REDUCED GATE TOP CD WITH WRAP-AROUND GATE CONTACT

A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

BACKGROUND

The present invention relates generally to semiconductor devices, and more specifically, to constructing reduced gate top critical dimensions (CDs) with a wrap-around gate contact.

The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node. With the increased demands for miniaturization, higher speed, greater bandwidth, lower power consumption, and lower latency, chip layout has become more complicated and difficult to achieve in the production of semiconductor dies.

SUMMARY

In accordance with an embodiment, a semiconductor structure is provided. The semiconductor structure includes a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof.

In accordance with another embodiment, a semiconductor structure is provided. The semiconductor structure includes a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a bi-layer configuration, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof.

In accordance with yet another embodiment, a method for forming a semiconductor structure is provided. The method includes constructing a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, forming first spacers on sidewalls of each FET device, forming second spacers over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and disposing a gate contact in direct contact with an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof.

DETAILED DESCRIPTION

Embodiments in accordance with the present invention provide methods and devices for constructing reduced gate top critical dimensions (CDs) with a wrap-around gate contact. The exemplary methods and structures are enabled by forming a reduced gate top CD by employing a local enlarged gate spacer and a reduced gate contact CD by employing inner spacers, as well as constructing a wrap-around gate contact for middle-of-line (MOL) scaling. The exemplary embodiments of the present invention achieve a similar MOL litho process window at a smaller contacted poly pitch (CPP) compared to existing technology with a larger gate pitch. The advantages of the exemplary embodiments of the present invention include at least not needing aggressive gate length (Lg) reduction, which compromises short channel effect (SCE), and not needing aggressive source/drain contact (CA) size reduction, which compromises ON-state resistance (Ron). Moreover, the exemplary structures only shrink the top gate CD and gate contact (CB) size, parameters which affect performance the least. However, the weakness of only shrinking the top gate CD and CB size can be mitigated by using a bi-layer top spacer followed by selectively removing the first layer after CB reactive ion etch (RIE) to recover the CB to gate contact dimension.

Examples of semiconductor materials that can be used in forming such structures include silicon (Si), germanium (Ge), silicon germanium alloys (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors and/or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. D-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements.

FIG.1is a cross-sectional view of a semiconductor structure including an NFET low voltage threshold (NLVT) device, an NFET regular voltage threshold (NRVT) device, a PFET regular voltage threshold (PRVT) device and a PFET low voltage threshold (PLVT) device, in accordance with an embodiment of the present invention.

In various example embodiments, a semiconductor structure5includes an NFET low voltage threshold (NLVT) device, an NFET regular voltage threshold (NRVT) device, a PFET regular voltage threshold (PRVT) device and a PFET low voltage threshold (PLVT) device. These devices are field effect transistor (FET) devices that are constructed over a substrate10defining fin channels12. The NLVT, NRVT, PRVT, and PLVT devices are separated from each other by an interlayer dielectric (ILD)16formed over source/drain (S/D) epi regions14. The S/D epi regions14extend into the substrate10. Spacers18are formed on opposed ends of the NLVT, NRVT, PRVT, and PLVT devices. Sidewalls of the spacers18directly contact sidewalls of the ILD16. Sidewalls of the spacers18further directly contact top sidewall sections of the S/D epi regions14. The spacers18can also be referred to as sidewall spacers.

The NLVT device includes a first work function metal (WFM) layer20, a second WFM layer22, and a third WFM layer24. The first WFM layer20is the outermost layer that directly contacts the sidewalls of the spacers18. It is noted that a thin high-k dielectric layer (not shown), such as HfO2, is also present between the outermost WFM layer (20,30,40,50) of the devices and the spacers18. The second WFM layer22rests within the first WFM layer20. The third WFM layer24rests within the second WFM layer22. A conductive material26is deposited within the third WFM layer24. The first, second, and third WFM layers20,22,24each define a substantially U-shaped configuration. Additionally, the first, second, and third WFM layers20,22,24collectively define a substantially U-shaped configuration. The conductive material26defines a substantially linear configuration. The third WFM layer24and the second WFM layer22have thicknesses that are greater than the thickness of the first WFM layer20.

The NRVT device includes a first WFM layer30, a second WFM layer32, and a third WFM layer34. The first WFM layer30is the outermost layer that directly contacts the sidewalls of the spacers18. It is noted that a thin high-k dielectric layer (not shown), such as HfO2, is also present between the outermost WFM layer (20,30,40,50) of the devices and the spacers18. The second WFM layer32rests within the first WFM layer30. The third WFM layer34rests within the second WFM layer32. The first and second WFM layers30,32each define a substantially U-shaped configuration. Additionally, the first and second WFM layers30,32collectively define a substantially U-shaped configuration. The third WFM layer34defines a substantially linear configuration. The second WFM layer32has a thickness that is greater than the thickness of the first WFM layer30. The third WFM layer34can have a thickness approximately equal to the thickness of the second WFM layer32.

The PRVT device includes a first WFM layer40, a second WFM layer42, and a third WFM layer44. The first WFM layer40is the outermost layer that directly contacts the sidewalls of the spacers18. It is noted that a thin high-k dielectric layer (not shown), such as HfO2, is also present between the outermost WFM layer (20,30,40,50) of the devices and the spacers18. The second WFM layer42rests within the first WFM layer40. The third WFM layer44rests within the second WFM layer42. The first and second WFM layers40,42each define a substantially U-shaped configuration. Additionally, the first and second WFM layers40,42collectively define a substantially U-shaped configuration. The third WFM layer44defines a substantially linear configuration.

It is noted that the third WFM layer34of the NRVT device has a thickness greater than the thickness of the third WFM layer44of the PRVT device. It is further noted that the first WFM layer30of the NRVT device has a thickness less than the thickness of the first WFM layer40of the of the PRVT device.

The PLVT device includes a first WFM layer50, a second WFM layer52, and a third WFM layer54. The first WFM layer50is the outermost layer that directly contacts the sidewalls of the spacers18. It is noted that a thin high-k dielectric layer (not shown), such as HfO2, is also present between the outermost WFM layer (20,30,40,50) of the devices and the spacers18. The second WFM layer52rests within the first WFM layer50. The third WFM layer54rests within the second WFM layer52. The first and second WFM layers50,52each define a substantially U-shaped configuration. Additionally, the first and second WFM layers50,52collectively define a substantially U-shaped configuration. The third WFM layer54defines a substantially linear configuration. The first WFM layer50has a thickness that is greater than the thickness of the second WFM layer52and the third WFM layer54.

It is noted that the third WFM layer44of the PRVT device has a thickness greater than the thickness of the third WFM layer54of the PLVT device. It is further noted that the first WFM layer50of the PLVT device has a greater thickness than the thickness of the first WFM layer40of the of the PRVT device.

Therefore, the thickness of the third WFM layer34of the NRVT device is greater than a thickness of the third WFM layer44of the PRVT device, which in turn has a thickness greater than the thickness of the third WFM layer54of the PLVT device. Similarly, the thickness of the first WFM layer50of the PLVT device is greater than a thickness of the first WFM layer40of the PRVT device, which in turn has a thickness greater than the thickness of the first WFM layer30of the NRVT device. The advantage of this configuration is that there is no need for WFM chamfering, which is a challenging process for devices with short Lg at CPP of less than 45 nm. This configuration creates four devices each with a different gate threshold voltage.

The first WFM layer20of the NLVT device, the first WFM layer30of the NRVT device, the first WFM layer40of the PRVT device and the first WFM layer50of the PLVT device can be, e.g., titanium nitride (TiN) layers. The second WFM layer22of the NLVT device, the second WFM layer32of the NRVT device, the second WFM layer42of the PRVT device and the second WFM layer52of the PLVT device can be, e.g., titanium carbide (TiC, or TiAlC) layers. The third WFM layer24of the NLVT device, the third WFM layer34of the NRVT device, the third WFM layer44of the PRVT device and the third WFM layer54of the PLVT device can be, e.g., TiN layers. The conductive material26can be, e.g., tungsten (W). It is noted that four types of devices (NLVT, NRVT, PRVT, PLVT) are listed, and this is only for illustration purposes, and the invention process and structures also work for more types of transistors with different threshold voltages.

The top view7illustrates the fins in relation to the gates and the CA, CB, and VA contacts.

In one or more embodiments, the substrate10can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate10can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate10can be essentially (e.g., except for contaminants) a single element (e.g., silicon), primarily (e.g., with doping) of a single element, for example, silicon (Si) or germanium (Ge), or the substrate10can include a compound, for example, Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate10can also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI). The substrate10can also have other layers forming the substrate10, including high-k oxides and/or nitrides. In one or more embodiments, the substrate10can be a silicon wafer. In an embodiment, the substrate10is a single crystal silicon wafer.

The ILD16can be any suitable material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the ILD16can be utilized. The ILD16can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

The S/D epi regions14can be of the same or different materials for pFET and nFET devices, and can be either in-situ doped with appropriate polarity dopants (B for pFET and P for nFET devices) or doped by ion implantation.

The terms “epitaxial growth” and “epitaxial deposition” refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has substantially the same crystalline characteristics as the semiconductor material of the deposition surface. The term “epitaxial material” denotes a material that is formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters set correctly, the depositing atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystal surface will take on a 1001 orientation.

The spacers18can include any of one or more of SiN, SiBN, SiCN and/or SiBCN films.

The WFMs20,22,24,30,32,34,40,42,44,50,52,54can be metals, such as, e.g., TiN, TiC, TiAl, TiAlC, TaN, or any combination thereof. The metal can be deposited by a suitable deposition process, for example, ALD, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal or e-beam evaporation, or sputtering. In various exemplary embodiments, the height of the WFMs20,22,24,30,32,34,40,42,44,50,52,54can be reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing.

FIG.2is a cross-sectional view of the semiconductor structure ofFIG.1where the spacers adjacent the NLVT, NRVT, PRVT, and PLVT devices are selectively recessed, in accordance with an embodiment of the present invention.

In various example embodiments, the spacers18adjacent the NLVT, NRVT, PRVT, and PLVT devices are selectively recessed to create openings60at top portions of the NLVT, NRVT, PRVT, and PLVT devices. The recessing exposes the sidewalls of the first WFM layer20of the NLVT device, the sidewalls of the first WFM layer30of the NRVT device, the sidewalls of the first WFM layer40of the PRVT device, and the sidewalls of the first WFM layer50of the PLVT device.

The etching can include a dry etching process such as, for example, wet etch, reactive ion etching, plasma etching, ion etching or laser ablation. The etching can further include a wet chemical etching process in which one or more chemical etchants are used to remove portions of the blanket layers that are not protected by the patterned photoresist.

The dry and wet etching processes can have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes can include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses can include Tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and helium (He), and Chlorine trifluoride (ClF3). Dry etching can also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Chemical vapor etching can be used as a selective etching method, and the etching gas can include hydrogen chloride (HCl), Tetrafluoromethane (CF4), and gas mixture with hydrogen (H2). Chemical vapor etching can be performed by CVD with suitable pressure and temperature.

FIG.3is a cross-sectional view of the semiconductor structure ofFIG.2where an isotropic etch is performed to selectively remove portions of work function metals (WFMs), in accordance with an embodiment of the present invention.

In various example embodiments, an isotropic etch is performed to selectively remove portions of WFMs of the NLVT, NRVT, PRVT, and PLVT devices to create wider openings62. The isotropic etch can shrink the gate top critical dimension (CD) uniformly despite the composition of the WFMs for different devices with different gate threshold voltages. This can be achieved by tuning the etch process such that the etch rates of various WFM layers are similar. For example, if the WFM layers include TiN and TiAlC, a citric-peroxide wet etch chemistry can be used at a proper mix ratio and temperature to achieve a 1:1 etch rate ratio between the TiN and the TiAlC.

In the NLVT device, the isotropic etch results in the first WFM layer20and the second WFM layer22being removed from the openings62. The third WFM layer24is recessed to a recessed third WFM layer24′. The conductive material26remains intact.

In the NRVT device, the isotropic etch results in the first WFM layer30being removed from the openings62. The second WFM layer32is recessed to a thin recessed second WFM layer32′. The third WFM layer34remains the same.

In the PRVT device, the isotropic etch results in the first WFM layer40being removed from the openings62. The second WFM layer42is slightly recessed to a recessed second WFM layer42′. The third WFM layer44remains the same.

In the PLVT device, the isotropic etch results in the first WFM layer50being recessed to a thin recessed first WFM layer50′. The second and third WFM layers52,54remain the same.

Therefore, the second WFM layer52of the PLVT device has a thickness greater than the thickness of the recessed second WFM layer42′ of the PRVT device, which in turn has a thickness greater than a thickness of the thin recessed second WFM layer32′ of the NRVT device.

FIG.4is a cross-sectional view of the semiconductor structure ofFIG.3where a dielectric is deposited in areas created by the isotropic etch and a first interlayer dielectric (ILD) is deposited over the structure, in accordance with an embodiment of the present invention.

In various example embodiments, a dielectric64is deposited in areas created by the isotropic etch and a first interlayer dielectric (ILD)66is deposited over the structure. The dielectric64can be planarized before deposition of the first ILD66. The dielectric64can also be referred to as a top spacer.

Regarding various dielectrics or dielectric layers (such as the dielectric64) discussed herein, the dielectrics can include, but are not limited to, SiN, SiOCN, SiOC, SiC, SiON, SiBCN, SO2, or ultra-low-k (ULK) materials, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, carbon-doped silicon oxide (SiCOH) and porous variants thereof, silsesquioxanes, siloxanes, or other dielectric materials having, for example, a dielectric constant in the range of about 2 to about 10.

In some embodiments, the dielectrics can be conformally deposited using atomic layer deposition (ALD) or, chemical vapor deposition (CVD). Variations of CVD processes suitable for forming the dielectrics include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof can also be employed.

The first ILD66includes a different material than the dielectric64.

The first ILD66can be any suitable material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the first ILD66can be utilized. The first ILD66can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

FIG.5is a cross-sectional view of the semiconductor structure ofFIG.4where source/drain (S/D) contacts are formed, in accordance with an embodiment of the present invention.

In various example embodiments, source/drain (S/D) contacts70are formed to the top surface of the S/D epi regions14. The S/D contacts70can also be referred to as CA contacts. The S/D contacts70are formed between the NLVT, NRVT, PRVT, and PLVT devices. The sidewalls of the S/D contacts70do not directly contact the sidewalls of the spacers18. The remaining first ILD66is designated as first ILD portions66′.

Non-limiting examples of suitable conductive materials for the S/D contacts70include a silicide liner such as Ti, Ni, NiPt, etc., an adhesion metal liner, such as TiN, TaN, and conductive metal fill, such as Al, W, Co, Ru, etc. The conductive material can further include dopants that are incorporated during or after deposition. The conductive metal can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.

FIG.6is a cross-sectional view of the semiconductor structure ofFIG.5where an etch stop layer is deposited and a second ILD is formed over the etch stop layer, in accordance with an embodiment of the present invention.

In various example embodiments, an etch stop layer72is deposited and a second ILD74is formed over the etch stop layer72.

The dielectric of the etch stop layer72can include, but is not limited to, SiN, SiOCN, SiOC, SiBCN, SO2, or ultra-low-k (ULK) materials, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, carbon-doped silicon oxide (SiCOH) and porous variants thereof, silsesquioxanes, siloxanes, or other dielectric materials having, for example, a dielectric constant in the range of about 2 to about 10.

In some embodiments, the dielectric of the etch stop layer72can be conformally deposited using atomic layer deposition (ALD) or, chemical vapor deposition (CVD). Variations of CVD processes suitable for forming the etch stop layer72include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof can also be employed.

FIG.7is a cross-sectional view of the semiconductor structure ofFIG.6where the second ILD is selectively etched to create an opening over a gate region and inner spacers are formed within the opening, in accordance with an embodiment of the present invention.

In various example embodiments, the second ILD74is selectively etched to create an opening78over the NRVT device. The opening78terminates at the top surface of the etch stop layer72. Inner spacers76are formed within the opening78. The inner spacers76accommodate the CPP shrink and gate top CD reduction. The inner spacers76are vertically aligned with the dielectric64of the NRVT device. The inner spacers76are also vertically aligned with the spacers18of the NRVT device.

The inner spacers76can include any of one or more of SiN, SiBN, SiCN and/or SiBCN films.

FIG.8is a cross-sectional view of the semiconductor structure ofFIG.7where the etch stop layer and the first ILD are etched to create an opening to a gate, in accordance with an embodiment of the present invention.

In various example embodiments, the etch stop layer72and the first ILD portion66′ of the NRVT device are etched to create an opening80to a top surface35of the NRVT device. The thin recessed second WFM layer32′ and the third WFM layer34are exposed.

FIG.9is a cross-sectional view of the semiconductor structure ofFIG.8where metallization takes place to form a CB contact and a VA contact, in accordance with an embodiment of the present invention.

In various example embodiments, metallization takes place to form a CB contact82and a VA contact84. The CB contact82can also be referred to as a gate contact. The final semiconductor structure85illustrates the CB contact82directly contacting the top surfaces of the thin recessed second WFM layer32′ and the third WFM layer34. The CB contact82also directly contacts top surfaces of the dielectric64of the NRVT device. The dielectric64can also be referred to as a top spacer. The CB contact82directly contacts sidewalls of the inner spacers76. The VA contact84directly contacts the top surface of the S/D contact70in the PLVT device. The CB contact82is vertically offset from the S/D epi regions14, whereas the VA contact84is vertically aligned with the S/D epi region14. Each of the NLVT, NRVT, PRVT, and PLVT devices has a different threshold voltage.

The final semiconductor structure85thus includes a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers (the spacers18) disposed on sidewalls of each FET device, second spacers (or top spacers or the dielectric64) disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and the gate contact or the CB contact82directly contacting an FET device of the plurality of FET devices, where only an upper portion of the CB contact82directly contacts third spacers (the inner spacers76) on opposed ends thereof.

The FET device directly contacting the CB contact82includes a first work function metal (WFM) layer30, a second WFM layer32, and a third WFM layer34. The first WFM layer30directly contacts sidewalls of the first spacers (the spacers18) and the second WFM layer32directly contacts sidewalls of the second spacers (top spacers or the dielectric64). The third WFM layer34rests within the second WFM layer32. The third WFM layer34directly contacts a bottom surface of the CB contact82. The third spacers (the inner spacers76) are vertically aligned with the first spacers and the second spacers. Moreover, the second spacers directly contact an upper portion of the FET device directly contacting the CB contact82.

Non-limiting examples of suitable conductive materials for the CB contact82and the VA contact84include a silicide liner such as Ti, Ni, NiPt, etc., an adhesion metal liner, such as TiN, TaN, and conductive metal fill, such as Al, W, Co, Ru, etc. The conductive material can further include dopants that are incorporated during or after deposition. The conductive metal can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.

FIG.10is a cross-sectional view of the semiconductor structure ofFIG.3where a bi-layer dielectric is deposited in areas created by the isotropic etch, in accordance with another embodiment of the present invention.

In various example embodiments, a bi-layer dielectric is deposited in areas created by the isotropic etch ofFIG.3. The bi-layer dielectric includes a first dielectric layer90and a second dielectric layer92. The first dielectric layer90rests within the second dielectric layer92. The second dielectric layer92has a substantially U-shaped configuration. The first and second dielectric layers90,92can be planarized. In one example, the first dielectric layer90can be SiC and the second dielectric layer92can be SiN, or vice versa.

FIG.11is a cross-sectional view of the semiconductor structure ofFIG.10where S/D contacts are formed, a first ILD, an etch stop layer, and a second ILD are deposited, and an opening is created to a top surface of a device, in accordance with an embodiment of the present invention.

In various example embodiments, the S/D contacts70are formed, the first ILD66with the first ILD portions66′, the etch stop layer72, and the second ILD74are deposited, and an opening94is created to a top surface35of the NRVT device to expose the thin recessed second WFM layer32′ and the third WFM layer34. A top surface of the second dielectric layer92is also exposed. Stated differently, the sections of the second dielectric layer92that directly contact the sidewalls of the thin recessed second WFM layer32′ are exposed.

FIG.12is a cross-sectional view of the semiconductor structure ofFIG.11where portions of the bi-layer dielectric are selectively etched, in accordance with an embodiment of the present invention.

In various example embodiments, portions of the bi-layer dielectric are selectively etched. In particular, the sections of the second dielectric layer92that directly contact the sidewalls of the thin recessed second WFM layer32′ are removed to create openings96. The openings96extend to a top surface of the first WFM layer30of the NRVT device. The openings96can be referred to as extensions or projections along the top area or top section of the NRVT device.

FIG.13is a cross-sectional view of the semiconductor structure ofFIG.12where metallization takes place to form a CB contact and a VA contact, in accordance with an embodiment of the present invention.

In various example embodiments, where metallization takes place to form a CB contact98and a VA contact99. The final semiconductor structure100illustrates the CB contact98directly contacting the top surfaces of the thin recessed second WFM layer32′ and the third WFM layer34. The CB contact98also directly contacts sidewalls of the first dielectric material90and the second dielectric material92. The CB contact98also directly contacts sidewalls of the thin recessed second WFM layer32′. In contrast to the CB contact82ofFIG.9, the CB contact98of the structure100extends further down into the WFM layers of the NRVT device. The CB contact98encapsulates or surrounds or wraps around top areas of the WFM layers of the NRVT device. The CB contact98thus includes extension regions or projections that wrap around the top portion of the NRVT device.

The bi-layer dielectric including the first and second dielectric layers90,92can also be referred to as a top spacer. The CB contact98directly contacts sidewalls of the inner spacers76. The VA contact99directly contacts the top surface of the S/D contact70in the PLVT device. The CB contact98is vertically offset from the S/D epi regions14, whereas the VA contact99is vertically aligned with the S/D epi region14. Each of the NLVT, NRVT, PRVT, and PLVT devices has a different gate threshold voltage.

The final semiconductor structure100includes a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers (the spacers18) disposed on sidewalls of each FET device, second spacers (top spacers or the dielectric64) disposed over and in direct contact with the first spacers, the second spacers having a bi-layer configuration (the first dielectric layer90and the second dielectric layer92), and the gate contact or CB contact98directly contacting an FET device of the plurality of FET devices, where only an upper portion of the CB contact98directly contacts third spacers (the inner spacers76) on opposed ends thereof.

The second spacers have a width greater than a width of the first spacers. The CB contact98wraps around a top portion of the FET device directly contacting the CB contact. The FET device directly contacting the CB contact98includes a first work function metal (WFM) layer30, a second WFM layer32, and a third WFM layer34. The first WFM layer30directly contacts sidewalls of the first spacers. The gate contact98directly contacts sidewalls of the second WFM layer32. The third WFM layer34rests within the second WFM layer32and the third WFM layer34directly contacts a bottom surface of the CB contact98. The second spacers have the bi-layer configuration directly contacting the sidewalls of the CB contact98. A bottommost surface of the CB contact98directly contacts top surfaces of both the first and second WFM layers30,32.

Thus, with respect toFIGS.9and13, a semiconductor structure or a contact structure is presented including a gate with a reduced dimension on a top portion thereof, and a top spacer with a larger width over the sidewall spacer. In one example, as inFIG.13, the top spacer can have a bi-layer configuration where the inner spacer is composed of a different material than the material of the outer spacer. Moreover, the contact structure can include a gate contact with an inner dielectric spacer on top, and no inner spacers at the bottom, the gate contact landing over the gate with a reduced dimension on top, with a wrap-around configuration. The method of constructing the contact structure includes the steps of forming a divot or opening next to the WFM by recessing the sidewall spacer, enlarging the divot by isotropically trimming the WFM, filling the divot or opening with a bi-layer dielectric where the first layer can be selectively etched to the second layer, depositing a first MOL ILD and forming a S/D contact, depositing an etch stop layer and a second MOL ILD, forming a two-stage gate contact which has inner spacers in the second MOL ILD and no-inner spacers in the first MOL ILD, further etching away the first layer dielectric in the divot or opening under the gate contact, and performing gate metallization.

In conclusion, the exemplary embodiments of the present invention introduce reduced gate top CDs with a wrap-around gate contact. The exemplary methods and structure are enabled by forming a reduced gate top CD by employing a local enlarged gate spacer and a reduced gate contact CD by employing inner spacers, as well as constructing a wrap-around gate contact for MOL scaling. The exemplary embodiments of the present invention achieve a similar MOL litho process window at 45 CPP compared to existing technology at 51 CPP. The exemplary embodiments can even make 42 CPP possible. The advantages of the exemplary embodiments of the present invention include at least not needing aggressive Lg reduction, which compromises SCE, and not needing aggressive CA size reduction, which compromises Ron. Moreover, the exemplary structures only shrink the top gate CD and CB size, parameters which affect performance the least. However, the weakness of only shrinking the top gate CD and CB size can be mitigated by using a bi-layer top spacer followed by selectively removing the first layer after CB RIE to recover the CB to gate contact dimension.

RegardingFIGS.1-13, deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. As used herein, “depositing” can include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, stripping, implanting, doping, stressing, layering, and/or removal of the material or photoresist as needed in forming a described structure.

Removal is any process that removes material from the wafer: examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), etc.

Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed. Patterning also includes electron-beam lithography.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps/blocks can be varied within the scope of the present invention.