Apparatus for receiving digital data

An apparatus for receiving digital data includes a memory unit for temporarily storing therein a plurality of data streams, each of which includes data and clock obtained by demodulating plural redundant signals received in each receiver in response to a signal generated based on each clock; a writing control unit for controlling a writing of the plurality of the data streams into the memory unit; a data reading control unit for reading the data streams stored temporarily in the memory unit in a synchronized manner; and a selection unit for selecting one of the read data streams to output the selected data stream. The writing control unit detects a synchronization packet included in the plurality of data streams to control the writing of the plurality of data streams into the memory unit based on the synchronization packet.

FIELD OF THE INVENTION

The present invention relates to an STL (studio transmitter link) receiving apparatus for receiving digital broadcasting signals transmitted from a broadcasting station or studio to a transmitting station; and, more particularly, a digital data switching technology for receiving plural redundant digital broadcasting signals received through plural paths to select one of the plural digital broadcasting signals.

BACKGROUND OF THE INVENTION

As for an STL receiving apparatus for receiving digital broadcasting signals transmitted from a broadcasting station or studio to a transmitting station, there is known a digital data receiving apparatus for receiving plural redundant broadcasting signals through plural receivers which includes a switching unit for selecting one of the plural digital broadcasting signals.

FIG. 4shows a block diagram illustrating an apparatus for receiving digital data disclosed in the patent application filed by the inventors prior to this patent application. Referring toFIG. 4, an STL receiving apparatus100selects TS (transport stream) data and a TS clock based on digital broadcasting signals received through an antenna10to send the selected TS data and TS clock to a first and a second broadcaster50A and50B. Further, the STL receiving apparatus100includes a first receiver20A and a second receiver20B, a switching control device40and a switching unit300.

In the STL receiving apparatus100, the digital broadcasting signals received through the antenna10are inputted to the first receiver20A and the second receiver20B. The inputted digital broadcasting signals are transformed into IF (intermediate frequency) signals by down converters21A and21B and then demodulated by demodulators22A and22B, which are installed in the receivers20A and20B, respectively. Dividers23A and23B divide the demodulated digital data obtained by the demodulators22A and22B into TS (transport stream) data and TS clocks.

A first TS clock30-1and a first TS data30-2outputted from the first receiver20A are inputted to a first synchronizing controller33A, which detects a synchronous code included in the first TS data30-2. A first write reset signal CTL for a first memory34A is generated based on the synchronous code. The first TS data30-2is written into the first memory34A in response to the first TS clock30-1and the first write reset signal CTL generated by the first synchronizing controller33A.

Likewise, a second TS data30-4is written into a second memory34B in response to a second TS clock30-3and a second write reset signal CTL generated by the second synchronizing controller33B based on the second TS data30-4.

A clock control device35receives the first and the second TS clock30-1and30-3and outputs a post-switching clock30-5pursuant to a switching control signal30-7outputted by a switching control device40. A data control device37receives the post-switching clock30-5from the clock control device35as well as, for example, the first TS data30-2from the first synchronizing controller33A and the second TS data30-4from the second synchronizing controller33B to output a read reset signal30-19to the memories34A and34B. The read reset signal30-19is outputted from the data control device37, for example, after a time period MAXW from a rising edge of the first write reset signal CTL and a time period MINX from a rising edge of the second write reset signal CTL, as shown inFIG. 5. The data control device37also outputs a selection signal to a selector31. The selector31selects one of the two TS read datas (TS read data30-17and TS read data30-18) in response to the selection signal outputted from the data control device37and outputs a post-switching data30-6. If, for example, the first TS read data30-17is corrupted but the second TS read data30-18is not, the second TS read data is selected and outputted as the post-switching data30-6.

The post-switching clock30-5is inputted to the first and the second memory34A and34B and used for reading data from the memories. The post-switching clock30-5is also inputted to the data control device37for generating the read reset signal30-19to the first memory34A and the second memory34B.

As a result, the first memory34A and the second memory34B are controlled by the same clock, i.e., the post-switching clock30-5, and the same control signal, i.e., the read reset signal30-19, when reading the memories34A and34B. Therefore, the first TS read data30-17outputted from the memory34A and the second TS read data30-18outputted from the memory34B are synchronous.

Hereinafter, waveforms of the signals generated in the apparatus100will be described with reference toFIG. 5. As shown inFIG. 5, the first TS read data30-17and the second TS read data30-18are read out at the same time because the memories34A and34B are read in response to the same read reset signal. Therefore, the first and the second data can be seamlessly switched into the post-switching data30-6by the selector31, as illustrated inFIG. 5. In the case shown inFIG. 5, for example, signals1-(0),1-(1),2-(2),2-(3) and1-(4) are outputted sequentially.

As described above, by using the apparatus for receiving digital data shown inFIG. 4, a plurality of data streams (data, clocks) obtained by demodulating plural redundant signals received in plural receivers can be switched so that a certain data stream can be switched into another data stream without causing an interruption of clocks or data.

However, the apparatus ofFIG. 4has such a drawback as explained hereinafter. Referring toFIG. 4, the first TS clock30-1and the first TS data30-2outputted from the first receiver20A are inputted to the first synchronizing controller33A. The synchronizing controller33A detects a synchronization byte (47h) included in the first TS data30-2to generate the first write reset signal CTL for the first memory34A. Using a synchronization byte (47h) in each TS data packet, a time delay between the first and the second data should not be greater than 1 TS (204 W) in order to properly handle the time delay, wherein 1 TS is 50 μs at a bit rate of 32.508 Mbps.

FIG. 4illustrates a case where the signals received by the antenna10are distributed through plural paths, a plurality of data streams are obtained by demodulating the received signals and a data stream selected from the plurality of data streams is outputted. In this case, a time delay between the receivers20A and20B is so small (1 to 10 μs) that it is possible to avoid problems due to the time delay.

However, e.g., in case where the receiver20A serves as a microwave transmission path and the receiver20B serves as an optical transmission path, a time delay greater than 1 TS may occur since each signal is received through a different path.

In other words, when transmitting signals from a broadcasting studio or station to a repeater station, i.e., an STL receiving apparatus, signals sent through the microwave transmission path are transmitted directly to the receiver20A whereas signals sent through the optical transmission path goes through a longer path because an optical fiber constituting the optical transmission path is installed underground. As a result, a time delay between the corresponding transmission paths becomes greater than 1 TS, making it difficult to perform a seamless data switching.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide an apparatus for receiving digital data that can perform a seamless switching even when there occurs a time delay greater than or equal to 1 TS among a plurality of data streams obtained by demodulating plural redundant signals received in plural receivers.

In accordance with the present invention, there is provided an apparatus for receiving digital data, including: a memory unit for temporarily storing therein a plurality of data streams, each of which includes data and clock information, obtained by demodulating plural redundant signals received in each receiver in response to a signal generated based on the each clock; a writing control unit for controlling a writing of the plurality of the data streams into the memory unit; a data reading control unit for reading the data streams stored temporarily in the memory unit in a synchronized manner; and a selection unit for selecting one of the read data streams to output the selected data stream, wherein the writing control unit detects a synchronization packet included in the plurality of data streams to control the writing of the plurality of data streams into the memory unit based on the synchronization packet, wherein the synchronization packet is included in the data streams at a rate of a single packet per frame.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1shows a block diagram illustrating an apparatus for receiving digital data in accordance with a preferred embodiment of the present invention. In the apparatus for receiving digital data shown inFIG. 1, digital broadcasting signals received through an antenna10are demodulated by a receiver20A, and those received through an optical transmission path11are demodulated by a receiver20B. The apparatus ofFIG. 1has the same configuration as that shown inFIG. 4, except that synchronizing controllers39A and39B are provided in place of the synchronizing controllers33A and33B. The synchronizing controllers39A and39B detect IIP packets included in data streams and perform controls (write resets) on memories34A and34B to write a plurality of data streams into the memories34A and34B based on the detected IIP packets, whereas the synchronizing controllers33A and33B detect a synchronous byte (47h) included in TS data and perform controls (write resets) on the memories34A and34B.

Hereinafter, the synchronizing controllers39A and39B will be explained in detail with reference toFIG. 2.FIG. 2illustrates an enlarged view of a section including a synchronizing controllers39A and39B shown inFIG. 1in accordance with the present invention.

Referring toFIG. 2, a first TS clock30-1and a first TS data30-2are inputted to the first synchronizing controller39A, which detects an IIP packet included in the first TS data30-2. A first control (write reset) signal CTL for a first memory34A is generated based on the detected IIP packet. The first TS data30-2is written into the first memory34A in response to the first TS clock30-1and the first control (write reset) signal CTL generated by the first synchronizing controller39A.

Likewise, a second TS data30-4is written into the second memory34B in response to a second TS clock30-3and a second control signal CTL generated by the second synchronizing controller39B based on the second TS data30-4.

A clock control device35receives the first TS clock30-1and the second TS clock30-2and outputs a post-switching clock30-5pursuant to a switching control signal30-7outputted by a switching control device40. A data control device37receives the post-switching clock30-5from the clock control device35as well as, for example, the first TS data30-2from the first synchronizing controller39A and the second TS data30-4from the second synchronizing controller39B to output a read reset signal30-19to the memories34A and34B. The read reset signal30-19is outputted from the data control device37, for example, after a time period corresponding to 1 TS from the end of a TS packet including the most lately detected IIP packet, i.e., the TS packet of 2-(M) in the second TS data30-4as shown inFIG. 3, on condition that the IIP packets are detected from both of the TS data30-2and30-4. The data control device37also outputs a selection signal to a selector31. The selector31selects one of the two TS read datas (the TS read data30-17and the TS read data30-18) in response to the selection signal from the data control device37and outputs a post-switching data30-6. If, for example, the first TS read data30-17is corrupted but the second TS read data30-18is not, the second TS read data is selected and outputted as the post-switching data30-6.

Hereinafter, waveforms of the signals will be described with reference toFIG. 3. As shown inFIG. 3, the first read data30-17and the second read data30-18are read out at the same time because the memory34A and34B are subject to a read operation in response to the same read reset signal.

In accordance with the present embodiment, as can be seen inFIG. 3, a data switching can be performed by minimizing the effect of a time delay Δt between the first TS data30-2and the second TS data30-4even when the time delay Δt is greater than or equal to 1 TS, because a memory is controlled based on an identical IIP packet throughout multiple frames.

In the following, there will be given an explanation on a configuration of an IIP packet included in a TS packet and a detection thereof with reference toFIGS. 6 and 7.FIG. 6shows a configuration of a TS packet of 1 TS (204 bytes). The 1STbyte is a synchronization byte and the bytes from 189thto 196thprovide information on a transmission control. There is provided an area for representing an IIP packet in the 190thbyte. Specifically, the bits from the 7thto the 4thof the 190thbyte are ‘1000’. A time delay not greater than 1 frame (about 230 ms) can be properly handled by detecting the IIP packet, because the IIP packet is inserted only once in every single frame (about 230 ms).

FIG. 7illustrates a block diagram showing the synchronizing controllers39A and39B for detecting an IIP packet shown inFIGS. 1 and 2. A47hdetector70receives TS data and detects ‘47h’ therefrom to send a detection signal to a delay unit71. The delay unit71holds the detection signal for a time period corresponding to 189 bytes and then outputs the delayed detection signal to an input EN of a FF (flip-flop)72, so that the 190thbyte of the TS packet effectively enters the FF72. Then, a comparator74checks whether an output signal of the FF72is ‘8Xh’ by using an output of an 8Xh generator73, wherein X represents an arbitrary hexadecimal number. That is, the 190thbyte is identified as an IIP packet when the output signal of the flip-flop72is equal to ‘8Xh’. In case the comparator74detects the IIP packet, a control signal generator75generates the first or second write reset signal CTL to be sent to the memories34A or34B. The write reset signal CTL is outputted, for example, in synchronization with the beginning of a TS packet immediately following the TS packet including the detected IIP Packet, as shown inFIG. 3. Meanwhile, for example, the first or second TS data30-2or30-4is sent to the data control device37from the synchronizing controller39A or39B.

As described above, in accordance with the present embodiment, there is provided an apparatus for receiving digital data that can perform a seamless data switching even when there occurs a time delay greater than or equal to 1 TS among a plurality of data streams (data, clocks) obtained by demodulating plural redundant signals received in plural receivers.

Furthermore, although an IIP packet is used as a synchronizing word in the present embodiment, it is not limited thereto. By employing any single packet per frame, e.g., a frame header flag, there may be implemented an apparatus for receiving digital data that can perform a seamless data switching even when a time delay among a plurality of data streams is greater than or equal to 1 TS.