Integrated Circuitry, Memory Circuitry Comprising Strings Of Memory Cells, And Methods Used In Forming Integrated Circuitry

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. The scribe-line area comprises a horizontal area in which a registration mark or an alignment mark is being fabricated. Horizontally-spaced features of the registration mark or of the alignment mark are simultaneously formed in the first tiers and the second tiers in the horizontal area and in the individual die areas. The horizontally-spaced features in the horizontal area are grouped in sections that are horizontally-separated by gaps in at least one vertical cross-section where there are less, if any, such horizontally-spaced features than are in the sections. Horizontally-spaced vertical slots are formed through uppermost of the first and second tiers of the stack in the horizontal area of the registration mark or of the alignment mark. Through the horizontally-spaced vertical slots, the sacrificial material is replaced with metal material. After the replacing, the first and second tiers in the scribe-line areas are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure, are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to integrated circuitry, to memory circuitry comprising strings of memory cells, and to methods used in forming integrated circuitry.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate.

NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor.

Memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory blocks may at least in part define longitudinal outlines of individual wordlines in individual wordline tiers of vertically-stacked memory cells. Connections to these wordlines may occur in a so-called “stair-step structure” at an end or edge of an array of the vertically-stacked memory cells. The stair-step structure includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of the individual wordlines upon which elevationally-extending conductive vias contact to provide electrical access to the wordlines.

Integrated circuitry such as memory circuitry described above is commonly manufactured in a sequence of patterning steps of one or more layers formed over a substrate such as a semiconductor wafer. Thereby, electronic components of the circuitry (e.g., transistors, capacitors, conductive vias, etc.) made of various materials are deposited onto the substrate in layers and patterned individually or multiple layers at a time. The separate patterning steps need to be aligned correctly relative one another, for example using a process commonly referred to as lithography. The semiconductor wafer is typically fabricated to have a plurality of individual die areas that are separated by scribe-line area. Each die area is fabricated to ultimately contain a complete integrated circuit that at the conclusion of processing is isolated by cutting through the scribe-line area to form individual integrated circuit chips (die) from the former interconnected individual die areas.

In patterning within the individual die areas, using lithography for example, a masking tool (e.g., a reticle) and the semiconductor wafer must be precisely x-y aligned relative one another. Patterns are typically formed in the scribe-line area which are examined by the lithography equipment for achieving proper x-y alignment and for determining whether acceptable x-y alignment was achieved. One of such patterns is commonly known as an alignment mark. Multiple of these would typically be placed within the scribe-line area and individually include a plurality of features for which the lithography equipment can optically scan to determine and modify x-y alignment of the wafer and masking tool prior to patterning. Another of such patterns is commonly known as a registration mark. Multiple of these would also typically be formed in the scribe-line area, with the lithography equipment being used to optically scan the registration marks to determine whether proper x-y alignment was achieved after the patterning.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass methods of forming integrated circuitry and integrated circuitry regardless of method of manufacture. One example form of such integrated circuitry is memory, although not all aspects of the inventions disclosed herein are so limited. Example methods of forming integrated circuitry are described with reference toFIGS.1-41.

Referring toFIG.1, such shows a portion of a construction10(e.g., a portion of a semiconductor wafer) comprising individual die areas100having scribe-line area200there-between. A registration mark or an alignment mark will be fabricated in scribe-line area200, with likely multiple such registration marks and/or alignment marks being fabricated. Multiple such marks may be fabricated that may be of the same or different configuration(s) relative one another, with the discussion largely proceeding with respect to fabrication of a single registration mark or a single alignment mark.

Referring toFIGS.2-6, such are enlarged views of a portion ofFIG.1showing a die area100and an immediately-adjacent scribe-line area200. In the example embodiment, memory circuitry comprising strings of memory cells are being fabricated. Embodiments of the invention encompass so-called “gate-last” or “replacement-gate” processing, so-called “gate-first” processing, and other processing whether existing or future-developed independent of when transistor gates are formed. Embodiments of the invention also encompass integrated circuitry such as that comprising a memory array comprising strings of memory cells (e.g., NAND architecture) independent of method of manufacture. Construction10comprises a base substrate11(e.g., part of a semiconductor wafer) that may comprise any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Materials may be aside, elevationally inward, or elevationally outward of theFIGS.3-6-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within an array (e.g., a memory array) may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

Example construction10comprises a conductor tier16comprising conductor material17(e.g., WSixunder conductively-doped polysilicon) above substrate11. Conductor tier16may comprise part of control circuitry (e.g., peripheral-under-array circuitry and/or a common source line or plate) used to control read and write access to the transistors and/or memory cells in an array12. In an embodiment where the integrated circuitry being fabricated will comprise memory circuitry, example array12is a memory-array region12within individual die areas100. Such may be juxtaposed relative to the edge(s) of individual die areas100(not shown) or be laterally-spaced therefrom (as shown), for example a space88being between array region12and an edge87of die area100.

A stack18comprising vertically-alternating first tiers22and second tiers20is directly above conductor tier16, with first tiers22comprising sacrificial material26(e.g., silicon nitride) and second tiers20comprising non-sacrificial material24that is of different composition from that of sacrificial material26(e.g., silicon dioxide). In some embodiments, first tiers22may be referred to as conductive tiers22and second tiers20may be referred to as insulative tiers20, with first tiers22being conductive and second tiers20being insulative at least in a finished-circuitry construction in some embodiments. Example thickness for each of tiers20and22is 20 to 60 nanometers. The example uppermost tier20may be thicker/thickest compared to one or more other tiers20and/or22. Only a small number of tiers20and22is shown, with more likely stack18comprising dozens, a hundred or more, etc. of tiers20and22. Other circuitry that may or may not be part of peripheral and/or control circuitry may be between conductor tier16and stack18. For example, multiple vertically-alternating tiers of conductive material and insulative material of such circuitry may be below a lowest of the first tiers22and/or above an uppermost of the first tiers22. For example, one or more select gate tiers (not shown) may be between conductor tier16and the lowest first tier22and one or more select gate tiers may be above an uppermost of first tiers22(not shown). Alternately or additionally, at least one of the depicted uppermost and lowest first tiers22may be a select gate tier.

Stack18extends from individual die areas100to and across scribe-line area200that is between immediately-adjacent individual die areas100. The example-depicted scribe-line area200comprises a horizontal area14in which a registration mark or an alignment mark is being fabricated. Multiple such registration and/or alignment marks would likely be formed, with the discussion largely proceeding with respect to a single registration or alignment mark. In one embodiment and as shown, horizontal area14comprises horizontally-spaced horizontal regions15of the mark being fabricated and horizontal space19between immediately-adjacent horizontal regions15(e.g., “among” when more than two regions15).

Referring toFIGS.7-16, horizontally-spaced features75of the registration mark or of the alignment mark being fabricated have simultaneously been formed in first tiers22and second tiers20in horizontal area14and in individual die areas100(e.g., in array12). For convenience and clarity in the figures, horizontal-scale has been reducedFIGS.8and9compared toFIGS.3-6while vertical-scale has not been reduced. Horizontally-spaced features75in horizontal area14are grouped in sections76that are horizontally-separated by gaps77in at least one vertical cross-section (e.g., that ofFIG.9) where there are less, if any, such horizontally-spaced features than there are in sections76.FIGS.7and9show an example wherein no horizontally-spaced features75have been formed in gaps77. In the depicted example embodiment, sections76and gaps77have been formed in individual horizontal regions15, with the at least one vertical cross-section being with respect to a respective one of individual horizontal regions15(e.g., example respective cut lines A-A that would be identical in vertical cross-sections to that depicted byFIG.9).

In one embodiment and as shown, the horizontally-spaced features formed in individual die areas100comprise operative (in the finished-circuitry construction) channel-material strings53x (e.g., comprising channel material36) of memory cells and that extend through first and second tiers22,20in openings25in memory-array region12in the finished-circuitry construction. Further in such embodiment, horizontally-spaced features75of the registration mark or the alignment mark being fabricated comprise dummy (meaning always inoperative) channel-material strings53z. Example features75comprising example channel-material strings53x,53zmay taper radially-inward and/or radially-outward moving deeper and stack18and may be vertical (as shown) or angled slightly from vertical (not shown). Example features75may also comprise charge-blocking material30, storage material32, and charge-passage material34elevationally along second tiers20and first tiers22. Materials30,32, and34(e.g., memory-cell materials) may be formed by, for example, deposition of respective thin layers thereof over stack18and within openings is stack18followed by planarizing such back at least to a top surface of stack18as shown. Another second tier20(FIG.16) comprising material24may optionally be formed atop stack18, with openings formed there-through corresponding in size and positions to openings25and that are filled with material50(e.g., polysilicon) to comprise part of features75. Such another second tier20and openings there-through may be formed before or after forming corresponding openings in stack18and/or other parts of features75that are ultimately below material75. Such another second tier20and/or material50may also be formed in memory array region12(not shown).

Operative channel-material strings53x(features75) in memory array region12are shown as being in openings25and are arranged in groups or columns of staggered rows of four and five per row in array12and are arrayed in laterally-spaced memory-block regions58that will comprise laterally-spaced memory blocks58in a finished-circuitry construction. In this document, “block” is generic to include “sub-block”. Memory-block regions58and resultant memory blocks58(not yet shown) may be considered as being longitudinally elongated and oriented, for example along a first direction55. Dummy channel-material strings53z(features75) in horizontal area14are shown as being in openings25and are arranged in groups or columns of staggered rows in some regions of four and five per row and in other regions of three and four per row. Features75/Strings53xand/or53zmay be in alternate arrangement(s) and be of different construction(s).

By way of example, features75/strings53x,53zare shown as comprising part of individual channel-material string constructions comprising charge-blocking material30, storage material32, and charge-passage material34that have been formed in individual channel openings25elevationally along insulative tiers20and conductive tiers22. Transistor materials30,32, and34(e.g., memory-cell materials) may be formed by, for example, deposition of respective thin layers thereof over stack18and within individual channel openings25followed by planarizing such back at least to a top surface of stack18as shown. Materials30,32,34, and36are collectively shown as and only designated as material37in some figures due to scale. Example channel materials36include appropriately-doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Example thickness for each of materials30,32,34, and36is 25 to 100 Angstroms. Punch etching may be conducted as shown to remove materials30,32, and34from the bases of channel openings25to expose conductor tier16such that channel material36is directly electrically coupled with conductor material17of conductor tier16at least in memory array region12. Such punch etching may occur separately with respect to each of materials30,32, and34(as shown) or may occur collectively with respect to all after deposition of material34(not shown). Alternately, and by way of example only, no punch etching may be conducted and channel material36may be directly electrically coupled with conductor material17of conductor tier16by a separate conductive interconnect (not shown). Channel openings25are shown as comprising a radially-central solid dielectric material38(e.g., spin-on-dielectric, silicon dioxide, and/or silicon nitride). Alternately, and by way of example only, the radially-central portion within channel openings25may include void space(s) (not shown) and/or be devoid of solid material (not shown).

Referring toFIGS.17-24, horizontally-spaced vertical slots40have been formed through uppermost (at least) of first and second tiers22/20of stack18in horizontal area14(e.g., in individual horizontal regions15) of the registration mark or of the alignment mark that is being formed. Slots40may extend through stack18in horizontal area14(as shown) or only partially into stack18(not shown). Ideally, such are formed commensurate with forming analogous slots40in memory-array region12in die areas100as is shown (e.g., when forming the example memory circuitry), and slots40in regions12and14need not be the same size and/or shape relative one another.

FIGS.25-35show replacing of sacrificial material26(not shown) with metal material48through horizontally-spaced slots40, thus forming a mark90that is a registration mark or an alignment mark. In one embodiment, the registration mark or the alignment mark is fabricated as an alignment mark and in one embodiment as a registration mark. As an example, where sacrificial material26is silicon nitride, such can be isotropically selectively etched away through slots40using liquid or vapor H3PO4as a primary etchant and other materials comprise one or more oxides or polysilicon. This can be followed by formation of metal material48through slots40into void space resulting from the removal of sacrificial material26and then removing remnant metal material48from slots40. In one embodiment, for example in accordance with fabrication of memory circuitry, metal material48is conductive in the fabrication of control gate lines of memory circuitry that is within memory-array region12.

FIGS.25-35also show, and in one embodiment, horizontally-spaced vertical slots40having been filled with intervening material57to form a vertical wall95in individual vertical slots40. Intervening material57in memory-array region12may provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory blocks. Such may include one or more of insulative, semiconductive, and conducting materials and, regardless, may facilitate conductive tiers22in memory-array region12from shorting relative one another in a finished-circuitry construction. Example insulative materials are one or more of SiO2, Si3N4, and Al2O3. Intervening material57in memory-array region12may include through-array vias (not shown).

A thin insulative liner (e.g., Al2O3and not shown) may be formed before forming metal material48. Approximate locations of transistors and/or memory cells56are indicated with a bracket in some figures and some with dashed outlines in some figures, with transistors and/or memory cells56being essentially ring-like or annular in the depicted example. Alternately, transistors and/or memory cells56may not be completely encircling relative to individual channel openings25such that each channel opening25may have two or more elevationally-extending strings49(e.g., multiple transistors and/or memory cells about individual channel openings in individual conductive tiers with perhaps multiple wordlines per channel opening in individual conductive tiers, and not shown). Metal material48may be considered as having terminal ends50corresponding to control-gate regions52of individual transistors and/or memory cells56. Control-gate regions52in the depicted embodiment comprise individual portions of individual conductive lines29. Materials30,32, and34may be considered as a memory structure65that is laterally between control-gate region52and channel material36. In one embodiment and as shown with respect to the example “gate-last” processing, metal material48of conductive tiers22is formed after forming channel openings25and/or trenches40. Alternately, the conducting material of the conductive tiers may be formed before forming channel openings25and/or trenches40(not shown), for example with respect to “gate-first” processing.

A charge-blocking region (e.g., charge-blocking material30) is between storage material32and individual control-gate regions52. A charge block may have the following functions in a memory cell: In a program mode, the charge block may prevent charge carriers from passing out of the storage material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate, and in an erase mode the charge block may prevent charge carriers from flowing into the storage material from the control gate. Accordingly, a charge block may function to block charge migration between the control-gate region and the storage material of individual memory cells. An example charge-blocking region as shown comprises insulator material30. By way of further examples, a charge-blocking region may comprise a laterally (e.g., radially) outer portion of the storage material (e.g., material32) where such storage material is insulative (e.g., in the absence of any different-composition material between an insulative storage material32and metal material48). Regardless, as an additional example, an interface of a storage material and conductive material of a control gate may be sufficient to function as a charge-blocking region in the absence of any separate-composition-insulator material30. Further, an interface of metal material48with material30(when present) in combination with insulator material30may together function as a charge-blocking region, and as alternately or additionally may a laterally-outer region of an insulative storage material (e.g., a silicon nitride material32). An example material30is one or more of silicon hafnium oxide and silicon dioxide.

Referring toFIGS.36-39, after forming metal material48in horizontal area14, first and second tiers22/20in scribe-line areas200are cut through to form individual die85(FIGS.36and37) that individually comprise one of individual die areas100. In one embodiment, the cutting may be through registration and/or alignment mark(s)90and individual die85may comprise remaining-scribe-line area200at edge(s)99of the individual die in the finished-circuitry construction. A remnant90wof registration or alignment mark90may be in remaining-scribe-line area200in the finished-circuitry construction and comprises remaining of horizontally-spaced features75.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

In one example embodiment and as shown, horizontal space19of a registration or alignment mark90is devoid of horizontally-spaced features75(FIGS.7,17,25).FIG.40shows an alternate embodiment construction10a. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a” or with different numerals. In construction10a, registration or alignment mark90ahas its horizontal space19ahaving horizontally-spaced features75therein. Further, and in one embodiment of such example, horizontally-spaced features75are arrayed in a horizontal pattern in sections76with such horizontal pattern being continuous in sections76and in and across horizontal space19a. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

By way example, the embodiments depicted byFIGS.17,25, and40show slots40in mark90/90aas being horizontally-parallel relative one another and horizontally-elongated orthogonal to the vertical cross-section referred to above with respect to gaps77where there are less, if any, such horizontally-spaced features than are in section76.FIG.41shows an alternate example embodiment construction10b. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b” or with different numerals. By way example, mark90bcomprises an alignment mark90bor a registration mark90bwhere slots40bare horizontally-parallel relative one another and horizontally-elongated parallel to the subject vertical cross-section (e.g., a vertical cross-section as would be cut through line A-A inFIG.41). Alternately, the slots may not be parallel relative one another and/or may not be horizontally-elongated orthogonal to the vertical cross-section and/or not be horizontally-elongated parallel to the subject vertical cross-section. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Various layers (e.g., silicon dioxide and silicon nitride) may be largely transparent to the incident optical radiation that is typically used in the scanning of alignment and registration marks. If features extending through those layers are not perfectly vertical, such can adversely impact x-y spatial determination from the scan. To preclude such, uppermost portions of material surrounding the features is typically formed to comprise radiation-opaque material, adding to cost and complexity in fabrication due to the added processing associated therewith. Fabrication as described herein may preclude use of such added processing.

Alternate embodiment constructions may result from method embodiments described above, or otherwise. Regardless, embodiments of the invention encompass memory arrays independent of method of manufacture. Nevertheless, such memory arrays may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate, form, and/or have any of the attributes described with respect to device embodiments.

In one embodiment, integrated circuitry (e.g.,10,10a,10b) comprises a die (e.g.,85) comprising remaining-scribe-line area (e.g.,200inFIGS.36and37) at an edge (e.g.,99) of the die. Operative circuitry (e.g., that comprising memory-cell strings49) is in the die laterally-inward of the remaining-scribe-line area away from the edge of the die. A remnant (e.g.,90w) of a registration mark (e.g.,90,90a,90b) or of an alignment mark (e.g.,90,90a,90b) is in the remaining-scribe-line area. The remnant comprises horizontally-spaced features (e.g.,75) of the registration mark or of the alignment mark and that extend through vertically-alternating insulative-material tiers (e.g.,20) and metal-material tiers (e.g.,22) that are of different compositions relative one another. In one embodiment, the remnant is of a registration mark and in one embodiment is of an alignment mark. In one embodiment, the metal material of the metal-material tiers is conductive. In one embodiment, the remnant comprises horizontally-spaced vertical walls (e.g.,95) extending through uppermost of the insulative-material tiers and the metal-material tiers and in one such embodiment such vertical walls are horizontally-parallel relative one another. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, memory circuitry (e.g.,10,10a,10b) comprising strings (e.g.,49) of memory cells (e.g.,56) comprises a die (e.g.,85) comprising remaining-scribe-line area (e.g.,200) at an edge (e.g.,99) of the die. A stack (e.g.,18) comprising vertically-alternating first tiers (e.g.,22) and second tiers (e.g.,20) is in the die. Operative channel-material strings (e.g.,53x) of memory cells extend through the first tiers and the second tiers in a memory-array region (e.g.,12) of the die. First tiers (e.g.,22) and second tiers (e.g.,20) extend from the memory-array region into the remaining-scribe-line area. The first tiers are conductive in the memory-array region (at least). The second tiers are insulative. A remnant (e.g.,90w) of a registration mark (e.g.,90,90a,90b) or of an alignment mark (e.g.,90,90a,90b) is in the remaining-scribe-line area. The remnant comprises dummy channel-material strings (e.g.,53z) that extend through the first tiers and the second tiers. The second tiers of the remnant at least predominantly (more than 50% up to and including 100%) comprise metal material. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Any use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles (i.e., other than the straight angle).

The composition of any of the conductive/conductor/conducting materials herein may be conductive metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more metallic compound(s).

Herein, any use of “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

Conclusion

In some embodiments, a method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. The scribe-line area comprises a horizontal area in which a registration mark or an alignment mark is being fabricated. Horizontally-spaced features of the registration mark or of the alignment mark are simultaneously formed in the first tiers and the second tiers in the horizontal area and in the individual die areas. The horizontally-spaced features in the horizontal area are grouped in sections that are horizontally-separated by gaps in at least one vertical cross-section where there are less, if any, such horizontally-spaced features than are in the sections. Horizontally-spaced vertical slots are formed through uppermost of the first and second tiers of the stack in the horizontal area of the registration mark or of the alignment mark. Through the horizontally-spaced vertical slots, the sacrificial material is replaced with metal material. After the replacing, the first and second tiers in the scribe-line areas are cut through to form individual die that individually comprise one of the individual die areas.

In some embodiments, integrated circuitry comprising a die comprises remaining-scribe-line area at an edge of the die. Operative circuitry in the die is laterally-inward of the remaining-scribe-line area away from the edge of the die. A remnant of a registration mark or of an alignment mark is in the remaining-scribe-line area. The remnant comprises horizontally-spaced features of the registration mark or of the alignment mark and extends through vertically-alternating insulative-material tiers and metal-material tiers that are of different compositions relative one another.

In some embodiments, memory circuitry comprising strings of memory cells comprises a die comprising remaining-scribe-line area at an edge of the die. A stack is included that comprises vertically-alternating first tiers and second tiers in the die. Operative channel-material strings of memory cells extend through the first tiers and the second tiers in a memory-array region of the die. The first tiers and the second tiers extend from the memory-array region into the remaining-scribe-line area. The first tiers are conductive in the memory-array region. The second tiers are insulative. A remnant of a registration mark or of an alignment mark is in the remaining-scribe-line area. The remnant comprises dummy channel-material strings that extend through the first tiers and the second tiers. The second tiers of the remnant at least predominantly comprise metal material.