Field effect transistors with wide bandgap materials

An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2017/040328, filed Jun. 30, 2017, entitled “FIELD EFFECT TRANSISTORS WITH WIDE BANDGAP MATERIALS,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

FIELD

Embodiments as described herein generally relate to a field of electronic device manufacturing, and in particular, to manufacturing III-V material based electronic devices.

BACKGROUND

Generally, III-V materials have higher electron mobility and injection velocity relative to conventional silicon. III-V materials can be used for high performance electronic devices in integrated circuit manufacturing. The III-V material based devices may be used for system-on-chips (“SoCs”) applications, for example, for power management integrated circuits (“ICs”) and radio frequency (“RF”)-power amplifiers. The III-V material based transistors may be used for high voltage and high frequency applications.

Typically, fin-based transistors are fabricated to improve electrostatic control over the channel, reduce the leakage current and overcome other short-channel effects comparing with planar transistors.

A conventional technique to fabricate a III-V transistor involves growing a narrow bandgap InGaAs channel layer on a wide bandgap GaAs buffer layer in trenches in silicon dioxide on a silicon substrate using an aspect ratio trapping (ART) technique. Generally, the ART refers to a technique that causes the defects to terminate at the silicon dioxide sidewalls of the trenches. The wide bandgap GaAs buffer layer is used to prevent parasitic leakage from a source to a drain of the transistor.

Currently, III-V material based field effect transistors (FETs) suffer from an off-state leakage associated with narrow bandgap semiconductor channel materials due to elevated band-to-band tunneling (BTBT), BTBT induced barrier lowering (BIBL), or both BTBT and BIBL comparing to conventional silicon transistors. The off-state leakage degrades the performance of the III-V transistors. For example, the off-state leakage degrades the ability of the device to completely turn off.

DETAILED DESCRIPTION

Methods and apparatuses to reduce a BTBT induced leakage in field effect transistors are described. In one embodiment, an electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor. A gate electrode is on the channel layer. In one embodiment, the second semiconductor of the channel layer has a conduction band that has a substantially zero offset relative to the conduction band of the first semiconductor of the channel layer. In one embodiment, the second semiconductor of the channel layer has a valence band that has a substantially large offset relative to the valence band of the first semiconductor of the channel layer, as described in further detail below.

Typically, narrow bandgap III-V material based transistors have a wide bandgap material placed in source/drain regions to reduce a BTBT caused off-state leakage. The electric fields in source/drain regions, however, are not high enough to cause BTBT. As a result, the wide bandgap materials in the source/drain regions of the transistors are not substantially effective in reducing the BTBT.

In one embodiment, a transistor has a wide bandgap material that is placed in the regions having the highest electric field when the transistor is in operation (e.g., under a gate edge of the transistor) to reduce BTBT without impacting external resistance Rext comparing to conventional transistors. In one embodiment, a narrow bandgap material under a gate edge of the transistor is removed using a lateral etch to form a recess, and an intentionally undoped wide bandgap material is placed in the recess under the gate edge of the transistor, as described in further detail below.

While certain exemplary embodiments are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that the embodiments are not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

Reference throughout the specification to “one embodiment”, “another embodiment”, or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases, such as “one embodiment” and “an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, inventive aspects lie in less than all the features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment. While the exemplary embodiments have been described herein, those skilled in the art will recognize that these exemplary embodiments can be practiced with modification and alteration as described herein. The description is thus to be regarded as illustrative rather than limiting.

FIG. 1is a view100illustrating an electronic device structure according to one embodiment. An insulating layer102is deposited on a substrate101, as shown inFIG. 1.

A trench103is formed in the insulating layer102. In at least some embodiments, trench103represents one of a plurality of trenches that are formed on substrate101. As shown inFIG. 1, trench103has a bottom111that is an exposed portion of the substrate101and opposing sidewalls112. In one embodiment, the bottom portion111of the trench103has slanted sidewalls that meet at an angle (not shown).

In an embodiment, the bottom portion111is formed by etching the exposed portion of the substrate101aligned along a (100) crystallographic plane (e.g., Si (100)). In one embodiment, the etch process etches the portions of the substrate aligned along a (100) crystallographic plane (e.g., Si (100)) fast and slows down at the portions of the substrate aligned along (111) crystallographic planes (e.g., Si (111)). In one embodiment, the etch process stops when the portions of Si (111) are met that results in a V-shaped bottom portion111.

Trench103has a depth D114and a width W115. In one embodiment, depth114is determined by the thickness of the insulating layer102. In an embodiment, the width of the trench is determined by the width of the electronic device. In at least some embodiments, the electronic device has a fin based transistor architecture (e.g., FinFET, Trigate, GAA, a nanowire based device, a nanoribbons based device, or any other electronic device architecture). In one embodiment, the width115is from about 5 nanometers (nm) to about 300 nm. In an embodiment, the aspect ratio of the trench (D/W) is at least 1.5.

In an embodiment, the substrate101comprises a semiconductor material. In one embodiment, substrate101is a monocrystalline semiconductor substrate. In another embodiment, substrate101is a polycrystalline semiconductor substrate. In yet another embodiment, substrate101is an amorphous semiconductor substrate. In an embodiment, substrate101is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any semiconductor material.

In various implementations, the substrate can be, e.g., an organic, a ceramic, a glass, or a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the embodiments of the present invention.

In another embodiment, substrate101comprises a III-V material. Generally, the III-V material refers to a compound semiconductor material that comprises at least one of group III elements of the periodic table, e.g., boron (“B”), aluminum (“Al”), gallium (“Ga”), indium (“In”), and at least one of group V elements of the periodic table, e.g., nitrogen (“N”), phosphorus (“P”), arsenic (“As”), antimony (“Sb”), bismuth (“Bi”). In an embodiment, substrate101comprises InP, GaAs, InGaAs, InAlAs, other III-V material, or any combination thereof.

In alternative embodiments, substrate101includes a group IV material layer. Generally, the group IV material refers to a semiconductor material comprising one or more elements of the group IV of the periodic table, e.g., carbon (C), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), or any combination thereof. In one embodiment, substrate101comprises a silicon layer, a germanium layer, a silicon germanium (SiGe) layer, or any combination thereof.

In one embodiment, substrate101includes one or more metallization interconnect layers for integrated circuits. In at least some embodiments, the substrate101includes interconnects, for example, vias, configured to connect the metallization layers. In at least some embodiments, the substrate101includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of the electronic device manufacturing. In one embodiment, the substrate includes one or more buffer layers to accommodate for a lattice mismatch between the substrate101and one or more layers above substrate101and to confine lattice dislocations and defects.

Insulating layer102can be any material suitable to insulate adjacent devices and prevent leakage. In one embodiment, electrically insulating layer102is an oxide layer, e.g., silicon dioxide, or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer102comprises an interlayer dielectric (ILD). In one embodiment, insulating layer102is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), e.g., carbon doped silicon dioxide, porous silicon dioxide, silicon nitride, or any combination thereof. In one embodiment, insulating layer102includes a dielectric material having k-value less than 5. In one embodiment, insulating layer102includes a dielectric material having k-value less than 2. In at least some embodiments, insulating layer102includes a nitride, oxide, a polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), other electrically insulating layer determined by an electronic device design, or any combination thereof. In one embodiment, insulating layer102is a shallow trench isolation (STI) layer to provide field isolation regions that isolate one fin from other fins on substrate101. In one embodiment, the thickness of the insulating layer102is at least 10 nm. In one non-limiting example, the thickness of the insulating layer102is in an approximate range from about 10 nm to about 2 microns (μm).

In an embodiment, the insulating layer is deposited on the substrate using one or more of the deposition techniques, such as but not limited to a chemical vapour deposition (“CVD”), a physical vapour deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), spin-on, or other insulating deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, trench103is formed in the insulating layer102using one or more patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 2is a view200similar toFIG. 1after a buffer layer104is deposited onto the bottom111between sidewalls112and113of the trench103according to one embodiment. The buffer layer104is deposited to accommodate for a lattice mismatch between the substrate101and one or more layers above the buffer layer104and to confine lattice dislocations and defects.

In one embodiment, an aspect ratio D/W of the trench103determines the thickness of the buffer layer104. In an embodiment, the thickness of the buffer layer104is such that most defects originated from the lattice mismatch are trapped within the buffer layer and are prevented from being propagated into a device semiconductor layer above the buffer layer104using an aspect ratio trapping (ART).

In one embodiment, buffer layer104has the sufficient thickness that most defects present at the bottom111do not reach the top surface of the buffer layer104. In one embodiment, the thickness of the buffer layer104is at least about 5 nm. In one embodiment, the thickness of the buffer layer104is from about 5 nm to about 500 nm.

In one embodiment, the buffer layer104comprises a III-V material. In an embodiment, substrate101is a silicon substrate, and buffer layer104comprises a III-V material, e.g., InP, GaAs, InGaAs, InAs, InAlAs, other III-V material, or any combination thereof. In another embodiment, buffer layer104comprises a group IV material. In one embodiment, buffer layer104comprises Si, Ge, SiGe, carbon, other group IV semiconductor material, or any combination thereof.

In at least some embodiments, buffer layer104is deposited through trench103onto the bottom111using one of epitaxial techniques known to one of ordinary skill in the art of microelectronic device manufacturing, such as but not limited to a CVD, a PVD, an MBE, an MOCVD, an ALD, spin-on, or other epitaxial growth technique.

In one embodiment, semiconductor channel layer105is InGaAs, buffer layer104is GaAs, and substrate101is silicon. In more specific embodiment, semiconductor channel layer105is an InxGa1-xAs layer, where x is in an approximate range from about 0.3 to about 0.7.

In one embodiment, semiconductor channel layer105is a part of a channel of a transistor, as described in further detail below. In one embodiment, semiconductor channel layer105comprises an intentionally undoped semiconductor material. In one embodiment, semiconductor channel layer105has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3. In one embodiment, the concentration of dopants in the semiconductor channel layer105is from about 10{circumflex over ( )}14 atoms/cm{circumflex over ( )}3to about 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

In one embodiment, the thickness of semiconductor channel layer105is determined by design. In one embodiment, semiconductor channel layer105is a part of an electronic device, e.g., a FinFET, Trigate, gate all around (GAA), a nanowire based device, a nanoribbons based device, or any other electronic device. In one embodiment, the thickness of the semiconductor channel layer105is at least about 5 nm. In one embodiment, the thickness of the semiconductor channel layer105is from about 5 nm to about 500 nm.

In one embodiment, semiconductor channel layer105is deposited on the buffer layer104in the trench103and on top of the insulating layer102. In an embodiment, semiconductor channel layer105is deposited using one of deposition techniques, such as but not limited to a CVD, a PVD, an MBE, an MOCVD, an ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

The semiconductor channel layer105is then polished back to be planar with the top portions of the insulating layer102using a chemical mechanical polishing (CMP) process as known to one of ordinary skill in the art of microelectronic device manufacturing. The insulating layer102is then recessed down to a predetermined depth that defines a height304of the fin301. In one embodiment, a patterned hard mask (not shown) is deposited onto semiconductor channel layer105before recessing insulating layer102. In one embodiment, insulating layer102is recessed by an etching technique, such as but not limited to a wet etching, a dry etching, or any combination thereof techniques using a chemistry that has substantially high selectivity to the semiconductor channel layer105. In one embodiment, after recessing the insulating layer102, the patterned hard mask is removed by a chemical mechanical polishing (CMP) process as known to one of ordinary skill in the art of microelectronic device manufacturing.

As shown inFIG. 3, fin301is a portion of the semiconductor channel layer105that protrudes from a top surface of the insulating layer102. Fin301comprises a top portion303and opposing sidewalls302. In an embodiment, the length of the fin is substantially greater than the width. The height and the width of the fin301are typically determined by a design. In one embodiment, the width of the fin301is determined by the width115of the trench103. In an embodiment, the height of the fin301is from about 10 nm to about 100 nm and the width of the fin301is from about 5 nm to about 20 nm.

In another embodiment, forming the fin301involves depositing the semiconductor channel layer105on the buffer layer104on the substrate101using one or more of deposition techniques, such as but not limited to a CVD, a PVD, an MBE, an MOCVD, an ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. A stack comprising the semiconductor channel layer105on the buffer layer104is patterned and etched using one or more fin patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing to form the fin301. The insulating layer102is deposited to a predetermined thickness adjacent to portions of the sidewalls of the fin stack on the substrate.

FIG. 4is a view400similar toFIG. 3after a gate electrode401is deposited on a channel portion of the semiconductor channel layer105according to one embodiment.FIG. 5is a perspective view500illustrating the electronic device structure depicted inFIG. 4according to one embodiment. In one embodiment, the electronic device structure depicted inFIGS. 5 and 4is a transistor structure. View400is a cross-sectional view of the electronic device structure shown inFIG. 5along an axis A-A′ (“gate cut view”) according to one embodiment. As shown inFIG. 5, an axis B-B′ represents a source-drain cut view.

As shown inFIGS. 4 and 5, gate electrode401is deposited on and around the fin301. Gate electrode401is deposited on top portion303and opposing sidewalls302of a portion of the fin301. In one embodiment, the area of the fin301surrounded by the gate electrode401defines a channel portion of the transistor device. In one embodiment, the gate electrode401is a sacrificial (dummy) gate electrode.

Gate electrode401can be formed of any suitable gate electrode material, such as but not limited to a polysilicon, a metal, or any combination thereof. In at least some embodiments, the gate electrode401is deposited using one or more of the gate electrode deposition and patterning techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, a dummy gate electrode stack comprising a dummy gate electrode on a dummy gate dielectric (not shown) is formed on the channel portion of the fin301. Example dummy gate dielectric materials include silicon dioxide, although any suitable dummy gate dielectric material can be used.

As shown inFIG. 5, spacers501are formed on the opposite sidewalls of the gate electrode401. In one embodiment, the thickness of the spacers501is from 1 nm to about 10 nm, or other thickness determined by design to target the tradeoffs between large S/D contact area (which requires a thin spacer) and small contact-to-gate parasitic capacitance (which requires a thick spacer).

In one embodiment, the portions502of the fin301exposed by the spacers501at opposite sides of the gate electrode401define source/drain regions of the transistor device.

In at least some embodiments, spacers501are formed using one or more spacer deposition techniques known to one of ordinary skill in the art of the microelectronic device manufacturing. In one embodiment, the spacers501are low-k dielectric spacers. In one embodiment, the spacers501are nitride spacers (e.g., silicon nitride), oxide spacers, carbide spacers (e.g., silicon carbide), or other spacers.

As shown inFIGS. 4 and 5, the electronic device has gate electrode401surrounding the fin301on three sides that provides three channels on the fin301, one channel extends between the source and drain regions on one of the sidewalls302of the fin301, a second channel extends between the source and drain regions on the top portion303of the fin301, and the third channel extends between the source and drain regions on the other one of the sidewalls302of the fin301. As shown inFIGS. 4 and 5, gate electrode401has a top portion and laterally opposite sidewalls separated by a distance that defines the length of the channel on the fin301. In one embodiment, the length of the channel on the fin301is from about 5 nanometers (nm) to about 300 nm. In one embodiment, the length of the channel on the fin301is from about 10 nm to about 20 nm.

FIG. 6is a view600similar toFIG. 4, after portions502of the semiconductor channel layer105are removed according to one embodiment. View600is a cross-sectional view of the electronic device structure shown inFIG. 5along axis B-B′, after portions502are removed. As shown inFIG. 6, portions502of the semiconductor channel layer105are removed to form recesses603. As shown inFIG. 6, the recesses603is defined by the exposed portion601of the buffer layer104and the sidewall602of the semiconductor channel layer105underneath the edge of the spacer501. As shown inFIG. 6, the remaining semiconductor channel layer105has a width604that is defined by the width of the gate electrode401and the thickness of the spacers501.

In one embodiment, recesses603are formed by etching portions502of the semiconductor channel layer105outside the gate electrode401and spacers501. In one embodiment, gate electrode401and spacers501are used as a mask to selectively remove portions502of the semiconductor channel layer105. In one embodiment, portions502are selectively removed using one of the dry etching techniques known to one of ordinary skill in the art of the microelectronic device manufacturing.

FIG. 7is a view700similar toFIG. 6, after portions of the semiconductor channel layer105underneath the spacers501and gate electrode401are removed to form undercut regions701and702according to one embodiment. In one embodiment, undercut regions701and702are formed by a lateral wet etch of the portions of the semiconductor channel layer105underneath spacers501. As shown inFIG. 7, the remaining semiconductor channel layer105has a width703that is smaller than the width604. As shown inFIG. 7, undercut region701of the semiconductor channel layer105extends laterally underneath the gate electrode401from the edge of one the spacers501to a width706. The undercut region701exposes a portion704of the buffer layer104. Undercut region702of the semiconductor channel layer105extends laterally underneath the gate electrode401from the edge of the other one of the spacers501to a width707. Undercut region702exposes a portion705of the buffer layer104. As shown inFIG. 7, the undercut region701is defined by the exposed portion704of the buffer layer104and the sidewall708of the remaining semiconductor channel layer105underneath the gate electrode401. The undercut region702is defined by the exposed portion705of the buffer layer104and the sidewall709of the remaining semiconductor channel layer105underneath the gate electrode401.

In one embodiment, each of the width706and707is from about 5 nm to about 20 nm, or other width determined by design, depending on the width of the spacer501. In one embodiment, widths706and707are substantially similar. As shown inFIG. 7, each of the undercut regions701and702extends from the corresponding edge of the gate electrode401beneath the gate electrode401to a predetermined width, such as a width711. In one embodiment, the width711is from about 5 nm to about 10 nm, depending on the width of the semiconductor channel layer105, or other width determined by design for a target off-state leakage.

In one embodiment, the portions of the semiconductor channel layer105underneath the spacers501and gate electrode401are selectively removed using one of the wet etching techniques known to one of ordinary skill in the art of the microelectronic device manufacturing. Examples of etch processes are aqueous hydrochloride solution (wet etch) or plasma-based Cl2/H2/Ar dry etch.

FIG. 8is a view800similar toFIG. 7, after a semiconductor channel layer801is deposited in the undercut regions701and702according to one embodiment. As shown inFIG. 8, a portion802of the semiconductor channel layer801is deposited on sidewall708and portion704of the buffer layer104. A portion803of the semiconductor channel layer801is deposited on sidewall709and portion705of the buffer layer104. As shown inFIG. 8, portion802of the semiconductor channel layer801extends from the edge of the gate electrode401laterally underneath the gate electrode401to a width804. The portion803of the semiconductor channel layer801extends from the edge of the gate electrode401laterally underneath the gate electrode401to a width805. In one embodiment, each of the widths804and805is from about 5 nm to about 10 nm, depending on the width of the semiconductor channel layer105, or other width determined by design for a target off-state leakage. In one embodiment, widths804and805are substantially similar.

In one embodiment, the semiconductor channel layer801is a wide bandgap material layer that has a bandgap greater than a bandgap of the semiconductor channel layer105. In one embodiment, the semiconductor channel layer801has a conduction band that has a zero offset relative to the conduction band of the semiconductor channel layer105. In one embodiment, the semiconductor channel layer801has a valence band that has a substantially large offset relative to the valence band of the semiconductor channel layer105, as described in further detail below. In one embodiment, the semiconductor channel layer801is an undoped semiconductor material. In one embodiment, the semiconductor channel layer801has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3. In one embodiment, the semiconductor channel layer801has a dopant concentration from about 10{circumflex over ( )}14 atoms/cm{circumflex over ( )}3to about 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

In one embodiment, the semiconductor channel layer801is deposited in the undercut regions701and702through the recesses603and on exposed portions601of the buffer layer104and on top of the gate electrode401and spacers501. In one embodiment, the portions of the semiconductor channel layer801on the exposed portions601of the buffer layer104and top of the gate electrode401and spacers501are selectively removed while retaining the sidewall portions801and802using one of the dry etching techniques known to one of ordinary skill in the art of the microelectronic device manufacturing. In another embodiment, the semiconductor channel layer801is selectively grown in the undercut regions701and702. In an embodiment, the semiconductor channel layer801is deposited using one or more of the deposition techniques, such as but not limited to a CVD, a PVD, an MBE, an MOCVD, an ALD, spin-on, or other deposition technique.

FIG. 9is a view900similar toFIG. 8, after source/drain regions901and902are formed in recesses603according to one embodiment. In one embodiment, the source/drain regions901and902comprise a wide bandgap semiconductor that has a bandgap greater than a bandgap of the semiconductor channel layer105. In one embodiment, the source/drain regions901and902comprise a III-V material layer, such as but not limited to gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium gallium phosphide (InGaP), indium arsenide (InAs), AlxGa1-xAs, GaAsxSb1-x(where 0≤x≤1), InxGa1-xAsySb1-y, InxGa1-xAsyP1-y, InxGa1-xPySb1-y(where 0≤x≤0.3, 0≤y≤1), InxAl1-xAsySb1-y, InxAl1-xAsyP1-y(where 0.8≤x≤1, 0≤y≤1), or any combination thereof.

In one embodiment, the material of the source/drain regions901and902is similar to that of the material of the semiconductor channel layer801. In another embodiment, the material of the source/drain regions901and902is different from that of the semiconductor channel layer801. In one specific embodiment, the material of the semiconductor channel layer105is InGaAs, the material of the semiconductor channel layer801is InP and the material of the source/drain regions901and902is InAs.

In at least some embodiments, the source/drain regions901and902are formed of the same conductivity type such as N-type or P-type conductivity. In another embodiment, the source and drain regions901and902are doped of opposite type conductivity. In one embodiment, the dopant concentration in the source/drain regions901and902is substantially greater than in the semiconductor channel layer105and the semiconductor channel layer801. In an embodiment, the channel portion of the fin including semiconductor channel layer105and portions of the semiconductor channel layer801is intrinsic or undoped. In one embodiment, the source/drain regions901and902have a dopant concentration of at least 1×10{circumflex over ( )}19 atoms/cm{circumflex over ( )}3. In one embodiment, the concentration of the dopants in the source/drain regions901and902is from about 10{circumflex over ( )}18 atoms/cm{circumflex over ( )}3to about 10{circumflex over ( )}22 atoms/cm{circumflex over ( )}3.

In an embodiment, the channel portion of the fin including semiconductor channel layer105and portions of the semiconductor channel layer801is doped, for example to a conductivity level of equal or smaller than 1×10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3. In an embodiment, when the channel portion is doped it is typically doped to the opposite conductivity type of the source/drain portion. For example, when the source/drain regions are N-type conductivity the channel portion would be doped to a P-type conductivity. Similarly, when the source/drain regions are P-type conductivity the channel portion would be N-type conductivity. In this manner a fin based transistor can be formed into either a NMOS transistor or a PMOS transistor respectively. The channel portion can be uniformly doped or can be doped non-uniformly or with differing concentrations to provide particular electrical and performance characteristics. For example, channel portion can include halo regions, if desired. The source/drain regions901and902can be formed of uniform concentration or can include sub-regions of different concentrations or doping profiles such as tip regions (e.g., source/drain extensions). In an embodiment, the source/drain regions901and902have the same doping concentration and profile. In an embodiment, the doping concentration and profile of the source/drain regions901and902vary to obtain a particular electrical characteristic. In at least some embodiments, source/drain regions901and902are deposited into recesses603using one or more of deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing, such as but not limited to a CVD, a PVD, an MBE, an MOCVD, an ALD, spin-on, or other deposition technique.

FIG. 10is a view1000similar toFIG. 9, after a metal gate stack1002is deposited on a gate dielectric1001on the semiconductor channel layer105and contacts1004are formed on source/drain regions901and902according to one embodiment.FIG. 11is a perspective view1100illustrating the electronic device structure according to one embodiment. Perspective view1100represents a portion of the electronic device structure depicted inFIG. 10without contacts1004and1005and a capping insulating layer1003.FIG. 10represents a cross-sectional view of a portion of the electronic device structure depicted inFIG. 11along an axis B-B′ (source-drain cut view) according to one embodiment.

As shown inFIGS. 10 and 11, gate electrode401is removed and replaced with the metal gate stack1002on the gate dielectric1001. In one embodiment, a protection layer (not shown), e.g., a nitride etch stop layer (NESL) is deposited on source/drain regions901and902to selectively remove sacrificial gate electrode401. In one embodiment, gate electrode401is removed to form a trench having exposed semiconductor channel layer105and portions1006and1007of semiconductor channel layer801as a bottom and spacers501as opposing sidewalls. The dummy gate electrode can be removed using one or more of the dummy gate electrode removal techniques known to one of ordinary skill in the art of electronic device manufacturing.

As shown inFIGS. 10 and 11, gate dielectric1001is deposited on the exposed portions of the semiconductor channel layer105and semiconductor channel layer801. In one embodiment, gate dielectric1001is an oxide layer, e.g., a silicon oxide layer, an aluminum oxide, a hafnium containing oxide, or any combination thereof. In one embodiment, the gate dielectric1001is a high-k dielectric material, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide (HfxZryOz), lanthanum oxide (La2O3), lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicate (TaSiOx), titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide (e.g., Al2O3), lead scandium tantalum oxide, and lead zinc niobate, or other high-k dielectric materials. In one embodiment, the thickness of the gate dielectric1001is from about 2 angstroms (Å) to about 20 Å.

In an embodiment, the gate dielectric1001is deposited using one or more of the deposition techniques, such as but not limited to a CVD, a PVD, an MBE, an MOCVD, an ALD, spin-on, or other gate dielectric deposition technique. In one embodiment, the metal gate stack1002is formed on the gate dielectric1001filling the trench between the spacers. In one embodiment, the metal gate stack1002is a metal gate electrode layer, such as but not limited to, tungsten, tantalum, titanium, and their nitrides. It is to be appreciated, the metal gate electrode stack need not necessarily be a single material and can be a composite stack of thin films, such as but not limited to a polycrystalline silicon/metal electrode or a metal/polycrystalline silicon electrode. The metal gate stack1002can be deposited using one of the gate electrode layer deposition techniques, such as but not limited to a CVD, PVD, MBE, MOCVD, ALD, spin-on, electroless, electro-plating, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

As shown inFIGS. 10 and 11, the metal gate stack1002is deposited on and around a fin1101. The fin1101includes semiconductor channel layer105, portions802and803of the semiconductor channel layer801and source/drain regions902and901. The metal gate stack1002is deposited on a top portion1102and opposing sidewalls302of a portion of the fin1101that includes semiconductor channel layer105and portions of the semiconductor channel layer801. In one embodiment, the area of the fin1101surrounded by the metal gate stack1002defines a channel portion of the transistor device.

As shown inFIG. 10, portion801of the semiconductor channel layer801extends from the edge of the metal gate stack1002laterally underneath the metal gate stack1002to a width1007. Portion802of the semiconductor channel layer801extends from the edge of the metal gate stack1002laterally underneath the metal gate stack1002to a width1006. As shown inFIG. 10, a channel region1008includes the narrow bandgap semiconductor channel layer105between portions of the wide bandgap semiconductor channel layer801. In one embodiment, each of the widths1006and1007is from about 5 nm to about 10 nm, or other width determined by design.

As shown inFIGS. 10 and 11, the metal gate stack1002surrounds the fin1101on three sides that provides three channels on the fin1101, one channel extends between the source/drain regions901and902on one of the sidewalls1103of the fin1101, a second channel extends between the source/drain regions901and902on the top portion1102of the fin1101, and the third channel extends between the source/drain regions901and902on the sidewall1104of the fin1101. As shown inFIGS. 10 and 11, metal gate stack1002has a top portion and laterally opposite sidewalls separated by a distance that defines the length of the channel on the fin1101. In one embodiment, the length of the channel on the fin1101is from about 5 nanometers (nm) to about 300 nm. In one embodiment, the length of the channel on the fin1101is from about 10 nm to about 20 nm.

As shown inFIG. 10, contacts1004are formed on source/drain regions901and902. In one embodiment, after the metal gate stack1002is formed, the protection layer (not shown) on source/drain regions901and902is removed using one of the protection layer etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. As shown inFIG. 10, contact1004is deposited on source/drain region902and contact1005is deposited on source/drain region901.

In an embodiment, the contacts are deposited using one of contact deposition techniques, such as but not limited to a CVD, PVD, MBE, MOCVD, ALD, spin-on, electroless, electro-plating, or other contact deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, metal gate stack1002between spacers501is recessed back to a predetermined height, then the spacers501are removed and a capping insulating layer1003is deposited on the recessed metal gate stack1002to encapsulate the metal gate stack1002. In one embodiment, the material of the capping insulating layer1003is represented by one or more of the insulating layer materials described above with respect to insulating layer102.

FIG. 12is a view1200illustrating an electronic device structure according to one embodiment. As shown inFIG. 12, a metal gate stack1205is deposited on a gate dielectric1204on a semiconductor channel layer1201on a buffer layer1204on a substrate1201. Contacts1206and1207are formed on source/drain regions1202and1203on buffer layer1204on substrate1201. A capping insulating layer1208is deposited on the metal gate stack1205to encapsulate the metal gate stack1205.

In one embodiment, substrate1201represents one of the substrates described above with respect to substrate101. In one embodiment, buffer layer1204represents one of the buffer layers described above with respect to buffer layer1204. In one embodiment, the semiconductor channel layer1201represents one of the narrow bandgap semiconductor channel layers described above with respect to the narrow bandgap semiconductor channel layer105. In one embodiment, the gate dielectric1204represents one of the gate dielectrics described above with respect to the gate dielectric1001. In one embodiment, the metal gate stack1205represents one of the metal gate stacks described above with respect to the metal gate stack1002. In one embodiment, the source/drain regions1202and1203represent the source/drain regions described above with respect to the source/drain regions901and902. In one embodiment, the contacts1206and1207represent the contacts described above with respect to contacts1003and1004. In one embodiment, the capping insulating layer1208represent one of the capping insulating layers described above with respect to the capping insulating layer1003.

FIG. 12is different fromFIG. 11in that the wide bandgap semiconductor material is deposited only in the source/drain regions1202and1203. In the source/drain regions1202and1203the electric field is not high enough to cause BTBT. As a result, the wideband gap materials deposited in the source/drain regions are not substantially effective in the BTBT reduction, as described in further detail below.

FIG. 13is a view1300illustrating an energy band diagram of the electronic device structure according to one embodiment. As shown inFIG. 13, the energy band diagram includes an energy1302of electric current carriers, such as electrons and holes as a function of a distance1301along the electronic device structure. The electronic device structure includes a wide bandgap drain region1313adjacent to a narrow bandgap channel region1314adjacent to a wide bandgap source region1315. In one embodiment, the narrow bandgap channel region1314represents the semiconductor channel layer1201, and the wide bandgap drain region1313and wide bandgap source region1315represent the wide bandgap source/drain regions1202and1203depicted inFIG. 12.

The narrow bandgap channel region1314is beneath the gate electrode (not shown). As shown inFIG. 13, the narrow bandgap channel region1314is within the edges1311and1312of the gate electrode. As shown inFIG. 13, the wide bandgap drain region1313and the wide bandgap source region1315are outside of the gate electrode edges1311and1312.

As shown inFIG. 13, the wide bandgap drain region1313has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1316, narrow bandgap channel region1314has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1317and the wide bandgap source region1315has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1318. As shown inFIG. 13, each of the bandgap1318and bandgap1316is greater than a bandgap Eg1317of the narrow bandgap channel region1314. As shown inFIG. 13, the valence band of the wide bandgap source region1315has a valence band offset VBO1310at the gate edge1311relative to the valence band of the narrow bandgap channel region1314. Generally, the VBO is defined as a valence band discontinuity at the interface between the wide bandgap semiconductor and the narrow bandgap semiconductor.

As shown inFIG. 13, electrons1319tunnel1304from the valence band Ev of the narrow bandgap channel region1314to the conduction band Ec of the wide bandgap drain region1313above the Fermi level Ef leaving holes1321in the narrow bandgap channel region1314. As shown inFIG. 13, electron tunneling1304occurs within a BTBT window1303. As shown inFIG. 13, the BTBT increases a floating charge that lowers an energy of the valence band Ev in the narrow bandgap region1314from an energy1308to an energy1309. Generally, the BTBT window is defined as a distance between the valence band Ev in the narrow bandgap semiconductor and the Fermi level Ef in the wide bandgap semiconductor. The electron tunneling from the narrow bandgap channel region1314to the wide bandgap drain region1313within the BTBT window1303increases the off-state leakage current Id. As shown inFIG. 13, the valence band offset (VBO)1310is outside the BTBT window1303.

As shown inFIG. 13, the BTBT reduces an energy barrier from a conduction band level1305to a conduction band level1306for thermal electrons that travel from the wide bandgap region1315to the narrow bandgap channel region1314above the Fermi level. The BTBT induced barrier lowering (BIBL)1307further increases the off-state leakage current Id.

FIG. 14is a view1400of a graph including a set of curves1403showing an off-state leakage drain current Id1401of a narrow bandgap transistor as a function of a gate voltage Vg1402at different drain voltages according to one embodiment. In one embodiment, the narrow bandgap transistor has a structure that is similar to the narrow bandgap electronic device structure depicted inFIG. 12. In one embodiment, the transistor has InP source/drain regions, InGaAs channel region, where the heterojunctions of InP source/drain and InGaAs channel are at the gate edges (XUD=0). As shown inFIG. 14, when the narrow bandgap transistor is turned off (voltage at the gate electrode Vg is zero), the gate induced drain leakage (GIDL) Id increases as the bias voltage between the source and drain Vd increases. Typically, for the conventional narrow bandgap transistor devices, the off-state GIDL Id is elevated due to the BTBT or a combination of the BTBT and BIBL. In the latter case, the BTBT induced charge in the channel cannot easily flow into the substrate electrode, but floats inside the channel and the GIDL Id is due to both the BTBT and BIBL. The BTBT induced charge floats in the channel because there is no substrate or because there is an energy barrier which the BTBT induced charge cannot overcome. The type of devices in which the floating charge can occur include silicon on insulator (SOI) devices, gate-all-around devices, nanowire devices, nanoribbon devices, quantum well devices, or other electronic devices.

FIG. 15is a view1500illustrating an energy band diagram of the electronic device structure according to one embodiment. As shown inFIG. 15, the energy band diagram includes an energy1502of electric current carriers, such as electrons and holes as a function of a distance1501along the electronic device structure. The electronic device structure includes a channel region1521between a wide bandgap drain region1516and a wide bandgap source region1518. The channel region1521includes a narrow bandgap channel portion1517between a wide bandgap channel portion1514and a wide bandgap channel portion1515. The wide bandgap channel portion1514is adjacent to the wide bandgap drain region1516. The wide bandgap channel portion1515is adjacent to the wide bandgap source region1518. In one embodiment, the channel region1521represents the channel region1008, the wide bandgap drain region1516and wide bandgap source region1518represent the wide bandgap source/drain regions901and902depicted inFIGS. 10 and 11. In one embodiment, the wide bandgap channel portion1514and the wide bandgap channel portion1515represent parts of the wide bandgap semiconductor portions801and802depicted inFIGS. 10 and 11.

As shown inFIG. 15, the wide bandgap channel portion1514, narrow bandgap channel portion1517and the wide bandgap channel portion1515are beneath the gate electrode (not shown). As shown inFIG. 15, the channel region1521including the wide bandgap channel portion1514, narrow bandgap channel portion1517and the wide bandgap channel portion1515is within edges1522and1513of the gate electrode. As shown inFIG. 15, the wide bandgap drain region1516and the wide bandgap source region1518are outside of the gate electrode edges1522and1523.

As shown inFIG. 15, at the bias voltage Vd substantially equal to about 1.1V (Ef_s at distance 0.085 um−Ef_d at distance 0), the wide bandgap drain region1516has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1524, wide bandgap channel portion1514has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1525, narrow bandgap channel region1517has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1526, the wide bandgap channel portion1515has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1527, and the wide bandgap source region1518has a conduction energy band Ecand a valence energy band Evthat are separated by a bandgap Eg1528. As shown inFIG. 15, each of the bandgaps1524,1525,1527and1528is greater than a bandgap Eg1526of the narrow bandgap channel region1517. In one embodiment, the values of the bandgaps1524,1525,1527and1528are substantially the same. As shown inFIG. 15, the valence band of the wide bandgap channel portions1514and1515has a valence band offset VBO1509and1510underneath the gate electrode within the edges1522and1523relative to the valence band of the narrow bandgap channel region1517. As shown inFIG. 15, the conduction band Ec of each of the wide bandgap channel portions1514and1515has a substantially zero offset relative to the conduction band Ec of the narrow bandgap channel portion1517.

As shown inFIG. 15, at the bias voltage Vd substantially equal to about 1.1V, the valence band in the narrow bandgap channel region1517is at an energy level1506, which is above the Fermi level Ef of the wide bandgap drain region1516. As the energy states above Ef are empty while the energy states below energy level1506are filled with electrons, a BTBT window1503exists between energy level1506and the Fermi level Ef of the wide bandgap drain region1516within which electrons from the occupied states below energy level1506can tunnel to the empty states above the Fermi level Ef of the wide bandgap drain region1516through the bandgap1525of the wide bandgap channel portion1514. Because the wide bandgap channel portion1514coincides with the BTBT window, the tunneling width for electrons to tunnel through is increased by the valance band offset VBO1509and, as a result, the tunneling rates are reduced exponentially. As shown inFIG. 15, electrons tunnel within the BTBT window1503from the valence band Ev of the narrow bandgap channel region1517through the width of the wide bandgap channel portion1514to the conduction band Ec of the wide bandgap drain region1516above the Fermi level Ef.

As shown inFIG. 15, the valence band of the wide bandgap channel region1515has a valence band offset VBO1510underneath the gate electrode relative to the valence band of the narrow bandgap channel region1517. As shown inFIG. 15, the valence band of the narrow bandgap channel region1517is below the Fermi level Ef of the wide bandgap source region1518so that there is no BTBT window created. That is, electrons below energy level1506cannot tunnel to the conduction band Ec of wide bandgap source region1518through the bandgap1510because there are not empty states for electrons to occupy below the Fermi level Ef of the wide bandgap source region1518. The wide bandgap channel portion1514placed under the gate contains the BTBT window1503in the substantially high electric field region. In one embodiment, the electric field in the wide bandgap channel portion1514is at least 106V/cm. As shown inFIG. 15, the BTBT window in the high electric field region has the wide bandgap channel portion1514. The wide bandgap channel portion1514increases the tunneling width from the narrow bandgap channel region1517to the wide bandgap drain region1516that significantly lowers the BTBT rate comparing to the BTBT rate of the semiconductor structure illustrated inFIG. 13. In one embodiment, as the width of the wide bandgap channel region1514increases, the width of the tunnel for the carriers increases. In more specific embodiment, the electronic device with the wide bandgap channel region1514having the width of about 10 nm increases the carrier tunnel width so that the BTBT reduces in about 40 times comparing to the BTBT of the electronic device that does not have the wide bandgap channel region.

As the BTBT rate is lowered, the floating charge that increases an energy of the valence band Ev in the narrow bandgap channel region1517from an energy level1507to an energy level1506is reduced comparing to the floating charge of the electronic device structure depicted inFIG. 13. As the BTBT rate is lowered, the BIBL that reduces an energy barrier from a conduction band level1504to a conduction band level1505is reduced comparing to the BIBL of the electronic device structure depicted inFIG. 13.

As shown inFIG. 15, an energy barrier1519is generated by the gate-source field between the Fermi level Ef of the wide bandgap source region1518and the conduction band1504of the narrow bandgap channel region1517for thermal electrons that travel from the wide bandgap source region1518to the narrow bandgap channel region1517above the Fermi level. As shown inFIG. 15, an energy barrier1508is generated by the same gate-source field plus the VBO1510between energy level1506of the valence band in the narrow bandgap channel region1517and the valence band Ev of the wide bandgap source region1518for thermal holes that travel from the narrow bandgap channel region1517to the wide bandgap source region1518. As holes generated by BTBT1511cannot overcome the large energy barrier1508, the holes remain in the narrow bandgap channel region1517. This causes the floating charge effect that lowers the conduction band Ec from energy level1504to energy level1505, and valence band Ev from energy level1506to energy level1507. The floating charge effect reduces the thermal barrier for electrons1519that increases the thermionic leakage BIBL.

FIG. 16is a view1600of a graph including a set of curves1603showing an off-state leakage drain current Id1601of a narrow bandgap transistor having the wide bandgap channel portions as a function of a gate voltage Vg1402at different drain voltages according to one embodiment. In one embodiment, the narrow bandgap transistor has a structure that is similar to the narrow bandgap electronic device structure depicted inFIGS. 10 and 11. In one embodiment, the transistor has InP source/drain regions, the channel region including the InGaAs narrow bandgap portion between the InP wide bandgap portion, the width of each of the wide bandgap channel portions is about 10 nm, centered at the gate edge (and extending 5 nm from the gate edge), and the VBO is about 0.4 electron volts (eV). As shown inFIG. 15, the off-state drain leakage Id does not increase as the bias voltage between the source and drain Vd increases. As shown inFIG. 15, the off-state leakage current is not elevated with increasing the drain bias Vd.

FIG. 17illustrates an interposer1700that includes one or more embodiments of the invention. The interposer1700is an intervening substrate used to bridge a first substrate1702to a second substrate1704. The first substrate1702may be, for instance, an integrated circuit die that includes the transistors as described herein, diodes, memory devices, or other semiconductor devices. The second substrate1704may be, for instance, a memory module, a computer motherboard, or another integrated circuit die that includes the transistors, as described herein. Generally, the purpose of an interposer1700is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1700may couple an integrated circuit die to a ball grid array (BGA)1706that can subsequently be coupled to the second substrate1704. In some embodiments, the first and second substrates1702/1704are attached to opposing sides of the interposer1700. In other embodiments, the first and second substrates1702/1704are attached to the same side of the interposer1700. And in further embodiments, three or more substrates are interconnected by way of the interposer1700.

The interposer1700may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as but not limited to silicon, germanium, group III-V and group IV materials.

The interposer may include metal interconnects1708, vias1710and through-silicon vias (TSVs)1712. The interposer1700may further include embedded devices1714, including passive and active devices that include the transistors as described herein. The passive and active devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1700. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer1700.

FIG. 18illustrates a computing device1800in accordance with one embodiment of the invention. The computing device1800houses a board1802. The board1802may include a number of components, including but not limited to a processor1804and at least one communication chip1806. The processor1804is physically and electrically coupled to the board1802. In some implementations the at least one communication chip is also physically and electrically coupled to the board1802. In further implementations, at least one communication chip1806is part of the processor1804.

Depending on the application, computing device1800may include other components that may or may not be physically and electrically coupled to the board1802. These other components include, but are not limited to, a memory, such as a volatile memory1810(e.g., a DRAM), a non-volatile memory1812(e.g., ROM), a flash memory, an exemplary graphics processor1816, a digital signal processor (not shown), a crypto processor (not shown), a chipset1814, an antenna1820, a display, e.g., a touchscreen display1830, a display controller, e.g., a touchscreen controller1822, a battery1832, an audio codec (not shown), a video codec (not shown), an amplifier, e.g., a power amplifier1815, a global positioning system (GPS) device1826, a compass1824, an accelerometer (not shown), a gyroscope (not shown), a speaker1828, a camera1850, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth) (not shown).

In at least some embodiments, the processor1804of the computing device1800includes an integrated circuit die having one or more electronic devices, e.g., transistors or other electronic devices, as described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip1806also includes an integrated circuit die package having the transistors, as described herein. In further implementations, another component housed within the computing device1000may contain an integrated circuit die package having the transistors, as described herein. In accordance with one implementation, the integrated circuit die of the communication chip includes one or more electronic devices including the transistors, or other electronic devices, as described herein. In various implementations, the computing device1800may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device1800may be any other electronic device that processes data.

The following examples pertain to further embodiments:

In Example 1, an electronic device comprises a semiconductor channel layer on a buffer layer on a substrate, the semiconductor channel layer having a first portion and a second portion adjacent to the first portion, the first portion comprising a first semiconductor, the second portion comprising a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor; and a gate electrode on the semiconductor channel layer.

In Example 2, the subject matter of Example 1 can optionally include that the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.

In Example 3, the subject matter of any of Examples 1-2 can optionally include that the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

In Example 4, the subject matter of any of Examples 1-3 can optionally include that each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.

In Example 5, the subject matter of any of Examples 1-4 can optionally include that the first semiconductor comprises indium gallium arsenide, indium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium phosphide antimonide (InxGa1-xPySb1-y), indium aluminum arsenide antimonide (InxAl1-xAsySb1-y), indium aluminum arsenide phosphide (InxAl1-xAsyP1-y), where 0≤x≤1, 0≤y≤1, or any combination thereof.

In Example 7, the subject matter of any of Examples 1-6 can optionally include that the width of the second portion is from 5 nanometers to 10 nanometers.

In Example 8, the subject matter of any of Examples 1-7 can optionally include a source/drain region in a recess in the semiconductor channel layer; and a gate dielectric on the semiconductor channel layer.

In Example 9, the subject matter of Example 8 can optionally include that the gate dielectric wraps around the semiconductor channel layer.

In Example 10, the subject matter of any of Examples 9-10 can optionally include that the source/drain region comprises a third semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

In Example 11, the subject matter of any of Examples 1-10 can optionally include that the semiconductor channel layer is a part of a fin, a nanowire, or a nanoribbon.

In Example 12, the subject matter of any of Examples 1-11 can optionally include that the first portion of the semiconductor channel layer comprises an undercut region extending laterally underneath the gate electrode, and wherein the second portion is in the undercut region.

In Example 13, a system comprises a chip including an electronic device comprising a semiconductor channel layer on a buffer layer on a substrate, the semiconductor channel layer having a first portion and a second portion adjacent to the first portion, the first portion comprising a first semiconductor, the second portion comprising a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor; and a gate electrode on the semiconductor channel layer.

In Example 14, the subject matter of any of Example 13 can optionally include that the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.

In Example 15, the subject matter of any of Examples 13-14 can optionally include that the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

In Example 16, the subject matter of any of Examples 13-15 can optionally include that each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.

In Example 17, the subject matter of any of Examples 13-16 can optionally include that the first semiconductor comprises indium gallium arsenide, indium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium phosphide antimonide (InxGa1-xPySb1-y), indium aluminum arsenide antimonide (InxAl1-xAsySb1-y), indium aluminum arsenide phosphide (InxAl1-xAsyP1-y), where 0≤x≤1, 0≤y≤1, or any combination thereof.

In Example 19, the subject matter of any of Examples 13-18 can optionally include that the width of the second portion is from 5 nanometers to 10 nanometers.

In Example 20, the subject matter of any of Examples 13-19 can optionally include a source/drain region on the buffer layer; and a gate dielectric on the semiconductor channel layer. In Example 21, the subject matter of Example 20 can optionally include that the gate dielectric wraps around the semiconductor channel layer.

In Example 22, the subject matter of any of Examples 20-21 can optionally include that the source/drain region comprises a third semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

In Example 23, the subject matter of any of Examples 13-22 can optionally include that the semiconductor channel layer is a part of a fin, a nanowire, or a nanoribbon.

In Example 24, the subject matter of any of Examples 13-23 can optionally include that the first portion of the semiconductor channel layer comprises an undercut region extending laterally underneath the gate electrode, and wherein the second portion is in the undercut region.

In Example 25, a method to manufacture an electronic device comprises depositing a semiconductor channel layer comprising a first semiconductor on a buffer layer on a substrate; forming a gate electrode on the semiconductor channel layer; forming an undercut region in the semiconductor channel layer; depositing a second semiconductor in the undercut region, wherein the second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

In Example 26, the subject matter of any of Example 25 can optionally include that the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.

In Example 27, the subject matter of any of Examples 25-26 can optionally include that the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

In Example 28, the subject matter of any of Examples 25-27 can optionally include that each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.

In Example 29, the subject matter of any of Examples 25-28 can optionally include that the first semiconductor comprises indium gallium arsenide, indium arsenide, indium antimonide, indium gallium antimonide, or any combination thereof.

In Example 30, the subject matter of any of Examples 25-29 can optionally include that the second semiconductor comprises indium phosphide, gallium phosphide, indium gallium phosphide, or any combination thereof.

In Example 31, the subject matter of any of Examples 25-30 can optionally include that the width of the second portion is from 5 nanometers to 10 nanometers.

In Example 32, the subject matter of any of Examples 25-31 can optionally include forming a spacer on the gate electrode; etching a portion of the semiconductor channel layer outside the gate electrode to form a recess; and depositing a source/drain region in the recess.

In Example 33, the subject matter of Example 32 can optionally include that the second semiconductor is deposited in the undercut region through the recess.

In Example 34, the subject matter of any of Examples 25-33 can optionally include that the semiconductor channel layer is a part of a fin, a nanowire, or a nanoribbon.

In Example 35, the subject matter of any of Examples 25-34 can optionally include that the second semiconductor that has a bandgap greater than a bandgap of the first semiconductor, wherein the undercut region is formed using a wet etch.

In Example 36, the subject matter of any of Examples 25-35 can optionally include removing the gate electrode; depositing a gate dielectric on the semiconductor channel layer; and forming a metal gate stack on the gate dielectric.

In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.