Method for the testing of a dynamic memory

A method for the testing of the retention time of a piece of information in a dynamic memory cell includes increasing the leakages of current in this cell to accelerate the loss of information. Under these testing conditions, a reduced retention time is controlled to approach the true retention time obtained under conditions of normal reading. This method makes it possible to reduce the time taken to test the retention time of the dynamic memories while at the same time being very reliable.

FIELD OF THE INVENTION 
The present invention relates to memories, and, more particularly, to a 
method for testing a dynamic memory. 
BACKGROUND OF THE INVENTION 
The principle of dynamic storage relies on the holding, for a very short 
period of about one millisecond, of the charge of a capacitance associated 
with a MOS transistor. Thus, a dynamic memory is characterized especially 
by its period of retention of a piece of information. This sets the 
minimum data refreshing frequency needed to preserve the information in 
the memory. The refreshing of the data is obtained by setting up a read 
type access and then a write type access on each of the cells of the 
memory. 
The retention time of a dynamic memory depends on the technology used, 
variations inherent in the manufacturing process, the structure of the 
memory cell, the supply and bias voltages used, and the memory. The 
retention time is tested on each of the cells of the dynamic memories at 
the end of manufacture. The testing of this retention time actually 
comprises two steps. 
A first step known as a characterizing step includes making very precise 
measurements of this retention time on one or more cells of a batch of 
dynamic memory circuits. A value is obtained characterizing the memory and 
its method of manufacture for a batch or series of batches. The 
measurement of the retention time is done in practice by successive 
approximations, in specifying the real retention time by increasingly 
approaching values. In one practical example, a "1" is written in a cell 
of the dynamic memory, then reread at the end of one millisecond for 
example. If a "0" is read, it means that the information has been lost. 
Since the data has been lost, the "1" has to be rewritten and then a read 
access has to be done again, but at the end of a shorter period of time, 
such as, 500 microseconds for example. If a "1" is read, it means that the 
retention time in the example ranges from 500 microseconds to 1 
millisecond. 
Since a "1" has been read, the read access has refreshed the data element. 
It is possible to carry out a new read access after a slightly longer 
period of time, such as, 750 microseconds, for example. This procedure is 
continued until the value of the retention time has been specified with 
sufficient precision. 
Once one or more manufactured batches of DRAMs have been characterized, all 
the memories of these lots are tested. This operation is designed to 
ascertain that all the cells of all these memories have a retention time 
included in the interval that has been measured for characterization. This 
is the testing step. 
This testing step is very lengthy. Indeed, the retention time has to be 
guaranteed for each of the cells of each of the memories. Furthermore, it 
is not possible to limit the operations to only one reading per cell. 
Ideally it is necessary, in each memory, to measure these values for all 
the positions of a single `1` among the zeros and a single zero among the 
`1`'s. In practice, only 5 or 6 readings are done per cell with tests 
known as zero-field tests, one-field tests, and checkerboard pattern 
tests. 
Even if it is possible to carry out word access operation, the retention 
times with current technologies being about 1 millisecond, it is already 
necessary to take up nearly 25 seconds for testing just one 1-megabit 
memory. The testing of the dynamic memories is therefore very lengthy 
which means that it is very costly. 
SUMMARY OF THE INVENTION 
In view of the foregoing background, it is therefore an object of the 
invention to provide a method for the testing of dynamic memories that 
enables a major reduction in testing times without accepting any loss in 
the reliability of the measurements made. 
The invention uses the principle of retention of dynamic memories, namely 
capacitive holding. More specifically, the approach of the invention is 
based on the leakages that cause the loss of information in a dynamic 
memory cell. Indeed, the measurement of the retention time is nothing 
other than the measurement of the influence of the losses of current in 
the cell. These current losses are due partly to the bit line voltages, 
the bias voltages of the transistors used, and especially the bias voltage 
of the bulks when the transistors of the cells are MOS transistors made in 
wells (P type transistors using N well technology, N type transistors 
using triple well technology). 
The principle of the invention is as follows: by acting in a controlled way 
on at least one of the factors that are known to increase the current 
leakages, a controlled and known reduction will be obtained in the 
retention time of the dynamic memory cell. A reduced retention time is 
obtained as opposed to the true retention time which is the retention time 
measured under the normal operational conditions of the memory. 
In the testing method according to the invention, a reduced retention time 
is measured and it is ascertained that this time corresponds to the true 
retention time expected. Through this procedure, the testing time is very 
substantially reduced without any loss of quality (namely reliability). 
In practice, to enable a comparison of the retention time of the 
measurement with the true retention time expected for the cell, it is 
enough, in the phase of characterizing the dynamic memory, to make a first 
characterization which will give the true retention time measured under 
normal conditions of operation, and a second characterization to measure 
the corresponding reduced value under conditions of modified operation 
which make it possible to increase the leakages in a known and controlled 
way. There is thus obtained the value (or interval of values) 
characteristic of the true retention time of the dynamic memory. 
The method according to the invention gives rise to an additional step of 
characterization but, in return, a great deal of time is gained in testing 
memory cells. In the practical example of a true retention time of 1 
millisecond, it is possible to obtain a reduced retention time of about a 
hundred microseconds. 
Thus, the invention relates to a method for testing a dynamic memory 
comprising a step for the verification of the retention time of each of 
the cells of the memory. The verification step includes, for each cell, an 
operation for writing an information element in the cell and an operation 
for reading the cell at the end of a specified time. This verification 
step comprises a phase for the modification of operation between the write 
operation and the read operation to increase the leakage currents in the 
cell. The specified time corresponds to a reduced retention time in the 
cell. 
Preferably, the phase for modifying the operation includes the modification 
of at least one bias voltage of one or more transistors of the memory 
cell. It may be the bit line voltage of the cell or the bias voltage for 
the bulk of one of more transistors of the cell. It may also be the gate 
control voltage of one or more access transistors of the cell. The choice 
of either modification or of a combination of these modifications depends 
on the structure of the cell and the reduced retention time to be obtained 
.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 shows an exemplary cell of a dynamic memory of the prior art. It is 
a memory known as the type with a MOS transistor with access by 
information bit. This structure has been chosen solely to illustrate the 
invention which can be applied to any type of dynamic memory cell 
structure. 
The cell 1 thus comprises an access transistor N1 and an information 
storage capacitor which, in the example, is the capacitance of a capacitor 
CMEM. This capacitor is connected between the source of the access 
transistor and a bias line of a potential Vplot of about Vdd/2. 
The access transistor N1 is controlled at its gate by a row selection line 
of the memory Rowi. The transistor N1 has its drain connected to a bit 
line referenced BL. This bit line is connected to an input/output 
amplifier circuit by associated bit line selection transistors (not 
shown). 
The principle of storage and reading is well known. It is based on the 
voltage stored by the capacitor CMEM. Briefly, in write mode, if it is 
sought to write a 0, the 0 level (GND) is applied to the bit line BL. The 
row of the cell to be written is selected by applying an appropriate 
potential to the row selection line Rowi to turn the access transistor N1 
on. The capacitor CMEM then stores a zero level. 
If this cell is read before the information is lost (when the retention 
time is not exceeded), the bit line BL is precharged to Vdd/2. If the 
corresponding row selection line Rowi is activated to make the access 
transistor N1 conductive, the potential of the bit line will be modified 
according to the charge stored by the capacitor CMEM. The resulting 
potential is compared with the reference level Vdd/2. 
The information is stored in the cell so long as the capacitor is not 
discharged. This capacitor gets discharged through the access transistor 
owing to the current leakages inherent in the structure. It is these leaks 
that determine the retention time of the dynamic memory cell. 
In the invention, the biasing conditions of the access transistor of the 
cell are acted upon to increase the current leakages. Then, a reduced 
retention time is obtained. In testing, it is ascertained that the cell 
has a reduced retention time corresponding to the true retention time of 
the dynamic memory. 
To increase the current leakages, it is possible to act on at least one of 
the potentials applied to the transistor of the cell. In the example 
shown, the access transistor N1 is an N type transistor made in a P type 
well. The bulk of an N type transistor is usually biased at a potential 
Vbulk connected to the ground GnD. According to the principle of the 
invention, between the write operation and the read operation of the 
verification step, it is possible to temporarily modify this bias 
potential Vbulk of the bulk and lower this potential by a transistor 
threshold voltage. In the example, there will then be Vbulk=Gnd-Vtn. In 
doing so, the leakage of current in the access transistor N1 and the 
capacitor CMEM is increased. 
It is also possible to act on the bit line voltage. Indeed, in normal 
operation, it is common practice after a write operation to carry the bit 
line to a potential of some hundreds of millivolts (200 millivolts for 
example) to reduce the leakages due to the access transistor N1. In the 
invention, for the testing of the retention time, the bit line is taken to 
zero volts so as to increase the leakages with respect to a normal mode of 
operation. By temporarily biasing the bit line to zero volts in the 
verification step, between the write operation and the read operation, 
instead of 200 millivolts applied in normal operation mode, it is possible 
to obtain a reduced retention time of 100 microseconds instead of one 
millisecond obtained in normal operating mode. It is also possible to act 
on the gate voltage of the access transistor. 
The invention has been explained with reference to FIG. 1. It can be 
applied more generally to all the DRAM cell structures. In particular, it 
can also be applied to cells that use the MOS transistor gate parasitic 
capacitance as a storage capacitor and have several access transistors. 
FIG. 2 thus shows an exemplary structure of a DRAM cell with four MOS 
transistors per bit: two access transistors N1 and N2 and two storage 
transistors N3 and N4. These four transistors are all herein of an N type, 
made in P type wells. Ideally, there is one well for the access 
transistors and one well for the storage transistors but, in general, to 
gain space, there is only one well in which the four transistors are made. 
In the example, they are made in the same well and their bulk is at a same 
potential Vbulk equal to the ground potential. 
The two access transistors N1 and N2 are controlled at their gate by the 
same row selection line of the memory Rowi. The transistor N1 has its 
drain connected to a bit line BLA while the transistor N2 has its drain 
connected to the complementary bit line BLB. 
The storage transistors N3 and N4 have their source connected to the ground 
Gnd. Their drain is connected to the source of the associated access 
transistor: N1 for the transistor N3 and N2 for the transistor N4. 
Finally, the gate of one storage transistor is connected to the drain of 
the other storage transistor (and therefore to the source of the access 
transistor associated with this other storage transistor). This dynamic 
memory cell structure is also known as the quasi-static RAM memory cell 
QSRAM for it is derived from the structure of a static RAM. 
In this case, the principle of the invention includes modifying at least 
one of the bias potentials of the cell, preferably the bit line potential 
BLA or BLB and/or the bulk potential Vbulk of the storage transistors 
and/or the access transistors. It is possible to modify the bulk potential 
of only one of the groups of transistors, preferably the storage 
transistors, if these two groups are made in two different wells. 
In any case, what has to be done is to temporarily modify at least one of 
the bias voltages applied to the cell, between the write operation and the 
read operation, to increase the current leaks, but without damaging the 
cell (without causing stress to it). The choice of one or more bias 
voltages to be modified depends on the structure of the dynamic memory 
cell in question, of which FIGS. 1 and 2 represent only some examples of 
the prior art. The method of the invention can be applied as well to P 
type transistor cells, and to transistor cells without wells. It is not 
limited to the structures described in the present application. 
According to the structure of the cell and the reduced retention time to be 
achieved, action will be taken on only one of the bias voltages of the 
transistors of the cell or on several voltages at a time. The method of 
the present invention can be used to obtain a reduced retention time that 
is far smaller than the true retention time corresponding to the normal 
conditions of operation (or use). For example, if this reduced retention 
time is equal to 100 microseconds for a true retention time of 1 
millisecond, and when it is known that the test has to be performed on all 
the cells of all the memories at the end of manufacture, it is possible to 
realize the considerable gain in time obtained by the testing method 
according to the invention. 
Furthermore, the verification tests thus include verifying the behavior 
under temperature. Now the temperature tests are costly in terms of 
equipment (for heating) and time. By using the reduced retention time to 
perform these temperature tests, precious time is gained. This entails the 
assumption that the steps for characterizing the true retention time and 
the reduced retention time comprise a phase of characterization in 
temperature. 
In practice, the step of verifying a dynamic memory cell according to the 
invention will comprise an operation for writing an information element in 
the cell (under normal biasing conditions), an operation for temporarily 
modifying a potential of at least one of the transistors of the cell to 
increase the current leaks in this cell, and then a read operation (under 
normal biasing conditions) at the end of a specified time corresponding to 
the expected reduced retention time. 
This expected reduced retention time is determined in an additional 
characterizing step prior to the verification step in which this duration 
is measured under specified modified access conditions. A flow chart 
illustrating the method for testing a dynamic memory in accordance with 
the present invention will now be described with reference to FIG. 3. From 
the start at Block 20, the method for testing a dynamic memory comprises 
the step of verifying a retention time of each of the memory cells of the 
dynamic memory, wherein each memory cell comprises one or more 
transistors. The verifying step includes the steps of writing an 
information element to the memory cell at Block 22, and temporarily 
increasing leakage currents in at least one of the transistors to cause a 
specified time of the memory cell to correspond to a reduced retention 
time at Block 24. The method further includes the step of reading the 
information from the memory cell at the end of the reduced retention time 
at Block 26. The method of the present invention obtains a reduced 
retention time that is smaller than the true retention time corresponding 
to the normal conditions of operation. A significant amount of time is 
thus gained in testing a dynamic memory by temporarily reducing the 
retention time of each memory cell. It is thus possible to establish the 
correspondence between the tested reduced retention time and the true 
retention time that is characteristic of the memory and guaranteed for 
users of these memories, in a range of temperature.