Semiconductor device and manufacturing method thereof

It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a circuit in which a thin film transistor (hereinafter referred to as TFT) is formed on a substrate having an insulating surface, and to a manufacturing method thereof. More particularly, the present invention relates to an electro-optical device typically known as a liquid crystal display device provided with an excellent-shaped contact hole, and to electronic equipment with an electro-optical device. Moreover, the semiconductor device according to the present invention refers to all equipment utilizing the semiconductor characteristics for functioning. The above electro-optical device and the electronic equipment with an electro-optical device are also included in semiconductor devices.

2. Description of the Related Art

The development of a semiconductor device having a large-area integrated circuit formed by the TFT (thin film transistor) on its insulating surface is under progression. AN active matrix liquid crystal display device, an EL display device, a contact-type image sensor, and the like are known as representative examples.

The characteristics of the TFT are deteriorated and reliability is lowered when organic resin film is directly formed on the TFT provided on the insulating surface. To solve those problems, conventionally, a laminated organic resin film is formed on the TFT after the formation of an inorganic insulating film (also called passivation film).

The TFT is normally connected to wirings through a contact hole. Therefore, when the above inorganic insulating film is provided on the TFT, it is necessary to form a contact hole for connecting to the upper layer wiring in the inorganic insulating film and the organic resin film which covers a TFT gate electrode, a source electrode, or a drain electrode. For instance, the contact hole is formed for connecting a drain electrode of a pixel TFT with a pixel electrode in an active matrix liquid crystal display using TFT.

A conventional manufacturing process will be described with reference toFIGS. 17A through D. Shown here is an example of an active matrix liquid crystal display applied to this process. Although the pixel TFT is not shown for simplification, a first conductive film11is identical with a drain electrode of a pixel TFT or electrically connected thereto. Also not shown is that there is a single layer or a multiple layer of insulating film between a substrate10and the first conductive film11.

Shown inFIG. 17Ais a state where the first conductive film11identical with the drain electrode of a pixel TFT or electrically connected thereto is formed on the substrate10on which the pixel TFT is formed. An inorganic insulating film12and an organic resin film13formed in laminations are formed on top of the first conductive film11.

And shown inFIG. 17Bis a state where the first patterning is performed by using a resist mask14by way of photolithography, and a first contact hole is opened only in the organic resin film13.

Subsequently, a second patterning is performed by using a resist mask15after removing the resist mask14, and a second contact hole is opened only in the inorganic insulating film12. This state is shown in FIG.17C. Since the second contact hole is formed in the bottom portion of the first contact hole, the diameter of its opening is smaller than that of the first contact hole.

Shown inFIG. 17Dnext is a state where a pixel electrode16, made of transparent conductive film, is formed after removing the resist mask15.

As shown inFIG. 17D, in this way there is a step in the shape of the contact hole because it has been formed after the first and second patterning processes.

Additionally, besides the above conventional manufacturing method, another method is to perform patterning right after forming the inorganic insulating film, then form the organic resin film and perform patterning again to form a contact hole. Two patterning processes were also necessary even in this method.

Since the number of processes and masks has increased due to two patterning (organic resin film patterning and inorganic insulating film patterning) processes in the conventional method, this led to an increase in costs.

In the two patterning processes, each method uses different photo mask, and therefore poor contact occurred when the masks had not been overlapped in precision. Also, in the example of the conventional process shown inFIG. 17, fining of the contact hole is difficult. That is because considering the margin when overlapping, the opening diameter of the second contact hole that was opened in the second patterning is 1.5 to 2 times bigger than the opening diameter of the first contact hole opened in the first patterning process.

Furthermore, the shape of a conventional contact hole (of which an example is shown inFIG. 17D) is a complicated shape formed by overlapping two contact holes with different opening diameter. Thus, poor coverage has occurred on a second conductive film formed later.

SUMMARY OF THE INVENTION

A technique of the present invention is for solving the above problems, and therefore it is an object of the present invention to provide a manufacturing method of a semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film (inorganic insulating film and organic resin film) of different material and film thickness by conducting etching once.

It is another object of the present invention to improve operating efficiency and reliability of a semiconductor device by providing a contact hole that is uniform in shape, and moreover an appropriate one.

It is still another further object of the present invention to form a pixel electrode of good coverage and to provide a structure for improving the yield of an active matrix type liquid crystal display device.

In order to solve the above problems, the present invention provides a semiconductor device comprising: a first conductive film formed on an insulating substrate; an inorganic insulating film covering said first conductive film; an organic resin film covering said inorganic insulating film; a contact hole that goes through said inorganic insulating film and said organic resin film; and a second conductive film formed on said organic resin film which is connected to said first conductive film at a bottom surface of said contact hole.

Further, according to the above structure, said contact hole is formed by performing one etching.

Still further, according to each structure of the above, an edge portion of an inorganic insulating film that comes in contact with a bottom surface of said contact hole is taper like having an angle range of 30° to 80° from a horizontal surface.

Further, according to each structure of the above, an edge portion of an organic resin film that comes in contact with said inorganic insulating film has an angle range of 50° to 90° from a horizontal surface.

Still further, according to each structure of the above, a TFT is electrically connected to said first conductive film.

Further, according to each structure of the above, said second conductive film is a pixel electrode.

According to each structure of the above, said inorganic insulating film is a silicon nitride film or a silicon oxide nitride film.

Moreover, in order to realize the above structure, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: forming a first conductive film; forming an inorganic insulating film on said first conductive film; forming an organic resin film on said inorganic insulating film; forming a contact hole in a laminated film formed of said inorganic insulating film and said organic resin film in one process; and forming a second conductive film in said contact hole.

Further, according to the above structure, said process of forming a contact hole is performed by dry etching employing mixed gas containing fluorine-based etchant gas and oxygen gas.

Furthermore, according to the above structure, a selective ratio of an etching rate of said inorganic insulating film to an etching rate of said organic resin film is 1.6 to 2.9.

Still further, according to the above structure, said inorganic insulating film is a silicon nitride film or a silicon oxide nitride film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description of preferred embodiments of the present invention will be given with reference toFIGS. 1 through 7.

FIGS. 1A through 1Care diagrams showing a manufacturing process of the present invention.

First of all, a first conductive film501, an inorganic insulating film502, and an organic resin film503are formed in laminations on a substrate500. (FIG. 1A)

After achieving the state illustrated inFIG. 1A, a resist mask504is formed by way of photolithography. Then, the opening of a contact hole is formed by simultaneously etching, only once, the lamination films of the inorganic insulating film502and the organic resin film503which are formed in laminations. (FIG. 1B) The etching conducted here is dry etching employing mixed gas, which contains oxygen and etchant gas that is at least fluorine-based.

The fluorine-based etchant gas as used herein indicates either fluorine or gas that partially contains fluorine. It also indicates, for example, simple substance gas such as F2, BF3, SiF4, HF, CF4, and the like or mixed gas. Moreover, it indicates gas obtained from the simple substance gas or mixed gas diluted by gases that do not contain chlorine (for example, H2, O2, N2, etc.

Subsequently, a second conductive film505is formed after the resist mask504is removed and then the first conductive film501and the second conductive film505are electrically connected. (FIG. 1C)

The above is a manufacturing process of the present invention. A number of experiments has been tested on the process illustrated in FIG.1B.

In order to obtain the state illustrated inFIG. 1A, a Ti film as the first conductive film501to be a connection layer is formed by sputtering and a 330 nm of silicon oxide nitride film (represented as SiOxNy) is formed by using SiH4/NH3/N2O/Ar or SiH4/NH3/N2/N2O/Ar as the inorganic insulating film502on the substrate500. Next, a 1 μm of acrylic resin film as the organic resin film503is formed in lamination by coating thereon.

The resist mask504is then formed by photolithography. In this process, dry etching is performed by employing mixed gas which at least contains oxygen and CF4.

An experiment was conducted by first changing the flow rate ratio of CF4to oxygen in dry etching. Setting 400 W (2.56 W/cm2) to an RF electric power, 0.4 Torr to a gas pressure, 35 sccm to an He flow rate, and 40 sccm/60 sccm, 45 sccm/55 sccm, 50 sccm/50 sccm, 55 sccm/45 sccm, and 60 sccm/40 sccm to a CF4flow rate/oxygen flow rate, respectively, the experiment was conducted.

The result of this experiment is shown inFIGS. 2A and 2B. When the flow rate ratio of CF4is increased, the etching rate of acrylic resin film with respect to the etching gas decreases whereas the etching rate of silicon oxide nitride film with respect to etching gas increases as shown in FIG.2A. The graph ofFIG. 2Billustrating a selective ratio (etching rate of acrylic resin film/etching rate of silicon oxide nitride film, etching rate of silicon oxide nitride film/etching rate of Ti film) is based on FIG.2A.

Furthermore, photographic views that correspond to the respective flow rate conditions are illustrated inFIGS. 3 and 4.

Among the photographic views ofFIGS. 3 and 4, a contact hole that is at its best shape is when the flow rate condition of CF4is 45 sccm to 55 sccm, preferably 50 sccm (FIG.3C). An edge portion of the inorganic insulating film that is in contact with the bottom surface of the contact hole in this state is taper like having an angle of 70° from the horizontal surface. And also fromFIG. 2B, when the contact hole is most excellently-shaped, the selection ratio is 1.6 to 2.9, preferably 1.9.

An experiment using an organic resin film made of polyimide rather than acrylic was conducted resulting in similar results. And another experiment using a nitrogenous inorganic insulating film such as a silicon nitride film and the like rather than silicon oxide nitride film was conducted and similar results were obtained.

The present inventor has proved from the results of the above experiments that by setting the selective ratio of dry etching (etching rate of organic resin film/etching rate of nitrogenous inorganic insulating film) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.

Although the upper portion of the contact hole is slightly an overhanging shape, the coverage of the second conductive film is not influenced as shown in FIG.3C. The reason for the occurrence of the overhang shape is that a complete anisotropic etching was not performed although by adjusting other etching conditions (gas pressure, RF electric power, etc.), a contact hole of a much better shape can be obtained. The following is a description of experiments conducted by adjusting other etching conditions.

The next experiment was conducted by setting the flow rate ratio of CF4to oxygen in dry etching at 50/50 and changing the gas pressure. Setting 400 W (2.56 W/cm2) to the RF electric power, 35 sccm to the He flow rate, and 0.2 Torr, 0.3 Torr, 0.4 Torr, and 0.5 Torr to gas pressure, respectively, the experiment was conducted.

The result of this experiment is shown inFIGS. 6A and 6B.FIG. 6Ais a graph illustrating a pressure dependency of the etching rate andFIG. 6Bis a graph illustrating a pressure dependency of the selective ratio. By lowering the pressure in this experiment, the overhang in the top portion of the contact hole can be suppressed.

Next, another experiment was conducted by setting the flow rate ratio of CF4to oxygen in dry etching at 50/50 and changing the RF electric power. Setting 0.4 Torr to gas pressure, 35 sccm to the He flow rate, and 300 W, 400 W, 500 W, and 600 W to the RF electric power, respectively, the experiment was conducted.

The result of this experiment is shown inFIGS. 7A and 7B.FIG. 7Ais a graph illustrating an RF electric power dependency of the etching rate andFIG. 7Bis a graph illustrating an RF electric power dependency of the selective ratio. By making the RF electric power higher, the overhang in the top portion of the contact hole can be suppressed.

By employing one condition (the flow rate ratio of CF4to oxygen to He at 50/50/35, gas pressure at 0.3 Torr, RF electric power at 400 W) from among the preferable range that can be obtained from the results of experiments 1 to 3, the contact hole is opened taper shaped in multiple steps and a desirable shape can also be opened without an overhang occurring in the top portion of the contact hole as shown inFIGS. 5A and 5B.FIG. 5Cis an enlarged schematic view of the contact hole corresponding to FIG.5B.

An edge portion of the inorganic insulating film that comes in contact with the bottom surface of the contact hole (FIG. 5C, a) can be taper like with an angle range of 30° to 80° from a horizontal surface by utilizing the present invention. Additionally, an edge portion of the organic resin film that comes in contact with the inorganic insulating film (FIG. 5C, b) can be angled at a range of 50° to 90° from a horizontal surface.

Further, by employing the present invention, a fine shape contact hole with a precise diameter of 3 μm or lower, preferably 1.2 μm or lower, can be achieved.

Furthermore, a more detailed description of embodiments of the present invention is described in the following.

An embodiment according to the present invention is described with reference toFIGS. 8to11. A manufacturing method that manufactures a pixel circuit and a driving circuit, which controls the pixel circuit, on the same substrate at the same time will be explained here. However, to simplify the explanation, in the driving circuit, a CMOS circuit that is the basic circuit of a shift resist circuit, a buffer circuit, or the like, and an N channel TFT that forms a sampling circuit are shown in the diagrams.

InFIG. 8A, it is preferred that a quarts substrate or a silicon substrate be used as a substrate101. A quartz substrate is used in the present embodiment. Others such as a metal substrate or a stainless substrate with an insulating film formed thereon can also be used as a substrate. Substrates having heat resistant properties that can stand a temperature of 800° C. are demanded in the present embodiment, therefore any of the substrates that meets this demand can be used.

A semiconductor film102with a film thickness of 20 to 100 nm (preferably 40 to 80 nm) containing an amorphous structure is formed by low pressure thermal CVD, plasma CVD, or sputtering on the surface in which a TFT of the substrate101is to be formed. Though an amorphous silicon film with a film thickness of 60 nm is formed in the present embodiment, this film thickness is not the final active layer film thickness of the TFT since there is a thermal oxide process later.

Also, as a semiconductor film containing an amorphous structure, there are an amorphous semiconductor film and a microcrystal semiconductor film. A compound semiconductor film containing an amorphous structure such as an amorphous silicon germanium film is included also.

Next, a mask film103formed of an insulating film containing silicon is formed on the amorphous silicon film102, and opening portions104aand104bare formed by patterning. During a crystallization process, the opening portions become a doped region for doping catalytic element to promote crystallization. (FIG. 8A)

Moreover, a silicon oxide film, a silicon nitride film, and a silicon oxide nitride film can be used as the insulating film containing silicon. A silicon oxide nitride film is an insulating film containing a predetermined amount of silicon, nitrogen, and oxygen and an insulating film represented by SiOxNy. It is possible to manufacture a silicon nitride oxide film using SiH4, N2O, and NH3as raw gas and better if it contains nitrogen at a concentration of 25 atomic % or higher and less than 50 atomic %.

While performing patterning on the mask film103, a marker pattern is formed that will be the standard (reference) for a patterning process which will be performed later. When performing etching on the mask film103, the amorphous silicon film102will be slightly etched. However, this step can be used as the marker pattern when joining (aligning) the masks later.

Next, a semiconductor film containing a crystal structure will be formed according to a technology disclosed in Japanese Patent Application Laid-Open No.Hei 10-247735 (corresponding to the serial number of U.S. patent application Ser. No. 09/034,041). The above disclosed technology is a crystallization means using catalytic elements (one or more type of elements chosen from nickel, cobalt, germanium, tin, lead, palladium, iron, and copper) that promote crystallization of the semiconductor film.

To be more specific, heat treatment is performed while holding a catalytic element on a surface of the semiconductor film containing amorphous structure. This is to convert the semiconductor film containing an amorphous structure to a semiconductor film containing a crystal structure. A technology disclosed in an embodiment 1 of Japanese Patent Application Laid-Open No. Hei 7-130652 can be used as a crystallization means. Furthermore, a single crystalline semiconductor film and also a polycrystalline semiconductor film are included as a semiconductor film containing a crystal structure, though a semiconductor film containing a crystal structure formed by using the technology disclosed in the above publication has a crystal grain boundary.

The above publication employs a spin coating method for forming a layer containing a catalytic element on a mask film. However, gaseous methods such as vapor method and sputtering can be as film forming means to form thin films containing a catalytic element.

Depending upon the amount of hydrogen contained in the amorphous silicon film, heat treatment is performed for a duration of 1 hour preferably at 400 to 550° C. It is desired that hydrogen be sufficiently eliminated before crystallization and the preferred amount of hydrogen contained be 5 atomic % or less.

In the crystallization process, first, heat treatment process is performed at 400 to 500° C. for a duration of 1 hour to eliminate hydrogen from the inside of the film, followed by performing heat treatment at 500 to 650° C. (preferably at 550 to 600° C.) for a duration of 6 to 16 hours (preferably for 8 to 14 hours).

In the present embodiment, nickel is used as the catalytic element, and heat treatment is performed for a duration of 14 hours at 570° C. As a result, crystallization progresses in a direction roughly parallel with the substrate (in the direction shown by the arrows) using the opening portions104aand104bas the starting point and semiconductor films (crystalline silicon films in the present embodiment)105a-105dhaving a crystal structure comprising crystals whose crystal growth directions are macroscopically aligned are formed. (FIG. 8B)

Gettering process is performed next to remove the nickel used in the crystallization process from the crystalline silicon film. In the present embodiment, using the mask film13that was previously formed just as the mask, the process of adding an element that belongs to group15(phosphorous in the present embodiment) is performed and then phosphorous doped regions containing phosphorous (hereinafter referred as gettering region)106aand106bare formed at 1×1019to 1×1020atoms/cm3of concentration on the crystalline silicon film exposed from the opening portions104aand104b. (FIG. 8C)

Next, heat treatment process is performed at 450 to 650° C. (preferably at 500 to 550° C.) in a nitrogen atmosphere for a duration of 4 to 24 hours (preferably for 6 to 12 hours). Through this heat treatment process, the nickel in the crystalline silicon film moves toward the direction of the arrow and is captured in the gettering regions106aand106bby the gettering action of phosphorus. Namely, since nickel is removed from the crystalline silicon film, the concentration of nickel in crystalline silicon films107athrough107dafter gettering can be reduced to 1×1017atoms/cm3or below, preferably up to 1×1016atms/cm3.

Then after removing the mask film103, a protection film.108is formed for doping of impurities later on the crystalline films107athrough107d. It is better to utilize either a silicon oxide nitride film or a silicon oxide film with a thickness of 100 to 200 nm (preferably 130 to 170 nm) as the protection film108. During impurity doping, this protection film108is for not exposing the crystalline silicon film directly to the plasma and is meant for making it possible to control subtle concentration.

A resist mask109is formed on top of the protection film108and an impurity element that gives P-type is doped (hereinafter referred as P-type impurity element) via the protection film108. A representative element belonging to group13as a P-type impurity element, typically boron or gallium can be used. This process (called channel dope process) is to control the threshold voltage of TFT. Furthermore, diborane (B2H6) is not mass separated but is doped by a plasma excited ion doped method. Of course, ion implantation can be employed to perform mass separation.

In this process, impurity regions110aand110bcontaining a P-type impurity element (boron in the present embodiment) are formed at a 1×1015to 1×1018atoms/cm3(typically 5×1016to 5×1017atoms/cm3) concentration. The above concentration range of the impurity region (a region excluding phosphorus) containing P-type impurity element is defined as P-type impurity region (b) in the specifications of the present invention. (FIG. 8D)

Next, the resist mask109is removed, patterning is performed on the crystalline silicon film, and island-like semiconductor layers (hereinafter referred as active layer)111through114are formed. Further, by selectively doping nickel and then performing crystallization, the active layers111through114are formed of crystalline silicon films of extremely good crystal quality. Specifically, rod like or column like crystal has crystal structures with specific directional properties.

After crystallization, nickel is removed-or reduced by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the active layers111through114is 1×1017atoms/cm3or less, preferably 1×1016atoms/cm3. (FIG. 8E)

The active layer111of P channel TFT is a region that does not contain an intentionally doped impurity element and the active layers112through114of N channel TFT are P-type impurity regions (b). The present invention defines the state of all these active layers111through114as intrinsic or substantially intrinsic. That is, it can be considered that a region intentionally doped with impurities without hindering the operation of the TFT to a certain degree is a substantially intrinsic region.

An insulating film containing silicon with a thickness of 10 to 100 nm is formed by plasma CVD or sputtering. A silicon oxide nitride film of 30 nm thickness is formed in the present embodiment. A single layer or a laminated layer of other insulating films containing silicon can be used as the insulating film containing silicon.

Next, heat treatment process is performed under an oxidizing atmosphere (thermal oxidation process) at a temperature of 800 to 1150° C. (preferably 900to 1000° C.) for a duration of 15 minutes to 8 hours (preferably 30 minutes to 2 hours). In the present embodiment, heat treatment process is performed at 950° C. for 80 minutes under oxygen atmosphere doped with 3% by volume of hydrogen chloride. Furthermore, the boron doped in the process ofFIG. 8Dis activated during this thermal oxide process. (FIG. 9A)

Oxide reaction is progressing even on an interface between the insulating film containing silicon and the active layers111through114under this insulating film during the thermal oxidation process. The present invention takes this into consideration and makes adjustments so that the film thickness of a gate insulating film115when finally formed is 50 to 200 nm (preferably 100 to 150 nm). In the thermal oxidation process of the present embodiment, oxidation is conducted on 25 nm of the 60 nm thickness of active layers so that the film thickness of the active layers111through114becomes 35 nm. Since a thermal oxide film with a 50 nm of film thickness is added to a 30 nm thickness insulating film containing silicon, the final film thickness of the gate insulating film115will be 105 nm.

Subsequently, new resist masks116through119are formed and impurity regions120through122that presents N-type are formed by adding an impurity element that gives N-type (hereinafter referred to as N-type impurity element). Further, as a representative element belonging to group15as an N-type impurity element, typically phosphorus or arsenic can be used. (FIG. 9B)

The impurity regions120through122are impurity regions for functioning as an LDD region later for the N channel TFT of the CMOS circuit and the sampling circuit. The N-type impurity elements in the impurity regions formed here contain 2×1016to 5×1019atoms/cm3of concentration (typically 5×1017to 5×1018atoms/cm3). The present invention defines the impurity regions containing N-type impurity elements in the above concentration range as N-type impurity region (b).

Here, mass separation is not performed on phosphine(PH3) and phosphorus is doped at 1×1018atoms/cm3by plasma excited ion dope means. Of course, the ion implantation method, which performs mass separation, can be employed. Phosphorus is doped in the crystalline silicon film via the gate film115in this process.

Next, heat treatment is performed at 600 to 1000° C. (preferably 700 to 800° C.) in an inactive atmosphere in order to activate the phosphorus that was doped in the process of FIG.9B. In this embodiment, heat treatment is performed at 800° C. for 1 hour in a nitrogen atmosphere.

The active layer and the interface between the active layer and the gate insulating film that was damaged during the doping of phosphorus can be restored. It is preferred that electric heat furnaces be employed in this activating process such as furnace annealing, though light annealing such as lamp annealing and laser annealing can both be used.

Through this process, the connecting portion with the boundary surface of the N-type impurity regions (b)120through122, that is, the intrinsic or substantially intrinsic portion that exists around the N-type impurity region (b) (of course including the P-type impurity region (b)) becomes clear. This means that the LDD region and the channel-forming region will form a remarkably good connecting portion at the time the TFT is completed.

A conductive film that is to be a gate wiring is formed next. Although the gate wiring can be formed as a single layer conductive film, it is preferred that a lamination film of 2 or 3 layers be formed to meet the needs when required. In this embodiment, a first conductive film123and a second conductive film124are formed as the layered films. (FIG. 9D)

Elements chosen from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si); conductive films from the above elements as the main component (typically a, nitride tantalum film, a nitride tungsten film, a nitride titanium film) or alloy films from the combination of the above elements (typically an alloy of Mo—W, an alloy of Mo—Ta) can be used for the first conductive film123and the second conductive film124.

It is better that the first conductive film123have a thickness of 10 to 50 nm (preferably 20 to 30 nm) and the second conductive film have a thickness of 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 50 nm thickness of nitride tungsten (WN) film as the first conductive film123and a 350 nm thickness of tungsten film as the second conductive film124are employed. Further, although not shown, it is effective to form a silicon film of about 2 to 20 nm thickness under the first conductive film123. By forming this silicon film, the adhesion property of the conductive film formed thereon can be improved and oxidation can be prevented.

Employing a nitride tantalum film as the first conductive film123and a tantalum film as the second conductive film is also effective.

Next, 400 nm thickness of gate wirings125through128are formed by etching the first conductive film123and the second conductive film124together. During this time, the gate wirings126and127, formed in a driving circuit, are formed to overlap with a portion of the N-type impurity regions (b)120through122through the gate insulating film115. The gate wirings128aand128bcan be seen as two wirings from a cross section, but actually the gate wirings128aand128bare formed of one pattern connected continuously. (FIG.9E).

Then a resist mask129is formed and a P-type impurity element (boron in this embodiment) is doped so that the impurity regions130and131containing boron is formed at high concentration. In this embodiment, boron is doped at 3×1020to 3×1021atoms/cm3(typically 5×1020to 1×1021atoms/cm3) of concentration by the ion doping means employing diborane (of course ion implantation can be used). The present invention defines the impurity regions containing P-type impurity elements in the above concentration range as P-type impurity region (a). (FIG. 10A)

Subsequently, the resist mask129is removed and resist masks132through134are formed so as to cover the gate wirings and a region that is to be a P channel TFT. Then an N-type impurity element (phosphorus in this embodiment) is doped and impurity regions135through141containing phosphorus are formed at high concentration. The ion doping means employing phosphine (PH3) is also conducted here (of course ion implantation can be used). The concentration of phosphorus in this region is 1×1020to 1×1021atoms/cm3(typically, 2×1020to 5×1021atoms/cm3). (FIG. 10B)

The specifications of the present invention define the impurity regions containing N-type impurity elements in the above concentration range as N-type impurity region (a). Although the region in which the impurity regions135through141have been formed already contains phosphorus and boron that were doped in the previous process, there is no need to take into consideration the influences of phosphorus and boron that were doped in the previous process since it is considered that phosphorus was doped at a sufficient high concentration.

Next, the resist masks132through134are removed and a cap film142formed of an insulating film containing silicon is formed at a film thickness of 25 to 100 nm (preferably 30 to 50 nm). A silicon nitride film of 25 nm thickness is used in this embodiment.

Using the gate wirings125through128as masks, an N-type impurity element (phosphorus in this embodiment) is doped in a self-aligning manner. Impurity regions143through146formed in this way are adjusted so that phosphorus can be doped at a concentration of ½ to {fraction (1/10)} of the above N-type impurity regions (b) (typically ⅓ to ¼)(however, a concentration that is 5 to 10 times higher than the concentration of boron doped in the above-mentioned channel doping process, representatively 1×1016to 5×1018atoms/cm3, typically 3×1017to 3×1018atoms/cm3). In the specification, the impurity regions containing N-type impurity elements (however, excluding P-type impurity region (a)) in the above concentration range are defined as N-type impurity region (c). (FIG. 10C)

As phosphorus is doped through a 105 nm film thickness of insulating film (the lamination film of the cap film142and the gate insulating film115), the cap film that is formed on the sidewall of the gate wirings134aand134balso functions as a mask. That is, the length of an off-set region corresponding to the film thickness of the cap film142is formed. In order to lower the value of the off-electric current, it is important to suppress the overlap of the LDD region and the gate wiring as much as possible. In this sense, providing an off-set region is effective.

The length of the off-set region is determined by the film thickness of a cap film that is actually formed on the sidewall of a gate wiring or by a wraparound phenomenon during the doping of an impurity element (a phenomenon in which the doping of impurities is like slipping under the mask). From the viewpoint of suppressing the overlap of the LDD region and the gate wiring, it is extremely effective that a cap film be formed in advance when forming the N-type impurity region (c) as in the present embodiment.

As phosphorus is also doped at a concentration of 1×1016to 5×1018atoms/cm3in all the impurity regions except the portion concealed by the gate wiring in this process, since concentration is extremely low, influences are not inflicted on the functions of each impurity region. Also, as boron is already doped in the N-type impurity regions (b)143through146at a concentration of 1×1015to 1×1018atoms/cm3in the channel doping process, phosphorus is doped at a concentration that is 5 to 10 times higher than the concentration of boron in the P-type impurity regions (b). In this situation, it can also be considered that boron does not influence the functions of the N-type impurity regions (b).

However, strictly the phosphorus concentration of a portion of the N-type impurity regions (b) of either147or148that overlaps with the gate wiring is as it is, 2×1016to 5×1019atoms/cm3, though a 1×1016to 5×1018atoms/cm3concentration of phosphorus is added to the portion that does not overlap on the gate wiring, which means that the N-type impurity region contains phosphorus at a little higher concentration.

Next, a first interlayer insulating film149is formed. The first interlayer insulating film149with a film thickness of 100 to 400 m can be formed of an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon oxide nitride film or a lamination film formed of a combination of the above films.

Then heat treatment process is performed on the N-type or P-type impurity element, doped at its concentration respectively, for activation. In this process, heat treatment can be performed by furnace annealing, laser annealing, lamp annealing, or a combination of methods. If performing by furnace annealing, heat treatment is performed at 500 to 800° C., preferably at 550 to 600° C., in an inactive atmosphere. The impurity elements are activated at 600° C. for a duration of 4 hours in this embodiment. (FIG. 10D)

Moreover, in the present embodiment, the silicon nitride film and the silicon oxide nitride film are formed in a laminated state so as to cover the gate wiring, and activation is performed in this state. Although tungsten is used as the material for wirings in this embodiment, it is known that the tungsten film is extremely weak to oxide. That is, even if the tungsten film is covered with a protective film when oxidized, the tungsten film is oxidized immediately if a pinhole exists in the protective film. Since the silicon nitride film and the silicon oxide nitride film are laminated in this embodiment, activation process can be performed at high temperature without worrying about the pinhole problem.

Heat treatment is performed at 300 to 450° C. for a duration of 1 to 4 hours in an atmosphere containing 3 to 100% of hydrogen after the activation process. Then hydrogenation is carried out on the active layer. This process is to terminate dangling bonds in a semiconductor layer by thermally excited hydrogen. As other hydrogenation means, plasma hydrogenation (using hydrogen excited by plasma) can be performed.

A second interlayer insulating film150at a thickness of 500 nm to 1.5 μm is formed on top of the first interlayer insulating film146after finishing the activation process. This second interlayer insulating film150is a silicon oxide film with an 800 nm thickness formed by plasma CVD in this embodiment. A 1 μm thickness of inter layer insulating film is formed by a lamination film of the first interlayer insulating film149(silicon nitride oxide film) and the second interlayer insulating film150(silicon oxide film) in this way.

Furthermore, in a later process if thermal resistance permits, organic resin film such as polyimide, acrylic, polyamide, polyimide-amide, BCB (benzocyclobutene), and the like can be used as the second interlayer insulating film150.

A contact hole that reaches a source region or a drain region of a TFT opens and then source wirings151through154and drain wirings155through157are formed. The drain wiring155for forming the CMOS circuit is mutualized (common) between the P channel TFT and the N channel TFT. Though not shown, this wiring according to the present embodiment is a 3-layered structure formed of a 200 nm Ti film, a 500 nm aluminum film containing Ti, and a 100 nm Ti film by sputtering in successions.

Subsequently, a silicon nitride film, a silicon oxide film, or a silicon oxide nitride film can be used to form a passivation film158at 50 to 500 nm in thickness (typically 200 to 300 nm). According to the embodiment, a silicon nitride oxide film with a film thickness of 300 nm is formed as the passivation film158. (FIG. 11A) During this time, according to the present embodiment, a plasma process employing gas containing hydrogen such as H2, NH3, and the like is performed in advance before forming the film and then heat treatment is performed after the forming of the film. The excited hydrogen from the previous process is supplied into the first and the second interlayer insulating film. By performing heat treatment in this state, improvements can be made on the film of the passivation film115together with effectively hydrogenating the active layer since the hydrogen that was doped into the first and the second interlayer insulating films has diffused to the lower layer.

Furthermore, the hydrogenation process can be performed after forming the passivation film158. For example, performing heat treatment at 300 to 450° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen, or employing a plasma hydrogenation process in which similar effects can be obtained.

Then, a third interlayer insulating film159formed of organic resin is formed at about 1 μm in thickness. Polyimide, acrylic, polyamide, polyimide-amide, BCB (benzocyclobutene), etc. can be used as inorganic resin. The advantages of using organic resin are the simplification of forming a film, the reduction of a parasitic capacity due to a low dielectric constant, and having excellent flatness. Other organic resin or organic-based SiO compounds besides the ones mentioned above can be employed as well. Here, after coating the substrate, the interlayer insulating film159is formed by baking at 300° C. using a type of acrylic that is thermal polymeric.

In a region that is to be a pixel circuit, a shielding film160is formed on top of the third interlayer insulating film159. In the context of the present invention, the term “shielding film” means the shielding of light and electromagnetic wave. The shielding film160is formed of an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or has one of these elements as a main component at a thickness of 100 to 300 nm. According to the present embodiment, an aluminum film containing 1 wt % of titanium is formed at 125 nm in thickness.

Moreover, by forming a 5 to 50 nm of insulating film such as a silicon oxide film and the like on top of the third interlayer insulating film159, the adhesion of the shielding film to be formed thereon can be raised. Further, by applying the plasma process using CF4gas on to a surface of the third interlayer insulating film159formed of inorganic resin, the adhesion of the shielding film to be formed on the film can be raised due to modification of the surface.

By employing the aluminum film containing titanium, not only can the shielding film be formed but other connection wiring can be formed also. For example, connection wiring for connecting circuits in a driving circuit can be formed. However, in this situation, it is necessary to open a contact hole in the third interlayer insulating film in advance before the deposition of the materials that form the shielding film or the connection wire.

Next, an oxide161is formed at 20 to 100 nm (preferably 30 to 50 nm) in thickness by anodic oxidation or plasma oxidation on the surface of the shielding film160(anodic oxidation in the present embodiment). According to the present embodiment, since a film mainly composed of aluminum is used as the shielding film160, an aluminum oxide film (alumina film) is formed as the anodic oxide film. (FIG. 11B) The anodic oxide161is formed on the surface of the shielding film160at about a thickness of 50 nm thereby the film thickness of the shielding film160becomes 90 nm. A user can appropriately set the numeric value that relates to the anodic oxidation method.

The process here was to employ anodic oxidation to form an insulating film provided only on the surface of the shielding film, though other gaseous methods such as plasma CVD, thermal CVD, or sputtering can be employed to form the insulating film. In that case preferably the film thickness be 20 to 100 nm (preferably 30 to 50 nm). Also, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, a DLC (Diamond like carbon) film, a tantalum oxide film or an organic resin film and further a combination of the above as a lamination film can be used as the insulating film.

Thereafter, a contact hole that goes through the third interlayer insulating film159and the passivation film158and reaches the drain wiring157is opened.

In the present embodiment, after forming a resist mask (not shown), by performing dry etching which uses mixed gas containing CF4and oxygen (O2), a contact hole that goes through the third interlayer insulating film (acrylic)159and the passivation film (silicon oxide nitride film)158is opened at the same time in one etching.

Furthermore, according to the present embodiment, the flow rate of CF4and the flow rate of O2was adjusted so that the ratio (selective ratio) of the etching rate of the third interlayer insulating film to the etching rate of the passivation film is 2:1. By doing this, a contact hole having a good shape can be opened as shown inFIGS. 5A and 5B.

Dry etching was performed when the flow rate of CF4was set at 50 sccm, the flow rate of O2at 50 sccm, the flow rate of He at 35 sccm, electric power of RF at 400 W, and gas pressure at 0.3 Torr.

Subsequently, a pixel electrode162is formed in the contact hole formed by the above process. A pixel electrode163is the pixel electrode of a neighboring different pixel. If the pixel electrodes162and163are to be transmission type liquid crystal display devices, a transparent conductive film is used. On the other hand, if they are to be reflection type liquid crystal display devices, a metallic film is used. Here the pixel electrodes are transmission type liquid crystal devices; therefore an indium tin oxide (ITO) film is formed to a thickness of 110 nm by sputtering. (FIG. 12A)

The pixel electrode162and the shielding film160overlap via the anodic oxide161to form a capacitance storage164at this time. In this case, it is desirable that the shielding film160be set at a floating state (in an electrically independent state) or at a fixed electric potential, preferably a common electric potential (inter-electric potential of image signals sent as data).

An active matrix substrate having a driving circuit and a pixel circuit on the same substrate is completed this way. As shown inFIG. 12A, a P channel TFT301and N channel TFTs302and303are formed in the driving circuit; a pixel TFT304formed of an N channel TFT is formed in the pixel circuit.

In the P channel TFT301of the driving circuit, a channel forming region201, a source region202, and a drain region203are respectively formed in the P-type impurity regions (a). However, strictly the source region202and the drain region203contain phosphorus at a concentration of 1×1016to 5×1018atoms/cm3.

Further, in the N channel TFT302, a channel forming region204, a source region205and a drain region206are formed. Also, a region207, which overlaps a gate wiring via a gate insulating film, is formed between the channel forming region and the drain region (the present invention calls this region “Lov” region, where “ov” refers to overlap). The Lov region207at this time contains phosphorus at a concentration of 2×1016to 5×1019atoms/cm3and is formed as to overlap the gate wiring completely.

Furthermore, in the N channel TFT303, a channel forming region208, a source region209and a drain region210are formed. Also, LDD regions211and212are formed in manner sandwiching the channel forming region. That is, an LDD region is formed between the source region and the channel forming region, and between the drain region and the channel forming region.

Since the LDD regions211and212are arranged so that a portion of the region overlaps with the gate wiring in this structure, via a gate insulating film, a region that overlaps with the gate wiring (Lov region) and a region that does not overlap with the gate wiring (the present invention calls this type of region “Loff region,”, “off” meaning offset) are realized.

The LDD region211can further be classified as an Lov region and an Loff region. The above Lov region contains phosphorus at a concentration of 2×1016to 5×1019atoms/cm3while the Loff region contains phosphorus at a concentration that is 1 to 2 times higher that the Lov region (typically, 1.2 to 1.5 times).

In the pixel TFT304, channel forming regions213and214, a source region215, a drain region216, Loff regions217through220, and an N-type impurity region (a)221that contacts with the Loff region218and219are formed. At this time, the source region215and the drain region216are respectively formed in the N-type impurity region (a) and the Loff regions217through220are formed in the N-type impurity region (c).

The present embodiment is able to improve the operating efficiency and reliability of a semiconductor device by optimizing the structure of TFTs which form each circuit to meet the circuit specifications demanded by pixel circuits and driving circuits. More specifically, N channel TFT can realize both a TFT structure attaining a high-speed operation or focusing on a hot carrier countermeasure and a TFT structure focusing on a low off current operation on the same substrate by making the arrangement of the LDD region different depending upon the circuit specifications and by distinguishing the Lov region from the Loff region.

Moreover, the width of the Lov region207of the N channel TFT302is 0.3 to 3.0 μm, typically. 0.5 to 1.5 μm, with respect to the 3 to 7 μm of channel length. The width of the Lov region and the Loff region of the N channel TFT can be 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, and 1.0 to 3.5 μm, typically 1.5 to 2.0 μm respectively. The width of the Loff regions217to220provided in the pixel TFT304can be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.

The present embodiment uses an alumina film that has a high 7 to 9 dielectric constant as the dielectric of capacitance storage, and therefore the occupying area that is necessary for the capacitance storage to form the necessary capacity can be reduced. Moreover, the opening rate (aperture ratio) of the image display portion of the active matrix liquid display device can be improved by making the shielding film, which is formed on the pixel TFT, as the other electrode of the capacitance storage as in the present embodiment.

The present invention is not necessarily limited to the structure of the capacitance storage indicated in the present embodiment. For example, a structure of a capacitance storage disclosed by the present applicant in Japanese Patent Application No. Hei 9-316567, Japanese Patent Application No. Hei 9-273444, or Japanese Patent Application No. Hei 10-254097 can be used.

A process of manufacturing an active matrix liquid crystal display from an active matrix substrate is described hereon. As shown inFIG. 12B, an orientated film401is formed on a substrate in the state shown inFIG. 12A. Apolyimide film is used as the orientated film in the present embodiment. Then a facing electrode (counter electrode)403, formed of transparent conductivity film, and an orientated film404are formed on a facing substrate (counter substrate)402. It is appropriate to form a color filter or a shielding film on the facing substrate (counter substrate) whenever it requires.

After forming the orientated film, a rubbing operation is performed to make adjustments so that the crystal molecules are orientated at a fixed pre-tilt angle. Then using a well-known cell assembling process, the counter substrate and the active matrix substrate formed of the pixel circuit and the driving circuit are stuck with sealing materials or a spacer (both not shown). Then, after injecting a liquid crystal405between the two substrates, the liquid crystal is completely sealed by a sealing agent (not shown). It is appropriate to use well-known liquid crystal material as the liquid crystal. The active matrix liquid crystal display device is completed in this way as shown in FIG.12B.

The structure of the active matrix liquid crystal display device will be described next with reference to the perspective view of FIG.13. It should be noted that the same reference numerals as that ofFIGS. 8 through 12are used inFIG. 13for correspondence. The active matrix substrate comprises a pixel circuit801, a scanning (gate) signal driving circuit802, and an image (source) signal driving circuit803, which are formed on the quarts substrate101. The pixel TFT304of the pixel circuit is an N channel TFT, and the driving circuit provided in the periphery is structured with a CMOS circuit as the basic circuit. The scanning signal driving circuit802and the image signal driving circuit803are connected to the pixel circuit801by the gate wiring128and source wiring154, respectively. Connecting wiring806and807are provided from an external input/output terminal805connected by a FPC804to the input/output terminal of the driving circuit.

Further, the illustration inFIG. 14is an example of a structure of a circuit of the active matrix liquid crystal display shown in FIG.13. The active matrix liquid crystal display device according to the present embodiment has an image signal driving circuit901, a scanning signal driving circuit (A)907, a scanning signal driving circuit (B)911, a pre-charge circuit912, and a pixel circuit906. According to the present invention, the image signal driving circuit901and the scanning signal driving circuit907are included in the driving circuit.

Furthermore, the structure of the present invention can be easily realized by manufacturing a TFT following the processes indicated inFIGS. 8 through 12. Although the present embodiment illustrates only the structure of a pixel circuit and a driving circuit, other signal operating circuits (or logic circuits) such as a signal division circuit, a frequency dividing circuit, a D/A converter circuit, an operational amplifier circuit, a γ correction circuit, and a microprocessor circuit as well can be formed on the same substrate according to the manufacturing method of the present invention.

In this way, the present invention can provide a semiconductor device that includes on the same substrate at least a pixel circuit and a driving circuit for controlling the pixel circuit. For example, a semiconductor device provided with a signal operating circuit, a driving circuit, and a pixel circuit all on the same substrate can be realized.

A crystalline silicon film that has unique crystal structures in which the crystal lattices have continuous characteristics is formed if the process according to the present embodiment is performed until FIG.9B. Details relating to this kind of crystalline silicon film can be referred by the present applicant in Japanese Patent Application No. Hei 10-044659, Japanese Patent Application No. Hei 10-152316, Japanese Patent Application No. Hei 10-152308, or Japanese Patent Application No.Hei 10-152305. Hereinafter, a characteristic of a crystal structure experimentally examined by the applicant is briefly explained. Besides, this characteristic coincides with the characteristic of the semiconductor layer in this embodiment which forms the active layer of the TFT.

The above crystalline silicon film has a crystal structure in which there are a plurality of needle like and rod like crystals (hereinafter abbreviated as rod-like crystal) collectively arranged as seen from a microscopic observation. This can be easily confirmed by observation through a TEM (transmission electron microscope).

Further, by utilizing electron beam diffraction and X-ray diffraction, it can be confirmed that the surface of the crystalline silicon film (the portion that forms a channel) has a {110} plane as the main orientation plane though the crystal axis is somewhat tilted. If an analysis was performed using the electron beam diffraction now, it can be confirmed that the diffraction spot, which corresponds to the {110} plane, will appear nicely. The fact that each spot has a concentric circle distribution can also be confirmed.

Furthermore, when the grain boundary formed by the connection of every rod-like crystal is observed through a HR-TEM (High Resolution-Transmission Electron Microscope), the crystal lattice of the grain boundary having continuity properties can be confirmed. This observation can be easily confirmed from the fact that the lattice stripes in the grain boundary being observed were continuously linked together.

Due to the continuity of the crystal lattices in the crystal grain boundary, the crystal grain boundary is called “plane-like grain boundary”. In the present invention, the definition of the plane-like grain boundary is “planar boundary disclosed in “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol. 27, No. 5, pp. 751-758, 1988

According to the above article, a twin grain boundary, an unique lamination defect, and an unique twist grain boundary are included as the plane-like grain boundary and this plane-like grain boundary has a characteristic of being electrically inactive. That is, although the plane-like grain boundary is a crystal grain boundary, it does not function as a trap to obstruct the movements of carriers. Thus, the plane-like grain boundary can be regarded as substantially non-existing.

Especially when the crystal axis (perpendicular axis to the crystal plane) is axis <110>, a {211} twin crystal grain boundary can also be called the corresponding grain boundary of the Σ3. The value of Σ3is a parameter, that is a pointer for indicating the degree of conformity of the corresponding grain boundary. The smaller the value of Σ, the better the conformity of the grain boundary is well known.

If the crystalline silicon film of the present embodiment is actually observed in detail under the TEM, almost all (above 90%, typically above 95%) of the crystal grain boundary are the Σ3of the corresponding grain boundary, typically the {211} twin crystal grain boundary.

It is known that the grain boundary formed between two crystal grains becomes the corresponding grain boundary of Σ3when the plane direction of the two crystals is {110} and the angle θ formed by a lattice stripe which corresponds to a {111} plane is θ=70.5°. Each lattice stripe of the crystal grains lined next to each other in the crystal grain boundary of the crystalline silicon film according the present embodiment is surely linked together at an angle about 70.5°. From this fact, it can be said that the crystal grain boundary is the corresponding grain boundary of Σ3.

Moreover, the crystal grain boundary becomes the corresponding grain boundary of Σ9when θ=38.9° meaning that other corresponding grain boundaries do exist. However, in any case, all are inactive.

Corresponding grain boundaries of this type are only formed between crystal grains of the same plane direction. That is, the plane direction of the crystalline silicon film of the present embodiment is substantially aligned at {110} which is why a wide range of this type of corresponding grain boundary can be formed.

This kind of crystal structure (precisely the structure of a crystal grain boundary) indicates that the joining of two different types of crystal grains in the crystal grain boundary is extremely conforming. That is, in the crystal grain boundary, the crystal lattices are linked together continuously and structured in such a way making it extremely difficult to form trap levels which are caused by crystal defects and the like. Hence, it can be regarded that crystal grain boundary substantially does not exist in a semiconductor thin film having this kind of crystal structure.

Furthermore, it has been confirmed from a TEM observation that almost all the defects existing inside a crystal grain are extinguished through a heat treatment process at a very high temperature of 800 to 1150° C. (corresponding to the thermal oxidation in embodiment 1). This is obvious since the number of defects has been largely lessened after thermal oxidation.

The difference in the number of defects will appear as the difference in spin density through an electron spin resonance analysis (ESR). The spin density of the crystalline silicon film according to the present embodiment in the present state has been identified as at least 5×1017spins/cm3or less (preferably 3×1017spins/cm3or less). However, this measured value is near the value that the present existing measurement device can limitedly detect. The actual spin density is expected to be lower.

From the above explanation, the defects inside a crystal grain of the crystalline silicon film according to the present embodiment are extremely small, and since it is proved that a crystal grain boundary substantially does not exists, it is appropriate to consider the crystalline silicon film as a single-crystal silicon film or a substantially single-crystal silicon film.

The present invention can be employed when an interlayer insulating film is formed on a conventional MOSFET and when forming a TFT thereon. That is, the realization of a three-dimensional structure semiconductor device is possible. Further, SOI substrates such as the SIMOX, the Smart-Cut (registered trademark of SOITEC), the ELTRAN (registered trademark of Canon Inc.), etc. can be used as a substrate.

Moreover, the structure of the present invention can be freely combined with any one of the structures in embodiment 1.

The present invention can be applied to an active matrix EL display of which an example is shown in FIG.15.

FIG. 15is a diagram showing a circuit of the active matrix EL display. In the figure, reference numeral81denotes a pixel circuit and provided around the circuit are an X-directional driving circuit82and a Y-directional driving circuit83. Each pixel in the pixel circuit81has a TFT switch84, a condenser85, an electric current control TFT86, and an organic EL element87. An X-directional signal line88a(or88b) and a Y-directional signal line89a(or89b) are connected to the TFT switch84. Power source lines90aand90bare connected to the electric current control TFT86.

When forming a contact hole in the active matrix EL display according to the present embodiment, etching is performed once to simultaneously form a lamination film by using the technique described in the present embodiment.

Furthermore, the structure in either embodiment 1 or 2 may be combined with respect to the active matrix EL display of the present embodiment.

A diversity of crystal liquid materials can be used in a liquid crystal display device manufactured by the present invention. As such materials, there are TN liquid crystal, PDLC (Polymer Distributed Liquid Crystal), FLC (Ferroelectric Liquid Crystal), AFLC (Antiferroelectric Liquid Crystal), or a mixture of FLC and AFLC (Antiferroelectric LCD).

Specifically, with respect to an electric field, as Thresholdless Antiferroelectric LCD (abbreviated as TL-AFLC) that indicates electro-optical response characteristic of continuously changing transmission rate, there is a type that indicates a V-shaped type (or U-shaped type) of electro-optical response characteristic. It has been proved that the drive voltage is approximately ±2.5 V (cell thickness is about 1 μm to 2 μm). Due to this fact, there are cases where the power voltage for pixel circuits is sufficient from 5 to 8 V and the possibility of operating the driving circuit and the pixel circuit at the same power source voltage has been suggested. That is, attempts can be made on the low consumption of electric power of the whole liquid display device.

Ferroelectric liquid crystals and antiferroelectric liquid crystals have an advantage of having a faster response velocity when compared with TN liquid crystals. For realizing TFTs like the TFT used in the present invention which has extremely rapid operational velocity, a liquid crystal display device having a fast image response velocity can be realized by sufficiently utilizing the speed of the response velocity of ferroelectric liquid crystals and antiferroelectric liquid crystals.

Generally, the voluntary polarization of the thresholdless antiferroelectric LCD is large and the dielectric constant high. For this reason, when utilizing the thresholdless ferroelectric liquid crystal in the liquid crystal display device, a comparatively bigger capacitance storage is needed for the pixel. Therefore, the utilization of a thresholdless antiferroelectric LCD of smaller voluntary polarization is preferred. In this sense, the capacitance storage shown inFIG. 8Aof embodiment 1 is preferable since this capacitance storage can accumulate a large capacity in a small area.

Needless to say, utilizing the liquid crystal display device of this embodiment as the display for electronic equipment such as a personal computer and the like is effective.

Moreover, the structure of this invention may be freely combined with a structure of any one of embodiments 1 to 3.

On account of improving the uniformity of the shape of a contact hole in this embodiment, an example different from an embodiment mode of carrying out the present invention is shown in FIG.16.

First, a first conductive film1601, a first insulating film1602, a thin second insulating film, and an organic resin film1604are formed one after another in laminations on a substrate1600. (FIG. 16A)

A silicon nitride film, a silicon oxide film, or a silicon oxide nitride film all of which at 100 to 400 nm in thickness can be used as the first insulating film. A 200 nm thickness of silicon oxide nitride film formed by plasma CVD using SiH4, N2O, and NH3as raw gas is used in this embodiment (however, nitrogen concentration is 25 to 50 atomic %).

Further, although a 30 nm thickness of silicon oxide film formed by plasma CVD is used in this embodiment as the second insulating film, other silicon oxide films with a 20 to 50 nm in thickness can be used.

Furthermore, the organic resin film is formed of a 1 μm of acrylic resin film that is formed in laminations by the coating method.

After achieving the state inFIG. 16A, a resist mask1605is formed by photolithography and then the lamination film of the laminated first insulating film1602and the organic resin film1604are simultaneously etched one time to form a contact hole. (FIG. 16B) This etching is dry etching using etchant gas, which is mixed gas containing at least oxygen and fluorine-based gas. In this embodiment, dry etching was conducted with the flow rate of CF4set at 50 sccm, flow rate of O2at 50 sccm, flow rate of He at 35 sccm, electric power of RF at 400 W, and gas pressure at 0.3 Torr.

Subsequently, after removing the resist mask1605, the second conductive film1606is formed and electrically connected to the first conductive film1606. (FIG. 16C)

Compared with the etching rate of the organic resin film1604and the first insulating film1602, the second insulating film1603with a slower etching rate has been chosen in this embodiment. Since the film thickness of the second insulating film1603is thin, removal is accomplished without changing the conditions. By using this type of second insulating film, there are no longer any etched remains of organic resin and a contact hold with little dispersion in its shape can be formed.

This embodiment can be freely combined with any one of embodiments 1 to 4.

An example of an EL (electroluminescence) display device manufactured by employing the present invention is described in this embodiment.FIG. 18Ais a top sectional view andFIG. 18Bis a cross-sectional view of the EL display device of the present invention.

InFIG. 18A, reference numeral4001denotes a substrate,4002a pixel portion,4003a source side driving circuit, and4004a gate side driving circuit. The respective driving circuits are connected to an external equipment by a wiring4005through an FPC (flexible print circuit)4006.

A first sealing material4101, a covering material4102, a filling material4103, and a second sealing material4104are provided in a manner surrounding the pixel portion4002, the source side driving circuit4003, and the gate side driving circuit4004during this time.

Further,FIG. 18Bis a cross-sectional view taken along a line A-A′ of FIG.18A. In this figure, a drive TFT4201included in the source side driving circuit (an N channel TFT and a P channel TFT are shown here) and an electric current control TFT4202(TFT for controlling the electric current flowing to the EL device) included in the pixel portion4002are formed on the substrate4001.

A TFT of the same structure as that of the P channel TFT or N channel TFT ofFIG. 12is utilized for the drive TFT4201and a TFT of the same structure as that of the P channel TFT ofFIG. 12is utilized for the electric current control TFT4202in this embodiment. Also, a capacitance storage (not shown), which is connected to the gate of the electric current control TFT4202, is provided in the pixel portion4002.

An interlayer insulating film4301(flattened film) formed of resin material is formed on the drive TFT4201and the pixel TFT4202and a pixel electrode (anode)4302, electrically connected to the drain of the pixel TFT4202. A transparent conductive film with a large working function is used as a pixel electrode4302. A compound of oxide indium and oxide tin, or a compound of oxide indium and oxide zinc can be used for a transparent conductive film. A transparent conductive film doped with gallium can also be used as the above transparent conductive film.

Thereafter, an insulating film4303is formed on the pixel electrode4302, then an opening portion is formed on the top of the pixel electrode4302and an EL (electroluminescence) layer4304is formed in the opening portion on the insulating film4303. Well-known materials or inorganic EL materials can be used as the EL layer4304. Additionally, either monomer based materials or polymer materials can be used as the organic EL materials.

It is appropriate to employ the well-known evaporation technique or the coating technique as the method for forming the EL layer4304. This EL layer4303may be structured as a lamination structure or a single layer structure by freely combining an electron hole implant layer, an electron hole conveyance layer, a luminescent layer, an electron conveyance layer, and an electron implant layer.

A cathode4305formed of a conductive film having shielding characteristics (typically a conductive film mainly composed of aluminum, copper, or silver or a lamination film of these materials and another conductive film), is formed on the EL layer4304. It is desirable that the moisture and oxygen existing in the interface of the cathode4305and EL layer4304be eliminated as much as possible. Therefore, the formation of the cathode4305and the EL layer4304needs contriving, that is, to form both of them both continuously in a vacuum or to form the EL layer4304in an atmosphere containing nitrogen or inert gas and form the cathode4305without exposure to moisture and oxygen. By employing a multi-chamber system (cluster tool system) of a film-forming device, this embodiment is able to form a film as described above.

Thereafter, the cathode4305is electrically connected to the wiring4005in the region indicated by reference numeral4306. The wiring4005is a wiring for applying a predetermined voltage to the cathode4305, and thus the cathode4305is electrically connected to the FPC4006via an anisotropy conductive film4307.

The EL device (element) made up of the pixel electrode (anode)4304, the EL layer4303, and the cathode4305is formed in the way described above. This EL device (element) is wrapped by the first sealing material4101and the covering material4102which is stuck to the substrate4001by the first sealing material4101, and then the EL device (element) is encapsulated by the filling material4103.

As the covering material4102, materials such as glass, metal (typically stainless), ceramic, and plastic (including plastic film) can be used. Materials such as an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used as plastic materials. Also, a sheet structured with an aluminum foil sandwiched in a PVF film or a mylar film can be used.

However, if light from the EL device (element) radiates in the direction of the covering material, the covering material must be transparent. In that case, transparent materials such as a sheet of glass, a sheet of plastic, polyester film, or acrylic film should be used.

Furthermore, an ultraviolet cure resin or a thermal cure resin can be use as the filling material4103, and additionally, PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) may be used. By providing a hygroscopic material (preferably oxide barium) or a substance that absorbs oxygen inside the filling material4103, deterioration of the EL device (element) can be restrained.

A spacer may be included in the filling material4103. The spacer can be hygroscopic when formed with oxide barium during this time. In the case of providing a spacer, disposing a resin film that acts as a buffer layer to ease the pressure from the spacer on the cathode4305is effective.

The wiring4005is electrically connected to the FPC4006via the anisotropy conductive film4307. Signals transmitted to the pixel portion4002, the source side driving circuit4003, and the gate side driving circuit4004are conveyed by the wiring4005to the FPC4006which electrically connects the EL device (element) to an external equipment.

Moreover, this embodiment provides a second sealing material4104so as to cover an exposing portion of the first sealing material4101and a portion of the FPC4006resulting into a structure that completely shuts the EL device (element) from the open air. Through this process, the EL device (element) has a structure as shown in the cross-sectional view of FIG.18B.

In this embodiment, an example of a pixel structure that can be utilized in the pixel portion of the EL display device illustrated in embodiment 6 or embodiment 8 is described with reference toFIGS. 19Ato19C. According to this embodiment, reference numerals4601denotes a source wiring of a switching TFT4602,4603denotes a gate wiring of the switching TFT4602,4604denotes an electric current control TFT,4605denotes a condenser (capacitor),4606and4608denote electric current supple wiring, and finally4607denotes an EL device (element).

FIG. 19Ais a diagram showing an example of which the electric current supple wiring4606is commonly provided for two pixels. That is, the characteristic structure is that the two pixels are formed in a linearly symmetrical manner with the electric current supply wiring4606as a center. In this situation, since the number of lines in the electric current supply wiring can be lessened, a higher fining of the pixel portion can further be achieved.

Further,FIG. 19Bis a diagram showing an example of which the electric current supply wiring4608is provided parallel to the gate wiring4603. In this figure, though the structure is that of the electric current supply wiring4608and the gate wiring4603being provided so as not to overlap each other, they can be set in an overlapping manner via an insulating film provided that both wiring are formed in different layers. Since the electric current supply wiring4608and the gate wiring4603are made to share an exclusive area in this situation, a higher fining of the pixel portion can further be achieved.

Further, similar to the structure ofFIG. 19B,FIG. 19Cshows the characteristic structure in which the electric current supply wiring4608is provided parallel to the gate wiring4603and further two pixels are formed in a linearly symmetric manner with the electric current supply wiring4606as a center. Moreover, providing the electric current supply wiring and the gate wiring4603in a manner where whichever one overlaps the other is effective. In this situation, since the number of lines in the electric current supply wiring is lessened, a higher fining of the pixel portion can further be achieved.

According to this embodiment,FIGS. 20A and 20Bshow an example of a pixel structure of an EL display device implementing the present invention. In this embodiment, reference numerals4701denotes a source wiring of a switching TFT4702,4703denotes a gate wiring of the switching TFT4702,4704denotes an electric current control TFT,4705denotes a condenser (capacitor) which can be omitted,4706denotes an electric current supply wiring,4707denotes a power source control TFT,4709denotes a gate wiring for power source control, and finally4708denotes an EL device. The operations of the power source control TFT4707can be referred in Japanese Patent Application No. Hei 11-321272.

In this embodiment, the power source control TFT4707is provided between the electric current control TFT4704and the EL element4708though the electric current control TFT4704may be provided between the power source control TFT4707and the EL element4708. Also, the power source control TFT4707and the electric current control TFT4704can be of the same structure; however these are desirably formed in series on the same active layer.

Further,FIG. 20Ais a diagram showing an example of which the electric current supple wiring4706is commonly provided for two pixels. That is, the characteristic structure is that the two pixels are formed in a linearly symmetrical manner with the electric current supply wiring4706as a center. In this situation, since the number of lines in the electric current supply wiring can be lessened, a higher fining of the pixel portion can further be achieved.

Furthermore,FIG. 20Bis a diagram showing an example of which an electric current supply wiring4710is provided parallel to the gate wiring4703and a power source control gate wiring4711is provided parallel to the source wiring4701. In this figure, though the structure is that the electric current supply wiring4710and the gate wiring4703is provided so as not to overlap each other, they can be set in an overlapping manner via an insulating film provided that both wiring are formed in different layers. Since the structure of this embodiment is able to make the electric current supply wiring4710and the gate wiring4703share an exclusive area in this situation, a higher fining of the pixel portion can further be achieved.

According to this embodiment,FIGS. 21A and 21Bshow an example of a pixel structure of an EL display device implementing the present invention. In this embodiment, reference numerals4801denotes a source wiring of a switching TFT4802,4803denotes a gate wiring of the switching TFT4802,4804denotes an electric current control TFT,4805denotes a condenser (capacitor) which can be omitted,4806denotes an electric current supply wiring,4807denotes an elimination TFT,4808denotes elimination gate wiring, and finally4809denotes an EL device (element). The operations of the elimination TFT4807can be referred in Japanese Patent Application No. Hei 11-338786.

The drain of the elimination TFT4807is connected to the gate of the electric current control TFT4804, and the structure in this embodiment is able to forcibly change the gate voltage of the electric current control TFT4804. Moreover, the elimination TFT4807can be an N channel TFT or a P channel TFT though it is preferred that the elimination TFT4807be of the same structure as that of the switching TFT4802in order to make the off current smaller.

Further,FIG. 21Ais a diagram showing an example of which the electric current supple wiring4806is commonly provided for two pixels. That is, the characteristic structure is that the two pixels are formed in a linearly symmetrical manner with the electric current supply wiring4806as a center. In this situation, since the number of lines in the electric current supply wiring can be lessened, a higher fining of the pixel portion can further be achieved.

Furthermore,FIG. 21Bis a diagram showing an example of which an electric current supply wiring4810is provided parallel to the gate wiring4803and an elimination gate wiring4811is provided parallel to the source wiring4801. In this figure, though the structure is that the electric current supply wiring4810and the gate wiring4803are provided so as not to overlap each other, they can be set in an overlapping manner via an insulating film provided that both wirings are formed in different layers. Since the structure in this embodiment is able to make the electric current supply wiring4810and the gate wiring4803share an exclusive area in this situation, a higher fining of the pixel portion can further be achieved.

The EL display device according to the present invention can be so structured that the pixel may include any number of TFTs. For example, four to six or more TFTs can be provided. Implementation of the present invention is possible without being limited to the pixel structure of the EL display device.

A CMOS circuit and a pixel matrix circuit formed through carrying out the present invention may be applied to various display devices (active matrix type liquid crystal displays, active matrix type EL displays, active matrix type EC displays). Namely, the present invention may be embodied in all the electronic equipments that incorporate those display devices into display units.

As such an electronic equipment, a video camera, a digital camera, a projector (rear-type or front-type projector), a head mount display (goggle-type display), a navigation system for vehicles, a stereo for vehicles, a personal computer, and a portable information terminal (a mobile computer, a cellular phone, or an electronic book, etc.) may be enumerated. Examples of those are shown inFIGS. 22Ato24C.

FIG. 22Ashows a personal computer comprising a main body2001, an image inputting unit2002, a display unit2003, and a key board2004and the like. The present invention is applicable to the image inputting unit2002, the display unit2003, and other signal control circuits.

FIG. 22Bshows a video camera comprising a main body2101, a display unit2102, a voice input unit2103, operation switches2104, a battery2105, and an image receiving unit2106and the like. The present invention is applicable to the display unit2102and other signal control circuits.

FIG. 22Cshows a mobile computer comprising a main body2201, a camera unit2202, an image receiving unit2203, an operation switch2204, and a display unit2205and the like. The present invention is applicable to the display unit2205and other signal control circuits.

FIG. 22Dshows a goggle-type display comprising a main body2301, a display unit2302and arm portions2303and the like. The present invention is applicable to the display unit2302and other signal control circuits.

FIG. 22Eshows a player that employs a recoding medium in which programs are recorded (hereinafter referred to as recording medium), and comprises a main body2401, a display unit2402, a speaker unit2403, a recording medium2404, and an operation switch2405and the like. Incidentally, this player uses as the recoding medium a DVD (digital versatile disc), a CD and the like to serve as a tool for enjoying music or movies, for playing video games and for connecting to the Internet. The present invention is applicable to the display unit2402and other signal control circuits.

FIG. 22Fshows a digital camera comprising a main body2501, a display unit2502, an eye piece section2503, operation switches2504, and an image receiving unit (not shown) and the like. The present invention is applicable to the display unit2502and other signal control circuits.

FIG. 23Ashows a front-type projector comprising a projection device2601, a screen2602and the like. The present invention is applicable to a liquid crystal display device2808that constitutes a part of the projection device2601and other signal control circuits.

FIG. 23Bshows a rear-type projector comprising a main body2701, a projection device2702, a mirror2703, and a screen2704and the like. The present invention is applicable to the liquid crystal display device2808that constitutes a part of the projection device2702and other signal control circuits.

FIG. 23Cis a diagram showing an example of the structure of the projection devices2601and2702inFIGS. 23A and 23B. The projection device2601or2702comprises a light source optical system2801, mirrors2802and2804to2806, dichroic mirrors2803, a prism2807, liquid crystal display devices2808, phase difference plates2809, and a projection optical system2810. The projection optical system2810consists of an optical system including a projection lens. This embodiment shows an example of “three plate type”, but not particularly limited thereto. For instance, the invention may be applied also to “single plate type”. Further, in the light path indicated by an arrow inFIG. 23C, an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference and an IR film may be provided on discretion of a person who carries out the invention.

FIG. 23Dis a diagram showing an example of the structure of the light source optical system2801in FIG.23C. In this embodiment, the light source optical system2801comprises a reflector2811, light source2812, lens arrays2813and2814, a polarization conversion element2815, and a condenser lens2816. The light source optical system shown inFIG. 23Dis an example thereof, and is not particularly limited. For instance, on discretion of a person who carries out the invention, the light source optical system may be provided with an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference and an IR film.

The projector shown inFIG. 23shows the case in which the display device of transmission type is employed and an application example using the electro-optical device of reflective type and the EL display device is not illustrated.

FIG. 24Ais a cellular phone that is composed of a main body2901, a voice output unit2902, a voice input unit2903, a display unit2904, operation switches2905, and an antenna2906and the like. The present invention can be applied to the voice output unit2902, the voice input unit2903and the display unit2904and other signal control circuits.

FIG. 24Bshows a portable book (electronic book) that is comprised of a main body3001, display units3002and3003, a memory medium3004, an operation switch3005and an antenna3006and the like. The present invention can be applied to the display units3002and3003and other signal circuits.

FIG. 24Cshows a display that is comprised of a main body3101, a support base3102and a display unit3103and the like. The present invention can be applied to the display unit3103. The display according to the present invention is advantageous in the case where the display is particularly large-sized and in the case where the display is 10 inches or more in diagonal (particularly 30 inches or more).

As described above, the present invention has so wide application range that it is applicable to electronic equipments in any field. In addition, the electronic equipments of this embodiment may be realized with any construction obtained by combining Embodiments 1 to 10.

By employing the present invention, a contact hole can be formed by simultaneously performing etching once on a lamination film (a lamination film of an inorganic insulating film and an organic resin film) of different material and film thickness; hence the number of processes can be decreased.

Further, the operating efficiency and the reliability of a semiconductor device can be improved by providing a contact hole that is uniform in shape, and moreover an appropriate one.

Furthermore, the yield of an active matrix type liquid crystal display device can be improved by forming a pixel electrode of good coverage. In addition, since a fine contact hole can be formed, a detailed fining of every TFT is possible.