Data encoding and decoding within PRML class IV sampling data detection channel of disk drive

A serializer/deserializer encoder-decoder for a disk drive achieves increased storage capacity through the use of partial response maximum likelihood class IV (PRML-IV) coding. Reduction of hardware requirements is realized by the integration of similar read and write mode functions into common circuit elements in order to reduce duplication. To this end, a data word selector selectively receives or sends data words in the write/read mode, respectively, from a data sequencer. Dependent upon the mode the data words are either provided to an encoder or received from a decoder for translation to/from code words. The encoder-decoder sends or receives the code words to a code word selector which in turn connects with the serializer-deserializer for coupling with the write or read channel.

REFERENCE TO RELATED APPLICATION 
The present invention is related to U.S. patent application Ser. No. 
07/937,064 filed on the same date as the application resulting in this 
patent and entitled DISK DRIVE USING PRML

SYSTEM OVERVIEW 
With reference to FIG. 4, an exemplary high performance, high data 
capacity, low cost disk drive 10 incorporating a programmable and adaptive 
PR4,ML write/read channel in accordance with the principles of the present 
invention includes e.g. a head and disk assembly ("HDA") 12 and at least 
one electronics circuit board (PCB) 14. The HDA 12 may follow a wide 
variety of embodiments and sizes. One example of a suitable HDA is given 
in commonly assigned U.S. Pat. No. 5,027,241. Another suitable HDA is 
described in commonly assigned U.S. Pat. No. 4,669,004. Yet another 
suitable HDA is described in commonly assigned U.S. Pat. No. 5,084,791. 
Yet another HDA arrangement is illustrated in commonly assigned, copending 
U.S. patent application Ser. No. 07/881,678, filed on May 12, 1992, and 
entitled "Hard Disk Drive Architecture". The disclosures of these patents 
and this application are incorporated herein by reference thereto. 
The electronics PCB 14 physically supports and electrically connects the 
circuitry for an intelligent interface disk drive subsystem, such as the 
drive 10. The electronics circuitry contained on the PCB 14 includes an 
analog PR4, ML read/write channel application-specific integrated circuit 
(ASIC) 15, a digital PR4, ML read/write channel ASIC 17, a data sequencer 
and cache buffer controller 19, a cache buffer memory array 21, a high 
level interface controller 23 implementing a bus level interface 
structure, such as SCSI II target, for communications over a bus 25 with a 
SCSI II host initiator adapter within a host computing machine (not 
shown). A micro-controller 56 includes a micro-bus control structure 58 
for controlling operations of the sequencer 19, interface 23, a servo loop 
24, a spindle motor controller 27, a programmable analog filter/equalizer 
40, adaptive FIR filter 48, Viterbi detector 50, and a digital timing 
control 54 as well as a digital gain control 64. The micro-controller 56 
is provided with direct access to the DRAM memory 21 via the 
sequencer/memory controller 19 and may also include on-board and outboard 
read only program memory, as may be required or desired. 
The printed circuit board 14 also carries circuitry related to the head 
positioner servo 24 including e.g. a separate microprogrammed digital 
signal processor (DSP) for controlling head position based upon detected 
actual head position information supplied by a servo peak detection 
portion of the PR4,ML read channel and desired head position supplied by 
the microcontroller 56. The spindle motor control circuitry 27 is provided 
for controlling the disk spindle motor 18 which rotates the disk or disks 
16 at a desired angular velocity. 
The HDA 12 includes at least one data storage disk 16. The disk 16 is 
rotated at a predetermined constant angular velocity by a speed-regulated 
spindle motor 18 controlled by spindle motor control/driver circuitry 27. 
An e.g. in-line data transducer head stack assembly 20 is positioned e.g. 
by a rotary voice coil actuator 22 which is controlled by the head 
position servo loop circuitry 24. As is conventional, a data transducer 
head 26 of the head stack assembly 20 is associated in a "flying" 
relationship over a disk surface of each disk 16. The head stack assembly 
20 thus positions e.g. thin film data transducer heads 26 relative to 
selected ones of a multiplicity of concentric data storage tracks 71 
defined on each storage surface of the rotating disk 16. While thin film 
heads are presently preferred, improvements in disk drive performance are 
also realized when other types of heads are employed in the disclosed PR4, 
ML data channel, such as MiG heads or magnetoresistive heads, for example. 
The heads 16 are positioned in unison with each movement of the actuator 
and head stack assembly 20, and the resulting vertically aligned, circular 
data track locations are frequently referred to as "cylinders" in the disk 
drive art. The storage disk may be an aluminum alloy or glass disk which 
has been e.g. sputter-deposited with a suitable multi-layer magnetic thin 
film and a protecting carbon overcoat in conventional fashion, for 
example. Other disks and magnetic media may be employed, including plated 
media and or spin-coated oxide media, as has been conventional in drives 
having lower data storage capacities and prime costs. 
A head select/read channel preamplifier 28 is preferably included within 
the HDA 12 in close proximity to the thin film heads 26 to reduce noise 
pickup. As is conventional, the preamplifier 28 is preferably mounted to, 
and connected by, a thin flexible plastic printed circuit substrate. A 
portion of the flexible plastic substrate extends exteriorly of the HDA 12 
to provide electrical signal connections with the circuitry carried on the 
PCB 14. Alternatively, and equally preferably, the preamplifier 28 may be 
connected to the other circuitry illustrated in FIG. 4 exteriorly of the 
HDA 12 in an arrangement as described in the referenced copending U.S. 
patent application Ser. No. 07/881,678, filed on May 12, 1992, and 
entitled "Hard Disk Drive Architecture". 
A bidirectional user data path 30 connects the digital integrated circuit 
17 with the data sequencer and memory controller 19. The data path 30 from 
the sequencer 19 enters an encoder/decoder ("ENDEC") 32 which also 
functions as a serializer/deserializer ("SERDES"). In this preferred 
embodiment, the ENDEC 32 converts the binary digital byte stream into 
coded data sequences in accordance with a predetermined data coding 
format, such as (0,4,4) code. This coded serial data stream is then 
delivered over a path 33 to a precoder 34 which precodes the data in 
accordance with the PR4 precoding algorithm 1/(1.sym.D.sup.2). The 
precoded data is then passed over a path 35 to a write driver circuit 36 
within the analog IC 15 wherein it is amplified and precompensated by a 
write precompensation circuit 774 and is then delivered via a head select 
function within the circuit 28 to the selected data transducer head 26. 
The head 26 writes the data as a pattern of alternating flux transitions 
within a selected data track 71 of a block 72 of data tracks defined on a 
selected data storage surface of the disk 16, see FIGS. 5 and 6. Embedded 
servo patterns are written by a servo writer, preferably in accordance 
with the methods described in a commonly assigned U.S. patent application 
Ser. No. 07/569,065 filed on Aug. 17, 1990, entitled "Edge Servo For Disk 
Drive Head positioner, now U.S. Pat. No. 5,170,299, the disclosure thereof 
being hereby incorporated by reference. 
Returning to FIG. 4, during playback, flux transitions sensed by the e.g. 
thin film data transducer head 26 as it flies in close proximity over the 
selected data track 71 are preamplified by the read preamplifier circuit 
28. The preamplified analog signal (or "read signal") is then sent to the 
analog IC 15 on a path 29 and into an analog variable gain amplifier (VGA) 
37, a fixed gain amplifier 38, and a second VGA 39. After controlled 
amplification, the read signal is then passed through a programmable 
analog filter/equalizer stage 40. During non-read times, an analog 
automatic gain control circuit 42 feeds an error voltage to a control 
input of the VGA 37 over a control path 43. During read times, a digital 
gain control value from a digital gain control circuit 64 is converted 
into an analog value by a gain DAC 66 and applied over a path to control 
the second VGA 39, while the analog error voltage on the path 43 is held 
constant. 
The analog filter/equalizer 40 is programmed so that it is optimized for 
the data transfer rate of the selected data zone 70 from within which the 
transducer head 26 is reading data. The equalized analog read signal is 
then subjected to sampling and quantization within a high speed flash 
analog to digital (A/D) converter 46 which, when synchronized to user 
data, generates raw data samples {x.sub.k }. 
The FIR filter 48 employs adaptive filter coefficients for filtering and 
conditioning the raw data samples {x.sub.k } in accordance with the 
desired PR4 channel response characteristics, as plotted in FIG. 1, in 
order to produce filtered and conditioned samples {y.sub.k }. The bandpass 
filtered and conditioned data samples {y.sub.k } leaving the filter 48 are 
then passed over a path 49 to the Viterbi detector 50 which detects the 
data stream, based upon the Viterbi maximum likelihood algorithm employing 
a lattice pipeline structure implementing a trellis state decoder of the 
type illustrated in FIG. 3, for example. At this stage, the decoded data 
put out on a path 96 is in accordance with a (0,6,5) coding convention. A 
postcoder 52 receives the (0,6,5) coded data stream and restores the 
original (0,4,4) coding convention to the decoded data. The restored 
(0,4,4) coded data stream is decoded from the (0,4,4) code and 
deserialized by the ENDEC/SERDES 32 which frames and puts out eight bit 
user bytes which then pass into the sequencer 19 over the data path 30. 
In order for the present system to work properly, the raw data samples {xk} 
must be taken on the incoming analog signal waveform at precisely proper, 
regular locations. A dual mode timing loop is provided to control the 
frequency and phase of the flash analog to digital converter 46. The 
timing loop includes an analog timing control circuit 60, and a digital 
timing control circuit 54 and a timing DAC 57. A timing phase locked 
synthesizer circuit 262 supplies synthesized timing signals to the control 
circuit 60 and a timing reference signal to a summing junction 58. A sum 
put out by the summing junction 58 controls a current controlled 
oscillator 62 in order to clock the A/D 46. The oscillator 62 also 
includes zero phase start circuitry to provide controlled startup at an 
approximately correct phase with the incoming data samples. 
In order to achieve full utilization of the flash A/D 46, a dual mode gain 
loop is also provided. The gain loop includes the analog gain control 
circuit 42 which controls the first VGA 37, and a digital gain control 
circuit 64 and the gain DAC 66 which controls the second VGA 39. 
Data Recording Pattern 
As shown in FIG. 5, an exemplary data storage surface of a storage disk 16 
comprises a multiplicity of concentric data tracks 71 which are preferably 
arranged in a plurality of data recording zones 70 between an inner 
landing zone area LZ and a radially outermost peripheral data track zone 
70-1. In the illustrated example, the data tracks are shown as arranged 
into e.g. nine data zones including the outermost zone 70-1, and radially 
inward zones 70-2, 70-3, 70-4, 70-5, 70-6, 70-7, 70-8 and 70-9, for 
example. In practice, more zones, such as 16 zones, are presently 
preferred. Each data zone has a bit transfer rate selected to optimize 
areal transition domain densities for the particular radius of the zone. 
Since the number of available magnetic storage domains varies directly as 
a function of disk radius, the tracks of the outermost zone 70-1 will be 
expected to contain considerably more user data than can be contained in 
the tracks located at the innermost zone 70-9. The number of data fields, 
and the data flux change rate will remain the same within each data zone, 
and will be selected as a function of radial displacement from the axis of 
rotation of the storage disk 16. 
FIG. 5 also depicts a series of radially extending embedded servo sectors 
68 which e.g. are equally spaced around the circumference of the disk 16. 
As shown in FIG. 6, each servo sector includes a servo preamble field 68A, 
a servo identification field 68B and a field 68C of circumferentially 
staggered, radially offset, constant frequency servo bursts, for example. 
In addition to data fields 76 which store user data information and error 
correction code syndrome remainder values, for example, each data track 
has certain overhead information such as the FIG. 6 data block header 
fields 74, and data block ID fields 78. While the number of data sectors 
per track varies from data zone to data zone, in the present example, the 
number of embedded servo sectors 68 per track remains constant throughout 
the surface area of the disk 16. In this present example the servo sectors 
68 extend radially and are circumferentially equally spaced apart 
throughout the extent of the storage surface of the disk 16 so that the 
data transducer head 26 samples the embedded servo sectors 68 while 
reading any of the concentric tracks defined on the data storage surface. 
Also, the information recorded in the servo ID field 68B of each servo 
sector 68 is e.g. prerecorded with servowriting apparatus at the factory 
at a predetermined relative low constant frequency, so that the servo 
information will be reliable at the innermost track location, e.g. within 
the innermost zone 70-9. While regular servo sectors are presently 
preferred, a pattern of servo sectors aligned with data sectors and 
therefore unique within each data zone 70 is also within the contemplation 
of the present invention. Such a pattern is illustrated in U.S. Pat. No. 
4,016,603, to Ottesen, for example, the disclosure thereof being hereby 
incorporated by reference. 
Each data sector is of a predetermined fixed storage capacity or length 
(e.g. 512 bytes of user data per data sector); and, the density and data 
rates vary from data zone to data zone. Accordingly, it is intuitively 
apparent that the servo sectors 68 interrupt and split up at least some of 
the data sectors or fields into segments, and this is in fact the case in 
the present example. The servo sectors 68 are preferably recorded at a 
single data cell rate and with phase coherency from track to track with a 
conventional servo writing apparatus at the factory. A laser servo writer 
and head arm fixture suitable for use with the servo writer are described 
in commonly assigned U.S. Pat. No. 4,920,442, the disclosure of which is 
hereby incorporated herein by reference. A presently preferred servo 
sector pattern is described in the referenced, copending U.S. patent 
application Ser. No. 07/569,065. 
As shown in FIG. 6, a data track 71 includes a data block 76 for storage of 
a predetermined amount of user data, such as 512 or 1024 bytes of user 
data, recorded serially in 0,4,4 code bits in data field segments 76A, 76B 
and 76C of the depicted track segment. The data block 76 is shown in FIG. 
6 to be interrupted and divided into segments of unequal length by several 
servo sectors 68 which contain embedded servo information providing head 
position information to the disk drive 10. Each data block 76 includes a 
block ID header field 74 at the beginning of the data block and a data ID 
header field 78 immediately preceding each data field segment including 
the segment 76A following the ID header 74, and the segments 76B and 76C 
following interruption by servo sectors 68. The data header field 78 is 
written at the same time that data is written to the segments 76A, 76B and 
76C for example, and write splice gaps therefore exist just before each 
data ID header 78, before ID fields, and before servo fields, for example. 
ENDEC/SERDES 32 
The ENDEC/SERDES 32 is a combination of two acronyms: 
ENDEC=encoder/decoder; and SERDES=serializer/deserializer. The 
endec/serdes 32 combines two necessary functions: encoding and decoding 
eight bit user data bytes into and from nine-bit code words, thereby 
achieving the desired 8/9ths coding arrangement of the 0,4,4 PR4,ML 
channel; and, serializing and deserializing the 9-bit code words for 
serial recording onto, and from serial playback from, the selected data 
block on a disk storage surface 16. 
Encoder/Decoder 
Those skilled in the art will appreciate that there are 256 eight-bit byte 
combinations, and there are 279 possible nine-bit code word combinations 
which maintain the (0,4,4) code integrity. If M represents the eight-bit 
universe of bytes, and N represents the nine-bit universe of code words, a 
suitable mapping algorithm may be employed to map between M and N. In one 
preferred example 110 characters are mapped by directly transferring the 
eight bit M value and adding a zero at the 9th (MSB) position. 59 other 
characters are mapped by directly transferring the eight bit M values and 
adding a one at the 9th (MSB) position. 47 characters are mapped as the 
two's complement of the eight bit M value and adding a one at the 9th 
(MSB) position. The remaining 39 characters are mapped by a table lookup 
arrangement. In this arrangement two sync values are written at the 
beginning of the data block during encode, and are decoded during decode. 
The following Verilog program sets forth the logical equations needed to 
carry out the encoder mapping described herein. In this program, the 
following conventions are employed: "b" means binary; "o" means octal; "h" 
means hexadecimal; "!=" means not equal; "==" means equal; "&" means 
logical AND, and ".about." means total bit inversion. 
______________________________________ 
`define c1 {encin [7:6]} 
`define c2 {encin [2:0]} 
`define c3 {encin [4], encin [2], encin [0]} 
`define c4 {encin [7], encin [5], encin [3]} 
`define c5 {encin [5:1]} 
`define c6 {encin [6:2]} 
`define c7 {encin [6], encin [4]} 
`define c8 {encin [5], encin [3], encin [1]} 
`define c9 {encin [7:3]} 
* / 
begin 
/ * 
if (syncdata) 
begin 
$display ("This is in endec block syncdata %h", syncdata); 
encout = {encin{7:1],1'b1,encin[0]}; 
end 
else 
begin 
* / 
encout [8] = !syncdata & !case1; 
encout [7] = bit 7 encin [7]; 
encout [6] = bit 6 encin [6]; 
encout [5] = bit 5 encin [ 5]; 
encout [4] = bit 4 encin [4]; 
encout [3] = bit 3 encin [3]; 
encout [2] = bit 2 encin [2]; 
encout [1] = bit 1 encin [1]; 
encout [0] = bit 0 encin [0]; 
/ * 
encout = {1'b1, encin}; 
case (encin) // synopsys parallel.sub.-- case 
8'h00: encout [7:0] = 8'hf2; 
8'h07: encout [7:0] = 8'hf1; 
8'h15: encout [7:4] = 4'he; 
8'h17: encout [7:0] = 8'hf4; 
8'h2a: encout [7:0] = 8'hd9; 
8'h47: encout [3:0] = 4'hd; 
8'h50: encout [7:0] = 8'h63; 
8'h51: encout [3:0] = 4'h9; 
8'h52: encout [3:0] = 4'ha; 
8'h53: encout [3:0] = 4'hb; 
8'h54: encout [3:0] = 4'hc; 
8'h55: encout [7:0] = 8'h6c; 
8'h56: encout [3:0] = 4'he; 
8'h57: encout [7:0] = 8'h6d; 
8'h58: encout [7:0] = 8'h66; 
8'h6a: encout [3:0] = 4'h9; 
8'h70: encout [3:0] = 4'h3; 
8'h78: encout [3:0] = 8'h6; 
8'h95: encout [3:0] = 4'hc; 
8'ha8: encout [7:0] = 8'h96; 
8'haa: encout [7:0] = 8'h99; 
8'hb8: encout [3:0] = 4'h6; 
8'hc0: encout [3:0] = 4'h3; 
8'hc1: encout [3:0] = 4'hb; 
8'hc2: encout [3:0] = 4'hd; 
8'hc4: encout [3:0] = 4'he; 
8'hc5: encout [3:0] = 4'hc; 
8'hc8: encout [3:0] = 4'h6; 
8'hea: encout [3:0] = 4'h9; 
8'hd0: encout [3:0] = 4'h3; 
8'hd1: encout [3:0] = 4'hb; 
8'hd4: encout [3:0] = 4'he; 
8'hd5: encout [3:0] = 4'hc; 
8'hd8: encout [3:0] = 4'h6; 
8'he0: encout [3:0] = 4'h3; 
8'he8: encout [3:0] = 4'h6; 
8'hea: encout [3:0] = 4'h1; 
8'hf0: encout [3:0] = 4'h3; 
8'hf8: encout [3:0] = 4'h6; 
default: begin 
if (`c1 != 2'b00 & `c2 != 3'o0 & `c3 != 3'o0 & `c4 !=3'o0 & 
`c5 != 5'h00 &`c6 ! = 5'h00 & `c7 != 2'o0 & 
`c8 != 3'o0) 
encout[8] = 1`b0; 
else begin 
if (!((`c1 == 2'b00 .vertline. `c7 == 2'b00) & `c2 != 3'o0 & 
`c3 != 3'o0 & `c4 != 3' o0 & `c5 != 5'h00 & 
`c6 != 5"h00 & `c8 != 3'o0 & `c9 != 5'h00)) 
encout = .about.encin; 
end 
______________________________________ 
The decoder operates in accordance with an inverse of the logic described 
by the foregoing logic equations. With this arrangement the entire logical 
structure required for implementing the foregoing logic equations 
comprises approximately 150 gates of an application-specific integrated 
circuit. Other, less preferred approaches require upwards of 400 gates or 
more to carry out the encoding and decoding function. 
Serdes 
Turning now to FIG. 7, the ENDEC/SERDES 32 receives serial data during read 
mode from the postcoder 52 via a serial data path 53. This coded serial 
data read back from the disk surface is passed through a multiplexer 682 
and into a first bit position D0 of a nine-bit shift-right shift register 
686. The incoming coded data bits are then clocked to the right within the 
shift register 686 by the BITCLK clock signal on a path 45. The shift 
register 686 is operated by a load-shift control signal LDSHFTN in which a 
logical high condition signals a parallel load operation and a logical low 
condition signals a serial shift operation. The LDSHFTN control is put out 
by a load-shift gate 687 which selects between load and shift control 
modes in accordance with a signal generated by the digital IC controller. 
During a data read sequence, once a nine-bit code word is framed in the 
shift register 686, it is fed onto a nine bit code word bus 688. 
The nine-bit code word on the path 688 passes through a selector 690 and is 
then clocked into a nine-bit register 692 by a BYTECLK signal. In order to 
preclude a race between the BITCLK clock signal on the path 45 and the 
BYTECLK clock signal on a path 689, during read mode, the BYTECLK clock 
signal transitions true (rising edge) upon a falling edge of the BITCLK 
clock phase during a ninth bit cycle thereof. This is so that the latch 
register 692 is written after the ninth bit has arrived in the shift 
register 686 and before the first bit of the next code word comes in. 
The code word values held in the register 692 are then clocked out over a 
bus 694 to a decoder 696 at the BYTECLK clock rate. The decoder 696 
decodes the code words into eight bit data bytes in accordance with an 
inverse of e.g. the N to M mapping scheme described above in connection 
with the encoder 710. The decoder 696 puts out decoded eight-bit data 
bytes over a path 697 to a multiplexer 698 which passes the bytes to a 
register 700 during read mode. 
The register 700, clocked by the BYTECLK signal on the path 689, puts out 
the data bytes over a path 702 and through e.g. an eight bit to two bit 
data buffer 704 which is provided to minimize the number of external pin 
connections of the digital IC 17. The outgoing two bit groups are then 
sent onto the two-bit bidirectional data path 30 leading into the 
sequencer 19, where they are formatted and checked for error correction, 
etc., and sent onto the buffer 21 for delivery to the interface 23 and 
host computing environment via the bus 25. 
During data writing operations, a different signal path is followed. Eight 
bit data bytes to be written to disk enter the ENDEC/SERDES 32 as two-bit 
groups via the bus 30 and are passed through the buffer 704 to a path 708 
leading to and through the multiplexer 698 and to the register 700. These 
bytes are then clocked out to the encoder 710 over the bus 702 in 
accordance with the BYTECLK signal on the path 689. The bytes on the path 
702 entering the encoder 710 are mapped into nine-bit code words in 
accordance with the N to M mapping scheme described above. 
In order to provide a sync field immediately following each data write 
splice, a control SYNCDATAN on a path 711 is provided to control the 
operation of the encoder 710. If SYNCDATAN is equal to one, the data 
preamble sync field 78 is to be written. In one preferred example, the 
sequencer 19 will put out eight bytes. The first six bytes will be data 
words FF(Hex). The seventh byte will be 02 (Hex) and the eighth byte will 
be 07 (Hex). During this sync field interval, the SYNCDATA value will be 
true, indicating that the sync field pattern is to be written as a 
sinewave burst, and that no encoding is to be performed, i.e. a 
1,1111,1111 nine-bit code pattern for each of the first six bytes is to be 
written. During this time period, the encoder 710 merely appends an 
additional 1 bit to the eight 1 bit values of each byte to come up with a 
string of nine 1s for each code word. The seventh data byte becomes 
encoded to 0 0000 0110, and the eight byte becomes encoded to 0 0000 
1111, for example. 
A sync/data gate 706 monitors the output data stream from the encoder 710 
and detects the pattern of the eighth byte. When this detection occurs, 
the SYNCDATA control changes from high to low, signifying that a data 
pattern is now to be encoded, and the encoder 710 is enabled to operate 
normally in encoding the data bytes into nine bit code words in accordance 
with the predetermined coding arrangement as described above implemented 
within the encoder 710. 
The nine bits put out from the encoder 710 are selected through the 
selector 690 and loaded into the latch register 692. These bits are then 
clocked out to the bus 694 by the BYTECLK signal on the path 689 and are 
then loaded in parallel into the nine positions of the shift register 686 
in accordance with the LOSHFTN control from the load/shift gate 687, and 
clocked out serially over the path 33 to the precoder 34 in accordance 
with the BITCLK signal 
As was true during read mode, during write mode the BYTECLK clock signal is 
phase-adjusted with respect to the BITCLK clock signal in order to prevent 
a race between shift operations of the shift register 686 and parallel 
load operations. During write mode, the BYTECLK clock signal transitions 
true (rising edge) when the BITCLK clock signal transitions false (falling 
edge) within a data bit one clock cycle. This assures that a parallel load 
operation is carried out after the last (ninth) bit of the last code word 
has been shifted out of the shift register 686. 
The four-input multiplexer 698 includes two additional inputs: one 
comprising a pseudo-random sequence preload value from the register file 
of the digital chip 17, and another from the pseudo-random sequence 
generator 258. These additional inputs are used during FIR filter 
coefficients training mode. The generator 258, implemented in hardware on 
the digital chip 17, receives an output on the path 702 from the register 
700 and modifies the output recursively in accordance with its rules of 
operation and supplies the output to the fourth input of the multiplexer. 
FIR filter training using the present circuit arrangement is described in 
the U.S. patent application referred to at the beginning of this 
application Ser. No. 07/937,064. 
Precoder 34 
FIG. 8 sets forth the precoder in greater detail. The data to be written to 
disk put out on the path 33 is passed through an exclusive OR function 
714. The resultant value BK0 is passed through a multiplexer 716 to a 
first register 718. The signal BK1 put out from the first register 718 is 
then passed through a second multiplexer 720 to a second register 722. The 
signal BK2 put out from the second register 722 is also provided as an 
input to the exclusive OR gate 714. The registers 718 and 722 are cleared 
by a clear command on a path 724. Two precoder preset values PRCVAL0 and 
PRCVAL1 from the register file 804 are preloaded into the registers 718 
and 722 by an initialization signal on a path 726. As illustrated, the 
precoder 34 precodes the code word data into the desired function 
(1/1.sym.D.sup.2). 
Postcoder 52 
The postcoder 52 is shown structurally in FIG. 9. Decoded code word 
patterns from the Viterbi detector 50 enter the postcoder 52 via a path 
96. In the postcoder 52, the serial values are latched into a first 
register 728 which provides an output value RK1. This value is then passed 
through a second register 730 which provides a second output value RK2. 
The RK2 value, together with the incoming value on the path 96 are 
compared in an exclusive OR function 732 with a result put out as 
postcoded decoded nine-bit code words to the ENDEC/SERDES 32 over the path 
53. The postcoder thus decodes the played back code word stream in 
accordance with the desired function (1.sym.D.sup.2) which restores the 
desired 8/9ths code to the code words before they are decoded in the 
ENDEC/SERDES 32 and put out to the sequencer 19 as user data bytes. 
Having thus described an embodiment of the invention, it will now be 
appreciated that the objects of the invention have been fully achieved, 
and it will be understood by those skilled in the art that many changes in 
construction and widely differing embodiments and applications of the 
invention will suggest themselves without departing from the spirit and 
scope of the invention. The disclosure and the description herein are 
purely illustrative and are not intended to be in any sense limiting.