SEMICONDUCTOR DEVICE

A semiconductor device includes a chip having a principal surface, a trench insulating structure formed in the principal surface of the chip, a first conductivity type body region formed in a surface layer portion of the principal surface such that the body region is in contact with the trench insulating structure, a second conductivity type source region formed in a surface layer portion of the body region while being separated from the trench insulating structure, a first conductivity type butting region formed in a region between the trench insulating structure and the source region in the surface layer portion of the body region, and a planar gate structure that passes through a side of the butting region, covers the body region and the trench insulating structure, and is capable of controlling reversal and non-reversal of a channel in the body region.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND ART

For example, Patent Literature 1 (Japanese Translation of International Application No. 2005-510080) discloses a method of restricting formation of a divot of a shallow trench isolation (STI) structure. The method of Patent Literature 1 includes a step of providing oxide deposited on a trench which is formed in a silicon region, a step of oxidizing an upper layer of the silicon region and forming a thermal oxide layer in an upper surface of the silicon region, and a step of selectively etching the oxide on which the thermal oxide is deposited.

DESCRIPTION OF EMBODIMENTS

Next, a preferred embodiment of the present disclosure will be described in detail with reference to the attached drawings.

FIG.1is a schematic plan view of a semiconductor device1according to a preferred embodiment of the present disclosure.FIG.2is an enlarged view of a region surrounded by a double chain line II inFIG.1.FIG.3is a cross-sectional view taken along line III-III inFIG.2.FIG.4is a cross-sectional view taken along line IV-IV inFIG.2.FIG.5is a cross-sectional view taken along line V-V inFIG.2.FIG.6is a cross-sectional view taken along line VI-VI inFIG.2.FIG.7is an enlarged view of a part surrounded by a double chain line VII inFIG.6.

The semiconductor device1includes a rectangular-parallelepiped semiconductor chip2. In this preferred embodiment, the semiconductor chip2is formed by an Si (silicon) chip. The semiconductor chip2has a first principal surface3on one side, a second principal surface4on the other side, and first to fourth side surfaces5A to5D that connect the first principal surface3and the second principal surface4.

The first principal surface3and the second principal surface4are formed in a square shape in a plan view seen from the normal direction Z of the principal surfaces (hereinafter, simply referred to as “in a plan view”). The normal direction Z is also the thickness direction of the semiconductor chip2. The first side surface5A and the second side surface5B extend in the first direction X (horizontal direction) along the first principal surface3, and oppose each other in the second direction Y (horizontal direction) crossing (specifically, orthogonal to) the first direction X. The third side surface5C and the fourth side surface5D extend in the second direction Y and oppose each other in the first direction X.

The semiconductor device1includes a p-type region6(first conductivity type region) and an n-type region7(second conductivity type region) formed in the semiconductor chip2.

The p-type region6is formed in a surface layer portion of the second principal surface4of the semiconductor chip2. The p-type region6is formed over the entire surface layer portion of the second principal surface4, and exposed from the second principal surface4and the first to fourth side surfaces5A to5D. A p-type impurity concentration of the p-type region6may be, for example, not less than 1.0×1013cm−3and not more than 1.0×1015cm−3. A thickness of the p-type region6may be not less than 100 μm and not more than 500 μm. In this preferred embodiment, the p-type region6may be formed by a p-type semiconductor substrate. It is noted that since having a relatively low impurity concentration, the p-type region6may also be called as the p−-type region.

The n-type region7is formed in a surface layer portion of the first principal surface3of the semiconductor chip2. In this preferred embodiment, the n-type region7is in direct contact with the p-type region6. An n-type impurity concentration of the n-type region7may be, for example, not less than 1.0×1014cm−3and not more than 1.0×1016cm−3. The n-type region7is formed over the entire surface layer portion of the first principal surface3, and exposed from the first principal surface3and the first to fourth side surfaces5A to5D. A thickness of the n-type region7is, for example, smaller than the thickness of the p-type region6. The thickness of the n-type region7may be not less than 5 μm and not more than 20 μm. In this preferred embodiment, the n-type region7may be formed by an n-type epitaxial layer. It is noted that since having a relatively low impurity concentration, the n-type region7may also be called as the n−-type region.

The semiconductor device1includes a plurality of element regions8provided in the first principal surface3(n-type region7). The plurality of element regions8are regions in which various functional elements are respectively formed. The plurality of element regions8are respectively partitioned in an inner side portion of the first principal surface3at an interval from the first to fourth side surfaces5A to5D in a plan view. The number, arrangement, and shape of the element regions8are arbitrary, and are not limited to the particular number, arrangement, and shape.

The plurality of functional elements may respectively include at least one of a semiconductor switching element, a semiconductor rectifying element, and a passive element. The semiconductor switching element may include at least one of a junction field effect transistor (JFET), a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), and an insulated gate bipolar junction transistor (IGBT).

The semiconductor rectifying element may include at least one of a pn-junction diode, a pin-junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive element may include at least one of a resistance, a capacitor, an inductor, and a fuse. In this preferred embodiment, the plurality of element regions8include at least one transistor region9. Hereinafter, a structure on the transistor region9side will be specifically described.

In the transistor region9, the semiconductor device1may include an element separation portion10, an embedded layer11, a trench insulating structure12, a body region13, source regions14, butting regions15, a drift region16, a drain region17, a back gate region18, a back gate contact region19, and a planar gate structure20.

The element separation portion10may include element separation wells21,22. More specifically, the p-type element separation wells21,22formed in a band shape, the element separation wells that draw a closed curve in a plan view as illustrated inFIG.2may reach the p-type region6from the first principal surface3of the semiconductor chip2. In this preferred embodiment, the element separation portion10is formed in a square ring shape in a plan view as illustrated inFIG.2, but may have, for example, other closed curve structures of a circular ring shape, a triangular ring shape, etc.

The element separation portion10may have a double layer structure of a p+-type well region21disposed on the upper side, and a−-type low isolation (L/I) region22disposed on the lower side. A border between these regions may be set in an intermediate portion in the thickness direction of the n-type region7. For example, the border between the regions may be set at a depth position of 1.0 μm to 2.0 μm from the first principal surface3of the semiconductor chip2. Thereby, in the semiconductor chip2, the transistor region9formed by part of the n-type region7which is surrounded by the element separation portion10on the p-type region6is partitioned.

The n+-type embedded layer11(B/L) is selectively formed in the transistor region9. With reference toFIGS.3to6, the embedded layer11goes across a border between the p-type region6and the n-type region7in the semiconductor chip2. A thickness of the embedded layer11may be, for example, 2.0 μm to 3.0 μm.

In this preferred embodiment, the trench insulating structure12includes a trench23formed in the n-type region7, and an embedded insulating body24embedded in the trench23.

The trench23has a side surface25and a bottom surface26. The side surface25of the trench23may be a surface orthogonal to the first principal surface3, or may be a surface inclined with respect to the first principal surface3as illustrated inFIGS.3to6. The trench23may have a tapered shape whose width is gradually narrowed from the first principal surface3toward the bottom surface26in the third direction Z in a cross-sectional view.

The embedded insulating body24may be, for example, silicon oxide (SiO2), silicon nitride (SiN), etc. In this preferred embodiment, the embedded insulating body24is made of silicon oxide. The embedded insulating body24exposes an opening end27of the trench23. Also, the trench insulating structure12may also be called as a shallow trench isolation (STI) as a general name.

In this preferred embodiment, the trench insulating structure12may include a plurality of trench insulating structures12. The plurality of trench insulating structures12may include a first trench insulating structure28and a second trench insulating structure29. InFIG.2, a region of the trench insulating structure12is hatched.

With reference toFIG.2, the first trench insulating structure28is formed in an outer peripheral portion of the transistor region9such that the first trench insulating structure28overlaps with the element separation portion10in a plan view. In this preferred embodiment, the first trench insulating structure28is formed in a square ring shape in a plan view as illustrated inFIG.2, but may have, for example, other closed curve structures of a circular ring shape, a triangular ring shape, etc.

The second trench insulating structure29is formed at an interval inward from an inner peripheral edge of the first trench insulating structure28. The second trench insulating structure29is physically separated from the first trench insulating structure28. With reference toFIG.2, the second trench insulating structure29is surrounded by the first trench insulating structure28. The second trench insulating structure29has a first opening30and a second opening31. Inner peripheral edges of the first opening30and the second opening31may be the opening end27of the trench23described above.

With reference toFIG.2, the first opening30is formed in a rectangular shape in a plan view elongated along the second direction Y. The second opening31includes a pair of second openings31that sandwich the first opening30in the first direction X. Each second opening31is formed in a rectangular shape in a plan view elongated along the second direction Y. The second trench insulating structure29includes a ring-shaped outer peripheral portion32that surrounds the first opening30and the second opening31, and a coupling portion33that couples a plurality of points of the outer peripheral portion32and forms a border between the first opening30and the second opening31. The coupling portion33includes a pair of coupling portions33formed on both the sides of the first opening30in the first direction X.

The body region13is formed in a surface layer portion of the n-type region7and electrically connected to the n-type region7. The body region13is formed in an inner region of the first opening30at an interval from the second trench insulating structure29. With reference toFIGS.3and4, the body region13is physically separated inward from an inner peripheral edge of the first opening30in the first direction X. With reference toFIGS.5and6, the body region13extends in the second direction Y, and is in contact with the second trench insulating structure29in both end portions of the first opening30in the second direction Y. With reference toFIGS.5and6, the body region13has an overlap portion34that projects to the outer side of the inner peripheral edge of the first opening30and overlaps with the second trench insulating structure29in the second direction Y. The overlap portion34gets into under the second trench insulating structure29, and is in contact with a bottom portion of the second trench insulating structure29(the bottom surface26of the trench23). In this preferred embodiment, the body region13is a p-type semiconductor region. The body region13has an impurity concentration of 1×1017cm−3to 1×1018cm−3, for example. Also, a depth of the body region13is deeper than a bottom portion position of the trench insulating structure12, and may be, for example, 0.5 μm to 4.0 μm.

The source regions14and the butting regions15are formed in a surface layer portion of the body region13and electrically connected to the body region13. Since the butting region15is a region of the same conductivity type as the body region13, the region being connected to the body region13, the butting region15may also be called as a body contact region. With reference toFIGS.3and4, the source regions14and the butting regions15are physically separated inward from an outer peripheral edge of the body region13and formed in an inner region of the body region13in the first direction X. Regions sandwiched between the outer peripheral edge of the body region13and outer peripheral edges of the source regions14and configured by the body region13are channel regions35in which channels are formed when an appropriate voltage is applied to the planar gate structure20.

With reference toFIGS.2,5, and6, the plurality of source regions14and the plurality of butting regions15are formed alternately along the second direction Y. The source region14and the butting region15adjacent to each other are in contact with each other. In this preferred embodiment, the butting regions15are formed in regions between the second trench insulating structure29and the source regions14in the second direction Y. More specifically, the butting regions15include first butting regions36and a second butting region37.

The first butting regions36are formed on the outer side of the source regions14and sandwiched between the outer peripheral portion32of the second trench insulating structure29and the source regions14in the second direction Y. Thereby, the first butting regions36are in contact with the second trench insulating structure29. In this preferred embodiment, the first butting regions36are formed one by one in each of both the end portions of the first opening30(a first end portion38and a second end portion39of the body region13) in the second direction Y, and cover the opening end27of the trench23from the side. Since the first butting regions36are formed on the outer side of the source regions14, the first butting regions36may also be called as outside butting regions. With reference toFIG.2, the first butting regions36are formed in a square shape in a plan view.

The second butting region37is sandwiched by the pair of source regions14in the second direction Y. In this preferred embodiment, only one second butting region37is formed in a central portion40of the body region13in the second direction Y. However, a plurality of second butting regions37may be formed. Since the second butting region37is formed on the inner side of the source regions14, the second butting region37may also be called as an inside butting region. With reference toFIG.2, the second butting region37is formed in a square shape in a plan view. The second butting region37has a planar area larger than the first butting regions36.

The source regions14are formed in regions of the body region13exposed from the first opening30, the regions excluding the butting regions15. The source region14is formed between the pair of adjacent butting regions15and sandwiched between the pair of butting regions15in the second direction Y. In this preferred embodiment, the source regions14are n+-type semiconductor regions. The source regions14have an impurity concentration of 1×1019cm−3to 5×1021cm−3, for example. Also, a depth of the source regions14is shallower than the body region13and the trench insulating structure12, and may be, for example, 0.2 μm to 1.0 μm. Therefore, in a cross-sectional view, side portions and bottom portions of the source regions14are integrally covered by the body region13in the first direction X (seeFIG.3).

In this preferred embodiment, the butting regions15are p+-type semiconductor regions and have an impurity concentration higher than the body region13. The butting regions15have an impurity concentration of 1×1019cm−3to 5×1021cm−3, for example. Also, a depth of the butting regions15is shallower than the body region13and the trench insulating structure12, and may be, for example, 0.2 μm to 1.0 μm. Therefore, in a cross-sectional view, side portions and bottom portions of the butting regions15are integrally covered by the body region13in the first direction X (seeFIG.4).

The drift region16is formed in the surface layer portion of the n-type region7and electrically connected to the n-type region7. The drift region16goes across the first opening30and the second opening31of the second trench insulating structure29, and exposed from both the first opening30and the second opening31. The drift region16extends along the body region13in the second direction Y, and is in contact with the second trench insulating structure29in both the end portions of the first opening30in the second direction Y. Also, the drift region16may be in contact with the body region13in the second opening31.

With reference toFIGS.3and4, the drift region16has an overlap portion41that projects to the outer side of an inner peripheral edge of the second opening31and overlaps with the second trench insulating structure29in the first direction X. The overlap portion41gets into under the second trench insulating structure29, and is in contact with the bottom portion of the second trench insulating structure29(the bottom surface26of the trench23). In this preferred embodiment, the drift region16is an n-type semiconductor region and has an impurity concentration higher than the n-type region7. The drift region16has an impurity concentration of 1×1017cm−3to 1×1018cm−3, for example. Also, a depth of the drift region16is deeper than the bottom portion position of the trench insulating structure12, and may be, for example, 0.5 μm to 4.0 μm.

The drain region17is formed in a surface layer portion of the drift region16and electrically connected to the drift region16. The drain region17is separated from the body region13in the first direction X and exposed from the second opening31of the second trench insulating structure29. The drain region17is formed in a rectangular shape in a plan view extending along the longitudinal direction of the second opening31. The drain region17may include a pair of drain regions17that oppose each other across the source regions14in the first direction X. In this preferred embodiment, the drain region17is an n+-type semiconductor region and has an impurity concentration higher than the drift region16. The drain region17has an impurity concentration of 1×1019cm−3to 5×1021cm−3, for example. Also, a depth of the drain region17may be, for example, 0.2 μm to 2.0 μm. For example, the drain region17may have the same depth as the source regions14.

The back gate region18is a region formed by the n-type region7in the transistor region9. The back gate region18is exposed from a third opening42between the first trench insulating structure28and the second trench insulating structure29. The back gate region18has an exposed part that surrounds the second trench insulating structure29.

The back gate contact region19is formed in a surface layer portion of the back gate region18and electrically connected to the back gate region18. The back gate contact region19is separated from the body region13and the drift region16and exposed from the third opening42. The back gate contact region19is formed in a square ring shape in a plan view extending along the third opening42. In this preferred embodiment, the back gate region18is an n+-type semiconductor region and has an impurity concentration higher than the n-type region7. The back gate region18has an impurity concentration of 1×1019cm−3to 5×1021cm−3, for example. Also, a depth of the back gate region18may be, for example, 0.2 μm to 2.0 μm. For example, the back gate region18may have the same depth as the source regions14and the drain region17.

The planar gate structure20is formed on the first principal surface3and covers the channel regions35. The planar gate structure20integrally includes a main body portion43that controls ON/OFF of the channel regions35, and contact portions44that receive supply of a voltage.

With reference toFIGS.2to4, the main body portion43includes a pair of main body portions43that oppose the pair of channel regions35formed on both the sides of the source regions14in the first direction X. The pair of main body portions43extend across a plurality of borders between the source regions14and the butting regions15along the second direction Y. The pair of main body portions43are parallel to each other along the second direction Y. The pair of main body portions43cover both end portions of the source regions14and the butting regions15in the first direction X. The pair of main body portions43are formed in a rectangular shape in a plan view elongated along the second direction Y and have both end portions on the second trench insulating structure29.

The contact portions44are formed on the second trench insulating structure29and connected to the main body portion43on the second trench insulating structure29. Each one of the contact portions44is formed in both longitudinal end portions of the pair of main body portions43. The contact portions44are formed in a rectangular shape in a plan view elongated along the direction going across the pair of main body portions43(direction along the first direction X). Thereby, the planar gate structure20is formed in a substantially square ring shape in a plan view as illustrated inFIG.2, and has a gate opening45in a central portion thereof. The gate opening45is formed in a rectangular shape in a plan view, and the butting regions15and the source regions14are alternately exposed along the longitudinal direction thereof. Both longitudinal ends of the gate opening45are formed on the second trench insulating structure29.

The planar gate structure20includes a gate insulating film46and a gate electrode47laminated in this order from the first principal surface3side. The gate insulating film46may include a silicon oxide film. The gate insulating film46preferably includes a silicon oxide film made of oxide of the semiconductor chip2. The gate electrode47preferably includes conductive polysilicon. The gate electrode47preferably includes conductive polysilicon to which an impurity is introduced. The gate electrode47may have a conductivity type of a p-type or may have a conductivity type of an n-type. A side wall48is formed in a periphery of the gate electrode47. The side wall48is continuously formed over the entire periphery of the gate electrode47and covers a side surface of the gate electrode47. The side wall48may be, for example, silicon oxide (SiO2), silicon nitride (SiN), etc.

With reference toFIGS.3to6, an interlayer insulating film49is formed on the first principal surface3and covers the planar gate structure20. The interlayer insulating film49is made of silicon oxide, for example. A plurality of wirings50to53are formed on the interlayer insulating film49. The plurality of wirings50to53may include a source wiring50, a drain wiring51, a back gate wiring52, and a gate wiring53, respectively.

The source wiring50is connected to the source regions14and the butting regions15via a source contact54embedded in the interlayer insulating film49. With reference toFIG.2, the source contact54may be formed in a rectangular shape in a plan view extending along the longitudinal direction of the first opening30. The source contact54goes across the borders between the source regions14and the butting regions15in the second direction Y and is collectively connected to the source regions14and the butting regions15.

The drain wiring51is connected to the drain region17via a drain contact55embedded in the interlayer insulating film49. With reference toFIG.2, the drain contact55may be formed in a rectangular shape in a plan view extending along the longitudinal direction of the second opening31.

The back gate wiring52is connected to the back gate contact region19via back gate contacts56embedded in the interlayer insulating film49. With reference toFIG.2, the plurality of back gate contacts56are disposed at intervals along the circumferential direction of the third opening42.

The gate wiring53is connected to the gate electrode47(contact portion44) via gate contacts57embedded in the interlayer insulating film49. With reference toFIG.2, the plurality of gate contacts57are disposed at intervals along the longitudinal direction of the contact portion44.

With reference toFIG.7, a cross-sectional structure of the first end portion38and the second end portion39in the second direction Y of the body region13will be described in detail. AlthoughFIG.7illustrates a structure in the first end portion38among the first end portion38and the second end portion39of the body region13as an example, the structure of the first end portion38can also be applied to the second end portion39. A dent58is selectively formed in the embedded insulating body24of the second trench insulating structure29in the vicinity of the first end portion38of the body region13. The dent58is a dent58generated due to cleaning processing (such as light etching with a hydrofluoric acid solution), etc., performed each time before a thermal oxidation process for forming the gate insulating film46, and may also be called as a divot. This dent58may be continuously formed over the entire periphery of the body region13such that the dent58surrounds the body region13.

The gate insulating film46covers the opening end27of the trench23such that the gate insulating film46is connected to the embedded insulating body24in this dent58. The gate electrode47covers the dent58of the embedded insulating body24and may include an embedded portion60embedded in the dent58. In a part of the dent58, a remarkable thin film portion59is generated in the gate insulating film46. For example, a thickness T1of the gate insulating film46in the central portion40in the second direction Y of the body region13(part between the first end portion38and the second end portion39) is not less than 50 Å and not more than 250 Å, and a thickness T2of the thin film portion59is smaller than the thickness T1of the central portion40. This thin film portion59becomes a cause of leakage, and invites a decrease in a withstand voltage of the gate insulating film46. Also, since this thin film portion59partially forms a region of a low threshold value, the thin film portion59invites deterioration of static characteristics (such as instability of a threshold value) of a transistor.

Therefore, in this preferred embodiment, a structure in which the deterioration of the static characteristics is not generated is provided. More specifically, the butting regions15are formed in end cap parts of the body region13(in this preferred embodiment, the first end portion38and the second end portion39). The butting regions15are regions that ensure conduction with respect to the body region13and do not relate to transistor actions. Therefore, at the time of applying a gate voltage, it is possible to suppress formation of channels in the first end portion38and the second end portion39of the body region13in contact with the thin film portion59of the gate insulating film46, and preferentially and stably form a channel in the central portion40of the body region13. As a result, it is possible to suppress a hump phenomenon from generating in a drain current-gate voltage (Ids-Vgs) characteristic.

For example, the graph ofFIG.8is a graph respectively illustrating relationships between gate voltages applied to Samples 1 and 2 and drain currents flowing through transistors of Samples 1 and 2. Sample 1 is the semiconductor device1according to this preferred embodiment, and Sample 2 is a semiconductor device1in which the first butting regions36are not disposed in the semiconductor device1. From comparison between the graph of Sample 1 and the graph of Sample 2, it is found that a hump waveform is suppressed in Sample 1.

Although the preferred embodiment of the present disclosure has been described, the present disclosure can also be implemented in other preferred embodiments.

For example, the example in which the first conductivity type is the p-type and the second conductivity type is the n-type is described in the preferred embodiment described above. However, the first conductivity type may be the n-type and the second conductivity type may be the p-type. A specific arrangement of this case can be obtained by replacing the n-type regions with the p-type regions and replacing the p-type regions with the n-type regions in the above description and the attached drawings. In the preferred embodiment described above, the example in which the p-type is expressed as the “first conductivity type” and the n-type is expressed as the “second conductivity type” is described. However, these are used for clarifying the order of description. The p-type may be expressed as the “second conductivity type,” and the n-type may be expressed as the “first conductivity type.”

As described above, the preferred embodiments of the present disclosure are examples in all points, should not be interpreted in a limited manner, and intend to include changes in all points.

The following appended features can be extracted from the descriptions in this Description and the drawings.

A semiconductor device, including a chip having a principal surface, a trench insulating structure formed in the principal surface of the chip, a first conductivity type body region formed in a surface layer portion of the principal surface such that the body region is in contact with the trench insulating structure, a second conductivity type source region formed in a surface layer portion of the body region while being separated from the trench insulating structure, a first conductivity type butting region formed in a region between the trench insulating structure and the source region in the surface layer portion of the body region, and a planar gate structure that passes through a side of the butting region, covers the body region and the trench insulating structure, and is capable of controlling reversal and non-reversal of a channel in the body region.

The semiconductor device according to Appendix 1-1, wherein the butting region has an impurity concentration higher than the body region.

The semiconductor device according to Appendix 1-1 or 1-2, wherein the butting region is formed in the surface layer portion of the body region such that the butting region is in contact with the trench insulating structure.

The semiconductor device according to any one of Appendices 1-1 to 1-3, wherein the planar gate structure has a part that covers the butting region.

The semiconductor device according to any one of Appendices 1-1 to 1-4, further including at least one first conductivity type inside butting region formed in the surface layer portion of the body region while being separated from the trench insulating structure.

The semiconductor device according to Appendix 1-5, wherein a planar area of the inside butting region is larger than a planar area of the butting region.

The semiconductor device according to any one of Appendices 1-1 to 1-6, wherein the trench insulating structure includes a trench formed in the principal surface, and an insulating body embedded in the principal surface such that the insulating body exposes an opening end of the trench, and the planar gate structure includes a gate insulating film that covers the body region and the opening end, and a gate electrode that opposes the body region and the opening end across the gate insulating film.

The semiconductor device according to Appendix 1-7, wherein the trench insulating structure has a divot dented toward a bottom wall of the trench so that the opening end of the trench is exposed in an upper end portion of the insulating body, and the gate insulating film covers the opening end such that the gate insulating film is connected to the insulating body in the divot.

The semiconductor device according to Appendix 1-7 or 1-8, wherein the butting region covers the opening end in the body region.

The semiconductor device according to any one of Appendices 1-1 to 1-9, further including a second conductivity type drain region formed in the surface layer portion of the principal surface while being separated from the body region.

The semiconductor device according to Appendix 1-10, further including a second conductivity type drift region formed in a region different from the body region in the surface layer portion of the principal surface, wherein the drain region is formed in a surface layer portion of the drift region.

The semiconductor device according to Appendix 1-11, wherein the drain region has an impurity concentration higher than the drift region.