Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems

Providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems is disclosed. In this regard, in one aspect, a processor-based system provides a partitioned resource (such as a system cache or memory access bandwidth to a shared system memory) that is subdivided into a plurality of partitions, and that is configured to service a plurality of resource clients. A resource allocation agent of the processor-based system provides a plurality of allocation indicators corresponding to each combination of resource client and partition, and indicating an allocation of each partition for each resource client. The resource allocation agent allocates the partitioned resource among the resource clients based on an interpolation of the plurality of allocation indicators. Because each allocation indicator may be different for each combination of resource client and partition, interpolation of the allocation indicators provides a higher-resolution aggregate resource allocation for each resource client.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to partitioned resources in processor-based systems, and, in particular, to Quality of Service (QoS) mechanisms for partitioned resources.

Conventional processor-based systems provide resources, such as system caches and/or memory access bandwidth, which may be shared among multiple resource clients. To increase parallelism, a resource may be subdivided into partitions that may be operated and/or accessed largely independently of one another. For instance, a system cache (e.g., a last-level cache, as a non-limiting example) may be partitioned into multiple “slices” or “instances,” each providing a same number of cache ways. Cache access operations by different resource clients may be assigned to one of the cache partitions using conventional address-to-partition mapping techniques based on, for example, hashes of memory addresses of cache access operations.

To facilitate sharing, a Quality of Service (QoS) mechanism may selectively allocate portions of a resource among difference resource clients, which may operate under different priorities, relative importance, and/or performance goals. For instance, in the cache example described above, a “way mask” (i.e., a bit mask including a bit for each cache way) corresponding to a resource client may be used to allocate a subset of the cache ways for each cache partition for use by that resource client. As a non-limiting example, a 20-way set-associative cache may be subdivided into eight (8) partitions, with each resource client's way mask having 20 bits to indicate which of the 20 ways are allocated to that resource client. Because each resource client's way mask is applied to all partitions, the minimum cache space that can be allocated to each resource client is 5%, or one (1) of the 20 ways over the eight (8) partitions.

Likewise, memory access bandwidth may also be allocated using conceptually similar controls. As an example, a processor-based system may provide four (4) memory controllers as memory access bandwidth providers. Each resource client may be assigned a “memory stride value” of four (4) bits to indicate how requests for memory bandwidth are weighted for that resource client, with a lower memory stride value indicating a higher weight. Because the memory stride value may have 16 different values (i.e., 0-15), the minimum memory access bandwidth that can be allocated to each resource client is 6.25% (or 1/16) of the total memory access bandwidth.

However, finer-grained QoS control may be desirable for allocation of shared resources. The QoS mechanisms described above permit only relatively coarse-grained controls that limit allocation resolution and restrict the number of resource clients that may access a given shared resource. Moreover, many mechanisms for implementing fine-grained QoS control may result in higher hardware implementation costs.

SUMMARY OF THE DISCLOSURE

Aspects according to the disclosure include providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems. In this regard, in one aspect, a processor-based system provides a partitioned resource (i.e., a system cache or memory access bandwidth to a shared system memory, as non-limiting examples) that is subdivided into a plurality of partitions and configured to service a plurality of resource clients. For each combination of resource client and partition, an allocation indicator is provided to indicate an allocation of the partition for the resource client. As a non-limiting example, aspects in which the partitioned resource is a partitioned cache having a plurality of ways may provide an allocation indicator to indicate how many ways of the partition may be allocated to the resource client. Similarly, aspects in which the partitioned resource is a plurality of memory access bandwidth providers may provide that the allocation indicator indicates a stride to be applied by a memory controller when performing a memory access operation for the resource client.

Because each allocation indicator may be different for each combination of resource client and partition, interpolation of the allocation indicators provides a higher-resolution aggregate resource allocation for each resource client. For instance, if the partitioned resource is a 10-way set-associative cache divided into four (4) partitions, conventional QoS mechanisms would only allow the cache to be allocated with a minimum resolution of 10% (i.e., a minimum allocation is 1 way out of 10). However, according to aspects disclosed herein, the allocation indicators for a given resource client may vary for each partition. As a non-limiting example, a resource client may be allocated 50% of the first and second partitions, and 60% of the third and fourth partitions. This results in a total aggregate allocation of the cache of 55% for the resource client.

In another aspect, a processor-based system for providing fine-grained QoS control of partitioned resources is disclosed. The processor-based system comprises a partitioned resource subdivided into a plurality of partitions and configured to service a plurality of resource clients. The processor-based system further comprises a resource allocation agent and a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of a plurality of resource clients, and representing an allocation of the partition for the resource client. The resource allocation agent is configured to allocate the partitioned resource among the plurality of resource clients based on an interpolation of the plurality of allocation indicators for each resource client of the plurality of resource clients.

In another aspect, a processor-based system for providing fine-grained QoS control of partitioned resources is disclosed. The processor-based system comprises a means for allocating a partitioned resource, subdivided into a plurality of partitions, among a plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

In another aspect, a method for providing fine-grained QoS control of partitioned resources is disclosed. The method comprises allocating, by a resource allocation agent of a processor-based system, a partitioned resource, subdivided into a plurality of partitions, among a plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

In another aspect, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores thereon computer-executable instructions which, when executed by a processor, cause the processor to allocate a partitioned resource, subdivided into a plurality of partitions, among a plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

DETAILED DESCRIPTION

Aspects disclosed in the detailed description include providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems. In this regard,FIG. 1illustrates an exemplary processor-based system100that includes a central processing unit (CPU)102and a partitioned resource104that is shared among multiple resource clients106(0)-106(C). The partitioned resource104according to some aspects may comprise a system cache, such as a last-level cache, and/or memory access bandwidth for a shared system memory accessible via a plurality of memory controllers (not shown). The resource clients106(0)-106(C) may comprise concurrently executing software processes, virtual machines, hardware devices, or other entities configured to access the partitioned resource104, as non-limiting examples. It is to be understood that the processor-based system100ofFIG. 1may encompass any one of known digital logic elements, semiconductor circuits, and processing cores, and/or memory structures, among other elements, or combinations thereof. Aspects described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor dies or packages. It is to be understood that some aspects of the processor-based system100may include elements in addition to those illustrated inFIG. 1.

To facilitate parallel usage by the resource clients106(0)-106(C) of the partitioned resource104, the processor-based system100provides that the partitioned resource104is subdivided into a plurality of partitions108(0)-108(P), each of which may be further divided into sub-units that can be selectively allocated among the resource clients106(0)-106(C). For instance, in aspects of the processor-based system100in which the partitioned resource104comprises a system cache (e.g., a last-level cache, as a non-limiting example), the partitions108(0)-108(P) may comprise cache “slices” or “instances,” each of which provides a same number of cache ways. Similarly, aspects of the processor-based system100in which the partitioned resource104comprises memory access bandwidth providers for a shared system memory may provide that each of the partitions108(0)-108(P) comprises a memory access bandwidth provider such as a memory controller. In both aspects, an access request110from a resource client106(0)-106(C), such as the resource client106(0), is assigned to one of the partitions108(0)-108(P) based on, for example, a hash of a memory address associated with the access request110.

However, as noted above, conventional QoS mechanisms for allocating the partitioned resource104among the resource clients106(0)-106(C) may not provide sufficient allocation resolution (i.e., the smallest allocatable portion of the partitioned resource104that can be allocated by the QoS mechanism may still be too large for precise allocation). Moreover, such coarse-grained QoS mechanisms may impose an inherent limit on the number of resource clients that may access a given shared resource. Thus, it is desirable to implement a fine-grained QoS mechanism to provide higher allocation resolution without incurring excessively higher hardware implementation costs.

In this regard, the processor-based system100ofFIG. 1provides a resource allocation agent112. While the resource allocation agent112is illustrated as a standalone element inFIG. 1, in some aspects the resource allocation agent112may be integrated into the CPU102, into a cache controller (not shown) or a memory management unit (MMU) (not shown), integrated into or distributed across other elements of the processor-based system100, and/or implemented in part by a software entity (not shown) such as an operating system or a hypervisor executed by the CPU102of the processor-based system100. The resource allocation agent112employs a plurality of allocation indicators114(0)-114(C),114′(0)-114′(C) associated with the partitions108(0)-108(P). Each of the allocation indicators114(0)-114(C),114′(0)-114′(C) corresponds to a unique combination of one of the resource clients106(0)-106(C) and one of the partitions108(0)-108(P), and represents an allocation of the partition108(0)-108(P) for the corresponding resource client106(0)-106(C). For example, inFIG. 1, assume that the allocation indicator114(0) corresponds to the partition108(0) for the resource client106(0), while the allocation indicator114′(0) corresponds to the partition108(P) for the resource client106(0). Depending on whether the access request110is assigned to the partition108(0) or the partition108(P), either the allocation indicator114(0) or the allocation indicator114′(0) will be used by the resource allocation agent112to determine how much of the corresponding partition108(0),108(P) may be allocated to the resource client106(0) to satisfy the access request110.

Unlike conventional QoS mechanisms, each of the allocation indicators114(0)-114(C),114′(0)-114′(C) for a given one of the resource clients106(0)-106(C) may vary across different partitions108(0)-108(P). As a result, a resource client such as the resource client106(0) may be allocated different portions of each of the partitions108(0)-108(P). By interpolating the different allocation indicators114(0)-114(C),114′(0)-114′(C), a higher allocation resolution may be attained, thus enabling a smaller portion of the partitioned resource104to be allocated to each of the resource clients106(0)-106(C) if desired.

To illustrate exemplary aspects of the processor-based system100,FIGS. 2-5are provided.FIG. 2illustrates an exemplary implementation of the processor-based system100ofFIG. 1wherein the partitioned resource104comprises a system cache and the resource allocation agent112comprises a cache controller, whileFIG. 4illustrates an exemplary implementation of the processor-based system100ofFIG. 1wherein the partitioned resource104comprises memory access bandwidth providers for a shared system memory and the resource allocation agent112comprises an MMU.FIGS. 3 and 5are provided to illustrate how interpolation of the allocation indicators114(0)-114(C),114′(0)-114′(C) provides fine-grained QoS control in each of the aforementioned aspects.

As seen inFIG. 2, one aspect of the processor-based system100may provide a cache controller200corresponding to the resource allocation agent112ofFIG. 1.FIG. 2further provides a system cache202that corresponds to the partitioned resource104ofFIG. 1, and a plurality of cache partitions204(0)-204(H) corresponding to the partitions108(0)-108(P) ofFIG. 1. Accordingly, disclosures herein regarding the resource allocation agent112, the partitioned resource104, and the partitions108(0)-108(P) ofFIG. 1apply to the cache controller200, the system cache202, and the cache partitions204(0)-204(H), respectively, ofFIG. 2. The system cache202may comprise a Level 1 (L1) cache, a Level 2 (L2) cache, a Level 3 (L3) cache, and/or a last-level cache, as non-limiting examples. Upon receiving a cache access request206comprising a memory address208, the cache controller200assigns the cache access request206to one of the cache partitions204(0)-204(H) (e.g., based on a hash of the memory address208).

FIG. 3provides a more detailed illustration of how the allocation indicators114(0)-114(C),114′(0)-114′(C) in the example ofFIG. 2may be interpolated to provide fine-grained QoS control of the system cache202ofFIG. 2. In this example, assume that the number of cache partitions204(0)-204(H) is four (i.e., H=3), and further that the cache partitions204(0)-204(3) of the system cache202are made up of 10 ways. Accordingly, the allocation indicators114(0)-114(3),114′(0)-114′(3) provide way masks300(0)-300(3),300′(0)-300′(3), each of which is made up of 10 bits corresponding to the 10 ways. The allocation indicators114(0)-114(3) represent the allocation of the cache partitions204(0)-204(3), respectively, of the system cache202for the resource client106(0). The allocation indicators114′(0)-114′(3) similarly represent the allocation of the cache partitions204(0)-204(3), respectively, of the system cache202for the resource client106(C).

Because the system cache202in this example is made up of 10 ways, a conventional QoS mechanism would be able to allocate the system cache202only in increments of 10%. However, by interpolating the allocation indicators114(0)-114(3),114′(0)-114′(3) to determine aggregate allocations of the system cache202for the resource clients106(0),106(C), a higher allocation resolution can be attained. In the example ofFIG. 3, instead of a resolution of 10%, the system cache202may be allocated in increments as small as 2.5% (i.e., the number of ways (10) divided by the number of cache partitions204(0)-204(3), in this example) by allocating one (1) way in one (1) of the cache partitions204(0)-204(3), and allocating zero (0) ways allocated in the remaining cache partitions204(0)-204(3). It is to be understood that the percentages discussed above are specific to the example ofFIG. 3, and may vary in some aspects according to the number of ways and the number of cache partitions204(0)-204(H).

In the example ofFIG. 3, the allocation indicators114(0) and114(1) have the first five (5) bit indicators set to a value of one (1), indicating that the first five (5) ways (i.e., 50%) of the cache partitions204(0) and204(1), respectively, are allocated to the resource client106(0). The allocation indicators114(2) and114(3) have the first six (6) bit indicators set to a value of one (1), indicating that the first six (6) ways (i.e., 60%) of the cache partitions204(2) and204(3), respectively, are allocated to the resource client106(0). Thus, the total aggregate allocation of the system cache202for the resource client106(0) is 55% (i.e., (50+50+60+60)/4). Likewise, the allocation indicators114′(0) and114′(1) have the last five (5) bit indicators set to a value of one (1), indicating that the last five (5) ways (i.e., 50%) of the cache partitions204(0) and204(1), respectively, are allocated to the resource client106(C). The allocation indicators114′(2) and114′(3) have the last four (4) bit indicators set to a value of one (1), indicating that the last four (4) ways (i.e., 40%) of the cache partitions204(2) and204(3), respectively, are allocated to the resource client106(C). The total aggregate allocation of the system cache202for the resource client106(C) is therefore 45% (i.e., (50+50+40+40)/4), an allocation that would not be possible using conventional QoS mechanisms with coarser resolutions.

Referring now toFIG. 4, in another aspect, the processor-based system100ofFIG. 1may provide an MMU400corresponding to the resource allocation agent112ofFIG. 1, memory access bandwidth providers402that corresponds to the partitioned resource104ofFIG. 1, and a plurality of memory controllers404(0)-404(M) corresponding to the partitions108(0)-108(P) ofFIG. 1. Disclosures herein regarding the resource allocation agent112, the partitioned resource104, and the partitions108(0)-108(P) ofFIG. 1thus may apply to the MMU400, the memory access bandwidth providers402, and the memory controllers404(0)-404(M), respectively, ofFIG. 4. The processor-based system100also includes a shared system memory406that is accessible by the resource clients106(0)-106(C) via the memory controllers404(0)-404(M). In some aspects, the shared system memory406may comprise dynamic random access memory (DRAM), as a non-limiting example.

In the example ofFIG. 4, the allocation indicators114(0)-114(C),114′(0)-114′(C) each comprise a memory stride value (not shown) that indicates a weight associated with requests for memory access bandwidth for the corresponding resource client106(0)-106(C). In some aspects, the memory stride values are inversely proportional to the weight assigned to the requests for memory access bandwidth, such that a lower memory stride value indicates a higher weight. When the MMU400receives a memory access request408comprising a memory address410, the MMU400assigns the memory access request408to be handled by one of the memory controllers404(0)-404(M). As a non-limiting example, the memory access request408may be assigned to one of the memory controllers404(0)-404(M) based on a hash of the memory address410.

FIG. 5illustrates in greater detail how fine-grained QoS control of the memory access bandwidth providers402ofFIG. 4may be provided by interpolating the allocation indicators114(0)-114(C),114′(0)-114′(C). InFIG. 5, it is assumed that the number of memory controllers404(0)-404(M) is four (i.e., M=3). The allocation indicators114(0)-114(3),114′(0)-114′(3) provide memory stride values500(0)-500(3),500′(0)-500′(3) that have a size of four (4) bits and that indicate the relative weights assigned to requests for memory access bandwidth for the corresponding resource clients106(0)-106(C) and the memory controllers404(0)-404(3). In particular, the allocation indicators114(0)-114(3) represent the allocations of the memory controllers404(0)-404(3), respectively, of the memory access bandwidth providers402for the resource client106(0), while the allocation indicators114′(0)-114′(3) represent the allocations of the memory controllers404(4)-404(3), respectively, of the memory access bandwidth providers402for the resource client106(C).

Because there are16possible values for each of the four-bit memory stride values500(0)-500(3),500′(0)-500′(3), a conventional QoS mechanism would be able to allocate the memory access bandwidth providers402only in increments of 6.25% (i.e., 1/16). In the example ofFIG. 5, though, a higher allocation resolution can be achieved by interpolating the allocation indicators114(0)-114(3),114′(0)-114′(3) to provide fractional memory stride values for the resource clients106(0),106(C). In the example ofFIG. 5, instead of a resolution of 6.25%, the memory access bandwidth providers402may be allocated in increments as small as 1.5625% (i.e., 1/16 divided by the number of memory controllers404(0)-404(3), in this example) by selecting a memory stride value500(0)-500(3),500′(0)-500′(3) of one (1) for one (1) of the memory controllers404(0)-404(M), and selecting a memory stride value500(0)-500(3),500′(0)-500′(3) of zero (0) in the remaining memory controllers404(0)-404(3). It is to be understood that the percentages discussed above are specific to the example ofFIG. 5, and may vary in some aspects according to the size of the memory stride values500(0)-500(3),500′(0)-500′(3) and the number of memory controllers404(0)-404(3).

As seen inFIG. 5, the allocation indicators114(0) and114(1) have been assigned the memory stride values500(0) and500(1), respectively, each having a value of two (2). The allocation indicators114(2) and114(3) have been assigned the memory stride values500(2) and500(3), respectively, each of which has a value of one (1) Thus, the total aggregate memory stride value of the memory access bandwidth providers402for the resource client106(0) is 1.5. Similarly, the allocation indicators114′(0) and114′(1) have been assigned the memory stride values500′(0) and500′(1), respectively, each having a value of four (4), while the allocation indicators114′(2) and114′(3) have been assigned the memory stride values500′(2) and500′(3), respectively, each having a value of three (3). The total aggregate memory stride value of the memory access bandwidth providers402for the resource client106(C) is therefore 3.5.

FIG. 6illustrates exemplary operations of the processor-based system100and the resource allocation agent112ofFIG. 1for providing fine-grained QoS control using interpolation for the partitioned resource104. For the sake of clarity, elements ofFIG. 1are referenced in describingFIG. 6. InFIG. 6, operations begin with the processor-based system100providing the partitioned resource104subdivided into a plurality of partitions108(0)-108(P) and configured to service a plurality of resource clients106(0)-106(C) (block600). In this regard, the processor-based system100may be referred to herein as “a means for providing a partitioned resource subdivided into a plurality of partitions and configured to service a plurality of resource clients.”

The resource allocation agent112(e.g., the cache controller200ofFIG. 2and/or the MMU400ofFIG. 4, as non-limiting examples) then allocates the partitioned resource104among the plurality of resource clients106(0)-106(C) based on an interpolation of a plurality of allocation indicators114(0)-114(C),114′(0)-114′(C), each corresponding to a partition108(0)-108(P) of the plurality of partitions108(0)-108(P) and a resource client106(0)-106(C) of the plurality of resource clients106(0)-106(C), and representing an allocation of the partition108(0)-108(P) for the resource client106(0)-106(C) (block602). Accordingly, the resource allocation agent112may be referred to herein as “a means for allocating the partitioned resource among the plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.”

To illustrate further exemplary operations of the resource allocation agent112ofFIG. 1for receiving and assigning an access request, such as the access request110ofFIG. 1, to the partitions108(0)-108(P) of the partitioned resource104,FIG. 7is provided. Elements ofFIGS. 1-5are referenced in describingFIG. 7, for the sake of clarity. Operations inFIG. 7begin with the resource allocation agent112receiving the access request110for the partitioned resource104from a resource client106(0)-106(C) of the plurality of resource clients106(0)-106(C) (block700). In aspects of the processor-based system100providing the system cache202ofFIG. 2, operations of block700for receiving the access request110may be carried out by the cache controller200, and may comprise receiving a cache access request206comprising a memory address208(block702). Likewise, aspects of the processor-based system100including the shared system memory406ofFIG. 4may provide that operations of block700for receiving the access request110may be carried out by the MMU400, and may comprise receiving a memory access request408comprising a memory address410(block704).

Next, the access request110is assigned to a partition108(0)-108(P) of the partitioned resource104(block706). Operations of block706for assigning the access request110according to the aspects illustrated inFIGS. 2 and 3may comprise selecting a cache partition204(0)-204(H) of the plurality of cache partitions204(0)-204(H) of the system cache202, based on a hash of the memory address208(block708). In aspects illustrated inFIGS. 4 and 5, operations of block706for assigning the access request110may comprise selecting a memory controller404(0)-404(M) of the plurality of memory controllers404(0)-404(M) to access the memory access bandwidth, based on a hash of the memory address410(block710). The resource allocation agent112(e.g., the cache controller200ofFIG. 2and/or the MMU400ofFIG. 4, as non-limiting examples) allocates a portion of the partition108(0)-108(P) of the partitioned resource104to the resource client106(0)-106(C) based on an allocation indicator114(0)-114(C),114′(0)-114′(C) of the plurality of allocation indicators114(0)-114(C),114′(0)-114′(C), each corresponding to a partition108(0)-108(P) of the plurality of partitions108(0)-108(P) and a resource client106(0)-106(C) of the plurality of resource clients106(0)-106(C) (block712).

Providing fine-grained QoS control using interpolation for partitioned resources in processor-based systems according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard,FIG. 8illustrates an example of a processor-based system800that corresponds to the processor-based system100ofFIGS. 1, 2, and 4, and that can employ the resource allocation agent112illustrated inFIG. 1. The processor-based system800includes one or more CPUs802, each including one or more processors804. The CPU(s)802may have cache memory806that is coupled to the processor(s)804for rapid access to temporarily stored data, and that in some aspects may comprise the resource allocation agent112ofFIG. 1. The CPU(s)802is coupled to a system bus808and can intercouple master and slave devices included in the processor-based system800. As is well known, the CPU(s)802communicates with these other devices by exchanging address, control, and data information over the system bus808. For example, the CPU(s)802can communicate bus transaction requests to a memory controller810as an example of a slave device. According to some aspects, the memory controller810may correspond to the memory controllers404(0)-404(M) ofFIG. 4.

Other master and slave devices can be connected to the system bus808. As illustrated inFIG. 8, these devices can include a memory system812, one or more input devices814, one or more output devices816, one or more network interface devices818, and one or more display controllers820, as examples. In some aspects, the memory system812may comprise the resource allocation agent112ofFIG. 1. The input device(s)814can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s)816can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s)818can be any devices configured to allow exchange of data to and from a network822. The network822can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s)818can be configured to support any type of communications protocol desired. The memory system812can include one or more memory units824(0)-824(N).

The CPU(s)802may also be configured to access the display controller(s)820over the system bus808to control information sent to one or more displays826. The display controller(s)820sends information to the display(s)826to be displayed via one or more video processors828, which process the information to be displayed into a format suitable for the display(s)826. The display(s)826can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.