Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing

A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises polysilicon(31-32), a diffusion barrier (34) on the polysilicon and an oxygen stable material (36) on the diffusion barrier (34). The oxygen stable material (36) is formed by first forming a disposable dielectric layer (50) patterned and etched to expose the area where the storage node is desired and then depositing the oxygen stable material (36). The oxygen stable material (36) is then either etched back or CMP processed using the disposable dielectric layer (50) as an endpoint. The disposable dielectric layer (50) is then removed. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

FIELD OF THE INVENTION
 This invention generally relates to the fabrication of high dielectric
 constant capacitors.
 BACKGROUND OF THE INVENTION
 The increasing density of integrated circuits (e.g., DRAMs) is increasing
 the need for materials with high dielectric constants to be used in
 electrical devices such as capacitors. Generally, capacitance is directly
 related to the surface area of the electrode in contact with the capacitor
 dielectric, but it is not significantly affected by the electrode volume.
 The current method generally used to achieve higher capacitance per unit
 area is to increase the surface area/unit area by increasing the
 topography in trench and stack capacitors using silicon dioxide or silicon
 dioxide/silicon nitride as the dielectric. This approach becomes very
 difficult in terms of manufacturability for devices such as the 256 Mbit
 and 1 Gbit DRAMs.
 An alternative approach is to use a high permitivity dielectric material.
 Many high dielectric constant (HDC) materials including perovskites,
 ferroelectrics and others, such as (Ba, Sr)TiO3 (BST), usually have much
 larger capacitance densities than standard SiO2-Si3N4-SiO2 capacitors. The
 deposition process for HDC materials such as BST usually occurs at high
 temperature (generally greater than 500.degree. C.) in an oxygen
 containing atmosphere. Therefore, the lower electrode structure formed
 prior to the HDC deposition should be stable in an oxygen atmosphere and
 at these temperatures.
 Various metals and metallic compounds, and typically noble metals such as
 Pt and conductive oxides such as RuO2, have been proposed as the
 electrodes for the HDC materials. However, there are several problems with
 the materials thus far chosen for the lower electrode in thin-film
 applications. Many of these problems are related to semiconductor process
 integration. For example, it has been found to be difficult to use Pt
 alone as the lower electrode. While Pt is stable in oxygen, it generally
 allows oxygen to diffuse through it allowing neighboring materials to
 oxidize. Pt. does not normally stick very well to traditional dielectrics
 such as silicon dioxide and silicon nitride and Pt can rapidly form a
 silicide at low temperatures. Therefore, prior art methods have used lower
 electrodes comprising multiple layers to separate the Pt from the
 underlying silicon. However, even when multiple layers are used for the
 lower electrode, a problem remains in that Pt is very difficult to etch
 when using a pattern. The principle problem is the difficulty in forming
 volatile halides. For example, etching Pt in fluorine and chlorine gas
 mixtures is almost a completely physical process until very high
 temperatures (&gt;300.degree. C.) are reached. Physical etching typically
 results in redeposition on the sidewalls of photoresist or other pattern
 definers unless a very sloped sidewall (&lt;65 degrees) is used. If the goal
 is to etch 1 G-like structures (F-0.18 .mu.m) with reasonable aspect
 ratios (&gt;1), then sloped sidewalls are a serious problem.
 SUMMARY OF THE INVENTION
 A capacitor structure and method of forming the capacitor structure are
 disclosed herein. The capacitor comprises a HDC dielectric and upper and
 lower electrodes. The lower electrode comprises, at least in part, an
 oxygen stable material. The oxygen stable material is formed by first
 forming a disposable dielectric layer patterned and etched to expose the
 area where the storage node is desired and then depositing the oxygen
 stable material. The oxygen stable material is then either etched back or
 CMP processed using the disposable dielectric layer as an endpoint. The
 disposable dielectric layer is then removed. The HDC dielectric is then
 formed adjacent the oxygen stable material.
 An advantage of the invention is proving a method of forming a high-K
 capacitor that does not require a fine patterned etch of the oxygen stable
 material for the lower electrode.

Corresponding numerals and symbols in the different figures refer to
 corresponding parts unless otherwise indicated.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
 The invention is described herein in conjunction with a high-K capacitor
 structure for a DRAM application. It will be apparent to those of ordinary
 skill in the art that the benefits of the invention are also applicable to
 other high-K capacitor structures.
 A pair of DRAM cells 10 each including a capacitor 12 according to the
 invention are shown in FIG. 1. The pair of DRAM cells 10 are located on
 substrate 14. Substrate 14 is typically silicon. However, other
 semiconductors such as germanium or diamond, compound semiconductors such
 as GaAs, InP, Si/Ge, or SiC, and ceramics may alternatively be used.
 Insulating regions 16 are used to isolate the pair of DRAM cells 10 from
 other DRAM cell pairs (not shown). As shown, insulating regions 16
 comprise a field oxide region. Other isolation structures known in the
 art, such as shallow trench isolation, may alternatively be used. Wordline
 structures 18 form the gates of the transistor. Wordlines structures 18
 may the same as those used conventionally in DRAM structures. Bitline 20
 is connected to the common source/drain 22 of the DRAM cell pair 10. The
 opposite source/drain regions 26 are each connected to the bottom
 electrode of a capacitor 12. The interlevel dielectric layers 24 and 28
 are capped by an etchstop layer 30. The interlevel dielectric layers 24
 and 28 typically comprise an oxide such as silicon dioxide. The etchstop
 layer 30 comprises a material that may be etched selectively with respect
 to a temporary dielectric described further below. In the preferred
 embodiment, etchstop layer 30 comprises silicon-nitride. Other materials
 that provide a non-reactive etchstop and possible diffusion barrier, such
 as undoped TEOS, aluminum-oxide, titanium-oxide or aluminum-nitride may
 alternatively be used.
 The bottom electrode of capacitors 12 comprises a base 32. Base 32 may
 comprise the shape of a plug that extends from source/drain region 26
 through interlevel dielectric layer 24 and a storage node contact (SNCT)
 31 that extends from base 32 through interlevel dielectric 28. Base 32 and
 SNCT 31 would typically comprise doped polysilicon, such as insitu-doped
 polysilicon. Above SNCT 31, a diffusion barrier layer 34 is located. The
 thickness of diffusion barrier layer 34 may be on the order of 1000 A.
 Above diffusion barrier layer 34 is oxygen stable layer 36. The height of
 oxygen stable layer 36 is the height desired for the storage node. For a 1
 Gbit BST DRAM, a store thickness of approximately 3000 A is appropriate.
 Diffusion barrier 34 preferably comprises titanium-aluminum-nitride. Other
 materials that prevent the diffusion of oxide and that do not react with
 the SNCT 31, such as titanium-nitride, ternary (or greater) amorphous
 nitrides (e.g., Ti--Si--N, Ta--Si--N, Ta--B--N, or Ti--B--N), or other
 exotic conductive nitrides (e.g., Zr nitride, Hf nitride, Y nitride, Sc
 nitride, La nitride and other rare earth nitrides, nitride deficient Al
 nitride, doped Al nitride, Mg nitride, Ca nitride, Sr nitride and Ba
 nitride) may alternatively be used. Oxygen stable layer 36 preferably
 comprises platinum. Other possible materials include other noble metals or
 alloys thereof (e.g., palladium, iridium, ruthenium, rhodium, gold,
 silver), conductive metal compounds (e.g., binary oxides, RuOx, tin oxide,
 IrOx, indium oxide, etc,), or conductive perovskite like materials (e.g.,
 (La,Sr)CoO3+, SrRuO3, etc.).
 Diffusion barrier 34 prevents oxygen from diffusing through oxygen stable
 layer 36 and reacting with/oxidizing SNCT 31. It also prevents oxygen
 stable layer 36 from reacting with base 32 to form a silicide. The
 diffusion barrier 34 might not be used for some combinations of oxygen
 stable materials and high-K material process temperature and ambients.
 The capacitor dielectric 40 is a high dielectric constant dielectric,
 typically having a dielectric constant greater than 50. Barium-strontium
 titanate (BST) is a typical example. Other examples include SrTiO3,
 BaTiO3, ferroelectric materials such as Pb(Zr,Ti)O3, (Pb,La)(Zr,Ti)O3, Nb
 doped PZT, doped PZT, Bi4Ti3O12, SrBi2(Ta,Nb)2O9, and other layered
 perovskites, relaxors such as lead-magnesiumniobate. Dielectric 40 follows
 the contour of the device and is located on the sidewalls and on the
 surface of oxygen stable layer 36. The formation of dielectric 40 is
 typically performed in an O2 ambient. Oxygen stable layer 36 is stable in
 O2 and since only the oxygen stable layer portion of the bottom electrode
 is exposed during BST formation, oxidation of the bottom electrode is
 prevented. A top electrode 44 is located over the dielectric 40. The top
 electrode 44 comprises conventional materials.
 A method for forming the DRAM cell pair 10 of FIG. 1 will now be described
 in conjunction with FIGS. 2A-2I. The structure is processed through the
 formation of interlevel dielectric 24 as shown in FIG. 2A. Isolating
 regions 16, source/drain regions 22 and 26, wordline structures 18, and
 bitlines 20 have already been formed. Conventional techniques known in the
 art may be used to formed these structures.
 Referring to FIG. 2B, a second thick interlevel dielectric film 28 is
 deposited over the structure followed by the deposition of a thin etchstop
 layer 30. The second interlevel dielectric film 28 may, for example,
 comprise TEOS and have a thickness on the order of 3000 A. Etchstop layer
 30 would typically comprise silicon nitride. Etchstop layer 30 and
 interlevel dielectric film 28 are patterned and etched using a SNCT
 pattern to expose areas where the storage node is desired. In most
 capacitor-over-bitline (COB) DRAM architectures, a self-aligned contact
 (SACT) has previously been filled with a polysilicon base 32 to form a pad
 landing at the bitline 20 height. The SNCT pattern aligns to the
 polysilicon base 32. Although an ideal alignment is desired, FIG. 2B shows
 a slight misalignment accounting for alignment tolerances. The diameter of
 the base 32 is minimum critical dimension (CD). For the case of a 1 Gbit
 DRAM, the CD is on the order of 0.18 .mu.m. In order to help in the
 alignment of the store pattern, whose width is also at minimum CD, to the
 base 32, an optional dielectric sidewall liner 33 can be deposited at this
 point, as shown in FIG. 2C. Although this increases the contact resistance
 of the subsequently formed SNCT, it improves the probability of having
 only the base 32 exposed at this point. If, on the other hand, base 32 had
 not previously been formed, the etch described above would continue
 through interlevel dielectric 24 to source/drain region 26.
 Next, the SNCT 31 is formed. In the preferred embodiment, ISD polysilicon
 is deposited to a thickness greater than one half of the diameter of the
 SNCT area and etched back to form SNCT 31. Either an anisotropic etchback
 or a chemical-mechanical polish may be used. SNCT 31 is recessed
 approximately 300-500 A below the surface of layer 30. It should be noted
 that either or both base 32 and SNCT 31 may alternatively comprise metal
 compounds (such as nitrides, silicides, or carbides), conductive metals
 (such as titanium, tungsten, tantalum, or molybdenum), single component
 semiconductors (such as silicon or germanium), compound semiconductors
 (such as GaAs, InP, Si/Ge, or SiC), or combinations of the above.
 The next step in the formation of the bottom electrode/storage node is the
 deposition of the diffusion barrier 34. Although titanium-nitride is a
 popular diffusion barrier, a material such as Ti--Al--N is preferable
 because of its superior oxidation resistance. Optimum TiAlN compositions
 are Ti.sub.1-x Al.sub.x N, where 0.3&lt;.times.&lt;0.5. Other materials that may
 be used for diffusion barrier 34 include, but are not limited to, ternary
 (or greater) amorphous nitrides and exotic conductive nitrides as listed
 in more detail above. In forming diffusion barrier 34, CVD processes are
 preferable, but sputter deposition of a 1000 A thick film may
 alternatively be used. A planarization process such a reactive ion etching
 (RIE) etchback or CMP, is then performed to remove the diffusion barrier
 material from the surface of the etchstop layer 30. Diffusion barrier 34
 is thus left only above the SNCT 31. The height of diffusion barrier 34 is
 such that the surface of diffusion barrier 34 is at or below the surface
 of the etchstop layer 30, as shown in FIG. 2E.
 Next, a disposable dielectric layer 50 is deposited over the structure.
 Examples for disposable dielectric layer 50 included PSG and TEOS. Other
 examples will be apparent to those of ordinary skill in the art having
 reference to the specification. The composition of disposable layer 50 and
 etchstop layer 30 should be chosen such that disposable dielectric layer
 50 may be removed selectively with respect to etchstop layer 30. The
 thickness of layer 50 is on the order of the desired thickness of the
 storage node. For a 1 Gbit BST DRAM this is expected to be on the order of
 3000 A. A store hole pattern is then placed on disposable layer 50. The
 store hole pattern exposes disposable layer 50 where the storage node is
 desired. This pattern can be slightly larger than minimum CD in order to
 improve the alignment to SNCT 31. Using this pattern, a very anisotropic
 etch is used to etch the disposable dielectric layer 50, as shown in FIG.
 2F. The pattern is then removed.
 Referring to FIG. 2G, an oxygen stable layer 52 is deposited over the
 structure. Pt is an excellent oxygen stable material for layer 52. Other
 examples for an oxygen stable layer 52 include other noble metals
 (described above) and conductive oxides such as RuO2+, IrOx, PdO,
 (LaSr)CoO3+ and SrRuO3. For the oxygen stable layer 52, a CVD would be
 preferred but a sputter process with .about.50% step coverage could be
 successfully integrated into the process flow. Alternative processes
 include reflow of the oxygen stable material or forcefill of the oxygen
 stabel material.
 Referring to FIG. 2H, oxygen stable layer 52 is then etched-back (RIE or
 CMP) to remove the oxygen stable layer 52 to a level just below the top of
 disposable dielectric layer 50, creating storage node 36. Finally,
 disposable layer 50 is removed, as shown in FIG. 2I. For example, a wet,
 selective dry or vapor dielectric etch may be used. The remaining storage
 node 36 can have 90.degree. sidewalls. The top of the storage node 36 may
 not be planar. However, the majority of the storage area comes from the
 storage node 36 sidewalls.
 The invention has several benefits. One benefit is that the oxygen stable
 bottom electrode is defined by etching the easily etchable material of the
 temporary dielectric 50 (e.g. PSG) and not by fine pattern etching the
 oxygen stable material 36. With the exception of Ru, most of the oxygen
 stable bottom electrode materials are very hard to dry etch fine patterns.
 The principle problem is the difficulty in forming volatile halides or
 oxides. For example, etching Pt in fluorine and chlorine gas mixtures is
 almost a completely physical process until very high temperatures
 (&gt;300.degree. C.) are reached. Physical etching typically results in
 redeposition on the sidewalls of photoresist or other pattern definers
 unless a very sloped sidewall (&lt;65 degrees) is used. If the goal is to
 etch 1 G-like structures (F-0.18 .mu.m) with reasonable aspect ratios
 (&gt;1), then sloped sidewalls are a serious problem.
 The structure of FIG. 2H is the storage node 36 upon which the HDC
 capacitor dielectric is deposited (see FIG. 1). The preferred HDC
 dielectric is BST. However, other HDC dielectric could alternatively be
 used. Finally, the top capacitor electrode 44 is formed over HDC
 dielectric 40. Exemplary top electrode materials for use over a HDC
 dielectric are known in the art. The top electrode 44 will, in general,
 comprises the same material(s) as the bottom electrode in order to have
 symmetrical leakage currents. The material in contact with the capacitor
 dielectric 40 can be relatively thin if it is covered by a conductive
 diffusion barrier or other metallization layer. A specific embodiment
 might comprises a 50 nm thick Pt or Ir layer. The deposition is either
 sputter deposited (long throw, collimated, or ionized for better
 conformality) or CVD. Next, a 50-100 nm thick layer of TiN or TiAlN is
 deposited by reactive sputter deposition or by CVD. The top electrode 44
 is then pattern by reactive ion etch process and TiN or TiAlN can be used
 as a hardmask for the remaining etch if desired. The sample might be
 annealed in N.sub.2 is TiN is used of O.sub.2 is TiAlN is used as a
 hardmask. Typical anneal conditions are 650.degree. C. in N.sub.2 or
 O.sub.2 for 30 sec for 550.degree. C. in N.sub.2 or O.sub.2 for 30 min.
 While this invention has been described with reference to illustrative
 embodiments, this description is not intended to be construed in a
 limiting sense. Various modifications and combinations of the illustrative
 embodiments, as well as other embodiments of the invention, will be
 apparent to persons skilled in the art upon reference to the description.
 It is therefore intended that the appended claims encompass any such
 modifications or embodiments.