Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP

A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming an interposer and opposing build-up interconnect structure with connecting conductive TMVs for electrical interconnect of a Fo-WLCSP.

BACKGROUND OF THE INVENTION

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. The term “semiconductor die” as used herein refers to both the singular and plural form of the word, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

In a fan-out wafer level chip scale package (Fo-WLCSP), a semiconductor die is typically enclosed by an encapsulant. A top and bottom build-up interconnect structure are formed over opposite surfaces of the encapsulant for electrical interconnect, e.g. when stacking the Fo-WLCSPs. Each build-up interconnect structure requires formation of a redistribution layer (RDL) involving complex, expensive, and time-consuming manufacturing steps, such as lithography, etching, and metal deposition.

SUMMARY OF THE INVENTION

A need exists for a simple and cost effective electrical interconnect for stackable Fo-WLCSPs. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a plurality of first conductive vias formed through the substrate and first conductive layer formed over the substrate, providing a carrier, mounting a semiconductor die over the carrier, mounting the substrate to the semiconductor die opposite the carrier, depositing an encapsulant between the substrate and carrier around the semiconductor die, and forming a plurality of second conductive vias through the substrate and encapsulant. The second conductive vias are electrically connected to the first conductive layer and first conductive vias. The method further includes the steps of removing the carrier, and forming an interconnect structure over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the second conductive vias.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a conductive path through the substrate, providing a semiconductor die, mounting the substrate to the semiconductor die, depositing an encapsulant around the semiconductor die, forming a plurality of conductive vias through the substrate and encapsulant, and forming an interconnect structure over a surface of the encapsulant and semiconductor die opposite the substrate. The conductive vias are electrically connected to the conductive path through the substrate. The interconnect structure is electrically connected to the conductive vias.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die, depositing an encapsulant around the semiconductor die, mounting a substrate to the semiconductor die, forming a plurality of conductive vias through the substrate and encapsulant, and forming an interconnect structure over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive vias.

In another embodiment, the present invention is a semiconductor device comprising a semiconductor die and encapsulant deposited around the semiconductor die. A substrate is mounted to the semiconductor die. A plurality of conductive vias is formed through the substrate and encapsulant. An interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive vias.

DETAILED DESCRIPTION OF THE DRAWINGS

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and bond wires82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74or bond wires82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Bond wires94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and bond wires94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flipchip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flipchip style first level packaging without intermediate carrier106.

FIG. 3ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by inter-die wafer area or saw streets126as described above. Saw streets126provide cutting areas to singulate semiconductor wafer120into individual semiconductor die124. In one embodiment, semiconductor die124may have dimensions ranging from 2×2 millimeters (mm) to 15×15 mm.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back surface128and active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. Semiconductor die124can be a flipchip type die, conductive through silicon vias (TSV) die, or bond wire die.

An electrically conductive layer132is formed over active surface130using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer132can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer132operates as contact pads electrically connected to the circuits on active surface130. Contact pads132can be disposed side-by-side a first distance from the edge of semiconductor die124, as shown inFIG. 3b. Alternatively, contact pads132can be offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die.

InFIG. 3c, semiconductor wafer120is singulated through saw street126using a saw blade or laser cutting tool134into individual semiconductor die124.

FIG. 4a-4cshow formation of a wafer-form, strip leadframe or interposer. InFIG. 4a, a substrate or carrier140contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape142is formed over carrier140as a temporary adhesive bonding film or etch-stop layer. A semiconductor wafer or substrate144contains a base material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. As a semiconductor wafer, substrate144can contain embedded semiconductor die or passive devices. Substrate144can also be a multi-layer flexible laminate, ceramic, or leadframe. Substrate144is mounted to interface layer142over carrier140.

InFIG. 4b, a plurality of vias is formed through substrate144using laser drilling, mechanical drilling, or deep reactive ion etching (DRIE). The vias are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect conductive vias146.

An insulating or passivation layer148is formed over a surface of substrate144and conductive vias146using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer148contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. A portion of insulating layer148is removed by an etching process to expose substrate144and conductive vias146.

An electrically conductive layer or RDL150is formed over the exposed substrate144and conductive vias146using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer150can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer150is electrically connected to conductive vias146.

InFIG. 4c, a substrate or carrier154contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape156is formed over carrier154as a temporary adhesive bonding film or etch-stop layer. Leading with insulating layer148and conductive layer150, substrate144is mounted to interface layer156over carrier154. Carrier140and interface layer142are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose a surface of substrate144and conductive vias146opposite conductive layer150.

An insulating or passivation layer158is formed over substrate144and conductive vias146using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer158contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer158is removed by an etching process to expose substrate144and conductive vias146.

An electrically conductive layer or RDL160is formed over the exposed substrate144and conductive vias146using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer160can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer160is electrically connected to conductive vias146. In another embodiment, conductive vias146are formed through substrate144after forming conductive layers150and/or160. The resulting wafer-form, strip leadframe or interposer162provides electrical interconnect vertically and laterally across the interposer. The interposer162can also be an internal stacking module (ISM).

FIGS. 5a-5hillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming an interposer and opposing build-up interconnect structure with connecting conductive TMVs for electrical interconnect of a Fo-WLCSP. InFIG. 5a, a substrate or carrier170contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape172is formed over carrier170as a temporary adhesive bonding film or etch-stop layer.

Semiconductor die124fromFIGS. 3a-3care mounted to interface layer172and carrier170using a pick and place operation with active surface130oriented toward the carrier. Fiducial alignment marks173are formed on carrier170to assist alignment, e.g. around edge of the carrier or around each die location.FIG. 5bshows semiconductor die124mounted to carrier170. In another embodiment, an ISM is mounted to carrier170.

InFIG. 5d, an encapsulant or molding compound176is deposited between interposer162and carrier170around semiconductor die124using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant176can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant176can be deposited through side openings178between interposer162and carrier170with vacuum assist. Alternatively, encapsulant176is deposited through opening180in interposer162. The viscosity of encapsulant176is selected for uniform coverage, e.g. a lower viscosity increases the flow of the encapsulant. Encapsulant176is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

InFIG. 5e, a plurality of vias is formed through interposer162and encapsulant176using mechanical drilling, laser drilling, or DRIE. The via location can be adjusted to align with conductive layers150and160of interposer162. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive through mold vias (TMV)182. An optional insulating layer can be formed around conductive TMVs182. Conductive TMVs182extend completely through encapsulant176into interface layer172or carrier170. Conductive TMVs182are electrically connected to conductive vias146and conductive layers150and160of wafer-form, strip leadframe or interposer162.

InFIG. 5f, carrier170and interface layer172are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose active surface130, encapsulant176, and conductive TMVs182. Since conductive TMVs182extend completely through encapsulant176to carrier170, the conductive TMVs are exposed and protrude from encapsulant176following removal of the carrier.

InFIG. 5g, a build-up interconnect structure184is formed over semiconductor die124, encapsulant176, and conductive TMVs182. The build-up interconnect structure184includes an electrically conductive layer or RDL186formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer186can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The protruding conductive TMVs182assist with formation of build-up interconnect structure184by aligning conductive layer186with the protruding conductive TMVs. One portion of conductive layer186is electrically connected to contact pads132of semiconductor die124. Another portion of conductive layer186is electrically connected to conductive TMVs182. Other portions of conductive layer186can be electrically common or electrically isolated depending on the design and function of semiconductor die124.

An insulating or passivation layer188is formed between conductive layer186for electrical isolation using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer188contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer188can be removed by an etching process to expose conductive layer186for bump formation or additional package interconnect. The build-up interconnect structure184is electrically connected to interposer162by way of conductive TMVs182.

InFIG. 5h, an electrically conductive bump material is deposited over build-up interconnect structure184and electrically connected to the exposed portion of conductive layer186using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer186using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps190. In some applications, bumps190are reflowed a second time to improve electrical contact to conductive layer186. An under bump metallization (UBM) layer can be formed under bumps190. The bumps can also be compression bonded to conductive layer186. Bumps190represent one type of interconnect structure that can be formed over conductive layer186. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

Semiconductor die124are singulated through encapsulant164with saw blade or laser cutting tool192into individual Fo-WLCSP194, as shown inFIG. 6. Semiconductor die124is electrically connected through contact pads132, build-up interconnect structure184, and conductive TMVs182to interposer162. The wafer-form, strip leadframe or interposer162and opposing build-up interconnect structure184with connecting conductive TMVs182provide a simple and cost effective structure for vertical interconnect of semiconductor die124, as well as efficient package stacking through the wiring layer of the interposer and build-up interconnect structure184.

FIG. 8shows an embodiment of Fo-WLCSP196, similar toFIG. 6, with stacked semiconductor die124having similar or different electrical functions. Semiconductor die124ais mounted back surface-to-back surface of semiconductor die124bwith die attach adhesive198. The interposer162is mounted to semiconductor die124bwith die attach adhesive201. Contact pads132of semiconductor die124bcan be electrically connected to conductive layer150and160of interposer162with bump200or conductive vias202. Semiconductor die124aand124bare electrically connected by way of build-up interconnect structure184, conductive TMVs182, and interposer162.

FIGS. 9a-9gillustrate, in relation toFIGS. 1 and 2a-2c, another process of forming an interposer and opposing build-up interconnect structure with connecting conductive TMVs for electrical interconnect of a Fo-WLCSP. Continuing fromFIG. 5b, an encapsulant or molding compound204deposited over carrier170around semiconductor die124using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator, as shown inFIG. 9a. Encapsulant204can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant204is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

InFIG. 9b, a portion of encapsulant204is removed by grinder206to planarize the encapsulant. The grinding operation can also remove bulk semiconductor material from back surface128of semiconductor die124for a thinner package profile.

InFIG. 9c, wafer-form, strip leadframe or interposer162is mounted to the back surface of semiconductor die124and encapsulant204with die attach adhesive208, such as epoxy resin.

InFIG. 9d, a plurality of vias is formed through interposer162and encapsulant204using mechanical drilling, laser drilling, or DRIE. The via location can be adjusted to align with conductive layers150and160of interposer162. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive TMVs210. An optional insulating layer can be formed around conductive TMVs210. Conductive TMVs210extend completely through encapsulant204into interface layer172or carrier170. Conductive TMVs210are electrically connected to conductive vias146and conductive layers150and160of wafer-form, strip leadframe or interposer162.

InFIG. 9e, carrier170and interface layer172are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose active surface130, encapsulant204, and conductive TMVs210. Since conductive TMVs210extend completely through encapsulant204into carrier170, the conductive TMVs are exposed and protrude from encapsulant204following removal the carrier.

InFIG. 9f, a build-up interconnect structure214is formed over semiconductor die124, encapsulant204, and conductive TMVs210. The build-up interconnect structure214includes an electrically conductive layer or RDL216formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer216can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The protruding conductive TMVs210assist with formation of build-up interconnect structure214by aligning conductive layer216with the exposed conductive TMVs. One portion of conductive layer216is electrically connected to contact pads132of semiconductor die124. Another portion of conductive layer216is electrically connected to conductive TMVs210. Other portions of conductive layer216can be electrically common or electrically isolated depending on the design and function of semiconductor die124.

An insulating or passivation layer218is formed between conductive layer216for electrical isolation using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer218contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer218can be removed by an etching process to expose conductive layer216for bump formation or additional package interconnect. The build-up interconnect structure214is electrically connected to interposer162by way of conductive TMVs210.

InFIG. 9g, an electrically conductive bump material is deposited over build-up interconnect structure214and electrically connected to the exposed portion of conductive layer216using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer216using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps220. In some applications, bumps220are reflowed a second time to improve electrical contact to conductive layer216. A UBM layer can be formed under bumps220. The bumps can also be compression bonded to conductive layer216. Bumps220represent one type of interconnect structure that can be formed over conductive layer216. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

Semiconductor die124are singulated through encapsulant204with saw blade or laser cutting tool222into individual Fo-WLCSP224, as shown inFIG. 10. Semiconductor die124is electrically connected through contact pads132, build-up interconnect structure214, and conductive TMVs210to interposer162. The wafer-form, strip leadframe or interposer162and opposing build-up interconnect structure214with connecting conductive TMVs210provide a simple and cost effective structure for vertical interconnect of semiconductor die124, as well as efficient package stacking through the wiring layer of the interposer and build-up interconnect structure214.