Additive structure and method for testing semiconductor wire bond dies

A structure and method for achieving burn-in and full functional testing of a semiconductor wire bond die are provided. The structure comprises an electrical conductor which connects a wire bond pad to a solderable test contact laterally displaced from the wire bond pad. The solderable test contact is configured to facilitate electrical connection of an external testing device thereto for electrical testing and/or burn-in of integrated circuitry associated with the die, without direct physical contact to the wire bond pads. The structure does not need to be removed following the burn-in or test.

TECHNICAL FIELD 
The present invention generally relates to a structure and method for 
testing semiconductor wire bond dies, and more particularly, to a 
structure and method for burn-in and full functionality testing of 
semiconductor wire bond dies. 
BACKGROUND ART 
Full functionality testing is known to be carried out on semiconductor 
solder bump connect dies while the dies are still embodied in the silicon 
wafer. However, burn-in followed by the testing of semiconductor wire bond 
dies is generally not done at the wafer level because of inherent 
structural difficulties and the nature of making wire connections to 
external structures. Instead, burn-in and full testing of wire bond dies 
is generally done only after the dies have been severed from the wafer and 
packaged. 
Typically, semiconductor wire bond dies defined on a semiconductor wafer 
undergo initial low-level dc testing wherein individual dies are tested 
for satisfactory operation. However, there are problems associated with 
this form of testing. External testing probes directly contacting wire 
bond pads can damage the wire bond pads by scratching or marking the pads 
such that subsequent wire bond electrical connection thereto can be 
difficult. In addition, electrical contact to wire bond pads may be 
inconsistent when probe contacts must be maintained for any considerable 
length of time. 
After dc testing, the wafer is severed between individual dies, inoperable 
dies are discarded, and operable dies are collected for packaging into a 
module. After packaging, burn-in and full functionality testing of each 
die circuit is conducted under extended time and temperature conditions 
directed to assessing circuit reliability. If a particular wire bond die 
is found inoperable after packaging, the entire module must often be 
discarded. 
Efforts have been made to eliminate the need for two separate tests and to 
avoid damaging the surface of the wire bond pad. Such efforts have 
principally been directed toward constructing a method and structure for 
conducting wafer level burn-in and full functionality testing of wire bond 
dies. However, these methods generally require use of additional test 
structures and levels of interconnection in the kerf region of the wafer. 
Such structures typically must be removed before dicing the die from the 
wafer in order to prevent degradation of internal die circuitry 
performance. Another problem associated with the use of test structures 
formed in the kerf region is that the number of dies which can be defined 
on a wafer is limited by the amount of area the test structures require. 
In addition, the technology required for adding and removing temporary 
interconnections can contribute significantly to the wafer processing 
costs. 
A need, therefore, continues to exist for an improved structure and method 
for achieving burn-in and full functionality testing of a semiconductor 
wire bond die. 
DISCLOSURE OF THE INVENTION 
Briefly, in one aspect of the present invention, a structure is provided 
for facilitating electrical testing of a semiconductor wire bond die 
without direct physical contact of an external testing device to a wire 
bond pad of the die. The structure, which is disposed at an upper surface 
of the semiconductor wire bond die, comprises an electrical conductor 
having a solderable test contact. The solderable test contact, which is 
laterally displaced from the wire bond pad, is configured to facilitate 
electrical connection of an external testing or burn-in device thereto for 
electrical testing or burning in of the semiconductor wire bond die. The 
electrical conductor is disposed entirely in a region above the active 
circuitry of the semiconductor wire bond die and does not require removal 
after testing or burning in of the die. 
In a more specific embodiment, the present invention provides a structure 
for facilitating the testing of or burning in a semiconductor wire bond 
die having an upper surface insulator with an aperture through which a 
wire bond pad is exposed. conductive strap physically and electrically 
contacts the wire bond pad by covering an upper surface thereof. The 
conductive strap extends laterally from the wire bond pad above the upper 
surface insulator and connects with a solderable conductive test 
protrusion which is disposed thereon. The conductive strap and the 
solderable conductive test protrusion are disposed in a region above the 
active circuitry of the semiconductor wire bond die. The solderable 
conductive test protrusion is configured to facilitate connection of an 
external testing device thereto in order to allow electrical testing of 
the semiconductor wire bond die without direct physical contact of the 
external testing device to the wire bond pad. The solderable conductive 
test protrusion allows connection between the die and a high performance 
testing or burn-in device without affecting the surface of the wire bond 
pad. 
In another aspect, the present invention provides a method for electrically 
testing a semiconductor wire bond die defined on a semiconductor wafer. 
The semiconductor wire bond die has a wire bond pad disposed at an upper 
surface thereof. The method includes forming an electrical conductor 
having a solderable test contact above the upper surface of the die and 
above the active circuitry of the die. The solderable test contact is 
laterally displaced from the wire bond pad and is configured to facilitate 
electrical testing of the die through contact with an electrical testing 
device. The electrical conductor includes an electrical interconnect 
portion which electrically connects the wire bond pad with the solderable 
test contact. The method also includes electrically connecting an external 
test connector to the solderable test contact, then electrically testing 
the semiconductor wire bond die using the external test connector without 
directly physically contacting the wire bond pad. 
To restate, the present invention satisfies the need for a structure and 
method for achieving burn-in and testing of individual semiconductor wire 
bond dies prior to modular packaging. The invention provides a structure 
for testing that is confined within the boundary of the semiconductor wire 
bond die, thereby eliminating use of the kerf area surrounding the wire 
bond die. The structure need not be removed from the die after testing but 
can remain on the die without impacting circuit performance or 
reliability. Also, because the kerf area is not used, the physical 
presence of the test structure is not a limiting factor in determining the 
number of semiconductor wire bond dies that can be defined on a wafer. 
Another advantage of the present invention is that no direct physical 
contact is made to the wire bond pads by an external testing device. Thus, 
the wire bond pads remain undamaged from testing, and subsequent wire bond 
electrical connection thereto is facilitated. Further, the present 
invention provides a structure and method that obviate the conventional 
practice of utilizing a separate low-level method of testing the die using 
a probe, followed by burn-in and full functionality testing after 
severance and packaging. Currently, use of expensive test probes limits 
the minimum size of the die because the wire bond pads must be spaced far 
enough apart to prevent probe damage. Because probe testing on the wire 
bond pad is eliminated in accordance with the invention, wire bond dies 
can be fabricated in a smaller size. 
The structure and method for testing presented herein are economically 
beneficial because losses incurred due to discarded defective multichip 
modules can be eliminated. Finally, a savings to the semiconductor chip 
manufacturer and ultimately to the consumer can be realized because a 
greater number of dies can be defined on a wafer due to smaller die size 
and more efficient use of the kerf area surrounding the dies.

BEST MODE FOR CARRYING OUT THE INVENTION 
As noted, the present invention provides a structure and method for 
achieving burn-in and testing of a semiconductor wire bond die. In 
particular, a new contact point for facilitating electrical testing of the 
die's integrated circuitry is created above the active region of the die 
to replace use of the wire bond pads for testing. Thus, no direct physical 
contact of an external testing device is made to the wire bond pads of the 
die during testing or burn-in, and the problem of damage thereto is 
eliminated. The test contact points and electrical connections between the 
contact points and the die circuitry through the wire bond pads remain on 
the die after testing or burn-in. Thus, if the tested die is defined on a 
wafer, subsequent dicing may be done without removing the structure and 
without impacting circuitry performance. 
Referring to the drawings, FIG. 1 is a top plan view of a portion 10 of an 
individual semiconductor wire bond die illustrating one embodiment of an 
additive test structure 11 (shaded region) in accordance with the present 
invention, shown in relation to a single wire bond pad 28 (FIG. 2) of the 
die 10. Portion 10 is entirely disposed above the active integrated 
circuitry of the die. Additive test structure 11 includes a conductive 
strap 16 and a solderable test protrusion 20. As shown in FIG. 2, wire 
bond pad 28 resides directly beneath conductive strap 16. 
"Conductive strap" is used herein to include any electrical conductor and 
is preferably a conductive metal layer compatible with wire bonding 
disposed on the semiconductor wire bond die. "Solderable" is used herein 
to refer to a metal capable of being joined with other metals using a 
melted metal alloy such as tin and lead. "Solderable test protrusion" is 
used herein to refer to a solderable conductive test contact on the die, 
which is preferably a protruding solderable conductive metal configured to 
facilitate electrical connection to an external connector such as a high 
performance testing or burn-in device. A bump such as a gold bump or 
solder ball is preferred, and a controlled collapse chip connect (C4) type 
solder ball comprising lead and tin may be used. 
Final passivation layer 12, which generally covers the entire top surface 
of the processed semiconductor wafer, serves to protect and insulate 
individual dies from damage during packaging and probe testing. Layer 12 
may comprise a dielectric material such as a polyimide, silicon dioxide, 
or silicon nitride. Structure 11 is shown disposed on final passivation 
layer 12, but the structure is not limited to being directly thereon, and 
the term "final passivation layer" as used herein includes any upper 
surface insulator of the semiconductor wire bond die. 
An aperture 13 in passivation layer 12 traditionally exposes upper surface 
29 of wire bond pad 28, and final passivation layer 12 has a sloped upper 
surface 18 bordering aperature 13. As shown in the FIGS. 1 and 2, 
passivation layer 12 does not reach wire bond pad 28. However, passivation 
layer 12 may contact wire bond 28, and other configurations of passivation 
layer 12 with respect to wire bond pad 28 will be obvious to those skilled 
in the art. 
Conductive strap 16 electrically interconnects wire bond pad 28 and 
solderable test protrusion 20 such that external testing of the 
semiconductor wire bond die is possible through solderable test protrusion 
20 without direct physical contact of the test device to wire bond pad 28 
or to upper surface 17 of conductive strap 16. Also, because conductive 
strap 16 preferably covers the entire upper surface 29 of wire bond pad 28 
and has an upper surface 17 itself, subsequent wire bond electrical 
connection to wire bond pad 28 can be made through upper surface 17 of 
conductive strap 16. 
Conductive strap 16 extends from wire bond pad 28, up sloped surface 18, 
and laterally across final passivation layer 12. Conductive strap 16 
terminates thereon preferably at an end 22 disposed beneath test 
protrusion 20 at a point laterally displaced from wire bond pad 28. Test 
protrusion 20 resides directly on conductive strap 16, and preferably, on 
a portion of final passivation layer 12 adjacent to conductive strap 16. 
Conductive strap 16 has a tapered width from a middle section 30 to end 22 
beneath test protrusion 20. This tapering allows increased adherence of 
test protrusion 20 to final passivation layer 12. Because test protrusion 
20 is preferably not removed from the semiconductor wire bond die after 
testing, good adherence of test protrusion 20 to the semiconductor wire 
bond die is important to prevent inadvertent detachment of the test 
protrusion during testing, burning-in, dicing, or packaging. 
The width of middle section 30 of conductive strap 16 is shown narrower 
than that covering wire bond pad 28. However, middle section 30 may have 
any width and is not limited to a width less than that contacting wire 
bond pad 28 or greater than that at end 22. 
As shown in FIG. 2, additive test structure 11 of the present invention is 
disposed above a semiconductor wire bond die comprising a semiconductor 
substrate having a region of active circuitry 24 associated therewith, 
metallization levels 26 electrically connected to active circuitry region 
24, and wire bond pad 28 disposed above metallization levels 26. Wire bond 
pad 28 is electrically connected to active circuitry region 24 through 
metallization levels 26. Wire bond pad 28 has an upper surface 29 above 
the lower metallization levels. 
An adhesive conductive film 23 comprising a layer or layers of a conductive 
metal may be interposed between solderable test protrusion 20 and 
conductive strap 16 and between solderable test protrusion 20 and exposed 
surface 15 of final passivation layer 12 in order to increase adherence of 
solderable test protrusion 20 thereto. Preferably, a first layer of 
chromium or titanium is used which is known to adhere well to the 
aforementioned passivation layers. However, solderable metals, such as 
those used to form solderable test protrusion 20, do not adhere well to 
chromium or titanium. Thus, in addition, a metallic layer or layers which 
adhere well to the underlying chromium or titanium first layer and 
solderable test protrusion 20 are interposed between solderable test 
protrusion 20 and the first layer to facilitate adherence. Preferably, a 
layer of copper on the chromium or titanium first layer, followed by a 
layer of gold on the copper layer is used. However, the present invention 
is not limited to the use of the aforementioned metals, and additional 
metals that may be used to form an adhesive conductive film will be 
obvious to those skilled in the art. 
FIG. 3a is a top plan view of a semiconductor wafer 32 comprised of a 
plurality of semiconductor wire bond dies 34. Surrounding each 
semiconductor wire bond die 34 is a kerf region 36. 
FIG. 3b is an enlarged view of FIG. 3a illustrating two rows, each of a 
series of four semiconductor wire bond dies 34. The underlying region of 
active circuitry is contained within boundary 35 of each wire bond die 34, 
with kerf region 36 surrounding each die 34. A plurality of additive test 
structures 11 reside on each semiconductor wire bond die 34, with each 
additive test structure being connected to a corresponding wire bond pad. 
Additive test structures 11 are spaced apart so as to be electrically 
isolated. Each additive test structure 11 is disposed entirely over the 
active circuitry of the die such that dicing through kerf 36 may be done 
without severing any additive test structure 11. Thus, additive test 
structures 11 may remain on the semiconductor wire bond dies without 
impacting circuit performance upon dicing. Each individual wire bond die 
34 diced from wafer 32 forms a semiconductor wire bond chip that will have 
a plurality of additive test structures 11 thereon. 
The method for testing a semiconductor wire bond die in accordance with the 
present invention includes forming the above-discussed additive test 
structure 11. Generally, conductive strap 16 of structure 11 is formed on 
the die by depositing a metallization layer, e.g., comprising a layer of 
aluminum or a layer of aluminum over a layer of titanium, onto exposed 
surface 15 of final passivation layer 12. The metallization layer is then 
patterned employing available techniques, such as additive lift-off or 
reactive-ion-etching. The metallization layer is deposited to a thickness 
sufficient for conductive strap 16 to overlay sloped upper surface 18. For 
example, where aluminum over titanium is used as the metallization layer, 
an aluminum layer having a thickness of about 4 .mu.on a layer of titanium 
having a thickness of about 1000.ANG. is sufficient. 
Solderable conductive test protrusion 20, such as a solder ball or gold 
bump, is then formed on conductive strap 16, adjacent end 22 and on final 
passivation layer 12. However, conductive adhesive film 23 may be 
deposited prior to formation of solderable conductive test protrusion 20 
to aid in adhesion of solderable conductive test protrusion 20 to final 
passivation layer 12. 
Testing of die circuitry is performed after electrically connecting an 
external testing connector (not shown) directly to solderable test 
protrusion 20. Testing includes, but is not limited to, burning-in of the 
semiconductor wire bond die followed by full functionality ac testing. 
After testing, the external test connector is removed from solderable test 
protrusion 20. 
As stated above in relation to FIGS. 3a and 3b, dicing of individual 
semiconductor wire bond dies 34 from wafer 32 may be done after testing 
without removing additive test structures 11 from dies 34. This is because 
the entire additive test structure 11 of the invention resides above the 
active circuitry of the die and does not extend into wafer kerf area 36. 
Therefore, dicing through kerf area 36 does not cut through any portion of 
additive structure 11 exposing die circuitry, and the need for removal of 
the added elements of structure 11 is eliminated. Subsequent wire bond 
electrical connection to wire bond pad 28 is facilitated through provision 
of an upper surface 17 on conductive strap 16. 
The method of the invention can also include fabricating the semiconductor 
wire bond die to be tested. As shown in FIG. 2, active circuitry 24 is 
defined in a semiconductor substrate along with a plurality of wire bond 
pads 28 electrically connected thereto through metallization levels 26. A 
final passivation layer 12 comprising a polyimide, silicon dioxide, or 
silicon nitride is then formed above the active circuitry 24 and 
metallization levels 26, and a plurality of apertures 13 is etched through 
final passivation layer 12 exposing each wire bond pad 28. Additive test 
structure 11 is then formed on exposed surface 15 of final passivation 
layer 12 and on upper surface 29 of wire bond pad 28. 
While the invention has been described in detail herein in accordance with 
certain preferred embodiments thereof, many modifications and changes 
therein may be effected by those skilled in the art. Accordingly, it is 
intended by the appended claims to cover all such modifications and 
changes as fall within the true spirit and scope of the invention.