Method for mounting a semiconductor chip on a carrier

A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

TECHNICAL FIELD

This invention relates to a method for mounting a semiconductor chip on a carrier, in particular, a leadframe.

BACKGROUND

Semiconductor device manufacturers are constantly striving to increase the performance of their products, while decreasing their cost of manufacture. A cost intensive area in the manufacture of semiconductor devices is packaging the semiconductor chips. As those skilled in the art are aware, integrated circuits are fabricated in wafers, which are then singulated to produce semiconductor chips. Subsequently, the semiconductor chips may be mounted on electrically conductive carriers, such as leadframes. During the mounting process, the semiconductor chip may be subject to thermal stress which may damage the semiconductor chip.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements.

Devices containing semiconductor chips are described below. The semiconductor chips may be of different types, may be manufactured by different technologies and may include, for example, integrated electrical, electro-optical or electro-mechanical circuits or passives. The integrated circuits may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, memory circuits or integrated passives. Furthermore, the semiconductor chips may be configured as so-called MEMS (micro-electro mechanical systems) and may include micro-mechanical structures, such as bridges, membranes or tongue structures. The semiconductor chips may be configured as sensors or actuators, for example, pressure sensors, acceleration sensors, rotation sensors, microphones etc. Moreover, the semiconductor chips may be configured as power semiconductor chips, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors or power diodes. In particular, semiconductor chips having a vertical structure may be involved, that is to say that the semiconductor chips may be fabricated in such a way that electric currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. A semiconductor chip having a vertical structure may have contact pads, in particular, on its two main surfaces, that is to say on its top side and bottom side. In particular, power semiconductor chips may have a vertical structure. By way of example, the source electrode and gate electrode of a power MOSFET may be situated on one main surface, while the drain electrode of the power MOSFET is arranged on the other main surface. The semiconductor chips need not be manufactured from specific semiconductor material, for example, Si, SiC, SiGe, GaAs, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors.

The semiconductor chips may have contact pads (or electrodes or contact elements) which allow electrical contact to be made with the integrated circuits included in the semiconductor chips. The contact pads may include one or more metal layers which are applied to the semiconductor material of the semiconductor chips. The metal layers may be manufactured with any desired geometric shape and any desired material composition. The metal layers may, for example, be in the form of a layer covering an area. Any desired metal or metal alloy, for example, aluminum, titanium, tungsten, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium, may be used as the material. The metal layers need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the metal layers are possible. The contact pads may be situated on the active main surfaces of the semiconductor chips or on other surfaces of the semiconductor chips.

Solder material may be deposited on the semiconductor chips. For example, AuSn, AgSn, CuSn, Sn, AgIn, In, or CuIn may be used as the solder material. A surface of the solder material may have a certain roughness.

The semiconductor chips may be placed on carriers. The semiconductor chips may be pressed on the carriers such that solder material, which has previously been deposited on the semiconductor chips, is deformed and a form-closed joint between the semiconductor chips and the carriers is produced. The carriers may be of any shape, size and material. During the fabrication of the devices the carriers may be connected to each other. The carriers may also be made from one piece. The carriers may be connected among each other by connection means with the purpose of separating some of the carriers in the course of the fabrication. Separation of the carriers may be carried out by mechanical sawing, a laser beam, cutting, stamping, milling, etching or any other appropriate method. The carriers may be electrically conductive. They may be entirely fabricated from metals or metal alloys, in particular, copper, copper alloys, iron nickel, aluminum, aluminum alloys, steel, stainless steel or other appropriate materials. The carriers may be, for example, a leadframe or a part of a leadframe. Furthermore, the carriers may be plated with an electrically conductive material, for example, copper, silver, iron nickel or nickel phosphorus. In one embodiment, the carrier is a composite substrate, for example, a DCB (Direct Copper Bond), which is a ceramic substrate with copper layers on its top and bottom surface.

The devices described below may include external contact pads (or external contact elements), which may be of any shape and size. The external contact pads may be accessible from outside the devices and may thus allow electrical contact to be made with the semiconductor chips. Furthermore, the external contact pads may be thermally conductive and may serve as heat sinks for dissipating the heat generated by the semiconductor chips. The external contact pads may be composed of any desired electrically conductive material, for example, of a metal, such as copper, aluminum or gold, a metal alloy or an electrically conductive organic material. Solder material, such as solder balls or solder bumps, may be deposited on the external contact pads.

The semiconductor chips or at least parts of the semiconductor chips may be covered with an encapsulation material, which may be electrically insulating and which may form an encapsulation body. The encapsulation material may be any appropriate duroplastic, thermoplastic or thermosetting material or laminate (prepreg) and may contain filler materials. Various techniques may be employed to encapsulate the semiconductor chips with the encapsulation material, for example, compression molding, injection molding, powder molding, liquid molding or lamination. Heat and/or pressure may be used to apply the encapsulation material.

FIGS. 1A-1Cschematically illustrate a method for mounting a semiconductor chip on a carrier.

FIG. 1Aschematically illustrates a semiconductor chip10having a first main surface11and a second main surface12opposite to the first main surface11. A layer of solder material13is deposited on the first main surface11of the semiconductor chip10. The layer of the solder material13, in particular a surface14of this layer facing away from the first main surface11of the semiconductor chip10, may have a roughness of at least 1 μm.

FIG. 1Bschematically illustrates a carrier15on which the semiconductor chip10is placed with the first main surface11of the semiconductor chip10facing the carrier15. The semiconductor chip10is pressed on the carrier15with a force F such that a pressure of at least 1 Newton per mm2of surface area of the first main surface11is applied.

FIG. 1Cschematically illustrates that the solder material13is heated to a temperature T in order to attach the semiconductor chip10to the carrier15firmly.

FIGS. 2A-2Bschematically illustrate a method for depositing solder material on a semiconductor chip.

FIG. 2Aschematically illustrates the semiconductor chip10in cross-section with its first main surface11facing upwards and its second main surface12facing downwards. A contact pad, which allows electrical contact to be made with the integrated circuits included in the semiconductor chip10, may be located on the first main surface11. The contact pad may be a doped region in the semiconductor material. According to one embodiment, the semiconductor chip10shown inFIG. 2Ais still part of a semiconductor wafer. According to another embodiment, the semiconductor chip10has already been singulated from the semiconductor wafer.

FIG. 2Bschematically illustrates a layer of solder material13deposited on the first main surface11of the semiconductor chip10. The solder material13covers the contact pad located on the first main surface11of the semiconductor chip10and, in particular, may cover the entire first main surface11. The surface14of the solder material13has a certain minimum roughness. For example, the surface14may have a roughness of at least 1 μm or 1.5 μm or 2 μm. The solder material13may contain any appropriate material, for example, Sn, AuSn, AgSn, CuSn, AgIn, In, or CuIn. If the semiconductor chip10is still in the wafer bond during the deposition of the solder material13, the semiconductor chip10is singulated from the semiconductor wafer after the deposition of the solder material13.

In one embodiment, the solder material13is deposited by using a sputtering process. In this case, the deposition rate is set to such a value that a desired surface roughness of the deposited solder material13is obtained.

In one embodiment, the solder material13is deposited by an electrochemical deposition process. For that purpose, a solution containing solder particles is applied to the semiconductor chip10, and an appropriate voltage is applied between the semiconductor chip10and a reference electrode such that the solder particles deposit on the first main surface11of the semiconductor chip10. In addition, the solution contains additives which also deposit on the first main surface11. The solder layer13does not grow at locations where the additives have deposited which leads to the rough surface of the solder layer13.

In one embodiment, the first main surface11of the semiconductor chip10has a certain surface roughness, which may, for example, be produced by an etching step. The layer of the solder material13, which is subsequently deposited on the first main surface11, has the same or a similar roughness than the first main surface11.

FIG. 3illustrates an idealized model of the surface roughness of the layer made of the solder material13. In this model, the surface14of the layer has peaks16having an average height h and an average peak-to-peak distance d. The wave length of the roughness of the surface14may be in the order of the average peak height h. The wave length may be also significantly smaller than the dimensions of the first main surface11. The average peak height h may be in the range from 1 μm to 5 μm and, in particular, in the range from 1 μm to 2 μm. The average peak-to-peak distance d may be in the range from 2 μm to 10 μm and, in particular, in the range from 3 μm to 5 μm. In particular, these values for the average peak height h and the average peak-to-peak distance d are valid when the first main surface11has a size of up to 10 mm2. For larger surface areas the parameters of the surface roughness can be adapted. In one embodiment, the surface roughness of the layer made of the solder material13is characterized by the average peak height h. In one embodiment, the surface roughness of the layer made of the solder material13is characterized by the average peak height h and the average peak-to-peak distance d.

In one embodiment, the solder material13applied to the semiconductor chip10has a certain ductility. Ductility is a mechanical property that describes the extent in which solid materials can be plastically deformed without fracture. A measure for the ductility is the yield stress or the yield strength. The yield stress is the stress at the yield point. In practice, the yield stress is chosen such that it causes a permanent strain of 0.002. The yield strength is defined as the yield stress, which is actually the stress level at which a permanent deformation of 0.2% of the original dimension of the material happens, and is defined as the stress level at which a material can withstand the stress before it is deformed permanently. In one embodiment, the yield stress of the solder material13deposited on the semiconductor chip10has a yield stress in the range from 10 MPa to 200 MPa. In one embodiment, the yield strength of the solder material13deposited on the semiconductor chip10has a yield strength in the range from 10 MPa to 200 MPa.

The solder material13may be deposited directly onto the semiconductor material of the semiconductor chip10as illustrated inFIG. 2B.

FIG. 4schematically illustrates an embodiment where one or more metal layers are arranged between the semiconductor material of the semiconductor chip10and the layer of the solder material13. InFIG. 4metal layers20,21and22are deposited on the first main surface11of the semiconductor chip10before the solder material13is applied to the metal layer22. The metal layers20-22may be deposited by a vacuum deposition method, such as sputtering, or other appropriate physical or chemical deposition methods. Each of the metal layers20-22may have a thickness in the range from 50 to 300 nm, but may also be thinner or thicker. Aluminum, titanium, tungsten, gold, silver, copper, palladium, platinum, nickel, chromium, nickel vanadium or other appropriate metals or metal alloys may be used as the materials for the metal layers20-22. In one embodiment, one or more additional metal layers are arranged between the metal layers20and21and/or the metal layers21and22.

The metal layer20may serve to make an electrical contact to the semiconductor chip10. The function of the metal layer21may be that of a diffusion barrier which protects the semiconductor material of the semiconductor chip10from the solder material13during the soldering process. The metal layer22may function as an adhesion layer, which enables the solder material13to adhere to the semiconductor chip10.

According to one embodiment, the semiconductor chip10has a vertical structure and thus has contact pads or electrodes on both main surfaces11and12. The semiconductor chip10shown inFIG. 4has contact pads24and25located on the second main surface12opposite to the first main surface11. The contact pads24and25may include one or more metal layers.

The semiconductor chip10may, for example, be a power semiconductor chip, such as a power transistor, a power diode or an IGBT. In the case of a power MOSFET, the contact pad located on the first main surface11is a drain electrode, and the contact pads24and25are source and gate electrode, respectively.

FIG. 5shows an SEM (scanning electron microscope) image of a semiconductor chip10as an example of the embodiment illustrated inFIG. 4. The following layers are deposited on the first main surface11of the semiconductor chip10: a metal layer20, a metal layer21, a metal layer22and a layer of solder material13and having a rough surface14.

FIG. 6illustrates a schematic view of a method for mounting the semiconductor chip10on the carrier15.FIG. 6shows a die bonder30that picks up a single semiconductor chip10and places the semiconductor chip10on a carrier15. The carrier15is positioned on a conveyor31. The conveyor31is, for example, driven by a step motor and moves the carrier15together with the semiconductor chip10in a direction x shown inFIG. 6. After the placement of the semiconductor chip10on the carrier15, the carrier15and the semiconductor chip10pass through a tunnel furnace32. The temperature profile of the tunnel furnace32is also shown inFIG. 6. A temperature profile which is different from the tunnel profile shown inFIG. 6may also be used. The temperature profile of the tunnel furnace32may, for example, include a portion with a rising temperature and a subsequent portion with a declining temperature.

FIGS. 7A-7Eschematically illustrate the steps of the method ofFIG. 6in more detail.

FIG. 7Aschematically illustrates the die bonder30, which picks up the semiconductor chip10at a loading position and moves the semiconductor chip10to the bonding position. The die bonder30holds the semiconductor chip10with its second main surface12such that the first main surface11of the semiconductor chip10and thus the layer of the solder material13face towards the carrier15. In the embodiment ofFIG. 7A, the solder material13is directly attached to the semiconductor chip10. It may also be provided that one or more metal layers are arranged between the semiconductor chip10and the solder material13as illustrated, for example, inFIG. 4or5.

The carrier15may be made of an electrically conductive material, such as a metal or metal alloy, for example, copper, copper alloys, iron nickel or other appropriate materials. The carrier15may be a leadframe or a part of a leadframe, such as a die pad. Furthermore, the carrier15may be coated with an electrically conductive material, for example, copper, silver, iron nickel or nickel phosphorus. The carrier15has a surface33, on which the semiconductor chip10is placed. In one embodiment, the carrier15is a composite substrate, for example, a DCB including a ceramic substrate and copper layers arranged on the top and the bottom surface of the ceramic substrate.

FIG. 7Bschematically illustrates the die bonder30, which places the semiconductor chip10on the surface33of the carrier15. The die bonder30applies a force F onto the semiconductor chip10such that the semiconductor chip10is pressed on the carrier15. The force F may be applied for at least 10 ms. It is also possible to apply the force F for much longer times. Since the process step illustrated inFIG. 7Bdoes not involve a temperature step, the die attach time may be relatively short.

The force F causes a pressure on the solder material13of at least 1 Newton per mm2of the surface area of the first main surface11. It may also be provided that a higher pressure is generated, for example, a pressure in the range from 3 to 100 Newton per mm2of the surface area of the first main surface11. In one embodiment, the pressure may be higher than 2 or 3 or 5 or 10 Newton per mm2.

Due to the rough surface14of the solder material13, only some spots of the surface14(i.e., the peaks16shown inFIG. 3) are in contact with the carrier15when the semiconductor chip10is placed on the carrier15. The pressure on the solder material13applied by the die bonder30is high enough to deform the solder material13locally and to produce a mechanical connection between the semiconductor chip10and the carrier15. In particular, the pressure on the solder material13causes the portion of the solder material13that is in contact with the carrier15to penetrate into grooves in the surface33of the carrier15, which are due to the manufacturing of the carrier15. Thus the surface14of the solder material13adapts to the shape of the surface33of the carrier15. This facilitates a mechanical bond, in particular a form-closed joint of the semiconductor chip10and the carrier15.

The mechanical connection between the semiconductor chip10and the carrier15ensures that there is no shift in the position of the semiconductor chip10with respect to the carrier15when the step motor moves the conveyor31forward.

FIG. 7Cschematically illustrates that the die bonder30is released from the semiconductor chip10, and subsequently the carrier15together with the semiconductor chip10are introduced into the tunnel furnace32to a position x1(see also the temperature profile inFIG. 6). At the position x1the solder material13is exposed to a temperature T1which is lower than the melting temperature Tmeltof the solder material13(the melting temperature Tmeltof the solder material13is indicated inFIG. 6). The temperature T1causes solid state diffusion at the interface between the solder material13and the carrier15and leads to the formation of an intermetallic phases34. The intermetallic phases34at the interface between the solder material13and the carrier15have a melting temperature, which is higher than the melting temperature Tmeltof the solder material13.

FIG. 7Dschematically illustrates the semiconductor chip10and the carrier15at a position x2in the tunnel furnace32. At the position x2the solder material13is exposed to a temperature T2which is higher than the melting temperature Tmeltof the solder material13, which causes the remaining solder material13to melt. The intermetallic phases34, however, do not melt at the temperature T2and thus hold the semiconductor chip10in place during this process step. The temperature T2may be 10-20° C. higher than the melting temperature Tmeltof the solder material13, i.e., the temperature T2may be in the range from Tmelt+10° C. to Tmelt+20° C. In particular, the temperature T2may be higher than Tmelt+20° C. For example, if tin is used as the solder material13, which has a melting temperature Tmeltof 232° C., the temperature T2may be around 250° C.

FIG. 7Eschematically illustrates the semiconductor chip10and the carrier15at a position x3in the tunnel furnace32. At the position x3the solder material13is exposed to a temperature T3which is higher than the melting temperature Tmeltof the solder material13. All the low-melting solder material13has completely transformed at this stage, i.e., it has passed completely into an intermetallic phase35. The metallic joint between the semiconductor chip10and the carrier15produced by the intermetallic phase35is able to withstand high temperatures, is highly mechanically stable and exhibits a high electrical and thermal conductivity.

The time the semiconductor chip10and the carrier15are exposed to the temperature profile ofFIG. 6in the tunnel furnace32may be higher than 10 s and, in particular, higher than 60 s. It may be provided that the temperature in the tunnel furnace32is lower than Tmelt+100° C. or Tmelt+50° C. or Tmelt+30° C. or Tmelt+25° C. or Tmelt+20° C., wherein Tmeltis the melting temperature of the used solder material13. The temperature in the tunnel furnace32may, for example, be lower than 800° C. or 700° C. or 600° C. or 500° C. or 400° C. or 300° C. Due to the low temperature which is necessary to bond the semiconductor chip10to the carrier15, only a little stress is induced into the system of semiconductor chip10and carrier15, which leads to an increased reliability. Moreover, the low temperatures lead to only a little thermal expansion of the carrier15and thus ensures an accurate positioning and aligning of the semiconductor chip10. In addition, the production costs are reduced because it is not necessary that the solder material13is highly enriched with gold. The methods described herein also allow a lead-free chip mounting.

FIG. 8illustrates a schematic view of a further method for mounting the semiconductor chip10on the carrier15. Similar to the method ofFIG. 6, the die bonder30picks up the single semiconductor chip10and bonds the semiconductor chip10onto the carrier15by applying a force F as described above in connection withFIGS. 7A-7B. Thereafter, the carrier15and the semiconductor chip10are not passed through the tunnel furnace32, but they are placed in a magazine36. Further carriers15with attached semiconductor chips10may be placed in the magazine36as well. Subsequently, the magazine36and possibly further magazines36are placed in a furnace37where a temperature profile as illustrated inFIG. 6is applied to the solder material13at the interface between the semiconductor chips10and the carriers15.

FIG. 9schematically illustrates an embodiment where the carrier15is a die pad of a leadframe. The semiconductor chip10is attached with its first main surface11to the surface33of the carrier15as illustrated inFIG. 7E. In this embodiment, the semiconductor chip10is a power MOSFET with a source electrode24and a gate electrode25located on its second main surface12. The leadframe further includes leads or pads38and39. The source electrode24and the gate electrode25are electrically coupled to the leads or pads38and39by means of bond wires40and41, respectively, or any other appropriate coupling means, such as metallic clips or layers. The leads or pads38and39may have the function of external contact elements. In addition, the semiconductor chip10may be covered with an encapsulation material.