Liquid crystal display data driver capable of column inversion and 3-column inversion driving method

A liquid crystal display includes a plurality of pixels, a plurality of data lines connected to the plurality of pixels, and a data driver connected to the plurality of data lines, where the data driver supplies data voltage to the plurality of data lines, where the data driver includes a data latch which outputs input image data in response to image data corresponding to the plurality of pixels, wherein the data latch rearranges a sequence of the image data, and a digital-to-analog converting unit which includes a positive digital-to-analog converter which generates a positive data voltage in response to the input image data, and a negative digital-to-analog converter which generates a negative data voltage in response to the input image data.

This application claims priority to Korean Patent Application No. 10-2011-0027612, filed on Mar. 28, 2011, and all the benefits accruing therefrom under 35 U.S.C. §119, the e content of which in its entirety is herein incorporated by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present disclosure relates to a liquid crystal display.

(b) Description of the Related Art

A liquid crystal display, which is one of widely used types of flat panel display, typically includes two display panels on which a field generating electrode, such as a pixel electrode and a common electrode, is disposed and a liquid crystal layer interposed between the two display panels. The liquid crystal display generates an electric field in the liquid crystal layer by applying voltage to the field generating electrode to determine orientations of liquid crystal molecules of the liquid crystal layer and control polarization of incident light, thereby displaying an image.

The liquid crystal display generally includes a pixel including a switching element, typically implemented as a thin film transistor (“TFT”) that is a 3-terminal element, and a display panel provided with display signal lines such as a gate line and a data line. The TFT serves as the switching element that transfers or interrupts data voltage transferred through the data line to a pixel based on a gate signal transferred through the gate line.

A liquid crystal capacitor includes a pixel electrode and a common electrode as two terminals, and the liquid crystal layer interposed between the two electrodes serves as a dielectric material. Charge voltage of the liquid crystal capacitor, i.e., pixel voltage, is determined by a difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode. Orientations of liquid crystal molecules vary depending on the magnitude of the pixel voltage, and polarization of light passing through the liquid crystal layer thereby varies. The polarization variation is shown as variation of transmittance of light by a polarizer attached to the liquid crystal display, and the pixel thereby displays luminance corresponding to a gray of an image signal.

The polarity of the data voltage may be positive or negative. The polarity of the data voltage represents the polarity of the data voltage with respect to the common voltage. The positive data voltage is data voltage of (+) with respect to the common voltage, and the negative data voltage is data voltage of (−) with respect to the common voltage.

When the liquid crystal display is driven, an inversion driving, in which data voltage having a polarity opposite to a polarity of data voltage applied in a predetermined frame is applied in a subsequent frame, is typically used. The inversion driving method includes a column inversion driving and 3-column inversion driving, for example. The column inversion driving is a driving method in which data voltage inverted every column is applied in each frame, and the 3-column inversion driving is a driving method in which the data voltage having the same polarity is applied to three neighboring columns and the data voltage inverted every three columns is applied.

However, the size of a driving circuit of the liquid crystal display may be increase when the 3-column inversion driving is used, and a manufacturing cost may be thereby increased.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide a liquid crystal display using an inversion driving method without increasing the size of a driving circuit.

In an exemplary embodiment of the invention, a liquid crystal display includes: a plurality of pixels; a plurality of data lines connected to the plurality of pixels; and a data driver connected to the plurality of data lines, where the data driver supplies data voltage to the plurality of data lines, and the data driver includes a data latch which outputs input image data in response to image data corresponding to the plurality of pixels, wherein the data latch rearranges a sequence of the image data, and a digital-to-analog converting unit which includes a positive digital-to-analog converter which generates a positive data voltage in response to the input image data, and a negative digital-to-analog converter which generates a negative data voltage in response to the input image data.

According to an exemplary embodiment of the invention, a liquid crystal display is driven using an inversion driving method without increasing the size of a driving circuit.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, an exemplary embodiment of a liquid display according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1shows a case in which an exemplary embodiment of a liquid crystal display is driven by a column inversion driving method according to the invention, andFIG. 2shows a case in which an exemplary embodiment of a liquid crystal display is driven by a 3-column inversion driving method according to the invention.

Referring toFIGS. 1 and 2, the liquid crystal display includes a plurality of pixels arranged in matrix and display signal lines, e.g., a plurality of gate lines G1, G2, . . . , and a plurality of data lines D1, D2, . . . , and the like. Each of the plurality of pixels includes a switching element (not shown), and is electrically connected to a corresponding gate line and a corresponding data line. The gate lines G1, G2, . . . are connected with a gate driver (not shown) to transfer gate voltage that turns on/turns off the switching element. The data lines D1, D2, . . . are connected with a data driver (not shown) to transfer data voltage corresponding to digital image data.

The polarity of the data voltage may be positive or negative. The polarity of the data voltage represents the polarity of the data voltage with respect to common voltage Vcom. The positive data voltage is data voltage of (+) with respect to the common voltage Vcom and the negative data voltage is data voltage of (−) with respect to the common voltage Vcom.

Each of the plurality of pixels corresponds to one among three colors in order to implement a color display. In one exemplary embodiment, for example, three colors may be red R, green G and blue B, but not being limited thereto. Pixels of the same color are arranged on the same column and pixels of three different colors are continuously arranged in a column direction. As shown inFIGS. 1 and 2, a red (R) pixel, a green (G) pixel and a blue (B) pixel may be repeated every three columns, but not being limited thereto.

The liquid crystal display drives the data driver based on a selection signal SEL to transfer data voltage corresponding to the plurality of data lines D1, D2, . . . . The selection signal includes a first selection signal SEL1and a second selection signal SEL2. The first selection signal SEL1directs the inversion driving method of the data driver and the second selection signal SEL2directs a sequence of polarities.

As shown inFIGS. 1 and 2, when the first selection signal SEL1is low L, the data driver is driven by the column inversion driving method and when the first selection signal SEL1is high H, the data driver is driven by the 3-column inversion driving method. In one exemplary embodiment, for example, when the second selection signal SEL2is high, the polarity of the data voltage of the first data line D1is negative and when the second selection signal SEL2is low, the polarity of the data voltage of the first data line D1is positive. In an alternative exemplary embodiment, the first selection signal SEL1and the second selection signal SEL2may be implemented as one selection signal SEL. In one exemplary embodiment, for example, a selection signal of 2 bits may direct both the inversion driving method of the data driver and the sequence of the polarities.

As shown inFIG. 1, the first data line D1transfers negative data voltage R− in frame N, the second data line D2transfers positive data voltage G+, the third data line D3transfers negative data voltage B−, and the data driver is driven by the column inversion driving method. In frame N+1, which is a subsequent frame of frame N, the polarity of the data voltage applied to each of the plurality of pixels is frame-inverted such that the polarity of the data voltage in a current frame, e.g., frame N+1, is opposite to the polarity of the data voltage in a previous frame, e.g., frame N.

In an exemplary embodiment, when the column inversion driving method is used, a column corresponding to one color has a polarity different from polarities of columns corresponding to the other two colors in a three columns corresponding to three colors. As shown inFIG. 1, when the red (R) pixel, the green (G) pixel and blue (B) pixel are repeated every three columns, the polarity of the green (G) pixel has a phase opposite to phases of the red (R) pixel and the blue (B) pixel. In such an embodiment, an amount of a data voltage applied to the green pixel increases, such that greenish may occur. In such an embodiment, the common voltage Vcom (shown inFIG. 9) may be distorted due to asymmetry in amounts of the voltage charged in the pixel.

As shown inFIG. 2, the first data line to the third data line D1to D3transfer negative data voltages R−, G− and B− in frame M, and the fourth data line to the sixth data line D4to D6transfer positive data voltages R+, G+ and B+. In such an embodiment, the data driver is driven by the 3-column inversion driving method. Frame is inversed in frame M+1 which is the subsequent frame.

In an exemplary embodiment, when the 3-column inversion driving method is used, the polarities of each three columns that correspond to three colors are the same. In such an embodiment, the polarities of the data voltages are maintained in the same phase by the 3-column inversion driving method at each three columns that are continuously arranged corresponding to three colors. In such an embodiment when the 3-column inversion driving method is used, asymmetric charging and greenish may be substantially reduced or effectively prevented.

Hereinafter, a data driver which drives using both the column inversion driving method and the 3-column inversion driving method will be described referring toFIGS. 3 and 4. In an exemplary embodiment, the data driver may include a plurality of data driving integrated circuits.FIGS. 3 and 4describe a single data driving integrated circuit for convenience of description.

FIG. 3is a block diagram showing an exemplary embodiment of a data driving integrated circuit of a liquid crystal display according to the invention, andFIG. 4is a block diagram showing an exemplary embodiment of a data latch included in the data driving integrated circuit ofFIG. 3.

Referring toFIG. 3, the data driving integrated circuit510includes a data latch512, a demultiplexing unit516, a digital-to-analog converting unit517, a multiplexing unit518and an output buffer519. The output buffer519is connected to a plurality of data lines, e.g. a first to sixth data lines D1, D2, . . . , D6. InFIG. 3, the data driving integrated circuit510is shown to be connected to only the first data line D1to the sixth data line D6among the plurality of data lines for convenience of description, but the exemplary embodiment is not limited thereto. The data driving integrated circuit ofFIGS. 3 and 4may be similarly applied to the other data lines connected thereto, e.g., the data lines D7, . . . following the sixth data line D6. In such an embodiment, the same data driving integrated circuit may be connected to each of data line sets in which 6 data lines are collected among the plurality of data lines. However, the number of the data lines connected to the data driving integrated circuit510is not limited to 6.

The data driving integrated circuit510receives digital image data DAT for 6 pixels during a first horizontal period1H, generates 6 data voltages for 6 pixels, and supplies data voltage to each of 6 data lines D1, D2, . . . , D6. In such an embodiment, 6 pixels are pixels in the same row among the pixels connected to the first data line D1to the sixth data line D6in the liquid crystal display. The liquid crystal display applies the data voltage to all the pixels to display an image of one frame by repeating such a process for each row every unit horizontal period1H.

Referring toFIG. 4, the data latch512includes a first latch513and a second latch515. The first latch513receives and stores the digital image data DAT for six pixels in sequence and rearranges the sequence of the digital image data DAT corresponding to 6 pixels and sends down the rearranged digital image data DAT to the second latch515. Hereinafter, in regards to the digital image data DAT for 6 pixels, the digital image data corresponding to a pixel of a first column to a pixel of a sixth column are represented by 1, 2, 3, 4, 5 and 6 in sequence. The first latch513rearranges the digital image data DAT for 6 pixels in the sequence of 1, 4, 2, 5, 3 and 6 and sends down the rearranged digital image data DAT to the second latch515. Since the pixels of the same color are repeated every three columns, the data latch512rearranges the sequence of the digital image data for 6 pixels such that the digital image data corresponding to the same color are arranged to be adjacent to each other. In one exemplary embodiment, for example, when the digital image data 1, 2, 3, 4, 5 and 6 of the pixels in the first to sixth columns correspond to R, G, B, R, G and B in sequence, the digital image data 1, 4, 2, 5, 3 and 6 for 6 pixels, the sequence of which is rearranged correspond to a sequence of R, R, G, G, B and B.

InFIG. 4, an exemplary embodiment of the data latch512rearranges the sequence of the digital image data DAT for 6 pixels using two latches, but not being limited thereto.

Referring back toFIG. 3, the data latch512outputs input digital image data IN1, IN4, IN2, IN5, IN3and IN6, the sequence of which is rearranged to the demultiplexing unit516. Herein, IN n (n is a natural number of 1 to 6) represents digital image data of an n-th column among the digital image data DAT for 6 pixels.

Each of the plurality of demultiplexers DEMUX1to DEMUX6is connected with the data latch512through one wire. In such an embodiment, each of the plurality of demultiplexers DEMUX1to DEMUX6is connected with one positive digital-to-analog converter P1, P3or P5and one negative digital-to-analog converter N2, N4or N6through two wires. Each of the plurality of demultiplexers DEMUX1to DEMUX6receives one input digital image data IN1, IN4, IN2, IN5, IN3or IN6from the data latch512and outputs the input digital image data IN1, IN4, IN2, IN5, IN3or IN6to one digital-to-analog converter among the positive digital-to-analog converter P1, P3or P5and the negative digital-to-analog converter N2, N4or N6according to the selection signal SEL. In such an embodiment, each of the plurality of demultiplexers DEMUX1to DEMUX6is a 1-to-2 demultiplexer that receives one input and selectively outputs one output between two outputs.

The digital-to-analog converting unit517receives the input digital image data IN1to IN6and converts the received input image digital image data IN1to IN6into data voltage which is an analog signal. The digital-to-analog converters P1, P3and P5convert the input digital image data into the positive data voltage and the negative digital-to-analog converters N2, N4and N6convert the input digital image data into the negative data voltage.

Each of the plurality of digital-to-analog converters, e.g., a first digital-to-analog converter P1, a second digital-to-analog converter N2, a third digital-to-analog converter P3, a fourth digital-to-analog converter N4, a fifth digital-to-analog converter P5and a sixth digital-to-analog converter N6, is connected to two of the multiplexers, e.g., a first to sixth multiplexers MUX1-MUX6. Each of the plurality of digital-to-analog converters P1, N2, P3, N4, P5and N6transfers the data voltage to the two of the multiplexers connected thereto.

Each of the first digital-to-analog converter P1and the second digital-to-analog converter N2is connected to the first multiplexer MUX1and the fourth multiplexer MUX4, each of the third digital-to-analog converter P3and the fourth digital-to-analog converter N4is connected to the second multiplexer MUX2and the fifth multiplexer MUX5, and each of the fifth digital-to-analog converter P5and the sixth digital-to-analog converter N6is connected to the third multiplexer MUX3and the sixth multiplexer MUX6.

Each of the plurality of multiplexers MUX1to MUX6is connected with one positive digital-to-analog converter, e.g., the first, third and fifth digital-to-analog converter P1, P3, or P5, and one negative digital-to-analog converter, e.g., the second, fourth and sixth digital-to-analog converter N2, N4, or N6. In such an embodiment, each of the plurality of multiplexers MUX1to MUX6is connected to the output buffer519.

Each of the plurality of multiplexers MUX1to MUX6receives the positive data voltage from one positive digital-to-analog converter P1, P3or P5and the negative data voltage from one negative digital-to-analog converter N2, N4or N6, and outputs to the output buffer519one of the output data voltages, e.g., a first to sixth output data voltages OUT1to OUT6, among the positive data voltages and the negative data voltages based on the selection signal SEL. In such an embodiment, each of the plurality of multiplexers MUX1to MUX6is a 2-to-1 multiplexer that selects and outputs one between two inputs.

The output buffer519receives the output data voltages, e.g., first to sixth output data voltages OUT1to OUT6, and supplies the data voltages to the plurality of data lines D1, D2, . . . , D6, respectively.

In an exemplary embodiment, as shown in Table 1 below, the digital-to-analog converters P1, N2, P3, N4, P5and N6may be selected as an output by each of the plurality of demultiplexers DEMUX1to DEMUX6based on the selection signal SEL, and the digital-to-analog converters P1, N2, P3, N4, P5and N6may be selected as an input by each of the plurality of multiplexers MUX1to MUX6based on the selection signal SEL.

Hereinafter, a driving method of a data driver in an exemplary embodiment of the liquid crystal display using an inversion driving method according to the invention will be described referring to Table 1 andFIGS. 5 and 6.

FIG. 5shows an exemplary embodiment of a driving method of a data driver in frame N and frame N+1 of Table 1, andFIG. 6shows an exemplary embodiment of a driving method of a data driver in frame M and frame M+1 of Table 1.

FIGS. 5 and 6show an exemplary embodiment, in which the data driver generates 12 data voltages for 12 pixels during one horizontal period1H and supplies the data voltage to each of 12 data lines. In such an embodiment, two data driving integrated circuits510ofFIG. 3may be used. InFIGS. 5 and 6,12data voltages are shown for convenience of description. In an exemplary embodiment, more than 12 data voltages may be generated using a method substantially similar to the method described inFIGS. 5 and 6. In an exemplary embodiment of the data driver, the data voltage generating method for each 6 pixels is substantially the same when each 6 pixels are in a same row and in 6 neighboring columns among the plurality of pixels arranged in a matrix form. In such an embodiment, since a data voltage generation method of 6 initial pixels connected to 6 data lines is substantially the same as a data voltage generating method of subsequent 6 pixels connected to subsequent 6 data lines, only the data voltage generating method for the 6 initial pixels will now be described for convenience of description.

FIG. 5shows an exemplary embodiment of driving method, in which the data driver is driven by column inversion, andFIG. 6shows an exemplary embodiment of a driving method, in which the data driver is driven by 3-column inversion.

In an exemplary embodiment of the column inversion driving method shown inFIG. 5, the first input digital image data IN1is inputted into the second digital-to-analog converter N2to be converted into negative first output data voltage OUT1− and outputted to a first data line of a group of 6 data lines in frame N, and inputted into the first digital-to-analog converter P1to be converted into positive first output data voltage OUT1+ and outputted to the first data line of the group of 6 data lines in frame N+1.

The fourth input digital image data IN4is inputted into the first digital-to-analog converter P1to be converted into positive fourth output data voltage OUT4+ and outputted to a fourth data line of the group of 6 data lines in frame N, and inputted into the second digital-to-analog converter N2to be converted into negative fourth output data voltage OUT4− and outputted to the fourth data line of the group of 6 data lines in frame N+1.

The second input digital image data IN2is inputted into the third digital-to-analog converter P3to be converted into positive second output data voltage OUT2+ and outputted to a second data line of the group of 6 data lines in frame N, and inputted into the fourth digital-to-analog converter N4to be converted into negative second output data voltage OUT2− and outputted to the second data line of the group of 6 data lines in frame N+1.

The fifth input digital image data IN5is inputted into the fourth digital-to-analog converter N4to be converted into negative fifth output data voltage OUT5− and outputted to a fifth data line of the group of 6 data lines in frame N, and inputted into the third digital-to-analog converter P3to be converted into positive fifth output data voltage OUT5+ and outputted to the fifth data line of the group of 6 data lines in frame N+1.

The third input digital image data IN3is inputted into the sixth digital-to-analog converter N6to be converted into negative third output data voltage OUT3− and outputted to a third data line of the group of 6 data lines in frame N, and inputted into the fifth digital-to-analog converter P5to be converted into positive third output data voltage OUT3+ and outputted to the third data line of the group of 6 data lines in frame N+1.

The sixth input digital image data IN6is inputted into the fifth digital-to-analog converter P5to be converted into positive sixth output data voltage OUT6+ and outputted to a sixth data line of the group of 6 data lines in frame N, and inputted into the sixth digital-to-analog converter N6to be converted into negative sixth output data voltage OUT6− and outputted to the sixth data line of the group of 6 data lines in frame N+1.

In an exemplary embodiment of the 3-column inversion driving method shown inFIG. 6, the first input digital image data IN1is inputted into the second digital-to-analog converter N2to be converted into the negative first output data voltage OUT1− and outputted to the first data line of the group of 6 data lines in frame M, and inputted into the first digital-to-analog converter P1to be converted into the positive first output data voltage OUT1+ and outputted to the first data line of the group of 6 data lines in frame M+1.

The fourth input digital image data IN4is inputted into the first digital-to-analog converter P1to be converted into the positive fourth output data voltage OUT4+ and outputted to the fourth data line of the group of 6 data lines in frame M, and inputted into the second digital-to-analog converter N2to be converted into the negative fourth output data voltage OUT4− and outputted to the fourth data line of the group of 6 data lines in frame M+1.

The second input digital image data IN2is inputted into the fourth digital-to-analog converter N4to be converted into the negative second output data voltage OUT2− and outputted to the second data line of the group of 6 data lines in frame M, and inputted into the third digital-to-analog converter P3to be converted into the positive second output data voltage OUT2+ and outputted to the second data line of the group of 6 data lines in frame M+1.

The fifth input digital image data IN5is inputted into the third digital-to-analog converter P3to be converted into the positive fifth output data voltage OUT5+ and outputted to the fifth data line of the group of 6 data lines in frame M, and inputted into the fourth digital-to-analog converter N4to be converted into the negative fifth output data voltage OUT5− and outputted the fifth data line of the group of 6 data lines in frame M+1.

The third input digital image data IN3is inputted into the sixth digital-to-analog converter N6to be converted into the negative third output data voltage OUT3− and outputted to the third data line of the group of 6 data lines in frame M, and inputted into the fifth digital-to-analog converter P5to be converted into the positive third output data voltage OUT3+ and outputted to the third data line of the group of 6 data lines in frame M+1.

The sixth input digital image data IN6is inputted into the fifth digital-to-analog converter P5to be converted into the positive sixth output data voltage OUT6+ and outputted to the sixth data line of the group of 6 data lines in frame M, and inputted into the sixth digital-to-analog converter N6to be converted into the negative sixth output data voltage OUT6− and outputted to the sixth data line of the group of 6 data lines in frame M+1.

As described above, when the sequence of the digital image data for 6 pixels is rearranged such that image data corresponding to the same color are adjacent to each other, each digital-to-analog converter includes two outputs. In one exemplary embodiment, for example, the first digital-to-analog converter P1includes the output to the first data line and the fourth data line of the group of 6 data lines. In such an embodiment, two outputs are included in each digital-to-analog converter to drive the data driver by the column inversion driving method or the 3-column inversion driving method. Accordingly, each of the multiplexers MUX1to MUX6of the multiplexing unit518ofFIG. 3is the 2-to-1 multiplexer which selects one output between two outputs.

Hereinafter, an exemplary embodiment of a data voltage generating operation according to the inversion driving method of the data driver in which the sequence of the image data is not rearranged will be described with reference toFIGS. 7 and 8.

FIG. 7shows an exemplary embodiment of driving method, in which the data driver is driven by column inversion, andFIG. 8shows an exemplary embodiment of driving method, in which the data driver is driven by 3-column inversion.

In an exemplary embodiment of the column inversion driving method shown inFIG. 7, the first input digital image data IN1is inputted into the second digital-to-analog converter N2to be converted into the negative first output data voltage OUT1− and outputted to the first data line of the group of 6 data lines in frame N, and inputted into the first digital-to-analog converter P1to be converted into the positive first output data voltage OUT1+ and outputted to the first data line of the group of 6 data lines in frame N+1.

The second input digital image data IN2is inputted into the first digital-to-analog converter P1to be converted into the positive second output data voltage OUT2+ and outputted to the second data line of the group of 6 data lines in frame N, and inputted into the second digital-to-analog converter N2to be converted into the negative second output data voltage OUT2− and outputted to the second data line of the group of 6 data lines in frame N+1.

The third input digital image data IN3is inputted into the fourth digital-to-analog converter N4to be converted into the negative third output data voltage OUT3− and outputted to the third data line of the group of 6 data lines in frame N, and inputted into the third digital-to-analog converter P3to be converted into the positive third output data voltage OUT3+ and outputted to the third data line of the group of 6 data lines in frame N+1.

The fourth input digital image data IN4is inputted into the third digital-to-analog converter P3to be converted into the positive fourth output data voltage OUT4+ and outputted to the fourth data line of the group of 6 data lines in frame N, and inputted into the fourth digital-to-analog converter N4to be converted into the negative fourth output data voltage OUT4− and outputted to the fourth data line of the group of 6 data lines in frame N+1.

The fifth input digital image data IN5is inputted into the sixth digital-to-analog converter N6to be converted into the negative fifth output data voltage OUT5− and outputted to the fifth data line of the group of 6 data lines in frame N, and inputted into the fifth digital-to-analog converter P5to be converted into the positive fifth output data voltage OUT5+ and outputted to the fifth data line of the group of 6 data lines in frame N+1.

The sixth input digital image data IN6is inputted into the fifth digital-to-analog converter P5to be converted into the positive sixth output data voltage OUT6+ and outputted to the sixth data line of the group of 6 data lines in frame N, and inputted into the sixth digital-to-analog converter N6to be converted into the negative sixth output data voltage OUT6− and outputted to the sixth data line of the group of 6 data lines in frame N+1.

In an exemplary embodiment of the 3-column inversion driving method shown inFIG. 8, the first input digital image data IN1is inputted into the second digital-to-analog converter N2to be converted into the negative first output data voltage OUT1− and outputted to the first data line of the group of 6 data lines in frame M, and inputted into the first digital-to-analog converter P1to be converted into the positive first output data voltage OUT1+ and outputted to the first data line of the group of 6 data lines in frame M+1.

The second input digital image data IN2is inputted into the fourth digital-to-analog converter N4to be converted into the negative second output data voltage OUT2− and outputted to the second data line of the group of 6 data lines in frame M, and inputted into the third digital-to-analog converter P3to be converted into the positive second output data voltage OUT2+ and outputted to the second data line of the group of 6 data lines in frame M+1.

The third input digital image data IN3is inputted into the sixth digital-to-analog converter N6to be converted into the negative third output data voltage OUT3− and outputted to the third data line of the group of 6 data lines in frame M, and inputted into the fifth digital-to-analog converter P5to be converted into the positive third output data voltage OUT3+ and outputted to the third data line of the group of 6 data lines in frame M+1.

The fourth input digital image data IN4is inputted into the first digital-to-analog converter P1to be converted into the positive fourth output data voltage OUT4+ and outputted to the fourth data line of the group of 6 data lines in frame M, and inputted into the second digital-to-analog converter N2to be converted into the negative fourth output data voltage OUT4− and outputted to the fourth data line of the group of 6 data lines in frame M+1.

The fifth input digital image data IN5is inputted into the third digital-to-analog converter P3to be converted into the positive fifth output data voltage OUT5+ and outputted to the fifth data line of the group of 6 data lines in frame M, and inputted into the fourth digital-to-analog converter N4to be converted into the negative fifth output data voltage OUT5− and outputted to the fifth data line of the group of 6 data lines in frame M+1.

The sixth input digital image data IN6is inputted into the fifth digital-to-analog converter P5to be converted into the positive sixth output data voltage OUT6+ and outputted to the sixth data line of the group of 6 data lines in frame M, and inputted into the sixth digital-to-analog converter N6to be converted into the negative sixth output data voltage OUT6− and outputted to the sixth data line of the group of 6 data lines in frame M+1.

As described above, when the sequence of the image data is not rearranged, each digital-to-analog converter includes three outputs. In one exemplary embodiment, for example, the first digital-to-analog converter P1includes the output to the first data line, the second data line and the fourth data line of the group of 6 data lines. In such an embodiment, three outputs are included in each digital-to-analog converter to drive the data driver by the column inversion driving method or the 3-column inversion driving method. In an exemplary embodiment, a 3-to-1 multiplexer that selects one output among three outputs is included.

In such an embodiment, since the size of the 3-to-1 multiplexer is larger than the size of the 2-to-1 multiplexer by approximately 30 to 40%, the size of the data driver increases, net die decreases, and the price of the data driver increases compared to the exemplary embodiment shown inFIGS. 3 to 6.

In an exemplary embodiment shown inFIGS. 3 to 6, the data driver may be driven by the column inversion driving method or the 3-column inversion driving method without increasing the size of the data driver.

FIG. 9is a block diagram showing an exemplary embodiment of a liquid crystal display according to the invention, andFIG. 10is an equivalent circuit diagram showing a single pixel in an exemplary embodiment of a liquid crystal display according to the invention.

As shown inFIG. 9, an exemplary embodiment of the liquid crystal display includes a liquid crystal panel assembly300, a gate driver400and a data driver500connected to the liquid crystal panel assembly300, a gray voltage generator800connected to the data driver500, and a signal controller600which controls the gate driver400and the data driver500.

The liquid crystal panel assembly300includes a plurality of signal lines G1to Gn and D1to Dm, and a plurality of pixels PX connected to the signal lines and arranged substantially in a matrix form when viewed from the equivalent circuit. As shown inFIG. 10, the liquid crystal panel assembly300includes lower and upper panels100and200facing each other and a liquid crystal layer3interposed therebetween.

The signal lines G1to Gn and D1to Dm include a plurality of gate lines G1to Gn that transfers a gate signal (also referred to as a “scan signal’) and a plurality of data lines D1to Dm that transfers data voltage. The gate lines G1to Gn extend substantially in a row direction and are substantially parallel to each other, and the data lines D1to Dm extend substantially in a column direction and are substantially parallel to each other.

Each of the pixels PX, e.g., a pixel PX connected to an i-th gate line G1and a j-th data line Dj, includes a switching element Q connected to corresponding signal lines G1and Dj, and a liquid crystal capacitor Clc and a storage capacitor Cst connected to the corresponding signal lines. In an exemplary embodiment, the storage capacitor Cst may be omitted.

The switching element Q is a 3-terminal element, e.g., a thin film transistor, provided on the lower panel100. A control terminal of the switching element Q is connected to a corresponding gate line G1, an input terminal is connected to a corresponding data line Dj, and an output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst. The thin film transistor may contain polycrystalline silicon or amorphous silicon.

The liquid crystal capacitor Clc is defined by a pixel electrode191of the lower panel100and a common electrode270of the upper panel200as two terminals thereof and the liquid crystal layer3between the two electrodes191and270serves as a dielectric material. The pixel electrode191is connected with the switching element Q and the common electrode270is disposed on a front surface of the upper panel200and receives the common voltage Vcom. In an alternative exemplary embodiment, unlike an exemplary embodiment shown inFIG. 10, the common electrode270may be provided on the lower panel100. In such an embodiment, at least one of the two electrodes191and270may have a linear or rod shape.

The storage capacitor Cst supports the liquid crystal capacitor Clc. In an exemplary embodiment, the storage capacitor Cst may be defined by an additional signal line (not shown) and the pixel electrode191that are provided on the lower panel100and overlapping each other with an insulator interposed therebetween, and predetermined voltage, e.g., the common voltage Vcom may be applied to the additional signal line. In an alternative exemplary embodiment, the storage capacitor Cst may be defined by the pixel electrode191overlapping a gate line of a neighboring pixel with the insulator interposed therebetween.

In an exemplary embodiment, each pixel PX uniquely displays one of primary colors (spatial division) to display a color image or each pixel PX alternately displays the primary colors according to the time (temporal division) to recognize a desired color through the spatial and temporal sum of the primary colors to display a color image. In an exemplary embodiment, the primary colors may include three primary colors of red, green and blue.FIG. 10shows an exemplary embodiment of a pixel using the spatial division. In such an embodiment, each pixel PX includes a color filter230to display one of the primary colors in the region of the upper panel200corresponding to the pixel electrode191. In an exemplary embodiment, three pixels PX that display red, green and blue, respectively form one dot that displays one color. In an exemplary embodiment, the color filter230may be placed over or below the pixel electrode191of the lower panel100.

At least one polarizer (not shown) that polarizes light may be provided on an outer surface of the liquid crystal panel assembly300.

Referring back toFIG. 9, the gray voltage generator800generates two pairs of gray voltage sets associated with transmittance of the pixel PX. One pair of the two pairs of gray voltage sets has a positive value with respect to the common voltage Vcom, and the other pair has a negative value with respect to the common voltage Vcom. The number of gray voltages included in one pair of gray voltage sets generated by the gray voltage generator800may be the same as the number of grays to be displayed by the liquid crystal display.

The data driver500is connected with the data lines D1to Dm of the liquid crystal panel assembly300, and selects the gray voltage from the gray voltage generator800and applies the selected gray voltage to the data lines D1to Dm as the data voltage.

The gate driver400applies the gate signal including the gate-on voltage Von and the gate-off voltage Voff to the gate lines G1to Gn.

In an exemplary embodiment, each of the elements e.g., the gate driver400, the data driver500, the signal controller600and the gray voltage generator800, may be integrated on the liquid crystal panel assembly300together with the signal lines G1to Gn and D1to Dm and the switching element Q. In an alternative exemplary embodiment, the elements400,500,600and800may be mounted directly on the liquid crystal panel assembly300in the form of at least one integrated circuit chip, mounted on a flexible printed circuit film (not shown) to be attached to the liquid crystal panel assembly300in the form of a tape carrier package (“TCP”), or mounted on an additional printed circuit board (not shown). In another alternative exemplary embodiment, the elements400,500,600and800may be integrated as a single chip. In such an embodiment, at least one of the elements400,500,600and800or at least one circuit element configuring the elements400,500,600and800may be positioned outside the single chip.

Hereinafter, an operation of the liquid crystal display will be described in detail.

The signal controller600receives input image signals R, G and B and input control signals that control the display from an external device, e.g., a graphic controller (not shown). The input image signals R, G and B include luminance information of each pixel PX and the luminance has a predetermined number, e.g., 1024 (=210), 256 (=28), or 64 (=26) grays. In an exemplary embodiment, the input control signals may include a vertically synchronization signal Vsync and a horizontal synchronization signal Hsync, a main clock MCLK and a data enable signal DE.

The signal controller600generates and appropriately processes an output image signal DAT based on the input image signals R, G and B and the input control signals and generates a gate control signal CONT1, a data control signal CONT2, and a lighting control signal CONT3. Thereafter, the signal controller600outputs the gate control signal CONT1to the gate driver400, and outputs the data control signal CONT2and the processed output image signal DAT to the data driver500.

The gate control signal CONT1includes a scan start signal STV, which directs a scan start, and at least one clock signal, which controls an output cycle of the gate-on voltage Von. The gate control signal CONT1may further include an output enable signal OE that limits a time for maintaining the gate-on voltage Von.

The data control signal CONT2includes a horizontal synchronization start signal STH indicating a transmission start of the output image signal DAT for one group of pixels PX, a load signal LOAD that directs the application of the data voltage to the liquid crystal panel assembly300, and a data cock signal HCLK. The data control signal CONT2may further include an inversion signal RVS that inverts a voltage polarity (hereinafter, referred to as a “polarity of the data signal” by abbreviating the “voltage polarity of the data signal to the common voltage) of the data voltage to the common voltage Vcom.

In response to the data control signal CONT2from the signal controller600, the data driver500receives a digital output image signal DAT for one group of pixels PX, and selects the gray voltage corresponding to each digital output image signal DAT, and converts the digital output image signal DAT into analog data voltage and applies the analog data voltage to the corresponding data lines D1to Dm.

The gate driver400applies the gate-on voltage Von to the gate lines G1to Gn to turn on the switching element Q connected to the gate lines G1to Gn in response to the gate control signal CONT1from the signal controller600. Then, the data voltage applied to the data lines D1to Dm is applied to the corresponding pixel PX through the switching element Q that is turned on.

A difference between the data voltage applied to the pixel PX and the common voltage Vcom is the charge voltage of the liquid crystal capacitor Clc, i.e., pixel voltage. Orientations of liquid crystal molecules vary depending on the magnitude of the pixel voltage, and thus, polarization of light passing through the liquid crystal layer varies. The variation of the polarization is displayed as variation of transmittance of light by the polarizer on the panel assembly300, and thus, the pixel PX displays luminance displayed by the gray of the image signal DAT.

By repetitively performing the process during each unit horizontal period (also referred to as“1H” and the same as one period of the horizontal synchronization signal Hsync and the data enable signal DE), the gate-on voltage Von is applied sequentially to all the gate lines G1to Gn, and the data voltage is applied to all the pixels PX to display an image of one frame.

When one frame ends, a subsequent frame starts and a state of the inversion signal RVS applied to the data driver500is controlled such that the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the data voltage applied thereto in the previous frame (“frame inversion”). In such an embodiment, even within one frame, the polarity of the data voltage that flows through one data line is changed by the inversion signal RVS (e.g., row inversion and dot inversion) or even the polarities of the data voltages applied to one pixel row may be different from each other (e.g., column inversion and dot inversion).

According to the exemplary embodiments of the invention, a liquid crystal display drives a data driver by a column inversion driving method or a 3-column inversion driving method without increasing the size of the data driver.