MEMORY CONTROL CIRCUIT AND MEMORY CONTROL METHOD

A memory control circuit includes a plurality of main terminal circuits, a monitoring unit, an arithmetic unit, and a memory controller. The main terminal circuits output a plurality of control commands. The monitoring unit generates an operation record based on each of the control commands. The arithmetic unit includes a recurrent neural network module. The arithmetic unit generates a corresponding first feature vector based on the operation record and generates a plurality of second feature vectors based on the first feature vectors corresponding to a plurality of candidate combinations. The recurrent neural network module obtains estimated efficiency information based on the second feature vectors and selects a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination. The memory controller is configured to execute the control command corresponding to each main terminal circuit in the selected main terminal combination for a memory.

CROSS-REFERENCE TO RELATED APPLICATION

This non-provisional application claims priority under 35 U.S.C. § 119 (a) to patent application No. 113118453 filed in Taiwan, R.O.C. on May 17, 2024, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Technical Field

The present disclosure relates to a control circuit, in particular, to a memory control circuit and a memory control method.

Related Art

For a memory control element in an electronic circuit system, time required for the memory control element to complete a memory access request of each module in a system is different due to various different conditions such as memory specifications, system and memory clock frequency, architecture and setting of a memory control element, and characteristics of modules that need to access a memory in the system. Since access efficiency of the memory control element and the memory controlled by the memory control element is highly related to system performance, it is necessary to estimate the time required for the memory control element to complete the access request and operating efficiency.

SUMMARY

In view of the above, a memory control circuit coupled to a memory is provided. In an embodiment, the memory control circuit includes a plurality of main terminal circuits, a first monitoring unit, an arithmetic unit, and a memory controller. Each of the main terminal circuits is configured to output a plurality of control commands corresponding to the memory within a time interval. The first monitoring unit is coupled to the main terminal circuits and configured to monitor an operation behavior of each of the control commands on the memory to generate an operation record corresponding to each control command. The arithmetic unit is coupled to the main terminal circuits and the first monitoring unit, and includes a first recurrent neural network module. The arithmetic unit is configured to encode the operation records corresponding to a same main terminal circuit into a first feature vector in time sequence, and generate a plurality of second feature vectors based on at least one of the first feature vectors corresponding to a plurality of candidate combinations. The first recurrent neural network module obtains estimated efficiency information based on the second feature vectors, and selects a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination. The candidate combination is a group composed of a candidate quantity of main terminal circuits selected from the main terminal circuits. The memory controller is coupled to the memory, the main terminal circuits, and the arithmetic unit, and configured to execute the control command corresponding to each of the main terminal circuits in the selected main terminal combination for the memory.

In an embodiment, the memory control circuit further includes a plurality of second recurrent neural network modules, respectively coupled to the corresponding main terminal circuits and the arithmetic unit, where each of the second recurrent neural network modules obtains an operation prediction based on the operation record of each corresponding main terminal circuit.

In an embodiment, the arithmetic unit is configured to encode the operation records and the operation prediction corresponding to a same main terminal circuit into the first feature vector in time sequence.

In an embodiment, the first recurrent neural network module obtains the estimated efficiency information based on the second feature vectors and a historical selected main terminal combination.

In an embodiment, the memory control circuit further includes a second monitoring unit. The second monitoring unit is coupled to the memory and the arithmetic unit, and is configured to monitor an idle state of the memory to obtain an idle record. The first recurrent neural network module selects the candidate combination corresponding to one piece of the estimated efficiency information and the idle record as the selected main terminal combination.

In an embodiment, each of the second recurrent neural network modules performs machine learning based on the operation records and the operation prediction of the corresponding main terminal circuit.

In an embodiment, each of the second recurrent neural network modules obtains the operation prediction based on a predetermined quantity of operation records.

A memory control method is further provided, including: controlling a plurality of main terminal circuits to output a plurality of control commands corresponding to a memory within a time interval; monitoring an operation behavior of each of the control commands on the memory to generate an operation record corresponding to each control command; encoding the operation records corresponding to one of the main terminal circuits into a first feature vector in time sequence, and generating a plurality of second feature vectors based on at least one of the first feature vectors corresponding to a plurality of candidate combinations; and obtaining, by a first recurrent neural network module, estimated efficiency information based on the second feature vectors, and selecting a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination; and executing the control command corresponding to each of the main terminal circuits in the selected main terminal combination for the memory.

Based on the above, according to the memory control circuit and the memory control method of any embodiment, a task schedule of each main terminal circuit can be determined by using a recurrent neural network, so as to optimize operation efficiency (such as read/write efficiency) of the memory. That is, based on the operation record generated by the operation behavior of each main terminal circuit on the memory, the first recurrent neural network module is used to perform prediction to select the candidate combination with the optimal estimated efficiency as the selected main terminal combination, and then the memory controller executes the control command corresponding to each main terminal circuit in the selected main terminal combination for the memory.

DETAILED DESCRIPTION

Referring to FIG. 1, the present disclosure relates to a memory control circuit A. The memory control circuit A is coupled to a memory 10 and includes a plurality of main terminal circuits 20, a first monitoring unit 30, an arithmetic unit 40, and a memory controller 50. The memory controller 50 is coupled to the memory 10, the main terminal circuits 20, and the arithmetic unit 40. In an embodiment, the memory control circuit A includes the memory 10 that is directly or indirectly coupled thereto. In an embodiment, the memory controller 50 includes the memory 10, the main terminal circuits 20, and the arithmetic unit 40 that are directly or indirectly coupled thereto.

Referring to FIG. 1 and FIG. 2, each of the main terminal circuits 20 is configured to output a plurality of control commands corresponding to the memory 10 within a time interval (step S01). In some embodiments, each main terminal circuit 20 is configured to successively output a plurality of control commands corresponding to the memory 10 within a time interval. Referring to FIG. 3, for example, there are 6 control commands in total within a first time interval t1, 6 control commands in total within a second time interval t2, and 5 control commands in total within a third time interval t3. In addition, the quantity of control commands within each time interval is different, and FIG. 3 is only an illustration. In an embodiment, as shown in FIG. 3, the first time interval t1 and the second time interval t2 partially overlap, and therefore the 6 control commands C1-C6 in data transmitted for the first time and the 6 control commands C3-C8 in data transmitted for the second time overlap by four repeated control commands C3-C6. The second time interval t2 and the third time interval t3 partially overlap, and therefore the 6 control commands C3-C8 in the data transmitted for the second time and the 5 control commands C6-C10 in data transmitted for the third time overlap by three repeated control commands C6-C8. In an embodiment, the main terminal circuit 20 is a specifically a direct memory access device (DMA). In an embodiment, the control command is a write command that specifies an operation as a write operation or a read command that specifies an operation as a read operation.

Referring to FIG. 1 and FIG. 2, the first monitoring unit 30 is coupled to each main terminal circuit 20. In an embodiment, the first monitoring unit 30 includes each main terminal circuit 20 that is directly or indirectly coupled thereto. The first monitoring unit 30 is configured to monitor an operation behavior of each of the control commands on the memory 10 to generate an operation record corresponding to each control command (step S02). Referring to FIG. 3, in an embodiment, the operation record includes a plurality of control commands within a time interval. For example, the 6 control commands C1-C6 in total within the first time interval t1 represent a first operation record X1, the 6 control commands C3-C8 in total within the second time interval t2 represent a second operation record X2, and the 5 control commands C6-C10 in total within the third time interval t3 represent a third operation record X3. In an embodiment, the operation record includes a data operation amount, a time interval, and an operation completion time. The data operation amount includes a data reading amount and a data writing amount. The operation completion time includes a data reading completion time and a data writing completion time. In an embodiment, the operation record further includes a read/write address of data.

Referring to FIG. 1, the arithmetic unit 40 is coupled to each main terminal circuit 20 and the first monitoring unit 30, and includes a first recurrent neural network module 41. In an embodiment, the arithmetic unit 40 includes each main terminal circuit 20 and the first monitoring unit 30 that are directly or indirectly coupled thereto. In an embodiment, the first recurrent neural network module 41 includes a long short-term memory (LSTM) module and gated recurrent units (GRUs). The arithmetic unit 40 is configured to encode the operation records corresponding to one of the main terminal circuits 20 into the first feature vector in time sequence. That is to say, as shown in FIG. 1 and FIG. 3, an example in which the plurality of main terminal circuits 20 include a first main terminal circuit 20A, a second main terminal circuit 20B, and a third main terminal circuit 20C is used. The arithmetic unit 40 encodes the operation records X1, X2, X3, . . . , and Xn of the first main terminal circuit 20A into a first feature vector Y=[X1, X2, X3, . . . , Xn] in time sequence, where n is a quantity of main terminal circuits 20. For the remaining main terminal circuits 20B and 20C, details are not described again.

In some embodiments, a parameter combination of the first feature vector is a specified operation type (read or write), a required data operation amount, a read/write address, and a read/write time interval.

To estimate which one or more control commands of the main terminal circuit 20 are most efficient for the memory controller 50 to execute at a next time point, the arithmetic unit 40 determines candidate combinations based on a quantity of sources (the main terminal circuits 20) that can execute the control commands at the next time point. Next, the arithmetic unit 40 generates a plurality of second feature vectors based on the first feature vectors corresponding to a plurality of candidate combinations. An example in which one source executes a control command is used as an example. A first candidate combination is the first main terminal circuit 20A, and the generated first second feature vector is the first feature vector of the first main terminal circuit 20A. A second candidate combination is the second main terminal circuit 20B, and the generated second second feature vector is a first feature vector of the second main terminal circuit 20B. A third candidate combination is the third main terminal circuit 20C, and the generated third second feature vector is a first feature vector of the third main terminal circuit 20C. That is, the arithmetic unit 40 respectively generates three second feature vectors based on the first feature vectors corresponding to the three candidate combinations. For another example, for two main terminal circuits 20 that can execute the control commands at the next time point, as shown in Equation 1, a candidate combination is the first main terminal circuit 20A and the second main terminal circuit 20B, and the generated first second feature vector is a combination of the first feature vector Ya of the first main terminal circuit 20A and the first feature vector Yb of the second main terminal circuit 20B. Another candidate combination is the second main terminal circuit 20B and the third main terminal circuit 20C, and the generated second second feature vector is a combination of the first feature vector of the second main terminal circuit 20B and the first feature vector of the third main terminal circuit 20C. Still another candidate combination is the third main terminal circuit 20C and the first main terminal circuit 20A, and the generated third second feature vector is a combination of the first feature vector of the third main terminal circuit 20C and the first feature vector of the first main terminal circuit 20A. In this way, the arithmetic unit 40 respectively generates three second feature vectors based on the first feature vectors corresponding to the three candidate combinations, and so on. Details are not described again.

Referring to FIG. 1, FIG. 2, FIG. 3, and FIG. 5, the first recurrent neural network module 41 obtains estimated efficiency information based on the second feature vector (step S03), that is, predicts operation efficiency of the candidate combination based on the second feature vector. In some embodiments, the first recurrent neural network module 41 obtains the estimated efficiency information based on each second feature vector or some of the second feature vectors. In some embodiments, the estimated efficiency information is a total estimated operation amount within a time interval, including a total data reading amount and a total data writing amount. Referring to FIG. 5, for example, when the candidate combination is the first main terminal circuit 20A, the total amount of data read/written of the memory 10 controlled by the first main terminal circuit 20A based on the control command within a fourth time interval t4 may be estimated through the first recurrent neural network module 41. Therefore, the first feature vector Y1 formed by each candidate combination is inputted to the first recurrent neural network module 41. Then the first recurrent neural network module 41 selects a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination P1. In an embodiment, the first recurrent neural network module 41 selects a candidate combination corresponding to an optimal piece of the estimated efficiency information as a selected main terminal combination P1, where the optimal estimated efficiency information indicates highest estimated efficiency. In an embodiment, the first recurrent neural network module 41 selects a candidate combination corresponding to an appropriate one piece of the estimated efficiency information as a selected main terminal combination P1. For example, when the first recurrent neural network module 41 determines that the prediction efficiency of the candidate combination of the first main terminal circuit 20A and the second main terminal circuit 20B is optimal, the first main terminal circuit 20A and the second main terminal circuit 20B are selected as the selected main terminal combination P1. The first feature vector Y1 represents the first feature vector formed by the candidate combinations within the first time interval t1, and the selected main terminal combination P1 represents the candidate combination with the optimal estimated efficiency predicted within the second time interval t2. For the remaining first feature vectors Y1-Ym and the selected main terminal combination P1-Pm, details are not described again. In addition, m is a positive integer.

Referring to FIG. 1 and FIG. 2, the memory controller 50 executes the control command corresponding to each main terminal circuit 20 in the selected main terminal combination for the memory 10 (step S04). For example, when the first main terminal circuit 20A and the second main terminal circuit 20B are selected as the selected main terminal combinations, the memory controller 50 executes the control command of the first main terminal circuit 20A and the control command of the second main terminal circuit 20B to operate the memory 10.

In an embodiment of the present disclosure, based on the operation record generated by the operation behavior of each main terminal circuit 20 on the memory 10, the first recurrent neural network module 41 is used to perform prediction to select the candidate combination with the optimal estimated efficiency as the selected main terminal combination, and then the memory controller 50 executes the control command corresponding to each main terminal circuit 20 in the selected main terminal combination for the memory 10. Therefore, in the present disclosure, the first recurrent neural network module 41 is used to determine a task schedule of each main terminal circuit 20, so as to optimize operation efficiency of the memory 10.

Referring to FIG. 1, FIG. 3, and FIG. 4, in an embodiment, the memory control circuit A further includes a plurality of second recurrent neural network modules 60. The second recurrent neural network modules 60 are respectively coupled to each corresponding main terminal circuit 20 and the arithmetic unit 40. Each of the second recurrent neural network modules 60 obtains an operation prediction h0 based on the operation record of each corresponding main terminal circuit 20. In an embodiment, each second recurrent neural network module 60 includes the corresponding main terminal circuit 20 and the arithmetic unit 40 that are directly or indirectly coupled thereto. Referring to FIG. 3, for example, the second recurrent neural network module 60 predicts part of the third operation record X3 (that is, part of the operation commands C7-C10 within the third time interval t3) and predicted operation commands C11-C12 within the fourth time interval t4. Therefore, the operation prediction h0 is prediction of a fourth operation record X4, and the operation prediction h0 includes C7-C12. Referring to FIG. 4, in an embodiment, the second recurrent neural network module 60 first inputs the first operation record X1 and the second operation record X2 for adjustment. Therefore, when the second recurrent neural network module 60 inputs the third operation record X3, prediction accuracy of the fourth operation record X4 may be improved, that is, accuracy of the operation prediction h0 within the fourth time interval t4. Similarly, when the fourth operation record X4 is inputted to the second recurrent neural network module 60, an operation prediction h1 is generated. The operation prediction h1 is prediction of a fifth operation record X5. For a sixth operation record (omitted in the drawing), an operation prediction h2, and so on, details are not described again.

Referring to FIG. 1 and FIG. 3, in an embodiment, the arithmetic unit 40 is configured to encode the operation records and the operation prediction h0 corresponding to one of the main terminal circuits 20 into the first feature vector in time sequence. Therefore, the first feature vector Y=[X1, X2, . . . , Xn, h0]. This enables the first recurrent neural network module 41 to estimate the efficiency based on the operation prediction h0 outputted by the second recurrent neural network module 60, thereby improving prediction accuracy of the estimated efficiency information. In addition, the first recurrent neural network module 41 estimates the efficiency not only based on the operation prediction h0 outputted by the second recurrent neural network module 60 but also based on a historical selected main terminal combination, so as to realize more accurate estimation. Therefore, in an embodiment, the first recurrent neural network module 41 obtains the estimated efficiency information based on the second feature vectors and the historical selected main terminal combination. In an embodiment, the first recurrent neural network module 41 obtains the estimated efficiency information based on the historical selected main terminal combination and each second feature vector or some of the second feature vectors.

Referring to FIG. 1, in an embodiment, the memory control circuit A further includes a second monitoring unit 70 coupled to the memory 10 and the arithmetic unit 40. In an embodiment, the second monitoring unit 70 includes the memory 10 and the arithmetic unit 40 that are directly or indirectly coupled thereto. The second monitoring unit 70 is configured to monitor an idle state of the memory 10 to obtain an idle record, and the idle record includes a refresh time of the memory 10. The first recurrent neural network module 41 selects a candidate combination corresponding to one piece of the estimated efficiency information and the idle record as the selected main terminal combination, so as to prevent the refresh time of the memory 10 from affecting the overall operation efficiency, thereby improving estimation accuracy of the first recurrent neural network module 41. In an embodiment, the first recurrent neural network module 41 selects a candidate combination corresponding to the optimal piece of the estimated efficiency information and the idle record as a selected main terminal combination P1, where the optimal estimated efficiency information indicates highest estimated efficiency. In an embodiment, the first recurrent neural network module 41 selects a candidate combination corresponding to an appropriate one piece of the estimated efficiency information and the idle record as a selected main terminal combination P1.

Referring to FIG. 1, in an embodiment, each second recurrent neural network module 60 performs machine learning based on the operation record and the operation prediction of the corresponding main terminal circuit 20, so as to improve prediction accuracy of the second recurrent neural network module 60.