Semiconductor device including a transistor, and manufacturing method of the semiconductor device

The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transistor that uses an oxide semiconductor layer, a semiconductor device including the transistor, and a manufacturing method of the transistor and the semiconductor device.

2. Description of the Related Art

There are various kinds of metal oxides, which are used for a wide range of applications. Indium oxide is a well-known material and used as a material of a transparent electrode which is needed in a liquid crystal display or the like.

Some metal oxides exhibit semiconductor characteristics. In general, metal oxides serve as insulators; however, it is known that metal oxides can serve as semiconductors depending on the combination of elements included in the metal oxides.

For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like can be given as metal oxides exhibiting semiconductor characteristics, and thin film transistors in which a channel formation region is formed using such the metal oxides are already known (Patent Documents 1 to 4, Non-Patent Document 1).

As the metal oxides, not only single-component oxides but also multi-component oxides are known. For example, InGaO3(ZnO)m(m: natural number) having a homologous series is known as a multi-component oxide semiconductor including In, Ga, and Zn (Non-Patent Documents 2 to 4).

Further, it is proved that an oxide semiconductor formed using an In—Ga—Zn based oxide as described above can be used for a channel layer of a thin film transistor (also referred to as a TFT) (Patent Document 5, Non-Patent Documents 5 and 6).

However, semiconductor characteristics are likely to vary because of damage to the oxide semiconductor due to an etchant or plasma or contamination of an element such as hydrogen to the oxide semiconductor in an element manufacturing process. Accordingly, problems of variation and deterioration in electrical characteristics of the element are caused.

SUMMARY OF THE INVENTION

In view of the above-described problems, it is an object of an embodiment of the present invention to suppress variation and deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor.

In order to achieve the above-described object, an embodiment of the present invention discloses a structure where a p-type silicon layer is provided over and in contact with a surface of an oxide semiconductor layer (back channel side) in a transistor in which a channel layer is formed using an oxide semiconductor. In this case, the p-type silicon layer serves as a protective film for reducing entry of en element such as hydrogen to the oxide semiconductor layer and also serves as a protective film for the oxide semiconductor layer during the manufacturing process, whereby variation and deterioration in electrical characteristics of the transistor can be suppressed. Further, even in the case where oxygen vacancy is generated on the back channel side of the oxide semiconductor layer to generate carriers (electrons), the p-type silicon layer can capture the generated carriers (electrons), so that variation or deterioration in electrical characteristics can be reduced.

Another embodiment of the present invention can have a structure in which a p-type silicon layer is provided in contact with at least a region of an oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.

Another embodiment of the present invention can have a structure in which low-resistance regions functioning as a source region and a drain region are provided in regions of an oxide semiconductor layer, over which a p-type silicon layer is not provided, and a source electrode layer and a drain electrode layer are provided in contact with the low-resistance regions.

Another embodiment of the present invention provides a transistor which includes a gate electrode, a gate insulating layer provided over the gate electrode, an oxide semiconductor layer provided over the gate insulating layer and overlapped with the gate electrode, a p-type silicon layer provided over and in contact with a surface of the oxide semiconductor layer, and a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer. Further, the source electrode layer and the drain electrode layer can be provided over and in contact with part of the surface of the oxide semiconductor layer, over which the p-type silicon layer is not provided. A first low-resistance region functioning as a source region can be provided in a region of the oxide semiconductor layer, which is in contact with the source electrode layer, and a second low-resistance region functioning as a drain region can be provided in a region of the oxide semiconductor layer, which is in contact with the drain electrode layer.

Another embodiment of the present invention provides a transistor which includes a gate electrode, a gate insulating layer provided over the gate electrode, an oxide semiconductor layer provided over the gate insulating layer and overlapped with the gate electrode, a p-type silicon layer provided over and in contact with part of a surface of the oxide semiconductor layer, a first metal oxide layer and a second metal oxide layer provided over and in contact with part of the surface of the oxide semiconductor layer over which the p-type silicon layer is not provided, a source electrode layer which is electrically connected to the first metal oxide layer, and a drain electrode layer which is electrically connected to the second metal oxide layer.

Another embodiment of the present invention provides a transistor which includes a gate electrode, a gate insulating layer provided over the gate electrode, a source electrode layer and a drain electrode layer provided over the gate insulating layer, an oxide semiconductor layer provided over the source electrode layer and the drain electrode layer and provided over the gate electrode with the gate insulating layer interposed therebetween, and a p-type silicon layer provided over and in contact with a surface of the oxide semiconductor layer.

Another embodiment of the present invention provides a manufacturing method of a transistor, which includes the steps of forming a gate electrode over a substrate, forming a gate insulating layer over the gate electrode, forming an oxide semiconductor layer over the gate insulating layer so as to overlap with the gate electrode, forming a p-type silicon layer so as to cover the oxide semiconductor layer, etching the p-type silicon layer to expose part of the oxide semiconductor layer, forming a conductive film over the p-type silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer.

Another embodiment of the present invention provides a manufacturing method of a transistor, which includes the steps of forming a gate electrode over a substrate, forming a gate insulating layer over the gate electrode, forming an oxide semiconductor layer over the gate insulating layer so as to overlap with the gate electrode, forming a p-type silicon layer so as to cover the oxide semiconductor layer, etching the p-type silicon layer to expose part of the oxide semiconductor layer, performing plasma treatment on the exposed part of the oxide semiconductor layer to form low-resistance regions, forming a conductive film over the p-type silicon layer and the oxide semiconductor layer, and etching the conductive film to form a source electrode layer and a drain electrode layer.

In this specification, silicon oxynitride contains more oxygen than nitrogen, and in the case where measurements are conducted using Rutherford backscattering spectrometry (RBS) and hydrogen forward scattering (HFS), silicon oxynitride preferably contains oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 50 at. % to 70 at. %, 0.5 at. % to 15 at. %, 25 at. % to 35 at. %, and 0.1 at. % to 10 at. %, respectively. Further, silicon nitride oxide contains more nitrogen than oxygen, and in the case where measurements are conducted using RBS and HFS, silicon nitride oxide preferably contains oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 5 at. % to 30 at. %, 20 at. % to 55 at. %, 25 at. % to 35 at. %, and 10 at. % to 30 at. %, respectively. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above, where the total number of atoms contained in the silicon oxynitride or the silicon nitride oxide is defined as 100 at. %.

In this specification, a semiconductor device means any device which can function by utilizing semiconductor characteristics, and a display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device. In addition, in this specification, a display device includes a light-emitting device and a liquid crystal display device in its category. The light-emitting device includes a light-emitting element, and the liquid crystal display device includes a liquid crystal element. A light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic electroluminescent (EL) element, an organic EL element, an LED element, and the like.

When “B is formed on A” or “B is formed over A” is explicitly described in this specification, it does not necessarily mean that B is formed in direct contact with A. The description includes the case where A and B are not in direct contact with each other, i.e., the case where another object is interposed between A and B.

According to an embodiment of the present invention, a p-type silicon layer is provided over and in contact with a surface of an oxide semiconductor layer in a transistor in which a channel layer is formed using an oxide semiconductor, whereby deterioration in electrical characteristics of the transistor can be suppressed.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description of the embodiments. It is easily understood by those skilled in the art that modes and details of the present invention can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to description of the embodiments below. Further, structures according to different embodiments can be implemented in combination as appropriate. In the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

In this embodiment, an example of a structure of a transistor included in a semiconductor device will be described with reference to drawings.

A transistor120illustrated inFIGS. 1A to 1Cincludes a gate (including a gate wiring and a gate electrode (hereinafter referred to as a “gate electrode102”)) provided over a substrate100, a gate insulating layer104provided over the gate electrode102, an oxide semiconductor layer108provided over the gate insulating layer104, a p-type silicon layer112provided over and in contact with a surface of the oxide semiconductor layer108, and a source (including a source wiring and a source electrode (hereinafter referred to as a “source electrode layer116a”)) and a drain (including a drain wiring and a drain electrode (also referred to as a “drain electrode layer116b”)) which are electrically connected to the oxide semiconductor layer108(seeFIGS. 1A to 1C).

The oxide semiconductor layer108is provided so that at least part thereof overlaps with the gate electrode102with the gate insulating layer104interposed therebetween, and the oxide semiconductor layer108functions as a layer for forming a channel region of the transistor120(a channel layer).

An oxide material having semiconductor characteristics may be used for the oxide semiconductor layer108. For example, an oxide semiconductor having a structure expressed by InMO3(ZnO)m(m>0) can be used, and an In—Ga—Zn—O based oxide semiconductor is preferably used. Note that M represents one or more of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). As well as the case where only Ga is contained as M, there is a case where Ga and any of the above metal elements except Ga, for example, Ga and Ni or Ga and Fe are contained as M. Moreover, in the oxide semiconductor, in some cases, a transition metal element such as Fe or Ni or an oxide of the transition metal is contained as an impurity element in addition to the metal element contained as M. In this specification, among the oxide semiconductors whose composition formulae are represented by InMO3(ZnO)m(m>0), an oxide semiconductor whose composition formula includes at least Ga as M is referred to as an In—Ga—Zn—O based oxide semiconductor, and a thin film of the In—Ga—Zn—O based oxide semiconductor is referred to as an In—Ga—Zn—O based non-single-crystal film.

As the oxide semiconductor which is applied to the oxide semiconductor layer108, any of the following oxide semiconductors can be applied in addition to the above: an In—Sn—Zn—O based oxide semiconductor; an In—Al—Zn—O based oxide semiconductor; a Sn—Ga—Zn—O based oxide semiconductor; an Al—Ga—Zn—O based oxide semiconductor; a Sn—Al—Zn—O based oxide semiconductor; an In—Zn—O based oxide semiconductor; a Sn—Zn—O based oxide semiconductor; an Al—Zn—O based oxide semiconductor; an In—O based oxide semiconductor; a Sn—O based oxide semiconductor; and a Zn—O based oxide semiconductor.

The p-type silicon layer112is provided over and in contact with the surface of the oxide semiconductor layer108at least in a region that overlaps with the gate electrode102. In addition, the p-type silicon layer112can be provided over part of the surface of the oxide semiconductor layer108, and the source electrode layer116aand the drain electrode layer116bcan be provided in contact with regions of the oxide semiconductor layer108, on which the p-type silicon layer112is not provided. Here, an example where the regions of the oxide semiconductor layer108, on which the p-type silicon layer112is not provided, are provided apart from each other and the source electrode layer116aand the drain electrode layer116bare provided in contact with the regions is described.

Further, the p-type silicon layer112is formed using p-type silicon. Note that the “p-type silicon” here means silicon which includes a p-type impurity element at a concentration of 1×1017atoms/cm3or higher and oxygen and nitrogen each at a concentration of 1×1020atoms/cm3or less. As an example of an impurity imparting p-type, phosphorus and the like can be given. Note that the concentration of impurities included in the p-type silicon layer112can be measured by secondary ion mass spectroscopy (SIMS).

As the crystal state of the p-type silicon layer112, amorphous silicon, microcrystalline silicon, or polycrystalline silicon (polysilicon) can be used. Note that the p-type silicon layer112may include two or more crystal structures among the above crystal structures (e.g., the amorphous structure and the microcrystalline structure (or the polycrystalline structure)).

As a formation method of the p-type silicon layer112, a CVD method, a sputtering method, an evaporation method, a coating method, or the like can be used. The thickness of the p-type silicon layer112can be set to be greater than or equal to 1 nm and less than or equal to 500 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm.

For example, the p-type silicon layer112is formed by a sputtering method in an atmosphere which does not include hydrogen or an atmosphere which includes a small amount of hydrogen such as an argon atmosphere, whereby the concentration of hydrogen contained in the p-type silicon layer112can be reduced. Accordingly, variation in semiconductor characteristics of the oxide semiconductor layer108due to hydrogen contained in the p-type silicon layer112can be reduced.

In the case of forming the p-type silicon layer112by a sputtering method, a direct current (DC) sputtering apparatus (including a pulsed DC sputtering apparatus which applies a bias in a pulsed manner) is preferably used. The DC sputtering apparatus can deal with a substrate with larger size as compared to an RF sputtering apparatus. This is a great advantage as compared to the case of using an insulating layer such as a silicon oxide layer or a silicon nitride layer as a protective layer, because RF sputtering, which has difficulty in processing a large-sized substrate, needs to be used in the case of forming an insulating layer such as a silicon oxide layer or a silicon nitride layer by a sputtering method (in the case of using an insulator as a target).

In the case of forming the p-type silicon layer112with a DC sputtering apparatus, a silicon target into which an impurity imparting p-type such as boron is added can be used.

As illustrated inFIGS. 1A to 1C, the p-type silicon layer112is provided in contact with the back channel side (the surface on the opposite side from the gate electrode102) of the oxide semiconductor layer108, whereby the p-type silicon layer112functions as a protective film and contamination of hydrogen or the like to the oxide semiconductor layer108can be suppressed. As a result, variation in semiconductor characteristics of the oxide semiconductor layer108due to contamination of an element such as hydrogen can be suppressed; accordingly, variation and deterioration in electrical characteristics of a transistor which uses the oxide semiconductor layer108as a channel layer can be suppressed.

Even in the case where oxygen vacancy, due to damage caused by etching, film formation, or the like, is generated on the back channel side of the oxide semiconductor layer108to generate carriers (electrons), the p-type silicon layer112provided in contact with the oxide semiconductor layer108can capture the generated carriers (electrons), so that variation or deterioration in electrical characteristics can be reduced.

In the case where the source electrode layer116aand the drain electrode layer116bare provided over the oxide semiconductor layer108, the p-type silicon layer112can serve as a channel protective layer (a channel stop layer). As compared to the case where the p-type silicon layer112is not formed over the oxide semiconductor layer108(channel-etch type), variation in characteristics caused by exposure of the oxide semiconductor layer108can be suppressed. In the case where the p-type silicon layer112is made to actively serve as a channel protective layer, the p-type silicon layer112is preferably formed dense. For example, the p-type silicon layer112can be formed dense by a CVD method.

The p-type silicon layer112may be provided in contact with a surface of at least a region in which a channel is formed in the oxide semiconductor layer108. In addition, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film may be formed over the p-type silicon layer112. The insulating film provided over the p-type silicon layer112may be formed by film formation using a sputtering method, a CVD method, and the like, or by oxidation (including natural oxidation) or nitridation of a surface of the p-type silicon layer112. The surface of the p-type silicon layer112can be oxidized by plasma treatment in an oxygen atmosphere or nitrided by plasma treatment in a nitrogen atmosphere.

Further, inFIGS. 1A to 1C, the source electrode layer116afunctions as a source of the transistor120, and the drain electrode layer116bfunctions as a drain of the transistor120. Depending on the driving method of the transistor120, the source electrode layer116amight function as a drain and the drain electrode layer116bmight function as a source.

In the structure illustrated inFIGS. 1A to 1C, p-type germanium, p-type silicon germanium produced by adding germanium in silicon, or p-type silicon carbide (SiC), as well as p-type silicon, may be used as a material provided in contact with the surface of the oxide semiconductor layer108.

Next, the effectiveness of the oxide semiconductor layer provided in contact with the silicon layer will be described based on simulation with a calculator. Here, the effectiveness of amorphous silicon (a-Si) and amorphous silicon oxide (a-SiO2) for blocking hydrogen was researched.

First, motion of atoms was tracked by numerically solving equations of motion for each kind of atoms by classical molecular dynamics simulation where the temperature T was set at 27° C. and the pressure P was set at 1 atm. With the use of mean-square displacement of H atoms obtained from the calculation results, the diffusion coefficient D of H atoms was calculated from Einstein relation (Formula 1). As the diffusion coefficient D is larger, diffusion is more likely to be caused.

An a-Si:H model in which 60 H atoms (10 atom %) are added into 540 a-Si atoms (seeFIG. 27A) and an a-SiO2:H model in which 60 H atoms (10 atom %) are added into 540 a-SiO2atoms (seeFIG. 27B) were prepared. Here, three-dimensional periodic boundary conditions are used, which allows calculation of a bulk.

An empirical potential which characterizes the interaction between atoms is defined in the classical molecular dynamics method which is used in this calculation, so that force that acts on each atom is evaluated. For the a-Si:H model, a Tersoff potential was used. For a-SiO2of the a-SiO2:H model, a Born-Mayer-Huggins potential and a Morse potential were used, and for the interaction between a-SiO2and a hydrogen atom (between a silicon atom and a hydrogen atom and between an oxygen atom and a hydrogen atom), a Lennard-Jones potential was used. As a calculation program, a simulation software “Materials Explorer 5.0”, which is manufactured by Fujitsu Limited, was used.

Classical molecular dynamics simulation was performed on each calculation model under the conditions where the temperature T was set at 27° C., the pressure P was set at 1 atm, and the time was set at 1 nsec (time step: 0.2 fsec×5 million steps).

<Calculation Results and Consideration>

The mean-square displacement of H atoms in a-Si and the mean-square displacement of H atoms in a-SiO2, which were obtained from the calculation, are shown inFIG. 28A.FIG. 28Bshows the diffusion coefficients D of H atoms in the calculation models, each of which are obtained from the region where the both slopes in the graph ofFIG. 28Aare substantially constant (70 psec to 100 psec). FromFIG. 28B, it was found that the diffusion coefficient of H atoms in a-Si is smaller than that of H atoms in a-SiO2and H atoms in a-Si are less likely to be diffused than H atoms in a-SiO2. In other words, it seems that an a-Si film has a high effect of preventing entry of hydrogen as compared to an a-SiO2film.

Next, an effect in the case where the silicon layer which is provided in contact with the oxide semiconductor layer108has p-type conductivity is described based on computational simulation.

Structures of thin film transistors used for the calculation are shown inFIGS. 29A to 29D.

A structure (a structure1) shown inFIG. 29Ahas a gate electrode902, a gate insulating layer904provided over the gate electrode902, an oxide semiconductor layer908provided over the gate insulating layer904, and a source and drain electrode layers916aand916bprovided over the oxide semiconductor layer908. The structure1is an assumed ideal structure of a channel-etch type thin film transistor.

A structure (a structure2) shown inFIG. 29Bis the same as the structure shown inFIG. 29Aexcept a point that carriers (electrons) generated on a surface on a back channel side (a surface on the opposite side from the gate electrode902) of the oxide semiconductor layer908by oxygen vacancy or contamination of hydrogen are assumed (damage due to etching, film formation, or the like is assumed).

A structure (a structure3) shown inFIG. 29Chas a gate electrode902, a gate insulating layer904provided over the gate electrode902, an oxide semiconductor layer908provided over the gate insulating layer904, an n-type silicon layer922provided over the oxide semiconductor layer908, and a source and drain electrode layers916aand916bprovided over the oxide semiconductor layer908and the n-type silicon layer922. Note that, in the structure3, carriers (electrons) generated on a surface on the back channel side of the oxide semiconductor layer908by oxygen vacancy or contamination of hydrogen are assumed similarly to the structure2.

A structure (a structure4) shown inFIG. 29Dis almost the same as the structure shown inFIG. 29Cexcept a point that the case where a p-type silicon layer912, not an n-type silicon layer, is provided over the oxide semiconductor layer908(the structure shown inFIGS. 1A to 1C) is assumed. Note that in the structure4, carriers (electrons) generated on the surface on the back channel side of the oxide semiconductor layer908by oxygen vacancy or contamination of hydrogen are assumed similarly to the structures2and3.

InFIGS. 29A to 29D, the gate electrode902was assumed to be a tungsten layer with a thickness of 100 nm, and the work function thereof was assumed to be 4.6 eV. The gate insulating layer904was assumed to be a silicon oxynitride layer with a thickness of 100 nm, and the dielectric constant thereof was assumed to be 4.1. The oxide semiconductor layer908was assumed to be an IGZO layer (an i-layer) with a thickness of 50 nm, and the band gap (Eg), the electron affinity (x), and the intrinsic electron mobility were assumed to be 3.05 eV, 4.3 eV, and 15 cm2/Vs, respectively. The source and drain electrode layers916aand916bwere assumed to be a titanium layer with a thickness of 100 nm, and the work function thereof was assumed to be 4.3 eV.

In the structure3, the n-type silicon layer922was assumed to be an amorphous silicon layer with a thickness of 50 nm, and it was assumed that an impurity element imparting n-type conductivity was added thereto at 1×1017atoms/cm3.

In the structure4, the p-type silicon layer912was assumed to be an amorphous silicon layer with a thickness of 50 nm, and it was assumed that an impurity element imparting p-type conductivity was added thereto at 1×1017atoms/cm3.

In the structures2to4, a donor level which supplies electrons is assumed to exist in a region which is within 10 nm from the surface on the back channel side of the oxide semiconductor layer908, as for the carriers (electrons) assumed to be on the back channel side of the oxide semiconductor layer908. Note that, generally, in the case where a silicon layer is provided in contact with a back channel side of an oxide semiconductor layer (the structures3and4), the silicon layer functions as a protective film and damage to the oxide semiconductor layer can be reduced as compared to a channel-etch type transistor (the structure2); however, here, similar donor levels were assumed in the structures2to4for comparison.

Next, calculation for the structures ofFIGS. 29A to 29Dwas performed using the simulation software “ATLAS” made by Silvaco Data Systems Inc.

Note that in performing the calculation, the structures of the transistors were assumed as shown inFIGS. 30A and 30B. Specifically, the length of the gate electrodes in the channel length direction is 20 μm and the distance between the source and drain electrode layers is 10 μm in the structures1to4. Furthermore, the length of the silicon layer in the channel length direction is 12 μm in the structures3and4as shown in theFIG. 30B. In addition, the channel width W is 100 μm in the structures1to4.

FIG. 31shows results of calculation for current-voltage characteristics of the thin film transistors shown inFIGS. 29A to 29D. Here, Vds=10 V. Note that inFIG. 31, the vertical axis represents source-drain current Ids [A/μm] and the horizontal axis represents a potential difference between a gate and a source Vgs [V].

As shown inFIG. 31, in the ideal structure1where damage to the back channel side of the oxide semiconductor layer908is not assumed, it was confirmed that an Id-Vg curve rose at Vg=0V. On the other hand, in the structure2where damage to the back channel side of the oxide semiconductor layer908is assumed, it was confirmed that the threshold voltage (Vth) of the structure2was shifted toward the minus side and the transistor was normally on.

Further, in the structure3where damage to the back channel side of the oxide semiconductor layer908is assumed and the n-type silicon layer922is provided in contact with the back channel side of the oxide semiconductor layer908, it was confirmed that Vth of the structure3was largely shifted toward the minus side and off leak (leak current when the transistor is off) was high.

On the other hand, in the structure4where damage to the back channel side of the oxide semiconductor layer908is assumed and the p-type silicon layer912is provided in contact with the back channel side of the oxide semiconductor layer908, it was confirmed that semiconductor characteristics closer to those of the structure1which is an ideal structure can be obtained as compared to the structures2and3. This is probably because carriers (electrons) generated on the back channel side of the oxide semiconductor layer are captured in the p-type silicon layer which is provided in contact with the oxide semiconductor layer, whereby deterioration of electrical characteristics of the transistor is suppressed.

Next, in the structure4, the results of calculation which was performed while changing the thickness of the silicon layer and the concentration of the p-type impurity element are shown inFIGS. 32A and 32B. Note that conditions other than the thickness of the silicon layer and the concentration of the impurity element were assumed as the same as those of the structure4. Accordingly, carriers (electrons) generated on the surface on the back channel side of the oxide semiconductor layer908by oxygen vacancy or contamination of hydrogen are assumed as well.

FIG. 32Ashows results of calculation for current-voltage characteristics of the thin film transistors in the case where the concentration of the impurity element imparting p-type conductivity contained in the silicon layer with a thickness of 50 nm is changed.FIG. 32Bshows results of calculation for current-voltage characteristics of the thin film transistors in the case where the concentration of the impurity element imparting p-type conductivity contained in the silicon layer with a thickness of 10 nm is changed.

FromFIGS. 32A and 32B, it was confirmed that Vth of the transistor was shifted toward the plus side as the concentration of the impurity element contained in the silicon layer becomes higher. Further, in the case where the concentration of the impurity element is high, it was confirmed that Vth of the transistor with a larger thickness was more largely shifted toward the plus side.

Next, the shapes of the oxide semiconductor layer108and the p-type silicon layer112in the structure illustrated inFIGS. 1A to 1Cwill be described. Note that in the description below, in the channel width direction, the width of the p-type silicon layer112(Wb) and the width of the oxide semiconductor layer108(Wc) mean the length of the p-type silicon layer112and the length of the oxide semiconductor layer108, respectively. Further, in the channel length direction, the length of the p-type silicon layer112(Lb) and the length of the oxide semiconductor layer108(Lc) mean the length of the p-type silicon layer112and the length of the oxide semiconductor layer108, respectively. Furthermore, the channel length direction means the direction which is generally parallel to the direction in which carriers move in the transistor120(the direction in which the source electrode layer116aand the drain electrode layer116bare connected to each other), and the channel width direction means the direction which is generally perpendicular to the channel length direction.

The transistor illustrated inFIGS. 1A to 1Cis a transistor in the case where the width of the p-type silicon layer112(Wb) is larger than the width of the oxide semiconductor layer108(Wc) and the p-type silicon layer112is provided to extend beyond (to cross) both edges of the oxide semiconductor layer108in the channel width direction. In addition, the length of the p-type silicon layer112(Lb) is smaller than the length of the oxide semiconductor layer108(Lc). Further, two regions in the oxide semiconductor layer108which are not covered with the p-type silicon layer112are provided in the channel length direction, and the source electrode layer116aand the drain electrode layer116bare provided in the two regions that are apart from each other so as to be electrically connected. In this manner, leakage current caused by change in semiconductor characteristics on the surface of the oxide semiconductor layer108can be reduced.

The structure of the transistor of this embodiment is not limited to the one illustrated inFIGS. 1A to 1C.

FIGS. 1A to 1Cillustrate the transistor120in which the length of the oxide semiconductor layer108(Lc) is made large so that the oxide semiconductor layer108extends beyond edges of the gate electrode102in the channel length direction; however, as in a transistor121illustrated inFIGS. 3A and 3B, the length of the oxide semiconductor layer108(Lc) may be made small and the whole region of the oxide semiconductor layer108may be located over the gate electrode102. Note thatFIG. 3Ais a top view andFIG. 3Bis a cross-sectional view taken along line A1-B1ofFIG. 3A.

In the structures ofFIGS. 1A to 1CandFIGS. 3A and 3B, the widths of the source electrode layer116aand the drain electrode layer116b(Wd) may each be larger than the width of the oxide semiconductor layer108(Wc) in region where the source electrode layer116aand the drain electrode layer116boverlap with the oxide semiconductor layer108(seeFIGS. 4A and 4B). In a transistor122and a transistor123illustrated inFIGS. 4A and 4Brespectively, regions of the oxide semiconductor layer108, which the p-type silicon layer112is not in contact with, can be covered with the source electrode layer116aand the drain electrode layer116b; accordingly, there is an advantage that the oxide semiconductor layer108is protected and thereby reliability is improved. Further, contact resistance between the oxide semiconductor layer108and the source and drain electrode layers116aand116bcan be reduced by the increase in the contact area between the oxide semiconductor layer108and the source and drain electrode layers116aand116b.

The widths of the source electrode layer116aand the drain electrode layer116b(Wd) indicate the lengths of the source electrode layer116aand the drain electrode layer116bin the channel width direction.

The widths of the source electrode layer116aand the drain electrode layer116b(Wd) may be larger than the width of the p-type silicon layer112(Wb). Alternatively, only one of the widths of the source electrode layer116aand the drain electrode layer116b(Wd) may be larger than the width of the oxide semiconductor layer108(Wc) (or the width of the p-type silicon layer112(Wb)).

In the structures described in this embodiment, a light-blocking portion such as a black matrix may be provided above and/or below the p-type silicon layer112to shield the p-type silicon layer112from light. In this case, variation in electrical characteristics of a transistor due to irradiation of the p-type silicon layer112with light can be suppressed. In the case where the gate electrode102is formed using a light-blocking material, a light-blocking portion such as a black matrix may be provided over the p-type silicon layer112(on the opposite side from the gate electrode102).

Next, an example of a manufacturing method of the transistor illustrated inFIGS. 1A to 1Cwill be described with reference toFIGS. 2A to 2F.

First, the gate electrode102is formed over the substrate100and the gate insulating layer104is formed over the gate electrode102. Then, an oxide semiconductor layer106is formed over the gate insulating layer104(seeFIG. 2A).

A substrate having an insulating surface may be used as the substrate100, and for example, a glass substrate can be used. Alternatively, as the substrate100, an insulating substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate; a semiconductor substrate which is formed using a semiconductor material such as silicon and whose surface is covered with an insulating material; or a conductive substrate which is formed using a conductor such as metal or stainless steel and whose surface is covered with an insulating material can be used. Further alternatively, a plastic substrate can be used as long as it can withstand heat treatment in a manufacturing process.

The gate electrode102can be formed in the following manner: after a conductive film is formed over an entire surface of the substrate100, the conductive film is etched by a photolithography method.

The gate electrode102can be formed using a conductive material such as aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (W), titanium (Ti), or the like. Note that when aluminum is used alone for the wiring or the electrode, there are problems in that aluminum has low heat resistance and that aluminum is easily eroded, for example. Therefore, it is preferable to use aluminum in combination with a heat-resistant conductive material.

As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc); an alloy containing the above element as its component; an alloy containing a combination of the above elements; or a nitride containing the above element as its component may be used. A film formed using any of these heat-resistant conductive materials and an aluminum (or copper) film may be stacked, so that the wiring and the electrode may be formed.

The gate electrode102may be formed using a material having high conductivity and a light-transmitting property to visible light. As such a material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organoindium, organotin, zinc oxide (ZnO), or the like can be used, for example.

The gate insulating layer104can be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a tantalum oxide film, or the like. Further, any of these films may be stacked. For example, any of these films can be formed by a sputtering method or the like with a thickness of greater than or equal to 10 nm and less than or equal to 500 nm.

The oxide semiconductor layer106can be formed using an In—Ga—Zn—O based oxide semiconductor. In this case, the oxide semiconductor layer106having an amorphous structure can be formed by a sputtering method using an oxide semiconductor target including In, Ga, and Zn (e.g., In2O3:Ga2O3:ZnO=1:1:1).

For example, the conditions of the sputtering method can be set as follows: the distance between the substrate100and the target is 30 mm to 500 mm inclusive, the pressure is 0.01 Pa to 2.0 Pa inclusive, the direct current (DC) power supply is 0.25 kW to 5.0 kW inclusive, the temperature is 20° C. to 200° C. inclusive, the atmosphere is an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen.

Note that a pulse direct current (DC) power supply is preferable in a sputtering method because dust can be reduced and the film thickness can be uniform. The thickness of the oxide semiconductor layer106can be set to greater than or equal to 5 nm and less than or equal to 200 nm.

In the case where an In—Ga—Zn—O based non-single-crystal film is formed as the oxide semiconductor layer106, an insulating impurity may be contained in the oxide semiconductor target including In, Ga, and Zn. The impurity is an insulating oxide typified by silicon oxide, germanium oxide, aluminum oxide, or the like; an insulating nitride typified by silicon nitride, aluminum nitride, or the like; or an insulating oxynitride such as silicon oxynitride or aluminum oxynitride. Any of these insulating oxides and insulating nitrides is added at a concentration at which electrical conductivity of the oxide semiconductor does not decrease.

When the oxide semiconductor layer106contains an insulating impurity, crystallization of the oxide semiconductor layer106can be suppressed, which enables stabilization of characteristics of the thin film transistor. Further, in the case where an impurity such as silicon oxide is contained in the In—Ga—Zn—O based oxide semiconductor, crystallization of the oxide semiconductor or generation of microcrystal grains can be prevented even through heat treatment at 200° C. to 600° C. inclusive.

As the oxide semiconductor which is applied to the oxide semiconductor layer106, any of the following oxide semiconductors can be applied in addition to the above: an In—Sn—Zn—O based oxide semiconductor, an In—Al—Zn—O based oxide semiconductor, an Sn—Ga—Zn—O based oxide semiconductor, an Al—Ga—Zn—O based oxide semiconductor, an Sn—Al—Zn—O based oxide semiconductor, an In—Zn—O based oxide semiconductor, an Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, an In—O based oxide semiconductor, an Sn—O based oxide semiconductor, and a Zn—O based oxide semiconductor. Further, by addition of an impurity which suppresses crystallization to keep an amorphous state to these oxide semiconductors, characteristics of the thin film transistor can be stabilized. As the impurity, an insulating oxide typified by silicon oxide, germanium oxide, aluminum oxide, or the like; an insulating nitride typified by silicon nitride, aluminum nitride, or the like; or an insulating oxynitride such as silicon oxynitride or aluminum oxynitride is applied.

Next, the oxide semiconductor layer106is etched to form the island-shaped oxide semiconductor layer108(seeFIG. 2B). At this time, the oxide semiconductor layer106is etched so that the island-shaped oxide semiconductor layer108remains at least above the gate electrode102.

Then, a p-type silicon layer110is formed so as to cover the oxide semiconductor layer108(seeFIG. 2C).

The p-type silicon layer110can be formed by a sputtering method. In this case, the p-type silicon layer110can be formed by a DC sputtering method using a silicon target to which boron is added, in an argon atmosphere. However, without limitation to this, the p-type silicon layer110may be formed by a CVD method or the like. Depending on the film formation conditions, there is a case where a mixed layer of the oxide semiconductor layer108and the p-type silicon layer110(e.g., an oxide of silicon or the like) is formed thin at an interface between the oxide semiconductor layer108and the p-type silicon layer110.

Next, the p-type silicon layer110is etched to form the island-shaped p-type silicon layer112(seeFIG. 2D). At this time, the p-type silicon layer110is etched so that the island-shaped p-type silicon layer112remains at least in a region that overlaps with the gate electrode102. In addition, the etching of the p-type silicon layer110is performed so as to expose at least part of the oxide semiconductor layer108.

As the etching, wet etching with the use of tetramethylammonium hydroxide (TMAH) can be applied. In this case, etching selectivity of the p-type silicon layer110with respect to the oxide semiconductor layer108is high and the p-type silicon layer110can be favorably etched while the oxide semiconductor layer108is hardly etched. Further, damage to the oxide semiconductor layer108can be reduced.

Note that etching selectivity shows, for example in the case of etching a layer A and a layer B, the difference between etching rates of the layer A and the layer B. Accordingly, a high etching selectivity means that there is a sufficient difference between the etching rates.

Next, a conductive film114is formed over the gate insulating layer104, the oxide semiconductor layer108, and the p-type silicon layer112(seeFIG. 2E).

The conductive film114can be formed by a sputtering method, a vacuum evaporation method, or the like using metal including an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc); an alloy including the above element as a component; or a material including a nitride or the like in which the above element is included.

For example, the conductive film114can be formed to have a single-layer structure of a molybdenum film or a titanium film. The conductive film114may be formed to have a stacked structure and, for example, can be formed to have a stacked structure of an aluminum film and a titanium film. Alternatively, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are sequentially stacked may be used. A three-layer structure in which a molybdenum film, an aluminum film, and a molybdenum film are sequentially stacked may be used. As the aluminum films used for these stacked structures, an aluminum film including neodymium (Al—Nd) may be used. Further alternatively, the conductive film114may be formed to have a single-layer structure of an aluminum film including silicon.

The conductive film114may be formed using a material having high conductivity and a light-transmitting property to visible light. As such a material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organoindium, organotin, zinc oxide (ZnO), or the like can be used for example.

Next, the conductive film114is etched to form the source electrode layer116aand the drain electrode layer116b(seeFIG. 2F). At this time, depending on the etching conditions, the p-type silicon layer112might also be etched and reduced in thickness at the time of etching of the conductive film114. Here, a case where the p-type silicon layer112is also etched and reduced in thickness at the time of etching of the conductive film114is described.

In the above-described step, the p-type silicon layer112functions as a channel protective layer (a channel stop layer) which suppresses etching of the oxide semiconductor layer108when the conductive film114is etched. In some cases, the oxide semiconductor layer108is reduced in thickness at the time of etching of the conductive film114in a region of the oxide semiconductor layer108over which the p-type silicon layer112is not provided.

Thus, by providing the p-type silicon layer112in contact with the oxide semiconductor layer108, contamination of unnecessary elements such as hydrogen to the oxide semiconductor layer108from the outside can be suppressed.

Through the above-described process, the transistor120can be manufactured.

Further, a protective insulating layer may be formed so as to cover the transistor120. For example, a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed by a CVD method, a sputtering method, or the like as the protective insulating layer. Further, after the source electrode layer116aand the drain electrode layer116bare formed, the exposed portion of the p-type silicon layer112may be oxidized (including natural oxidation) or nitrided to form a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film in a region over the p-type silicon layer112, which is located between the source electrode layer116aand the drain electrode layer116b.

In the process ofFIGS. 2A to 2F, after formation of the oxide semiconductor layer108, it is preferable to perform heat treatment at 100° C. to 600° C. inclusive, typically 200° C. to 400° C. inclusive in a nitrogen atmosphere or an air atmosphere. For example, heat treatment can be performed at 350° C. in a nitrogen atmosphere for 1 hour. This heat treatment is important because the heat treatment causes rearrangement at the atomic level of the island-shaped oxide semiconductor layer108and distortion that interrupts carrier movement in the oxide semiconductor layer108can be reduced.

There is no particular limitation on the timing of the heat treatment as long as it is performed after the formation of the oxide semiconductor layer106, and the heat treatment may be performed after the formation of the p-type silicon layer110, the formation of the island-shaped p-type silicon layer112, the formation of the conductive film114, the formation of the source electrode layer116aand the drain electrode layer116b, or the formation of the protective insulating layer. Depending on the conditions or the like of the heat treatment, a mixed layer of the oxide semiconductor layer108and the p-type silicon layer112(e.g., an oxide of silicon or the like) might be formed thin at an interface between the oxide semiconductor layer108and the p-type silicon layer112.

Then, various electrodes and wirings are formed, whereby a semiconductor device including the transistor120is completed.

The case where the p-type silicon layer110is formed after the oxide semiconductor layer108is formed is illustrated inFIGS. 2A to 2F. However, after the oxide semiconductor layer106and the p-type silicon layer110are formed in succession so as to be stacked, they may be patterned into the oxide semiconductor layer108and the p-type silicon layer112, respectively, with a plurality of masks. A manufacturing method in this case will be described with reference toFIGS. 25A to 25E.

First, the gate electrode102is formed over the substrate100, and then the gate insulating layer104is formed over the gate electrode102. Then, the oxide semiconductor layer106and the p-type silicon layer110are sequentially formed to be stacked over the gate insulating layer104, and a resist mask175is selectively formed (seeFIG. 25A). It is preferable that layers of from the gate insulating layer104to the p-type silicon layer110, or from the oxide semiconductor layer106to the p-type silicon layer110be formed in succession.

Next, unnecessary portions of the p-type silicon layer110and the oxide semiconductor layer106are etched using the resist mask175, so that the island-shaped oxide semiconductor layer108and the p-type silicon layer111are formed (seeFIG. 25B). Then, the resist mask175is removed.

Then, a resist mask176is formed over the p-type silicon layer111, and the exposed p-type silicon layer111is etched using the resist mask176; thus, the island-shaped p-type silicon layer112is formed (seeFIG. 25C).

Next, after forming the conductive film114over the gate insulating layer104, the oxide semiconductor layer108, and the p-type silicon layer112(seeFIG. 25D), the conductive film114is etched to form the source electrode layer116aand the drain electrode layer116b(seeFIG. 25E).

Through the above-described process, a transistor124as illustrated inFIGS. 26A to 26Ccan be manufactured.FIGS. 26A to 26Cillustrate the transistor124in the case where the width of the p-type silicon layer112(Wb) and the width of the oxide semiconductor layer108(Wc) are equal.FIG. 26Ais a top view,FIG. 26Bis a cross-sectional view taken along line A1-B1ofFIG. 26A, andFIG. 26Cis a cross-sectional view taken along line A2-B2ofFIG. 26A.

By forming the oxide semiconductor layer106and the p-type silicon layer110in succession in this manner, damage to the surface of the oxide semiconductor layer106due to an etchant, plasma, or the like can be reduced.

This embodiment can be implemented in combination with any of the structures described in other embodiments, as appropriate.

In this embodiment, a structure and a manufacturing method of a transistor which is different from that of Embodiment 1 will be described with reference to drawings.

First, the manufacturing method of the transistor will be described with reference toFIGS. 5A to 5E. Note that the manufacturing process (such as applicable materials) described in this embodiment is in common with that of Embodiment 1 in many points. Thus, description of the common points is omitted below and only points different from those of Embodiment 1 will be described in detail.

First, the gate electrode102is formed over the substrate100, and then the gate insulating layer104is formed over the gate electrode102. Then, the oxide semiconductor layer106and the p-type silicon layer110are sequentially formed to be stacked over the gate insulating layer104, and a resist mask171is selectively formed (seeFIG. 5A). It is preferable that layers of from the gate insulating layer104to the p-type silicon layer110, or from the oxide semiconductor layer106to the p-type silicon layer110be formed in succession.

Next, the p-type silicon layer110is etched using the resist mask171, so that an island-shaped p-type silicon layer111is formed (seeFIG. 5B). Here, wet etching with the use of an alkaline etchant is performed. When an alkaline etchant is used, etching selectivity of the p-type silicon layer110with respect to the oxide semiconductor layer106is high and the p-type silicon layer110can be selectively etched. As the alkaline etchant, tetramethylammonium hydroxide (TMAH) can be used, for example.

Then, the oxide semiconductor layer106is etched using the resist mask171, so that the island-shaped oxide semiconductor layer108is formed (seeFIG. 5C). Here, wet etching with the use of an acid-based etchant is performed. When an acid etchant is used, etching selectivity of the oxide semiconductor layer106with respect to the p-type silicon layer111is high and the oxide semiconductor layer106can be selectively etched. As the acid-based etchant, a mixed liquid of phosphoric acid, acetic acid, nitric acid, and water (also referred to as an aluminum mixed acid) can be used, for example.

Next, the p-type silicon layer111is etched using the resist mask171, so that the island-shaped p-type silicon layer112is formed (seeFIG. 5D). Here, wet etching with the use of an alkaline etchant is performed again. When an alkaline etchant is used, etching selectivity of the p-type silicon layer111with respect to the oxide semiconductor layer108is high and the p-type silicon layer111can be selectively etched. Here, etching proceeds isotropically and side surfaces of the p-type silicon layer111are etched (side-etched). As the alkaline etchant, tetramethylammonium hydroxide (TMAH) can be used, for example.

By etching the p-type silicon layer in succession to etching of the oxide semiconductor layer in the above-described manner, the oxide semiconductor layer and the p-type silicon layer can be etched without addition of a mask, which simplifies the process.

Next, after forming a conductive film over the gate insulating layer104, the oxide semiconductor layer108, and the p-type silicon layer112, the conductive film is etched to form the source electrode layer116aand the drain electrode layer116b(seeFIG. 5E).

Through the above-described process, a transistor130as illustrated inFIGS. 6A to 6Ccan be manufactured.FIG. 6Ais a top view,FIG. 6Bis a cross-sectional view taken along line A1-B1ofFIG. 6A, andFIG. 6Cis a cross-sectional view taken along line A2-B2ofFIG. 6A.

In the case of using the manufacturing method illustrated inFIGS. 5A to 5E, the width of the p-type silicon layer112(Wb) is smaller than the width of the oxide semiconductor layer108(Wc) and the length of the p-type silicon layer112(Lb) is smaller than the length of the oxide semiconductor layer108(Lc), as illustrated inFIGS. 6A to 6C.

By forming the oxide semiconductor layer106and the p-type silicon layer110in succession in the manufacturing process ofFIGS. 5A to 5E, damage to the surface of the oxide semiconductor layer106due to an etchant, plasma, or the like can be reduced. By providing, over the oxide semiconductor layer, the p-type silicon layer whose etching selectivity with respect to the oxide semiconductor layer is favorable, the process can be simplified without addition of a mask even in the case of etching the oxide semiconductor layer and the p-type silicon layer.

After the transistor130is formed, a protective insulating layer may be formed so as to cover the transistor130. In the process ofFIGS. 5A to 5E, after forming the oxide semiconductor layer108, heat treatment may be performed in a nitrogen atmosphere or an air atmosphere.

The manufacturing method of the transistor130illustrated inFIGS. 6A to 6Cis not limited to the method illustrated inFIGS. 5A to 5E. For example, the p-type silicon layer112may be formed in the following manner: after the process up toFIG. 5Cis performed, ashing with the use of oxygen plasma is performed on the resist mask171to isotropically shrink the resist mask171and expose part of the p-type silicon layer111, and then the exposed part of the p-type silicon layer111is etched.

This embodiment can be implemented in combination with any of the structures described in other embodiments, as appropriate.

In this embodiment, a transistor which is different from the transistors in Embodiments 1 and 2 and a manufacturing method thereof will be described with reference to drawings. Note that the manufacturing process (such as applicable materials) described in this embodiment is in common with that of Embodiment 1 in many points. Thus, description of the common points is omitted below and only points different from those of Embodiment 1 will be described in detail.

A transistor140illustrated inFIGS. 7A and 7Bincludes the gate electrode102provided over the substrate100, the gate insulating layer104provided over the gate electrode102, the oxide semiconductor layer108provided over the gate insulating layer104, the p-type silicon layer112provided over and in contact with the surface of the oxide semiconductor layer108, and the source electrode layer116aand the drain electrode layer116bprovided over and in contact with the surface of the oxide semiconductor layer108. In addition, the low-resistance regions109aand109bare provided in regions of the oxide semiconductor layer108, which are in contact with the source electrode layer116aand the drain electrode layer116b.

That is, the transistor140described in this embodiment has a structure where the low-resistance regions109aand109bare added to regions of the oxide semiconductor layer108on which the p-type silicon layer112is not provided in the above-described embodiments. Note thatFIG. 7Ais a top view andFIG. 7Bis a cross-sectional view taken along line A1-B1ofFIG. 7A.

The low-resistance regions109aand109bcan be provided by generating oxygen vacancy (by forming regions which are in an oxygen vacancy state as compared to a region which is in contact with the p-type silicon layer112) in the oxide semiconductor layer108. Oxygen vacancy may be provided by selectively performing plasma treatment on the regions of the oxide semiconductor layer108on which the p-type silicon layer112is not provided, using a reducing gas such as hydrogen or argon.

Besides, hydrogen may be selectively added to the oxide semiconductor layer108to provide the low-resistance regions109aand109b.

The low-resistance regions109aand109bfunction as a source region and a drain region in the transistor140. The source electrode layer116ais provided in contact with the low-resistance region109aand the drain electrode layer116bis provided in contact with the low-resistance region109b, whereby contact resistance between the oxide semiconductor layer108and the source and drain electrode layers116aand116bcan be reduced.

Next, an example of a method for manufacturing the transistor illustrated inFIGS. 7A and 7Bis described with reference toFIGS. 8A to 8D.

First, the process shown inFIGS. 2A to 2Dis performed and a resist mask172which is used in etching to form the p-type silicon layer112is left (seeFIG. 8A).

Next, the oxide semiconductor layer108is subjected to plasma treatment using a reducing gas such as hydrogen or argon with the use of the resist mask172, so that the low-resistance regions109aand109bare formed in the oxide semiconductor layer108(seeFIG. 8B).

Then, the conductive film114is formed over the gate insulating layer104, the oxide semiconductor layer108, and the p-type silicon layer112(seeFIG. 8C). Note that the conductive film114is formed so as to be in contact with the low-resistance regions109aand109bin the oxide semiconductor layer108.

The conductive film114is etched to form the source electrode layer116aand the drain electrode layer116b(seeFIG. 8D).

Through the above process, the transistor140can be manufactured.

Note that a protective insulating layer may be formed so as to cover the transistor140after the transistor140is formed. In addition, in the process ofFIGS. 8A to 8D, after the oxide semiconductor layer108is formed, heat treatment may be performed under a nitrogen atmosphere or an air atmosphere.

Note that inFIGS. 7A and 7BandFIGS. 8A to 8D, the case where the contact resistance between the oxide semiconductor layer108and the source and drain electrode layers116aand116bis reduced by providing the low-resistance regions109aand109bin the oxide semiconductor layer108is described; however, the present invention is not limited thereto.

As in a transistor141illustrated inFIGS. 9A and 9B, a first metal oxide layer115aand a second metal oxide layer115bmay be provided between the oxide semiconductor layer108and the source electrode layer116aand between the oxide semiconductor layer108and the drain electrode layer116b, respectively. Note thatFIG. 9Ais a top view andFIG. 9Bis a cross-sectional view taken along line A1-B1ofFIG. 9A.

The first metal oxide layer115aand the second metal oxide layer115bmay be provided using metal oxide whose resistance is at least lower than that of the oxide semiconductor layer108.

The first metal oxide layer115aand the second metal oxide layer115bcan be provided using the same material as that of the oxide semiconductor layer108and under different deposition conditions. For example, in the case where an In—Ga—Zn—O based non-single-crystal film is used as the oxide semiconductor layer108, the first metal oxide layer115a, and the second metal oxide layer115b, the In—Ga—Zn—O based non-single-crystal film of the oxide semiconductor layer108is formed under deposition conditions where the ratio of an oxygen gas flow rate to an argon gas flow rate is higher than the ratio of an oxygen gas flow rate to an argon gas flow rate under the deposition conditions for the In—Ga—Zn—O based non-single-crystal films of the first metal oxide layer115aand the second metal oxide layer115b. Specifically, the In—Ga—Zn—O based non-single-crystal film of the first metal oxide layer115aand the second metal oxide layer115bcan be formed in a rare gas (such as argon or helium) atmosphere (or an atmosphere including an oxygen gas at 10% or less and an argon gas at 90% or more), and the In—Ga—Zn—O based non-single-crystal film of the oxide semiconductor layer108can be formed in a mixed oxygen atmosphere (an oxygen gas flow rate is more than to a rare gas flow rate).

The first metal oxide layer115aand the second metal oxide layer115bare provided between the oxide semiconductor layer108and the source electrode layer116aand between the oxide semiconductor layer108and the drain electrode layer116b, respectively, in this manner, whereby a carrier injection barrier from the source electrode layer116aand the drain electrode layer116bcan be reduced. Thus, the contact resistance between the oxide semiconductor layer108and the source and drain electrode layers116aand116bcan be reduced.

Note that after the process inFIGS. 2A to 2Dis performed, a metal oxide layer and the conductive film114are formed in this order over the p-type silicon layer112and the oxide semiconductor layer108, and the metal oxide layer is etched with a mask used at the etching of the conductive film114, so that the first metal oxide layer115aand the second metal oxide layer115bcan be formed. In this case, the conductive film114and the metal oxide layer or the conductive film114, the metal oxide layer, and the oxide semiconductor layer108are etched at the same time in some cases, depending on the etching condition and selected materials.

As in a transistor142illustrated inFIG. 9C, the low-resistance regions109aand109bmay be provided in the oxide semiconductor layer108and the first metal oxide layer115aand the second metal oxide layer115bmay also be provided.

This embodiment can be implemented in combination with any of the structures of the other embodiments as appropriate.

In this embodiment, a transistor which is different from the transistors in Embodiments 1 to 3 and a manufacturing method thereof will be described with reference to drawings. Note that the manufacturing process (such as applicable materials) described in this embodiment is in common with that of Embodiment 1 in many points. Thus, description of the common points is omitted below and only paints different from those of Embodiment 1 will be described in detail.

A transistor150illustrated inFIGS. 10A and 10Bincludes the gate electrode102provided over the substrate100, the gate insulating layer104provided over the gate electrode102, the source electrode layer116aand the drain electrode layer116bprovided over the gate insulating layer104, the oxide semiconductor layer108provided over the source electrode layer116aand the drain electrode layer116band provided over the gate insulating layer104which is located in a region above the gate electrode102and between the source electrode layer116aand the drain electrode layer116b, and the p-type silicon layer112provided so as to cover the oxide semiconductor layer108.

That is, the transistor150and a transistor151described in this embodiment have a structure where the position of the source electrode layer116aand the drain electrode layer116band the position of the oxide semiconductor layer108(the order of stacking) are interchanged in the structures of the above embodiments. The structures illustrated inFIGS. 10A to 10Care also called a bottom-gate bottom-contact type. Note thatFIG. 10Ais a top view andFIG. 10Bis a cross-sectional view taken along line A1-B1ofFIG. 10A.

By providing the p-type silicon layer112in contact with the back channel side (the surface on the opposite side from the gate electrode102) of the oxide semiconductor layer108as illustrated inFIGS. 10A and 10B, entry of hydrogen into the oxide semiconductor layer108can be suppressed. As a result, variation in semiconductor characteristics of the oxide semiconductor layer108due to the entry of hydrogen can be suppressed, which can suppress variation in characteristics of the transistor in which the oxide semiconductor layer108is used as a channel layer.

As in the transistor151illustrated inFIG. 10C, the metal oxide layers115aand115bmay be provided between the source and drain electrode layers116aand116band the oxide semiconductor layer108. The contact resistance between the oxide semiconductor layer108and the source and drain electrode layers116aand116bcan be reduced by providing the metal oxide layers115aand115b.

Next, an example of a method for manufacturing the transistor illustrated inFIGS. 10A and 10Bis described with reference toFIGS. 11A to 11E.

First, the gate electrode102is formed over the substrate100and the gate insulating layer104is formed over the gate electrode102. After that, the source, electrode layer116aand the drain electrode layer116bare formed over the gate insulating layer104(seeFIG. 11A).

Next, the oxide semiconductor layer106is formed so as to cover the source electrode layer116aand the drain electrode layer116b(seeFIG. 11B).

Then, the oxide semiconductor layer106is etched to form the island-shaped oxide semiconductor layer108(seeFIG. 11C). At this time, the oxide semiconductor layer106is etched so as to leave the island-shaped oxide semiconductor layer108at least above the gate electrode102.

Next, the p-type silicon layer110is formed so as to cover the oxide semiconductor layer108(seeFIG. 11D).

Through the above process, the transistor150can be manufactured.

Note that after the transistor150is formed, a protective insulating layer may be formed so as to cover the transistor150. In addition, in the process ofFIGS. 11A to 11E, heat treatment may be performed under a nitrogen atmosphere or an air atmosphere after the oxide semiconductor layer108is formed.

In the case where the transistor illustrated inFIG. 10Cis manufactured, inFIG. 11A, a conductive film forming the source electrode layer116aand the drain electrode layer116band a metal oxide layer forming the metal oxide layers115aand115bmay be stacked in this order over the gate insulating layer104, and then may be etched. In addition, the structure illustrated inFIG. 10Cshows the case where the metal oxide layers115aand115bare etched at the same time when the oxide semiconductor layer106is etched to form the island-shaped oxide semiconductor layer108.

Note that inFIGS. 11A to 11E, the case where the island-shaped p-type silicon layer112is formed so as to completely cover the oxide semiconductor layer108is described; however, the present invention is not limited thereto. The p-type silicon layer112may be provided at least so as to be in contact with a region where a channel is formed in the oxide semiconductor layer108. For example, as in a transistor152illustrated inFIGS. 12A and 12B, the p-type silicon layer112can be provided in contact with part of the oxide semiconductor layer108. InFIGS. 12A and 12B, the case is shown where the p-type silicon layer112is formed so as to be in contact with the part of the oxide semiconductor layer108(formed so as not to be in contact with the source electrode layer116aand the drain electrode layer116b) and a protective insulating layer119is provided over the p-type silicon layer112, the oxide semiconductor layer108, and the source electrode layer116aand the drain electrode layer116b.

As the protective insulating layer119, for example, a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed by a CVD method, a sputtering method, or the like.

Note thatFIG. 12Ais a top view andFIG. 12Bis a cross-sectional view taken along line A1-B1ofFIG. 12A.

This embodiment can be implemented in combination with any of the structures of the other embodiments as appropriate.

In this embodiment, a manufacturing process of a display device which is an example of a usage pattern of a semiconductor device including the transistor described in any of Embodiments 1 to 4 will be described with reference to drawings. Note that the manufacturing process (such as applicable materials) described in this embodiment is in common with that of Embodiment 1 in many points. Thus, description of the common points is omitted below and only points different from those of Embodiment 1 will be described in detail. Note that in the following description, each ofFIG. 15,FIG. 16,FIG. 17,FIG. 18, andFIG. 19is a top view, and each ofFIGS. 13A to 13DandFIGS. 14A to 14Cis a cross-sectional view taken along line A3-B3and line A4-B4ofFIG. 15,FIG. 16,FIG. 17,FIG. 18, andFIG. 19.

First, a wiring and an electrode (a gate wiring including the gate electrode102, a capacitor wiring308, and a first terminal321) are formed over the substrate100having an insulating surface, and then the gate insulating layer104and the oxide semiconductor layer106are formed in succession (seeFIG. 13AandFIG. 15).

The capacitor wiring308and the first terminal321can be formed using the same material as that of the gate electrode layer102, simultaneously.

After the oxide semiconductor layer106is etched to form the island-shaped oxide semiconductor layer108(seeFIG. 16), the p-type silicon layer110is formed so as to cover the oxide semiconductor layer108(seeFIG. 13B). At this time, the oxide semiconductor layer106is etched so as to leave the island-shaped oxide semiconductor layer108at least above the gate electrode102.

Then, the p-type silicon layer110is etched to form the island-shaped p-type silicon layer112(seeFIG. 13CandFIG. 17). At this time, the p-type silicon layer110is etched so as to leave the island-shaped p-type silicon layer112at least in a region overlapping with the gate electrode102. In addition, the p-type silicon layer110is etched so as to expose at least part of the oxide semiconductor layer108.

After a contact hole313is formed in the gate insulating layer104so as to expose the first terminal321, the conductive film114is formed so as to cover the gate insulating layer104, the oxide semiconductor layer108, and the p-type silicon layer112(seeFIG. 13D). Thus, the conductive film114and the first terminal321are electrically connected to each other through the contact hole313.

Next, the conductive film114is etched to form the source electrode layer116a, the drain electrode layer116b, a connection electrode320, and a second terminal322(seeFIG. 14AandFIG. 18). In this case, the p-type silicon layer112functions as a channel protective layer of the oxide semiconductor layer108.

The second terminal322can be electrically connected to a source wiring (a source wiring including the source electrode layer116a). The connection electrode320can be directly connected to the first terminal321.

Through the above process, the thin film transistor160can be manufactured.

Next, heat treatment is preferably performed at 200° C. to 600° C., typically, 300° C. to 500° C. For example, heat treatment is performed under a nitrogen atmosphere at 350° C. for one hour. By this heat treatment, rearrangement of the In—Ga—Zn—O based non-single-crystal film forming the oxide semiconductor layer108is performed at the atomic level. This heat treatment (which may be light annealing) is effective because distortion which hinders the transfer of carriers is reduced by this heat treatment. Note that there is no particular limitation on the timing to perform the heat treatment as long as it is after the formation of the oxide semiconductor layer106, and for example, the heat treatment may be performed after a pixel electrode is formed.

Next, a protective insulating layer340is formed so as to cover the transistor160, and the protective insulating layer340is selectively etched to form a contact hole325which reaches the drain electrode layer116b, a contact hole326which reaches the connection electrode320, and a contact hole327which reaches the second terminal322(seeFIG. 14B).

Next, a transparent conductive layer310which is electrically connected to the drain electrode layer116b, a transparent conductive layer328which is electrically connected to the connection electrode320, and a transparent conductive layer329which is electrically connected to the second terminal322are formed (seeFIG. 14CandFIG. 19).

The transparent conductive layer310functions as a pixel electrode, and the transparent conductive layers328and329serve as electrodes or wirings used for connection with an FPC. More specifically, the transparent conductive layer328formed over the connection electrode320can be used as a terminal electrode for connection which functions as an input terminal of a gate wiring, and the transparent conductive layer329formed over the second terminal322can be used as a terminal electrode for connection which functions as an input terminal of a source wiring.

In addition, a storage capacitor can be formed using the capacitor wiring308, the gate insulating layer104, the protective insulating layer340, and the transparent conductive layer310. In this case, the capacitor wiring308and the transparent conductive layer310each serve as an electrode, and the gate insulating layer104and the protective insulating layer340each serve as a dielectric.

The transparent conductive layers310,328, and329can be formed using indium oxide (In2O3), an alloy of indium oxide and tin oxide (In2O3—SnO2, abbreviated as ITO), an alloy of indium oxide and zinc oxide (In2O3—ZnO), or the like by a sputtering method, a vacuum evaporation method, or the like. For example, a transparent conductive film is formed, and then a resist mask is formed over the transparent conductive film. Then, an unnecessary portion is removed by etching, whereby the transparent conductive layers310,328, and329can be formed.

Through the above process, elements such as a bottom-gate n-channel thin film transistor and the storage capacitor can be completed. By arranging these elements in matrix corresponding to respective pixels, an active matrix display device can be manufactured.

This embodiment can be implemented in combination with any of the structures of the other embodiments as appropriate.

In this embodiment, an example of a liquid crystal display device will be described as a semiconductor device including a thin film transistor. First, the appearance and a cross section of a liquid crystal display panel, which is one mode of the semiconductor device, will be described with reference toFIGS. 20A to 20C.FIGS. 20A and 20Bare each a top view of a panel in which thin film transistors4010and4011which include an oxide semiconductor layer, and a liquid crystal element4013, which are formed over a first substrate4001, are sealed between the first substrate4001and a second substrate4006with a sealant4005.FIG. 20Ccorresponds to a cross-sectional view taken along line M-N ofFIGS. 20A and 20B.

The sealant4005is provided so as to surround a pixel portion4002and a scan line driver circuit4004which are provided over the first substrate4001. The second substrate4006is provided over the pixel portion4002and the scan line driver circuit4004. Thus, the pixel portion4002and the scan line driver circuit4004as well as a liquid crystal layer4008are sealed between the first substrate4001and the second substrate4006with the sealant4005. A signal line driver circuit4003that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate which is prepared separately is mounted in a region that is different from the region surrounded by the sealant4005over the first substrate4001.

Note that there is no particular limitation on the connection method of a driver circuit which is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used.FIG. 20Aillustrates an example in which the signal line driver circuit4003is mounted by a COG method, andFIG. 20Billustrates an example in which the signal line driver circuit4003is mounted by a TAB method.

Each of the pixel portion4002and the scan line driver circuit4004which are provided over the first substrate4001includes a plurality of thin film transistors.FIG. 20Cillustrates the thin film transistor4010included in the pixel portion4002and the thin film transistor4011included in the scan line driver circuit4004. Insulating layers4020and4021are provided over the thin film transistors4010and4011.

Any of the structures described in the above embodiments can be applied to the thin film transistors4010and4011. In this embodiment, the thin film transistors4010and4011are n-channel thin film transistors.

A pixel electrode layer4030included in the liquid crystal element4013is electrically connected to the thin film transistor4010. A counter electrode layer4031of the liquid crystal element4013is formed on the second substrate4006. A portion where the pixel electrode layer4030, the counter electrode layer4031, and the liquid crystal layer4008overlap corresponds to the liquid crystal element4013. Note that the pixel electrode layer4030and the counter electrode layer4031are provided with insulating layers4032and4033which function as alignment films, respectively, and the liquid crystal layer4008is sandwiched between the pixel electrode layer4030and the counter electrode layer4031with the insulating layers4032and4033interposed therebetween.

Note that the first substrate4001and the second substrate4006can be formed using glass, metal (typically, stainless steel), ceramic, or plastic. As for plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

A columnar spacer denoted by reference numeral4035is obtained by selective etching of an insulating film and is provided to control a distance (a cell gap) between the pixel electrode layer4030and the counter electrode layer4031. Note that a spherical spacer may also be used. In addition, the counter electrode layer4031is electrically connected to a common potential line provided on the same substrate as the thin film transistor4010. With the use of a common connection portion, the counter electrode layer4031and the common potential line can be electrically connected to each other through conductive particles arranged between a pair of substrates. Note that the conductive particles are included in the sealant4005.

In addition, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of liquid crystal phases and a phase which appears just before the transition from a cholesteric phase to an isotropic phase when the temperature of cholesteric liquid crystal is increased. Because the blue phase appears only in a small temperature range, a liquid crystal composition in which greater than or equal to 5 weight % of a chiral agent is mixed is used for the liquid crystal layer4008in order to improve the temperature range. The liquid crystal composition including liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 10 μs to 100 μs and are optically isotropic; therefore, alignment treatment is unnecessary, and viewing angle dependence is small.

Note that the liquid crystal display device described in this embodiment is an example of a transmissive liquid crystal display device; however, the liquid crystal display device can be applied to either a reflective liquid crystal display device or a semi-transmissive liquid crystal display device.

The liquid crystal display device described in this embodiment is an example in which a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are provided on the inner surface of the substrate in this order; however, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is also not limited to this embodiment and may be appropriately set depending on materials of the polarizing plate and the coloring layer or conditions of the manufacturing process. In addition, a light-blocking film which functions as a black matrix may be provided.

In this embodiment, in order to reduce surface unevenness of the thin film transistors and to improve reliability of the thin film transistors, the thin film transistors are covered with the insulating layers (the insulating layer4020and the insulating layer4021) functioning as a protective film or a planarizing insulating film. Note that the protective film is provided to prevent entry of a contaminant impurity such as an organic substance, a metal substance, or moisture floating in air and is preferably a dense film. As the protective film, a single layer or a stacked layer of any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed by a sputtering method. In this embodiment, an example in which the protective film is formed by a sputtering method is described; however, there is no particular limitation on the method, and a variety of methods may be used.

Here, the insulating layer4020having a stacked structure is formed as the protective film. Here, a silicon oxide film is formed by a sputtering method, as a first layer of the insulating layer4020. When the silicon oxide film is used as the protective film, the silicon oxide film has an effect of preventing a hillock of an aluminum film used as a source electrode layer and a drain electrode layer.

An insulating layer is formed as a second layer of the protective film. Here, a silicon nitride film is formed by a sputtering method, as a second layer of the insulating layer4020. The use of the silicon nitride film as the protective film can prevent mobile ions of sodium or the like from entering a semiconductor region so that variation in electrical characteristics of a TFT can be suppressed.

After the protective film is formed, annealing (200° C. to 400° C.) of the semiconductor layer may be performed.

The insulating layer4021is formed as the planarizing insulating film. An organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used for the insulating layer4021. In addition to such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. Note that the insulating layer4021may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a resin formed using a siloxane-based Material as a starting material and having the bond of Si—O—Si. As for the siloxane-based resin, an organic group (e.g., an alkyl group or an aryl group) or a fluoro group may be used as a substituent. The organic group may include a fluoro group.

There is no particular limitation on the method for forming the insulating layer4021, and the following method can be used depending on the material of the insulating layer4021: a sputtering method, an SOG method, a spin coating method, a dip coating method, a spray coating method, a droplet discharge method (e.g., an inkjet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. When the insulating layer4021is formed using material liquid, annealing (200° C. to 400° C.) of the semiconductor layer may be performed in a baking step at the same time. A baking step of the insulating layer4021also serves as the annealing of the semiconductor layer, whereby a semiconductor device can be manufactured efficiently.

A conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the pixel electrode layer4030and the counter electrode layer4031. The pixel electrode formed using a conductive composition preferably has a light transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive polymer included in the conductive composition is preferably less than or equal to 0.1Ω·cm.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. As examples thereof, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of more than two kinds of them, and the like can be given.

Further, a variety of signals and potentials are supplied to the signal line driver circuit4003which is formed separately, the scan line driver circuit4004or the pixel portion4002from an FPC4018.

In this embodiment, a connection terminal electrode4015is formed using the same conductive film as the pixel electrode layer4030included in the liquid crystal element4013. A terminal electrode4016is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors4010and4011.

The connection terminal electrode4015is electrically connected to a terminal included in the FPC4018through an anisotropic conductive film4019.

FIGS. 20A to 20Cillustrate an example in which the signal line driver circuit4003is formed separately and mounted on the first substrate4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

This embodiment can be implemented in combination with any of the structures of the other embodiments as appropriate.

In this embodiment, electronic paper is described as an example of a semiconductor device including a transistor.

FIG. 21illustrates active matrix electronic paper as an example of the semiconductor device. A thin film transistor581used for the semiconductor device can be formed in a manner similar to the thin film transistor described in any of Embodiments 1 to 5.

The electronic paper inFIG. 21is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The thin film transistor581provided over a substrate580is a thin film transistor having a bottom gate structure. A source electrode layer or a drain electrode layer is electrically connected to a first electrode layer587through a contact hole formed in insulating layers583,584, and585. Between the first electrode layer587and a second electrode layer588, spherical particles589each including a black region590aand a white region590b, and a cavity594filled with liquid around the black region590aand the white region590bare provided. The circumference of each of the spherical particles589is provided with a filler595such as a resin (seeFIG. 21). InFIG. 21, the first electrode layer587corresponds to a pixel electrode, and the second electrode layer588corresponds to a common electrode. The second electrode layer588is electrically connected to a common potential line provided on the same substrate as the thin film transistor581. A common connection portion described in the above embodiment is used, whereby the second electrode layer588provided on a substrate596and the common potential line can be electrically connected to each other through the conductive particles arranged between a pair of substrates.

Further, instead of the twist ball, an electrophoretic element can also be used. In that case, a microcapsule having a diameter of approximately 10 μm to 200 μm, in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and black microparticles move to opposite sides from each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element, and is called electronic paper in general. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an assistant light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device including a display device) is distanced from an electric wave source.

In this manner, highly reliable electronic paper can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with any of the structures of the other embodiments as appropriate.

In this embodiment, an example of a light-emitting display device will be described as a semiconductor device including a transistor. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In the organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, the carriers (electrons and holes) are recombined, so that the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. The dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions.

Next, the appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of the semiconductor device, will be described with reference toFIGS. 22A and 22B.FIG. 22Ais a top view of the panel in which thin film transistors4509and4510and a light-emitting element4511are sealed between a first substrate4501and a second substrate4506with a sealant4505.FIG. 22Bis a cross-sectional view taken along line H-I ofFIG. 22A. Note that description is made here using an organic EL element as a light-emitting element.

The sealant4505is provided to surround a pixel portion4502, signal line driver circuits4503aand4503b, and scanning line driver circuits4504aand4504b, which are provided over the first substrate4501. In addition, the second substrate4506is provided over the pixel portion4502, the signal line driver circuits4503aand4503b, and the scanning line driver circuits4504aand4504b. Accordingly, the pixel portion4502, the signal line driver circuits4503aand4503b, and the scanning line driver circuits4504aand4504bare sealed together with a filler4507, by the first substrate4501, the sealant4505, and the second substrate4506. It is preferable that the pixel portion4502, the signal line driver circuits4503aand4503b, and the scanning line driver circuits4504aand4504bbe thus packaged (sealed) with a protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so as not to be exposed to the outside air.

The pixel portion4502, the signal line driver circuits4503aand4503b, and the scanning line driver circuits4504aand4504bformed over the first substrate4501each include a plurality of thin film transistors, and the thin film transistor4510included in the pixel portion4502and the thin film transistor4509included in the signal line driver circuit4503aare illustrated as an example inFIG. 22B.

Any of the structures described in the above embodiments can be applied to the thin film transistors4509and4510. In this embodiment, the thin film transistors4509and4510are n-channel thin film transistors.

Moreover, reference numeral4511denotes a light-emitting element. A first electrode layer4517that is a pixel electrode included in the light-emitting element4511is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor4510. Note that although the light-emitting element4511has a stacked structure of the first electrode layer4517, an electroluminescent layer4512, and a second electrode layer4513, the structure of the light-emitting element4511is not limited to the structure described in this embodiment. The structure of the light-emitting element4511can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element4511, or the like.

A partition wall4520is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall4520be formed of a photosensitive material to have an opening over the first electrode layer4517so that a sidewall of the opening is formed as an inclined surface With continuous curvature.

The electroluminescent layer4512may be formed using a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer4513and the partition wall4520in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

A variety of signals and potentials are supplied to the signal line driver circuits4503aand4503b, the scanning line driver circuits4504aand4504b, or the pixel portion4502from FPCs4518aand4518b.

In this embodiment, a connection terminal electrode4515is formed using the same conductive film as the first electrode layer4517included in the light-emitting element4511, and a terminal electrode4516is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors4509and4510.

The connection terminal electrode4515is electrically connected to a terminal of the FPC4518athrough an anisotropic conductive film4519.

The second substrate4506located in the direction in which light is extracted from the light-emitting element4511needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used.

The signal line driver circuits4503aand4503band the scanning line driver circuits4504aand4504bmay be mounted as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared. Alternatively, only the signal line driver circuits or part thereof, or only the scanning line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated inFIGS. 22A and 22B.

Through the above-described process, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

This embodiment can be implemented in combination with any of the structures described in other embodiments, as appropriate.

A semiconductor device including any of the transistors described in the above embodiments can be applied to a variety of electronic appliances (including an amusement machine). Examples of electronic appliances are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a cellular phone (also referred to as a mobile phone or a mobile phone set), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.

FIG. 23Aillustrates an example of a television set9600. In the television set9600, a display portion9603is incorporated in a housing9601. Images can be displayed on the display portion9603. Here, the housing9601is supported by a stand9605.

The television set9600can be operated by an operation switch of the housing9601or a separate remote controller9610. Channels and volume can be controlled by an operation key9609of the remote controller9610so that an image displayed on the display portion9603can be controlled. Furthermore, the remote controller9610may be provided with a display portion9607for displaying data output from the remote controller9610.

Note that the television set9600is provided with a receiver, a modem, and the like. With the receiver, a general television broadcast can be received. Furthermore, when the television set9600is connected to a communication network by wired or wireless connection via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver, between receivers, or the like) data communication can be performed.

FIG. 23Billustrates an example of a digital photo frame9700. For example, in the digital photo frame9700, a display portion9703is incorporated in a housing9701. Various images can be displayed on the display portion9703. For example, the display portion9703can display data of an image shot by a digital camera or the like to function as a normal photo frame.

Note that the digital photo frame9700is provided with an operation portion, an external connection terminal (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although they may be provided on the same surface as the display portion, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame9700. For example, a memory which stores data of an image shot by a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be downloaded and displayed on the display portion9703.

The digital photo frame9700may have a configuration capable of wirelessly transmitting and receiving data. Through wireless communication, desired image data can be downloaded to be displayed.

FIG. 24Ais a portable amusement machine including two housings, a housing9881and a housing9891. The housings9881and9891are connected with a connection portion9893so as to be opened and closed. A display portion9882and a display portion9883are incorporated in the housing9881and the housing9891, respectively. In addition, the portable amusement machine illustrated inFIG. 24Aincludes a speaker portion9884, a recording medium insertion portion9886, an LED lamp9890, an input means (an operation key9885, a connection terminal9887, a sensor9888(a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared rays), or a microphone9889), and the like. It is needless to say that the structure of the portable amusement machine is not limited to the above and other structures provided with at least a semiconductor device may be employed. The portable amusement machine may include another accessory equipment as appropriate. The portable amusement machine illustrated inFIG. 24Ahas a function of reading a program or data stored in a recording medium to display it on the display portion, and a function of sharing information with another portable amusement machine by wireless communication. The portable amusement machine illustrated inFIG. 24Acan have various functions without limitation to the above.

FIG. 24Billustrates an example of a slot machine9900which is a large-sized amusement machine. In the slot machine9900, a display portion9903is incorporated in a housing9901. In addition, the slot machine9900includes an operation means such as a start lever or a stop switch, a coin slot, a speaker, and the like. It is needless to say that the structure of the slot machine9900is not limited to the above and other structures provided with at least a semiconductor device may be employed. The slot machine9900may include another accessory equipment as appropriate.

This embodiment can be implemented in combination with any of the structures described in other embodiments, as appropriate.

This application is based on Japanese Patent Application serial no. 2009-030971 filed with Japan Patent Office on Feb. 13, 2009, the entire contents of which are hereby incorporated by reference.