Test apparatus for semiconductor device

A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.

BACKGROUND OF THE INVENTION

The present invention relates to a test apparatus for a semiconductor device, and, more particularly, to a test apparatus equipped with a test circuit connected between a semiconductor device and an external test unit.

In case where a test for circuit functions or electric characteristics or the like is performed on a plurality of chips of semiconductor memory devices on a wafer, conventionally, a probe is made to contact a pad of each chip and is connected to a test apparatus via a connection cable. The test apparatus provides a predetermined test program to each chip and conducts individual function tests in accordance with the test program.

The probe test suffers a poor precision of signal waveforms to be supplied to the test apparatus and cannot sufficiently secure the reliability in an operational test on a semiconductor memory device which operates at a high speed.

As the operational speeds and the capacities of recent semiconductor memory devices are increased, there arises a problem such that the performance of an external test unit cannot follow up the characteristics of the semiconductor memory devices.

To supplement the performance of the external test unit, therefore, a test chip called Built Out Self Test (BOST) or a test circuit which is called Built In Self Test (BIST) and preformed in each chip is intervened between a wafer and the external test unit.

Japanese Laid-Open Patent Publication No. 2000-100880 or Japanese Laid-Open Patent Publication No. 9-49864 discloses a test apparatus which has a BOST or BIST provided between an external test unit and a circuit to be measured and performs an operational test.

However, all tests, such as a timing dependency test and a pattern dependency test, cannot be controlled by the BOST or BIST. In other words, there are test items that can be executed only in a low-speed operational test which is conducted by an external test unit. This makes it difficult to speed up an operational test on target devices on a wafer.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST and BIST.

In one aspect of the present invention, a test apparatus for testing a semiconductor device is provided. The test apparatus includes an external test unit, a test circuit formed in the semiconductor device, and a test device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the test circuit and pattern data for a timing dependency test is stored in the test device.

In another aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a BIST circuit in which plural pieces of test pattern data for performing a pattern dependency test are stored.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a schematic block diagram of a test apparatus100according to one embodiment of the present invention. The test apparatus100includes an external test unit1, a BOST device (hereinafter called “BOST”)3and a BIST circuit (hereinafter called “BIST”)4. The BOST3is connected between a memory chip2or a to-be-tested chip on a wafer and the external test unit1. The BOST3is a semiconductor chip for a test.

The BIST4is a test circuit formed in the memory chip2. Stored in the BIST4are test patterns, such as march, refresh, disturb and long cycle, for a pattern dependency test.

The BOST3receives BOST-IN signals including supply voltages VDDand GND from the external test unit1. The BOST3includes a pattern generating circuit5and a decision circuit6.

The BOST3supplies the BIST4in the memory chip2with BOST-OUT signals including the supply voltages VDDand GND. The BOST-OUT signals are test mode signals for activating the BIST4. The BIST4performs a pattern dependency test using prestored test patterns in accordance with the BOST-OUT signals and generates signals indicating test results.

The BIST4supplies the BOST3with signals DATA0to DATAn indicating test results. The decision circuit6of the BOST3determines whether the test results are correct according to the signals DATA0to DATAn and supplies the external test unit1with signals indicating test results.

The pattern generating circuit5will now be described referring toFIG. 2. The pattern generating circuit5includes a pattern memory7, a timing generator8, a wave formatter9, a counter10and a clock buffer11. The pattern memory7is supplied with a BOST clock signal or a control signal from the external test unit1. The pattern memory7supplies the timing generator8with prestored test pattern data PT for pattern data for a timing dependency test in accordance with the BOST clock signal. The test pattern data PT includes front pattern data.

The timing generator8generates a reference clock signal CLK and supplies the reference clock signal CLK to the wave formatter9and the counter10. The timing generator8also provides the test pattern data PT to the wave formatter9.

The wave formatter9receives an expected-value control signal or a signal DATA from the external test unit1and selects either front pattern data or back pattern data and supplies the selected pattern data to the clock buffer11. When the front pattern data is selected, the wave formatter9supplies the front pattern data directly to the clock buffer11. When the back pattern data is selected, the wave formatter9inverts the front pattern data to generate the back pattern data.

The counter10counts the pulses of the reference clock signal CLK and provides a count-up signal to the clock buffer11when the count value reaches a predetermined pulse number.

The clock buffer11receives test pattern data from the wave formatter9and supplies that test pattern data to the memory chip2every time it receives the count-up signal.

The memory chip2performs a timing dependency test based on the test pattern data supplied from the clock buffer11and the BOST-OUT signals supplied from the BOST3.

The decision circuit6will now be explained with reference toFIG. 3. The decision circuit6includes a driver12, a comparator13, a P/F decision circuit14and a result holding RAM15. The driver12receives test pattern data PT, generated by the pattern generating circuit5, as write data WD and supplies the write data WD to the memory chip2. The test pattern data PT is a write data pattern to be written in the memory chip2.

After an operation of writing data in the memory chip2is finished, the written data is sequentially read from the memory chip2. The comparator13receives the write data WD and compares the write data WD with read data RD. The comparator13generates a comparison signal of “0” when the write data WD matches with the read data RD and generates a comparison signal of “1” when there is no match.

The P/F decision circuit14receives the comparison signal from the comparator13and the expected-value control signal DATA from the pattern generating circuit5. When the comparison signal is “0”, the P/F decision circuit14supplies the result holding RAM15with a decision signal having the same value (e.g., 0) as the value of the expected-value control signal DATA. When the comparison signal is “1”, the P/F decision circuit14supplies the result holding RAM15with a decision signal having a value (e.g., 1) opposite to the value of the expected-value control signal DATA.

The result holding RAM15stores the decision signal supplied from the P/F decision circuit14. When the pattern generating circuit5provides an output command signal OCM to the result holding RAM15after an operation of reading data from the memory chip2is finished, the result holding RAM15supplies the stored decision signal to the external test unit1.

When receiving the decision signal having the same value as the value of the expected-value control signal DATA from the P/F decision circuit14after the read operation is completed, the external test unit1decides that the memory chip2is normal. When receiving the decision signal whose value is opposite to the value of the expected-value control signal DATA from the P/F decision circuit14, the external test unit1decides that the memory chip2is defective.

As shown inFIG. 1, a supply voltage VDDand a ground potential GND are supplied as input/output determining supply voltages to the decision circuit6from the external test unit1. Specifically, the supply voltage VDDand the ground potential GND are supplied to the driver12and the comparator13of the decision circuit6, as shown inFIG. 4. The driver12receives the test pattern data PT and supplies the memory chip2with a write data signal having a maximum amplitude set by the potential difference between the supply voltage VDDand the ground potential GND.

The comparator13generates a predetermined decision level based on the supply voltage VDDand the ground potential GND and generates a binary comparison signal of “1” or “0” by comparing the read data from the memory chip2with the predetermined decision level. The output level of the driver12and the decision level of the comparator13can be adjusted arbitrarily by changing the voltage levels of the supply voltage VDDand the ground potential GND.

As shown inFIG. 5, different supply voltages are supplied to the BOST3and the memory chip2. In case of conducting an operational test on the memory chip2, a supply voltage which is out the operation-guaranteeing range may be supplied in order to guarantee the supply voltage margin. Because the BOST3includes a circuit which needs to be operated with a high precision, such as a circuit for a timing test, a constant supply voltage of, for example, 3.3 V should be supplied to the BOST3.

For example, the voltage of a voltage supply VDD1is supplied to the memory chip2from the external test unit1and the voltage of a voltage supply VDD2different from the voltage supply VDD1is supplied to the BOST3.

The BOST3includes a BOST circuit16, a memory-chip I/O circuit17connected between the BOST circuit16and the memory chip2, and a test-apparatus I/O circuit18connected between the BOST circuit16and the external test unit1.

The memory chip2is supplied with the voltage of the high-potential voltage supply VDD1of 3.9 V from the external test unit1and the BOST3is supplied with the voltage of the high-potential voltage supply VDD2of 3.3 V from the external test unit1. The voltage of a low-potential voltage supply VSSis supplied to both the memory chip2and the BOST3.

The input/output of signals between the BOST circuit16and the memory chip2is carried out via the memory-chip I/O circuit17. The input/output of signals between the BOST circuit16and the external test unit1is carried out via the test-apparatus I/O circuit18.

The memory-chip I/O circuit17will now be discussed with reference toFIG. 6. The memory-chip I/O circuit17includes I/O buffers19which are equal in quantity to the input/output terminals of the BOST3.

Each I/O buffer19includes a driver20, comparators21aand21band a buffer circuit22. The output-level generation voltages VHand VLare supplied to the driver20. Based on an input signal IN from the BOST circuit16, the driver20supplies the memory chip2with an output signal OUT having a maximum amplitude set by the potential difference between the output-level generation voltages VHand VL.

The input-level reference voltage VRHis provided to the comparator21a. When the voltage of the signal supplied from the memory chip2is higher than the reference voltage VRH, the comparator21asupplies an output signal having an H (high) level to the buffer circuit22.

The input-level reference voltage VRLis provided to the comparator21b. When the voltage of the signal supplied from the memory chip2is lower than the reference voltage VRL, the comparator21bsupplies an output signal having an L (low) level to the buffer circuit22. The reference voltage VRHis higher than the reference voltage VRL.

FIG. 7presents a schematic circuit diagram of the driver20. The input signal IN is supplied to the gate of an N channel MOS (NMOS) transistor Tr1and also to the gate of an NMOS transistor Tr2via an inverter circuit23a.

The voltage of the voltage supply VSSis supplied to the source of the transistor Tr1whose drain is connected to the drain of a P channel MOS (PMOS) transistor Tr3. The voltage of the voltage supply VSSis supplied to the source of the transistor Tr2whose drain is connected to the drain of a PMOS transistor Tr4.

The output-level generation voltage VHis supplied to the sources of the transistors Tr3and Tr4, the gate of the transistor Tr3is connected to the drain of the transistor Tr4whose gate is connected to the drain of the transistor Tr3. The drain of the transistor Tr3is connected to the input terminal of an inverter circuit23bas an output stage.

The inverter circuit23bis supplied with the output-level generation voltage VHas a high-potential supply voltage and with the output-level generation voltage VLas a low-potential supply voltage.

The inverter circuit23boutputs the output signal OUT which is in phase with the input signal of the driver20. The output signal OUT varies between the output-level generation voltages VHand VL.

As shown inFIG. 8, the BOSTs3are connected to the memory chip2formed on a wafer25via a contactor substrate24. Each BOST3is connected to the associated in memory chip2.

As shown inFIG. 9, the BOST3is connected to the memory chip2via a switch circuit26which is connected to an intra-substrate interconnection line of the contactor substrate24. The switch circuit26is opened or closed in response to an enable signal EN output from the BOST3.

The BOST3generates the enable signal EN based on a decision signal read from the result holding RAM15of the decision circuit6. When the memory chip2is determined as defective based on the decision signal, the enable signal EN disables the switch circuit26. When the memory chip2is determined as normal, the enable signal EN enables the switch circuit26. The memory chip2that has been decided as defective in the operational test, it is disconnected from the BOST3and the supply of the BOST-OUT signals to the memory chip2is stopped.

FIGS. 10 through 12illustrate different connections between the BOST3and the memory chip2on the wafer25.

According to the connection method shown inFIG. 10, contactors27aare formed on both the top and bottom surfaces of the BOST chip3. In this case, the BOST chip3is sandwiched between the contactor substrate24and the wafer25, the external test unit1is connected to the memory chip2on the wafer25via the BOST chip3which is connected in close proximity to the memory chip2.

The BOST-IN signals are supplied to the BOST3from the external test unit1via the contactor substrate24, and the BOST-OUT signals generated in the BOST3are supplied to the memory chip2on the wafer25via the contactors27a.

According to the connection method, a package for retaining the BOST chip3may be formed and contactors may be formed on both the top and bottom surfaces of the package. In this case, it is possible to retain different BOST chips3in a general-purpose package and connect the contactor substrate24to the wafer25by the BOST3.

According to the connection method shown inFIG. 11, contactors27band27care formed only on a first surface of the BOST chip3, and a second surface of the BOST chip3is adhered to the contactor substrate24. As the contactors27cof the BOST chip3are made to contact the memory chip2, the external test unit1and the memory chip2on the wafer25are connected via the BOST chip3. At this time, the BOST chip3is connected in close proximity to the memory chip2.

According to the connection method shown inFIG. 12, the contactors27band27care formed on the first surface of the BOST chip3. The BOST chip3is retained in a socket28and the contactors27band27care respectively connected to contactors29aand29bof the socket28.

Contactors29cand29dare formed on the upper end of the outer wall of the socket28. Some contactors29aof the socket28are connected to the contactors29cthrough the inside of the outer wall of the socket28. The other contactors29aare connected to the contactors29dvia contactors24aformed in the contactor substrate24and interconnection lines30laid in the outer wall.

The socket28is fastened into a cap31which is provided with pogo pins32. The pogo pins32are respectively connected to the contactors29cand29d. The pogo pins32are also connected to the external test unit1.

The contactors29bof the socket28are connected to contactors33formed in the contactor substrate24. Each contactor33has a needle-like portion which runs through the contactor substrate24. The distal ends of the contactors33are connected to the memory chip2on the wafer25.

In the connection method, as the contactors27band27cof the BOST chip3are made to contact the contactors29aand29bof the socket28, the external test unit1is connected to the memory chip2on the wafer25via the BOST chip3. At this time, the BOST chip3is connected in close proximity to the memory chip2.

FIG. 13shows a method of measuring the access time of the memory chip2using the BOST3at the time of performing an operational test on the memory chip2. The pattern generating circuit5in the BOST3provides the clock signal CLK to the memory chip2and the decision circuit6. In accordance with the clock signal CLK, the memory chip2operates and provides an output signal DQ (DATA) to the decision circuit6.

Let x be the length of the interconnection line for supplying the clock signal CLK to the memory chip2from the pattern generating circuit5, y be the length of the interconnection line for supplying the output signal DQ to the decision circuit6from the memory chip2and x+y be the length of the interconnection line for supplying the clock signal CLK to the decision circuit6from the pattern generating circuit5. The decision circuit6compares the input timing for the output signal DQ with the input timing for the clock signal CLK to measure the access time from the supply of the clock signal CLK to the memory chip2to the outputting of the output signal DQ. That is, the method can measure the access time without using a correction circuit for correcting delays caused by the interconnection lines x and y.

The structure for determining the access time will now be described. The decision circuit6shown inFIG. 14includes latch circuits34aand34b, a selection circuit35, a frequency counter36, a high frequency generator37and an access time determining circuit38in addition to the driver12, the comparator13, the P/F decision circuit14and the result holding RAM15shown inFIG. 3.

The latch circuit34acompares the voltage of the clock signal CLK supplied from the pattern generating circuit5with a predetermined decision voltage and generates an access clock signal clk of an H level or L level, as shown inFIG. 15. The latch circuit34bcompares the voltage of the output signal DQ supplied from the memory chip2with a predetermined decision voltage and generates an access signal dq of an H level or L level, as shown inFIG. 16.

The selection circuit35receives the access clock signal clk and the access signal dq and generates an output signal which goes to an H level in response to that one of the access clock signal clk and access signal dq which rises earlier and goes to an L level in response to the signal that rises later. That is, the selection circuit35generates an EOR logical signal of the access clock signal clk and the access signal dq.

The frequency counter36counts the number of pulses of a high-frequency pulse signal from the high frequency generator37. The frequency counter36resets the count value and starts counting the number of pulses of the output signal of the high frequency generator37in response to the rising of the output signal of the selection circuit35, and stops counting in response to the falling of the output signal of the selection circuit35.

The access time determining circuit38compares the count value of the frequency counter36with a predetermined reference value and outputs a comparison result. Based on the comparison result, it is determined whether the access time lies within a predetermined range.

Referring now toFIG. 17, a description will be given of the decision circuit6which includes the access time determining circuit in case where the output signals DQ of plural bits are output in parallel from the memory chip2.

The decision circuit6includes the access time determining circuit38, first and second frequency counters39aand39b, an OR circuit40aand an AND circuit41a.

The clock signal CLK is latched in the latch circuit (not shown) and the access clock signal clk is generated. The access clock signal clk is supplied to the first and second frequency counters39aand39b.

A high-frequency pulse signal is supplied to each of the first and second frequency counters39aand39b. The first frequency counter39astarts counting the pulses of the pulse signal at the rising of the output signal of the OR circuit40aand stops counting at the rising of the access clock signal clk. The second frequency counter39bstarts counting the pulses of the pulse signal at the rising of the access clock signal clk and stops counting at the falling of the output signal of the AND circuit41a.

The count values of the first and second frequency counters39aand39bare supplied to the access time determining circuit38which in turn determines the access time based on the count values.

When the rising times of the access signals dq1to dq3differ from one another, as shown inFIG. 18, an output signal out1is output from the OR circuit40aand an output signal out2is output from the AND circuit41a.

A signal eor rises in response to the rising of the output signal out1and falls in response to the falling of the output signal out2. That is, the signal eor indicates the EOR logic of the output signals out1and out2and represents the skew of the access signals dq1to dq3.

The operation of the access time determining circuit38will now be described by referring toFIG. 19. To begin with, a description will be given of the case where the rising of the access signals dq1to dq3leads the rising of the access clock signal clk (the case of a signal eor1).

In this case, a time t1from the rising of the signal eor1to the rising of the access clock signal clk is the access time that should be guaranteed. At the rising of the signal eor1, the first frequency counter39ais reset and starts the counting operation. The first frequency counter39aperforms the counting operation during the time t1from the rising of the signal eor1to the falling of the access clock signal clk. Therefore, the count value of the first frequency counter39aduring the time t1is supplied to the access time determining circuit38. The access time determining circuit38determines the access time based on the count value and generates a decision signal JG.

A description will now be given of the case where the rising of the access signals dq1to dq3lags behind the rising of the access clock signal clk (the case of a signal eor2).

In this case, a time t2from the rising of the access clock signal clk to the falling of the signal eor2is the access time that should be guaranteed. At the rising of the access clock signal clk, the second frequency counter39bis reset and starts the counting operation. The second frequency counter39bperforms the counting operation during the time t2from the rising of the access clock signal clk to the falling of the signal eor2. Therefore, the count value of the second frequency counter39bduring the time t2is supplied to the access time determining circuit38. The access time determining circuit38determines the access time based on the count value and generates the decision signal JG.

A description will now be given of the case where the access signals dq1to dq3rise around the rising of the access clock signal clk (the case of a signal eor3). In this case, a time t3from the rising of the signal eor3to the falling thereof is the access time that should be guaranteed. During the time from the rising of the signal eor3to the rising of the access clock signal clk, the first frequency counter39aperforms the counting operation. During the time from the rising of the access clock signal clk to the falling of the signal eor3, the second frequency counter39bperforms the counting operation. The count values of the first and second frequency counters39aand39bare supplied to the access time determining circuit38. The access time determining circuit38determines the access time based on the two count values and generates the decision signal JG.

There may be a case where a signal for stopping the counting operation is not supplied to one of the first and second frequency counters39aand39bin the decision circuit. In this case, the counting operation may be stopped in the following manner. One frequency counter receives the decision signal JG based on the count value of the other frequency counter from the access time determining circuit38and stops the counting operation.

FIG. 20illustrates a circuit200which determines the skew of the access signals dq1to dq3. The decision circuit200includes an OR circuit40b, an AND circuit41b, a frequency counter42aand the access time determining circuit38.

The OR circuit40breceives the access signals dq1to dq3and supplies an OR logical signal to the frequency counter42a. The AND circuit41breceives the access signals dq1to dq3and supplies an AND logical signal to the frequency counter42a. The frequency counter42aperforms the counting operation in accordance with the OR logical signal from the OR circuit40band the AND logical signal from the AND circuit41band provides a count value to the access time determining circuit38. The access time determining circuit38determines the skew of the access signals dq1to dq3based on the count value.

FIG. 21is a schematic block diagram showing a decision circuit300which determines the access time using a reference clock signal ck and an access signal dq supplied from the external test unit1. An OR circuit40creceives the reference clock signal ck and the access signal dq and generates an OR logical signal. An AND circuit41creceives the reference clock signal ck and the access signal dq and generates an AND logical signal. A frequency counter42bperforms the counting operation in accordance with the OR logical signal and the AND logical signal and provides a count value to the access time determining circuit38. The access time determining circuit38determines the access time based on the count value.

The test apparatus100has the following advantages.(1) The pattern dependency test and timing dependency test for the memory chip2can be conducted using the external test unit1, the BOST3or a test chip and the BIST4in the memory chip2.(2) The pattern dependency test can be performed by operating the BIST4in response to the control signal supplied to the BIST4via the BOST3from the external test unit1.(3) The wave formatter9produces back pattern data from front pattern data of test pattern data PT in accordance with the expected-value control signal supplied from the external test unit1using the test pattern data PT read from the pattern memory7of the pattern generating circuit5of the BOST3. It is therefore unnecessary to store both front pattern data and back pattern data in the pattern memory7with respect to a single piece of test pattern data PT. This can lead to reduction of the memory capacity of the pattern memory7and make the BOST chip3compact.(4) The BOST3generates test pattern data PT for the timing dependency test and supplies the test pattern data PT to the memory chip2on the wafer25. The BOST3is located in close proximity to the wafer25. As the test pattern data PT is supplied from a location near the wafer25, therefore, the precision of the waveform of the test pattern data PT is improved. This results in a faster operational test and an improvement of the reliability of the operational test.(5) As shown inFIG. 3, the decision circuit6of the BOST3determines if data read from the memory chip2is normal. When the data is normal, the decision circuit6directly supplies the expected-value control signal DATA, supplied from the external test unit1, to the external test unit1as the decision result. If the data is not normal, the decision circuit6inverts the expected-value control signal DATA and supplies the inverted expected-value control signal DATA to the external test unit1as the decision result. Therefore, the external test unit1can easily perform a defect check based on the result of the operational test.(6) As shown inFIG. 6, the external test unit1supplies the output-level generation voltages VHand VLto the driver20of the I/O circuit17in the BOST3. This stabilizes the level of the output signal of the BOST3that is to be supplied to the memory chip2, thus improving the reliability of the operational test.(7) As shown inFIG. 6, the external test unit1supplies the input-level reference voltages VRHand VRLto the comparators21aand21bof the I/O circuit17in the BOST3. This stabilizes the operation of determining the level of the output signal of the memory chip2, thus improving the reliability of the operational test.(8) As shown inFIG. 9, the memory chip2that has been determined as defective is disconnected from the BOST3. Therefore, a defective memory chip can be disabled reliably, thus preventing other normal memory chips from malfunctioning due to the operation of the defective memory chip.(9) According to the connection methods illustrated inFIGS. 10 to 12, the BOST chip3is placed at a position in close proximity to the memory chip2on the wafer25. This results in a faster operational test and an improvement of the reliability of the operational test.(10) As the BOST chip3is retained in the socket28, it is easy to replace a damaged BOST chip3with a proper one.(11) The access-time measuring method shown inFIG. 13can measure the access time free of the delay caused by the length of the interconnection line between the pattern generating circuit5and the memory chip2and the length of the interconnection line between the memory chip2and the decision circuit6, without using a correction circuit.(12) The access time of the output signal DQ of the memory a chip2is measured by generating an EOR logical signal of the clock signal CLK and the output signal DQ and counting the pulse width of that EOR logical signal by means of the frequency counter.(13) In case where a multi-bit output signal is read from the memory chip2, as shown inFIG. 17, the output signal of each bit is supplied to the OR circuit40aand the AND circuit41a. In response to the logical output signals of the OR circuit40aand the AND circuit41a, the first and second frequency counters perform the counting operations. The access time determining circuit38measures the access time of the output signal based on the count values.(14) As shown inFIG. 20, the skew of a multi-bit output signal can be measured and determined.

InFIG. 10, the BOST chip3may be retained in a package which has contactors formed on both sides.

The operational test may be performed on other semiconductor IC chips than a memory chip.