Efficient phase calibration methods and systems for serial interfaces

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

FIELD

The present application generally relates to phase calibration techniques, and more particularly to efficient phase calibration methods and systems for serial interfaces.

BACKGROUND

Transferring data over high-speed serial interfaces rely on clock signals to be calibrated with the data that is being sent over the interface. Uncalibrated clock signals may sometimes result in receiving unreliable, error prone data. Therefore, techniques for efficiently calibrating clock signals are desired.

SUMMARY

According to an embodiment, a phase calibration method is described. The method may include: receiving a serial clock signal; receiving a serial data signal; sweeping a plurality of phase codes applicable to the serial clock signal to shift a phase of the serial clock signal; identifying a first phase code out of the plurality of phase codes, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value; identifying a second phase code out of the plurality of phase codes, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value; identifying a third phase code out of the plurality of phase codes, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value; identifying a fourth phase code out of the plurality of phase codes, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value; determining an average phase code based on the first phase code, the second phase code, the third phase code, and the fourth phase code; and applying the average phase code to a phase interpolator to shift the phase of the serial clock signal.

The serial data signal may include a training pattern that is the same as the serial clock signal, and each of the first, second, third, and fourth threshold number of bits may correspond to about 0% to about 5% of total bits extracted.

The particular value may include ones or zeros, wherein the ones may include bits that are extracted from the serial data signal at points that are earlier than intended, and wherein the zeros may include bits that are extracted from the serial data signal at points that are later than intended.

The sweeping the plurality of phase codes may include sweeping three unit intervals of the serial data.

The applying the average phase code to the phase interpolator to shift the phase of the serial clock signal may include shifting the serial clock signal such that an edge of the serial clock signal is aligned with middle of data eye of the serial data signal.

The extracted bits from the serial data signal may include a first bit corresponding to a rising edge of the serial clock signal and a second bit corresponding to a falling edge of the serial clock signal.

The method may further include: sweeping a first window of phase codes to identify an updated first phase code and an updated second phase code, wherein the first window begins at the first phase code minus a constant and ends at the second phase code plus the constant; sweeping a second windows of phase codes to identify an updated third phase code and an updated fourth phase code, wherein the second windows begins at the third phase code minus the constant and ends at the fourth phase code plus the constant; determining an updated average phase code based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code; and applying the updated average phase code to the phase interpolator to further shift the serial clock signal.

The constant may be a predetermined value that is programmable.

The updated first phase code may be different from the updated second phase code, and the updated third phase code is different from the updated fourth phase code.

According to another embodiment a system is described. The system may include: a memory storing computer-executable instructions; and a processor configured to execute the instructions and causes the system to perform operations comprising: receiving a serial clock signal; receiving a serial data signal; sweeping a plurality of phase codes applicable to the serial clock signal to shift a phase of the serial clock signal; identifying a first phase code out of the plurality of phase codes, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value; identifying a second phase code out of the plurality of phase codes, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value; identifying a third phase code out of the plurality of phase codes, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value; identifying a fourth phase code out of the plurality of phase codes, wherein the fourth phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be the particular value; determining an average phase code based on the first phase code, the second phase code, the third phase code, and the fourth phase code; and applying the average phase code to a phase interpolator to shift the phase of the serial clock signal.

The system of may include further instructions that causes the system to perform operations including: sweeping a first window of phase codes to identify an updated first phase code and an updated second phase code, wherein the first window begins at the first phase code minus a constant and ends at the second phase code plus the constant; sweeping a second windows of phase codes to identify an updated third phase code and an updated fourth phase code, wherein the second windows begins at the third phase code minus the constant and ends at the fourth phase code plus the constant; determining an updated average phase code based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code; and applying the updated average phase code to the phase interpolator to further shift the serial clock signal.

According to another embodiment, a phase calibration method may be described. The method may include: receiving a serial clock signal; receiving a serial data signal; sweeping a first window of phase codes, applicable to the serial clock signal to shift a phase of the serial clock signal, to identify an updated first phase code and an updated second phase code, wherein the first window begins at a predetermined first phase code minus a constant and ends at a predetermined second phase code plus the constant; identifying the updated first phase code, wherein the updated first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value; identifying the updated second phase code, wherein the updated second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value; sweeping a second window of phase codes, applicable to the serial clock signal to shift the phase of the serial clock signal, to identify an updated third phase code and an updated fourth phase code, wherein the second window begins at a predetermined third phase code minus the constant and ends at a predetermined fourth phase code plus the constant; identifying the updated third phase code, wherein the updated third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value; identifying the updated fourth phase code, wherein the updated fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value; determining an average phase code based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code; and applying the average phase code to a phase interpolator to shift the phase of the serial clock signal.

Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

DETAILED DESCRIPTION

Embodiments of the present disclosure relate to devices that use high-speed serial data interfaces to transfer data from one device to another. One example of the high-speed serial data interface may be a mobile display interface such as MIPI D-PHY that transfers video and/or audio data from one device to another device. Other examples of high-speed serial data interfaces may include DDR interfaces or other high-speed serial data interfaces known to those skilled in the art. More generally, the embodiments of the present disclosure relate to phase calibration techniques in forwarded-clock PHY protocols to adjust the phase of the forwarded clock to ensure data is sampled correctly.

FIG. 1illustrates an electronic device with a serial interface and an example block diagram of a phase calibration circuit, according to embodiments of the present disclosure.

According to an embodiment, a transmitter102is configured to send data to a receiver108that is coupled together over a high-speed serial data interface, such as a MIPI D-PHY interface. For example, the transmitter102may be a computer tablet and the receiver108may be a display device, and the computer tablet may be configured to send video data to the display device to be displayed. In some embodiments, the transmitter102includes at least a clock transmitter104and a data transmitter106, and the receiver108includes at least a clock receiver110and a data receiver112. The clock transmitter104is configured to transmit a serial clock signal which is received by the clock receiver110, and the data transmitter106is configured to transmit a serial data signal which is received by the data receiver112. Accordingly, a slicer (or sampler)118coupled to the receiver is configured to sample the received serial data signal based on the received clock signal, for example, at every rising edge of the clock signal.

In some embodiments, the transmitter102and the receiver108may be part of the same electronic device or system. For example, the transmitter102and the receiver108may both be within the display device connected via the high-speed serial interface. In other embodiments, the transmitter102and the receiver108may both be within a single computer connected via the high-speed serial interface, and configured to transfer data from one area of the computer to another area.

According to an embodiment as illustrated inFIG. 1, a periodic square wave clock signal is transmitted by the clock transmitter104and the data signal is transmitted by the data transmitter106. Here, the clock signal and the data signal are transmitted such that the edges (e.g., rising edge or falling edge) of the clock signal aligns with the middle of the data eye as illustrated at122inFIG. 1. This alignment is desirable because the data signal is sampled by the slicer118by using an edge of the clock signal, for example, the rising edge of the clock signal. By aligning the edge of the clock signal and with the middle of the data eye, it assures that the correct data is sampled. That is, if the data is a logic 1, then a logic 1 is sampled, and if the data is a logic 0, then a logic 0 is sampled because the clock edge is in the middle of the data eye where the data does not change from a 1 to a 0 or from a 0 to a 1.

As the clock signal and the data signal are transmitted to a receiver over the high-speed serial interface, the phase of the clock signal may be shifted (e.g., relative to the data signal). In some instances, the phase of the clock signal may shift such that the edge of the clock signal becomes aligned or approximately aligned with the edge of the data signal as illustrated at124inFIG. 1. When this happens and the slicer118samples the data signal at, for example, the rising edge of the clock signal, but the sampler may not extract an accurate sample of the data because the clock signal and the data signal are no longer aligned. That is, the sampled data may be extracted as a logic 1 or a logic 0 depending on whether the data signal is sampled slightly earlier or slightly later. Thus, it is desirable to calibrate the phase shift in a phase calibration process so that the edges of the received clock signal aligns with the middle of the data eye of the data signal as originally transmitted by the transmitter102. Accordingly, by performing the phase calibration, the clock signal and the data signal may be properly aligned as illustrated at126inFIG. 1. In some embodiments, the phase calibration may be performed initially when the system or devices are turned on. In other embodiments, the phase calibration may be performed periodically or at some regular interval during operation (e.g., when there is a pause in data transmission) by sending calibration data or training data. Yet in other embodiments, a combination of initial phase calibration and periodic phase calibration may be performed to further reinforce a properly calibrated serial interface.

According to an embodiment, a phase interpolator116is coupled to the serial clock receiver108and is configured to receive a phase shifted clock signal. The slicer118is coupled to the data receiver112and is configured to receive the data signal. The phase shifted clock signal is sent from the phase interpolator116to the slicer118, and the slicer118samples the received serial data based on this phase shifted clock signal. Thus, the embodiments of the present disclosure provide techniques for phase calibrating the phase shifted clock signal so that the phase interpolator116may provide a phase adjusted (or phase calibrated) clock signal to the slicer118so that the slicer118may correctly sample data. In some embodiments, a training data signal that is the same or substantially the same signal as the serial clock signal, comprising alternating zeros and ones, may be provided to the slicer118to perform the phase calibration.

According to an embodiment, the sampled data from the slicer118is provided to a deserializer120which deserializes the serial data signal and provides the deserialized data to a phase calibrator114. In some embodiment, the deserialized data may be a block of 16 bits of data, yet in other embodiments, the deserialized data may be a block of 32, 64, or any predefined number of bits of data. The phase calibrator114then takes the deserialized data and performs a phase calibration process to determine a phase code, which will be provided to and used by the phase interpolator116to adjust the phase shifted clock signal.

FIGS. 2A-2Billustrate a case where the clock signal has moved or shifted due to, for example, external factors such as interferences from cables, connections, etc. More in particular,FIG. 2Aillustrates a serial clock signal and a serial data signal where the serial clock signal has moved to the right relative to a clock signal that is properly calibrated. Here, a properly calibrated clock signal is one where the rising edge of the clock signal is aligned with the center of the data eye (e.g., center of the zeros) of the data signal as illustrated at122inFIG. 1, and therefore, the clock signal inFIG. 2Ais shown to have moved to the right because the rising edge is aligned away from the center of the zeros of the data signal and closer toward the rising edge of the data signal. Accordingly, the data signal lags the clock signal and the slicer118may sample the data signal at points that are later than intended with a properly calibrated clock signal, which is referred to herein the present disclosure as “late bits.” In other words, the data signal is sampled closer to the rising edge of the data signal instead of toward the center of the data eye of the data signal during the rising edge of the clock signal.

FIG. 2Billustrates a serial clock signal and a serial data signal where the serial clock signal has moved to the left relative to a clock signal that is properly calibrated. Here, a properly calibrated clock signal is one where the rising edge of the clock signal is aligned with the center of the data eye (e.g., center of the ones) of the data signal as illustrated at122inFIG. 1, and therefore, the clock signal inFIG. 2Bis shown to have moved to the left because the rising edge is aligned away from the center of the ones of the data signal and closer toward the rising edge of the data signal. Accordingly, the data signal leads the clock signal and the slicer118may sample the data signal at points that are earlier than intended with a properly calibrated clock signal, which may be referred to herein the present disclosure as “early bits.” In other words, the data signal is sampled closer to the rising edge of the data signal instead of toward the center of the data eye of the data signal during the rising edge of the clock signal. A late or a lagging data signal, as depicted inFIG. 2A, or an early or a leading data signal, as depicted inFIG. 2B, may result in the slicer118generating incorrect data, particularly if the data is sampled too close to the edges of the data signal. Therefore, the clock signal may be phase calibrated by shifting the clock signal inFIG. 2Ato the left such that the edges of the clock signal aligns with the middle of the data eye of the data signal, and the clock signal inFIG. 2Bmay be phase calibrated by shifting the clock signal to the right such that the edge of the clock signal aligns with the middle of the data eye of the data signal.

In some embodiments, the data may be sampled at the rising edge of the clock signal and if the sampled data is all or mostly all zeros as illustrated inFIG. 2A, then the phase calibrator may determine that the data signal lags the clock signal, and therefore the data signal is sampled at a later time than intended. On the other hand, if the sampled data is all or mostly all ones as inFIG. 2B, then the phase calibrator114may determine that the data signal leads the clock signal, and therefore the data signal is sampled at an earlier time than intended. Moreover, in some embodiment, sampled data that is all or mostly zeros may instead indicate that the data signal is sampled earlier (instead of later) because a different data signal pattern may be used and/or the data may be sampled at the falling edges of the clock signals. Similarly, sampled data that is all or mostly ones may instead indicate that the data signal is sampled later (instead of earlier) for the same reasons. Accordingly, the phase calibrator114may look for all or mostly all zeros, or all or mostly all ones so that an appropriate phase code may be applied to the clock signal to shift the edge of the clock signal to align with the middle of the data eye of the data signal.

Similar toFIG. 2A,FIG. 3Aillustrates a serial clock signal and a serial data signal where the clock signal has moved to the right relative to a clock signal that is properly calibrated. Here, a properly calibrated clock signal is one where the rising edge of the clock signal is aligned with the center of the data eye of the zeros of the data signal, and the falling edge of the clock signal is aligned with the center of the data eye of the ones of the data signal, and therefore, the clock signal inFIG. 3Ais shown to have moved to the right because the rising edge is aligned away from the center of the data eye of zeros of the data signal and closer toward the rising edge of the data signal, and the falling edge is aligned away from the center of the eye of ones of the data signal and closer toward the falling edge of the data signal. Accordingly, the data signal lags the clock signal and the slicer118may sample the data signal at points that are later than intended.

Similar toFIG. 2B,FIG. 3Billustrates a serial clock signal and a serial data signal where the clock signal has moved to the left relative to a clock signal that is properly calibrated. Here, a properly calibrated clock signal is one where the rising edge of the clock signal is aligned with the center of the data eye of the ones of the data signal, and the falling edge of the clock signal is aligned with the center of the data eye of the zeros of the data signal. Therefore, the clock signal inFIG. 3Bis shown to have moved to the left because the rising edge is aligned away from the center of the data eye of ones of the data signal and closer toward the rising edge of the data signal, and the falling edge is aligned away from the center of the eye of zeros of the data signal and closer toward the falling edge of the data signal. Accordingly, the data signal leads the clock signal and the slicer118may sample the data signal at points that are earlier than intended. However, differently fromFIGS. 2A-2B,FIGS. 3A-3Billustrate data sampling techniques where the data is sampled at both the rising edge and the falling edge of the serial clock signal. For example, referring toFIG. 3A, if all of the even bits of the sampled data are zeros and all of the odd bits of the sampled data are ones, then the phase calibrator114may determine that the data signal lags the clock signal, according to an embodiment. On the other hand, if all of the even bits of the sampled data are ones and all of the even bits of the sampled data are zeros, then the phase calibrator114may determine that the data signal leads the clock signal, according to an embodiment.

In some embodiments, the phase calibrator114may set a phase code depending on whether the data is being sampled early or late, so that the phase shift of the clock signal may be adjusted such that the edges of the clock signal will align with the middle of the data eye of the data signal. A phase code may be, for example, a numerical value represented by 8-bits, i.e., 0-255, corresponding to 256 different incremental shifts to the clock signal. Accordingly, when a phase code is applied to the phase interpolator116, the phase interpolator116may shift the phase of the clock signal by an amount that is associated with the given phase code. For example, a phase code of 1 may correspond to a 1.4 degrees phase shift to the clock signal. Therefore, when the phase code of 1 is applied to the phase interpolator116, the phase interpolator116may shift or offset the clock signal by 1.4 degrees. In another example, a phase code of 37 may correspond to a phase shift of 52 degree to the clock signal. Therefore, when the phase code of 37 is applied to the phase interpolator116, the phase interpolator116may shift or offset the clock signal by 52 degrees. Thus, the phase interpolator116may offset, and thereby adjust the phase of the clock signal based on the phase code that is provided to the phase interpolator116. Accordingly, the phase adjusted clock signal may be used to sample the serial data signal by the slicer118, and the sampled data may be deserialized120and then analyzed by the phase calibrator114to determine whether the clock signal is adjusted as desired. In one embodiment, the desired outcome is when the clock signal is calibrated such that the rising edge of the clock signal is aligned with the center of the data eye of the data signal. Accordingly, different phase codes may be applied to the phase interpolator116until the desired phase shifted clock signal is achieved through trial and error.

By sampling the data at both the rising edge and the falling edge of the clock signal, for example in a DDR-based seral link where one clock cycle is equivalent to two unit intervals, the data signal may be sampled faster (i.e., at twice the speed) than sampling the data at just the rising edge or just the falling edge of the clock signal (e.g., a given number of bits may be sampled from the data signal in half the number of clock cycles compared to sampling only on falling edges or only rising edges). Because phase calibration algorithms may depend on sampling a particular number of bits, by sampling the data at a faster speed, the phase code may be determined and set at a faster speed and the phase shifted clock signal may be adjusted faster, thus improving the speed of the overall phase calibration process.

FIG. 4is a graph representing a percentage of bits of data that are ones that are sampled early (“early bits”) by the clock signal for each phase code during a phase code sweep. For example, a phase code that is represented by 8-bits has 256 different phase codes that causes the clocks signal to shift by 256 different increments, and the percentage of ones obtained as a result of each of the 256 different clock phases may be plotted in the graph to generate a graph of phase code vs. percentage of ones, as illustrated inFIG. 4. That is, for each phase code out of the plurality of phase codes that are swept, the percentage of bits that are ones are plotted in this graph. The lower regions of the graph correspond to phase codes where substantially none (e.g., 0-5%) of the extracted data bits from the phase code sweep are ones. In other words, almost all of the extracted data bits (e.g., 95-100%) are sampled later (“late bits”) by the clock signal. On the other hand, the upper regions of the graph correspond to phase codes where substantially all (e.g., 95-100%) of the extracted data bits from the phase code sweep are ones. The middle regions of the graph correspond to phase codes where the about half of the extracted bits are ones and about half of the extracted bits are zeros. Accordingly, this 50% threshold corresponds to when the edges of the serial clock signal align with the edges of the serial data signal. Therefore, by determining the phase codes that correspond to the 50% threshold, the clock signal may be adjusted by shifting the clock signal away from the 50% threshold point so that the edges of the clock signal aligns with the middle of the data eye.

According to an embodiment, the phase codes corresponding to POINT1and POINT2inFIG. 4may be saved and averaged, to determine the average phase code, which may then be applied to the clock signal to align the edges of the clock signal with the middle of the data eye of the data signal. In other words, as the phase code is swept, a plurality (e.g., 64, 128, 256, etc.) different phase adjusted clock signals are generated by the interpolator116, and when the percentage of ones increase from about zero to about 50% (i.e, about 50% of the bits are early and about 50% of the bits are not early), then the corresponding phase code may be saved as POINT1. The phase code may then continue to sweep and the percentage of ones will increase to about 100% and then begin to decrease again. When the percentage of ones decrease to about 50% again, then the corresponding phase code can be saved as POINT2. However, this technique of setting the phase code may be relatively slow and prone to errors. For example, when the edges of the clock signal and the edge of the data are aligned, the data samples may become jittery, thus resulting in false detection of the phase code as shown with the graph as illustrated inFIG. 5where the average of POINT1and POINT2do not necessarily reflect a phase code corresponding to 50% ones.

FIG. 6, likeFIG. 4, is a graph that represents a percentage of ones during a phase code sweep. Differently fromFIG. 4, however,FIG. 6illustrates a 4-point detection technique for determining the correct phase code by saving different POINTS of the phase code sweep graph to avoid or reduce errors that may result due to jitters. Accordingly, a more accurate phase code may be determined.

According to the embodiment, a plurality of phase codes may be swept to determine the percentage of ones. For example, the phase codes may be made up of any number of bits, for example, 8-bits comprising 256 different phase codes that are applied to the phase interpolator to generate 256 different phase adjusted clock signals, which are used to sample the data signal and the percentage of ones is determined from the sampled bits. In order to determine which phase codes generate about 50% ones and 50% zeros, two phase codes that correspond to substantially no ones (e.g., no ones plus some threshold such as about 0-5% ones) are saved, and two phase codes that correspond to substantially all ones (e.g., all ones plus some threshold such as amount 95-100% ones) are saved.

More particularly, as the phase code sweep is performed, as the percentage of the ones increases from zero to near-zero (e.g., about 5%), that corresponding phase code is saved as POINT1as illustrated inFIG. 6. As the phase code sweep continues, the percentage of ones increases toward 100%. The phase code corresponding to near-100% (e.g., about 95%) to 100% is saved as POINT2as illustrated inFIG. 6. In some embodiments, the phase code sweep continues and eventually, the percentage of ones begin to decrease again. Here, as the percentage of ones begin to decrease from 100% to near-100% (e.g., about 95%), that corresponding phase code is saved as POINT3as illustrated inFIG. 6. Finally, the phase code sweep continues to decrease and the phase code corresponding to near-zero (e.g., about 5%) to zero is saved as POINT4.

In some embodiments, the average of these four phase codes, POINT1, POINT2, POINT3, and POINT4may be computed to determine a final phase codes that corresponds to about 50% ones. That is, for example, if there are 256 phase codes and if phase codes corresponding to POINTS1,2,3,4are 40, 60, 200, 215, respectively, then the average phase code is (40+50+200+215)/4=126.25. According to an embodiment, once the phase codes that correspond to the 50% ones is computed through the averaging of the four saved POINTS, the final averaged phase code is applied to the phase interpolator116to adjust the clock phase so that the edges of the clock signal aligns with the middle of the data eye of the data signal. Additionally, phase codes are circular, and therefore “wrap around.” For example, for phase codes that range from 0 to 255, and the phase codes corresponding to POINTS1,2,3,4are 190, 192, 64, 66, respectively, then the “circular” average is (190+192+(64+256)+(66+256)/4=256=0.

According to another embodiment of the present disclosure, a fast calibration technique is described. The fast calibration technique may be initiated after an initial execution of the 4-point detection technique. For example, the fast calibration technique may be used to perform phase calibration on the system periodically during use or during pauses between operations.FIG. 7is a graph of a phase code sweep vs. the percentage of ones according to the fast calibration technique. Differently from the 4-point detection technique described above with reference toFIG. 6, the fast calibration technique performs phase code sweeps in smaller ranges, for example, by performing a first window of phase code sweep over a smaller range of phase codes, and then performing second window of phase code sweep over another smaller range of phase codes to reduce the amount of time spent sweeping the phase codes.

In some embodiments, the first window of phase code sweep may begin at N phase codes before the POINT1and end at N phase codes after POINT2, where N corresponds to a predetermined or programmable constant value. In other words, similar toFIG. 6, POINT1inFIG. 7may be a phase code that corresponds to zero to substantially zero (e.g., about 5%) ones and POINT2may be a phase code that corresponds to substantially all (e.g., about 95%) or all ones and the phase code sweep starts at N phase codes before this POINT1(i.e., POINT1−N) and ends at N phase codes after POINT2(i.e., POINT2+N). Accordingly, the first window of phase code sweep is substantially less than a full phase code sweep as described with reference toFIG. 6.

According to one example, N may be selected to be a value of 4 (out of 256 phase codes). Thus, the first window of the phase code sweep will start at 4 phase codes before POINT1and end at 4 phase codes after POINT2. Accordingly, the programmable N values allow an end user to vary a trade-off between speed of calibration and phase-drift tolerance. That is, a larger N value may take a longer time to perform the sweep, thus resulting in a slower calibration, but will be able to tolerate a larger phase code drift by up to N-codes from the last calibration. On the other hand, a smaller N value may take less time to perform the sweep, thus resulting in a faster calibration, but will be able to tolerate smaller phase code drifts.

In some embodiments, the second window of phase code sweep may begin at N phase codes before POINT3and end at N phase codes after POINT4. In other words, similar toFIG. 6, POINT3may be a phase code that corresponds to substantially all (e.g., about 95%) to all ones and POINT4may be a phase code that corresponds to zero to substantially zero (e.g., about 5%) ones and the phase code sweep starts at N phase codes before this POINT3(i.e., POINT3−N) and ends at N phase codes after POINT4(i.e., POINT4+N). Accordingly, the second window of phase code sweep is substantially less than a full phase code sweep as described with reference toFIG. 6. In other words, the first window of phase codes and the second window of phase code are swept, but the phase codes between POINT2+N and POINT3−N are not swept. Also, the phase codes before POINT1−N and the phase codes after POINT4+N are not swept. Therefore, the amount of time spent in sweeping the phase codes may be reduced, being able to obtain POINT1, POINT2, POINT3, and POINT4much faster.

Next, the average phase codes of POINT1, POINT2, POINT3, and POINT4may be computed to determine a final phase codes that corresponds to about 50% ones. According to an embodiment, once the phase codes that correspond to the 50% ones is computed through the averaging of the four saved POINTS, the final averaged phase code is applied to the phase interpolator116to adjust the clock phase so that the edges of the clock signal aligns with the middle of the data eye. Thus, similar results to the method described with reference toFIG. 6may be achieved much faster according to this this technique by utilizing the phase code information obtained earlier. That is, for example, the phase code corresponding to POINT1from a previous calibration cycle may be used to obtain POINT1−N, and start the phase code sweep at POINT1−N and skipping the region before POINT1−N. Similarly, the region between POINT2+N and POINT3−N may be skipped before the phase code corresponding to POINT3is already known from a previous calibration cycle and therefore the second window of phase code sweep may be started at POINT3−N.

FIG. 8is a flow chart of the 4-point detection technique and the fast calibration technique. According to an embodiment, a phase calibration request is received by the phase calibrator114to calibrate the serial clock signal with the serial data signal. During initial calibration, an initial calibration method (804) using the 4-point detection technique may be executed. Alternatively, during periodic calibration, a periodic calibration method (816) using the fast mode calibration technique may be executed. In some embodiments, the initial calibration method (804) may be executed even when a periodic calibration is desired, however, the initial calibration method may take longer to execute than the periodic calibration method.

Once the initial calibration mode is selected, the phase code sweeping process may begin. As previously discussed, the phase code sweep may include any number of different phase codes, for example 256 phase codes wherein each one corresponds to a clock signal that is shifted slightly (e.g., 1/256th of a clock cycle). According to an embodiment, the phase code is first set to 0 (806), which corresponds to the first phase code out of a plurality of phase codes that will be used during a phase code sweep (e.g., 1st phase code out of 0 to 255 phase codes). In some embodiments, the phase code may be a 6-bit phase code comprising 64 phase codes for a phase code sweep. Yet in other embodiments, the phase code may be an 7-bit phase code comprising 128 phase codes for a phase code sweep. For purposes of providing an example in this disclosure, the phase code is assumed to be 8-bits by way of example only.

Next, the phase code is swept by applying a plurality of phase codes to the phase interpolator (808). As the phase code sweep is executed, the phase of the clock is adjusted and the percentage of ones may be determined from the sampled and deserialized data, varying from no ones to all ones. When 0 to nearly 0% (e.g., about 5%) of the bits are ones, the corresponding phase code is saved as POINT1, as described with reference toFIG. 6(810). According to an embodiment, the phase code sweep is performed for three unit intervals (UIs) (e.g., duration of one bit of serial clock) to capture POINT1, POINT2, POINT3, and POINT4as described with reference toFIG. 6. For example, POINT2is saved when the percentage of ones is nearly 100% (e.g., about 95%) to 100%, POINT3is saved when the percentage of ones is nearly 100% (e.g., about 95%) to 100%, and POINT4is saved when the percentage of ones is nearly 0% (e.g., about 5%) to 0%. Once the four POINTS are saved (812), a final phase code is calculated by averaging the phase codes corresponding to POINT1-POINT4(838), and the calculated phase code is applied to the phase interpolator116(840). If the phase code sweep has not been performed for three UIs (812), then the phase code will be incremented to the next phase code, e.g., from phase code 1 to phase code 2, and so on, and then steps808-812will be repeated until three UIs have been swept and the four POINTS have been saved.

In some embodiments, the periodic calibration method using the fast calibration technique may be executed (816). First, the phase code is set to POINT1−N (818), where N is a predetermined or a programmable constant. The phase code for POINT1may be determined from a previous phase code sweep, for example, from the initial calibration mode. Next, a first window of phase codes are swept by applying a plurality of phase codes to the phase interpolator (820). As the first window phase code sweep is executed, the phase of the clock is adjusted and the percentage of ones may be determined from the sampled and deserialized data, varying from no ones to all ones. When 0 to near-0% (e.g., about 5%) of the bits are ones, the corresponding phase code is saved as POINT1, as described with reference toFIG. 7(822). The first window phase code sweep is continued and when the phase code is equal to POINT2+N, the first window of phase code sweep has been executed for the first two POINTS (824). If the phase code does not equal to POINT2+N, then the phase code is incremented and steps820-824are repeated until both POINT1and POINT2are saved (826). Then, once POINT1and POINT2are saved, then the phase code is set to POINT3−N (828), and a phase code sweep of the second window is executed and applied to the phase interpolator (830). When the percentage of ones is nearly 100% (e.g., about 95%) to 100% of ones is determined, the corresponding phase code is saved as POINT3, as described with reference toFIG. 7(832), and checked to see if the phase code is equal to POINT4+N, which indicates that the phase code sweep has been executed for the third and fourth POINTS (834). If the phase code does not equal POINT4+N, then the phase code is incremented (836) and steps830-834are repeated until both POINT3and POINT4are saved (836). Once both POINT3and POINT4are saved, a final phase code may be calculated by averaging the phase codes corresponding to POINT1, POINT2, POINT3, and POINT4(838), and the calculated phase code is applied to the phase interpolator (840). Once the calibration cycle is completed, the phase calibrator enters an idle state and waits until another calibration request is received (842).

According to an embodiment, once the phase interpolator116is updated with the calculated final phase code, the phase interpolator116may adjust the clock signal and provide the now calibrated clock signal to the slicer118, which will then use this calibrated clock signal to sample incoming serial data. Accordingly, the edges of the calibrated clock signal now align with the middle of the data eye of the incoming serial data signal.

While the above described techniques refer to percentage of ones (e.g., bits that are early), in other embodiments, the bits may instead be zeros (e.g., bits that are late). Thus, 4-point detection technique or the fast calibration technique may utilize the percentage of zeros instead of the percentage of ones by applying the same techniques.

In some embodiments, multiple calibration techniques may be performed together to achieve improved calibration results. For example, the 4-point detection technique described above with reference toFIG. 6may be applied together with the two-edge sampling technique described above with reference toFIGS. 3A-3Bwhere the data is sampled at both the rising edge and the falling edges of the clock signal. Yet, in other embodiments, the fast calibration technique described above with reference toFIG. 7may be applied together with the two-edge sampling technique described above with reference toFIGS. 3A-3B.

Embodiments described herein are examples only. One skilled in the art may recognize various alternative embodiments from those specifically disclosed. Those alternative embodiments are also intended to be within the scope of this disclosure. As such, the embodiments are limited only by the following claims and their equivalents.