Successive approximation register analog to digital converters

A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an analog to digital converter (ADC), and more particularly to an ADC that uses successive approximation techniques.

2. Description of the Related Art

Analog to digital converters (ADCs) are widely used in a variety of applications, such as medical systems, audio systems, test and measurement equipment, communication systems, and image and video systems, etc. The most common ADC construction comprises flash ADCs, pipeline ADCs and successive approximation register (SAR) ADCs. The power consumption of the SAR ADC is smaller than the flash ADC and the pipeline ADC. Thus the systems with limited power supply, such as portable devices, usually use SAR ADCs.

The conversion accuracy of the SAR ADCs is mainly subject to the DAC mismatch and offset errors. Particularly, for the switched-capacitor SAR ADCs, the capacitor mismatch is the dominant one.

BRIEF SUMMARY OF THE INVENTION

Thus, it is desired to provide a successive approximation register circuit which can correct error caused by the capacitor mismatch.

An exemplary embodiment of a successive approximation register (SAR) analog to digital converter (ADC) circuit is provided. The SAR ADC circuit receives an analog input signal and operates in a sample phase and a conversion phase following the sample phase to generate a digital output signal. The SAR ADC circuit comprises a plurality of capacitors, a comparator, and a logic unit. The plurality of capacitors are coupled to a summing node. Before the conversion phase, a target capacitor among the plurality of capacitors is coupled to a direct current (DC) voltage and the other capacitors among the plurality of capacitors are coupled to the analog input signal. The comparator has an input terminal coupled to the summing node. In the conversion phase, the comparator performs a comparison operation to a summing voltage at the summing node The logic unit has a plurality of weighting values corresponding to the plurality of capacitors respectively and generates the digital output signal according to the weighting values and a comparison result of the comparison operation. The DC voltage has a first voltage level or a second voltage level different from the first voltage level according to a random sequence. The weighting value of the target capacitor is calibrated according to the digital output signal and the random sequence.

An exemplary embodiment of a successive approximation register (SAR) analog to digital converter (ADC) circuit is provided. The SAR ADC circuit receives an analog input signal and operates in a sample phase and a conversion phase following the sample phase to generate a digital output signal. The SAR ADC circuit comprises a first switch, a plurality of capacitors, a plurality of second switches, a plurality of switch circuits, a comparator, a logic unit, and an extraction and compensation unit. The first switch is coupled between a first voltage and a summing node. Each capacitor has a first terminal coupled to the summing node and further has a second terminal. Each second switch is coupled between the second terminal of one of the plurality of capacitors and a second voltage. The plurality of switch circuits receives the analog input signal, Each switch circuits is coupled to the second terminal of one of the plurality of capacitors and, before the conversion phase, provides a DC voltage or the analog input signal to the corresponding capacitor. The comparator has an input terminal coupled to the summing node. In the conversion phase, the comparator performs a comparison operation to a summing voltage at the summing node. The logic unit has a plurality of weighting values corresponding to the plurality of capacitors respectively and generates the digital output signal according to the weighting values and a comparison result of the comparison operation. The extraction and compensation unit receives the digital output signal. When a target capacitor among the plurality of switch circuits receive the DC voltage from the corresponding switch circuit, the DC voltage has a first voltage level or a second voltage level different from the first voltage level based on a random sequence,. The extraction and compensation unit obtains a calibrated weighting value according to the digital output signal and the random sequence, and the calibrated weighting value serves as the weighting value of the target capacitor.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows an exemplary embodiment of a successive approximation register (SAR) analog to digital converter (ADC) circuit. As shown inFIG. 1an SAR ADC circuit1comprises an SAR DAC10, and an extraction and compensation unit11. The SAR ADC circuit1operates in a sample phase and a conversion phase following the sample phase in several cycles. The SAR ADC10receives an analog input signal Vinand generates a digital output signal Doaccording to the analog input signal Vin, weighting values of capacitors (shown inFIG. 2) , a direct current (DC) voltage, and a random signal q·Vr, wherein q represents is a binary value random sequence which is uncorrelated with the analog input signal Vin, and each value of the random sequence is equal to 1 or −1. Thus, the voltage level of the random signal q·Vris the level of −Vror Vr. In the embodiment, the random signal q·Vris injected to at least one capacitor (shown inFIG. 2) to be calibrated in the SAR ADC10. Thus, the digital output signal Docomprises one term related to the random signal q·Vr. The extraction and compensation unit11extracts the real weighting value of the capacitor to be calibrated according to the digital output signal Doand the random signal q·Vr. Then, the extraction and compensation unit11corrects the digital output signal Dobased on the real weighting value of the capacitor to be calibrated

The detailed structure of the SAR DAC10is shown inFIG. 2. As shown inFIG. 2, the SAR DAC10comprises N capacitors C0˜CN−1, a sample switch SWS, N switches SW0˜SWN−1, N switch circuits SWC0˜SWCN−1, a comparator20, and a logic unit21, wherein N is an positive integer. The sample switch SWS is coupled to a summing node N20and a signal. In the embodiment, the signal which is coupled to the sample switch SWS is a ground voltage GND. One terminal of the comparator20is coupled to the summing node N20, and the other terminal thereof is coupled to the ground voltage GND. Each of the capacitors C0˜CN−1has two terminals. A first terminal of each capacitor is coupled to the summing node N20. In the embodiment, a second terminal of each capacitor is coupled to one switch SWjand one switch circuit SWCj, wherein 0≦j≦N−1. For example, the other terminal of the capacitor CN−1is coupled to the switch SWN−1and the switch circuit SWCN−1, and the other terminal of the capacitor C0is coupled to the switch SW0and the switch circuit SWC0. The sample switch SWS, the N switches SW0˜SWN−1, and the N switch circuits SWC0˜SWCN−1are controlled by the logic unit21.

The each of the switch circuits SWC0˜SWCN−1receives the analog input signal Vinand the random signal q·Vr. Each switch circuit is controlled by the logic unit21to provide the analog input signal Vinor a DC voltage to the corresponding capacitor. The level of the DC voltage is determined by the random signal q·Vr, that is the level of the DC voltage is the level of −Vror Vr.FIG. 3shows the timing of the sample phase and the conversion phase of the SAR ADC circuit10InFIG. 3, φ1erepresents the timing of the sample phase, φSARrepresents the timing of the conversion phase, and φ1represents the timing of the operation of the switch circuits. In the sample phase between a time point T1and a time point T2, the sample switch SWS is turned on. In the case, it is desired to calibrate the weighting value of one capacitor Cj(also referred to as “target capacitor”) of the capacitor C0˜CN−1, before the occurrence of the conversion phase (that is before the time point T4), the corresponding switch circuit SWCjprovides the DC voltage to the one capacitor Cj, and the other switch circuits provide the analog input signal Vinto the corresponding capacitors. Atthe sampling time, the charge stored at the summing node N20is equal to:
Qx,lc=−Vin×Ctot+Vin×Cj−q·Vr×Cj(1)
where Ctot=Σi=0N−1Ci.

In the conversion phase between the time point T4and a time point T5, the switches SWN−1˜SW0are sequentially turned on to provide the voltage Vr to the respective capacitors SWN−1˜SW0. The comparator20determines the binary code word from MSB bN−1to the LSB b0by examining the polarity of the voltage at the summing node N20sequentially. At the end of the conversion phase, the charged stored at the summing node N20is given by:

Qx,2=∑i=0N-1⁢(Vx-bi·Vr)⨯Ci(2)
where Vxrepresents the voltage at the summing node N20.

According to the charge conservation at the summing node N20, Qx,1Cis equal to Qx,2, and the voltage at the summing node N20is express as:

Ideally, since the voltage Vxapproaches zero at the end of the conversion phase, Do=[bN−1, bN−2, . . . b0] is the best quantized representation of the analog input signal Vin, and the corresponding digital value of the digital output signal Dois given by:

According to the above description, the weighting value of capacitor Cjis desired to be calibrated. As shown in Equation (4), the Rj=Vr×(Cj/Ctot) represents the weighting value of capacitor Cjand determines the real weighting value of the capacitor Cj. In order to extract the parameter Rj, the extraction and compensation unit11performs a correlation operation to the digital output signal Dowith the random sequence q and further performs a low-pass-filtering operation to the digital output signal Doto generate a calibrated weighting value Ŵjof the capacitor Cj. In other words, the digital output signal Dois correlated with the random sequence q and then low-pass filtered to obtain the weighting value Ŵj. The extraction and compensation unit11then corrects the digital output signal Doaccording to the calibrated weighting value Ŵjto generate the output signal DoC

FIG. 4shows an exemplary embodiment of an extraction circuit110in the extraction and compensation unit11. For detailed illustration,FIG. 4also shows the SAR DAC10. As shown inFIG. 4, the extraction circuit11comprises a multiplier40and a low-pass filter (LPF)41. The multiplier40receives the digital output signal Doand the random sequence q to achieve the correlation operation to the digital output signal Doand the random sequence q. The low-pass filter41is coupled to the multiplier40and performs the low-pass-filtering operation to the digital output signal Doto generate the calibrated weighting value Ŵj. According to the operations of the multiplier40and the low-pass filter41, the term Rjis retained, and the calibrated weighting value Ŵjis the digital expression of the term Rj. Thus, the calibrated weighting value Ŵjrelated to the real weighting value of the capacitor Cjis obtained and used to correct the digital output signal Do.

Finally, the digital output signal Dois corrected, and the corrected output signal is represented by:

If several weighting values of the capacitors required to be calibrated, the above operations performed to obtain the calibrated weighting value Ŵjrelated to the real weighting value of the capacitor Cjare also performed for the other capacitors required to be calibrated. The related description is omitted. For example, in the case where it is desired to calibrate the weighting values of the capacitors C0˜Cjamong the capacitor C0˜CN−1, the corresponding calibrated weighting values Ŵ0˜Ŵjthe corrected output signal is represented by:

According to Equation (5) and Equation (6), the weighting values of the capacitors can be calibrated. Even though the capacitor mismatch occurs, the digital output signal Docan more approach the accurate digital value of the analog input signal Vin.

FIG. 5shows an exemplary embodiment of the switch circuits SWC0˜SWCN−1. InFIG. 5, only the switch circuit SWjis shown. The structures of the other switch circuits are the same as the structure of the switch circuit SWj, thus, omitting the related description here. The switch circuit SWCjcomprises three switches50˜52. The switch50is coupled between the capacitor Cjand the voltage Vr. The switch51is coupled between the capacitor Cjand the voltage −Vr. The switch52is coupled between the capacitor Cjand the analog input signal Vin. The switches50-52are controlled by the logic unit21and not turned on at the same time. Thus, one of the three voltages Vr, −Vr, and Vinserves as the DC voltage provided the capacitor Cj. The logic unit21controls the switches50and51according to the random sequence q. Thus, in equivalent, the switch circuit SWCjreceives the random signal q·Vr, which determines the voltage Vr or −Vr to be provided to the capacitor Cjbefore the conversion phase.

InFIG. 3, the DC voltage (Vr or −Vr) is provided to the capacitor Cjto be calibrated in the period between the time point T1and a time point T3, as shown by φ1, however, without limitation. The DC voltage can be provided to the capacitor Cjin any period which just occurs before the conversion phase occurs (that is before the time point T4).

FIG. 6Ashows another exemplary embodiment of the SAR ADC10. The SAR ADC shown inFIG. 6Ais a differential-type, 12-bit ADC. The signals which are coupled to the sample switches SWS are analog input signals Vipand Vin. InFIG. 6A, a switch group are coupled to the capacitors C1˜C11. The switch group60comprises several switches and switch circuits as shown inFIG. 2. Each set of one switch SWjand one switch circuit SWCjis coupled to the corresponding capacitor and performs the same operations of the embodiment ofFIG. 2. Moreover, Vrpreplaces the Vrto be provided to capacitors coupled to the positive input (+) of the comparator20, while Vrnreplaces the Vrto be provided to capacitors coupled to the negative input (−) of the comparator20.

In order to calibrate the weighting values of the capacitors C8˜C11, the larger capacitance of the capacitors C9˜C11is divided to small capacitance to relax the lost of dynamic range, as shown inFIG. 6B, that is:
C9=C9,1+C9,0
C10=C10,3+C10,2+C10,1+C10,0
C11=C11,7+C11,6+C11,5+C11,4+C11,3+C11,2++C11,1+C11,0

Thus, the weighting values of the capacitors C8, C9,0˜C9,1, C10,0˜C10,3, and C11,0˜C11,7are required to be calibrated. The calibration process of the capacitor C8is the similar to the above process for calibrating the weighting value of the capacitor Cj. Thus, before the conversion phase, the charge at the input of the comparator01is equal to:

At the end of the conversion phase, the charge at the input of the comparator20is given by:

According to the charge conservation, Qφ1=QφSAR, and the voltage at the input of the comparator20is expressed as:

At the end of the conversion phase, (Vxp−Vxn) approaches to zero, and Equation (9) is rewritten as:

To extract actual weighting value of the capacitor C8, the digital output signal Dois correlated with the random q and then low-pass filtered. In the embodiment, the low-pass filtering is achieved by integration and average operations. That is, the digital output signal Dois further integrated and divided by M cycles. As shown inFIG. 7, in this embodiment the low-pass filter41is implemented by a digital accumulator (Digital Accumu.)70and a divider (1/M)71. Thus, we have:

Assume that the random sequence q is uncorrelated with the analog input signal Vin. The calibrated weighting value of the capacitor C8is obtained as:

While the calibrated weighting value Ŵ8is obtained, the digital output signal Docan be corrected according to the calibrated weighting value Ŵ8as:

The above calibration process is also performed to the C9,0˜C9,1, C10,0˜C10,3, and C11,0˜C11,7. The corresponding calibrated weighting values are given by:

After the calibration process of the weighting values of C8, C9,0˜C9,1, C10,0˜C10,3, and C11,0˜C11,7, the digital output signal Dois corrected as: