Buffer architecture formed on a semiconductor wafer

In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.

BACKGROUND

A variety of electronic and optoelectronic devices can be enabled by developing thin film relaxed lattice constant III-V semiconductors on elemental silicon (Si) substrates. Surface layers capable of achieving the performance advantages of III-V materials may host a variety of high performance electronic devices such as complementary metal oxide semiconductor (CMOS) and quantum well (QW) transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb), indium gallium arsenide (InGaAs) and indium arsenide (InAs).

Despite all these advantages, the growth of III-V materials upon silicon substrates presents many challenges. Crystal defects are generated by lattice mismatch, polar-on-nonpolar mismatch and thermal mismatch between the III-V semiconductor epitaxial layer and the silicon semiconductor substrate. Such mismatch can lead to poor electrical characteristics such as low carrier mobility and high leakage. When the lattice mismatch between the epitaxial layer and substrate exceeds a few percent, the strain induced by the mismatch becomes too great and defects are generated in the epitaxial layer when the epitaxial film relaxes the lattice mismatch strain. Many defects, such as threading dislocations and twins, tend to propagate into the “device layer” where the semiconductor device is fabricated.

DETAILED DESCRIPTION

In various embodiments, indium gallium arsenide (InGaAs)-based semiconductor devices may be formed on a silicon (Si) substrate. Using such an InGaAs-based structure, high speed and low power performance can be realized. To enable such architectures, embodiments may provide a buffer layer design to bridge material mismatch issues between an active InGaAs channel layer and the underlying Si substrate. In some implementations, a buffer design may be a dual layer including a gallium arsenide (GaAs) layer grown on the Si substrate, followed by a graded indium aluminium arsenide (InAlAs) or indium gallium aluminium arsenide (InGaAlAs) layer formed on the GaAs layer.

Such a buffer layer may serve several purposes. This buffer layer may bridge lattice constants between a substrate and a channel layer formed thereon. Furthermore, the buffer layer may provide compressive strain for carrier confinement inside a quantum well (QW) of the channel layer and may further serve as a bottom barrier to the channel layer. Still further, the buffer may provide large band offset between this bottom barrier and the channel layer, as well as provide device isolation and eliminate parallel conduction from the buffer layer to the channel layer due to the large bandgap. Accordingly, high structural and electrical quality InGaAs-based devices may be formed on a Si substrate.

Referring now toFIG. 1, shown is a cross section view of a device structure10in accordance with an embodiment of the present invention. As shown inFIG. 1, structure10may be used to form an NMOS or PMOS device on a substrate30. In various embodiments, substrate30may be a high resistivity n or p-type (100) off-oriented Si substrate, although the scope of the present invention is not limited in this regard. Substrate30may have a vicinal surface prepared by off-cutting the substrate from an ingot. The (100) substrate30may be off cut at an angle between 2 and 8 degrees towards the (110) direction to produce a surface having terraces in one embodiment. In other embodiments, other off cut orientations or a substrate without an off cut may be used. Such a high resistivity substrate may provide for device isolation. Furthermore, off-cutting may eliminate anti-phase domains in anti-phase boundaries.

As shown inFIG. 1, next a nucleation and buffer layer (hereafter nucleation layer)34may be formed on substrate30. In various embodiments, nucleation layer34may be a GaAs layer. Nucleation layer34may be formed via a metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), or another such process. Nucleation layer34may be used to thus fill the lowest silicon substrate terraces with atomic bi-layers of the GaAs material. The nucleation layer portion of nucleation layer34may create an anti-phase domain-free “virtual polar” substrate. In some embodiments, this portion of layer34may be between approximately 30 angstroms (Å)-500 Å. In some embodiments, MBE may be performed at temperatures between approximately 400° Celsius (C.)-500° C. The buffer layer portion of nucleation layer34may provide for gliding dislocation and control of the lattice mismatch of between approximately 4% to 8% between Si and a barrier layer to be formed over nucleation layer34. In some embodiments, the buffer portion of layer34may be formed at a higher temperature than the nucleation portion and may be relatively thicker in some embodiments. Buffer layer34may be between approximately 0.3 microns (μm) and 5.0 μm, in some embodiments.

Referring still toFIG. 1, another buffer layer38may be formed over buffer layer36. In various embodiments, buffer layer38may be an indium aluminium arsenide (InxAl1-xAs) material and may be graded in accordance with an embodiment of the present invention. By forming of a graded buffer layer, dislocations may glide along relatively diagonal planes within the graded buffer layer. Buffer layer38may be between approximately 0.5 and 2.0 microns in some embodiments. Together, nucleation layer34and buffer layer38may form a dislocation filtering buffer. This buffer may provide compressive strain for an InGaAs quantum well (QW) structure. Furthermore, these layers may control lattice mismatch of about approximately 4% to minimize threading dislocations. In some implementations, buffer layer38may be inverse step graded InAlAs or indium gallium aluminium arsenide (InGaAlAs) in order to have a larger bandgap for device isolation. Furthermore, depending upon Al percentage, strain to a quantum well layer to be formed thereon can be modulated. Buffer layer38may further provide for strain relaxation.

A lower barrier layer40may be found on the dislocation filtering buffer. Lower barrier layer40may be formed of a higher bandgap material than a quantum well layer to be formed thereon. Lower barrier layer40may be of sufficient thickness to provide a potential barrier to charge carriers in the transistor stack. In one embodiment, lower barrier layer40may have a thickness of between approximately 100 Å-250 Å. In other embodiments, lower barrier layer may be between approximately 2-5 μm.

Referring still toFIG. 1, a quantum well layer42may be formed over lower barrier layer40. Quantum well layer42may be formed of a material having a smaller bandgap than that of lower barrier layer40. In one embodiment, quantum well layer42may be formed of InxGa1-xAs, where x equals between approximately 0.53-0.8. Quantum well layer42may be of sufficient thickness to provide adequate channel conductance. In some embodiments, quantum well layer42may be between approximately 10-50 nanometers (nm). Quantum well layer42may provide high electron mobility and velocity for NMOS devices, and also may provide high hole mobility and velocity for PMOS devices, both compared to a Si-based device.

As further shown inFIG. 1, a spacer layer44may be formed over quantum well layer42. Spacer layer44may be an InxAl1-xAs or InAlAs spacer layer. Spacer layer44may provide for carrier confinement and reduced interaction between a doping layer and a two dimensional electron gas (2DEG) formed inside the channel (i.e., the channel of quantum well layer42). Still further, spacer layer44may provide compressive strain to the channel. In various embodiments, spacer layer44may be approximately 20 Å to 30 Å thick.

A doping layer may be formed over spacer layer44. Doping layer46may be delta-doped, modulation doped and/or combinations thereof. For example, in one embodiment doping layer46may be a Si modulation delta-doped layer having a thickness of approximately 3 Å-5 Å. For an NMOS device, doping may be implemented using Si and teryllium (Te) impurities. As for a PMOS device, doping may be beryllium (Be) or carbon (C).

Referring still toFIG. 1, an upper barrier layer48may be formed over doping layer46to complete the device stack or layer. In one embodiment, barrier layer48may be an InxAl1-xAs barrier layer. Barrier layer48may have a thickness of between approximately 50 Å-500 Å, and may be a Schottky barrier layer for gate control. An etch stop layer49may be formed over upper barrier layer48, and may be indium phosphide (InP) in some embodiments.

As further shown inFIG. 1, a contact layer52may be present to act as a contact layer to provide source and drain contacts with low contact resistance and may be formed of InxGa1-xAs, in various embodiments. For an NMOS device, contact layer52may be n+doped, while for a PMOS device, contact layer52may be p+doped. Contact layer52may be between approximately 30 Å-300 Å thick.

While not shown inFIG. 1, a fully completed device may further include source and drain electrodes. Furthermore, a dielectric material may be formed on barrier layer48over which a gate electrode may be formed. Note that a gate recess etch may be performed within upper barrier layer48to form a gate recess on which the dielectric layer and gate electrode may be formed. Thus a Schottky junction may be formed through which gate electrode58may control quantum well layer42.

Accordingly, in various embodiments devices may be formed using a high electron mobility material to form high electron mobility transistors (HEMTs) having high speed and low power consumption. Such devices may have dimensions less than approximately 50 nm with a switching frequency of approximately 562 gigahertz (GHz). Such devices may be able to operate at between approximately 0.5-1.0 volts without significant reduction of drive current. Furthermore, embodiments may provide lower gate delay at a gate length than a silicon based device.

Referring now toFIG. 2, shown is a band diagram of a structure in accordance with an embodiment of the present invention. As shown inFIG. 2, the band diagram illustrates, via the top line a conduction band (i.e., EC) and via the lower line a valence band (i.e., EV). Beginning at the right-hand side ofFIG. 2, a Si substrate on which a device stack is formed may have a band gap of approximately 1.1 electron volts (eV). Over the Si substrate, a nucleation and buffer layer may be formed, e.g., of GaAs. As shown, these layers have a higher band gap, e.g., approximately 1.42 eV. Then, a buffer layer and bottom barrier layer may be formed, e.g., of indium aluminium arsenide, to draw a suitable balance between carrier confinement for a channel structure formed in a quantum well layer and relaxation.

Note that three different possible paths, namely paths A, B and C are possible paths of this buffer layer to provide compressive strain to a quantum well layer formed thereon. Path A, which may correspond to a band gap of approximately 1.5 eV, may be obtained by providing buffer and barrier layers having an indium concentration of approximately 52%, namely In0.52Al0.48As. While such layer formation may provide for suitable carrier confinement characteristics, the difference in lattice constants between this type of layer and the underlying substrate may lead to a lattice constant mismatch and thus defects at the interface. Instead, path C shown with a dashed line, which may have relatively poor carrier confinement characteristics, provides a reduced lattice constant mismatch to avoid defects. For path C, a linearly increasing indium concentration from approximately 0% (i.e., AlAs) to approximately 70% indium (i.e., In0.70Al0.30As) may be present. In this case, the In composition in the graded InxAl1-xAs or InGaAlAs buffer is same as the In composition in the InxGa1-xAs channel formed above it, so that the channel is unstrained with respect to bottom barrier. Although the defect is less inside the QW layer, the carrier confinement is poor due to low valence band offset between InxAl1-xAs (e.g., x=0.7) bottom barrier and InxGa1-xAs (e.g., x=0.7) channel as well as not taking the advantage of the strain in the quantum well.

To achieve benefits of both carrier confinement and a relaxation characteristic that provides for a nearly fully relaxed (i.e., metamorphic) structure, path B (shown inFIG. 2as the dotted line) may be implemented. In this implementation, the barrier layer may be formed with an inverse grading with an indium concentration, x, varying from 0% at the interface with the GaAs nucleation and buffer layer up to an amount of x equal to approximately 62% or 63%, and then reducing the x amount back to approximately 52%, as shown in path B. In this way, suitable carrier confinement can be realized while providing a substantially metamorphic profile.

Referring still toFIG. 2over this bottom barrier layer a QW layer may be formed with a relatively small band gap. Specifically, in one embodiment, a QW layer may be formed of indium gallium arsenide with x equal to 0.7 (i.e., In0.7Ga0.3As) such that the band gap is approximately 0.6 eV. To provide further compressive strain to this QW structure, a top barrier may be formed of indium aluminium arsenide having x equal to approximately 52% (i.e., In0.52Al0.48As), corresponding to a band gap of approximately 1.5 eV.

Referring now toFIG. 3, shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown inFIG. 3, method100may begin by forming GaAs nucleation and buffer layers over a Si substrate (block110). Next, InxAl1-xAs buffer and barrier layers may be formed over the GaAs buffer layer (block120). As described above, in some embodiments the buffer layer may be inverse step graded. Together the GaAs and InxAl1-xAs layers may form a dislocation filtering buffer. Next, a QW channel layer, which may be formed of InxGa1-xAs, is formed over the lower barrier layer (block130). Then a spacer layer may be formed over the quantum well (QW) channel layer (block140). Next, a modulation delta-doped layer may be formed (block150). To complete the device stack, an upper barrier layer, formed of InxAl1-xAs, may be formed over the doped layer (block160). Then an InP etch stop layer may be formed (block170), and a contact layer formed of InxGa1-xAs over the etch stop layer (block180). Of course, from this contact layer, source and drains of a device may be formed, and further a gate electrode may be formed on a dielectric layer formed over the contact layer. While shown with this particular implementation in the embodiment ofFIG. 3, the scope of the present invention is not limited in this regard.