MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A magnetic memory device includes a substrate, a spin-orbit torque (SOT) induction structure, and a magnetic tunnel junction (MTJ) stack. The SOT induction structure is disposed over the substrate. The SOT induction structure includes a metal and at least one dopant. The MTJ stack is disposed over the SOT induction structure.

BACKGROUND

A magnetic random access memory (MRAM) offers comparable performance to volatile static random access memory (SRAM) and comparable density with lower power consumption to volatile dynamic random access memory (DRAM). Compared to non-volatile memory (NVM) flash memory, an MRAM offers much faster access times and suffers minimal degradation over time, whereas a flash memory can only be rewritten a limited number of times. One type of an MRAM is a spin transfer torque magnetic random access memory (STT-MRAM). An STT-MRAM utilizes a magnetic tunneling junction (MTJ) written at least in part by a current driven through the MTJ. Another type of an MRAM is a spin orbit torque (SOT) MRAM (SOT-MRAM), which generally requires a lower switching current than an STT-MRAM.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the Figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, there may be one or more additional operations in/between the described operations, and the order of operations may be changed. In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. Materials, configurations, dimensions, processes, and/or operations described with respect to one embodiment may be employed in the other embodiments, and detailed explanation thereof may be omitted.

In an SOT-MRAM, the magnetic moment of the free magnetic layer of an MTJ film stack is switched using the spin-orbit interaction effect generated by a current flowing adjacent to the free magnetic layer of the MTJ film stack. This current can flow in a SOT induction structure. Manipulating the free magnetic layer orientation causes a resistance change of the MTJ film stack, which may be used to record a data value in the cell. The magnetic moment of the free magnetic layer may be switched spin-orbit torque only or with assistant magnetic field. There are three general types of SOT-MRAM, which depend on the orientation relationship between the magnetization of free magnetic layer and the write current flowing through the SOT induction structure. An x-type of SOT-MRAM has a free magnetic layer moment which is parallel to the current through the SOT induction structure and an assistant magnetic field which is orthogonal to the plane of the current flow in the SOT induction structure. A y-type of SOT-MRAM has a free magnetic layer moment which is perpendicular to, but in the same plane as, the direction of the current through the SOT induction structure. A z-type of SOT-MRAM has a free magnetic layer moment which is orthogonal to the plane of the current flow through the SOT induction structure and an assistant magnetic field is needed which is parallel to the current flow.

Although the present disclosure generally relates to an x-type of SOT-MRAM, some of the aspects discussed herein may be transferrable to the other types of SOT-MRAM devices, such as will be discussed below. In x-type of SOT-MRAM devices, the assistant magnetic field to switch the free magnetic layer may be generated externally to the cell, thereby complicating the cell structure. Embodiments of the present disclosure improve performance in several ways.

FIG.1illustrates a schematic view of the SOT-MRAM function elements of a magnetic memory cell MC1according to some embodiments of the present disclosure.FIG.2andFIG.3illustrates intermediate step used in formation of a SOT induction structure10. The elements ofFIG.1may include a bottom electrode5and/or buffer layer7, a SOT induction structure10, and a MTJ film stack100. It should be understood that these layers may include multiple sub-layers comprising different materials, which will be discussed in detail below. The SOT induction structure10serves as a spin-orbit interaction active layer to provide induction influence on the MTJ film stack100. The SOT induction structure10is a perpendicular Hall metal (p-HM) structure and may be alternatively referred to as a p-HM structure10.

The SOT induction structure10may be a metal doped with at least one dopant, i.e., the SOT induction structure10may include a metal and the at least one dopant. With the aid of dopant, it can assist the metal to maintain the desired phase, therefore, the thickness and spin-hall angle (SHA) of SOT induction structure10may be increased, the resistivity may be decreased, while the good thermal stability of magnetic memory device MC1may be maintained (data as shown in Table 1). In some embodiments, the thickness of the SOT induction structure10may be greater than or equal to 5 nm, and the spin-hall angle (SHA) of the SOT induction structure10may be greater than 0.4. In some embodiments, since the thickness may be increased, the MTJ etching recess window can be improved to decrease probability of occurrence of short or other electrical issue, but not limited to.

In some embodiments, the SOT induction structure10may be a doped W (doped tungsten), and the doped W may include Co, Ru, Pt, CoFeB (CFB), Ta, MgO, or combinations thereof, i.e., the SOT induction structure10may include a metal (W) and the at least one dopant (Co, Ru, Pt, CoFeB, Ta, MgO, or combinations thereof). For example, the at least one dopant may include hall metal, magnetic material, insulator, or combinations thereof, the hall metal may include Pt and/or Ta, the magnetic material may include Co and/or CoFeB, and the insulator may include MgO, therefore, the at least one dopant can hold up transformation from β-W to α-W, and the desired phase (β-W) is maintained.

In some embodiments, α-W is the undesired phase, β-W is a metastable structure between amorphous-W and α-W, the dopant may break the α-W texture formation, and may have different crystal structure to slow down or inhibit transformation to α-W, i.e., the desired phase (β-W) may be maintained. In some embodiments, amorphous structure (such as CoFeB), HCP structure (such as Co, Ru) and/or FCC structure (such as Pt) materials are stabilized in β-W phase due to lattice mismatch with α-W (BCC structure). In some embodiments, conductive materials (such as Co, Ru, Pt) may reduce the resistivity of doped W.

In some embodiments, the SOT induction structure10is not a stacked structure, the SOT induction structure10may not include multiple layers, therefore, there is substantially no interface in the SOT induction structure10, and the SOT induction structure10may be a doping state. In some embodiments, different to alloy, a percent of the at least one dopant may be less than 10% of the SOT induction structure10to ensure that the metal (W) maintains the original material property, but not limited to. In some embodiments, low concentration of Co and/or low concentration of CoFeB can boost SHA without too much enhancement in resistivity.

With reference toFIG.2, in some embodiments, the SOT induction structure10may be formed by sputtering a metal material10aand a dopant material10bsimultaneously to form doped state. In some embodiments, the metal material10amay be tungsten (W), and dopant material10bmay be cobalt (Co). With reference toFIG.3, in some embodiments, the SOT induction structure10may be formed by following steps. A plurality of metal material layers10cand a plurality of dopant material layers10dmay be formed, and the plurality of metal material layers10cand the plurality of dopant material layers10dare alternately stacked. The top layer may be metal material layers10c. Next, a heating process is performed, such that the plurality of dopant material layers10dare dispersed into the plurality of metal material layers10cto form doped state (substantially no interface in the SOT induction structure10). In some embodiments, the metal material layer10cmay be required to have a certain thinness to form doped state, i.e., a thickness of each of the metal material layer10cmay be less than or equal to 1.5 nm.

With reference toFIG.1, the MTJ film stack100may also include various configurations. In some embodiments, a free layer30is disposed over the SOT induction structure10, a barrier layer40is disposed over the free layer30, and a reference layer50is disposed over the barrier layer40. In some embodiments, a magnetic coupling tuning spacer layer20(e.g., spacer layer20A and/or spacer layer20B) may be interposed between the SOT induction structure10and the free layer30. Other embodiments may use other arrangements for the MTJ film stack100. For example, in some embodiments, the structure ofFIG.1may be inverted, including all the layers of the MTJ film stack100. As illustrated, the MTJ film stack100includes a pinned layer60and is “top pinned.” In embodiments inverting the structure of the MTJ film stack100, the resulting film stack would be considered “bottom pinned.”

The spacer layer20may be formed from a metal material or a dielectric material, such as a metal oxide. Where the spacer layer20is formed from a metal material, the spacer layer20may be formed of a metal material such as a non-ferromagnetic metal material such as W, Ru, Pt, Mo, Ti, Mg, the like, or combinations thereof. Where the spacer layer20may be formed of a dielectric material such as magnesium oxide (MgOx), cobalt oxide (CoOx), aluminum oxide (AlOx), the like, or combinations thereof. In some embodiments, the spacer layer20may be formed from multiple layers which each may be a different material, including a metal material and/or a dielectric material. In some embodiments, the spacer layer20A may be formed and patterned in conjunction with the SOT induction structure10and may have a similar foot print as the SOT induction structure10. In some embodiments, the spacer layer20B may be patterned when the MTJ film stack100is patterned such that the spacer layer20B may have a similar foot print as the MTJ film stack100. In some embodiments, both the spacer layer20A and the spacer layer20B may be present. In some embodiments, the spacer layer20may be omitted.

The total thickness of the spacer layer20(including spacer layer20A and spacer layer20B) depends on the materials of the free layer30and the SOT induction structure10. Depending on the materials selected for the spacer layer20, the free layer30, and the SOT induction structure10, the spacer layer20may have a total thickness between about 2 Å and about 13 Å. In some embodiments, such as when the spacer layer20is made of a magnesium oxide, the spacer layer20may have a total thickness between about 6.5 Å and about 8.5 Å. In other embodiments, such as when the spacer layer20is made of magnesium, the spacer layer20may have a total thickness between about 10 Å and about 13 Å. In yet other embodiments, such as when the spacer layer20is made of titanium, the spacer layer20may have a total thickness between about 6.5 Å and about 10 Å. In still other embodiments, such as when the spacer layer20is made of tungsten, the spacer layer20may have a total thickness between about 5 Å and about 10 Å.

The free layer30may be formed of one or more ferromagnetic materials, such as cobalt iron boron (CoFeB), cobalt/palladium (CoPd), cobalt iron (CoFe), cobalt iron boron tungsten (CoFeBW), nickel iron (NiFe), Ru, Co, alloys thereof, the like, or combinations thereof. The free layer30may include multiple layers of different materials, such as a layer of Ru between two layers of CoFeB, a layer of Co between two layers of CoFeB, or a layer of Ru and a layer of Co between two layers of CoFeB, though other configurations of layers or materials may be used. In some embodiments, the material of the free layer30includes a crystalline material deposited to have a particular crystalline orientation, such as a (100) orientation. The total thickness of the free layer30may be between about 1 nm and about 4 nm.

In some embodiments, the barrier layer40is formed of one or more materials such as MgO and AlO, the like, or combinations thereof. In some embodiments, the material of the barrier layer40includes a crystalline material deposited to have a particular crystalline orientation, such as a (100) orientation. The material of the barrier layer40may be deposited to have the same crystalline orientation as the free layer30. In some embodiments, the barrier layer40may have a thickness between about 0.3 nm and about 3 nm.

The reference layer50is second magnetic layer of which the magnetic moment does not change. The reference layer50may be made of any of the same materials as the free layer30as set forth above, and may have the same material composition as the free layer30. In some embodiments, the reference layer50includes one or more layers of magnetic materials. In some embodiments, the reference layer50includes a layer of a combination of cobalt (Co), iron (Fe), and boron (B), such as Co, Fe, and B; Fe and B; Co and Fe; Co; and so forth. In some embodiments, the material of the reference layer50includes a crystalline material deposited to have a particular crystalline orientation, such as a (100) orientation. The material of the reference layer50may be deposited to have the same crystalline orientation as the barrier layer40. In some embodiments, a thickness of the reference layer50is in a range from about 0.2 nm to about 8 nm.

The pinned layer60is a hard bias layer used to pin the spin polarization direction of the reference layer50in a fixed direction. Pinning the spin polarization direction of the reference layer50allows the magnetic memory device to be toggled between a low-resistance state and a high-resistance state by changing the spin polarization direction of the free layer30relative to the reference layer50. Because the pinned layer60is formed over the reference layer50, the example MTJ film stack100shown inFIG.1may be considered a “top-pinned” MTJ stack. In some embodiments, however, the order of the layers of the MTJ film stack100may be reversed. In such embodiments, because the reference layer50would be formed over the pinned layer60, such an MTJ film stack may be considered a “bottom-pinned” MTJ stack.

The pinned layer60may include multiple layers of different materials, in some embodiments, and may be referred to as a synthetic anti-ferromagnetic (SAF) layer. For example, the pinned layer60may comprise a stack of one or more ferromagnetic layers and one or more non-ferromagnetic layers. For example, the pinned layer60may be formed from a non-ferromagnetic layer sandwiched between two ferromagnetic layers or may be a stack of alternating non-ferromagnetic layers and ferromagnetic layers. The ferromagnetic layers may be formed of a material such as Co, Fe, Ni, CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, the like, or combinations thereof. The non-ferromagnetic layers may be formed of material such as Cu, Ru, Ir, Pt, W, Ta, Mg, the like, or combinations thereof. In some embodiments, the ferromagnetic layer(s) of the pinned layer60may have a thickness between about 2 nm and about 5 nm. In some embodiments, a thicker pinned layer60may have stronger antiferromagnetic properties, or may be more robust against external magnetic fields or thermal fluctuation. In some embodiments, the non-ferromagnetic layer(s) of the pinned layer60may have a thickness between about 2 Å and about 10 Å. For example, the pinned layer60may include a layer of Ru that has a thickness of about 4 Å or about 8.5 Å, though other layers or thicknesses are possible. In some embodiments, one or more layers of the pinned layer60includes a crystalline material deposited to have a particular crystalline orientation, such as a (111) orientation. The pinned layer60may be formed to have an in-plane magnetic anisotropy (IMA), that is, in the same plane as the horizontal direction of the pinned layer60. In some embodiments, a total thickness of the pinned layer60is in a range from about 3 nm to 25 nm.

In some embodiments, the pinned layer60may include an anti-ferromagnetic material (AFM) layer such as PtMn or IrMn to provide strong exchange bias to fix the pinned layer. This forms a “spin-valve structure” and provides better stability of the pinned layer.

The capping layer70may be a single or multi-layer structure that serves both to protect the layers under the capping layer70during subsequent processes and to provide a top electrode for an overlying via or metal line to connect to. The layer(s) may be formed of a non-ferromagnetic material such as such as Cu, Ru, Ir, Pt, W, Ta, Mg, Ti, TaN, TiN, the like, or combinations thereof. In some embodiments, the capping layer70may include two non-ferromagnetic material layers sandwiching another non-ferromagnetic material layer, such as another one of such as Cu, Ru, Ir, Pt, W, Ta, Mg, Ti, TaN, TiN, or the like. For example, in some embodiments, the capping layer may include Ta or Ti sandwiched between two layers of Ru. The thickness of the capping layer70may be between about 3 nm and about 25 nm, though other thicknesses are contemplated. In embodiments using multiple layers for the capping layer70, each layer may be between about 1 nm and about 12 nm.

A top electrode75may be disposed over the capping layer70. The top electrode75may be used to provide electrical connection to a conductive pattern coupled to the top of the MTJ film stack100. The top electrode75may be formed of any suitable material, such as titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof.

FIG.4is illustrations of a SOT induction structure, in accordance with various embodiments. InFIG.4, SOT induction structure10may further include a spacer layer12interposed in the SOT induction structure10, and the SOT induction structure10may be separated in a plurality of portions10e, therefore, the spacer layer12and portions10emay be alternately stacked. In some embodiments, the spacer layer comprises MgO or MgO/CoFeB.

In some embodiments, the aforementioned structure may be formed in the SOT induction structure10by following steps. The steps ofFIG.3is performed, and when the first portion10eof the SOT induction structure10is achieved a certain thickness, the first portion10eof the SOT induction structure10may be removed from a processing chamber (not shown), and then the spacer layer12may be formed on the first portion10eof the SOT induction structure10. Next, the spacer layer12formed on the first portion10eof the SOT induction structure10may be move in the processing chamber again, and the second portion10eof the SOT induction structure10may be formed on the spacer layer12. Repeat the above steps until the SOT induction structure10is made, but not limited to. As noted above, the composition of each portion10eis similar to SOT induction structure10previously described.

FIGS.5through14illustrate intermediate steps in the formation of the magnetic memory device300(such as SOT-MRAM device). The materials and formation method used to form the various structures and elements of the magnetic memory device300are described above and are not repeated.

FIG.5illustrates a cross-sectional view of a substrate102and multiple FETs110formed on the substrate102, in accordance with some embodiments. The FETs110are part of the subsequently formed magnetic memory cell MC1(SOT-MRAM cells) of the magnetic memory device300. Some example FETs110are indicated inFIG.5. The substrate102may be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

In some embodiments, the FETs110are Fin Field-Effect Transistors (FinFETs) comprising fins116, gate structures114, and source regions112S and drain regions112D. As shown inFIG.5, the fins116are formed on the substrate102and may comprise the same material as the substrate102or a different material. In some embodiments, dummy fins (not shown) may be formed between some fins116to improve process uniformity. The gate structures114are formed over multiple fins116and extend in a direction perpendicular to the fins116. In some embodiments, spacers (not shown in the Figures) may be disposed on the sidewalls of the gate structures114. In some embodiments, dummy gate structures121may be formed between some gate structures114to improve process uniformity. The dummy gate structures121may be considered “dummy transistors” or “dummy FinFETs,” in some embodiments. Some gate structures114are used as Word Lines in the SOT-MRAM device300(described in greater detail below), and have been labeled as “WL,” such as “WL2,” accordingly. The source regions112S and the drain regions112D are formed in the fins116on either side of the gate structures114. The source regions112S and the drain regions112D may be, for example, implanted regions of the fins116or epitaxial material grown in recesses formed in the fins116. In the embodiment shown inFIG.5, one side of each fin116is adjacent source regions112S and the other side of each fin116is adjacent drain regions112D.

The FETs110shown in the Figures are representative, and some features of the FETs110may have been omitted from the Figures for clarity. In other embodiments, the arrangement, configuration, sizes, or shapes of features such as fins116, dummy fins, gate structures114, dummy gate structures21, source regions112S, drain regions112D, or other features may be different than shown. In other embodiments, the FETs110may be another type of transistor, such as planar transistors.

InFIG.6, a dielectric layer104is formed over the substrate102and patterned to expose the source regions112S and drain regions112D, in accordance with some embodiments. The dielectric layer104may cover the FETs110, and may be considered an Inter-Layer Dielectric layer (ILD) in some embodiments. The dielectric layer104may be formed of any suitable dielectric material including, for example, any of the materials listed above for an ILD. The dielectric layer104may be formed using any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof. In some embodiments, the dielectric layer104may be a low-k dielectric material, such as a dielectric material having a dielectric constant (k value) lower than about 3.0, for example.

The dielectric layer104may be patterned to form openings106that expose the source regions112S and the drain regions112D for subsequent formation of contact plugs118(seeFIG.7). The dielectric layer104may be patterned using a suitable photolithography and etching process. For example, a photoresist structure (not shown) may be formed over the dielectric layer104and patterned. The openings106may be formed by etching the dielectric layer104using the patterned photoresist structure as an etching mask. The dielectric layer104may be etching using a suitable anisotropic etching process, such as a wet etching process or a dry etching process.

Turning toFIG.7, contact plugs118are formed to make electrical connection to the source regions112S and the drain regions112D, in accordance with some embodiments. In some embodiments, the contact plugs118are formed by depositing a barrier layer (not individually shown) extending into the openings106, depositing a conductive material over the barrier layer, and performing a planarization process such as a Chemical Mechanical Polish (CMP) process or a grinding process to remove excess portions of the blanket conductive barrier layer and the conductive material. The barrier layer or the conductive material of the contact plugs118may be formed using a suitable process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), plating, or the like. The barrier layer, if used, may be formed of any suitable material, such as TiN, Ti, TaN, Ta, the like, or combinations thereof.

Turning toFIG.8, conductive lines130A are formed to electrically connect the contact plugs118and provide electrical routing within the SOT-MRAM device. The conductive lines130A may be formed within a dielectric layer128A that is formed over the dielectric layer104. The dielectric layer128A may be a material similar to those described above for dielectric layer104(seeFIG.6), and may be deposited using similar techniques as dielectric layer104. The dielectric layer128A may be considered an Inter-Metal Dielectric layer (IMD) in some embodiments.

The conductive lines130A may be formed using a suitable technique such as damascene, dual-damascene, plating, deposition, the like, or combinations thereof. In some embodiments, the conductive lines130A are formed by first depositing the dielectric layer128A and patterning the dielectric layer128A to form openings (e.g., using a suitable photolithography and etching process), and then filling the openings in the dielectric layer128A with conductive material. For example, the conductive lines130A may be formed by depositing an optional blanket barrier layer (not individually shown) over the patterned dielectric layer128A, depositing a conductive material over the blanket barrier layer, and performing a planarization process such as a CMP process or a grinding process to remove excess portions of the blanket conductive barrier layer and the conductive material. The barrier layer or the conductive material may be similar to those described above for the contact plugs118(seeFIG.7), and may be deposited using similar techniques. In some embodiments, the conductive material of the contact plugs118and the conductive lines130A may be deposited in the same step, for example, if a dual-damascene process is used to form the contact plugs118and the conductive lines130A.

In some embodiments, the conductive lines130A are formed by first depositing the optional blanket barrier layer over the dielectric layer104and contact plugs118, depositing a conductive material over the blanket barrier layer, and then patterning the barrier layer and conductive material (e.g., using a suitable photolithography and etching process) to form the conductive lines130A. The dielectric layer128A may be deposited over the conductive lines130A and a planarization process performed to expose the conductive lines130A.

InFIG.9, vias126A are formed within a dielectric layer124A to make electrical connection to the conductive lines130A, in accordance with some embodiments. In some embodiments, the dielectric layer124A is first formed over the conductive lines130A and the dielectric layer128A. The dielectric layer124A may be a material similar to those described above for the dielectric layer104and the vias126A may be formed using processes and materials similar to those described above with regard to the contact plugs118. The process of forming conductive lines and vias are repeated to form a desired number of metal wiring layers.

In some embodiments, the vias126A formed under the SOT induction structure10may be formed using a single damascene process from copper, tungsten, or titanium nitride and can function as bottom electrode5(seeFIG.1) for the SOT induction structure10. An optional barrier layer may also be used, as discussed above with respect to the contact plugs118to prevent diffusion of the material of the contact plugs118to the surrounding dielectric layer124A.

As illustrated inFIG.9, after forming the vias126A, the SOT induction structure10may be formed over the substrate102. As noted above, in some embodiments, the vias126A may serve as the bottom electrode5. In some embodiments, the buffer layer7may be formed over the vias126A separately or along with deposition of SOT induction structure10using any suitable process. In embodiments utilizing a buffer layer, the buffer layer may include magnesium oxide or the like deposited to a thickness between about 0.2 and 0.9 nm. The bottom electrode5may be formed using the techniques discussed above with respect to the formation of the conductive lines130A.

After forming the buffer layer7(if used), the SOT induction structure10film stack may be deposited. The SOT induction structure10is formed using processes and materials such as those discussed above with respect toFIGS.2and3. The spacer layer20is deposited over the SOT induction structure10using processes and materials such as those discussed above. In some embodiments, after the spacer layer20is deposited, the MTJ film stack100is deposited sequentially.

InFIG.10, the MTJ film stack100may be deposited in sequential layers, such as indicated with respect toFIG.1. Layers for the MTJ film stack100are formed over the SOT induction structure10, including the free layer30, the barrier layer40, the reference layer50, the pinned layer60, the capping layer70. In some embodiments the top electrode75(seeFIG.1) is then deposited, while in other embodiments the hard mask101(seeFIG.11B) may function as the top electrode. In some embodiments a spacer layer20may be formed as a first layer under the free layer30. Each of the layers of the MTJ film stack100can be formed by suitable film formation methods which can provide capability of precise thickness control. Such methods may include, for example, physical vapor deposition (PVD) sputtering. Other methods may include: molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam (e-beam) epitaxy; or any combinations thereof. It may be possible to use chemical vapor deposition (CVD) or its derivatives if thickness deposition can be precisely controlled.

Following deposition of the MTJ film stack100layers an anneal may be performed. If a first anneal after formation of the SOT induction structure10is performed, then in some embodiments, a second anneal after deposition of the MTJ film stack100may be performed in the presence of a horizontal magnetic field, for setting the in-plane crystal anisotropy of AFM layer. If a first anneal after formation of the SOT induction structure10is not performed, then the first anneal after deposition of the MTJ film stack100may be performed in the presence of a perpendicular magnetic field to enhance the PMA of the SOT induction structure10. Then a second anneal may also be performed in the presence of a horizontal magnetic field to set the AFM layer.

FIGS.11A,11B,11C,11Dillustrate various views in a process of patterning the MTJ film stack100to form an MTJ pillar and patterning the SOT induction structure10film stack to form the SOT induction structure10. InFIG.11A, a hard mask layer101is deposited over the MTJ film stack100layers. The hard mask layer101may be deposited using any suitable process and may be made of any suitable material, such as silicon nitride, or a conductive metal layer, such as tantalum, tungsten, titanium nitride, the like, or combinations thereof, such as a first layer of a conductive metal and a second layer of a dielectric, such as silicon nitride. In embodiments where the hard mask layer101includes a metal, the hard mask layer101may also function as the top electrode75(FIG.1) over the MTJ film stack100. The hard mask layer101is patterned by using one or more lithography and etching operations, as shown inFIG.11B.

InFIG.11C, the hard mask layer101is used as a mask to pattern the various films of the MTJ film stack100. In some embodiments, the spacer layer20may be patterned with the MTJ film stack100, such as illustrated inFIG.11C(and the left hand side ofFIG.12), while in other embodiments, the spacer layer20may be patterned with the SOT induction structure10film stack, such as illustrated inFIG.11E(and the right hand side ofFIG.12). Other embodiments may pattern the spacer layer20into a first and second spacer layer20A and20B, such as illustrated inFIG.1. In some embodiments, as shown inFIG.11C, the cross-sectional view of the MTJ film stack100has a tapered (mesa) shape. In some embodiments, the hard mask layer101or a dielectric portion of the hard mask layer101may be consumed in the patterning of the MTJ film stack100. The remaining metal portion of the hard mask layer101may act as the top electrode75(hereafter labeled as top electrode75).

InFIG.11D, a dielectric protection layer103is blanket deposited using any suitable deposition technique, such as PVD, CVD, ALD, the like, or combinations thereof. The dielectric protection layer103is deposited over the SOT induction structure10films and the patterned MTJ film stack100, and may be formed of any suitable material such as silicon nitride, silicon carbide, the like, or combinations thereof.

InFIG.11E, the SOT induction structure10film stack is patterned to form the SOT induction structure10using suitable photolithography and etching techniques. Where the optional buffer layer7is used, it is also patterned along with the SOT induction structure10film stack to have the same shape in top view.FIG.11Ealso shows an embodiment where the spacer layer20is not patterned as part of the MTJ film stack100, but rather as part of the SOT induction structure10film stack. As noted above, the spacer layer20may include a portion patterned as part of the MTJ film stack100and a portion patterned as part of the spacer layer20, such as illustrated inFIG.1.

InFIG.12, after patterning the MTJ film stack100and the SOT induction structure10, one or more dielectric material layers, e.g., ILD124B, including any of the ILD candidate materials described above, are deposited to fully cover the MTJ film stack100. A planarization operation, such as CMP, may be performed to level the upper surface of the ILD124B. In some embodiments, the CMP will have a floating stop in the ILD124B, such as illustrated inFIG.12. In other embodiments, the CMP may stop on the protective dielectric layer103. As noted above, the left hand side MTJ film stack100, spacer layer20, and SOT induction structure10are patterned so that the spacer layer20is patterned with the MTJ film stack100and has the same shape as the MTJ film stack100. The right hand side MTJ film stack100, spacer layer20, and SOT induction structure10are patterned so that the spacer layer20is patterned with the SOT induction structure10and has the same shape as the SOT induction structure10. This embodiment view is omitted in subsequent Figures. A combination of the two may also be utilized, in accordance with some embodiments.

InFIG.13, after forming the MTJ film stacks100and depositing the ILD124B and performing a CMP, vias126B may be formed through the ILD124B and protective dielectric layer103to contact the top electrode75over the MTJ film stack100. Vias126B may be formed using processes and materials similar to those used to form vias126A. For example, vias126B may be formed using a damascene process where a mask is used to pattern openings in the ILD124B and etch the dielectric protective layer103, and an optional diffusion barrier layer is deposited in the openings followed by conductive plug material, followed by a CMP.

InFIG.14, conductive lines130C are formed to electrically connect the vias126B and provide electrical routing within the SOT-MRAM device300to the bit lines160. The conductive lines130C may be formed within a dielectric layer128C that is formed over the ILD124B. The dielectric layer128C may be a material similar to those described above for dielectric layer104, and may be deposited using similar techniques as dielectric layer104. The dielectric layer128C may be considered an Inter-Metal Dielectric layer (IMD) in some embodiments.

FIG.15illustrates a three-dimensional view of MC1of the magnetic memory device300ofFIG.14, in accordance with some embodiments. Materials, configurations, dimensions, processes, and/or operations described with respect toFIG.1throughFIG.14may be employed in the following embodiments, and detailed explanation thereof may be omitted.

In some embodiments, a word line120(coupled to a gate of FET110) extends in the Y-direction and the source lines125SL1and SL2extend in the X-direction. The SOT induction structure10is located above the source or drain regions of two adjacent FETs110and is coupled at either end to the respective source or drain regions of the two adjacent FETs110by vias and metal wiring layers. The SOT induction structure10may have a direction which is predominantly in the X-direction, in some embodiments.

As shown inFIG.15, the MTJ film stack100is disposed over SOT induction structure10with a spacer layer20interposed between the MTJ film stack100and the SOT induction structure10, in some embodiments. The MTJ film stack100may have a rounded pillar (type Z) or cylinder in ellipse shape (type X and Y), which may taper as illustrated in other Figures. The bit line160is electrically coupled to the top of the MTJ film stack100by a via and/or top electrode of the MTJ film stack and may extend in the X-direction.

In the present disclosure, the SOT induction structure10may be a metal doped with at least one dopant, therefore, with the aid of dopant, it can assist the metal to maintain the desired phase, therefore, the thickness and spin-hall angle (SHA) of SOT induction structure10may be increased, the resistivity may be decreased, while the good thermal stability of magnetic memory device MC1may be maintained.

In accordance with some embodiments of the present disclosure, a magnetic memory device includes a substrate, a spin-orbit torque (SOT) induction structure, and a magnetic tunnel junction (MTJ) stack. The SOT induction structure is disposed over the substrate. The SOT induction structure includes a metal and at least one dopant. The MTJ stack is disposed over the SOT induction structure. In an embodiment, the metal may include W, and the at least one dopant may include Co, Ru, Pt, CoFeB, Ta, MgO, or combinations thereof. In an embodiment, a thickness of the SOT induction structure may be greater than or equal to 5 nm. In an embodiment, a spin-hall angle (SHA) of the SOT induction structure may be greater than 0.4. In an embodiment, a magnetic memory device may further include a spacer layer interposed in the SOT induction structure, and the SOT induction structure is separated in a plurality of portion. In an embodiment, the spacer layer may include MgO or MgO/CoFeB.

In accordance with some embodiments of the present disclosure, a magnetic memory device includes a substrate, a spin-orbit torque (SOT) induction structure, and a magnetic tunnel junction (MTJ) stack. The SOT induction structure is disposed over the substrate. The SOT induction structure includes doped W. The MTJ stack is disposed over the SOT induction structure. In an embodiment, the doped W may include hall metal, magnetic material, insulator, or combinations thereof. In an embodiment, the doped W may include Co, Ru, Pt, CoFeB, Ta, MgO, or combinations thereof. In an embodiment, a thickness of the SOT induction structure may be greater than or equal to 5 nm. In an embodiment, a spin-hall angle (SHA) of the SOT induction structure may be greater than 0.4. In an embodiment, a magnetic memory device may further include a spacer layer interposed in the SOT induction structure, and the SOT induction structure is separated in a plurality of portion. In an embodiment, the spacer layer may include MgO or MgO/CoFeB.

In accordance with some embodiments of the present disclosure, a method including providing a substrate, forming a spin-orbit torque (SOT) induction structure over the substrate, wherein the SOT induction structure comprises metal doped with at least one dopant, and forming a magnetic tunnel junction (MTJ) stack over the SOT induction structure. In an embodiment, the SOT induction structure may be formed by sputtering a metal material and a dopant material simultaneously to form doped state. In an embodiment, the SOT induction structure may be formed by: forming a plurality of metal material layers and a plurality of dopant material layers, wherein the plurality of metal material layers and the plurality of dopant material layers are alternately stacked; and performing a heating process, such that the plurality of dopant material layers are dispersed into the plurality of metal material layers to form doped state. In an embodiment, a top layer in alternately stacked layers is the metal material layer. In an embodiment, a thickness of each of the metal material layer may be less than or equal to 1.5 nm. In an embodiment, the metal comprises W, and the at least one dopant comprises Co, Ru, Pt, CoFeB, Ta, MgO, or combinations thereof. In an embodiment, a method may further include: forming a spacer layer in the SOT induction structure.