UV LIGHT EMITTING DIODE

A UV light emitting diode includes a substrate having a plurality of holes surrounded by a flat surface, a first conductivity type semiconductor layer disposed on the substrate, a second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A distance from the flat surface to the active layer is smaller than a distance from bottom surfaces of the plurality of holes to the active layer. The flat surface is in contact with the first conductivity type semiconductor layer.

TECHNICAL FIELD

The present disclosure relates to an inorganic semiconductor light emitting diode, and more particularly, to a light emitting diode emitting UV light of 300 nm or less.

BACKGROUND ART

In general, a light emitting diode emitting UV light within a range of 200 nm to 300 nm can be used in various applications, including a sterilization device, a water or air purification device, a high-density optical recording device, and an excitation source for a bio-aerosol fluorescence detection system.

Unlike a near-UV light emitting diode or a blue light emitting diode, a light emitting diode that emits relatively more UV light includes a well layer containing Al, such as AlGaN. Due to a composition of this gallium nitride-based semiconductor layer, a UV light emitting diode has a structure significantly different from that of the blue light emitting diode.

In particular, for the blue light emitting diode, a patterned sapphire substrate is generally used as a growth substrate. A light extraction efficiency of the light emitting diode may be increased by a pattern formed on the sapphire substrate. However, in a case of the UV light emitting diode, it is necessary to grow a semiconductor layer having a high Al content, such as AlGaN, which does not grow with a good crystal quality on a conventional patterned sapphire substrate, unlike the semiconductor layer used in the blue light emitting diode.

Accordingly, the conventional UV light emitting diode has been generally manufactured using a sapphire substrate having a flat growth surface, and thus, there is a limit in increasing the light extraction efficiency. Moreover, the conventional UV light emitting diode does not have a favorable crystal quality, and thus, a performance thereof is easily deteriorated with prolonged use.

DETAILED DESCRIPTION OF THE DISCLOSURE

Technical Problem

Exemplary embodiments of the present disclosure provide a UV light emitting diode with an improved light extraction efficiency.

Exemplary embodiments of the present disclosure provide a UV light emitting diode with a decreased performance degradation even it is used for a long time.

Technical Solution

A UV light emitting diode according to an exemplary embodiment of the present disclosure includes: a substrate having a plurality of holes surrounded by a flat surface; a first conductivity type semiconductor layer disposed on the substrate; a second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer; an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, in which a distance from the flat surface to the active layer is smaller than a distance from bottom surfaces of the plurality of holes to the active layer, and the flat surface is in contact with the first conductivity type semiconductor layer.

Diameters of inlets of the holes may be less than 1 μm, and diameters of the bottom surfaces of the holes may be 500 nm or less.

The diameters of the inlets of the holes may be in a range of 500 nm to 700 nm.

Furthermore, a distance between centers of adjacent holes may be 1 μm or more and 3 μm or less.

In an exemplary embodiment, the holes may be arranged in a honeycomb shape.

The first conductivity type semiconductor layer may include a plurality of cavities therein, and the plurality of cavities may be disposed on the holes, corresponding to the holes.

Furthermore, the first conductivity type semiconductor layer may include an AlN layer, and the cavities may be formed in the AlN layer.

The UV light emitting diode may further include: an n-ohmic contact layer contacting the first conductivity type semiconductor layer; a p-ohmic contact layer contacting the second conductivity type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layer; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer, in which the p-pad metal layer may be formed so as to surround the n-pad metal layer.

The n-bump and the p-bump are disposed in a region over the second conductivity type semiconductor layer.

The UV light emitting diode may further include a lower insulation layer covering the p-ohmic contact layer and the n-ohmic contact layer, in which the lower insulation layer may have openings exposing the p-ohmic contact layer and the n-ohmic contact layer, and the n-pad metal layer and the p-pad metal layer may be electrically connected to the n-ohmic contact layer and the p-ohmic contact layer through the openings of the lower insulation layer, respectively.

The UV light emitting diode may further include an upper insulation layer covering the n and p-pad metal layers, in which the upper insulation layer may have openings exposing the n-pad metal layer and the p-pad metal layer, wherein the n-bump and the p-bump may be disposed on the upper insulation layer, and may be electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulation layer.

In the UV light emitting diode according to an exemplary embodiment of the present disclosure, a peak wavelength of an emission spectrum is 280 nm or less, and after driving at room temperature for 1000 hours, a light output is 85% or more compared to an initial light output.

In some exemplary embodiments, the light output of the UV light emitting diode after driving at room temperature for 1000 hours may be greater than or equal to 90% of the initial light output.

The UV light emitting diode may include: a substrate; a first conductivity type semiconductor layer disposed on the substrate; an active layer disposed on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer disposed on the active layer; an n-ohmic contact layer contacting the first conductivity type semiconductor layer; a p-ohmic contact layer contacting the second conductivity type semiconductor layer; an n-bump electrically connected to the n-ohmic contact layer; and a p-bump electrically connected to the p-ohmic contact layer, in which the substrate may have a hole pattern.

Furthermore, the first conductivity type semiconductor layer may include an AlN layer, and the AlN layer may have a plurality of cavities therein. The plurality of cavities may be disposed on the holes corresponding to the holes of the hole pattern.

A portion of the cavities may be disposed in the holes.

The second conductivity type semiconductor layer may include a p-type GaN layer, in which the p-type GaN layer may have a thickness of 50 nm or less, and the p-ohmic contact layer may be in-ohmic contact with the p-type GaN layer.

The UV light emitting diode may further include an upper insulation layer covering the n-pad metal layer and the p-pad metal layer, in which the upper insulation layer may have openings exposing the n-pad metal layer and the p-pad metal layer, and the n-bump and the p-bump may be electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulation layer, respectively.

In addition, the upper insulation layer may cover side surfaces of the second conductivity type semiconductor layer and the active layer.

The opening exposing the n-pad metal layer may be disposed near one edge of a mesa, and the opening exposing the p-pad metal layer may be disposed near an opposite edge of the mesa.

Advantageous Effects

According to exemplary embodiments of the present disclosure, it is possible to provide a UV light emitting diode with improved light output and reliability by making a distance from a flat surface of a substrate to an active layer smaller than a distance from bottom surfaces of a plurality of holes to the active layer. In addition, it is possible to provide a UV light emitting diode with improved light output and reliability using holes having a size of 1 μm or less.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. The following exemplary embodiments are provided by way of example so as to fully convey the spirit of the present disclosure to those skilled in the art to which the present disclosure pertains. Accordingly, the present disclosure should not be limited to the specific disclosed forms, and be construed to include all modifications, equivalents, or replacements included in the spirit and scope of the present disclosure. In the drawings, widths, lengths, thicknesses, and the like of elements can be exaggerated for clarity and descriptive purposes. When an element or layer is referred to as being “disposed above” or “disposed on” another element or layer, it can be directly “disposed above” or “disposed on” the other element or layer or intervening elements or layers can be present. Throughout the specification, like reference numerals denote like elements having the same or similar functions.

Nitride-based semiconductor layers described below may be grown using generally known various methods, and may be grown using technology, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydration vapor phase epitaxy (HVPE), or the like. However, in exemplary embodiments described below, it is described that semiconductor layers are grown in a growth chamber using MOCVD. In a process of growing the nitride-based semiconductor layers, sources introduced into the growth chamber may be generally known sources, for example, TMGa, TEGa, or the like may be used as a Ga source, TMAl, TEAl, or the like may be used as an Al source, TMIn, TEIn, or the like may be used as an In source, and NH3may be used as a N source. However, the inventive concepts are not limited thereto.

FIG. 1Ais a schematic plan view illustrating a UV light emitting diode100according to an exemplary embodiment of the present disclosure, andFIG. 1Bis a schematic cross-sectional view taken along line A-A′ of its corresponding plan view shown inFIG. 1A. Meanwhile,FIG. 2Ais a schematic plan view illustrating a hole pattern formed on a substrate,FIG. 2Bis a planar SEM image showing the hole pattern formed on the substrate, according to an exemplary embodiment, andFIG. 2Cis a cross-sectional SEM image showing the hole pattern formed on the substrate, according to an exemplary embodiment. In addition,FIG. 3Ais a schematic cross-sectional view illustrating a first conductivity type semiconductor layer formed on the substrate,FIG. 3Bis a cross-sectional TEM image showing the first conductivity type semiconductor layer formed on the substrate according to an exemplary embodiment of the present disclosure, andFIG. 3Cis a cross-sectional TEM image showing a first conductivity type semiconductor layer formed on the substrate according to another exemplary embodiment of the present disclosure.

Referring toFIG. 1AandFIG. 1B, the UV light emitting diode100according to the illustrated exemplary embodiment may include a substrate21, a first conductivity type semiconductor layer23, an active layer25, a second conductivity type semiconductor layer27, an n-ohmic contact layer31, a p-ohmic contact layer33, a lower insulation layer35, an n-pad metal layer37a, a p-pad metal layer37b, an upper insulation layer39, an n-bump41a, and a p-bump41b.

The substrate21is not particularly limited as long as it is a substrate capable of growing a nitride-based semiconductor, and may include, for example, a heterogeneous substrate such as a sapphire substrate, a silicon substrate, a silicon carbide substrate, a spinel substrate, or the like. In particular, the substrate21may be a sapphire substrate.

The substrate21is relatively thick compared to a substrate used in a blue light emitting diode, and for example, it may have a thickness of 200 μm or more, furthermore, 400 μm or more. An upper limit of the thickness of the substrate21is not particularly limited, but may be, for example, 800 μm or less. By using the relatively thick substrate21, an amount of ultraviolet rays emitted to the outside may be increased.

As shown inFIG. 1B, the substrate21may have a hole pattern including a plurality of holes21aformed on a flat surface21b. The flat surface21bprovides a growth site for a nitride semiconductor layer.

The hole pattern of the illustrated exemplary embodiment is different in size from a pattern on a sapphire substrate patterned according to a prior art. The pattern according to the prior art includes a bottom surface and a protrusion, in which the bottom surface provides a main growth site, and a growth layer is merged on the protrusion. In contrast, in the illustrated exemplary embodiment, in the nitride semiconductor layer, the flat surface21bprovides a main growth site, and a growth layer is merged on the holes21a.

As shown inFIG. 2A, the holes21aare spaced apart from one another, and the flat surface21bis interposed between the holes21a. A minimum width of the flat surface21binterposed between the holes21amay be 100 nm or more, further, 200 nm or more. The holes21amay be arranged, for example, in a honeycomb shape, without being limited thereto. In addition, distances L1, L2, and L3between adjacent holes21amay be identical in any direction, but the inventive concepts are not limited thereto. For example, L1may be smaller compared to L2and L3. A minimum distance L1between centers of the adjacent holes21amay be 1 μm or more, and may be 3 μm or less. When the distance between the centers of the holes21ais less than 1 it is difficult to grow the nitride semiconductor layer, and when it exceeds 3 μm, an effect of introducing the hole pattern is lowered, which is not preferable.

The hole21amay include an inclined surface and a bottom surface. As shown inFIG. 2, the bottom surface of the hole21amay be formed to have a diameter D1, and an inlet of the hole21amay be formed to have a diameter D2. A region between the diameters D1and D2is an inclined surface, and growth of the nitride semiconductor layer on the inclined surface is limited. Meanwhile, the diameter D1of the bottom surface of the hole21amay have a size of 500 nm or less, and further may have a size of 400 nm or less. For example, the diameter D1of the bottom surface of the hole21amay be about 300 nm to about 400 nm. However, the inventive concepts are not limited thereto, and there may be no flat bottom surface. That is, the diameter D1may be 0 nm. The diameter D2may be less than 1 and further may be 700 nm or less. For example, the diameter D2may be in a range of about 500 nm to about 700 nm. The inclined surface may be formed as a curved surface, and may be a convex curved surface or a concave curved surface in a direction of a central axis of the hole21a. In addition, the inclined surface may be disposed between the flat surface21bof the substrate and a light exiting surface that is disposed opposite to the flat surface21band emits light to the outside. However, the present disclosure is not limited to a specific shape of the inclined surface.

By limiting the size of the hole21ato 1 μm or less, a crystal layer grown on the flat surface21bmay be merged over the holes21a. The crystal layer may also be grown on the bottom surface of the hole21a, but this layer is limited in the hole21a. Accordingly, as shown inFIG. 3A, cavities23h1and23h2may be formed over the holes21a.

The patterned sapphire substrate of the prior art includes protrusions spaced apart from one another in an island type, and has a structure in which the protrusions are surrounded by concave portions. In a case of a blue light emitting diode, semiconductor layers can be grown using the concave portions as a growth surface, but in a case of a deep UV light emitting diode, in a conventional patterned sapphire substrate, the crystal layers do not grow well in the concave portion and the crystal layers are not merged well, and thus, many defects such as high density dislocations in the grown nitride semiconductor layers remain.

On the contrary, according to the illustrated exemplary embodiment, by forming the holes21ahaving a small size of less than 1 μm on the upper surface of the substrate21and using the flat surface21bas the growth surface, it is possible to grow the nitride semiconductor layer for the UV light emitting diode, and to achieve the merge of the crystal layers. Accordingly, the UV light emitting diode may be manufactured using the nitride semiconductor layer having favorable crystal quality. Furthermore, a light extraction efficiency may be improved by using the hole pattern formed on the substrate21.

In addition, a height level of the flat surface21bused as the growth surface in the present disclosure is higher than that of a flat surface used as the growth surface in the conventional patterned sapphire substrate. In the present disclosure, since it is not necessary to completely fill the hole, a semiconductor layer having a high Al content may be easily formed, and it is effective to form the semiconductor layer for the UV light emitting diode with an improved crystallinity. In particular, even when the Al content is high, crystal growth is preferentially achieved on the flat surface, thereby improving the crystallinity, and thus, a reduction rate of luminous intensity may be decreased even when the light emitting diode is driven for a long time.

In addition, in the patterned sapphire substrate of the prior art, there is a high possibility that light generated from an active layer is first incident on a surface of the protrusion, and scattering and re-incident into the semiconductor layer due to the curved surface of the protrusion, and thus, the light extraction efficiency may be reduced. However, in a structure of the present disclosure, since there is a high possibility that light generated from the active layer is incident on the flat surface rather than the curved surface of the hole, scattering of light is reduced by the flat surface and the possibility of light entering the inside of the substrate increases, and thus, the light extraction efficiency is increased. Accordingly, as a thickness of the substrate increases in the UV light emitting diode, an amount of light entering the substrate increases, and thus, the luminous intensity may be improved.

In addition, the substrate21may have a width (a), a length (b), and a thickness (h), and a luminous density of UV light emitted through the substrate21may be increased. A value of the luminous density may be defined as a luminous density (mW/mm2·mA)=luminous intensity (mW)/(emission area (mm)2×current (mA)), in which the emission area (mm2) may be defined as (ab)+2h·(a+b). Therefore, in a case of a UV light emitting diode having a width of 0.95 mm, a length of 0.6 mm, and a thickness of 0.4 mm, the luminous density (mW/mm2·mA) may be 0.083 or more.

The first conductivity type semiconductor layer23is disposed on the substrate21. The first conductivity type semiconductor layer23may include, for example, a buffer layer (23aofFIG. 3A) and an n-type AlGaN layer (23bofFIG. 3A). The buffer layer23amay have a thickness of 2 μm or more, may have a thickness of about 5 μm or less, and an AlN material may be used. In an exemplary embodiment, a first AlGaN layer may include a lower n-type AlGaN layer (about 2.15 μm) with an Al molar ratio of 0.8 or more, an intermediate AlGaN layer (1.7 nm) with an Al molar ratio of 0.7 to 0.8, and an upper n-type AlGaN layer with a thickness of about 66.5 nm. The first conductivity type semiconductor layer23is formed of a nitride-based semiconductor having a band gap higher than that of the active layer such that light generated in the active layer passes therethrough. When the gallium nitride-based semiconductor layer is grown on the sapphire substrate21, the first conductivity type semiconductor layer23may generally include a plurality of layers so as to improve a crystal quality.

According to the illustrated exemplary embodiments, as shown inFIG. 3A, the cavities23h1and23h2may be formed over the holes21a. As shown inFIG. 3BandFIG. 3C, cavities23h1and23h2having various shapes may be formed according to growth conditions of the buffer layer23a, for example, various combinations of two-dimensional growth and three-dimensional growth. The cavities23h1and23h2are disposed inside the buffer layer23a, and an upper surface of the buffer layer23aprovides a flat growth surface. A first AlGaN layer23bmay be grown on the flat growth surface of the buffer layer23a.

In cross-section view, the cavity may be disposed in a region between the flat surface21band the flat surface, and may be formed at a location vertically overlapped with a region of the hole21a. A width of the cavity may not be greater than a width of the hole21a. Since the cavity does not extend to the flat surface21b, a bonding strength between the flat surface21band the buffer layer23ais maintained, and thus, it is possible to prevent the substrate21from being separated from the semiconductor layer in a process of forming a light emitting device by placing electrodes or others, thereafter.

The cavity includes a lower cavity23h1and an upper cavity23h2, in which both the lower cavity and the upper cavity may be disposed in a region that is vertically overlapped with the region of the hole21a, or at least one of the two may be disposed. When forming an imaginary line connecting the flat surfaces21b, the lower cavity23h1may be disposed so as to be overlapped with the imaginary line. That is, a portion of the lower cavity23h1may be disposed in the hole21a. Also, when a plurality of lower cavities23h1is formed, the plurality of lower cavities23h1may be linearly disposed on the imaginary line. An inner region of the lower cavity23h1has a different refractive index from those of the semiconductor layers, for example, the buffer layer23aand the substrate21, and since the lower cavity23h1is disposed on a same line as the flat surface21b, light proceeding generally parallel to the flat surface21bmay be reflected upwardly by the lower cavity23h1to improve the light extraction.

The upper cavity23h2may be disposed over the lower cavity23h1, and the upper cavity may be disposed in the region that is vertically overlapped with the region of the hole21a. A maximum width of the upper cavity may be greater than a maximum width of the lower cavity, and the maximum width of the upper cavity may be less than a maximum width of the hole. Moreover, a height of the upper cavity may be greater than that of the lower cavity, preferably greater than a depth of the hole. The height of the upper cavity may be greater than the width of the upper cavity.

The cavities23h1and23h2may be disposed below half of the thickness of the buffer layer23a. The cavities23h1and23h2may be disposed closer to the surface of the substrate21than the active layer25, thereby contributing to light scattering, reflection, and emission in a region where the substrate21and the semiconductor layer are in contact.

The lower cavity23h1may be formed in plurality, and may be disposed to be spaced apart from one another. The plurality of lower cavities23h1may have different shapes, and may have irregular shapes. The upper cavity23h2may be formed in plurality, and may be disposed to be spaced apart from one another. The plurality of upper cavities23h2may have different shapes, and may have irregular shapes. At least one upper cavity23h2may have a shape that becomes narrower in a direction closer to the active layer25.

A mesa M is disposed on a partial region of the first conductivity type semiconductor layer23. The mesa M includes the active layer25and the second conductivity type semiconductor layer27. In general, after the first conductivity type semiconductor layer23, the active layer25, and the second conductivity type semiconductor layer27are sequentially grown, the mesa M is formed by patterning the second conductivity type semiconductor layer27and the active layer25through a mesa etching process.

The active layer25may be a single quantum well structure or a multi-quantum well structure including a well layer and a barrier layer. The well layer may be formed of AlGaN or AlInGaN, and the barrier layer may be formed of AlGaN or AlInGaN having a band gap wider than the well layer. For example, each well layer may be formed of AlGaN having an Al molar ratio of about 0.5 with a thickness of about 3.1 nm, and each barrier layer may be formed of AlGaN having an Al molar ratio of about 0.7 or more with a thickness of about 9 nm or more. In particular, a first barrier layer may be formed to be thicker than other barrier layers with a thickness of 12 nm or more. Meanwhile, AlGaN layers having an Al molar ratio of 0.7 to 0.8 in contact with a top and a bottom of each well layer may be disposed in a thickness of about 1 nm, respectively. However, an Al molar ratio of the AlGaN layer in contact with a last well layer may be 0.8 or more in consideration of the contact with an electron blocking layer.

Meanwhile, the second conductivity type semiconductor layer27may include an electron blocking layer and a p-type GaN contact layer. The electron blocking layer prevents electrons from overflowing from the active layer to the second conductivity type semiconductor layer, thereby improving a recombination rate of electrons and holes. The electron blocking layer may be formed of, for example, p-type AlGaN having an Al molar ratio of about 0.8, and may have a thickness of, for example, about 55 nm to about 100 nm. The electron blocking layer may be formed of a plurality of layers having different Al molar ratios. In the plurality of layers having different Al molar ratios, a thickness of a layer having a high Al molar ratio may be twice or more than that of a layer having a low Al molar ratio. A difference in Al molar ratios of the plurality of layers in the electron blocking layer may be in a range of about 0.05 to about 0.1. When the difference in Al molar ratios is too large, a lattice defect may occur due to a lattice difference, and non-luminescent recombination may occur due to the defect before holes reach the active layer. When the difference in Al molar ratios is too small, a band gap energy is large, and a movement of holes is lowered, and thus, a radiation efficiency may be lowered. Therefore, by setting the difference in Al molar ratios in a range of about 0.05 to about 0.1, an efficiency of the hole movement may be facilitated and the radiation efficiency may be increased. Meanwhile, the p-type contact layer may be formed to have a thickness of about 10 nm to about 50 nm, and may be p-AlxGa(1-x)N(0≤x≤0.8). In addition, the p-type contact layer may be formed of a plurality of layers having different Al molar ratios, in which a layer having a higher Al composition ratio among the plurality of layers may be disposed close to the electron blocking layer.

Meanwhile, the p-type GaN contact layer is used for an ohmic contact. The p-type GaN contact layer may absorb light generated in the active layer25. A prior art does not solve a drawback of UV absorption by the p-type GaN contact layer. The present invention may reduce light absorption of the p-type GaN contact layer by reducing the thickness of the p-type GaN contact layer. In the prior art, the p-type GaN contact layer is generally formed to have a thickness of more than 300 nm, but in the illustrated exemplary embodiment, it may be formed to have a thickness of 50 nm or less, further 30 nm or less. As such, light absorption by the p-type GaN contact layer may be reduced to improve the light extraction efficiency.

In another exemplary embodiment, instead of using the p-type GaN contact layer, an n-type AlGaN layer may be formed as the contact layer using a tunnel junction. For example, the n-type AlGaN layer may be tunnel functioned to the p-type AlGaN layer, and the n-type AlGaN layer may be used instead of the p-type contact layer.

The mesa M may have a rectangular shape elongated in one direction, and includes a plurality of via holes30hexposing the first conductivity type semiconductor layer23. Each of the via holes30hmay have a concentrically circular shape, and may be arranged at substantially equal intervals to one another in a region of the mesa M. As well illustrated inFIG. 2A, the via-holes30hmay be arranged in a honeycomb shape, and thus, it is possible to make intervals between the via-holes30huniform.

The via holes30hmay have a mirror symmetrical structure with respect to a plane passing in a short axis direction of the mesa M. This mirror symmetrical structure assists to spread currents in the mesa M to improve a radiation efficiency.

Meanwhile, the n-ohmic contact layers31are disposed on the first conductivity type semiconductor layer23exposed to the via holes30h. The n-ohmic contact layers31may be formed by depositing a plurality of metal layers, and thereafter, by alloying the metal layers through a rapid thermal alloy (RTA) process. For example, the n-ohmic contact layers31may be alloyed through the RTA process after sequentially depositing Cr/Ti/Al/Ti/Au. Accordingly, the n-ohmic contact layers31become alloy layers containing Cr, Ti, Al, and Au.

The n-ohmic contact layers31are disposed in the via holes30h, respectively. The n-ohmic contact layers31are spaced apart from the active layer25and the second conductivity type semiconductor layer27in the via holes30h. In a UV light emitting diode according to the prior art, an n-ohmic contact layer is generally formed to surround the mesa M along a perimeter of the mesa M, but in the illustrated exemplary embodiment, the n-ohmic contact layer is not disposed around the mesa M. Accordingly, it is possible to prevent light emitted through a side surface of the mesa M from being blocked by the n-ohmic contact layer31or the like.

The p-ohmic contact layer33is disposed on the second conductivity type semiconductor layer27to be in-ohmic contact with the second conductivity type semiconductor layer27. The p-ohmic contact layer33may be formed through, for example, the RTA process after depositing Ni/Rh. The p-ohmic contact layer33is in-ohmic contact with the second conductivity type semiconductor layer27, and covers most of a region over the mesa M, for example, 80% or more. Rh has a higher reflectivity to UV rays than Au, which is advantageous for improving the light extraction efficiency. In this specification, since the thickness of the p-type GaN contact layer is reduced to decrease light absorption by the p-type GaN contact layer, so as to reflect light passing through the second conductivity type semiconductor layer27, favorable reflection performance of the p-ohmic contact layer33is required.

The lower insulation layer35covers the mesa M, and covers the p-ohmic contact layer33and the n-ohmic contact layers31. The lower insulation layer35also covers the exposed first conductivity type semiconductor layer23around the mesa M and in the via holes30h. Meanwhile, the lower insulation layer35has openings35afor allowing electrical connection to the n-ohmic contact layers31and openings35bfor allowing electrical connection to the p-ohmic contact layer33. The opening35bmay be formed so as to surround all of the via holes30hin a ring shape.

The lower insulation layer35may be formed of, for example, SiO2, without being limited thereto, or may be formed as a distributed Bragg reflector.

Meanwhile, the n-pad metal layer37aand the p-pad metal layer37bare disposed on the lower insulation layer35. The n-pad metal layer37aand the p-pad metal layer37bmay be formed together in a same process as a same metal layer and disposed on a same level, that is, on the lower insulation layer35. The n- and p-pad metal layers37aand37bmay include, for example, Al layers.

The n-pad metal layer37ais electrically connected to the n-ohmic contact layers31through the openings35aof the lower insulation layer35. The n-ohmic contact layers31are electrically connected to one another by the n-pad metal layer37a. The n-pad metal layer37amay be disposed within the region of the mesa M. The n-pad metal layer37amay function as a reflection layer (second reflection layer) that reflects light emitted through the side surface of the mesa M in the via hole30h, thereby improving a light efficiency of the light emitting diode.

Meanwhile, the p-pad metal layer37bmay be electrically connected to the p-ohmic contact layer33through the opening35bof the lower insulation layer35. The p-pad metal layer37bmay cover the opening35b, and may surround the n-pad metal layer37ain a ring shape. The p-pad metal layer37bmay be limited in the region over the mesa M such that the p-pad metal layer does not cover side surfaces of the mesa M.

The upper insulation layer39covers the n-pad metal layer37aand the p-pad metal layer37b. Meanwhile, the upper insulation layer39has openings39aexposing the n-pad metal layer37aand has openings39bover the mesa M exposing the p-pad metal layer37b. The opening39amay expose the n-pad metal layer37anear one edge of the mesa M, and the opening39bmay expose the p-pad metal layer37bnear an opposite edge of the mesa M.

A plurality of openings39amay be arranged, without being limited thereto, or one opening39amay be arranged. In addition, although the opening39bis illustrated as being continuously formed in a C shape in the drawing, the plurality of openings39bmay be disposed apart from one another. The upper insulation layer39may be formed of, for example, silicon nitride or silicon oxide.

The n-bump41aand the p-bump41bare placed on the upper insulation layer39. The n-bump41acovers the openings39aand is connected to the n-pad metal layer37aexposed through the openings39a. The n-bump41ais electrically connected to the first conductivity type semiconductor layer23through the n-pad metal layer37aand the n-ohmic contact layer31. Outer edges of the n-bump41aand the p-bump41bmay be disposed over the mesa M so as not to cover the side surface of the mesa M.

The p-bump41bcovers the opening39band is connected to the p-pad metal layer37bexposed through the opening39b. The p-bump41bis electrically connected to the second conductivity type semiconductor layer27through the p-pad metal layer37band the p-ohmic contact layer33.

The n-bump41aand the p-bump41bmay be formed of, for example, Ti/Au/Cr/Au. As shown inFIG. 1, the n-bump41aand the p-bump41bmay be disposed opposite each other, and may occupy about ⅓ of an area of the mesa M, respectively. By making the areas of the n-bump41aand the p-bump41brelatively wide, heat generated in the light emitting diode may be easily dissipated, thereby improving a performance of the light emitting diode.

Furthermore, the openings39aand39bare covered by the n-bump41aand the p-bump41b, and thus, moisture or solder from the outside may be prevented from infiltrating into a device through the openings39aand39b, thereby improving a reliability thereof.

Meanwhile, although not shown, an anti-reflection layer may be disposed on a light exiting surface of the substrate21. The anti-reflection layer may be formed of a transparent insulation layer such as SiO2to have a thickness that is an integer multiple of ¼ of a wavelength of ultraviolet rays, for example. Alternatively, a bandpass filter in which layers having different refractive indices are repeatedly stacked may be used as the anti-reflection layer.

First, referring toFIG. 4AandFIG. 4B, a hole pattern is formed on an upper surface of a substrate21. A plurality of holes21amay be formed on the surface of the substrate. The holes21amay be formed using photolithography and etching processes, but expensive equipment has to be introduced for the photolithography process so as to form small-sized holes21a. To avoid this, nano-imprint technology may be used. Sizes, shapes, and arrangements of the holes21aare identical to those described above with reference toFIGS. 2A, 2B, and 2C, and thus detailed descriptions thereof will be omitted.

Referring toFIG. 5AandFIG. 5B, a first conductivity type semiconductor layer23, an active layer25, and a second conductivity type semiconductor layer27are grown on the substrate21.

Since the first conductivity type semiconductor layer23, the active layer25, and the second conductivity type semiconductor layer27are identical to those described above, detailed descriptions thereof will be omitted to avoid redundancy. However, the second conductivity type semiconductor layer27may include a semiconductor layer having a band gap smaller than a well layer of the active layer25, for example, a GaN layer. In particular, a p-type GaN layer may be used for an ohmic contact. The semiconductor layer having the band gap smaller than the well layer is controlled to have a thickness of 500 nm or less, furthermore, 30 nm or less. In another exemplary embodiment, the p-type GaN layer is omitted, and an n-type AlGaN layer tunnel functioned to the p-type AlGaN layer may be used instead of the p-type contact layer.

Meanwhile, a mesa M is formed by patterning the second conductivity type semiconductor layer27and the active layer25. The mesa M may have a generally elongated rectangular shape, but the inventive concepts are not limited to a specific shape. As the mesa M is formed, the first conductivity type semiconductor layer23may be exposed along a perimeter of the mesa M. Also, a plurality of via holes30hare formed in a mesa M region. The via holes30hexpose the first conductivity type semiconductor layer23. The via holes30hmay be spaced apart from one another at substantially equal intervals, and may be arranged, for example, in a honeycomb structure. Furthermore, the via-holes30hmay be spaced apart from an edge of the mesa M by more than the interval between the via-holes30h.

Referring toFIG. 6AandFIG. 6B, n-ohmic contact layers31are formed on bottom surfaces of the via holes30h. The n-ohmic contact layers31may be alloyed through an RTA process, for example, after sequentially depositing Cr/Ti/Al/Ti/Au. For example, the n-ohmic contact layer31may be alloyed through the RTA process at about 965° C. for 30 seconds.

Referring toFIG. 7AandFIG. 7B, after the n-ohmic contact layer31is formed, a p-ohmic contact layer33is formed on the mesa M. The p-ohmic contact layer33is in ohmic contact with the second conductivity type semiconductor layer27. In particular, the p-ohmic contact layer33may be in ohmic contact with the p-type GaN layer.

The p-ohmic contact layer33may include a reflection metal layer such as Au or Rh. For example, after depositing Ni/Au or Ni/Rh, it may be alloyed through the RTA process. Ni/Au may be heat-treated, for example, at 590° C. for 80 seconds. In contrast, Ni/Rh may be heat-treated at a relatively lower temperature for a longer time, for example, may be heat-treated at 500° C. for 5 minutes. Rh has a higher reflectivity to UV rays than Au, and thus, the light extraction efficiency may be further increased.

Furthermore, Ni/Rh is advantageous compared to Ni/Au because an interface between the p-type contact layer27and the p-ohmic contact layer33is formed smoothly to exhibit stable ohmic resistance characteristics. In addition, since the present invention reduces light absorption of the p-type contact layer27by reducing a thickness of the p-type GaN contact layer, an amount of light reflected by the p-ohmic contact layer33is increased. Accordingly, the light extraction efficiency may be improved by using Rh having a relatively high reflectivity.

Referring toFIG. 8AandFIG. 8B, a lower insulation layer35is formed on the mesa M. The lower insulation layer35covers side and upper surfaces of the mesa M. The lower insulation layer35covers the n-ohmic contact layer31and the p-ohmic contact layer33. Meanwhile, the lower insulation layer35has openings35aexposing the n-ohmic contact layers31and openings35bexposing the p-ohmic contact layer33.

The opening35bof the lower insulation layer35may be formed in a ring shape along an entire perimeter of the via holes30h. However, the inventive concepts are not limited thereto, and a plurality of openings may be formed so as to expose the p-ohmic contact layer33. For example, a portion of the ring-shaped opening35bclose to the via holes30hmay be covered with the lower insulation layer35, and openings may be formed in portions thereof relatively far from the via holes30h.

Referring toFIG. 9AandFIG. 9B, an n-pad metal layer37aand a p-pad metal layer37bare formed on the lower insulation layer35. The n-pad metal layer37amay be formed so as to cover the via-holes30h, and may be electrically connected to the n-ohmic contact layers31in the via-holes30h. The n-pad metal layer37amay also cover inner walls of the via holes30h.

The p pad metal layer37bmay cover the opening35b, and may be electrically connected to the p-ohmic contact layer33exposed to the opening35b. The p-pad metal layer37bmay be formed in a ring shape so as to surround the n-pad metal layer37a. The p-pad metal layer37bmay be formed so as to cover the side surface of the mesa M, or may be formed to be limited in a region over the mesa M so as not to block light emitted to the side surface of the mesa M.

Referring toFIG. 10AandFIG. 10B, an upper insulation layer39is formed on the n-pad metal layer37aand the p-pad metal layer37b. The upper insulation layer39may cover the n-pad metal layer37aand the p-pad metal layer37band may also cover the side surface of the mesa M.

Meanwhile, the upper insulation layer39has openings39aand39bexposing the n-pad metal layer37aand the p-pad metal layer37b. The openings39aexpose the n-pad metal layer37a, and the openings39bexpose the p-pad metal layer37b. The openings39amay be formed near one edge of the mesa M, and the opening39bmay be formed near an opposite edge of the mesa M to face the openings39a.

Referring toFIG. 11AandFIG. 11B, an n-bump41aand a p-bump41bare formed on the upper insulation layer39. The n-bump41ais electrically connected to the n-pad metal layer37athrough the openings39a, and the p-bump41bis electrically connected to the p-pad metal layer37bthrough the opening39b.

The n-bump41aand p-bump41bmay partially cover the side surface of the mesa M, respectively, but may be formed so as to be limited a region over the mesa M.

According to the illustrated exemplary embodiment, current may be uniformly spread over an entire region of the mesa M by forming the via holes30hin the mesa M region and forming the n-ohmic contact layers31. In addition, the light extraction efficiency may be improved by reducing the thickness of the p-type GaN contact layer that absorbs light generated in the active layer25and by using Ni/Rh as the p-ohmic contact layer33.

Although the via hole30hhas been illustrated and described as having a circular shape in the previous exemplary embodiment, the shape of the via hole is not limited to the circular shape, and may have various other shapes. The shape and the size of the via hole30haffect the size of the ohmic contact region or the size of the light emitting region. Accordingly, the shape of the via hole30hmay be variously modified so as to adjust a magnitude of a radiation intensity.

FIG. 12Ais a schematic plan view illustrating a UV light emitting diode according to an exemplary embodiment of the present disclosure, andFIG. 12Bis a schematic cross-sectional view taken along line B-B′ of its corresponding plan view shown inFIG. 12A.

Referring toFIG. 12AandFIG. 12B, the UV light emitting diode according to the illustrated exemplary embodiment may include a substrate121, a first conductivity type semiconductor layer123, an active layer125, a second conductivity type semiconductor layer127, and n-ohmic contact layers131aand131b, a p-ohmic contact layer133, an n-capping layer134a, a p-capping layer134b, a lower insulation layer135, an n-pad metal layer137a, a p-pad metal layer137b, an upper insulation layer139, an n-bump141a, and a p-bump141b.

The substrate121includes a plurality of holes121asurrounded by a flat surface121b. Since the substrate121is similar to the substrate21described with reference toFIGS. 1A and 1B, a detailed description thereof will be omitted to avoid redundancy. The first conductivity type semiconductor layer123is disposed on the substrate121. The first conductivity type semiconductor layer123is substantially similar to the first conductivity type semiconductor layer23described with reference toFIGS. 1A and 1B. In addition, as described with reference toFIG. 3A, a cavity may be formed in the first conductivity type semiconductor layer123. However, in the illustrated exemplary embodiment, edges of an n-type semiconductor layer123may be disposed inside a region surrounded by edges of the substrate121, and thus, an upper surface of the substrate121may be exposed along the edges of the first semiconductor layer123. However, the inventive concepts are not limited thereto, and an entire surface of the substrate121may be covered with the first conductivity type semiconductor layer123. Furthermore, an upper surface of an AlN layer, which is a portion of the first conductivity type semiconductor layer123, may be exposed near the edge of the substrate121.

A mesa M is disposed on a partial region of the first conductivity type semiconductor layer123. The mesa M includes the active layer125and the second conductivity type semiconductor layer127. In general, the first conductivity type semiconductor layer123, the active layer125, and the second conductivity type semiconductor layer127are sequentially grown, and thereafter, the mesa M is formed by patterning the second conductivity type semiconductor layer127and the active layer125through a mesa etching process.

Since a stacked structure of the active layer125and the second conductivity type semiconductor layer127is similar to that described with reference toFIGS. 1A and 1B, a detailed description thereof will be omitted to avoid redundancy.

The mesa M may have a rectangular external shape elongated in one direction, and includes a groove130gexposing the first conductivity type semiconductor layer123. The groove130gmay extend along a longitudinal direction of the mesa M. As shown inFIG. 12A, the groove130gmay extend from one edge of the mesa M toward an opposite edge thereof along the longitudinal direction of the mesa M. A mesa region is disposed on both sides of the groove130gby the groove130g. A length of the groove130gexceeds ½ of a length of the mesa M. In other words, the length of the groove130gis greater than a distance between an inner end of the groove130gand the opposite edge of the mesa M. Furthermore, the distance between the inner end of the groove130gand the opposite edge of the mesa M may be smaller than a width of the mesa region disposed on both sides of the groove130g.

The groove130gmay have a linear shape, and the mesa M may have a symmetrical structure with respect to a straight line passing through a center of the light emitting diode and parallel to the groove130g.

Meanwhile, corners of the mesa M may have curved shapes. The edge of the mesa M may include a straight region and curved regions disposed on both sides thereof. By forming the corners of the mesa M to be curved, it is possible to prevent light from being condensed at the corner portion and thereby being lost due to light absorption.

Meanwhile, the n-ohmic contact layer131ais disposed on the first conductivity type semiconductor layer123exposed by the groove130g. The n-ohmic contact layer131bis disposed on the first conductivity type semiconductor layer123exposed along a perimeter of the mesa M. The n-ohmic contact layer131amay be connected to the n-ohmic contact layer131b, but the inventive concepts are not limited thereto. The n-ohmic contact layers131aand131bmay be spaced apart from the mesa M to surround the mesa M.

Materials and methods of forming the n-ohmic contact layers131aand131bare similar to those of forming the n-ohmic contact layers31described with reference toFIGS. 1A and 1B, and thus, detailed descriptions thereof will be omitted to avoid redundancy.

The p-ohmic contact layer133is disposed on the second conductivity type semiconductor layer127to be in ohmic contact with the second conductivity type semiconductor layer127. The p-ohmic contact layer133may be formed using, for example, Ni/Rh or Ni/Au. The p-ohmic contact layer133is in ohmic contact with the second conductivity type semiconductor layer127and covers most of a region over the mesa M, for example, 80% or more.

The n-capping layer134amay cover upper surfaces and side surfaces of the n-ohmic contact layers131aand131b. The p-capping layer134bmay cover the upper and side surfaces of the p-ohmic contact layer133. The n-capping layer134aand the p-capping layer134bprevent the n-ohmic contact layers131aand131band the p-ohmic contact layer133from being damaged by etching, oxidation, or the like, respectively. The n-capping layer134aand the p-capping layer134bmay be formed of a same metal in a same process. For example, the n-capping layer134aand the p-capping layer134bmay be formed of Ti/Au/Ti.

The lower insulation layer135covers the mesa M, and covers the n-capping layer134aand the p-capping layer134b. The lower insulation layer135also covers the first conductivity type semiconductor layer123exposed around the mesa M and in the groove130g. Furthermore, the lower insulation layer135may cover a portion of the substrate121exposed around the first conductivity type semiconductor layer123. Meanwhile, the lower insulation layer135has openings135afor allowing electrical connection to the n-ohmic contact layers131aand131band openings135bfor allowing electrical connection to the p-ohmic contact layer133. The opening135amay have a shape similar to those of the n-ohmic contact layers131aand131bor the n-capping layer134a. That is, the opening135asurrounds the mesa M and also extends into the groove130g. A width of the opening135amay be smaller than that of the n-capping layer134a, and thus, the first conductivity type semiconductor layer123may not be exposed through the opening135a. Meanwhile, the opening135bis disposed in the region over the mesa M, and exposes the p-capping layer134b. A plurality of openings135bmay be disposed on the p-capping layer134b. In particular, the openings may be symmetrically disposed on both sides of the groove130g.

The lower insulation layer135may be formed of, for example, SiO2, without being limited thereto, and may be formed as a distributed Bragg reflector. In particular, the lower insulation layer135may be formed so as to constitute an omni-directional reflector (ODR). For example, the lower insulation layer135may be formed of about 10,000 Å of SiO2.

Meanwhile, the n-pad metal layer137aand the p-pad metal layer137bare disposed on the lower insulation layer135. The n-pad metal layer137aand the p-pad metal layer137bmay be formed together in a same process with a same metal layer and disposed on a same level, that is, on the lower insulation layer135. The n and p-pad metal layers137aand137bmay include, for example, an Al layer.

The n-pad metal layer137ais electrically connected to the n-ohmic contact layers131aand131bthrough the opening135aof the lower insulation layer135. The n-pad metal layer137amay directly contact the n-capping layer134athrough the opening135aof the lower insulation layer135. The n-pad metal layer137amay cover most region of the mesa M, and may also cover a region around the mesa M. The n-pad metal layer137amay form the ODR together with the lower insulation layer135.

Meanwhile, the p-pad metal layer137bmay be electrically connected to the p-ohmic contact layer133through the opening135bof the lower insulation layer135. The p-pad metal layers137bmay cover each of the openings135b. Each of the p-pad metal layers137bmay be surrounded by the n-pad metal layer137a. The p-pad metal layers37bmay be limited in the region over the mesa M. In the illustrated exemplary embodiment, all side surfaces of the mesa M are covered with the n-pad metal layer137a. Accordingly, it is possible to prevent light loss from occurring at the side surfaces of the mesa M.

The upper insulation layer139covers the n-pad metal layer137aand the p-pad metal layer137b. However, the upper insulation layer139may have openings139aexposing the n-pad metal layer137aand openings139bexposing the p-pad metal layer137b. The opening139amay expose the n-pad metal layer137anear one edge of the mesa M, and the openings139bmay expose the p-pad metal layer137bnear the opposite edge of the mesa M. The openings139aand139bmay be symmetrically disposed with respect to a line passing through the groove130g, but the inventive concepts are not limited thereto.

The upper insulation layer139may be formed of, for example, silicon nitride or silicon oxide.

The n-bump141aand the p-bump141bare disposed on the upper insulation layer139. The n-bump141acovers the openings139aand is connected to the n-pad metal layer137aexposed through the openings139a. The n-bump141ais electrically connected to the first conductivity type semiconductor layer123through the n-pad metal layer137aand the n-ohmic contact layers131aand131b. The n-bump141aand the p-bump141bmay partially cover the side surfaces of the mesa M.

The p-bump141bcovers the openings139band is connected to the p-pad metal layer137bexposed through the openings139b. The p-bump141bis electrically connected to the second conductivity type semiconductor layer127through the p-pad metal layer137band the p-ohmic contact layer133.

The n-bump141aand p-bump141bmay include Ti/Au, and may be formed of, for example, Ti/Au/Cr/Au or Ti/Ni/Ti/Ni/TiNi/Ti/Au. As shown inFIG. 12A, the n-bump141aand the p-bump141bmay be disposed opposite each other, and may occupy about ⅓ of an area of the mesa M, respectively. By making the areas of the n-bump141aand the p-bump141brelatively wide, heat generated in the light emitting diode may be easily dissipated, thereby improving a performance of the light emitting diode.

Furthermore, the openings139aand139bare covered by the n-bump141aand the p-bump141b, and thus, moisture or solder from the outside may be prevented from infiltrating into the openings139aand139b, thereby improving reliability.

Meanwhile, although not shown, an anti-reflection layer may be disposed on a light exiting surface of the substrate121. The anti-reflection layer may be formed of a transparent insulation layer such as SiO2to have a thickness that is an integer multiple of ¼ of a wavelength of ultraviolet rays, for example. Alternatively, a bandpass filter in which layers having different refractive indices are repeatedly stacked may be used as the anti-reflection layer.

Referring toFIG. 13AandFIG. 13B, first, a first conductivity type semiconductor layer123, an active layer125, and a second conductivity type semiconductor layer127are grown on a substrate121.

The substrate121includes a plurality of holes121asurrounded by a flat surface121b. Since the substrate121, the first conductivity type semiconductor layer123, the active layer125, and the second conductivity type semiconductor layer127are identical to those described above, detailed descriptions thereof will be omitted to avoid redundancy.

Meanwhile, a mesa M is formed by patterning the second conductivity type semiconductor layer127and the active layer125. The mesa M may have a generally elongated rectangular shape, but the inventive concepts are not limited to a specific shape. As the mesa M is formed, the first conductivity type semiconductor layer123may be exposed along a perimeter of the mesa M. In addition, a groove130gis formed in a mesa M region. The groove130gmay extend from one edge toward an opposite edge along a longitudinal direction of the mesa M. An inner end of the groove130gmay be disposed near the opposite edge. The mesa regions disposed on both sides of the groove130gmay be identical to one another, and a width of each of the mesa regions may be greater than or equal to a distance between the inner end of the groove130gand the opposite edge of the mesa M.

Referring toFIG. 14AandFIG. 14B, n-ohmic contact layers131aand131bare formed on the first conductivity type semiconductor layer123. The n-ohmic contact layers131aand131bmay be formed by, for example, sequentially depositing Cr/Ti/Al/Ti/Au, and thereafter being alloyed using an RTA process. For example, the n-ohmic contact layers131aand131bmay be alloyed through the RTA process at about 965° C. for 30 seconds. The n-ohmic contact layer131ais formed on the first conductivity type semiconductor layer123exposed by the groove130g, and the n-ohmic contact layer131bis formed on the first conductivity type semiconductor layer123exposed around the mesa M. The n-ohmic contact layer131amay extend from the n-ohmic contact layer131b. By continuously forming the n-ohmic contact layer131aand the n-ohmic contact layer131b, current spreading may be aided. However, the inventive concepts are not limited thereto, and the n-ohmic contact layer131amay be spaced apart from the n-ohmic contact layer131b.

Referring toFIG. 15AandFIG. 15B, after the n-ohmic contact layers131aand131bare formed, a p-ohmic contact layer133is formed on the mesa M. The p-ohmic contact layer133is in ohmic contact with the second conductivity type semiconductor layer127. In particular, the p-ohmic contact layer133may be in ohmic contact with a p-type GaN layer.

The p-ohmic contact layer133may include a reflection metal layer such as Au or Rh. For example, after depositing Ni/Au or Ni/Rh, it may be alloyed through the RTA process.

Referring toFIG. 16AandFIG. 16B, an isolation process for dividing the first conductivity type semiconductor layer123is carried out. That is, the first conductivity type semiconductor layer123between adjacent light emitting diode regions is removed to expose an upper surface of the substrate121. By adding the isolation process, singularization of the light emitting diodes may be aided.

Referring toFIG. 17AandFIG. 17B, an n-capping layer134aand a p-capping layer134bare formed. The n-capping layer134acovers upper and side surfaces of the n-type ohmic contact layers131aand131b, and the p-capping layer134bcovers upper and side surfaces of the p-type ohmic contact layer133. The n-capping layer134aand the p-capping layer134bmay be formed of, for example, Ti/Au/Ti.

Referring toFIG. 18AandFIG. 18B, a lower insulation layer135covering the mesa M is formed. The lower insulation layer135covers side and upper surfaces of the mesa M. The lower insulation layer135also covers the n-capping layer134aand the p-capping layer134b. The lower insulation layer135may cover a side surface of the first conductivity type semiconductor layer123, and may partially cover the substrate121exposed around the first conductivity type semiconductor layer123. Meanwhile, the lower insulation layer135has openings135aand135bexposing the n-capping layer134aand the p-capping layer134b.

The opening135aof the lower insulation layer135exposes the n-capping layer134a, and the opening135bexposes the p-capping layer134b. A plurality of openings135bmay be formed on the p-capping layer134b. As illustrated, the openings135bmay be symmetrically disposed on both sides of the groove130g.

Referring toFIG. 19AandFIG. 19B, an n-pad metal layer137aand a p-pad metal layer137bare formed on the lower insulation layer135. The n-pad metal layer137amay be electrically connected to the n-capping layer134athrough the opening135a, and the p-pad metal layer137bmay be electrically connected to the p-capping layer134bthrough the opening135b. As illustrated, the n-pad metal layer137amay surround the p-pad metal layers137b.

The n-pad metal layer137amay cover the opening135a, and the p-pad metal layer137bmay cover the opening135b. In addition, the n-pad metal layer137amay continuously cover the side surface of the mesa M, and thus, light reflectivity may be improved on the side surface of the mesa M.

Referring toFIG. 20AandFIG. 20B, an upper insulation layer139is formed on the n-pad metal layer137aand the p-pad metal layer137b. The upper insulation layer139may cover the n-pad metal layer137aand the p-pad metal layer137band may also cover an edge of the first conductivity type semiconductor layer123. The upper insulation layer139may also cover a portion of the upper surface of the substrate121.

The upper insulation layer139has openings139aand139bexposing the n-pad metal layer137aand the p-pad metal layer137b. The openings139aexpose the n-pad metal layer137a, and the openings139bexpose the p-pad metal layer137b. The openings139amay be formed near one edge of the mesa M, and the openings139bmay be formed near an opposite edge of the mesa M to face the openings139a.

Subsequently, as shown inFIGS. 12A and 12B, an n-bump141aand a p-bump141bare formed on the upper insulation layer139. The n-bump141ais electrically connected to the n-pad metal layer137athrough the openings139a, and the p-bump141bis electrically connected to the p-pad metal layer137bthrough the opening139b.

The n-bump141aand p-bump141bmay partially cover the side surface of the mesa M, respectively, but may be formed to be limited in a region over the mesa M.

According to the illustrated exemplary embodiment, by forming the groove130gwithin the mesa M region and forming the n-ohmic contact layers131aand131baround the mesa M and in the groove130g, current may be uniformly spread over an entire region of the mesa M.

FIG. 21is a schematic plan view illustrating a modified example of a mesa of a UV light emitting diode according to an exemplary embodiment of the present disclosure.

Referring toFIG. 21, a groove130gextends from one edge of the mesa M toward an opposite edge in a longitudinal direction. A distance between an inner end of the groove130gand the opposite edge of the mesa M, that is, a difference W1between a total length of the mesa M and a length of the groove130gmay be less than or equal to a width W2of each mesa region which is disposed on both sides of the groove130g. Moreover, the length of the groove130gis greater than W1, and thus, exceeds ½ of the length of the mesa M. Meanwhile, an area A1of the mesa M between the groove130gand the opposite edge of the mesa M may be smaller than an area A2of each mesa region disposed on the both sides of the mesa M. That is, a total area2A2of the mesa regions disposed on the both sides of the mesa M may exceed ½ of a total area of the mesa.

FIG. 22is a schematic cross-sectional view illustrating a light emitting module according to an exemplary embodiment of the present disclosure.

Referring toFIG. 22, the light emitting module may include a circuit board201, a light emitting diode200, bonding layers203aand203b, and a cover205. Since the light emitting diode200is identical to the light emitting diode described with reference toFIGS. 12Aand12B, a detailed description thereof will be omitted. The light emitting diode100described with reference toFIGS. 1A and 1Bmay be used.

The light emitting diode200may be flip-bonded on the circuit board201such that the substrate121is disposed on an upper surface thereof to form a light exiting surface. The light emitting diode200may be bonded to the circuit board201through the bonding layers203aand203b.

The cover205covers the light emitting diode200. The cover205may be formed of a material having transmittance to ultraviolet rays. The cover205in a form of quartz or glass may be disposed over to be spaced apart from the light emitting diode200, or in contrast, as shown inFIG. 22, the cover205formed of a silicone material may be disposed to cover upper and side surfaces of the light emitting diode200. When the silicone material is used, an external shape may be a dome-type shape having a curved surface so as to facilitate light extraction. To prevent damage to the silicone material by ultraviolet rays, the silicone material may be a fluorine-based material, and may include a carbon material together. A content of fluorine compared to carbon may be in a range of 10-35 atomic %: 65-90 atomic %, and in a case of having such a fluorine content, it is possible to effectively extract 200 nm to 300 nm of UV light while maintaining an effect of preventing silicone damage. In the above case, since an active layer125generating UV light is disposed closer to a flat surface121bof a substrate121, a possibility of light first contacting and entering the flat surface121bincreases. Accordingly, a decrease in luminous intensity due to scattering of light generated at a boundary between the substrate121and the semiconductor layer is prevented, and the light extraction efficiency is increased.

Example

According to a prior art, a UV light emitting diode of a Comparative Example was manufactured using a flat sapphire substrate having no hole pattern as a growth substrate, and, a UV light emitting diode of an Inventive Example was manufactured using a sapphire substrate having a hole pattern as a growth substrate. Both Comparative Example and Inventive Example were fabricated using 2-inch wafers. In an exemplary embodiment, a hole pattern was formed with a target that a diameter of the hole (D2) was 800 nm (±40 nm), and a depth of the hole was 200 nm (±50 nm). For the Comparative Example, five samples fabricated on a same wafer were prepared, and for the Inventive Example, nine samples fabricated on a same wafer were prepared. The samples of these Comparative Example and Inventive Example were driven at room temperature for 1000 hours to measure changes of light outputs, threshold voltages, and turn-on voltages over time with respect to an initial light output. The initial light output means radiant power measured within 24 hours after driving the samples. The initial light output was expressed as 100%, and the changes over time at 250-hour intervals were summarized in Tables 1 and 2 below as a percentage of an initial value. The initial light outputs and turn-on voltages of the samples of the Inventive Example were relatively higher than those of the samples of the Comparative Example, and the initial threshold voltages of the samples of the Inventive Example were relatively lower than those of the samples of the Comparative Example.

Referring to Tables 1 and 2, the samples of the Inventive Example exhibited light output of 85% or more compared to the initial value after driving for 1000 hours, and most of them exhibited light output of 90% or more. Among the samples, the light output of the sample showing a minimum value after driving for 1000 hours was 87.4% compared to the initial value. In contrast, the samples of Comparative Example exhibited the light output of less than 85% compared to the initial value after 1000 hours of driving, and most of them exhibited the light output of 80% or less. Among the samples of Comparative Example, the light output of the sample showing a maximum value after 1000 hours of driving was 81.9% compared to the initial value.

The threshold voltages of the samples of the Inventive Example were also maintained closer to the initial value than the samples of the Comparative Example after driving for 1000 hours. Meanwhile, the turn-on voltages of the samples of the Comparative Example were generally increased after driving for 1000 hours, and the turn-on voltage of Sample4was sharply decreased after driving for 1000 hours.

As a result of the driving test of the samples of the Comparative Example and the Inventive Example, it is understood that the samples of the Inventive Example to which the hole pattern is added have the high initial light outputs and well maintain the light outputs even after driving for a long time.

Although some exemplary embodiments have been described herein, it should be understood that the above exemplary embodiments may be variously modified and changed without departing from the spirit and scope of the present disclosure, and the present disclosure includes all of the broad scope of the appended claims.