Devices and methods for reducing power consumption of a demultiplexer

The present disclosure relates to devices and methods for reducing power consumption of a display. One electronic display includes a first switch coupled between a first gate of a first transistor and a second gate of a second transistor to selectively connect the first gate to the second gate. The display includes a second switch coupled between the second gate of the second transistor and a third gate of a third transistor to selectively connect the second gate to the third gate. The display also includes driving circuitry that controls the first switch to connect the first gate to the second gate to share a first charge between the first and second gates. The driving circuitry also controls the second switch to connect the second gate to the third gate to share a second charge between the second and third gates. Accordingly, power consumption of the display may be reduced.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Non-Provisional Application of U.S. Provisional Patent Application No. 61/725,806, entitled “Devices and Methods for Reducing Power Consumption of a Demultiplexer”, filed Nov. 13, 2012, which is herein incorporated by reference.

BACKGROUND

The present disclosure relates generally to electronic displays and, more particularly, to reducing power consumption of a demultiplexer of a display.

Electronic displays, such as liquid crystal displays (LCDs) or organic light emitting diode (OLED) displays, are commonly used in electronic devices such as televisions, computers, and handheld devices (e.g., cellular telephones, audio and video players, gaming systems, and so forth). Such display devices typically provide a flat display in a relatively thin package that is suitable for use in a variety of electronic goods. In addition, such display devices typically use less power than comparable display technologies, making them suitable for use in battery-powered devices or in other contexts where it is desirable to minimize power usage.

LCDs typically include an LCD panel having, among other things, a liquid crystal layer and various circuitry for controlling orientation of liquid crystals within the layer to modulate an amount of light passing through the LCD panel and thereby render images on the panel. The LCD may include a demultiplexer to facilitate sharing of each output from the LCD driving circuitry with multiple data lines of the LCD panel. For example, each output from the LCD driving circuitry may be used to provide pixel data to three data lines of the LCD panel. The demultiplexer may include multiple switches, such as thin-film transistors (TFTs), to alternate which of the data lines each output from the LCD driving circuitry is electrically connected to. OLED displays may also include a demultiplexer with multiple switches, such as TFTs, to alternate which of the data lines receive output from driving circuitry. Unfortunately, the TFTs in either type of display may be activated using a high gate voltage resulting in large voltage swings when alternating between activating and deactivating the gate. Therefore, the demultiplexer may consume a substantial amount of power. Accordingly, there is a need for low power techniques that decrease the amount of power consumed by a demultiplexer, and thereby decreasing the amount of power consumed by an electronic display.

SUMMARY

The present disclosure relates to various techniques, systems, devices, and methods for reducing power consumption of a display. Accordingly, a demultiplexer of the display may include multiple thin-film transistors (TFTs) with gates that are activated using driving circuitry. Certain gates of the TFTs may be selectively coupled together during operation of the demultiplexer to facilitate charge sharing between the gates to reduce power consumption of the demultiplexer, and thereby reduce power consumption of the display. For example, one electronic display includes a demultiplexer having a first transistor, a second transistor, and a third transistor. The display also includes a first switch coupled between a first gate of the first transistor and a second gate of the second transistor. The first switch may be used to selectively connect the first gate to the second gate. The display includes a second switch coupled between the second gate of the second transistor and a third gate of the third transistor. The second switch may be used to selectively connect the second gate to the third gate. The display also includes driving circuitry that controls the first switch to connect the first gate to the second gate to share a first charge stored on the first gate with the second gate. The driving circuitry also controls the second switch to connect the second gate to the third gate to share a second charge stored on the second gate with the third gate. Accordingly, power consumption of the display may be reduced.

DETAILED DESCRIPTION

With the foregoing in mind, it is useful to begin with a general description of suitable electronic devices that may employ the display devices and techniques described below. In particular,FIG. 1is a block diagram depicting various components that may be present in an electronic device suitable for use with such display devices and techniques.FIGS. 2, 3, and 4respectively illustrate front and perspective views of suitable electronic devices, which may be, as illustrated, a handheld electronic device, a tablet computing device, or a notebook computer.

Turning first toFIG. 1, an electronic device10according to an embodiment of the present disclosure may include, among other things, a display12, input/output (I/O) ports14, input structures16, one or more processor(s)18, memory20, nonvolatile storage22, an expansion card24, RF circuitry26, and a power source28. The various functional blocks shown inFIG. 1may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium) or a combination of both hardware and software elements. It should be noted thatFIG. 1is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in the electronic device10.

By way of example, the electronic device10may represent a block diagram of the handheld device depicted inFIG. 2, the tablet computing device depicted inFIG. 3, the notebook computer depicted inFIG. 4, or similar devices, such as desktop computers, televisions, and so forth. It should be noted that the processor(s)18and/or other data processing circuitry may be generally referred to herein as “data processing circuitry.” This data processing circuitry may be embodied wholly or in part as software, firmware, hardware, or any combination thereof. Furthermore, the data processing circuitry may be a single contained processing module or may be incorporated wholly or partially within any of the other elements within the electronic device10.

In the electronic device10ofFIG. 1, the processor(s)18and/or other data processing circuitry may be operably coupled with the memory20and the nonvolatile storage22to execute instructions. Such programs or instructions executed by the processor(s)18may be stored in any suitable article of manufacture that includes one or more tangible, computer-readable media at least collectively storing the instructions or routines, such as the memory20and the nonvolatile storage22. The memory20and the nonvolatile storage22may include any suitable articles of manufacture for storing data and executable instructions, such as random-access memory, read-only memory, rewritable flash memory, hard drives, and optical discs. Also, programs (e.g., an operating system) encoded on such a computer program product may also include instructions that may be executed by the processor(s)18.

In one embodiment, the display12may be a touch-screen liquid crystal display (LCD), for example, which may enable users to interact with a user interface of the electronic device10. In another embodiment, the display12may be an organic light emitting diode (OLED) display. In some embodiments, the electronic display12may be a MultiTouch™ display that can detect multiple touches at once.

The input structures16of the electronic device10may enable a user to interact with the electronic device10(e.g., pressing a button to increase or decrease a volume level). The I/O ports14may enable electronic device10to interface with various other electronic devices, as may the expansion card24and/or the RF circuitry26. The expansion card24and/or the RF circuitry26may include, for example, interfaces for a personal area network (PAN), such as a Bluetooth network, for a local area network (LAN), such as an 802.11x Wi-Fi network, and/or for a wide area network (WAN), such as a 3G or 4G cellular network. The power source28of the electronic device10may be any suitable source of power, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.

As mentioned above, the electronic device10may take the form of a computer or other type of electronic device. Such computers may include computers that are generally portable (such as laptop, notebook, and tablet computers) as well as computers that are generally used in one place (such as conventional desktop computers, workstations and/or servers).FIG. 2depicts a front view of a handheld device10A, which represents one embodiment of the electronic device10. The handheld device10A may represent, for example, a portable phone, a media player, a personal data organizer, a handheld game platform, or any combination of such devices. By way of example, the handheld device10A may be a model of an iPod® or iPhone® available from Apple Inc. of Cupertino, Calif.

The handheld device10A may include an enclosure32to protect interior components from physical damage and to shield them from electromagnetic interference. The enclosure32may surround the display12, which may include a screen34for displaying icons36. The screen34may also display indicator icons38to indicate, among other things, a cellular signal strength, Bluetooth connection, and/or battery life. The I/O ports14may open through the enclosure32and may include, for example, a proprietary I/O port from Apple Inc. to connect to external devices.

User input structures16, in combination with the display12, may allow a user to control the handheld device10A. For example, the input structures16may activate or deactivate the handheld device10A, navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, activate a voice-recognition feature of the handheld device10A, provide volume control, and toggle between vibrate and ring modes. The electronic device10may also be a tablet device10B, as illustrated inFIG. 3. For example, the tablet device10B may be a model of an iPad® available from Apple Inc.

In certain embodiments, the electronic device10may take the form of a computer, such as a model of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, or Mac Pro® available from Apple Inc. By way of example, the electronic device10, taking the form of a notebook computer10C, is illustrated inFIG. 4in accordance with one embodiment of the present disclosure. The depicted computer10C may include a housing32, a display12, I/O ports14, and input structures16. In one embodiment, the input structures16(such as a keyboard and/or touchpad) may be used to interact with the computer10C, such as to start, control, or operate a GUI or applications running on computer10C. For example, a keyboard and/or touchpad may allow a user to navigate a user interface or application interface displayed on the display12.

An electronic device10, such as the devices10A,10B, and10C discussed above, may be configured to reduce the power consumed by the display12, such as by reducing power consumed by a demultiplexer of the display12.FIG. 5illustrates pixel-driving circuitry that may be found in the display12and may be configured for such operation. In certain embodiments, the pixel-driving circuitry depicted inFIG. 5may be embodied on a liquid crystal display (LCD) panel42of the display12. The pixel-driving circuitry includes an array or matrix54of unit pixels60that are driven by data (or source) line driving circuitry56and scanning (or gate) line driving circuitry58. The matrix54of unit pixels60may form an image display region of the display12. In such a matrix, each unit pixel60may be defined by the intersection of data lines62and scanning lines64, which may also be referred to as source lines62and gate (or video scan) lines64. The data line driving circuitry56may include one or more driver integrated circuits (also referred to as column drivers) for driving the data lines62. The scanning line driving circuitry58may also include one or more driver integrated circuits (also referred to as row drivers).

Each unit pixel60includes a pixel electrode66and a thin film transistor (TFT)68for switching access to the pixel electrode66. In the depicted embodiment, a source70of each TFT68is electrically connected to a data line62extending from respective data line driving circuitry56, and a drain72is electrically connected to the pixel electrode66. Similarly, in the depicted embodiment, a gate74of each TFT68is electrically connected to a scanning line64extending from respective scanning line driving circuitry58.

In one embodiment, column drivers of the data line driving circuitry56send image signals to the pixels via the respective data lines62. Such image signals may be applied by line-sequence, i.e., the data lines62may be sequentially activated during operation. The scanning lines64may apply scanning signals from the scanning line driving circuitry58to the gate74of each TFT68. Such scanning signals may be applied by line-sequence with a predetermined timing or in a pulsed manner

Each TFT68serves as a switching element which may be activated and deactivated (i.e., turned on and off) for a predetermined period based on the respective presence or absence of a scanning signal at its gate74. When activated, a TFT68may store the image signals received via a respective data line62as a charge in the pixel electrode66with a predetermined timing.

The image signals stored at the pixel electrode66may be used to generate an electrical field between the respective pixel electrode66and a common electrode (VCOM)76. Such an electrical field may align liquid crystals within a liquid crystal layer to modulate light transmission through the LCD panel42. Unit pixels60may operate in conjunction with various color filters, such as red, green, and blue filters. In such embodiments, a “pixel” of the display may actually include multiple unit pixels, such as a red unit pixel, a green unit pixel, and a blue unit pixel, each of which may be modulated to increase or decrease the amount of light emitted to enable the display to render numerous colors via additive mixing of the colors.

In some embodiments, a storage capacitor may also be provided in parallel to the liquid crystal capacitor formed between the pixel electrode66and the common electrode to prevent leakage of the stored image signal at the pixel electrode66. For example, such a storage capacitor may be provided between the drain72of the respective TFT68and a separate capacitor line.

Additional components that may be used to provide image signals to the LCD panel42are depicted inFIG. 6. In the illustrated embodiment, a demultiplexer76is electrically coupled between the data line driving circuitry56and the array of unit pixels54. The demultiplexer76enables the data line driving circuitry56to include fewer outputs than the total number of data lines62. For example, the demultiplexer76may enable a ratio of data line driving circuitry56outputs to data lines62of 1 to 2, 1 to 3, 1 to 4, and so forth. Specifically, in the illustrated embodiment, the ratio of data line driving circuitry56outputs to data lines62is 1 to 3. Accordingly, the demultiplexer76receives data from a data line driver A78output from the data line driving circuitry56and demultiplexes the data onto data lines62A,62B, and62C. Furthermore, the demultiplexer76receives data from a data line driver B80output from the data line driving circuitry56and demultiplexes the data onto data lines62D,62E, and62F. As may be appreciated, the demultiplexer76may be controlled by various control signals to facilitate demultiplexing. In certain embodiments, the control signals may be used to activate and deactivate gates of TFTs used to provide data from the data line drivers A78and B80to the data lines62. For example, an activation line A82, an activation line B84, and an activation line C86may be controlled by the data line driving circuitry56to activate and deactivate gates of TFTs of the demultiplexer76. While the demultiplexer76is illustrated as being separate from the data line driving circuitry56, in certain embodiments, the demultiplexer76may be part of the data line driving circuitry56. Furthermore, while the demultiplexer76is illustrated as being part of an LCD panel42, in other embodiments, the demultiplexer76may be part of an OLED display, or any other suitable electronic device.

Circuitry of the demultiplexer76may be arranged in a variety of ways.FIG. 7illustrates one embodiment of circuitry of the demultiplexer76. As illustrated, the demultiplexer76includes TFTs88that are used to switch provide from the data line drivers A78and B80to the data lines62. The TFTs88may be any suitable TFTs, such as n-type TFTs, p-type TFTs, CMOS TFTs, and so forth. Moreover, in certain embodiments, the demultiplexer76may include any suitable switching device in place of the TFTs88.

As may be appreciated, the output of the demultiplexer76may be determined based on which gates90of the TFTs88are activated. Specifically, during operation of the LCD panel42, the data line driving circuitry56may drive the activation line A82to activate gate90A of TFT88A and to activate gate90D of TFT88D. With the gate90A activated, data may be provided from the data line driver A78to the data line62A. Moreover, with the gate90D activated, data may be provided from the data line driver B80to the data line62D.

Furthermore, the data line driving circuitry56may drive the activation line B84to activate gate90B of TFT88B and to activate gate90E of TFT88E. With the gate90B activated, data may be provided from the data line driver A78to the data line62B. Moreover, with the gate90E activated, data may be provided from the data line driver B80to the data line62E.

Similarly, the data line driving circuitry56may drive the activation line C86to activate gate90C of TFT88C and to activate gate90F of TFT88F. With the gate90C activated, data may be provided from the data line driver A78to the data line62C. Moreover, with the gate90F activated, data may be provided from the data line driver B80to the data line62F. As may be appreciated, during operation only one of the gates90A,90B, and90C may be activated at a time to properly demultiplex the data from the data line driver A78to the data lines62A,62B, and62C. Furthermore, only one of the gates90D,90E, and90F may be activated at a time to properly demultiplex the data from the data line driver B80to the data lines62D,62E, and62F.

Total power consumption of the demultiplexer76may be calculated using the following formula: P=N*C*V^2*F. In this equation, P corresponds to a total power consumption of the demultiplexer76, N corresponds to a number of demultiplexer76control lines (e.g., activation lines), C corresponds to the total capacitance of one demultiplexer76control line, V corresponds to a voltage swing of the voltage provided on the control lines (e.g., 15 to 20 volts), and F corresponds to a frequency calculated by a frame rate multiplied by a number of vertical lines.

As may be appreciated, power may be consumed by charging a capacitance of the gates90while the gates90are being activated. Accordingly, by decreasing the amount of power needed to charge the capacitance of the gates90, the total power consumption of the demultiplexer76may be reduced. For example, in certain embodiments, the power consumption of the demultiplexer76may be reduced by approximately 50%. In such an embodiment, the power consumption of the demultiplexer76may be determined by using the following formula: P=N*C*V^2*F/2. Moreover,FIG. 8illustrates an embodiment of an LCD panel42that includes circuitry to facilitate reduced power consumption of the demultiplexer76.

As illustrated, the data line driving circuitry56includes gate driving circuitry92for activating the gates90of the TFTs88. The activation line A82is electrically coupled between the gate driving circuitry92and the gate90A to carry signals for driving the gate90A. Moreover, a switch A94is electrically coupled between the gate driving circuitry92and the gate90A. The switch A94is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the gate driving circuitry92and the gate90A, respectively.

Furthermore, the activation line B84is electrically coupled between the gate driving circuitry92and the gate90B to carry signals for driving the gate90B. Moreover, a switch B96is electrically coupled between the gate driving circuitry92and the gate90B. The switch B96is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect and disconnect the gate driving circuitry92and the gate90B, respectively.

In addition, the activation line C86is electrically coupled between the gate driving circuitry92and the gate90C to carry signals for driving the gate90C. Moreover, a switch C98is electrically coupled between the gate driving circuitry92and the gate90C. The switch C98is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect and disconnect the gate driving circuitry92and the gate90C, respectively.

The data line driving circuitry56also includes a switch AB100electrically coupled between the gate90A and the gate90B. The switch AB100is controlled by the data line driving circuitry56to a closed position to establish a connection102(e.g., make the connection102, connect) between the gate90A and the gate90B. Moreover, the switch AB100is controlled by the data line driving circuitry56to an open position to disconnect (e.g., break the connection102) the gate90A from the gate90B.

Furthermore, the data line driving circuitry56also includes a switch BC104electrically coupled between the gate90B and the gate90C. The switch BC104is controlled by the data line driving circuitry56to a closed position to establish a connection106(e.g., make the connection106, connect) between the gate90B and the gate90C. Moreover, the switch BC104is controlled by the data line driving circuitry56to an open position to disconnect (e.g., break the connection106) the gate90B from the gate90C.

In addition, the data line driving circuitry56also includes a switch AC108electrically coupled between the gate90A and the gate90C. The switch AC108is controlled by the data line driving circuitry56to a closed position to establish a connection110(e.g., make the connection110, connect) between the gate90A and the gate90C. Moreover, the switch AC108is controlled by the data line driving circuitry56to an open position to disconnect (e.g., break the connection110) the gate90A from the gate90C. The switches94,96,98,100,104, and108may be any suitable switching device (e.g., transistor). As may be appreciated, although the switches94,96,98,100,104, and108are described as being part of the data line driving circuitry56, the switches may not be part of the data line driving circuitry56. Moreover, the switches94,96,98,100,104, and108may be controlled by any suitable control circuitry.

The switches AB100, BC104, and AC108may be used to share a charge stored on one of the gates90with another gate. Accordingly,FIG. 9illustrates a timing diagram112that shows one embodiment for operating the data line driving circuitry56in conjunction with the demultiplexer76. Specifically, at a time114, the switch A94, the switch B96, and the switch C98all transition from an open position to a closed position where they remain until a time116. Furthermore, between times114and116, the switches AB100, BC104, and AC108are all open. Moreover, the activation line A82is driven to a logic high voltage to activate the gate90A. In addition, the activation lines B84and C86are driven to a logic low voltage so that the gates90B and90C are not activated. With the gate90A active, data provided by the data line driver A78is provided to the data line62A. For example, data for a red pixel may be provided between the time114and the time116.

At the time116, the switch A94and the switch B96transition from the closed position to the open position where they remain until a time118. Furthermore, between times116and118, the switches BC104and AC108are open, while the switch AB100is closed. With the switch AB100closed, the gate90A is electrically coupled to the gate90B. Moreover, the charge stored by the gate90A is shared with the gate90B, such that gate90A and the gate90B may have approximately the same charge. For example, each of gates90A and90B may be charged with approximately half of the charge needed to drive the gates90A and90B (e.g., the charge of the gate90A is shared with the gate90B). Accordingly, the activation lines A82and B84may be driven to a voltage between a logic low voltage and a logic high voltage (e.g., midway point) where the gates90A and90B are not activated. The activation line C86is driven to a logic low voltage so that the gate90C is not activated. Because none of the gates90A,90B, and90C are activated, data provided by the data line driver A78is not provided to one of the data lines62.

At the time118, the switch A94and the switch B96transition from the open position to the closed position where they remain until a time120. Furthermore, between times118and120, the switches AB100, BC104, and AC108are all open. Moreover, the activation line B84is driven to a logic high voltage to activate the gate90B. Because of the charge sharing from the gate90A, the voltage applied to the activation line B84changes from the midway point to the logic high voltage rather than changing from the logic low voltage to the logic high voltage. Therefore, the voltage swing used to drive the gate90B is reduced. In certain embodiments, the voltage swing to drive the gate90B may be reduced by approximately 50% (e.g., reduced in half). Moreover, in some embodiments, the charge sharing between the gates90A and90B may reduce power for driving the activation line B84by approximately 50%. In other embodiments, the charge sharing between the gates90A and90B may reduce power for driving the activation line B84by a factor of four. Accordingly, the power consumption of the demultiplexer76may be reduced, thereby reducing power consumption of the display12. The activation lines A82and C86are driven to a logic low voltage so that the gates90A and90C are not activated. With the gate90B active, data provided by the data line driver A78is provided to the data line62B. For example, data for a green pixel may be provided between the time118and the time120.

At the time120, the switch B96and the switch C98transition from the closed position to the open position where they remain until a time122. Furthermore, between times120and122, the switches AB100and AC108are open, while the switch BC104is closed. With the switch BC104closed, the gate90B is electrically coupled to the gate90C. Moreover, the charge stored by the gate90B is shared with the gate90C, such that gate90B and the gate90C may have approximately the same charge. For example, each of gates90B and90C may be charged with approximately half of the charge needed to drive the gates90B and90C (e.g., the charge of the gate90B is shared with the gate90C). Accordingly, the activation lines B84and C86may be driven to a voltage between a logic low voltage and a logic high voltage (e.g., midway point) where the gates90B and90C are not activated. The activation line A82is driven to a logic low voltage so that the gate90A is not activated. Because none of the gates90A,90B, and90C are activated, data provided by the data line driver A78is not provided to one of the data lines62.

At the time122, the switch B96and the switch C98transition from the open position to the closed position where they remain until a time124. Furthermore, between times122and124, the switches AB100, BC104, and AC108are all open. Moreover, the activation line C86is driven to a logic high voltage to activate the gate90C. Because of the charge sharing from the gate90B, the voltage applied to the activation line C86changes from the midway point to the logic high voltage rather than changing from the logic low voltage to the logic high voltage. Therefore, the voltage swing used to drive the gate90C is reduced. In certain embodiments, the voltage swing to drive the gate90C may be reduced by approximately 50% (e.g., reduced in half). Moreover, in some embodiments, the charge sharing between the gates90B and90C may reduce power for driving the activation line C86by approximately 50%. In other embodiments, the charge sharing between the gates90B and90C may reduce power for driving the activation line C86by a factor of four. Accordingly, the power consumption of the demultiplexer76may be reduced, thereby reducing power consumption of the display12. The activation lines A82and B84are driven to a logic low voltage so that the gates90A and90B are not activated. With the gate90C active, data provided by the data line driver A78is provided to the data line62C. For example, data for a blue pixel may be provided between the time122and the time124.

At the time124, the switch A94and the switch C98transition from the closed position to the open position where they remain until a time126. Furthermore, between times124and126, the switches AB100and BC104are open, while the switch AC108is closed. With the switch AC108closed, the gate90C is electrically coupled to the gate90A. Moreover, the charge stored by the gate90C is shared with the gate90A, such that gate90C and the gate90A may have approximately the same charge. For example, each of gates90C and90A may be charged with approximately half of the charge needed to drive the gates90C and90A (e.g., the charge of the gate90C is shared with the gate90A). Accordingly, the activation lines C86and A82may be driven to a voltage between a logic low voltage and a logic high voltage (e.g., midway point) where the gates90C and90A are not activated. The activation line B84is driven to a logic low voltage so that the gate90B is not activated. Because none of the gates90A,90B, and90C are activated, data provided by the data line driver A78is not provided to one of the data lines62.

The pattern described between times114and126then repeats throughout operation, such that signals between times126and128are similar to the signals between times114and116, signals between times128and130are similar to the signals between times116and118, signals between times130and132are similar to the signals between times118and120, and so forth. As illustrated, the switch A94may remain closed while the switch BC104is closed, the switch B96may remain closed while the switch AC108is closed, and the switch C98may remain closed while the switch AB100is closed. However, in other embodiments, the switch A94may be open while the switch BC104is closed, the switch B96may be open while the switch AC108is closed, and the switch

C98may be open while the switch AB100is closed.

As may be appreciated, circuitry of the LCD panel42may be configured in a variety of ways to reduce power consumption of the demultiplexer76. For example,FIG. 10illustrates another embodiment of an LCD panel42that includes circuitry to facilitate reduced power consumption of the demultiplexer76.

As illustrated, the data line driving circuitry56includes the gate driving circuitry92for activating the gates90of the TFTs88. The gate driving circuitry92includes a high gate output voltage (VGH)134which may be used to activate the gates90. For example, in certain embodiments, the voltage of VGH134may be somewhere between approximately 5 to 20 volts, 5 to 10 volts, or 10 to 25 volts. The gate driving circuitry92also includes a low gate output voltage (VGL)136which may be used to deactivate the gates90. For example, in certain embodiments, the voltage of VGL136may be approximately 0 volts.

The activation line A82is electrically coupled between the VGH134of the gate driving circuitry92and the gate90A to carry signals for activating the gate90A. Moreover, a switch SWH_A138is electrically coupled between the VGH134and a segment A139of the activation line A82. The switch SWH_A138is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the VGH134and the segment A139, respectively.

Furthermore, the activation line B84is electrically coupled between the VGH134of the gate driving circuitry92and the gate90B to carry signals for activating the gate90B. Moreover, a switch SWH_B140is electrically coupled between the VGH134and a segment B141of the activation line B84. The switch SWH_B140is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the VGH134and the segment B141, respectively.

In addition, the activation line C86is electrically coupled between the VGH134of the gate driving circuitry92and the gate90C to carry signals for activating the gate90C. Moreover, a switch SWH_C142is electrically coupled between the VGH134and a segment C143of the activation line C86. The switch SWH_C142is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the VGH134and the segment C143, respectively.

A switch SWL_A144is electrically coupled between the VGL136and the segment A139. The switch SWL_A144is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the VGL136and the segment A139, respectively. Furthermore, a switch SWL_B146is electrically coupled between the VGL136and the segment B141. The switch SWL_B146is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the VGL136and the segment B141, respectively. In addition, a switch SWL_C148is electrically coupled between the VGL136and the segment C143. The switch SWL_C148is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the VGL136and the segment C143, respectively.

Moreover, a switch SWG_A150is electrically coupled between the segment A139and the gate90A. The switch SWG_A150is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the segment A139and the gate90A, respectively. Furthermore, a switch SWG_B152is electrically coupled between the segment B141and the gate90B. The switch SWG_B152is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the segment B141and the gate90B, respectively. In addition, a switch SWG_C154is electrically coupled between the segment C143and the gate90C. The switch SWG_C154is controlled to a closed position and to an open position by the data line driving circuitry56to electrically connect (e.g., make) and disconnect (e.g., break) the segment C143and the gate90C, respectively.

The data line driving circuitry56also includes a switch SWI_A156configured to be electrically coupled between the gate90A and another gate. The switch SWI_A156is controlled by the data line driving circuitry56to a closed position to establish a connection158(e.g., make the connection158, connect) between the gate90A and another gate. Moreover, the switch SWI_A156is controlled by the data line driving circuitry56to an open position to disconnect (e.g., break the connection158) the gate90A from another gate.

Furthermore, the data line driving circuitry56also includes a switch SWI_B160electrically coupled between the gate90B and the gate90C. The switch SWI_B160is controlled by the data line driving circuitry56to a closed position to establish a connection162(e.g., make the connection162, connect) between the gate90A and the gate90B. Moreover, the switch SWI_B160is controlled by the data line driving circuitry56to an open position to disconnect (e.g., break the connection162) the gate90A from the gate90B.

In addition, the data line driving circuitry56also includes a switch SWIC164electrically coupled between the gate90B and the gate90C. The switch SWI_C164is controlled by the data line driving circuitry56to a closed position to establish a connection166(e.g., make the connection166, connect) between the gate90B and the gate90C. Moreover, the switch SWI_C164is controlled by the data line driving circuitry56to an open position to disconnect (e.g., break the connection166) the gate90B from the gate90C. The switches138,140,142,144,146,148,150,152,154,156,160, and164may be any suitable switching device (e.g., transistor). As may be appreciated, although the switches138,140,142,144,146,148,150,152,154,156,160, and164are described as being part of the data line driving circuitry56, the switches may not be part of the data line driving circuitry56. Moreover, the switches138,140,142,144,146,148,150,152,154,156,160, and164may be controlled by any suitable control circuitry. In certain embodiments, fewer or more switches may be used.

The switches SWI_A156, SWI_B160, and SWI_C164may be used to share a charge stored on one of the gates90with another gate. Accordingly,FIG. 11illustrates a timing diagram170that shows one embodiment for operating the data line driving circuitry56in conjunction with the demultiplexer76. Specifically, at a time172, the switch SWG_A150transitions from a closed position to an open position where it remains until a time174. The switch SWI_A156transitions from an open position to a closed position where it remains until the time174. Furthermore, between times172and174, the switches SWH_A138, SWH_B140, SWH_C142, SWI_B160, and SWI_C164are all open, while the switches SWL_A144, SWL_B146, SWL_C148, SWG_B160, and SWG_C164are all closed. Moreover, the activation line A82shares a voltage with another activation line connected to the activation line A82by the switch SWI_A156. In addition, the activation lines B84and C86are driven to a logic low voltage so that the gates90B and90C are not activated.

At the time174, the switches SWH_A138and SWG_A150transition from an open position to a closed position where they remain until a time176. The switches SWL_A144and SWI_A156transition from a closed position to an open position where they remain until the time176. Furthermore, between times174and176, the switches SWH_B140, SWH_C142, SWI_B160, and SWI_C164are all open, while the switches SWL_B146, SWL_C148, SWG_B160, and SWG_C164are all closed. Moreover, the activation line A82is driven to a logic high voltage to activate the gate90A. In addition, the activation lines B84and C86are driven to a logic low voltage so that the gates90B and90C are not activated. With the gate90A active, data provided by the data line driver A78is provided to the data line62A. For example, data for a red pixel may be provided between the time174and the time176.

At the time176, the switches SWG_A150and SWG_B152transition from a closed position to an open position where they remain until a time178. The switch SWI_B160transitions from an open position to a closed position where it remains until the time178. Furthermore, between times176and178, the switches SWH_B140, SWH_C142, SWL_A144, SWI_A156, and SWI_C164are all open, while the switches SWH_A138, SWL_B146, SWL_C148, and SWG_C164are all closed. With the switch SWI_B160closed, the gate90A is electrically coupled to the gate90B. Moreover, the charge stored by the gate90A is shared with the gate90B, such that gate90A and the gate90B may have approximately the same charge. For example, each of gates90A and90B may be charged with approximately half of the charge needed to drive the gates90A and90B (e.g., the charge of the gate90A is shared with the gate90B). Accordingly, the activation lines A82and B84may be driven to a voltage between a logic low voltage and a logic high voltage (e.g., midway point) where the gates90A and90B are not activated. The activation line C86is driven to a logic low voltage so that the gate90C is not activated. Because none of the gates90A,90B, and90C are activated, data provided by the data line driver A78is not provided to one of the data lines62.

At the time178, the switches SWH_B140, SWL_A144, SWG_A150, and SWG_B152transition from an open position to a closed position where they remain until a time180. The switches SWH_A138, SWL_B146, and SWI_B160transition from a closed position to an open position where they remain until the time180. Furthermore, between times178and180, the switches SWH_C142, SWI_A156, and SWI_C164are all open, while the switches SWL_C148and SWG_C164are all closed. Moreover, the activation line B84is driven to a logic high voltage to activate the gate90B. Because of the charge sharing from the gate90A, the voltage applied to the activation line B84changes from the midway point to the logic high voltage rather than changing from the logic low voltage to the logic high voltage. Therefore, the voltage swing used to drive the gate90B is reduced. In certain embodiments, the voltage swing to drive the gate90B may be reduced by approximately 50% (e.g., reduced in half).

Moreover, in some embodiments, the charge sharing between the gates90A and90B may reduce power for driving the activation line B84by approximately 50%. In other embodiments, the charge sharing between the gates90A and90B may reduce power for driving the activation line B84by a factor of four. Accordingly, the power consumption of the demultiplexer76may be reduced, thereby reducing power consumption of the display12. The activation lines A82and C86are driven to a logic low voltage so that the gates90A and90C are not activated. With the gate90B active, data provided by the data line driver A78is provided to the data line62B. For example, data for a green pixel may be provided between the time178and the time180.

At the time180, the switches SWG_B152and SWG_C154transition from a closed position to an open position where they remain until a time182. The switch SWI_C164transitions from an open position to a closed position where it remains until the time182. Furthermore, between times180and182, the switches SWH_A138, SWH_C142, SWL_B146, SWI_A156, and SWI_B160are all open, while the switches SWH_B140, SWL_A144, SWL_C148, and SWG_A150are all closed. With the switch SWI_C164closed, the gate90B is electrically coupled to the gate90C. Moreover, the charge stored by the gate90B is shared with the gate90C, such that gate90B and the gate90C may have approximately the same charge. For example, each of gates90B and90C may be charged with approximately half of the charge needed to drive the gates90B and90C (e.g., the charge of the gate90B is shared with the gate90C). Accordingly, the activation lines B84and C86may be driven to a voltage between a logic low voltage and a logic high voltage (e.g., midway point) where the gates90B and90C are not activated. The activation line A82is driven to a logic low voltage so that the gate90A is not activated. Because none of the gates90A,90B, and90C are activated, data provided by the data line driver A78is not provided to one of the data lines62.

At the time182, the switches SWH_C142, SWL_B146, SWG_B152, and SWG_C154transition from an open position to a closed position where they remain until a time184. The switches SWH_B140, SWL_C148, and SWI_C164transition from a closed position to an open position where they remain until the time184. Furthermore, between times182and184, the switches SWH_A138, SWI_A156, and SWI_B160are all open, while the switches SWL_A144and SWG_A150are all closed. Moreover, the activation line C86is driven to a logic high voltage to activate the gate90C. Because of the charge sharing from the gate90B, the voltage applied to the activation line C86changes from the midway point to the logic high voltage rather than changing from the logic low voltage to the logic high voltage. Therefore, the voltage swing used to drive the gate90C is reduced.

In certain embodiments, the voltage swing to drive the gate90C may be reduced by approximately 50% (e.g., reduced in half). Moreover, in some embodiments, the charge sharing between the gates90B and90C may reduce power for driving the activation line C86by approximately 50%. In other embodiments, the charge sharing between the gates90B and90C may reduce power for driving the activation line C86by a factor of four. Accordingly, the power consumption of the demultiplexer76may be reduced, thereby reducing power consumption of the display12. The activation lines A82and B84are driven to a logic low voltage so that the gates90A and90B are not activated. With the gate90C active, data provided by the data line driver A78is provided to the data line62C. For example, data for a blue pixel may be provided between the time182and the time184. The pattern described between times172and184then repeats throughout operation.

By sharing a charge from a gate of one transistor with a gate of another transistor, power used to activate the gates may be reduced. Accordingly, using such techniques power consumption of the demultiplexer76may be reduced, thereby reducing power consumption of an electronic device10having the demultiplexer76. It should be noted that even though the embodiments described herein have been generally described as sharing charges between gates of TFTs of a demultiplexer, the techniques, methods, and devices described herein may also be applied to sharing charges between gates of TFTs of any suitable electronic component or device.