Method for forming an ESD protection circuit

An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to electronic circuits, and in particular to silicon controlled rectifier (SCR) structures for electrostatic discharge protection (ESD). More particularly this invention relates to polycrystalline silicon (polysilicon) bounded SCR structures and to electronic protection circuits employing polycrystalline silicon bounded SCR's.

2. Description of Related Art

In ESD protection circuits, the series resistance of the active devices affects the performance of the devices. Higher resistance at the voltage levels of an ESD event may lead to a voltage drop across the active devices that may destroy the device.FIG. 1shows an ESD protection diode structure of the prior art. In this example, shallow trenches are etched within the region that will become the N-well10and filled with an insulating material to form the shallow trench isolation (STI)15are formed on the substrate. A semiconductor material that is lightly doped with a p-type impurity is formed on the substrate to construct the P-well5. Within the P-well5, a lightly doped n-type impurity is diffused into the P-well5to form the N-well10. Between two of the STI regions15a P-type material is diffused into the N-well until a heavily doped P+region20is formed. Similarly, between two other STI regions15an N-type material is diffused into the N-well until a heavily doped N+region25is formed. An insulative layer40is formed on the surface of the substrate and opening32and37are created over the P+region20and the N+region25. Silicides30and35are respectively formed on the surfaces of the P+region20and N+region25to create the necessary contacts to external circuitry. In the case of the ESD protection diodes shown, the contacts will be to the signal input/output interface connection pads and the power supply voltage source connection pads.

According to U.S. Pat. No. 5,629,544 (Voldman, et al.—544), diode series resistance is largely determined by the dimensions of the diode features, the resistivity of N-well10in which diode is located, the distance current flows in N-well10and the depth of the current path, and by the resistance of contacts30and35to the p+ and n+ diffusions20and25. Thus, a wider diode with a lower well resistivity, a shorter current path, and silicided films and contacts provide a lower diode series resistance. In the case of the diode as shown, the depth of the current path is determined by the depth of the STI regions15. Further, it is known in the art that the width of the STI regions15have certain achievable minimums that cause the series resistance to be larger than desired.

Voldman, et al.—544 and “Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined And Polysilicon-Bound Source/Drain Diodes For ESD Networks,” Voldman, et al., Proceedings Electrical Overstress/Electrostatic Discharge Symposium, October 1998, pp: 151-160 discusses polysilicon-bounded diode. Refer toFIG. 2for more discussion of the structure of a polysilicon bounded diode. The structure of the polysilicon bounded diode is constructed in a P-type well5that has been created with a substrate has been lightly doped with a p-type impurity. Within the P-well5a lightly doped n-type impurity is diffused into the P-well5to form the N-well10. An insulative layer40is formed on the surface of the substrate. A gate stack is formed with a gate oxide layer60and a polysilicon layer65. Spacers70are added to the sides of the gate oxide layer60and the polysilicon layer65. A P-type material is diffused into the N-well until a heavily doped P+region75is formed and an N-type material is diffused into the N-well until a heavily doped N+region80is formed on each side of the gate stack. Openings77and82are created over the P+region75and the N+region80. Silicides90and95are respectively formed on the surfaces of the P+region75and N+region80to create the necessary contacts to external circuitry. As described above, the contacts will be to the signal input/output interface connection pads and the power supply voltage source connection pads.

In the polysilicon bounded diode as shown, the gate stack maybe constructed with smaller dimensions than those permitted in the diode constructed with the STI15ofFIG. 1. This permits the series resistance of the diode to be lower to and thus improves the operation of the diode during an ESD event.

Use of silicon controlled rectifiers (SCR) as ESD protection devices are well known in the art. Referring toFIG. 3, the P-well100is constructed of a semiconductor material that is lightly doped with a p-type impurity is diffused into a substrate. Within the P-well100a lightly doped n-type impurity is diffused into the P-well100to form the N-well105. Shallow trenches are then etched within the region of the N-well105and filled with an insulating material to form the shallow trench isolation (STI)110. Between two of the STI regions110a P-type material is diffused into the N-well until a heavily doped P+regions125and135are formed. Similarly, between two other STI regions110an N-type material is diffused into the N-well until the heavily doped N+regions120and130are formed. An insulative layer140is formed on the surface of the substrate and openings127and137are created over the P+regions125and135and openings122and132are created over the N+regions120and130. Silicides145,150,155, and160are formed on the surfaces of the P+regions125and135and N+regions120and130to create the necessary contacts to external circuitry. The contacts will be to the signal input/output interface connection pads and the power supply voltage source connection pads.

The SCR is formed of the P+regions125, the N-well105, the P-well105and the N+regions130. The anode of the SCR being the P+regions125and the cathode N+regions130. As structured, a positive voltage of an ESD event applied to the anode will cause the SCR to be activated once the snapback voltage is reached. In general the snapback voltage as shown is greater than 50V and may not cause damage to connected integrated circuits. However, as the feature sizes of integrated circuits have become smaller, the voltages at which damage may occur is becoming smaller and the SCR needs to be triggered at lower voltages that are greater than the operating voltages of the integrated circuits.

“Electrostatic Discharge (ESD) Protection in Silicon-On-Insulator (SOI) CMOS Technology with Aluminum and Copper Interconnects in Advanced Microprocessor Semiconductor Chips,” Voldman, et al., Proceedings Electrical Overstress/Electrostatic Discharge Symposium, 1999, pp: 105-115, discusses the electrostatic discharge (ESD) robustness of silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes.

“An ESD Protection Scheme for Deep Sub-Micron ULSI Circuits,” Sharma, et al. Digest of Technical Papers—1995 Symposium on VLSI Technology, 1995, pp: 85-86, describes a scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using low voltage zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET.

U.S. Pat. No. 6,605,493 (Yu) teaches about an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of suicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

U.S. Pat. No. 6,580,184 (Song) illustrates an ESD protection circuit having a silicon-controlled rectifier structure. A switch circuit is connected between a ground voltage terminal and a well region that is a base of the PNP transistor. The switch circuit is formed of plural diode-coupled MOS transistors, so that a trigger voltage of the SCR is determined by threshold voltages of the MOS transistors.

U.S. Pat. No. 6,534,834 (Ashton, et al.) teaches about a snapback device that functions as a semiconductor protection circuit to prevent damage to integrated circuits resulting from events such as electrostatic discharge. The snapback device includes a polysilicon film overlapping the active area.

U.S. Pat. No. 5,453,384 (Chatterjee) describes a silicon controlled rectifier structure that is provided for electrostatic discharge protection. A polysilicon gate layer is formed over a gate insulator region and is electrically coupled to the input pad of an integrated circuit.

U.S. Pat. No. 5,159,518 (Roy) details an input protection circuit that protects MOS semiconductor circuits from electrostatic discharge voltages and from developing circuit latchup. The input protection circuit includes a low resistance input resistor, and two complementary true gated diodes.

U.S. Patent Application 2003/0016479 (Song) describes an ESD protection circuit having silicon-controlled rectifier structure that includes a PNP transistor and an NPN transistor. A switch circuit is connected between a ground voltage terminal and a well region that is a base of the PNP transistor. The switch circuit is formed of plural diode-coupled MOS transistors, so that a trigger voltage of the SCR is determined by threshold voltages of the MOS transistors.

SUMMARY OF THE INVENTION

An object of this invention is to provide an ESD protection circuit that becomes activated at a voltage sufficient to protect integrated circuits connected to the protection circuit.

Another object of this invention is to provide an ESD protection circuit with a polysilicon bounded SCR that conducts of applied energy resulting from an ESD event to an input/output interface connection pad.

Still another object of this invention is to provide a bias triggering circuit for an SCR that causes the SCR to turn on at a lower voltage in order to conduct the energy of an ESD event.

A further object of this invention is to provide a diode bias triggering circuit for an SCR that causes the SCR to turn on at a lower voltage in order to conduct the energy of an ESD event.

One more object of this invention is to provide a resistor/capacitor triggering circuit for an SCR that causes the SCR to turn on at a lower voltage to conduct the energy of an ESD event.

To accomplish at least one of these objects, an ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR and a biasing circuit. The polysilicon bounded SCR is connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event.

The polysilicon bounded SCR includes a first well region lightly doped with impurities of a first conductivity type formed on the substrate and connected to the power supply connection and a second well region formed within the first well region and lightly doped with impurities of a second conductivity type. A first diffusion region is formed within the second well by heavily doping the region with the impurities of the first conductivity type. The first diffusion region is connected to the signal input/output interface contact. A second diffusion region is formed within the first well region at a second distance from the first diffusion region by heavily doping the region with impurities of the second conductivity type. The second diffusion region is connected to the power supply connection. A first heavily doped polycrystalline layer is formed at the surface of the substrate and placed between the first and second diffusion regions and astride a junction of the first well region and the second well region to form a bounding component to prevent silicide formation at junctions of the first diffusion region and the second well region, the first well region and the second region and the second diffusion region and the first well region during fabrication of the SCR.

The SCR being the junctions of the first diffusion region and the second well region, the junction of the first and second well regions, and the junction of the first well region and the second diffusion region. The anode of the SCR is the first well region and the cathode of the SCR is the second diffusion region.

The biasing circuit is formed of at least one polysilicon bounded diode formed on the substrate and connected between the signal input/output interface contact and an anode connection of the polysilicon bounded SCR to increase a holding voltage for the polysilicon bounded SCR when the polysilicon bounded SCR is turned on.

The polysilicon bounded diode is formed from the first diffusion region and the second well region and has a second heavily doped polysilicon layer formed at the surface of the substrate and placed adjacent to the first diffusion region and astride a junction of the second well region and first diffusion region to form a bounding component to prevent silicide formation at the junction of the first diffusion region and the second well region during fabrication of the polysilicon bounded diode. The junction of the first diffusion region and the second well region forms the polysilicon bounded diode.

The biasing circuit has a first resistance formed by material from the second well from a first gate of the polysilicon bounded SCR to a third diffusion region formed within the second well, heavily doped with the impurities of the second conductivity type, and connected to the power supply connection to provide a low resistance path to the second well from the power supply connection. The biasing circuit further has a second resistance formed material of the second well from the first gate to the first diffusion region.

A second embodiment of the biasing circuit includes a first resistor connected from the signal input/output interface contact to the first gate of the polysilicon bounded SCR and a first capacitor connected from the first gate of the polysilicon bounded SCR to the power supply connection. When an ESD event occurs, a top plate of the capacitor connected to the gate of the polysilicon bounded SCR is a virtual ground and the polysilicon bounded SCR is activated.

A third embodiment of the biasing circuit has a plurality of serially connected diodes. The first diode of the plurality of serially connected diodes is connected to the signal input/output interface contact and the last diode of the plurality of the serially connected diodes is connected to a second gate of the polysilicon bounded SCR. The biasing circuit further has a second resistor connected from the second gate and the last diode of the plurality of serially connected diodes to the power supply connection. When an ESD event occurs, a current flows through the plurality of serially connected diodes and the second resistor, which triggers the polysilicon bounded SCR to turn on.

A fourth embodiment of the biasing circuit: includes a resistor/capacitor biasing circuit connected from the first gate of the polysilicon bounded SCR and a diode triggering biasing circuit connected from the second gate of the polysilicon bounded SCR. The resistor/capacitor biasing circuit has a first resistor connected from the signal input/output interface to the first gate of the polysilicon bounded SCR and a first capacitor connected from the first gate of the polysilicon bounded SCR to the power supply connection. The diode triggering biasing circuit has a plurality of serially connected diodes. The first diode of the plurality of serially connected diodes is connected to the signal input/output interface contact and the last diode of the plurality of serially connected diodes is connected to a second gate of the polysilicon bounded SCR. The diode triggering biasing circuit has a second resistor connected from the second gate and the last diode of the plurality of serially connected diodes to the power supply connection.

When an ESD event occurs, the top plate of the capacitor connected to the gate of the polysilicon bounded SCR is a virtual ground and the polysilicon bounded SCR is activated. Simultaneously, a current flows through the plurality of serially connected diodes and the second resistor to trigger the polysilicon bounded SCR to turn on.

The heavily doped polycrystalline layer of the polysilicon bounded SCR and the polysilicon bounded diode permits a series resistance of the polysilicon bounded SCR and the polysilicon bound diode to be smaller for a more efficient operation. The heavily doped polycrystalline layer is connected to bias the heavily doped polysilicon layer such that salicide shorting is prevented the first and second diffusion regions and preventing of accidental formation of an inversion region heavily doped polycrystalline layer.

DETAILED DESCRIPTION OF THE INVENTION

The polysilicon bounded SCR of this invention as shown inFIGS. 4aand4bincludes a P-well200lightly doped with p-type impurities formed on the substrate and connected to the power supply connection280through the P+diffusion225. An N-well region205is formed within the P-well200and lightly doped with N-type impurities and connected through the N+diffusion region220to the power supply connection280. A P+diffusion region210is formed within the N-well205by heavily doping the N-well205with the P-type impurities. The P+diffusion region210is connected to the signal input/output interface contact275. An N+diffusion region215is formed within the P-well200at a second distance from the N+diffusion region210by heavily doping the P-well200with N-type impurities. The N+diffusion215is also connected to the power supply connection280.

An insulative material such as a silicon dioxide is formed on the surface of the substrate between the P+diffusion region210and the N+diffusion region215and astride a junction of the P-well200to form a gate oxide230. A polysilicon layer is then formed on the gate oxide230to form the gate structure240. The gate structure240forms a bounding component to prevent silicide formation at junctions of the P+diffusion region210and the N-well region205, the P-well200and the N-well region205and the N+diffusion region215and the P-well200during fabrication of the SCR.

As is known in the art, an SCR is regarded as a PNP transistor Q1connected serially with an NPN transistor Q2. Thus, the collector of the PNP transistor Q1is the P-well200, the base is the N-well205, and the emitter is the P+diffusion region210. The collector of the NPN transistor Q2is the N-well205, the base is the P-well200, and the emitter is the N+diffusion region215, with the junctions being the boundaries between the P+diffusion region210and the N-well region205, the P-well200and the N-well region205and the N+diffusion region215and the P-well200.

A N+diffusion region220is formed within the N-well205by heavily doping the N-well205with the N-type impurities and the P+diffusion region225is formed within the P-well200by heavily doping the P-well200with the P-type impurities. An insulation layer270is formed on the surface of the substrate to protect the surface. Openings227,217,212, and222are made in the insulation layer270to respectively provide access to the P+diffusion region225, N+diffusion region215, P+diffusion region210, and N+diffusion region220. A silicide contact265,255,250, and260is formed respectively on the surface of each of the P+diffusion region225, N+diffusion region215, P+diffusion region210, and N+diffusion region220. The silicide contacts255and250are restricted or bounded by the polysilicon gate structure240.

The diode D1is formed as the junction of the P+diffusion region210and the N-well205. The gate oxide235is formed between and slightly overlaps the P+diffusion region210and the N+diffusion region220. A polysilicon layer is formed on the gate oxide235to form the gate structure245. The gate structure245provides bounding for the suicide contacts250and260. The polysilicon bounding gate structures240and245permit the P+diffusion region210and N+diffusion region215to be placed relatively close by avoiding the necessity for a larger shallow trench isolation, thus minimizing the serial resistance of the diode D1and the SCR formed by the transistors Q1and Q2.

The gate structures240and245are connected to the power supply connection280to prevent salicide shorting between the silicide contacts265and250and silicide contacts250and260and preventing of accidental formation of an inversion region under said first and second diffusion regions. The silicide contacts265,255, and260provide low resistivity connections for the P+diffusion region225, N+diffusion region215, and N+diffusion region220to the power supply connection280. The silicide contact provides a low resistivity connection for the P+diffusion region210to the signal input/output interface pad275.

Refer now additionally toFIG. 5for a discussion of the circuit structure of the polysilicon bounded SCR having a diode triggering of this invention. As described above, the diode D1is formed as the junction of the P+diffusion region210and the N-well205. The polysilicon bounded SCR is formed of the P-well200, the N-well205, the P+diffusion region210, the N-well205, the P-well200, and the N+diffusion region215. The resistor R1-SUBis the bulk resistance of the N-well205to the P+diffusion region210. The resistor R2-SUBis the bulk resistance of the N-well205to the N+diffusion region220. And the resistor R3-SUBis the bulk resistance of the P-well200to the P+diffusion region225.

Upon application of the voltage of an ESD event to the input/output interface pad275, the diode D1begins to conduct. The current through the resistance R2-SUBdevelops sufficient voltage to turn on the transistor Q1, which in turn provides a current through the resistor R3-SUB. This develops a voltage sufficient to turn on the transistor Q2, thus completely activating the SCR.

Referring toFIG. 4c, as the voltage applied between the anode (P+diffusion region210) and the cathode (N+diffusion region215) of the Polysilicon bounded SCR increases the current rises slowly290until the biasing of the diode D1and the resistor R2-SUBturns on the SCR at the snapback point292. At the current and voltage level294the SCR fundamentally acts as a resistor, with the resistance determined by the internal resistance of the SCR. The internal resistance is then determined by the dimensions of the SCR and the proximity of the P+diffusion region210and the N+diffusion region215. The polysilicon gate structures240and245allow current to flow laterally between the P+diffusion region210and the N+diffusion region215more efficiently with a lower resistance to prevent ohmic heating of the device.

A second embodiment of the ESD protection circuit, as shown inFIG. 6is connected between the signal input/output interface pad275and the power supply connection pad280. The SCR is formed as described inFIGS. 4aand4b. The diodes D1and D2are optional diodes placed in series with the SCR between the signal input/output interface pad275and the SCR. These diodes are structured as the diode D1of theFIG. 4aand increase the holding voltage of the SCR when it is turned on. The base of the transistor Q1and the collector of the transistor Q2is the N-well205ofFIG. 4aand will be referred to as the first gate of the SCR. The base of the transistor Q2and the collector of the transistor Q1is the P-well200ofFIG. 4aand is referred to as the second gate of the SCR. The resistor R1is connected between the signal input/output interface pad275and the first gate. The capacitor C1is connected from the first gate to the power supply connection pad280. In this example the power supply connection pad280is the ground reference point for the integrated circuit.

The resistor RP-WELLis the bulk resistance of the P-well200ofFIG. 4aand is connected from the second gate of the SCR and the power supply connection pad280. The resistor R1is constructed using any known technique such as a highly doped diffusion region. The capacitance is constructed using any known technique such as employing a gate to bulk capacitance of a MOSFET as the capacitor C1.

When an ESD event285occurs, the voltage at the signal input/output interface pad285increases dramatically. The top plate of the capacitor C1at the first gate is at a virtual ground, thus causing the transistor Q1to turn on, which causes the current through the resistor RP-WELLto increase and turn on the transistor Q2. The SCR then transfers the energy to the power supply connection pad280.

A third embodiment of the ESD protection circuit, as shown inFIG. 7is connected between the signal input/output interface pad275and the power supply connection pad280. The SCR is formed as described inFIGS. 4aand4b. As described above, the base of the transistor Q1and the collector of the transistor Q2is the N-well205ofFIG. 4aand is referred to as the first gate of the SCR. The base of the transistor Q2and the collector of the transistor Q1are the P-well200ofFIG. 4aand is referred to as the second gate of the SCR.

The diodes D1, D2, and D3are serially connected from cathode to anode and are structured as the diode D1of theFIG. 4a. The anode of the first diode D1is connected to the signal input/output interface pad275and the cathode of the last diode D3is connected to the second gate of the SCR. The resistor R2is connected to the second gate of the SCR and the cathode of the last diode D3. It should be noted that while this embodiment is implemented with the three diodes D1, D2, and D3, there may be any number of diodes connected serially. The number being determined by the operational voltages of the integrated circuits connected to the signal input/output interface pad275.

The resistor RP-WELLis the bulk resistance of the P-well200ofFIG. 4aand is connected from the second gate of the SCR and the power supply connection pad280. The resistors R1and R2are constructed using any known technique such as a highly doped diffusion region.

When an ESD event285occurs, the voltage at the signal input/output interface pad285increases dramatically. The diodes D1, D2, and D3begin to conduct and a voltage is developed across the resistors R2and RP-WELL. The transistor Q2turns on causing current to flow through the resistor R1. The voltage developed across the resistor R1turns on the transistor Q2. The SCR is thus activated to conduct the energy of the ESD event from the integrated circuits connected to the signal input/output interface pad275to the power supply connection pad280.

A fourth embodiment of the ESD protection circuit, as shown inFIG. 8is connected between the signal input/output interface pad275and the power supply connection pad280. This embodiment incorporates the triggering bias circuits of the second and third embodiments. Further, the optional diodes D1and D2of the second embodiment are included as the diodes D4and D6and placed in series with the SCR between the signal input/output interface pad275and the SCR. These diodes are structured as the diode D1of theFIG. 4aand increase the holding voltage of the SCR when it is turned on.

The SCR is formed as described inFIGS. 4aand4b. The base of the transistor Q1and the collector of the transistor Q2is the N-well205ofFIG. 4aand will be referred to as the first gate of the SCR. The base of the transistor Q2and the collector of the transistor Q1are the P-well200ofFIG. 4aand are referred to as the second gate of the SCR.

The resistor/capacitor triggering circuit is formed by the resistor R1and capacitor C1. The resistor R1is connected between the signal input/output interface pad275and the first gate and the capacitor C1is connected from the first gate to the power supply connection pad280. In this example, the power supply connection pad280is the ground reference point for the integrated circuit.

As described above, the resistor R1is constructed using any known technique such as a highly doped diffusion region. The capacitance is constructed using any known technique such as employing a gate to bulk capacitance of a MOSFET as the capacitor C1.

The diode triggering circuit includes the serially connected diodes D1, D2, and D3and the resistor R2. The diodes D1, D2, and D3are serially connected cathode to anode and are structured as the diode D1of theFIG. 4a. The anode of the first diode D1is connected to the signal input/output interface pad275and the cathode of the last diode D3is connected to the second gate of the SCR. The resistor R2is connected to the second gate of the SCR and the cathode of the last diode D3. As noted above, that while this embodiment is implemented with the three diodes D1, D2, and D3, there may be any number of diodes connected serially. The number is determined by the operational voltages of the integrated circuits connected to the signal input/output interface pad275.

The resistor RP-WELLis the bulk resistance of the P-well200ofFIG. 4aand is connected from the second gate of the SCR and the power supply connection pad280. The resistor R2is constructed using any known technique such as a highly doped diffusion region.

When an ESD event285occurs, the voltage at the signal input/output interface pad285increases dramatically. The diodes D1, D2, and D3begin to conduct and a voltage is developed across the resistors R1and RP-WELL. The transistor Q2turns on. Simultaneously, the top plate of the capacitor C1at the first gate is at a virtual ground, thus causing the transistor Q1to turn on, thus activating the SCR. The SCR then transfers the energy to the power supply connection pad280.

A fifth embodiment of the ESD protection circuit, as shown inFIG. 9is connected between the signal input/output interface pad275and the power supply connection pad280. In this embodiment, the triggering bias circuit is a resistor R and capacitor C that are formed of a first metal oxide semiconductor (MOS) transistor M1biased to act as the resistor R and a second MOS transistor M5connected to form the capacitor C. The MOS transistor M2connected to bias the MOS transistor M1to an on condition to act as the resistor R. The junction connection between the resistor R and capacitor C is connected to an input terminal of a first inverter I1of a group of serially connected inverters I1, I2, and I3. In this embodiment the preferred implementation of the group of serially connected inverters I1, I2, and I3is shown as three inverters however, the number of inverters maybe adjusted according to the requirements of the design.

The SCR is formed as described inFIGS. 4aand4b. The base of the transistor Q1and the collector of the transistor Q2is the N-well205ofFIG. 4aand will be referred to as the first gate of the SCR. The base of the transistor Q2and the collector of the transistor Q1are the P-well200ofFIG. 4aand are referred to as the second gate of the SCR.

Each of the group of serially connected inverters I1, I2, and I3is formed as shown for the inverter I1. The inverter I1is formed of the PMOS transistor M3serially connected drain to drain with the NMOS transistor M4. The gates of the PMOS transistor M3and the NMOS transistor M4are connected to be the input of the inverter I1. The drains of the PMOS transistor M3and the NMOS transistor M4being the output of the inverter I1. The source of the NMOS transistor M4is connected to the power supply connection pad280and the source of the PMOS transistor M3is connected to the diode D2.

The output of the inverter I2that is in phase with the input of the group of serially connected inverters I1, I2, and I3is connected to the first gate of the SCR. The output of the inverter I3that is out of phase with the input of the group of serially connected inverters I1, I2, and I3is connected to the second gate of the SCR.

When an ESD event285occurs, the voltage at the signal input/output interface pad285increases dramatically. The top plate of the capacitor C1at the first gate is at a virtual ground, thus activating the group of serially connected inverters I1, I2, and I3. This causes the transistors Q1and Q2to turn on, thus activating the SCR. The SCR then transfers the energy to the power supply connection pad280. The group of serially connected inverters I1, I2, and I3provide a sharp transition and a clearly defined window when the SCR is turned on.

The diode D2is connected in series with the inverter I1to provide protection against accidental triggering of the ESD protection circuit during normal operation. The diode D1is placed in series with the SCR to increase the holding voltage of the ESD protection circuit. The diode D1may optionally be a group of serially connected diodes to adjust the holding voltage.

A sixth embodiment of the ESD protection circuit, as shown inFIG. 10is connected between the signal input/output interface pad275and the power supply connection pad280. In this embodiment, the triggering bias circuit is a resistor R and capacitor C are formed of a first metal oxide semiconductor (MOS) transistor M1biased to act as the resistor R and a second MOS transistor M4connected to form the capacitor C. The MOS transistor M2connected to bias the MOS transistor M1to an on condition to act as the resistor R.

The SCR is formed as described inFIGS. 4aand4b. The base of the transistor Q1and the collector of the transistor Q2is the N-well205ofFIG. 4aand will be referred to as the first gate of the SCR. The base of the transistor Q2and the collector of the transistor Q1are the P-well200ofFIG. 4aand are referred to as the second gate of the SCR.

The junction connection between the resistor R and capacitor C is connected to an input terminal of a first inverter I1and to the gates of the PMOS transistor M7, and the NMOS transistor M8within the inverter I3. The output of the inverter I1is connected to the gate of the NMOS transistor M4.

The inverter I2is constructed of the PMOS transistor M3and the NMOS transistor M4having their drains connected together. The source of the NMOS transistor M4is connected to the power supply connection pad280. The source of the PMOS transistors M3is connected to the anode of the diode D2and the cathode of the diode is connected to the signal input/output interface pad275. The output of the inverter I2at the junction of the drains of the PMOS transistor M3and the NMOS transistor M4is connected to the first gate of the SCR and the gate of the PMOS transistor M6.

The third inverter I3is constructed of the serially connected PMOS transistors M6and M7and the NMOS transistor M8. The junction connection between the resistor R and the capacitor C is connected to the gates of the PMOS transistors M7and the NMOS transistor M8, The output of the third inverter I3at the junction of the PMOS transistors M7and the NMOS transistor M8is connected to the second gate of the SCR and provide a weak feedback to the gate of the PMOS transistor M3.

When an ESD event285occurs, the voltage at the signal input/output interface pad275increases dramatically. The top plate of the capacitor C1at the first gate is at a virtual ground, thus activating the group of serially connected inverters I1, I2, and I3. This causes the transistors Q1and Q2to turn on, thus activating the SCR. The SCR then transfers the energy to the power supply connection pad280. The weak feedback at the pullup of the PMOS transistor M3provides a sharp transition and a clearly defined window when the SCR is turned on.

The diode D2is connected in series with the inverter I1to provide protection against accidental triggering of the ESD protection circuit during normal operation. The diode D1is placed in series with the SCR to increase the holding voltage of the ESD protection circuit. The diode D1may optionally be a group of serially connected diodes to adjust the holding voltage.

The ESD protection circuit of this invention, as shown in the six embodiments, is preferably a polysilicon bounded SCR of this invention. The polysilicon bounded SCR of this invention provides a more compact device with a lower internal resistance. However, the ESD protection circuit of this invention, as shown in the four embodiments may have a shallow trench isolation bounded SCR as shown inFIG. 3. Further the diodes D1and D2ofFIG. 6, diodes D1, D2and D3ofFIG. 7, and diodes D1, D2, D3, D4, and D5ofFIG. 8may be the shallow trench isolation bounded diodes as shown inFIG. 1. As is known in the art, the shallow trench isolation does not allow the small feature size achievable with the polysilicon bounded SCR or polysilicon bounded diodes. Further the depth of the shallow trench isolation forces the currents to travel farther through the bulk of the devices, thus increasing the series resistance of the devices and thereby the heating during an ESD event.