Non-volatile memories and data reading methods thereof

A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of Chinese Patent Application No. CN201610531757.2, filed on Jul. 7, 2016, the entire content of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of communication technology and, more particularly, relates to non-volatile memories and fabrication methods thereof.

BACKGROUND

Semiconductor memories used to store data are usually classified into volatile memories and non-volatile memories (NVMs). Data stored in the volatile memories may be lost when the power supplies are terminated. However, NVMs may still be able to keep the stored data after power outage. Compared to various volatile memories used in current memory technology such as disk drives, NVMs may have relatively smaller sizes. Therefore, NVMs have been more and more widely used in mobile communication systems, computers, memory cards, etc.

NVMs demonstrate capabilities in multi-time data storing, data reading, and data erasing. In general, an NVM usually includes a plurality of memory cells arranged into a matrix, a plurality of word lines arranged along the horizontal direction of the matrix, and a plurality of bit lines arrange along the longitudinal direction of the matrix.

During data reading operation, a bit line voltage is usually applied to the bit line corresponding to the memory cell in which the data to be read is stored. In addition, a sense amplifier (SA) is used. Specifically, one terminal of the SA receives the output voltage of the memory cell while the other terminal of the SA receives a bias voltage sent from a bias voltage source. The SA then compares the output voltage of the memory cell and the reference voltage from the bias voltage source to determine the information stored in the memory cell corresponding to logical ‘1’ or logical ‘0’.

However, the data reading accuracy of existing NVMs may still need to be improved. The disclosed NVMs and data reading methods thereof are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a non-volatile memory (NVM). The NVM includes at least one memory unit region. Each memory unit region includes a plurality of memory cells arranged into a memory array. The memory cells in odd columns of the memory array are first memory cells, and the memory cells in even columns of the memory array are second memory cells. Corresponding to each memory unit region, the NVM includes a plurality of bit lines including odd bit lines connected to the first memory cells and even bit lines connected to the second memory cells, a multiplexer (Y-mux) including a plurality of first bit line decoders connected to the odd bit lines and a plurality of second bit line decoders connected to the even bit lines, a comparator circuit, and a bias generation circuit used to generate a bias voltage. The comparator circuit includes a first input terminal connected to the plurality of first bit line decoders, a second input terminal connected to the plurality of second bit line decoders, and an output terminal. Moreover, during an operation to read the data information stored in a first memory cell, the Y-mux is controlled to send a first output voltage from the first memory cell to the first input terminal of the comparator circuit, and the bias generation circuit is controlled to send the bias voltage to the second input terminal of the comparator circuit; and during an operation to read the data information stored in a second memory cell, the Y-mux is controlled to send a second output voltage from the second memory cell to the second input terminal of the comparator circuit, and the bias generation circuit is controlled to send the bias voltage to the first input terminal of the comparator circuit.

Another aspect of the present disclosure provides a method for reading data information stored in an NVM. The method includes providing an NVM. The NVM includes at least one memory unit region, each including a plurality of memory cells arranged into a memory array. The memory cells in odd columns of the memory array are first memory cells, and the memory cells in even columns of the memory array are second memory cells. Corresponding to each memory unit region, the NVM includes a plurality of bit lines including odd bit lines connected to the first memory cells and even bit lines connected to the second memory cells, a multiplexer (Y-mux) including a plurality of first bit line decoders connected to the odd bit lines and a plurality of second bit line decoders connected to the even bit lines, a comparator circuit, and a bias generation circuit used to generate a bias voltage. The comparator circuit includes a first input terminal connected to the plurality of first bit line decoders, a second input terminal connected to the plurality of second bit line decoders, and an output terminal. Further, during an operation to read the data information stored in a first memory cell, the method includes sending a first output voltage from the first memory cell to the first input terminal of the comparator circuit through the Y-mux and the bias voltage to the second input terminal of the comparator circuit through the bias generation circuit. Moreover, during an operation to read the data information stored in a second memory cell, the method includes sending a second output voltage from the second memory cell to the second input terminal of the comparator circuit through the Y-mux, and the bias voltage to the first input terminal of the comparator circuit through the bias generation circuit.

DETAILED DESCRIPTION

According to existing fabrication methods and semiconductor structures, the data reading accuracy of existing NVMs may still need to be improved. In the following, an example will be given to illustrate the reasons for the poor data reading accuracy of existing NVMs.FIG. 1shows a schematic circuit diagram of an existing NVM.FIG. 2shows a portion of the circuit diagram shown inFIG. 1.

Referring toFIG. 1, the NVM includes a plurality of memory cells120arranged in a matrix to form a memory array. Each memory cell120stores one bit of information. The NVM also includes a plurality of bit lines150and the memory cells120arranged in a same column of the memory array share a common bit line150.

As shown inFIG. 1, the plurality of memory cells120form a memory unit region110. The NVM includes a plurality of memory unit regions110arranged in parallel with each other. For illustration purpose, only one memory unit region110is shown inFIG. 1. The bit lines150in the memory unit region110further include a plurality of main bit lines151and a reference bit line152. The main bit lines151are all formed on one side of the reference bit line152. For example, in the memory unit region110shown inFIG. 1, the plurality of main bit lines151include BL<0>, BL<1>, BL<2>, . . . BL<n−1>, where n is a positive integer; while the reference bit line152includes BL<Ref>. Moreover, the bit lines150in other memory unit regions (not shown) are also arranged in the same way as described above.

Moreover, the plurality of memory cells120connected with the main bit lines151are first memory cells121. The plurality of first memory cells121arranged in a same column of the memory array share a same main bit line151. In addition, the plurality of memory cells120connected with the reference bit line152are second memory cells122.

Corresponding to the plurality of main bit lines151, the NVM also includes a plurality of first bit line decoders111. Each first bit line decoder111is connected to a corresponding main bit line151and includes a P-type MOS (PMOS) transistor P11, an N-type MOS (NMOS) transistor N11, and another NMOS transistor N12. The plurality of first bit line decoders111are configured to send out a first output voltage V1from the plurality of first memory cells121on the main bit lines151.

The NVM further includes a bias voltage source300. The bias voltage source300is configured to generate a bias voltage Vref. The bias voltage source300is connected to a second bit line decoder112. The second bit line decoder112includes a PMOS transistor P12, an NMOS transistor N13, and another NMOS transistor N14. The second bit line decoder112is configured to send out the bias voltage Vref.

The plurality of first bit line decoders111and the second bit line decoder112together form a multiplexer (Y-Mux)100. The Y-mux100has two output terminals. The plurality of first bit line decoders111and the second bit line decoder112in the Y-mux100are collectively controlled by decoder signals to send a first output voltage V1and the bias voltage Vrefrespectively to the two terminals of the Y-mux100. Specifically, when the data information stored in a first memory cell121needs to be read out, the decoder signals are sent to the plurality of first bit line decoders111during the data reading operation to allow an output terminal of the Y-mux100to send out the corresponding first output voltage V1; simultaneously, the decoder signals also controls the other output terminal of the Y-Mux100to send out the bias voltage Vref.

Further, the NVM also includes an SA200corresponding to each memory unit region110. The SA200is used to compare the first output voltage V1and the bias voltage Vref, sent from the Y-mux100, to obtain the data information stored in the corresponding first memory cell121. Specifically, the SA200includes a first input terminal211, a second input terminal212, and an output terminal213. The first input terminal211is used to receive the first output voltage V1and the second input terminal212is used to receive the bias voltage Vref. During data reading operation of the NVM, when the first output voltage V1is smaller than the bias voltage Vref, the information read from the corresponding first memory cell121is logical ‘0’; while when the first output voltage V1is larger than the bias voltage Vref, the information read from the corresponding first memory cell121is logical ‘1’.

However, the structure of the main bit line151may be different from the structure of the reference bit line152and the fabrication process for the main bit line151may also be difference from the fabrication process of the reference bit line152. Therefore, the difference in the electrical performance (such as leakage current, parasitic capacitance, etc.) of the main bit line151and the reference bit line152may not be kept in a process-allowed range. With repeat operation of data storing, data reading, and data erasing, the difference in the electrical properties (such as leakage current, parasitic capacitance, etc.) of the main bit line151and the reference bit line152may continuously increase, which may easily cause an increased possibility of getting a false result from the comparison between the first output voltage V1and the reference voltage Vref, and thus may further lead to decreased data reading accuracy.

In view of the problems described above, the present disclosure provides an NVM.FIG. 3shows a schematic circuit diagram of an exemplary NVM consistent with disclosed embodiments.FIG. 4shows a portion of the circuit diagram shown inFIG. 3.

Referring toFIG. 3andFIG. 4, the NVM may include a plurality of memory unit regions401with each containing a memory array (not labeled). Moreover, the memory array may include a plurality of memory cells402arranged in a matrix. For illustration purpose, only one memory unit region401is shown inFIG. 3and each memory cell402in the memory array of the memory unit region401may only store one bit of information. Further, along a direction from left to right, the array matrix of the memory cells402may include a plurality of to columns. Memory cells402arranged in the odd columns of the array matrix are first memory cells411, and the memory cells arranged in even columns of the array matrix are second memory cells412.

Further, the NVM may include a plurality of bit lines420. The plurality of bit lines may further include odd bit lines471connected to the first memory cells411and even bit lines472connected to the second memory cells412.

Each memory unit region401of the NVM may include a plurality of first bit line decoders431configured to send out a first output voltage Vi from the plurality of first memory cells411on the odd bit lines471. Each first bit line decoder431may be connected to a corresponding odd bit line471and include a PMOS transistor P21and two NMOS transistors N21and N22.

Each memory unit region401of the NVM may also include a plurality of second bit line decoders432configured to send out a second output voltage V2from the plurality of second memory cells412on the even bit lines472. Each second bit line decoder432may be connected to a corresponding even bit line472and include a PMOS transistor P22and two NMOS transistors N23and N24.

For example, the selection/deselection of BL<0> and the selection/deselection of BL<1> may be simultaneously controlled by signals applied to the transistors of the corresponding first bit line decoder431and the corresponding second bit line decoder432. Specifically, when the information stored in the memory cell selected by the bit line BL<0> needs to be read out, the control signals, similar to bit line decoders, may enable the selection of BL<0> through transistors P21, N21, and N22. As such, the first output voltage V1stored in the memory cell corresponding to BL<0> may be sent to the first input terminal441of the sense amplifier440. In the meantime, the control signals may be simultaneously sent to the transistors P22, N23, and N24of the corresponding second bit line decoder432to ensure the deselection of BL<1>. Moreover, the first transistor451and the second transistor452of the enable unit421may be simultaneously controlled to allow the bias voltage Vrefto be sent to the second input terminal442of the sense amplifier440. The sense amplifier440may compare V1with the bias voltage Vrefand send the result to the IO of the sense amplifier440. As such, the information stored in the memory cell selected by bit line BL<0> may be read out.

Similarly, when the information stored in the memory cell selected by the bit line BL<1> needs to be read out, the control signals may enable the selection of BL<1> through transistors P22, N23, and N24. As such, the second output voltage V2stored in the memory cell corresponding to BL<1> may be sent to the second input terminal442of the sense amplifier440. In the meantime, the control signals may be simultaneously sent to the transistors P21, N21, and N22of the corresponding first bit line decoder431to ensure the deselection of BL<0>. Moreover, the first transistor451and the second transistor452of the enable unit421may be simultaneously controlled to allow the bias voltage Vrefto be sent to the first input terminal441of the sense amplifier440. The sense amplifier440may compare V2with the bias voltage Vrefand send the result to the IO of the sense amplifier440. As such, the information stored in the memory cell selected by bit line BL<1> may be read out.

Further, the plurality of first bit line decoders431and the plurality of second bit line decoders432may together form a Y-mux400. The Y-mux400may have two output terminals. The plurality of first bit line decoders431and the plurality of second bit line decoders432in the Y-mux400are collectively controlled by decoder signals to send a first output voltage V1or a second output voltage V2and a bias voltage Vrefto the two terminals. Specifically, when the data information stored in a first memory cell411needs to be read out, the corresponding decoder signals may be sent to the plurality of first bit line decoders431and the plurality of second bit line decoders432to allow the corresponding first output voltage V1to be sent to the output terminal connected to the plurality of first bit line decoders431, and the bias voltage Vrefto the other output terminal connected to the plurality of second bit line decoders432. Similarly, when the data information stored in a second memory cell412needs to be read out, the corresponding decoder signals may be sent to the plurality of first bit line decoders431and the plurality of second bit line decoders432to allow the corresponding second output voltage V2to be sent to the output terminal connected to the plurality of second bit line decoders432, and the bias voltage Vrefto the other output terminal connected to the plurality of first bit line decoders431.

Further, the NVM may include a comparator circuit corresponding to each memory unit region401. In one embodiment, the comparator circuit may be an SA440may including a first input terminal441, a second input terminal442, and an output terminal443. The first input terminal441may be connected to the plurality of first bit line decoders431while the second input terminal442may be connected to the plurality of second bit line decoders432.

The NVM may also include a bias generation circuit450. The bias generation circuit450may generate a bias voltage Vref. In addition, the bias generation circuit450may be used to apply the bias voltage Vrefto the second input terminal442when the first output voltage V1is applied to the first input terminal441so that the corresponding SA440may be able to read the information stored in the first memory cell411based on the voltage difference between the first output voltage V1and the bias voltage Vref. Moreover, the bias generation circuit450may also be used to apply the bias voltage Vrefto the first input terminal441when the second output voltage V2is applied to the second terminal442so that the corresponding SA440may be able to read the information stored in the second memory cell412based on the voltage difference between the second output voltage V2and the bias voltage Vref.

Further, the plurality of memory cells402may be used to store data information that may need to be read out. In one embodiment, each memory cell402may include a control gate (CG, not shown), a floating gate (FG, not shown), and a select gate410(SG, referring toFIG. 3). Prior to performing a data reading operation, the data information to be read out may be stored in the FG of a memory cell402. During the data reading operation, the channel region of the memory cell402may be turned on by controlling the SG410of the memory cell402such that outputting the first output voltage V1or the second output voltage V2may be realized.

Specifically, when reading the data information stored in a first memory cell411, the corresponding first output voltage V1may be sent to the first input terminal441of the corresponding SA440through the Y-mux400, and in the meantime, the bias voltage Vrefmay be sent to the second input terminal442of the SA440through the Y-mux400. Similarly, when reading the data stored in a second memory cell412, the corresponding second output voltage V2may be sent to the second input terminal442of the corresponding SA440through the Y-mux400, and in the meantime, the bias voltage Vrefmay be sent to the first input terminal441of the SA440through the Y-mux400.

The plurality of memory cells402may be duplicated cells. That is, the plurality of memory cells402may have an identical structure. In one embodiment, the memory cells are in the data reading state.

Further, the number of the columns of the memory array in each memory unit region401may be in a range from 256 to 4096, and the number of the rows of the memory array may be in a range from 256 to 2048.

For illustration purpose, the memory array is described to have 256 columns and 256 rows. Therefore, the memory cells located in the 1stcolumn, the 3rdcolumn . . . the 255thcolumn are the first memory cells411; while the memory cells located in the 2ndcolumn, the 4thcolumn . . . the 256thcolumn are the second memory cells412.

In one embodiment, the number of the plurality of bit lines420is n, where n is an even number. Specifically, the bit lines420include BL<0>, BL<1>, BL<2>, BL<3>. . . BL<n−2>, and BL<n−1>. Moreover, BL<0>, BL<2>. . . BL<n−2> are connected to memory cells in the 1stcolumn, the 3rdcolumn . . . the (n−1)thcolumn, respectively. That is, BL<0>, BL<2>. . . BL<n−2> are connected to the first memory cells411, respectively. Therefore, BL<0>, BL<2>. . . BL<n−2> are odd bit lines471. In the meantime, BL<1>, BL<3>. . . BL<n−1> are connected to memory cells in the 2ndcolumn, the 4thcolumn . . . the nthcolumn, respectively. That is, BL<1>, BL<3>. . . BL<n−1> are connected to the second memory cells412, respectively. Therefore, BL<1>, BL<3>. . . BL<n−1> are even bit lines472. Moreover, the plurality of odd bit lines471and the plurality of even bit lines472are alternately arranged along the extending direction of the rows of the memory array.

Therefore, a plurality of first memory cells411in a same column of the memory array may share an odd bit line471while a plurality of second memory cells412in a same column of the memory array may share an even bit line472.

In one embodiment, the NVM may include a plurality of memory unit regions401arranged along the extending direction of the rows of the memory array. Each memory unit region401may include memory cells402with an identical number of columns and an identical number of bit lines420. In addition, in each memory unit region401, the bit lines420may include a plurality of odd bit lines471and a plurality of even bit lines472alternately arranged along the extending direction of the rows of the memory array. The layout of bit lines420in different memory unit regions401may be the same. Moreover, the structure of the odd bit lines471and the structure of the even bit lines472may also be the same.

For example, a memory unit region401includes 6 columns of memory cells402and 6 bit lines420. The bit lines420are arranged along the extending direction of the rows of the memory array in an order of BL<0>, BL<1>, BL<2>, BL<3>, BL<4>, and BL<5>. Among the 6 bit lines420, BL<0>, BL<2>, and BL<4> are odd bit lines471, while BL<1>, BL<3>, and BL<5> are even bit lines472. In one embodiment, the number of columns in a memory unit region401is 128.

Further, the NVM may also include a plurality of word lines (not shown). Each word line may extend along a direction parallel to the extending direction of the rows of the memory array, and the plurality of word lines may be separated from each other along the extending direction of the columns of the memory array. Moreover, a plurality of memory cells402in a same row of the memory array may share one word line. Specifically, the word line may be connected to the CG of each memory cell402.

The plurality of bit lines420and the plurality of word lines may together be used to control the data reading operation of the memory cells402. In addition, the plurality of bit lines420and the plurality of word lines may also be used to determine the physical address of each memory cell402. Specifically, the column address of a certain memory cell402may be determined through the plurality of bit lines420, and the row address of the memory cell402may be determined through the plurality of word lines. As such, the complete address of the memory cell402that needs to be read in the memory array may then be determined.

Accordingly, the number of the bit lines420may be the same as the number of the columns of the memory array and the number of the word lines may be the same as the number of the rows of the memory array. In one embodiment, the number of bit lines420may be in a range from 256 to 4096, and the number of the word lines may be in a range from 256 to 2048.

In one embodiment, the plurality of first memory cells411may include a plurality of first SGs (not shown). For example, the first memory cells411may include SG<0>, SG<2>. . . SG<n−2>. The first SGs of the first memory cells411in a same row may be connected with each other. In addition, the plurality of second memory cells412may include a plurality of second SGs (not shown). For example, the second memory cells412may include SG<1>, SG<3>. . . SG<n−1>. The second SGs of the second memory cells412in a same row may be connected with each other. Moreover, the plurality of first SGs and the plurality of second SGs may together form the SGs410.

In one embodiment, the NVM may also include alternately arranged first SG electrodes and second SG electrodes. Each first SG electrode may be connected to the first SGs of the first memory cells411in a corresponding row of the memory array and each second SG electrode may be connected to the second SGs of the second memory cells412in a corresponding row of the memory array. That is, the plurality of first memory cells411in a same row of the memory array may have a common SG410and the plurality of second memory cells412in a same row of the memory array may also have a common SG410.

By distinguishing the SGs410for the first memory cells411and the second memory cells412, the channel region of each first memory cell411or each second memory cell412may be turned on or turned off such that the data information stored in the first memory cell411or in the second memory cell412may then be read out.

In one embodiment, each memory unit region401of the NVM may also include a plurality of first bit line decoders431configured to send out a first output voltage V1from the plurality of first memory cells411on the odd bit lines471. Each first bit line decoder431may be connected to a corresponding odd bit line471and include a PMOS transistor P21and two NMOS transistors N21and N22. Moreover, each memory unit region401of the NVM may also include a plurality of second bit line decoders432configured to send out a second output voltage V2from the plurality of second memory cells412on the even bit lines472. Each second bit line decoder432may be connected to a corresponding even bit line472and include a PMOS transistor P22and two NMOS transistors N23and N24.

The selection/deselection of BL<0> and the selection/deselection of BL<1> may be simultaneously controlled by signals applied to the transistors of the corresponding first bit line decoder431and the corresponding second bit line decoder432. Specifically, when the information stored in the memory cell selected by the bit line BL<0> needs to be read out, the control signals, similar to bit line decoders, may enable the selection of BL<0> through transistors P21, N21, and N22. As such, the first output voltage V1stored in the memory cell corresponding to BL<0> may be sent to the first input terminal441of the sense amplifier440. In the meantime, the control signals may be simultaneously sent to the transistors P22, N23, and N24of the corresponding second bit line decoder432to ensure the deselection of BL<1>. Moreover, the first transistor451and the second transistor452of the enable unit421may be simultaneously controlled to allow the bias voltage Vrefto be sent to the second input terminal442of the sense amplifier440. The sense amplifier440may compare V1with the bias voltage Vrefand send the result to the IO of the sense amplifier440. As such, the information stored in the memory cell selected by bit line BL<0> may be read out.

Similarly, when the information stored in the memory cell selected by the bit line BL<1> needs to be read out, the control signals may enable the selection of BL<1> through transistors P22, N23, and N24. As such, the second output voltage V2stored in the memory cell corresponding to BL<1> may be sent to the second input terminal442of the sense amplifier440. In the meantime, the control signals may be simultaneously sent to the transistors P21, N21, and N22of the corresponding first bit line decoder431to ensure the deselection of BL<0>. Moreover, the first transistor451and the second transistor452of the enable unit421may be simultaneously controlled to allow the bias voltage Vrefto be sent to the first input terminal441of the sense amplifier440. The sense amplifier440may compare V2with the bias voltage Vrefand send the result to the IO of the sense amplifier440. As such, the information stored in the memory cell selected by bit line BL<1> may be read out.

Further, corresponding to each memory unit region401of the NVM, the plurality of first bit line decoders431and the plurality of second bit line decoders432may together form a Y-mux400. The Y-mux400may have two output terminals. When the data information stored in a first memory cell411needs to be read out, the corresponding decoder signals may be sent to the plurality of first bit line decoders431and the plurality of second bit line decoders432during the data reading operation to allow an output terminal of the Y-mux400to send out the corresponding first output voltage V1, and the other output terminal of the Y-Mux400to send out a bias voltage Vref. Similarly, when the data information stored in a second memory cell412needs to be read out, the corresponding decoder signals may be sent to the plurality of first bit line decoders431and the plurality of second bit line decoders432during the data reading operation to allow an output terminal of the Y-mux400to send out the corresponding second output voltage V2, and the output terminal of the Y-Mux400to send out a bias voltage Vref.

Specifically, in one embodiment, because each memory unit region401includes a plurality of first memory cells411and a plurality of second memory cells412, the plurality of first memory cells411may send out a plurality of first output voltages V1and the plurality of second cells412may send out a plurality of second output voltages V2. Further, controlled by decoder signals, the first output voltages V1may be sequentially applied to the first input terminal441through the first bit line decoders431of the Y-mux400; in the meantime, the second output voltages V2may also be sequentially applied to the second input terminal442through the second bit line decoders432of the Y-mux400.

That is, at any given moment, only one first output voltage V1of the first memory cells411on the odd bit lines471may be selected and sent out through the Y-mux400, and only one second output voltage V2of the second memory cells412on the even bit lines472may be selected and sent out through the Y-mux400.

Further, in one embodiment, when the SA440is used to compare the voltage at the first input terminal441with the voltage at the second input terminal442, the difference between the voltages may be amplified. Therefore, the use of SA440may be conducive to comparing the voltages at the first input terminal441and the second input terminal442, and thus may improve the data reading accuracy.

Moreover, the NVM may include a plurality of memory unit regions401and each memory unit region401may be connected to a corresponding SA440to allow the data information stored in the memory unit region401to be read out. As such, a plurality of SAs440may simultaneously read out a plurality of data stored in the NVM, and thus the data reading efficiency may be improved. Accordingly, the number of the SAs440may be equal to the number of the memory unit regions401.

For example, the number of the columns of the memory array in the NVM may be in a range from 256 to 4096, and each memory unit region401in the NVM may include a memory array with 128 columns of memory cells402. That is, the number of memory unit regions401in the NVM may be in a range from 2 to 32. Accordingly, the number of the SAs440in the NVM may also be in a range from 2 to 32.

In one embodiment, the bias generation circuit450may include a bias voltage source423used to generate a bias voltage Vref, and an enable unit421connected to the first input terminal441and the second input terminal442of each SA440. The enable unit421may be used to apply the first output voltage V1to the first input terminal441and also apply the bias voltage Vrefto the second input terminal442so that the corresponding SA440may be able to read the information stored in the first memory cell411based on the voltage difference between the first output voltage V1and the bias voltage Vref. Moreover, the enable unit421may also be used to apply the bias voltage Vrefto the first input terminal441and also apply the second output voltage V2to the second terminal442so that the corresponding SA440may be able to read the information stored in the second memory cell412based on the voltage difference between the second output voltage V2and the bias voltage Vref.

Specifically, the enable unit421may include a control unit (not shown), a first metal-oxide-semiconductor (MOS) transistor451and a second MOS transistor452connected to the control unit, the bias voltage source423, and the corresponding SA440. Moreover, the to control unit may be used to turn off the second MOS transistor452when the first MOS transistor451is turned on, and thus the first MOS transistor451may further apply the bias voltage Vrefto the first input terminal441. In addition, the control unit may also be used to turn on the second MOS transistor452when the first MOS transistor451is turned off, and thus the second MOS transistor452may further apply the bias voltage Vrefto the second input terminal442. That is, the control unit may simultaneously control the first MOS transistor451and the second MOS transistor452to allow the bias voltage Vrefto be sent to only one input terminal of the corresponding SA440based on whether a first memory cell411or a second memory cell412is read out during the data reading operation.

In one embodiment, the first MOS transistor451may include a first gate electrode (not labeled), a first source electrode (not labeled), and a first drain electrode (not labeled), while the second MOS transistor452may include a second gate electrode (not labeled), a second source electrode (not labeled), and a second drain electrode (not labeled). Specifically, the first gate electrode and the second gate electrode may be connected to the control unit; the first source electrode and the second source electrode may be connected to the bias voltage source423; the first drain electrode may be connected to the first input terminal441; and the second drain electrode may be connected to the second input terminal442.

In one embodiment, the first MOS transistor451is an NMOS transistor while the second MOS transistor452may be a PMOS transistor. In another embodiment, the first MOS transistor may be a PMOS transistor and the second MOS transistor may be an NMOS transistor.

FIG. 5shows a schematic local layout structure of the exemplary NVM shown inFIG. 3. ReferringFIG. 5, for illustration purpose, the local layout structure of the NVM is described to have four bit lines420, i.e. BL<0>, BL<1>, BL<2>, and BL<3>. Specifically, the data reading operation of the first memory cells411corresponding to BL<0> and BL<2> may be realized by using a first via hole501on BL<0>, a third via hole503on BL<2>, a first metal layer (not shown) in connection with the first via hole501and the third via hole503, and the common SGs410(such as SG<0> and SG<2>) shared by the first memory cells411in a same row of the memory array. Similarly, the data reading operation of the second memory cells412corresponding to BL<1> and BL<3> may be realized by using a second via hole502on BL<1>, a fourth via hole504on BL<3>, a second metal layer (not shown) in connection with the second via hole502and the fourth via hole504, and the common SGs410(such as SG<0> and SG<2>) shared by the second memory cells412in a same row of the memory array.

Further, in one embodiment, the first memory cells411in a same column may share an odd bit line471, while the second memory cells412in a same column may share an even bit line472. Referring to the four bit lines420shown inFIG. 5, the first memory cells411in the first column of the memory array share BL<0>, the second memory cells412in the second column of the memory array share BL<1>, the first memory cells411in the third column of the memory array share BL<2>, and the second memory cells412in the fourth column of the memory array share BL<3>.

Further, in one embodiment, the first via hole501, the second via hole502, the third via hole503, and the fourth via hole504may be via holes in a same layer while the first metal layer and the second metal layer may be in a same layer.

Moreover, the layout structure of the odd bit lines471may be identical to the layout structure of the even bit lines472so that the layout design and the fabrication process may be simplified.

During a data reading operation of the NVM, when a bit line voltage is applied only to the odd bit lines471, i.e. the bit line voltage is not applied to the even bit lines472, data stored in the first memory cells411may be accessed during the data reading operation. In contrast, when the bit line voltage is only applied to applied to the even bit lines472, but not to the odd bit lines471, data stored in the second memory cells412may be accessed during the data reading operation. As such, data stored in all memory cells (not shown) of the memory array may be read out.

Compared to conventional NVMs, the disclosed NVM may demonstrate several advantages. Usually, a conventional NVM includes a plurality main bit lines and one or more reference bit line. The structure of the reference bit line may be different from the structure of the main bit line. Moreover, the bit line voltage may never be applied to the reference bit line, and thus the reference bit line may not be used as a main bit line.

In comparison, according to the present disclosure, when an odd bit line471is used as a main bit line, an even bit line472may be used as a reference bit line, and alternatively, when an even bit line472is used as a main bit line, an odd bit line471may be used as a reference bit line. In addition, the structures of the odd bit line471and the even bit line472may be identical to each other while the fabrication process for the odd bit line471may also be the same as the fabrication process for the even bit line472. Therefore, the odd bit line471and the even bit line472may have similar parasitic capacitance and leakage current so that data error caused by an overly large difference in the leakage current or the parasitic capacitance between the odd bit line471and the even bit line472may be avoided, and thus the data reading accuracy may be improved.

Moreover, according to the present disclosure, when an odd bit line471is used as a main bit line, an even bit line472may be used as a reference bit line, or when an even bit line472is used as a main bit line, an odd bit line471may be used as a reference bit line. As such, the information stored in all memory cells of the memory array may be read out. Therefore, the NVMs provided in the present disclosure may not require extra spaces for reference bit lines, and thus the disclosed NVMs may be conducive to the microminiaturization of NVMs.

Further, the present disclosure also provides a data reading method for NVMs. The data reading method may include providing an NVM consistent with the description above.

Referring toFIG. 3, the provided NVM may include at least one memory unit region401with each containing a memory array. For illustration purpose, only one memory unit region401is shown inFIG. 3. Further, the memory array of each memory unit region401may include a plurality of memory cells402arranged in a matrix and each memory cell402in the memory array of the memory unit region401may only store one bit of information. The plurality of memory cells402may be duplicated cells. That is, the plurality of memory cells402may have an identical structure. In one embodiment, the memory cells are in the data reading state. Moreover, along a direction from left to right, the array matrix of the memory cells may include a plurality of columns. Memory cells arranged in the odd columns of the array matrix are first memory cells411, and the memory cells arranged in even columns of the array matrix are second memory cells412.

Further, the NVM may include a plurality of bit lines420. The bit lines420may include a plurality of odd bit lines471connected to the first memory cells411and a plurality of even bit lines472connected to the second memory cells412.

A bias generation circuit450may be used to apply a bias voltage Vrefto the second input terminal442of the SA440when a first output voltage V1is applied to the first input terminal441of a SA440. Thus, the SA440may be used to read the information stored in a first memory cell411based on the voltage difference between the first output voltage V1and the bias voltage Vref.

Alternatively, the bias generation circuit450may be used to apply the bias voltage Vrefto the first input terminal441of the SA440when a second output voltage V2is applied to the second input terminal442of the SA440. Thus, the SA440may be used to read the information stored in a second memory cell412based on the voltage difference between the second output voltage V2and the bias voltage Vref.

In one embodiment, the process to apply the first output voltage V1to the first input terminal441of the SA440may include the following steps. First, a bit line voltage (not shown) may be sent to the odd bit lines471but not to the even bit lines472so that the first memory cells411corresponding to the odd bit lines471may be turned on while the second memory cells412corresponding to the even bit lines472may be turned off. Further, a first memory cell411may be selected from the plurality of first memory cells411connected to a same column such that the first output voltage V1may be applied to the first terminal441of the SA440.

Moreover, the process for the SA440to obtain the information stored in the first memory cell411based on the voltage difference between the first output voltage V1and the bias voltage Vrefmay include when the first output voltage V1is greater than the bias voltage Vref, the SA440may send out logic “1” as the information stored in the first memory cell411of the NVM; when the first output voltage V1is less than the bias voltage Vref, the SA440may send out logic “0” as the information stored in the first memory cell411of the NVM.

In one embodiment, the process to apply the bias voltage Vrefto the first input terminal441of the SA440and the second output voltage V2to the second input terminal442of the SA440may include the following steps. First, a bit line voltage (not shown) may be sent to the even bit lines472but not to the odd bit lines471so that the second memory cells412corresponding to the even bit lines472may be turned on while the first memory cells411corresponding to the odd bit lines471may be turned off. Further, a second memory cell412may be selected from the plurality of second memory cells412in a same column and the second output voltage V2may be applied to the second terminal442of the SA440.

Further, the process for the SA440to obtain the information stored in the second memory cell412based on the voltage difference between the second output voltage V2and the bias voltage Vrefmay include when the second output voltage V2is greater than the bias voltage Vref, the SA440may send out logic “1” as the information stored in the second memory cell412of the NVM; when the second output voltage V2is less than the bias voltage Vref, the SA440may send out logic “0” as the information stored in the second memory cell412of the NVM.

In one embodiment, the first output voltage V1may be in a range of 0 V to 1.6 V, the second output voltage V2may be in a range of 0 V to 1.6 V, and the bias voltage Vrefmay be in a range of 0.7 V to 0.8 V.

In one embodiment, the bias generation circuit450may include a bias voltage source423used to generate a bias voltage Vrefand an enable unit421connected to the first input terminal441and the second input terminal442of each SA440. The enable unit421may be used to apply the first output voltage V1to the first input terminal441and also apply the bias voltage Vrefto the second input terminal442so that the corresponding SA440may be able to read the information stored in the first memory cell411based on the voltage difference between the first output voltage V1and the bias voltage Vref. Moreover, the enable unit421may also be used to apply the bias voltage Vrefto the first input terminal441and also apply the second output voltage V2to the second terminal442so that the corresponding SA440may be able to read the information stored in the second memory cell412based on the voltage difference between the second output voltage V2and the bias voltage Vref.

Specifically, the enable unit421may include a control unit (not shown), a first MOS transistor451and a second MOS transistor452connected to the control unit, the bias voltage source423, and the corresponding SA440.

Accordingly, during a process to read the information stored in the second memory cell412, the control unit may turn off the second MOS transistor452and also turn on the first MOS transistor451such that the first MOS transistor451may apply the bias voltage Vrefto the first input terminal441. In addition, during a process to read the information stored in the first memory cell411, the control unit may turn on the second MOS transistor452and also turn off the first MOS transistor451such that the second MOS transistor452may apply the bias voltage Vrefto the second input terminal442.

In one embodiment, the first MOS transistor451is an NMOS transistor while the second MOS transistor452may be a PMOS transistor. Accordingly, the process for the control unit to turn on the first MOS transistor451and turn off the second MOS transistor452may include applying a high-level voltage to the first MOS transistor451and the second MOS transistor452; while the process for the control unit to turn off the first MOS transistor451and turn on the second MOS transistor452may include applying a low-level voltage to the first MOS transistor451and the second MOS transistor452.

In another embodiment, the first MOS transistor is a PMOS transistor while the second MOS transistor is an NMOS transistor. Accordingly, the process for the control unit to turn off the first MOS transistor and turn on the second MOS transistor may include applying a high-level voltage to the first MOS transistor and the second MOS transistor; while the process for the control unit to turn on the first MOS transistor and turn off the second MOS transistor may include applying a low-level voltage to the first MOS transistor and the second MOS transistor.

Further, the NVM may include a plurality of memory unit regions401arranged along the extending direction of the rows of the memory array. Each memory unit region401may include a plurality of first memory cells411and a plurality of second memory cells412. Accordingly, during the data reading operation, the plurality of first memory cells411may send out a plurality of first output voltages V1, and the plurality of second memory cells412may send out a plurality of second output voltages V2. Further, the plurality of first output voltages V1may then be sequentially received by the first input terminal441through a Y-mux400; in addition, the plurality of second output voltages V2may also be sequentially received by the second input terminal442through the Y-mux400.

The Y-mux400may be formed by a plurality of first bit line decoders431and a plurality of second bit line decoders432. The first bit line decoders431may be connected to the plurality of odd bit lines471with each including a PMOS transistor P21and two NMOS transistors N21and N22. The first bit line decoders431may be configured to send out a first output voltage V1from the plurality of first memory cells411on the odd bit lines471. The second bit line decoders432may be connected to the plurality of even bit lines472with each including a PMOS transistor P22and two NMOS transistors N23and N24. The second bit line decoders432may be configured to send out a second output voltage V2from the plurality of second memory cells412on the even bit lines472.

The Y-mux400may have two output terminals. When the data information stored in a first memory cell411needs to be read out, the corresponding decoder signals may be sent to the plurality of first bit line decoders431and the plurality of second bit line decoders432during the data reading operation to allow an output terminal of the Y-mux400to send out the corresponding first output voltage V1, and the other output terminal of the Y-Mux400to send out a bias voltage Vref. Similarly, when the data information stored in a second memory cell412needs to be read out, the corresponding decoder signals may be sent to the plurality of first bit line decoders431and the plurality of second bit line decoders432during the data reading operation to allow an output terminal of the Y-mux400to send out the corresponding second output voltage V2, and the output terminal of the Y-Mux400to send out a bias voltage Vref.

That is, at any given moment, only one first output voltage V1of the first memory cells411on the odd bit lines471may be selected and sent out through the first bit line decoders431of the Y-mux400. Thus, only one first output voltage V1may be applied to the first input terminal441of the SA440at any moment. Similarly, at any given moment, only one second output voltage V2of the second memory cells412on the even bit lines472may be sent out through the second bit line decoders432of the Y-mux400. Thus, only one second output voltage V2may be applied to the second input terminal442of the SA440at any moment.

In one embodiment, when the SA440is used to compare the voltage at the first input terminal441with the voltage at the second input terminal442, the difference between the voltages may be amplified. Therefore, the use of SA440may be conducive to comparing the voltages at the first input terminal441and the second input terminal442, and thus may improve the accuracy of data reading.

Moreover, each memory unit region401may be connected to a corresponding SA440to allow the data information stored in the corresponding memory unit region401to be read out. As such, a plurality of SAs440may simultaneously read out a plurality of data stored in the NVM, and thus the data reading efficiency may be improved.

During a data reading operation of the NVM, when a bit line voltage is applied only to the odd bit lines471, i.e. the bit line voltage is not applied to the even bit lines472, data stored in the first memory cells411may be accessed during the data reading operation. In contrast, when the bit line voltage is only applied to applied to the even bit lines472, but not to the odd bit lines471, data stored in the second memory cells412may be accessed during the data reading operation. As such, data stored in all memory cells (not shown) of the memory array may be read out.

Specifically, according to the disclosed NVM, the structures of the odd bit line471and the even bit line472may be identical to each other while the fabrication process for the odd bit line471may also be the same as the fabrication process for the even bit line472. Therefore, the odd bit line471and the even bit line472may have similar parasitic capacitance and leakage current so that data error caused by an overly large difference in the leakage current or the parasitic capacitance between the odd bit line471and the even bit line472may be avoided, and thus the data reading accuracy may be improved.

Compared to conventional NVMs with both main bit lines and one or more reference bit line, and the existing data reading methods, the disclosed NVM and the data reading method may demonstrate several advantages.

Specifically, according to the present disclosure, the NVM may include a memory array. The memory array may include a plurality of memory cells arranged into a matrix. Specifically, memory cells in the odd columns of the memory array are first memory cells and memory cells in the even columns of the memory array are second memory cells. The NVM may further include a plurality of bit lines. The bit lines may include a plurality of odd bit lines corresponding to the plurality of first memory cells and a plurality of even bit lines corresponding to the plurality of second memory cells. During a data reading operation to obtain the data information stored in the NVM, a bit line voltage may be applied only to the odd bit lines without affecting the even bit lines such that the information stored in the first memory cells may be accessed during the data reading operation. In contrast, the bit line voltage may be applied only to the even bit lines without affecting the odd bit lines such that the information stored in the second memory cells may be accessed during the data reading operation.

In conventional NVMs with both main bit lines and one or more reference bit line, the structure of the reference bit line may be different from the structure of the main bit line. Moreover, the bit line voltage may never be applied to the reference bit line, and thus the reference bit line may not be used as a main bit line.

In comparison, according to the disclosed NVM, when an odd bit line is used as a main bit line, an even bit line may be used as a reference bit line, and alternatively, when an even bit line is used as a main bit line, an odd bit line may be used as a reference bit line. In addition, the structure of the odd bit line may be identical to the structure of the even bit line while the fabrication process for the odd bit line may also be the same as the fabrication process for the even bit line. Therefore, the odd bit line and the even bit line may have similar parasitic capacitance and leakage current so that data error caused by an overly large difference in the to leakage current or the parasitic capacitance between the odd bit line and the even bit line may be avoided, and thus the data reading accuracy may be improved.

In addition, according to the present disclosure, by using an odd bit line as a main bit line and an even bit line as a reference bit line, or alternatively, using an even bit line as a main bit line and an odd bit line as a reference bit line, data stored in all memory cells of the memory array may be read out. Therefore, the disclosed NVMs may not require extra spaces for reference bit lines, and thus may be conducive to the microminiaturization of NVMs.

Further, the layout structure of the odd bit lines may be identical to the layout structure of the even bit lines and the fabrication process for the odd bit lines may be the same as the fabrication process for the even bit lines. Therefore, the layout design of the NVM and the fabrication process may be simplified.

According to the disclosed data reading method, during the data reading operation of the disclosed NVM, by applying a bit line voltage only to the odd bit lines without affecting the even bit lines, the information stored in the first memory cells may be accessed during the data reading operation; while by applying the bit line voltage only to the even bit lines without affecting the odd bit lines, the information stored in the second memory cells may be accessed during the data reading operation. That is, through the odd bit lines and the even bit lines, information of all memory cells may be read out. Compared to conventional NVMs and existing data reading methods, the disclosed NVM and the data reading method may allow an identical structure and an identical fabrication process for the odd bit lines and the even bit lines. Therefore, the odd bit line and the even bit line may have similar parasitic capacitance and leakage current so that data error caused by an overly large difference in the leakage current or the parasitic capacitance between the odd bit line and the even bit line may be avoided, and thus the data reading accuracy may be improved.