SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package includes a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, and a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core. The first gap filling portion and the second gap filling portion are directly bonded to each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0076174, filed on Jun. 14, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, the semiconductor package can include a plurality of sequentially stacked semiconductor chips and a method of manufacturing the same.

BACKGROUND

To manufacture a multi-chip package in which at least four semiconductor chips are stacked, in a die to wafer bonding process, pad-to-pad direct bonding may be performed without using solder bumps. In this case, as the number of stacked chips increases, unbonded areas (voids) may occur due to accumulation of bonding interface topology, resulting in deterioration of the bonding quality between the interfaces bonding in hybrid bonding.

SUMMARY

In general, aspects of the subject matter described in this specification can be embodied in a semiconductor package including: a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, and a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core. The first gap filling portion and the second gap filling portion are directly bonded to each other.

Another general aspect can be embodied in a semiconductor package including: a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core, and a top core die stack on the second core die stack, the top core die stack including a top core and a third gap filling portion covering an outer surface of the top core. Each of the at least one first intermediate core and the at least one second intermediate core includes a substrate, a front insulating layer provided on a front surface of the substrate and having a first bonding pad provided therein, and a backside insulating layer provided on a backside surface of the substrate and having a second bonding pad provided therein. The first gap filling portion and the second gap filling portion are directly bonded to each other.

Another general aspect can be embodied in a semiconductor package including: a buffer die, a plurality of core die stacks sequentially stacked on the buffer die, and a top core die stack stacked on an uppermost core die stack of the plurality of core die stacks. Each of the plurality of core die stacks includes at least one intermediate core and a gap filling portion covering an outer surface of the at least one intermediate core. The at least one intermediate core includes a substrate, a front insulating layer provided on a front surface of the substrate and having a first bonding pad provided therein, and a backside insulating layer provided on a backside surface of the substrate and having a second bonding pad provided therein.

Another general aspect can be embodied in a method of manufacturing a semiconductor package, where a first wafer including a buffer die formed therein is provided. A first reconstructed wafer including at least one first intermediate core and a first gap filling portion that covers an outer surface of the at least one intermediate core is formed on the first wafer. A second reconstructed wafer including at least second intermediate core and a second gap filling portion that covers an outer surface of the at least one second intermediate core is formed on a carrier substrate. The second reconstructed wafer is stacked on the first reconstructed wafer. The first gap fill portion and the second gap fill portion are directly bonded to each other.

In some implementations, a semiconductor package may include a plurality of core die stacks and a top core die stack sequentially stacked on a buffer die. Each of the core die stacks may include at least one intermediate core and a gap filling portion that covers an outer surface of the at least one intermediate core. The core die stacks may be bonded to each other through hybrid bonding. The gap filling portion of the core die stacks may be directly bonded to each other.

Each time each of the plurality of core die stacks is stacked, upper surfaces of uppermost intermediate cores may be planarized to initialize topology due to the stacking of the intermediate cores.

Accordingly, it may be possible to prevent voids from occurring at the bonding interface due to accumulation of bonding interface topology during high-level chip stacking. Thus, by using the wafer-to-wafer bonding method, costs due to an increase in the topology initialization process using a wafer support system may be reduced.

DETAILED DESCRIPTION

FIG.1is a cross-sectional view illustrating a semiconductor package.FIG.2is an enlarged cross-sectional view illustrating portion ‘A’ inFIG.1.FIG.3is an enlarged cross-sectional view illustrating portion ‘B’ inFIG.1.FIG.4is an enlarged cross-sectional view illustrating portion ‘C’ inFIG.1.

Referring toFIGS.1to4, a semiconductor package100includes semiconductor chips (core dies)20stacked therein. The semiconductor package100includes a buffer die10, and first to fourth core die stacks DS1, DS2, DS3, and DS4and a top core die stack DS5sequentially stacked on the buffer die10.

A plurality of semiconductor chip cores (dies)20a,20b,20c,20d,20e,20f,20g,and20hare stacked vertically. In this example, the semiconductor chips (dies)20a,20b,20c,20d,20e,20f,20g,and20hare substantially the same as or similar to each other. Accordingly, same or like reference numerals will be used to refer to the same or like elements and repeated descriptions of the same elements may be omitted.

In this example, the semiconductor package as a multi-chip package is illustrated as including eight stacked semiconductor chips, e.g., cores20a,20b,20c,20d,20e,20f,20g,and20h, on the buffer die10, however, the number is not limited thereto. For example, the semiconductor package may include 4, 12, or 16 stacked semiconductor chips.

Each of the semiconductor chips, e.g., cores20a,20b,20c,20d,20e,20f,20gand20h, may include an integrated circuit chip completed by performing semiconductor manufacturing processes. Each semiconductor chip may include, for example, a memory chip or a logic chip. The semiconductor package100may include a memory device. The memory device may include a high bandwidth memory (HBM) device.

In some implementations, a buffer die10may include a substrate11, a front insulating layer12, a plurality of first bonding pads13, a plurality of through electrodes14, and a backside insulating layer16, and a plurality of second bonding pads17. Additionally, the buffer die10may further include conductive bumps40as conductive connection members respectively provided on the first bonding pads13. The buffer die10may be mounted on a package substrate or an interposer via the conductive bumps40. For example, the conductive bump40may include a solder bump. Alternatively, the conductive bump40may include a pillar bump and a solder bump formed on the pillar bump.

The substrate11may have a first surface112and a second surface114opposite to the first surface112. The first surface112may be an active surface, and the second surface114may be a non-active surface. Circuit patterns may be provided on the first surface112of the substrate11. The first surface112may be referred to as a front surface on which the circuit patterns are formed, and the second surface may be referred to as a backside surface.

For example, the substrate11may be a single crystal silicon substrate. The circuit patterns may include transistors, capacitors, diodes, and other suitable/desired components. The circuit patterns may constitute circuit elements. Accordingly, the buffer die10may be a semiconductor device having a plurality of circuit elements formed therein.

As illustrated inFIG.2, the front insulating layer12as an insulation interlayer is formed on the first surface112of the substrate11, e.g., the front surface. The front insulating layer12includes a plurality of insulating layers222and224and wirings123in the insulating layers. Additionally, the first bonding pad13may be provided in an outermost insulating layer of the front insulating layer12.

For example, the front insulating layer12may include a metal wiring layer122and a first passivation layer124. The metal wiring layer122may include a plurality of wirings123therein. For example, the metal wiring layer122may include a metal interconnection structure including a plurality of wirings123vertically stacked in buffer layers and insulating layers. The first bonding pad13may be formed on an uppermost wiring among the plurality of wirings123. For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

The first passivation layer124may be formed on the metal wiring layer122and may expose at least a portion of the first bonding pad13. The first passivation layer124may include a plurality of stacked insulating layers. For example, the first passivation layer224may include a first protective layer including an oxide layer and a second protective layer including a nitride layer, sequentially stacked. The first protective layer may include silicon oxide, and the second protective layer may include silicon nitride or silicon carbonitride.

The first bonding pad13may be provided in the first passivation layer124. The first bonding pad13may be exposed through an outer surface of the first passivation layer124. In some implementations, an insulation interlayer may be provided on the first surface112of the substrate11to cover the circuit patterns. The insulation interlayer may be formed to include, for example, silicon oxide or a low dielectric material. The insulation interlayer may include lower wiring therein, which are electrically connected to the circuit patterns. Accordingly, the circuit pattern may be electrically connected to the first bonding pad13by the lower wirings and the wirings.

The through electrode (through silicon via, TSV)14may vertically penetrate the insulation interlayer and extend from the first surface112to the second surface114of the substrate11. The through electrode14may contact a lowermost wiring of the metal wiring structure. Accordingly, the through electrode24may be electrically connected to the first bonding pad13by the wirings123.

The backside insulating layer16may be formed on the second surface114of the substrate11, e.g., the backside surface. The second bonding pad17may be provided in the backside insulating layer16. For example, the second bonding pad17may be disposed on an exposed surface of the through electrode14. The backside insulating layer16may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), and other suitable/desired materials. Accordingly, the first and second bonding pads13and17may be electrically connected to each other by the through electrode24.

In some implementations, each of the first to fourth core die stack DS1, DS2, DS3, and DS4may include at least one intermediate core, e.g., second semiconductor chip20, and a gap filling portion30that covers an outer surface of the at least one intermediate core, e.g., second semiconductor chip20. The at least one intermediate core, e.g., second semiconductor chip20, may include a substrate21, a front insulating layer22provided on a front surface of the substrate21and in which a first bonding pad23is provided, and a backside insulating layer26provided on a backside surface of the substrate21and in which a second bonding pad27is provided. In addition, the at least one intermediate core, e.g., second semiconductor chip20, may further include a through electrode24that penetrates the substrate21and is electrically connected to the first and second bonding pads23and27.

In particular, the first core die stack DS1may be bonded onto the buffer die10. The first core die stack DS1may include first intermediate cores20aand20bstacked in two stages and a first gap filling portion30-1covering outer surfaces of the first intermediate cores20aand20b.

As illustrated inFIGS.2and3, the first-stage first intermediate core20aof the first core die stack DS1may include a substrate21a,a front insulating layer22a,and a plurality of first bonding pads23a,a plurality of through electrodes24a,a backside insulating layer26aand a plurality of second bonding pads27a.

The substrate21amay have a first surface212aand a second surface214aopposite to the first surface212a.The first surface212amay be an active surface, and the second surface214amay be a non-active side. Circuit patterns may be provided on the first surface212aof the substrate21a.The front insulating layer22aas an insulation interlayer may be formed on the first surface212aof the substrate21a,e.g., a front surface. The front insulating layer22amay include a plurality of insulating layers222aand224aand wirings223ain the insulating layers222and224. Additionally, the first bonding pad23amay be provided in an outermost insulating layer of the front insulating layer22a.For example, the front insulating layer22amay include a metal wiring layer222aand a first passivation layer224a.The metal wiring layer222amay include a plurality of wirings223atherein.

The through electrode24amay vertically extend from the first surface212ato the second surface214aof the substrate21a.The through electrode24amay be electrically connected to the first bonding pad23aby the wirings223a.The backside insulating layer26amay be formed on the second surface214aof the substrate21a,e.g., a backside surface. The second bonding pad27amay be provided in the backside insulating layer26a.Accordingly, the first and second bonding pads23aand27amay be electrically connected to each other by the through electrode24a.

Similarly, the second-stage first intermediate core20bof the first core die stack DS1may include a substrate21b,a front insulating layer22b,a plurality of first bonding pads23b,a plurality of through electrodes24b,a backside insulating layer26b,and a plurality of second bonding pads27b.Since the cores20a,20b,20c,20d,20e,20f,20g,and20hare substantially the same as or similar to each other, same or like reference numerals will be used to refer to the same or like elements and repeated descriptions of the same elements may be omitted.

As illustrated inFIG.2, the first-stage first intermediate core20aand the buffer die10may be bonded to each other by hybrid bonding. The second bonding pad17of the buffer die10and the first bonding pad23aof the first intermediate core20amay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding). The front surface of the first intermediate core20a,e.g., the front side insulating layer22aon the first surface212aof the substrate21amay be directly bonded to the backside insulating layer16of the substrate11of the buffer die10.

As illustrated inFIG.3, the second-stage first intermediate core20band the first-stage first intermediate core20amay be bonded to each other by hybrid bonding. The second bonding pad27aof the first-stage first intermediate core20aand the first bonding pad23bof the second-stage first intermediate core20bmay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

The front insulating layer22bon the front surface of the second-stage first intermediate core die20bmay be directly bonded to the backside insulating layer26aon the backside surface of the first-stage first intermediate core die20a.The outermost insulating layers of the backside insulating layer26aand the front insulating layer22bmay include an insulating material that contacts each other and provides excellent bonding strength, thereby providing a bonding structure. The backside insulating layer26aand the front insulating layer22bmay be bonded to each other by a high temperature annealing process while in contact with each other. Here, the bonding structure may have a relatively stronger bonding strength due to covalent bonding.

The first gap filling portion30-1may be provided to cover the outer surfaces of the first intermediate cores20aand20bstacked in two stages on the buffer die10. For example, the first gap filling portion30-1may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The first gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like.

In some implementations, the second core die stack DS2may be bonded onto the first core die stack DS1. The second core die stack DS2may include second intermediate cores20c,20dstacked in two stages and a second gap filling portion30-2covering outer surfaces of the second intermediate cores20cand20d.

The second-stage second intermediate core20dand the first-stage second intermediate core20cmay be bonded to each other by hybrid bonding. A second bonding pad27cof the first-stage second intermediate core20cand a first bonding pad23dof the second-stage second intermediate core20dmay be bonded to each other by copper-copper hybrid bonding. A front side insulating layer22don a front surface of the second-stage intermediate core20dmay be directly bonded to a backside insulating layer26con a backside surface of the first-stage second intermediate core20c.

The first-stage second intermediate core20cof the second core die stack DS2and the second-stage first intermediate core20bof the first core die stack DS1may be bonded to each other by hybrid bonding. The second bonding pad27bof the first intermediate core20band a first bonding pad23cof the second intermediate core20cmay be bonded to each other by copper-copper hybrid bonding. A front insulating layer22con a front surface of the second intermediate core20cmay be directly bonded to the backside insulating layer26bon the backside surface of the first intermediate core20b.

The second gap filling portion30-2may be provided to cover the outer surfaces of the second intermediate cores20cand20dstacked in two stages. For example, the second gap filling portion30-2may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The second gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like.

As illustrated inFIG.4, when the second core die stack DS2and the first core die stack DS1are bonded to each other, the second gap filling portion30-2of the second core die stack DS2and the first gap filling portion30-1of the first core die stack DS1may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the first gap filling portion30-1and the second gap filling portion30-2may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide. The bonding interface layer may be detected by a transmission electron microscope (TEM).

In some implementations, the third core die stack DS3may be bonded onto the second core die stack DS2. The third core die stack DS3may include third intermediate cores20eand20fstacked in two stages and a third gap filling portion30-3covering outer surfaces of the third intermediate cores20eand20f.

The second-stage third intermediate core20fand the first-stage third intermediate core20emay be bonded to each other by hybrid bonding. The first-stage third intermediate core20eof the third core die stack DS3and the second-stage second intermediate core20dof the second core die stack DS2may be bonded to each other by hybrid bonding.

The third gap filling portion30-3may be provided to cover the outer surfaces of the third intermediate cores20eand20fstacked in two stages. For example, the third gap filling portion may include an inorganic dielectric layer or an organic dielectric layer.

When the third core die stack DS3and the second core die stack DS2are bonded to each other, the third gap filling portion30-3of the third core die stack DS3and the second gap filling portion30-2of the second core die stack DS2may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the second gap filling portion30-2and the third gap filling portion30-3may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may include silicon oxide.

In some implementations, the fourth core die stack DS4may be bonded onto the third core die stack DS2. The fourth core die stack DS4may include a fourth intermediate core20gstacked in one stage and a fourth gap filling portion30-4covering an outer surface of the fourth intermediate core20g.

The fourth intermediate core20gof the fourth core die stack DS4and the third intermediate core20fof the third core die stack DS3may be bonded to each other by hybrid bonding. The fourth gap filling portion30-4may be provided to cover the outer surface of the fourth intermediate core20g.For example, the fourth gap filling portion may include an inorganic dielectric layer or an organic dielectric layer.

When the fourth core die stack DS4and the third core die stack DS3are bonded to each other, the fourth gap filling portion30-4of the fourth core die stack DS4and the third gap filling portion30-3of the third core die stack DS3may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the third gap filling portion30-3and the fourth gap filling portion30-4may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may include silicon oxide.

The top core20hof the top core die stack DS5and the fourth intermediate core20hof the fourth core die stack DS4may be bonded to each other by hybrid bonding. The fifth gap filling portion30-5may be provided to cover the outer surface of the top core20h.For example, the fifth gap filling portion30-5may include an inorganic dielectric layer or an organic dielectric layer.

When the top core die stack DS5and the fourth core die stack DS4are bonded to each other, the fifth gap filling portion30-5of the top core die stack DS5and the fourth gap filling portion30-4of the fourth core die stack DS4may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the fourth gap filling portion30-4and the fifth gap filling portion30-5may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may include silicon oxide.

In some implementations, a width of buffer die10may be the same as widths of the first to fourth core die stacks DS1, DS2, DS3, and DS4. The widths of the first to fourth core die stacks DS1, DS2, DS3, and DS4may be the same as a width of the top core die stack DS5. The width of the buffer die10may be the same as the width of the top core die stack DS5.

The outer surfaces of the first to fourth core die stacks DS1, DS2, DS3, and DS4and the outer surface of the top core die stack DS5may be positioned on the same plane. The outer surfaces of the first to fourth gap filling portions30-1,30-2,30-3, and30-4of the first to fourth core die stacks DS1, DS2, DS3, and DS4may be coplanar with an outer surface of the fifth gap filling portion30-5of the top core die stack DS5.

As mentioned above, the semiconductor package100may include the first to fourth core die stacks DS1, DS2, DS3, and DS4and the top core die stack DS5sequentially stacked on the buffer die10. Each of the first to fourth core die stacks DS1, DS2, DS3and DS4may include the at least one intermediate core20aand the gap filling portion30covering the outer surface of the at least one intermediate core, e.g., second semiconductor chip20.

The first to fourth core die stacks DS1, DS2, DS3, and DS4may be bonded to each other by hybrid bonding. The gap filling portions30-1,30-2,30-3, and30-4of the first to fourth core die stacks DS1, DS2, DS3, and DS4may be directly bonded to each other. The gap filling portions may include an inorganic dielectric layer or an organic dielectric layer. The gap filling portions may be directly bonded to each other to form the bonding interface layer32.

The first to fourth core die stacks DS1, DS2, DS3, and DS4may be bonded to each other. Each time each of the first to fourth core die stacks DS1, DS2, DS3, and DS4is stacked, the upper surfaces of the uppermost intermediate cores may be planarized to initialize topology due to the stacking of the intermediate cores.

Accordingly, it may be possible to prevent voids from occurring at the bonding interface due to accumulation of bonding interface topology during high-level chip stacking. Thus, by using the wafer-to-wafer bonding method, costs due to an increase in the topology initialization process using a wafer support system WSS may be reduced.

Hereinafter, a method of manufacturing the semiconductor package ofFIG.1will be described. A case where the semiconductor package includes a high bandwidth memory (HBM) device will be described. However, it will be understood that a method of manufacturing a semiconductor package is not limited thereto.

FIGS.5to28are views illustrating an example of a method of manufacturing a semiconductor package.FIG.6is an enlarged cross-sectional view illustrating portion ‘D’ inFIG.5.FIG.8is an enlarged cross-sectional view illustrating portion ‘E’ inFIG.7.FIG.10is an enlarged cross-sectional view illustrating portion ‘F’ inFIG.9.FIG.14is an enlarged cross-sectional view illustrating portion ‘G’ inFIG.13.FIG.16is an enlarged cross-sectional view illustrating portion ‘H’ inFIG.15.

Referring toFIGS.5to12, first, a second wafer W2may be individualized into semiconductor chips (core dies)20.

As illustrated inFIGS.5and6, the second wafer W2including a plurality of semiconductor chips (core dies) formed therein may be prepared.

In some implementations, the second wafer W2may include a substrate21and a front insulating layer22having a first bonding pad23that is provided in an outer surface thereof. Additionally, the second wafer W2may include a plurality of through electrodes24that are provided in the substrate21and are electrically connected to the first bonding pads23.

The substrate21may have a first surface212and a second surface214opposite to each other. The substrate21may include a die region DA where circuit patterns and cells are formed and a scribe lane region SA surrounding the die region DA. The substrate21may be cut along the scribe lane region SA that divides the plurality of die regions DA of the second wafer W2by a following dicing process to form individualized semiconductor chips.

The circuit patterns may include transistors, capacitors, diodes, and other suitable/desired electronic components. The circuit patterns may constitute circuit elements. Accordingly, the semiconductor chip may be a semiconductor device with a plurality of the circuit elements formed therein. The circuit patterns may be formed on the first surface212of the substrate21by performing a FEOL (Front End of Line) process for manufacturing semiconductor devices. The surface of the substrate on which the FEOL process is performed may be referred to as a front surface of the substrate, and a surface opposite to the front surface may be referred to as a backside surface.

The circuit element may include a plurality of memory devices. Examples of the memory devices include a volatile semiconductor memory device and a non-volatile semiconductor memory device. Examples of the volatile semiconductor memory device may be DRAM, SRAM, and other types of memory devices. Examples of the non-volatile semiconductor memory devices may be EPROM, EEPROM, Flash EEPROM, and other types of memory devices.

The front insulating layer22may be formed as an insulation interlayer on the first surface212of the substrate21, e.g., the front surface. The front insulating layer22may include a plurality of insulating layers122and124and wirings223in the insulating layers. Additionally, the first bonding pad23may be provided in the outermost insulating layer of the front insulating layer22.

As illustrated inFIG.6, for example, the front insulating layer22may include a metal wiring layer222and a first passivation layer224.

The metal wiring layer222may include the plurality of wirings223therein. For example, the metal wiring layer222may include a metal wiring structure including the plurality of wirings223vertically stacked in buffer layers and insulating layers. The first bonding pad23may be formed on an uppermost wiring among the plurality of wirings223. For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

The first passivation layer224may be formed on the metal wiring layer222and may expose at least a portion of the first bonding pad23. The first passivation layer224may include a plurality of stacked insulating layers. For example, the first passivation layer224may include a first protective layer including an oxide layer and a second protective layer including a nitride layer, sequentially stacked. The first protective layer may include silicon oxide, and the second protective layer may include silicon nitride or silicon carbonitride.

The first bonding pad23may be provided in the first passivation layer224. The first bonding pad23may be exposed from an outer surface of the first passivation layer224. In some implementations, an insulation interlayer may be provided on the first surface212of the substrate21to cover the circuit patterns. The insulation interlayer may be formed to include, for example, silicon oxide or a low dielectric material. The insulation interlayer may include lower wirings therein, which are electrically connected to the circuit patterns. Accordingly, the circuit pattern may be electrically connected to the first bonding pad23by the lower wirings and the wirings.

The through electrode (through silicon via, TSV)24may vertically penetrate the insulation interlayer and extend from the first surface212of the substrate21to a predetermined depth. The through electrode24may contact a lowermost wiring of the metal wiring structure. Accordingly, the through electrode24may be electrically connected to the first bonding pad23by the wirings223.

In some implementations, a liner layer may be provided on an outer surface of the through electrode24. The liner layer may include silicon oxide or carbon-doped silicon oxide. The liner layer may electrically insulate the through electrode24from the substrate21and the metal wiring layer222.

The through electrode24and the first bonding pad23may include a same metal. For example, the metal may include copper (Cu). However, it is not limited thereto, and the through electrode and the first bonding pad may include a material (e.g., gold (Au)) that can be bonded by inter-diffusion of metals by a high-temperature annealing process.

As illustrated inFIGS.7and8, the second surface214of the substrate21may be partially removed to expose one end portion of the through electrode24.

In some implementations, the second surface214of the substrate21may be partially removed using a substrate support system (WSS). First, the second wafer (W2) may be attached to a carrier substrate C1using an adhesive film, and then, the second surface214of the substrate21may be partially removed until the end portion of the through electrode24is exposed.

In particular, a grinding process such as a back lap process may be performed to partially remove the second surface214of the substrate21, and then an etching process such as a silicon recess process may be performed to expose the end portion of the through electrode24. Accordingly, a thickness of the substrate21may be reduced to a desired thickness. For example, the substrate21may have the thickness in a range of about 20 μm to about 50 μm.

In the back lap process, the entire backside surface of the second wafer W2may be grinded. In the silicon recess process, only the silicon in the backside surface of the second wafer W2may be selectively etched. The etching process may be an isotropic dry etching process. The etching process may include a plasma etching process or a similar method. The plasma etching process may be performed using inductively coupled plasma, capacitively coupled plasma, microwave plasma, and other types of plasma.

Since the grinding process and the etching process are performed in the wafer level, the entire second surface214of the substrate21may be reduced to a uniform thickness. Accordingly, the end portions of the through electrodes24may protrude uniformly from the second surface214of the substrate21across the entire second surface214of the substrate21to have same heights.

As illustrated inFIGS.9and10, a backside insulating layer26having a second bonding pad27in an outer surface thereof may be formed on the second surface214of the substrate21.

For example, an etch stop layer may be formed on the second surface214of the substrate21, and a sacrificial layer may be formed on the etch stop layer. The etch stop layer may be conformally formed to cover the end portions of the through electrodes24that protrude from the second surface214of the substrate21. The etch stop layer may cover the entire second surface214of the substrate21. For example, the etch stop layer may have a thickness within a range of 0.1 μm to 1 μm. The etch stop layer may include a material that can be used to detect a polishing end point in a subsequent chemical mechanical polishing process. The etch stop layer may include a silicon nitride layer. The thickness and material of the etch stop layer may be selected in consideration of a polishing selectivity and polishing conditions in the subsequent chemical mechanical polishing process.

The sacrificial layer may be formed on the etch stop layer to fill a gap between the protruding end portions of the through electrodes24. The sacrificial layer may include silicon oxide such as tetraethyl orthosilicate (TEOS).

Then, a chemical mechanical polishing (CMP) process may be performed to remove the sacrificial layer to expose the end portions of the through electrodes24. In the chemical mechanical polishing (CMP) process, the etch stop layer may be used to detect a polishing end point. Through the CMP process, the end portions of the through electrodes24and portions of the etch stop layer covering the end portions of the through electrodes24may be removed to form an etch stop layer pattern25on the second surface214of the substrate21.

The etch stop layer pattern25may expose the end portions of the through electrodes24. The end portions of the through electrodes24may protrude from the second surface214of the substrate21, and the etch stop layer pattern25may cover sidewalls of the end portions of the through electrodes that protrude from the second surface214of the substrate210. Accordingly, upper surfaces of the through electrodes24may be exposed by the etch stop layer pattern25. An upper surface of the etch stop layer pattern25and the exposed upper surfaces of the through electrodes24may be positioned on the same plane.

Then, the backside insulating layer26as a second passivation layer may be formed on the etch stop layer pattern25on the second surface214of the substrate21. The backside insulating layer26may have the second bonding pad27that is electrically connected to the through electrode24.

For example, after the backside insulating layer26is formed on the etch stop layer pattern25on the second surface214of the substrate21, an opening may be formed in the backside insulating layer26to expose the through electrode24, and a plating process may be performed to form the second bonding pad27in the opening of the backside insulating layer26. The second bonding pad27may be disposed on the exposed surface of the through electrode24. The backside insulating layer26may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), and other suitable/desired materials. Accordingly, the first and second bonding pads23and27may be electrically connected to each other by the through electrode24.

Referring toFIGS.11and12, the second wafer W2may be cut along the scribe lane region SA to form individual second semiconductor chips (core dies)20. The individual second semiconductor chip20may be separated from the carrier substrate C1.

Referring toFIGS.13to17, a first reconstructed wafer RW1including at least one first intermediate core20aand20band a first gap filling portion30-1covering an outer surface of the at least one first intermediate core20aand20bmay be formed on a first wafer W1. In this example, the first reconstructed wafer RW1may include, but is not limited to, the first intermediate cores20aand20bstacked in two stages.

As illustrated inFIGS.13and14, a plurality of the first intermediate cores20amay be attached in a first stage on the first wafer W1(die-to-wafer hybrid bonding process).

In some implementations, the first intermediate cores20amay be disposed on the first wafer W1to correspond to die region DA. The first intermediate core20amay be stacked such that a first surface212aof a substrate21afaces the first wafer W1.

A die bonding apparatus may pick up the first intermediate core20aseparated by a sawing process and may bond the first intermediate core20ato the first wafer W1. The die bonding apparatus may attach the first intermediate core20ato the first wafer W1by performing a thermal compression process at a predetermined temperature (for example, about 400° C. or less). By the thermal compression process, the first intermediate core20aand the first wafer W1may be bonded to each other through hybrid bonding. That is, a front surface of the first intermediate core20a, e.g., a front side insulating layer22aon the first surface212aof the substrate21amay be directly bonded to a backside insulating layer16on a substrate11of the first wafer W1.

A second bonding pad17of the first wafer W1and a first bonding pad23aof the first intermediate core20amay make contact with each other. The front surface of the first intermediate core20aand a backside surface of the first wafer W1may be bonded to face each other. When the first wafer W1and the first intermediate core20aare bonded to each other by wafer-to-die bonding, the second bonding pad17of the first wafer W1and the first bonding pads23aof the first intermediate core20amay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

As illustrated inFIGS.15and16, processes the same as or similar to the processes described with reference toFIGS.13and14may be performed to attach a plurality of first intermediate cores20bin a second stage on the plurality of first-stage first intermediate cores20aon the first wafer W1(die-to-wafer hybrid bonding process).

A front surface of the second-stage first intermediate core20bmay be stacked to face the backside surface of the first-stage first intermediate core20a.By a thermal compression process, the second-stage first intermediate core20band the first-stage first intermediate core20amay be bonded to each other through hybrid bonding. That is, a front insulating layer22bon the front surface of the second-stage first intermediate core20bmay be directly bonded to a backside insulating layer26aon the backside surface of the first-stage first intermediate core20a.When the first-stage first intermediate core20aand the second-stage first intermediate core20bare bonded to each other by die-to-die bonding, a second bonding pad27aof the first-stage first intermediate core20aand a first bonding pad23bof the second-stage first intermediate core20bmay be bonded to each other by copper-copper hybrid bonding.

As illustrated inFIG.17, the first gap filling portion30-1may be formed to fill gaps between the first intermediate cores20aand20bstacked in two stages on the first wafer W1.

A filling layer may be formed to cover the first intermediate cores20aand20bstacked in two stages on the first wafer W1, and an upper portion of the filling layer may be removed to form the first gap filling portion30-1that exposes upper surfaces of the second-stage first intermediate cores20b.For example, the first gap filling portion30-1may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The first gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like. The upper portion of the filling layer may be removed by a chemical mechanical polishing process or a mechanical grinding process.

Then, an upper surface of the first reconstructed wafer RW1, e.g., the upper surfaces of the second-stage first intermediate cores20b,may be planarized to initialize a topology due to the stacking of the first intermediate cores20aand20b.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the second-stage first intermediate cores20b(topology reset process).

Accordingly, the first reconstructed wafer RW1including the first intermediate cores20aand20bstacked in two stages and the first gap filling portion30-1covering the outer surfaces of the first intermediate cores20aand20bmay be formed.

Referring toFIGS.18to20, a second reconstructed wafer RW2including at least one second intermediate core20cand20dand a second gap filling portion30-2covering an outer surface of the at least one second intermediate core20cand20dmay be formed on a carrier substrate C2. In this example, the second reconstructed wafer RW2may include, but is not limited to, the second intermediate cores20cand20dstacked in two stages.

As illustrated inFIG.18, a plurality of the second intermediate cores20dmay be attached in a first stage on the carrier substrate C2.

In some implementations, the second intermediate cores20dmay be disposed on the carrier substrate C2to correspond to die region DA. The second intermediate cores20dmay be attached to the carrier substrate C2using an adhesive film or an oxide layer. The second intermediate core20dmay be stacked such that a second surface214dof a substrate21dfaces the carrier substrate C2.

As illustrated inFIG.19, processes the same as or similar to the processes described with reference toFIGS.13and14may be performed to attach a plurality of second intermediate cores20cin a second stage on the plurality of first-stage second intermediate cores20don the carrier substrate C2(die-to-wafer hybrid bonding process).

A backside surface of the second-stage second intermediate core20cmay be stacked to face a front surface of the first-stage second intermediate core20c.By a thermal compression process, the second-stage second intermediate core20cand the first-stage second intermediate core20dmay be bonded to each other through hybrid bonding. That is, a backside insulating layer26con the backside surface of the second-stage second intermediate core20cmay be directly bonded to a front side insulating layer22don the front surface of the first-stage second intermediate core20d.When the first-stage second intermediate core20dand the second-stage second intermediate core20care bonded to each other by die-to-die bonding, a first bonding pad23dof the first-stage second intermediate core20dand a second bonding pad27dof the second-stage second intermediate core20cmay be bonded to each other by copper-copper hybrid bonding.

As illustrated inFIG.20, processes the same as or similar to the processes described with reference toFIG.17may be performed to form the second gap filling portion30-2that fills gaps between the second intermediate cores20cand20dstacked in two stages on the carrier substrate C2.

A filling layer may be formed to cover the second intermediate cores20cand20dstacked in two stages on the carrier substrate C2, and an upper portion of the filling layer may be removed to form the second gap filling portion30-2that exposes upper surfaces of the second-stage second intermediate cores20c.For example, the second gap filling portion30-2may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The second gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like. The upper portion of the filling layer may be removed by a chemical mechanical polishing process or a mechanical grinding process.

Then, an upper surface of the second reconstructed wafer RW2, e.g., the upper surfaces of the second-stage second intermediate cores20c,may be planarized to initialize a topology due to the stacking of the second intermediate cores20cand20d.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the second-stage second intermediate cores20c(topology reset process).

Accordingly, the second reconstructed wafer RW2including the second intermediate cores20cand20dstacked in two stages and the second gap filling portion30-2covering the outer surfaces of the second intermediate cores20cand20dmay be formed.

Referring toFIGS.21and22, the second reconstructed wafer RW2may be attached to the first reconstructed wafer RW1on the first wafer W1(wafer-to-wafer hybrid bonding process).

As illustrated inFIG.21, the second reconstructed wafer RW2ofFIG.20may be bonded to the first reconstructed wafer RW1on the first wafer W1. A front surface of the second intermediate core20cof the second reconstructed wafer RW2may be stacked to face the backside surface of the first intermediate core20bof the first reconstructed wafer RW1.

When the second reconstructed wafer RW2and the first reconstructed wafer RW1are bonded to each other by wafer-to-wafer bonding, the second intermediate core20cof the second reconstructed wafer RW2and the first intermediate core20bof the first reconstructed wafer RW1may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22con the front surface of the second intermediate core20cmay be directly bonded to a backside insulating layer26bon the backside surface of the first intermediate core20b,and a second bonding pad27bof the first intermediate core20band a first bonding pad23cof the second intermediate core20cmay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the second reconstructed wafer RW2and the first reconstructed wafer RW1are bonded to each other by wafer-to-wafer bonding, the second gap filling portion30-2of the second reconstructed wafer RW2and the first gap filling portion30-1of the first reconstructed wafer RW1may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the first gap filling portion30-1and the second gap filling portion30-2may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

As illustrated inFIG.22, the carrier substrate C2may be removed to expose the backside surfaces of the second intermediate cores20dof the second reconstructed wafer RW2. At this time, upper surfaces (backside surfaces) of the second intermediate cores20dmay be planarized to initialize a topology due to the stacking of the second intermediate cores20cand20d.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the second intermediate cores20d(topology reset process).

Referring toFIG.23, processes the same as or similar to the processes described with reference toFIGS.18to20may be performed to form a third reconstructed wafer RW3including at least one third intermediate core20e,20fand a third gap filing portion30-3covering an outer surface of the at least one third intermediate core20e,20fon a carrier substrate, and processes the same as or similar to the processes described with reference toFIGS.21and22may be performed to attach the third reconstructed wafer RW3to the second reconstructed wafer RW2(wafer-to-wafer hybrid bonding process).

In some implementations, the third intermediate cores20e,20fmay be stacked in two stages on the carrier substrate and a filling layer may be formed to cover the third intermediate cores20eand20f,and an upper portion of the filling layer may be removed to form the third gap filling portion30-3that exposes upper surfaces of the second-stage third intermediate cores20c. Then, upper surfaces of the second-stage third intermediate cores20emay be planarized to initialize a topology due to the stacking of the third intermediate cores20eand20fFor example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the third-stage third intermediate cores20e(topology reset process).

Then, the third reconstructed wafer RW3may be stacked on the second reconstruction wafer RW2such that a front surface of the third intermediate core20eof the third reconstructed wafer RW3faces the backside surface of the second intermediate core20dof the second reconstructed wafer RW2.

When the third reconstructed wafer RW3and the second reconstructed wafer RW2are bonded to each other by wafer-to-wafer bonding, the third intermediate core20eof the third reconstructed wafer RW3and the second intermediate core20dof the second reconstructed wafer RW2may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22eon the front surface of the third intermediate core20emay be directly bonded to a backside insulating layer26don the backside surface of the second intermediate core20d,and a second bonding pad27dof the second intermediate core20dand a first bonding pad23eof the third intermediate core20emay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the third reconstructed wafer RW3and the second reconstructed wafer RW2are bonded to each other by wafer-to-wafer bonding, the third gap filling portion30-3of the third reconstructed wafer RW2and the second gap filling portion30-2of the second reconstructed wafer RW2may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the second gap filling portion30-2and the third gap filling portion30-3may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

Then, the carrier substrate may be removed to expose the backside surfaces of the third intermediate cores20fof the third reconstructed wafer RW3. At this time, upper surfaces (backside surfaces) of the third intermediate cores20fmay be planarized to initialize a topology due to the stacking of the third intermediate cores20eand20fFor example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the third intermediate cores20f(topology reset process).

Referring toFIG.24, a fourth reconstructed wafer RW4including at least one fourth intermediate core20gand a fourth gap filling portion30-4covering an outer surface of the at least one fourth intermediate core20gmay be formed on a carrier substrate C3. In this example, the fourth reconstructed wafer RW4may include, but is not limited to, the fourth intermediate cores20gstacked in one stage.

In some implementations, a plurality of the fourth intermediate cores20gmay be attached in one stage on the carrier substrate C3.

In particular, the fourth intermediate cores20gmay be disposed on the carrier substrate C3to correspond to die region DA. The fourth intermediate core20gmay be stacked such that a second surface214gof a substrate21gof the fourth intermediate core20gfaces the carrier substrate C3.

Then, the fourth filling portion30-4may be formed to fill gaps between the fourth intermediate cores20gstacked in one stage on the carrier substrate C3. A filling layer may be formed to cover the fourth intermediate cores20gstacked in one stage on the carrier substrate C3, and an upper portion of the filling layer may be removed to form the fourth gap filling portion30-4that exposes upper surfaces of the first-stage fourth intermediate cores20g.For example, the fourth gap filling portion30-4may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The fourth gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like. The upper portion of the filling layer may be removed by a chemical mechanical polishing process or a mechanical grinding process.

Accordingly, the fourth reconstructed wafer RW4including the fourth intermediate cores20gstacked in one stage and the fourth gap filling portion30-4covering the outer surfaces of the fourth intermediate cores20gmay be formed.

Referring toFIG.25, the fourth reconstructed wafer RW4may be attached to the third reconstructed wafer RW3(wafer-to-wafer hybrid bonding process).

In some implementations, the fourth reconstructed wafer RW4may be stacked on the third reconstruction wafer RW3such that a front surface of the fourth intermediate core20gof the fourth reconstructed wafer RW4faces the backside surface of the third intermediate core20fof the third reconstructed wafer RW3.

When the fourth reconstructed wafer RW4and the third reconstructed wafer RW3are bonded to each other by wafer-to-wafer bonding, the fourth intermediate core20gof the fourth reconstructed wafer RW3and the third intermediate core20fof the third reconstructed wafer RW3may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22gon the front surface of the fourth intermediate core20gmay be directly bonded to the backside insulating layer26gon the backside surface of the third intermediate core20f,and a second bonding pad27fof the third intermediate core20fand a first bonding pad23gof the fourth intermediate core20gmay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the fourth reconstructed wafer RW4and the third reconstructed wafer RW3are bonded to each other by wafer-to-wafer bonding, the fourth gap filling portion30-4of the fourth reconstructed wafer RW4and the third gap filling portion30-3of the third reconstructed wafer RW3may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the third gap filling portion30-3and the fourth gap filling portion30-4may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

Then, the carrier substrate C3may be removed to expose the backside surfaces of the fourth intermediate cores20gof the fourth reconstructed wafer RW4. At this time, upper surfaces (backside surfaces) of the fourth intermediate cores20gmay be planarized to initialize a topology due to the stacking of the fourth intermediate cores20g.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the fourth intermediate cores20g(topology reset process).

Referring toFIG.26, a fifth reconstructed wafer RW5including a top core20hand a fifth gap filing portion30-5covering an outer surface of the top core20hmay be formed on a carrier substrate C4.

In some implementations, a plurality of the top cores20hmay be attached in one stage on the carrier substrate C4. A thickness of the top core20hmay be greater than thicknesses of the intermediate cores. The thickness of the top core20hmay be in a range of 100 μm to 300 μm. The thicknesses of the intermediate core dies20a,20b,and20cmay be in a range of 20 μm to 50 μm.

In particular, the top cores20hmay be disposed on the carrier substrate C4to correspond to die region DA. The top cores20hmay be attached to the carrier substrate C4using an adhesive film or an oxide layer. The top core20hmay be stacked such that a second surface214hof a substrate21hof the top core20hfaces the carrier substrate C4.

Then, the fifth filling portion30-5may be formed to fill gaps between the top cores20hstacked in one stage on the carrier substrate C4. A filling layer may be formed to cover the top cores20hstacked in one stage on the carrier substrate C4, and an upper portion of the filling layer may be removed to form the fifth gap filling portion30-5that exposes upper surfaces of the top cores20h.For example, the fifth gap filling portion30-5may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The fifth gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like. The upper portion of the filling layer may be removed by a chemical mechanical polishing process or a mechanical grinding process.

Accordingly, the fifth reconstructed wafer RW5including the top cores20hstacked in one stage and the fifth gap filling portion30-5covering the outer surfaces of the top cores20hmay be formed.

Referring toFIG.27, the fifth reconstructed wafer RW5may be attached to the fourth reconstructed wafer RW4(wafer-to-wafer hybrid bonding process).

In some implementations, the fifth reconstructed wafer RW5may be stacked on the fourth reconstruction wafer RW4such that a front surface of the top core20hof the fifth reconstructed wafer RW5faces the backside surface of the fourth intermediate core20gof the fourth reconstructed wafer RW4.

When the fifth reconstructed wafer RW5and the fourth reconstructed wafer RW4are bonded to each other by wafer-to-wafer bonding, the top core20hof the fifth reconstructed wafer RW4and the fourth intermediate core20gof the fourth reconstructed wafer RW4may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22hon the front surface of the top core20hmay be directly bonded to the backside insulating layer26hon the backside surface of the fourth intermediate core20g,and a second bonding pad27gof the fourth intermediate core20gand a first bonding pad23hof the top core20hmay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the fifth reconstructed wafer RW5and the fourth reconstructed wafer RW4are bonded to each other by wafer-to-wafer bonding, the fifth gap filling portion30-5of the fifth reconstructed wafer RW5and the fourth gap filling portion30-4of the fourth reconstructed wafer RW4may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the fourth gap filling portion30-4and the fifth gap filling portion30-5may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

Referring toFIG.28, conductive bumps40as conductive connection members may be formed on first bonding pads13of the first wafer W1.

For example, a seed layer may be formed on the first bonding pad13of the front insulating layer12of the first wafer W1, and a photoresist pattern having openings that expose portions of the seed layer may be formed on the seed layer on the front insulating layer12. Then, the openings of the photoresist pattern may be filled up with a conductive material, the photoresist pattern may be removed and a reflow process may be performed to form solder bumps. For example, the conductive material may be formed on the seed layer by a plating process. Alternatively, the conductive bump may include a pillar bump and a solder bump formed on the pillar bump.

Then, the first wafer W1and portions of the first to fifth gap filling portions30-1,30-2,30-3,30-4, and30-5may be cut along a scribe lane region SA to complete a semiconductor package100ofFIG.1.

FIG.29is a cross-sectional view illustrating a semiconductor package. The semiconductor package is substantially the same as or similar to the semiconductor package described with reference toFIG.1except for the number of stacked core dies and a configuration of a gap filling portion. Thus, same reference numerals will be used to refer to the same or like elements and any further repetitive explanation concerning the above elements will be omitted.

Referring toFIG.29, a semiconductor package101includes semiconductor chips (dies)20stacked therein. The semiconductor package101includes a buffer die10, and first to third core die stacks DS1, DS2, and DS3and a top core die stack DS4sequentially stacked on the buffer die10.

A plurality of semiconductor chips (dies)20a,20b,20c,20d,20e,20f,20g,20h,20i,20j,20k,and20lmay be stacked vertically. In this example, the semiconductor chips (dies)20a,20b,20c,20d,20e,20f,20g,20h,20i,20j,20k,and20lmay be substantially the same as or similar to each other. Accordingly, same or like reference numerals will be used to refer to the same or like elements and repeated descriptions of the same elements may be omitted.

In this example, the semiconductor package as a multi-chip package is illustrated as including twelve stacked semiconductor chips, e.g., cores20a,20b,20c,20d,20e,20f,20g,20h,20i,20j,20k,and20l, on the buffer die10, however, the number is not limited thereto. For example, the semiconductor package may include 4, 8, or 16 stacked semiconductor chips.

Each of the semiconductor chips, e.g., cores20a,20b,20c,20d,20e,20f,20g,20h,20i,20j,20k,and20l, may include an integrated circuit chip completed by performing semiconductor manufacturing processes. Each semiconductor chip may include, for example, a memory chip or a logic chip. The semiconductor package101may include a memory device. The memory device may include a high bandwidth memory (HBM) device.

In some implementations, the first core die stack DS1may be bonded onto the buffer die10. The first core die stack DS1may include first intermediate cores20a,20b,20c,and20dstacked in four stages and a first gap filling portion30-1covering outer surfaces of the first intermediate cores20a,20b,20c,and20d.

The second core die stack DS2may be bonded onto the first core die stack DS1. The second core die stack DS2may include second intermediate cores20e,20f,20g,and20hstacked in four stages and a second gap filling portion30-2covering outer surfaces of the second intermediate cores20e,20f,20g,and20h.

When the second core die stack DS2and the first core die stack DS1are bonded to each other, the second gap filling portion30-2of the second core die stack DS2and the first gap filling portion30-1of the first core die stack DS1may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the first gap filling portion30-1and the second gap filling portion30-2may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

The third core die stack DS3may be bonded onto the second core die stack DS2. The third core die stack DS3may include third intermediate cores20i,20j,and20kstacked in three stages and a third gap filling portion30-3covering outer surfaces of the third intermediate cores20i,20j,and20k.

When the third core die stack DS3and the second core die stack DS2are bonded to each other, the third gap filling portion30-3of the third core die stack DS3and the second gap filling portion30-2of the second core die stack DS2may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the second gap filling portion30-2and the third gap filling portion30-3may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

When the top core die stack DS4and the third core die stack DS3are bonded to each other, the fourth gap filling portion30-4of the top core die stack DS4and the third gap filling portion30-3of the third core die stack DS3may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the third gap filling portion30-3and the fourth gap filling portion30-4may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may include silicon oxide.

Hereinafter, a method of manufacturing the semiconductor package ofFIG.29will be described.

FIGS.30to35are views illustrating an example of a method of manufacturing a semiconductor package.

Referring toFIGS.30and31, a first reconstructed wafer RW1including at least one first intermediate core20a,20b,20c,and20dand a first gap filling portion30-1covering an outer surface of the at least one first intermediate core20a,20b,20c,and20dare formed on a first wafer1. In this example, the first reconstructed wafer RW1may include, but is not limited to, the first intermediate cores20a,20b,20c,and20dstacked in four stages.

As illustrated inFIG.30, processes the same as or similar to the processes described with reference toFIGS.13to16may be performed to attach a plurality of the first intermediate cores20a,20b,20c,and20din four stages on the first wafer W1(die-to-wafer hybrid bonding process).

In some implementations, the first intermediate cores20amay be disposed on the first wafer W1to correspond to die region DA. The first intermediate core20amay be stacked such that a first surface212aof a substrate21afaces the first wafer W1. By a thermal compression process, the first intermediate core20aand the first wafer W1may be bonded to each other through hybrid bonding.

Similarly, a plurality of the first intermediate cores20bmay be attached on the first-stage first intermediate cores20ain a second stage, a plurality of the first intermediate cores20cmay be attached on the second-stage first intermediate cores20bin a third stage, and a plurality of the first intermediate cores20dmay be attached on the third-stage first intermediate cores20cin a fourth stage.

As illustrated inFIG.31, processes the same as or similar to the processes described with reference toFIGS.17may be performed to form the first gap filling portion30-1that fills gaps between the first intermediate cores20a,20b,20c,and20dstacked in four stages on the first wafer W1.

A filling layer may be formed to cover the first intermediate cores20a,20b,20c,and20dstacked in four stages on the first wafer W1, and an upper portion of the filling layer may be removed to form the first gap filling portion30-1that exposes upper surfaces of the fourth-stage first intermediate cores20d.For example, the first gap filling portion30-1may be formed by a conformal deposition process such as an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The first gap filling portion may include an inorganic dielectric layer or an organic dielectric layer. The inorganic dielectric layer may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), and other suitable/desired materials. The organic dielectric layer may include a polymer or the like. The upper portion of the filling layer may be removed by a chemical mechanical polishing process or a mechanical grinding process.

Then, an upper surface of the first reconstructed wafer RW1, e.g., the upper surfaces of the fourth-stage first intermediate cores20c,may be planarized to initialize a topology due to the stacking of the first intermediate cores20a,20b,20c,and20d.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the fourth-stage first intermediate cores20d(topology reset process).

Accordingly, the first reconstructed wafer RW1including the first intermediate cores20a,20b,20c,and20dstacked in four stages and the first gap filling portion30-1covering the outer surfaces of the first intermediate cores20a,20b,20c,and20dmay be formed.

Referring toFIG.32, processes the same as or similar to the processes described with reference toFIGS.18to20may be performed to form a second reconstructed wafer RW2including at least one second intermediate core20e,20f,20g,and20hand a second gap filling portion30-2covering an outer surface of the at least one second intermediate core20e,20f,20g,and20hon a carrier substrate, and processes the same as or similar to the processes described with reference toFIGS.21and22may be performed to attach the second reconstruction wafer RW2on the first reconstruction wafer RW1(wafer-to-wafer hybrid bonding process).

In some implementations, the second intermediate cores20e,20f,20g,and20hmay be attached in four stages on the carrier substrate and a filling layer may be formed to cover the second intermediate cores20e,20f,20g,and20hand an upper portion of the filling layer may be removed to form the second gap filling portion30-2that exposes upper surfaces of the fourth-stage second intermediate cores20e.Then, upper surfaces of the fourth-stage second intermediate cores20emay be planarized to initialize a topology due to the stacking of the second intermediate cores20e,20f,20g,and20h.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the fourth-stage second intermediate cores20e(topology reset process).

Then, the second reconstructed wafer RW2may be stacked on the first reconstruction wafer RW1such that a front surface of the second intermediate core20eof the second reconstructed wafer RW2faces the backside surface of the first intermediate core20dof the first reconstructed wafer RW1.

When the second reconstructed wafer RW2and the first reconstructed wafer RW1are bonded to each other by wafer-to-wafer bonding, the second intermediate core20eof the second reconstructed wafer RW2and the first intermediate core20dof the first reconstructed wafer RW1may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22eon the front surface of the second intermediate core20emay be directly bonded to a backside insulating layer26don the backside surface of the first intermediate core20d,and a second bonding pad27dof the first intermediate core20dand a first bonding pad23eof the second intermediate core20emay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the second reconstructed wafer RW2and the first reconstructed wafer RW1are bonded to each other by wafer-to-wafer bonding, the second gap filling portion30-2of the second reconstructed wafer RW2and the first gap filling portion30-1of the first reconstructed wafer RW1may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the first gap filling portion30-1and the second gap filling portion30-2may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

Then, the carrier substrate may be removed to expose backside surfaces of the second intermediate cores20hof the second reconstructed wafer RW2. At this time, upper surfaces (backside surfaces) of the second intermediate cores20hmay be planarized to initialize a topology due to the stacking of the second intermediate cores20e,20f,20g,and20h.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the second intermediate cores20h(topology reset process).

Referring toFIG.33, processes the same as or similar to the processes described with reference toFIGS.18to20may be performed to form a third reconstructed wafer RW3including at least one third intermediate core20i,20j,and20kand a third gap filling portion30-3covering an outer surface of the at least one third intermediate core20i,20j,and20kon a carrier substrate, and processes the same as or similar to the processes described with reference toFIGS.21and22may be performed to attach the third reconstruction wafer RW3on the second reconstruction wafer RW2(wafer-to-wafer hybrid bonding process).

In some implementations, the third intermediate cores20i,20j,and20kmay be attached in three stages on the carrier substrate and a filling layer may be formed to cover the third intermediate cores20i,20j,and20kand an upper portion of the filling layer may be removed to form the third gap filling portion30-3that exposes upper surfaces of the fourth-stage third intermediate cores20i.Then, upper surfaces of the fourth-stage third intermediate cores20imay be planarized to initialize a topology due to the stacking of the third intermediate cores20i,20j, and20k.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the fourth-stage third intermediate cores20i(topology reset process).

Then, the third reconstructed wafer RW3may be stacked on the second reconstruction wafer RW2such that a front surface of the third intermediate core20iof the third reconstructed wafer RW3faces the backside surface of the second intermediate core20hof the second reconstructed wafer RW2.

When the third reconstructed wafer RW3and the second reconstructed wafer RW2are bonded to each other by wafer-to-wafer bonding, the third intermediate core20iof the third reconstructed wafer RW3and the second intermediate core20hof the second reconstructed wafer RW2may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22ion the front surface of the third intermediate core20imay be directly bonded to a backside insulating layer26hon the backside surface of the second intermediate core20h,and a second bonding pad27hof the second intermediate core20hand a first bonding pad23iof the third intermediate core20imay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the third reconstructed wafer RW3and the second reconstructed wafer RW2are bonded to each other by wafer-to-wafer bonding, the third gap filling portion30-3of the third reconstructed wafer RW3and the second gap filling portion30-2of the second reconstructed wafer RW2may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the second gap filling portion30-2and the third gap filling portion30-3may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

Then, the carrier substrate may be removed to expose backside surfaces of the third intermediate cores20kof the third reconstructed wafer RW3. At this time, upper surfaces (backside surfaces) of the third intermediate cores20kmay be planarized to initialize a topology due to the stacking of the third intermediate cores20i,20j,and20k.For example, a chemical mechanical polishing (CMP) process may be performed to remove topology accumulation in bonding interfaces of the third intermediate cores20k(topology reset process).

Referring toFIG.34, processes the same as or similar to the processes described with reference toFIG.26may be performed to form a fourth reconstructed wafer RW4including a top core20land a fourth gap filling portion30-4covering an outer surface of the fourth intermediate core20lon a carrier substrate, and processes the same as or similar to the processes described with reference toFIG.27may be performed to attach the fourth reconstruction wafer RW4on the third reconstruction wafer RW3(wafer-to-wafer hybrid bonding process).

In some implementations, a plurality of the top cores20lmay be attached in one stage on the carrier substrate and a filling layer may be formed to cover the top core20land an upper portion of the filling layer may be removed to form the fourth gap filling portion30-4that exposes upper surfaces of the top cores20l. A thickness of the top core20lmay be greater than thicknesses of the intermediate cores. The thickness of the top core20lmay be in a range of 100 μm to 300 μm.

Then, the fourth reconstructed wafer RW4may be stacked on the third reconstruction wafer RW3such that a front surface of the top core20lof the fourth reconstructed wafer RW4faces the backside surface of the third intermediate core20kof the third reconstructed wafer RW3.

When the fourth reconstructed wafer RW4and the third reconstructed wafer RW3are bonded to each other by wafer-to-wafer bonding, the top core20lof the fourth reconstructed wafer RW4and the third intermediate core20kof the third reconstructed wafer RW3may be hybrid-bonded to each other by a thermal compression process and an annealing process. That is, a first front insulating layer22lon the front surface of the top core20lmay be directly bonded to a backside insulating layer26kon the backside surface of the third intermediate core20k,and a second bonding pad27kof the third intermediate core20kand a first bonding pad23lof the top core20lmay be bonded to each other by copper-copper hybrid bonding (Cu—Cu Hybrid Bonding).

When the fourth reconstructed wafer RW4and the third reconstructed wafer RW3are bonded to each other by wafer-to-wafer bonding, the fourth gap filling portion30-4of the fourth reconstructed wafer RW4and the third gap filling portion30-3of the third reconstructed wafer RW3may be bonded to each other by a thermal compression process and an annealing process. By the annealing process, the third gap filling portion30-3and the fourth gap filling portion30-4may be directly bonded to each other to form a bonding interface layer. The bonding interface layer may have a thickness in a range of 2 Å to 500 Å. The bonding interface layer may include silicon oxide.

Referring toFIG.35, conductive bumps40as conductive connection members may be formed on first bonding pads13of the first wafer W1.

Then, the first wafer W1and portions of the first to fourth gap filling portions30-1,30-2,30-3, and30-4may be cut along a scribe lane region SA to complete a semiconductor package101ofFIG.29.

The semiconductor package may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (APs), or the like, and volatile memory devices such as DRAM devices, HBM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, or the like.