A light-emitting-element array has a semiconductor layer formed on a current-blocking layer. Light-emitting elements are formed in the semiconductor layer by diffusion of an impurity of a different conductive type. An isolation trench divides the semiconductor layer into a first region and a remaining region, and divides the array of light-emitting elements into segments disposed alternately in these two regions, each segment preferably including one or two light-emitting elements. A first shared interconnecting pad is electrically coupled to the light-emitting elements in the first region by electrical paths not crossing the isolation trench. A second shared interconnecting pad is electrically coupled to light-emitting elements in the remaining semiconductor region by electrical paths crossing the isolation trench. The array can then be driven by a number of separate interconnecting pads equal to half the number of the light-emitting elements.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a light-emitting-element array, more particularly to its wire-bonding interconnection pads and their interconnections to the light-emitting elements.

2. Description of the Related Art

The type of light-emitting-element array with which the present invention is concerned has a plurality of light-emitting elements spaced at equal intervals. A light-emitting-element array using light-emitting diodes (LEDs) as its light-emitting elements is referred to as an LED array. Conventional LED arrays have, for example, the structure shown inFIGS. 18 and 19, which are taken from page 60 of ‘LED Purinta no Sekkei’ (Design of LED Printers), published by Triceps.

FIG. 18is a sectional view of the relevant parts of an LED array100, andFIG. 19is a plan view. The LED array100comprises an n-type gallium arsenide phosphide (GaAsP) layer101formed on an n-type gallium arsenide (GaAs) substrate105. A p-type impurity such as zinc (Zn) is selectively diffused into the GaAsP layer101to form a row of p-type regions106that function as light-emitting elements. The GaAsP layer101is covered by a dielectric film102with openings through which the tips of aluminum electrodes103make individual contact with the p-type regions106.

In order to form an electrical connection with a driver circuit (not shown), each of the other ends of the aluminum electrodes103is electrically coupled to an electrode pad107formed to present a flat surface with an adequate area for wire bonding. A gold-germanium-nickel (AuGeNi) electrode104is formed under the n-type GaAs substrate105as a common electrode, electrically coupled to the p-type regions106through the n-type GaAs substrate105and GaAsP layer101.

In many conventional LED arrays, each light-emitting element has a separate electrode pad107, as shown. A dense array of light-emitting elements therefore has a correspondingly dense set of electrode pads, but the density of the electrode pads makes wire bonding difficult, leading to a rise in manufacturing cost.

The necessary number of electrode pads can be reduced by a matrix driving scheme, but known matrix driving schemes also lead to low manufacturing yields and correspondingly high manufacturing costs. The low yields are due to interconnection faults such as short circuits and open circuits that may occur where interconnecting lines cross one another, or cross isolation trenches.

SUMMARY OF THE INVENTION

An object of the present invention is to reduce the number of wire-bonding interconnections needed to drive a light-emitting-element array.

Another object of the invention is to improve manufacturing yields by reducing the occurrence of interconnection faults in a light-emitting-element array.

A further object is to enable a light-emitting-element array to be driven by an inexpensive driving circuit.

The present invention provides a light-emitting-element array having a semiconductor layer of a first conductive type formed on a current-blocking layer. The semiconductor layer is divided by an isolation trench into a first semiconductor region and a remaining semiconductor region, electrically isolated from the first semiconductor region.

A plurality of light-emitting elements are formed by diffusion of an impurity of a second conductive type into the surface of the semiconductor layer. The light-emitting elements are disposed in, for example, a linear array or a staggered array. The isolation trench divides the array into segments including at least one light-emitting element each, the segments being disposed alternately in the first semiconductor region and the remaining semiconductor region. The segments preferably include either just one light-emitting element each, or just two light-emitting elements each.

The light-emitting-element array also includes first and second shared interconnecting pads. The first shared interconnecting pad is electrically coupled to the light-emitting elements in the first semiconductor region by electrical paths not crossing the isolation trench. The second shared interconnecting pad is electrically coupled to the light-emitting elements in the remaining semiconductor region by electrical paths crossing the isolation trench.

The light-emitting-element array may also include a number of separate interconnecting pads equal to half the total number of light-emitting elements, each separate interconnecting pad being electrically coupled to a mutually adjacent pair of light-emitting elements belonging to different segments of the array. The separate interconnecting pads may be disposed in the remaining semiconductor region, in which case the first and second shared interconnecting pads are preferably disposed in the first semiconductor region.

In this light-emitting-element array, the necessary number of wire-bonding interconnections is reduced because each separate interconnecting pad drives two light-emitting elements.

The isolation trench may have a square-wave configuration weaving through the linear array of light-emitting elements. Alternatively, the isolation trench may surround each array segment disposed in the remaining semiconductor region, thereby dividing the remaining semiconductor region into mutually isolated subregions.

Compared with conventional matrix-driving schemes, the present invention reduces the number of points at which interconnecting leads and lines must cross one another. The square-wave trench configuration in particular also reduces the number of points at which interconnecting leads and lines cross the isolation trench. The probability of occurrence of interconnection faults is therefore reduced, and manufacturing yields are improved.

The semiconductor layer in the light-emitting array may include an n-type AlyGa1-yAs light-emitting layer, an underlying n-type AlxGa1-xAs layer, an overlying n-type AlzGa1-zAs layer, and an n-type GaAs contact cap layer. The bottom diffusion fronts of the light-emitting elements are disposed in the n-type AlyGa1-yAs layer. Parts of the n-type GaAs contact cap layer including the lateral diffusion fronts of the light-emitting elements are removed to eliminate pn junctions from regions having a lower aluminum content than the n-type AlyGa1-yAs light-emitting layer. This structure improves the light-emitting efficiency of the array, permitting it to be driven by an inexpensive driving circuit.

The present invention also provides an optical printing head including at least one light-emitting-element array of the invented type, and an electrophotographic printer including at least one such optical printing head.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.

First Embodiment

An LED array1according to a first embodiment of the invention is illustrated in plan view in FIG.1.FIGS. 2A,2B, and2C show sectional views through index lines201,202, and203, respectively, inFIG. 1, seen from the direction of arrows A and B.

As shown in the sectional views, the LED array1comprises a high-resistance substrate2such as a semi-insulating GaAs substrate, on which is formed an n-type semiconductor layer3(n-type corresponding to the first conductive type). A pair of dielectric films13and14are formed on the semiconductor layer3. As shown inFIG. 1, an isolation trench10is formed in a square-wave pattern running in the longitudinal direction of the array, dividing the array1(more specifically, the n-type semiconductor layer3) into two semiconductor blocks1a,1bwith interlocking comb-tooth-like projections1c,1d.

In this embodiment, semiconductor block1aconstitutes the first semiconductor region and semiconductor block1bconstitutes the remaining semiconductor region.

A row of p-type semiconductor diffusion regions4(p-type corresponding to the second conductive type) are formed in respective comb-tooth-like projections1cand1dby diffusion of a p-type impurity such as zinc. The p-type semiconductor diffusion regions4are formed at locations in or near semiconductor block1b, and are aligned in the longitudinal direction of the array. In addition, n-electrodes5are formed in respective comb-tooth-like projections1cand1dat locations in or near semiconductor block1a, also aligned in the longitudinal direction of the array. The n-electrodes5are disposed in openings in the dielectric films13,14. A row of anode interconnecting pads6(separate interconnecting pads) is disposed on the first dielectric film13, aligned in the longitudinal direction of the array in semiconductor block1b.

In the comb-tooth-like projections1cof semiconductor block1a, first leads6aof anode interconnecting pads6contact the p-type semiconductor diffusion regions4through openings in the first dielectric film13, as shown in the sectional view inFIG. 2A, and branch leads7aof an upper shared interconnecting line7contact the n-electrodes5through openings in the second dielectric film14.

In the comb-tooth-like projections1dof semiconductor block1binFIG. 1, second leads6bof the anode interconnecting pads6contact the p-type semiconductor diffusion regions4through openings in the first dielectric film13, as shown in the sectional view inFIG. 2B, and the ends8aof interconnecting leads8contact the n-electrodes5through openings in both dielectric films13,14.

The interconnecting leads8are formed on the second dielectric film14. The other ends8bof the interconnecting leads8contact a lower shared interconnecting line9, formed on the first dielectric film13, through further openings in the second dielectric film14. The upper shared interconnecting line7is electrically coupled to a first cathode interconnecting pad15, shown in FIG.1. The lower shared interconnecting line9is electrically coupled to a second cathode interconnecting pad16. The cathode interconnecting pads15,16are disposed on the first dielectric film13in semiconductor block1a.

The pn junction formed between each p-type semiconductor diffusion region4and the n-type semiconductor layer3functions as a light-emitting element11. The light-emitting elements11are disposed in a linear array. The first cathode interconnecting pad15functions as the first shared interconnecting pad; the second cathode interconnecting pad16functions as the second shared interconnecting pad. The interconnecting leads8and the lower shared interconnecting line9form electrical paths that cross the isolation trench10; the upper shared interconnecting line7and its branch leads7aform electrical paths that do not cross the isolation trench10.

The invention is not restricted to a linear array of light-emitting elements11. For example, the light-emitting elements11may be disposed in a staggered array, as will be illustrated in FIG.17.

Next, a method of fabricating the LED array1will be described with reference toFIGS. 3A and 3B,4A to4C,5A to5C,6, and7.

FIGS. 3A and 3Bshow the stage at which the row of p-type semiconductor diffusion regions4have been formed at predetermined locations in the longitudinal direction of the LED array1.FIG. 3Ais a plan view, andFIG. 3Bis a sectional view through index line104inFIG. 3A, as seen from the direction of the arrows marked C. First, the process steps preceding the formation of the p-type semiconductor diffusion regions4will be briefly described.

As shown inFIG. 3B, a high-resistance substrate2, such as a semi-insulating GaAs substrate, on which an n-type semiconductor layer3has been epitaxially grown is employed as the substrate of the LED array1. An n-type aluminum-gallium arsenide (AlGaAs) layer can be used as the n-type semiconductor layer. To obtain good electrode contact, an n-type GaAs contact cap layer17is formed at the top of the n-type semiconductor layer3.

Next, the first dielectric film13, which is five hundred to three thousand angstroms (500 Å to 3000 Å) thick and also serves as a diffusion mask, is formed on the LED array substrate by sputtering, and openings13aare formed at locations corresponding to the light-emitting elements by photolithography and etching. Then zinc, which is a p-type impurity, is diffused into the n-type semiconductor layer3through the openings13aby a solid-phase diffusion process, for example, thereby forming the p-type semiconductor diffusion regions4.

FIGS. 4Ato4C andFIGS. 5Ato5C show subsequent fabrication steps.FIGS. 4A and 5Aare plan views;FIGS. 4B and 5Bshow sectional views through index line105inFIGS. 4A and 5A, respectively, as seen from the direction of arrows A, whileFIGS. 4C and 5Cshow sectional views through index line106inFIGS. 4A and 5A, respectively, as seen from the direction of arrows A.

As shown inFIGS. 4A,4B, and4C, in order to form the isolation trench10, the diffusion mask13is first removed from a square-wave-shaped ribbon-like region extending generally in the longitudinal direction of the LED array1. This ribbon-like region is then etched at least as far down as the high-resistance substrate2, as shown inFIGS. 4B and 4C, to form the isolation trench10. The etching is carried out by a wet etching procedure using an etchant such as a solution of phosphoric acid and hydrogen peroxide. The LED array1is thereby divided into two electrically isolated semiconductor blocks1aand1bfacing each other with interlocked comb-tooth-like projections1cand1d. The isolation trench10divides the linear array of p-type semiconductor diffusion regions4into segments disposed alternately in semiconductor blocks1aand1b, each segment including just one p-type semiconductor diffusion region4.

Next, as shown inFIGS. 5Ato5C, an intermediate dielectric film20is formed on the entire major surface of the LED array1, except for areas20aabove the p-type semiconductor diffusion regions4and areas20bin which n-electrodes will be formed in the comb-tooth-like projections1cand1dof the semiconductor blocks1aand1b. In this step in this embodiment, first a silicon-nitride (SiN) dielectric film 500 Å to 3000 Å thick, for example, is formed; then, photolithography is carried out to define the above areas20aand20b, and the SiN dielectric film is removed from these areas by etching.FIGS. 2A,2B, and2C show the intermediate dielectric film as if it were part of the first dielectric film13.

Next, as shown inFIGS. 5Ato5C, the n-electrodes5are formed in areas20b. In this embodiment, the n-electrodes5are formed on the n-type semiconductor layer3by deposition of a gold alloy material followed by lift-off of unwanted portions. The n-electrodes5are then sintered to form ohmic contacts.

FIGS. 6 and 7are plan views of the LED array1showing the subsequent fabrication steps. As shown inFIG. 6, after the n-electrodes5have been formed, the anode interconnecting pads6, their first and second leads6a,6b, the first cathode interconnecting pad15, the second cathode interconnecting pad16, and its lower shared interconnecting line9are simultaneously formed on the intermediate dielectric film20by deposition and lift-off of a gold alloy or other suitable material. The first and second leads6a,6bof the anode interconnecting pads6make individual contact with the p-type semiconductor diffusion regions4through the openings in the areas20aof the intermediate dielectric film20shown inFIGS. 5B and 5C. Sintering is carried out to form ohmic contacts.

Next, as shown inFIG. 7, the second dielectric film14is formed on the entire major surface of the LED array1, except for pad areas14ain which the anode interconnecting pads6, first cathode interconnecting pad15, and second cathode interconnecting pad16are left exposed, n-electrode areas14bin which the n-electrodes5are left exposed, and connection areas14cin which the lower shared interconnecting line9is left exposed. The connection areas14cface the n-electrode areas14bin comb-tooth-like projections1d.

Then the upper shared interconnecting line7, its branch leads7a, and the interconnecting leads8are formed simultaneously on the second dielectric film14by deposition and lift-off of a material such as a gold alloy. As shown inFIG. 1, the interconnecting leads8electrically couple the lower shared interconnecting line9to the n-electrodes5in comb-tooth-like projections1dthrough the openings formed in the second dielectric film14in the connecting areas14cand in the n-electrode areas14bin comb-tooth-like projections1d. The upper shared interconnecting line7and its branch leads7aelectrically couple the n-electrodes5in comb-tooth-like projections1cto the first cathode interconnecting pad15through the openings in the second dielectric film14formed in the pad regions14aand the n-electrode areas14bin comb-tooth-like projections1c.

A method of driving the LED array1will now be described with reference to the plan view in FIG.1. To facilitate the description, the light-emitting elements11inFIG. 1are numbered D1, D2, D3, D4, . . . in sequence from the left in FIG.1. The n-electrodes5in the odd-numbered light-emitting elements11are all electrically coupled to the second cathode interconnecting pad16, the n-electrodes5in the even-numbered light-emitting elements11are all electrically coupled to the first cathode interconnecting pad15, and the first and second leads6aand6bof each anode interconnecting pad6are electrically coupled as p-electrodes to the p-type regions in a consecutive pair of light-emitting elements11.

Desired light-emitting elements are driven by electrically selecting the anode interconnecting pads6and the first or second cathode interconnecting pad15and supplying forward current from the p-side to the n-side. To drive an odd-numbered light-emitting element such as light-emitting element D5, for example, the anode interconnecting pad6connected to its anode electrode and the second cathode interconnecting pad16are selected, and forward current is supplied. Likewise, to drive an even-numbered light-emitting element such as light-emitting element D10, the anode interconnecting pad6connected to its anode electrode and the first cathode interconnecting pad15are selected, and forward current is supplied.

In this matrix driving scheme,2nlight-emitting elements can be driven by using two cathode interconnecting pads and n separate anode interconnecting pads, where n is a positive integer.

In the LED array1according to the first embodiment, the cathode electrodes are divided into two groups, and a shared cathode interconnecting pad is provided for each group, thereby enabling the number of anode interconnecting pads to be reduced by half. Since the isolation trench that separates the two groups is formed in a square-wave pattern, the number of interconnecting lines crossing the isolation trench is greatly reduced. More specifically, the branch leads7aof the upper shared interconnecting line7and the second leads6bof the anode interconnecting pads6do not cross the isolation trench10.

There is a general tendency for interconnecting lines formed on the sloping side walls of a trench to be thinner than interconnecting lines formed on a flat surface, and therefore more prone to failures such as open circuits. In the LED array1in this embodiment, the probability of such failures is reduced because the number of interconnecting lines crossing the trench is reduced.

In the above embodiment, the high-resistance substrate2functions as a current blocking layer, enabling the isolation trench10to divide the n-type semiconductor layer3into mutually isolated regions. In place of the high-resistance substrate2, however, a semiconductor substrate of the conductive type opposite to the n-type semiconductor layer3(that is, a p-type semiconductor substrate) may be employed as a current blocking layer. Alternatively, instead of having the substrate function as a current-blocking layer, a separate current-blocking layer (either a high-resistance layer or a layer of the opposite conductive type) may be formed between the semiconductor layer3and the substrate, in which case the conductive type and resistivity of the substrate are immaterial.

Second Embodiment

FIG. 8is a plan view of part of an LED array31illustrating a second embodiment of the present invention.FIGS. 9A,9B, and9C show sectional views through index lines201,202, and203, respectively, inFIG. 8, seen from the direction of arrows A and B.

The LED array31in the second embodiment differs from the LED array1shown inFIG. 1in the first embodiment in that the isolation trench32is formed so as to create island-like semiconductor blocks33. The following description will focus on the differences between the first embodiment and the second embodiment, omitting descriptions of component elements that are the same as in the first embodiment.

As shown inFIG. 8, the isolation trench32in the second embodiment divides the n-type semiconductor layer3into a first semiconductor block1aand a remaining semiconductor region, as in the first embodiment, but the isolation trench now includes a continuous straight lane32athat divides the remaining semiconductor region into a plurality of island-like blocks33and a single rectangular block34.

The island-like blocks33, which include the odd-numbered light-emitting elements11, are electrically independent of other regions. The comb-tooth-like projections1cof semiconductor block1a, which include the even-numbered light-emitting elements11, are electrically continuous with one another as in the first embodiment. As shown inFIG. 9A, the first leads6aof the anode interconnecting pads6cross the isolation trench32as they did in the first embodiment. As shown inFIG. 8, these crossings occur in the straight lane32a. As shown inFIG. 9B, the second leads6bof the anode interconnecting pads6in the LED array31also cross the straight lane32aof the isolation trench.

Aside from the different isolation trench configuration, the same fabrication process can be used for this LED array31as for the LED array1in the first embodiment, and the driving method is also the same. Descriptions of the fabrication process and driving method will therefore be omitted.

In the LED array31in the second embodiment, the n-type semiconductor layer3in the rectangular block34, which serves as a base for the anode interconnecting pads6, is electrically isolated from the array of light-emitting elements11. Accordingly, even if an anode interconnecting pad6and the underlying first dielectric film13are unintentionally pierced in the wire-bonding process, no short circuit is formed between the anode interconnecting pad6and the n-type semiconductor layer3in the light-emitting elements11. Manufacturing yields of the LED array are therefore improved.

Third Embodiment

FIGS. 10A and 10Bshow part of an LED array41illustrating a third embodiment of the present invention.FIG. 10Ais a plan view, whileFIG. 10Bis a sectional view through index line201inFIG. 10A, seen from the direction of the arrows marked A.

The LED array41in the third embodiment differs from the LED array31shown inFIG. 8in the second embodiment in that the isolation trench comprises a plurality of separate closed loops43surrounding the island-like blocks33. The following description will focus on the difference between the second and third embodiments, omitting descriptions of component elements that are the same as in the first and second embodiments.

As shown inFIG. 10A, the isolation trench loops43make the island-like blocks33, which include the odd-numbered light-emitting elements11, independent of other regions. The comb-tooth-like projections1cof semiconductor block1a, shown inFIG. 8, which include the even-numbered light-emitting elements11, are now continuous with the rectangular block34inFIG. 8, the parts of the straight lane32aof the isolation trench that separated them from the rectangular block34inFIG. 8having been removed. The comb-tooth-like projections1cthus become bridges42ain FIG.10A.

Accordingly, the semiconductor block1aand the separate rectangular block34in the LED array31in the second embodiment are connected in the LED array41in the third embodiment to form a continuous first semiconductor region42. As shown in the sectional view inFIG. 10B, the first leads6aof the anode interconnecting pads6in the LED array41are formed on a flat surface, without crossing the isolation trenches43.

Aside from the different isolation trench configuration, the same fabrication process can be used for this LED array41as for the LED array1in the first embodiment, and the driving method is also the same. Descriptions of the fabrication process and driving method will therefore be omitted.

As explained above, according to the LED array41in the third embodiment, the number of conductive lines that cross the isolation trenches is reduced, as in the LED array1in the first embodiment. The probability of failures such as open circuits or the like caused by the thinness of the interconnecting lines formed on the sloping side walls of the trenches is thereby reduced.

Fourth Embodiment

FIG. 11a plan view of part of an LED array51illustrating a fourth embodiment of the present invention.

The LED array51in the fourth embodiment differs from the LED array1in the first embodiment, shown inFIG. 1, in that the isolation trench52that weaves through the array of light-emitting elements11divides the array into segments of two light-emitting elements each, these segments being alternately disposed in semiconductor blocks51aand51b. Because of this arrangement, the locations at which the n-electrodes5are connected to the upper and lower shared interconnecting lines53and54are changed, which constitutes another difference. The following description will focus on the differences between the first and fourth embodiments, omitting descriptions of component elements that are the same as in the first embodiment.

The isolation trench52is etched through the n-type semiconductor layer3(shown inFIGS. 2A and 2B) in a square-wave pattern extending in the longitudinal direction of the LED array51in FIG.11. The LED array51is thereby divided into two electrically isolated semiconductor blocks51aand51bfacing each other with interlocking comb-tooth-like projections51cand51d.

Two adjacent light-emitting elements11are disposed in each of the comb-tooth-like projections51cand51d. The upper shared interconnecting line53electrically couples the pairs of n-electrodes5disposed in the comb-tooth-like projections51cof semiconductor block51ato the first cathode interconnecting pad15. The interconnecting leads8and the lower shared interconnecting line54electrically couple the pairs of n-electrodes5disposed in the comb-tooth-like projections51dof semiconductor block51bto the second cathode interconnecting pad16.

Each of the anode interconnecting pads6is formed so that its first and second leads6aand6bcontact the p-type semiconductor diffusion regions4in a pair of mutually adjacent light-emitting elements11disposed in different comb-tooth-like projections.

Aside from the different isolation trench configuration and different interconnections of the upper and lower shared interconnecting lines53and54, the same fabrication process can be used for this LED array51as for the LED array1in the first embodiment. Descriptions of the fabrication process will therefore be omitted.

A method of driving the LED array51formed as described above will be described with reference to the plan view in FIG.11. To facilitate the description, the light-emitting elements11inFIG. 11are numbered D1, D2, D3, D4, . . . in sequence from the left in FIG.11.

Desired light-emitting elements are driven by electrically selecting the anode interconnecting pads6and the first or second cathode interconnecting pad15or16and supplying forward current from the p-side to the n-side.

To drive a light-emitting element or element such as light-emitting element D5disposed in semiconductor block51b, for example, the anode interconnecting pad6connected to its anode electrode and the second cathode interconnecting pad16are selected, and forward current is supplied. Likewise, to drive a light-emitting element such as light-emitting element D10disposed in semiconductor block51a, the anode interconnecting pad6connected to its anode electrode and the first cathode interconnecting pad15are selected, and forward current is supplied.

As in the preceding embodiments,2nlight-emitting elements can be driven by using two cathode interconnecting pads and n separate anode interconnecting pads, where n is a positive integer.

The LED array51according to the fourth embodiment provides the effects noted in the first embodiment. In addition, the number of turns in the square-wave pattern of the isolation trench52is reduced, thereby shortening the overall length of the isolation trench. This reduces the probability that a conductive particle will lodge in the isolation trench during photolithography and etching steps in the semiconductor fabrication process, causing a failure by electrically interconnecting the upper and lower semiconductor blocks. Manufacturing yields of the LED array are therefore improved.

Fifth Embodiment

FIGS. 12A and 12Bshow part of an LED array61according to a fifth embodiment of the present invention.FIG. 12Ais a plan view, whileFIG. 12Bis a sectional view through index line201inFIG. 10A, seen from the direction of the arrows marked A.

The LED array61in the fifth embodiment differs from the LED array1shown inFIG. 1in the first embodiment in the manner in which the n-electrodes in comb-tooth-like projections in the first semiconductor region are electrically coupled to the first cathode interconnecting pad. The following description will focus on the differences between the first embodiment and the fifth embodiment, omitting descriptions of component elements that are the same as in the first embodiment.

LED array61has a shared electrode63, made of a gold alloy, that may be formed simultaneously with the n-electrodes5in the step described in the first embodiment. The n-electrodes5disposed in comb-tooth-like projections61cof semiconductor block61aare made large enough to closely approach the lower shared interconnecting line9that will be formed later, and the shared electrode63is formed closely parallel to the lower shared interconnecting line9on the opposite side thereof from the n-electrodes5.

Accordingly, the intermediate dielectric film20is removed from an area in which the shared electrode63will be formed as well as from the light-emitting areas20aand the n-electrode formation areas20binFIGS. 5A and 5B.FIG. 12Bshows the diffusion mask and the intermediate dielectric film (20) as a single first dielectric film13. There is no second dielectric film.

When the first cathode interconnecting pad62is formed, a shared cathode interconnecting line64extending from the first cathode interconnecting pad62onto the shared electrode63is formed simultaneously, and interconnecting sheets65are also formed on the n-electrodes5in the comb-tooth-like projections61c. The anode interconnecting pads6, the second cathode interconnecting pad16, and the lower shared interconnecting line9may also be formed in this step, as described in the first embodiment.

In the first embodiment, the interconnecting leads8shown inFIG. 1were formed in a subsequent step. In the fifth embodiment, however, the interconnecting leads9aare integral with the lower shared interconnecting line9, and are formed at the same time as the lower shared interconnecting line9.

With this arrangement, the n-electrodes5in the comb-tooth-like projections61care electrically coupled to the first cathode interconnecting pad62through the GaAs contact cap layer17, n-type semiconductor layer3, GaAs contact cap layer17, shared electrode63, and shared cathode interconnecting line64, in this order. Together with the interconnecting sheets65, these elements form an electrical path that does not cross the isolation trench.

The GaAs contact cap layer17has a high impurity concentration and is formed to create an ohmic contact between the n-type semiconductor layer3on the one hand and the shared electrode63and n-electrodes5on the other hand. Although the LED array can operate without the n-electrodes5and interconnecting sheets65, operating efficiency would be reduced, because current would have to flow for a longer distance through the n-type semiconductor layer3, which has a higher resistance than the n-electrodes5and interconnecting sheets65. The n-electrodes5and interconnecting sheets65are desirable because they allow current to bypass part of the n-type semiconductor layer3.

The other fabrication steps and the driving method are the same as in the LED array1in the first embodiment. Descriptions of these steps and method will therefore be omitted.

By connecting the first cathode interconnecting pad62to the shared electrode63for substantially the entire length of the shared electrode63, the shared cathode interconnecting line64reduces the resistance of the electrical path extending from the first cathode interconnecting pad62. If the resistivity of the shared electrode63is already satisfactorily low, however, the shared cathode interconnecting line64can be shortened to connect the first cathode interconnecting pad62to the shared electrode63for only part of the length of the shared electrode63.

As described above, the LED array61in the fifth embodiment has an interconnection configuration that completely avoids overlapping metal wiring. Thus, all necessary metalization can be performed in one step and the number of dielectric films can be reduced by one. As compared with the first embodiment, the wiring configuration is simplified and the number of fabrication steps can be reduced, contributing to an improvement in manufacturing yields and a reduction in cost.

Sixth Embodiment

FIG. 13shows a light-emitting element11in an LED array1according to a sixth embodiment of the present invention. It will be assumed that the LED array1has the same overall structure as in the first embodiment.

A semi-insulating GaAs substrate2or other high-resistance substrate, on which an n-type semiconductor layer3has been epitaxially grown, is employed as the substrate of the LED array1. The n-type semiconductor layer3comprises at least three AlGaAs semiconductor layers: an n-type AlyGa1-yAs light-emitting layer3a, the parameter y of which determines the emission wavelength (1>y>0); an overlying n-type AlzGa1-zAs layer3b(1>z>y>0); and an underlying n-type AlxGa1-xAs layer3c(1>x>y>0). In order to obtain a light emission wavelength close to, for example, seven hundred sixty nanometers (760 nm), y may be set equal to 0.15, while x and z are set equal to 0.6.

The p-type semiconductor diffusion region4comprises a p-type AlyGa1-yAs light-emitting layer4adisposed within the n-type AlyGa1-yAs light-emitting layer3a, a p-type AlzGa1-zAs layer4bdisposed within the n-type AlzGa1-zAs layer3b, and a p-type GaAs contact region74. The p-type GaAs contact region74is part of a GaAs contact cap layer17formed on the n-type semiconductor layer3as a top layer for making ohmic electrical contact with, for example, the n-electrodes5(shown inFIG. 1) and the leads6a,6bof the anode interconnecting pads6.

To obtain the desired light-emission wavelength, the zinc diffusion process is controlled so that the bottom diffusion front of each p-type semiconductor diffusion region4is located within the n-type AlyGa1-yAs layer3a, and the pn junction at the lateral diffusion front is removed from at least regions71in the GaAs contact cap layer17and its interface with the underlying AlzGa1-zAs layer3b. Thus no pn junctions are formed in an n-type semiconductor layer with a lower aluminum content than the aluminum content (y) of the light-emitting n-type AlyGa1-yAs layer3a.

Next, a method of fabricating the light-emitting element in the sixth embodiment will be described with reference toFIGS. 14Ato14D.

Referring toFIGS. 14A and 14B, the first dielectric film13, which serves as the diffusion mask, is formed on the GaAs contact cap layer17, which is the top layer of the substrate. Then openings13aare formed at locations corresponding to the light-emitting elements by photolithography and etching, and zinc is selectively diffused into the substrate through the openings13ato form p-type semiconductor diffusion regions4. As shown inFIG. 14B, the diffusion depth is controlled so that the bottom diffusion front of each p-type semiconductor diffusion region4is located within the n-type AlyGa1-yAs light-emitting layer3a.

Next, as shown inFIG. 14C, material including the lateral diffusion front in the GaAs contact cap layer17and its interface with the underlying n-type AlzGa1-zAs layer3bis removed by etching so that no pn junctions are left within regions71having a lower aluminum content than that of the light-emitting n-type AlyGa1-yAs layer3a.

In this embodiment, the first dielectric film13is removed by etching from the peripheries of the openings13a. Then the n-type GaAs contact cap layer17is removed by etching from annular regions73surrounding the contact regions74where the electrodes will be formed, as shown in FIG.14D. The removed regions73include the boundaries between the p-type semiconductor diffusion regions4and the surrounding n-type GaAs contact cap layer17. The etched regions73extend through the interface between the n-type GaAs contact cap layer17and the underlying n-type AlzGa1-zAs layer3b.

Next, the isolation trench10shown inFIG. 1is formed as described in the first embodiment. Subsequent steps are also performed as in the first embodiment, so descriptions will be omitted.

The light-emitting elements in the sixth embodiment have an enhanced light-emitting efficiency that enables sufficient light emission to be obtained with a relatively low driving current. Accordingly, inexpensive driver ICs can be employed, and the overall cost of, for example, an electrophotographic printing head including the LED array can be reduced accordingly.

Seventh Embodiment

FIG. 15shows an example of an LED printing head700embodying the present invention. The LED printing head700includes a base701on which an LED unit702is mounted. The LED unit702includes a plurality of LED arrays of the type described in any of the preceding embodiments, aligned end to end to form a single linear array of light-emitting elements. The LED unit702also includes driver ICs to which the LED arrays are electrically coupled by wire-bonding. The LED arrays and driver ICs are mounted in area702a, the light-emitting elements being positioned beneath a rod lens array703. The linear array is seen here in cross-section.

The rod lens array703is supported by a holder704. The base701, LED unit702, and holder704are held together by clamps705. Light emitted by the light-emitting elements in the LED unit702is focused by rod lenses in the rod lens array703onto, for example, a photosensitive drum (not shown) in an electrophotographic printer or copier.

Eighth Embodiment

FIG. 16shows an example of an LED color printer800embodying the present invention. The printer800sends printing media such as paper810through a yellow process unit811a, a magenta process unit811b, a cyan process unit811c, and a black process unit811d, which are mounted following one another in tandem fashion. Each process unit811a,811b,811c,811dincludes a photosensitive drum812, a charging unit813that supplies current to the photosensitive drum812to charge the surface thereof, an LED printing head814that selectively illuminates the charged surface of the photosensitive drum812to form an electrostatic latent image, a developing unit815that supplies toner particles to the surface of the photosensitive drum812to develop the electrostatic latent image, and a cleaning unit816that removes remaining toner from the photosensitive drum812after the developed image has been transferred to the paper810. The LED printing head814has, for example, the structure described in the seventh embodiment, and includes LED arrays of the type described in any of the first six embodiments.

The paper810(or other media) is held as a stack of sheets in a cassette817. A hopping roller818feeds the paper810one sheet at a time toward a paired registration roller819aand pinch roller820a. After passing between these rollers, the paper810travels to another registration roller819band pinch roller820b, which feed the paper toward the yellow process unit811a.

Guided by a paper guide821, the paper810passes through the process units811a,811b,811c,811din turn, traveling in each process unit between the photosensitive drum812and a transfer roller822made of, for example, semi-conductive rubber. The transfer roller822is charged so as to create a potential difference between the photosensitive drum812and the transfer roller822. The potential difference attracts the toner image from the photosensitive drum812onto the paper810. A full-color image is built up on the paper810in four stages, the yellow process unit811ausing yellow toner to print a yellow image, the magenta process unit811busing magenta toner to print a magenta image, the cyan process unit811cusing cyan toner to print a cyan image, the black process unit811dusing black toner to print a black image.

From the black process unit811d, the paper810travels through a fuser823, in which a heat roller and back-up roller apply heat and pressure to fuse the transferred toner image onto the paper. A first delivery roller824aand pinch roller825athen feed the paper810upward to a second delivery roller824band pinch roller825b, which deliver the printed paper onto a stacker826at the top of the printer.

The photosensitive drum812and various of the rollers are driven by motors and gears not shown in the drawing. The motors are controlled by a control unit (not shown) that, for example, drives registration roller819aand halts registration roller819buntil the front edge of a sheet of paper810rests flush against registration roller819b, then drives registration roller819b, thereby assuring that the paper810is correctly aligned during its travel through the process units811a,811b,811c,811d. The registration rollers819a,819b, delivery rollers824a,824b, and pinch rollers820a,820b,825a,825balso have the function of changing the direction of travel of the paper810.

The LED heads814account for a significant part of the manufacturing cost of this type of LED printer800, and the density of the light-emitting elements in their LED arrays is a significant factor in the quality of the printed image. By enabling high-density LED arrays to be manufactured without the need for expensive, high-density wire bonding, the present invention enables high-quality printing to be obtained at a reasonable cost.

Next, a few variations of the preceding embodiments will be noted.

In the first embodiment, instead of a linear array of light-emitting elements being divided into segments by an isolation trench with a square-wave configuration, the isolation trench10may be linear and the light-emitting elements11may be disposed in a staggered array alternately above and below the isolation trench10, as illustrated in FIG.17. In this variation, since the two semiconductor blocks1a,1bdo not have comb-tooth-like projections, the isolation trench10is shortened, with the advantage of improved manufacturing yields, as noted in the fourth embodiment. The time interval between the driving of the light-emitting elements disposed in semiconductor block1aand the driving of the light-emitting elements disposed in semiconductor block1bcan be adjusted according to the rotational speed of a photosensitive drum in an electrophotographic printer, so that both groups of light-emitting elements illuminate a single line of dots on the surface of the photosensitive drum as the photosensitive drum turns at a constant speed.

The arrays of light-emitting elements in the other embodiments may also be staggered instead of linear.

In the fourth embodiment, instead of having a square-wave configuration as in the first embodiment, the isolation trench may form closed loops as in the second or third embodiment, each closed loop surrounding a pair of light-emitting elements.

In the fifth embodiment, instead of having the configuration shown in the first embodiment, the isolation trench may have the configuration shown in the second, third, or fourth embodiment, or the configuration in the above variation of the first or fourth embodiment.

The light-emitting elements shown in the sixth embodiment were described as being used in an LED array configured as in the first embodiment, but these light-emitting elements may also be used in an LED array configured as in any of the second to fifth embodiments.

In the embodiments described above, the first conductive type was n-type and the second semiconductor conductive type was p-type, but these conductive types may be interchanged.

Terms such as “left”, “above”, “underlying” and “overlying” in the descriptions of the embodiments and the appended claims are used for convenience and do not limit the absolute positional relationships of the various parts of the LED arrays.

Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined by the appended claims.