Semiconductor device and manufacturing method thereof

A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

BACKGROUND

DETAILED DESCRIPTION

FIG.1is a schematic perspective view of a semiconductor device SD10according to some embodiments of the disclosure.FIG.2is a schematic cross-sectional view of the semiconductor device SD10according to some embodiments of the disclosure. The view ofFIG.2may be taken in an XZ plane, where the X, Y, and Z directions form a set of orthogonal Cartesian coordinates. In some embodiments, the semiconductor device SD10includes a semiconductor substrate100and an interconnection structure105formed on the semiconductor substrate100. In some embodiments, the semiconductor substrate100includes one or more semiconductor materials, which may be elemental semiconductor materials, compound semiconductor materials, or semiconductor alloys. For instance, the elemental semiconductor material may include Si or Ge. The compound semiconductor materials and the semiconductor alloys may respectively include SiGe, SiC, SiGeC, a III-V semiconductor, a II-VI semiconductor, or semiconductor oxide materials. For example, the semiconductor oxide materials may be one or more of ternary or higher (e.g., quaternary and so on) semiconductor oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin oxide (ITO). In some embodiments, the semiconductor substrate100may be a semiconductor-on-insulator, including at least one layer of dielectric material (e.g., a buried oxide layer) disposed between a pair of semiconductor layers.

FIG.1andFIG.2further illustrate functional circuits that may be formed over the semiconductor substrate100. For example, a transistor110and a transistor120are illustrated on the semiconductor substrate100. The transistor110may include a pair of source and drain regions112,114embedded in the semiconductor substrate100, separated from each other by a portion of semiconductor substrate100which functions as a channel region of the transistor110. A gate structure116is disposed on the channel region in between the source and drain regions112,114. In some embodiments, the source and drain regions112,114may be doped, for example with n-type materials or p-type materials. In some embodiments, the transistor120may also include a pair of source and drain regions122,124, which may be optionally doped with n-type materials or p-type materials. In some embodiments, the source and drain regions122,124are doped with materials of opposite conductivity type with respect to the source and drain regions112,114. In some embodiments, the source and drain regions122,124may be embedded in a region126of different composition. For example, the region126may be doped with a material of opposite conductivity type with respect to the source and drain regions122,124, or the region126may include a same dopant as the source and drain regions122,124, but in different concentration. For example, the source and drain regions122,124may be doped with a p-type material, and the region126may be doped with an n-type material. In some embodiments, a gate structure128is disposed on the region126in between the source and drain regions122,124.

It should be noted that the disclosure does not limit the architecture of the transistors110,120. For example, the transistors110,120may be planar field effect transistors, fin field effect transistors, gate all around transistors, or any other transistor architecture. Furthermore, different gate contact schemes, such as front-gate, back-gate, double-gate, staggered, etc., are contemplated within the scope of the disclosure. Although inFIGS.1and2are illustrated transistors110,120formed over the semiconductor substrate100, other active devices (e.g., diodes or the like) and/or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuit.

The interconnection structure105may be formed over the semiconductor substrate100to integrate the circuit devices formed on the semiconductor substrate100in one or more functional circuits. For example, the interconnection structure105may include an interlayer dielectric130in which are embedded metallization layers that interconnect the circuit devices with each other. It should be noted that the interlayer dielectric130may be shown as a single layer for simplicity, but, in practice, it may be constituted by multiple interlayer dielectric layers (e.g.,132,134,135,136,138,139) stacked on each other and possibly containing different materials. The disclosure does not limit the number of interlayer dielectric layers included in the interlayer dielectric130, and the number illustrated in the drawings is but one example. Additional layers such as barrier layers, etch stop layers140,150, etc., may also be formed in between the interlayer dielectric layers132,134,135,136138,139. The interlayer dielectric130may be formed on the semiconductor substrate100, extending on the transistors110,120and on other circuit devices which may be formed on the semiconductor substrate100. Each metallization layer (e.g., the bottommost metallization layer162) may include conductive patterns and interconnect vias extending through the interlayer dielectric130to electrically couple to the circuit devices formed on the semiconductor substrate100, for example to couple to the source/drain regions112,114,122,124and to the gate structures116,128of the transistors110,120. In some embodiments, one or more additional metallization layers164(schematically represented as dots inFIG.1andFIG.2) are formed over the semiconductor substrate100. In some embodiments, the functional circuits formed by the interconnection structure105may comprise logic circuits, memory circuits, sense amplifiers, controllers, input/output circuits, image sensor circuits, the like, or combinations thereof. The disclosure does not limit the number of additional metallization layers164formed in an interconnection structure105, which may be adapted according to routing and design requirements.

In some embodiments, the interlayer dielectric130of the interconnection structure105may include low-k dielectric materials. Examples of low-k dielectric materials include Xerogel, Aerogel, amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutenes), flare, hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), or a combination thereof. In some embodiments, the individual interlayer dielectric layers132,134,135,136,138,139of the interlayer dielectric130may be fabricated to a suitable thickness by flowable CVD (FCVD), CVD, HDPCVD, SACVD, spin-on, sputtering, or other suitable methods. In some embodiments, the metallization layers (e.g.,140,150) may include cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metallic materials, and may be fabricated through a sequence of deposition (e.g., CVD, PVD, ALD), plating, or other suitable material-forming processes, and planarization steps (e.g., chemical mechanical polishing). In some embodiments, the interconnection structure105may be formed via damascene, dual damascene, or other suitable processes.

In some embodiments, in correspondence of one or more of the metallization layers of the interconnection structure105, is formed a transistor array170. The transistor array170may be over the semiconductor substrate100embedded in the interconnection structure105, for example formed on one of the lower metallization layers164. Additional metallization layers182and conductive patterns184may be formed over the transistor array170, to further integrate the transistor array170with the remaining circuitry of the semiconductor device SD10, and to bring signals generated or processed by the semiconductor device SD10towards an I/O interface. For example, the conductive patterns184may be formed as the topmost metallization level, at the top of the interlayer dielectric130(e.g., in the uppermost interlayer dielectric layer139, at the side of the interlayer dielectric130further away from the semiconductor substrate100). Contact pads186may be formed to land on the conductive patterns184, and to act as I/O interfaces to integrate the semiconductor device SD10into larger devices. A passivation layer190may be disposed on the interconnection structure105. The passivation layer190may include a dielectric material, and may protect the underlying components of the semiconductor device SD10.

As illustrated by the above examples, in some embodiments, the semiconductor device SD10may be a semiconductor die. In some embodiments, the semiconductor device SD10may be integrated in larger semiconductor devices, for example by connecting the contact pads186to interposers, circuit substrates, or the like.

FIG.3is a schematic cross-sectional view of the transistor array170according to some embodiments of the disclosure.FIG.4Ais a schematic cross-sectional view of a region of the transistor array170according to some embodiments of the disclosure. The view ofFIG.4Amay be taken at the level height of the line I-I′ illustrated inFIG.3.FIG.4Bis a schematic bottom view of the same region illustrated inFIG.4Aaccording to some embodiments of the disclosure. The view ofFIG.4Bcorresponds to the view ofFIG.4A, with added the footprints of some elements disposed along the negative Z direction with respect to the plane of view ofFIG.4A(e.g., moving towards the semiconductor substrate100illustrated inFIG.1).FIG.4Cis a schematic top view of the same region illustrated inFIG.4Aaccording to some embodiments of the disclosure. The view ofFIG.4Ccorresponds to the view ofFIG.4A, with added the footprints of some elements disposed along the positive Z direction with respect to the plane of view ofFIG.4A(e.g., moving away from the semiconductor substrate100illustrated inFIG.1). Referring toFIG.1toFIG.4C, in some embodiments, the transistor array170includes a plurality of unit cells202,204disposed in an array manner, in rows and columns extending along orthogonal directions (e.g., the X and Y directions inFIG.4). Each unit cell202,204may include at least one transistor. The transistor array170may include conductive lines210which extend parallel to each other along one of the two directions of the array of unit cells202,204(e.g., the Y direction) and are distributed along the other direction of the array of unit cells202,204(e.g., X direction). The conductive lines210may be embedded in an interlayer dielectric layer134of the interlayer dielectric130. In some embodiments, the conductive lines210and the interlayer dielectric layer134are formed on an etch stop layer140. The etch stop layer140may include one or more layers of materials having adequate etching selectivity with respect to the material of the interlayer dielectric layer134. For example, the etch stop layer140may include a layer comprising a nitride (e.g., silicon nitride), a layer comprising an oxide (e.g., aluminum oxide), at least one each of said layers or layers including other suitable materials, or the like.

In some embodiments, each conductive line210extends below a line (e.g., a column) of unit cells202,204of the array, and is connected to the unit cells202,204of such line. That is, unit cells202formed at a same level height along the X direction may be connected to a same conductive line210, while unit cells202,204formed at different level heights along the X direction may be connected to different conductive lines210. More specifically, each unit cell202,204may include a gate pattern220which is connected by a contact via230to one of the conductive lines210. Individual gate patterns220may be dedicated to individual cells202,204. The gate patterns220may be formed in an interlayer dielectric layer135of the interlayer dielectric130stacked on the interlayer dielectric layer134in which the conductive lines210are formed. An etch stop layer150may be disposed between the interlayer dielectric layer134and the interlayer dielectric layer135. The etch stop layer150may have a similar structure and include similar materials as previously described for the etch stop layer140. The contact vias230may extend from the gate patterns220through the interlayer dielectric layer135and the etch stop layer150to contact the conductive lines210. In some embodiments, the gate patterns220may include any suitable metallic material, such as cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), zirconium (Zr), hafnium (Hf), titanium aluminum (TiAl), tantalum aluminum (TaAl), tungsten aluminum (WAl), zirconium aluminum (ZrAl), hafnium aluminum (HfAl), titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), a combination thereof, or the like.

A gate dielectric layer240may be disposed on the array of gate patterns220, blanketly covering the gate patterns220and the interlayer dielectric layer135. In some embodiments, the gate dielectric layer240includes a material with a dielectric constant greater than about 4, greater than about 12, greater than about 16, or even greater than about 20. For example, a material of the gate dielectric layer240may include a metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HMO, a silicate such as HfSiO, HfSiON, LaSiO, AlSiO, a combination thereof, or other suitable materials. The gate dielectric layer240may have a substantially uniform thickness along the Z direction, for example in the range up to about 200 angstroms.

On the gate dielectric layer240may be sequentially stacked a semiconductor channel layer250, a cap layer260, and a hard mask layer270. The semiconductor channel layer250may include an oxide material having semiconducting character, and suitable to function as channel for the transistors of the transistor array170. For example, the semiconductor oxide materials may be metal oxide materials including one or more of In, Zn, G, Sn, Pb, Zr, Sr, Ru, Mn, Mg, Nb, Ta, Hf, Al, La, Sc, Ti, V, Cr, Mo, W, Fe, Co, Ni, Pd, Ir, Ag, or combination thereof. Some elements may be present as dopant of other metal oxides. In some embodiments, the semiconductor oxide material may be ternary or higher (e.g., quaternary and so on) semiconductor oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin oxide (ITO). In some embodiments, a thickness of the semiconductor channel layer250along the Z direction may be in the range up to about 300 angstroms.

In some embodiments, the cap layer260is disposed on the semiconductor channel layer250. In some embodiments, the cap layer260includes a material having etching selectivity with respect to the semiconductor channel layer250. For example, the cap layer260may include an oxide such as silicon oxide, and may be formed with a thickness along the Z direction in the range up to about 500 angstroms. The hard mask layer270is disposed on the cap layer260, and may include a material having etching selectivity with respect to the cap layer260. In some embodiments, the hard mask layer270may include a nitride, such as silicon nitride, an oxide, such as aluminum oxide, a combination thereof, or the like. In some embodiments, a thickness along the Z direction of the hard mask layer270may be in the range up to about 500 angstroms.

In some embodiments, the unit cells202,204include source contacts280and drain contacts290. The source contacts280and the drain contacts290may be at least partially embedded in an interlayer dielectric layer136, which interlayer dielectric layer136extends on the hard mask layer270. Furthermore, in some embodiments, the source contacts280and the drain contacts290extend through the hard mask layer270and the cap layer260to land on the semiconductor channel layer250. That is, the source contact280and the drain contact290may directly contact the semiconductor channel layer250. In some embodiments, each unit cell202,204may include a dedicated source contact280, while the drain contacts290may be shared between adjacent unit cells202,204. For example, two source contacts280of adjacent unit cells202,204may be disposed at opposite sides (e.g., along the X direction) of a same drain contact290, separated from the shared drain contact290by portions1361of the interlayer dielectric layer136. The two unit cells202,204sharing the same drain contact290may belong to a same row of the transistor array170(e.g., may be located at the same level height along the Y direction), so as to be connected to different conductive lines210. Gate patterns220of each unit cell202,204may extend at the opposite side of the semiconductor channel layer250with respect to the portions1361of interlayer dielectric layer136separating the source contacts280from the drain contacts290. Upon application of an adequate voltage to the gate pattern220by the corresponding conductive line210, current would flow through the semiconductor channel layer250from the source contact280to the drain contact290of the unit cell202,204to which the gate pattern220belongs. Therefore, unit cells202,204sharing the same drain contact290may be selectively addressed by applying voltage to the associated conductive lines210. In some embodiments, the conductive material of the source contacts280and drain contacts290includes cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metallic materials. In some embodiments, the conductive material may be provided on one or more seed layers, barrier layers, etc. (not shown). That is, the source contacts280and the drain contacts290may include one or more seed layers, barrier layers, etc.

In some embodiments, pairs of unit cells202,204sharing the same drain contact290are encircled by spacers300. The spacers300may form a meshed structure, with meshes laterally surrounding the pairs of unit cells202,204. In particular, parts of the spacers300may extend along a first direction (e.g., the Y direction) covering outer side surfaces of the source contacts280opposite to the portions1361of interlayer dielectric layer136separating the source contacts280from the common drain contact280. Such parts may then be joined together by additional parts of the spacers300extending along a perpendicular direction (e.g., the X direction) to cover other outer side surfaces of the source contacts280, the drain contacts290and the intervening portions1361of interlayer dielectric layer136. The spacers300may be also partially embedded in the interlayer dielectric layer136, and may further extend through the hard mask layer270, the cap layer260, and the semiconductor channel layer250. In some embodiments, the spacers300land on the gate dielectric layer240, so that each pair of unit cells202,204includes a separate portion of the semiconductor channel layer250. In some embodiments, the spacers300may include any suitable dielectric material, such as oxides, nitrides, carbides, oxynitrides, or the like. In some embodiments, the material of the spacers300may be selected so as to further perform a barrier function. For example, when the spacers300include diffusion barrier materials such as aluminum oxide, the spacers300may protect the material of the semiconductor channel layer250from diffused H or O atoms, thus reducing instability and enhancing the reliability of the semiconductor device SD10.

In some embodiments, another interlayer dielectric layer138is formed on the interlayer dielectric layer136, extending over the spacers300and over at least portions of the source contacts280and the drain contacts290. Conductive lines310may be embedded in the interlayer dielectric layer138. The conductive lines310may extend parallel to each other along the other direction of the array with respect to the extending direction of the conductive lines210. That is, the conductive lines310may extend perpendicularly with respect to the conductive lines210. So, for example, if the conductive lines210extend along the column direction (e.g., the Y direction) of the transistor array170, the conductive lines310may extend along the row direction (e.g., the X direction) of the transistor array170. Furthermore, the conductive lines310are spaced from each other within the interlayer dielectric layer138along the extending direction of the conductive lines210(e.g., along the Y direction). The conductive lines310are connected to the drain contacts290by contact vias320extending through the interlayer dielectric layer138. In particular, the conductive lines310may extend over lines (e.g., rows) of unit cells202,204of the transistor array170, so that unit cells202,204formed at a same level height along the Y direction are connected to the same conductive line310, and unit cells202,204formed at different level heights along the Y direction are connected to different conductive lines310. In other words, the conductive lines210and310extend perpendicular with respect to each other, and the unit cells202,204are located in correspondence of the intersection points of the extending directions of the conductive lines210and310, so that any individual unit cell202,204may be selected by the combination of associated conductive lines210and310. In some embodiments, the conductive lines310and the contact vias320include cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), a combination thereof, or other suitable metallic materials.

Referring toFIG.3andFIG.4AtoFIG.4C, in some embodiments, the portions1361of interlayer dielectric layer136separating the source contacts280and the drain contacts290may have a substantially square or rectangular footprint when viewed in cross-sections transversal with respect to the Z direction, such as in XY planes. For example, such portions1361of interlayer dielectric layer136may have a pair of side surfaces136s1extending along one of the two directions of the transistor array170(e.g., the Y direction) which contact the source contacts280and the drain contacts290. The side surfaces136s1are joined together by another pair of side surfaces136s2extending along the other one of the two directions of the transistor array170(e.g., the X direction) and contacting the spacers300. The portion of interlayer dielectric layer136may have an overall rectangular footprint, for example with an aspect ratio of the size136L along the Y direction to the size136W along the X direction in the range between 0.1 to 20. For example, the size136L along the Y direction may be about in the range from 10 angstroms to 200 angstroms, and the size136W along the X direction may be about in the range from 10 angstroms to 100 angstroms, however the disclosure is not limited thereto.

The gate patterns220may overlap with the portions1361of interlayer dielectric layer136of the corresponding unit cells202,204, and the conductive lines210may overlap with multiple gate patterns220aligned along the X direction. InFIG.4Bare also shown the footprints of the contact vias230joining the gate patterns220to the conductive lines210. In some embodiments, the contact vias230of adjacent (along the X direction) unit cells202,204sharing a same drain contact290may be formed at different level heights along the Y direction, but the disclosure is not limited thereto.

In some embodiments, the source contacts280and the drain contacts290may protrude into the spacers300with respect to the portions1361of interlayer dielectric layer136. That is, the outer side surfaces of the source contacts280and the drain contacts290in contact with the spacers300may be substantially straight along the Z direction, while may present some curvature along the X and/or Y direction. For example, from what could be considered core regions282of the source contacts280, convexities284may protrude into the spacers300along the Y direction with respect to the side surfaces136s2of the portions1361of interlayer dielectric layer136. The convexities284may be formed at both sides of the core region282with respect to the Y direction. Furthermore, a convexity286may protrude from the core region282into the spacers300along the X direction, at an opposite side of the core region282with respect to the portion of interlayer dielectric layer136. As a way of example, the size280L of the source contacts280along the Y direction (measured as the distance between the peaks of the convexity284) may be up to about 1.5 times the size136L of the adjacent portion of interlayer dielectric layer136. For example, the ratio of the size280L to the size136L may be about in the range from 1 to 1.5. In some embodiments, the size280L may be about in the range from 10 angstroms to 300 angstroms, however the disclosure is not limited thereto. In some embodiments, the source contacts280may have a slightly elongated shape along the Y direction. For example, the size280W along the X direction may be about in the range from 10 angstroms to 100 angstroms.

Similarly, the drain contacts290may be considered to include core regions292delimited along the X direction by the interlayer dielectric layer136, and convexities294protruding into the spacers300at opposite sides of the core regions292along the Y direction. The size290L of the drain contacts290along the Y direction (measured as the distance between the peaks of the convexities294) may be in a similar range as previously described for the size280L of the source contact280. In some embodiments, the size290L of the drain contacts290may be substantially equal to the size280L of the source contacts280. For example, the ratio of the size290L to the size136L may be about in the range from 1 to 1.5. In some embodiments, the drain contacts290may be slightly wider along the X direction than the source contacts280, for example with a size290W along the X direction about in the range from 10 angstroms to 200 angstroms.

In some embodiments, the contact vias320connecting the drain contacts290to the conductive lines310may land in correspondence of the core regions292, while the contact vias330connected to the source contacts280may land on the convexities284. For example, for a pair of unit cells202,204sharing the same drain contact290, the contact vias330contacting the source contacts280may be disposed at opposite sides of the conductive line310along the Y direction. However, the disclosure is not limited thereto, and other configurations are possible. For example, the conductive line310may overlay the convexities294, so that the contact via320lands on the convexities294, while one or both of the contact vias330land on the core regions282.

In some embodiments, the spacers300present regions of varying thickness, where the thickness of the spacer may be measured as the distance (gap) between facing elements along the X and/or Y direction, for example. For example, the gap136G between portions1361of interlayer dielectric layer136belonging to unit cells202,204consecutively aligned along the Y direction may be larger than the gaps284G or294G between the facing convexities284,294of the source contacts280and the drain contacts294(where the gaps284G,294G may be measured in correspondence of the peaks of the convexities284,294) of the same unit cells202,204. For example, the gaps284G,294G may independently be about in the range from 5 angstroms to 1000 angstroms, and the gaps136G may be about in the range from 10 angstroms to 1000 angstroms, so that the ratio of the gap284G or294G to the hap136G may be about in the range from 0.5 to 1. That is, along the Y direction, the spacers300may be thicker in correspondence of the portions1361of interlayer dielectric layer136and may be thinner in correspondence of the source contacts280and drain contacts290. Similarly, the spacers may present regions of varying thickness along the X direction. For example, the gap286G between facing convexities286of source contacts280belonging to consecutive unit cells202,204along the X direction not sharing a common drain contact290may be smaller than the gap280G between the peaks of the convexities284of the same source contacts280. Both the gaps286G and280G may be measured along the X direction, in correspondence of the peaks of the convexities286and284, respectively. For example, the gap280G may be between about 1.1 to 2000 times the gap286G. For example, the gap286G between the peaks of convexities286may be about in the range from 5 angstroms to 1000 angstroms, and the gap280G between the peaks of convexities284may be about in the range from 5.5 angstroms to 10000 angstroms.

It should be noted that while the above description presented the semiconductor device SD10as including one transistor array170within the interconnection structure105, the disclosure is not limited thereto. For example, in some embodiments, multiple transistor arrays170may be stacked on each other. Furthermore, while the conductive lines210were shown to contact the unit cells202,204from the side of the semiconductor substrate100, the disclosure is not limited thereto. In some embodiments, the conductive lines210may contact the unit cells202,204from the opposite side with respect to the semiconductor substrate100.

In some embodiments, the transistor array170may be configured as a memory array, with the conductive lines210acting a word lines, the conductive lines310acting as bit lines, and the unit cells202,204corresponding to memory cells. For example, the source contacts280may be connected to suitable memory elements, so that the transistor array170may be configured as a dynamic random-access memory (DRAM), a high-density non-volatile memory such as a magneto-resistive random-access memory (MRAM), a resistive random-access memory (RRAM), a phase-change random-access memory (PCRAM), a conductive bridging random-access memory (CBRAM), or the like.

In the following, some aspects of a manufacturing method of the semiconductor device SD10will be illustrated with reference toFIG.5AtoFIG.5P.FIG.5AandFIG.5Bare schematic cross-sectional views of a region of structures formed during a manufacturing method of the semiconductor device SD10according to some embodiments of the disclosure. The views ofFIG.5CtoFIG.5Pare schematic cross-sectional views of structures formed during a manufacturing method of the semiconductor device SD10corresponding to a region where the transistor array170is formed, for example corresponding to the area350inFIG.5B.

Referring toFIG.5A, in some embodiments, the transistors110,120are formed on the semiconductor substrate100during front-end-of-line processes. The source and drain regions112,114,122,124may be formed according to any suitable process, such as epitaxial growth, ion implantation, etc. The gate structures116,128may be formed according to any suitable process, for example by a gate replacement process employing dummy gate structures. The interlayer dielectric layer132may be blanketly formed over the semiconductor substrate100, burying the source/drain regions112,114,122,124and the dummy gate structures. The dummy gate structures may then be removed and the gate structures116,128may be formed in place of the dummy gate structures. The lower metallization layers162,164of the interconnection structure105(illustrated inFIG.1) may then be formed in the interlayer dielectric layer132, up to the level where the transistor array170is to be formed.

InFIG.5B, the etch stop layer140is blanketly formed on the interlayer dielectric layer132. For example, the etch stop layer140may be a composite etch stop layer, including multiple layers143,144of different materials. The interlayer dielectric layer134may then be blanketly formed over the etch stop layer140. The interlayer dielectric layer134may then be patterned to include openings340in correspondence of the intended locations of the conductive lines210. For example, the openings340may be a series of parallel trenches elongated along the Y direction and disposed at a distance from each other along the Y direction. The openings may be filled by conductive material to form the conductive lines210, for example by deposition, plating or the like. In some embodiments, the conductive material is formed so as to initially extend on the interlayer dielectric layer134, and a planarization process (e.g., chemical mechanical polishing, grinding, or the like), is performed until the interlayer dielectric layer134is once again exposed, leaving the conductive lines210in the openings340.

InFIG.5C, the etch stop layer150is blanketly formed on the interlayer dielectric layer134. In some embodiments, the etch stop layer150may be a composite etch stop layer, including multiple layers152,154,156of different materials. The interlayer dielectric layer135may be blanketly formed over the etch stop layer150and then patterned to include gate trenches362in correspondence of the intended locations of the gate patterns220and via trenches364in correspondence of the intended locations of the contact vias230. The via trenches364may be extended through the etch stop layer150to expose regions of the underlying conductive lines210, so that the gate patterns220may be connected to the conductive lines210. The gate patterns220and contact vias230may be formed in the interlayer dielectric layer135according to any suitable process, such as damascene, dual damascene, or the like. In some embodiments, the gate trenches362and the via trenches264may be filled together by conductive material, for example by deposition, plating or the like. In some embodiments, the conductive material is formed so as to initially extend on the interlayer dielectric layer135, and a planarization process (e.g., chemical mechanical polishing, grinding, or the like), is performed until the interlayer dielectric layer135is once again exposed.

InFIG.5D, the gate dielectric layer240, the semiconductor channel layer250, the cap layer260, the hard mask layer270, and the interlayer dielectric layer136are sequentially and blanketly formed over the interlayer dielectric layer135and the gate patterns220. In some embodiments, the stacked layers240,250,260,270,136may be formed by a sequence of suitable processes to the desired thicknesses, such as deposition (CVD, PVD, ALD), spin-coating, or the like.

InFIG.5E, the interlayer dielectric layer136and the hard mask layer270are patterned to form a contact trench370exposing at its bottom sections of the cap layer260. In some embodiments, the contact trench370is formed by one or more etching steps. The etching may be any acceptable etch process, such as dry etching, plasma etching, ion beam etching (IBE), the like, or a combination thereof. In some embodiments, the etching may be anisotropic. In some embodiments, one or more auxiliary masks (not illustrated) may be employed to define the pattern of the interlayer dielectric layer136during a first etching step, which pattern is then transferred to the hard mask layer270. In some embodiments, portions1361of the interlayer dielectric layer136may remain interspersed within the contact trench370, which portions1361of interlayer dielectric layer136correspond to the separating structures between source contacts280and drain contacts290previously discussed with reference toFIG.4A.

InFIG.5F, a resist mask380is formed filling the contact trench370and further covering the interlayer dielectric layer136. That is, the resist mask380may be formed of a thickness larger than the depth of the contact trench370. In some embodiments, the resist mask380is a composite structure, including a bottom anti-reflective coating layer and a resist material disposed on the bottom anti-reflective coating layer. In some embodiments, the resist mask380includes a photoactive material. In some embodiments, the photoactive material is a positive photoresist. In some embodiments, the photoactive material is a negative photoresist. Referring toFIG.5G, in some embodiments, the resist mask380is patterned to include spacer openings382exposing at their bottom the cap layer260. In some embodiments, the spacer openings382form a reticulate structure within the contact trench370, with openings extending along the X direction intersecting openings extending along the Y direction. Pairs of portions1361of interlayer dielectric layer136may remain within the meshes of the reticulate structure of the spacer openings382, for example one pair per mesh. In some embodiments, the spacer openings382may be formed by exposure and development of the resist mask380. InFIG.5H, the spacer openings382are further extended through the cap layer260and the semiconductor channel layer250so as to expose at their bottom the gate dielectric layer240. In some embodiments, the spacer openings382may be extended through one or more etching steps. The etching may be any acceptable etch process, such as dry etching, plasma etching, ion beam etching (IBE), the like, or a combination thereof. In some embodiments, the etching may be anisotropic. In some embodiments, the spacer openings382may be further extended through the gate dielectric layer240.

Referring toFIG.5I, in some embodiments, a spacer material302is deposited within the spacer openings382and further on top of the resist mask380. In some embodiments, the spacer material302fills the spacer openings and further extends on the top surface380tof the resist mask380. The spacer material302may be formed by any suitable process, such as ALD, PVD, CVD, or the like. Referring toFIG.5IandFIG.5J, the spacer material302may be etched back until the top surface380tof the resist mask380is exposed, while the spacers300remains filling the spacer openings382.

Referring toFIG.5JandFIG.5K, in some embodiments, the resist mask380is removed, for example via ashing or stripping, so that the cap layer260at the bottom of the contact trench370is once again exposed. Upon removal of the resist mask380, a network (e.g., a meshed structure) formed by the spacers300remains in the contact trench370, dividing the contact trench370in a plurality of regions390in which pairs of unit cells202,204sharing a same drain contact290(as illustrated inFIG.4A, for example) are subsequently formed, as further discussed in the following. The regions390may correspond to the meshes of the reticulum formed by the spacers300.

Referring toFIG.5L, an isotropic etching step may be performed to round the corners of the spacers300. For example, the isotropic etching may be dry etching, such as plasma etching. In some embodiments, following the etching step, the spacers300may present rounded tips300tas well as concavities where the sidewalls300sof the spacers300are exposed within the contact trench370. On the other hand, in regions where the spacers300contacts the portions of interlayer dielectric136, the sidewalls300sof the spacers300may be protected during the etching step, so that no material is removed. In some embodiments, rounding the corners of the spacers300may facilitate subsequent metal filling steps.

InFIG.5M, the contact trench370is further extended through the cap layer260to expose the semiconductor channel layer250at its bottom. For example, an etching step may be performed to remove the portions of the cap layer260exposed at the bottom of the contact trench370. The etching may be any suitable etching process, such as dry etching, plasma etching, ion beam etching (IBE), the like, or a combination thereof. In some embodiments, the etching may be anisotropic.

Referring toFIG.5MandFIG.5N, in some embodiments a metallic material400is disposed in the contact trench370. For example, the metallic material400may be formed by deposition (e.g., CVD, PVD, ALD, etc.), plating, or the like. In some embodiments, the metallic material400fills the contact trench370and further buries the spacers300. That is, the metallic material400may be formed of sufficient thickness to completely cover the tops300tof the spacers300and extend on the interlayer dielectric layer136. In some embodiments, the metallic material400occupies the concavities of the spacers300formed during the previous corner rounding step. That is, convexities of the metallic material400may be formed in correspondence of the concavities of the spacers300.

Referring toFIG.5NandFIG.5O, in some embodiments, a planarization process (e.g., grinding, chemical mechanical polishing, or the like) may be performed to remove portions of the metallic material400and the spacers300until the top surface136tof the interlayer dielectric layer136is exposed. After planarization, the source contacts280, the drain contacts290, and the spacers300remain filling the contact trench370, with corresponding top surfaces280t,290t,300tsubstantially coplanar with the top surface136tof the interlayer dielectric layer136. InFIG.5P, the interlayer dielectric layer138is formed over the planarized top surfaces136t,280t,290t,300t. The conductive lines310may then be formed embedded in the interlayer dielectric layer136, with the contact vias320connecting the conductive lines310to the associated drain contacts290. In some embodiments, the structure ofFIG.1may be obtained from the structure ofFIG.5Pby forming additional interlayer dielectric layers (e.g., the interlayer dielectric layer139) and metallization layers182,184, as well as the passivation layer190and the contact pads186.

As illustrated inFIG.5AtoFIG.5P, in some embodiments, the spacers300are formed within the spacer openings382of a resist mask380before the source contacts280and the drain contacts290are formed. By doing so, the shapes and positions of the source contacts280and the drain contacts290are defined by the final spacers300, rather than by dummy spacers which are then substituted with the final spacers. That is, in the process illustrated above, the use of dummy spacers and the processes involved in the replacement of the dummy spacers with the final spacers may be avoided. Therefore, the manufacturing process may be simplified and the production costs reduced, for example by reducing the number of masks required to define the positions of the source contacts280, the drain contacts290, and the spacers300. In some embodiments, the simplification of the process may reduce the production costs as well as the variability of the manufactured structures, increasing the process reliability and reproducibility, even for high-density structures.

FIG.6is a schematic cross-sectional view of a region of a transistor array172of a semiconductor device SD12according to some embodiments of the disclosure. The view ofFIG.6may be taken in correspondence of a region as illustrated inFIG.5P.FIG.7Ais a schematic cross-sectional view of a region of the transistor array172according to some embodiments of the disclosure. The view ofFIG.7Ais taken in correspondence of the region illustrated inFIG.4A.FIG.7Bis a schematic bottom view of the same region illustrated inFIG.7Aaccording to some embodiments of the disclosure. The view ofFIG.7Bcorresponds to the view ofFIG.7A, with added the footprints of some elements disposed along the negative Z direction with respect to the plane of view ofFIG.7A(e.g., moving towards the semiconductor substrate100illustrated inFIG.1).FIG.7Cis a schematic top view of the same region illustrated inFIG.7Aaccording to some embodiments of the disclosure. The view ofFIG.7Ccorresponds to the view ofFIG.7A, with added the footprints of some elements disposed along the positive Z direction with respect to the plane of view ofFIG.7A(e.g., moving away from the semiconductor substrate100illustrated inFIG.1).

In some embodiments, the semiconductor device SD12may have a similar structure and may be manufactured according to similar processes as previously described for the semiconductor device SD10, and the corresponding description may be considered to equally apply, unless addressed in the following. A difference between the semiconductor device SD10and the semiconductor device SD12lies in that adjacent unit cells202,204may not share a drain contact290. Rather, the unit cells202,204may have dedicated drain contacts290as well as source contacts280and gate patterns220. The source contact280and the drain contact290of a given cell202or204may be separated by portions1361of the interlayer dielectric layer136, and separated by the source contacts280, drain contacts290, and portions1361of the interlayer dielectric layer136of the other unit cells202,204by the spacers300.

In some embodiments, the portions1361of interlayer dielectric layer136may have similar shapes and sizes136L,136W as previously described for the semiconductor device SD10. Similarly, the source contacts280may have similar shapes and sizes280L,280W as previously described for the semiconductor device SD10. That is, the source contacts280may include core regions282and convexities284and286protruding into the spacers300along the Y direction and the X direction, respectively. In some embodiments, the drain contacts290also includes core regions292and convexities294protruding into the spacers along the Y direction, similar to the semiconductor device SD10. Furthermore, the drain contacts290may include convexities296protruding from the core regions292into the spacers300along the X direction, at an opposite side of the core regions292with respect to the adjacent portions1361of the interlayer dielectric layer136. In some embodiments, the size290W of the drain contacts290along the X direction may be about in the range from 10 angstroms to 100 angstroms.

In some embodiments, the spacers300still presents region of varying thickness according to whether the spacers300are in contact with the interlayer dielectric layer136or the source contacts280or the drain contacts290. For example, the spacers300may be thicker in correspondence of regions contacting the interlayer dielectric layer136, and thinner in correspondence of regions contacting the source contacts280or the drain contacts290. For example, the spacers300may have thickness along the Y direction corresponding to the gaps136G,284G, and294G respectively located between facing portions of interlayer dielectric layer136, convexities284of the source contacts280, and convexities294of the drain contacts290in the same ranges as previously described for the semiconductor device SD10. Furthermore, the spacers300may have a thickness in correspondence to the gaps289G between the peaks of the convexities284and294of facing source contacts280and drain contacts290belonging to adjacent unit cells202,204which is larger than a thickness in correspondence to the gaps296G between the peaks of the convexities286and296of the same source contacts280and drain contacts290. For example, the gaps289G may be about in the range from 5.5 angstroms to 10000 angstroms, and the gaps296G may be about in the range from 5 to 1000 angstroms. In some embodiments, the ratio of the thicknesses of the spacers300in correspondence of the gaps289G to the gaps296G may be about in the range from 1.1 to 2000.

In some embodiments, the contact vias230connecting the gate patterns220to the conductive lines210are disposed at different level heights along the Y direction for unit cells202,204consecutively disposed adjacent to each other with respect to the X direction. However, the disclosure is not limited thereto. In some embodiments, the contact vias230of unit cells202,204consecutively disposed adjacent to each other with respect to the X direction at the same level height along the Y direction may be formed at the same level height along the Y direction. In some embodiments, the contact vias330contacting the source contacts280may be formed on a same side (e.g., along the positive Y direction) with respect to the conductive lines310contacting the associated drain contacts290for all unit cells202,204. However, the disclosure is not limited thereto. In some embodiments, the contact vias330of unit cells202,204belonging to rows at different level heights along the Y direction may be formed at different sides (along the Y direction) with respect to the conductive lines310. For examples, the contact vias330of a first row of unit cells202,204located at a first level height along the Y direction may be formed at one side with respect to the associated conductive lines310(e.g., at the positive Y direction), while the contact vias330of a second row of unit cells202,204adjacent to the first row and located at a second level height along the Y direction may be formed at an opposite side with respect to the associated conductive lines310(e.g., at the negative Y direction).

FIG.8is a schematic cross-sectional view of a region of a transistor array174of a semiconductor device SD14according to some embodiments of the disclosure. The view ofFIG.8may be taken in correspondence of a region as illustrated inFIG.5P.FIG.9Ais a schematic cross-sectional view of a region of the transistor array174according to some embodiments of the disclosure. The view ofFIG.9Ais taken in correspondence of a region as illustrated inFIG.4A.FIG.9Bis a schematic bottom view of the same region illustrated inFIG.9Aaccording to some embodiments of the disclosure. The view ofFIG.9Bcorresponds to the view ofFIG.9A, with added the footprints of some elements disposed along the negative Z direction with respect to the plane of view ofFIG.9A(e.g., moving towards the semiconductor substrate100illustrated inFIG.1).FIG.9Cis a schematic top view of the same region illustrated inFIG.9Aaccording to some embodiments of the disclosure. The view ofFIG.9Ccorresponds to the view ofFIG.9A, with added the footprints of some elements disposed along the positive Z direction with respect to the plane of view ofFIG.9A(e.g., moving away from the semiconductor substrate100illustrated inFIG.1).

In some embodiments, the semiconductor device SD14may have a similar structure and may be manufactured according to similar processes as previously described for the semiconductor device SD10, and all the corresponding description may be considered to equally apply, unless addressed in the following. So, for example, the transistor array174may include plural unit cells412,414disposed in an array configuration, arranged along intersecting rows and columns. Parallel conductive lines430extending along the X direction may be embedded in an interlayer dielectric layer422of an interlayer dielectric420and may be connected by contact vias440to the unit cells412,414. Unit cells412,414located at a same level height along the Y direction may be connected to a same conductive line430. The unit cells412,414may include stacked semiconductor channel layers450, gate dielectric layers460, cap layer470, and hard mask layers475, which may be all formed with similar materials as previously described. The semiconductor channel layers450may be separated from the conductive lines430by the interlayer dielectric layer424. A difference between the semiconductor device SD14and the semiconductor device SD10lies in that the gate patterns480which control current flows in the unit cells412,414are stacked on the gate dielectric layer460in between the source contacts490and the drain contacts500. That is, the gate patterns480may be formed in the same interlayer dielectric layer426as the source contacts490and the drain contacts500. In some embodiments, the gate patterns480land on the gate dielectric layer460, while the source contacts490and the drain contacts500may extend through the gate dielectric layer460and, possibly, through the semiconductor channel layer450to land on the interlayer dielectric layer424.

In some embodiments, the conductive lines430contacting the drain contacts500may be located closer to the semiconductor substrate100(illustrated, e.g., inFIG.1) than the gate patterns480, while the conductive lines530which control the gate patterns480may be located at an opposite side of the gate patterns480with respect to the semiconductor substrate100(and, for example, the conductive lines430). For example, the conductive lines530may extend along the Y direction, with individual conductive lines530contacting the gate patterns480of unit cells412,414located at a same level height along the X direction. The conductive lines530may be embedded in the interlayer dielectric layer428which extends on the interlayer dielectric layer426, the gate patterns480, the source contacts490, the drain contacts500, and the spacers510. Contact vias520may connect the conductive lines530to the associated gate patterns480.

In some embodiments, pairs of unit cells412,414may share a drain contact500, and be surrounded by the spacers510. So, for example, two gate patterns480may be disposed at opposite sides along the X direction of a common drain contact500, being separated from the drain contact500by portions4261of the interlayer dielectric layer426, and two source contacts480may be disposed at opposite sides of the gate patterns480with respect to the drain contact500, being separated from the gate patterns480by portions4261of the interlayer dielectric layer426. In some embodiments, the portions4261of the interlayer dielectric layer426interposed between the gate patterns480, the source contacts490, and the drain contacts500may have similar shapes and sizes462L,462W as previously described for the portions4261of interlayer dielectric layer136of the semiconductor device SD10(illustrated, e.g., inFIG.4A). Similarly, the source contacts490may have similar shapes and sizes490L,490W as previously described for the source contacts280of the semiconductor device SD10. That is, the source contacts490may include core regions492and convexities494and496protruding into the spacers510along the Y direction and the X direction, respectively. In some embodiments, the drain contacts500and the gate patterns480also include core regions (502and482, respectively) and convexities (504and484, respectively) protruding into the spacers along the Y direction, similar to the drain contacts290of the semiconductor device SD10. In some embodiments, the size480L of the gate pattern480along the Y direction may be about in the range from 10 angstroms to 300 angstroms, and the size480W of the gate patterns480along the X direction may be about in the range from 10 angstroms to 200 angstroms. Similarly, the size500L of the drain contacts500along the Y direction may be about in the range from 10 angstroms to 300 angstroms, and the size500W of the drain contacts500along the X direction may be about in the range from 10 angstroms to 200 angstroms.

In some embodiments, the spacers510still presents region of varying thickness according to whether the spacers510are in contact with the interlayer dielectric layer426, the gate patterns480, the source contacts490, or the drain contacts500. For example, the spacers510may be thicker in correspondence of regions contacting the interlayer dielectric layer426, and thinner in correspondence of regions contacting the gate patterns480, the source contacts490, or the drain contacts500. For example, the spacers510may have thickness along the Y direction corresponding to the gaps426G,484G,494G, and504G respectively located between facing portions of interlayer dielectric layers426, convexities484of the gate patterns480, convexities494of the source contacts490, and convexities504of the drain contacts500. In same embodiments, the gaps426G,494G,504G may be in the same ranges and ratios as previously described for the gaps136G,284G,294G of the semiconductor device SD10. The gap484G may be about in the range from 5 angstrom to 1000 angstroms. In some embodiments, a ratio of the gap484G to the gap426G may be about in a range from 0.5 to 1. Furthermore, the spacers510may have a thickness in correspondence to the gaps490G between the peaks of the convexities494of source contacts480belonging to adjacent unit cells412,414which do not share a same drain contact500which is larger than a thickness in correspondence to the gaps496G between the peaks of the convexities496of the same source contacts490. For example, the gaps490G may be in the range from 5.5 angstroms to 10000 angstroms, and the gaps496G may be about in the range from 5 angstroms to 1000 angstroms. In some embodiments, the ratio of the thicknesses of the spacers510in correspondence of the gaps490G to the gaps496G may be about in the range from 1.1 to 2000.

In some embodiments, the contact vias520connecting the gate patterns480to the conductive lines530may be disposed at the same level heights along the Y direction for unit cells412,414consecutively disposed adjacent to each other with respect to the X direction at a same level height along the Y direction, whether or not such unit cells412,414share a same drain contact500. However, the disclosure is not limited thereto. In some embodiments, the contact vias520of unit cells412,414consecutively disposed adjacent to each other with respect to the X direction may be formed at different level heights along the Y direction. In some embodiments, the contact vias520connecting the gate patterns480to the conductive lines530may land in correspondence of the core regions482, however the disclosure is not limited thereto. In some alternative embodiments, the contact vias520may land in correspondence of the convexities484. In some embodiments, the contact vias440connecting the drain contacts500to the conductive lines430may land in correspondence of the core regions502, while the contact vias540connected to the source contacts490may land on the convexities494. For example, for a pair of unit cells412,414sharing the same drain contact500, the contact vias540contacting the source contacts490may be disposed at opposite sides of the conductive line430along the Y direction. However, the disclosure is not limited thereto, and other configurations are possible. For example, the conductive lines430may overlay the convexities504, so that the contact vias440land on the convexities504, while one or both of the contact vias540land on the core regions492.

In some embodiments, the semiconductor device SD14may be manufactured following substantially the same process as previously described with respect to the semiconductor device SD10inFIG.5AtoFIG.5P. Referring toFIG.10, in some embodiments, the spacers510may be formed so as to extend through the semiconductor channel layer450. Furthermore, before the metallic material of the gate patterns480, the source contacts490, and the drain contacts500is disposed (e.g., at a step corresponding toFIG.5Kin the process previously described), an additional resist mask550may be provided including contact openings553,554which are used to remove further portions of the semiconductor channel layer450and the gate dielectric layer460beside the spacers510and in correspondence of the contact vias440, thus defining the position of the source contacts490and the drain contacts500. For example, the contact openings554may expose at their bottom the contact vias440, thus defining the location of the drain contacts500, while the contact openings553may expose at their bottom the contact vias540. In some embodiments, the additional resist mask550may be formed anew after the resist mask used to define the spacers510is removed (e.g., the resist mask380inFIG.5G). Alternatively, the additional resist mask550may be formed from the resist mask used to define the spacers510after the spacer material is removed from the top of the resist mask, for example via additional exposure and development. Upon removal of the resist mask550, process steps similar to the ones previously described with reference toFIG.5LtoFIG.5Pmay be performed to form the semiconductor device SD14.

It should be noted that the features previously described may also be implemented in the structure of the semiconductor device SD14. For example, adjacent unit cells412,414are not limited to share a common drain contact500, and, in some embodiments, the unit cells412,414may have dedicated individual drain contacts500, as previously discussed for the semiconductor device SD12with reference toFIG.7A. Consequently, the drain contacts500may also include convexities along the X direction, other than the convexities504along the Y direction as illustrated inFIG.9A.

In accordance with some embodiments of the disclosure, a semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

In accordance with some embodiments of the disclosure, a semiconductor device includes a semiconductor substrate, an interlayer dielectric, transistors, and spacers. The interlayer dielectric is disposed on the semiconductor substrate and includes a first interlayer dielectric layer. The transistors are embedded in the interlayer dielectric and are arranged in an array of rows and columns. The spacers separate adjacent transistors of the transistors. The transistor includes semiconductor channel layers, source contacts, drain contacts, and gate patterns. The semiconductor channel layers extend along a first direction. The first direction is an extending direction of the rows of the array. The source contacts contact first ends of the semiconductor channel layers. The drain contacts contact second ends of the semiconductor channel layers. The gate patterns overlap middle sections of the semiconductor channel layers. The middle sections join the first ends to the corresponding second ends. The source contacts are separated from the drain contacts by portions of a first interlayer dielectric layer of the interlayer dielectric layers. The source contacts and the drain contacts both comprise core regions and first convexities protruding from the core regions into the spacers.

In accordance with some embodiments of the disclosure, a manufacturing method of a semiconductor device includes the following steps. A semiconductor channel layer is formed over a first interlayer dielectric layer. A second interlayer dielectric layer is formed over the semiconductor channel layer. The second interlayer dielectric layer is patterned to form isolated portions and form a contact trench. The isolated portions of the second interlayer dielectric layer remains in the contact trench. A patterned resist mask is formed in the contact trench and on the second interlayer dielectric layer. The patterned resist mask includes a reticulate opening formed within the contact trench. The reticulate opening is filled with spacer material. The patterned resist mask and spacer material are removed to form spacers with meshes within the contact trench. The isolated portions of the second interlayer dielectric layer are located within the meshes of the spacers. The meshes of the spacers in the contact trench are filled with metallic material to form source contacts and drain contacts. The source contacts and the drain contacts contact the semiconductor channel layer.