Semiconductor device

Provided is a semiconductor device and a method for forming the same. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.

TECHNICAL FIELD

The present invention relates to a semiconductor device.

BACKGROUND ART

With the development of a technique for reducing the power consumption of power conversion apparatuses, there are growing expectations for a technique for reducing the power consumption of a power device which plays a key role in the power conversion apparatus. For example, among various types of power devices, an insulated gate bipolar transistor (IGBT) has been generally used which can reduce the on-voltage using the conductivity modulation effect and whose operation is easily controlled by the control of a voltage-driven gate. The use of the IGBT makes it possible to ensure a high breakdown voltage and to significantly improve a switching speed even in a power device provided in a circuit area in which a large amount of current flows.

However, with an increase in the switching speed, EMI (Electro Magnetic Interference) noise problems have emerged. In particular, it is necessary to suppress the EMI noise to an allowable level when the IGBT is turned on. As a result, an increase in the switching speed is limited and it is difficult to sufficiently reduce switching loss. It is important to achieve a soft recovery free wheeling diode (FWD) which is combined with the IGBT in order to reduce the EMI noise.

In order to achieve the soft recovery FWD, it is necessary to reduce the carrier density of an anode to reduce a reverse recovery current during reverse recovery. In addition, it is necessary to increase the carrier density of a cathode in order to suppress the oscillation of a voltage-current waveform due to the depletion of the carriers. As a structure in which the carrier density of the anode is low and the carrier density of the cathode is high, the following structures have been known: an anode structure with low injection efficiency; a structure in which a Schottky diode is locally arranged; and a structure which controls a local lifetime to optimize a carrier distribution.

In recent years, as another structure in which the carrier density of the anode is low and the carrier density of the cathode is high, a structure has been proposed which forms a floating buried p layer on the cathode side, avalanches a pn diode on the cathode side when a high voltage is applied, and forcedly increases the carrier density of the cathode to achieve soft recovery (for example, see the following Patent Documents 1 and 2). The FWD according to the related art disclosed in the following Patent Documents 1 and 2 will be described with reference toFIG. 29.FIG. 29is a cross-sectional view illustrating the structure of the FWD according to the related art.

As illustrated inFIG. 29, the FWD according to the related art includes an active region100and an edge termination structure portion (edge portion)110surrounding the active region100, which are provided in an n−semiconductor substrate that will be an n−drift region101. A p+anode layer102is provided in a surface layer of the front surface of the n−semiconductor substrate in the active region100. A field limiting ring (FLR)108is provided in a floating p-type region in the edge termination structure portion110. An interlayer insulating film109covers the front surface of the n−semiconductor substrate in the edge termination structure portion110. An anode electrode103is provided on the surface of the p+anode layer102and has an end portion which extends onto the interlayer insulating film109.

An n+cathode layer104is provided in a surface layer of the rear surface of the n−semiconductor substrate so as to extend from the active region100to the edge termination structure portion110. An n buffer layer105is provided between the n−drift region101and the n+cathode layer104so as to extend from the active region100to the edge termination structure portion110. A plurality of buried p layers106are provided in a surface layer of the n buffer layer105which is close to the n+cathode layer104at predetermined intervals so as to extend from the active region100to the edge termination structure portion110. The buried p layer106comes into contact with the n+cathode layer104. A cathode electrode107is provided on the entire rear surface of the n−semiconductor substrate.

As another FWD, a device has been proposed which includes a first electrode, a first layer of a first conductivity type that is provided on the first electrode, a second layer that is a second conductivity type different from the first conductivity type and is provided on the first layer, a third layer that is provided on the second layer, a second electrode that is provided on the third layer, and a fourth layer that is the second conductivity type and is provided between the second layer and the third layer. In the device, the third layer includes a first portion which is the second conductivity type and has an impurity concentration peak value greater than the impurity concentration peak value of the second layer and a second portion of the first conductivity type. The ratio of the area of the second portion to the total area of the first and second portions is equal to or greater than 90% and equal to or less than 95% (for example, see the following Patent Document 3).

CITATION LIST

Patent Document

Patent Document 3: JP 2010-283132 A

DISCLOSURE OF THE INVENTION

Problem to be Solved by the Invention

However, the problems caused by an increase in the switching speed include the problem that the maximum voltage which is applied during the reverse recovery of the FWD or a current change rate di/dt exceeds a safe operating area (SOA), which results in element breakdown, in addition to the EMI noise problem. For example, one of the causes of the element breakdown is that the carriers which are spread in an inactive region (for example, the edge termination structure portion) when the FWD is turned on move to the anode electrode through a contact of the active region (a junction between the p+anode layer and the anode electrode) during reverse recovery and a current is concentrated on an outer circumferential portion of the active region. Another example of the cause of the element breakdown is that the electric field intensity of the p+anode layer increases due to the curvature of an end portion of the p+anode layer. This problem is not solved by the soft recovery of the FWD.

In the techniques disclosed in Patent Documents 1 and 2 illustrated inFIG. 29, ion implantation is performed on the rear surface of the substrate, using an ion implantation mask which is formed on the rear surface of the substrate by photolithography as a mask, to form the plurality of buried p layers106. In this case, when the ion implantation mask is patterned, alignment is performed on the rear surface of the substrate on the basis of dicing lines on the front surface of the substrate. For example, a chip which is formed on a wafer with a diameter of 6 inches has a chip size of about 1 cm×1 cm and the width of the edge termination structure portion110is in the range of about 0.1 mm to 1 mm. Therefore, the width of the active region100is in the range of about 9 mm to 9.9 mm. Therefore, alignment accuracy on the rear surface of the substrate needs to be high in order to form a plurality of buried p layers106in the active region100and the edge termination structure portion110in a fine pattern with high dimension accuracy according to a design.

As a method for improving alignment accuracy on the rear surface of the substrate, a method has been known which places an n−semiconductor substrate on a transparent stage, with the front surface down and radiates infrared rays from the stage to the n−semiconductor substrate to detect the dicing lines in the front surface of the substrate. However, this method requires a special device for detecting the dicing lines in the front surface of the n−semiconductor substrate from the rear surface of the n−semiconductor substrate. Therefore, this method has the problem that costs increase.

The invention has been made in order to solve the above-mentioned problems of the related art and an object of the invention is to provide a semiconductor device which achieves soft recovery and has a high breakdown voltage during reverse recovery.

Means for Solving Problem

In order to solve the above-mentioned problems and achieve the object of the invention, a semiconductor device according to an aspect of the invention has the following characteristics. A second semiconductor region of a second conductivity type is selectively provided in a surface layer of one surface of a first semiconductor region of a first conductivity type. A first electrode which comes into contact with the second semiconductor region is provided. A third semiconductor region of the first conductivity type which has a higher impurity concentration than that of the first semiconductor region is provided in a surface layer of the other surface of the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a position deeper than the third semiconductor region from the other surface of the first semiconductor region. A second electrode which comes into contact with the third semiconductor region is provided. An end portion of the fourth semiconductor region is located inside a side surface of the first semiconductor region.

In the semiconductor device according to the above-mentioned aspect of the invention, the end portion of the fourth semiconductor region may be located inside an end portion of a junction between the second semiconductor region and the first electrode.

The semiconductor device according to the above-mentioned aspect of the invention may further include a fifth semiconductor region of the first conductivity type which is provided in the first semiconductor region so as to extend from the other surface of the first semiconductor region to a position deeper than the third semiconductor region and has an impurity concentration that is higher than the impurity concentration of the first semiconductor region and is lower than the impurity concentration of the third semiconductor region. An end portion of the third semiconductor region may be located inside the end portion of the junction. A Schottky junction between the fifth semiconductor region and the second electrode may be formed outside the third semiconductor region.

The semiconductor device according to the above-mentioned aspect of the invention may further include a sixth semiconductor region of the second conductivity type which is provided in the fifth semiconductor region provided outside the third semiconductor region so as to be separated from the third semiconductor region and the fourth semiconductor region.

In the semiconductor device according to the above-mentioned aspect of the invention, the fifth semiconductor region may be formed by a plurality of proton irradiation processes and a plurality of the fifth semiconductor regions may be arranged at different depths from the other surface of the first semiconductor region.

In the semiconductor device according to the above-mentioned aspect of the invention, the occupation area ratio of the surface area of the fourth semiconductor region to the surface area of an active region in which a main current flows may be equal to or greater than 90% and equal to or less than 98%.

In the semiconductor device according to the above-mentioned aspect of the invention, in the occupation area ratio of the surface area of the fourth semiconductor region to the surface area of an active region in which a main current flows, the occupation area ratio on an inner circumferential side of the position of a contact end portion, which is obtained by projecting a contact end portion of a contact region between the first electrode and the second semiconductor region from the one surface to the other surface, may be higher than the occupation area ratio on an outer circumferential side of the position of the contact end portion.

In the semiconductor device according to the above-mentioned aspect of the invention, the length of the fourth semiconductor region, which is disposed on an inner circumferential side of the position of a contact end portion obtained by projecting a contact end portion of a contact region between the first electrode and the second semiconductor region from the one surface to the other surface, in a direction horizontal to the other surface may be equal to or greater than 250 μm.

In the semiconductor device according to the above-mentioned aspect of the invention, a length L1of the fourth semiconductor region, which is disposed on an inner circumferential side of the position of a contact end portion obtained by projecting a contact end portion of a contact region between the first electrode and the second semiconductor region from the one surface to the other surface, in a direction horizontal to the other surface may satisfy the following expression:
L1≧{(q·μ·d·Np·Vbi)/J}1/2

(where J is the current density of a main current of the semiconductor device, q is an elementary charge, μ is hole mobility, d is the thickness of the fourth semiconductor region in a depth direction, Np is the impurity concentration of the fourth semiconductor region, and Vbi is the built-in potential of a pn junction between the fourth semiconductor region and the third semiconductor region).

In the semiconductor device according to the above-mentioned aspect of the invention, the fourth semiconductor region may be disposed on an inner circumferential side of the position of a contact end portion which is obtained by projecting a contact end portion of a contact region between the first electrode and the second semiconductor region from the one surface to the other surface and the distance of a separation portion between the position of the contact end portion and the end portion of the fourth semiconductor region may be equal to or less than 2000 μm.

According to the invention, the buried p layer (fourth semiconductor region) is uniformly provided and the end portion of the buried p layer is located inside the side surface (chip end portion) of the n−drift region (first semiconductor region). Therefore, during reverse recovery, an avalanche occurs in the pn junction between the buried p layer and the n+cathode layer and holes are injected from the n+cathode layer to the n−drift region. As a result, soft recovery characteristics are obtained. In addition, since a short circuit between the buried p layer and the cathode electrode does not occur in the chip end portion, it is possible to prevent a jump in the current-voltage waveform (I-V waveform).

In addition, according to the invention, since the end portion of the buried p layer is located inside the end portion of an anode contact (a junction between the second semiconductor region and the first electrode), the dynamic breakdown voltage of the active region is less than the dynamic breakdown voltage of an inactive region (for example, the edge termination structure portion). Therefore, it is possible to suppress the concentration of the electric field on the end portion of the anode contact during reverse recovery.

Furthermore, the p−layer which separates the n+cathode layer that extends to the outside of the buried p layer from the chip end portion is provided. Alternatively, the p−layer which is separated from the buried p layer and comes into contact with the cathode electrode is provided on the outer circumferential side of the buried p layer. Therefore, electrons are not injected into the inactive region and the diffusion of carriers to the inactive region is suppressed. As a result, the concentration of a current on the end portion of the p+anode layer (second semiconductor region) is reduced and the breakdown voltage during reverse recovery increases.

Effect of the Invention

According to the semiconductor device of the invention, it is possible to achieve soft recovery and to increase a breakdown voltage during reverse recovery.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of a semiconductor device according to the invention will be described in detail with reference to the accompanying drawings. In the specification and the accompanying drawings, in the layers or regions having “n” or “p” appended thereto, an electron or a hole means a majority carrier. In addition, symbols “+” and “−” added to n or p mean that impurity concentration is higher and lower than that of the layer without the symbols. In the description of the following embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and the description thereof will not be repeated.

The structure of a semiconductor device according to Embodiment 1 will be described.FIG. 1is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 1.FIG. 2is a characteristic diagram illustrating an impurity concentration distribution along the cutting line A-A′ ofFIG. 1. InFIG. 2, the horizontal axis indicates the distance from the rear surface of a substrate (an interface between an n+cathode layer4and a cathode electrode7) in the depth direction of the substrate and the vertical axis indicates impurity concentration along the cutting line A-A′ which traverses a rear-surface-side region of the substrate in the depth direction (which holds forFIGS. 9 and 13. As illustrated inFIG. 1, the semiconductor device according to Embodiment 1 includes an active region10and an edge termination structure portion (edge portion)11that surrounds the active region10, which are provided in an n−semiconductor substrate that will be an n−drift region (first semiconductor region)1. The active region10is a region in which a current flows when the semiconductor device is in an on state. The edge termination structure portion11has a function of reducing the electric field on the front surface side of the substrate and holding a breakdown voltage.

A p+anode layer (second semiconductor region)2is provided in a surface layer of the front surface of the n−semiconductor substrate in the active region10. A field limiting ring (FLR)8which is, for example, a floating p-type region is provided in the surface layer of the front surface in the edge termination structure portion11. The lifetime τp of a minority carrier (hole) in the n−drift region1is controlled to be, for example, equal to or less than 10 μs (non-killer), preferably, equal to or greater than 0.1 μs and equal to or less than 3 μs. An interlayer insulating film9covers the front surface of the n−semiconductor substrate in the edge termination structure portion11. An inner circumferential end portion of the interlayer insulating film9extends onto the surface of the p+anode layer2. An anode electrode (first electrode)3is provided on the surface of the p+anode layer2. An end portion of the anode electrode3extends onto the interlayer insulating film9.

The n+cathode layer (third semiconductor region)4is provided on a surface layer of the rear surface of the n−semiconductor substrate so as to extend from the active region10to the edge termination structure portion11. The cathode electrode (second electrode)7is provided on the entire rear surface of the n−semiconductor substrate, that is, the entire surface of the n+cathode layer4. An n buffer layer (fifth semiconductor region)5is provided in a portion of the n−drift region1close to the n+cathode layer4so as to extend from the active region10to the edge termination structure portion11. When an outer circumferential end portion of the n buffer layer5extends to a side surface1aof the n−semiconductor substrate, it is possible to reduce a leakage current and to hold the breakdown voltage. The n buffer layer5has a function of preventing a depletion layer, which is spread from a pn junction between the p+anode layer2and the n−drift region1when the semiconductor device is turned off, from reaching the n+cathode layer4. When the n buffer layer5does not have this function, it may come into contact with the n+cathode layer4or it may be separated from the n+cathode layer4.

In a portion of the n−drift region1close to the n+cathode layer4, a floating buried p layer (fourth semiconductor region)6is provided at a position that is deeper than the n+cathode layer4from the rear surface of the substrate. The buried p layer6is uniformly provided in a predetermined range of the active region10which comes into contact with the n+cathode layer4. When the n buffer layer5comes into contact with the n+cathode layer4, the buried p layer6is provided in the surface layer of the n buffer layer5close to the n+cathode layer4. When the buried p layer6is provided, the minority carriers are injected from the cathode to the n−drift region1during reverse recovery to avalanche a pn diode on the cathode side, thereby forcedly increasing carrier density on the cathode side. Therefore, it is possible to perform soft recovery. The impurity concentration of the buried p layer6is higher than the impurity concentration of the n buffer layer5and is lower than the impurity concentration of the n+cathode layer4. Specifically, the impurity concentration of the buried p layer6may be, for example, equal to or greater than about 1×1016/cm3and equal to or less than about 1×1019/cm3and preferably equal to or greater than about 1×1017/cm3and equal to or less than about 1×1018/cm3. When the impurity concentration of the buried p layer6is within the above-mentioned range, it is possible to prevent an increase in leakage current.

An end portion6aof the buried p layer6is located inside the side surface1aof the n−semiconductor substrate (in the active region10). That is, the end portion6aof the buried p layer6does not reach the side surface1a(chip side surface) of the n−semiconductor substrate. As such, when the end portion6aof the buried p layer6is located inside the side surface1aof the n−semiconductor substrate, snapback does not occur (snapback voltage≈0 V) and it is possible to prevent a jump in the current-voltage waveform (I-V waveform). The jump in the I-V waveform will be described below. In addition, the end portion6aof the buried p layer6is located inside the end portion of the n+cathode layer4. In this way, it is possible to prevent a short circuit due to the contact between the buried p layer6and the cathode electrode7.

As such, since the buried p layer6is not provided over the entire active region10and the entire edge termination structure portion11, the avalanche breakdown voltage (the voltage at which avalanche breakdown occurs) of the edge termination structure portion11can be greater than the avalanche breakdown voltage of the active region10, as compared to the structure in which the buried p layer6is provided over the entire active region10and the entire edge termination structure portion11. The reason is as follows. In the active region10, when a reverse voltage is applied, holes are generated due to the avalanche breakdown which occurs in the pn junction between the buried p layer6and the n+cathode layer4and a hole current flows to the p+anode layer2through the n−drift region1. The hole current becomes a base current in a parasitic pnp transistor including the p+anode layer2, the n−drift region1, and the buried p layer6and the parasitic pnp transistor operates. As a result, the avalanche breakdown voltage of the active region10is reduced.

Here, the avalanche breakdown voltage of the edge termination structure portion11can be calculated as follows. For example, a known device simulation is performed to calculate the breakdown voltage in the structure in which the edge termination structure portion is connected to the active region with a simple p-i-n (p-intrinsic-n) structure including a p+anode layer, an n−drift region, and an n+cathode layer. The calculated value may be used as the avalanche breakdown voltage of the edge termination structure portion11. In this way, the avalanche breakdown voltage of the active region10can be less than the avalanche breakdown voltage of the edge termination structure portion11. Therefore, an avalanche current can flow to the entire active region10. As a result, it is possible to prevent the concentration of a current on the edge termination structure portion11.

In addition, since the buried p layer6is not provided over the entire active region10and the entire edge termination structure portion11, it is possible to reduce the number of electrons injected into an inactive region (for example, the edge termination structure portion11) during reverse recovery. Therefore, it is possible to prevent the concentration of a current on an outer circumferential portion of the active region10, that is, an end portion3aof an anode contact due to the migration of the carriers, which are spread to the edge termination structure portion11, to the anode electrode3through the anode contact during reverse recovery.

It is preferable that the end portion6aof the buried p layer6be disposed at a position that is a first length t1inside from the end portion3aof the anode contact (a junction between the p+anode layer2and the anode electrode3) of the active region10(a position close to a central portion of an FWD cell). The FWD cell is a unit region including the p+anode layer2, the n+cathode layer4, the n buffer layer5, and the buried p layer6. The first length t1from the end portion3aof the anode contact to the end portion6aof the buried p layer6which is disposed inside the end portion3amay be equal to or less than a diffusion length Lhof the minority carrier (t1≦Lh). The reason is as follows. When the semiconductor device is in an on state, the buried p layer6enables the minority carriers, which are injected from the cathode to the n−drift region1, to reach the end portion3aof the anode contact. Therefore, it is possible to prevent a reduction in the effect obtained by the buried p layer6.

The diffusion length Lhof the minority carrier is represented by the following Expression (1). In the following Expression (1), the lifetime of the minority carrier is τhand a diffusion coefficient of the minority carrier is Dh. The diffusion coefficient Dhof the minority carrier is represented by the following Expression (2). In the following Expression (2), an elementary charge is q, a Boltzmann constant is K, an absolute temperature is T, and the mobility of the minority carrier is μh. KT/q is a thermal voltage at an absolute temperature T of 300 K.

Specifically, the diffusion coefficient Dhof the minority carrier is 1.56×10−3cm2/s, the mobility μhof the minority carrier is 0.06 cm2/Vs, and KT/q is 2.60×102eV. Therefore, when the lifetime τhof the minority carrier in the n−drift region1is 10 μs (that is, when the minority carrier is a non-killer), the diffusion length Lhof the minority carrier is 124.90 μm from the above-mentioned Expressions (1) and (2). When the lifetime τhof the minority carrier in the n−drift region1is 3 μs, the diffusion length Lhof the minority carrier is 68.41 μm. When lifetime τhof the minority carrier in the n−drift region1is 0.1 μs, the diffusion length Lhof the minority carrier is 12.49 μm.

Next, a method for manufacturing the semiconductor device according to Embodiment 1 will be described.FIG. 3is a flowchart illustrating the outline of the method for manufacturing the semiconductor device according to Embodiment 1. First, a front surface element structure, such as the p+anode layer2or the FLR8, is formed on the front surface side of the n−semiconductor substrate which will be the n−drift region1(Step S1). Specifically, a resist mask in which a region for forming the p+anode layer2and the FLR8is opened is formed on the front surface of the n−semiconductor substrate. Then, p-type impurity ions, such as boron (B) ions, are implanted into the front surface of the n−semiconductor substrate, using the resist mask as a mask.

Then, after the resist mask is removed, the implanted p-type impurities are thermally diffused to form the p+anode layer2and the FLR8. Then, the interlayer insulating film9is formed on the front surface of the n−semiconductor substrate. Then, a portion of the interlayer insulating film9corresponding to the active region10is removed to form an anode contact hole through which the p+anode layer2is exposed. In this way, the front surface element structure is formed on the front surface side of the n−semiconductor substrate. Then, the rear surface of the n−semiconductor substrate is ground to reduce the thickness of the n−semiconductor substrate (Step S2).

Then, n-type impurity ions, such as selenium (Se) ions, are implanted into the entire ground rear surface of the n−semiconductor substrate to form the n buffer layer5(Step S3). Then, a resist mask in which a region for forming the buried p layer6is opened is formed on the rear surface of the n−semiconductor substrate. For example, the resist mask covers the edge termination structure portion11and a portion of the active region10which is the first length t1inside from the end portion of the anode contact hole. Then, p-type impurity ions, such as boron ions, are implanted into the rear surface of the n−semiconductor substrate, using the resist mask as a mask, to form the buried p layer6in the active region10(Step S4).

It is preferable that, in the ion implantation of Step S4, boron concentration in the rear surface of the substrate be reduced such that the surface layer of the rear surface of the n−semiconductor substrate becomes an n-type region. Specifically, the p-type impurity concentration of the rear surface of the n−semiconductor substrate by ion implantation in Step S5, which will be described below, may be, for example, equal to or less than 1×1015/cm3. The reason is that, when the n+cathode layer4formed in Step S5does not have a uniform thickness, it is possible to prevent a short circuit between the buried p layer6and the cathode electrode7in a thin portion of the n+cathode layer4. That is, it is preferable that the surface layer of the rear surface of the n−semiconductor substrate after the ion implantation in Step S5have an impurity concentration distribution close to that of the n-type region.

Then, after the resist mask is removed, n-type impurity ions, such as phosphorus (P) ions, are implanted into the entire rear surface of the n−semiconductor substrate to form the n+cathode layer4at a position deeper than the buried p layer6(Step S5). Then, the impurities implanted in the ion implantation process of Steps S3to S5are collectively thermally diffused by a heat treatment using, for example, furnace annealing (Step S6). Since the impurities implanted in the ion implantation process of Steps S3to S5are collectively thermally diffused, it is possible to reduce the number of processes and to reduce costs. Whenever the ion implantation process of Steps S3to S5is performed, it is preferable to thermally diffuse the implanted impurities. In addition, the order of the ion implantation process of Steps S3to S5may be changed in various ways.

Then, the anode electrode (front surface electrode)3is formed on the front surface of the n−semiconductor substrate so as to be buried in the anode contact hole and is patterned in a predetermined shape (Step S7). Then, a passivation film (not illustrated) is formed on the front surface of the n−semiconductor substrate and is patterned in a predetermined shape (Step S8). Then, for example, electron beams are radiated to the n−semiconductor substrate to control the lifetime of the carriers in the n−drift region1(Step S9). Then, the cathode electrode7is formed on the rear surface of the n−semiconductor substrate (Step S10). In this way, the FWD illustrated inFIG. 1is completed.

Next, the operation of the semiconductor device according to the invention will be described.FIG. 4is a diagram illustrating the operation of a semiconductor device according to a comparative example when a forward voltage is applied.FIG. 5is a diagram illustrating the operation of the semiconductor device according to Embodiment 1 when the forward voltage is applied.FIG. 4illustrates an FWD (hereinafter, referred to as a comparative example) with a structure in which an end portion126aof a buried p layer126reaches a side surface121aof an n−semiconductor substrate.FIG. 5illustrates the FWD according to Embodiment 1 illustrated inFIG. 1. InFIG. 5, the edge termination structure portion11is shortened and the n buffer layer5is not illustrated, in order to clearly describe the operation of the carriers.

In the comparative example illustrated inFIG. 4, since the side surface121aof the n−semiconductor substrate is roughened due to unevenness which occurs during dicing, a leakage current is likely to flow from the side surface121aof the n−semiconductor substrate. Therefore, when the forward voltage is applied, holes which are injected from a p+anode layer122to an n−drift region121move to a cathode electrode127on the side surface121aof the n−semiconductor substrate through a buried p layer126-1(a path indicated by a dotted arrow) and do not reach an n+cathode layer124. That is, this is substantially the same as a state in which a short circuit occurs between the buried p layer126-1and the cathode electrode127in the side surface121aof the n−semiconductor substrate. Therefore, no electron is injected from the n+cathode layer124to the n−drift region121and the FWD is not turned on.

In addition, in the comparative example illustrated inFIG. 4, the following problems are likely to arise.FIG. 4(a)illustrates a first comparative example in which the rear surface of a chip is soldered to, for example, a direct copper bond (DCB) substrate. As illustrated inFIG. 4(a), in the first comparative example, a solder layer128on the rear surface of the chip protrudes from the side surface of the chip (the side surface121aof the n−semiconductor substrate) and the end portion126aof the buried p layer126-1is short-circuited to the cathode electrode127by the solder layer128(a portion represented by reference numeral120). As such, the state in which the solder layer128reaches the side surface121aof the n−semiconductor substrate (that is, the state in which the short circuit occurs between the cathode electrode127and the buried p layer126-1) indicates, for example, a state in which, when the n−semiconductor substrate is incorporated into a power module and is soldered to the DCB substrate, the solder layer128which is melted in the rear surface of the n−semiconductor substrate flows from the rear surface to the side surface121aof the n−semiconductor substrate and comes into contact with the side surface121a. The depth of a junction interface between the n+cathode layer124and the buried p layer126-1in the rear surface of the n−semiconductor substrate is about 1 μm to 3 μm from the rear surface of the n−semiconductor substrate. Therefore, when the solder layer128with a thickness of 300 μm or more protrudes from the side surface121aof the n−semiconductor substrate, a short circuit is likely to occur between the buried p layer126-1and the cathode electrode127in the side surface121aof the n−semiconductor substrate.

Therefore, no electron is injected from the cathode to the n−drift region121and a voltage drop in a short pass does not become a built-in voltage (0.7 V). As a result, the FWD according to the first comparative example is not turned on. Thereafter, when a given amount of current flows, the buried p layer126-1and the n+cathode layer124are biased forward by resistance R11in the short pass of the buried p layer126-1. Then, electrons are injected from the cathode to the n−drift region121and the voltage drop in the short pass is greater than the built-in voltage. As a result, latch-up occurs in a portion close to the active region and the FWD is turned on.

As such, the first comparative example has undesirable characteristics that, after the forward voltage is applied, there is a period for which the FWD does not operate (a jump in the I-V waveform) and the FWD starts to operate after the period has elapsed.FIG. 30illustrates an I-V waveform when a diode is biased forward.FIG. 30is a characteristic diagram illustrating the current-voltage waveform when the diode is biased forward. As represented by a thick solid line, in a general waveform (hereinafter, referred to as a normal waveform)21, a current increases with a forward voltage drop. However, when the latch-up is less likely to occur, a high forward voltage drop occurs and little current flows, as represented by a dotted line (a waveform represented by reference numeral22). Therefore, at the time when the voltage drop between the buried p layer and the n cathode layer is equal to or greater than the built-in voltage due to the passage of holes, a current flows at once and the forward voltage drop of the diode is reduced. A region which serves as negative resistance is snapback, that is, a jump22ain the I-V waveform.

As in a second comparative example illustrated inFIG. 4(b), as the impurity concentration of a buried p++layer126-2increases, the resistance R12of the short pass in the buried p++layer126-2decreases and a voltage (snapback voltage) which causes the snapback increases. Therefore, the jump in the I-V waveform increases. InFIG. 30, the magnitude of the impurity concentration of the buried p layer is represented by the direction of an arrow20. The jump22aincreases as the impurity concentration of the p layer increases (an I-V waveform22indicated by a dashed line). That is, among three I-V waveforms22in which the jump22aoccurs, the I-V waveform22with the smallest jump22awhich is represented by the thinnest dotted line corresponds to the first comparative example illustrated inFIG. 4(a)and the other I-V waveforms22correspond to the second comparative example illustrated inFIG. 4(b). InFIGS. 4(a) and 4(b), reference numeral122indicates a p+anode layer and reference numeral123indicates an anode electrode.

In contrast, as illustrated inFIG. 5, in the invention, the end portion6aof the buried p layer6does not reach the side surface1aof the n−semiconductor substrate and the buried p layer6is in a floating state. In addition, resistance R10between the end portion6aof the buried p layer6and the side surface1aof the n−semiconductor substrate is determined by the impurity concentration of the n−drift region1with high resistance and is more than the resistance R11and the resistance R12of the first and second comparative examples which are determined by the impurity concentration of the buried p layers126-1and126-2. Therefore, the holes which are injected from the p+anode layer2to the buried p layer6through the n−drift region1when the forward voltage is applied is less likely to move from the end portion6aof the buried p layer6to the cathode electrode7on the side surface1aof the n−semiconductor substrate (a portion represented by reference numeral12) and moves to the n+cathode layer4. Then, electrons are injected from the n+cathode layer4to the n−drift region1. Therefore, in the semiconductor device according to the invention, a jump in the I-V waveform does not occur. As a result, the semiconductor device according to the invention has the normal waveform21illustrated inFIG. 30and operates substantially similarly to the general FWD without the buried p layer6. Reference numeral28indicates a solder layer when the rear surface of the chip is soldered to, for example, the DCB substrate.

As described above, according to Embodiment 1, since the buried p layer is uniformly provided, a uniform voltage drop (avalanche breakdown) can occur in the rear surface of the substrate during reverse recovery and it is possible to prevent a jump in the I-V waveform. Therefore, it is possible to perform soft recovery and to avoid problems due to EMI noise. In addition, according to Embodiment 1, since the buried p layer is uniformly provided, alignment accuracy in the rear surface of the substrate does not need to be higher than that in the structure according to the related art in which a plurality of buried p layers are provided at predetermined intervals. Therefore, it is possible to form the buried p layer with high dimensional accuracy with a small number of processes. In addition, special equipment for improving alignment accuracy is not needed. Therefore, it is possible to provide a semiconductor device at low costs.

According to Embodiment 1, since the end portion of the buried p layer is located inside the end portion of the anode contact, the breakdown voltage of the active region is less than the breakdown voltage of an inactive region. Therefore, it is possible to prevent the concentration of the electric field on the end portion of the active region during reverse recovery. The reason is as follows. When a high voltage is applied to the FWD during reverse recovery, the pn junction (hereinafter, referred to as a pn junction J1) between the buried p layer and the n cathode layer on the rear surface of the substrate is reversely biased. The impurity concentration of the two layers is higher than the impurity concentration of the semiconductor substrate by two digits or more. Therefore, even when a voltage of 100 V or less is applied to the pn junction J1, avalanche breakdown is easy to occur. When the pn junction J1causes the avalanche breakdown, holes are injected from the pn junction J1in which the buried p layer is formed. The holes drift to the p+anode layer in the depletion layer. Then, electric field intensity is increased by the holes even in the vicinity of a pn junction (hereinafter, referred to as a pn junction J2) between the p+anode layer and the n drift layer. That is, the gradient of electric field intensity increases in the vicinity of the pn junction J2due to an excessive increase in positive charge caused by the holes according to the Poisson's equation. That is, the effective impurity concentration of the semiconductor substrate increases. When the gradient of the electric field intensity increases, the maximum electric field intensity of the pn junction J2significantly increases and reaches critical electric field intensity. As a result, avalanche breakdown occurs. In other words, a dynamic breakdown voltage is reduced in the active region. Since the increase in the maximum electric field intensity of the pn junction J2occurs only in the active region in which the buried p layer is formed, the dynamic breakdown voltage is not reduced in the inactive region. This is the reason why the dynamic breakdown voltage is reduced in the active region and the inactive region. Since the dynamic breakdown voltage is reduced only in the region in which the buried p layer is formed, a reverse recovery current does not flow to the end portion of the p+anode layer when the buried p layer is formed inside the p+anode layer in the chip. Therefore, the concentration of a current on the end portion of the p+anode layer is prevented and it is possible to prevent element breakdown due to the maximum voltage applied to during reverse recovery or a current change rate di/dt.

Next, a semiconductor device manufacturing method according to Embodiment 2 will be described.FIG. 6is a flowchart illustrating the outline of the semiconductor device manufacturing method according to Embodiment 2. The semiconductor device manufacturing method according to Embodiment 2 differs from the semiconductor device manufacturing method according to Embodiment 1 in that, after electron beams are radiated to control the lifetime, an n+cathode layer4is formed and laser annealing is performed to activate the n+cathode layer4.

Specifically, first, similarly to Embodiment 1, a process from the formation of a front surface element structure to the formation of a buried p layer6is performed (Steps S11to S14). Then, after a resist mask used to form the buried p layer6is removed, impurities which are implanted by an ion implantation process for forming an n buffer layer5and an ion implantation process for forming the buried p layer6are thermally diffused by a heat treatment using, for example, furnace annealing (Step S15). Then, similarly to Embodiment 1, a process from the formation of an anode electrode3to the control of the lifetime is performed (Steps S16to S18). Then, the n+cathode layer4is formed on the entire rear surface of the n−semiconductor substrate (Step S19). A method for forming the n+cathode layer4is the same as that in Embodiment 1. Then, laser annealing is performed on the rear surface of the n−semiconductor substrate to activate the n+cathode layer4(Step S20). Then, a cathode electrode7is formed on the rear surface of the n−semiconductor substrate (Step S21). In this way, the FWD illustrated inFIG. 1is completed.

As described above, according to Embodiment 2, it is possible to obtain the same effect as that in Embodiment 1.

Next, a semiconductor device manufacturing method according to Embodiment 3 will be described.FIG. 7is a flowchart illustrating the outline of the semiconductor device manufacturing method according to Embodiment 3. The semiconductor device manufacturing method according to Embodiment 3 differs from the semiconductor device manufacturing method according to Embodiment 2 in that an anode electrode3is formed on the front surface of an n−semiconductor substrate before the rear surface of the n−semiconductor substrate is ground to reduce the thickness of the n−semiconductor substrate.

Specifically, first, a front surface element structure is formed on the front surface of the n−semiconductor substrate which will be an n−drift region1(Step S31) and the anode electrode3is formed (Step S32). A method for forming the front surface element structure and a method for forming the anode electrode3are the same as those in Embodiment 1. Then, similarly to Embodiment 2, a process from the grinding of the rear surface of the n−semiconductor substrate to a heat treatment is performed (Steps S33to S36). Then, similarly to Embodiment 2, a process from the formation of a passivation film to the formation of a cathode electrode7is performed (Steps S37to S41). In this way, the FWD illustrated inFIG. 1is completed.

As described above, according to Embodiment 3, it is possible to obtain the same effect as that in Embodiments 1 and 2.

Next, the structure of a semiconductor device according to Embodiment 4 will be described.FIG. 8is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 4.FIG. 9is a characteristic diagram illustrating an impurity concentration distribution along a cutting line B-B′ ofFIG. 8. The semiconductor device according to Embodiment 4 differs from the semiconductor device according to Embodiment 1 in that a plurality of n buffer layer15are formed at different depths from the rear surface of a substrate by multi-stage irradiation with protons from the rear surface of the substrate. For example, when the n buffer layers15are formed by three-stage irradiation with protons, an n buffer layer15ais arranged at the deepest position from the rear surface of an n−semiconductor substrate which will be an n−drift region1.

In addition, an n buffer layer15bis arranged at a position that is shallower than the n buffer layer15afrom the rear surface of the n−semiconductor substrate so as to be separated from the n buffer layer15a. Then, an n buffer layer15cis arranged at a position that is shallower than the n buffer layer15bfrom the rear surface of the n−semiconductor substrate so as to be separated from the n buffer layer15b. That is, the n−drift region1is arranged between the n buffer layers15ato15c. The n buffer layer15cis arranged at a position that is deeper than the n+cathode layer4and a buried p layer6is provided between the n buffer layer15cand an n+cathode layer4in an active region10. The n buffer layer15cmay come into contact with the buried p layer6or it may be separated from the buried p layer6.

Next, a method for manufacturing the semiconductor device according to Embodiment 4 will be described.FIG. 10is a flowchart illustrating the outline of the semiconductor device manufacturing method according to Embodiment 4. First, a front surface element structure is formed on the front surface side of the n−semiconductor substrate which will be the n−drift region1(Step S51) and the anode electrode3is formed (Step S52). A method for forming the front surface element structure and a method for manufacturing the anode electrode3are the same as those in Embodiment 1. Then, the rear surface of the n−semiconductor substrate is ground to reduce the thickness of the n−semiconductor substrate (Step S53).

Then, for example, three proton irradiation processes are performed in different ranges from the rear surface of the n−semiconductor substrate to form the n buffer layers15ato15cat different depths from the rear surface of the substrate (Step S54). Then, n-type impurity ions, such as phosphorus ions, are implanted into the entire rear surface of the n−semiconductor substrate to form the n+cathode layer4(Step S55). Then, the buried p layer6is formed at the position that is deeper than the n+cathode layer4and is shallower than the n buffer layer15cfrom the rear surface of the substrate (Step S56). A method for forming the n+cathode layer4and a method for forming the buried p layer6are the same as those in Embodiment 1.

Then, a heat treatment is performed to collectively activate and thermally diffuse the protons and the impurities which are implanted in Steps S54to S56(Step S57). Then, a passivation film is formed on the front surface of the n−semiconductor substrate (Step S58) and the lifetime of the carriers in the n−drift region1is controlled (Step S59). A method for forming the passivation film and a method for controlling the lifetime are the same as those in Embodiment 1. Then, laser annealing is performed on the rear surface of the n−semiconductor substrate to activate the n+cathode layer4(Step S60). Then, a cathode electrode7is formed on the rear surface of the n−semiconductor substrate (Step S61). In this way, the FWD illustrated inFIG. 8is completed.

As described above, according to Embodiment 4, it is possible to obtain the same effect as that in Embodiments 1 to 3.

Next, the structure of a semiconductor device according to Embodiment 5 will be described.FIG. 11is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 5. An impurity concentration distribution along a cutting line A-A′ ofFIG. 11is the same as the impurity concentration distribution illustrated inFIG. 2. The semiconductor device according to Embodiment 5 differs from the semiconductor device according to Embodiment 1 is that an end portion14aof an n+cathode layer14is located inside a side surface1aof an n−semiconductor substrate (on the side close to the center of an FWD cell). That is, in Embodiment 5, the n+cathode layer14is not provided on the rear surface side of the substrate in an edge termination structure portion11and a Schottky junction between a cathode electrode7and an n buffer layer5is formed on the rear surface side of the substrate.

An end portion6aof a buried p layer6is preferably provided at a position that is a second length t2inside from the end portion14aof the n+cathode layer14. In this case, it is possible to prevent the buried p layer6from coming into contact with the cathode electrode7on the rear surface of the substrate due to an alignment error. Preferably, the second length t2has allowance for alignment accuracy (for example, allowance that is about two times the alignment accuracy). For example, the second length t2is preferably equal to or greater than about 1 μm and equal to or less than about 10 μm. Specifically, the second length t2from the end portion6aof the buried p layer6to the end portion14aof the n+cathode layer14is preferably, for example, equal to or greater than about 1 μm and equal to or less than about 10 μm.

In a method for manufacturing the semiconductor device according to Embodiment 5, a resist mask in which a region for forming the n+cathode layer14is opened may be formed on the rear surface of the n−semiconductor substrate and the n+cathode layer14may be formed in an active region10, using the resist mask as a mask in Step S5which is the same as that in the semiconductor device manufacturing method according to Embodiment 1. The semiconductor device manufacturing method according to Embodiment 5 is the same as the semiconductor device manufacturing method according to Embodiment 1 except for the step of forming the n+cathode layer14.

As described above, according to Embodiment 5, it is possible to obtain the same effect as that in Embodiments 1 to 4. In addition, according to Embodiment 5, the n+cathode layer is not provided in the edge termination structure portion and the Schottky junction between the n+cathode layer and the cathode electrode is formed in the edge termination structure portion. Therefore, when the forward voltage is applied, the injection of the carriers (electrons) from the cathode in the edge termination structure portion is further suppressed. Therefore, it is possible to prevent the carriers from being stored in the edge termination structure portion and thus to prevent the concentration of a current on the end portion of the anode contact during reverse recovery. As a result, it is possible to improve the breakdown voltage during reverse recovery.

Next, the structure of a semiconductor device according to Embodiment 6 will be described.FIG. 12is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 6.FIG. 13is a characteristic diagram illustrating an impurity concentration distribution along the cutting line C-C′ ofFIG. 12. The impurity concentration distribution along the cutting line A-A′ ofFIG. 12is the same as the impurity concentration distribution illustrated inFIG. 2. The semiconductor device according to Embodiment 6 differs from the semiconductor device according to Embodiment 5 in that a p−region (sixth semiconductor region)16is provided in an n buffer layer5in an edge termination structure portion11so as to come into contact with a cathode electrode7, thereby forming a Schottky junction between the p−region16and the cathode electrode7. An outer circumferential end portion16aof the p−region16extends to a side surface1aof an n−semiconductor substrate. The impurity concentration of the p−region16may be equal to the impurity concentration of a buried p layer6.

A distance between an end portion6aof the buried p layer6and the inner circumferential end portion16bof the p−region16is a third length t3. According to this structure, since a potential difference occurs between the buried p layer6and the p−region16, it is possible to prevent a jump in the I-V waveform, similarly to Embodiment 1. Specifically, the third length t3between the end portion6aof the buried p layer6and the inner circumferential end portion16bof the p−region16is preferably equal to or greater than the width Xn of a built-in depletion layer at the pn junction between the n buffer layer5and the buried p layer6, and equal to or less than the diffusion length Lhof the minority carrier. The reason why the third length t3is set to be equal to or less than the diffusion length Lhof the minority carrier is to prevent a reduction in the effect obtained by the formation of the p−region16.

The reason why the third length t3is set to be equal to or greater than the width Xn of the built-in depletion layer at the pn junction between the n buffer layer5and the buried p layer6is as follows. In a thermal equilibrium state in which the forward voltage is not applied, the depletion layer (built-in depletion layer) is formed at the pn junction between the n buffer layer5and the buried p layer6in the n buffer layer5. When the built-in depletion layer comes into contact with the p−region16in the thermal equilibrium state, the depletion layer which is spread from the pn junction between the n buffer layer5and the buried p layer6reaches the p−region16due to the holes which are injected from the anode by the application of the forward voltage and a jump in the I-V waveform occurs.

The width Xn of the built-in depletion layer at the pn junction between the n buffer layer5and the buried p layer6is represented by the following Expression (3). A built-in voltage Φbof the pn junction between the n buffer layer5and the buried p layer6is represented by the following Expression (4). In the following Expressions (3) and (4), the donor concentration of the n buffer layer5is ND, the acceptor concentration of the buried p layer6is NA, an elementary charge is q, a Boltzmann constant is K, an absolute temperature is T, intrinsic carrier concentration when the absolute temperature T is 300 K is ni, vacuum permittivity is ε0, and the specific permittivity of silicon is εs. In addition, KT/q indicates a thermal voltage when the absolute temperature T is 300 K.

Specifically, the donor concentration NDof the n buffer layer5is 1.00×1021/cm3, the acceptor concentration NAof the buried p layer6is 1.00×1023/cm3, the intrinsic carrier concentration niis 1.50×1016/cm3, KT/q is 2.60×102eV, the vacuum permittivity ε0is 8.85×10−12F/cm, the specific permittivity εsof silicon is 1.17×10 F/cm, and the elementary charge q is 1.60×1019C. Therefore, from the above-mentioned Expression (4), the built-in voltage Φbof the pn junction between the n buffer layer5and the buried p layer6is 6.87×10−1V. In addition, from the above-mentioned Expression (3), the width Xn of the built-in depletion layer at the pn junction between the n buffer layer5and the buried p layer6is 0.945 μm.

Next, an example of a method for manufacturing the semiconductor device according to Embodiment 6 will be described. In the semiconductor device manufacturing method according to Embodiment 6, after the buried p layer6is formed (Step S4), a resist mask in which a region for forming the n+cathode layer14is opened is formed on the rear surface of the n−semiconductor substrate and the n+cathode layer14is formed in the active region10using the resist mask as a mask in Step S5, unlike the semiconductor device manufacturing method according to Embodiment 1. In addition, after the resist mask for forming the n+cathode layer14is removed and before a heat treatment in Step S6, a resist mask in which a region for forming the p−region16is opened is formed and the p−region16is formed in the edge termination structure portion11using the resist mask as a mask. Then, in Step S6, the heat treatment is preferably performed to collectively activate the impurities implanted by an ion implantation process. The semiconductor device manufacturing method according to Embodiment 6 is the same as the semiconductor device manufacturing method according to Embodiment 1 except for the steps of forming the n+cathode layer14and the p−region16.

As described above, according to Embodiment 6, it is possible to obtain the same effect as that in Embodiments 1 to 5. In addition, according to Embodiment 6, the n+cathode layer is not provided in the edge termination structure portion and the junction between the p−region and the cathode electrode is formed in the edge termination structure portion. Therefore, it is possible to obtain the same effect as that in Embodiment 5.

Next, the structure of a semiconductor device according to Embodiment 7 will be described.FIG. 14is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 7.FIGS. 15 to 17are plan views illustrating examples of the plane pattern of a buried p layer in a semiconductor device according to Embodiment 7. InFIGS. 15 to 17, the position of an end portion3aof an anode contact which is projected from the front surface of a substrate to an n+cathode layer4on the rear surface of the substrate is represented by a dotted line (which holds forFIGS. 21 and 22). The semiconductor device according to Embodiment 7 differs from the semiconductor device according to Embodiment 1 in that a buried p layer26is selectively provided and the area ratio (=A11/A10) of the occupation area A11of the surface area of the buried p layer26to the surface area A10of a portion (e.g., the active region10) which is disposed inside the end portion3aof the anode contact is set in a predetermined range.

The area ratio of the occupation area A11of the surface area of the buried p layer26to the surface area A10of the portion which is disposed inside the end portion3aof the anode contact may be equal to or greater than 90% and equal to or less than 98% and preferably equal to or greater than 92% and equal to or less than 96%. In this case, it is possible to obtain a low transient VF(on-voltage) and soft recovery characteristics. The surface area A10of the portion which is disposed inside the end portion3aof the anode contact means the surface area of the active region10. The occupation area A11of the surface area of the buried p layer26means the total surface area of the buried p layer26. An end portion26aof the pattern of the buried p layer26which is closest to the edge termination structure portion11is preferably located at a position that is a first length t1inside from the end portion3aof the anode contact (toward the center of the FWD cell), similarly to Embodiment 1. The first length t1is preferably, for example, about 50 μm corresponding to the diffusion length Lhof the minority carrier.

The plane pattern of the buried p layer26can vary depending on the design condition. For example, the plane pattern of the buried p layer26has a stripe shape, a matrix shape in which substantial rectangles or substantial dots are regularly arranged at predetermined intervals (that is, a shape in which the buried p layer26is opened in a lattice shape:FIG. 15), a shape in which substantially rectangular openings or substantially circular openings are regularly arranged in a matrix at predetermined intervals in the buried p layer26(FIG. 16), and a mosaic shape in which openings with an arbitrary shape are arranged in an arbitrary pattern. For example, the plane pattern of the buried p layer26may be the same plane pattern as that in Embodiment 1. That is, one buried p layer26with a substantially rectangular shape may be uniformly formed on the entire central portion of the active region10and a region in which the buried p layer26is not provided may be provided in a substantially rectangular frame shape around the buried p layer26in the active region10. In this case, the width of the region, in which the buried p layer26is not provided, around the buried p layer26is preferably equal to the first length t1which can obtain the above-mentioned area ratio.

When a forward bias is applied, the buried p layer26which is uniformly formed hinders the injection of electrons from the n+cathode layer4to the n−drift region1and conductivity modulation is less likely to occur. As a result, there is a concern that a transient forward voltage will increase. The transient forward voltage is as follows.FIG. 18is a characteristic diagram illustrating the voltage waveform of the FWD. As illustrated inFIG. 18, when the voltage changes from the reverse bias (for example, a power supply voltage of 600 V or more) to the forward bias during current blocking and the semiconductor device is turned on, the drop of a forward voltage VF(a voltage VAKbetween the anode and the cathode) increases temporarily while the carriers are stored in the n−drift region1(for example, about a few tens of volts). Then, when the storage of the carriers is completed, the semiconductor device is in a steady state and the forward voltage VFis converged on a steady-state value (for example, about 1 V to 3 V). The forward voltage VFwhich transiently increases while the voltage changes from the reverse bias to the forward bias and the semiconductor is turned on is referred to as the transient forward voltage (hereinafter, referred to as a transient VF).

When the transient VFis high, electrical loss occurs during the actual operation of a machine, such as an inverter, and an element temperature increases due to the electrical loss. Therefore, it is preferable that the transient VFbe low. For this reason, when the buried p layer26is formed, a portion of the buried p layer26is removed to form an opening portion (hole). In this way, when the forward bias is applied, electrons are injected from the n+cathode layer4to the n−drift region1through the opening portion, without being blocked by the buried p layer26. That is, the opening portion of the buried p layer26serves as the path of the electrons injected from the n+cathode layer4to the n−drift region1. The planar shape of the opening portion in the buried p layer26may be, for example, a lattice shape with a width t4in which substantial rectangles with a fourth length (width) L1remain in a matrix as illustrated inFIG. 15or a shape in which circles with a diameter t5are regularly arranged in a matrix at an interval of the fourth length L1as illustrated inFIG. 16.

As illustrated inFIG. 17, when one buried p layer26having a substantially rectangular shape with the fourth length (width) L1is uniformly formed on the entire surface of the central portion of the active region10, the opening portion of the buried p layer26may have a substantially rectangular frame shape which surrounds the buried p layer26. That is, this is equivalent to a structure in which the opening portion which serves as the path of the electrons injected from the n+cathode layer4to the n−drift region1is not formed in the buried p layer26, but is formed around the buried p layer26. In this case, the width (that is, the first length t1) of the opening portion of the buried p layer26may be greater than the diffusion length Lhof the minority carrier or 50 μm. When the opening portion is formed in the buried p layer26in this way, the occupation area (=A10-A11) of the surface area of the region, which does not hinder the injection of electrons from the n+cathode layer4to the n−drift region1, in the surface area A10of the portion which is disposed inside the end portion3aof the anode contact is ensured in a predetermined range.

When the forward bias is applied, the holes which are injected from the p+anode layer2to the n−drift region1cause a voltage drop in the buried p layer26, move in the buried p layer26, and reaches the n+cathode layer4through the opening portion of the buried p layer26. When the voltage drop is greater than the built-in potential of the pn junction between the buried p layer26and the n+cathode layer4, electrons are injected from the n+cathode layer4to the buried p layer26. In this case, when the length (fourth length L1) of the buried p layer26in a direction horizontal to the rear surface of the substrate is not sufficiently large, the movement distance of the holes which are injected from the p+anode layer2to the n−drift region1in the direction horizontal to the rear surface of the substrate is short and a voltage drop is reduced. Therefore, electrons are less likely to be injected from the n+cathode layer4to the buried p layer26. This causes an increase in the transient VFor a jump in the I-V waveform.

When the opening portion which serves the path of the electrons injected from the n+cathode layer4to the n−drift region1is provided around the buried p layer26as illustrated inFIG. 17, the sufficient length of the buried p layer26in the direction horizontal to the rear surface of the substrate is maintained. Therefore, when the opening portion which serves the path of the electrons injected from the n+cathode layer4to the n−drift region1is provided around the buried p layer26as illustrated inFIG. 17, it is easy to prevent an increase in the transient VFor a jump in the I-V waveform, as compared to the structure in which the opening portion is selectively provided in the buried p layer26. In addition, in the case in which the opening portion which serves the path of the electrons injected from the n+cathode layer4to the n−drift region1is provided around the buried p layer26as illustrated inFIG. 17, when the ratio of the total surface area of the buried p layer26to the surface area A10of the portion which is disposed inside the end portion3aof the anode contact is equal to or greater than 50%, the soft recovery effect is sufficiently obtained during reverse recovery. In this case, the distance (that is, the first length t1) between the projected position of the end portion3aof the anode contact on the rear surface of the substrate and the end portion26aof the buried p layer26is preferably set to a value at which the area ratio of the occupation area A11of the surface area of the buried p layer26is equal to or greater than 50%. For example, the distance is preferably equal to or less than 2000 μm.

InFIGS. 15 to 17, the length (fourth length) L1of the buried p layer26in the direction horizontal to the rear surface of the substrate depends on the impurity concentration of the buried p layer26and can be calculated, for example, as follows. When current density is J, an elementary charge is q, hole mobility is μ, the thickness of the buried p layer26is d, the impurity concentration of the buried p layer26is Np, and the built-in potential of the pn junction between the buried p layer26and the n+cathode layer4is Vbi, the length L1of the buried p layer26in the direction horizontal to the rear surface of the substrate satisfies the following Expression (5).
L1={(q·μ·d·Np·Vbi)/J}1/2[Expression (5)]

For example, assuming that hole mobility at room temperature (300K) is (cm2/Vs), the thickness of the cathode p layer is 1 μm, the p-type impurity concentration of the cathode p layer is 1×1017/cm3, and the current density J at which sufficient conductivity modulation occurs is 1 A/cm2, the length L1of the buried p layer26in the direction horizontal to the rear surface of the substrate is about 250 μm from the above-mentioned Expression (5). When the length L1of the buried p layer26in the direction horizontal to the rear surface of the substrate is equal to or greater than 250 μm, it is possible to reduce the transient VF. Therefore, the length L1of the buried p layer26in the direction horizontal to the rear surface of the substrate may satisfy the following Expression (6).
L1≧{(q·μ·d·Np·Vbi)/J}1/2[Expression (6)]

Next, a method for manufacturing the semiconductor device according to Embodiment 7 will be described. The semiconductor device manufacturing method according to Embodiment 7 differs from the semiconductor device manufacturing method according to Embodiment 1 in that, when the buried p layer26is formed, a mask in which the plane pattern of the buried p layer26is formed is used as an ion implantation mask. Specifically, first, a process from the formation of the front surface element structure to the formation of an n buffer layer5is performed, similarly to Steps S1to S3in Embodiment 1. Then, the n+cathode layer4is formed on the rear surface of an n−semiconductor substrate. A method for forming the n+cathode layer4is the same as that in Embodiment 1.

Then, a resist mask in which a region for forming the buried p layer26is opened is formed on the rear surface of the n−semiconductor substrate by photolithography. The resist mask covers, for example, the edge termination structure portion11and a portion of the active region10that is the first length t1inside from the end portion of the anode contact hole. In addition, the pattern of the buried p layer26is formed in a portion of the resist mask which is disposed inside the end portion of the anode contact hole. Then, p-type impurity ions, such as boron ions, are implanted into the rear surface of the n−semiconductor substrate, using the resist mask as a mask, to form the buried p layer26.

The order in which the n+cathode layer4, the n buffer layer5, and the buried p layer26are formed can be changed in various ways. Similarly to Embodiment 1, the n buffer layer5, the buried p layer26, and the n+cathode layer4may be formed in this order. Then, similarly to Step S6in Embodiment 1, thermal diffusion is collectively performed on the impurities which are implanted by the ion implantation process. Instead of the collective heat treatment, whenever impurities are implanted by the ion implantation process, thermal diffusion may be performed on the implanted impurities. Then, a process from the formation of an anode electrode3to the formation of a cathode electrode7is performed similarly to Steps S7to S10in Embodiment 1. In this way, the FWD illustrated inFIG. 14is completed.

As described above, according to Embodiment 7, it is possible to obtain the same effect as that in Embodiments 1 to 6. In addition, according to Embodiment 7, the buried p layer26is provided inside the end portion3aof the anode contact at a predetermined area ratio and the area ratio of the buried p layer is optimized. Therefore, it is possible to provide a semiconductor device which has soft recovery characteristics and a low transient VF. In the structure disclosed in Patent Document 1, since the conductivity modulation of the pnpn structure portion is delayed, a high transient on-voltage is generated when the FWD is turned on. As a result, the switching loss of the FWD increases and the surge voltage increases when the IGBT of the opposite arm is turned off. In contrast, according to the invention, it is possible to obtain soft recovery and a low transient VF. Therefore, the problems of the structure disclosed in Patent Document 1 do not occur.

Next, the structure of a semiconductor device according to Embodiment 8 will be described.FIG. 19is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 8. The semiconductor device according to Embodiment 8 differs from the semiconductor device according to Embodiment 7 in that a plurality of n buffer layers15which have different depths from the rear surface of a substrate are formed by multi-stage irradiation with protons from the rear surface of the substrate. An n buffer layer15has the same structure as that in Embodiment 4. That is, for example, when the n buffer layer15is formed by three-stage irradiation with protons, the n buffer layer15includes n buffer layers15ato15cin ascending order of depth from the rear surface of an n−semiconductor substrate.

A method for manufacturing the semiconductor device according to Embodiment 8 differs from the semiconductor device manufacturing method according to Embodiment 4 in that, when a buried p layer26is formed, an ion implantation mask in which the plane pattern of the buried p layer26is formed in a portion that is disposed inside an end portion of an anode contact hole is used, similarly to Embodiment 7. The semiconductor device manufacturing method according to Embodiment 8 is the same as the semiconductor device manufacturing method according to Embodiment 4 except for a step of forming the buried p layer26.

As described above, according to Embodiment 8, it is possible to obtain the same effect as that in Embodiments 1 to 7.

Next, the structure of a semiconductor device according to Embodiment 9 will be described.FIG. 20is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 9.FIG. 21is a plan view illustrating an example of the plane pattern of a buried p layer illustrated inFIG. 20.FIG. 21illustrates an example in which buried p layer (hereinafter, referred to as first and second buried p layers)26and36are regularly arranged in a matrix at predetermined intervals. The semiconductor device according to Embodiment 9 differs from the semiconductor device according to Embodiment 7 in that the second buried p layer36is selectively provided in an edge termination structure portion11and the area ratio (=A21/A20) of the occupation area A21of the surface area of the second buried p layer36in the edge termination structure portion11to the surface area A20of a portion which is disposed outside an end portion3aof an anode contact is set in a predetermined range.

Specifically, the area ratio of the occupation area A21of the surface area of the second buried p layer36in the edge termination structure portion11to the surface area A20of the portion which is disposed outside the end portion3aof the anode contact is less than the area ratio of the occupation area A11of the surface area of the first buried p layer26to the surface area A10of a portion which is disposed inside the end portion3aof the anode contact. Therefore, when dynamic avalanche occurs, the breakdown voltage of the edge termination structure portion11is greater than the breakdown voltage of an active region10. As a result, the breakdown voltage of the active region10is a standard in an avalanche during reverse recovery. Therefore, it is possible to avoid the concentration of a current on the end portion3aof the anode contact during reverse recovery and to improve the breakdown voltage.

Specifically, the second buried p layer36is arranged in the range from the vicinity of the boundary between the end portion3a(active region10) of the rectangular anode contact and the edge termination structure portion11to the edge termination structure portion11so as to be laid across the end portion3aof the anode contact. The width t6of an opening portion in the second buried p layer36is greater than that in the first buried p layer26which is disposed inside the end portion3aand the anode contact and the length L2of the second buried p layer36in a direction horizontal or parallel to the rear surface of the substrate is less than that in the first buried p layer26(t6>t4and L2<L1). For example, the first buried p layer26has the same structure as that in Embodiment 7. As such, since the second buried p layer36is provided in the edge termination structure portion11, it is possible to further reduce the transient VFand to further improve soft recovery characteristics.

As described above, according to Embodiment 9, it is possible to obtain the same effect as that in Embodiments 1 to 8.

Next, the structure of a semiconductor device according to Embodiment 10 will be described.FIG. 22is a plan view illustrating the structure of the semiconductor device according to Embodiment 10.FIG. 22illustrates an example of the plane pattern of a buried p layer. The semiconductor device according to Embodiment 10 differs from the semiconductor device according to Embodiment 1 in that second buried p layers46are provided at four corners of an end portion3aof a rectangular anode contact so as to be laid across the vicinity of the boundary between the end portion3aof the anode contact and an edge termination structure portion11. The second buried p layer46comes into contact with a buried p layer (hereinafter, referred to as a first buried p layer)6which is disposed inside the end portion3aof the anode contact.

In Embodiment 10, when dynamic avalanche occurs, the breakdown voltage of the edge termination structure portion11is reduced at the corners of the end portion3aof the anode contact. However, when the forward bias is applied, conductivity modulation is less likely to occur at the corners of the end portion3aof the anode contact. The holes which are injected from a p+anode layer2to an n−drift region1when dynamic avalanche occurs flows to a contact surface of an anode electrode3which is surrounded by the end portion3aof the anode contact according to electrostatic potential. The number of carriers stored in the edge termination structure portion11is reduced at the corners of the end portion3aof the anode contact. Therefore, when the forward bias is applied, the concentration of a current on the corners of the end portion3aof the anode contact is reduced. As a result, during reverse recovery, the concentration of a current on the corners of the end portion3aof the anode contact is also reduced.

As described above, according to Embodiment 10, it is possible to obtain the same effect as that in Embodiments 1 to 9.

Next, the relationship among a transient VF(on-voltage), a surge voltage during reverse recovery, and the area ratio of a buried p layer was verified.FIG. 23is a characteristic diagram illustrating the relationship among a transient forward voltage, a surge voltage during reverse recovery, and the area ratio of a buried p layer in a semiconductor device according to Example 1. An FWD (hereinafter, referred to as Example 1) in which the area ratio of a buried p layer was changed to various values was manufactured by the semiconductor device manufacturing method according to Embodiment 7 and the transient VF(on-voltage) and the surge voltage during the reverse recovery were measured.FIG. 23illustrates the measurement results. In Example 1, a breakdown voltage was 1200 V, a rated current was 100 A, a power supply voltage Vcc was 900 V, a junction (pn junction) temperature Tj was the room temperature (for example, 25° C.)

When the occupation area A11of the surface area of the buried p layer26is high, it is easy to achieve soft recovery, but the transient on-voltage (transient forward voltage) increases. On the other hand, when the occupation area A11of the surface area of the buried p layer26is low, the transient on-voltage is reduced, but it is difficult to achieve soft recovery. The results illustrated inFIG. 23proved that, when the area ratio of the occupation area A11of the surface area of the buried p layer26to the surface area A10of the portion which was disposed inside the end portion3aof the anode contact was equal to or greater than 90% and equal to or less than 98% and preferably equal to or greater than 92% and equal to or less than 96%, it was possible to reduce the transient VFand to achieve soft recovery.

When the transient VFis equal to or less than 100 V and the surge voltage is equal to or less than 1170 V, it is possible to achieve a low transient VFand soft recovery. The reason why the transient VFis set to 100 V or less is that, when the transient VFis greater than 100 V, electrical loss increases during the operation of an inverter. The reason why the surge voltage is set to 1170 V or less is to reduce damage due to an electrical load which is applied to a diode by the surge voltage.

Next, a semiconductor device manufacturing method according to Embodiment 11 will be described.FIG. 24is a flowchart illustrating the outline of the semiconductor device manufacturing method according to Embodiment 11. The semiconductor device manufacturing method according to Embodiment 11 differs from the semiconductor device manufacturing method according to Embodiment 4 in that, after a front surface protective film is formed, each process (hereinafter, referred to as a rear surface forming process) is performed on the rear surface of a substrate.

Specifically, first, a front surface element structure and an anode electrode3are formed on the front surface side of an n−semiconductor substrate which will be an n−drift region1(Steps S71and72) and a passivation film is formed on the front surface side of the n−semiconductor substrate (Step S73). A method for forming the front surface element structure, a method for forming the anode electrode3, and a method for forming the passivation film are the same as those in Embodiment 1. Then, the rear surface of the n−semiconductor substrate is ground to reduce the thickness of the n−semiconductor substrate (Step S74). Then, similarly to Embodiment 4, for example, three proton irradiation processes are performed in different ranges from the rear surface of the n−semiconductor substrate to form n buffer layers15ato15cat different depths from the rear surface of the substrate (Step S75). Then, for example, furnace annealing is performed to activate the protons injected into the n−semiconductor substrate (Step S76). Then, n-type impurity ions, such as phosphorus ions, are implanted into the entire rear surface of the n−semiconductor substrate to form an n+cathode layer4(Step S77).

Then, a resist mask in which a region for forming a buried p layer6is opened is formed on the rear surface of the n−semiconductor substrate. Then, the buried p layer6is formed at a position that is deeper than the n+cathode layer4and is shallower than the n buffer layer15cfrom the rear surface of the substrate, using the resist mask as a mask (Step S78). Then, after the resist mask is removed, laser annealing is performed on the rear surface of the n−semiconductor substrate to activate the n+cathode layer4(Step S79). Then, an irradiation process and an annealing process which control the lifetime of carriers in the n−drift region1are performed (Steps S80and S81). A lifetime control method in Steps S80and S81is the same as that in Embodiment 1. Then, a cathode electrode7is formed on the rear surface of the n−semiconductor substrate (Step S82). In this way, the FWD illustrated inFIG. 8is completed.

As described above, according to Embodiment 11, it is possible to obtain the same effect as that in Embodiments 1 to 4.

Next, a semiconductor device manufacturing method according to Embodiment 12 will be described.FIG. 25is a flowchart illustrating the outline of the semiconductor device manufacturing method according to Embodiment 12. The semiconductor device manufacturing method according to Embodiment 12 differs from the semiconductor device manufacturing method according to Embodiment 11 in that, after laser annealing for activating an n+cathode layer4and a buried p layer6is performed, furnace annealing is performed to activate n buffer layers15ato15c.

Specifically, first, similarly to Embodiment 11, a process from the formation of a front surface element structure to the formation of the n buffer layers15ato15cis performed (Step S91to S95). Then, similarly to Embodiment 11, a process from the formation of an n+cathode layer4to laser annealing for activating the n+cathode layer4and the buried p layer6is performed (Steps S96to S98). Then, furnace annealing is performed to activate the n buffer layers15ato15c(Step S99). Then, similarly to Embodiment 11, a process from the control of the lifetime to the formation of a cathode electrode7is performed (Steps S100to S102). In this way, the FWD illustrated inFIG. 8is completed.

As described above, according to Embodiment 12, it is possible to obtain the same effect as that in Embodiments 1 to 4 and Embodiment 11.

Next, a semiconductor device manufacturing method according to Embodiment 13 will be described.FIG. 26is a flowchart illustrating the outline of the semiconductor device manufacturing method according to Embodiment 13. The semiconductor device manufacturing method according to Embodiment 13 differs from the semiconductor device manufacturing method according to Embodiment 11 in that, after laser annealing for activating an n+cathode layer4and a buried p layer6is performed, n buffer layers15ato15care formed by proton irradiation and furnace annealing is performed to activate the n buffer layers15ato15c.

Specifically, first, similarly to Embodiment 11, a process from the formation of a front surface element structure to the grinding of the rear surface of an n−semiconductor substrate is formed (Step S111to S114). Then, similarly to Embodiment 11, a process from the formation of an n+cathode layer4to laser annealing for activating the n+cathode layer4and the buried p layer6is performed (Steps S115to S117). Then, the n buffer layers15ato15care formed at different depths from the rear surface of the substrate by multi-stage irradiation with protons from the rear surface of the substrate (Step S118). A method for forming the n buffer layers15ato15cis the same as that in Embodiment 4. Then, furnace annealing is performed to activate the n buffer layers15ato15c(Step S119). Then, similarly to Embodiment 11, a process from the control of the lifetime to the formation of a cathode electrode7is performed (Steps S120to S122). In this way, the FWD illustrated inFIG. 8is completed.

Then, the impurity concentration of an n−drift region1and an n buffer layer15in a semiconductor device manufactured by the semiconductor device manufacturing method according to Embodiment 13 was verified.FIG. 28is a characteristic diagram illustrating an impurity concentration distribution on the rear surface side of a substrate in a semiconductor device according to Example 2. An FWD (hereinafter, referred to as Example 2) was manufactured by the semiconductor device manufacturing method according to Embodiment 13 and the impurity concentration of the n−drift region1and the n buffer layer15was measured. The measurement result is illustrated inFIG. 28.FIG. 28illustrates the impurity concentration (donor concentration) distribution of the first-stage n buffer layer15a, which is arranged at the deepest position from the rear surface of the substrate, in a depth direction from the rear surface of the substrate. InFIG. 28, a starting point of the horizontal axis is the interface between the n buffer layer15aand a portion of the n−drift region1which is interposed between the n buffer layers15aand15b.

That is,FIG. 28illustrates the donor concentration distribution of the first-stage n buffer layer15a, which is formed by multi-stage irradiation with protons, in a direction from the rear surface to the front surface of the substrate. A portion of the n−drift region1which is closer to the front surface of the substrate than the n buffer layer15ahas a uniform impurity concentration distribution at a position deeper than a position with the impurity concentration peak of the n buffer layer15a. In addition, for comparison,FIG. 28illustrates the impurity concentration distribution of an FWD (hereinafter, referred to as a comparative example), which is manufactured without performing laser annealing on the rear surface of the substrate in Step S117, at the same depth as that in Example 2. A method for manufacturing the comparative example is the same as the method for manufacturing Example 2 except that laser annealing in Step S117is not performed.

The results illustrated inFIG. 28proved that, in the comparative example (laser annealing was not performed), the impurity concentration of a portion of the n−drift region1which was interposed between the n buffer layers15aand15bwas higher than the impurity concentration of the portion (n−drift region1) which has a uniform impurity concentration distribution at the position deeper than a position with the impurity concentration peak of the n buffer layer15a. In contrast, in Example 2 (laser annealing is performed), impurity concentration at the interface between the n−drift region1and the n buffer layer15ais substantially equal to the impurity concentration of the portion (n−drift region1) which has a uniform impurity concentration distribution at the position deeper than a position with the impurity concentration peak of the n buffer layer15a. That is, the results proved that it was possible to form the n buffer layer15, without changing the impurity concentration of the n−drift region1.

The results proved that, when proton irradiation and activation annealing were performed in Steps S118and S119after laser annealing was performed on the rear surface of the substrate in Step S117, it was possible to prevent a variation in donor concentration, as illustrated inFIG. 28.

As described above, according to Embodiment 13, it is possible to obtain the same effect as that in Embodiments 1 to 4, 11, and 12.

Next, a semiconductor device manufacturing method according to Embodiment 14 will be described.FIG. 27is a flowchart illustrating the semiconductor device manufacturing method according to Embodiment 14. The semiconductor device manufacturing method according to Embodiment 14 differs from the semiconductor device manufacturing method according to Embodiment 13 in that, after a buried p layer6is formed, an n+cathode layer4is formed.

Specifically, first, similarly to Embodiment 13, a process from the formation of a front surface element structure to the grinding of the rear surface of an n−semiconductor substrate is formed (Step S131to S134). Then, the buried p layer6is formed (Step S135) and then the n+cathode layer4is formed (Step S136). A method for forming the buried p layer6and a method for forming the n+cathode layer4are the same as those in Embodiment 13. Then, similarly to Embodiment 13, a process from laser annealing for activating the n+cathode layer4and the buried p layer6to the formation of a cathode electrode7is performed (Steps S137to S142). In this way, the FWD illustrated inFIG. 8is completed.

As described above, according to Embodiment 14, it is possible to obtain the same effect as that in Embodiments 1 to 4 and 11 to 13.

Various modifications and changes of the invention can be made. In each of the above-described embodiments, for example, the dimensions or impurity concentration of each component varies depending on, for example, required specifications. In each of the above-described embodiments, the lifetime of the carrier is controlled by electron beam irradiation. However, the invention is not limited thereto. For example, metal particles, such as platinum (Pt) particles, may be diffused to control the lifetime of the carrier, or particle beams, such as protons or helium (He) ions, other than the electron beams may be radiated to the semiconductor substrate to control the lifetime of the carrier. In addition, in each of the above-described embodiments, the first conductivity type is an n type and the second conductivity type is a p type. However, in the invention, the first conductivity type may be a p type and the second conductivity type may be an n type. In this case, the same effect as described above is obtained.

INDUSTRIAL APPLICABILITY

As described above, the semiconductor device according to the invention is useful for a power semiconductor device which is used in, for example, a power conversion apparatus.

EXPLANATIONS OF LETTERS OR NUMERALS