Semiconductor substrate, semiconductor device, and method of manufacturing the same

A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress to it.

FIELD OF THE INVENTION

The present invention relates to a semiconductor substrate, semiconductor device, and method of manufacturing the same.

BACKGROUND OF THE INVENTION

Conventionally, hetero epitaxial growth is known as a method of epitaxially growing, on a single-crystal substrate, a material different from it. In hetero epitaxial growth, an epitaxial layer having a strained crystal lattice can be formed depending on the material and conditions of crystal growth. In an epitaxial layer having a strained crystal lattice, the atomic interval in the epitaxial layer increases due to tensile stress. Accordingly, the effective mass of carriers in the epitaxial layer decreases, and the carrier mobility can be increased.

As a technique using this fact, Japanese Patent Laid-Open No. 2000-286418 discloses a technique for increasing the carrier mobility by using a silicon layer (to be referred to as a “strained silicon layer” hereinafter) strained by an SiGe layer. In the strained Si technology, an Si layer is formed on an SiGe layer to strain the semiconductor layer to make the lattice constant of the semiconductor layer larger than that of the unstrained Si, thereby increasing the carrier mobility in a channel. When silicon is epitaxially grown on an SiGe layer, it grows complying with SiGe having a lattice constant larger than that of silicon (the lattice constant difference between Si and Ge is about 4%). Hence, strain of several % occurs (the strain amount changes depending on the amount of Ge contained in the SiGe layer).

On the Internet, an article titled “Two high-performance transistor techniques developed in front line of semiconductor field” is disclosed at http://www.mitsubishielectric.co.jp/news/2002/1217-b.ht ml with a dateline of Dec. 17, 2002. In this technique, tensile stress is applied to a silicon layer from its upper side to strain the crystal lattice of the silicon layer. For example, tensile stress is applied to a channel region from the side of a gate electrode formed above the channel region, thereby increasing the carrier mobility in the channel region.

However, in the technique of Japanese Patent Laid-Open No. 2000-286418, since the SiGe layer contains defects, it is difficult to form a strained silicon layer having high crystallinity. In the article disclosed on the Internet, after an unstrained silicon layer is formed, strain is introduced by a device structure formed on the silicon layer. In this case, the structure under the strained silicon layer is made of a material matched before the silicon layer is strained. For this reason, when strain is to be applied from the upper side of the silicon layer, a force which prevents the strain is generated in the layer under the silicon layer. Generally, when biaxial stress is applied to a silicon layer to strain it, a strain amount is generated in the plane of silicon in accordance with
ε=(1−ν)·σ/E(Equation 1)
where ε is the strain amount (no unit) in the plane of silicon, ν is the Poisson's ratio (no unit) of silicon crystal, σ is biaxial stress [GPa] applied in the plane of silicon, and E is the Young's modulus [GPa] of silicon crystal. Normally, to obtain 1% to 2% as the strain amount ε of silicon on SiGe when E=162 GPa, and ν=0.26, stress σ of 2.2 to 4.4 [GPa] is necessary. Hence, in a general Si-LSI (Large-Scale Integration) structure, not only the surface silicon layer but also an underlying portion must be strained. To do this, if stress is applied from the upper or side surface of the silicon layer, larger stress than the above value needs to be applied.

On the other hand, in manufacturing semiconductor devices, reduction of the element size progresses to implement high integration degree and high operation speed of semiconductor devices. However, along with the reduction of the element size, the carrier mobility decreases, and the leakage current increases. It is accordingly pointed out that the micropatterning technology should reach its physical limit in the future.

To cope with this problem, Japanese Patent Laid-Open No. 2000-286418 discloses a strained Si technology for increasing the carrier mobility of a transistor without depending on micropatterning. However, as described above, since an SiGe layer generally contains defects, it is difficult to form a strained silicon layer having high crystallinity.

“A folded-channel MOSFET for deep-sub-tenth micron era”, in IEDM Tech. Dig., 1998, pp. 1032–1034 discloses, as an epoch-making device structure next to the strained Si structure, a Fin FET developed by a group of Professor C. Hu et al in the University of California, Berkeley. In a conventional planar FET, the channel is controlled from the upper side by a gate electrode formed on silicon. In the Fin FET, a gate electrode is formed to sandwich a channel called a “Fin” on silicon so that the channel is controlled from both sides. With this structure, the increase in leakage current, which poses a problem in the conventional planar FET, can effectively be suppressed, and a finer device structure can be formed.

A Fin FET can easily be manufactured by using the current semiconductor device process. In addition, it is supposed that elements 400 times that in the prior art can be integrated on the chip. Hence, the Fin is regarded as a promising device structure of next generation.

In the Fin FET however, the channel is formed on a non-porous layer. If strain is to be applied from the upper side of the channel, a force which counteracts the strain is generated in the layer under the channel. Hence, the channel can hardly efficiently be strained.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the above situation, and has as its object to efficiently strain a semiconductor layer or semiconductor region.

According to the first aspect of the present invention, there is provided a semiconductor substrate characterized by comprising a semiconductor layer, a porous layer which supports the semiconductor layer, and a strain inducing region which strains the semiconductor layer by applying stress to the semiconductor layer.

According to the second aspect of the present invention, there is provided a semiconductor substrate characterized in that a semiconductor device is formed on the semiconductor layer.

According to the third aspect of the present invention, there is provided a semiconductor substrate manufacturing method characterized by comprising steps of forming a porous layer on a substrate, forming a semiconductor layer on the porous layer, and forming a strain inducing region which strains the semiconductor layer by applying stress to the semiconductor layer.

According to the fourth aspect of the present invention, there is provided a semiconductor device manufacturing method characterized by comprising steps of preparing a semiconductor substrate manufactured by applying the above manufacturing method, and forming a semiconductor device on the semiconductor substrate.

According to the fifth aspect of the present invention, there is provided a semiconductor device comprising a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of a sectional shape is larger than a width of the sectional shape, and a strain inducing region which strains the structure by applying stress to the structure.

According to the sixth aspect of the present invention, there is provided a transistor comprising the above semiconductor device, a source which is formed at one end of a semiconductor region, and a drain which is formed at other end of the semiconductor region.

According to the seventh aspect of the present invention, there is provided a semiconductor device manufacturing method comprising steps of forming a porous layer on a substrate, forming a semiconductor layer on the porous layer, etching the semiconductor layer to form a semiconductor region whose height of a sectional shape is larger than a width of the sectional shape, and forming a strain inducing region which strains the semiconductor region by applying stress to the semiconductor region.

According to the eighth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising steps of forming a porous layer on a substrate, forming a semiconductor layer on the porous layer, etching the porous layer and the semiconductor layer to form a semiconductor region whose height of a sectional shape is larger than a width of the sectional shape, and forming a strain inducing region which strains a porous region and the semiconductor region by applying stress to the porous region and the semiconductor region.

According to the ninth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising steps of partially forming a porous layer on a substrate, forming a semiconductor layer on the partially formed porous layer, etching the semiconductor layer to form, on the partially formed porous layer, a semiconductor region whose height of a sectional shape is larger than a width of the sectional shape, and forming a strain inducing region which strains the semiconductor region by applying stress to the semiconductor region.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A to 1Eare sectional views for explaining a substrate manufacturing method according to the preferred first embodiment of the present invention.

In the step shown inFIG. 1A, a substrate11is prepared. As the substrate11, for example, silicon is preferable. However, any other material may be employed.

In the step shown inFIG. 1B, a porous layer12is formed on the surface of the substrate11. The Young's modulus of the porous layer12is lower than that of a semiconductor layer13to be formed in the step shown inFIG. 1C. As the material of the porous layer12, porous silicon prepared by porosifying silicon is preferably employed. A porous silicon layer can be formed by anodizing the surface of the silicon substrate. Anodizing can be executed by arranging an anode and a cathode in an electrolytic solution containing hydrofluoric acid, placing the substrate between the electrodes, and supplying a current between the electrodes.

The porous silicon layer may include a single layer having an almost uniform porosity or two or more layers having different porosities. The Young's modulus of the porous silicon layer can be changed to at least about 1 GPa to about 83 GPa by changing the porosity (e.g., D. Bellet, “Properties of Porous Silicon”, edited by L Canham, INSPEC, The Institution of Electrical Engineers, pp. 127–131).

FIG. 5is a graph showing the relationship between a porosity σ and the Young's modulus E of porous silicon on the basis of data disclosed in the paper by D. Bellet. As shown inFIG. 5, the higher the porosity of porous silicon becomes, the lower the Young's modulus becomes. When anodizing is used, the porosity of porous silicon can be controlled by the concentration of the solution, the current density, and the resistivity of the silicon substrate. Hence, porous silicon having a desired Young's modulus can be formed.

In the present invention, the method of forming a porous layer is not limited to anodizing. For example, a method of implanting hydrogen ions or helium ions in the substrate can also be employed.

In the step shown inFIG. 1C, the semiconductor layer13is formed on the porous layer12by epitaxial growth. By epitaxial growth, a high-quality semiconductor layer can be formed.

In the step shown inFIG. 1D, after a resist is applied onto the semiconductor layer13, the porous layer12and semiconductor layer13are patterned by general lithography to form opening portions. With this process, a plurality of porous layers12′ and semiconductor layers13′ each having an island shape are formed on the substrate11. The width of each opening portion is not particularly limited, though it is preferably 1 μm or more.

In the step shown inFIG. 1E, a strain inducing region14which applies stress to the semiconductor layer13′ is formed on the substrate11exposed to each opening portion formed in the step shown inFIG. 1D. The strain inducing region14acts to pull the porous layer12′ and semiconductor layer13′ in a direction almost parallel to their surfaces so that stress acts on the second semiconductor layer13′ to stretch it in an almost horizontal direction. In the semiconductor layer13′ to which a tensile force acts in the in-plane direction by the strain inducing region14, the crystal lattice is strained, and the mobility of carriers that move in the semiconductor layer13′ increases. As the strain inducing region14, silicon oxide or SiN using, e.g., TEOS (Tetra Ethyl Ortho Silicate) as a raw material can be employed.

With the above method, a substrate having the porous layer12′ formed on the substrate11, the semiconductor layer13′ formed on the porous layer12′, and the strain inducing region14which applies stress to the semiconductor layer13′ to increase the carrier mobility in the semiconductor layer13′ can be manufactured.

To form CVD (Chemical Vapor Deposition) oxide silicon, TEOS, TEOS+O2, TEOS+O3, SiH4+O2, SiH4+N2O, SiH2Cl2+N2O, or the like is used. CVD methods include thermal CVD and plasma CVD.

To form silicon nitride, thermal CVD and plasma CVD can be used. Examples of a raw material containing Si are SiCl2, SiH, and SiH2Cl2. Examples of a raw material containing N are NH3, N2H4, and N2.

The porous layer12′ having a lower Young's modulus than that of the semiconductor layer13′ is formed on the lower side. For this reason, most of the tensile force applied from the strain inducing region14to the semiconductor layer13′ acts on the semiconductor layer13′ so that the force that pulls the semiconductor layer13′ can be small. When the porous layer12′ is arranged under the semiconductor layer13′ to efficiently convert the tensile force into in-plane strain, large strain can be generated by smaller stress.

In addition, when the island-shaped semiconductor layers13′ are formed, they can independently be strained. If the semiconductor layer13is formed uniformly on the porous layer12and strained, the entire strain amount can be enormous. For example, if SiGe is completely relaxed, the strained silicon layer on SiGe is strained by about 1% in plane. In a wafer having a diameter of 300 mm, the total strain amount is 3 mm. When the layer is strained from an unstrained state, a silicon layer having a diameter larger by 3 mm is formed. Actually, the entire silicon layer cannot be strained up to such an amount. According to the first embodiment, the semiconductor layers13′ each having an island shape are formed on the substrate11. Accordingly, a 1-μm opening portion is formed in correspondence with, e.g., a 10-μm square semiconductor layer13′. Each island-shaped semiconductor layer13′ has a size of 10.1 mm, and each opening portion between the semiconductor layers13′ has a size of 0.9 mm so that the island-shaped semiconductor layers13′ can individually be strained.

In forming strained Si on SiGe, it is already strained at the time of deposition (epitaxial growth). Hence, the actual size never increases. However, when an unstrained layer is strained later, the above-described problem is posed.

A substrate manufacturing method according to the preferred second embodiment of the present invention will be described next. In the substrate manufacturing method according to this embodiment, some steps in the substrate manufacturing method according to the first embodiment are changed.FIGS. 2A to 2Eare sectional views for explaining the substrate manufacturing method according to the second embodiment. The steps shown inFIGS. 2A to 2Care the same as those shown inFIGS. 1A to 1C.

In the step shown inFIG. 2D, a semiconductor layer13is etched to form opening portions. In the step shown inFIG. 2E, a strain inducing region14is formed on a porous layer12exposed to each opening portion. With the above structure, a semiconductor layer13′ formed on the porous layer12can efficiently be strained.

A substrate manufacturing method according to the preferred third embodiment of the present invention will be described next. In the substrate manufacturing method according to this embodiment, some steps in the substrate manufacturing method according to the first embodiment are changed.FIGS. 3A to 3Eare sectional views for explaining the substrate manufacturing method according to the third embodiment. The steps shown inFIGS. 3A and 3Care the same as those shown inFIGS. 1A and 1C.

In the step shown inFIG. 3B, porous layers are partially formed in a substrate11. When anodizing is employed as a method of forming the porous layer, for example, a protective film (e.g., a nitride film or HF-resistant mask) which protects the substrate from the chemical solution (e.g., hydrofluoric acid) used in anodizing is formed on the substrate11. After that, the substrate11is anodized to form partial porous layers12′ shown inFIG. 3B. In the step shown inFIG. 3D, a semiconductor layer13is etched to form opening portions. In the step shown inFIG. 3E, a strain inducing region14is formed on the substrate11exposed to each opening portion. With the above structure, a semiconductor layer13′ formed on the porous layer12can efficiently be strained.

[First Application Example of Semiconductor Substrate]

In this application example, a method of manufacturing a semiconductor device using a semiconductor substrate which can be manufactured by using the substrate manufacturing method according to one of the preferred first to third embodiments of the present invention will be described.

FIGS. 4A to 4Dshow a structure near a semiconductor layer13′ and strain inducing region14of a substrate which is manufactured by the steps according to the second embodiment of the preferred first to third embodiments of the present invention. First, an element isolation region54and a gate insulating film56are formed on the surfaces of the semiconductor layer13or13′ (FIG. 4A). As the material of the gate insulating film56, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, titanium oxide, scandium oxide, yttrium oxide, gadolinium oxide, lanthanum oxide, zirconium oxide, or mixed glass thereof is preferably used. The gate insulating film56can be formed by, e.g., oxidizing the surface of the semiconductor layer13or13′ or depositing an appropriate substance on the surface of the semiconductor layer13or13′ by CVD or PVD.

A gate electrode55is formed on the gate insulating film56. The gate electrode55can be formed from, e.g., polysilicon doped with a p- or n-type impurity, a metal such as tungsten, molybdenum, titanium, tantalum, aluminum, or copper, an alloy containing at least one of them, or a metal silicide such as molybdenum silicide, tungsten silicide, or cobalt silicide, or a metal nitride such as titanium nitride, tungsten nitride, or tantalum nitride. The gate insulating film56may be formed by stacking a plurality of layers made of different materials, like, e.g., a polycide gate. The gate electrode55may be formed by, e.g., a method called salicidation (self-aligned formation of silicide), a method called a damascene gate process, or any other method. With the above step, the structure shown inFIG. 4Ais obtained.

Next, an n-type impurity such as phosphorus, arsenic, or antimony or a p-type impurity such as boron is doped into the semiconductor layer13or13′ to form relatively lightly doped source and drain regions58(FIG. 4B). The impurity can be doped by, e.g., ion implantation and annealing.

An insulating film which covers the gate electrode55is formed and etched back to form a sidewall59on the side portion of the gate electrode55.

An impurity having the same conductivity type as that of the above impurity is doped into the semiconductor layer13or13′ again to form relatively heavily doped source and drain regions57. With the above step, the structure shown inFIG. 4Bis obtained.

A metal silicide layer60is formed on the upper surface of the gate electrode55and the upper surfaces of the source and drain regions57(FIG. 4C). As the material of the metal silicide layer60, for example, nickel silicide, titanium silicide, cobalt silicide, molybdenum silicide, or tungsten silicide is preferably used. These silicides can be formed by depositing a metal to cover the upper surface of the gate electrode55and the upper surfaces of the source and drain regions57, executing annealing to make the metal react with silicon on the lower side, and removing unreacted portions of the metal by using an etchant such as sulfuric acid. The surface of the suicide layer may be nitrided as needed. With the above step, the structure shown inFIG. 4Cis obtained.

An insulating layer61is formed to cover the upper surface of the gate electrode and the upper surfaces of the source and drain regions, which are converted into a silicide (FIG. 4D). As the material of the insulating layer61, silicon oxide containing phosphorus and/or boron is preferably used.

The surface is planarized by CMP (Chemical Mechanical Polishing) as needed. Then, contact holes are formed in the insulating layer61. When photolithography using KrF excimer laser, ArF excimer laser, F2excimer laser, electron beam, or X-rays is applied, a rectangular contact hole having a side smaller than 0.25 μm or a circular contact hole having a diameter smaller than 0.25 μm can be formed.

The contact holes are filled with a conductive material. As a preferable method of filling the contact holes with a conductive material, a film of a high refractory metal or a nitride thereof, which serves as a barrier metal62, is formed on the inner walls of the contact holes. Then, a conductive material63such as a tungsten alloy, aluminum, an aluminum alloy, copper, or a copper alloy is deposited by CVD, PVD (physical vapor deposition), or plating. A conductive material deposited higher than the upper surface of the insulating layer61may be removed by etch back or CMP. Before filling the contact holes with the conductive material, the surfaces of the silicide layers in the source and drain regions exposed to the bottom portions of the contact holes may be nitrided. With the above step, a transistor such as a FET (Field Effect Transistor) can be formed on the substrate, and a semiconductor device having the structure shown inFIG. 4Dcan be obtained.

As described above, according to this embodiment, the semiconductor layer can efficiently be strained, and the carrier mobility of the semiconductor layer can be increased. Hence, the device such as a transistor formed on the semiconductor layer can be driven at a high speed.

[Second Application Example of Semiconductor Substrate]

In this application example, the semiconductor device manufactured by the first application example of the semiconductor substrate is further improved. In this application example, as a gate electrode55formed on the surface of a semiconductor layer13or13′ by the first application example of the semiconductor substrate, a gate electrode which stretches the second semiconductor layer13or13′ in an almost horizontal direction is used, thereby further straining the semiconductor layer13or13′. To do this, the gate electrode55which is ion-implanted and then annealed can be used.

In this case, as a strain inducing region14, a material which applies a tensile force to the semiconductor layer13or13′ formed into an island shape is preferably used. However, such a material need not always be used. Various materials (i.e., the materials do not always apply a tensile force to the semiconductor layer13or13′) and structures optimized in accordance with the characteristic of element isolation can be used.

In addition, when an interlayer dielectric film is formed on the surface of the semiconductor layer13or13′, and stress due to this film is controlled, more stress can be applied to the semiconductor layer13or13′.

Examples 1 to 5 of the present invention will be described below.

An 8-inch p-type silicon wafer11(resistivity: 0.013 to 0.017 Ω-cm) was prepared (FIG. 1A). Porous silicon12was formed on the surface of the silicon wafer11by anodizing (FIG. 1B). The anodizing solution was 50% HF:IPA=2:1 (volume ratio), the current density was 8 mA/cm2, the current application time was 11 min, and the thickness of the porous silicon12was 10 μm. After the anodizing, the silicon wafer11was oxidized in oxygen at a low temperature of 400° C. for 1 hr. The surface oxide film was removed by DHF. Then, the wafer was loaded to an epitaxial apparatus. After being loaded to the epitaxial apparatus, the silicon wafer11was subjected to surface treatment in a hydrogen atmosphere at 950° C. for 10 sec to fill the surface pores. In addition, a small amount of silicon-based gas was introduced to fill the remaining surface pores. After that, silicon was epitaxially grown on the silicon wafer11to form an epitaxial silicon layer13having a predetermined thickness (FIG. 1C). The thickness of the epitaxial silicon layer13was determined in accordance with the device to be manufactured and could be controlled in a wide range of about 10 nm to several μm.

Next, a protective oxide film was formed on the surface of the epitaxial silicon layer13. Patterning and etching were executed by lithography to pattern the epitaxial silicon layer13and the porous silicon12under it into an island shape (FIG. 1D). The size and shape of each island were determined in accordance with the device to be manufactured. The size of an island could be controlled to 1 to several hundred μm.

After the silicon was etched off, oxide films14were formed in the gaps between epitaxial silicon layers13′ and porous silicon12′ having an island shape by CVD using TEOS+O3as a raw material (FIG. 1E). The silicon oxide film can control its stress in a wide range. For this reason, conditions were set such that a tensile force was applied to the epitaxial silicon layers13′ and porous silicon12′ having an island shape.

With the above process, the silicon semiconductor layer13′ on the surface could be strained.

In Example 2, some steps in Example 1 were changed. More specifically, in Example 2, instead of forming a protective oxide film on the surface of an epitaxial silicon layer13, and executing patterning and etching by lithography to pattern the epitaxial silicon layer13and porous silicon12under it, the epitaxial silicon layer13was patterned into island shapes (FIG. 2D).

In Example 3, some steps in Example 1 were changed. More specifically, in Example 3, porous silicon layers12″ were partially formed in a silicon wafer11(FIG. 3B). To selectively anodize silicon to partially form the porous silicon layers12″, for example, (1) boron is ion-implanted in a region where silicon is to be porosified to form a p++-layer, or (2) an insulating protective film having an HF resistance is patterned on the silicon to cover the surface except the regions to be selectively porosified.

In Examples 1 to 3, a CMOS (Complementary Metal-Oxide Semiconductor) structure having an island shape was formed on the surface silicon (FIGS. 4A to 4D). The CMOS was formed by a general method. It was confirmed that the electron mobility and hole mobility in the NMOS and PMOS transistors increased as compared to a device with an unstrained structure.

A method of applying strain to a silicon semiconductor layer was applied to Example 4. More specifically, arsenic was injected to a gate electrode55immediately above the channel to form a gate protective film which surrounds the gate. After that, annealing was executed. By using expansion and contraction of the gate electrode55and gate protective film, local strain was generated in the channel region. In addition to the tensile force in the material which applied a tensile force between island-shaped silicon layers, stress was applied from immediately above the gate so that a semiconductor layer13or13′ could efficiently be strained. In addition, porous silicon12or12′ having a lower Young's modulus than that of the semiconductor layer13or13′ was arranged under it. With this structure, the silicon semiconductor layer13or13′ on the surface could further efficiently be strained.

In Examples 1 to 5 described above, the porous silicon formation conditions are not limited to the above conditions. To change the porosity, the type (p-type or n-type) of the substrate, resistivity, solution concentration, current, and temperature can be changed. As a method of epitaxially growing silicon on porous silicon, various methods such as CVD, MBE (Molecular Beam Epitaxy), sputtering, and liquid-phase growth can be employed. Other steps can also be executed not only under the conditions limited in the examples but also under various conditions.

As described above, according to the present invention, for example, a semiconductor layer can efficiently be strained.

Other preferred embodiments of the present invention will be described next with reference to the accompanying drawings.FIGS. 6A to 8Hare sectional views taken along a line A–A′ inFIG. 9B.

FIGS. 6A to 6Hare sectional views for explaining a Fin device manufacturing method according to the preferred fourth embodiment of the present invention.

In the step shown inFIG. 6A, a substrate21is prepared. As the substrate21, a substrate whose surface can be porosified is preferable. For example, silicon can be used.

In the step shown inFIG. 6B, a porous layer22is formed on the surface of the substrate21. For the porous layer22, a material having a Young's modulus lower than that of a semiconductor layer33to be formed in the step shown inFIG. 6Cis preferably used. For example, when a silicon substrate is used as the substrate21, porous silicon formed by porosifying the surface of the silicon substrate can be used as the porous layer22. Porous silicon can be formed by anodizing the surface of the silicon substrate. Anodizing can be executed by arranging an anode and a cathode in an electrolytic solution containing hydrofluoric acid, placing the substrate between the electrodes, and supplying a current between the electrodes.

As a characteristic of porous silicon, its Young's modulus can be changed to at least about 1 GPa to about 83 GPa by changing the porosity. Hence, when the porosity of the porous silicon is adjusted to set the Young's modulus of the-porous silicon, the Young's modulus of the porous layer22can be set lower than that of the semiconductor layer23to be formed in the step shown inFIG. 6C.

The porous silicon layer may include a single layer having an almost uniform porosity or two or more layers having different porosities. In the present invention, the method of forming a porous layer is not limited to anodization, and may adopt a method of forming a porous layer by implanting an ion such as a hydrogen ion or helium ion in a substrate.

In the step shown inFIG. 6C, the semiconductor layer23is formed on the porous layer22formed in the step shown inFIG. 6B. The method of forming the semiconductor layer23is not particularly limited. The semiconductor layer23can be formed by, e.g., epitaxial growth. When epitaxial growth is used, a high-quality single-crystal semiconductor layer can be formed.

In the step shown inFIG. 6D, an insulating film24is formed on the semiconductor layer23. The insulating film24includes, e.g., an oxide film, nitride film, LTO and other insulating film, and a multilayered structure of these films.

In the step shown inFIG. 6E, a resist is applied onto the insulating film24and patterned by lithography. Then, the insulating film24and semiconductor layer23are etched to form Fins23″ each of which has an insulating film24′ and semiconductor layer23′ and whose height of the section shape is larger than the width of the section shape. The Fin23″ is formed such that a width t1and height t2of the sectional shape satisfy t1<t2. That is, as a characteristic feature of the Fin23″, it has a vertically long sectional shape. A structure having the thus formed Fin is called a “Fin structure”. A device having a Fin structure is called a “Fin device”.

A gate insulating film26is formed on the surface of the Fin23″. As the material of the gate insulating film26, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, titanium oxide, scandium oxide, yttrium oxide, gadolinium oxide, lanthanum oxide, zirconium oxide, or mixed glass thereof is preferably used. The gate insulating film26can be formed by, e.g., oxidizing the surface of the SOI layer or depositing an appropriate substance on the surface of the SOI layer by CVD or PVD.

In the step shown inFIG. 6F, a gate electrode25is formed on the Fin23″. The gate electrode25can be formed from, e.g., polysilicon doped with a p- or n-type impurity, a metal such as tungsten, molybdenum, titanium, tantalum, aluminum, or copper, an alloy containing at least one of them, or a metal silicide such as molybdenum silicide, tungsten silicide, or cobalt silicide, or a metal nitride such as titanium nitride, tungsten nitride, or tantalum nitride. The gate insulating film26may be formed by stacking a plurality of layers made of different materials, like, e.g., a polycide gate. The gate electrode55may be formed by, e.g., a method called salicidation (self-aligned formation of silicide), a method called a damascene gate process, or any other method.

In the step shown inFIG. 6G, patterning is performed to form the gate electrode25and gate insulating film26at least on the side surfaces of the central portion of the Fin23″. The gate electrode25is formed on the gate insulating film26such that the Fin23″ is sandwiched by the gate electrode25. Next, an n-type impurity such as phosphorus, arsenic, or antimony or a p-type impurity such as boron is doped into the Fin23″ exposed to both sides of the gate electrode25to form a relatively lightly doped source region25′ and drain region25″. The impurity can be doped by, e.g., ion implantation and annealing.

In the step shown inFIG. 6H, strain inducing regions27to apply stress to the Fin structure having the Fin23″ are formed in contact with the gate electrode25and Fin23″ in the source region25′ and drain region25″. As the strain inducing region27, silicon oxide or SiN using, e.g., TEOS (Tetra Ethyl Ortho Silicate) as a raw material can be employed. Oxide silicon can be formed from TEOS, TEOS+O2, TEOS+O3, SiH4+O2, SiH4+N2O, SiH2Cl2+N2O, or the like by CVD (Chemical Vapor Deposition). As CVD, thermal CVD or plasma CVD can be used. Silicon nitride can be formed by using thermal CVD and plasma CVD. Examples of a raw material containing Si are SiCl2, SiH, and SiH2Cl2. Examples of a raw material containing N are NH3, N2H4, and N2.

The strain inducing region27spreads almost parallel to the surface of the porous layer22to apply compression stress to the Fin structure having the Fin23″. The Fin23″ has such a structure that the width t1and the height t2of the sectional shape satisfy t1<t2. For this reason, stress from the side surface is converted into in-plane strain. Hence, larger strain can be generated in the Fin23″ by smaller stress from the strain inducing region27. When strain is generated in the strain inducing region27, the mobility of carriers which moves in the Fin23″ increases.

The porous layer22′ having a lower Young's modulus than that of the Fin23″ is formed on the lower side. For this reason, most of the compression stress applied from the strain inducing region27to the Fin23″ acts on the Fin23″ so that the stress from the strain inducing region27can be smaller. As described above, when the porous layer22′ is arranged under the Fin23″ to efficiently convert the compression stress into in-plane strain, large strain can be generated by smaller stress.

A Fin device is manufactured by the above method.

FIGS. 9A and 9Bare schematic views showing the structure of the Fin device manufactured by the above Fin device manufacturing method.FIG. 9Ais a sectional view taken along a line A–A′ inFIG. 9B.FIG. 9Bis a perspective view of the Fin device. As shown inFIGS. 9A and 9B, according to this embodiment, a Fin FET having the porous layer22formed on the substrate21, and the strain inducing region27which applies stress to the Fin23″ formed on the porous layer22is manufactured.

A plurality of Fins23″ may be formed on the porous layer22. For example,FIG. 6Eillustrates two identical structures. Increasing the number of structures corresponds to increasing W (width) of the channel of the transistor having a Fin structure. In this case, for example, an element isolation region29such as an insulating film or shallow trench is preferably formed on the porous layer22in the step shown inFIG. 6Bby using an element isolation method such as LOCOS or STI. In the step shown inFIG. 6D, the insulating film24is formed on the semiconductor layer23. The insulating film24may be omitted. In this case, the gate insulating film26is formed on the upper surface of the Fin23″ in the step shown inFIG. 6E.

A Fin device manufacturing method according to the preferred fifth embodiment of the present invention will be described below. In the Fin device manufacturing method according to this embodiment, some steps in the Fin device manufacturing method according to the fourth embodiment are changed.FIGS. 7A to 7Hare sectional views showing the Fin device manufacturing method according to the fifth embodiment. A description of, in the steps shown inFIGS. 7A to 7H, the same steps as inFIGS. 6A to 6Hwill be omitted.

In the step shown inFIG. 7E(corresponding toFIG. 6E), a resist is applied onto an insulating film24and patterned by lithography. Then, the insulating film24, semiconductor layer23, and porous layer22are etched. The patterned semiconductor layer23and porous layer22form a Fin23′″ having a semiconductor region whose height of the sectional shape is larger than the width of the sectional shape. The Fin23′″ is formed such that a width t1and height t2of the sectional shape satisfy t1<t2.

In the step shown inFIG. 7H(corresponding toFIG. 6H), strain inducing regions27which apply stress onto a substrate21are formed. As the strain inducing region27, silicon oxide or SiN using, e.g., TEOS (Tetra Ethyl Ortho Silicate) as a raw material can be employed.

A Fin device manufacturing method according to the preferred sixth embodiment of the present invention will be described below. In the Fin device manufacturing method according to this embodiment, some steps in the Fin device manufacturing method according to the fourth embodiment are changed.FIGS. 8A to 8Hare sectional views showing the Fin device manufacturing method according to the sixth embodiment. A description of, in the steps shown inFIGS. 8A to 8H, the same steps as inFIGS. 6A to 6Hwill be omitted.

In the step shown inFIG. 8B(corresponding toFIG. 6B), porous layers22″ are partially formed in a substrate21. When anodizing is employed as a method of partially forming the porous layers22″, for example, a protective film (e.g., a nitride film or HF-resistant mask) which protects the substrate from the chemical solution (e.g., hydrofluoric acid) used in anodizing is formed on the substrate21. After that, the substrate21is anodized to form the partial porous layers22′ shown inFIG. 8B.

In the step shown inFIG. 8E(corresponding toFIG. 6E), an insulating film24and semiconductor layer23are etched as in the fourth embodiment. The sixth embodiment is different from the fourth embodiment in that a Fin23′″ having a semiconductor region whose height of the sectional shape is larger than the width of the sectional shape is formed on the partial porous layer22″ formed in the step shown inFIG. 8B. The Fin23′″ is formed such that a width t1and height t2of the sectional shape satisfy t1<t2.

A plurality of Fins23′″ may be formed on the substrate21. In this case, for example, an element isolation region29such as an insulating film or shallow trench is formed on the substrate21in the step shown inFIG. 8Bby using an element isolation method such as LOCOS or STI.

As described above, according to the present invention, for example, a semiconductor region can efficiently be strained.

Examples 6 to 8 of the present invention will be described below.

An 8-inch p-type silicon wafer21(resistivity: 0.013 to 0.017 Ω-cm) was prepared (FIG. 6A). Porous silicon22was formed on the surface of the substrate21by anodizing (FIG. 6B). The anodizing solution was 50% HF:IPA=2:1 (volume ratio), the current density was 8 mA/cm2, the current application time was 11 min, and the thickness of the porous silicon12was 10μm. After anodizing, the silicon wafer21was oxidized in oxygen at a low temperature of 400° C. for 1 hr. The surface oxide film was removed by DHF. Then, the wafer was loaded to an epitaxial apparatus. After loading to the epitaxial apparatus, the silicon wafer21was subjected to surface treatment in a hydrogen atmosphere at 950° C. for 10 sec to fill the surface pores. In addition, a small amount of silicon-based gas was introduced to fill the remaining surface pores. After that, silicon was epitaxially grown on the silicon wafer21to form an epitaxial silicon layer23having a predetermined thickness (FIG. 6C). The thickness of the epitaxial silicon layer23was determined in accordance with the device to be manufactured and could be controlled in a wide range of about 10 nm to several μm.

Next, an insulating film24was formed on the surface of the epitaxial silicon layer23(FIG. 6D). Patterning and etching were executed by lithography to etch the insulating film24and epitaxial silicon layer23under it into a Fin structure. After that, a gate insulating film26is formed on the surface of a Fin23″ (FIG. 6E).

A gate electrode25was formed on the Fin23″ (FIG. 6F).

The gate electrode25and gate insulating film26were patterned to form the gate electrode25on the gate insulating film26at the central portion of the Fin23″ such that the Fin23″ was sandwiched by the gate electrode25. Next, an n-type impurity such as phosphorus, arsenic, or antimony or a p-type impurity such as boron was doped into the Fin23″ exposed to both sides of the gate electrode25to form a relatively lightly doped source region25′ and drain region25″ (FIG. 6G).

Next, strain inducing regions27to apply stress to the Fin structure having the Fin23″ were formed in contact with the gate electrode25and Fin23″ in the source region25′ and drain region25″ (FIG. 6H). The strain inducing region27were formed in the gaps between the epitaxial silicon layer23′ and porous silicon22′ having a Fin shape by CVD using TEOS+O3as a raw material. The silicon oxide film can control its stress in a wide range. For this reason, conditions were set such that a tensile force was applied to the sidewalls of the epitaxial silicon layer23″ having a Fin shape. With the above process, the Fin23″ could be strained. A Fin device was thus manufactured.

In Example 7, some steps in Example 6 were changed. More specifically, in Example 7, instead of forming a protective oxide film on the surface of an epitaxial silicon layer23, and executing patterning and etching by lithography to pattern an insulating film24and epitaxial silicon layer23, the insulating film24, epitaxial silicon layer23, and porous layer22were etched into a Fin structure (FIG. 7E).

In Example 8, some steps in Example 6 were changed. More specifically, in Example 8, porous silicon layers22″ were partially formed in a silicon wafer21(FIG. 8B). To selectively anodize silicon to partially form the porous silicon layers22″, for example, (1) boron is ion-implanted in a region where silicon is to be porosified to form a p+-layer, or (2) an insulating protective film having an HF resistance is patterned on the silicon to cover the surface except the regions to be selectively porosified. Unlike Example 1, a Fin23′″ having a semiconductor region whose height of the sectional shape is larger than the width of the sectional shape was formed (FIG. 8E). The Fin23′″ was formed such that a width t1and height t2of the sectional shape satisfied t1<t2. It was confirmed that the carrier mobility in the FIN transistor formed in Examples 6 to 8 according to the present invention increased as compared to a device with an unstrained structure.

In Examples 6 to 8 described above, the porous silicon formation conditions are not limited to the above conditions. To change the porosity, the type (p-type or n-type) of the substrate, resistivity, solution concentration, current, and temperature can be changed. As a method of epitaxially growing silicon on porous silicon, various methods such as CVD, MBE (Molecular Beam Epitaxy), sputtering, and liquid-phase growth can be employed. Other steps can also be executed not only under the conditions limited in the examples but also under various conditions.