IMAGE SENSOR DEVICE AND METHODS OF FORMING THE SAME

An image sensor device and methods of forming the same are described. In some embodiments, the device includes a substrate, a contact pad structure extending from a contact pad region to a black level correction region, a dielectric layer disposed over the substrate in the black level correction region, and a light blocking structure disposed on and through the dielectric layer in the black level correction region. A first portion of the contact pad structure disposed in the black level correction region is in contact with the light blocking structure, and the light blocking structure is in contact with the substrate.

BACKGROUND

Semiconductor image sensors are used to sense incoming visible or non-visible radiation, such as visible light, infrared light, etc. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital still cameras, mobile phones, tablets, goggles, etc. These image sensors utilize an array of pixels that absorb (e.g., sense) the incoming radiation and convert it into electrical signals. An example of an image sensor is a backside illuminated (BSI) image sensor, which detects radiation from a “backside” of a substrate of the BSI image sensor.

Improvements have been made to semiconductor image sensors. For example, power consumption may be lowered to achieve smaller dimensions and high performance. However, lowered power consumption can lead to reduced full-well capacity (FWC). Therefore, an improved image sensor is needed.

DETAILED DESCRIPTION

An image sensor device including a contact pad structure extending from the contact pad region to the black level correction (BLC) region and the methods of forming the same are provided in accordance with some embodiments of the present disclosure. Plural intermediate stages of manufacturing the image sensor device are illustrated. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS.1-13illustrate a method for forming an image sensor device100at various intermediate stages of manufacture according to some embodiments of the present disclosure. For simplicity, some components of the image sensor device100are omitted. The illustration is merely exemplary and is not intended to be limiting beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.1-13, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

As shown inFIG.1, the image sensor device100may include a pixel array region102, a black level correction (BLC) region104, a contact pad region106, and an alignment mark region108. The dashed lines inFIGS.1-13designate the approximate boundaries between the regions102-108. The photosensitive pixels (not shown) are formed in the pixel array region102. The photosensitive pixels (not shown) are formed in the BLC region104and serve as reference pixels that are used to generate reference black level signals, thereby establishing a baseline of an intensity of light for the image sensor device100. The contact pad region106can include one or more contact pad structures through which electrical connections between the image sensor device100and external circuit can be established.

As shown inFIG.1, photosensitive pixels (not shown) are formed in a substrate110. The substrate110may include, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate110may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe. GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

The photosensitive pixels are formed at the front surface110A of the substrate110. The photosensitive pixels may include respective photosensitive region (not shown), which may be formed, for example, by implanting suitable impurity ions into the substrate110from the front surface110A of the substrate110. In some embodiments, the impurity ions may be implanted in an epitaxial layer (not shown) within the substrate110. The photosensitive regions are configured to covert light signals (e.g., photons) to electrical signals, and may be PN junction photo-diodes, PNP photo-transistors, NPN photo-transistors, or the like. For example, the photosensitive regions may include an n-type implantation region formed within a p-type semiconductor layer (e.g., at least a portion of the substrate110). In such embodiments, the p-type semiconductor layer may isolate and reduce electrical cross-talk between adjacent photo-active regions of the photosensitive pixels. In some embodiments, the photosensitive regions may include a p-type implantation region formed within an n-type semiconductor layer (e.g., at least a portion of the substrate110).

Prior to the formation of the photosensitive region, isolation structures (not shown) may be formed at the front surface110A of the substrate110. In some embodiments, the isolation structures may include shallow trench isolation (STI) structures. In some embodiments, the STI structures may be formed by patterning the front surface110A of the substrate110to form trenches in the substrate110and filling the trenches with suitable dielectric materials to form the STI structures. The dielectric materials may include silicon oxides. In some embodiments, the substrate110is patterned using suitable photolithography and etching process. In other embodiments, the isolation structures132may include various doped regions formed using suitable implantation processes. In some embodiments, an isolation layer134may be formed in the contact pad region106and the alignment mark region108. The isolation layer134may be formed simultaneously with the isolation structures. In some other embodiments, the isolation structures may be omitted.

An interconnect structure150may be formed on the front surface110A of the substrate110, thereby forming electrical circuits with the photosensitive pixels. The interconnect structure150may include an ILD layer152and/or IMD layers154containing conductive features (e.g., conductive lines and vias including copper, aluminum, tungsten, combinations thereof, and the like) formed using any suitable method, such as damascene, dual damascene, or the like. For example, the interconnect structure150include a conductive line154M as shown inFIG.1. The ILD layer152and IMD layers154may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the ILD layer152and IMD layers154may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, formed by any suitable method, such as spinning, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like.

In some embodiments, prior to the formation of the interconnect structure150, one or more active and/or passive devices may be formed on the front surface110A of the substrate110in addition to the photosensitive pixels including the photosensitive regions, the transfer gate transistors (not shown), and the floating diffusion capacitors (not shown). The one or more active and/or passive devices may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only and are not meant to limit the present disclosure in any manner. Other circuitry may be used as appropriate for a given application.

As shown inFIG.2, the structure ofFIG.1is flipped and optionally bonded to a carrier substrate (not shown) such that the front surface110A of the substrate110faces the carrier substrate and the back surface110B of the substrate110is exposed for further processing. In some embodiments, the carrier substrate may provide mechanical support for processing steps performed on the back surface110B of the substrate110. In some embodiments, the carrier substrate may be formed of silicon or glass and may be free from electrical circuitry formed thereon. In such embodiments, the carrier substrate provides temporary support and is de-bonded from the image sensor device100after completing the process steps performed on the back surface110B of the substrate110. In other embodiments, the carrier substrate may include a semiconductor substrate, one or more active devices (not illustrated) on the semiconductor substrate, and an interconnect structure (not illustrated) over the one or more active devices. In such embodiments, in addition to providing the mechanical support, the carrier substrate may provide additional electrical functionality to the image sensor device100depending on design requirements.

After flipping over the structure, a thinning process may be performed on the back surface110B of the substrate110to thin the substrate110. In some embodiments, the thinning process serves to allow more light to pass through from the back surface110B of substrate110to the photosensitive regions of the photosensitive pixels without being absorbed by the substrate110. The thinning process may be implemented by using suitable techniques such as grinding, polishing, and/or chemical etching.

As shown inFIG.3, the back surface110B of the substrate110is patterned to form plural trenches110T in the substrate110. In some embodiments, the back surface110B of the substrate110is patterned using a suitable anisotropic wet etching process, while using a patterned mask (e.g., photoresist or a non-photosensitive material, such as silicon nitride) as an etch mask. In some embodiments in which the substrate110is formed of silicon, the anisotropic wet etch may be performed using potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or similar. The patterned mask may be removed after the etching process. In some embodiments in which the patterned mask is formed of a photoresist, the patterned mask may be removed using an ashing process followed by a wet clean process. In other embodiments in which the patterned mask is formed of a non-photosensitive material, the patterned mask may be removed using a suitable etching process.

As shown inFIG.4, after forming the trenches110T, a dielectric layer160is formed on the back surface110B of the substrate110, thereby filling the trenches110T. The dielectric layer160may include a charge accumulation layer162conformally formed on the back surface110B of the substrate110and a buffer layer164over the charge accumulation layer162.

In some embodiments, the charge accumulation layer162may include one or plural high-k dielectric materials. For example, the charge accumulation layer162may include a HfO2layer and a Ta2O5layer over the HfO2layer. The charge accumulation layer162helps to accumulate negative or positive charges in the substrate110to an interface between the charge accumulation layer162and the substrate110to form electric dipoles, which functions as a carrier barrier to trap defects such as dangling bonds. The configuration of the charge accumulation layer162may reduce leakage current of the image sensor devices.

In some embodiments, the buffer layer164may be formed of silicon oxide, although other suitable dielectric materials may be used. In some embodiments, the buffer layer164may be formed using ALD, CVD, PECVD, the like, or a combination thereof. In some embodiments, the charge accumulation layer162and the buffer layer164is planarized using a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or the like. Through the configuration, portions of the layers162and164in the trenches110T of the substrate110form the isolation structures160I between neighboring photosensitive pixels. The isolation structures160I may prevent electrical cross-talk between the photosensitive pixels. The isolation structures160I may be referred to as backside deep trench isolation (BDTI) structures. In some other embodiments, the charge accumulation layer162may be omitted.

As shown inFIG.5, the dielectric layer160is patterned to form one or more openings160T1and160T2that expose the back surface110B of the substrate110in the BLC region104and the alignment mark region108, respectively. In some embodiments, the dielectric layer160may be patterned using suitable photolithography and etching processes. For example, a photoresist is coated over the dielectric layer160and then patterned using photolithography techniques to expose portions of the dielectric layer160in the BLC region104and the alignment mark region108. Subsequently, an etching process is performed to remove the exposed portions of the dielectric layer160, thereby exposing the underlying substrate110.

As shown inFIG.6, a light blocking layer170is formed over the dielectric layer160. The light blocking layer170may be a metal layer. In some embodiments, the light blocking layer170is made of a reflective metal material or a light absorption material. For example, the light blocking layer170may include Cu, Au, Ag, Al, Ni, W, alloys thereof, or the like and may be formed using PVD, plating, or the like. In some embodiments, prior to the formation of the light blocking layer170, a barrier/adhesion layer (not shown) may be conformally formed over the dielectric layer160. The barrier/adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, or multilayers thereof and may be formed using PVD. CVD, MOCVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), electroplating and/or the like. The light blocking layer170made of an electrically conductive material. In some embodiments, the light blocking layer170located in the BLC region104may include grooves corresponding to the openings160T1. The grooves may be formed in a top surface of the light blocking layer170.

As shown inFIG.7, the light blocking layer170(FIG.6) is patterned into a light blocking grid172in the pixel array region102, a light blocking structure174in the BLC region104, and a light blocking structure178in the alignment mark region108. The patterning process may include suitable photolithography and etching processes. For example, a patterned mask (e.g., photoresist) is formed over the light blocking layer170and exposing portions of the light blocking layer170in the pixel array region102and a portion of the light blocking layer170in the contact pad region106. Subsequently, an etching process is performed to remove the exposed portions of the light blocking layer170. The etching process may include wet etch, dry etch, or the combination thereof. For example, the etching process may include a dry etch using gas etchants such as Cl2, HBr, CF4, or the like. The etching process may be performed until the dielectric layer160is exposed. In some embodiments, the exposed portions of the dielectric layer160may be consumed by the etching process and thus are recessed to fall below the lateral interface between the light blocking layer170and the dielectric layer160. Through the patterning process, the dielectric layer160is exposed through the openings170O1and170O2in the light blocking layer170. In some embodiments, in the etching process, the BLC region104and the alignment mark region108are protected from etching, and the layers therein are not etched.

The light blocking structure174in the BLC region104blocks the light that otherwise would be received by the reference photosensitive pixels. The light blocking structure174may be electrically coupled to the substrate110, for example, the light blocking structure174is in contact with the back surface110B of the substrate110. Such electrical coupling provides grounding. The grounding may release unwanted charges in the BLC region104. In some embodiments, the light blocking structure174may be a ring-shaped structure in a top view that laterally surrounds or encircle the pixel array region102.

The light blocking grid172has the openings170O1aligned with respective photosensitive pixels. For example, in some embodiments, walls of the light blocking grid172may encircle each active photosensitive pixel as viewed from top. Through the configuration, the light blocking grid172prevents optical cross-talk between neighboring active photosensitive pixels.

The light blocking structure178located in the alignment mark region108may be referred to as an alignment mark (e.g., a scribe lane primary mark (SPM) or an overlay (OVL) mark). In some embodiments, the light blocking structure178may include grooves corresponding to the openings160T2. For example, grooves formed in light blocking structure178allow for alignment correction to detect misalignment during a photolithography process. In alternative embodiments, the entirety of the light blocking layer170in alignment mark region108is removed by the patterning process.

As shown inFIG.8, a dielectric layer180is formed over the light blocking grid172, the light blocking structures174,178, and the dielectric layer160. In some embodiments, the dielectric layer180may be formed using similar materials and methods as the buffer layer164described above with reference toFIG.4and the description is not repeated herein. In some embodiments, the dielectric layer180and the buffer layer164may be formed of the same material. In other embodiments, the dielectric layer180and the buffer layer164may be formed of different materials. Subsequently, the dielectric layer180is planarized using a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or the like.

As shown inFIG.9, an etching process is performed to remove a portion of the dielectric layer180, a portion of the dielectric layer160, and a portion of the substrate110in the contact pad region106, thereby forming an opening180O in the contact pad region106. The isolation layer134is exposed in the opening180O, as shown inFIG.9. Subsequently, a buffer oxide layer190is formed over a remaining portion of the dielectric layer180in the regions102,104,106, and108, and extends into the opening180O on the exposed portion of the isolation layer134, as shown inFIG.10.

As shown inFIG.11, the buffer oxide layer190and the underlying dielectric materials (e.g., the isolation layer134and the ILD layer152) in the contact pad region106are patterned to form openings180O1to expose the conductive lines154M of the interconnect structure150. The buffer oxide layer190and the underlying dielectric layer180in the BLC region104are also patterned to form an opening190O to expose the light blocking structure174. The patterning of materials in both regions104,106may be performed simultaneously.

Subsequently, a conductive layer192is formed on buffer oxide layer190in regions102,108, in the opening190O in the BLC region104, and in the openings180O,180O1in the contact pad region106, as shown inFIG.12. As shown inFIG.13, the conductive layer192is patterned to form a contact pad structure194. In some embodiments, the portions of the conductive layer192disposed in the pixel array region102and the alignment mark region108are removed, and the remaining conductive layer192, or the contact pad structure194, is disposed in the BLC region104and the contact pad region106. As described above, the light blocking structure174is in contact with the back surface110B of the substrate110, and such electrical coupling provides grounding that may release unwanted charges in the BLC region104. As shown inFIG.13, the portion of the contact pad structure194disposed in the BLC region104is in contact with the light blocking structure174. In some embodiments, the portion of the contact pad structure194disposed in the BLC region104fills the grooves formed in the top surface of the light blocking structure174. The portion of the contact pad structure194disposed in the BLC region104is in contact with the buffer oxide layer190and the dielectric layer180. The portion of the contact pad structure194located in the contact pad region106is electrically coupled to the exposed conductive lines154M and electrically isolated from the sidewall of the substrate110by the buffer oxide layer190. The portion of the contact pad structure194located in the contact pad region106is used for forming an electrical connection, such as a wire bonding (not shown), to electrically couple to the circuits and the photosensitive pixels. The portion of the contact pad structure194located in the contact pad region106may be coupled to the photosensitive pixels through interconnect structure150.

Subsequent processes may be performed to form the image sensor device100. For example, a color filter layer (not shown) may be formed over the dielectric layer180in the pixel array region102. In some embodiments, the color filter layer includes plural color filters, aligned with respective active photosensitive pixels. The color filters may be used to allow specific wavelengths of light to pass while reflecting other wavelengths, thereby allowing the image sensor device100to determine the color of the light being received by the active photosensitive pixels. For example, the color filters may be a red, green, and blue filter as used in a Bayer pattern. Other combinations, such as cyan, yellow, and magenta, may also be used. The number of different colors of the color filters may also vary. The color filters may include a polymeric material or resin, such as polymethyl-methacrylate (PMMA), polyglycidyl-methacrylate (PGMA), or the like, which includes colored pigments.

The portion of the contact pad structure194disposed in the BLC region104provides a location to apply a negative voltage to the ground, such as from about 0 v to −0.5 v. As shown inFIG.14, during operation of the image sensor device100with reduced power supply, such as 2.5 v reduced from 3.0 v, a probe196is inserted into the image sensor device100and in contact with the portion of the contact pad structure194disposed in the BLC region104, and the negative voltage applied to the ground by the probe196can increase the FWC by increasing energy barrier when the transfer gate (TG) is off.FIGS.15A and15Billustrates the effect of applying −0.5 v voltage to the ground with the reduced power supply. As shown inFIGS.15A and15B, when −0.5 v voltage is applied to the ground, the electrical potential is increased, which means the FWC is increased.

Referring back toFIG.14, in some embodiments, the light blocking structure174includes portions174A extending through the dielectric layer160and in contact with the substrate110. In some embodiments, the light blocking structure174includes a plurality of portions174A in contact with the substrate110. As shown inFIGS.16A and16B, the portions174A of the light blocking structure174, which are shown in dashed lines because the portions174A are located below the contact pad structure194, may be arranged in a matrix. The remaining portion of the light blocking structure174is omitted for the sake of clarity. In some embodiments, each portion174A has a diameter ranging from about 1 micron to about 10 microns. As shown inFIG.16A, a distance D1between adjacent portions174A in the X direction ranges from about 0.5 microns to about 20 microns, and a distance D2between adjacent portions174A in the Y direction ranges from about 1 micron to about 10 microns. In some embodiments, as shown inFIG.16A, the portion of the contact pad structure194located in the BLC region104may have an oval or circular shape and may surround the plurality of portions174A. In some embodiments, the portion of the contact pad structure194located in the BLC region104may have a rectangular shape and may surround the plurality of portions174A. The portions174A may have any suitable shape and be arranged in any suitable pattern. The portion of the contact pad structure194located in the BLC region104may have any suitable shape.

FIGS.17and18illustrates a method for forming an image sensor device100at various intermediate stages of manufacturing, in accordance with alternative embodiments. As shown inFIG.17, instead of the plurality of openings160T1, one or more larger openings160T3are formed in the dielectric layer160. Next, as shown inFIG.18, the light blocking structure174is formed in and over the dielectric layer160in the BLC region104. The light blocking structure174includes one or more portions174B, which is substantially larger than the portion174A. Other portions of the image sensor device100may be substantially the same as the image sensor device100shown inFIG.13. As shown inFIG.17, the portion174B is in contact with the substrate110. The light blocking structure174includes a recess in the top surface, and the portion of the contact pad structure194located in the BLC region104fills the recess in the top surface of the light blocking structure174.

FIGS.19A and19Billustrate top views of a portion of the contact pad structure194disposed over the light blocking structure174of the image sensor device100ofFIG.18, in accordance with some embodiments. As shown inFIGS.19A and19B, the portions174B of the light blocking structure174are shown in dashed lines because the portions174B are located below the contact pad structure194. The remaining portion of the light blocking structure174is omitted for the sake of clarity. As shown inFIG.19A, in some embodiments, the portion174B has an oval or circular shape, and the portion of the contact pad structure194located in the BLC region104has a similar shape as the portion174B. The dimension of the portion of the contact pad structure194may be substantially larger than the dimension of the portion174B. As shown inFIG.19B, in some embodiments, the portion174B has a rectangular shape, and the portion of the contact pad structure194located in the BLC region104has a similar shape as the portion174B. The dimension of the portion of the contact pad structure194may be substantially larger than the dimension of the portion174B. The shapes of the portion of the contact pad structure194located in the BLC region104and the portion174B of the light blocking structure174may be substantially the same, as shown inFIGS.19A and19B. In some embodiments, the shapes of the portion of the contact pad structure194located in the BLC region104and the portion174B of the light blocking structure174are substantially different.

FIGS.20A and20Billustrate top views of a portion of the image sensor device100, in accordance with some embodiments. As shown inFIGS.20A and20B, the image sensor device100includes the pixel array region102, which is surrounded by the BLC region104, which is surrounded by the contact pad region106. As shown inFIG.20A, the plurality of portions174A of the light blocking structure174are located in the BLC region104. The remaining portion of the light blocking structure174is omitted for the sake of clarity. A plurality of contact pad structures194are disposed over the portions174A of the light blocking structure174. Each contact pad structure194is disposed in both the BLC region104and the contact pad region106. In some embodiments, each contact pad structure194is a continuous layer extending from the contact pad region106into the BLC region104. The shape of the contact pad structure194may vary, as shown inFIGS.20A and20B. In some embodiments, the shape of the portion of the contact pad structure194in the contact pad region106is the same as the shape of the portion of the contact pad structure194in the BLC region104, as shown inFIGS.20A and20B. In some embodiments, the shape of the portion of the contact pad structure194in the contact pad region106is different from the shape of the portion of the contact pad structure194in the BLC region104. In some embodiments, multiple contact pad structures194having different shapes are formed in the BLC region104and the contact pad region106, as shown inFIGS.20A and20B. In some embodiments, multiple contact pad structures194having the same shape are formed in the BLC region104and the contact pad region106.

As shown inFIG.20B, in some embodiments, the light blocking structure174includes both the portions174A and174B. For example, in the areas in the BLC region104where the contact pad structures194are located, the portions174B are formed in order to increase the contact area to the substrate110. In other areas of the BLC region104where no contact pad structures194are formed, the portions174A are formed.

The present disclosure provides the image sensor device100and the method of forming the same. In some embodiments, the image sensor device100includes a contact pad structure194extending from the contact pad region106to the BLC region104. The portion of the contact pad structure194in the BLC region104is electrically connected to the substrate110. Some embodiments may achieve advantages. For example, during operation, a probe196is inserted into the image sensor device100and in contact with the portion of the contact pad structure194disposed in the BLC region104, and a negative voltage applied to the ground by the probe196can increase the FWC by increasing energy barrier when the transfer gate (TG) is off.

An embodiment is an image sensor device. The device includes a substrate, a contact pad structure extending from a contact pad region to a black level correction region, a dielectric layer disposed over the substrate in the black level correction region, and a light blocking structure disposed on and through the dielectric layer in the black level correction region. A first portion of the contact pad structure disposed in the black level correction region is in contact with the light blocking structure, and the light blocking structure is in contact with the substrate.

Another embodiment is a method. The method includes forming one or more trenches in a pixel array region of a substrate, depositing a first dielectric layer over the substrate and in the one or more trenches, forming one or more openings in the first dielectric layer, depositing a light blocking layer over the first dielectric layer and in the one or more openings, and patterning the light blocking layer to form a light blocking structure in a black level correction region. The light blocking structure is in contact with the substrate. The method further includes forming a first opening in the first dielectric layer and the substrate in a contact pad region, depositing a conductive layer over the substrate and in the first opening, and patterning the conductive layer to form a contact pad structure. The contact pad structure extends from the contact pad region to the black level correction region.

A further embodiment is a method. The method includes depositing a first dielectric layer over a substrate, and the first dielectric layer is deposited in the pixel array region, the black level correction region, the contact pad region, and the alignment mark region. The method further includes forming openings in the first dielectric layer in the black level correction region and the alignment mark region, depositing a light blocking layer over the first dielectric layer and in the openings, removing portions of the light blocking layer in the pixel array region and the contact pad region to form a light blocking grid in the pixel array region and light blocking structures in the black level correction region and the alignment mark region, and depositing a conductive layer in the pixel array region, the black level correction region, the contact pad region, and the alignment mark region. The conductive layer is in contact with the light blocking structure in the black level correction region. The method further includes removing portions of the conductive layer in the pixel array region and the alignment mark region to form a contact pad structure extending from the contact pad region to the black level correction region.