Wafer level shielding in multi-stacked fan out packages and methods of forming same

An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.

BACKGROUND

In an aspect of conventional packaging technologies, such as multi-stacked fan-out packages, redistribution layers (RDLs) may be formed over a die and electrically connected to active devices in a die. External input/output (I/O) pads such as solder balls on under-bump metallurgy (UBMs) may then be formed to electrically connect to the die through the RDLs. An advantageous feature of this packaging technology is the possibility of forming fan-out packages. Thus, the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.

In such packaging technologies, a molding compound may be formed around the die to provide surface area to support the fan-out interconnect structures. For example, RDLs typically include one or more polymer layers formed over the die and molding compound. Conductive features (e.g., conductive lines and/or vias) are formed in the polymer layers and electrically connect I/O pads on the die to the external I/O pads over the RDLs. The external I/O pads may be disposed over both the die and the molding compound.

DETAILED DESCRIPTION

Various embodiments include a device package having multiple device dies (e.g., logic dies, memory dies, and the like) stacked in different package layers. Fan-out redistribution layers (RDLs) are disposed between the dies and provide electrical connections between the dies. Conductive through inter-vias (TIVs) may also be disposed in each package layer, and a combination of the fan-out RDLs and the TIVs provide electrical connections from a first side of the device package (e.g., a side having external connectors such as solder balls) to an opposing side of the device package. When an electromagnetic interference (EMI) shield is formed on the opposing side of the device package, the TIVs in each tier provide an electrical ground connection from the external connectors, through the device package, to EMI shield. Thus, a grounded EMI shield may be formed in a multi-layered device package.

FIGS. 1 through 13Aillustrate cross-sectional views of various intermediary stages of manufacturing a device package180(seeFIG. 13A) according to some embodiments. Referring first toFIG. 1, a carrier substrate102is illustrated. Generally, carrier substrate102provides temporary mechanical and structural support various features (e.g., device dies, seeFIG. 4) during subsequent processing steps. In this manner, damage to the device dies is reduced or prevented. The carrier substrate102may comprise, for example, glass, silicon oxide, aluminum oxide, and the like.

Various layers may be formed over carrier substrate102. For example, a polymer layer104may be formed over carrier substrate102. Polymer layer104may comprise polybenzoxazole (PBO), for example, and polymer layer104in order to facilitate the removal of carrier substrate102from package wafer100in subsequent process steps (see e.g.,FIG. 1YY). A seed layer106is formed over polymer layer104, and seed layer106may comprises a conductive material, such as copper, which is formed by sputtering in an embodiment.

As further illustrated byFIG. 1, a patterned photoresist108is formed over seed layer106. Photoresist108may be patterned to include openings110by exposing photoresist108to light (e.g., ultraviolet light) using a photomask (not shown). Exposed or unexposed portions of photoresist108may then be removed depending on whether a positive or negative resist is used to form openings110. Openings110extend through photoresist108and expose portions of seed layer106. Openings110may then be filled with a conductive material112(e.g., in an electro-chemical plating process, electroless plating process, and the like) as illustrated byFIG. 2. Subsequently, as illustrated inFIG. 3, photoresist108may be removed in an ashing and/or wet strip process, leaving TIVs114over carrier102. Excess portions of seed layer106(e.g., portions of seed layer106not covered by TIVs114) may also be removed using a combination of photolithograph and etching, for example. In the resulting structure, top surfaces of TIVs114may or may not be substantially level. In the completed device package180(seeFIG. 13B), TIVs114are used to electrically connect an EMI shield formed over the package to ground. In some embodiments, TIVs114may have a pitch P1of about 60 μm or greater. It has been observed that by providing TIVs having larger dimensions (e.g., in the range described above), improved grounding connections can be provided by TIVs114to a subsequently formed EMI shield (e.g., EMI shield140, seeFIG. 12). However, in other embodiments (e.g., embodiments where having a smaller form factor), smaller TIVs114may be formed as well.

Next, inFIG. 4, dies200are attached to a carrier substrate102for further processing. In an embodiment, an adhesive die attach film202is used to attach dies200to carrier substrate102. The adhesive may be any suitable adhesive, such as an ultraviolet (UV) glue, or the like. Die200may be a semiconductor die and could be any type of integrated circuit, such as a processor, logic circuitry, memory, analog circuit, digital circuit, mixed signal, and the like. Die200may include a substrate, active devices, and an interconnect structure (not individually illustrated). The substrate may comprise, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

Active devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like may be formed at the top surface of the substrate. An interconnect structure may be formed over the active devices and the substrate. The interconnect structure may include inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD) layers containing conductive features (e.g., conductive lines and vias comprising copper, aluminum, tungsten, combinations thereof, and the like) formed using any suitable method. The ILD and IMDs may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the ILD and IMDs may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, formed by any suitable method, such as spinning, chemical vapor deposition (CVD), and plasma-enhanced CVD (PECVD). The interconnect structure electrically connects various active devices to form functional circuits within die200. The functions provided by such circuits may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of the present invention and are not meant to limit the present invention in any manner. Other circuitry may be used as appropriate for a given application.

I/O and passivation features may be formed over the interconnect structure. For example, contact pads204may be formed over the interconnect structure and may be electrically connected to the active devices through the various conductive features in the interconnect structure. Contact pads204may comprise a conductive material such as aluminum, copper, and the like. Furthermore, a passivation layer206may be formed over the interconnect structure and the contact pads. In some embodiments, the passivation layer206may be formed of non-organic materials such as silicon oxide, un-doped silicate glass, silicon oxynitride, and the like. Other suitable passivation materials may also be used. Portions of the passivation layer may cover edge portions of contact pads204.

Additional interconnect features, such as additional passivation layers, conductive pillars, and/or under bump metallurgy (UBM) layers, may also be optionally formed over contact pads204. For example, as illustrated byFIG. 4, conductive pillars210may be formed on and electrically connect to contact pads204, and a dielectric layer208may be formed around such conductive pillars210. The various features of dies200may be formed by any suitable method and are not described in further detail herein. Furthermore, the general features and configuration of dies200described above are but one example embodiment, and dies200may include any combination of any number of the above features as well as other features.

After dies200are attached to carrier substrate102, a molding compound116may be formed around dies200and TIVs114as illustrated byFIG. 5. Molding compound116may include any suitable material such as an epoxy resin, phenol resin, a thermally-set resin, and the like. In addition to these materials, molding compound116may or may not include various additive fillers, such as silicon oxide, aluminum oxide, boron nitride, and the like. Suitable methods for forming molding compound116may include compressive molding, transfer molding, liquid encapsulent molding, and the like. For example, molding compound116is shaped or molded using a molding tool (not illustrated) which may have a border or other feature for retaining molding compound116when applied. The molding tool may be used to dispense molding compound116around dies200/TIVs114to force molding compound116into openings and recesses, eliminating air pockets or the like. Molding compound116may be dispensed around dies200and TIVs114in liquid form. Subsequently, a curing process is performed to solidify molding compound116.

Molding compound116may be formed to initially extend over and cover top surfaces of dies200and TIVs114. Subsequently, a planarization process (e.g., a mechanical grinding, chemical mechanical polish (CMP), or other etch back technique) may be employed to remove excess portions of molding compound116over dies200. After planarization, connectors (e.g., conductive pillars210) of dies200are exposed, and top surfaces of molding compound116, TIVs114, and dies200may be substantially level. In a top down view of the resulting structure (not shown), molding compound116may encircle dies200and TIVs114.

FIG. 6illustrates the formation of RDLs118over molding compound116, TIVs114, and dies200. RDLs118may extend laterally past edges of dies200over a top surface of molding compound116. RDLs118may include conductive features120formed in one or more polymer layers122. Polymer layers122may be formed of any suitable material (e.g., polyimide (PI), polybenzoxazole (PBO), benzocyclobuten (BCB), epoxy, silicone, acrylates, nano-filled pheno resin, siloxane, a fluorinated polymer, polynorbornene, and the like) using any suitable method, such as, a spin-on coating technique, lamination, and the like.

Conductive features120(e.g., conductive lines120A and/or vias120B) may be formed in polymer layers122and electrically connect to dies200(e.g., through conductive pillars210) and TIVs114. The formation of conductive features120may include patterning polymer layers122(e.g., using a combination of photolithography and etching processes) and forming conductive features over and in the patterned polymer layer. For example, conductive features120may further include depositing a seed layer (not shown), using a mask layer (not shown) having various openings to define the shape of conductive features120, and filling the openings in the mask layer using an electro-chemical plating process, for example. The mask layer and excess portions of the seed layer may then be removed. Thus, RDLs118are formed over dies200and molding compound116. The number of polymer layers and conductive features of RDLs118is not limited to the illustrated embodiment ofFIG. 6. For example, RDLs118may include any number of stacked, electrically connected conductive features in multiple polymer layers. Thus, a first package tier100A is formed in a package wafer100. Package tier100A includes dies200, TIVs114, molding compound116, and fan-out RDLs118.

Next inFIG. 7, a second package tier100B is formed over first package tier100A in package wafer100. Package tier100B includes dies220; TIVs124adjacent dies220; molding compound126surrounding dies220and TIVs124; and fan-out RDLs128formed over dies220, TIVs124, and molding compound126. Dies220, TIVs124, molding compound126, and RDLs128may be substantially similar to dies200, TIVs114, molding compound116, and fan-out RDLs118, respectively, and may be formed in a substantially similar way as discussed above. For example, TIVs124may be formed over RDLs118using a patterned photoresist (not illustrated) to define a shape of TIVs124. Dies220may then be attached to a top surface of fan-out RDLs118between TIVs124using an adhesive layer221. Dies200and220may perform a same or different functions. In any embodiment, dies200are dynamic random access memory (DRAM) dies whereas dies220are system on chip (SoC) dies although dies200and200may provide different functions in other embodiments. Subsequently, molding compound126is formed around dies220and TIVs124, and RDLs128are formed over molding compound126, TIVs124, and dies220. In some embodiments, additional device layers (not shown), comprising semiconductor dies, TIVs, and fan-out RDLs, for example, may optionally be formed over package tier100B.

InFIG. 8, additional package features, such as external connectors132(e.g., BGA balls, C4 bumps, and the like) may be formed over RDLs128. Connectors132may be disposed on UBMs130, which may also be formed over RDLs128. Connectors132may be electrically connected to dies200and220by way of RDLs118and/or RDLs128. Connectors132may be used to electrically connect packages180(seeFIG. 13A) to other package components such as another device die, interposers, package substrates, printed circuit boards, a mother board, and the like, and at least a subset of connectors132may be used to electrically connect TIVs114to ground. Other connectors132may be used to provide ground, power, and/or signal lines to dies200and220.

Subsequently, carrier substrate102may be removed as illustrated inFIG. 9. As further illustrated inFIG. 9, an orientation of device package may be reversed to expose polymer layer104for further processing. In the reversed orientation, connectors132may be attached to a temporary support frame134(e.g., comprising a support tape) for further processing. The further processing may include exposing TIVs114through polymer layer104as illustrated byFIG. 10. In an embodiment, TIVs114are exposed by laser etching openings136in polymer layer104. As described above, TIVs114are electrically connected to connectors132by RDLs118, TIVs124, and RDLs128. Thus, an electrical connection pathway extending through package wafer100is provided by exposing TIVs114. Other methods for exposing TIVs114may also be used, such as, an etch back process or patterning polymer layer104prior to forming TIVs114as described in greater detail in subsequent paragraphs.

FIGS. 11 through 13Aillustrate the formation of an EMI shield and package singulation. First, inFIG. 11, step cut process is performed (e.g., using a mechanical saw) to partially saw between individual packages180(including dies200/220, corresponding portions of RDLs118/128, UBMs130, and connectors132) in package wafer100, for example, along scribe lines (not shown). The step cup process forms openings138extending between each package180. In some embodiments, openings138only extend partially through the package wafer to a depth D1of about 60 μm or less.

Next, inFIG. 12, EMI shield140is formed over a top surface of package wafer100using a conformal deposition process for example. In an embodiment, EMI shield140comprises a conductive material, such as, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, a metallic alloy (e.g., stainless steel), alloys thereof, or combinations thereof, and may be deposited by any suitable process, such as electroless plating, sputtering, CVD, or the like. In some embodiments, EMI shield140has a thickness T1of about 3 μm to about 10 μm although EMI shield140may have a different thickness in other embodiments. EMI shield140may be at least partially disposed in openings136, extend through polymer layer104, and contact TIVs114. EMI shield140may further partially fill openings138between individual device packages180. Thus, when the individual packages180are fully singulated (seeFIG. 13A), EMI shield140may be disposed on exterior sidewalls of the singulated package180. During formation of the EMI shield140, scatter shields142may be disposed at peripheral regions of package wafer100to prevent (or reduce) damage to support frame134. Thus, in some embodiments, EMI shield140may not be formed along exterior sidewalls100′ of the package wafer100prior to singulation. These packages180at the edge of the wafer without EMI shield140(sometimes referred to as ugly dies) may be subsequently discarded.

Subsequently, inFIG. 13A, individual packages180may be singulated along scribe lines (not shown) using a suitable die saw technique. For example, a die saw to cut through remaining portions of package wafer100exposed by openings138(seeFIG. 11). After singulation, packages180are sorted and stored, for example, in a tray144until further processing (e.g., bonding packages180to another package component). In the completed package100, various TIVs and RDLs (e.g., TIVs114, RDLs118, TIVs124, and RDLs128) in the package tiers (e.g., tiers100A and100B) provide an electrical grounding path through package180from external connectors132to EMI shield140. Thus, by including TIVs in each package layer, EMI shield140may be grounded in package180.

Furthermore, package180inFIG. 13Ais singulated using two separate sawing processes. For example, a first die saw partially cuts through package wafer100(seeFIG. 11), EMI shield140is formed over package wafer100(seeFIG. 12), and a second die saw separates package180from other packages in the wafer (seeFIG. 13A). In these embodiments, damage to external connectors132as a result of forming EMI shield140(e.g., backside scatter deposition) may be reduced due at least in part to the partial saw process, which exposes sidewalls of each individual package100without exposing connectors132.

In another embodiment, packages180may be singulated using a single die saw process, which may advantageously decrease manufacturing costs. In such embodiments, openings138may extend through package wafer100, and EMI shield140is subsequently formed on sidewalls and a top surface of packages180after singulation.FIG. 13Billustrates the resulting package180′. As illustrated byFIG. 13B, EMI shield140includes a bottom surface140A that extends past molding compound116/126and RDLs118/128. In contrast, molding compound116and RDLs128extend under bottom surface140A of EMI shield140in device package180ofFIG. 13A.

FIGS. 14 through 15illustrate forming an EMI shield in a package wafer300according to another embodiment. Package wafer300may be substantially similar to package wafer100where like reference numerals indicate like elements. The process steps prior to the package ofFIG. 14may be substantially similar to those described above with respect toFIGS. 1 through 9. However, in contrast to using laser etching to expose TIVs114, a suitable etch back technique may be used to remove polymer layer104(seeFIG. 9) and expose TIVs114in the illustrated embodiment. Subsequently, as illustrated byFIG. 15, a die saw operation may be performed along scribe lines, and EMI shield140may be deposited on package wafer300, for example. Because polymer layer104is removed, EMI shield140may be in contact with TIVs114as well as a top surface of molding compound116. In such embodiments, a top surface of EMI shield140may be substantially level. AlthoughFIG. 15illustrates a two-step package saw process (e.g., similar to the process illustrated byFIGS. 11 through 13A), other embodiments may include a one-step package saw process (e.g., similar toFIG. 13B).

Subsequently inFIG. 18, patterned photoresist108is formed over seed layer106. Photoresist108may be patterned to include openings110by photolithography as described above. Openings110may be aligned with openings150in polymer layer104. Next, inFIG. 19, openings110and150may be filled with a conductive material112(e.g., in an electro-chemical plating process, electroless plating process, and the like). Subsequently, as illustrated inFIG. 20, photoresist108may be removed in an ashing and/or wet strip process, leaving TIVs114over carrier102. Excess portions of seed layer106(e.g., portions of seed layer106not covered by TIVs114) may also be removed using a combination of photolithograph and etching, for example. In the resulting structure, TIVs114extend through polymer layer104.

After TIVs114are formed, additional processing as described above with respect toFIGS. 4 through 13Bmay be performed. For example, package tiers (e.g., tiers100A/100B) may be formed by attaching various device dies to carrier substrate102, encapsulating the dies/TIVs in a molding compound, forming fan-out RDLs, forming external connectors, singulating various packages, and forming an EMI shield over a top surface and extending at least partially along sidewalls of the package. The resulting device package400is illustrated inFIG. 21. As illustrated, TIVs114extend through polymer layer104to electrically connect EMI shield140. In the resulting package, a top surface of EMI shield140may be substantially level, and EMI shield140may be electrically connected to ground through TIVs114, RDLs118, TIVs114, RDLs128, and connectors132.

FIG. 22illustrates a process flow500for forming a device package according to some embodiments. In step502, TIVs (e.g., TIVs114) are formed over a polymer layer (e.g., polymer layer104) on a carrier substrate. In step504, various package features (e.g., device dies200/220, molding compound116/126, TIVs114/124, RDLs118/128, external connectors132) are also formed in the device package. In step506, the carrier is removed and an orientation of the device package is flipped so that the polymer layer is exposed. In step508, the TIVs are exposed through the polymer layer. Exposing the TIVs may include laser etching the polymer layer, removing the polymer layer (e.g., using an etch back process), or the like. In another embodiment, the polymer layer may be patterned prior to forming the TIVs, and the TIVs may be formed to extend through the polymer layer. In such embodiments, the TIVs may be exposed in step506(e.g., removing the carrier). In step510, the package is singulated and an EMI shield (e.g., EMI shield140) is formed over a top surface of the singulated package (e.g., either the fully singulated package or the partially singulated packaged). The EMI shield may be electrically connected to electrical ground by the TIVs, various RDLs, and the external connectors in the package.

Various embodiments include a package having device dies stacked in different package tiers. Fan-out RDLs are disposed between the dies and provide electrical connections between the dies. Conductive through inter-vias (TIVs) may also be disposed in each package tier, and a combination of the fan-out RDLs and the TIVs provide electrical connections from a first side of the device package (e.g., a side having external connectors such as solder balls) to an opposing side of the device package (e.g., a side having an EMI shield formed thereon). Thus, a grounded EMI shield may be formed in a multi-layered device package.

In accordance with an embodiment, a device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.

In accordance with another embodiment, a device package includes a first package tier including a first device die, a first molding compound extending along sidewalls of the first device die, and first conductive through inter-vias (TIVs) extending through the first molding compound. The device package also includes fan-out redistribution layers (RDLs) over the first package tier and a second package tier over the fan-out RDLs. The second package tier includes a second device die, a second molding compound extending along sidewalls of the second device die, and second conductive TIVs extending through the second molding compound. The device package also includes an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the second package tier, wherein the EMI shield contacts the second conductive TIVs. The first conductive TIVs, the fan-out RDLs, and the second conductive TIVs electrically connect the EMI shield to ground.

In accordance with yet another embodiment, a method for forming a device package includes forming conductive through inter-vias (TIVs) over a carrier substrate and attaching a device die to the carrier substrate. The device die is disposed between adjacent ones of the conductive TIVs. The method also includes forming a molding compound around the device die and the conductive TIVs, exposing the conductive TIVs, and forming an electromagnetic interference (EMI) shield over the device die and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIVs, and the conductive TIVs electrically connect the EMI shield to external connectors formed on an opposing side of first device die as the EMI shield.