ALTERNATING SACRIFICIAL LAYER MATERIALS FOR MECHANICALLY STABLE 2D NANORIBBON ETCH

Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of semiconductor structures and processing and, in particular, to alternating sacrificial layers that are etch selective to each other in order to provide mechanical support for 2D nanoribbon transistor architectures.

BACKGROUND

Variability in conventional and currently known fabrication processes may limit the possibility to further extend them into the 10 nanometer node or sub-10 nanometer node range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors and gate-all-around (GAA) transistors, have become more prevalent as device dimensions continue to scale down. Tri-gate transistors and GAA transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure.

Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

DESCRIPTION OF THE EMBODIMENTS

Embodiments described herein comprise alternating sacrificial layers that are etch selective to each other in order to provide mechanical support for 2D nanoribbon transistor architectures. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Transition metal dichalcogenides (TMDs) have been an area of investigation in order to continue scaling transistor devices to smaller process nodes. For example, TMD channels enable aggressive scaling of channel length to below 10 nm. The use of TMDs for the channel is not without issue. Primarily, it has been shown that the TMD channels are susceptible to mechanical damage due to their thin, layered, nature and may be damaged during channel release and gate stack deposition processes. That is, the TMD channels (which may be only one monolayer or several monolayers thick) are unsupported along their length between the source region and the drain region. Without support, the capillary forces may act on the channels and cause damage or otherwise non-functional transistors. As such, it is difficult to form vertical stacks of multiple TMD channels.

An example, of such a process is shown inFIGS.1A-1C. InFIG.1A, a transistor device100includes source/drain regions120that are provided on opposite ends of semiconductor channels130that are formed over a substrate101. The channels130may be nanoribbon or nanowire channels. For example, the semiconductor channels130may be TMD material. The channels130are supported from above and below by a sacrificial layer132. Spacers125may be outside of the sacrificial layer132, and the channels130pass through the spacers125.

Referring now toFIG.1B, a cross-sectional illustration of the transistor device100after the sacrificial layers132are removed to form openings141is shown. The removal of the sacrificial layers132may be done with an etching process that does not significantly attack the channels130. As shown, the channels130have a relatively long span between the source/drain regions120. Due to their small thickness (in the vertical direction ofFIG.1), the channels130are susceptible to mechanical damage. For example, capillary forces from the etchant may bend, break, stress, strain, delaminate, or otherwise damage the channels130. In some instances, adjacent channels130may be brought into contact with each other. Then, inFIG.1C, a gate stack150is applied around the channels130. The gate stack150may include a gate dielectric151and a gate metal152. In cases with damaged channels130, the gate stack150may be improperly formed and lead to non-working or defective transistors100.

Accordingly, embodiments disclosed herein include a process that provides constant support to the semiconductor channels. This is done by providing a pair of sacrificial layers. The first sacrificial layers and the second sacrificial layers are alternated with each other. Additionally, the sacrificial layers are etch selective to each other. As such, the first sacrificial layers may be etched leaving the second sacrificial layers to support the channels. A first part of the gate stack may then be formed in place of the first sacrificial layers. Then, the second sacrificial layers are removed, and the channels are supported by first portion of the gate stack. The second portion of the gate stack can then be formed in place of the second sacrificial layers. In this way, the channels are mechanically supported through the entire process.

Referring now toFIG.2A, a cross-sectional illustration of a transistor device200is shown, in accordance with an embodiment. In an embodiment, the transistor device200is a non-planar transistor device formed over a substrate201. More particularly, the transistor device200may be a gate-all-around (GAA) device. In an embodiment, the transistor device200comprises a stack of semiconductor channels230. For example, four channels230are shown inFIG.2A. Though, it is to be appreciated that any number of channels230(e.g., one or more) may be included in the transistor device200.

In an embodiment, the substrate201may comprise any substrate material. In an embodiment, the underlying substrate201represents a general workpiece object used to manufacture integrated circuits. In an embodiment, the substrate201may comprise a semiconductor substrate201. The semiconductor substrate201often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates201include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials, such as substrates including germanium, carbon, or group III-V materials.

In a particular embodiment, the semiconductor channels230may be a transition metal dichalcogenide (TMD) semiconductor material. TMD materials typically take the form of MX2, where M is transition metal atom (e.g., Mo, W, etc.), and X is a chalcogen atom (e.g., S, Se, or Te). Typically, a layer of M atoms are sandwiched between layers of chalcogen atoms. TMD materials may generally be considered a 2D material. Other 2D semiconductor materials may also be used in some embodiments disclosed herein. The TMD semiconductor material may be a single layer (i.e., a layer of the M atom sandwiched between two X atom layers) or multiple layers thick. The channels230may have any form factor. For example, the channels230may include nanoribbon channels230or nanowire channels230. A nanoribbon channel refers to a structure that has one confined dimension (e.g., a small thickness compared to a length and a width of the channel), and a nanowire channel refers to a structure that has two confined dimensions (e.g., a small thickness and a small width, compared to a length of the channel). In a particular embodiment, the confined dimension (or dimensions) may have values of approximately 5 nm or smaller, or approximately 1 nm or smaller. As used herein, “approximately” may refer to a range of values that are within ten percent of the stated value. For example, approximately 1 nm may include a range from 0.9 nm to 1.1 nm. The use of TMD semiconductor materials allows for aggressive scaling of the transistor device200. For example, channel lengths may be approximately 10 nm or smaller.

While TMD material and other 2D semiconductor materials are described in greater detail herein, it is to be appreciated that three dimensional (3D) semiconductor materials may also be used in order to form the transistor device200. For example, the channels230may comprise silicon, silicon germanium, or the like.

In an embodiment, the channels230may pass through a pair of spacers225. The ends of the channels230may be substantially coplanar with the outer surfaces of the spacers225. In an embodiment, the spacers225may be any suitable spacer material. In one instance the spacers225may comprise silicon, oxygen, and carbon (e.g., SiOC) or aluminum and oxygen (e.g., a-Al2O3). In an embodiment, source/drain regions220may be provided on outside surfaces of the spacers225. In an embodiment, the source/drain regions220may include contact metals, such as tungsten, other metals, or other alloys. In other embodiments, the source/drain regions220may comprise epitaxially grown material, such as a metallic phase of the TMD channel. In an embodiment, the source/drain regions220may comprise metallic phase TMD material and contact metals. As used herein source/drain regions220may refer to either a source region or a drain region. That is, source/drain regions220are not both a source region and a drain region. For example, inFIG.2A, the source/drain region220on the left may be a source region, and the source/drain region220on the right may be a drain region.

In an embodiment, sacrificial layers234and232may be provided around the channels230. Particularly, first sacrificial layers234and second sacrificial layers232may be provided in an alternating pattern around the channels230. For example, a second sacrificial layer232may be below a bottommost channel230and a first sacrificial layer234may be provided over the bottommost channel230. That is, each channel230may be contacted by both a first sacrificial layer234and a second sacrificial layer232. As such, the sacrificial layers234and232can be selectively removed while maintaining mechanical support to the channels230, as will be described in greater detail below. The first sacrificial layers234and the second sacrificial layers232may be etch selective to each other. This allows for a first etchant to be used to remove the first sacrificial layers234without also removing the second sacrificial layers232.

Referring now toFIG.2B, a cross-sectional illustration of the transistor200after the first sacrificial layers234are removed is shown, in accordance with an embodiment. In an embodiment, the first sacrificial layers234may be removed with a first etching process. The first etching process may include an etchant chemistry that leaves the second sacrificial layers232substantially unaltered. Removing the first sacrificial layers234results in openings242being formed between the channels230. The openings242result in one surface (top or bottom) of each channel230being exposed. However, it is to be appreciated that each of the channels230remain mechanically supported by the second sacrificial layers232. As such, capillary forces do not damage the channels230.

Referring now toFIG.2C, a cross-sectional illustration of the transistor device after a first portion of the gate stack250is formed is shown, in accordance with an embodiment. In an embodiment, the first portion of the gate stack250may be formed in the openings242between the channels230. That is, the first portion of the gate stack250may replace the volume previously occupied by the first sacrificial layers234. In an embodiment, the gate stack250may comprise a gate dielectric251and a gate metal252.

In an embodiment, the gate metal252may include a workfunction metal and a fill metal. When the workfunction metal will serve as an N-type workfunction metal, the gate metal252preferably has a workfunction that is between about 3.9 eV and about 4.2 eV. N-type materials that may be used to form the gate metal252include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides that include these elements, i.e., titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide and aluminum carbide. When the workfunction metal will serve as a P-type workfunction metal, the gate metal252preferably has a workfunction that is between about 4.9 eV and about 5.2 eV. P-type materials that may be used to form the gate metal252include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.

Referring now toFIG.2D, a cross-sectional illustration of the transistor200after the second sacrificial layers232are removed is shown, in accordance with an embodiment. In an embodiment, the second sacrificial layers232may be removed with an etching process that does not substantially alter the gate stack250. Removal of the second sacrificial layers232results in openings243being formed. The openings243allow for surfaces (either top or bottom) of the channels230to be exposed. However, since the gate stack250is still present, the channels230remain mechanically supported. As such, capillary forces do not damage the channels230.

Referring now toFIG.2E, a cross-sectional illustration of the transistor200after the second portion of the gate stack250is formed is shown, in accordance with an embodiment. In an embodiment, the gate stack250may fill the openings243formed by the removal of the second sacrificial layers232. The gate stack250may include a gate dielectric251and a gate metal252. The gate dielectric251and the gate metal252may be substantially similar to the gate dielectric251and the gate metal252formed in the openings242. Accordingly, gate metal252is provided around the channels230. In the illustrated view, the gate metal252is above and below each of the channels230. However, it is to be appreciated that the gate metal252may also wrap around sides of the channels230(into and out of the plane ofFIG.2E) in order to provide gate-all-around (GAA) control of the channels230.

Referring now toFIG.3, a cross-sectional illustration of a transistor300is shown, in accordance with an embodiment. The transistor300may include a substrate301. A stack of channels330may be provided over the substrate301. The channels330may pass through spacers325to contact source/drain regions320. In an embodiment, a gate stack350is provided around the channels330within the spacers325. For example, the gate stack350may include a gate dielectric351and a gate metal352.

As shown inFIG.3, residual portions of the sacrificial layers334and332may be provided between the channels330. In a particular embodiment, the first sacrificial layer334is a different material than the second sacrificial layer332. Residual portions may remain due to incomplete etching of the sacrificial layers in previous operations. As shown, only a single type of the residual sacrificial layers334and332is provided between a given pair of channels330. For example, residual portions of the first sacrificial layer334are provided between the bottommost channel330and the second channel330, and residual portions of the second sacrificial layer332are provided between the second channel330and the third channel330.

Referring now toFIG.4is a perspective view illustration of a transistor400is shown, in accordance with an embodiment. In an embodiment, the transistor400is formed over a substrate401. An insulating layer470may be provided around the channels (not shown), the source/drain regions420, the spacers425, and the gate stack450.FIG.4illustrates access holes460Aand460Bthat are provided along sides of the channels. The access holes460Aand460Bmay be formed into the insulating layer470and provide access to the sacrificial layers that are removed with etching processes. After the sacrificial layers are removed, the access holes460Aand460Bmay be filled with the materials of the gate stack450(i.e., the gate dielectric451and the gate metal452.

The access holes460Aand460Bare formed with separate patterning and etching processes. As such, there will generally be some degree of misalignment between the first access hole460Aand the second access hole460B. For example, the second access hole460Bmay be shifted over (e.g., shifted towards the source/drain region420on the right) compared to the first access hole460A. In an embodiment, the offset between the access hole460Aand the access hole460Bmay be 1 nm or more. Though, smaller offsets may also be possible depending on the patterning processes used to form the access holes460. In addition to having an offset with each other, the size and/or shape of the offset holes460Aand460Bmay be different from each other.

While referred to as “access holes”, it is to be appreciated that the hole is through the insulating layer470. The structure that fills the access holes (i.e., the gate dielectric451and the gate metal452) may sometimes be referred to as extensions of the gate stack450. That is, the extensions may extend out laterally away from the edges of the channels of the transistor400.

In the embodiment shown inFIG.4, the first access hole460Aand the second access hole460Bmay have different architectures. For example, access hole460Ahas a gate dielectric layer451that lines an entire perimeter of the gate metal452, whereas the gate dielectric layer451of the access hole460Bonly lines a partial perimeter of the gate metal452. In other embodiments, the gate dielectric layer451may be similar for both the first access hole460Aand the second access hole460B.

Referring now toFIGS.5A-5E, a series of cross-sectional illustrations of the transistor500at various stages of manufacture is shown, in accordance with an embodiment. The plane illustrated inFIGS.5A-5Eis the plane of line5-5′ inFIG.4.

Referring now toFIG.5A, a cross-sectional illustration of the transistor500at a stage of manufacture is shown, in accordance with an embodiment. In an embodiment, the transistor500may comprise a substrate501, such as a silicon substrate or the like. In an embodiment, a stack of channels530are provided above the substrate501. The ends of the channels530may contact an insulator layer570. Additionally, sacrificial layers534and532may be provided between the channels530. For example, first sacrificial layers534and second sacrificial layers532may be provided in an alternating pattern around the channels530. The first sacrificial layers534may be a different material than the second sacrificial layers532. For example, the first sacrificial layers534may be etch selective to the second sacrificial layers532.

Referring now toFIG.5B, a cross-sectional illustration of the transistor500after a first access hole560A is formed and the first sacrificial layers534are removed is shown, in accordance with an embodiment. As shown, the first access hole560A is adjacent to edges of the channels530. The first access hole560A provides access to the first sacrificial layers534so that they may be etched with an etching chemistry that is selective to the second sacrificial layers532.

As shown, the channels530remain mechanically supported by the second sacrificial layers532. The channels530may also be connected to the source/drain regions and spacers (out of the plane ofFIG.5B). Accordingly, the channels530are not as susceptible to capillary forces that may otherwise damage the channels530.

Referring now toFIG.5C, a cross-sectional illustration of the transistor500after a first portion of the gate stack550is formed is shown, in accordance with an embodiment. In an embodiment, the gate stack550may comprise a gate dielectric551and a gate metal552. As shown, the gate dielectric551and the gate metal552may also fill the first access hole560A. Ends of the channels530may also be covered by the gate dielectric551in some embodiments.

Referring now toFIG.5D, a cross-sectional illustration of the transistor500after a second access hole560B is formed is shown, in accordance with an embodiment. The second access hole560B may be formed on the opposite side of the channels530from the first access hole560A. The second access hole560B provides access to remove the second sacrificial layers532with an etching process. After removal of the second sacrificial layers532, the channels530remain supported by the gate stack550, the source/drain regions, and the spacers. As such, the channels530are not susceptible to capillary forces that may damage the channels530.

Referring now toFIG.5E, a cross-sectional illustration of the transistor500after a second portion of the gate stack550is formed is shown, in accordance with an embodiment. As shown, gate dielectric551and gate metal552may fill the volume previously occupied by the second sacrificial layers532. The gate dielectric551and the gate metal552may also fill the second access hole560B. Accordingly, the gate stack550comprises gate structures around the channels530and extensions adjacent to the channels within the first access hole560A and the second access hole560B.

FIG.6illustrates a computing device600in accordance with one implementation of an embodiment of the disclosure. The computing device600houses a board602. The board602may include a number of components, including but not limited to a processor604and at least one communication chip606. The processor604is physically and electrically coupled to the board602. In some implementations the at least one communication chip606is also physically and electrically coupled to the board602. In further implementations, the communication chip606is part of the processor604.

The processor604of the computing device600includes an integrated circuit die packaged within the processor604. In an embodiment, the integrated circuit die of the processor may comprise a transistor device with channels that are mechanically supported throughout the manufacturing process, as described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip606also includes an integrated circuit die packaged within the communication chip606. In an embodiment, the integrated circuit die of the communication chip may comprise a transistor device with channels that are mechanically supported throughout the manufacturing process, as described herein.

In further implementations, another component housed within the computing device600may comprise a transistor device with channels that are mechanically supported throughout the manufacturing process, as described herein.

FIG.7illustrates an interposer700that includes one or more embodiments of the disclosure. The interposer700is an intervening substrate used to bridge a first substrate702to a second substrate704. The first substrate702may be, for instance, an integrated circuit die. The second substrate704may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. In an embodiment, one of both of the first substrate702and the second substrate704may comprise a transistor device with channels that are mechanically supported throughout the manufacturing process, in accordance with embodiments described herein. Generally, the purpose of an interposer700is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer700may couple an integrated circuit die to a ball grid array (BGA)706that can subsequently be coupled to the second substrate704. In some embodiments, the first and second substrates702/704are attached to opposing sides of the interposer700. In other embodiments, the first and second substrates702/704are attached to the same side of the interposer700. And in further embodiments, three or more substrates are interconnected by way of the interposer700.

The interposer700may include metal interconnects708and vias710, including but not limited to through-silicon vias (TSVs)712. The interposer700may further include embedded devices714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer700. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer700.

Thus, embodiments of the present disclosure may comprise a transistor device with channels that are mechanically supported throughout the manufacturing process.

Example 1: a transistor, comprising: a source region; a drain region; a first semiconductor channel between the source region and the drain region; a second semiconductor channel between the source region and the drain region over the first semiconductor channel; an insulator around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel; a first access hole in the insulator adjacent to a first edge of the first semiconductor channel; and a second access hole in the insulator adjacent to a second edge of the first semiconductor channel.

Example 2: the transistor of Example 1, wherein the first access hole and the second access hole are filled with a dielectric liner and a conductive material.

Example 3: the transistor of Example 1 or Example 2, wherein the first access hole is offset from the second access hole.

Example 4: the transistor structure of Example 3, wherein a sidewall of the first access hole is offset from a sidewall of the second access hole by 1 nm or more.

Example 5: the transistor of Examples 1-4, wherein a shape of the first access hole is different from a shape of the second access hole.

Example 6: the transistor of Examples 1-5, wherein the first semiconductor channel and the second semiconductor channel are nanoribbon channels or nanowire channels.

Example 7: the transistor of Example 6, wherein the first semiconductor channel and the second semiconductor channel comprises a transition metal dichalcogenide (TMD), wherein the TMD takes the form of MX2, where M is transition metal atom including molybdenum or tungsten, and wherein X is a chalcogen atom including sulfur, selenium, or tellurium.

Example 8: the transistor of Examples 1-7, wherein a remnant of a first sacrificial layer is between the first semiconductor channel and the second semiconductor channel, and wherein a remnant of a second sacrificial layer is above the second semiconductor channel, wherein the first sacrificial layer is etch selective to the second sacrificial layer.

Example 9: a transistor, comprising: a source region; a drain region; a semiconductor channel between the source region and the drain region; and a gate stack over the semiconductor channel, wherein the gate stack comprises a first extension along a first edge of the semiconductor channel and a second extension along a second edge of the semiconductor channel.

Example 10: the transistor of Example 9, wherein the first extension is offset from the second extension.

Example 11: the transistor of Example 10, wherein the first extension is offset from the second extension by 1 nm or more.

Example 12: the transistor of Examples 9-11, wherein a shape of the first extension is different than a shape of the second extension.

Example 13: the transistor of Examples 9-12, wherein the gate stack comprises: a dielectric liner; and a metal over the dielectric liner.

Example 14: the transistor of Example 13, wherein the first extension and the second extension are lined by the dielectric liner and are filled with the metal.

Example 15: the transistor of Examples 9-14, wherein the semiconductor channel is a nanoribbon channel or a nanowire channel.

Example 16: the transistor of Example 15, wherein the semiconductor channel comprises a transition metal dichalcogenide (TMD).

Example 17: the transistor of Examples 9-16, further comprising: a first sacrificial layer remnant above the semiconductor channel; and a second sacrificial layer remnant below the semiconductor channel, wherein the first sacrificial layer remnant is etch selective to the second sacrificial layer remnant.

Example 18: a method of forming a transistor, comprising: providing a plurality of semiconductor channels in a stack, wherein first sacrificial layers and second sacrificial layers are provided between the plurality of semiconductor channels; removing the first sacrificial layers with a first etching chemistry that leaves the second sacrificial layers; forming a first gate stack in the place of the first sacrificial layers; removing the second sacrificial layers with a second etching chemistry; and forming a second gate stack in the place of the second sacrificial layers.

Example 19: the method of Example 18, wherein the first sacrificial layers and the second sacrificial layers are provided in an alternating pattern.

Example 20: the method of Example 18 or Example 19, wherein the plurality of semiconductor channels are mechanically supported from above or below at all times.

Example 21: the method of Examples 18-20, wherein the plurality of semiconductor channels comprises a transition metal dichalcogenide (TMD), wherein the TMD takes the form of MX2, where M is transition metal atom including molybdenum or tungsten, and wherein X is a chalcogen atom including sulfur, selenium, or tellurium.

Example 22: the method of Example 21, wherein the plurality of semiconductor channels comprise transition metal dichalcogenide (TMD) material.

Example 23: an electronic system, comprising: a board; a package substrate coupled to the board; and a die coupled to the package substrate, wherein the die comprises a transistor, wherein the transistor comprises: a first semiconductor channel; a second semiconductor channel over the first semiconductor channel; a first remnant of a first sacrificial layer between the first semiconductor channel and the second semiconductor channel; and a second remnant of a second sacrificial layer under the first semiconductor channel, wherein the first sacrificial layer is different than the second sacrificial layer.

Example 24: the electronic system of Example 23, further comprising: a gate stack around the first semiconductor channel and the second semiconductor channel.

Example 25: the electronic system of Example 24, wherein the gate stack comprises a first extension along a first edge of the first semiconductor channel and a second extension along a second edge of the first semiconductor channel, wherein the first extension is offset from the second extension.