Semiconductor device having source field plate and method of manufacturing the same

A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119 to Chinese Patent Application No. 201510363973.6, filed on Jun. 26, 2015, in the State Intellectual Property Office of China, which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device.

BACKGROUND

In a High Electron Mobility Transistor (HEMT) device working under a high drain-source voltage, dense electric field lines are formed at an end of a gate electrode which is adjacent to a drain electrode, thus a high electric field peak is generated. Such a high electric field in a local region may result in a very large gate electrode leak current, and even lead to material breakdown and device failure, thus reducing a breakdown voltage of the device. The higher the electric field peak is, the smaller the bearable breakdown voltage of the device is. Meanwhile, as time passes, a dielectric layer or a semiconductor layer at a surface of the device may be degraded or denatured due to the high electric field, which reduces reliability and lifetime of the device. In this case, advantages of an HEMT device, e.g. being resistant of high temperature, high pressure and high frequency, are affected greatly. Therefore, in structure design and process development for a semiconductor device, it is required to reduce the electric field near the gate electrode so as to improve the breakdown voltage and thus reliability of the device.

SUMMARY

Aspects of the present invention are directed to a semiconductor device with improved reliability and performance and a method of manufacturing such a semiconductor device.

According to an aspect of the present invention, a semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

According to another aspect of the present invention, a method of manufacturing a semiconductor device comprises: forming a semiconductor layer on a prepared substrate; forming a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode on the semiconductor layer; and forming a source field plate on the semiconductor layer, the source field plate sequentially comprising: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

According to embodiments of the present invention, the first intermediate portion of the source field plate has an air bridge structure, in which air exists between the first intermediate portion and the semiconductor layer, which reduces parasitic gate-source capacitance and parasitic resistance. Meanwhile, the end portion of the source field plate is spaced apart from the semiconductor layer with air therebetween, which further reduces the parasitic gate-source capacitance and the parasitic resistance.

Furthermore, there is no air between the second intermediate portion of the source field plate and the semiconductor layer, thus the distance from the second intermediate portion to the strong electric field region near the gate electrode is not reduced, so the effect of modulation to the strong electric field by the source field plate is not or substantially not weakened.

In addition, in the above-described manufacturing method, the groove may be formed using the air bridge self-aligned lithography and etching process. With such a process, the position of the groove with respect to the semiconductor layer is automatically aligned with the positions of the source field plate and the gate source, which avoids alignment deviation caused by a separate lithography process forming the groove, thus improves yield and reduces manufacture costs.

DETAILED DESCRIPTION

In addition, when an element is referred to as being “on” another element, it can be directly on the other element or be indirectly on the other element with one or more intervening elements interposed therebetween. Also, when an element is referred to as being “connected to” another element, it can be directly connected to the other element or be indirectly connected to the other element with one or more intervening elements interposed therebetween.

In order to reduce strength of an electric field near a gate electrode of a semiconductor device, usage of field plates is widely employed. In detail, a field plate is disposed at an end of the gate electrode which is adjacent to a drain electrode and is connected to a source electrode or the gate electrode. In this way, an additional potential is generated in a gate-drain region, an area of a depletion region is increased, and a bearable voltage of the depletion region is increased. In addition, the field plate modulates dense electric field lines near the end of the gate electrode which is adjacent to the drain electrode to make distribution of the electric field lines more uniform, which decreases the strength of the electric field near the end of the gate electrode which is adjacent to the drain electrode, reduces gate electrode leak current and improves breakdown voltage of the device.

FIG. 1is a cross-sectional view schematically illustrating a semiconductor device according to the prior art. As shown inFIG. 1, a semiconductor device comprises: a substrate101; a nucleation layer102, a buffer layer103, a channel layer104and a barrier layer105sequentially stacked on the substrate101; a source electrode106and a drain electrode107formed on the barrier layer105, and a gate electrode108between the source electrode106and the drain electrode107; a first dielectric layer109formed on a part of the barrier layer105between the source electrode106and the gate electrode108and another part of the barrier layer105between the gate electrode108and the drain electrode107; a second dielectric layer110formed on the gate electrode108and the first dielectric layer109; and a source field plate111formed on the second dielectric layer110and connected to the source electrode106. An additional potential may be generated in the gate-drain region due to the source field plate111, thus an electric field peak near an end of the gate electrode108which is adjacent to the drain electrode107can be effectively suppressed, thereby improving breakdown voltage and reliability of the device.

However, in the semiconductor device described as above, the source field plate111directly covers the second dielectric layer110, the metal of the source field plate111having a large area completely overlaps the underlying gate electrode108and two-dimensional electron gas in a channel, thus parasitic gate-source capacitance Cgs is generated. The parasitic gate-source capacitance Cgs is inversely proportional to a distance between the source field plate111and the gate electrode108, and is proportional to the overlapping area between the source field plate111and the gate electrode108. In addition, the dielectric constant of the dielectric layer is relatively large, so a large parasitic gate-source capacitance Cgs will be generated during operation of the device, resulting in deterioration of the frequency characteristics of the device. Further, the source field plate111is generally connected to the lowest potential, which affects distribution of the two-dimensional electron gas below the source field plate111so that the two-dimensional electron gas is expanded to the channel layer. In this way, concentration of the two-dimensional electron gas in the channel is reduced, resulting in generation of parasitic resistance, so on-resistance is increased during operation of the device.

In order to reduce the parasitic gate-source capacitance Cgs and the parasitic resistance, a thickness of the dielectric layer can be increased. However, increase of the thickness of the dielectric layer will result in increase of distance between the source field plate111and the region with a strong electric field, which reduces the effect of modulation to the strong electric field. In addition, the process will become difficult if the dielectric layer is excessive thick, and often the thickness of the dielectric layer is specially designed and cannot be changed randomly.

In view of this, embodiments of the present invention provide a semiconductor device having reduced parasitic gate-source capacitance Cgs and reduced parasitic resistance while maintaining the effect of the modulation to the strong electric field.

Hereinafter semiconductor devices according to exemplary embodiments of the present invention will be described in detail with reference toFIGS. 2-12.

FIG. 2is a cross-sectional view schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.

As shown inFIG. 2, a semiconductor device comprises: a substrate11; a semiconductor layer12formed on the substrate11; a source electrode13, a drain electrode14and a gate electrode15between the source electrode13and the drain electrode14formed on the semiconductor layer12; and a source field plate19formed on the semiconductor layer12.

The source field plate19sequentially comprises a start portion191electrically connected to the source electrode13, a first intermediate portion192formed on the semiconductor layer12with air therebetween, a second intermediate portion193contacting a portion of the semiconductor layer12between the gate electrode15and the drain electrode14, and an end portion194formed on the semiconductor layer12with air therebetween. Since the second intermediate portion193is in direct contact with the semiconductor layer12, it means that no air exists between the second intermediate portion193and the semiconductor layer12. The source field plate19is made by an air bridge metal process using a metallic material. The thickness of the source field plate19can be determined and adjusted based on design requirements or process capability.

In an embodiment, the substrate11is formed of a material selected from a group consisting of gallium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon and combination thereof, or any other material which is capable of growing group III nitride.

The semiconductor layer12may be formed of a semiconductor material based on III-V group compounds. The semiconductor layer12may include a nucleation layer121formed on the substrate11. The nucleation layer121affects parameters, such as crystal quality, surface morphology and electrical properties, of heterojunction material located thereon, and acts as matching substrate material and semiconductor material layer in the heterojunction structure.

The semiconductor layer12may further comprise a buffer layer122formed on the nucleation layer121. The buffer layer122protects the substrate11from metal ions, and acts as bonding another semiconductor material layer grown thereon. The buffer layer122may be formed of one selected from AlGaN, GaN, AlGaInN and other III-nitride material.

The semiconductor layer12may further comprise a channel layer123formed on the buffer layer122and a barrier layer124formed on the channel layer123. The barrier layer124may be made of AlGaN. The channel layer123and the barrier layer124form a heterojunction structure together, a Two-Dimensional Electron Gas (2DEG) channel is formed at an interface of the heterojunction structure, as shown by the dotted line inFIG. 2. Here, the channel layer123provides a channel for movement of 2DEG, and the barrier layer124acts as a barrier.

The source electrode13and the drain electrode14on the barrier layer124are in contact with the 2DEG respectively. The gate electrode15is located on the barrier layer124and between the source electrode13and the drain electrode14, and may be a T shaped gate. When the gate electrode15is applied with an appropriate bias voltage, a current flows between the source electrode13and the drain electrode14through the 2DEG channel between the channel layer123and the barrier layer124.

The semiconductor device may further include a dielectric layer formed on the semiconductor layer12. In this case, the second intermediate portion193of the source field plate19is in direct contact with the dielectric layer. The dielectric layer may include a first dielectric layer16formed on the semiconductor layer12and a second dielectric layer17formed o the first dielectric layer16. In this case, the second intermediate portion193of the source field plate19is in direct contact with the second dielectric layer17, as shown inFIG. 2.

According to this embodiment, the first intermediate portion192of the source field plate19has an air bridge structure, in which the first intermediate portion192is not in direct contact with the dielectric layer on the gate electrode15, the source-gate region and a part of the gate-drain region. Instead, the first intermediate portion192is spaced apart from the dielectric layer and air having a very small dielectric constant exists therebetween, which reduces parasitic gate-source capacitance and parasitic resistance. Meanwhile, the end portion194of the source field plate19is not in contact with the dielectric layer on the gate-drain region, which further reduces the parasitic gate-source capacitance and the parasitic resistance.

Furthermore, the second intermediate portion193of the source field plate19is in direct contact with the dielectric layer, thus the distance from the second intermediate portion193to the strong electric field region near the gate electrode15is not reduced, so the effect of modulation to the strong electric field by the source field plate19is not or substantially not weakened.

In another embodiment, the dielectric layer may include only the first dielectric layer16, without the second dielectric layer17. In this case, the second intermediate portion193is in direct contact with the first dielectric layer16.

The dielectric layer acts as passivation and protection for the surface of the device, and may be formed of any one selected from SiN, SiO2, SiON, Al2O3, HfO2, HfAlOx and combination thereof.

In yet another embodiment, as shown inFIG. 3, the dielectric layer may be omitted. In this case, the second intermediate portion193is in direct contact with the barrier layer124, i.e., in direct contact with the semiconductor layer12.

FIG. 4is a cross-sectional view schematically illustrating a semiconductor device according to another exemplary embodiment of the present invention. The semiconductor device shown inFIG. 4is substantially the same as that shown inFIG. 2, except for a groove, thus repeated description will be omitted.

As shown inFIG. 4, in order to further strengthen the effect of modulation to the strong electric field by the source field plate19, a groove18is formed at a position in the dielectric layer corresponding to the position of the second intermediate portion193of the source field plate19in the horizontal direction, so that the second intermediate portion193of the source field plate19is located in the groove18. As an example, the dielectric layer comprises the first dielectric layer16and the second dielectric layer17, and the groove18is formed in the second dielectric layer17. In this way, the second intermediate portion193is closer to the strong electric field region, compared with the embodiment shown inFIG. 2, so the strong electric field can be modulated more effectively.

As another example, the dielectric layer may comprise the first dielectric layer16only, without the second dielectric layer17. In this case, as shown inFIG. 5, the groove18is formed in the first dielectric layer16. Compared with the embodiment shown inFIG. 4, the second dielectric layer17is omitted, it means that a portion of the second dielectric layer17on the gate region, the source-gate region and a part of the gate-drain region is replaced with air having the same thickness, which can further reduce the parasitic capacitance and parasitic resistance. Meanwhile, the groove18is etched in the first dielectric layer16, thus the second intermediate portion193located in the groove18is closer to the strong electric field region, compared with the embodiment shown inFIG. 4, therefore the electric field in the region between the gate electrode15and the drain electrode14can be modulated more effectively.

If intensity of the electric field near an end of the gate electrode15which is adjacent to the drain electrode14is very large, the etching depth of the groove18can be increased to achieve better modulation effect. Referring toFIG. 6, the semiconductor device comprises the first dielectric layer16formed on the semiconductor layer12and the second dielectric layer17formed on the first dielectric layer16. The groove18in which the second intermediate portion193is located is extended into the semiconductor layer12passing through the first dielectric layer16and the second dielectric layer17. With this structure, the distance from the second intermediate section193to the strong electric field region is closer, and the effect of modulation to the strong electric field is further enhanced.

Alternatively, the semiconductor device does not include the dielectric layer. In this case, as shown inFIG. 7, the groove18is located in the barrier layer124, i.e., in the semiconductor layer12. Compared with the embodiment shown inFIG. 6, the dielectric layer including the first dielectric layer16and the second dielectric layer17is omitted, it means that a portion of the dielectric layer on the gate region, the source-gate region and a part of the gate-drain region is replaced with air having the same thickness, which can further reduce the parasitic capacitance and the parasitic resistance. Meanwhile, the groove18is etched in the barrier layer124, thus the second intermediate portion193located in the groove18is closer to the strong field region, compared with the embodiment shown inFIG. 4, therefore the electric field in the region between the gate electrode15and the drain electrode14can be modulated more effectively.

Of course, although not shown, according to teaching from the embodiments shown inFIGS. 6 and 7, those skilled in the art can appreciate a case where the second dielectric layer17is omitted but the first dielectric layer16is remained on the basis of the embodiment shown inFIG. 6.

In the semiconductor devices shown inFIGS. 4-7, by forming the groove18, the distance from the second intermediate portion193of the source field plate19to the strong electric field region is shorter, which enables effective modulation to the electric field, increase of the breakdown voltage and reduction of the leak current.

The groove18may be etched by an air bridge self-aligned lithography and etching process, which will be described in detail later. With this process, the position of the groove18with respect to the semiconductor layer12is automatically aligned with the positions of the source field plate19and the gate source15, which avoids alignment deviation caused by a separate lithography process forming the groove18, thus improves yield and reduces manufacture costs.

FIGS. 8 and 9are cross-sectional views schematically illustrating semiconductor devices according other exemplary embodiments of the present invention. Each of the semiconductor devices shown inFIGS. 8 and 9is substantially the same as that shown inFIG. 4, except for shape of the second intermediate portion193, thus repeated description will be omitted.

As shown inFIG. 8, in this embodiment, a side wall of the groove18has a shape of an inclined surface, rather than a steep surface shown inFIG. 4. With this structure, electric field concentration effect occurring at a corner between the side wall and the bottom surface of the groove18can be reduced, and the breakdown electric field at the position can be reduced also. The specific tilt angle can be determined based on device design requirements and process capability.

Alternatively, as shown inFIG. 9, the side wall of the groove18has a shape of a curved surface. In this way, the transition between the side wall and the bottom surface of the groove18will be smoother compared with the embodiment shown inFIG. 8, thus the electric field concentration effect occurring at the corner between the side wall and the bottom surface of the groove18can be further reduced, and the breakdown electric field at the position can be further reduced also. The specific shape of the curved surface can be determined based on device design requirements and process capability.

FIG. 10is a cross-sectional view schematically illustrating a semiconductor device according to still another exemplary embodiment of the present invention. The semiconductor device shown inFIG. 10is substantially the same as that shown inFIG. 4, except for shape of the source field plate19, thus repeated description will be omitted.

As shown inFIG. 10, in this embodiment, if the intensity of the electric field inside the semiconductor device is not very high, the length of the end portion194of the source field plate19may be reduced to about zero, so as to substantially eliminate the parasitic gate-source capacitance and the parasitic resistance due to the end portion194of the source field plate19.

FIG. 11is a plan view schematically illustrating the semiconductor device shown in any ofFIGS. 4-10.

As shown inFIG. 11, the source field plate19has a fork-like structure, i.e. there are a plurality of first intermediate portions192branching off from the second intermediate portion193. In particular, there are a plurality of start portions191and a plurality of first intermediate portions192, each of the plurality of start portions191and each of the plurality of first intermediate portions192form an integral part respectively. The source field plate19comprise a plurality of such integral parts, and all of the integral parts are connected to the same second intermediate portion193, so as to form a fork-like structure. With this structure, the overlapping area between the source field plate19and the gate electrode15as well as the 2DEG channel may be decreased, which further reduces the parasitic gate-source capacitance and the parasitic resistance. The number and structure of the integral parts can be determined based on device design requirements and process capability.

FIG. 12is a plan view schematically illustrating a semiconductor device according to a modified embodiment ofFIG. 11.

As shown inFIG. 12, at least one of the plurality of first intermediate portions192has a concave shape in the longitudinal direction thereof, which further decreases the overlapping area between the source field plate19and the gate electrode15as well as the 2DEG channel, and further reduces the parasitic gate-source capacitance and the parasitic resistance.

Those skilled in the art can appreciate that the embodiments shown inFIGS. 11 and 12are examples only, and are not intended to limit the scope of this invention. For example, in the embodiments shown inFIGS. 11 and 12, the grooves18can be omitted. In this case, the second intermediate portion193of the source field plate19can be directly located on the semiconductor layer12or the dielectric layer.

In the semiconductor devices shown inFIGS. 2 to 12, the maximum height difference between the source field plate19and the semiconductor layer12may be in a range of about 0.5 μm to about 5 μm.

In addition, in the semiconductor devices shown inFIGS. 2 to 9, 11 and 12, the length of the end portion194of the source field plate19may be greater than about 0 μm and less than or equal to about 5 μm. Herein, the length of the end portion194of the source field plate19means the longitudinal length of the projection of the end portion194on the semiconductor layer12or the dielectric layer.

Next, a method of manufacturing a semiconductor device will be described with reference toFIGS. 13a-13e.

FIGS. 13a-13eare cross-sectional views schematically illustrating steps of a method of manufacturing the semiconductor device shown inFIG. 4.

First, as shown inFIG. 13a, a semiconductor layer12is formed on a prepared substrate11.

In particular, a nucleation layer121, a buffer layer122, a channel layer123and a barrier layer124are sequentially formed on the substrate11. Here, the channel layer123and the barrier layer124form a heterojunction structure, and 2DEG is formed at an interface of the heterojunction structure.

Next, referring toFIG. 13b, a source electrode13, a drain electrode14and a gate electrode15between the source electrode13and the drain electrode14are formed on the semiconductor layer12.

The source electrode13and the drain electrode14are in contact with the 2DEG at the interface of the heterojunction structure. The source electrode13and the drain electrode14can be formed using one of a high temperature annealing method, a heavy doping method and an ion implantation method.

Next, referring toFIG. 13c, a dielectric layer is formed on the semiconductor layer12.

The dielectric layer may include a first dielectric layer16formed on the semiconductor layer12and a second dielectric layer17formed on the first dielectric layer16. In particular, the first dielectric layer16is formed on a part of the barrier layer124between the source electrode13and the gate electrode15and another part of the barrier layer124between the gate electrode15and the drain electrode14. The second dielectric layer17is formed on the gate electrode15and the first dielectric layer16. The dielectric layer may be formed using a dielectric layer depositing process. The dielectric layer acts as passivation and protection for the surface of the device, and may be formed of any one selected from SiN, SiO2, SiON, Al2O3, HfO2, HfAlOx and combination thereof.

The thickness of the first dielectric layer16and the second dielectric layer17can be determined and adjusted based on the device design requirements.

Next, referring toFIG. 13d, a groove18is formed in the dielectric layer using an air bridge self-aligned lithography and etching process.

In particular, two photoresist arch structures21which are spaced apart from each other are formed in a source-drain region, i.e. between the source electrode13and the drain electrode14, of the device using an air bridge layout design and an air bridge lithography process. Then, etching process is performed directly to the dielectric layer, with the two photoresist arch structures21as a mask, so as to form the groove18between the two photoresist arch structures21. After completion of the etching process, the two photoresist arch structures21are remained. The process described above is referred as the air bridge self-aligned lithography and etching process. With such a process, the position of the groove18with respect to the semiconductor layer12is automatically aligned with the positions of the source field plate19and the gate source15, which avoids alignment deviation caused by a separate lithography process forming the groove18, thus improves yield and reduces manufacture costs.

A width and a depth of the groove18as well as a distance between the gate electrode15and the groove18can be determined and adjusted based on the device design requirements.

Finally, referring toFIG. 13e, a source field plate19is formed using an air bridge metal process.

The source field plate19sequentially comprises a start portion191electrically connected to the source electrode13, a first intermediate portion192formed on the second dielectric layer17with air therebetween, a second intermediate portion193contacting a portion of the second dielectric layer17between the gate electrode15and the drain electrode14, and an end portion194formed on the second dielectric layer17with air therebetween.

After forming the groove18, photoresist22is formed on the source electrode13, the drain electrode14and the two photoresist arch structures21using a lithography process, so as to define a coverage area of the source field plate19. Then, the source field plate19is formed on the area not covered by the photoresist22using one or combination of a metal electron beam evaporation process, a metal sputtering process and a metal plating process, with metal as the material. The source field plate19covers the groove18. The thickness and shape of the source field plate19can be determined and adjusted based on device design requirements or process capacity. Finally, the two photoresist arch structures21and the photoresist22are removed, so as to form the source field plate19having a projection which can be received in the groove18.

If the source field plate19is too close to the dielectric layer, the parasitic capacitance and the parasitic resistance will be increased. In other hand, if the source field plate19is too far from the dielectric layer, reliability of the air bridge structure will be affected. Thus a length, a thickness and a distance to the surface of the dielectric layer can be determined and adjusted based on the device design requirements.

In one embodiment, the maximum height difference between the source field plate19and the semiconductor layer12may be in a range of about 0.5 μm to about 5 μm.

In addition, the length of the end portion194of the source field plate19may be greater than about 0 μm and less than or equal to about 5 μm.

A method for manufacturing the semiconductor device shown inFIG. 4has been described as an example. Those skilled in the art will appreciate that the above-described method can be adjusted to manufacturing a semiconductor device according to another embodiment. For example, in the case of only the first dielectric layer16, the step of forming the second dielectric layer17can be omitted, the grooves18can be formed in the first dielectric layer16, or alternatively be formed in the semiconductor layer12passing through the first dielectric layer16. In the case of no dielectric layer, the step of forming the dielectric layer may be omitted, and the groove18may be formed directly in the semiconductor layer12. And in this case, the source field plate19is formed directly on the semiconductor layer12.

As another example, in the case of no groove, the step of forming the groove18can be omitted. In this case, if the dielectric layer comprises both of the first dielectric layer16and the second dielectric layer17, the second intermediate portion193of the source field plate19can be in direct contact with the second dielectric layer17. If the dielectric layer comprises the first dielectric layer16only, the second intermediate portion193of the source field plate19can be in direct contact with the first dielectric layer16. In contrast, if there is no dielectric layer, the second intermediate portion193of the source field plate19may be in direct contact with the semiconductor layer12.

In an embodiment of the present invention, at least one of a gate field plate, a drain field plate and a floating field plate may be formed on the dielectric layer, so as to further increase the breakdown voltage of the semiconductor device.

In the above-described manufacturing method, the groove18is formed using the air bridge self-aligned lithography and etching process. With such a process, the position of the groove18with respect to the semiconductor layer12is automatically aligned with the positions of the source field plate19and the gate source15, which avoids alignment deviation caused by a separate lithography process forming the groove18, thus improves yield and reduces manufacture costs. Of course, the air bridge self-aligned lithography and etching process is taken as an example only and is not intended to limit the scope of the present invention.