NAND memory arrays, and devices comprising semiconductor channel material and nitrogen

Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

TECHNICAL FIELD

NAND memory arrays, devices comprising semiconductor channel material and nitrogen, and methods of forming NAND memory arrays.

BACKGROUND

NAND architecture may be a basic unit of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells. It is desired to develop improved NAND architecture.

Transistors are another common component of integrated circuitry. Example transistors are flash transistors. Such may be utilized in, for example, memory, sensors, etc. It is desired to develop improved transistor architectures.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Semiconductor components may comprise semiconductor channel material. For instance, NAND may be configured to have semiconductor channel material extending along a string of NAND memory cells. As another example, flash transistors are typically configured to have semiconductor channel material between a pair of source drain regions. The channel material will have suitable conductivity for transport of electrons during operation of a device (e.g., during string operations of NAND memory, during electrical flow between the source/drain regions of a flash transistor, etc.), The semiconductor channel material may comprise any of numerous semiconductor materials; including, for example, silicon, germanium, III/V materials (e.g., GaAs, InP, GaP and GaN), etc. In some aspects, it is found that diffusion of nitrogen into semiconductor channel material, and/or formation of silicon nitride directly against the channel material, can improve conductivity of the channel material. The mechanism for such improvement may be through modification of grain boundaries within the channel material and/or through other physical/chemical enhancements to the channel material. The possible mechanism is provided to assist the reader in understanding aspects of the invention described herein, and is not to limit the invention except to the extent, if any, that such mechanism is expressly recited in the claims that follow. Example embodiments are described with reference toFIGS. 1-13.

Referring toFIGS. 1 and 1A, a portion of an integrated structure10is illustrated, with such portion being a fragment of a three-dimensional NAND memory array12.

The integrated structure10comprises a stack15of alternating first and second levels18and20. The levels18are insulative (i.e., dielectric), and the levels20are conductive. The “levels”18and20may be alternatively referred to as “layers”18and20.

The insulative levels18comprise insulative material26. Such insulative material may comprise any suitable composition or combination of compositions; and may, for example, comprise silicon dioxide.

The conductive levels20and insulative levels18may be of any suitable vertical thicknesses. In some embodiments, the conductive levels20and the insulative levels18may have vertical thicknesses within a range of from about 10 nanometers (nm) to about 300 nm. In some embodiments, the conductive levels20may have about the same vertical thicknesses as the insulative levels18. In other embodiments, the conductive levels20may have substantially different vertical thicknesses than the insulative levels18.

The stack15is supported by a base17. The base17may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base17may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials; such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base17may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

A gap is provided between the base17and the stack15to indicate that there may be other materials, components, etc., provided between the base17and the stack15. For instance, a conductive source line (not shown) may be provided between the stack15and the base17.

An opening30extends through the stack15. The opening has sidewalls31that extend along the levels18and20. Although the opening30appears to have two sidewalls in the cross-sectional view ofFIG. 1, in actual practice the opening may have a closed shape when viewed from above (e.g., a circular shape, elliptical shape, polygonal shape, etc.), and accordingly there may be a continuous sidewall extending entirely around the opening30as shown in the top view ofFIG. 1A.

A charge-blocking region32extends vertically along the sidewalls31of opening30, with the charge-blocking region comprising charge-blocking material34. The charge-blocking material34may comprise any suitable composition or combination of compositions; including, for example, silicon dioxide and one or more high-k dielectric materials, etc.

Charge-storage material36extends vertically along the charge-blocking material34. The charge-storage material36may comprise any suitable composition or combination of compositions; and in some embodiments may comprise floating gate material (for instance, doped or undoped silicon) or charge-trapping material (for instance, silicon nitride, metal dots, etc.). In some embodiments, the charge-storage material36may comprise, consist essentially of, or consist of silicon nitride. In such embodiments, the charge-storage material36may have a thickness within a range of from about 50 Å to about 80 Å. The illustrated embodiment ofFIG. 1is representative of a configuration commonly associated with NAND having charge-trapping material utilized for charge-storage material36. A configuration commonly associated with NAND utilizing floating gate material is described below with reference toFIG. 11.

A dielectric region38extends vertically along the charge-storage material36. The dielectric region38comprises dielectric material40. In some embodiments, the dielectric material40may be referred to as gate dielectric material, as tunneling material, or as charge-passage material. The dielectric material40may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. In some embodiments, the dielectric material40may be band-gap engineered to have desired charge tunneling properties; and in such embodiments may comprise silicon nitride sandwiched between a pair of silicon dioxide layers, and/or any other suitable configuration.

Channel material42extends vertically along the dielectric material40. In some embodiments, the channel material42may be considered to form a hollow tube44extending vertically along the opening30through stack15.

The channel material42may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of appropriately-doped semiconductor material. Such semiconductor material may include, for example, one or more of silicon, germanium and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP and GaN). In some embodiments, the channel material42may comprise, consist essentially of, or consist of appropriately-doped polycrystalline silicon.

The tube44of channel material42has an exterior surface41along the dielectric material40, an interior surface43in opposing relation to the exterior surface41; and a wall thickness45between the interior surface43and the exterior surface41. In some embodiments, such wall thickness may be within a range of from about 50 Å to about 150 Å.

Nitride is formed along the interior surface43of the channel material42and/or nitrogen is diffused into the channel material42. In some embodiments, the nitride formed along the interior surface43of the channel material42may comprise, consist essentially of, or consist of silicon nitride. In the illustrated embodiment ofFIG. 1, a thin layer (i.e., film) of silicon nitride46is formed along the interior surface43of the hollow tube44of channel material42.

The silicon nitride46may be considered to be a layer having a wall thickness49. Such wall thickness may be within a range of from about 5 Å to about 30 Å in some embodiments. The silicon nitride46may be referred to as stoichiometric silicon nitride in some embodiments to indicate that the silicon nitride has the stoichiometric composition corresponding to Si3N4.

Insulative material48is provided within the hollow tube44. The insulative material48may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

In some embodiments, the conductive levels20may be referred to as wordline levels of a NAND memory array. Terminal ends50of the wordline levels20may function as control gate regions52of NAND memory cells54, with approximate locations of the memory cells54being indicated with brackets inFIG. 1.

The vertically-stacked memory cells54form a vertical string (such as, for example, a vertical NAND string of memory cells), with the number of memory cells in each string being determined by the number of conductive levels20. The stack15may comprise any suitable number of conductive levels. For instance, the stack may have 8 conductive levels, 16 conductive levels, 32 conductive levels, 64 conductive levels, 512 conductive levels, 1028 conductive levels, etc.

The configuration ofFIG. 1may be considered to have memory cells54with gates52spaced from semiconductor channel material42by dielectric regions32and38, and by charge-storage material36. Nitrogen-containing material46is directly against the semiconductor channel material42and on an opposing side of the semiconductor channel material42from the dielectric regions32/38and the charge-storage material36.

In some embodiments, nitrogen extends into the semiconductor channel material42; with such nitrogen being diagrammatically illustrated with stippling inFIGS. 1 and 1A. The nitrogen may extend only partially into the semiconductor channel material42(as shown with the indicated stippling ofFIGS. 1 and 1A), or may extend entirely through the semiconductor channel material42. In some embodiments, the nitrogen may be primarily along an interface51where the semiconductor channel material42joins with the nitrogen-containing material46. In operation, charge flows parallel to the interface51as the charge flows within the channel material42along the vertical string of memory cells54. The nitrogen along the interface and/or within the channel material42is found to increase the conductivity of the channel region42which advantageously improves charge flow along the vertical string of memory cells.

In some embodiments, the nitrogen is present within a volume of the semiconductor channel material to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent. In some embodiments, the volume of the semiconductor channel material comprising the nitrogen may be within a range of from about one volume percent of the semiconductor channel material42to about an entirety of the semiconductor channel material42; within a range of from about 1 volume percent of the semiconductor channel material42to about 50 volume percent of the semiconductor channel material42; within a range of from about 1 volume percent of the semiconductor channel material42to about 25 volume percent of the semiconductor channel material42; etc. In some embodiments, the volume of the semiconductor channel material comprising the nitrogen therein may be within a distance of no greater than about 10 Å from the interface51; may be within a distance of no greater than about 30 Å from the interface51; may be within a distance of no greater than about 50 Å from the interface51; etc.

In some embodiments, one or more of oxygen, fluorine and hydrogen may be within the semiconductor channel material42in addition to the nitrogen. In such embodiments, the oxygen, fluorine and/or hydrogen may be contained within a same volume of the semiconductor channel material as the nitrogen. Alternatively, the nitrogen may extend into an additional volume of the semiconductor channel material which is not occupied by oxygen, fluorine and/or hydrogen; or the oxygen, fluorine and/or hydrogen may extend into an additional volume of the semiconductor channel material which is not occupied by the nitrogen. If oxygen, fluorine and/or hydrogen is present in the semiconductor channel material42, such may be present to any suitable concentration. For instance, oxygen may be present to a concentration within a range of from about 0.1 atomic percent to about 10 atomic percent; fluorine may be present to a concentration within a range of from about 0.1 atomic percent to about 10 atomic percent; and hydrogen may be present to a concentration within a range of from about 0.1 atomic percent to about 40 atomic percent.

The nitrogen concentration within the semiconductor channel material42may be substantially constant throughout a volume of the channel material comprising the nitrogen, or may vary along a gradient. The term “substantially constant” means constant to within reasonable tolerances of fabrication and measurement.FIGS. 2 and 3diagrammatically illustrate regions of construction10, and show example distributions of nitrogen within the semiconductor channel material42; andFIGS. 4-6graphically illustrate the nitrogen concentration within locations of the construction10.

FIG. 2shows an example in which the nitrogen is only along the interface51between the semiconductor channel material42and the nitrogen-containing material46. An approximate location of the nitrogen is diagrammatically illustrated with stippling.FIG. 4graphically illustrates the nitrogen concentration gradient as a line56. The nitrogen is only within a portion of the channel material42, and is present to a substantially constant amount across such portion of the channel material42.

FIG. 3shows an example in which the nitrogen extends across an entirety of the semiconductor channel material42, and where the nitrogen concentration [N] increases in a direction toward the interface51(as represented by stippling within region42, and by an arrow beneath region42indicating a concentration gradient of nitrogen). In some embodiments, the concentration of nitrogen within the channel material42may be considered to vary along a lateral direction, and to remain substantially constant along a vertical direction relative to the embodiment ofFIG. 3. The nitrogen concentration within channel material42may vary along a gradient. An example gradient is illustrated inFIG. 5. The example gradient is a linear gradient decreasing across the entirety of the channel material42. In other embodiments, the gradient may be a step gradient or any other suitable gradient. In some embodiments, the gradient may extend only partially across the channel material42. In yet other embodiments, the gradient may extend beyond channel material42and partially or entirely through the tunnel dielectric material40.FIG. 6shows an example embodiment in which the election concentration gradient extends into the tunnel dielectric material40.

The construction10ofFIG. 1may be formed with any suitable processing. Example processes are described with reference toFIGS. 7-10.

Referring toFIG. 7, the construction10is illustrated at a processing stage after formation of an assembly comprising the vertical stack15of alternating insulative levels18and wordline levels20. The opening30has been formed through the stack15, and the materials34,36,40and42have been formed within such opening. The semiconductor channel material42is configured as the hollow tube44which extends vertically through the stack. The hollow tube44comprises the interior surface43.

Referring toFIG. 8, nitrogen-containing material58is flowed into the opening30and utilized to disperse nitrogen along the interior surface43of the hollow tube44, and/or into the semiconductor channel material42. The nitrogen-containing material58may comprise any suitable material, and may be provided within the opening30utilizing any suitable methodology. For instance, in some embodiments the nitrogen-containing material58may comprise precursor suitable to form silicon nitride deposited along the interior surfaces43utilizing one or both of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In some embodiments, the nitrogen-containing material58may comprise one or both of ammonia (NH3) and hydrazine (N2H2) and may be utilized for rapid thermal nitridation (RTN). Such may be conducted at a temperature of from about 800° C. to about 1000° C., for a time of from about five seconds to about 60 seconds, under atmospheric pressure or any other suitable pressure. In some embodiments, the nitrogen-containing material58may comprise N2and may be utilized for plasma nitridation. The plasma nitridation may include a plasma that contacts the channel material42, and may be conducted under conditions with no bias, a power of from about 500 watts (W) to about 3500 W, and a temperature of from about 200° C. to about 700° C. Alternatively, the plasma nitridation may be remote plasma nitridation (RPN) and may utilize plasma that does not contact the channel material42. If plasma nitridation is utilized, one or both of argon and hydrogen may be included with the nitrogen in the plasma.

One or more of oxygen, fluorine and hydrogen may be provided within the opening30in addition to the nitrogen-containing material58. In such embodiments, the oxygen, fluorine and/or hydrogen may be flowed into the opening30together with the nitrogen-containing material58, or may be flowed into the opening30sequentially relative to the nitrogen-containing material58.

Referring toFIG. 9, construction10is shown at a processing stage following that ofFIG. 8, and in accordance with an embodiment in which the nitrogen-containing material58forms the stoichiometric silicon nitride46along the interior surface43of the tube44of semiconductor channel material42, and disperses nitrogen into the channel material42(as is diagrammatically indicated by stippling). In other embodiments, the nitrogen-containing material ofFIG. 8(material58) may simply disperse nitrogen within channel material42without forming the stoichiometric silicon nitride46along the surface of material42.

Referring toFIG. 10, the insulative material48is provided within 30, and such completes the configuration described above with reference toFIG. 1.

FIGS. 1-10illustrate an example NAND memory array.FIG. 11shows a construction10aillustrating another example NAND memory array12a. The charge-storage material36of construction10ais configured as floating gates. The tunneling material (i.e. gate dielectric material)40is provided between the charge-storage material36and the channel material42, and the charge-blocking material34partially surrounds the charge-storage material36and is between the charge-storage material36and the wordline material28.

Regardless of whether the NAND memory configuration ofFIG. 1is utilized, the NAND memory configuration ofFIG. 11is utilized, or a different NAND memory configuration is utilized, such may benefit from inclusion of nitrogen along an interior surface of the channel material42and/or dispersed into the channel material42in that such nitrogen can increase current (i.e., reduce resistivity) along the channel material42. The increased current may enable improved read operations and/or other operations as compared to conventional NAND memory constructions lacking nitrogen along and/or within analogous channel material.

Nitrogen along and/or within channel material may be incorporated into flash transistor architecture in some embodiments. For instance,FIG. 12shows a construction100comprising a flash transistor (or flash memory transistor)102. The transistor102includes a control gate104, a charge-storage material108, charge-blocking material106between the gate104and the charge-storage material108, and tunnel dielectric110beneath the charge-storage material108. The control gate104may comprise any of the electrically conductive compositions described above relative to the wordline material28ofFIG. 1; the charge-blocking material106may comprise any of the compositions described above relative to the charge-blocking material34ofFIG. 1; the charge-storage material108may comprise any of the compositions described above relative to the charge-storage material36ofFIG. 1; and the tunnel dielectric material110may comprise any of the compositions described above with reference to the tunnel dielectric material40ofFIG. 1.

The materials104,106,108and110together form a stack112, and such stack is supported by a substrate114. The substrate114includes a pair of source/drain regions116and118that extend into a semiconductor material120. The semiconductor material120may comprise any of the compositions described above relative to the semiconductor channel material42ofFIG. 1.

A channel region122is within the semiconductor material120and between the source/drain regions116and118. The channel region122is directly beneath the stack112in the illustrated embodiment.

The semiconductor material120is supported by a nitrogen-containing material124. Such nitrogen-containing material may comprise, consist essentially of, or consist of silicon nitride in some embodiments. An interface125is between the nitrogen-containing material124and the semiconductor material120directly along the channel region122. In operation, charge flows parallel to such interface when the charge flows through the channel region122and between the source/drain regions116and118. The nitrogen along interface125may improve conductivity within the channel region122. Further, in some embodiments nitrogen may disperse from the nitrogen-containing material124into the channel region122(as is diagrammatically indicated with stippling), which may further improve conductivity within the channel region.

In some embodiments, the nitrogen-containing material124may be stoichiometric silicon nitride. The channel region122has a first side121directly against a dielectric region comprising the dielectric material110, and has a second side123in opposing relation to the first side121. The second side123is along the interface125. In the shown embodiment, a region of the nitrogen containing material (e.g., stoichiometric silicon nitride)124extends upwardly to be laterally between the source/drain regions116and118. Generally, it may be desired that the nitrogen containing material (e.g., stoichiometric silicon nitride) extends no more than about halfway up the source/drain regions116and118as the nitrogen containing material may be insulative and the conductivity of the channel region may be impaired if the vertical thickness of the channel region is overly restricted by an insulative nitrogen-containing material124.

The nitrogen within the channel region122may be primarily along the interface125, or may extend a substantial distance into the channel region. If the nitrogen extends a substantial distance into the channel region, a gradient of nitrogen concentration may be established analogously to the gradients described above with reference toFIGS. 3, 5 and 6. For instance,FIG. 13shows construction100in an embodiment in which a gradient of nitrogen concentration [N] extends downwardly toward the interface125(with such gradient being diagrammatically illustrated with an arrow and with stippling).

The structures discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include device which includes a gate spaced from semiconductor channel material by a dielectric region, and nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region.

Some embodiments include a device which includes a gate spaced from semiconductor channel material by a dielectric region, and nitrogen within at least some of the semiconductor channel material.

Some embodiments include a memory array (e.g., a NAND memory array) which comprises a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically through the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material.

Some embodiments include a memory array, comprising a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically through the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material.

Nitrogen-containing material is directly against the channel material and on an opposing side of the channel material from the dielectric material.

Some embodiments include a method of forming a memory array (e.g., a NAND memory array). An assembly is formed to comprise a vertical stack of alternating insulative levels and wordline levels, and to comprise a hollow tube of semiconductor channel material extending vertically through the stack. Nitrogen is dispersed along an interior surface of the hollow tube and into the semiconductor channel material.