Circuit board, method for manufacturing circuit board, and electronic device

A circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.

FIELD

The embodiments discussed herein are related to a circuit board, a method for manufacturing a circuit board, and an electronic device.

BACKGROUND

There has been a technology in which a capacitor is incorporated in a circuit board. A capacitor has a structure in which a dielectric layer using a given material is sandwiched between a pair of conductor layers. In relation to the circuit board incorporating the capacitor, there has been a technology in which, for interlayer coupling inside the circuit board, a conductor via is provided which penetrates the capacitor while making contact with the dielectric layer and one of the pair of conductor layers sandwiching the dielectric layer therebetween. In addition, there has been also a technology in which a conductor via is provided which penetrates the capacitor in a non-contact relation with the dielectric layer and at least one of the pair of conductor layers sandwiching the dielectric layer therebetween. The conductor via is provided in the circuit board by forming a hole penetrating a given part of the capacitor and forming a conductor via material in the hole.

Examples of related-art documents are Japanese Laid-open Patent Publication No. 2006-210776 and Japanese Laid-open Patent Publication No. 2015-18988.

SUMMARY

According to an aspect of the embodiments, a circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first conductor via and the second conductor via.

DESCRIPTION OF EMBODIMENTS

In recent years, in regard of semiconductor devices such as semiconductor chips and semiconductor packages to be mounted on electronic devices and electronic apparatuses, increases in performance, operation speed and current and a decrease in voltage have been under way. For a stable operation of such a semiconductor device, it is important to restrain variations in power supply voltage and to remove high-frequency noises. Therefore, with respect to a circuit board on which to mount a semiconductor device, a reduction in power supply impedance is requested.

As one of techniques for reducing the power supply impedance, there has been known a technique of mounting a chip capacitor on the circuit board, and coupling the chip capacitor between a power supply line and a ground (GND) line of the circuit board. From the viewpoint of shortening the wiring length from the semiconductor device to the capacitor and, suppressing an inductance component of the wiring, there have been known a technique of incorporating a chip capacitor in a circuit board and a technique of incorporating a capacitor (thin film capacitor) formed by a dielectric layer and a pair of conductor layers sandwiching the dielectric layer therebetween.

A circuit board incorporating a capacitor will be described. The circuit board incorporating a capacitor includes a capacitor including a structure in which a dielectric layer is sandwiched between a pair of conductor layers, in an insulating layer. One of the pair of conductor layers is set to a power supply potential, while the other is set to a GND potential, and the one and the other are electrically coupled to a power supply terminal and a GND terminal for external coupling of the circuit board.

In the circuit board incorporating a capacitor, a conductor via which penetrates a capacitor provided in an insulating layer may be provided for interlayer coupling inside the circuit board. The circuit board including such a conductor via is formed, for example, using a method as follows.

FIGS. 1A, 1B, 1C and 1DandFIGS. 2A and 2Bare figures illustrating an example of a method for forming a circuit board. InFIGS. 1A to 1DandFIGS. 2A and 2B, a section of a major part in each process in forming the circuit board is illustrated schematically.

First, a capacitor board100ain which a dielectric layer110is sandwiched between a pair of a conductor layer (electrode layer)120and a conductor layer (electrode layer)130as illustrated inFIG. 1Ais prepared. The capacitor board100ais obtained, for example, by forming the dielectric layer110on the electrode layer130on one side and forming thereon the electrode layer120on the other side. Various dielectric materials may be used for the dielectric layer110, and various conductor materials may be used for the electrode layer120and the electrode layer130. A ceramic material such as barium titanate (BaTiO3; BTO) is used for the dielectric layer110, and a metallic material such as copper (Cu) and nickel (Ni) is used for the electrode layer120and the electrode layer130.

The electrode layer120and the electrode layer130of the capacitor board100aare patterned into respective given shapes. The patterning of the electrode layer120and the electrode layer130is performed, for example, by etching. InFIG. 1Bis illustrated an example in which the electrode layer120is formed with an opening part121in a region including a position where to form a conductor via310(or a hole300for forming thereof) to be described later.

The capacitor board100aafter the patterning is united with the insulating layer210, as illustrated inFIG. 1C. The insulating layer210is an insulating layer of a resin, a prepreg or the like, an insulating layer using an epoxy resin or the like, which is provided on a base board including one or a plurality of wiring layers. Onto such an insulating layer210, the capacitor board100ais adhered under heating and pressurizing (thermocompression bonded), whereby the capacitor board100ais united with the insulating layer210.

The capacitor board100aunited with the insulating layer210is formed with an insulating layer220, as illustrated inFIG. 1D. The insulating layer220is an insulating layer of a resin, a prepreg or the like, an insulating layer using an epoxy resin or the like. Such an insulating layer220is thermocompression bonded onto the capacitor board100aon the insulating layer210. This results in that the capacitor board100aunited with the insulating layer210is covered by the insulating layer220.

For example, the method as illustrated inFIGS. 1A to 1Dis used, to form a basic structure of a circuit board in which the capacitor100(capacitor board100a) is incorporated in the insulating layer210and the insulating layer220(insulating layer200).

In the case of providing the circuit board with a conductor via penetrating the incorporated capacitor100, for interlayer coupling inside the circuit board, a hole300penetrating the capacitor100is first formed, as illustrated inFIG. 2A. The hole300is formed by laser processing or drilling.

The hole300is formed in such a manner as, for example, to penetrate the circuit board or to reach a part of a wiring layer provided on the base board the insulating layer210side.

The hole300is formed at the position of the opening part121of the electrode layer120formed precedingly, in an opening size smaller than that of the opening part121(in a size smaller than the opening part121in plan view). For example, at the time of patterning (FIG. 1B) of the electrode layer120, the opening part121is larger in opening size than the hole300. Of the dielectric layer110, the electrode layer120and, the electrode layer130of the capacitor100, the dielectric layer110and the electrode layer130on one side are exposed at an inner wall of the hole300, as illustrated inFIG. 2A.

After the formation of the hole300, a conductor material is formed on the inner wall of the hole300, and the conductor via310is formed, as illustrated inFIG. 2B. Various conductor materials, for example, a metallic material such as Cu, may be used for the conductor via310. The conductor via310is obtained, for example, by first forming a conductor layer (seed layer)301by electroless plating, and then forming a conductor layer (plating layer)302by electroplating using the seed layer301as a current supplying layer.

When the conductor via310is formed on the inner wall of the hole300, the seed layer301and the plating layer302are formed also on an upper surface of the insulating layer220. The seed layer301and the plating layer302formed on the upper surface of the insulating layer220are used as part (conductor layer313) of wiring coupled to the conductor via310, of the circuit board.

As illustrated inFIG. 2B, the conductor via310provided on the inner wall of the hole300makes contact with the dielectric layer110and the electrode layer130of the capacitor100which are exposed at the inner wall at the time of formation of the hole300. This results in that the conductor via310penetrating the capacitor100and the electrode layer130of the capacitor100are electrically coupled. The conductor via310and the electrode layer130of the capacitor100thus coupled are set to a power supply potential or a GND potential. Of the capacitor100, the electrode layer120on another side which is provided with the opening part121and is not coupled to the conductor via310is set to a potential different from that of the electrode layer130coupled to the conductor via310. By the conductor via310, an interlayer coupling structure for electrically coupling a plurality of layers inclusive of the capacitor100, in the circuit board, is formed.

As illustrated inFIG. 2B, for example, in a central area of the hole300formed with the conductor via310on the inner wall thereof, a cavity400is left, after the formation of the conductor via310. The cavity400may be filled with a resin (not illustrated) such as an epoxy resin. While a conformal via formed on the inner wall of the hole300is illustrated here as an example of the conductor via310, a filled via in which the hole300is filled with a conductor material may be formed.

While illustration is omitted, a so-called build-up process may be carried out in which an insulating layer of a resin or the like is laminated on the insulating layer220side and the insulating layer is formed with a conductor via and a conductor layer, after the process ofFIG. 2B. Such a build-up process is conducted one time or repeated multiple times, whereby a circuit board including a desired number of wiring layers is obtained.

Other than the above, a so-called collective lamination process of laminating one or a plurality of boards including an insulating layer of a resin or the like and a conductor layer patternedly formed thereon on the capacitor100side may, for example, be conducted after the process ofFIG. 1D, thereby obtaining a circuit board including a desired number of wiring layers. In this, case, after the collective lamination, process, the formation of the hole300is conducted as illustrated inFIG. 2A, and the formation of the conductor via310is performed as illustrated inFIG. 2B.

The method as above, for example, is used to form the conductor via310penetrating the capacitor100, and an interlayer coupling structure of the circuit board by the conductor via310is realized. As another method for obtaining an interlayer coupling structure of a circuit board, there is a so-called multi-stage laser processing method in which each layer laminated is subjected respectively to formation of a hole by laser processing and formation of a conductor material in the hole, whereby a conductor via for electrically coupling the layers is formed.

When the method for collectively forming the hole300in the plurality of layers (FIG. 2A) and forming the conductor via310in the hole300(FIG. 2B) as above is used, simplification of the circuit board formation and enhancement of the efficiency thereof may be realized, as compared to the case where the multi-stage laser processing method is used. When the formation of the hole300is conducted by drilling, the hole300may be formed in a given opening diameter and in a desired depth, and enhancement of the degree of freedom in design in multilayer formation of a circuit board may be realized.

On the other hand, in the method for forming the hole300by drilling, situations as illustrated inFIGS. 3A, 3B and 3CandFIGS. 4A, 4B and 4Cmay occur.FIGS. 3A, 3B and 3Care illustrations of a hole forming process in forming a circuit board, andFIGS. 4A, 4B and 4Care illustrations of a conductor via forming process and a heating process in forming a circuit board.FIG. 3Aillustrates schematically a section of a major part before hole formation.FIG. 3Billustrates schematically a section of a major part during the hole formation andFIG. 3Cillustrates schematically a section of a major part after the hole formation.FIG. 4Aillustrates schematically a section of a major part in an electroless plating process.FIG. 4Billustrates schematically a section of a major part in an electroplating process, andFIG. 4Cillustrates schematically a section of a major part in a heating process.

As illustrated inFIG. 3A, for forming a laminate (FIG. 1D) of the insulating layer210, the capacitor100and the insulating layer220with the hole300for the conductor via310, hole formation by use of a drill500as depicted inFIG. 3Bis conducted. The hole formation by use of the drill500is carried out, for example, from the insulating layer220side, in such a manner that the hole formed penetrates the insulating layer220, the electrode layer130and the dielectric layer110of the capacitor100, and the insulating layer210. The hole formation is conducted at the position of the opening part121formed in the electrode layer120of the capacitor100, as illustrated inFIG. 2A. InFIGS. 3A, 3B and 3CandFIGS. 4A, 4B and 4C, the electrode layer120is not illustrated (the opening part121thereof is illustrated). At the inner wall of the hole300formed by the drill500, there are exposed the insulating layer220, the electrode layer130, the dielectric layer110and the insulating layer210, as illustrated inFIG. 3B.

When the hole formation is thus conducted using the drill500, stress at the time of the processing deforms the electrode layer130, and the dielectric layer110is deformed attendant on the deformation of the electrode layer130, as illustrated inFIGS. 3B and 3C. Due to such deformations of the electrode layer130and the dielectric layer110and, further, to differences in physical properties of the layers, adhesion properties and the like, a crack600as depicted inFIGS. 3B and 3Cmay be generated between the electrode layer130and the dielectric layer110.

When electroless plating is performed in a state in which such a crack600has been generated, as illustrated inFIG. 4A, the crack600may be left without being filled with a plating solution610of the electroless plating or with the seed layer301formed. When electroplating is further conducted as depicted inFIG. 4Bafter the electroless plating, a plating solution620may enter into the crack600left. Alternatively, the crack600may remain as void even after the electroplating. The plating solution620having entered into the crack600or the void remaining in the crack600may be enclosed in the crack600through a process in which the inner wall of the hole300is closed with the seed layer301formed by the electroless plating and the plating layer302formed by the electroplating, for example, the conductor via310.

When the circuit board after the formation of the conductor via310is heated due to application of heat at the time of a test or in practical use in a state in which the plating solution620or the void is left in the crack600, the plating solution620or the void (a gas inside thereof) remaining in the crack600may expand. When the plating solution620or the void in the crack600thus expands due to heating, as illustrated inFIG. 4C, exfoliation630may be generated between the electrode layer130and the dielectric layer110of the capacitor100, with the crack600at the inner wall of the hole300as a starting point. The exfoliation630generated between the electrode layer130and the dielectric layer110would cause a lowering in capacitance of the capacitor100.

Thus, when the method for forming the hole300by drilling is used, the crack600generated between the electrode layer130and the dielectric layer110and the exfoliation630arising therefrom may lower the reliability and performance of the capacitor100and the circuit board incorporating the capacitor100.

A case in which drilling is applied to a laminated part of the electrode layer130and the dielectric layer110present at a position corresponding to the opening part121of the electrode layer120has been described here as an example. The same as above applies also to a case in which drilling is applied to a laminated part of the dielectric layer110and the electrode layer120present at a position corresponding to the opening part of the electrode layer130. In this case, also, the crack and exfoliation generated between the dielectric layer110and the electrode layer120due to the drilling may cause a lowering in the reliability and performance of the capacitor100and the circuit board incorporating the capacitor100.

Taking the above-mentioned points into consideration, the lowering in the reliability and performance of the circuit board incorporating the capacitor due to heating is restrained by use of techniques as described in the embodiments below. First, a first embodiment will be described.

FIGS. 5 to 7A and 7Bare figures illustrating an, example of a circuit board according to the first embodiment.FIG. 5illustrates schematically a section of a major part of the circuit board according to the first embodiment.FIG. 6illustrates schematically a plane as viewed along arrow line L1-L1ofFIG. 5.FIG. 7Aillustrates schematically an example of a plane as viewed along arrow line L2-L2ofFIG. 5, andFIG. 7Billustrates schematically another example of the plane as viewed along arrow line L2-L2ofFIG. 5.

A circuit board1illustrated inFIG. 5includes an insulating layer20(an insulating layer21and an insulating layer22), and a capacitor10(capacitor board10a) provided in the insulating layer20. The circuit board1further includes a conductor via31provided in a hole30penetrating the insulating layer20and the capacitor10, a conductor via (coupling via)32coupled to the capacitor10, and a conductor layer33coupled to the conductor via31and the coupling via32.

The capacitor10includes a dielectric layer11, and a pair of a conductor layer (electrode layer)12and a conductor layer (electrode layer)13sandwiching the dielectric layer11therebetween. Various dielectric materials may be used for the dielectric layer11. For example, a ceramic material is used for the dielectric layer11. As the ceramic material for the dielectric layer11, various high dielectric materials such as BTO may be used. As the ceramic material for the dielectric layer11, there may be used high dielectric materials such as barium strontium titanate (BaxSr1-xTiO3; BSTO) obtained by addition of strontium (Sr) to BTO, strontium titanate (SrTiO3; STO), lead zirconate titanate (Pb(Zr,Ti)O3; PZT), and lanthanum added PZT (PLZT). The thickness of the dielectric layer11is, for example, 1 to 3 μm.

For the electrode layer12and the electrode layer13, various conductor materials may be used. For example, a metallic material or materials are used for the electrode layer12and the electrode layer13. As the metallic material for the electrode layer12, there may be used Cu, Ni and the like. The thicknesses of the electrode layer12and the electrode layer13are, for example, 15 to 30 μm. The electrode layer12and the electrode layer13are respectively patterned into given shapes. The electrode layer12includes an opening part12ain a region including the position at which to form the conductor via31or the hole30. The electrode layer13also includes an opening part13ain a region including the position at which to form the conductor via31or the hole30. The electrode layer12and the electrode layer13are provided respectively with the opening part12aand an opening part13aat positions corresponding to each other. The opening part12aand the opening part13adiffering in opening size are illustrated here as an example. The opening part12aand the opening part13amay be the same or comparable in opening size, and an increase in the area of facing parts of the electrode layer12and the electrode layer13makes it possible to increase capacitance.

The capacitor10may be obtained by forming the dielectric layer11(for example, a layer containing BTO as a main constituent) on the electrode layer13on one side (for example, a layer containing Ni as a main constituent), and forming thereon the electrode layer12on the other side (for example, a layer containing Cu as a main constituent), as will be described later. The capacitor10obtained in this way is formed on the insulating layer21, and the insulating layer22is formed on the capacitor10, as will be described later.

The insulating layer21, as that part of the insulating layer20which is provided under the capacitor10, is, for example, an insulating layer of a resin, a prepreg or the like, which is provided on a base board including one or a plurality of wiring layers. For the insulating layer21, there may be used resin materials such as epoxy resin, polyimide resin, and bismaleimide-triazine resin, or such a resin material in which glass or other fibers or cloth is contained. For the insulating layer22, as that part of the insulating layer20which is provided on the capacitor10, also, there may, be used resin materials such as epoxy resin, polyimide resin, and bismaleimide-triazine resin, or such a resin material in which glass or other fibers or cloth is contained.

The hole30is formed in such a manner as to penetrate the insulating layer22, the capacitor10and the insulating layer21. The hole30is formed at the position of the opening part12aof the electrode layer12and the opening part13aof the electrode layer13, in an opening size smaller than those of the opening part12aand the opening part13a(in a size smaller than the opening part12aand the opening part13ain plan view). For example, the electrode layer12and the electrode layer13are preliminarily formed with the opening part12aand the opening part13ain opening sizes larger than that of the hole30to be formed. Therefore, of the dielectric layer11, the electrode layer12and the electrode layer13of the capacitor10, only the dielectric layer11is exposed at the inner wall of the hole30. For example, a hole30which is circular in plan view and has an opening size of 50 to 300 μm in diameter is provided.

The conductor via31is provided in the hole30. For the conductor via31, various conductor materials may be used. For example, a metallic material is used for the conductor via31. As the metallic material for the conductor via31, there may be used Cu and the like. The conductor via31is formed by use of a plating method, as will be described later. Since the electrode layer12and the electrode layer13of the capacitor10are not exposed at the inner wall of the hole30as aforementioned, the conductor via31is directly coupled with neither of the electrode layer12and the electrode layer13of the capacitor10. The conductor via31is, for example a conformal via which is provided on the inner wall of the hole30, with the cavity40left in central area. The cavity40may be filled with a resin (not illustrated).

A schematic figure in a plane as viewed along arrow line L1-L1along plane directions of the electrode layer13of the capacitor10is illustrated inFIG. 6. InFIG. 6, the opening part12aof the electrode layer12of the capacitor10is indicated by dotted line. The opening part13aof the electrode layer13smaller in opening size than the opening part12aof the electrode layer12is provided at a position corresponding to the opening part12a. The conductor via31is located on the inner side of edges of the opening part12aand the opening part13a, of the electrode layer12and the electrode layer13and is not in contact with either of the electrode layer12and the electrode layer13.

While the conductor via31, the opening part12aand the opening part13awhich are circular in planar outer shape are illustrated as an example inFIG. 6, the outer shapes of the conductor via31, the opening part12aand the opening part13aare not limited to the circular planar shape. The outer shapes of the conductor via31, the opening part12aand the opening part13amay be any of various planar shapes, provided that a structure in which the conductor via31on the inner wall of the hole30makes contact with neither of the electrode layer12and the electrode layer13of the capacitor10is ensured.

As illustrated inFIG. 5, the conductor layer33coupled to the conductor via31provided in the hole30is provided on the upper surface22aof the insulating layer22. For the conductor layer33, various conductor materials may be used. For example, a metallic material is used for the conductor layer33. As the metallic material for the conductor layer33, there may be used Cu and the like. The conductor layer33is formed, for example, simultaneously with the conductor via31when the conductor via31is formed on the inner wall of the hole30by use of a plating method, as will be described later.

As illustrated inFIG. 5, the coupling via32coupled to the electrode layer13on one side of the capacitor10and to the conductor layer33on the insulating layer22on the capacitor10is provided in the insulating layer22. For the coupling via32, various conductor materials may be used. For example, a metallic material is used for the coupling via32. As the metallic material for the coupling via32, there may be used Cu and the like. The coupling via32is formed, for example, by subjecting the insulating layer22on the capacitor10to laser processing, and filling a hole32aformed thereby in the insulating layer22with a conductor material, before the formation of the conductor layer33or of the conductor layer33and the conductor via31, as will be described later.

Schematic figures in plane as viewed along arrow line L2-L2of the insulating layer22provided with the coupling via32are illustrated inFIGS. 7A and 7B. The coupling via32is a continuous conductor wall32bprovided in such a manner as to surround the conductor via31in the hole30, as illustrated inFIG. 7A, for example. Alternatively, the coupling via32includes a plurality of (here, as an example, eight) conductor vias32cprovided in such a manner as to surround the conductor via31in the hole30, as illustrated inFIG. 7B, for example. In the insulating layer22, the hole or holes32aare formed in a shape according to the form of the coupling via32, or the form of the conductor wall32bor the group of conductor vias32c.

While the conductor wall32band the group of conductor vias32cwhich are circular in planar outer shape are illustrated as an, example inFIGS. 7A and 7B, the outer shapes of the conductor wall32band the group of conductor vias32care not limited to the circular planar shape. The outer shapes of the conductor wall32band the group of conductor vias32cmay be any of various planar shapes, provided that the electrode layer13of the capacitor10and the conductor layer33on the insulating layer22are electrically coupled.

As has been described above, in the circuit board1, a structure is adopted in which the electrode layer12and the electrode layer13of the capacitor10are not exposed at the inner wall of the hole30where the conductor via31is formed, and the conductor via31is not directly coupled with either the electrode layer12or the electrode layer13of the capacitor10in the hole30. Of the capacitor10, the electrode layer13on one side is electrically coupled to the conductor via31in the hole30through the coupling via32in the insulating layer22and the conductor layer33on the insulating layer22. In the circuit board1, the electrode layer13on one side of the capacitor10is set to a given potential by the conductor via31, the conductor layer33and the coupling via32.

The coupling via32may be configured to include the conductor wall32bas illustrated inFIG. 7Aor the group of the conductor vias32cas depicted inFIG. 7B, or may be a single columnar conductor via, provided that the conductor via31and the conductor layer33and the electrode layer13of the capacitor10may be electrically coupled. It is to be noted, however, that when the coupling via32is configured to include the conductor wall32bor the group, of conductor vias32cas above-mentioned, the area of contact between the coupling via32and the conductor layer33is comparatively large. This enables realization of, for example, a reduction in the electric resistance between the coupling via32and the conductor layer33, and stabilization of the potential of the electrode layer13of the capacitor10.

The circuit board1as above-described is formed, for example, by a method as follows.FIGS. 8A, 8B, 8C and 8D to 10A and 10Bare figures illustrating an example of a method for forming the circuit board according to the first embodiment.FIGS. 8A to 8D, 9A and 9B, and 10A and 10Beach illustrate schematically a section of a major part in each process in forming the circuit board according to the first embodiment.

The capacitor board10ain which the dielectric layer11is sandwiched between a pair of the electrode layer12and the electrode layer13as depicted inFIG. 8Ais first prepared. The capacitor board10ais obtained, for example, by a process in which the dielectric layer11containing BTO as a main constituent is sinteredly formed on the electrode layer13on one side containing Ni as a main constituent, and the electrode layer12on the other side containing Cu as a main constituent is coveringly formed thereon.

The electrode layer12and the electrode layer13of the capacitor board10aare respectively patterned into given shapes, by etching, for example. InFIG. 8B, there is depicted an example in which the electrode layer12is formed with the opening part12a, and the electrode layer13is formed with the opening part13a, by patterning. The opening part12aand the opening part13aare both formed in a region including the position where to form the hole30and the conductor via31.

The capacitor board10aafter the patterning is united with the insulating layer21formed using a resin or the like, as illustrated inFIG. 8C. The capacitor board10ais united with the insulating layer21, for example, by thermocompression bonding onto the insulating layer21, with the electrode layer12side thereof facing the insulating layer21side.

On the capacitor board10aunited with the insulating layer21, the insulating layer22using a resin or the like is further formed, as depicted inFIG. 8D. The insulating layer22is, for example, thermocompression bonded onto the capacitor board10aprovided on the insulating layer21, thereby being united with the insulating layer21and the capacitor board10a.

For example, the method as illustrated inFIGS. 8A to 8Dis used to form a board1aincorporating the capacitor10(capacitor board10a) in the insulating layer21and the insulating layer22(the insulating layer20).

After the formation of the board1aas depicted inFIG. 8D, a hole32areaching the electrode layer13of the capacitor10is formed, as illustrated inFIG. 9A. The hole32ais formed by, for example, laser processing, for example, processing using carbon dioxide gas laser (CO2laser), applied to the insulating layer22on the capacitor10.

After the formation of the hole32ain the insulating layer22, the hole32aformed is filled with a conductor material such as Cu, to form the coupling via32, as depicted inFIG. 9B. For example, the coupling via32is formed in the hole32aby electroless plating and electroplating.

After the formation of the coupling via32, a hole30penetrating the insulating layer22, the capacitor10and the insulating layer21is formed, as depicted inFIG. 10A. The hole30is formed at the position of the opening part12aand the opening part13aprovided in the electrode layer12and the electrode layer13of the capacitor10, in an opening size smaller than those of the opening part12aand the opening part13a.

The hole30is formed by drilling. In the drilling, the insulating layer22, the dielectric layer11of the capacitor10, and the insulating layer21are cut by a drill, to form the hole30. Since the opening part12aof the electrode layer12and the opening part13aof the electrode layer13of the capacitor10are larger in opening size than the hole30to be formed, the electrode layer12and the electrode layer13are suppressed from being cut by the drill. For this, reason, deformation of the electrode layer130and the dielectric layer110thereunder and generation of the crack600between the electrode layer130and the dielectric layer110, as depicted inFIGS. 3A, 3B and 3CandFIGS. 4A, 4B and 4Care restrained from being generated due to stress at the time of drilling.

The adhesion between the dielectric layer11and the insulating layer21and the insulating layer22is higher than the adhesion between the dielectric layer11and the electrode layer13, so that even when the insulating layer22, the dielectric layer11and the insulating layer21are subjected to drilling, generation of a crack between the dielectric layer11and the insulating layer21and the insulating layer22is restrained.

After the formation of the hole30, a conductor material such as Cu is formed on the inner wall of the hole30, to form the conductor via31, as depicted inFIG. 10B. For example, a conductor layer (seed layer)30ais first formed by electroless plating, and a conductor layer (plating layer)30bis then formed by electroplating in which the seed layer30ais used as a current supply layer. This results in that the conductor via31is formed on the inner wall of the hole30.

At the time of formation of the conductor via31, the seed layer30aand the plating layer30bare formed on the upper surface22aof the insulating layer22in addition to on the inner wall of the hole30, as illustrated inFIG. 10B. This enables the formation of the conductor layer33on the upper surface22aof the insulating layer22. The conductor layer33may be patterned into a given shape. By the conductor layer33on the insulating layer22, electrical coupling between the conductor via31in the hole30and the coupling via32in the insulating layer22is provided.

The conductor via31is formed on the inner wall of the hole30, and is formed as a conformal via in which the cavity40is left in a central area. In this case, the cavity40may be filled with a resin (not illustrated) such as epoxy resin. The hole30may be filled with a conductor material, to form a filled via.

The circuit, board1is formed by the above-mentioned processes. In the circuit board1, the electrode layer12and the electrode layer13of the capacitor10are provided with the opening part12aand the opening part13alarger than the conductor via31, at the position where to form the conductor via31or the hole30. For this reason, even in the case where the hole30for forming the conductor via31is formed by drilling, the electrode layer12and the electrode layer13are suppressed from being cut, so that generation of a crack between the dielectric layer11and the electrode layer12and the electrode layer13is restrained.

The conductor via31in the hole30is electrically coupled to one of the electrode layer12and the electrode layer13of the capacitor10, in, this example, the electrode layer13. The electrical coupling between the electrode layer13of the capacitor10and the conductor via31in the hole30is realized by the coupling via32which is formed in the insulating layer22in such a manner as to be coupled to the electrode layer13and the conductor layer33which is formed on the insulating layer22and coupled to the conductor via31in the hole30.

Since generation of a crack between the dielectric layer11and the electrode layer12and the electrode layer13is restrained, in the circuit board1, penetration of a plating solution into such a crack at the time of forming the conductor via31in the hole30by use of a plating method is restrained. Since the generation of a crack and the penetration of the plating solution into such a crack are restrained, it is ensured that even when the circuit board1is heated at the time of a tester during practical use, expansion of the plating solution in the crack and the resulting exfoliation between the dielectric layer11and the electrode layer12and the electrode layer13are restrained from being generated. As a result, a lowering in the capacitance of the capacitor10incorporated in the circuit board1is restrained.

According to the above-mentioned technique, a circuit board1excellent in reliability and performance is realized in which it is possible to effectively restrain generation of a crack at the time of drilling, exfoliation at the time of a test or practical use involving heating, and the resulting lowering in capacitance, in the capacitor10.

While the capacitor10or the capacitor board10ahas the electrode layer12disposed directed to the insulating layer21side and has the electrode layer13disposed directed to the insulating layer22side here, it is natural that the electrode layer13may be disposed directed to the insulating layer21side and the electrode layer12may be disposed directed to the insulating layer22side. In this case, the coupling via32is formed in the insulating layer22in such a manner as to be coupled to the electrode layer12on the upper layer side, and electrical coupling between the electrode layer12and the conductor via31is realized by the coupling via32and the conductor layer33on the insulating layer22that is coupled to the conductor via31in the hole30.

Though not illustrated, a build-up process of laminating an insulating layer of a resin or the like on the circuit board1formed as above and forming the insulating layer with a conductor via and a conductor layer may be conducted once or repeated multiple times, to obtain a circuit board including a desired number of wiring layers.

Now, a second embodiment will be described. The process of forming the hole30for forming the conductor via31(hole formation) may be performed after the build-up process is conducted once or repeated multiple times. Such an embodiment will be described here as the second embodiment.

FIGS. 11A and 11BandFIGS. 12A and 12Bare figures illustrating an example of a method for forming a circuit board according to the second embodiment.FIGS. 11A and 11BandFIGS. 12A and 12Beach illustrate schematically a section of a major part in each process in forming the circuit board according to the second embodiment.

For example, after the processes ofFIGS. 8A to 8DandFIGS. 9A and 9Bdescribed in the first embodiment above are performed, a build-up process as depicted inFIGS. 11A and 11Bis carried out.

In this example, after the formation of the hole32adepicted inFIG. 9A, a conductor material such as Cu is formed in the hole32aand on the upper surface22aof the insulating layer22by a plating method, and the conductor material formed on the upper surface22aof the insulating layer22is patterned into a given shape by etching. This results in that a board1aincluding the coupling via32and a conductor layer34provided thereon, as depicted inFIG. 11A, is obtained.

An insulating layer23is formed on such a board1a, and a hole35ais formed in the insulating layer23, as illustrated inFIG. 11A. The insulating layer23is an insulating layer of a resin, a prepreg or the like, an insulating layer using an epoxy resin or the like. The formation of the hole35ain the insulating layer23is performed by laser processing.

After the formation of the hole35a, as illustrated inFIG. 11B, a conductor material such as Cu is formed in the thus formed hole35aby a plating method, to form a coupling via35in the insulating layer23. The coupling via35is electrically coupled to the electrode layer13the capacitor10through the conductor layer34and the coupling via32.

The coupling via35formed in the insulating layer23may be a continuous conductor wall surrounding the conductor via31in the hole30in plan view, according to the example ofFIG. 7A. Alternatively, the coupling via35may be configured to include a plurality of conductor vias surrounding the conductor via31in plan view, according to the example ofFIG. 7B. In the process ofFIG. 11A, the hole or holes35aare formed in the insulating layer23in a shape according to the form (a conductor wall or a group of conductor vias) of the coupling via35to be formed in the process ofFIG. 11B.

By the processes as depicted inFIGS. 11A and 11B, a board1bformed with a build-up layer2including the insulating layer23and the coupling via35is obtained. After the formation of the coupling via35, a hole30penetrating the insulating layer23, the insulating layer22, the capacitor10and the insulating layer21is formed, as depicted inFIG. 12A, according to the example ofFIG. 10Aabove. The hole30is formed at the position of the opening part12aand the opening part13aprovided in the electrode layer12and the electrode layer13of the capacitor10, in an opening size smaller than those of the opening part12aand the opening part13a, by drilling. Since the electrode layer12and the electrode layer13of the capacitor10are suppressed from being cut by the drill at the time of drilling, generation of a crack between the electrode layers and the dielectric layer11is restrained.

After the formation of the hole30, a conductor material such as Cu is formed on an inner wall of the hole30by a plating method, as depicted inFIG. 12B, according to the example ofFIG. 10Babove. This results in that the conductor via31is formed on the inner wall of the hole30. For example, a seed layer30ais first formed by electroless plating, and then a plating layer30bis formed by electroplating in which the seed layer30ais used as a current supply layer, to form the conductor via31on the inner wall of the hole30. At the time of formation of the conductor via31, as illustrated inFIG. 12B, the seed layer30aand the plating layer30bare formed also on an upper surface23aof the insulating layer23. This results in that a conductor layer33is formed on the upper surface23aof the insulating layer23. The conductor layer33may be patterned into a given shape.

By the above-mentioned processes, there is obtained a circuit board1A including a structure in which the electrode layer13of the capacitor10is electrically coupled to the conductor via31in the hole30through the coupling via32, the conductor layer34, the coupling via35and the conductor layer33.

In the circuit board1A, the cavity40in a central area of the conductor via31which is a conformal via may be filled with a resin (not illustrated) such as epoxy resin. In the circuit board1A, the hole30may be filled with a conductor material, to form a filled via.

While an example in which the formation of a single build-up layer2is followed by the formation of the hole30by drilling and the formation the conductor via31in the hole30has been described here, the formation of the hole30and the conductor via31may be conducted after the formation of two or more build-up layers. The drilling enables formation of a hole30in a given opening size even when the number of layers in the circuit board is increased, so that a lowering in the degree of freedom in design in realizing a multilayer configuration may be restrained.

As has been described in the second embodiment above, the formation of the hole30and the conductor via31may be conducted after the build-up process is performed once or repeated multiple times, to obtain, for example, the circuit board1A incorporating the capacitor10.

Now, a third embodiment will be described.FIG. 13is a figure illustrating an example of a circuit board according to the third embodiment.FIG. 13illustrates schematically a section of a major part in the example of the circuit board according to the third embodiment.

A circuit board16depicted inFIG. 13differs from the circuit board1, described in the first embodiment above, in that the coupling via32electrically coupling the conductor layer33on the insulating layer22and the capacitor10to each other penetrates the dielectric layer11of the capacitor10and is coupled to the electrode layer12on the lower side.

In the circuit board1B, the opening layer12ais provided in a given region of the electrode layer12of the capacitor10, and the opening part13alarger in opening size than the opening part12ais provided in a given region of the electrode layer13.

The conductor via31provided in the hole30penetrating the insulating layer22, the capacitor10and the insulating layer21is provided on the inner side of edges of the opening part12aand the opening part13ain the electrode layer12and the electrode layer13of the capacitor10, and is in a non-contact relation with the electrode layer12and the electrode layer13.

The coupling via32provided in the insulating layer22is provided on the inner side of an edge of the opening part13ain the electrode layer13and on the outer side of an edge of the opening part12ain the electrode layer12, penetrates the dielectric layer11, and is coupled to the electrode layer12.

In the circuit board1B, the conductor via31in the hole30is electrically coupled to the electrode layer12of the capacitor10through the conductor layer33on the insulating layer22and the coupling via32in the insulating layer22. In the circuit board1B, the cavity40may be filled with a resin (not illustrated) such as epoxy resin. A filled via may be formed in the hole30.

As in the circuit board1descried in the first embodiment above and the circuit board1B described in the third embodiment, the conductor via31in the hole30may be selectively and electrically coupled with both of the electrode layer12and the electrode layer13of the capacitor10, by use of the conductor layer33and the coupling via32.

In regard of the circuit board1B described in the third embodiment, the formation of the hole30and the conductor via31may be performed after the build-up process is conducted once or repeated multiple times, to obtain, for example, the circuit board1B incorporating the capacitor10, according to the example described in the second embodiment.

Now, a fourth embodiment will be described.FIG. 14is a figure illustrating an example of a circuit board according to the fourth embodiment.FIG. 14illustrates schematically a section of a major part in the example of the circuit board according to the fourth embodiment.

A circuit board1C depicted inFIG. 14includes a base board24including a wiring24a, the insulating layer21provided on the base board24, the capacitor10provided on the insulating layer21, and the insulating layer22provided on the capacitor10. In the insulating layer22, there are provided the coupling via32awhich is coupled to the electrode layer13of the capacitor10, and the coupling via32which penetrates the dielectric layer11and is coupled to the electrode layer12. A plurality of (here, as an example, three) holes30are provided in such a manner as to penetrate the insulating layer22, the dielectric layer11of the capacitor10, the insulating layer21and the base board24. On an inner wall of each hole30, the conductor via31in a conformal via shape is provided.

The electrode layer12and the electrode layer13of the capacitor10are provided respectively with the opening part12aand the opening part13awhich are larger than the conductor via31. This realizes a structure in which the electrode layer12and the electrode layer13of the capacitor10are both out of contact with the conductor via31in the hole30. Electrical coupling of the conductor via31with the electrode layer12and the electrode layer13of the capacitor10is performed through the conductor layer33provided on the insulating layer22and the coupling via32provided in the insulating layer22.

The inside of the conductor via31is filled with a resin41. Conductor layers36are provided on the upper and lower sides of the conduct via31filled with the resin41. The conductor layers36are formed, for example, by use of a plating method (so-called lid-plating). The conductor layer33provided on the insulating layer22and the conductor layer33provided beneath the base board24are respectively patterned into given shapes together with the conductor layers36, after the formation of the conductor layers36.

Build-up layers2aare respectively provided on the insulating layer22and beneath the base board24. The build-up layers2aeach include the insulating layer23, the coupling via35provided in the hole35apenetrating the insulating layer23and reaching the conductor layer36on the conductor via31, and a conductor layer37provided on the coupling via35. For example, the conductor layer37is used as a terminal for external coupling of the circuit board1C.

FIG. 14illustrate, as an example, three conductor vies31, for example, a conductor via31awhich is not electrically coupled to the capacitor10, and a conductor via31band a conductor via31cwhich are electrically coupled to the capacitor10. In the circuit board1C, the conductor layer37(terminal37a) which is electrically coupled to the conductor via31ais used as a signal terminal. Of the conductor layer37(terminal37b) electrically coupled to the conductor via31band the conductor layer37(terminal37c) electrically coupled to the conductor via31c, one is used as a power supply terminal and the other is used as a GND terminal. This results in that, of the electrode layer12electrically coupled to the conductor via31band the electrode layer13electrically coupled to the conductor via31c, of the capacitor10, one is set to a power supply potential and the other is set to a GND potential.

In the circuit board1C, the electrode layer12and the electrode layer13of the capacitor10are provided with the opening part12aand the opening part13alarger in opening size than the conductor via31, and electrical coupling between the capacitor10and the conductor via31is performed using the coupling via32. This realizes a circuit board1C excellent in reliability and performance in which it is possible to effectively restrain generation of a crack, at the time of drilling, exfoliation at the time of heating due to such a crack, and the resulting lowering in capacitance, in the capacitor10.

While a circuit board1C in which a single build-up layer2aeach is provided on the insulating layer22side and on the base board24side has been described here as an example, the number of the build-up layer or layers2ais not limited to this. The conductor vias31(31a,31b,31c) may be configured as filled vias.

Now, a fifth embodiment will be described. A variety of electronic parts, for example, semiconductor devices such as semiconductor chips and semiconductor packages may be mounted on the circuit boards1,1A,1B,1C and the like as described in the first to fourth embodiments.

FIG. 15is a figure illustrating an example of an electronic device according to the fifth embodiment.FIG. 15illustrates schematically a section of a major part in the example of the electronic device according to the fifth embodiment. The circuit board1C described in the fourth embodiment is taken here as an example. An electronic device50depicted inFIG. 15includes the circuit board1C, and an electronic part60mounted on the circuit board1C. The electronic device50includes a configuration in which the circuit board1C with the electronic part60mounted thereon is mounted on a circuit board70.

The electronic part60is, for example, a semiconductor chip, or a semiconductor package which includes a semiconductor chip. Such an electronic part60is mounted on the circuit board1C. The terminal37a, the terminal37band the terminal37cprovided on the side of that surface of the circuit board1C on which to mount the electronic part60and a terminal61a, a terminal61band a terminal61cprovided in the electronic part60are bonded through bumps62using a solder or the like. This realizes electrical coupling between the electronic part60and the circuit board1C. The terminal61aof the electronic part60is a signal terminal. Of the terminal61band the terminal61cof the electronic part60, for example, the terminal61bis a power supply terminal and the terminal61cis a GND terminal.

The circuit board1C on which the electronic part60is thus mounted is further mounted on the circuit board70. The circuit board70is, for example, a printed circuit board. The terminal37a, the terminal37band the terminal37cwhich are provided on the circuit board70side of the circuit board1C and a terminal71a, a terminal71band a terminal71cwhich are provided on the circuit board70are bonded through bumps72using a solder or the like. This results in that the circuit board1C with the electronic part60mounted thereon and the circuit board70are electrically coupled. The terminal71aof the circuit board70is a signal terminal. Of the terminal71band the terminal71cof the circuit board70, for example, the terminal71bis a power supply terminal and the terminal71cis a GND terminal.

In the electronic device50, power is supplied from the circuit board70to the electronic part60through the bumps72, the circuit board1C and the bumps62. The capacitor10is provided on a power supply line from the circuit board70to the electronic part60. In this example, the electrode layer12of the capacitor10is set to a power supply potential, and the electrode layer13is set to, a GND potential. With the capacitor10provided on the power supply line, a reduction in power supply impedance, variations in power supply voltage, and generation of high-frequency noises are restrained, and a stable operation of the electronic part60is realized.

In the circuit board1C, the electrode layer12and the electrode layer13of the capacitor10are provided with the opening part12aand the opening part13alarger in opening size than the conductor via31, and electrical coupling between the capacitor10and the conductor via31is performed using the coupling via32. This results in realization of a circuit board1C excellent in reliability and performance in which it is possible to effectively restrain generation of a crack at the time of drilling, exfoliation at the time of a test or practical use involving heating, and the resulting lowering in capacitance, in the capacitor10. The use of such a circuit board1C realizes an electronic device50excellent in reliability and performance against heating.

The electronic device50may be further mounted on any of various electronic apparatuses (also called electronic devices). For example, the electronic device50may be mounted on various electronic apparatuses such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio apparatuses, measuring instruments, inspection devices, and manufacturing equipment.

FIG. 16is a figure illustrating an example of an electronic apparatus according to the fifth embodiment.FIG. 16illustrates schematically the example of the electronic apparatus. As illustrated inFIG. 16, the electronic device50as above is mounted (incorporated) on (in) an electronic apparatus80. In the circuit board1C used for the electronic device50, it is possible to effectively restrain generation of a crack at the time of drilling, exfoliation at the time of a test or practical use involving heating, and the resulting lowering in capacitance, in the capacitor10. This realizes an electronic device50excellent in reliability and performance against heating, and realizes an electronic apparatus80on which such an electronic device50is mounted and which is excellent in reliability and performance.

The foregoing merely describes examples. A multiplicity of further modifications and changes are possible by a person skilled in the art, the present, technology is not to be limited to the accurate configurations and application examples described above, and all the corresponding modifications and the equivalence thereof are in the scope of the present technology defined by claims and the equivalence thereof.

Note. According to one aspect of the above embodiments, a circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part, the second opening part having a different size than the first opening part in plan view; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via, provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first conductor via and the second conductor via.