Method of creating aligned vias in ultra-high density integrated circuits

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

FIELD

The present disclosure relates to manufacturing of integrated circuits, and more particularly to formation of vias in ultra-high density integrated circuits.

BACKGROUND

During manufacturing of ultra-high density integrated circuits (UHDICs), such as certain memory chips, metal lines and vias are formed to provide various conductive connections. Pitch between metal lines and vias is typically the smallest pitch between conductive elements of the UHDICs. The metal lines and vias may be formed using a dual damascene process. During the dual damascene process masks are formed for the metal lines and the vias. The masks for the vias can overlay the masks for the metal lines. Due to processing errors, systematic shifts and/or noise, the masks for the vias may not be aligned with the masks for the metal lines. As a result, one or more vias may be spaced closer to one or more of the metal lines, thus further reducing a minimum pitch between metal lines and vias.

This mask layer-to-mask layer overlay error is illustrated byFIGS. 1A-2B, which show metal lines and respective vias.FIGS. 1A and 1Bshow two vias100,102aligned with two metal lines104,106in a direction in which the metal lines104,106are extending, such that two opposing sides108,110of each of the vias100,102are aligned with two opposing sides112,114of each of the metal lines. The vias100,102are disposed along and between ends116,118of the metal lines104,106. The two metal lines104,106may be Vdd and Vss nets (or rails) and are in a same layer Mx. The first metal line104may be connected to a voltage supply and be at a voltage Vdd. The second metal line106may be connected to a reference terminal (or ground) and have a voltage Vss. The first via100may be connected as shown to an interconnect line (not shown), which may be in a layer Mx−1. The aligned metal lines104,106and vias100,102have an associated metal line-to-via pitch S (i.e., distance between each of the metal lines104,106and a corresponding one of the vias100,102that is connected to the other one of the metal lines104,106metal line).

FIGS. 2A and 2Bshow two vias200,202misaligned relative to two metal lines204,206.FIG. 2Ashows the vias200,202offset from the metal lines204,206and having associated metal line-to-via pitch of S′. The metal lines204,206are in a same layer Mx. The first via200may be connected to a voltage supply and be at a voltage Vdd. The second via202may be connected to a reference terminal (or ground) and have a voltage Vss. The first via200may be connected to an interconnect line (not shown), which may be in a layer Mx−1.

UHDICs are typically designed to minimize pitch between circuit elements. This includes minimizing spacing between metal lines and vias. The spacing between metal lines and vias may be set based on a photolithography resolution limit. Minimizing the spacing minimizes associated chip area. However, due to the above-stated mask layer-to-mask layer overlay error, the spacing may be further reduced in certain areas. In a deep sub-100 nanometer (nm) process, overlay of masks becomes a large portion of metal line to via edge placement error. Reduced spacing between Vdd and Vss metal lines and vias can result in a short between circuit elements and/or a breakdown over time of dielectric material between the metal lines and vias. A short can result in a functionality failure. A reliability issue exists if the dielectric between the circuit elements breakdown over time (referred to as a time dependent dielectric breakdown (TDDB)).

SUMMARY

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stack including first layers, where the first layers include a dielectric layer, a capped layer, a hard mask layer, a first film layer, and a first photoresist layer; patterning the first photoresist layer to provide metal line masks; etching the hard mask layer based on the patterned first photoresist layer to form metal line masks in the hard mask layer; ashing the first photoresist layer and the first film layer; and forming second layers on the hard mask layer, where the second layers include a second film layer and a second photoresist layer. The method further includes: patterning the second photoresist layer to form via masks, where the via masks extend across opposing sides of the metal line masks; etching the second film layer and the capped layer based on the patterned second photoresist layer; ashing the second photoresist layer and the second film layer; etching the dielectric layer and the capped layer based on a pattern of the hard mask layer to provide via regions and metal line regions; etching the hard mask layer and the capped layer; and performing dual damascene process operations to form the vias and the metal lines in the via regions and the metal line regions.

In other features, a processing system for processing a substrate and forming vias aligned with metal lines in an integrated circuit is provided. The processing system includes a processor, a memory and one or more applications stored in the memory and including instructions. The instructions are executable by the processor to: form a stack including first layers, where the first layers include a dielectric layer, a capped layer, a hard mask layer, a first film layer, and a first photoresist layer; pattern the first photoresist layer to provide metal line masks; etch the hard mask layer based on the patterned first photoresist layer to form metal line masks in the hard mask layer; and ash the first photoresist layer and the first film layer. The instructions are further executable to: form second layers on the hard mask layer, where the second layers include a second film layer and a second photoresist layer; pattern the second photoresist layer to form via masks, where the via masks extend across opposing sides of the metal line masks; etch the second film layer and the capped layer based on the patterned second photoresist layer; ash the second photoresist layer and the second film layer; etch the dielectric layer and the capped layer based on a pattern of the hard mask layer to provide via regions and metal line regions; etch the hard mask layer and the capped layer; and perform dual damascene process operations to form the vias and the metal lines in the via regions and the metal line regions.

DESCRIPTION

Functionality and reliability issues associated with metal line-to-via spacing may be prevented by increasing design spacing (or pitch) between metal lines and vias. This can however increase area utilized by circuit elements, increase size and costs of associated ICs, cause introduction of additional qualifications in design, and increase overlay management and logistic complexity.

The examples set forth herein include methods of aligning stacked portions of vias and aligning vias to metal lines. The methods include introducing hard mask layers, providing via mask layers patterned and shaped differently than traditional via mask layers, and other unique processing operations. The methods eliminate misalignment errors between metal lines and vias and thus allow a corresponding pitch between metal lines and vias to be minimized. The pitches may be minimized to a photolithography resolution limit. As a result, chip size, cost, and corresponding functionality and reliability issues are minimized. The methods include determining and adjusting dimensions of via masks without impacting metal line-to-via (or metal-to-metal) spacing. The via masks are oversized in a direction perpendicular to a direction at which a corresponding metal line is extending. This assures removal of patterning film layers over etched away portions of the hard mask layers for proper etching of dielectric layers for aligned via formation.

FIG. 3illustrates a method of forming aligned vias and/or other conductive elements of an IC. The method may be referred to as a type of dual damascene process, but includes operations not traditionally performed during a dual damascene process. The method may be performed by the example processing system ofFIG. 18or by another suitable processing system. The operations may be controlled and timed by the control module ofFIGS. 18-19. This method may be performed while manufacturing ICs and/or corresponding layers of the ICs. In an embodiment, the method includes aligning portions of vias and aligning the vias to metal lines. The method includes forming and shaping via masks and layer stacks to provide aligned vias. The method allows for via mask overlay error while providing aligned vias, which decreases chip and system yield losses during manufacturing of ICs. At least some of the operations that may be performed during this method are illustrated inFIGS. 4A-15B.

The method may begin at300. At302, an interconnect layer and/or other layer to which vias and/or metal lines may extend to and/or terminate is formed.FIGS. 4A-4Bshow a portion400of the interconnect layer of an IC being formed. The portion400includes interconnects402,404. The interconnects402,404are separated by dielectric material406.

At304, multiple non-conductive layers including an etch stop layer500, a dielectric layer502, a capped layer504, and a hard mask layer506are formed as an example on the interconnect layer at302.FIGS. 5A-5Bshow formation of the layers500,502,504, and506on the portion400ofFIG. 4A. The dielectric layer502may be a low permittivity (low-k) dielectric film. In an embodiment, the permittivity k of the dielectric layer502is greater than 1 and less than 2.7 Farads per meter (F/m). As an example, the dielectric layer502may be formed of carbon doped silicon oxide SiO2. The capped layer504may be a dielectric film layer formed of a different material than the dielectric layer502. As an example, the capped layer504may be formed of silicon nitride Si3N4. As an example, the hard mask layer506may be formed of titanium nitride TiN.

At306, a first patterning film layer600and a first photoresist layer602is formed.FIGS. 6A-6Cshown formation of the layers600,602including metal line masks604on the hard mask layer ofFIGS. 5A-5B. The metal line masks604are open areas between portions606of the photoresist layer602. In an embodiment, the patterning film layer600is formed of amorphous silicon and/or an anti-reflective coating film. The photoresist layer602may be spun on and is patterned using photolithography to provide the metal line masks604(shown as trenches), which are used in a following operation to etch the hard mask layer506.

At308, exposed portions of the first patterning film layer600and the hard mask layer506are etched using a first composition of etching material (e.g., tetrafluoromethane (CF4)-oxygen (O2) plasma) in areas below the metal line masks604to provide metal line openings (or masks)700in the hard mask layer506. The openings700are between portions702of the hard mask layer506. The etching is stopped on a top surface of the capped layer504. At310, the remainder of the first patterning film layer600and the first photoresist layer602are ashed way.FIGS. 7A-7Cshow the etched hard mask layer506and metal line masks604and etching away of a remainder of the first patterning film layer600and the first photoresist layer602.

At312, a second patterning film layer800and a second photoresist layer802are formed on the hard mask layer506and the capped layer504.FIGS. 8A-8Cshow formation of the second patterning film layer800and the second photoresist layer802including oversized via masks804on the etched hard mask layer506ofFIGS. 7B-7C. The second patterning film layer800may be formed of amorphous silicon and/or an anti-reflective coating film. The second photoresist layer802may be spun on and is patterned using photolithography to provide the via masks804. The via masks804are oversized and used in a following operation to etch the second patterning film layer800and the capped layer504. The via masks804are open areas between portions806of the second photoresist layer802. The via masks804may or may not be centered over respective openings in the hard mask layer506. For example, the via mask804′ is shown inFIG. 8Bas not being centered over opening807in the hard mask layer506. As shown inFIG. 8B, the via mask804′ is offset to the right of a centerline809of the opening807. The oversizing of the via masks804allows for errors in centering the via masks804over the corresponding metal line masks in the hard mask layer506.

The via masks804are shaped to extend over opposing sides808of the line masks700. Each of the via masks804extends perpendicular to one of the metal line masks and over each opposing side808(or edge) of that metal line mask. The via masks804extend in a direction that is sensitive to via alignment errors, such as the errors shown inFIGS. 2A and 2B. As shown, each of the via masks804may extend across one of the metal line masks and over portions of the hard mask layer506. In an embodiment, the via masks804extend past the sides808an amount greater than 0 and less than or equal to 50% of a distance S between the metal line masks (i.e., pitch between to be created metal lines). The via masks open areas of targeted vias in the IC being formed. This process provides overlay error tolerance (or extra margin for overlay errors) during dual damascene process operations.

At314, exposed portions of the second patterning film layer800and the capped layer504are anisotropically etched based on the patterned second photoresist layer802and the second patterning film layer800following the via mask formed at312. Anisotropically etching includes directional plasma dry etching in only a vertical direction (or direction, for example, perpendicular to a plane extending between two adjacent ones of the layers500,502,504and506). This etching may include use of a second composition of etching material (e.g., nitrogen trifluoride (NF3)-oxygen (O2) plasma) different than the first composition.FIGS. 9A-9Cshow the patterning film layer800and the capped layer504ofFIGS. 8B-8Cin an etched state. The anisotropical etching provides oversized via openings (or masks)900in the second patterning film layer800and a via openings902in the capped layer504. The pattern of the etched hard mask layer506is used to align the via openings902in the capped layer504. The etching is stopped at a top surface of the dielectric layer502. The capped layer504is not etched in areas (e.g., area904) below openings (or masks) in the hard mask layer506that are covered by the second patterning film layer800and the second photoresist layer802.

At316, the second photoresist layer802and the second patterning film layer800are ached away.FIGS. 10A-10Cshow the second patterning film layer800and the second photoresist layer802ofFIGS. 9B-9Cremoved from the hard mask layer506. The layers502,504and506remain subsequent to performing this aching process.

At318, exposed portions of the dielectric layer502is anisotropically etched based on patterns of the hard mask layer506and the capped layer504.FIGS. 11A-11Cshows the dielectric layer502anisotropically etched. The hard mask layer506and the capped layer504are each used as a mask layer. The hard mask layer506may be referred to as a first mask layer and the capped layer504may be referred to as a second mask layer. The dielectric layer502is anisotropically etched in areas below the previous removed areas of the hard mask layer506and the capped layer504, as shown. A third composition of etching material (e.g., fluoroform (CHF3) plasma) is used to etch the dielectric layer502. The third composition may be different than the first composition and second composition. The stack of layers during this operation are etched to a depth, such that the depth D of the corresponding trench is equal to a height H of a via to be formed minus the thickness T of the hard mask layer506. The depth D and the thickness T are shown inFIG. 11Aand the height H is shown inFIG. 14C.

At320, exposed portions of the capped layer504are anisotropically etched based on the pattern of the hard mask layer506. A fourth composition of etching material (e.g., nitrogen trifluoride (NF3)-oxygen (O2)-argon (Ar) plasma) may be used to etch the capped layer504.FIGS. 12A-12Cthe capped layer504with additional etched away portions. The fourth composition of etching material may be different than the first composition, second composition and third composition. The openings created by this etching in the capped layer504are designated1200. The dielectric layer502is not etched during this operation.

At322, the dielectric layer502is further etched based on the patterns of the hard mask layer506and the capped layer504.FIGS. 13A-13Cshow the dielectric layer502subsequent to this etching. A fifth composition of etching material (e.g., fluoroform (CHF3) plasma) may be used to etch the dielectric layer502. The fifth composition may match or be different than the third composition of etching material. The fifth composition may be different than the first composition and second composition. The dielectric layer502is etched until via regions1300reach a top surface of the etch stop layer500. This etching of the dielectric layer502also provides open areas, such as open area1302, for metal lines to be formed during a subsequent operation.

At324, the etch stop layer500is anisotropically etched based on a pattern of the hard mask layer506, a pattern of the capped layer504and/or a pattern of the dielectric layer502to extend via regions. A sixth composition of etching material (e.g., hexafluoroethane (C2F6)-oxygen (O2)-argon (Ar) plasma) may be used to perform this etching process.FIGS. 14A-14Cshow the dielectric layer502, the etch stop layer500and the interconnect layer402ofFIGS. 13B-13Cillustrating the etch stop layer subsequent to etching. The fifth composition of etching material may be different than the first composition, second composition, third composition, fourth composition, and fifth composition. At326, the hard mask layer506and the capped layer504are etched away. This may include applying a seventh composition of etching material (e.g., tetrafluoromethane (CF4)-oxygen (O2) plasma) and then an eighth composition of etching material (e.g., nitrogen trifluoride (NF3)-oxygen (O2) plasma). The seventh composition and the eighth composition may be different than the first composition, second composition, third composition, fourth composition, fifth composition and sixth composition. The dielectric layer502is not etched during operations324and326.

Although shown as a single operation, operation328includes multiple operations, which are performed to complete the dual damascene process. At328, a barrier layer1500(e.g., a layer of titanium nitride TiN), a seed layer1502, and an electroplating layer1504are formed in the via regions1300and the metal line regions1302.FIGS. 15A-15Cshow the dielectric layer502, the etch stop layer500and the interconnect layer402ofFIGS. 14A-14Cillustrating formation of the layers1500,1502,1504and chemical mechanical planarization (CMP) of the dielectric layer502and the electroplating layer1504. The seed layer1502may be formed over the barrier layer1500. Electroplating is then performed to fill remainders of the via regions1300and the metal line regions1302not filled by the barrier layer1500and the seed layer1502to provide the electroplating layer1504. The seed layer1502and the electroplating layer1504may be formed of a same or different material and/or composition of materials. Following electroplating, CMP may be performed to remove a top portion of the resulting stack and provide a planar overall top surface1506. The resulting stack includes metal lines1510and vias1512.

The resulting stack provided as shown inFIGS. 14B-14Cincludes spacing between metal line regions and via regions that allow for the formation of the seed layer1502and the electroplating layer1504to form metal lines and vias having a predetermined minimum pitch S. The predetermined minimum pitch S is provided without alignment errors between the metal lines and vias. This allows a designer to minimize the pitch S to be based on for example a photolithography resolution limit. This eliminates reliability errors. The method may end at330.

The above-described method may be applied to high-density memory chips, high density ICs, and/or other applications where a minimum pitch is to be provided between circuit elements, logic circuit elements, analog circuit blocks, digital circuit blocks, etc. Although the above-described method is described with respect to aligning vias to metal lines, the described alignment may be applied when aligning interconnects to contacts (e.g., underlying slotted contacts) and/or when aligning other circuit elements.

The above-described operations are meant to be illustrative examples. The operations may be performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application. Also, any of the operations may not be performed or skipped depending on the implementation and/or sequence of events.

The above-described method includes forming oversized via masks to allow for overlay errors in masks and formation of conductive elements, such as metal lines, vias, interconnects, contacts, etc. The method is scalable to different generations of chip technologies and allows for smaller chip areas and thus size and costs of ICs.

FIG. 16is an example of a portion1600of an IC including metal lines1602and aligned vias1604formed in accordance with the above-described method. In the example shown, two of the metal lines1602are connected respectively to a power supply and a reference terminal. The vias1604may be connected to interconnects or contacts1605. The power supply provides a supply voltage Vdd. The reference terminal is at a voltage potential Vss. As shown, the via1604may be connected to p+and n+doped regions of a complementary metal-oxide-semiconductor (CMOS) inverter circuit including a p-channel metal-oxide-semiconductor (PMOS) transistor and a n-channel metal-oxide-semiconductor (NMOS) transistor. P-well and n-well regions of the transistors may be disposed in a base (or bottom most) layer1608. The CMOS inverter circuit may be implemented in, for example, a high-density memory. The transistors have gates1610. An example, of a six-transistor static random-access memory (SRAM) cell, which may include the CMOS inverter circuit and corresponding stack, is shown inFIG. 17.

FIG. 17shows a six-transistor SRAM cell1700of a SRAM memory. The six-transistor SRAM memory cell1700includes: a wordline WL; bitlines BL, BL′; CMOS inverter circuits including respectively transistors P1, N1and P2, N2; and NMOS transistors N3, N4. The transistors P1, P2are connected to a power supply and have source terminals at Vdd. The transistors N1, N2are connect the reference terminal and have source terminals at Vss.

FIG. 18shows a processing system1800configured to perform the method ofFIG. 3. The processing system1800may include various chambers1802and a cluster tool1830programmed to process a substrate according to the method ofFIG. 3. Each of the chambers1802may be used to perform one or more of the operations in the described process. The arrangement and combination of chambers may be altered for purposes of performing operations of a fabrication process. The cluster tool1830is preferably equipped with a control module1832programmed to carry out the method ofFIG. 3. In order to begin the process, a substrate is introduced through a cassette loadlock1840. Robots1842,1843may have blades (e.g., a blade1844) that transfer the substrate between the chambers1802. The processing system1800may receive power from a power source1845.

FIG. 19shows an example of the control module1832. The control module1832may include a photolithography module1900, a mask module1902, a removal module1904, a forming module1906, a dual damascene completion module1908, and/or other modules to perform the operation of the method ofFIG. 3. As an example, the photolithography module1900may perform operations306,312. The mask module1902may perform operations308,314. The removal module1904may perform operations310,316. The forming module1906may perform operations302,304,318,320,322,324,326. The dual damascene completion module1907may perform operation328. The control module1832may execute one or more applications stored in a memory1910. In one embodiment, the modules1900,1902,1903,1906and1908are implemented as applications executed by the control module1832.

In this application, apparatus elements described as having particular attributes or performing particular operations are specifically configured to have those particular attributes and perform those particular operations. Specifically, a description of an element to perform an action means that the element is configured to perform the action. The configuration of an element may include programming of the element, such as by encoding instructions on a non-transitory, tangible computer-readable medium associated with the element.