Circuits and methods for improved FET matching

Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.

BACKGROUND OF THE INVENTION

The present invention is related to circuits and methods for implementing transistor devices, and more particularly to circuits and methods for reducing mismatch across transistor devices.

A typical semiconductor device includes a large number of transistors configured to perform one or more functions germane to the operation of the semiconductor device. In some cases, operation of the semiconductor device may be limited due to mismatches between transistors incorporated on the semiconductor device. Such mismatches include a variance in threshold voltage (VT), length (L) and width (W) across transistors. As some examples, a mismatch in transistors used in a current mirror or differential pair can lead to subtle operational differences that may in some cases be fundamental to proper operation.

FIGS. 1a-1bshow an exemplary current mirror100and an exemplary differential input pair150where a mismatch in transistors results in an undesirable operational variance. Current mirror100includes a PMOS transistor102and two resistors104,106. In addition, current mirror100includes three NMOS transistors108,110,112. In operation, a voltage (Vin)114is applied to the gate of PMOS transistor102. This causes PMOS transistor102to turn on such that the drain of PMOS transistor102exhibits a voltage near that of the source of PMOS transistor102. The voltage at the drain of PMOS transistor102is applied to the drain of NMOS transistor108, and the gates of NMOS transistors108,110,112. This results in a reference current116(Ir) traversing PMOS transistor102and NMOS transistor108. Currents118,120(Ia, Ib) proportional to reference current116traverse NMOS transistor110and NMOS transistor112, respectively. The following equations describe proportional currents118,120:
Ia=k1*Ir; and
Ib=k2*Ir.
The constant k1is the ratio of the area of NMOS transistor108to NMOS transistor110, and the constant k2is the ratio of the area of NMOS transistor108to NMOS transistor112. As can be readily appreciated, any variance in the width or length in any of NMOS transistor108, NMOS transistor110or NMOS transistor112has a direct impact on the relationship of each of proportional currents118,120.

Turning toFIG. 1b, differential input pair150is depicted. Differential input pair150includes an NMOS transistor152and an NMOS transistor154. The drain of NMOS transistor152is electrically coupled to a resistor156and a positive output164(Vout+), and the drain of NMOS transistor154is electrically coupled to a resistor158and to a negative output160(Vout−). The gate of NMOS transistor152is electrically coupled to a positive input162(Vin+), and the gate of NMOS transistor154is electrically coupled to a negative input160(Vin−). The source of each of NMOS transistors152,154are electrically coupled to each other, and to a current source168. Ideally, when positive input162equals negative input164, the same current (i.e., ½ current source168) should traverse each of resistors156,158such that positive output164equals negative output166. However, where the threshold voltage of NMOS transistor152is different from that of NMOS transistor154, positive output164will not equal negative output166when positive input162equals negative input160. Thus, a variance in threshold voltage across transistors has a direct and undesirable impact on circuit performance.

In some cases variance in threshold voltage, width and length across transistors exhibits an absolute maximum. Thus, an increase in area of a transistor minimizes the impact of any length or width variance. This is, however, contrary to trends in the semiconductor area where reduced transistor sizes are desired. Indeed, as transistor sizes continue to decrease, the impact of variances is becoming more and more significant. Some attempts to reduce the variance have involved decreasing the resolution of semiconductor manufacturing equipment to further limit any variance. While such attempts have generally been successful, a certain variance across transistors is still expected.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for implementing transistors.

BRIEF SUMMARY OF THE INVENTION

The present invention is related to circuits and methods for implementing transistor devices, and more particularly to circuits and methods for reducing mismatch across transistor devices.

Various embodiments of the present invention provide methods for reducing the impact of inter-transistor variance. Such embodiments include providing a first and a second matching transistor. The first transistor includes a first channel that varies in cross-sectional width from the source to the drain, and the second transistor includes a second channel that varies in cross-sectional width from the source to the drain. In some cases of the aforementioned embodiments of the present invention, providing the first transistor includes physically shaping the first channel such that a first cross-sectional width of the first channel near the source is less than a second cross-sectional width of the first channel near the drain. Such physical shaping may result in either a smooth edge or a stepped edge on the first channel. In other cases of the aforementioned embodiments, providing the first transistor includes providing a plurality of component transistors with the plurality of component transistors electrically coupled such that the first channel is an effective channel extending from a drain of one of the plurality of component transistors to a source of another of the plurality of component transistors. In some such cases, the plurality of component transistors includes transistors of at least two different sizes resulting in an effective channel that has a first cross-sectional width near the source and a second cross-sectional width near the drain. In particular cases, the first cross-sectional width is less than the second cross-sectional width.

In some particular instances of the aforementioned embodiments, the first transistor is implemented in one side of a differential circuit, and the second transistor is implemented in another side of the differential circuit. In such cases, the area of the first channel may be substantially the same as the area of the second channel. In other particular instances of the aforementioned embodiments, the first transistor is implemented in one stage of a current mirror and the second transistor is implemented in another stage of the current mirror. In such cases, an area of the first channel may be a multiple of the area of the second channel. The multiple may be unity or some other multiple.

Other embodiments of the present invention provide transistors that each include a drain, a source and a channel extending between the drain and the source. A cross-sectional width of the channel near the source is substantially less than a cross-sectional width of the channel near the drain. In some instances of the aforementioned embodiments, the transistor includes a plurality of component transistors that are electrically coupled such that the channel is an effective channel extending from a drain of one of the plurality of component transistors to a source of another of the plurality of component transistors. In particular cases, the plurality of component transistors includes transistors of at least two different sizes and the effective channel has a first cross-sectional width near the source and a second cross-sectional width near the drain, and wherein the first cross-sectional width is less than the second cross-sectional width.

In other instances of the aforementioned embodiments, the transistor is a first transistor with a first drain, a first source and a first channel. In such instances, the first transistor may be part of a matched transistor pair that additionally includes a second transistor. The second transistor includes a second drain, a second source and a second channel extending between the second drain and the second source. A cross-sectional width of the second channel near the second source is substantially less than a cross-sectional width of the second channel near the second drain. In such instances, the transistor pair may be configured as a differential pair where an area of the first channel is approximately the same as the area of the second channel. Alternatively, the transistor pair may be implemented as part of a current mirror. In such cases, a proportional current provided by the current mirror is a reference current multiplied by a ratio of an area of the first channel and an area of the second channel.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is related to circuits and methods for implementing transistor devices, and more particularly to circuits and methods for reducing mismatch across transistor devices.

Field Effect Transistors (FET) exhibit at least two operational conditions including a triode condition and a saturation condition. The saturation condition is described by the following equation:
VDS>VGS−VT,
where VDSis the drain to source voltage drop, and VGSis the gate to source voltage drop. The triode condition is described by the following equation:
VDS<VGS−VT.
When operating in the triode condition, a FET is conducting in an Ohmic manner and is less sensitive to changes in the (VGS−VT) term when compared with operation in the saturation condition. Hence, in the triode condition, variance in VTis less critical in comparison to the impact of variance when operating in the saturation condition.

When operating in the saturation condition, voltage drops in a non-uniform manner from the drain to the source across the device channel. Therefore, voltage applied at the gate of a device exerts a corresponding non-uniform control over the carrier density in the channel. In particular, the voltage drop per unit distance will tend to increase along a line extending from the source to the drain end of a FET. Because of this, devices at the drain end of a FET have a greater influence over the carriers in the channel. The area under the gate located closest to the source end of the FET tends to act more like a device in triode as the gate has less relative influence over the carriers at that location in the device. Hence, the impact of transistor variance is greater near the drain end of the FET than at the source end.

It has been discovered that when series transistors or other combinations of transistors are utilized, better matching between the different transistors may be had without incurring an overall increase in transistor area through use of varied channel shapes. In particular, better matching may be achievable per unit total of transistor area where a transistor channel has a variable width. In one particular case, a variable width that increases from the source to the drain end of the transistor has been found to be favorable.

Some embodiments of the present invention provide for transistor devices that are physically and/or electrically shaped to take advantage of the aforementioned device operation to reduce the impact of variance when compared with a traditional rectangular device of approximately the same area. Various embodiments of the present invention provide for transistor devices that are physically and/or electrically shaped to take advantage of the previously described device operation to provide transistor devices that exhibit susceptibility to variance comparable to that exhibited by traditional rectangular devices implemented in larger areas. One or more embodiments of the present invention shape the transistor by modifying the cross-sectional width of the transistor channel between the drain and source of the transistor. Particular embodiments of the present invention include one or more channels extending from a drain to source where the channel has a greater cross-sectional width near the drain end of the channel compared with the cross-sectional width near the source end of the channel. In some cases, the transition between the source and drain is substantially smooth, while in other cases the transition between source and drain is stepped. Other particular embodiments of the present invention combine a number of rectangular transistors to provide a composite transistor exhibiting a narrower channel cross-section near the source of the device when compared with the channel cross-section near the drain of the device. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other uses for transistors shaped in accordance with the various embodiments of the present invention.

Turning toFIG. 2a, a two transistor layout200is shown including smooth channels where a cross-sectional width of the channels near the drain is greater than the cross-sectional width near the source in accordance with one or more embodiments of the present invention. Transistor layout200is schematically represented by a schematic210. As shown, schematic210includes two NMOS transistors222,224. It should be noted that while NMOS transistors are depicted, PMOS transistors may be used in accordance with the embodiments of the present invention. NMOS transistor222includes a drain212(D1) and a source214(S1). Similarly, NMOS transistor224includes a drain216(D2) and a source218(S2). A common gate220(G) is used for both NMOS transistor222and NMOS transistor224.

As shown, each transistor is shown to include four drains that are electrically coupled to each other (e.g., D1), four sources that are electrically coupled to each other (e.g., S1), and four channels extending between the drain/source pairs. It should be noted that transistors with shaped channels may be formed using only a single drain/source pair, or any number of drain/source pairs in accordance with different embodiments of the present invention. In some cases, it may be desirable to use source/pairs that are powers of two as the shape of the channel is complimentary and use of pairs may provide for certain area efficiencies when implementing such transistors in generally rectangular regions of a semiconductor die.

Transistor layout200includes: two sources214(S1) that are electrically coupled to each other, two drains212(D1) that are electrically coupled to each other, two sources218(S2) that are electrically coupled to one another, and two drains216(D2) that are electrically coupled to each other. In addition, transistor layout200includes four channels240,242,244,246extending between source214(S1) and drain212(D1); and four channels230,232,234,236extending between source218(S2) and drain216(D2). Gate220(G) is disposed above each of230,232,234,236,240,242,244,246. The identified drain, source, gate and channel regions may be created using one or more methods known in the art for manufacturing semiconductor devices. Thus, for example, known doping and metallization techniques may be used to create drain, source, gate and channel regions. In operation, a voltage is applied to gate220causing NMOS transistors222,224to operate in either the triode condition or the saturation condition depending upon the magnitude of the applied voltage.

As shown, each of channels230,232,234,236,240,242,244,246exhibits a smooth transition248between the associated drains and sources. As used herein, the phrase “smooth transition” is used in its broadest form to mean any edge that is substantially free of right angles. Thus, for example, a smooth transition may be a straight edge extending between associated drains and sources. As another example, a smooth transition may be a curvilinear edge extending between associated drains and sources. Also, as used herein, the phrase “physically shaped” is used in its broadest sense to mean any area whose edges or shape are defined physically. Thus, using a masking process capable of defining a tapered channel results in a physically shaped channel. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of smooth transitions that may be used to define channels in accordance with one or more embodiments of the present invention.

Further, each of channels230,232,234,236,240,242,244,246exhibits a cross-sectional width that is narrower near the source end than at the drain end of the respective channel. As used herein, the phrase “cross-sectional width” is used in its broadest sense to mean any distance across a channel that runs substantially perpendicular to the channel. Among other things, transistor layout200takes advantage of the difference in operational characteristics near the source end and the drain end of the channel to reduce the impact in any variance between NMOS transistor222and NMOS transistor224as described above.

In some cases, existing design tools and/or semiconductor manufacturing equipment make it difficult to create a channel exhibiting a smooth transition between a source of one width and a drain of another width. At least in part to accommodate this limitation, some embodiments of the present invention provide transistor layouts that include stepped channels where a cross-sectional width of the channels near one end of the device is greater than that of the other end of the device. Turning toFIG. 2b, a two transistor layout250is shown including stepped channels where a cross-sectional width of the channels near the drain is greater than the cross-sectional width near the source in accordance with other embodiments of the present invention. Transistor layout250is schematically represented by a schematic260. As shown, schematic260includes two NMOS transistors272,274. Again, it should be noted that while NMOS transistors are depicted, PMOS transistors may be used in accordance with the embodiments of the present invention. NMOS transistor272includes a drain262(D1) and a source264(S1). Similarly, NMOS transistor274includes a drain266(D2) and a source268(S2). A common gate270(G) is used for both NMOS transistor272and NMOS transistor274.

Transistor layout250includes: two sources264(S1) that are electrically coupled to each other, two drains262(D1) that are electrically coupled to each other, two sources268(S2) that are electrically coupled to one another, and two drains266(D2) that are electrically coupled to each other. In addition, transistor layout250includes four channels290,292,294,296extending between source264(S1) and drain262(D1); and four channels280,282,284,286extending between source268(S2) and drain266(D2). Gate270(G) is disposed above each of280,282,284,286,290,292,294,296. The identified drain, source, gate and channel regions may be created using one or more methods known in the art for manufacturing semiconductor devices. Thus, for example, known doping and metallization techniques may be used to create drain, source, gate and channel regions. In operation, a voltage is applied to gate220causing NMOS transistors272,274to operate in either the triode condition or the saturation condition depending upon the magnitude of the applied voltage.

As shown, each of channels280,282,284,286,290,292,294,296exhibits a stepped transition298between the associated drains and sources. As used herein, the phrase “stepped transition” is used in its broadest form to mean any edge that includes one or more right angles forming steps. Thus, for example, a stepped transition may include a number of vertical and horizontal transitions that together extend between associated drains and sources. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of stepped transitions that may be used to define channels in accordance with one or more embodiments of the present invention. Further, each of channels280,282,284,286,290,292,294,296exhibits a cross-sectional width that is narrower near the source end than at the drain end of the respective channel. Among other things, transistor layout250takes advantage of the difference in operational characteristics near the source end and the drain end of the channel to reduce the impact in any variance between NMOS transistor272and NMOS transistor274as described above.

Various design tools and/or semiconductor manufacturing equipment make it difficult to create a channel with a sufficiently fine length between steps. At least in part to accommodate this limitation, some embodiments of the present invention provide transistor layouts that include a number of component transistors combined to yield effective channels where a cross-sectional width of the channels near the drain is greater than the cross-sectional width near the source. Turning toFIG. 3, a differential pair300is depicted that is formed of multiple component transistors to yield effective channels where a cross-sectional width of the channels near the drain is greater than the cross-sectional width near the source in accordance with various embodiments of the present invention Differential pair300includes a positive input362(VA) that is applied to the gates of a number of component transistors312,314,316,318,320,332,334,352,354,356. In addition, differential pair300includes a negative input364(VB) that is applied to the gates of a number of other component transistors313,315,317,319,321,333,335,353,355,357. As shown, each of component transistors312,313,314,315,316,317,318,319,320,321,332,333,334,335,352,353,354,355,356,357are NMOS transistors. It should be noted that other embodiments of the present invention may be implemented using PMOS transistors. Based on the disclosure provided herein, one of ordinary skill in the art will recognize various combinations of component transistors that may be used in relation to different embodiments of the present invention.

The drain of component transistor312is electrically coupled to a current output372(IOUTA). The source of component transistor312is electrically coupled to the drain of component transistor314; the source of component transistor314is electrically coupled to the drain of component transistor316; the source of component transistor316is electrically coupled to the drain of component transistor318; the source of component transistor318is electrically coupled to the drain of component transistor320; the source of component transistor332is electrically coupled to the drain of component transistor334; the source of component transistor334is electrically coupled to the drain of component transistor352; the source of component transistor352is electrically coupled to the drain of component transistor354; the source of component transistor354is electrically coupled to the drain of component transistor356; and the source of component transistor356is electrically coupled to a current source360. The drain of component transistor313is electrically coupled to a current output374(IOUTB). The source of component transistor313is electrically coupled to the drain of component transistor315; the source of component transistor315is electrically coupled to the drain of component transistor317; the source of component transistor317is electrically coupled to the drain of component transistor319; the source of component transistor319is electrically coupled to the drain of component transistor321; the source of component transistor333is electrically coupled to the drain of component transistor335; the source of component transistor335is electrically coupled to the drain of component transistor353; the source of component transistor353is electrically coupled to the drain of component transistor355; the source of component transistor355is electrically coupled to the drain of component transistor357; and the source of component transistor357is electrically coupled to a current source360.

The aforementioned component transistors are collected into groups of component transistors. In particular, component transistors312,313,314,315,316,317,318,319,320,321are included in a group310, and are each of a size N*(W/LA). N is the number of fingers included in each of the transistors, W is the width of each of the transistors, and LAis the length of each of the transistors. Component transistors332,333,334,335are included in a group330, and are each of a size (N/K)*(W/LA). N/K is the number of fingers included in each of the transistors. Component transistors352,353,354,355,356,357are included in a group350, and are each of a size (N/K)*(W/LB). LBis the length of each of the transistors.

The combination of component transistors define two effective transistors (i.e., one effective transistor including the component transistors on the left, and the other effective transistor including the component transistors on the right). The left side effective transistor has an effective channel extending from the drain of component transistor312to the source of component transistor356. The right side effective transistor has an effective channel extending from the drain of component transistor313to the source of component transistor357. As an example, where K is greater than one, the number of fingers included in each of the component transistors in group330is less than that of group310. Therefore, the total area of each of the component transistors in group310is greater than that of the component transistors in group330. Further, where the product of(N/K)/LBis less than the product of N/LA, the area of each of the transistors in group350is less than that of group310. By utilizing combinations of different sized component transistors such as those exemplified in differential pair300, the channel extending from the drain to source of the effective transistors may be effectively tapered such that a cross-sectional width near the source is different from the cross-sectional width near the drain. In this particular case, the cross-sectional width near the drain is larger than the cross-sectional width near the source.

Turning toFIG. 4, the aforementioned tapering from drain to source of the effective transistor is shown in the form of an exemplary layout400of differential pair300. Each of component transistors312,313,314,315,316,317,318,319,320,321,332,333,334,335,352,353,354,355,356,357is created from one or more fingers. For example, component transistor313is formed from three fingers451,453,455(i.e., N=3). Each of the fingers in group310has a width W and a length LA. As another example, component transistor333is formed from two fingers461,463(i.e., N/K=2). Each of the fingers in group330has the same width and length as the fingers in group310. As yet another example, component transistor353is formed from two fingers471,473(i.e., N/K=2). Each of the fingers in group350has the same width as the fingers in groups310,330, but a longer length (LB) than that of the fingers in groups310,330. As used herein, the phrase “finger” identifies a transistor element that includes a source element (labeled S), a drain element (labeled D) and a channel element extending between the source and the drain. The length of a finger is the distance from the source element to the drain element, and the width is the distance across a cross section of the channel element extending from the source element to the drain element. As an example, component transistor313is created by electrically coupling the sources of fingers451,453,455together to form a composite source, and by electrically coupling the drains of fingers451,453,455together to form a composite drain. The composite drains and sources are electrically coupled in accordance with the schematic ofFIG. 3.

The effective channels discussed above in relation toFIG. 3extend between the composite drain of component transistor313and the composite source of component transistor357; and between the composite drain of component transistor312and the composite source of component transistor356. As shown, varying the width of transistors that are used results in a tapered effective channel that has a larger cross-sectional width near the drain end (e.g., near the composite drain of component transistor313) than that near the source end (e.g., near the composite drain of component transistor357). As used herein, an effective channel that is shaped through use of different sizes of transistors is referred to as an “electrically shaped” channel or a channel with an “electrical shape”. It should be noted that the example ofFIG. 4results in an effective channel with a particular electrical shape. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a number of other electrical shapes that may be achieved in accordance with different embodiments of the present invention through use of different numbers of component transistors, fingers, and/or finger dimensions.

It should be noted that exemplary layout400is one of many possible layouts that may be implemented in accordance with different embodiments of the present invention. In particular, the various fingers may be aligned to allow for simplified interconnection and/or area savings. In addition, the various fingers may be inter-digitated to co-locate portions of matching transistors. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of layouts, finger widths and/or finger lengths that may be utilized in accordance with the various embodiments of the present invention.

FIG. 5shows a current mirror500formed of multiple component transistors to yield effective channels where a cross-sectional width of the channels near the drain is greater than the cross-sectional width near the source in accordance with some embodiments of the present invention. Similar to that discussed above in relation toFIG. 4, current mirror500may be laid out such that a tapered effective channel is achieved through use of a number of different sizes of component transistors. Again, it should be noted that based on the disclosure provided herein, one of ordinary skill in the art will recognize a number of different electrical shapes that may be achieved for an effective channel in accordance with one or more embodiments of the present invention.

Current mirror500includes three current stages570,580,590. Current stage570generates a reference current504(Ir), and includes a PMOS transistor501and a number of component transistors511,512,513,514,515,531,532,551,552,553. Current stage580generates a proportional current505(Ia) that is proportional to reference current504, and includes a resistor502and a number of component transistors516,517,518,519,520,533,534,554,555,556. Current stage590generates a proportional current506(Ib) that is proportional to reference current504, and includes a resistor503and a number of component transistors521,522,523,524,525,535,536,557,558,559. It should be noted that while current mirror500is implemented using NMOS component transistors, other embodiments of the present invention may be implemented using PMOS component transistors. Based on the disclosure provided herein, one of ordinary skill in the art will recognize various combinations of component transistors that may be used in relation to different embodiments of the present invention.

Each of current stages570,580,590includes an effective NMOS transistor exhibiting an effective channel. In particular, current stage570includes an effective NMOS transistor with an effective channel that extends from the drain of component transistor511to the source of component transistor553; current stage580includes an effective NMOS transistor with an effective channel that extends from the drain of component transistor516to the source of component transistor556; and current stage590includes an effective NMOS transistor with an effective channel that extends from the drain of component transistor521to the source of component transistor559. Ia and Ib vary in proportion to Ir as described by the following equations:

Similar to that described in relation to differential pair300ofFIG. 3, the effective channels are electrically shaped through use of different sizes of component transistors. The aforementioned component transistors a collected into groups of component transistors. In particular, component transistors511,512,513,514,515are included in a group510, and are each of a size N*(W/LA). Component transistors516,517,518,519,520are included in group510, and are each of a size X*N*(W/LA); and component transistors521,522,523,524,525are included in group510, and are each of a size Y*N*(W/LA). N, X*N and Y*N is the number of fingers included in each of the transistors, W is the width of each of the fingers, and LAis the length of each of the fingers. Component transistors531,532are included in a group530, and are each of a size (N/K)*(W/LA). Component transistors533,534are included in group530, and are each of a size X*(N/K)*(W/LA); and component transistors535,536are included in group530, and are each of a size Y*(N/K)*(W/LA). (N/K), X*(N/K) and Y*(N/K) is the number of fingers included in each of the transistors. Component transistors551,552,553are included in a group550, and are each of a size (N/K)*(W/LB). Component transistors554,555,556are included in group550, and are each of a size X*(N/K)*(W/LB); and component transistors557,558,559are included in group550, and are each of a size Y*(N/K)*(W/LB). Again, (N/K), X*(N/K) and Y*(N/K) is the number of fingers included in each of the transistors, and LBis the length of each of the fingers. Accordingly, the equations defining the relationship between Ir, Ia and Ib may be restated as follows:
Ia=Ir*X; and
Ib=Ir*Y.

Turning toFIG. 6, a transistor800including a transistor pinch off point810is shown in relation to a two-dimensional view of a combination small channel area820and large channel area830in accordance with yet other embodiments of the present invention. In particular, transistor800includes a source892, a drain894and a gate896. A channel898extends between source892and drain894under gate896. A two-dimensional view860of channel898is included. Of note, channel898is wider near drain894than near source892. This may be accomplished by using two rectangular areas (i.e., small channel area820and large channel area830) as shown, or by other approaches such as, for example, using three or more rectangular areas or using a tapered area. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of geometries and approaches that may be used in relation to different embodiments of the present invention for implementing a channel with a differential width between the source and drain of a transistor.

As shown, during operation of transistor800, charge distributes toward source892with pinch off point810being established along channel898when a voltage is applied at gate896. Control of charge transfer through channel898is greatest at pinch off point810. Thus, some embodiments of the present invention are implemented to assure that pinch off point810occurs within the channel at a location where the channel is relatively wide. Thus, in this case, transistor800is designed such that pinch off point810occurs within large channel area830. This increases control over the field developed in channel898as larger channel area830provides for less variation in the applied control field. Thus, greater control is had without an increase in the entire width of channel898. It should be noted that some embodiments of the present invention may provide a channel that is substantially the same width near both the source and the drain, but with a bulge around the area where a pinch off point is expected to develop. Such a design may also provide for increased control without requiring an overall expansion of the channel width.

Some methods in accordance with different embodiments of the present invention include providing a transistor with a channel of variable width. The methods further include designing the transistor such that the pinch off point occurs over a region of the channel that is larger than other regions of the channel.

In conclusion, the invention provides novel systems, devices, methods and arrangements for improved FET matching. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, physically shaped transistors in accordance with embodiments of the present invention may include one or more source/drain/channel elements. As another example, electrically shaped transistors in accordance with different embodiments of the present invention may include any number of component transistors of any number of shapes. Such component transistors may be electrically coupled to produce an effective transistor with an effective channel of desired proportions. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.