Methods and apparatus for thinner package on package structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

BACKGROUND

As devices manufactured using integrated circuits continue to shrink, the need for smaller packages for the integrated circuit devices continues to increase. One approach increasingly used to save space on a system circuit board and to reduce the board area used is to provide two or more integrated circuits in a combined, vertically arranged package structure called a “Package on Package” or “PoP” device. The PoP structure reduces the system circuit board area needed for the integrated circuits by combining them into a single package structure, and also eliminates the need for some of the connector traces on the circuit board that would otherwise connect the devices to each other. Through via connections may be used to provide electrical connections between the vertically arranged packaged devices.

For example, a memory module may be the device mounted on an upper package in a PoP structure. The memory module could include one, two or more commodity memory devices such as DDR DRAM, or FLASH devices, as non-limiting examples. The upper package substrate may be a multiple level circuit board, and may be formed of a resin, for example woven glass reinforced epoxy resin such as FR4 or BT resin, ceramic, plastic, film, or other substrate materials.

The bottom surface of the upper substrate may have one or more rows of PoP connectors extending vertically away from the bottom surface of the top substrate. These PoP connectors provide the connections to either the integrated circuit mounted on the bottom package of the PoP device, or, to connections that will be mapped to the system board when the PoP device is finally mounted on the system circuit board.

The bottom package is a substrate with an integrated circuit mounted on it. The integrated circuit may be an “application processor” or “AP”. The upper surface of the bottom package has lands or pads for receiving and electrically connecting to the PoP connectors. For example, if the PoP connectors are rows of solder balls extending from the bottom surface of the upper package, lands or pads on the upper surface of the bottom package will correspond to, and receive, those connectors.

The bottom package of the PoP structure will also have external connectors on it, typically on the bottom side, for making the final connection between the PoP structure and the system circuit board. The bottom package may be a ball grid array (“BGA”) type package and have solder balls arranged in an array on the bottom surface. Thus the PoP device has PoP connectors between the top substrate and the bottom substrate, and, external connector terminals extending from the bottom substrate that are mounted on pads on a system circuit board.

However, as the need for higher performance and higher frequency operation devices increases, the routing used in the PoP structures has become a significant limiting factor. The signal paths, which may include board traces, solder balls, solder bumps or C4 connectors, and bond wires, used to get signals from the devices in the PoP structure to and from the system board are quite long. These paths create IR drops and result in slower systems. Further, the use of PoP devices in portable applications increases the need for ever thinner packages.

The drawings, schematics, and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.

DETAILED DESCRIPTION

The making and using of example and illustrative embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed concepts of the application, and do not limit the scope of the disclosure and do not limit the scope of the appended claims.

Embodiments of the present application, examples of which are now described in detail, provide novel methods and apparatus for PoP structures with reduced thickness and shorter signal routing length. The shorter routing distances of the embodiment PoP structures are particularly advantageous in forming packages for high frequency or high performance devices, however, advantageous use of the embodiments are not limited to those applications. The thinner PoP structures that are obtained using the embodiments are advantageous for providing a thinner overall form factor, which increasingly is demanded for hand held and portable devices such as smartphones, tablet computers, e-readers, PDAs, portable video and music players, cameras, hand held web browser or video receivers, and the like.

FIG. 1depicts, in a three dimensional view, a quarter section of a conventional PoP structure13that includes a ball grid array (“BGA”) package15as the bottom package; and an upper package17mounted over the BGA package in a PoP structure. External connectors extending from the bottom surface of the upper package17inFIG. 1connect to lands or pads on the upper surface of the BGA package15.

The embodiments described in this application have connectors extending from the bottom of the upper package to lands on the upper surface of the bottom package of the PoP structures. In some embodiments, these connectors may be formed as solder balls. However, the embodiments and the various applications for the embodiments are not so limited. Copper connectors, such as copper columns, pillars, or studs, controlled collapse chip connectors (“C4”), copper or solder bumps, and columns of other conductive material may all be used instead of, or along with, the solder balls shown as the example connectors in the figures. Further, the term “solder” as used herein includes both lead containing and lead-free solders. Lead containing solders such as Pb/Sn compositions, and lead-free solders including without limiting the embodiments SnAgCu (“SAC”) compositions for example, are within the term “solder”, which also includes other solder compositions such as eutectics. Various platings and coatings may be used to improve the solderability, reduce oxidation, improve adhesion, improve reflow processes, or improve other characteristics of the connectors. All of these variations are contemplated as alternative embodiments of the embodiments discussed herein, and these alternatives also fall within the scope of the appended claims.

InFIG. 1, the PoP structure13is mounted on a system board21. System board21may be, for example, a printed circuit board. The PoP structure may be mounted using the ball connectors to couple to lands on the system board21in a thermal reflow process. In the reflow process the BGA balls are first placed in alignment with the lands on the system board21which are formed in a correspondence to the BGA balls, the PoP structure is moved to put the BGA balls in contact with the lands on the system board21, and a thermal process is used to cause the BGA balls to melt and reflow and mechanically bond with the circuit board, completing both an electrical and a mechanical connection of the PoP structure to the circuit board. Adhesives may be used to further add mechanical strength, and underfill materials may be used to provide stress relief to the connection between the PoP structure13and the system board21.

As the number of input and output connections for devices increase, the use of these devices in the conventional PoP structure results in thicker structures. As the PoP structure gets thicker, the distance of the paths from the devices on the upper package to the system board increases. A signal path may include a bond pad, bond wire, traces on the upper package, a through hole via through the upper package, a solder ball or copper column connector to the lower package, a solder bump and solder pad to the integrated circuit on the lower package, another through hole via and another solder ball to the system circuit board. This path may have significant voltage drop from the current-resistance (“IR”) in the path. Also, the package height becomes an issue in designing very thin, hand held and portable devices where a thinner package is required. A typical PoP structure as inFIG. 1may be greater than 1.2 millimeters in thickness. This thickness may be too large for certain thin device applications.

FIG. 2depicts in a cross-sectional view a first embodiment of an improved PoP structure30. InFIG. 2, an upper package27is provided having a substrate29. This substrate may be a “core” of a woven glass reinforced epoxy resin. Other substrate materials may be used including, without limitation, BT resin, for example. Materials used in printed circuit board construction such as FR4 may be used for the substrate29. The core has layers of dielectric material separating conductive traces to form a multiple layer circuit board. For example, a pad36for receiving a bond wire35is shown overlying a dielectric layer. Vias and contacts may be used to vertically couple the traces to provide routing and mapping connections. Through vias may be used to provide vertical paths for signals through the substrate, such as through via37, which is formed as a hole extending through the substrate29that is then filled, or lined, with conductive material to complete a vertical connection path. Traces on the bottom surface of upper package27then provide a way to further couple signals to the through via37and up to the upper side of upper package27. The upper package27has a solder mask layer33on both the upper surface and the lower surface. Also shown inFIG. 2is a passivation layer39, which may be an overmolded layer formed, for example, by compression molding of a thermoset molding compound, to protect the through via37, the bond wires35, and the pads36from moisture and thermal stresses. Other overmolding materials may be used such as resins and epoxies.

The upper package27may carry, as an illustrative but non-limiting example, commodity integrated circuit devices31such as memory devices. In this embodiment, devices31may be FLASH, SRAM or DRAM devices. These are shown stacked as two stacked dies. More dies may be mounted to increase the size of the memory provided, or alternatively only one die may be used. Other types of devices may be mounted on substrate29as well. InFIG. 2, bond wires such as35are shown coupling the devices31to the pads such as36on substrate29. However, in alternative arrangements, the bottom memory die may be a “flip chip” and may be bonded to lands on the central portion of the substrate29using solder bumps, or copper connections. In some embodiments a memory module of several vertically stacked dies may be formed as a component, using for example through via connections to couple the stacked memory devices to form a memory module, and the bottom die in the module may be flip chip mounted to the substrate29. All of these arrangements are alternative embodiments contemplated as part of the embodiments, and fall within the scope of the appended claims.

Connectors38form the PoP connectors for the structure ofFIG. 2. These connectors38may be solder or other conductive materials. They may be solder balls, as shown inFIG. 2, but the embodiments are not limited to the use of solder balls, the connectors could be copper columns, copper studs, controlled collapse chip connectors (“C4”), or other connectors used for connecting components to an underlying board or device. Further, the term “solder” as used in this description is not limited to any particular type and lead containing, or lead free, solder may be used. A solder ball of lead and tin (Pb/Sn) or Pb and additional materials may be used. In the alternative, lead free compositions including, as a non-limiting example, tin, silver and copper (“SAC”) may be used. Eutectic compositions may be used to form the connectors. The shape of the connectors38is also not limited to a “ball” shape and columns, pillars, ovoids, towers, squares, rectangles and other shapes may be used.

In the embodiment ofFIG. 2, the PoP connectors38are arranged in rows at the periphery of the substrate29. This arrangement leaves space in the central portion of the bottom surface of the upper package27for a chip mounted beneath it to be placed inside the vertical space provided by the connectors38, and adjacent to the bottom surface of the upper package27. In this manner, the thickness T2for the PoP structure30is reduced. As will be further described below, in additional embodiments, this vertical spacing can be still further reduced by various additional modifications.

InFIG. 2, it should be noted that the upper package could be used in applications other than the PoP structure30. The connectors38may be mounted to a circuit board, for example, and the memory devices37could be used in other applications. Thus, the upper package27has utility other than for the embodiments discussed here.

InFIG. 2, a “coreless” bottom package25is shown beneath the upper package27. This package forms the “BGA” part of the PoP structure and carries an application processor or “AP”42. AP42may be, without limitation, a microprocessor. Alternatives for AP42include the use of application specific integrated circuits (“ASICs”), digital signal processors (“DSPs”), a radio transceiver IC, or other functional device that performs selected desired functions. If the AP42is a processor or microprocessor, then it can be seen that the memory devices31may be program storage, or cache, associated with the AP42; thus, the use of the PoP structure30provides a “system” for use in a device. The system of the PoP structure30then includes several integrated circuits but requires only one portion of the system circuit board.

The bottom package25is built on a coreless substrate41. This package does have some of the features of the upper package27; for example, conductive traces and dielectric layers are shown with vias and contacts, and a solder mask is used to protect the upper and lower surfaces of the substrate41. But the substrate29, or “core”, used in the upper package27is now omitted. As will be further described below, some of the embodiments of the PoP structure disclosed herein use a novel method for manufacturing a coreless substrate with reduced thickness, as41inFIG. 2.

The thickness T2of the PoP structure30is reduced from the thickness a conventional PoP device would achieve. Reducing the thickness by omitting the “core” has several advantages. The path lengths from the devices such as31and42to the system board connections are shortened. Since each path is a voltage drop caused by the product of current through the path multiplied by the resistance of the path (“IR”), a shorter path has a lowered “IR” drop. Further, the shorter paths allow for shorter delay times in signal travel, and thus, allow for higher frequency of operation. The package is also physically thinner as a result of the use of the coreless substrate, which allows for a thinner system package.

InFIG. 2, AP42is shown mounted to the coreless substrate41using a “flip chip” approach; that is, the bond pads on the face of the AP42are “flipped” over so it is “face down”, and the bond pads are connected to traces on the substrate41with conductive material. In this particular embodiment, which is not limiting and is but one alternative, a “board on trace” or “BOT” connection is used. Copper connectors are formed on the bond pads of AP42. These are connected directly to the copper traces on the upper surface of substrate41, forming an electrical connection. Using a BOT approach allows for a finer pitch (smaller spacing between bond pads) of the connections as compared to the more conventional “SOP” or “solder on pad” approach. The SOP approach requires more space between pads formed on the traces, to allow the solder on the pads to reflow with the solder bumps that are then be used on the AP42. However, SOP embodiments may be used to mount AP42to substrate41, and for certain applications this approach may have advantages. All of these alternatives are within the scope of the appended claims.

An underfill material44is shown between the BOT connections underneath the AP42. The underfill is typically dispensed as a liquid using a capillary underfill (“CUF”) approach. A resin or epoxy liquid is flowed beneath the AP42and fills the spaces between the connectors. Room temperature, UV, or thermal curing may be used to cure the material. The underfill provides mechanical strength and stress relief.

Lands or pads51on the upper surface of the coreless substrate41receive the PoP connectors38, which in this embodiment are solder balls. These connectors may be coupled to traces that connect the devices31, for example, to the AP42, or to the external connectors48(shown in this embodiment as solder balls) for connection to the system. Through vias may be formed in substrate41, or vertical connections may be made through a via to an internal trace within the substrate, through another via to a trace on the other surface of the substrate41.

External connectors48may be solder connectors such as solder balls. These solder balls may be arranged in a grid pattern of rows and columns and may cover most of the bottom surface of the substrate41. The external connectors thus form a “ball grid array” or “BGA” and the bottom package25may be referred to as a BGA package. The bottom package25may also have utility other than the PoP structure30; that is, the bottom package25provides a package for AP42which may be used in the PoP structure with memory devices on a PoP package, for example, or bottom package25may be mounted to a circuit board without the PoP package.

FIG. 3depicts an alternative embodiment PoP structure60in a cross-sectional view. Many of the elements ofFIG. 2are shown again inFIG. 3, and for those elements, like reference numerals are used.

InFIG. 3, the upper package67is now also formed on a coreless substrate79. This substrate is formed of a plurality of dielectric layers that may be formed, for example, using a method embodiment that is described below. The layers carry conductive traces and contain vias so that using vias and contacts to the conductive traces, a multiple layer circuit board may be formed of coreless substrate79. A through via77is shown providing electrical connection between the upper surface and lower surface of substrate79. The coreless substrate79is thinner than the substrate29inFIG. 2; thus, the PoP structure60has a thickness T3that is less than that of T2forFIG. 2, where only the lower package was coreless. Here, both the upper and lower packages67and25are coreless. The remaining elements ofFIG. 3are identical toFIG. 2. The space49ofFIG. 3above the AP42and below the upper package67is optional; the space could be smaller or no space provided as inFIG. 2as well. The thickness T3achieved in this embodiment is also less than the thickness that can be achieved using a conventional PoP structure.

InFIG. 4, a further alternative PoP structure80is depicted in another cross sectional view. Many of the elements are identical to those ofFIG. 2and like reference numbers are used for like elements.

InFIG. 4, the upper package27is the same as inFIG. 2, with devices31, bond wires35, pads36, solder mask33, and through via37on a cored substrate29.

The lower package is now referenced as85, to distinguish the differences in the embodiment as compared toFIG. 2. The lower package85has a coreless substrate91, which has an embedded chip42in it. This AP42may be the same type of device as inFIG. 2, but in this embodiment, the AP42is embedded in the substrate91; that is, the body of the AP42lies within the thickness of coreless substrate91instead of being disposed on top of it. PoP connectors38can therefore be made thinner and the PoP structure80can have a thickness T4much less than the conventional approach to a PoP structure. AP42is depicted mounted as a BOT connected device within a cavity formed in the coreless substrate91, so that the upper surface of the AP42and the upper surface of the solder mask93lying over the substrate91may be substantially co-planar, although this feature is not required. Alternatively, the AP42may also extend vertically above the solder mask surface.

The upper package27inFIG. 4is identical to the upper package27inFIG. 2, like reference numerals are used and no further description is needed here.

FIG. 5depicts in a cross-sectional view a PoP structure embodiment100. In this embodiment, the upper package is renumbered107to distinguish this embodiment from the upper package27ofFIG. 2, for example. InFIG. 5, the upper package107is formed of a core substrate109which may be, for example, a woven glass reinforced epoxy resin substrate. A cavity105is formed on the bottom portion of the substrate109. This “cavity down” arrangement allows the body of the AP42, which is mounted on the lower package25, to extend partially into the cavity within the body of the upper package107, and so the thickness T5is again able to be greatly reduced from the thickness that a conventional PoP structure would have. The reduced vertical area needed for the AP42allows the PoP connectors38to be reduced in thickness also.

The remaining elements ofFIG. 5including the lower package25which is a coreless substrate package as inFIG. 2, the devices31on the upper package, the AP42, the external connectors48, are the same as inFIG. 2and like numerals are used. The remaining features of the embodiment100are the same as for the PoP structure30.

FIG. 6depicts another embodiment110in a cross-sectional view. InFIG. 6, PoP structure110has the same “cavity down” upper package as that inFIG. 5for upper package107. The lower package125is now a cored substrate such as a FR4 substrate with woven glass reinforced epoxy resin111. The remaining features ofFIG. 6are identical to those inFIG. 5and like reference numerals are therefore used. The thickness T6of structure110is lowered by the use of cavity105, as inFIG. 5; however the lower PoP package125is now a conventional “cored” substrate111. The use of the cavity down upper package107again allows the thickness T6of the structure110to be less than the thickness that could be achieved in a conventional PoP structure.

FIG. 7depicts the embodiment60ofFIG. 2and further illustrates an example signal path20for the devices in the embodiment. The signal path20illustrates a path from a device31to the upper substrate by a bond wire35, to a copper trace, through a via77to the lower surface of the substrate. The signal path continues through a solder ball connector38to a trace in the coreless substrate of the lower package25, to the AP42, then through a via in the lower package, to a solder ball48and on to the printed circuit board. The vertical portions of the signal path are shortened by the reduced thicknesses achieved by the use of the coreless substrates and the BOT mounting of the embodiments, which greatly reduces the IR drop for the signal paths, improving device performance.

FIG. 8depicts in yet another cross-sectional view an embodiment PoP structure130with reduced warp characteristics. Again, the upper package27is formed using a cored substrate29such as a woven glass reinforced epoxy resin like FR4, while the lower package135in this embodiment is also a cored substrate, numbered here as136. This substrate136has an asymmetric system of circuit layers; the upper surface has, in this example, two layers of dielectric and copper traces137,139stacked vertically, while on the bottom surface of this cored substrate136, a single dielectric layer141is shown. In testing, this arrangement has been shown to reduce the package warp over similar structures with “symmetric” layering. The embodiments may have additional layers on the upper surface of substrate136, or the lower surface, but in all the embodiments, the upper surface of substrate136has a greater number of dielectric layers than the lower surface of substrate135. During thermal cycles and in assembly of the PoP structure, this asymmetric layer arrangement reduces the substrate warp that might otherwise occur.

The remaining features shown inFIG. 8are identical to those in prior embodiments, and like numerals are again used for like elements. Upper package27, including devices31, wire bonds35, pads36, solder mask33, through via37, and cored substrate29are the same as inFIG. 2, for example. Lower substrate135is similar to cored substrate125inFIG. 7, except that the layers of dielectric material137,139and141are arranged in an asymmetric fashion as described above. The connectors48, AP42, and PoP connectors38are arranged as before.

Another aspect ofFIG. 8is that the connections from the AP42to the lower package135are now shown as solder on pad or “SOP” connectors. These are numbered143to distinguish them from the BOT connectors43in other embodiments described above. However, in alternative embodiments, this asymmetric layer substrate arrangement could also be used with the BOT connectors for AP42, as in prior embodiments in the figures above. The SOP connectors143have pads with solder on the substrate135, and the AP42has solder bumps, enabling a solder connection to be formed by using a thermal reflow process. Underfill43is again provided after the AP42is flip chip mounted to substrate136. SOP connections require more distance between connections (greater pitch) and thus cannot achieve the fine pitch resolution of the terminals on AP42that may be achieved using the BOT connections. BOT connections can support a minimum pitch distance of less than 30 microns, for example.

A method embodiment for making the coreless substrates for use with the embodiments is now described. InFIG. 9, an intermediate structure150for forming the coreless substrate is depicted in a cross-sectional view. A carrier158, which may be a glass or metal carrier, is shown with two identical assemblies on either surface in an intermediate stage of the process. Layers of preimpregnated material (“prepreg”)153are resin impregnated paper or cloth that are provided with a layer of conductive material155, such as a copper layer, on one surface. The conductive layer155is adhered temporarily to the carrier158for processing. A laser drill or other drilling mechanism may be used to form openings156to expose the underlying conductive layers155at selected locations. These openings will become vias.

InFIG. 10the structure150is depicted following additional processing steps. To transition fromFIG. 9toFIG. 10, an electroless copper is applied, lithography is used to pattern the electroless layer, electroplating is performed, and additional patterning is performed to define vias156and traces159on the surfaces of the prepreg layers153. These traces159will form internal connections in a multiple layer structure for the coreless substrate.

FIG. 11depicts in a cross sectional view the structure150following additional processing. To transition to the stage depicted inFIG. 11, an additional layer of prepreg162is laminated to the prepreg layers153. Additional metal processes are performed. Again, a laser is used to form openings in areas164, which are vias. Electroless plating is performed, followed by lithographic patterning and electroplating of a copper layer, which is then patterned to form traces165on the outer surfaces of prepreg162. These traces165will form the lands for connection to the AP42integrated circuit, and for the PoP connectors that are to be formed on the upper surface when the coreless substrate is used in one of the embodiment PoP structures.

FIG. 12depicts in a cross-sectional view one of the two coreless substrates ofFIG. 10following additional processing. The substrate is diced or singulated into an individual unit and removed from carrier158, which is no longer shown. The bottom conductive layer155is then patterned to form lands for the BGA balls on the bottom surface of prepreg layer153, the remaining elements such as prepreg layer162, vias164, and traces165,159are arranged as before.

FIG. 13depicts the coreless substrate ofFIG. 12following some additional processing steps. A solder mask layer167is formed on both the upper and lower surfaces of the coreless substrate. The solder mask is then patterned to form openings over the traces and under bump metallization169is plated onto the ball lands. Traces165are ready for mounting the integrated circuit AP42as a BOT device.

FIG. 14depicts in a cross sectional view the finished assembly using the coreless substrate to form bottom package25as shown inFIG. 2above. The integrated circuit AP42is mounted on the central portion of the coreless substrate41. The external connectors48, which may be solder balls, are mounted on the bottom surface. The bottom package25is thus a BGA package and is ready for assembly into the PoP structure30as shown inFIG. 2.

FIG. 15depicts in a flow diagram a method embodiment for forming the coreless substrate as shown above. In step62, an upper package is provided with an IC mounted on an upper surface of a first substrate, with PoP connectors extending from a bottom surface of the first substrate. In step64, a lower package is provided with at least one IC on a second substrate, with lands on an upper surface for receiving the PoP connectors. In step66, an array of external connectors are provided on the bottom of the second substrate for connecting to a circuit board. In step68, the upper and lower package are stacked and bonded together, and the second substrate is a coreless substrate of laminated layers of dielectric and conductors, with no intervening core.

FIG. 16depicts in a flow diagram an alternative method embodiment. In step72, an upper package is provided with an IC on a first substrate with PoP connectors extending from the bottom surface, and a cavity is provided in the central portion of the first substrate. In step74, a lower package is provided with at least one IC on a second substrate, having lands on an upper surface of the second substrate for receiving the PoP connectors. In step76, an array of external connectors is provided on the bottom surface of the second substrate. In step78, the upper package and the lower package are stacked together to form a PoP structure, joining the PoP connectors to the lands on the upper surface of the second substrate, and the IC on the second substrate extends into the cavity on the bottom surface of the first substrate. Each of the methods provides embodiments with reduced signal length and thinner PoP structures when compared to the conventional approaches. In a test vehicle, use of the embodiments enabled a PoP structure that had a thickness reduced by 30% and lowered below 1 millimeter for a package that, in a conventional PoP structure, had a thickness greater than 1.2 millimeters.

In one embodiment, a semiconductor device structure includes a first integrated circuit package having at least one integrated circuit device mounted on a first substrate, and having a plurality of package on package connectors extending from a bottom surface of the first substrate; and a second integrated circuit package comprising at least another integrated circuit device mounted on a second substrate, having a plurality of lands on an upper surface of the second substrate coupled to the plurality of package on package connectors, and having a plurality of external connectors extending from a second bottom surface of the second integrated circuit package; wherein at least the second substrate comprises a plurality of dielectric layers and conductors stacked together without an intervening core.

In another embodiment, the above structure includes wherein the plurality of package on package connectors are solder. In a further embodiment, the plurality of external connectors are solder. In still another embodiment, the first substrate includes a plurality of dielectric layers and conductors stacked together without an intervening core. In yet another embodiment, the above semiconductor device structure includes the first substrate having a first plurality of dielectric layers on a first surface of a core material, and a second plurality of dielectric layers on a second surface of the core material. In still another embodiment, the first substrate further includes a cavity formed in a central portion of the bottom surface of the first substrate. In another alternative, in the above structure, the at least another integrated circuit device of the second package extends partially into the cavity formed in the central portion of the bottom surface of the first surface. In still a further embodiment, the at least another integrated circuit device is embedded into the second substrate. In yet another embodiment, the at least another integrated circuit device is mounted to the second substrate using board on trace connectors.

In a further embodiment, in the above semiconductor device structure the at least one integrated circuit device is a memory. In still another embodiment, the at least another integrated circuit device is a microprocessor.

In a further alternative embodiment, a semiconductor device structure includes a first integrated circuit package having at least one integrated circuit device mounted on a first substrate, and having a plurality of package on package connectors extending from a bottom surface of the first substrate, and a cavity formed on the bottom surface and extending into the first substrate, the package on package connectors arranged spaced from the cavity; and a second integrated circuit package having at least another integrated circuit device mounted on a second substrate, including a plurality of lands on an upper surface of the second substrate coupled to the plurality of package on package connectors, and further including a plurality of external connectors extending from a bottom surface of the second integrated circuit package; wherein at least a portion of the at least another integrated circuit device extends into the cavity on the bottom surface of the first substrate.

In another embodiment, a method includes providing a first integrated circuit package comprising one or more integrated circuits on an upper surface of a first substrate, and providing a plurality of package on package connectors extending from a lower surface of the first substrate; providing a second integrated circuit package by providing a second substrate having one or more other integrated circuits on an upper surface of the second substrate, the second substrate including a plurality of lands on the upper surface of the second substrate arranged for receiving the plurality of package on package connectors, and further providing a plurality of external connectors extending from a bottom surface of the second substrate; and mounting the first integrated circuit package to the upper surface of the second substrate by bonding the package on package connectors of the first integrated circuit package to the plurality of lands on the second substrate; wherein providing the second substrate includes providing a plurality of dielectric layers and conductors stacked over one another without an intervening core.

In a further embodiment, the above method is performed wherein providing the second substrate includes providing a first dielectric layer with a conductor covering one surface; forming first level vias in the first dielectric layer; forming first level conductive material in the first level vias; forming first level conductive traces over the conductive material in the first level vias; and disposing a second dielectric layer over the conductive traces. In another embodiment, the method continues by forming second level vias in the second dielectric layer; forming conductive material in the second level vias in the second dielectric layer; forming second level conductive traces over the conductive material in the second level vias; and patterning the conductor covering the one surface for receiving external connectors.

In yet another embodiment, in the above methods, the methods include flip chip mounting the one or more integrated circuits to the second level conductive traces of the second substrate. In still a further embodiment, the methods include embedding the one or more integrated circuits into the second substrate.

In an embodiment, a semiconductor device structure includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface of the first substrate, and a cavity formed on the bottom surface and extending into the first substrate. The package on package connectors are arranged spaced from the cavity. The second integrated circuit package includes at least another integrated circuit device mounted on a second substrate, a plurality of lands on an upper surface of the second substrate coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second integrated circuit package. At least a portion of the at least another integrated circuit device extends into the cavity on the bottom surface of the first substrate.

In another embodiment, a package on package device structure includes a first package and a second package. The first package includes a first substrate including a substrate core, a first die bonded to the first substrate, a plurality of connectors extending from a bottom surface of the first substrate, and a cavity in a portion of the bottom surface of the first substrate. The second package includes a second substrate including a plurality of dielectric layers and conductors stacked together without an intervening core, a second die bonded to the second substrate, wherein a bottom portion of the second die is embedded in the second substrate, and wherein a top portion of the second die extends into the cavity in the bottom surface of the first substrate, and a plurality of lands on an upper surface of the second substrate. The plurality of lands is coupled to the plurality of connectors, and the plurality of connectors extends between the first substrate and the second substrate.

In yet another embodiment, a semiconductor device structure includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes at least one integrated circuit device bonded to a first substrate including a core, and having a plurality of package on package connectors extending from a bottom surface of the first substrate and arranged in rows at a periphery of the first substrate. The second integrated circuit package includes at least another integrated circuit device mounted on a second substrate using copper connectors formed on bond pads of the at least another integrated circuit device connected directly to copper traces on an upper surface of the second substrate, including a plurality of lands on the upper surface of the second substrate coupled to the plurality of package on package connectors, and including a plurality of external connectors extending from a bottom surface of the second integrated circuit package. The plurality of package on package connectors extends between the first substrate and the second substrate. The first substrate includes a cavity formed in a central portion of the bottom surface of the first substrate.