Memory device having hardware regulation training

A memory device includes a memory control unit and a write output clock device. The memory control unit is used to provide a write input clock and a first control value. The write output clock device produces a plurality of internal clocks based on the write input clock, and selects a target internal clock from the plurality of internal clocks, and further delays the target internal clock to become a write output clock to a memory unit based on the first control value. The memory unit produces a data signal based on the write output clock. The memory control unit identifies whether the write output clock meets the time-sequence requirements of the memory unit. If the time-sequence requirements are not met, the memory control unit changes the first control value and/or changes the selected target internal clock to change the write output clock.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of China Patent Application No. 201910660657.3, filed on Jul. 22, 2019, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a memory device and, in particular, to a memory device having hardware regulation training.

Description of the Related Art

With the widespread use of dual in-line memory modules (DIMMs) in personal computers and server systems, adjusting the data transmission of DIMMs has become an important issue. DIMM techniques have been developed to include Double-Data-Rate third generation (DDR3) DRAM and the newest Double-Data-Rate fourth generation (DDR4) DRAM. To support the operation of DDR3 and DDR4 in high-frequency environments, DIMM has adopted the topology of a Fly-by structure in order to reduce synchronous noises and improve signal integrity.

In the Fly-by structure, the clock signals, command signals, read/write data and addresses go through each DRAM (dynamic random access memory) particle, and the read/write data is connected to each DRAM particle. Because the clock signals, command signals, read/write data and addresses are delivered to each DRAM particle on the DIMM at different distances, there is a distinct transmission time between the read/write data reaching each DRAM particle on the DIMM. As a result, the present invention provides a memory device to make the clock period of the read/write data comply with the clock period on the DIMM when the read/write data are processed.

BRIEF SUMMARY OF THE INVENTION

In view of this, the present invention proposes a memory device which can regulate the clock period of the read/write data in order to solve the problems mentioned above.

A memory device comprises a memory control unit and a write output clock device. The memory control unit is configured to provide a write input clock and a first control value. The write output clock device is configured to generate a plurality of internal clocks according to the write input clock, and select a target internal clock from among the plurality of internal clocks according to control of the memory control unit. The write output clock device delays the target internal clock based on the first control value to become a write output clock delivered to a memory unit. The memory unit generates a data signal (DQ signal) according to the write output clock, and the memory control unit receives the DQ signal and identifies whether the write output clock meets the time-sequence requirements of memory unit. If the memory control unit identifies that the write output clock fails to meet the time-sequence requirements, the memory control unit adjusts the first control value and/or the selected target internal clock for regulating the write output clock.

DETAILED DESCRIPTION OF THE INVENTION

The following description is an embodiment of the present invention. The purpose of the present invention is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

There is at least one control device set in the memory device. During the period of writing data into DRAM, the control device in the memory device needs to control the data selection signal (DQS signal) between each DRAM particle to be sent at independent time, in order to comply with the time for the DQS signal reaching each DRAM particle and satisfy the time-sequence requirements, such as tDQSS, between the DQS signal and the input clock for DRAM particles. While the DRAM reads data, each DRAM particle has to adjust the time it takes to deliver the read DQS signal to the control device in the memory device, and the input clock and read DQS signal satisfy the time-sequence requirements, such as tDQSCK, for the DRAM particles. Because the clocks of the DQS signals output from different DRAM particles are not identical, the control device in the memory device needs to adjust the input selection clocks of the DQS signals output from different DRAM particles, in order to correctly deliver the data to the control device in the memory device.

For the operation regarding the writing/reading data of DRAM, JEDEC (Joint Electron Tube Engineering Council) provides the standards for the writing/reading regulation function of DRAM. Under JEDEC, the memory device in the present invention has the function of adjusting the write output clock of each of the DRAM particles on the data path, and the memory device is used to compensate for the write offset of the DIMM having a fly-by structure. In addition, Under JEDEC, the memory device in the present invention can adjust the clock differences of the DQS signals output from different DRAM particles in order to correctly deliver the data to the control device in the memory device.

The control device in the memory device can be a controller, a processor, microprocessor or central processing unit (CPU) etc., but the present invention is not so limited.

FIG. 1is a block diagram of an operation for writing data in a memory device100, in accordance with one embodiment of the present invention. As shown inFIG. 1, the memory device100includes a memory control unit102, a write output clock device104, a write output generation device106and a memory unit108etc. In some embodiments, the memory unit108can be a DRAM, SDRAM (synchronous dynamic random-access memory) and so on, and the memory unit108has different DDR storage particles. These DDR storage particles can be connected to the memory control unit102, the write output clock device104and the write output generation device106via the input/output contact.

In some embodiments, the memory control unit102provides a write input clock Tin to the write output clock device104. The write output clock device104can delay the write input clock Tin to generate a write output clock Tout based on the control of the memory control unit102. At the same time, the write output clock device104initially delivers the write output clock Tout to the memory unit108. The DDR storage particles in the memory unit108generate a data signal, such as DQ signal, to the memory control unit102based on the write output clock Tout. According to the DQ signal of the memory unit108, the memory control unit102can identify whether the write output clock Tout complies with the time-sequence requirements. If the memory control unit102identifies that the write output clock Tout fails to comply with the time-sequence requirements for operating the memory unit108, the memory control unit102would control the output clock device104to continuously regulate the write input clock Tin for changing the write output clock Tout to memory unit108.

When the memory control unit102identifies that the write output clock Tout complies with the time-sequence requirements for operating the memory unit108, the write output clock device104delivers the write output clock Tout to the write output generation device106. At the same time, the memory control unit102can also provide the write input data Din to the write output generation device106. According to the write output clock Tout from the write output clock device104, the write output generation device106adjusts the clock period of the write input data Din for generating the write output data Dout to the memory unit108. In addition, the write output clock device104also includes a sampling unit (not pictured). The sampling unit can sample the write output clock Tout, and the sampling unit delivers the sampling result S4to the memory control unit102. According to the sampling result S4, the memory control unit102can identify if the write output clock Tout meets the time-sequence requirements of the memory unit108.

In some embodiments, the memory unit108can receive the write output clock Tout output by the write output clock device104for generating the DQ signal (or data signal) to the memory control unit102. In some other embodiments, the memory unit108can directly receive the DQS signal (or data selection control signal) from the memory control unit102to generate the DQ signal (or data signal) to the memory control unit102. According to the DQ signal, the memory control unit102identifies whether the write output clock Tout meets the time-sequence requirements of the memory unit108, but the present invention is not so limited. The procedures of the operation of the write output clock device104are illustrated in detail below.

FIG. 2is a block diagram of the write output clock device104, in accordance with one embodiment of the present invention. As shown inFIG. 2, the write output clock device104includes a clock delay unit104a, a clock selection unit104b, a sampling unit104c, a first adjustable delay unit104dand a clock phase detection circuit104e. The clock delay unit104ais coupled to the memory control unit102to receive the write input clock Tin. In addition, the clock delay unit104ais also coupled to the clock phase detection circuit104eto receive the second control value S2. Based on the write input clock Tin and the second control value S2, the clock delay unit104agenerates a plurality of internal clocks to the clock selection unit104b. The plurality of internal clocks include a first internal clock T1, a second internal clock T2, a third internal clock T3and a fourth internal clock T4, and the first to fourth internal clocks T1-T4represent different delay clock periods.

In some embodiments, the first internal clock T1and the write input clock Tin have the same clock period. The second internal clock T2is delayed by a quarter of the clock period of the first internal clock T1. The third internal clock T3is delayed by half the clock period of the first internal clock T1. The fourth internal clock T4is delayed by three-quarters of the clock period of the first internal clock T1. However, the present invention is not so limited.

As mentioned above, the clock selection unit104bis coupled to the memory control unit102, the clock delay unit104aand the first adjustable delay unit104d. After the clock selection unit104breceives the plurality of internal clocks including the first to fourth internal clocks T1-T4, based on the selection signal S3output by the memory control unit102, the clock selection unit104bselects one of the plurality of internal clocks as a target internal clock T5. The clock selection unit104boutputs the target internal clock T5to the first adjustable delay unit104d.

The first adjustable delay unit104dis coupled to the memory control unit for receiving the first control value S1output by the memory control unit102. According to the first control value S1, the first adjustable delay unit104ddelays the clock period (or time period) of the target internal clock T5to generate the write output clock Tout. In view ofFIG. 1andFIG. 2, the first adjustable delay unit104dcan deliver the write output clock Tout to the memory unit108, and the memory unit108generates the DQ signal (data signal) to the memory control unit102according to the write output clock Tout. If the memory control unit102identifies that the write output clock Tout fails to comply with the time-sequence requirements for operating the memory unit108based on the DQ signal, the memory control unit102outputs the selection signal S3to control the clock selection unit104b, and the clock selection unit104bselects one of the other internal clocks which are not selected as the target internal clock T5. For example, if the clock selection unit104bselects the first internal clock T1at the first time, the clock selection unit104bselects one of the second to fourth internal clocks as the target internal clock T5at the second time.

At the same time, the memory control unit102can also adjust the first control value S1to the first adjustable delay unit104d. As a result, according to the adjusted first control value S1, the first adjustable delay unit104dadjusts the delay clock period (or time) of the adjusted target internal clock T5for outputting the write output clock Tout to the memory unit108. When the memory control unit102identifies that the write output clock Tout meets the time-sequence requirements of the memory unit108, the memory control unit102stops adjusting the first control value S. The clock selection unit104bstops selecting the other internal clocks, and the first adjustable delay unit104dstop changing the delay clock period (or time) of the target internal clock T5.

In some other embodiments, when the memory control unit102identifies that the write output clock Tout fails to meet the time-sequence requirements of the memory unit108based on the DQ signal, the sampling unit104cin the write output clock device104receives the first internal clock T1and samples the clock period of the write output clock Tout. The sampling unit104ccompares the first internal clock T1to the clock period of the write output clock Tout for outputting the sampling result S4to the memory control unit102. According to the sampling result S4, the memory control unit102can control the clock selection unit104bto select one of a plurality of internal clocks as a target internal clock T5.

When the memory control unit102identifies that the write output clock Tout meets the time-sequence requirements of the operation of the memory unit108, the first adjustable delay unit104ddelivers the write output clock Tout to the write output generation device106.

In some other embodiments, the clock selection unit104bcan select the first to fourth internal clocks T1-T4in order as the target internal clock T5. The steps of the operation of this embodiment are illustrated in detail below.

FIG. 3is a block diagram of the write output clock device300, in accordance with another embodiment of the present invention. Please refer toFIGS. 1-3for illustrating each of the following embodiments. InFIG. 2andFIG. 3, the clock delay unit104ain the write output clock device104is composed of the second initial delay chain302, the second adjustable delay unit304, the clock reverse circuit306and the clock reverse circuit308. The clock selection unit104bin the write output clock device104is composed of the clock selection circuits312,314and318in the write output clock device300. The sampling unit104cin the write output clock device104is composed of the clock selection circuit310, the clock selection circuit316, the first initial delay chain320and sampling circuit322in the write output clock device300. For simplifying the illustration of each of the embodiments in the present invention, the write output clock device104inFIG. 1is replaced by the write output clock device300.

As shown inFIG. 1andFIG. 3, when the write output clock device300receives the write input clock Tin from the memory control unit102, the second initial delay chain302generates the first internal clock T1. In addition, according to the second control value S2output by the clock phase detection circuit104e, the second adjustable delay unit304converts the write input clock Tin to the second internal clock T2. The first internal clock T1is converted as the third internal clock T3by the clock reverse circuit306, and the second internal clock T2is converted as the fourth internal clock T4by the clock reverse circuit308.

Specifically, in some embodiments, the first to fourth internal clocks T1-T4represent different delay clock periods (or time). The delay clock periods represented by the first to fourth internal clocks T1-T4have been described in detail above, and thus are not described again. In some other embodiments, the second internal clock T2is delayed by a quarter of the clock period of the first internal clock T1. The third internal clock T3is delayed by a quarter of the clock period of the second internal clock T2. The fourth internal clock T4is delayed by a quarter of the clock period of the third internal clock T3. However, the present invention is not so limited.

In some embodiments, as shown inFIG. 1, when the memory control unit102outputs the DQS signal to the memory unit108, the DRAM particles in the memory unit108will generate a DQ signal (or data signal) to the memory control unit102according to its own write regulation function. The memory control unit102receives the DQ signal (or data signal). According to the DQ signal, the memory control unit102identifies whether the write output clock Tout meets the time-sequence requirements of the operation of the memory unit108. Specifically, in some other embodiments, by receiving the write output clock Tout, the memory unit108can also generate the DQ signal to the memory control unit102, but the present invention is not so limited.

Because the different firmware units are configured in the memory control unit102, the methods for determining the time-sequence requirements by the memory control unit102according to the DQ signal (or data signal) are not completely identical. When the memory control unit102receives the potential of the DQ signal which is “0”, it represents that the write output clock Tout (or the DQS signal) transmitted to DRAM particles is ahead of time-sequence requirements. Therefore, the memory control unit102delays the write output clock Tout. When the memory control unit102receives the potential of the DQ signal which is “1”, it represents that the write output clock Tout (or DQS signal) transmitted to DRAM particles meets the time-sequence requirements. However, the present invention is not so limited.

InFIG. 1andFIG. 3, when the memory control unit102identifies that the write output clock Tout fails to meet the time-sequence requirements, the memory control unit102begins to the steps of delaying the write output clock Tout (or the steps of hardware regulation). At the initial step, according to the selection signal S3aoutput by the memory control unit102, the clock selection circuit312in the write output clock device300can select and adjust the first internal clock T1to the clock selection circuit318. Then, the clock selection circuit318receives the adjusted first internal clock T1and the selection signal S3cwhich is from the memory control unit102to generate the target internal clock T5. At the same time, the initial setting of the first control value provided by the memory control unit102is zero, but the present invention is not so limited. The first adjustable delay unit104dreceives the first control value S1(equal to zero) and the target internal clock T5to generate the write output clock Tout. At this time, the total delay period of the write output clock Tout is the sum of the delays of the second initial delay chain302, the clock selection circuit312and318, and the first adjustable delay unit104d.

In the initial step, if the DQ signal generated by the memory unit108according to the write output clock Tout is still determined by the memory control unit102to not meet the time-sequence requirements, the memory control unit102would increase the first control value S1to the first adjustable delay unit104dto increase the delay clock period of the write output clock Tout. When the memory control unit102increases the first control value S1that is equal to the second control value S2, the memory control unit102stops the initial step. Specifically, in the initial step, before the first control value S1is equal to the second control value S2, the initial step of delaying the write output clock Tout is stopped as long as the memory control unit102determines that the write output clock Tout meets the time-sequence requirements. When the first control value S1is equal to the second control value S2, if the memory control unit102determines that the write output clock Tout fails to meet the time-sequence requirements, the memory control unit102stops the initial step of the hardware regulation and performs the second step of the hardware regulation.

In the second step of the hardware regulation, the clock selection circuit312in the write output clock device300selects and adjusts the second internal clock T2to the clock selection circuit318according to the selection signal S3aoutput by the memory control unit102. Then, the clock selection circuit318receives the selection signal S3cfrom the memory control unit102and the adjusted second internal clock T2to generate the target internal clock T5. At the same time, the first control value S provided by the memory control unit102is reset to zero, but the invention is not limited thereto. The first adjustable delay unit104dreceives the first control value S1(equal to zero) and the target internal clock T5to generate a write output clock Tout. At this time, the total delay period of the write output clock Tout is the sum of the delays of the second initial delay chain302, the clock selection circuits312and318, and the first adjustable delay unit104d. That is, the total delay of the write output clock Tout in the second step is as the same as the total delay of the write output clock Tout in the initial step.

In the second step, if the DQ signal generated by the memory unit108according to the write output clock Tout is still determined by the memory control unit102to not meet the time-sequence requirements, the memory control unit102adds the first control value S1to the first adjustable delay unit104dfor increasing the delay clock period of the write output clock Tout. In the second step, unlike the initial step, the write output clock device300samples the write output clock Tout through the sampling circuit322, and the sampling circuit322compares the sampled write output clock Tout with a reference clock Tref to output the sampling result S4to the memory control unit102. The sampling unit104cinFIG. 2can be composed of the clock selection circuits310and316, the first initial delay chain320and the sampling circuit322inFIG. 3. It should be noted that the clock selection circuits310and316and the first initial delay chain320delay the first internal clock T1to generate the reference clock Tref.

In the second step, the memory control unit102determines whether the write output clock Tout meets the time-sequence requirements according to the sampling result S4. Since different firmware is configured in the memory control unit102, the ways in which the memory control unit102determines the time-sequence requirements according to the sampling result S4are not completely identical. For example, when the potential of the sampling result S4received by the memory control unit102is “1”, it represents that the write output clock Tout transferred to the DRAM particles still fails to meet the time-sequence requirements. Therefore, when the potential of the sampling result S4received by the memory control unit102is “0”, the memory control unit102stops the second step of performing the hardware regulation. However, the invention is not limited thereto.

When the potential of the sampling result S4received by the memory control unit102is “0”, the sum of the delays of the write output clock Tout is the sum of the delays of the first initial delay chain320, the second initial delay chain302, the clock selection circuits310and316, and the delay of the ½ clock period. At the same time, the sum of the delays of the write output clock Tout is also as the same as the sum of the delays of the following components: the second adjustable delay unit304, the clock selection circuits312and318, and the first adjustable delay unit104d.

When the potential of the sampling result S4received by the memory control unit102is “0”, if the memory control unit102determines that the write output clock Tout fails to meet the time-sequence requirements according to the DQ signal, the memory control unit102continues to perform the third step of the hardware regulation.

In the third step, the memory control unit102outputs the selection signals S3b, S3cto control the write output clock device300. At this time, the write output clock device300selects the third internal clock T3output from the clock reverse circuit306, and the write output clock device300generates the target internal clock T5through the clock selection circuits314and318to output the write output clock Tout. In the initial third step, the memory control unit102resets the first control value S1to zero. If the memory control unit102still determines that the DQ signal generated by the memory unit108according to the write output clock Tout fails to meet the time-sequence requirements, the memory control unit102increases the first control value S1to the first adjustable delay unit104dfor increasing the delay clock period of the write output clock Tout. When the first control value S1increased by the memory control unit102is equal to the second control value S2, the memory control unit102stops the third step. The delay process in the third step is similar to the initial step of the hardware regulation. The significant difference is that the initial step generates the target internal clock T5according to the first internal clock T1, and the third step generates the target internal clock T5according to the third internal clock T3, so it will not be described again.

In the third step, when the first control value is identical to the second control value, if the memory control unit102determines that the write output clock Tout fails to meet the time-sequence requirements according to the DQ signal, the memory control unit102stops the third step of the hardware regulation and performs the fourth step of the hardware regulation.

In the fourth step, the memory control unit102outputs the selection signals S3band S3cto control the write output clock device300. At this time, the write output clock device300selects the fourth internal clock T4output by the clock reverse circuit308and generates the target internal clock T5through the clock selecting circuits314and318to output the write output clock Tout. The delay process in the fourth step is similar to the initial step of the hardware regulation. The difference is that the initial step generates the target internal clock T5according to the first internal clock T1, and the fourth step generates the target internal clock T5according to the fourth internal clock T4, so it will not be described again.

Through the initial step to the fourth step of the hardware regulation mentioned above, it is ensured that the write output clock Tout output by the write output clock device300meets the time-sequence requirements of the memory unit108. In particular, the initial step to the fourth step of the hardware regulation can also ensure that the delay of the write output clock Tout is continuous and linearly increased. In addition, by the four steps of the hardware regulation above, the adjustment of the first control value S1and the switching of the first to fourth internal clocks T1-T4can ensure that the delay of the write output clock Tout with respect to the write input clock Tin is continuous and linearly increased.

After the write output clock Tout is completed according to the hardware regulation of the memory device, the memory control unit102generates the write output data Dout to the memory unit108via the write output generation device106. The operation process for generating the write output data Dout will be described in detail below.

FIG. 4depicts a flow chart of the operation of the write output generation device106, in accordance with one embodiment of the present invention. As shown inFIG. 4, the write output generation device106includes first to fourth data sampling circuits106a-106dand a data selection circuit106e. The write output generation device106is coupled to the memory control unit102to receive the write input data Din, and the write output generation device106is further coupled to the write output clock device104to receive the first to fourth internal clocks T1-T4and the write output clock Tout. When the memory control unit102completes the hardware regulation's steps mentioned above to output an appropriate write output clock Tout, the write output clock device104delivers the first to fourth internal clocks T1-T4to the write output generation device106. Simultaneously, the memory control unit102also outputs the write input data Din to the write output generation device106.

The first data sampling circuit106ain the write output generation device106receives the write input data Din and the third internal clock T3. The first data sampling circuit106aadjusts the clock period of the write input data Din according to the third internal clock T3, and the first data sampling circuit106aoutputs the first internal data D1to the data selection circuit106e.

The second data sampling circuit106bin the write output generation device106receives the write input data Din and the fourth internal clock T4. The second data sampling circuit106badjusts the clock period of the write input data Din in accordance with the fourth internal clock T4. The second data sampling circuit106boutputs the second internal data D2to the data selection circuit106e.

The third data sampling circuit106cin the write output generation device106receives the first internal data D1and the first internal clock T1output from the first data sampling circuit106a. The third data sampling circuit106cadjusts the clock period of the first internal data D1in accordance with the first internal clock T1. The third data sampling circuit106coutputs the third internal data D3to the data selection circuit106e.

The fourth data sampling circuit106din the write output generation device106receives the first internal data D1and the second internal clock T2output from the first data sampling circuit106a. The fourth data sampling circuit106dadjusts the clock period of the first internal data D1in accordance with the second internal clock T2, and the fourth data sampling circuit106doutputs the fourth internal data D4to the data selection circuit106e.

As described above, all of the first to fourth internal clocks T1-T4are generated by the write output clock device104according to the write input clock Tin. The write output generation device106samples the first internal data D1based on the first internal clock T1for generating the third internal data D3. The write output generation device106samples the first internal data D1based on the second internal clock T2for generating the fourth internal data D4. The write output generation device106samples the write input data Din based on the third internal clock T3for generating the first internal data D1. The write output generation device106samples the write input data Din based on the fourth internal clock T4for generating the second internal data D2. As a result, the first to fourth internal data D1-D4respectively correspond to the third internal clock T3, the fourth internal clock T4, the first internal clock T1and the second internal clock T2in order.

In some embodiments, the data selection circuit106ein the write output generation device106selects the first to fourth internal data D1-D4in accordance with the write output clock Tout output by the write output clock device104to output the write output data Dout. For example, if the write output clock Tout is the first internal clock T1, the data selection circuit106eselects the third internal data D3corresponding to the first internal clock T1as the write output data Dout, according to the write output clock Tout. If the write output clock Tout is the third internal clock T3, the data selection circuit106eselects the first internal data D1corresponding to the third internal clock T3as the write output data Dout, in accordance with the write output clock Tout, and so on. In this way, it can be ensured that the write output data Dout output by the data selection circuit106emeets the time-sequence requirements. Specifically, the embodiments described above are merely illustrative, but the invention is not limited thereto.

In some other embodiments, the data selection circuit106emay also select the first to fourth internal data D1-D4as the write output data Dout according to the DQS signal (or data selection control) output by the memory control unit102. Because the memory control unit102can identify the internal clock (one of the first to fourth internal clocks T1-T4) selected by the write output clock device104as the write output clock Tout, the memory control unit102can generate a control signal (e.g., a DQS signal) to the data selection circuit106ebased on the selected internal clock. Therefore, by outputting the DQS signal, the memory control unit102controls the data selection circuit106eto select the first to fourth internal data D1to D4as the write output data Dout.

In addition to the clock cycle adjustment of the operation of writing data from the memory control unit102to the memory unit108, the present invention can also perform operations for reading data from the memory unit108to the memory control unit102. Clock cycle adjustment.

FIG. 5is a block diagram of an operation for reading data in a memory device200, in accordance with one embodiment of the present invention. As shown inFIG. 5, the memory device200includes a memory control unit102, a read input selection circuit103, a read input sampling circuit105, a read input sampling-selection generation circuit107and a memory unit108. The memory control unit102controls the read input sampling-selection generation circuit107to generate a read sampling clock Tr to the memory unit108. The read input sampling-selection generation circuit107has the same circuit architecture as the write output clock device104inFIG. 1. In addition, the memory control unit102can also control the read input selection circuit103and the read input sampling circuit105by read input sampling-selection generation circuit107.

In some embodiments, when the memory unit108receives the read sampling clock Tr, the memory unit108outputs the DQS signal. The memory control unit102samples the DQS signal by the read input selection circuit103and the read input sampling circuit105, and the memory control unit102determines whether the sampling result meets the time-sequence requirements of the read input data of the memory control unit102.

Since different firmware is configured in the memory control unit102, the ways in which the memory control unit102determines the time-sequence requirements according to the DQS signals are not completely identical. For example, when the potential of the DQS signal sampled by the memory control unit102is “0”, it represents that the DQS signal fails to meet the time-sequence requirements of the read input data of the memory control unit102, and the memory control unit102adjusts the read sampling clock Tr. When the potential of the DQS signal sampled by the memory control unit102is “1”, it indicates that the DQS signal meets the time-sequence requirements of the read input data of the memory control unit102. However, the invention is not so limited.

The operation mentioned above ensures that the clock period of the read selection signal S5output by the read input sampling-selection generation circuit107is ¼ clock period earlier than the read sampling clock Tr. As a result, the read input selection circuit103advances by ¼ of the clock period of the DQS signal received by the memory control unit102. This ensures that the input signal (including the DQS signal and the read input data Dr) can be completely delivered to the memory control unit102.

In conclusion, the operation methods of the hardware regulation for a clock, which are proposed by the present invention, can process the clock regulation to the write output clock Tout and read sampling clock Tr. This can ensure that a clock that is adjusted by the hardware regulation can satisfy the monotonic continuity requirements of memory units (include DRAM), which have different operation frequencies. Thus, the write regulation mechanism and the read regulation mechanism of the present invention can make sure that the memory unit satisfies time-sequence requirements such as tDQSS, between the input clock and DQS signal for DRAM particles. Each of the DRAM particles can also output data in accordance with the time-sequence requirements (e.g., tDQSCK) while the memory control unit is reading the data.

While the invention has been described above in terms of a preferred embodiment, it is not intended to limit the scope of the invention, and it should be understood by those of ordinary skill in the art without departing from the spirit and scope of the invention. Instead, the scope of the invention should be determined by the scope of the appended claims.