Method and apparatus for redundancy circuits using power fets

A circuit used in combination with a redundant power supply system to electrically disconnect its failed power supplies. The circuit comprises a power FET, a rectifier and filter circuit, a start-up circuit and a shut-down circuit. The rectifier and filter circuit rectifies an input AC waveform and subsequently filters a resultant DC voltage which is subsequently used to supply an output voltage at an output terminal connected to the power FET. In parallel with the rectifier and filter circuit, the start-up circuit is coupled to a gate of the power FET to ramp the voltage supplied to that gate slowly turning on the power FET. Coupled in parallel with the start-up circuit, the shut-down circuit conducts voltage from the gate thereby turning-off the power FET to preclude current from other power supplies of the redundant power supply system to pass current to its failed power supply.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to the field of electronic circuitry. More 
particularly, the present invention relates to a circuit implemented in 
association with a redundant power supply system to electrically 
disconnect a respective power supply that has failed. 
2. Description of Art Related to the Invention 
It is well known that certain electronic systems are implemented with 
multiple power supplies that provide power, namely output voltages and 
load currents, to one or more of its printed circuit boards. Traces on the 
printed circuit board dedicated as power lines transfer the output 
voltages and load currents to components connected to the printed circuit 
board. These power supplies may be arranged in a redundant fashion in 
which multiple power supplies are dedicated to collectively produce a 
requisite output voltage and load current as shown in FIG. 1. 
In FIG. 1, a redundant power supply system 100 that produces output voltage 
"V.sub.out " is shown. The redundant power supply system 100 includes a 
plurality of power supplies 110a-110n ("n" being arbitrary) coupled to a 
redundancy control circuit 120 that enables V.sub.out to be maintained 
even if one or perhaps more of the power supplies 110a-110n fail. As 
shown, the redundancy control circuit 120 is a plurality of OR'ing diodes 
125a-125n in which the anode of each diode 125a-125n is uniquely coupled 
to one of the plurality of power supplies 110a-110n and its cathode is 
coupled to a common node 130. This prevents V.sub.out from dropping below 
a minimum specified voltage level in the event that one of the plurality 
of power supplies 110a-110n fails. Instead, the remaining power supplies 
that are in operation provide larger load currents in order to compensate 
for the current loss of the failed power supply and maintain the output 
voltage at V.sub.out. 
Although this configuration of the redundancy control circuit 120 using 
OR'ing diodes is effective for a redundant power supply system, it has a 
number of disadvantages. One disadvantage is each diode 125a-125n imposes 
a voltage drop of approximately 0.4 volts ("V"). In light of the fact that 
the sum of the power supplies are collectively providing voltage levels of 
+3.3 V and +5 V, the combined voltage drop experienced by the power 
supplies of a redundant power supply system is quite significant. Hence, 
the conventional redundant power supply systems are somewhat inefficient 
and subject to potential thermal dissipation concerns since multiple 
diodes are implemented within the chassis of the computer system. Another 
disadvantage is that using discrete diode components is somewhat more 
expensive than the circuitry utilized by the present invention. 
SUMMARY OF THE INVENTION 
The present invention relates to a circuit used in combination with a 
redundant power supply system to electrically disconnect its failed power 
supplies. The circuit comprises a power FET, a rectifier and filter 
circuit, a start-up circuit and a shut-down circuit. The rectifier and 
filter circuit is coupled to a secondary winding of a transformer to 
rectify an AC waveform and subsequently filter a resultant DC voltage. The 
DC voltage is supplied to a source of the power FET in an effort to 
produce an output voltage at an output terminal connected to a drain of 
the power FET. 
Connected to be in parallel with the rectifier and filter circuit, the 
start-up circuit is coupled to the secondary winding and the gate of the 
power FET. At power-on of the power supply, it provides an output voltage 
through an internal diode of the power FET. The start-up circuit then 
ramps the voltage supplied to the gate of the power FET until its voltage 
substantially exceeds the DC voltage supplied to the source, which turns 
on the power FET. Thus, the internal diode of the power FET is shunted by 
the low "on" resistance of the power FET which allows a low voltage drop 
allowing load current to flow from the power supply to the output 
terminal. The slow turn-on of the power FET allows a smooth turn-on of the 
current sharing of the power supplies. 
The shut-down circuit is also coupled to the secondary winding and the 
power FET in parallel with the start-up circuit. When the power supply is 
operating, it does not conduct voltage from the gate of the power FET. 
However, if the power supply fails, it conducts voltage from the gate 
thereby turning-off the power FET to preclude current from other power 
supplies of the redundant power supply system to pass current to the 
failed power supply.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
A circuit and method for electrically disconnecting a failed power supply 
of a redundancy power supply system from adversely effecting a requisite 
output voltage applied a load is described herein. In order to provide a 
thorough understanding of the invention, certain specific details are set 
forth such as specific component interconnections and the like. It will be 
evident, however, to those skilled in the art that these specific details 
illustrate one of a number of embodiments that could be utilized by the 
present invention. In other instances, well known circuits have not been 
described in detail in order to avoid obscuring the present invention. 
Referring to FIG. 2A, a first illustrative embodiment of a general computer 
system incorporating the present invention is shown. The computer system 
200 includes a chassis 210 housing a number of printed circuit boards such 
as, for example, a motherboard 220. The motherboard 220 is coupled to a 
plurality of redundant power supply systems 230 typically implemented 
off-board within the chassis 210. Each redundant power supply system 230 
receives AC power from a wall socket 240 via a power cord 250. Although 
not shown, the computer may further includes a display monitor, a cursor 
control device (e.g., mouse, trackball, touchpad, etc.), an alphanumeric 
keyboard and other peripherals (e.g., printers, plotters, modems, etc.), 
all of which are coupled to ports externally visible from the chassis 210. 
As briefly mentioned above, redundant power supply systems 230 receive AC 
power usually from the wall socket 240 and produces various levels of DC 
power for use by its load normally being one or more electronic components 
(e.g., processor) connected to the printed circuit board. These levels of 
DC power may feature DC voltages of +12 V, +5 V and +3.3 V although other 
voltage ranges are not excluded. Each DC voltage level is supplied to the 
motherboard 220 through a respective common power line. The redundant 
power supply systems 230 are preferably coupled in close proximity to 
their respective load to reduce the resistance and inductance effect of 
their power line. 
Referring to FIG. 2B, a second illustrative embodiment of the computer 
system incorporating the present invention is shown. As in FIG. 2A, the 
computer system 200 features a plurality of printed circuit boards housed 
within the chassis 210 including the motherboard 220 and a power 
distribution circuit board 260. The power distribution circuit board 260 
features a redundancy control circuit associated with each power supply of 
the redundancy power supply systems 230. This implementation avoids 
placement of the redundancy control circuit within the power supply or on 
the printed circuit board. The redundancy control circuit precludes 
current from propagating to one of the power supplies if it fails. In this 
embodiment, the power distribution circuit board 260 provides 3.3 V, 5 V 
and 12 V to the motherboard 220. 
Referring now to FIG. 3, a circuit diagram of the redundancy control 
circuit 300 that electrically disconnects a failed power supply by 
precluding current from flowing back to a failed power supply is shown. 
The redundancy control circuit 300 is designed to avoid an appreciable 
power loss as denoted by the use of OR'ing diodes of FIG. 1. It is 
contemplated that the redundancy control circuitry 300 may be employed 
entirely within each power supply of the redundancy power supply system or 
partially employed within the power supply and on either the printed 
circuit board that is receiving power (e.g., a motherboard) or a power 
distribution board as shown in FIG. 2B. 
The redundancy control circuit 300 includes a power FET 310 having a drain 
311, source 312 and gate 313 as well as a rectify and filter circuit 325. 
With respect to its architecture, the drain 311 of the power FET 310 is 
coupled to an output terminal 320. The source 312 of the power FET 310 is 
coupled to a voltage bus line 321 that receives a DC voltage when the 
power supply is turned-on. This DC voltage is obtained by inputting an AC 
waveform from transformer 345 into the rectify and filter circuit 325. The 
rectify and filter circuit 325 includes a first diode 330 having its anode 
coupled to a secondary winding 345 of the transformer 345. The first diode 
330 and a second diode 331 of the rectify and filter circuit 325 are used 
to rectify the AC waveform in order to produce the DC voltage which is 
subsequently filtered by inductors 332 and 333 and capacitors 334 and 335. 
As shown in FIG. 3, the power FET 310 includes an internal diode 314 that 
is forward biased between its source 312 and drain 311. Thus, if a voltage 
"V.sub.gate " applied to the gate 313 of the power FET 310 is 
substantially greater than the voltage applied to the source 312 of the 
power FET 310, the power FET 310 is turned on reducing the voltage drop 
across the internal diode 314 to a nominal value. This allows an output 
voltage "V.sub.out1 ", equivalent to V.sub.out which is a combination of 
voltages provided by the operational power supplies of the system, to be 
applied to the output terminal 320 and load current to propagate through 
the power FET 310 and output voltage terminal 320. Otherwise, the power 
FET 310 is placed in an "Off" state allowing the internal diode 314 to 
preclude current from flowing through the power FET 310 to the voltage bus 
line 321. Such current could cause the combined output voltage to drop 
below the minimum voltage if the failing power supply has an internal 
component in the rectify and filter circuit 325 shorted. 
As further shown in FIG. 3, the redundancy control circuit 300 includes a 
"start-up" circuit 350 and a "shut-down" circuit 360 situated in parallel 
with the start-up circuit 350. The purpose of the start-up circuit 350 is 
to slowly turn on the power FET 310 immediately after powering the power 
supply and to continue to supply power to the output terminal 320. This 
avoids a voltage surge on a gate line 315 coupled to the gate 313 of the 
power FET 310 which would quickly turn-on the power FET 310 and cause a 
voltage surge on the output terminal 320. In contrast, the shut-down 
circuit 360 is used to quickly turn off the power FET 310 in the event 
that the power supply fails to preclude a large current surge from 
propagating from the output terminal 320 to the rectify and filter circuit 
325 through bus line 321. Such failure may be caused by an electronic 
component being shorted or any number of reasons. 
The start-up circuit 350 is coupled between the secondary winding 340 of 
the transformer 345 and the gate line 315. The start-up circuit 350 
includes a third diode 351 having its anode coupled to the secondary 
winding 340 of the transformer 345. A cathode of the third diode 351 is 
coupled to a first resistor 352 which, in turn, is coupled to a third 
capacitor 353, a second resistor 354 and third resistor 355. The other 
leads of the third capacitor 353 and second resistor 354 are coupled to 
ground. As the third capacitor 353 is charged to maintain a voltage, a 
fourth capacitor 356 coupled to the third resistor 355 and in parallel 
with the third capacitor 353 is charged at a time constant "K" which is 
equivalent to the resistance of the third resistor 355 multiplied by the 
capacitance of the fourth capacitor 356. The nominal values of the 
first-fourth resistors and third-fourth capacitors are approximately the 
following: 51 .OMEGA., 100K .OMEGA., 51K .OMEGA., 10K .OMEGA., 1 .mu.F and 
10 .mu.F, respectively. 
In general, the functionality of the components of the start-up circuit 350 
are as follows. The first resistor 352 is used to limit the current 
through diode 351. The second resistor 354 is a discharge resistor for the 
third and fourth capacitors 353 and 356. The second resistor 355 and the 
fourth capacitor 356 form the charging time constant of the start-up 
circuit 350. Lastly, the fourth resistor 357 isolates the fourth capacitor 
356 from the gate 315 of the power FET 310. 
The shut-down circuit 360 is coupled to the second winding 340 of the 
transformer 345 and the gate line 315 for the power FET 310. The shut-down 
circuit 360 includes a fourth diode 361 having its anode coupled to the 
secondary winding 340 of the transformer 345. As current flows through the 
fourth diode 361 as well as the fifth resistor 362, it charges the fifth 
capacitor 363. This precludes a reversed-biased fifth diode 364 from 
conducting voltage away from the gate line 315 until the power supply is 
shut off or fails. This allows a sixth resistor 365 to discharge the fifth 
capacitor 363 very quickly (approximately 1 millisecond) and thereafter 
allowing the fifth diode 364 to discharge voltage from the gate line 315 
through the sixth resistor 365 to ground. It is contemplated that the 
preferred nominal values of the fifth and sixth resistors 362 and 365 as 
well as the fifth capacitor 363 are approximately 51 .OMEGA., 1K .OMEGA., 
and 1 .mu.F, respectively. 
Referring still to FIG. 3, the operations of the redundancy control circuit 
in combination with the transformer of the power supply is described 
herein. In the turn-on sequence, upon powering up the power supply, an AC 
waveform appears on the secondary winding 345 of the transformer 345 which 
is coupled to anodes of the first diode 330, the third diode 351 and the 
fourth diode 361. The AC waveform charges capacitors 334 and 335 through 
the first and second diodes 330-331 as well as the first and second 
inductors 332-333. This produces a main DC voltage output from the power 
supply. Since there is no gate voltage applied to the gate 313 of the 
power FET 310, the power FET 310 is initially in its "off" state. Rather, 
the voltage across the second capacitor 335 may be transferred through the 
internal diode 314 of the power FET 310 to the output terminal 320. 
Concurrently, the AC waveform is applied to the anode of the third diode 
351 which quickly charges the third capacitor 353 because the first 
resistor 352 has a small resistance and the third capacitor 353 has a 
small capacitance. As a result, the fourth capacitor 356 begins charging 
at a rate according to the time constant "K" derived by the product of the 
resistance of the third resistor 355 and the capacitance of the fourth 
capacitor 356. This produces a ramp V.sub.gate voltage applied to the gate 
313 of the power FET 310. When Vgate is approximately 5-10 volts greater 
than the voltage of the source 311 of the power FET 310. The power FET 310 
is turned on allowing load current to flow through the "on" resistance of 
the power FET 310 to flow through and produce the output voltage "Vout1". 
The reason is that the internal diode 314 is shorted so that the voltage 
drop across the "on" resistance at the FET 310 is much less than the 
internal diode 314. 
In the turn-off sequence, if the power supply fails for any reason, 
including a short in its diodes or capacitors (e.g., diodes 330-331, 
capacitors 334-335, etc.) the AC waveform appearing on the secondary 
winding 340 of the transformer 345 disappears. This immediately causes the 
sixth resistor 365 to discharge the voltage on the fifth capacitor 363. 
Thus, the fifth diode 364 now conducts voltage away from the gate 313 of 
the power FET 310 to ground through the sixth resistor 365. By turning off 
the power FET 310, the internal diode 314 now prevents current from 
flowing back into the power supply via the voltage bus line 321 thereby 
operating in a manner similar to the OR'ing diode as shown in FIG. 1. 
However, the voltage drop across the "on" resistance of the power FET 310 
is substantially less than a voltage drop experienced from a discrete 
diode component. 
Referring to FIG. 4, a flowchart illustrating the steps necessary for the 
discretionary redundancy circuit to perform certain operations in order to 
preclude current from flowing into a failed power supply is shown. First, 
the power supply has to be powered on causing an AC voltage to appear at 
the transformer T1 and the anodes of the first, third and fourth diodes 
(Step 300). In Step 305, a DC voltage is produced at the source of the 
power FET and load current flows through the internal diode of the power 
FET. Concurrently, in Step 310, the voltage at the gate "V.sub.gate " of 
the power FET is ramped at a rate according to a time constant associated 
with the startup circuit. In Steps 315 and 320, once V.sub.gate is greater 
than the source voltage by a selected voltage, the internal diode 314 of 
the power FET is shunted by the low "on" resistance of the power FET 
thereby allowing the power supply to produce the full output voltage 
V.sub.out1. Concurrently with the ramping of V.sub.gate, the fourth diode 
charges the fifth capacitor so that the fifth diode is reversed biased so 
no current is flowing therethrough. In Step 325, in the event that the 
power supply fails and shuts off for whatever reason due to failure of one 
or more of its components or lack of an AC input, the voltage applied to 
the fifth capacitor is discharged by the sixth resistor because no voltage 
is applied to the cathode of the fourth diode. Such discharge is performed 
quickly in order to allow the voltage applied to the gate to be pulled 
towards ground through the diode. Since the fourth resistor is ten times 
greater in resistance than the sixth resistor, the sixth resistor 
essentially pulls the gate of the power FET within ten percent of ground 
almost immediately. This turns off the power FET and the presence of the 
internal diode within the power precludes current flowing back to the 
power supply via the drain of the power FET to its source since other 
power supplies coupled to the output terminal may still be in operation 
(Step 330). 
In view of the foregoing specification, the invention has been described 
with reference to the specific embodiments. However, it is evident that 
various modifications and changes to the above-identified embodiments may 
be made without departing from the spirit and scope of the present 
invention as set forth in the claims which follow.