Construction of integrated circuitry and a method of forming an elevationally-elongated conductive via to a diffusion region in semiconductive material

A construction of integrated circuitry comprises a trench isolation region in semiconductive material. The trench isolation region comprises laterally-opposing laterally-outermost first regions which comprise a first material and a second region laterally-inward of the first regions. The second region comprises a second material of different composition from that of the first material. A diffusion region is in the uppermost portion of the semiconductive material directly against a sidewall of one of the first regions. Insulator material is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the one first region. The conductive via is directly against a top surface of the diffusion region, is directly against an upper portion of a sidewall of the diffusion region, and is directly against a laterally-outer sidewall of the second material of the second region of the trench isolation material. Other embodiments, including method, are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to constructions of integrated circuitry and to methods of forming an elevationally-elongated conductive via to a diffusion region in semiconductive material.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Other programmable materials may be used as a capacitor insulator to render capacitors non-volatile.

A field effect transistor is another type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Regardless, the gate insulator may be programmable, for example being ferroelectric.

Capacitors and transistors may of course be used in integrated circuitry other than memory circuitry. Regardless, a conductive via is an elevationally-extending (e.g., vertical) conductor that is used to electrically connect upper and lower capacitors, transistors, and other integrated circuitry components together. For example, a conductive via may directly electrically couple to a diffusion region (e.g., a source/drain region of transistor) in semiconductive material and extend upwardly therefrom.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass constructions of integrated circuitry and methods of forming an elevationally-elongated conductive via to a diffusion region in semiconductive material. Example embodiments of a method of forming an elevationally-elongated conductive via to a diffusion region in semiconductive material are described initially with reference toFIGS. 1-15.

Referring toFIGS. 1-3, an example fragment of a substrate construction8comprises an array or array area/region10and a peripheral circuitry area/region13that have been fabricated relative to a base substrate11. Base substrate11may comprise any one or more of conductive/conductor/conducting (i.e., electrically herein), semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Various materials are above and within base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS. 1-3-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within a memory array may also be fabricated and may or may not be wholly or partially within a memory array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

Base substrate11comprises semiconductive material12, for example appropriately and variously doped monocrystalline and/or polycrystalline silicon, Ge, SiGe, GaAs, and/or other existing or future-developed semiconductive material. Trench isolation regions14and15in semiconductive material12define active area regions16comprising suitably and variously-doped semiconductive material12. In but in one example embodiment, array area10will comprise memory cells occupying space within outlines75, for example DRAM memory cells, individually comprising a field effect transistor device25and a charge-storage device such as a capacitor85. However, embodiments of the invention encompass fabricating of other memory cells and other constructions of integrated circuitry independent of whether containing memory cells.

Example transistors25are in the form of recessed access devices (a type of construction of a field effect transistor), with example construction8showing such recessed access devices grouped in individual pairs of such devices. Individual recessed access devices25include a buried access line construction18within a trench in semiconductive material12. Constructions18comprise conductive gate material (e.g., conductively-doped semiconductor material and/or metal material) that functions as a conductive gate of individual access devices25. A gate insulator (e.g., silicon dioxide and/or silicon nitride, and not shown) is along sidewalls and a base of the individual trenches between the conductive gate material and semiconductive material12. Insulator material37(e.g., silicon dioxide and/or silicon nitride) is within the trenches above the conductive gate material. Individual devices25comprise a pair of source/drain regions24,26in upper portions of semiconductive material12on opposing sides of the individual trenches (e.g., regions24,26being laterally outward of and higher than access line constructions18). Source/drain regions24and/or26may include other doped regions (not shown), for example halo regions, LDD regions, etc.

One of the source/drain regions (e.g., region26) of the pair of source/drain regions in individual of the pairs of recessed access devices25is laterally between the conductive gate material and is shared by the pair of devices25. Others of the source/drain regions (e.g., regions24) of the pair of source/drain regions are not shared by the pair of devices25. Thus, in the example embodiment, each active area region16in array area10comprises two devices25(e.g., one pair of devices25), with each sharing a central source/drain region26.

A channel region (not numerically designated) is in semiconductive material12below pair of source/drain regions24and26along the trench sidewalls and around the trench base. The channel region may be suitably doped with a conductivity-increasing dopant likely of the opposite conductivity-type of the dopant in source/drain regions24,26. When suitable voltage is applied to the conductive gate material of an access line construction18, a conductive channel forms within the channel region proximate the gate insulator such that current is capable of flowing between a pair of source/drain regions24and26under the access line construction18within an individual active area region16. Stippling is diagrammatically shown to indicate primary conductivity-modifying dopant concentration (regardless of type), with denser stippling indicating greater dopant concentration and lighter stippling indicating lower dopant concentration. Conductivity-modifying dopant may be, and would likely be, in other portions of material12as shown. Only two different stippling densities are shown in material12for convenience, and additional dopant concentrations may be used and constant dopant concentration is not required in any region.

Digitlines30(only one being shown) have been formed and that individually directly electrically couple to the one shared source/drain region26of multiple (not shown) of the individual pairs of devices25. Digitlines30comprise conductive material (e.g., metal material and/or conductively-doped semiconductive material). Elevationally-extending conductive vias34(e.g., metal material and/or conductively-doped semiconductive material, and only one via34being shown) extend downwardly from digitline30. Conductive vias34individually directly electrically couple digitlines30to individual of shared source/drain regions26of the individual pairs of devices25. A pair of capacitors85individually directly electrically couple to one of the other source/drain regions24in the individual pairs of devices25.

Example peripheral circuitry area13comprises a pair of transistors31comprising a pair of source/drain regions32,33having a channel region35there-between. A gate36comprising conductive material is operatively laterally between source/drain regions32,33. A gate insulator38separates gate36from channel region35. Insulator material40(e.g., doped or undoped silicon dioxide and/or silicon nitride) is above the various depicted components in array area10and in peripheral circuitry area13.

Source/drain regions32,33are example diffusion regions32,33to which an elevationally-elongated conductive via (not shown) will connect. In accordance with some embodiments of the invention, diffusion regions32and33need not be source/drain regions of a transistor, and may be any diffusion region. In this document, a “diffusion region” is defined as a region at least partially in semiconductive material and that has conductivity-enhancing dopant therein at a greater concentration than a region of the semiconductive material that is immediately-adjacent the diffusion region, and regardless of how the diffusion region was formed (e.g., regardless of whether formed by diffusion doping, ion implantation, or any other existing or future-developed technique).

Trench isolation regions14,15in semiconductive material12may be of the same size, shape, and/or configuration relative one another (not shown) or may be of different at least one of size, shape, or configuration relative one another. Example trench isolation region15is of different size, shape, and configuration relative to that of a trench isolation regions14. Regardless, and in some embodiments, a particular trench isolation region comprises laterally-opposing laterally-outermost first regions comprising a first material and comprises a second region laterally-inward of the first regions, with the second region comprising a second material of different composition from that of the first material. Example trench isolation region15is shown as comprising laterally-opposing laterally-outermost first regions42,43comprising a first material48and comprising a second region44laterally-inward of first regions42,43. Second region44comprises a second material50that is of different composition from that of first material48. Trench isolation region14comprises laterally-opposing laterally-outermost first regions45,46and a second region47laterally-inward of first regions45,46. Second region47comprises second material50that is of different composition from that of first material48. In one embodiment, the first regions of an individual trench isolation region are individually chemically homogenous, and in one such embodiment the second region is chemically homogenous everywhere laterally between the first regions (e.g., trench isolation region14, not trench isolation region15). In one embodiment, the second region is not chemically homogenous everywhere laterally between the first regions. For example, trench isolation region15is shown as comprising its second region44as comprising second material50and first material48laterally-inward thereof. In one embodiment, first material48is silicon dioxide and second material50is silicon nitride. In one embodiment, the first material and the first regions consist essentially of silicon dioxide and the second material and the second region consist essentially of silicon nitride. In one embodiment and as shown, the first regions are formed to individually be laterally thinner than the second region.

For purposes of the continuing discussion and in some embodiments, the first regions may be considered as having laterally-outer sidewalls60(FIG. 3) and second material50/second region47may be considered as having a laterally-outer sidewall55, in one embodiment a laterally-outermost sidewall55. Further, diffusion region32and/or33may be considered as having a top surface49and a sidewall52. Further, sidewall52may be considered as having some upper portion51and some lower portion53. Diffusion region32and/or33is in an uppermost portion of semiconductive material12and directly against sidewall52of one of first regions45,46.

Referring toFIGS. 4-6, a contact opening62,63, and/or64has been etched through insulator material40to a diffusion region32or33and to trench isolation region15or14. The contact opening laterally overlaps the respective diffusion region and the associated one first region. In one embodiment, the contact opening laterally overlaps the respective second region47or44. In one embodiment, such etching of the contact opening is stopped after etching into insulator material40and ideally after etching completely there-through to the diffusion region and the one first region. Such may, by way of example only, be conducted using photolithographic patterning (with or without pitch multiplication) and any suitable dry anisotropic etching chemistry, and in one embodiment the etching is conducted selectively relative to the diffusion region and the trench isolation region.

Referring toFIGS. 7 and 8, and in one embodiment, a dielectric lining61(e.g., a material of different composition from that of insulator material40, and in one embodiment which comprises second material50) has been formed along sidewalls of contact opening62,63, and/or64. Dielectric lining61may be formed by depositing a conformal layer of material50followed by maskless anisotropic etch thereof to substantially remove such from being over horizontal surfaces. In one embodiment where the contact opening laterally overlaps a second region44or47, dielectric lining61laterally overlaps second region44or47.

Referring toFIGS. 9 and 10, the etching of contact opening62,63and/or64has been continued into first material48of the respective one first region45,46or43selectively relative to second material50of the respective isolation region14or15and selectively relative to diffusion region32and/or33. In one embodiment, such etching is also conducted selectively relative to dielectric lining61when present. Insulator material40and first material48may be of the same or different composition(s) relative one another. If of the same composition, the etching through insulator material40may be conducted as a timed etch to preclude significant etching into first material48prior to forming dielectric lining61when such is so formed. The artisan may select any suitable existing or future-developed etching chemistry for such etching.

Conductive material is ultimately forming in contact opening62,63and/or64directly against a top surface and a sidewall of the diffusion region. In one embodiment and as shown inFIGS. 11 and 12, the conductive material comprises a conductive metal silicide66. Such may be formed by any existing or future-developed technique, for example by reaction of a refractory metal (not shown) with silicon of diffusion region32or33(when such comprises silicon), followed by etching away the refractory metal selectively relative to the formed silicide. In such example and as shown inFIG. 12, such has formed diffusion region32,33to have another top surface67and other sidewalls68and69, with conductive metal silicide66being directly there-against. Conductive metal silicide66is vertically thicker along sidewall68of the diffusion region than above top surface67.

Referring toFIGS. 13-15, additional conductive material70(e.g., titanium nitride) and conductive material71(e.g., elemental tungsten) have been formed within contact openings62,63and64. Accordingly and in one embodiment, conductive material (e.g., a combination of conductive materials66,70, and71) has been formed in the respective contact opening directly against a top surface (e.g.,67) and a sidewall (e.g.,68) of the respective diffusion region. In one embodiment and as shown, the conductive material extends no deeper into the respective diffusion region than two thirds of a maximum depth MD (FIG. 15) of the diffusion region in semiconductive material12. Such may reduce current leakage to substrate material12below that which would otherwise occur if the conductive material extends more than two thirds of such maximum depth and/or may reduce risk of the conductive material extending completely through the source/drain region to substrate material12there-below.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used with respect to the above described embodiments.

In one embodiment, conductive material66/70/71does not laterally overlap second region47and/or44, for example as shown. Alternately, the conductive material does laterally overlap the second region, for example as shown with respect to an alternate embodiment construction8awith conductive vias72ainFIG. 16. Like numerals from the above-described embodiments have been used where appropriate, with some construction difference being indicated with the suffix “a”.FIG. 16also shows an example embodiment devoid of a dielectric lining61(not shown). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention encompass structures and/or devices independent of method of manufacture. Nevertheless, such structures and/or devices may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate and form any of the attributes described with respect to structures and/or devices embodiments.

In some embodiments, a construction (e.g.,10,10a) of integrated circuitry (e.g., existing or future-developed circuitry, for example logic and/or memory) comprises a trench isolation region (e.g.,14or15) in semiconductive material (e.g.,12). The trench isolation region comprises laterally-opposing laterally-outermost first regions (e.g.,45,46or42,43) comprising a first material (e.g.,48) and comprising a second region (e.g.,47or44) laterally-inward of the first regions. The second region comprises a second material (e.g.,50) of different composition from of that of the first material. A diffusion region (e.g.,32or33) is in an uppermost portion of the semiconductive material directly against a sidewall (e.g.,60) of one of the first regions. Insulator material (e.g.,40) is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via (e.g.,72or72a) is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the one first region. The conductive via is directly against a top surface (e.g.,67) of the diffusion region, is directly against an upper portion (e.g.,51) of a sidewall (e.g.,68) of the diffusion region. The conductive via is directly against a laterally-outer sidewall (e.g.,55) of the second material of the second region of the trench isolation material. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

An embodiment of the invention comprises a construction (e.g.,10,10a) of integrated circuitry comprising a trench isolation region (e.g.,14or15) in semiconductive material (e.g.,12) and in some embodiments regardless of whether comprising the above-described first region, second region, first material, and/or second material. A diffusion region (e.g.,32or33) is in an uppermost portion of the semiconductive material and is directly against a sidewall (e.g.,60) of the trench isolation region. Insulator material (e.g.,40) is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via (e.g.,72or72a) is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the trench isolation region. The conductive via is directly against a top surface (e.g.,67) of the diffusion region and is directly against a sidewall (e.g.,68) of the diffusion region. The conductive via comprises a conductive metal silicide (e.g.,66) directly against the top surface and the sidewall of the diffusion region. The conductive metal silicide is vertically thicker (e.g., T2inFIG. 15) along the sidewall of the diffusion region than it is (e.g., T1inFIG. 15) above the top surface. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above” and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Additionally, “metal material” is any one or combination of an elemental metal, a mixture or an alloy of two or more elemental metals, and any conductive metal compound.

Herein, “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method of forming an elevationally-elongated conductive via to a diffusion region in semiconductive material comprises forming a trench isolation region in semiconductive material. The trench isolation region comprises laterally-opposing laterally-outermost first regions that comprise a first material and a second region laterally-inward of the first regions. The second region comprises a second material of different composition from that of the first material. A diffusion region is formed in an uppermost portion of the semiconductive material directly against a sidewall of one of the first regions. Insulator material is formed above the trench isolation region and the diffusion region. A contact opening is etched through the insulator material to the diffusion region and the trench isolation region. The contact opening laterally overlaps the diffusion region and the one first region. The contact opening is etched into the first material of the one first region selectively relative to the second material of the isolation region and selectively relative to the diffusion region. Conductive material is formed in the contact opening directly against a top surface and a sidewall of the diffusion region.

In some embodiments, a construction of integrated circuitry comprises a trench isolation region in semiconductive material. The trench isolation region comprises laterally-opposing laterally-outermost first regions which comprise a first material and a second region laterally-inward of the first regions. The second region comprises a second material of different composition from that of the first material. A diffusion region is in the uppermost portion of the semiconductive material directly against a sidewall of one of the first regions. Insulator material is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the one first region. The conductive via is directly against a top surface of the diffusion region, is directly against an upper portion of a sidewall of the diffusion region, and is directly against a laterally-outer sidewall of the second material of the second region of the trench isolation material.

In some embodiments, a construction of integrated circuitry comprises a trench isolation region in semiconductive material. A diffusion region is in the uppermost portion of the semiconductive material directly against a sidewall of the trench isolation region. Insulator material is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the trench isolation region. The conductive via is directly against a top surface of the diffusion region and is directly against a sidewall of the diffusion region. The conductive via comprises a conductive metal silicide directly against the top surface and the sidewall of diffusion region. The conductive metal silicide is vertically thicker along the sidewall of the diffusion region than above the top surface.