Semiconductor package including a power plane and a ground plane

An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

CROSS REFERENCE TO RELATED APPLICATIONS

This disclosure claims priority to U.S. Provisional Patent Application No. 61/430,664, filed Jan. 7, 2011, U.S. Provisional Patent Application No. 61/552,813, filed Oct. 28, 2011, and to U.S. Provisional Patent Application No. 61/556,767, filed Nov. 7, 2011, the entire specifications of which are hereby incorporated by reference in their entireties for all purposes, except for those sections, if any, that are inconsistent with this specification.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly, to techniques, structures, and configurations of power and ground planes for electronic package assemblies.

BACKGROUND

Integrated circuit devices, such as transistors, are formed on semiconductor dies or chips having features that continue to scale in size to smaller dimensions. The shrinking dimensions of these features are challenging conventional routing configurations of power signals and/or ground signals for semiconductor dies in an electronic package assembly (or semiconductor package). For example, the routing of power signals and/or ground signals using conventional pin technologies for multiple semiconductor dies in a same electronic package assembly may considerably increase manufacturing cost of the electronic package assembly.

FIG. 1Aillustrates an example conventional semiconductor package100that includes a single semiconductor die102(or chip). A central processing unit (CPU)104and a plurality of switches106located along and/or around the periphery of the CPU104are integrated on the single semiconductor die102. In the example ofFIG. 1A, the plurality of switches are coupled to the CPU104via a metal interconnect layer108.FIG. 1Billustrates another example of a conventional semiconductor package108including two separate semiconductor dies—a first semiconductor die including a switch (switch die110) and a second semiconductor die including a CPU (CPU die112). The switch die110is coupled to the CPU die112via a plurality of wirebonds114. In the example ofFIG. 1B, each of the switch die110and the CPU die112respectively have power and ground planes.

In both the examples ofFIGS. 1A-1B, as a result of the switches being located outside of the periphery of the CPU, when power is needed for the interior circuitry within the CPU, traces or electrical connections (not illustrated) typically have to be run from the periphery of the CPU to the interior of the CPU. Power is often lost or wasted along such traces or electrical connections, thus preventing a CPU from utilizing power efficiently which, in turn, affects an overall performance of the CPU.

SUMMARY

In one embodiment, the present disclosure provides an apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

In another embodiment, the present disclosure provides an apparatus that comprises a semiconductor die configured as a central processing unit (CPU). The apparatus also comprises a switching array disposed on a surface of the CPU. The switching array is communicatively coupled to the CPU.

DETAILED DESCRIPTION

Embodiments of the present disclosure describe techniques, structures, and configurations for electronic package assemblies having a power/ground arrangement including a power plane and a ground plane, in which the power plane is separate from the ground plane.

FIGS. 2A-2Gillustrate cross-sectional side views of various stages for fabricating a power/ground arrangement200.FIG. 2Aillustrates a silicon layer or semiconductor die202. The semiconductor die202comprises, for example, silicon (Si), silicon-germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), and the like.

In embodiments, a base metal layer (not illustrated) can be included over the semiconductor die202. The base metal layer can include, for example, aluminum (Al), aluminum-copper alloy, copper (Cu), or nickel (Ni). Such a base metal layer can be deposited by processes such as, for example, electrodeposition, evaporation, or a sputtering process. The base metal layer can provide input/output (I/O) functionality for the semiconductor die202. The base metal layer can also serve as a redistribution layer (RDL) for the power/ground arrangement200.

FIG. 2Billustrates an insulating layer206formed over the semiconductor die202. The insulating layer206can be formed with any dielectric material including, epoxy, polyimide, low-k dielectric, silicon dioxide (SiO2), or the like. The insulating layer206separates the respective conducting parts or layers of the power/ground arrangement200from one another and protects the semiconductor die202from other conducting metal layers of the power/ground arrangement200.

A number of device features can be formed in the insulating layer206. The device features can include, for example, bondable traces, a plurality of lines, and a plurality of vias208. As illustrated, the vias208serve as connectors in the insulating layer206to allow a conductive connection between different layers of the power/ground arrangement200. For example, the vias208serve as contacts by connecting the semiconductor die202to different conductors, such as additional metal layers of the power/ground arrangement200. In an embodiment, the vias208are formed of metal, as is known in the art.

In embodiments, an electroplating process, an electrochemical deposition process, or a sputtering process deposits the first metal layer210over the insulating layer206. In yet another embodiment, a damascene process deposits a thin layer of copper that serves as the first metal layer210over the insulating layer206. The first metal layer210can be chemically and mechanically planarized in some embodiments. Those skilled in the art are familiar with such processes and thus, these processes will not be described in greater detail herein.

A plurality of islands212defined by one or more openings213is formed in the first metal layer210. The islands212can have different dimensions and/or shapes with respect to each other if desired. For example, the plurality of islands212generally has a substantially rectangular-shape. In embodiments, the shapes for the plurality of islands212can include, but are not limited to, a substantially square-shape, a substantially oval-shape, and a substantially round-shape.

In an embodiment, the plurality of islands212is located in a center of the first metal layer210. The plurality of islands212provides an electrical pathway between layers of the power/ground arrangement200. The plurality of islands212, as well as the openings213, (in one embodiment) also provides stress relief with respect to the first metal layer210. The location of the plurality of islands212in the center of the first metal layer210provides for a shorter electrical path between the layers of the power/ground arrangement200, as will be discussed in further detail herein. The shorter electrical path leads to better electrical performance, based on less inductance and less resistance being generated.

In an embodiment, the first metal layer210is a solid ground (GND) plane. The first metal layer210isolates the signals on top of the GND plane from the signals below the GND plane. In particular, the first metal layer210isolates the noise for the signals below within the semiconductor die202, especially during high current switching. The plurality of islands212in the first metal layer210is configured to connect a signal, for example, such as VDD, from another layer through the first metal layer210to the semiconductor die202to be discussed in further detail herein. The first metal layer210acting as a solid GND plane helps reduce a drop in voltage within the power/ground arrangement200.

FIG. 2Dillustrates a dielectric layer214formed over the first metal layer210. The dielectric layer214may be formed with any dielectric material including, for example, oxide, polyimide, low-k dielectric, silicon dioxide (SiO2), or the like. The dielectric layer214separates the conducting parts or layers within the power/ground arrangement200from one another and protects the first metal layer210from the other conducting metal layers. In an embodiment, the dielectric layer214is an interlayer dielectric layer.

A number of device features can be formed in the dielectric layer214. The device features may include, for example, bondable traces, a plurality of lines, and a plurality of vias216. The vias216are a connector in the dielectric layer214to connect the first metal layer210and the semiconductor die202to different conductors, such as additional metal layers within the power/ground arrangement200. In an embodiment, the vias216are formed of metal, as is known in the art.

In an embodiment, the vias216in the dielectric layer214can be positioned in locations that correspond to the locations of the vias208of the insulating layer206and islands212. In other words, the vias208,216and islands212can be located in similar positions in their respective layers such that the vias208,216and islands212are substantially aligned relative to one another.

FIG. 2Eillustrates a second metal layer218formed over the dielectric layer214. The second metal layer218can include, for example, aluminum (Al), aluminum-copper alloy, aluminum-silicon alloy, nickel, or copper (Cu). In embodiments, the second metal layer218can be formed over the dielectric layer214using suitable processes that are well known, for example, a physical vapor deposition (PVD) process a sputtering process, an electrodeposition, or an evaporative deposition. Those skilled in the art are familiar with such processes and thus, these processes will not be described herein.

A plurality of islands220, defined by openings224, is formed on the second metal layer218to provide stress relief and to provide electrical pathways. The islands220can have different dimensions and/or shapes with respect to each other if desired. For example, in one embodiment, the plurality of islands220has a substantially rectangular-shape. In other embodiments, the shapes of the plurality of islands220include, but are not limited to, a substantially square-shape, a substantially oval-shape, and a substantially round-shape.

In an embodiment, the plurality of islands220is located in a center of the second metal layer218. The location of the plurality of islands220in the center of the second metal layer218provides for a shorter electrical path from the second metal layer218to a die stacked on top of the power/ground arrangement200, as will be described in further detail herein. The shorter electrical path provides better electrical performance, based on less inductance and less resistance being generated. In an embodiment, some of the plurality of islands220in the second metal layer218are positioned in locations that correspond to the locations of some of the plurality of islands212of the first metal layer210. In other words, some of the plurality of islands220,212are located in similar positions on each of their respective metal layers218,210such that the plurality of islands220,212are substantially aligned.

In an embodiment, the second metal layer218serves as a power plane, which power plane is configured to provide power at the top of the power/ground arrangement200. The second metal layer218receives power from an external device (not illustrated) through a wirebond connection and provides power to the semiconductor die202through the vias208,216and islands212and220aligned with the vias208,216.

A passivation layer (not illustrated) may be formed over the second metal layer218. The passivation layer may be formed with any suitable material including, for example, oxide, nitride, silicon-oxide, silicon-nitride, or the like. The passivation layer is generally chemically or mechanically planarized. The passivation layer is not required to be planarized if desired. The passivation layer protects the underlying metal layers and the fine-line metal interconnections. The passivation layer also prevents the penetration of mobile ions and other contaminations.

Thus, as can be seen, the power/ground arrangement200includes separate ground and power planes (e.g., the first metal layer210and the second metal layer218, respectively) to provide ground and/or power signals to the semiconductor die202. The separate ground and power planes can also provide ground and/or power signals to other dies as will be described in further detail herein.

FIG. 3illustrates a top view of the power/ground arrangement200ofFIGS. 2A-2E. The top view illustrates exposed portions of the semiconductor die202, the second metal layer218, and exposed portions of the first metal layer210, as well as the plurality of islands220in the second metal layer218. The exposed portions of the semiconductor die202and the first metal layer210are located along a periphery of the power/ground arrangement200to allow for wirebond connections to the various layers.

The plurality of islands220provides electrical pathways and, in one embodiment, also provides stress relief. Likewise, the one or more openings224can provide stress relief, some of which may not define islands220. For example, the stress in the second metal layer218results from differences in thermal expansion or from the microstructure of the second metal layer218(intrinsic stress). Locations for the plurality of islands220are illustrated as examples, not as actual placement locations. The plurality of islands220further represent examples without limiting the number, which may be formed in the second metal layer218, as well as without limiting a size, dimension or a shape.

FIG. 3further illustrates examples of multiple contact points. For instance, the contact points provide electrical connections with the bond pads306,308,310coupled to bondwires312at multiple locations. The bond pads306,308,310are generally located along a peripheral edge of the semiconductor die202on exposed portions of the semiconductor die202and the metal layers210and218. For example, bond pad306is located on the second metal layer218, bond pad308is located on an exposed portion of the first metal layer210, and bond pad310is located on an exposed portion of the semiconductor die202.

In an embodiment, the VDDpower from an external device (not illustrated) is received at the bond pad306located on the second metal layer218through the bondwire312. The VDDpower is provided from the second metal layer218to the semiconductor die202through pathways defined by a via216, an island212and a via208(as illustrated inFIGS. 2B-2E). Isolation is provided in the power/ground arrangement200to avoid unwanted interaction of components with each other. For example, the vias208,216make contact with the first metal layer210, which serves as the GND plane appearing to the signals as an infinite ground potential.

In another embodiment, the GND signal is received at the bond pad308of the first metal layer210through the bondwire312. The GND signal can then be provided to the semiconductor die202through a via208. Additionally, the plurality of islands220provide an electrical pathway of the GND signal from the first metal layer210to a second die (not illustrated) that can be stacked on top of the power/ground arrangement200. For example, the electrical pathway of the GND signal can include the first metal layer210to the via216(illustrated inFIG. 2Eof the cross-sectional views), to an island220, and to the second die stacked on top of the power/ground arrangement200.

Additionally, an I/O signal can be received at a bond pad310of the semiconductor die202through a bondwire312, either from an external device (not illustrated) or from the semiconductor die202. Also, an I/O signal can be brought from the semiconductor die202through the second metal layer218and/or to the second die stacked on top of the power/ground arrangement200. For example, the electrical pathway of the I/O signal begins at the semiconductor die202, passes through the via208(illustrated inFIGS. 1B-1Eof the cross-sectional views), and passes through an island212in the first metal layer210(i.e., the GND plane). The electrical pathway further passes through the via216(illustrated inFIG. 1Eof the cross-sectional views), to the second metal layer218(i.e., the power plane), and to the second die stacked on top of the power/ground arrangement200.

The power/ground layout of the power/ground arrangement200increases the I/O functionality by providing multiple bond pad sites located on the semiconductor die202, the first metal layer210, and the second metal layer218for the I/O, GND, and/or power signals through the bondwires312. In addition, the first metal layer210as the GND plane reduces the drop in voltage by providing mechanisms for electrical connections to the different layers in a more efficient manner. Overall, this electronic package assembly reduces the drop in voltage and keeps the size of the electronics package small while increasing I/O functionality and keeping costs down.

The roles of the first metal layer210and the second metal layer218may be reversed such that the first metal layer210is the power plane and the second metal layer218is the GND plane. Thus, the roles of the plurality of islands212in the first metal layer210and the plurality of islands220in the second metal layer218would be reversed such that the plurality of islands212in the first metal layer210are configured to route the GND signals through the other layers and the plurality of islands220in the second metal layer218are configured to route the power and I/O signals through the metal layers. For clarity, the Detailed Description will continue to describe the embodiment in which the first metal layer210is the GND plane and the second metal layer218is the power plane.

FIG. 4schematically illustrates a side view of an electronic package assembly400that includes a power/ground arrangement200, in which the power ground arrangement200includes separate ground and power planes (e.g., first metal layer210and second metal layer218) to respectively provide ground and power signals for one or more dies (e.g., a first semiconductor die202within the power/ground arrangement200and a second semiconductor die402). In an embodiment, the electronic package assembly400includes power/ground arrangement200, second semiconductor die402, substrate404, adhesive406, one or more bonding wires412, and molding compound414, coupled as illustrated.

The power/ground arrangement200and the second semiconductor die402are mounted/disposed on the substrate404, as illustrated. The substrate404can include, for example, a printed circuit board or a leadframe in some embodiments, but can further include any suitable structure for mounting the power/ground arrangement200and the semiconductor die402in the electronic package assembly400in other embodiments. The substrate404can be used to route electrical signals such as the power and/or ground signals from a source external to the electronic package assembly400to the power/ground arrangement200using any suitable electrical pathway (e.g., wires, not illustrated).

The semiconductor die402generally comprises a semiconductor material, such as, for example, silicon. The power/ground arrangement200and the semiconductor die402are coupled to the substrate404using an adhesive406such as, for example, an epoxy. The power/ground arrangement200and the semiconductor die402can be coupled to the substrate404using any other suitable technique in other embodiments.

FIG. 5schematically illustrates a top view of the electronic package assembly400ofFIG. 4. The molding compound414ofFIG. 4is not depicted inFIG. 5for the sake of clarity. Power signals can be routed from the power/ground arrangement200to the second semiconductor die402using one or more bonding wires412. As can be seen, the second metal layer218at bond pad306is electrically coupled to, for example, a bond pad502on a surface of the second semiconductor die402using a bonding wire412. In this manner, the power/ground arrangement200is configured to route power signals to the second semiconductor die402. Additional bonding wires412and bonding pads306,502may be used to route power signals between the power/ground arrangement200and the second semiconductor die402if desired.

Ground signals can be routed from the power/ground arrangement200to the second semiconductor die402using one or more bonding wires412. As can be seen, the first metal layer210at bond pad308is electrically coupled to a bond pad504on the surface of the second semiconductor die402using a bonding wire412. In this manner, the power/ground arrangement200is configured to route ground signals to the second semiconductor die402. More bonding wires412and bonding pads308,504may be used to route ground signals between the power/ground arrangement200and the second semiconductor die402if desired.

Signals can be routed to and from the semiconductor die202in the power/ground arrangement200to the second semiconductor die402using one or more bonding wires412. As can be seen, the semiconductor die202at bond pad310is electrically coupled to a bond pad506on the surface of the second semiconductor die402using a bonding wire412. In this manner, the power/ground arrangement200is configured to route signals between the semiconductor die202(e.g., a CPU die) and the second semiconductor die402(e.g., a memory die). More bonding wires412and bonding pads310,506may be used to route signals between the semiconductor die202and the second semiconductor die402if desired.

The second semiconductor die402is positioned adjacent and side-by-side to the power/ground arrangement200. In an embodiment, the semiconductor die202within the power/ground arrangement200comprises a processor (e.g., system-on-a-chip) and the second semiconductor die402comprises memory. In the embodiment ofFIGS. 4-5where the second semiconductor die402comprises memory, the memory only needs connections to the power/ground arrangement200along one side in order to interact with the semiconductor die202, and receive power and ground signals from the power/ground arrangement200.

Although only two semiconductor dies (e.g., semiconductor die202and semiconductor die402) are depicted/described in the electronic package assembly400ofFIGS. 4 and 5, additional semiconductor dies can be disposed within the electronic package assembly400either in a stacked configuration or side-by-side configuration in other embodiments. The additional semiconductor dies can likewise be coupled to the power/ground arrangement200for routing of power and/or ground signals using techniques as described herein. For example, the various layers of the power/ground arrangement200can be exposed on multiple edges of the power/ground arrangement200(as illustrated inFIG. 3) to facilitate electrical coupling of additional dies to the power/ground arrangement200using bond pads and bonding wires as described herein. Furthermore, bonding wires may be coupled to islands220to route signals to additional semiconductor dies. Also, one or more additional dies may be stacked on top of power/ground arrangement200, using known techniques, such that the one or more additional semiconductor dies are communicatively coupled with islands220to receive signals from the power/ground arrangement200.

In some embodiments, a molding compound414is formed to substantially encapsulate the power/ground arrangement200, the second semiconductor die402, and the one or more bonding wires412. The molding compound414generally comprises an electrically insulative material, such as a thermosetting resin, that is disposed to protect the power/ground arrangement200and the second semiconductor die402from moisture, oxidation, or chipping associated with handling.

Referring toFIG. 6A, a semiconductor package600is illustrated that includes a semiconductor die604. In accordance with various embodiments, the semiconductor die604is configured as a central processing unit (CPU). The semiconductor package600further includes a switching array608disposed on top of the semiconductor die604. The size of the switching array608generally approximates the size of the semiconductor die604. In accordance with various embodiments, the switching array608may be identically sized to the semiconductor die604, or may be different in size with respect to the semiconductor die604. Furthermore, the switching array608may be formed in a separate die that is then coupled to the semiconductor die604.

FIG. 6Billustrates another embodiment of semiconductor package600wherein multiple switching arrays608are disposed on top of the semiconductor die604. It should be understood that other components (not shown), such as, a heat sink, and other semiconductor dies, may be disposed on top of the multiple switching arrays608. Depending on the design, one or more of the switching arrays608may function solely as structural support for components residing on top. For example, the switching array608in the middle may provide switching functions and structural support, while the left and the right switching arrays608may function solely as structural support for a heat sink (not shown) disposed on top of the switching arrays608.

In accordance with various embodiments, the switching array608is formed as a power/ground arrangement200in a manner similar to that described with respect toFIGS. 2A-2E. The silicon layer or semiconductor die202within such a power/ground arrangement200is configured to include a plurality of switches and capacitors. The power/ground arrangement200also includes a ground plane and a power plane, e.g., first metal layer210and second metal layer218, in which the ground plane is separate from the power plane.

Referring toFIG. 7A, a partial schematic view of the switching array608and the semiconductor die604is illustrated. For the sake of clarity, only one switch702and one capacitor704are illustrated. It should be understood that the switching array608can includes multiple switches and capacitors. As shown inFIG. 7A, the switch702and the capacitor704are formed within the silicon layer202and are coupled to the semiconductor die604through an electrical path comprising (through-silicon) vias706and a flip chip joint710. The flip chip joint710can be, for example, a solder bump, a gold bump, copper bump, and so on. The vias706are defined within the Si layer202. The ground plane210and the power plane218are in separate layers and formed in a manner at least similar to the methods previously described with respect toFIGS. 2A-2E.

FIG. 7Billustrates another embodiment of the switching array608. Once again, for the sake of clarity, only one switch702and one capacitor704are illustrated, but it should be understood that the switching array608can include multiple switches and capacitors. The power and ground planes218and210are situated between the switch702and the capacitor704configuration and the semiconductor die604. In an embodiment, the switching array608is connected to the semiconductor die604via a flip chip joint710. The flip chip joint710can be formed through a flip chip operation, and the flip chip joint710generally provides connections at various bonding pads (not illustrated) on the switching array608and bonding pads on the semiconductor die604. In an implementation, one or more bonding wires712provide an electrical path for signals to and/or from the semiconductor die604.

FIG. 8illustrates an embodiment of a package arrangement800wherein solder balls or bumps802are added to the semiconductor package600. As can be seen, due to the slight increase in thickness where the switching array608is on top of the semiconductor die604, the solder balls802aare slightly smaller than the solder balls802b. Thus, the semiconductor package600with the solder balls802is generally the same height with respect to line804. In other embodiments, the switching array608and the semiconductor die604may be very thin relative to the solder balls or bumps802b, and thus, solder balls or bumps802aand802bhave substantially the same size and height.

FIG. 9illustrates an embodiment a package arrangement900wherein the package arrangement800ofFIG. 8is flipped onto a package902, e.g., a ball grid array (BGA) via a flip chip operation. The solder balls802provide electrical connections between the semiconductor package600, including the semiconductor die604and switching array608, and the BGA902. In other embodiments, other electrical connections that are known may be used in place of the solder balls802. For example, the semiconductor package600and the BGA902may not be stacked on top of each other, but rather may be in a side by side arrangement and thus, bonding wires may be used.

Signals between the BGA902and the semiconductor die604(including signals from the power and ground planes) may be provided through the solder balls802and through the switches702and capacitors704of the switching array608, as well as the vias defined within the power/ground arrangement200and/or the intermediate layer708. With the switching array608located on top of the semiconductor die604, delivery of power to the semiconductor die604is more efficient. This is generally due to the fact that the distance from the switching array608to the interior of the semiconductor die604is shorter and more direct, thus reducing power loss or waste along the traces or electrical connections. In general, the switching array608is generally maintained as thin as possible. In accordance with various embodiments, the switching array608has a thickness of approximately 20 microns. Additionally, while the switching array608has been described as being formed in a manner similar to that with respect to power/ground arrangement200and then coupled to the semiconductor die604, the switching array608may be formed directly on the semiconductor die604.

FIG. 10is a process flow diagram of a method1000to fabricate a semiconductor package (e.g., semiconductor package600ofFIG. 6A) described herein. At1002, the method1000includes providing a semiconductor die configured as a CPU. At1004, the method further includes coupling a switching array to a surface of the semiconductor die. In an embodiment, the switching array is coupled to the semiconductor die via a flip chip operation. In another embodiment, the switching array is coupled to the semiconductor die by forming the switching array on the surface of the semiconductor die. In another embodiment, the switching array is coupled to the semiconductor die via an intermediate layer.

The description may use perspective-based descriptions such as over/under. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

For the purposes of the present disclosure, the phrase “A/B” means A or B. For the purposes of the present disclosure, the phrase “A and/or B” means “(A), (B), or (A and B).” For the purposes of the present disclosure, the phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).” For the purposes of the present disclosure, the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.

The description uses the phrases “in an embodiment,” “in embodiments,” or similar language, which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present disclosure. For example, although semiconductor die604is described as being configured as a CPU, the semiconductor die604can be generally configured to implement any logic or circuitry requiring a ground and power for operation. This disclosure is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.