Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing target using, as masks, the first mask and the first supporter; forming a second supporter so as to be contacted with a side surface of the processing target exposed in first processing step and the other side surface of the first mask; removing the first supporter; and patterning the processing target using, as masks, the first mask and the second supporter.

TECHNICAL FIELD

This application is based upon and claims the benefit of the priority of Japanese patent application No. 2011-145126, filed on Jun. 30, 2011, the disclosure of which is incorporated herein in its entirety by reference thereto.

The present disclosure relates to a method of manufacturing a semiconductor device having a minute pattern.

BACKGROUND

In recent years, as a semiconductor device has been downsized, a double patterning technology has been developed. The double patterning technology is a technology for forming a minute circuit pattern, in which the circuit pattern to be formed is separated into two parts followed by exposure. As the double patterning technology, a method of forming a minute pattern using a sidewall as an etching mask has been known (see Japanese Patent Kokai Publication No. JP2001-156283A (Patent Document 1), for example).

FIGS. 21A to 22Cillustrate schematic flowcharts (including figures corresponding toFIGS. 1(a)-(f) of Patent Document 1) to explain a method of forming a minute pattern according to a background art. InFIGS. 21A to 22C, (Z) figures on a left side are schematic top views of a semiconductor device. At the upper left ofFIG. 21A, directions in the (Z) figures are shown. In the (Z) figures, a lateral (horizontal) direction corresponds to X axis, a vertical direction corresponds to Y axis, and a perpendicular direction to the surface corresponds to Z axis. The (X) figures at the central are schematic cross-sections along an X-X line of the (Z) figure on the left side, and the (Y) figures on the right side are schematic cross-sections along a Y-Y line of the (Z) figure. InFIG. 21A, a semiconductor substrate91, a processing target layer92and a first dielectric interlayer93are stacked. Here, the background art will be explained giving an example of a method of forming the minute pattern of the processing target layer92.

First, the first dielectric interlayer93is etched to make openings94on both sides, and therefore a dielectric interlayer line93ais formed (FIG. 21B). Next, an etching mask layer95is formed on the processing target layer92and the dielectric interlayer line93a(FIG. 21C). Next, sidewalls of the dielectric interlayer line93aare formed by etching-back of the etching mask layer95(FIG. 21D). These sidewalls serve as etching masks95aalong side surfaces of the dielectric interlayer line93a. Next, the dielectric interlayer line93abetween two etching masks95ais removed by etching (FIG. 22A). Next, minute patterns92aare formed by etching the processing target layer92using the etching masks95aas masks (FIG. 22B). Lastly, the etching masks95aare removed, and a second dielectric interlayer96is formed around the minute patterns (FIG. 22C).

The following analysis is given in view of the present disclosure.

In the method illustrated inFIGS. 21-22, as described in Patent Document 1, the etching mask95aexists on the minute pattern92ain the state illustrated inFIG. 22B. Because the thickness of the minute pattern92ais equal to the thickness of the processing target layer92, and the etching mask95ais formed as the sidewall of the first dielectric interlayer93, a total thickness t of the minute pattern92aand etching mask95adepends on a thickness of each layer (200 nm of the total thickness t, for example). Accordingly, the narrower the width w of the minute pattern92abecomes (10 nm-30 nm of the width w, for example), the higher an aspect ratio (7 to 20 in the above example of the thickness t and width w, for example) of the combination pattern of the minute pattern92aand etching mask95abecomes.

Therefore, there is a probability that a combination pattern of the minute pattern92aand the etching mask95abecomes unstable so as to fall down. This may happen also in a state where only the etching mask is present as illustrated inFIG. 22A.

SUMMARY

According to a first aspect of the disclosure, there is provided a method of manufacturing a semiconductor device comprising: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing target with masks of the first mask and the first supporter; forming a second supporter so as to be contacted with a side surface of the processing target that is exposed in the first processing step and the other side surface of the first mask; removing the first supporter; and patterning the processing target with the first mask and the second supporter.

PREFERRED EXAMPLES

The disclosure will be now described herein with reference to illustrative exemplary embodiments. Those skilled in the art will recognize that many alternative exemplary embodiments can be accomplished using the teachings of the present disclosure and that the disclosure is not limited to the exemplary embodiments illustrated for explanatory purposes. Symbols are appended merely to make the understanding easy but not intended to limit the present disclosure to illustrated modes.

First Exemplary Embodiment

A method of manufacturing a semiconductor device according to a first exemplary embodiment of the present disclosure will be explained. First, the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the first exemplary embodiment of the present disclosure will be explained.FIG. 1illustrates a schematic cross-sectional view of a semiconductor device to be manufactured by the method of manufacturing a semiconductor device according to the first exemplary embodiment of the present disclosure. The semiconductor device1comprises a semiconductor substrate11, a first material layer fins12bformed on the semiconductor substrate11as a minute pattern, and a first filling layer16and second filling layer19formed around the first material layer fins12bon the semiconductor substrate11. In the mode illustrated inFIG. 1, two first material layer fins12bare formed. Width T3of the first material layer fin12bis lower in relation with height H1, and an aspect ratio becomes high (3 or more of H1/T3, for example). The first material layer fins12b, which are formed as a set of two fins in the Y direction, may have 10 nm in width T3and 40 nm in height H1at an interval of 50 nm in the Y direction.

Next, the method of manufacturing the semiconductor device1will be explained.FIGS. 2-4are schematic flowcharts to explain the method of manufacturing the semiconductor device according to the first exemplary embodiment of the present disclosure. InFIG. 21and others, (Z) figures on the left side are schematic top plan views of the semiconductor device. At the upper left ofFIG. 2A, directions in the (Z) figures are shown. In the (Z) figures, a lateral direction corresponds to the X axis, a lengthwise direction corresponds to the Y axis, and a perpendicular direction to the surface corresponds to the Z axis. The (X) figures at the central are schematic cross-sections along the X-X line of the (Z) figure on the left side, and the (Y) figures on the right side are schematic cross-sections along the Y-Y line of the (Z) figure.

First, the semiconductor substrate11is prepared. Next, a first material layer12having a thickness T1, which serves as a base of a minute pattern (a fin-like body having minute width, for example), is formed on the semiconductor substrate11. As a material of the first material layer12, a metal, semiconductor, insulator and the like may be used. When the semiconductor device11in which the first material layer fin12billustrated inFIG. 1serves as an electrode is manufactured, for example, the first material layer12may be formed of titanium nitride having 50 nm in thickness T1.

Next, a first mask layer13having a thickness T2is formed on the first material layer12(FIG. 2A). The first mask layer13serves as a base to form a second mask layer. As the first mask layer13, silicon oxide having 50 nm in thickness T2may be used. The thickness T2corresponds to a height of a second mask layer sidewall15adescribed below. Therefore, it is preferred that the thickness T2is set to an enough height that the second mask layer sidewall15aserves as a mask and, for example, that the second mask layer sidewall15acan function as a mask even if the thickness is reduced by etching.

Next, a resist mask to process the first mask layer13is formed on the first mask layer13(not illustrated). Next, using this resist mask, the first mask layer13is partially removed by etching to form first openings14, and therefore a first mask layer line13ahaving a line-like (band-like) shape is formed. Next, the resist mask on the first mask layer13is removed (FIG. 2B). In the mode illustrated inFIGS. 2A-D, the first mask layer line13aextends in the X direction (see the direction diagram at the upper left ofFIG. 2A) and has a width W1in the Y direction. The width of the resist mask in the Y direction corresponds to the width W1of the first mask layer line13a. The width W1also corresponds to a gap between two first material layer fins12billustrated inFIG. 1. The first mask layer13may have 50 nm in width W1, for example.

Next, the second mask layer15that serves as a base of a mask to process the first material layer12is formed. The second mask layer15is formed along an exposed surface of the first material layer12and the side and top surfaces of the first mask layer line13aso that openings14are not filled and so that the first mask layer line13ais covered (FIG. 2C). As a material of the second mask layer15, a material capable of serving as a mask to process the first material layer12may be used. In this exemplary embodiment, the second mask layer15may be formed of tungsten, for example. The second mask layer15may have 10 nm in thickness T3, for example. The thickness T3of the second mask layer15corresponds to the width of the first material layer fin12billustrated inFIG. 1. Accordingly, it is preferred that the thickness T3of the second mask layer15is set corresponding to the width of the first material layer12to be shaped.

Next, by etching-back of the second mask layer15, a top surface of the first material layer12and a top surface of the first mask layer line13aare exposed, and second mask layer sidewalls15aextending along the side surfaces of the first mask layer line13ain the X direction and having the width T3and height T2is formed (FIG. 2D; First mask forming step). A pattern of the second mask layer sidewall15acorresponds to a pattern to form the first material layer fin12billustrated inFIG. 1.

Next, using the second mask layer sidewalls15aand first mask layer line13aas masks, the first material layer12exposed in the first openings14is etched so as to expose the semiconductor substrate11(first etching), and therefore the first material layer line12ais formed (FIG. 3A; First processing step). The first material layer line12ahas a width (W+T3×2) and a height T2and extends in the X direction.

Next, a filling layer is formed so as to fill the openings14. Next, using a CMP (Chemical Mechanical Polishing) method or the like, the filling layer on the first mask layer line13aand second mask layer sidewalls15ais polished and removed so as to expose the top surfaces of the first mask layer line13aand second mask layer sidewalls15a, and therefore a first filling layer16that fills the openings14is formed (FIG. 3B; Second supporter forming step). The first filling layer16may be formed by an etching-back method. As a material of the first filling layer16, a material capable of serving as a mask to etch the first mask layer line13ain a subsequent etching step is preferably used. In the above example, silicon nitride may be used as the material of the first filling layer16, for example.

Next, a third opening18is formed by partially etching the first material layer line12aexposed from the second opening17so as to expose the semiconductor substrate11(second etching) using masks of the second mask layer sidewalls15aand first filling layer16. Therefore, the first material layer line12ais processed into the first material layer fins12b(FIG. 3D; Second processing step). That is, the first material layer12is processed to a fin shape having the width T3in the Y direction and height T1and extending in the X direction by transferring the pattern of the second mask layer sidewall15aon the plane by the first etching (FIG. 3A) and second etching.

Next, a second filling layer19is formed, which fills at least the second opening17and third opening18(FIG. 4A; Third supporter forming step). As a material of the second filling layer19, the same material (silicon nitride, for example) as that of the first filling layer16is preferably used, so that the first filling layer16and second filling layer19may be polished at once in a next CMP step.

Next, the second filling layer19, second mask layer sidewalls15aand first filling layer16are polished and removed by the CMP method to make the semiconductor device1(FIG. 4B; First mask removing step). This polishing and removing are performed until the second mask layer sidewalls15aare removed and the first material layer fins12bare exposed. In the mode illustrated inFIG. 4B, the upper part of the first material layer fins12bare polished so that the top surfaces of the first material layer fins12b, second filling layer19and first filling layer16are flush with one another. When the first material layer12has 50 nm in height T1, for example, the first material layer fin12bmay have 40 nm in height H1by being polished by 10 nm in the CMP step. The second filling layer19, second mask layer sidewalls15aand first filling layer16may be removed not by the CMP method but by the etching method.

If the first material layer fin12bto be formed has narrow width, the second mask layer sidewall15athat serves as the etching mask has also a narrow width T3. The height of the second mask layer sidewall15aneeds to keep the predetermined height T2in consideration of a thickness reduction by the etching. Accordingly, the aspect ratio of the height T2to the width T3in the second mask layer sidewall15acan not avoid becoming higher. If only the second mask layer sidewall15ais formed alone, there is a probability that the second mask layer sidewall15afalls down owing to the high aspect ratio. According to the method of manufacturing the semiconductor device according to the first exemplary embodiment of the present disclosure, however, there is no possibility that the second mask layer sidewall15afalls down even if the aspect ratio is high because any one of the side surfaces is supported. In the steps illustrated inFIGS. 2D and 3A, for example, one side surface of the second mask layer sidewall15ais supported with the first mask layer line13a. Accordingly, the possibility of falling down of the second mask layer sidewall15ais decreased. In the steps illustrated inFIGS. 3C and 3D, the other side surface of the second mask layer sidewall15ais supported with the first filling layer16. Accordingly, the possibility of falling down of the second mask layer sidewall15ais decreased. In the step illustrated inFIG. 3D, in particular, the first material layer fin12band the second mask layer sidewall15aare stacked, and therefore a total aspect ratio becomes even higher. According to the method of manufacturing the semiconductor device according to the first exemplary embodiment of the present disclosure, however, both of the first material layer fin12band the second mask layer sidewall15aare supported with the first filling layer16. Accordingly, even after the first material layer fin12bis formed, the possibility of falling down of the first material layer fin12band the second mask layer sidewall15acan be decreased.

Second Exemplary Embodiment

Next, a method of manufacturing a semiconductor device according to a second exemplary embodiment of the present disclosure will be explained. First, the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the second exemplary embodiment of the present disclosure will be explained.FIG. 5illustrates a schematic cross-sectional view of the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the second exemplary embodiment. The semiconductor device2comprises a semiconductor substrate21having semiconductor substrate fins21b. In the mode illustrated inFIG. 5, two semiconductor substrate fins21b12bare formed. A width T6of the semiconductor substrate fin21bis lower in relation with height H2, and an aspect ratio becomes high (3 or more in H2/T6, for example). The semiconductor substrate fins21b, which are formed as a set of two fins in the Y direction, may have 10 nm in width T6and 50 nm in height H2at an interval of 50 nm in the Y direction, for example.

Next, the method of manufacturing the semiconductor device2will be explained.FIGS. 6-8illustrate schematic flowcharts to explain the method of manufacturing the semiconductor device according to the second exemplary embodiment of the present disclosure.

First, the semiconductor substrate21having a thickness T4is prepared. The thickness T4is set thicker than the height H2of the semiconductor substrate fin21billustrated inFIG. 5. Next, in the same way as inFIG. 2Aof the first exemplary embodiment, a first mask layer23having a thickness T5is formed on the semiconductor substrate21(FIG. 6A). This mode is different in existence of the first material layer from the mode illustrated inFIG. 2A. As the first mask layer23, silicon oxide having 50 nm in thickness T5may be used, for example.

Next, in the same way as inFIG. 2Bof the first exemplary embodiment, the first mask layer line23ahaving a width W2is formed (FIG. 6B). First openings24are formed on both sides of the first mask layer line23a. The first mask layer line23amay have 50 nm in width W2, for example.

Next, in the same way as inFIG. 2Cof the first exemplary embodiment, a second mask layer25having a thickness T6is formed (FIG. 6C). The second mask layer25may be tungsten having 10 nm in thickness T6, for example.

Next, in the same way as inFIG. 2Dof the first exemplary embodiment, second mask layer sidewalls25ahaving the width T6and thickness (i.e. height) T5is formed (FIG. 6D).

Next, the semiconductor substrate21is partially etched using, as masks, the first mask layer line23aand second mask layer sidewalls25a(first etching) to form second openings21cin the semiconductor substrate21, and therefore a semiconductor substrate line21ahaving height H2and width (W2+T6×2) is formed (FIG. 7A). The height H2may be 50 nm, for example.

Next, in the same way as inFIG. 3Bof the first exemplary embodiment, a first filling layer26is formed so as to fill the second openings21c(FIG. 7B). Silicon nitride may be used as the first filling layer26, for example.

Next, in the same way as inFIG. 3Cof the first exemplary embodiment, a third opening27is formed by electively etching and removing the first mask layer line23a(FIG. 7C).

Next, in the same way as inFIG. 3Dof the first exemplary embodiment, the exposed semiconductor substrate line21ais partially etched using, as masks, the second mask layer sidewalls25aand filling layer26to form a fourth opening28(second etching), and therefore semiconductor substrate fins21bare formed (FIG. 7D). It is preferred that depth H3by which the semiconductor substrate21is etched is similar to, (same as, preferably), the height H2of the semiconductor substrate line21a. Therefore, the semiconductor substrate fins21bhave the width T6and height H2.

Next, the second mask layer sidewalls25aand first filling layer26are selectively removed to expose the semiconductor substrate fins21b, and therefore the semiconductor device2is manufactured (FIG. 8; First mask removing step).

According to the second exemplary embodiment, the semiconductor substrate fin21bis monolithically formed as a part of the semiconductor substrate21, which is different from the first exemplary embodiment, and thus the semiconductor substrate fin21bhas a structure that is hard to fall down even though the filling layer that supports the side face is removed. According to the second exemplary embodiment, in the same manner as the first exemplary embodiment, in the steps shown inFIGS. 6D,7A,7C and7D, one side surface of the second mask layer sidewall25ais supported with the first mask layer line23aand first filling layer26, and thus the possibility that the second mask layer sidewall25afalls down can be decreased.

Third Exemplary Embodiment

Next, a method of manufacturing a semiconductor device according to a third exemplary embodiment of the present disclosure will be explained. First, the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the third exemplary embodiment of the present disclosure will be explained.FIG. 9illustrates schematic cross-sectional views of the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the third exemplary embodiment. Figure (X) is a schematic cross-section along the X direction and figure (Y) is a schematic cross-section along the Y direction. A semiconductor device3comprises a PRAM (Phase-change Random Access Memory). In detail, the semiconductor device3comprises: a semiconductor substrate(s)51having an element forming region65that is separated by an element isolation region(s)52, a source/drain region(s)51aformed in the semiconductor substrate51, a gate electrode(s)64formed on the semiconductor substrate51, a bit line(s)59that is electrically connected to the source/drain region(s)51athrough a bit line contact plug(s)58that penetrates a gate interlayer(s)60, an electrode pad(s)32that is electrically connected to the source/drain region(s)51athrough an electrode contact plug(s)57that penetrates the gate interlayer60and bit line interlayer61and that is formed in an electrode pad interlayer31, a first lower electrode layer pillar(s)35cthat is electrically connected to a top surface of the electrode pad32, a first insulating layer pillar33cand second insulating layer pillar36bthat extend, with the same width as the first lower electrode layer pillar35c, between the first lower electrode layer pillars35cwhich are adjacent to each other in the X direction, a first filling layer41and second filling layer44that fill gaps formed by the first lower electrode layer pillar(s)35c, the first insulating layer pillar(s)33cand the second insulating layer pillar(s)36b, a first phase change material layer45that is electrically connected to the top surface of the first lower electrode layer pillar35c, an upper electrode layer46formed on the first phase change material layer45, an upper interlayer62that covers the first phase change material layer45and upper electrode layer46, and an upper wiring (interconnect)63formed on the upper interlayer62. The gate electrode64has a gate insulating layer53, a gate conducting layer54, a gate cap layer55, and a sidewall56.

The first lower electrode layer pillar35c, first phase change material layer45and upper electrode layer46make up the PRAM. As the first phase change material layer45, a material in which resistance is variable by applying heat or the like may be used, for example, and a compound including chalcogenide may be used, for example. The first lower electrode layer pillar35chas a shape like a pillar (or column) having a quadrilateral contact surface with the first phase change material layer45. In the PRAM of the semiconductor device3, because the contact area between the first lower electrode layer pillar35cand the first phase change material layer45is very small (10 nm×10 nm, for example), a rewriting current can be reduced. Because the first lower electrode layer pillar35citself has a small volume, the rewriting current can be also reduced owing to decrease of heat loss.

Next, a method of manufacturing the semiconductor device3will be explained.FIGS. 10-14illustrate schematic flowcharts to explain the method of manufacturing the semiconductor device according to the third exemplary embodiment of the present disclosure.

First, a manufacturing method untilFIG. 10Awill be explained briefly (drawings are omitted). The element isolation regions52are formed on the semiconductor substrate51. The element forming regions65are demarcated by the element isolation regions52. The gate electrodes64having the gate insulating layer53, gate conducting layer54, gate cap layer55and sidewalls56are formed. An impurity is introduced into the element forming regions65by using the gate insulating layers53, gate conducting layers54and gate cap layers55as masks to form the source/drain regions51a. The gate interlayer60is formed on the semiconductor substrate51. The bit line contact plugs58that penetrate the gate interlayer60and that are electrically connected with the source/drain regions51aare formed. The bit lines59that are electrically connected with the bit line contact plugs58are formed. The bit line interlayer61is formed on the bit lines59. The electrode contact plugs57that penetrate the bit line interlayer61and that are electrically connected with the source/drain regions51aare formed. The electrode pad interlayer31is formed on the electrode contact plugs57. The electrode pads32that penetrate the electrode pad interlayer31and that are electrically connected with the electrode contact plugs57are formed (Electrode pad forming step). The electrode pads32are arrayed in gridlike fashion at intervals of 2F each in the X direction and Y direction with the minimum processing size F of the lithography method.

Next, a first insulating layer33having a thickness T7is formed on the electrode pad interlayer31and electrode pads32(FIG. 10B). The first insulating layer33may be silicon oxide having 60 nm in thickness T7, for example.

Next, in the same way as inFIG. 2Bof the first exemplary embodiment, first insulating layer lines33ahaving a width W3are formed by forming first openings34extending in the X direction (FIG. 10C; Fourth supporter forming step). The first insulating layer lines33aextend in the Y direction and are arranged in a row at intervals of predetermined gaps in the X direction. One first insulating layer line33ais formed between the electrode pads32that are adjacent to each other in the X direction, that is, along a line of the electrode pads32arrayed in the Y direction. Both sides of the first insulating layer line33aapproximately cover a half of each electrode pad32. If the electrode pads32are arrayed in the gridlike fashion by 2F pitches, for example, the first insulating layer lines33aare formed by 4F pitches in the X direction so as to have a distance D1of 2F.

Next, in the same way as inFIG. 2Cof the first exemplary embodiment, a lower electrode layer35having a thickness T8is formed (FIG. 10D). The lower electrode layer35may be titanium nitride having 10 nm in thickness T8, for example.

Next, in the same way as inFIG. 2Dof the first exemplary embodiment, lower electrode layer fins35athat extend in the Y direction as sidewalls of the first insulating layer line33aare formed by etching-back of the lower electrode layer35so as to expose the top surfaces of the electrode pads32(FIG. 11A; Processing target processing step).

Next, a second insulating layer36is formed by filling an insulating layer in the first openings34and polishing the insulating layer with the CMP method or the like so as to expose the top surfaces of the lower electrode layer fins35a(FIG. 11B). The upper parts of the lower electrode layer fins35aand first insulating layer line33amay be polished so that the top surfaces of the lower electrode layer fins35a, first insulating layer line33aand second insulating layer36become flush with one another. This can make the lower electrode layer fins35aand others having 50 nm in height H4etc., for example.

Next, in the same way as inFIG. 2Aof the first exemplary embodiment, a first mask layer37having a thickness T9is formed on the first insulating layer33and others (FIG. 11C). The first mask layer37may be silicon oxide having 50 nm in thickness T9, for example.

Next, in the same way as inFIG. 2Bof the first exemplary embodiment, the second openings38are formed by etching the first mask layer37so as to expose the top surfaces of the lower electrode layer fins35a, first insulating layer lines33aand second insulating layer36, and therefore first mask layer lines37aare formed (FIG. 11D). The first mask layer lines37aextend in the X direction and are arrayed in a row at intervals of predetermined gaps in the Y direction. One first mask layer line37ais formed between the electrode pads32that are adjacent to each other in the Y direction, that is, along a line of the electrode pads32arrayed in the X direction. Both sides of the first mask layer line37aapproximately cover a half of each electrode pad32. If the electrode pads32are arrayed in the gridlike fashion by 2F pitches, for example, the first mask layer lines37aare formed by 4F pitches in the X direction so as to have a distance D2of 2F.

Next, in the same way as inFIG. 2Cof the first exemplary embodiment, a second mask layer39having a thickness T10is formed on the first insulating layer33and others (FIG. 12A). The second mask layer39may be tungsten having 10 nm in thickness T10, for example.

Next, in the same way as inFIG. 2Dof the first exemplary embodiment, second mask layer sidewalls39aare formed along the side surfaces of the first mask layer line37a(FIG. 12B).

Next, in the same way as inFIG. 3Aof the first exemplary embodiment, third openings40are formed by etching the lower electrode layer fins35a, first insulating layer lines33aand second insulating layer36using masks of the second mask layer sidewalls39aand first mask layer lines37aso as to expose the electrode pads32and electrode pad interlayer31(First etching). Therefore, the third openings40separate the lower electrode layer fins35a, first insulating layer lines33aand second insulating layer36that extend in the Y direction, and therefore a plurality of lower electrode layer blocks35b, first insulating layer blocks33band second insulating layer blocks36aare formed (FIG. 12C).

Next, in the same way as inFIG. 3Bof the first exemplary embodiment, a first filling layer41is formed by forming a filling layer in the second openings38and third openings40and exposing the top surfaces of the first mask layer lines37aand second mask layer sidewalls39a(FIG. 12D).

Next, in the same way as inFIG. 3Cof the first exemplary embodiment, fourth openings42are formed by selectively removing the first mask layer lines37aso as to expose the lower electrode layer blocks35b, first insulating layer blocks33band second insulating layer blocks36a(FIG. 13A).

Next, in the same way as inFIG. 3Dof the first exemplary embodiment, fifth openings43are formed by etching and removing the lower electrode layer blocks35b, first insulating layer blocks33band second insulating layer blocks36a, which are exposed under the fourth openings42, using the masks of the second mask layer sidewalls39aand first filling layer41so as to expose the electrode pads32and electrode pad interlayer31(Second etching). This makes the lower electrode layer blocks35b, first insulating layer blocks33band second insulating layer blocks36ahaving widths same as that of the second mask layer sidewalls39a, and therefore the first lower electrode layer pillars35c, first insulating layer pillars33cand second insulating layer pillars36bare formed (FIG. 13B). The formed lower electrode layer pillars35care shaped into a quadrangular prism having the width T8in the X direction, the width T10in the Y direction and the height H4as shown inFIG. 13Ddescribed below.

Next, in the same way as inFIG. 4Aof the first exemplary embodiment, a second filing layer44is formed so as to fill the fifth openings43and fourth openings42(FIG. 13C).

Next, in the same way as inFIG. 4Bof the first exemplary embodiment, the second mask layer sidewalls39a, first filling layer41and second filling layer44are polished and removed by the CMP method so as to expose at least the top surface of the first lower electrode layer pillars35c(FIG. 13D; First mask removing step). The upper parts of the first lower electrode layer pillars35cmay be also polished and removed. This makes the top surfaces of the first lower electrode layer pillars35c, first filling layer41, second filling layer44, first insulating layer pillars33cand second insulating layer pillars36bflush with one another. The first lower electrode layer pillar35cis surrounded with the first insulating layer pillar33c, second insulating layer pillar36b, first filling layer41and second filling layer44. The first lower electrode layer pillar may have 40 nm in height H5, for example.

Next, the first phase change material layers are formed on the first lower electrode layer pillars35c(Phase change material forming step). Next, the upper electrode layers46are formed on the first phase change material layers45(FIG. 14; Conductor forming step). The first phase change material layers45and upper electrode layers46extend along lines of the electrode pads32arrayed in the X direction. The widths the first phase change material layer45and upper electrode layer46may be made similar to the width of the electrode pad32in the Y direction.

Next, the upper interlayer62that covers the first phase change material layers45and upper electrode layers46is formed. Peripheral contacts that are electrically connected with conducting layers, such as the source/drain region(s)51aof the semiconductor substrate51, gate electrode(s)64, bit line(s)59and others, from the upper interlayer62are formed in a peripheral circuit region (not illustrated). The upper wiring63is formed on the peripheral contacts. An interlayer, through hole, wiring, passivation layer and the like are formed, if necessary, and the semiconductor device3is manufactured.

According to the third exemplary embodiment, the first lower electrode layer pillar35chaving small areas of the top and bottom surfaces, as shown inFIG. 13D, can be formed. Even if the aspect ratio of the first lower electrode layer pillar35cis high, a possibility that each element of the first lower electrode layer pillar35cand others falls down in the forming steps can be reduced. InFIG. 11A, one side surface of the lower electrode layer fin35ais supported with the first insulating layer line33a. InFIG. 12B, one side surface of the second mask layer sidewalls39ais supported with the first mask layer line37a. InFIG. 13A, one side surface of the second mask layer sidewall39ais supported with the first filling layer41. InFIG. 13B, although the first lower electrode layer pillar35c, first insulating layer pillar33cand second insulating layer pillar36bhave fin shapes, one side surfaces of the second mask layer sidewall39aand the fins of the first lower electrode layer pillar35c, first insulating layer pillar33cand second insulating layer pillar36bare supported with the first filling layer41. The both sides of the first lower electrode layer pillar35care supported with the first insulating layer pillar33cand second insulating layer pillar36b. Therefore, according to this exemplary embodiment, even if each element is processed into a shape having a high aspect ratio, the possibility of falling down can be reduced, because any side surface of the element is supported with another element.

Fourth Exemplary Embodiment

Next, a method of manufacturing a semiconductor device according to a fourth exemplary embodiment of the present disclosure will be explained. First, the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the fourth exemplary embodiment of the present disclosure will be explained.FIG. 15illustrates the schematic cross-sectional view of the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the fourth exemplary embodiment. InFIGS. 15 and 16, same symbols are added to elements which are same as the third exemplary embodiment. In the third exemplary embodiment, the phase change material extends in a line on the lower electrode, whereas, in a semiconductor device4according to the fourth exemplary embodiment, a second phase change material plug72ahas a planar area similar to that of the first lower electrode layer pillar35c. That is, the second phase change material plug72ais made smaller than the phase change material layer in the third exemplary embodiment. Therefore, according to the semiconductor device4, the rewriting current of the PRAM can be further decreased than the semiconductor device according to the third exemplary embodiment.

Next, a method of manufacturing the semiconductor device4will be explained.FIG. 16illustrates a schematic flowchart to explain the method of manufacturing the semiconductor device according to the fourth exemplary embodiment of the present disclosure. The steps untilFIG. 13Dare same as the third exemplary embodiment.

After the first lower electrode layer pillars35care formed, upper parts of the first lower electrode layer pillars35care partially removed by etching to form recesses71, and the lower electrode layer is referred to as a second lower electrode layer pillar35d(FIG. 16A; Sixth processing step). The recess71may have 20 nm in depth D3, for example.

Next, a second phase change material layer72is formed so as to fill the recesses71(FIG. 16B).

Next, second phase change material plugs72aare formed by polishing the second phase change material layer72by the CMP method so as to expose the phase change material layer filled in the recesses71(FIG. 16C; Phase change material forming step).

Next, upper electrode layers46having a pattern are formed so as to be electrically connected with the top surfaces of the second phase change material plugs72a(FIG. 16D; Conductor forming step). The subsequent steps are same as the third exemplary embodiment.

According to the fourth exemplary embodiment, the phase change material layer can be further made smaller than the third exemplary embodiment. Therefore, the rewriting current of the PRAM can be further reduced.

Fifth Exemplary Embodiment

Next, a method of manufacturing a semiconductor device according to a fifth exemplary embodiment of the present disclosure will be explained. First, the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the fifth exemplary embodiment of the present disclosure will be explained.FIG. 17illustrates a schematic cross-sectional view of the semiconductor device to be manufactured by the method of manufacturing the semiconductor device according to the fifth exemplary embodiment. InFIGS. 17-20, same symbols are added to the elements same as the third exemplary embodiment. The lower electrode layer pillar in the third exemplary embodiment has a shape of a long and narrow quadrangular prism, whereas a lower electrode layer pillar35iin a semiconductor device5according to the fifth exemplary embodiment has a convex shape on a cross section in the Y direction. That is, the lower electrode layer pillar35ihas a lower electrode layer projection35hat the upper part that has a narrower width in the Y direction than that of the lower part, and the top surface of the lower electrode layer projection35his electrically connected with the first phase change material layer45. The semiconductor device5has a third mask layer sidewall82aand fourth mask layer sidewall86aon the lower electrode layer pillar35iexcept the lower electrode layer projection35h. The lower electrode layer projection35his sandwiched between the third mask layer sidewall82aand the fourth mask layer sidewall86a.

According to this exemplary embodiment, the lower electrode layer pillar35ihas the thinner upper part and the thicker lower part. Therefore, the rewriting current can be reduced by contacting the thinned lower electrode layer projection35hwith the first phase change material layer45, and mechanical strength can be enhanced by thickening the lower part of the lower electrode layer pillar35i.

Next, a method of manufacturing the semiconductor device5will be explained.FIGS. 18-20illustrate schematic flowcharts to explain the method of manufacturing the semiconductor device according to the fifth exemplary embodiment of the present disclosure. The steps untilFIG. 12Bare same as the third exemplary embodiment.

After the second mask layer sidewalls39aare formed, sixth openings81are formed by partially etching the lower electrode layer fins35a, first insulating layer lines33aand second insulating layer36by using as masks, the second mask layer sidewalls39aand first mask layer lines37aso as not to expose the electrode pads32and electrode pad interlayer31. Therefore, lower electrode layer fins35e, first insulating layer lines33dand second insulating layer lines36care formed (FIG. 18A). The lower electrode layer fins35aand others may be polished by 30 nm in width D4, and the lower electrode layer fin35eand others may have 20 nm in a remaining height H6, for example.

Next, a third mask layer82having a thickness T11is formed so as to cover the second mask layer sidewalls39aand first mask layer lines37aand the inner surfaces of the sixth openings81(FIG. 18B). As a material of the third mask layer82, a material of a mask for etching of the first mask layer line37amay be used. Silicon nitride may be used as the material of the third mask layer82, for example. The third mask layer preferably has such a thickness that the sixth opening81is not filled and may have 15 nm in thickness T11, for example.

Next, third mask layer sidewalls82aare formed on the inner walls of the sixth openings81by etching-back of the third mask layer82(FIG. 18C; Second mask forming step). The third mask layer sidewall82aextends along one side surface of the second mask layer sidewall39aand the side surfaces of the sixth opening81formed with the lower electrode layer fins35e, first insulating layer lines33dand second insulating layer lines36c.

Next, seventh openings83are formed by etching and removing the lower electrode layer fins35e, first insulating layer lines33dand second insulating layer lines36c, which are exposed on the bottom of the sixth opening81, using masks of the third mask layer sidewalls82a, second mask layer sidewalls39aand first mask layer lines37aso as to expose the electrode pad interlayer31and electrode pads32(only the electrode pad interlayer31inFIG. 18). The seventh openings83separate the lower electrode layer fins35e, first insulating layer lines33dand second insulating layer lines36c, which extend along in the Y direction, and therefore a plurality of lower electrode layer blocks35f, first insulating layer blocks33eand second insulating layer blocks36dare formed (FIG. 18D; Third processing step). The cross sections of the lower electrode layer block35f, first insulating layer block33eand second insulating layer block36din the (Y) figure have a convex shape.

Next, a third filling layer84is formed by filling a filling layer in the sixth openings81and seventh openings83and polishing and removing the filling layer by the CMP method or the like so as to expose the top surfaces of the third mask layer sidewalls82aand others (FIG. 19A; Fifth supporter forming step).

Next, the first mask layer lines37aare selectively removed using the masks of the second mask layer sidewalls39a, third mask layer sidewalls82aand third filling layer84so as to expose the lower electrode layer blocks35f, first insulating layer blocks33eand second insulating layer blocks36d(First supporter removing step). Next, in the same way as inFIG. 18A, eighth openings85are formed by partially etching the lower electrode layer blocks35f, first insulating layer blocks33eand second insulating layer blocks36dusing masks of the second mask layer sidewalls39a, third mask layer sidewalls82aand third filling layer84so as not to expose the electrode pads32and electrode pad interlayer31. Therefore, lower electrode layer blocks35g, first insulating layer blocks33fand second insulating layer blocks36eare formed (FIG. 19B; Fourth processing step). The lower electrode layer block35ghas lower electrode layer projections35h, which project in a vertical direction of the substrate, under the second mask layer sidewalls39a. It is preferred that the etching is performed so that the right and left lower electrode layer projections35hof the lower electrode layer block35ghave the same height. That is, it is preferred that etching depth D5is same as the depth D4shown in FIG.18A (30 nm, for example) and that height H7of the lower electrode layer block35gin the eighth opening85is same as the height H6shown inFIG. 18A(20 nm, for example).

Next, in the same way as inFIG. 18B, a fourth mask layer86having a thickness T12is formed so as to cover the second mask layer sidewalls39a, third mask layer sidewalls82aand third filling layer84and the inner surfaces of the eighth openings85(FIG. 19C). As a material of the fourth mask layer86, a material of the mask for the etching of the lower electrode layer block35gcan be used. Silicon nitride may be used as the material of the fourth mask layer86, for example. The fourth mask layer86preferably has such a thickness T12that the eighth opening85is not filled and may have 15 nm in thickness T12, for example.

Next, in the same way as inFIG. 18C, fourth mask layer sidewalls86aare formed on the inner walls of the eighth opening85by the etching-back of the fourth mask layer86(FIG. 19D; Third mask forming step). The fourth mask layer sidewall86aextends along the other side surface of the second mask layer sidewall39aand the side surfaces of the eighth opening85formed with the lower electrode layer blocks35g, first insulating layer blocks33fand second insulating layer blocks36e. The second mask layer sidewall39ais sandwiched between the third mask layer sidewall82aand the fourth mask layer sidewall86a.

Next, in the same way as inFIG. 18D, ninth openings87are formed by etching and removing the lower electrode layer blocks35g, first insulating layer blocks33fand second insulating layer blocks36e, which are exposed on the bottoms of the eighth openings85, using masks of the third mask layer sidewalls82a, second mask layer sidewalls39a, fourth mask layer sidewalls86aand third filling layer84so as to expose the electrode pad interlayer31and electrode pads32. Therefore, the ninth openings87separate the lower electrode layer blocks35g, first insulating layer blocks33fand second insulating layer blocks36ewhich extend in the Y direction, and therefore a plurality of lower electrode layer pillars35i, first insulating layer pillars33gand second insulating layer pillars36fare formed (FIG. 20A; Fifth processing step). The cross sections of the lower electrode layer pillars35i, first insulating layer pillars33gand second insulating layer pillars36fin the (Y) figure have a convex shape. There are the second mask layer sidewall39a, third mask layer sidewalls82aand fourth mask layer sidewalls86aon the lower electrode layer pillar35i.

Next, in the same way as inFIG. 19A, the eighth openings85and ninth openings87are filled with a fourth filling layer88(Sixth supporter forming step), and the third mask layer sidewalls82a, second mask layer sidewalls39a, fourth mask layer sidewalls86a, third filling layer84and fourth filling layer88are polished by the CMP method or the like so as to expose the top surfaces of the lower electrode layer projections35h. In order to surely expose the top surfaces of the lower electrode layer projections35h, the upper parts of the lower electrode layer projections35h, first insulating layer pillars33gand second insulating layer pillars36fmay be partially polished. Therefore, the top surfaces of the lower electrode layer pillar35i, first insulating layer pillar33g, second insulating layer pillar36f, third filling layer84and fourth filling layer88are made flush with one another (FIG. 20B; First mask removing step). The lower electrode layer pillar35imay have 40 nm in thickness H8, for example.

Next, in the same way as inFIG. 14, the first phase change material layers45are formed so as to be electrically connected with the top surface of the lower electrode layer projections35h(Phase change material forming step). Next, the upper electrode layers46are formed on the first phase change material layers45(FIG. 20C; Conductor forming step). The subsequent steps are performed same as the third exemplary embodiment, and the semiconductor device5is manufactured.

The method of manufacturing the semiconductor device of the present disclosure is explained based on the above exemplary embodiments, but is not limited to the above exemplary embodiments, and may include any modification, change and improvement to the exemplary embodiments within the scope of the present disclosure and based on the basic technical idea of the present disclosure. Within the scope of the claims of the present disclosure, various combinations, displacements and selections of disclosed elements are available.

A further problem, object and exemplary embodiment of the present disclosure become clear from the entire disclosure of the present invention including claims and drawings.