Three-state programming of memory cells

The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to three-state programming of memory cells.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, and movie players, among other electronic devices.

Resistance variable memory devices can include resistance variable memory cells that can store data based on the resistance state of a storage element (e.g., a memory element having a variable resistance). As such, resistance variable memory cells can be programmed to store data corresponding to a target data state by varying the resistance level of the memory element. Resistance variable memory cells can be programmed to a target data state (e.g., corresponding to a particular resistance state) by applying sources of an electrical field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses) to the cells (e.g., to the memory element of the cells) for a particular duration. A state of a resistance variable memory cell can be determined by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.

Various memory arrays can be organized in a cross-point architecture with memory cells (e.g., resistance variable cells) being located at intersections of a first and second signal lines used to access the cells (e.g., at intersections of word lines and bit lines). Some resistance variable memory cells can comprise a select element (e.g., a diode, transistor, or other switching device) in series with a storage element (e.g., a phase change material, metal oxide material, and/or some other material programmable to different resistance levels). Some resistance variable memory cells, which may be referred to as self-selecting memory cells, comprise a single material which can serve as both a select element and a storage element for the memory cell.

DETAILED DESCRIPTION

The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

Embodiments of the present disclosure can provide benefits, such as increased density, reduced cost, reduced power consumption, and/or faster and/or more complex operations, as compared to previous memory devices. For example, previous approaches for programming resistance variable memory cells, such as self-selecting memory cells, may be able to generate two different states for the cells, such that the cells can be programmed to one of two possible data states (e.g., state 0 or state 1). However, programming approaches for resistance variable memory cells in accordance with the present disclosure can generate an additional (e.g., third) state for the cells, such that the cells can be programmed to one of three possible data states.

Such three-state programming can be useful in supporting complex memory operations, such as, for instance, machine learning applications, in which data is encoded and matching functions or partial matching functions (e.g., Hamming distances) are computed. For instance, such three-state programming can support the computation of the matching function or partial matching function of an input vector pattern with many stored vectors in an efficient manner.

Further, such three-state programming can be useful for reducing the cost and/or increasing the density of standard memory applications. For example, such three-state programming can reduce (e.g., by 63%) the number of bits needed to encode the equivalent number of data states utilizing previous two-state programming approaches. These extra bits could be used for error correction code (ECC) and/or data redundancy operations, for instance.

As used herein, “a”, “an”, or “a number of” can refer to one or more of something, and “a plurality of” can refer to two or more such things. For example, a memory device can refer to one or more memory devices, and a plurality of memory devices can refer to two or more memory devices. Additionally, the designators “N” and “M”, as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits.

FIG. 1is a three-dimensional view of an example of a memory array100(e.g., a cross-point memory array), in accordance with an embodiment of the present disclosure. Memory array100may include a plurality of first signal lines (e.g., first access lines), which may be referred to as word lines110-0to110-N, and a plurality second signal lines (e.g., second access lines), which may be referred to as bit lines120-0to120-M) that cross each other (e.g., intersect in different planes). For example, each of word lines110-0to110-N may cross bit lines120-0to120-M. A memory cell125may be between the bit line and the word line (e.g., at each bit line/word line crossing).

The memory cells125may be resistance variable memory cells, for example. The memory cells125may include a material programmable to different data states. In some examples, each of memory cells125may include a single material that may serve as a select element (e.g., a switching material) and a storage element, so that each memory cell125may act as both a selector device and a memory element. Such a memory cell may be referred to herein as a self-selecting memory cell. For example, each memory cell may include a chalcogenide material that may be formed of various doped or undoped materials, that may or may not be a phase-change material, and/or that may or may not undergo a phase change during reading and/or writing the memory cell. In some examples, each memory cell125may include a ternary composition that may include selenium (Se), arsenic (As), and germanium (Ge), a quaternary composition that may include silicon (Si), Se, As, and Ge, etc.

In various embodiments, the threshold voltages of memory cells125may snap back in response to a magnitude of an applied voltage differential across them exceeding their threshold voltages. Such memory cells may be referred to as snapback memory cells. For example, a memory cell125may change (e.g., snap back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., lower impedance) state in response to the applied voltage differential exceeding the threshold voltage. For example, a memory cell snapping back may refer to the memory cell transitioning from a high impedance state to a lower impedance state responsive to a voltage differential applied across the memory cell being greater than the threshold voltage of the memory cell. A threshold voltage of a memory cell snapping back may be referred to as a snapback event, for example.

FIG. 2Aillustrates threshold distributions associated with various states of memory cells, such as memory cells125illustrated inFIG. 1, in accordance with an embodiment of the present disclosure. For instance, as shown inFIG. 2A, the memory cells can be programmed to one of three possible data states (e.g., state 0, state 1, or state T). That is,FIG. 2Aillustrates threshold voltage distributions associated with three possible data states to which the memory cells can be programmed.

InFIG. 2A, the voltage VCELL may correspond to a voltage differential applied to (e.g., across) the memory cell, such as the difference between a bit line voltage (VBL) and a word line voltage (VWL) (e.g., VCELL=VBL−VWL). The threshold voltage distributions (e.g., ranges)200-1,200-2,201-1,201-2,202-T1, and202-T2may represent a statistical variation in the threshold voltages of memory cells programmed to a particular state. The distributions illustrated inFIG. 2Acorrespond to the current versus voltage curves described further in conjunction withFIGS. 2B and 2C, which illustrate snapback asymmetry associated with assigned data states.

In some examples, the magnitudes of the threshold voltages of a memory cell125in a particular state may be asymmetric for different polarities, as shown inFIGS. 2A, 2B and 2C. For example, the threshold voltage of a memory cell125programmed to state 0 or state 1 may have a different magnitude in one polarity than in an opposite polarity. For instance, in the example illustrated inFIG. 2A, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions201-1and201-2) whose magnitude is greater for a negative polarity than a positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions200-1and200-2) whose magnitude is greater for a positive polarity than a negative polarity. In such an example, an applied voltage magnitude sufficient to cause a memory cell125to snap back can be different (e.g., higher or lower) for one applied voltage polarity than the other.

In some examples, the magnitudes of the threshold voltages of a memory cell125in a particular state may be symmetric for different polarities, as shown inFIG. 2A. For example, the threshold voltage of a memory cell125programmed to state T may have the same magnitude in opposite polarities. For instance, in the example illustrated inFIG. 2A, a third data state (e.g., state T) is associated with a symmetric threshold voltage distribution (e.g., threshold voltage distributions202-T1and202-T2) whose magnitude is substantially equal (e.g. high) for both a positive polarity and a negative polarity. In such an example, an applied voltage magnitude sufficient to cause a memory cell125to snap back can be the same for different applied voltage polarities.

FIG. 2Aillustrates demarcation voltages VDM1and VDM2, which can be used to determine the state of a memory cell (e.g., to distinguish between states as part of a read operation). In this example, VDM1is a positive voltage used to distinguish cells in state 0 (e.g., in threshold voltage distribution201-2) from cells in state 1 (e.g., threshold voltage distribution200-2) or state T (e.g., threshold voltage distribution202-T2). Similarly, VDM2is a negative voltage used to distinguish cells in state 1 (e.g., threshold voltage distribution200-1) from cells in state 0 (e.g., threshold voltage distribution201-1) or state T (e.g., threshold voltage distribution202-T1). In the examples ofFIGS. 2A-2C, a memory cell125in a positive state 1 or T does not snap back in response to applying VDM1; a memory cell125in a positive state 0 snaps back in response to applying VDM1; a memory cell125in a negative state 1 snaps back in response to applying VDM2; and a memory cell125in a negative state 0 or T does not snap back in response to applying VDM2.

Embodiments are not limited to the example shown inFIG. 2A. For example, the designations of state 0 and state 1 can be interchanged (e.g., distributions201-1and201-2can be designated as state 1 and distributions200-1and200-2can be designated as state 0).

FIGS. 2B and 2Care examples of current-versus-voltage curves corresponding to the memory states ofFIG. 2A, in accordance with an embodiment of the present disclosure. As such, in this example, the curves inFIGS. 2B and 2Ccorrespond to cells in which state 1 is designated as the higher threshold voltage state in a particular polarity (positive polarity direction in this example), and in which state 0 is designated as the higher threshold voltage state in the opposite polarity (negative polarity direction in this example). As noted above, the state designation can be interchanged such that state 0 could correspond to the higher threshold voltage state in the positive polarity direction with state 1 corresponding to the higher threshold voltage state in the negative direction.

FIGS. 2B and 2Cillustrate memory cell snapback as described herein. VCELL can represent an applied voltage across the memory cell. For example, VCELL can be a voltage applied to a top electrode corresponding to the cell minus a voltage applied to a bottom electrode corresponding to the cell (e.g., via a respective word line and bit line). As shown inFIG. 2B, responsive to an applied positive polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution200-2) is in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be referred to as a snapback event, which occurs when the voltage applied across the cell (in a particular polarity) exceeds the cell's threshold voltage. Accordingly, voltage Vtst02can be referred to as a snapback voltage. InFIG. 2B, voltage Vtst01corresponds to a snapback voltage for a cell programmed to state 1 (e.g., threshold voltage distribution200-1). That is, as shown inFIG. 2B, the memory cell transitions (e.g., switches) to a conductive state when VCELL exceeds Vtst01in the negative polarity direction.

Similarly, as shown inFIG. 2C, responsive to an applied negative polarity voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution201-1) is in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell snaps back to a conductive (e.g., lower resistance) state. InFIG. 2C, voltage Vtst12corresponds to the snapback voltage for a cell programmed to state 0 (e.g., threshold voltage distribution201-2). That is, as shown inFIG. 2C, the memory cell snaps back from a high impedance non-conductive state to a lower impedance conductive state when VCELL exceeds Vtst12in the positive polarity direction.

In various instances, a snapback event can result in a memory cell switching states. For instance, if a VCELL exceeding Vtst02is applied to a state 1 cell, the resulting snapback event may reduce the threshold voltage of the cell to a level below VDM1, which would result in the cell being read as state 0 (e.g., threshold voltage distribution201-2). As such, in a number of embodiments, a snapback event can be used to write a cell to the opposite state (e.g., from state 1 to state 0 and vice versa).

In an embodiment of the present disclosure, a memory cell, such as memory cells125illustrated inFIG. 1, can be programmed to one of three possible data states (e.g., state 0, state 1, or state T) by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage cell, and applying (e.g., determining whether to apply) an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back. For instance, the current data state of the memory cell can be determined based on the determination of whether the memory cell snaps back, and the additional voltage pulse can be applied to the memory cell (e.g., it can be determined whether to apply the additional voltage pulse to the memory cell) based on the determination of the current data state of the cell.

For example, a bias voltage pulse (e.g., VCELL) with a magnitude high enough to cause (e.g., to be capable of causing) the memory cell to snap back can be applied to the cell. The bias voltage pulse can comprise, for instance, a voltage pulse having a first polarity and/or a voltage pulse having a second polarity that is opposite the first polarity. For instance, applying the bias voltage pulse can comprise applying a positive 5.5 Volt (V) pulse and/or a negative 5.5 V pulse to the memory cell.

Once (e.g., if) the memory cell snaps back to the conductive state in response to the applied bias voltage pulse, a pulse of current (e.g., a current transient) may flow through the memory cell. After a particular amount of time, the current transient through the cell may dissipate, and a DC current may be established across the cell. An example illustrating such a current flow through the memory cell will be further described herein (e.g., in connection withFIG. 4).

After the voltage pulse (e.g., the bias voltage pulse) has been applied to the memory cell, it can be determined whether the memory cell has snapped back in response to the applied voltage pulse (e.g., in response to the positive or negative pulse). This determination can be made by, for example, sensing a voltage change associated with the memory cell (e.g., on a signal line coupled to the cell) that has occurred in response to the applied voltage pulse. For instance, sensing such a voltage change may indicate that the memory cell has snapped back, while sensing no voltage change may indicate that a snapback event has not occurred. An example further illustrating such a determination of whether the memory cell has snapped back, and the circuitry that can be used to perform such a determination, will be further described herein (e.g., in connection withFIG. 3).

The current data state of the memory cell can then be determined based on the determination of whether the memory cell has snapped back. For instance, a data value indicative of the current data state can be latched (e.g., stored in a latch) upon determining the memory cell has snapped back, as will be further described herein (e.g., in connection withFIG. 3).

After determining the memory cell has snapped back (e.g., after a delay to allow for the current transient through the memory cell to dissipate), the current to the memory cell (e.g., the current flow through the signal line coupled to the memory cell) may be turned off (e.g., inhibited). An additional voltage pulse can then be applied to the memory cell (e.g., it can be determined whether to apply the additional voltage pulse to the memory cell) based on the determination of whether the memory cell has snapped back (e.g., based on the determination of the current data state of the memory cell). For instance, the additional voltage pulse can be a single short pulse or can comprise a plurality of pulses based on whether the memory cell has snapped back, and/or can be a positive polarity or a negative polarity based on whether the memory cell has snapped back, as will be further described herein. As used herein, a short pulse can refer to a pulse having a duration that is shorter than the duration of the bias voltage. The magnitude of the additional voltage pulse can be the same as the magnitude of the bias voltage, for example. As an additional example, the initial bias voltage pulse may be extended after determining the memory cell has snapped back.

Applying the additional voltage pulse (or extending the initial bias voltage pulse) to a memory cell currently in a 0 state or a 1 state may not change the magnitude of the threshold voltage of the cell if the threshold voltage is a first polarity, but may change the magnitude of the threshold voltage of the cell if the threshold voltage is a second polarity that is opposite the first polarity. For example, the additional voltage pulse may not change a high magnitude threshold voltage of one polarity, but may increase a low magnitude threshold voltage of the opposite polarity from the low magnitude to a high magnitude. For instance, the additional voltage pulse may not change a threshold voltage that is within distribution201-1, but may move a threshold voltage from distribution201-2to200-2. Similarly, the additional voltage pulse may not change a threshold voltage that is within distribution200-2, but may move a threshold voltage from distribution200-1to201-1.

In contrast, applying the additional voltage pulse to a memory cell currently in a T state may not change the high magnitude of the threshold voltage of the cell regardless of the polarity of the threshold voltage. For instance, the additional voltage pulse may not change a threshold voltage that is within distribution202-T1or202-T2. As such, embodiments of the present disclosure can program the memory cell to a third data state (e.g., state T), in addition to states 0 and 1.

As an example, to program the memory cell to state T, a first bias voltage (e.g., a detection bias voltage) pulse having a positive polarity can be applied to the cell, and it can be determined whether the memory cell snaps back in response to the applied first bias voltage pulse. If it is determined (e.g., detected) that the memory cell has snapped back, the current data state of the cell may be 0. Upon determining that the memory cell has snapped back in response to the first bias voltage pulse (e.g., that the current data state of the cell is 0), a single (e.g., one) short additional pulse having a negative polarity can be applied to the cell to program the cell to state T.

If no snap back of the memory cell is detected in response to the first bias voltage pulse, the current data state of the cell may be 1 or T. Upon determining that the memory cell did not snap back in response to the first bias voltage pulse, a second bias voltage pulse having a negative polarity can be applied to the cell, and it can be determined whether the cell snaps back in response to the applied second bias voltage pulse.

If it is determined that the memory cell has snapped back in response to the second bias voltage pulse, the current data state of the cell may be 1. Upon determining that the memory cell has snapped back in response to the second bias voltage pulse (e.g., that the current data state of the cell is 1), a single short additional voltage pulse having a positive polarity can be applied to the cell to program the cell to state T. If no snap back of the memory cell is detected in response to the second bias voltage pulse, the current data state of the cell may be T, and no additional pulses may be needed to program the cell to state T. Accordingly, upon determining that the memory cell has not snapped back in response to the second bias voltage pulse (e.g., that the current data state of the cell is T), an additional short voltage pulse may not be applied. An example further illustrating the programming of the memory cell to state T will be further described herein (e.g., in connection withFIGS. 5A-5B).

Additionally or alternatively, the memory cell can be programmed to state T without applying the bias voltage pulse(s) to the cell (e.g., without attempting to detect a snap back of the memory cell or the current data state of the memory cell). For example, two short voltage pulses of opposite polarity (e.g., one positive and one negative, or vice versa) can be applied to the memory cell to program the cell to state T, regardless of the current data state of the cell.

As an additional example, to program the memory cell to state 0, a bias voltage pulse having a positive polarity can be applied to the cell, and it can be determined whether the memory cell snaps back in response to the applied bias voltage pulse. If it is determined (e.g., detected) that the memory cell has snapped back, the current data state of the cell may be 0, and no additional pulses may be needed to program the cell to state 0. Accordingly, upon determining that the memory cell has snapped back in response to the bias voltage pulse (e.g., that the current data state of the cell is 0), no additional voltage pulses may be applied to the memory cell.

If no snap back of the memory cell is detected in response to the bias voltage pulse, the current data state of the cell may be 1 or T. Upon determining that the memory cell did not snap back in response to the bias voltage pulse (e.g., that the current data state of the cell is 1 or T), a plurality of short additional voltage pulses, each having a positive polarity, can be applied to the cell to program the cell to state 0. For instance, six short additional positive voltage pulses can be applied to the cell. Embodiments of the present disclosure, however, are not limited to a particular number of additional voltage pulses. Further, as an additional example, a single voltage pulse having a larger magnitude and/or duration than the bias voltage pulse can be applied to the cell to program the cell to state 0.

Additionally or alternatively, the memory cell can be programmed to state 0 without applying the bias voltage pulse to the cell (e.g., without attempting to detect a snap back of the memory cell or the current data state of the memory cell). For example, a plurality of short voltage pulses, each of positive polarity, can be applied to the memory cell to program the cell to state 0, regardless of the current data state of the cell. Further, as an additional example, a single voltage pulse having a larger magnitude and/or duration than the bias voltage pulse can be applied to the cell to program the cell to state 0.

As an additional example, to program the memory cell to state 1, a first bias voltage pulse having a positive polarity can be applied to the cell, and it can be determined whether the memory cell snaps back in response to the applied first bias voltage pulse. If it is determined (e.g., detected) that the memory cell has snapped back, the current data state of the cell may be 0. Upon determining that the memory cell has snapped back in response to the first bias voltage pulse (e.g., that the current data state of the cell is 0), a plurality of short additional voltage pulses, each having a negative polarity, can be applied to the cell to program the cell to state 1. For instance, six short additional negative voltage pulses can be applied to the cell. Embodiments of the present disclosure, however, are not limited to a particular number of additional voltage pulses. Further, as an additional example, a single voltage pulse having a larger magnitude and/or duration than the first bias voltage pulse can be applied to the cell to program the cell to state 1.

If no snap back of the memory cell is detected in response to the first bias voltage pulse, the current data state of the cell may be 1 or T. Upon determining that the memory cell did not snap back in response to the first bias voltage pulse, a second bias voltage pulse having a negative polarity can be applied to the cell, and it can be determined whether the cell snaps back in response to the applied second bias voltage pulse.

If it is determined that the memory cell has snapped back in response to the second bias voltage pulse, the current data state of the cell may be 1. Upon determining that the memory cell has snapped back in response to the second bias voltage pulse (e.g., that the current data state of the cell is 1), and no additional negative voltage pulses may be needed to program the cell to state 1. Accordingly, upon determining that the memory cell has snapped back in response to the second bias voltage pulse (e.g., that the current data state of the cell is 1), no additional negative voltage pulses may be applied to the memory cell.

If no snap back of the memory cell is detected in response to the second bias voltage pulse, the current data state of the cell may be T. Upon determining that the memory cell has not snapped back in response to the second bias voltage pulse (e.g., that the current data state of the cell is T), the plurality of short additional negative voltage pulses can be applied to the cell to program the cell to state 1. Further, as an additional example, a single voltage pulse having a larger magnitude and/or duration than the second bias voltage pulse can be applied to the cell to program the cell to state 1.

Additionally or alternatively, the memory cell can be programmed to state 1 without applying the bias voltage pulse(s) to the cell (e.g., without attempting to detect a snap back of the memory cell or the current data state of the memory cell). For example, a plurality of short voltage pulses, each of negative polarity, can be applied to the memory cell to program the cell to state 1, regardless of the current data state of the cell. Further, as an additional example, a single voltage pulse having a larger magnitude and/or duration than the bias voltage pulse(s) can be applied to the cell to program the cell to state 1.

FIG. 3illustrates an example of a portion of a memory array300and associated circuitry for detecting snapback events in accordance with an embodiment of the present disclosure. Memory array300may be a portion of memory array100previously described in connection withFIG. 1. Memory cell325is coupled to a word line310and a bit line320and may be operated as described herein.

The example shown inFIG. 3includes a driver350(e.g., a word line driver350) coupled to word line310. Word line driver350may supply bi-polar (e.g., positive and negative) current and/or voltage signals to word line310. A sense amplifier330, which may comprise a cross-coupled latch, is coupled to word line driver350, and may detect positive and negative currents and/or positive and negative voltages on word line310. In some examples, sense amplifier330may be part of (e.g., included in) word line driver350. For example, the word line driver350may include the sensing functionality of sense amplifier330. A bit line driver352is coupled to bit line320to supply positive and/or negative current and/or voltage signals to bit line320.

The sense amplifier330and word line driver350are coupled to a latch340, which can be used to store a data value indicating whether or not a snapback event of cell325has occurred responsive to an applied voltage differential. For instance, an output signal354of sense amplifier330is coupled to latch340such that responsive to detection, via sense amplifier330, of memory cell325snapping back, the output signal354causes the appropriate data value to be latched in latch340(e.g., a data value of “1” or “0” depending on which data value is used to indicate a detected snapback event). As an example, if a latched data value of “1” is used to indicate a detected snapback event, then signal354will cause latch340to latch a data value of logical 1 responsive to a detected snapback of cell325, and vice versa.

When a positive voltage differential VDM1is applied to memory cell325(e.g., the word line voltage VWL1is low and the bit line voltage VBL1is high) and memory cell325stores state 0, voltage differential VDM1may be greater than the threshold voltage Vtst12(FIG. 2C), and memory cell325may snap back to a conductive state, causing the positive current flow, shown inFIG. 2C, through memory cell325from bit line320to word line310. Sense amplifier330may detect this current, and/or a voltage associated therewith, for example, and may output signal354to latch340in response to detecting this current and/or voltage. For example, signal354may indicate to latch340(e.g., by having a logical high value) that current is positive, and thus that word line voltage is high. In response to the signal354indicating that the word line voltage is high, latch340may output a signal356(e.g. voltage) to circuitry358of or coupled to word line driver350that turns off (e.g., inhibits) the current flow through word line310, and thus through memory cell325.

In examples, when a negative voltage differential VDM2is applied to memory cell325(e.g., the word line voltage VWL2is high and the bit line voltage VBL2is low) and memory cell325stores state 1, voltage differential VDM2is greater (in a negative sense) than the threshold voltage Vtst01(FIG. 2B), and memory cell328may snap back to a conductive state, causing the negative current flow, shown inFIG. 2B, through memory cell325from word line310to bit line320. Sense amplifier330may detect this current, and/or a voltage associated therewith, for example, and may output the signal354to latch340in response to detecting this current and/or a voltage. For example, signal354may indicate to latch340that current is negative (e.g., by having a logical low value), and thus that word line voltage is low. In response to the signal354indicating that the word line voltage is low, latch340may output a signal360(e.g. voltage) to circuitry362of or coupled to word line driver350that turns off the current flow through word line310. In some examples, sense amplifier330in combination with circuitries358and362may be referred to as detection circuitry.

FIG. 4illustrates an example, in the form of graph435, of current flow through a memory cell, in accordance with an embodiment of the present disclosure. For example, graph435can illustrate the current flow through a memory cell during an operation to program the memory cell to one of three possible data states in accordance with the present disclosure. The memory cell can be, for example, memory cell325and/or125previously described in connection withFIGS. 3 and 1, respectively.

At time t1shown inFIG. 4, a bias voltage pulse with a magnitude high enough to cause the memory cell to snap back is applied to the memory cell. When the memory cell snaps back, a pulse437of current flows through the memory cell, as illustrated inFIG. 4, which can be used to detect the snap back event, as previously described herein. The current flow then dissipates after time t1, as shown inFIG. 4, and a DC current is established across the memory cell.

At time t2shown inFIG. 4(e.g., after memory cell has snapped back and the snapback event has been detected), the current to the memory cell is turned off (e.g., inhibited). When the current to the memory cell is turned off, no current flows through the cell, as illustrated inFIG. 4.

At time t3shown inFIG. 4(e.g., after the current to the memory cell has been turned off), an additional voltage pulse can be applied to the memory cell. The additional voltage pulse can be applied to the memory cell based on a determination that the memory cell has snapped back, as previously described herein. Further, the additional pulse is applied to memory cell for a short amount of time (e.g., from time t3to time t4), as illustrated inFIG. 4, and can have a negative or positive polarity, as previously described herein. As an additional example, the additional pulse can have a longer duration, and/or comprise a plurality of voltage pulses, as previously described herein.

When the additional voltage pulse is applied to the memory cell, an additional pulse439of current flows through the memory cell, as illustrated inFIG. 4. The additional pulse of current439can cause the memory cell to be programmed to one of the three possible data states, as previously described herein.

FIGS. 5A-5Billustrate examples of programming a memory cell to a third data state (e.g., state T) in accordance with an embodiment of the present disclosure. For instance,FIG. 5Aillustrates an example551of programming a memory cell that is currently in a first data state (e.g., state 0) to state T, andFIG. 5Billustrates an example553of programming a memory cell that is currently in a second data state (e.g., state 1) to state T. The memory cell can be, for instance, memory cell325and/or125previously described in connection withFIGS. 3 and 1, respectively. Further, demarcation voltages VDM1and VDM2illustrated inFIGS. 5A-5Bcan be analogous to demarcation voltages VDM1and VDM2, respectively, previously described in connection withFIGS. 2A-2C. Further, although the high magnitude threshold voltage distributions associated with state T are shown inFIGS. 5A-5Bas being separate from the high magnitude threshold voltage distributions associated with states 0 and 1, these distributions may overlap, as in the example previously described in connection withFIG. 2A.

As shown in the example illustrated inFIG. 5A, applying a single short voltage pulse having a negative polarity and a magnitude greater than VDM1and VDM2(e.g., sufficient to reach the high threshold voltage state of the target memory cell) to a memory cell currently in state 0 can program the cell to state T (e.g., change the state of the cell from 0 to T). For example, as shown inFIG. 5A, the single short voltage pulse may not change a threshold voltage of the cell observed (e.g., measured) as a high magnitude threshold in the negative direction. However, a threshold voltage of the cell observed as a low magnitude threshold in the positive direction may increase to a high magnitude threshold, as shown inFIG. 5A.

As shown in the example illustrated inFIG. 5B, applying a single short voltage pulse having a positive polarity and a magnitude greater than VDM1and VDM2(e.g., sufficient to reach the high threshold voltage state of the target memory cell) to a memory cell currently in state 1 can program the cell to state T (e.g., change the state of the cell from 1 to T). For example, as shown inFIG. 5B, the single short voltage pulse may not change a threshold voltage of the cell observed as a high magnitude threshold in the positive direction. However, a threshold voltage of the cell observed as a low magnitude threshold in the negative direction may increase to a high magnitude threshold, as shown inFIG. 5B.

FIG. 6is a block diagram illustration of an example apparatus, such as an electronic memory system600, in accordance with an embodiment of the present disclosure. Memory system600includes an apparatus, such as a memory device602, and a controller604, such as a memory controller (e.g., a host controller). Controller604might include a processor, for example. Controller604might be coupled to a host, for example, and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host and may output data to the host.

Memory device602includes a memory array606of memory cells. For example, memory array606may include one or more of the memory arrays, such as a cross-point array, of memory cells disclosed herein.

Memory device602includes address circuitry608to latch address signals provided over I/O connections610through I/O circuitry612. Address signals are received and decoded by a row decoder614and a column decoder616to access the memory array606. For example, row decoder614and/or column decoder616may include drivers, such as drivers350, as previously described in conjunction withFIG. 3.

Memory device602may sense (e.g., read) data in memory array606by sensing voltage and/or current changes in the memory array columns using sense/buffer circuitry that in some examples may be read/latch circuitry620. Read/latch circuitry620may read and latch data from the memory array606. I/O circuitry612is included for bi-directional data communication over the I/O connections610with controller604. Write circuitry622is included to write data to memory array606.

Control circuitry624may decode signals provided by control connections626from controller604. These signals may include chip signals, write enable signals, and address latch signals that are used to control the operations on memory array606, including data read and data write operations.

Control circuitry624may be included in controller604, for example. Controller604may include other circuitry, firmware, software, or the like, whether alone or in combination. Controller604may be an external controller (e.g., in a separate die from the memory array606, whether wholly or in part) or an internal controller (e.g., included in a same die as the memory array606). For example, an internal controller might be a state machine or a memory sequencer.

In some examples, controller604may be configured to cause memory device602to at least perform the methods disclosed herein, such as programming the memory cells of array606to one of three possible data states. In some examples, memory device602may include the circuitry previously described in conjunction withFIG. 3. For example, memory device602may include the sense amplifier circuitry and latches, such as sense amplifier330and latch340, disclosed herein.

As used herein, the term “coupled” may include electrically coupled, directly coupled, and/or directly connected with no intervening elements (e.g., by direct physical contact) or indirectly coupled and/or connected with intervening elements. The term coupled may further include two or more elements that co-operate or interact with each other (e.g., as in a cause and effect relationship).

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory system600ofFIG. 6has been simplified. It should be recognized that the functionality of the various block components described with reference toFIG. 6may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component ofFIG. 6. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component ofFIG. 6.