Semiconductor device having positive fixed charge containing layer

A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0001511 filed on Jan. 6, 2014, in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

FIELD

An aspect of the inventive concepts relates to a semiconductor device, and more particularly, to a semiconductor device having a positive fixed charge containing layer.

BACKGROUND

Semiconductor devices including isolation technology for isolating a large number of semiconductor devices may be used in highly integrated circuits.

SUMMARY

According to an aspect of the inventive concept, there is provided a semiconductor device including a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.

In some embodiments, the upper surfaces of the word lines are lower than those of the upper surfaces of the plurality of active regions.

In some embodiments, the plurality of word lines may be bulb-type word lines that have lower cross-sections that are circular or have U-shaped lower cross-sections. On the other hand, the positive fixed charge containing layer may be formed of a different material from that of the isolation film. The isolation film may be formed of a single material.

In some embodiments, each of the plurality of word lines may include a first portion positioned between two active regions adjacent in the first direction and a second portion positioned between two active regions adjacent in the second direction, the first portion may be surrounded by the isolation film and the positive fixed charge containing layer, and the second portion may be surrounded by the isolation film.

In some embodiments, the positive fixed charge containing layer may cover side and lower surfaces of the plurality of word lines. In addition, an upper surface of the positive fixed charge containing layer may be positioned on an identical level as that of upper surfaces of the plurality of word lines.

In some embodiments, the positive fixed charge containing layer may be formed of silicon nitride or silicon oxynitride.

According to another aspect of the inventive concept, there is provided a semiconductor device including a semiconductor substrate having a trench, an isolation film in the trench, a plurality of active regions defined in the semiconductor substrate by the isolation film, a plurality of word lines that extend across the plurality of active regions and the isolation film, a positive fixed charge containing layer covering at least parts of the plurality of word lines, respectively, a first interlayer insulating film covering the plurality of active regions and the isolation film, a bit line on the first interlayer insulating film, a bit line contact connecting the bit line and a first active region selected from the plurality of active regions, a second interlayer insulating film covering the bit line on the first interlayer insulating film, a first storage electrode formed on the second interlayer insulating film, and a first storage contact connecting the first storage electrode and the first active region.

In some embodiments, a distance from the positive fixed charge containing layer to the first storage contact in the first direction may be smaller than a distance from the positive fixed charge containing layer to the bit line contact in the first direction.

In some embodiments, the semiconductor device may further include a second active region adjacent to the first active region among the plurality of active regions in a second direction, a second storage electrode connected to the second active region, and a second storage contact connecting the second storage electrode and the second active region. The isolation film positioned between the bit line contact on the first active region and the second storage contact may be an oxide film.

In some embodiments, the positive fixed charge containing layer may continuously extend along the plurality of word lines. On the other hand, among the plurality of active regions, a pair of active regions adjacent in the second direction may be shifted in opposite directions in the first direction to partially overlap in the second direction so that the pair of active regions are aligned athwart and the positive fixed charge containing layer may be absent from between the pair of active regions.

According to still another aspect of the inventive concept, there is provided a semiconductor device including a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively, wherein at least a portion of the positive fixed charge containing layer is disposed in the isolation film.

In some embodiments, the positive fixed charge containing layer may not contact with the plurality of the active regions.

In some embodiments, the positive fixed charge containing layer may extend into the plurality of the active regions.

In some embodiments, the upper surfaces of the plurality of word lines may have lower levels than those of upper surfaces of the plurality of active regions.

In some embodiments, the positive fixed charge containing layer may cover side and lower surfaces of the plurality of word lines.

DETAILED DESCRIPTION OF EMBODIMENTS

The inventive concept is described hereinafter with reference to the accompanying drawings, in which elements of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to one of ordinary skill in the art. The same elements in the drawings are denoted by the same reference numerals and a repeated explanation thereof will not be given.

In other embodiments, a specific order of processes may be changed. For example, two processes consecutively described herein may be simultaneously performed or may be performed in an order opposite to that described.

Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be construed to include deviations in shapes that result, for example, from manufacturing.

FIG. 1Ais a plan view illustrating a partial structure of a semiconductor device100according to embodiments of the inventive concept.FIG. 1Bis a cross-sectional view taken along line B1-B1′ ofFIG. 1A.FIG. 1Cis a cross-sectional view taken along line C1-C1′ ofFIG. 1A.

Referring toFIGS. 1A to 1C, the semiconductor device100includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines130, a gate dielectric film132, a gate capping layer134, and a positive fixed charge containing layer140.

Each of the plurality of active regions110includes an upper surface110T having a long axis in a first direction (the X direction ofFIG. 1A) and a short axis in a second direction (the Y direction ofFIG. 1A). The plurality of active regions110are repeatedly and separately formed in the first direction (the X direction ofFIG. 1A) and the second direction (the Y direction ofFIG. 1A).

The isolation film120includes a plurality of upper surfaces120T separated from each other (when viewed in a plan view). The isolation film120is formed in a trench120H formed in the semiconductor substrate101. In some embodiments, the isolation film120may be formed of a single material, and the single material may be an oxide film. However, the inventive concept is not limited thereto, and the isolation film120may include other material(s) within the scope of the inventive concept.

The plurality of word lines130extend across the plurality of active regions110and the isolation film120. In some embodiments, the plurality of word lines130are positioned on a lower level than that of the upper surfaces110T of the plurality of active regions110or the upper surface120T of the isolation film120. That is, the plurality of word lines130may be formed in a plurality of trenches130H that extend across the plurality of active regions110and the isolation film120. When the plurality of word lines130are formed in the plurality of trenches130H, an effective channel length of the semiconductor device100is increased so that a short channel effect may be reduced. In addition, the plurality of word lines130may be covered with the gate capping layer134.

In some embodiments, the plurality of word lines130may have U-shaped lower cross-sections. The plurality of word lines130may be bulb-type word lines (refer to230ofFIG. 2) that have lower cross-sections that are circular.

Each of the plurality of word lines130includes a first portion130xpositioned between two active regions110xadjacent in the first direction among the plurality of active regions110and a second portion130ypositioned between two active regions110yadjacent in the second direction among the plurality of active regions110. In some embodiments, the first portion130xmay be surrounded by the isolation film120and the positive fixed charge containing layer140. In addition, the second portion130ymay be surrounded by the isolation film120.

In some embodiments, the gate dielectric film132may cover internal walls of the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120. That is, the gate dielectric film132may be interposed between the plurality of word lines130and the plurality of active regions110or between the plurality of word lines130and the isolation film120.

In some embodiments, the gate dielectric film132may be an oxide film and may be formed of the same material as that of the isolation film120. In other embodiments, the gate dielectric film132may be formed of a different material from that of the isolation film120. For example, the gate dielectric film132may be formed as a high K dielectric film.

In some embodiments, the gate capping layer134may be formed to cover the plurality of word lines130. An upper surface134T of the gate capping layer134may be positioned on the same level as those of the upper surfaces110T of the plurality of active regions110and the upper surface120T of the isolation film120.

The positive fixed charge containing layer140covers at least parts of the plurality of word lines130. Here, the positive fixed charge containing layer140may be positioned on a higher level than that of lower surfaces of the plurality of word lines130.

In some embodiments, the positive fixed charge containing layer140may surround the first portion130xpositioned between the two active regions110xadjacent in the first direction and does not surround the second portion130ypositioned between the two active regions110yadjacent in the second direction.

In some embodiments, the positive fixed charge containing layer140is formed of a different material from that of the isolation film120. The positive fixed charge containing layer140may be formed of silicon nitride or silicon oxynitride. However, the inventive concept is not limited thereto and the positive fixed charge containing layer140may include other material(s) within the scope of the inventive concept.

The plurality of active regions110yare repeatedly and separately formed in the second direction,

FIG. 2is a cross-sectional view of a semiconductor device200according to another embodiment of the inventive concept, which is taken along line B1-B1′ ofFIG. 1A. InFIG. 2, the same reference numerals as those ofFIGS. 1A to 1Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 2, the semiconductor device200includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines230, a gate dielectric film232, a gate capping layer134, and a positive fixed charge containing layer140.

The plurality of word lines230extend across the plurality of active regions110and the isolation film120. In some embodiments, the plurality of word lines230are positioned on a lower level than that of upper surfaces110T of the plurality of active regions110or an upper surface120T of the isolation film120. That is, the plurality of word lines230may be formed in a plurality of trenches230H that extend across the plurality of active regions110and the isolation film120. In addition, the plurality of word lines230may be covered with the gate capping layer134.

As illustrated inFIG. 2, the plurality of word lines230may be bulb-type word lines that have lower cross-sections that are circular.

When the plurality of word lines230are the bulb-type word lines, the plurality of word lines230are formed in the semiconductor substrate101. Therefore, an effective channel length of the semiconductor device200can be increased so that a short channel effect may be reduced. In addition, since the plurality of word lines230have circular lower cross-sections, the doping density of the semiconductor substrate101may be reduced and drain-induced barrier lowering (DIBL) may be improved.

Each of the plurality of word lines230includes a first portion130xpositioned between two active regions110xadjacent in a first direction and a second portion130ypositioned between two active regions110yadjacent in a second direction (refer toFIG. 1A). In some embodiments, the first portion130xmay be surrounded by the isolation film120and the positive fixed charge containing layer140. In addition, the second portion130ymay be surrounded by the isolation film120.

In some embodiments, the gate dielectric film232may cover internal walls of the plurality of trenches230H that extend across the plurality of active regions110and the isolation film120. The gate dielectric film232may be interposed between the plurality of word lines230and the plurality of active regions110or between the plurality of word lines230and the isolation film120.

In some embodiments, the gate dielectric film232may be an oxide film and may be formed of the same material as that of the isolation film120. In other embodiments, the gate dielectric film232may be formed of a different material from that of the isolation film120. For example, the gate dielectric film232may be formed as a high K dielectric film.

FIG. 3Ais a plan view illustrating a partial structure of a semiconductor device300according to embodiments of the inventive concept.FIG. 3Bis a cross-sectional view taken along line B3-B3′ ofFIG. 3A.FIG. 3Cis a cross-sectional view taken along line C3-C3′ ofFIG. 3A. InFIGS. 3A to 3C, the same reference numerals as those ofFIGS. 1Ato1C refer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIGS. 3A to 3C, the semiconductor device300includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines130, a gate capping layer134, and a positive fixed charge containing layer340.

In operation of the semiconductor device300, the positive fixed charge containing layer340may function as the gate dielectric film132.

The plurality of word lines130are positioned on a lower level relative to an upper surface340T of the positive fixed charge containing layer340.

In some embodiments, the plurality of word lines130and the positive fixed charge containing layer340may have U-shaped lower cross-sections. In other embodiments, the plurality of word lines130and the positive fixed charge containing layer340may be bulb-type word lines that have lower cross-sections that are circular.

In some embodiments, the positive fixed charge containing layer340covers side and lower surfaces of the plurality of word lines130. That is, the positive fixed charge containing layer340covers internal walls of a plurality of trenches130H that extend across the plurality of active regions110and the isolation film120. The positive fixed charge containing layer340may be interposed between the plurality of word lines130and the plurality of active regions110or between the plurality of word lines130and the isolation film120. The upper surface340T of the positive fixed charge containing layer340is positioned on the same level as those of upper surfaces110T of the plurality of active regions110and an upper surface120T of the isolation film120.

In some embodiments, the positive fixed charge containing layer340may be formed of a different material from that of the isolation film120. The positive fixed charge containing layer340may be formed of silicon nitride or silicon oxynitride. However, the inventive concept is not limited thereto and the positive fixed charge containing layer340may include other material(s) within the scope of the inventive concept.

A plurality of active regions110yare repeatedly and separately formed in a second direction.

In the respective active regions that form the plurality of active regions110y, side surfaces110S of a plurality of active regions110xformed in a first direction are surrounded by the isolation film120. As described above, the isolation film120may be formed of a single material, and the single material may be an oxide film. However, the inventive concept is not limited thereto and the isolation film120may include other material(s) within the scope of the inventive concept.

FIG. 4is a cross-sectional view of a semiconductor device400according to another embodiment of the inventive concept, which is taken along line B3-B3′ ofFIG. 3A. InFIG. 4, the same reference numerals as those ofFIGS. 1A to 3Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 4, the semiconductor device400includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines130, a gate dielectric film432, a gate capping layer134, and a positive fixed charge containing layer440.

The gate dielectric film432may cover parts of internal walls of a plurality of trenches130H that extend across the plurality of active regions110and the isolation film120. That is, the gate dielectric film432may be interposed between the plurality of word lines130and the plurality of active regions110or between the plurality of word lines130and the isolation film120. In some embodiments, an upper surface T432of the gate dielectric film432may be positioned on a lower level than that of upper surfaces130T of the plurality of word lines130.

In some embodiments, the gate dielectric film432may be an oxide film and may be formed of the same material as that of the isolation film120. In other embodiments, the gate dielectric film432may be formed of a different material from that of the isolation film120. For example, the gate dielectric film432may be formed as a high K dielectric film.

The positive fixed charge containing layer440covers at least parts of the plurality of the word lines130. In some embodiments, the positive fixed charge containing layer440covers side surfaces of the plurality of word lines130and the gate capping layer134. Here, the positive fixed charge containing layer440may be positioned on a higher level than that of lower surfaces of the plurality of word lines130. An upper surface440T of the positive fixed charge containing layer440is positioned on the same level as those of upper surfaces110T of the plurality of active regions110and an upper surface120T of the isolation film120.

Alternatively, the positive fixed charge containing layer440may be formed by processes described with respect toFIGS. 10A to 10E.

In some embodiments, the positive fixed charge containing layer440may be formed of a different material from that of the isolation film120. The positive fixed charge containing layer440may be formed of silicon nitride or silicon oxynitride. However, the inventive concept is not limited thereto and the positive fixed charge containing layer440may include other material(s) within the scope of the inventive concept.

FIG. 5is a cross-sectional view of a semiconductor device500according to another embodiment of the inventive concept, which is taken along line B3-B3′ ofFIG. 3A. InFIG. 5, the same reference numerals as those ofFIGS. 1A to 4refer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 5, the semiconductor device500includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines130, a gate capping layer534, and a positive fixed charge containing layer540.

In operation of the semiconductor device500, the positive fixed charge containing layer540may function as the gate dielectric film132.

In some embodiments, side surfaces534S of the gate capping layer534may be surrounded by the plurality of active regions110or the isolation film120. An upper surface534T of the gate capping layer534is positioned on the same level as those of upper surfaces110T of the plurality of active regions110and an upper surface120T of the isolation film120.

The positive fixed charge containing layer540covers side and lower surfaces of the plurality of word lines130. In some embodiments, an upper surface540T of the positive fixed charge containing layer540is positioned on the same level as that of upper surfaces130T of the plurality of word lines130.

In some embodiments, the positive fixed charge containing layer540may have a U-shaped lower cross-section. In other embodiments, the positive fixed charge containing layer540may have a circular lower cross-section.

In some embodiments, the positive fixed charge containing layer540may be formed of a different material from that of the isolation film120. The positive fixed charge containing layer540may be formed of silicon nitride or silicon oxynitride. However, the inventive concept is not limited thereto and the positive fixed charge containing layer540may include other material(s) within the scope of the inventive concept.

FIG. 6Ais a plan view illustrating a partial structure of a semiconductor device600according to embodiments of the inventive concept.FIG. 6Bis a cross-sectional view taken along line B6-B6′ ofFIG. 6A.FIG. 6Cis a cross-sectional view taken along line C6-C6′ ofFIG. 6A. InFIGS. 6A to 6C, the same reference numerals as those ofFIGS. 1A to 5refer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIGS. 6A to 6C, the semiconductor device600includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines130, a positive fixed charge containing layer140, a first interlayer insulating film650, a second interlayer insulating film652, a bit line660, a bit line contact662, a first storage electrode670a, a second storage electrode670b, a first storage contact672a, and a second storage contact672b.

The semiconductor device600may be, for example, a part of a cell array region of a semiconductor memory device.

Each of the plurality of active regions110includes an upper surface having a long axis in a first direction (the X direction ofFIG. 6A) and a short axis in a second direction (the Y direction ofFIG. 6A). The plurality of active regions110are repeatedly and separately formed in the first direction (the X direction ofFIG. 6A) and the second direction (the Y direction ofFIG. 6A).

The semiconductor substrate101is planar having lower and upper surfaces and includes a plurality of trenches130H that extend across the plurality of active regions110and the isolation film120. In some embodiments, the semiconductor substrate101may be, for example, a silicon substrate. The isolation film120is formed in a trench120H formed in the semiconductor substrate101.

The plurality of active regions110are defined in the semiconductor substrate101by the isolation film120. Here, the plurality of active regions110may be angled with respect to the plurality of word lines130and the bit line660at a predetermined angle. That is, in order to minimize a cell area of the semiconductor device600, the plurality of word lines130and the bit line660may perpendicularly intersect, respectively. Here, the plurality of active regions11Q may be limited to being bar-shaped by the isolation film120and may be diagonal with respect to the plurality of word lines130and the bit line660.

Among the plurality of active regions110, a pair of active regions110zadjacent in the second direction, are shifted in opposite directions in the first direction to partially overlap in the second direction so that the pair of active regions110zmay be aligned athwart.

In some embodiments, among the plurality of active regions110, between the pair of active regions110zadjacent in the second direction, the positive fixed charge containing layer140is not formed.

Each of the plurality of active regions110may include a first source/drain region110aand a second source/drain region110b. The first source/drain region110aand the second source/drain region110bmay be formed by, for example, an ion implantation process.

In a first active region610aselected from the plurality of active regions110, two adjacent word lines among the plurality of word lines130and the bit line660may intersect.

A second active region610bis defined as an active region adjacent to the first active region610ain the second direction among the plurality of active regions110. In some embodiments, the isolation film120positioned between the bit line contact662on the first active region610aand the second storage contact672bmay be formed of an oxide film.

In some embodiments, a distance D1from the positive fixed charge containing layer140to the first storage contact672ain the first direction is smaller than a distance D2from the positive fixed charge containing layer140to the bit line contact662in the first direction.

The first interlayer insulating film650covers the plurality of active regions110and the isolation film120on the semiconductor substrate101. That is, the first interlayer insulating film650covers an upper surface on which processes to be described with respect toFIGS. 8A to 11Care performed. In some embodiments, the first interlayer insulating film650is formed by a deposition process and, after the first interlayer insulating film650is formed, a chemical mechanical polishing (CMP) process may be performed. The first interlayer insulating film650may be, for example, oxide or nitride film based.

The bit line660diagonally extends with respect to the first direction. In addition, the bit line660may extend orthogonal to the plurality of word lines130. In some embodiments, the bit line660may be formed of doped silicon having conductivity. However, the inventive concept is not limited thereto and the bit line660may be formed of metal or a metal compound. For example, the bit line660may be formed of metal such as tungsten (W), aluminium (Al), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), and ruthenium (Ru), metal nitride such as titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN), or metal silicide such as cobalt silicide (CoSi2), titanium silicide (TiSiO2), and tungsten silicide (WSi2).

The bit line660may have two or more kinds of widths in accordance with a position thereof A width of the bit line660may increase with respect to the bit line contact662. Therefore, the bit line660may have a tab structure in which a portion thereof that overlaps the first source/drain region110amay have a larger width than that of a portion thereof that does not overlap the first source/drain region110a.

The bit line contact662connects the bit line660and the first source/drain region110a. The bit line contact662may be formed of doped silicon, like the bit line660. The bit line660may further include carbon.

A bit line contact hole for forming the bit line contact662may be formed in the first interlayer insulating film650by etching the first interlayer insulating film650formed on the first source/drain region110a. Continuously, the bit line contact662may be formed by depositing doped silicon in the formed bit line contact hole and performing a CMP process.

A bit line capping layer664may function as a protective film for protecting the bit line660. In some embodiments, the bit line capping layer664may be silicon nitride having an insulating property.

Insulating spacers666are formed on side walls of the bit line660. An insulating film is formed on the first interlayer insulating film650where the bit line660and the bit line capping layer664are formed and an etching process is performed on the insulating film to form the insulating spacers666. The etching process may be a dry etching process, and the insulating spacers666may include oxide or nitride such as silicon nitride.

The second interlayer insulating film652is formed on the first interlayer insulating film650to cover the bit line660. The second interlayer insulating film652may be a tetraethoxysilane (TEOS) oxide film or a high density plasma (HDP) oxide film having high step coverage. InFIG. 6B, the second interlayer insulating film652is formed of a single material layer. In some embodiments, the second interlayer insulating film652may be formed of a plurality of layers.

The first storage contact672aand the second storage contact672bconnect the second source/drain region110bformed in each of the plurality of active regions110to the first storage electrode670aand the second storage electrode670b, respectively. The first storage contact672aand the second storage contact672bmay be formed of, for example, polysilicon (Poly-Si).

In some embodiments, the first storage contact672aand the second storage contact672bmay be formed by etching the second interlayer insulating film652in a position where the first storage electrode670aand the second storage electrode670bare to be formed. Specifically, a mask pattern for defining a position in which the first storage electrode670aand the second storage electrode670bare to be formed is formed on the second interlayer insulating film652by a photolithography technology and the first interlayer insulating film650and the second interlayer insulating film652are removed by using the mask pattern as an etching mask to form a storage contact hole. An etching process for forming the storage contact hole may be performed while continuously or discontinuously changing an etching condition such as wet etching or dry etching. Continuously, after the remaining mask pattern is removed by common strip and ashing processes and the storage contact hole is washed, the first storage contact672aand the second storage contact672bare formed.

The first storage electrode670aand the second storage electrode670bare connected to the second source/drain region110bformed in each of the plurality of active regions110through the first storage contact672aand the second storage contact672b, respectively. The first storage electrode670aand the second storage electrode670bmay be formed of a material such as Ti, TiN, TaN, platinum (Pt), W, Poly-Si, and silicon germanium (SiGe).

In some embodiments, the first storage electrode670aand the second storage electrode670bmay be cylinder-shaped. The first storage electrode670aand the second storage electrode670bmay be also pillar-shaped without being limited thereto.

FIG. 7Ais a plan view illustrating a partial structure of a semiconductor device700according to embodiments of the inventive concept.FIG. 7Bis a cross-sectional view taken along line B7-B7′ ofFIG. 7A.FIG. 7Cis a cross-sectional view taken along line C7-C7′ ofFIG. 7A. InFIGS. 7A to 7C, the same reference numerals as those ofFIGS. 1A to 6Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIGS. 7A to 7C, the semiconductor device700includes an isolation film120for defining a plurality of active regions110in a semiconductor substrate101, a plurality of word lines130, a positive fixed charge containing layer340, a first interlayer insulating film650, a second interlayer insulating film652, a bit line660, a bit line contact662, a first storage electrode670a, a second storage electrode670b, a first storage contact672a, and a second storage contact672b.

The semiconductor device700may be, for example, a part of a cell array region of a semiconductor memory device.

Each of the plurality of active regions110includes an upper surface having a long axis in a first direction (the X direction ofFIG. 7A) and a short axis in a second direction (the Y direction ofFIG. 7A). The plurality of active regions110are repeatedly and separately formed in the first direction (the X direction ofFIG. 7A) and the second direction (the Y direction ofFIG. 7A).

In operation of the semiconductor device700, the positive fixed charge containing layer340may function as the gate dielectric film132.

The positive fixed charge containing layer340covers side and lower surfaces of the plurality of word lines130. In some embodiments, the positive fixed charge containing layer340continuously extends along the plurality of word lines130.

FIGS. 8A to 8Eare cross-sectional views illustrating methods of manufacturing semiconductor devices, according to embodiments of the inventive concept in the order.FIGS. 8A to 8Eillustrate cross-sectional structures of portions corresponding to the cross-section taken along line B1-B1′ ofFIG. 1A. InFIGS. 8A to 8E, the same reference numerals as those ofFIGS. 1A to 1Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 8A, the isolation film120is formed in the trench120H of the semiconductor substrate101. A void V may be formed in the upper surface of the isolation film120. The isolation film120may be formed of, for example, silicon oxide.

In some embodiments, a process of forming the isolation film120may be performed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Specifically, in CVD, the isolation film120may be formed by thermal CVD of generating vapor of a compound by thermal energy, plasma CVD of decomposing a reaction gas by plasma, and photo-induced CVD of decomposing raw material gas molecules by optical energy from a light source, such as laser light. In the PVD of accumulating generated vapor to grow the isolation film120, the isolation film120may be formed by vacuum deposition, sputtering, and ion plating.

Referring toFIG. 8B, the void V formed in the upper surface of the isolation film120is enlarged to a predetermined size to form an enlarged void V′. In some embodiments, the void V is enlarged by an etching process. Here, the etching process may be a wet etching process or a dry etching process.

Referring toFIG. 8C, the enlarged void V′ is filled with the positive fixed charge containing layer140. That is, a width and a length of the enlarged void V′ are equal to a width140wand a depth140dof the positive fixed charge containing layer140. In some embodiments, an upper surface140T of the positive fixed charge containing layer140is positioned on the same level as that of the upper surface120T of the isolation film120. In some embodiments, the width140wof the positive fixed charge containing layer140is smaller than the width120wof the isolation film120. The depth140dof the positive fixed charge containing layer140is smaller than a depth120dof the isolation film120.

Referring toFIG. 8D, the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120are formed.

In some embodiments, a width130wof each of the plurality of trenches130H is smaller than the width140wof the positive fixed charge containing layer140. A depth130dof each of the plurality of trenches130H is larger than the depth140dof the positive fixed charge containing layer140.

The gate dielectric film132is formed in the plurality of trenches130H. A process of forming the gate dielectric film132may be performed by CVD such as thermal CVD of generating vapor of a compound by thermal energy, plasma CVD of decomposing a reaction gas by plasma, and photo-induced CVD of decomposing raw material gas molecules by optical energy from a light source, such as laser light, or PVD such as vacuum deposition, sputtering, and ion plating.

In some embodiments, a thickness of the gate dielectric film132may be no less than 2 nm. In some embodiments, the gate dielectric film132may be a silicon oxide (SiO2) film. The gate dielectric film132may be formed of various materials such as a hafnium oxide (HfO2) film and a lanthanum oxide (La2O3) film.

Referring toFIG. 8E, the plurality of word lines130are formed on the gate dielectric film132. As described above, the plurality of word lines130are positioned on a lower level relative to the upper surfaces110T of the plurality of active regions110or the upper surface120T of the isolation film120(refer toFIG. 1B). The gate capping layer134covers the plurality of word lines130.

FIGS. 9A to 9Care cross-sectional views illustrating methods of manufacturing a semiconductor device, according to embodiments of the inventive concept.FIGS. 9A to 9Cillustrate cross-sectional structures of portions corresponding to the cross-section taken along line B1-B1′ ofFIG. 1A. InFIGS. 9A to 9C, the same reference numerals as those ofFIGS. 1A to 1Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 9A, the isolation film120is formed in the trench120H of the semiconductor substrate101. A void V may be formed in the upper surface of the isolation film120. The isolation film120may be formed by a deposition process. The deposition process may be similar to the process described with reference toFIG. 8A.

Referring toFIG. 9B, a positive fixed charge containing layer940is formed by a nitrogen ion implantation process. In some embodiments, the positive fixed charge containing layer940may be formed by a plasma nitrification process. Here, the plasma nitrification process refers to a process of implanting nitrogen atoms into silicon by using plasma. In some embodiments, the positive fixed charge containing layer940may be formed by performing the plasma nitrification process on the void V formed in the isolation film120with a predetermined slope.

In some embodiments, a width940wof the positive fixed charge containing layer940is smaller than the width120wof the isolation film120. A depth940dof the positive fixed charge containing layer940is smaller than the depth120dof the isolation film120.

Referring toFIG. 9C, the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120are formed, and the gate dielectric film132is formed in the plurality of trenches130H. Then, the plurality of word lines130are formed on the gate dielectric film132. As described above, the plurality of word lines130are positioned on a lower level relative to the upper surfaces110T of the plurality of active regions110or the upper surface120T of the isolation film120(refer toFIG. 1B). The gate capping layer134covers the, plurality of word lines130. Such a series of processes may be similar to the processes described with reference toFIGS. 8D and 8E.

In some embodiments, a width130wof each of the plurality of trenches130H is smaller than the width940wof the positive fixed charge containing layer940. A depth130dof each of the plurality of trenches130H is larger than the depth940dof the positive fixed charge containing layer940.

FIGS. 10A to 10Care cross-sectional views illustrating methods of manufacturing a semiconductor device, according to embodiments of the inventive concept.FIGS. 10A to 10Cillustrate cross-sectional structures of portions corresponding to the cross-section taken along line B3-B3′ ofFIG. 3A. InFIGS. 10A to 10C, the same reference numerals as those ofFIGS. 1A to 9Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 10A, the isolation film120is formed in the trench120H of the semiconductor substrate101. The isolation film120may be formed by a similar process to the process described with reference toFIG. 8A.

Referring toFIG. 10B, the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120are formed, and the gate dielectric film132is formed in the plurality of trenches130H. Then, the plurality of word lines130are formed on the gate dielectric film132. The gate capping layer134covers the plurality of word lines130. Such a series of processes may be similar to the processes described with reference toFIGS. 8D and 8E.

Referring toFIG. 10C, a plasma nitrification process of implanting nitrogen atoms into silicon by using plasma is performed on an upper surface of the gate dielectric film132with a predetermined slope to form the positive fixed charge containing layer440. As a result, a part of the gate dielectric film132remains as the gate dielectric film432.

The positive fixed charge containing layer440covers at least parts of the plurality of word lines130. In some embodiments, the positive fixed charge containing layer440covers the side surfaces of the plurality of word lines130and the gate capping layer134. As described with reference toFIG. 4, the positive fixed charge containing layer440may be positioned on a higher level relative to the lower surfaces of the plurality of word lines130. The upper surface440T of the positive fixed charge containing layer440is positioned on the same level as those of the upper surfaces110T of the plurality of active regions110and the upper surface120T of the isolation film120(refer toFIG. 4).

The gate dielectric film432covers parts of the internal walls of the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120. The gate dielectric film432may be interposed between the plurality of word lines130and the plurality of active regions110or between the plurality of word lines130and the isolation film120. In some embodiments, the upper surface T432of the gate dielectric film432may be positioned on a lower level relative to the upper surfaces130T of the plurality of word lines130(refer toFIG. 4).

FIGS. 11A to 11Care cross-sectional views illustrating methods of manufacturing a semiconductor device according to embodiments of the inventive concept.FIGS. 11A to 11Cillustrate cross-sectional structures of portions corresponding to the cross-section taken along line B3-B3′ ofFIG. 3A. InFIGS. 11A to 11C, the same reference numerals as those ofFIGS. 1A to 10Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Referring toFIG. 11A, the isolation film120is formed in the trench120H of the semiconductor substrate101. The isolation film120may be formed by a similar process to the process described with reference toFIG. 8A. Then, the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120are formed, and the gate dielectric film132is formed in the plurality of trenches130H. Such a series of processes may be similar to the processes described with reference toFIG. 8D.

Referring toFIG. 11B, a plasma nitrification process of implanting nitrogen atoms into silicon by using plasma is performed on the gate dielectric film132with a predetermined slope to form the positive fixed charge containing layer340.

As described above, the gate dielectric film132may be formed of silicon oxide. Therefore, the positive fixed charge containing layer340formed by performing the plasma nitrification process on the gate dielectric film132may be formed of silicon oxynitride. That is, in operation of the semiconductor device, the positive fixed charge containing layer340may function as the gate dielectric film132. In some embodiments, the positive fixed charge containing layer340covers parts of the internal walls of the plurality of trenches130H that extend across the plurality of active regions110and the isolation film120.

Referring toFIG. 11C, the plurality of word lines130are formed on the positive fixed charge containing layer340. That is, the positive fixed charge containing layer340may be interposed between the plurality of word lines130and the plurality of active regions110or between the plurality of word lines130and the isolation film120. As described above, the plurality of word lines130are positioned on a lower level relative to the upper surfaces110T of the plurality of active regions110or the upper surface120T of the isolation film120(refer toFIG. 1B). The gate capping layer134covers the plurality of word lines130. Such a series of processes may be similar to the processes described with reference toFIGS. 8D and 8E.

FIG. 12Ais a plan view illustrating a current characteristic of a semiconductor device according to embodiments of the inventive concept.FIGS. 12B and 12Care cross-sectional views taken along line B12-B12′ ofFIG. 12A. InFIGS. 12A to 12C, the same reference numerals as those ofFIGS. 1A to 11Crefer to the same elements and detailed descriptions of the elements will not be repeated here.

Description is made based on an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS) transistor with reference toFIGS. 12A to 12C. However, similar description may be made based on a p-channel (MOSFET) (PMOS) transistor.

Referring toFIGS. 12A and 12B, a first portion130ppositioned between a pair of active regions110padjacent in a first direction among a plurality of word lines130is surrounded by an isolation film120and a positive fixed charge containing layer140.

In the case where the positive fixed charge containing layer140is not formed, when an operating voltage is applied to the first portion130ppositioned between the pair of active regions110padjacent in the first direction among the plurality of word lines130, an escape wall of electrons filled in a second source/drain region110bis not high. Therefore, in operation of the semiconductor device without the positive fixed charge containing layer140, undesired movement of the electrons may occur.

In the semiconductor device according to the inventive concept, the first portion130ppositioned between the pair of active regions110padjacent in the first direction among the plurality of word lines130is surrounded by the isolation film120and the positive fixed charge containing layer140. Therefore, positive charges formed in the positive fixed charge containing layer140maintain the escape wall of the electrons filled in the second source/drain region110bhigh when the operating voltage is applied to the first portion130ppositioned between the pair of active regions110padjacent in the first direction among the plurality of word lines130. That is, it is possible to prevent the electrons filled in the second source/drain region110bfrom undesirably moving in the operation of the semiconductor device.

Referring to FIGS,12A to12C, when the operating voltage is applied to word lines130apositioned in a plurality of active regions110among the plurality of word lines130, current flows from a first source/drain region110ato the second source/drain region110b. That is, the electrons filled in the second source/drain region110bmove to the first source/drain region110a. When positive charges exist in the isolation film120between a pair of active regions110zadjacent in a second direction among the plurality of active regions110, an energy wall, over which the electrons filled in the second source/drain region110bare injected into another second source/drain region110badjacent to the second source/drain region110bwith the first source/drain region110ainterposed, is lowered so that a current characteristic of the semiconductor device may deteriorate. In the semiconductor device according to the inventive concept, since the positive charges do not exist in the isolation film120between the pair of active regions110zadjacent in the second direction among the plurality of active regions110, it is possible to prevent the energy wall, over which the electrons filled in the second source/drain region110bare injected into another second source/drain region110badjacent to the second source/drain region110bwith the first source/drain region110ainterposed, from being lowered. That is, the current characteristic of the semiconductor device may be improved.

FIG. 13is a plan view of a memory module1000including a semiconductor device according to the inventive concept.

The memory module1000may include a printed circuit board (PCB)1100and a plurality of semiconductor packages1200.

The plurality of semiconductor packages1200may include any of the semiconductor devices100,200,300,400,500,600, and700according to the embodiments of the inventive concept. In particular, the plurality of semiconductor packages1200may include a distinctive structure of at least one semiconductor device selected from the above-described semiconductor devices according to the embodiments of the inventive concept.

The memory module1000according to the inventive concept may be a single in-lined memory module (SIMM), in which the plurality of semiconductor packages1200are mounted only on one surface of the PCB1100or a dual in-lined memory module (DIMM), in which the plurality of semiconductor packages1200are arranged on both surfaces of the PCB1100. In addition, the memory module1000according to the inventive concept may be a fully buffered DIMM (FBDIMM) having an advanced memory buffer (AMB) for providing external signals to the plurality of semiconductor packages1200, respectively.

FIG. 14is a block diagram of a memory card2000including a semiconductor device according to the inventive concept.

The memory card2000may be arranged so that a controller2100and a memory2200exchange electrical signals. For example, when the controller2100issues a command, the memory2200may transmit data.

The memory2200may include any of the semiconductor devices100,200,300,400,500,600, and700according to the embodiments of the inventive concept. In particular, the memory2200may include a distinctive structure of at least one semiconductor device selected from the above-described semiconductor devices according to the embodiments of the inventive concept.

The memory card2000may form various kinds of memory cards such as a memory stick card, a smart media card (SM), a secure digital card (SD), a mini-secure digital card (mini-SD), and a multimedia card (MMC).

FIG. 15is a schematic diagram of a system3000including a semiconductor device according to the inventive concept.

In the system3000, a processor3100, a memory3200, and an input/output apparatus3300may perform data communications via a bus3400.

The memory3200of the system3000may include random access memory (RAM) and read only memory (ROM). In addition, the system3000may include a peripheral apparatus3500such as a floppy disk drive and a compact disk (CD) ROM drive.

The memory3200may include any of the semiconductor devices100,200,300,400,500,600, and700according to the embodiments of the inventive concept. In particular, the memory3200may include a distinctive structure of at least one semiconductor device selected from the above-described semiconductor devices according to the embodiments of the inventive concept.

The memory3200may store code and data for operation of the processor3100.

The system3000may be used for a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.