Apparatus and method for calculation of divisions and square roots

Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i−2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i−1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i−2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

This application relies for priority upon Korean Patent Application Serial No. 2001-72685, filed on Nov. 21, 2001, the contents of which are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention is in the field of data processing and, more specifically, relates to an apparatus and method for executing division and square rooting operations at high speed.

BACKGROUND OF THE INVENTION

With a recent rapid growth in computer application environments that require complex mathematical computations, such as graphic rendering, computer-aided design (CAD), or digital signal processing (DSP), almost all high performance microprocessors may be required to support operations of floating-point addition, multiplication, division, square rooting, etc., on the basis of the IEEE 754-1985 floating-point standard.

In a typical data processing system, the division and square rooting operations may more infrequently happen than addition or multiplication. However, while addition or multiplication may require about 3 cycles of latency, the division and square rooting operations each may require more than 20 cycles of latency, which will considerably affect overall performance of a system at least from a latency point of view.

The most common division process is the SRT division process. The SRT is an acronym for Sweeney, Robertson, and Tocher, who proposed processs similarly characterized to those at the same period. The SRT division process enhances the operation speed of non-restoring division by admitting zero (0), as a quotient digit, with which there is no need of conducting addition/subtraction. The principle of the SRT division process can be applied to a square rooting operation. The structure of the SRT process is disclosed in detail in “Computer Arithmetic Algorithms and Hardware Design” of Oxford university Press 2000 by Behrooz Parhami.

It is easy to implement the traditional radix-2 SRT process in a hardware structure, but a lot of iterations are necessary to obtain quotient/square-roots. To the contrary, the radix-4 SRT process is difficult to reduce to a hardware structure and has a longer delay time for each iterative operation, while it reduces the number of iterations to a half of the radix-2. U.S. Pat. No. 5,258,944 discloses a way of referring a lookup table to select a quotient at each iterative step by means of the radix-4 SRT process.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide an apparatus and method for executing fast operations of division and square rooting by means of a radix-2 arithmetic process.

The invention provides novel arithmetic processes of non-restoring radix-2 division and/or square rooting operations, which are kinds of modified radix-2 SRT processes and utilize the same quotient/root digit set {−1, 0, +1} as the conventional radix-2 SRT procedures. In particular, a novel quotient/root prediction table (QRT/RPT) is used for the modified radix-2 SRT process according to the present invention. By means of the quotient/root prediction table, the i'th quotient/root digit is determined with reference to the i'th partial remainder obtained from the (i−2)'th partial remainder. The present procedures generate the (i−1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i−2)'th correction term, and skip an iterative operation to obtain the i'th partial remainder.

The present radix-2 arithmetic processes reduce the time of iterative operations by a half of the conventional ones, without lengthening a delay time of each iterative operation.

In accordance with the invention, an apparatus for generating a quotient by dividing a dividend with a divisor is provided. The apparatus includes a first correction term generator for creating a first correction term and a second correction term generator for creating a second correction term. A first subtractor deducts the first correction term from a left-shifted value of an (i−2)'th partial remainder. A second subtractor deducts the second correction term from the left-shifted value of the (i−2)'th partial remainder. A carry propagation detector determines whether there is a borrow while calculating an (i−1)'th partial remainder. Quotient digit prediction means predicts an i'th quotient digit in response to an (i−1)'th quotient digit, the (i−2)'th partial remainder, and an output of the carry propagation detector. Selection means selects an alternative one of outputs of the first and second subtractors as an i'th partial remainder in response to the i'th quotient digit.

In another aspect, the invention is directed to an apparatus for providing a square root of a radicand by an iterative operation. The apparatus includes a root digit selector for selecting an (i−1)'th root digit from an (i−2)'th partial remainder. A first correction term generator creates a first correction term by means of an (i−2)'th partial square root and the (i−1)'th root digit. A second correction term generator creates a second correction term by means of an (i−1)'th partial square root. A third correction term generator creates a third correction term by means of the (i−1)'th partial square root. A first subtractor deducts the first and second correction terms from a left-shifted value of an (i−2)'th partial remainder. A second subtractor deducts the first and second correction terms from the left-shifted value of the (i−2)'th partial remainder. A carry propagation detector determines whether there is a borrow or a carry-in while calculating (i−1)'th partial remainder. Root digit prediction means predicts an i'th root digit in response to an (i−1)'th root digit, the (i−2)'th partial remainder, and an output of the carry propagation detector. Selection means selects an alternative one of outputs of the first and second subtractors as an i'th partial remainder in response to the i'th root digit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Now, a preferred embodiment of the invention will be described in conjunction with theFIG. 1.

I. Radix-2 Division Process Using Quotient Prediction Table (QPT)

The following is a notation for a floating point binary division process;

The expression of the remainder x, z−(d*q), is derived from the basic divisional equation z=(d*q)+x. The division process obtains quotient digits in sequence by means of partial remainders (PR).

The recurrence relation for the radix-2 division is summarized in the Equation 1 as follows:
x(i)=2x(i−1)−q−i*dEquation 1

In the Equation 1, x(i)is the i'th partial remainder, x(i−1)is the (i−1)'th partial remainder, q−1is the i'th quotient digit, d is a divisor, and q−i*d is the i'th correction term. From the Equation 1, the initiative partial remainder is x(0)=z, q−i∈{−1, 0, +1}.

Equation 1 may be reformed with the (i−2)'th partial remainder x(i−2), as follows;
x(i)=4x(i−2)−(2q−(i−1)+q−i)*dEquation 2

According to Equation 2, the i'th partial remainder x(i)results from the (i−1)'th quotient digit q−(i−1) and the divisor d. Therefore, Equation 2 shows that it is omissible for the (i−1)'th iterative operation, which is to obtain the (i−1)'th partial remainder x(i−1)necessary for deciding the i'th quotient digit q−i, if the i'th quotient digit q−isubordinate to the (i−1)'th quotient digit q−(i−1)is settled therein.

With the present radix-2 division process employing the quotient digit set {−1. 0, +1}, the i'th quotient digit q−inecessary for obtaining the i'th partial remainder x(i)is established as follows by the level-shifted value 2x(i−1)of the (i−1)'th partial remainder x(i−1);

After defining the (i−1)'th quotient digit q−(i−1), the i'th quotient digit q−iis correctly predicted with reference to the q−(i−1)without executing an iterative operation for the (i−1)'th partial remainder x(i−1). The prediction of the i'th quotient digit q−iuses a quotient prediction table (QPT). When a correction term of the (i−1)'th iteration is generated to calculate the (i−1)'th partial remainder x(i−1), the (i−2)'th correction term occurs simultaneously with the (i−1)'th correction terms for q−i=+1 and for q−i=−1. With the (i−2)'th correction term and the (i−1)'th correction terms for q−i=+1 and for q−i=−1, two conditional partial remainders, x1 and x2, are established, and then one of the conditional partial remainders is selected as x(i)in accordance with the i'th predicted quotient digit q−i.

Next, described will be a procedure of predicting the i'th quotient digit q−1.

To predict quotient digits, the divisor d=0.1d−2d−3d−4. is considered.

As same as the former case of d−2=1, it is understood that the value of q−iis predictable with reference to q−(i−1)obtained from each condition.

From the results, it is possible to make up quotient prediction tables (QPT) for predicting the i'th quotient digit q−ias shown in the following Tables 1 and 2. Table 1 arranges predicted values of the i'th quotient digit q−iin the case of d=0.11d−3d−4(the q−iprediction case 1 : d−2=1), and Table 2 arranges predicted values of the i'th quotient digit q−iin the case of d=0.10d−3d−4(the q−iprediction case 2 : d−2=0).

In Table 1, as the divisor d=0.11d−3d−4. . . when x(i−2)=0.010x−4x5. . . , the (i−1)'th quotient digit q−(i−1)becomes “+1”. If a borrow occurs (borrow=1) at the calculation step for the (i−1)'th partial remainder x(i−1), the i'th quotient digit q−iis set to “−1”. If there is no borrow (borrow=0) at the step for the (i−1)'th partial remainder x(i−1), the i'th quotient digit q−ibecomes “0”.

In Table 2, as the divisor d=0.10d−3d−4. . . when x(i−2)=0.110x−4x−5. . . , the (i−1)'th quotient digit q−(i−1)becomes “0”. If a borrow occurs (borrow=1) at the calculation step for the (i−1)'th partial remainder x(i−1), the i'th quotient digit q−iis set to “−1”. If there is no borrow (borrow=0) at the step for the (i−1)'th partial remainder x(i−1) the i'th quotient digit q−i becomes “0”.

The following Tables 3 and 4 represent division results by the conventional Radix-2 SRT process and the present Radix-2 SRT process, respectively, in the case of the dividend x=0.01000101 and the divisor d=0.1010.

As shown in Table 4, the proposed process calculates the first quotient digit q−1from the initiative partial remainder x(0)in the first iterative operation, and then the quotient prediction table predicts the second quotient digit q−2with reference to the calculated q−1(refer that the conventional one obtains the q−2from the second iterative operation). Thereafter, the quotient digits q−1and q−2are applied to a calculating operation for the first partial remainder x(1). In the second iterative operation, the second quotient digit q−3is obtained from x(1)and then the quotient prediction table defines the fourth quotient digit q−4with reference to the settled q−3(refer that the convention q−4is obtained in the fourth iterative operation). Thereafter, the second partial remainder x(2)is established from the digits q−3and q−4. As a result, since the proposed Radix-2 division process needs not performing the iterative operations for the first and third partial remainders, x(1)and x(3), it shortens the latency by a half of the conventional case. Additionally, the present process completes the whole division operation sooner than the conventional process does because each execution time of the iterative operations is the same with the conventional.

II. Radix-2 Square-Rooting Arithmetic Process Using a Root Prediction Table (RPT)

The following is a notation of the present floating point binary square-rooting process;

The basic equation for the square-rooting operation is z=q2+x. The SRT square-rooting operation process is to obtain the root digits q−1q−2. . . q−nwith the partial remainders.

The following is the circular equation for the Radix-2 square-rooting operation;
x(i)=2x(i−1)−(2q(i−1)+q−i2−i)q−iEquation 3

Equation 3 may be converted into the following form for the (i−2)'th iterative operation;
x(i)=4x(i−2)−2(2q(i−2)+q−(i−1)2−i+1)q−(i−1)−2(2q(i−1)+q−i2−i)q−iEquation 4

In Equation 4, x(i−2)is the (i−2)'th partial remainder, q(i−2)is the (i−2)'th partial square root, and q−(i−1)is the (i−1)'th root digit.

Equation 4 may also be summarized into the following form by substituting the term 2q(i−2)+q−(i−1)2−i+1with C(i−2), and 2q(i−1)+q−i2−iwith C(i−1);
x(i)=4x(i−1)−2C(i−2)q−(i−1)−2C(i−1)q−iEquation 5

The square-rooting operation, as the division operation, selects a root digit by a partial remainder in each iterative operation, and obtains the next partial remainder by generating a correction term.

The proposed Radix-2 square-rooting process, as the present Radix-2 division process aforementioned, uses the set {−1, 0, +1} as a root digit set. The i'th root digit q−iis established by the (i−1)'th partial remainder x(i−1), as follows:

The present process predicts the i'th root digit q−iwith reference to four bits of the (i−2)'th partial remainder x(i−2). Simultaneously with generation of the (i−2)'th correction term C(i−2), the (i−1)'th correction term C(i−1)is generated to calculate the i'th partial remainder. While generating the (i−1)'th correction term C(i−1), correction terms for the case of the i'th root digit q−1=+1 and −1 are preliminarily prepared. Two conditional partial remainders, x1 and x2, are calculated from the (i−1)'th root digit q−(i−1), the i'th root digit q−i, the (i−2)'th correction term C(i−2), and the correction terms for the case of the i'th root digit q−i=+1 and −1. And, one of the conditional partial remainders, x1 or x2, is selected as x(i)in accordance with the i'th root digit q−isettled finally.

Such a process in the proposed Radix-2 square-rooting process makes it possible to skip an iterative operation for the (i−1)'th partial remainder x(i−1). It shortens an iterative operation time by a half of the conventional Radix-2 SRT square-rooting process, and does not lengthen a delay time of each iterative operation, different from the conventional.

The prediction of root digits proceeds according to the following conditions, assuming that the radicand z=z2z1z0.z−1z−2. . . and the partial remainder x(i)=x2x1x0.x−1x−2. . .

The i'th Root Digit Prediction Case 1: z−1=0 and x2=0

The q−(i−1)is always −1 when z−1=0 and x21. Under the initiative condition, it can be understood that the values of the root digits are obtained in the conditions the same with the former q−1prediction case 1: z−1=0 and x2=0.

From the above results, it is possible to make up root prediction tables (RPT) for predicting the i'th root digit q−ias shown in the following Tables 5 and 6. Table 5 shows predicted values of the i'th root digit q−iin the case of the radicand z=z2z1z0.0z−2. . . and the partial remainder x(i)=0x1x0.x−1x−2. . . (the q−1prediction case 1: z−1=0 and x2=0), and Table 6 arranges predicted values of the i'th root digit q−iin the case of the radicand z=z2z1z0.0z−2. . . and the partial remainder x(i)=1x1x0.x−1x−2. . . (the q−iprediction case 2: z−1=0 and x2=1).

In Table 5, the (i−1)'th root digit q−(i−1)becomes “+1” or “−1” when the (i−2)'th partial remainder x(i−2)=000.10x−3x−4. . . When the (i−1)'th root digit q−(i−1)=+1, the i'th root digit q−iis “−1” if a borrow occurs while calculating the (i−1)'th partial remainder x(i−1)(borrow=1). At this time, although there is no borrow while calculating the (i−1)'th partial remainder x(i−1)(borrow=0), the i'th root digit q−iwill also be “−1”. When the (i−2)'th partial remainder x(i−2)=010.11x−3x−4and the (i−1)'th root digit q−(i−1)=−1, the i'th root digit q−iis “0” if a carry-in occurs while calculating the (i−1)'th partial remainder x(i−1)(carry-in =1). At this time, although there is no carry-in while calculating the (i−1)'th partial remainder x(i−1)(carry-in=0), the i'th root digit q−1becomes “−1”.

From Table 6, the (i−1)'th root digit q−(i−1)becomes “+1” or “−1” when the (i−2)'th partial remainder x(i−2)=101.01x−3x−4. . . When the (i−1)'th root digit q−(i−1)=+1, the i'th root digit q−iis “−1” if a borrow occurs while calculating the (i−1)'th partial remainder x(i−1)(borrow=1). If there is no borrow while calculating the (i−1)'th partial remainder x(i−1)(borrow=0), the i'th root digit q−iwill be “0”. When the (i−2)'th partial remainder x(i−2)=110.11x−3x−4and the (i−1)'th root digit q−(i−1)=−1, the i'th root digit q−iis “0” if a carry-in occurs while calculating the (i−1)'th partial remainder x(i−1)(carry-in =1). If there is no carry-in while calculating the (i−1)'th partial remainder x(i−1)(carry-in=0), the i'th root digit q−1becomes “0”.

The following Tables 7 and 8 represent operation results from the conventional Radix-2 SRT square-rooting process and the present Radix-2 SRT square-rooting process, respectively, in the case of the radicand z=01.110110.

The conventional Radix-2 SRT square-rooting arithmetic process, as shown in Table 7, determines each root digit in accordance with the relation with the partial remainders during each iterative operation, and then the settled root digit is put into the calculating process for the next partial remainder. Therefore, the conventional process needs a plurality of iterative operation cycles with the same number of that of the floating-point digits (whole bits+fraction bits).

On the other hand, in the proposed square-rooting arithmetic process, as shown in Table 8, the root digits q0and q−1are obtained from the initiative partial remainder x(0)and the root digit prediction table (RPT) establishes q−2with reference to the q0and q−1(consider that the conventional gets the q−2in the second iterative operation). And then, the first partial remainder x(1)arises from q0, q−1, and q−2. In the second iterative operation, x(1)produces q−3that is referred by the root prediction table RPT to settle q−4(consider that the conventional gets the q−4in the fourth iterative operation). Next, the second partial remainder x(2)is generated by means of the digits q−3and q−4. In the third iterative operation, x(2)produces q−5that is referred by the root prediction table RPT to settle q−6(consider that the conventional gets the q−6in the sixth iterative operation). Next, the second partial remainder x(3)is generated by means of the digits q−5and q−6.

As stated above, the present Radix-2 square-rooting arithmetic process can proceed without executing the iterative operation steps for obtaining the first, the third, and the partial remainders, x(1), x(3), and x(5), in order. Therefore, the latency of the present process downs to a half of the conventional. More considering the processing time of the present is the same with that of the conventional, the square-rooting operation of the invention can be conductive faster than the conventional case.

FIG. 1contains a block diagram of a division/square-rooting arithmetic apparatus1in accordance with an embodiment of the invention. The apparatus includes a controller10, a divisor register12, quotient/root registers14,20, and46, remainder registers16and48, quotient/root digit selector18, multiplexers22,24,36, and44, correction term generators26,28, and30, subtractors32and34, a carry propagation detector38, and quotient/root digit prediction blocks40and42.

The controller10supplies clock signals CLKs and control signals to conduct division and square-rooting operations. The divisor register12stores the divisor d for the division operation. The register14stores the (i−2)'th quotient digit q−(i−2)or the (i−2)'th partial square root q−(i−2)containing the (i−2)'th root digit q−(i−2). The register16stores the (i−2)'th partial remainder x(i−2). The quotient/root digit selector18designates the (i−1)'th quotient digit q−(i−1)by means of the (i−2)'th partial remainder x(i−2). The register20stores the (i−1)'th quotient digit q−(i−1)or the (i−1)'th partial square root q−(i−1)containing the (i−1)'th root digit q−(i−1).

The multiplexer22applies an alternative one of the contents of the divisor register12and the quotient/root register14, i.e., the divisor d and the quotient digit q−(i−2)or the (i−2)'th partial square root q−(i−2)containing the (i−2)'th root digit q−(i−2), to the correction term generator26. The multiplexer24provides an alternative one of the contents of the divisor register12and the quotient/root register20, i.e., the divisor d and the quotient digit q−(i−1)or the (i−1)'th partial square root q−(i−1)containing the (i−1)'th root digit q−(i−1), to the correction term generators28and30. The multiplexers22and24apply the divisor d to the correction term generators26,28, and30from the divisor register12during the division. While, during the square-rooting operation, the multiplexer22applies the (i−2)'th partial square root q−(i−2)to the correction term generator26, and the multiplexer24applies the (i−1)'th partial square root q−(i−1)to the correction term generators28and30.

The correction term generator26creates the (i−2)'th correction term, while the correction term generators28and30create the (i−1)'th correction terms. In particular, the correction term generator28forms the (i−1)'th correction term in the condition of the i'th quotient/root digit q−1=1, while the correction term generator30forms the (i−1)'th correction term in the condition of the i'th quotient/root digit q−1=−1. All the correction term generators26,28, and30make their corresponding correction terms simultaneously. An output of the correction term generator26is applied to both the subtractors32and34, and outputs of the correction term generators28and30are applied to the subtractors32and34, respectively.

The subtractors32and34receive the contents of the register16, i.e., x(i−2). The subtractor32deducts the output of the correction term generator26and/or the output of the correction term generator28from the level-shifted value of the (i−2)'th partial remainder x(i−2), 4x(i−2). Similarly, the subtractor34deducts the output of the correction term generator26and/or the output of the correction term generator30from the level-shifted value of the (i−2)'th partial remainder x(i−2), 4x(i−2). The subtractor32deducts the output of the correction term generator28from the level-shifted value of the (i−2)'th partial remainder x(i−2), 4x(i−2)during the division and deducts the outputs of the correction term generators26and28from the level-shifted value of the (i−2)'th partial emainder x(i−2), 4x(i−2)during the square-rooting. The subtractor34deducts the output of the correction term generator30from the level-shifted value of the (i−2)'th partial remainder x(i−2), 4x(i−2)during the division and deducts the outputs of the correction term generators26and30from the level-shifted value of the (i−2)'th partial remainder x(i−2), 4 x(i−2)during the square-rooting. The outputs from the subtractors32and34are applied to the multiplexer36.

The carry propagation detector38determines whether there is a borrow or a carry-in during the calculation step for the (i−1)'th partial remainder x(i−1)from the (i−2)'th correction term. Techniques for detecting whether a carry at a given bit position has been generated, propagated, or annihilated (or absorbed) are known.

The quotient/root digit prediction block40contains the i'th quotient/root digits when the borrow or the carry-in occurs as shown in Tables 1, 2, 5, and 6 (i.e., borrow/carry-in=1). The quotient/root digit prediction block42contains the i'th quotient/root digits when the borrow or the carry-in does not occur as shown in Tables 1, 2, 5, and 6 (i.e., borrow/carry-in=−1). The quotient/root digit prediction blocks40and42receive the contents of the registers16and20, i.e., x(i−2)and q−(i−1).

The quotient/root digit prediction block40predicts the i'th conditional quotient/root digit q1(i.e., the i'th quotient/root digit in the case of borrow/carry-in=1) corresponding to the content of the register16, i.e., x(i−2), and the content of the register20, i.e., q−(i−1). The quotient/root digit prediction block42predicts the i'th conditional quotient/root digit q2(i.e., the i'th quotient/root digit in the case of borrow/carry-in=0) corresponding to the content of the register16, i.e., x(i−2), and the content of the register20, i.e., q−(i−1).

Outputs of the quotient/root digit prediction blocks40and42, q1and q2, are applied to the multiplexer44. The multiplexer44selects an alternative one of the outputs q1and q2as the i'th quotient/root digit q−iin response to the output of the carry propagation detector38.

The i'th quotient/root digit q−iis stored in the register46, simultaneously being applied to the multiplexer36. The multiplexer36selects an alternative one of the outputs of the subtractors, q1and q2, as the (i−1)'th partial remainder x(i)in response to i'th quotient/root digit q−1, which is stored in the register48.

As described above, the present Radix-2 arithmetic process does not need iterative operation steps for obtaining the (i−1)'th partial remainder because the (i−1)'th correction term necessary to the calculation of the (i−1)'th partial remainder is generated with the (i−2)'th correction term simultaneously. Hence, the overall iterative operation time is reduced to a half of the convention case, and its delay times do not lengthen thereof. Moreover, the proposed arithmetic apparatus shares the correction term generators and the functional blocks for calculating the division and square-rooting operations, rendering a small area overhead for itself.