Semiconductor device passive thermal management

Cubic BAs is used in semiconductors to improve the thermal characteristics of a device. The BAs is used in device layers to improve thermal conductivity. The BAs also provides thermal expansion characteristics that are compatible with other semiconductors and thereby further improves reliability. The substrates of the semiconductors may also include vias that contain BAs. The BAs in the vias may contact the BAs in the device layers. Some vias may have a surface area to volume ratio of greater than 10 to better assist with device heat dissipation.

TECHNICAL FIELD

An embodiment of the present invention relates to the field of semiconductor devices, more particularly, to semiconductor device thermal management.

BACKGROUND

Next generation smaller feature size microelectronic devices (e.g. GaN HEMT on SiC) are expected to operate at hot-spot or junction level power densities >30,000 W/cm2 or 3× that of the sun. Heat dissipation for these devices becomes the overwhelming factor governing their reliability and operational performance. During operation a large portion of the temperature rise occurs in the substrate due to its thermal resistance. Despite the high thermal conductivity of SiC, the thermal resistance of the substrate still limits the performance of power amplifiers. Junction temperature rise and its impact on reliability is the main factor limiting the output power for GaN HEMT devices.

Active thermal management systems such as thermoelectric elements, micro-channel liquid coolants and heat pipes are all being actively investigated for high power density device applications. These active systems are complex, expensive and have low reliability.

SUMMARY

Several embodiments of the present invention provide improved semiconductor thermal management using passive cooling that is less complex, less expensive and more reliable than active thermal management systems. Overall semiconductor device reliability and performance is further improved by, for example, the thermal conductivity of materials used, the arrangement of the materials used and the coefficient of thermal expansion of materials used.

An embodiment of the present invention comprises a semiconductor device with a substrate having a top surface and a bottom surface, a first boron arsenide (BAs) electrically insulating layer, a device buffer layer, and a device channel layer on top of the device buffer layer. The device buffer layer is between the top surface of the substrate and the device channel layer, and the BAs electrically insulating layer is in thermal contact with the device buffer layer and the device channel layer. The BAs layer provides excellent thermal conductivity and may be, for example, a cubic BAs layer.

In another embodiment of the present invention, the BAs electrically insulating layer is in direct contact with the device channel layer.

In yet another embodiment of the present invention, the BAs electrically insulating layer is in direct contact with the device buffer layer and the top surface of the substrate.

In still another embodiment of the present invention, the substrate comprises at least one via through the bottom surface and into the substrate, and the at least one via contains BAs.

In another embodiment of the present invention, the BAs in the at least one via contacts the BAs electrically insulating layer.

In yet another embodiment of the present invention, the bottom surface of the substrate has a BAs electrically insulating layer.

In still another embodiment, the present invention comprises a semiconductor device with a first layer having a first layer conductive contact and being doped at a first concentration of a first dopant type, the first dopant type being one of a P type or a N type dopant, and a second layer on top the first layer and being doped at a second concentration of the first dopant type, the second concentration being less than the first concentration, and a third layer on top of the second layer and having a third layer conductive contact and being doped with a second dopant type, the second dopant type being one of the P type or the N type dopants, and being a different dopant type than the first dopant type, and a fourth layer on top of the third layer and having a fourth layer conductive contact and being doped with the first dopant type, wherein at least one of the first and second layers is a BAs layer. The BAs layers provide excellent thermal conductivity and may be, for example, cubic BAs layers.

In yet another embodiment of the present invention a BAs electrically insulating layer is in contact with the first layer, the second layer, the third layer and the fourth layer.

DETAILED DESCRIPTION

FIG. 1illustrates an embodiment of the present invention involving a Field Effect Transistor (FET). The figure illustrates a cross-section of a FET. FET10is mounted to fixture12. Fixture12may be made of, for example, any machineable low resistance metal such as Kovar, A40, CuW, or even Al or Cu. FET10is mounted to fixture12through die bondline14. Die bondline14may be made of, for example, metal eutectic solders or epoxies. The layer of FET10mounted to die bond line14is substrate16. Substrate16may be made from, for example, semi-insulating materials such as BAs, sapphire, GaAs or InP. Theses substrates are usually single crystal materials grown via traditional crystal growth techniques and polished or grown/deposited as epitaxal films. They may be, for example, pulled from a melt or vapor deposited using seed crystals. Positioned above substrate16is BAs electrically insulating layer18. Layer18may be in direct contact with the top surface of substrate16and may be epitaxially deposited on layer16. Layer18may be grown by, for example, chemical vapor deposition (CVD) or by molecular-beam epitaxy (MBE). Layer18may be cubic BAs. Positioned above and in direct contact with layer18is device buffer layer20. Device buffer layer20may be epitaxially deposited on layer18and may, for example, provide a better lattice match for the device channel layer. Layer20may be formed by, for example, CVD, MBE or liquid phase epitaxy (LPE). Device buffer layer20may be fabricated using for example, a compound semiconductor buffer layer such as InAlAs, InP, AlGaAs, GaN or AlGaN. Device channel layer22is fabricated on top of device buffer layer20. Device channel layer22may be epitaxially deposited on layer20. Layer22may be formed by, for example, CVD, MBE or LPE. Layer22is fabricated with the appropriate P type and N type doping materials to create a P-channel or an N-channel device. Conductive contacts24and28, and electrode26are placed in contact with the appropriate portions of device channel layer22as is well known in the design of FETs. Contacts24and28and electrode26may be made of, for example, titanium, aluminum, chromium, copper or gold.

An example of a hot-spot in FET10is illustrated by hot-spot30. Layer18is in thermal contact with layers16,20and22. The heat from hot-spot30is spread through the high thermal conductivity of layer18. This helps to remove heat from layers22and20, and into substrate16and eventually fixture12to keep FET10cooler and thereby improve reliability and performance.

FIG. 2illustrates an embodiment of the present invention involving a FET. The figure illustrates a cross-section of the FET. FET40is mounted to fixture42through die bondline44. Fixture42and die bondline44are similar to the corresponding structures discussed regardingFIG. 1. In this embodiment, a device buffer layer is not illustrated because in this example, there is a near lattice match between the substrate and device channel layer. If a closer lattice match is desired, a device buffer layer may be used to improve lattice match with the device channel layer. Substrate layer46is mounted on top of die bondline44. Substrate46may be made from, for example, semi-insulating materials such as BAs, sapphire, GaAs or InP. Theses substrates are usually single crystal materials grown via traditional crystal growth techniques and polished or grown/deposited as epitaxal films. They may be, for example, pulled from a melt or vapor deposited using seed crystals. Device channel layer50is fabricated on top of layer46. Device channel layer50may be epitaxially deposited on layer46. Layer50may be formed by, for example, CVD, MBE or LPE. Device channel layer50may be fabricated with the appropriate P type and N type doping materials to create a P-channel or an N-channel device. Electrical contacts52and54are in electrical contact with layer50, and may be made of, for example, titanium, aluminum, chromium, copper or gold. BAs electrically insulating layer56is formed on top of layer50and may be in direct contact with layer50. Layer56may be cubic BAs. Layer56may be formed by, for example, CVD, MBE, or LPE. In addition to acting as a heat spreader, this layer also acts as a device barrier layer. Layer56is in thermal contact with layers50and46. Electrode58is positioned in contact with layer56to affect operation of the FET, and may be made of, for example, titanium, aluminum, chromium, copper or gold.

Hot-spot60illustrates the heat produced by the FET. The heat is spread by layer56and thereby enhances heat dissipation through layers50and46, and eventually to fixture42.

FIG. 3illustrates an embodiment of the present invention involving a FET. The figure illustrates a cross-section of the FET. FET80is mounted to fixture82using die bondline84. Fixture82and die bondline84are similar to the corresponding structures discussed regardingFIG. 1. Substrate86may be mounted on top of die bond line84. Substrate86may be made from, for example, semi-insulating materials such as BAs, sapphire, GaAs or InP. Theses substrates are usually single crystal materials grown via traditional crystal growth techniques and polished or grown/deposited as epitaxal films. They may be, for example, pulled from a melt or vapor deposited using seed crystals. Positioned above substrate86is BAs electrically insulating layer88. Layer88may be in direct contact with the top surface of substrate86and may be epitaxially deposited on layer86. Layer88may be grown by, for example, CVD or MBE. Layer88may be cubic BAs. Positioned above and in direct contact with layer88is device buffer layer90. Device buffer layer90may be epitaxially deposited on layer88. Device buffer layer90may be fabricated using for example, a compound semiconductor buffer layer such as InAlAs, InP, AlGaAs, GaN or AlGaN. Layer90may be formed by, for example, CVD, MBE or LPE. Device channel layer92is fabricated on top of device buffer layer90. Layer92is fabricated with the appropriate P type and N type doping materials to create a P-channel or a N-channel device. Device channel layer92may be epitaxially deposited on layer90. Layer92may be formed by, for example, CVD, MBE or LPE. Conductive contacts94and98, and electrode98are placed in contact with the appropriate portions of device channel layer92as is well known in the design of FETs. Contacts94and98, and electrode96may be made of, for example, titanium, aluminum, chromium, copper or gold.

Substrate layer86includes vias100. Vias100are etched into substrate86from the bottom surface of the substrate and into the substrate. The vias may extend partially into substrate86or they may extend through substrate86in order to contact layer88. Vias100contain BAs. BAs may be cubic BAs. The BAs in vias100may for example, coat the inner surfaces of the vias, partially fill the vias or completely fill the vias. The BAs in the vias may contact the BAs of layer88. It is also possible to coat the bottom surface of substrate86with BAs and to have the BAs on the bottom surface of substrate86contact the BAs in vias100. The BAs on the bottom surface of substrate86may be cubic BAs. Layer88is in thermal contact with layers90and92thereby provides a path for heat dissipation from layers90and92through vias100and eventually to fixture82.

FIG. 4illustrates an embodiment of the present invention involving a FET. The figure illustrates a cross-section of the FET and is similar toFIG. 3. FET110is mounted to fixture112by die bondline114. Substrate layer116of FET110is mounted to die bondline114. Substrate116may be made from, for example, semi-insulating materials such as BAs, sapphire, GaAs or InP. Theses substrates are usually single crystal materials grown via traditional crystal growth techniques and polished or grown/deposited as epitaxal films. They may be, for example, pulled from a melt or vapor deposited using seed crystals. Positioned above substrate116is BAs electrically insulating layer118. Layer118may be in direct contact with the top surface of substrate116and may be epitaxially deposited on layer116. Layer118may be grown by, for example, CVD or MBE. Layer118may be cubic BAs. Positioned above and in direct contact with layer118is device buffer layer120. Device buffer layer120may be epitaxially deposited on layer118. Device buffer layer120may be fabricated using for example, a compound semiconductor buffer layer such as InAlAs, InP, AlGaAs, GaN or AlGaN. Layer120may be formed by, for example, CVD, MBE or LPE. Device channel layer122is fabricated on top of device buffer layer120. Layer122is fabricated with the appropriate P type and N type doping materials to create a P-channel or an N-channel device. Device channel layer122may be epitaxially deposited on layer120. Layer122may be formed by, for example, CVD, MBE or LPE. Electrical contacts124and126are in electrical contact with layer122. These contacts may be made of, for example, titanium, aluminum, chromium, copper or gold. BAs electrically insulating layer128is formed on top of layer122and may be in direct contact with layer122. Layer128may be cubic BAs. In addition to acting as a heat spreader, this layer also acts as a device barrier layer. Layer128is in thermal contact with layers122,120and118. Layer128may be formed by, for example, CVD, MBE, or LPE. Electrode130is positioned in contact with layer128to affect operation of the FET. Electrode130may be made of, for example, titanium, aluminum, chromium, copper or gold.

Substrate layer116includes vias132. Vias132are etched into substrate116from the bottom surface of the substrate and into the substrate. The vias may extend partially into substrate116or they may extend through substrate116in order to contact layer118. Vias132contain BAs. BAs may be cubic BAs. The BAs in vias132may for example, coat the inner surfaces of the vias, partially fill the vias or completely fill the vias. The BAs in the vias may contact the BAs of layer118. It is also possible to coat the bottom surface of substrate116with BAs and to have the BAs on the bottom surface of substrate116contact the BAs in vias132. The BAs coating the bottom surface of substrate116may be cubic BAs. Layer118is in thermal contact with layers120and122thereby provides a path for heat dissipation from layers120and122through vias132and eventually to fixture112.

FIGS. 5A and 5Billustrate examples of semiconductor devices with vias etched in their substrate layers. The semiconductor devices ofFIGS. 5A and 5Bare cross-sections. Device150has via152etched into substrate layer154. In this example, via152and the bottom surface substrate154are coated with BAs or cubic BAs. In this example, the shape of via152is pyramidal.

FIG. 5Billustrates semiconductor device160. Semiconductor device160has via162etched into substrate layer164. In this example, via162and the bottom surface substrate164are coated with BAs or cubic BAs. In this example, the shape of via162is paraboloidal.

It is possible to use a variety of shapes for vias. The coefficient of thermal expansion (CTE) for BAs or cubic BAs closely matches the coefficient of thermal expansion of substrates such as the substrates ofFIGS. 3 and 4, and therefore supports a wide variety of via shapes. The close matching of the coefficient of thermal expansion also permits via shapes with sharper angles.

FIG. 6illustrates a table comparing the CTEs of different materials. The table shows that the CTE of cubic BAs closely matches many materials used in semiconductor fabrication. This close CTE match facilitates using a wider variety of via shapes.

FIGS. 7A-7Billustrate examples of a variety of possible via shapes. The figures illustrate the shapes and the area to volume ratio of the particular shape. Shapes having area to volume ratios of greater than 10 provide good heat transfer. The shapes illustrated inFIG. 7Amay also be modified to use truncated versions, which are illustrated inFIG. 7B. For example, a truncated version ofFIG. 7A's square pyramid180would involve, as depicted inFIG. 7B, flattening apex182. Similarly, a truncated version ofFIG. 7A's tetrahedron184would involve, as depicted inFIG. 7B, flattening apex186.

FIG. 8illustrates an HBT (Heterojunction Bipolar Transistor) cross-section. HBT200is mounted to fixture202using die bondline204. Fixture202may be made of, for example, any machineable low resistance metal such as Kovar, A40, CuW, or even Al or Cu, and die bondline204may be made of, for example, metal eutectic solders or epoxies. In this example, subcollector206may be epitaxially grown from BAs or cubic BAs that is been doped with an N type dopant such as silicon, tellurium or another N type dopant to a concentration that is higher than a concentration used in collector layer208. Layer208may be epitaxially grown from, for example, InP, InGaAs or InAlAs and may be in direct contact with subcollector layer206. Layer208may be doped with an N type dopant such as silicon or tellurium. Base layer210is fabricated on top of collector layer208and may be in direct contact with layer208. Base layer210may be epitaxially grown from, for example, InP, InGaAs or InAlAs, and may be doped with a P type dopant such as beryllium or carbon. Emitter layer212is fabricator on top of base layer210and may be in direct contact with base layer210. Emitter layer212may be epitaxially grown from, for example, InP, InGaAs or InAlAs, and may be doped with an N type dopant such as silicon or tellurium. Collector contact214is electrically connected to subcollector layer206. Base contact216is electrically connected base layer210and emitter contact218is electrically connected to emitter layer212. Contacts214,216and218may be fabricated by, for example, CVD or MBE using, for example, titanium, aluminum, chromium, copper or gold.

Hot-spot220illustrate how heat is spread by subcollector layer206and eventually transferred to fixture202. The thermal conductivity of the BAs or cubic BAs of subcollector layer206enhances thermal management and thereby improves reliability of device200.

It should be noted that the example ofFIG. 8was discussed with regard to a NPN transistor, but an embodiment of the present invention also applies to PNP transistors. For example, in the case of an PNP transistor, subcollector206is fabricated from BAs or cubic BAs that is been doped with a P type dopant such as beryllium, carbon, magnesium or another P type dopant to a concentration that is higher than a concentration used in collector layer208. In this example, layer208may be fabricated from, for example, InP, InGaAs or InAlAs. Layer208may be doped with a P type dopant such as beryllium or carbon. Base layer210may be fabricated from, for example, InP, InGaAs or InAlAs and may be doped with an N type dopant such as silicon or tellurium. Emitter layer212may be fabricated from, for example, InP, InGaAs or InAlAs, and may be doped with a P type dopant such as beryllium or carbon.

In the above disclosed examples ofFIG. 8, the non-BAs layers were fabricated from doped InP, InGaAs or InAlAs. In additional embodiments of the examples ofFIG. 8, the non-BAs layers may be fabricated from doped GaAs, AlGaAs or InGaP.

FIG. 9illustrates an HBT cross-section. HBT240dismounted to fixture242using die bondline244. Fixture242may be made of, for example, any machineable low resistance metal such as Kovar, A40, CuW, or even Al or Cu, and die bondline244may be made of, for example, metal eutectic solders or epoxies. In this example, subcollector layer246may be epitaxially grown from, for example, InP, InGaAs or InAlAs that is doped with an N type dopant such as silicon or tellurium to a concentration that is higher than a concentration used in collector layer248. Layer248may be epitaxially grown from BAs or cubic BAs that is doped with an N type dopant such as silicon, tellurium or another N type dopant and may be in direct contact with subcollector layer246. Base layer250as fabricated on top of collector layer248and may be in direct contact with layer248. Base layer250may be epitaxially grown from, for example, InP, InGaAs or InAlAs that is doped with a P type dopant such as carbon or beryllium. Emitter layer252is fabricated on top of base layer250and may be in direct contact with base layer250. Emitter layer252may be epitaxially grown from, for example, InP, InGaAs or InAlAs that is doped with an N type dopant such as silicon or tellurium. Collector contact254is electrically connected to subcollector layer246. Base contact256is electrically connected base layer250and emitter contact258is electrically connected to emitter layer252. Contacts254,256and258may be fabricated by, for example, CVD or MBE using, for example, titanium, aluminum, chromium, copper or gold.

Hot-spot260illustrates how heat is spread by collector layer248and eventually transferred the fixture242. The thermal conductivity of the BAs of collector layer248enhances thermal management and thereby improves reliability of device240.

It should be noted that the example ofFIG. 9was discussed with regard to a NPN transistor, but an embodiment of the present invention also applies to PNP transistors. For example, in the case of an PNP transistor, collector layer248may be fabricated from BAs or cubic BAs that is doped with a P type dopant such as carbon, beryllium, magnesium or another P type dopant to a concentration that is lower than a concentration used in subcollector layer246. In this example, layer246may be fabricated from, for example, InP, InGaAs or InAlAs. and is doped with a P type dopant such as carbon or beryllium. Base layer250may be fabricated from, for example, InP, InGaAs or InAlAs that is doped with an N type dopant such as silicon or tellurium. Emitter layer252may be fabricated from, for example, InP, InGaAs or InAlAs that is doped with a P type dopant such as carbon or beryllium.

In the above disclosed examples ofFIG. 9, the non-BAs layers were fabricated from doped InP, InGaAs or InAlAs. In additional embodiments of the examples ofFIG. 9, the non-BAs layers may be fabricated from doped GaAs, AlGaAs or InGaP.

FIG. 10illustrates an HBT cross-section. HBT280is mounted to fixture282using die bondline284. Fixture282may be made of, for example, any machineable low resistance metal such as Kovar, A40, CuW, or even Al or Cu, and die bondline284may be made of, for example, metal eutectic solders or epoxies. In this example, subcollector286may be epitaxially grown from BAs or cubic BAs that is doped with an N type dopant such as silicon, tellurium or another N type dopant to a concentration that is higher than a concentration used in collector layer288. Layer288may be epitaxially grown from BAs or cubic BAs that is doped with an N type dopant such as silicon, tellurium or another N type dopant and may be in direct contact with subcollector layer286. Base layer290may be epitaxially grown on top of collector layer288and may be in direct contact with layer288. Base layer290may be fabricated from, for example, InP, InGaAs or InAlAs that is doped with a P type dopant such as carbon or beryllium. Emitter layer292is fabricated on top of base layer290and may be in direct contact with base layer290. Emitter layer292may be epitaxially grown from, for example, InP, InGaAs or InAlAs that is doped with an N type dopant such as silicon or tellurium. Collector contact294is electrically connected to subcollector layer286. Base contact296is electrically connected base layer290and emitter contact298is electrically connected to emitter layer292. Contacts294,296and298may be fabricated by, for example, CVD or MBE using, for example, titanium, aluminum, chromium, copper or gold.

It should be noted that the example ofFIG. 10was discussed with regard to a NPN transistor, but an embodiment of the present invention also applies to PNP transistors. For example, in the case of an PNP transistor, collector layer288may be fabricated from BAs or cubic BAs that is doped with a P type dopant such as carbon, beryllium, magnesium or another P type dopant to a concentration that is lower than the concentration of the P type dopant used in the BAs or cubic BAs of subcollector layer286. The P type dopant used in subcollector layer286may be, for example, carbon, beryllium, magnesium or another P type dopant. In this example, base layer250may be fabricated from, for example, InP, InGaAs or InAlAs that is doped with an N type dopant such as silicon or tellurium. Emitter layer252may be fabricate from, for example, InP, InGaAs or InAlAs that is doped with a P type dopant such as carbon or beryllium.

In the above disclosed examples ofFIG. 10, the non-BAs layers were fabricated from doped InP, InGaAs or InAlAs. In additional embodiments of the examples ofFIG. 10, the non-BAs layers may be fabricated from doped GaAs, AlGaAs or InGaP.

FIG. 11illustrates the example ofFIG. 10with BAs or cubic BAs barrier layer300added. BAs layer300is an electrically insulating layer. It is in contact with the subcollector layer, the collector layer, the base layer and emitter layer. Layer300helps to dissipate heat as well as protect the other layers of the semiconductor device. In further embodiments of the present invention, this layer may be applied, for example, to the devices ofFIGS. 8 and 9as well.

FIG. 12illustrates an example of a top view of the HBT ofFIG. 10. Subcollector layer286is below collector layer288, and collector layer288is below base layer290. Base layer290is below emitter layer292. Collector contact294is electrically connected to subcollector layer286. Base contact296is electrically connected to base layer290. Emitter contact298is electrically connected to emitter layer292, which is positioned below contact298and above base layer290.

The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only and not as a limitation. The actual scope of the invention is intended to be defined in the following claims when viewed in their proper perspective based on the prior art.