Control system with delayed protection for a three-level inverter

A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

TECHNICAL BACKGROUND

Three-level inverter topology has become increasingly popular in high power applications, such as uninterruptible power supplies (UPS) and solar inverters. By increasing the bus voltage within these devices to 1000V or 1500V DC, the current is reduced while maintaining the same power levels, which significantly reduces the power loss with less copper design. Also, three-level inverter topology makes it possible to use the same switching device to support much higher voltage stress than traditional two-level inverters.FIG.1illustrates a typical single-phase three-level I-type inverter, called a neutral point clamped (NPC) inverter. In many embodiments, three of these single-phase inverters are used to generate a three-phase alternating current (AC) output.

This example single-phase NPC inverter module100includes four power switches, Q1111, Q2112, Q3113, and Q4114, such as Insulated-Gate Bipolar Transistors (IGBTs), in series. First switch Q1111and fourth switch Q4114are called outer switches, and second switch Q2112and third switch Q3113are called inner switches. Power switches Q1111, Q2,112, Q3113, and Q4114are controlled by signals S1151, S2152, S3153, and S4154respectively. The DC link is split in two symmetric halves connected in series.

Inverter module100also includes bus voltage supply105providing a voltage of VIN to the inverter. Protective diodes D1121, D2122, D3123, and D4124are provided across power switches Q1-Q4111-114respectively. Neutral point input N is received at node101, while output AC is provided at node102. Inverter module100further includes capacitors C1131and C2132, along with diodes D5125and D6126, which provide filtering.

During normal operation Q1111switches opposite to Q3113, while Q2112switches opposite to Q4114. There is an interlock with deadtime between Q1111and Q3113, as well as between Q2112and Q4114, preventing a shoot-through condition. Q1111and Q4114are not allowed to be activated simultaneously.

During normal operation while providing AC power and coupled to a power grid, the switching states of the power switches Q1-Q4111-114are illustrated below in Table 1.

As illustrated in Table 1, during the positive portion of the AC cycle, Q1111and Q3113are alternatively switching, while Q2112remains on and Q4114remains off. During the negative portion of the AC cycle, Q2112and Q4114are alternatively switching, while Q1111remains off and Q3113remains on.

Compared to a traditional two-level inverter, three-level inverters require more complicated power conversion control (as illustrated by Table 1), and also require more complicated fault protection logic. Events such as over current, over voltage, short circuit, thermal overload, and the like, trigger rapid shut downs of the three-level inverter in order to protect the power switches and the system or grid itself.

In two-level inverters, during shut down, all of the power switches are switched off immediately and simultaneously. However, three-level inverters require a specific shut down and recovery sequence for protection of the power switches and other circuitry. In three-level inverters, during shut down, outer switches Q1111and Q4114must be shut off before inner switches Q2112and Q3113, which are shut off after a specific delay. Typically, outer switches Q1111and Q4114are immediately shut off when a fault or trip event is detected. Then, after a specific delay, during a positive portion of the AC cycle Q2112is shut down, or during a negative portion of the AC cycle Q3113is shut down.

During the recovery process, inner switches Q2112and Q3113must be activated before outer switches Q1111and Q4114in order to prevent energy stored in inductor L1141from causing a large voltage overshoot and potentially damaging the power switches.

This delayed protection requirement of three-level inverters has been a challenge for designers of UPS and solar energy systems. Software methods include excessive delay and therefore are unable to provide real-time protection. Current hardware methods include the use of external hardware circuits, such as Field-Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and the like to provide the required shut off and recovery sequences. An example prior art hardware method is illustrated inFIG.2and described in detail below. However, these designs increase system cost and development effort.

OVERVIEW

In an implementation, a microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of Enhanced Pulse Width Modulation (EPWM) modules, each configured to control a power switch within the three-level inverter.

The microcontroller unit also includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module.

The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

In another implementation, a method for controlling a three-level inverter including delayed fault protection with a microcontroller unit is provided. The method includes receiving a trip signal from a fault detection module at an input port within the microcontroller unit, and controlling a plurality of power switches within the three-level inverter via a plurality of Enhanced Pulse Width Modulation (EPWM) modules within the microcontroller unit, each configured to control one of the power switches within the three-level inverter.

The method also includes producing a delayed trip signal from the trip signal via an auxiliary EPWM module within the microcontroller unit, and in response to activation of the trip signal, directing one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and directing a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

DETAILED DESCRIPTION

FIG.1illustrates an example embodiment of a single-phase three-level I-type inverter module100and was described in detail above. Note that whileFIG.1illustrates a single-phase three-level I-Type inverter, called a neutral point clamped (NPC) inverter, other embodiments use any of a wide variety of three-level inverter designs and configurations, all within the scope of the present invention.

FIG.2illustrates an example embodiment of a prior art hardware system200for providing shut off and recovery sequences to a three-level inverter module100. In this example embodiment, a three-level inverter module100such as inverter module100fromFIG.1is controlled by microcontroller unit (MCU)230and provides an AC output201. Gate Driver210provides power switch control signals S1-S4205to inverter module100. microcontroller unit (MCU)230provides Enhanced Pulse Width Modulation (EPWM) signals203to CPLD/FPGA220, which modifies the EPWM signals203to include the necessary sequencing of the shut down and restoration of inverter module100when a fault is detected. The modified EPWM signals204are provided to gate driver210.

Fault detection module240monitors AC output201to detect faults such as over current, over voltage, short circuit, thermal overload, and the like. When a fault is detected, fault detection module provides trip or fault signal202to CPLD/FPGA220which then modifies the EPWM signals203to include the necessary sequencing of the shut down and restoration of inverter module100. In addition to the cost of the CPLD/FPGA, the CPLD/FPGA requires VHDL (VHSIC (Very High-Speed Integrated Circuits) Hardware Description Language) or Verilog to configure its logic primitives. This in turn requires additional software development efforts and resources to create and maintain the additional coding.

FIG.3illustrates an example embodiment of a system300for providing shut down and recovery sequences to a three-level inverter module. In this example embodiment of the present invention, MCU330is configured to respond to a trip or fault signal302by modifying its EPWM signals to include the necessary sequencing of the shut down and restoration of inverter module100when a fault is detected. One example configuration of MCU330including this protection is illustrated inFIG.4and described in detail below.

In this example embodiment, a three-level inverter module100such as inverter module100fromFIG.1is controlled by microcontroller unit (MCU)330and provides an AC output voltage301. Gate driver310provides power switch control signals S1-S4304to inverter module100. microcontroller unit (MCU)330provides Enhanced Pulse Width Modulation (EPWM) signals303to gate driver310.

Fault detection module340monitors AC output301to detect faults such as over current, over voltage, short circuit, thermal overload, and the like. When a fault is detected, fault detection module provides trip signal302to MCU330which then modifies the EPWM signals303to include the necessary sequencing for the shut down and restoration of inverter module100.

FIG.4illustrates an example embodiment of a microcontroller unit400configured to provide shut down and recovery sequences to a three-level inverter module100. In this example embodiment of the present invention, a MCU400such as MCU330fromFIG.3is configured to provide the necessary sequencing of the shut down and restoration of three-level inverters, such as inverter module100fromFIG.1. In one example embodiment, MCU400comprises a C2000™ series microcontroller unit from Texas Instruments Inc. Other embodiments use other microcontroller units all within the scope of the present invention.

In this example, MCU400includes multiple Type 4 Enhanced Pulse Width Modulator (EPWM) modules including EPWM1A420, EPWM1B426, EPWM2A430, EPWM2B436, EPWM7404, and EPWM7A406. EPWM1A420and EPWM1B426are channels within EPWM module EPWM1. EPWM2A430and EPWM2B436are channels within EPWM module EPWM2. Each EPWM module includes a time-base counter triggered by a clock signal, and each EPWM module is configurable to generate different outputs according to desired events. For example, when the time-base counter equals the value within a counter-comparator register.

EPWM modules EPWM1A420, EPWM1B426, EPWM2A430, and EPWM2B436produce four pulse width modulated signals that are provided to a gate driver such as gate driver310fromFIG.3, which in turn provides signals S1-S4304to drive the four power switches within inverter module100. In this example embodiment, EPWM1A420produces a signal which is used to control power switch Q1111within inverter module100, EPWM1B426produces a signal which is used to control power switch Q3113within inverter module100, EPWM2A430produces a signal which is used to control power switch Q4114within inverter module100, and EPWM2B436produces a signal which is used to control power switch Q2112within inverter module100.

EPWM modules EPWM7404and EPWM7A406comprise an auxiliary EPWM channel which is used to produce delayed signals for use during the necessary sequencing of the shut down and restoration of inverter module100. EPWM7A406is one channel of the EPWM modules EPWM7404. In an example embodiment, the desired delay is configurable via a register within EPWM7404, such as illustrated inFIG.7and described below.

In this example, trip signal302fromFIG.3is provided as trip input440to a trip (input) port of MCU400. The trip signal is active low in this example. The trip signal440passes through crossbar402which routes it to various other modules within MCU400. In this example, when trip signal440falls (or is activated) this is called a T1 event. When trip signal440rises (or is de-activated for recovery) this is called a T2 event.

During a T1 event, the falling trip signal441is processed by EPWM module EPWM7404and crossbar408to produce a delayed trip signal443, using a dead-band module within EPWM7404, which is then provided to the other EPWM modules for use in generating delayed shut off signals to the inner power switches within inverter module100. Crossbars402and408route signals internally and reduce external signal connections.

Trip signal442and delayed trip signal443are provided to T1/T2 Action Modules410and412which then provide appropriate trip signals to EPWM modules EPWM1A420, EPWM1B426, EPWM2A430, and EPWM2B436.

Since the grid-tied inverter needs to take care of the control during both positive and negative cycles of the AC current, EPWM1B426and EPWM2B436need to be reconfigured at the zero-cross point of the cycles. During the positive cycle, EPWM1B426and EPWM2B436should be active high complementary (AHC) to EPWM1A420and EPWM2A430respectively. This is accomplished by dead-band modules within EPWM1and EPWM2.

During the negative portion of the AC cycle, EPWM1B426and EPWM2B436should be sourced from a normally high signal configured with actions from the T1 and T2 events. This is accomplished by T1/T2 Action modules410and412respectively.

Trip action modules424and434are configured to control the EPWM modules using the trip signal442as necessary to turn off the power switches within inverter module100in the desired sequence to prevent damage during a fault or trip event.

While this example embodiment illustrates the operation of MCU400to control a single three-level inverter, other embodiments use additional EPWM modules to control multiple three-level inverters, such as used in three-phase power inverter topologies. In such a configuration, EPWM7A406produces delayed trip signals for use by the other EPWM modules.

In this example embodiment, the on-chip signal crossbars402and408enable the routing of any general-purpose input/output (GPIO) signal to operate as any of the dedicated EPWM trip signals. For example, the external fault or trip signal, which comes from the external current/voltage sensing circuit (fault detection module340) is coupled to a GPIO within MCU400as the trip source, and it may also be coupled to one or more of the on-chip crossbars. In other example embodiments, the trip source is flexibly selected from an internal comparator output.

In other example embodiments, trip events of type T1 or T2, sourcing from comparator, trip, or sync events, also generate actions through an action qualifier submodule inside the EPWM modules, allowing for dead-band insertion of trip events.

FIG.5illustrates an example timing diagram of a microcontroller unit configured to provide shut down and recovery sequences to a three-level inverter module during a positive portion of the AC power cycle.

In this example embodiment, various signals within MCU400fromFIG.4are illustrated during a positive portion of the AC power cycle. Clock500in this example is a 20 kHz triangle wave signal provided to the EPWM modules within MCU400. PW set501is used by the EPWM modules to set the pulse width of their outputs. In this example, PW set501is stored in a register, such as that illustrated inFIG.7and described below. When the clock signal500crosses the value of PW set501one or more of the EPWM modules is activated or deactivated.

This timing diagram includes trip event signal502and the outputs of EPWM modules EPWM7A406, EPWM1A420, EPWM1B426, EPWM2A430, and EPWM2B436fromFIG.4.

During the positive portion of the AC power cycle, within inverter module100, first switch Q1111and third switch Q3113are alternatively switching, while second switch Q2112remains on and fourth switch Q4114remains off. As described above, the output of EPWM1A420produces signal S1151which controls first power switch Q1111, the output of EPWM1B426produces signal S3153which controls third power switch Q3113, the output of EPWM2A430produces signal S4154which controls fourth power switch Q4114, and the output of EPWM2B436produces signal S2152which controls second power switch Q2112.

Thus, during the positive portion of the AC power cycle, the outputs of EPWM1A420and EPWM1B426are alternatively switching (while remaining non-overlapping), the output of EPWM2B436remains high, and the output of EPWM2A430remains low. This normal operation is illustrated at times T0520, T1521, T2522, and T3523of the timing diagram. Note that the output of EPWM1B426transitions low at time T0520before the output of EPWM1A420transitions high at time T1521, and the output of EPWM1A420transitions low at time T2522before the output of EPWM1B426transitions high at time T3523, thus providing non-overlapping signals.

Trip event signal502is active low. When a fault or T1 type trip event occurs at time T4524, the output of EPWM1A420immediately transitions low, shutting off outer power switch Q1111. EPWM7A406provides a delayed trip signal (active high) at time T5525, which causes the output of EPWM2B436to transition low, shutting off inner power switch Q2112. Since the outputs of EPWM1B426and EPWM2A430are already low at time T4524they do not need to change.

At time T6526, the trip event signal502is de-activated (T2 type trip event) and recovery of inverter module100begins. The output of EPWM2B436immediately transitions high, turning on inner power switch Q2112, and at the beginning of the next clock cycle at time T7527normal operation of the EPWM modules resumes.

During some faults or trip events, the fault may remain over more than a single clock cycle. This situation is illustrated in the timing diagram at times T8528, T9529, and T10530. When a fault or T1 type trip event occurs at time T8528, the output of EPWM1A420immediately transitions low shutting off outer power switch Q1111. EPWM7A406provides a delayed trip signal (active high) at time T9529, which causes the output of EPWM2B436to transition low shutting off inner power switch Q2112. Since the outputs of EPWM1B426and EPWM2A430are already low at time T8528they do not need to change.

At time T10530, the trip event signal502is de-activated (T2 type trip event) and recovery of inverter module100begins. The output of EPWM2B436immediately transitions high turning on inner power switch Q2112, and at the beginning of the next clock cycle at time T11531normal operation of the EPWM modules resumes.

FIG.6illustrates an example timing diagram of a microcontroller unit configured to provide shut down and recovery sequences to a three-level inverter module during a negative portion of the AC power cycle.

In this example embodiment, various signals within MCU400fromFIG.4are illustrated during a positive portion of the AC power cycle. Clock600in this example is a 20 kHz triangle wave signal provided to the EPWM modules within MCU400. PW set601is used by the EPWM modules to set the pulse width of their outputs. In this example, PW set601is stored in a register. When the clock signal600crosses the value of PW set601one or more of the EPWM modules is activated or de-activated.

This timing diagram includes trip event signal502and the outputs of EPWM modules EPWM7A406, EPWM1A420, EPWM1B426, EPWM2A430, and EPWM2B436fromFIG.4.

During the negative portion of the AC power cycle, within inverter module100, second switch Q2112and fourth switch Q4114are alternatively switching, while third switch Q3113remains on and first switch Q1111remains off. As described above, the output of EPWM1A420produces signal S1151which controls first power switch Q1111, the output of EPWM1B426produces signal S3153which controls third power switch Q3113, the output of EPWM2A430produces signal S4154which controls fourth power switch Q4114, and the output of EPWM2B436produces signal S2152which controls second power switch Q2112.

Thus, during the negative portion of the AC power cycle, the outputs of EPWM2A430and EPWM2B436are alternatively switching (while remaining non-overlapping), the output of EPWM1B426remains high, and the output of EPWM1A420remains low. This normal operation is illustrated at times T0620, and T1621of the timing diagram. Note that the output of EPWM2B436transitions low before the output of EPWM2A430transitions high, and the output of EPWM2A430transitions low before the output of EPWM2B436transitions high, thus providing non-overlapping signals.

Trip event signal602is active low. When a fault or T1 type trip event occurs at time T2622, the output of EPWM2A430immediately transitions low, shutting off outer power switch Q4114. EPWM7A406provides a delayed trip signal (active high) at time T3623, which causes the output of EPWM1B426to transition low, shutting off inner power switch Q3113. Since the outputs of EPWM2B436and EPWM1A420are already low at time T2622they do not need to change.

At time T4624, the trip event signal602is de-activated (T2 type trip event) and recovery of inverter module100begins. The output of EPWM1B426immediately transitions high, turning on inner power switch Q3113, and at the beginning of the next clock cycle at time T5625normal operation of the EPWM modules resumes.

During some faults or trip events, the fault may remain over more than a single clock cycle. This situation is illustrated in the timing diagram at times T6626, T7627, and T8628. When a fault or T1type trip event occurs at time T6626, the output of EPWM2A430immediately transitions low, shutting off outer power switch Q4114. EPWM7A406provides a delayed trip signal (active high) at time T7627, which causes the output of EPWM1B426to transition low, shutting off inner power switch Q3113. Since the outputs of EPWM2B436and EPWM1A420are already low at time T6628they do not need to change.

At time T8628, the trip event signal602is de-activated (T2 type trip event) and recovery of inverter module100begins. The output of EPWM1B426immediately transitions high, turning on inner power switch Q3113, and at the beginning of the next clock cycle at time T9629normal operation of the EPWM modules resumes.

FIG.7illustrates an example embodiment of a microcontroller unit700for controlling a three-level inverter including delayed fault protection. As discussed above, microcontroller unit700may take on any of a wide variety of configurations. Here, a simplified example configuration is provided for a microcontroller unit400as illustrated in greater detail inFIG.4and described above.

In this example embodiment, microcontroller unit700comprises input port710, processing circuitry720, auxiliary EPWM module725, EPWM modules730, and internal storage system740. Input port710comprises circuitry configured to receive a trip or fault signal from a fault detection module such as fault detection module340fromFIG.3. EPWM modules730comprise a plurality of EPWM modules each configured to control a power switch within the three-level inverter. Auxiliary EPWM module725is configured to receive the trip signal702from input port710and to produce a delayed trip signal for use by processing circuitry720and EPWM modules730. The trip delay is stored within delay value register752.

Processing circuitry720comprises electronic circuitry configured to direct microcontroller unit700to control a three-level inverter100including delayed fault protection as described above. Processing circuitry720may comprise microprocessors and other circuitry that retrieves and executes software760. Examples of processing circuitry720include general purpose central processing units, application specific processors, and logic devices, as well as any other type of processing device, combinations, or variations thereof. Processing circuitry720can be implemented within a single processing device but can also be distributed across multiple processing devices or sub-systems that cooperate in executing program instructions.

Internal storage system740can comprise any non-transitory computer readable storage media capable of storing software760that is executable by processing circuitry720. Internal storage system720can also include various data structures750which comprise one or more registers, databases, tables, lists, or other data structures. Storage system740can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. In this example embodiment, internal storage system740includes registers within the EPWM modules and flash memory within microcontroller unit700which also stores configuration codes and instructions.

Storage system740can be implemented as a single storage device but can also be implemented across multiple storage devices or sub-systems co-located or distributed relative to each other. Storage system740can comprise additional elements, such as a controller, capable of communicating with processing circuitry720. Examples of storage media include random access memory, read only memory, magnetic disks, optical disks, flash memory, virtual memory and non-virtual memory, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and that can be accessed by an instruction execution system, as well as any combination or variation thereof.

Software760can be implemented in program instructions and among other functions can, when executed by microcontroller unit700in general or processing circuitry720in particular, direct microcontroller unit700, or processing circuitry720, to operate as described herein to control a three-level inverter100including delayed fault protection. Software760can include additional processes, programs, or components, such as operating system software, database software, or application software. Software760can also comprise firmware or some other form of machine-readable processing instructions executable by elements of processing circuitry720.

In at least one example implementation, the program instructions include EPWM control module762, and trip action module764. EPWM control module762provides instructions to processing circuitry720for use in directing the plurality of EPWM modules730to each control a power switch within the three-level inverter. Trip action module764provides instructions to processing circuitry720for use in directing auxiliary EPWM module725to produce a delayed trip signal and to control EPWM modules730during a trip event.

In an example embodiment, data750includes delay value register752that stores a delay value used by auxiliary EPWM module725to produce the delayed trip signal. Data750also includes pulse width register754that stores one or more pulse width values used by EPWM modules730to set the width of their pulses.

In general, software760can, when loaded into processing circuitry720and executed, transform processing circuitry720overall from a general-purpose computing system into a special-purpose computing system customized to operate as described herein for a microcontroller unit700configured to control a three-level inverter100including delayed fault protection, among other operations. Encoding software760on internal storage system740can transform the physical structure of internal storage system740. The specific transformation of the physical structure can depend on various factors in different implementations of this description. Examples of such factors can include, but are not limited to the technology used to implement the storage media of internal storage system740and whether the computer-storage media are characterized as primary or secondary storage.

For example, if the computer-storage media are implemented as semiconductor-based memory, software760can transform the physical state of the semiconductor memory when the program is encoded therein. For example, software760can transform the state of transistors, capacitors, or other discrete circuit elements constituting the semiconductor memory. A similar transformation can occur with respect to magnetic or optical media. Other transformations of physical media are possible without departing from the scope of the present description, with the foregoing examples provided only to facilitate this discussion.

FIG.8illustrates an example flow chart of a method for operating a microcontroller unit700configured to provide shut down and recovery sequences to a three-level inverter module100.

In this example method, microcontroller unit700receives a trip signal from a fault detection module at an input port within the microcontroller unit700, (operation800). Processing circuitry720within microcontroller unit700controls a plurality of power switches111-114within the three-level inverter100via a plurality of Enhanced Pulse Width Modulation (EPWM) modules730within the microcontroller unit700, each configured to control one of the power switches within the three-level inverter100, (operation802).

Auxiliary EPWM module725within microcontroller unit700produces a delayed trip signal from the trip signal, (operation804). In response to activation of the trip signal702, processing circuitry720directs one of the plurality of EPWM modules730to shut off its corresponding power switch upon activation of the trip signal702, (operation806). Also in response to activation of the trip signal702, processing circuitry720directs a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal, (operation808).