Systems and methods for achieving uniformity across a redistribution layer

Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.

FIELD

The present embodiments relate to systems and methods for achieving uniformity across a redistribution layer.

BACKGROUND

Generally, electrochemical deposition processes are used in modern integrated circuit fabrication. Metal line interconnections drive a need for increasingly sophisticated electrodeposition processes and plating tools. Much of the sophistication evolved in response to a need for ever smaller current carrying lines in device metallization layers. These lines are formed by electroplating metal into very thin, high-aspect ratio trenches and vias.

Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally and colloquially as wafer level packaging (WLP) and electrical connection technology. These technologies present their own very significant challenges due in part to the generally smaller feature sizes and low aspect ratios.

It is important that with the smaller feature sizes and finer pitches, an amount of electrical conductivity provided by the features is not compromised. It is in this context that embodiments described in the present disclosure arise.

SUMMARY

Embodiments of the disclosure provide systems and methods for achieving uniformity across a redistribution layer. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a device, or a method on a computer-readable medium. Several embodiments are described below.

High density fan-out (HDFO) wafer-level packaging (WLP) is a plating technology aimed at improving package performance, shrinking a form factor, and driving down associated costs. HDFO WLP is viewed as an alternative to a significantly more expensive through-silicon-via (TSV) technology. HDFO presents some electroplating applications of interest, such as fine pitch redistribution layer (RDL) and stacking RDLs.

Fan out (FO) technology involves a Semi-Additive-Process (SAP) where RDL lines are formed, copper is plated in a patterned area, and photoresist is stripped and a barrier and seed layer is etched from substrate. Moreover, FO technology includes electrodepositing single layer copper RDLs which vary in line thickness from 10 microns to 100 microns and in spacing between two adjacent lines from 10 microns to 100 microns, while HDFO technology includes electrodepositing copper in much finer pitch RDLs. For example, in HDFO technology, thickness of an RDL lines is 2 microns and spacing between two adjacent RDL lines is 2 microns. As another example, in HDFO technology, thickness of an RDL lines ranges from 2 microns to 10 microns and spacing between two adjacent RDL lines ranges from 2 microns to 10 microns.

During a stacked RDL process, significant topography is created over a wafer surface during the creation of each RDL layer. This variation in topography limits a depth of focus of lithography, which in turn, leads to line size variation across the wafer surface and resolution issues of finer line scaling. Described herein are methods to overcome the issue of the variation of the topography with a two-step process (1) plate the RDL conformally while superfilling a via, such that overgrowth of a conductive material, such as copper or invar (FeNi36) or cobalt, is created over the via, followed by (2) electropolishing or electroetching the conductive material so that a planar via-RDL surface is formed.

In some embodiments, the systems and methods for achieving uniformity across the RDL layer include superfilling a via with an RDL structure, e.g., a bump, such that overgrowth over the via is formed. Further, the systems and methods include performing an electropolish or electroetch process to planarize the RDL structure of the RDL layer and/or other RDL regions of the RDL layer to minimize any topographical variation induced by electroplating of the conductive material. In various embodiments, the superfilling and electropolish or electroetch process for the RDL structure and/or the other RDL regions are performed sequentially in the same plating bath to minimize wafer transfers and maximize tool throughput. In some embodiments, the superfilling and electropolish or electroetch process for the RDL structure and/or the other RDL regions is performed sequentially in different plating cells or different plating baths but within the same plating tool platform to simplify a wafer process flow and maximize wafer yields.

In various embodiments, a method for processing a substrate to improve topographic uniformity of a redistribution layer when interfaced with a via is described. The method includes patterning a photoresist layer over the substrate. The patterning defines a region for a conductive line and the via disposed below the region for the conductive line. The conductive line is at a level of the redistribution layer. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing is further controlled to cause an overgrowth of conductive material of the conductive line to form a bump of the conductive material directly over the via. The conductive material of the conductive line and the bump are maintained to a fill level that is below a top surface of the patterned photoresist layer. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by a liquid chemistry that is caused to exert a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump. The method includes stripping the photoresist after performing the planarizing.

In some embodiments, a method for achieving uniformity of a redistribution layer is described. The method includes depositing an organic dielectric layer on top of a pad located on a substrate, creating a plurality of vias within the dielectric layer to create a plurality of intermediate portions of the dielectric layer, and depositing a barrier and seed layer on top the dielectric layer to form a film on top of the dielectric layer. The film is formed within the vias and on top of the intermediate portions. The method further includes depositing a photoresist on top of the film of the seed layer to fill the vias and to form a layer over the intermediate portions of the dielectric layer. The method includes pattering intermittent areas of the photoresist by removing portions of the photoresist to uncover portions of the film deposited within the vias and additional portions of the film deposited on sections of the intermediate portions of the dielectric layer. The method includes depositing the redistribution layer on top of the portions of the film deposited within the vias and on top of the additional portions of the film such that a height of the redistribution layer is less than a height of the layer of the photoresist. The height of the redistribution layer and the height of the layer of the photoresist are measured from the substrate. The operation of depositing the redistribution layer is performed to overfill the vias. The overfill is performed to create bumps of the redistribution layer. The bumps are created between the intermittent areas of the photoresist. The method includes removing the bumps between the intermittent areas of the photoresist to achieve the uniformity.

Some advantages of the herein described systems and methods for achieving uniformity across the RDL layer, e.g., reducing nonuniformity across the RDL layer, removing nonuniformity across the RDL layer, etc., by performing the electroetching or the electropolishing of the RDL layer that is present between two adjacent areas of a patterned photoresist layer. The areas of the patterned photoresist layer define placement of the RDL layer. Moreover, a high, uniform transverse shear flow of a catholyte from a plating reactor facilitates achieving a uniform electrodeposition of copper of the RDL layer across a surface of the substrate. Likewise, a uniform shear flow of the catholyte improves the uniformity and overall efficiency of the electrodeposition or of an electroetching process.

Additional advantages of the herein described systems and methods include using cobalt or invar or a combination thereof to fabricate the RDL layer. Cobalt and invar have a low thermal expansion, and therefore have a low chance of cracking under high temperatures.

Further advantages of the herein described systems and methods include using a combination of two or more of copper, cobalt, and invar to fabricate the RDL layer. The combination has a low chance of cracking under high temperatures.

DETAILED DESCRIPTION

The following embodiments describe systems and methods for achieving uniformity across a redistribution layer. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

FIG. 1Ais a diagram of an embodiment of a method100to illustrate fabrication of a redistribution layer (RDL)104(FIG. 1B) over a substrate102. The substrate102is a thin slice of material, such as, silicon or an alloy of silicon and germanium, etc. The method100includes an operation150of depositing a layer124of a dielectric material, e.g., an organic dielectric material such as polyimide (PI), on top of a pad122, to form a film of the dielectric material overlaid on the pad122. An example of the operation150is a spincoat process. The operation150is performed using a system800described below with reference toFIG. 8. The pad122is made of a metal, such as, copper, or aluminum, or tungsten, or a combination thereof. The pad122is overlaid on top of the substrate102. In some embodiments, the pad122is deposited on the substrate102by using the system800. The pad layer122is between the dielectric layer124and the substrate102. It should be noted that in some embodiments, there is no pad122between the substrate102and the dielectric layer124. Rather, the dielectric layer124is adjacent to the substrate102.

After depositing the dielectric layer124on top of the pad122, in an operation152of the method100, the dielectric layer124is patterned to create multiple vias, such as a via154, between intermediate portions, such as intermediate portions124A and124B, of the dielectric layer124. The operation152is performed using a wafer stepper900, illustrated inFIG. 9, and an immersive container1000, illustrated inFIG. 10. The immersive container1000is sometimes referred to herein as a wet bench. The vias between the intermediate portions of the dielectric layer124are formed to uncover portions, such as a portion156, of the pad122.

Furthermore, after the operation152of patterning, a thin film of a barrier layer, e.g., a layer of titanium, or a layer of tungsten, or a layer of tantalum, or a layer of a combination of two or more of titanium, tungsten, and tantalum, etc., is deposited on top of the dielectric layer124. The thin film of the barrier layer is deposited in an operation158of the method100to cover the intermediate portions124A and124B of the dielectric layer124and to cover the portion156of the pad122on top of which the via154is patterned. The operation158is performed using physical vapor deposition (PVD). The PVD process is described below using a system1100.

Moreover, a copper seed layer is deposited on top of the barrier layer in the operation158to form a thin film of the copper seed layer on top of the barrier layer. For example, the PVD process is repeated again in the operation158after depositing the barrier layer to deposit the copper seed layer. The copper seed layer is deposited to cover portions of the barrier layer that cover the intermediate portions124A and124B of the dielectric layer124and to cover portions of the barrier layer that are overlaid on top of the portion156of the pad122. The copper seed layer and the barrier seed layer are collectively referred to herein as a barrier and seed layer123. When the barrier and seed layer123is deposited on top of the intermediate portions124A and124B of the dielectric layer124and top of portions, such as the portion156, of the pad122, vias, such as a via106, are formed between the intermediate portions124A and124B of the dielectric layer124. When the via154is coated with the barrier and seed layer123, the via106is formed on top of a portion of the barrier and seed layer123. The portion of the barrier and seed layer123is overlaid within the via106. The entire via154is not filled with the barrier and seed layer123but a thin film of the barrier and seed layer123is formed within the via154to create the via106.

After the operation158of depositing the barrier and seed layer123is performed, in an operation160of the method100, a photoresist layer108is deposited on top of the barrier and seed layer123. The photoresist layer108is deposited by performing the spincoat process. For example, the system800is used to overlay the photoresist layer108on top of the barrier and seed layer123. The photoresist layer108is deposited to fill the via106and to form a thick layer on top of the barrier and seed layer123, e.g., over the intermediate portions124A and124B of the dielectric layer124. The photoresist layer108includes portions, such as a portion128, which are further described below. The portion128extends over a portion of the intermediate portion124A, over a portion of the intermediate portion124B, and over the via106.

It should be noted that a combination of the substrate102, the pad122on top of the substrate102, and the dielectric layer124on top of the pad122is referred to herein as a substrate package103. Moreover, a combination of the substrate102, the pad122on top of the substrate102, and the adjacent portions124A and124B of the dielectric layer124on top of the pad122and the via154on top of the pad122is sometimes referred to herein as a substrate package105. Also, a combination of the substrate102and the pad122is sometimes referred to herein as a substrate package107. A combination of the substrate102, the pad122, the intermediate portions124A and124B, and the barrier and seed layer123is sometimes referred to herein as a substrate package109.

FIG. 1Bis a diagram of an embodiment of the method100for illustrating the fabrication of the RDL layer104.FIG. 1Bis a continuation of the method100illustrated inFIG. 1A. After performing the operation160ofFIG. 1A, an operation162of the method100is performed. In the operation162, the photoresist layer108(FIG. 1A) is patterned such that adjacent areas, e.g., adjacent areas A1and A2, of the photoresist layer108are formed to create multiple regions, such as a region110, between the adjacent areas. The region110is a space between the areas A1and A2. The patterning of the photoresist layer108is performed using the wafer stepper900(FIG. 9) and the immersive container1000(FIG. 10). The region110is formed between the two adjacent areas A1and A2and on top of the via106. A distance between the two adjacent areas A1and A2is represented as d. The distance d is a width of the region110and is greater than a maximum width w, e.g., a diameter, etc., of the via106. The maximum width w of the via106is greater than all remaining widths of the via106. The region110is created by removing portions, such as a portion128(FIG. 1A), of the photoresist layer108. The portion128is removed to uncover portions132A and132B of the barrier and seed layer123. The portion132A is deposited on a section134A of the dielectric layer124and the portion132B is deposited on a section134B of the dielectric layer124. Moreover, the portion128is removed to uncover an additional portion130of the barrier and seed layer123that is below the maximum width w of the via106.

After performing the operation162, a descum operation164of the method100is performed. The descum operation162is performed to remove any residual photoresist within trenches of the via106and to improve wettability of the photoresist areas A1and A2. The descum operation164makes the photoresist less hydrophobic. The descum operation164is performed using a system1200illustrated inFIG. 12.

After performing the descum operation164, a pre-treatment operation166of the method100is performed. An example of the pre-treatment operation166is described in U.S. Pat. No. 8,962,085, which is incorporated by reference herein in its entirety. As another example, the pre-treatment operation is a pre-wetting operation performed using a system1300ofFIG. 13Aor a system1320ofFIG. 13B.

In an operation168of the method100, a conductive material112, such as copper, or cobalt, or invar, or nickel, or an alloy of nickel and cobalt and iron, or a combination of two or more of copper, cobalt, invar, nickel, the alloy of nickel and cobalt and iron, is deposited within the vias, such as the via106, and within the regions, such as the region110, between the adjacent areas A1and A2of the photoresist layer108. An example of the alloy of nickel, cobalt, and iron is F15™ material with matched alpha to borosilicate glass. The operation168is performed after the pre-treatment operation166. It should be noted that in some embodiments, cobalt is impervious to copper seed etchant chemistry, e.g., etchant that is used to etch the copper seed layer, and has approximately 2× higher Young's modulus compared to copper to improve electrical and mechanical performance of the RDL layer104. The higher Young modulus strengthens the RDL layer104. Moreover, cobalt has a thermal expansion of 17 parts per million per degree Celsius (ppm/° C.) and copper has a thermal expansion of 13 ppm/° C. Therefore, a high density fan out (HDFO) package that has cobalt as an RDL layer has a lower chance, such as by 30%, of cracking during applications of the HDFO package that include high temperatures. Similarly, invar has a thermal expansion of less than 1 ppm/° C.

A table, provided below, provides properties of copper and cobalt.

Moreover, a table provided below provides properties of invar.

The operation168of electrodeposition is performed using a system1400illustrated inFIG. 14A. In some embodiments, the operation168is performed using an apparatus described in U.S. Pat. No. 9,523,155, which is incorporated by reference in its entirety. In the operation168, the vias, such as the via106, are overfilled with the conductive material112to create multiple bumps, such as a bump114, and to create multiple leveled layers, such as a leveled layer LL1and a leveled layer LL2. As an example, a diameter of the bump114ranges between 180 micrometers to 220 micrometers. To illustrate, a diameter of the bump114is 200 micrometers. The conductive material112is deposited on top of the portions132A and132B of the barrier and seed layer123and on top of the portion130of the barrier and seed layer123. Each of the leveled layers LL1and LL2are at a level117. The bump114is created over, e.g., directly over, the via106. For example, a width, e.g., a diameter, a perimeter, etc., of the bump114is less than the maximum width w of the via106. As another example, the bump114is concentric with the via106. As yet another example, the width of the bump114is less than the maximum width w of the via106and the bump is concentric with the via106. As another example, the width of the bump114is less than the maximum width w of the via106and the bump114lies within a confinement defined by lines extending vertically from the maximum width w. In some embodiments, a width of the bump114is greater than the maximum width w of the via106. Also, a fill level116until which the via106and a portion of the RDL layer104directly over the via106is filled is less than a level118of a top surface of the photoresist layer108. Also, the level117is lower than the fill level116and the level118of the top surface of the photoresist layer108. The leveled layer LL1is developed between the bump114and the adjacent area A1of the photoresist layer108and the leveled layer LL2is developed between the bump114and the adjacent area A2of the photoresist layer108. In some embodiments, a portion of the leveled layer LL1is created over, e.g., directly over, the via106and a portion of the leveled layer LL1is created over, e.g., directly over, the via106with the bump114also created directly over the via106. It should be noted that a height h2of the areas A1and A2of the photoresist layer108is greater than a height h1of the bump114. The heights h1and h2are measured from a bottom surface of the substrate102. Similarly, the levels116through118are measured from the bottom surface of the substrate102. The bump114is fabricated between the adjacent areas A1and A2of the photoresist layer108.

Once the operation168is performed, in an operation170of the method100, the bumps of the conductive material112, e.g., the bump114, is removed in an electropolishing operation170, which is sometimes referred to herein as an electroetching operation. The electropolishing operation170is performed using the system1400ofFIG. 14B. However, instead of using the conductive material112as a catholyte, during the electropolishing operation170, an acid, such as a phosphoric acid or sulfuric acid, is used to polish the bumps. In some embodiments, the conductive material112is used to etch the bumps. The bumps of the conductive material112are polished to planarize a top surface120of the RDL layer104. The planarizing of the top surface120is performed to form leveled areas, e.g., a leveled area LL3, between the leveled layers LL1and LL2.

In various embodiments, the planarizing of the top surface120is performed to remove or reduce nonuniformities in areas of the RDL layer104between the bump114and the area A1or A2of the photoresist layer108. In these embodiments, some nonuniformities may remain after the operation168.

In some embodiments, the level of the leveled areas, e.g., the leveled area LL3, matches a height, measured from the lower surface of the substrate102, of the leveled layers LL1and LL2such that a leveled layer is formed between the adjacent areas A1and A2. For example, each of the leveled layers LL1, LL2, and LL3is at the level117.

After the operation170, an operation172of photoresist stripping of the method100is performed. The operation172is performed using the system1200ofFIG. 12. In some embodiments, the operation172is performed using an apparatus described in U.S. Pat. No. 7,605,063, which is incorporated by referenced in its entirety. In various embodiments, a diptank is used to perform the operation172of photoresist stripping. The photoresist layer108having the adjacent areas A1and A2are dipped in a photoresist solvent to remove the areas A1and A2. The photoresist layer108, e.g., the adjacent areas A1and A2, are removed or etched during the operation172. The adjacent areas, such as the adjacent areas A1and A2, of the photoresist layer108are removed to uncover portions, such as portions136A and136B, or the barrier and seed layer123that surround the RDL layer104

Upon performing the operation172, an operation174of the method100is performed. The operation174is performed using the apparatus1200ofFIG. 12. To illustrate, the copper seed layer is etched away first during the operation172to uncover the barrier layer. The copper seed layer is etched away using an etchant, e.g., an acid, a corrosive chemical, a copper etchant, etc. The barrier layer, that is below the copper seed layer, is then etched away to uncover portions, such as portions138A and138B, of the dielectric layer124. The barrier layer is etched away using an etchant, e.g., an acid, a corrosive chemical, etc. During the operation174, the portions, e.g., the portions136A and136B, etc., of the barrier and seed layer123are etched away to uncover the portions of the dielectric layer124. After the operation174is performed, conductive lines of the RDL layer104remain on top of the via106. Each conductive line has a leveled top surface. For example, the conductive line of the RDL layer104has a planar top surface that lies within a horizontal plane. To illustrate, there is a lack of nonuniformity in the planar top surface of the RDL layer104after performing the operation170of electropolishing. As another illustration, an amount of uniformity within the RDL layer104is less than a pre-determined threshold after performing the operation170of electropolishing. As yet another illustration, there are none or minimal nonuniform areas, e.g., roughness, grooves, etc., in which residue or remnants trap themselves thereby reducing conductivity of the RDL layer104.

In some embodiments, both the operations172and174are performed in the same chamber, e.g., a single plasma chamber1202, which is described below with reference toFIG. 12. It should be noted that the portion138A of the dielectric layer124is adjacent to the portion134A of the dielectric layer124and the portion138B of the dielectric layer124is adjacent to the portion134B of the dielectric layer124. The portion134A of the dielectric layer124is adjacent to the via106and the portion134B of the dielectric layer124is adjacent to the via106. The portion134B of the dielectric layer124is located on an opposite side of the via106compared to the portion134A of the dielectric layer124. Similarly, the portion138A of the dielectric layer124is located on an adjacent side of the via106compared to the portion138B of the dielectric layer124.

In an operation176, which is performed after the operation174, a spin, rinse, and dry (SRD) process is performed on the RDL layer104and the portions138A and138B of the dielectric layer124. The SRD process occurs in a spin rinse dryer. During the SRD operation, the substrate102is rotated on a support to perform the spin operation. Moreover, the rinse operation is performed by allowing a flow of deionized water on top of the RDL layer104and the portions138A and138B of the dielectric layer124for a set period of time, e.g., a minute, two minutes, etc. The deionized water is then blown out from the SRD. During the dry operation, a space within the SRD is heated using heaters to evaporate droplets of the deionized water from the RDL layer104and from the portions138A and138B of the dielectric layer124.

It should be noted that a combination of the substrate102, the pad122, the patterned dielectric layer124, the portions130,132A and132B of the barrier and seed layer123, and the patterned photoresist layer108is sometimes referred to herein as a substrate package135. Furthermore, it should be noted that a combination of the substrate102, the pad122, the patterned dielectric layer124, the areas A1and A2of the patterned photoresist layer108, and the RDL layer104having the bumps is sometimes referred to herein as a substrate package141. Moreover, it should be noted that a combination of the substrate package102, the pad122, the patterned dielectric layer124, the via106, the RDL layer104, and the patterned photoresist layer108is sometimes referred to herein as a substrate package137. Also, it should be noted that a combination of the substrate package102, the pad122, the patterned dielectric layer124, the via106, the RDL layer104, and the portions136A and136B of the barrier and seed layer123is sometimes referred to herein as a substrate package139.

In some embodiments, adjacent areas, described herein, are sometimes referred to herein as proximate regions.

FIG. 2is a diagram of an embodiment of a method200to illustrate a fabrication of the RDL layer104over the substrate102. In the method200, the operation160of depositing the photoresist layer108on top of the barrier and seed layer123is performed. It should be noted that as illustrated inFIG. 2, there is no dielectric layer124and no pad122located between the substrate102and the photoresist layer108. Moreover, after the operation160, the operation162of patterning the photoresist layer108, the descum operation164, and the pre-treatment operation166are performed in the method200. The operation162of patterning the photoresist layer108is performed to fabricate the adjacent areas A1, A2, and more adjacent areas A3, A4, and A5. Once the operation166is performed, the operation168of electrodeposition of the conductive material112is performed in the method200. For example, another bump114of the RDL layer104is fabricated between the adjacent areas A3and A1, yet another bump114of the RDL layer104is fabricated between the adjacent areas A2and A4, and another bump114of the RDL layer104is fabricated between the adjacent areas A4and A5. Also, after the operation168is performed, the operation170of electropolishing each bump114is performed. Each bump114is electropolished to form the top surface120of the RDL layer104to form patterns P1, P2, P3, and P4of the RDL layer104. For example, another top surface120is formed between the adjacent areas A3and A1, yet another top surface120is formed between the adjacent areas A2and A4, and another top surface120is formed between the adjacent areas A4and A5.

After the operation170, the operation172of the method200is performed. The operation172includes stripping patterns, e.g., the adjacent areas A1through A5, of the photoresist layer108is performed. The operation172of stripping the adjacent areas A1through A5of the photoresist layer108is performed until portions136A and136B of the barrier and seed layer123are uncovered. Moreover, during the operation172, a portion136C of the barrier and seed layer123is uncovered. It should be noted that the portion136A is between the two adjacent patterns P1and P2of the RDL layer104, the portion136B is between the two adjacent patterns P2and P3of the RDL layer104, and the portion136C is between the two adjacent patterns P3and P4of the RDL layer106.

Once the operation172is performed, the operation174of the method200is performed. During the operation174, the portions, such as the portions136A,136B, and136C of the barrier and seed layer123are etched. When the portions of the barrier and seed layer123are etched, portions, such as portions182A,182B,182C, and182D of the substrate102are uncovered. The portion182B is between the portions P1and P2of the RDL layer104, the portion182C is between the portions P2and P3of the RDL layer104, and the portion182D is between the portions P3and P4of the RDL layer104.

FIG. 3is a diagram of an embodiment of a substrate package300to illustrate the RDL layer104that includes the bumps, such as the bump114. The substrate package300includes the substrate102as its bottom layer. The substrate102is overlaid with the pad122on top of the substrate102. The dielectric layer108is deposited on the pad122and is patterned to form the intermediate portions124A and124B of the dielectric layer108The operation of electrodeposition is performed to overfill the via106with the conductive material112to form the RDL layer106with the bump114. For example, a diameter of the bump114is less than the maximum width w of the via106and a height of the bump114as measured from a lower surface302of the substrate102is greater than a height of the via106from the lower surface302. Moreover, a height of the leveled layer LL1from the lower surface302of the substrate102is greater than the height of the via106and a height of the leveled layer LL2from the lower surface302of the substrate102is greater than the height of the via106.

FIG. 4is a diagram of an embodiment of a substrate package400to illustrate nonuniformities in an RDL layer2created by nonuniformities in an RDL layer1. The substrate package400includes a substrate. Over the substrate is a pad. On top of the pad is a dielectric layer1. Over the dielectric layer1is an RDL layer1. There is a nonuniformity402within the RDL layer1. For example, the nonuniformity402has multiple surfaces404A,404B, and404C angled with respect to each other. To illustrate, an angle between the surface404A and404B is greater than 0 degree or greater than 0.1 degree. As another illustration, an angle between the surface404B and404C is greater than 0 degree or greater than 0.1 degree. As another example, the nonuniformity402has a curvature and is not straight. Comparatively, in some embodiments, a uniform RDL layer lacks a curvature and is straight, e.g., leveled. As yet another example, a level of the surfaces404A,404B, and404C deviates from a level LVL1of a top surface403of the RDL layer1.

As a result of the nonuniformity of the RDL layer1, a dielectric layer2that is on top of the RDL layer1is nonuniform. Moreover, as a result of the nonuniformity of the dielectric layer2, another RDL layer2that is over the dielectric layer2is nonuniform. For example, there is a nonuniformity406within the RDL layer2. The nonuniformity406has a curvature. As another example, the nonuniformity406deviates from a level LVL2of the RDL layer2. The nonuniformity406degrades performance of the RDL layer2. For example, conductivity of the RDL layer2decreases. Also, there may be remnant materials of a process, described herein, e.g., SRD process, etc., deposited within the nonuniformity406to degrade the performance.

FIG. 5is a diagram of an embodiment of a substrate package500to illustrate an RDL layer506that has minimal, e.g., within the pre-determined threshold, etc., or zero nonuniformities on its top surface. The substrate package500includes the substrate102and the pad122deposited over the substrate102. In some embodiments, there is a layer, e.g., a dielectric layer, between the pad122and the substrate102.

The package500further includes the dielectric layer124deposited on top of the pad122and the RDL layer104deposited over the dielectric layer124. Another dielectric layer502of the package500is deposited on top of the RDL layer104. For example, the operation150(FIG. 1A) of depositing the dielectric material on the RDL layer104is repeated to deposit the dielectric layer502. Moreover, the dielectric layer502is patterned by repeating the operation152to create vias, such as a via504, within the dielectric layer502. Furthermore, the operation158(FIG. 1A) is repeated to deposit a thin film of a barrier and seed layer on top of the dielectric layer502. Also, a photoresist layer is deposited on the barrier and seed layer deposited on top of the dielectric layer502by repeating the operation160ofFIG. 1A. The photoresist layer deposited on the barrier and seed layer is then patterned by repeating the operation162ofFIG. 1B. The patterning is created to create additional adjacent areas, such as the adjacent areas A1and A2(FIG. 1B), of the photoresist layer deposited over the dielectric layer502. Moreover, a distance between the additional adjacent areas of the photoresist layer deposited over the dielectric layer502is greater than a maximum width of the via504.

Furthermore, the operations164and166ofFIG. 1Bare repeated to be performed on the patterned photoresist layer. Then, the operation168(FIG. 1B) of electrodeposition of the conductive material112is performed on the barrier and seed layer deposited on the dielectric layer502and between the additional adjacent areas of the patterned photoresist layer deposited over the dielectric layer502to fabricate bumps, such as the bump114(FIG. 1B), of the conductive material112and to create leveled layers, such as the leveled layers LL1and LL2(FIG. 1B), of the RDL layer506. The bumps are fabricated directly over the vias, such as the via504.

Thereafter, the operation170of electropolishing is performed to remove the bumps of the conductive material112to further create a leveled surface, similar to the top surface120having the leveled layers LL1, LL2, and LL3, of the RDL layer506. For example, the operation170applies the shear horizontal force to remove a bump, similar to the bump114(FIG. 1B), of the conductive material112to further create a planar surface between two of the additional adjacent areas. The horizontal shear force is parallel to a top surface507of the RDL506and is applied between the bump and the two additional adjacent areas. After the bumps of the RDL layer506are removed, the patterned photoresist is then striped using the operation172ofFIG. 1B. Moreover, the barrier and seed layer is etched using the operation174ofFIG. 1Bto form the RDL layer504. The RDL layer504is on top of the barrier and seed layer and over the dielectric layer502. Then the operation176(FIG. 1B) of SRD is performed on the substrate package500.

It should be noted that the RDL layer104does not have any or has a minimal amount of nonuniformities. The RDL layer506, therefore, also does not have any or has a minimal amount of nonuniformities. It should further be noted that a combination of the pad122over the substrate102, the dielectric layer124on top of the pad124, the RDL104over the dielectric layer124, and the dielectric layer502on top of the RDL104is sometimes referred to herein as a substrate package503.

In various embodiments, the RDL layer104is fabricated from copper and the RDL layer506is fabricated from cobalt or invar. This is because etchant of the copper seed layer deposited on top of the patterned dielectric layer502has less of an effect on mechanical integrity of the RDL layer506fabricated from cobalt of invar.

FIG. 6is a diagram of an embodiment of a substrate package600to illustrate deposition of multiple RDL layers. The substrate package600includes the layers of the substrate package500(FIG. 5). Moreover, on top of the RDL layer506, a dielectric layer602of the substrate package600is deposited by using the operation150ofFIG. 1A. Furthermore, after depositing the dielectric layer602, the dielectric layer602is patterned by performing the operation152(FIG. 1A). After the dielectric layer602is patterned, a barrier and seed layer is deposited on top of the patterned dielectric layer602by performing the operation158(FIG. 1A). Thereafter, a photoresist layer is deposited on the barrier and seed layer deposited on top of the patterned dielectric layer602by performing the operation160(FIG. 1A). The photoresist layer is then patterned by performing the operation162(FIG. 1B), followed by the descum operation164(FIG. 1B) and the pre-treatment operation166(FIG. 1B). Then, the conductive material112is deposited between portions of the patterned, descummed, and pre-treated photoresist layer to form bumps, such as the bump114(FIG. 1B), of the conductive material112and to create leveled areas, such as the leveled layers LL1and LL2(FIG. 1B), of the conductive material112. For example, a bump and the leveled areas are created between two adjacent areas of the patterned, descummed, and pre-treated photoresist layer. The operation170(FIG. 1B) of electropolishing the bumps is then performed to create a leveled surface, similar to the top surface120, of an RDL layer606that is formed over the dielectric layer602and on top of the barrier and seed layer. For example, a horizontal shear force is applied to remove the bump between the adjacent areas of the patterned, descummed, and pre-treated photoresist layer. Once the electropolishing operation170is performed, the operation172(FIG. 1B) of stripping the patterned, descummed, and pre-treated photoresist layer is performed. Portions of the barrier and seed layer on top of the dielectric layer602are etched by performing the operation174(FIG. 1B). Then the operation176(FIG. 1B) of SRD is performed on the substrate package600.

It should be noted that the RDL layer506does not have any or has a minimal amount of nonuniformities. The RDL layer606, therefore, also does not have any or has a minimal amount of nonuniformities. It should further be noted that a combination of the substrate package503, the RDL506over the dielectric layer502and the dielectric layer602on top of the RDL506is sometimes referred to herein as a substrate package603.

In some embodiments, any number of RDL layers, e.g., four, five, six, etc., are deposited over the substrate102, in a similar manner in which the RDL layers506and606are formed over the substrate102.

In various embodiments, the RDL layer104is fabricated from cobalt, the RDL layer506is fabricated from invar, and the RDL layer606is also fabricated from invar. This is because a high conductivity of cobalt results creates a low resistance in the RDL layer506and use of invar minimizes any coefficient of thermal expansion (CTE) effects.

In some embodiments, the RDL layer104is fabricated from copper, the RDL layer506is fabricated from invar, and the RDL layer606is also fabricated from invar. This is because a high conductivity of copper results in a low resistivity of the RDL layer104and use of invar minimizes any coefficient of thermal expansion (CTE) effects.

In various embodiments, the RDL layer104is fabricated from any of the conductive materials, e.g., the conductive material112, described above, the RDL layer506is fabricated from any of the conductive materials, e.g., the conductive material112, described above, and the RDL layer606is fabricated from any of the conductive materials, e.g., the conductive material112, described above. For example, the RDL layer104is fabricated from nickel, the RDL layer506is fabricated from invar, and the RDL layer606is fabricated from an alloy of nickel and cobalt and iron. As another example, the RDL layer104is fabricated from an alloy of nickel and cobalt and iron, the RDL layer506is fabricated from cobalt, and the RDL layer606is fabricated from invar.

FIG. 7is a diagram of an embodiment of an integrated circuit stack700. The integrated circuit stack700is a high density fan out (HDFO) package that has multi-die systems. In some embodiments, a thickness of the HDFO package ranges between 0.8 millimeters and 0.1 millimeters. For example, a height of the HDFO package is 0.9 millimeters. The integrated circuit stack700has benefits, such as, a lower height compared to a through-silicon-via (TSV) integrated circuit stack, improved thermal performance compared to the TSV integrated circuit stack, consumption of lower power than the TSV integrated circuit stack, a higher bandwidth memory compared to the TSV integrated circuit stack, and a simplified supply chain compared to the TSV integrated circuit stack.

The integrated circuit stack700includes a top integrated circuit (IC) package702, such as a memory circuit package, and a bottom IC package704, such as a logic circuit package. In some embodiments, both the top and bottom IC packages are memory circuit packages or logic circuit packages.

The top IC package702includes a system-on-chip (SoC)706A that is placed on top of another SoC706B. In some embodiments, the top IC package702has a single SoC or multiple SoCs stacked on top of each other. The bottom IC package704has an SoC708. In some embodiments, the bottom IC package704has multiple SoCs stacked on top of each other.

A substrate package710of the bottom IC package704is coupled to the SoC708via one or more under bump metallizations (UBMs), such as a UBM712, and one or more pillars, e.g., a pillar714. Sometimes, a pillar is referred to herein as a microbump. The substrate package500(FIG. 5) is an example of the substrate package710. In some embodiments, instead of the substrate package500, the substrate package600(FIG. 6) or another substrate package with multiple RDLs is used in the integrated circuit stack700.

Moreover, the SoC708is coupled to the top IC package702via an RDL716and one or more megapillars, e.g., a megapillar718. A component, e.g., a memory device, a memory controller, a processor, a logic circuit, etc., of the SOC708communicates with another component, e.g., a memory device, a memory controller, a processor, a logic circuit, etc., of the top IC package702via the RDL716and the one or more megapillars.

In some embodiments, the one or more UBMs are fabricated from copper, or nickel, or gold, or a combination of two or more of copper, nickel, and gold, e.g., CuNiAu. Moreover, in various embodiments, each UBM has a thickness, e.g., a diameter, ranging from 3 microns to 5 microns. For example, the UBM712has a thickness of 3 microns. As another example, the UBM712has a thickness of 5 microns. In some embodiments, each UBM has a critical dimension (CD) ranging from 190 microns to 240 microns. For example, each UBM has a CD of 190 microns. As another example, each UBM has a CD of 210 microns. In various embodiments, each UBM has a nonuniformity that is between 8% and 12%. For example, each UBM has a nonuniformity that is 10%.

In various embodiments, the one or more pillars, e.g., microbumps, are fabricated from copper, or nickel, or silver, or stannum, or a combination of two or more of copper, nickel, stannum, and silver, e.g., Cu(Ni)SnAg. Moreover, in some embodiments, each pillar has a thickness ranging from 25 microns to 40 microns. For example, the pillar714has a thickness of 25 microns. As another example, the pillar714has a thickness of 40 microns. In several embodiments, each pillar has a CD ranging from 25 microns to 90 microns. For example, each pillar has a CD of 25 microns. As another example, each pillar has a CD of 90 microns. As yet another example, some pillars have a CD of 25 microns and remaining pillars have a CD of 90 microns. In some embodiments, each pillar has a nonuniformity that is between 8% and 12%. For example, each pillar has a nonuniformity that is 10%.

In various embodiments, the RDL716is fabricated from the conductive material112. Moreover, in some embodiments, the RDL716has a thickness ranging from 0.75 microns to 3 microns. For example, the RDL716has a thickness of 1 micron. As another example, the RDL716has a thickness of 2 microns. In several embodiments, the RDL716has a CD ranging from 3 microns to 5 microns. For example, the RDL716has a CD of 3 microns. As another example, the RDL716has a CD of 5 microns. In some embodiments, a distance between two adjacent RDLs, e.g., RDLs at the same level, ranges from 0.75 microns to 3 microns. For example, a distance or spacing between two adjacent RDLs at the same level is 2 microns. As another example, a distance or spacing between two adjacent RDLs at the same level is 1 micron. In various embodiments, the RDL716has a nonuniformity that is between 4% and 12%. For example, the RDL716has a nonuniformity that is 4%. As another example, the RDL716has a nonuniformity that is 10%, e.g., 10 percent of a top surface of the RDL716has nonuniformity.

In some embodiments, the one or more megapillars are fabricated from the conductive material112. Moreover, in some embodiments, the one or more megapillars has a thickness ranging from 150 microns to 200 microns. For example, the megapillar718has a thickness of 150 microns. As another example, the megapillar718has a thickness of 200 microns. In several embodiments, the megapillar718has a CD ranging from 100 microns to 200 microns. For example, the megapillar718has a CD of 100 microns. As another example, the megapillar718has a CD of 200 microns. In various embodiments, the megapillar718has a nonuniformity that is between 5% and 10%. For example, the megapillar718has a nonuniformity that is 5%.

FIG. 8is a diagram of an embodiment of the system800that includes a spinner802. The system800includes the spinner800, a host computer804, a motor806, a vacuum pump808, and a liquid storage810. The substrate102is placed on top of a support816, e.g., a metal support, a plastic support, etc., within the spinner802. The support816is connected to the motor806via one or more connection mechanisms, e.g., one or more rods, a combination of rods and gears, etc.

The motor806is coupled to the host computer804, which is coupled to the vacuum pump808and a valve812. The host computer804controls the valve812to open or close the valve812. For example, the host computer804sends a signal to a valve driver, e.g., a conductor, to generate a current, which generates an electric field to open or close the valve812. The opening of the valve allows passage of a liquid, e.g., the dielectric material deposited in the operation150(FIG. 1A), the photoresist deposited in the operation160(FIG. 1A), etc., to the spinner802to be deposited on a surface814over the substrate102of a substrate package815. For example, the liquid is deposited at or close to a center of the surface814. The substrate package815is an example of the substrate package107or the substrate package109(FIG. 1A). The surface814is an example of a top surface of the pad122(FIG. 1A, operation150) or a top surface of the barrier and seed layer123(FIG. 1A, operation160).

After depositing the liquid on the surface814, the host computer804controls the motor806to operate to rotate the support816. For example, the host computer804sends a control signal to a motor driver, e.g., one or more transistors, to generate a current signal. The current signal is sent to a rotor of the motor806to rotate the rotor with respect to a stator of the motor to rotate the support816via the connection mechanism. The rotation of the support816rotates the surface814to evenly spread the liquid on the surface814via a centrifugal force such that the liquid is deposited on the surface814.

The host computer804controls the vacuum pump808to operate to remove any excess liquid within the spinner802. For example, the host computer804sends a signal to a vacuum driver, e.g., one or more transistors, etc., to turn on the vacuum pump808to create a partial vacuum within the spinner802to remove any excess liquid from the spinner802. In some embodiments, the vacuum pump808is operated by the host computer804before the liquid is allowed to enter into the spinner802from the liquid storage810to remove any excess remnant materials from the spinner802.

FIG. 9is a diagram of an embodiment of the wafer stepper900for illustrating formation of a pattern on a dielectric layer or a photoresist layer. Examples of the dielectric layer include the dielectric layer124(FIG. 1A), the dielectric layer502(FIG. 5), and the dielectric layer602(FIG. 6). Examples of the photoresist layer include the photoresist layer108(FIG. 1A).

The wafer stepper900includes a light source902, e.g., an ultraviolet (UV) light source, an X-ray light source, etc., a lens904, a photomask906, and a projection lens908. An example of the UV light source includes a mercury-vapor lamp. The substrate102(FIG. 1A) over which one or more layers, e.g., the photoresist layer, the dielectric layer, etc., are deposited is placed on a substrate holder910within the wafer stepper900.

The light source902generates light, e.g., UV light, x-ray, etc., that passes through the lens904. The lens904directs, e.g., focuses, the light towards the photomask906. The directed light passes through areas of the photomask906that allow passage of the directed light and is incident on the projection lens908. The projection lens908directs the incident light on a portion of the layer, e.g., a dielectric layer described herein, a photoresist layer described herein, on which the pattern is to be imposed, e.g., imprinted, overlaid, etc. The light that is directed on the layer overlays the pattern on the layer deposited over the substrate102. The substrate holder910is moved in x and y directions to repeat the imposition of the pattern.

FIG. 10is a diagram of an embodiment of the immersive container1000to illustrate stripping of a dielectric layer or a photoresist layer on which the pattern is imposed. The immersive container1000is filled with a chemical solution, e.g., a developer, deionized water combined with nitrogen, deionized water, etc., to remove areas of the dielectric layer that are exposed to light or the photoresist layer that are exposed to light. If the photoresist of the photoresist layer is positive, regions of the photoresist that are exposed to the light become soluble in the developer when immersed. On the other hand, if the photoresist of the photoresist layer is negative, regions of the photoresist that are not exposed to the light become soluble in the developer when immersed. An example of photolithography is described in US Patent Application Publication No. 2008/0171292, which is incorporated by reference herein in its entirety.

FIG. 11is a diagram of an embodiment of the system1100for illustrating the PVD process. The system1100includes a radio frequency generator (RFG)1102, an impedance matching circuit (IMC)1104, a plasma chamber1106, a container1108for storage of one or more process gases, the host computer804, another RFG1112, another IMC1114, and a vacuum pump1116.

An IMC includes multiple electrical components, e.g., one or more capacitors, or one or more resistors, or one or more inductors, or a combination of one or more capacitors and one or more resistors, or a combination of one or more capacitors and one or more inductors, or a combination of one or more resistors and one or more inductors, or a combination of one or more capacitors and one or more resistors and one or more inductors. Some of the one or more electrical components are coupled with each other in a serial manner or a parallel manner.

The host computer804is a desktop computer, or a laptop computer, or a smartphone. The host computer804includes one or more processors and one or more memory devices coupled to the one or more processors. As used herein, a processor is an application specific IC, or a programmable logic device, or a microprocessor, or a central processing unit (CPU). Moreover, as used herein, a memory device is a random access memory (RAM) or a read-only memory (ROM) or a combination of RAM and ROM. The host computer804is coupled to the RFG1102via a cable, e.g., a serial data transfer cable, a parallel data transfer cable, a universal serial bus (USB) cable, etc. Similarly, the host computer804is coupled to the RFG1112via another cable, e.g., a serial data transfer cable, a parallel data transfer cable, a USB cable, etc.

The RFG1102is coupled to the IMC1104via an RF cable1126and the IMC1104is coupled to the top plate1122via an RF transmission line1128. Moreover, the RFG1112is coupled to the IMC1114via an RF cable1130and the IMC1114is coupled to the chuck1120via an RF transmission line1132.

The plasma chamber1106includes a chuck, e.g., an electrostatic chuck (ESC) on which a substrate package1124is placed, a top plate1122, and other parts (not shown), e.g., an upper dielectric ring surrounding the top plate1122, an upper electrode extension surrounding the upper dielectric ring, a lower dielectric ring surrounding a lower electrode of the chuck1120, a lower electrode extension surrounding the lower dielectric ring, an upper plasma exclusion zone (PEZ) ring, a lower PEZ ring, etc. Examples of the substrate package1124include the substrate package105(FIG. 1A), or the substrate package503(FIG. 5), or the substrate package603(FIG. 6). The top plate1122is located opposite to, on top of, and facing the chuck1120. Each of the top plate1122and the chuck1120is made of a metal, e.g., aluminum, alloy of aluminum, copper, a combination of copper and aluminum, etc. Examples of the process gases stored in the container1108include a sputtering gas, argon, etc.

The host computer804sends a signal to a valve driver, examples of which are provided above, to open a valve1124. When the valve1124is open, the process gases flow from the container1108via an inlet of the plasma chamber1106into the plasma chamber1106. Moreover, upon receiving a control signal from the host computer804via the cable, the RFG1102generates an RF signal that is supplied to the IMC1104. Upon receiving the RF signal from the RFG1102, the IMC1104matches an impedance of a load coupled to an output of the IMC1104with that of a source coupled to an input of the IMC1104to generate a modified RF signal. Examples of the load coupled to the IMC1104include the plasma chamber1106and the RF transmission line1128. Examples of the source coupled to the IMC1104include the RFG1102and the RF cable1126. The modified RF signal is sent from the IMC1104via the RF transmission line1128to the top plate1122.

Similarly, upon receiving a control signal from the host computer804via the cable, the RFG1112generates an RF signal that is supplied to the IMC1114. Upon receiving the RF signal from the RFG1112, the IMC1114matches an impedance of a load coupled to an output of the IMC1114with that of a source coupled to an input of the IMC1114to generate a modified RF signal. Examples of the load coupled to the IMC1114include the plasma chamber1106and the RF transmission line1132. Examples of the source coupled to the IMC1114include the RFG1112and the RF cable1130. The modified RF signal is sent from the IMC1114via the RF transmission line1132to the chuck1120.

The supply of the modified RF signal to the top plate1122, the modified RF signal to the chuck1120, and the process gases via the inlet to the plasma chamber1106generates plasma, such as strikes plasma, within the plasma chamber1106. The plasma includes ions of the process gases and the ions react with a layer of a target material that is attached to the top plate1122. Examples of the target material include a material of a material of the barrier layer, described herein, and a material of the copper seed layer, described herein. To illustrate, the target material is copper or titanium or tungsten or tantalum, or a combination of two or more of titanium, tungsten, and tantalum.

When the ions interact with the target material, the target material is sputtered from the layer of the target material to be deposited on top of the substrate package1124. For example, the barrier layer or the copper seed layer is formed on top of the intermediate portions124A and124B (FIG. 1A) of the patterned dielectric layer and on top of the portion156of the pad122(FIG. 1A). The vacuum pump1116is operated to create a partial vacuum within the plasma chamber1106to remove remnant materials from the plasma chamber1106.

In some embodiments, instead of sputtering the target material, the PVD process includes thermal evaporation. The thermal evaporation is a deposition technique in which a source material is heated to be vaporized. The vaporized source material is deposited on the substrate package1124.

FIG. 12is a diagram of an embodiment of the system1200for performing the operation172of photoresist stripping, the descum operation164, and the operation174of barrier and seed layer etching (FIG. 1B). The system1200includes the RFG1102, the IMC1104, the RFG1112, the host computer804, a plasma chamber1202, a container1204for storing one or more process gases, and another container1205for storing one or more etchants.

The plasma chamber1202includes a showerhead1210and the chuck1120. The showerhead1210is facing the chuck1120. The showerhead1210includes multiple holes to allow the one or more process gases stored in the container1204to be applied to a substrate package1208placed on the chuck1210. The showerhead1210also includes an upper electrode plate. In some embodiments, the upper electrode plate of the showerhead1210is made from aluminum, or an alloy of aluminum, or copper, or a combination of copper and aluminum, etc.

To etch the copper seed layer, an etchant, e.g., the copper etchant, an acid, etc., is supplied from the container1205via a valve1207to the showerhead1210. The host computer804controls the valve1207via a valve driver, described above, to open the valve1207. The etchant is supplied via the showerhead1210to the substrate package1208to etch away the copper seed layer. Similarly, to etch the barrier layer, a barrier etchant, e.g., an acid, etc., is supplied from the container1205via the valve1207to the showerhead1210. The barrier etchant when applied to the substrate package1208etches away the barrier layer.

During the photoresist stripping operation172(FIG. 1B) or the descum operation164, the host computer804sends a signal via a valve driver, which is described above, to open a valve1206. When the valve1206is open, one or more process gases, e.g., carbon dioxide, oxygen, an etchant gas, etc., stored within the container1204are supplied. Moreover, the modified RF signal is supplied via the RF transmission line1132to the chuck1120. Also, the modified RF signal is supplied via the RF transmission line1128to the upper electrode plate of the showerhead1210.

When the modified signals are supplied to the showerhead1210and to the chuck1120, the one or more process gases supplied to the plasma chamber1202are ignited to strike plasma within the plasma chamber1202. The plasma performs the photoresist stripping operation172or the descum operation164on the substrate package1208. To illustrate, when the one or more process gases include carbon dioxide or an etchant gas, the photoresist stripping operation172is performed. As another illustration, when the one or more process gases include oxygen or an etchant gas, the descum operation164is performed.

It should be noted in some embodiments, an RFG other than the RFG1102, an RF cable other than the RF cable1126, an IMC other than the IMC1104, an RF transmission line other than the RF transmission line1128, an RFG other than the RFG1112, an RF cable other than the RF cable1130, an IMC other than the IMC1114, and an RF transmission line other than the RF transmission line1132is used in the system1200.

It should further be noted that the substrate package1208is an example of the substrate package135(FIG. 1B) when the descum operation164is performed on the substrate package1208. Moreover, the substrate package1208is an example of the substrate package137(FIG. 1B) when the photoresist stripping operation172is performed on the substrate package1208. Also, the substrate package1208is an example of the substrate package139(FIG. 1B) when the barrier and copper seed etch operation174is performed on the substrate package1208.

In some embodiments, the operation172of photoresist stripping and the operation174of barrier and seed layer etching are quite often performed in one and the same process tool, e.g., a process tool other than the system1200, and the descum operation164is performed using the system1200. Furthermore, a solvent-based wet chemistry is applied within the process tool for performing the operation172of photoresist stripping with a single wafer spray system. Likewise, a copper etchant, e.g., a dilute piranha solution, etc., is dispensed via the single wafer spray system over the substrate102to etch a copper seed layer, described herein.

FIG. 13Ais a diagram of an embodiment of a system1300for illustrating the pre-treatment operation166(FIG. 1B). The system1300includes a chamber1302, a motor1304, and a container1306. The motor1304is coupled to the wafer holder1308via one or more connection mechanisms, which are described above. The wafer holder1308holds a substrate package1312. The substrate package1312is an example of the substrate package135(FIG. 1B) on which the descum operation164has been performed and the pre-treatment operation166is to be performed.

The host computer804sends a signal to a valve driver, described above, to further open a valve1310. When the valve1310is open, a pre-wet fluid, e.g., water, a water-miscible solvent, a chemistry solution, deionized water, a combination of deionized water and the chemistry solution, etc., from the container1306flows into the chamber1302. Moreover, the host computer804sends a signal to a motor driver, described above, to operate the motor1304. The motor1304operates, e.g., rotates, etc., to lower a position of the wafer holder1308to enable the substrate package1312to be immersed into the pre-wet fluid in the chamber1302.

Once the substrate package1312is pre-wetted, the motor1304is operated to raise the wafer holder1312to remove the substrate package1312from being immersed in the pre-wetting fluid. The motor1304is further operated to rotate the wafer holder1312to remove the pre-wetting fluid from a surface of the substrate package1312. Before, during, or after the pre-treatment operation166, the vacuum pump1116is operated to remove any undesirable remnant materials, e.g., the pre-wetting fluid, from a surface of the substrate package1312, etc., from the chamber1302.

FIG. 13Bis a diagram of an embodiment of a system1320for illustrating the pre-treatment operation166(FIG. 1B). The system1320includes a chamber1322, the motor1304, and the container1306. The motor1304is coupled to a chuck1324via one or more connection mechanisms, which are described above. The chuck1324holds a substrate package1312. For example, the chuck1324has arms orientated at equal angles, e.g., 120 degrees, around a circumference of the substrate package1312to hold the substrate package1312.

The host computer804sends a signal to a valve driver, described above, to open the valve1310. When the valve1310is open, the pre-wet fluid from the container1306is dispensed or sprayed into the chamber1322on top of the substrate package1312.

Moreover, the host computer804sends a signal to a motor driver, described above, to operate the motor1304. The motor1304operates, e.g., rotates, etc., to rotate the substrate package1312while the substrate package1312is being held by the chuck1324and while the pre-wet fluid is being applied to the substrate package1312. The substrate package1312is being held to reduce chances of slipping or moving of the substrate package1312. In some embodiments, the motor1304is not being operated while the pre-wet fluid is being applied to the substrate package1312.

Once the substrate package1312is pre-wetted, the motor1304is operated to rotate the chuck1324to remove the pre-wetting fluid from the surface of the substrate package1312to be collected at a bottom of the chamber1324. Before, during, or after the pre-treatment operation166, the vacuum pump1116is operated to remove the undesirable remnant materials from the chamber1324.

FIG. 14Ais a diagram of an embodiment of a system1400for illustrating the electrodeposition operation168(FIG. 1B). The system1400includes the host computer804, a rotatable spindle1418, a chamber1420, a container1422for storing the catholyte, and a pump1424. Examples of the catholyte include a liquid made of the conductive material112, e.g., copper, or cobalt, or copper sulfate, or invar, or a combination of two or more of cobalt, invar, copper sulfate, and copper. In some embodiments, the catholyte includes the liquid made of the conductive material and further includes a combination of one or more accelerators and one or more levelers. In various embodiments, the catholyte includes the liquid made of the conductive material and further includes a combination of one or more accelerators and one or more suppressors. In several embodiments, the catholyte includes the liquid made of the conductive material and further includes a combination of one or more accelerators and one or more suppressors and one or more levelers. An accelerator accelerates filling of the conductive material112within a via, e.g., the via106(FIG. 1A), the via504(FIG. 5), the via604(FIG. 6), etc., to overfill the via to form a bump, e.g., the bump114(FIG. 1B). The suppressor suppresses, e.g., reduces acceleration, decelerates, etc., of filling of the conductive material112in portions of the via, e.g., the via106(FIG. 1A), the via504(FIG. 5), the via604(FIG. 6), etc. To illustrate, when the conductive material112is to be filled primarily at a bottom surface of the via, e.g., the via106, or the via504or the via604, etc., the suppressor suppresses the filing of the conductive material112at side surfaces of the via. The side surfaces are adjacent to the bottom surface and are angled, e.g., slanted, positively sloped, negatively sloped, etc., with respect to the bottom surface. The leveler levels the conductive material112to form a leveled layer, e.g., the leveled layer LL1, the leveled layer LL2(FIG. 1B), etc., of the conductive material112on top of another layer, e.g., the portion132A of the barrier and seed layer123, the portion132B of the barrier and seed layer123(FIG. 1B), etc. In some embodiments, the catholyte is a plating chemistry that includes the liquid made of the conductive material and further includes additives, e.g., a combination of an accelerator, a suppressor, and a leveler.

A substrate package1404is held, positioned, and rotated by a wafer holder1406of the chamber1420. The chamber1420includes a plating cell1408, which is dual chamber cell having an anode chamber with, for example, a counter electrode1409, e.g., a copper electrode, etc., and anolyte. The anode chamber and cathode chamber are separated by, for example, a membrane1410, e.g., a cationic membrane, which is used for electrodeposition and is supported by a support member1412. The system1400further includes a channeled ionically resistive plate (CIRP)1414. A flow diverter1416is on top of the CIRP1414, and aides in creating a transverse shear flow of the catholyte. The catholyte is introduced from the container1422via flow ports1433above the cationic membrane1410. From the flow port1433, the catholyte passes through the CIRP1414and produces impinging flow onto a surface, e.g., on top of the portions132A and132B of the barrier and seed layer123(FIG. 1B) and on top of the portion130of the barrier and seed layer123(FIG. 1B), etc., of the substrate package1404to overfill the via106to create the bump114and to deposit the conductive material112on the portions132A and132B to create the leveled layers LL1and LL2. Moreover, the catholyte is introduced from the container1422via the pump1424into a flow port1430, which is located at a side1402of the chamber1420. For example, an inlet of the flow port1430is located below the anode1408. In this example, the flow port1430is a channel in a side wall1432of the plating cell1408. The functional result is that catholyte flow is introduced directly into a plating region formed between the CIRP1414and the substrate package1404to enhance the transverse shear flow across the substrate package1404as shown by a direction1407of the arrow inFIG. 14A. For example, the transverse shear flow is in the direction1407that is parallel to the top surface120of the leveled layers LL1and LL2. The transverse shear flow is applied between the adjacent areas A1and A2to create the bump114between the leveled layers LL1and LL2.

Moreover, when the catholyte having the conductive material112and a combination of two or more of an accelerator, a suppressor, and a leveler is introduced into the chamber1420on the substrate package1404, the host computer804controls a direct current (DC) power source1434of the system1400to supply DC power to the counter electrode1409and to the wafer holder1406. The wafer holder1406is positively charged by the DC power to serve as a cathode and the counter electrode1409is negatively charged by the DC power to serve as an anode to enable electrodeposition of ions of the catholyte onto the substrate package1404. In some embodiments, for the electrodeposition operation168, the wafer holder1406and the substrate package1404serve as the cathode and involve the reduction of Cu2+→Cu, while the anode is oxidized from Cu→Cu2+. In these embodiments, the anode includes copper.

FIG. 14Bis a diagram of an embodiment of the system1401to illustrate the electropolishing operation170(FIG. 1B). The system1401is similar in structure and components to the system1400(FIG. 14A) except that the system1401includes a chamber1421and a container1423. The chamber1421is similar in structure and components to the chamber1420(FIG. 14A) except that the chamber1421includes a counter electrode1411. When an acid, e.g., phosphoric acid, hydrochloric acid, sulfuric acid, etc., is stored inside a container1423and is used instead of the catholyte and is introduced into the chamber1421on the substrate package1404, the host computer804controls the DC power source1434of the system1401to supply DC power to the counter electrode1411and to the wafer holder1406. The wafer holder1406is negatively charged by the DC power to serve as an anode and the counter electrode1411is positively charged by the DC power to serve as a cathode to enable electropolishing of bumps, such as the bump114, of the substrate package1404. The anodic reaction is of Cu→Cu2+ and the cathode reaction includes 2H+→H2. The cathode is fabricated from an inert material, such as, e.g., titanium, or platinum, or iridium, or a combination of two or more thereof.

The flow diverter1416is on top of the CIRP1414, and aides in creating a transverse shear flow of the acid. The acid is introduced from the container1422via flow ports1433above the membrane1410. From the flow port1433, the acid passes through the CIRP1414and produces impinging flow onto a surface, e.g., on top of the bump114, of the substrate package1404to remove the bump114to create the top surface120(FIG. 1B) of the RDL layer104. Moreover, the acid is introduced from the container1423via the pump1424into the flow port1430. The functional result is that the acid flow is introduced directly into a region formed between the CIRP1414and the substrate package1404to enhance the transverse shear flow across the substrate package1404as shown by the direction1407of the arrow inFIG. 14B. The transverse shear flow is applied between the adjacent areas A1and A2to the bump114between the leveled layers LL1and LL2to remove the bump114to further create the leveled area LL3.

It should be noted that the substrate package1404is an example of the substrate package135when the electrodeposition operation168(FIG. 1B) is to be performed on the substrate package1404. Moreover, it should be noted that the substrate package1404is an example of the substrate package141(FIG. 1B) when the electropolishing operation170(FIG. 1B) is to be performed on the substrate package1404.

Embodiments described herein may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

In some embodiments, a controller is part of a system, which may be part of the above-described examples. Such systems include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a system.

Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access of the wafer processing. The computer enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

In some embodiments, a remote computer (e.g. a server) provides process recipes to a system over a network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters are specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

It is further noted that in some embodiments, the above-described operations apply to several types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma chamber, a capacitively coupled plasma reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, one or more RF generators are coupled to an inductor within the ICP reactor. Examples of a shape of the inductor include a solenoid, a dome-shaped coil, a flat-shaped coil, etc.

With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are those physically manipulating physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over the computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

One or more embodiments can also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter be read by a computer system. Examples of the non-transitory computer-readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

Although the method operations above were described in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.