Slave device enhancing data rate of DSI3 bus

Disclosed DSI3 slave devices may enhance the data rate of the DSI3 bus using modified nibble encoding, pulse shaping, spectral shaping, and/or message preambles to provide chip time and level tracking. In one embodiment, there is provided a communications method that includes: converting a binary data stream into a ternary unipolar non-return-to-zero level channel signal; and driving the channel signal as an electrical current on a signal conductor. The converting uses an encoder that maps binary nibbles to a set of ternary triplets, each triplet in the set having an average level between 2/3 and 4/3 inclusive, and each triplet including at least one internal transition between levels.

BACKGROUND

Current and future vehicles are incorporating increasing numbers of on-board sensors and systems to enable or aid critical vehicle functions including Adaptive Cruise Control (ACC), Parking Assistance, Forward Collision Warning (FCW), Forward Collision with Active Braking, Blind Spot Warning (BSW), Lane Keeping Systems (LKS), and others. These technologies provide direct driver assistance in normal driving and critical scenarios, and some are even capable of enhancing driver control or providing autonomous control to prevent or mitigate a crash or negative outcome.

To accommodate the many sensors, actuators, and control systems being employed for such features, manufacturers are implementing increasingly sophisticated data communication networks in each vehicle. The 3rd generation Distributed System Interface (DSI3) standard published by the DSI Consortium (dsiconsortium.org) provides one example of such a communication network.

DSI3 and other communication standards must contend with a unique set of circumstances that challenge their performance. The networks are portable, battery powered (i.e., low voltage), with wire runs long enough to cause (and be susceptible to) electromagnetic interference (EMI). The networks should be resistant to vibration effects, yet remain inexpensive and easy to repair. The DSI3 standard has thrived by offering a number of desirable features including single-conductor communication with optionally integrated power delivery. However, the signal conductor is unshielded and carries a single-ended (as opposed to differential) unipolar signal. Attempts to increase the rate of data communication across the DSI3 bus's single signal conductor are being impaired by the industry's strict limits on EMI emissions.

SUMMARY

Accordingly, there are disclosed herein slave devices that enhance the data rate of the DSI3 bus using modified nibble encoding, pulse shaping, spectral shaping, and/or message preambles to provide chip time and level tracking. In one embodiment, there is provided a communications method that includes: converting a binary data stream into a ternary unipolar non-return-to-zero level channel signal; and driving the channel signal as an electrical current on a signal conductor. The converting uses an encoder that maps binary nibbles to a set of ternary triplets, each triplet in the set having an average level between 2/3 and 4/3 inclusive, and each triplet including at least one internal transition between levels.

In another embodiment, there is provided a slave device that couples to a DSI3 (3rd generation distributed system interface) bus. The slave device includes an encoder that converts a binary data stream into a ternary unipolar non-return-to-zero level data stream; an analog-to-digital converter coupled to the encoder to generate a channel signal that conveys the ternary unipolar non-return-to-zero level data stream; and a driver that drives the channel signal as an electrical current on a signal conductor of the DSI3 bus. The encoder operates by mapping binary nibbles to a set of ternary triplets, each triplet in the set having an average level between 2/3 and 4/3 inclusive, and each triplet including at least one internal transition between levels.

In yet another embodiment, there is provided a method of manufacturing a slave device that couples to an DSI3 (3rd generation distributed system interface) bus. The method includes: creating an encoder to convert a binary data stream into a ternary unipolar non-return-to-zero level data stream; coupling the encoder to an analog-to-digital converter to generate a channel signal that conveys the ternary unipolar non-return-to-zero level data stream; and providing a driver to drive the channel signal as an electrical current on a signal conductor of the DSI3 bus. The encoder is configured to map binary nibbles to a set of ternary triplets, each triplet in the set having an average level between 2/3 and 4/3 inclusive, and each triplet including at least one internal transition between levels.

Each of the foregoing embodiments may be employed separately or conjointly, and may optionally include one or more of the following features in any suitable combination: 1. the signal conductor is a Distributed System Interface (DSI) coupling an automotive sensor to an electronic control unit (ECU). 2. the channel signal conveys contents of the data stream to the ECU at more than 400 kbps. 3. said converting includes filtering a stream of ternary triplets from the encoder using a pulse-shaping filter, the pulse-shaping filter being one of: a sinc filter, a Hann filter, a Hamming filter, a Blackman filter, and a Nuttall filter. 4. said driving includes applying a transmit correction filter to the channel signal to attenuate high-frequency components of the channel signal. 5. the signal conductor couples the channel signal to a receiver having a receive correction filter, the receive correction filter boosting said high-frequency components to compensate for effects of the transmit correction filter. 6. said binary data stream is generated using a scrambling mask. 7. said binary data stream is framed into fixed length messages, each message being preceded by a synchronization preamble. 8. the slave device is an automotive sensor that generates the binary data stream to convey measurements to a electronic control unit (ECU).

DETAILED DESCRIPTION

The attached drawings and following description set out particular embodiments and details for explanatory purposes, but It should be understood that the drawings and corresponding detailed description do not limit the disclosure. On the contrary, they provide a foundation that, together with the understanding of one of ordinary skill in the art, discloses and enables all modifications, equivalents, and alternatives falling within the scope of the appended claims.

FIG. 1shows an electronic control unit (ECU)102coupled to the various ultrasonic sensors104and a radar array controller106as the center of a star topology. Of course, other topologies including serial, parallel, and hierarchical (tree) topologies, are also suitable and contemplated for use in accordance with the principles disclosed herein. The radar array controller106couples to the transmit and receive antennas in the radar antenna array to transmit electromagnetic waves, receive reflections, and determine a spatial relationship of the vehicle to its surroundings. To provide automated parking, assisted parking, lane-change assistance, obstacle and blind-spot detection, autonomous driving, and other desirable features, the ECU102may further connect to a set of actuators such as a turn-signal actuator108, a steering actuator110, a braking actuator112, and throttle actuator114. ECU102may further couple to a user-interactive interface116to accept user input and provide a display of the various measurements and system status.

Various standards exist to support communications between the ECU102and the various sensors and actuators. Of particular interest with respect to the present disclosure is the 3rd generation Distributed System Interface (DSI3) bus standard, which provides for half-duplex single-ended signal communication between a bus master device (typically the ECU) and one or more slave devices (e.g., the sensors and actuators). Because the DSI3 bus requires only one signal conductor, it may at times be referred to as a “one-wire” bus.

FIG. 2Ais a block diagram of an illustrative slave device200suitable for use on a standard DSI3 bus. While maintaining physical compatibility with the DSI3 standard, the illustrative device200includes certain features to enhance communications performance, at least some of which extend the standard in a way that may necessitate a firmware adjustment in the bus master device as discussed further below. Other features can be employed to enhance performance without departing from full compatibility with the existing standard. The disclosed features, which can be employed individually or in various combinations, include: (1) pulse shaping, (2) spectral shaping, (3) scrambling, and (4) modified nibble encoding.

Slave device200includes a controller202that collects measurements and buffers relevant messages in memory204for communicating the measurement data to the bus master device. While the message length can be varied, in at least one contemplated embodiment each message is 16 bytes and may begin with or be preceded by a preamble that is one or two nibbles in length. A scrambler206masks each message with a pseudorandom binary sequence using a bitwise exclusive-or (XOR) operation to randomize or “whiten” any repeating data patterns. If present, the preamble is not masked, so as to preserve the preamble pattern in the scrambler's output bitstream. The seed for the pseudorandom sequence may vary for each message and may vary for each slave device.

A channel encoder208encodes the bitstream from the scrambler206by mapping each nibble to a corresponding triplet of channel symbols. Each triplet includes three ternary channel symbols. Channel symbols are also referred to herein as “chips” and are transmitted as one of three unipolar non-return-to-zero levels: 0, 1, or 2, each symbol having a fixed symbol duration which may be about 3 or 4 microseconds. As provided in the standard, “0” may correspond to a quiescent channel signal current of IQ. A “1” may correspond to a response channel signal current of IQ+IRESP, and a “2” may correspond to a response channel signal current of IQ+2IRESP. In at least some embodiments, IQis limited to no more than 2 mA, and IRESPis approximately 12 mA. Some contemplated embodiments may switch from three-level signaling to two level signaling to improve noise immunity. In such embodiments, the channel encoder208maps 8-bit bytes to 8-bit codewords, in this case only IQand IQ+2IRESPcurrent levels are used.

A pulse-shaping filter210may operate on the channel symbol stream from the encoder208, providing a transfer function that converts rectangular pulses (e.g., NRZ chips) into smoother pulse shapes that provide the channel signal with more desirable spectral properties. One contemplated embodiment of the pulse-shaping filter210is a sinc filter such as that shown inFIG. 6. Filters that provide pulse shapes with raised-cosine roll-offs are also contemplated. More specifically, the contemplated pulse shaping filter types include a Hann filter, a Hamming filter, a Blackman filter, and a Nuttall filter. A digital-to-analog converter212operates on the filtered channel signal to convert it from digital form to analog form, which herein may be termed the uplink channel signal. A transmit correction filter214may operate on the uplink channel signal to further shape the channel signal spectrum as discussed further below with respect toFIGS. 3, 4A, and 4B. To be clear, the transmit correction filter214can be omitted, combined with the pulse shaping filter210, implemented as a separate digital filter, or implemented as shown (a separate analog filter).

A channel driver216converts the uplink channel signal into an electrical current on an input/output pin of the slave device200. A low pass RC filter (capacitor C3, resistor R3) couples the input/output pin to the signal conductor of the DSI3 bus.

Current biasing of the input/output pin is provided by a current sink218and a receive buffer220. Controller202adjusts the current sink218as needed for biasing during the forward (downlink) and reverse (uplink) communication phases of the half-duplex DSI3 communication protocol. During the downlink communication phase, the input/output pin receives a downlink channel signal in the form of an electrical voltage signal. Receive buffer220provides a high input impedance for the input/output pin, buffering the downlink channel signal for the analog-to-digital converter224.

A downlink receive filter225may limit the digital receive signal bandwidth and/or enhance signal to noise ratio of the downlink signal. In at least some embodiments, the filter225operates to suppress noise above 300 kHz. In system embodiments where the master device employs a transmit correction filter (similar to filter214above), the downlink receive filter225may include a compensation function to boost downlink signal frequencies up to about 150 kHz, before rolling off to suppress noise at signal frequencies above about 250 or 300 kHz.

A symbol detector and decoder226operates on the filtered receive signal to determine the command type and associated payload, placing the information in the receive buffer for the controller202to use when formulating a response.

FIG. 2Ashows both a pulse-shaping filter210and a transmit correction filter214. Either or both of these filters may be omitted. The filter order can also be interchanged, with the digital-to-analog conversion occurring before, between, or after the filtering operations.

FIG. 2Bis a block diagram of an illustrative bus master device240suitable for use on a standard DSI3 bus. As with the slave device200, the master device240maintains physical compatibility with the DSI3 standard, but includes certain features to enhance uplink communication performance when employed in conjunction with a compatible slave device.

Master device240includes a controller242that formulates downlink messages in memory244for communication to one or more slave devices. A channel encoder246encodes the binary downlink messages by mapping bits 0 and 1 to upward and downward channel voltage transitions as provided by, e.g., Manchester-1 encoding. A digital-to-analog converter248converts the encoded signal into an analog downlink signal. A driver249supplies the analog downlink signal as a voltage signal to an input/output pin of the master device240. Though the DSI3 standard provides for a 2 volt swing between “high” and “low” symbol voltages, some contemplated embodiments employ a 4 volt swing to enhance noise immunity. A low pass RC filter (capacitor C1, resistor R1) couples the input/output pin to the signal conductor of the DSI3 bus.

A high impedance receive buffer250couples the uplink signal from the input/output pin to an optional receive correction filter251. The optional receive correction filter251may, e.g., boost high frequency content of the uplink signal to compensate for operation of the transmit correction filter214. An analog to digital converter252digitizes the uplink signal, and an uplink receive filter253operates on the digital signal to limit signal bandwidth and/or enhance signal-to-noise ratio. Filter253may be a matched filter, having a filter response based at least in part on the pulse shape provided by the pulse shaping filter210. Filters251and253can be re-ordered, merged into a single filter, and each implemented in digital or analog form.

A chip detector254operates on the filtered uplink signal to detect channel symbol levels. A threshold capture unit255may capture and/or adapt comparator threshold levels for the chip detector254based at least in part on the message preambles as discussed further below. A decoder256operates on the channel symbol sequence from the chip detector254, inverting the operation of encoder208to map the chip triplets to binary nibbles. A descrambler257operates on the bitstream from the decoder256, inverting the operation of the scrambler206to extract the message data sent by the slave device. The message data may be stored in memory244for analysis and use by controller242.

The illustrative slave device illustrated inFIG. 2Aemploys a channel driver216and receive buffer220that operates with reference to ground. We observe here that the ground node can drift with respect to the ground used by the master device, typically in a symmetric fashion with the drift experienced by the voltage supply nodes of the master and slave devices. (The symmetry is a result of the power supply conductor impedances on the DSI3 bus.) Consequently, a greater degree of noise immunity can be achieved if, rather than using the ground node as a reference for signal transmission and reception, the slave and master devices use a half-voltage reference. That is, the master device splits the difference between its supply voltage and ground voltage to determine the reference voltage for transmitting the downlink signal, and the slave device splits the difference between its supply voltage and ground voltage to determine the reference voltage for receiving the downlink signal. Accordingly, at least some contemplated embodiments of the slave and master devices use a half-voltage node as the reference voltage for sending and receiving signals on the DSI3 bus.

FIG. 3is a schematic illustrating the operation of, and relationship between, transmit correction filter214and receive correction filter251. In the illustrative implementation ofFIG. 3, transmit correction filter214employs a low pass RC filter configuration (R11and C12, with capacitor C12having a series resistance R12) to provide 6 dB of attenuation for signal frequencies above about 200 kHz as shown inFIG. 4A. Transmit correction filter214is employed on the transmit side to facilitate channel signal compliance with industry-specified EMC (electromagnetic compatibility) limitations. At the receive side, a receive buffer D2supplies the channel signal to a receive correction filter251. The receive correction filter employs an RC shunt (R13and C13), with an amplifier A1coupled across the resistance R13to measure and amplify the high frequency signal components. A summer51adds the amplifier output to the receive signal to boost the high frequency signal content in a way that compensates for the operation of the transmit correction filter. Thus, as shown inFIG. 4B, signal frequencies above about 200 kHz are boosted by 6 dB of gain.

To further illustrate the correction filter operations,FIG. 5Ashows an illustrative transmit signal TX generated by spaced-apart one-byte (two-triplet) messages. (In practice, uplink messages would generally be longer.) Transmit correction filter214attenuates the high frequency signal components of the transmit signal, yielding the line signal LN shown inFIG. 5B. At the receiver, the receive correction filter251restores the high frequency components, yielding the receive signal RX shown inFIG. 5C. It can be seen thatFIG. 5Cvery closely resemblesFIG. 5A.

In the presence of channel noise, the receive correction filter251may have the undesired effect of boosting the noise and thereby reducing the signal to noise ratio of the receive signal. Such boosting can be limited, or avoided, by using the pulse shaping filter to limit the high frequency content of the transmit signal in the first place, relaxing or eliminating the need for high frequency attenuation by the transmit correction filter. For example,FIG. 6is a graph of coefficient values suitable for a pulse shaping filter210. By softening the transitions of a traditional rectangular pulse, the pulse shaping filter reduces the high frequency content of the channel signal.

Scrambling and coding can be used to provide further control of the channel signal spectrum.FIG. 7compares spectra of channel signals under three different conditions. An illustrative channel signal transmitted with a chip duration of 3 microseconds by a slave device lacking any measures to limit electromagnetic interference has a spectrum given by the first curve labeled “444 kbps”. This spectrum has particularly strong harmonics, with first harmonic peak at about 110 kHz having the same magnitude as the baseband peak.

If the slave device applies a scrambling mask to whiten the bitstream before transmission, the spectrum is given by the second curve labeled “Scramble”. Scrambling reduces the magnitude of the first harmonic peak by 11.6 dB relative to the baseband peak. While this improvement is substantial, the harmonic energy remains undesirably high and may not satisfy the industry's electromagnetic compatibility requirements.

Before discussing the final curve inFIG. 7, we turn toFIGS. 8A and 8B.FIG. 8Ais a table of the encoder map from the 16 possible 4-bit nibbles to respective triplets of ternary channel symbols. We note that there are 27 possible triplets of ternary symbols. In designing this encoder map, the DSI3 standard discarded some of the possible triplets. In particular, the triplets that begin with “0” are discarded, leaving 18 possible triplets. Of these, the standard also discards those triplets having the same value for all three chips in order to guarantee at least one transition in each triplet. The 16 remaining triplets are those used in the table.

The table ofFIG. 8Afurther includes a row sum (RS) for each ternary triplet and a column sum (CS) for each chip in the triplets. We note that the column sum for the first chip is 60% larger than the other column sums. Consequently the signal energy in a sequence of triplets gets unevenly distributed among the chips, being preferentially concentrated in the first chip and thereby producing a strong harmonic at 110 kHz.

FIG. 8Bis a table of a modified encoder map which provides a greater balance of signal energy among the chips and reduces variation of the row sums relative to the table ofFIG. 8A. As withFIG. 8A, each of the triplets inFIG. 8Bincludes at least one internal transition between chip values. Using this modified code in combination with the scrambling mask, the slave device produces a channel signal having the spectrum given by the third curve labeled “M.Code” inFIG. 7. The harmonic peak at 110 kHz is suppressed 22 dB relative to the baseband peak. Accordingly, the use of a modified code is expected to significantly aid in meeting the industry's electromagnetic compatibility requirements.

Though harmonic peaks are still evident at, e.g., 330 kHz, 440 kHz, and 660 kHz, the use of a pulse shaping filter and/or spectral shaping filter is expected to suppress these peaks.

With the use of the modified code, it is noted that some of the triplets now begin with “0”. To assure that messages are detected when they start, slave devices may prepend a preamble to each message to guarantee that the first chip is nonzero. The preamble may further be chosen to provide timing synchronization and decision threshold training as described below.

FIG. 9shows an illustrative message template for use by the slave device. The template begins after an idle period90in which, e.g., a downlink message is detected. As the slave device transitions to a transmit mode, there is a “Fade in” interval91during which the slave device begins sourcing an electrical current corresponding to a “0” signal level for at least the duration of one chip. A preamble92indicates the beginning of a message. The illustrated preamble is a 2-0-2 triplet. In another contemplated embodiment, the preamble is a 2-0-2 triplet followed by a 0-2-0 triplet. Other preambles would also be suitable, including a single chip having a nonzero value.

The message93is a sequence of triplets from the modified encoder map (FIG. 8B). In at least one embodiment, the message93consists of 32 triplets to convey 16 bytes of binary message data. The message93is followed by a fade out interval94during which the slave device transitions out of the transmit mode. The slave device begins listening again during the subsequent idle period95.

The preamble can be used to capture and/or train the threshold values used by the chip detector254.FIGS. 10A-10Bshow illustrative embodiments of a threshold capture unit255that determines the threshold values using the 2-0-2 preamble.

InFIG. 10A, an illustrative chip detection unit254includes a first comparator401and a second comparator402. Comparator401compares the receive signal RX to a low threshold TL, providing an output signal C1that is asserted if the RX signal is above TL and deasserted if RX is below TL. Similarly, comparator402compares the receive signal RX to a high threshold TH, providing an output signal C2that is asserted if RX is above TH and deasserted if RX is below TH. The threshold TL is set midway between the current levels corresponding to 0 and 1, while TH is set midway between the current levels corresponding to 1 and 2. Thus C1and C2are both deasserted when the RX signal corresponds to the 0 current level. C1is asserted and C2deasserted when the RX signal corresponds to the 1 current level. Both C1and C2are asserted when the RX signal corresponds to the 2 current level.

As the slave device enters the transmit mode, a synchronization detector410monitors the RX signal to detect the preamble. In at least some contemplated embodiments, the sync detector410detects the RX signal exceeding a predetermined threshold and remaining above that predetermined threshold for at predetermined duration. For example, the predetermined threshold may roughly correspond to a “1” current level and the predetermined duration may correspond to half of a chip interval. Upon detecting the preamble, the sync detector may provide rising clock edges for latches411and412at suitable delays with respect to the detection. The clock for latch411may be triggered immediately upon detection or at two chip durations after the detection, while the clock for latch412may be triggered at one chip duration after the detection. In either case, latch411captures an RX signal value corresponding to a “2” while latch412captures an RX signal value corresponding to a “0”.

The captured RX signal values are added by a summer413to obtain their sum, and subtracted by a summer414to determine their difference. A divider415then determines their average (which corresponds to a “1”), while a second divider416divides the difference by 4 (which corresponds to a threshold offset of “0.5”). Summer417adds the offset to the average to obtain the high threshold TH. Summer418subtracts the offset from the average to obtain the low threshold TL. The threshold capture unit then provides the TH and TL values to the chip detector254for detecting the chip values of the ensuing message.

FIG. 10Bemploys a similar threshold determination method, but rather than relying on a preamble detector419, the illustrated unit255initially uses default threshold values TH, TL to detect the chip values. During a sampling period, i.e., when the SAMPLE signal is asserted, the AND gate422triggers a clock signal for a filter423when the chip detector detects a “0” chip value. AND gate424triggers a clock signal for a filter423when the chip detector detects a “2” chip value. Filters423,425combine values of the corresponding chip values within the sample window to provide a filtered “0” and “2” value, which the components413-418use to determine the TH and TL values as described previously. After a predetermined time, or once the TH and TL values converge, the SAMPLE signal is deasserted.

The unit255ofFIG. 10Cincludes AND gates422,424which supply clock signals to filters423,425when “0” and “2” chip values are detected during the sampling period. In addition, an AND gate432triggers a clock signal to a filter433when a “1” chip value is detected during the sampling period. A summer434sums the filtered “1” and “2” chip values, and a divider436calculates the average for use as high threshold TH. Another summer435sums the filtered “0” and “1” values, and a divider437calculates the average for use as a low threshold TL.

Though it is contemplated that the sampling will be done only during preambles, some contemplated embodiments employ adaptive threshold tracking continuously during communications. Different threshold values may be tracked for each slave device connected to the bus master device. These and numerous other modifications, equivalents, and alternatives, will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such modifications, equivalents, and alternatives where applicable.