Broadband power transistor devices and amplifiers with input-side harmonic termination circuits and methods of manufacture

Embodiments of RF amplifiers and RF amplifier devices include a transistor, a multiple-section bandpass filter circuit, and a harmonic termination circuit. The bandpass filter circuit includes a first connection node coupled to the amplifier input, a first inductive element coupled between the first connection node and a ground reference node, a first capacitance coupled between the first connection node and a second connection node, a second capacitance coupled between the second connection node and the ground reference node, and a second inductive element coupled between the second connection node and the transistor input. The harmonic termination circuit includes a third inductive element and a third capacitance connected in series between the transistor input and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the RF amplifier.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to radio frequency (RF) amplifiers, and more particularly to broadband power transistor devices and amplifiers, and methods of manufacturing such devices and amplifiers.

BACKGROUND

Wireless communication systems employ power amplifiers for increasing the power of radio frequency (RF) signals. In a cellular base station, for example, a Doherty power amplifier may form a portion of the last amplification stage in a transmission chain before provision of the amplified signal to an antenna for radiation over the air interface. High gain, high linearity, stability, and a high level of power-added efficiency are characteristics of a desirable power amplifier in such a wireless communication system.

In the field of power amplifier device design, it is becoming increasingly desirable to achieve concurrent multi-band, broadband amplification. To successfully design a wideband power amplifier device for concurrent multi-band, broadband operation in a Doherty power amplifier circuit, for example, it is desirable to enable a good broadband fundamental match (e.g., over 20 percent fractional bandwidth) to appropriately handle harmonic frequency interactions, and to enable a wide video bandwidth. However, achieving these goals continues to provide challenges to power amplifier device designers.

DETAILED DESCRIPTION

In the field of high-power radio frequency (RF) power amplification for cellular base stations and other applications, broadband power amplification using silicon-based devices (e.g., laterally diffused metal oxide semiconductor (LDMOS) power transistor devices with output matching networks) has been successfully achieved. However, such silicon-based devices exhibit relatively low efficiencies and power densities when compared with the efficiencies and power densities of gallium nitride (GaN)-based power amplifier devices. Accordingly, GaN-based power amplifier devices have been increasingly considered for high power broadband applications. However, there are challenges to using GaN technology to achieve broadband power amplification (e.g., over 20 percent fractional bandwidth).

For example, the nonlinear input capacitance of RF power devices that include GaN transistors are known to generate harmonics and intermodulation distortion that can impair efficiency and linearity. Second harmonic terminations also play an important role in the overall performance of a power amplifier design that uses GaN-based transistors. Without the information of second harmonic impedance at the current source terminal plane, it is very difficult to tune a power amplifier to achieve relatively high fractional bandwidth with good performance. Furthermore, the second harmonic termination may vary significantly across a large bandwidth for broadband applications, which further increases the difficulty of circuit tuning.

To overcome these and other challenges in designing broadband power amplifiers using GaN-based devices, embodiments disclosed herein may achieve broadband input impedance matching at fundamental frequency using a multiple-section (e.g., two-section) bandpass filter topology. An input-side harmonic termination circuit is added close to the gate terminal using a bondwire connection and an RF capacitor. Some specific embodiments of the inventive subject matter include input harmonic termination circuitry that includes an integrated capacitance (e.g., metal-insulator-metal (MIM) capacitor) and an inductance (e.g., in the form of a bondwire array) series-coupled between the transistor input and a ground reference. The harmonic termination circuitry embodiments may be used to control the second harmonic impedance across a wide (e.g., 20 percent plus) fractional bandwidth at relatively low impedance (e.g., close to short circuit). This may be useful in achieving relatively high efficiency for broadband applications.

A shunt capacitor in the input-side impedance matching circuit is desirably selected to be eligible for broadband impedance matching. More specifically, the shunt capacitor in the input-side impedance matching circuit has a high enough capacitance value (e.g., greater than 60 picofarads) to provide an acceptable RF low-impedance point (e.g., a quasi-RF cold-point). This RF low-impedance point represents a low impedance point in the circuit for RF signals. A baseband decoupling circuit with good RF isolation is connected to the quasi-RF cold-point.

FIG. 1is a schematic diagram of an RF power amplifier circuit100. Circuit100includes an input102(e.g., a first conductive package lead), an input impedance matching circuit110, a harmonic termination circuit130, a transistor140, an output impedance matching circuit150, baseband decoupling (BBD) circuits160,162(also referred to as video bandwidth circuits), and an output lead104(e.g., a second conductive package lead), in an embodiment. Each of the input and output102,104may be more generally referred to as an “RF input/output (I/O).”

The input impedance matching circuit110, harmonic termination circuit130, and baseband decoupling circuit160may be referred to collectively as an “input circuit.” Similarly, the output impedance matching circuit150and baseband decoupling circuit162may be referred to collectively as an “output circuit.” Although transistor140and various elements of the input and output impedance matching circuits110,150, the baseband decoupling circuits160,162, and the harmonic termination circuit130are shown as singular components, the depiction is for the purpose of ease of explanation only. Those of skill in the art would understand, based on the description herein, that transistor140and/or certain elements of the input impedance matching circuit110, the harmonic termination circuit130, the output impedance matching circuit150, and the baseband decoupling circuits160,162each may be implemented as multiple components (e.g., connected in parallel or in series with each other). Further, embodiments may include single-path devices (e.g., including a single input lead, output lead, transistor, etc.), dual-path devices (e.g., including two input leads, output leads, transistors, etc.), and/or multi-path devices (e.g., including two or more input leads, output leads, transistors, etc.). Further, the number of input/output leads may not be the same as the number of transistors (e.g., there may be multiple transistors operating in parallel for a given set of input/output leads). The description of transistor140and various elements of the input impedance matching circuit110, the harmonic termination circuit130, the output impedance matching circuit150, and the baseband decoupling circuits160,162, below, thus are not intended to limit the scope of the inventive subject matter only to the illustrated embodiments.

Input102and output104each may include a conductor, which is configured to enable the circuit100to be electrically coupled with external circuitry (not shown). More specifically, the input and output102,104are physically positioned to span between the exterior and the interior of a device package, in an embodiment. Input impedance matching circuit110, harmonic termination circuit130, and baseband decoupling circuit160, are electrically coupled between the input102and a first terminal142of transistor140(e.g., the gate terminal). Similarly, output impedance matching circuit150and baseband decoupling circuit162are electrically coupled between a second terminal144of transistor140(e.g., the drain terminal) and the output104. A third terminal145of transistor140(e.g., the source terminal) is coupled to a ground reference node.

According to an embodiment, transistor140is the primary active component of circuit100. Transistor140includes a control terminal142and two current conducting terminals144,145, where the current conducting terminals144,145are spatially and electrically separated by a variable-conductivity channel. For example, transistor140may be a field effect transistor (FET), which includes a gate terminal (control terminal142), a drain terminal (a first current conducting terminal144), and a source terminal (a second current conducting terminal145). According to an embodiment, and using nomenclature typically applied to FETs in a non-limiting manner, the gate terminal142of transistor140is coupled to the input impedance matching circuit110, the harmonic termination circuit130, and the baseband decoupling circuit160, the drain terminal144of transistor140is coupled to the output impedance matching circuit150and the baseband decoupling circuit162, and the source terminal145of transistor140is coupled to ground (or another voltage reference). Through the variation of control signals provided to the gate terminal of transistor140, the current between the current conducting terminals of transistor140may be modulated.

According to various embodiments, transistor140is a III-V field effect transistor (e.g., a high electron mobility transistor (HEMT)), which has a relatively low drain terminal-source terminal capacitance, Cds, when compared with a silicon-based FET (e.g., an LDMOS FET). InFIG. 1, the drain terminal-source terminal capacitance of transistor140is represented with capacitor146between the drain terminal of transistor140and a transistor output terminal144. More specifically, capacitor146is not a physical component, but instead models the drain terminal-source terminal capacitance of transistor140. According to an embodiment, transistor140may have a drain terminal-source terminal capacitance that is less than about 0.2 pF/W. Further, in some embodiments, transistor140may be a GaN FET, although in other embodiments, transistor140may be another type of III-V transistor (e.g., gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb)), or another type of transistor that has a relatively low drain terminal-source terminal capacitance.

As mentioned above, the input impedance matching circuit110, harmonic termination circuit130, and baseband decoupling circuit160, are electrically coupled between the input102and a first terminal142of transistor140(e.g., the gate terminal). According to one embodiment, a first inductive element112(e.g., a first set of bondwires) is coupled between input102and the input impedance matching circuit110. More specifically, the first inductive element112is coupled between the input102and a first node113(also referred to as a “connection node”), which essentially corresponds to an input of the input impedance matching circuit110. Besides functioning to make the electrical connection between the input102and the input impedance matching circuit110, the first inductive element112also may add reactance to a final transformed impedance provided by the input impedance matching circuit110.

The input impedance matching circuit110is coupled between connection node113and the control terminal142(e.g., gate terminal) of the transistor140. Input impedance matching circuit110is configured to transform (e.g., raise) the gate impedance of transistor140to a higher (e.g., intermediate or higher) impedance level (e.g., in a range from about 2 to about 10 ohms or higher) at node102. This is advantageous in that it allows the printed circuit board level (PCB-level) matching interface from a driver stage to have an impedance that can be achieved in high-volume manufacturing with minimal loss and variation (e.g., a “user friendly” matching interface).

According to an embodiment, input impedance matching circuit110has a two-section bandpass filter configuration, which includes a series inductive element116, a series capacitance120, a shunt inductive element118, and a shunt capacitance114. According to an embodiment, series inductive element116and shunt capacitance114form a low-pass filter of the bandpass filter configuration, and shunt inductive element118and series capacitance120form a high pass filter of the bandpass filter configuration. The bandpass configuration allows for wideband operation at RF frequencies that would not be as easily achieved with simpler matching networks.

Series capacitance120and a series inductive element116(e.g., a second set of bondwires) are coupled in series between input102(or more specifically inductance112or connection node113) and the control terminal142of transistor140. More specifically, a first terminal of the series capacitance120is coupled to the first node113, a second terminal of the series capacitance120is coupled to a second node115(also referred to as a “connection node”), and the series inductive element116is coupled between the second node115and the control terminal142of transistor140.

Shunt inductive element118is coupled between the first node113and ground (or another voltage reference). As will be described in more detail later, in an embodiment in which a DC gate bias is provided through input102, rather than through the below-described gate terminal bias circuit190, a DC blocking capacitor119may be connected in series with the third inductive element118. A first terminal of shunt capacitance114is coupled to the second node115, and a second terminal of shunt capacitance114is coupled to ground (or another voltage reference).

According to an embodiment, inductive element112may have an inductance value in a range between about 150 picohenries (pH) to about 400 pH, inductive element116may have an inductance value in a range between about 80 pH to about 250 pH, shunt inductance118may have an inductance value in a range between about 100 pH to about 350 pH, series capacitance120may have a capacitance value in a range between about 25 picofarads (pF) to about 50 pF, and shunt capacitance114may have a capacitance value in a range between about 60 pF to about 200 pF. Desirably, shunt capacitance114has a relatively-large capacitance (e.g., greater than about 60 pF) to provide an acceptable RF low-impedance point at node115. In other embodiments, some or all of the above-listed components may have smaller or larger component values than the above-given ranges.

According to an embodiment, harmonic termination circuit130is coupled between the control terminal142(e.g., gate terminal) of transistor140and ground (or another voltage reference). Harmonic termination circuit130includes inductive element132(e.g., a third set of bondwires) and capacitance134coupled in series between the control terminal142of transistor140and ground (or another voltage reference), and this series combination of elements functions as a low impedance path to ground for signal energy at a harmonic frequency (e.g., a second harmonic of a fundamental frequency of operation of circuit100). According to an embodiment, inductive element132may have an inductance value in a range between about 100 pH to about 1 nH, and capacitance134may have a capacitance value in a range between about 1 pF to about 100 pF, although these components may have values outside of these ranges, as well. For example, at an example fundamental frequency of operation of 2.0 gigahertz (GHz), which has a second harmonic at 4.0 GHz, inductive element132may have an inductance value of about 120 pH, and capacitance134may have a capacitance value of about 12 pF. As will be explained later, the desired inductance and/or capacitance values used to achieve a low impedance path to ground for signal energy at the second harmonic frequency may be affected by mutual coupling between bondwires used to implement inductors116and132.

Desirably, shunt capacitance114has a relatively-large capacitance (e.g., greater than about 60 pF) to provide an RF low-impedance point at node115. In other words, node115represents a low impedance point in the circuit for RF signals. According to an embodiment, a first (in-package) baseband decoupling (BBD) circuit160is coupled between node115(e.g., or another RF low-impedance point at or coupled to node115) and the ground reference node. The first baseband decoupling circuit160may function to improve the low frequency resonance (LFR) of circuit100caused by the interaction between the input matching circuit110and the bias feeds (not shown) by presenting a low impedance at envelope frequencies and/or a high impedance at RF frequencies. The first baseband decoupling circuit160essentially may be considered to be “invisible” from an RF matching standpoint, as it primarily effects the impedance at envelope frequencies (i.e., baseband decoupling circuit160provides terminations for the envelope frequencies of circuit100). As will be discussed in more detail later in conjunction withFIGS. 2A-2F, the first baseband decoupling circuit160may have any of a number of different circuit configurations, in various embodiments.

Amplifier circuit100also may include gate terminal bias circuit190coupled to node115, in an embodiment, which may function as a second (out-of-package) baseband decoupling circuit that is essentially coupled in parallel with the first baseband decoupling circuit160. A similarly (or differently) configured drain terminal bias circuit (not shown) may be coupled to node158. Bias circuit190includes a series-coupled inductive element192(e.g., one or more bondwires592,FIG. 5, coupled in series with a bias lead492,FIG. 4) and capacitor196, with an intermediate node193between the inductor/capacitor combination. According to an embodiment, inductive element192may have an inductance value in a range between about 1500 pH to about 2500 pH, and capacitor196may have a capacitance value in a range between about 8,000 nanofarads (nF) to about 12,000 nF, although the inductance and/or capacitance values could be lower or higher, as well.

To provide a gate bias voltage to the gate terminal142of the transistor140, an external bias circuit (not shown) may be connected to node193(e.g., the distal end of a bias lead), and the bias voltage may be provided through this node. A drain bias voltage may be similarly provided to node158.

In other embodiments, either or both the input-side or output-side bias circuits may be excluded. In such embodiments, the external bias circuits may be connected instead to the input102or to the output104, and the bias voltage(s) may be provided through the input102and/or the output104. For example, in an embodiment in which the gate bias is provided through the input102, circuit100also includes a resistor122coupled in parallel with capacitance120between nodes113and115, and a DC blocking capacitor119in series with inductance118. When included, resistor122and DC blocking capacitor119each are configured to provide high impedance at RF frequencies. According to an embodiment, resistor122may have a resistance value in a range of about 50 ohms to about 150 ohms, and DC blocking capacitor119may have a capacitance value in a range of about 50 pF to about 300 pF, although the resistance and capacitance values of these components could be lower or higher, as well. AlthoughFIG. 1illustrates the third inductive element118and the DC blocking capacitor119in a particular series arrangement (e.g., with the third inductive element118directly connected to node113), in other embodiments, the order of the third inductive element118and the DC blocking capacitor119could be reversed (e.g., with the DC blocking capacitor119directly connected to node113, as is the case in the integrated passive device500illustrated inFIG. 5, and described in detail below). Again, and as indicated by depicting resistor122and DC blocking capacitor119with dashed lines, resistor122and DC blocking capacitor119may be excluded from circuit100in an embodiment in which the gate bias voltage is provided through gate terminal bias circuit190.

On the output side of the circuit100, output impedance matching circuit150is coupled between the first current conducting terminal144(e.g., drain terminal) of transistor140and the output104. Output impedance matching circuit150is configured to match the output impedance of circuit100with the input impedance of an external circuit or component (not shown) that may be coupled to output104. Output impedance matching circuit150may have any of a number of different circuit configurations, and just one example is shown inFIG. 1. More specifically, in the non-limiting example shown inFIG. 1, output impedance matching circuit150includes two inductive elements152,154and shunt capacitance156. A first inductive element152(e.g., a fourth set of bondwires) is coupled between the first current conducting terminal144(e.g., drain terminal) of transistor140and the output104. A second inductive element154(e.g., a fifth set of bondwires) is coupled between the first current conducting terminal144of transistor140and a node158, which corresponds to another RF low-impedance point, in an embodiment. A second terminal of the shunt capacitance156is coupled to ground (or to another voltage reference), in an embodiment.

Again, the RF low-impedance point158represents a low impedance point in the circuit for RF signals. According to an embodiment, another baseband decoupling circuit162is coupled between the RF low-impedance point158and the ground reference node. Again, baseband decoupling circuit162may function to further improve the LFR of circuit100caused by the interaction between the output impedance matching circuit150and the bias feeds (not shown) by presenting a low impedance at envelope frequencies and/or a high impedance at RF frequencies. Baseband decoupling circuit162also may be considered to be “invisible” from an RF matching standpoint.

As will now be described in conjunction withFIGS. 2A-2F, the baseband decoupling circuits160,162may have any of a number of different circuit configurations, in various embodiments. For example,FIGS. 2A-2Fillustrate six example embodiments of baseband decoupling circuits (e.g., baseband decoupling circuits160,162,FIG. 1). In each ofFIGS. 2A-2F, baseband decoupling circuit200,201,202,203,204,205is coupled between a connection node215(e.g., node115and/or node158,FIG. 1) and ground (or another voltage reference). Further, each baseband decoupling circuit200-205includes an envelope inductance262, Lenv, an envelope resistor264, Renv, and an envelope capacitor266, Cenv, coupled in series between the connection node215and ground. In each ofFIGS. 2A-2E, a first terminal of envelope inductance262is coupled to node215, and a second terminal of envelope inductance262is coupled to node280. A first terminal of envelope resistor264is coupled to node280, and a second terminal of envelope resistor264is coupled to node282. A first terminal of envelope capacitor266is coupled to node282, and a second terminal of the envelope capacitor266is coupled to ground (or another voltage reference). Although the order of the series of components between node215and the ground reference node is the envelope inductance262, the envelope resistor264, and the envelope capacitor266inFIGS. 2A-2E, the order of components in the series circuit could be different, in other embodiments. For example, inFIG. 2F, the envelope resistor264is coupled between node215and a node284, the envelope inductance262is coupled between node284and a node286, and the envelope capacitor266is coupled between node286and ground (or another voltage reference).

Referring toFIGS. 2A-2F, and according to an embodiment, the envelope inductance262, may be implemented as an integrated inductance (e.g., inductance562,FIG. 5), as a discrete inductor, and/or as a set of bondwires coupling the connection node215to the envelope resistor264(e.g., via node280). For example, and as will be described in detail later, envelope inductance262may be integrally formed as a portion of an integrated passive device (IPD), such as IPD480-483,FIGS. 4-6. For example, envelope inductance262may have an inductance value in a range between about 5 pH to about 2000 pH. Desirably, envelope inductance262has an inductance value less than about 500 pH (e.g., as low as 50 pH, in an embodiment, or possibly even lower). In other embodiments, the value of envelope inductance262may be lower or higher than the above-given range.

Envelope resistor264may be implemented as an integrated resistor (e.g., resistor564,FIG. 5), in an embodiment, or as a discrete resistor, in another embodiment. For example, envelope resistor264may be integrally formed as a portion of an IPD, such as IPD480-483,FIGS. 4-6. In some instances, envelope capacitor266and envelope inductor262may provide additional parasitic resistance which can be considered part of the overall resistance that forms envelope resistor264. In an embodiment, envelope resistor264may have a resistance value in a range between about 0.1 ohm to about 5.0 ohm, although envelope resistor264may have a resistance value outside of this range, as well.

Envelope capacitor266may be implemented as an integrated capacitor (e.g., capacitor566,FIG. 5), in an embodiment, or as a discrete capacitor (e.g., a “chip capacitor”), in another embodiment. For example, envelope capacitor266may be integrally formed as a portion of an IPD, such as IPD480-483,FIGS. 4-6. In an embodiment, envelope capacitor266may have a capacitance value in a range between about 1 nF to about 1 microfarad (μF), although envelope capacitor266may have a capacitance value outside of this range, as well.

The first embodiment of baseband decoupling circuit200illustrated inFIG. 2Aincludes a simple series combination of envelope inductance262, envelope resistor264, and envelope capacitor266. Conversely, in the embodiments ofFIGS. 2B-2F, the baseband decoupling circuit201-205may include one or more “bypass” or “parallel” capacitors268,270,272,274,276,278, Cpara, which are coupled in parallel with the envelope inductance262and/or the envelope resistor264. Each of the bypass capacitors268,270,272,274,276,278may be implemented as a discrete capacitor (e.g., capacitor578,FIGS. 5, 6), in some embodiments, or as an integrated capacitor, in other embodiments. In each of these embodiments, a bypass capacitor268,270,272,274,276,278may have a capacitance value in a range between about 3.0 pF to about 1400 pF. In other embodiments, the value of any of bypass capacitors268,270,272,274,276,278may be lower or higher than the above-given range.

In the baseband decoupling circuit201ofFIG. 2B, bypass capacitor268, Cpara, is coupled in parallel with the envelope inductance262. More specifically, first terminals of envelope inductance262and bypass capacitor268are coupled to node215, and second terminals of envelope inductance262and bypass capacitor268are coupled to node280.

In the baseband decoupling circuit202ofFIG. 2C, bypass capacitor270, Cpara, is coupled in parallel with the envelope resistor264. More specifically, first terminals of envelope resistor264and bypass capacitor270are coupled to node280, and second terminals of envelope resistor264and bypass capacitor270are coupled to node282.

In the baseband decoupling circuit203ofFIG. 2D, bypass capacitor272, Cpara, is coupled in parallel with the envelope inductance262and envelope resistor264. More specifically, bypass capacitor272is coupled across nodes215and282.

In the baseband decoupling circuit204ofFIG. 2E, a first bypass capacitor274, Cpara1, is coupled in parallel with the envelope inductance262, and a second bypass capacitor276, Cpara2, is coupled in parallel with the envelope resistor264. More specifically, first terminals of envelope inductance262and first bypass capacitor274are coupled to node215, and second terminals of envelope inductance262and first bypass capacitor274are coupled to node280. In addition, first terminals of envelope resistor264and second bypass capacitor276are coupled to node280, and second terminals of envelope resistor264and second bypass capacitor276are coupled to node282.

Referring to the baseband decoupling circuits201,204, and205ofFIGS. 2B, 2E, and 2F, parallel-coupled inductance262and capacitor268,274or278form a parallel resonant circuit at frequencies in proximity to the center operational frequency of the device or circuit (e.g., circuit100) within which circuit201,204or205is incorporated. As used herein, and according to an embodiment, the term “in proximity to the center operating frequency” means “within 20 percent of the center operating frequency.” Accordingly, for example, when a device has a center operating frequency of 2.0 gigahertz (GHz), a frequency that is “in proximity to the center operating frequency” corresponds to a frequency that falls in a range from 1.8 GHz to 2.2 GHz. Although 2.0 GHz is given as an example center operating frequency, a device may have a center operating frequency that is different from 2.0 GHz, as well. In alternate embodiments, the term “in proximity to the center operating frequency” may mean “within 10 percent of the center operating frequency” or “within 5 percent of the center operating frequency.”

Because Lenv/Cparaform a parallel resonant circuit at frequencies in proximity to the center operational frequency of the device, the parallel resonant circuit Lenv/Cparaessentially appears as an open circuit to such frequencies. Accordingly, RF energy near the center operational frequency that may be present at the node215to which circuit201,204or205is coupled will be deflected by the parallel resonant circuit Lenv/Cpara. This deflection may be provided even using a relatively low inductance value for inductance262. For these reasons, circuits201,204, and205may significantly improve the LFR of a device or circuit (e.g., circuit100) in which it is incorporated by presenting a low impedance at envelope frequencies and a high impedance at RF frequencies.

In each of the embodiments of baseband decoupling circuits202,203,204ofFIGS. 2C, 2D, and 2E, bypass capacitor270,272or276is coupled in parallel with envelope resistor264. Because capacitor270,272or276may function to route RF current around the envelope resistor264, circuits202,203,204may result in a reduction in the RF current dissipated by the envelope resistor264. This characteristic of circuits202,203,204also may serve to better protect the envelope resistor264from potential compromise due to excessive current that may otherwise flow through the envelope resistor264in the absence of bypass capacitor270,272or276.

Each of circuits201-205may increase the device efficiency, when compared with circuit200, since they allow less RF current to flow through (and be dissipated by) the envelope resistor264. Further, because circuits201-205present a high impedance to RF frequencies in proximity to the center operational frequency of a device into which the baseband decoupling circuit is incorporated, it is not as important for circuits201-205to be connected to an RF low-impedance point (e.g., RF low-impedance point115or158,FIG. 1), although they may be. Instead, the benefits of circuits201-205may be achieved even when circuits201-205are coupled to a node that shows higher RF impedance. This includes other nodes in both the input and output impedance matching circuits.

Referring again toFIG. 1, and as will be described in more detail later in conjunction withFIGS. 4-6, various embodiments of RF amplifier devices may include at least one input-side integrated passive device (IPD) assembly (e.g., IPD assemblies480,481,FIGS. 4-6), and at least one output-side IPD assembly (e.g., IPD assemblies482,483,FIG. 4). The input-side IPD assembly(ies) (e.g., IPD assemblies480,481) include portions of the input circuit110, the harmonic termination circuit130, and the baseband decoupling circuit160. Similarly, the output-side IPD assembly(ies) (e.g., IPD assemblies482,483) include portions of the output circuit150and the baseband decoupling circuit162. More specifically, each IPD assembly may include a semiconductor substrate with one or more integrated passive components. In a particular embodiment, each input-side IPD assembly may include shunt capacitances114and134, and components of baseband decoupling circuit160(e.g., components262,264,266,268,270,272,274,276,278,FIGS. 2A-2F). In other particular embodiments, each output-side IPD assembly may include shunt capacitance156, and components of baseband decoupling circuit162(e.g., components262,264,266,268,270,272,274,276,278,FIGS. 2A-2F).

In other embodiments, some portions of the input and output impedance matching circuits110,150and baseband decoupling circuits160,162may be implemented as distinct/discrete components or as portions of other types of assemblies (e.g., a low-temperature co-fired ceramic (LTCC) device, a small PCB assembly, and so on). In still other embodiments, some portions of the input and/or output impedance matching circuits110,150may be coupled to and/or integrated within the semiconductor die that includes transistor140. The below, detailed description of embodiments that include IPD assemblies should not be taken to limit the inventive subject matter, and the term “passive device substrate” or “IPD substrate” means any type of structure that includes a passive device, including an IPD, a LTCC device, a transistor die, a PCB assembly, and so on.

The RF amplifier circuit100ofFIG. 1may be utilized as a single-path amplifier, which receives an RF signal at input102, amplifies the signal through transistor140, and produces an amplified RF signal at output104. Alternatively, multiple instances of the RF amplifier circuit100may be utilized to provide a multiple-path amplifier, such as a Doherty power amplifier or another type of multi-path amplifier circuit.

For example,FIG. 3is a simplified schematic diagram of a Doherty power amplifier300in which embodiments of RF power amplifier circuit100may be implemented. Amplifier300includes an input node302, an output node304, a power divider306(or splitter), a main amplifier path320, a peaking amplifier path321, and a combining node380. A load390may be coupled to the combining node380(e.g., through an impedance transformer, not shown) to receive an amplified RF signal from amplifier300.

Power divider306is configured to divide the power of an input RF signal received at input node302into main and peaking portions of the input signal. The main input signal is provided to the main amplifier path320at power divider output308, and the peaking input signal is provided to the peaking amplifier path321at power divider output309. During operation in a full-power mode when both the main and peaking amplifiers340,341are supplying current to the load390, the power divider306divides the input signal power between the amplifier paths320,321. For example, the power divider306may divide the power equally, such that roughly one half of the input signal power is provided to each path320,321(e.g., for a symmetric Doherty amplifier configuration). Alternatively, the power divider306may divide the power unequally (e.g., for an asymmetric Doherty amplifier configuration).

Essentially, the power divider306divides an input RF signal supplied at the input node302, and the divided signals are separately amplified along the main and peaking amplifier paths320,321. The amplified signals are then combined in phase at the combining node380. It is important that phase coherency between the main and peaking amplifier paths320,321is maintained across a frequency band of interest to ensure that the amplified main and peaking signals arrive in phase at the combining node380, and thus to ensure proper Doherty amplifier operation.

Each of the main amplifier340and the peaking amplifier341includes one or more single-stage or multiple-stage power transistor integrated circuits (ICs) (or power transistor die) for amplifying an RF signal conducted through the amplifier340,341. According to various embodiments, all amplifier stages or a final amplifier stage of either or both the main amplifier340and/or the peaking amplifier341may be implemented, for example, using a III-V field effect transistor (e.g., a HEMT), such as a GaN FET (or another type of III-V transistor, including a GaAs FET, a GaP FET, an InP FET, or an InSb FET). Where only one of the main amplifier340or the peaking amplifier341is implemented as a III-V FET, the other amplifier may be implemented as a silicon-based FET (e.g., an LDMOS FET), in some embodiments.

Although the main and peaking power transistor ICs may be of equal size (e.g., in a symmetric Doherty configuration), the main and peaking power transistor ICs may have unequal sizes, as well (e.g., in various asymmetric Doherty configurations). In an asymmetric Doherty configuration, the peaking power transistor IC(s) typically are larger than the main power transistor IC(s) by some multiplier. For example, the peaking power transistor IC(s) may be twice the size of the main power transistor IC(s) so that the peaking power transistor IC(s) have twice the current carrying capability of the main power transistor IC(s). Peaking-to-main amplifier IC size ratios other than a 2:1 ratio may be implemented, as well.

During operation of Doherty amplifier300, the main amplifier340is biased to operate in class AB mode, and the peaking amplifier341is biased to operate in class C mode. At low power levels, where the power of the input signal at node302is lower than the turn-on threshold level of peaking amplifier341, the amplifier300operates in a low-power (or back-off) mode in which the main amplifier340is the only amplifier supplying current to the load390. When the power of the input signal exceeds a threshold level of the peaking amplifier341, the amplifier300operates in a high-power mode in which the main amplifier340and the peaking amplifier341both supply current to the load390. At this point, the peaking amplifier341provides active load modulation at combining node380, allowing the current of the main amplifier340to continue to increase linearly.

Input and output impedance matching networks310,350(input MNm, output MNm) may be implemented at the input and/or output of the main amplifier340. Similarly, input and output impedance matching networks311,351(input MNp, output MNp) may be implemented at the input and/or output of the peaking amplifier341. In each case, the matching networks310,311,350,351may be used to transform the gate and drain impedances of main amplifier340and peaking amplifier341to a more desirable system level impedance, as well as manipulate the signal phases to ensure proper Doherty amplifier operation. All or portions of the input and output impedance matching networks310,311,350,351may be implemented inside a power transistor package that includes the main and/or peaking amplifiers340,341, or some portions of the input and output impedance matching networks310,311,350,351may be implemented on a PCB or other substrate to which a power transistor package is mounted.

In addition, as will be described in detail later, embodiments of the inventive subject matter include harmonic frequency termination circuits330,331coupled between the inputs of amplifiers340,341and a ground reference. The harmonic frequency termination circuits330,331are configured to control the harmonic impedance across a relatively wide fractional bandwidth. For example, the harmonic frequency termination circuits330,331may provide a low impedance path to ground for signal energy at the second harmonic of the center frequency of operation, fo, of the amplifier300(also referred to herein as the “fundamental frequency” of operation).

Doherty amplifier300has a “non-inverted” load network configuration. In the non-inverted configuration, the input circuit is configured so that an input signal supplied to the peaking amplifier341is delayed by 90 degrees with respect to the input signal supplied to the main amplifier340at the center frequency of operation, fo, of the amplifier300. To ensure that the main and peaking input RF signals arrive at the main and peaking amplifiers340,341with about 90 degrees of phase difference, as is fundamental to proper Doherty amplifier operation, phase delay element382applies about 90 degrees of phase delay to the peaking input signal. For example, phase delay element382may include a quarter wave transmission line, or another suitable type of delay element with an electrical length of about 90 degrees.

To compensate for the resulting 90 degree phase delay difference between the main and peaking amplifier paths320,321at the inputs of amplifiers340,341(i.e., to ensure that the amplified signals arrive in phase at the combining node380), the output circuit is configured to apply about a 90 degree phase delay to the signal between the output of main amplifier340and the combining node380. This is achieved through an additional delay element384. Alternate embodiments of Doherty amplifiers may have an “inverted” load network configuration. In such a configuration, the input circuit is configured so that an input signal supplied to the main amplifier340is delayed by about 90 degrees with respect to the input signal supplied to the peaking amplifier341at the center frequency of operation, fo, of the amplifier300, and the output circuit is configured to apply about a 90 degree phase delay to the signal between the output of peaking amplifier341and the combining node380.

Amplifiers340and341, along with harmonic frequency termination circuits330,331and portions of matching networks310,311,350,351may be implemented in discrete, packaged power amplifier devices. In such devices, input and output leads are coupled to a substrate, and each amplifier340,341may include a single-stage or multi-stage power transistor also coupled to the substrate. Portions of the harmonic frequency termination circuits330,331and the input and output matching networks310,311,350,351may be implemented as additional components within the packaged device. Further, as is described in detail below, the baseband decoupling circuits (e.g., embodiments of VBW circuits160,162,FIG. 1, illustrated inFIGS. 2A-2F) also may be implemented as additional components within the packaged device.

For example,FIG. 4is a top view of an embodiment of a packaged RF amplifier device400that embodies two parallel instances of the circuit100ofFIG. 1, and which may be utilized to provide amplifiers (e.g., amplifiers340,341,FIG. 3), and portions of matching networks (e.g., portions of matching networks310,311,350,351,FIG. 3) in a Doherty amplifier (e.g., Doherty amplifier300,FIG. 3). In addition, as will be described in more detail below, device400includes two input-side IPD assemblies480,481, each of which includes portions of an input impedance matching circuit410,411(e.g., circuit110,310,311FIGS. 1, 3), a baseband decoupling circuit460,461(e.g., circuit160,FIG. 1), and a harmonic termination circuit430,431(e.g., circuit130,330,331,FIGS. 1, 3). Further, device400includes two output-side IPD assemblies482,483, each of which includes portions of an output impedance matching circuit450,451(e.g., circuit150,350,351FIGS. 1, 3), and a baseband decoupling circuit462,463(e.g., circuit162,FIG. 1).

Device400includes a flange406(or “device substrate”), in an embodiment, which includes a rigid electrically-conductive substrate with a thickness that is sufficient to provide structural support for various electrical components and elements of device400. In addition, flange406may function as a heat sink for transistor dies440,441and other devices mounted on flange406. Flange406has top and bottom surfaces (only a central portion of the top surface is visible inFIG. 4), and a substantially-rectangular perimeter that corresponds to the perimeter of the device400.

Flange406is formed from an electrically conductive material, and may be used to provide a ground reference node for the device400. For example, various components and elements may have terminals that are electrically coupled to flange406, and flange406may be electrically coupled to a system ground when the device400is incorporated into a larger electrical system. At least the top surface of flange406is formed from a layer of conductive material, and possibly all of flange406is formed from bulk conductive material.

An isolation structure408is attached to the top surface of flange406, in an embodiment. Isolation structure408, which is formed from a rigid, electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads402-405,492-495and flange406). Isolation structure408has a frame shape, in an embodiment, which includes a substantially enclosed, four-sided structure with a central opening. Isolation structure408may have a substantially rectangular shape, as shown inFIG. 4, or isolation structure408may have another shape (e.g., annular ring, oval, and so on).

A portion of the top surface of flange406that is exposed through the opening in isolation structure408is referred to herein as the “active area” of device400. Transistor dies440,441are positioned within the active device area of device400, along with IPD assemblies480,481,482,483, which will be described in more detail later. For example, the transistor dies440,441and IPD assemblies480-483may be coupled to the top surface of flange406using conductive epoxy, solder, solder bumps, sintering, and/or eutectic bonds.

Device400houses two amplification paths (indicated with arrows420,421), where each amplification path420,421represents a physical implementation of circuit100(FIG. 1). When incorporated into a Doherty amplifier (e.g., Doherty amplifier300,FIG. 3), amplification path420may correspond to a main amplifier path (e.g., main amplifier path320,FIG. 3), and amplification path421may correspond to a peaking amplifier path (e.g., peaking amplifier path321,FIG. 3). In some instances, the order could be switched, where amplification path420may correspond to a peaking amplifier path, and amplification path421may correspond to a main amplifier path.

The input and output leads402-405are mounted on a top surface of the isolation structure408on opposed sides of the central opening, and thus the input and output leads402-405are elevated above the top surface of the flange406, and are electrically isolated from the flange406. Generally, the input and output leads402-405are oriented to allow for attachment of bondwires between the input and output leads402-405and components and elements within the central opening of isolation structure408.

Each transistor die440,441includes an integrated power FET, where each FET has a control terminal (e.g., a gate terminal) and two current conducting terminals (e.g., a drain terminal and a source terminal). A control terminal of a FET within each transistor die440,441is coupled through an input impedance matching circuit410,411to an input lead402,403. In addition, one current conducting terminal (e.g., the drain terminal) of a FET within each transistor die440,441is coupled through an output impedance matching circuit450,451to an output lead404,405. The other current conducting terminal (e.g., the source terminal) of a FET within each transistor die440,441is electrically coupled through the die440,441to the flange406(e.g., to ground), in an embodiment.

Embodiments of the input impedance matching circuits410,411, baseband decoupling circuits460,461, and harmonic termination circuits430,431will be described in more detail later in conjunction withFIGS. 5 and 6, which illustrate the components of these circuits410,411,430,431,460,461in greater detail. As will be explained in conjunction withFIGS. 5 and 6, some of the components of these circuits may be implemented within IPD assemblies480,481. Briefly, each input impedance matching circuit410,411is coupled between an input lead402,403and the control terminal of a FET within a transistor die440,441. Each input-side baseband decoupling circuit460,461is coupled between a node415,416(e.g., a conductive bond pad) within IPD assembly480,481and a ground reference (e.g., flange406). Each harmonic termination circuit430,431is coupled between the control terminal (e.g., the gate terminal) of a FET within a transistor die440,441and the ground reference (e.g., flange406).

Some of the components of the output impedance matching circuits450,451and baseband decoupling circuits462,463may be implemented within IPD assemblies482,483. Briefly, each output impedance matching circuit450,451is coupled between a current conducting terminal (e.g., the drain terminal) of a FET within a transistor die440,441and an output lead404,405. Each baseband decoupling circuit462,463is coupled between a node458,459(e.g., an RF low-impedance point in the form of a conductive bond pad) within IPD assembly482,483and a ground reference (e.g., flange406).

In addition to the input and output leads402-405, device400also may include bias circuitry (e.g., including bias circuit190,FIG. 1). In the embodiment ofFIG. 4, each of the bias circuits include an inductive element (e.g., inductive element192,FIG. 1), and each of the input-side (gate) bias circuits further include a capacitor496,497(e.g., capacitor196,FIG. 1). For example, each capacitor496,497may be a discrete capacitor with a first terminal coupled to a bias lead492,493, and a second terminal coupled to a ground reference node (e.g., on a PCB to which the device400is connected).

The inductive element of each bias circuit may include, for example, a series-coupled arrangement of a bias lead492,493,494,495and one or more bondwires (e.g., bondwire592,FIG. 5) coupling each bias lead492-495to a control terminal (e.g., the gate terminal) or to a current conducting terminal (e.g., the drain terminal) of a FET within each transistor die440,441. The distal end of each bias lead492-495may be electrically coupled to an external bias circuit (not shown), which provides a bias voltage to the control terminal or current conducting terminal of each FET through the bias lead492-495. When the gate bias voltage is provided through bias leads492,493, the below-described resistors522(e.g., resistor122,FIG. 1) and capacitor519(e.g., capacitor119,FIG. 1) may be excluded from device400. In other embodiments, either or both the input-side or output-side bias circuits may be excluded. In such embodiments, the external bias circuits may be connected instead to the input leads402,403or to the output leads404,405and the bias voltage(s) may be provided through the input leads402,403and/or the output leads404,405.

In the example ofFIG. 4, device400includes two transistor dies440,441that essentially function in parallel, although another semiconductor device may include a single transistor die or more than two transistor dies, as well. In addition, device400includes two input-side IPD assemblies480,481and two output-side IPD assemblies482,483, which also essentially function in parallel. It is to be understood that more or fewer of IPD assemblies480-483may be implemented, as well.

According to an embodiment, device400is incorporated in an air cavity package, in which transistor dies440,441, the IPD assemblies480-483, and various other components are located within an enclosed air cavity. Basically, the air cavity is bounded by flange406, isolation structure408, and a cap (not shown) overlying and in contact with the isolation structure408and leads402-405,492-495. InFIG. 4, an example interior perimeter of the cap is indicated by dashed box409, while an exterior perimeter would approximately align with the outer perimeter of flange406. In other embodiments, the components of device400may be incorporated into an overmolded package (i.e., a package in which the electrical components within the active device area are encapsulated with a non-conductive molding compound, and in which portions of the leads402-405,492-495also may be encompassed by the molding compound). In an overmolded package, isolation structure408may be excluded.

Reference is now made toFIGS. 5 and 6, which include enlarged views of portions of device400(FIG. 4) that include embodiments of input impedance matching circuits410, baseband decoupling circuit460, and harmonic termination circuit430. More specifically,FIG. 5is a top view of the lower-left, input-side portion500of packaged RF power amplifier device400along amplifier path420. Portion500(FIG. 5) includes a portion of power transistor die440, a portion of input lead402, and input-side IPD assembly480. For enhanced understanding,FIG. 6includes a cross-sectional, side view of the portion500of the RF power amplifier device ofFIG. 5along line6-6, in accordance with an example embodiment. More specifically,FIG. 6is a cross-sectional view through input lead402, IPD assembly480, a portion of flange406, and transistor die440. As indicated inFIG. 6, the power transistor die440and the IPD assembly480are coupled to the conductive flange406, and the input lead402is electrically isolated from the conductive flange406(e.g., using an isolation structure408). It should be noted that the input-side portion of the device400along amplifier path421may be substantially the same as portion500shown inFIGS. 5 and 6.

The power transistor die440includes a transistor input terminal542(e.g., a conductive bond pad), which is electrically connected within the power transistor die440to a control terminal (e.g., a gate terminal) of a single-stage or final-stage FET630integrated within the die440. As discussed previously, each FET630may include a III-V field effect transistor (e.g., a HEMT), such as a GaN FET (or another type of III-V transistor, including a GaAs FET, a GaP FET, an InP FET, or an InSb FET). More specifically, each FET630may be integrally formed in and on a base semiconductor substrate632(e.g., a GaN substrate, a GaN-on-silicon substrate, a GaN-on-silicon carbide substrate, and so on). Conductive connections between the control terminal of the FET630(e.g., the gate terminal) and the input terminal542of the die440may be made through a build-up structure634of alternating dielectric and patterned conductive layers, where portions of the patterned conductive layers are electrically connected using conductive vias. A conductive layer636on a bottom surface of the die440may provide a ground node (e.g., for the source terminal, which may be connected to the conductive layer636(and thus to the conductive flange406) using through substrate vias or doped sinker regions (not shown)).

The IPD assembly480also may include a base semiconductor substrate682(e.g., a silicon substrate, a silicon carbide substrate, a GaN substrate, or another type of semiconductor substrate, which may be referred to as an “IPD substrate” herein) and a build-up structure684of alternating dielectric and patterned conductive layers, where portions of the patterned conductive layers are electrically connected using conductive vias. As will be discussed in more detail below, various electrical components of the input impedance matching circuit410, the baseband decoupling circuit460, and the harmonic termination circuit430are integrally formed within and/or connected to the IPD assembly480. These electrical components may be electrically connected to conductive bond pads (e.g., bond pads415,513,533) at the top surface of the IPD assembly480, and also may be electrically connected to the conductive flange406(e.g., to ground) using through substrate vias to a conductive layer686on a bottom surface of the IPD assembly480.

First, connections between the transistor die440and the input lead402through the input impedance matching circuit410will be described in more detail. More specifically, an input lead402is electrically coupled, through an instance of an input impedance matching circuit410, to the input terminal542of the transistor die440. The input terminal542, in turn, is electrically coupled to the control terminal (e.g., the gate terminal) of a FET within the transistor die440.

For example, in an embodiment, the input impedance matching circuit410may include three inductive elements512,516,518(e.g., inductive elements112,116,118,FIG. 1), a series capacitor520(e.g., series capacitance120,FIG. 1), and a shunt capacitor514(e.g., shunt capacitance114,FIG. 1). The first inductive element512(e.g., inductive element112,FIG. 1) may be implemented as a first set of bondwires that are coupled between the input lead402and a conductive bond pad513(e.g., corresponding to connection node113,FIG. 1) on a top surface of the IPD assembly480. The second inductive element516(e.g., inductive element116,FIG. 1) may be implemented as a second set of bondwires that are coupled between bond pad415(corresponding to connection node115,FIG. 1) and the input terminal542of the transistor die440. To avoid clutteringFIG. 5, only one bondwire in the set of bondwires comprising inductive element516is circled and numbered with reference number516. It should be understood that inductive element516includes all bondwires coupled between bond pad415and the input terminal542. Finally, the third inductive element518(e.g., inductive element118,FIG. 1) may be implemented as one or more transmission line segments (e.g., coils, as shown) that are integrally formed as part of the IPD assembly480, and that are electrically coupled between bond pad513and a ground reference (e.g., flange406).

In the illustrated embodiment, a DC blocking capacitor519(e.g., DC blocking capacitor119,FIG. 1) is coupled between the bond pad513and the third inductive element518. However, as described previously, DC blocking capacitor519may be excluded when the gate bias voltage is provided through a separate gate bias circuit (e.g., through bias leads492and493). When included, DC blocking capacitor519may be implemented as a metal-insulator-metal (MIM) capacitor (or a plurality of parallel-coupled MIM capacitors) that is integrally formed as part of the IPD assembly480, where a MIM capacitor includes first and second conductive electrodes (formed from patterned portions of the conductive layers of build-up structure684) that are aligned with each other and electrically separated by dielectric material of the build-up structure684. Alternatively, DC blocking capacitor519may be implemented as one or more discrete capacitors (“chip capacitors”) that are connected to a top surface of IPD assembly480.

A first terminal of the series capacitor520(e.g., series capacitance120,FIG. 1) is coupled directly or indirectly to bond pad513(corresponding to corresponding to node113,FIG. 1), and a second terminal of the series capacitor520is coupled directly or indirectly to conductive bond pad415(corresponding to corresponding to node115,FIG. 1). The series capacitor520(e.g., series capacitance120,FIG. 1) may be implemented as a discrete capacitor (or a plurality of parallel-coupled discrete capacitors, as shown inFIG. 4) connected to a top surface of IPD assembly480. Alternatively, the series capacitor520may be implemented as a MIM capacitor (or a plurality of parallel-coupled MIM capacitors) that is integrally formed as part of the IPD assembly480.

In the illustrated embodiment, one or more resistors522(e.g., resistor122,FIG. 1) are coupled in parallel with capacitor(s)520. However, as described previously, resistors522may be excluded when the gate bias voltage is provided through a separate gate bias circuit (e.g., through bias leads492and493). According to an embodiment, when included, each resistor522may be integrally formed as part of the IPD assembly480. For example, each resistor522may be a polysilicon resistor formed from a layer of polysilicon on or within build-up structure684.

According to an embodiment, a first electrode (or terminal) of the shunt capacitor514(e.g., shunt capacitor114,FIG. 1) is electrically coupled to the conductive bond pad415(and thus to capacitor(s)520and bondwires516), and a second electrode (or terminal) of the shunt capacitor514is electrically coupled to the conductive flange (e.g., using conductive through substrate vias that extend through the semiconductor substrate682). The shunt capacitor514may be implemented as a MIM capacitor (or a set of parallel-coupled MIM capacitors) that is integrally formed as part of the IPD assembly480. In a more specific embodiment, the first electrode of the shunt capacitor514is “directly connected” to the bond pad415, where “directly connected” means electrically connected, possibly with one or more conductive traces and/or conductive vias, but without intervening circuit elements (i.e., circuit elements that have more than a trace inductance, where a “trace inductance” is an inductance less than about 100 pH). Because the shunt capacitor514and the bond pad415are “directly connected,” and the bond pad415also has only a trace inductance, in an embodiment, the bondwires516and the shunt capacitor514also may be considered to be “directly connected.” In an alternate embodiment, the shunt capacitor514may be implemented using one or more discrete capacitors coupled to a top surface of the IPD assembly480, or using another type of capacitor.

According to an embodiment, bondwires512may have an inductance value in a range between about 150 pH to about 400 pH, bondwires516may have an inductance value in a range between about 80 pH to about 250 pH, shunt inductor518may have an inductance value in a range between about 100 pH to about 350 pH, series capacitor520may have a capacitance value in a range between about 25 pF to about 50 pF, resistor522may have a resistance value in a range of about 50 ohms to about 150 ohms, and shunt capacitor514may have a capacitance value in a range between about 60 pF to about 200 pF. DC blocking capacitor519may have a capacitance value in a range of about 50 pF to about 300 pF. In other embodiments, some or all of the above-listed components may have smaller or larger component values than the above-given ranges.

As mentioned above, a baseband decoupling circuit460is included in input-side IPD assembly480, in an embodiment. Each baseband decoupling circuit460may have any one of a number of configurations, in various embodiments, such as but not limited to one of the configurations illustrated inFIGS. 2A-2F. In the embodiment illustrated inFIGS. 5 and 6, which corresponds to the baseband decoupling circuit205ofFIG. 2F, the baseband decoupling circuit460includes a series combination of an envelope resistor564(e.g., resistor264,FIG. 2F), an envelope inductor562(e.g., inductor262,FIG. 2F), and an envelope capacitor566(e.g., capacitor266,FIG. 2F) electrically connected between node415(e.g., node115,215,FIGS. 1, 2F, which may correspond to or be coupled to an RF low-impedance point) and a ground reference (e.g., flange406). In addition, each baseband decoupling circuit460includes a bypass capacitor578(e.g., bypass capacitor278,FIG. 2F) connected in parallel with envelope inductor562. In the embodiments ofFIGS. 5 and 6, two instances of the parallel combination of envelope inductor562and bypass capacitor578are implemented on opposite sides of the IPD assembly480. More specifically, the parallel combinations of envelope inductor562and capacitor578are connected in parallel between envelope resistor564and envelope capacitor566, in the illustrated embodiment. In an alternate embodiment, the baseband decoupling circuit460may include only one instance of the combination of envelope inductor562and capacitor578, or more than two instances of the combination of envelope inductor562and capacitor578.

In the embodiment ofFIGS. 5 and 6, envelope resistor564is integrally formed as part of the IPD assembly480. For example, each envelope resistor564may be a polysilicon resistor formed from a layer of polysilicon on or within build-up structure684, and electrically coupled between node418and the parallel combination of envelope inductor562and bypass capacitor578. In other alternate embodiments, the envelope resistor564may be formed from tungsten silicide or another material, may be a thick or thin film resistor, or may be a discrete component coupled to a top surface of IPD assembly480.

The envelope inductor562also may be integrally formed as part of the IPD assembly480, as is illustrated in the embodiment ofFIGS. 5 and 6. For example, each envelope inductor562may be a patterned conductor formed from portion(s) of one or more conductive layers of the build-up structure684, where a first end of the conductor is electrically coupled to envelope resistor564, and a second end of the conductor is electrically coupled to a first terminal of envelope capacitor566. In alternate embodiments, each envelope inductor562may be implemented as a plurality of bondwires, or as a spiral inductor (e.g., on or proximate to the top surface of IPD assembly480), or as a discrete inductor coupled to a top surface of IPD assembly480.

A bypass capacitor578is coupled in parallel with each envelope inductor562, in an embodiment. Each of the bypass capacitors578may be, for example, a discrete capacitor that is connected (e.g., using solder, a conductive epoxy, or other means) to a top surface of IPD assembly480. More specifically, a first terminal of each bypass capacitor578may be electrically coupled to the envelope resistor564and to a first terminal of an envelope inductor562, and a second terminal of each bypass capacitor578may be connected to a second terminal of an envelope inductor562and to a first terminal of envelope capacitor566.

For example, each bypass capacitor578may be a multiple-layer capacitor (e.g., a multiple-layer ceramic capacitor) with parallel, interleaved electrodes and wrap-around end terminations. Alternatively, each bypass capacitor578may form a portion of a separate IPD (e.g., a MIM capacitor formed on a semiconductor substrate), or may be a capacitor (e.g., a MIM capacitor) that is integrally formed with the semiconductor substrate of the IPD assembly480. Alternatively, each bypass capacitor578may be implemented as some other type of capacitor capable of providing the desired capacitance for the baseband decoupling circuit460.

The envelope capacitor566is electrically coupled between a ground reference node (e.g., conductive layer686at the bottom surface of each IPD assembly480) and the parallel combination of envelope inductor562and bypass capacitor578. Capacitor566may be a MIM capacitor that is integrally formed with the IPD substrate of IPD assembly480, for example. In some embodiments, capacitor566may be formed in the build-up structure684entirely above the semiconductor substrate682, or capacitor566may have portions that extend into the semiconductor substrate682or are otherwise coupled to, or in contact with, the semiconductor substrate682. According to an embodiment, the capacitor566may be formed from a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material of capacitor566may include one or more layers of polysilicon, various oxides, a nitride, or other suitable materials. In various embodiments, the first and second electrodes of capacitor566may include horizontal portions of conductive layers (e.g., portions that are parallel to the top and bottom surfaces of IPD assembly480) and/or vertical portions (e.g., portions that are parallel to the sides of IPD assembly480) of conductive layers that are interconnected. Further, the first and second electrodes of capacitor566may be formed from metal layers and/or from conductive semiconductor materials (e.g., polysilicon). Alternatively, each envelope capacitor566may be, for example, a discrete capacitor that is connected (e.g., using solder, a conductive epoxy, or other means) to a top surface of the IPD assembly480. Although particular two-plate capacitor structures are shown inFIG. 6for capacitors514,534, and566, a variety of other capacitor structures alternatively may be utilized, as would be understood by one of skill in the art based on the description herein.

As discussed previously in conjunction withFIG. 1, a harmonic termination circuit430also is connected between the control terminal (e.g., the gate terminal) of a FET within each transistor die440and a ground reference (e.g., to the conductive layer686on the bottom surface of IPD assembly480). In the embodiment ofFIGS. 5 and 6, the harmonic termination circuit430includes a series combination of a shunt inductance532(e.g., shunt inductive element132,FIG. 1) and a shunt capacitor534(e.g., shunt capacitance134,FIG. 1). The shunt inductance532may be implemented as a set of bondwires, where first ends of the bondwires are connected to the input terminal542of die440(and thus to the control terminal of the FET), and second ends of the bondwires are connected to a conductive bond pad533that is exposed at a top surface of IPD assembly480. To avoid clutteringFIG. 5, only one bondwire in the set of bondwires comprising inductive element532is circled and numbered with reference number532, and only one capacitor534is numbered inFIG. 5. It should be understood that inductive element532includes all bondwires coupled between bond pad533and the input terminal542. Within IPD assembly480, the bond pad533is electrically connected to a first terminal of shunt capacitor534, and a second terminal of shunt capacitor534is electrically connected (e.g., using through substrate vias) to the ground reference (e.g., to the conductive layer686on the bottom surface of IPD assembly480).

According to an embodiment, the shunt capacitor534of harmonic termination circuit430may be implemented as a capacitor that is integrally formed with the IPD substrate of the IPD assembly480. For example, shunt capacitor534may be implemented as an integrated MIM capacitor, which includes first and second conductive electrodes (formed from patterned portions of the conductive layers of build-up structure684) that are aligned with each other and electrically separated by dielectric material of the build-up structure684. A first electrode (or terminal) of the shunt capacitor534is electrically coupled to the conductive bond pad533, and a second electrode (or terminal) of the shunt capacitor534is electrically coupled to the conductive flange406(e.g., using through substrate vias), in an embodiment. In a more specific embodiment, the first electrode of the shunt capacitor534is “directly connected” (as defined previously) to the bond pad533. Because the shunt capacitor534and the bond pad533are “directly connected,” and the bond pad533also has only a trace inductance, in an embodiment, the bondwires532and the shunt capacitor534also may be considered to be “directly connected.” In an alternate embodiment, the shunt capacitor534may be implemented using a discrete capacitor coupled to a top surface of the IPD assembly480, or using another type of capacitor.

According to an embodiment, the harmonic termination circuit430functions as low impedance path to ground for signal energy at a harmonic frequency (e.g., a second harmonic of a fundamental frequency of operation of device400). More specifically, the component values for the shunt inductance532and the shunt capacitance534are selected so that the series combination of the shunt inductance532and shunt capacitance534resonate at or near the second harmonic frequency. For example, the fundamental frequency of operation of device400may be in a range of about 800 megahertz (MHz) to about 6.0 gigahertz (GHz), and thus the second harmonic frequency (and resonant frequency of circuit430) may be in a range of about 1.6 GHz to about 12.0 GHz. According to an embodiment, inductance532may have an inductance value in a range between about 80 pH to about 1 nH, and capacitor534may have a capacitance value in a range between about 1 pF to about 100 pF, although these components may have values outside of these ranges, as well. As discussed above in conjunction withFIG. 1, for example, at a fundamental frequency of operation of 2.0 GHz, which has a second harmonic at 4.0 GHz, inductance532may have an inductance value of about 120 pH, and capacitor534may have a capacitance value of about 12 pF. However, the designed inductance and/or capacitance values may be affected by mutual coupling between bondwires used to implement inductances516,532.

More specifically, and according to an embodiment, the bondwires corresponding to inductive elements516and532are physically configured and arranged, with respect to each other, to exhibit a predictable mutual coupling between adjacent sets of bondwires during operation. More specifically, the bondwire profiles (e.g., the heights and shapes of each set of bondwires) and their proximities to other bondwires result in predictable mutual coupling, during operation, that results in different effective inductance values of the inductive elements516and532, during operation, than the self-inductance values of the inductive elements516and532when each inductance is taken in isolation (i.e., not affected by mutual inductance from other inductances).

As also discussed previously, a bias circuit (e.g., bias circuit190,FIG. 1) also may be coupled to the control terminal (e.g., gate terminal) of the transistor630, and in one embodiment, this connection is made through the IPD assembly480. More particularly, in an embodiment, the first end of at least one bondwire592also may be connected to the conductive bond pad415, and the second end of bondwire592is connected to a bias lead (e.g., bias lead492,FIG. 4). When a bias voltage is provided by an external bias circuit to the bias lead, the bias voltage may be conveyed through bondwires592, conductive landing pad415, bondwires516, and conductive landing pad542to the gate terminal of the FET within transistor die440. According to an embodiment, the series combination of bondwire592and the bias lead (e.g., bias lead492,FIG. 4) may have an inductance value in a range between about 500 pH to about 3000 pH, although the inductance value could be lower or higher, as well.

FIGS. 4-6illustrate embodiments of RF amplifier devices that include input and output leads coupled to a substrate (e.g., with intervening electrical isolation), and a transistor die also coupled to the substrate between the input and output leads. Such RF amplifier devices may be particularly well suited for high-power amplification. Those of skill in the art would understand, based on the description herein, that the various embodiments may be implemented using different forms of packaging or construction, as well. For example, one or multiple amplification paths that include embodiments of the inventive subject matter could be coupled to a substrate such as a PCB, a no-leads type of package (e.g., a quad-flat no-leads (QFN) package), or another type of package. In such embodiments, inputs and outputs of the amplification path(s) could be implemented using conductive lands or other input/output (I/O) structures. Such implementations may be particularly suitable for lower-power amplification systems, for example, including a relatively low-power Doherty amplifier in which main and peaking amplification paths (including bare transistor dies, IPDs, bias circuits, and so on), a power divider, delay and impedance inversion elements, a combiner, and other components may be coupled to the substrate. It should be understood that implementations of the inventive subject matter are not limited to the illustrated embodiments.

FIG. 7is a flowchart of a method for fabricating a packaged RF power amplifier device (e.g., device400,FIG. 4) that includes embodiments of input and output impedance matching circuits, input-side and output-side baseband decoupling circuits, and input-side harmonic termination circuits (e.g., circuits200-205,410,411,430,431,450,451,460-463,FIGS. 2A-2F, 4), in accordance with various example embodiments. The method may begin, in blocks702-704, by forming one or more IPD assemblies. More specifically, in block702, one or more input and output IPDs (e.g., IPD480-483,FIGS. 4-6) may be formed. According to an embodiment, each input IPD (e.g., IPDs480,481) includes components of an impedance matching circuit, a baseband decoupling circuit, and a harmonic termination circuit. For example, each input IPD may include one or more integrated series capacitors (e.g., capacitors120,520,FIGS. 1, 5, 6), one or more integrated shunt capacitors (e.g., capacitors114,119,134,266,514,519,534,566,FIGS. 1, 2, 5, 6), one or more inductive elements (e.g., inductive elements118,262,518,562,FIGS. 1, 2, 5, 6), and one or more resistors (e.g., resistors122,264,522,564,FIGS. 1, 2, 5, 6). As mentioned previously, components associated with DC biasing through the input terminal (e.g., capacitor119,519and resistor122,522,FIGS. 1, 5) may be excluded in embodiments in which biasing is provided through a bias lead. According to an embodiment, each output IPD (e.g., IPDs482,483) also includes components of an impedance matching circuit, and a baseband decoupling circuit. In addition to forming the passive components of each IPD, forming each IPD also includes forming various conductive features (e.g., conductive layers and vias), which facilitate electrical connection between the various components of each circuit. For example, forming the IPDs also may include forming various accessible connection nodes at a surface of each IPD substrate. As discussed previously, the connection nodes may include conductive bond pads, which may accept attachment of inductive elements (e.g., bondwires512,516,532,FIGS. 5, 6). In addition, in block704, when some components corresponding to various circuit elements (e.g., capacitors520,578,FIGS. 5, 6) are implemented as discrete components (rather than integrated components), those discrete components may be coupled to conductors exposed at the surface of each IPD to form one or more IPD assemblies.

In block706, for an air cavity embodiment, an isolation structure (e.g., isolation structure408,FIG. 4) is coupled to a device substrate (e.g., flange406). In addition, one or more active devices (e.g., transistors440,441) and IPD assemblies (e.g., IPD assemblies480-483) are coupled to a portion of the top surface of the substrate that is exposed through an opening in the isolation structure. Leads (e.g., input and output leads402-405, and bias leads492-495, if included) are coupled to the top surface of the isolation structure. For overmolded (e.g., encapsulated) device embodiments, the isolation structure may be excluded, and the substrate and leads may form portions of a leadframe.

In block708, the input lead(s), transistor(s), IPD assembly(ies), and output lead(s) are electrically coupled together. For example, the electrical connections may be made using bondwires between the various device components and elements, as discussed previously. Some of the bondwires correspond to inductive components of input or output matching circuits (e.g., bondwires512,516,FIGS. 4-6), and harmonic termination circuits (e.g., bondwires532,FIGS. 4-6), for example. Finally, in block710, the device is capped (e.g., for an air cavity package) or encapsulated (e.g., with mold compound for an overmolded package). The device may then be incorporated into a larger electrical system (e.g., a Doherty amplifier or other type of electrical system).

An embodiment of an RF amplifier includes a transistor die with a transistor and a transistor input terminal, a multiple-section bandpass filter circuit, and a harmonic termination circuit. The multiple-section bandpass filter circuit is coupled between a first input of a first amplification path and the transistor input terminal, and the multiple-section bandpass filter circuit includes a first connection node coupled to the first input, a first inductive element coupled between the first connection node and a ground reference node, a second connection node, a first capacitance coupled between the first connection node and the second connection node, a second capacitance coupled between the second connection node and the ground reference node, and a second inductive element coupled between the second connection node and the transistor input terminal. The harmonic termination circuit includes a third inductive element and a third capacitance connected in series between the transistor input terminal and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the RF amplifier.

An embodiment of a packaged RF amplifier device includes a device substrate, input and output leads coupled to the device substrate, a transistor die coupled to the device substrate, and a multiple-section bandpass filter circuit coupled the input lead and the transistor input terminal. The transistor die includes a transistor, a transistor input terminal coupled to the input lead, and a transistor output terminal coupled to the output lead. The multiple-section bandpass filter circuit includes a first connection node coupled to the input lead, a first inductive element coupled between the first connection node and a ground reference node, a second connection node, a first capacitance coupled between the first connection node and the second connection node, a second capacitance coupled between the second connection node and the ground reference node, and a second inductive element coupled between the second connection node and the transistor input terminal. The packaged RF amplifier also includes a harmonic termination circuit that includes a third inductive element and a third capacitance connected in series between the transistor input terminal and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device.

An embodiment of a method of manufacturing an RF amplifier device includes coupling an input lead and an output lead to a device substrate, coupling a transistor die to the device substrate between the input and output leads, coupling a multiple-section bandpass filter circuit between the input lead and the transistor input terminal, and coupling a harmonic termination circuit between the transistor input terminal and a ground reference node. The transistor die includes a transistor and a transistor input terminal. The multiple-section bandpass filter circuit includes a first connection node coupled to the input lead, a first inductive element coupled between the first connection node and a ground reference node, a second connection node, a first capacitance coupled between the first connection node and the second connection node, a second capacitance coupled between the second connection node and the ground reference node, and a second inductive element coupled between the second connection node and the transistor input terminal. The harmonic termination circuit includes a third inductive element and a third capacitance connected in series. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.