Memory module and memory controller for controlling a memory module

The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2).

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 from European Patent Application No. 11188806.1 filed Nov. 11, 2011, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a memory module and to a memory controller for controlling a memory module. Further, the invention relates to method for controlling a memory module having a plurality of memory chips and a plurality of connections.

2. Description of Related Art

Memory or computer memory, e.g. based on DRAM technology, can be built in the form of Dual Inline Memory Modules (DIMM). Such a DIMM includes a number of memory chips on a printed circuit board and is plugged into the main board of the computer. The number of connections or connector contacts from the DIMM to the main board is limited by mechanical and reliability issues.

Over time, the memory capacity has grown. A conventional DIMM containing 1 GB of memory has 64 bidirectional data connections, 14 multiplexed address connections and additional connections for clock, status, power and the like. For other markets, such as servers, the format and connector assignments can be different. Since the market for memory is very large, changing the format, including the mechanical dimensions, connector density or type, can be difficult.

Depending on a current application, a computer needs to access memory in different granularity. While some applications read and write entire cash lines of 64 bytes or 128 bytes, other applications can need less data from each address.

However, the pin-out of conventional DIMM fixes the ratio of address transfers and data transfers and hence the optimal granularity. If data is accessed with lower granularity, the data throughput will decrease, because the access rate is limited by the address wires.

U.S. Pat. No. 2010/0036997 A1, a multiple data channel memory module architecture is described. U.S. Pat. No. 2010/0262790 A1 shows memory controllers, methods, and systems supporting multiple memory modes. In U.S. Pat. No. 2010/0293325 A1, memory devices and systems including multi-speed access of memory modules are described. Reference U.S. Pat. No. 6,705,877 B1 shows stackable memory module with variable bandwidth. In U.S. Pat. No. 7,739,441 B1, communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocol is described

M. Awasthi et al. “Handling the problems and opportunities posed by multiple on-chip memory controllers”, PACT'10, Vienna, Austria, ACM 978-1-4503-0178-7/10/09 mentions a solution for handling the problems and opportunities posed by multiple on-chip memory controllers. In F. Cabarcas et al. “Interleaving granularity on high bandwidth memory architecture for CMPs”, IEEE, 978-1-4244-7938-2/10 interleaving granularity on high bandwidth memory architecture for CMPs is described.

Accordingly, it is an aspect of the present invention to provide a memory module with a configurable ratio of address transfers and data transfers.

SUMMARY OF THE INVENTION

In one aspect of the invention, a memory module is provided. The memory module includes a plurality of memory chips, a plurality of connections for connecting the memory module to a processor, wherein a part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips, N≧2.

In a second aspect of the invention, a memory controller for controlling a memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor is provided. The memory controller includes a configurator for configuring the memory module such that a part of the connections is grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips, N≧2.

Similar or functionally similar elements in the figures have been allocated the same reference signs if not otherwise indicated.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The memory module has a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least a part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2).

According to some implementations, the connector assignment can be modified in the present memory module, but the mechanical format and the electrical properties of the connections, in particular wires, between the memory chips and the memory controller controlling the memory module can be unchanged. Particularly, this allows building a memory module with a configurable ratio of address transfers and data transfers. Therefore, each customer can decide on its own how many large data granularity and how many lower data throughput, but higher data transaction rate he chooses. A memory chip can have a package of memory cells, in particular a matrix of memory cells. The connections can include connectors, connector contacts and/or wires.

For the example that N=2, a memory module format is proposed that uses two sets of address connections and half the number of data connections such that the data throughput is reduced, but the number of transactions is increased.

In an embodiment, said part of the connections is configurable such that each set of the N sets of address and control connections is connectable to a respective group of the N separate groups. Thus, each set of the N sets of address and control connections can be allocated to one group of the N separate groups.

In a further embodiment, the storage is configured to provide one selected set of the number of sets of configuration data to a memory controller for configuring the memory module by the selected configuration data.

In a further embodiment, the plurality of connections includes one data connection for each memory chip of the plurality of memory chips.

In a further embodiment, each set of configuration data includes a group indication, N member indications and N capacity indications. The group indication indicates the number N of groups. The N member indications include one member indication for each group, wherein the respective member indication indicates the memory chips of the respective group. The N capacity indications include one capacity indication for each group of the N groups, wherein the respective capacity indication indicates a capacity of the memory chips of the respective group.

InFIG. 1, a schematic block diagram of an embodiment of a memory module10is depicted. The memory module10has four memory chips21-24. Further, the memory module10has a plurality of connections31,32,51-54. The connections31,32,51-54are adapted to connect the memory module10to a processor (not shown). A part of the connections31,32,51-55is configurable to be grouped into two sets of address and control connections31,32for two separatively controllable groups G1, G2of memory chips21-24. Each set of address and control connections31,32can comprise a plurality of physical lines connectable to the processor or to an interface for interfacing with the processor.

Without loss of generality, the memory module10ofFIG. 1has four memory chips21-24. Moreover, without loss of generality, the memory chips21-24are grouped into two groups G1, G2.

In the example ofFIG. 1, a first set31of address and control connections31is connectable to a first group G1including a first memory chip21and a second memory chip22. Further, a second set32of address and control connections is connectable to a second group G2including a third memory chip23and a fourth memory chip24. Moreover, the plurality of connections31,32,51-54includes one data connection51-54for each memory chip21-24of the memory module10. Thus, a first data connection51is provided for the first memory chip21, for example. The memory module10can be embodied as a Dual In-line Memory Module (DIMM).

FIG. 2shows a schematic block diagram of a second embodiment of a memory module10. The second embodiment of the memory module10includes all features of the memory module10ofFIG. 1. Further, the memory module10ofFIG. 2comprises storage40. The storage40can be embodied as EEPROM storage. The storage40is configured to provide a selected set S of configuration data for configuring the connections31,32,51-54from a number of sets S of configuration data.

In this regard,FIG. 3shows a schematic diagram of an embodiment of a configuration data set S. The configuration data set S includes a group indication GI, a member indication MI, a capacity indication CI, a timing information TI, a power supply information PS, a latency information LI and refreshment requirements RR.

For example, the group indication GI indicates the number N of groups, which is two for the example ofFIGS. 1 and 2. The member indication MI indicates the members of memory chips21-24for each of the groups G1, G2. Thus, for the example ofFIGS. 1 and 2, the member indication MI indicates that the first memory chip21and the second memory chip22are part of the first group G1, and the third memory chip23and the fourth memory chip24are part of the second group G2. The capacity indication CI indicates the capacity of the memory chips21,22;23,24of the group G1; G2.

InFIG. 4, a schematic block diagram of the first embodiment of a system1having the memory module10ofFIG. 2and a memory controller60is depicted.

The memory controller60has a configurator61and schematically shown memory controller components62, which are configured by the configurator61over a configuration interface63. Details for the memory components62are given inFIG. 6.

The configurator61is adapted to configure the memory module10such that a part of the connections31,32,51-54is grouped into two sets of address and control connections31,32for two separatively controllable groups G1, G2of memory chips21-24. The connections31,32,51-54are illustrated as a memory bus70inFIG. 4. The configurator61can configure the connections31,32,51-54of the memory bus70in dependence on a configuration data set S which is requested and received from the storage40of the memory module10.

To illustrate this in more detail,FIG. 5shows a schematic block diagram of a second embodiment of a system1having the memory module10ofFIG. 2and the memory controller60. The configurator61ofFIG. 5has a receiver64and a selector65.

The selector65is configured to transmit a request R to the storage40of the memory module10for selecting one set S of the stored configuration data sets. The storage40is adapted to provide the selected configuration data set S to the memory controller60, in particular to the receiver64. Then, the configurator61can be adapted to configure the plurality of connections of the memory bus70in dependence on the received configuration data set S.

Moreover,FIG. 6shows a schematic block diagram of an embodiment of a memory controller60coupled to a memory module10(not shown inFIG. 6) by a memory bus70and to a processor (not shown inFIG. 6) by an address/control interface101and a data interface102.

The memory controller60has the configurator61and a number of memory controller components62. The memory controller components62and the configurator61can be coupled by means of the configuration interface63. By means of the configuration interface63, the configurator61can configure the memory controller components62, in particular on the basis of the received configuration data set S as provided by the storage40of the memory module10(not shown).

The memory controller components62include a line driver91, a memory protocol state machine scheduler62, a command queue93and a multiplexer94coupled between the memory bus70and the address/control interface101.

Further, the memory controller components62include a first data formatter95, a second data formatter96and an Error Correcting Code (ECC) entity97coupled between the line driver91and the data interface102. The line driver91is configured to drive the connections of the memory bus70. The memory protocol state machine scheduler92is configured to control the line driver91. The command queue93is adapted to input address and control data received over the address/control interface101and the multiplexer94for the memory protocol state machine scheduler92.

The first data formatter95coupled between the line driver91and the second data formatter96is configured to format data to be transmitted between the memory module10and the processor within each group G1, G2of the two separatively controllable groups G1, G2of memory chips21-24. The second data formatter96can include a data concentrator and a data splitter for formatting data between the separatively controllable groups G1, G2. The ECC97coupled between the second data formatter96and the data interface102can provide error correction.

The memory controller60can be part of a processor, network component, a graphics accelerator or the like. The interfaces101and102provide a connection for the memory controller to the rest of the system. Through this memory access interfaces101,102, the memory controller60can receive requests for memory accesses, and—if the request requires—data for this request. Further, the memory controller60can also provide results like signaling completion or providing resulting data, e.g. read data through these interfaces101,102.

Request information, such as operation type, address or such is stored in the command queue93. Depending on the connected memory module, for example a conventional one with one address/command address and control connection or a DIMM with two address and control connections, the queue93is split into a number of logical queues. For example inFIGS. 1 and 2, there are two queues required because of the two groups G1, G2. In the present case of splitting, a request distributor can control into which of the two logical queues it is put.

If data is received with the command, the ECC97can compute an error correction code and data is put into one part of the data buffer dependent on the configuration. Then, the data is formatted according to the number of data wires on the memory bus70.

The memory protocol state machine scheduler92creates the signals on the address and control lines, either for one or for two groups of memory chips on the DIMM, for example. If there are two, it operates as two independent state machines. The detailed operations, e.g. bank open/close, precharge, etc., are transmitted over the memory bus70by means of the line driver91which guarantees the right electrical properties, for instance with respect to termination.

For example, data wires are terminated by the memory controller60on a read operation, but by the memory chip21-24on a write operation. Address lines are terminated on the DIMM10, in particular outside the memory chips21-24. For the present memory controller60, this is configurable, i.e. the disabling of the termination necessary for data lines on a read operation is only used, when the wire on the memory bus70is used as a data wire and not as an address and control connection.

Furthermore,FIG. 7shows an embodiment of a sequence of method steps for controlling a memory module. In step701, a memory module is provided which comprises a plurality of memory chips and a plurality of connections for connecting the memory module to a processor.

In step702, the memory module is configured such that a part of the connections is grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2).

FIG. 8shows a second embodiment of a sequence of method steps for controlling a memory module, for example a DIMM, which includes a plurality of memory chips and a plurality of connections for connecting the memory module to the processor. The memory module can be embodied as shown inFIG. 1 or 2.

In step801, a newly connected DIMM is detected during power-up of the processor. In step802, the configuration data set stored in the storage40of the memory module is read to the configurator of the memory controller.

In step803, the memory controller and particularly the memory module are configured. Said step803particularly includes setting the line driver, setting a defined number of active state machines, setting the queue organization of the command queue, setting the first data formatter95and the second data formatter96.

In step804, the remaining processor system is informed about the actual connected DIMM. In step805, the newly connected DIMM is enabled. Thus, the configuration procedure is completed.

Computerized devices can be suitably designed for implementing embodiments of the present invention as described herein. In that respect, it can be appreciated that the methods described herein are largely non-interactive and automated. In exemplary embodiments, the methods described herein can be implemented either in an interactive, partly-interactive or non-interactive system. The methods described herein can be implemented in software (e.g., firmware), hardware, or a combination thereof. In exemplary embodiments, the methods described herein are implemented in software, as an executable program, the latter executed by suitable digital processing devices. In further exemplary embodiments, at least one step or all steps of above method forFIG. 7 or 8can be implemented in software, as an executable program, the latter executed by suitable digital processing devices. More generally, embodiments of the present invention can be implemented wherein general-purpose digital computers, such as personal computers, workstations, etc., are used.

For instance, the system900depicted inFIG. 9schematically represents a computerized unit901, e.g., a general-purpose computer. In exemplary embodiments, in terms of hardware architecture, as shown inFIG. 9, the unit901includes a processor905, memory910coupled to a memory controller915, and one or more input and/or output (I/O) devices940,945,950,955(or peripherals) that are communicatively coupled via a local input/output controller935. The input/output controller935can be, but is not limited to, one or more buses or other wired or wireless connections, as is known in the art. The input/output controller935can have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface can include address, control, and/or data connections to enable appropriate communications among the aforementioned components. For example, the memory910can be embodied by the memory module10ofFIG. 1 or 2. Moreover, the memory controller915can be embodied by the memory controller60ofFIG. 6.

The processor905is a hardware device for executing software, particularly that stored in memory910. The processor905can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer901, a semiconductor based microprocessor (in the form of a microchip or chip set), or generally any device for executing software instructions.

The memory910can include any one or combination of volatile memory elements (e.g., random access memory) and nonvolatile memory elements. Moreover, the memory910can incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory910can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor905.

The software in memory910can include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 9, the software in the memory910includes methods described herein in accordance with exemplary embodiments and a suitable operating system (OS)911. The OS911essentially controls the execution of other computer programs, such as the methods as described herein (e.g.,FIG. 7 or 8), and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

The methods described herein can be in the form of a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed. When in a source program form, then the program needs to be translated via a compiler, assembler, interpreter, or the like, as known per se, which can or cannot be included within the memory910, so as to operate properly in connection with the OS911. Furthermore, the methods can be written as an object oriented programming language, which has classes of data and methods, or a procedure programming language, which has routines, subroutines, and/or functions.

Possibly, a conventional keyboard950and mouse955can be coupled to the input/output controller935. Other I/O devices940-955can include sensors (especially in the case of network elements), i.e., hardware devices that produce a measurable response to a change in a physical condition like temperature or pressure (physical data to be monitored). Typically, the analog signal produced by the sensors is digitized by an analog-to-digital converter and sent to controllers935for further processing. Sensor nodes are ideally small, consume low energy, are autonomous and operate unattended.

In addition, the I/O devices940-955can further include devices that communicate both inputs and outputs. The system900can further include a display controller925coupled to a display930. In exemplary embodiments, the system900can further include a network interface or transceiver960for coupling to a network965.

The network965transmits and receives data between the unit901and external systems. The network965is possibly implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as WiFi, WiMax, etc. The network965can be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and includes equipment for receiving and transmitting signals.

The network965can also be an IP-based network for communication between the unit901and any external server, client and the like via a broadband connection. In exemplary embodiments, network965can be a managed IP network administered by a service provider. Besides, the network965can be a packet-switched network such as a LAN, WAN, Internet network, etc.

If the unit901is a PC, workstation, intelligent device or the like, the software in the memory910can further include a basic input output system (BIOS). The BIOS is stored in ROM so that the BIOS can be executed when the computer901is activated.

When the unit901is in operation, the processor905is configured to execute software stored within the memory910, to communicate data to and from the memory910, and to generally control operations of the computer901pursuant to the software. The methods described herein and the OS911, in whole or in part are read by the processor905, typically buffered within the processor905, and then executed. When the methods described herein (e.g. with reference toFIG. 7 or 8) are implemented in software, the methods can be stored on any computer readable medium, such as storage920, for use by or in connection with any computer related system or method.

As will be appreciated by one skilled in the art, aspects of the present invention can be embodied as a system, method or computer program product. Accordingly, aspects of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects. Furthermore, aspects of the present invention can take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. Any combination of one or more computer readable medium(s) can be utilized.

Program code embodied on a computer readable medium can be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. Computer program code for carrying out operations for aspects of the present invention can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code can execute entirely on the unit901, partly thereon, partly on a unit901and another unit901, similar or not.

More generally, while the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of the present invention. In addition, many modifications can be made to adapt a particular situation to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.