Semicondcutor structure and semiconductor manufacturing process thereof

A semiconductor structure has a semiconductor device, a first seal ring, and a second seal ring. The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and adjacent to edges of the second surface. A semiconductor manufacturing process is also provided.

BACKGROUND

Integrated circuits are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Integrated circuits are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer. The dies of the wafer may be singulated to be packaged at wafer level. Seal ring formation is an important part in the back-end of line semiconductor processes. Seal rings are stress protection structures around integrated circuits, protecting the internal circuit inside semiconductor chips from damage caused by the dicing of the dies from wafers.

DETAILED DESCRIPTION

FIG. 1AtoFIG. 1Gare schematic cross sectionals of various stages in a semiconductor manufacturing process of a semiconductor structure according to some exemplary embodiments of the present disclosure. Referring toFIG. 1A, a wafer100is provided. The wafer100includes a plurality of semiconductor devices110formed in a semiconductor substrate. InFIG. 1A, only one semiconductor device110is shown inFIG. 1Afor illustration. The semiconductor device110is manufactured through a front end of line (FEOL) process, and includes devices such as active devices (e.g., diodes and/or transistors), passive devices (e.g., capacitors and/or resistors), etc. The devices are formed in an active region100A of the semiconductor device110.

Furthermore, an interconnection layer120is formed on the semiconductor devices110of the wafer100. The interconnection layer120is formed by dielectric material layers and metallization layers layer by layer. In some embodiments, the interconnection layer120may include more or less than the number of dielectric material layers shown inFIG. 1A. In alternative embodiments, the interconnection layer120may include more or less than the number of metallization layers shown. The number of metallization layers and the number of dielectric material layers may be adjusted depending on the routing requirement of the respective semiconductor structure. The material of the dielectric material layers in the interconnection layer120includes polymer, polymide, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable dielectric material. The material of the metallization layers in the interconnection layer120includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, but is not limited by the above-mentioned materials.

Further referring toFIG. 1A, in some embodiments, the interconnection layer120includes a seal ring structure122. The seal ring structure122is formed from the dielectric material layers and metallization layers layer by layer as described above. Other portions of the interconnection layer120may include interconnect structures not shown for other routing requirements of the devices formed in the active region100A of the semiconductor device110. The seal ring structure122is formed on the periphery region100B of the semiconductor device110. The periphery region100B of the semiconductor device110does not include the devices usually. The periphery region100B surrounds the active region100A. The seal ring structure122is part of a first seal ring126, and may be formed with the interconnect structures in the interconnection layer120, or be formed independently of the interconnect structures in the interconnection layer120.

Further referring toFIG. 1A, in some embodiments, a top metal layer124is formed with the interconnection layer120, and is formed on the seal ring structure122. The top metal layer124and the seal ring structure122are connected to form the first seal ring126on the first surface110aof the semiconductor device110. The first seal ring126is disposed on the first surface110aof the semiconductor device110. The first seal ring126is in the periphery region100B of the semiconductor device110. In some embodiments, the first seal ring126is electrically floated, or electrically grounded. Furthermore a passivation layer130is formed on the interconnection layer120, and covers the top metal layer124. The passivation layer130and the interconnection layer120are formed through any suitable back end of line (BEOL) process. The description of the material of the passivation layer130can be referred to the material of the dielectric material layers in the interconnection layer120.

As seen inFIG. 1A, the wafer100is provided on a carrier150, and an adhesive layer140is disposed between the wafer100and the carrier150. The adhesive layer140is any material suitable for bonding the wafer100onto the carrier150. The adhesive layer140may be an adhesive tape, adhesive glue, or any other suitable material. The disclosure is not limited thereto. Furthermore, the front side of the wafer100is adhered on the carrier150. That is to say, the wafer100is face down in the carrier150, and the back side of the wafer100is facing up. Thus, the back side of the wafer100can be processed. The wafer100also includes a plurality of scribe lines112(only one is shown), for where the wafer100is to be diced or sawed during the wafer singulation process.

Next, as seen inFIG. 1B, in some embodiments, the wafer100is thinned. As a result, material is removed from the semiconductor device110such that the semiconductor device110is thinned. The wafer100is thinned through any suitable wafer backside thinning process such as mechanical grinding, chemical mechanical polishing (CMP), wet etching and atmospheric downstream plasma (ADP) dry chemical etching (DCE) or combinations thereof, but is not limited by the above-mentioned processes. The wafer thinning process reduces a thickness of the semiconductor device110to a second surface110bof the semiconductor device110.

Next, referring toFIG. 1C, in some embodiments, a conductive layer160is formed on the second surface110bof the semiconductor device110. The conductive layer160is formed by, for example, deposition, sputtering, electroplating, or any other suitable method. A material of the conductive layer160includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, but is not limited by the above-mentioned materials.

Next, referring toFIG. 1D, in some embodiments, a patterned photoresist layer170is formed on the conductive layer160. In some embodiments, the patterned photoresist layer170is formed by forming a photoresist layer through spin coating and then patterning by projecting light through a photo mask (not shown). The material of the photoresist layer170is any suitable photosensitive material used during the photolithography process.

Referring toFIG. 1E, in some embodiments, the patterned photoresist layer170is used as the etch mask, and an etching process is performed towards the conductive layer160to pattern the conductive layer160. The patterning of the conductive layer160forms a second seal ring162. In some embodiments, the conductive layer160is also patterned for forming the required backside metal routing163on the semiconductor device110of the wafer100. That is to say, the backside metal routing163and the second seal ring162are formed in the etching process inFIG. 1E. The backside metal routing163of the patterned conductive layer160′ is formed through patterning in the active region100A of the semiconductor device110, and the second seal ring162is formed in the periphery region100B of the semiconductor device110. In some embodiments, the second seal ring162is electrically floated, or electrically grounded. Then inFIG. 1F, in some embodiments, the patterned photoresist layer170is stripped and removed. The patterned photoresist layer170is removed through any suitable process.

Referring toFIG. 1G, in some embodiments, a passivation layer180is then formed on the second surface110bof the semiconductor device110and covers the backside metal routing163and the second seal ring162. Similar to the dielectric layers in the interconnection layer120and the passivation layer130, the passivation layer180may be deposited on the second surface110bof the semiconductor device110and the backside metal routing163and the second seal ring162of the patterned conductive layer160′. However, the disclosure is not limited thereto; the dielectric layers in the interconnection layer120, the passivation layer130, and the passivation layer180may be formed through any suitable process. The description of the material of the passivation layer180may be referred to the material of the dielectric layers in the interconnection layer120. Furthermore, the wafer100has been diced along the scribe line112inFIG. 1Gto form the semiconductor structure. It can be seen inFIG. 1Gthat the wafer100has been cut along the scribe line112to cingulate the semiconductor structures. After the wafer100has been singulated, the semiconductor structure is debonded from the carrier through any suitable pickup mechanism. Before debonding the semiconductor structure, the adhesiveness in the adhesive layer140may be reduced through any suitable process such as a thermal or chemical process. The semiconductor structures that are debonded may then undergo a packaging process.

As seen inFIG. 1G, the semiconductor structure of the wafer100is formed. The semiconductor structure includes the semiconductor device110having the first surface110aand the second surface110bopposite to the first surface110a. The semiconductor structure includes the first seal ring126disposed on the first surface110aof the semiconductor device110and adjacent to edges110cof the first surface110a. The first seal ring126is on the periphery region100B of the semiconductor device110. The semiconductor structure also includes the second seal ring162disposed on the second surface110bof the semiconductor device110and adjacent to edges110cof the second surface110b. The second seal ring162is on the periphery region100B of the semiconductor device110. Thus, during a wafer dicing process, as the wafer100is sawed or cut at the scribe line112, the first seal ring126and the second seal ring162can stop undesirable damaging towards the semiconductor device110or metallization routing on the front side and back side of the semiconductor device110. In addition, the first seal ring126and the second seal ring162can enable structural reinforcement of the semiconductor structure, thereby preventing operational reliability of the semiconductor device110from being degraded. In some embodiments, the width W1of the second seal ring162is between 1 um and 10 um, and the height H1of the second seal ring162(or the conductive layer160) is between 1 um and 10 um.

FIG. 2AtoFIG. 2Jare schematic cross sectionals of various stages in a semiconductor manufacturing process of a semiconductor structure according to some exemplary embodiments of the present disclosure. Referring toFIG. 2A, a wafer200is provided. The wafer200is similar to the wafer100inFIG. 1A, and similar elements will use similar reference numerals, and similar descriptions will be repeated herein. The wafer200includes at least one semiconductor device210having a first surface210a, an interconnection layer220having a first seal ring226, scribe lines212, and a passivation layer230. The first seal ring226is made up of a seal ring structure222and a top metal layer224. The wafer200is disposed on a carrier250through an adhesive layer240. The semiconductor device210is similar to the semiconductor device110, and has an active region200A and a periphery region200B. The same descriptions will not be repeated herein.

Referring toFIG. 2B, in some embodiments, the wafer200is thinned to a second surface210bof the semiconductor device210, and is similar to the description inFIG. 1B. The same description can be referred to inFIG. 1B. Next, inFIG. 2C, a patterned photoresist layer290is formed on the second surface210b. In some embodiments, the patterned photoresist layer290is formed by forming a photoresist layer through spin coating and then patterning by projecting light through a photo mask (not shown). The material of the photoresist layer290is any suitable material used during the photolithography process.

Next, inFIG. 2D, in some embodiments, a trench214is formed in the second surface210bof the semiconductor device210. The trench214is formed through etching by using the patterned photoresist layer290as a mask. The trench214is formed in the periphery region200B of the semiconductor device210. Then inFIG. 2E, in some embodiments, the patterned photoresist layer290is stripped and removed. The patterned photoresist layer290is removed through any suitable process. In some embodiments, the depth D1(or height) of the trench214is between 1 um and 10 um, and the width W1of the trench214is between 0.5 um and 5 um.

Referring toFIG. 2F, in some embodiments, a conductive layer260is formed conformally on the second surface210band the trench214. The process of forming the conductive layer260may be referred to the description of forming the conductive layer160ofFIG. 1C. The same description will not be repeated herein.

Referring toFIG. 2G, in some embodiments, a patterned photoresist layer270is formed on the conductive layer260. In some embodiments, the patterned photoresist layer270is formed by forming a photoresist layer through spin coating and then patterning by projecting light through a photo mask (not shown). The material of the photoresist layer270is any suitable material used during the photolithography process.

Referring toFIG. 2H, in some embodiments, the patterned photoresist layer270is used as the mask, and an etching process is performed towards the conductive layer260to pattern the conductive layer260. The patterned conductive layer260′ has a second seal ring262and a backside metal routing264. The description of forming the conductive layer260and the second seal ring262can be referred to in the description of the conductive layer160and the second seal ring162inFIG. 1E. The difference is, inFIG. 2H, the second seal ring262is formed on the trench214, such that the shape of the trench214from a top view is conformal to the shape of the second seal ring262from a top view. The second seal ring262overlaps the trench214, and is on the periphery region200B of the semiconductor device210. In some embodiments, the second seal ring262is electrically floated, or electrically grounded. Then inFIG. 2I, in some embodiments, the patterned photoresist layer270is stripped and removed. The patterned photoresist layer270is removed through any suitable process.

Referring toFIG. 2J, in some embodiments, a passivation layer280is then formed on the second surface210bof the semiconductor device210and covers the patterned conductive layer260′. The description of forming the passivation layer280can be referred to the description of forming the passivation layer180inFIG. 1G. The same description will not be repeated herein. Furthermore, the wafer200has been diced along the scribe line212inFIG. 2Jto form the semiconductor structure. The dicing and debonding process can be referred to the description inFIG. 1G, and the same description will not be repeated herein.

As seen inFIG. 2J, the semiconductor structure of the wafer200is formed. The semiconductor structure of the wafer200is similar to the semiconductor structure of the wafer100ofFIG. 1G. The difference is, inFIG. 2J, the semiconductor structure of the wafer200further includes the trench214. By having the trench214, the structure of the second seal ring262is further reinforced and enhanced. In some embodiments, the height H1of the second seal ring262is between 2 um and 20 um, and the width W2of the second seal ring262is between 1 um and 10 um. In some embodiments, the height H2of the conductive layer260is between 1 um and 10 um. Furthermore, it can be seen that the semiconductor structure includes the first seal ring226disposed on the first surface210aof the semiconductor device210and adjacent to edges210cof the first surface210a. The semiconductor structure also includes the second seal ring262disposed on the second surface210bof the semiconductor device210and adjacent to edges210cof the second surface210b.

FIG. 3AtoFIG. 3Iare schematic cross sectionals of various stages in a semiconductor manufacturing process of a semiconductor structure according to some exemplary embodiments of the present disclosure. Referring toFIG. 3A, a wafer300is provided. The wafer300is similar to the wafer100inFIG. 1A, and similar elements will use similar reference numerals, and similar descriptions will be repeated herein. The wafer300includes at least one semiconductor device310having a first surface310a, an interconnection layer320having a first seal ring326, scribe lines312, and a passivation layer330. The first seal ring326is made up of a seal ring structure322and a top metal layer324. The wafer300is disposed on a carrier350through an adhesive layer340. The semiconductor device310is similar to the semiconductor device110, and has an active region300A and a periphery region300B. The same descriptions will not be repeated herein.

Referring toFIG. 3B, in some embodiments, the wafer300is thinned to a second surface310bof the semiconductor device310, and is similar to the description inFIG. 1B. The same description can be referred to inFIG. 1B.

Next, inFIG. 3C, an interconnection layer360is formed. The interconnection layer360is formed by dielectric material layers and metallization layers layer by layer. In some embodiments, the interconnection layer360may include more or less than the number of dielectric material layers shown inFIG. 3C. In alternative embodiments, the interconnection layer360may include more or less than the number of metallization layers shown. The number of metallization layers and the number of dielectric material layers may be adjusted depending on the routing requirement of the respective semiconductor structure. The material of the metallization layers and the dielectric material layers may be referred to the description of the interconnection layer120inFIG. 1A. The same description will not be repeated herein.

Further referring toFIG. 3C, in some embodiments, as the interconnection layer360is formed, a first seal ring structure362is also formed by dielectric material layers and metallization layers layer by layer as described above. Other portions of the interconnection layer360may include other interconnect structures not shown for other routing requirements of the devices in the active region300A of the semiconductor device310. The first seal ring structure362is formed on the periphery region300B of the semiconductor device310. The periphery region300B of the semiconductor device310does not include the devices. The periphery region300B surrounds the active region300A. The first seal ring structure362may be formed with the other interconnect structures in the interconnection layer360, or be formed independently of the other interconnect structures in the interconnection layer360.

Referring toFIG. 3D, in some embodiments, a trench364is formed in the interconnection layer360. The process of forming the trench364is similar to the process of forming the trench214inFIGS. 2C, 2D, and 2E. The same descriptions will not be repeated herein. In some embodiments, the depth D1(or height) of the trench364is between 1 um and 10 um, and the width W1of the trench364is between 0.5 um and 5 um.

Referring toFIG. 3E, a conductive layer370is formed with the interconnection layer360, and is formed conformally on the interconnection layer360, the trench364, and the first seal ring structure362. The process of forming the conductive layer370may be referred to the description of forming the conductive layer160ofFIG. 1C. The same description will not be repeated herein.

Referring toFIG. 3F, in some embodiments, a patterned photoresist layer380is formed on the conductive layer370. In some embodiments, the patterned photoresist layer380is formed by forming a photoresist layer through spin coating and then patterning by projecting light through a photo mask (not shown). The material of the photoresist layer380is any suitable material used during the photolithography process.

Referring toFIG. 3G, in some embodiments, the patterned photoresist layer380is used as the mask, and an etching process is performed towards the conductive layer370to pattern the conductive layer370. The patterning of the conductive layer370forms a second seal ring structure372and a backside metal routing374. The description of forming the conductive layer370and the second seal ring structure372can be referred to in the description of the conductive layer160and the second seal ring162inFIG. 1E. The difference is, inFIG. 3G, the second seal ring structure372is formed on the trench364, such that the shape of the trench364from a top view is conformal to the shape of the second seal ring structure372from a top view. The second seal ring structure372overlaps the trench364and is connected to the first seal ring structure362to form the second seal ring366of the interconnection layer360. The second seal ring366is on the periphery region300B of the semiconductor device310. In some embodiments, the second seal ring366is electrically floated, or electrically grounded. Then inFIG. 3H, in some embodiments, the patterned photoresist layer380is stripped and removed. The patterned photoresist layer380is removed through any suitable process.

Referring toFIG. 3I, in some embodiments, a passivation layer390is then formed on the interconnection layer360and covers the patterned conductive layer370and the second seal ring366. The description of forming the passivation layer390can be referred to the description of forming the passivation layer180inFIG. 1G. The same description will not be repeated herein. Furthermore, the wafer300has been diced along the scribe line312inFIG. 3Ito form the semiconductor structure. The dicing and debonding process can be referred to the description inFIG. 1G, and the same description will not be repeated herein.

As seen inFIG. 3I, the semiconductor structure of the wafer300is formed. The semiconductor structure of the wafer300is similar to the semiconductor structure of the wafer100ofFIG. 1G. The difference is, inFIG. 3I, the semiconductor structure of the wafer300further includes the interconnection layer360having the trench364, and the first seal ring structure362and the second seal ring structure372. By having the interconnection layer360, the semiconductor structure of the wafer300may have additional interconnections and routing on the backside of the semiconductor device310. Furthermore, having the first seal ring structure362and the second seal ring structure372of the second seal ring366is further reinforces and enhances the protection of the metal routing on the back side of the semiconductor device310. In some embodiments, the height H1of the second seal ring366is between 5 um and 60 um, and the width W2of the first seal ring structure362of the second seal ring366is between 1 um and 10 um. In some embodiments, the width W3of the second seal ring structure372of the second seal ring366is between 1 um and 10 um. In some embodiments, the height H2of the conductive layer370is between 1 um and 10 um. Furthermore, it can be seen that the semiconductor structure includes the first seal ring326disposed on the first surface310aof the semiconductor device310and adjacent to edges310cof the first surface310a. The semiconductor structure also includes the second seal ring362disposed on the second surface310bof the semiconductor device310and adjacent to edges310cof the second surface310b.

FIG. 4is a schematic backside view illustrating a semiconductor structure according to some exemplary embodiments of the present disclosure. Referring toFIG. 4,FIG. 4shows the backside of the semiconductor structure of the wafer100. Specifically, the second seal ring162on the second surface110bof the semiconductor device110is shown, and adjacent to the edges110cof the second surface110b. The passivation layer180on the second surface110band covering the second seal ring162is not shown. In addition, the backside metal routing of the patterned conductive layer160is not shown. It can be seen that the second seal ring162is a single seal ring loop pattern. From a plan view of the backside of the semiconductor structure, the shape of the second seal ring162is a square. However, the disclosure is not limited thereto. In other embodiments, the second seal ring162inFIG. 4is a circle, polygon, or any other suitable shape from a plan view. In addition, in other embodiments, the second seal ring162is not a closed loop, but may have openings in the second seal ring162loop pattern. Furthermore, the second seal ring162surrounds the active region100A. The second seal ring162is on the periphery region100B of the semiconductor device110, and the periphery region100B extends to the area of the semiconductor device110outside of the second seal ring162. That is to say, the active region100A is the region within the dotted line labeled as100A. The periphery region100B is the region between the dotted lined area labeled100B to the dotted lined area labeled100A. In some embodiments, the dotted line labeled as100B overlaps with the outermost edges of the semiconductor device110.

FIG. 5is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 5,FIG. 5shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 5is similar to the description of the second seal ring162inFIG. 4. The same descriptions will not be repeated herein. The difference is, in the second seal ring162ofFIG. 5, from a plan view of the backside of the semiconductor structure, the shape of the second seal ring162is an octagon. However, the disclosure is not limited thereto. In other embodiments, the second seal ring162ofFIG. 5is a circle, polygon, or any other suitable shape from a plan view.

FIG. 6is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 6,FIG. 6shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 6is similar to the description of the second seal ring162inFIG. 4. The same descriptions will not be repeated herein. The difference is the second seal ring162ofFIG. 6includes a second seal ring loop164and a plurality of corner structures166. The corner structures166are formed as a same layer as the second seal ring loop164, are disposed between the corners of the semiconductor device110and the second seal ring loop164of the second seal ring162. In some embodiments, from a plan view of the backside of the semiconductor structure110, the description of the shape of the second seal ring162can be referred to inFIG. 5, and will not be repeated herein. In some embodiments, from a plan view of the backside of the semiconductor structure110, the shape of the corner structures166is a triangle, and the number of corner structures166is four. However, the disclosure is not limited thereto. In other embodiments, the shape of the corner structures166is a circle, polygon, or any other suitable shape from a plan view, and the number of corner structures166can be adjusted according to user requirements. The corner structures166further reinforce and enhance the strength of the second seal ring162around the edges of the second seal ring loop164.

FIG. 7is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 7,FIG. 7shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 7is similar to the description of the second seal ring162inFIG. 6. The same descriptions will not be repeated herein. The difference is the shape of the corner structures166inFIG. 7from a plan view is a pentagon. However, the disclosure is not limited thereto. In other embodiments, the shape of the corner structures166is a circle, polygon, or any other suitable shape from a plan view.

FIG. 8is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 8,FIG. 8shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 8is similar to the description of the second seal ring162inFIG. 4. The same descriptions will not be repeated herein. The difference is that the second seal ring162ofFIG. 8is a multiple seal ring loop structure. That is to say, the second seal ring162ofFIG. 8has a first seal ring loop164and a second seal ring loop168. The second seal ring loop168surrounds the first seal ring loop164. The second seal ring loop168and the first seal ring loop164are formed as the same layer to form the second seal ring162. From a plan view of the backside of the semiconductor structure, the shapes of the second seal ring loop168and the first seal ring loop164are squares. However, the disclosure is not limited thereto. In other embodiments, the shapes of the second seal ring loop168and the first seal ring loop164may be circles, polygons, or any other suitable shapes from a plan view. In addition, the shapes of the second seal ring loop168and the first seal ring loop164may be different from each other. In addition, in other embodiments, the second seal ring loop168and the first seal ring loop164are not closed loops, but may have openings in the second seal ring162loop pattern. By being a multiple seal ring loop structure, the second seal ring162is further reinforced and enhanced.

FIG. 9is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 9,FIG. 9shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 9is similar to the description of the second seal ring162inFIG. 8. The same descriptions will not be repeated herein. The difference is, in the second seal ring162ofFIG. 5, from a plan view of the backside of the semiconductor structure, the shapes of the second seal ring loop168and the first seal ring loop164are octagons. However, the disclosure is not limited thereto. In other embodiments, the shapes of the second seal ring loop168and the first seal ring loop164may be circles, polygons, or any other suitable shapes from a plan view. In addition, the shapes of the second seal ring loop168and the first seal ring loop164may be different from each other.

FIG. 10is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 10,FIG. 10shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 10is similar to the description of the second seal ring162inFIG. 8. The same descriptions will not be repeated herein. The difference is, in the second seal ring162ofFIG. 10, further includes a plurality of corner structures166. The corner structures166are formed as a same layer as the first and second seal ring loops164,168, and are disposed between the corners of the semiconductor device110and the second seal ring loop168of the second seal ring162. In some embodiments, from a plan view of the backside of the semiconductor structure110, the description of the shapes of the second seal ring loop168and the first seal ring loop can be referred to inFIG. 9, and will not be repeated herein. In some embodiments, from a plan view of the backside of the semiconductor structure110, the shape of the corner structures166is a triangle, and the number of corner structures166is four. However, the disclosure is not limited thereto. In other embodiments, the shape of the corner structures166is a circle, polygon, or any other suitable shape from a plan view, and the number of corner structures166can be adjusted according to user requirements. The corner structures166further reinforce and enhance the strength of the second seal ring162around the edges of the second seal ring loop168and the first seal ring loop164.

FIG. 11is a schematic backside view illustrating a semiconductor structure according to some other exemplary embodiments of the present disclosure. Referring toFIG. 11,FIG. 11shows the backside of the semiconductor structure of the wafer100according to another embodiment of the disclosure. The description of the second seal ring162inFIG. 11is similar to the description of the second seal ring162inFIG. 10. The same descriptions will not be repeated herein. The difference is the shape of the corner structures166inFIG. 11from a plan view is a pentagon. However, the disclosure is not limited thereto. In other embodiments, the shape of the corner structures166is a circle, polygon, or any other suitable shape from a plan view.

It should be noted that the second seal ring patterns shown inFIG. 4toFIG. 11can also be applied to the wafers200,300in the embodiments ofFIG. 2JandFIG. 3I. That is to say, the second seal rings262and366can also apply the different seal ring patterns shown inFIG. 4toFIG. 11. That is to say, the multiple seal ring loop patterns and corner structures may also have the trench structures214,364and/or the seal ring structure362shown inFIG. 3I. The disclosure is not limited thereto. Furthermore, from a top side view, the first seal rings126,226,326in the embodiments ofFIG. 1A,FIG. 2A, andFIG. 3Acan also apply the different seal ring patterns shown inFIG. 4toFIG. 11. The disclosure is not limited thereto.

According to some embodiments, a semiconductor structure has a semiconductor device, a first seal ring, and a second seal ring. The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and adjacent to edges of the second surface.

According to some embodiments, a semiconductor structure has a semiconductor device, a first interconnection layer, and a second interconnection layer. The semiconductor device has a first surface and a second surface opposite to the first surface. The first interconnection layer is disposed on the first surface of the semiconductor device. The first interconnection layer includes a first seal ring adjacent to edges of the first surface. The second interconnection layer is disposed on the second surface of the semiconductor device. The second interconnection layer includes a second seal ring adjacent to edges of the second surface.

According to some embodiments, a semiconductor manufacturing process includes the following steps. A wafer having at least one semiconductor device is provided. The at least one semiconductor device has a first surface and a second surface, and a first seal ring is disposed on the first surface of the at least one semiconductor device and adjacent to edges of the first surface. A second seal ring is formed on the second surface of the at least one semiconductor device, wherein the second seal ring is adjacent to edges of the second surface.