Semiconductor device having buried gate structure and method of fabricating the same

A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0021726 filed on Feb. 12, 2015, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

The present disclosure relates to a semiconductor device having a buried gate structure and a method of fabricating the same.

Semiconductor devices are widely used in the electronics industry because of their small sizes, multifunctionality, and low manufacturing cost. However, since semiconductor devices have become highly integrated with the development of the electronics industry, various problems have been generated. For example, intervals between cell transistors formed in the same active region have been reduced, and thus electrons moving along a channel of a cell transistor in an on state can move to a channel of adjacent cell transistor in an off state. As a result, data stored in a capacitor connected with the cell transistor in the off state can be lost.

SUMMARY

Example embodiments of the inventive concept may provide semiconductor devices that may mitigate inter-cell interference in the same active region and methods of fabricating the semiconductor devices.

Other example embodiments of the inventive concept may provide electronic devices including the semiconductor device.

In accordance with certain aspects of the inventive concept, a semiconductor device includes a device isolation region defining an active region in a substrate, an active gate structure in the active region, and a field gate structure in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A channel area may be formed between the upper active gate structure and the lower active gate structure. A volume of the gate conductive layer of the upper active gate structure may be smaller than a volume of the gate conductive layer of the lower active gate structure. A top surface of the gate conductive layer of the field gate structure may be located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

In accordance with certain aspects of the inventive concept, a semiconductor device includes a device isolation region configured to define an active region in a substrate, a lower gate structure disposed in the active region, an upper active gate structure vertically spaced apart from the active gate insulating structure on the active gate insulating structure, and a field gate structure disposed in the device isolation region. The upper active gate structure may include a gate conductive layer. Also, the field gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure may be substantially coplanar with a top surface of the lower active gate structure.

In accordance with certain aspects of the inventive concept, a semiconductor device includes a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a filed gate insulating layer and a filed gate conductive layer on the filed gate insulating layer. The active gate structure may include a first gate structure including a blocking insulation layer, a first gate insulating layer on the blocking insulation layer, and a first gate conductive layer on the first gate insulating layer, a second gate structure formed on the first gate structure and vertically spaced apart from the first gate structure. The second gate structure may include a second gate insulating layer and a second gate conductive layer on the second gate insulating layer. A bottom surface of the blocking insulation layer of the first gate structure is lower than a bottom surface of the field gate conductive layer of the field gate structure.

DETAILED DESCRIPTION

Various exemplary embodiments will now be described more fully with reference to the accompanying drawings. The various aspects of the inventive concepts disclosed herein may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Known processes, elements, and techniques are not described with respect to some of the embodiments of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein to describe the relationship of one element or feature to another, as illustrated in the drawings. It will be understood that such descriptions are intended to encompass different orientations in use or operation in addition to orientations depicted in the drawings. For example, if a device is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” is intended to mean both above and below, depending upon overall device orientation.

Unless the context indicates otherwise, terms such as “equal,” “same,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning.

Like numerals refer to like elements throughout the specification. Accordingly, the same numerals and similar numerals can be described with reference to other drawings, even if not specifically described in a corresponding drawing. Further, when a numeral is not marked in a drawing, the numeral can be described with reference to other drawings.

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.

FIG. 1is layout schematically illustrating semiconductor devices according to example embodiments.

Referring toFIG. 1, semiconductor devices according to example embodiments may include gate lines20extending in an X-direction, and bar-shaped active regions11extending in a Z-direction diagonal to the X-direction. The active regions11may be disposed to be staggered in the X-direction as shown inFIG. 1.

As used herein, a semiconductor device may refer to any of the various devices such as shown inFIGS. 2A to 2D, and may also refer, for example, to a transistor or a device such as a semiconductor chip (e.g., memory chip and/or logic chip formed from a wafer), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a package-on-package device including a plurality of packages.

An electronic device, as used herein, may refer to one of these devices and may also include products that include these devices, such as a memory module, a hard drive including additional components, a mobile phone, laptop, tablet, desktop, camera, server, computing system, or other consumer electronics device, etc.

Referring toFIGS. 1 and 2A, a semiconductor device100A according to example embodiments of the inventive concept may include device isolation regions12defining active regions11in a substrate10, and gate structures20. The gate structures20may include active gate structures20A and field gate structures20F. The active gate structures20A may be formed in the active regions11. The field gate structures20F may be formed in the device isolation regions12. The active gate structures20A may include upper active gate structures20AU and lower active gate structures20AL.

The device isolation regions12may include device isolation trenches12aformed in the substrate10, and a device isolation insulating material12bfilling the device isolation trenches12a. The device isolation insulating material12bmay include, for example, silicon oxide.

The active regions11may include a source area11sbetween the active gate structures20A and drain areas11dbetween the active gate structures20A and the device isolation regions12. The source area11sand the drain areas11dmay include, for example, N-type impurities such as phosphorus (P) and/or arsenic (As).

Each of the upper active gate structures20AU may include an upper active gate insulating layer22AU, an upper active gate barrier pattern23AU, an upper active gate electrode pattern24AU and upper active gate capping insulating pattern25AU in an upper active gate trench21AU.

The upper active gate trench21AU may be formed from a surface of the substrate10toward the inside of the substrate10in the active regions11.

The upper active gate insulating layer22AU may be conformally formed on an entire inner wall of the upper active gate trench21AU. The upper active gate insulating layer22AU may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a metal oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, or titanium oxide.

The upper active gate barrier pattern23AU may be conformally formed on the upper active gate insulating layer22AU. The upper active gate barrier pattern23AU may be formed in part of the upper active gate trench21AU. For example, the upper active gate barrier pattern23AU may be formed in a lower portion of the upper active gate trench21AU. The upper active gate barrier pattern23AU may include a barrier metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

The upper active gate electrode pattern24AU may be formed on the upper active gate barrier pattern23AU to partially fill the upper active gate trench21AU. For example, the upper active gate electrode pattern24AU may fill the lower portion of the upper active gate trench21AU. A top surface of the upper active gate electrode pattern24AU and a top surface of the upper active gate barrier pattern23AU may be coplanar. The upper active gate electrode pattern24AU may include a metal such as tungsten or copper.

The upper active gate capping insulating pattern25AU may be formed on the upper active gate insulating layer22AU, the upper active gate barrier pattern23AU and the upper active gate electrode pattern24AU to fill the upper active gate trench21AU. The upper active gate capping insulating pattern25AU may include, for example, silicon nitride.

Each of the lower active gate structures20AL may include a lower active gate tunnel21AL, a lower active gate insulating layer22AL, a lower active gate barrier pattern23AL, a lower active gate electrode pattern24AL, and a lower active gate blocking pattern25AL.

The lower active gate tunnel21AL may be formed in the substrate10to be vertically aligned with the upper active gate trench21AU. The lower active gate tunnel21AL may extend in an X direction. The lower active gate tunnel21AL may be vertically spaced apart from the upper active gate trench21AU. Accordingly, channel areas CA between top surfaces of the lower active gate structures20AL and bottom surfaces of the upper active gate structures20AU may be formed. The channel areas CA may be connected to the active regions11located at both sides of the active gate structures20A. A width of the lower active gate tunnel21AL may be substantially the same as a width of the upper active gate trench21AU. In another embodiment, the width of the lower active gate tunnel21AL may be wider than the width of the upper active gate trench21AU.

The lower active gate insulating layer22AL may be conformally formed on an entire inner wall of the lower active gate tunnel21AL. The lower active gate insulating layer22AL may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a metal oxide. The metal oxide may include hafnium oxide, aluminum oxide, or titanium oxide.

The lower active gate barrier pattern23AL may be conformally formed on the lower active gate insulating layer22AL. The lower active gate barrier pattern23AL may include a barrier metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

The lower active gate electrode pattern24AL may be formed on the lower active gate barrier pattern23AL to fully fill the lower active gate tunnel21AL. The lower active gate electrode pattern24AL may include a metal such as tungsten or copper.

The lower active gate electrode pattern24AL and the lower active gate barrier pattern23AL may have volumes different from volumes of the upper active gate electrode pattern24AU and the upper active gate barrier pattern23AU, respectively. For example, the volumes of the lower active gate electrode pattern24AL and the lower active gate barrier pattern23AL are greater than the volumes of the upper active gate electrode pattern24AU and the upper active gate barrier pattern23AU, respectively. For example, vertical lengths (e.g., thicknesses) of the lower active gate electrode pattern24AL and the lower active gate barrier pattern23AL are greater than vertical lengths of the upper active gate electrode pattern24AU and the upper active gate barrier pattern23AU, respectively. In example embodiments, a thickness of the lower active gate electrode pattern24AL may be greater than a thickness of the upper active gate electrode pattern24AU. In example embodiments, horizontal widths of the lower active gate electrode pattern24AL and the lower active gate barrier pattern23AL are greater than horizontal widths of the upper active gate electrode pattern24AU and the upper active gate barrier pattern23AU.

The lower active gate blocking pattern25AL may be formed beneath the lower active gate tunnel21AL. For example, the lower active gate tunnel21AL may be disposed on the lower active gate blocking pattern25AL. A width of the lower active gate blocking pattern25AL is substantially the same as a width of the lower active gate tunnel21AL. The lower active gate blocking pattern25AL may include, for example, silicon oxide. When the lower active gate insulating layer22AL includes the silicon oxide, a boundary between the lower active gate insulating layer22AL and the lower active gate blocking pattern25AL may disappear. The lower active gate blocking pattern25AL may be relatively thicker than the upper active gate insulating layer22AU and the lower active gate insulating layer22AL.

The field gate structures20F may include a field gate insulating layer22F, a field gate barrier pattern23F, a field gate electrode pattern24F, and field gate capping insulating pattern25F which are formed in a field gate trench21F.

The field gate trench21F may be formed from a surface of the substrate10toward the inside of the substrate10in the device isolation region12. A bottom surface of the field gate trench21F may be located at a lower level than a bottom surface of the upper active gate trench21AU of the upper active gate structure20AU and a bottom surface of the lower active gate tunnel21AL of the lower active gate structure20AL. The bottom surface of the field gate trench21F may be located at a higher level than a bottom surface of the lower active gate blocking pattern25AL of the lower active gate structure20AL. The field gate insulating layer22F may be conformally formed on an entire inner wall of the field gate trench21F. The field gate insulating layer22F may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a metal oxide. The metal oxide may include hafnium oxide, aluminum oxide, or titanium oxide.

The field gate barrier pattern23F may be conformally formed on the field gate insulating layer22F. The field gate barrier pattern23F may be formed in part of the field gate trench21F. For example, the field gate barrier pattern23F may be formed on a lower portion of the field gate trench21F. The field gate barrier pattern23F may include a barrier metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

The field gate electrode pattern24F may be formed on the field gate barrier pattern23F to partially fill the field gate trench21F. For example, the field gate electrode pattern24F may fill the lower portion of the field gate trench21F. A top surface of the field gate electrode pattern24F and a top surface of the field gate barrier pattern23F may be substantially coplanar. The field gate electrode pattern24F may include a metal such as tungsten or copper. In example embodiments, a bottom surface of the field gate electrode pattern24F may be located at a higher level than a bottom surface of the lower active gate blocking pattern25AL.

In example embodiments, the top surfaces of the field gate electrode pattern24F and the field gate barrier pattern23F may be located at a lower level than a bottom surface of the upper active gate structure20AU. For example, the top surfaces of the field gate electrode pattern24F and the field gate barrier pattern23F may be located at a lower level than the bottom surface of the upper active gate trench21AU of the upper active gate structure20AU. For example, the top surface of the field gate electrode pattern24F may be located at a lower level than the bottom surface of the upper active gate electrode pattern24AU of the upper active gate structure20AU. Also, the top surfaces of the field gate electrode pattern24F and the field gate barrier pattern23F may have levels equal to or higher than a top surface of the lower active gate structure20AL. For example, the top surfaces of the field gate electrode pattern24F and the field gate barrier pattern23F may overlap or not overlap the channel areas CA between the upper active gate structures20AU and the lower active gate structures20AL in a horizontal direction.

The field gate capping insulating pattern25F may be formed on the field gate insulating layer22F, the field gate barrier pattern23F and the field gate electrode pattern24F to fill the field gate trench21F. The field gate capping insulating pattern25F may include silicon nitride.

According to example embodiments, the semiconductor device100A may include an active gate structure20A including an upper active gate structure20AU and a lower active gate structure20AL which are vertically spaced apart from each other. Accordingly, channels surrounded by the active gate structures may be formed. As a result, interference between cell transistors can be prevented by blocking electron movement from one channel to an adjacent channel.

In example embodiments, a top surface of the field gate electrode pattern24F formed in a device isolation region12may be formed at a level lower than a bottom surface of an upper gate electrode pattern24AU formed in an active region11. Accordingly, the gate induced drain leakage (GIDL) can be improved by removing the passing gate effect.

In example embodiments, a vertical length (e.g., a thickness) of an upper active gate structure20AU may be reduced. Accordingly, a channel length can be reduced, and thus a read/write speed can be improved by increasing a channel current.

In example embodiments, a lower active gate blocking pattern25AL beneath a lower active gate structure20AL may be formed. Accordingly, it can prevent electrons from moving to an adjacent cell transistor through a lower portion of the lower active gate structure20AL.

FIG. 2Bshows cross-sectional views taken along lines I-I′, II-II′ and III-III′ ofFIG. 1for describing a semiconductor device100B according to example embodiments. In the example embodiments, detailed descriptions of the same content as those of the above-described embodiments will be omitted.

Referring toFIGS. 1 and 2B, a semiconductor device100B according to example embodiments may include lower active insulating structures30AL beneath the upper active gate structures20AU, compared to the semiconductor device100A inFIG. 2A. The lower active insulating structures30AL may be vertically spaced apart from the upper active gate structures20AU.

The lower active insulating structures30AL may include lower active insulating tunnels31AL formed in the substrate10, and a lower active insulating material32AL filling the lower active insulating tunnels31AL. The lower active insulating material32AL may include, for example, silicon oxide. In example embodiments, channel areas CA formed in the active regions11may be surrounded by the upper active gate structures20AU and the lower active insulating structures30AL. Horizontal widths of the upper active gate structures20AU may be substantially the same as horizontal widths of the lower active insulating structures30AL. Vertical lengths of the upper active gate structures20AU may be smaller than vertical lengths of the lower active insulating structures30AL.

FIG. 2Cshows cross-sectional views taken along lines I-I′, II-II′ and III-III′ ofFIG. 1for describing a semiconductor device100C according to example embodiments. In the example embodiments, detailed descriptions of the same content as those of the above-described embodiments will be omitted.

Referring toFIGS. 1 and 2C, a semiconductor device100C according to example embodiments may include a plurality of intermediate active gate structures20AI formed between upper active gate structures20AU and lower active gate structures20AL, compared to the semiconductor device100A inFIG. 2A. The upper active gate structures20AU, the intermediate active gate structures20AI and the lower active gate structures20AL may be vertically spaced apart from each other. For example, first channel areas CA1, second channel areas CA2, and third channel areas CA3may be formed between the upper active gate structures20AU and the intermediate active gate structures20AI, between the intermediate active gate structures20AI, and between the intermediate active gate structures20AI and the lower active gate structures20AL, respectively. For example, the semiconductor device100C may include multi channel areas CA1, CA2, and CA3in the active regions11.

Each of the intermediate active gate structures20AI may include an intermediate active gate tunnel21AI, an intermediate active gate insulating layer22AI conformally formed on inner walls of the intermediate active gate tunnel21AI, an intermediate active gate barrier pattern23AI conformally formed on the intermediate active gate insulating layer22AI, and an intermediate active gate electrode pattern24AI formed on the intermediate active gate barrier pattern23AI to fill the intermediate active gate tunnel21AI.

In example embodiments, a lower active gate structure20AL may have a lower active gate blocking pattern25AL including the same material as a lower active gate insulating layer22AL. The lower active gate blocking pattern25AL may be relatively thicker than the upper active gate insulating layer22AU and also may be relatively thicker than the lower active gate insulating layer22AL.

FIG. 2Dshows cross-sectional views taken along lines I-I′, II-II′ and III-III′ ofFIG. 1for describing a semiconductor device100D according to example embodiments. In the example embodiments, detailed descriptions of the same content as those of the above-described embodiments will be omitted.

Referring toFIGS. 1 and 2D, each of upper active gate structures20AU of a semiconductor device100D according to example embodiments may include air gaps26AU formed between inner sidewalls of an upper active gate trench21AU and upper active gate barrier pattern23AU and an upper active gate insulating layer22AU formed between inner bottom surface of the upper active gate trench21AU and the upper active gate barrier pattern23AU, compared to the semiconductor device100A inFIG. 2A.

FIGS. 3A, 3B, 4A, 4B. . .9A,9B,10,11and12are plan views for describing a method of fabricating a semiconductor device100A according to example embodiments and cross-sectional views taken along lines I-I′, II-II′ and III-III′ of the above plan views.

Referring toFIGS. 3A and 3B, the method of fabricating the semiconductor device100A according to example embodiments may include forming first mask patterns M1on a substrate10, and forming first trenches T1in the substrate10by performing an etching process using the first mask patterns M1as an etching mask. Referring toFIG. 2A, the first trenches T1may be trenches for forming lower active gate structures20AL in active regions11of the substrate10. Each of the first mask patterns M1may be disposed spaced apart from and parallel to each other in a Y direction. Each of the first mask patterns M1may extend in an X direction. Each of the first trenches T1may be disposed spaced apart from and parallel to each other in the Y direction and extend in the X direction. The first mask patterns M1may include, for example, silicon oxide.

Referring toFIGS. 4A and 4B, the method may include forming lower active gate blocking patterns25AL to fill lower portions of the first trenches T1. The lower active gate blocking patterns25AL may include, for example, silicon oxide. The forming of the lower active gate blocking patterns25AL may include forming a silicon oxide layer on the substrate10to fill the first trenches T1, and removing the silicon oxide layer to form the lower active gate blocking patterns25AL on the lower portions of the first trenches T1by performing an etch-back process. For example, the first mask patterns M1may be removed at the same time as partially removing the silicon oxide in the first trenches T1.

Referring toFIGS. 5A and 5B, the method may include forming sacrificial patterns SP on the lower active gate blocking patterns25AL in the first trenches T1. The sacrificial patterns SP may include, for example, silicon-germanium SiGe or silicon nitride SiN. The forming of the sacrificial patterns SP may include forming sacrificial layers on the substrate10to fill the first trenches T1, and removing the sacrificial layer to form the sacrificial patterns SP partially filling the first trenches T1by performing an etch-back process.

Referring toFIGS. 6A and 6B, the method may include forming poly-crystalline silicon patterns15on the sacrificial patterns SP in the first trenches T1to fully fill the first trenches T1. The forming of the poly-crystalline silicon patterns15may include forming a poly-crystalline silicon layer on the substrate10to fill the first trenches T1, and removing the poly-crystalline silicon layer on the substrate10to expose a surface of the substrate10by performing a planarization process.

Referring toFIGS. 7A and 7B, the method may include changing the poly-crystalline silicon patterns15to single-crystalline silicon patterns10aby performing a single crystallization process. The single crystallization process may include, for example, a laser process, a thermal treatment process, a rapid thermal process (RTP), or an annealing process using a furnace. When the single crystallization process is performed, the poly-crystalline silicon patterns15may be single-crystallized using the substrate10located at both sides of the poly-crystalline silicon patterns15as single crystallization seeds. Accordingly, boundaries (dotted lines) between single-crystalline silicon patterns10aand the substrate10may disappear.

Referring toFIGS. 8A and 8B, the method may include forming a device isolation region12defining active regions11in the substrate10. The forming of the device isolation region12may include performing a shallow trench isolation (STI) process. The STI process may include forming a device isolation trench12ain the substrate10and filling the device isolation trench12awith a device isolation insulating material12b. The device isolation insulating material12bmay include, for example, silicon oxide.

Referring toFIGS. 9A and 9B, the method may include forming second mask patterns M2on the active regions11and the device isolation region12, and forming upper active gate trenches21AU and field gate trenches21F in the substrate10by performing an etching process using the second mask patterns M2as an etching mask. Each of the second mask patterns M2may extend in the X direction, and be disposed spaced apart from and parallel to each other in the Y direction. By forming the upper active gate trenches21AU and the field gate trenches21F, the sacrificial patterns SP formed in the active regions11may be exposed. For example, side surfaces of the sacrificial patterns SP may be exposed in the field gate trenches21F.

Referring toFIG. 10, the method may include removing the exposed sacrificial patterns SP. When the sacrificial patterns SP are removed, lower active gate tunnels21AL on the lower active gate blocking patterns25AL in the active regions11may be formed.

Referring toFIG. 11, the method may include conformally forming an upper active gate insulating layer22AU, lower active gate insulating layers22AL and field gate insulating layers22F on inner walls of the upper active gate trenches21AU, the lower active gate tunnels21AL and the field gate trenches21F, respectively. The upper active gate insulating layer22AU, the lower active gate insulating layer22AL, and the field gate insulating layer22F may include silicon oxide or a metal oxide. The metal oxide may include hafnium oxide, aluminum oxide, or titanium oxide. The upper active gate insulating layer22AU, the lower active gate insulating layer22AL, and the field gate insulating layer22F may be formed using, for example, an atomic layer deposition (ALD) process and/or a thermal oxidation process. When the gate insulating layer22is formed using the thermal oxidation process, the upper active gate insulating layer22AU, the lower active gate insulating layer22AL, and the field gate insulating layer22F may not be formed on top surfaces of the second mask patterns M2, top surfaces of the lower active gate blocking patterns25AL exposed in the lower active gate tunnels21AL, and inner walls of the field gate trenches21F.

Referring toFIG. 12, the method may include forming upper active gate barrier patterns23AU and upper active gate electrode patterns24AU partially filling the upper active gate trenches21AU, forming lower active gate barrier patterns23AL and lower active gate electrode patterns24AL fully filling the lower active gate tunnels21AL, and forming field gate barrier pattern23F and field gate electrode patterns24F partially filling the field gate trenches21F.

The forming of the upper active gate barrier patterns23AU and the upper active gate electrode patterns24AU, the lower active gate barrier patterns23AL and the lower active gate electrode patterns24AL, and the field gate barrier patterns23F and the field gate electrode patterns24F may include the following process.

First, the process may include conformally forming a gate barrier layer on the upper active gate insulating layer22AU, the lower active gate insulating layer22AL, and the field gate insulating layer22F. The gate barrier layer may be formed by performing an ALD process. The gate barrier layer may include a barrier metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

Next, the process may include forming a gate electrode layer on the gate barrier layer filling the upper active gate trenches21AU, the lower active gate tunnels21AL, and the field gate trenches21F. The gate electrode layer may be formed by performing an ALD process or a chemical vapor deposition (CVD) process. The gate electrode layer may include a metal such as tungsten or copper.

Next, the process may include forming the upper active gate barrier patterns23AU and the upper active gate electrode patterns24AU, the lower active gate barrier patterns23AL and the lower active gate electrode patterns24AL, and the field gate barrier patterns23F and the field gate electrode patterns24F by partially removing upper portions of the gate barrier layer and the gate electrode layer in the upper active gate trenches21AU and the field gate trenches21F by performing an etch-back process. At this time, top surfaces of the upper active gate barrier patterns23AU are coplanar with top surfaces of the upper active gate electrode patterns24AU. Also, top surfaces of the field gate barrier patterns23F are coplanar with top surfaces of the field gate electrode patterns24F.

Further, the top surfaces of the field gate barrier patterns23F and top surfaces of the field gate electrode patterns24F are located at lower levels than the top surfaces of the upper active gate barrier patterns23AU and top surfaces of the upper active gate electrode patterns24AU, respectively. This can be implemented by varying etching conditions for the gate barrier layer and the gate electrode layer on the upper active gate trenches21AU, and the gate barrier layer and the gate electrode layer on the field gate trenches21F. Alternatively, this can be implemented by forming widths of the upper active gate trenches21AU smaller than widths of the field gate trenches21F and etching the gate barrier layer and the gate electrode layer on the upper active gate trenches21AU with a rate slower than the gate barrier layer and the gate electrode layer on the field gate trenches21F.

Referring toFIG. 2A, the above method may include forming upper active gate capping insulating patterns25AU on the upper active gate insulating layer22AU, the upper active gate barrier patterns23AU, and upper active gate electrode patterns24AU to fill the upper active gate trenches21AU and forming field gate capping insulating patterns25F on the field gate insulating layer22F, the field gate barrier patterns23F, and the field gate electrode patterns24F to fill the field gate trenches21F. The upper active gate capping insulating patterns25AU and the field gate capping insulating patterns25F may include silicon nitride.

FIGS. 13 to 19are cross-sectional views taken along lines I-I′, II-II′ and III-III′ ofFIG. 1for describing a method of fabricating a semiconductor device100B according to example embodiments. In the example embodiments, detailed descriptions of the same content as those of the above-described embodiments will be omitted.

Referring toFIGS. 3A and 3B, a method of fabricating a semiconductor device100B according to example embodiments may include forming the first mask patterns M1on the substrate10, and forming the first trenches T1in the substrate10by performing an etching process using the first mask patterns M1as an etching mask.

Referring toFIG. 13, the method may include filling lower portions of the first trenches T1with a lower active gate insulating material32AL. The lower active gate insulation material32AL may include, for example, silicon oxide.

Referring toFIG. 14, the method may include forming poly-crystalline silicon patterns15on the lower active gate material32AL in the first trenches T1to fully fill the first trenches T1.

Referring toFIG. 15, the method may include changing the poly-crystalline silicon patterns15to single-crystalline silicon patterns10aby performing a single crystallization process. The single crystallization process may include, for example, a laser process, a thermal treatment process, an RTP, or an annealing process using a furnace. Boundaries (dotted lines) between single-crystalline silicon patterns10aformed by the single crystallization process and the substrate10may disappear. As the single crystallization process is performed, lower active gate insulating structures30AL in which lower active gate insulating tunnels31AL are filled with the lower active gate material32AL may be formed.

Referring toFIG. 16, the method may include forming a device isolation region12defining active regions11in the substrate10. The forming of the device isolation region12may include performing an STI process. The STI process may include forming a device isolation trench12ain the substrate10and filling the device isolation trench12awith a device isolation insulating material12b. The device isolation insulating material12bmay include silicon oxide.

Referring toFIG. 17, the method may include forming second mask patterns M2in the active regions11and the device isolation region12, and forming upper active gate trenches21AU and field gate trenches21F in the substrate10by performing an etching process using the second mask patterns M2as an etching mask.

Referring toFIG. 18, the method may include conformally forming upper active gate insulating layers22AU and field gate insulating layers22F on inner walls of the upper active gate trenches21AU and the field gate trenches21F, respectively. The upper active gate insulating layer22AU and the field gate insulating layer22F may include silicon oxide or a metal oxide. The metal oxide may include hafnium oxide, aluminum oxide, or titanium oxide. The upper active gate insulating layer22AU and the field gate insulating layer22F may be formed using, for example, an ALD process and/or a thermal oxidation process.

Referring toFIG. 19, the method may include forming upper active gate barrier patterns23AU and upper active gate electrode patterns24AU partially filling the upper active gate trenches21AU and forming field gate barrier patterns23F and field gate electrode patterns24F partially filling the field gate trenches21F.

Referring toFIG. 2B, the method may include forming upper active gate capping insulating patterns25AU on the upper active gate insulating layer22AU, the upper active gate barrier patterns23AU, and upper active gate electrode patterns24AU to fill the upper active gate trenches21AU and forming field gate capping insulating patterns25F on the field gate insulating layer22F, the field gate barrier patterns23F, and the field gate electrode patterns24F to fill the field gate trenches21F. The upper active gate capping insulating patterns25AU and the field gate capping insulating patterns25F may include silicon nitride.

FIG. 20is a diagram conceptually showing a memory module2100including at least one of the semiconductor devices100A to100D according to certain embodiments. Referring toFIG. 20, the memory module2100may include a module substrate2110, a plurality of memory devices2120disposed on the module substrate2110, and a plurality of terminals2130disposed on a side of the module substrate2110. The module substrate2110may include a printed circuit board (PCB). The memory devices2120may include one of the semiconductor devices100A to100D according to various embodiments described herein. The plurality of terminals2130may include a metal such as copper. Each of the terminals2130may be electrically connected to each of the memory devices2120. Since the memory module2100includes memory devices2120having a low leakage current and superior carrier mobility, device performance can be improved.

FIG. 21is a diagram conceptually showing a semiconductor module2200in accordance with example embodiments. Referring toFIG. 21, the semiconductor module2200may include a processor2220mounted on a module substrate2210, and semiconductor devices2230. The processor2220or the semiconductor devices2230may include at least one of the semiconductor devices100A to100D according to various embodiments described herein. Conductive input/output terminals2240may be disposed on at least one side of the module substrate2210.

FIG. 22is a block diagram conceptually showing an electronic system2300in accordance with example embodiments. Referring toFIG. 22, the electronic system2300may include a body2310, a display unit2360, and an external apparatus2370. The body2310may include a microprocessor unit2320, a power supply2330, a function unit2340, and/or a display controller unit2350. The body2310may be a system board or motherboard including a PCB and/or a case. The microprocessor unit2320, the power supply2330, the function unit2340, and the display controller unit2350may be mounted or disposed on a top surface or an inside of the body2310. The display unit2360may be disposed on the top surface of the body2310or an inside/outside of the body2310. The display unit2360may display an image processed by the display controller unit2350. For example, the display unit2360may include a liquid crystal display (LCD), an active matrix organic light emitting diode (AMOLED), or various display panels. The display unit2360may include a touch screen. Accordingly, the display unit2360may include an input/output function. The power supply2330may supply a current or voltage to the microprocessor unit2320, the function unit2340, the display controller unit2350, etc. The power supply2330may include a rechargeable battery, a socket for a dry cell, or a voltage/current converter. The microprocessor unit2320may receive a voltage from the power supply2330to control the function unit2340and the display unit2360. For example, the microprocessor unit2320may include a CPU or an application processor (AP). The function unit2340may include a touch-pad, a touch-screen, a volatile/nonvolatile memory, a memory card controller, a camera, a lighting, an audio and video playback processor, a wireless transmission/reception antenna, a speaker, a microphone, a USB port, and other units having various functions. The microprocessor unit2320or the function unit2340may include at least one of the semiconductor devices100A to100D according to various embodiments described herein.

Referring toFIG. 23, an electronic system2400in accordance with example embodiments of the inventive concept may include a microprocessor2414, a memory2412, and a user interface2418which performs data communication using a bus2420. The microprocessor2414may include a CPU or an AP. The electronic system2400may further include a random access memory (RAM)2416which directly communicates with the microprocessor2414. The microprocessor2414and/or the RAM2416may be assembled in a single package. The user interface2418may be used to input data to or output data from the electronic system2400. For example, the user interface2418may include a touch-pad, a touch-screen, a keyboard, a mouse, a scanner, a voice detector, a cathode ray tube (CRT) monitor, an LCD, an AMOLED, a plasma display panel (PDP), a printer, a lighting, or various other input/output devices. The memory2412may store codes for operating the microprocessor2414, data processed by the microprocessor2414, or external input data. The memory2412may include a memory controller, a hard disk, or a solid state drive (SSD). The microprocessor2414, the RAM2416, and/or the memory2412may include at least one of the semiconductor devices100A to100D according to various embodiments described herein.

Semiconductor devices according to various embodiments described herein may include gate structures having upper gate structures and lower gate structures and vertically spaced apart from each other in the same active region. Accordingly, channels surrounded by the gate structures may be formed. As a result, interference between cell transistors can be prevented by blocking electron movement from one channel to an adjacent channel.

Further, in the semiconductor devices according to various embodiments described herein, a top surface of the field gate electrode formed in a device isolation region may be formed at a level lower than a bottom surface of an upper gate electrode formed in an active region. Accordingly, the gate induced drain leakage (GIDL) may be improved by removing the passing gate effect.

Furthermore, in the semiconductor devices according to various embodiments described herein, a vertical length of an upper gate structure in an active region may be shortened. Accordingly, a channel length may be reduced, and thus a read/write speed may be improved by increasing channel current.

Other various effects have been described in the above detailed descriptions.

Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of the invention as defined in the claims.