Amplifiers with shunt switches

Amplifiers with shunt switches to mitigate interference are disclosed. In an exemplary design, an apparatus includes an amplifier and a shunt switch. The amplifier has an input operatively coupled to an input/output (I/O) pad of an integrated circuit (IC) chip. The shunt switch grounds the amplifier when the shunt switch is closed. The shunt switch is isolated from the I/O pad and the amplifier input. The amplifier may be a low noise amplifier (LNA) or some other type of amplifier. In an exemplary design, the shunt switch is isolated from the I/O pad by a series switch. The series switch and the shunt switch may be closed when the amplifier is disabled and may be opened when the amplifier is enabled.

BACKGROUND

The present disclosure relates generally to electronics, and more specifically to amplifiers.

Amplifiers are commonly used in various electronic devices to provide signal amplification. Different types of amplifiers are available for different uses. For example, a wireless communication device such as a cellular phone may include a transmitter and a receiver for bi-directional communication. The receiver may include a low noise amplifier (LNA), the transmitter may include a driver amplifier (DA) and a power amplifier (PA), and the receiver and transmitter may include variable gain amplifiers (VGAs).

A wireless device may include a number of LNAs to support different frequency bands, different radio technologies, etc. Only a subset of the LNAs may be enabled at any given moment, and the remaining LNAs may be disabled to conserve battery power. The disabled LNAs should not adversely impact the performance of the wireless device.

DETAILED DESCRIPTION

The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.

Amplifiers with shunt switches are disclosed herein. These amplifiers may be used for various electronic devices such as wireless communication devices (e.g., cellular phones, smartphones, etc.), tablets, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, smartbooks, netbooks, cordless phones, wireless local loop (WLL) stations, Bluetooth devices, consumer electronic devices, etc. For clarity, the use of amplifiers with shunt switches for a wireless communication device is described below.

FIG. 1shows a wireless device110capable of communicating with different wireless communication systems120and122. Wireless systems120and122may each be a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Long Term Evolution (LTE) system, a wireless local area network (WLAN) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1×, Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity,FIG. 1shows wireless system120including one base station130and one system controller140, and wireless system122including one base station132and one system controller142. In general, each wireless system may include any number of base stations and any set of network entities.

Wireless device110may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device110may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, a consumer electronic device, etc. Wireless device110may be capable of communicating with wireless system120and/or122. Wireless device110may also be capable of receiving signals from broadcast stations (e.g., a broadcast station134), signals from satellites (e.g., a satellite150) in one or more global navigation satellite systems (GNSS), etc. Wireless device110may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA lx, TD-SCDMA, GSM, IEEE 802.11, etc.

FIG. 2shows a block diagram of an exemplary design of wireless device110inFIG. 1. In this exemplary design, wireless device110includes a transceiver220coupled to a primary antenna210, a transceiver222coupled to a secondary antenna212, and a data processor/controller280. Transceiver220includes multiple (K) transmitters230pato230pkand multiple (K) receivers240pato240pkto support multiple frequency bands, multiple radio technologies, carrier aggregation, etc. Transceiver222includes M transmitters230sato230smand M receivers240sato240smto support multiple frequency bands, multiple radio technologies, carrier aggregation, receive diversity, multiple-input multiple-output (MIMO) transmission from multiple transmit antennas to multiple receive antennas, etc.

In the exemplary design shown inFIG. 2, each transmitter230includes transmit circuits248and a power amplifier (PA)250. For data transmission, data processor280processes (e.g., encodes and modulates) data to be transmitted and provides an analog output signal to a selected transmitter. The description below assumes that transmitter230pais the selected transmitter. Within transmitter230pa, transmit circuits248paamplify, filter, and upconvert the analog output signal from baseband to radio frequency (RF) and provide a modulated RF signal. Transmit circuits248pamay include amplifiers, filters, mixers, matching circuits, an oscillator, a local oscillator (LO) generator, a phase locked loop (PLL), etc. A PA250pareceives and amplifies the modulated RF signal and provides a transmit RF signal having the proper output power level. The transmit RF signal is routed through an antenna interface circuit224and transmitted via antenna210. Antenna interface circuit224may include switches, duplexers, diplexers, transmit filters, receive filters, matching circuits, a directional coupler, etc. Each remaining transmitter230in transceivers220and222may operate in similar manner as transmitter230pa.

In the exemplary design shown inFIG. 2, each receiver240includes an LNA260and receive circuits262. For data reception, antenna210receives signals from base stations and/or other transmitter stations and provides a received RF signal, which is routed through antenna interface circuit224and provided to a selected receiver. The description below assumes that receiver240pais the selected receiver. Within receiver240pa, LNA260paamplifies the received RF signal and provides an output RF signal. Receive circuits262padownconvert the output RF signal from RF to baseband, amplify and filter the downconverted signal, and provide an analog input signal to data processor280. Receive circuits262pamay include mixers, filters, amplifiers, matching circuits, an oscillator, an LO generator, a PLL, etc. Each remaining receiver240in transceivers220and222may operate in similar manner as receiver240pa.

FIG. 2shows an exemplary design of transmitter230and receiver240. A transmitter and a receiver may also include other circuits not shown inFIG. 2, such as filters, matching circuits, etc. All or a portion of transceivers220and222may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. For example, transmit circuits248, LNAs260, and receive circuits262and may be implemented on one module, which may be an RFIC, etc. Antenna interface circuits224and226may be implemented on another module, which may be a hybrid module, etc. PAs250may be implemented on an RFIC with LNAs260or a module with antenna interface circuits224and226. The circuits in transceivers220and222may also be implemented in other manners.

Data processor/controller280may perform various functions for wireless device110. For example, data processor280may perform processing for data being transmitted via transmitters230and data being received via receivers240. Controller280may control the operation of the various circuits within transceivers220and222. A memory282may store program codes and data for data processor/controller280. Data processor/controller280may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.

Wireless device110may be able to operate in low-band from 698 to 960 megahertz (MHz), mid-band from 1475 to 2170 MHz, and/or high-band from 2300 to 2690 and 3400 to 3800 MHz. Low-band, mid-band, and high-band refer to three groups of bands (or band groups), with each band group including a number of frequency bands (or simply, “bands”).

Wireless device110may support a number of bands. Each band may be used for frequency division duplexing (FDD) or time division duplexing (TDD). Each band used for FDD is associated with (i) a first frequency range for transmission on the uplink from wireless devices to base stations, which may be referred to as a transmit range, and (ii) a second frequency range for transmission on the downlink from base stations to wireless devices, which may be referred to as a receive range. The transmit and receive ranges are from the perspective of a wireless device.

Table 1 lists some bands that may be supported by wireless device110and also provides the transmit range (Uplink/TX) and the receive range (Downlink/RX) for each band. As shown in Table 1, the transmit range of one band may overlap the receive range of another band. For example, the transmit range of 1920 to 1980 MHz for IMT-2000 band overlaps the receive range of 1930 to 1990 MHz for PCS band. Two bands may be considered as overlapping bands if the transmit range of one band overlaps the receive range of another band. In such a scenario, a transmit RF signal from a transmitter for one band may cause interference to a receiver for that band due to insufficient isolation between receivers, as described below.

FIG. 3shows an example of interference due to overlapping bands and insufficient isolation between receivers. In this example, a wireless device300includes (i) an antenna310, (ii) a switchplexer320, (iii) a duplexer330, a PA350, and an LNA360for IMT-2000 band, and (iv) a duplexer332, a PA352, and an LNA362for PCS band. Switchplexer320includes (i) a switch322coupled between node A and duplexer330and (ii) a switch324coupled between node A and duplexer332. Antenna310is coupled to node A. Duplexer330includes a transmit (TX) filter334and a receive (RX) filter335for IMT-2000 band. Duplexer332includes a transmit filter336and a receive filter337for PCS band. PA350and LNA360are coupled to transmit filter334and receive filter335, respectively, within duplexer330for IMT-2000 band. PA352and LNA362are coupled to transmit filter336and receive filter337, respectively, within duplexer332for PCS band. PAs350and352and LNAs360and362are implemented on an IC chip340and are coupled to input/output (I/O) pads370,372,380and382, respectively, on IC chip340. I/O pads370to382may be coupled to solder balls or external pins of an IC package, which may have limited isolation (e.g., 40 decibels (dB) or less of isolation) between solder balls or external pins.

In the example shown inFIG. 3, PA350and LNA360for IMT-2000 band are enabled, and PA352and LNA362for PCS band are disabled. PA350provides a transmit RF signal at +28 dBm in order to obtain the highest required output power of +25 dBm at antenna310. dBm is a ratio of measured power to 1 milliwatt in dB. The transmit RF signal is at +26 dBm after duplexer330due to 2 dB of insertion loss of transmit filter334and is at +25 dBm at antenna310due to 1 dB of insertion loss of closed switch322.

Switch324has 30 dB of rejection when it is opened, and a portion of the transmit RF signal leaks through switch324. The leaked transmit RF signal is at −5 dBm at the input of duplexer332due to 30 dB of rejection of switch324. The passband of receive filter337for PCS band overlaps the passband of transmit filter334for IMT-2000 band, as shown in Table 1. Hence, the leaked transmit RF signal passes through receive filter337for the PCS band and is at −7 dBm at the input of LNA362due to 2 dB of insertion loss of receive filter337. The isolation between I/O pads380and382may be 20 to 40 dB. A portion of the leaked transmit RF signal at the input of LNA362would then leak to the input of LNA360, and this leaked RF signal may be at −27 to −47 dBm at the input of LNA360.

Duplexer330has 55 dB of rejection between transmit filter334and receive filter335. A portion of the transmit RF signal leaks from transmit filter334to receive filter335, and the leaked transmit RF signal is at −27 dBm at the input of LNA360.

As shown inFIG. 3, the leaked transmit RF signal at the input of LNA362may be relatively high (e.g., −7 dBm) due to (i) the finite isolation of switch324and (ii) the receive range of the PCS band overlapping the transmit range of the IMT-2000 band. Even though LNA362is turned off, relatively strong jammers may be coupled between I/O pads380and382and may result in desensitization of the receive path for the IMT-2000 band. A jammer is a large undesired signal.

In an aspect of the present disclosure, a shunt switch may be used to attenuate undesired signals at a disabled first LNA in order to reduce coupling of the undesired signals from the disabled first LNA to an enabled second LNA. The first LNA may be coupled to an I/O pad. In an exemplary design, the shunt switch may be isolated from the I/O pad via a first circuit, which may comprise a series switch and/or other circuit components. In an exemplary design, the shunt switch may be isolated from the input of the first LNA via a second circuit. The shunt switch has parasitic capacitance when it is turned off. This parasitic capacitance acts as a capacitive load that may degrade the sensitivity of the first LNA if the shunt switch and the first LNA input are both coupled directly to the I/O pad. Isolating the shunt switch from the I/O pad via the first circuit and from the first LNA input via the second circuit may mitigate degradation in sensitivity of the first LNA due to the parasitic capacitance of the shunt switch.

FIG. 4Ashows a first circuit topology400for implementing a shunt switch430for an LNA460. In the exemplary design shown inFIG. 4A, a circuit420is coupled between an I/O pad410and node X. Shunt switch430is coupled between node X and circuit ground. A circuit440is coupled between node X and an LNA input450of LNA460. Circuits420and440may each be implemented in various manners, as described below. Shunt switch430is isolated from I/O pad410via circuit420and is isolated from LNA input450via circuit440.

FIG. 4Bshows a second circuit topology402for implementing shunt switch430for LNA460. In the exemplary design shown inFIG. 4B, circuit420is coupled between I/O pad410and node X. Shunt switch430is coupled between node X and circuit ground. LNA460has its input coupled directly to I/O pad410. Shunt switch430is isolated from I/O pad410via circuit420and is also isolated from LNA input450via circuit420.

FIG. 4Cshows a third circuit topology404for implementing shunt switch430for LNA460. In the exemplary design shown inFIG. 4C, circuit420is coupled between I/O pad410and node X. Shunt switch430is coupled between node X and circuit ground. A circuit470is coupled between node X and the output of LNA460. Circuit470may comprise another LNA, a feedback circuit, and/or some other circuit. The feedback circuit may include a resistor, a capacitor, a transistor, some other circuit component, or a combination thereof LNA460has its input coupled directly to I/O pad410. Shunt switch430is isolated from I/O pad410via circuit420and is also isolated from LNA input450via circuit420.

FIG. 4Dshows a fourth circuit topology406for implementing shunt switch430for LNA460. In the exemplary design shown inFIG. 4D. LNA460has its input coupled directly to I/O pad410. Shunt switch430is coupled between an internal node of LNA460and circuit ground. Shunt switch430is isolated from I/O pad410via LNA460and is also isolated from LNA input450via LNA460.

FIGS. 4A to 4Dshow four exemplary designs in which a shunt switch is isolated from an I/O pad via a first circuit and isolated from an LNA input via a second circuit. The second circuit may be different from the first circuit (e.g., as shown inFIG. 4A) or may be the same circuit as the first circuit (e.g., as shown inFIGS. 4B,4C and4D). A shunt switch may also be isolated from an I/O pad and an LNA input in other manners.

FIG. 5shows an exemplary design of a receiver500that implements the first circuit topology inFIG. 4A. In the exemplary design shown inFIG. 5, a circuit520comprising an N-channel metal oxide semiconductor (NMOS) transistor522is coupled between an I/O pad510and node X. NMOS transistor522operates as a series switch and has its source coupled to I/O pad510, its drain coupled to node X, and its gate receiving a51control signal. A shunt switch530implemented with an NMOS transistor532is coupled between node X and circuit ground. NMOS transistor532has its source coupled to circuit ground, its drain coupled to node X, and its gate receiving a S2control signal.

A circuit540is coupled between node X and LNA input550. In the exemplary design shown inFIG. 5, circuit540includes (i) a variable resistor542coupled between node X and node B, (ii) a variable resistor544coupled between node B and circuit ground, and (iii) an alternating current (AC) coupling capacitor546coupled between node B and LNA input550. Resistors542and544may have their values adjusted to obtain the desired attenuation of an input RF signal received via I/O pad510. Circuit540may also include only AC coupling capacitor546coupled between node X and LNA input550and/or other circuit components. Shunt switch530is isolated from I/O pad510via circuit520and is also isolated from LNA input550via circuit540.

In the exemplary design shown inFIG. 5, LNA560includes a gain NMOS transistor564, a cascode NMOS transistor566, and a load circuit568. Gain transistor564has its source coupled to circuit ground and its gate coupled to LNA input550. Cascode transistor566has its source coupled to the drain of gain transistor564, its gate receiving a Vb bias voltage, and its drain providing an output RF signal (RFout). Load circuit568is coupled between a power supply voltage and the drain of cascode transistor566. AC coupling capacitor546enables gain transistor564to be biased with a proper bias voltage and allows shunt switch530to be closed without impacting the DC operation of LNA560.

When LNA560is enabled, series switch520may be closed, and shunt switch530may be opened. LNA560may then amplify an input RF signal received via I/O pad510and provide an output RF signal. When LNA560is disabled, series switch520and shunt switch530may both be closed. The input RF signal may then be shorted to circuit ground via switches520and530, which may reduce interference to another LNA that is enabled.

FIG. 6shows an exemplary design of a receiver600that implements the second circuit topology inFIG. 4Band also the third circuit topology inFIG. 4C. In the exemplary design shown inFIG. 6, a circuit620comprising an NMOS transistor622is coupled between an I/O pad610and node X. A shunt switch630implemented with an NMOS transistor632is coupled between node X and circuit ground. A high-gain LNA660has its LNA input650coupled directly to I/O pad610and its output coupled to node D. A low-gain LNA662has its input coupled to node X and its output coupled to node D. Low-gain LNA662may be implemented with circuit540and LNA560inFIG. 5or with some other LNA circuit design. High-gain LNA660may be implemented with a modified version of LNA560, which includes a source degeneration inductor coupled between the source of NMOS transistor564and circuit ground. High-gain LNA660may also be implemented with LNA560or with some other LNA circuit design.

High-gain LNA660and low-gain LNA662may be used for a particular band K (e.g., PCS band) and may operate in one of three modes at any given moment. In a first mode, high-gain LNA660may be enabled and low-gain LNA662may be disabled when band K is selected and the input RF signal is sufficiently small, e.g., when the received power of the input RF signal is below a low threshold. In the first mode, series switch620may be opened, and shunt switch630may be closed. In a second mode, low-gain LNA662may be enabled and high-gain LNA660may be disabled when band K is selected and the input RF signal is not small. In the second mode, series switch620and shunt switch630may both be opened. In a third mode, high-gain LNA660and low-gain LNA662may both be disabled when band K is not selected. In the third mode, series switch620and shunt switch630may both be closed. The use of high-gain LNA660and low-gain LNA662for band K may improve performance and reduce power consumption across different input RF signal levels.

If shunt switch630is coupled directly at the input of high-gain LNA660, then the sensitivity of LNA660may be degraded when shunt switch630is opened. Hence, shunt switch630may be placed at the input of low-gain LNA662, after series switch620. Shunt switch630is isolated from I/O pad610via series switch620and is also isolated from LNA input650via series switch620.

Isolating shunt switch630from I/O pad610and LNA input650may provide various advantages. First, series switch620may have a relatively large size in order to obtain a low On resistance when series switch620is closed. Hence, a low resistance path from I/O pad610to circuit ground may be obtained via switches620and630when both switches are closed. This low resistance path to circuit ground may effectively attenuate undesired signals and filter out TX jammers when band K is not selected. Second, shunt switch630has parasitic capacitance at node X when it is opened, but this parasitic capacitance may have negligible impact on the performance of enabled LNA660or662. Low-gain LNA662has lower sensitivity requirements since it is enabled when the input RF signal level is sufficiently strong. Low-gain LNA662may thus be able to handle the additional capacitive loading due to the parasitic capacitance of shunt switch630with negligible degradation to sensitivity and can meet its sensitivity requirements. The additional capacitive loading of shunt switch630is isolated from LNA input650via series switch620and may thus have negligible impact on the performance of high-gain LNA660.

FIG. 7shows an exemplary design of a receiver700that implements the fourth circuit topology inFIG. 4D. In the exemplary design shown inFIG. 7, an LNA760has its LNA input750coupled directly to an I/O pad710and its output providing an output RF signal. LNA760includes a source degeneration inductor762, a gain NMOS transistor764, a cascode NMOS transistor766, and a load circuit768, which are coupled as shown inFIG. 7. A shunt switch730implemented with an NMOS transistor732is coupled between the drain of gain transistor764and circuit ground. Shunt switch730is isolated from I/O pad710via LNA760and is also isolated from LNA input750via LNA760.

In the exemplary design shown inFIG. 7, shunt switch730is coupled to the drain of gain transistor764. This exemplary design may be used if source degeneration inductor762is not shared by two LNAs covering two overlapping bands (e.g., not shared by LNAs360and362inFIG. 3for IMT-2000 and PCS bands). Shunt switch730may be opened when LNA760is enabled and may be closed when LNA760is disabled. Shunt switch730has parasitic capacitance when it is turned off, and the parasitic capacitance may impact the performance of LNA760when it is enabled. The impact due to the parasitic capacitance of shunt switch730may increase at higher frequency. Hence, LNA760may be designed to account for the parasitic capacitance of shunt switch730.

In an exemplary design, LNAs for different bands may be implemented with separate circuits, e.g., as shown inFIG. 3. The isolation between these LNAs may then be dependent on the coupling between the LNAs, e.g., between the I/O pads of the LNAs, as shown inFIG. 3. In another exemplary design, LNAs for different bands may share one or more circuit components (e.g., a source degeneration inductor) in order to reduce component count, circuit area, and cost. The isolation between these LNAs may be dependent on coupling via the share circuit component(s).

FIG. 8Ashows an exemplary design of a receiver800with two LNAs860aand860bsharing a source degeneration inductor862and a load circuit868. LNA860acovers band A (e.g., IMT-2000 band) and includes a gain NMOS transistor864aand a cascode NMOS transistor866a, which are coupled as shown inFIG. 8A. LNA860bcovers band B (e.g., PCS band) and includes a gain NMOS transistor864band a cascode NMOS transistor866b, which are coupled as shown inFIG. 8A. Inductor862has one end coupled to the sources of gain transistors864aand864band the other end coupled to circuit ground. Load circuit868is coupled to the drains of cascode transistors866aand866b. The gate of gain transistor864acorresponds to an LNA input850aof LNA860aand is coupled to an I/O pad810a. The gate of gain transistor864bcorresponds to an LNA input850bof LNA860band is coupled to an I/O pad810b. The drains of cascode transistors866aand866bare coupled together and provide an output RF signal (RFout) for LNA860aor860b.

FIG. 8Bshows an exemplary design of a receiver802with two LNAs860aand860bsharing source degeneration inductor862and load circuit868and implementing the second circuit topology inFIG. 4B. Receiver802includes LNA860afor band A and LNA860bfor band B, as described above forFIG. 8A. Receiver802further includes (i) a circuit820coupled between I/O pad810band node X and (ii) a shunt switch830coupled between node X and circuit ground. Circuit820comprises an NMOS transistor822operating as a series switch and is coupled between I/O pad810band node X. Shunt switch830comprises an NMOS transistor832coupled between node X and circuit ground.

The exemplary design inFIG. 8Bincludes series switch820and shunt switch830that can mitigate TX jammers from a transmitter for band A (e.g., IMT-2000 band), which overlaps with band B (e.g., PCS band). A series switch and a shunt switch may be used to mitigate TX jammers from a transmitter for band B and may be coupled to I/O pad810ain similar manner as series switch820and shunt switch830to I/O pad810b.

Receiver802operates as follows. When band A is selected, LNA860ais enabled, LNA860bis disabled, and series switch820and shunt switch830are both closed. LNA860areceives the first input RF signal via I/O pad810aand provides an output RF signal. Since series switch820and shunt switch830are closed, the second input RF signal from I/O pad810bis shorted to circuit ground and causes little interference to the first input RF signal. Conversely, when band B is selected, LNA860bis enabled, LNA860ais disabled, and series switch820and shunt switch830are both opened. LNA860breceives the second input RF signal via I/O pad810band provides an output RF signal.

In one exemplary design, LNA860bmay be a high-gain LNA for band B. Receiver802may include a low-gain LNA for band B having its input coupled to node X, e.g., as shown inFIG. 6. The high-gain LNA may be implemented in similar manners as LNA760inFIG. 7. The low-gain LNA may be implemented with circuit540and LNA560inFIG. 5. The high-gain LNA and low-gain LNA may also be implemented in other manners.

As described above, low-band, mid-band, and high-band may each include a number of bands. Each band may cover up to 200 MHz and may include one or more carriers. Each carrier may cover up to 20 MHz in LTE. LTE Release 11 supports 35 bands, which are referred to as LTE/UMTS bands and are listed in 3GPP TS 36.101.

A wireless device may support carrier aggregation, which is operation on multiple carriers. Carrier aggregation may also be referred to as multi-carrier operation. The wireless device may be configured with up to 5 carriers in one or two bands for carrier aggregation in LTE Release 11.

In general, carrier aggregation (CA) may be categorized into two types—intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.

FIG. 9Ashows an example of intra-band CA. In the example shown inFIG. 9A, a wireless device is configured with two carriers CA1 and CA2 in the same band, which is Band 2 or PCS band. For FDD, each carrier is associated with a transmit frequency channel and a receive frequency channel, which are separated by a fixed duplex spacing defined for the band in which the carrier belongs. The wireless device may send and receive transmissions on carriers CA1 and CA2 within the same band.

FIG. 9Bshows an example of inter-band CA. In the example shown inFIG. 9B, a wireless device is configured with two carriers in different bands, which include carrier CA1 in Band 2 and carrier CA2 in Band 4. The wireless device may send and receive transmissions on carriers CA1 and CA2 in different bands.

FIGS. 9A and 9Bshow two examples of intra-band CA and inter-band CA. Intra-band CA and inter-band CA may also be supported for other combinations of bands and band groups.

For intra-band CA, if a transmit frequency channel of a given carrier C overlaps a receive frequency channel of a band Q supported by the wireless device, then a transmit RF signal for carrier C may appear at the input of a disabled LNA for band Q. The transmit RF signal may leak into the receive path for carrier C, and the leaked transmit RF signal may appear as a TX jammer, e.g., as shown inFIG. 3.

For inter-band CA, a transmit RF signal for one carrier CA1 may act as interference to a receiver for another carrier CA2 and may desensitize the receiver for carrier CA2. For both intra-band CA and inter-band CA, a first transmit RF signal for carrier CA1 and/or a second transmit RF signal for carrier CA2 may cause third-order intermodulation product (IMD3) to fall on a receive frequency channel for carrier CA1. The IMD3 may act as interference to an enabled LNA for carrier CA1. The interference caused by the leaked transmit RF signal may be more problematic if a leakage path through a disabled LNA is not sufficiently isolated from the enabled LNA. Carrier aggregation may be supported for a large number of bands, and it may be challenging to consider all possible desensitization and intermodulation distortion scenarios. Hence, shunt switches may be used for all LNAs, or just LNAs deemed to be more problematic in coupling interference, in order to improve the performance of the enabled LNAs.

LNAs to support intra-band CA and inter-band CA may be implemented in various manners. In an exemplary design, LNAs860aand860binFIG. 8Bmay be used to receive two input RF signals for two bands. Either LNA860aor860bmay be enabled to amplify its input RF signal and provide an output RF signal. In another exemplary design, LNAs660and662inFIG. 6may be used to support one or more bands for intra-band CA and inter-band CA. Either high-gain LNA660or low-gain LNA662may be enabled to amplify an input RF signal and provide an output RF signal. Intra-band CA and inter-band CA may also be supported with LNAs implemented in other manners. Shunt switches may be used for the LNAs to mitigate coupling of interference from the disabled LNAs to the enabled LNAs.

A shunt switch that is isolated from both an I/O pad and an LNA input of a first LNA may be used to mitigate interference to a second LNA. The first LNA may be for a first band (e.g., PCS band) and the second LNA may be for a second band (e.g., IMT-2000 band). When the second band is selected, the shunt switch may improve the sensitivity of the second LNA in the presence of a TX jammer in the second band by shorting the TX jammer at the first LNA. When the first band is selected, the shunt switch may have negligible adverse impact on the performance of the first LNA since it is isolated from the I/O pad and the LNA input of the first LNA.

Performance of a receiver with two LNAs for two overlapping bands (e.g., IMT-2000 and PCS bands) was simulated with and without a shunt switch. The simulation indicates that the performance of the receiver may be improved by using the shunt switch.

FIG. 10Ashows noise figure (NF) of an enabled LNA (e.g., enabled LNA360for IMT-2000 band inFIG. 3) versus transmit power at a disabled LNA (e.g., disabled LNA362for PCS band inFIG. 3). The vertical axis shows noise figure in units of dB, with a lower noise figure being better. The horizontal axis shows transmit power at the input of the disabled LNA in units of dBm. A plot1010shows noise figure of the enabled LNA versus transmit power at the disabled LNA when a shunt switch is used for the disabled LNA and is closed. A plot1012shows noise figure of the enabled LNA versus transmit power at the disabled LNA when a shunt switch is not used for the disabled LNA. Plots1010and1012show the enabled LNA having significantly better noise figure at higher transmit power levels (e.g., greater than −5 dBm) when the shunt switch is used.

FIG. 10Bshows gain compression of the enabled LNA versus transmit power at the disabled LNA. Strong TX jammers at the enabled LNA may cause saturation of the LNA, which may then reduce the gain of the LNA and result in gain compression. The vertical axis shows gain compression in units of dB, with less gain compression being better. The horizontal axis shows transmit power at the input of the disabled LNA in units of dBm. A plot1020shows gain compression of the enabled LNA versus transmit power at the disabled LNA when a shunt switch is used for the disabled LNA and is closed. A plot1022shows gain compression of the enabled LNA versus transmit power at the disabled LNA when a shunt switch is not used for the disabled LNA. Plots1020and1022show the enabled LNA having significantly less gain compression at higher transmit power levels (e.g., greater than −5 dBm) when the shunt switch is used.

FIG. 10Cshows triple beat input-inferred third-order interception point (TB-IIP3) of the enabled LNA versus transmit power at the disabled LNA. TB-IIP3 is related to cross-intermodulation between two TX jammers and one RX jammer and is a measure of linearity of an amplifier. The vertical axis shows TB-IIP3 in units of dBm, with higher TB-IIP3 being better. The horizontal axis shows transmit power at the input of the disabled LNA in units of dBm. A plot1030shows TB-IIP3 of the enabled LNA versus transmit power at the disabled LNA when a shunt switch is used for the disabled LNA and is closed. A plot1032shows TB-IIP3 of the enabled LNA versus transmit power at the disabled LNA when a shunt switch is not used for the disabled LNA. Plots1030and1032show the enabled LNA having better TB-IIP3 when the shunt switch is used.

In an exemplary design, an apparatus (e.g., a wireless device, an IC chip, a circuit module, etc.) may include an amplifier and a shunt switch. The amplifier (e.g., LNA460inFIGS. 4A to 4D) may have an amplifier input operatively (e.g., directly or indirectly) coupled to an I/O pad of an IC chip. The shunt switch (e.g., shunt switch430inFIGS. 4A to 4D) may be coupled between a node and circuit ground and may ground the amplifier when the shunt switch is closed. The amplifier is grounded by shorting the node to which the shunt switch is coupled to circuit ground, which may then inhibit the amplifier from causing interference to other circuits. The shunt switch may be isolated from the I/O pad and the amplifier input.

The amplifier may correspond to LNA460inFIGS. 4A to 4D. The amplifier may receive an input RF signal via the I/O pad and provide an output RF signal when the amplifier is enabled. The amplifier may also be an amplifier of some other type. The shunt switch may be isolated from the I/O pad by a first circuit, which may correspond to circuit420inFIGS. 4A to 4Cor LNA460inFIG. 4D. The shunt switch may be isolated from the amplifier input by a second circuit, which may correspond to circuit440inFIG. 4A, circuit420inFIGS. 4B and 4C, or LNA460inFIG. 4D. The first circuit may be the same as the second circuit or may be different from the second circuit. In an exemplary design, the amplifier input may be coupled directly to the I/O pad, and the shunt switch may be isolated from the I/O pad and the amplifier input by the same circuit, e.g., as shown inFIGS. 4B to 4D.

In an exemplary design, a series switch (e.g., switch520inFIG. 5, switch620inFIG. 6, or switch820inFIG. 8B) may be coupled between the I/O pad and the shunt switch. The series switch and the shunt switch may be closed when the amplifier is disabled and may be opened when the amplifier is enabled.

In an exemplary design, a circuit may be coupled between the shunt switch and the amplifier input and may comprise at least one of a resistor divider network and an AC coupling capacitor, e.g., as shown inFIG. 5. In an exemplary design, the apparatus may further include a feedback circuit (e.g., circuit470inFIG. 4C) coupled between the shunt switch and an output of the amplifier.

In an exemplary design, the apparatus may further include a second amplifier having an input coupled to the shunt switch. The amplifier may be a high-gain amplifier (e.g., high-gain LNA660inFIG. 6). The second amplifier may be a low-gain amplifier (e.g., low-gain LNA662inFIG. 6) having a smaller gain than the high-gain amplifier. The shunt switch may be opened when the second amplifier is enabled and may be closed when the amplifier and the second amplifier are disabled.

In another exemplary design, the apparatus may further include a second amplifier having an input operatively coupled to a second I/O pad. The amplifier (e.g., LNA810binFIG. 8B) and the second amplifier (e.g., LNA810ainFIG. 8B) may share a source degeneration inductor (e.g., inductor862).

In an exemplary design, the amplifier may comprise a gain transistor (e.g., gain transistor764inFIG. 7). The shunt switch may be coupled between the drain of the gain transistor and ground, e.g., as shown inFIG. 7.

In an exemplary design, the amplifier may cover a first band (e.g., PCS band) that overlaps a second band (e.g., IMT-2000 band) supported by the apparatus. The shunt switch may be opened when the first band is selected and the amplifier is enabled. The shunt switch may be closed when the second band is selected and the amplifier is disabled.

In an exemplary design, the apparatus may support carrier aggregation. The amplifier may receive an input RF signal comprising transmissions sent on multiple carriers at different frequencies to the apparatus and may provide an output RF signal. The amplifier may be used to amplify the input RF signal for one or more carriers being received. The shunt switch may be closed when the amplifier is disabled. In another exemplary design, the amplifier is not used to receive an input RF signal for carrier aggregation. The shunt switch may be closed when the amplifier is disabled in order to mitigate interference to one or more amplifiers that are enabled to receive one or more input RF signals for carrier aggregation.

In another exemplary design, an apparatus (e.g., a wireless device, an IC chip, a circuit module, etc.) may include an amplifier, a series switch, and a shunt switch. The amplifier may have an amplifier input coupled to an I/O pad of an IC chip. The amplifier may comprise an LNA or some other type of amplifier. The series switch may be coupled between the I/O pad and a node. The shunt switch may be coupled between the node and circuit ground and may be isolated from the I/O pad and the amplifier input by the series switch.

FIG. 11shows an exemplary design of a process1100for controlling an amplifier. Process1100may be performed by a wireless device or by some other entity. An amplifier having an amplifier input operatively coupled to an I/O pad of an IC chip may be enabled or disabled (block1112). A shunt switch may ground the amplifier when the shunt switch is closed (block1114). The shunt switch may be isolated from the I/O pad and the amplifier input. In an exemplary design, the shunt switch may be isolated from the I/O pad by a series switch, which may be closed when the amplifier is disabled (block1116).

The amplifiers with shunt switches described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc. The amplifiers with shunt switches may be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), NMOS, P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

An apparatus implementing the amplifiers with shunt switches described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.