Semiconductor structure and method making the same

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

BACKGROUND

In semiconductor technology, an integrated circuit pattern can be formed on a substrate using various processes including a photolithography process, ion implantation, deposition and etch. Damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. During a damascene process, trenches are formed in a dielectric material layer, copper or tungsten is filled in the trenches, then a chemical mechanical polishing (CMP) process is applied to remove excessive metal on the dielectric material layer and planarize the top surface. Studies and researches have been conducted to search, new conductive, dielectric materials, and new process integration schemes for a better interconnection. New interconnection materials, such as integrating copper metallurgy in place of traditional aluminum can be used to reduce the resistance component of the RC time delay. New insulating material with a lower dielectric constant (k) than the incumbent silicon dioxide can be applied to reduce the capacitance component as well as cross-talk between conductive lines to minimize time delay and power dissipation. In addition, metal capping or silicide capping can be used to overcome the reliability problem caused by the dimensions scaling down.

Although existing approaches have been generally serving their intended purposes, they have not been entirely satisfactory in all respects. Accordingly, a semiconductor structure including a cap layer and a method making the same are needed.

DETAILED DESCRIPTION

FIG. 1illustrates a flowchart of a method100to form an integrated circuit (IC) structure including an aluminum (Al)-containing dielectric layer according to some embodiments of the present invention.FIGS. 2-5are cross sectional views of an IC structure200including an Al-containing dielectric layer during various fabrication stages using the method100ofFIG. 1, constructed according to various aspects of the present disclosure in one or more embodiments. The method100and the IC structure200are collectively described below with reference toFIGS. 1-5. Additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced or eliminated for additional embodiments of the method. The discussion that follows illustrates various embodiments of the IC structure200that can be fabricated according to the method100ofFIG. 1.

Referring toFIGS. 1 and 2, the method100begins at step102by providing a semiconductor substrate202. The semiconductor substrate202may include silicon (Si). Alternatively or additionally, the substrate202may include other elementary semiconductor such as germanium (Ge). The substrate202may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate202may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, the substrate202includes an epitaxial layer. For example, the substrate202may have an epitaxial layer overlying a bulk semiconductor. In some embodiments, the substrate202may include a semiconductor-on-insulator (SOI) structure. For example, the substrate202may include a buried oxide layer formed by a process such as separation by implanted oxygen or other suitable technique, such as wafer bonding and grinding.

The substrate202may also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, light doped region (LDD), heavily doped source and drain (S/D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED). The substrate202may further include other functional features such as a resistor or a capacitor formed in and on the substrate. In some embodiments, the substrate202may further include lateral isolation features provided to separate various devices formed in the substrate202. The isolation features may include shallow trench isolation (STI) features to define and electrically isolate the functional features. In some examples, the isolation regions may include silicon oxide, silicon nitride, silicon oxynitride, an air gap, other suitable materials, or combinations thereof. The isolation regions may be formed by any suitable process. The various IC devices may further include other features, such as silicide disposed on S/D and gate stacks overlying channels.

The IC structure200may also include a plurality of dielectric layers and conductive features integrated to form an interconnect structure configured to couple the various p-type and n-type doped regions and the other functional features (such as gate electrodes), resulting a functional integrated circuit. In some embodiments, the substrate202may include a portion of the interconnect structure and is collectively referred to as the substrate202.

As noted above, the IC structure200includes an interconnect structure. The interconnect structure includes a multi-layer interconnect (MLI) structure and an inter-level dielectric (ILD) integrated with the MLI structure, providing an electrical routing to couple various devices in the substrate202to the input/output power and signals. The interconnect structure includes various metal lines, contacts and via features (or via plugs). The metal lines provide horizontal electrical routing. The contacts provide vertical connection between the substrate202and metal lines while via features provide vertical connection between metal lines in different metal layers.

As shown inFIG. 2, the IC structure200includes a conductive feature208. In some embodiments, the conductive feature208may include a metal contact, a metal via, or a metal line. In some embodiments as shown inFIG. 2, the conductive feature208may be further surrounded by a barrier layer206to prevent diffusion and/or provide material adhesion. In some examples, the conductive feature208may include aluminum (Al), copper (Cu) or tungsten (W). The barrier layer206may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN) or tantalum silicon nitride (TaSiN). The conductive feature208and the barrier layer206may be formed by a procedure including lithography, etching and deposition. In another embodiment, the conductive feature208includes an electrode of a capacitor, a resistor or a portion of a resistor. Alternatively, the conductive feature208includes a doped region (such as a source or a drain), or a gate electrode. In another example, the conductive feature208includes a silicide feature disposed on respective source, drain or gate electrode. The silicide feature may be formed by a self-aligned silicide (salicide) technique.

Still referring toFIGS. 1 and 2, the method100proceeds to step104by forming a cap layer210on the conductive feature208. In some embodiments, the conductive feature208includes Cu, and the cap layer includes a cobalt (Co) cap layer. In some alternative embodiments, the cap layer includes at least one layer of manganese (Mn), nickel (Ni), ruthenium (Ru), titanium (Ti) and/or combinations thereof. The cap layer210may be deposited using any suitable method, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, the cap layer210may have a thickness in a range from about 5 Å to about 100 Å. In the present embodiment, the cap layer210is selectively grown on the conductive feature208, but not the substrate202, for capping the conductive feature208, such as Cu line. Therefore, the cap layer210is self-aligned with the conductive feature208, as shown inFIG. 2. The cap layer210may be formed using a metal precursor, such as Co included precursor. In some embodiments, the Co included precursor includes at least one of bis(cyclopentadienyl)cobalt(II) (Co(C5H5)2), bis(ethylcyclopentadienyl)cobalt(II) (C14H18Co), bis(pentamethylcyclopentadienyl)cobalt(II) (C20H30Co), dicarbonylcyclopentadienyl cobalt(I) (C5H5Co(CO)2), or cobalt carbonyl (Co2(CO)8). The cap layer210may effectively reduce the contact resistance and avoid the electromigration between different layers of interconnect structures. The cap layer210may also provide a good intrinsic adhesion between the conductive feature208and the subsequent layers formed on the conductive feature, such as etch stop layer (ESL), so that the material integration of the IC structure200can be improved.

Referring toFIGS. 1 and 3, method100proceeds to step106by forming an aluminum (Al)-containing dielectric layer212on the cap layer210. The Al-containing dielectric layer212may be formed to cover both the cap layer210and the part of the substrate202that is not covered by the cap layer210as shown inFIG. 4. In some embodiments, the Al-containing dielectric layer212includes aluminum (Al), oxygen (O), nitrogen (N) and/or combinations thereof. In some embodiments, the Al-containing dielectric layer212includes Al with a composition in a range from about 5 wt % to about 20 wt %. In some embodiments, the Al-containing dielectric layer212includes 0 with a composition in a range from about 60 wt % to about 80 wt %. In some embodiments, the Al-containing dielectric layer212includes N with a composition in a range from about 10 wt % to about 30 wt %. In a preferable embodiment, the Al-containing dielectric layer212includes about 10 wt % of Al, about 70 wt % of 0, and about 20 wt % of N. The thickness of the Al-containing dielectric layer212may be controlled to have high enough etching selectivity over the low-k dielectric layer during a plasma etching process, and high enough etching selectivity over the ESL during a wet etching process. Meanwhile, the thickness of the Al-containing dielectric layer212may also be controlled to have low enough contact resistance. In some embodiments, the Al-containing dielectric layer212may have a thickness in a range from about 5 Å to about 30 Å.

In some embodiments, the Al-containing dielectric layer212may be formed using a CVD or an ALD process. The precursor used to form the Al-containing dielectric layer includes an Al included organic chemical, such as trimethylaluminium (TMA). In some embodiments, the formation of the Al-containing dielectric layer212starts with a pretreatment process using NH3plasma, where the deposition chamber becomes a reduced environment including N free radical. Then the Al included precursor is imported and the Al from the precursor can be bonded with the N. The Al from the precursor may also adsorb oxygen (O) that is attached to the surface of the cap layer210, such as the surface oxidation layer of Co cap layer. In some embodiments, the NH3plasma treatment and the import of the Al included precursor are carried out for more than one cycle for depositing the Al-containing dielectric layer212including Al, O, and N.

In some embodiments during the deposition of the Al-containing dielectric layer, the chamber pressure is in a range from about 0.1 torr to about 100 torr. The radio frequency (RF) power is in a range from about 10 W to about 1000 W. The flow rate of NH3is in a range from about 50 sccm to about 5000 sccm. The deposition temperature is in a range from about 150° C. to about 400° C. In some preferable embodiments, the Al-containing dielectric layer212of the present invention is deposited at chamber pressure in a range from about 1 torr to about 10 torr. In some embodiments, the RF power for the deposition is in a range from about 200 W to about 1000 W. In some embodiments, the NH3gas flow rate is in a range from about 100 sccm to about 1000 sccm. In some embodiments, the deposition temperature is in a range from about 200° C. to about 400° C. In a preferable embodiment of the present disclosure, the Al-containing dielectric layer is deposited at a chamber pressure of about 3 torr, a RF power at about 600 W, a NH3 gas flow rate of about 500 sccm, and a deposition temperature of about 350° C. In some embodiments, the Al-containing dielectric layer212formed using a CVD or an ALD process has a porous structure with low density. In some embodiments, the reflectivity index (RI) of the Al-containing dielectric layer is in the range from about 1.76 to about 1.80.

In some embodiments, Al-containing dielectric layer212has a high etching selectivity over the low-k dielectric layer during a plasma etching process to form contact trenches. The Al-containing dielectric layer212may also have high etching selectivity over the ESL during a wet etching process to etch the ESL in the contact regions. The porous structure of the Al-containing dielectric layer212may enable the electron tunneling and/or the diffusion of the conductive feature (e.g., Cu) between two adjacent interconnect levels, so that the Al-containing dielectric layer can reduce the contact resistance of the IC structure. In addition, the Al-containing dielectric layer212may effectively prevent the cap layer210and/or the conductive feature208from being oxidized by the oxygen included plasma in the following process.

Referring toFIGS. 1 and 4, method100proceeds to step108by forming an etch stop layer (ESL)214on the Al-containing dielectric layer212. In some embodiments, the ESL214includes a dielectric material chosen to have etching selectivity for proper etch process at subsequent processes to form contact trenches. In some embodiments, the ESL214may be deposited using any suitable technique, such as CVD, physical vapor deposition (PVD), ALD, or an epitaxial growing process. In some embodiments, the ESL214includes a silicon nitride (Si3N4) layer, a nitrogen (N) doped silicon carbide (SiC) layer, and/or combinations thereof. The ESL214may have a thickness in a range from about 50 Å to about 200 Å. In some embodiments, the ESL214is formed using materials including silane (SiH4) and ammonia (NH3) plasma. In some embodiments, the ESL214may have a dielectric constant (k) that is greater than about 5.5. The ESL214may have a higher density than the Al-containing dielectric layer212. The ESL214may also have a lower etching selectivity than the Al-containing dielectric layer212during the etching process of the low-k dielectric layer to form contact trenches as discussed later in the following process. In some embodiments, the ESL214may be formed to cover the Al-containing dielectric layer212as shown inFIG. 3.

In some embodiments, with the formation of the Al-containing dielectric layer212in the present disclosure, the ESL215(ofFIG. 8) may include a dielectric material that has a dielectric constant (k) less than about 5. In some embodiments, the ESL215includes nitrogen (N) doped silicon carbide (SiC), oxygen (O) doped SiC, and/or combinations thereof. In some embodiments, the ESL215may be formed using silane (SiH4), and a plasma gas including CO2, N2O or combinations thereof. In some embodiments, the thickness of the ESL215is in a range from about 10 Å to about 100 Å, as discussed later with reference toFIG. 8in this disclosure. In some alternative embodiments, with the Al-containing dielectric layer212formed in the IC structure200, the ESL may not be needed, as discussed later with reference toFIG. 9in this disclosure.

Still referring toFIGS. 1 and 4, method100may proceed to an optional step110to form a dielectric layer216on the ESL214. In some embodiments, the dielectric layer216may include a silicon oxide (SiO2) layer configured to block gas generated from the ESL214from getting in contact with the photoresist material that is used to pattern the subsequent layers. Because the ESL214may include nitrogen (N), the ESL214may generate NH3gas during outgassing, and the NH3gas may diffuse to the photoresist layer to react with the photoresist layer, causing the photoresist layer to fail to be sensitive to the photons during the lithography process. Therefore, a SiO2layer216may be used to block the NH3outgassing from the ESL214to be in contact with the photoresist layer. In some alternative embodiments, the dielectric layer216may not be needed, as discussed later in this disclosure with reference toFIGS. 8-9.

Still referring toFIGS. 1 and 4, method100may proceed to step112by forming a low-k dielectric layer218over the Al-containing dielectric layer212. In some embodiments, the low-k dielectric layer218may include one or more materials selected from the group consisting of fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, other suitable materials, and combinations thereof. In some embodiments, the low-k dielectric layer218includes an extreme low-k dielectric material (XLK). In some embodiments, the low-k dielectric layer218includes a porous version of an existing Dow Corning dielectric material called FOX (flowable oxide) which is based on hydrogen silsesquioxane. A process of forming the low-k dielectric layer218may utilize spin-on coating or CVD. In some embodiments, a chemical mechanical polishing (CMP) process may be used to further planarize the top surface of the low-k dielectric layer218.

Referring toFIGS. 1 and 5, method100proceeds to step114by etching the low-k dielectric layer218to form a contact trench220. In some embodiments, the contact trench220may be formed by a lithography process and an etching process including one or more etching steps. The lithography process is used to pattern the low-k dielectric layer218, and the etching process is applied to etch the low-k dielectric layer218to expose the contact regions. In some embodiments, the etching process includes an etch step using a plasma etch with a suitable etchant, such as a fluorine-containing etchant, to selectively etch the low-k dielectric layer218without damaging to the conductive feature208. In some alternative embodiments, the etching process includes a first etch step to remove the low-k dielectric layer218in the contact regions using a dry etch process with difluoromethane (CH2F2) plasma. The first etch step may stop at the ESL214so that the ESL214can protect the substrate202, the conductive feature208and the cap layer210, from being damaged during the first etch step. Then a second etch step is used to selectively remove the ESL214in the contact regions using a wet etch with a suitable etchant, such as a hot phosphorous (H3PO4) acid. The second etching step may stop at the Al-containing dielectric layer212, so that the Al-containing dielectric layer212can protect the substrate202or the lower level interconnect features, including the conductive feature208or the cap layer210, from being damaged during the second etch step. In some embodiments, the Al-containing dielectric layer212includes a dielectric material having high selectivity over the ESL214in the second etch step. Therefore, the formation of the Al-containing dielectric layer212may effectively reduce or eliminate the damage to the lower level interconnect feature, such as the contact feature208.

Referring toFIGS. 1 and 6, method100proceeds to step116by forming a barrier layer222along the wall of the contact trench220. The barrier layer222may also be formed on the top surface of the Al-containing dielectric layer212exposed in the contact trench220. In some embodiments, the barrier layer222includes metal and is electrically conductive but does not permit inter-diffusion and reactions between the low-k dielectric layer218and the metal layer to be filled in the contact trench220. The barrier layer222may include refractory metals and their nitrides. In various examples, the barrier layer222includes one or more materials selected from the group consisting of TiN, TaN, Co, WN, TiSiN, TaSiN, and combinations thereof. In some embodiments, the barrier layer222may include multiple films. For example, Ti and TiN films may be used as the barrier layer222. In some embodiments, the barrier layer222may be deposited by PVD, CVD, metal-organic chemical vapor deposition (MOCVD), ALD, other suitable techniques, or combinations thereof.

Still referring toFIGS. 1 and 6, method100proceeds to step118by depositing a metal layer224on the barrier layer222to fill the contact trench220. In some embodiments, the metal layer224may include copper (Cu), aluminum (Al), tungsten (W) or other suitable conductive material. In some embodiments, the metal layer224may also include Cu or Cu alloy, such as copper magnesium (CuMn), copper aluminum (CuAl) or copper silicon (CuSi). In some embodiments, the metal layer224may be deposited by PVD. In some examples, the metal layer224may include Cu, and the Cu layer224may be formed by depositing a Cu seed layer using PVD, and then forming a bulk Cu layer by plating. In some embodiments, the metal layer224may include a metal contact, a metal via, or a metal line. After the deposition of the metal layer224, a chemical mechanical polishing (CMP) process may be performed to remove excessive metal layer224. A substantially coplanar top surface of the metal layer224and the low-k dielectric layer218.

Referring toFIGS. 1 and 6, method100proceeds to step120by forming an upper cap layer226on the metal layer224. The method and the upper cap layer226formed at step120may be substantially similar to that of step104. Referring toFIGS. 1 and 7, method100proceeds to step122by forming an upper Al-containing dielectric layer228on the upper cap layer226. The method and the Al-containing dielectric layer228formed at step122may be substantially similar to that of step106.

FIGS. 8-9illustrate some alternative embodiments of the IC structure200having an Al-containing dielectric layer ofFIG. 5according to various aspects of the present disclosure. In some embodiments as shown inFIG. 8, the ESL215may include materials with dielectric constant that is lower than about 5, such as N doped SiC and/or O doped SiC. The thickness of the ESL215may be in a range from about 10 Å to about 100 Å, and the dielectric layer216may not be necessary in the IC structure200. The formation of the ESL215may include using CO2or N2O plasma. The CO2or N2O plasma may oxidize the cap layer210and/or the conductive feature208. In some embodiments, the formation of the contact trenches in the IC structure200ofFIG. 8may include an etching process including more than one step. For example, the etching process includes a first etch step to etch the low-k dielectric layer218in the contact regions. The first etch step may include a dry etch using difluoromethane (CH2F2) plasma, and the first etch step stops at the ESL215. Then a second etch step is used to selectively remove the ESL215in the contact regions using a wet etch with a suitable etchant, such as a hot phosphorous (H3PO4) acid. The second etching step selectively removes the ESL215in the contact regions and stops at the Al-containing dielectric layer212. Therefore, the Al-containing dielectric layer212may protect the substrate202or the lower level interconnect features, including the conductive feature208or the cap layer210, from being damaged during the contact trench etching process. As discussed earlier in the present disclosure, the Al-containing dielectric layer212may effectively prevent the cap layer210and/or the conductive feature208from being oxidized by the CO2or N2O plasma.

In some alternative embodiments as shown inFIG. 9, neither the ESL215nor the dielectric layer216is necessary in the IC structure200when the IC structure includes an Al-containing dielectric layer212. In some embodiments, the formation of the contact trenches in the IC structure200ofFIG. 9may include a one-step etching process using a plasma etch with a suitable etchant, such as a fluorine-containing etchant, to selectively etch the low-k dielectric layer218in the contact regions without damaging the Al-containing dielectric layer212or the conductive feature208. This is due to the high etching selectivity of the Al-containing dielectric layer212over the low-k dielectric layer218, so that the contact trench etching process may stop at the Al-containing dielectric layer212. In addition, the Al-containing dielectric layer212may effectively prevent the cap layer210and/or the conductive feature208from being oxidized. In some alternative embodiments, the IC structure including the Al-containing dielectric layer may also eliminate the cap layer210, leaving the Al-containing dielectric layer212as the interfacial layer between the upper level and the lower level of the interconnect structure.

FIG. 10compares the reflectivity of the surface of the Cu layer in the IC structure with different capping schemes when exposed to N2O plasma according to some embodiments of the present disclosure. As shown inFIG. 10, the pure Cu without any capping layer or the Cu with only Co capping layer demonstrate obvious oxidation effect, as evidenced by the reduced reflectivity of the surface of the Cu layer. The reduced reflectivity can be caused by the formation of the copper oxide layer on the surface of the Cu layer. When the Cu layer is covered with the Al-containing dielectric layer212as discussed in the present disclosure (e.g.,FIG. 7,FIG. 8, orFIG. 9), the Cu layer maintains its high reflectivity as shown inFIG. 10.FIG. 10shows an effective anti-oxidation capability of the Al-containing dielectric layer, which could prevent the surface of the Cu layer from being oxidized by the oxygen included plasma (e.g., CO2or N2O plasma).

An IC structure without the Al-containing dielectric layer may result in an over etching problem. The over etching can result in an increased contact resistance from the upper level to the lower level in the interconnect structure, and can affect the reliability performance of the IC structure and the final device. Although not intended to be limiting, the present disclosure provides one or more benefits. The Al-containing dielectric layer included in the IC structure as discussed in the present disclosure can effectively prevent the over etching during the contact trench etching process due to the high etching selectivity of the Al-containing dielectric. The Al-containing dielectric layer can also effectively reduce the capacitance and provide an improved reliability performance as the dimension of the IC structure scales down.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a substrate including a conductive feature; forming an aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

In some embodiments, the method further includes forming a cap layer between the conductive feature and the Al-containing dielectric layer. A width of the cap layer is substantially similar to a width of the conductive feature. The forming the cap layer may include selectively depositing at least one layer of Co, Mn, Ni, Ru, or Ti to be aligned with the conductive feature.

In some embodiments, the method further includes forming an etch stop layer (ESL) between the Al-containing dielectric layer and the low-k dielectric layer; and etching the ESL to form the contact trench. The forming the ESL may include depositing a layer including at least one of N doped SiC layer or O doped SiC layer using a plasma gas, the plasma gas including at least one of CO2or N2O. The forming the ESL may include depositing a layer including at least one of N doped SiC layer or Si3N4layer using silane (SiH4) and NH3plasma. The etching the low-k dielectric layer may include a dry etch process using a fluorine-containing etchant. The etching the ESL may include a wet etch process which stops at the Al-containing dielectric layer. In some embodiments, the method further includes forming a dielectric layer between the ESL and the low-k dielectric layer; and etching the dielectric layer to form the contact trench.

In some embodiments, the forming the Al-containing dielectric layer includes performing a NH3plasma treatment; importing an Al-containing organic precursor; and depositing the Al-containing dielectric layer including Al, N and O. The Al-containing dielectric layer is formed using a process selected from the group consisting of chemical vapor deposition (CVD), atomic layer deposition (ALD), and a combination thereof. The forming the Al-containing dielectric layer may include depositing the Al-containing dielectric layer using a chamber pressure in a range from about 0.1 torr to about 100 torr. The forming the Al-containing dielectric layer may include depositing the Al-containing dielectric layer using a RF power in a range from about 10 W to about 1000 W. The forming the Al-containing dielectric layer may include depositing the Al-containing dielectric layer at a temperature in a range from about 150° C. to about 400° C. The forming the Al-containing dielectric layer may include depositing the Al-containing dielectric layer using a flow rate of the NH3plasma in a range from about 50 sccm to about 5000 sccm.

The present disclosure also provides a method for forming an integrated circuit (IC) structure. The method includes providing a substrate including a conductive feature; forming a cap layer on the conductive feature; forming an aluminum (Al)-containing dielectric layer on the cap layer; forming an etch stop layer (ESL) on the Al-containing dielectric layer; forming a low-k dielectric layer on the ESL; and etching the low-k dielectric layer and the ESL to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

In some embodiments, the etching the low-k dielectric layer and the ESL includes dry etching the low-k dielectric layer using a fluorine-containing etchant, and wet etching the ESL using a hot phosphorous acid (H3PO4). The wet etching the ESL stops at the Al-containing dielectric layer.

The present disclosure also provides yet another embodiment of an integrated circuit (IC) structure. The IC structure comprises a substrate including a first conductive feature; a cap layer formed on the conductive feature and aligned with the first conductive feature; an aluminum (Al)-containing dielectric layer disposed on the cap layer; an etch stop layer (ESL) disposed on the Al-containing dielectric layer; a low-k dielectric layer disposed on the ESL; and a second conductive feature filling a contact trench formed through the low-k dielectric layer and the ESL. The second conductive feature is aligned with the first conductive feature. The Al-containing dielectric layer is inserted between the cap layer on the first conducive feature and the second conductive feature. A width of the cap layer is substantially similar to a width of the first conductive feature. The Al-containing dielectric layer is formed to cover the cap layer and the substrate.

In some embodiments, a thickness of the ESL is in a range from about 10 Å to about 200 Å. The Al-containing dielectric layer may include Al, N and O. A thickness of the Al-containing dielectric layer is in a range from about 5 Å to about 30 Å.