BALANCING POWER, ENDURANCE AND LATENCY IN A FERROELECTRIC MEMORY

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

SUMMARY

Various embodiments of the present disclosure are generally directed to a memory storage system that incorporates ferroelectric memory elements (FMEs) and a control system that manages the storage of data to the FMEs that balances power, endurance and latency characteristics of the FMEs.

Without limitation, some embodiments operate to program a data set received from an external client device to a group of FMEs at a target location using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set.

The profile may be selected from among a plurality of profiles for different operational conditions. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

These and other features and advantages of various embodiments can be understood from a review of the following detailed description in conjunction with the accompanying drawings.

DETAILED DISCUSSION

Various embodiments of the present disclosure are generally directed to systems and methods for providing a ferroelectric memory with control characteristics that balance various operational parameters associated with the memory, such as power, endurance and latency.

FMEs are semiconductor based memory cells that provide non-volatile data storage with fast response and low power consumption characteristics. A typical FME includes a stack of layers that includes at least one ferroelectric layer which stores data in relation to a programmed and retained electrical field orientation of the layer. The ferroelectric orientation provides different current response characteristics, such as differences in voltage drop across the layer or electrical resistance of the layer. These differences allow the layer to store one or more data storage bits in a non-volatile fashion.

FMEs can be configured in a number of ways to include additional layers including but not limited to an electrode layer, an interposed layer (such as a tunneling layer or a dielectric layer), a metallic layer, a channel region, etc. As noted above, one or more data bits can be stored by each FME based on the programmed electric polarity, or polarities, of the ferroelectric layer(s) of the FME.

A variety of FME constructions have been proposed. These include ferroelectric tunneling junctions (FTJs), ferroelectric field effect transistors (FeFETs), and ferroelectric random access memory (FeRAM). Other forms of FMEs have been proposed as well.

Generally, FTJs are somewhat analogous to magnetic tunneling junctions (MTJs) and are usually arranged as two-junction cells with a ferroelectric layer and a tunneling barrier layer sandwiched between opposing electrodes. FTJs are particularly suitable for cross-point arrays and other architectures with two connection points to each memory element.

FeFETs are somewhat analogous to flash memory cells and generally include a gate structure arranged between respective source and drain doped regions. The gate structure includes a ferroelectric layer which is programmed to have a selected electrical polarity that changes the source-drain connectivity of the cell. FeFETs usually have three-junctions (drain, source, gate) and can be readily arranged into two-dimensional (2D) or three-dimensional (3D) structures.

FeRAM cells are somewhat analogous to DRAM cells and are usually arranged with at least one transistor and at least one capacitor. The capacitor includes a ferroelectric layer. A tunneling barrier layer may also be provided in the capacitor. A number of FeRAM arrangements have been proposed, including 1T1FC (one-transistor, one-ferroelectric capacitor) cells, 2T2C cells, 1T4C cells, 6T4C cells, etc. The transistor in each FeRAM cell may be a traditional transistor (e.g., a conventional field effect transistor, FET), although in some cases ferroelectric layer(s) can be applied to the gate structure of the transistor as well as to the capacitor (“dual layer FeRAM”). The impressed electrical polarity of the ferroelectric layer(s) in the capacitor(s) and, as required, the transistor(s), establishes the programmed state of the cell.

A variety of materials, metals and alloys can be used to make up the respective ferroelectric, tunneling and electrode layers. Suitable materials for the ferroelectric layer can include, without limitation, HfO2, ZrO2, Hf1-xZxO2, etc. These materials may be doped with other elements such as but not limited to Si, Ge, Al, Ti, Sc, Y, La, Ce, Gd, Nb, Sr, Ba, N, etc. The tunneling layer(s) may be a suitable non-ferroelectric dielectric including, but not limited to Al2O3, MgO, SrTiO3, etc. Electrodes are electrically conductive material and may include, without limitation, TiN, TaN, Pt, Ag, CrRu, CrMo, CrW, CrTi, and RuAl. In some cases, anti-ferroelectric materials such as ZrO2 may be used in the place of the ferroelectric layer if an internal bias field, e.g., from two dissimilar electrodes, is introduced in order to shift its hysteresis loop to enable the storage of binary information. These and other examples are merely illustrative and are not limiting.

Various embodiments of the present disclosure are directed to a method and apparatus for storing data using ferroelectric memory element (FME) cells using a controller circuit that balances various operational parameters such as power, endurance, and latency to optimize data storage characteristics in the FME cells.

FMEs store data in relation to the strength and endurance of the impressed electric field in the ferroelectric layer. The following terms relate to the manner in which FMEs can be programmed, how quickly the FMEs can be read, and how long the FMEs will tend to retain the stored information.

Power relates to what amount of power (and in at least some cases, dwell time) is required to program an FME cell. Generally, the larger amount of power (e.g., applied current magnitude, applied voltage magnitude, etc.), the “stronger” the resulting impressed electric field will be stored by the ferroelectric layer. Longer dwell times will, up to a point, also aid in developing higher magnitude electric fields. The field strength can be quantified as E, which in turn can be expressed as F/q (force per charge), where F is force and q is magnitude of charge. Standard metric units are Newtons/Coulomb. Since power is a limited resource in a storage device (or in other applications), gaining the greatest field strength from the least amount of expended power is desirable.

Endurance relates to how long a programmed FME cell can maintain a programmed state. There are three (3) main types of endurance that can be associated with FME cells: programming endurance (persistence), imprinting, and fatigue endurance (wear). These are distinct but somewhat related as well.

Programming endurance, also sometimes referred to as retention, generally describes the rate at which a given FME, once programmed, can maintain a sufficient field strength in the associated ferroelectric layers to enable the readback circuitry to correctly and reliably recover the stored data. This can be measured a number of ways, one common way is elapsed time. So for example, two weeks, two months, two years, etc. are valid ways to consider programming endurance, or the persistence of the data. Refresh operations can be carried out at appropriate times to reset this period. A refresh would essentially involve reading the data and then immediately rewriting the present data state. This would consume power so this is related to the power aspect described above.

Imprinting is related to programming endurance, but generally relates to the imprinting, or setting, of a given polarity in a ferroelectric layer over time. Generally, it has been observed that if a ferroelectric layer maintains a selected polarity over an extended period of time, field drift and reprogramming difficulties can result. Field drift relates to asymmetric distribution of charges over polarity. This is analogous to charge drift in a flash memory cell, and operates the same way; as the data ages, the programmed field strength can decrease. It is presumed that adjacent reads can also induce reductions in programmed field strength (analogous to read disturb in flash memory applications). Imprinting also can enhance reprogramming difficulties in that, the longer or more frequently a ferroelectric layer is subjected to a particular programmed polarity, the harder it may be to overcome and reset that cell.

Fatigue endurance, or wear, relates to the overall operational life of the memory. Imprinting is similar although these may be caused by separate mechanisms. Regardless, over time a ferroelectric layer loses its efficiency in being able to retain an electric field, both based on aging and usage effects. Wear can be expressed in terms of total programming cycles, or the number of times a given FME cell has been programmed. This is analogous to P/E counts in a flash memory. As noted previously, FMEs tend to have wear rates (operational lives) on the order of 1010cycles, whereas flash may have operational lives on the order of 104cycles (or even less as higher numbers of bits are stored per cell).

Latency is a characteristic usually related to the amount of overall time required to perform data accesses on an FME cell. As noted previously, FMEs are significantly faster than other forms of non-volatile memory, such as flash. Typical read and programming (write) latencies for the reading and programming, respectively, of FME cells is on the order of several nanoseconds, ns. As such, FMEs operate substantially at the same rate as conventional DRAMs (or in some cases, faster than conventional DRAMs).

The construction of an FME can affect its performance; for example, it has been found that, generally, a thicker ferroelectric layer will tend to require higher power levels to establish a selected electrical polarity and may have longer read latency characteristics, but the thicker layer will provide better endurance characteristics. Similarly, environmental factors, such as temperature and wear (e.g., program counts, etc.), can affect power, endurance and latency of a given FME based memory construction.

Accordingly, the various embodiments of the present disclosure provide a controller circuit which has the capability of balancing power, endurance, and latency to optimize data storage characteristics in FME cells of an FME based memory controlled by the controller circuit.

In some embodiments, a method includes steps of receiving a data set for storage to a non-volatile memory (NVM) comprising ferroelectric memory cells. A parameter is identified that is associated with the data set or with a target location to which the data set is to be stored in the NVM. An operational mode is selected for the data set based on the selected parameter. The data set is thereafter programmed to the NVM at the target location using a programming profile selected in relation to the selected operational mode. The system can be both reactive and proactive and based on various inputs and profiles.

Various alternative embodiments evaluate the various operational modes, the aspects of the target location, the various parameters including data aging, programming counts, hotness/coldness of the data based on historical or other factors, different types of FMEs, modes based on enhancing power, endurance or latency, further adjustments based on environmental conditions (e.g., temperature), and so on.

Ultimately, the programming profile selected by the controller circuit balances various factors including power (the amount of power required to perform a particular data transfer operation), endurance (the ability of the FME memory to retain a given programmed state), and latency (the time required to transfer data from and to the FME memory).

These and other features and advantages of various embodiments can be understood beginning with a review ofFIG.1, which shows a functional representation of a data processing system100. The system100includes a client (host) device101that communicates with a data storage device102via an interface103. The client device101may take the form of a personal computer, a smart phone, a workstation, a tablet, a laptop, a gaming system, a microcontroller, a server, an edge device, an Internet of Things (IoT) device, a mass storage array, etc.

The data storage device102is configured to store and retrieve data utilized by the user of the client device101and may be a local processor memory, a data cache, a server cache, a RAID storage system, a cloud storage system, a solid-state drive (SSD), a hard disc drive (HDD), a hybrid storage device, an array of storage devices, a portable thumb (e.g., USB) drive, etc. The interface103can take substantially any form including but not limited to a local wired or wireless interface, a local area network (LAN), a wide area network (WAN), a cloud computing interface, the Internet, etc. Substantially any useful interface protocol can be implemented for the interface103including Ethernet, USB, SCSI, SAS, Fibre Channel, PCMI, wireless connections, etc.

Of interest is the data storage device102, which is shown to include a controller104and a memory106. The controller104can include one or more programmable processors that execute program instructions stored in a local memory to carry out various functions, including the control of data transfers between the memory106and the client101across the interface103. Additionally or alternatively, the controller104can utilize a hardware circuitry such as formed of ASCI (application specific integrated circuits), FPGA (field programmable gate arrays), state machines, or other arrangements of gate logic.

The memory106can include any number of useful forms including local memory for the controller, cache memory, buffer, main storage, etc. The memory106includes non-volatile memory (NVM), which will be understood, consistent with the customary usage of this term, as persistent memory that continues to retain information stored therein even after the removal of applied power to the memory. The form of the main data store can take any number of forms, including semiconductor based memory, rotatable data storage memory, tape based memory, etc.

FIG.2depicts aspects of a data storage device110that corresponds to the data storage device102ofFIG.1in some embodiments. InFIG.2, the data storage device110is characterized as a solid-state drive (SSD) that utilizes flash memory as a main memory store. This is not limiting, as any number of other forms of data storage devices can be utilized, including but not limited to hard disc drives (HDDs), hybrid drives, tape drives, optical drives, magneto-optical (MO) drives, etc.

The SSD110includes a device controller112that corresponds to the controller104inFIG.1. A write cache114is an internal buffer memory that temporarily stores sets of write data provided from the external host prior to transfer to the main store. These sets of write data may accompany a write command from the requesting client to store the data for future use.

A flash memory electronics circuit116operates as a front end to receive and process the sets of write data for transfer to a flash array118. A read buffer120temporarily stores corresponding sets of read back data retrieved from the flash array118, via the electronics circuit116, in response to a read command. The read back data are subsequently transferred from the read buffer120to the requesting client that issued the read command. Internal controller memory (MEM)122may store program instructions, data queues, command queues, map data, and other forms of control data to facilitate these operations.

It is contemplated that at least aspects of the SSD110will incorporate ferroelectric memory. This can include aspects of the write cache114, circuit116, flash118(including as buffers or as the actual main memory in lieu of flash memory cells), read buffer120and/or the device control memory122.

FIG.3shows a control circuit130of the SSD ofFIG.2in some embodiments. The control circuit includes a controller132with various functional control circuits incorporated therein, including a power management circuit134, an endurance management circuit136and a latency management circuit138. These various functional circuits can be realized using hardware or programmable processing circuitry as described above. Suitable constructions and operations of these circuits will be described below.

A read/write circuit140is configured to respective write (program) data bits to individual FME cells, such as depicted at142, as well as to subsequently read the programmed bits therefrom. In some cases, a refresh operation may be required to rewrite the data after a read operation, depending on the configuration of the FME cell. A monitor circuit144is configured to monitor these read and write operations as well as to accumulate and analyze various data states associated with the FME cell142, as further explained below.

The controller132is further shown to incorporate an error correction circuit146. This can take a number of different constructions, such as but not limited to one or more LDPC (low density parity check) decoders used to correct bit errors in blocks of retrieved data.

The various power, endurance and latency management circuitry134,136,138can operate adaptively responsive to information obtained from the error correction circuitry146(e.g., bit error rates, syndrome counts, etc.). In this way, adjustments may be carried out based on real time and accumulated history data to maintain certain specified levels of performance for the system130. In one embodiment, a particular data set can be written to a group of FMEs at a target location in the memory using a first profile, after which the data are read and, responsive to at least one read error, a different second profile can be used to rewrite the data set back to the memory. This can further enable the generation of various profiles for different combinations of power, endurance and latency for ongoing and future data sets.

The FME cell142depicted inFIG.3can take any number of different configurations as desired.FIG.4shows a construction of the FME cell142as an FTJ160. The FTJ160is a two-terminal device with outer conductive electrode layers162164, an inner (programming) layer of ferroelectric material164, and an optional tunnel barrier layer166. The tunnel barrier layer168is contemplated but not necessarily required as a separate layer, and may be any suitable material such as but not limited to a non-ferroelectric material, a dielectric material, etc.

With the appropriate choice of electrode materials, tunnel barrier, and ferroelectric layer, the resistance of the FTJ can be made to depend on the orientation of the ferroelectric polarization of the ferroelectric layer166. Stated another way, an FTJ such as the FTJ160operates in a manner similar to magnetic tunnel junctions (MTJs), and will present different electrical resistances between electrodes162,164based on the programmed polarization of the ferroelectric layer166. The differences in electrical resistance will vary depending on construction, but differential resistance values can be greater than 104ohms.

FIG.5shows another example construction for each of the FME cells142inFIG.3as FeRAM cells170. Each FeRAM cell170is characterized as a 1T1C arrangement, although other configurations can be used. The FeRAM cell170includes at least one transistor172and at least one capacitor174. Each transistor172is formed using a base semiconductor substrate176with respective doped regions178,180to form respective source and drain regions. A channel (CH) is formed between these respective regions, as shown. A gate structure182is disposed between the source and drain regions178,180adjacent the channel region. The gate structure182includes a conductive gate184and an isolating region186.

A capacitor structure188extends from the drain region180via conductive path190. The capacitor structure includes upper and lower electrode layers192,194. A ferroelectric layer196is disposed between the electrode layers190,192. As desired, a tunneling layer (not separately shown) can also be provided between the electrode layers. In this way, the control gate voltage applied to electrode conductive gate184can be used to determine the electric polarity of ferroelectric layer196in relation to the amount of voltage required to place the transistor into a forward conductive state from source to drain178,180.

FIG.6shows an FME memory cell element configured as an FeFET200. The FeFET200includes a semiconductor substrate202in which doped regions204,206are formed to provide respective source and drain regions. A gate structure208is provided between the source and drain regions204,206to manage a channel (CH) therebetween. The gate structure208includes a ferroelectric layer210sandwiched between an isolating layer212and an electrically conductive gate layer214. It will be noted that a number of different gate structures are known for FeFETs, including a single layer of ferroelectric material, the addition of an insulative layer (as shown), the addition of a metal layer, a laminated arrangement with multiple spaced apart ferroelectric layers, and so on.

While the FTJs160and FeRAM170may be read destructive and therefore may require a refresh operation after a read operation, the FeFETs200are often not read destructive (e.g., truly non-volatile) and therefore may not need the application of a subsequent refresh operation to retain the storage state after a read operation. Many other ferroelectric memory configurations are known in the art and can be arranged as desired, including XTYC configurations where X and Y are some selected integers of transistors and capacitors; hybrid configurations where ferroelectric layers are arranged in various gate structures or other elements, and so on.

FIG.7shows a control circuit220that can be used to control various FME cells in accordance with various embodiments. This circuitry includes a program (write) driver222, a read driver224, a sense circuit226and a refresh circuit228. These various circuits operate to set, sense and, as necessary, retain the programmed electrical polarity of a ferroelectric layer230of a selected memory cell.

The program driver222is utilized to write (program) data to the respective memory cells of the stack on a cache line basis. This can include the presentation of appropriate voltages and/or currents on the control lines to place the associated ferroelectric layers in the desired programmed orientations.

The read driver224places appropriate voltages and/or currents on the respective control lines to enable the sense circuit226to sense the programmed orientations of the respective ferroelectric layers.

The refresh circuit228operates to refresh the current programmed states of the ferroelectric layers230at appropriate times. In some cases, the refresh circuit158operates at the conclusion of each read operation, since a read operation destroys the currently stored state. In this situation, once data are read from a selected location in the ferroelectric layers, the refresh circuit buffers and rewrites the previously stored data back to that selected location from which the data retrieved (as is commonly performed with DRAM). That is, as data bits are stored within the stack, data bits may need to be rewritten (or not) as the data are read.

FIG.8provides a functional block representation of aspects of a power management circuit240, similar to the circuit discussed above inFIG.3. Other arrangements can be used. The circuit240includes a write driver242, a read driver244and a sense circuit246which are arranged to operate upon an FME cell248. The write driver242provides driving current and/or voltage at selected power levels configured to establish an electrical polarity in each of the associated ferroelectric layers.

It will be appreciated that higher power levels tend to provide stronger impression of the electrical polarities of the respective ferroelectric layers, whereas lower power levels tend to provide weaker fields in the respective ferroelectric layers. It follows that higher power will cause higher strength fields, which can be used to distinguish among various bit levels when multiple bits are being stored, and also tends to enhance the duration at which the layers will retain the impressed program state.

As such, different profiles may be applied to meet the requirements of a given application. For example, should the FME be incorporated as part of the main memory and specified for long term (e.g., multi-month or multi-year) storage of the data, a first profile may be applied by the write driver to program the data in such a way as to obtain these specified data retention rates. On the other hand, should the FME be part of a temporary cache (such as the read buffer, write cache, local memory, etc. fromFIG.3), a second profile may be applied using a lower power and duration, since the data may not be retained for a relatively long period of time.

Generally, a storage medium can store n bits using2nstorage states; for example, a single bit can be stored using two (2) storage states (e.g., 0 or 1). Two bits can be stored using four (4) storage stages (e.g., 00, 01, 10 and 11). Three bits can be stored using eight (8) storage states (e.g., 000, 001, 010, 011, 100, 101, 110, 111), and so on. The power circuitry of the write driver242can thus be used to not only provide a desired storage state to distinguish among these various granularities, but can also be used to enhance longevity of the stored state. For example, if data are intended to be stored for only a short period of time, then a lower power rate may be applied during a write operation as compared to a memory intended to provide longer term storage.

FIG.9provides a functional representation of an endurance management circuit250that generally corresponds to the circuitry ofFIG.3discussed above. Other arrangements can be used soFIG.9is merely illustrative of one embodiment. The circuit250includes a read count circuit252, a write count circuit254and an analysis circuit256. The management circuit250can thus operate to track the duration of how long stored data have been pending (data aging) as well as how often various memory locations have been programmed (wear). In some cases, retained data may be refreshed or relocated based on read disturb, field drift or other effects.

FIG.10shows a latency management circuit260corresponding to the circuitry shown inFIG.3above. As before, the arrangement inFIG.10is merely illustrative and is not limiting. The circuit260includes a read timing circuit262, a write timing circuit264and an error count circuit266. These elements generally track latency times associated with the transfers of data to and from the various FME cells. In some cases, the circuitry may be able to discern individual transfers. In other cases, the circuitry may provide average calculated transfers based on the transfer of larger sets of data (e.g., based on average transfer rates of large multi-bit blocks of data, individual average transfer rates can be evaluated). The error count circuitry can track the extent to which read retries, adjustments in read sense voltages, etc. are carried out in order to recover the data.

From these descriptions it can be seen that a controller such as the controller132inFIG.3can adaptively operate to adjust different system parameters during both writes and reads to enhance and optimize power, endurance and latency performance of an FME based memory. In some cases, a suitable endurance level is first specified, and then power levels are selected to achieve that specified endurance level while obtaining the desired latency (and other factors, such as BER, etc.).

FIG.11shows a flow diagram270to illustrate steps that may be carried out in accordance with some embodiments. At block272, an FME array is initially configured with baseline power, endurance and latency parameters. Some of these parameters may be inherent from the construction type and features of the FME cells (e.g., FTJs v. FeFETs; number and thicknesses of the ferroelectric layers; and so on). Others of these parameters may be empirically derived based on observed performance. For example, programming operations (either using test data or actual user data) can be carried out in order to establish appropriate power levels (e.g., power values supplied to the write and read drivers; appropriate thresholds for the various sense circuits, etc.).

Thereafter, the system is operated and monitored as shown by block274. As before, these can include periodic calibration operations or operations involving user data from the client device. At block276, the monitored data accumulated from block274are used to make adjustments to one or more system parameters, such as applied power, thresholds, etc. in order to adaptively adjust the system. It is contemplated that these steps will continue in an adaptive fashion so that the system maintains specified levels of performance. In some cases, history data can be accumulated and used to make these and other parametric adjustments.

FIG.12is a functional block representation of an adaptive adjustment system300constructed and operated in accordance with further embodiments. The system300represents aspects of the controller132inFIG.3, and can be realized using hardware and/or programmable processor circuits.

The system300includes a profile generation and selection circuit302and an associated memory304. The circuit302operates as described above to generate and select various profiles for the programming, reading and management of data in an associated FME based memory.

Various inputs are shown to be utilized by the circuit302. Other inputs can be used so that the arrangement depicted inFIG.12is merely exemplary and is not limiting. FME LOCATION relates to the physical location of the associated FME(s) being managed within the associated memory. FME TYPE relates to the particular physical construction of the FME(s) (e.g., FTJ, FeRAM, FeFET, 2D, 3D, large, small, multi-cell, etc.).

The EXISTING R/W PARAMETERS input relates to the current read and write (programming) settings for the associated FME(s). As discussed above these can include write current/voltage magnitudes and durations, read sensing current/voltage values, programmed temperature, etc. BER is bit error rate and indicates a measure of current and/or historical error rate performance for the FME(s). Other error rate indications can be used as required.

WEAR PARAMETERS relates to program/erase (P/E) counts or other accumulated parameters associated with historical usage of the FME(s). OBSERVED DATA TYPE (HOT, COLD) relates to an assessment by the system of the relative importance of the data as utilized by the client. Hot data are retrieved on a relatively frequent basis, while cold data tend to be retrieved infrequently (if at all). This parameter can be tracked by the controller based on LBA or other block addressing indications from commands processed from the host. Data aging is a related parameter and can be a measure of how long the data have remained in a particular location since a most recent refresh operation, can be can be determined independently of client command history. Either or both of these can be utilized as part of the profile selection process.

TEMPERATURE is an indication of the current measured or estimated temperature of the memory array, and can be obtained including through the use of one or more temperature sensors. It will be appreciated that the current temperature may affect a particular read or write operation. Finally, CLIENT INPUTS are directives or hints supplied by the client device with regard to the data, such as an instruction to place the data for short term access or long term storage, etc.

The circuit302uses these and other inputs as required to evaluate and select an appropriate profile for a given operation. The memory304can be used by the circuit302to maintain various data structures including history data306and various different profiles308,310,312(denoted as Profiles 1-3). The various profiles can be derived at a selected granularity, including multiple profiles for the same FMEs for different operational and environmental conditions, separate profile sets for different locations, and so on. The profiles can cover a broad range of parameters including programming, reading, erasure voltage (particularly suitable for FeFETs), program during read refresh operations (particularly suitable for FeRAMs), and so on.

FIG.13shows an FME cache memory device320constructed and operated in accordance with further embodiments. The memory device320can be incorporated into the various embodiments discussed above, including the SSD110ofFIG.2. The memory device320takes a hybrid construction with different cache lines formed of different construction types of FMEs for different use cases. Without limitation, this can include FTJs for a first type at322, FeRAM for a second type at324, FeFETs for a third type at326, etc. Other types and varieties of construction can be incorporated into the memory320, such as multi-FME cells, cells with thicker or thinner ferroelectric layers for different operational conditions, and so on.

FIG.14shows another memory in the form of an FME memory array330in accordance with further embodiments and which can be incorporated into the various systems described above including the SSD110. In some embodiments, the array330is used as a stack register, although such is not limiting.

FIG.14illustrates how different locations within the array330may factor into the decision making process utilized by the circuit302inFIG.12. In one non-limiting example, FMEs within the array330that are located near an edge of the array, such as represented at332, may be provisioned with one set of profiles. FMEs within an interior portion of the array330, denoted by334, may be provisioned with a different set of profiles. Factors that can influence such different profiles can include heat dissipation rates, signal loss effects, and so on. Hence, the relative or absolute location of the given set of FMEs being evaluated by the circuit302can be taken into account using any desired level of granularity.

It will now be appreciated that various embodiments can provide a number of benefits over the existing art. Operations can be advantageous in which a parameter is identified that is associated with a data set to be written to an NVM, or associated with a target location in the NVM to which the data set is to be stored. A selected profile is identified and used to write the user data set to the NVM accordingly.

In some cases, the selected profile can be adjusted based on a number of factors, such as various operational modes, the aspects of the target location, the various parameters including data aging, programming counts, hotness/coldness of the data based on historical or other factors, different types of FMEs, modes based on enhancing power, endurance or latency, further adjustments based on environmental conditions (e.g., temperature), and so on.