Method for preventing crack extensions during lift-off process

A method for preventing crack extensions during a lift-off process is provided. The method includes forming an epitaxial layer on a wafer substrate; forming a guard trench in the epitaxial layer, wherein a depth of the guard trench in a thickness direction of the epitaxial layer is at least half of a thickness of the epitaxial layer, and a total length of the guard trench is greater than at least a quarter of a circumference of the epitaxial layer; and performing a lift-off process to separate the wafer substrate from the epitaxial layer.

BACKGROUND

Field of Invention

The present disclosure relates to a method performed before a lift-off process which can prevent crack extensions.

Description of Related Art

There is a trend that a size of one device becomes smaller, especially in the semiconductor industry. In recent years said trend also becomes popular in the light-emitting display field. One of the important issues when the size of one device gradually goes down is the yield during manufacturing processes. Many efforts and resources have been poured in to enhance the yield in various ways.

SUMMARY

According to some embodiments of the present disclosure, a method for preventing crack extensions during a lift-off process is provided. The method includes forming an epitaxial layer on a wafer substrate; forming a guard trench in the epitaxial layer, in which a depth of the guard trench in a thickness direction of the epitaxial layer is at least half of a thickness of the epitaxial layer, and a total length of the guard trench is greater than at least a quarter of a total length of a circumference of the epitaxial layer; and performing a lift-off process to separate the wafer substrate from the epitaxial layer.

DETAILED DESCRIPTION

In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions, and processes, etc., in order to provide a thorough understanding of the present disclosure. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present disclosure. Reference throughout this specification to “one embodiment,” “an embodiment”, “some embodiments” or the like means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in one embodiment,” “in an embodiment”, “according to some embodiments” or the like in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

Although most of terms described in the following disclosure use singular nouns, said terms may also be plural in accordance with figures or practical applications.

Reference is made toFIG. 1andFIGS. 2A to 2C.FIG. 1is a flow chart of a method100for preventing crack extensions during a lift-off process LO according to some embodiments of the present disclosure.FIG. 2Ais a schematic cross-sectional view of an intermediate step of the method100ofFIG. 1.FIG. 2Bis a schematic top view of an intermediate step of the method100ofFIG. 1.FIG. 2Cis a schematic cross-sectional view of an intermediate step of the method100ofFIG. 1. The method100begins with an operation110in which an epitaxial layer220is formed on a wafer substrate210(referred toFIG. 2A). The method100continues with an operation120in which a guard trench230is formed in the epitaxial layer220(referred toFIG. 2B). The method100continues with an operation130in which a lift-off process LO is performed to separate the wafer substrate210from the epitaxial layer220(referred toFIG. 2C).

Reference is made toFIGS. 2A and 3.FIG. 3is an enlarged cross-sectional view of the wafer substrate210and the epitaxial layer220as shown inFIG. 1. In some embodiments, the epitaxial layer220includes a first type semiconductor layer222, an active layer224, and a second type semiconductor layer226. The active layer224is in contact with the first type semiconductor layer222. The second type semiconductor layer226is joined with the first type semiconductor layer222through the active layer224. The first type semiconductor layer222can be a p-type semiconductor layer, but should not be limited thereto. The second type semiconductor layer224can be an n-type semiconductor layer, but should not be limited thereto. In some embodiments, the formation of the epitaxial layer220on the wafer substrate210includes forming the second type semiconductor layer226on the wafer substrate210, forming the active layer224on the second type semiconductor layer226, and forming the first type semiconductor layer222on the active layer224. In some embodiments, the wafer substrate210includes one of a sapphire, a silicon, a silicon carbide (SiC), a gallium arsenide (GaAs), and a gallium nitride (GaN), but should not be limited thereto.

Reference is made toFIGS. 2B and 4. A view angle ofFIG. 2Bis viewed in an opposite direction of a Z direction in which the wafer substrate210is not visible in the figure. That is, the epitaxial layer220shown inFIG. 2Bis lying on an X-Y plane.FIG. 4is an enlarged cross-sectional view of the epitaxial layer220showing a guard trench230in the epitaxial layer220according to some embodiments of the present disclosure. The guard trench230is formed in a surface of the epitaxial layer220away from the wafer substrate210. In some embodiments, when a guard trench230is formed in the epitaxial layer220, a depth H1of the guard trench230in a thickness direction (i.e. the Z direction as shown inFIG. 4) of the epitaxial layer220is at least half of a thickness H2of the epitaxial layer220. If the depth H1is too small, cracks may extend across the guard trench230through a portion of the epitaxial layer220underneath the guard trench230. The guard trench230is formed in a surface of the epitaxial layer220away from the wafer substrate210. The guard trench230is so named due to one of its applications in which the epitaxial layer220is guarded by the guard trench230and the cracks formed during a manufacturing process (e.g., a laser lift-off process) are prevented from extending across the guard trench230. The guard trench230can be formed by wet etching, dry etching, laser cutting, or mechanical cutting, but should not be limited thereto. A total length of the guard trench230is greater than at least a quarter of a total length of the circumference222C of the epitaxial layer220. Specifically, the total length is a length measured from a first end e1to a second end e2of the guard trench230along a path of the guard trench230. Although a shape of the guard trench230shown inFIG. 2Bis an arc, other shapes are also within the scope of the present disclosure. If the total length of the guard trench230is too short, cracks may still be formed due to insufficient space for sharing the stress. In some embodiments, the total length of the guard trench230is less than the total length of the circumference220C of the epitaxial layer220. If the total length of the guard trench230is too long, the yield of the epitaxial layer220which can be used to manufacture light-emitting devices after chipping may drop to an unsatisfactory situation. Notice that the “yield” herein includes a ratio between a portion of the epitaxial layer220which can be used to fabricate devices (e.g., light-emitting diodes) after the guard trench230is formed and the whole epitaxial layer220.

Reference is made to2C, in which the lift-off process LO is performed to separate the wafer substrate210from the epitaxial layer220. In some embodiments, the lift-off process LO includes a laser lift-off process. In some other embodiments, chemical lift-off processes are also within the scope of the present disclosure. The guard trench230is omitted since the guard trench230is too narrow to be explicitly shown inFIG. 2C.

Reference is made toFIG. 5.FIG. 5is a schematic top view of the epitaxial layer220according to some embodiments of the present disclosure. A view angle ofFIG. 5is the same as that ofFIG. 2B. In some embodiments, the surface of the epitaxial layer220away from the wafer substrate210has a partial area220A surrounded by the guard trench230and at least greater than 40 percent of a total area of the surface, such that the guard trench230can better share a stress distributed among the epitaxial layer220. Specifically, said partial area220A is defined and surrounded by the guard trench230and a virtual straight line230L connecting the two ends e1and e2of the guard trench230. In some embodiments, cracks are easier to be formed near a circumference220C of the epitaxial layer220. As a result, the guard trench230can better prevent cracks from extending into the partial area220A. If said partial area220A is too small, crack extensions may be too long due to insufficient guard trench230for sharing the stress.

Reference is made toFIG. 6.FIG. 6is a schematic top view of the epitaxial layer220according to some embodiments of the present disclosure. A difference between embodiments as illustrated byFIG. 6and the embodiments as illustrated byFIG. 5is that a partial area220B is enclosed by the guard trench230-1in the embodiments as illustrated byFIG. 6. In these embodiments, a length of the virtual straight line230L used for defining the area is infinitesimal, or there is substantially no virtual straight line230L.

Reference is made toFIG. 7.FIG. 7is a schematic top view of the epitaxial layer220according to some embodiments of the present disclosure. A difference between embodiments as illustrated byFIG. 7and the embodiments as illustrated byFIG. 2Bis that an additional guard trench230′ is formed in the epitaxial layer220. In some embodiments, a sum of the total length of the guard trench230and a total length of the additional guard trench230′ present in the epitaxial layer220is greater than at least a quarter of the total length of the circumference220C of the epitaxial layer220. In some embodiments, the sum of the total length of the guard trench230and the total length of the additional guard trench230′ present in the epitaxial layer220is less than the total length of the circumference220C of the epitaxial layer220. In some embodiments, there may be a plurality of additional guard trenches230′ present in the epitaxial layer220.

In summary, a method for preventing crack extensions during a lift-off process is provided in some embodiments of the present disclosure in which at least one guard trench is formed to share a stress generated by the lift-off process, so as to prevent crack extensions in the epitaxial layer.