PACKAGE STACK STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

BACKGROUND

1. Technical Field

The present disclosure relates to package structures, and, more particularly, to a package stack structure and a method for manufacturing the same.

2. Description of Related Art

With the evolution of semiconductor packaging techniques, numerous types of packages have been developed for semiconductor devices. More particularly, a plurality of package structures are stacked on one another to form a package-on-package (POP) structure in order to enhance the electrical functionality and save space in the package. This type of packaging method takes advantage of the heterogeneous integration characteristic of system in packages (SiP), allowing various electronic components having different functionalities, such as memories, CPUs, graphics processors, image application processors, and the like, to be integrated together by stacking them. This makes it suitable for applications in compact and light electronic products.

FIGS. 1A and 1Bare schematic cross-sectional diagrams depicting different aspects of a conventional package stack structure1and1′.

As shown inFIG. 1A, the package stack structure1includes a first package substrate11and a second package substrate12. The first package substrate11includes a plurality of circuit layers110, and the second package substrate12includes a core layer120and a plurality of circuit layers121. A first semiconductor component10is provided on the first package substrate11in a flip-chip manner, and then an underfill14is filled between the first semiconductor component10and the first package substrate11. Second semiconductor components15are wire bonded on the second package substrate12, and then an encapsulant16is used to encapsulate the second semiconductor components15. A plurality of solder balls13are then stacked to electrically connect the first package substrate11and the second package substrate12.

As shown inFIG. 1B, the package stack structure1′ includes a first package substrate11and a second package substrate12. The first package substrate11includes a plurality of circuit layers110, and the second package substrate12includes a core layer120and a plurality of circuit layers121. A first semiconductor component10is provided on the first package substrate11in a flip-chip manner, and an underfill14is filled between the first semiconductor component10and the first package substrate11. Then, a plurality of solder balls13are stacked to electrically connect the first package substrate11and the second package substrate12. Thereafter, an encapsulant16′ is used to encapsulate the solder balls13and the first semiconductor component10, and then second semiconductor components15′ are wire bonded on the second package substrate12in a flip-chip manner.

However, in the conventional package stack structures1and1′, the second package substrates12include the core layers120, which makes it more difficult for the package stack structure1,1′ to meet the demand of a thin structure.

Therefore, there is a need for a solution that addresses the aforementioned issues in the prior art.

SUMMARY

In view of the aforementioned shortcomings of the prior art, the present disclosure provides a package stack structure, which may include: a first unit including an insulating layer, a circuit portion and a plurality of conductive elements, wherein the insulating layer includes a first surface and a second surface opposite to the first surface, the circuit portion is combined with the insulating layer, the conductive elements are disposed vertically on the first surface of the insulating layer and in contact with the circuit portion, and the first unit includes no core layer; a board stacked on the first surface of the insulating layer via the conductive elements; and a first electronic component provided on the board.

In an embodiment, the package stack structure may further include a support portion combined on the second surface of the insulating layer. In another embodiment, the support portion may include at least one metal layer, and is combined with the second surface of the insulating layer via the metal layer. In yet another embodiment, the support portion may include a plurality of metal layers and a plurality of isolation layers, and is combined with the second surface of the insulating layer via the metal layers.

The present disclosure also provides a method for manufacturing a package stack structure, which may include: providing a first unit including an insulating layer, a circuit portion, a plurality of conductive elements and a support portion, wherein the insulating layer includes a first surface and a second surface opposite to first surface, the circuit portion is combined with the insulating layer, the conductive elements are disposed vertically on the first surface of the insulating layer and in contact with the circuit portion, and the insulating layer is combined with the support portion via the second surface; disposing the first unit on a second unit, wherein the second unit includes a board and a first electronic component provided on the board, and the insulating layer, the circuit portion and the support portion are stacked on the board via the conductive elements; and removing the support portion after disposing the first unit on the second unit.

In an embodiment, the support portion includes at least one metal layer, and is combined with the second surface of the insulating layer via the metal layer.

In an embodiment, the support portion includes a plurality of metal layers and a plurality of isolation layers, and is combined with the second surface of the insulating layer via the metal layers.

In an embodiment, the circuit portion includes at least one circuit layer.

In an embodiment, an outer surface of the circuit portion is lower than the second surface of the insulating layer.

In an embodiment, the conductive elements are solder balls, copper core balls or metallic parts.

In an embodiment, the method may further include disposing a second electronic component on the second surface of the insulating layer.

In an embodiment, the method may further include forming an encapsulant between the first surface of the insulating layer and the board.

In an embodiment, the circuit portion is embedded in the insulating layer.

As is clear from the above, the package stack structure and the method for manufacturing the same according to the present disclosure allow the first unit to be stacked on the board of the second unit before the support portion is removed, thereby reducing the overall thickness of the package stack structure while maintaining stability of the first unit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present disclosure is described by the following specific embodiments. Those with ordinary skills in the arts can readily understand other advantages and functions of the present disclosure after reading the disclosure of this specification. The present disclosure may also be practiced or applied with other different implementations. Based on different contexts and applications, the various details in this specification can be modified and changed without departing from the spirit of the present disclosure.

It should be noted that the structures, ratios, sizes shown in the drawings appended to this specification are to be construed in conjunction with the disclosure of this specification in order to facilitate understanding of those skilled in the art. They are not meant, in any ways, to limit the implementations of the present disclosure, and therefore have no substantial technical meaning. Without affecting the effects created and objectives achieved by the present disclosure, any modifications, changes or adjustments to the structures, ratio relationships or sizes, are to be construed as fall within the range covered by the technical contents disclosed herein. Meanwhile, terms, such as “above”, “first”, “second”, “third”, “one”, “a”, “an” and the like, are for illustrative purposes only, and are not meant to limit the range implementable by the present disclosure. Any changes or adjustments made to their relative relationships, without modifying the substantial technical contents, are also to be construed as within the range implementable by the present disclosure.

FIGS. 2A to 2Dare schematic cross-sectional diagrams illustrating a method for manufacturing a package stack structure2in accordance with a first embodiment of the present disclosure.

As shown inFIG. 2A, a first unit2ais provided, which includes an insulating layer20, a circuit portion21, a plurality of conductive elements22and a support portion23.

The insulating layer20includes a first surface20aand a second surface20bopposite to the first surface20a, and the second surface20bis combined with the support portion23.

In an embodiment, the insulating layer20may be made of a dielectric material such as a prepreg, a molding compound, an Ajinomoto Build-up Film (ABF), or the like. In an embodiment, the thickness t of the insulating layer20is 15 μm.

The circuit portion21is combined with the insulating layer20by embedding itself, for example, in the insulating layer20. In an embodiment, the circuit portion21includes a first circuit layer211embedded in the first surface20a, a second circuit layer212embedded in the second surface20b, and a plurality of conductive blind vias210electrically connecting the first and second circuit layers211and212. It can be appreciated that the first and second circuit layers211and212can also be provided on the first surface20aand the second surface20b, respectively.

In an embodiment, the first circuit layer211, the second circuit layer212, and the conductive blind vias210may be made of copper, nickel/gold or other appropriate conductive materials.

The conductive elements22are provided vertically on the first surface20aof the insulating layer20and are in contact with the first circuit layer211of the circuit portion21.

In an embodiment, the conductive elements22are solder balls, copper core balls, metallic (e.g., copper or gold material) parts (in the shapes of columns, lumps or needles) or the like.

Moreover, there is no limit on the shapes of the conductive elements22. In an embodiment, the conductive elements22can be of cone shape (i.e., their volumes taper from the bottom to the top) or other shapes.

In an embodiment, the height h of the conductive elements22protruding out of the first surface20acan be, for example, 165 μm.

The support portion23can be a singulated board unit or the entire structure (i.e., including a plurality of units), in strip form or wafer form, for example.

In an embodiment, the support portion23comprises a first metal layer231, a second metal layer232and a third metal layer233, and is combined with the second surface20bof the insulating layer20and the second circuit layer212via the first metal layer231.

In an embodiment, the first and third metal layers231and233are copper layers, and the second metal layer232is a nickel layer.

In an embodiment, the thickness d of the first metal layer231and the thickness r of the second metal layer232are 3 μm, and the thickness L of the third metal layer233is 70 μm.

As shown inFIG. 2B, the first unit2ais disposed on a second unit2b, wherein the second unit2bincludes a board24and a first electronic component25provided on the board24, and the first surface20aof the insulating layer20is stacked on the board24(or the first unit2ais stacked on the board24). In an embodiment, an encapsulant26is formed between the first surface20aof the insulating layer20and the board24to encapsulate the first electronic component25and the conductive elements22.

The board24is a circuit structure with a core or a coreless circuit structure, such as a substrate, and includes, for example, circuit layout such as fan-out redistribution layers (RDLs). It can be appreciated that the board can also be other board material for carrying chips, such as a leadframe, a wafer, or other carrier with metal routings, and the present disclosure is not limited to those described above.

In an embodiment, the conductive elements22are melted and combined onto solder materials241on conductive pads240of the board24.

The first electronic component25can be an active component, a passive component or a combination of both, wherein the active component can be a semiconductor chip, for example, and the passive component can be a resistor, a capacitor, or an inductor, for example.

In an embodiment, the first electronic component25is disposed on the board24in a flip-chip manner and electrically connected with the board24via a plurality of conductive bumps250(such as a solder material). In another embodiment, the first electronic component25can be wire bonded and electrically connected to the board24via a plurality of bonding wires (not shown). In yet another embodiment, the first electronic component25may be in direct contact with the circuits on the board24. Nevertheless, the way in which the first electronic component25is electrically connected with the board24is not limited to those described above.

The encapsulant26can be formed using polyimide (PI), a dry film, an epoxy resin, a molding compound, or the like, and the present disclosure is not limited as such.

As shown inFIG. 2C, the support portion23is removed, and the second circuit layer212is exposed from the second surface20bof the insulating layer20.

In an embodiment, the third metal layer233and the second metal layer232are removed through an etching process to obtain a planar surface. Then, the first metal layer231is micro-etched extending down to 3 to 5 μm below the second surface20bof the insulating layer20(i.e., removing a portion of the second circuit layer212), such that the outer surface of the second circuit layer212of the circuit portion21is lower than the second surface20bof the insulating layer20.

It can be understood that, if the support portion23is removed before the insulating layer20with the embedded circuit portion21is stacked on the board24, during the process of removing the support portion23, the first unit2adue to a lack of rigidity cannot be held stably. This may cause shifting of the first unit2a, and the insulating layer20cannot be picked and placed by the machine. Therefore, in the method according to the present disclosure, the first unit2ais first stacked on the board24before the support portion23is removed, and the first unit2ais thus held stably through the board24(and the encapsulant26) during the thinning process (i.e., removal of the support portion23), resolving the issue of the pick and place failure because of a lack of rigidity.

As shown inFIG. 2D, the structure ofFIG. 2Cis singulated along a cutting path S shown inFIG. 2C, then a second electronic component27is disposed on the second surface20bof the insulating layer20, and conductive elements such as solder balls28are planted below the board24.

In an embodiment, the second electronic component27can be a package, an active component, a passive component, or a combination of the above, wherein the package is, for example, a chip scale package (CSP), the active component can be a semiconductor chip, for example, and the passive component can be a resistor, a capacitor, or an inductor, for example. In an embodiment, the second electronic component27is stacked on the second surface20band electrically connected with the second circuit layer212via a plurality of conductive bumps270such as a solder material. In another embodiment, the second electronic component27can be wire bonded and electrically connected to the second circuit layer212via a plurality of bonding wires (not shown). In yet another embodiment, the second electronic component27may be in direct contact with the second circuit layer212. Nevertheless, the way in which the second electronic component27is electrically connected with the second circuit layer212is not limited to those described above.

In the method according to the present disclosure, the first unit2ais first stacked on the board24of the second unit2b, and then a portion of the first unit2ais removed (i.e., the support portion23is removed). Thus, compared to the prior art, the method according to the present disclosure reduces the overall thickness of the package stack structure2since the coreless circuit portion21is stacked on the board24.

FIGS. 3A to 3Dare schematic cross-sectional diagrams illustrating a method for manufacturing a package stack structure3in accordance with a second embodiment of the present disclosure. The second embodiment and the first embodiment differ only in the structure of the first unit.

As shown inFIG. 3A, which is similar to the process shown inFIG. 2B, a first unit3aincluding the insulating layer20, a circuit portion31, a plurality of conductive elements22, and a support portion33is stacked on the board24of the second unit2b, and the encapsulant26is formed between the first surface20aof the insulating layer20and the board24.

The circuit portion31is a single circuit layer that is embedded in the first surface20aof the insulating layer20.

The conductive elements22are disposed vertically on the first surface20aof the insulating layer20, are in contact with the circuit portion31, and are melted and combined onto the board24.

The support portion33includes first and second metal layers331and332and first and second isolation layer330and333, and is bonded to the second surface20bof the insulating layer20via the first metal layer331.

In an embodiment, the insulating layer20and the second isolation layer333can be made of Ajinomoto Build-up Films (ABFs), the first and second metal layers331and332can be made of copper layers, and the first isolation layer330acts as a core layer. It can be appreciated that the first unit3ais a symmetrical structure about the core layer. The insulating layer20and the second isolation layer333can be made of the same or different materials, and the structure of the first unit3ais not limited to that described above.

As shown inFIG. 3B, the support portion33is removed by grinding to expose the second surface20bof the insulating layer20.

As shown inFIG. 3C, a plurality of openings300are formed on the second surface20bof the insulating layer20using laser drilling, for example, such that a portion of the circuit portion31is exposed from the second surface20bof the insulating layer20.

As shown inFIG. 3D, solder balls28are planted below the board24, and singulation is performed. Then, the second electronic component27is disposed on the second surface20bof the insulating layer20, and conductive bumps270disposed in the openings300are electrically connected to the circuit portion31.

In an embodiment, the first unit3ais first stacked on the board24, and then a portion of the first unit3ais removed (i.e., the support portion33is removed). Thus, compared to the prior art, the method according to the present disclosure allows the first unit3ato be held stably during the thinning process (i.e., removal of the support portion33), and resolves the issue of the pick and place failure because of a lack of rigidity. The method according to the present disclosure also reduces the overall thickness of the package stack structure3since the coreless circuit portion31is stacked on the board24.

In an embodiment, as shown inFIG. 4, a support portion43of the first unit may also be a single metal layer, such as copper, iron or stainless steel, and is etched or ground away during the manufacturing process.

The present disclosure further provides a package stack structure2,3, which includes an insulating layer20, a circuit portion21,31, a plurality of conductive elements22, a board24, and at least one first electronic component25.

The insulating layer20includes a first surface20aand a second surface20bopposite to the first surface20a.

The circuit portion21,31is combined with the insulating layer20, by embedding themselves, for example, in the insulating layer20.

The conductive elements22are disposed vertically on the first surface20aof the insulating layer20and in contact with the circuit portion21,31.

The board24is disposed on the conductive elements22in order to be stacked on the first surface20aof the insulating layer20.

The first electronic component25is provided on the board24.

In an embodiment, the circuit portion21,31includes at least one circuit layer.

In an embodiment, the outer surface of the circuit portion21is lower than the second surface20bof the insulating layer20.

In an embodiment, the conductive elements22are solder balls, copper core balls or metallic parts.

In an embodiment, the package stack structure2,3further includes a second electronic component27provided on the second surface20bof the insulating layer20.

In an embodiment, the package stack structure2,3further includes an encapsulant26formed between the first surface20aof the insulating layer20and the board24.

In an embodiment, the package stack structure2,3further includes a support portion23,33,43combined on the second surface20bof the insulating layer20. In another embodiment, the support portion23,43includes at least one metal layer (e.g., first to third metal layers231,232and233), and is combined with the second surface20bof the insulating layer20via the metal layer. In yet another embodiment, the support portion33includes a plurality of metal layers (e.g., first and second metal layers331and332) and a plurality of isolation layers (e.g., first and second isolation layers330and333), and is combined with the second surface20bof the insulating layer20via the metal layers.

In summary, the package stack structure and the method for manufacturing the same according to the present disclosure allow the first unit to be stacked on the board of the second unit before the support portion is removed, thereby reducing the overall thickness of the package stack structure while maintaining stability of the first unit.

The above embodiments are only used to illustrate the principles of the present disclosure, and should not be construed as to limit the present disclosure in any way. The above embodiments can be modified by those with ordinary skill in the art without departing from the scope of the present disclosure as defined in the following appended claims.