Semiconductor device for domain crossing

An apparatus, for use in a semiconductor device, for providing a domain crossing operation. The apparatus includes a domain crossing sensing block, in response to an operation mode signal, first and second delay locked loop (DLL) clock signals and a CAS latency, generates a plurality of selection signals. An output enable signal generator, in response to the plurality of selection signals, generates a plurality of output enable signals. A data control block, in response to the output enable signals and the CAS latency, controls a data output operation in the semiconductor device. Each of a plurality of data align block, in response to the selection signals, the first and second DLL clock signals and an address signal, aligns data corresponding to the address signal in the data output operation.

FIELD OF INVENTION

The present invention relates to a semiconductor device; and, more particularly, to a semiconductor device for domain crossing in a synchronous dynamic random access memory SDRAM and double data rate DDR, DDRII, DDRIII SDRAMs.

DESCRIPTION OF PRIOR ART

Generally, in a semiconductor memory device, a domain crossing takes place during its operation. For instance, some devices use an internal clock as an operation reference and the others use a delay locked loop (DLL) clock as the operation reference. In addition, a conversion from a receiver domain to a transmitter domain comes under the domain crossing.

FIG. 1is a block diagram showing a semiconductor device included in a conventional memory device for domain crossing.

As shown, the conventional memory device includes a first flip-flop131, a memory cell140, a second flip-flop150, a plurality of pipe latches180, a driver190, a third flip-flop132, a domain crossing circuit161, a controlling and generating block162, a second read controller170, an internal clock generator110and a DLL block120.

For the sake of reading and writing data, the conventional memory device may further include more specific function blocks. However, inFIG. 1, there is described only specific function blocks for domain crossing in detail.

An internal clock INT—CLK is generated from an external clock EXT—CLK through the internal block generator110. The DLL block generates a DLL clock DLL—CLK from the external clock EXT—CLK. Herein, a delay time when the DLL clock passes through a first read controller, a second read controller170and the driver190is defined as a flight time. In the conventional memory device, a data access is synchronized with the external clock EXT—CLK. As a result, in the DLL block120, the DLL clock should be generated by compensating the flight time in order to supporting a reliability of the conventional semiconductor memory device.

Herein, compared with the first and third flip-flops131and132using the internal clock INT—CLK as a reference clock, the controlling and generating block162, the second read controller170, the plurality of pipe latches180and the driver190use the DLL clock as the reference clock. Namely, the domain crossing has occurred. For the domain crossing of the reference clock, there is the domain crossing circuit161.

FIG. 2is a block diagram describing the conventional domain crossing circuit161.

As shown, the conventional domain crossing circuit includes first and second output enable signal generators210and230, a DLL clock delay block220, a data controller240, a data output controller250, first and second data align signal generators260and270.

The first output enable signal generator210receives a read command signal CASP—RD and the internal clock INT—CLK and outputs an initial output enable signal OE00. The DLL clock delay block220receives a column address strobe (CAS) latency CL and rising and falling DLL clock signals RCLK—DLL and FCLK—DLL generated from the DLL block120and generates an output enable clock signal in response to a selected clock signal based on the CAS latency CL. Then, the second output enable signal generator230generates a plurality of output enable signals in response to the initial output enable signal OE00and the output enable clock signal.

The data controller240receives the CAS latency CL and the plurality of output enable signals and determines a valid period of output data synchronized with the external clock. The data output controller250receives the plurality of output enable signals and determines an active section of a data strobe signal.

After receiving each address signal, e.g., ADD0, the internal clock INT—CLK, the rising and falling DLL clocks RCLK—DLL and FCLK—DLL, the CAS latency CL and the output enable clock signal, each data align signal generator, e.g.,260outputs a data align signal in response to a logical value of the inputted address signal ADD0and the CAS latency CL.

FIG. 3is a block diagram depicting a DLL clock delay block220in the conventional domain crossing circuit shown inFIG. 2.

As shown, the DLL clock delay block220includes first to third rising clock delay blocks321A to321C, first to third falling clock delay block322A to322C and first and second MUXs321D and322D.

The DLL clock delay block220receives the rising and falling DLL clocks RCLK—DLL and FCLK—DLL. The rising DLL clock RCLK—DLL is input to the first to third rising clock delay blocks321A to321C. Herein, the first to third rising clock delay blocks321A to321C have each different delay value. As a result, first to third delayed rising DLL clocks RCLK—DLL—OE1, RCLK—DLL—OE2and RCLK—DLL—OE3each having a different delay value are output from the first to third rising clock delay blocks321A to321C. The first MUX321D outputs at least one among the rising DLL clock RCLK—DLL and the first to third delayed rising DLL clocks RCLK—DLL—OE1, RCLK—DL—OE2and RCLK—DL—OE3in response to the CAS latency.

Likewise, the first to third falling clock delay block322A to322C receive the falling DLL clocks FCLK—DLL and outputs first to third delayed falling DLL clocks FCLK—DLL—OE1, FCLK—DLL—OE2and FCLK—DLL—OE3. Then, the second MUX322D outputs at least one among the falling DLL clock FCLK—DLL and the first to third delayed falling DLL clocks FCLK—DLL—OE1, FCLK—DL—OE2and FCLK—DL—OE3in response to the CAS latency.

FIG. 4is a schematic circuit diagram showing a second output enable signal generator230in the conventional domain crossing circuit shown inFIG. 2.

The second output enable signal generator230includes a plurality of flip-flops. The plurality of flip-flops is divided into two groups: one432A to432F receives output signals of the first MUX321D; and the other433A to433F receives output signals of the second MUX322D. The initial output enable signal OE00is inputted to a first flip-flop431, synchronized with the first delayed rising DLL clocks RCLK—DLL—OE1and outputted to first flip-flops432A and433A of the two groups. The plurality of flip-flops respectively outputs the plurality of output enable signals OE10—DLL, OE15—DLL to OE65—DLL, OE70—DLL in response to the input delayed rising and falling DLL clock. Herein, the plurality of output enable signals OE10—DLL, OE15—DLL to OE65—DLL, OE70—DLL is for determining a valid period of a data (DQ) which is output to an external circuit after it is synchronized with rising and falling edges of the external clock EXT—CLK.

FIG. 5is a schematic circuit diagram showing the data controller240in the conventional domain crossing circuit shown inFIG. 2.

The data controller240receives the plurality of output enable signals OE10—DLL, OE15—DLL to OE65—DLL, OE70—DLL and outputs a data pre-enable signal QSEN—PRE and a data enable signal QSEN in response to the CAS latencies CL4to CL10. As shown, the data controller240includes first and second signal selection blocks541and543and first and second logics542and544. Each signal selection block having a plurality of inverters and a plurality of NAND gates receives a plurality of output enable signals OE15—DLL to OE65—DLL outputted from the other flip-flop group433A to433F and selects one in response to the CAS latencies CL4to CL10. The first and second logics542and544receives at least one output signals, which are output from the first and second signal selection blocks541and543, and outputs the data pre-enable signal QSEN—PRE and the data enable signal QSEN.

FIGS. 6A and 6Bare schematic circuit diagrams showing the data output controller250in the conventional domain crossing circuit shown inFIG. 2.

As shown, the data output controller250includes a rising output enable signal generator651, a falling output enable signal generator652, a signal process block653and a third logic654.

The rising output enable signal generator651receives a plurality of output enable signals OE20—DLL to OE60—DLL outputted from the one flip-flop group433A to433F in the second output enable signal generator230and selects one in response to the CAS latencies CL4to CL10. The falling output enable signal generator652receives a plurality of output enable signals OE15—DLL to OE65—DLL output from the other flip-flop group433A to433F in the second output enable signal generator230and selects one in response to the CAS latencies CL4to CL10. The signal process block653receives the plurality of output enable signals OE20—DLL to OE60—DLL output from the one flip-flop group433A to433F and outputs a result signal of NOR-NAND-NOR calculation to the third logic654. Then, the third logic654outputs a control signal determining an active period of a data strobe signal (DQS) outputted to an external circuit after synchronized with rising and falling edges of the external clock EXT—CLK.

FIG. 7is a schematic circuit diagram showing the first data align signal generator260in the conventional domain crossing circuit shown inFIG. 2.

The first data align signal generator260has a plurality of flip-flops762to766. Each flip-flop receives each delayed rising DLL clock, e.g., RCLK—DLLOE1, RCLK—DLL—OE2and RCLK—DLL—OE3and the rising DLL clock RCLK—DLL at a clock terminal and outputs each data align signal, e.g., SOSEZ15, SOSEZ25, SOSEZ35, SOSEZ45and SOSEZ55. Likewise, if not shown, the second data align signal generator270has a plurality flip-flops which respectively receive each delayed falling DLL clock, e.g., FCLK—DLL—OEl, FCLK—DLL—OE2and FCLK—DLL—OE3and the falling DLL clock FCLK—DLL at a clock terminal and outputs each data align signal.

FIGS. 8A to 8Care timing diagrams demonstrating an operation of the conventional domain crossing circuit shown inFIG. 2. In detail,FIG. 8Bdescribes the operation of the conventional single clock domain crossing circuit when the CAS latency is 3; andFIG. 8Cdepicts the operation of the convention multi clocks domain crossing circuit when the CAS latency is 5.

As shown inFIG. 8A, it is assumed that the CAS latency is 6. After a read instruction RD is input, a data output enable signal ROUTEN should be activated in response to the CAS latency. Namely, the data output enable signal ROUTEN is activated before the sixth timing ‘6’ of the external clock CLK if the read instruction RD is inputted at the initial timing ‘0’.

In the conventional domain crossing circuit, the DLL clock DLL—CLK passes through a plurality of flip-flops. In response to the CAS latency CL, the initial output enable signal OE00is also delayed by a plurality of flip-flops. However, if an operation of the semiconductor system is faster, the plurality of flip-flops delaying DLL clock is unstable because a setup time of each flip-flop is not guaranteed. Thus, a total delay time ΔT of the output enable signal is not fixed in response to the CAS latency CL. Then, it is not guaranteed that the data output enable signal ROUTEN is activated in response to the CAS latency CL.

In addition, an abnormal operation of the semiconductor system can result from a low power voltage, a temperature, a complex process and the like. If the setup time of each flip-flop included in a high frequency semiconductor system is not guaranteed sufficiently, the high frequency semiconductor system may not operate properly.

SUMMARY OF INVENTION

It is, therefore, an object of the present invention to provide a semiconductor system having a domain crossing circuit which detects a phase difference between an internal clock and a delay locked loop (DLL) clock, senses a flight time when the DLL clock passes from a DLL clock generator to a data output driver and protects against an abnormal operation of the semiconductor system resulting from a high frequency, a low power voltage, a temperature, a complex process and the like by considering the phase difference and the flight time into the domain crossing circuit.

In accordance with an aspect of the present invention, it is provided with an apparatus, for use in a semiconductor device, for providing a domain crossing operation including a domain crossing sensing block in response to an operation mode signal, first and second delay locked loop (DLL) clock signals and a CAS latency for generating a plurality of selection signals; an output enable signal generator in response to the plurality of selection signals for generating a plurality of output enable signals; a data control block in response to the output enable signals and the CAS latency for controlling a data output operation in the semiconductor device; and a plurality of data align block, each in response to the selection signals, the first and second DLL clock signals and an address signal for aligning data corresponding to the address signal in the data output operation.

In accordance with another aspect of the present invention, it is provided with a semiconductor device for providing a domain crossing operation including a domain crossing sensing block in response to an operation mode signal, first and second delay locked loop (DLL) clock signals and a CAS latency for generating a plurality of selection signals; an output enable signal generator in response to the plurality of selection signals for generating a plurality of output enable signals; a data control block in response to the output enable signals and the CAS latency for controlling a data output operation in the semiconductor device; and a plurality of data align block, each in response to the selection signals, the first and second DLL clock signals and an address signal for aligning data corresponding to the address signal in the data output operation.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a semiconductor device for domain crossing according to the present invention will be described in detail referring to the accompanying drawings.

FIG. 9is a block diagram describing a domain crossing circuit in accordance with the present invention.

The domain crossing circuit includes a domain crossing sensing block920, a first output enable signal generator910, a second output enable signal generator930, a data controller940, a data output controller950, a first data align signal generator960and a second data align signal generator970.

The domain crossing sensing block920enabled by an internal clock INT—CLK receives a refresh state signal SREF, a DLL disable signal DIS—DLL and a RAS idle signal RASIDLE. Then, the domain crossing sensing block920detects a phase of rising and falling DLL clock signals RCLK—DLL and FCLK—DLL in response to a CAS latency CL and generates a setup selection signal SELB and a plurality of output selection signals A, B and C in response to the detection result.

The first output enable signal generator910generates an output initialization signal OE00synchronized with the internal clock INT—CLK by a read instruction. The second output enable signal generator930receives the plurality of output selection signals A, B and C and the output initialization signal OE00and generates a plurality of delayed output enable signals.

The data controller940receives the plurality of delayed output enable signals and generates a data enable signal deciding a valid period of an outputted data. The data output controller950receives the plurality of delayed output enable signals and generates a data strobe enable signal which defines an active period of a data strobe signal.

The first data align signal generator960receives a first address ADD0and generates a first data align signal which aligns the input data in response to the first address ADD0and the detection result of the domain crossing sensing block. And, the second data align signal generator970receives a second address ADD1and generates a first data align signal which aligns the input data in response to the second address ADD1and the detection result of the domain crossing sensing block.

FIG. 10is a block diagram depicting the domain crossing sensing block920in the domain crossing circuit in accordance with the present invention.

The domain crossing sensing block920includes a sensing control signal generator1010, a phase detector1020, a reading path modeling block1030and a latency detector1040.

The sensing control signal generator1010generates a sensing start signal STARTZ in response to the refresh state signal SREF, the DLL disable signal DIS—DLL and the RAS idle signal RASIDLE. The phase detector1020compares the rising DLL clock signal RCLK—DLL with the falling DLL clock signal FCLK—DLL in response to the sensing start signal STARTZ and generates the setup selection signal SELB, which is activated during the CAS latency CL, and a phase detection signal FPVT—DETD, which defines a phase detection period, in response to the setup selection signal SELB;

The reading path modeling block1030delays the phase detection signal FPVT—DET by a predetermined value, which is equal to a delay time through a data reading path, and generates a delayed phase detection signal FPVT—DETD. The latency detector1040compares the delayed phase detection signal with the CAS latency synchronized with the internal clock and generates the plurality of output selection signals A, B and C.

FIG. 11is a block diagram showing the sensing control signal generator1010in the domain crossing circuit in accordance with the present invention.

As shown, the sensing control signal generator1010receives the refresh state signal SREF, the DLL disable signal DIS—DLL and the RAS idle signal RASIDLE. First, first and second edge pulse blocks1111and1112respectively output first and second edge pulses in response to the refresh state signal SREF and the DLL disable signal DIS—DLL. Then, the sensing start signal STARTZ is generated in response to the RAS idle signal RASIDLE, the internal clock INT—CLK and the first and second edge pulses.

FIG. 12is a block diagram describing the phase detector1020in the domain crossing circuit in accordance with the present invention.

The phase detector1020includes an internal to DLL phase detection block, a latency detection start block and a phase detection selection block.

The internal to DLL phase detection block has first to third flip-flops1211to1213and a first MUX1231. The first flip-flop1211synchronizes the supply voltage VDD with the internal clock INT—CLK, and the second and third flip-flops1212and1213respectively synchronizes an outputted signal of the first flip-flop with the rising and falling DLL clock FCLK—DLL and RCLK—DLL.

Then, the phase detection selection block receives output signals F and R of the second and third flip-flops1212and1213and generates the setup selection signal SELB.

Thereafter, the first MUX1231included in the internal to DLL phase detection block selects one of the outputted signals F and R of the second and third flip-flops1212and1213in response to the setup selection signal SELB.

Next, in latency detection start block1241, the selected signal OE01outputted from the first MUX1231is synchronized with the rising DLL clock RCLK—DLL. The latency detection start block1241outputs the phase detection signal FPVT—DET.

FIG. 13is an internal schematic circuit diagram depicting the flip-flop, e.g.,1211and1241included in the phase detector shown inFIG. 12.

As shown, each flip-flop synchronizes a data signal inputted at D terminal with a clock signal input at CLK terminal and outputs the synchronized data signal to Q terminal.

FIGS. 14A to 14Care block diagrams showing the latency detector1040in the domain crossing sensing block shown inFIG. 10.

As shown, the latency detector1040includes a first flip-flop group1410, a flight timing sensing block1430and a selector1450.

The first flip-flop group1410, which has a plurality of flip-flops, synchronizes the supply voltage VDD with the internal clock INT—CLK. In detail, each flip-flop included in the first flip-flop group1410receives the internal clock at a clock terminal, the sensing start signal at a reset terminal and a supply voltage at an input terminal. Then, input and output signals M0and M1of the last flip-flop in the first flip-flop group1410are output to the flight timing sensing block1430.

The delayed phase detection signal FPVT—DETD output from the reading path modeling block1030is delayed. As a result, a first control signal EN delayed by a delay block1420is output to the flight timing sensing block1430.

Referring toFIG. 14B, the flight timing sensing block1430receives the input and output signals M0and M1and the first control signal EN and generates a plurality of plurality of flight detection signals D1to D3in response to the input and output signals M0and M1.

Referring toFIG. 14C, the selector1450outputs the plurality of output selection signals A, B and C in response to the plurality of flight detection signals D1to D3. Herein, “CL6789A” means one among CL6, CL7, CL8, CL9and CL10.

FIG. 15is a block diagram describing the second output enable signal generator930in the domain crossing circuit shown inFIG. 9.

As described above, the second output enable signal generator930receives the plurality of output selection signals A, B and C and the output initialization signal OE00and generates the plurality of delayed output enable signals, e.g., OE2—40.

As shown, the second output enable signal generator930includes second to forth MUX1514,1524and1534and a plurality of flip-flops1511,1512, . . . ,1535.

The second MUX1514selects a based control signal for generating the plurality of delayed output enable signals in response to the setup selection signal SELB. Namely, the setup selection signal SELB determines whether the plurality of delayed output enable signals is generated based on the rising DLL clock RCLK—DLL or the falling DLL clock FCLK—DLL.

The 13thflip-flop1531synchronizes the based control signal with the rising DLL clock RCLK—DLL. After receiving an output signal from the 13thflip-flop1531, the 14thand 15thflip-flops1532and1533respectively outputs control signals RB and RC synchronized with the rising DLL clock RCLK—DLL. Then fourth MUX1534receives control signals RA, RB and RC outputted from the 13thto 15thflip-flops and selects one of them in response to the plurality of output selection signals A, B and C outputted from the selector1450. Then, the 16thto 18thflip-flops outputs some of the plurality of delayed output enable signals, e.g., OE70synchronized with the rising DLL clock RCLK—DLL.

Likewise, through the third MUX and the 8thto 12thflip-flops, the other of the plurality of delayed output enable signals, e.g., OE65are output synchronized with the falling DLL clock FCLK—DLL.

FIGS. 16A and 16Bare block diagrams describing the data output controller950in the domain crossing circuit shown inFIG. 9.

The data output controller950includes a rising output enable signal generator1610, a falling output enable signal generator1620and an output reset signal generator1630.

The rising output enable signal generator1610receives some of the plurality of delayed output enable signals, e.g., OE60synchronized with the rising DLL clock RCLK—DLL and selects one of them in response to the CAS latency, e.g., CL8. The selected signal is delayed by a block1614and, then, outputted as a rising output enable signal ROUTEN.

Namely, the data output controller950includes a plurality of enable signal generators for respectively receiving the plurality of delayed output enable signals, e.g., OE50and individually generating the data strobe enable signal, i.e., output enable signal ROUTEN by transmitting one of the plurality of output enable signals in response to a modified CAS latency, wherein the modified CAS latency results from a NOR operation on at least two CAS latencies, e.g., CL7and CL9.

Likewise, the falling output enable signal generator1620receives the others of the plurality of delayed output enable signals, e.g., OE55synchronized with the falling DLL clock FCLK—DLL and selects one of them in response to the CAS latency, e.g., CL7. The selected signal is delayed by a block1624and, then, output as a falling output enable signal FOUTEN.

The output reset signal generator1630receives the initial output enable signal OE00and some of the plurality of delayed output enable signals, e.g., OE60synchronized with the rising DLL clock RCLK—DLL. Then, the output reset signal generator1630outputs a data output reset signal RST—douz through a logical operation shown inFIG. 16B.

FIG. 17is a block diagram describing the data controller940in the domain crossing circuit shown inFIG. 9.

As shown, the data controller940receives some of the plurality of delayed output enable signals, e.g., OE2—45outputted from the second output enable signal generator930. Then, using each two delayed output enable signals, e.g., OE55and /OE65, a plurality of enable control signals are generated by each NAND gate, e.g.,1713.

Namely, the data controller940includes a plurality of enable control signal generators for respectively receiving the plurality of delayed output enable signals, e.g., OE2—45and individually generating the data enable signal by transmitting one of the plurality of output enable signals in response to a modified CAS latency, wherein the modified CAS latency is resulted from NOR operation of at least two CAS latencies, e.g., CL7and CL9.

Thereafter, first to fourth transmission blocks1715,1711,1726and1721respectively deliver the plurality of enable control signals in response to the CAS latency. Then, fifth and sixth logics1716and1727outputs a pre data enable signal qsEN—pre and a data enable signal qsEN. Herein, the data enable signal qsEN determines a valid period of an outputted data.

FIG. 18is a schematic circuit diagram showing the first data align signal generator960in the domain crossing circuit shown inFIG. 9. Herein, since the first and second data align signal generators960and970shown inFIG. 9have the same structure, a description about the second data align signal generator970is omitted.

As described above, the first data align signal generator960receives a first address ADD0and generates a first data align signal which aligns the input data in response to the first address ADD0and the detection result of the domain crossing sensing block920.

As shown, the first data align signal generator960includes a fifth MUX1824, a sixth MUX1834, a fifth flip-flop1831, sixth to seventh flip-flop groups and a signal generator1840.

The fifth MUX1824selects one of the rising and falling DLL clock signals RCLK—DLL and FCLK—DLL in response to the setup selection signal SELB. Then, the fifth flip-flop1831receives an output signal from the first MUX1824at an input terminal, the rising DLL clock signal RCLK—DLL at a clock terminal and the sensing start signal STARTZ at a reset terminal and synchronizing the output signal from the fifth MUX1824with the rising DLL clock signal RCLK—DLL.

The sixth flip-flop group1832and1833receives the output signal FA from the fifth flip-flop1831, wherein the sixth flip-flop group1832and1833has a plurality of flip-flops which receive respectively the falling DLL clock signal FCLK—DLL at a clock terminal, the sensing start signal STARTZ at a reset terminal and an output signal of the last flip-flop at an input terminal. Then, each flip-flop generates individually pre-align control signal, e.g., FB synchronized with the falling DLL clock signal FCLK—DLL.

The sixth MUX1834selects one among an output signal FA from the first flip-flip and the pre-align control signals FB and FC in response to the plurality of output selection signals A, B and C.

The seventh flip-flop group1835and1836receives an output signal SOSEZ1—35from the second MUX1834, wherein the seventh flip-flop group1835and1836has a plurality of flip-flops which receive respectively the falling DLL clock signal FCLK—DLL at a clock terminal, the sensing start signal STARTZ at a reset terminal and an output signal of the last flip-flop at an input terminal. Then, each flip-flop generates individually align control signals SOSEZ45and SOSEZ55synchronized with the falling DLL clock signal FCLK—DLL.

The signal generator1840receives the output signal SOSEZ1—35from the second MUX and the align control signals SOSEZ45and SOSEZ55and outputs the data align signal SOSEZ—RD in response to the CAS latency CL.

FIG. 19is a timing diagram demonstrating an operation of the domain crossing circuit shown inFIG. 9. Herein, it is assumed that the CAS latency is 7.

First, a read instruction RD is input at timing ‘0’. Then, at a predetermined timing <1> of the internal clock INT—CLK, the phase detector1020senses a phase of the rising or falling DLL clock signal RCLK—DLL or FCLK—DLL. Herein, the predetermined timing <1> is for guaranteeing a setup time of the domain crossing circuit after a data is inputted. The predetermined timing <1> is determined based on a circumstance such a high frequency, a low power voltage, a temperature, a complex process and the like.

For instance, referring toFIG. 19, when an operation frequency of the domain crossing circuit is high, the phase detector1020senses the falling DLL clock signal FCLK—DLL. In other case when the operation frequency is typical, the phase detector1020senses the rising DLL clock signal RCLK—DLL. Last, when the operation frequency is low, the phase detector1020senses the falling DLL clock signal FCLK—DLL.

FIGS. 20A and 20Bare as an example timing diagrams demonstrating an operation of a semiconductor memory device including the domain crossing circuit shown inFIG. 9.

Hereinafter, referring toFIG. 20A, the operation of the domain crossing circuit is described in detail.

First, the sensing start signal STARTZ becomes logic low level by the sensing control signal generator1010. In the phase detector1020, the first flip-flop1211outputs a logic high level output signal synchronized with a rising edge of the internal clock INT—CLK. Then, after the output signal of the first flip-flop1211is the logic high level, the output signal is detected at ‘B’ timing, not ‘a’ timing, because the setup time of the second and third flip-flops1212and1213is not guaranteed.

At this time, the output signal R of the third flip-flops1213is activated; and, then, the output signal F of the second flip-flops1212is activated. As a result, the setup selection signal SELB becomes a logic low level and the first MUX431outputs a selected one of the outputted signals R and F to the forth flip-flop1241.

Thereafter, the reading path modeling block100receives an output signal FPVT—DET of the fourth flip-flop1241and outputs the phase detection signal FPVT—DETD after delaying it for the flight time.

Then, in the latency detector1040, the phase detection signal FPVT—DETD is input to the delay block1420and converted into the first control signal EN. The flight timing sensing block1430receives the output signals M0and M1of the first flip-flop group1410and the first control signal EN and generates a plurality of plurality of flight detection signals D1to D3in response to the outputted signals M0and M1.

Referring toFIG. 20B, there are timing diagrams describing an operation of the domain crossing circuit in three cases corresponding to the operation frequency, the power voltage and the temperature.

Consequently, the domain crossing circuit of the present invention can operate stably under various circumstance by using the plurality of output enable signals generated from the second output enable signal generator930.

In addition, the domain crossing circuit in accordance with the present invention can detect a minute phase difference between an internal clock and a delay locked loop (DLL) clock and sense a flight time when the DLL clock passes from a DLL clock generator to a data output driver. Then, in response to the phase difference and the flight time, the domain crossing circuit can protect against an abnormal operation of the semiconductor system resulting from a high frequency, a low power voltage, a high temperature, a complex process and the like.