Decision feedback equalization embedded in a slicer

An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

BACKGROUND

Data transfer rate over a data communication channel (e.g., bus or backplane communication link) is limited by a number of factors including, for example, frequency dependent insertion loss, crosstalk noise, and reflection caused by impedance mismatch in media and discrete losses caused by vias, connectors, and various adapters. These impairments can reduce signal strength as well as cause inter-symbol interference (ISI) at a receiver. As such, ISI arising from channel imperfections may severely limit the transmission data rate. The ISI arises in bandwidth limited channels due to rising resistive and dielectric losses of the channel, which give rise to a long channel impulse response or frequency-dependent attenuation of the transmitted signal. Reflections caused by an impedance mismatch of the channel due to vias, connectors and branches in the channel, for example, can result in crests and troughs that are non-uniformly distributed over a large number of symbol intervals in a channel impulse response or sharp troughs in a frequency domain response. Thus, to implement electrical signaling at very high speeds (e.g., above 10 GB/s) an equalization method and system is needed to compensate for the ISI at the receiver.

A continuous-time linear equalizer (CTLE) can be employed at the receiver to boost the high frequency component around the Nyquist frequency of the signals to remove ISI. However, a continuous-time linear equalizer also amplifies noise and does not improve the SNR (Signal-to-noise ratio) of the signal. Both transmitter finite impulse response (FIR) equalization and receiver CTLE components are incapable of equalizing reflections caused by impedance mismatch and additionally can amplify the crosstalk noise.

On the other hand, a decision feedback equalizer (DFE) offers an effective ISI cancelling technique without noise amplification and minimal hardware for correcting inter-symbol interference (ISI) caused by previously transmitted symbols in the data communication channel. When utilizing a DFE, the eye-diagram or eye-opening can be used as a metric regarding performance of the DFE at the receiver. The eye-diagram measurement obtained at the receiver is a superposition of all possible realizations of the received signal as viewed within a particular signaling interval. The width of the eye opening defines the time interval over which the received signal can be sampled without imposition of errors such as errors caused by inter-symbol interference, while the vertical eye opening defines a noise margin for the receiver.

Generally, a DFE, in order to compensate for ISI, will adapt feedback from previously detected symbols to equalize a currently received symbol. For example, a number of previously decoded symbols may be multiplied by coefficients, or taps, to approximate ISI and then subtracted from the received symbol. However, in conventional DFE designs, the DFE feedback loop timing is not met at very high data rates, which severely limits the receiver's performance. As such, in conventional DFE designs, the DFE feedback loop delay may include: (1) a settling time of the slicer; (2) a settling time of the DFE summer amplifier; (3) a setup time of the slicer; and (3) a settling time of the storage elements like RS-latch or flip-flops. Therefore, current methods and systems for a DFE based compensation of ISI are not entirely satisfactory.

The information disclosed in this Background section is intended only to provide context for various embodiments of the disclosure described below and, therefore, this Background section may include information that is not necessarily prior art information (i.e., information that is already known to a person of ordinary skill in the art). Thus, work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

DETAIL DESCRIPTION

Various exemplary embodiments of the present disclosure are described below with reference to the accompanying figures to enable a person of ordinary skill in the art to make and use the present disclosure. As would be apparent to those of ordinary skill in the art, after reading the present disclosure, various changes or modifications to the examples described herein can be made without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and/or hierarchy of steps in the methods disclosed herein are merely exemplary approaches. Based upon design preferences, the specific order or hierarchy of steps of the disclosed methods or processes can be re-arranged while remaining within the scope of the present disclosure. Thus, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or acts in a sample order, and the present disclosure is not limited to the specific order or hierarchy presented unless expressly stated otherwise.

FIG. 1Adepicts a non-return-to-zero (NRZ)/Pulse Amplitude Modulation-2 (PAM-2) eye diagram101. A NRZ/PAM-2 signaling scheme provides for two analog voltage levels, each corresponding to a single-bit transmitted over the communication channel. Here, a digital “0” is encoded as a low state of the transmitted signal, and a digital “1” is encoded as a high state of the signal. In the NRZ/PAM-2 signaling scheme, the input signals are compared to a single threshold voltage corresponding to Vrefof a data slicer.

In another embodiment of the present disclosure, a quaternary (or four-level) pulse amplitude modulation (PAM-4) encoding scheme may be utilized for a data signal transmitted on a transmission channel. As such, PAM-4 scheme may have one of four different signal levels that each encode a particular 2-bit symbol. For example, the 2-bit sequence “00” may be encoded as a low level, the 2-bit sequence “01” may be encoded as a first higher level, the 2-bit sequence “10” is encoded as a next higher level, and the 2-bit sequence “11” is encoded as a highest level.FIG. 1Billustrates the eye diagram102of the PAM-4 encoding scheme. As can be noted fromFIGS. 1A and 1B, PAM-4 encoding, operating at the same clock rate as a NRZ/PAM-2 scheme, is capable of transmitting twice the data as the NRZ/PAM-2 scheme. PAM-4 signaling provides three slicer thresholds (e.g., Vref1, Vref2, Vref3).

FIG. 1Cillustrates the channel impulse response or a transfer function of a single input single output (SISO) discrete time linear channel modeled as 1-tap107and as a 3-tap109,111, and113linear filter. As shown inFIG. 1C, a communication channel, modeled as 1-tap linear filter107, does not introduce an ISI on its output since the input signal is simply scaled by h0. However, for example, a communication channel modeled as 3-tap linear filter that accounts for the channel impairments such as reflections due to impedance mismatch or cross-talk, may introduce an ISI on its output.

As shown inFIG. 2, a serializer/deserializer (SerDes) receiver front-end200includes a continuous time linear equalizer (CTLE)201and a decision feedback equalizer203(DFE) that is followed by a decoder205, a demultiplexer207(DMUX), which performs the serial-to-parallel conversion on the received data, and a clock and a data recovery (CDR) circuit209, in accordance with some embodiments. In some embodiments, the CDR circuit209may be a circuit configured to receive an external clock signal and recover the transmission clock from a changing edge of the received data output from the DFE203. As such, the CDR circuit209, is optimized to sample data where the vertical eye opening of an eye diagram is the largest or at the middle of the eye to ensure signal integrity. Moreover, the decoder205determines the output data having four-level (two bits) from the outputs of the DFE203, in accordance with some embodiments. In various embodiments, the serializer/deserializer (SerDes) receiver front-end200may include a self-calibration circuit202coupled to the DFE203and to an output of the DMUX207. The self-calibration circuit202may be configured to adaptively learn N-tap linear filter coefficients (h1, h2, . . . , hN) within the SerDes receiver. In other embodiments, the self-calibration circuit202may set a desired eye height with a predetermined value of Vp, before the DFE203adaptation loop is initiated. In some embodiments, self-calibration circuit202may include an eye peak detection module, a DFE adaptation loop, an automatic gain control loop configured to achieve the desired eye. In this regard, Least Mean Squares (LMS) algorithm may be utilized to achieve the convergence of the DFE filter coefficients (h1, h2, . . . , hN). The self-calibration circuit202may be implemented in digital hardware logic or, alternatively, if the processing speed is not a concern, the self-calibration circuit202may be implemented in a software.

FIG. 3illustrates an N-tap decision feedback equalizer (DFE)300, in accordance with various embodiments. In some embodiments, the DFE300can determine, from an input symbol xk received by the DFE300, an intermediate value zk, which can be expressed as:
zk=xk−Σi=1Nyk−ihi,
where yk−irepresents feedback from the previously detected input symbol xk−1, and hiare coefficients of the N-tap linear filter that models the communication channel impairments.

The DFE architecture illustrated inFIG. 3uses linear combinations of the delayed versions of the previous decision outputs ykto cancel the ISI. Moreover, since a slicer303converts its input signals to binary decision outputs yk, the linear combinations of the delayed versions of the previous decision outputs ykmay be implemented with digital flip-flops309(FF), summers301and305, and multipliers307. In various embodiments, the digital flip-flops309may be implemented as SR (“set-reset”), D (“data” or “delay”), T (“toggle”), or JK latches.

For very high data rate applications, a tight timing constraint exists in the implementation of the DFE300, as shown inFIG. 3. In one embodiment, the timing constraint for the first tap h1of the equalizer300involves a delay through the data slicer303, the flip-flop309, and the adders301and305. In this embodiment, to ensure data integrity, the delay should settle within a one bit-time period. Thus, the implementation of the DFE300structure, as shown inFIG. 3, may require a high power consumption to meet the tight timing requirement.

Referring still toFIG. 3, in some embodiments, after subtracting (via the summer301) a dot-product Σi=1Nyk−ihi, calculated based on N previously detected symbols (to approximate ISI), from xk, the slicer303compares zkto a threshold voltage Vrefand generates a binary signal (e.g., a binary logic “1” or logic “0” in the case of NRZ/PAM-2 scheme) with respect to the final output symbol yk. In a PAM-2 scheme, the slicer303may determine: if zk>Vrefthen yk=“0”/“1”; otherwise (zk<0) yk=“1”/“0”. As another example, in a PAM-4 scheme, the DFE slicer303can determine yk: if zk>Vref1, zk>Vref2, zk>Vref3then yk=“11”; if zk<Vref1, zk>Vref2, zk>Vref3then yk=“10”; if zk<Vref1, zk<Vref2, zk>Vref3then yk=“01”; otherwise (zk<Vref1, zk<Vref2, zk<Vref3) yk=“00”.

Moreover, in accordance with various embodiments of the present disclosure, the N-tap linear filter coefficients (h1, h2, . . . , hN) may be learned adaptively within the SerDes receiver. For example, in one embodiment, the self-calibration module202, embedded the SerDes receiver, may be configured to vary the N-tap (h1, h2, . . . , hN) coefficients from their initial value across a range of values, while tracking the respective CDR settling points, which determine data sampling times and further operable to select a value for the N-tap (h1, h2, . . . , hN) coefficients from the range of values that maximizes sampled signal integrity.

Referring toFIG. 4, a feedback loop, comprising a plurality of summers and multipliers operable to implement the linear combination of the delayed versions of the previous decision outputs yk, may be embedded in a slicer401of the DFE, in accordance with some embodiments. As shown inFIG. 4, the slicer401receives inputs (d1, d2, . . . , dN) and (h1, h2, . . . , hN)403in addition to a CK (clock) signal and an input symbol xkfrom the CTLE407. In some embodiments, inputs (d1, d2, . . . , dN) may be delayed versions of the previous decision outputs ykand (h1, h2, . . . , hN) may be associated with coefficients of N-tap linear filter that models the communication channel impairments.

FIG. 5Aillustrates a circuit diagram of a DFE slicer500A with a dynamic threshold voltage calibration circuitry503, in accordance with some embodiments. In some embodiments, as shown inFIG. 5A, the DFE slicer500A includes a single stage clocked comparator circuit, which utilizes metal oxide semiconductor field effect transistors (MOSFETs). In other embodiments, other transistor technologies may be utilized to implement the comparator circuitry of the DFE slicer500A, consistent with the present disclosure. Other transistor technologies may include, but are not limited to;bipolar junction transistor (BJT) technologies (e.g., npn BJTs, pnp BJTs, heterojunction BJTs), other field effect transistor (FET) technologies (e.g., junction field effect transistors (JFETs), finFETs, insulated gate FETs (IGFETs), etc), etc.

The single-stage docked comparator circuitry depicted inFIG. 5Aand used in NRZ/PAM-2 signaling schemes includes two transistor switches513, in accordance with some embodiments. In some embodiments, the transistor switches513may be P-type or N-type MOSFETs. A respective gate of each of the transistor switches513are configured to receive a clock signal CKIN. The sources of the two transistors switches513are coupled to the supply voltage Vcc. The drain of one of the transistor switch513is coupled to an output node OutN via a latch514. The drain of another transistor switch513is coupled to an output node OutP via the latch514. In some embodiments, the outputs OutP and OutN are differential outputs that are latched using the latch circuit514. In some embodiment, a transistor switch505is coupled to the source of the transistor switch513and the latch514and is further configured to receive a clock signal CKIN. In operation, a transistor switch505may short the drains of transistors508and510to the supply voltage Vcc when the clock signal CKIN is low. When the clock signal CKIN is high, the transistors502,504,508,510,511,512will amplify the difference between voltages VINP and VINN applied to the gates of transistors502and504, respectively so that the voltagesat the drains of transistors508and510will exhibit a complementary logic. Moreover, the outputs OUTP and OUTN may change, through latch514, based on the voltage levels at the drains of transistors508and510. In various embodiments, the latch circuit514may be implemented as SR (“set-reset”), D (“data” or “delay”), T (“toggle”), or JK latch.

The clocked comparator circuitry ofFIG. 5Aalso includes transistors511and512with drains coupled to Vcc. The gate of transistor511and the source of the transistor512are coupled to each other and to the output node OutP via the latch514. The gate of the transistor512and the source of transistor511are coupled to each other and to the output node OutN via the latch514. The clocked comparator circuitry further includes transistors502and504. A gate of the transistor502is coupled to an input node VInP and a gate of the transistor the504is coupled to an input node VInN. The sources of transistors502and504are coupled to each other and to a drain of a transistor501. The gate of the transistor501is configured to receive the clock signal CKIN and the source of the transistor501is coupled to ground. The drain of the transistor502is coupled to a source of a transistor508and to a dynamic threshold voltage calibration circuit503configured to control the current flowing through the transistor502. Similarly, the drain of the transistor504is coupled to a source of a transistor510and to a dynamic threshold voltage calibration circuit506configured to control the current flowing through the transistor504. The gate of the transistor508is coupled to the output node OutP via the latch514and the gate of the transistor510is coupled to the output node OutN via the latch514. The drain of the transistor508is coupled to the output node OutN via the latch514and the drain of the transistor510is coupled to the output node OutP via the latch514. In some embodiments, the transistor switches507are driven by the clock signal CKIN and are configured to enable/disable the dynamic threshold voltage calibration circuits503and506.

Referring still toFIG. 5A, the DFE slicer500A circuitry may initially be in the reset state when the clock signal CKIN is low. As such, the transistor switches513may be on, i.e. conducting, therefore, coupling Vcc to the drains of the transistors508and510, referred inFIG. 5Aas nodes OutP1and OutN1. Here, the outputs OUTP and OUTN of the latch514may keep their previous data when the drains of the transistors508and510are coupled to the supply voltage Vcc. Moreover, the transistor switches511and512may be off since their respective gate is driven with the supply voltage Vcc signal. The transistor switch501may be off since its gate is driven with the low clock signal CKIN. When the clock signal, CKIN, transitions from low to high, the switches513may then turn off, decoupling the output nodes OutN1and OutP1from the supply voltage Vcc, and the transistor501may turn on coupling the sources of transistors502and504to ground. At this point, the transistor502and/or transistor504may start conducting when the voltages VINP and/or VINN applied to the respective gates is greater than the threshold voltage of the respective transistor. if the voltage VNN is greater than the voltage VINP, the transistor504may begin to conduct before the transistor502conducts. When the transistor504begins to conduct, the transistor510may also conduct, while providing a current path between the output node OutP1and ground. As the voltage on the output node OutP1decreases from Vcc toward ground, the transistor512may turn on when the voltage at output node OutP1minus the voltage at the output node OutN1is more negative than the threshold voltage of the transistor512. Similarly, if the voltage applied to the input node VINP is greater than the voltage applied to the input node VINN, the transistor502may begin to conduct before the transistor504conducts. When the transistor502starts conducting, the transistor508may also conduct, while providing a current path between the output node OutN1and ground. As the voltage on output node OutN1decreases from Vcc toward ground, the transistor511may turn on when the voltage on output node OutN1minus the voltage on output node OutP1is more negative than the threshold voltage of transistor511. Thus, the differential voltage across the output nodes OutP and OutN may correspond to a decision of the clocked comparator depicted inFIG. 5A.

The dynamic control circuitry503that regulates the current path between the output node OutP1and OutN1and ground through the transistors508,510, and501may be enabled via the transistor switch507controlled by the clock signal MIN, as shown inFIG. 5A, in accordance with various embodiments. Unlike the paths between the output nodes OutN1and OutP1and ground via the transistors508,502and501or transistors510,504, and501, the dynamic control circuitry503provides additional current paths between the output nodes OutP1, OutN1and ground through the transistors508,510, and501. As such, an exemplary advantage of the dynamic control circuitry503is that it effectively controls an equivalent dynamic offset voltage shift of threshold voltage Vref, which results in reduced ISI. Another exemplary advantage of the dynamic control circuitry503is that it does not increase the power consumption of the DFE slicer500A. Moreover, the dynamic control circuitry503is further configured to regulate the current flow between at least one output node OutP and/or OutN, and ground, in response to CKIN and based on N-tap linear filter coefficients (h1, h2, . . . , hN) and delayed versions of the previous outputs of the DFE slicer500A (d1, d2, . . . , dN). In some embodiments, the N-tap linear filter coefficients (h1, h2, . . . , hN) that regulate the current flow in the dynamic control circuitry may be learned adaptively within the SerDes receiver.

FIG. 5Billustrates a respective example of the DFE slicer500A with dynamic threshold voltage calibration circuitry515and516implemented as a plurality of current sources I1. . . IN, in accordance with some embodiments. As such, the DFE slicer500B with the dynamic threshold voltage calibration circuitry515and516is equivalent to an N-tap linear filter that models the communication channel impairments. In other embodiments, the dynamic threshold voltage calibration circuitry515and516are further configured to regulate the plurality of current sources I1. . . INbased on the N-tap linear filter coefficients (h1, h2, . . . , hN) and delayed versions of the previous outputs of the DFE slicer500B (d1, d2, . . . , dN). In some embodiments, the plurality of current sources I1. . . INof the dynamic threshold voltage calibration circuitry515and516may be learned adaptively within the SerDes receiver to reduce the ISI. Other elements of the circuitry shown inFIG. 5Bare similar to corresponding elements shown inFIG. 5A. Thus, to avoid redundancy, a description of such elements is not repeated here.

FIG. 6illustrates a respective example of the DFE slicer500A with the dynamic control circuitry implemented as a single current source I1601, in accordance with some embodiments. As such,FIG. 6shows a single ended comparator circuitry of the DFE slicer600. in some embodiments, the current source I1601is associated with a dynamic offset voltage shift±α603. In operation, when the input voltage VIN applied to a gate of a transistor504is equal to the voltage Vrefapplied to a gate of a transistor502, the differential output of the DFE slicer600may be logical “0” and when VIN is larger than Vref+α (i.e. I1+Iref<Iin, where Iinis the current flow through the transistor504and Irefis the current flow through the transistor502), the differential output of the DFE slicer600may be logical “1”. In other embodiments, the current source I1601may be learned adaptively within the SerDes receiver to reduce the ISI. In these embodiments, the current source I1601may be dynamically controlled based on the previous output of the DFE slicer600. In some embodiments, an exemplary advantage of the DFE slicer600is that it provides a dynamic reference voltage Vrefthat changes based on previous outputs of the DFE slicer600. Yet another advantage of the DFE slicer600is that it does not increase the power consumptions of the DFE slicer600compared to traditional DFE slicer architectures. Other elements of the circuitry shown inFIG. 6are similar to corresponding elements shown inFIG. 5A. Thus, to avoid redundancy, a description of such elements is not repeated here.

Turning now toFIG. 7A, a double ended comparator circuit of a DFE slicer700A, with dynamic threshold voltage calibration circuitry is shown, in accordance with some embodiments of the present disclosure. In some embodiments, dynamic threshold voltage calibration circuitry701and707are each implemented as a plurality of current sources I1. . . IN. As such, the DFE slicer700A with the dynamic threshold voltage calibration circuitry701and707is equivalent to an N-tap linear filter that models the communication channel impairments. In other embodiments, the dynamic threshold voltage calibration circuitry701and707are further configured to regulate the plurality of current sources I1. . . INbased on the N-tap linear filter coefficients (h1, h2, . . . , hN) and delayed versions of the previous outputs of the DFE slicer700A (d1, d2, . . . , dN). In some embodiments, the plurality of current sources I1. . . INmay be regulated with switches702. In other embodiments, the plurality of current sources I1. . . INmay be learned adaptively using any learning method with the goal of reducing ISI.

In one embodiment, the plurality of current sources I1. . . INin the dynamic threshold voltage calibration circuitry701and707are associated with dynamic offset voltage shifts±α1. . . ±αNthat are related to the N-tap linear filter coefficients (h1, h2, . . . , hN). In operation, when the input voltage INP applied to a gate of a transistor704is greater than the voltage VREFP±α1. . .±αN, where VREFPis applied to a gate of a transistor703, and the input voltage INN applied to a gate of a transistor706is less than the voltage VREFN±α1. . .±αN, where VREFNis applied to a gate of a transistor705, the differential output of the DFE slicer700A may be logical “1” and when the input voltage INP is less than the voltage VREFPand the input voltage INN is greater than the voltage VREFN, the differential output of the DFE slicer700A may be logical “0”. In particular, when the input voltage INP is greater than the voltage VREFP±α1. . .±αN, I1. . .+IN+Irefp<Iinp, where Iinpis the current flow through the transistor704and Irefpis the current flow through the transistor703. Similarly, when the input voltage INN is less than the voltage VREFN±α1. . .±αN, I1. . .+IN+Irefn>Iinn, where Iinnis the flow current through the transistor706and Irefnis the current flow through the transistor705.

FIG. 7Bshows a block diagram of a self-calibration module700B for determining a voltage reference or threshold signals needed for a DFE slicer709, consistent with several embodiments of the present disclosure. In some embodiments, in order to improve timing margins of the receiver front-end200, a multi-phased clock may be used. As shown inFIG. 7B, the self-calibration module700B includes a digital-to-analog converter (DAC)713coupled to a low pass filter711and operable to select voltage reference or threshold signals (VREFP/VREFN) for the DFE709slicer. In various embodiments, the low pass filter711may be implemented in the DAC713. In some embodiments, the self-calibration module700B adaptively computes the threshold signals VREFP/VREFN based on previous outputs of the DFE709. In one embodiments of the inventions, the threshold signals are determined using the Least Mean Square (LMS) algorithm, which approximates the steepest descent algorithm. The LMS algorithm may include an adaptation coefficient μ, which determines the pace of the convergence. Of course, in other embodiments, the self-calibration module700B may sweep the threshold signals VREFP/VREFN to determine the optimal threshold based on acceptable bit error rate results. As such, VREFP may be defined as VREFP=VCOM+β and VREFN may be defined as VREFN=VCOM+β, where VCOM is a some common voltage and β is a parameter that is swept between a predetermined range of values βϵ[β,β].

FIG. 7Cillustrates NRZ/PAM2 signaling diagrams. As such, in the signaling diagram715, the NRZ/PAM2 data (e.g., “1101”) is received at a DFE slicer with its threshold voltage level set to zero (e.g., VREFP/VREFN=0). The signaling diagram715also shows that the threshold voltage level may be used to determine whether a received voltage signal is above (including equal to) or below the threshold voltage level. For example, a DFE slicer, without dynamic offset voltage calibration, may determine that the third received data sample is above the threshold VREFP and decide that a logic “1” was sent, while a logic “0” was originally sent, therefore, resulting in ISI, as shown inFIG. 7C. On the other hand, the signaling diagram717shows that the threshold voltage (e.g., VREFP/VREFN) levels may be dynamically offset, which provides more margin in determining whether a received voltage signal is above (including equal to) or below the offset threshold voltage levels. For example, a DFE slicer700A, with dynamic offset voltage calibration, may provide an increased noise margin and enhanced eye opening, as shown inFIG. 7C. Furthermore, even though the above description is generally related to an NRZ/PAM-2 mode of communication, it is applicable to PAM-4 or other types of modulation.

FIG. 8illustrates a self-calibration module803for determining voltage reference or threshold signals needed for the DFE slicers embedded in PAM-4 decoding receivers, in accordance with some embodiments. In accordance with various embodiments, in order to improve timing margins of the receiver front-end200, a multi-phased clock may be used, as shown inFIG. 8. In some embodiments, each self-calibration module803may provide time-varying discrete or continuous voltage reference or threshold signals in order to produce a larger eye diagram opening, which can facilitate faster data rates and reduced bit-error rate (BER) in the SerDes receivers. In some embodiments, each self-calibration module803includes three DFE embedded slicers801operable to compare data symbols with thresholds Vref1, Vref2, Vref3, respectively, to determine the state of data symbols and subsequently their corresponding bit mapping. In various embodiments, each self-calibration module803may further include a decoder805configured to decode data from a series of binary data received from the DFEs801. In this regard, the decoder805, may determine the most likely sequence of state transitions for the received series of binary data, wherein each such state represents a symbol instant. The decoder803may also be implemented as a Maximum A posteriori Probability (MAP) Decoder or a Maximum Likelihood Sequence Estimation Viterbi (MLSE) Decoder, in accordance with various embodiments of the present disclosure.

In addition, a self-calibration module803may include a low pass filter (LPF)807coupled to an output of the decoder805. An output of the LFP807is received by a digital to analog converter (DAC)809, which provides analog voltage reference or threshold levels to the DFE slicer801. In some embodiments, the voltage reference or threshold levels needed for the DFE slicers801provided by the DAC809are learned autonomously by various search algorithms, descent methods, heuristics or other control loops, with various learning goals, depending on implementation (e.g., Zero-Forcing of the ISI, Maximization of Signal to Noise Ratio, Minimum Mean Square Error (MMSE), etc.). Some self-calibration modules803of various embodiments may have a mixture of these learning methods. Furthermore, the autonomous learning may occur during a normal operating mode and/or a calibration mode. Thus, the adaptation may be performed once, continuously (online), and/or as needed.

As shown inFIG. 9A, the eye diagram measuring circuit900for a DFE with a feedback loop embedded in a slicer includes a signal source901, a communication channel903, a device under test905comprising the DFE with a feedback loop embedded in a slicer, and a Built-In-Self-Test (BIST) circuit907operable to perform eye monitoring on the equalized data signal. In some embodiments, the signal source901may include a pseudo random binary sequence (PRBS) data generator, wherein the PRBS data generator is further configured to include mode controls for selecting a desired PRBS sequence (e.g. PRBS7, PRBS23, etc.). As such, the desired PRBS sequence generated by the signal source901may have a desired frequency content. Moreover, the communication channel903may exhibit various frequency responses as shown inFIG. 9B. In this regard,FIG. 9Billustrates a magnitude909of the communication channel transfer function for a range of frequencies (e.g., 0 to 56 GHz). Furthermore, the quality of the measured eye diagram obtained from the data communication channel903with 7 dB loss, for example, and equalized by the DFE905is depicted inFIG. 9C. In this regard, a large eye diagram opening911is indicative of the quality of the operation of the DFE circuitry and the CDR circuitry associated with the DFE circuitry.

FIG. 10illustrates a flow diagram of a method for reducing an inter-symbol interference (ISI), in accordance with some embodiments. At operation1001, the DFE slicer500A may receive an input signal from the communication channel903. Moreover, at operation1001, the DFE slicer500A may also receive a delayed feedback signals from a plurality of delay latches, such as SR (“set-reset”), D (“data” or “delay”), T (“toggle”), or JK latches, that are coupled to the DFE slicer500A. In some embodiments, the delayed feedback signals each corresponds to a bit history of the received input signal that is decided by the DFE slicer500A.

At operation1003, a current flow is regulated between output nodes of the DFE slicer500A and ground based on the received delayed feedback signals and the communication channel's impulse response coefficients. In some embodiments, the current flow is regulated by controlling an off/on state of a plurality of current sources. In further embodiments, the off/on state of the plurality of current sources may be controlled by complementary metal-oxide-semiconductor (CMOS) switches.

At operation1005, the DFE slicer500A determines a logical state of the received input signal. More specifically, at operation1005, the DFE slicer500A may determine the logical state corresponding to the received input. In some embodiments, the logical state may correspond to one of four signal levels used in pulse amplitude modulation (PAM-4) encoding scheme.

In some embodiments, the present invention provides a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel. In further embodiments, the dynamic threshold voltage calibration circuit is enabled by a transistor switch controlled by a clock signal and the plurality of delay latches are implemented with digital flip-flops. In some embodiments, the dynamic threshold voltage calibration circuit comprises a plurality of current sources and a plurality of transistor switches configured to control an off/on state of the plurality of current sources.

In further embodiments, a receiver includes: a decision feedback equalizer (DFE) comprising a slicer circuit, wherein, the slicer circuit regulates a current flow between output nodes of the slicer circuit and ground based on a time-varying threshold voltage; and a self-calibration circuit coupled to the DFE and configured to adaptively adjust the time-varying threshold voltage of the slicer circuit. In some embodiments, the receiver further includes a decoder coupled to the DFE and configured to determine the most likely sequence of state transitions for a series of binary data received from the DFE. In further embodiments, the receiver further includes a demultiplexer (DMUX) coupled to the decoder and configured to perform a serial-to-parallel conversion on a received input data. In some embodiments, the self-calibration circuit is further configured to determine the time-varying threshold voltage using an approximate gradient descent algorithm, and further configured to sweep the time-varying threshold voltage to determine an optimal threshold voltage based on resulting bit error rates.

In alternative embodiments, a method includes: receiving an input signal from a communication channel and delayed feedback signals from a plurality of delay latches coupled to a slicer circuit; regulating a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signals and the communication channel's impulse response coefficients; and determining a logical state of the received input signal. In further embodiments, the step of regulating the current flow includes controlling an off/on state of a plurality of current sources and/or adaptively determining the communication channel's impulse response coefficients. In some embodiments, the method further includes determining the communication channel's impulse response coefficients by an approximate gradient descent algorithm.

A person of ordinary skill in the art would further appreciate that any of the various illustrative logical blocks, modules, processors, means, circuits, methods and functions described in connection with the aspects disclosed herein can be implemented by electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two), firmware, various forms of program or design code incorporating instructions (which can be referred to herein, for convenience, as “software” or a “software module), or any combination of these techniques.

To clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software, or a combination of these techniques, depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in various ways for each particular application, but such implementation decisions do not cause a departure from the scope of the present disclosure. In accordance with various embodiments, a processor, device, component, circuit, structure, machine, module, etc. can be configured to perform one or more of the functions described herein. The term “configured to” or “configured for” as used herein with respect to a specified operation or function refers to a processor, device, component, circuit, structure, machine, module, signal, etc. that is physically constructed, programmed, arranged and/or formatted to perform the specified operation or function.

Furthermore, a person of ordinary skill in the art would understand that various illustrative logical blocks, modules, devices, components and circuits described herein can be implemented within or performed by an integrated circuit (IC) that can include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, or any combination thereof. The logical blocks, modules, and circuits can further include antennas and/or transceivers to communicate with various components within the network or within the device. A processor programmed to perform the functions herein will become a specially programmed, or special-purpose processor, and can be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other suitable configuration to perform the functions described herein.