DIGITAL CANCELLATION OF CIM3 DISTORTION FOR DIGITAL TRANSMITTERS

An apparatus includes a first circuit to receive a first input data, a second input data and coefficients, generate a first distortion term and a second distortion term based, respectively on the first input data and the coefficients and the second input data and the coefficients, and change a polarity of the first distortion term and the second distortion term. A first subtraction circuit subtracts the first distortion term from the first input data and generates first difference data, and a second subtraction circuit subtracts the second distortion term from the second input data and generates second difference data. A transmit data-path generates a RF output. The first difference data and the second difference data compensate, based on the polarity changes of the first distortion term and the second distortion term, respectively, one or more impairments of the RF output.

TECHNICAL FIELD

The present description relates generally to data communications including, for example, a digital cancellation of third counter intermodulation (CIM3) distortion for digital transmitters.

BACKGROUND

Radio frequency (RF) digital transmitters and power amplifiers may include, among other blocks, digital-to-analog converter (DAC) circuits. In a conventional RF-DAC circuit, two separate DAC circuits are used for in-phase (I) and quadrature (Q) signals. The I-DAC circuit receives a digital I-input data and mixes the I-input data with a corresponding clock signal (Iclk) to generate an analog I-output signal. Similarly, the Q-DAC circuit, receives a digital Q-input data and mixes the digital Q-input data with a corresponding clock signal (Qclk) to generate an analog Q-output signal, which is combined with the analog I-output signal to form the analog I/Q output signal for transmission.

In complex signal digital transmitters, individual cells combine switched currents, for example, by using a passive attenuator (PAD) circuit. The output current is a hard-switching, square-wave like waveform. This current, similar to any square wave, has strong odd-order harmonics including third order and fifth order harmonics. In the presence of a third order nonlinearity (e.g., in a PAD), the signal around three times the local oscillator (LO) frequency (3ωLO) mixes with the wanted signal (ωss) and generates an in-band third counter intermodulation (CIM3) distortion at a frequency of ωLO-3ωss, which needs to be canceled or at least reduced.

DETAILED DESCRIPTION

According to some aspects, the subject technology is directed to a digital cancellation of CIM3 distortion for digital transmitters. The digital transmitter of the subject technology includes a first circuit (a distortion-generation circuit) configured to receive a first input data and a second input data and generate a first modified input data and a second modified input data. A first DAC circuit mixes the first modified input data with a first clock signal and generate a first output signal. A second DAC circuit mixes the second modified input data with a second clock signal and generate a second output signal. The first modified input data and the second modified input data are generated based on the first input data, the second input data and cancellation coefficients. In some embodiments, the cancellation coefficients are adjustable cancellation coefficients and are adjusted to reduce a power of a CIM3 component in the first output signal and the second output signals.

In some embodiments, the cancellation coefficients are determined experimentally through a calibration process, by generating a single-sideband tone and running it through the digital transmitter or the RF-DAC circuits. In some embodiments, a single-sideband tone is a signal generated by a SSB modulator, which removes a sideband of the signal in frequency domain. The cancellation coefficients are then swept while monitoring the power of the CIM3 component at the output of the digital transmitter or the RF-DAC until acceptable values are reached. The acceptable cancellation coefficients would result in a minimum determined value of the monitored power of the CIM3 component.

FIGS.1A and1Bare a block diagram illustrating an example of a transmitter100within which some aspects of the subject technology are implemented and a corresponding chart. In some embodiments, the transmitter100is a digital transmitter. As shown, the transmitter100includes, but is not limited to, a cancellation circuit110, a first digital-to-analog converter (DAC) circuit160, a second DAC circuit170, a combiner circuit180and a load182. In some embodiments, the cancellation circuit is a processor that receives a first digital input data102and a second digital input data104and generate a first processed input data and a second processed input data. In some embodiments, the cancellation circuit110includes, but is not limited to, a CMI3 distortion-generation circuit120, a digital transmit (DTX) data-path circuit150and subtraction circuits140and142. The cancellation circuit110receives a first digital input data102(Idata[k]) and a second digital input data104(Qdata[k]) and generates a first modified input data152(Iout[n]) and a second modified input data154(Qout[n]), respectively. The first digital input data102and the first modified input data152are in-phase (I) components, and the second digital input data104and the second modified input data154are quadrature (Q) components.

The first DAC circuit160(also referred to as a first RF circuit or the first mixer circuit) mixes the first modified input data152with a first clock signal (Iclk) to generate a first output signal162. In some embodiments, the first DAC circuit160is an I-DAC circuit. The second DAC circuit170(also referred to as a second RF circuit or a second circuit) mixes the second modified input data154with a second clock signal (Qclk) to generate a second output signal172. In some embodiments, the second DAC circuit170is a Q-DAC circuit. The first output signal162and the second output signal172are combined by the combiner circuit180(e.g., a transformer) to generate an RF output signal, which is delivered to a load182(e.g., a resistor).

In some embodiments, the CMI3 distortion-generation circuit120generates a first distortion term122and a second distortion term124based on the first digital input data102and the second digital input data104, respectively, as well as based on cancellation coefficients α, ϕ, β and θ. In some embodiments, the distortion terms include CMI3 distortions generated by the CMI3 distortion-generation circuit120. In some embodiments, the cancellation coefficients α, ϕ, β and θ are adjustable cancellation coefficients. In some embodiments, the cancellation coefficients α, ϕ, β and θ are determined through a calibration process, discussed below. In some embodiments, the calibration process includes generating a single-sideband tone and running it through the transmitter100or the first DAC circuit160and the second DAC circuit170. Using the cancellation coefficients α, ϕ, β and θ the CMI3 distortion-generation circuit120produces the first distortion term122and the second distortion term124. In some embodiments, the first distortion term122and the second distortion term124are scaled to be equal in magnitudes and opposite in polarity to compensate the one or more impairments (e.g., the CIM component) and the scaled first distortion term and the scaled second distortion term are subtracted from the first digital input data102and the second digital input data104, respectively, by a subtraction circuit140and a subtraction circuit142. The subtraction circuits140and142produce correction data including a first difference data128(Icorr[k]) and a second difference data130(Qcorr[k]), respectively. In some embodiments, the first difference data128is the difference between the first digital input data102and the first distortion term122. In some embodiments, the second difference data130is the difference between the second digital input data104and the second distortion term124. The first difference data128(Icorr[k]) and the second difference data130(Qcorr[k]) have zero or reduced-power CIM3 components and are further processed by the DTX data-path circuit150. In some embodiments, the DTX data-path circuit150is configured to up-sample, filter and condition the first difference data128and the second difference data130to subsequently provide the first modified input data152and the second modified input data154for delivering to the first DAC circuit160and the second DAC circuit170. The up-sampling process is the process of increasing the sampling rate of a signal, which in the case of an image, enhances the resolution of the image. The sampling rate of the signal is increased by an up-sampling factor, which can be an integer or a rational fraction greater than unity. The filtering is a process that selectively reduces or removes unwanted features (e.g., frequency components) of the signal, for example the higher frequency images generated by the up-sampling. In some embodiments, the first difference data128and the second difference data130are unsampled and filtered to increase the sampling rate and remove unwanted frequency components. The conditioning of a signal is a signal processing operation that prepares the signal in term of, for example, amplitude, phase or frequency spectrum based on a condition of a next processing circuit.

The chart100B shows plots190,192and194. The plot190depicts a desired (e.g., acceptable) signal193along with a CIM3 distortion195caused by the nonlinearity of the transmitter100. The plot192depicts a CIM3 distortion197generated by CMI3 distortion-generation circuit120, which is scaled to be equal in magnitude and opposite in polarity to cancel the CIM3 distortion195. In some embodiments, a CIM3 distortion197is opposite in polarity with respect to the CIM3 distortion195, which implies that positive (negative) magnitudes of the CIM3 distortion197are the same as the negative (positive) magnitudes of the CIM3 distortion195. The plot194shows the desired signal193signal along with a cancelled CIM3 distortion199, which a significantly reduced with respect to the CIM3 distortion195.FIGS.2A,2B and2Care charts200A,200B and200C illustrating an example of a calibration procedure for determining CIM3 cancellation coefficient, according to aspects of the subject technology. The chart200A show equations (Eq.) 1, 2, 3 and 4. In Eq. 1, the correction voltage term Vcorris calculated by subtracting CIM3 voltage (VCIM3) from the data voltage (Vdata). In Eq. 2, Vcorris defined as a complex value based on the first difference data128and the second difference data130ofFIG.1A, and in Eq. 3, Vdatais defined as a complex value based on the first digital input data102and the second digital input data104ofFIG.1A. Finally, in Eq. 4, the CIM3 correction voltage (VCIM3) is expressed in terms of the cancellation coefficients α, ϕ, β and θ and the first and second digital input data. The CIM3 distortion is minimized at the output when the optimal values of the cancellation coefficients α, φ, β, and θ are used. The optimal values of the cancellation coefficients α, φ, β, and θ are found through a calibration procedure, as discussed below.

The calibration procedure is an experimental procedure in which a single-band tone is generated and applied to inputs of the transmitter100ofFIG.1A. During the experiment, the values of the cancellation coefficients α, φ, β, and θ are swept while monitoring the CIM3 component.

The chart200B shows the amplitudes of the single-band tone and the CIM3 component with a variable X that represents the difference between the powers or amplitudes of the single-band tone and the CIM3 component.

The chart200C shows a plot210of variation of the variable X versus values of any of the cancellation coefficients α, φ, β, and θ that are swept. The highest point in the plot210corresponds to a desired (e.g., acceptable) value of the respective parameter, as it corresponds to a respective lowest value (e.g., minimum determined value) of the CIM3 component. By repeating the experiment for different cancellation coefficients α, φ, β, and θ, respective desired (e.g., acceptable) values for all cancellation coefficients are obtained, which can be used in Eq. 4 of the chart200A to determine the VCIM3that corresponds to the lowest value of the CIM3 component.

FIG.3is a flow diagram illustrating an example of a process300for a CIM3 cancellation, according to aspects of the subject technology. The process300includes receiving, by a cancellation circuit (e.g., cancellation circuit110ofFIG.1), a first input data (e.g., first digital input data102ofFIG.1) and a second input data (e.g., second digital input data104ofFIG.1) and generating a first modified input data (e.g., first modified input data152ofFIG.1) and a second modified input data (e.g., second modified input data154ofFIG.1) (310). The process300also includes mixing, by a first digital-to-analog converter (DAC) circuit (e.g., first DAC circuit160ofFIG.1), the first modified input data with a first clock signal (e.g., IclkofFIG.1), to generate a first output signal (e.g., first output signal162ofFIG.1) (320). The process300further includes mixing, by a second DAC circuit (e.g., second DAC170ofFIG.1), the second modified input data with a second clock signal (e.g., QclkofFIG.1) and generate a second output signa (e.g., second output signal172ofFIG.1) (330). The process300further includes reducing a power of a CIM3 component in the first output signal and the second output signals by adjusting cancellation coefficients (e.g., α and ϕ ofFIG.1), based on which the first modified input data and the second modified input data are generated (340).

FIG.4illustrates an example of a wireless communication device400within which some aspects of the subject technology are implemented. In one or more implementations, the wireless communication device400can be a tablet, a smartphone, a smartwatch, or other electronic device that includes a pressure sensor. The wireless communication device400may comprise an RF antenna410, a duplexer412, a receiver420, a transmitter430, a baseband processing module440, a memory450, a processor460, and a local oscillator generator (LOGEN)470. In various aspects of the subject technology, one or more of the circuits represented inFIG.4may be integrated on one or more semiconductor substrates. For example, circuits420-470may be realized in a single chip, a single system on a chip, or in a multichip chipset.

The receiver420may comprise suitable logic circuitry and/or code that may be operable to receive and process signals from the RF antenna410. The receiver420may, for example, be operable to amplify and/or down convert received wireless signals. In various aspects of the subject technology, the receiver420may be operable to cancel noise in received signals and may be linear over a wide range of frequencies. In this manner, the receiver420may be suitable for receiving signals in accordance with a variety of wireless standards such as Wi-Fi, WiMAX, BT, and various cellular standards. In various aspects of the subject technology, the receiver420may not use any sawtooth acoustic wave filters, and few or no off-chip discrete components such as large capacitors and inductors.

The transmitter430may comprise suitable logic circuitry and/or code that may be operable to process and transmit signals from the RF antenna410. The transmitter430may, for example, be operable to upconvert baseband signals to RF signals and amplify RF signals. In various aspects of the subject technology, the transmitter430may be operable to upconvert and amplify baseband signals processed in accordance with a variety of wireless standards. Examples of such standards may include Wi-Fi, WiMAX, BT, and various cellular standards. In various aspects of the subject technology, the transmitter430may be operable to provide signals for further amplification by one or more power amplifiers. In some implementations, the transmitter430may be implemented as a digital transmitter and include the cancellation circuit110ofFIG.1and implements the process ofFIG.4to reduce a power of the CIM3 component.

The duplexer412may provide isolation in the transmit band to avoid saturation of the receiver420or damaging parts of the receiver420, and to relax one or more design requirements of the receiver420. Furthermore, the duplexer412may attenuate the noise in the receive band. The duplexer412may be operable in multiple frequency bands of various wireless standards.

The baseband processing module440may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to perform the processing of baseband signals. The baseband processing module440may, for example, analyze received signals, and generate control, and/or feedback signals for configuring various components of the wireless communication device400, such as the receiver420. The baseband processing module440may be operable to encode, decode, transcode, modulate, demodulate, encrypt, decrypt, scramble, descramble, and/or otherwise process data in accordance with one or more wireless standards.

The processor460may comprise suitable logic, circuitry, and/or code that may enable processing data and/or controlling operations of the wireless communication device400. In this regard, the processor460may be enabled to provide control signals to various other portions of the wireless communication device400. The processor460may also control the transfer of data between various portions of the wireless communication device400. Additionally, the processor460may enable implementation of an OS or otherwise execute code to manage operations of the wireless communication device400. In one or more implementations, the processor460may be interfaced with any transducer modules via standard host interface technologies such as an inter-integrated circuit (I2C), a serial interface protocol (SPI), a peripheral component interconnect express (PCIE), a universal asynchronous receiver-transmitter (UART), and/or other interface technologies, depending on the data rate needed to sample and pipe from the transducers module to the processor460.

The memory450may comprise suitable logic, circuitry, and/or code that may enable storage of various types of information such as received data, generated data, code, and/or configuration information. The memory450may comprise, for example, RAM, ROM, flash, and/or magnetic storage. In various aspects of the subject technology, information stored in the memory450may be utilized for configuring the receiver420and/or the baseband processing module440.

The LOGEN470may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to generate one or more oscillating signals of one or more frequencies. The LOGEN470may be operable to generate digital and/or analog signals. In this manner, the LOGEN470may be operable to generate one or more clock signals, and/or sinusoidal signals. Characteristics of the oscillating signals such as the frequency and duty cycle, may be determined based on one or more control signals from, for example, the processor460and/or the baseband processing module440.

In operation, the processor460may configure the various components of the wireless communication device400based on a wireless standard according to which it is designed to receive signals. Wireless signals may be received via the RF antenna410, amplified, and down converted by the receiver420. The baseband processing module440may perform noise estimation and/or noise cancellation, decoding, and/or demodulation of the baseband signals. In this manner, information in the received signal may be recovered and utilized appropriately. For example, the information may be audio and/or video to be presented to a user of the wireless communication device400, data to be stored to the memory450, and/or information affecting, and/or enabling operation of the wireless communication device400. The baseband processing module440may modulate, encode, and perform other processing on audio, video, and/or control signals to be transmitted by the transmitter430in accordance with various wireless standards.

In some embodiments, a digital transmitter of the subject technology includes a cancellation circuit to receive a first input data and a second input data and generate a first modified input data and a second modified input data. A first digital-to-analog converter (DAC) circuit mixes the first modified input data with a first clock signal and generate a first output signal. A second DAC circuit mixes the second modified input data with a second clock signal and generate a second output signal. The first modified input data and the second modified input data are generated based on the first input data, the second input data and cancellation coefficients that are adjustable to reduce a power of a third counter intermodulation (CIM3) component in the first output signal and the second output signals.

In some embodiments, the cancellation circuit includes a CIM3 distortion generation circuit to generate a first distortion term and a second distortion term based on the cancellation coefficients.

In some embodiments, the cancellation circuit further includes subtraction circuits to subtract the first distortion term and a second distortion term from the first input data and the second input data, respectively, and to generate a first difference data and a second difference data.

In some embodiments, the cancellation circuit further includes a digital second circuit configured to further process the first difference data and the second difference data.

In some embodiments, the digital second circuit further processes the first difference data and the second difference data by using the first clock signal and the second clock signal.

In some embodiments, the digital second circuit up-samples, filters and conditions the first difference data and the second difference data and provides the first modified input data and the second modified input data.

In some embodiments, the cancellation coefficient is produced by an experimental calibration process.

In some embodiments, the experimental calibration process is implemented by a calibration circuit configured to apply a single-sideband tone to input ports of the cancellation circuit and determine desired values of the cancellation coefficients.

In some embodiments, the calibration circuit monitors a power of the CIM3 component in the first output signal and the second output signal while values of the cancellation coefficients are adjusted. In some embodiments, the values of the cancellation coefficients are adjusted based on a value of the monitored power of the CIM3 component.

In some embodiments, the values of the cancellation coefficients are adjusted until the desired values of the cancellation coefficient is reached, wherein the desired values of the cancellation coefficient are values that result in a lowest value of the monitored power of the CIM3 component is achieved. The lowest value of the power of the CIM3 component is not a predefined or known value and is observed while experimentally monitoring the power of the CIM3 component.

In some embodiments, an integrated circuit of the subject technology includes a processor to process a first input data and a second input data and generate a first processed input data and a second processed input data. The integrated circuit also include a first circuit to mix the first processed input data with a first clock signal and generate a first output signal, and a second circuit to mix the second processed input data with a second clock signal and generate a second output signal. The processor includes a distortion generation circuit and a data-path circuit to process the first input data and the second input data using cancellation coefficients, and the cancellation coefficients are experimentally adjustable to reduce a power of a CIM3 component in the first output signal and the second output signals.

In some embodiments, a communication device of the subject technology includes a processor to process a first input data and a second input data and generate a first processed input data and a second processed input data. A first RF circuit receives the first processed input data and generate a first output signal, and a second RF circuit receives the second processed input data and generates a second output signal. The processor can process the first input data and the second input data using adjustable cancellation coefficients. Using the first processed input data and the second processed input data, respectively, by the first RF circuit and the second RF circuit alters a CIM3 component in the first output signal and the second output signals. The alteration may include causing a power reduction of the CIM3 component.