Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

TECHNICAL FIELD

The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices, memory devices, and electronic systems.

BACKGROUND

A continuing goal of the microelectronics industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes memory strings vertically extending through one or more stack structures individually including tiers of conductive structures and insulative structures. Each memory string may include at least one select device coupled in series to a serial combination of vertically stacked memory cells. Such a configuration permits a greater number of switching devices (e.g., transistors) to be located in a unit of die area (i.e., length and width of active surface consumed) by building the array upwards (e.g., vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.

Vertical memory array architectures generally include electrical connections between the conductive structures of the tiers of the stack structure of the memory device and conductive routing structures so that the memory cells of the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such an electrical connection includes forming so-called “staircase” (or “stair step”) structures at edges (e.g., horizontal ends) of the tiers of the stack structure of the memory device. Such staircase structures include individual “steps” defining contact regions of the conductive structures, upon which conductive contact structures can be positioned to provide electrical access to the conductive structures.

Unfortunately, as feature packing densities have increased and margins for formation errors have decreased, conventional methods of forming memory devices (e.g., 3D NAND Flash memory devices) have resulted in undesirable damage that can diminish desired memory device performance, reliability, and durability. For example, conventional methods of forming the stack structure of a memory device (e.g., 3D NAND Flash memory device) using so called “replacement gate” or “gate last” processing, wherein sacrificial structures of a preliminary stack structure are at least partially replaced with the conductive structures, can result in undesirable deformations (e.g., tier bending, tier warping, tier bowing) and/or undesirable damage (e.g., tier cracking, tier collapse) proximate the staircase structures within the preliminary stack structure. Such deformations and/or damage can result in undesirable defects, undesirable reliability, and/or undesirable durability in the memory device including the stack structure formed through such conventional methods.

DETAILED DESCRIPTION

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device, such as 3D NAND device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessary limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional DRAM; conventional non-volatile memory, such as conventional NAND memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., regions, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, “insulative material” means and includes electrically insulative material, such as one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x”, “y”, and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x”, “y”, and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “homogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term “heterogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) vary throughout different portions of the feature. If a feature is heterogeneous, amounts of one or more elements included in the feature may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the feature. The feature may, for example, be formed of and include a stack of at least two different materials.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

FIG. 1AthroughFIG. 5Bare simplified partial cross-sectional (FIGS. 1A, 2A, 3A, 4A, and 5A) and simplified partial top-down (FIGS. 1B, 2B, 3B, 4B, and 5B) views illustrating embodiments of a method of forming a microelectronic device structure (e.g., a memory structure) for a microelectronic device (e.g., a memory device, such as a 3D NAND Flash memory device). With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used for forming various devices. In other words, the methods of the disclosure may be used whenever it is desired to form a microelectronic device.

Referring collectively toFIG. 1AandFIG. 1B(which depicts a simplified partial top-down view of the microelectronic device structure100at the processing stage shown inFIG. 1A), a microelectronic device structure100may be formed to include a base structure108, a source tier109over the base structure108, an isolation material112over the source tier109, and a sacrificial material114over the isolation material112. The foregoing features, as well as additional features (e.g., additional materials, additional structures, additional devices), of the microelectronic device structure100at the processing stage depicted inFIG. 1AandFIG. 1B, are described in further detail below. The view depicted inFIG. 1Ais a simplified partial cross-sectional view of the microelectronic device structure100about the dashed line Ai-Ai illustrated inFIG. 1B.

As shown inFIG. 1AandFIG. 1B, the microelectronic device structure100may be divided into multiple regions in a first horizontal direction (e.g., the X-direction). For example, in the X-direction depicted inFIG. 1AandFIG. 1B, the microelectronic device structure100may include at least one memory array region102, at least one staircase region104(e.g., at least one access line contact region), and at least one intervening region106horizontally interposed (e.g., in the X-direction) between the memory array region102and the staircase region104. Additional features (e.g., additional structures, additional materials, additional devices) facilitating desirable functions and characteristic of the microelectronic device structure may subsequently be formed in the different horizontal regions (e.g., the memory array region102, the staircase region104, and the intervening region106) of the microelectronic device structures100, as described in further detail below.

As shown inFIG. 1B, the microelectronic device structure100may be further divided into additional regions in a second horizontal direction (e.g., the Y-direction) orthogonal to the first horizontal direction (e.g., the X-direction). For example, in the Y-direction depicted inFIG. 1B, the microelectronic device structure100may include block regions116, and slot regions118horizontally surrounding (e.g., in the Y-direction and in the X-direction) the block regions116. The slot regions118may be horizontally interposed between horizontally neighboring block regions116. The block regions116and the slot regions118may define areas for block structures and slots (e.g., slits, trenches) to be formed during subsequent processing of the microelectronic device structure100to form a microelectronic device, as described in further detail below.

InFIG. 1AandFIG. 1B, interfaces between horizontally boundaries of different horizontal regions (e.g., the memory array region102, the staircase region104, the intervening region106, the block regions116) of the microelectronic device structure100are depicted by way of dashed lines. For clarity and ease of understanding the description, inFIG. 1Athe dashed lines associated with the interfaces between the horizontally boundaries of the memory array region102, the staircase region104, and the intervening region106only extend into the sacrificial material114. However, it will be understood that the different horizontal regions of the microelectronic device structure100are not limited to the sacrificial material114alone. Additional features (e.g., additional structures, additional materials, additional devices) may subsequently be formed within the different horizontal regions of the microelectronic device structure100, as described in further detail below. Some of the additional features may be formed to be substantially confined with one or more of the different horizontal regions of the microelectronic device structure100, such that these additional features are formed to be located in at least one but less than all of the different horizontal regions of the microelectronic device structure100. Some other of the additional features may be formed to be located in each of the different horizontal regions of the microelectronic device structure100, such that portions of these other additional features are located in all of the different horizontal regions of the microelectronic device structure100.

The base structure108comprises a construction upon which additional features (e.g., materials, structures, devices) of the microelectronic device structure100are formed. The base structure108may include a semiconductive structure (e.g., a semiconductive wafer), and/or a semiconductive material on or over another structure (e.g., a supporting structure). Semiconductive material of the base structure108may, for example, include one or more of silicon, such monocrystalline silicon and/or polycrystalline silicon (also referred to herein as “polysilicon”); silicon-germanium; germanium; gallium arsenide; a gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride. The base structure108may further include one or more additional materials (e.g., conductive materials, insulative materials), structures (e.g., conductive structures, insulative structure), devices (e.g., control logic devices), and/or regions therein. For example, the base structure108may include a control logic region therein including various transistors and conductive routing structures (e.g., conductive line structures, conductive contact structures) that together form control logic circuitry for various control logic devices of the microelectronic device structure100. In some embodiments, the control logic devices within the base structure108comprise complementary metal oxide semiconductor (CMOS) circuitry.

The control logic devices within the control logic region of the base structure108may be configured to control various operations of additional features (e.g., arrays of memory cells) to subsequently be formed within the memory array region102of the microelectronic device structure100, as described in further detail below. As a non-limiting example, the control logic devices may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), Vddregulators, string drivers, page buffers, and various chip/deck control circuitry. As another non-limiting example, the control logic devices may include devices configured to control column operations for arrays (e.g., memory cell arrays) to be formed within the memory array region102of the microelectronic device structure100, such as one or more (e.g., each) of decoders (e.g., local deck decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuitry (e.g., column repair circuitry), I/O devices (e.g., local I/O devices), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices. As a further non-limiting example, the control logic devices may include devices configured to control row operations for arrays (e.g., memory cell arrays) to be formed within the memory array region102of the microelectronic device structure100, such as one or more (e.g., each) of decoders (e.g., local deck decoders, row decoders), drivers (e.g., access line drivers, word line (WL) drivers), repair circuitry (e.g., row repair circuitry), memory test devices, MUX, ECC devices, and self-refresh/wear leveling devices.

The source tier109may be vertically interposed (e.g., in the Z-direction) between the base structure108and the sacrificial material114overlying the base structure108. The source tier109may include at least one source structure110. The source tier109may also include one or more contact structures111(e.g., contact pads) horizontally neighboring and electrically isolated from the source structure110. As shown inFIG. 1A, at least one dielectric material107may be interposed between the source structure110and the contact structures111.

The source structure110and the contact structures111of the source tier109may each be formed of and include conductive material. A material composition of the source structure110may be substantially the same as a material composition of the contact structures111. In some embodiments, the source structure110and the contact structures111are formed of and include conductively doped semiconductive material, such as a conductively doped form of one or more of a silicon material, such as monocrystalline silicon or polycrystalline silicon; a silicon-germanium material; a germanium material; a gallium arsenide material; a gallium nitride material; and an indium phosphide material. As a non-limiting example, the source structure110and the contact structures111may be formed of and include silicon (e.g., polycrystalline silicon) doped with at least one dopant (e.g., one or more of at least one n-type dopant, at least one p-type dopant, and at least one other dopant). In additional embodiments, the source structure110and the contact structures111are formed of and include one or more of a metal, an alloy, and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). As a non-limiting example, the source structure110and the contact structures111may be formed of and include W.

The isolation material112overlying the source tier109may be formed of and include insulative material. By way of non-limiting example, the isolation material112may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and a MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric oxycarbide material (e.g., SiOxCy), at least one hydrogenated dielectric oxycarbide material (e.g., SiCxOyHz), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). A material composition of the isolation material112may be substantially the same as a material composition of the dielectric material107, or a material composition of the isolation material112may be different than a material composition of the dielectric material107. In some embodiments, the isolation material112is formed of and includes at least one dielectric oxide material (e.g., SiOx, such as silicon dioxide (SiO2)). The isolation material112may be substantially homogeneous, or the isolation material112may be heterogeneous.

Referring toFIG. 1A, vertical contact structures113may be formed to vertically extend through the isolation material112. The vertical contact structures113may, for example, be formed to vertically extend (e.g., in the Z-direction) from the sacrificial material114overlying the isolation material112, through the isolation material112, and to the source tier109. At least some of the vertical contact structures113contact (e.g., physically contact, electrically contact) the source structure110of the source tier109. The vertical contact structures113may couple the source structure110to additional structures (e.g., lateral contact structures) to subsequently be formed using the sacrificial material114, as described in further detail below. The vertical contact structures113may each be formed of and include conductive material. By way of non-limiting example, the vertical contact structures113may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the vertical contact structures113are formed of and include W.

The sacrificial material114may be formed of and include at least one material that may be selectively removed relative to the isolation material112and insulative structures of a stack structure to be formed on or over the sacrificial material114(as described in further detail below). A material composition of the sacrificial material114is different than a material composition of the isolation material112and the insulative structures to be formed. The sacrificial material114may be selectively etchable relative to the isolation material112and the insulative structures to be formed during common (e.g., collective, mutual) exposure to a first etchant; and the isolation material112and the insulative structures may be selectively etchable relative to the sacrificial material114during common exposure to a second, different etchant. As used herein, a material is “selectively etchable” relative to another material if the material exhibits an etch rate that is at least about five times (5×) greater than the etch rate of another material, such as about ten times (10×) greater, about twenty times (20×) greater, or about forty times (40×) greater.

As a non-limiting example, the sacrificial material114may be formed of and include a semiconductive material, such as one or more of silicon (e.g., monocrystalline silicon and/or polycrystalline silicon), silicon-germanium, germanium, gallium arsenide, a gallium nitride, gallium phosphide, indium phosphide, indium gallium nitride, and aluminum gallium nitride. In some embodiments, the sacrificial material114is formed of and includes polycrystalline silicon.

As another non-limiting example, the sacrificial material114may be formed of and include a different insulative material than the isolation material112and insulative structures to subsequently be formed, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and a MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric oxycarbide material (e.g., SiOxCy), at least one hydrogenated dielectric oxycarbide material (e.g., SiCxOyHz), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, such as embodiments wherein the isolation material112and insulative structures to subsequently be formed comprise a dielectric oxide material (e.g., SiOx, such as Sift), the sacrificial material114is formed of and includes at least one dielectric nitride material (e.g., SiNy, such as Si3N4).

Next, referring collectively toFIG. 2AandFIG. 2B(which depicts a simplified partial top-down view of the microelectronic device structure100at the processing stage shown inFIG. 2A), an etch-resistant material120may be formed within the sacrificial material114. The etch-resistant material120may be relatively more resistant to removal than the sacrificial material114during common (e.g., collective, mutual) exposure to an etchant (e.g., an etching agent, such as a wet etching agent). The sacrificial material114may be selectively etchable relative to the etch-resistant material120during common exposure to the etchant. The view depicted inFIG. 2Ais a simplified partial cross-sectional view of the microelectronic device structure100about the dashed line Ai-Ai illustrated inFIG. 2B.

The etch-resistant material120may at least be formed within horizontal areas previously occupied by the sacrificial material114that correspond to intersecting portions (e.g., horizontally overlapping portions) of the staircase region104of the microelectronic device structure100and the block regions116of the microelectronic device structure100. Optionally, the etch-resistant material120may also be formed within additional horizontal areas previously occupied by the sacrificial material114that correspond to intersecting portions of the staircase region104of the microelectronic device structure100and the slot regions118of the microelectronic device structure100. In addition, optionally, the etch-resistant material120may also be formed within additional horizontal areas previously occupied by the sacrificial material114that correspond to intersecting portions of the intervening region106of the microelectronic device structure100and at least the block regions116(and, optionally, the slot regions118) of the microelectronic device structure100. The etch-resistant material120may be omitted from (e.g., not formed within) horizontal areas of the sacrificial material114corresponding to intersecting portions of the memory array region102of the microelectronic device structure100and the block regions116of the microelectronic device structure100. In some embodiments, the etch-resistant material120is substantially confined within horizontal areas previously occupied by intersecting portions of the staircase region104and the block regions116of the microelectronic device structure100. In additional embodiments, the etch-resistant material120is substantially confined within horizontal areas previously occupied by intersecting portions of the staircase region104and the block regions116of the microelectronic device structure100, and intersecting portions of the intervening region106and the block regions116of the microelectronic device structure100.

Still collectively referring toFIG. 2AandFIG. 2B, in some embodiments, the etch-resistant material120is formed by removing (e.g., etching) portions of the sacrificial material114to form one or more opening(s) (e.g., aperture(s), trenches(s)) within the sacrificial material114, and then filling the openings with the etch-resistant material120. The opening(s) may be formed to vertically extend substantially through the sacrificial material114. For example, the opening(s) may vertically extend to and expose (e.g., uncover) portions of the isolation material112underlying the sacrificial material. The etch-resistant material120may be formed (e.g., deposited) to substantially fill the opening(s) formed in the sacrificial material114. An upper vertical boundary (e.g., an upper surface) of the etch-resistant material120may be formed to be substantially coplanar with an upper vertical boundary (e.g., an upper surface) of a remaining (e.g., unremoved) portion of the sacrificial material114.

If portions of the sacrificial material114are removed to form openings that are then filled with the etch-resistant material120, the etch-resistant material120may comprise one or more of an insulative material, a conductive material, and a semiconductive material having relatively greater etch resistance than the sacrificial material114during common (e.g., collective, mutual) exposure to at least one etchant (e.g., phosphoric acid (H3PO4), tetramethylammonium hydroxide (TMAH), another etchant) employed in subsequent processing of the microelectronic device structure100. As a non-limiting example, the etch-resistant material120may be formed of and include at least one dielectric material, such as one or more of at least one dielectric oxide material, at least one dielectric nitride material, at least one dielectric oxynitride material, at least one dielectric oxycarbide material, at least one hydrogenated dielectric oxycarbide material, and at least one dielectric carboxynitride material. In some embodiments, the etch-resistant material120is formed of and includes at least one dielectric oxide material, such as SiOx(e.g., SiO2). In additional embodiments, the etch-resistant material120is formed of and includes at least one dielectric nitride material (e.g., SiNy, such as Si3N4) doped with one or more of carbon and oxygen. As another non-limiting example, the etch-resistant material120may be formed of and include at least one conductive material, such as one or more of at least one metal, at least one alloy, at least one conductive metal-containing material (e.g., at least one conductive metal nitride, at least one conductive metal silicide, at least one conductive metal carbide, at least one conductive metal oxide), and at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped silicon SiGe). In some embodiments, the etch-resistant material120is formed of and includes one or more of at least one metal (e.g., one or more of W, Co, and Mo), at least one conductive metal nitride (e.g., one or more of WNxand TiNx), at least one conductive metal silicide (e.g., one or more of WSixand CoSix), and at least one conductive metal oxide. In additional embodiments, the etch-resistant material120is formed of and includes polysilicon doped with one or more of at least one P-type dopant (e.g., one or more of boron (B), aluminum (Al), and gallium (Ga)), carbon, nitrogen, and oxygen. The sacrificial material114may be substantially homogeneous, or the sacrificial material114may be heterogeneous.

In additional embodiments, the etch-resistant material120is formed by doping portions of the sacrificial material114with at least one dopant (e.g., chemical species) that modify the etch resistance of the doped portions of the sacrificial material114relative to other portions of the sacrificial material114. The doped portions of the sacrificial material114may constitute the etch-resistant material120. The dopant may be selected at least partially based on the material composition of the sacrificial material114, so as to enhance the etch resistance of the doped portions of sacrificial material114forming the etch-resistant material120during exposure to at least one etchant relative to other portions of the sacrificial material114remaining undoped with the dopant. As a non-limiting example, if the sacrificial material114comprises polysilicon, the portions of the sacrificial material114may be doped with one or more of at least one P-type dopant (e.g., one or more of B, Al, and Ga), carbon, nitrogen, and oxygen to form the etch-resistant material120. The etch-resistant material120(e.g., doped polysilicon) may, for example, have greater etch resistance to TMAH than remaining portions of the sacrificial material114not doped with the one or more of at least one P-type dopant, carbon, nitrogen, and oxygen. As another non-limiting example, if the sacrificial material114comprises a dielectric nitride material (e.g., SiNy, such as Si3N4), the portions of the sacrificial material114may be doped with one or more of carbon and oxygen to form the etch-resistant material120. The etch-resistant material120(e.g., doped dielectric nitride material) may, for example, have greater etch resistance to H3PO4than remaining portions of the sacrificial material114not doped with the one or more of carbon and oxygen.

If the sacrificial material114is doped to form the etch-resistant material120, a concentration range of dopant within the etch-resistant material120may at least partially depend on material compositions of the sacrificial material114and the dopant. As a non-limiting example, if the sacrificial material114comprises polysilicon and the dopant comprises at least one P-type dopant, a concentration range of the P-type dopant within the etch-resistant material120(e.g., doped poly silicon) may be greater than or equal to about 1E17 units (e.g., atoms, ions) of P-type dopant per cubic centimeter (cm3), such as greater than or equal to 1E17 units of P-type dopant/cm3, from about 1E18 units of P-type dopant/cm3to about 5E18 units of P-type dopant/cm3. As another non-limiting example, if the sacrificial material114comprises polysilicon or dielectric nitride material (e.g., SiNy, such as Si3N4) and the dopant comprises oxygen, the etch-resistant material120(e.g., doped polysilicon or doped dielectric nitride material) may comprise greater than or equal to 1 atomic percent oxygen, such as from about 1 atomic percent oxygen to about 66 atomic percent oxygen. As a further non-limiting example, if the sacrificial material114comprises polysilicon or dielectric nitride material (e.g., SiNy, such as Si3N4) and the dopant comprises carbon, the etch-resistant material120(e.g., doped polysilicon or doped dielectric nitride material) may comprise greater than or equal to 1 atomic percent carbon, such as from about 1 atomic percent carbon to about 20 atomic percent carbon.

Next, referring collectively toFIG. 3AandFIG. 3B(which depicts a simplified partial top-down view of the microelectronic device structure100at the processing stage shown inFIG. 3A), a preliminary stack structure122including at least one staircase structure130therein may be formed on or over the etch-resistant material120and remaining portions of the sacrificial material114. The preliminary stack structure122may horizontally extend (e.g., in the X-direction and the Y-direction) throughout the memory array region102, the staircase region104, and the intervening region106of the microelectronic device structure100. The staircase structure130may be formed within the staircase region104of the microelectronic device structure100. In addition, further features may be formed within portions of the memory array region102and the intervening region106horizontally overlapping with the block regions116of the microelectronic device structure100. Non-limiting examples of such further features include cell pillar structures134, dummy pillar structures136, and deep contact pillar structures137. The foregoing features, as well as other features of the microelectronic device structure100at the processing stage ofFIG. 3AandFIG. 3B, are described in further detail below. The view depicted inFIG. 3Ais a simplified partial cross-sectional view of the microelectronic device structure100about the dashed line Ai-Ai illustrated inFIG. 3B.

The preliminary stack structure122may be formed to include a vertically alternating (e.g., in the Z-direction) sequence of insulative material124and additional sacrificial material126arranged in tiers128. Each of the tiers128of the preliminary stack structure122may include the additional sacrificial material126vertically neighboring the insulative material124. The preliminary stack structure122may be formed to include any desired number of the tiers128, such as greater than or equal to sixteen (16) of the tiers128, greater than or equal to thirty-two (32) of the tiers128, greater than or equal to sixty-four (64) of the tiers128, greater than or equal to one hundred and twenty-eight (128) of the tiers128, or greater than or equal to two hundred and fifty-six (256) of the tiers128.

The insulative material124of the tiers128of the preliminary stack structure122may be formed of and include at least one dielectric material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). A material composition of the insulative material124may be different than material composition(s) of the additional sacrificial material126and the sacrificial material114. The material composition of the insulative material124may be substantially the same as a material composition of the etch-resistant material120, or the material composition of the insulative material124may be different than the material composition of the etch-resistant material120. In some embodiments, each of the insulative material124is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The insulative material124of each of the tiers128may be substantially homogeneous, or the insulative material124of one or more (e.g., each) of the tiers128may be heterogeneous.

The additional sacrificial material126of the tiers128of the preliminary stack structure122may be formed of and include at least one material (e.g., at least one insulative material) that may be selectively removed relative to the insulative material124, the etch-resistant material120, and the isolation material112. A material composition of the additional sacrificial material126is different than material compositions of the insulative material124, the etch-resistant material120, and the isolation material112. The material composition of the additional sacrificial material126may be substantially the same as a material composition of the sacrificial material114, or the material composition of the insulative material124may be different than the material composition of the sacrificial material114. The additional sacrificial material126may be selectively etchable relative to the insulative material124, the etch-resistant material120, and the isolation material112during common (e.g., collective, mutual) exposure to a first etchant; and the insulative material124, the etch-resistant material120, and the isolation material112may be selectively etchable relative to the additional sacrificial material126during common exposure to a second, different etchant. In some embodiments, each of the additional sacrificial material126is formed of and includes a dielectric nitride material, such as SiNy(e.g., Si3N4). In some of such embodiments, the sacrificial material114is formed of and includes the same dielectric nitride material (e.g., SiNy, such as Si3N4) as the additional sacrificial material126. The additional sacrificial material126and the sacrificial material114may, for example, be selectively etchable relative to the insulative material124, the etch-resistant material120, and the isolation material112during common exposure to a wet etchant comprising H3PO4. In additional embodiments, each of the additional sacrificial material126is formed of and includes polycrystalline silicon. In some of such embodiments, the sacrificial material114is also formed of and includes the polycrystalline silicon. The additional sacrificial material126and the sacrificial material114may, for example, be selectively etchable relative to the insulative material124, the etch-resistant material120, and the isolation material112during common exposure to a wet etchant comprising TMAH. The additional sacrificial material126may be substantially homogeneous, or the additional sacrificial material126may be heterogeneous.

The at least one staircase structure130may be formed and positioned within portions of the preliminary stack structure122within horizontal boundaries (e.g., in the X-direction) of the staircase region104of the microelectronic device structure100. The staircase structure130may be formed to horizontally extend (e.g., in the Y-direction) across the block regions116and the slot regions118of the microelectronic device structure100. The staircase structure130includes steps132at least partially defined by horizontal ends (e.g., in the X-direction) of the tiers128of the preliminary stack structure122. The steps132of the staircase structure130may be employed as contact regions to electrically connect the conductive structures subsequently formed using the additional sacrificial material126(e.g., through so-called “replacement gate” or “gate last” processing) to other features (e.g., control logic devices within the base structure108) of the microelectronic device structure100, as described in further detail below. A quantity of steps132included in the staircase structure130may be substantially the same as (e.g., equal to) or may be different than (e.g., less than, greater than) the quantity of tiers128in the preliminary stack structure122. As shown inFIG. 3A, in some embodiments, the steps132of the staircase structure130are arranged in order, such that steps132directly horizontally adjacent one another in the X-direction correspond to tiers128of the preliminary stack structure122directly vertically adjacent (e.g., in the Z-direction) one another. In additional embodiments, the steps132of the staircase structure130are arranged out of order, such that at least some steps132of the staircase structure130directly horizontally adjacent one another in the X-direction correspond to tiers128of preliminary stack structure122not directly vertically adjacent (e.g., in the Z-direction) one another. The staircase structure130may vertically overlie (e.g., in the Z-direction) and horizontally overlap (e.g., in the X-direction and in the Y-direction) the etch-resistant material120.

The cell pillar structures134may be formed and positioned within horizontal areas of the preliminary stack structure122corresponding to intersecting portions (e.g., horizontally overlapping portions) of the memory array region102and the block regions116of the microelectronic device structure100. The cell pillar structures134may at least partially vertically overlie (e.g., in the Z-direction) and horizontally overlap (e.g., in the X-direction and in the Y-direction) remaining portions of the sacrificial material114. As shown inFIG. 5A, in some embodiments, the cell pillar structures134vertically extend through the tiers128of the preliminary stack structure122and to the remaining portions of the sacrificial material114. The cell pillar structures134may vertically terminate at or within the remaining portions of the sacrificial material114. In additional embodiments, the cell pillar structures134vertically extend through the tiers128of the preliminary stack structure122and also vertically extend through the remaining portions of the sacrificial material114. The cell pillar structures134may vertically terminate below the remaining portions of the sacrificial material114, such as at or within the isolation material112, at or within the source tier109, or at or within the base structure108.

The cell pillar structures134may each individually be formed of and include a stack of materials. By way of non-limiting example, each of the cell pillar structures134may be formed to include a charge-blocking material, such as first dielectric oxide material (e.g., SiOx, such as SiO2; AlOx, such as Al2O3); a charge-trapping material, such as a dielectric nitride material (e.g., SiNy, such as Si3N4); a tunnel dielectric material, such as a second oxide dielectric material (e.g., SiOx, such as SiO2); a channel material, such as a semiconductive material (e.g., silicon, such as polycrystalline Si); and a dielectric fill material (e.g., a dielectric oxide, a dielectric nitride, air). The charge-blocking material may be formed on or over surfaces of the insulative material124and the additional sacrificial material126of the tiers128of the preliminary stack structure122at least partially defining horizontal boundaries of the cell pillar structures134; the charge-trapping material may be horizontally surrounded by the charge-blocking material; the tunnel dielectric material may be horizontally surrounded by the charge-blocking material; the channel material may horizontally surrounded by the tunnel dielectric material; and the dielectric fill material may horizontally surrounded by the channel material.

The dummy pillar structures136, if any, may comprise pillar structures that are and/or that will be electrically disconnected from other features (e.g., conductive structures, such as conductive lines) of the microelectronic device structure100; and/or that do not and/or will not facilitate electrical communication between the other features of the microelectronic device structure100. The dummy pillar structures136may, for example, be employed to mitigate damage to and/or defects at edges of arrays of the cell pillar structures134(e.g., commonly referred to as “array edge effects”).

If formed, the dummy pillar structures136may horizontally neighbor outermost (e.g., in the X-direction) cell pillar structures134, such as cell pillar structures134positioned relatively closest to horizontal boundaries (e.g., in the X-direction) of the memory array region102of the microelectronic device structure100. The dummy pillar structures136may be formed and positioned within horizontal areas of the preliminary stack structure122corresponding to intersecting portions (e.g., horizontally overlapping portions) of the intervening region106and the block regions116of the microelectronic device structure100. The dummy pillar structures136may vertically extend through the tiers128of the preliminary stack structure122to remaining portions of the sacrificial material114and/or to the etch-resistant material120. As shown inFIG. 5A, in some embodiments, the dummy pillar structures136vertically extend through the tiers128of the preliminary stack structure122and to the remaining portions of the sacrificial material114and/or to the etch-resistant material120. The dummy pillar structures136may vertically terminate at or within the remaining portions of the sacrificial material114and/or at or within the etch-resistant material120. In additional embodiments, the dummy pillar structures136vertically extend through the tiers128of the preliminary stack structure122and also vertically extend through the remaining portions of the sacrificial material114and/or etch-resistant material120. The dummy pillar structures136may vertically terminate below the remaining portions of the sacrificial material114and the etch-resistant material120, such as at or within the isolation material112, at or within the source tier109, or at or within the base structure108.

The dummy pillar structures136, if any, may be formed of and include one or more materials (e.g., insulative materials, conductive materials, semiconductive materials) able to alleviate undesirable array edge effects for arrays of the cell pillar structures134within subsequently formed blocks of a stack structure subsequently formed from the preliminary stack structure122. In some embodiments, the dummy pillar structures136comprise dielectric pillar structures. In additional embodiments, the dummy pillar structures136comprise semiconductive pillar structures. In further embodiments, the dummy pillar structures136comprise conductive pillar structures. In yet further embodiments, the dummy pillar structures136comprise pillar structures substantially similar to the cell pillar structures134, but that will not be electrically connected to one or more conductive structures (e.g., conductive lines, such as digit lines; lateral contact structures) that the cell pillar structures134will be electrically connected to. In such embodiments, the cell pillar structures134may be considered “active” cell pillar structures, and the dummy pillar structures136may be considered “inactive” cell pillar structures.

The deep contact pillar structures137may be formed and positioned within horizontal areas of the preliminary stack structure122corresponding to intersecting portions (e.g., horizontally overlapping portions) of the intervening region106and the block regions116of the microelectronic device structure100. The deep contact pillar structures137may vertically extend through the tiers128of the preliminary stack structure122, through remaining portions of the sacrificial material114and/or the etch-resistant material120, through the isolation material112, and to the source tier109of the microelectronic device structure100. One or more of the deep contact pillar structures137may be configured and positioned to electrically connect one or more features of the source tier109(e.g., the source structure110, the contact structures111) to one or more conductive features (e.g., additional contact structures, conductive line structures) to subsequently be formed over upper vertical boundaries of the preliminary stack structure122. Optionally, one or more other of the deep contact pillar structures137may be configured and positioned to serve as support structures for subsequent processing of the preliminary stack structure122, such as subsequent replacement gate processing of the preliminary stack structure122. The one or more other of the deep contact pillar structures137may, for example, be configured and positioned to provide support to the preliminary stack structure122at or proximate the staircase structure130to mitigate tier128collapse at or proximate the staircase structure130during the subsequent replacement gate processing. In some embodiments, the one or more other of the deep contact pillar structures137are positioned to electrically disconnected from the conductive features (e.g., additional contact structures, conductive line structures) to subsequently be formed over the upper vertical boundaries of the preliminary stack structure122.

The deep contact pillar structures137may individually be formed of and include at least one conductive material, and at least one insulative liner material substantially horizontally surrounding and covering (e.g., across an entire vertical height of) the conductive material. In some embodiments, the conductive material of the deep contact pillar structures137comprises W. In additional embodiments, the conductive material of the deep contact pillar structures137comprises conductively doped polysilicon. The insulative liner material may be formed of and include at least one insulative material. In some embodiments, the insulative liner material of the deep contact pillar structures137comprises SiOx(e.g., SiO2).

In embodiments wherein the etch-resistant material120is formed to horizontally extend into horizontal areas of the preliminary stack structure122corresponding to intersecting portions (e.g., horizontally overlapping portions) of the intervening region106and the block regions116of the microelectronic device structure100, one or more (e.g., each) of the dummy pillar structures136and/or one or more (e.g., each) of the deep contact pillar structures137may be formed and provided within horizontal boundaries of the etch-resistant material120. In additional embodiments wherein the etch-resistant material120is not formed to horizontally extend into horizontal areas of the preliminary stack structure122corresponding to intersecting portions (e.g., horizontally overlapping portions) of the intervening region106and the block regions116of the microelectronic device structure100, the dummy pillar structures136and the deep contact pillar structures137may be formed and provided outside of horizontal boundaries of the etch-resistant material120.

Next, referring collectively toFIG. 4AandFIG. 4B(which depicts a simplified partial top-down view of the microelectronic device structure100at the processing stage shown inFIG. 4A), portions of at least the preliminary stack structure122and the sacrificial material114within horizontal boundaries (e.g., in the Y-direction and the in the X-direction) of the slot regions118(FIG. 3B) (as well as portions of the etch-resistant material120within the horizontal boundaries of the slot regions118, if any) of the microelectronic device structure100may be removed to form slots140(e.g., slits, openings, trenches). The slots140may divide (e.g., partition) the preliminary stack structure122into preliminary blocks138horizontally separated from one another by the slots140. In addition, the slots140may also divide the sacrificial material114into multiple segments individually confined within horizontal boundaries of individual preliminary blocks138vertically thereover and horizontally separated from one another by the slots140. The view depicted inFIG. 4Ais a simplified partial cross-sectional view of the microelectronic device structure100about the dashed line Ai-Ai illustrated inFIG. 4B.

As shown inFIG. 4B, the slots140may be formed to include first slots140A horizontally extending in a first horizontal direction (e.g., the X-direction), and second slots140B horizontally extending in a second horizontal direction (e.g., the Y-direction) orthogonal to the first horizontal direction. The first slots140A may be horizontally interposed between preliminary blocks138(and, hence, segments of the sacrificial material114) horizontally neighboring one another in the second horizontal direction; and the second slots140B may be horizontally interposed between preliminary blocks138(and, hence, segments of the sacrificial material114) horizontally neighboring one another in the first horizontal direction. The first slots140A may horizontally intersect the second slots140B, and may be integral and continuous with the second slots140B. The slots140, including the first slots140A and the second slots140B thereof, may subsequently be filled with insulative material after subjecting the microelectronic device structure100to so called “replacement gate” or “gate last” processing, as described in further detail below.

Next, referring toFIG. 5AandFIG. 5B(which depicts a simplified partial top-down view of the microelectronic device structure100at the processing stage shown inFIG. 5A) the microelectronic device structure100may be subjected to so called “replacement gate” or “gate last” processing. The replacement gate processing may at least partially replace remaining portions of the additional sacrificial material126(FIG. 4A) and the sacrificial material114(FIG. 4A) with conductive material to form conductive structures148and lateral contact structures152, respectively. The replacement gate processing may convert the preliminary stack structure122(FIG. 4AandFIG. 4B) including the preliminary blocks138(FIG. 4AandFIG. 4B) into a stack structure142including blocks150. The stack structure142may include a vertically alternating (e.g., in the Z-direction) sequence of insulative structures146and the conductive structures148arranged in tiers144. The insulative structures146may correspond to remaining (e.g., unremoved) portions of the insulative material124(FIG. 4A) following the replacement gate processing. The stack structure142may be divided into the blocks150, and the shapes and dimensions of the blocks150may be substantially the same as the shapes and dimensions of the preliminary blocks138(FIG. 4AandFIG. 4B) of the preliminary stack structure122(FIG. 4AandFIG. 4B). The slots140may be interposed between horizontally neighboring blocks150of the stack structure142. The view depicted inFIG. 5Ais a simplified partial cross-sectional view of the microelectronic device structure100about the dashed line Ai-Ai illustrated inFIG. 5B.

The conductive structures148of the stack structure142may be employed as access line structures (e.g., local access line structures, local word line structures). In some embodiments, the conductive structures148are formed of and include W. Optionally, at least one liner material (e.g., at least one insulative liner material, at least one conductive liner materials) may be formed around the conductive structures148. The liner material may, for example, be formed of and include one or more of a metal (e.g., titanium, tantalum), an alloy, a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), and a metal oxide (e.g., aluminum oxide). In some embodiments, the liner material comprises at least one conductive material employed as a seed material for the formation of the conductive structures148. In some embodiments, the liner material comprises titanium nitride (TiNx, such as TiN). In further embodiments, the liner material further includes aluminum oxide (AlOx, such as Al2O3). As a non-limiting example, AlOx(e.g., Al2O3) may be formed directly adjacent the insulative structures146, TiNx(e.g., TiN) may be formed directly adjacent the AlOx, and W may be formed directly adjacent the TiNx. For clarity and ease of understanding the description, the liner material is not illustrated inFIG. 5AandFIG. 5B, but it will be understood that the liner material may be disposed around the conductive structures148.

At least one lower conductive structure148of an individual block150of the stack structure142may be employed as at least one lower select gate (e.g., at least one source side select gate (SGS)) for lower select transistors (e.g., source side select transistors) of the block150. In some embodiments, a single (e.g., only one) conductive structure148of a vertically lowermost tier144of a block150of the stack structure142is employed as a lower select gate (e.g., a SGS) for the block150. In addition, upper conductive structure148of an individual block150of the stack structure142may be employed as upper select gate(s) (e.g., drain side select gate(s) (SGDs)) for upper select transistors (e.g., drain side select transistors) of the block150. In some embodiments, horizontally neighboring (e.g., in the Y-direction) conductive structures148of a vertically uppermost tier144of a block150are employed as upper select gates (e.g., SGDs) for the block150. The horizontally neighboring conductive structures of the vertically uppermost tier144of the block150may be separated from one another by an additional slot (e.g., an SGD slot) may be subsequently be filled with insulative material.

Intersections of the cell pillar structures134and the conductive structures148of the stack structure142may define vertically extending strings of memory cells154coupled in series with one another within the stack structure142. In some embodiments, the memory cells154formed at the intersections of the conductive structures148and the cell pillar structures134within different tiers144of the stack structure142comprise so-called “MONOS” (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells154comprise so-called “TANOS” (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called “BETANOS” (band/barrier engineered TANOS) memory cells, each of which are subsets of MONOS memory cells. In further embodiments, the memory cells154comprise so-called “floating gate” memory cells including floating gates (e.g., metallic floating gates) as charge storage structures. The floating gates may horizontally intervene between central structures of the cell pillar structures134and the conductive structures148of the different tiers144of the stack structure142.

The lateral contact structures152may be employed to electrically connect the cell pillar structures134(and, hence, the vertically extending strings of memory cells154) vertically extending through the blocks150of the stack structure142to the source structure110of the source tier109. Individual lateral contact structures152may extend between and contact (e.g., physically contact, electrically contact) the channel material (e.g., polysilicon) of multiple cell pillar structures134within individual block150of the stack structure142, and may also contact (e.g., physically contact, electrically contact) at least some of the vertical contact structures113coupled to the source structure110within the source tier109of the microelectronic device structure100. Within horizontal boundaries of an individual block150, individual lateral contact structures152may be located horizontally adjacent (e.g., in the X-direction) the etch-resistant material120within the horizontal boundaries of the individual block150.

The lateral contact structures152may at least be formed and positioned within horizontal boundaries (e.g., in the X-direction) of the memory array region102of the microelectronic device structure100. In some embodiments, the lateral contact structures152are substantially confined within the horizontal boundaries of the memory array region102of the microelectronic device structure100. In additional embodiments, depending on the horizontal geometric configurations of the remaining portions of the sacrificial material114(FIG. 4A) and the etch-resistant material120, the lateral contact structures152are formed to extend beyond the horizontal boundaries of the memory array region102of the microelectronic device structure100. For example, if the remaining portions of the sacrificial material114(FIG. 4A) horizontally extend into the intervening region106of the microelectronic device structure100, the lateral contact structures152may also horizontally extend into the intervening region106of the microelectronic device structure100. The lateral contact structures152may not substantially horizontally extend into the staircase region104of the microelectronic device structure100. The staircase region104of the microelectronic device structure100may be substantially free of the lateral contact structures152. As shown inFIG. 5A, the etch-resistant material120may remain within the staircase region104of the microelectronic device structure100following the replacement gate processing of the microelectronic device structure100.

A material composition of the lateral contact structures152may be substantially the same as a material composition of the conductive structures148of the stack structure142, or the material composition of the lateral contact structures152may be different than the material composition of the conductive structures148of the stack structure142. In some embodiments, the lateral contact structures152are formed of and include W. The lateral contact structures152may individually be substantially homogeneous, or the lateral contact structures152may individually be heterogeneous.

The replacement gate processing employed to form the stack structure142and the lateral contact structures152may include treating the microelectronic device structure100with at least one wet etchant formulated to selectively remove portions of the sacrificial material114(FIG. 4A) and the additional sacrificial material126(FIG. 4A) exposed by the slots140without substantially removing portions of the isolation material112, the etch-resistant material120, and the insulative material124(FIG. 4A) exposed by the slots140to form recesses. By way of non-limiting example, depending on material compositions of the sacrificial material114(FIG. 4A), the additional sacrificial material126(FIG. 4A), the isolation material112, the etch-resistant material120, and the insulative material124(FIG. 4A), the wet etchant may one or more of TMAH, H3PO4, sulfuric acid (H2SO4), hydrochloric acid (HCl), nitric acid (HNO3), and another material. In some embodiments wherein the sacrificial material114(FIG. 4A) and the additional sacrificial material126(FIG. 4A) comprise polysilicon, the sacrificial material114(FIG. 4A) and the additional sacrificial material126(FIG. 4A) are at least partially removed without substantially removing the isolation material112, the etch-resistant material120, and the insulative material124(FIG. 4A) using a wet etchant comprising TMAH. In additional embodiments wherein the sacrificial material114(FIG. 4A) and the additional sacrificial material126(FIG. 4A) comprise a dielectric nitride material (e.g., SiNy, such as Si3N4), the sacrificial material114(FIG. 4A) and the additional sacrificial material126(FIG. 4A) are at least partially removed without substantially removing the isolation material112, the etch-resistant material120, and the insulative material124(FIG. 4A) using a wet etchant comprising H3PO4. Following the selective removal of the portions of the sacrificial material114(FIG. 4A) and the additional sacrificial material126(FIG. 4A), the resulting recesses may be filled with conductive material to form the lateral contact structures152and the conductive structures148, respectively.

During the replacement gate processing, the etch-resistant material120within at least the staircase region104of the microelectronic device structure100may impede or prevent undesirable damage (e.g., tier collapse, tier cracking, tier lifting) and/or undesirable deformations (e.g., tier bending, tier warping, tier bowing) to the preliminary stack structure122(FIG. 4A) within the staircase region104of the microelectronic device structure100that may otherwise occur if portions of the sacrificial material114(FIG. 4A) were not replaced with the etch-resistant material120during the processing stage previously described with respect toFIG. 2AandFIG. 2B. For example, forming the etch-resistant material120within the staircase region104of the microelectronic device structure100circumvents removal of sacrificial material114(FIG. 4A) within the staircase region104that may otherwise occur during the replacement gate processing and that may impart stresses effectuating undesirable damage to and/or undesirable deformations of portions of the tiers128(FIG. 4A) of the preliminary stack structure122(FIG. 4A) within the staircase region104ahead of the formation of the conductive structures148.

Thus, in accordance with embodiments of the disclosure, a method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures.

FIG. 6illustrates a partial cutaway perspective view of a portion of a microelectronic device201(e.g., a memory device, such as a 3D NAND Flash memory device) including a microelectronic device structure200. The microelectronic device structure200may be substantially similar to the microelectronic device structure100following the processing stage previously described with reference toFIG. 5AandFIG. 5B. In some embodiments, the microelectronic device structure200is formed through the processes previously described with reference toFIG. 1AthroughFIG. 5B. To avoid repetition, not all features (e.g., structures, materials, regions, devices) shown inFIG. 6are described in detail herein. Rather, unless described otherwise below, inFIG. 6, a feature designated by a reference numeral that is a 100 increment of the reference numeral of a feature previously described with reference to one or more ofFIG. 1AthroughFIG. 5Bwill be understood to be substantially similar to the previously described feature. In addition, for clarity and ease of understanding the drawings and associated description, some features of the microelectronic device structure100following the processing stage previously described with reference toFIG. 5AandFIG. 5Bare not shown inFIG. 6. However, it will be understood that any features of the microelectronic device structure100following the processing stage previously described with reference toFIG. 5AandFIG. 5Bmay be included in the microelectronic device structure200of the microelectronic device201described herein with reference toFIG. 6.

As shown inFIG. 6, in addition to the features of the microelectronic device structure200previously described herein in relation to the microelectronic device structure100, the microelectronic device201may further include digit lines256(e.g., data lines, bit lines), access line routing structures258, access line contact structures260, select line routing structures262, and select line contact structures264. The access line contact structures260and the select line contact structures264may contact (e.g., physically contact, electrically contact) steps232of staircase structures230within the staircase region204of the microelectronic device201, and may couple components to one another as shown (e.g., the select line routing structures262to conductive structures248of the stack structure242employed as upper select gates (e.g., SGDs); the access line routing structures258to conductive structures248of the stack structure242employed as local access lines). In addition, as shown inFIG. 6, at least a portion of the base structure208is positioned within horizontal boundaries of the memory array region202of the microelectronic device201. The base structure208may include a control logic region including control logic circuitry (e.g., CMOS circuitry) that may be coupled to the digit lines256, the source structure210within the source tier209, the access line routing structures258, and the select line routing structures262. In such embodiments, the control logic region of the base structure208may be characterized as having a “CMOS under Array” (“CuA”) configuration.

Thus, in accordance with embodiments of the disclosure, a microelectronic device comprises blocks, an etch-resistant material, lateral contact structures, and additional conductive structures. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the blocks comprises a staircase structure having steps comprising horizontal ends of the tiers. The etch-resistant material vertically underlies each of the blocks and is within horizontal boundaries of the staircase structure of each of the blocks. The lateral contact structures vertically underlie each of the blocks and are outside of horizontal boundaries of the staircase structure. The lateral contact structures horizontally neighbor and are at substantially the same vertical position as the etch-resistant material. The additional conductive structures vertically underlie and are electrically connected to the lateral contact structures.

Furthermore, in accordance with embodiments of the disclosure, a memory device comprises a stack structure, a staircase structure, an etch-resistant material, additional conductive structures, vertically extending strings of memory cells, and a base structure. The stack structure comprises blocks each having tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The staircase structure is within a contact region of each block of the stack structure, and has steps comprising edges of the tiers of the block. The etch-resistant material vertically underlies the stack structure and is within horizontal boundaries of the contact region of each block of the stack structure. The additional conductive structures vertically underlie the stack structure and are within horizontal boundaries of a memory array region of each block of the stack structure. The additional conductive structures horizontally neighbor and are at substantially the same vertical position as the etch-resistant material. The vertically extending strings of memory cells are within the memory array region of each block of the stack structure and are coupled to the additional conductive structures. The base structure vertically underlies the stack structure and comprises control logic circuitry coupled to the vertically extending strings of memory cells.

Microelectronic devices structures (e.g., the microelectronic device structure100(FIGS. 5A and 5B)) and microelectronic devices (e.g., the microelectronic device201(FIG. 6)) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG. 7is a block diagram of an illustrative electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an IPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, one or more of a microelectronic device structure (e.g., the microelectronic device structure100(FIGS. 5A and 5B)) and a microelectronic device (e.g., the microelectronic device201(FIG. 6)) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, include one or more of a microelectronic device structure (e.g., the microelectronic device structure100(FIGS. 5A and 5B)) and a microelectronic device (e.g., the microelectronic device201(FIG. 6)) previously described herein. While the memory device302and the electronic signal processor device304are depicted as two (2) separate devices inFIG. 7, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device302and the electronic signal processor device304is included in the electronic system300. In such embodiments, the memory/processor device may include one or more of a microelectronic device structure (e.g., the microelectronic device structure100(FIGS. 5Aand5B)) and a microelectronic device (e.g., the microelectronic device201(FIG. 6)) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308may comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304.

Thus, in accordance with embodiments of the disclosures, an electronic system comprises an input device, an output device, a processor device operably connected to the input device and the output device, and a memory device operably connected to the processor device. The memory device comprises blocks, strings of memory cells, digit line structures, an etch-resistant material, lateral contact structures, at least one source structure, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the blocks comprises a staircase structure having steps comprising horizontal ends of the tiers of the block. The strings of memory cells vertically extend through the blocks. The digit line structures vertically overlie the blocks and are coupled to the strings of memory cells. The etch-resistant material vertically underlies each of the blocks and is within horizontal boundaries of the staircase structure of each of the blocks. The lateral contact structures vertically underlie each of the blocks and are outside of the horizontal boundaries of the staircase structure of each of the blocks. The lateral contact structures are each coupled to some of the strings of memory cells and are each directly horizontally adjacent to some of the etch-resistant material. The at least one source structure vertically underlies and is coupled to the lateral contact structures. The base structure vertically underlies the at least one source structure and comprising control logic devices coupled to the conductive structures of the blocks, the digit line structures, and the at least one source structure.

The methods, structures (e.g., the microelectronic device structure100(FIGS. 5A and 5B)), devices (e.g., the microelectronic device201(FIG. 6)), and systems (e.g., the electronic system300(FIG. 7)) of the disclosure advantageously facilitate one or more of improved performance, reliability, and durability, lower costs, increased miniaturization of components, improved pattern quality, and greater packaging density as compared to conventional structures, conventional devices, and conventional systems. By way of non-limiting example, the methods and structures of the disclosure may reduce the risk of undesirable deformations (e.g., tier bending, tier warping, tier bowing) and damage (e.g., tier collapse) during the formation of devices (e.g., the microelectronic device201) of the disclosure, and may effectuate increased yield and decreased current leakage (e.g., which may otherwise result from the undesirable deformations and/or damage) as compared to conventional methods, conventional structures, and conventional devices.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalent. For example, elements and features disclosed in relation to one embodiment of the disclosure may be combined with elements and features disclosed in relation to other embodiments of the disclosure.