Thermal spreading management of 3D stacked integrated circuits

An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

TECHNICAL FIELD

Embodiments described herein generally semiconductor devices and systems.

BACKGROUND

Semiconductor devices can contain three dimensional (3D) stacks of integrated circuits (IC) dies connected to a singles logic die. In such stacks, heat dissipation can be uneven throughout the dies. It is desired to have more uniform heat distribution that address these concerns, and other technical challenges.

DESCRIPTION OF EMBODIMENTS

In the figures and the text that follows, the terms “top” and “bottom” are used to show orientations of particular features on particular elements, or relative orientations of one element to another element. The designations of top and bottom are used merely for convenience and clarity and are not intended to represent absolute orientation or direction. For example, a “top” surface of an element remains a top surface regardless of an absolute orientation of the element, even if the element is inverted during storage or use. This document uses the common convention of a chip package being positioned on top of a motherboard, which establishes directions of up and down, and top and bottom, relative to this convention.

Three dimensional (3D) stacked integrated circuit (IC) dies present unique challenges to thermal management. The resistance of the stacked dies can be high due to inter-die dielectric layers. Non-uniform dispersion of heat throughout the stacked dies can cause hot spots and cold spots through the stacked dies.

In conventional 3D stacked ICs, a portion of the power source could be on a small region on the bottom of the logic die or other bottom die. The logic die and inter-die dielectric layer can, in turn, have a thickness and resistance that prevent even spreading of heat from the power source to the rest of the device, creating inefficient dissipation of power (heat) that results in hot spots or cold spots. For this reason, a conventional device can be subject to uneven heating and become the limiter of power in a larger package into which it is incorporated.

This can result in limited package performance overall. Specifically, inefficient heat dissipation can cause certain portions of a conventional device to heat at a faster rate, reaching a threshold junction temperature (Tj) faster. The threshold junction temperature is the highest temperature at which a semiconductor (or other electronic device) can operate at. Once threshold junction temperature is reached, clock frequency and other performance metrics are reduced.

Previous attempts at regulating thermal dissipation in 3D stacked ICs have included, for example, reduction of total package power through reducing central processing unit (CPU) or graphic processing unit (GPU) power, reduced workload and frequency of using stacked ICs, the use of liquid cooling fluid, use of high conductivity thermal interface layers (e.g., (solder or other TIM), or increased refresh rate (e.g., for HBM) to enable a higher threshold junction temperature (Tj).

Each of these approaches has certain disadvantages. Reducing power or workload of the 3D stacked ICs decreases total package performance. This is not sustainable with increasing thermal designation power (TDP) demands. Liquid cooling or solder solutions increase package cost, size, and decrease lifetime reliability. Increasing HBM refresh rates increases overall power consumption, resulting in more burdens for the cooling system.

Discussed herein is the use of a dummy die, made of a thermally conductive material, such as boron nitride, diamond, boron arsenide, silicon or silicon carbide, between a bottom die (i.e., a logic die) and a substrate, or between the bottom die (i.e., a logic die) and the stack of dies. The use of a dummy die can, for example, promote uniform dispersion of heat through stacked dies in a 3D stacked IC device.

The use of a dummy die can help spread (or dissipate) heat throughout a 3D stacked IC. In some embodiments, the heat can be dissipated when it reaches air; in other embodiments, the heat is spread more evenly throughout the 3D stacked IC.FIG. 1illustrates a schematic view of a semiconductor device including a 3D stacked IC100with a dummy die170in various embodiments. Device100includes die stack110with individual dies120and interface layers130, interconnect140, logic die150, power source160, and dummy die170. Device100can run at a total stack power from about 0.0 W to about 100.0 W (e.g., about 15.0 W to about 20.0 W, or about 16.0 W to about 18.0 W). In device100, power source160is electrically coupled to logic die150, which is electrically coupled via interconnect140to die stack110. Die stack110includes individual dies120separated by interface layers130, and electrically connected through interconnect140. Dummy die170is attached between die stack110and bottom die150.

Device100can be a 3D stacked IC. 3D stacked ICs can, for example, include a 3D integration scheme that relies on interconnect at the package level, such as wire bonding or flip chip to achieve vertical stacks. Examples of 3D packages can include package-on-package (PoP) where individual die are packaged, and the packages are stacked and interconnected with wire bonds or flip chip processes, or, for example, 3D wafer-level packaging that uses redistribution layers and bumping processes to form interconnects.

3D stacked ICs, such as device100can, for example, contain dies which are stacked together and connected with through silicon vias (TSVs, e.g., holes created in a silicon wafer using an etch process used as interconnects), or alternatively can use fabrication processes to stack multiple device layers on a single die, that can sometimes use TSVs. In some embodiments, device100can be monolithic 3D stacked ICs where a base wafer is, for example, added onto with additional layers of crystallized silicon, metalized layers, and active or passive circuitry. In monolithic 3D stacked ICs, interconnects may be formed, for example, between layers rather than dies.

In device100, an example 3D IC, die stack110can, for example, be a memory die stack including volatile memory such as a dynamic random-access memory (DRAM). If die stack110is a DRAM die stack, it can be, for example, a type of random access semiconductor memory that stores each bit of data in a separate capacitor within an IC (i.e., one of dies140). Each capacitor within the DRAM die can, for example, be charged or discharged, representing two or more values of a bit, such as a 0 or a 1. A DRAM die, such as dies120, can prevent loss of electric charge (and loss of data) by connection to an external memory refresh circuit.

Alternatively, die stack110can include other types of memory, such as a synchronous dynamic random access memory (SDRAM), RAMBUS dynamic random access memory (RDRAM), or other type of random access memory device. In other embodiments, die stack110can include non-volatile memory, such as, for example, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Alternatively, die stack110can include a static RAM (SRAM) or other memory dies for use with a multi-core processor die; or die stack110could include a a system of chip (SOC). Other appropriate 3D stacked ICs could be used for die stack110as known to one in the art.

InFIG. 1, eight individual dies120are schematically represented. In other embodiments, more or less dies120can be present. Each of the adjacent individual dies120can be separated by interface layers130. Interface layers130can include, for example, solder, thermal bumps, electrical bumps, a metallic interface, an epoxy-based material, an underfill, combinations thereof, or other materials as appropriate in the art. The interface layers130can serve to spatially and electrically separate individual dies120within die stack110. The interface material130can, for example, serve as an adhesive, dielectric layer, or a laminate. Interconnect140can, for example, pass through the interface layers130.

Interconnect140can electrically couple individual dies120to each other and to logic die150(discussed below). Interconnect140can be, for example, a vertical interconnect made of an electrically conductive material. In some embodiments, interconnect140can include one or more through silicon vias (TSVs) running through the individual dies120. In other embodiments, one or more wire bonds can be used along with, or in place of interconnect140, implemented using a die stack or stair step configuration, or other interconnects appropriate in the art.

Logic die150can be connected to die stack110through interconnect140. Logic die can be, for example, a logic die for HBM or other appropriate logic die for a 3D stacked IC device100. Thickness of logic die150, which can be in the range of about 50 micrometers, can hinder heat dissipation from power source160to the rest of device100. In some embodiments, logic die150is another type of die located on the bottom of the die stack. In alternative embodiments, logic die150can be a multi-core processor die (i.e., on which an alternative memory die stack110would sit), or a voltage regulator (i.e., on which a memory plus processor or other SOC die stack110would sit).

Power source160provides power to device100. Power source160can be connected to logic die150opposite die stack110. In some embodiments, power source160is integrated with logic die150. Power source160can be electrically coupled to logic die150through direct connection, wire bonds, or other appropriate means. Power source160can provide, for example, power of about 0.00 W to about 100.0 W (e.g., 6.0 W to about 9.0 W or about 7.0 W to about 8.0 W).

In device100, dummy die170is inserted into device100between logic die150and die stack110. Dummy die170can be made of silicon, silicon carbide, or other appropriate thermally conductive material with optional passive circuitry, such as, for example, boron nitride, diamond, or boron arsenide. Overall area and thickness of dummy die170can vary depending on power from power source160, size and material of logic die150, and overall heat dispersion needs. For example, dummy die170can have larger footprint than DRAM die if desired for heat dissipation. In some embodiments, the dummy die170can have a thickness of about 50 μm to about 300 μm (e.g., about 100 μm to about 200 μm), depending on the specifics of device100. The length and width of the dummy die can range from about 2 mm to about 30 mm (e.g., about 5 mm to about 20 mm).

Generally, dummy die170can be, for example, a die similar to individual dies120. Dummy die170can be shaped and processed, for example, like individual dies120. For this reason, processing of dummy die170need not be separate or expensive compared to the processing of 3D stacked IC100as a whole.

However, dummy die170has minimal or no electrical circuitry, such that it is not “active” in the die stack110, and is not in electric communication with individual dies120. In general, dummy die170has minimal electrical components. In some instances, dummy die170can have minimal circuitry to allow for pass through of, for example, through silicon vias or other interconnets. However, dummy die170is in thermal communication with logic die150, power source160, and die stack110.

In device100, the dummy die170can be located between the logic die and the plurality of silicon dies for lateral thermal spreading. The dummy die can have, for example, a thermal conductivity of about 120 W/mK to about 400 W/mK at room temperature (e.g., about 150 W/mK to about 350 W/mK).

The dummy die170can be attached to both the logic die150and the die stacks110via solder. For example, solder thermal interface material (sTIM) or other highly thermally conductive materials can be used to bond dummy die170to logic die150and die stack110to allow for thermal spreading.

Inserting a dummy die170between logic die150and die stack110allows for spread of heat through device100. This is due in part to the high thermal conductivity of silicon (or silicon carbide) that dummy die160is made of Spreading of heat throughout device100can minimize formation of hot spots that is common in conventional 3D stacked ICs. Moreover, the use of dummy die170can reduce the maximum temperature on logic die150and/or memory die stack110.

In an alternative embodiment,FIG. 2illustrates a schematic view of a semiconductor device including a 3D stacked IC200with a die stack210with individual dies220and interface layers230, interconnect240, logic die250, power source260, dummy die270, and substrate280. Device200can run at a total stack power from about 0.00 W to about 100.0 W (e.g., about 15.0 W to about 19.0 W or about 16.0 W to about 18.0 W).

In device200, power source260is electrically coupled to logic die250, which is electrically coupled via interconnect240to die stack210. Die stack210includes individual dies220separated by interface layers230, and electrically connected via interconnect240. Logic die4040250is sitting on substrate280, with dummy die270therebetween. Die stack210with individual dies220, interface layers230, interconnect240, logic die250, and power source260are similar to the corresponding components as discussed with reference toFIG. 1.

Dummy die270in device200can be made of, for example, silicon, silicon carbide, or other appropriate thermally conductive material with optional passive circuitry, such as, for example, boron nitride, diamond, or boron arsenide. Overall size and thickness of dummy die270can vary depending on power from power source260, size and material of logic die250, and overall heat dispersion needs. The dummy die can have, for example, a thermal conductivity of about 120 W/mK to about 400 W/mK at room temperature.

In device200, the dummy die270can be located between the logic die and substrate180for lateral thermal spreading. Substrate280can be, for example, a substrate for hosting device200. The dummy die270can be attached to both the logic die250and the substrate280via solder. For example, solder thermal interface material (sTIM) or other highly thermally conductive materials can be used to bond dummy die270to logic die250and substrate280to allow for thermal spreading.

Inserting a dummy die270between logic die250and substrate280allows for spreading of heat through device200. This is due in part to the high thermal conductivity of silicon (or silicon carbide) that dummy die260is made of. Spreading of heat throughout device200can minimize formation of hot spots that is common in conventional 3D stacked ICs

HBM DRAM embodiments of devices with dummy dies showed constant silicon dummy dies had a thermal conductivity of 120 W/mK, while silicon carbide dummy dies had a thermal conductivity of 300 W/mK at room temperature. At increased temperatures, the thermal conductivity of both silicon and silicon carbide increased, giving additional thermal management benefits.

Using thermal imaging, hot spots were observed in HBM DRAM device samples without dummy dies, and particularly appeared at a high temperature gradients with hot spots appearing in small regions. In contrast, with the added dummy die of silicon carbide, the heat was spread out from the hot spot.

During testing of embodiments of HBM DRAM device samples with dummy dies, a reduced threshold junction temperature (threshold Tj, e.g., a highest operating temperature of a semiconductor) was observed compared to prior art devices without a dummy die. HBM DRAM devices with a silicon dummy die showed an average Tj of 4-5° C. lower compared to devices without dummy dies. HBM DRAM devices with a silicon carbide dummy die showed an average Tj of 8-10° C. lower compared to devices without dummy dies.

The devices with the dummy die placed between the HBM logic die and the DRAM die stack showed an average Tj of 4-8° C. lower compared to devices without dummy dies. The devices with the dummy die placed between the HBM logic die and a substrate showed an average Tj of 5-10° C. lower compared to devices without dummy dies.

Overall, devices with a dummy die, such as the embodiments shown as devices100and200, can have a reduced junction temperature while maintaining total package power, increasing overall performance. During side by side testing, up to ten degrees Celsius reduction was achieved while maintaining package power. Alternatively, the power of the device package can be comparatively higher while maintaining the original junction temperature.

FIG. 3illustrates a method300for manufacturing the semiconductor device. Optionally, all dies (i.e., logic die, die stack, dummy die), can be configured to include active or passive circuitry and/or cut as needed prior to stacking.

The die stack can then be prepared by alignment and stacking of individual dies as needed to begin creating the 3D stack. For example, the dies can be joined by interface layers such as solder, thermal bumps, epoxy-based materials, or other materials as known in the art.

Then, in step310, the 3D stacked die stack can be electrically coupled to the logic die. This can be done, for example, with wire bonding, stair stepping, through silicon vias, vertical interconnects, or other interconnects as appropriate in the art.

Next, in step320the dummy die can be attached to the logic die. For example, this can be done by applying solder TIM or other thermally conductive attachment material to the dummy die and the logic die so as to thermally couple the two dies. Finally, in step330, a power source can be electrically coupled to the logic die by methods such as wire bonding or other electrically conductive methods. In some embodiments, the power source is part of the circuitry on and integrated with the logic die.

FIG. 5illustrates a system level diagram, depicting an example of an electronic device (e.g., system) that may include the device and/or methods described above. In one embodiment, system400includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system600includes a system on a chip (SOC) system.

In one embodiment, processor410has one or more processor cores412and412N, where412N represents the Nth processor core inside processor410where N is a positive integer. In one embodiment, system400includes multiple processors including410and505, where processor505has logic similar or identical to the logic of processor410. In some embodiments, processing core412includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor410has a cache memory416to cache instructions and/or data for system400. Cache memory416may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor410includes a memory controller414, which is operable to perform functions that enable the processor410to access and communicate with memory430that includes a volatile memory432and/or a non-volatile memory434. In some embodiments, processor410is coupled with memory430and chipset420, such as the 3D stacked ICs100,200, or other chipsets including a dummy die described herein. Processor410may also be coupled to a wireless antenna478to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna478operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra-Wide Band (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

In some embodiments, volatile memory432includes, but is not limited to, Synchronous Dynamic Random-Access Memory (SDRAM), Dynamic Random-Access Memory (DRAM), RAMBUS Dynamic Random-Access Memory (RDRAM), and/or any other type of random-access memory device. Non-volatile memory434includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory430stores information and instructions to be executed by processor410. In one embodiment, memory430may also store temporary variables or other intermediate information while processor410is executing instructions. In the illustrated embodiment, chipset420connects with processor410via Point-to-Point (PtP or P-P) interface layers517and422. Chipset420enables processor410to connect to other elements in system400. In some embodiments of the example system, interface layers517and422operate in accordance with a PtP communication protocol such as the Intel® Quick Path Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset420is operable to communicate with processor410,505N, display device440, and other devices, including a bus bridge572, a smart TV476, I/O devices574, nonvolatile memory460, a storage medium (such as one or more mass storage devices)462, a keyboard/mouse464, a network interface466, and various forms of consumer electronics477(such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset420couples with these devices through an interface424. Chipset420may also be coupled to a wireless antenna478to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.

Chipset420connects to display device440via interface426. Display440may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor410and chipset420are merged into a single SOC. In addition, chipset420connects to one or more buses450and455that interconnect various system elements, such as I/O devices574, nonvolatile memory460, storage medium462, a keyboard/mouse464, and network interface466. Buses450and455may be interconnected together via a bus bridge572.

While the modules shown inFIG. 4are depicted as separate blocks within the system400, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory416is depicted as a separate block within processor410, cache memory416(or selected aspects of416) can be incorporated into processor core412.

EXAMPLES

To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:

Example 1 includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon.

Example 2 includes the semiconductor device of example 1, wherein the plurality of dies are attached to each other through a plurality of interface layers.

Example 3 includes the semiconductor device of examples 1-2, wherein the plurality of dies comprise a die stack.

Example 4 includes the semiconductor device of examples 1-3, wherein the plurality of dies are coupled to the logic die by one or more wire bonds.

Example 5 includes the semiconductor device of examples 1-4, wherein plurality of dies are coupled to the logic die by one or more through silicon vias.

Example 6 includes the semiconductor device of examples 1-5, wherein the logic die is a high bandwidth memory die.

Example 7 includes the semiconductor device of examples 1-6, wherein the dummy die comprises silicon, silicon carbide, boron nitride, diamond, boron arsenide, or combinations thereof.

Example 8 includes the semiconductor device of examples 1-7, wherein the dummy die is attached to the logic die by solder, thermal bumps, electrical bumps, a metallic interface, an epoxy-based material, an underfill, or combinations thereof.

Example 9 includes the semiconductor device of examples 1-8, wherein the dummy die is located between the logic die and the plurality of dies.

Example 10 includes the semiconductor device of examples 1-9, wherein the dummy die is attached to the plurality of dies by solder, thermal bumps, electrical humps, a metallic interface, an epoxy-based material, an underfill, or combinations thereof.

Example 11 includes the semiconductor device of examples 1-10, wherein the dummy die has a thermal conductivity of about 120 W/mK to about 400 W/mK at room temperature.

Example 12 includes the semiconductor device of examples 1-11, further comprising a power source coupled to the logic die.

Example 13 includes the semiconductor device of examples 1-12, wherein the power source provides power of about 6.0 W to about 9.0 W.

Example 14 includes the semiconductor device of examples 1-13, wherein the power source provides power of about 7.0 W to about 8.0 W.

Example 15 includes the semiconductor device of examples 1-14, wherein the semiconductor device has a power of from about 15.0 W to about 19.0 W.

Example 16 includes the semiconductor device of examples 1-15, wherein the semiconductor device has a power of from about 16.0 W to about 18.0 W.

Example 17 includes a semiconductor device including a die stack comprising a plurality of dies, a logic die coupled to the die stack by an interconnect, a power source coupled to the logic die and configured to produce heat, and a dummy die attached to the logic die, the dummy die configured to spread the heat produced by the power source.

Example 18 includes the device of Example 17, wherein the dummy die comprises one or more through silicon vias and no other electrical components.

Example 19 includes a system comprising a motherboard, a display device electrically connected to the motherboard, an antenna electrically connected to the motherboard, and a semiconductor device coupled to the motherboard including a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon.

Example 20 includes a method of manufacturing a semiconductor device comprising coupling a three-dimensional stacked integrated circuit to a logic die, attaching a dummy die to the logic die, and coupling a power source to the logic die.