Hardware module for determining a clock value based on multiple timing references

A hardware module includes a high stability oscillator, a satellite signal receiver, a processor, and electrical contacts. The high stability oscillator is configured to provide a first timing reference output. The satellite signal receiver is configured to receive signals transmitted by location positioning satellites and provide a second timing reference output. The processor is configured to use the first timing reference output from the high stability oscillator and the second timing reference output from the satellite signal receiver to determine an absolute physical hardware clock value and provide the absolute physical hardware clock value to a host system. The electrical contacts are configured to allow the hardware module to be electrically and physically coupled to and removable from the host system as a single physical module.

BACKGROUND OF THE INVENTION

Computer network time synchronization involves distributing time values to computer devices in different spatial locations. Synchronization may be required for financial transactions, telecommunications transmissions, sensor data collection, and various other applications. Various synchronization protocols can be used. For example, network time protocol (NTP) and precision time protocol (PTP) may be utilized to synchronize clocks of a computer network. Oftentimes, one or more high-precision clocks are required for synchronization of a computer network. Such clocks may be referred to as master clocks, grandmasters, time providers, or other similar terms. Master clocks are oftentimes bulky, specialized, and expensive. Thus, it would be beneficial to develop computer network clock hardware technology that is more compact, adaptable, and cost effective.

DETAILED DESCRIPTION

A hardware module includes a high stability oscillator, a satellite signal receiver, a processor, and electrical contacts. The high stability oscillator is configured to provide a first timing reference output. The satellite signal receiver is configured to receive signals transmitted by location positioning satellites and provide a second timing reference output. The processor is configured to use the first timing reference output from the high stability oscillator and the second timing reference output from the satellite signal receiver to determine an absolute physical hardware clock value and provide the absolute physical hardware clock value to a host system. The electrical contacts are configured to allow the hardware module to be electrically and physically coupled to and removable from the host system as a single physical module.

A technological advantage of the hardware module disclosed herein is flexibility to include different types and different numbers of timing reference sources, such as multiple high-stability oscillators and/or Global Navigation Satellite System (GNSS) timing reference sources. In various embodiments, the hardware module is compact and does not include a network interface controller (NIC) and thus is flexible in terms of being compatible with various types of host systems. Another technological advantage is adaptability to support various network connection speeds and communications protocols. In various embodiments, there is flexibility to perform different types of clock filtering operations by utilizing a field-programmable gate array (FPGA). As described in further detail herein, the hardware module disclosed herein has an advantageous small form factor (e.g., a computer device card form) that allows it to be slotted into many types of computer host systems. Thus, high-precision timing can be provided for various host computer systems through a small timing card form factor, which is superior to approaches that involve bulky and expensive standalone time providers that cannot be incorporated into host computer systems.

The hardware module disclosed herein can be utilized as a grandmaster clock in a PTP computer network. As described in further detail herein, in various embodiments, high-precision time for accurate PTP synchronization is provided by a GNSS receiver coupled with fault tolerance holdover provided by an atomic clock. In various embodiments, the hardware module includes a high stability oscillator (e.g., an atomic clock), a GNSS receiver, an FPGA (for high stability oscillator and GNSS signal processing and general processing), and other supporting components. In various embodiments, the hardware module is configured to be able to be plugged into a host computer system, which recognizes the hardware module as a time provider device card.

FIG.1is a block diagram illustrating an embodiment of a hardware module for providing physical hardware clock values. In the example illustrated, hardware module100includes satellite signal receiver102, high stability oscillator104, processor106, and electrical contacts108.

In various embodiments, satellite signal receiver102is a GNSS receiver. GNSS refers to satellite-based radionavigation providing geolocation and time information to receivers (GNSS receivers) located on or near the Earth. The Global Positioning System (GPS) is a widely known example of a GNSS. Other examples include GLONASS, BeiDou, and Galileo. A GNSS includes three primary components: satellites that broadcast satellite position and time information, ground stations that monitor and manage the operational health of the satellites, and receivers (on or near the Earth) that listen for satellite broadcasted information to utilize to calculate receiver position and time. GNSS satellites carry stable atomic clocks that are synchronized with one another and with ground clocks. Each satellite transmits a radio signal including time and three-dimensional position information. A receiver that receives information from multiple satellites can utilize the information to solve equations governing receiver position and time. Typically, the receiver utilizes information from at least four satellites, corresponding to solving for four dimensions—three spatial dimensions as well as time. Solving for time (e.g., a current time common to all the GNSS satellites) for receivers in different locations results in time synchronization of the different receivers. Satellite signal receiver102is coupled to a physical antenna (not shown inFIG.1) that provides signals for satellite signal receiver102to process. The antenna intercepts radio waves propagating through space in order to produce an electric current at its terminals. The antenna can include a low noise amplifier that increases the strength of received signals. Examples of antenna types include patch and quad helix antennas. The antenna is tuned to frequencies transmitted by satellites it is listening to.

Satellite signal receiver102processes signals received by an antenna. In some embodiments, satellite signal receiver102estimates its current position on Earth (e.g., reporting latitude, longitude, and elevation coordinates) and a time offset between an internal receiver clock and GNSS time (e.g., atomic clock time of satellites of a satellite system). In some embodiments, the time offset is utilized to synchronize satellite signal receiver102's internal clock with the atomic clocks of a GNSS. In some embodiments, processing to estimate satellite signal receiver102's position on Earth and the time offset is performed by electronic circuits and/or software of satellite signal receiver102. For example, an application-specific integrated circuit (ASIC) of satellite signal receiver102may be configured to perform the position and time calculations. In various embodiments, satellite signal receiver102includes a (pulse per second) PPS generator configured to output a periodic waveform (e.g., a square wave) aligned with GNSS time. For example, the PPS generator can be configured to output a square wave at the exact start of each second of time kept by atomic clocks of a GNSS. The PPS generator can be driven by a reference oscillator of satellite signal receiver102(e.g., a quartz oscillator) or a reference oscillator connected to satellite signal receiver102. A signal with a period of one second (or with another period) can be generated from the reference oscillator using electronic divider circuits. In some embodiments, time that is calculated by satellite signal receiver102to correspond to GNSS time is utilized to adjust the reference oscillator frequency and/or phase to cause a waveform (e.g., a square wave) associated with the reference oscillator to align with the start of each second of time kept by the GNSS. In various embodiments, satellite signal receiver102outputs a time of day (TOD) corresponding to GNSS time. In the example illustrated, satellite signal receiver102provides information (e.g., a PPS signal and TOD) to processor106.

In the example illustrated, high stability oscillator104also provides information to processor106. In various embodiments, high stability oscillator104is a significantly more precise clock/oscillator than what a typical computer possesses (e.g., a piezoelectric crystal oscillator). In some embodiments, high stability oscillator104is an atomic clock. Examples of high stability oscillator104include: cesium, rubidium, hydrogen maser, oven-controlled crystal oscillator (OCXO), double oven-controlled crystal oscillator (DOCXO), cesium fountain, and other clocks. GNSS signals (and thus satellite signal receiver102) provide superior long-term stability and high stability oscillators (and thus high stability oscillator104) provide superior short-term stability. Thus, utilizing both timing sources combines long-term stability and short-term stability to provide superior overall stability. In various embodiments, when GNSS signals become unavailable, high stability oscillator104provides for a holdover state. Various scenarios can require the holdover state. For example, satellite signal receiver102may be jammed (e.g., disrupted by deliberate use of radio transmissions to prevent listening to broadcasts from a satellite system), spoofed (e.g., fed incorrect signals intended to be mistaken for actual signals from a satellite system), or otherwise interfered with (e.g., from electronic noise emitted by other electronic devices operating legally in the same vicinity). It is also possible, though rare, for a GNSS to fail (e.g., due to a solar flare, maintenance, etc.). Stated alternatively, in some scenarios, information from satellite signal receiver102may be unreliable. As used herein, an outage (also referred to herein as a GNSS outage, satellite outage, satellite signal reception outage, etc.) refers to any scenario (e.g., jamming, spoofing, interference, etc.) in which satellite signal receiver102cannot reliably provide accurate time information. Satellite signal receiver102communicates to processor106when there is an outage event (e.g., when satellite signal receiver102does not receive a strong enough signal to process or receives a signal that falls outside of normal signal parameters). Processor106determines there is an outage event if satellite signal receiver102reports an outage event.

In the example illustrated, satellite signal receiver102and high stability oscillator104are communicatively connected to processor106. Processor106includes logic that disciplines high stability oscillator104. As used herein clock disciplining (or simply disciplining) refers to controlling the output of high stability oscillator104to agree with the signals received by satellite signal receiver102. Hardware for clock disciplining is described in further detail herein (e.g., seeFIG.3). Processor106also includes logic to route and select the signals from satellite signal receiver102and high stability oscillator104to output to a host computer system. For example, in a normal operation mode, time from satellite signal receiver102can be outputted; whereas, during an outage associated with satellite signal receiver102, time from high stability oscillator104can be outputted. In some embodiments, satellite signal receiver102provides PPS and TOD signals that processor106passes to the host computer system during normal operation. Processor106also handles PPS and TOD signals from high stability oscillator104, which are sent to the host computer system during satellite signal reception outages. In various embodiments, processor106is programmed to detect satellite signal reception outages. In some embodiments, hardware module100includes multiple satellite signal receivers and/or multiple high stability oscillators and processor106selects from among them (e.g., processor106can be programmed with a selection heuristic). Various PPS inputs/outputs and oscillator inputs/outputs can also be included on hardware module100, which processor106can also handle. Stated alternatively, processor106processes/routes timing traffic. In some embodiments, processor106is an FPGA. The FPGA can be programmed with customized filtering operations. Alternative hardware implementations of processor106are also possible, e.g., as an ASIC or central processing unit (CPU).

In the example illustrated, electrical contacts108allow hardware module100to physically connect to a host computer system. In various embodiments, hardware module100slots into the host computer system and is coupled using electric contacts108. In some embodiments, electrical contacts108includes one or more SMA (SubMiniature version A) connectors. Other examples of connection interfaces that can be included in electrical contacts108include USB, DVI, VGA, serial, serial/parallel, and various other connector types. An example of a host computer system is shown inFIG.6. In the example illustrated, hardware module100does not include a network card (e.g., a NIC). In various embodiments, the network card (e.g., the NIC) is included as part of the host computer system to which hardware module100attaches. As used herein, NIC refers to a computer hardware component that connects a computer to a computer network. NICs may also be referred to as network interface cards, network adapters, local area network (LAN) adapters, physical network interfaces, or other similar terms. NICs implement the electronic circuitry needed to communicate among computers in a network (e.g., a LAN). Computers in a network can be synchronized by synchronizing the NICs of the computers.

In some embodiments, the host computer system that incorporates hardware module100serves as a master clock device utilized to synchronize time in a network of clock devices (e.g., seeFIG.5). NTP and PTP are commonly used protocols to synchronize clocks throughout a computer network. PTP, due to its higher accuracy, is more suitable for applications that require high precision. NTP, though, is typically easier to implement and may be more appropriate for applications that do not require the precision of PTP. PTP has been published as the IEEE-1588 standard. In various scenarios, PTP is implemented as a packet-based synchronization protocol using Ethernet connections. PTP's increased accuracy (compared to NTP) is a result of hardware time stamping and a servo mechanism to continuously reduce timing error. PTP utilizes hardware timestamping that accounts for device latency (e.g., amount of time that synchronization messages stay in a device).

In the example shown, portions of the communication path between the components are shown. Other communication paths may exist, and the example ofFIG.1has been simplified to illustrate the example clearly. Although single instances of components have been shown to simplify the diagram, additional instances of any of the components shown inFIG.1may exist. For example, more satellite signal receivers and/or high stability oscillators may exist. The number of components and the connections shown inFIG.1are merely illustrative. Components not shown inFIG.1may also exist.

FIG.2is a block diagram illustrating an embodiment of a system for processing multiple timing reference outputs to determine a physical hardware clock value. In some embodiments, processor200is processor106ofFIG.1. Processor200may also be described as a processing unit, logic unit, etc. In the example illustrated, processor200includes selector unit202, clock disciplining unit204, clock value unit206, TOD unit208, and bridge unit210. Inputs to processor200include oscillator source(s)212, PPS input(s)214, and GNSS TOD216. In the example shown, PPS output218is an output of processor200. In some embodiments, at least a portion of processor200is implemented as digital logic gates. For example, at least a portion of processor200may be implemented as digital logic gates of an FPGA. The various units of processor200refer to different functional units that can be implemented with different collections of digital logic. It is also possible for at least a portion of processor200to be implemented as an ASIC or CPU.

In the example illustrated, selector unit202receives oscillator source(s)212. Selector unit202selects from potentially multiple oscillator sources. In various embodiments, oscillator source(s)212includes high stability oscillator104ofFIG.1. It is also possible for other oscillators to be available for selection (e.g., an oscillator external to hardware module100ofFIG.1that is fed into hardware module100ofFIG.1, such as a large, heavy cesium clock that cannot fit on hardware module100ofFIG.1). In the example shown, the output of selector unit202(the selected oscillator signal) is received by clock disciplining unit204. In various embodiments, clock disciplining unit204aligns the selected oscillator source (the output of selector unit202) to agree with a PPS signal that is selected by clock disciplining unit204from among PPS input(s)214. In some embodiments, clock discipling unit204includes filtering logic, control logic, and a digital phase-locked loop (DPLL). Clock disciplining hardware is described in further detail herein (e.g., seeFIG.3). In some embodiments, a PPS signal from satellite signal receiver102ofFIG.1is included in PPS input(s)214. It is also possible for other PPS signals to be available for selection by clock disciplining unit204(e.g., from a GNSS source external to hardware module100ofFIG.1). In various embodiments, during a normal operation mode, a GNSS PPS signal (e.g., from satellite signal receiver102ofFIG.1) is utilized as both a signal sent to a host computer system to be used for time synchronization (e.g., of other computer devices in a computer network) as well as a disciplining signal for a high stability oscillator (to align the time of the high stability oscillator with the GNSS PPS signal). By utilizing the GNSS PPS signal to discipline the high stability oscillator signal, during an outage of the GNSS PPS signal, the high stability oscillator signal will be ready to use in a holdover state because it is already aligned with the GNSS PPS signal. Thus, the high stability oscillator signal serves as a backup to ensure continuous, uninterrupted provision of precision time. Because the high stability oscillator signal typically has superior short-term stability (e.g., from a highly stable atomic clock), accurate time can be kept during GNSS outages, which are typically of a short duration relative to the stability window of the high stability oscillator.

In various embodiments, clock value unit206provides a current time value to clock discipling unit204that clock discipling unit204utilizes to output an updated time value. In the example shown, clock value unit206receives the current time value from TOD unit208. Clock value unit206keeps a digital record of time. For example, clock value unit206can be configured to have a time resolution of 80 bits, of which 32 bits are used for sub-second time. The various bits for recording time can be stored in hardware registers that are constantly updated. In some embodiments, clock disciplining unit204adds or subtracts a difference value (difference in time between a GNSS PPS signal and a high stability oscillator signal) to the current time value provided by clock value unit206to arrive at a new output time value that is sent to TOD unit208. The new output time value (plus a time increment corresponding to how often clock value unit206updates) corresponds to the current time value that is inputted to clock disciplining unit204(via clock value unit206) in the next loop of disciplining. In the example shown, clock disciplining unit204, clock value unit206, and TOD unit208form a loop that acts to minimize error between a high stability oscillator and GNSS time.

In the example illustrated, TOD unit208receives GNSS TOD216. Stated alternatively, TOD unit208receives time of day information from a GNSS source that it can pass on to a host computer system (information pathway not shown inFIG.2) during normal operation (absence of a GNSS related outage). By receiving an output from clock disciplining unit204, TOD unit208can also pass on to the host computer system (information pathway not shown inFIG.2) time information from the high stability oscillator that aligns with the GNSS source in the event that a GNSS outage occurs. In some embodiments, PPS output218is the output passed to the host computer system. PPS output218corresponds to the current time possessed by clock value unit206, which accurately aligns with GNSS time as long as clock disciplining is successfully performed by clock disciplining unit204. In some embodiments, PPS output218is received by a NIC of the host computer system.

In the example illustrated, selector unit202, clock disciplining unit204, clock value unit206, and TOD unit208are communicatively connected with bridge unit210. In various embodiments, bridge unit210controls configuration settings associated with selector unit202, clock disciplining unit204, clock value unit206, and TOD unit208. For example, bridge unit210may determine which oscillator source is selected by selector unit202and direct clock disciplining unit204to perform a specific type of filtering. In some embodiments, a host computer system provides control inputs through bridge unit210. In some embodiments, bridge unit210is a peripheral component interconnect (PCI) bridge, such as a PCI express (PCIe) bridge. Stated alternatively, in some embodiments, processor200is part of a hardware module that is a PCI (e.g., PCIe) device. For example, in some embodiments, hardware module100ofFIG.1is a PCIe device, of which processor200is a component. Thus, in some embodiments, hardware module100ofFIG.1is connected to a host computer system through the PCIe standard and/or processor200communicates with the host computer system through the PCIe standard.

In the example shown, portions of the communication path between the components are shown. Other communication paths may exist, and the example ofFIG.2has been simplified to illustrate the example clearly. Although single instances of components have been shown to simplify the diagram, additional instances of any of the components shown inFIG.2may exist. The number of components and the connections shown inFIG.2are merely illustrative. Components not shown inFIG.2may also exist. For example, direct connections between TOD unit208to a host computer system may exist.

FIG.3is a block diagram illustrating an embodiment of a system for disciplining a clock. In some embodiments, clock disciplining unit300is clock disciplining unit204ofFIG.2. In the example illustrated, clock disciplining unit300includes selector unit302, control unit304, difference unit306, filtering and multiplier308, and DPLL310, which includes adder unit312. Inputs to clock disciplining unit300include PPS signal(s)314, control signals316, oscillator signal318, and clock value320. In the example shown, next clock value322is an output of clock disciplining unit300. In some embodiments, at least a portion of clock disciplining unit300is implemented as digital logic gates, e.g., as digital logic gates of an FPGA. The various units of clock disciplining unit300refer to different functional units that can be implemented with different collections of digital logic. It is also possible for at least a portion of clock disciplining unit300to be implemented as an ASIC or CPU.

In the example illustrated, selector unit302receives PPS signal(s)314. Selector unit302selects from potentially multiple sources of PPS signal sources. In some embodiments, PPS signal(s)314corresponds to PPS input(s)214ofFIG.2. In some embodiments, control unit304directs selection of a PPS signal based on control signals316. In some embodiments, control signals316include signals from bridge unit210ofFIG.2. Control signals316may also include information outputted by control unit304, e.g., status information of selector unit302or other units to which control unit304can be connected, such as difference unit306, filtering and multiplier308, and DPLL310(connections not shown inFIG.3).

Selector unit302routes a selected PPS signal (e.g., a GNSS signal, such as from satellite signal receiver102ofFIG.1) as one of the inputs to difference unit306. The other input to difference unit306is a filtered and multiplied form of oscillator signal318. In some embodiments, oscillator signal318is from an oscillator source selected by selector unit202ofFIG.2. In the example illustrated, oscillator signal318is received by filtering and multiplier308. In various embodiments, filtering and multiplier308performs filtering of oscillator signal318to smooth and/or reduce noise of oscillator signal318. Examples of filtering techniques that may be performed include direction cosine matrix (DCM), Kalman, and other filtering techniques. In various embodiments, the filtering is programmable and customizable by a user, such as when clock disciplining unit300is implemented on an FPGA (e.g., programming instructions from a host system can be received). In some embodiments, filtering control occurs through control signals316(connections not shown inFIG.3). In various embodiments, oscillator signal318is multiplied by filtering and multiplier308. For example, if oscillator signal318is a 10-megahertz (MHz) signal, it may be multiplied by a factor of 12.5 to create a 125 MHz signal. This multiplication results in a smaller period for the oscillator signal, which allows for finer time increments. For a 125 MHz signal, the period is 8 nanoseconds (ns).

In the example illustrated, difference unit306is communicatively connected to DPLL310. In various embodiments, difference unit306sends a PPS difference value to DPLL310. The PPS difference value is the difference between the selected PPS signal from selector unit302and the output of filtering and multiplier308. If the output of filtering and multiplier308is precisely aligned with the PPS signal, the PPS difference value would be 0 ns. With the example 125 MHz signal given above, corresponding to a period of 8 ns, the maximum PPS difference value would be 8 ns. The PPS difference value is utilized by adder unit312. Adder unit312combines the PPS difference value with clock value320to determine next clock value322. In some embodiments, clock value320is a current clock value outputted by clock value unit206ofFIG.2. Thus, adder unit312corrects the current clock value with the PPS difference value. In some embodiments, next clock value322corresponds to the output of clock disciplining unit204ofFIG.2that is sent to TOD unit208ofFIG.2. The next clock value depends on the period of the system clock. For the example of a 125 MHz clock, the next clock value is equal to the corrected current clock value plus the time of one period of the system clock, e.g., 8 ns.

Difference unit306also sends the multiplied oscillator signal (e.g., at 125 MHz) to DPLL310to drive oscillations of DPLL310. In various embodiments, DPLL310is an all-digital phase-locked loop (ADPLL) in which a numerically-controlled oscillator (NCO) serves as a digital signal generator to create a synchronous, discrete-time, discrete-valued representation of a periodic waveform. In some embodiments, the PPS difference value is utilized by DPLL310to adjust its oscillation frequency. For example, for the 125 MHz (8 ns period) example, the oscillation period can be adjusted up or down (e.g., to 8.1 ns or 7.9 ns) to decrease the PPS difference value for a next iteration of determining next clock value322. Such an adjustment can be made adaptively until the PPS difference value is zero or falls below a specified threshold. It is also possible to perform this adjustment by altering the frequency or period at filtering and multiplier308before or after multiplication. In some embodiments, control unit304provides control signals to filtering and multiplier308and/or DPLL310to configure adjustments to oscillation frequency or period (e.g., provide a heuristic or algorithm for the adjustments). In the example illustrated, adder unit312is included in DPLL310. It is also possible for adder unit to be separate from but communicatively connected to DPLL310. An advantage of a DPLL (e.g., as implemented on an FPGA) is compactness, which is advantageous for implementing a timing card in a hardware module (e.g., hardware module100ofFIG.1) that can be slotted into a host computer system.

In the example shown, portions of the communication path between the components are shown. Other communication paths may exist, and the example ofFIG.3has been simplified to illustrate the example clearly. Although single instances of components have been shown to simplify the diagram, additional instances of any of the components shown inFIG.3may exist. The number of components and the connections shown inFIG.3are merely illustrative. Components not shown inFIG.3may also exist.

FIG.4is a flow chart illustrating an embodiment of a process for utilizing multiple timing reference outputs to determine a physical hardware clock value. In some embodiments, the process ofFIG.4is performed by hardware module100ofFIG.1.

At402, a first timing reference output is provided. In some embodiments, the first timing reference output is provided by a high stability oscillator (e.g., high stability oscillator104ofFIG.1). In some embodiments, the first timing reference output is a periodic signal at a specified oscillation frequency.

At404, one or more signals transmitted by one or more location positioning satellites are received and a second timing reference output is provided. In some embodiments, the signals are received by satellite signal receiver102ofFIG.1. In some embodiments, satellite signal receiver102ofFIG.1processes the satellite (e.g., GNSS) signals into the second timing reference output. In some embodiments, the second timing reference output includes TOD information and a PPS signal.

At406, the first timing reference output and the second timing reference output are used to determine an absolute physical hardware clock value and the absolute physical hardware clock value is provided to a host system. The clock value is a physical hardware clock value because it is provided by a hardware source (e.g., hardware module100ofFIG.1). The clock value is absolute in the sense that it is a time value that is not relative to a standardized time value but rather the standardized time value itself (e.g., a GNSS time value). In various embodiments, the clock value is a GNSS time value or a time value from a high stability oscillator that has been aligned to GNSS time. Thus, the time value corresponds to a standardized time that can be considered an absolute (not relative) time value. In some embodiments, processor106ofFIG.1and/or processor200ofFIG.2processes the first timing reference output and the second timing reference output. In various embodiments, in scenarios in which the second timing reference output is determined to be reliable (e.g., during normal operation in the absence of a satellite related outage), the second timing reference output is transmitted to the host system (the second timing reference output oftentimes includes TOD information that can be directly transmitted to the host system) and the second timing reference output is used to discipline the first timing reference output. In some embodiments, clock disciplining unit204ofFIG.2and/or clock disciplining unit300ofFIG.3aligns the first timing reference output to match the second timing reference output. In various embodiments, in scenarios in which the second timing reference output is determined to be unreliable (e.g., during a satellite related outage), the first timing reference output is used (e.g., in a holdover state) to provide absolute physical hardware clock values. In some embodiments, a physical hardware clock updates itself according to oscillations of the first timing reference output. When the first timing reference output is aligned with the second timing reference output, clock values as accurate as those associated with the second timing reference output can be provided by utilizing the first timing reference output even when there is an outage associated with the second timing reference output. In some embodiments, the host system is computer system600ofFIG.6. In various embodiments, a processor performing406is part of a hardware module that includes electrical contacts (e.g., electrical contacts108ofFIG.1) configured to allow the hardware module to be electrically and physically coupled to and removable from the host system as a single physical module.

FIG.5is a diagram illustrating an embodiment of clock devices connected via a network. In system500, master clock device504and clock devices506,508,510, and512are communicatively connected to one another through network502. The number of clock devices shown is merely illustrative. It is possible for there to be fewer or more clock devices in system500. Examples of network502include one or more of the following: a direct or indirect physical communication connection, mobile communication network, Internet, intranet, Local Area Network, Wide Area Network, Storage Area Network, and any other form of connecting two or more systems, components, or storage devices together. In some embodiments, master clock device504is a computer system that includes hardware module100ofFIG.1. In some embodiments, the clock devices are computers with NICs. For example, physical hardware clocks (PHCs) located on NICs can be utilized to keep time. In various embodiments, each PHC generates internal hardware clock values corresponding to the time kept by the PHC. In various embodiments, the PHC is an integrated circuit clock, such as a silicon-based or quartz crystal-based oscillator. In some embodiments, PHCs utilize 80-bit counters (80 binary digits), of which 32 bits measure sub-second time.

In various embodiments, the clocks in system500exhibit timing errors that are remedied with a network synchronization protocol such as NTP, PTP, or another protocol. In the example illustrated, master clock device504serves as a master clock against which other clocks are synchronized. The master clock device may be referred to as a grandmaster, time provider, or another similar term. The grandmaster is oftentimes a clock that is of higher quality and is more accurate than the other clocks. Clocks other than the grandmaster can be ordinary clocks (non-grandmaster clocks with a single network connection, also referred to as slaves), boundary clocks (clocks with multiple network connections that can synchronize one network segment to another), or transparent clocks (clocks that modify messages passing through and can measure and adjust for network delays). The clock devices in system500may be communicatively connected in a variety of different topologies. The types of clock devices in system500may also vary.

FIG.6is a functional diagram illustrating a programmed computer system. In some embodiments, computer system600is a host computer system that includes hardware module100ofFIG.1.

In the example shown, computer system600includes various subsystems as described below. Computer system600includes at least one microprocessor subsystem (also referred to as a processor or a central processing unit (CPU))602. For example, processor602can be implemented by a single-chip processor or by multiple processors. In some embodiments, processor602is a general-purpose digital processor that controls the operation of computer system600. Using instructions retrieved from memory610, processor602controls the reception and manipulation of input data, and the output and display of data on output devices (e.g., display618).

Persistent memory612(e.g., a removable mass storage device) provides additional data storage capacity for computer system600, and is coupled either bi-directionally (read/write) or uni-directionally (read only) to processor602. For example, persistent memory612can also include computer-readable media such as magnetic tape, flash memory, PC-CARDS, portable mass storage devices, holographic storage devices, and other storage devices. A fixed mass storage620can also, for example, provide additional data storage capacity. The most common example of fixed mass storage620is a hard disk drive. Persistent memory612and fixed mass storage620generally store additional programming instructions, data, and the like that typically are not in active use by the processor602. It will be appreciated that the information retained within persistent memory612and fixed mass storages620can be incorporated, if needed, in standard fashion as part of memory610(e.g., RAM) as virtual memory.

In addition to providing processor602access to storage subsystems, bus614can also be used to provide access to other subsystems and devices. As shown, these can include a display monitor618, a network interface616, a keyboard604, and a pointing device606, as well as an auxiliary input/output device interface, a sound card, speakers, and other subsystems as needed. For example, pointing device606can be a mouse, stylus, track ball, or tablet, and is useful for interacting with a graphical user interface.

Network interface616allows processor602to be coupled to another computer, computer network, or telecommunications network using a network connection as shown. For example, through network interface616, processor602can receive information (e.g., data objects or program instructions) from another network or output information to another network in the course of performing method/process steps. Information, often represented as a sequence of instructions to be executed on a processor, can be received from and outputted to another network. An interface card or similar device and appropriate software implemented by (e.g., executed/performed on) processor602can be used to connect computer system600to an external network and transfer data according to standard protocols. Processes can be executed on processor602, or can be performed across a network such as the Internet, intranet networks, or local area networks, in conjunction with a remote processor that shares a portion of the processing. Additional mass storage devices (not shown) can also be connected to processor602through network interface616. In some embodiments, network interface616is coupled to hardware module100ofFIG.1so that timing information provided by hardware module100ofFIG.1can be distributed by network interface616to other devices via a network. In various embodiments, hardware module100ofFIG.1(not shown inFIG.6) is a subsystem of computer system600that is connected to computer system600via bus614.

In addition, various embodiments disclosed herein further relate to computer storage products with a computer readable medium that includes program code for performing various computer-implemented operations. The computer-readable medium is any data storage device that can store data which can thereafter be read by a computer system. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM disks; magneto-optical media such as optical disks; and specially configured hardware devices such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and ROM and RAM devices. Examples of program code include both machine code, as produced, for example, by a compiler, or files containing higher level code (e.g., script) that can be executed using an interpreter.