Method for connecting substrate and method for manufacturing semiconductor device

A method for connecting substrates is provided. The method includes the steps of: preparing a first wiring substrate having a first substrate including a first region and a second region which are provided with a first metal wire, wherein an area ratio between the first region and the first metal wires in the first region is different from an area ratio between the second region and the first metal wire in the second region; heating the first wiring substrate to bend the first wiring substrate; and electrically connecting a third wiring on a third substrate to the first metal wire provided on the first wiring substrate, thereby mounting the first wiring substrate on the third substrate in a manner that the first surface of the first substrate is nonparallel to the first surface of the third substrate.

The entire disclosure of Japanese Patent Application No. 2011-010582, filed Jan. 21, 2011 is expressly incorporated by reference herein

BACKGROUND

1. Technical Field

The present invention relates to methods for connecting substrates and methods for manufacturing semiconductor devices.

2. Related Art

In recent years, electronic equipment often use FPC (Flexible Printed Circuit: Flexible substrate) as a method for electrically connecting electronic components to be provided on the electronic equipment. Amid advancing miniaturization of electronic equipment which require installation of electronic components in a small space, FPCs are more often used as electronic components can be laid out within a small space of electronic equipment while freely bending highly flexible FPCs. However, for further miniaturization of electronic equipment and application of FPCs to electronic devices, FPCs that can provide controllable bent shapes are in greater demand.

In this connection, Japanese Laid-open Patent Application 2002-171031 (Patent Document 1) proposes a FPC equipped with portions that can be readily bent, which are formed with a plurality of through holes, in other words, perforations, at bending portions in the FPC. Also, Japanese Laid-open Patent Application 2006-140452 (Patent Document 2) describes a structure to prevent a cover film from peeling from a resin base film, in which metal wires at bending portions are made thinner to increase bonding areas between the base film and the cover film, which uses the property of adhesive in which the adhesive force of the adhesive bonding the cover film to the resin base film is greater than to the metal wires.

However, both of the references Patent Documents 1 and 2 described above involve an independent bending step of bending a FPC, and pertain to readiness of bending the FPC and prevention of damage to the FPC. In particular, according to Patent Document 1, perforations need to be formed in advance in a FPC, which results in a longer manufacturing process, and thus a higher cost.

SUMMARY

In accordance with an aspect of embodiments of the invention, there is provided a method for connecting substrates together while bending an FPC, which does not require an independent step of bending a FPC.

The invention can be implemented by any one of the following embodiments and application examples to solve at least one of the problems described above.

APPLICATION EXAMPLE 1

A method for connecting substrates in accordance with Application Example 1 includes the steps of: preparing a first wiring substrate having a first substrate including a first surface, the first surface having a first region and a second region including a first metal wire located therein, wherein an area ratio between the first region and the first metal wire in the first region is different from an area ratio between the second region and the first metal wire in the second region; electrically bonding second metal wire on a second substrate to the first metal wire provided in the first region of the first wiring substrate; heating the first wiring substrate to bend the first wiring substrate between the first region and the second region; and electrically connecting a third wiring located in a first surface of a third substrate to the first metal wire provided in the second region of the first wiring substrate, thereby mounting the first wiring substrate on the third substrate in a manner that a portion or the entirety of the first surface of the first substrate is nonparallel to the first surface of the third substrate.

According to the application example described above, the area ratios of the first metal wire in the first region and in the second region of the first wiring substrate to the substrate are made different from each other, and heat is applied to the first wiring substrate, to cause a difference between the thermal expansion of the first wiring substrate in the first region and the thermal expansion of the first wiring substrate in the second region, thereby causing a flexural deformation near a boundary between the first region and the second region of the first wiring substrate. By the flexural deformation, a predetermined bent portion can be formed in the first wiring substrate by simply approximating the first wiring substrate together with the second substrate to the third substrate, for connecting the first wiring substrate connected to the second substrate to the third substrate. Accordingly, it is not necessary to provide in advance a step to form the first wiring substrate into a predetermined bent shape in a mounted state, and therefore a method for connecting substrates that streamlines the process and reduces the cost can be obtained.

APPLICATION EXAMPLE 2

A method for bonding substrates together in accordance with Application Example 2 includes the steps of: preparing a first wiring substrate that has a first metal wire located in a first surface of a first substrate and having a first portion and a second portion that has a narrower width than the first portion; heating the first wiring substrate to bend the first wiring substrate between the first portion and the second portion; electrically bonding a second metal wire on a second substrate to the first portion of the first wiring substrate; and electrically connecting a third wire located in a first surface of a third substrate to the second portion of the first metal wire, thereby mounting the first wiring substrate on the third substrate in a manner that a portion or the entirety of the first surface of the first substrate is nonparallel to the first surface of the third substrate.

According to the application example described above, the metal wire are made narrower in the second potion compared to the first portion of the first wiring substrate, and heat is applied to the first wiring substrate, to cause a difference between the thermal expansion of the first wiring substrate in the first portion and the thermal expansion of the first wiring substrate in the second portion, thereby causing a flexural deformation near a boundary between the first portion and the second portion of the first wiring substrate. By the flexural deformation, a predetermined bent portion can be formed in the first wiring substrate by simply approximating the first wiring substrate together with the second substrate to the third substrate, for connecting the first wiring substrate connected to the second substrate to the third substrate. Accordingly, it is not necessary to provide in advance a step to form the first wiring substrate into a predetermined bent shape required in a mounted state, and therefore a method for connecting substrates that can streamline the process and reduce the cost can be obtained.

APPLICATION EXAMPLE 3

In the application examples described above, the first substrate may be thicker than the first metal wiring.

According to the application example described above, by making the first frustrate having a greater thermal expansion thicker, compared to the metal wire having a smaller thermal expansion, a bent section occurring due to thermal deformation is securely generated, and the amount of flex is made greater to improve the connection property with respect to the third substrate.

APPLICATION EXAMPLE 4

In the application examples described above, the step of bending the first wiring substrate may include heating the first wiring substrate at temperatures between 150° C. and 250° C.

According to the application example described above, a bent section can be securely generated in the first wiring substrate.

APPLICATION EXAMPLE 5

In the application examples described above, the first portion and the second portion of the first metal wire may be connected by a third portion that continuously narrows from the first portion toward the second portion.

According to the application example described above, stress concentration in the metal wire at the bent section is alleviated, such that breakage of the metal wires can be prevented.

APPLICATION EXAMPLE 6

A method for manufacturing a semiconductor device in accordance with Application Example 6 includes the steps of: preparing a first wiring substrate having a first substrate including a first surface, the first surface having a first region and a second region including a first metal wire located therein, wherein an area ratio between the first region and the first metal wire in the first region is different from an area ratio between the second region and the first metal wire in the second region; electrically bonding a second metal wire on a second substrate to the first metal wire provided in the first region of the first wiring substrate; heating the first wiring substrate to bend the first wiring substrate between the first region and the second region; and electrically connecting a third wiring located in a first surface of a third substrate to the first metal wire provided in the second region of the first wiring substrate, thereby mounting the first wiring substrate on the third substrate in a manner that a portion or the entirety of the first surface of the first substrate is nonparallel to the first surface of the third substrate. The second substrate is a semiconductor chip.

According to the application example described above, the area ratios of the first metal wire in the first region and in the second region of the first wiring substrate to the substrate are made different from each other, and heat is applied to the first wiring substrate, to cause a difference between the thermal expansion of the first wiring substrate in the first region and the thermal expansion of the first wiring substrate in the second region, thereby causing a flexural deformation near a boundary between the first region and the second region of the first wiring substrate. By the flexural deformation, a predetermined bent portion can be formed in the first wiring substrate by simply approximating the first wiring substrate together with the semiconductor device to the third substrate, for connecting the first wiring substrate connected to the semiconductor device to the third substrate. Accordingly, it is not necessary to provide in advance a step to form the first wiring substrate into a predetermined bent shape required in a mounted state, and therefore a method for manufacturing a semiconductor device that can streamline the process and reduce the cost can be obtained.

APPLICATION EXAMPLE 7

A method for manufacturing a semiconductor device in accordance with Application Example 7 includes the steps of; preparing a first wiring substrate that a has first metal wire located in a first surface of a first substrate and including a first portion and a second portion having a narrower width than the first portion; heating the first wiring substrate to bend the first wiring substrate between the first portion and the second portion; electrically bonding a second metal wire on a second substrate to the first portion of the first wiring substrate; and electrically connecting a third wire located in a first surface of a third substrate to the second portion of the first metal wire, thereby mounting the first wiring substrate on the third substrate in a manner that a portion or the entirety of the first surface of the first substrate is nonparallel to the first surface of the third substrate. The second substrate is a semiconductor chip.

According to the method for manufacturing a semiconductor device in accordance with the application example described above, the metal wire is made narrower in the second potion compared to the first portion of the first wiring substrate, and heat is applied to the first wiring substrate, to cause a difference between the thermal expansion of the first wiring substrate in the first portion and the thermal expansion of the first wiring substrate in the second portion, thereby causing a flexural deformation near a boundary between the first portion and the second portion of the first wiring substrate. By the flexural deformation, a predetermined bent portion can be formed in the first wiring substrate by simply approximating the first wiring substrate together with the semiconductor element to the third substrate, for connecting the first wiring substrate connected to the semiconductor element to the third substrate. Accordingly, it is not necessary to provide in advance a step to form the first wiring substrate into a predetermined bent shape required in a mounted state, and therefore a method for manufacturing a semiconductor device that can streamline the process and reduce the cost can be obtained.

APPLICATION EXAMPLE 8

In the application example described above, the first substrate may be thicker than the first metal wiring.

According to the application example described above, by making the first frustrate having a greater thermal expansion thicker, compared to the metal wire having a smaller thermal expansion, generation of a bent section clue to thermal deformation is secured, and the amount of flex is made greater to improve the connection property with respect to the third substrate.

In the application example described above, the step of bending the first wiring substrate may include heating the first wiring substrate at temperatures between 150° C. and 250° C.

According to the application example described above, a bent section can be securely generated in the first wiring substrate.

APPLICATION EXAMPLE 10

In the application example described above, the first portion and the second portion of the first metal wire may be connected by a third portion that continuously narrows from the first portion toward the second portion.

According to the application example described above, stress concentration to the metal wire at the bent section is alleviated, such that breakage of the metal wires can be prevented.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the invention will be described below with reference to the accompanying drawings.

First Embodiment

FIGS. 1A and 1Bshow a semiconductor device100in accordance with a first embodiment.FIG. 1AandFIG. 1Bare, respectively, a plan view and a cross-sectional view of the semiconductor device100. For convenience in description, a cap60is not illustrated inFIG. 1A, and the cap60is shown by a phantom line (two-dot and dash lines) inFIG. 1B.

FIG. 1Ashows an electronic component100that is a semiconductor device in accordance with an embodiment of the invention (hereafter referred to as a semiconductor device100). The semiconductor device100equipped with gyro oscillation elements11,12and13will be described as an example of the embodiment. The gyro oscillation elements11,12and13are affixed on semiconductor chips21,22and23(hereafter referred to as semiconductor elements21,22and23) which respectively define second substrates. The semiconductor elements21,22and23have active surfaces21a,22aand23aon which a plurality of connection pads21c,22cand23care provided, respectively, which are bonded to electrode wires (not shown) provided on support sections11a,12aand13aof the gyro oscillation elements11,12and13, respectively. For convenience in drawing, the support section13aof the gyro oscillation element13is not illustrated.

In the semiconductor device100, surfaces11b,12band13bof the gyro oscillation elements11,12and13are each arranged to be orthogonal to X, Y and Z axes, as shown in the figures, such that each of the gyro oscillation elements11,12and13functions as a 3-axis gyro sensor. The semiconductor elements21,22and23equipped with the gyro oscillation elements11,12and13are affixed to element fixing sections provided on an element fixing plate30, which will be shown in detail inFIGS. 2A and 2B, by an appropriate method, such as, bonding with adhesive. According to the present example, the element fixing plate30is affixed at one surface of the element fixing section30aof the element fixing plate30to a package substrate40that defines a third substrate.

The semiconductor elements21,22and23affixed to the package substrate40through the element fixing plate30are electrically connected to external connection terminals21b,22band23bformed on the active surfaces21a,22aand23aof the semiconductor elements21,22and23through FPCs51,52and53that define first wiring substrates, and to electrodes40a,40band40cformed on a loading surface42a(hereafter referred to as a mounting surface42a) of the package substrate40.

The package substrate40is formed by laminating the second substrate, a first substrate41and a third substrate43. The second substrate has a mounting surface42athat is provided with the electrodes40a,40band40cformed thereon and on which the element fixing plate30equipped with the semiconductor elements21,22and23is mounted. The first substrate41is equipped with external electrodes41aconnected to the electrodes40a,40band40cthrough internal wiring (not shown). The third substrate43has a sealing surface43afor sealing and fixing the cap60that seals the inner portion.

As shown inFIG. 1A, the active surfaces22aand23aof the semiconductor elements22and23are mounted on the package substrate40at about 90 degrees with respect to the mounting surface42a, i.e., in a vertical mounting mode. Accordingly, the FPC53is formed with a bent section53a, thereby electrically connecting the semiconductor element23to the package substrate40. Although not shown inFIG. 1, the FPC52is also formed with a bent section, like the FPC53, thereby electrically connecting the semiconductor element22and the package substrate40.

The FPCs51,52and53will be described.FIGS. 3A,3B and3C show the FPCs51,52and53.FIG. 3Ais a plan view,FIG. 3Bis a cross-sectional view taken along a line A-A′ ofFIG. 3A, andFIG. 3Cis a cross-sectional view taken along a line B-B′ ofFIG. 3A. The FPCs51,52and53have generally the same configuration, and therefore only the FPC53is described as an example.

The FPC53includes a FPC substrate53that defines a first substrate having a wiring forming surface53cthat defines a first surface, and a plurality of conductive wires53dformed on the wiring forming surface53c. Further, a dielectric film or a coating53emay be formed to cover the conductive wires53dexcept the bonding portion between the semiconductor element23and the package substrate40. The FPC substrate53bmay be formed from a film of synthetic resin. As the synthetic resin material, any known material, such as, polyimide may preferably be used. The conductive wires53dmay preferably be formed from conductive metal with excellent ductility, such as, for example, copper, aluminum, gold or the like.

In the FPC53, the line width W2of each of the conductive wires53gat the section B-B′ is formed to be narrower than the line width W1of each of the conductive wires53fat the A-A′ section shown inFIG. 3A. As shown inFIG. 3D, let us define a region of the FPC53where the conductive wires53fare formed as a region L that is a first region or a first portion, and a region where the conductive wires53gare formed as a region M that is a second region or a second portion. Also, a region where conductive wires53hwhose width continuously changes to connect the conductive wires53fand the conductive wires53ghaving different line widths is defined as a region N that is a third portion.

The conductive wires53fformed in the region L are electrically connected and bonded to the external connection terminals23bformed on the active surface23aof the semiconductor element23shown inFIGS. 1A and 1B, at their end sides on the opposite side of the region M. Also, the conductive wires53gformed in the region M are electrically connected and bonded to the electrodes40bformed on the mounting surface42aof the package substrate40on their end sides on the opposite side of the region L. As shown inFIG. 1B, in a configuration in which the semiconductor element23and the package substrate40are connected to each other by the FPC53being bent in a middle section of the FPC53, the FPC53is bent near a line C-C′ shown inFIG. 3Athat is a border between the conductive wires53gin the region M where the line width is narrow and the conductive wires53hwhose line width is changed.

In other words, the conductive wires53hthat change the line width W2of the conductive wires53gto the line width W1of the conductive wires53fdefine a line width changing point, and the conductive wires53dmade of metal have large bending strength compared to polyimide that forms the FPC substrate53b, such that the FPC53bents around the C-C′ portion as a bent section where it becomes more difficult to bend.

FIG. 3Eshows other examples of the conductive wires53hwhose line width changes, which are mutually different in the manner how the line width changes. As shown inFIG. 3E, the line width of the conductive wire53hmay be formed with a curve shown on the left in the figure, that is, a concave configuration toward the inner side of the line width, or with a curve shown in the center in the figure, that is, a convex configuration toward the outer side of the line width. Also, it is possible to use a configuration in which the conductive wire53fand the conductive wire53gare directly joined together without the conductive wire53hprovided there between, as shown on the right inFIG. 3E.

The FPC53described above has, as an example, a configuration in which the line width W2of the conductive wires53gin the region M is smaller, compared to the line width W1of the conductive wires53fin the region L. However, the invention is not limited to this configuration. For example, when the region L of the FPC53has an area SLin a plan view, the conductive wire53fhas an area Slin a plan view, the region M has an area SMin a plan view, and the conductive wire53ghas an area Smin a plan view, the following relation may be established:
(Sm/SM)/(SlSL)<1.0

In other words, the conductive wires53dmay be formed in a configuration in which the forming area ratio of the conductive wires53gin the region M is smaller than the forming area ratio of the conductive wires53fin the region L.

For example,FIG. 4Ashows a FPC70including conductive wires70ahaving different line widths in the regions L and M, and conductive wires70bhaving the same line width in the regions L and M, which are mixed together. In the region L, the area SLof the region L is given by:
SL=HL×WL

The area Slof the conductive wires70aand70bin the region L in a plan view is the sum of areas s1-s5of the conductive wires70aand the conductive wires70bin the region L, which is given by:
Sl=s1+s2+s3+s4+s5

Meanwhile, the area SMof the region M is given by:
SM=HM×WM

The area Smof the conductive wires70aand70bin the region M in a plan view is the sum of areas s6-s10of the conductive wires70aand the conductive wires70bin the region M, which is given by
Sm=s6+s7+s8+s9+s10

The line widths of the conductive wires70aand70bare to be decided such that the values Sm, SM, Sland SLthus obtained satisfy the following relation:
(Sm/Sm)/(Sl/SL)<1.0

Also,FIG. 4Bshows a FPC71including conductive wires71ahaving the same line width. Even in this case, its FPC substrate71bcan be formed to have a width WLin the region L and a with WMgreater than the width WLin the region M, whereby the aforementioned relation, (Sm/SM)/(Sl/SL)<1.0 can be satisfied.

Second Embodiment

As a second embodiment, a method for manufacturing the semiconductor device100in accordance with the first embodiment described above will be described.FIG. 5is a flow chart showing steps of manufacturing the semiconductor device100of the first embodiment.

First, semiconductor elements21,22and23, and gyro oscillation elements11,12and13composing the semiconductor device100in accordance with the first embodiment are prepared (S1). In step S1, on active surfaces21a,22aand23aof the semiconductor elements21,22and23, connection pads21c,22cand23cfor connecting to the gyro oscillation elements11,12and13, and external connection terminals21b,22band23bfor connecting to the FPC51,52and53are formed in the shape of bumps (in the shape of protrusions) by, for example, stud bumps or paste. The gyro oscillation element11,12and13are formed from, for example, crystal quartz, and equipped with predetermined electrode wires.

As shown inFIGS. 3A and 3B, each of the FPCs (51,52and53) is provided with conductive wires (51d,52dand53d) including conductive wires (51f,52fand53f) that define first metal wires formed in the region L defining the first region corresponding to the external connection terminals (21b,22band23b) provided on the semiconductor element (21,22and23), and conductive wires (51g,52gand53g) that define second metal wires formed in the region M defining the second region corresponding to the electrodes (40a,40band40c) of the package substrate40.

Next, a FPC connection step (S2) is conducted. In the FPC connection step (S2), the FPCs51,52and53are processed by the same method, and therefore this step is described using the FPC53as an example. In the FPC connection step (S2), as shown inFIG. 6A, the external connection terminals23bformed on the active surface23aof the semiconductor element23and the conductive wires53fof the FPC53in the region L are aligned with each other, and bonded together by ultrasonic bonding. The bonding method is not limited to ultrasonic bonding, and any one of appropriate bonding methods may be selected.

Next, a gyro oscillation element connection step (S3) is conducted. In the step S3, gyro oscillation elements11,12and13are mounted on the semiconductor elements21,22and23bonded to the FPCs51,52and53, respectively. It is noted that, in the gyro oscillation element connection step (S3), the gyro oscillation elements11,12and13are processed by the same method, and therefore this step is described using the gyro oscillation element13as an example. As shown inFIG. 6B, in the gyro oscillation element connection step (S3), an electrode section (not shown) (which is provided opposite the connection pad23c) of the support section13aof the gyro oscillation element13is electrically connected and fixedly bonded to the connection pad23cformed on the active surface23aof the semiconductor element23by conductive adhesive. Alternatively, the connection pad23cand the support section13amay be electrically connected together by application of heat and pressure. Also, at the time of heat application, heating may be conducted in a manner that heat transfers to the FPC53. The bonding is not limited to the method using conductive adhesive, and any one of appropriate bonding methods may be used.

Next, a gyro oscillation element frequency adjustment step (S4) is conducted. In the gyro oscillation element frequency adjustment step (S4), a laser beam is irradiated on electrode films or metal films for adjustment formed on the driving arms of each of the gyro oscillation elements11,12and13, thereby partially removing the metal films to adjust the oscillation frequency of each of the gyro oscillation elements11,12and13to a predetermined frequency.

Next, an element fixing plate attachment step (S5) is conducted. In the element fixing plate adhesion step (S5), an element fixing plate30shown inFIGS. 2A and 2Bis prepared in advance. The element fixing plate30is formed using a plate member made of, for example, stainless steel, brass, aluminum or the like. As shown inFIG. 7A, the semiconductor elements21,22and23which have been processed up to the step S4are attached to the element fixing plate30.

The semiconductor elements21,22and23may be attached to the element fixing plate, using adhesive. Any type of adhesive may be used without any particular limitation, and adhesive with excellent bonding and insulation property, such as, for example, epoxy based adhesive may preferably be used. In the present example shown, the semiconductor element21is affixed with adhesive to the element fixing section30athat is affixed with adhesive to the mounting surface42aof the package substrate40. However, after the element fixing plate30may be first affixed to the package substrate40to be discussed later, and then the semiconductor element21may be bonded to the element fixing section30a.

Next, a FPC heating step (S6) is conducted. In the FPC heating step (S6), the FPCs52and53are heated to form slight bent sections in advance in the FPC52and53that will be bent when they are assembled onto the package substrate40. The FPCs52and53may be heated by any appropriate heating method using, for example, hot air, a halogen lamp, solid state heater contact or the like. In order to avoid unnecessary heat load to be applied to the semiconductor elements22and23, and the semiconductor element21equipped with the FPC51that is not bent, heating with a halogen lamp that can collect and irradiate heat or heating by contact with a solid state heater is suitable.

As shown inFIG. 7A, halogen heaters80each equipped with a heat collector device may be disposed opposite the FPCs52and53, and the FPCs52and53are retained and heated at 150° C.-200° C. for 1-2 minutes. By heating in this manner, deformation is generated in the FPCs52and53in a direction indicated by an arrow D as shown inFIG. 7B.

The deformation in the direction D caused by heat is generated due to thermal expansion of polyimide that is the material of the FPC substrates51b,52band53bof the FPCs51,52and53.FIGS. 8A and 8Bare schematic illustrations for explaining the phenomenon in which thermal deformation is generated in the FPC heating step (S6). As shown in a schematic plan view inFIG. 8A, the FPCs52and53are fixedly bonded to the external connection terminals22band23bof the semiconductor elements22and23. In other words, the regions L of the FPCs52and53are in effect fixedly bonded to the semiconductor elements22and23.

Moreover, as described above, in the region L of the FPCs52and53, the line width of the conductive wires52fand53f, or the area ratio of the conductive wires52fand53foccupying the region L is large, as shown inFIG. 3A, and the thermal expansion of the metal conductive wires52fand53fis smaller, compared to polyimide forming the FPC substrates52band53b, such that thermal expansion of the FPCs52and53in the region L is restricted.

In contrast, in the region M of the FPCs52and53, the line width of the conductive wires52gand53g, or the area ratio thereof is small, such that polyimide of the FPC substrates52band53bthermally expands, and would expand to a shape F1after expansion as indicated inFIG. 8A. However, as the thermal expansion of the FPCs52and53in the region L is restricted, as described above, the thermal expansion of the region M is brought into a state in which its shape is restricted to a shape F2. In this instance, at a section P1-P1′ of the region M near the region L, the FPCs52and53warp as shown in a cross-sectional view taken along P1-P1′ ofFIG. 8Ain order to absorb an increase in the width of the FPCs52and53caused by the thermal expansion, because the FPCs52and53before thermal expansion are influenced by the restriction of the thermal expansion in the region L. The influence of the restriction of thermal expansion in the region L gradually diminishes to a farther section P2-P2′ and to an even farther section P3-P3′, and the degree of warping of the FPCs52and53becomes smaller accordingly.

On the other hand, along a section Q-Q′ shown inFIG. 8A, as shown in a cross-sectional view taken along Q-Q′, the warping in the cross section P1-P1′ generated by the influence of the restriction of thermal expansion in the region L causes a warping in a direction D shown in the figure. This causes warping in two directions, as shown in a perspective view inFIG. 8B. It is noted that the FPCs are heated by using the halogen heaters80in the FPC heating step (S6), but instead, the bent sections described above may be formed in the FPCs by heat applied to the FPCs in the gyro oscillation element connection step (S3).

Next, an element fixing plate-substrate fixing step (S7) is conducted. In the element fixing plate-substrate fixing step (S7), the element fixing plate30to which the semiconductor elements21,22and23have been affixed in the steps S5and S6is mounted on the package substrate40. First, the element fixing plate30with the semiconductor elements21,22and23affixed thereto is mounted on the package substrate40. In this process, the FPCs52and53that have been warped in the step S6are brought in contact at their tips to the mounting surface42aof the package substrate40, as shown inFIG. 9A. Then, as shown inFIG. 9B, the tip sections of the FPCs52and53gradually move along the mounting surface42a, while, at the same time, the bent sections52aand53agradually bend further at the C-C′ section shown inFIG. 3A. Then, the element fixing plate30is mounted in a predetermined assembly position, as shown inFIG. 9C. Then, the mounting surface42aand the element fixing plate30are bonded together by adhesive or the like.

In this manner, by forming the warped sections in the FPCs52and53in the region M by heat application in the FPC heating step (S6), the predetermined bent sections52aand53can be automatically formed in the FPCs52and53concurrently with the mounting work in the step of fixing the element fixing plate to the substrate (S7).

The bent sections52aand53astart bending around the C-C′ section as a bending start point which defines a boundary between the conductive wires52g(53g) in the region M and the conductive wires52h(53h) in the region N shown inFIG. 3A. In other words, as the conductive wires52h(53h) in the region N where the line width becomes greater are more difficult to bend, the portions along the C-C′ section at the boundary would more readily bend. Therefore, the position of the C-C′ section that defines the boundary between the conductive wires52g(53g) in the region M and the conductive wires52h(53h) in the region N may be decided in advance, whereby the bending positions in the FPCs52and53can be controlled.

Next, a FPC-substrate connection step (S8) is conducted. In the FPC-substrate connection step (S8), as shown inFIG. 10, one end sections of the FPCs51,52and53are electrically connected to the electrodes40aformed on the mounting surface42aof the package substrate40. For the connection, for example, in the case of the FPC53shown in the figure, the tip of an ultrasonic cone90may be abutted to the connection section in a manner to push the FPC53against the electrode40c, and the FPC53and the electrode40care connected by ultrasonic bonding. By using the same method, the FPCs51and52are connected to the package substrate40. It is noted that the connection may be conducted individually for each of the FPCs51,52and53. Alternatively, a plurality of ultrasonic cones may be used to connect them at the same time.

Next, a capping (sealing) step (S9) is conducted. In the capping (sealing) step (S9), as the semiconductor device100shown in the present example is equipped with the gyro oscillation elements11,12and13, a cap60shown inFIG. 1Bis fixedly bonded to the upper surface of the third substrate43of the package substrate40, in order to remove oxygen gas and nitrogen gas in the air which are gas compositions around the elements which make vibration of the gyro oscillation elements11,12and13unstable, and maintain the interior of the semiconductor device100vacuum sealed. The cap60may be made of metal, such as, for example, stainless steel, titanium, titanium alloy, aluminum, aluminum alloy or the like. The cap60is placed on the package substrate40, and the cap60and the third substrate43are sealed and affixed together in a vacuum (a reduced pressure) atmosphere, thereby completing the semiconductor device10shown inFIG. 1.

When the semiconductor elements22and23that define the second substrates are mounted on the package substrate40that defines the third substrate in orientations nonparallel to one another, for example, as in the present example, angled at about 90 degrees with one another, the FPCs52and53that define the first wiring substrates for connecting the semiconductor elements22and23with the package substrate40need to be provided with bent sections. As described above, the following method is conducted for forming the bent sections. The FPCs52and53are heated to form warped sections; in the process of mounting the semiconductor elements22and23together with the element fixing plate30, the tip sections of the FPCs52and53with the warped sections formed therein are slidably moved along the mounting surface42aof the package substrate40; at the time when the element fixing plate is mounted on the mounting surface42a, the FPCs52and53are each provided with the predetermined bent configuration. In other words, in any mount methods, which may be represented by the so-called vertical mount method, excluding the surface mount method, bent sections in FPCs can readily be formed, processes for mounting electronic components can be streamlined, and cost-reduction can be achieved.

It is noted that the embodiment has been described above, using a semiconductor device as an example. However, without any particular limitation to the above, the FPC connection method in accordance with the invention is applicable even when electronic components other than semiconductor elements are mounted on a substrate nonparallel to one another.

Embodiment Examples

A semiconductor element10and a FPC50fixedly bonded to the semiconductor element10having dimensions as shown inFIG. 11Awere prepared, and the FPC50was heated at 200° C. for two minutes. As a result, the FPC50acquired a bent at an angle of about 20 degrees as shown inFIG. 11B. The semiconductor element10having the FPC50with the bent was fixedly bonded to the element fixing plate30, and mounted on the package substrate40. As a result, as shown inFIG. 11C, the FPC50was successfully bent along the mounting surface42aof the package substrate40.