Parallel connected power supplies having parallel connected control circuits which equalize output currents to a load even after one supply is turned off

A power supply system comprises several power supplies, each of which has output terminals that are coupled in parallel to supply respective DC output currents at the same time to a single load. Each power supply also has a branch of a control circuit, and each branch from every supply is coupled in parallel to thereby form a complete control circuit. In these branches, control currents flow that cause the respective output currents from the several power supplies to equalize. Each power supply also has a circuit for automatically turning the supply off independent of the other power supplies when a component in the supply fails; and under such conditions, a switch in the control circuit branch of the failing supply automatically opens which prevents control current from flowing therein and enables the remaining supplies to share the added load.

BACKGROUND OF THE INVENTION 
This invention relates to power supplies that furnish DC voltages and DC 
currents to integrated circuits in data processing apparatus such as 
computers and peripherals; and more particularly, it relates to systems of 
several intercoupled power supplies which operate in parallel to share in 
furnishing the DC current. 
Basically, a power supply of the above type receives AC power from a wall 
outlet, and it converts that AC input power to DC output power. In one 
typical power supply, the Ac input power is at 208 volts and 60 Hz, while 
the DC output power is at 5 volts. Each power supply has a maximum power 
rating which determines how much current it can furnish and still maintain 
the DC voltage within a certain regulation band. For example, a 1500 watt, 
5 volt power supply can furnish up to 300 amps and still maintain a 5 volt 
DC output voltage. 
Frequently, DC power is furnished to the circuits of data processing 
apparatus by just one large power supply. However, a system of several 
small power supplies operating in parallel can also be employed. Suppose, 
for example, that the data processing apparatus requires 4500 watts at 5 
volts. This can be achieved by one 4500 watt, 5 volt power supply which 
furnishes 900 amps, or it can be achieved by a system of three 1500 watt, 
5 volt power supplies which operate in parallel and furnish 300 amps each. 
If a single large power supply is used, then the total number of power 
supply parts will generally be minimized. Also, the total number of 
connections which need to be made in order to install the power supply in 
the data processing apparatus will generally be minimized. 
But when a system of several small power supplies is used, the individual 
supplies can be arranged to fit into differently shaped spaces within the 
data processing apparatus. Also, it generally is easier to circulate air 
through several small power supplies rather than one large power supply, 
and thus cooling the smaller power supplies may be easier. Further, with 
small power supplies, it generally is easier to shorten the distance which 
large currents must travel; and thus it is easier to reduce inductive 
noise in the power supplies' output voltage. 
One problem, however, with systems of paralleled power supplies in the 
prior art is that individual supplies in the system could not be 
separately turned off and turned back on without causing the DC output 
voltage of the system to go outside of its regulation band. But such a 
feature is very desirable because it enables any one power supply in the 
system to become defective, to be automatically turned off, to be 
replaced, and to be turned back on without ever stopping the operation of 
the data processing apparatus. 
Accordingly, a primary object of the invention is to provide a system of 
parallel power supplies in which the above problem is overcome. 
BRIEF SUMMARY OF THE INVENTION 
A power supply system which is constructed according to the invention 
comprises: a plurality of power supplies having respective output 
terminals which are coupled in parallel to supply respective DC output 
currents at the same time; each power supply has a branch of a control 
circuit which includes a voltage generator for generating a control 
voltage which is proportional to the respective output current from the 
power supply, and a resistor in series with the voltage generator; each 
power supply has its control circuit branch coupled in parallel with the 
control circuit branches of the remaining power supplies to thereby form a 
complete control circuit in which respective control currents flow in 
response to any imbalance in the control voltage in the respective power 
supplies; each power supply also includes a circuit for adjusting the 
magnitude of its respective output current as a function of the respective 
control current through the resistor in its control circuit branch; each 
power supply also forms a signal for turning the supply on and off 
independent of the other power supplies; and, each power supply further 
includes an automatically operated electronic switch in its control 
circuit branch for automatically enabling control current to flow therein 
only when the power supply is on.

DETAILED DESCRIPTION OF THE INVENTION 
Referring now to FIG. 1, a preferred embodiment of a power supply system 
which is constructed according to the invention will be described in 
detail. This particular power supply system includes three power supplies 
which are labeled PS.sub.1, PS.sub.2, and PS.sub.3. As an alternative, 
however, the system can include any number of power supplies as indicated 
by the dots (....) at the bottom of FIG. 1. 
Each power supply in the system has a pair of output terminals, and they 
are indicated in the righthand side of FIG. 1 by a plus and minus sign. 
These terminals are coupled in parallel and simultaneously supply 
respective DC output currents to an external load R.sub.L. Power supplies 
PS.sub.1, PS.sub.2, and PS.sub.3 respectively supply output currents 
IO.sub.1, IO.sub.2, and IO.sub.3 ; and those currents together form a load 
current I.sub.L which produces a DC voltage drop V.sub.L across the 
external load. 
Each power supply further includes one branch of a control circuit. In 
power supply PS.sub.1, the control circuit branch comprises several 
components which are labeled RA.sub.1, VC.sub.1, RB.sub.1, C.sub.1, 
S.sub.1, and VR.sub.1. These components are interconnected as illustrated; 
and, as described hereafter in conjunction with FIGS. 2 and 3, they 
regulate the amount of output current IO.sub.1. 
Similarly, in power supply PS.sub.2, the control circuit branch comprises 
components RA.sub.2, VC.sub.2, RB.sub.2, C.sub.2, S.sub.2, and VR.sub.2. 
And in power supply PS.sub.3, the control circuit branch comprises 
components RA.sub.3, VC.sub.3, RB.sub.3, C.sub.3, S.sub.3, and VR.sub.3. 
Here again these components are interconnected as illustrated, and they 
regulate the amount of output current which the corresponding power supply 
furnishes to the external load R.sub.L. 
Components RA.sub.1, RA.sub.2, and RA.sub.3 are resistors, and a suitable 
value for each of them is 24.9K ohms. Components RB.sub.1, RB.sub.2, and 
RB.sub.3 are resistors, and a suitable value for each of them is 49.9K 
ohms. Components C.sub.1, C.sub.2, and C.sub.3 are capacitors; and a 
suitable value for each of them is 0.1 microfarad. Components VR.sub.1, 
VR.sub.2, and VR.sub.3 are reference voltage generators, and they each 
generate a fixed reference voltage, such as 5 volts. 
Components VC.sub.1, VC.sub.2, and VC.sub.3 are control voltage generators. 
They each generate a control voltage which varies in proportion to the 
respective output current from the corresponding power supply. A preferred 
embodiment for each voltage generator is described hereafter in 
conjunction with FIG. 4. 
Components S.sub.1, S.sub.2, and S.sub.3 are electrically operated 
switches. They each enable a respective control current IC.sub.1, IC.sub.2 
and IC.sub.3 to flow through a control circuit branch when the 
corresponding power supply is on, and they inhibit the respective control 
current from flowing through the control circuit branch when the 
corresponding power supply is off. A preferred embodiment for each switch 
is described hereafter in conjunction with FIG. 5. 
All of the remaining components of each of the power supplies PS.sub.1, 
PS.sub.2, and PS.sub.3 are contained within respective modules labeled 
PS.sub.1 ', PS.sub.2 ', and PS.sub.3 '. Included in each module is 
circuitry for manually turning the power supply on, and circuitry for 
manually and automatically turning the power supply off. This circuitry 
will be described further in conjunction with FIGS. 4 and 5. 
Also respectively included in the modules PS.sub.1 ', PS.sub.2 ', and 
PS.sub.3 ' are control terminals labeled CT.sub.1 , CT.sub.2 , and 
CT.sub.3. These terminals are connected to the control circuit branches as 
illustrated. In operation, each module compares the voltage on its control 
terminal to the load voltage V.sub.L ; and it increases its output current 
if the load voltage is lower than the control terminal voltage, and 
decreases its output current if the load voltage is higher than the 
control terminal voltage. 
That control terminal voltage is dependent upon the control currents 
IC.sub.1, IC.sub.2 and IC.sub.3 which flow in the control circuit 
branches. Specifically, the voltage on control terminal CT.sub.1 equals 
the reference voltage VR.sub.1 plus or minus the quantity (IC.sub.1 ) 
(RC.sub.1 ). Similarly, the control voltage on terminal CT.sub.2 equals 
the reference voltage VR.sub.2 plus or minus the quantity (IC.sub.2 
)(RC.sub.2 ); and the voltage on control terminal CT.sub.3 equals the 
reference voltage VR.sub.3 plus or minus the quantity (IC.sub.3 )(RC.sub.3 
). 
Each power supply has its control circuit branch coupled in parallel with 
the control circuit branches of the remaining power supplies. This forms a 
complete control circuit in which the respective control currents 
IC.sub.1, IC.sub.2 and IC.sub.3 flow. These currents have a magnitude and 
direction which is determined by any imbalance in the control voltages 
VC.sub.1, VC.sub.2, and VC.sub.3 l . 
Under ideal operating conditions, each power supply furnishes the same 
amount of output current to the external load. Consequently, the control 
voltages VC.sub.1, VC.sub.2, and VC.sub.3 are all zero. This is shown in 
FIG. 2 as occurring at time t.sub.1. 
Suppose now that output current IO.sub.1 from supply PS.sub.1 increases and 
becomes larger than output currents IO.sub.2 and IO.sub.3. When that 
occurs, the voltage from control voltage generator VC.sub.1 will be larger 
than the voltage from the control voltage generators VC.sub.2 and 
VC.sub.3. 
Due to this imbalance in the control voltages, current IC.sub.1 will flow 
in a positive direction through the control circuit branch of supply 
PS.sub.1 ; current IC.sub.2 will flow in a negative direction through the 
control circuit branch of supply PS.sub.2 ; and current IC.sub.3 will flow 
in a negative direction through the control circuit branch of supply 
PS.sub.3. This is shown in FIG. 2 as occurring at time t.sub.2. 
Mathematical expressions for the magnitudes of the currents IC.sub.1, 
IC.sub.2, and IC.sub.3 are also given in FIG. 2 by equation 1. 
As current IC.sub.1 flows through the control circuit branch of supply 
PS.sub.1, it produces a voltage drop across resistor RC.sub.1 which lowers 
the voltage on terminal CT.sub.1. Thus the output current IO.sub.1 from 
power supply PS.sub.1 is reduced. This in turn lowers the voltage from 
control voltage generator VC.sub.1, and that reduces the imbalance in the 
control voltages. 
At the same time, control currents IC.sub.2 and IC.sub.3 in power supplies 
PS.sub.2 and PS.sub.3 produce respective voltage rises in control 
terminals CT.sub.2 and PS.sub.3 increase their respective output currents 
IO.sub.2 and IO.sub.3. This in turn increases the voltages from control 
voltage generators VC.sub.2 and VC.sub.3, and that further reduces the 
imbalance in the control voltages. 
As the imbalance in the control voltages is reduced, the magnitudes of the 
control currents are also reduced. This is shown in FIG. 2 as occurring at 
time t.sub.3. Such reduction continues to occur until, as shown at time 
t.sub.4, currents IC.sub.1, IC.sub.2, and IC.sub.3 are again returned to 
zero. 
Consider now how the power supply system operates when one of the power 
supplies is turned off while the remaining power supplies are left on. 
This operation is illustrated in FIG. 3. Such a turning off of one power 
supply can, for example, be initiated automatically by the detection of an 
output overvoltage condition that is caused by a component failure within 
the supply. 
Initially, as shown at time t.sub.1 in FIG. 3, all of the power supplies 
are on; and they each are delivering equal amounts of output current to 
the external load. Subsequently, at time t.sub.2, power supply PS.sub.1 is 
turned off; and as an immediate response, the electrically operated switch 
S.sub.1 opens. This inhibits may control current IC.sub.1 from flowing 
through the turned off power supply. 
Shortly thereafter, the output current IO.sub.1 and the voltage from 
generator VC.sub.1 both decay in a ramped fashion to zero. This is shown 
as starting to occur at time t.sub.3. Due to the rampdown of current 
IO.sub.1, the voltage V.sub.L across the external load starts to decrease. 
Also, due to the rampdown of voltage generator VC.sub.1, a voltage 
imbalance occurs in the respective control voltage branches. 
This voltage imbalance tends to generate control current IC.sub.1 in a 
negative direction and generate control currents IC.sub.2 and IC.sub.3 in 
a positive direction. This is shown by the dashed lines in FIG. 3 at time 
t.sub.4. However, since switch S.sub.1 is open, each of the control 
currents IC.sub.1, IC.sub.2, and IC.sub.3 stay at zero as indicated by the 
solid line at time t.sub.4. 
As the load voltage V.sub.L drops, it becomes less than the voltage at the 
control terminals CT.sub.2 and CT.sub.3. Consequently, the power supplies 
PS.sub.2 and PS.sub.3 increase their respective output currents IO.sub.2 
and IO.sub.3, and this restores the load voltage V.sub.L to its regulated 
value. This sequence is illustrated in FIG. 3 as occurring between times 
t.sub.3 and t.sub.5. 
To further appreciate the significance of the switches S.sub.1, S.sub.2, 
and S.sub.3 in the above power-off sequence, suppose now that they are not 
included in the power supply system. In that case, the control currents 
IC.sub.1, IC.sub.2, and IC.sub.3 will flow as shown by the dashed lines 
beginning at time t.sub.3. Currents IC.sub.2 and IC.sub.3 will generate 
respective voltage drops across resistors RC.sub.2 and RC.sub.3, and that 
will lower the voltage on the control terminals CT.sub.2 and CT.sub.3. 
As a result, the output currents IO.sub.2 and IO.sub.3 will be reduced 
until the load voltage V.sub.L equals the lowered voltage on the control 
terminals CT.sub.2 and CT.sub.3. In other words, the load voltage V.sub.L 
will be forced to a level below the reference voltage and may even be 
outside of a predetermined regulation band. This is indicated in FIG. 3 by 
the dashed line at time t.sub.6. 
Consider now the signal sequence that occurs when the switches S.sub.1, 
S.sub.2, and S.sub.3 are in place, the defective component in power supply 
PS.sub.1 has been repaired, and power supply PS.sub.1 is manually turned 
back on. That signal sequence is illustrated in the righthand half of FIG. 
3. Initially, as shown at time t.sub.10, switch S.sub.1 closes as an 
immediate response to power supply PS.sub.1 being turned on. That in turn 
allows the control current IC.sub.1 to flow. Current IC.sub.1 will be 
negative and currents IC.sub.2 and IC.sub.3 will be positive since the 
voltage across generator VC.sub.1 is initially zero. This is illustrated 
as occurring at time t.sub.11. 
Control current IC.sub.1 causes the voltage on control terminal CT.sub.1 to 
rise. Consequently, output current IO.sub.1 begins to ramp up. At the same 
time, control currents IC.sub.2 and IC.sub.3 respectively decrease the 
voltage on control terminals CT.sub.2 and CT.sub.2 ; and thus the output 
currents IO.sub.2 and IO.sub.3 begin to ramp down. This is shown in FIG. 3 
as occurring at time t.sub.12. 
As the output current IO.sub.1 increases, the voltage across generator 
VC.sub.1 also increases; and as the output currents IO.sub.2 and IO.sub.3 
decrease, the voltages across generators VC.sub.2 and VC.sub.3 decrease. 
This action continues until all of the output currents IO.sub.1, IO.sub.2, 
and IO.sub.3 are equal to each other. At that time, the control voltages 
VC.sub.1, VC.sub.2, and VC.sub.3 are in balance and so the control 
currents IC.sub.1, IC.sub.2, and IC.sub.3 are reduced to zero. This is 
shown as occurring at time t.sub.13. 
Turning now to FIG. 4, additional details of a preferred embodiment of each 
of the control voltage generators VC.sub.1, VC.sub.2 and VC.sub.3 will be 
described.this embodiment includes four diodes D1, D2, D3 and D4, a 
resistor R, and a current transformer T1. All of these components are 
interconnected as illustrated. Suitably, resistor R has a resistance of 20 
ohms. 
As shown in FIG. 4, the primary side of transformer T1 is coupled in series 
with the primary side of a power transformer T2 which lies within power 
supply module PS'. That power transformer T2 separates module PS' into an 
input section and an output section. In operation, the input section 
receives AC power from a wall outlet at 60 Hz and converts that power to a 
higher frequency across transformer T2; and the output section receives 
the high frequency power and converts it to DC power for the external load 
R.sub.L. For example, the input section receives 208 volts at 60 Hz and 
converts it to 150 volts at 20 KHz; and the output section converts the 20 
KHz power to 5 volts DC. 
That higher frequency current through the primary of transformer T2 has a 
variable duty cycle. Specifically, the currents pulse width is increased 
when the output voltage is lower than the voltage on the control terminal 
CT, and vice versa. Suitably, this is achieved by a TDA 4700 control chip 
from Siemens. 
Transformer T1 has fewer turns in its primary than in its secondary; and 
transformer T2 has more turns in its primary than in its secondary. 
Suitably, transformer T1 has a primary-secondary turns ratio of 1:200; and 
transformer T2 has a primary-secondary turns ratio of 10:1. Thus, when a 
current of 200 amps flows through the secondary of transformer T2, a 
current of only 100 milliamps flows in the secondary of transformer T1. 
And when a current of 300 amps flows through the secondary of transformer 
T2, a current of only 150 milliamps flows through the secondary of 
transformer T1. 
That current which flows through the secondary of transformer T1 is 
rectified by the diodes D1-D4 such that it flows in one direction (from 
left to right) through resistor R. Thus a voltage is generated across 
resistor R which is a measure of the current which the power supply 
delivers to the external load. Resistors RA, RB, and capacitor C operate 
to filter this voltage and retain its DC component. With the above 
described turns ratio, this voltage across resistor R is 1:0 volts per 100 
amps of output current. 
Next, reference should be made to FIG. 5 wherein a preferred embodiment of 
each of the electronically controlled switches S.sub.1, S.sub.2, and 
S.sub.3 is shown. This embodiment includes a pair of electro-optical 
couplers EOC1 and EOC2, a pair of resistors RC and RD, a buffer B, a delay 
network D, a mechanical power-on switch ON, and three diodes D11 through 
D13. All of these components are interconnected as FIG. 5 illustrates. 
When the power supply is manually turned on, the power-on switch ON is in 
an open position. Also, if the power supply is not defective, all of the 
signals to the diodes D12 and D13 are true or high. This combination 
causes the RUN signal to be at high voltage +V. Thus, buffer B causes a 
current to flow through the diode portion of the electro-optical couplers 
EOC1 and EOC2. As a result, the transistor portions of those couplers 
become conductive, and that enables the previously described control 
currents IC.sub.1, IC.sub.2, and IC.sub.3 to pass through them. 
Conversely, when the power supply is manually turned off, the power-on 
switch ON is closed. This causes the RUN signal to be at a low voltage. 
Thus the output of buffer B also goes to a low voltage, and that stops any 
current from flowing through the diode portion of the electro-optical 
couplers EOC1 and EOC2. In response, the transistor portions of those 
electro-optical couplers become nonconductive and prevent the control 
currents IC.sub.1, IC.sub.2 and IC.sub.3 from flowing. 
Similarly, when the power supply is turned off automatically, the RUN 
signal will be forced low. For example, if a component failure in the 
power supply causes the DC output voltage to get too high, then signal 
OUTPUTOVERV goes low which forces the RUN signal low. In like manner, 
signal OUTPUTOVERI will go low and force signal RUN low if a component 
failure in the supply causes the DC output current to get too large. 
All high and low voltages from the output of buffer B are delayed by the 
delay network D. Preferably, this delay is in the range of ten 
microseconds to ten milliseconds. Those delayed high and low voltages from 
delay network D are generated as a control signal which is used within the 
PS' input section to respectively enable and disable the high frequency AC 
power from being applied to the primary winding of transformer T2. 
Consequently, the switch always opens before the power supply turns off, 
and the switch closes before the power supply turns on. 
A preferred embodiment of the invention has now been described in detail. 
In addition, however, many changes and modifications can be made to these 
details without departing from the nature and spirit of the invention. For 
example, the electro-optical couplers EOC1 and EOC2 in the FIG. 5 switch 
may be replaced with an electro-mechanical relay whose coil is energized 
by the signal from buffer B and whose contacts pass/stop the control 
current. Alternatively, couplers EOC1 and EOC2 may be replaced with a pair 
of field effect transistors, one of which is P-channel and the other of 
which is N-channel, that are coupled to pass/stop the control current in 
parallel. Buffer B's output signal is coupled to the gate of the N-channel 
transistor, and the complement of that signal is coupled to the gate of 
the P-channel transistor. Accordingly, since many such changes may be 
made, it is to be understood that the invention is not limited to the 
above details but is defined by the appended claims.