Semiconductor device and electronic device

A semiconductor device includes: first and second semiconductor elements each having two electrodes respectively disposed on two surfaces; two first terminals respectively connected to the two electrodes of the first semiconductor element and arranged side by side in one direction; two second terminals respectively connected to the two electrodes of the second semiconductor element, and arranged side by side in the one direction to be adjacent to the two first terminals; and a sealing resin portion covering the first and second semiconductor elements and the first and second terminals in a state where facing surfaces of the first and second terminals are exposed from the sealing resin portion. The facing surfaces of the two first terminals have different area ratios, the facing surfaces of the two second terminals have different area ratios, and one of the first terminals is arranged adjacent to both the two second terminals.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and an electronic device including the semiconductor device.

BACKGROUND

Conventionally, a semiconductor device including two semiconductor elements has been known.

SUMMARY

The present disclosure provides a semiconductor device and an electronic device including the semiconductor device. The semiconductor device includes: first and second semiconductor elements each having two electrodes respectively disposed on two surfaces; two first terminals respectively connected to the two electrodes of the first semiconductor element and arranged side by side in one direction; two second terminals respectively connected to the two electrodes of the second semiconductor element, and arranged side by side in the one direction to be adjacent to the two first terminals; and a sealing resin portion covering the first and second semiconductor elements and the first and second terminals in a state where facing surfaces of the first and second terminals are exposed from the sealing resin portion. The facing surfaces of the two first terminals have different area ratios, the facing surfaces of the two second terminals have different area ratios, and one of the first terminals is arranged adjacent to both the two second terminals.

DETAILED DESCRIPTION

A semiconductor device according to a comparative example includes a composite power metal oxide semiconductor field effect transistor (MOSFET) that forms a DC-DC converter, a high-side power MOSFET is composed of a lateral MOSFET, and a low-side power MOSFET is composed of a vertical MOSFET.

In the above semiconductor device, two semiconductor elements are configured in the same shape. Therefore, it is difficult to use the semiconductor elements as switching elements for an inverter or a semiconductor relay. In addition, in products that handle large currents, a wiring area and a width become large, and it becomes more difficult to achieve both.

A semiconductor device according to a first aspect of the present disclosure is configured to be mountable on a wiring board having wiring, and includes a first semiconductor element, a second semiconductor element, two first terminals, two second terminals, and a sealing resin portion. The first semiconductor element has two electrodes respectively disposed on two surfaces of the first semiconductor element. The second semiconductor element has two electrodes respectively disposed on two surfaces of the second semiconductor element. The two first terminals are configured to be connected to a part of the wiring in a state of being mounted on the wiring board, electrically connected to the two electrodes of the first semiconductor element, respectively, and arranged side by side in one direction. The two second terminals are configured to be connected to another part of the wiring in the state of being mounted on the wiring board, electrically connected to the two electrodes of the second semiconductor element, respectively, and arranged side by side in the one direction to be adjacent to the two first terminals. The sealing resin portion covers the first semiconductor element, the second semiconductor element, the first terminals, and the second terminals in a state where facing surfaces of the first terminals and the second terminals are exposed from the sealing resin portion. The facing surfaces of the first terminals and the second terminals face the wiring board in the state of being mounted on the wiring board. The facing surfaces of the two first terminals have area ratios different from each other. The facing surfaces of the two second terminals have area ratios different from each other. One of the first terminals is arranged adjacent to both the two second terminals.

In the semiconductor device according to the first aspect, the first terminals and the second terminals are configured as described above. Therefore, in the semiconductor device according to the first aspect, the semiconductor elements can be used as switching elements for an inverter or a semiconductor relay depending on a connection point between the wiring of the wiring board and each of the first terminals and the second terminals while suppressing the increase in size.

An electronic device according to a second aspect of the present disclosure includes the semiconductor device according to the first aspect and a wiring board on which the semiconductor device is mounted and having wiring connected to the two first terminals and the two second terminals.

The electronic device according to the second aspect can exhibit the same effects as those of the first aspect.

Hereinafter, multiple embodiments of the present disclosure will be described with reference to the drawings. In each embodiment, portions corresponding to those described in the preceding embodiment are denoted by the same reference numerals, and redundant descriptions will be omitted in some cases. In each embodiment, in a case where only a part of the configuration is described, another preceding embodiment can be referenced to and applied to the other parts of the configuration. Hereinafter, three directions perpendicular to each other are denoted as an X direction, a Y direction, and a Z direction.

First Embodiment

A semiconductor device100according to a first embodiment of the present disclosure will be described with reference toFIGS.1to8B. As shown inFIGS.1,2, and3, the semiconductor device100includes two semiconductor elements, that is, a first semiconductor element1and a second semiconductor element2, two lead frames, and two clips3and4, and sealing resin portion7. The semiconductor device100is configured to be mountable on a printed circuit board200having wires210and220. The wires210and220may be referred to as wiring. The printed circuit board200corresponds to a wiring board. A structure including the semiconductor device100and the printed circuit board200on which the semiconductor device100is mounted corresponds to an electronic device.

InFIG.1, a part of the sealing resin portion7is omitted in order to simplify the drawing and make each component easy to understand. That is, inFIG.1, the portion of the sealing resin portion7that covers the two semiconductor elements1and2, the two lead frames, and the two clips3and4is omitted.

On both sides of each of the semiconductor elements1and2, electrodes are formed. As an example, a metal-oxide semiconductor field-effect transistor (MOSFET) is adopted as each of the semiconductor elements1and2. However, the present disclosure is not limited to this example, and an insulated gate bipolar transistor (IGBT) or the like can also be adopted as each of the semiconductor elements1and2. As another example, a reverse conduction (RC)-IGBT in which an IGBT and a diode are integrated can also be adopted as an each of the semiconductor elements1and2. Further, as each of the semiconductor elements1and2, for example, a semiconductor element having Si as a main component or a semiconductor element having SiC as a main component can be adopted.

As shown inFIGS.1,2, and3, the first semiconductor element1includes a first substrate having a front surface and a rear surface opposite from each other, a first drain electrode13exposed on the rear surface of the first substrate, a first source electrode12and a first gate electrode11exposed on the front surface of the first substrate. The first drain electrode13is formed on substantially the entire area of the front surface of the first substrate. On the other hand, the first gate electrode11and the first source electrode12are partially formed on the rear surface of the semiconductor substrate.

The first substrate has, for example, a rectangular shape in an XY plane and has a thickness in the Z direction. In the present embodiment, as an example, the first substrate in which the Y direction is a longitudinal direction and the X direction is a lateral direction is adopted.

The first semiconductor element1may be formed with a temperature sensor, a current sensor, or the like. In this case, in the first semiconductor element1, a pad electrically connected to the temperature sensor or the current sensor is formed on the same surface as the first gate electrode11and the first source electrode12. Further, the pad is arranged side by side with the first gate electrode11in the X direction, for example.

The second semiconductor element2includes a second substrate, a second drain electrode23exposed on a rear surface of the second substrate, and a second source electrode22and a second gate electrode21exposed on a front surface of the second substrate. The second semiconductor element2has a structure similar to the first semiconductor element1. Therefore, regarding the second semiconductor element2, the description of the first semiconductor element1can be referred to.

The first drain electrode13and the second drain electrode23correspond to rear surface electrodes. The first source electrode12and the second source electrode22correspond to front surface electrodes.

In the semiconductor device100, the first semiconductor element1and the second semiconductor element2are arranged in opposite directions. That is, the first semiconductor device100is arranged so that the arrangement direction of the first gate electrode11and the first source electrode12is opposite to the arrangement direction of the second gate electrode21and the second source electrode22.

The two lead frames include a first lead frame for the first semiconductor element1and a lead frame for the second semiconductor element2. The first lead frame has a first drain terminal51, a first source terminal52, and an external connection terminal6. The first drain terminal51and the first source terminal52correspond to two first terminals. The first lead frame may contain a conductive material as a main component. The conductive material is a metallic material such as Cu, Fe, or an alloy thereof. The first drain terminal51, the first source terminal52, and the external connection terminal6are separated from each other.

Each of the terminals51,52, and6is a plate-shaped member. Further, each of the terminals51,52, and6has a rectangular surface along the XY plane. Each of the terminals51,52, and6has sidewalls perpendicular to the XY plane. Therefore, in the first drain terminal51, the area of one surface on which the first semiconductor element1is mounted and the area of the surface opposite to the one surface are substantially the same, but may be different. This is the same for the other terminals52and6.

As shown inFIGS.2and3, the first semiconductor element1is mounted on a mounting surface of the first drain terminal51. More specifically, the first drain terminal51is a portion where the first semiconductor element1is mounted and the first drain electrode13is electrically connected. The first drain terminal51is electrically connected to the first drain electrode13via a conductive connecting member such as solder. Therefore, the first semiconductor element1is mounted on the first drain terminal51by electrically connecting the first drain electrode13and the first drain terminal51via the conductive connecting member. In the present embodiment, solder is used as the conductive connecting member. The first drain terminal51corresponds to a first rear surface terminal.

As shown inFIG.2, the first source terminal52is electrically connected to the first source electrode12via a first clip3described later. In this way, the first source terminal52is not mounted with the first semiconductor element1, and is electrically connected to the first semiconductor element1(first source electrode12) via the first clip3. The first source terminal52corresponds to a first front surface terminal. In this way, the first drain terminal51and the first source terminal52are electrically connected to the electrodes13and12of the first semiconductor element1.

The first lead frame has a first terminal surface S21that is the opposite surface of the mounting surface of the first semiconductor element1in the first drain terminal51and the opposite surface of the connection surface of the first clip3in the first source terminal52. The first terminal surface S21corresponds to a facing surface.

The first terminal surface S21is exposed from the sealing resin portion7described later. Therefore, the first drain terminal51and the first source terminal52have a function as a heat sink for radiating heat generated from the first semiconductor element1in addition to the function as an electric wiring. Therefore, the first terminal surface S21can be said to be a heat dissipation surface. In the first drain terminal51and the first source terminal52, the portion exposed from the sealing resin portion7is connected to a part of the wires210and220in a state where the semiconductor device100is mounted on the printed circuit board200.

As the mounting surface, the connecting surface, and the first terminal surface S21, for example, a flat surface can be adopted. Further, the first terminal surface S21of the first drain terminal51and the first terminal surface S21of the first source terminal52are configured to be flush with each other.

Further, as shown inFIG.1, the first drain terminal51and the first source terminal52are arranged side by side in one direction. In the present embodiment, an example in which the first drain terminal51and the first source terminal52are arranged side by side in the Y direction is adopted. The area ratio of the first terminal surface S21is different between the first drain terminal51and the first source terminal52. That is, the first drain terminal51and the first source terminal52have different surface areas along the XY plane. The first terminal surface S21of the first drain terminal51is wider than the first terminal surface S21of the first source terminal52.

The second lead frame has a second drain terminal53, a second source terminal54, and an external connection terminal6. The target of the second lead frame to be connected and mounted is the second semiconductor element2, but the configuration is similar to that of the first lead frame. Therefore, regarding the second lead frame, the description of the first lead frame can be referred to. For example, as shown inFIG.1, the second drain terminal53and the second source terminal54are arranged side by side in one direction, and the area ratio of the first terminal surface S21is different. That is, the second drain terminal53and the second source terminal54have different surface areas along the XY plane. The first terminal surface S21of the second drain terminal53is wider than the first terminal surface S21of the second source terminal52.

The second drain terminal53corresponds to a second rear surface terminal. The second source terminal54corresponds to a second front surface terminal. Further, the present embodiment adopts the semiconductor device100in which a part of the first drain terminal51protrudes to a position adjacent to the external connection terminal6, and a part of the second source terminal54protrudes to a position adjacent to the external connection terminal6.

In the first source terminal52, the width in the Y direction is defined as a first terminal width LW1, and the width in the X direction is defined as a second terminal width LW2. The width of the first drain terminal51in the Y direction is longer than the first terminal width LW1, and the width of the first drain terminal51in the X direction is the same as the second terminal width LW2.

On the other hand, the width of the second source terminal54in the Y direction is the same as the first terminal width LW1, and the width of the second source terminal54is the same as the second terminal width LW2. The width of the second drain terminal53in the Y direction is longer than the first terminal width LW1, and the width of the second drain terminal53in the X direction is the same as the second terminal width LW2. Further, the width of the second drain terminal53in the Y direction is the same as the width of the first drain terminal51in the Y direction.

A first distance LD1, which is a distance between the first drain terminal51and the first source terminal52, is narrower than the width of the first drain terminal51in the Y direction and the width of the first source terminal52in the Y direction. That is, the first distance LD1is narrower than the first terminal width LW1. An distance between the second drain terminal53and the second source terminal54described below is the same as that of the first distance LD1. The relationship between the distance between the second drain terminal53and the second source terminal54and the width of the second drain terminal53and the second source terminal54in the Y direction is the same as relationship determined in the first drain terminal51and the first source terminal52.

Further, a second distance LD2, which is a distance between the first source terminal52and the second drain terminal53, is narrower than the second terminal width LW2. The distance between the first drain terminal51and the second drain terminal53and the distance between the first drain terminal51and the second source terminal54are the same as the second distance LD2.

The first lead frame and the second lead frame have multiple external connection terminals6. That is, the first lead frame has multiple external connection terminals6. Similarly, the second lead frame has multiple external connection terminals6. The external connection terminals6are arranged side by side in the X direction.

The external connection terminals6of the first lead frame are electrically connected to the first gate electrode11via wires (not shown). Similarly, the external connection terminals6of the second lead frame are electrically connected to the second gate electrode21via wires. The external connection terminals6includes a terminal electrically connected to a pad electrically connected to a temperature sensor or a current sensor.

Further, as shown inFIG.1, the first drain terminal51is arranged adjacent to both the second drain terminal53and the second source terminal54. That is, the first drain terminal51is adjacent to both the second drain terminal53and the second source terminal54in the X direction. Similarly, the second drain terminal53is adjacent to both the first drain terminal51and the first source terminal52in the X direction. Therefore, the first drain terminal51has a first overlap portion51afacing the second drain terminal53. On the other hand, the second drain terminal53has a second overlap portion53afacing the first drain terminal51.

In the semiconductor device100, the arrangement direction of the first drain terminal51and the first source terminal52and the arrangement direction of the second drain terminal53and the second source terminal54are opposite to each other. Therefore, in the semiconductor device100, it can be said that the terminals51and52for the first semiconductor element1and the terminals53and54for the second semiconductor element2are alternately arranged.

The first clip3corresponds to a first bridge member. For example, the first clip3may contain a conductive material such as a metal material such as Cu, Fe or an alloy thereof as a main component. As shown inFIGS.1and2, the first clip3has a first electrode facing portion31facing the first source electrode12, a first terminal facing portion32corresponding to the first source terminal52, and a first connecting portion33connecting the electrode facing portion31and the first terminal facing portion32. The first electrode facing portion31, the first terminal facing portion32, and the first connecting portion33are a block-shaped member configured as an integral body.

The first electrode facing portion31is electrically connected to the first source electrode12via solder. Similarly, the first terminal facing portion32is electrically connected to the first source terminal52via solder. In this way, in the first semiconductor element1, the first source electrode12and the first source terminal52are electrically connected via the first clip3. In the present embodiment, as an example, the first clip3which has a rectangular shape in the XY plane and has a thickness in the Z direction is adopted.

A second clip4corresponds to a second bridge member. The second clip4has a second electrode facing portion41, a second terminal facing portion42, and a second connecting portion43. The second clip4is connected to the second semiconductor element2, but has a configuration similar to the first clip3. Therefore, regarding the second clip4, the description of the first clip3can be referred to.

In the present disclosure, instead of the clips3and4, a wire containing aluminum, copper or the like as a main component can be adopted. However, since the clips3and4have lower resistance than the wire, a large current can be passed with low loss, and a current can be passed from the entire source electrodes12and22of the semiconductor elements1and2. Therefore, the semiconductor device100can keep the source potential constant by using the clips3and4. Further, when a sense MOS is formed in each of the semiconductor elements1and2, the current detection accuracy of the semiconductor device100is improved.

As described above, the clips3and4and the electrodes12and22, and the clips3and4and the terminals52and53are connected by solder. That is, solder is used to fix these components and to pass an electric current. Therefore, it is preferable to use a material having a low resistivity for the solder. For example, as the material for the solder, SnAgCu, which is a lead-free solder, or PbSn containing lead is used. However, the present disclosure is not limited to this, and solders made of other materials can also be adopted. Furthermore, the present disclosure can also adopt Ag paste, molten Ag, or the like.

The sealing resin portion7contains an electrically insulating resin and a filler having a higher thermal conductivity than the electrically insulating resin as constituent materials. That is, in the sealing resin portion7, the filler is embedded in the electrically insulating resin. As the electrically insulating resin, for example, an epoxy resin or the like can be adopted. On the other hand, as the filler, inorganic particles such as alumina can be adopted.

The sealing resin portion7may have electrical insulation and may have a thermal conductivity of 2.2 W or more, for example. The thermal conductivity of the sealing resin portion7can be adjusted depending on the amount and material of the filler. The sealing resin portion7is formed by, for example, injection molding using a mold.

The sealing resin portion7integrally covers the semiconductor elements1and2, both lead frames, the clips3and4, and the wire. It can be said that the sealing resin portion7is sealed while being in contact with them. The sealing resin portion7has a rectangular shape on the XY plane.

As shown inFIGS.2and3, the sealing resin portion7has a resin surface S11and a resin rear surface S12opposite to the resin surface S11. For the resin front surface S11and the resin rear surface S12, for example, a flat surface can be adopted. Further, it can be said that the resin front surface S11and the resin rear surface S12are formed along the XY plane.

Further, the sealing resin portion7covers the semiconductor elements1and2, both lead frames, and the clips3and4in a state where the first terminal surfaces S21of the drain terminals51and53and the source terminals52and54are exposed. The present embodiment adopts an example in which surfaces of the clips3and4opposite from surfaces facing the semiconductor elements1and2are exposed from the sealing resin portion71. That is, in the first clip3, the surface opposite from the surface facing the first gate electrode11and the first source electrode12of the first semiconductor element1is exposed from the sealing resin portion7. Similarly, in the second clip4, the surface opposite from the surface facing the second gate electrode21and the second source electrode22of the second semiconductor element2is exposed from the sealing resin portion7. The resin surface S11is configured to be flush with the first terminal surface S21.

As described above, in the semiconductor device100, the first terminal surface S21is exposed from the sealing resin portion7. Therefore, the first terminal surface S21is connected to a part of the wires210and220in a state whether the first terminal surface S21is mounted on the printed circuit board200. The first terminal surface S21and the wires210and220are connected by a conductive connecting member such as solder.

Here, a manufacturing method of the semiconductor device100will be described. First, the semiconductor elements1and2are manufactured by a wafer process. If necessary, the wafer may be thinned. Since the semiconductor elements1and2are to be older-bonded on both sides, the semiconductor elements1and2are plated with a material that can be solder-bonded, such as nickel. After that, a wafer acceptance test (WAT) is performed to inspect the electrical characteristics in the wafer state, and the wafer is diced.

After that, solder is printed on the first lead frame, and the first semiconductor element1is mounted. Then, the first semiconductor element1and the first clip3are joined by soldering. Similarly, solder is printed on the second lead frame, and the second semiconductor element2is mounted. Then, the second semiconductor element2and the second clip4are joined by soldering. The first semiconductor element1and the second semiconductor element2may be mounted at the same time, and the first clip3and the second clip4may be mounted at the same time, or the above four components may be mounted at the same time. For solder application, thread solder may be used instead of solder printing.

After that, each of the external connection terminals6and the semiconductor elements1or2are connected by wire bonding. As the material of the wire, gold, copper, aluminum or the like can be adopted. Further, the connection between each of the external connection terminals6and the semiconductor elements1or2may be made by soldering a clip instead of the wire.

After that, the outer shape is formed by the sealing resin portion7. Usually, multiple packages are collectively formed in the sealing resin portion7in order to form the multiple packages (semiconductor device100) on both lead frames. Then, it is divided into each semiconductor device100by singulation. After that, the electrical characteristics are confirmed by inspection, visual inspection is carried out, and the product is shipped.

In the semiconductor device100, the area ratio of the first terminal surface S21in the first drain terminal51and the first source terminal52is different, and the area ratio of the first terminal surface S21in the second drain terminal53and the second source terminal54is different. Accordingly, in the semiconductor device100, the first drain terminal51is arranged adjacent to both the second drain terminal53and the second source terminal54, and the second drain terminal53is arranged adjacent to both the first drain terminal51and the first source terminal52.

Therefore, in the semiconductor device100, each of the semiconductor elements1and2is used as a switching element for an inverter or a semiconductor relay depending on the connection points between the wires210and220of the printed circuit board200and the terminals51to54, while suppressing the increase in size. That is, each of the semiconductor elements1and2can be used as a switching element for an inverter or a semiconductor relay while the semiconductor device100is formed in one package. Further, it can be said that the semiconductor device100can have a common package for an inverter and a semiconductor relay. Further, since a large current flows through the wires210and220, the terminal widths LW1, LW2are widened and electric resistance are reduced. In order to widen the terminal widths LW1and LW2, the distances LD1and LD2are made as narrow as possible. In the semiconductor device100, the semiconductor elements1and2may be independently configured depending on the connection points between the wires210and220of the printed circuit board200and the terminals51to54.

Further, since the semiconductor device100is configured as described above, even if the occupancy rate of the first terminal surface S21adjacent to the resin surface S11becomes high, each of the semiconductor elements1and2can be used for a switching element for an inverter or a semiconductor relay.

Here, an example of a mounting structure of the semiconductor device100on the printed circuit board200will be described with reference toFIGS.4to8B.

In the printed circuit board200, the wires210and220are formed on an electrically insulating base member. As the base member, resin, ceramics, or the like can be adopted. Further, as the printed circuit board200, a multilayer board in which the wires210and220are laminated via the base member and a single-layer board in which wires210and220are formed on a surface of the base member can be adopted. The wires210and220are electrically connected to the terminals51to54in a state where the semiconductor device100is mounted on the printed circuit board200.

First, a case where the semiconductor device100is used as an inverter configuration device100awill be described with reference toFIGS.4and5. The inverter configuration device100ahas a structure similar to the semiconductor device100. Further, in this example, the printed circuit board200on which a capacitor110is mounted is adopted. The capacitor110is a snubber capacitor.

As shown inFIG.4, the inverter configuration device100ais mounted on the printed circuit board200, and the first source terminal52and the second drain terminal53are electrically connected via the first wire210. As a result, in the inverter configuration device100a, the terminals51to54are connected as shown inFIG.8A. Then, as shown inFIG.5, the first semiconductor element1and the second semiconductor element2function as switching elements for an inverter. Further, the terminal52and the terminal53are connected to a motor as shown inFIG.19, and a current flows through the inverter configuration device100aas shown by the long dashed double-dotted line inFIG.4. However, the current does not flow in the first semiconductor element1and the second semiconductor element2at the same time, and the current flows in each of the first semiconductor element1and the second semiconductor element2through another inverter configuration device100aat s timing corresponding to a rotation of the motor.

Further, in the inverter configuration device100a, the portion protruding from the first drain terminal51and the portion protruding from the second source terminal54are connected to the capacitor110by wires or the like. The inverter configuration devices100ahas the alternate arrangement as described above. Therefore, in the inverter configuration device100a, the first drain terminal51and the second source terminal54can be arranged closer to each other than when they are not arranged alternately. That is, in the inverter configuration device100a, the first drain terminal51and the second source terminal54can be arranged close to each other while maintaining the planar mounting. In the inverter configuration device100a, the second drain terminal53and the first source terminal52can be arranged similarly.

Therefore, in the inverter configuration device100a, the capacitor110can be arranged at a position close to both the first drain terminal51and the second source terminal54. That is, in the inverter configuration device100a, the distance between the first drain terminal51and the second source terminal54and the capacitor110can be closer than when they are not arranged alternately. As a result, the inverter configuration device100acan reduce the parasitic inductance due to wiring, improve the switching speed of each of the semiconductor elements1and2, and reduce the switching loss of each of the semiconductor elements1and2.

Next, a case where the semiconductor device100is used as a relay configuration device100bwill be described with reference toFIGS.6and7. The relay configuration device100bhas a structure similar to the semiconductor device100.

As shown inFIG.6, the relay configuration device100bis mounted on the printed circuit board200, and the first source terminal52and the second drain terminal53are electrically connected via the first wire210. Accordingly, in the relay configuration device100b, the terminal51to54are connected as shown inFIG.8B. Then, as shown inFIG.7, the first semiconductor element1and the second semiconductor element2function as switching elements of a semiconductor relay. In the relay configuration device100b, a current flows as shown by the long dashed double-dotted line inFIG.6. However, the relay configuration device100bcan also be configured so that a current flows in the direction opposite to the long dashed double-dotted line inFIG.6.

The first embodiment of the present disclosure has been described above. However, the present disclosure is not limited to the above-described embodiment in any manner, and various modifications are possible within a scope that does not depart from the gist of the present disclosure. Hereinafter, as other embodiments of the present disclosure, second to fifth embodiments and first to third modification will be described. The above-described embodiment, the second to fifth embodiments, and the first to third modifications can be carried out individually, but can also be carried out in combination as appropriate. The present disclosure can be performed by various combinations without being limited to the combination described in the embodiments.

A semiconductor device101according to the first modification will be described with reference toFIG.9. Here, the differences between the semiconductor device101and the semiconductor device100will be mainly described. The semiconductor device101is different from the semiconductor device100in a configuration of a sealing resin portion7a. In the semiconductor device101, the same reference numerals are given to the same components as those of the semiconductor device100. Therefore, the components having the same reference numerals can be applied with reference to the above embodiment. The cross-sectional view ofFIG.9corresponds to the cross-sectional view ofFIG.3.

The sealing resin portion7ais made of a material similar to the sealing resin portion7. However, as shown inFIG.9, the sealing resin portion7ahas a surface layer resin portion71aformed above the clips3and4. That is, in the semiconductor device101, the clips3and4are covered with the sealing resin portion7awithout being exposed from the sealing resin portion7a. Accordingly, the semiconductor device101can secure the electrical insulation of the clips3and4.

The surface layer resin portion71ahas a thickness at least 1 time a particle size of the filler. As a result, the sealing resin portion7ahave the surface layer resin portion71acontaining the filler. That is, the sealing resin portion7acan secure electrical insulation while maintaining the thermal conductivity of the filler. In other words, the sealing resin portion7acan secure heat dissipation and electrical insulation.

When the thickness of the surface layer resin portion71ais about the particle size of the filler, it can be said that one resin layer of the sealing resin portion7ais formed above the clips3and4. Further, it can be said that the sealing resin portion7aincludes the surface layer resin portion71ahaving a thickness of 1 time or more the particle size of the filler.

The surface layer resin portion71apreferably has a thickness of 0.2 mm or more and 0.6 mm or less. The thickness of the surface layer resin portion71ais the thickness in the Z direction. The thickness of the surface layer resin portion71acan be adjusted by adjusting a size of a cavity of a mold.

It is conceivable that the thickness of the surface layer resin portion71avaries depending on a tolerance of a shape and a thickness the clips3and4, a tolerance of solder formed on both sides of the semiconductor elements1and2, and a tolerance of a plate thickness of the lead frame. The inventors examined the thickness of the surface layer resin portion71ain consideration of these tolerances and the process capability when molding the sealing resin portion7a. Then, the inventors could obtain the result that the thickness of the surface layer resin portion71ais preferably 0.4 mm±0.2 mm. That is, in the semiconductor device100, by setting the thickness of the surface layer resin portion71ato 0.4 mm 0.2 mm, it is easy to form the surface layer resin portion71acontaining the filler, and heat dissipation and electrical insulation can be ensured.

As described above, since the semiconductor device101is covered with the sealing resin portion7awithout exposing the clips3and4, electrical insulation can be ensured. Further, since the semiconductor device101has a thermal conductivity of 2.2 W or more in the sealing resin portion7a, heat dissipation can be ensured. That is, the semiconductor device101can secure electrical insulation and heat dissipation without providing an electrically insulating heat dissipation gel or the like on the clips3and4. In other words, the semiconductor device101can secure electrical insulation and heat dissipation without additional component. Therefore, the semiconductor device101does not need to guarantee electrical insulation and heat dissipation on a user side such as a delivery destination. The semiconductor device101can have effects similar to the semiconductor device100.

Second Embodiment

A semiconductor device102of the second embodiment will be described with reference toFIGS.10to14. Here, the differences between the semiconductor device102and the semiconductor device100will be mainly described. The semiconductor device102is different from the semiconductor device100in that an application specific integrated circuit (ASIC)9is provided. In the semiconductor device102, the same reference numerals are given to the same components as those of the semiconductor device100. Therefore, the components having the same reference numerals can be applied with reference to the above embodiment.

In the present embodiment, the shapes of the terminals51to54and the shapes of the clips3and4are different from those of the above embodiment, but they are not essential differences. Therefore, in the present embodiment, the same reference numerals as those in the above-described embodiment are given for convenience.

As shown inFIGS.11and13, the semiconductor device102is configured in a manner similar to the semiconductor device100. However, as shown inFIGS.10and12, in the semiconductor device102, the ASIC9is mounted above the second source terminal54.

As shown inFIG.14, the semiconductor device102includes a first input terminal61, a second input terminal62, a power supply terminal63, and a ground terminal64as external connection terminals6. Further, the semiconductor device102includes a charge pump circuit (CP)91that supplies power to a drive circuit93described later. The charge pump circuit91is separated from a power supply (PS) supplied to each of the terminal51to54. That is, the power supply for the drive circuit93is separated from the power supply for the terminals51to54. The charge pump circuit91corresponds to a power supply for the drive circuit. InFIG.14, a reference numeral93is assigned to the drive circuit configured in the ASIC9.

In the ASIC9, a circuit for driving each of the semiconductor elements1and2is formed. The ASIC9is mounted above the second source terminal54. The ASIC9is connected to the second source terminal54via a silver paste. The ASIC9may be mounted collectively with the semiconductor elements1and2, or may be mounted at different timings from the semiconductor elements1and2.

As described above, a rear surface of the ASIC9is connected to the second source terminal54by the silver paste, so that the ASIC9is grounded. Since the ASIC9does not carry a large current, the ASIC9may be connected to the second source terminal54with the silver paste that does not have a low resistance like solder.

However, the ASIC9may be connected to the second source terminal54by solder instead of the silver paste. In this case, it is necessary to form a plating such as nickel on the rear surface of the ASIC9.

As shown inFIGS.10and14, the ASIC9is connected to the first input terminal61, the second input terminal62, the power supply terminal63, the ground terminal64, and the gate electrodes11and21via the wire8. Accordingly, the ASIC9can be electrically connected to an external device provided outside the semiconductor device102.

As described above, aluminum, copper, gold, or the like can be used for the wire8. Also, in the present disclosure, a clip may be adopted instead of the wire8.

The drive circuit93operates at a voltage in which the voltage of the power supply terminal63is boosted by the charge pump circuit91(power supply circuit). Further, the drive circuit93applies a gate signal to the first semiconductor element1in response to the signal input from the first input terminal61. Similarly, the drive circuit93applies a gate signal to the second semiconductor element2in response to the signal input from the second input terminal62.

Each of the semiconductor element1and2may be provided with a sense MOS or a temperature-sensitive diode. In this case, the ASIC9receives signals from the sense MOS or the temperature sensitive diode via the wire8.

Further, the charge pump circuit91may be built in the ASIC9. Accordingly, the semiconductor device102does not need to add a power supply IC according to the usage environment.

The semiconductor device102can have effects similar to those of the semiconductor device100. Further, since the semiconductor device102is provided with the ASIC9, the semiconductor device102can be used regardless of whether it is on the high side or the low side. Thus, the semiconductor device102can be standardized. Therefore, the semiconductor device102does not need to use a dedicated drive IC or a dedicated drive IC depending on the usage environment, the development period can be shortened, and the resource cost can be reduced. The semiconductor device102may also adopt the surface layer resin portion71aof the first modification.

The mounting location of the ASIC9is not limited to the above example. The ASIC9can be mounted above the first drain terminal51, above the second clip4, above the second source electrode22of the second semiconductor element2, or any other place where the potential fluctuation is small.

A semiconductor device103of the second modification will be described with reference toFIG.15andFIGS.16A to16C. Here, the differences between the semiconductor device103and the semiconductor device102will be mainly described. The semiconductor device103differs from the semiconductor device102in that a capacitor110is connected. In the semiconductor device103, the same reference numerals are given to the same components as those of the semiconductor device102. Therefore, the components having the same reference numerals can be applied with reference to the above embodiment. InFIGS.16A to16C, the semiconductor device103is shown by the dashed line.

As shown inFIG.15, the semiconductor device103is connected to the capacitor110in a manner similar to the inverter configuration device100a. Further, the semiconductor device103is mounted on the printed circuit board200in a manner similar to the inverter configuration device100a. Therefore, the electronic device includes the printed circuit board200on which the semiconductor device103and the capacitor110are mounted. As described above, when the semiconductor device103is used as an inverter configuration device, effects similar to those described above can be obtained by connecting the capacitor110.

As shown inFIG.15andFIGS.16A to16C, the semiconductor device103includes the ASIC9including the drive circuit in a manner similar to the semiconductor device102.FIG.16Ashows an example in which the semiconductor device103is applied to an inverter configuration device and has a power supply terminal for the ASIC9. In this case, the power supply terminal of the ASIC9is connected to a boot strap circuit92. As a result, the semiconductor device103can cope with the bootstrap circuit92. That is, the ASIC9can obtain an external power supply.

FIG.16Bshows an example in which the semiconductor device103is applied to an inverter configuration device and is provided with the charge pump circuit91. The charge pump circuit91may be built in the ASIC9. Since the semiconductor device103of this example requires low voltage operation (startability) as in a vehicle, it can be said that the semiconductor device103has the built-in ASIC9provided with the charge pump circuit91.

FIG.16Cshows an example in which the semiconductor device103is applied to a relay configuration device and is provided with the charge pump circuit91. InFIG.16C, an example including a temperature terminal65connected to a temperature sensor is adopted. Since the semiconductor device103of this example needs to hold the MOS on, the charge pump circuit91is required.

The semiconductor device103can have effects similar to those of the semiconductor device102. Further, by sharing a charge pump power output with a cathode side of a diode of the external bootstrap circuit92, the semiconductor device103can acquire power from the built-in charge pump circuit91or the external bootstrap circuit92, and free gate drive becomes possible.

Third Embodiment

A semiconductor device104of the third embodiment will be described with reference toFIG.17andFIGS.18A and18B. Here, the differences between the semiconductor device104and the semiconductor device100will be mainly described. In the semiconductor device104, the orientations of the first terminals51and52and the second terminals53and54are different from those of the semiconductor device100. In the semiconductor device104, the same reference numerals are given to the same components as those of the semiconductor device100. Therefore, the components having the same reference numerals can be applied with reference to the above embodiment.

As shown inFIG.17, in the semiconductor device104, the first drain terminal51and the second drain terminal53are arranged adjacent to each other in the X direction. Further, in the semiconductor device104, the first source terminal52and the second source terminal54are arranged adjacent to each other in the X direction. In this way, in the semiconductor device104, the arrangement direction of the first drain terminal51and the first source terminal52for the first semiconductor element1and the arrangement direction of the second drain terminal53and the second source terminal54for the second semiconductor element2are the same.

Further, the first source terminal52is arranged adjacent to both the second drain terminal53and the second source terminal54in the X direction. Further, the second drain terminal53is arranged adjacent to both the first drain terminal51and the first source terminal52in the X direction. Therefore, the second drain terminal53has a second overlap portion53afacing the first source terminal52. On the other hand, the first source terminal52has a third overlap portion52afacing the second drain terminal53.

As shown inFIG.18AandFIG.18B, the semiconductor device104can be the inverter configuration device100aor the relay configuration device100bby connecting the terminals with the wiring of the printed circuit board200in a manner similar to the first embodiment. The inverter configuration device100ais configured by connecting the first source terminal52and the second drain terminal53with wiring, as shown inFIG.18A. On the other hand, the relay configuration device100bis configured by connecting the first source terminal52and the second source terminal54by wiring, as shown inFIG.18B.

The semiconductor device104can have effects similar to those of the semiconductor device100.

Fourth Embodiment

Semiconductor devices100aand100baccording to the fourth embodiment will be described with reference toFIG.19. The present embodiment adopts an example in which two types of semiconductor devices100aand100bare applied to an electric power steering system (EPS system).FIG.19is a circuit of a power part of the EPS system.

The EPS system includes a three-phase motor400. Further, the EPS system includes the relay configuration device100bused as a power supply relay and a reverse connection prevention relay, and the inverter configuration device100aused as a half bridge of an inverter300. That is, the EPS system includes the semiconductor device100used as the power supply relay and the reverse connection prevention relay, and the semiconductor device100used as the half bridge of the inverter300.

The power relay is a function of stopping the power supply to the EPS circuit and the motor400when the EPS is stopped or when an abnormality occurs. The reverse connection prevention relay is a function to prevent the current from flowing through a built-in diode in the power supply relay when a vehicle battery is reversely connected.

The inverter300is provided three inverter configuration devices100awhich are half bridges, and each of the inverter configuration devices100ais connected to a motor terminal. That is, the inverter300is provided with the inverter configuration devices100arespectively for a U phase, a V phase, and a W phase of the motor400. The inverter300rotates the motor400by turning on and off the semiconductor elements1and2in each of the inverter configuration devices100a.

The EPS system requires a drive circuit to drive the inverter configuration devices100a. The drive circuit may be built in the ASIC9in a manner similar to the above embodiment. The ASIC9may be mounted in a package common to the semiconductor elements1and2, or may be separately configured externally. Further, the EPS system requires a power supply having a voltage higher than the power supply voltage in order to drive the high-side semiconductor elements1and2. Therefore, in the EPS system, the charge pump circuit91and the bootstrap circuit are used as in the above embodiment.

The inverter configuration device100aand the relay configuration device100bcan have effects similar to those of the semiconductor device100. Further, in the present embodiment, the same package (semiconductor device100) can be used for the inverter configuration device100aand the relay configuration device100b. Since the semiconductor device100can be commonly used for different functions in this way, the development efficiency and the production efficiency can be improved.

Fifth Embodiment

A semiconductor device105according to a fifth embodiment will be described with reference toFIGS.20and21. Here, the differences between the semiconductor device105and the semiconductor device101will be mainly described. The semiconductor device105differs from the semiconductor device101in the configurations of the first terminals51band52band the second terminals53band54b. In the semiconductor device105, the same reference numerals are given to the same components as those of the semiconductor device101. Therefore, the components having the same reference numerals can be applied with reference to the above embodiment.

As shown inFIG.20, the first lead frame includes a first gate terminal6a, a first drain terminal51b, and a first source terminal52b. The first drain terminal51bincludes a first portion on which the first semiconductor element1is mounted and a second portion protruding from the first portion. Therefore, the first drain terminal51bcan be regarded as a configuration in which the first drain terminal51and the external connection terminal6are integrated.

The first source terminal52bis composed of multiple members. That is, the first source terminal52bcan be regarded as having a configuration including multiple external connection terminals6. The first gate terminal6ais one of the external connection terminals6.

The second lead frame includes a second gate terminal6b, a second drain terminal53b, and a second source terminal54b. Each terminal6b,53b,54bis the same as each terminal6b,51b,52b.

As shown inFIG.21, the sealing resin portion7bhas a surface layer resin portion71b, similarly to the sealing resin portion7a. The surface layer resin portion71bcorresponds to the surface layer resin portion71a.

The semiconductor device105can have effects similar to those of the semiconductor device101. The configuration of the present embodiment can be applied to other embodiments.

Normally, a solder connection portion connecting a printed circuit board and a semiconductor device is damaged from an outer terminal because stress such as a temperature cycle is strongly applied to the outer terminal. That is, the life of the solder connection portion is shorter at the outer terminal than at the inner terminal. The semiconductor device cannot be electrically bonded between a terminal having a damaged solder joint and the printed circuit board. In this case, the semiconductor device may not operate.

In the semiconductor device105, the gate terminals6aand6bare arranged inside. Therefore, the semiconductor device105is less affected by damage due to the solder life at the gate terminals6aand6b, and the reliability is improved. Further, even if the semiconductor device105has a terminal different from the gate terminals6aand6b, the same effect can be obtained by arranging only one terminal inside. The outside is an end in the X direction. The inside is a place that is not the end in the X direction.

Further, in the semiconductor device105, the drain terminals51band53band the source terminals52band54bare also arranged on the outside. However, since the drain terminals51band53band the source terminals52band54bare also arranged inside the semiconductor device105, the semiconductor device105operates normally even if the outer terminals are damaged.

FIG.22shows a semiconductor device500according to a reference example. The semiconductor device500includes one semiconductor element510, a drain terminal520, a gate terminal530, a source terminal540, a clip550, and a sealing resin portion560. The semiconductor device500has a gate terminal530arranged inside in a manner similar to the semiconductor device105. Therefore, the semiconductor device500is less affected by damage due to the solder life at the gate terminal530, and the reliability is improved in a manner similar to the semiconductor device105. Further, since the semiconductor device500is arranged in the same manner as the semiconductor device105with respect to the drain terminal520and the source terminal540, the same effect as that of the semiconductor device105can be obtained.

A semiconductor device101according to the third modification will be described with reference toFIG.23. Here, the differences between the semiconductor device106and the semiconductor device105will be mainly described. The semiconductor device106differs from the semiconductor device105in the configuration of a sealing resin portion7c. In the semiconductor device106, the same reference numerals are given to the same components as those of the semiconductor device105. Therefore, the components having the same reference numerals can be applied with reference to the above embodiment.FIG.23is a cross-sectional view corresponding toFIG.21.

The semiconductor device106includes the sealing resin portion7c. The sealing resin portion7cis provided in a state where the surface of the second clip4opposite to the surface facing the second semiconductor element2is exposed in a manner similar to the sealing resin portion7. Furthermore, the sealing resin portion7cis provided in a state where the surface of the first clip3opposite to the surface facing the first semiconductor element1is exposed. The semiconductor device106can have effects similar to those of the semiconductor device105.