Managed memory component

The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

TECHNICAL FIELD

This invention relates to integrated circuit modules and, in particular, to integrated circuit modules that provide memory and controller in a compact footprint module.

BACKGROUND

A variety of systems and techniques are known for combining integrated circuits in compact modules. Some techniques are suitable for combining packaged integrated circuits while other techniques are suitable for combining semiconductor die. Many systems and techniques employ flex circuitry as a connector between packaged integrated circuits in, for example, stacks of packaged leaded or chip-scale integrated circuits. Other techniques employ flex circuitry to “package” semiconductor die and function as a substitute for packaging.

Within the group of technologies that stack packaged integrated circuits, some techniques are devised for stacking chip-scale packaged devices (CSPs) while other systems and methods are better directed to leaded packages such as those that exhibit a set of leads extending from at least one lateral side of a typically rectangular package.

Integrated circuit devices (ICs) are packaged in both chip-scale (CSP) and leaded packages. However, techniques for stacking CSP devices are typically not optimum for stacking leaded devices, just as techniques for leaded device stacking are typically not suitable for CSP devices. Few technologies are, however, directed toward combining packaged integrated circuits with semiconductor die.

Although CSP devices are gaining market share, in many areas, integrated circuits continue to be packaged in high volumes in leaded packages. For example, the well-known flash memory integrated circuit is typically packaged in a leaded package with fine-pitched leads emergent from one or both sides of the package. A common package for flash memory is the thin small outline package commonly known as the TSOP typified by leads emergent from one or more (typically a pair of opposite sides) lateral sides of the package.

Flash memory devices are gaining wide use in a variety of applications. Typically employed with a controller for protocol adaption, flash memory is employed in solid state memory storage applications that are supplanting disk drive technologies. However, when flash memory is employed with controller logic, the application footprint typically expands to accommodate the multiple devices required to provide a module that is readily compatible with most memory subsystem interface requirements. Consequently, what is needed is a memory module that includes a controller logic and flash memory storage without substantial increases in footprint or thickness.

SUMMARY OF THE INVENTION

The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce the footprint of the combination. A leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, leads of the leaded packaged IC have a configuration that allows the lower surface of the body of the leaded packaged IC to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest upon the body of the leaded packaged IC either directly or indirectly. Module contacts are provided in a variety of configurations. The leaded packaged IC is preferably a flash memory device and the semiconductor die is preferably a controller.

DETAILED DESCRIPTION

FIG. 1is a side view of an exemplar module10devised in accordance with a preferred embodiment of the present invention. Exemplar module10is comprised of leaded IC12and semiconductor die14each connected to flex circuitry20. In preferred embodiments, leaded IC12is a flash memory circuit and semiconductor die14is a controller. In a preferred embodiment, semiconductor die14is covered by an encapsulate16as shown.

FIG. 2is an enlarged side view of the area marked “A” inFIG. 1of a module devised in accordance with a preferred embodiment of the present invention. As shown inFIG. 2, leaded packaged IC12has upper side29and lower side25and is connected to flex circuitry20through leads24that are connected to leaded circuit pads21along one side of flex circuitry20which is identified as side11in later views. Leads24typically but not always, exhibit feet36. Later views will show embodiments in which leads24do not exhibit feet36. Leads24may be connected to either or both of the sides of flex circuitry20as will be later shown.

Preferably an adhesive33is used between body27of leaded IC12and flex circuit20. Module contacts18which comprise module array18A are, in the depicted embodiment, pads such as those found in land grid array (LGA) but other types of module contacts18may be employed in embodiments of the present invention.

Body27of leaded packaged IC12has a lower surface25that is in contact with flex circuitry20. In this disclosure, “contact” between the lower surface25of leaded packaged IC12and the surface of flex circuit20includes not only direct contact between lower surface or side25of leaded packaged IC12and the flex circuitry but shall include those instances where intermediate materials such as depicted adhesive33is used between the respective leaded packaged IC and flex circuitry. As shown inFIGS. 1 and 2, leaded packaged IC12exhibits lateral sides S1and S2which, as those of skill will recognize, may be in the character of edges or sides and need not be perpendicular in aspect to the upper and lower surfaces29and25, respectively. Leads24are emergent from sides S1and S2in the depicted leaded packaged IC12but those of skill will note that some leaded packaged ICs may have leads emergent from only one side or more than two sides. In the embodiment depicted inFIG. 2, leads24are configured within space SP defined by planes PL and PU which are defined by lower and upper surfaces25and29, respectively, of the leaded IC to allow the lower surface25of the leaded packaged IC12to be in contact with the flex circuitry20(either directly or indirectly) when leaded packaged IC12is connected to the flex.

To realize the contact relationship between the lower side25of the leaded packaged IC12and the flex circuitry, leads24may be modified or reconfigured. This is preferably performed before mounting of the leaded IC to flex circuit20. Those of skill will note that a preferred method for reconfiguration of leads24, if desired, comprises use of a jig to fix the position of body27of the leaded packaged IC and, preferably, support the lead at the point of emergence from the body at sides S1and S2before deflection of the respective leads toward the upper plane PU to confine leads24to the space between planes PL and PU of the leaded packaged IC. This is because typically, leaded packaged ICs such as TSOPs are configured with leads that extend beyond the lower plane PL. In order for the lower surface25of the respective leaded packaged ICs to contact (either directly or through an adhesive or thermal intermediary, for example) the respective surfaces of the flex circuit, the leads24may need to be reconfigured.

Other configurations of leads24may not, however, require or exhibit configurations in which the lead is within space SP and yet lower surface25still exhibits contact with flex circuitry20. For example, inFIG. 3, leaded packaged IC12exhibits a straight lead24that penetrates flex circuitry20and is connected to both sides9and11of flex circuitry20with solder35.

FIG. 4depicts an alternative embodiment in accord with the present invention in which flex circuitry20exhibits lead holes22through which leads24project so that leads24may be connected to leaded IC pads21which, in this instance, are on side9of flex circuitry20rather than side11as depicted in several other Figs. The result is that lower major surface25of leaded packaged IC12contacts flex circuitry20.

FIG. 5depicts yet another technique for connection of leaded packaged IC12to flex circuitry20while realizing contact between lower surface25and flex circuitry20. As shown inFIG. 5, in this embodiment, an area20CA of flex circuitry20is deflected to allow leads24and in particular, feet36of leads24to be connected to leaded IC pads21on side11of flex circuitry20. Again the result is that lower surface25of leaded package IC12is in contact with flex circuitry20.

FIG. 6depicts yet another technique for connecting leaded packaged IC12to flex circuitry20. In the embodiment depicted inFIG. 6, leads24penetrate deflected area20CA of flex circuitry20which, in this embodiment, is deflected toward the body27of leaded packaged IC12rather than away from leaded packaged IC12as shown in earlierFIG. 5. In this depiction, leads24are connected to both sides9and11of flex circuitry20. Leads24are also parallel with lower major surface25as shown. Lower major surface25of leaded packaged IC is in contact with flex circuitry20and, in particular, with side11of flex circuitry20.

FIG. 7depicts an alternative embodiment of the present invention in which flex circuitry20has distal ends20D that are deflected to contact inner side24I of leads24which has, as shown, an inner side24I and an external side24X. Thus, flex circuitry20accomodates the configuration of leads24and lower surface25is in contact with flex circuitry20.

FIG. 8is a perspective view of a module devised in accordance with an embodiment of the present invention. As depicted, semiconductor die14is connected through wire bonds32to flex circuit20. As will be later shown, wire bonds32are attached to flex pads20P along surface9of flex circuitry20. Concurrently, leaded packaged IC12is connected to the other major side of flex circuitry20through leads24.

FIG. 9is a side view of an exemplar module10devised in accordance with a preferred embodiment of the present invention. Die14is shown encapsulated by encapsulate16. A variety of methods can be employed to effectuate the encapsulation of die14and such methods are known to those of skill in the art.

FIG. 10depicts a major side11of flex circuitry20as employed in a preferred embodiment of the present invention. The plurality of leaded IC pads21shown along side11of flex circuitry20provide contact sites for the leads24of leaded IC12. As earlier shown, leaded IC pads21need not be on side11of flex circuitry20if leads24reach side9of flex circuitry20as shown in an earlier Fig. Flex circuitry20is preferably comprised from one or more conductive layers supported by one or more flexible substrate layers. The entirety of flex circuitry20may be flexible or, as those of skill in the art will recognize, the flexible circuitry may be made flexible in certain areas and rigid in other areas such as those areas where leaded packaged IC12is mounted, for example.

FIG. 11depicts major surface9of flex circuit20illustrating module contacts array18A and module contacts18as well as mounted semiconductor die14wire-bond connected to the plurality20A of flex pads20P. InFIG. 11, semiconductor die14is depicted as being mounted on the surface of flex circuitry20. A later alternative embodiment is an example of an embodiment in which semiconductor die14is inset into a window in flex circuitry20.

FIG. 12depicts an enlarged portion of a module10devised in accordance with a preferred embodiment. In the depicted module ofFIG. 12, module contacts18are illustrated as the commonly understood BGA type contacts often found along the surfaces of CSP devices. Other types of contacts may be employed as module contacts18.

FIG. 13depicts a module10devised in accordance with an alternative embodiment in which semiconductor die14is set into a window in flex circuitry20. In the earlier depicted embodiments, semiconductor die14resided on flex circuit20. In the depicted embodiment of an alternative embodiment, flex circuitry20has a window into which is set semiconductor die14. Thus, in such embodiments, die14is not on the surface of flexible circuitry20and although it may be connected to either side of flexible circuitry20, it is shown in enlarged detail inFIG. 16, for example, as being wire-bond connected to the upper surface of flexible circuitry20which corresponds to earlier identified major surface9of flexible circuitry20. Consequently, semiconductor die14is shown with a lower profile than depicted in earlier depictions of this disclosure. In some Figs., a semiconductor die that is inset into a window in flex circuitry20will be identified as die14R which is, as shown, preferably encapsulated as shown to protect, for example, the wire bonds and the die.

As those of skill will recognize, many techniques exist for connecting the leads of leaded packaged IC12to leaded pads21. Such techniques include, as a non-limiting example, use of solder such as solder35shown in several of the preceding Figs., or other conductive attachment. Other forms of bonding other than solder between leaded IC pads21and leads24may also be employed (such as brazing, welding, tab bonding, or ultrasonic bonding, just as examples) but soldering techniques are well understood and adapted for use in large scale manufacturing.

FIG. 14is an enlarged depiction of a portion of module10identified inFIG. 13with the letter “B”. Inset semiconductor die14R is identified in encapsulate16while leaded packaged IC12is shown connected to flex circuitry20through leads24connected to leaded circuit pads21of flexible circuitry20while both the upper and lower surfaces29and25, respectively, of body27of leaded packaged IC12are preferably connected to flexible circuitry20through adhesive33. The identification of “upper” and “lower” surfaces or sides of leaded packaged IC12is with reference to the normal orientation of the device and typically employed, but such oriented terms are not with reference to a relative “up” or “down” in the Figs. Those of skill will understand, therefore, that the identified upper side29is actually seen as being below the lower side25of leaded packaged IC12in the depiction of, for example,FIG. 14when that depiction is viewed.

FIG. 15depicts recessed semiconductor die14R and illustrates the plural die pads14P and plural flex pads20P and the wire bonds32that connect die14R to flex circuit20. Die attach14DA is also shown. As those of skill understand, die attach14DA is typically an adhesive.

FIG. 16is an enlarged depiction showing a cross-sectional view along the line identified as C-C in earlierFIG. 13. Body27of leaded packaged IC12is shown supporting recessed semiconductor die14R which is attached to body27through die attach shown as14DA. Exemplar die pad14P is connected to flex pad20P of flexible circuitry20through wire bond32. The entire connection area is preferable encapsulated with encapsulate16.

FIG. 17depicts flex circuitry20prepared for use with an alternative embodiment that recesses semiconductor die14in a window W in the flex circuitry. Such constructions result in lower profiles for modules10. Leaded pads21are shown along side11of flexible circuitry20.

FIG. 18depicts flex circuitry20prepared for use with a recessed semiconductor die arrangement for module10. Flexible circuitry pads20P along side9and array18A of module contacts18are shown. Window W provides the space through which die14is disposed when a module10in accordance with an alternative embodiment is constructed. For sake of clarity, when semiconductor die14is recessed in a module10it is identified as die14R, while in those instances where die14resides on flex circuitry20, it is identified as semiconductor die14. Those of skill will, however, recognize that a die can be used in either mode, recessed in a window W of flex circuitry20or on the surface of flex circuitry20.

The present invention may also be employed with circuitry other than or in addition to memory such as the flash memory depicted in a number of the present Figs. Other exemplar types of circuitry that may be aggregated in accordance with embodiments of the invention include, just as non-limiting examples, DRAMs, FPGAs, and system stacks that include logic and memory as well as communications or graphics devices. It should be noted, therefore, that the depicted profile for leaded packaged IC12is not a limitation and that leaded packaged IC12does not have to be a TSOP or TSOP-like and the package employed may have more than one die or leads emergent from one, two, three or all sides of the respective package body. For example, a module10in accordance with embodiments of the present invention may employ a leaded packaged IC12that has more than one die within the package and may exhibit leads emergent from only one side of the package.

It will be seen by those skilled in the art that many embodiments taking a variety of specific forms and reflecting changes, substitutions, and alternations can be made without departing from the spirit and scope of the invention. Therefore, the described embodiments illustrate but do not restrict the scope of the claims.