Storing bits with cells in a memory device

Methods, systems, and devices for storing bits, such as N−1 bits, with cells, such as N cells, in a memory device are described. A memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. The memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including storing N−1 bits with N cells in a memory device.

BACKGROUND

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. FeRAM may be able to achieve densities similar to volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device.

DETAILED DESCRIPTION

In some memory systems, multiple cells may be used to store a single bit. For example, in a two-transistor two-memory cell (2TM) memory architecture, two cells may be used together to store the single bit. Using two cells to store the single bit may improve performance (e.g., reliability, latency) relative to other techniques that store, for example, one bit per cell. However, using two cells to store a single bit may reduce the capacity of a memory device relative to other techniques.

The techniques and designs described herein allow a memory device to increase capacity while retaining the performance advantages of using multiple cells to store fewer bits (instead of other techniques that store one bit per cell). Specifically, the techniques and designs described herein enable the storage of N−1 bits using N cells, where N is an integer. For example, three bits may be stored using four cells. In such an example, the first bit may be sensed based on a first pair of memory cells, the second bit may be sensed based on a second pair of memory cells, and the third bit may be sensed based on both the first pair of memory cells and the second pair of memory cells. For instance, the third bit may be sensed based on 1) a first sensing voltage that is generated from the first pair of memory cells and 2) a second sensing voltage that is generated from the second pair of memory cells. Thus, the performance advantages (e.g., improved reliability, faster sensing) of using multiple cells to store one bit may be at least partially maintained while increasing the total number of bits stored by a set of cells.

Features of the disclosure are initially described in the context of systems and dies with reference toFIGS.1and2. Features of the disclosure are described in the context of circuits and waveform diagrams with reference toFIGS.3through7. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to storing N−1 bits with N cells in a memory device as described with reference toFIGS.8through9.

FIG.1illustrates an example of a system100that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110).

Portions of the system100may be examples of the host device105. The host device105may be an example of a processor (e.g., circuitry, processing circuitry, a processing component) within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host device105may refer to the hardware, firmware, software, or any combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host (e.g., host device105).

The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110(e.g., operating as a secondary-type device to the host device105, operating as a dependent-type to the host device105) may respond to and execute commands provided by the host device105through the external memory controller120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host device105may be coupled with one another using a bus135.

The device memory controller155may include components (e.g., circuitry, logic) operable to control operation of the memory device110. The device memory controller155may include hardware, firmware, or instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160.

In some examples, the memory device110may communicate information (e.g., data, commands, or both) with the host device105. For example, the memory device110may receive a write command indicating that the memory device110is to store data received from the host device105, or receive a read command indicating that the memory device110is to provide data stored in a memory die160to the host device105, among other types of information communication.

In some examples, the memory device110may improve performance relative to other techniques by using multiple (e.g., two) cells to store one bit. For instance, the memory device110may use 2N cells to store N bits. But using two cells to store one bit may be an inefficient use of cells. According to the techniques described herein, the memory device110may store N−1 bits using N cells, thus improving the efficiency of the cells while maintaining performance advantages relative to techniques that store one bit per cell (e.g., techniques that use N cells to store N bits).

FIG.2illustrates an example of a memory die200that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The memory die200may be an example of the memory dies160described with reference toFIG.1. In some examples, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG.1.

In some examples, a memory cell205may store a state (e.g., a polarization state, a dielectric charge) representative of the programmable states in a capacitor. The memory cell205may include a logic storage component, such as capacitor240, and a switching component245(e.g., a cell selection component). A first node of the capacitor240may be coupled with the switching component245and a second node of the capacitor240may be coupled with a plate line220. The switching component245may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components. In FeRAM architectures, the memory cell205may include a capacitor240(e.g., a ferroelectric capacitor) that includes a ferroelectric material to store a charge (e.g., a polarization) representative of the programmable state.

The memory die200may include access lines (e.g., word lines210, digit lines215, plate lines220) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. In some examples, word lines210may be referred to as row lines. In some examples, digit lines215may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or their analogues, are interchangeable without loss of understanding. Memory cells205may be positioned at intersections of the word lines210, the digit lines215, or the plate lines220.

Operations such as reading and writing may be performed on memory cells205by activating access lines such as a word line210, a digit line215, or a plate line220. By biasing a word line210, a digit line215, and a plate line220(e.g., applying a voltage to the word line210, digit line215, or plate line220), a single memory cell205may be accessed at their intersection. The intersection of a word line210and a digit line215in a two-dimensional or in a three-dimensional configuration may be referred to as an address of a memory cell205. Activating a word line210, a digit line215, or a plate line220may include applying a voltage to the respective line.

Accessing the memory cells205may be controlled through a row decoder225, a column decoder230, or a plate driver235, or any combination thereof. For example, a row decoder225may receive a row address from the local memory controller265and activate a word line210based on the received row address. A column decoder230may receive a column address from the local memory controller265and activate a digit line215based on the received column address. A plate driver235may receive a plate address from the local memory controller265and activate a plate line220based on the received plate address.

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component245. The capacitor240may be in electronic communication with the digit line215using the switching component245. For example, the capacitor240may be isolated from digit line215when the switching component245is deactivated, and the capacitor240may be coupled with digit line215when the switching component245is activated.

A word line210may be a conductive line in electronic communication with a memory cell205that is used to perform access operations on the memory cell205. In some architectures, the word line210may be in electronic communication with a gate of a switching component245of a memory cell205and may be operable to control the switching component245of the memory cell. In some architectures, the word line210may be in electronic communication with a node of the capacitor of the memory cell205and the memory cell205may not include a switching component.

A digit line215may be a conductive line that couples the memory cell205with a sense component250. In some architectures, the memory cell205may be selectively coupled with the digit line215during portions of an access operation. For example, the word line210and the switching component245of the memory cell205may be operable to selectively couple or isolate the capacitor240of the memory cell205and the digit line215. In some architectures, the memory cell205may be in electronic communication (e.g., constant) with the digit line215.

A plate line220may be a conductive line in electronic communication with a memory cell205that is used to perform access operations on the memory cell205. The plate line220may be in electronic communication with a node (e.g., the cell bottom) of the capacitor240. The plate line220may cooperate with the digit line215to bias the capacitor240during access operation of the memory cell205.

The sense component250may determine a state (e.g., a polarization state, a charge) stored on the capacitor240of the memory cell205and determine a logic state of the memory cell205based on the detected state. The sense component250may include one or more sense amplifiers to amplify the signal output of the memory cell205. The sense component250may compare the signal received from the memory cell205across the digit line215to a reference255(e.g., a reference voltage, a reference line). The detected logic state of the memory cell205may be provided as an output of the sense component250(e.g., to an input/output260), and may indicate the detected logic state to another component of a memory device (e.g., a memory device110) that includes the memory die200.

The local memory controller265may control the operation of memory cells205through the various components (e.g., row decoder225, column decoder230, plate driver235, and sense component250). The local memory controller265may be an example of the local memory controller165described with reference toFIG.1. In some examples, one or more of the row decoder225, column decoder230, and plate driver235, and sense component250may be co-located with the local memory controller265. The local memory controller265may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host device105, another controller associated with the memory die200), translate the commands or the data (or both) into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to a host (e.g., a host device105) based on performing the one or more operations. The local memory controller265may generate row signals and column address signals to activate the target word line210, the target digit line215, and the target plate line220. The local memory controller265also may generate and control various signals (e.g., voltages, currents) used during the operation of the memory die200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die200.

The local memory controller265may be operable to perform one or more access operations on one or more memory cells205of the memory die200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller265in response to various access commands (e.g., from a host device105). The local memory controller265may be operable to perform other access operations not listed here or other operations related to the operating of the memory die200that are not directly related to accessing the memory cells205.

The local memory controller265may be operable to perform a write operation (e.g., a programming operation) on one or more memory cells205of the memory die200. During a write operation, a memory cell205of the memory die200may be programmed to store a desired state (e.g., logic state, charge state). The local memory controller265may identify a target memory cell205on which to perform the write operation. The local memory controller265may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., an address of the target memory cell205). The local memory controller265may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The local memory controller265may apply a signal (e.g., a write pulse, a write voltage) to the digit line215during the write operation to store a specific state (e.g., charge) in the capacitor240of the memory cell205. The signal used as part of the write operation may include one or more voltage levels over a duration.

The local memory controller265may be operable to perform a read operation (e.g., a sense operation) on one or more memory cells205of the memory die200. During a read operation, the state (e.g., logic state, charge state, polarization state) stored in a memory cell205of the memory die200may be evaluated (e.g., read, determined, identified). The local memory controller265may identify a target memory cell205on which to perform the read operation. The local memory controller265may identify a target word line210, a target digit line215, and target plate line220coupled with the target memory cell205. The local memory controller265may activate the target word line210, the target digit line215, and the target plate line220(e.g., applying a voltage to the word line210, digit line215, or plate line220) to access the target memory cell205. The target memory cell205may transfer a signal (e.g., charge, voltage) to the sense component250in response to biasing the access lines. The sense component250may amplify the signal. The local memory controller265may activate the sense component250(e.g., latch the sense component) and compare the signal received from the memory cell205to a reference (e.g., the reference255). Based on that comparison, the sense component250may determine a logic state that is stored on the memory cell205.

In some examples, the memory die200may improve performance and efficiency by using N cells to store N−1 bits. For example, the memory die200may store a first bit using a first pair of cells, may store a second bit using a second pair of cells, and may store a third bit using the first pair of cells and the second pair of cells. To sense the first bit, the memory die200may compare the digit line voltages of the first pair of cells. To sense the second bit, the memory die200may compare the digit line voltages of the second pair of cells. To sense the third bit, the memory die200may compare a first sensing voltage that is based on the digit line voltages of the first pair of cells with a second sensing voltage that is based on the digit line voltages of the second pair of cells. Thus, three bits may be sensed from four cells, and each bit may have two voltage components (e.g., elements) that improve sensing performance relative to other techniques.

FIG.3illustrates an example of a circuit300that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The circuit300may include a first cell305-a, a second cell305-b, a first selection component310-a, and a second selection component310-barranged in a 2TM configuration. In some examples, the first cell305-aand the second cell305-bmay be FeRAM cells. However, the techniques described herein can be implemented using other types of memory cells, including but not limited to DRAM cells.

The 2TM configuration of the cells305may allow for differential sensing in which the voltages output by the cells305are compared to each other to determine a bit value stored by the cells305. Relative to other sensing techniques that rely on reference voltages, differential sensing using two cells may be more reliable (e.g., because the bit value is determined based on the polarity of the output signal rather than the magnitude of the output signal) and faster (e.g., because the difference between the compared voltages may be larger in differential sensing relative to techniques that rely on a reference voltage that is between programming voltages).

The selection components310may be configured to couple the memory cells305with the digit lines320, where coupling refers to establishing a conductive path between the components. For example, the selection component310-amay (e.g., if activated via the word line (WL)325) couple cell305-awith digit line (DL)320-a. And the selection component310-bmay (e.g., if activated via the word line325) couple cell305-bwith digit line320-b. As shown, the selection components310may be coupled with the same word line (e.g., word line325). In other examples, the selection components310may be coupled with respective word lines.

The cells305may be configured to store charge that corresponds to a value (e.g., a decimal value). For example, a cell305may be written to store a first amount of charge (e.g., +x micro-coulomb (μC)) that corresponds to ‘0’ or may be written store a second amount of charge (e.g., −y μC) that corresponds to ‘1.’ Collectively, the values stored by the cells305may represent a bit value. For example, according to coding scheme315, a bit value equal to zero may be represented by cell305-astoring a ‘0’ and cell305-bstoring a ‘1,’ whereas a bit value equal to one may be represented by cell305-astoring a ‘1’ and cell305-bstoring a ‘0.’ A bit value may also be referred to as a data bit value or other suitable terminology.

The cells305may be accessed (e.g., written, read) by applying voltages to a plate line (e.g., plate line (PL)340) coupled with the cells305. For example, different magnitudes and/or polarities of voltage may be used to write the cells305to a ‘1’ or a ‘0.’ To read a cell305, the voltage on the plate line340may be increased to a threshold value that causes the cell305to discharge onto the respective digit line320(assuming the respective word line325is activated). As shown, the cells305may be coupled with the same plate line (e.g., plate line340). In other examples, the cells305may be coupled with respective plate lines.

The sense component (SC)330may be configured to compare input voltages and to output the difference between input voltages as a signal335. For example, the sense component330may compare the voltage of digit line320-a(denoted voltage A) and the voltage of digit line320-b(denoted voltage B). To illustrate, the sense component330may subtract the input voltage at the positive terminal of the sense component330(e.g., voltage B) from the input voltage at the negative terminal of the sense component330(e.g., voltage A) and output the difference. If the difference is negative, the memory device may determine (e.g., according to the coding scheme315) that the stored bit value is equal to one. If the difference is positive, the memory device may determine (e.g., according to the coding scheme315) that the stored bit value is equal to zero. Thus, a bit value may be determined based on the polarity of the signal335, regardless of the magnitude of the difference, which may improve reliability and decrease sensing latency. In some examples, the sense component330may be a differential sense amplifier.

So, two cells305may be used to store one bit value, which may provide various advantages (e.g., reliability advantages, latency advantages) relative to memory architectures that store one bit per cell. But using 2N cells to store N bit values may be an inefficient use of the memory array. According to the techniques described herein, a memory device may store N−1 bit values in N cells by using pairs of cells to store whole bit values as well as partial bit values. For example, a pair of cells that stores a first bit value may be used in conjunction with another pair of cells (which stores a second bit value) to collectively store a third bit value.

FIG.4illustrates an example of a circuit400that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The circuit400may include digit lines DL0through DL7(which may be coupled with respective memory cells) and decoders405for selecting between digit lines for sensing. The circuit400may also include sense components SC0through SC2for sensing bit values from the memory cells and switching components S0, S1, S4, and S5for coupling various components together to enable sensing of N−1 bit values (e.g., three bit values) using N cells (e.g., four cells). The memory cells coupled with the digit lines are omitted from the drawing for visual clarity.

The memory cells coupled with the digit lines may be arranged in 2TM configurations. For example, the circuit400may include a first pair of cells (cell0and cell1, coupled with digit line DL0and DL1, respectively) arranged in a 2TM configuration as illustrated and described with reference toFIG.3. The circuit400may also include a second pair of cells (cell4and cell5, coupled with digit line DL4and DL5mrespectively) arranged in a 2TM configuration. In some examples, the circuit400include additional pairs of cells arranged in 2TM configurations and coupled with DL2, DL3, DL5, and DL6. The cells may be FeRAM cells, DRAM cells, or other types of memory cells.

The circuit400may include word line0(denoted WL0) and various plate lines. Word line0may be coupled with the selection components of the memory cells as illustrated inFIG.3. Plate line0(denoted PL0) may be coupled with the memory cells that are coupled with DL0and DL1(cell0, cell1). Plate line1(denoted PL1) may be coupled with the memory cells that are coupled with DL2and DL3(cell2, cell3). Plate line2(denoted PL2) may be coupled with the memory cells that are coupled with DL4and DL5(cell4, cell5). And plate line3(denoted PL3) may be coupled with the memory cells that are coupled with DL6and DL7(cell6, cell7).

The cells may be configured to store various amounts of charge that correspond to different values (e.g., a decimal values). For example, a cell may be written to store a first amount of charge (e.g., +x μC) that corresponds to ‘0,’ may be written to store a second amount of charge (e.g., 0 μC) that corresponds to ‘0.5,’ or may be written to store a third amount of charge (e.g., −y μC) that corresponds to ‘1.’ Use of three programming levels (as opposed to two programming levels) may enable the storage of N−1 bits using N cells.

The values stored by the cell0and cell1(denoted CO and Cl in the coding scheme415) may collectively represent a first bit value (denoted Bit0), and the values stored by cell4and cell5(denoted C4and C5) may collectively represent a second bit value (denoted Bit1). However, the third bit value (denoted Bit2) may be represented by the values collectively stored by cell0, cell1, cell4, and cell5. Compared to other coding schemes, the coding scheme415may maximize and equalize the voltages at the input terminals of the sense components.

The memory device may implement a first sensing operation to sense Bit0and Bit1, and may implement a second sensing operation to sense Bit2.

To sense Bit0, the memory device may activate the word line and plate line coupled with cell0and cell1(e.g., word line0, plate line0) so that cell0and cell1discharge onto digit line0and digit line1, respectively. Thus, voltage0(denoted V0) may develop on digit line0and voltage1(denoted V1) may develop on digit line1. The memory device may then activate the sense component SC0so that the sense component SC0compares V0with V1and outputs the difference between V0and V1(e.g., as signal0). If signal0is positive, the memory device may determine that Bit0is equal to one; if signal0is negative, the memory device may determine that Bit0is equal to zero.

To sense Bit1, the memory device may activate the word line and plate line coupled with cell4and cell5(e.g., word line0, plate line2) so that cell4and cell5discharge onto digit line4and digit line5, respectively. Thus, voltage4(denoted V4) may develop on digit line4and voltage5(denoted V5) may develop on digit line5. The memory device may then activate the sense component SC1so that the sense component SC1compares V4with V5and outputs the difference between V4and V5(e.g., as signal1). If signal1is positive, the memory device may determine that Bit1is a one; if signal1is negative, the memory device may determine that Bit1is a zero.

To sense Bit2, the memory device may couple together digit line0and digit line1to generate sensing voltage A (denoted SVA) and may couple together digit line4and digit line5to generate sensing voltage B (denoted SVB). Thus, sensing voltage A may be a combination (e.g., average) of V0and V1. And sensing voltage B may be a combination of V4and V5. The memory device may sense Bit2after sensing Bit0and Bit1so that coupling the digit lines together does not impact Bit0and Bit1. Put another way, the memory device may sense Bit0and Bit1during a first sensing stage and may sense Bit2during a second sensing stage after the first sensing stage. Use of DL0, DL1, DL4, and DL5(which are non-adjacent pairs of digit lines) to store three bits (as opposed to use of DL0, DL1, DL3, and DL4, which are adjacent pairs of digit lines) may avoid electrical interference between the digit lines that may otherwise occur during sensing.

The memory device may couple together digit line0and digit line1by activating switching component S0and switching component S1. Coupling together digit line0and digit line1may refer to establishing a conductive path between digit line0and digit line1so that charge-sharing between the digit lines can occur. Switching component S0may be coupled with digit line0, sense component SC0, and sense component SC2, among other components. In some examples, switching component S0may be coupled with a first input terminal of sensing component SC0as well as a first input terminal of sensing component SC2. Switching component S1may be coupled with digit line1, sense component SC0, and sense component SC2, among other components. In some examples, switching component S1may be coupled with a second input terminal of sensing component SC0as well as the first input terminal of sensing component SC2.

The memory device may couple together digit line4and digit line5by activating switching component S4and switching component S5. Coupling together digit line4and digit line5may refer to establishing a conductive path between digit line4and digit line5so that charge-sharing between the digit lines can occur. Switching component S4may be coupled with digit line4, sense component SC1, and sense component SC2, among other components. In some examples, switching component S4may be coupled with a first input terminal of sensing component SC1as well as a second input terminal of sensing component SC2. Switching component S5may be coupled with digit line5, sense component SC1, and sense component SC2, among other components. In some examples, switching component S5may be coupled with a second input terminal of sensing component SC0as well as the second input terminal of sensing component SC2.

Thus, by coupling the digit lines as described, a first sensing voltage (SVA) may develop at the first input terminal of sensing component SC2and a second sensing voltage (SVB) may develop at the second input terminal of sensing component SC2. After generating the sensing voltages, the memory device may activate the sense component SC2so that the sense component SC2compares SVA with SVB and outputs the difference between SVA and SVB (e.g., as signal2). If signal2is positive, the memory device may determine that Bit2is a one; if signal2is negative, the memory device may determine that Bit2is a zero.

In some examples, the circuit400may include decoders405that are coupled with the digit lines and configured to selectively couple pairs of the digit lines with the sense components. For example, decoder405-amay be coupled with DL0, DL1, DL2, and DL3and may be configured to selectively couple either DL0and DL1or DL3and DL4with the sense component SC0. Similarly, decoder405-bmay be coupled with DL4, DL5, DL6, and DL7and may be configured to selectively couple either DL4and DL5or DL6and DL7with the sense component SC2. In some examples, a decoder405may be a multiplexer (e.g., a circuit that accepts multiple input signals and outputs one of those input signals).

Thus, four memory cells (N=4) may be used to store three bits (N−1=3), which may allow the memory device to increase array efficiency while preserving advantages of a 2TM architecture.

FIG.5illustrates an example of a waveform diagram500that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The waveform diagram500illustrates voltages from the circuit400during a sensing process to sense N−1 bit values (e.g., three bit values) from N cells (e.g., four cells). For example, the waveform diagram500represent voltages from sensing cells0,1,4, and5, which may store Bit0=0, Bit1=1, and Bit2=1. Two bits (Bit0, Bit1) may be sensed during a first sensing stage and one bit (Bit2) may be sensed during a second sensing stage. The voltages depicted in the waveform diagram500may be associated with row seven of the coding scheme415, which is partially reproduced inFIG.4.

The waveform diagram500may include word line voltage VWL, which may be the voltage on word line0, and plate line voltage VPL, which may represent the respective voltages on plate line0and plate line2. The waveform diagram500may also include the voltage on digit line0(V0), the voltage on digit line1(V1), the voltage on digit line4(V4), and the voltage on digit line5(V5). For ease of illustration, the voltage associated with ‘1’ is shown as 1 V, the voltage associated with ‘0.5’ is shown as 0.5 V, and the voltage associated with ‘0’ is shown as 0 V.

At time to, the word line voltage VWLmay be increased to activate the selection components coupled with the cell0, cell1, cell4, and cell5. Also at time to, the plate line voltage VPLmay be increased so that the memory cells discharge onto respective digit lines (e.g., digit line0, digit line1, digit line4, digit line5). Thus, the voltage on digit line0(V0) may increase to 0.5 V, the voltage on digit line1(V1) may increase to 1 V, the voltage on digit line4(V4) may increase to 0.5 V, and the voltage on digit line5(V5) may increase to or stay near 0 V.

After the digit line voltages have reached equilibrium (and before time t1), sense component SC0and sense component SC1may be activated to sense Bit0and Bit1. For example, sense component SC0may compare V0and V1and output signal0(denoted Sig0) as −0.5 V based on the comparison (because V0−V1=−0.5 V). Similarly, sense component SC1may compare V4and V5and output signal1(denoted Sig1) as +0.5 V based on the comparison (because V4−V5=+0.5 V). Accordingly, based on the coding scheme415, the memory device may determine that Bit0=0 (because Sig0is negative) and Bit1=1 (because Sig1is positive). Thus, Bit0and Bit1may be sensed during the first sensing phase.

At time t1, the memory device may activate switching component S0and switching component S1to couple digit line0and digit line1with the negative input terminal of sense component SC2. Accordingly, digit line0and digit line1may charge-share causing the voltage on digit line0(V0) and the voltage on digit line1(V1) to reach equilibrium at +0.75 V (e.g., the average voltage of V0and V1). Thus, the voltage at the negative input terminal of sense component SC2(e.g., sensing voltage SVA) may become +0.75 V.

Also at time t1, the memory device may activate switching component S4and switching component S5to couple digit line4and digit line5with the positive input terminal of sense component SC2. Accordingly, digit line5and digit line5may charge-share causing the voltage on digit line4(V4) and the voltage on digit line5(V5) to reach equilibrium at +0.25 V (e.g., the average voltage of V4and V5). Thus, the voltage at the positive input terminal of sense component SC2(sensing voltage SVB) may become +0.25 V.

At time t2, sense component SC2may be activated to sense Bit2. For example, sense component SC2may compare SVA and SVB and output signal2(denoted Sig2) as +0.5 V based on the comparison (because SVA−SVB=+0.5 V). Accordingly, based on the coding scheme415, the memory device may determine that Bit2=1 (because Sig2is positive). Thus, Bit2may be sensed during the second sensing phase.

In summary, two bits may be sensed during the first sensing phase and one bit may be sensed during the second sensing phase, which may allow three bits to be sensed from four memory cells.

FIG.6illustrates an example of a circuit600that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The circuit600may support sensing of N−1 bit values (e.g., seven bit values) using N cells (e.g., eight cells). The circuit600may include sub-circuit605-aand sub-circuit605-b, which may be examples of the circuit400. The memory cells in sub-circuit605-amay store three bit values (Bit0, Bit1, Bit4) and part of Bit6. The memory cells in sub-circuit605-bmay store three bit values (Bit2, Bit3, Bit5) and part of Bit6. The sub-circuit610may be used to sense the seventh bit value (Bit6).

Sub-circuit605-amay operate similarly to the circuit400and so description of sub-circuit605-ais abbreviated for concision. Sub-circuit605-amay include digit lines DL0through DL5, which may be coupled with corresponding memory cells (cell0through cell5) arranged in T2M configurations. Sense component SC0may output Sig0(which represents Bit0) based on the voltages of digit line0and digit line1(denoted V0, V1), and sense component SC1may output Sig1(which represents Bit1) based on the voltages of digit line4and digit line5(denoted V4, V5). Sub-circuit605-amay include switching components615-afor coupling the digit lines together (and with respective input terminals of sense component SC4) so that sense component SC4can output Sig4(which represents Bit4) based on sensing voltage SVA and sensing voltage SVB. As described with reference toFIG.4, sensing voltage SVA may be based on (e.g., equal to the average of) V0and V1, whereas sensing voltage SVB may be based (e.g., equal to the average of) V4and V5.

Sub-circuit605-bmay operate similarly to the circuit400and so description of sub-circuit605-bis abbreviated for concision. Sub-circuit605-bmay include digit lines DL8through DL13, which may be coupled with corresponding memory cells (cell8through cell13) arranged in T2M configurations. Sense component SC2may output Sig2(which represents Bit2) based on the voltages of digit line8and digit line9(denoted V8, V9), and sense component SC3may output Sig3(which represents Bit3) based on the voltages of digit line12and digit line13(denoted V12, V13). Sub-circuit605-bmay include switching components615-bfor coupling the digit lines together (and with respective input terminals of sense component SC5) so that sense component SC5can output Sig5(which represents Bit5) based on sensing voltage SVC and sensing voltage SVD. As described with reference toFIG.4, sensing voltage SVC may be based on (e.g., equal to the average of) V8and V9, whereas sensing voltage SVD may be based (e.g., equal to the average of) V12and V13.

Sub-circuit410may include switching components (S8through S11) for coupling sense components together to generate sensing voltages (e.g., sensing voltage SVE and sensing voltage SVF) associated with Bit6. Sub-circuit410may also include sense component SC6for sensing Bit6. For example, activating switching component S8and switching component S10may couple the input terminals of sense component SC4together and to the negative input terminal of sense component SC6. Thus, sensing voltage SVE may be generated based on sensing voltage SVA and sensing voltage SVB. Similarly, activating switching component S9and switching component S11may couple the input terminals of sense component SC5together and to the positive input terminal of sense component SC6. Thus, sensing voltage SVF may be generated based on sensing voltage SVC and sensing voltage SVD.

The sense component SC6may compare sensing voltage SVE and sensing voltage SVF and output Sig6based on the difference between sensing voltage SVE and sensing voltage SVF. If Sig6is negative, the memory device may determine that Bit6is a zero. If Sig6is positive, the memory device may determine that Bit6is a one. Thus, sub-circuit605-amay be used to sense three bits (e.g., Bit0, Bit1, Bit4), sub-circuit605-bmay be used to sense three bits (e.g., Bit2, Bit3, Bit5), and sub-circuit410may be used to sense one bit (e.g., Bit6), for a total of seven bits.

FIG.7illustrates an example of a waveform diagram700that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The waveform diagram700illustrates voltages from the circuit600during a sensing process to sense N−1 bit values (e.g., seven bit values) from N cells (e.g., eight cells). For example, the waveform diagram700represent voltages from sensing cells0,1,4,5,8,9,12, and13, which may store Bit0=1, Bit1=1, Bit2=0, Bit3=1, Bit4=1, Bit5=1, and Bit6=1. Four bits (Bit0, Bit1, Bit2, Bit3) may be sensed during a first sensing stage, two bits (Bit4, Bit5) may be sensed during a second sensing stage, and one bit (Bit6) may be sensed during a third sensing stage.

The waveform diagram700may include word line voltage VWL, which may be the voltage on a word line coupled with the memory cells in the circuit600, and plate line voltage VPL, which may represent the voltage on the plate lines coupled with the different pairs of memory cells in the circuit600. The waveform diagram700may also include the voltages on the digit lines DL0, DL1, DL4, DL5, DL8, DL9, DL12, DL13(denoted V0, V1, V4, V5, V8, V9, V12, V13, respectively). For ease of illustration, the voltage associated with ‘1’ is shown as 1 V, the voltage associated with ‘0.5’ is shown as 0.5 V, and the voltage associated with ‘0’ is shown as 0 V.

At time to, the word line voltage VWLmay be increased to activate the selection components coupled with the cells in sub-circuit605-a(e.g., cell0, cell1, cell4, cell5) and the cells in sub-circuit605-b(cell8, cell9, cell12, cell13). Also at time t0, the plate line voltage(s) VPLmay be increased so that the memory cells discharge onto respective digit lines (e.g., digit line0, digit line1, digit line4, digit line5, digit line8, digit line9, digit line12, digit line13). Thus, in sub-circuit605-a, the voltage on digit line0(V0) may increase to 1 V, the voltage on digit line1(V1) may increase to 0.5 V, the voltage on digit line4(V4) may increase to 1 V, and the voltage on digit line5(V5) may increase to or stay near 0 V. In sub-circuit605-b, the voltage on digit line8(V0) may increase or stay near 0 V, the voltage on digit line9(V9) may increase to 1 V, the voltage on digit line12(V12) may increase to 0.5 V, and the voltage on digit line13(V13) may increase to or stay near 0 V.

After the digit line voltages have reached equilibrium (and before time t1), sense components in sub-circuit605-aand sub-circuit605-bmay be activated.

In sub-circuit605-a, sense component SC0and sense component SC1may be activated to sense Bit0and Bit1. For example, sense component SC0may compare V0and V1and output signal0(denoted Sig0) as +0.5 V based on the comparison (because V0−V1=+0.5 V). Similarly, sense component SC1may compare V4and V5and output signal1(denoted Sig1) as +1 V based on the comparison (because V4−V5=+1 V). Accordingly, the memory device may determine that Bit0=1 (because Sig0is positive) and Bit1=1 (because Sig1is positive).

In sub-circuit605-b, sense component SC2and sense component SC3may be activated to sense Bit2and Bit3. For example, sense component SC2may compare V8and V9and output signal2(denoted Sig2) as −1 V based on the comparison (because V8−V9=−1 V). Similarly, sense component SC3may compare V12and V13and output signal3(denoted Sig3) as +0.5 V based on the comparison (because V12−V13=+5 V). Accordingly, the memory device may determine that Bit2=0 (because Sig2is negative) and Bit2=1 (because Sig3is positive). Thus, four bits (Bit0, Bit1, Bit2, and Bit3) may be sensed during the first sensing phase.

At time t1, the memory device may activate the switching components in sub-circuit605-aand sub-circuit605-b.

In sub-circuit605-a, the memory device may activate the switching components615-ato A) couple digit line0and digit line1with the negative input terminal of sense component SC4and B) couple digit line4and digit line5with the positive input terminal of sense component SC4. Accordingly, digit line0and digit line1may charge-share causing the voltage at the negative input terminal of sense component SC4(SVA) to become +0.75 V. Similarly, digit line4and digit line5may charge-share causing the voltage at the positive input terminal of sense component SC4(SVB) to become +0.5 V.

In sub-circuit605-b, the memory device may activate the switching components615-bto A) couple digit line8and digit line9with the negative input terminal of sense component SC5and B) couple digit line12and digit line13with the positive input terminal of sense component SC5. Accordingly, digit line8and digit line9may charge-share causing the voltage at the negative input terminal of sense component SC5(SVC) to become +0.5 V. Similarly, digit line12and digit line13may charge-share causing the voltage at the positive input terminal of sense component SC5(SVD) to become +0.25 V.

After the sensing voltages have reached equilibrium (and before time t1), sense component SC4and sense component SC5may be activated to sense Bit4and Bit5. For example, sense component SC4may compare SVA and SVB and output signal4(denoted Sig0) as +0.25 V based on the comparison (because SVA−SVB=+0.25 V). Similarly, sense component SC5may compare SVC and SVD and output signal5(denoted Sig5) as +0.25 V based on the comparison (because SVC−SVD=+0.25 V). Accordingly, the memory device may determine that Bit4=1 (because Sig4is positive) and Bit5=1 (because Sig5is positive). Thus, two bits (Bit4and Bit5) may be sensed during the second sensing phase.

At time t2, the memory device may activate the switching components in sub-circuit410. For example, the memory device may activate switching component S8and switching component S10to couple the input terminals of sense component SC4with the negative input terminal of SC6. Accordingly, the input terminals of sense component SC4may charge-share causing the voltage at the negative input terminal of sense component SC6(sensing voltage SVE) to become +0.625 V. Also at time t2, the memory device may activate switching component S9and switching component S11to couple the input terminals of sense component SC5with the positive input terminal of SC6. Accordingly, the input terminals of sense component SC5may charge-share causing the voltage at the positive input terminal of sense component SC6(sensing voltage SVF) to become +0.325 V.

After the sensing voltages have reached equilibrium, sense component SC6may be activated to sense Bit6. For example, sense component SC6may compare SVE and SVF and output signal6(denoted Sig6) as +0.3 V based on the comparison (because SVE−SVF=+0.3 V). Accordingly, the memory device may determine that Bit6=1 (because Sig6is positive). Thus, one bits (Bit6) may be sensed during the third sensing phase.

FIG.8shows a block diagram800of a memory device820that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The memory device820may be an example of aspects of a memory device as described with reference toFIGS.1through7. The memory device820, or various components thereof, may be an example of means for performing various aspects of storing N−1 bits with N cells in a memory device as described herein. For example, the memory device820may include a circuit825, a first sense component830, a second sense component835, a switching circuitry840, a third sense component845, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The circuit825may be configured as or otherwise support a means for generating a first sensing voltage that is based at least in part on a first voltage of a first digit line and a second voltage of a second digit line. In some examples, the circuit825may be configured as or otherwise support a means for generating a second sensing voltage that is based at least in part on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The first sense component830may be configured as or otherwise support a means for determining a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.

In some examples, the second sense component835may be configured as or otherwise support a means for determining a second bit value based at least in part on a difference between the first voltage of the first digit line and the second voltage of the second digit line.

In some examples, the third sense component845may be configured as or otherwise support a means for determining a third bit value based at least in part on a difference between the third voltage of the third digit line and the fourth voltage of the fourth digit line.

In some examples, the circuit825may be configured as or otherwise support a means for combining the first voltage of the first digit line with the second voltage of the second digit line, where the first sensing voltage is generated based at least in part on combining the first voltage of the first digit line with the second voltage of the second digit line.

In some examples, the circuit825may be configured as or otherwise support a means for combining the third voltage of the third digit line with the fourth voltage of the fourth digit line, where the second sensing voltage is generated based at least in part on combining the third voltage of the third digit line with the fourth voltage of the fourth digit line.

In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling the first digit line with the second digit line, where the first sensing voltage is generated based at least in in part on coupling the first digit line with the second digit line. In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling the third digit line with the fourth digit line, where the second sensing voltage is generated based at least in in part on coupling the third digit line with the fourth digit line.

In some examples, the switching circuitry840may be configured as or otherwise support a means for activating a first switching component coupled with a first sense component and a second sense component, where the first digit line is coupled with the second digit line based at least in part on activating the first switching component. In some examples, the switching circuitry840may be configured as or otherwise support a means for activating a second switching component coupled with the first sense component and the second sense component, where the first digit line is coupled with the second digit line based at least in part on activating the second switching component.

In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling the first digit line with a first input of a sense component. In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling the second digit line with the first input of the sense component, where the first sensing voltage is generated by at least in part on coupling the first digit line and the second digit line with the first input of the sense component.

In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling the third digit line with a second input of the sense component. In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling the fourth digit line with the second input of the sense component, where the second sensing voltage is generated by at least in part on coupling the third digit line and the fourth digit line with the second input of the sense component.

In some examples, the switching circuitry840may be configured as or otherwise support a means for coupling each of the first digit line and the second digit line with a second sense component. In some examples, the second sense component835may be configured as or otherwise support a means for determining, before determining the bit value, a second bit value based at least in part on coupling the first digit line and the second digit line with the second sense component.

FIG.9shows a flowchart illustrating a method900that supports storing N−1 bits with N cells in a memory device in accordance with examples as disclosed herein. The operations of method900may be implemented by a memory device or its components as described herein. For example, the operations of method900may be performed by a memory device as described with reference toFIGS.1through8. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware.

At905, the method may include generating a first sensing voltage (e.g., SVA) that is based at least in part on a first voltage of a first digit line and a second voltage of a second digit line. The operations of905may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of905may be performed by a circuit825as described with reference toFIG.8.

At910, the method may include generating a second sensing voltage (e.g., SVB) that is based at least in part on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The operations of910may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of910may be performed by a circuit825as described with reference toFIG.8.

At915, the method may include determining a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage. The operations of915may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of915may be performed by a first sense component830as described with reference toFIG.8.

In some examples, an apparatus as described herein may perform a method or methods, such as the method900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof for performing the following aspects of the present disclosure:Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for generating a first sensing voltage that is based at least in part on a first voltage of a first digit line and a second voltage of a second digit line; generating a second sensing voltage that is based at least in part on a third voltage of a third digit line and a fourth voltage of a fourth digit line; and determining a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a second bit value based at least in part on a difference between the first voltage of the first digit line and the second voltage of the second digit line.Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a third bit value based at least in part on a difference between the third voltage of the third digit line and the fourth voltage of the fourth digit line.Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for combining the first voltage of the first digit line with the second voltage of the second digit line, where the first sensing voltage is generated based at least in part on combining the first voltage of the first digit line with the second voltage of the second digit line.Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for combining the third voltage of the third digit line with the fourth voltage of the fourth digit line, where the second sensing voltage is generated based at least in part on combining the third voltage of the third digit line with the fourth voltage of the fourth digit line.Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for coupling the first digit line with the second digit line, where the first sensing voltage is generated based at least in in part on coupling the first digit line with the second digit line and coupling the third digit line with the fourth digit line, where the second sensing voltage is generated based at least in in part on coupling the third digit line with the fourth digit line.Aspect 7: The method, apparatus, or non-transitory computer-readable medium of aspect 6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for activating a first switching component coupled with a first sense component and a second sense component, where the first digit line is coupled with the second digit line based at least in part on activating the first switching component and activating a second switching component coupled with the first sense component and the second sense component, where the first digit line is coupled with the second digit line based at least in part on activating the second switching component.Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for coupling the first digit line with a first input of a sense component and coupling the second digit line with the first input of the sense component, where the first sensing voltage is generated by at least in part on coupling the first digit line and the second digit line with the first input of the sense component.Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for coupling the third digit line with a second input of the sense component and coupling the fourth digit line with the second input of the sense component, where the second sensing voltage is generated by at least in part on coupling the third digit line and the fourth digit line with the second input of the sense component.Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 8 through 9, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for coupling each of the first digit line and the second digit line with a second sense component and determining, before determining the bit value, a second bit value based at least in part on coupling the first digit line and the second digit line with the second sense component.

It should be noted that the methods described herein are possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 11: An apparatus, including: a first switching component coupled with a first digit line and configured to couple the first digit line with a second digit line and a first input of a sense component; a second switching component coupled with the second digit line and configured to couple the second digit line with the first digit line and the first input of the sense component; a third switching component coupled with a third digit line and configured to couple the third digit line with a fourth digit line and with a second input of the sense component; and a fourth switching component coupled with the fourth digit line and configured to couple the fourth digit line with the third digit line and the second input of the sense component.Aspect 12: The apparatus of aspect 11, further including: the sense component configured to compare a first sensing voltage that is generated based at least in part on coupling the first digit line with the second digit line and a second sensing voltage that is generated based at least in part on coupling the third digit line with the fourth digit line.Aspect 13: The apparatus of aspect 12, further including: a second sense component coupled with the first digit line and the second digit line and configured to compare a first voltage of the first digit line with a second voltage of the second digit line; and a third sense component coupled with the third digit line and the fourth digit line and configured to compare a third voltage of the third digit line with a fourth voltage of the fourth digit line.Aspect 14: The apparatus of any of aspects 11 through 13, further including: a second sense component including a first input coupled with the first switching component and including a second input coupled with the second switching component.Aspect 15: The apparatus of aspect 14, further including: a third sense component including a first input coupled with the third switching component and including a second input coupled with the fourth switching component.Aspect 16: The apparatus of any of aspects 11 through 15, further including: a first sense component coupled with a second sense component via the first switching component and the second switching component and coupled with a third sense component via the third switching component and the fourth switching component.Aspect 17: The apparatus of any of aspects 11 through 16, further including: a first selection component coupled with the first digit line; a second selection component coupled with the second digit line; and a first word line coupled with the first selection component and the second selection component.Aspect 18: The apparatus of any of aspects 11 through 17, further including: a first memory cell coupled with the first digit line; a second memory cell coupled with the second digit line; and a first plate line coupled with the first memory cell and the second memory cell.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 19: An apparatus, including: a memory array including a first memory cell coupled with a first digit line, a second memory cell coupled with a second digit line, a third memory cell coupled with a third digit line, and a fourth memory cell coupled with a fourth digit line; and a controller coupled with the memory array and configured to cause the apparatus to: generate a first sensing voltage that is based at least in part on a first voltage of the first digit line and a second voltage of the second digit line; generate a second sensing voltage that is based at least in part on a third voltage of the third digit line and a fourth voltage of the fourth digit line; and determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.Aspect 20: The apparatus of aspect 19, where the controller is further configured to cause the apparatus to: determine a second bit value based at least in part on a difference between the first voltage of the first digit line and the second voltage of the second digit line; and determine a third bit value based at least in part on a difference between the third voltage of the third digit line and the fourth voltage of the fourth digit line.Aspect 21: The apparatus of any of aspects 19 through 20, where the controller is further configured to cause the apparatus to: couple the first digit line with the second digit line, where the first sensing voltage is generated based at least in in part on coupling the first digit line with the second digit line; and couple the third digit line with the fourth digit line, where the second sensing voltage is generated based at least in in part on coupling the third digit line with the fourth digit line.Aspect 22: The apparatus of any of aspects 19 through 21, where the controller is further configured to cause the apparatus to: couple the first digit line with a first input of a sense component; and couple the second digit line with the first input of the sense component, where the first sensing voltage is generated by at least in part on coupling the first digit line and the second digit line with the first input of the sense component.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (e.g., in conductive contact with, connected with, coupled with) one another if there is any electrical path (e.g., conductive path) between the components that can, at any time, support the flow of signals (e.g., charge, current, voltage) between the components. At any given time, a conductive path between components that are in electronic communication with each other (e.g., in conductive contact with, connected with, coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. A conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

A switching component (e.g., a transistor) discussed herein may represent a field-effect transistor (FET), and may comprise a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components through conductive materials (e.g., metals, alloys). The source and drain may be conductive, and may comprise a doped (e.g., heavily-doped, degenerate) semiconductor region. The source and drain may be separated by a doped (e.g., lightly-doped) semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (e.g., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic device, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).