HYBRID SSD WITH DELTA ENCODING

A storage device includes a controller, a first memory device with a first type of non-volatile memory, and a second memory device with a second type of non-volatile memory. The second type of non-volatile memory may be byte-addressable and may exhibit a lower latency for write operations than the first type of non-volatile memory. The controller may be configured to receive, from a host device, a write request that include a data log. The data log may include first data associated with a first logical block address and second data associated with a second logical block address. The controller may also be configured to, responsive to determining that a size of the data is at least a threshold size, store at least a portion of the first data to the first memory device. The controller may also be configured to, responsive to determining that the size of the first data does not satisfy the threshold size, store the data to the second memory device.

TECHNICAL FIELD

The disclosure generally relates to storage devices, and more particularly, to solid state storage devices.

BACKGROUND

Solid-state drives (SSDs) may be used in computers when relatively low latency is desired. For example, SSDs may exhibit lower latency, particularly for random reads and writes, than hard disk drives (HDDs). This may allow greater throughput for random reads from and random writes to a SSD compared to a HDD. Additionally, SSDs may utilize multiple, parallel data channels to read from and write to memory devices, which may result in high sequential read and write speeds.

SSDs may utilize non-volatile memory (NVM) devices, such as NAND flash memory devices, which continue to store data without requiring persistent or periodic power supply. NAND flash memory devices may be written many times. However, to reuse a particular NAND flash page, the controller typically erases the particular NAND flash block (e.g., during garbage collection). Erasing NAND flash memory devices many times may cause the flash memory cells to lose their ability to store charge, which reduces or eliminates the ability to write new data to the flash memory cells.

SUMMARY

In one example, a storage device includes a controller, a first memory device, and a second memory device. The first memory device includes a first type of non-volatile memory and the second memory device includes a second type of non-volatile memory. The second type of non-volatile memory is byte-addressable and exhibits lower latency for read and/or write operations compared to the first type of non-volatile memory. The controller is configured to receive, from a host device, a write request that includes a data log. The data log includes first data associated with a first logical block address and second data associated with a second logical block address. The data log can include many pieces of data and logical block addresses associated with respective pieces of data. The controller is also configured to, responsive to determining that a size of the first data is at least a threshold size, store at least a portion of the data to the first memory device. The controller is further configured to, responsive to determining that the size of the data is less than the threshold size, or is not a multiple of the threshold size, store at least a portion of the first data to the second memory device.

In another example, a method includes receiving, by a controller of a storage device and from a host device, a write request that includes a data log. The data log includes first data associated with a first logical block address and second data associated with a second logical block address. The method includes, responsive to determining that a size of the first data is at least a threshold size, storing, by the controller, at least a portion of the first data to a first memory device of the storage device, where the first memory device includes a first type of non-volatile memory. The method further includes, responsive to determining that the size of the first data is less than the threshold size, storing, by the controller, the data to a second memory device of the storage device, where the second memory device includes a second type of non-volatile memory, and where the second type of non-volatile memory is byte-addressable and exhibits lower latency for write operations than the first type of non-volatile memory.

In another example, a storage device includes means for receiving a write request that includes a data log. The data log includes first data associated with a first logical block address and second data associated with a second logical block address. The storage device includes, responsive to determining that a size of the first data is at least a threshold size, means for storing at least a portion of the first data to a first memory device of the storage device, where the first memory device comprises a first type of non-volatile memory. The storage device further includes, responsive to determining that the size of the first data is less than the threshold size, means for storing the first data to a second memory device of the storage device, where the second memory device comprises a second type of non-volatile memory, and the second type of non-volatile memory is byte-addressable and exhibits lower latency for write operations than the first type of non-volatile memory.

DETAILED DESCRIPTION

In general, this disclosure describes techniques for managing read and write operations involving a storage device, such as a solid state drive (SSD). A storage device may include two or more different types of non-volatile memory (NVM) devices. For example, the storage device may include a first type of NVM device (e.g., a NAND flash memory device) and a second, different type of NVM device (e.g., magnetoresistive random-access memory (MRAM)) that is byte-addressable and has a lower read and/or write latency than the first NVM device. In other words, the second NVM device may perform read and/or write operations faster than the first NVM device.

The storage device may include a controller that may manage write operations to, and read operations from, the different types of NVM devices. The controller may receive a single write request that includes first data (e.g., a portion of a data log) and a logical block address (LBA) associated with the first data, as well as a second data (e.g., a different portion of the data log) and an LBA associated with the second data. The first data may include at least one physical sector (or logical block) of data (e.g., 4 kilobytes (KB)) and the second data may include less than a physical sector (or logical block) of data (e.g., 1 KB). For example, the first data may include a logical block of data in an initial state, where the first data is associated with a first LBA. The second data may include less than a logical block of data associated with a second LBA. The second data may include one or more changes to pre-existing data (also referred to as one or more deltas). The controller may write the first data to the flash memory device and may write the second data to the other NVM device.

By writing the first data (e.g., at least one physical sector of data) to the flash memory device and writing the second data (e.g., less than one physical sector of data) to the other NVM device, the controller may reduce the number of write operations to the flash memory device. Reducing the number of write operations to the flash memory device may increase the longevity of the flash memory device. Writing only the updated data (as opposed to re-writing the entire logical block of data), and writing the updated data to the other NVM (which may perform write operations faster than the flash memory devices), may also increase write performance.

When performing read operations, the controller may retrieve data (e.g., at least a physical sector of data) associated with an LBA from the flash memory device and/or data (e.g., less than a physical sector of data) associated with the LBA from another (e.g., non-flash) NVM device. If the controller retrieves data from only the non-flash NVM device during a particular read operation no data is read from the flash memory device for this particular read operation), the controller may improve read performance because the non-flash NVM device has lower latency for read operations relative to flash memory devices. When retrieving data from the flash memory device and data from the non-flash NVM device, the controller may simultaneously retrieve the data from flash memory and non-flash memory. The controller may finish retrieving the data from the non-flash NVM device before finishing retrieving the data from flash memory, and may combine the data with minimal (or no) effect on read performance.

FIG. 1is a conceptual and schematic block diagram illustrating an example storage environment2in which storage device6may function as a storage device for host device4, in accordance with one or more techniques of this disclosure. For instance, host device4which may store data to and/or retrieve data from one or more storage devices6. In some examples, storage environment2may include a plurality of storage devices, such as storage device6, which may operate as a storage array. For instance, storage environment2may include a plurality of storages devices6configured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for host device4.

Host device4may include any computing device, including, for example, a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (e.g., laptop) computer, a tablet computer, a set-top box, a mobile computing device such as a “smart” phone, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, or the like. Host device4may include at least one processor54and host memory56. At least one processor24may include any form of hardware capable of processing data and may include a general purpose processing unit (such as a central processing unit (CPU)), dedicated hardware (such as an application specific integrated circuit (ASIC)), configurable hardware (such as a field programmable gate array (FPGA)), or any other form of processing unit configured by way of software instructions, microcode, firmware, or the like. Host memory56may be used by host device4to store information (e.g., temporarily store information). In some examples, host memory56may include volatile memory, such as random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, and the like).

As illustrated inFIG. 1, storage device6may include controller8, non-volatile memory array (NVMA)10, power supply11, volatile memory12, and interface14. In some examples, storage device6may include additional components not shown inFIG. 1for sake of clarity. For example, storage device6may include a printed board (PB) to which components of storage device6are mechanically attached and which includes electrically conductive traces that electrically interconnect components of storage device6, or the like. In some examples, the physical dimensions and connector configurations of storage device6may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5″ data storage device (e.g., an HDD or SSD), 2.5″ data storage device, 1.8″ data storage device, peripheral component interconnect (PCI®), PCI-extended (PCI-X®), PCI Express (PCIe®) (e.g., PCIe® x1, x4, x8, x16, PCIe® Mini Card, MiniPCI®, etc.), M.2, or the like. In some examples, storage device6may be directly coupled (e.g., directly soldered) to a motherboard of host device4.

Storage device6may include interface14for interfacing with host device4. Interface14may include one or both of a data bus for exchanging data with host device4and a control bus for exchanging commands with host device4. Interface14may operate in accordance with any suitable protocol. For example, as described in more detail with reference to the examples ofFIGS. 2-5, interface14may operate according to a serially attached SCSI (SAS) protocol.

However, in other examples, the techniques of this disclosure may apply to an interface14that operates in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA), and parallel-ATA (PATA)), Fibre Channel, small computer system interface (SCSI), Non-Volatile Memory Express (NVMe™), PCI®, PCIe®, or the like. The interface14(e.g., the data bus, the control bus, or both) is electrically connected to controller8, providing a communication channel between host device4and controller8, allowing data to be exchanged between host device4and controller8. In some examples, the electrical connection of interface14may also permit storage device6to receive power from host device4.

Storage device6may include power supply11, which may provide power to one or more components of storage device6. When operating in a standard mode, power supply11may provide power to the one or more components using power provided by an external device, such as host device4. For instance, power supply11may provide power to the one or more components using power received from host device4via interface14. In some examples, power supply11may include one or more power storage components configured to provide power to the one or more components when operating in a shutdown mode, such as where power ceases to be received from the external device. In this way, power supply11may function as an onboard backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, super capacitors, batteries, and the like.

Storage device6also may include volatile memory12, which may be used by controller8to store information. In some examples, controller8may use volatile memory12as a cache. For instance, controller8may store cached information in volatile memory12until the cached information is written to non-volatile memory array10. Volatile memory12may consume power received from power supply11. Examples of volatile memory12include, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, and the like).

Storage device6includes non-volatile memory array (NVMA)10, which includes two or more different types of non-volatile memory. For example, NVMA10includes a first type of NVM15and a second, different type of NVM17. NVM15and NVM17may each include a plurality of memory devices. For example, as illustrated inFIG. 1, NVM15may include memory devices16A-16N (collectively, “memory devices16”) and NVM17may include memory devices18A-18N (collectively, “memory devices18”). Each of memory devices16,18may be configured to store and/or retrieve data. For instance, controller8may store data in memory devices16,18and may read data from memory devices16,18. In some examples, each of memory devices16,18may be referred to as a die. In some examples, each memory device16,18may include more than one die. In some examples, a single physical chip may include a plurality of dies (i.e., a plurality of memory devices16,18). In some examples, each of memory devices16,18may be configured to store relatively large amounts of data (e.g., 128 MB, 512 MB, 1 GB, 4 GB, 16 GB, 64 GB, 128 GB, 512 GB, 1 TB, etc.).

Memory devices16,18may each include any type of NVM devices, such as flash memory devices (e.g., NAND or NOR), phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magnetoresistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory devices. Unlike flash memory devices, PCM devices, ReRAM devices, MRAM devices, and F-RAM devices may not require stale block reclamation (e.g., garbage collection), but still may utilize wear leveling to reduce effects of limited write endurance of individual memory cells. In some examples, PCM, ReRAM, MRAM, and F-RAM devices may have better endurance than flash memory devices. In other words, PCM, ReRAM, MRAM, and F-RAM devices may be capable of performing more read and/or write operations before wearing out compared to flash memory devices.

In examples where memory devices16of NVM15include flash memory devices, each memory device of memory devices16may include a plurality of blocks, each block including a plurality of pages. Each block may include 128 KB of data, 256 KB of data, 2 MB of data, 8 MB of data, etc. In some instances, each page may include 1 kilobyte (KB) of data, 4 KB of data, 8 KB of data, etc. Controller8may write data to and read data from memory devices16at the page level and erase data from memory devices16at the block level. In other words, memory devices16may be page addressable. In examples where memory devices18of NVM17include PCM, ReRAM, MRAM, F-RAM, or similar non-flash NVM devices, each memory device of memory devices18may be byte addressable. In other words, controller8may write to memory devices18in units of a byte and may write to memory devices16in units of a page.

Storage device6includes controller8, which may manage one or more operations of storage device6. For instance, controller8may manage the reading of data from and/or the writing of data to NVMA10. Controller8may represent one of or a combination of one or more of a microprocessor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), or other digital logic circuitry.

In accordance with techniques of this disclosure, controller8may manage writes to, and reads from, different types of non-volatile memory devices within NVMA10. In some examples, NVMA10includes a first type of NVM15and a second, different type of NVM17. NVM15and NVM17may each include a plurality of memory devices. For example, as illustrated inFIG. 1, NVM15includes memory devices16and NVM17includes memory devices18.

NVM15may perform slow read and/or write operations relative to NVM17. In other words, NVM17may exhibit lower latency for read operations and/or write operations compared to NVM15. For example, memory devices16of NVM15may include flash memory devices (e.g., NAND or NOR), which may, in some examples, have read latencies in the tens of microseconds (μs) and write latencies in the hundreds of μs. For instance, the read latency for memory devices16may be between approximately 20 μs and approximately 30 μs and the write latency for memory device16may be between approximately 100 μs and approximately 500 μs.

In contrast, memory devices18may, in some instances, have read latencies in the nanoseconds (ns). As one example, the read latency for memory devices18may be between approximately 3 ns and approximately 60 ns. The write latency, in this example, for memory devices18may be between approximately 10 ns and approximately 1 μs. Examples of memory devices18of NVM17capable of providing such read and write latencies may include phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magnetoresistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), or any other type of memory device that has a lower read and/or write latency compared to memory devices16.

In some examples, NVM17may have better endurance than NVM15. In other words, NVM17may be capable of performing more read and/or write operations before becoming unable to reliably store and retrieve data compared to NVM15. NVM15may also utilize stale block reclamation (e.g., garbage collection) and wear leveling, while NVM17may not need to utilize garbage collection but may still utilize wear leveling to reduce effects of limited write endurance of individual memory cells.

Each memory device of memory devices16and18may include a plurality of blocks, each block including a plurality of pages, and each page including a plurality of bytes. In some examples, the internal architecture of memory devices18of NVM17may be similar to the internal architecture of volatile memory (e.g., DRAM). In some instances, each page may include 1 kilobyte (KB) of data, 4 KB of data, 8 KB of data, etc. In some examples (e.g., where memory devices16of NVM15include flash memory devices), controller8may write data to and read data from memory devices16at the page level and erase data from memory devices16at the block level. In other words, memory devices16may be page addressable. In some examples (e.g., where memory devices18of NVM17include PCM, ReRAM, MRAM, F-RAM, or other non-flash NVM devices), each memory device of memory devices18may be byte addressable. In other words, controller8may write to memory devices18in units of a byte and may write to memory devices16in units of a page.

In operation, controller8may receive a write request from host device4and may determine where to store the data included in the write request. The write request may include a data log that includes metadata and a data payload. The data payload may include data associated with one or more LBAs. In some instances, the data payload may be divided into a number of separate units, referred to herein as “sections.” For instance, a first section of the data payload may include a quantity of data (e.g., a logical block, two logical blocks, etc.), also referred to herein as a data block. In some instances, a second section of the data payload may include one or more changes, also referred to as deltas, to one or more data blocks. The one or more deltas may represent a change to an initial or previous state of the data block. While the payload is described as including a first section of data and a second section of data, it is to be understood that the payload may include additional data blocks associated with other LBAs and/or additional deltas associated with other LBAs.

In some examples, the metadata includes a size of the data log (e.g., a number of bytes) and a number of sections (also referred to as portions of data) in the data payload. The metadata may also include a cyclic redundancy check (CRC) of the data log. In some instances, the metadata indicates a logical block address (LBA) associated with each respective section and a size of each respective section (e.g., a number of bytes). The metadata may also include a flag for each section in the data payload, which may indicate whether the section is compressed.

In response to receiving a data log, controller8may determine an NVM device (e.g., NVM15or NVM17) to store the data included in the data log. In some examples, controller8may determine an NVM device to store each section of data the data payload based on the size of each section of data. For example, controller8may parse the metadata associated with each section of data in the data log to determine the size of each section of data.

Controller8may determine whether a size of a particular section of data satisfies a threshold size. In some instances, controller8may determine that the size of the section satisfies the threshold size if the section of data is at least equal to the threshold size. The threshold size may be a logical block (or physical sector) of data. If the size of the first section is less than the threshold size, controller8may store the section of data to memory devices18of NVM17. For example, if the section of data includes a 1 KB delta and the threshold size equals 4 KB, controller8may determine the delta does not satisfy the threshold size and may store the delta to memory devices18of NVM17.

In response to determining that the section of data satisfies the threshold size, controller8may store at least a portion of the section of data to memory devices16of NVM15. In some examples, controller8may store data from the first section to memory devices16in increments equal to the threshold size. For example, if the threshold size equals 4 KB and the section of data equals 4 KB of data, controller8may store the entire section to memory devices16of NVM15. If the section of data includes 10 KB of data, controller8may extract 8 KB of data from the section and may store the extracted portion of the section to memory devices16. In such an example, controller8may store the remaining 2 KB to memory device18of NVM17. In some instances, controller8may store the entire first section of data to memory device16of NVM15in response to determining the size of the first section satisfies the threshold size.

Because memory devices18of NVM17may be addressable in relatively small units (e.g., bytes) compared to memory devices16of NVM15(e.g., which may be addressable in units of a page), writing the deltas to memory devices18may utilize the overall memory space of storage device6more efficiently than writing the deltas to memory devices16. In some storage devices, re-writing a single page of data to a page addressable memory devices15may involve writing the page to a new physical location, updating (e.g., by a flash-translation layer) a mapping between the logical address and the new physical location, and marking the old pages as stale, which may eventually require erasing an entire block (e.g., performing garbage collection) to re-use the old pages. In contrast, in the techniques described in this disclosure, controller8may store a change to a single byte of data by writing the deltas to memory devices18. As a result, controller8may store updates to data stored at NVMA10in smaller data units while also potentially reducing the number of writes and erasures performed on NVM15.

In this manner, controller8may store at least a portion of each section of a data log that satisfies a threshold size to NVM15and may store each section of the data log that does not satisfy the threshold size to NVM17. Because writes to NVM17may take less time than writes to NVM15(e.g., NVM17may exhibit a lower write latency than NVM15), writing the deltas to NVM17may improve the speed of a write operation. Further, writing the deltas to NVM17may reduce the number of write operations performed at NVM15, which increase the longevity of NVM15.

FIG. 2is a conceptual and schematic block diagram illustrating example details of controller8. In some examples, controller8may include one or more address translation modules22, one or more write modules24, one or more maintenance modules26, and one or more read modules28. In other examples, controller8may include additional modules or hardware units, or may include fewer modules or hardware units. Controller8may include various types of digital logic circuitry, such as any combination of one or more microprocessors, one or more digital signal processors (DSPs), one or more application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), or other types of digital logic circuitry.

Controller8of storage device6(e.g., as shown inFIG. 1) may interface with the host device4ofFIG. 1via interface14and manage the storage of data to and the retrieval of data from memory devices16and18of NVMA10ofFIG. 1. For example, one or more write module24of controller8may manage writes to memory devices16and18. In some examples, controller8may include one or more write modules24that may write data to different memory devices. For instance, a first write module24may write data to memory devices16and a second write module24may write data to memory devices18. For purposes of illustration only, controller8is described as including a single write module24. For instance, write module24may receive a write request that includes a data log from host device4via interface14and may manage writing of the data block(s) and/or delta(s) in the data log to memory devices16and18.

Write module24may communicate with one or more address translation modules22, which manages translation between logical addresses (LBAs) used by host device4to manage storage locations of data and physical addresses used by write module24to direct writing of data to memory devices16and18. In some examples, controller8may include one or more address translation modules22. For instance, a first address translation module22may be associated with memory devices16and a second address translation module22may be associated with memory devices18. For purposes of illustration only, controller8is described as including a single address translation module22. Address translation module22of controller8may utilize an indirection table, also referred to as a mapping table, that translates logical addresses (or logical block addresses) of data stored by memory devices16and18to physical addresses of data stored by memory devices16and18. For example, host device4may utilize the logical block addresses of the data stored by memory devices16and18in instructions or messages to storage device6, while write module24utilizes physical addresses of the data to control writing of data to memory devices16and18. (Similarly, read module28may utilize physical addresses to control reading of data from memory devices16and18.) The physical addresses correspond to actual, physical locations of memory devices16and18. In some examples, address translation module22may store the indirection table in volatile memory12and periodically store a copy of the indirection table to memory devices16and/or18.

In this way, host device4may use a static logical block address for a certain set of data, while the physical address at which the data is actually stored may change. Address translation module22may maintain the indirection table to map the logical block addresses to physical addresses to allow use of the static logical block address by the host device4while the physical address of the data may change, e.g., due to wear leveling, garbage collection, or the like.

As described in more detail with reference toFIG. 3, write module24of controller8may perform one or more operations to manage the writing of data to memory devices16and/or18in response to write requests. For example, write module24may manage the writing of data to memory devices16and/or18by selecting physical locations within memory devices16and/or18to store the data specified in the write request. As discussed above, write module24may interface with address translation module22to update the mapping table based on the selected physical locations.

For instance, write module24may receive a message from host device4that includes a data log, which includes at least one section of data and a logical block address associated with the section of data. Write module24may next determine a physical location of memory devices16and/or18to store the data, and interface with the particular physical location of memory devices16and/or18to actually store the data. Write module24may then interface with address translation module22to update the mapping table to indicate that the logical block address corresponds to the selected physical location(s) within the memory devices16and/or18.

Read module28similarly may control reading of data from memory devices16and/or18in response to a read request. In some examples, controller8may include one or more read modules28that may read data from different memory devices. For instance, a first read module28may read data from memory devices16and a second read module28may read data from memory devices18. For purposes of illustration only, controller8is described as including a single read module28. For example, read module28may receive a read request or other message from host device4requesting data with an associated logical address. Read module28may interface with address translation module22to convert the logical address to a physical addresses using the mapping table. Read module28may then retrieve the data from the physical addresses provided by address translation module22.

Maintenance module26may represent a module configured to perform operations related to maintaining performance and extending the useful life of storage device6(e.g., memory devices16and18). For example, maintenance module26may implement at least one of wear leveling or garbage collection techniques.

FIG. 3is a conceptual diagram illustrating example storage environment2in which a storage device6may perform a write operation, in accordance with one or more techniques of this disclosure.FIG. 3illustrates and describes conceptual and functional elements ofFIGS. 1 and 2, with concurrent reference to the physical components illustrated inFIGS. 1 and 2.

Host device4may store data in host memory56. When sending data from host memory56to storage device6as part of a write request, host device4may generate a data log300. In some examples, host device4may generate a data log by a block layer subsystem or by the file system. Log300may include metadata302and a data payload304. Payload304may include a plurality of data sections306A,306B, and306N (collectively, “sections306”). As described with reference toFIG. 1, in some examples, each section306may include a data block, one or more deltas, or a combination therein. Metadata302of each log entry302may include one or more LBAs associated with the respective payload306. Similarly, metadata302may indicate the size of each portion of data (e.g., each data block or delta) in each section306and a logical address associated with each portion of data in each section306.

Storage device6ofFIG. 1may receive a write request that includes log300and may store the log300in volatile memory12. As illustrated inFIG. 3, section306A includes data block310A, section306B includes delta312B associated with data block310B (which may have been previously stored to memory device15), and section306N includes a plurality of deltas312C-312N associated with data blocks310C-310N (which may have been previously stored to memory device15). Controller8may determine, for each portion of data in the respective sections306, whether the size of each portion of data (e.g., each data block or delta) in the section306satisfies (e.g., is greater than or equal to) a threshold size (e.g., one physical sector or logical block). For instance, write module24ofFIG. 2may parse metadata302after log300is stored in the volatile memory12to determine whether each data block310and/or delta312(e.g., stored in volatile memory12) satisfies the threshold size. As illustrated inFIG. 3, by parsing metadata302, write module24may determine that data block310A satisfies the threshold size, and each delta of deltas3112B-312N does not satisfy the threshold size.

After storing data log300to volatile memory12, write module24may determine an NVM device (e.g., NVM15or NVM17) to store the data received as part of data log300. For example, write module24may store some of the data in log300to a first type of NVM device (e.g., NMV15) and may store other data in log300to a second type of NVM device (e.g., NVM17) that is byte addressable. In some instances, the second type of NVM device exhibits lower read and/or write latencies relative to the first type of NVM device. In response to determining that data block310A is at least equal to the threshold size, write module24may store at least a portion of data block310A NVM15. In some examples, write module24may store data to NVM15in increments of the threshold size. In other words, in some instances, if the threshold size equals 4 KB and data block310A includes 6 KB of data, write module24may store 4 KB from data block310A to NVM15and may store the remaining 2 KB from data block310A to NVM17. In some examples, write module24may store all of data block310A to NVM15in response to determining the data block is at least equal to the threshold size. Either way, address translation module22may select a physical location of NVM15to store at least a portion of the data and write module24may store the data at the respective physical locations of NVM15.

Similarly, write module24may determine that a some of data of log300does not satisfy the threshold size. For example, write module24may determine, based on metadata302, that delta312B of section306B does not satisfy a threshold size and that each of deltas312C-312N does not satisfy the threshold size. In response to determining that each delta of deltas312B-312N do not satisfy the threshold size, write module24may store the deltas312to NVM17. For instance, address translation module22may determine the physical locations of NVM17to store deltas312, and write module24may cause the NVM17to store the deltas312at the particular physical locations associated with each respective delta312.

Storage device6may include one or more mapping tables used to track the physical locations at which data is stored. For instance, address translation module22may manage mapping table308to translate between logical addresses used by host device4and physical address used to actually store data blocks310at NVM15. Mapping table308may be stored in volatile memory12and may also be stored in persistent memory (e.g., NVM15, and/or NVM17).

In some examples, in response to determining a physical location at which to store each respective delta of deltas312, address translation module22may update mapping table308to indicate the physical byte address of NVM17at which each delta312is stored. Address translation module22may also update mapping table308to include a logical block address associated with each delta312and/or a physical byte address of NVM15associated with each respective delta312. For example, as illustrated in Table 1, address translation module22may update mapping table308in response to determining a physical location of NVM17to store each respective delta312. For instance, address translation module22may determine to store delta312B at byte address 0x000F of NVM17, and address translation module22may update mapping table308to indicate that delta312B is associated with LBA310B and is stored at byte address 0x0000F of NVM17. Similarly, address translation module22may update mapping table22to include the physical byte address for each delta312and write module24may store each delta at the respective physical byte address.

Controller8may perform a merge operation to merge data blocks310and one or more deltas312to generate one or more updated data blocks. In some examples, maintenance module26of controller8may perform a merge operation in response to performing garbage collection and/or wear leveling operation or in response to determining that a bit error rate (BER) is greater than a threshold BER. For example, while performing a garbage collection operation, maintenance module26may merge deltas312within NVM17with the respective corresponding data blocks310. For instance, maintenance module26may merge block310B and delta312B to generate an updated data block310B′, block310C and delta312C to generate an updated data block310C′, and so on. In some examples, maintenance module26may merge a subset of deltas312and the corresponding data blocks310. For example, if storage device6stores snapshots of different states of a logical block, maintenance module26may move a data block (e.g.,310B) without merging the data block310B with the corresponding delta312B.

Maintenance module26of controller8may perform a merge operation in response to determining that the number of deltas312satisfies a threshold number of deltas. In some instance, maintenance module26may compare the number of deltas312associated with a particular data block310to a first threshold number of deltas. Maintenance module26may alternatively or additionally compare the total number of deltas312in NVM17to a second threshold number of deltas. In other words, maintenance module26may compare the number of deltas312associated with a particular data block310to one threshold, and/or may compare the total number of deltas312in NVM17to a different threshold. In some instances, maintenance module26may determine whether the number of deltas312satisfies a threshold in response to initiating a garbage collection or wear leveling operation, in response to determining that a BER satisfies a threshold BER, or in response to determining that controller8is idle (e.g., is not performing a read or write operation). In some examples, maintenance module26may periodically determine whether the number of deltas312satisfies a threshold. For example, maintenance module26may compare the number of deltas312to a threshold number of deltas every time a write request is received, after a threshold number of write requests, every time a read request is received, after a threshold number read requests, or at regular time intervals (e.g., once per hour, day, week, month, etc.).

Maintenance module26may query mapping table308to determine how many deltas are included in NVM17and/or how many deltas in NVM17are associated with each data block in NVM15. Maintenance module26may determine that NVM17includes X number of deltas (where X is any integer) and may compare the number of deltas312to a threshold number of deltas (e.g., 10, 50, 250, or any other number). For example, maintenance module26may determine that the number of deltas312associated with a particular data block310satisfies the first threshold number (e.g., 5) of deltas. As another example, if the second threshold number of deltas equals 150 (e.g., the threshold number for all deltas in NVM17equals 150) and maintenance module26determines that the total number of deltas in NVM17equals 200, maintenance module26may determine the total number of deltas satisfies the threshold because the total number of deltas is greater than the second threshold. If maintenance module26determines that either the first or second threshold is satisfied, maintenance module8may perform a merge operation.

In some examples, maintenance module26may perform a merge operation by retrieving one or more data blocks310from NVM15, one or more deltas312associated with data blocks310from NVM17, storing data blocks310and deltas312to volatile memory12or NVMA10, and combining the data block and respective deltas into an updated data block. For instance, maintenance module26may query mapping table308to determine the physical addresses of MAI17used to store each of deltas312, may query a mapping table308to determine the physical addresses of NVM15used to store the data blocks310associated with each delta312, and may retrieve deltas312and the respective data blocks310from NVM17and15, respectively. Maintenance module26may combine each data block310with the respective deltas312to generate an updated data block310′. In response to generating updated data block310′, maintenance module26may write the updated data blocks310′ to NVM15(e.g., to a different physical location) and may update mapping table308to indicate that there are no longer any deltas associated with updated data blocks310′. For example, maintenance module26may delete the deltas312from NVM17or may mark the deltas312as stale. In some examples, maintenance module26may delete the data stored at the physical addresses of NVM17used to store deltas312or may mark the data as stale, such that write module22may reuse the physical addresses to store additional deltas312.

FIG. 4is a conceptual and schematic block diagram illustrating an example storage environment in which a storage device may perform a read operation, in accordance with one or more techniques of this disclosure.FIG. 4illustrates and describes conceptual and functional elements ofFIGS. 1 and 2, with concurrent reference to the physical components illustrated inFIGS. 1 and 2.

Controller8of storage device2may receive, from host device4, a read request to retrieve data associated with a particular LBA. In response to receiving the read request, address translation module22may query a mapping table408to translate the particular LISA to a physical address at which a particular data block is stored. Similarly, address translation module22may query mapping table408to determine whether there are any deltas associated with the particular data block and if so, to determine the physical addresses at which the corresponding deltas412are stored. For instance, the read request may include a request to retrieve data from an LBA associated with data block410B. Address translation module22may determine a physical address at which data block410B is stored and the physical addresses at which deltas412B1-412B2are stored. Read module28may retrieve data block410B from NVM15and deltas412B from NVM17.

In response to retrieving data block410B and deltas412B, read module28of controller8may merge the data block410B and deltas412B to form a current data block410B′. In some instances, the read module28may also receive metadata that describes how to apply deltas412B to data block410B. The metadata may be stored at storage device6(e.g., within volatile memory12) or may be received from host device4as part of the read request. Read module28may load data block410B and deltas412B into a temporary memory (e.g., volatile memory12ofFIG. 1) and may update, within the temporary memory, data block410B with the deltas412B. In other words, current data block410B′ may represent the current state of data block410after updating the data block to include the changes represented by deltas412B. After updating data block410B within the temporary memory to generate current state of data block410B′, read module28may output current state of data block410B′ to host device4. In this way, controller8may respond to the read request from host device4by sending a current copy of the data associated with the particular LISA even though storage device6does not necessarily include all of the most recent data at the same physical location.

In some examples, read module28may retrieve data from only NVM17in response to receiving a read request. For example, host device4may request a small file (e.g., 1 KB of data) that was previously stored to NVM17(e.g., because the size of the file is less than the threshold size). Because, in this example, read module28only needs to retrieve data from NVM17, read module28may retrieve the data faster that if read module28retrieved data from NVM15and NVM17. As a result, in some instances, techniques of this disclosure may improve read performance.

FIG. 5is a flow diagram illustrating an example technique for storing data to a storage device, in accordance with one or more techniques of this disclosure. For ease of illustration, the technique ofFIG. 5will be described with concurrent reference to storage device6ofFIGS. 1-2. However, the techniques may be used with any combination of hardware or software.

Controller8of storage device6may receive a write request from host device4(502). The write request may include a data log300that includes one or more sections of data and a particular logical block address associated with each respective section of data. The data associated with a logical block address may include a data block310, one or more deltas312to a data block, or both. In some examples, the data log300may also include metadata302that indicates a size of the data associated with the logical block address. In some instances, metadata302may indicate an offset from the beginning of a logical block. Controller8may store the data log in a temporary memory of storage device6(e.g., volatile memory12).

Controller8may determine whether the size of the data associated with the logical block address satisfies a threshold size (504). Controller8may determine the size of data by parsing metadata302of log300within volatile memory12. For instance, metadata302may indicate the size of data that is associated with a respective logical block address. In some instances, the threshold size equals a physical sector of data.

In response to determining that the size of the data associated with the logical block address satisfies a threshold size (“Yes” decision of block504), controller8may store at least a portion of the data to a first NVM device15of storage device6(506). For example, controller8may store the data associated with the logical block address to the first NVM device15. For instance, controller8may store data in increments of the threshold size, such that, if the data equals 9 KB of data and the threshold size equals 4 KB, controller8may store 8 KB of data to first memory device15and may store the remaining 1 KB of data to the second NVM device17. In some examples, controller8may store an entire amount of data (e.g., a logical block) to NVM device15in response to determining that a particular data block satisfies the threshold size.

In response to determining that the size of the data associated with the logical block address does not satisfy the threshold size (“NO” decision of block504), controller8may store the data to a second NVM device17of storage device6(508). For instance, controller8store the data to the second NVM device17. In some examples, the second NVM17may be byte-addressable and may exhibit lower latencies for write operations than the first NVM15, For instance, NVM15may include a flash (NAND or NOR) memory device and NVM17may include a PCM device, ReRAM device, MRAM device, or F-RAM device.

FIG. 6is a flow diagram illustrating an example technique for storing data to a storage device, in accordance with one or more techniques of this disclosure. For ease of illustration, the technique ofFIG. 6will be described with concurrent reference to storage device6ofFIGS. 1-3. However, the techniques may be used with any combination of hardware or software.

Controller8of storage device6may receive a write request from host device4(602). The write request may include a data log300that includes one or more sections of data and a logical block address associated with each respective section of data. The data associated with the logical block address may include a data block310, one or more deltas312to a data block, or both. In some examples, the data log300may also include metadata.302, which may indicate a size of the data associated with the logical block address.

Controller8may determine whether the size of the data associated with the logical block address satisfies a threshold size (604). Controller8may determine the size of data by parsing metadata302of log300within volatile memory12. For instance, metadata302may indicate the size of data that is associated with a respective logical block address. In some instances, the threshold size equals a physical sector of data.

In some examples, the data associated with the logical block address may include a data block310. The size of a data block310may be greater than or equal to a physical sector of data. In response to determining that the size of the data associated with the logical block address satisfies (e.g., is greater than or equal to) a threshold size (“Yes” decision of block604), controller8may store at least a portion of the data in a first NVM device15. For instance, controller8may store data in increments of the threshold size, such that, if the data equals 9 KB of data and the threshold size equals 4 KB, controller8may store 8 KB of data to first memory device15and may store the remaining 1 KB of data to the second NVM device17. For instance, controller8may determine a physical location within a first NVM device15to store a first portion of the data (e.g., 8 KB) and may write the data associated with the particular logical block address at the physical location of the first NVM device15of storage device6(606). In some instance, controller8may store a second portion of the data (e.g., the remaining 1 KB) to second NVM device17. The first NVM device15may be a NAND flash memory device. The first NVM device15may be page-addressable. In response to determining a physical location of NVM15at which to store the data, controller8may update a mapping table to indicate the physical page address of NVM15at which the data is located (610).

In some examples, the data associated with the logical block address may include a delta312. A delta312may be as small as one byte. In response to determining that the size of the data associated with the logical block address does not satisfy a threshold size (“No” decision of block604), controller8may store the data in a second NVM device17. For instance, controller8may determine a physical location of the second NVM device17to store the data. In response to determining the physical location of the second NVM device17, controller8may store the data associated with the particular logical block address to the physical location. In some examples, the second NVM17may be byte-addressable. The second. NVM17may exhibit a lower latency for write operations than the first NVM15. For instance, NVM16may include a flash (NAND or NOR) memory device and NVM17may include a PCM device, ReRAM device, MRAM device, or F-RAM device. In response to determining a physical location of NVM17at which to store the data, controller8may update a mapping table308to indicate the physical byte address of NVM17at which the data is located (612).

Controller8may determine whether to perform a merge operation to merge one or more deltas312stored at the second memory device with a corresponding data block310stored at the first memory device (614). For example, controller8may determine whether the number of deltas312stored at the second memory device satisfies (e.g., is greater than or equal to) a threshold number of deltas. In some instances, controller8may query mapping table308to determine the number of deltas312for one logical block. Controller8may determine to perform a merge operation if the number of deltas (e.g., the total number of deltas in NVM17or the number of deltas for one logical block) is greater than the threshold number of deltas. Controller8may, in some examples, determine to perform a merge operation upon initiating a garbage collection operation or a wear leveling operation. In another example, controller8may determine to perform a merge operation if a BER of the first NVM device15and/or second NVM device17is equal to greater than a threshold HER. In some examples, in response to determining not to perform a merge operation (614, “NO” path), controller8may wait to receive a subsequent read or write request from host device4(620).

In response to determining to perform a merge operation (614, “YES” path), controller8may perform a merge operation by merging each delta312with a respective data block310that is associated with the same logical block address as the delta312(616). For example, controller8may combine data block310A and delta312A to generate an updated data block310A′, combine data block310B and delta312B to generate an updated data block310B′, and so on. In response to generating the updated data blocks, controller8may write each updated data block310′ to NVM1.5. In some instances, controller8may, in response to writing updated data blocks310′, delete deltas312N or may mark deltas312N as stale.

Controller8may, in response to merging data block310N and deltas312, may update mapping table308(618). For instance, controller8may update mapping table308to indicate that there are no longer any deltas312associated with the updated data blocks310′ and to indicate the new physical location of data blocks310′. For example, controller8may delete the entries of mapping table308that are associated with deltas312or may mark the entries as stale. In response to updating mapping table308, controller8may wait to receive additional write requests from host device4(620). Host device4may send another write request and controller8may receive the write request (602).

FIG. 7is a flow diagram illustrating an example technique for retrieving data from a storage device, in accordance with one or more techniques of this disclosure. For ease of illustration, the technique ofFIG. 7will be described with concurrent reference to storage device6ofFIGS. 1-4. However, the techniques may be used with any combination of hardware or software.

Controller8of storage device2may receive, from host device4, a read request to retrieve data associated with a particular LBA (702). For instance, the read request may include a request to retrieve data from a particular LBA, such as an LBA associated with data block410B.

In some examples, controller8may retrieve a data block associated with the particular LBA from a first memory device (704). For example, address translation module22of controller8may query an indirection table to translate the particular LBA to a physical address at which a particular data block is stored. In response to determining the physical address at which the data block is stored, read module28may retrieve the data block from NVM15and may store the data block in a temporary memory (e.g., volatile memory12).

Controller8may retrieve one or more deltas associated with the particular LBA from a second memory device (706). For instance, address translation module22may query mapping table408to determine whether there are any deltas associated with the particular data block and to determine the physical addresses at which the corresponding deltas412are stored. In response to determining the physical addresses at which deltas412B1-412B2are stored, read module28may retrieve data block410B from NVM15and deltas412B from NVM17and may store deltas412B in the temporary memory. Controller8may retrieve the one or more deltas from the second memory device at the same time controller8retrieves a data block from the first memory device.

In response to retrieving data block410B and deltas412B, read module28of controller8may merge the data block410B and deltas412B to form a current data block410B′ (708). For instance, read module28may update, within the temporary memory, data block410B with deltas412B. In other words, read module28may generate a current data block410B′ that represents the current state of data block410after updating the data block to include the changes represented by deltas412B.

After generating current data block410B′, read module28may output current data block410B′ to host device4(710). In this way, controller8may respond to the read request from host device4by sending a current copy of the data block associated with the particular LBA.