Semiconductor device and semiconductor module

According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor member, and first and second insulating members. The semiconductor member is located between the second and first electrodes, and includes a first semiconductor region a second semiconductor region between the first semiconductor region and the first electrode, a third semiconductor region between the second semiconductor region and the first electrode, a fourth semiconductor region between the second semiconductor region and the first electrode, a fifth semiconductor region between the first semiconductor region and the second electrode, a sixth semiconductor region between the fifth semiconductor region and the second electrode, and a seventh semiconductor region between the fifth semiconductor region and the second electrode. A portion of the first insulating member is between the third electrode and the semiconductor member. A portion of the second insulating member is between the fourth electrode and the semiconductor member.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-183559, filed on Nov. 2, 2020; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a semiconductor module.

BACKGROUND

For example, it is desirable to reduce the loss in a semiconductor device such as a transistor or the like.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a fourth electrode, a semiconductor member, a first insulating member, and a second insulating member. A direction from the second electrode toward the first electrode is along a first direction. The semiconductor member is located between the second electrode and the first electrode in the first direction. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region located between the first semiconductor region and the first electrode, the second semiconductor region being of a second conductivity type, a third semiconductor region located between the second semiconductor region and the first electrode, the third semiconductor region being of the first conductivity type, a fourth semiconductor region located between the second semiconductor region and the first electrode, the fourth semiconductor region being of the second conductivity type, a fifth semiconductor region located between the first semiconductor region and the second electrode, the fifth semiconductor region being of the second conductivity type, a sixth semiconductor region located between the fifth semiconductor region and the second electrode, the sixth semiconductor region being of the first conductivity type, and a seventh semiconductor region located between the fifth semiconductor region and the second electrode, the seventh semiconductor region being of the second conductivity type. The fourth semiconductor region includes a first impurity concentration of the second conductivity type, a first carrier concentration of the second conductivity type, and a first volume ratio of a volume of the fourth semiconductor region to a volume of the semiconductor member. The seventh semiconductor region includes at least one of a second impurity concentration that is of the second conductivity type and is greater than the first impurity concentration, a second carrier concentration that is of the second conductivity type and is greater than the first carrier concentration, or a second volume ratio that is greater than the first volume ratio. The second volume ratio is a volume ratio of the seventh semiconductor region to the volume of the semiconductor member. A second direction from a portion of the third electrode toward the second semiconductor region crosses the first direction. At least a portion of the third semiconductor region is in at least one of a first position or a second position. The first position is between the fourth semiconductor region and a portion of the third electrode in the second direction. The second position is between the portion of the third electrode and a portion of the second semiconductor region in the second direction. A third direction from a portion of the fourth electrode toward the fifth semiconductor region crosses the first direction. At least a portion of the sixth semiconductor region is in at least one of a third position or a fourth position. The third position is between the seventh semiconductor region and a portion of the fourth electrode in the third direction. The fourth position is between the portion of the fourth electrode and a portion of the fifth semiconductor region in the third direction. At least a portion of the first insulating member is between the third electrode and the semiconductor member. At least a portion of the second insulating member is between the fourth electrode and the semiconductor member.

According to one embodiment, a semiconductor module includes the semiconductor device described above, and a controller electrically connected with the third and fourth electrodes. In a first operation of switching the third electrode from a first potential to a second potential, the controller switches the fourth electrode from a third potential to a fourth potential at a second time before a first time of switching the third electrode from the first potential to the second potential. The second potential is less than the first potential. The fourth potential is greater than the third potential.

First Embodiment

FIGS.1A to1CandFIGS.2A to2Care schematic cross-sectional views illustrating a semiconductor device according to a first embodiment.

FIG.1Bis a line A1-A2cross-sectional view ofFIG.1A.FIG.1Cis a line A3-A4cross-sectional view ofFIG.1A.FIG.2Bis a line A1-A2cross-sectional view ofFIG.2A.FIG.2Cis a line A3-A4cross-sectional view ofFIG.2A.

As shown inFIG.1A, the semiconductor device110according to the embodiment includes a first electrode51, a second electrode52, a third electrode53, a fourth electrode54, a semiconductor member10, a first insulating member41, and a second insulating member42.

The direction from the second electrode52toward the first electrode51is along a first direction. The first direction is taken as a Z-axis direction. One direction perpendicular to the first direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

The semiconductor member10is located between the second electrode52and the first electrode51in the first direction (the Z-axis direction). The semiconductor member10includes a first semiconductor region11of a first conductivity type, a second semiconductor region12of a second conductivity type, a third semiconductor region13of the first conductivity type, a fourth semiconductor region14of the second conductivity type, a fifth semiconductor region15of the second conductivity type, a sixth semiconductor region16of the first conductivity type, and a seventh semiconductor region17of the second conductivity type.

For example, the first conductivity type is an n-type; and the second conductivity type is a p-type. According to the embodiment, the first conductivity type may be the p-type; and the second conductivity type may be the n-type. In the following examples, the first conductivity type is the n-type; and the second conductivity type is the p-type.

The first semiconductor region11is between the second electrode52and the first electrode51. The second semiconductor region12is located between the first semiconductor region11and the first electrode51. The third semiconductor region13is located between the second semiconductor region12and the first electrode51. The fourth semiconductor region14is located between the second semiconductor region12and the first electrode51. In the example, the direction from the third semiconductor region13toward the fourth semiconductor region14crosses the Z-axis direction. For example, the direction from the third semiconductor region13toward the fourth semiconductor region14is along the X-axis direction.

The fifth semiconductor region15is located between the first semiconductor region11and the second electrode52. The sixth semiconductor region16is located between the fifth semiconductor region15and the second electrode52. The seventh semiconductor region17is located between the fifth semiconductor region15and the second electrode52. In the example, the direction from the sixth semiconductor region16toward the seventh semiconductor region17crosses the Z-axis direction. For example, the direction from the sixth semiconductor region16toward the seventh semiconductor region17is along the X-axis direction.

In the example, the semiconductor member10includes an eighth semiconductor region18and a ninth semiconductor region19. The eighth semiconductor region18is located between the first semiconductor region11and the second semiconductor region12. The eighth semiconductor region18is of the first conductivity type. The ninth semiconductor region19is located between the first semiconductor region11and the fifth semiconductor region15. The ninth semiconductor region19is of the first conductivity type.

A second direction from a portion of the third electrode53toward the second semiconductor region12crosses the first direction. The second direction is, for example, the X-axis direction. In the example, at least a portion of the third semiconductor region13is between the fourth semiconductor region14and a portion of the third electrode53in the second direction (e.g., the X-axis direction).

A third direction from a portion of the fourth electrode54toward the fifth semiconductor region15crosses the first direction. In the example, the third direction is along the X-axis direction. The direction from the fourth electrode54toward the fifth semiconductor region15is along, for example, the third direction (e.g., the X-axis direction). In the example, at least a portion of the sixth semiconductor region16is between the seventh semiconductor region17and a portion of the fourth electrode54in the third direction (e.g., the X-axis direction). In the example, the third direction is along the second direction.

The position in the first direction (the Z-axis direction) of a portion11pof the first semiconductor region11is between the position in the first direction of the fourth electrode54and the position in the first direction of the third electrode53. In the example, the third electrode53and the fourth electrode54are between the second electrode52and the first electrode51. In the example, the portion11pof the first semiconductor region11is between the fourth electrode54and the third electrode53in the first direction (the Z-axis direction).

At least a portion of the first insulating member41is between the third electrode53and the semiconductor member10. A portion of the first insulating member41may be located between the third electrode53and the first electrode51.

At least a portion of the second insulating member42is between the fourth electrode54and the semiconductor member10. A portion of the second insulating member42may be located between the fourth electrode54and the second electrode52.

In the semiconductor device110, the following first and second operations can be performed. In the first operation, the current that flows between the first electrode51and the second electrode52can be controlled by the potential of the third electrode53. The potential of the third electrode53is, for example, a potential that is referenced to the potential of the first electrode51. In the first operation, the current flows in the orientation from the second electrode52toward the first electrode51. In the second operation, the current is caused to flow in the orientation from the first electrode51toward the second electrode52by setting the fourth electrode54to a high potential. The semiconductor device110is, for example, an RC-IGBT (Reverse-Conducting Insulated Gate Bipolar Transistor). For example, the first operation corresponds to an IGBT operation. For example, the second operation corresponds to a diode operation. The first electrode51is, for example, an emitter electrode. The second electrode52is, for example, a collector electrode. The third electrode53is, for example, a gate electrode. The fourth electrode54is, for example, a control electrode. The first operation and the second operation may be repeatedly performed.

As shown inFIG.2A, the distance along the first direction (the Z-axis direction) between the second electrode52and the third electrode53is taken as a first distance d1. The distance along the first direction between the second electrode52and the second semiconductor region12is taken as a second distance d2. The first distance d1is less than the second distance d2.

As shown inFIG.2A, the distance along the first direction (the Z-axis direction) between the first electrode51and the fourth electrode54is taken as a third distance d3. The distance along the first direction between the first electrode51and the fifth semiconductor region15is taken as a fourth distance d4. The third distance d3is less than the fourth distance.

For example, the lower end of the third electrode53is lower than the upper end of the first semiconductor region11. For example, the upper end of the fourth electrode54is higher than the lower end of the first semiconductor region11.

In the example, the direction from the third semiconductor region13toward the fourth semiconductor region14crosses the first direction (the Z-axis direction). For example, the direction from the third semiconductor region13toward the fourth semiconductor region14is along the second direction (e.g., the X-axis direction). The direction from the sixth semiconductor region16toward the seventh semiconductor region17crosses the first direction (the Z-axis direction). For example, the direction from the sixth semiconductor region16toward the seventh semiconductor region17is along the second direction (e.g., the X-axis direction).

In the example, at least a portion of the third semiconductor region13is between the fourth semiconductor region14and a portion of the third electrode53. At least a portion of the sixth semiconductor region16is between the seventh semiconductor region17and a portion of the fourth electrode54.

The third semiconductor region13and the fourth semiconductor region14are electrically connected with the first electrode51. The sixth semiconductor region16and the seventh semiconductor region17are electrically connected with the second electrode52.

For example, the second-conductivity-type carrier concentration (e.g., a first carrier concentration) in the fourth semiconductor region14is greater than the second-conductivity-type carrier concentration in the second semiconductor region12. The electrical resistance of the connection with the first electrode51is reduced thereby. For example, a collector-emitter saturation voltage VCE (sat) can be reduced.

For example, the second-conductivity-type carrier concentration (e.g., a second carrier concentration) in the seventh semiconductor region17is greater than the second-conductivity-type carrier concentration in the fifth semiconductor region15. The electrical resistance of the connection with the second electrode52is reduced thereby. For example, the collector-emitter saturation voltage VCE (sat) can be reduced.

For example, the first-conductivity-type carrier concentration in the third semiconductor region13is greater than the first-conductivity-type carrier concentration in the first semiconductor region11. The electrical resistance of the connection with the first electrode51is reduced thereby. For example, the collector-emitter saturation voltage VCE (sat) can be reduced.

For example, the first-conductivity-type carrier concentration in the sixth semiconductor region16is greater than the first-conductivity-type carrier concentration in the first semiconductor region11. The electrical resistance of the connection with the second electrode52is reduced thereby. For example, the collector-emitter saturation voltage VCE (sat) can be reduced.

For example, the first-conductivity-type impurity concentration in the eighth semiconductor region18is greater than the first-conductivity-type impurity concentration in the first semiconductor region. For example, the first-conductivity-type impurity concentration in the ninth semiconductor region19is greater than the first-conductivity-type impurity concentration in the first semiconductor region11.

For example, the first semiconductor region11is an n−-region or an n-region. The third semiconductor region13and the sixth semiconductor region16are, for example, n++-regions. The eighth semiconductor region18and the ninth semiconductor region19are, for example, n+-regions.

For example, the second semiconductor region12and the fifth semiconductor region15are p-regions. For example, the fourth semiconductor region14may be a p+-region, etc. The seventh semiconductor region17may be, for example, a p++-region, etc.

In one example of the embodiment, the second-conductivity-type carrier concentration in the fourth semiconductor region14is different from the second-conductivity-type carrier concentration in the seventh semiconductor region17. According to the embodiment as described below, at least one of the conduction characteristic or the configuration is different between the fourth semiconductor region14and the seventh semiconductor region17.

For example, the fourth semiconductor region14has the first impurity concentration of the second conductivity type. The fourth semiconductor region14has the first carrier concentration of the second conductivity type. The fourth semiconductor region14has a first thickness z1along the first direction (referring toFIG.2A). The fourth semiconductor region14has a first area ratio. The first area ratio is the ratio of the surface area of the fourth semiconductor region14per unit area in a first plane PL1crossing the first direction (referring toFIG.1A). For example, the first plane PL1passes through the fourth semiconductor region14along the X-Y plane. The fourth semiconductor region14has a first volume ratio. The first volume ratio is the ratio of the volume of the fourth semiconductor region14to the volume of the semiconductor member10.

For example, the seventh semiconductor region17has the second impurity concentration of the second conductivity type. The seventh semiconductor region17has the second carrier concentration of the second conductivity type. The seventh semiconductor region17has a second thickness z2along the first direction (referring toFIG.2A). The seventh semiconductor region17has a second area ratio. The second area ratio is the ratio of the surface area of the seventh semiconductor region17per unit area in a second plane PL2crossing the first direction (referring toFIG.2A). For example, the second plane PL2passes through the seventh semiconductor region17along the X-Y plane. The seventh semiconductor region17has a second volume ratio. The second volume ratio is the ratio of the volume of the seventh semiconductor region17to the volume of the semiconductor member10.

For example, the second impurity concentration is greater than the first impurity concentration. For example, the second carrier concentration is greater than the first carrier concentration. For example, the second thickness z2is greater than the first thickness z1. For example, the second area ratio is greater than the first area ratio. For example, the second volume ratio is greater than the first volume ratio.

As described below, a turn-off switching loss Eoff can be reduced thereby. For example, the collector-emitter saturation voltage VCE (sat) can be reduced. By setting the second-conductivity-type carrier concentration in the fourth semiconductor region14to be low, for example, a reverse recovery operation switching loss Err can be reduced.

An example of characteristics of the semiconductor device will now be described. A relationship between characteristics in the off-state of the IGBT operation and the carrier concentration difference between the fourth semiconductor region14and the seventh semiconductor region17will now be described.

FIG.3is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG.3is a ratio CR of the carrier concentrations. The ratio CR is the ratio of the second-conductivity-type carrier concentration (a second carrier concentration C2) in the seventh semiconductor region17to the second-conductivity-type carrier concentration (a first carrier concentration C1) in the fourth semiconductor region14. The ratio CR is C2/C1. The vertical axis ofFIG.3is a reduction amount Eoff_1of the turn-off switching loss Eoff. The reduction amount Eoff_1of the turn-off switching loss Eoff is the reduction amount referenced to the turn-off switching loss Eoff for a configuration that does not include the fourth electrode54. A large reduction amount Eoff_1of the turn-off switching loss Eoff corresponds to a small turn-off switching loss Eoff. InFIG.3, the potential of the fourth electrode54is set to the on-state at the time at which the potential of the third electrode53is set to the off-state.

As shown inFIG.3, the reduction amount Eoff_1of the turn-off switching loss Eoff increases as the ratio CR increases. FromFIG.3, it can be seen that the turn-off switching loss Eoff can be reduced by increasing the ratio CR. It is considered that more carriers are stored in the on-state when the ratio CR is high. Accordingly, when the ratio CR is high, the total carrier amount that is ejectable by switching the fourth electrode54on is high. It is considered that the turn-off switching loss Eoff is reduced thereby.

FIG.4is a graph illustrating a characteristic of the semiconductor device.

InFIG.4, the potential of the fourth electrode54is set to the on-state before the time at which the potential of the third electrode53is set to the off-state. In the example ofFIG.4, the difference between the time at which the potential of the fourth electrode54is set to the on-state and the time at which the potential of the third electrode53is set to the off-state is 60 ρS. The horizontal axis ofFIG.4is the ratio CR. The vertical axis ofFIG.4is the reduction amount Eoff_1of the turn-off switching loss Eoff. In the example shown inFIG.4as well, the reduction amount Eoff_1of the turn-off switching loss Eoff increases as the ratio CR increases.

FIG.5is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG.5is the ratio CR. The vertical axis ofFIG.5is a reduction amount VCE (sat)_1of the collector-emitter saturation voltage VCE (sat). The reduction amount VCE (sat)_1of the collector-emitter saturation voltage VCE (sat) is the reduction amount referenced to the collector-emitter saturation voltage VCE (sat) for a configuration that does not include the fourth electrode54. It can be seen fromFIG.5that the reduction amount VCE (sat)_1of the collector-emitter saturation voltage VCE (sat) increases as the ratio CR increases. The collector-emitter saturation voltage VCE (sat) can be reduced by increasing the ratio CR.

FromFIGS.3to5, it is favorable for the ratio CR of the second-conductivity-type carrier concentration (the second carrier concentration C2) in the seventh semiconductor region17to the second-conductivity-type carrier concentration (the first carrier concentration C1) in the fourth semiconductor region14to be not less than 20. For example, the turn-off switching loss Eoff can be reduced thereby. For example, the collector-emitter saturation voltage VCE (sat) can be reduced.

According to the embodiment, for example, the amount of the second-conductivity-type carriers in the seventh semiconductor region17is greater than the amount of the second-conductivity-type carriers in the fourth semiconductor region14. For example, in the IGBT operation, the injection efficiency of holes at the second electrode52is high. For example, the injection efficiency of the holes at the second electrode52in the IGBT operation is greater than the hole injection efficiency at the first electrode51in the diode operation. The reverse recovery operation switching loss Err in the diode operation is easily reduced. On the other hand, for the off-state of the IGBT operation, the turn-off switching loss Eoff can be reduced by the second electrode52at which the carrier concentration is high.

According to the embodiment, for example, the turn-off switching loss Eoff can be effectively reduced. For example, the collector-emitter saturation voltage VCE (sat) can be effectively reduced.

Thus, for example, the loss can be reduced by setting the second-conductivity-type carrier concentration (the second carrier concentration) in the seventh semiconductor region17to be greater than the second-conductivity-type carrier concentration (the first carrier concentration) in the fourth semiconductor region14. According to the embodiment, a semiconductor device can be provided in which the loss can be reduced.

According to the embodiment, it is favorable for the second carrier concentration to be not less than 20 times the first carrier concentration. The loss can be effectively reduced thereby. For example, the second carrier concentration may be not more than 2000 times the first carrier concentration.

According to the embodiment, the fourth semiconductor region14and the seventh semiconductor region17may be formed by introducing a second-conductivity-type impurity into a first-conductivity-type region. In such a case, the carrier concentration difference in these regions may be formed by the concentration difference of the second-conductivity-type impurity.

According to the embodiment, for example, it is favorable for the second impurity concentration to be not less than 20 times the first impurity concentration. The loss can be effectively reduced thereby. For example, the second impurity concentration may be not more than 2000 times the first impurity concentration.

The example ofFIG.3shows the relationship between the electrical characteristic and the impurity concentration difference between the fourth semiconductor region14and the seventh semiconductor region17. The characteristic illustrated inFIG.3is obtained by the volume difference between the fourth semiconductor region14and the seventh semiconductor region17.

For example, the loss can be reduced by setting the second thickness z2of the seventh semiconductor region17to be greater than the first thickness z1of the fourth semiconductor region14. The loss can be reduced thereby.

For example, the loss can be reduced by setting the ratio (the second area ratio) of the surface area of the seventh semiconductor region17per unit area in the second plane PL2to be greater than the ratio (the first area ratio) of the surface area of the fourth semiconductor region14per unit area in the first plane PL1. According to the embodiment, for example, the second area ratio is not less than 20 times the first area ratio. The loss can be effectively reduced thereby. For example, the second area ratio may be not more than 2000 times the first area ratio.

For example, the loss can be reduced by setting the ratio (the second volume ratio) of the volume of the seventh semiconductor region17to the volume of the semiconductor member10to be greater than the ratio (the first volume ratio) of the volume of the fourth semiconductor region14to the volume of the semiconductor member10. According to the embodiment, for example, the second volume ratio is not less than 20 times the first volume ratio. The loss can be effectively reduced thereby.

For example, the volume ratio may be modified by modifying the lengths (a first width w1and a second width w2referring toFIG.2C) in the X-axis direction of the fourth and seventh semiconductor regions14and17. The volume ratio may be modified by modifying the lengths (a first length L1and a second length L2referring toFIG.2C) in the Y-axis direction of the fourth and seventh semiconductor regions14and17.

Several examples of the semiconductor device according to the embodiment will now be described. A description is omitted for portions to which configurations similar to those of the semiconductor device110are applicable.

FIGS.6A to6Care schematic cross-sectional views illustrating a semiconductor device according to the first embodiment.

FIG.6Bis a line A1-A2cross-sectional view ofFIG.6A.FIG.6Cis a line A3-A4cross-sectional view ofFIG.6A.

In the semiconductor device110aas shown inFIG.6A, the second thickness z2of the seventh semiconductor region17is greater than the thickness of the first thickness z1of the fourth semiconductor region14. According to the embodiment, for example, the second thickness z2is not less than 20 times the first thickness z1. The loss can be effectively reduced thereby. The second thickness z2may be not more than 2000 times the first thickness z1.

FIGS.7A to7Care schematic cross-sectional views illustrating a semiconductor device according to the first embodiment.

FIG.7Bis a line A1-A2cross-sectional view ofFIG.7A.FIG.7Cis a line A3-A4cross-sectional view ofFIG.7A.

In the semiconductor device110bas shown inFIGS.7B and7C, the second width w2along the second direction (the X-axis direction) of the seventh semiconductor region17is greater than the first width w1along the second direction of the fourth semiconductor region14. According to the embodiment, for example, the second width w2is not less than 20 times and not more than 2000 times the first width w1. The loss can be effectively reduced thereby.

FIGS.8A to8Care schematic cross-sectional views illustrating a semiconductor device according to the first embodiment.

FIG.8Bis a line A1-A2cross-sectional view ofFIG.8A.FIG.8Cis a line A3-A4cross-sectional view ofFIG.8A.

As shown inFIGS.8B and8C, in the semiconductor device110cas well, the second width w2of the seventh semiconductor region17is greater than the first width w1. In the semiconductor device110c, a portion of the second semiconductor region12is between the third semiconductor region13and the fourth semiconductor region14. In the semiconductor device110cas well, the loss can be reduced.

FIGS.9A to9Care schematic cross-sectional views illustrating a semiconductor device according to the first embodiment.

FIG.9Bis a line A1-A2cross-sectional view ofFIG.9A.FIG.9Cis a line A3-A4cross-sectional view ofFIG.9A.

As shown inFIGS.9B and9C, the semiconductor device110dincludes multiple fourth semiconductor regions14and multiple seventh semiconductor regions17. The multiple fourth semiconductor regions14and the multiple seventh semiconductor regions17each have island shapes. A portion of the second semiconductor region12is between one of the multiple fourth semiconductor regions14and another one of the multiple fourth semiconductor regions14. A portion of the fifth semiconductor region15is between one of the multiple seventh semiconductor regions17and another one of the multiple seventh semiconductor regions17.

In the semiconductor device110d, the length in the Y-axis direction is different between the fourth semiconductor region14and the seventh semiconductor region17. For example, a direction that crosses a plane including the first direction (the Z-axis direction) and the second direction (e.g., the X-axis direction) is taken as a fourth direction. The fourth direction is, for example, the Y-axis direction. The second length L2of the seventh semiconductor region17along the fourth direction is greater than the first length L1of the fourth semiconductor region14along the fourth direction. In the semiconductor device110das well, the loss can be reduced. According to the embodiment, for example, the second length L2is 20 times the first length L1. The loss can be effectively reduced thereby. For example, the second length L2may be not more than 2000 times the first length L1.

FIGS.10A to10Care schematic cross-sectional views illustrating a semiconductor device according to the first embodiment.

FIG.10Bis a line A1-A2cross-sectional view ofFIG.10A.FIG.10Cis a line A3-A4cross-sectional view ofFIG.10A.

As shown inFIGS.10B and10C, the semiconductor device110ealso includes the multiple fourth semiconductor regions14and the multiple seventh semiconductor regions17. In the semiconductor device110e, the length in the Y-axis direction of the second semiconductor region12between the multiple fourth semiconductor regions14is greater than the length in the Y-axis direction of the fifth semiconductor region15between the multiple seventh semiconductor regions17. The ratio (the second area ratio) of the surface area of the seventh semiconductor region17per unit area in the X-Y plane is greater than the ratio (the first area ratio) of the surface area of the fourth semiconductor region14per unit area in the X-Y plane. In the semiconductor device110eas well, the loss can be reduced.

According to the embodiment, the area ratio can be modified by modifying at least one of the width or the length for the fourth and seventh semiconductor regions14and17. The volume ratio can be modified by modifying the area ratio. The volume ratio can be modified by modifying the thicknesses of the fourth and seventh semiconductor regions14and17.

According to the embodiment, at least one of the impurity concentration, the carrier concentration, or the volume ratio may be modified. For example, the seventh semiconductor region17may have at least one of the second impurity concentration of the second conductivity type that is greater than the first impurity concentration, the second carrier concentration of the second conductivity type that is greater than the first carrier concentration, or the second volume ratio that is greater than the first volume ratio.

FIG.11is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

In the semiconductor device110fas shown inFIG.11, at least a portion of the third semiconductor region13is between a portion of the third electrode53and a portion of the second semiconductor region12in the second direction (e.g., the X-axis direction). At least a portion of the sixth semiconductor region16is between a portion of the fourth electrode54and a portion of the fifth semiconductor region15in the third direction (e.g., the X-axis direction). The third semiconductor region13is between the second semiconductor region12and the fourth semiconductor region14in the Z-axis direction. The sixth semiconductor region16is between the fifth semiconductor region15and the seventh semiconductor region17in the Z-axis direction.

Thus, at least a portion of the third semiconductor region13is in at least one of a first position between the fourth semiconductor region14and a portion of the third electrode53in the second direction (the X-axis direction) or a second position between a portion of the third electrode53and a portion of the second semiconductor region12in the second direction. At least a portion of the sixth semiconductor region16is in at least one of a third position between the seventh semiconductor region17and a portion of the fourth electrode54in the third direction (the X-axis direction) or a fourth position between a portion of the fourth electrode54and a portion of the fifth semiconductor region15in the third direction.

FIG.12is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

In the semiconductor device110gas shown inFIG.12, the multiple third electrodes53are arranged in the X-axis direction. The multiple fourth electrodes54are arranged in the X-axis direction. The position in the X-axis direction of one of the multiple third electrodes53is between the position in the X-axis direction of one of the multiple fourth electrodes54and the position in the X-axis direction of another one of the multiple fourth electrodes54. The position in the X-axis direction of one of the multiple fourth electrodes54is between the position in the X-axis direction of one of the multiple third electrodes53and the position in the X-axis direction of another one of the multiple third electrodes53.

FIG.13is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG.13, the semiconductor device110hfurther includes a first conductive member61, a second conductive member62, a third insulating member43, and a fourth insulating member44in addition to the first electrode51, the second electrode52, the third electrode53, the fourth electrode54, the first insulating member41, and the second insulating member42described above.

The position in the first direction (the Z-axis direction) of the portion11pof the first semiconductor region11is between the position in the first direction of the second conductive member62and the position in the first direction of the first conductive member61. At least a portion of the third insulating member43is between the first conductive member61and the semiconductor member10. At least a portion of the fourth insulating member44is between the second conductive member62and the semiconductor member10. The first conductive member61is electrically connected with the first electrode51. As described below, the first conductive member61may be electrically connectable with the first electrode51. The second conductive member62is electrically connected with the second electrode52. As described below, the second conductive member62may be electrically connectable with the second electrode52. For example, the first conductive member61and the second conductive member62may function as field plates. For example, the concentration of the electric field is suppressed. For example, a high breakdown voltage is obtained.

FIG.14is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG.14, the semiconductor device110ialso includes the first conductive member61, the second conductive member62, the third insulating member43, and the fourth insulating member44. In the semiconductor device110i, the first conductive member61is electrically connected with the first electrode51via a connection member61C, a connection member51C, and a connection member51L. A terminal61T that is electrically connected with the first conductive member61may be provided. A terminal51T that is electrically connected with the first electrode51may be provided. The terminal51T and the terminal61T may be electrically connected by the connection member51L. The connection member51L may not be included in the semiconductor device110i. Thus, the first conductive member61may be electrically connectable with the first electrode51.

The second conductive member62is electrically connected with the second electrode52via a connection member62C, a connection member52C, and a connection member52L. A terminal62T that is electrically connected with the second conductive member62may be provided. A terminal52T that is electrically connected with the second electrode52may be provided. The terminal52T and the terminal62T may be electrically connected by the connection member52L. The connection member52L may not be included in the semiconductor device110i. Thus, the second conductive member62may be electrically connectable with the second electrode52. For example, the concentration of the electric field is suppressed. For example, a high breakdown voltage is obtained.

In the semiconductor devices110ato110i, for example, the seventh semiconductor region17may have at least one of the second impurity concentration of the second conductivity type that is greater than the first impurity concentration, the second carrier concentration of the second conductivity type that is greater than the first carrier concentration, or the second volume ratio that is greater than the first volume ratio. The loss can be reduced.

Second Embodiment

A second embodiment relates to a semiconductor module.

FIG.15is a schematic view illustrating a semiconductor module according to the second embodiment.

As shown inFIG.15, the semiconductor module210according to the second embodiment includes the semiconductor device according to the first embodiment (in the example, the semiconductor device110) and a controller70. The controller70is electrically connected with the first to fourth electrodes51to54. The controller70can control the potential of the third electrode53and the potential of the fourth electrode54. The potential of the third electrode53and the potential of the fourth electrode54are, for example, potentials that are referenced to the potential of the first electrode51.

FIGS.16A and16Bare schematic views illustrating operations of the semiconductor module according to the second embodiment.

InFIGS.16A and16B, the horizontal axis is a time tm. The vertical axis ofFIG.16Ais a potential E3of the third electrode53. The vertical axis ofFIG.16Bis a potential E4of the fourth electrode54. These potentials are controlled by the controller70.

As shown inFIG.16A, the controller70is configured to perform the first operation of switching the third electrode53from a first potential V1to a second potential V2that is less than the first potential V1. The first operation corresponds to the “off-operation” of causing the IGBT operation to transition from the “on-state” to the “off-state”. In the first operation, the controller70switches the third electrode53from the first potential V1to the second potential V2at a first time t1. The first potential V1is, for example, +15 V. The second potential V2is, for example, −15 V. In such a first operation, the controller70switches the fourth electrode54from a third potential V3to a fourth potential V4that is greater than the third potential V3at a second time t2that is before the first time t1. The third potential V3is, for example, 0 V. The fourth potential V4is, for example, +15 V. The turn-off switching loss Eoff can be reduced by such an operation.

As shown inFIG.16B, the time between the first time t1and the second time t2is taken as a time difference td. An example of the change of the turn-off switching loss Eoff when changing the time difference td will now be described.

FIG.17is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG.17is the time difference td between the time of the change of the potential of the third electrode53and the time of the change of the potential of the fourth electrode54in the off-state of the IGBT operation. When the time difference td is 0, the potential of the fourth electrode54becomes the on-state potential when the potential of the third electrode53becomes the off-potential. When the time difference td is positive, the potential of the fourth electrode54becomes the on-state potential after the potential of the third electrode53becomes the off-potential. When the time difference td is negative, the potential of the fourth electrode54becomes the on-state potential before the potential of the third electrode53becomes the off-potential. As shown inFIG.17, the turn-off switching loss Eoff decreases when the time difference td is negative. It is considered that this effect is caused by the carriers that were stored in the on-state being ejected directly before turn-off. The turn-off switching loss Eoff can be reduced by setting the time difference td to be negative and by setting the absolute value of the time difference td to be not less than 1 μs. The turn-off switching loss Eoff can be reduced by setting the time difference td to be negative and by setting the absolute value of the time difference td to be not less than 5 μs. The turn-off switching loss Eoff can be effectively reduced by setting the time difference td to be negative and by setting the absolute value of the time difference td to be not less than 10 μs.

According to the embodiment, it is favorable for the time difference td to be negative, and for the absolute value of the time difference td to be not less than 10 μs. The turn-off switching loss Eoff can be reduced thereby. It is more favorable for the time difference td to be negative and for the absolute value of the time difference td to be not less than 20 ρS. The turn-off switching loss Eoff can be effectively reduced thereby. It is favorable for the time difference td to be negative and for the absolute value of the time difference td to be not more than 200 μs. If the time difference td is excessively long, for example, the conduction loss in the IGBT operation increases. By setting the time difference td to be negative and by setting the absolute value of the time difference td to be not more than 200 the conduction loss in the IGBT operation is easily suppressed.

For example, the fourth electrode54is caused to transition to the on-state potential before the time of switching the IGBT operation off by setting the third electrode53to the off-potential. In such a case, the effect of the reduction of the turn-off switching loss Eoff is increased because the amount of the second-conductivity-type carriers in the seventh semiconductor region17is greater than the amount of the second-conductivity-type carriers in the fourth semiconductor region14. It is considered that this is caused by more carriers being ejected directly before turn-off.

In embodiments described above, it is favorable for the first-conductivity-type carrier concentration in the first semiconductor region11to be not less than 1×1012/cm3and not more than 1×1014/cm3. It is favorable for the second-conductivity-type carrier concentration in the second semiconductor region12to be not less than 1×1016/cm3and not more than 1×1018/cm3. It is favorable for the first-conductivity-type carrier concentration in the third semiconductor region13to be not less than 1×1018/cm3and not more than 5×1020/cm3. It is favorable for the second-conductivity-type carrier concentration in the fourth semiconductor region14to be not less than 1×1018/cm3and not more than 1×1020/cm3. It is favorable for the second-conductivity-type carrier concentration in the fifth semiconductor region15to be not less than 1×1016/cm3and not more than 1×1018/cm3. It is favorable for the first-conductivity-type carrier concentration in the sixth semiconductor region16to be not less than 1×1018/cm3and not more than 5×1020/cm3. It is favorable for the second-conductivity-type carrier concentration in the seventh semiconductor region17to be not less than 1×1018/cm3and not more than 1×1020/cm3. It is favorable for the first-conductivity-type carrier concentration in the eighth semiconductor region18to be not less than 1×1015/cm3and not more than 1×1017/cm3. It is favorable for the first-conductivity-type carrier concentration in the ninth semiconductor region19to be not less than 1×1015/cm3and not more than 1×1017/cm3.

In embodiments described above, it is favorable for the first-conductivity-type impurity concentration in the first semiconductor region11to be not less than 1×1012/cm3and not more than 1×1014/cm3. It is favorable for the second-conductivity-type impurity concentration in the second semiconductor region12to be not less than 1×1016/cm3and not more than 1×1018/cm3. It is favorable for the first-conductivity-type impurity concentration in the third semiconductor region13to be not less than 1×1018/cm3and not more than 5×1020/cm3. It is favorable for the second-conductivity-type impurity concentration in the fourth semiconductor region14to be not less than 1×1018/cm3and not more than 1×1020/cm3. It is favorable for the second-conductivity-type impurity concentration in the fifth semiconductor region15to be not less than 1×1016/cm3and not more than 1×1018/cm3. It is favorable for the first-conductivity-type impurity concentration in the sixth semiconductor region16to be not less than 1×1018/cm3and not more than 5×1020/cm3. It is favorable for the second-conductivity-type impurity concentration in the seventh semiconductor region17to be not less than 1×1018/cm3and not more than 1×1020/cm3. It is favorable for the first-conductivity-type impurity concentration in the eighth semiconductor region18to be not less than 1×1015/cm3and not more than 1×1017/cm3. It is favorable for the first-conductivity-type impurity concentration in the ninth semiconductor region19to be not less than 1×1015/cm3and not more than 1×1017/cm3.

The semiconductor member includes, for example, silicon. The semiconductor member may include, for example, a compound semiconductor, etc. The first electrode51includes, for example, aluminum, etc. The second electrode52includes, for example, aluminum, etc. At least one of the third electrode53, the fourth electrode54, the first conductive member61, or the second conductive member62includes, for example, conductive silicon. The first to fourth insulating members41to44include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

In embodiments, information that relates to the configurations of the semiconductor regions, etc., is obtained by, for example, electron microscopy, etc. Information that relates to the impurity concentrations of the semiconductor regions is obtained by, for example, EDX (Energy Dispersive X-ray Spectroscopy), SIMS (Secondary Ion Mass Spectrometry), etc. Information that relates to the carrier concentrations of the semiconductor regions is obtained by, for example, SCM (Scanning Capacitance Microscopy), etc.

According to embodiments, a semiconductor device and a semiconductor module can be provided in which the loss can be reduced.

Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.