Adjustable ground shielding circuitry

An integrated circuit (IC) die may include a substrate layer and an inductor with an associated capacitance formed on one of multiple metal layers above the substrate layer. Power shielding strips may be formed between the inductor and the substrate layer. Portions of the power shielding strips may be selectively activated to adjust the capacitance of the inductor. As an example, switches may be coupled to the power shielding strips to selectively couple a portion of the power shielding strips to a ground voltage to increase the capacitance of the inductor. As another example, a fuse element may be used to selectively activate desired portions of the power shielding strips.

BACKGROUND

Integrated circuits (ICs) may include transceiver circuitry that includes high-speed receivers and transmitters that may be used in various types of applications. Generally, an inductance-capacitance voltage-controlled oscillator (LC-VCO) circuit is used to control the tuning frequency of the transceiver circuitry on an IC. Accordingly, the tuning range of the transceiver circuitry is determined by the tuning range of the LC-VCO circuit that controls the transceiver circuitry.

As is generally known, an LC-VCO circuit may include an inductor (L) (or inductors) and variable capacitors or varactors (C). Even though an LC-VCO circuit with a wide frequency tuning range is generally desired, the tuning range of an LC-VCO circuit is typically limited by the minimum and maximum capacitance values of the varactors in the LC-VCO circuit. A capacitor array with metal-oxide-semiconductor field-effect transistor (MOSFET) switches is usually used to enlarge the tuning range of an LC-VCO circuit. However, the capacitor array with MOSFET switches typically occupies additional die area and hence increases the overall die area required for the LC-VCO circuit.

For high-speed circuitry, inductors with a high quality factor (Q) are preferred. Achieving high Q is generally challenging due to inductor loss that results from current flowing from the inductor to the substrate of the IC. To improve Q, a patterned ground shield is conventionally used to isolate the inductor from the substrate. However, the patterned ground shield may introduce a fixed parasitic capacitance to the LC-VCO circuit. Parasitic capacitance is undesirable because it reduces the tuning range and limits the resonance frequency of the LC-VCO circuit.

It is within this context that the embodiments described herein arise.

SUMMARY

An IC with an inductor and a patterned ground shield is provided. The patterned ground shield includes ground shielding strips that may be selectively activated or coupled to a ground voltage (or other power supply voltage) to increase the capacitance of the inductor and adjust the resonant frequency of an LC-VCO circuit in the IC. Embodiments of the present invention include different configurations for such types of patterned ground shields.

It is appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.

An IC die may include a substrate layer and an inductor with an associated capacitance value. The inductor may be formed in a metal layer above the substrate layer. Multiple ground shielding strips may be formed between the inductor and the substrate layer. The ground shielding strips may collectively form a patterned ground shield for the inductor. Selected ground shielding strips may accordingly be activated to increase the capacitance of the inductor. As an example, switching circuitry may be coupled to the ground shielding strips to selectively activate the ground shielding strips.

A patterned ground shielding strip may also be formed in the same metal layer as the inductor. As an example, the patterned ground shielding strip may be formed laterally adjacent to the inductor. The patterned ground shielding strip may be used to increase the capacitance of the inductor. In some scenarios, additional ground shielding strips formed in other metal layers (e.g., metal layers between the inductor and the substrate layer) in the IC die and the patterned ground shielding strip formed adjacent to the inductor may collectively form a patterned ground shield for the inductor.

Alternatively, an IC may include an inductor with first and second edges where current flows in one direction along the first edge of the inductor and flows in another direction along the second edge of the inductor. First and second groups of power shielding strips may be formed directly under the respective first and second edges of the inductor. A switching circuit may be coupled between the first and second groups of power shielding strips to electrically connect the first and second groups of power shielding strips. The capacitance of the inductor may be increased when the first and second groups of power shielding strips are electrically connected.

DETAILED DESCRIPTION

The embodiments provided herein include integrated circuits (ICs) with an inductor and a patterned ground shield. The patterned ground shield includes ground shielding strips that may be selectively activated or coupled to a ground voltage to adjust the capacitance of the inductor. Embodiments of the present invention include different configurations for such a patterned ground shield.

It will be obvious, however, to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

An IC device, such as a field-programmable gate array (FPGA) device or an application specific integrated circuit (ASIC) device, generally includes a core region and a peripheral region with input-output circuitry.FIG. 1, meant to be illustrative and not limiting, shows a block diagram of IC100that can implement embodiments of the present invention. An IC device such as IC100may include core logic region115at its center region and input-output elements110arranged at its peripheral region.

Core logic region115may be populated with logic cells that include “logic elements” (LEs)117, among other circuits. LEs117may include look-up table-based logic regions and may be grouped into “Logic Array Blocks” (LABs). LEs117and groups of LEs or LABs can be configured to perform logical functions desired by the user. Configuration data loaded into configuration memory may be used to produce control signals that configure LEs117and groups of LEs and LABs to perform the desired logical functions.

As is generally known, IC devices may use a clock signal to synchronize different circuit elements in the device. Phase-locked loops (PLLs)125for clock generation and timing, may be located outside core logic region115(e.g., at corners of IC100and adjacent to input-output elements110as shown inFIG. 1). It should be noted that IC100may include a clock network (not shown) that is used to transmit clock signals from clock circuits (e.g., PLLs125) to core logic region115and various parts of IC100, including input-output elements110.

Signals received at input-output elements110from external circuitry or components coupled to IC100may be routed from input-output elements110to core logic region115or other logic blocks (not shown) on IC100. Core logic region115, or more specifically, logic blocks within core logic region115, on IC100may perform functions based on the signals received. Signals are accordingly sent from core logic region115to any external circuitry or components that may be connected to IC100via input-output elements110.

In the embodiment ofFIG. 1, input-output elements110may include input-output buffers and various circuits that connect IC100to other external components via a variety of input-output interfaces. A single device such as IC100may support a variety of different interfaces and each individual input-output block110may support a different input-output standard with a different interface or protocol (e.g., high-speed serial interface protocol).

As an example, input-output blocks110may include transceiver circuitry. It should be noted that high-speed receivers and transmitters are used in applications that require a wide frequency tuning range. Such transceiver circuitry, therefore, may include an inductance-capacitance voltage-controlled oscillator (LC-VCO) circuit that is used to control the tuning frequency of the transceiver circuitry. To improve the quality factor (Q) of the inductor in the LC-VCO circuit, a patterned ground shield structure may be formed in IC100.

FIG. 2shows an illustrative cross-sectional side view200of an IC die in accordance with embodiments of the present invention. As shown inFIG. 2, the IC die may include multiple metal layers M1-M9(sometimes referred to as metal routing layers) formed over substrate layer205(e.g., a semiconductor substrate such as a p-type silicon substrate). InFIG. 2, every two metal layers M1-M9are separated by a dielectric layer D1-D8. It should be noted that adjacent metal layers may be connected to each other through vias formed in the dielectric layers D1-D8(not shown). Dielectric layers D1-D8are therefore sometimes referred to as via layers. The alternating arrangement of metal routing layers and via layers is sometimes referred to collectively as a dielectric stack or as interconnect routing layers. It should also be noted that even though metal layers M1-M9are shown, an IC die may include more (or fewer) metal layers with dielectric via layers formed in between two metal layers.

An inductor such as that mentioned above may be formed in any of the metal layers M1-M9. It should be noted that interconnects (not shown inFIG. 2) may be formed in any or all of the metal layers M1-M9to couple the inductor to other circuitry on the IC die. As an example, the inductor (or the coil of the inductor) may be formed in an upper metal layer or a metal layer farthest from the substrate layer (e.g., metal layer M9inFIG. 2).

A patterned ground shield with multiple ground shielding strips may be formed in any of the metal layers. In one embodiment, a portion of the ground shielding strips may be formed in the same metal layer as the inductor (e.g., metal layer M9, if the inductor is formed in that layer). In some embodiments, switching circuitry (not shown inFIG. 2) may be coupled to the ground shielding strips. The switching circuitry may thus activate selected portions of the ground shielding strips to adjust the capacitance of the inductor formed in one of the metal layers.

In some embodiments, the ground shielding strips of the patterned ground shield may be formed in different metal layers (e.g., any of metal layers M1-M8). The ground shielding strips may be selectively activated or coupled to a ground voltage as required to adjust the capacitance of the inductor. As an example, portions of the ground shielding strips in the patterned ground shield may be activated to adjust the capacitance of the inductor formed above (or, in some instances, below) the patterned ground shield structure. As an example, activating portions of the ground shielding strips in the patterned ground shield may increase the capacitance of the inductor. In some instances, the tuning range of an LC-VCO circuit in the IC may be adjusted by selectively activating portions of the ground shielding strip.

FIG. 3Ais an illustrative topographical view300A of inductor structure310formed in an IC in accordance with embodiments of the present invention. As shown inFIG. 3A, groups of ground shielding strips320A,320B, and320C may be formed beneath inductor structure310. Inductor structure310may have an associated capacitance and in one embodiment, its capacitance may be adjusted by selectively activating portions or groups of ground shielding strips320A,320B, and320C.

As shown in the embodiment ofFIG. 3A, switching circuitry may be used to selectively activate portions of the ground shielding strips. As an example, switching circuitry325A is coupled to a group of ground shielding strips320A, switching circuitry325B is coupled to ground shielding strips320B, and switching circuitry325C is coupled to ground shielding strips320C. The groups of ground shielding strips shown inFIG. 3Amay collectively form a patterned ground shield for inductor structure310.

The ground shielding strips are formed such that the individual ground shielding strips in each of groups320A,320B, and320C runs orthogonally with respect to a corresponding side of inductor structure310. In one embodiment, the groups of ground shielding strips320A,320B, and320C may include ground shielding strips formed in different metal layers beneath inductor structure310. As an example, inductor structure310may be formed in a metal layer farthest from the substrate layer, whereas the groups of ground shielding strips320A,320B, and320C may include ground shielding strips that are formed in any of the metal layers between inductor structure310and the substrate layer.

Accordingly, each switching circuitry (325A,325B, and325C) may include individual switches formed in different metal layers to control or activate the ground shielding strips formed in those metal layers (details of which are shown in the cross-section view along the line A-A′, as described below with reference toFIG. 3B). To activate a selected portion of ground shielding strips in each group of ground shielding strips320A,320B and320C, the corresponding switches in the switching circuitry325A,325B, and325C may be closed.

When switches within switching circuitries325A,325B, and325C are closed, the respective groups of ground shielding strips320A,320B, and320C may be coupled to a ground voltage and may accordingly be activated. In one embodiment, fuses may be used as switches in switching circuitries325A,325B, and325C. In another embodiment, the switches may include transistors.

FIG. 3Bshows an illustrative cross-sectional side view300B along line A-A′ of the structure shown inFIG. 3Ain accordance with embodiments of the present invention. Four metal layers, MX, MX+1, MX+2, and MX+3 are shown on top of substrate305in the embodiment ofFIG. 3B. Ground shielding strips320A-1,320A-2, and320A-3are formed in metal layers MX, MX+1, and MX+2, respectively, and inductor310(or part of inductor310) is formed in metal layer MX+3.

A respective switch circuit may be coupled to each ground shielding strip to selectively activate the respective ground shielding strips. As shown inFIG. 3B, switch circuit325A-1is coupled to ground shielding strip320A-1; switch circuit325A-2is coupled to ground shielding strip320A-2; and switch circuit325A-3is coupled to ground shielding strip320A-3. In one scenario, as shown inFIG. 3B, transistors may be used as switches. It should be noted that even though N-type metal-oxide-semiconductor field-effect (NMOS) transistors are shown inFIG. 3, other transistors such as P-type metal-oxide-semiconductor field-effect (PMOS) transistors may be used in this context.

A source-drain terminal of each of the NMOS transistors325A-1,325A-2, and325A-3is coupled to a ground voltage whereas another source-drain terminal is coupled to a corresponding ground shielding strip. Different logic values may be supplied to the gate terminals of the respective NMOS transistors325A-1,325A-2, and325A-3. For example, when a logic high value is supplied to the gate terminal of any of the transistors325A-1,325A-2, and325A-3, that particular transistor will activate its corresponding ground shielding strip by connecting that ground shielding strip to a ground voltage. It should be noted that even though a ground voltage is described herein, the transistors or switches may be coupled to a positive power supply voltage terminal, an intermediate voltage terminal, a negative power supply voltage terminal, etc.

Two ground shielding strips (e.g., metal strips) on two adjacent metal layers (or conductive layers) may form a capacitor (shown in dotted lines), or have a capacitance value. In the embodiment ofFIG. 3B, ground shielding strip320A-1in metal layer MX and substrate layer305beneath metal layer MX may form a capacitor. Accordingly, inductor310formed in metal layer MX+3 and ground shielding strip320A-3in metal layer MX+2 may collectively form another capacitor.

In some instances, additional ground shielding strips, if desired, may be formed in the same metal layer as the inductor. As an example, additional ground shielding strips320A-4and320-5may be formed adjacent to inductor310. InFIG. 3B, the additional ground shielding strips320A-4and320A-5are shown in dotted lines as both ground shielding strips320A-4and320A-5are not shown in the topographical view inFIG. 3A.

Accordingly, the additional ground shielding strips320A-4and320A-5may be coupled to ground shielding strip320A-3in metal layer MX+2. As shown inFIG. 3B, vias315may be used to connect additional ground shielding strips320A-4and320A-5to ground shielding strip320A-3. It should be noted that vias315are represented with dotted lines to highlight that the additional ground shielding strips320A-4and320A-5may be optional in this context. In some instances, having additional ground shielding strips320A-4and320A-5may further increase the capacitance value of inductor structure310.

FIG. 3Cis an illustrative circuit representation of the cross-sectional side view structure300B ofFIG. 3Bin accordance with embodiments of the present invention. Circuit300C shows inductor310represented as two separate inductive components, each with an inductance, L/2. Four capacitors350A-0,350A-1,350A-2, and350A-3are coupled to inductor310. It should be noted that the respective capacitors350A-0,350A-1,350A-2, and350A-3are formed by ground shielding strip320A-1with substrate layer305; adjacent ground shielding strips320A-1and320A-2, and320A-2and320A-3; and inductor310and ground shielding strip320A-3(as shown inFIG. 3B).

Each of the capacitors350A-1-350A-3may be controlled by respective switching circuits355A-1-350A-3. It should be noted that switching circuits355A-1,355A-2, and355A-3may represent NMOS transistors325A-1,325A-2, and325A-3, respectively. As shown inFIG. 3C, one side of capacitor350A-0is coupled capacitor350A-1whereas another side of capacitor is coupled to a ground voltage. Accordingly, when none of the switching circuits355A-1-355A-3is closed, capacitors350A-1-350A-3are connected in series to capacitor350A-0, which is coupled to a ground voltage. If should be appreciated that connecting capacitors in series may lower the total capacitance of a circuit as the total capacitance in series may be obtained from the following equation: total capacitance,

As can be seen in the equation above, connecting more capacitors in series will lower the total capacitance in a circuit. It should be noted that the total capacitance of multiple capacitors that are coupled in parallel is represented by the following equation: total capacitance, C=C1+C2+ . . . Cn. Accordingly, connecting capacitors in parallel increases the total capacitance of a circuit. Therefore, when any of the switching circuits355A-1-355A-3is closed, thereby creating a parallel connection, the total capacitance of circuit300C may be increased. For example, when all of the switching circuits355A-1,355A-2, and355A-3are closed, capacitors350A-0,355A-1,355A-2, and355A-3may be connected in parallel. In one embodiment, any or all of switching circuits355A-1,355-2, and355A-3may be closed at any one time.

It should be noted that even though four metal layers MX, MX+1, MX+2, and MX+3 are shown in the embodiment ofFIG. 3B, more or fewer metal layers may be formed in an integrated circuit, and more (or fewer) ground shielding strips may be formed on those metal layers. Accordingly, more or fewer capacitors may be connected in circuit300C ofFIG. 3C. As an example, an additional metal layer may be formed above metal layer MX+3 ofFIG. 3Band an additional ground shielding strip may be formed in that metal layer.

FIG. 4shows an illustrative cross-sectional side view400of an inductor structure formed between two metal layers in accordance with embodiments of the present invention. It should be noted that cross-sectional side view400shares similarities with cross-sectional side view300B ofFIG. 3Band as such, for the sake of brevity, elements that have been described above (e.g., inductor structure310; substrate layer305; metal layers MX, MX+1, MX+2, MX+3, and MX+4; ground shielding strips320A-1,320A-2,320A-3,320A-4, and320A-5; switching circuits325A-1,325A-2, and325A-3; and vias315) are not described in detail again.

In the embodiment ofFIG. 4, an additional ground shielding strip420is formed in a metal layer MX+4 above inductor structure310. Accordingly, ground shielding strip420and inductor structure310may form a capacitor structure (shown in dotted lines). A switching circuit425may be coupled to ground shielding strip420. As with switching circuits320A-1-320A-3, switching circuit425may selectively activate ground shielding strip420to adjust the capacitance value provided to inductor structure310. In the embodiment ofFIG. 4, an NMOS transistor is used as switching circuit425.

It should be noted that vias315(in dotted lines) may be formed between ground shielding strip420and ground shielding strips320A-4and320A-5instead of between ground shielding strip320A-3and ground shielding strips320A-4and320A-5. In some instances, fewer or more switching circuits may be used to control the respective ground shielding strips320A-1,320A-2,320A-3,320A-4,320A-5, and420. Accordingly, different configurations (e.g., with different numbers of ground shielding strips or switching circuits) may be utilized in this context.

FIG. 5Ashows a topographical view500A of an inductor structure and ground shielding strips formed below the inductor structure in accordance with embodiments of the present invention. Groups of ground shielding strips520A and520B are formed beneath inductor structure510. Ground shielding strips520A and520B may not be coupled to a ground voltage. As such, the two groups of ground shielding strips520A and520B may form a floating shield beneath inductor structure510. Inductor structure510may have an associated capacitance that may be adjusted by selectively activating portions or groups of ground shielding strips520A and520B.

In the embodiment ofFIG. 5A, switching circuit525is coupled between the two groups of ground shielding strips520A and520B. Inductor structure510may be coupled to signals (e.g., currents or voltages) that are 180 degrees out of phase with each other (e.g., differential signals/currents, or currents flowing in opposite directions). For example, one end of inductor structure may be driven by a voltage level (+V) whereas another end of the inductor structure may be driven by a 180-degree phase-shifted version of that voltage level (−V). Such an arrangement may create a virtual ground (e.g., 0V) between ground shielding strips520A and520B beneath inductor structure510.

The ground shielding strips are formed such that one group of ground shielding strips520A extends perpendicularly along a first edge of inductor structure510and another group of ground shielding strips520B extends perpendicularly a second edge (that is parallel to the first edge) of inductor structure510. It should be noted that the groups of ground shielding strips520A and520B may include ground shielding strips formed in different metal layers (not shown inFIG. 5A) beneath inductor structure510.

Switching circuitry525may be coupled between the two groups of ground shielding strips520A and520B to connect selected ground shielding strips to the virtual ground formed between ground shielding strips520A and520B. As there may be ground shielding strips formed in different metal layers beneath (or even above) inductor structure510, switching circuitry525may accordingly include individual switches formed in the different metal layers to control or activate the ground shielding strips formed in those metal layers.

Details of ground shielding strips and switches formed in different metal layers are shown in the cross-section view along the line B-B′, as described below with reference toFIG. 3B. To activate a selected portion of ground shielding strips in each group of ground shielding strips520A and520B, the corresponding switches in switching circuitry525may be closed.

FIG. 5Bshows an illustrative cross-sectional side view500B along line B-B′ of the structure shown inFIG. 5Ain accordance with embodiments of the present invention. InFIG. 5B, Ground shielding strips520A-1/520B-1,520A-2/520B-2, and520A-3/520B-3are formed in metal layers MX, MX+1, and MX+2, respectively, and inductor structure510(or part of inductor structure510) is formed in metal layer MX+3.

A switch circuit may be coupled between two adjacent ground shielding strips in the same metal layer to selectively activate the respective ground shielding strips. As shown inFIG. 5B, switch circuit525-1is coupled between ground shielding strips520A-1and520B-1in metal layer MX, switch circuit525-2is coupled to between ground shielding strips520A-2and520B-2, and switch circuit525-3is coupled between ground shielding strips520A-3and520B-3. In one scenario, as shown inFIG. 5B, transistors may be used as switches. It should be noted that even though NMOS transistors are shown inFIG. 5B, other transistors such as PMOS transistors may be used in this context.

A source-drain terminal of each of the NMOS transistors525-1,525-2, and525-3is coupled to the respective ground shielding strips520A-1,520A-2, and520A-3, whereas another source-drain terminal is coupled to the respective ground shielding strips520B-1,520B-2, and520B-3. Different logic values may be supplied to the gate terminals of the respective NMOS transistors525-1,525-2, and525-3. For example, when a logic high value is supplied to the gate terminal of any of the transistors525-1,525-2, and525-3, that particular transistor will activate its corresponding ground shielding strips by connecting the two adjacent ground shielding strips together.

It should be noted that two ground shielding strips in two adjacent metal layers (or conductive layers) may form a capacitor (shown in dotted lines), or have a capacitance value. In the embodiment ofFIG. 5B, ground shielding strip520A-1(or ground shielding strip520B-1) in metal layer MX and ground shielding strip520A-2(or ground shielding strip520B-2) in metal layer MX+1 may form a capacitor. Accordingly, inductor structure510formed in metal layer MX+3 and ground shielding strip520A-3(or520B-3) in metal layer MX+2 may collectively form another capacitor.

FIG. 5Cis an illustrative circuit representation of the cross-sectional side view500B shown inFIG. 5Bin accordance with embodiments of the present invention. Circuit500C shows six capacitors550A-1,550A-2,550A-3,550B-1,550B-2, and550B-3coupled to inductor510. It should be noted that the six capacitors represent the capacitors formed by the respective pairs of ground shielding strips (and the respective inductor and ground shielding strip pair) shown inFIG. 5B.

Each pair of capacitors (550A-1and550B-1,550A-2and550B-2,550A-3and550B-3) may be controlled by a switching circuit. As shown inFIG. 5C, switching circuit555-1is coupled between capacitors550A-1and550B-1, switching circuit555-2is coupled between capacitors550A-2and550B-2, and switching circuit555-3is coupled between capacitors550A-3and550B-3. It should be noted that switching circuits555-1,555-2, and555-3may represent NMOS transistors525-1,525-2, and525-3(as shown inFIG. 5B), respectively.

When any of the switching circuits555-1,555-2, and555-3is closed, the corresponding pair of capacitors are coupled in parallel. For example, when switching circuit555-3is closed, capacitor550A-3and capacitor550B-3are coupled in parallel. As mentioned, connecting capacitors in parallel may increase the overall capacitance in a circuit. Accordingly, when any of the switching circuits555-1,555-2, and555-3is closed, the total capacitance of circuit500C may be increased. In one embodiment, any or all of switching circuits555-1,555-2, and555-3may be closed at any one time to obtain the desired capacitance. In the example ofFIG. 5C, maximum capacitance may be obtained by closing all of switching circuits555-1,555-2, and555-3.

It should be noted that even though four metal layers MX, MX+1, MX+2, and MX+3 are shown in the embodiment ofFIG. 5B, more or fewer metal layers may be formed in an integrated circuit, and more (or fewer) ground shielding strips may be formed on those metal layers. Accordingly, more or fewer capacitors may be connected in circuit500C ofFIG. 5C. As an example, an additional metal layer may be formed above metal layer MX+3 ofFIG. 5Band an additional ground shielding strip may be formed in that metal layer.

FIG. 6shows an illustrative cross-sectional side view600of an inductor structure formed between two metal layers in accordance with embodiments of the present invention. It should be noted that cross-sectional side view600shares similarities with cross-sectional side view600B ofFIG. 5Band as such, for the sake of brevity, elements that have been described above (e.g., inductor structure510; metal layers MX, MX+1, MX+2, and MX+3; ground shielding strips520A-1,520A-2,520A-3,520B-1,520B-2and520B-3; and switching circuits525-1,525-2, and525-3) are not described in detail again.

In the embodiment ofFIG. 6, an additional pair of ground shielding strips620A and620B are formed in metal layer MX+4 above inductor structure510. Accordingly, the pair of ground shielding strips620A/620B and inductor structure510may form a pair of capacitors (shown in dotted lines). A switching circuit625may be coupled between the pair of ground shielding strips620A and620B. Switching circuit625may connect the pair of ground shielding strips620A and620B together to adjust the capacitance value provided to inductor structure510. In the embodiment ofFIG. 6, an NMOS transistor is used as switching circuit625. It should be noted that even though four switching circuits are shown inFIG. 6, more or fewer ground shielding strips may be formed in different metal layers and different numbers of switching circuits may be used in this context.

The embodiments, thus far, were described with respect to programmable logic circuits. The method and apparatus described herein may be incorporated into any suitable circuit. For example, the method and apparatus may also be incorporated into numerous types of devices such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just to name a few.