Strained-channel semiconductor device fabrication

A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.

BACKGROUND

Unqualified improvements are not always possible. Often technological advances have drawbacks that must be balanced against the benefits conveyed. These drawbacks may render a refinement that is appropriate for one application undesirable elsewhere. For example, increasing IC device strain improves carrier mobility through the channel region but also increases device leakage. The improved performance is necessary in some applications, whereas the increased leakage is not acceptable in others. Methods of controlling characteristics such as device strain allow designers to manage the tradeoffs posed by modern IC manufacturing techniques.

DETAILED DESCRIPTION

The present disclosure relates generally to IC device manufacturing and more particularly, to a method for controlling device strain in IC devices and to the devices thereby formed.

A method100for manufacturing an IC device and IC devices200and250are described with reference made toFIGS. 1-9.FIG. 1is a flow diagram of the method100for manufacturing an IC device according to aspects of the present disclosure. It is understood that additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced or eliminated for other embodiments of the method.FIGS. 2-9are sectional views of the first IC device200and the second IC device250according to various embodiments of the present disclosure.

Referring toFIG. 1, the method100begins at block102where a substrate202is received. The substrate may be a wafer, a semiconductor substrate, or any base material on which processing is conducted to produce layers of material, pattern features, and/or integrated circuits. In the present example, the substrate is a bulk silicon substrate. Alternatively, the semiconductor substrate includes an elementary semiconductor including silicon or germanium in crystal; a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. The alloy semiconductor substrate may have a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. The alloy SiGe may be formed over a silicon substrate. The SiGe substrate may be strained. Furthermore, the semiconductor substrate may be a semiconductor on insulator (SOI). In some examples, the semiconductor substrate may include a doped epi layer. In other examples, the silicon substrate may include a multilayer compound semiconductor structure. Alternatively, the substrate may include a non-semiconductor material, such as a glass substrate for thin-film-transistor liquid crystal display (TFT-LCD) devices, or fused quartz or calcium fluoride for a photomask (mask).

Some exemplary substrates include an insulator layer. The insulator layer comprises any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and/or combinations thereof. An exemplary insulator layer may be a buried oxide layer (BOX), oxidation, deposition, and/or other suitable process. In some substrates, the insulator layer is a component (e.g., layer) of a silicon-on-insulator substrate.

The substrate may include various doped regions depending on design requirements as known in the art (e.g., p-type wells or n-type wells). The doped regions may be doped with p-type dopants, such as phosphorus or arsenic, and/or n-type dopants, such as boron or BF2. The doped regions may be formed directly on the substrate, in a P-well structure, in a N-well structure, in a dual-well structure, or using a raised structure. The semiconductor substrate may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device (referred to as an NMOS) and regions configured for a P-type metal-oxide-semiconductor transistor device (referred to as a PMOS). It is understood that the first IC device200and the second IC device250may be formed by CMOS technology processing, and thus some processes are not described in detail herein.

The substrate202may further include one or more isolation regions on the substrate202to isolate various regions of the substrate, for example, to isolate NMOS and PMOS device regions. The isolation regions may utilize isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various regions. The isolation regions can comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The isolation regions can be formed by any suitable process. As one example, the formation of an STI may include a photolithography process, etching a trench in the substrate (for example, by using a dry etching and/or wet etching process), and filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials. The filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

As illustrated inFIG. 2, one or more gate stacks204may be formed on the substrate202. In a gate first process, the gate stack204may be all or part of a functional gate. Conversely, in a gate last process, the gate stack204may be a dummy gate. An exemplary gate stack204includes an interfacial layer, a gate dielectric layer206, a gate electrode layer208, and a hard mask layer210. An exemplary interfacial layer includes silicon oxide (e.g., thermal oxide or chemical oxide) and/or silicon oxynitride (SiON) and may be formed by any suitable process to any suitable thickness.

The gate stack204is formed by any suitable process or processes. For example, the gate stack204can be formed by a procedure including deposition, photolithography patterning, and etching processes. The deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods, and/or combinations thereof. The photolithography patterning processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. Alternatively, the photolithography exposing process is implemented or replaced by other proper methods such as maskless photolithography, electron-beam writing, and ion-beam writing. The etching processes include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching).

In block104, an identification of IC devices that benefit from high-strain processes is received. In various embodiments, the identification is received from an integrated circuit design facility, from an integrated circuit manufacturer, from a manufacturing equipment provider, from a packaging facility, from an integrated circuit consumer, and/or from other design, manufacturing, and consuming facilities.

Devices may be identified based on an intrinsic property of the device. For example, IC devices with smaller critical dimensions may require greater carrier mobility in order to meet performance requirements. Thus, small-gate IC devices may be designated high-strain. High-strain devices may be identified based on a processing factor. For example, nMOS devices tend to benefit most from tensile strain, whereas pMOS devices derive performance benefits from compressive strain. For processes that induce tensile strain, nMOS devices may be designated high-strain. As a further example, a method for creating and memorizing strain may induce smaller strain forces on devices with smaller critical dimensions. This is typical for uniaxial strain processes. To compensate, smaller devices may be designated high-strain. Cumulative strain increases as the strained area increases. Thus, devices with larger gate-to-gate spacing may exhibit greater strain effects. This can lead to dislocations in IC devices having a larger strained volume. Dislocations tend to increase device leakage, which may not be acceptable. IC devices which are unlikely to form dislocations may be selected to undergo processes that create relatively greater device strain without adverse effects. High-strain devices may also be identified based on the application. For example, IC devices critical to overall performance may be designated high-strain. In many embodiments, devices are identified based on a combination of device properties, processing characteristics, and performance requirements. Other criteria for identifying high-strain devices are contemplated as well. Referring toFIG. 2, first IC device200is a high-strain IC device.

In block106, an identification of low-strain IC devices is received. As with high-strain IC devices, low-strain IC devices may be identified by a device characteristic such as gate width, source/drain region area, process factors, performance characteristics, design considerations, and/or other suitable criteria. Referring toFIG. 2, second IC device250is a low-strain IC device.

Referring to block108andFIG. 3, an implantation is performed on the source/drain regions of the high-strain devices. The implantation process or processes introduce dopant atoms into the substrate. The doping species depends on the type of device being fabricated and includes p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. Implantation may include forming lightly doped source/drain (LDD) regions302. LDD regions302are formed in the substrate202by ion implantation processes, photolithography processes, diffusion processes, annealing processes (e.g., rapid thermal annealing and/or laser annealing processes), and/or other suitable processes. Implantation may also include forming halo/pocket regions304, which can reduce short channel effects (e.g., punch-through effects). Processes used to create halo/pocket regions304may include a tilt-angle ion implantation, such as a large-angle tilted halo/pocket implantation. In an embodiment, the implantation process damages the lattice structure of the substrate202and forms amorphous regions306. In a further embodiment, the halo/pocket region304and the amorphous regions306are formed by a single implantation. An implantation specifically designed to damage the lattice structure may be referred to as a pre-amorphization implantation (PAI). A PAI may be performed using a dopant, or, when doping is not desired, using a semiconductor such as Ge. A single PAI may involve both doping species and semiconductor species.

Referring toFIG. 3, in order to limit the implantation to only the source/drain regions of the high-strain devices, other devices on the substrate202, including the low-strain devices, may be covered by a resist layer308prior to implantation. The resist layer308is patterned to expose only the high-strain devices to implantation. In an embodiment, the resist layer308is a photoresist. In a further embodiment, the resist layer308is a hard mask. Exemplary hard mask materials include an oxide material, such as silicon oxide; a nitrogen-containing material, such as silicon nitride or silicon oxynitride, an amorphous carbon material; silicon carbide; tetraethylorthosilicate (TEOS); other suitable materials; and/or combinations thereof. Patterning the resist layer308may include exposing the resist layer308to a pattern through a process such as photolithography, may include performing a post-exposure bake process, and may include developing the resist layer308. Patterning may also be implemented or replaced by other proper methods, such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. The resist layer308may be removed after implantation and prior to annealing.

In block110, an annealing process is performed in the substrate202. Referring toFIGS. 3 and 4, in an embodiment, the annealing process restores the crystalline structure of amorphous regions306. The annealing process may be a rapid thermal anneal (RTA) or a millisecond thermal anneal (MSA), such as a millisecond laser thermal anneal. In one embodiment, the annealing process is implemented in a rapid thermal annealing (RTA) tool. In another embodiment, the annealing process is applied to the substrate202with an annealing temperature ranging between about 700° C. and about 1500° C. In another embodiment, the annealing process is applied to the substrate202with an annealing duration ranging between about 2 milliseconds and about 30 seconds. The annealing process may include a long range pre-heat, which reduces or even eliminates end of range (EOR) defects. Suitable ranges for the long range pre-heat range from about 200° C. to about 700° C., and include other appropriate temperatures and ranges. The long range pre-heat may be performed for about 50 to about 300 seconds. In a particular embodiment, the long range pre-heat has a temperature of about 550° C. for about 180 seconds.

Referring to block112andFIG. 5, an implantation process is performed on the source/drain regions of the low-strain devices. This may include forming lightly doped source/drain (LDD) regions502and/or halo/pocket regions504. In an embodiment, the implantation process includes a PAI that damages the lattice structure of the substrate202and forms amorphous regions506. Referring toFIG. 5, in order to limit the implantation to only the source/drain regions of the low-strain devices, other devices on the substrate202, including the high-strain device200, may be covered by a resist layer508. The resist layer508is patterned to expose only the low-strain devices to implantation. In an embodiment, the resist layer508is a photoresist layer. In another embodiment, the resist layer508is a hard mask. In an example of such an embodiment, the hard mask resist layer508is patterned using a photoresist layer. In many embodiments, the resist layer508is removed after the implantation process is performed.

Referring to block114andFIG. 6, a capping layer602is deposited. In an embodiment, the capping layer602comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, and/or combinations thereof. The capping layer602may be formed by thermal deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, other processes known to one of skill in the art and/or combinations thereof. The capping layer602may be used to form spacers604on the gate stack. In such embodiments, the deposition of the capping layer602is adapted to control the thickness of the spacers604. In various examples, the thickness of a SiN capping layer602range from about 50 A to about 200 A, and the thickness of an oxide capping layer602range from about 15 A to about 50 A. In some embodiments, forming the capping layer602is followed by a chemical-mechanical planarization (CMP) process.

In block116, source/drain recesses702aand702bare created, as shown inFIG. 7. Recess creation may include an etching process, such as a dry etching process, wet etching process, and/or combination thereof. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. For example, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. After the etching process, a pre-cleaning process may be performed to clean the source/drain recesses702aand702bwith a hydrofluoric acid (HF) solution or other suitable solution.

Even though the high-strain device and the low-strain device may undergo the same etching process, the structure of the source/drain regions may cause dramatically different etching profiles. In an illustrated embodiment, the source/drain regions of the high-strain device200are recrystallized during the post-implantation annealing. Therefore, the etching process can be configured to produce a source/drain recess702awith uniform edges along a crystalline plane. In one of such embodiments, the etching profile of the source drain recess702ais defined by a surface704ain a {111} crystallographic plane of the substrate202, and a surface704bin a {100} crystallographic plane of the substrate202. Conversely, the low-strain device250may not undergo a post-implantation annealing process, and therefore the source/drain regions may retain an amorphous structure. As a result, the etching process may produce a source/drain recess702bwith a different recess profile such as the arcuate surface706.

In some embodiments, the etching step includes an anisotropic etching. Anisotropic etching is orientation dependent and may be used to create alternate recess profiles. For example, an etching may be performed using TMAH. Because TMAH is an anisotropic etchant, TMAH produces different etching profiles when used to etch uniformly crystalline regions compared to amorphous regions. Other anisotropic etchants include KOH and EDP (ethylene diamine and pyrocatechol). Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching).

Referring to block118andFIG. 8, a source/drain epitaxy is performed. Epitaxy forms source/drain structures802aand802bin the recesses702aand702bof the substrate by depositing a semiconductor material. The epitaxial process may include a selective epitaxy growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epi process, or combination thereof. The epi process may use gaseous and/or liquid precursors, which may interact with the composition of the substrate202. In an example, where an NFET device is desired, the source/drain structures include epitaxially grown silicon (epi Si). Alternatively, where a PFET device is desired, the source/drain structures include epitaxially grown silicon germanium (SiGe). The source/drain structures may be in-situ doped or undoped during the epi process. For example, the epitaxially grown SiGe source/drain features may be doped with boron; and the epitaxially grown Si epi source/drain features may be doped with carbon to form Si:C source/drain features, phosphorous to form Si:P source/drain features, or both carbon and phosphorous to form SiCP source/drain features. When the source/drain features are undoped, it is understood that they may be doped in a subsequent process. The doping may be achieved by an ion implantation process, plasma immersion ion implantation (PIII) process, gas and/or solid source diffusion process, other suitable process, or combinations thereof.

Referring to block120andFIG. 9, an annealing process may be performed on the substrate202and the source/drain structures802aand802b. Annealing processes include rapid thermal annealing (RTA) and a millisecond thermal annealing (MSA), such as millisecond laser thermal annealing. The annealing process may also include a long range pre-heat. In an embodiment, the annealing process includes a pre-heat performed by epitaxial equipment used to perform the source/drain epitaxy of block118. In an embodiment, the annealing process recrystallizes amorphous structures within the source/drain regions such as region802bas well as structures within the substrate202such as the amorphous region506ofFIG. 8.

A further embodiment of a method1000for manufacturing an IC device and IC devices1100and1150are described with reference made toFIGS. 10-13.FIG. 10is a flow diagram of the method1000for manufacturing an IC device according to aspects of the present disclosure. It is understood that additional steps can be provided before, during, and after the method1000, and some of the steps described can be replaced or eliminated for other embodiments of the method. The embodiment of method1000may include similar process steps as embodiments of the method100, which is disclosed above. With respect to method1000, some details regarding processing and/or structure may be skipped for simplicity if they are similar to those described in the embodiment of method100.FIGS. 11-13are sectional views of the first IC device1100and the second IC device1150according to various embodiments of the present disclosure. The semiconductor devices1100and1150ofFIGS. 11-13are similar in certain respects to the semiconductor devices200and250ofFIGS. 2-9. Accordingly, similar features inFIGS. 2-9andFIGS. 11-13are identified by the same reference numerals for clarity and simplicity. In this way,FIGS. 11-13have been simplified for the sake of clarity to better convey the inventive concepts of the present disclosure.

Referring to block1002ofFIG. 10, the method1000begins with the receipt of a substrate. The receipt of the substrate in block1002is substantially similar to that of block102of method100ofFIG. 1. In that regard, the substrate may be a wafer, a semiconductor substrate, and/or any other base material on which processing is conducted. The substrate may include an insulator layer, various doped regions, isolation regions, and/or one or more gate stacks. Referring to block1004ofFIG. 10, an identification of IC devices to undergo a high-strain process is received. The receipt of the identification of high-strain IC devices in block1004is substantially similar to that of block104of method100ofFIG. 1. Referring to block1006ofFIG. 10, an identification of IC devices to undergo a low-strain process is received. The receipt of the identification of low-strain IC devices in block1006is substantially similar to that of block106of method100ofFIG. 1. Referring to block1008ofFIG. 10, an implantation is performed on a high-strain device. The implantation in block1008is substantially similar to that of block108of method100ofFIG. 1. For example, as described with respect to block108, the implantation may include the formation of a resist layer over areas that are not intended to be implanted. Referring to block1010ofFIG. 10, an annealing is performed on the substrate. The annealing in block1010is substantially similar to that of block110of method100ofFIG. 1. Referring to block1012ofFIG. 10, an implantation is performed on a low-strain device. The implantation in block1012is substantially similar to that of block112of method100ofFIG. 1. For example, as described with respect to block112, the implantation may include the formation of a resist layer over areas that are not intended to be implanted. Referring to block1014ofFIG. 10, a capping layer is deposited. The deposition in block1014is substantially similar to that of block114of method100ofFIG. 1.

Referring now to block1016ofFIG. 10and toFIG. 11, source/drain recesses702aand702bare created. Source/drain recesses702aand702bare substantially similar to recesses702aand702bofFIG. 7and are formed by a process substantially similar to that of block116of method100ofFIG. 1. For example, source/drain recesses702aand702bofFIG. 11may be created by an etching process, such as a dry etching process, wet etching process, and/or combination thereof. In an embodiment, the etching process is configured to produce a source/drain recess702awith uniform edges along a crystalline plane. In one of such embodiments, the etching profile of the source drain recess702ais defined by a surface704ain a {111} crystallographic plane of the substrate202, and a surface704bin a {100} crystallographic plane of the substrate202. In a further embodiment, the etching process may produce a source/drain recess702bwith a different recess profile such as the arcuate surface706.

Referring to block1018andFIG. 12, in an embodiment, an annealing process is performed on the recessed substrate202prior to source/drain epitaxy. In one such embodiment, the annealing process restores the crystalline structure of amorphous regions such as amorphous region506ofFIG. 11. In an embodiment, the annealing process includes a pre-heat process carried out by equipment further suitable for an epitaxial growth process. For example, the temperature of the annealing process may be between about 500° C. and about 800° C. In an embodiment, the duration of the annealing process is between about 10 second and about 600 seconds.

Referring to block1020andFIG. 13, source/drain epitaxy is performed on the annealed substrate. The epitaxial process of block1020is substantially similar to that of block120of method100ofFIG. 1. For example, the epitaxial process of block1020may form source/drain structures802aand802bin the recesses702aand702bof the substrate by depositing a semiconductor material. The epitaxial process may include a selective epitaxy growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial process, or combination thereof. The epitaxial process may use gaseous and/or liquid precursors, which may interact with the composition of the substrate202. The source/drain structures may be in-situ doped or may be formed undoped during the epitaxial process.

As will be obvious to one of skill in the art, a method to control the strain present in a device and to produce a single substrate with high- and low-strain devices provides designers and manufacturers the ability to balance the benefits of strained-channel devices against the tradeoffs including increased power consumption. Thus, the present disclosure provides a method for producing differently strained IC devices on a single substrate and provides the devices thereby formed.

In one embodiment, the method comprises: receiving an IC device substrate having a device region corresponding to an IC device; performing an implantation process on the device region, thereby forming an amorphous region having an amorphous crystalline structure, the amorphous region disposed within the device region; recessing the IC device substrate to define a source/drain recess in the device region, wherein the recessing is configured to define the source/drain recess as having a profile determined by the amorphous crystalline structure of the amorphous region; and performing source/drain epitaxy after the recessing of the IC device substrate to form a source/drain structure within the source/drain recess.

In a further embodiment, the semiconductor device comprises: an IC device substrate having a device region corresponding to a IC device; a gate stack disposed within the device region and defining a source/drain region of the IC device substrate; and a source/drain structure disposed within the source/drain region, wherein the source/drain structure defines a surface between the IC device substrate and the source/drain structure; and wherein the surface has an arcuate profile.

In yet another embodiment, the semiconductor device comprises: an IC device substrate having a first device region corresponding to a first IC device and a second device region corresponding to a second IC device; a first gate stack disposed within the first device region and defining a first source/drain region, wherein the first source/drain region includes a first source/drain structure disposed within the IC device substrate, and wherein the first source/drain structure has a first profile; a second gate stack disposed within the second device region and defining a second source/drain region, wherein the second source/drain region includes a second source/drain structure disposed within the IC device substrate, wherein the second source/drain structure has a second profile, and wherein the first profile and the second profile are different.