Random access memory RAM employing complementary transistor switch (CTS) memory cells

The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.

CROSS REFERENCE TO RELATED US PATENT APPLICATION 
U.S. patent application Ser. No. 624,488 entitled "Improved Random Access 
Memory Array Employing Complementary Transistor Switch (CTS) Memory Cells" 
filed June 25, 1984 by Y. H. Chan, F.D. Jones and W. F. Stinson. 
U.S. patent application Ser. No. 624,486 entitled "Voltage Mode Operation 
Scheme For Bipolar Array" filed June 25, 1984 by Y. H. Chan and J. R. 
Struk. 
BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention is directed to an improved random access memory (RAM). More 
particularly the invention is directed to improved bit selection circuitry 
and to improved word line selection circuitry for an array using CTS 
(Complementary Transistor Switch) memory cells, or "unclamped" CTS memory 
cells. 
2. Background Art 
The following patents and publications are directed to memory array 
circuitry and more particularly bit selection, word line selection and 
related circuitry employed therein. It is to be appreciated that the 
following art is not submitted to be the only, the best, or the most 
pertinent art. 
Patents 
U.S. Pat. No. 3,423,737 entitled "Nondestructive Read Transistor Memory 
Cell" granted Jan. 21, 1969 to L. R. Harper. 
U.S. Pat. No. 3,525,084 entitled "Memory Sense System with Fast Recovery" 
granted Aug. 18, 1970 to L. J. Dunlop et al. 
U.S. Pat. No. 3,582,911 entitled "Core Memory Selection Matrix" granted 
June 1, 1971 to J. P. Smith. 
U.S. Pat. No. 3,623,033 entitled "Cross-Coupled Bridge Core Memory 
Addressing System" granted Nov. 23, 1971 to P. A. Harding. 
U.S. Pat. No. 3,636,377 entitled "Bipolar Semiconductor Random Access 
Memory" granted Jan. 18, 1972 to P. C. Economopoulos et al. 
U.S. Pat. No. 3,736,574 entitled "Pseudo-Hierarchy Memory System" granted 
Dec. 30, 1971 to E. D. Gersbach et al. 
U.S. Pat. No. 3,753,008 entitled "Memory Pre-Driver Circuit" granted Aug. 
14, 1973 to G. Guarnashelli. 
U.S. Pat. No. 3,771,147 entitled "IGFET Memory System" granted Nov. 6, 1973 
to H. J. Boll et al. 
U.S. Pat. No. 3,786,442 entitled "Rapid Recovery Circuit For Capacitively 
Loaded Bit Lines" granted Jan. 15, 1974 to S. B. Alexander et al. 
U.S. Pat. No. 3,789,243 entitled "Monolithic Memory Sense Amplifier/Bit 
Driver Having Active Bit/Sense Pull-Up" granted Jan. 29, 1974 to N. M. 
Donofrio et al. 
U.S. Pat. No. 3,843,954 entitled "High-Voltage Integrated Driver Circuit 
and Memory Embodying Same" granted Oct. 22, 1974 to A. A. Hansen et al. 
U.S. Pat. No. 3,863,229 entitled "SCR (or SCS) Memory Array with Internal 
and External Load Resistors" granted Jan. 28, 1975 to J. E. Gersbach. 
U.S. Pat. No. 3,919,566 entitled "Sense-Write Circuit for Bipolar 
Integrated Circuit Ram" granted Nov. 11, 1975 to M. S. Millhollan et al. 
U.S. Pat. No. 3,942,160 entitled "Bit Sense Line Speed-Up Circuit for Mos 
Ram granted Mar. 2, 1976 to R. T. Yu. 
U.S. Pat. No. 4,007,451 entitled "Method and Circuit Arrangement for 
Operating A Highly Integrated Monolithic Information Store granted Feb. 8, 
1977 to K. Heuber et al. 
U.S. Pat. No. 4,042,915 entitled "Mos Dynamic Random Access Memory Having 
An Improved Address Decoder Circuit granted Aug. 16, 1977 to J. A. Reed. 
U.S. Pat. No. 4,078,261 entitled "Sense/Write Circuits for Bipolar Random 
Access Memory" granted Mar. 7, 1978 to M. S. Millhollan et al. 
U.S. Pat. No. 4,090,254 entitled "Charge Injector Transistor Memory" 
granted May 16, 1978 to I. T. Ho et al. 
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating A 
Semiconductor Memory System" granted May 16, 1978 to H. H. Berger, et al. 
U.S. Pat. No. 4,104,735 entitled "Arrangement for Addressing A Mos Store" 
granted Aug. 1, 1978 to R. Hofmann. 
U.S. Pat. No. 4,172,291 entitled "Preset Circuit For Information Storage 
Devices" granted Oct. 23, 1979 to W. K. Owens, et al. 
U.S. Pat. No. 4,174,541 entitled "Bipolar Monolithic Integrated Circuit 
Memory With Standby Power Enable" granted Nov. 13, 1979 to C. R. Schmitz. 
U.S. Pat. No. 4,194,130 entitled "Digital Predecoding System" granted Mar. 
18, 1980 to J. D. Moench. 
U.S. Pat. No. 4,200,918 entitled "Control Circuit For The Adaptation of 
Storage Cells In Bipolar Integrated Circuits" granted Apr. 29, 1090 to H. 
Glock et al. 
U.S. Pat. No. 4,242,605 entitled "Transient Array Drive For Bipolar 
Rom/Prom" granted Dec. 30, 1980 to W. C. Seelbach. 
U.S. Pat. No. 4,264,828 entitled "Mos Static Decoding Circuit" granted Apr. 
28, 1981 to G. Peregos et al. 
U.S. Pat. No. 4,287,575 entitled "High Speed High Density, Multi-Port 
Random Access Memory Cell" granted Sept. 1, 1981 to D. H. Eardley et al. 
U.S. Pat. No. 4,308,595 entitled "Array Driver" granted Dec. 29, 1981 to R. 
J. Houghton. 
U.S. Pat. No. 4,322,820 entitled Semiconductor Integrated Circuit Device" 
granted Mar. 30, 1982 to K. Toyoda. 
U.S. Pat. No. 4,323,986 entitled "Electric Storage Array Having DC Stable 
Conductivity Modulated Storage Cells" granted Apr. 6, 1982 to S. D. 
Malaviva. 
U.S. Pat. No. 4,326,270 entitled "Preset Circuit For Information Storage 
Devices" granted Apr. 20, 1982 to W. K. Owens et al. 
U.S. Pat. No. 4,330,853 entitled "Method of and Circuit Arrangement For 
Reading and/or Writing An Integrated Semiconductor Storage With Storage 
Cells In MLT (I.sup.2 L) Technology" granted May 18, 1982 to H. H. 
Heimeier et al. 
U.S. Pat. No. 4,413,191 entitled "Array Word Line Driver System" granted 
Nov. 1, 1983 to R. J. Houghton. 
U.S. Pat. No. 4,417,159 entitled "Diode-Transistor Active Pull Up Driver" 
granted Nov. 22, 1983 to J. A. Dorler et al. 
U.S. Pat. No. 4,417,326 entitled "Static Semiconductor Memory Device" 
granted Nov. 22, 1983 to K. Toyoda et al. 
Publications 
[IBM Technical Disclosure Bulletin (IBM TDB)] 
"Static Cell Array Circuit to Enable Write by Turning Off The Cell Load 
Devices" by D. B. Eardley, IBM TDB, Vol. 24, No. 6, Nov. 1981, pages 
3044-47. 
"AC Write Scheme For Bipolar Random-Access Memories Using Schottky Coupled 
Cells" by J. A. Dorler et al, IBM TDB, Vol. 23, No. 11, Apr. 1981, pages 
4960-2. 
"Constant Voltage, Current Sensing Circuit" by V. Marcello et al, IBM TDB, 
Vol. 24, No. 1B, June, 1981 pages 483-4. 
"Tri-State Read/Write Control Circuit" by V. Marcello et al, IBM TDB Vol 
24, No. 1B, June 1981, pages 480-2. 
"Read/Write Control Circuit Reference Voltage Generator" by V. Marcello et 
al, IBM-TDB, Vol. 24, No. 1B, June, 1981, pages 478-9. 
"Bit Current Steering Network" by V. Marcello et al, IBM TDB Vol 24, No. 
1B, June 1981, pages 475-77. 
"Complementary Transistor Switch Memory Cell" by J. A. Dorler et al, IBM 
TDB, Vol 16, No. 12, May 1984. 
"Memory Cell" by S. K. Wiedmann, IBM TDB Vol 13, No. 3, August 1970, pages 
616-7. 
"A 1024 Byte ECL Random Access Memory Using a Complementary Transistor 
Switch (CTS) Cell" by J. A. Dorler et al, IBM Journal of Research and 
Development, Vol 25, No. 3, May, 1981, pages 126-34. 
"Bit Driver and Select Circuit For Schottky-Coupled Cell Arrays" by C. U. 
Buscaglia et al, IBM TDB, Vol 24, No. 10, March, 1982, pages 5167-8. 
"Low Power Write Circuit For Fast VLSI Arrays" by R. D. Dussault et al, IBM 
TDB, Vol. 24, No. 11A, April, 1982, pages 5630-1. 
"Read/Write Scheme For Bipolar Random-Access Memories Using Schottky 
Coupled Cells" by R. D. Daussault et al, IBM TDB, Vol. 24, No. 11A, April, 
1982, pages 5632-3. 
Random access memories employing CTS type memory cells are known to the 
art. See for the example, The Gerbach Pat. No. 3,863,229, the Dorler et al 
IBM TDB publication, and the Dorler et al IBM Journal of Research and 
Development Article, each fully identified hereinabove. 
The known random access memories and the in particular those employing CTS 
memory cells have two relatively serious bit selection short comings. 
First, the bit decode transistor has to drive a number of bit columns 
across the chip. Due to long metal line and large fan out current, voltage 
drop along the bit decode line is high. The cells at the end of the bit 
decode line may have insufficient voltage across their "1" bit rail 
resistors to provide adequate gate currents into the cells. This may lead 
to potential data retention problems on the selected cells. Secondly, both 
selection and deselection of the bit rails are slow due to the fact that 
the bit decode transistor has large fan-out loadings. Discharge speed of 
the bit rails is limited by the bit rail resistors. The bit selection 
scheme in accordance with the invention obviates the above recited 
short-comings of known RAMs and in particular RAMs using CTS cells. 
In high performance arrays using cells like CTS, selection of a cell is 
accomplished by lowering its word lines and raising its bit rails. Known 
designs use a fixed current source to pull down the selected word lines. 
There are three problems usually associated with this method of word 
selection in "current mode". 
(1) Slow speed. 
With CTS cells, the word lines are very capacitive. (For word lines having 
60 to 80 cells, this word line capacitance could be as high as 30 to 40 
pf). A constant current source pulls down the selected word lines 
according to its large RC time constant. Hence cell selection is very 
slow, and its drive capability is often limited by the fixed source of 
current. 
(2) Instability. 
Since the selected word lines are held down by a current source, their 
voltage levels are easily affected by noise or current source variations. 
If the word line levels drift to a degree that they no longer track with 
those of the bit rails, data retention problems could result. 
(3) Long address set up time to "write". 
During write operation, the bit line voltage of the side to be written a 
"1" is driven high. This causes the bit rail and the drain line levels to 
rise. A long address set up time is needed to wait for the previous 
selected cell to get out of the way before writing can start in order to 
avoid write-through problems. 
The above problems are obviated and overcome by the "voltage mode word 
selection scheme" in accordance with the invention. 
Summary of the Invention 
A primary object of the invention is to provide an improved random access 
memory. 
A further object of the invention is to provide an improved random access 
memory which employs complementary transistor switch (CTS) memory cells, 
particularly the "unclamped" CTS cells. 
A further object of the invention is to provide an improved bit selection 
scheme for a random access memory. 
A further object of the invention is to provide an improved voltage mode 
word selection scheme for a random access memory. 
A further object of the invention is to provide an improved bit selection 
scheme for a random access memory which employs complementary transistor 
switch (CTS) memory cells, particularly the "unclamped" CTS cell. 
A further object of the invention is to provide an improved voltage mode 
word selection scheme for a random access memory which employs 
complementary transistor switch (CTS) memory cells. 
A yet further object of the invention is to provide a random access memory 
employing bit selection circuitry which, particularly in a RAM employing 
unclamped CTS cells, obviates data retention concerns on fully selected 
cells. 
A still further object of the invention is to provide a random access 
memory employing bit selection circuitry which, particularly in a RAM 
employing unclamped CTS cells, improves the line select and deselect 
speeds. 
A still further object of the invention is to provide a random access 
memory employing a voltage mode word selection scheme which, particularly 
in a RAM employing CTS cells, improves (1) speed of selection of word 
lines, (2) stability of selected word lines, and (3) reduces address 
set-up time for "write" operation. 
The invention may be summarized as improved bit selection circuitry and 
word selection circuitry for a RAM, in particular one using CTS 
(Complementary Transistor Switch) cells. The bit select circuitry includes 
interconnected first and second level matrix decoders, each memory column 
has a pair of bit lines, each pair of bit lines has connected thereto bit 
select circuit means, each of said bit select circuit means being 
connected to an output of said second level decoder, a bit up-level clamp 
circuit connected to each of said bit select circuit means of each pair of 
bit lines, each of said bit select circuit means including first circuit 
means for increasing the speed of selection of the selected pair of bit 
lines, said bit up-level clamp circuit cooperating with said bit select 
circuit means of said selected pair of bit lines for positively limiting 
the upper potential level of said selected pair of bit lines, and each of 
said bit select circuit means including second circuit means for 
increasing the speed of deselection of the selected pair of bit lines. The 
invention also includes voltage mode word selection means in a RAM 
preferably employing CTS type memory cells. 
The foregoing and other objects, features and advantages of the invention 
will be apparent from the following more particular description of 
preferred embodiments of the invention, as illustrated in the accompanying 
drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
In high performance arrays using CTS cells, selection of a cell is done by 
lowering its word lines and raising its bit rails. As depicted in FIG. 1, 
known designs use a fixed current source to pull down the selected word 
and drain lines. There are three problems frequently associated with the 
"current mode" method of word selection. 
(1) Slow speed. 
With CTS cells, the word lines are very capacitive. (For word lines having 
60 to 80 cells, this word line capacitance could be as high as 30 to 40 
pf). A constant current source pulls down the selected word line according 
to its large RC time constant. Hence, cell selection is very slow, and its 
drive capability is often limited by the fixed source of current. 
(2) Instability. 
Since the selected word lines are held down by a current source, their 
voltage levels are easily affected by noise or current variations. If the 
word line levels drift to a degree that they no longer track with those of 
the bit rails, data retention problems could result. 
(3) Long address set up time to "write" 
During write operation, the bit line voltage of the side to be written a 
"1" is driven high. This causes the bit rail and the drain line levels to 
rise. A long address set up time is needed to wait for the previous 
selected cell to go out of the way before writing can start in order to 
avoid write-through problems. 
The above problems are overcome and obviated by the "voltage mode word 
selection technique" in accordance with the invention and as disclosed 
herein. FIG. 8 shows the schematic diagram of this scheme. 
Also known high performance arrays using CTS cells have bit selection 
concerns or short comings. Again referring to FIG. 1, these concerns are 
as follows: 
1. The bit decode transistor TB has to drive a number of bit columns across 
the chip. Due to long metal line and large fanout current, voltage drop 
along the bit decode line (BD) is high. The cells at the end of the bit 
decode line may have insufficient voltage potential across their "1" bit 
rail resistors to define adequate gate currents (I1) into the cells. This 
may lead to potential data retention problems on the selected cells. 
2. Both selection and deselection of the bit rails are slow, due to the 
fact that the bit decode transistor has large fanout loadings. Discharge 
speed of the bit rails is limited by the bit rail resistors RBL and RBR. 
The above problems and concerns are addressed and overcome by the random 
access memory disclosed hereinafter. 
The above problems are overcome by using distributive bit select circuits 
and word line selection circuits illustrated in FIGS. 3, 3A, 8 and 9. 
For purpose of illustration, FIG. 2 shows a 1k.times.4 RAM in accordance 
with the invention. This RAM has an array density of 4096 cells arranged 
in 64 words (rows) by 64 bit (columns). The 64 bit columns are further 
divided into 4 data groups, so that it will write 4 bits (therefore 4 data 
inputs) and read 4 bits (4 data outputs) at a time. The RAM has 6 word 
addresses (to select 1 out of 64 rows) and 4 bit addresses (to select 4 
out of 64 bits). Read and write operations are controlled by the RW input. 
Referring to FIG. 3, a two level matrix decode scheme is employed for bit 
address decoding. The first level decode includes two groups of 4 address 
lines (BA0-BA3 and BA4-BA7) formed from output emitter dotting of the four 
bit address receivers. The bit address receivers are current switch 
emitter follower circuits as shown in FIG. 4. They convert the address 
inputs to true and complement signals. By means of emitter follower output 
dotting of the address receiver pairs, a partial decode of 1 out of 4 is 
formed from each group, hence, giving a total of two selected (low level) 
lines. 
The second level decode function is performed by the 16 bit decoders (FIG. 
5), which have current switch inputs and high speed push-pull outputs. 
Input 1 of the bit decoder is connected to one of the 4 lines in BA0-BA3 
address group, and input 2 is connected to one in the BA4-BA7 group. Of 
the 16 BD output lines, only one is decoded to a selected up level. Each 
BD line fans out to drive four bit columns (one from each data group), so 
that four cells are selected at a time for READ or WRITE operation. 
Each bit column has a bit select circuit (FIGS. 3 and 6) to perform bit 
line select and deselect functions. The selected bit lines up level is set 
by a bit up level clamp circuit (Bit UPCL, FIG. 7), so that the cells' 
read and write operating points can be readily adjusted by changing the up 
clamp (UC) level. 
For unclamped CTS cell, the SCR device operates in saturation mode. The 
cell, is more capacitive (due to higher B-C junction saturation 
capacitance) than a normal CTS with Schottky clamp. This makes the 
unclamped cell very difficult to write. It is essential that the bit 
select circuit is capable of driving high transient current into the cell 
to enable fast write performance. A novel circuit technique utilizing 
capacitive boot straping and transient drive mechanism is designed for 
this application. The bit select circuit's modes of operation are 
described below. 
Unselected State 
In an unselected state, the BD line is held low by its corresponding bit 
decoder to a voltage close to V.sub.N. Transistors T1 and T2 of the bit 
select circuit are driven into inverse saturated mode operation. Nodes 1 
and 2 are clamped low by the B-C junctions of T1 and T2 to a voltage a 
V.sub.BC above the BD level. Nodes 3 and 4 are also driven negative by the 
inverse transistors to a voltage close to that of the BD line (a V.sub.CES 
above from BD). With nodes 1, 2, 3 and 4 being held low, transistors T3, 
T4 and T5, T6 are shut off. No current will flow into the bit rail 
resistors RBL and RBR. The bit lines BL and BR levels are equal to those 
of nodes 3 and 4. In this state, resistors R1 and R2 provide small amount 
of base currents that conducts through T1 and T2 into the BD line. Since 
T1 and T2 conducts in inverse saturation mode, they develop large 
diffusion capacitance (due to storage charge) across their B-C and B-E 
junctions. These storge charges will be used to boot strap nodes 1, 2 and 
nodes 3, 4 up rapidly when the BD line is selected high. 
Selected READ 
When a bit column is selected, its BD line is actively pulled up by the 
corresponding bit decoder to a voltage about a V.sub.BE below V.sub.P. 
This forces the collectors of T1 and T2 to move up quickly at the same 
rate. The rapid discharge of the B-C and B-E junctions of T1 and T2 
provide very fast capacitive push up action on nodes 1, 2 and 3, 4 
respectively. When nodes 3 and 4 move up, high transient currents are 
driven into resistors RBL and RBR to raise bit lines BL and BR. While 
nodes 3 and 4 are moving up, transistors T3 and T4 are also being turned 
ON rapidly to actively pull up the bit lines. It is this transient drive 
mechanism from T3 and T4 that enables high speed bit rail selection. 
During READ mode, both the PDL and PDR lines are high (up at around 
V.sub.P). Nodes 1 and 2's up levels are clamped by the transistor diodes 
T5 and T6 respectively to a voltage set by the UC line. (See FIG. 12). The 
read reference level on the UC line is generated by the bit up level clamp 
circuit in such a way that it tracks with the selected cells' voltages to 
ensure proper read currents (load current I.sub.L and gate current 
I.sub.G). The cell's read currents are supplied by T1 and T2 through 
resistors RBL and RBR. Typical READ currents are set at I.sub.L 
.apprxeq.1.0 mA and I.sub.G .apprxeq.0.2 mA. This results in a voltage 
differential of about 600-700 mV across the bit lines for read sensing by 
the sense amplifier. 
In the selected state, T1 and T2 operate in active forward mode to provide 
DC read currents. Transistors T3 and T4 are only turned ON transiently. 
They will stay OFF after the bit lines BL and BR reach their fully 
selected up levels. Since the BD line's voltage level is set to be higher 
than those of nodes 1 and 2, transistors T1 and T2 in the selected state 
are always kept in active forward conduction. The read currents are 
defined by the read reference level and will not be affected by the BD's 
voltage variations or line drops. 
Selected WRITE 
In the WRITE mode, bit line selection is similar to that of the READ as 
described above. The only difference here is that one of the write control 
lines (either PDL or PDR, depending on the data to be written) is driven 
negative to a voltage close to V.sub.N, by the write control circuit prior 
to bit selection. (See FIG. 13). The lowered PDL or PDR line will clamp 
down either node 1 or 2 through the transistor diode T5 or T6 
respectively, so that when the bit rail is selected, only one side of the 
bit lines will be driven high to provide write current into the cell. The 
other side will stay at down level in order to shut off the bit line 
current that normally flows into the cell. This mode of write operation is 
denoted "Differential Mode Write" hereinafter. 
During WRITE mode, node 1 or 2's up level is also clamped by the transistor 
diode T5 or T6 to a voltage set by the UC line. The write reference 
voltage is typically 600-800 mV above the READ reference voltage, so that 
sufficient over voltage and sufficient write current are always guaranteed 
to provide fast write performance. For unclamped CTS cell, writing is 
primarily done by driving large transient current into the cell to 
overcome its original state. This large transient write current (typically 
a few milli ampere) is sourced by either T3 or T4 from V.sub.P directly. 
After the cell has been written, its bit line voltage will rise up to the 
"1" level. Transistor T3 or T4 will be gradually turned off to remove the 
large transient write current. Resistor RBL or RBR will then supply a 
small DC write current I.sub.W from either T1 or T2 to reinforce the state 
of the newly written cell. As in READ mode, the large transient write 
current is sourced directly from V.sub.P through T3 or T4. The write 
performance is therefore not affected by the BD line's level variation. 
Deselecting 
When a bit column is deselected, its corresponding bit decoder output falls 
to the unselected down level. Transistors T1 and T2 of the bit select 
circuit are driven into inverse saturation mode. Nodes 1, 2 and 3, 4 are 
pulled negative to shut off the read or write bit rail currents. The bit 
lines, at the same time, are also pulled down actively by Schottky diodes 
SL and SR and will discharge into the BD line. While diodes SL and SR are 
pulling down the bit lines, the bit rail resistors RBL and RBR are also 
driven low by the inverse transistors to discharge the bit lines. After 
the bit lines are fully discharged to their unselect down levels, 
resistors RBL, RBR and diodes SL, SR will stop conducting. The bit column 
is now said to be in an unselected state. The disclosed bit select scheme 
has particular utility in arrays using CTS (Complementary Transistor 
Switch, FIG. 1A) cells. With this scheme, at least the following two 
advantages have been achieved over the known designs. 
(I) Improved bit line "select/deselect" speed, hence faster bit path access 
time. 
(II) Eliminates the effects of bit decode up level line drop, hence reduce 
data retention concerns for the selected cells. 
The improved bit selection circuit means, in accordance with the invention 
includes the following elements: 
1. Two level matrix decode (FIG. 3)--First level is emitter dotting of the 
current switch emitter follower address receivers. Second level is the bit 
decoders with current switch input and high speed push-pull outputs. 
2. Distributive bit select circuit (FIGS. 3 & 6). It utilizes capacitive 
discharge mechanism of inverse saturation transistors (T1 & T2) to enhance 
bit rail selection speed. The same transistors are also used in active 
forward mode (when the bit column is selected) to source the DC READ and 
WRITE currents into the cell through resistors RBL and RBR. It has 
transistors T3 and T4 to provide high speed high power transient drive 
mechanism on the bit lines to enable fast READ/WRITE performance. It uses 
Schottky barrier diodes (SL and SR) in conjunction with the bit rail 
resistors RBL & RBR for active bit rail pull down to enable fast bit 
column deselection. It also uses multi-emitter transistor diodes T5 and T6 
for READ/WRITE control as well as setting the operating points for the 
selected cell. 
3. Bit up level clamp (FIGS. 3 and 7)--The selected bit lines' read and 
write up levels are controlled by a reference circuit (Bit UPCL) so as to 
enable easy operating point adjustment. This circuit is also designed, as 
more fully explained hereinafter, to meet various tracking requirements 
(such as tracking with selected drain line level in read mode). 
The improved word line decoder and control circuitry represented by the 
block labelled "Word Decode" in FIG. 3 is shown in detail in FIGS. 8 and 
9. FIG. 8 shows the voltage mode word selection scheme whereas FIG. 9 
discloses in detail the circuit of the word decoder. 
Referring to FIG. 8, there are 6 word addresses to decode 1 out of 64 rows. 
A two level matrix decode scheme similar to that of the bit path is 
employed for word address decoding. The first level decode includes three 
groups of 4 address lines (WA4-WA3, WA0-WA7, and WA8-WAll) formed from 
output emitter dotting of the 6 word address receivers. The word address 
receivers are current switch emitter follower circuits (FIG. 4). They 
convert the address inputs to true and complement signals. By means of 
emitter follower output dotting of the address receiver pairs, a partial 
decode of 1 out of 4 is obtained from each group, hence giving a total of 
three selected (low level) lines. 
The second level decode function is performed by the 64 word decoders (FIG. 
9). Each word decoder has three current switch inputs (IN1-IN3) and two 
high speed high power push-pull outputs (WL and DL). INl of the word 
decoder is connected to one of the four lines in WA0-WA3 address group. 
IN2 is connected to one in the second group (WA4-WA7), and IN3 is 
connected to one in the third group (WA8-WAll). All these three inputs 
have to be low in order to select a row line. The two outputs of the word 
decoder are connected to the word line (WL) and drain line (DL) of the 
memory cells as shown. 
Operations of the word decoder, in accordance with the invention, are 
explained hereinafter. 
Unselected state 
An unselected word decoder will have at least one of its three inputs high. 
Decoding transistors T1, T2 or T3 are turned ON to pull down node 1. 
Transistors T5 and T6 form a dual phase level shifter, so that node 4 is 
also pulled negative to a voltage close to V.sub.N and node 3 is pulled 
positive to V.sub.P. With node 4 being down, the open collector transistor 
TL is shut off, allowing the word line WL and drain line DL to move up to 
their unselected (high) levels. In this state, the cells' stand-by 
current, as well as word and drain line voltages are defined by the 
current sources I.sub.SBH and I.sub.SBL. 
To enable fast switching speed, transistors T5 and T6 are never shut OFF 
but kept in slight conduction. The active pull up devices (T.sub.7 and 
T.sub.H) are OFF when the word line reaches its full unselected DC level 
(about one and a half V.sub.BE below V.sub.P). 
Selected state 
When a word decoder is selected, all its three inputs are low. Transistors 
T1, T2 and T3 are OFF. Node 1 goes high to turn ON T5 and T6 hard. Node 3 
is pulled down by T5's collector to keep T.sub.7 -T.sub.H OFF, so that WL 
and DL are allowed to move down to their selected levels. At the same 
time, node 4 is driven high to turn ON TL. It is this high power open 
collector pull down action on the drain line that enables the cells to be 
selected fast. While the drain line is being driven low, the word line 
follows it at the same rate with a voltage offset defined by the cells. 
When the word and drain lines are fully selected, T.sub.7 -T.sub.H are OFF 
and TL is maintained ON to sink the large READ/WRITE currents conducting 
from the selected cells. In this state, the word and drain line voltages 
are defined by following two equations: 
EQU V.sub.(DL) =V.sub.N +V.sub.CE(TL) (1) 
EQU V.sub.(WL) =V.sub.(DL) +V.sub.(CELL) (2) 
Since the selected drain line is pulled down by a high power open collector 
transistor (T.sub.L), word selection is therefore very fast and its drive 
capability is not limited by fixed current sources as in prior designs. 
Furthermore, the selected drain and word line levels are solidly defined 
to voltages offset from power supply V.sub.N, they are more stable than 
those of the prior art. This technique of word selection is denoted herein 
as "Voltage Mode Word Selection". 
Deselected state 
After a row line has been selected for a READ or a WRITE operation, it is 
deselected back to its stand-by state. A deselecting word decoder will 
have at least one of its inputs go positive. Decoding transistors T1, T2 
or T3 are turned ON again, driving node 1 down to shut OFF the open 
collector transistor T.sub.L. At the same time, node 4 is pulled positive 
to V.sub.P, driving the emitter follower devices T.sub.7 -T.sub.H 
transiently ON to pull up word line WL until it reaches its unselected DC 
level. While the word line is being pulled positive, drain line DL follows 
it up at the same rate with a voltage offset defined by the cells. When 
the word and drain lines are fully up at their stand-by levels, T.sub.7 
-T.sub.H and T.sub.L are all OFF. The row line is now said to be in an 
unselected state. 
READ operation 
A cell is selected for the READ operation when its row lines (WL, DL) and 
bit lines (BL, BR) are both selected (FIG. 12). The row lines are selected 
by the voltage mode word selection scheme as previously described. The bit 
lines are selected by the bit selection scheme explained earlier (FIG. 3). 
After a cell is fully selected, read currents I.sub.L and I.sub.G are fed 
into its bit rail Schottky SL and SR, which then couple the cell's 
internal voltages ("0" and "1") on to the bit lines for READ sensing. In 
order to guarantee cell stability during READ, I.sub.L and I.sub.G 
currents have to be controlled within a chosen operating range. This is 
accomplished by a READ reference level applied to the bit rail driving 
transistors (T.sub.1 and T.sub.2 of FIG. 12) from the UC line. The READ 
reference is generated by a bit up level clamp circuit (Bit UPCL, FIG. 7) 
which tracks fully with the selected cells, so that sufficient voltage 
potentials (V"0" and V"1") are always ensured across bit rail resistors 
RBL and RBR to define I.sub.L and I.sub.G currents. Generation of this 
READ reference level, and the operation of the bit up level clamp circuit, 
will be more fully explained in the following sections. 
WRITE Operation 
With voltage mode word selection technique, WRITE operation is performed in 
three sequential steps (FIGS. 13 and 14). 
1. The row lines are selected/deselected as previously described. 
2. After crossing of the selecting and deselecting drain lines (See FIG. 
14), WRITE operation is initiated. The RW clock switches the bit up level 
clamp circuit to generate a WRITE reference voltage on the UC line. This 
RW signal is also applied to a write control circuit, which depending on 
its data input, will drive either one of its two output lines PDL or PDR 
low. The lowered PDL or PDR line will then pull down node 1 or 2 of the 
bit select circuit respectively by the transistor diodes T5 or T6, so that 
when the bit rail is selected, only one side of the bit lines will be 
driven high to provide WRITE current into the cell. The other side will 
stay at down level in order to shut off the bit line current that normally 
flows into this side of the cell. The shutting off of the gate current 
that normally flows into the cell before WRITING is essential for a 
successful write operation. With the presence of gate current during 
WRITE, the presently ON NPN transistor in the cell will remain ON and will 
not be able to be overcome by the write current I.sub.W. 
3. After the PDL or PDR line is lowered, the bit select circuit is 
selected. The side of the bit line to be written a "1" is raised high by 
the bit rail driving transistors T1-T3 or T2-T4. Large transient write 
current is injected into the cell through T3-RBL or T4-RBR until the 
desired cell state is reached. After the cell has been written, the bit 
line voltage of the "1" side will rise up to its normal "1" level. This 
reduces the potential difference across the conducting bit rail resistor 
RBL or RBR, hence the transient transistor T3 or T4 is shut off. The bit 
rail resistor RBL or RBR will then supply a small DC WRITE current 
(I.sub.W) from T1 or T2 to reinforce the state of the newly written cell. 
The magnitude of the DC WRITE current I.sub.W is controlled by a WRITE 
reference level applied to the bit rail driving transistor T1 or T2 
through the U.sub.C line. This WRITE current can readily be adjusted by 
changing the bit up level clamp's WRITE reference level. 
The above write scheme is denoted "Differential Mode Write", since one side 
of the bit line is raised high while the other side is being held low 
during write time. 
The key advantage of this write scheme is that since the drain line is 
selected to a fixed voltage a V.sub.CE above V.sub.N, when write current 
is injected into the cell, the level of this line will not move up but 
remain stable. The chasing effect with the deselecting cells as exists in 
"current mode" word selection scheme used by prior art designs is hence 
eliminated. The RW clock can now come in sooner (as soon as the selecting 
and deselecting drain lines cross over) without waiting for the 
deselecting cells to get out of the way. This minimizes address set up 
time required prior to write. Due to faster word selection and shorter 
address set up time, write performance is therefore greatly improved. 
Furthermore, since the selected drain line is solidly held to a voltage 
level, and the deselected one is actively pulled up quickly to its 
unselected level, no "write through" (i.e., writing into the deselecting 
as well as the standby cells) problems exist. 
As is submitted to be evident from the above description the use of the 
voltage mode word selection technique, in accordance with invention, 
particularly in CTS RAMs, provides the following benefit and advantages: 
(1) Enables very high speed word select and 
deselect, hence faster "READ" performance. 
(2) Provides large row lines drive capability, 
hence very desirable for high density applications. 
(3) Stabilizes the selected drain line level, hence eliminates possible 
data retention and WRITE through problems. 
(4) Enables faster "WRITE" performance. 
Bit up level clamp circuit 
The proper operation of a voltage mode word selection scheme in a CTS RAM 
requires a bit up level clamp circuit to define the selected cells' 
operating levels. This is particularly important for the READ operation. A 
read reference voltage is generated by the bit up level clamp to track 
with the selected cells in temperature, power supply (V.sub.N) and device 
(V.sub.BE and V.sub.FSBD) variations, so that proper read currents 
(I.sub.G and I.sub.L) are always guaranteed under all conditions to ensure 
cell stability. The bit up level clamp circuit (FIG. 7) represented in 
FIGS. 3 and 3A by the block labelled "BIT UPCL" will now be explained with 
particular reference to FIGS. 8, 12 and 13. 
(1) READ REFERENCE 
Referring to FIG. 12, the voltage level required at the emitter of the 
clamping diode T5 in READ mode can be determined by summing up the 
potential rises/falls from V.sub.N in the word decoder. 
EQU Voltage@T.sub.5 =V.sub.N +V.sub.BE (TL)-V.sub.F (S2)+V.sub.BE (TR)+V.sub.F 
(SL)+V"1"+V.sub.BE (T1)-V.sub.BE (T5) 
Cancelling the V.sub.BE rises/falls and V.sub.F rises/falls in the above 
expression, a simplified equation defining the READ reference voltage is 
obtained: 
EQU Voltage@T.sub.5 =V.sub.N +2V.sub.BE +V"1" (1) 
For a READ operation, the R/W control input of the bit up level clamp 
circuit (FIG. 7) is high. Transistor T1 is ON and T2 is OFF, so that node 
3 is up to turn ON T3, T4 and T5. The output line UC is clamped down by T3 
to generate a READ reference voltage defined by the equation below. 
##EQU1## 
Equating expressions (1) and (2), we have: 
##EQU2## 
V"1" is the voltage across the "1" side of the bit rail resistor. It is 
this voltage potential across RBL that defines the gate current I.sub.G to 
maintain cell stability during READ. The read currents I.sub.G and I.sub.L 
are related by the following expressions: 
##EQU3## 
As seen from equation (3), since V"1" is defined by the voltage difference 
between a V.sub.BE (forward mode Base-Emitter voltage of an NPN 
transistor) and V.sub.F (forward conduction voltage of a Schottky diode), 
it is therefore independent of power supply (V.sub.P and V.sub.N) 
variations. Furthermore, temperature effects on the devices are also 
equally cancelled out. 
(2) WRITE REFERENCE 
In a WRITE mode, the R/W input is low. Transistor T1 is OFF and T2 is ON. 
Node 1 is high to pull up T6 while node 3 is down to shut OFF T3. The 
WRITE reference level at the UC line is given by: 
EQU V.sub.UC (WRITE)=V.sub.P -V.sub.BE (T6) (4) 
This WRITE reference voltage is applied to the bit rail driving transistors 
(T.sub.1 and T.sub.2, FIG. 13) to define the write current I.sub.W. 
Read Sensing Circuitry 
The operation of circuitry represented in FIG. 3 by the block labelled 
"sensing circuitry" will now be explained with particular reference to 
FIGS. 10 and 11. 
FIG. 3A illustrates the sensing scheme employed for the RAM shown in FIG. 
2. The 64 bit columns of this RAM is divided into four data groups of 16 
bits. Each data group contains a sense amplifier (FIG. 10) for READ 
sensing. The state of the sense amplifier is determined by the selected 
cell within its data group. Data read by the sense amplifier is sent off 
chip through an off chip driver (OCD) circuit. 
FIG. 11 illustrates the sense amplifier arrangement for a data group. 
Within a data group, each bit column has a pair of sensing transistors (TL 
and TR) attached to its bit lines for voltage sensing. When a cell is 
selected for READ, its row lines (WL and DL) are pulled down by its 
corresponding word decoder, and its bit lines (BL and BR) are raised up by 
its bit select circuit. Since there are 16 bit columns per data group, bit 
selection is always 1 out of 16. Of the thirty-two bit lines, only two are 
up at any one time. The higher of these two selected bit lines turns on 
the corresponding sensing transistor in the sense amplifier circuit. 
Sense Amplifier Circuit Operation 
FIG. 10 illustrates a high speed sense amplifier circuit designed for the 
above sensing scheme. The circuit uses current steering technique to 
enable very fast switching performance. Its sensing speed is independent 
of the number of bit columns in the data group. 
Referring to FIG. 10, the thrity-two sensing transistors T11 to TL16 and 
TR1 to TR16 form a big current switch input for the sense amplifier. The 
bases of these transistors are connected to the sixteen bit columns in the 
data group. Transistors T1 and T2 are emitter followers providing 
dual-phase outputs to drive the off chip driver. Transistors T3 and T4 are 
set to be ON all the time to define a fixed voltage at nodes A and B, so 
that switching of these two devices is done in current mode. 
At any time, either bit-left or bit-right of a selected bit column is up at 
a high voltage level. The higher voltage bit line turns on its 
corresponding sensing transistor. The sense current I.sub.S from the 
current source T5 is then steered by the ON sensing transistor through 
either T3 or T4, pulling node 1 or 2 down accordingly. 
Since voltage levels at node A and B will never be switched but remain 
fixed, any capacitance at these nodes, therefore will have no effect on 
the switching time. In fact, the circuit's delay will stay constant, 
disregarding the number of sensing transistors attached to its input 
stage. Furthermore, transistors T1, T2 and T3, T4 are active all the time; 
hence, their switching delay is kept to a minimum. 
The features of the sense amplifier circuit in FIG. 10 are summarized as 
follows: 
1. The sensing transistors are configurated as a bit current switch, with 
their bases connected to bit lines within the data group. This forms the 
input stage of the sense amplifier. 
2. The switching of the circuit is done in current mode, i.e., input 
voltages at A and B are fixed, and switching is performed by steering 
sense current I.sub.S through T3 or T4. This mode of operation enables 
very large fan-in capability, as well as high circuit speed independent of 
input loadings. 
3. All switching devices (T1, T2 and T3, T4) are kept active at all times 
to minimize circuit delay. 
It is to be appreciated, that for convenience of explanation and 
understanding, in the foregoing description of applicants' invention only 
a limited number of memory cells, word lines etc. were shown and 
described. Persons skilled in the art readily recognize that the size of 
the Array depicted in the drawing and described in the specification is 
not to be construed as a limitation on applicants' invention. 
While this invention has been particularly described with reference to the 
preferred embodiments thereof, it will be understood by those skilled in 
the art that the foregoing and other changes in from and details may be 
made therein without departing from the spirit and scope of the invention.