Method of manufacturing non-volatile memory device

A method for manufacturing a non-volatile memory includes depositing a first conductive film and a protective film on a substrate including a logic area and a cell area, patterning the protective film, depositing a hard mask layer on the first conductive film and the patterned protective film to pattern the hard mask layer, using the patterned hard mask layer to form a logic gate on the logic area, exposing a surface of the first conductive film in the cell area and forming a control gate on the cell area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 USC §119(a) of Korean Patent Application No. 10-2014-0017762 filed on Feb. 17, 2014, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to a method for manufacturing a non-volatile memory device forming a control gate and a logic gate in the non-volatile memory device.

2. Description of Related Art

A conventional method for protecting elevated poly-silicon structures during etching processes is a technology forming a protective mask layer by protecting the corresponding poly-silicon structure. The corresponding protective mask layer may use a silicon dioxide, an amorphous carbon or a photo resist.

However, in such a prior art, a control gate is located on an upper portion of a floating gate so that the control gate is easily damaged in an etching process for generating a logic gate. Also, a cell area is protected by a single protective mask layer in a logic gate forming process not to effectively protect the control gate and the floating gate.

SUMMARY

In one general aspect, there is provided a method of manufacturing the non-volatile memory device forming a control gate and a logic gate having a step (differential height/thickness) by a hard mask and a photo resist.

In another general aspect, there is provided a method of manufacturing the non-volatile memory device forming the control gate after forming the logic gate.

In another general aspect, there is provided a method of manufacturing the non-volatile memory device that the control gate is located beside the floating gate.

In another general aspect, there is provided a method of manufacturing a non-volatile memory device includes providing a substrate comprising a logic area and a cell area, forming a floating gate on the cell area, depositing a first conductive film and a protective film on the substrate, patterning the protective film, depositing a hard mask layer on the first conductive film and the patterned protective film, patterning the hard mask layer, forming a logic gate on the logic area using the patterned hard mask layer, exposing a surface of the first conductive film in the cell area, and forming a control gate on the cell area.

The patterning of the protective film may include forming a first mask pattern on an upper portion of the floating gate, and removing the protective film exposed by the first mask pattern, the first mask pattern corresponding to an etching mask.

The patterning of the hard mask layer may include forming a second mask pattern for etching the hard mask layer, patterning the hard mask layer by the second mask pattern, the second mask pattern corresponding to the etching mask, removing the first mask pattern, and forming a third mask pattern on an upper portion of the floating gate.

The exposing of the surface of the first conductive film in the cell area may include forming a fourth mask pattern exposing the hard mask layer in the upper portion of the floating gate, and sequentially etching the hard mask layer and the protective layer of the upper portion of the floating gate.

A height of the control gate may be greater than that of the logic gate.

The control gate may be located beside the floating gate.

The protective film may be of silicon oxide.

A thickness of the protective film may be greater than or equal to about 1000 Å and less than or equal to about 2000 Å.

The hard mask layer may include silicon oxide and silicon oxynitride (SiON).

A step between the cell area and the logic area may be at least about 500 nm.

The first conductive film may be deposited before the protective film.

In another general aspect, there is provided a method of manufacturing a non-volatile memory device, including forming a floating gate on a semiconductor substrate, depositing a gate insulator, a first conductive film and a protective film on the floating gate, patterning the protective film, depositing a hard mask layer on the patterned protective film, removing the hard mask layer and the patterned protective film to expose a surface of the first conductive film, etching back the first conductive film, and forming a control gate beside the floating gate.

The removing of the hard mask layer and the patterned protective film may include forming a third mask pattern to expose the hard mask layer, and wet etching the hard mask layer and the patterned protective film.

The control gate may be higher than the logic gate.

The protective film may be silicon oxide.

The hard mask layer may be silicon oxide and silicon oxynitride (SiON).

The gate insulator may be deposited before the first conductive film, and the first conductive film may be deposited before the protective film.

DETAILED DESCRIPTION

While terms such as “first” and “second,” etc., may be used to describe various components, such components must not be understood as being limited to the above terms. The above terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of the present disclosure, and likewise a second component may be referred to as a first component.

It will be understood that when an element is referred to as being “connected to” another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly connected to” another element, no intervening elements are present. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising,” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. Meanwhile, other expressions describing relationships between components such as “˜between”, “immediately˜between” or “adjacent to˜” and “directly adjacent to˜” may be construed similarly.

FIG. 1is a diagram illustrating an example of a non-volatile memory device. Referring toFIG. 1, a non-volatile memory device100includes a substrate110, an insulator120, a logic gate130, a floating gate140, a control gate150, and a dielectric layer170.

The substrate110may divide into a logic area111and a cell area112. The logic area111may include the logic gate130and the cell area112may include the floating gate140and the control gate150.

The insulator120is an isolation area corresponding to a deactivation area in an active area.

The logic gate130is located on an upper portion of the logic area111and is formed by material, such as, for example, poly-silicon.

The floating gate140is formed on an upper portion of the cell area112and is enclosed by the control gate150. In one example, the floating gate140may be located below the control gate150.

The control gate150is formed on the upper portion of the cell area112and encloses the floating gate140. The control gate150may have a height that is different from a height of the logic gate130. The control gate150may be formed higher than the logic gate130. When a step between the control gate150and the logic gate130exists, a thickness of a photo resist being applied to a corresponding step may be different and the upper portion of the floating gate140may be damaged because of difference of the corresponding thickness in an etching process for forming the logic gate130.

Therefore, a separate process is required in order to prevent the damage of the floating gate140in the etching process. A protecting procedure of the floating gate140will be described below.

The dielectric layer170may be formed of a high dielectric oxide. When the high dielectric oxide is used, a capacitance and a coupling efficiency may be increased.

FIG. 2throughFIG. 9are diagrams illustrating examples of a manufacturing process of a non-volatile memory device by using a protective film.

InFIG. 2, the substrate110is divided into the logic area111and the cell area112. A tunneling gate insulator formed with at least one or a stack of a silicon oxide, a silicon nitride (SiN) and a silicon oxynitride (SiON) is deposited on the semiconductor substrate.

A conductive film is deposited on the tunneling gate insulator (not shown). The conductive film may be formed with a single poly-silicon or a stacked metal poly-silicon. A mask pattern is formed using the photo resist (PR) (not shown) to form the floating gate140(not shown). The mask pattern corresponding to an etching mask etches the conductive film to form the floating gate140on the tunneling gate insulator (not shown). The tunneling gate insulator and the floating gate140are formed in the cell area, and the tunneling gate insulator and the floating gate140formed in the logic area are removed so that the semiconductor substrate is exposed.

The gate insulator207used for the control gate is deposited on the semiconductor substrate in the cell area. The gate insulator207used for the logic gate130is formed on the semiconductor substrate in the logic area. The gate insulator207may be formed with at least one or the stack of the silicon oxide, the silicon nitride (SiN) and the silicon oxynitride (SiON). In another example, a High-K insulator having a high dielectric constant value may be used as the gate insulator207. The conductive film210is deposited on the gate insulator207. The conductive film210may be used for the control gate150and may be formed with the single poly-silicon or the stacked metal poly-silicon. The upper portion and a side portion of the floating gate140are enclosed by the conductive film210forming the control gate150.

The protective film211is deposited on the conductive film210. The non-exhaustive examples described herein use the silicon oxide for the protective film211, however, the protective film211may be formed with at least one or the stack of the silicon oxide, the silicon nitride (SiN) and the silicon oxynitride (SiON). The protective film211uses a TEOS (Tetra Ethyl Ortho Silicate) material and is deposited by a LPCVD (Low Pressure Chemical Vapor Deposition) procedure. The protective film211is stacked on an upper portion of the logic area111and the cell area112. The protective film211is formed on the conductive film210to protect the conductive film210in the etching processes.

The protective film211protects the upper portion of the floating gate140of the cell area112in the etching process and is removed at a final process.

InFIG. 3, a first photo resist220ais formed on the upper portion of the floating gate140in the cell area112. The conductive film210and the protective film211are formed on the upper portion of the floating gate140and the conductive film210and the protective film211are used for forming the control gate150.

InFIG. 4, a first etching process is shown. InFIG. 4, the protective film211of the upper portion of the cell area112is protected by the first photo resist220a. The protective film211of the upper portion of the logic area111is removed by the etching process. The protective film211of the upper portion of the floating gate in the cell area112remains after the first etching process and the protective film211may function to protect the control gate150in a later etching process for forming the logic gate130.

InFIG. 5, the second photo resist220bis formed on a part of the cell area112and the logic area111. The second photo resist220bfunctions to protect a part of the control gate150and the logic gate130of the logic area111to form the logic gate130. The logic gate130is formed in a lower area that is protected by the second photo resist220bin the logic area111.

When a step between a conductive film210of the logic area111and a conductive film210stacked on the floating gate140exists in the cell area112, the second photo resist220bis affected by the corresponding step. In a photo resist forming process, a thickness of the second photo resist220bof the upper portion of the logic gate130may be thicker than that of the upper portion of the floating gate140.

InFIG. 6, a second etching process is shown. The logic gate130is formed on the upper portion of the logic area111in the second etching progress. The protective film211of the upper portion of the conductive film210in the cell area113is partially removed by the second etching process. That is, a part of the protective film211ais removed by the second etching process as described inFIG. 6.

As described above, a thickness difference of the second photo resist220bmay damage the conductive film211of the upper portion of the floating gate140while each of the etching processes is in progress. However, the conductive film210may be protected by the protective film211stacked thereon to prevent the damage of the conductive film210of the upper portion of the floating gate140.

InFIG. 7, a third photo resist220cis formed on a part of the logic area111and the cell area113. The third photo resist220cmay be formed on the logic area111to protect the logic gate130and may determine a shape of the control gate150.

InFIG. 8, a third etching process is shown. The third etching process corresponds to a wet etching and the rest of the protective film211aof the upper portion of the cell area113is completely removed by the third etching process.

InFIG. 9, a fourth etching process is shown using the third photo resist220cformed by the above process. During the fourth etching a part of the conductive film210of the upper portion of the floating gate140is removed by etching back as shown inFIG. 9. The conductive film210enclosing a side of the floating gate remains. Therefore, a shape of the control gate150may be determined by a shape of the third photo resist220c.

FIG. 10throughFIG. 20are diagrams illustrating examples of a manufacturing process of a non-volatile memory device using a protective film and a hard mask.

FIG. 10illustrates a procedure of preparing a semiconductor substrate including a logic area and a cell area, forming a floating gate on the cell area, depositing a first conductive film on a front surface of the substrate, and depositing a protective film on the first conductive film.

The semiconductor substrate includes the logic area111and the cell area112. A tunneling gate insulator (not shown) formed with at least one or a stack of a silicon oxide, a silicon nitride (SiN), and a silicon oxynitride (SiON) is deposited on the semiconductor substrate. The conductive film is deposited on the tunneling gate insulator (not shown). The conductive film may be formed with the single poly-silicon or the stacked metal poly-silicon. The photo resist (PR) (not shown) is used to form the floating gate140for the mask pattern. The conductive film is etched by the mask pattern corresponding to the etching mask to form the floating gate140on the tunneling gate insulator. The tunneling gate insulator and the floating gate140are formed in the cell area112, and the tunneling gate insulator and the floating gate140formed in the logic area are removed so that the semiconductor substrate is exposed.

A gate insulator207used for the control gate150is deposited on the semiconductor substrate in the cell area. The gate insulator207used for the logic gate130is formed on the semiconductor substrate310in the logic area. The gate insulator207may be formed with at least one or a stack of the silicon oxide, the silicon nitride (SiN) and the silicon oxynitride (SiON). In another example, the High-K insulator having a high dielectric constant value may be used as the gate insulator207.

A conductive film310is deposited on the gate insulator207. The conductive film310may be used for the control gate150and may be formed with the single poly-silicon or the stacked metal poly-silicon. The upper and a side of the floating gate140are enclosed by the conductive film310forming the control gate150.

The protective film311is deposited on the conductive film310. The protective film311is formed with at least one or a stack of the silicon oxide, the silicon nitride (SiN) and the silicon oxynitride (SiON). The example described herein uses the silicon oxynitride (SiON) for the protective film311, however, the present disclosure is not limited to SiON and it is understood that those skilled in the art may include other types of protective film. The protective film311uses the TEOS material and is deposited by the LPCVD procedure. The protective film311is stacked on the upper portion of the logic area111and the cell area112. The protective film311is formed on the conductive film310to protect the conductive film310used for the control gate150in the etching processes. The protective film311protects the upper portion of the floating gate140of the cell area112in the etching process and is removed in the final process.

FIG. 11andFIG. 12illustrate procedures of patterning the protective film311. Patterning the protective film311includes forming a first mask pattern on the upper portion of the floating gate140(FIG. 11) and removing the exposed protective film311by using the first mask pattern as the etching mask (FIG. 12). Between the floating gate140and the first mask pattern, the gate insulator207, the conductive film310used for the control gate150and the protective film311are formed, so the first mask pattern320amay be in contact with the protective film311. As described inFIG. 12, the rest of the exposed protective film311except for a periphery of the floating gate140is removed by the etching process.

InFIG. 13, a hard mask layer330is deposited on the upper portion of the logic area111and the cell area112. The hard mask layer330is formed with at least one or a stack of the silicon oxide, the silicon nitride (SiN) and the silicon oxynitride (SiON). The present example uses the silicon oxide (SiO2) depositing the silicon oxynitride (SiON) or the silicon oxide (SiO2) depositing the silicon nitride (SiN), however, the present disclosure is not so limited and it is understood that those skilled in the art may include other types of hard mask layers. When the etching process for forming the logic gate130is in progress, the hard mask layer330prevents damage of the conductive film310on the upper portion of the floating gate140.

As described inFIG. 13, the gate insulator207, the protective film310used for the control gate150, the protective film311and the hard mask layer330are formed in the cell area112so a height of the cell area112is higher than a height of the logic area111. This is because the floating gate structure is already formed in the cell area112before the conductive film310is formed. A height of the floating gate structure is more than or equal to at least about 500 nm, therefore, a step (differential height/ thickness) between the cell area112and the logic area111after the conductive film is formed, is also more than or equal to at least about 500 nm.

FIG. 14throughFIG. 16illustrate examples of patterning the hard mask layer330. Patterning the hard mask layer330includes forming a second mask pattern (320a,320b) used for etching the hard mask layer330(FIG. 14), patterning the hard mask layer by the second mask pattern as the etching mask and removing the second mask pattern (320a,320b) (FIG. 15) and forming a third mask pattern (320c) on the upper portion of the floating gate140(FIG. 16). The first and third mask patterns use a same mask pattern so that the first and third mask patterns function to protect the upper portion of the floating gate140.

FIG. 14illustrates an example of forming the second mask pattern (320a,320b) used for etching the hard mask layer330. The second photo resist320aand320bcorresponding to the second mask pattern is formed on a part of the cell area112and the logic area111. The second photo resists320aand320bis deposited to form the hard mask pattern. There is a step (differential height/thickness) between the conductive film310of the logic area111and the conductive film310stacked on the floating gate140of the cell area112. This is because the gate insulator207, the conductive film310used for the control gate, the protective film311and the hard mask layer330are formed in the cell area112as described above. A thickness difference of the second photo resists320aand320bis affected by the corresponding step (differential height/ thickness). A second photo resist320astacked on an area for forming the logic gate130may be thicker than a thickness of the second photo resist320bstacked on the upper portion of the floating gate140.

FIG. 15illustrates an example of patterning the hard mask layer330by the second mask pattern corresponding to the etching mask and removing the second mask pattern (320a,320b).FIG. 15illustrates an example of the second etching process for forming the logic gate130. InFIG. 15, a part of the hard mask layer330aof the upper portion of the floating gate140is removed by the second etching process so that the protective film311may be exposed. InFIG. 15unlikeFIG. 14, in spite of a thickness difference between the second photo resists320aand320b, the conductive film310of the upper portion of the floating gate140is not damaged by the second etching process. This is because the conductive film310of the upper portion of the floating gate140is protected by the hard mask layer330and the protective film311. The hard mask layer330remains in an area for forming the logic gate130after the second etching process. The rest of the hard mask layer330may function as a mask for forming the logic gate130in the following etching process.

FIG. 16illustrates an example of forming a third mask pattern (320c) on the upper portion of the floating gate140. A third photo resist320crepresenting the third mask pattern is formed on the cell area112to protect the cell area112from the third etching process.

FIG. 17illustrates an example of the third etching process. The logic gate130is formed by etching the conductive film310through the patterned hard mask layer330corresponding to the etching mask. A part of the conductive film310of the logic area111is removed by the third etching process. The logic gate130is formed by the conductive film310being protected by the hard mask layer330and the rest of the conductive layer that is not protected by the hard mask layer330is removed.

FIG. 18andFIG. 19are diagrams illustrating an example of exposing a surface of the conductive film310used for the control gate150of the cell area112.FIG. 18illustrates an example of forming a fourth mask pattern (320d) exposing the hard mask layer330of the upper portion of the floating gate140andFIG. 19illustrates an example of substantially etching the hard mask layer330and the protective film311on the upper portion of the floating gate140.

InFIG. 18, a fourth photo resist320dcorresponding to a fourth mask pattern is formed on a part of the logic area111and the cell area112. The fourth photo resist320dmay protect the logic gate130formed on the logic area111and may open the control gate150being formed on the cell area112.

InFIG. 19illustrates an example of a fourth etching process. InFIG. 19, the hard mask layer330aand the protective film311partially remaining on the upper portion of the floating gate140are removed by the fourth etching process. The fourth etching process is in progress by wet etching.

FIG. 20is illustrates an example of forming the control gate150. An example of the fifth etching process is shown inFIG. 20. A part of the conductive film310of the upper portion of the cell area113is removed by the fifth etching process. The control gate150is formed by the conductive film310remaining on the upper portion of the cell area113after etching. The fifth etching process is in progress by etching back process. The control gate150is formed beside the floating gate140being spacer shaped by the etching back process. An insulator is formed between the floating gate140and the control gate150. A conductive film310used for the floating gate140may be same as the conductive film used for the control gate150.

An electrode of the logic gate130is formed on the gate insulator207in the logic area111. In the cell area112, the floating gate140is formed on the tunneling gate insulator, the control gate150is formed beside the floating gate140and the insulator is formed between the floating gate140and the control gate150. The conductive film310used for the floating gate140may be same with the conductive film310used to the control gate150.

DESCRIPTION OF SYMBOLS