Semiconductor device package and methods of manufacture

A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

BACKGROUND

Integrated circuits are formed on semiconductor wafers, which are then sawed into semiconductor chips. The semiconductor chips may be bonded onto package substrates. During the bonding process, the solder bumps between the semiconductor chips and the package substrates are reflowed. Conventional reflow methods include convection-type reflow or thermal compressive reflow. The convection-type reflow has relatively high throughput since multiple package substrates and the overlying dies may be bonded through the reflow at the same time. However, the convection-type reflow requires a long period of time to heat solder bumps. The resulting high thermal budget may cause significant warpage in the dies, and may possibly cause delamination between low-k dielectric layers in the dies.

The thermal compressive reflow requires a lower thermal budget than the convection-type reflow. In conventional thermal compressive bonding processes, a die is stacked on a package substrate, with the solder bumps on a surface of the die, being pressed against the solder bumps on the surface of the package substrate. After melting the solder bumps, solder bumps cool down to solidify.

DETAILED DESCRIPTION

Various embodiments provide methods applied to, but not limited to, the formation of a device package comprising one or more semiconductor chips bonded to an interposer and a package substrate bonded to a side of the interposer opposing the one or more semiconductor chips. In some embodiments, the device package may be referred to a chip-on-wafer-on-substrate (CoWoS). The interposer may be bonded to the one or more semiconductor chips using solder bumps on the semiconductor chip(s) and/or the interposer that are reflowed using thermal compression bonding (TCB). The thermal compression bonding (TCB) apparatus comprises a TCB bonding head that provides a vacuum force to hold a first workpiece (e.g., a semiconductor chip) and a vacuum chuck table that provides a vacuum force to hold a second workpiece (e.g. a package substrate). During the bonding of the interposer to the semiconductor chip, a heating process is performed to reflow the solder bumps in which the TCB bonding head and the vacuum chuck table provide heat to reflow the solder bumps. During the heating process, the height of the solder bumps can be maintained to allow for the formation of solder bumps with a column shape, or the height of the solder bumps can be increased to allow for the formation of solder bumps with an hourglass shape. Advantageous features of one or more embodiments disclosed herein may include an improvement in the device package coplanarity (COP), and the prevention of deformation or warpage of the interposer and the package substrate due to the presence of the vacuum forces during the heating process. This improvement in coplanarity and reduced warpage allows for an improved connection between the package substrate (e.g., a printed circuit board) and the interposer when the package substrate and the interposer are bonded together.

Embodiments will be described with respect to a specific context, namely a Die-Interposer-Substrate stacked package using Chip-on-Wafer-on-Substrate (CoWoS) processing. However, other embodiments may also be applied to other packages. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Like reference numbers and characters in the figures below refer to like components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1,2,3,4,5,6A,6B,6C,7,8,9,10and11illustrate cross-sectional views of intermediary stages of manufacturing a semiconductor device package1000in accordance with some embodiments.

FIG.1illustrates one or more dies68. In some embodiments, the one or more dies68may be initially formed as part of a wafer, which is subsequently singulated. In an embodiment, the substrate60may include a bulk semiconductor substrate, semiconductor-on-insulator (SOI) substrate, multi-layered semiconductor substrate, or the like. The semiconductor material of the substrate60may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The substrate60may be doped or undoped. Devices, such as transistors, capacitors, resistors, diodes, and the like, may be formed in and/or on an active surface62.

An interconnect structure64comprising one or more dielectric layer(s) and respective metallization pattern(s) is formed on the active surface62. The metallization pattern(s) in the dielectric layer(s) may route electrical signals between the devices, such as by using vias and/or traces, and may also contain various electrical devices, such as capacitors, resistors, inductors, or the like. The various devices and metallization patterns may be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like.

More particularly, an inter-metallization dielectric (IMD) layer may be formed in the interconnect structure64. The IMD layer may be formed, for example, of a low-K dielectric material, such as undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or the like. A metallization pattern may be formed in the IMD layer, for example, by using photolithography techniques to deposit and pattern a photoresist material on the IMD layer to expose portions of the IMD layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in the IMD layer corresponding to the exposed portions of the IMD layer. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, the like, or a combination thereof, deposited by atomic layer deposition (ALD), or the like. The conductive material of the metallization patterns may comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, physical vapor deposition (PVD), or the like. Any excessive diffusion barrier layer and/or conductive material on the IMD layer may be removed, such as by using a chemical mechanical polish (CMP).

Additionally, die connectors66, such as conductive pillars, conductive bumps, or the like, are formed in and/or on the interconnect structure64to provide an external electrical connection to the circuitry and devices within the interconnect structure64and on the active surface62. In the illustrated embodiment, the die connectors66are formed in openings of the dielectric layers of the interconnect structure64. Each die connector66extends through an opening of a dielectric layer of the interconnect structure64to contact a conductive pad of the interconnect structure64. A photoresist (not illustrated) may be formed by spin coating or the like and may be exposed to light for patterning. The patterning forms openings through the photoresist to expose the conductive pads of the interconnect structure64. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the conductive pads to form the die connectors66. The die connectors66may comprise a metal such as copper, aluminum, gold, nickel, palladium, the like, or a combination thereof and may be formed by sputtering, printing, electro plating, electroless plating, CVD, or the like. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. The die connectors66may be solder free and have substantially vertical sidewalls. In some embodiments, the die connectors66protrude from the interconnect structure64to form pillar structures to be utilized when bonding the dies68to other structures. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes. Other circuitry may be used as appropriate for a given application.

InFIG.2, the substrate60including the interconnect structure64is singulated into individual dies68. Typically, each of the dies68may contain the same circuitry, such as devices and metallization patterns, although the dies may have different circuitries in some embodiments. The singulation may include sawing, dicing, or the like.

The dies68may include one or more logic dies (e.g., central processing unit, graphics processing unit, system-on-a-chip, field-programmable gate array (FPGA), microcontroller, or the like), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, or the like), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. Also, in some embodiments, the dies68may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the dies68may be the same size (e.g., same heights and/or surface areas). In an embodiment, each of the dies68may have a die area equal to or larger than 1200 mm2. In an embodiment, each of the dies68may have a thickness that is equal to or larger than 400 μm.

FIG.3illustrates a package substrate40, which may be initially formed as part of a wafer, for example. A substrate70of the package substrate40may comprise a bulk semiconductor substrate, SOI substrate, multi-layered semiconductor substrate, or the like. The semiconductor material of the substrate70may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The substrate70may be doped or undoped. Devices, such as transistors, capacitors, resistors, diodes, and the like, may be formed in and/or on a first surface72, which may also be referred to as an active surface, of the substrate70. In other embodiments, the package substrate40may be free of any active devices, and the package substrate40may be referred to as an interposer in such embodiments. In an embodiment, an area of a major surface of the package substrate40may be equal to or larger than 3600 mm2.

Through-vias (sometimes referred to as Through-Substrate Vias (TSVs))24may be formed to extend from the first surface72into the substrate70. TVs24are also sometimes referred as through-silicon vias when formed in a silicon substrate. Although not shown inFIG.3, each of TVs24may be encircled by an isolation liner, which is formed of a dielectric material such as silicon oxide, silicon nitride, or the like. The isolation liner isolates the respective TVs24from substrate70.

Redistribution structure76is formed over the first surface72of the substrate70, and is used to electrically connect to TVs24. Redistribution structure76is also used to electrically connect the integrated circuit devices (if any) to external devices. The redistribution structure76may include one or more dielectric layer(s) and respective metallization pattern(s) in the dielectric layer(s). The metallization patterns may comprise vias and/or traces to interconnect any devices and/or to an external device. The metallization patterns are sometimes referred to as redistribution lines (RDL). The dielectric layers may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layers may be deposited by any suitable method known in the art, such as spinning, CVD, PECVD, HDP-CVD, or the like. A metallization pattern may be formed in the dielectric layer, for example, by using photolithography techniques to deposit and pattern a photoresist material on the dielectric layer to expose portions of the dielectric layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in the dielectric layer corresponding to the exposed portions of the dielectric layer. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by ALD, or the like, and the conductive material may comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVD, a plating process, or the like. Any excessive diffusion barrier layer and/or conductive material on the dielectric layer may be removed, such as by using a CMP.

Electrical connectors77are formed at the top surface of the redistribution structure76on conductive pads. In some embodiments, the conductive pads include under bump metallurgies (UBMs). In the illustrated embodiment, the pads are formed in openings of the dielectric layers of the redistribution structure76. In another embodiment, the pads (UBMs) can extend through an opening of a dielectric layer of the redistribution structure76and also extend across the top surface of the redistribution structure76. As an example to form the conductive pads, a seed layer (not shown) is formed at least in the opening in the dielectric layer of the redistribution structure76. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pads. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the pads. In the embodiment, where the pads are formed differently, more photoresist and patterning steps may be utilized.

In an embodiment, the electrical connectors77are then formed on the conductive pads and may comprise solder balls and/or bumps, such as micro-bumps, controlled collapse chip connection (C4), electroless nickel immersion Gold (ENIG), electroless nickel electroless palladium immersion gold technique (ENEPIG) formed bumps, or the like. In an embodiment, the electrical connectors77are formed by initially forming a patterned layer of solder through suitable methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a patterned layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In an embodiment, the bump electrical connectors77may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof.

InFIG.4, the electrical connectors77of the package substrate40are coated with a flux78, such as a no-clean flux. The electrical connectors77may be dipped in the flux78or the flux78may be jetted onto the electrical connectors77in some embodiments.

FIG.5illustrates a thermal compression bonding (TCB) bonding head81and vacuum chuck table82of a thermal compression bonding (TCB) apparatus. The TCB bonding head81may comprise one or more vacuum channels used to create a first vacuum force83, so that TCB bonding head81may be used to pick and hold a first workpiece (e.g., the die68) as shown inFIG.5. The function, position and vacuum force83of the TCB bonding head81may be adjustable which allows for vertical movement of the TCB bonding head81. Likewise, the vacuum chuck table82may comprise one or more vacuum channels used to create a second vacuum force85, so that vacuum chuck table82may be used to hold a second workpiece (e.g., the package substrate40) as shown inFIG.5.

InFIG.6A, TCB bonding head81may be used to pick up the die68, and to place the die68on the package substrate40, such that the electrical connectors77and the die connectors66are in contact. After the placement of the die68on the package substrate40, TCB bonding head81remains contacting the die68, and may apply an upward force on the die68due to the vacuum force83. A position of the TCB bonding head81relative to the vacuum chuck table82may be maintained such that a height between a topmost surface of each die connector66and a bottommost surface of a corresponding electrical connector77that it is in contact with is equal to a first height H1. The TCB bonding head81is then heated and may provide heat to the die68in a heating process87, which by thermal conduction causes the reflow of the electrical connectors77and the bonding of the electrical connectors77to the die connectors66. In an embodiment, the TCB bonding head81includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process87may heat up the TCB bonding head81and the die68to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process87may be performed for a duration that is in a range from 0.1 s to 300 s. During the heating process87, and during the melting of the electrical connectors77, the height between the topmost surface of each die connector66and the bottommost surface of the corresponding electrical connector66is maintained at the first height H1by holding the TCB bonding head81at a fixed vertical position relative to the vacuum chuck table82. In an embodiment, the first height H1may be in a range from 5 μm to 60 μm. In an embodiment, the first height H1may be up to 100 μm.

FIG.6Billustrates a cross-sectional view of the device package1000after performing the reflow process and heating process87described above inFIG.6A.FIG.6Cshows an enlarged view of the region93shown inFIG.6B. The height between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77that it is in contact with is equal to the first height H1. Because the first height H1is maintained during the heating process87shown inFIG.6A, a column joint42is formed that has a uniform first width W1throughout the an entirety of the first height H1of the column joint42. For example, the die connector66may have a cylindrical shape that has a uniform width equal to the first width W1, and the reflowed electrical connector77may likewise have a cylindrical shape that has uniform width equal to the first width W1. Flux78is then removed (or cleaned) using a method that may comprise spraying solvent, applying de-ionized (DI) water, heating, and drying the device package1000, in accordance with some embodiments.

The electrical connectors77melt in the conventional reflow process without controlling the space between die and substrate, and are solidified thereafter. The space between die and substrate or space between two substrates in package(s) may change due to gravity and thermal expansion coefficient. The convectional reflow may cause deformation or warpage.

Advantages can be achieved as a result of the formation of the device package1000in which the package substrate40are bonded to the die68using the electrical connectors77on the package substrate40that are reflowed using thermal compression bonding (TCB). The thermal compression bonding (TCB) apparatus includes the TCB bonding head81that provides the vacuum force83to hold the die68and the vacuum chuck table82that provides the vacuum force85to hold the package substrate40. During the bonding of the package substrate40to the die68, the heating process87is performed to reflow the electrical connectors77in which the TCB bonding head81provides heat to reflow the electrical connectors77. During the heating process87, the first height H1between the topmost surfaces of the die connectors66and the bottommost surfaces of the electrical connectors77are maintained at a constant in order to allow for the formation of the column joint42. The advantages may include an improvement in the coplanarity (COP) of the device package1000and the prevention of deformation or warpage of the die68and the package substrate40due to the presence of the vacuum forces83and85during the heating process87. This improvement in coplanarity and reduced warpage further allows for an improved connection between the package substrate40and another component package44(e.g., a printed circuit board described below inFIG.8) when the package substrate40and the component package44are bonded together.

InFIG.7, an underfill material100is dispensed into the gap between the die68and the redistribution structure76. In some embodiments, the underfill material100may extend up along sidewall of the die68. The underfill material100may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like. The underfill material100may be formed by a capillary flow process after the die68is attached, or may be formed by a suitable deposition method before the die68is attached.

In a subsequent step, a planarization step such as a CMP step or a mechanical grinding step is performed to thin the substrate70of the package substrate40. In accordance with some embodiments of the present disclosure, the planarization process is performed until the through-vias24are exposed through a second surface172of the substrate70.

Redistribution structure102may then be formed over the second surface172of the substrate70, and is used to electrically connect through-vias24to a subsequently bonded component package44(described inFIG.8). The redistribution structure102may include one or more dielectric layer(s) and respective metallization pattern(s) in the dielectric layer(s). The metallization patterns may comprise vias and/or traces to interconnect the through-vias24to an external device. The metallization patterns are sometimes referred to as redistribution lines (RDL).

In accordance with some embodiments of the present disclosure, a dielectric layer25may be formed over the second surface172and may comprise a polymer such as PBO, polyimide, or the like. The formation method may include coating the dielectric layer25in a flowable form, and then curing the dielectric layer25. In accordance with some embodiments of the present disclosure, the dielectric layer25may be formed of an inorganic dielectric material such as silicon nitride, silicon oxide, or the like. The formation method may include Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), or other applicable deposition methods. Openings are then formed in the dielectric layer25, for example, through a photo lithography process that exposes the through-vias24through the openings.

Next, RDL104is formed, that may include vias formed in the openings of the dielectric layer25to contact through-vias24, and metal traces (metal lines) over the dielectric layer25. In accordance with some embodiments of the present disclosure, RDL104is formed in a plating process, which includes depositing a metal seed layer (not shown), forming and patterning a photo resist (not shown) over the metal seed layer, and plating a metallic material such as copper and/or aluminum over the metal seed layer. The metal seed layer and the plated metallic material may be formed of the same material or different materials. The patterned photo resist is then removed, followed by etching the portions of the metal seed layer previously covered by the patterned photo resist.

In an embodiment, one or more dielectric layers may be formed over the dielectric layer25. In an embodiment, one or more RDLs may be formed over and connecting to RDL104. The one or more dielectric layers may be formed using a material selected from the same or different group of candidate materials for forming the dielectric layer25, which may include PBO, polyimide, BCB, or other organic or inorganic materials. The material and the formation process of the one or more RDLs may be the same as the formation of RDL104, which includes forming a seed layer, forming a patterned mask, plating each of the one or more RDLs and then removing the patterned mask and undesirable portions of the seed layer.

FIG.7further illustrates the formation of electrical connectors106, such as conductive pillars, conductive bumps, or the like, that are formed in and/or on the redistribution structure102to provide an external electrical connection to the circuitry and devices within the redistribution structure76and on the first surface72through the TVs24. In an embodiment, the electrical connectors106are formed in openings of the dielectric layers of the redistribution structure102. Each electrical connector106extends through an opening of a topmost dielectric layer of the redistribution structure102to contact a conductive pad (e.g., RDL104of the redistribution structure102). The material and the formation process of the electrical connectors106may be the same as the formation of the die connectors66described previously inFIG.1. Accordingly, the process steps and applicable materials may not be repeated herein.

InFIGS.8through11, a component package44is attached to the package substrate40. The component package44may comprise a printed circuit board such as a laminate substrate formed as a stack of multiple thin layers (or laminates) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, or the like. However, any other suitable substrate, such as a silicon interposer, a silicon substrate, organic substrate, a ceramic substrate, or the like, may also be utilized. As illustrated inFIG.8, the component package44may comprise electrical connectors108that may include solder balls and/or bumps, such as controlled collapse chip connection (C4), electroless nickel immersion Gold (ENIG), electroless nickel electroless palladium immersion gold technique (ENEPIG) formed bumps, or the like. In an embodiment, the electrical connectors108are formed by initially forming a layer of solder through suitable methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In an embodiment, the bump electrical connectors108may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof.

InFIG.9, the electrical connectors108of the component package44are coated with a flux178, such as a no-clean flux. The electrical connectors108may be dipped in the flux178or the flux178may be jetted onto the electrical connectors108. In another embodiment, the flux178may also be applied to the electrical connectors108. TCB bonding head81may then be used to pick up the device package1000shown inFIG.7, and to place the device package1000on the component package44, such that the electrical connectors108and the electrical connectors106are in contact. The vacuum chuck table82may be used to hold the component package44. After the placement of the device package1000on the component package44, TCB bonding head81remains contacting the device package1000, and may apply an upward force on the device package1000due to the vacuum force83A position of the TCB bonding head81relative to the vacuum chuck table82may be maintained such that a height between a topmost surface of each electrical connector106and a bottommost surface of a corresponding electrical connector108that it is in contact with is equal to a second height H2. The TCB bonding head81is then heated and may provide heat to the device package1000in the heating process87, which by thermal conduction causes the reflow of the electrical connectors108and the bonding of the electrical connectors108to the electrical connectors106. In an embodiment, the vacuum chuck table82may also be heated and may provide heat to the component package44in a heating process89. In an embodiment, the vacuum chuck table82includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process89may heat up the vacuum chuck table82to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process89may be performed for a duration that is in a range from 0.1 s to 300 s. During the heating processes87and89and during the melting of the electrical connectors108, the height between the topmost surface of each electrical connector106and the bottommost surface of the corresponding electrical connector108is maintained at the second height H2by holding the TCB bonding head81at a fixed vertical position. In an embodiment, the second height H2may be in a range from 40 μm to 130 μm. In an embodiment, the second height H2is at least 10 μm.

FIG.10illustrates a cross-sectional view of the device package1000after performing the reflow process and heating process87and89described above inFIG.9.FIG.11shows an enlarged view of the region94shown inFIG.10. The height between the topmost surface of each electrical connector106and the bottommost surface of a corresponding electrical connector108that it is in contact with is equal to the second height H2. Because the second height H2is maintained during the heating process87and89shown inFIG.9, a column joint142is formed that has a uniform second width W2throughout the an entirety of the second height H2of the column joint142. For example, the electrical connector106may have a cylindrical shape that has a uniform width equal to the second width W2, and the reflowed electrical connector108may likewise have a cylindrical shape that has uniform width equal to second width W2. Flux178is then removed (or cleaned) using a method that may comprise spraying solvent, applying de-ionized (DI) water, heating, and drying the device package1000, in accordance with some embodiments.

An underfill material (not shown) can be dispensed between the component package44and the package substrate40. The underfill material may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like. In an alternate embodiment, the component package44is attached to the package substrate40in the manner described subsequently inFIGS.12E through12H. Accordingly, the process steps and applicable materials may not be repeated herein.

FIGS.12A,12B,12C and12Dillustrate cross-sectional views of intermediary stages of manufacturing a semiconductor device package2000, in accordance with some embodiments. The device package2000is another embodiment in which like reference numerals represent like components in the embodiment shown inFIGS.1through11, unless specified otherwise. Accordingly, the process steps and applicable materials may not be repeated herein. The initial steps of this embodiment are essentially the same as shown inFIGS.1through5.

InFIG.12A, TCB bonding head81may be used to pick up the die68, and to place the die68on the package substrate40, such that the electrical connectors77and the die connectors66are in contact. After the placement of the die68on the package substrate40, TCB bonding head81remains contacting the die68, and may apply an upward force on the die68due to the vacuum force83After the electrical connectors77and the die connectors66are brought into contact, a position of the TCB bonding head81relative to the vacuum chuck table82may be such that a height between a topmost surface of each die connector66and a bottommost surface of a corresponding electrical connector77that it is in contact with is equal to a third height H3. The TCB bonding head81is then heated and may provide heat to the die68in a heating process87, which by thermal conduction causes the reflow of the electrical connectors77and the bonding of the electrical connectors77to the die connectors66. In an embodiment, the TCB bonding head81includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process87may heat up the TCB bonding head81and the die68to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process87may be performed for a duration that is in a range from 0.1 s to 300 s. During the heating process87and during the melting of the electrical connectors77, the height between the topmost surface of each die connector66and the bottommost surface of the corresponding electrical connector66that it is in contact with is adjusted to be at a fourth height H4, as shown inFIG.12B. This may be performed by vertically adjusting the height of the TCB bonding head81relative to the vacuum chuck table82. In some embodiments, the fourth height H4may be larger than the third height H3. For example, a distance between the topmost surfaces of the die connectors66and the bottommost surfaces of the electrical connectors77may be increased. In an embodiment, the third height H3may be in a range from 5 μm to 60 μm and the fourth height H4may be in a range from 7 μm to 70 μm. In an embodiment, the third height H3may be up to 100 μm. In an embodiment, the fourth height H4may be up to 100 μm.

FIG.12Cillustrates a cross-sectional view of the device package2000after performing the reflow process and heating process87described above inFIGS.12A and12B.FIG.12Dshows an enlarged view of the region95shown inFIG.12C. The height between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77that it is in contact with is equal to the fourth height H4. Because the height between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77is adjusted (e.g., increased) from the third height H3to the fourth height H4during the heating process87shown inFIGS.12A and12B, an hourglass joint46is formed.

The hourglass joint46comprises the die connector66and the electrical connector77. The die connector66may have a column shape with a uniform third width W3. The electrical connector77may comprise an hourglass shape with a first portion of the electrical connector77having a fourth width W4, a second portion of the electrical connector77having a fifth width W5, and a third portion of the electrical connector77having a sixth width W6. The second portion of the electrical connector77may be between the first portion and the third portion of the electrical connector77. In some embodiments, the fifth width W5is smaller than the fourth width W4and the sixth width W6. In some embodiments, the third width W3, the fourth width W4, and the sixth width W6are equal. In some embodiments, the electrical connector77may comprise curved, concave sidewalls.

In an embodiment, the third portion of the electrical connector77may extend through a solder resist layer110on the redistribution structure76as shown inFIG.12D. The third portion of the electrical connector77in the solder resist layer110may have a substantially uniform width throughout, and the electrical connector77may decrease continuously in width in a direction toward a mid-point between the bottommost surface of the die connector66and a topmost surface of a solder resist110. Further, the curved, concave sidewalls of the electrical connector77may extend continuously from a topmost surface of the solder resist layer110to a bottommost surface of the die connector66. In an embodiment, the third width W3, the fourth width W4, and the sixth width W6are not equal (e.g., as shown inFIG.12I). In an embodiment, one of the third width W3, the fourth width W4, and the sixth width W6is not equal to the other two widths. In an embodiment, the electrical connector77may comprise sidewalls that are curved differently from each other (e.g., as shown inFIG.12J). In an embodiment, sidewalls of one or more of the die connector66, the first portion of the electrical connector77and the third portion of the electrical connector77may be curved or sloping (e.g., as shown inFIG.12K) In an embodiment where the third portion of the electrical connector77is curved or sloping, the third portion of the electrical connector77may extend through the solder resist layer110on the redistribution structure76. Flux78is then removed (or cleaned) using a method that may comprise spraying solvent, applying de-ionized (DI) water, heating, and drying the device package2000, in accordance with some embodiments. The next steps of this embodiment are similar to the ones described above inFIG.7. Accordingly, the process steps and applicable materials may not be repeated herein.

Advantages can be achieved as a result of the formation of the device package2000in which the package substrate40are be bonded to the die68using the electrical connectors77on the package substrate40that are reflowed using thermal compression bonding (TCB). The thermal compression bonding (TCB) apparatus includes the TCB bonding head81that provides the vacuum force83to hold the die68and the vacuum chuck table82that provides the vacuum force85to hold the package substrate40. During the bonding of the package substrate40to the die68, a heating process87is performed to reflow the electrical connectors77in which the TCB bonding head81provides heat to reflow the electrical connectors77. During the heating process87, the third height H3between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77that it is in contact with is adjusted and increased to the fourth height H4, in order to allow for the formation of the hourglass joint46. The advantages may include an improvement in the coplanarity (COP) of the device package2000, and the prevention of deformation or warpage of the die68and the package substrate40due to the presence of the vacuum forces83and85during the heating process87. This improvement in coplanarity and reduced warpage further allows for an improved connection between the package substrate40and another component package44(e.g., a printed circuit board described above inFIG.8) when the package substrate40and the component package44are bonded together.

InFIG.12E through12H, the component package44(described previously inFIG.8) is attached to the package substrate40. InFIG.12E, the electrical connectors108of the component package44are coated with a flux178, such as a no-clean flux. The electrical connectors108may be dipped in the flux178or the flux178may be jetted onto the electrical connectors108. In another embodiment, the flux178may also be applied to the electrical connectors108. TCB bonding head81may then be used to pick up the device package2000shown inFIG.12C, and to place the device package2000on the component package44, such that the electrical connectors108and the electrical connectors106are in contact. The vacuum chuck table82may be used to hold the component package44. After the placement of the device package2000on the component package44, TCB bonding head81remains contacting the device package2000, and may apply an upward force on the device package2000due to the vacuum force83. After the electrical connectors108and the electrical connectors106are brought into contact, a position of the TCB bonding head81relative to the vacuum chuck table82may be such that the height between a topmost surface of each electrical connector106and a bottommost surface of a corresponding electrical connector108that it is in contact with is equal to a fifth height H5. The TCB bonding head81is then heated and may provide heat to the device package2000in the heating process87, which by thermal conduction causes the reflow of the electrical connectors108and the bonding of the electrical connectors108to the electrical connectors106. In an embodiment, the vacuum chuck table82may also heated and may provide heat to the component package44in the heating process89. In an embodiment, the vacuum chuck table82includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process89may heat up the vacuum chuck table82to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process89may be performed for a duration that is in a range from 0.1 s to 300 s. During the heating processes87and89and during the melting of the electrical connectors108, the height between the topmost surface of each electrical connector66and the bottommost surface of the corresponding electrical connector108that it is in contact with is adjusted to be at a sixth height H6, as shown inFIG.12F. This may be performed by vertically adjusting the height of the TCB bonding head81relative to the vacuum chuck table82. In some embodiments, the sixth height H6may be larger than the fifth height H5. For example, a distance between the topmost surfaces of the electrical connectors106and the bottommost surfaces of the electrical connectors108may be increased. In an embodiment, the fifth height H5may be in a range from 40 μm to 130 μm and the sixth height H6may be in a range from 45 μm to 150 μm. In an embodiment, the fifth height H5may be at least 10 μm. In an embodiment, the sixth height H6may be at least 10 μm.

FIG.12Gillustrates a cross-sectional view of the device package2000after performing the reflow process and heating process87and89described above inFIGS.12E and12F.FIG.12Hshows an enlarged view of the region195shown inFIG.12G. The height between the topmost surface of each electrical connector106and the bottommost surface of a corresponding electrical connector108that it is in contact with is equal to the sixth height H6. Because the height between the topmost surface of each electrical connector106and the bottommost surface of a corresponding electrical connector108is adjusted from the fifth height H5to the sixth height H6during the heating process87and89shown inFIGS.12E and12F, an hourglass joint146is formed. The hourglass joint146comprises the electrical connector106and the electrical connector108. The electrical connector106may comprise a column with a uniform seventh width W7. The electrical connector108may comprise an hourglass shape with a first portion of the electrical connector108having a eighth width W8, a second portion of the electrical connector108having a ninth width W9, and a third portion of the electrical connector108having a tenth width W10. The second portion of the electrical connector108may be in between the first portion and the third portion of the electrical connector108. In some embodiments, the ninth width W9is smaller than the eighth width W8and the tenth width W10. In some embodiments, the seventh width W7, the eighth width W8, and the tenth width W10are equal. In some embodiments, the electrical connector108may comprise curved, concave sidewalls. In an embodiment, the third portion of the electrical connector108may extend through a solder resist layer110on the component package44as shown inFIG.12H. The third portion of the electrical connector108in the solder resist layer110may have a substantially uniform width throughout, and the electrical connector108may decrease continuously in width in a direction toward a mid-point between the bottommost surface of the electrical connector106and a topmost surface of a solder resist110. Further, the curved, concave sidewalls of the electrical connector108may extend continuously from a topmost surface of the solder resist layer110to a bottommost surface of the electrical connector106. In an embodiment, the seventh width W7, the eighth width W8, and the tenth width W10are not equal (e.g. as shown inFIG.12L). In an embodiment, one of the seventh width W7, the eighth width W8, and the tenth width W10is not equal to the other two widths. In an embodiment, the electrical connector108may comprise sidewalls that are curved differently from each other (e.g., as shown inFIG.12M). In an embodiment, sidewalls of one or more of the electrical connector106, the first portion of the electrical connector108and the third portion of the electrical connector108may be curved or sloping (e.g. as shown inFIG.12N). In an embodiment where the third portion of the electrical connector108is curved or sloping, the third portion of the electrical connector108may extend through the solder resist layer110on the component package44. Flux178is then removed (or cleaned) using a method that may comprise spraying solvent, applying de-ionized (DI) water, heating, and drying the device package2000, in accordance with some embodiments. An underfill material (not shown) can be dispensed between the component package44and the package substrate40. The underfill material may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like. In an alternate embodiment, the component package44(described previously inFIG.8) may be attached to the package substrate40using the steps described inFIGS.8through11. Accordingly, the process steps and applicable materials may not be repeated herein.

FIGS.13A,13B, and13Cillustrate cross-sectional views of intermediary stages of manufacturing a semiconductor device package3000, in accordance with some embodiments. The device package3000is another embodiment in which like reference numerals represent like components in the embodiment shown inFIGS.1through11, unless specified otherwise. Accordingly, the process steps and applicable materials may not be repeated herein. The initial steps of this embodiment are essentially the same as shown inFIGS.1through5.

InFIG.13A, TCB bonding head81may be used to pick up the die68, and to place the die68on the package substrate40, such that the electrical connectors77and the die connectors66are in contact. After the placement of the die68on the package substrate40, TCB bonding head81remains contacting the die68, and may apply an upward force on the die68due to the vacuum force83A position of the TCB bonding head81relative to the vacuum chuck table82may be maintained such that a height between a topmost surface of each die connector66and a bottommost surface of a corresponding electrical connector77that it is in contact with is equal to a seventh height H7. The TCB bonding head81is then heated and may provide heat to the die68in a heating process87, and the vacuum chuck table82is also heated and may provide heat to the package substrate40in a heating process89. The heating processes87and89may by thermal conduction cause the reflow of the electrical connectors77and the bonding of the electrical connectors77to the die connectors66. In an embodiment, the TCB bonding head81includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process87may heat up the TCB bonding head81and the die68to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process87may be performed for a duration that is in a range from 0.1 s to 300 s. In an embodiment, the vacuum chuck table82includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process89may heat up the vacuum chuck table82to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process89may be performed for a duration that is in a range from 0.1 s to 300 s. During the heating processes87and89, and during the melting of the electrical connectors77, the height between the topmost surface of each die connector66and the bottommost surface of the corresponding electrical connector66is maintained at the seventh height H7by holding the TCB bonding head81at a fixed vertical position relative to the vacuum chuck table82. In an embodiment, the seventh height H7may be in a range from 5 μm to 60 μm. In an embodiment, the seventh height h7may be up to 100 μm.

FIG.13Billustrates a cross-sectional view of the device package3000after performing the reflow process and heating processes87and89described above inFIG.13A.FIG.13Cshows an enlarged view of the region97shown inFIG.13B. The height between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77that it is in contact with is equal to the seventh height H7. Because the seventh height H7is maintained during the heating processes87and89shown inFIG.13A, a column joint48is formed that has a uniform eleventh width W11throughout an entirety of the seventh height H7of the column joint48. For example, the die connector66may have a cylindrical shape that has a uniform width equal to the eleventh width W11, and the reflowed electrical connector77may likewise have a cylindrical shape that has uniform width equal to the eleventh width W11. Flux78is then removed (or cleaned) using a method that may comprise spraying solvent, applying de-ionized (DI) water, heating, and drying the device package3000, in accordance with some embodiments. The next steps of this embodiment are essentially the same as shown inFIG.7. Accordingly, the process steps and applicable materials may not be repeated herein.

After the formation of the redistribution structure102and the electrical connectors106in the manner described inFIG.7, the component package44(described previously inFIG.8) is attached to the package substrate40. In an embodiment, the component package44is attached to the package substrate40in the manner described inFIGS.8through11, In an alternate embodiment, the component package44is attached to the package substrate40in the manner described inFIGS.12E through12H. Accordingly, the process steps and applicable materials may not be repeated herein.

Advantages can be achieved as a result of the formation of the device package3000in which the package substrate40are bonded to the die68using the electrical connectors77on the package substrate40that are reflowed using thermal compression bonding (TCB). The thermal compression bonding (TCB) apparatus includes the TCB bonding head81that provides the vacuum force83to hold the die68and the vacuum chuck table82that provides the vacuum force85to hold the package substrate40. During the bonding of the package substrate40to the die68, a heating process87and a heating process89is performed to reflow the electrical connectors77in which the TCB bonding head81and the vacuum chuck table82provide heat to reflow the electrical connectors77. During the heating processes87and89, the seventh height H7between the topmost surfaces of the die connectors66and the bottommost surfaces of the electrical connectors77are maintained at a constant in order to allow for the formation of the column joint48. The advantages may include an improvement in the coplanarity (COP) of the device package3000, and the prevention of deformation or warpage of the die68and the package substrate40due to the presence of the vacuum forces83and85during the heating processes87and89. This improvement in coplanarity and reduced warpage further allows for an improved connection between the package substrate40and another component package44(e.g., a printed circuit board described above inFIG.8) when the package substrate40and the component package44are bonded together.

FIGS.14A,14B,14C and14Dillustrate cross-sectional views of intermediary stages of manufacturing a semiconductor device package4000, in accordance with some embodiments. The device package4000is another embodiment in which like reference numerals represent like components in the embodiment shown inFIGS.1through11, unless specified otherwise. Accordingly, the process steps and applicable materials may not be repeated herein. The initial steps of this embodiment are essentially the same as shown inFIGS.1through5.

InFIG.14A, TCB bonding head81may be used to pick up the die68, and to place the die68on the package substrate40, such that the electrical connectors77and the die connectors66are in contact. After the placement of the die68on the package substrate40, TCB bonding head81remains contacting the die68, and may apply an upward force on the die68due to the vacuum force83. After the electrical connectors77and the die connectors66are brought into contact, a position of the TCB bonding head81relative to the vacuum chuck table82may be such that a the height between a topmost surface of each die connector66and a bottommost surface of a corresponding electrical connector77that it is in contact with is equal to an eighth height H8. The TCB bonding head81is then heated and may provide heat to the die68in a heating process87, and the vacuum chuck table82is also heated and may provide heat to the package substrate40in a heating process89. The heating processes87and89may by thermal conduction cause the reflow of the electrical connectors77and the bonding of the electrical connectors77to the die connectors66. In an embodiment, the TCB bonding head81includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process87may heat up the TCB bonding head81to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process87may be performed for a duration that is in a range from 0.1 s to 300 s. In an embodiment, the vacuum chuck table82includes coils (not shown) that heats up when an electrical current(s) flows through. In an embodiment, the heating process89may heat up the vacuum chuck table82to a temperature in a range from 25° C. to 400° C. In an embodiment, the heating process89may be performed for a duration that is in a range from 0.1 s to 400 s. During the heating processes87and89, and during the melting of the electrical connectors77, the height between the topmost surface of each die connector66and the bottommost surface of the corresponding electrical connector66that it is in contact with is adjusted to be at a ninth height H9, as shown inFIG.14B. This may be performed by vertically adjusting the height of the TCB bonding head81relative to the vacuum chuck table82. In some embodiments, the ninth height H9may be larger than the eighth height H8. For example, a distance between the topmost surfaces of the die connectors66and the bottommost surfaces of the electrical connectors77may be increased. In an embodiment, the eighth height H8may be in a range from 5 μm to 60 μm and the ninth height H9may be in a range from 7 μm to 70 μm. In an embodiment, the eighth height H8may be up to 100 μm. In an embodiment, the ninth height H9maybe up to 100 μm.

FIG.14Cillustrates a cross-sectional view of the device package4000after performing the reflow process and heating processes87and89described above inFIGS.14A and14B.FIG.14Dshows an enlarged view of the region99shown inFIG.14C. The height between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77that it is in contact with is equal to the ninth height H9. Because the height between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77is adjusted from the eighth height H8to the ninth height H9during the heating processes87and89shown inFIGS.14A and14B, an hourglass joint50is formed. The hourglass joint50comprises the die connector66and the electrical connector77. The die connector66may comprise a column with a uniform twelfth width W12. The electrical connector77may comprise an hourglass shape with a first portion of the electrical connector77having a thirteenth width W13, a second portion of the electrical connector77having a fourteenth width W14, and a third portion of the electrical connector having a fifteenth width W15. The second portion of the electrical connector77may be in between the first portion and the third portion of the electrical connector77. In some embodiments, the fourteenth width W14is smaller than the thirteenth width W13and the fifteenth width W15. In some embodiments, the twelfth width W12, the thirteenth width W13, and the fifteenth width W15are equal. In some embodiments, the electrical connector77may comprise curved, concave sidewalls. In an embodiment, the third portion of the electrical connector77may extend through a solder resist layer110on the redistribution structure76as shown inFIG.14D. The third portion of the electrical connector77in the solder resist layer110may have a substantially uniform width throughout, and the electrical connector77may decrease continuously in width in a direction toward a mid-point between the bottommost surface of the die connector66and a topmost surface of a solder resist110. Further, the curved, concave sidewalls of the electrical connector77may extend continuously from a topmost surface of the solder resist layer110to a bottommost surface of the die connector66. In an embodiment, the twelfth width W12, the thirteenth width W13, and the fifteenth width W15are not equal (e.g., as shown inFIG.12O). In an embodiment, one of the twelfth width W12, the thirteenth width W13, and the fifteenth width W15is not equal to the other two widths. In an embodiment, the electrical connector77may comprise sidewalls that are curved differently from each other (e.g., as shown inFIG.12P). In an embodiment, sidewalls of one or more of the die connector66, the first portion of the electrical connector77and the third portion of the electrical connector77may be curved or sloping (e.g., as shown inFIG.12Q). In an embodiment where the third portion of the electrical connector77is curved or sloping, the third portion of the electrical connector77may extend through the solder resist layer110on the redistribution structure76. Flux78is then removed (or cleaned) using a method that may comprise spraying solvent, applying de-ionized (DI) water, heating, and drying the device package4000, in accordance with some embodiments. The next steps of this embodiment are essentially the same as shown inFIG.7. Accordingly, the process steps and applicable materials may not be repeated herein.

After the formation of the redistribution structure102and the electrical connectors106in the manner described inFIG.7, the component package44(described previously inFIG.8) is attached to the package substrate40. In an embodiment, the component package44is attached to the package substrate40in the manner described inFIGS.8through11, In an alternate embodiment, the component package44is attached to the package substrate40in the manner described inFIGS.12E through12H. Accordingly, the process steps and applicable materials may not be repeated herein.

Advantages can be achieved as a result of the formation of the device package4000in which the package substrate40is be bonded to the die68using the electrical connectors77on the package substrate40that are reflowed using thermal compression bonding (TCB). The thermal compression bonding (TCB) apparatus comprises the TCB bonding head81that provides the vacuum force83to hold the die68and the vacuum chuck table82that provides the vacuum force85to hold the package substrate40. During the bonding of the package substrate40to the die68, a heating process87and a heating process89are performed to reflow the electrical connectors77in which the TCB bonding head81and the vacuum chuck table82provide heat to reflow the electrical connectors77. During the heating processes87and89, the eighth height H8between the topmost surface of each die connector66and the bottommost surface of a corresponding electrical connector77that it is in contact with is increased to the ninth height H9, in order to allow for the formation of the hourglass joint50. The advantages may include an improvement in the coplanarity (COP) of the device package4000, and the prevention of deformation or warpage of the die68and the package substrate40due to the presence of the vacuum forces83and85during the heating processes87and89. This improvement in coplanarity and reduced warpage further allows for an improved connection between the package substrate40and another component package44(e.g., a printed circuit board described above inFIG.8) when the package substrate40and the component package44are bonded together.

The embodiments of the present disclosure have some advantageous features. The embodiments include the formation of a device package comprising one or more semiconductor chips bonded to an interposer and a package substrate bonded to a side of the interposer opposing the one or more semiconductor chips. The interposer may be bonded to the one or more semiconductor chips using solder bumps on the semiconductor chip(s) and/or the interposer that are reflowed using thermal compression bonding (TCB). During the bonding of the interposer to the semiconductor chip, a heating process is performed to reflow the solder bumps in which a TCB bonding head and a vacuum chuck table provide heat to reflow the solder bumps. During the heating process, the height of the solder bumps can be maintained to allow for the formation of solder bumps with a column shape, or the height of the solder bumps can be increased to allow for the formation of solder bumps with an hourglass shape. As a result, one or more embodiments disclosed herein allow for an improvement in the device package coplanarity (COP), and a reduction in warpage. This improvement in coplanarity and reduced warpage also allows for an improved connection between the package substrate (e.g., a printed circuit board) and the interposer when the package substrate and the interposer are bonded together.

In accordance with an embodiment, a method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, where the die includes a plurality of conductive pillars; attaching a first substrate to a chuck through vacuum suction, where the first substrate includes a plurality of solder bumps; contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, where contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump; and adhering the first solder bump to the first conductive pillar to form a first joint, where adhering the first solder bump to the first conductive pillar includes heating the TCB head. In an embodiment, the method further includes jetting a flux over the first substrate, where the flux coats the plurality of solder bumps on the first substrate; and removing the flux after adhering the first solder bump to the first conductive pillar. In an embodiment, after adhering the first solder bump to the first conductive pillar, a lower portion of the first solder bump extends through a solder resist layer, the lower portion of the first solder bump having a uniform width throughout. In an embodiment, during heating the TCB head the vertical position of the TCB head relative to the chuck is adjusted such that the topmost surface of the first conductive pillar is disposed a second height from the bottommost surface of the first solder bump, where the second height is larger than the first height. In an embodiment, during heating the TCB head the height between the topmost surface of the first conductive pillar and the bottommost surface of the first solder bump is maintained at the first height by maintaining the vertical position of the TCB head relative to the chuck. In an embodiment, adhering the first solder bump to the first conductive pillar further includes heating the chuck. In an embodiment, the first joint has an hourglass shape.

In accordance with an embodiment, a method includes bonding a first side of a first die to a first side of a first substrate, where the first substrate includes a first plurality of solder bumps on the first side of the first substrate, and the first die includes a first plurality of conductive pillars on the first side of the first die, where bonding the first side of the first die to the first side of the first substrate includes attaching the first die to a thermal compression bonding (TCB) head through vacuum suction; attaching the first substrate to a chuck through vacuum suction; adjusting the vertical distance of the TCB head relative to the chuck to initiate contact between a first conductive pillar of the first plurality of conductive pillars and a first solder bump of the first plurality of solder bumps; and heating the TCB head and the chuck to adhere the first conductive pillar to the first solder bump and form a first joint, where during the heating the TCB head and the chuck, the vertical distance of the TCB head relative to the chuck is increased. In an embodiment, after adhering the first conductive pillar to the first solder bump to form the first joint, the first solder bump includes curved, concave sidewalls. In an embodiment, after adhering the first conductive pillar to the first solder bump to form the first joint, the first solder bump and the first conductive pillar include sloping sidewalls. In an embodiment, where after adhering the first conductive pillar to the first solder bump, a lower portion of the first solder bump extends through a solder resist layer, and where the first solder bump decreases continuously in width in a direction toward a mid-point between a bottommost surface of the first conductive pillar and a topmost surface of the solder resist layer. In an embodiment, the method further includes bonding a second side of the first substrate to a first side of a component package. In an embodiment, bonding the second side of the first substrate to the first side of the component package includes attaching the first die and the first substrate to a TCB head through vacuum suction, where the first substrate includes a second plurality of conductive pillars on the second side of the first substrate; attaching the component package to a chuck through vacuum suction, where the component package includes a second plurality of solder bumps on the first side of the component package; adjusting the vertical distance of the TCB head relative to the chuck to initiate contact between a second conductive pillar of the second plurality of conductive pillars and a second solder bump of the second plurality of solder bumps; and heating the TCB head and the chuck to adhere the second conductive pillar to the second solder bump and form a second joint, where during the heating the TCB head and the chuck the vertical distance of the TCB head relative to the chuck is maintained. In an embodiment, bonding the second side of the first substrate to the first side of the component package includes attaching the first die and the first substrate to a TCB head through vacuum suction, where the first substrate includes a third plurality of conductive pillars on the second side of the first substrate; attaching the component package to a chuck through vacuum suction, where the component package includes a third plurality of solder bumps on the first side of the component package; adjusting the vertical distance of the TCB head relative to the chuck to initiate contact between a third conductive pillar of the third plurality of conductive pillars and a third solder bump of the third plurality of solder bumps; and heating the TCB head and the chuck to adhere the third conductive pillar to the third solder bump and form a third joint, where during the heating the TCB head and the chuck, the vertical distance of the TCB head relative to the chuck such is increased. In an embodiment, after adhering the third conductive pillar to the third solder bump to form the third joint the third solder bump includes curved, concave sidewalls. In an embodiment, the concave sidewalls of the third solder bump are curved differently from each other.

In accordance with an embodiment, a package includes a first die; a first substrate bonded to the first die using a plurality of first conductive connectors, where each of the plurality of first conductive connectors includes a first conductive pillar adhered to a first solder bump, where each of the plurality of first conductive connectors includes an hourglass shape, where a lower portion of the first solder bump extends through a solder resist layer, and where the first solder bump decreases continuously in width in a direction toward a mid-point between a bottommost surface of the first conductive pillar and a topmost surface of the solder resist layer; and a second substrate bonded to the first substrate using a plurality of second conductive connectors. In an embodiment, each of the plurality of second conductive connectors includes a second conductive pillar adhered to a second solder bump, and where each of the plurality of second conductive connectors includes an hourglass shape. In an embodiment, each of the plurality of second conductive connectors includes a third conductive pillar adhered to a third solder bump, where the third conductive pillar has a cylindrical shape with a uniform first width, and the third solder bump has a cylindrical shape with a uniform second width. In an embodiment, the first width is equal to the second width.