Electronic assembly, package structure having hollow cylinders and method of fabricating the same

A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.

BACKGROUND

Semiconductor devices and integrated circuits used in a variety of electronic applications, such as cell phones and other electronic equipment, are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for the wafer level packaging.

DETAILED DESCRIPTION

FIG. 1AtoFIG. 7are schematic cross-sectional views of various stages in a manufacturing method of a package structure according to some exemplary embodiments of the present disclosure. Referring toFIG. 1A, a carrier102with a buffer layer104coated thereon is provided. In one embodiment, the carrier102may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstituted wafer used for the method of fabricating the package structure.

In some embodiments, the buffer layer104includes a de-bonding layer104A and a dielectric layer104B, wherein the de-bonding layer104A is located in between the carrier102and the dielectric layer104B. In certain embodiments, the de-bonding layer104A is disposed on the carrier102, and the material of the de-bonding layer104A may be any material suitable for bonding and de-bonding the carrier102from the above layer(s) (e.g., the dielectric layer104B) or any wafer(s) disposed thereon. In some embodiments, the de-bonding layer104A may include a release layer (such as a light-to-heat conversion (“LTHC”) layer) or an adhesive layer (such as an ultra-violet curable adhesive or a heat curable adhesive layer). In some embodiments, the dielectric layer104B may be formed above the de-bonding layer104A. The dielectric layer104B may be made of dielectric materials such as benzocyclobutene (“BCB”), polybenzoxazole (“PBO”), or any other suitable polymer-based dielectric material.

It is noted that the materials of the carrier102, the de-bonding layer104A and the dielectric layer104B are not limited to the descriptions of the embodiments. In some alternative embodiments, the dielectric layer104B may be optionally omitted; in other words, merely the de-bonding layer104A is formed over the carrier102. In certain embodiments, a die-attach film (not shown) may be directly formed on the de-bonding layer104A for the attachment to above components.

After forming the buffer layer104, a plurality of hollow cylinders CX and at least one semiconductor die106A are disposed on the carrier102over the buffer layer104.FIG. 1Bis an enlarged view of the hollow cylinder CX. Referring toFIG. 1B, in the exemplary embodiment, each of the hollow cylinders CX includes a cylindrical body CB, the hollow cylinders CX have lids (L1/L2) covering two opposite terminals of the cylindrical body CB. For instance, a first lid L1is sealing a first terminal of the cylindrical body CB, and a second lid L2is sealing a second terminal of the cylindrical body CB, wherein the first terminal is opposite to the second terminal. In certain embodiments, the cylindrical body CB is hollow in the middle. In other words, a space exists in between the first lid L1and the second lid L2.

Referring back toFIG. 1A, in some embodiments, a width Wx of the hollow cylinders CX is in a range of 1 mm to 10 mm, but the disclosure is not limited thereto. In alternative embodiments, the width Wx of the hollow cylinders CX may be adjusted based on actual design requirements. In some embodiments, the hollow cylinders CX are disposed to surround the semiconductor die106A. In case where a plurality of semiconductor dies exist, the hollow cylinders CX are disposed to surround all the plurality of semiconductor dies. In some embodiments, the hollow cylinders CX are located at corners or edges of the package structure. In some embodiments, the hollow cylinders CX may be disposed on the carrier102after bonding the semiconductor die106A on the carrier102. In some alternative embodiments, the hollow cylinders CX may be disposed on the carrier102before bonding the semiconductor die106A on the carrier102. In some embodiments, the hollow cylinders CX are made of a plastic material or a metal material. In certain embodiments, the hollow cylinders CX are made of metal materials such as copper, gold, silver, or made of plastic materials such as poly(methyl methacrylate), the disclosure is not limited thereto.

As illustrated inFIG. 1A, one or more semiconductor die106A may be picked and placed on the buffer layer104. In certain embodiments, the semiconductor die106A has an active surface AS, and a backside surface BS opposite to the active surface AS. For example, the backside surface BS of the semiconductor die106A may be attached to the buffer layer104through a die attach film (not shown). By using the die attach film, a better adhesion between the semiconductor die106A and the buffer layer104is ensured. In the exemplary embodiment, only one semiconductor die106is illustrated. However, the disclosure is not limited thereto. It should be noted that the number of semiconductor die106A disposed on the buffer layer104may be adjusted based on product requirement.

In the exemplary embodiment, the semiconductor die106A includes a semiconductor substrate106a-1, a plurality of conductive pads106a-2, a passivation layer106a-3, a plurality of conductive posts106a-4, and a protection layer106a-5. As illustrated inFIG. 1A, the plurality of conductive pads106a-2is disposed on the semiconductor substrate106a-1. The passivation layer106a-3is formed over the semiconductor substrate106a-1and has openings that partially expose the conductive pads106a-2on the semiconductor substrate106a-1. The semiconductor substrate106a-1may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and further includes active components (e.g., transistors or the like) and optionally passive components (e.g., resistors, capacitors, inductors or the like) formed therein. The conductive pads106a-2may be aluminum pads, copper pads or other suitable metal pads. The passivation layer106a-3may be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer or a dielectric layer formed of any suitable dielectric materials. Furthermore, in some embodiments, a post-passivation layer (not shown) is optionally formed over the passivation layer106a-3. The post-passivation layer covers the passivation layer106a-3and has a plurality of contact openings. The conductive pads106a-2are partially exposed by the contact openings of the post passivation layer. The post-passivation layer may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers. In some embodiments, the conductive posts106a-4are formed on the conductive pads106a-2by plating. In some embodiments, the protection layer106a-5is formed on the passivation layer106a-3or on the post passivation layer, and covering the conductive posts106a-4so as to protect the conductive posts106a-4. In some embodiments, the semiconductor die106A may be selected from application-specific integrated circuit (ASIC) chips, analog chips (for example, wireless and radio frequency chips), digital chips (for example, a baseband chip), integrated passive devices (IPDs), voltage regulator chips, sensor chips, memory chips, or the like. The disclosure is not limited thereto.

Referring toFIG. 2, in a next step, an insulating material108is formed on the buffer layer104and over the semiconductor die106A. The insulating material108is formed to cover the hollow cylinders CX. In the exemplary embodiment, since the terminals of the hollow cylinders CX are covered by the lids (L1/L2), the insulating material108does not fill into the space within the hollow cylinders CX. In some embodiments, the insulating material108is formed through, for example, a compression molding process, filling up the gaps between the semiconductor die106A and the hollow cylinders CX, and encapsulating the semiconductor die106A. The insulating material108also covers and encapsulates the hollow cylinders CX. At this stage, the conductive posts106a-4and the protection layer106a-5are encapsulated by and well protected by the insulating material108. In other words, the conductive posts106a-4and the protection layer106a-5are not revealed by the insulating material108.

In some embodiments, the insulating material108includes polymers (such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), dielectric materials having low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In an alternative embodiment, the insulating material108may include an acceptable insulating encapsulation material. In some embodiments, the insulating material108may further include inorganic filler or inorganic compound (e.g. silica, clay, and so on) which can be added therein to optimize coefficient of thermal expansion (CTE) of the insulating material108. The disclosure is not limited thereto.

Referring toFIG. 3, a thinning process is performed to remove portions of the insulating material108so that the conductive posts106a-4and the hollow cylinders CX are revealed. In some embodiments, the insulating material108and the protection layer106a-5are ground or polished by a planarization step. For example, the planarization step is performed through a mechanical grinding process and/or a chemical mechanical polishing (CMP) process until the top surfaces106A-TS of the conductive posts106a-4are revealed. In some embodiments, the hollow cylinders CX are also partially polished so that the first lids L1are removed from the terminals of the hollow cylinders CX. In other words, the hollow cylinders CX are grinded and polished to reveal the space therein.

In the illustrated embodiment, the insulating material108is polished to form an insulating encapsulant108′. In some embodiments, the top surface108T of the insulating encapsulant108, the top surface of the conductive posts106a-4, and the top surface of the polished protection layer106a-5are coplanar and levelled with one another. In certain embodiments, a height H1of the hollow cylinders CX is substantially equal to a height H2of the insulating encapsulant108′ after the grinding/polishing process. In some embodiments, after the mechanical grinding or chemical mechanical polishing (CMP) steps, a cleaning step may be optionally performed. For example, the cleaning step is preformed to clean and remove the residue generated from the planarization step. However, the disclosure is not limited thereto, and the planarization step may be performed through any other suitable methods.

Referring toFIG. 4, after the planarization step, a redistribution layer110is formed on the insulating encapsulant108′ and over the semiconductor die106A and the hollow cylinders CX. In some embodiments, the formation of the redistribution layer110includes sequentially forming one or more dielectric layers110a, and one or more metallization layers110bin alternation. In certain embodiments, the metallization layers110bare sandwiched between the dielectric layers110a. Although only two layers of the metallization layers110band three layers of dielectric layers110aare illustrated herein, however, the scope of the disclose is not limited by the embodiments of the disclosure. In other embodiments, the number of metallization layers110band the dielectric layers110amay be adjusted based on product requirement. In some embodiments, the metallization layers110bare electrically connected to the conductive posts106a-4of the semiconductor die106A. In certain embodiments, the metallization layers110bare not located in a region above the hollow cylinders CX.

In certain embodiments, the material of the dielectric layers114A may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In the exemplary embodiment, a first dielectric layer110a-1, a second dielectric layer110a-2and a third dielectric layer110a-3are formed. In some embodiments, in order to prevent the dielectric layer110afrom filling into the space of the hollow cylinders CX, the first dielectric layer110a-1is formed over the insulating encapsulant108′ through a lamination step. Subsequently, the second dielectric layer110a-2and the third dielectric layer110a-3are formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. The disclosure is not limited thereto.

In some embodiments, the material of the metallization layer110bmay be made of conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. In some embodiments, the metallization layer110bmay be patterned copper layers or other suitable patterned metal layers. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc.

After forming the redistribution layer110, a plurality of conductive pads110cmay be disposed on an exposed top surface of the topmost layer of the metallization layers110bfor electrically connecting with conductive balls. In certain embodiments, the conductive pads110care for example, under-ball metallurgy (UBM) patterns used for ball mount. As shown inFIG. 4, the conductive pads110care formed on and electrically connected to the redistribution layer110. In some embodiments, the materials of the conductive pads110cmay include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed by an electroplating process, for example. The number of conductive pads110care not limited in this disclosure, and may be selected based on the design layout. In some alternative embodiments, the conductive pads110cmay be omitted. In other words, conductive balls112formed in subsequent steps may be directly disposed on the redistribution layer110.

Referring still toFIG. 4, after forming the conductive pads110c, a plurality of conductive balls112is disposed on the conductive pads110cand over the redistribution layer110. In some embodiments, the conductive balls112may be disposed on the conductive pads110cby a ball placement process or reflow process. In some embodiments, the conductive balls112are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the conductive balls112are connected to the redistribution layer110through the conductive pads110c. In certain embodiments, the conductive balls112may be electrically connected to the semiconductor die106A through the redistribution layer110. The number of the conductive balls112is not limited to the disclosure, and may be designated and selected based on the number of the conductive pads110c. In some alternative embodiments, an integrated passive device (IPD) (not shown) may optionally be disposed on the redistribution layer110and be electrically connected to the redistribution layer110.

Referring toFIG. 5, in a next step, portions of the redistribution layer110are removed to form the through holes TH. For example, the redistribution layer110may be removed through mechanical or laser drilling. In certain embodiments, portions of the redistribution layer110located above the hollow cylinders CX are removed to reveal the space in the hollow cylinders CX and to form the through holes TH. In some embodiments, the through holes TH penetrate through the redistribution layer110and is connected to the space within the hollow cylinders CX.

Referring toFIG. 6, after removing portions of the redistribution layer110, the structure shown inFIG. 5may be turned upside down and attached to a tape201supported by a frame202. Subsequently, the carrier102is de-bonded so as to separate the dielectric layer104B and the other elements formed thereon from the carrier102. In the exemplary embodiment, the de-bonding process includes projecting a light such as a laser light or an UV light on the de-bonding layer104A (e.g., the LTHC release layer), such that the carrier102can be easily removed. In certain embodiments, the de-bonding layer104A may be further removed or peeled off to reveal the dielectric layer104B. The remaining dielectric layer104B may then be patterned to form a plurality of openings that reveal the second lids L2of the hollow cylinders, wherein the second lids L2are further removed to complete the formation of the through holes TH. In some embodiments, the through holes TH penetrate through the hollow cylinders CX and the redistribution layer110. In certain embodiments, the through holes TH extends from the bottom surface108-BS of the insulating encapsulant108′ through the plurality of hollow cylinders CX to a top surface110-TS of the redistribution layer110.

Referring toFIG. 7, after forming the through holes TH, a thermal module TM may be disposed on the bottom surface108-BS of the insulating encapsulant108′. In some embodiments, the thermal module TM may be a heat sink, a cold plate, or the like, the disclosure is not limited thereto. In certain embodiments, the thermal module TM may be any type of thermal modules used for improving thermal dissipation. After providing the thermal module TM, a fastener FT is used for mechanically fixing the thermal module TM to the package structure PK1. In some embodiments, the fastener FT includes a bolt301that passes through the through holes TH, and nuts302located over the thermal module TM and the redistribution layer110, wherein the nuts302are threaded onto the bolt301. In the exemplary embodiment, bolt301and nuts302are used as the fastener FT for mechanically fixing the thermal module TM to the package structure PK1, however, the disclosure is not limited thereto. In alternative embodiments, any other type of fasteners that is suitable for mechanically fixing the thermal module TM to the package structure PK1can be used.

FIG. 8is a cross-sectional of an electronic assembly according to some exemplary embodiments of the present disclosure. Referring toFIG. 8, in some embodiments, the package structure PK1obtained inFIG. 7may be further mounted onto a circuit substrate SB with other packages, passive devices, and connectors (not shown) to form an electronic assembly. In certain embodiments, the package structure PK1is electrically connected to the circuit substrate SB through the conductive balls112. After mounting the package structure PK1onto the circuit substrate SB, the fastener FT is used for mechanically fixing the package structure PK1to the circuit substrate. For example, the fastener FT includes a bolt301that passes through the through holes TH, and nuts302located over the thermal module TM and the circuit substrate SB, wherein the nuts302are threaded onto the bolt301.

FIG. 9toFIG. 14are schematic cross-sectional views of various stages in a manufacturing method of a package structure according to some other exemplary embodiments of the present disclosure. The embodiment shown inFIG. 9toFIG. 14is similar to the embodiment shown inFIG. 1AtoFIG. 7, hence the same reference numerals are used to refer to the same or liked parts. The difference between the embodiments will be described below.

Referring toFIG. 9, a plurality of hollow cylinders CX and at least one semiconductor die106B are disposed on the carrier102over the buffer layer104. The hollow cylinders CX are disposed on the carrier102to surround the semiconductor die106B. In the exemplary embodiment, a height H1of the hollow cylinders CX is greater than a height H3of the semiconductor die106B. The semiconductor die106B includes a semiconductor substrate106b-1, a plurality of conductive pads106b-2, a passivation layer106b-3, a plurality of conductive posts106b-4, and a protection layer106b-5. As illustrated inFIG. 1A, a top surface106B-TS of the conductive posts106b-4are exposed from the protection layer106b-5.

Referring toFIG. 10, in a next step, a mold MD is provided on the carrier102covering the semiconductor die106B and the plurality of hollow cylinders CX. In some embodiments, the mold MD may comprise runner holes RH and a release film RF attached to an inner surface of the mold MD. The runner holes RH are located on one side of the mold MD. In some embodiments, the release film RF is pressed onto the semiconductor die106B to cover the top surface106B-TS of the conductive posts106b-4. Furthermore, the release film RF is further pressed onto the hollow cylinders CX to partially cover the hollow cylinders CX. Thereafter, an insulating material108is injected into the mold MD through the runner holes RH, so that the insulating material108encapsulates the semiconductor die106B and partially encapsulates the plurality of hollow cylinders CX. In some embodiments, the insulating material108is injected from one side of the mold MD and is spread onto the buffer layer104to cover the buffer layer104. In some embodiments, the insulating material108spreads and surrounds the semiconductor die106B. In certain embodiments, the insulating material108fill up the gaps in between the semiconductor die106B and adjacent hollow cylinders CX. Due to the presence of the release film RF, portions of hollow cylinders CX are not covered by the insulating material108.

Referring toFIG. 11, in a next step, the insulating material108is cured to form an insulating encapsulant108′. The mold MD may then be removed, and the release film RF is peeled off to reveal a top surface106B-TS of the conductive posts106b-4and portions of the hollow cylinders CX. After removing the mold MD, the formed insulating encapsulant108′ encapsulates the semiconductor die106B and partially encapsulates the plurality of hollow cylinders CX. In certain embodiments, the plurality of hollow cylinders CX protrude out from the insulating encapsulant108′. At this stage, the terminals of each of the hollow cylinders CX are still sealed by the first lids L1and the second lids L2.

Referring toFIG. 12, after forming the insulating encapsulant108′, a redistribution layer110is formed over the insulating encapsulant108′ and formed to surround the plurality of hollow cylinders CX. In the exemplary embodiment, the hollow cylinders CX are surrounded by the insulating encapsulant108′ and the redistribution layer110. Furthermore, the height H1of the plurality of hollow cylinders CX is equal to a sum of a height H2of the insulating encapsulant108′ and a height H4of the redistribution layer110. In some embodiments, the formation of the redistribution layer110includes sequentially forming one or more dielectric layers110a, and one or more metallization layers110bin alternation. For example, the first dielectric layer110a-1, the second dielectric layer110a-2and the third dielectric layer110a-3are formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. Furthermore, the metallization layer110bmay be formed by electroplating or deposition and be patterned using photolithography and etching processes. Thereafter, conductive pads110cand conductive balls112may be fabricated in the same way using the methods described in the above embodiments. After forming the redistribution layer110, the first lid L1located at one terminal of the hollow cylinders CX may then be removed to reveal the space within the hollow cylinders CX. For instance, the first lids L1may be removed by mechanical or laser drilling, or other suitable removal techniques.

Referring toFIG. 13, after forming the redistribution layer110and removing the first lids L1, the structure shown inFIG. 12may be turned upside down and attached to a tape201supported by a frame202. Subsequently, the carrier102is de-bonded so as to separate the dielectric layer104B and the other elements formed thereon from the carrier102. In the exemplary embodiment, the de-bonding process includes projecting a light such as a laser light or an UV light on the de-bonding layer104A (e.g., the LTHC release layer), such that the carrier102can be easily removed. In certain embodiments, the de-bonding layer104A may be further removed or peeled off to reveal the dielectric layer104B. The remaining dielectric layer104B may then be patterned to form a plurality of openings that reveal the second lids L2of the hollow cylinders, wherein the second lids L2are further removed to complete the formation of the through holes TH. In some embodiments, the through holes TH penetrate through the hollow cylinders CX. In certain embodiments, the through holes TH extends from the bottom surface108-BS of the insulating encapsulant108′ through the plurality of hollow cylinders CX to a top surface110-TS of the redistribution layer110.

Referring toFIG. 14, after forming the through holes TH, a thermal module TM may be disposed on the bottom surface108-BS of the insulating encapsulant108′. In some embodiments, the thermal module TM may be a heat sink, a cold plate, or the like, the disclosure is not limited thereto. In certain embodiments, the thermal module TM may be any type of thermal modules used for improving thermal dissipation. After providing the thermal module TM, a fastener FT is used for mechanically fixing the thermal module TM to the package structure PK2. In some embodiments, the fastener FT includes a bolt301that passes through the through holes TH, and nuts302located over the thermal module TM and the redistribution layer110, wherein the nuts302are threaded onto the bolt301. In the exemplary embodiment, bolt301and nuts302are used as the fastener FT for mechanically fixing the thermal module TM to the package structure PK2, however, the disclosure is not limited thereto. In alternative embodiments, any other type of fasteners that is suitable for mechanically fixing the thermal module TM to the package structure PK2can be used.

FIG. 15is a cross-sectional of an electronic assembly according to some other exemplary embodiments of the present disclosure. Referring toFIG. 15, in some embodiments, the package structure PK1obtained inFIG. 14may be further mounted onto a circuit substrate SB with other packages, passive devices, and connectors (not shown) to form an electronic assembly. In certain embodiments, the package structure PK2is electrically connected to the circuit substrate SB through the conductive balls112. After mounting the package structure PK2onto the circuit substrate SB, the fastener FT is used for mechanically fixing the package structure PK1to the circuit substrate SB. For example, the fastener FT includes a bolt301that passes through the through holes TH, and nuts302located over the thermal module TM and the circuit substrate SB, wherein the nuts302are threaded onto the bolt301.

In the above embodiments, a plurality of hollow cylinders is provided prior to forming the insulating encapsulant and the redistribution layer. In some applications that require a though hole in the package structure (e.g. for screw bolt fastening), the mechanical or laser drilling process will cause extra mechanical strain or heat that could induce damage to the package body. The presence of the hollow cylinders will reduce the need of mechanical or laser drilling processes in producing through holes in the package structure. For example, through holes can be simply produced by removing the lids covering the hollow cylinders. As such, damages to the package structure caused by mechanical or laser drilling can be significantly reduced. Furthermore, the process cost can also be significantly reduced.

In some embodiments of the present disclosure, a package structure including at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes are provided. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.

In another embodiment of the present disclosure, an electronic assembly including a circuit substrate, a package structure and a fastener is provided. The package structure is disposed on the circuit substrate, wherein the package structure includes at least one semiconductor die, an insulating encapsulant, a plurality of hollow cylinders, a redistribution layer and through holes. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die. The plurality of hollow cylinders is embedded in the insulating encapsulant. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are extending from the bottom surface of the insulating encapsulant through the plurality of hollow cylinders to a top surface of the redistribution layer. The fastener passes through the through holes of the package structure, and is used for mechanically fixing the package structure to the circuit substrate.

In yet another embodiment of the present disclosure, a method of fabricating a package structure is described. The method includes the following steps. At least one semiconductor die and a plurality of hollow cylinders are placed on a carrier, wherein the plurality of hollow cylinders surround the at least one semiconductor die and have lids covering two opposite terminals of each of the hollow cylinders. An insulating encapsulant is formed to encapsulate the at least one semiconductor die and the plurality of hollow cylinders. A redistribution layer is formed over the insulating encapsulant. The lids covering the terminals of the plurality of hollow cylinders are removed to form through holes extending from a bottom surface of the insulating encapsulant through the plurality of hollow cylinders to a top surface of the redistribution layer. A thermal module is provided on the bottom surface of the insulating encapsulant. A fastener passing though the through holes is provided, wherein the fastener is used for mechanically fixing the thermal module to the package structure.