Semiconductor device and method of manufacturing same

To improve the heat dissipation characteristics of a semiconductor device.The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste. Heat in the semiconductor chip is conducted from the back surface of the semiconductor chip to the heat dissipating plate via the silver paste, the die pad, and the member, and dissipated to the outside of the semiconductor device therefrom via the lead.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2009-86427 filed on Mar. 31, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method of manufacturing the same, in particular, to technology which is effective when applied to a resin-sealed semiconductor package and a method of manufacturing the same.

A QFP semiconductor device is manufactured by mounting a semiconductor chip over a chip mounting part of a lead frame, coupling a plurality of leads of the lead frame and a plurality of electrodes of the semiconductor chip with a bonding wire, forming a sealing resin part that seals the chip mounting part, the semiconductor chip, the bonding wire, and the inner lead part of the leads, cutting the lead from the lead frame, and bending the outer lead part of the lead.

Japanese Patent Laid-Open No. Hei 6-216303 (Patent Document 1) describes a technique to make the outer dimensions of a die pad smaller than the outer dimensions of a semiconductor chip to be mounted thereon.

Japanese Patent Laid-Open No. Hei 11-168169 (Patent Document 2) describes a technique to provide a ground coupling part electrically coupled to a tab suspension lead and supported thereby.

Japanese Patent Laid-Open No. Hei 8-78605 (Patent Document 3) describes a technique to provide a slit in the center of a die pad part and at the same time, to provide a plurality of slits that surround the slit around the outer circumference of the die pad part.

Japanese Patent Laid-Open No. 2001-345412 (Patent Document 4) describes a semiconductor device having a configuration in which a die pad support that supports a die pad has a stress relaxing part in a region located between the die pad and the tip end of an inner lead.

Japanese Patent Laid-Open No. 2005-183492 (Patent Document 5) describes that a die pad has a bonded part in the center, an opened slit part, and a circumferential edge part, the circumferential edge part is formed around the outside of the bonded part, the slit part is formed so as to surround the bonded part and to be located between the bonded part and the circumferential edge part, the four corners of a semiconductor chip bonded to the bonded part are supported while overlapping the circumferential edge part, and part of the slit part bulges out to the outside of the semiconductor chip.

SUMMARY OF THE INVENTION

The examination of the inventors of the present invention has found the following.

A semiconductor package (semiconductor device) used in an automobile etc. is placed in a high temperature environment when on board, and therefore, an LSI formed in a semiconductor chip in the package is operated in a high temperature environment as a result. Further, as the functions of an LSI are improved or its operation speed is increased, power consumption of a semiconductor chip in a package tends to increase and the amount of generated heat also tends to increase. Because of this, the temperature of a semiconductor element in operation, which constitutes the LSI in the semiconductor chip, is the sum of the high temperature in the environment and an increase in temperature due to heat generation, and therefore, the temperature becomes higher and higher.

However, the higher the temperature of a semiconductor element (MISFET element etc.) in operation, which constitutes an LSI in a semiconductor chip, the more likely the deterioration of a gate insulating film etc. occurs, and therefore, its lifetime is reduced. Further, in an operation at high temperatures, the leak current tends to increase and therefore a malfunction becomes more likely to occur. Because of this, it is desired to suppress an increase in temperature of a semiconductor chip in a package by improving the heat dissipation characteristics of the semiconductor package. For example, for a semiconductor package used as a microcomputer for controlling an engine and a transmission of an automobile, it is demanded to suppress the temperature of a semiconductor element formed in a semiconductor chip in the package to 150° C. or less under the conditions that power consumption is 0.7 W and the temperature of the environment when in operation is 125° C.

Because of this, a semiconductor package is desired, which has high reliability and has improved the heat dissipation characteristics (that is, the thermal resistance is low).

The present invention has been made in view of the above circumstances and provides a technique capable of improving the heat dissipation characteristics of a semiconductor device.

The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.

The following explains briefly the outline of a typical invention among the inventions disclosed in the present application.

A semiconductor device according to a typical embodiment has a semiconductor chip, a plurality of leads arranged around the semiconductor chip, a bonding wire that electrically couples the lead and an electrode, respectively, a chip mounting part on which the semiconductor chip is mounted, a frame body part arranged between the chip mounting part and the lead so as to surround the chip mounting part, and a plurality of suspension leads linked to the outer edge of the frame body part. Further, the semiconductor device comprises a sealing body that seals the semiconductor chip, the bonding wire, the chip mounting part, the frame body part, the suspension lead, and part of the lead. Then, the chip mounting part is located immediately under the semiconductor chip and has a first part smaller than the outer shape of the semiconductor chip and a plurality of second parts that connect the first part and the inner edge of the frame body part, and the main surface of the first part and the main surface of the part of the second part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with an adhesive.

A semiconductor device according to another typical embodiment has a semiconductor chip, a plurality of leads arranged around the semiconductor chip, a bonding wire that electrically couples the lead and the electrode, respectively, a chip mounting part on which the semiconductor chip is mounted, a frame body part arranged between the chip mounting part and the lead so as to surround the chip mounting part, and a plurality of suspension leads linked to the outer edge of the frame body part. Further, the semiconductor device comprises a sealing body that seals the semiconductor chip, the bonding wire, the chip mounting part, the frame body part, the suspension lead, and part of the lead. Then, the chip mounting part is located immediately under the semiconductor chip and has a first part smaller than the outer shape of the semiconductor chip and a plurality of second parts that connect the first part and the inner edge of the frame body part, the main surface of the first part and the main surface of the part of the second part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with an adhesive, and the thermal conductivity of the adhesive is higher than the thermal conductivity of the sealing body.

A semiconductor device according to still another typical embodiment has a semiconductor chip, a plurality of leads arranged around the semiconductor chip, a bonding wire that electrically couples the lead and the electrode, respectively, a chip mounting part on which the semiconductor chip is mounted, and a plurality of suspension leads linked to the chip mounting part. Further, the semiconductor device comprises a sealing body that seals the semiconductor chip, the bonding wire, the chip mounting part, the suspension lead, and part of the lead. Then, the outer edge of the chip mounting part is located outside the outer circumference of the semiconductor chip, a plurality of openings that penetrate through from the main surface to the back surface is formed in the chip mounting part, and the respective openings have a part that overlaps the semiconductor chip in a planar manner and a part that does not. Then, the main surface of the chip mounting part in the region in opposition to the back surface of the semiconductor chip and in the region where the openings are not formed is bonded to the back surface of the semiconductor chip in its entire surface with an adhesive.

A method of manufacturing a semiconductor device according to still another typical embodiment has the steps of (a) preparing a lead frame having a chip mounting part having a frame body part, a first part located in the center of a region surrounded by the frame body part, and a plurality of second parts that connect the first part and the inner edge of the frame body part, and a plurality of leads arranged around the frame body part, and (b) applying an adhesive over the main surface of the chip mounting part of the lead frame. Further, the method has the steps of (c) after the step (b), arranging the semiconductor chip via the adhesive over the main surface of the chip mounting part of the lead frame so that the back surface of the semiconductor chip is in opposition to the main surface of the chip mounting part, and spreading the adhesive on the entire surface of the part where the main surface of the chip mounting part and the back surface of the semiconductor chip are in opposition to each other by applying a load to the semiconductor chip, and (d) after the step (c), curing the adhesive.

The following explains briefly the effect acquired by the typical invention among the inventions disclosed in the present application.

According to a typical embodiment, it is possible to improve the heat dissipation characteristics of a semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following embodiments will be explained, divided into plural sections or embodiments, if necessary for convenience. Except for the case where it shows clearly in particular, they are not mutually unrelated and one has relationships such as a modification, details, and supplementary explanation of some or entire of another. In the following embodiments, when referring to the number of elements, etc. (including the number, a numeric value, an amount, a range, etc.), they may be not restricted to the specific number but may be greater or smaller than the specific number, except for the case where they are clearly specified in particular and where they are clearly restricted to a specific number theoretically. Furthermore, in the following embodiments, it is needless to say that an element (including an element step etc.) is not necessarily indispensable, except for the case where it is clearly specified in particular and where it is considered to be clearly indispensable from a theoretical point of view, etc. Similarly, in the following embodiments, when shape, position relationship, etc. of an element etc. is referred to, what resembles or is similar to the shape substantially shall be included, except for the case where it is clearly specified in particular and where it is considered to be clearly not right from a theoretical point of view. This statement also applies to the numeric value and range described above.

Embodiments of the present invention are explained in detail below based on the drawings. In all the drawings for explaining embodiments, the same symbol is attached to the same member having the same function, as a principle, and the repeated explanation thereof is omitted. In the following embodiments the explanation of the same or similar parts is not given unless it is necessary in particular.

In the drawings used in the embodiments, in order to make a drawing intelligible, hatching may be omitted even if it is a section view. In order to make a drawing intelligible, hatching may be attached even if it is a plan view.

First Embodiment

About Structure of Semiconductor Device

A semiconductor device in an embodiment of the present invention is explained with reference to the drawings.

FIG. 1is a top view (plan view) of a semiconductor device1, which is an embodiment of the present invention,FIG. 2is a bottom view (back view) of the semiconductor device1, andFIG. 3is a plan perspective view (top view) of the semiconductor device1when a sealing resin part7is viewed perspectively.FIG. 4is a partially enlarged view (partially enlarged plan perspective view) ofFIG. 3, showing an enlarged view of the part in the vicinity of the center (a semiconductor chip2and a region in the vicinity thereof) inFIG. 3.FIG. 5is a plan perspective view (partially enlarged plan perspective view) of the semiconductor device1when the semiconductor chip2and a bonding wire5are removed (when viewed perspectively). For easier understanding, the position at which the semiconductor chip2is mounted (arranged) is shown by a dotted line inFIG. 5.FIG. 6andFIG. 7are each a section view (side section view) of the semiconductor device1and the section view at the position along A1-A1line inFIG. 1toFIG. 3substantially corresponds toFIG. 6and the section view at the position along B1-B1line inFIG. 1toFIG. 3substantially corresponds toFIG. 7. Symbol X shown in each plan view (plan views in the first embodiment and in second to ninth embodiments to be described later) indicates a first direction (X direction) and symbol Y indicates a second direction (Y direction) perpendicular to the first direction X.

The semiconductor device1in the present embodiment shown inFIG. 1toFIG. 7is a semiconductor device in the form of a resin-sealed semiconductor package, that is, a QFP (Quad Flat Package) semiconductor device.

The semiconductor device1in the present embodiment has the semiconductor chip2, a die pad3that supports or mounts the semiconductor chip2, a plurality of leads4formed by a conductor, a plurality of the bonding wires5that electrically couple the leads4and a plurality of electrodes PD on a surface2aof the semiconductor chip2, respectively, a heat dissipating plate6arranged between the semiconductor chip2and the leads4, and the sealing resin part7that seals these parts.

The sealing resin part (sealing part, sealing resin, sealing body)7includes, for example, a resin material, such as a thermosetting resin material, and may include a filler etc. By the sealing resin part7, the semiconductor chip2, the lead4, the bonding wire5, and the heat dissipating plate6are sealed and protected both electrically and mechanically. The sealing resin part7has a top surface7a, which is one of the main surfaces, and a bottom surface (back surface, bottom surface)7b, which is the main surface on the opposite side of the top surface7a. The plane figure (outer shape) of the sealing resin part7that intersects its width is a rectangle and each of sides SD1, SD2, SD3, SD4of the plane rectangle of the sealing resin part7is parallel with the X direction or Y direction. That is, the side SD1and the side SD3in opposition to each other of the sealing resin part7are parallel with the Y direction and the side SD2and the side SD4in opposition to each other of the sealing resin part7are parallel with the X direction perpendicular to the Y direction.

The plane figure of the semiconductor chip2that intersects its width is a rectangle, and the semiconductor chip2is manufactured by, for example, after forming various semiconductor elements or semiconductor integrated circuits on the main surface of a semiconductor substrate (semiconductor wafer) including single crystal silicon etc., separating the semiconductor substrate into each semiconductor chip by dicing etc. The semiconductor element formed in the semiconductor chip2includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) element etc. Hereinafter, when the plane figure is a rectangle, it may sometimes be referred to as a plane rectangle.

On the surface (main surface, top surface)2a, which is one of the main surfaces of the semiconductor chip2and at the same time, is the main surface on the semiconductor element formation side, a plurality of the electrodes (pad electrodes, bonding pads) PD is formed. Each electrode PD of the semiconductor chip2is electrically coupled to a semiconductor element or semiconductor integrated circuit formed inside the semiconductor chip2or in the surface layer part. It is assumed that the main surface of the semiconductor chip2on the side on which the electrode PD is formed is referred to as the surface2aand the main surface on the opposite side of the main surface (that is, the surface2a) on which the electrode PD is formed is referred to as a back surface2bof the semiconductor chip2. The electrodes PD are arranged along the periphery of the surface2aof the semiconductor chip2.

The semiconductor chip2is mounted (arranged) over a top surface3aof the die pad3so that the surface2aof the semiconductor chip2faces upward, and the back surface2bof the semiconductor chip2is bonded (joined) to and fixed on the top surface3aof the die pad3via an adhesive (die bond material, joint material)8. As the adhesive8, an adhesive having a high thermal conductivity is used. In particular, it is recommended to use a silver paste containing a filler of silver (Ag) in an epoxy resin as the adhesive8. The thermal conductivity of the adhesive8is higher than the thermal conductivity of the sealing resin part7. For example, when the sealing resin part7is an epoxy resin containing a silica filler, its thermal conductivity is about 1 W/m·K and when the adhesive8is an epoxy resin containing a silver filler, its thermal conductivity is about 3 to 6 W/m·K. The semiconductor chip2is sealed in the sealing resin part7and not exposed from the sealing resin part7. The semiconductor chip2is arranged in the sealing resin part7so that each side (each of the four sides of the plane rectangular semiconductor chip2) of the semiconductor chip2is parallel with the X direction or the Y direction.

The lead (lead part)4includes a conductor, and preferably, is made of a metal material, such as copper (Cu) or copper alloy. Each lead4includes an inner lead part4a, which is a part of the lead4located inside the sealing resin part7, and an outer lead part4b, which is a part of the lead4located outside the sealing resin part7, and the outer lead part4bprojects from the side surface of the sealing resin part7to the outside of the sealing resin part7.

The leads4are arranged around the semiconductor chip2so that one end part of each lead4(tip end part of the inner lead part4a) is in opposition to the semiconductor chip2. Hereinafter, the end part of the lead4on the side in opposition to the semiconductor chip2is referred to as the tip end part of the inner lead part4a.

A material that constitutes the sealing resin part7is filled between the inner lead parts4aof the neighboring leads4. Each electrode PD on the surface2aof the semiconductor chip2is electrically coupled to the inner lead part4aof each lead4via the bonding wire5, which is a conductive coupling member. That is, one end part of both ends of each bonding wire5is coupled to each electrode PD of the semiconductor chip2and the other end part is coupled to a top surface4cof the inner lead part4aof each lead4. The bonding wire5is a conductive coupling member for electrically coupling the electrode PD of the semiconductor chip2and the lead4, and more specifically, it is a conductive wire and preferably, made of a thin metal wire, such as a gold (Au) wire or copper (Cu) wire. The bonding wire5is sealed in the sealing resin part7and not exposed from the sealing resin part7.

The outer lead part4bof each lead4is bent and worked so that the bottom surface of the outer lead part4bin the vicinity of the end part is located somewhat below the bottom surface7bof the sealing resin part7. The outer lead part4bof the lead4functions as an external coupling terminal part (external terminal) of the semiconductor device1.

The heat dissipating plate (frame body, frame body part)6is arranged so as to be located between the semiconductor chip2and the leads4and to surround the semiconductor chip2in a planar view. The heat dissipating plate6is a member in the form of a frame (that is, a frame body part) that surrounds the semiconductor chip2in a planar manner, and preferably, is arranged at a position and in a form that do not overlap the semiconductor chip2in a planar manner. That is, preferably, the semiconductor chip2is arranged inside an inner edge (inner circumference)6cof the heat dissipating plate6in the form of a frame so that the outer circumference of the semiconductor chip2is located inside (that is, toward the side nearer to the die pad3) the inner edge6cof the heat dissipating plate6in the form of a frame in a planar view. The inner lead parts4aof the leads4are arranged so as to surround an outer edge (outer circumference)6dof the heat dissipating plate6in the form of a frame along the outer edge6dof the heat dissipating plate6in the form of a frame in a planar view. Preferably, the heat dissipating plate6and the leads4do not overlap in a planar manner, and if so, it becomes easy to work the die pad3and the heat dissipating plate6so as to be lowered.

In the present application, the wording “in a planar manner” or “in a planar view” means that something is viewed in a plane parallel with the top surface2aor the back surface2bof the semiconductor chip2. Further, in the present application, the wording “to surround in a planar manner” or just “to surround” means that something is surrounded when viewed in a plane parallel with the top surface2aor the back surface2bof the semiconductor chip2and the case is also included, where the height of what surrounds differs from the height of what is to be surrounded.

The die pad3is surrounded by the heat dissipating plate6in the form of a frame in a planar manner, and the die pad (first part of a chip mounting part)3is arranged in the center of the region surrounded by the heat dissipating plate6in the form of a frame, and the heat dissipating plate6and the die pad3are linked with a plurality of members (second parts of the chip mounting part)9. The heat dissipating plate6, the die pad3, and the member9are formed integrally by the same material, and the member9is a linking part that connects (links) an inner edge6bof the heat dissipating plate6and the die pad3.

In the die pad3, the inner lead part4a, the heat dissipating plate6, and the member9, respectively, the main surface facing the side of the top surface7aof the sealing resin part7is referred to as a top surface and the main surface facing the side of the bottom surface7bof the sealing resin part7is referred to as a bottom surface (or back surface), and the top surface and the bottom surface are the main surfaces on the opposite sides. The top surfaces of die pad3, the inner lead part4a, the heat dissipating plate6, and the member9, respectively, face in the same direction (toward the side of the top surface7aof the sealing resin part7) and the bottom surfaces of the die pad3, the inner lead part4a, the heat dissipating plate6, and the member9, respectively, face in the same direction (toward the side of the bottom surface7bof the sealing resin part7). Consequently, the heat dissipating plate6has a top surface (main surface)6afacing the side of the top surface7aof the sealing resin part7, the bottom surface (back surface)6bon the opposite side of the top surface6aand facing the side of the bottom surface7bof the sealing resin part7, the inner edge6cfacing the side of the die pad3, and an outer edge6don the opposite side of the inner edge6c. The top surface of the die pad3and the top surface of the member9are continuous and flat. Because of this, the top surface of the die pad3and the top surface of the member9are both assigned symbol3aand referred to as the top surface (main surface)3a, and the bottom surface of the die pad3and the bottom surface of the member9are both assigned symbol3band referred to as a bottom surface (back surface)3b.

One end of each member9is formed (linked, coupled) integrally to the inner edge6cof the heat dissipating plate6and the other end is formed (linked, coupled) integrally to the die pad3. A plurality of the members9is formed and preferably, the four members9are formed. In the present embodiment, the four members9are formed so that the four corners of the heat dissipating plate6are connected (linked) to the die pad3. The plane figure of the die pad3is, for example, a circle, and the plane dimensions (outer shape, outer dimensions) of the die pad3are less than the plane dimensions (outer shape, outer dimensions) of the semiconductor chip2and the die pad3is included in a planar manner by the semiconductor chip2mounted thereon.

The die pad3is arranged immediately under the semiconductor chip2and preferably, is arranged immediately under the center part of the semiconductor chip2(center part of the back surface2b). However, the plane dimensions of the die pad3are less than the plane dimensions (outer dimensions) of the semiconductor chip2, and therefore, the entire top surface of the die pad3overlaps the semiconductor chip2in a planar manner, however, the back surface2bof the semiconductor chip2includes a region that overlaps the die pad3in a planar manner, a region that overlaps the member9in a planar manner, and a region that overlaps none of the die pad3, the member9, and the heat dissipating plate6.

The region of the back surface2bof the semiconductor chip2, which overlaps the die pad3in a planar manner and which is in opposition to the top surface3aof the die pad3, is bonded to the top surface3aof the die pad3in its entire region via the adhesive8. Then, the region of the back surface2bof the semiconductor chip2, which overlaps the member9in a planar manner and which is in opposition to the top surface3aof the member9, is bonded to the top surface3aof the member9in its entire region via the adhesive8. On the other hand, to the region of the back surface2bof the semiconductor chip2, which overlaps none of the die pad3, the member9, and the heat dissipating plate6in a planar manner and which is in opposition to neither the top surface3aof the die pad3nor the top surface3aof the member9, the sealing resin part7is bonded.

In other words, the whole of the top surface3aof the die pad3and part of the top surface3aof each member9overlap the semiconductor chip2in a planar manner and are in opposition to the back surface2bof the semiconductor chip2, and in the region that overlaps the semiconductor chip2in a planar manner and which is in opposition to the back surface2bof the semiconductor chip2, the whole of the top surface3aof the die pad3and the member9is bonded to the back surface2bof the semiconductor chip2with the adhesive8. Because the heat dissipating plate6in the form of a frame and the semiconductor chip2do not overlap in a planar manner, the part of the top surface3aof each member9in the vicinity of the part linked to the heat dissipating plate6may not overlap the semiconductor chip2in a planar manner. Because of this, in the region that does not overlap the semiconductor chip2in a planar manner and which is not in opposition to the back surface2bof the semiconductor chip2, the sealing resin part7is bonded over the top surface6aof the heat dissipating plate6and over the top surface3aof each member9. That is, all of the regions of the top surface3aof the die pad3and each member9, which are in opposition to the back surface2bof the semiconductor chip2, are bonded to the back surface2bof the semiconductor chip2via the adhesive8.

In the present embodiment, the semiconductor chip2is bonded not only to the die pad3but also to the member9with the adhesive8, and therefore, it is possible to regard the combination of both the die pad3and the member9as a chip mounting part. Because of this, the top surface3aof the die pad3and the member9is a chip mounting surface (surface on which the semiconductor chip2is mounted). The member9further has a function as a heat conduction path (heat dissipation path) that conducts heat produced in the semiconductor chip2to the heat dissipating plate6via the member9, in addition to the function to hold the die pad3to the heat dissipating plate6and the function to mount the semiconductor chip2.

On the outer edge (outer circumference)6dof the heat dissipating plate6, a plurality of suspension leads10is formed integrally. The suspension lead10is provided in order to hold the die pad3, the member9, and the heat dissipating plate6to (the frame of) the lead frame for manufacturing the semiconductor device1when manufacturing the semiconductor device1.

Each suspension lead10is formed integrally with the heat dissipating plate6by the same material as that of the heat dissipating plate6, and one end is formed (linked, coupled) integrally to the heat dissipating plate6and extends outwardly (in the direction of departing from the heat dissipating plate6and the die pad3in a planar manner), and extends in the sealing resin part7until the end part on the opposite side of the side linked to the heat dissipating plate6reaches the side surface of the sealing resin part7. Preferably, to the respective four corners of the outer edge6dof the heat dissipating plate6, the suspension lead10is formed integrally and extends in the sealing resin part7until the end part on the opposite side of the side coupled to the heat dissipating plate6of each suspension lead10reaches the side surface of the four corners (corner parts) of the sealing resin part7in the form of a plane rectangle. In other words, each suspension lead10extends in the sealing resin part7in the direction from the center of the sealing resin part7toward the corner parts (four corners) of the sealing resin part7in a planar view.

The part of the suspension lead10that projects from the sealing resin part7is cut after the sealing resin part7is formed, and the cut surface (end surface) produced by the cutting of the suspension lead10is exposed at the side surface (here, the side surface of the four corners) of the sealing resin part7. The cut surface of the suspension lead10exposed at the side surface (here, the side surface of the four corners) of the sealing resin part7is the end part on the opposite side of the end part on the side coupled to the heat dissipating plate6of the suspension lead10. Each of the (four, here) suspension leads4is bent at a bending part (flexing part)10aso that the top surface3aof the die pad3and the member9and the top surface6aof the heat dissipating plate6are lower than the top surface4cof the inner lead part4aof the leads4.

The die pad3, the (four, here) members9, the heat dissipating plate6, and the (four, here) suspension leads10are formed integrally by the same material. The heat dissipating plate6is arranged in order to promote the dissipation of heat produced in the semiconductor chip2to the lead4. Because of this, it is preferable to use a metal material having a high thermal conductivity as a material to constitute the die pad3, the member9, the heat dissipating plate6, and the suspension lead10.

Further, it is preferable to form the suspension lead10into a thin shape so as not to block the array of the leads4as long as it has rigidity capable of holding the die pad3, the member9, and the heat dissipating plate6to the lead frame when manufacturing the semiconductor device1. On the other hand, the member9has the function to conduct (transmit) heat produced in the semiconductor chip2to the heat dissipating plate6, and therefore, if it is formed into too thin a shape, the heat dissipating characteristics are degraded. Because of this, preferably, a width (width in the direction perpendicular to the direction in which the member9extends from the die pad3toward the heat dissipating plate6) W1of the member9is greater than a width (width in the direction perpendicular to the direction in which the suspension lead10extends) W2(that is, W1>W2). As a result, it is possible to cause both the improvement in the thermal conductivity from the semiconductor chip2to the heat dissipating plate6via the member9and the easiness of arraying the leads4to coexist.

The lead4is separated from the die pad3, the member9, the heat dissipating plate6, and the suspension lead10and not formed integrally therewith. However, it is made easy to manufacture the semiconductor device1by providing the lead4, the die pad3, the member9, the heat dissipating plate6, and the suspension lead10in the same lead frame. Because of this, it is preferable that the lead4, the die pad3, the member9, the heat dissipating plate6, and the suspension lead10be formed by the same material and due to this, it is possible to manufacture the semiconductor device1by providing the lead4, the die pad3, the member9, the heat dissipating plate6, and the suspension lead10in the same lead frame and thereby the manufacture of the semiconductor device1is made easy. Because the lead4has the function to lead the circuit within the semiconductor chip2to the outside of the semiconductor device, and therefore, it is preferable to use a material having a high electric conductivity and because a metal material has a high electric conductivity, it is preferable to use a metal material as a material to constitute the lead4. Because of this, it is preferable for the die pad3, the lead4, the heat dissipating plate6, the member9, and the suspension lead10to be formed by the same metal material from the standpoint of the high thermal conductivity of the heat dissipating plate6and the high electric conductivity of the lead4. It is particularly preferable for the die pad3, the lead4, the heat dissipating plate6, the member9, and the suspension lead10to be formed by a metal material that contains copper (Cu) as its principal component, such as copper (Cu) and copper alloy, from the standpoint of the high thermal conductivity, high electric conductivity, cost, and easiness of working.

The semiconductor chip2, the die pad3, the bonding wire5, the heat dissipating plate6, and the member9are sealed in the sealing resin part7and not exposed from the sealing resin part7. On the other hand, as to the lead4, the inner lead part4ais sealed in the sealing resin part7and the outer lead part4bis exposed from the sealing resin part7as described above. The end surface of the suspension lead10on the opposite side of the side coupled to the heat dissipating plate6is exposed at the corner part side surface of the sealing resin part7and other parts are sealed in the sealing resin part7.

<About Heat Dissipation Path of QFP>

Next, a heat dissipation path of a QFP semiconductor device is explained.FIG. 8is an explanatory diagram heat dissipation path of a QFP semiconductor device101.

In the semiconductor device101, a semiconductor chip102is mounted over a die pad103of a lead frame, a lead104of the lead frame and the electrode of the semiconductor chip102are coupled with a bonding wire105, the die pad103, the semiconductor chip102, the bonding wire105, and the inner lead part of the lead104are sealed by a sealing resin part107, the lead104is cut from the lead frame, and the outer lead part of the lead104is bent and worked. The semiconductor device101is packaged (by solder) over a packaging substrate (wiring substrate) PWB. At this time, the outer lead part of the lead104of the semiconductor device101and a terminal TE on the top surface of the packaging substrate PWB are joined and electrically coupled via a solder SD. The method of packaging the semiconductor device1described above in the present embodiment on the packaging substrate PWB is the same as that of the semiconductor device101. That is, when packaging the above-mentioned semiconductor device1on the packaging substrate PWB, (the bottom surface4cof) the outer lead part4bof the lead4of the semiconductor device1is joined and electrically coupled to the terminal TE on the top surface of the packaging substrate PWV via the solder SD. When the above-mentioned semiconductor device1is packaged on the packaging substrate PWB, it is only required to read the semiconductor device101, the semiconductor chip102, the die pad103, the lead104, the bonding wire105, and the sealing resin part107as the semiconductor device1, the semiconductor chip2, the die pad3, the lead4, the bonding wire5, and the sealing resin part7, respectively.

In the case of a general packaging method as shown inFIG. 8, in which a heat dissipating fin etc. is not provided over the top surface of the sealing resin part107of the semiconductor device101, most of the heat produced in the semiconductor chip2in the semiconductor device101is dissipated through the following three paths (first heat dissipation path, second heat dissipation path, third heat dissipation path).

The first heat dissipation path is a heat dissipation path schematically shown by an arrow H1inFIG. 8, and heat produced in the semiconductor chip2flows directly downward from the semiconductor chip2and flows through the die pad103and the sealing resin part107, and then, flows into the packaging substrate PWB through the air from the bottom surface of the sealing resin part107. Then the heat that has flowed into the packaging substrate PWB is further dissipated in the planar direction within the packaging substrate PWB and dissipated into the air from the packaging substrate PWB.

The second heat dissipation path is a heat dissipation path schematically shown by an arrow H2inFIG. 8, and heat produced in the semiconductor chip2flows from the peripheral part of the semiconductor chip2into the inner lead part of the lead104via the bonding wire105and the sealing resin part107, and then flows into the packaging substrate PWB along the outer lead part of the lead104. Then, the heat that has flowed into the packaging substrate PWB is further dissipated in the planar direction within the packaging substrate PWB and dissipates into the air from the packaging substrate PWB.

The third heat dissipation path is a heat dissipation path schematically shown by an arrow H3inFIG. 8, and heat produced in the semiconductor chip2flows directly upward from the semiconductor chip2and is dissipated into the air from the top surface of the sealing resin part107via the sealing resin part107.

In the case where the general QFP type semiconductor device101is packaged in a general manner, such as one in which a heat dissipating fin etc. is not provide on the top surface thereof, as shown inFIG. 8, heat dissipation through the first and second heat dissipation paths is predominant. For example, in the QFP in which one side of the sealing resin part107has a length of 20 mm, the above-mentioned first heat dissipation path (heat dissipation path shown by the arrow H1inFIG. 8) accounts for about 50% of the total amount of heat dissipation, the above-mentioned second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8) about 45% of the total amount of heat dissipation, and the above-mentioned third heat dissipation path (heat dissipation path shown by the arrow H3inFIG. 8) about 5% of the total amount of heat dissipation.

As the functions of an LSI are improved and its operation speed is increased, the power consumption of the semiconductor chip in the package increases and for a recent semiconductor package whose amount of produced heat tends to increase, it is demanded to improve the heat dissipation characteristics to dissipate heat produced in the semiconductor chip in the package to the outside of the semiconductor package. In order to improve the heat dissipation characteristics, it can be conceived to expose the bottom surface of the die pad103that mounts the semiconductor chip102from the bottom surface of the sealing resin part107, and thereby, the heat dissipation through the first heat dissipation path is improved and thus the heat dissipation characteristics of the semiconductor device101can be improved. However, when the bottom surface of the die pad103is exposed from the bottom surface of the sealing resin part107, there is a possibility that moisture (water) etc. may reach the semiconductor chip102through the boundary surface between the die pad103exposed at the bottom surface of the sealing resin part107and the sealing resin part107in a high-temperature and high-humidity load test and there is a risk that the reliability (moisture resistance) of a semiconductor device is degraded. Because of this, it is desirable that the die pad103be not exposed at the bottom surface of the sealing resin part107from the standpoint of improvement of the reliability (moisture resistance) of a semiconductor device.

Because of the above, in the present embodiment, the heat dissipating plate6is provided inside the sealing resin part7in order to improve the heat dissipation characteristics without exposing the back surface of the die pad103. Its working for the first heat dissipation path is to improve the heat dissipation characteristics by increasing the sectional area of the heat dissipation path by causing heat produced in the semiconductor chip2to flow downward after once spreading the heat in the heat dissipating plate6.

For the second heat dissipation path, the heat dissipation characteristics are improved by providing the heat dissipating plate6between the chip2and the tip end of the inner lead4to reduce the resistance of heat flow from the side of the semiconductor chip2to the inner lead4a. This will be explained later in detail.

<About Structure of Die Pad in Comparative Example>

FIG. 9is a plan perspective view of essential parts when a die pad103ain a first comparative example the inventors of the present invention have examined is applied as the die pad103in the semiconductor device101.FIG. 10is a plan perspective view of essential parts when a die pad103bin a second comparative example the inventors of the present invention have examined is applied,FIG. 11is that when a die pad103cin a third comparative example the inventors of the present invention have examined is applied, andFIG. 12is that when a die pad103din a fourth comparative example the inventors of the present invention have examined is applied.FIG. 9toFIG. 12correspond toFIG. 5in the present embodiment. As inFIG. 5, the position where the semiconductor chip102is mounted (arranged) is indicated by a dotted line also inFIG. 9toFIG. 12. InFIG. 9toFIG. 12, symbol110denotes a suspension lead, provided in order to hold the die pads103ato103dto the lead frame when manufacturing the semiconductor device101.

FIG. 9toFIG. 12are each a plan perspective view when the sealing resin part107, the semiconductor chip102, and the bonding wire105are viewed perspectively, and therefore, the sealing resin part107or the bonding wire105is not shown schematically inFIG. 9toFIG. 12. However, in the semiconductor device, as can also be seen fromFIG. 8, the die pads103ato103d, the semiconductor chip102, the suspension lead110, and the lead4(also including the bonding wire105that couples the electrode of the semiconductor chip102and the lead104) shown inFIG. 9toFIG. 12are sealed by the sealing resin part107.

As shown inFIG. 9, the die pad103ain the first comparative example has plane dimensions greater than the plane dimensions of the semiconductor chip102. Because of this, the entire back surface of the semiconductor chip102is bonded to the top surface of the die pad103awith a die bond material (adhesive).

However, when the entire back surface of the semiconductor chip102is bonded to the top surface of the die pad103awith a die bond material, the semiconductor chip102becomes more likely to be peeled off from the die pad103aat the time of solder reflow when packaging the semiconductor device101on the packaging substrate PWB, and therefore, the reliability (solder reflow resistance) of the semiconductor device is degraded. This results mainly from that the strength of the die bond material itself is low and that the strength of adhesion between the sealing resin part107and the die pad103ais low.

The plane dimensions of the die pad103bin the second comparative example shown inFIG. 10are less than the plane dimensions of the semiconductor chip102. Because of this, if the semiconductor chip102is mounted over the die pad103b, the center part of the back surface of the semiconductor chip102is bonded to the top surface of the die pad103bwith a die bond material (adhesive), however, to the region of the back surface of the semiconductor chip102, which is not in opposition to the die pad103, the sealing resin part107is bonded as a result. The strength of adhesion between the back surface of the semiconductor chip102and the sealing resin part107is far higher than the strength of adhesion between the sealing resin part107and the die pad103b. Because of this, compared to the case where the die pad103ain the first comparative example inFIG. 9is used, in the case where the die pad103bin the second comparative example inFIG. 10is used, it is possible to prevent the semiconductor chip102from peeling off from the die pad103bat the time of solder reflow when packaging the semiconductor device101on the packaging substrate PWB by the firm adhesion of the part of the back surface of the semiconductor chip102to the sealing resin part107. Consequently, it is possible to improve the reliability (solder reflow resistance) of the semiconductor device101.

The plane figure of the die pad103cin the third comparative example shown inFIG. 11is a frame and an opening111ais formed in the center part. Because of this, if the semiconductor chip102is mounted over the die pad103c, the peripheral part of the back surface of the semiconductor chip102is bonded to the top surface of the die pad103cwith a die bond material (adhesive), however, the center part of the back surface of the semiconductor chip102is exposed from the opening111aof the die pad103cand the sealing resin part107is bonded thereto. Because of this, as in the case where the die pad103bin the second comparative example inFIG. 10is used, in the case also where the die pad103cin the third comparative example inFIG. 11is used, it is possible to prevent the semiconductor chip102from peeling off from the die pad103bat the time of solder reflow when packaging the semiconductor device101on the packaging substrate PWB by the firm adhesion of the part of the back surface of the semiconductor chip102to the sealing resin part107, and therefore, it is possible to improve the reliability of the semiconductor device101.

However, over the die pad103cin the third comparative example, only the semiconductor chip102can be mounted, the plane dimensions of which are greater than the plane dimensions of the opening111a. This is because if the semiconductor chip102is smaller than the opening111aof the die pad103c, it will drop from the opening111a. Because of this, when the die pad103cin the third comparative example is used, there are limitations to the plane dimensions of the semiconductor chip102that can be mounted and it is no longer possible to use a common lead frame for the semiconductor chip102of different plane dimensions. That is, it is necessary to change the plane dimensions of the die pad103cfor each of the semiconductor chips102of different plane dimensions, resulting in a disadvantage in reducing the cost of the semiconductor device.

On the other hand, in the case of the die pad103bin the second comparative example shown inFIG. 10, the semiconductor chips102of various dimensions can be mounted over the die pad103b, and therefore, it is possible to use a common lead frame for the semiconductor chips102of different plane dimensions, and therefore, an attempt can be made to reduce the cost of the semiconductor device. However, in the case of the die pad103bin the second comparative example shown inFIG. 10, when the plane dimensions of the semiconductor chip102to be mounted are reduced, the space between the semiconductor chip102and the lead104increases, resulting in a disadvantage in dissipating heat through the second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8). Then, the die pad103bin the second comparative example shown inFIG. 10has a large space between the die pad103band the lead104and a structure in which heat is hard to conduct from the die pad103bto the lead104because the die pad103bis small in size, and therefore, the die pad103can hardly contribute in heat dissipation through the second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8).

Like the die pad103cin the third comparative example shown inFIG. 11, the plane figure of the die pad103din the fourth comparative example shown inFIG. 12is a frame and the opening111ais provided in the center part, however, compared to the die pad103cin the third comparative example, the outer edge side of the die pad103dis widened so as to come close to the lead part104. In the die pad103din the fourth comparative example inFIG. 12, a slit111bis provided at a position where it does not overlap the semiconductor chip102. As described above, there is a risk that the boundary surface peels off at the time of solder reflow because of the low adhesion strength between the top surface of the die pad103dand the sealing resin part107. In the fourth comparative example, the width of the die pad103dis greater than that in the third comparative example, and therefore, if a peeling occurs, it develops into a crack of the sealing resin part107and there is a risk that the wire is cut. Because of this, the slit111bis provided to confine a peeling to a small area even if it occurs and to prevent it from developing into a crack.

Compared to the case where the die pad103cin the third comparative example inFIG. 11is used, in the case where the die pad103din the fourth comparative example inFIG. 12is used, the distance from the outer edge of the die pad103dto the tip end of the inner lead part of the lead104is reduced, and therefore, heat produced in the semiconductor chip102can be easily conducted to the inner lead part of the lead104via the die pad103d. Consequently, this is an advantage in heat dissipation through the second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8). However, like the die pad103cin the third comparative example inFIG. 11, also in the case of the die pad103din the fourth comparative example inFIG. 12, there are limitations to the plane dimensions of the semiconductor chip102that can be mounted, and it is no longer possible to use a common lead frame for the semiconductor chips102of different plane dimensions. That is, it is necessary to change the plane dimensions of the die pad103dfor each of the semiconductor chips102of different plane dimensions, resulting in a disadvantage in reducing the cost of the semiconductor device.

The characteristics of the die pad structure in the comparative examples shown inFIG. 9toFIG. 12are explained as above. In contrast to these comparative examples, in the semiconductor device1in the present embodiment, the die pad3is arranged immediately under the center part of the back surface2bof the semiconductor chip2. That is, the center part of the semiconductor chip2overlaps the die pad3in a planar manner. In other words, the center part of the back surface2bof the semiconductor chip2is located immediately over the die pad3.

Because of this, it is possible to mount the semiconductor chips2of various dimensions over the die pad3.FIG. 13andFIG. 14are each a partially enlarged plan perspective view of the semiconductor device1in the present embodiment, corresponding toFIG. 5described above, andFIG. 13corresponds to the case where the semiconductor chip2to be mounted is small andFIG. 14corresponds to the case where the semiconductor chip2to be mounted is large. LikeFIG. 5described above, inFIG. 13andFIG. 14also, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line, however, unlikeFIG. 5, inFIG. 13andFIG. 14, the region in which the adhesive8is arranged (applied) is hatched. A difference betweenFIG. 5andFIG. 14lies only in that the region in which the adhesive8is arranged (applied) is hatched inFIG. 14and the size of the semiconductor chip2is the same in bothFIG. 5andFIG. 14. A difference betweenFIG. 13andFIG. 14lies in the plane dimensions (outer size) of the semiconductor chip2and the plane dimensions of the semiconductor chip2inFIG. 14are greater than those inFIG. 13.

As can also be seen fromFIG. 13andFIG. 14, it is possible to hold (support) the semiconductor chip2by the die pad3(and the member9) even if the plane dimensions of the semiconductor chip2are different. This is because it is possible to mount the semiconductor chip2so that the die pad3is arranged immediately under the center part of the back surface2bof the semiconductor chip2when the semiconductor chip2is small as shown inFIG. 13and when the semiconductor chip2is large as shown inFIG. 14. Because of this, it is possible to mount the semiconductor chips2of various plane dimensions over the die pad3. Consequently, it is possible to make an attempt to reduce the cost of a semiconductor device because a common lead frame can be used for the semiconductor chips2of various plane dimensions.

Further, in the present embodiment, the plane dimensions of the die pad3are made smaller than the plane dimensions of the semiconductor chip2. Because of this, the part of the back surface2bof the semiconductor chip2mounted over the die pad3, which is in opposition to the die pad3and the member9, is bonded to the die pad3and the member9via the adhesive8, however, there is a part of the back surface2bof the semiconductor chip2, which is in opposition to neither the die pad3nor the member9, and the sealing resin part7is bonded thereto. That is, at least part of the back surface2bof the semiconductor chip2is in opposition to neither the die pad3nor the member9and the sealing resin part7is bonded thereto in opposition to the sealing resin part7, and this also applies to second to ninth embodiments to be described later, not only to the present embodiment. Because of this, compared to the case where the die pad103ain the first comparative example inFIG. 9is used, in the present embodiment, it is possible to prevent the semiconductor chip102from peeling off from the die pad103band the member9at the time of solder reflow when packaging the semiconductor device1on the packaging substrate PWB by the firm adhesion of (the part of the back surface2bin opposition to neither the die pad3nor the member9) the back surface2bof the semiconductor chip2to the sealing resin part107. Consequently, it is possible to improve the reliability (solder reflow resistance) of the semiconductor device1.

Further, in the present embodiment, the heat dissipating plate6is provided in order to improve the heat dissipation characteristics of the semiconductor device1. As a result, it is possible to improve the heat dissipation characteristics through the first heat dissipation path (heat dissipation path shown by the arrow H1inFIG. 8) by once diffusing the heat produced in the semiconductor chip2to the heat dissipating plate6. It is also possible to improve the heat dissipation characteristics through the second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8) by conducting the heat in the semiconductor chip2to the inner lead part4aof the lead4. This is explained with reference toFIG. 15andFIG. 16.

FIG. 15is an explanatory diagram of heat dissipation of the semiconductor device1in the present embodiment and an enlarged view of the region corresponding to the region shown by symbol RG1inFIG. 6is shown. InFIG. 15, a sealing resin part16is not shown schematically.FIG. 16is an explanatory diagram of heat dissipation when the back surface2bof the semiconductor chip2is bonded to the die pad3with the adhesive8but not bonded to the member9with the adhesive8, unlike the present embodiment, and the same region as that inFIG. 15is shown. InFIG. 15andFIG. 16, how heat produced in the semiconductor chip2flows to the heat dissipating plate6is schematically shown by an arrow H4.

In the present embodiment, as can also be seen fromFIG. 6,FIG. 7, andFIG. 13toFIG. 15, the semiconductor chip2is mounted over the die pad3and the member9and the entire surface of the part of the back surface2bof the semiconductor chip2, which is in opposition to (the top surface3aof) the die pad3and the member9, is bonded to the die pad3and the member9with the adhesive8. Because of this, as shown schematically inFIG. 15, heat produced in the semiconductor chip2is conducted mainly from the back surface2bof the semiconductor chip2to the die pad3and the member9through the adhesive8and is further conducted to the heat dissipating plate6via the member9. Heat conducted from the member9to the heat dissipating plate6spreads over the entire heat dissipating plate6in the form of a frame. Because the heat conduction path from the back surface2bof the semiconductor chip2to the heat dissipating plate6does not pass byway of the sealing resin part7the thermal conductivity of which is low, it is possible to efficiently conduct heat produced in the semiconductor chip2to the heat dissipating plate6. Part of heat having spread over the entire heat dissipating plate6is conducted downward from the bottom surface6bof the heat dissipating plate6and flows into the packaging substrate (PWB) (the packaging substrate PWB that has packaged the semiconductor device1) from the bottom surface7bof the sealing resin part7via a thin air layer thereunder. Because of this, as to the first heat dissipation path, its sectional area is the sum of the area of the semiconductor chip2, the area of the heat dissipating plate6, and the area of the part of the member9, which does not overlap the semiconductor chip2in a planar manner. Further, part of heat having spread over the entire heat dissipating plate6is conducted to the inner lead part4aof the lead4via the sealing resin part7interposed between the heat dissipating plate6and the inner lead part4a. Heat conducted from the heat dissipating plate6to the inner lead part4aflows into the packaging substrate PWB (the packaging substrate PWB that has packaged the semiconductor device1) through the outer lead part4aof the lead4.

Unlike the present embodiment, in the second comparative example inFIG. 10described above, in which nothing corresponding to the heat dissipating plate6is provided, there is nothing corresponding to the heat dissipating plate6, and therefore, the sectional area of the first heat dissipation path is limited approximately only to the area of the semiconductor chip2and the heat dissipation performance is low. As the second heat dissipation path described above (heat dissipation path shown by the arrow H2inFIG. 8), there are only a path through which heat is dissipated from the side surface of the semiconductor chip2to the inner lead part of the lead104via the sealing resin part107and a path through which heat is dissipated from the electrode PD over the semiconductor chip2to the inner lead part of the lead104via the bonding wire5, and therefore, the heat dissipation characteristics are low and if the semiconductor chip2is reduced in size, the heat dissipation characteristics are further deteriorated.

In contrast to the above, in the present embodiment, the sectional area of the first heat dissipation path described above (heat dissipation path shown by the arrow H1inFIG. 8) is the sum of the area of the semiconductor chip2, the area of the heat dissipating plate6, and the area of the part of the member9, which does not overlap the semiconductor chip2in a planar manner. As the second heat dissipation path described above (heat dissipation path shown by the arrow H2inFIG. 8), in addition to a path through which heat is dissipated from the side surface of the semiconductor chip2to the inner lead part4avia the sealing resin part7, a path can be used to dissipate heat in the semiconductor chip2, through which heat is dissipated from the back surface2bof the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member9and the heat is further dissipated from the heat dissipating plate6to the inner lead part4avia the sealing resin part7. Because of this, it is possible to improve the heat dissipation characteristics of the semiconductor device1.

As the plane dimensions of the semiconductor chip2become smaller, the sectional area of the first heat dissipation path, that is, the area of the semiconductor chip2becomes smaller, and therefore, the heat dissipation performance is deteriorated. Further, as to the second heat dissipation path, the distance from the side surface of the semiconductor chip2to the tip end of the inner lead part4abecomes larger and heat dissipation from the side surface of the semiconductor chip2to the inner lead part4avia the sealing resin part7becomes less efficient. However, in the present embodiment, the heat dissipating plate6is provided and the sectional area of the first heat dissipation path is the sum of the area of the semiconductor chip2, the area of the heat dissipating plate6, and the area of the part of the member9, which does not overlap the semiconductor chip2in a planar manner, and therefore, it is possible to suppress the deterioration of the heat dissipation characteristics. As to the second heat dissipation path, even if the semiconductor chip2to be mounted becomes smaller, the distance between the heat dissipating plate6and the inner lead part4aremains unchanged. Because of this, as shown inFIG. 13, even when the plane dimensions of the semiconductor chip2to be mounted are small, heat can be dissipated from the back surface2bof the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member9, and the heat can be further dissipated from the heat dissipating plate6to the inner lead part4avia the sealing resin part7, and therefore, it is possible to suppress the deterioration of the heat dissipation characteristics accompanying the downsizing of the semiconductor chip2to be mounted.

On the other hand, in the case ofFIG. 16, the semiconductor chip2is arranged over the die pad3and the member9, however, while the part of the back surface2bof the semiconductor chip2, which is in opposition to the die pad3, is bonded to the die pad3with the adhesive8, the part of the back surface2bof the semiconductor chip2, which is in opposition to the member9, is not bonded to the member9with the adhesive8. That is, the member9and the back surface2bof the semiconductor chip2are not bonded to each other with the adhesive8. Because of this, a state is brought about where a void is formed between the back surface2bof the semiconductor chip2and the top surface of the member9, or the material of the sealing resin part7is interposed therebetween. That is,FIG. 16corresponds to a structure in which the back surface2bof the semiconductor chip2is bonded only to the die pad3with the adhesive8(that is, the back surface2bis not bonded to the member9with the adhesive8).

As shown inFIG. 16, when the back surface2bof the semiconductor chip2is bonded only to the die pad3with the adhesive8, heat produced in the end part (peripheral part) of the semiconductor chip2is conducted from the center part of the back surface2bof the semiconductor chip2to the die pad3through the adhesive8after the heat is made to skirt (conduct) in the direction of the center part side of the semiconductor chip2in the semiconductor chip2as shown schematically by the flow of the heat by the arrow H4, and then, is conducted to the heat dissipating plate6via the member9. Because of this, the length of the heat dissipation path from the semiconductor chip2to the heat dissipating plate6becomes longer compared to the case ofFIG. 15, and therefore, the heat dissipation characteristics are deteriorated. Further, when the back surface2bof the semiconductor chip2is bonded only to the die pad3with the adhesive8as shown inFIG. 16, a void exists between the back surface2bof the semiconductor chip2and the top surface of the member9or the material of the sealing resin part7is interposed therebetween. The thermal conductivity of the void and the thermal conductivity of the material of the sealing resin part7are lower than the thermal conductivity of the adhesive8, and therefore, the heat dissipation efficiency of the heat dissipation path (heat dissipation path shown by an arrow H5inFIG. 16) from the back surface2bof the semiconductor chip2to the member9via the void or the material of the sealing resin part7is very low.

In contrast to the above, in the present embodiment, as shown inFIG. 6,FIG. 7andFIG. 13toFIG. 15, the entire surface of the part of the back surface2bof the semiconductor chip2, which is in opposition to the die pad3and the member9, is bonded to the die pad3and the member9with the adhesive8. In other words, the semiconductor chip2is mounted over the die pad3and the members9and the top surface3aof the die pad3and the top surface3aof the part of the members9, which is in opposition to the back surface2bof the semiconductor chip2, are bonded to the back surface2bof the semiconductor chip2in their entire surfaces with the adhesive8. Because of this, as shown schematically by the flow of heat by the arrow H4inFIG. 16, the heat produced in the end part (peripheral part) of the semiconductor chip2can also be conducted to the member9located immediately thereunder via the adhesive8the thermal conductivity of which is higher than that of the sealing resin part7. Because of this, the heat dissipation path from the semiconductor chip2to the heat dissipating plate6becomes shorter compared to the case ofFIG. 15, and therefore, it is possible to improve the heat dissipation characteristics.

As described above, in the present embodiment, what is important is that the top surface3aof the die pad3and the top surface3aof the part of the members9, which is in opposition to the back surface2bof the semiconductor chip2, are bonded to the back surface2bof the semiconductor chip2in their entire surfaces with the adhesive8, and this also applies to second to ninth embodiment, to be described later.

By the provision of the heat dissipating plate6, the heat dissipation path from the back surface2bof the semiconductor chip2to the inner lead part4avia the adhesive8, the die pad3, the member9, and the heat dissipating plate6becomes effective for the first time, and without the heat dissipating plate6itself, there arises no trouble even if the back surface2bof the semiconductor chip2is bonded only to the die pad3with the adhesive8. Because of this, it can be said that the technique to bond the entire surface of the part of the back surface2bof the semiconductor chip2, which is in opposition to the die pad3and the member9, to the die pad3and the member9with the adhesive is a technique that is not necessary until the heat dissipating plate6is provided.

Further, it is necessary for the thermal conductivity of the adhesive8to be higher than at least the thermal conductivity of the sealing resin part7, however, preferably, the thermal conductivity of the adhesive8is as high as possible. Because of this, it is possible to use a silver paste preferably as the adhesive8and due to this, it is possible to increase the thermal conductivity of the adhesive8, for example, as high as five to six times the thermal conductivity of the sealing resin part7. As a silver paste used as the adhesive8, an epoxy resin-based adhesive containing a silver (Ag) filler etc. can be used.

Preferably, the die pad3is located in the center of the region surrounded by the heat dissipating plate6in the form of a frame, and due to this, it is possible to surround the semiconductor chip2mounted so that the die pad3is located immediately under the center part of the back surface2bof the semiconductor chip2by the heat dissipating plate6in the form of a frame in a planar, well-balanced manner, and therefore, it is possible to magnify the effect to improve the heat dissipation characteristics due to the provision of the heat dissipating plate6.

Further, the semiconductor chip2is mounted over the die pad3and the member9, and therefore, it is possible to regard the combination of the die pad3and the member9as a chip mounting part. In this case, it is possible to regard the heat dissipating plate6as the frame body part arranged so as to surround the chip mounting part (combination of the die pad3and the member9) instead of the chip mounting part.

In another view, it is possible to regard the heat dissipating plate6also as the chip mounting part, not only the die pad3and the member9, because the die pad3, the member9, and the heat dissipating plate6are integrally formed. That is, as assigned a symbol inFIG. 13andFIG. 14, it is also possible to regard the whole of the combination of the die pad3, the member9, and the heat dissipating plate6as a chip mounting part12. In the chip mounting part12, a plurality of openings13surrounded by the heat dissipating plate6, the member9, and the die pad3is formed. The outer edge (corresponding to the outer edge6dof the heat dissipating plate6) of the chip mounting part12is located outside the outer circumference of the semiconductor chip2. Each of the openings13of the chip mounting part12is an opening and penetrates through from the top surface of the chip mounting part12to the bottom surface of the chip mounting part12. Here, the top surface of the semiconductor chip2includes the top surface3aof the die pad3and the member9and the top surface6aof the heat dissipating plate6and the bottom surface of the chip mounting part12includes the bottom surface3bof the die pad3and the member9and the bottom surface6bof the heat dissipating plate6. The entire surface of the region of the top surface of the chip mounting part12, which is in opposition to the back surface2bof the semiconductor chip2and in which the opening13is not formed, is bonded to the back surface2bof the semiconductor chip2with the adhesive8. In the chip mounting part12, immediately under the center part of the semiconductor chip2, the opening13is not arranged because the die pad3is arranged immediately under the center part of the semiconductor chip2.

Unlike the present embodiment,FIG. 17is a plan perspective view (partially enlarged plan perspective view) of essential parts of a semiconductor device when a semiconductor chip202, the plane dimensions of which are further increased than those of the semiconductor chip2, is mounted instead of the semiconductor chip2in the present invention, corresponding toFIG. 5. LikeFIG. 5, inFIG. 17also, the position where the semiconductor chip202is mounted (arranged) is indicated by a dotted line.

In the case ofFIG. 17, unlike the present embodiment, the inner edge6cof the heat dissipating plate6is located immediately under the semiconductor chip2and the entire outer circumference of the semiconductor chip2overlaps the heat dissipating plate6in a planar view. That is, in the case ofFIG. 17, the state is such that the entire region of the opening13when the total combination of the heat dissipating plate6, the member9, and the die pad3is regarded as the chip mounting part12is covered by the semiconductor chip2in a planar manner. In other words, in the case ofFIG. 17, the state is such that the opening13is included by the semiconductor chip2in a planar manner.

As shown inFIG. 17, when the opening13is included by the semiconductor chip2in a planar manner, in a molding step of forming the sealing resin part7(resin sealing step), the state is such that the opening13is covered with the lid by the semiconductor chip2, and therefore, when the mold resin (resin material of the sealing resin part7) flows into the opening13, a void is likely to be produced. Because of this, in a manufactured semiconductor device, a void is likely to be produced in the sealing resin part7within the opening13(under the semiconductor chip202), and because a void acts to deteriorate the reliability of a semiconductor device, and therefore, it is unacceptable from the standpoint of the reliability of a semiconductor device.

In contrast to the above, in the present embodiment, as shown inFIG. 13andFIG. 14, the outer circumference of the semiconductor chip2is located between the inner edge6cof the heat dissipating plate6and the die pad3and the outer circumference of the semiconductor chip2does not overlap the heat dissipating plate6in a planar view. In another view (a view in which the total combination of the die pad3, the member9, and the heat dissipating plate6is regarded as the chip mounting part12), the opening13has a part that overlaps the semiconductor chip2in a planar manner and a part that does not overlap in a planar manner. That is, each opening13is in a state where a part is covered by the semiconductor chip2in a planar manner, however, the other part is not covered by the semiconductor chip2in a planar manner.

Because of this, in the present embodiment, in the molding step (resin sealing step) of forming the sealing resin part7, even when the mold resin (resin material of the sealing resin part7) enters the opening13, it is possible for the mold resin to flow upward and downward from the chip mounting part12in the opening13of the part not covered by the semiconductor chip2, and therefore, it is possible to suppress or prevent a void from occurring in the sealing resin part7within the opening13. As a result, it is possible to improve the reliability of the semiconductor device1.

Consequently, in the present embodiment, it is possible to manufacture the semiconductor device1using a common lead frame (lead frame having the die pad3, the member9, the heat dissipating plate6, the suspension lead10, and the lead4) for the semiconductor chips2of different plane dimensions, however, it is necessary to create a design as follows.

That is, when there is a possibility that a plurality of kinds of the semiconductor chips2of different plane dimensions may be mounted, the plane dimensions of the die pad3are made smaller than the plane dimensions of the semiconductor chip2of the minimum dimensions that has a possibility of being mounted. As a result, even when the semiconductor chip2of the minimum dimensions is bonded over the die pad3and the member9with the adhesive8, part of the back surface2bof the semiconductor chip2can be bonded to the sealing resin part7without opposing the die pad3or the member9. With the arrangement, as described above, it is possible to prevent the semiconductor chip2from peeling off from the die pad3or the member9at the time of solder reflow when packaging the semiconductor device1on the packaging substrate PWB, as described above, and therefore, it is possible to improve the reliability (solder reflow resistance) of the semiconductor device1.

Further, when there is a possibility that a plurality of kinds of the semiconductor chips2of different plane dimensions may be mounted, the inner edge6cof the heat dissipating plate6is made to be located outside the position of the outer circumference of the semiconductor chip2of the maximum dimensions having a possibility of being mounted. That is, even when the semiconductor chip2of the maximum dimensions having a possibility of being mounted is mounted, the outer circumference of the semiconductor chip2is made to be located between the inner edge6cof the heat dissipating plate6and the die pad3in a planar view (the outer circumference of the semiconductor chip2does not overlap the heat dissipating plate6in a planar view). In other words, even when the semiconductor chip2of the maximum dimensions having a possibility of being mounted is mounted, it is required to bring about a state where part of the opening13is covered by the semiconductor chip2in a planar manner, however, the other part is not covered by the semiconductor chip2in a planar manner. As a result, it is possible to suppress or prevent a void from occurring in the sealing resin part7under the semiconductor chip2, and therefore, it is possible to improve the reliability of the semiconductor device1.

Further, it is preferable for the space between the outer circumference of the semiconductor chip2and the inner edge6cof the heat dissipating plate6to be designed by taking into consideration the mounting position precision of the semiconductor chip in a die boding step. That is, preferably, even when the semiconductor chip2of the maximum dimensions having a possibility of being mounted is mounted and a certain amount of shift is caused in the mounting position of the semiconductor chip resulting from the boding device etc., the outer circumference of the semiconductor chip2is made to be located between the inner edge6cof the heat dissipating plate6and the die pad3in a planar view (the outer circumference of the semiconductor chip2does not overlap the heat dissipating plate6in a planar view). From this standpoint, it is possible to design the inner edge6cof the heat dissipating plate6so that the space between the outer circumference of the semiconductor chip2and the inner edge6cof the heat dissipating plate6is, for example, about 0.1 mm in a planar view when the semiconductor chip2of the maximum dimensions having a possibility of being mounted is mounted.

According to the experiment conducted by the inventors of the present invention, the thermal resistance of the semiconductor device101, to which the second comparative example inFIG. 10in which nothing corresponding to the heat dissipating plate6was not provided was applied, was 41° C./W (when the heat generation of the semiconductor chip102is 1 W, the rise in temperature of the semiconductor chip102is 41° C. from the ambient temperature). In contrast to this, in the semiconductor device1in the present embodiment, the thermal resistance was 35.4° C. (when the heat generation of the semiconductor chip2is 1 W, the rise in temperature of the semiconductor chip2is 35.4° C. from the ambient temperature). According to the present embodiment, as described above, it is possible to improve the heat dissipation characteristics (that is, to reduce the thermal resistance) of a semiconductor device.

Second Embodiment

FIG. 18is a plan perspective view (top view) of semiconductor device1ain the present embodiment, showing a plan perspective view of the semiconductor device1awhen the sealing resin part7is viewed perspectively.FIG. 19is a partially enlarged view (partially enlarged plan perspective view) ofFIG. 18, showing an enlarged view of the part in the vicinity of the center part inFIG. 19(the semiconductor chip2and the region in the vicinity thereof).FIG. 20is a plan perspective view (partially enlarged plan perspective view) of the semiconductor device1awhen the semiconductor chip2and the bonding wire5are removed (viewed perspectively) inFIG. 19.FIG. 18,FIG. 19, andFIG. 20correspond toFIG. 3,FIG. 4, andFIG. 5in the first embodiment, respectively. As inFIG. 5, inFIG. 20, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line for easier understanding.FIG. 21toFIG. 23are each a section view (side section view) of the semiconductor device1ain the present embodiment and the section view of the position along A2-A2line inFIG. 18substantially corresponds toFIG. 21, the section view of the position along B2-B2inFIG. 18substantially corresponds toFIG. 22, and the section view of the position along C2-C2inFIG. 18substantially corresponds toFIG. 23. For easier understanding, inFIG. 20also, the positions corresponding to the A2-A2line, the B2-B2line, and the C2-C2line inFIG. 18are assigned the A2-A2line, the B2-B2line, and the C2-C2line, however, while only part of the semiconductor device1ais shown inFIG. 20,FIG. 21toFIG. 23are each a section view of the entire semiconductor device1a(the entire region shown inFIG. 18).FIG. 24andFIG. 25are each a partially enlarged plan perspective view of the semiconductor device1in the present embodiment, whereinFIG. 24corresponds to the case where the semiconductor chip2to be mounted is small andFIG. 25corresponds to the case where the semiconductor chip2to be mounted is large, corresponding toFIG. 13andFIG. 14, respectively. As inFIG. 13andFIG. 14, inFIG. 24andFIG. 25also, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line and the region where the adhesive8is arranged (applied) is hatched by dots. The size of the semiconductor chip2is the same both inFIG. 20and inFIG. 25, however, the plane dimensions of the semiconductor chip2inFIG. 24are smaller than those inFIG. 25. Because the top view and the bottom view of the semiconductor device1ain the present embodiment are the same as the top view and the bottom view in the first embodiment, and therefore, they are not shown schematically here.

A structure of the semiconductor device1ain the present embodiment shown inFIG. 18toFIG. 25is explained, the points different from the semiconductor device1in the first embodiment being focused on.

As can also be seen fromFIG. 20, in the semiconductor device1ain the present embodiment shown inFIG. 18toFIG. 23, the direction in which each member9that connects the die pad3and the inner edge6cof the heat dissipating plate6extends is the X direction and the Y direction. That is, the four members9are provide in total, the two members9extending in opposite directions from the die pad3and parallel with the X direction and the other two members9extending in opposite directions from the die pad3and parallel with the Y direction. The four sides (sides SD1to SD4) of the sealing resin part7in the shape of a plane rectangle include the two sides (sides SD2, SD4) in parallel with the X direction and the other two sides (sides SD1, SD3) parallel with the Y direction, and therefore, the direction in which each member9extends is perpendicular to each side (of the sides SD1to SD4) of the sealing resin part7in the shape of a plane rectangle.

From another viewpoint, in the semiconductor device1ain the present embodiment, the heat dissipating plate6in the form of a frame has four sides respectively along the four sides of the semiconductor chip2in the shape of a plane rectangle, and the center part of each side of the heat dissipating plate6and the die pad3are connected by the member9. That is, the four members9are provided and the position in the inner edge6cof the heat dissipating plate6, where the member9is linked, is each center part of the four sides of the heat dissipating plate6. More specifically, each side of the heat dissipating plate6in the form of a frame extends in the X direction and Y direction, and to the center part of the side of the heat dissipating plate6extending in the X direction, the member9extending in the Y direction is connected, and to the center part of the side of the heat dissipating plate6extending in the Y direction, the member9extending in the X direction is connected.

In this manner, it is possible to connect the die pad3and the heat dissipating plate6with the member9by the shortest distance. That is, when the position and the shape of the die pad3and the heat dissipating plate6are the same, if the case where the four corners of the heat dissipating plate6and the die pad3are connected with the member9as in the first embodiment is compared with the case where each of the center parts of the four sides of the heat dissipating plate6and the die pad3are connected with the member9as in the present embodiment, it is possible to reduce the length of the member9more in the present embodiment. Here, the length of the member9corresponds to the length in the direction parallel with the direction in which the member9extends from the die pad3toward the heat dissipating plate6.

Because it is possible to reduce the length of the member9in the present embodiment, the thermal resistance can be reduced when heat in the semiconductor chip2diffuses from the back surface2bof the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member9, and therefore, it is possible to further improve the heat dissipation characteristics of the semiconductor device.

In the semiconductor device1aof the present embodiment, the width (width or distance from the outer edge6dto the inner edge6c) of the heat dissipating plate6is greater at each center part of the four sides of the heat dissipating plate6than at the part other than the center parts. That is, as to the width (width from the outer edge6dto the inner edge6c) of the heat dissipating plate6, the width (width from the outer edge6dto the inner edge6c) at each center part of the four sides of the heat dissipating plate6is greater than the width (width from the outer edge6dto the inner edge6c) at the part other than the center parts. In other words, each shape of the four sides of the heat dissipating plate6is such that the outer edge6dof the center part extends toward the direction in which the inner lead part4ais arranged. Then, the tip end of the inner lead part4aof the leads4is arranged along the outer edge6dof the heat dissipating plate6in a planar view.

From another viewpoint, it is possible to regard that each side of the heat dissipating plate6is a part sandwiched by the suspension leads10of the heat dissipating plate6because the suspension lead10is linked to each end part of the four sides (that is, each of the four corners) of the heat dissipating plate6in the form of a frame and each of the four sides of the heat dissipating plate6is sandwiched by the suspension leads10. Because of this, in the semiconductor device1ain the present embodiment, it can be said that the distance (width) from the outer edge6dto the inner edge6cof the part sandwiched by the suspension leads10(that is, each side of the heat dissipating plate6) is greater at the center part of the part sandwiched by the suspension leads10of the heat dissipating plate6(that is, each side of the heat dissipating plate6) than at the part other than the center part. It can also be said that the shape of the part sandwiched by the suspension leads10of the heat dissipating plate6(that is, each side of the heat dissipating plate6) is such that the outer edge6dof the center part extends toward the direction in which the inner lead4ais arranged. Then, in a planar view, the tip end of the inner lead part4aof the leads4is arranged along the outer edge6dof the heat dissipating plate6.

The inner lead parts4aand the electrodes PD of the semiconductor chip2are electrically coupled via the bonding wires5. In order to arrange and design the bonding wire so as to satisfy the restrictions on the processing of the wire bonding, it is effective to arrange the inner lead part4ato be wire-bonded to the electrode PD located at the center of the two sides of the semiconductor chip2so that its tip end is distant from the semiconductor chip2and to arrange the inner lead part4ato be wire-bonded to the electrode PD at a position distant from the center of the two sides of the semiconductor chip2so that its tip end is close to the semiconductor chip2. Further, in order to reduce the thermal resistance, it is effective to increase the width of the heat dissipating plate6, however, it is necessary to lay out the heat dissipating plate6so as not to overlap the lead4in a planar manner because of the restrictions on processing etc.

Because of the above, in the present embodiment, the tip end of the inner lead part4aof the leads4surrounding the semiconductor chip2is arranged at a position where the wire-bonding can be done easily, and a layout is designed so that the width of the heat dissipating plate6is as great as possible. That is, as described above, it is designed so that the width of the heat dissipating plate6is greater at each center part of the four sides of the heat dissipating plate6than at the part other than the center part, and the tip end of the inner lead part4aof the leads4is arranged along the outer edge6dof the heat dissipating plate6in a planar view. In other words, the shape of each of the four sides of the heat dissipating plate6is made to be such that the outer edge6dof the center part extends toward the direction in which the inner lead part4ais arranged and the tip end of the inner lead part4aof the leads4is arranged along the outer edge6dof the heat dissipating plate6in a planar view, and thereby, it is possible to obtain the easiness of wire-bonding and the effect of the further improvement of the heat dissipation characteristics (effect to reduce the thermal resistance) due to the increase in the width of the heat dissipating plate6.

Other configurations of the semiconductor1ain the present embodiment are the same as those of the semiconductor1in the first embodiment, and therefore, its explanation is omitted here.

According to the experiment conducted by the inventors of the present invention as described above, while the thermal resistance of the semiconductor device101, to which the second comparative example inFIG. 10in which nothing corresponding to the heat dissipating plate6was not provided was applied, was 41° C./W and the thermal resistance in the semiconductor device1in the first embodiment was 35.4° C., in the semiconductor device la in the present embodiment, the thermal resistance was 33.0° C./W (when the heat generation in the semiconductor chip2is 1 W, the rise in temperature of the semiconductor chip2is 33.0° C. from the ambient temperature). According to the present embodiment, as described above, it is possible to further improve the heat dissipation characteristics (that is, to further reduce the thermal resistance) of a semiconductor device.

Further, as in the first embodiment described above, in the present embodiment also, the top surface3aof the die pad3and the top surface3aof the part of the members9, which is in opposition to the back surface2bof the semiconductor chip2, are bonded to the back surface2bof the semiconductor chip2in their entire surfaces with the adhesive8regardless of the size of the semiconductor chip2to be mounted, as can also be seen fromFIG. 21toFIG. 25.

Furthermore, as in the first embodiment, in the present embodiment also, it is possible to regard the combination of the die pad3and the member9as the chip mounting part because the semiconductor chip2is mounted over the die pad3and the member9, and in this case, it is possible to regard the heat dissipating plate6as the frame body part arranged so as to surround the chip mounting part (combination of the die pad3and the member9), instead of the chip mounting part.

From another view different from that in the first embodiment described above, in the present embodiment also, the die pad3, the member9, and the heat dissipating plate6are formed integrally, and therefore, it is possible to regard the heat dissipating plate6as the chip mounting part, not only the die pad3and the member9. That is, as symbols are assigned inFIG. 24andFIG. 25, it is possible to regard the total combination of the die pad3, the member9, and the heat dissipating plate6as the chip mounting part12and in the chip mounting part12, a plurality of the openings13surrounded by the heat dissipating plate6, the member9, and the die pad3is formed. The outer edge (corresponding to the outer edge6dof the heat dissipating plate6) of the chip mounting part12is located outside the outer circumference of the semiconductor chip2and each opening13penetrates through from the top surface of the chip mounting part12to the bottom surface of the chip mounting part12. The region of the top surface of the chip mounting part12, which is in opposition to the back surface2bof the semiconductor chip2and in which the opening13is not formed, is bonded to the back surface2bof the semiconductor chip2in its entire surface with the adhesive8. In the chip mounting part12, the opening13is not arranged immediately under the center part of the semiconductor chip2, and this is because the die pad3is arranged immediately under the center part of the semiconductor chip2.

FIG. 26is a partially enlarged plan perspective view showing a modified example of the semiconductor device la in the present embodiment, corresponding toFIG. 25described above. The plane figure of the opening13is not limited to a rectangle, but another shape, for example, a circle as inFIG. 26may be acceptable.

That is, regardless of the shape of the opening13, each opening13has a part that overlaps the semiconductor chip2in a planar manner and a part that does not. That is, it is necessary for each opening13to be in a state where a part is covered by the semiconductor chip2in a planar manner but the other part is not covered by the semiconductor chip2in a planar manner regardless of the shape of the opening13. As a result, as explained in the first embodiment, in the molding step, when the mold resin enters the opening13, it is possible for the mold resin to flow both upward and downward from the chip mounting part12in the opening13of the part not covered by the semiconductor chip2, and therefore, it is possible to suppress or prevent avoid from occurring in the sealing resin part7in the opening13and thus the reliability of the semiconductor device can be improved.

Most preferably, the four corners of the semiconductor chip2in the shape of a plane rectangle do not overlap the chip mounting part12in a planar manner and are located over the opening13. That is, most preferably, the opening13is arranged over a plane so as to surround the corners of the semiconductor chip2. In other words, most preferably, the openings13are arranged so as to surround the corners of the semiconductor chip2in a planar view. As a result, the part that does not overlap the semiconductor chip2in a planar manner is not divided but continuous in each opening13, and therefore, when the mold resin enters the opening13, it is possible for the mold resin to flow smoothly both upward and downward from the opening13, and therefore, it becomes possible to appropriately prevent a void from forming. Further in the molding step, a void is likely to occur in the vicinity of the corner parts of the opening13corresponding to the four corners of the semiconductor chip2, however, if the four corners of the semiconductor chip2are arranged over the opening13, the part where a void is likely to occur can be released without being covered by the semiconductor chip2, and therefore, this arrangement is advantageous in preventing formation of a void.

If the plane figure of the member9includes a part with a narrow width and a part with a great width mixedly, the thermal resistance is increased by the part with a narrow width. Because of this, when the area of the member9is the same, it is possible to reduce the thermal resistance more when the width of the member9is uniform than when the width of the member9varies in the direction in which the member9extends. Because of this, in order to reduce the thermal resistance of the member9, it is most preferable for the member9to extend from the die pad3toward the member9with the same width.

Third Embodiment

FIG. 27is a plan perspective view of essential parts of a semiconductor device of the present invention, corresponding toFIG. 20in the above-mentioned second embodiment. The present embodiment corresponds to a modified example of the second embodiment. As inFIG. 20, inFIG. 27also, a plan perspective view of essential parts of a semiconductor device is shown when the sealing resin part7is viewed perspectively and further, the semiconductor chip2and the bonding wire5are removed (viewed perspectively), and for easier understanding, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line.

In the first and second embodiments described above, the plane figure of the die pad3is a circle having a diameter greater than the width (width in the direction perpendicular to the direction in which the member9extends from the die pad3toward the heat dissipating plate6) W1of the member9. In contrast to that, in the present embodiment, the plane figure of the die pad3is a rectangle, in which the length of each side of the die pad3in the shape of a rectangle is the same as the width (width in the direction perpendicular to the direction in which the member9extends from the die pad3toward the heat dissipating plate6) W1of the member9. That is, the region of intersection of the member9extending in the X direction and the member9extending in the Y direction is the die pad3, and the width of the region of intersection (die pad3) is the same as the width W1of the member9other than the region of intersection (die pad3).

Other configurations of the semiconductor device in the present embodiment are the same as those in the semiconductor device la in the second embodiment, and therefore, their explanation is omitted here.

In the present embodiment, compared to the semiconductor device1ain the second embodiment described above, it is possible to increase the area of adhesion between the back surface2bof the semiconductor chip2and the sealing resin part7by an amount corresponding to the amount of reduction in the area of the die pad3. Because of this, it is possible to appropriately prevent the semiconductor chip2from peeling off from the die pad3and the member9at the time of solder reflow when packaging the semiconductor device on the packaging substrate PWB etc., and therefore, the reliability (solder reflow resistance) of the semiconductor device can be improved further.

On the other hand, as in the first and second embodiments described above, when the plane figure of the die pad3is a circle having a diameter greater than the width W1of the member9, it is possible to stably perform the die bonding step of the semiconductor chip2stably, and therefore, the assembling characteristics (easiness of assembling) of the semiconductor device can be improved. Further, the larger the area of the die pad3, the more the thermal resistance can be reduced, and therefore, the heat dissipation characteristics can be improved further.

The present embodiment can be applied to any of the first and second embodiments, and fifth to ninth embodiments, to be described later.

Fourth Embodiment

FIG. 28is a plan perspective view of essential parts of a semiconductor device in the present embodiment, corresponding toFIG. 20andFIG. 27in the second and third embodiments. The present embodiment corresponds to a further modified example of the third embodiment. As inFIG. 20andFIG. 27, inFIG. 28also, a plan perspective view of essential parts of a semiconductor device is shown when the sealing resin part7is viewed perspectively and further, the semiconductor chip2and the bonding wire5are removed (viewed perspectively), and for easier understanding, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line.

In the third embodiment, the plane figure of the die pad3is a rectangle and the length of each side of the rectangular die pad3is the same as the width W1of the member9. In contrast to that, in the present embodiment, the plane figure of the die pad3is a rectangle, however, the length of each side of the die pad3is shorter than the width (width in the direction perpendicular to the direction in which the member9extends from the die pad3toward the heat dissipating plate6) W1of the member9. That is, the region of intersection of the member9extending in the X direction and the member9extending in the Y direction is the die pad3and the width of the region of intersection (die pad3) is less than the width W1of the member9other than the region of intersection (die pad3).

Other configurations of the semiconductor device in the present embodiment are the same as those of the semiconductor device in the third embodiment, and therefore, their explanation is omitted here.

In the third embodiment, the dimension of the chip mounting part to be bonded with the adhesive8is greatest in the diagonal direction of the region of intersection of the member9extending in the X direction and the member9extending in the Y direction, however, in the present embodiment, it is possible to reduce the length of the plane of adhesion between the back surface2bof the semiconductor chip2and the die pad3via the adhesive8compared to the above, and therefore, it is possible to further appropriately prevent the semiconductor chip2from peeling off from the die pad3and the member9at the time of solder reflow when packaging the semiconductor device on the packaging substrate PWB, and the reliability (solder reflow resistance) of the semiconductor device can be improved further.

The back surface2bof the semiconductor chip2is bonded also to the member9not only to the die pad3with the adhesive8, and it is effective to increase the width W1of the member9in order to efficiently conduct heat produced in the semiconductor chip2to the heat dissipating plate6. However, although it is advantageous to increase the width W1of the member9in improving the heat dissipation characteristics, it is disadvantage from the standpoint of preventing the semiconductor chip2from peeling off from the die pad3and the member9at the time of solder reflow when packaging the semiconductor device on the packaging substrate PWB etc. Because of this, when increasing the width W1of the member9in order to further improve the heat dissipation characteristics, if the present embodiment is applied, its effect will be great. By applying the present embodiment, it will become easier to suppress the semiconductor chip2from peeling off from the die pad3and the member9at the time of solder reflow when packaging the semiconductor device on the packaging substrate PWB etc. even if the width W1of the member9is increased.

The present embodiment can also be applied to any of the first and second embodiments and fifth to ninth embodiments, to be described later.

Fifth Embodiment

FIG. 29is a plan perspective view of essential parts of a semiconductor device1bin the present embodiment andFIG. 30toFIG. 32are each a section view of the semiconductor device1bin the present embodiment. The present embodiment corresponds to a modified example of the second embodiment.FIG. 29corresponds toFIG. 20in the second embodiment, FIG.30corresponds toFIG. 21in the second embodiment (that is, the section at the position corresponding to the A2-A2line inFIG. 18),FIG. 31corresponds toFIG. 22in the second embodiment (that is, the section at the position corresponding to the B2-B2line inFIG. 18), andFIG. 32corresponds toFIG. 23in the second embodiment (that is, the section at the position corresponding to the C2-C2line inFIG. 18). As inFIG. 20, inFIG. 29also, a plan perspective view of essential parts of a semiconductor device is shown when the sealing resin part7is viewed perspectively and further, the semiconductor chip2and the bonding wire5are removed (viewed perspectively), and for easier understanding, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line. Further, for easier understanding, inFIG. 29also, the positions corresponding to the A2-A2line, the B2-B2line, and the C2-C2line inFIG. 18are assigned the A2-A2line, the B2-B2line, and the C2-C2line, however, while only part of the semiconductor device1bis shown inFIG. 29,FIG. 30toFIG. 32are each a section view of the entire semiconductor device1b(the entire region shown inFIG. 18).

Both in the second embodiment and in the present embodiment, the height position of the die pad3and the member9is set lower than the height position of the inner lead part4aso that wire bonding between the inner lead part4aand the electrode PD of the semiconductor chip2is easy to perform. However, the height position of the heat dissipating plate6is different between the second embodiment and the present embodiment.

The height or the height position referred to in the present application corresponds to the height from the back surface7bof the sealing resin part7, which is the reference, to the top surface of each member. For example, the height position of the die pad3corresponds to the height from the back surface7bof the sealing resin part7to the top surface3aof the die pad3, the height position of the member9corresponds to the height from the back surface7bof the sealing resin part7to the top surface3aof the member9, the height position of the heat dissipating plate6corresponds to the height from the back surface7bof the sealing resin part7to the top surface6aof the heat dissipating plate6, and the height position of the inner lead part4acorresponds to the height from the back surface7bof the sealing resin part7to the top surface4cof the inner lead part4a.

That is, in the second embodiment, as can also be seen fromFIG. 21toFIG. 23, (the respective top surfaces3a,6aof) the die pad3, the member9, and the heat dissipating plate6are at the same height position and the heat dissipating plate6is arranged at a position (height position) lower than the inner lead part4a. Because of this, in the second embodiment, as shown inFIG. 20andFIG. 21, the bending part (flexing part)10ais provided in the midway of the suspension lead10. By bending the suspension lead10at the bending part10a, the height position of the suspension lead10, the heat dissipating plate6, the member9, and the die pad3inside the bending part10a(on the side nearer to the center of the die pad3or the semiconductor chip2) is made to be lower than the height position of the suspension lead10outside the bending part10a(on the side more distant from the center of the die pad3or the semiconductor chip2). The height position of the suspension lead10outside the bending part10ais substantially the same as the height position of the inner lead part4a. In the second embodiment, by providing the bending part10ato the suspension lead10, it is possible to arrange the die pad3, the member9, and the heat dissipating plate6at a position (height position) lower than the inner lead part4a.

On the other hand, in the semiconductor device1bin the present embodiment, as can also be seen fromFIG. 30toFIG. 32, the height position of (the top surface6aof) the heat dissipating plate6is higher than the height position of (the top surface3aof) the die pad3and the member9, and preferably, (the top surface6aof) the heat dissipating plate6is at the same height position as that of (the top surface4cof) the inner lead4a. Because of this, nothing corresponding to the bending part10aformed in the second embodiment is provided to the suspension lead10in the present embodiment. Instead, in the present embodiment, a bending part9ais provided between each member9and the inner edge6cof the heat dissipating plate6, and the bending part9ais bent so that the top surface3aof the die pad3and the member9is lower than the top surface6aof the heat dissipating plate6. The bending part9ais formed integrally with the heat dissipating plate6and the member9. By the bending part9a, the height position of the member9and the die pad3is made to be lower than the height position of the suspension lead10and the heat dissipating plate6.

In the present embodiment, nothing corresponding to the bending part10ais provided to the suspension lead10, and therefore, the height position of the suspension lead10, the height position of the heat dissipating plate6, and the height position of the inner lead part4aare substantially the same. Then, by providing the bending part9abetween the member9, not the suspension lead10, and the heat dissipating plate6, it is possible to arrange (the top surface3aof) the die pad3and the member9at a position lower than (the top surface4cof) the inner lead part4a, and at the same time, it is also possible to arrange (the top surface6a) of the heat dissipating plate6at a position higher than (the top surface3aof) the die pad3and the member9. Preferably, it is possible to arrange (the top surface6aof) the heat dissipating plate6at the same height position as (the top surface4cof) the inner lead4a.

In the present embodiment, the bending part9ais provided between the member9and the heat dissipating plate6, however, it is not possible to mount the semiconductor chip2over the bending part9a, and the semiconductor chip2is bonded to the member9and the die pad3, which are flat, other than the bending part9awith the adhesive8. Because of this, as also shown inFIG. 29andFIG. 31, the semiconductor chip2is arranged over the member9and the die pad3, which are flat, inside the bending part9a(on the side nearer to the center of the die pad3) so as not overlap the bending part9ain a planar manner and is bonded to the member9and the die pad3, which are flat, via the adhesive8. Preferably, the bending part9ais provided at a position as close as possible to the inner edge6of the heat dissipating plate6so that the upper limit of the plane dimensions of the semiconductor chip2that can be mounted is as great as possible.

Other configurations of the semiconductor device1bin the present embodiment are the same as those of the semiconductor device1ain the second embodiment, and therefore, their explanation is omitted here.

The closer the height position of the heat dissipating plate6to the height position of the inner lead part4a, the more likely heat is conducted from the heat dissipating plate6to the inner lead part4a, and if the height position of the heat dissipating plate6is the same as the height position of the inner lead part4a, the outer edge6dof the heat dissipating plate6and the tip end of the inner lead part4aoppose each other by the shortest distance, and therefore, it is possible to conduct heat most efficiently from the heat dissipating plate6to the inner lead part4a. In the present embodiment, by providing the bending part9abetween the heat dissipating plate6and the member9, the height position of (the top surface6aof) the heat dissipating plate6is made to be higher than the height position of (the top surface3aof) the die pad3and the member9, and thereby, it is possible to make the height position of the heat dissipating plate6close to the height position of the inner lead part4aand preferably, it is possible to make the height position (of the top surface6a) of the heat dissipating plate6equal to the height position of (the top surface4cof) the inner lead4a. Consequently, it is possible to efficiently conduct heat from the heat dissipating plate6to the inner lead part4a, and therefore, it is possible to efficiently conduct heat produced in the semiconductor chip2from the heat dissipating plate6to the inner lead part4avia the die pad3, the member9, and the heat dissipating plate6, and the heat dissipation characteristics through the second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8) can be improved further. Because of this, it is possible to further improve the heat dissipation characteristics of the semiconductor device lb.

In the present embodiment, it is possible to make the height position of (the top surface6aof) the heat dissipating plate6equal to a height position between the back surface2bof the semiconductor chip2and the top surface2aof the semiconductor chip2by the bending part9a. As a result, the heat dissipating plate6enters a state of opposing the side surface of the semiconductor chip2, and therefore, it is possible to conduct heat in the semiconductor chip2from the side surface of the semiconductor chip2to the heat dissipating plate6via the sealing resin part7between the side surface of the semiconductor chip2and the heat dissipating plate6, in addition to the path through which heat is conducted from the back surface2bof the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member9. Consequently, it is possible to more efficiently conduct heat in the semiconductor chip2to the heat dissipating plate6, and the heat dissipation characteristics of the semiconductor device1bcan be further improved.

In the present embodiment, the heat dissipating plate6, which occupies a comparatively large area, is located in the vicinity of the center in the thickness direction of the sealing resin part7, and therefore, the thickness of the sealing resin part7is substantially the same at the top part of the heat dissipating plate6and at the bottom part of the heat dissipating plate6, thereby it becomes possible to more appropriately suppress the warp of the semiconductor device1bwhen subjected to the change in temperature.

On the other hand, as in the second embodiment, when the height position of the heat dissipating plate6is made equal to the height position of the die pad3by providing the bending part10ato the suspension lead10, it is possible to make flat the position of the member9, where the bending part9ais provided, and therefore, it is possible to increase the maximum dimensions of the semiconductor chip2that can be mounted.

The present embodiment can be applied to any of the first to fourth embodiments and sixth to ninth embodiments, to be described later.

Sixth Embodiment

In the present embodiment, a method of manufacturing the semiconductor device1ain the second embodiment is explained. It is also possible to manufacture the semiconductor device in the first, third to fifth embodiments, and in seventh to ninth embodiments, to be described later, in substantially the same manner as that of the semiconductor device1ain the second embodiment, and therefore, a manufacturing step of the semiconductor device la in the second embodiment is explained here as a typical example with reference to the drawings.

FIG. 33is manufacturing process flow diagram showing a manufacturing step of the semiconductor device la.FIG. 34is a plan view (top view) of a lead frame LF used in manufacturing the semiconductor device1a, andFIG. 35andFIG. 36are each a section view of essential parts of the lead frame LF.FIG. 34shows a region (region from which one semiconductor device1ais manufactured) corresponding to one semiconductor package of the lead frame LF. In reality, the lead frame LF is a multiple lead frame, in which a plurality of unit structures shown inFIG. 34is linked (repeated) in the Y direction shown inFIG. 34, or a matrix lead frame, in which a plurality of unit structures is linked (repeated) both in the X direction and in the Y direction, respectively. InFIG. 34, the positions corresponding to the A2-A2line, the B2-B2line, and the C2-C2line inFIG. 18are assigned the A2-A2line, the B2-B2line, and the C2-C2line, and the section of the lead frame LF along the B2-B2line inFIG. 34substantially corresponds toFIG. 35and the section of the lead frame LF along the C2-C2line inFIG. 34substantially corresponds toFIG. 36. Because of this, the section view inFIG. 35is a section view at the corresponding sectional position inFIG. 22(along the B2-B2line) and the section view inFIG. 36is a section view at the corresponding sectional position inFIG. 23(along the C2-C2line).

In order to manufacture the semiconductor device1a, first, the lead frame LF and the semiconductor chip2are prepared (step S1inFIG. 33).

The lead frame LF shown inFIG. 34toFIG. 36is made of a conductor material (preferably, metal material), for example, a metal material containing copper or copper alloy as its principal component.

The lead frame LF has a frame21, the leads4linked to the frame21, the heat dissipating plate6linked to the frame21via the suspension leads10(four, here), and the die pad3linked to the heat dissipating plate6via the members9(four, here) in the form of integration. Further, the lead frame21has a tie bar (dam bar, link part)22that links the leads4and the suspension leads10in the form of integration and (the outer lead parts4bof) the neighboring leads4are linked by the tie bar22. It is possible to form the lead frame LF by, for example, processing a metal plate. The shapes and positional relationship of the die pad3, the member9, the heat dissipating plate6, the lead4, and the suspension lead10in the part located in the sealing resin part7, to be formed later, are the same as those of the semiconductor device after manufactured, and are already explained, and therefore, their explanation is omitted here.

It is possible to prepare the semiconductor chip2by, for example, after forming various semiconductor elements or semiconductor integrated circuits on the main surface of a semiconductor substrate (semiconductor wafer) including single crystal silicon etc., separating the semiconductor substrate into individual semiconductor chips by dicing etc.

In step S1, it may also be possible to prepare the semiconductor chip2after preparing the lead frame LF, or to prepare the lead frame LF after preparing the semiconductor chip2, or to prepare the lead frame LF and the semiconductor chip2simultaneously.

Next, by performing the die bonding step, the semiconductor chip2is mounted and bonded over the die pad3and the member9of the lead frame LF with the adhesive8(step S2inFIG. 33). The die bonding step in step S2is explained below.

FIG. 37toFIG. 41are each a section view of essential parts (FIG. 37,FIG. 39, andFIG. 40) or a plan view of essential parts (FIG. 38andFIG. 41) showing the die bonding step in step S2. InFIG. 37andFIG. 39, a section view of a region corresponding toFIG. 35(that is, the section along the B2-B2line) is shown, inFIG. 40, a section view of a region corresponding toFIG. 36(that is, the section along the C2-C2line) is shown, and inFIG. 38andFIG. 41, a plan view of a region corresponding toFIG. 20is shown. The section view inFIG. 37and the plan view inFIG. 38correspond to the same step stage and the section view inFIG. 39andFIG. 40and the plan view inFIG. 41correspond to the same step stage.

In the die bonding step in step S2, first, as shown inFIG. 37andFIG. 38, over the top surface3aof the die pad3and the member9of the lead frame LF, an adhesive (die bond material)8ais applied (arranged). The adhesive8awill cure to be the adhesive8later. AlthoughFIG. 38is a plan view, the adhesive8ais hatched to make the drawing easier-to-see.

As described above, in order to improve the heat dissipation characteristics, it is important to bond the entire surface of the part of the back surface2bof the semiconductor chip2, which is in opposition to the die pad3and the member9, to the die pad3and the member9with the adhesive8. Because of this, as shown inFIG. 37andFIG. 38, it is preferable to apply (arrange) the adhesive8aat a plurality of positions on the top surface3aof the die pad3and the member9. Further, it is preferable to apply (arrange) the adhesive8aover the part of the top surface3aof the member9, which is in opposition to the back surface2bof the semiconductor chip2to be mounted later, not only over the top surface3aof the die pad3. As a result, it becomes more likely for the adhesive8ato spread over the entire part in opposition to the back surface2bof the semiconductor chip2when mounting the semiconductor chip2. In the step of applying (arranging) the adhesive8a, it may be possible to apply (arrange) the adhesive8aat a plurality of positions using one nozzle (an application device with one nozzle) or apply (arrange) the adhesive8aat a plurality of positions using a multipoint nozzle (an application device with multiple nozzles). It is possible to shorten the time required for applying the adhesive8ausing the multipoint nozzle than when using a single point nozzle.

If the width W1of the member9is reduced to the minimum dimension (for example, about 1 mm) with which the application of the adhesive8aover the member9is possible, it becomes possible to apply the adhesive8aover the member9and at the same time, to increase the adhesion area between the back surface2bof the semiconductor chip2and the sealing resin part7, and therefore, the reliability (solder reflow resistance) of the semiconductor device can be improved.

After applying the adhesive8aover the top surface3aof the die pad3and the member9of the lead frame LF, the semiconductor chip2is arranged (mounted) over the top surface3aof the die pad3and the member9as shown inFIG. 39toFIG. 41. At this time, the semiconductor chip2is arranged (mounted) over the top surface3aof the die pad3and the member9via the adhesive8aso that the back surface2bof the semiconductor chip2opposes the top surface3aof the die pad3and the member9, and a load is applied to the semiconductor chip2to press the semiconductor chip2against the die pad3and the member9. As a result, the adhesive8ais spread (in a wetted manner) over the entire surface of the part where the top surface3aof the die pad3and the member9and the back surface2bof the semiconductor chip2are in opposition to each other. Then, by performing curing processing for curing the adhesive8a(for example, thermal processing for curing), the adhesive8acures into the adhesive8and the semiconductor chip2is fixed on the die pad3and the member9with the adhesive8. For easier understanding, in the plan view ofFIG. 41, the position of the die pad3and the member9located under the semiconductor chip2is shown by a dotted line and the region in which the adhesive8(that is, the adhesive8aspread in a wetted manner) is arranged (applied) is hatched by slashes, however, in reality, the adhesive8(adhesive8a) is hidden under the semiconductor chip2and not seen.

As described above, the die pad3is located in the center of the region surrounded by the heat dissipating plate6in the form of a frame and the die bonding step in step S2is performed so that the center part of the back surface2bof the semiconductor chip2is located immediately over the die pad3.

In this manner, it is possible to perform the die bonding step in step S2.

By performing the wire bonding step after performing die bonding in step S2, the electrodes PD of the semiconductor chip2and (the top surface4cof the inner lead part4aof) the leads4of a lead frame LD are electrically coupled respectively via the bonding wires5as shown inFIG. 42(step S3inFIG. 33).FIG. 42is a section view in the stage where the wire bonding step in step S3is performed and shows a section view of the region corresponding toFIG. 36andFIG. 40(that is, the section along the C2-C2line). The wire bonding process in step S3is explained later in detail.

After performing the wire bonding in step S3, resin sealing by the molding step (resin forming step, for example, transfer molding step) is performed and as shown inFIG. 43, the semiconductor chip2and the bonding wires5coupled thereto are sealed by the sealing resin part7(step S4inFIG. 33). At this time, the inner lead part4aof the lead part4, the die pad3, the heat dissipating plate6, the member9, and the suspension lead10are also sealed by the sealing resin part7. Here,FIG. 43is a section view in the stage where the molding step in step S4is performed and shows a section view of the region corresponding toFIG. 36,FIG. 40, andFIG. 42(that is the section along the C2-C2line).

By the molding step in step S4, the sealing resin part7is formed, which seals the semiconductor chip2, the die pad3, the inner lead part4aof the lead parts4, the bonding wires5, the heat dissipating plate6, the members9(four, here), and the suspension leads10(four, here). The sealing resin part7includes a resin material, such as, for example, a thermosetting resin material, and may also include a filler etc.

In each lead part4, the inner lead part4ais sealed in the sealing resin part7and not exposed but the outer lead part4bof each lead part4is located outside the sealing resin part7and exposed. Part of the suspension lead10is also located outside the sealing resin part7and exposed.

After the adhesive8ais cured in the die bonding step in step S2and until the sealing resin part7is formed in the molding step in step S4, at least part of the back surface2bof the semiconductor chip2is in opposition to neither die pad3nor the member9and is exposed. Because of this, when the sealing resin part7is formed in the molding step in step S4, the sealing resin part7is bonded to the part of the back surface2bof the semiconductor chip2, which is in opposition to neither the die pad3nor the member9and is exposed, as a result.

Next, the tie bar22of the lead frame LF is cut (step S5inFIG. 33). Before the tie bar22is cut in step S5, the outer lead parts4bof the neighboring leads4are linked to each other by the tie bar22. The tie bar22has a function to prevent the inner lead parts4aof the leads4from coming into contact with each other to short-circuit and a function to prevent resin from flowing out when forming the sealing resin part7, however, in the manufactured semiconductor device, it is necessary for the leads4to be electrically separated from each another, and therefore, the tie bar22that links the outer lead parts4bof the leads4located outside the sealing resin part7is cut in step S5. By performing the cutting step of the tie bar22in step S5, the neighboring leads4enter a separated state.

Next, plating processing is performed for the outer lead part4bof the lead4exposed from the sealing resin part7(step S6inFIG. 33). As a result, it is made easier to join the outer lead part4bof the lead4of the semiconductor device1band the terminal TE of the packaging substrate PWB via solder when packaging (solder-packaging) the semiconductor device1bon the packaging substrate PWB etc.

Next, outside the sealing resin part7, after the lead4is cut at a predetermined position, the outer lead part4bof the lead4, which projects from the sealing resin part7, is bent (lead processing, lead formation) (step S7inFIG. 33).FIG. 44is a section view in the stage where the cutting and the forming step of the lead4in step S7are performed, showing a section view of a region corresponding toFIG. 36,FIG. 40,FIG. 42, andFIG. 43(that is, the section along the C2-C2line).

In step S7, first by performing the cutting step of the lead4, the lead4is separated from (the frame21of) the lead frame LF and a state is brought about where the outer lead part4bof the lead4projects from the side surface of the sealing resin part7. That is, the lead4is cut so that the outer lead part4bwith a predetermined length is left on the side of the semiconductor device1. In the cutting step of the lead4in step S7, not only the lead4is cut but also the suspension lead10of the part projecting from the sealing resin part7is also cut. The suspension lead10is cut so that the suspension lead10does not project from the side surface of the sealing resin part7after the cutting. Because of this, the cut surface of the suspension lead10is exposed at the side surface of the sealing resin part7.

In step S7, after the cutting step of the lead4, the outer lead part4bof the lead4projecting from the heat dissipating plate6ais bent as shown inFIG. 44. As a result, the semiconductor device1bdivided into pieces is obtained (manufactured).

FIG. 45toFIG. 52are each an explanatory diagram of the wire bonding step in step S3. It is desirable to securely hold the semiconductor chip2in the wire bonding step so as to prevent ultrasonic waves from being emitted from the wire bonder. In the following, a technique is explained, which is for stably holding the semiconductor chip2in accordance with the magnitude of the plane dimensions of the semiconductor chip2in the wire bonding step in step S3.

FIG. 46toFIG. 48ofFIG. 45toFIG. 52show a technique suitable when applied to the case where the plane dimensions of the semiconductor chip2are large, and in the following, this technique is referred to as a first holding method, and the first holding method is explained.

FIG. 45shows the lead frame LF in which the semiconductor chip2is mounted over the die pad3and the member9(hereinafter, referred to as a work WK) after the steps up to the die bonding step in step S2are performed.FIG. 45corresponds to the section at the position of the A2-A2line inFIG. 34.FIG. 46andFIG. 47show a state where the work WK (the work WK inFIG. 45) is arranged on a stage31for wire bonding in the wire bonding step in step S3.FIG. 46shows a section view corresponding toFIG. 45(that is, the section along the A2-A2line) andFIG. 47shows a section view corresponding toFIG. 39(that is, the section along the B2-B2line).FIG. 48shows a planar region corresponding toFIG. 41, showing the position of the die pad3and the member9located under the semiconductor chip2by a dotted line, and inFIG. 48, the planar position where it is attracted by an attracting hole part32, to be described later, is hatched for easier understanding, however, in reality, the back surface2bof the semiconductor chip2is attracted, and therefore, the attracted part is hidden under the semiconductor chip2and not seen.

In the first holding method shown inFIG. 46toFIG. 48, the back surface2bof the semiconductor chip2is attracted (vacuum attracted). To explain specifically, the part of the back surface2bof the semiconductor chip2, which is in opposition to the die pad3and the member9, cannot be attracted, however, the part in opposition to neither the die pad3nor the member9(that is, the part located over the opening13) is exposed, and therefore, can be attracted. Because of this, as shown inFIG. 46andFIG. 47, a recess (recess part, groove part)33that can accommodate the die pad3, the member9, and the heat dissipating plate6is provided on a top surface31aof the stage31and when arranging the work WK over the stage31, the die pad3, the member9, and the heat dissipating plate6are accommodated in the recess33. As a result, it is possible to make the back surface2bof the semiconductor chip2(the part exposed from the opening13) come into contact with (the attracting hole part32provided on) the top surface31aof the stage31. If the attracting hole part (attraction hole for vacuum attraction)32is arranged at a part of the contact surface of the back surface2bof the semiconductor chip2(part exposed from the opening13) and the top surface31aof the stage31, it is possible to attract (vacuum attract) the back surface2bof the semiconductor chip2from the attracting hole part32by vacuum suction, and therefore, to hold the semiconductor chip2.

That is, the wire bonding step in step S3is performed while vacuum attracting the exposed part (that is, the part exposed from the opening13) of the back surface2bof the semiconductor chip2, which is in opposition to neither the die pad3nor the member9. In order to stably hold the semiconductor chip2, it is preferable to attract a plurality of parts of the back surface2bof the semiconductor chip2by a plurality of the attracting hole parts32. Because of this, as shown inFIG. 48, it is preferable to attract the respective parts (four parts inFIG. 48) exposed from the openings13by the attracting hole part32. By attracting the parts (preferably, four parts) of the back surface2bof the semiconductor chip2to fix the semiconductor chip2, ultrasonic waves are prevented from being emitted at the time of wire boding, and therefore, it is possible to perform wire bonding stably.

In the first holding method, the die pad3, the member9, and the heat dissipating plate6are accommodated in the recess33of the stage31, however, it is preferable for the bottom surface3bof the die pad3and the member9and the bottom surface6bof the heat dissipating plate6not to come into contact with the stage31. That is, it is preferable for there to be a gap of a certain size between the bottom surfaces3b,6bof the die pad3, the member9, and the heat dissipating plate6and the bottom of the recess33of the stage31. As a result, it is possible to absorb the warp and twist of the die pad3, the member9, and the heat dissipating plate6, or variations in thickness of the adhesive8, and therefore, it becomes possible to appropriately attract the back surface2bof the semiconductor chip2by the attracting hole part32.

FIG. 50toFIG. 52ofFIG. 45toFIG. 52show a technique suitable when applied to the case where the plane dimensions of the semiconductor chip2are small, and in the following it is referred to as a second holding method and the second holding method is explained.

FIG. 49shows the lead frame LF in which the semiconductor chip2is mounted over the die pad3and the member9(hereinafter, referred to as the work WK) after the steps up to the die bonding step in step S2are performed. LikeFIG. 45,FIG. 49corresponds to a section at the position of the A2-A2line inFIG. 34, however, in the work WK, the dimensions of the semiconductor chip2mounted are smaller inFIG. 49than those inFIG. 45.FIG. 50andFIG. 51show a state where the work WK (the work WK inFIG. 49) is arranged on the stage31for wire bonding in the wire bonding step in step S3.FIG. 50shows a section view corresponding toFIG. 49(that is, the section along the C2-C2line) andFIG. 51shows a section view corresponding toFIG. 39(that is, the section along the B2-B2line).FIG. 52shows a planar region corresponding toFIG. 41, showing the position of the die pad3and the member9located under the semiconductor chip2by a dotted line, and inFIG. 48, the planar position where it is attracted by the attracting hole part32, to be described later, is hatched by slashes for easier understanding, however, in reality, the bottom surface of the die pad3and the heat dissipating plate6is attracted, and therefore, the attracted part is hidden under the die pad3and the heat dissipating plate6and not seen.

When the plane dimensions of the semiconductor chip2are reduced, the area of the back surface2bof the semiconductor chip2, which is exposed from the opening13, is reduced, and therefore, it becomes difficult to attract the back surface2bof the semiconductor chip2, while it is not by the first holding method. Because of this, in the second holding method shown inFIG. 50toFIG. 52, the bottom surface3bof the die pad3and the bottom surface6bof the heat dissipating plate6are attracted (vacuum attracted).

Because of this, as shown inFIG. 50andFIG. 51, a recess (recess part, groove part)34that can accommodate the die pad3, the member9, and the heat dissipating plate6is provided on the top surface31aof the stage31, and when arranging the work WK over the stage31, the die pad3, the member9, and the heat dissipating plate6are accommodated in the recess34and the bottom surface3bof the die pad3and the member9and the bottom surface6bof the heat dissipating plate6are made to come into contact with the bottom of the recess34. If the attracting hole part (attracting hole for vacuum attraction)32is arranged in a part of the contact surface of the bottom surfaces3b,6bof the die pad3and the heat dissipating plate6and the bottom of the recess34, it is possible to attract (vacuum attract) the bottom surface3bof the die pad32and the bottom surface6bof the heat dissipating plate6from the attracting hole part32by vacuum suction. As a result, it is possible to hold the work WK and the semiconductor chip2bonded over the die pad3and the member9. It is preferable to attract the bottom surface3bof the die pad3, however, if it is hard to attract the bottom surface3bof the die pad3, it may also be possible to attract the bottom surface3bof the member9instead of the die pad3, and it may also be possible to attract both the bottom surface3bof the die pad3and the bottom surface3bof the member9. In order to hold the semiconductor chip2stably, it is important to attract also the bottom surface6bof the heat dissipating plate6from the attracting hole part32in addition to at least one part of the bottom surface3bof the die pad3and the member9. That is, the wire bonding step in step S3is performed while vacuum attracting the bottom surface of the chip mounting part including the die pad3and the member9, and the bottom surface6bof the heat dissipating plate6.

FIG. 53andFIG. 54are each an explanatory diagram of the wire bonding step when the die pad103bin the second comparative example inFIG. 2is applied, corresponding toFIG. 51andFIG. 52in the present embodiment, respectively.

When the die pad103bin the second comparative example is applied, if the plane dimensions of the semiconductor chip2to be mounted over the die pad103bare reduced, it is not possible to attract the back surface of the semiconductor chip102but possible to attract only the bottom surface of the die pad103bas shown inFIG. 53andFIG. 54. Because of this, during the wire bonding, a θ rotation is caused by its vibrations and trouble becomes more likely to occur in the wire bonding.

In contrast to the above, in the second holding method, not only the bottom surface3bof the die pad3but also the bottom surface6bof the heat dissipating plate6is also attracted (vacuum attracted), and therefore, it is possible to stably hold and fix the work WK. In particular, it is preferable to attract (vacuum attract) the part where the width of the heat dissipating plate6is great (center part of each of the four sides of the heat dissipating plate6) because it is easy to attract the heat dissipating plate6. Further, if a plurality of parts of the bottom surface of the heat dissipating plate6is attracted (vacuum attracted), it is possible to hold the work WK more stably.

At the time of wire bonding, the heat dissipating plate6also plays a role to absorb heat from the stage31, and therefore, compared to the case where the die pad103bin the second comparative example, which has nothing corresponding to the heat dissipating plate6, is applied, there is an advantage that the time required from when the work WK is set over the stage31to when the dimensions of each part of the work WK become stable is reduced. That is, it is possible to suppress a phenomenon that dimensions vary during wire bonding.

Next, a method of forming the lead frame LF, which is prepared in step S1described above, is explained below.

It is possible to form the lead frame LF by a technique to etch a metal plate or a technique to press-work a metal plate. Here, a technique to form the lead frame LF by press-working a metal plate is explained.FIG. 55toFIG. 58are each an explanatory diagram of a technique to form the lead frame LF by press-working a metal plate41.

As shown inFIG. 55,FIG. 57, andFIG. 58, it is possible to work the metal plate41into the form of the lead frame LF by punching out the metal plate41with pressing (cutting) punches42a,42b.

Here, the opening13is formed with the punch42a, and at this time, it is preferable to punch out the metal plate41with the punch42ain the direction from a top surface LFa side of the lead frame LF (that is, from the top surface3aside of the die pad3and the member9) toward a bottom surface LFb side of the lead frame LF (that is, the bottom surface3bof the die pad3and the member9). The reason for this is as follows.

That is, to the die pad3, the heat dissipating plate6is linked via the member9, and therefore, if coining is performed after the press working (punching out with the punch42a), the die pad3and the member9are lengthened in the planar direction by an amount corresponding to the crushed part and there arises a problem that the heat dissipating plate6, the member9, and the die pad3deform in the direction toward the outside of the plane. Because of this, it is preferable not to perform coining for the die pad3. However, if coining is not performed, a burr (metal burr)43aproduced by the punching out with the punch42aremains in the die pad3and the member9. If the burr43aexists on the top surface3aof the die pad3and the member9, which is a chip mounting surface, it will cause trouble, such as that the semiconductor chip2mounted over the top surface3aof the die pad3and the member9is inclined because of the burr43aand that wetting of the adhesive8is insufficient.

In contrast to the above, in the present embodiment, when forming the die pad3and the member9by press working, it is recommended to punch out the metal plate41with the punch42ain the direction from the top surface LFa side of the lead frame LF (that is, the top surface3aside of the die pad3and the member9) toward the bottom surface LFb side of the lead frame LF (that is, the bottom surface3bside of the die pad3and the member9), as shown inFIG. 55. As a result, the burr43ais formed on (the end part of) the bottom surface3bof the die pad3and the member9, however, the burr43ais not formed on (the end part of) the top surface3aof the die pad3and the member9, and (the end part of) the top surface3aof the die pad3and the member9is in the form of a sag. Further, as shown inFIG. 56, even if the semiconductor chip2is mounted (bonded) over the top surface3aof the die pad3and the member9via the adhesive8, it is possible to suppress or prevent trouble, such as that the semiconductor chip2is inclined because of burr and that the wetting of the adhesive8is insufficient, because the burr43ais not formed on the top surface3aof the die pad3and the member9, which is a chip mounting surface.

Consequently, in the die pad3and the member9, the burr43aformed on the bottom surface3bside of the die pad3and the member9faces in the direction from the top surface3atoward the bottom surface3bof the die pad3and the member9, and the burr43aremains after the semiconductor device (here, the semiconductor device1a) is manufactured.

The inner edge6cof the heat dissipating plate6is formed simultaneously with the die pad3and the member9with the same punch42aas that with which the die pad3and the member9are formed. Because of this, as shown inFIG. 55, on the inner edge6cof the heat dissipating plate6, the burr43ais formed on the bottom surface6bside of the heat dissipating plate6, however, the burr43ais not formed on the top surface6aside of the heat dissipating plate6, and the top surface6aside of the heat dissipating plate6is in the form of a sag. On the inner edge6cof the heat dissipating plate6, the burr43aformed on the bottom surface6bside of the heat dissipating plate6faces in the same direction as that of the burr43aformed on the bottom surface3bside of the die pad3and the member9, that is, in the direction from the top surface6atoward the bottom surface6bof the heat dissipating plate6, and the burr43aremains after the semiconductor device (here, the semiconductor device1a) is manufactured.

On the other hand, the tip end of the inner lead part4aof the lead4(tip end in opposition to the semiconductor chip2) and the outer edge6dof the heat dissipating plate6are formed simultaneously with the same punch42b, as shown inFIG. 57orFIG. 58. That is, by punching out the metal plate41with the same punch42b, the tip end of the inner lead part4aand the outer edge6dof the heat dissipating plate6are formed simultaneously.

When forming the tip end of the inner lead part4aand the outer edge6dof the heat dissipating plate6, there are two cases: a case where the metal plate41is punched out with the punch42bin the direction from the bottom surface LFb side of the lead frame LF toward the top surface LFa side of the lead frame LF, as shown inFIG. 57; and a case where the metal plate41is punched out with the punch42bin the direction from the top surface LFa side of the lead frame LF toward the bottom surface LFb side of the lead frame LF, as shown inFIG. 58. After the punching out with the punch42b, the suspension lead10is bent at the bending part10a, however,FIG. 57shows a state before the bending, and therefore, the inner lead4aand the heat dissipating plate6are at the same height position.

As shown inFIG. 57, when the metal plate41is punched out with the punch42bin the direction from the bottom surface LFb side of the lead frame LF (the side of the bottom surfaces6b,4dof the heat dissipating plate6and the inner lead part4a) toward the top surface LFa side of the lead frame LF (the side of the top surfaces6a,4cof the heat dissipating plate6and the inner lead part4a), a burr (metal burr)43bproduced by the punching out with the punch42bon the outer edge6dof the heat dissipating plate6and on the tip end of the inner lead part4ais as follows.

That is, as shown inFIG. 57, on the outer edge6dof the heat dissipating plate6, the burr43bis formed on the top surface6aside of the heat dissipating plate6, however, on the bottom surface6bside of the heat dissipating plate6, the burr43bis not formed but it is in the form of a sag. Because of this, the burr43bformed on the outer edge6dof the heat dissipating plate6faces in the direction from the bottom surface6bof the heat dissipating plate6toward the top surface6a. Similarly, on the tip end of the inner lead part4a, the burr43bis formed on the top surface4cside of the inner lead part4a, however, on the bottom surface4dside of the inner lead part4a, the burr43is not formed but it is in the form of a sag.

Because of this, the burr43bformed on the tip end of the inner lead part4afaces in the direction from the bottom surface4dof the inner lead part4atoward the top surface4c. That is, on the outer edge6dof the heat dissipating plate6and on the tip end of the inner lead part4a, the burr43bfacing in the opposite direction of the burr43a(the burr43aformed on the inner edge6cof the die pad3, the member9, and the heat dissipating plate6) is formed on the top surfaces6a,4cside of the heat dissipating plate6and the inner lead part4a, and the burr43bremains after the semiconductor device (here, the semiconductor device1a) is manufactured.

It is necessary to perform wire bonding for the flat surface while avoiding the region with the burr43bor in the form of a sag, however, the burr43bis formed locally by the punching out with the punch42b, but the form of a sag occurs in an area larger than the area of the burr43b, and therefore, it is more advantageous to select the burr43bformation side rather than the surface side in the form of a sag as the surface side for bonding in order to increase the bonding area of wire bonding. It is possible to crush the burr on the tip end part of the inner lead part4aby coining, however, in general, the depth of the coining is less than the depth of the form of a sag, and therefore, even when the burr on the tip end part of the inner lead part4ais crushed by coining, it is more advantageous to select the burr43bformation side rather than the surface side in the form of a sag as the surface side for bonding in order to increase the bonding area of wire bonding.

Because of this, when the burr43bis formed on the top surface4cside of the inner lead part4aand the bottom surface4dside of the inner lead part4ais in the form of a sag, it is possible to ensure a large area of the part (that is, the bonding surface) against which a capillary is pressed on the top surface4C of the inner lead4ain the wire boding step in step S3. This is preferable when applied to the case where the area of the bonding surface is desired to be increased in the inner lead part4a(for example, when the area of the bonding surface is desired to be increased as much as possible because the width of the inner lead part4ais small).

On the other hand, as shown inFIG. 58, when the metal plate41is punched out with the punch42bin the direction from the top surface LFa side of the lead frame LF (the side of the top surfaces6a,4cof the heat dissipating plate6and the inner lead part4a) toward the bottom surface LFb side of the lead frame LF (the side of the bottom surfaces6b,4dof the heat dissipating plate6and the inner lead part4a), the burr (metal burr)43bproduced by the punching out with the punch42bon the outer edge6dof the heat dissipating plate6and on the tip end of the inner lead part4ais as follows.

That is, as shown inFIG. 58, on the outer edge6dof the heat dissipating plate6, the burr43bis formed on the bottom surface6bside of the heat dissipating plate6, however, on the top surface6aside of the heat dissipating plate6, the burr43bis not formed but it is in the form of a sag. Because of this, the burr43bformed on the outer edge6dof the heat dissipating plate6faces in the direction from the top surface6aof the heat dissipating plate6toward the bottom surface6b. Similarly, on the tip end of the inner lead part4a, the burr43bis formed on the bottom surface4dside of the inner lead part4a, however, on the top surface4cside of the inner lead part4a, the burr43is not formed but it is in the form of a sag. Because of this, the burr43bformed on the tip end of the inner lead part4afaces in the direction from the top surface4cof the inner lead part4atoward the bottom surface4d. That is, on the outer edge6dof the heat dissipating plate6and on the tip end of the inner lead part4a, the burr43bfacing in the same direction as that of the burr43a(the burr43aformed on the inner edge6cof the die pad3, the member9, and the heat dissipating plate6) is formed on the bottom surfaces6b,4dside of the heat dissipating plate6and the inner lead part4a, and the burr43bremains after the semiconductor device (here, the semiconductor device1a) is manufactured.

In this case, the direction of punching out with the punch42ais the same as the direction of the punching out with the punch42b, and therefore, it is possible to form (work) the inner edge6cof die pad3, the member9, and the heat dissipating plate6, the outer edge6dof the heat dissipating plate6, and the tip end of the inner lead part4aby one-time punching out using the punches42a,42b. Because of this, it is possible to reduce the number of steps required to form the lead frame LF. This is preferable when applied to the case where it is not necessary to ensure a large area of the bonding surface in the inner lead part4a(for example, when it is not necessary to ensure a large area of the bonding surface because the width of the inner lead part4ais great).

The reason why it is preferable not to perform coining for the die pad3is already stated above, and this also applies to the heat dissipating plate6. To the heat dissipating plate6, the die pad3is linked via the member9, and therefore, if coining is performed after the press working, the heat dissipating plate6and the member9are lengthened by an amount corresponding to the crushed part in the planar direction and there is a possibility that the die pad3, the member9, and the heat dissipating plate6deform in the direction toward the outside of the plane.

Consequently, even if it is possible to crush the burr43bformed on the tip end of the inner lead part4aby coining, coining cannot be performed for the heat dissipating plate6because of the reason described above, and therefore, the burr43bformed on the outer edge6dof the heat dissipating plate6remains after the semiconductor device (here, the semiconductor device1a) is manufactured.

The present embodiment can be applied to any of the first to fifth embodiments described above and seventh to ninth embodiments, to be described later.

Seventh Embodiment

FIG. 59is a bottom view (back view) of a semiconductor device is in the present embodiment,FIG. 60is a partially enlarged plan perspective view of the semiconductor device is in the present embodiment, andFIG. 61toFIG. 63are each a section view (side surface section view) of the semiconductor device1cin the present embodiment. The present embodiment corresponds to a modified example of the second embodiment and the fifth embodiment described above.FIG. 60corresponds toFIG. 20of the second embodiment, showing a plan perspective view of essential parts of the semiconductor device when the sealing resin part7is viewed perspectively and further, the semiconductor chip2and the bonding wire5are removed (viewed perspectively), and for easier understanding, the position where the semiconductor chip2is mounted (arranged) is shown by a dotted line.FIG. 61corresponds toFIG. 21of the second embodiment (that is, the section at the position corresponding to the A2-A2line inFIG. 18),FIG. 62corresponds toFIG. 22of the second embodiment (that is, the section at the position corresponding to the B2-B2line inFIG. 18), andFIG. 63corresponds toFIG. 23of the second embodiment (that is, the section at the position corresponding to the C2-C2line inFIG. 18). InFIG. 60also, for easier understanding, the positions corresponding to the A2-A2line, the B2-B2line, and the C2-C2line inFIG. 18are assigned the A2-A2line, the B2-B2line, and the C2-C2line, however, while only part of the semiconductor device1cis shown inFIG. 60,FIG. 61toFIG. 63are each a section view of the entire semiconductor device1c(the entire region shown inFIG. 18).

In the semiconductor device1ain the second embodiment, the heat dissipating plate6is sealed in the sealing resin part7and not exposed from the sealing resin part7. In contrast to this, in the semiconductor device1cin the present embodiment, as can also be seen fromFIG. 59, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7. The top surface6aand the side surface of the heat dissipating plate6are sealed in the sealing resin part7.

In any of the second and fifth embodiments and the present embodiment also, the height position of the die pad3and the member9is set lower than the height position of the inner lead part4aso that wire bonding between the inner lead part4aand the electrode PD of the semiconductor chip2is easy to perform, however, the bottom surface3aof the die pad3and the member9is not exposed from the bottom surface7bof the sealing resin part7. However, the height position of the heat dissipating plate6is different among the second embodiment, the fifth embodiment, and the present embodiment.

That is, in the second embodiment, as can also be seen fromFIG. 21toFIG. 23, the heat dissipating plate6is arranged at a position lower than the inner lead part4a, however, the heat dissipating plate6is at the same height position as the die pad3and the member9and none of the heat dissipating plate6, the member9, and the die pad3is exposed at the bottom surface7bof the sealing resin part7. In the fifth embodiment, the height position of the heat dissipating plate6is set higher than the die pad3and the member9and none of the heat dissipating plate6, the member9, and the die pad3is exposed at the bottom surface7bof the sealing resin part7. In contrast to the above, in the present embodiment, the height position of the heat dissipating plate6is set further lower than the die pad3and the member9, and thereby, the bottom surface3bof the die pad3and the member9is not exposed at the bottom surface7bof the sealing resin part7, however, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7.

To explain specifically, in the semiconductor device is in the present embodiment, as can also be seen fromFIG. 60toFIG. 63, a bending part (flexing part)10bis provided in the middle of the suspension lead10(in the vicinity of the part linked to the heat dissipating plate6). The direction of bending of the bending part10bin the present embodiment is the same as the direction of the bending of the bending part10ain the second embodiment, however, the difference in height due to the bending is larger in the bending part10bin the present embodiment than that in the bending part10ain the second embodiment. That is, in the present embodiment, the bending part10bof each of the suspension leads10(four, here) is bent so that the height position of the heat dissipating plate6is lower than the height position of the inner lead part4aand the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7. As a result, while the bottom surface6bof the heat dissipating plate6is not exposed at the bottom surface7bof the sealing resin part7in the second embodiment, it is possible to expose the bottom surface6bof the heat dissipating plate6at the bottom surface7bof the sealing resin part7in the semiconductor device is in the present embodiment.

That is, the height position of the suspension lead10outside the bending part10bis substantially the same as the height position of the inner lead part4a, however, because the suspension lead10is provided with the bending part10b, it is possible to arrange the heat dissipating plate6at a position lower than the inner lead part4a. Then, it is possible to expose the bottom surface6bof the heat dissipating plate6at the bottom surface7bof the sealing resin part7by forming the sealing resin part7so that the bottom surface6bof the heat dissipating plate6is exposed in the molding step in step S4.

Further, in the present embodiment, as can also be seen fromFIG. 60toFIG. 63, the height position of (the top surface3aof) the die pad3and the member9is higher than the height position of (the top surface6aof) the heat dissipating plate6. Because of this, in the present embodiment, the bending part (flexing part)9bis provided between each member9and the inner edge6cof the heat dissipating plate6, however, the direction of bending of the bending part9bin the present embodiment is opposite to the direction of bending of the bending part9ain the fifth embodiment. That is, while the bending part9ais bent so that the top surface3aof the die pad3and the member9is lower than the top surface6aof the heat dissipating plate6in the fifth embodiment, the bending part9bis bent so that the top surface3aof the die pad3and the member9is higher than the top surface6aof the heat dissipating plate6in the present embodiment. The bending part9bis formed integrally with the heat dissipating plate6and the member9. By the bending part9, the height position of the member9and the die pad3is made higher than the height position of the heat dissipating plate6. As a result, it is possible to expose the bottom surface6bof the heat dissipating plate6at the bottom surface7bof the sealing resin part7while preventing the bottom surface3bof the member9and the die pad3from being exposed at the bottom surface7bof the sealing resin part7.

In the present embodiment, the bending part9bis provided between the member9and the heat dissipating plate6, however, it is not possible to bond the semiconductor chip2over the bending part9b, and the semiconductor chip2is bonded to the member9and the die pad3, which are flat, other than the bending part9bwith the adhesive8. Because of this, as also shown inFIG. 60, the semiconductor chip2is arranged over the member9and the die pad3, which are flat, inside the bending part9b(on the side nearer to the center of the die pad3) so as not to overlap the bending part9bin a planar manner and is bonded to the member9and the die pad3, which are flat, via the adhesive8. Preferably, the bending part9bis provided at a position as close as possible to the inner edge6of the heat dissipating plate6so that the upper limit of the plane dimensions of the semiconductor chip2that can be mounted is as great as possible.

Other configurations of the semiconductor device1cin the present embodiment are the same as those of the semiconductor device1ain the second embodiment and the semiconductor device1bin the fifth embodiment, and therefore, their explanation is omitted here.

In the present embodiment, by exposing the bottom surface6bof the heat dissipating plate6at the bottom surface7bof the sealing resin part7, it is possible to conduct heat produced in the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member and to dissipate the heat to the outside of the semiconductor device is (under the semiconductor device1c) from the heat dissipating plate6. Because of this, it is possible to dissipate heat in the semiconductor chip2to the outside of the semiconductor device is (under the semiconductor device1c) from the heat dissipating plate6via the adhesive8having a thermal conductivity higher than that of the sealing resin part7, the die pad3, the member9, and the heat dissipating plate6, not via the sealing resin part7having a low thermal conductivity, and therefore, the heat dissipation characteristics of the semiconductor device1ccan be improved further. When packaging the semiconductor device is on the packaging substrate PWB, if the bottom surface6bof the heat dissipating plate6exposed at the bottom surface7bof the sealing resin part7is joined (solder-coupled) to the terminal TE of the top surface of the packaging substrate PWB, it is possible to efficiently dissipate heat from the bottom surface6bof the heat dissipating plate6to the packaging substrate PWB, and therefore, the effect to improve the heat dissipation characteristics of the semiconductor device1ccan be further magnified.

Unlike the present embodiment, when not only the bottom surface6bof the heat dissipating plate6but also the bottom surface3bof the die pad3and the member9is exposed at the bottom surface7bof the sealing resin part7, the boundary surface between the die pad3and the member97exposed at the bottom surface7bof the sealing resin part7and the sealing resin part7is close to the semiconductor chip2, and therefore, in a high-temperature and high-humidity load test, there is a possibility that moisture etc. may be conducted to the semiconductor chip2through the boundary surface. This may degrade the reliability (moisture resistance) of the semiconductor device.

In contrast to the above, in the present embodiment, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7, however, the die pad3and the member9that mount the semiconductor chip2are not exposed from the sealing resin part7. Then, the boundary surface between the heat dissipating plate6exposed at the bottom surface7bof the sealing resin part7and the sealing resin part7is comparatively distant from the semiconductor chip2. Because of this, when compared to the case where the die pad3and the member9are exposed at the bottom surface7bof the sealing resin part7, in the case where only the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7, as in the present embodiment, moisture etc. is unlikely to be conducted to the semiconductor chip2through the boundary surface formed on the bottom surface7bof the sealing resin part7in a high-temperature and high-humidity load test, and therefore, it is possible to suppress or prevent the deterioration of the moisture resistance of the semiconductor device. Because of this, it is possible to improve the heat dissipation characteristics while suppressing deterioration of the moisture resistance.

On the other hand, like the semiconductor device1ain the second embodiment and the semiconductor device1bin the fifth embodiment, when not only the die pad3and the member9but also the heat dissipating plate6is sealed in the sealing resin part7and not exposed at the bottom surface7bof the sealing resin part7, the boundary surface that leads to the semiconductor chip2is only the exposed surface of the suspension lead10at the side surface of the sealing resin part7. The exposed surface of the suspension lead10is sufficiently distant from the semiconductor chip2. Because of this, from the standpoint of the durability (moisture resistance) in a high-temperature and high-humidity load test, such a structure in which the heat dissipating plate6is also sealed in the sealing resin part7, like the semiconductor device1ain the second embodiment and the semiconductor device1bin the fifth embodiment, is most excellent.

Consequently, when creating a design to improve the heat dissipation characteristics as much as possible while aiming at the coexistence of the improvement of heat dissipation characteristics and that of the moisture resistance (durability in a high-humidity load test), it is recommended to employ such a structure in which the bottom surface6bof the heat dissipating plate6is exposed from the sealing resin part7like the semiconductor device1cin the present embodiment. On the other hand, when creating a design to improve the moisture resistance as much as possible while aiming at the coexistence of the improvement of heat dissipation characteristics and that of the moisture resistance, it is recommended to employ such a structure in which the heat dissipating plate6is not exposed from the sealing resin part7like the semiconductor device1ain the second embodiment and the semiconductor device1bin the fifth embodiment.

The present embodiment can be applied to any of the first to sixth embodiments and eighth and ninth embodiments, to be described later.

Eighth Embodiment

FIG. 64is a top view (plan view) of a semiconductor device1din the present embodiment,FIG. 65is a bottom view (back view) of the semiconductor device1d, andFIG. 66is a plan perspective view (top view) of the semiconductor device1dwhen the sealing resin part7is viewed perspectively.FIG. 67is a plan perspective view (top view) of the semiconductor device1dwhen the semiconductor chip2and the bonding wire5are removed (viewed perspectively) inFIG. 66. InFIG. 67, for easier understanding, the position where the semiconductor chip2is mounted (arranged) is indicated by a dotted line.FIG. 68is a section view (side surface section view) of the semiconductor device1dand the section view at the position along the B3-B3line inFIG. 66substantially corresponds toFIG. 68.

In the present embodiment, the structure in the seventh embodiment is applied to a QFN (Quad Flat Non leaded package) semiconductor device. Because of this, the semiconductor device1din the present embodiment shown inFIG. 64toFIG. 68is a resin-sealed, surface-mount type semiconductor package, that is, a QFN semiconductor device, and different from the semiconductor device1cin the seventh embodiment in the following points.

The semiconductor device is in the seventh embodiment is a QFP semiconductor device and part of each lead4(that is, the outer lead part4b) projects from the side surface of the sealing resin part7and is bent and worked. In contrast to the above, in the semiconductor device1din the present embodiment, the lead4has both functions as an inner lead embedded in the sealing resin part7and an outer lead exposed at the bottom surface7bof the sealing resin part7. That is, the bottom surface4dof each lead4is exposed at the bottom surface7bof the sealing resin part7and functions as an external coupling terminal (external terminal) of the semiconductor device id, and the end part (the surface of the lead4cut from the lead frame) on the opposite side of the side in opposition to the heat dissipating plate6of each lead4is exposed at the side surface of the sealing resin part7, and the side surface and the top surface of each of the other leads4are sealed by the sealing resin part7. The exposed surface (bottom surface4d) of the lead4at the bottom surface7bof the sealing resin part7has substantially a rectangular shape. Like that the bonding wire5is coupled to the top surface of the inner lead part4aof the lead4in the semiconductor devices1a,1cin the second and seventh embodiments, in the present embodiment also, to the top surface of each lead4sealed by the sealing resin part7, one end of the bonding wire5is coupled and the other end of the bonding wire5is coupled to the electrode PD of the semiconductor chip2. As a result, as in the second and seventh embodiments, in the present embodiment also, the electrodes PD and the leads4of the semiconductor chip2are electrically coupled via the bonding wires5.

In the semiconductor device1din the present embodiment, as can also be seen fromFIG. 65, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7and this is the same as the semiconductor device1cin the seventh embodiment. On the other hand, the bottom surface of the suspension lead10is not exposed at the bottom surface7bof the sealing resin part7as shown inFIG. 65, however, it is also possible to expose the bottom surface of the suspension lead10at the bottom surface7bof the sealing resin part7in another embodiment. When, the bottom surface of the suspension lead10is not exposed at the bottom surface7bof the sealing resin part7, as shown inFIG. 65, it is recommended to make the height position of suspension lead10higher than the heat dissipating plate6by providing a bending part, such as the bending part10b, to the suspension lead10, or to form the suspension lead10so as to be thinner than the heat dissipating plate6. As a result, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7, however, it is possible to prevent the suspension lead10from being exposed at the bottom surface7bof the sealing resin part7. If the suspension lead10and the heat dissipating plate6are made to have the same thickness without providing the bending part10bto the suspension lead10, it is possible to expose not only the bottom surface6bof the heat dissipating plate6but also the bottom surface of the suspension lead10at the bottom surface7bof the sealing resin part7.

In the semiconductor device1din the present embodiment, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7, however, the die pad3and the member9at the part where the semiconductor chip2is bonded by the adhesive8are sealed in the sealing resin part7and not exposed from the sealing resin part7, and this is the same as the semiconductor device1cin the seventh embodiment. Because of this, in the present embodiment also, the bending part9bsimilar to that in the seventh embodiment is provided between each member9and the inner edge6cof the heat dissipating plate6and the bending part9bis bent so that the top surface3aof the die pad3and the member9is higher than the top surface6aof the heat dissipating plate6(that is, the bottom surface3bof the die pad3and the member9is higher than the bottom surface6bof the heat dissipating plate6). By the bending part9bformed integrally with the heat dissipating plate6and the member9, the height position of the member9and the die pad3is made higher than the height position of the heat dissipating plate6. As a result, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7, however, it is possible to prevent the bottom surface3bof the member9and the die pad3from being exposed at the bottom surface7bof the sealing resin part7.

Other configurations of the semiconductor device1din the present embodiment are substantially the same as those of the semiconductor device1cin the seventh embodiment, and therefore, their explanation is omitted here.

In the present embodiment also, as in the seventh embodiment, it is possible to conduct heat produced in the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member9and to dissipate the heat to the outside of the semiconductor device1d(under the semiconductor device1d) from the heat dissipating plate6, and thus, the heat dissipation characteristics of the semiconductor device1dcan be improved. When packaging the semiconductor device1don the packaging substrate PWB, if the bottom surface6bof the heat dissipating plate6exposed at the bottom surface7bof the sealing resin part7is joined (solder coupled) to the terminal TE of the top surface of the packaging substrate PWB, it is possible to efficiently dissipate heat from the bottom surface6bof the heat dissipating plate6to the packaging substrate PWB, and therefore, the effect to improve the heat dissipation characteristics of the semiconductor device1dcan be magnified further.

In the present embodiment also, as in the seventh embodiment, the bottom surface6bof the heat dissipating plate6is exposed at the bottom surface7bof the sealing resin part7, however, the die pad3and the member9that mount the semiconductor chip2are not exposed from the sealing resin part7. Because of this, compared to the case where the die pad3and the member9are exposed at the bottom surface7bof the sealing resin part7, it is possible to more suppress or prevent the degradation of the moisture resistance of the semiconductor device. Consequently, it is possible to improve the heat dissipation characteristics while suppressing the degradation of the moisture resistance.

Ninth Embodiment

FIG. 69is a plan perspective view (top view) of a semiconductor device1ein the present embodiment, showing a state where the sealing resin part7is viewed perspectively.FIG. 70is a plan perspective view (top view) of the semiconductor device1ewhen the semiconductor chip2and the bonding wire5are removed (viewed perspectively) inFIG. 69and for easier understanding, the position where the semiconductor chip2is mounted (arranged) is indicated by a dotted line.FIG. 71toFIG. 73are each a section view (side surface section view) of the semiconductor device1e. The section view at the position along the A4-A4line shown inFIG. 70substantially corresponds toFIG. 71, the section view at the position along the B4-B4line shown inFIG. 70substantially corresponds toFIG. 72, and the section view at the position along the C4-C4line shown inFIG. 70substantially corresponds toFIG. 73.

In the present embodiment, the structure in the second embodiment is applied to an SOP (Small Outline Package) semiconductor device. Because of this, the semiconductor device1ein the present embodiment shown inFIG. 69toFIG. 73is a resin-sealed semiconductor package, that is, an SOP semiconductor device, and different from the semiconductor device1ain the second embodiment in the following points.

The semiconductor device1ain the second embodiment is a QFP semiconductor device and from the four sides (side surface constituting the four sides) of the sealing resin part7in the shape of a plane rectangle, the outer lead parts4bof the leads4project, respectively. Then, the four suspension leads10are provided and the four suspension leads10extend in the sealing resin part7from the four corner parts of the heat dissipating plate6in the form of a frame toward the four corner parts of the sealing resin part7in the shape of a plane rectangle.

In contrast to the above, in the semiconductor device1ein the present embodiment shown inFIG. 69toFIG. 73, the outer lead parts4bof the leads4project, respectively, from the two long sides (side surface constituting the two long sides) of the sealing resin part7in the shape of a plane rectangle having long sides and short sides. Then, the two suspension leads10are provided and the two suspension leads10extend in the sealing resin part7from the center part of the two sides in opposition to each other of the heat dissipating plate6in the form of a frame toward the center part of the two sides in opposition to each other of the sealing resin part7in the shape of a plane rectangle.

Other configurations of the semiconductor device1ein the present embodiment are substantially the same as those of the semiconductor device1ain the second embodiment, and therefore, their explanation is omitted here.

As in the second embodiment, in the present embodiment also, it is possible to dissipate heat in the semiconductor chip2through a path through which heat is dissipated from the back surface2bof the semiconductor chip2to the heat dissipating plate6via the adhesive8, the die pad3, and the member9, and the heat is dissipated from the heat dissipating plate6to the inner lead part4avia the sealing resin part7, in addition to the path through which heat is dissipated from the side surface of the semiconductor chip2to the inner lead4avia the sealing resin part7as the second heat dissipation path (heat dissipation path shown by the arrow H2inFIG. 8). Because of this, it is possible to improve the heat dissipation characteristics of the semiconductor device1e.

The invention developed by the inventors is specifically explained as above based on the embodiments, however, it is needless to say that the present invention is not limited to the embodiments and there can be various modifications in the scope without departing from its gist.

The present invention is suitable when applied to a semiconductor device in the form of a semiconductor package and a method of manufacturing the same.