Dielectric emitter with PN junction

A method for emitting electrons includes the steps of applying a voltage to an electron source to cause hot electrons to be generated with the source, and applying an electric field to cause at least a portion of the hot electrons to be emitted from the electron source.

FIELD OF THE INVENTION

The invention is in the microelectronics field. The invention particularly concerns emitters and devices incorporating emitters.

BACKGROUND OF THE INVENTION

Emitters have a wide range of potential applicability in the microelectronics field. An emitter emits electrons in response to an electrical signal. The controlled emissions form a basis to create a range of useful electrical and optical effects. Prior conventional emitters include spindt tip cold cathode devices as well as flat emitters.

Challenges presented by spindt tip emitters include their manufacturability and stability over their service life. Manufacturing of spindt tip emitters requires a number of relatively difficult deposition steps, with the result that it is generally expensive and time consuming. Once formed, a tip may be unstable as it can change as it is operated, and is subject to damage if not operated in high vacuum.

Traditional flat emitters are comparably advantageous because they present a larger emission surface and can be operated in less stringent vacuum environments. Flat emitters include a dielectric emission layer that responds to an electrical field created by a potential applied between an electron source and a thin metal layer on either side of a dielectric layer. Electrons travel from the electron source to the conduction band of the dielectric somewhere in the dielectric layer. Once into the conduction band, the electrons are accelerated towards the thin metal. The electrons then travel through the thin metal and exit the emitter.

Problems and unresolved needs remain with flat emitters, however.

SUMMARY OF THE INVENTION

According to the invention, an emitter includes a PN junction, a conducting layer, and a dielectric layer sandwiched between the PN junction and the conducting layer.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to emitters, emitter devices, methods for emitting electrons, and methods for making emitters. An exemplary method of the invention includes a two step emission process wherein a PN junction is reverse biased to generate hot electrons, and a high electric field then applied to the PN junction to cause at least a portion of the hot electrons to be emitted. An exemplary emitter of the invention includes a PN junction with a thin dielectric layer formed over a portion of its surface. A thin metal layer is then formed over the dielectric layer. When the PN junction is reverse biased, hot electrons are generated. Applying a voltage to the thin metal layer creates an electric field across the thin dielectric, and causes a portion of the hot electrons to tunnel through the thin dielectric layer and to be emitted. Other exemplary invention embodiments may be directed to emitters, methods for making emitters, and devices incorporating an emitter, with examples including an integrated circuit, a display device, and a memory device.

Turning now to the drawings,FIG. 1shows a preferred emitter embodiment of the invention in cross section generally at10. The emitter10includes the PN junction shown generally at12. A conducting layer14that may be made of Aluminum, for example, forms a base of the PN junction12. The exemplary PN junction12also includes a first P+ silicon region16, a P silicon region18, and a second P+ silicon region20arranged generally as shown. The P+ region20is generally cylindrical and is surrounded about its perimeter by a portion of the P region18.

A generally ring shaped N+ silicon region22is near the upper surface of the PN junction12. Interior to the ring shaped N+ region22is a shallower second N+ silicon region24. The shallow N+ region24may have a thickness of between about 50 and 200 Angstroms, and by way of particular example may be about 100 Angstroms thick. The shallow N+ region22preferably has a top surface that is substantially flat. The term “substantially flat” as used herein with reference to a surface is intended to broadly refer to a condition of a surface that is substantially free of bumps, ridges, and other irregularities.

The P+ and P regions16-20, as well as the N+ regions22-24are made of an electron source, with silicon and poly silicon being exemplary materials. As will be appreciated by those skilled in the art, creation of the N+, P+, and P regions16-24is achieved through doping of the silicon with a relatively small number of impurity atoms. As used herein a “+” indicates an enhanced level of doping. Factors such as the type and concentration of the doping impurity and the energy used in implanting the impurity determines whether a region becomes an N/N+ or P/P+ region.

A dielectric layer26is formed on a top surface of the PN junction, and preferably in a generally circular or ringed shape to define a well28. Exemplary dielectrics include nitrides and oxides of Si or Ti. The dielectric layer26and its interior well28may be formed using a standard formation process such as deposition with masking or the like. Within the well28, a thin dielectric layer30is formed over the shallow N+ region24. The thin dielectric layer30may be made of the same material as the dielectric layer26, or may be made of a different material.

Designers applying the invention will understand that an optimized thickness of the thin dielectric layer30produces maximum emission efficiency. The thin dielectric layer30may have a thickness of between about 5 to about 25 nm for example, and by way of particular example may be about 100 Angstroms thick. Thinner layers reduce the tunneling resistance of the layer and produce emissions at lower voltages, while increasing the thickness increases its tunneling resistance. The layer30may be made of a low-K dielectric for some applications. One low K dielectric layer30is a porous layer having nano-size spacing to enhance tunneling. The layer30can be made porous by methods generally known in the art.

A conductor layer32is formed over the thin dielectric layer30, and may extend out of the well28to overlie a portion of the layer24for convenience of formation and electrical connection. The conductor layer32may be made of a metal or metal alloy for example, with an exemplary layer32made of Al, Ta, Pt or alloys thereof. The portion of the conductor layer32that sits in the well28should be of a thickness large enough to provide a sufficient electric field and yet be thin enough so as to permit electron and photon emissions to escape through the layer32. Artisans will appreciate that the thickness of the layer32portion in the well28may be selected according to various design factors such as applied bias voltage, thickness of the dielectric layer portion30, materials of construction, end use of the emitter, and the like. By way of example, the portion of the layer32that sits in the well28may be between about 3 and 15 nm thick, and by way of particular example may be about 10 nm thick.

Also, the conductor layer32may be provided with nanohole openings to enhance emission level density. These nanohole openings will provide an emission path for electrons that tunnel through the dielectric layer portion30but that do not normally have sufficient energy to escape through the conductor layer32. The nanohole openings may be created during an annealing process, and may have any of a variety of shapes, including but not limited to circular, crack-like, fissures, voids, serpentine, and the like. The nanohole openings may be uniform or distributed in size. The distribution of the nanoholes is preferably substantially uniform across the area of the conductor layer32in the well28. Exemplary dimensions for the nanoholes include a width of about 1 to about 50 nanometers, and a length of about 10 to about 100 nanometers for crack-like and fissure shaped holes. Length is generally less important than width when considering crack-like and fissure shaped nanoholes. For nanoholes that are generally circular, or that may be more closely approximated as a circle than a crack, the holes may have a diameter of about 1 to about 50 nanometers.

Two connections are established, with a first34between the metal layer14and the N+ region22, and a second36between the metal layer14and the conductor layer30. The connection34has been illustrated schematically inFIG. 1as extending through a passage in the oxide layer26; this may be achieved in practice through etching or the like. The connection34functions to create two diodes: a contact diode and an emission diode. The contact diode has a terminal formed by the generally ring shaped N+ region22. The shallower N+ region within the ring shaped contact diode forms the emission diode.

The N+ region22may be doped at a higher concentration than the shallower N+ region24. A higher doping in the region22is generally desirable to enhance connection and reduce series resistance with regards to the connection34. Doping in the shallower region24may be at a lower concentration selected to achieve a good PN junction emission efficiency, and to raise the breakdown voltage threshold. Particular doping concentrations will vary depending on factors as are generally known in the art such as the end use application, applied voltages, materials and doping impurities used, and the like.

By way of example, the region22may be doped with Arsenic at a concentration of about 5×1015atoms/cm2, the shallower N+ region24may be doped with Arsenic at a concentration of about 2×1015atoms/cm2, and the P+ region20may be doped with Boron at a dosage of about 3×1013atoms/cm2. After doping the various regions may be thermally activated at about 950° C. for a period of about 30 minutes, for example.

Exemplary emitters of the invention offer many advantages and benefits. For example, the surface of the N+ region24may be substantially flat to achieve very low scatter of emitted electrons. Further, very high densities of emission centers may be achieved in the region24. As used herein, the term “emission center” is intended to broadly refer to a site from which a hot electron may be emitted. The term “hot electron” as used herein is intended to broadly refer to an electron that is not in thermal equilibrium with the lattice. Emission centers from the region24may be of the order of the atom density at the surface. For example, it is believed that practice of the invention may potentially yield emission center densities in the doped N+ silicon region24of greater than about 105per micron2, with a concentration of about 106per micron2believed possible.

The exemplary emitter10will be useful to illustrate an exemplary method of emitting electrons of the invention. A potential is applied across the connection34at a level below the avalanche voltage of the PN junction12to reverse bias the junction12. This causes hot electrons to be generated within the junction12, and in particular near the junction interface of the regions24and20. The hot electrons travel at a velocity in the general direction towards the thin dielectric layer portion30. Maintaining the applied potential below the avalanche voltage ensures that the PN junction will enjoy a relatively long service life and greatly reduces the possibility of junction breakdown.

Applying a potential across the connection36results in a voltage being applied to the conductor layer32and creating an electric field across the thin dielectric layer30. The magnitude of the potential applied is preferably sufficient to generate a high field across the thin dielectric layer30. By way of example only, a potential may be applied to cause a high field of at least about 107V/cm to be created across the dielectric layer30. The high field causes a portion of the hot electrons to be accelerated from their initial velocity towards the dielectric layer30, to tunnel through the thin dielectric layer30, and to be emitted from the conductor layer32. It is noted that the field across the layer30does not necessarily require that the connection36be between the base layer14and the conductor32. For example, the connection36could link the layers22and32and still cause a field to be created across the layer30.

The magnitudes of the potentials applied across the connections34and36may be selected based on design and application factors. Factors such as the materials used and the thickness of the PN junction layers14-24, the dielectric layer30, the conducting layer32, the desired emission current, and the like may be considered. It is believed that methods and emitters of the invention can be configured to provide an emission efficiency of at least about 6%.

An exemplary method of the invention thereby uses a two stage emission process: a first stage applies a voltage to an electron source to generate hot electrons in the source, and a second stage applies an electric field to cause at least a portion of the electrons to be emitted from the electron source. In a preferred method embodiment, the electron source is a PN junction, with a voltage applied to it below its avalanche voltage to cause hot electrons to be generated. Methods of the invention offer several advantages. For example, by operating at a potential that is below the avalanche voltage of the PN junction, a relatively uniform turn-on voltage is available. This provides for improved emission current control. This may also be desirable, for example, when a plurality of emitters is present in a device. Other advantages of methods of the invention will be apparent to those knowledgeable in the art.

There are a wide-range of potential uses of emitters and methods for emitting electrons of the invention due to the general utility of emissions as a basis for electrical, electrochemical, and electro optical effects. Further, emitters of the invention are easily incorporated into integrated circuit fabrication techniques. A few particularly preferred applications of emitters and methods of emitting electrons of the invention will now be discussed by way of example.

FIG. 2is an exemplary schematic of an exemplary emitter device of the invention including an emitter shown generally at200useful to generate focused electrons204to impact a target202. In this application, the emissions206from the emitter200of the invention are focused by an electrostatic focusing device or lens208. The emitter200generally comprises an electron source such as a PN junction shown generally at210. The PN junction210includes a P region212, an N region214, and an underlying metal substrate layer216. A generally circular or ring shaped dielectric layer218such as a metallic oxide overlies a portion of the N region214, with a well defining therein. A thin dielectric layer portion220sits at the base of the well over a portion of the N region214. A thin metal layer222is formed over the dielectric layer portion220.

When a potential of less than the avalanche voltage is applied across the connection224, hot electrons are generated near the junction interface. Applying a potential across the connection226charges the conductor layer222and subjects the thin dielectric layer portion220to a high electric field. The high field causes a portion of the hot electrons206to tunnel through the layer220and to be emitted from the conductor layer222.

Within the lens208, an aperture228in a conductor can be set at a predetermined voltage that can be adjusted to change the focusing effect of the lens208. Those skilled in the art will appreciate that the lens208can be made from more than one conductor layer to create a desired focusing effect. The emissions206are focused by the lens208into a focused beam204directed onto the target anode medium202. The target anode medium202is set at an anode voltage Va. The magnitude of Vawill depend on factors such as the intended emitter use, the distance between the anode medium202and the emitter200, and the like.

For example, with the anode medium being a recordable memory medium for a storage device, Vamight be chosen to be between about 500 and about 2000 volts. The lens208focuses the electron emissions206by forming an electric field in the aperture220in response to voltage Vlwithin its aperture. By being set at a proper voltage difference from the potential across the connection226, the emitted electrons206from the emitter200are directed to the center of the aperture and then further attracted to the anode medium202to form the focused beam204.

The anode medium202may be configured as appropriate for any of several emitter applications, with two preferred applications including the target medium202being a visual display or a memory. If the anode medium202comprises a display, the focusing of the beam onto the anode medium202can be used to produce an effect to stimulate a visual display. Similarly, if the anode medium202comprises a memory medium, the electrochemical properties of the medium may be changed through the focused beam204. These changes may be “coded” in a binary or other manner to store retrievable information, for instance by spatially organizing portions of the anode medium202and then selectively changing some of those portions through the emitted electrons204. A visual display medium and a memory medium may employ a plurality of emitters200arranged in an array, and may employ a mover such as a micropositioner driven by a motor for moving one or the other of the emitter200and the anode medium202relative to the other. Also, a control circuit may be used to control the emitters200and/or other components.

FIG. 3, for example, is a schematic of an exemplary integrated circuit embodiment300of the invention that includes at least one and preferably a plurality of integrated emitters302arranged in an array or other geometrical manner. An emitter control circuit304is integrated onto the integrated circuit300and used to operate the integrated emitters302.

FIG. 4is a schematic embodiment of a display application using an integrated emitter400of the invention. In particular, this embodiment entails a plurality of PN junction flat emitters402formed in an integrated circuit404. Each of the emitters402emits electrons, as generally illustrated by the upwardly directed arrows of FIG.4. An anode structure406having a plurality of individual pixels408that form a display410receives the emitted electrons. The pixels408are preferably a phosphor material that creates photons when struck by emissions from the emitters402. Other components such as a power supply, a control circuit, and the like may also be provided.

A particular preferred memory device is schematically shown inFIGS. 5A and 5B. The memory device includes a plurality of flat emitters500of the invention that include at least a PN junction, a dielectric layer, and a thin metal layer. In this exemplary embodiment, the plurality of emitters500are integrated into an integrated circuit (IC)502. A lens array504of focusing mechanisms505that may be aligned with the integrated emitters500is used to create a focused beam506of electrons that affects a recording surface media508. The surface media508is linked to a mover510that positions the media508with respect to the integrated emitters500and/or the lens array504. Preferably, the mover510has a reader circuit512integrated within.

The reader circuit512is illustrated inFIG. 5Bas an amplifier514making a first ohmic contact516to the media508and a second ohmic contact518to the mover510, preferably a semiconductor or conductor substrate. When a focused beam506strikes the media508, if the current density of the focused beam is high enough, the media is phase-changed to create an affected media area520. When a low current density focused beam506is applied to the media508surface, different rates of current flow are detected by the amplifier514to create reader output. Thus, by affecting the media508with the energy from the emitter500, information is stored in the media using structural phase changed properties of the media. An exemplary phase-change material is InSe.

Still additional aspects of the invention are directed to methods for making emitters.FIG. 6is a flowchart illustrating steps of an exemplary method600of the invention. In describing the exemplary method600, consideration of emitters of the invention such as those discussed herein and illustrated inFIGS. 1-5will be helpful. Indeed, those knowledgeable in the art will appreciate that description of those emitters and devices will be useful in illustrating alternate steps of methods of the invention.

Turning now toFIG. 6, the method600includes a step of providing a PN junction having a substantially flat surface (block602). A dielectric layer is then formed over the PN junction substantially flat surface (block604), with a thin conductor layer then formed over the dielectric layer (block606). The PN junction, dielectric layer, and thin conductor layer may be, by way of example, consistent in materials, dimensions, and configuration with the elements12,30, and32, respectively, of the emitter10illustrated in FIG.1.

The method600next comprises the step of forming an electrical connection to the PN junction configured to apply a voltage to the PN junction for reverse biasing the junction (block608). The connection is preferably configured to apply a voltage below the avalanche voltage of the PN junction. The method also includes a step of forming an electrical connection to the thin conductor layer configured to charge the layer to generate a high field across the dielectric layer (block610). Other exemplary method steps may include providing targets, focusing means and integrated circuits, for example, as will be appreciated in considering the exemplary emitter devices ofFIGS. 2-5.

While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims. For example, it will be appreciated that many applications in addition to a memory and a visual display may be practiced using an emitter of the invention.