Digitizer with enhanced accuracy

Systems and techniques for converting an analog input signal to a digital code are described. A system includes a differential stage to produce a sign bit indicative of a sign of the analog input signal and to generate a first analog signal that is approximately equal to an absolute value of the analog input signal. The system also includes an analog-to-digital converter (ADC) to convert the first analog signal to a second digital code representing a magnitude of the analog input signal and a controller to combine the second digital code and the sign bit to produce a first digital code.

TECHNICAL FIELD

This patent application relates to improving the performance of an analog-to-digital converter, and more particularly to improving its accuracy and dynamic range.

BACKGROUND

A bipolar analog-to-digital converter (ADC) converts an analog input signal to a digital output code that can represent both positive and negative values. Although there are different ways to represent a negative number as a digital code, most representations use the most significant bit (MSB) of the code to signify whether the represented value is positive or negative. The MSB is sometimes referred to as a “sign bit”. Examples of binary representations of negative numbers include a one's complement representation and a two's complement representation.

The transfer function of an ADC is a plot of the code generated at the ADC output as function of the input signal value. Such a plot is not continuous but is a plot of 2Nsteps, where N the number of bits in the digital output. For an ideal ADC, a single straight line can be drawn through the points at each code-transition boundary, beginning at the origin of the plot.

FIG. 1shows a plot2of an ideal transfer function4for a 3-bit ADC with reference points at code transition boundaries. The ADC in this example produces a total of eight steps that each represents a value of the analog input signal as a two's complement binary code. In this case, the MSB (i.e., the first bit of each code) signifies whether the code represents a negative or a positive value. For example, all of the digital codes having an MSB equal to “1” represent negative values, and all of the digital codes having an MSB equal to “0” represent either a positive value or zero. The transition occurs at one code width, which is equal to a least significant bit (LSB). The actual value of an LSB is equal to Vref/2(N−1), where Vrefis the reference voltage that determines the full-scale range of the ADC (i.e., the range of analog input values that ADC can convert to digital values). The resolution of the ADC, which determines the best accuracy to which the ADC can represent an analog input value, is equal to the value of the LSB. In the example shown inFIG. 1, the resolution is Vref/4.

SUMMARY

The invention provides methods and systems, including computer program products, for converting an analog input signal to a digital code.

In general, in one aspect, the invention features a system that includes a differential stage to produce a sign bit indicative of a sign of the analog input signal and to generate a first analog signal that is approximately equal to an absolute value of the analog input signal. The system also includes an analog-to-digital converter (ADC) to convert the first analog signal to a second digital code representing a magnitude of the analog input signal and a controller to combine the second digital code and the sign bit to produce a first digital code.

In general, in another aspect, the invention features a method for converting an analog input signal to a first digital code. Using a differential stage, a sign bit indicative of the sign of the analog input signal is produced and a first analog signal that is approximately equal to the absolute value of the analog input signal is generated. Using an analog-to-digital converter (ADC) the first analog signal is converted to a second digital code representing the magnitude of the analog input signal. Using a controller coupled to the differential stage and the ADC, the second digital code and the sign bit are combined to produce the first digital code.

Embodiments may include one or more of the following. The sign bit may be a most significant bit of the first digital code, and the first digital code can represent both positive and negative values of the analog input signal. For example, the first digital code may be one of a one's complement representation and a two's complement representation. A voltage buffer coupled between the differential stage and the ADC, in which the voltage buffer is configured to provide an output impedance that is less than an input impedance of the ADC, may be provided.

The differential stage may include a differential pair that includes a first transistor and a second transistor. A first applied voltage that is substantially equal to the analog input signal may be applied to the base of the first transistor and a second applied voltage that is substantially equal in magnitude and opposite in sign to the analog input signal may be applied to the base of the second transistor. The collectors of the first and second transistor may be configured to conduct current when the first and second applied voltage are greater than a threshold voltage (e.g., zero) and the sum of currents conducted by the collectors of the first and second transistors is constant. The differential stage may also include a differential to single-ended converter to select a value of the sign bit in response to detecting a current flowing through one of the collectors of the first and second transistors. For example, the differential to single-ended converter may be configured to select the value of the sign bit to indicate that the analog input signal is positive in response to detecting a current flowing through the collector of the first transistor and select the value of the sign bit to indicate that the analog input signal is negative in response to detecting a current flowing through the collector of the second transistor.

The emitters of the first and second transistor may produce voltages that follow the first and second applied voltages, respectively, when the collectors of the first and second transistor conduct current. The emitters of the first and second transistors may also be connected at a node that carries the first analog signal that is approximately equal to the absolute value of the analog input signal and that includes voltages produced at the emitters of the first and second transistors. A current source (e.g., a current mirror) may be coupled to the emitters of the first and second transistors.

Third and fourth transistors configured to reduce a Miller effect of a parasitic capacitance between the base and the collector of the first and second transistors, respectively, may be provided. For example, the third and fourth transistors may receive fixed voltages at their bases, and their collectors may be coupled to a voltage supply. The emitter of the third transistor may be connected to the collector of the first transistor, and the emitter of the fourth transistor may be connected to the collector of the second transistor.

DETAILED DESCRIPTION

Testing equipment for characterizing the performance of various electronic devices often includes one or more ADCs. For testing some state-of-the-art devices, the best available ADCs at the time the testing equipment is designed may not have sufficient resolution and dynamic range. Replacing the ADCs with those having improved resolution and dynamic range may be prohibitively expensive and/or require modifications to other parts of the testing equipment.

FIG. 2shows a composite ADC10that can improve resolution and dynamic range of an N-bit ADC14by adding an extra bit to the output of an existing ADC14to produce an overall output having N+1 bits. In addition to the ADC14, the composite ADC10includes an external differential stage12coupled to the ADC14, and a processor26coupled to the ADC14and the differential stage12. A differential to single-ended converter32within the differential stage12produces a sign bit indicative of the sign of an analog input signal received at an input pin30a. The input pin30ais connected to the positive terminal of an analog voltage source and the input pin30bis connected to the negative terminal of the source and therefore receives a negated version of the analog input signal. At output pins34a–b, the differential stage12produces an analog signal that is equal to the absolute value of the analog input signal. This signal is received from output pin34aby the ADC14, which in turn converts the absolute value to a digital code. The processor26then combines the sign bit generated by the differential to single-ended converter32and the digital code produced by the ADC14to yield an overall N+1-bit output code that represents the analog input. The sign bit is the MSB of the overall output code. The overall output code may conform to any format that can represent both negative and positive values. Examples of formats include one's complement and two's complement representations. As will be discussed in more detail below, because the ADC14converts only positive analog values, the codes that a conventional ADC would have used to represent negative numbers are used by the ADC14to represent positive values. As a result, the resolution of the composite ADC10is doubled without reducing its dynamic range below that of the conventional ADC. Alternatively, the dynamic range of the ADC14can be half of that of a conventional ADC yet the composite ADC10will still exhibit the same dynamic range as the conventional ADC because the differential stage12supplies an extra bit.

In addition to the input pins30a–b, to the differential to single-ended converter32, and to the output pins34a–b, the differential stage12includes a differential pair16that extracts the sign of the input analog signal; voltage followers18,20, and22; multiple current sources28a–d(referred to collectively as “current sources28”), a dc power supply38, and ground pins36connected to ground. All of the transistors shown inFIG. 2are bipolar-junction transistors (BJTs). It is possible to replace the BJTs in this application by field effect transistors (FET).

The differential pair16has two functions: it extracts the sign of the analog input signal40and produces the absolute value of the analog input40as an input to the ADC14. It includes a pair of telescopic cascodes. The first telescopic cascode includes two npn transistors T1and T3and a resistor R1, and the second telescopic cascode includes two npn bipolar transistors T2and T4and a resistor R2. The input pins30aand30bare connected to opposite polarities of an analog voltage source and to the respective bases of transistors T1and T2. The positive polarity of the analog source40, which generates the analog input signal, is received at the base of transistor T1and the negative polarity of the source, which generates a signal that is equal in magnitude but opposite in sign to the analog input signal, is received at the base of transistor T2. The voltages at the bases of transistors T3and T4are fixed to a DC bias circuit (not shown) that are derived from the dc power supply38.

The circuit that includes transistors T1and T2is a trans-impedance linear amplifier. So the current will change smoothly. When the input voltage varies, the base current of both transistors T1and T2vary. The base current variation is proportional to voltage variation. As a result, the collector currents of the transistors T1and T2will also vary proportionally to the input voltage variation. The output current variation is β times the input current variation. Therefore, the voltage gain is β times the ratio of the load impedance to the input impedance. The sum of the two collector currents is almost constant due to the current source. The differential to single-ended converter thus also acts as an amplifier.

When the total gain is high enough and the output of either transistors T1and T2is saturated, the differential pair16could be approximate to a sign detector. At values greater than zero, the analog input signal received at the base of transistor T1is large enough to cause the voltage between the base and emitter of the transistor T1to exceed a threshold voltage, causing current to flow through the collector of the transistor T1. A positive analog input value causes a negative voltage to be applied to the base of the transistor T2. When the input voltage to transistor T2falls below the threshold voltage, the transistor T2is in the cutoff mode, and no current flows through the transistor T2or through the transistor T4. If, however, the analog input value is negative, the transistor T1is in the cutoff mode (i.e., no current flows through the transistors T1and T3), and a positive voltage is applied to the base of the transistor T2. If the positive voltage exceeds the threshold voltage of the transistor T2, a current flows through the collectors of the transistors T2and T4. At any given time, the current flowing through the transistors T1and T3may be larger than that flowing through the transistors T2and T4or vice versa. Thus a flow of current through the transistors T1and T3that is greater than a flow of current through the transistors T2and T4indicates a positive analog input voltage, and a flow of current through the transistors T2and T4that is greater than a flow of current through the transistors T1and T3indicates a negative analog input voltage. The differential to single-ended comparator32determines whether more current is flowing through transistors T1and T3or through the transistors T2and T4and selects the value of the sign bit to be either “1” or “0” based on the determination. For example, if the differential to single-ended converter detects more current flowing through the transistors T1and T3, it produces a sign bit of “0” to signify that the analog input is positive. Conversely, if the differential to single-ended comparator32detects more current flowing through the transistors T2and T4, it produces a sign bit equal to “1” to signify that the analog input is negative. In some embodiments, the differential to single-ended comparator32determines whether a voltage drop has occurred across the resistor R1(caused by current flowing through transistors T1and T3) or across the resistor R2(caused by current flowing through transistors T2and T4). In some embodiments, the differential to single-ended comparator32produces a sign bit of “0” to represent a negative analog input and a sign bit of “1” to represent a positive analog input.

The magnitude of the analog input is controlled at output pin34aby the transistors T1and T2and at output pin34bby the transistors T5and T6. The transistors T7and T8buffer the signals before they are transmitted through the output pins34aand34b. The signals produced at the output pins34aand34bare complementary signals that are out of phase by 180 degrees. The transistors T1, T2, T5, and T6are each arranged in a configuration referred to as an “emitter follower” configuration. In an emitter follower configuration, the input signal is applied to the base and the output signal is taken from the emitter. The ratio of the voltage at the emitter to the voltage at the base closely approaches unity, which means that the signal at the emitter closely follows that at the base. The process by which the magnitude of the analog input is generated by the transistors T1and T2at the output pin34aand by the transistors T5and T6at the output pin34bis described in further detail with respect toFIG. 3.

The transistors T1and T2are biased with a constant-current source28bhaving a high output impedance. An optional resistor R3is provided to introduce a DC offset if needed. The value of R3is usually small compared with the current source so the signal loss is negligible. The collector currents of the transistors T1and T2are received at the emitters of T3and T4, respectively. The current at each of the collectors of the transistors T1and T2are approximately equal to the current at each of their respective bases multiplied by a gain factor β which is approximately between 100 and 300. The load resistances seen by the transistors T1and T2are the input resistances at the emitters of transistors T3and T4. The low load resistance seen by the transistors T1and T2considerably reduces the Miller effect (also referred to as the Muller effect) of parasitic capacitances between their bases and collectors. The Miller effect is defined below.

The following discusses in further detail how the transistors T3and T4reduce the Miller effect in the transistors T1and T2. If, for example, the transistor T3were omitted from the differential pair16, the collector of the transistor T1would be connected directly to the resistor R1. When the voltage at the base of the transistor T1increases, the current through the base is amplified in proportion to the base current by gain factor β, as discussed above. As the collector current through the transistor T1increases with the base current, the voltage drop across the resistor R1, which is equal to the collector current multiplied by the resistance value of R1, also increases. Because there is a parasitic capacitance between the collector and base of the transistor T1, a change in voltage across the resistor R1causes the voltage at the base of the transistor T1to change as well. Namely, a drop in voltage across the resistor R1causes the voltage at the base of the transistor T1to drop. Because the voltages at either side of the parasitic capacitance are in a ratio approximately equal to the gain factor β, the parasitic capacitance is effectively increased by the gain factor β as well. This phenomena is referred to as the Miller effect. Higher signal frequencies increase the effect of the parasitic capacitance, causing an effective short circuit between the base and the collector. This in turn degrades the accuracy with which the emitter voltage of transistor T1follows the base voltage, which ultimately leads to poor performance of the differential pair16. Similarly, if transistor T4were omitted from the differential pair16, the performance of transistor T2at high frequencies would be impaired due to the Miller effect.

The addition of the transistor T3between the transistor T1and the resistor R1, and, similarly, the addition of the transistor T4between the transistor T2and the resistor R2prevents a voltage drop across the resistors R1and R2from affecting the base voltages of the transistors T1and T2, respectively. Because the base voltages of the transistors T3and T4are fixed, neither of those transistors experiences the Miller effect. The transistors T3and T4essentially act as current buffers that isolate the voltage changes across the resistors R1and R2. The transistors T3and T4pass the signal current to the differential to single-ended comparator32, while presenting low load resistances to the amplifying transistors T1and T2. The collectors of the transistors T3and T4carry currents that are almost equal to the currents at the collectors of the transistors T1and T2, respectively.

The voltage followers18and20are coupled, respectively, to the output pins34aand34b. The signals produced at the output pints34aand34bare complementary signals that are out of phase by 180 degrees. Voltage followers18and20are implemented by the transistors T8and T7, respectively, both arranged in an emitter-follower configuration. These two transistors provide a differential output if both are used or a single-ended output if one of them is used. Although the transistor T8is pnp and the transistor T7is npn, their functions are essentially the same. The voltage followers18and20exhibit a voltage gain that is smaller but close to unity, a high input resistance, and a low output resistance. The voltage followers18and20are included as the last stages of the differential stage12to provide a low output resistance. A low output impedance enables sufficient current to be provided to the ADC14, also referred to as the “load”.

The current sources28may be implemented using a variety of known circuits that include, for example, BJT transistors, MOS (metal-oxide semiconductor) transistors, operational amplifiers, diodes, and resistors. Examples of circuits for implementing the current sources28may include, but are not limited to, basic current mirrors, cascode current mirrors, Wilson current mirrors, and any combination thereof.

FIG. 3shows plots50a–dof the signals produced at key points in the differential stage12. Plots50b–cshows the signals at the emitters of the transistors T1and T2given a sinusoidal analog input shown in the plot50a. The plot50dshows the signal at the output pins34a–bthat is received by the ADC14.

As seen in the plots50a–c, when the analog input voltage is positive, the voltage at the emitter of the transistor T1(labeled VE1inFIG. 3) follows the voltage applied to its base (i.e., the analog input voltage a signal level greater than a predetermined threshold over Vi). The transistor T2, however, is in the cutoff mode when the input voltage is positive, and therefore the voltage at the emitter of transistor T2(labeled VE2inFIG. 3) is zero. Conversely, when the analog input voltage is negative, a voltage that is equal and opposite to the analog input voltage is applied to the base of the transistor T2, and the voltage VE2follows that voltage. The transistor T1is in the cutoff mode when the analog input voltage is negative, and thus the voltage VE1is zero. As the input signal switches between positive and negative voltages, the transistors T1and T2switch between active and cutoff modes such that the transistor T1is in the active mode when the transistor T2is in cutoff and vice versa. Voltage change is performed quickly without interfering with base voltages at the transistors T1and T2. As soon as the input voltage changes from positive to negative, or vice versa, the voltages at the emitters of the transistors T1and T2change quickly due to the current source28b. Because the emitters of the transistors T1and T2are tied together, the currents flowing through the transistors T1and T2share the same path. Therefore, the signal received by the ADC14, after passing through the voltage buffer18, is equal to the sum of the voltages VE1and VE2. A comparison of the plots50aand50dreveals that the input to the ADC14(labeled “V at pins34a–b” inFIG. 3) is approximately equal to the absolute value of the input voltage.

The transistors T5and T6of voltage buffer stage22are essentially the same as the transistors T1and T2except that because they are pnp, rather than npn. Therefore, the voltage polarities and current flow of the transistors T5and T6in the active mode are the reverse of that for the transistors T1and T2. Similar to the resistor R3, the resistor R4may optionally be used to increase the input resistance of the transistors T5and T6and to adjust the overall voltage gain between the collector and the base of each of the transistors T5and T6. The signals produced at the emitters of the transistors T5and T6in relation to a sinusoidal input voltages are essentially the same as those shown in plots50band50cin relation to transistors T1and T2. Furthermore, the signal produced at output pin34b, after passing though the voltage buffer20is approximately equal to the absolute value of the input voltage and exhibits a waveform akin to that shown in plot50d, except for that it is out of phase by 180 degrees.

FIG. 4shows a plot60of an ideal transfer function62of the composite ADC10that has the same dynamic range and resolution of a conventional ADC whose ideal transfer function4is shown inFIG. 1. Because the differential stage12provides the sign bit, the dynamic range of the ADC14can be half of that of the conventional ADC yet the composite ADC10will still exhibit the same dynamic range as that of the conventional ADC. In the example shown inFIG. 4, the code width of ADC14has been reduced from three bits to two bits.

FIG. 5shows a plot70of an ideal transfer function72of the composite ADC10having a dynamic range that is the same as that of a conventional ADC whose ideal transfer function4is shown inFIG. 1. However, the composite ADC10has twice the resolution of the conventional ADC. The code-width of the ADC14is the same as that of the conventional ADC, but because the ADC14converts only positive values, the codes that the conventional ADC uses to represent negative numbers can now be used in the ADC14to improve the resolution with which it represents positive values. In the example shown inFIG. 5, the resolution of the composite ADC10is Vref/8, which is twice that of the conventional ADC, which has a resolution of Vref/4 (seeFIG. 1).

The circuitry described herein, including the differential pair16, the voltage followers22,18, and20, the ADC14, differential to single-ended comparator32, processor26, and/or portions thereof, may be implemented as part of composite ADC10or as separate circuitry for use in conjunction with composite ADC10.

A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, another differential stage, similar to the differential stage12could be coupled to the input ADC10, which includes the differential stage12coupled to the input of ADC14. Similarly, any number of differential stages12could be cascaded together and coupled to the input of the ADC10. The ADC10could have a unipolar output or bipolar outputs.

In some embodiments, some or all of the BJT transistors could be replaced with metal-oxide-semiconductor (MOS) transistors or other types of transistors. Any number of bypass capacitors and other biasing circuitry could be included in the differential stage12. The transistors T1and T3could be arranged in a folded cascade configuration. Likewise, transistors T2and T4could be arranged in a folded cascade configuration. One or more of the resistors R1, R2, R3, and R4could be replaced with transistors configured to operate as resistors.

The conversion process performed by the composite ADC10is not limited to use with the hardware described herein. The conversion process can be implemented, at least in part, in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations thereof.

Method steps associated with implementing the conversion process can be performed by one or more programmable processors executing one or more computer programs to perform the functions of the processes. All or part of the conversion process can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) and/or an ASIC (application-specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer include a processor for executing instructions and one or more memory devices for storing instructions and data.