Processor and instruction execution method

A processor comprises a trusted execution environment and a non-trusted execution environment. The processor further comprises a common resource accessible in both the trusted execution environment and the non-trusted execution environment and an instruction processing device including circuitry configured to fetch an instruction for decoding and execute the decoded instruction. The instruction processing device includes circuitry further configured to determine consistency between a current execution environment of the processor and a resource status in response to a result from instruction decoding indicating that instruction involves access to the common resource, and load content corresponding to the current execution environment into the common resource in response to a determination that the current execution environment is inconsistent with the resource status, wherein the resource status indicates an execution environment corresponding to content in the common resource. A corresponding instruction execution method in the processor is also disclosed.

CROSS REFERENCE TO RELATED APPLICATION

This disclosure claims the benefits of priority to Chinese application number 201910111338.7, filed Feb. 12, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

In the fields of mobile Internet and Internet of Things, to improve security, a trusted world status is added as an operating mode of a processor. The trusted world status can be used to identify processors in a trusted world, system IPs with trusted attributes, and other sensitive and important software/hardware resources in a system. Resources in the trusted world are only accessible to members in the trusted world through hardware mechanisms, hence providing isolation between the trusted world and a non-trusted world and guaranteeing the confidentiality and integrity of the resources.

SUMMARY

According to some embodiments of the present disclosure, a processor is provided, having a trusted execution environment and a non-trusted execution environment, and comprising: a common resource accessible in both the trusted execution environment and the non-trusted execution environment; and an instruction processing device adapted to fetch an instruction for decoding and execute the decoded instruction. The instruction processing device further comprises a delay switching unit adapted to judge consistency between a current execution environment of the processor and a resource status when the result from instruction decoding indicates that the instruction involves access to the common resource, and load content corresponding to the current execution environment into the common resource if it is judged that the current execution environment is inconsistent with the resource status, wherein the resource status indicates an execution environment corresponding to content in the common resource.

According to some embodiments of the present disclosure, an instruction execution method in a processor is provided. The processor has a trusted execution environment and a non-trusted execution environment, and comprises a common resource accessible in all execution environments. The method comprises steps of: fetching and decoding an instruction; judging consistency between a current execution environment of the processor and a resource status if the result from instruction decoding indicates that the instruction involves access to the common resource, wherein the resource status indicates an execution environment corresponding to content in the common resource; loading content corresponding to the current execution environment into the common resource if it is judged that the current execution environment is inconsistent with the resource status; and executing the instruction.

DETAILED DESCRIPTION

To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure are described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are merely some rather than all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those with ordinary skill in the art without creative efforts should fall within the protective scope of the present disclosure.

Existing ways to isolate resources include using two copies of the resources, one in the trusted world and one in the non-trusted world. Having two copies of the resources, however, can be wasteful for memory storage. As a result, there can be a common resource shared by the trusted world and the non-trusted world.

When processors switch between the trusted world and the untrusted world, the common resource generally needs to be stored and cleared. If the common resource is not used after the switching, the storing and clearing operations are unnecessary, and the speed of the switching is reduced. This is especially an issue with interrupts that have high time requirements.

As a result, there is a demand for a new processor instruction execution solution, which can realize more flexible access to the common resource for accelerating response speed during switching.

According to the embodiments of the present disclosure, when execution environment switching is performed in the processor, a common resource is not stored at the same time; instead, the switching of the common resource is started only when it is found during the execution of an instruction that the instruction involves access to the common resource. As such, the speed of switching the execution environment can be accelerated by delaying the switching time of the common resource.

In addition, according to the embodiments of the present disclosure, a resource status flag indicating an execution environment of a current common resource is introduced. As such, when an instruction involving access to the common resource is executed, whether to switch the common resource can be determined according to whether a current execution environment flag is consistent with the resource status flag, thus providing a convenient common resource switching solution.

FIG. 1is a schematic diagram of an example processor, according to some embodiments of the present disclosure. As shown inFIG. 1, processor100comprises a trusted core110and a non-trusted core120. Trusted core110is a part of a trusted world, and non-trusted core120is a part of a non-trusted world. Trusted core110and non-trusted core120are logically independent for security purposes.

Processor100can perform execution in trusted core110, which can be a part of the trusted world. In this case, processor100is in a trusted execution environment and can access a trusted resource112. Trusted resource112can be unique to trusted core110. Processor100can also perform execution in non-trusted core120, which can be a part of the non-trusted world. In this case, processor100is in a non-trusted execution environment and can access a non-trusted resource122. Non-trusted resource122can be unique to non-trusted core120.

Processor100can further include a common resource130. Common resource130can be accessible in both the trusted world and the non-trusted world. According to some embodiments of the present disclosure, common resource130can include a variety of registers. In some embodiments, common resource130may not include security information. Common resource130can load different content according to whether processor100is in the trusted execution environment or the non-trusted execution environment.

In some embodiments, common resource130can include a general-purpose register GPR132. General-purpose register GRP132can be generally configured to transmit data and temporarily store data. General-purpose register GRP132can also participate in logic operations (e.g., arithmetic logic operations) and store operation results from the logic operations. Since a register can be accessed faster than a memory, a plurality of general-purpose registers may be designed in the modern processor architecture to accelerate the execution speed of the processor (e.g., processor100).

In some embodiments, common resource130can further include a vector general-purpose register VGPR134. Similar to the functions of general-purpose register GPR132, vector general-purpose register VGPR134can also be a register configured to transmit data and temporarily store data. In some embodiments, vector general-purpose register can participate in logic operations (e.g., arithmetic logic operations). In some embodiments, vector general-purpose register VGPR134may have more digits than general-purpose register GPR134does. In some embodiments, vector general-purpose register can be configured to be more efficient for floating point operations in a vector arithmetic unit VDSP or a floating-point arithmetic unit FPU.

In some embodiments, common resource130can further include a control register CR136. Control register CR136can control and determine an operating mode of the processor (e.g., processor110). In some embodiments, control register CR136can set system operation functions, I/O control, etc. In some embodiments, control register CR136in common resource130can generally be a register that does not include security information. A control register CR that includes security information can be set separately for trusted core110and non-trusted core120. For example, a trusted control register CR112can be set in trusted core110, and a non-trusted control register CR122can be set in the non-trusted core120.

In some embodiments, in order to support the switching between the trusted world and the non-trusted world, processor100can further include a trusted program status register T_PSR114and a non-trusted program status register NT_PSR124. In some embodiments, trusted program status register T_PSR can be located in trusted core110. In some embodiments, non-trusted program status register NT_PSR124can be located in non-trusted core120. In some embodiments, the two registers have basically the same results, and provide access in the same logical way. For example, both registers can provide access under the name of a program status register PSR. For example, when processor100is operating in the trusted execution environment or trusted world and instructions in processor100access program status register PSR, the instructions can access trusted program status register T_PSR114. When processor100is operating in the non-trusted execution environment or non-trusted world and instructions in the processor100access a PSR, the instructions can access non-trusted program status register NT_PSR124.

In some embodiments, trusted program status register T_PSR114and non-trusted program status register NT_PSR124can each have an execution environment indicator bit T. In some embodiments, T is one bit in the register. When a value of T is 1, it indicates that processor100is currently in the trusted execution environment or the trusted world. When the value of T is 0, it indicates that processor100is currently in the non-trusted execution environment or the non-trusted world. Therefore, in some embodiments, the bit T of trusted program status register T_PSR114can have a fixed value of 1, and the bit T of non-trusted program status register NT_PSR124can have a fixed value of 0. In some embodiments, processor100can be configured to switch between worlds by modifying the value of the bit T of program status register PSR.

In some embodiments, processor100can further include a security flag bit (not shown inFIG. 1) of the common resource. The security flag bit can be used for indicating the world to which the common resource currently belongs. The security flag bit of the common resource can be recorded in a number of different ways.

In some embodiments, trusted core110can further include a trusted processor configuration register T_PCR116. Trusted processor configuration register T_PCR116can include an STV bit. The STV bit can be configured as a security flag bit of the common resource, which can indicate the world to which the common resource belongs. When a value of the STV bit is 1, it indicates that the common resource belongs to the trusted world. When the value of the STV bit is 0, it indicates that the common resource belongs to the non-trusted world.

In some embodiments, the security flag bit of the common resource can be implemented using a common resource stack-push flag bit in another register. For example, when a value of the common resource stack-push flag bit is 1, it indicates that the common resource has been pushed to a stack by the trusted world, so that the common resource can be used in the non-trusted world without a need to trigger stack push operations in the trusted world. In other words, the STV value of the trusted processor configuration register T_PCR116is set to 0. Similarly, when the common resource stack-push flag bit is 1, it means that the common resource has been pushed to a stack or initialized by the non-trusted world, and thus the common resource can be used in the trusted world without the need to trigger the stack push operation in the non-trusted world.

In some embodiments, processor100can further include a trusted entry base register T_EBR118in trusted core110and a non-trusted entry base register NT_EBR128in non-trusted core120. A base address of an entry position of a storage space in the trusted world can be stored in trusted entry base register T_EBR118. Similarly, a base address of an entry position of a storage space in the non-trusted world can be stored in non-trusted entry base register NT_EBR128.

In some embodiments, the storage spaces of the trusted and non-trusted worlds each can be implemented as a stack. Therefore, base addresses of a trusted stack and a non-trusted stack can be stored in the trusted and non-trusted entry base registers respectively. Contents in common resource130can be stored in the corresponding stack according to the world to which the site of the common resource belongs. When the site of the common resource belongs to the trusted world, the content of the common resource can be pushed onto the trusted stack according to the base address of the trusted stack in trusted entry base register T_EBR118if the content of the common resource is to be stored. Similarly, when the site of the common resource belongs to the non-trusted world, the content of the common resource can be pushed onto the non-trusted stack according to the base address of the non-trusted stack in non-trusted entry base register NT_EBR118if the content of the common resource is to be stored. In addition, when the processor100is in the trusted execution environment, the content of the common resource used in the trusted world can be fetched by popping the stack with the base address of the trusted stack stored in trusted entry base register T_EBR118. Similarly, when processor100is in the non-trusted execution environment, the content of the common resource used in the non-trusted world can be fetched by popping the stack with the base address of the non-trusted stack stored in non-trusted entry base register NT_EBR128.

FIG. 2is a schematic diagram of an example processor, according to some embodiments of the present disclosure. As shown inFIG. 2, various components of a processor200can be configured for instruction execution. In some embodiments, processors100and200show different aspects of a processor. For example,FIG. 1shows various components in trusted core110and non-trusted core120in a processor, whereasFIG. 2shows various components for instruction execution for the processor.

As shown inFIG. 2, processor200includes an instruction processing device290. Instruction processing device290can be an instruction processing component in processor200. Instruction processing device290can be configured to fetch instructions for decoding and execute a variety of decoded instructions. In some embodiments, instruction processing device290can be a logical division of the functions of processor200, and all instruction-related components in processor200can be classified as a part of instruction processing device290n.

In some embodiments, instruction processing device290can include an instruction fetching unit210, an instruction decoding unit220, an instruction executing unit230, and an instruction retiring unit240.

Instruction fetching unit210includes circuitry configured to fetch a to-be-executed instruction, and to send the fetched instruction to instruction decoding unit220. The instruction can generally include an operation code and an address code. The operation code indicates an operation to be executed. The address code indicates an address or content of an operation object when the operation code is executed.

Instruction decoding unit220includes circuitry configured to decode and analyze an instruction to determine an operation code of the instruction. In some embodiments, instruction decoding unit220includes circuitry configured to further determine the nature and method of the operation. Instruction decoding unit220includes circuitry that is further configured to send the decoded instruction to instruction executing unit230, where the instruction can be executed in instruction executing unit230. In some embodiments, instruction executing unit230can include a variety of units that include circuitry configured to execute specialized instructions, such as an FPU unit232. FPU unit232includes circuitry configured to execute a floating point instruction. Vector arithmetic unit VDSP234includes circuitry configured to execute a VDSP instruction. Embodiments of the present disclosure are not limited to specific forms of instruction executing units that execute the specialized instructions.

In some embodiments, processor200can further include an instruction retiring unit240, so that processor200can process instructions in a pipelined manner. In some embodiments, after the execution of each instruction in instruction executing unit230is completed, the status of each instruction needs to be checked. For an instruction that has been executed and has no dependence on other instructions, the execution result of the instruction can be written back to the corresponding register and the instruction whose execution has been completed can be retired in the original order.

Instruction decoding unit220can include a delay switching unit222. As described above, instruction decoding can be performed in instruction decoding unit220, and instruction decoding unit220can determine whether the result from instruction decoding indicates that the to-be-executed instruction involves access to common resource130shown inFIG. 1. For example, the to-be-executed instruction involves access to the content in general-purpose register GPR132or vector general-purpose register VGPR134.

In some embodiments, if the to-be-executed instruction does not involve the access to common resource130, instruction decoding unit220can send the instruction to instruction executing unit230for execution. In some embodiments, if the instruction involves the access to common resource130, delay switching unit222can determine whether a current execution environment of processor100is consistent with a resource status of the common resource.

As described above, processor100can be in the trusted execution environment (e.g., a trusted world) or the non-trusted execution environment (e.g., a non-trusted world). If the instruction is to access the common resource at this point, the site of the common resource or the content in the common resource should belong to the corresponding execution environment. Since processor100does not correspondingly switch the content in common resource130simultaneously when switching the world, inconsistency may occur between them.

In some embodiments, when the current execution environment of processor100is consistent with the resource status of the common resource, delay switching unit222does not perform resource switching but sends the instruction to instruction executing unit230for subsequent instruction execution. In some embodiments, when the current execution environment is inconsistent with the resource status of common resource130, delay switching unit220switches the site of the common resource into the one consistent with the current execution environment. In other words, delay switching unit220can load the content corresponding to the current execution environment into the common resource, and then the instruction is sent to instruction executing unit230for subsequent instruction execution.

As such, through the operation in instruction decoding unit220, or in delay switching unit222, the consistency of instruction execution can be ensured while the delay of the switching of common resource130in the world switching is ensured.

As described above with reference toFIG. 1, bit T of program status register PSR in processor100can indicate the current execution environment, while the security flag bit of the common resource (e.g., an STV bit of a trusted processor configuration register T_PCR116) can indicate the world to which the site of the common resource belongs. Delay switching unit222can compare a value of bit T of program status register PSR with a value of bit STV of trusted processor configuration register T_PCR116to determine whether the current execution environment is consistent with the site of common resource130.

In some embodiments, when the current execution environment is inconsistent with the site of common resource130, delay switching unit222can switch the site of the common resource in the following steps.

First, bit T of program status register PSR is modified to a value corresponding to bit STV of trusted processor configuration register T_PCR116, thus triggering processor100to perform world switching to switch the current execution environment to an execution environment consistent with the site of the current common resource.

Then, content in common resource130is saved in the execution environment. In some embodiments, there is a corresponding entry base register (e.g., trusted entry base register T_EBR118or non-trusted entry base register NT_EBR128) in each world (e.g., each core). A base address of a stack of the world can be fetched from the entry base register, and the content of common resource130can be pushed and saved by pushing to the stack. In this case, the value of bit STV of trusted processor configuration register T_PCR116can be modified to indicate that the site of the current common resource has been saved and the common resource can be used in other worlds.

Next, bit T of program status register PSR is modified back to a value corresponding to the original execution environment, so that processor100is triggered to perform world switching to switch back to the original execution environment, and the content of the common resource corresponding to the execution environment is retrieved in the execution environment. In addition, the content stored in the stack can be read to the common resource by popping the stack with reference to the stack base address stored in the entry base register in the execution environment, thereby restoring the site of the common resource.

In the steps above, the current execution environment has been consistent with the site of the common resource, and thus the instruction can be sent to instruction executing unit230for subsequent processing.

In some embodiments, the value of bit STV of trusted processor configuration register T_PCR116can be modified after processor100is switched back to the current execution environment.

As described above, in some embodiments, the inconsistency between the current execution environment and the site of the common resource can be caused by the processing during the world switching.

In some embodiments, world switching is executed in instruction retiring unit240. Instruction retiring unit240can determine whether to perform world switching. For example, instruction retiring unit240can determine whether to switch the execution environment of processor100. If the world switching is not performed, instruction retiring unit240can instruct instruction fetching unit210to fetch the next to-be-executed instruction after performing operation related to retiring an instruction. When it is determined to perform the world switching, a related status of the current execution environment can be stored. For example, some dedicated resource content in the execution environment is pushed to the stack. In some embodiments, the content can be saved by pushing to the stack with reference to the base addresses of the stacks stored in registers such as the various entry base registers (e.g., trusted entry base register T_EBR118or non-trusted entry base register NT_EBR128). Then, the value of bit T of program status register PSR can be modified to trigger processor100to switch from the current execution environment to a target execution environment.

In some embodiments, the operation of saving the site of the common resource is not performed in the world switching operation of instruction retiring unit240. Instead, the dedicated status of each execution environment is saved, thus reducing the time required by the site switching and accelerating the site switching speed.

In some embodiments, processor100is not limited to the specific range of the common resource. For example, general-purpose register GPR132, vector general-purpose register VGPR134and control register CR136belong to common resources and may also be used frequently in the switched world, and thus content in the resources can be pushed and popped to and from the stack during world switching, and delay switching can be performed on common resources that may not be used frequently. The common resources on which delay switching is to be performed can be determined according to an application scenario of processor200.

FIG. 3is a flowchart of an example instruction execution method in a processor, according to some embodiments of the present disclosure. As shown inFIG. 3, an instruction execution method300can be performed in processors100ofFIG. 1or processor200ofFIG. 2. It is appreciated that some steps in method300have been described in the steps of processors100and200, and will not be repeated here.

Method300starts from step S310. In step S310, an instruction is fetched and decoded. This can be performed in instruction fetching unit210and instruction decoding unit220ofFIG. 2. Then, in step S320, it is determined whether the result from instruction decoding in step S310indicates that the instruction involves access to the common resource. If the determination result in step S320indicates that the instruction involves access to the common resource, the instruction is sent to step S380to execute the instruction. On the contrary, if the determination result in step S320indicates that the instruction involves access to the common resource, method300proceeds to step S330.

In step S330, it is determined whether a current execution environment of the processor is consistent with the site of the common resource. In other words, it is determined whether the world to which the content in the common resource belongs is consistent with the current world. In some embodiments, the implementation of making the above determination has been described above with reference toFIG. 2.

When the determination result in step S330indicates that the current execution environment is consistent with the site of the common resource, method300proceeds to step S380to execute the instruction. On the contrary, when the determination result in step S330indicates that the current execution environment is inconsistent with the site of the common resource, method300proceeds to step S340.

In step S340, the site of the common resource is restored to be consistent with the current execution environment or the current world. In other words, the content of the common resource corresponding to the current execution environment is loaded into the common resource. In some embodiments, the specific implementation of switching the common resource has been described above with reference toFIG. 2.

In some embodiments, after the current execution environment is set to be consistent with the site of the common resource in step S340, the method proceeds to step S380to execute the instruction.

In some embodiments, after the execution of the instruction in step S380is completed, the instruction can be retired in step S390. It is further determined in step S390whether the instruction involves world switching. If the instruction involves the world switching, the status of the current execution environment is saved and the world switching is performed, but the site of the common resource is not switched during the world switching, so as to accelerate the world switching speed. In some embodiments, the specific implementation of performing the world switching has been described above with reference toFIG. 3.

In some embodiments, after the execution of step390, method300goes back to step S310to fetch a next instruction for processing, thus repeating the various steps in method300above.

FIG. 4is a flowchart of an example instruction execution process400, according to some embodiments of the present disclosure. Various status changes during instruction execution are described inFIG. 4by taking that an instruction of processor100is executed in a trusted execution environment (e.g., trusted world) and switched to a non-trusted execution environment (e.g., non-trusted world) for execution as an example.

In a status410, the instruction is executed in the trusted world. In this case, program status register PSR is the trusted program status register T_PSR114, in which the value of the bit T is 1. In the initial status, the value of the STV bit in trusted processor configuration register T_PCR116is also equal to 1, indicating that the site of the common resource at this time is in the trusted world.

Then, in a status420, it is determined whether world switching is sent during the execution of the instruction. If the world switching is not performed, the process returns to status410to execute a new instruction.

If the world switching is performed, processor100is switched to the non-trusted world, and the process enters a status430where the instruction is executed in the non-trusted world. In status430, program status register PSR is NT_PSR124, and the value of the T bit is set to 0. The site of the common resource is not switched, and thus the value of the STV bit in trusted processor configuration register T_PCR116is still1.

In a status440, it is determined that the execution of the instruction involves access to the common resource. In status450, it is determined that the value 0 of the T bit of non-trusted program status register NT_PSR124is inconsistent with the value 1 of the trusted program configuration register T_PCR116, and thus the world switching is triggered. The process enters a status460.

In status460, it is in the trusted world, trusted program status register T_PSR114is used, the value of the bit T of trusted program status register T_PSR114is 1, and the site of the common resource is pushed. Then, in a status470, the value of the STV bit of trusted program configuration register T_PCR116is set to 0 after the site of the common resource is pushed, and the world switching is triggered once again.

In status480, it is in the non-trusted world, non-trusted program status register NT_PSR124is used, and the value of the bit T of non-trusted program status register NT_PSR124is 0. In this case, the value of the STV bit of trusted program configuration register T_PCR116is set to 0, and the two values are consistent with each other.

Therefore, in a status490, the execution involves access to the common resource. Also in a status492, a world switching instruction is executed so that the process returns to a status494in the trusted world. In status494, the value of trusted program status register T_PSR114is 1, but the site of the common resource is not switched, and thus the value of the STV bit of the T_PCR116remains 0. The process can then return to status410to continue to execute a new instruction in the trusted world.

According to the instruction execution solution of the present disclosure, the site of the common resource may not be switched immediately during world switching. After the world switching is completed, the common resource is switched only when it is found during execution of an instruction in the new world that the instruction involves access to the common resource. As a result, unnecessary stack pushing and popping operations on the common resource can be reduced, and the speed of the world switching is increased.

The various example embodiments described herein are described in the general context of method steps or processes, which may be implemented in one aspect by a computer program product, embodied in a computer-readable medium, including computer-executable instructions, such as program code, executed by computers to program the processors (e.g., processor100and processor200). A computer-readable medium may include removeable and nonremovable storage devices including, but not limited to, Read Only Memory, Random Access Memory, compact discs (CDs), digital versatile discs (DVD), etc. Generally, program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps or processes.

In the drawings and specification, there have been disclosed exemplary embodiments. Many variations and modifications, however, can be made to these embodiments. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the embodiments being defined by the following claims.