MANAGING STATUS OUTPUT

Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

BACKGROUND

Non-volatile memory devices are used in electronic systems to store data in a nonvolatile manner. During use, the memory devices output status of operations executed in the memory devices.

SUMMARY

The present disclosure describes methods, devices, systems, and techniques for managing status (e.g., error information) output (e.g., for a secure operation) in a semiconductor device, e.g., a non-volatile memory device such as NOR flash memory device.

One aspect of the present disclosure features a semiconductor device including: a memory array configured to store data; and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation in the memory array. The read packet includes readout data and error information associated with the readout data, and where the error information is indicated by at least one of an error code or one or more secure codes in the read packet.

In some embodiments, the error information indicates whether there is error occurrence on the readout data.

In some embodiments, the read operation is a secure read operation with error detection and correction using error correction code (ECC).

In some embodiments, the circuitry is configured to sequentially output the error code, the readout data, and the one or more secure codes in the read packet.

In some embodiments, the error code indicates that there is no error associated with the readout data, and the one or more secure codes indicate that there is an error associated with the readout data.

In some embodiments, where the one or more secure codes include at least one of a secure data code based on the readout data or a secure packet code based on the read packet.

In some embodiments, the circuitry is configured to: generate a message authentication code (MAC) of the readout data; and change the MAC to obtain the secure data code that is different from the MAC.

In some embodiments, the circuitry is configured to generate the MAC of the readout data by a cryptographic algorithm. The cryptographic algorithm can include an Advanced Encryption Standard (AES) algorithm including AES-GCM (Galois/Counter Mode) or AES-CCM (Counter with Cipher Block Chaining-Message Authentication Code). The MAC can include Galois Message Authentication Code (GMAC).

In some embodiments, the circuitry is configured to change the MAC to obtain the secure data code by inverting the MAC with a logic, and the logic includes at least one of an inverter or a XOR logic gate.

In some embodiments, the circuitry is configured to: generate a cyclic redundancy check (CRC) of the read packet; and change the CRC to obtain the secure packet code that is different from the CRC.

In some embodiments, the circuitry is configured to change the CRC to obtain the secure packet code by inverting the CRC with a logic, and the logic includes at least one of an inverter or a XOR logic gate.

In some embodiments, the circuitry is configured to generate the CRC of the read packet by a CRC calculation or algorithm.

In some embodiments, the circuitry is configured to output the error information after the readout data.

In some embodiments, the circuitry is configured to sequentially output the readout data, MAC of the readout data, the error code, and CRC of the read packet in the read packet, and the error information is indicated by the error code.

In some embodiments, there is no indication of error information in the MAC and in the CRC.

In some embodiments, the error information is further indicated by the CRC.

In some embodiments, the circuitry is configured to: generate an initial CRC of the read packet; and change the initial CRC to obtain the CRC that is different from the initial CRC.

In some embodiments, the circuitry is configured to: generate the error information in response to detecting a failure of error correction on at least a portion of the readout data.

In some embodiments, the readout data includes a first portion of the readout data output concurrently with the error code and a second portion of the readout data output after the error code, and the failure of error correction is on the second portion of the readout data.

In some embodiments, the circuitry is configured to: execute the read operation based on a request packet, where the request packet includes information specifying the read operation.

Another aspect of the present disclosure features a system, including: a semiconductor device and a controller. The semiconductor device includes: a memory array configured to store data; and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation, where the read packet includes readout data and error information associated with the readout data, and where the error information is indicated by at least one of an error code or one or more secure codes in the read packet. The controller is coupled to the semiconductor device and configured to receive the read packet from the semiconductor device. The controller is configured to detect the error information associated with the readout data based on the at least one of the error code or the one or more secure codes in the read packet.

In some embodiments, the controller is configured to: receive the error code before the readout data and the one or more secure codes in the read packet; and detect the error information associated with the readout data based on the one or more secure codes in the read packet.

In some embodiments, the one or more secure codes include a secure data code based on the readout data, and the controller is configured to: generate MAC of the readout data received in the read packet, compare the generated MAC with the secure data code received in the read packet to determine whether the generated MAC is different from the secure data code received in the read packet, and determine that there is an error associated with the readout data received in the read packet if the generated MAC is different from the secure data code received in the read packet.

In some embodiments, the one or more secure codes include a secure packet code based on the read packet, and the controller is configured to: generate CRC of the read packet, compare the generated CRC with the secure packet code received in the read packet to determine whether the generated CRC is different from the secure packet code received in the read packet, and determine that there is an error associated with the readout data received in the read packet if the generated CRC is different from the secure packet code received in the read packet.

In some embodiments, the controller is configured to: receive the error code after the readout data, and detect the error information associated with the readout data based on the error code.

In some embodiments, the controller is configured to send a request packet to the semiconductor device, where the request packet includes information specifying the read operation.

A further aspect of the present disclosure features a method including: executing a read operation in a memory array storing data; and outputting a read packet based on a result of executing the read operation. The read packet includes readout data and error information associated with the readout data, and where the error information is indicated by at least one of an error code or one or more secure codes in the read packet.

Note that in the present disclosure, the term “secure operation” represents an operation securely performed in a semiconductor device. The secure operation can be associated with a security procedure, e.g., authentication and/or verification of data, message, or any control information related to the operation. The secure operation can include a secure read operation, a secure write operation, a secure key generation, verification or update, or any other type of operation. The term “secure data” represents data that can be encrypted or authenticated using a cryptographic (or secret) key and/or using any suitable authentication or encryption algorithm, function, or scheme. The term “secure code” represents a code that can be generated, authenticated, and/or verified using an authentication and/or verification algorithm, function, or scheme. The secure code can be a message authentication code (MAC) or a cyclic redundancy check (CRC). The term “secure memory device” represents a memory device that can include encryption, decryption, authentication, and/or verification features. For example, a secure memory device can encrypt and/or decrypt data, and/or verify (or check) an authentication code from a controller to authenticate the controller.

Implementations of the above techniques include methods, systems, circuits, computer program products and computer-readable media. In one example, a method can include the above-described actions. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-described actions. One such computer-readable medium stores instructions that, when executed by one or more processors, are configured to cause the one or more processors to perform the above-described actions.

The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

Like reference numbers and designations in the various drawings indicate like elements. It is also to be understood that the various exemplary implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale.

DETAILED DESCRIPTION

Implementations of the present disclosure provide techniques for managing status output in semiconductor devices, e.g., non-volatile memory devices such as NOR flash memory devices, which can accurately report error information of secure operations (e.g., secure read operations with ECC capability) executed in the semiconductor devices.

In some implementations, a semiconductor device includes a memory array configured to store data (e.g., critical data or secure data), and a circuitry coupled to the memory array. The circuitry can be configured to execute a read operation (e.g., a secure read operation) to read out stored data in the memory array and output a read packet based on a result of the execution of the read operation in the memory array. The read packet can include different types of data (or information) including: error code associated with the read operation, readout data, a message authentication code (MAC) of the readout data, and/or a cyclic redundancy check (CRC) of the read packet. The circuitry can sequentially output the different types of data in the read packet in any suitable order. Error information associated with the read operation or the readout data can be indicated by at least one of the error code, the MAC, or the CRC.

In some cases, the error code is arranged to be output before the readout data. If the error code does not indicate any error for the read operation, the readout data is output following the error code. However, there may be an error occurrence (or an occurrence of error) on the readout data output at a later time than the error code. The circuitry can change (e.g., invert) an original MAC of the readout data internally and/or change (e.g., invert) an original CRC of the read packet internally to indicate the error occurrence on the readout data.

In some cases, the error code is arranged to be output after the readout data and the MAC. The error code can be used to indicate error occurrence on the readout data. For example, the circuitry can set a value for the error code in response to determining that the ECC cannot correct at least a portion of the readout data. The value can specify the level or degree of ECC uncorrectability on the readout data. The CRC is output after the error code, and can be changed (e.g., inverted) to indicate the error occurrence on the readout data.

The techniques disclosed herein provide an error information reporting scheme for operations (e.g., secure operations such as secure read operations) in semiconductor devices. For illustration purposes, a memory device is described herein as an example of a semiconductor device. It is noted that the techniques can be implemented for any type of circuits, devices, or systems that need error reporting. For example, besides memory devices, the techniques can be also applied to any other storage devices or logic devices such as microprocessors or controllers.

The techniques can be applied to various types of non-volatile memory devices such as NOR flash memory devices, NAND flash memory devices, erasable programmable read-only memory (EPROM), Ferroelectric Random Access Memory (FeRAM), Magnetoresistive random-access memory (MRAM), among others. The techniques can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (cMMC), or solid-state drives (SSDs), embedded systems, or computing network devices such as network routers or network processors, cache controllers and translation lookaside buffers, lookup tables, database engines, data compression hardware, artificial neural networks, intrusion prevention systems, custom computer, among others.

FIG.1Ais a schematic diagram illustrating an example of a system100, according to one or more embodiments of the present disclosure. The system100includes a device110and a host device120. The device110includes a device controller112and a memory116. The device controller112includes a processor113and an internal memory114. In some implementations, the device110includes a plurality of memories116that are coupled to the device controller112. The memory116includes a plurality of blocks. The memory116can be a two-dimensional (2D) memory including 2D memory blocks. The memory116can also be a three-dimensional (3D) memory including 3D memory blocks.

The host device120includes a host controller122that can include at least one processor and at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to perform one or more corresponding operations.

In some implementations, the device110is a storage device. For example, the device110can be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid-state drive (SSD), or some other suitable storage. In some implementations, the device110is a smart watch, a digital camera or a media player. In some implementations, the device110is a client device that is coupled to a host device120. For example, the device110is an SD card in a digital camera or a media player that is the host device120.

The device controller112is a general-purpose microprocessor, or an application-specific microcontroller. In some implementations, the device controller112is a memory controller for the device110. The following sections describe the various techniques based on implementations in which the device controller112is a memory controller. However, the techniques described in the following sections are also applicable in implementations in which the device controller112is another type of controller that is different from a memory controller.

The processor113is configured to execute instructions and process data. The instructions include firmware instructions and/or other program instructions that are stored as firmware code and/or other program code, respectively, in the secondary memory. The data includes program data corresponding to the firmware and/or other programs executed by the processor, among other suitable data. In some implementations, the processor113is a general-purpose microprocessor, or an application-specific microcontroller.

The processor113accesses instructions and data from the internal memory114. In some implementations, the internal memory114is a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM). For example, in some implementations, when the device110is an eMMC, an SD card or a smart watch, the internal memory114is an SRAM. In some implementations, when the device110is a digital camera or a media player, the internal memory114is DRAM.

In some implementations, the internal memory114is a cache memory that is included in the device controller112, as shown inFIG.1A. The internal memory114stores instruction codes, which correspond to the instructions executed by the processor113, and/or the data that are requested by the processor113during runtime. The device controller112transfers the instruction code and/or the data from the memory116to the internal memory114.

In some implementations, the memory116is a non-volatile memory that is configured for long-term storage of instructions and/or data, e.g., an NAND or NOR flash memory device, or some other suitable non-volatile memory device. The memory116can include one or more memory chips. In implementations where the memory116is an NAND flash memory, the device110is a flash memory device, e.g., a flash memory card, and the device controller112is an NAND flash controller. For example, in some implementations, when the device110is an eMMC or an SD card, the memory116is an NAND flash memory; in some implementations, when the device110is a digital camera, the memory116is an SD card; and in some implementations, when the device110is a media player, the memory116is a hard disk. In some implementations where the memory116is an NOR flash memory, the device110can optionally include the device controller112. In some cases, the device110can include no device controller and the memory116can directly communicate with the host device120.

FIG.1Bis a schematic diagram illustrating another example of a system150including a controller160and a memory device170, according to one or more embodiments of the present disclosure. The controller160is coupled to the memory device170via an electrical connection, e.g., an electrical wire, pin or bus, or a wireless connection, and communicates, e.g., directly, with the memory device170. The controller160can be the host controller122ofFIG.1Aor the device controller112ofFIG.1A. The memory device170can be the memory116ofFIG.1Aand can be implemented as a non-volatile memory device.

FIG.2is a schematic diagram illustrating an example of a memory device200, according to one or more embodiments of the present disclosure. The memory device200can be the memory116ofFIG.1Aor the memory device170ofFIG.1B. The memory device200can be a non-volatile memory device (e.g., a NOR flash memory). The memory device200can be implemented as a secure memory device configured to perform one or more secure operations, e.g., secure read, secure write, and/or key generation.

The memory device200can be configured to use an error correction code (ECC) to detect and correct data corruption that occurs in the memory device200. In some implementations, the memory device200has ECC capability, e.g., including an ECC module configured to perform error detection and correction.

As illustrated inFIG.2, the memory device200includes a number of components that can be integrated onto a board, e.g., a Si-based carrier board, and be packaged. The memory device200can have a memory array (or a memory cell array)210that can include a number of memory cells. The memory cells can be coupled in series to a number of row word lines and a number of column bit lines. Each memory cell can include at least one memory transistor configured as a storage element to store data. The memory transistor can include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable non-volatile memory MOS device that can store charges.

In some implementations, the memory device200includes one or more memory chips each storing a corresponding memory array. A data memory chip can include a larger memory array (e.g., the memory array210) for storing data, while a configuration memory chip can include a smaller memory array for storing configuration information.

The memory device200can include an X-decoder (or row decoder)238and optionally a Y-decoder (or column decoder)248. Each memory cell can be coupled to the X-decoder238via a respective word line and coupled to the Y-decoder248via a respective bit line. Accordingly, each memory cell can be selected by the X-decoder238and the Y-decoder248for read or write operations through the respective word line and the respective bit line.

The memory device200can include a memory interface (input/output—I/O)230having multiple pins configured to be coupled to an external device, e.g., the device controller112and/or the host device120ofFIG.1Aor the controller160ofFIG.1B. The memory interface230can be configured to support one or more types (e.g., communication protocols with the controller) and interface instructions. The memory interface230can be a Serial Peripheral Interface (SPI), Octal SPI (OPI), or any other suitable interface.

In some embodiments, the pins in the memory interface230can include SI/SIO0 for serial data input/serial data input & output, SO/SIO1 for serial data output/serial data input &output, SIO2 for serial data input or output, SIO3 for serial data input or output, CS # for chip select, and RESET # for hardware reset pin active low. The memory interface230can also include ECS # for hardware pin configured to independently report memory ECC error or failure, e.g., without a command from a controller. The memory interface230can also include one or more other pins, e.g., WP # for write protection active low, and/or Hold # for a holding signal input.

The memory device200can include a data register232, an SRAM buffer234, an address generator236, a synchronous clock (SCLK) input240, a clock generator241, a mode logic242, a state machine244, and a high voltage (HV) generator246. The SCLK input240can be configured to receive a synchronous clock input and the clock generator241can be configured to generate a clock signal for the memory device200based on the synchronous clock input. The mode logic242can be configured to determine whether there is a read or write operation and provide a result of the determination to the state machine244.

The memory device200can also include a sense amplifier250that can be optionally connected to the Y-decoder248by a data line252and an output buffer254for buffering an output signal from the sense amplifier250to the memory interface230. The sense amplifier250can be part of a read circuitry that is used when data is read from the memory device200. The sense amplifier250can be configured to sense low power signals from a bit line that represents a data bit (1or0) stored in a memory cell and to amplify small voltage swings to recognizable logic levels so the data can be interpreted properly. The sense amplifier250can also communicate with the state machine244, e.g., bidirectionally.

A controller, e.g., the host controller122or the device controller112ofFIG.1Aor the controller160ofFIG.1B, can generate commands, such as read commands and/or write commands that can be executed respectively to read data from and/or write data to the memory device200. Data being written to or read from the memory array210can be communicated or transmitted between the memory device200and the controller and/or other components via a data bus (e.g., a system bus), which can be a multi-bit bus.

In some examples, during a read operation, the memory device200receives a read command from the controller through the memory interface230. The state machine244can provide control signals to the HV generator246and the sense amplifier250. The sense amplifier250can also send information, e.g., sensed logic levels of data, back to the state machine244. The HV generator246can provide a voltage to the X-decoder238and the Y-decoder248for selecting a memory cell. The sense amplifier250can sense a small power (voltage or current) signal from a bit line that represents a data bit (1or0) stored in the selected memory cell and amplify the small power signal swing to recognizable logic levels so the data bit can be interpreted properly by logic outside the memory device200. The output buffer254can receive the amplified voltage from the sense amplifier250and output the amplified power signal to the logic outside the memory device200through the memory interface230.

In some examples, during a write operation, the memory device200receives a write command from the controller. The data register232can register input data from the memory interface230, and the address generator236can generate corresponding physical addresses to store the input data in specified memory cells of the memory array210. The address generator236can be connected to the X-decoder238and Y-decoder248that are controlled to select the specified memory cells through corresponding word lines and bit lines. The SRAM buffer234can retain the input data from the data register232in its memory as long as power is being supplied. The state machine244can process a write signal from the SRAM buffer234and provide a control signal to the HV generator246that can generate a write voltage and provide the write voltage to the X-decoder238and the Y-decoder248. The Y-decoder248can be configured to output the write voltage to the bit lines for storing the input data in the specified memory cells. The state machine244can also provide information, e.g., state data, to the SRAM buffer234. The SRAM buffer234can communicate with the output buffer254, e.g., sending information or data out to the output buffer254.

In some implementations, as illustrated inFIG.2, the memory device200includes a secure engine260configured for performing one or more secure operations in the memory device200. The secure engine260can be coupled to one or more components in the memory device200, e.g., the SRAM buffer234, the mode logic242, and/or the state machine244. The secure engine260can communicate, e.g., bidirectionally, with at least one of the SRAM buffer234, the mode logic242, or the state machine224. In some implementations, the SRAM buffer234can input secure information (e.g., authentication data) to the secure engine260. The mode logic242can decode a packet command (e.g., a request packet) from the controller for the secure engine260. The state machine244can activate the secure engine260, e.g., in response to receiving a secure read command from the controller, and/or check the secure engine260whether an authentication of the controller fails or succeeds.

In some implementations, during a secure write operation, the secure engine260can be configured to: i) decrypt information (e.g., write command, option code, addresses, and data) using a cryptographic key, ii) generate an authentication code to verify authentication information from the controller and authenticate the controller, and/or iii) perform secure writing data to one or more addresses in the memory array210.

In some implementations, as discussed with further details below, during a secure read operation to read data from one or more addresses in the memory array210(e.g., in response to receiving a read command from a controller), the secure engine260can be configured to: encrypt readout data using a cryptographic key and generate an authentication code (e.g., MAC) of the readout data. The authentication code can be output together with the readout data to the controller. The secure engine260can also generate a cyclic redundancy check (CRC) for a read packet (or output packet) using a CRC calculation or algorithm. CRC can be used for detecting errors in transmitted information (data or message) in the read packet. The CRC can be appended to the transmitted information, e.g., at an end of the read packet.

In some implementations, the secure engine260includes one or more modules, including a cryptographic (crypto) module, a CRC generation module, an authentication module, a secure write module, and/or a secure read module. Each module can include one or more logic circuits and/or registers configured to implement an algorithm or an operation. In some implementations, the controller coupled to the memory device200includes one or more corresponding modules, e.g., a crypto module, a CRC generation module, and/or an authentication module.

The crypto module can be configured to decrypt, using a cryptographic algorithm, encrypted information and/or authentication information (e.g., received from a controller). The crypto module can be also configured to encrypt, using the cryptographic algorithm, information (e.g., readout data or data in a read packet). The cryptographic algorithm can be an authenticated encryption algorithm designed to provide both authentication and confidentiality. In some examples, the cryptographic algorithm is an Advanced Encryption Standard (AES) algorithm, e.g., Advanced Encryption Standard Galois Counter Mode (AES-GCM), or Advanced Encryption Standard-Counter with Cipher Block Chaining-Message Authentication Code (AES-CCM).

The CRC generation module can be configured to perform CRC calculation on data or message in the output packet or read packet. The CRC calculation can be implemented with CRC-16 polynomial, CRC-CCITT (Consultative Committee for International Telephony and Telegraphy), CRC-32 or other polynomials. The authentication module can be configured to authenticate the controller based on a result of comparing an authentication code generated by the crypto module with an input authentication code from the controller. The secure write module can be configured to execute a secure write operation, e.g., in response to determining that the controller is authenticated, in the memory array210. The secure read module can be configured to execute a secure read operation, e.g., in response to determining that a read command from the controller is authenticated and/or authenticating readout data from the memory array210.

In some implementations, the memory device200includes one or more registers (or buffers) that can be coupled to one or more components in the memory device200, e.g., the state machine244, the sense amplifier250, and/or the output buffer254.

In some examples, the memory device200includes a configuration register220, e.g., a read configuration register (RDCR), configured to store a command (e.g., from a controller) for checking whether a read operation executed in the memory device200passes or fails and/or store pass/fail data associated with the read operation (e.g., to be output to the controller). The configuration register220can be coupled to the state machine244, the sense amplifier250, and/or the output buffer254. In some embodiments, the configuration register220can be configurable through a command input from the controller, e.g., through the memory interface230and the data register232. In some embodiments, the configuration register220can be pre-defined in the memory array210or inside circuitry of the memory device200, e.g., through the sense amplifier250.

In some examples, the memory device200includes a read status register (RDSR) configured to store a read status command (e.g., from the controller) for checking a ready/busy status of the memory device200and/or store the read status data of the memory device200(e.g., to be output to the controller). In some examples, the memory device200includes a read security register (RDSCUR) configured to store a command (e.g., from the controller) for checking whether a write operation executed in the memory device200passes or fails and/or store pass/fail data associated with the write operation (e.g., to be output to the controller).

In some examples, the memory device200includes a packet-in (PKTI) register configured to store a request packet (or input packet), e.g., from the controller. The request packet can include information indicating an operation, e.g., a secure write operation, a secure read operation, a secure key generation or exchange, or a secure data access.

FIG.3Aillustrates an example of a request packet300for a secure operation, according to one or more embodiments of the present disclosure. The request packet300includes different types of information (e.g., command, address, and/or data) with corresponding length information. As shown inFIG.3A, the request packet300includes a command call (PKTI), address (ADDR) with a fixed code specifying the PKTI command call, and DATA in sequence. DATA includes count (e.g., length of DATA), packet, and CRC of the packet that are input in sequence. The CRC can be generated by the controller and put in the request packet300.

The packet can include one or more of CMD code, option (OP), variables (e.g., variable1, variable2), InDATA (e.g., input data to be written), and InMAC (e.g., MAC of the input data), e.g., as illustrated in Table 1 below. The CMD code is used to specify a command for performing an operation in the memory device200, e.g., as illustrated in Table 2 below. The option is used to specify information of the operation, e.g., length of data to be written. The variables can include address information, e.g., address for writing data or reading data. InDATA represents input data to be written, and InMAC represents MAC of the input data that can be generated by the controller. A request packet for a write operation includes InDATA and InMAC in the packet.

Table 1 shows an example of data in a request packet with corresponding descriptions as follows:

Table 2 shows an example of different types of CMD codes with corresponding descriptions as follows:

CMDCategoryCodeNameDescriptionKey0x21KECDHKey exchange with Elliptic-curve Diffie-Hellman (ECDH) algorithm0x23SSGENGenerate a secure session for a Root keyRead0x0CPGRDRead plaintext data from data memory orconfiguration memoryWrite0x29PGWRWrite Configuration and Counter memorywhen the region is unlockNonce0x10NGENGenerates Nonce from the internalRandom Number Generator or importAdvance0x18HSDAHigh Secure Data Access

In some examples, the memory device200includes a packet-out (PKTO) register configured to store packet-out command or an output packet (e.g., a read packet) from the memory device200. The read packet can include status information of an operation (e.g., secure operation such as secure read operation) performed in the memory device200. As discussed with further details below, the status information can be indicated (or showed) by at least one of error code, output MAC, or CRC in the read packet.

FIG.3Billustrates an example of a read packet330for a secure read operation, according to one or more embodiments of the present disclosure. Similar to the request packet300ofFIG.3A, the read packet330includes different types of information (e.g., command, address, data) with corresponding length information in sequence.

As shown inFIG.3B, the read packet330includes a command call (PKO), address (ADDR) with a fixed code specifying the PKO command call, Dummy, and DATA in sequence. Dummy represents a configurable idle period after outputting the PKO and ADDR before outputting DATA, while one or more pins for outputting the read packet330can be at a high impedance (High-Z) mode. DATA includes count (e.g., length of DATA), Error Code332, OutDATA334, OutMAC336, and CRC338of DATA, which are output in sequence. That is, Error Code332is output before OutDATA334, OutMAC336is output after OutDATA334, and CRC338is output at the end. Note that a read packet for a secure read operation includes OutDATA and OutMAC.

OutDATA represents data to be output (or readout data), and OutMAC represents MAC of the OutDATA. The MAC can be generated by the memory device200by a cryptographic algorithm. The cryptographic algorithm can include an Advanced Encryption Standard (AES) algorithm that can be AES-GCM (Galois/Counter Mode) or AES-CCM (Counter with Cipher Block Chaining-Message Authentication Code). The MAC can include Galois Message Authentication Code (GMAC).

Error Code is used to report any error information associated with an operation (e.g., specified in the request packet or command from the controller) in the memory device200. Different values of the error code can represent different types of error information.

Table 3 shows an example of Error Code with corresponding descriptions as follows:

NameValueDescriptionPass00hLatest secure command was successfulCMDerr01hWrong CMDcode, wrong option, wrong variable and wrong lengthWrong security profile or not supportedADDRerr02hAttempted to Write protected region while Write, address is illegalBDRYerr04hCrossed a page boundary or wrong byte count in specific modePERMerr08hPermission violation. Attempted to access the zone in a mode not permittedby current configurationNONCEerr10hNonce invalidMACerr20hLatest secure command crypto-processing was not successfulNVMCerr40hGP_MC or UP_MC reached maximum (max) numberKEYerr80hKey is unable to update, wrong Key ID, wrong Session ID (SID), Sessionalready activated, Key generation or other key errorsLKDerrA0hWrong configuration setting or configuration has not been locked down ifrequiredVFYerrC0hData was failed at internal verification.Security critical parameters protect (CRC, SHA256) errorVMCerrB0hSession max number of transaction reached (e.g., CTE_MAX_DPA)SMNerrD0hSession max number reachedKATerrE0hKAT test errorRULCerr11hRule check errorECCerr22hData zone ECC uncorrectableCECCerr33hConfiguration ECC (CECC) uncorrectableCRCerr44hCRC check errorRNGerr55hRandom Number Generator (RNG) health testing errorCIPHerrFFhPass, ADDRerr, BDYerr, PERMerr or ECCerr in Host Sideband Bus Data(HSDA) command

Each read packet includes a specific value representing a corresponding type of error. For example, if the latest secure command for a secure operation is successfully executed in the memory device200, the error code is assigned with a value “00h” representing “pass”. The memory array210can include a number of data zones. If a data zone, that is in a mode not permitted to access, is accessed, the error code is assigned with a value “08h” representing “PERMerr”. In a read operation for reading data from one or more data zones, if data in at least one of the one or more data zones cannot be corrected by ECC code, the error code is assigned with a value “22h” representing “ECCerr”.

In some implementations, if the value of the error code in the read packet is not “00h”, it means that the latest secure command for a secure operation is not executed successfully for at least one of the errors shown in Table 3, and no OutDATA and OutMAC is output following the error code in the read packet. If the value of the error code is “00h” representing “pass”, it means that the latest secure command for a secure operation is executed successfully at least before the error code in the read packet is output or concurrent with outputting the error code. For example, a first portion334aof the OutDATA334(or readout data334) (e.g., as illustrated inFIG.3B) is output concurrently with the error code332. If the ECC on the first portion334aof the readout data334passes or succeeds, the value of the error code332is “00h” representing “pass”. If the ECC on the first portion334aof the readout data334fails, the value of the error code332is “22h” representing “ECCerr”, and outputting the readout data334can be ceased.

However, after the error code332“00h” representing “pass”, together with the first portion334aof readout data334, is output, the ECC on a second portion334bof the readout data (e.g., as illustrated inFIG.3B) that follows the first portion334amay fail. Thus, the error code332“00h” in the read packet cannot accurately report the error occurrence (e.g., ECCerr) on the second portion334bof the readout data334. Accordingly, the controller receiving the read packet cannot detect the error occurrence on the second portion334bof the readout data, which can affect a performance of the memory device200or a system (e.g.,100ofFIG.1A or150ofFIG.1B) including the memory device200and the controller.

Implementations of the present disclosure provide techniques for accurately reporting error information in a read packet output as a result of executing a read operation (e.g., a secure read operation) in a memory device (e.g., the memory device200ofFIG.2), as described with further details below.

In some implementations, the memory device200is configured to change at least one of an original MAC of the readout data internally or an original CRC of the read packet internally to indicate error occurrence on the readout data, e.g., in response to determining that the ECC on a portion of the readout data (e.g., the second portion334b) fails. As the OutMAC336and CRC338are output after the OutDATA334, the changed MAC and/or the changed CRC can be generated by the memory device200and be used to accurately report the error information associated with the readout data334. The controller and the memory device200can communicate according to a protocol, such that the controller can detect error information based on the changed MAC and/or the changed CRC in the read packet.

FIG.4Aillustrates an example400of changing a message authentication code (MAC), according to one or more embodiments of the present disclosure. As noted above, the memory device200can generate an original MAC of the readout data, e.g., OutMAC_internal401, using the secure engine260(e.g., based on a cryptographic algorithm and a cryptographic key). The memory device200can include a logic402(e.g., a glue logic) configured to change the original MAC, OutMAC_internal401, to be different from the original MAC. The changed MAC, e.g., OutMAC403, can be output as OutMAC336in the read packet. In some examples, the logic402is configured to be an inverter or an XOR logic gate, which can invert the original MAC.

According to the protocol, after receiving the read packet from the memory device200, the controller can generate MAC of the readout data334received in the read packet using the same cryptographic algorithm and same or corresponding cryptographic key). The controller can be configured to compare the generated MAC with the OutMAC336received in the read packet to determine whether the generated MAC is different from the OutMAC336received in the read packet. If the generated MAC is different from the OutMAC336received in the read packet, the controller can determine that there is an error associated with the readout data334received in the read packet. If the generated MAC is same as the OutMAC336received in the read packet, it indicates that the memory device200does not change the original MAC. The controller may determine that there is no error occurrence on the readout data334or continue to check the CRC received in the read packet. Note that the controller may determine whether the OutMAC336received in the read packet indicates error information by any other suitable manner.

FIG.4Billustrates an example450of changing a cyclic redundancy check (CRC), according to one or more embodiments of the present disclosure. As noted above, the memory device200can generate an original CRC of the read packet e.g., CRC_internal451, using the secure engine260(e.g., based on a CRC calculation or algorithm). The memory device200can include a logic452(e.g., a glue logic) configured to change the original CRC, CRC_internal451, to be different from the original CRC. The changed CRC, e.g., CRC453, can be output as CRC338in the read packet. In some examples, the logic452is configured to be an inverter or an XOR logic gate, which can invert the original CRC. In some examples, the logic452can be same as the logic402.

According to the protocol, after receiving the read packet from the memory device200, the controller can generate CRC338received in the read packet using a same CRC calculation or algorithm as the memory device200. The controller can be configured to compare the generated CRC with the CRC338received in the read packet to determine whether the generated CRC is different from the CRC338received in the read packet. If the generated CRC is different from the CRC338received in the read packet, the controller can determine that there is an error associated with the readout data received in the read packet. If the generated CRC is same as the CRC338received in the read packet, it indicates that the memory device200does not change the original CRC. If the controller determines that the generated MAC is same as the OutMAC336and the generated CRC is same as the CRC338received in the read packet, the controller can determine that there is no error in the readout data334received in the read packet. Note that the controller may determine whether the CRC338received in the read packet indicates error information by any other suitable manner.

In some implementations, the memory device200can accurately report error occurrence on readout data by outputting error code after the readout data. For example,FIG.3Cillustrates another example of a read packet350for a secure operation, according to one or more embodiments of the present disclosure.

As illustrated inFIG.3C, the read packet350includes OutDATA352, OutMAC354, Error Code356, and CRC358that are arranged in order and output in sequence. If there is any error occurrence on the OutDATA352, e.g., by detecting there is an ECC failure on the OutDATA352, the memory device200can set a value (e.g., 22h) for the Error Code356to indicate the error. Thus, the controller can detect whether there is any error associated with the OutDATA352based on the Error Code356received in the read packet350.

OutMAC354can be an original MAC of the OutDATA352generated by the memory device200and be output following the OutDATA352in the read packet350. In some implementations, CRC358is an original CRC of the read packet350generated by the memory device200. In some implementations, if the memory device200detects error occurrence on the OutDATA352, besides setting a specified value for the Error Code356, the memory device200can also change the original CRC, as noted above (e.g., as illustrated inFIG.4B), to be different from the original CRC. The controller can detect the error information associated with the OutDATA352based on the CRC358received in the read packet, as discussed above.

FIG.5is a flow chart of an example of a process500for managing status output in a semiconductor device, according to one or more embodiments of the present disclosure. The process500can be performed by the semiconductor device, e.g., the memory116ofFIG.1A, the memory device170ofFIG.1B, or the memory device200ofFIG.2. The semiconductor device can be a non-volatile memory device, such as a NOR flash memory device. The semiconductor device can be configured to perform a read operation (e.g., a secure read operation) with error detection and correction using error correction code (ECC).

The semiconductor device can include a memory array (e.g., the memory array210ofFIG.2) and a circuitry coupled to the memory array. The circuitry can include one or more components in the memory device200ofFIG.2, e.g., secure engine260, memory interface230, data register232, SRAM buffer234, address generator236, X-decoder238, mode logic242, state machine244, HV generator246, Y-decoder248, sense amplifier250, and/or output buffer254. The circuitry can also include one or more registers, e.g., configuration register220, a read status register (RDSR), a read security register (RDSCUR), a packet-in (PKTI) register, and/or a packet-out (PKTO) register. The circuitry can include an ECC module configured to perform error detection and correction on data in the memory array. The circuitry can also include one or more logic circuits, e.g., the logic402configured to invert MAC and/or the logic452configured to invert CRC.

A controller can be coupled to the semiconductor device. The controller can be the host controller122or the device controller112ofFIG.1Aor the controller160ofFIG.1B, or the controller as described with respect toFIGS.2to4B. The semiconductor device and the controller can communicate with each other according to a protocol. The protocol can include Serial Peripheral Interface (SPI) or OPI. The controller can include a secure engine corresponding to the secure engine in the circuitry of the semiconductor device.

At502, the circuitry executes a read operation in the memory array storing data. The read operation can be a secure read operation with error detection and correction using error correction code (ECC). The circuitry can execute the read operation based on a request packet, e.g., the request packet300ofFIG.3Aand Table 1. The request packet can include information specifying the read operation, e.g., using CMD code “PGRD” shown inFIG.3Aand Table 2. The request packet can be received by the semiconductor device from the controller and stored in a PKTI register in the circuitry.

At504, the circuitry outputs a read packet based on a result of the execution of the read operation. The read packet can be the read packet330ofFIG.3Bor the read packet350ofFIG.3C. The read packet can include readout data (e.g., OutDATA334ofFIG.3Bor OutDATA352ofFIG.3C) and error information associated with the readout data, and the error information can be indicated by at least one of an error code (e.g., Error Code356ofFIG.3C) or one or more secure codes (e.g., OutMAC336and/or CRC338ofFIG.3Bor CRC358ofFIG.3C) in the read packet. The error information can indicate whether there is error occurrence on the readout data.

In some implementations, the circuitry is configured to sequentially output the error code, the readout data, and the one or more secure codes in the read packet, e.g., as illustrated inFIG.3B. As the error code is output before the readout data, the error code (e.g., the Error Code332ofFIG.3B) indicates that there is no error associated with the readout data, and the one or more secure codes (e.g., OutMAC336and/or CRC338ofFIG.3B) indicate that there is an error associated with the readout data.

In some implementations, the one or more secure codes comprise at least one of a secure data code based on the readout data (e.g., OutMAC336ofFIG.3B) or a secure packet code based on the read packet (e.g., CRC338ofFIG.3B).

In some implementations, the circuitry is configured to: generate a message authentication code (MAC) of the readout data and change the MAC to obtain the secure data code that is different from the MAC. The circuitry can generate the MAC of the readout data by a cryptographic algorithm, and the cryptographic algorithm can include an Advanced Encryption Standard (AES) algorithm including AES-GCM (Galois/Counter Mode) or AES-CCM (Counter with Cipher Block Chaining-Message Authentication Code). The MAC can include Galois Message Authentication Code (GMAC). In some implementations, the circuitry can change the MAC to obtain the secure data code by inverting the MAC with a logic (e.g., the logic402ofFIG.4A). The logic can include at least one of an inverter or a XOR logic gate.

In some implementations, the circuitry is configured to: generate a cyclic redundancy check (CRC) of the read packet and change the CRC to obtain the secure packet code that is different from the CRC. The circuitry can change the CRC to obtain the secure packet code by inverting the CRC with a logic (e.g., the logic452ofFIG.4B), and the logic can include at least one of an inverter or a XOR logic gate. The circuitry can generate the CRC of the read packet by a CRC calculation or algorithm (e.g., CRC-16 polynomial).

In some implementations, the circuitry is configured to output the error information after the readout data, e.g., as illustrated inFIG.3C. The circuitry can sequentially output the readout data, MAC of the readout data, the error code, and CRC of the read packet in the read packet, and the error information can be indicated by the error code.

In some cases, there is no indication of error information in the MAC and in the CRC. In some cases, the error information is further indicated by the CRC. The circuitry can generate an initial CRC of the read packet and change the initial CRC to obtain the CRC that is different from the initial CRC, e.g., as illustrated inFIG.4B.

In some implementations, the circuitry is configured to generate the error information in response to detecting a failure of error correction on at least a portion of the readout data, e.g., a value of the Error code is “22h” as shown in Table 3. The readout data can include a first portion of the readout data output concurrently with the error code, e.g., the first portion334aof OutDATA334ofFIG.3B, and a second portion of the readout data output after the error code, e.g., the second portion334bof OutDATA334ofFIG.3B. The failure of error correction is on the second portion of the readout data.

In some implementations, the controller receives the read packet from the semiconductor device, and can detect the error information associated with the readout data based on the at least one of the error code or the one or more secure codes in the read packet.

In some implementations, the controller is configured to: receive the error code before the readout data and the one or more secure codes in the read packet (e.g., as shown in FIG.3B) and detect the error information associated with the readout data based on the one or more secure codes in the read packet.

In some examples, the one or more secure codes include a secure data code (e.g., OutMAC336ofFIG.3B) based on the readout data. The controller is configured to: generate MAC of the readout data received in the read packet, compare the generated MAC with the secure data code received in the read packet to determine whether the generated MAC is different from the secure data code received in the read packet, and determine that there is an error associated with the readout data received in the read packet if the generated MAC is different from the secure data code received in the read packet.

In some examples, the one or more secure codes include a secure packet code (e.g., CRC338ofFIG.3B) based on the read packet. The controller is configured to: generate CRC of the read packet, compare the generated CRC with the secure packet code received in the read packet to determine whether the generated CRC is different from the secure packet code received in the read packet, and determine that there is an error associated with the readout data received in the read packet if the generated CRC is different from the secure packet code received in the read packet.

In some implementations, the controller is configured to receive the error code after the readout data (e.g., as shown inFIG.3C), and detect the error information associated with the readout data based on the error code

The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).