Semiconductor device suitable for a ferroelectric memory and manufacturing method of the same

After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-099063, filed on Mar. 30, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method of the same.

2. Description of the Related Art

In recent years, the development of a ferroelectric memory (FeRAM) which holds information in a ferroelectric capacitor using polarization inversion of a ferroelectric has been advanced. The ferroelectric memory is a nonvolatile memory in which held information is not erased even if the power is turned off, and attracts special attention because it can realize high-density integration, an increase in driving speed, an improvement in durability, and a reduction in power consumption.

As materials for a ferroelectric film composing the ferroelectric capacitor, ferroelectric oxides having a perovskite crystal structure such as PZT(Pb(Zr, Ti)O3)), SBT(SrBi2Ta2O9), and the like are mainly used. These materials can obtain a remanent polarization amount as large as approximately 10 μC/cm2to 30 μC/cm2. However, regarding such a ferroelectric film, it is known that ferroelectric characteristics deteriorate due to moisture which has penetrated from the outside through an interlayer insulating film such as a silicon oxide film having a high affinity to moisture. The moisture which has penetrated into the ferroelectric memory (semiconductor device) from the outside is decomposed into hydrogen and oxygen during a high-temperature process when the interlayer insulating film and a metal wiring are formed. Then, the hydrogen which has reached the ferroelectric film reacts with oxygen in the ferroelectric film to cause oxygen deficiency to the ferroelectric film, which results in a reduction in crystallinity.

Moreover, if a ferroelectric memory is used over a long period of time after being manufactured, in some cases, the remanent polarization amount and dielectric constant of the ferroelectric film reduce accompanying the penetration of hydrogen, and thereby the performance of the ferroelectric capacitor deteriorates. Such a deterioration in performance occurs not only in the ferroelectric capacitor but also in other semiconductor elements such as a transistor.

FIG. 19shows a general view of a semiconductor circuit on which general logic circuits or ferroelectric capacitors are mounted. It shows a multi-tip structure, in which plural chips are formed in one shot.FIG. 20shows an enlarged view of one chip. As shown inFIG. 20, one chip is partitioned into a PAD section located at an outer periphery of the chip and a circuit section located inside the PAD section. In the case of a product in which both the logic circuit and the ferroelectric capacitor are mounted, the circuit section is further partitioned into a FeRAM section and a logic section.FIG. 21shows a layout of a section taken along the line X-Y inFIG. 20. From the X side, this chip is partitioned into a scribe section501, a scribe section-PAD section boundary section502, a PAD section503, a PAD section-circuit section boundary section504, a FeRAM section (cell section)505, a circuit-circuit boundary section506, a logic section507, a PAD section-circuit section boundary section508, a PAD section509, a scribe section-PAD section boundary section510, and a scribe section511. Outside the scribe sections501and511are regions for other chips.

FIG. 22is a sectional view showing the structure of the PAD section (a sectional view taken along the line A-B) of the semiconductor circuit on which the general logic circuit or the ferroelectric capacitor is mounted. As shown inFIG. 22, a silicon oxide film522and a silicon nitride film523are formed as a passivation film on a PAD wiring portion (wiring portion526), and a polyimide layer (PI layer)524is formed thereon. The PAD wiring portion526is formed on a wiring portion521with wiring contact portions525therebetween. A silicon oxide film527is formed between the wiring portion521and the PAD wiring portion526. Such a structure is a general PAD structure, but this PAD structure has the following problems.

First, the silicon oxide film522does not have a moisture and hydrogen barrier function, and if anything, it has hygroscopicity. Accordingly, when the silicon oxide film522is exposed to the surface, it allows moisture and hydrogen to permeate therethrough.

Secondly, the silicon nitride film523has a moisture barrier function to some extent, but allows hydrogen to permeate therethrough. If the silicon nitride film523is thickened simply in order to prevent moisture, a moisture barrier property is correspondingly improved. However, gas (for example, ammonia) containing a hydrogen group is used in the process of forming the silicon nitride film523, whereby the ferroelectric capacitor deteriorates due to the influence thereof. Therefore, the silicon nitride film cannot be thickened excessively.

Thirdly, similarly to the silicon oxide film522, the polyimide layer524has no moisture and hydrogen barrier property.

Hence, the following events occur in conventional PAD section structure and circuit section structure.

(A) Moisture and hydrogen penetrate into the PAD section.

(B) Hydrogen and a little moisture penetrate into the circuit section.

Namely, in the conventional PAD section structure, the penetration of moisture and hydrogen cannot be fully prevented. Moreover, as shown inFIG. 23, the silicon nitride film523may crack.

To improve these problems, a technique for preventing the penetration of moisture and hydrogen by using a metal film is disclosed in Patent Documents 1 and 4. A principal structure thereof is shown inFIG. 24. A metal wiring532, an insulating film533, a passivation film534, and a bonding pad535are formed on an interlayer insulating film531. This structure is characterized in that a metal PAD section is further formed on the PAD section to prevent the silicon oxide film above the PAD section from being exposed. However, even in this structure, the following events occur.

(A) No moisture penetrates into the PAD section. The hydrogen barrier property is high because of a metal film. However, in actuality, a sidewall of the metal PAD section on the PAD section easily cracks. Moreover, when the structure of such a publicly known example is adopted, it is necessary that after the metal PAD section is formed thick, it is subjected to CMP processing to be planarized or subjected to plating. But, this is not described in Patent Documents 1 and 4. Accordingly, the structure formed by the method described in Patent Documents 1 and 4 is as shown inFIG. 25. Further, a structure shown inFIG. 26is disclosed as the structure obtained after the CMP processing, but in the case of this structure, micro-scratches are generated in the passivation film (silicon nitride film)534at the time of the CMP processing of the PAD section.

(B) A little moisture and hydrogen as it is penetrate into the circuit section.

(C) Since the passivation film is used as an etching stopper when the second metal film is formed, irregularities occur on the surface, and hydrogen easily penetrates from its microscopic irregular portions.

A technique for preventing the penetration of moisture and hydrogen is disclosed also in Patent Document 2. A principal structure thereof is shown inFIG. 27AandFIG. 27B. An aluminum film542, an interlayer film543, an aluminum film544, and a cover film545are formed on a semiconductor substrate541, and a bonding wire546is connected to the aluminum film544. In this structure, the PAD section is entirely coated with the metal film (aluminum film544), but the following events occur.

(A) No moisture penetrates into the PAD section. A method of forming the aluminum film544is not described, but by adopting such a structure, only in the PAD section, the penetration of moisture is eliminated and the penetration of hydrogen is reduced.

(B) There is no description of the circuit section, but considering a technical level of those days, it is thought that the circuit section has a structure such as shown inFIG. 28. In this structure, moisture and hydrogen penetrate from above.

A technique for preventing the penetration of moisture and hydrogen is disclosed also in Patent Document 3. A principal structure thereof is shown inFIG. 29. An interlayer insulating film552, a pad metal film553, a PSG film554, a silicon nitride film555, and a metal film556are formed on a semiconductor substrate551. In this structure, the PAD section is entirely coated with the metal film556, but the following events occur.

(A) Since the PAD section is coated with the metal film556, no moisture penetrates thereinto. However, when the metal film556is an aluminum film, its hydrogen barrier property is not so high, whereby a little hydrogen penetrates. Further, since the metal film556on a sidewall of the PAD section cannot be formed thick by a sputtering method, there is a possibility that a crack opens later.

(B) There is no description of the circuit section, but considering a technical level of those days, it is thought that the circuit section has a structure such as shown inFIG. 30. In this structure, moisture and hydrogen penetrate from above.

As just described, even if these conventional techniques are adopted, it is extremely difficult to fully inhibit deterioration of the ferroelectric capacitor or the like accompanying the penetration of moisture.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device capable of inhibiting deterioration accompanying the penetration of moisture and hydrogen and a manufacturing method of the same.

As a result of assiduous study to solve the aforementioned problems, the present inventors have arrived at aspects of the present invention shown below.

In a semiconductor device according to the present invention, an element, a conductive pad connected to the element, and a silicon oxide film formed around the conductive pad are provided. Further provided is a penetration inhibiting film inhibiting penetration of hydrogen and moisture into the silicon oxide film.

In a manufacturing method of a semiconductor device according to the present invention, after an element is formed, a conductive pad connected to the element is formed. Then, a silicon oxide film is formed around the conductive pad. Thereafter, a penetration inhibiting film which inhibits penetration of hydrogen and moisture into the silicon oxide film is formed. It is desirable to form the penetration inhibiting film not only on a PAD section but also extensively on a circuit and on a scribe.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be specifically described below with reference to the attached drawings.FIG. 1is a circuit diagram showing the configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by methods according to embodiments of the present invention.

In this memory cell array, plural bit lines103which extend in one direction and plural word lines104and plate lines105which extend in a direction perpendicular to the direction in which the bit lines103extend are provided. Additionally, plural memory cells of a ferroelectric memory are arranged in an array form in such a manner as to match a grid composed of these bid lines103, word lines104, and plate lines105. In each memory cell, a ferroelectric capacitor (storage part)101and a MOS transistor (switching part)102are provided.

A gate of the MOS transistor102is connected to the word line104. One source/drain of the MOS transistor102is connected to the bit line103and the other source/drain thereof is connected to one electrode of the ferroelectric capacitor101. The other electrode of the ferroelectric capacitor101is connected to the plate line105. Incidentally, each of the word lines104and the plate lines105is shared by plural MOS transistors102arranged in the same direction as the direction in which this line extends. Similarly, each of the bit lines103is shared by plural MOS transistors102arranged in the same direction as the direction in which this line extends. The direction in which the word lines104and the plate lines105extend and the direction in which the bit lines103extend are sometimes called a row direction and a column direction, respectively. It is noted that the arrangement of the bit lines103, the word lines104, and the plate lines105is not limited to the arrangement described above.

In the memory cell array of the ferroelectric memory thus configured, data is stored according to the polarization state of a ferroelectric film provided in the ferroelectric capacitor101.

First Embodiment

Next, the first embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 2AtoFIG. 2Hare sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the first embodiment of the present invention step by step.

Manufactured as the semiconductor device according to the embodiment is a semiconductor device which, as shown inFIG. 10, includes, from the left, a scribe section201, a scribe section-PAD section boundary section202, a PAD section203, a PAD section-circuit section boundary section204, a logic section205, a circuit-circuit boundary section206, a FeRAM section (ferroelectric capacitor section)207, a PAD section-circuit section boundary section208, a PAD section209, a scribe section-PAD section boundary section210, and a scribe section211.

In the following description, methods of forming regions other than the FeRAM section207are represented by a method of forming the FeRAM section207, and hence the explanation thereof is omitted.

Incidentally, as shown inFIG. 11, if the vertical structure of the semiconductor device is partitioned, it is also said that the semiconductor device is composed of a wiring layer301, a ferroelectric layer302, and a transistor layer303. The transistor layer303contains a transistor (not shown) used in a FeRAM memory and a transistor (not shown) used in the logic section205. In the FeRAM207, the transistor is located near or under a FeRAM capacitor, and in the logic section205, the transistor is located near or under a logic circuit. Incidentally, to simplify the figure, the transistor in the logic section205is omitted from the figure.

In this embodiment, first, as shown inFIG. 2AandFIG. 10, an element isolation insulating film2which demarcates an element active region is formed on the surface of a semiconductor substrate1such as a Si substrate, for example, by a LOCOS (Local Oxidation of Silicon) method. Then, a transistor (MOSFET) which includes a gate insulating film3, a gate electrode4, a silicide layer5, a sidewall6, and a source/drain diffusion layer composed of a low-concentration diffusion layer21and a high-concentration diffusion layer22is formed in the element active region demarcated by the element isolation insulating film2. This transistor corresponds to the MOS transistor102inFIG. 1. As the gate insulating film3, a SiO2film having a thickness of approximately 100 nm is formed, for example, by thermal oxidation. Subsequently, a silicon oxynitride film7is formed over the entire surface so as to cover the MOSFET, and a silicon oxide film8ais further formed over the entire surface. The silicon oxynitride film7is formed to prevent hydrogen deterioration of the gate insulating film3and so on when the silicon oxide film8ais formed. The silicon oxide film8ais formed by a CVD method, for example, with using TEOS (tetraethylorthosilicate) as material, and a thickness thereof is approximately 700 nm, for example.

Thereafter, the silicon oxide film8ais degassed by annealing at 650° C. for 30 minutes in an N2atmosphere. Then, as a bottom electrode adhesive layer, an Al2O3film8bwith a thickness of approximately 20 nm is formed on the silicon oxide film8a, for example, by a sputtering method. A bottom electrode film9is formed on the Al2O3film8b. As the bottom electrode film9, a Pt film with a thickness of approximately 150 nm is formed, for example, by a sputtering method.

Then, similarly as shown inFIG. 2A, a ferroelectric film10is formed in an amorphous state on the bottom electrode film9. As the ferroelectric film10, a PLZT film with a thickness approximately between 100 nm and 200 nm is formed, for example, using a PLZT((Pb, La)(Zr, Ti)O3) target by a RF sputtering method. Subsequently, RTA (Rapid Thermal Annealing) at 650° C. or lower in an atmosphere containing Ar and O2is performed, and further RTA at 750° C. in an oxygen atmosphere is performed. As a result, the ferroelectric film10is completely crystallized, and the Pt film, which composes the bottom electrode film9, is densified, which inhibits mutual diffusion between Pt and O in the vicinity of an interface between the bottom electrode film9and the ferroelectric film10.

Thereafter, similarly as shown inFIG. 2A, a top electrode film11is formed on the ferroelectric film10. In the formation of the top electrode film11, an iridium oxide film with a thickness approximately between 200 nm and 300 nm is formed, for example, by a sputtering method.

Then, by patterning the top electrode film11, as shown inFIG. 2B, a top electrode11ais formed. Subsequently, heat treatment in an atmosphere containing oxygen to recover damage and the like caused by patterning is performed. Thereafter, by patterning the ferroelectric film10, similarly as shown inFIG. 2B, a capacitor insulating film10ais formed. Then, oxygen annealing for preventing an Al2O3film to be formed later from peeling off is performed. Subsequently, similarly as shown inFIG. 2B, as a protective film, an Al2O3film12is formed over the entire surface by a sputtering method. Thereafter, to mitigate damage caused by sputtering, oxygen annealing is performed. Penetration of hydrogen into the ferroelectric capacitor from the outside is prevented by the protective film (Al2O312).

Then, similarly as shown inFIG. 2B, by patterning the Al2O3film12and the bottom electrode film9, a bottom electrode9ais formed. Subsequently, oxygen annealing for preventing an Al2O3film to be formed later from peeling off is performed. The ferroelectric capacitor including the bottom electrode9a, the capacity insulating film11a, and the top electrode11acorresponds to the ferroelectric capacitor101inFIG. 1. Thereafter, similarly as shown inFIG. 2B, as a protective film, an Al2O3film13is formed over the entire surface by a sputtering method. Then, oxygen annealing is performed in order to reduce capacitor leakage.

Subsequently, as shown inFIG. 2C, an interlayer insulating film14is formed over the entire surface by a high density plasma method. The thickness of the interlayer insulating film14is, for example, approximately 1.5 μm. Thereafter, the interlayer insulating film14is planarized by a CMP (chemical mechanical polishing) method. Then, plasma processing using an N2O gas is performed. As a result, a surface layer portion of the interlayer insulating film14is slightly nitrided and thereby it becomes difficult for moisture to penetrate thereinto. Incidentally, this plasma processing is effective if gas containing at least one of N and O is used.

Subsequently, as shown inFIG. 2D, a hole which reaches the silicide layer5on the high-concentration diffusion layer22of the transistor is formed in the interlayer insulating film14, the Al2O3film8b, the silicon oxide film8a, and the silicon oxynitride film7. Thereafter, by forming a Ti film and a TiN film continuously in the hole by a sputtering method, a barrier metal film (not shown) is formed. Subsequently, a W film is embedded in the hole by a CVD (chemical vapor deposition) method, and by planarizing the W film by a CMP method, a W plug15is formed.

Then, as an oxidation preventing film of the W plug15, a SiON film (not shown) is formed, for example, by a plasma enhanced CVD method. Subsequently, a contact hole which reaches the top electrode11aand a contact hole which reaches the bottom electrode9aare formed in the SiON film, the interlayer insulating film14, the Al2O3film13, and the Al2O3film12. Thereafter, to recover damage, oxygen annealing is performed. Then, by removing all the SiON film by etch-back, the surface of the W plug15is exposed. Then, similarly as shown inFIG. 2D, by forming a barrier metal film, an Al film, and a barrier metal film in a state where a portion of the surface of the top electrode11a, a portion of the surface of the bottom electrode9a, and the surface of the W plug15are exposed and patterning these films, a wiring17is formed. At this time, the W plug15and the top electrode11aare connected to each other by a portion of the wiring17, for example.

Subsequently, as shown inFIG. 2E, a silicon oxide film19is formed over the entire surface, for example, by a high density plasma method, and the surface thereof is planarized. Thereafter, on the silicon oxide film19, an Al2O3film20is formed as a protective film to prevent penetration of hydrogen and moisture over the entire surface of a chip. Further, a silicon oxide film23is formed on the Al2O3film20, for example, by a high density plasma method.

Then, similarly as shown inFIG. 2E, a via hole which reaches the wiring17is formed in the silicon oxide film23, the Al2O3film20, and the silicon oxide film19and a W plug24is embedded therein.

Subsequently, similarly as shown inFIG. 2E, a wiring25, a silicon oxide film26, an Al2O3film27over the entire surface of the chip, a silicon oxide film28, W plugs29, and an Al wiring30are formed.

Thereafter, as shown inFIG. 2F, a silicon oxide film32and a silicon nitride film33are formed. In the formation of the silicon oxide film32, for example, TEOS (tetraethylorthosilicate) is used as a material therefor. The thickness of the silicon oxide film32is approximately between 100 nm and 1500 nm. When CMP is performed after the silicon oxide film32is formed, approximately 1200 nm or more is preferable, but unless CMP is performed, approximately 100 nm is sufficient. The thickness of the silicon nitride film33is approximately between 100 nm and 1000 nm.

Then, as shown inFIG. 2G, an opening34to expose a portion of the Al wiring30is formed in the silicon oxide film32and the silicon nitride film33. In the formation of the opening34, for example, anisotropic etching using a resist pattern is performed. Subsequently, as a penetration inhibiting film which blocks the penetration of hydrogen and moisture into the silicon oxide film32, an Al2O3film35is formed over the entire surface. The thickness of the Al2O3film35is preferably, for example, approximately between 30 nm and 100 nm when the Al2O3film35is formed by a sputtering method, and sufficient to be 10 nm or more when it is formed by an MO-CVD method.

Thereafter, as shown inFIG. 2H, an opening36to expose a portion of the Al wiring30is formed in the Al2O3film35. Then, a polyimide layer37is formed, and an opening38to expose the opening36is formed in the polyimide layer37. The portion of the Al wiring30exposed from the openings38and36is used as a pad.FIG. 12is a sectional view showing a structure in which a portion of the Al wiring30is used as a pad. Wiring to the pad may be formed in a layer of the Al wiring30or may be formed in a lower wiring layer.

Incidentally, the Al2O3film35as the penetration inhibiting film is placed in a region other than a PAD opening portions as shown inFIG. 13andFIG. 14B. As described above, the semiconductor device can be partitioned into the scribe section211, the scribe section-PAD section boundary section210, the PAD section209, the PAD section-circuit section boundary section208, the FeRAM section (cell section)207, the circuit-circuit boundary section206, the logic section205, and the PAD section-circuit section boundary section204, and so on. The layout thereof is as shown inFIG. 14A. Note that the Al2O3film35does not exist on the openings of the PAD section. Incidentally, a wiring under the PAD may be a Al—Cu wiring or an embedded Cu wiring.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

As described above, according to this embodiment, the silicon oxide film32and the silicon nitride film33are covered with the Al2O3film35. Namely, the Al2O3film35is formed on the silicon nitride film33not only on a side surface of the opening for the pad but also over the entire ferroelectric memory. Therefore, the diffusion of not only hydrogen and moisture penetrating from the opening for the pad but also hydrogen and moisture penetrating from the surface of the ferroelectric memory into the inside can be inhibited. This makes it possible to inhibit deterioration in the characteristics of the ferroelectric capacitor accompanying oxygen deficiency and the like. Incidentally, in structures described in conventional Patent Documents 1 to 3, it is difficult to block hydrogen and moisture penetrating from the surface of the semiconductor chip.

Second Embodiment

Next, the second embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 3AtoFIG. 3Care sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention step by step.

In the second embodiment, first, as shown inFIG. 3A, a series of processing steps until the formation of the silicon oxide film32and the silicon nitride film33is performed in the same manner as in the first embodiment.

Then, as shown inFIG. 3B, the opening34to expose a portion of the Al wiring30is formed in the silicon oxide film32and the silicon nitride film33by isotropic etching. Subsequently, by performing sputtering etching in an Ar atmosphere, an upper end portion of the opening34is rounded off. Thereafter, in the same manner as in the first embodiment, the Al2O3film35as the penetration inhibiting film which blocks the penetration of hydrogen and moisture is formed over the entire surface.

Then, as shown inFIG. 3C, the opening36to expose a portion of the Al wiring30is formed in the Al2O3film35. Then, the polyimide layer37is formed, and the opening38to expose the opening36is formed in the polyimide layer37. The portion of the Al wiring30exposed from the openings38and36is used as a pad. Incidentally, also in this embodiment, as shown inFIG. 13,FIG. 14A, andFIG. 14B, the Al2O3film35is formed in the region other than the PAD opening portions.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

Also in the aforementioned second embodiment, the same effect as in the first embodiment can be obtained.

Third Embodiment

Next, the third embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 4is a sectional view showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the third embodiment of the present invention step by step.

In the third embodiment, first, as shown inFIG. 4, a series of processing steps until the formation of the silicon oxide film32is performed in the same manner as in the first embodiment. Then, the silicon oxide film32is planarized by a CMP method or the like. Subsequently, the silicon nitride film33is formed on the silicon oxide film32.

Thereafter, similarly as shown inFIG. 4, the opening34to expose a portion of the Al wiring30is formed in the silicon oxide film32and the silicon nitride film33. Then, the Al2O3film35as the penetration inhibiting film which blocks the penetration of hydrogen and moisture is formed over the entire surface.

Subsequently, similarly as shown inFIG. 4, the opening36to expose a portion of the Al wiring30is formed in the Al2O3film35. Thereafter, the polyimide layer37is formed, and the opening38to expose the opening36is formed in the polyimide layer37. The portion of the Al wiring30exposed from the openings38and36is used as a pad. Incidentally, also in this embodiment, as shown inFIG. 13,FIG. 14A, andFIG. 14B, the Al2O3film35is formed in the region other than the PAD opening portions.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

Also in the aforementioned third embodiment, the same effect as in the first embodiment can be obtained.

Fourth Embodiment

Next, the fourth embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 5AtoFIG. 5Care sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the fourth embodiment of the present invention step by step.

In the fourth embodiment, first, as shown inFIG. 5A, a series of processing steps until the planarization of the silicon oxide film32is performed in the same manner as in the third embodiment. Then, an opening34ato expose a portion of the Al wiring30is formed in the silicon oxide film32. Subsequently, a TiN film41is formed as a conductive film over the entire surface. The thickness of the TiN film41is, for example, approximately between 50 nm and 200 nm.

Thereafter, as shown inFIG. 5B, the TiN film41is patterned. In this patterning, the TiN film41is processed in such a manner that an outer edge of a piece of the TiN film41which contacts the Al wiring30is located inside an outer edge of the Al wiring30in plan view. Namely, the portion of the TiN film41which contacts the Al wiring30is left as an island. Moreover, a portion other than this portion needs to be left as wide as possible within a range in which a short circuit between the portion and the portion as an island does not occur.

Then, as shown inFIG. 5C, the silicon nitride film33is formed over the entire surface. Subsequently, an opening34bto expose the portion of the TiN film which contacts the Al wiring30is formed in the silicon nitride film33. Thereafter, the polyimide layer37is formed, and the opening38to expose the opening34bis formed in the polyimide layer37. A portion of a stacked body of the TiN film41and the Al wiring30exposed from the openings38and34bis used as a pad.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

In the aforementioned fourth embodiment, the TiN film41functions as the penetration inhibiting film which blocks the penetration of hydrogen and moisture. In other words, the portion of the TiN film41which contacts the Al wiring30inhibits the penetration of moisture and so on from the opening for the pad. Moreover, a portion of the TiN film41which does not contact the Al wiring30inhibits the diffusion of moisture and so on, which penetrate from the surface of the ferroelectric memory, into the inside. Accordingly, as in the first embodiment, deterioration in the characteristics of the ferroelectric capacitor accompanying oxygen deficiency and the like can be inhibited.

Namely, in this embodiment, as shown inFIG. 15A,FIG. 15B,FIG. 15C, andFIG. 16, the TiN film41is formed in a region except the vicinity of each of the PAD opening portions.FIG. 15Bis an enlarged view showing a region enclosed by a broken line in FIG.15A, andFIG. 15Cis a diagram showing the layout of the TiN film41in the region shown inFIG. 15B. Incidentally, in this embodiment, the TiN film41is exposed in a topmost surface, but in this structure, when a probe is placed in a test process, there is a possibility that the probe slips. Therefore, it is desirable to form a thin film containing Al on the TiN film41. Further, a stacked body of a TiN film and a film containing Al may be formed.

Fifth Embodiment

Next, the fifth embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 6AtoFIG. 6Care sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the fifth embodiment of the present invention step by step.

In the fifth embodiment, first, as shown inFIG. 6A, a series of processing steps until the formation of the Al wiring30is performed in the same manner as in the first embodiment. Then, the silicon oxide film32is formed. Subsequently, the silicon oxide film32is planarized until the Al wiring30is exposed.

Thereafter, as shown inFIG. 6B, by etching back the silicon oxide film32, the surface of the silicon oxide film32is made lower than the surface of the Al wiring30. Then, as the penetration inhibiting film which blocks the penetration of hydrogen and moisture, the Al2O3film35is formed over the entire surface of the chip. Further, the silicon nitride film33is formed on the Al2O3film35.

Subsequently, as shown inFIG. 6C, an opening42to expose a portion of the Al wiring30is formed in the silicon nitride film33and the Al2O3film35. Thereafter, the polyimide layer37is formed, and the opening38to expose the opening42is formed in the polyimide layer37. The portion of the Al wiring30exposed from the openings38and42is used as a pad. Incidentally, also in this embodiment, as shown inFIG. 13,FIG. 14A, andFIG. 14B, the Al2O3film35is formed in the region other than the PAD opening portions.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

Also in the aforementioned fifth embodiment, the same effect as in the first embodiment can be obtained.

Incidentally, the etch-back of the silicon nitride film32is not necessarily required, but when etch-back is done, the penetration of moisture and so on becomes more difficult, so that etch-back is desirable.

Sixth Embodiment

Next, the sixth embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 7AtoFIG. 7Hare sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the sixth embodiment of the present invention step by step.

In the sixth embodiment, first, as shown inFIG. 7A, a series of processing steps until the planarization of the silicon oxide film32is performed in the same manner as in the third embodiment. Then, a resist pattern51having an opening which matches a portion of the Al wiring30in plan view is formed on the silicon oxide film32.

Subsequently, as shown inFIG. 7B, by anisotropic etching of the silicon oxide film32using the resist pattern51, the opening34ato expose the portion of the Al wiring30is formed in the silicon oxide film32. Thereafter, the resist pattern51is removed. Then, the silicon oxide film32is annealed in an N2atmosphere. By this annealing, the silicon oxide film32is degassed and the surface of the silicon oxide film32is nitrided, which makes moisture absorption difficult. Also in the first to sixth embodiments, it is desirable to perform the same annealing. This annealing may be omitted.

Then, as shown inFIG. 7C, as the penetration inhibiting film which blocks the penetration of hydrogen and moisture, the Al2O3film35is formed over the entire surface of the chip.

Subsequently, as shown inFIG. 7D, the silicon nitride film33is formed on the Al2O3film35.

Thereafter, as shown inFIG. 7E, a resist pattern52having an opening formed inside the opening34ain plan view is formed on the silicon nitride film33.

Then, as shown inFIG. 7F, by anisotropic etching of the silicon nitride film33and the Al2O3film35using the resist pattern52, the opening42to expose a portion of the Al wiring30is formed in the silicon nitride film33and the Al2O3film35. Subsequently, the resist pattern52is removed.

Thereafter, as shown inFIG. 7G, the polyimide layer37is formed. Then, as shown inFIG. 7H, the opening38to expose the opening42is formed in the polyimide layer37. The portion of the Al wiring30exposed from the openings38and42is used as a pad. Incidentally, also in this embodiment, as shown inFIG. 13,FIG. 14A, andFIG. 14B, the Al2O3film35is formed in the region other than the PAD opening portions.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

Also in the aforementioned sixth embodiment, the same effect as in the first embodiment can be obtained. Incidentally, as in the second embodiment, it is also possible to form the opening34aby isotropic etching and perform sputtering etching in the Ar atmosphere.

Seventh Embodiment

Next, the seventh embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 8AtoFIG. 8Iare sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the seventh embodiment of the present invention step by step.

In the seventh embodiment, first, as shown inFIG. 8A, a series of processing steps until the formation of the silicon oxide film32is performed in the same manner as in the first embodiment. Then, as shown inFIG. 8B, the silicon oxide film32is planarized until the Al wiring30is exposed.

Subsequently, as shown inFIG. 8C, a silicon nitride film61is formed over the entire surface. The thickness of the silicon nitride film61is, for example, approximately between 50 nm and 300 nm. Thereafter, as shown inFIG. 8D, as the penetration inhibiting film which blocks the penetration of hydrogen and moisture, the Al2O3film35is formed over the entire surface of silicon nitride film61.

Then, as shown inFIG. 8E, a silicon nitride film62is formed on the Al2O3film35. The thickness of the silicon nitride film62is, for example, approximately between 100 nm and 1000 nm. Subsequently, as shown inFIG. 8F, a resist pattern63having an opening which matches a portion of the Al wiring30in plan view is formed on the silicon nitride film62.

Thereafter, as shown inFIG. 8G, by anisotropic etching of the silicon nitride film62, the Al2O3film35, and the silicon nitride film61using the resist pattern63, an opening64to expose the portion of the Al wiring30is formed in the silicon nitride film62, the Al2O3film35, and the silicon nitride film61. Then, the resist pattern63is removed.

Subsequently, as shown inFIG. 8H, the polyimide layer37is formed. Thereafter, the opening38to expose the opening64is formed in the polyimide layer37. The portion of the Al wiring30exposed from the openings38and64is used as a pad. Incidentally, also in this embodiment, as shown inFIG. 13,FIG. 14A, andFIG. 14B, the Al2O3film35is formed in the region other than the PAD opening portions.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

Also in the aforementioned seventh embodiment, the same effect as in the first embodiment can be obtained. Incidentally, the formation of the silicon nitride film62may be omitted. Moreover, as in the fifth embodiment, the silicon oxide film32may be etched back.

Eighth Embodiment

Next, the eighth embodiment of the present invention will be described. Note that here, for convenience, a cross-sectional structure of a semiconductor device will be described with a manufacturing method thereof.FIG. 9AtoFIG. 9Jare sectional views showing a manufacturing method of a ferroelectric memory (semiconductor device) according to the eighth embodiment of the present invention step by step.

In the eighth embodiment, first, as shown inFIG. 9A, a series of processing steps until the formation of the resist pattern51is performed in the same manner as in the sixth embodiment. Then, as shown inFIG. 9B, by anisotropic etching of the silicon oxide film32using the resist pattern51, the opening34ato expose a portion of the Al wiring30is formed in the silicon oxide film32. Subsequently, the resist pattern51is removed. Thereafter, the silicon oxide film32is annealed in an N2atmosphere.

Then, as shown inFIG. 9C, the TiN film41as a conductive film is formed over the entire surface as in the fourth embodiment. Subsequently, as shown inFIG. 9D, a resist pattern71is formed on the TiN film41. At this time, used as the resist pattern71is a resist pattern in which an opening is formed in such a manner that an outer edge of a portion of the TiN film41which contacts the Al wiring30is located inside an outer edge of the Al wiring30in plan view. In other words, by subsequent etching, the portion of the TiN film41which contacts the Al wiring30is left as an island. Moreover, a portion other than this portion needs to be covered with the TiN film41as wide as possible within a range in which a short circuit between the portion and the portion left as an island does not occur.

Thereafter, as shown inFIG. 9E, by anisotropic etching of the TiN film41using the resist pattern71, the TiN film41is processed into an island-like portion and a portion which covers the silicon oxide film32.

Then, as shown inFIG. 9F, as the penetration inhibiting film which blocks the penetration of hydrogen and moisture, the Al2O3film35is formed over the entire surface. Subsequently, as shown inFIG. 41, the silicon nitride film33is formed on the Al2O3film35.

Thereafter, as shown inFIG. 9H, a resist pattern72having an opening formed inside the opening34ain plan view is formed on the silicon nitride film33. Then, as shown inFIG. 9I, by anisotropic etching of the silicon nitride film33and the Al2O3film35using the resist pattern72, an opening73to expose the portion of the TiN film41which contacts the Al wiring30is formed. Subsequently, the resist pattern72is removed.

Thereafter, as shown inFIG. 9J, the polyimide layer37is formed, and the opening38to expose the opening73is formed in the polyimide layer37. A portion of a stacked body of the TiN film41and the Al wiring30exposed from the openings38and73is used as a pad. Incidentally, also in this embodiment, as shown inFIG. 13,FIG. 14A, andFIG. 14B, the Al2O3film35is formed in the region other than the PAD opening portions.

Thus, the ferroelectric memory including the ferroelectric capacitor is completed.

Also in the aforementioned eighth embodiment, the same effect as in the fourth embodiment can be obtained.

Incidentally, in these embodiments, the ferroelectric capacitor has a planar structure, but may have a stacked structure.

Moreover, in the first to eighth embodiments, if dicing in the scribe sections201and211is performed, a side surface of the silicon oxide film32is exposed, but since a moisture-resistant ring220as a moisture protective film is usually formed inside a scribe line so as to surround the entire chip as shown inFIG. 17, moisture does not penetrate from a side surface of the chip even after dicing.FIG. 17shows the moisture-resistant ring220in the eighth embodiment as an example.

Further, when a portion of the silicon oxide film32outside the moisture-resistant ring220connects with a portion thereof inside the moisture-resistant ring220as shown inFIG. 18A, the connecting portion may be blocked with the TiN film41, as shown inFIG. 18B. Such a structure can be realized, for example, in the following manner. Namely, after the Al wiring30including the PAD is formed, the silicon oxide film32is formed, and portions of the silicon oxide film on the PAD and on the moisture-resistant ring220are removed at the same time. Thereafter, the TiN film (or metal film) is formed over the entire surface of the chip, and the TiN film (or metal film) is left only in necessary portions. Such a structure makes it possible to more certainly prevent the penetration of moisture after dicing. Additionally, the penetration of moisture and hydrogen from above is prevented by the TiN film41.

Furthermore, the type of the semiconductor device is not limited to the ferroelectric memory, and the present invention is also applicable to a DRAM, an SRAM, an LSI, and so on. When the ferroelectric capacitor is not formed, it is desirable to perform heat treatment at 350° C. or higher during the period from the formation of the silicon oxide film to the formation of the penetration inhibiting film. For example, the heat treatment is performed under the following conditions: Temperature=360° C.; N2flow rate=20 litter/minute; and Time=30 minutes. However, if the heat treatment at 400° C. or higher is performed, there is a possibility that the Al wiring and the like is deformed. On the other hand, when the ferroelectric capacitor is formed, it is desirable to perform heat treatment at 350° C. or lower during the period from the formation of the silicon oxide film to the formation of the penetration inhibiting film.

Moreover, in place of the Al2O3film35, an oxide film, a nitride film, a carbide film, or a polyimide film may be formed as the penetration inhibiting film. Examples of the oxide film are a titanium oxide film and a coating-type oxide film (for example, SOG (Spin on glass) film). Examples of the nitride film are a silicon nitride film, a silicon oxynitride film, and a boron nitride film. Examples of the carbide film are a silicon carbide film and a diamond-like carbon film. The thickness of the penetration inhibiting film is, for example, 20 nm or more, and preferably 50 nm or more. Incidentally, approximately 100 nm is sufficient for the thickness of the penetration inhibiting film. As examples of a method of forming the metal oxide film, a CVD method such as a MOCVD method and a sputtering method are given. When the silicon oxide film is heat-treated, it is desirable to move a wafer into another chamber without bringing the silicon oxide film into contact with the outside air after the heat treatment and form the metal oxide film there.

Further, as the conductive film, a Ti film, an Al film, an iridium oxide film, or the like may be formed in place of the TiN film41.

Furthermore, the wiring material is not particularly limited, and an Al wiring, a Cu wiring, a Al—Cu alloy wiring, and the like may be used. Especially when the Cu wiring is formed, it is desirable to adopt a damascene method. Note that even when the Cu wiring or the Al—Cu alloy wiring is used, it is desirable to use the Al film as the pad.

Besides, in any of the embodiments, as the ferroelectric for example, a PbZr1-xTixO3film, a Pb1-xLaxZr1-yTiyO3film, a SrBi2(TaxNb1-x)2O9film, a Bi4Ti2O12film, or the like can be used. Moreover, as the wiring material, in addition to Al and Cu, an Al—Cu alloy or the like may be used.

When the present inventors actually carried out a high-temperature/high humidity test up to 672 hours on a ferroelectric memory manufactured by a method according to the third embodiment and a ferroelectric memory manufactured by a conventional method, results shown in Table 1 were obtained.

As shown in Table 1, many defects occurred in the conventional method, but in the method according to the third embodiment, the semiconductor device in which an extremely small number of defects occurred could be obtained. Namely, in the method according to the third embodiment, deterioration in the characteristics of the ferroelectric capacitor accompanying oxygen deficiency and the like due to reduction by moisture or hydrogen was inhibited.

According to the present invention, penetration of moisture into a silicon oxide film which allows moisture to relatively easily permeate therethrough around a conductive pad can be inhibited, which makes it possible to inhibit deterioration accompanying the penetration of moisture from the outside. Further, when a penetration inhibiting film is formed not only on a PAD section but also on a circuit and on a scribe, deterioration accompanying the penetration of moisture and hydrogen from the surface of a chip can be further inhibited. Accordingly, moisture resistance can be greatly improved.

The present embodiments are to be considered in all respects as illustrative and no restrictive, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.