Multilayer chip capacitor

The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

CLAIM OF PRIORITY

This application claims the benefit of Korean Patent Application No. 2005-52562 filed on Jun. 17, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayer chip capacitor, more particularly, which is suitably used as a decoupling capacitor of a Micro Processor Unit (MPU) and is capable of reducing Equivalent Series Inductance (ESL).

2. Description of the Related Art

In general, a multilayer chip capacitor (MLCC) includes a plurality of dielectric layers made of ceramics, and internal electrodes interleaved therebetween. The multilayer chip capacitor is small-sized and capable of high capacitance, thus broadly used as capacitive parts of various electronic devices. Especially, the multilayer chip capacitor is extensively used as a decoupling capacitor installed between a semiconductor chip and an electric source in power supply circuits such as a Large Scale Integration (LSI) device.

The capacitor used as the decoupling capacitor needs to have lower ESL to inhibit rapid current change and stabilize the power supply circuits. Higher-frequency and higher-current trend of the MPU has increased such demand. A method for reducing ESL of the multilayer chip capacitor is disclosed in U.S. Pat. No. 5,880,925. The document teaches a method for disposing leads of a positive internal electrode adjacent to those of a negative internal electrode in an interdigitated arrangement. As an example of the conventional technique,FIGS. 1ato1cshow a multilayer chip capacitor in which adjacent leads of first and second internal electrodes having the opposite polarity are disposed alternately.

FIG. 1ais an exploded perspective view illustrating an internal electrode structure of a conventional multilayer chip capacitor.FIG. 1bis a perspective view illustrating the exterior of a conventional multilayer chip capacitor10employing the internal electrode structure ofFIG. 1a.FIG. 1cis a perspective view illustrating a partial internal structure of the multilayer chip capacitor ofFIG. 1b. Dielectric layers11a,11b,12aand12bare not illustrated inFIG. 1c. Referring toFIGS. 1aand1b, first internal electrodes13(13a,13b) are formed on respective dielectric layers11a,11band second internal electrodes14(14a,14b) are formed on respective dielectric layers12aand12b. Four leads15a,15b,16aand16bare formed on the respective electrodes13a,13b,14aand14b. These dielectric layers are stacked alternately to constitute a capacitor body20. To manufacture the multilayer chip capacitor10, the capacitor body20is compressed and fired, and in addition, external terminal electrodes17and18are formed to connect to the respective leads15a,15b,16aand16b.

At this time, the first internal electrodes13aand13bexhibit the same polarity (likewise, the second internal electrodes14aand14bexhibit the same polarity), however the opposite polarity with respect to the second internal electrodes14aand14b. In the adjacent leads15aand16ahaving the opposite polarity, currents flow in opposite directions as indicated with an arrow (see reference sign1a). Therefore, magnetic flux generated by a high-frequency current is partially cancelled, decreasing ESL of the capacitor10.

As shown inFIG. 1c, the vertically adjacent two leads of the first internal electrodes13aand13bextend in parallel (in the same direction) to an external electrode17. Thus, as shown in FIG. b, in the vertically adjacent leads15aand15bhaving the same polarity5aand15b, currents flow in the same direction (indicated with an arrow). In this fashion, currents flowing in the same direction through the leads15a,15bgenerate strong mutual inductance. This mutual inductance renders it hard to reduce ESL sufficiently. To be used as the decoupling capacitor for the MPU, the multilayer chip capacitor needs to exhibit lower ESL.

SUMMARY OF THE INVENTION

The present invention has been made to solve the foregoing problems of the prior art and therefore an object of certain embodiments of the present invention is to provide a multilayer chip capacitor with reduced ESL.

According to an aspect of the invention for realizing the object, there is provided a multilayer chip capacitor comprising: a capacitor body having a plurality of dielectric layers stacked in a thickness direction; a plurality of first and second internal electrodes separated from one another by the dielectric layers within the capacitor body, each of the first internal electrodes opposing each of the second internal electrodes, each of the first and second internal electrodes including at least two leads extending toward any side of the capacitor body; a plurality of external electrodes formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads, wherein vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle, and wherein the leads of the first internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

According to one embodiment of the invention, the vertically adjacent leads of the same polarity extend in different directions at an angle of 45 degree. The vertically adjacent leads of the same polarity may extend in different directions at a right angle.

According to further another embodiment of the invention, the capacitor body includes an upper dummy layer and a lower dummy layer, wherein the first and second internal electrodes are disposed between the upper and lower dummy layers, and wherein the lower dummy layer has a thickness smaller than that of the upper dummy layer. Preferably, the thickness ratio of the lower dummy layer to the upper dummy layer is 0.8 or less. At this time, preferably, the capacitor body has a marking formed on an upper surface thereof, for distinguishing the upper surface from a lower surface of the capacitor. The marking may be formed of e.g., a colored glass.

According to further another embodiment of the invention, at least one of the first and second internal electrodes has at least one slit formed therein. The slit lengthens a current path and consequently prevents excessive reduction in Equivalent Series Resistant (ESR).

According to further another embodiment of the invention, each of the first and second internal electrodes comprises a pair of separated rectangular conductive patterns disposed adjacent to each other, wherein each of the pair of conductive patterns has at least one slit extending from at least one side of the conductive pattern toward a central portion of the conductive pattern so as to change current flow within the conductive pattern, and wherein currents flow in opposite directions in adjacent areas of the pair of conductive patterns. Also, the pair of conductive patterns have the same or opposite polarity.

According to further another embodiment of the invention, currents flowing in the first and second internal electrodes cross each other perpendicularly. In this case, each of the first internal electrodes has a rectangular first conductive pattern with two slits extending from two opposing sides of the first conductive pattern toward a central portion of the first conductive pattern, and each of the second internal electrodes has a rectangular second conductive pattern with two slits extending from two opposing sides of the second conductive pattern toward a central portion of the second conductive pattern, the slits of the second internal electrodes crossing perpendicularly the slits of the first internal electrodes.

Alternatively, each of the first internal electrodes has a pair of first conductive patterns divided by a first slit, and each of the second internal electrodes has a rectangular second conductive pattern with two second slits extending from two opposing sides of the second conductive pattern toward a central portion of the second conductive pattern, the second slits crossing perpendicularly the first slits.

Alternatively, each of the first internal electrodes has a first conductive pattern, and each of the second internal electrodes has a pair of second conductive patterns divided by a slit.

According to the invention, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. Therefore, currents flow through the leads in different directions. This minimizes increase in magnetic flux and prevents mutual inductance from occurring as in the prior art. Consequently, the multilayer chip capacitor has much lower ESL.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the specification, major terms are defined as follows.

In the specification, a “dummy layer” is a region without internal electrodes which substantially contribute to capacitance. On the contrary, an “active layer” is a region with such internal electrodes which substantially contribute to capacitance.

A “lower dummy layer” is a dummy layer disposed between a bottom surface of the capacitor and a lowermost internal electrode. An “upper dummy layer” is a dummy layer disposed on an active layer, by which the upper dummy layer is separated from the lower dummy layer. Further, herein, a “bottom surface” or “underside” of the capacitor is a surface attached to a pad of a substrate when the capacitor is mounted on the substrate. A “top surface” of the capacitor is a surface opposing the bottom surface.

FIGS. 2aand2bare plan views illustrating the configuration of internal electrodes according to an embodiment of the invention.FIG. 3is an exploded perspective view illustrating an internal electrode structure of a multilayer chip capacitor employing the internal electrodes ofFIGS. 2aand2b.FIG. 2aillustrates the configuration of first internal electrodes103formed on dielectric layers101aand101b, andFIG. 2billustrates the configuration of second internal electrodes104formed on dielectric layers102aand102b. The first internal electrodes103and second internal electrodes104exhibit the opposite polarity during operation of the capacitor.

As shown inFIGS. 2a,2band3, vertically adjacent leads having the same polarity extend in different directions at a predetermined angle. That is, a lead105aof a first internal electrode103aextends in a different direction at a predetermined angle from a lead portion105bof a first electrode103b, thus connected to an external electrode of the same polarity (e.g., positive polarity). This allows currents to flow in opposite directions in the vertically adjacent leads105aand105bhaving the same polarity (e.g., negative polarity) (refer to an arrow).

Likewise, a lead106aof a second internal electrode104aextends in a different direction at a predetermined angle from a lead portion106bof a second internal electrode104b, thus connected to an external electrode of the same polarity (e.g., positive polarity). This allows currents to flow in different directions in the vertically adjacent leads106aand106bhaving the same polarity (negative polarity) (refer to an arrow).

In this fashion, currents flowing in different directions in the vertically adjacent leads of the same polarity eliminate or weaken a conventional problem of mutual inductance. Preferably, the leads105aand105bor the leads106aand106b, which are vertically adjacent to each other, are oriented at an angle of 45 degree to 135 degree. For example, in case where the vertically adjacent leads having the same polarity are oriented perpendicular to each other, mutual inductance is rarely generated therebetween.FIG. 4illustrates currents flowing in different directions in the vertically adjacent leads having the same polarity.

FIG. 4is a perspective view illustrating a partial internal structure of a multilayer chip capacitor employing the internal electrode structure ofFIG. 3. For the sake of convenience, dielectric layers are not illustrated inFIG. 4. As shown inFIG. 4, currents flow in different directions in vertically adjacent leads105aand105bhaving the same polarity (e.g., positive polarity) connected to an external electrode107(refer to an arrow). This prevents strong mutual inductance from occurring in the leads105aand105b(seeFIG. 1) as in the prior art. Likewise, vertically adjacent leads106aand106bof second electrodes104aand104bextend in different directions (seeFIG. 3). Consequently, strong mutual inductance does not arise in the leads106aand106b, thereby ensuring effects of ESL reduction. As a result of a simulation experiment, it has been confirmed that in case where the vertically adjacent leads having the same polarity are perpendicular to each other (seeFIG. 3), there is about 12% decrease in ESL compared with a conventional lead structure (seeFIG. 1a).

FIG. 5is a perspective view illustrating an exemplary multilayer chip capacitor employing the internal electrode structure ofFIG. 3. As shown inFIG. 5, the multilayer chip capacitor100includes a capacitor body120having dielectric layers101a,102a,101band102bstacked in a thickness direction. External electrodes107and108are formed on outer surfaces of the capacitor120. Also, first electrodes103and second internal electrodes104are stacked vertically between the dielectric layers inside the capacitor body120. The first electrodes103are coupled to the external electrode107of the same polarity via leads105aand105b, while the second internal electrode104is coupled to the external electrode108of the same polarity via leads106aand106b.

As shown inFIG. 5, in this embodiment of the invention, especially the internal electrodes103and104are disposed in the lower part of the capacitor. This is distinguished from a conventional capacitor10in which internal electrodes13and14are disposed in the central part of the capacitor20(seeFIG. 1b). As stated later, the internal electrodes103and104disposed in the lower part of the capacitor serve to further reduce ESL.

FIG. 6is a vertical cross-sectional view of the multilayer chip capacitor100taken along the line X-X′ inFIG. 5. Referring toFIG. 6, a capacitor body120includes an upper dummy layer152formed on an active layer150and a lower dummy layer151formed under the active layer150. As shown inFIG. 6, the thickness b of the lower dummy layer151is smaller than that of the upper dummy layer152so that the capacitor100has a vertically asymmetrical cross-section. In this fashion, the relatively smaller thickness of the lower dummy layer151reduces ESL, which is caused by currents traveling from a substrate pad (not illustrated), on which the capacitor is mounted, to external electrodes107and108. In addition, the bigger thickness of the upper dummy layer152ensures the capacitor100to be sufficiently thick, thereby preventing deterioration in mechanical strength of the capacitor.

As described earlier, the vertically asymmetrical cross-section of the multilayer chip capacitor100requires distinction between the upper and lower surfaces of the capacitor100when the capacitor100is mounted on a substrate. That is, to decrease ESL properties stemming from currents traveling from the substrate pad to the external electrodes according to the invention, the capacitor100should be mounted on the substrate such that a lower dummy layer151faces the substrate pad without the upper surface of the capacitor100facing downward. The upper and lower surfaces of the capacitor100can be distinguished by a marking130formed on a top surface of the capacitor100(seeFIG. 5). The marking130can be formed of e.g, a colored glass material.

Also, the multilayer chip capacitor according to the invention may employ an internal electrode structure capable of further reducing ESL and controlling ESR not to be extremely low. This internal electrode structure has at least one slit formed therein.

FIGS. 7ato12bare plan views illustrating various embodiments for internal electrodes that can be provided in a multilayer chip capacitor according to the invention.

FIGS. 7aand7bare plan views illustrating internal electrodes of the capacitor according to a first embodiment of the invention. Referring toFIGS. 7aand7b, first internal electrodes203a,203binclude four leads205a,205bconnected to external electrodes, respectively, and second electrodes204a,204binclude four leads206a,206bconnected to external electrodes, respectively. Reference numerals201a,201b,202aand202bdepict dielectric layers. The leads205aand205bof the first internal electrodes203are adjacent to the leads206aand206bof the second internal electrode204aand206bwith the opposite polarity, thereby canceling magnetic flux generated by respective high-frequency currents. In addition, currents flow in opposite directions in the leads205aand205bor the leads206aand206bwhich are adjacent to each other, thereby inhibiting occurrence of strong mutual inductance.

Respective first internal electrodes203aand203bhave separated first conductive patterns203-1aand203-1band second conductive patterns203-2aand203-2bdisposed in parallel on the same plane. The first conductive patterns203-1aand203-1band the second conductive patterns203-2aand203-2bon the same plane have the same polarity, e.g., (+). Also, currents flow in opposite directions in adjacent areas of the first conductive patterns203-1a,203-1band second conductive patterns203-2a,203-2bon the same plane, thereby leading to cancellation of magnetic flux. Likewise, the second internal electrodes204aand204bhave separated first conductive patterns204-1a,204-1band second conductive patterns204-2a,204-2bdisposed adjacent to each other, thereby resulting in cancellation of magnetic flux.

Each of the first conductive patterns and the second conductive patterns has a slit extending from one side of the conductive pattern toward a central portion of the conductive pattern. Therefore, currents flow in opposite directions between adjacent paths in a conductive pattern, thereby canceling magnetic flux within the conductive pattern. This further reduces ESL.

The slit lengthens a current path inside the each conductive pattern, thereby preventing excessive decline in ESR. Also, ESR can be adequately controlled by adjusting the slit length. In this fashion, control of ESR allows a target impedance to be satisfied and a power distribution network to be designed stably.

In the aforesaid embodiment, a conductive pattern has one slit formed therein but at least two slits may be present therein. Additionally, in place of two conductive patterns on the same plane, only a conductive pattern may be formed. The number of the leads formed in the respective internal electrodes may be more than 4.

FIGS. 8aand8bare plan views illustrating the configuration of internal electrodes of a capacitor according to a second embodiment. Referring toFIGS. 8aand8b, first conductive patterns303-1a,303-1b,304-1aand304-1band second conductive patterns303-2a,303-2b,304-2aand304-2bare shown, in which those formed on the same plane (e.g., the conductive patterns303-1aand303-2a) exhibit the opposite polarity. Reference numerals303aand303bdenote first internal electrodes303while reference numerals304aand304bdenote second internal electrodes304. As indicated with an arrow inFIGS. 8aand8b, in this embodiment, currents flow in opposite directions in adjacent areas between the first conductive patterns and second conductive patterns on the same plane, between vertically adjacent leads having the opposite polarity (e.g.,305aand306a) and inside a conductive pattern, thereby cancelling magnetic flux. Further, currents flow in opposite directions through the vertically adjacent leads having the same polarity (e.g.,305aand305b). Moreover, ESR can be adequately controlled through the slit formed in the respective conductive patterns.

According to embodiments of the invention, currents may flow in perpendicular directions between the vertically adjacent first internal electrodes and second internal electrodes.FIGS. 9ato12billustrate examples thereof.

FIGS. 9aand9billustrate the configuration of internal electrodes of a capacitor according to a third embodiment of the invention. Referring toFIGS. 9aand9b, respective first internal electrodes403(403aand403b) and respective second internal electrodes404(404aand404b) have one conductive pattern formed therein. Also, two collinear slits415and425are formed in the first internal electrodes403, and another two collinear slits416and426are formed in the second internal electrodes404. At this time, the slits415and425of the conductive patterns of the first internal electrodes403are perpendicular to the slits416and426of the conductive patterns of the second internal electrodes404. Currents flow in perpendicular directions between the vertically adjacent first internal electrodes403and second internal electrodes404, thereby leading to cancellation of magnetic flux. Moreover, currents flow in opposite directions through vertically adjacent leads having the same polarity such as the leads405aand405bor the leads406aand406b.

FIGS. 10aand10billustrate the configuration of internal electrodes of a capacitor according to a fourth embodiment of the invention. Referring toFIGS. 10aand10b, respective first internal electrodes503(503a,503b) have two conductive patterns503-1aand503-2a(in case of503a) or503-1band503-2b(in case of503b) divided by a slit515. Also, respective second internal electrodes504(504a,504b) have a conductive pattern with two collinear slits516and526. At this time, a slit515of the first internal electrodes503crosses perpendicularly slits516and526of the second internal electrodes504. Currents flow in perpendicular directions between vertically adjacent ones of the first internal electrodes503and the second internal electrodes504so that magnetic flux is cancelled. Furthermore, currents flow in opposite directions through the vertically adjacent leads having the same polarity such as the leads505aand505bor the leads506aand506b.

FIGS. 11aand11bare plan views illustrating the configuration of internal electrodes of a capacitor according to a fifth embodiment of the invention. Referring toFIGS. 11aand11b, respective first internal electrodes603(603a,603b) include a conductive pattern having two slits615and625formed on the same plane. Respective second internal electrodes604(604a,604b) have two conductive patterns divided by a slit616. At this time, slits615and625of the first internal electrode603cross perpendicularly a slit616of the second internal electrode604. Therefore, currents flow in perpendicular directions between the vertically adjacent ones of the first internal electrodes603and second internal electrodes604, resulting in cancellation of magnetic flux. Additionally, currents flow in opposite directions through the vertically adjacent leads having the same polarity such as the leads605aand605bor the leads606aand606b.

FIGS. 12aand12bare plan views illustrating the configuration of internal electrodes of a capacitor according to a sixth embodiment of the invention. Referring toFIGS. 12aand12b, respective first internal electrodes703(703a,703b) have a rectangular conductive pattern with no slit formed therein. Respective second internal electrodes704(704a,704b) have a pair of conductive patterns divided by a slit716. Currents flow in perpendicular directions between the vertically adjacent first internal electrodes703and second internal electrodes704, consequently canceling magnetic flux. Moreover, currents flow in opposite directions through vertically adjacent leads having the same polarity such as the leads705aand705bor the leads706aand706b.

As set forth above, according to preferred embodiments of the invention, adjacent leads having the same polarity extend in different directions at a predetermined angle. This allows currents to flow in different directions through the leads. Eventually, this ensures magnetic flux to be cancelled and prevents mutual inductance from occurring as in the prior art. Therefore, ESL of a multilayer chip capacitor further diminishes. In addition, at least one slit formed in internal electrodes prevents excessive decline in ESR and ensures a proper control of ESR. As a result, a target impedance can be easily met and a power distribution network can be stably designed.