Dual bond pad structure for photonics

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

FIELD OF THE INVENTION

The invention relates to semiconductor structures and, more particularly, to a dual bond pad structure for a wafer with laser die attach and methods of manufacture.

BACKGROUND

Silicon photonics chips are developed for high speed interconnects between dies. Waveguides can be built on silicon on insulator (SOI) wafers and can be integrated with CMOS devices; however, this requires a connection be made between a laser and the waveguide, which is a difficult from both a structural standpoint and a fabrication processing standpoint. For example, the laser die is attached to the wafer using a solder bump, but solder bump height for the laser must be smaller than that of other solder bumps connecting to an interposer. Thus, different solder bump processes must be used for attachment of the laser to the wafer, increasing fabrication time and costs.

SUMMARY

In an aspect of the invention, a method comprises forming a bonding layer on a surface of a substrate. The method further comprises forming solder bumps on the bonding layer. The method further comprises patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further comprises attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further comprises attaching an interposer substrate to the solder bumps formed on the bonding pads.

In an aspect of the invention, a method comprises: forming a bonding layer on a substrate; patterning the bonding layer with two different masks to form bonding pads for connecting an interposer substrate and a laser diode; forming solder bumps on a set of the bonding pads, using one of the masks patterned to have openings corresponding to the set of the bonding pads; attaching the laser diode to another set of the bonding pads by a reflow process of solder connections attached to the laser diode; and reflowing the solder bumps to connect the interposer substrate to the set of the bonding pads after the attaching of the laser diode.

In an aspect of the invention, a structure comprises: a first set of bond pads and a second set of bond pads; solder bumps electrically connected to the first set of bond pads, the solder bumps having a first height; an interposer substrate electrically connected to the solder bumps; and solder connections electrically connected to a laser diode and the second set of bond pads, the solder connections having a second height smaller than the first height and the laser diode being positioned below the interposer substrate.

DETAILED DESCRIPTION

The invention relates to semiconductor structures and, more particularly, to a dual bond pad structure for a wafer with laser die attach and methods of manufacture. More specifically, the present invention provides fabrication processes and resultant structures for bonding both a laser die and an interposer substrate with solder bump processes. Advantageously, the processes of the present invention can minimize the number of masks needed in order to form the bonds pads for both a laser die (diode) and an interposer substrate.

The dual bond pad structure of the present invention can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the bond pad structure of the present invention have been adopted from integrated circuit (IC) technology. For example, the structures of the present invention are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the dual bond pad structure of the present invention uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.

FIG. 1shows a structure and respective fabrication processes in accordance with aspects of the present invention. In embodiments, the structure10includes a silicon on insulator wafer, comprising an oxide or other insulator layer14bonded or otherwise attached to a wafer12(e.g., silicon substrate). In embodiments, the insulator layer14can be a buried oxide layer.

The structure10further includes front end of the line (FEOL) structures and back end of the line (BEOL) structures, generally represented at reference numeral16. In embodiments, the FEOL structures comprise any combination of active and passive devices such as, for example, field effect transistors (FETs) and waveguide structures (with diffusers); although other devices are also contemplated by the present invention. The BEOL structures can comprise any combination of wiring and interconnect structures, for example. The FEOL and BEOL structures can be formed using conventional CMOS technologies comprising lithography, etching and deposition of materials as should be understood by those of skill in the art.

Still referring toFIG. 1, a bond pad layer18is deposited on a surface of an uppermost BEOL layer. For example, the bond pad layer18can be deposited on an oxide film (or other interlevel dielectric material), in electrical connection with wiring layers of the BEOL structures. The bond pad layer18can comprise plural layers deposited using sputtering techniques, as well as other deposition processes such as physical vapor deposition (PVD), etc. In embodiments, the bond pad layer18can comprise, as an example, TiW/Cu/Ni; although other bonding materials are also contemplated by the present invention.

InFIG. 2, a resist20is formed over the bond pad layer18. The resist is then patterned by exposure to energy (light) to form openings20a. A metal plate (portion of subsequently formed bond pad)22is then formed within the openings20a. The metal plate22will act as a bond pad for a laser die (diode). In embodiments, the metal plate22can be a gold pad, formed by an electroplating process. In embodiments, the metal plate22can be other materials such as, for example, Nickel, Copper, Platinum, etc. The resist20can then be removed using conventional processes, e.g., oxygen ashing techniques.

InFIG. 3, a resist20′ is formed on the bond pad layer18and the metal plate22. The resist is then patterned by exposure to energy (light) to form openings20b. A solder bump24is formed within the openings20b, on the bond pad layer18. The solder bump24can be a controlled collapse chip connection (C4) for interconnecting an interposer substrate to the underlying wafer and its circuitry. In embodiments, the solder bump24can be a tin-based alloy or a copper pillar, deposited using electroplating processes. The resist20′ can then be removed using conventional processes, e.g., oxygen ashing techniques.

As shown inFIG. 4, the bond pad layer18can be patterned, to form discrete bond pads18′ and18″. The bond pads18′ and18″ can be electrically isolated from one another. The patterning can be performed using conventional wet etching processes, with selective chemistries to the materials of the bond pad layer18.

FIG. 5shows the connection of a laser die (diode)26to the bond pads18″, formed in the processes described above. In embodiments, the laser diode26includes a solder bump26′ formed on the laser diode devices, which is electrically connected (attached) to the bond pads18″ during a reflow process as should be understood by those of skill on the art. The reflow process can also reflow the solder bump24′. In embodiments, the laser diode26can be aligned with the bond pads18″ using known pick and place processes. As in each of the embodiments, the solder bump26′ will be of a different height than the solder bump24′, preferably of a smaller height, and the bond pads will be discrete bond pads electrically isolated from one another on the surface of the substrate.

InFIG. 6, thereafter, the interposer substrate28is connected to the solder bump24′ through a reflow process as is known to those of skill in the art. In this way, it is now possible to connect both the interposer substrate28and the laser diode26to the wafer using a dual bond pad fabrication process, with different height solder bumps for the interposer substrate28and the laser diode26. As shown in this embodiment and which may be applicable for each of the subsequently described embodiments, the interposer substrate28is positioned above the laser diode26.

FIGS. 7-10show fabrication processes and respective structures in accordance with additional aspects of the present invention. More specifically,FIG. 7shows a structure10′ similar to that ofFIG. 1, which includes a silicon on insulator wafer, comprising an oxide or other insulator layer14bonded or otherwise attached to the wafer12. The structure10further includes front end of the line (FEOL) structures and back end of the line (BEOL) structures, generally represented at reference numeral16. A bond pad layer18is deposited on a surface of an uppermost BEOL layer, as described with respect toFIG. 1such that no further explanation is required.

Still referring toFIG. 7, a masking layer30is patterned on the bond pad layer18. For example, a silicon nitride or SiO2can be deposited on the bond pad layer18using conventional deposition processes, e.g., CVD, PECVD, etc. A resist is formed over the masking layer30, which is then patterned by exposure to energy (light) to form openings. An etching process is then performed through the openings to remove exposed masking layer material, resulting in the pattern of the masking layer30shown inFIG. 7. The resist can then be removed using conventional processes, e.g., oxygen ashing techniques.

InFIG. 8, a resist20is formed over the bond pad layer18and the masking layer30. The resist is then patterned by exposure to energy (light) to form openings20b. A solder bump24is then formed within the openings20b, on the bond pad layer18. The solder bump24can be a controlled collapse chip connection (C4) for interconnecting an interposer substrate to the underlying wafer and its circuitry. In embodiments, the solder bump24can be a tin-based alloy or a copper pillar, deposited using electroplating processes. The resist20can then be removed using conventional processes, e.g., oxygen ashing techniques.

As shown inFIG. 9, the bond pad layer18can be patterned to form discrete bond pads18′,18″. In this embodiment, the bond pads18′ and18″ comprise the bond pad layer18, only. The patterning can be performed using conventional reactive ion etching processes, with selective chemistries to the materials of the bond pad layer18. In embodiments, the masking layer30and the solder bump24will protect the bond pads18′,18″ during this selective etching process. The masking layer30can then be removed using conventional etching processes, known to those of skill in the art.

FIG. 10shows the connection of the laser diode26and interposer substrate28, similar to that already described with respect toFIGS. 5 and 6. Specifically, the laser diode26is attached to the bond pads18″ during a reflow process of the solder bump26′. The reflow process can also reflow the solder bump24′. In embodiments, the laser diode26can be aligned with the bond pads18″ using known pick and place processes. Thereafter, the interposer substrate28is connected to the solder bump24′ through a reflow process as is known to those of skill in the art. In this way, it is now possible to connect both an interposer substrate28and a laser diode26to the wafer using a dual bond pad fabrication process, with different height solder bumps for both the interposer substrate28and the laser diode26.

FIGS. 11-13show fabrication processes and respective structures in accordance with additional aspects of the present invention. More specifically,FIG. 11shows a structure10″ similar to that ofFIG. 1, which includes a silicon on insulator wafer, comprising an oxide or other insulator layer14bonded or otherwise attached to the wafer12. The structure10further includes front end of the line (FEOL) structures and back end of the line (BEOL) structures, generally represented at reference numeral16. A bond pad layer18is deposited on a surface of an uppermost BEOL layer, as described with respect toFIG. 1such that no further explanation is required.

Still referring toFIG. 11, a resist20is formed over the bond pad layer18. The resist is then patterned by exposure to energy (light) to form openings20a′. A metal plate32is then formed in within the openings20a′. The metal plate32will act as a bond pad for both the laser diode and the interposer substrate, as described herein. In embodiments, the metal plate32can be plural layers or a single layer of metal. For example, the metal plate can be a nickel and gold pad, formed by an electroplating process. In embodiments, the metal plate32can be other materials such as, for example, Nickel, Copper, Platinum, etc., or any combinations thereof. The resist20can then be removed using conventional processes, e.g., oxygen ashing techniques.

InFIG. 12, a resist20′ is formed on the bond pad layer18and the metal plate32. The resist is then patterned by exposure to energy (light) to form openings20bexposing the metal plate on an interpose connection side of the structure. A solder bump24is then formed within the openings20b, on the metal plate32. The solder bump24can be a controlled collapse chip connection (C4) for interconnecting an interposer to the underlying wafer and its circuitry. In embodiments, the solder bump24can be a tin-based alloy or a copper pillar, deposited using electroplating processes. The resist20′ can then be removed using conventional processes, e.g., oxygen ashing techniques.

As shown inFIG. 13, the bond pad layer18can be patterned, to form discrete bond pads18′ comprising the bond pad layer18and the metal plate32. The patterning can be performed using conventional reactive ion etching processes, with selective chemistries to the materials of the bond pad layer18. The laser diode26and interposer substrate28can be connected to the bond pads18′″, similar to that already described with respect toFIGS. 5 and 6. Specifically, the laser diode26is attached to the bond pads18′″ during a reflow process of the solder bump26′. The reflow process can also reflow the solder bump24′. In embodiments, the laser diode26can be aligned with the bond pads18′ using known pick and place processes. Thereafter, the interposer substrate28is connected to the solder bump24′ through a reflow process as is known to those of skill in the art. In this way, it is now possible to connect both an interposer substrate28and a laser diode26to the wafer using a dual bond pad fabrication process, with different height solder bumps for both the interposer substrate28and the laser diode26.