Semiconductor memory

A semiconductor storage device includes a memory cell array that stores data and includes a plurality of memory cells two dimensionally arrayed on row and column lines extending along row and column directions, at least one of the memory cells assigned to a redundant memory cell having a larger area size than the other memory cells, the plurality of memory cells and at least one of the redundant memory cells arrayed on at least one of the row lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-170574 filed on Jul. 21, 2009, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment of the present invention discussed herein relates to a semiconductor memory.

BACKGROUND

Semiconductor memories have been known each of which contains alternative redundant memory cells provided in the row direction, in addition to memory cells normally used in system operations. In such a semiconductor memory, a redundant memory cell has a larger area than a normal memory cell. An alternative redundant memory cell and a defective normal memory cell are selected double. In the configuration, since a redundant memory cell has a larger area than a normal memory cell, correct data of the redundant memory cell is output even when the normal memory cell and the redundant memory cell are selected double.

Semiconductor memories with a redundant circuit have also been known which connect a high-sensitivity sense amplifier containing a transistor having a high drivability which is higher than the drivability of a sense amplifier used for a normal memory cell array to a spare cell in a spare row.

When the redundant memory cells are provided in the row direction as described above, the area of the corresponding sense amplifier may be increased with the increase in area of the redundant memory cells. As a result, the areas of the sense amplifiers increase in all columns. This may largely influence on a size of the area of the entire semiconductor memory.

In semiconductor memories with a redundant circuit, high sensitivity sense amplifiers may be provided to all spare cells in a spare row. This largely influence on a size of the entire area of the semiconductor memory.

The followings are a reference documents.[Patent Document 1] Japanese Laid-open Patent Publication No. 06-36592[Patent Document 2] Japanese Laid-open Patent Publication No. 01-213990

SUMMARY

According to an aspect of an embodiment, a semiconductor storage device includes a memory cell array that stores data and includes a plurality of memory cells two dimensionally arrayed on row and column lines extending along row and column directions, at least one of the memory cells assigned to a redundant memory cell having a larger area size than the other memory cells, the plurality of memory cells and at least one of the redundant memory cells arrayed on at least one of the row lines, and a plurality of sense amplifiers that amplify a first output signal from the memory cells, at least one of the sense amplifiers arrayed on the respective column lines, at least one of the sense amplifiers assigned to a redundant sense amplifier that amplifies a second output signal from the redundant memory cell having a larger area size than the other sense amplifiers, the plurality of sense amplifiers and at least one of the redundant sense amplifiers arrayed on at least one of the row lines.

DESCRIPTION OF EMBODIMENTS

With reference to drawings, embodiments will be described in detail below.

FIG. 1illustrates a schematic diagram of a static random access memory (SRAM) macro functioning as a semiconductor memory. The SRAM macro refers to a circuit block functioning as an SRAM.

The SRAM macro inFIG. 1includes memory cell arrays111, local blocks112, data paths113, a timer114and decoders115. In each of the memory cell arrays111, memory cells11(not illustrated inFIG. 1) are arranged two-dimensionally in the row and column directions. As illustrated inFIG. 1, the row direction of the memory cell arrays111is the horizontal direction while the column direction is the vertical direction. Therefore, in the memory cell array111, a series of memory cells11aligned in the horizontal direction are memory cells11in a row while a series of memory cells11aligned in the vertical direction is memory cells11in a column. For convenience of illustration,FIG. 1only illustrates a part of the memory cells11contained in the memory cell arrays111. The other memory cells11are not illustrated inFIG. 1. The lengths in the row direction of the memory cells11are uniformly L, and the memory cells11also have a uniform length in the column direction.

The timer114performs operation control over the entire SRAM macro. The timer114receives control signals and address signals from external circuits of the timer114. In accordance with a control signal and address signal, the timer114may switch between the ON and OFF states of the SRAM macro, adjust the operating timing or designate a memory cell11from or to which data is to be read or written, for example. The decoders115transmit a write enable signal to the corresponding local block112in accordance with a control signal from the timer114. The write enable signal enables reading data from a designated memory cell11or writing data to a designated memory cell11. The data paths113control external input/output to/from the SRAM macro on data read from memory cells11and data to be written to memory cells11. In reading data from memory cells11, the corresponding local block112controls so as to determine a signal acquired from the memory cell array111from the sense amplifier (not illustrated). Then, the corresponding local block112transmits the signal to the corresponding data path113. In writing data to a memory cell11, the corresponding local block112controls so as to transmit the data received from the data path113to the memory cell array111. Then, the corresponding local block112controls so as to write the data to the corresponding memory cell11. In memory cell arrays111, data are written to memory cells11being the target of the data writing on the basis of the signals received from the decoders115and local blocks112. Moreover, data are read from memory cells11being the target of the data writing. In other words, an address signal designating the memory cell11being the target of the data reading or writing is transferred from the timer114to the decoder115. Then, the decoder115decodes the transferred address signal. As a result, the memory cell11is accessed.

The SRAM macro inFIG. 1may include an alternative redundant memory cell (not illustrated) provided for a defective memory cell11in a memory cell array111. The redundant memory cells may be built in the row direction in the memory cell arrays111and be connected via special word lines, for example. In addition, as described above, correct data in the redundant memory cell may be output when the area of the redundant memory cell is larger than normal memory cells and a redundant memory cell and a defective normal memory cell are selected double. In this way, providing redundant memory cells in the row direction of the memory cell array110and increasing the area of the redundant memory cells and thus the area of all corresponding sense amplifiers as described above may largely influence on the area of the semiconductor memory.

In view of the problem, the following embodiments are configured to improve the yield of semiconductor memories, improve the working velocity and provide uniform characteristics in an entire semiconductor memory.

FIG. 2illustrates a schematic plan view of an SRAM macro functioning as a semiconductor memory according to a first embodiment.

The SRAM macro inFIG. 1includes memory cell arrays110, local blocks120, data paths130, a timer140and decoders150. In each of the memory cell arrays110, memory cells11are arranged two-dimensionally in the row and column directions. As illustrated inFIG. 2, the row direction of the memory cell arrays110is the horizontal direction inFIG. 2while the column direction is the vertical direction inFIG. 2. Therefore, in the memory cell arrays110, a series of memory cells11aligned in the horizontal direction are memory cells11in a row while a series of memory cells11aligned in the vertical direction is memory cells11in a column. For convenience of illustration,FIG. 2only illustrates a part of the memory cells11and12contained in the memory cell arrays110, and the other memory cells11and12are not illustrated. The lengths in the row direction of the memory cells11are uniformly L1. Moreover, the lengths in the row direction of the redundant memory cells12, which may be described later, are uniformly L2that is longer than L1. The lengths in the column direction of each of the memory cells11and12are uniform. The areas of the memory cells11are uniformly A1. Moreover, the areas of the redundant memory cells12are uniformly A2that is larger than A1. The size comparison relationship of A1and A2results in that A2>A1because L2>L1.

The timer140performs operation control over the entire SRAM macro. The timer140receives control signals and address signals from external circuits. The timer140may switch between the ON and OFF states of the SRAM macro in accordance with a control signal and address signal. Moreover, the timer140may adjust the operating timing or designate a memory cell11or12from or to which data is to be read or written, for example. The decoders150transmit a write enable signal to the corresponding local block120and memory cell array110in accordance with a control signal from the timer140. The write enable signal enables reading data from designated memory cells11or12or writing data to designated memory cells11or12. The data paths130control external input/output to/from the SRAM macro on data read from memory cells11or12and data to be written to the memory cells11or12. In reading data from the memory cell11or12, the corresponding local block120controls so as to determine a signal acquired from the memory cell array110from the sense amplifier21or22. Then, the corresponding local block120transmits the signal to the corresponding data path130. In writing data to a memory cell11or12, the corresponding local block120controls so as to transmit the data received from the data path130to the corresponding memory cell array110. Then, the corresponding local block120controls so as to write the data to the corresponding memory cell11or12. In the memory cell arrays110, data are written to the memory cells11or12being the target of the data writing, or read from the memory cells11or12being the target of the data reading on the basis of the signals received from the decoder150and local block120. In other words, an address signal designating the memory cell11or12being the target of the data reading or writing is transferred from the timer140to the decoder150. Then, the decoder150decodes the address signal. As a result, the memory cell11or12becomes accessible.

In the SRAM macro according to the first embodiment inFIG. 2, the redundant memory cells12are provided in the column direction in the columns at the right and left ends of the memory cell arrays110. In other words, referring toFIG. 2, the memory cells12in a total of two columns uniformly having a length of L2in the row direction of the memory cell arrays110are uniformly assigned as redundant memory cells12in the memory cell arrays110. As illustrated inFIG. 4, which may be described later, a redundant sense amplifier22and the redundant memory cells12in the same column share bit lines BL and XBL in each of the memory cell arrays110.

In order to improve the operating characteristics of the SRAM macro when a redundant memory cell12is actually used instead of a defective memory cell11, the transistors contained in the redundant memory cells12have a larger size than the transistors contained in the normal memory cells11, as described later. Similarly, the number of transistors contained in each of the redundant sense amplifiers22is larger than the number of transistors contained in each of the normal sense amplifiers21. More specifically, as described later with reference toFIG. 5, in each of the redundant memory cells12, the contained transistors have the same length in the column direction as the length of the normal memory cells11. Moreover, the contained transistors have the longer length only in the row direction. In each of the redundant sense amplifiers22, the contained transistors have the same length in the column direction as the length of the normal sense amplifiers21. Moreover, more transistors are aligned in the row direction. Thus, both of the redundant memory cells12and redundant sense amplifiers22may be longer only in the row direction. This may reduce the influence on the layout in the SRAM macro, in comparison with the case where the redundant memory cells12and redundant sense amplifier22are longer in both of the row direction and column direction.

According to this embodiment, the redundant memory cells12are arranged in the column direction of the memory cell array110as described above. The arrangement of the memory cells12may eliminate the necessity for word lines for the redundant memory cells12, and the necessity for increasing the drive capability of the word lines may hardly be considered.

The sizes of the redundant memory cells12and redundant sense amplifiers22may be increased uniformly in the column direction. Thus, the size of the transistors in the redundant memory cells12and redundant sense amplifier22may be increased at the same time.

The circuit in the SRAM macro is configured such that a redundant memory cell is to be used instead of an actually defective memory cell11, as described laterFIGS. 18 to 22.

Like another embodiment as described later with reference toFIG. 3, the size of the transistors may be increased in the memory cells and sense amplifiers at positions where the required operating characteristics are not acquired in the SRAM macro. As a result, the entire SRAM macro may provide a uniform operating characteristic. The positions where the required operating characteristics are not acquired in the SRAM macro may refer to the farthest column from or the nearest column to the decoders150and the timer140at the center of the SRAM macros according to another embodiment inFIG. 3, for example. The reasons are as follows: The required operating characteristics such as operating timing and margins of the transistors contained in the memory cells11and sense amplifiers21in far and significantly close areas from the center of the SRAM macros are largely different from those of the transistors in the other area than the area. According to a second embodiment inFIG. 3, the difference is addressed by changing the size of the transistors in the memory cells11and sense amplifiers21.

According to the second embodiment inFIG. 3, as described above, the size of transistors even in the memory cells11and sense amplifier21at positions where the required operating characteristics are not acquired in the SRAM macro are increased like those in the redundant memory cells12and redundant sense amplifiers22. InFIG. 3, like numbers refer to like components to those inFIG. 2, and the repetitive description may be omitted. The second embodiment inFIG. 3is different form the first embodiment inFIG. 2as follows. According to the second embodiment inFIG. 3, in the memory cell arrays110in the SRAM macro, the lengths in the row direction of the memory cells13in the neighboring columns to the decoders150and the timer140at the center and the sense amplifiers (not illustrated) in the column are uniformly L3. The length L3is longer than the length L1in the row directions of the normal memory cells11. According to the second embodiment inFIG. 3, the lengths in the row direction of the memory cells13in the farthest columns from the decoders150and the timer140at the center and the sense amplifiers (not illustrated) in the columns are uniformly L3in the memory cell arrays110in the SRAM macro. The expression “the farthest columns from the decoders150and the timer140at the center of the SRAM macro” refers to the columns that are one-column closer to the center than the column of the redundant memory cells12, as illustrated inFIG. 3. The length in the column direction of the memory cells13is equal to the length of the normal memory cells11. The area of each of the memory cells13is A3. Moreover, the area of each of the memory cells13is larger than the area A1of each of the normal memory cells11. The size comparison relationship of A1and A3results in that A3>A1because L3>L1. Each of the memory cells13in the neighboring column to the decoders150and the timer140at the center may sometimes be called an end memory cell13. Moreover, each of the memory cells13in the farthest columns from the decoders150and the timer140at the center of the SRAM macro may sometimes be called as “end memory cell”. Similarly, each of the sense amplifiers (not illustrated) in the same columns as those of the end memory cells13may sometimes be called as “end amplifier”.

As described above, according to the first embodiment inFIG. 2and the second embodiment inFIG. 3, the size of transistors in partial memory cell arrays110and local blocks120contained in an SRAM macro are increased. Moreover, the number of transistors therein is increased. According to the first embodiment inFIG. 2, the sizes of transistors in the redundant memory cells12are uniformly larger than those of the normal memory cells11in each of the memory cell arrays110. The number of parallel transistors in the redundant sense amplifiers22is larger than the number of parallel transistors in the normal sense amplifiers. According to the second embodiment inFIG. 3, the sizes of transistors in the redundant memory cells12and the end memory cells13are uniformly larger than the size of transistors in the normal memory cells11. The number of parallel transistors in the redundant sense amplifiers22and the end amplifiers is higher than the number of parallel transistors in the normal sense amplifiers. As a result, the influence on the layout within the SRAM macro may be suppressed. Moreover, the stability and the sensitivity of the operations in the entire SRAM macro may be increased. In other words, the increased size of transistors may reduce the scatterings in performance between the transistors, as described later with reference toFIG. 12. The increased size of transistors may improve the stability of the operations in the entire SRAM macro as a result. The performance of memory cells increases as the size of transistors increases. The sensitivity increases as the number of parallel transistors in sense amplifiers increases. Thus, when the redundant memory cell12and redundant sense amplifier22are used instead of a defective memory cell11and the corresponding sense amplifier21, the sensitivity of the entire SRAM macro may improve. According to the second embodiment inFIG. 3, uniform operating characteristics may be expected in the SRAM macro. In other word, according to the second embodiment inFIG. 3, the size of transistors in the memory cells having different required operating characteristics is increased so as to address the difference in required operating characteristics as described above. Furthermore, uniform operating characteristics may be expected within the SRAM macro. The increased size of the transistors may minimize the scatterings in characteristic values in manufacturing. Thus, the yield of the applied products may be improved, as described later inFIG. 12.

FIG. 4illustrates the connection of signal lines in the vicinity of the redundant memory cells12and the redundant sense amplifiers22in memory cell arrays110in an SRAM macro of the first embodiment inFIG. 2. As illustrated inFIG. 4, the redundant memory cells12arranged in the column direction share bit lines BL and XBL, like the normal memory cells in the column direction in the other columns. Each row of the memory cell arrays110contains normal memory cells11and a redundant memory cell12. The normal memory cell11and the redundant memory cell12in each row shares word lines WL0, WL2. . . and WLN (also collectively called as word lines “WL”).

According to the second embodiment inFIG. 3, as described above, the end memory cells13are arranged in the column direction in certain columns in the memory cell arrays110. The end memory cells13also share the bit lines BL and XBL. According to the second embodiment, the each row in the memory cell arrays110contains normal memory cells11, redundant memory cells12and end memory cells13. The normal memory cells11, redundant memory cells12and end memory cells13share the word lines WL in the rows.

FIG. 5illustrates the layout in the column having the redundant memory cells12and the vicinity in a memory cell array110.FIG. 6illustrates a simplified layout of each of the memory cells11and12. The end memory cells13in the second embodiment inFIG. 3have the same layout withFIGS. 5 and 6.FIG. 7illustrates a circuit configuration of each of the memory cells11and12. The end memory cells13in the second embodiment inFIG. 3also have the same circuit configuration withFIGS. 5 and 6.

FIG. 8illustrates a simplified layout of a redundant sense amplifier22. The end amplifiers in the second embodiment inFIG. 3have the same layout withFIG. 8.FIG. 9illustrates a circuit configuration of each of normal sense amplifiers21, redundant sense amplifiers22and illustrates another embodiment of the end amplifiers23illustrated inFIG. 3.

FIG. 10Ais a schematic diagram of each of transistors T11to T13and T21to T23contained in a redundant memory cell12. The transistors contained in each of the end memory cells13in the second embodiment inFIG. 3have the same configuration.FIG. 10Bis a schematic diagram of each of transistors T11to T13and T21to T23contained in a normal memory cell11.

FIG. 11Ais a schematic diagram of each of transistors T31, T41, T32, and T42contained in a redundant sense amplifier22. The transistors contained in each of the end amplifiers in the second embodiment inFIG. 3have the same configuration.FIG. 11Bis a schematic diagram of each of transistors T31, T41, T32, and T42contained in a normal sense amplifier21.

As illustrated inFIGS. 5,6,7, and10A and10B, each of the memory cells11and12contains six transistors T11to T13and T21to T23. The same is true in each of the end memory cells13in the second embodiment inFIG. 3. The transistors T11and T21are P-channel metal oxide semiconductor field effect transistors (MOSFETs), and the transistors T12, T22, T13, and T23are N-channel MOSFETs.

A pair of the transistors T11and T12function as an inverter12, as illustrated inFIG. 13A, which will be described later. Similarly, a pair of the transistors T21and T22functions as an inverter IL The transistors T13and T23are turned on by a signal of the word line WL and allow the signal to pass through between the corresponding memory cell11or12and the bit line BL and XBL.

Each of the transistors T11to T13and T21to T23has a gate electrode PG of polysilicon, a drain electrode and source electrode containing a diffusion layer DL. The gate lengths of the gate electrodes PG in the six transistors T11to T13and T21to T23in the memory cells11and12are uniformly11. The same is true in the end memory cells13in the second embodiment inFIG. 3. The gate widths of the gate electrodes PG in the six transistors T11to T13and T21to T23in the normal memory cells11are uniformly w1. On the other hand, the gate widths of the gate electrodes PG in the six transistors T11to T13and T21to T23in the redundant memory cells12are uniformly w2. Here, the size comparison relationship of w1and w2is w2>w1. The same is true in the end memory cells13in the second embodiment inFIG. 3.

In other words, the redundant memory cells12and the end memory cells13in the second embodiment inFIG. 3have transistors T11to T13and T21to T23having a larger gate width than the gate width of the normal memory cells11. As a result, the redundant memory cells12and end memory cells13extends in the row direction, in comparison with the normal memory cells11. The increase in length in the row direction is determined quantitatively to be consistent with the increase in area of the local block120. The increase in area of the local block120is caused by the increase in gate width of each of the transistors T31, T32, T41, and T42in the redundant sense amplifiers22and the end amplifiers in the second embodiment inFIG. 3.

The increase in gate width of the redundant memory cells12as described above in comparison with the gate width of the normal memory cells11allows larger current I2flowing than the current I1in the normal memory cells11when the transistors T11to T13and T21to T23are turned on as illustrated inFIG. 10.

Next, as illustrated inFIGS. 5,8,9, and11A and11B, each of the sense amplifiers21and22contains four transistors T31, T32, T41, and T42. The same is true in the end amplifiers in the second embodiment inFIG. 3. The transistors T31and T41are P-channel MOSFETs, and the transistors T32and T42are N-channel MOSFETs.

Each of the transistors T31and T32functions as an inverter112, as illustrated inFIG. 13B, which may be described later. Similarly, each of the transistors T41and T42functions as an inverter I11. Each of the sense amplifiers21and22has a latch configuration in which the two inverters I11and I12are connected in a loop form.

Each of the transistors T31, T32, T41and T42has a gate electrode PG of polysilicon, and a drain and source containing a diffusion layer DL. The gate lengths of the gate electrodes PG of the four transistors T31, T32, T41, and T42contained in the sense amplifiers21and22are uniformly12. The same is true in the end amplifiers in the second embodiment inFIG. 3.

In the four transistors T31, T41, T32, and T42contained in the normal sense amplifier21, the gate widths of the gate electrodes PG of the N-channel MOSFETs T32and T42are uniformly w11. The gate widths of the gate electrodes PG of the P-channel MOSFETs T31and T41are uniformly w12. In this case, since the P-channel MOSFETs have a worse current characteristic, the gate widths are adjusted to obtain w11>w12for consistency of the current characteristic with the N-channel MOSFETs.

In the four transistors T31, T41, T32, and T42contained in a redundant sense amplifier22, the gate widths of the gate electrodes PG of the N-channel MOSFETs T32and T42are uniformly w21. The gate widths of the gate electrodes PG of the P-channel MOSFETs T31and T41are uniformly w22. For the same reason, w21>w22. The gate width w12=the gate width w22, and the gate width w11=the gate width w21. However, in a redundant sense amplifier22, as illustrated inFIG. 8, the four transistors T31, T41, T32, and T42include two transistors T31-1and T32-2, T41-1and T41-2, T32-1and T32-2, and T42-1and T42-2, which are connected in parallel.

As a result, inFIG. 11A, when the far P-channel MOSFET T31or T41is turned on, currents (not illustrated) flow in parallel from the source electrodes of the far right and left parallel-connected two transistors inFIG. 11Ato the drain electrodes at the center. Similarly, the near N-channel MOSFET T32or T42is turned on ON, the currents I21and I22flow in parallel from the drain electrodes of the parallel-connected two transistors at the near center inFIG. 11Ato both right and left sources. In the normal sense amplifier21inFIG. 11B, when the far P-channel MOSFET T31or T41is turned on, current (not illustrated) flows from the far left source to the right drain inFIG. 11B. Similarly, when the near N-channel MOSFET T32or T42is turned on, the current I11flows from the near right drain electrode to the left source inFIG. 11B.

In a redundant sense amplifier22, as described above, the transistors T31, T41, T32, and T42have the two transistors T31-1and T32-2, T41-1and T41-2, T32-1and T32-2, and T42-1and T42-2, which are connected to each other in parallel. This doubles the current between the source electrodes and the drain electrodes of the parallel connected transistors when the transistors T31, T41, T32, and T42are turned on, compared with the normal sense amplifier21. As a result, the equivalent effect may be acquired to the double gate widths of the transistors T31, T41, T32, and T42. In the redundant sense amplifier22, as described above, the transistors T31, T41, T32, and T42respectively have the two transistors T31-1and T32-2, T41-1and T41-2, T32-1and T32-2, and T42-1and T42-2, which are connected to each other in parallel. In this case, the two transistors which are connected to each other in parallel are arranged in the row direction, as illustrated inFIG. 8. As a result, the length L2in the row direction of the redundant sense amplifier22is longer than the length L1in the row direction of the normal sense amplifier21as illustrated inFIG. 5. Similarly, according to the second embodiment inFIG. 3, the length L3in the row direction of the end amplifier23is longer than the length L1in the row direction of the normal sense amplifier21.

As descried above, the transistors in the redundant memory cells12and redundant sense amplifiers22have a larger gate width than the transistors in the normal memory cells11and normal sense amplifiers21. The configuration of the transistors in the redundant memory cells12and redundant sense amplifiers22provides the equivalent effect to those having the longer gate widths. The same is also true in the end memory cells13and end amplifiers23in the second embodiment inFIG. 3. The increase in gate width of the transistors increases the value of current flowing in the transistors when the transistors are turned on. Thus, the performance and sensitivity of the redundant memory cells12and redundant sense amplifiers22may be improved. The same is also true in the end memory cells13and end amplifiers23in the second embodiment inFIG. 3.

The characteristics of a transistor may strongly depend on a threshold voltage mainly. The threshold voltage varies between transistors due to scatterings in manufacturing. The scattering values strongly depend on the area (L*W) of the transistor. When the magnitude of a scattering value is σVth, the relationship may be as illustrated inFIG. 12, for example. The redundant memory cells12and redundant sense amplifiers22(and the end memory cells13and end amplifiers23in the second embodiment inFIG. 3) have a larger area than the normal memory cells11and normal sense amplifiers21. Thus, the scattering values are relatively small. This may stabilize the characteristics of the redundant memory cells12and redundant sense amplifiers22(and the end memory cells13and end amplifiers23in the second embodiment inFIG. 3). Moreover, the improvement in yield of the SRAM macro may be expected.

FIG. 13Ais a circuit diagram of a memory cell11or12(which is also true in the end memory cells13in the second embodiment inFIG. 3).FIG. 13Bis a circuit diagram of a sense amplifier21or22(which is also true in the end amplifier23).FIGS. 14A and 14Bare circuit diagrams in the vicinity of the memory cell arrays110.FIG. 15is a circuit diagram of the entire SRAM macro.FIG. 16is a timing chart in reading.FIG. 17is a timing chart in writing.

As illustrated inFIG. 13A, the memory cell has a latch configuration in which the inverters I1and I2are connected in a loop form. The input/output terminals RNL and RNR of the latch are connected to the bit lines BL and XBL through the transistors T13and T23for selecting the memory cell.

As illustrated inFIG. 13B, the sense amplifier has a latch configuration in which the inverters I11and I12are connected in a loop form. A source electrode NS of the N-channel MOSFETs included in the inverters I11and I12are connected to a transistor T60that receives a sense-amplifier enable signal SAE.

As illustrated inFIG. 14A, a timer140and decoders150receive a clock signal CLK, an address signal and a write enable signal (collectively called an ADS) from external circuits and outputs a signal of the word line WL, a column select signal CS and the sense-amplifier enable signal SAE.

As illustrated inFIG. 14B, the signal of the word line WL is given to a memory cell array110, and a row of memory cells included in the memory cell array110is thus selected. The column select signal CS and sense-amplifier enable signal SAE are given to the local block120, and a column of the memory cells contained in the memory cell array110is thus selected. The local block120and memory cell arrays110are connected via bit lines BL and XBL. For convenience of description, RBL and RXBL inFIG. 14Brefer to the bit lines BL and XBL of the columns having redundant memory cells12and redundant sense amplifiers22. As illustrated inFIG. 14B, write data WD to be output to a memory cell array110are given through a latch (write data latch) of a data path130to the local block120. The read data RD retrieved from a memory cell array110is once received through the local block120by a latch (read data latch) of the data path130. Then, the read data RD is then output to an external circuit.

As illustrated inFIG. 15, the timer140includes a latch141that receives a write enable signal WE, a row address signal RA and a column address signal CA (collectively called an ADS) from external circuits. The timer140further includes a clock control portion142that externally receives a clock signal CLK from an external circuit and generates internal clock signals CLK1, CLK2, and CLK3.

The decoder150includes a decoder151that decodes a row address signal RA to generate a word line signal WL. Moreover, the decoder150includes a decoder152that decodes a column address signal CA to generate a column select signal CS. The data path130includes the write data latch131that once latches write data WD. Moreover, the data path130includes the read data latch132that once latches read data RD.

As illustrated inFIG. 15, the local block120includes an amplifier121that amplifies write data WD and outputs the write data WD via the bit lines BL and XBL to a memory cell array110. The local block120further includes a bit pre-charger122that pre-charges the corresponding bit lines included in a memory cell array110. The local block120further includes a sense amplifier123(including the sense amplifiers21and22) that amplifies and fixes read data RD. The local block120further includes a multiplexer124that selects read data RD in the column designated by the column select signal CS.

FIG. 15separately illustrates the local blocks120and the data paths130above and below the memory cell array110.FIG. 15is separately illustrated for the purpose of easy understanding of the flow of signals of write data WD and read data RD and the circuit configuration. The real layout within the SRAM macro is as illustrated inFIG. 2or3.

FIG. 16Aillustrates a waveform of the clock signal CLK.FIG. 16Billustrates waveforms of address signals RA and CA.FIG. 16Cillustrates a waveform of a signal in the word line WL.FIG. 16Dillustrates a waveform of the column select signal CS.FIGS. 16E and 16Fillustrate waveforms of signals at internal nodes RNL and RNR in a memory cell, respectively.FIG. 16Gillustrates a signal waveform of the sense-amplifier enable signal SAE.FIGS. 16H and 161illustrate waveforms of signals of the bit lines BL and XBL, respectively.FIG. 163illustrates a signal waveform of read data RD.

In order to read data, a row included in a memory cell array110is selected in accordance with the signal of the word line WL generated on the basis of a row address signal RA. A column included in the memory cell array110is selected in accordance with the column select signal CS generated on the basis of the column address signal CA. From memory cells in the row selected in accordance with the word line WL and the column selected in accordance with the bit lines BL and XBL, read data RD is retrieved through the sense amplifier123in the column. The read data RD is output through the multiplexer124and read data latch132. Here, the sense amplifier123(21or22) latches the signal resulting from the amplification of the signal output from the memory cell11or12to the bit lines BL and XBL to fix the read data RD. In the example inFIGS. 16A to 163, data with a low output signal RD are read, as illustrated inFIG. 163. In this case, as illustrated inFIG. 161, the bit line XBL becomes low. As illustrated inFIG. 163, the read data RD becomes low. The broken waveform inFIG. 161is an example of the waveform when the memory cell is a redundant memory cell12. In the case with a redundant memory cell12, the bit line XBL becomes low earlier than the case with the normal memory cell case (as indicated by the solid waveform GB) as illustrated inFIG. 161. In other words, the redundant memory cells12and redundant sense amplifiers22allow faster reading operation than the normal memory cells11and sense amplifiers21. This is because, as described above, the redundant memory cells12and redundant sense amplifiers22include larger transistors or more parallel transistors than the normal memory cells11and normal sense amplifiers21and may proportionally provide higher performance.

FIG. 17Aillustrates a waveform of the clock signal CLK.FIG. 17Billustrates waveforms of the address signals RA and CA.FIG. 17Cillustrates a waveform of write data WD.FIG. 17Dillustrates a waveform of a signal in the word line WL.FIG. 17Eillustrates a waveform of the column select signal CS.FIG. 17Fillustrates waveforms of signals of the bit lines BL and XBL.FIG. 17Gillustrates waveforms of signals at internal nodes RNL and RNR, respectively, in a memory cell.

In order to write data, a row included in a memory cell array110is selected in accordance with the signal of the word line WL generated on the basis of a row address signal RA. A column included in the memory cell array110is selected in accordance with the column select signal CS generated on the basis of the column address signal CA. To memory cells in the row selected in accordance with the word line WL and the column selected in accordance with the bit lines BL and XBL, write data WD are written through the write data latch131and amplifier121. In the example inFIGS. 17A to 17G, as illustrated inFIG. 17F, the bit line XBL becomes low. Through the transistors T13and T23, the signals at the internal node RNR becomes high level, and the signal at the internal node RNL becomes low level. Then, the write data WD is written. The broken waveform inFIG. 17Gis an example of the waveforms when the memory cell is the redundant memory cell12. In the case with a redundant memory cell12, the change in state from low level to high level in the internal node RNR and the change in state from high level to low level in the internal node RNL are faster than the case with a normal memory cell (as indicated by the solid waveform GRC) as illustrated inFIG. 17G. In other words, the redundant memory cells12allow faster writing operations than the normal memory cells11. This is because, the redundant memory cells12contain larger transistors than the normal memory cells11and may proportionally provide drive capability as described above.

Next, with reference toFIGS. 18 to 20, there may be described a redundant replacement applicable to both of the SRAM macros according to the first embodiment inFIG. 2and the second embodiment inFIG. 3.

According to the redundant replacement, when a defective memory cell11or a defective sense amplifier21exists within an SRAM macro, it is replaced by a redundant memory cell12or redundant sense amplifier22, respectively. As a result, the fraction defective of the SRAM macro may be reduced. As described above, the replacement of the failed (or defective) memory cell11or failed (or defective) sense amplifier21by a redundant memory cell12or redundant sense amplifier22may be simply called a “redundant replacement” hereinafter.

Redundant data RDI for use in implementing the redundant replacement are prestored in a storage (not illustrated) provided outside of an SRAM macro. An SRAM macro product requiring a redundant replacement reads and uses the stored redundant data RDI when the redundant data RDI is used.

FIG. 18illustrates a circuit that reads and decodes redundant data RDI. The circuit is also provided in the data paths130within the SRAM macro. Here, the redundant data RDI itself is acquired in advance through tests on the SRAM macro products before shipment. The circuit includes N latches201, N inverters202, and a decoder203. The redundant data RDI are read in advance from the storage where the redundant data RDI is prestored by a system operation when the SRAM macro product is powered on. The read redundant data RDI are sequentially stored in a series of the latches201on the basis of the pulses of serial latch clock signals LC. The redundant data RDI stored in the latches201in this way are permanently held in the latches201until the SRAM macro is powered off.

After stored in the latches201in this way, the N-bit redundant data RDI are input through the inverters202to the decoder203. Then, the N-bit redundant data RDI are decoded in the decoder203. As a result, two to the nth power redundant select signals Dec_data_in_xx are output from the decoder203. In the output data, 1 bit indicating a defective memory cell only has “1”, and the other bits all have “0”. The “xx” in the redundant select signals Dec_data_in_xx indicates a value of 0, 1, 2, . . . , 35, . . . . The “xx” is also called an “n”.

FIG. 19illustrates an example of a circuit that replaces a memory cell11and sense amplifier21for one bit of a failed (or defective) part by a redundant memory cell12and redundant sense amplifier22on the basis of the redundant select signal Dec_data_in_xx output from the decoder203in data writing. The circuit is also included in the data paths130of the SRAM macro. This example assumes that write data WD, Write_Data_in_xx, for 36 bits are input. In other words, each of the rows of the memory cell array110includes37memory cells11and12for a total of 37 bits including 36 normal memory cells11and one redundant memory cell12. The local block120includes the corresponding 37 sense amplifiers21and22. In other words, the memory cell array110has 37 columns in this example. One column (which is the left end column inFIG. 19) out of the 37 columns is for the redundant memory cells12and redundant sense amplifiers22. In this example, a total of 37 redundant replacement circuits251are provided to each of the 37 columns as illustrated inFIG. 19.

Each of the redundant replacement circuits251has a circuit configuration illustrated inFIG. 20. The redundant replacement circuit251has a NOR element NO1, inverters INV1and INV2, and NAND elements NA1to NA6. In order to perform a redundant replacement, 1 bit of the redundant select signal Dec_data_in_xx (also called Dec_D_xx or Dec_D_n) has a value of “1”, as described above. The redundant replacement circuit251evaluates both data of write data Write_Data_in_xx (also called WD_xx or WD_n) and the redundant select signal Dec_data_in_xx. Then, the redundant replacement circuit251outputs the write data WD_out_xx and XWD_out_xx and a judgment signal Judge_xx. The write data Write_Data_in_xx are sequentially transferred to the left inFIG. 19in the 37 redundant select circuits251as WD_inout_xx and XWD_inout_xx. The redundant select signal Dec_data_in_xx is sequentially transferred as Red_D_xx to the left inFIG. 19in the 37 redundant select circuits251. The memory cells11and sense amplifier21in the column with the judgment signal Judge_xx having a value of “0” are determined as the target of the redundant replacement. Then, the memory cells11and sense amplifier21are replaced by the redundant memory cell12and redundant sense amplifier22. In the memory cell array110, write data WD are written in the row designated by the signal of the word line WL and the columns for 36 bits excluding the bit of the memory cell11replaced as the target of the redundant replacement as described above.

The operations by the redundant replacement circuit251may be described in detail below.

If the redundant replacement circuit251belongs to the column being the target of the replacement, the redundant select signal Dec_D_xx (Dec_D_n inFIG. 20) has a value of “1”. The signal is inverted by the inverter INV1to a value “0”. Then, the signal is output as a judgment signal Judge_n. If the judgment signal having a value of “0” is given to the NAND elements NAX and NAY inFIG. 19, the elements NAX and NAY functioning as gates close their gates. Thus, write data are not output to the memory cells11in the column. Therefore, writing is not performed on the memory cells11in the column to be replaced.

The redundant select signal Red_d_n−1 to be given to the redundant select circuit251has a value of “1” if the column on the right-hand side of the column to which the redundant replacement circuit251belongs is the target of the replacement. The element NO1outputs a value “0” if one of the input redundant select signals Dec_D_n and Red_D_n−1 has a value of “1”. The output value “0” is inverted by the inverter INV2to a value “1” Then, the output value “0” is transferred as Red_D_n to the adjacent left-hand redundant select circuit251.

If the element NO1outputs a value “0” to the elements NA1and NA2, the elements NA1and NA2functioning as gates close their gates and do not output write data WD_in_n and XWD_in_n to the memory cells11of the column. In other words, when one of the column itself and the adjacent right-hand columns is the target of the replacement, write data to be written to the column are not output to the memory cells11in the column. On the other hand, if the redundant select signal Red_D_n−1 having a value of “1” transferred from the adjacent right-hand column is input to the elements NA3and NA4, the elements NA3and NA4functioning as gates open their gates. Thus, the write data WD_in_n−1 and XWD_in_n−1 to be written to the memory cells11in the adjacent right-hand column are output through the NAND elements NA5and NA6instead. In other words, if one of the column itself and the adjacent right-hand columns is the target of the replacement, the write data to be written to the adjacent right-hand column is output to the memory cells11in the column.

On the other hand, if the elements NO1outputs a value “1” to the elements NA1and NA2, the elements NA1and NA2functioning as gates open their gates. Thus, the write data WD_in_n and XWD_in_n to be written to the memory cells11in the column are output through the NAND elements NA5and NA6. In other words, if one of the column itself and the adjacent right-hand columns is not the target of the replacement, the write data to be written to the column is output to the memory cells11in the column. On the other hand, if the redundant select signal Red_D_n−1 transferred from the adjacent right-hand column and having a value of “0” is input to the elements NA3and NA4, the elements NA3and NA4functioning as gates close their gates. Thus, the write data WD_in_n−1 and XWD_in_n−1 to be written to the memory cells11in the adjacent right-hand column are not output. In other words, if one of the column itself and the adjacent right-hand columns is not the target of the replacement, the write data to be written to the adjacent right-hand column are not output to the memory cells11in the column.

In this way, with the redundant select circuit251, if one of the column itself and the adjacent right-hand columns is the target of the replacement in columns of the memory cell arrays110, write data to be written to the column are sequentially output to the memory cells11in the adjacent left-hand column. On the other hand, if one of the column itself and the adjacent right-hand columns is not the target of the replacement, write data to be written to the column is directly output to the memory cells11in the column. As a result, to the right columns of the column to be replaced, the write data WD to be written to the column are directly and normally written to the memory cells11in the columns. On the other hand, to the column to be replaced and the left columns, the write data WD to be written to the adjacent right-hand column are written to the memory cells11in the columns. In this way, data are not written to the memory cells11in the column to be replaced. The data to be written to the memory cells11in the left columns of the column to be replaces are written to the memory cells11in the left columns sequentially shifted by one. Thus, the redundant replacement may be implemented.

FIG. 21illustrates an example of a circuit that performs a redundant replacement on a memory cell11and sense amplifier21for one bit of a failed (or defective) part by a redundant memory cell12and redundant sense amplifier22on the basis of the redundant select signal Dec_data_in_xx output from the decoder203in data reading. The circuit is also included in the data path130of the SRAM macro. In this example, Read_Data_in_xx and XRead_Data_in_xx (also called RD_in_xx and XRD_in_xx, respectively) that are read data RD for 37 bits are input. Each of the rows of the memory cell array110includes one redundant memory cell12and 36 normal memory cells. The local block120includes the corresponding 37 sense amplifiers21and22. In other words, in this example, the memory cell array110has 37 columns. One column (which is the left end column inFIG. 21) out of the 37 columns has the redundant memory cells12and redundant sense amplifiers22. Also in this example, as illustrated inFIG. 21, a total of 37 redundant replacement circuits252are provided to each of the 37 columns.

Each of the redundant replacement circuits252has a circuit configuration illustrated inFIG. 22. The redundant replacement circuit252has a NOR element NO2, inverters INV21and INV22, and NAND elements NA11to NA16. In order to perform a redundant replacement, 1 bit of the redundant select signal Dec_data_in_xx (also called Dec_D_xx) has a value of “1”, as described above. The redundant replacement circuit252evaluates both data of read data Read_Data_in_xx and XRead_Data_in_xx (also called RD_in_xx or XRD_in_xx) and the redundant select signal Dec_data_in_xx. Then, the redundant replacement circuit252outputs the read data RD_out_xx and XWD_out_xx and a judgment signal Judge_xx. The read data Read_Data_in_xx and XRead_Data_in_xx are sequentially transferred to the right inFIG. 21in the 37 redundant select circuits252as RD_inout_xx and XRD_inout_xx. The redundant select signal Dec_data_in_xx is sequentially transferred as Red_D_xx to the left inFIG. 19in the 37 redundant select circuits252.

In the column with the judgment signal Judge_xx having a value of “0”, the memory cells11and sense amplifier21in the column are determined as the target of the redundant replacement. Then, the column is replaced by the column of the redundant memory cell12and redundant sense amplifier22. In the memory cell array110, read data RD are retrieved in intersections of the row designated by the signal of the word line WL and the 36 columns for 36 bits excluding the bit of the column replaced as the target of the redundant replacement as described above.

The operations by the redundant replacement circuit252may be described in detail below. If the column that the redundant replacement circuit252belongs to is the column being the target of the replacement, the redundant select signal Dec_D_xx (Dec_D_n inFIG. 22) has a value of “1”. The signal is inverted by the inverter INV21to a value “0”. Then, the signal is output as a judgment signal Judge_n. The judgment signal having a value of “0” controls the transistor TX. Then, the read signals RD_in_n and XRD_in_n involved in the column become high. Thus, the read data from the memory cells11in the column are not output. Therefore, the data are not retrieved from the memory cells11in the column being the target of the replacement.

The redundant select signal Red_d_n−1 to be given from the adjacent right-hand redundant select circuit252has a value of “1” if the column on the right-hand side of the column to which the redundant replacement circuit252belongs is the target of the replacement. The element NO2outputs a value “0” if one of the input redundant select signals Dec_D_n and Red_D_n−1 has “1”. The output value “0” is inverted by the inverter INV22to a value “1”. Then, the output value is transferred as Red_D_n to the adjacent left-hand redundant select circuit252. If the element NO2outputs a value “0” to the elements NA11and NA12, the elements NA11and NAl2functioning as gates close their gates. Then, the elements NA11and NAl2do not handle the read data RD_in_n and XRD_in_n retrieved from the memory cells11of the column as the output RD_out_xx and XRD_out_xx of the column. In other words, when one of the column itself and the adjacent right-hand columns is the target of the replacement, read data from the memory cells11in the column are not output as the output RD_out_xx and XRD_out_xx. If the redundant select signal Red_D_n−1 having a value of “1” transferred from the adjacent right-hand column is input to the elements NA13and NA14, the elements NA13and NA14functioning as gates open their gates. Thus, the read data RD_in_n+1 and XRD_in_n+1 retrieved from the memory cells11in the immediate left column are output through the NAND elements NA15and NA16instead. In other words, if one of the column itself and the adjacent right-hand columns is the target of the replacement, the read data from the immediate left column is output to the memory cells11in the column.

On the other hand, if the elements NO2outputs a value “1” to the elements NA11and NA12, the elements NA11and NA12functioning as gates open their gates. Thus, the read data RD_in_n and XRD_in_n retrieved from the memory cells11in the column are output through the NAND elements NA15and NA16. In other words, if one of the column itself and the adjacent right-hand columns is not the target of the replacement, the read data from the memory cells11in the column are directly output. If the redundant select signal Red_D_n−1 transferred from the immediate right column and having “0” is input to the elements NA13and NA14, the elements NA13and NA14functioning as gates close their gates. Thus, the read data RD_in_n+1 and XRD_in_n+1 retrieved from the memory cells11in the immediate left column are not output. In other words, if one of the column itself and the adjacent right-hand columns is not the target of the replacement, the read data from the memory cells11in the immediate left column are not output.

In this way, with the redundant select circuit252, if one of the column itself and the adjacent right-hand columns is the target of the replacement in columns of the memory cell arrays110, read data retrieved from the memory cells11in the immediately left column are output. On the other hand, if one of the column itself and the adjacent right-hand columns is not the target of the replacement, read data retrieved from the memory cells11in the column are directly output. As a result, to the right-hand columns of the column to be replaced, the read data retrieved from the memory cells11in the columns are directly and normally output. On the other hand, to the column to be replaced and the left-hand columns, the read data retrieved from the memory cells11in the immediate left columns are output. In this way, read data retrieved from the memory cells11in the column to be replaced are not output. The read retrieved from the memory cells11in the left-hand columns of the column to be replaced are output from the memory cells11in the left columns sequentially shifted by one. Thus, the redundant replacement may be implemented.

According to the second embodiment inFIG. 3, the end memory cells13and end amplifiers23have a larger area than normal memory cells11and normal sense amplifiers21. However, the configurations of the end memory cells and end amplifiers are not limited to the configuration. According to another embodiment, the end memory cells and end amplifiers may have a smaller area than normal memory cells and normal sense amplifiers. According to the embodiment, for example, as illustrated inFIG. 23, the memory cells in the column neighboring to the decoders150may be handled as end memory cells14. The length L4and area A4in the row direction may be smaller than the length L1and area A1of the normal memory cells11. This allows a lower performance of the end memory cells14than the normal memory cells11. Similarly, the sense amplifier (not illustrated) in the column may be handled as an end amplifier, and its length and area in the row direction may be smaller than a normal sense amplifier. This allows a lower sensitivity than a normal sense amplifier.