FERROELECTRIC CAPACITOR WITH INSULATING THIN FILM

Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

BACKGROUND

Devices such as high charge capacity capacitors (e.g., metal-insulator-metal (MIM) capacitors) for backend can be formed as passive circuit elements or transistors (e.g., metal-oxide-semiconductor (MOS) transistors) for frontend as active circuit elements. Passive circuit elements can be used to provide charge storage and sharing, while active circuit elements can be used to enable low voltage and high current power supply. Traditional ferroelectric capacitors have low retention durations. New materials are desired to make capacitors with longer retentions and higher reliability.

The background description provided here is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated here, the material described in this section is not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

DETAILED DESCRIPTION

Hafnium (Hf) and Zirconium (Zr) based ferroelectric (FE) oxide thin films are promising options for next generation of front-end or back-end embedded dynamic random access memory (DRAM), high-density memory, and metal-insulator-metal (MIM) capacitor due to their scalability. However, for Hf and Zr-based ferroelectric oxide, leakage current is pushing oxygen vacancy re-distribution in the ferroelectric oxide layer, which degrade the ferroelectric polarization response after long endurance cycles. Further, for perovskite-based and lead-based ferroelectric oxide, the leakage current is typically high while scaling down the thickness. As such, existing ferroelectric oxide thin film continue to suffer from reliability issues. Hence, it remains challenging to have over 1012endurance cycle at high temperature (e.g., greater than 80 degree Celsius).

In some embodiments, a MIM capacitor is described which comprises a first structure (e.g., first electrode) comprising metal; and a second structure (e.g., second electrode) comprising metal, a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures; and a fourth structure adjacent to the third structure, wherein the fourth structure comprises insulative material. In some embodiments, the insulative material includes an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N. In some embodiments, the insulative material has a thickness in a range of 5 A (Angstrom) to 100 A. In some embodiments, the MIM capacitor includes a fifth structure adjacent to the first structure, wherein the fifth structure comprises a barrier material, which includes Ta and N. In some embodiments, the MIM capacitor includes a sixth structure adjacent to the fifth structure such that the fifth structure is between the first and sixth structures, wherein the sixth structure comprises metal including one or more of: Cu, Al, Au, Co, Ti, N. In some embodiments, the ferroelectric material includes one or more of: Hf or Zr. In some embodiments, the ferroelectric material includes one or more of: Pb, Ti, Zr, Ba, N Si, La, Al, or Hf. In some embodiments, the ferroelectric material has a thickness in a range of 2 nm (nanometer) to 20 nm. In some embodiments, the ferroelectric material is a super lattice of a first material and a second material, wherein the first material includes one of: PbTiO3(PTO), SrZrO3, or FeO3, and wherein the second material includes one of: SrTiO3(STO), BaZrO3, or YTiO3.

By using a low-leakage insulating thin film between the bottom electrode and the ferroelectric oxide, between the top electrode and the ferroelectric oxide, or in the middle of the ferroelectric oxide, leakage current is reduced and reliability of the ferroelectric oxide is improved. This low-leakage insulating thin film results in an efficient way to control the leakage current without changing the property e.g., (memory window and annealing temperature) of the ferroelectric oxide. As such, larger arrays of low power memory bit-cells can be realized. Further, such low-leakage capacitors can also be used as super capacitors to provide power to one or more electronic devices. Other technical effects will be evident from the various embodiments and figures.

The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

The term “scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. In some case, scaling to another process technology node also results into upsizing devices and their layout. The term “scaling” generally also refers to downsizing layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slowing down or speeding up—i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

Here, multiple non-silicon semiconductor material layers may be stacked within a single fin structure. The multiple non-silicon semiconductor material layers may include one or more “P-type” layers that are suitable (e.g., offer higher hole mobility than silicon) for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more “N-type” layers that are suitable (e.g., offer higher electron mobility than silicon) for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors. The multiple non-silicon semiconductor material layers may be fabricated, at least in part, with self-aligned techniques such that a stacked CMOS device may include both a high-mobility N-type and P-type transistor with a footprint of a single finFET.

Here, the term “backend” generally refers to a section of a die which is opposite of a “frontend” and where an IC (integrated circuit) package couples to IC die bumps. For example, high-level metal layers (e.g., metal layer6and above in a ten-metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term “frontend” generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low-level metal layers and corresponding vias that are closer to the active region (e.g., metal layer5and below in the ten-metal stack die example).

FIG.1Aillustrates a schematic of a ferroelectric capacitor (FE-Cap)100. FE-cap100generally comprises two metal layers101and102and ferroelectric material (e.g., FE oxide)103coupled between them. Unlike a normal dielectric based capacitor, a ferroelectric capacitor uses polarization charge to store the memory states, where positive and negative polarization charge indicates state “1” or “0”. Here, metal layer101is a bottom electrode and metal layer102is a top electrode. Ferroelectric material103is typically Hf and Zr-based ferroelectric oxide. However, leakage current is pushing oxygen vacancy re-distribution in the oxide FE oxide, which degrade the polarization response of the FE oxide after long endurance cycles. For perovskite-based and lead-based ferroelectric oxide material103, the leakage current is typically high while scaling down the thickness. As such, existing ferroelectric oxide thin film103continue to suffer from reliability issues. Hence, it is challenging to have over 1012endurance cycle at high temperature (e.g., greater than 80 degree Celsius).

FIG.2Aillustrates plot200showing charge versus voltage function of the FE-Cap, its memory states, and imprint charge. Here, x-axis is voltage (V) and y-axis is charge (C). To switch an FE-cap103, the applied FE-cap voltage VA is be higher than the ferroelectric coercive voltages (which behave as threshold voltages) when driven by a voltage source. For example, VA is greater than V+ for 0 to 1 state switching, and VA is less than V− for 1 to 0 state switching.

FIG.2Billustrates plot220showing hysteresis property of ferroelectric material103, in accordance with some embodiments. Ferroelectric material103exhibits ferroelectricity, which is a property by which a spontaneous electric polarization can be revered by an electric field (e.g., applied voltage). When dielectric materials are polarized, the induced polarization ‘P’ is almost exactly proportional to the applied external electric field E. In such materials, the polarization is a linear function of the applied electric field or voltage. Ferroelectric materials, on the other hand, demonstrate a spontaneous non-zero polarization even when the applied electric field E is zero. As such, the spontaneous polarization can be reversed by an applied electric field in the opposite direction. This results in a hysteresis loop because the polarization of a ferroelectric material is dependent not only on the present electric field but also on its history. The hysteresis loop of plot220shows two stable operating positions for FE103—position221and position222. These two stable positions indicate that the direction of polarization can be switched (e.g., polled) from one to another and this changes the response of polarization to applied AC voltage.

FIG.3Aillustrates a cross-section of a capacitor over bit-line (COB)300with insulative oxide layer above a ferroelectric material, in accordance with some embodiments of the disclosure. In some embodiments, COB300comprises first electrode301(e.g.,101), second electrode302(e.g.,102), ferroelectric material303, metal structure304, first barrier305, first interconnect306, second barrier307, second interconnect308, and insulative material309. Bottom electrode301is coupled to first interconnect306via a barrier layer305while top electrode304is coupled to second interconnect308via metal via304and second barrier307.

In COB configurations, in various embodiments, stacked memory capacitors are fabricated above an access transistor in the back-end interconnect portion of the process flow. In some embodiments, first and second electrodes301and302, respectively, comprise any metallic materials that have lattice constant smaller than 5.0 A. In some embodiments, first and second electrodes301and302, respectively, comprise metal including one or more of: Cu, Al, Au, Co, Ti. In various embodiments, first and second electrodes301and302, respectively, comprise material, which can be deposited by atomic layer deposition (ALD).

In various embodiments, ferroelectric material303is adjacent to a thin insulative layer309. In this example, layer309is above ferroelectric material303such that ferroelectric material303is coupled to top electrode302via layer309while ferroelectric material303is directly coupled to bottom electrode301. In some embodiments, insulative layer309comprises an oxide layer. In various embodiments, any low-leakage amorphous/polycrystalline/single crystalline insulating thin film can be used for layer309. The thickness of layer309along the z-axis ranges from 5 A to 100 A. Example material for layer209include: Al2O3, TiO2, HfO2, SiNx, or SiO2.

In various embodiments, the low-leakage insulating thin film309is inserted between bottom electrode301and ferroelectric oxide303, between top electrode302and ferroelectric oxide303, or in the middle of ferroelectric oxide303to reduce the leakage current. Because of low leakage current passing through Hf and Zr-based oxide layer, there is negligible oxygen vacancies re-distribution, which improve reliability of FE oxide303. For perovskite and lead-based FE oxide303, with inserting a low leakage oxide thin film the thickness of perovskite is scaled down while achieving low leakage current in FE oxide303. This is an efficient way to control the leakage current without changing the ferroelectric property (memory window and annealing temperature) in ferroelectric oxide303.

In some embodiments, ferroelectric material303employed in the ferroelectric capacitor300may include, for example, materials exhibiting ferroelectric behavior at thin dimensions, such as hafnium or zirconium-based oxide (Hf or Zr-based oxide). The thickness of FE material103along the z-axis is in a rage of 2 nm to 20 nm. The ferroelectric material303includes materials such as: hafnium zirconium oxide (HfZrO, also referred to as HZO, which includes hafnium, zirconium, and oxygen), silicon-doped (Si-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and silicon), germanium-doped (Ge-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and germanium), aluminum-doped (Al-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and aluminum), yttrium-doped (Y-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and yttrium), lead zirconate titanate (which is a material that includes lead, zirconium, and titanium), barium zirconate titanate (which is a material that includes barium, zirconium and titanium), and combinations thereof. Some embodiments include hafnium, zirconium, barium, titanium, and/or lead, and combinations thereof for FE material303.

In some embodiments, first and second interconnects306and308include one or more of: Cu, Al, graphene, CNT, Au, Co, or TiN. In some embodiments, barrier layers305and307are provided between the interconnects and electrodes. In various embodiments, these barrier layers are diffusion barriers and may comprise TaN. Barrier layers305and307include one or more of: TaN, graphene, MX2 or M2X, and transition metal dichalcogenides such as MoS2, MoSe2, Cu2S etc. The thickness ‘t’ along the z-axis for barrier layers305and307is 5 A to 40 A.

FIG.3Billustrates cross-section of COB320with insulative oxide layer329below ferroelectric material303, in accordance with some embodiments of the disclosure. Material for layer329is same as the material for layer309. In this embodiment, ferroelectric material309is coupled to bottom electrode301through insulative layer329. Likewise ferroelectric material309is directly coupled to top electrode302.

FIG.3Cillustrates cross-section of COB330with insulative oxide layer329inside ferroelectric material303, in accordance with some embodiments of the disclosure. Material for layer339is same as the material for layer309. In this embodiment, ferroelectric material303has top and bottom sections such that layer339is between the top and bottom sections of ferroelectric303. Here, the top section of layer303is directly coupled to top electrode302while the bottom section of layer303is directly coupled to bottom electrode301. Functionally, the COBs ofFIGS.3B-Coperate same as COB ofFIG.3Aand provide similar technical effect.

FIG.4Aillustrates a cross-section of MIM capacitor400with insulative oxide layer below a ferroelectric material, in accordance with some embodiments of the disclosure. Capacitor400has similar material as COB300. Capacitor400comprises first electrode401(e.g.,101), second electrode402(e.g.,102), ferroelectric material303, metal structure304, first barrier305, first interconnect306, second barrier307, second interconnect308; and insulating material409(same material as material309). The thickness of insulating material409along the z-axis is 5 to 10 Angstroms. Material wise, first and second electrodes401and402, respectively, are similar to materials for first and second electrodes301and302, respectively. Capacitor400can be used in the frontend or the backend. The thickness t1and t2are in a range from 50 A (Angstrom) to 200 A. The thickness t3is of a range from 20 A to 100 A.

FIG.4Billustrates cross-section of MIM capacitor420with insulative oxide layer above a ferroelectric material, in accordance with some embodiments of the disclosure. Material for layer429is same as the material for layer409. In this embodiment, ferroelectric material303is coupled to top electrode402through insulative layer429. Likewise ferroelectric material303is directly coupled to bottom electrode401. The thickness of insulating material429along the z-axis is 5 to 10 Angstroms.

FIG.4Cillustrates a cross-section of MIM capacitor430with insulative oxide layer is between ferroelectric material, in accordance with some embodiments of the disclosure. In this embodiment, ferroelectric material303has top303aand bottom303bsections such that layer439is between the top303aand bottom303bsections of ferroelectric303. Here, the top section303aof layer303is directly coupled to top electrode402while the bottom section303bof layer303is directly coupled to bottom electrode401. The thickness of insulating material439along the z-axis is 5 to 10 Angstroms. Functionally, the MIMs ofFIGS.4B-Coperate same as COB ofFIG.4Aand provide similar technical effect. The thickness t21and t22are in a range of 10 A to 50 A.

FIG.5illustrates a cross-section of an embedded dynamic random access memory (eDRAM) comprising COB of any one ofFIGS.3A-C, in accordance with some embodiments of the disclosure. In some embodiments, transistor500has source region502, drain region504and gate506. Transistor500(e.g., n-type transistor M1) further includes gate contact514disposed above and electrically coupled to gate506, source contact516disposed above and electrically coupled to source region502, and drain contact518disposed above and electrically coupled to drain region504. In various embodiments, COB300,320, or330(or MIM400,420,430) is disposed above transistor500such that electrode308is coupled to via or metal structure508A, and electrode306is coupled to via518.

In some embodiments, gate contact514is directly below COB300/320/330(or MIM400/420/430). In some embodiments, word-line (WL) contact570is disposed onto gate contact514on a second y-z plane behind (into the page) first y-z plane metal522a.

In some embodiments, transistor500associated with substrate501is a metal-oxide-semiconductor field-effect transistor (MOSFET or simply MOS transistors), fabricated on substrate501. In various embodiments of the present disclosure, transistor500may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. In an embodiment, transistor500is a tri-gate transistor.

Here, COB300,320, or330(or MIM400,420,430) stores data. For simplicity purposes,FIG.5is illustrated with reference to COB300, but other capacitor forms with insulating oxide layer can also be used. Data is written into COB300as charge via bit-line (BL)540when access transistor M1is turned on by applying voltage on word-line WL570.

In some embodiments, the underlying substrate501represents a surface used to manufacture integrated circuits. In some embodiments, substrate501includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate501includes other semiconductor materials such as germanium, silicon germanium, or a suitable group III-V or group III-N compound. Substrate501may also include semiconductor materials, metals, dopants, and other materials commonly found in semiconductor substrates.

Gate electrode layer512of transistor500is formed on gate dielectric layer510and may comprise of at least one P-type work-function metal or N-type work-function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some embodiments, the gate electrode layer512may comprise of a stack of two or more metal layers, where one or more metal layers are work-function metal layers and at least one metal layer is a conductive fill layer.

In some embodiments, gate electrode layer512may comprise a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers that form gate electrode layer512may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In some embodiments of the present disclosure, the gate electrode layer512may comprise of a combination of U-shaped structures and planar, non-U-shaped structures. For example, gate electrode layer512may comprise of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of gate dielectric layer510may be formed on opposing sides of the gate stack that bracket the gate stack. Gate dielectric layer510may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In some embodiments, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

In some embodiments, source region502and drain region504are formed within the substrate adjacent to the gate stack of transistor500. Source region502and drain region504are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region502and drain region504. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate source region502and drain region504. In some embodiments, the source region502and drain region504may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in-situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, source region502and drain region504may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. In some embodiments, one or more layers of metal and/or metal alloys may be used to form source region502and drain region504.

In some embodiments, gate contact514and drain contact518of the transistor500are disposed in first dielectric layer520disposed above substrate501. In some embodiments, terminal B is disposed in second dielectric layer522disposed on first dielectric layer520. In some embodiments, third dielectric layer524is disposed on the second dielectric layer522. In some embodiments, fourth dielectric layer526is disposed on third dielectric layer524. In some embodiments, source contact516is partially disposed in fourth dielectric layer526, partially disposed in the third dielectric layer524, partially disposed in second dielectric layer522and partially disposed on the first dielectric layer520. In some embodiments, terminal B contact is disposed in third dielectric layer524. In some embodiments, the conductive interconnect structure such as conductive interconnect structure508disposed in fourth dielectric layer526.

In the illustrated embodiment ofFIG.5, gate contract514is formed in poly region; drain contract518is formed in active, poly, and Metal 0 (M0); electrode306is formed in Via 0-1 layer; COB300is formed in Metal 1 (M1) and Via 1-2; electrode308is formed in Metal 2 (M2), and conductor508is formed in Via 2-3 and Metal (M3). In some embodiments, COB300is formed in the metal 3 (M3) region.

In some embodiments, an n-type transistor M1is formed in the frontend of the die while COB300is located in the backend of the die. In some embodiments, COB300is located in the backend metal layers or via layers for example in Via 3. In some embodiments, the electrical connectivity to the device is obtained in layers M0 and M4 or M1 and M5 or any set of two parallel interconnects. In some embodiments, COB300is formed in metal 2 (M2) and metal 1 (M1) layer region and/or Via 1-2 region.

While the embodiment ofFIG.5is illustrated with reference to a frontend transistor M1, eDRAM cell can also be formed entirely in the backend. In some embodiments, access transistor M1of the eDRAM cell may include a back end transistor that is coupled to ferroelectric capacitor300by sharing its source/drain terminal with one electrode of ferroelectric capacitor300and is used for both READ and WRITE access to ferroelectric capacitor300.

FIG.6illustrates apparatus600, which includes a power plane comprising a super capacitor with insulative oxide layer adjacent to a ferroelectric material, according to some embodiments of the disclosure. In some embodiments, apparatus600includes power plane601, dielectric layer602, layer of memory603, dielectric layer604, ground or sink layer605. Traditional front-end layer606comprises an active region (e.g., a region where a transistor is formed). In some embodiments, power plane601provides capacitance such that current or charge delivered by the capacitance is out-of-plane (e.g., perpendicular to the plane of apparatus600). In some embodiments, by delivering current or charge out-of-plane, high series resistance is avoided in patterned wires (e.g., mesh of wires of power plane601shown as dotted lines).

In some embodiments, power plane601comprises low-leakage insulating thin film309inserted between bottom electrode401and ferroelectric oxide303, between top electrode402and ferroelectric oxide303, or in the middle of ferroelectric oxide303to reduce the leakage current. Because of low leakage current passing through Hf and Zr-based oxide layer, there is negligible oxygen vacancies re-distribution, which improve reliability. For perovskite and lead-based oxide, with inserting a low leakage oxide thin film the thickness of perovskite is scaled down while achieving low leakage current. This is an efficient way to control the leakage current without changing the ferroelectric property (memory window and annealing temperature) in ferroelectric oxide.

In some embodiments, power plane601is disposed “on” or “over” dielectric layer602(e.g., oxide). In some embodiments, a beyond CMOS device layer603(e.g., layer comprising spin layer, magnetic logic, magnetic memory, magnetic junction (e.g., spin valve or magnetic tunneling junction), all spin logic (ASL), etc.). In some embodiments, beyond CMOS device layer603is adjacent to dielectric layer604. In some embodiments, dielectric layer604is adjacent to a ground plane605. In some embodiments, ground plane605is coupled to layer606, which includes traditional fabricating layers (e.g., layers used in a CMOS process). In some embodiments, the length ‘L’ and width ‘W’ of power plane601is 1 centimeter (cm) each resulting in a 100 mm2area plane which is large enough to provide power to a low voltage device beyond CMOS device formed in layer603. WhileFIG.6shows layer601above layer603other orientations are possible. For instance, layer603can be above layer601or beside layer601(e.g., rotating apparatus600by 180 or 90 degrees respectively).

FIG.7illustrates apparatus700showing distributed MIM capacitors with insulative oxide layer adjacent to a ferroelectric material, according to some embodiments of the disclosure. Apparatus700illustrates a mesh of two layers with super capacitor having FE formed between the two layers. In various embodiments, FE material is adjacent to an insulative oxide layer to reduce leakage effects of improve reliance of FE material303. Here the first layer is layer B having parallel lines B0through B7, and the second layer is layer A having parallel lines A0through A7, where lines A0through A7are orthogonal to lines B0through B7. In this example, 8 lines of layers A and B are shown. However, the distributed capacitor of various embodiments can be formed with any number of lines of layers A and B.

In some embodiments, the first layer B with lines B0through B7is coupled to a power supply, thus forming power supply lines. In some embodiments, the second layer A with lines A0through A7is coupled to a ground supply, thus forming ground supply lines. The array of super capacitors with FE303which is adjacent to an insulating oxide layer (e.g.,309) here forms a distributed network of parallel capacitors, in accordance with some embodiments. In some embodiments, super capacitors C00through C77(not all are labeled for sake of brevity) are formed between the regions of lines A0through A7and B0through B7. In some embodiments, the super capacitors comprise one of capacitors300/320/330or400/420/430(shown as a cross-section).

In some embodiments, the array of super capacitors C00through C77is used for charge storage and switching in backend of a computing chip. In some embodiments, the array of super capacitors C00through C77is integrated with low voltage logic and is used to provide power to it. In some embodiments, the array of super capacitors C00through C77provides power to frontend transistors (e.g., CMOS transistors).

FIGS.8A-Billustrate apparatuses800and850and for switch mode power supply during charging and discharging modes, respectively, according to some embodiments of the disclosure.FIG.8Adepicts a charge mode configuration in a SMPS (switch mode power supply) andFIG.8Bdepicts a discharge mode configuration in the power supply, in accordance with some embodiments. Elements840,841, and842represent capacitance (e.g., parasitic capacitance) between layers within the chip, in accordance with some embodiments. In some embodiments, capacitors810,811,812correspond FE capacitors C00, C01, C02, etc., which have FE material adjacent to an insulating oxide layer, in accordance with some embodiments. In some embodiments, capacitors840,841,842and onwards are coupled to power and ground lines of a beyond CMOS device801(e.g., spin logic operating on a 10 mV supply). In some embodiments, during the SMPS charging mode, capacitors810,811,812are charged in series. As shown in configuration850, switching mechanisms (e.g., circuits) may be configured to convert the SMPS from a series to a parallel connection when switching from charge mode to discharge mode, in which capacitors810,811,812are discharged in parallel.

The series configured charge mode provides for large voltage division and current multiplication, in accordance with some embodiments. For example, a 1 V power supply applied to charge configuration800may be divided down over 100 capacitors to provide 10 mV per capacitor. In place of the charging current of, for example, 1 A (Amperes), each of the capacitors supplies a discharge current of 1 A to create the total current of 100 A over the chip. In some embodiments, the parallel configured discharge mode enables ultra-low series resistance as power need not traverse extended paths and instead deploys out-of-plane directly to a logic device.

In some embodiments, the SMPS includes a charging cycle at, for example, 1 KHz-10 MHz where a bank of FE capacitors is coupled in series to charge to 1 V (FIG.8A). The FE capacitors comprises low-leakage insulating thin film309inserted between bottom electrode401and ferroelectric oxide303, between top electrode402and ferroelectric oxide303, or in the middle of ferroelectric oxide303to reduce the leakage current. Because of low leakage current passing through Hf and Zr-based oxide layer, there is negligible oxygen vacancies re-distribution, which improve reliability. For perovskite and lead-based oxide, with inserting a low leakage oxide thin film the thickness of perovskite is scaled down while achieving low leakage current. This is an efficient way to control the leakage current without changing the ferroelectric property (memory window and annealing temperature) in ferroelectric oxide.

In some embodiments, the SMPS includes a discharge cycle at 1 KHz-10 MHz where the capacitors (e.g., each at 10 mV) are discharged in parallel into the device layer. In some embodiments, in order to ensure an uninterrupted power supply, a part of the on-chip capacitors (e.g., C00through C07) can be in charge mode, while a part of the capacitors (e.g., C10through C17) can be in discharge mode. Then the SMPS is switched, and charge and discharge modes are reversed.FIGS.8A-Billustrate how an entire SMPS is located on a chip along with spin logic devices, spintronic memory, and the like. While the SMPS may cooperate with a battery located off chip, the SMPS itself is located on the chip, in accordance with some embodiments.

FIG.9illustrates a 4-terminal controlled switch900for the power plane, according to some embodiments of the disclosure. In some embodiments, the 4-terminal controlled switch comprises p-type transistor MP1, n-type transistors MN1and MN2, and FE capacitors C1and C2coupled together as shown. In some embodiments, the gate terminals of transistors MP1, MN1, and MN2are coupled to node901, which provides a switching signal. In some embodiments, capacitors C1and C2are according to any one of capacitors300/320/330or400/420/430.

In some examples, the switching element is part of a SMPS embodiment for converting a 1V, 1 A supply to a 10 mV, 100 A supply. In some embodiments, transistor MP1is operative during a clock phase and transistors MN2and MN2are operative in an opposite SMPS clock phase.

Some embodiments include the following capacitance per unit area characteristics to enable a low resistance, low power supply that is operative with beyond CMOS devices (e.g., spin logic devices).

In some embodiments, the total charge (Q) required for a chip having an area A=1 mm2with a Pd=1 W/cm2power requirement at the spin logic voltage VSL=0.01 V and SMPS switching frequency is 10 MHz is:

where Tsmpsis the period (inverse frequency) of SMPS switching.

The effective capacitance per unit area at a voltage 0.01 V is thus:

The required effective capacitance value corresponds to normal capacitance with 10 nm dielectric thickness. An embodiment has a constraint on the dielectric constant, at a dielectric thickness d=10 nm, of:

This is one option for a dielectric constant. A higher dielectric constant will help relax the requirement for the thickness of the layers, requirement on the area occupied by capacitors, or increase the performance of the power plane.

Some embodiments include a fill factor for the power plane at a given dielectric constant, where the fill factor of the power plane is the total area of the power plane used for the MIM capacitors divided by the chip area. Fill factor for the power plane is given by:

Hence, the fill factors of the supply plane will leave sufficient space for reuse of the metal layer for regular routing or for via dropping.

Some embodiments include a series resistance whereby series resistance seen by the logic device layer is the source resistance of the SMPS at the output. At a fill factor of 10% the series resistance of the via layer per unit chip area is (via resistivity is assumed 10 times copper resistivity):

where L is length of the via

The effective series resistance voltage drop over the vias is 0.16 nV (which is small compared to the 10 mV supply). At a voltage drop of Vdrop=1 mV, the required total conductance of the switches per unit chip area:

The power switching transistors (e.g., transistors MP1, MN1, and MN2) are operated at a low resistance region, below the supply voltage Vdd, where the resistance per unit length of the transistors is less than:

where Idsatis taken from the 2011 edition of the International Technology Roadmap for Semiconductors.

In some embodiments, the total conductance of Gtotalrequires a gate length per unit area of the chip to be:

Some embodiments may use a total power transistor gate length of 21 meters to power a 100 mm2chip at 1 W/cm2power budget.

In an embodiment the fraction of area of the power transistors (e.g., transistors MP1, MN1, and MN2) is:

Hence, the area overhead for power gating and conversion is less than 3%.

In an embodiment, power conversion losses in the SMPS (output delivered power of the SMPS as a fraction of the input power) is as follows:

Or in other words:

and power efficiency of the SMPS is given by:

Thus, an embodiment has a power conversion efficiency of 85.88% with an aerial overhead of 2.5% (for a high-k dielectric), on state drop of 1 mV, area fill factor of the power plane of 25%, and current density of 400 A/cm2. The series resistance drop is less than 1 nV, thereby avoiding the interconnect losses as outlined in a traditional voltage network.

FIG.10illustrates flowchart1000of a method for forming an FE capacitor with insulative oxide layer adjacent to a ferroelectric material, in accordance with some embodiments of the disclosure, in accordance with some embodiments. While the following blocks (or process operations) in the flowchart are arranged in a certain order, the order can be changed. In some embodiments, some blocks can be executed in parallel.

At block1001, a first structure (e.g.,301) is formed comprising metal. At block1002, a second structure (e.g.,302) is formed comprising metal. At block1003, a third structure (e.g.,303) is formed comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures. In some embodiments, the ferroelectric material includes one or more of: Hf or Zr. In some embodiments, the ferroelectric material includes one or more of: Pb, Ti, Zr, Ba, N Si, La, Al, or Hf. In some embodiments, the ferroelectric material has a thickness in a range of 2 nm to 20 nm. In some embodiments, the ferroelectric material is a super lattice of a first material and a second material, wherein the first material includes one of: PbTiO3(PTO), SrZrO3, or FeO3, and wherein the second material includes one of: SrTiO3(STO), BaZrO3, or YTiO3.

At block1004, a fourth structure is formed adjacent to the third structure, wherein the fourth structure comprises insulative material. In some embodiments, the insulative material includes an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N. In some embodiments, the insulative material has a thickness in a range of 5 A to 100 A. At block1005, a fifth structure is formed adjacent to the first structure, wherein the fifth structure comprises a barrier material, which includes Ta and N. In some embodiments, the method comprises forming a sixth structure adjacent to the fifth structure such that the fifth structure is between the first and sixth structures, wherein the sixth structure comprises metal including one or more of: Cu, Al, Au, Co, Ti, N.

FIG.11illustrates a smart device, a computer system, or a SoC (System-on-Chip) including FE capacitor with insulative oxide layer adjacent to a ferroelectric material, in accordance with some embodiments of the disclosure.FIG.11illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device1700represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device1700.

In some embodiments, computing device1700includes first processor1710with FE capacitor with insulative oxide layer adjacent to a ferroelectric material (e.g., capacitor300/320/330or400/420/430), according to some embodiments discussed. Other blocks of the computing device1700may also include FE capacitor with insulative oxide layer adjacent to a ferroelectric material (e.g., capacitor300/320/300or400/420/430), according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within1770such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In some embodiments, processor1710can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor1710include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device1700to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, computing device1700includes audio subsystem1720, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device1700, or connected to the computing device1700. In one embodiment, a user interacts with the computing device1700by providing audio commands that are received and processed by processor1710.

In some embodiments, computing device1700comprises display subsystem1730. Display subsystem1730represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device1700. Display subsystem1730includes display interface1732, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface1732includes logic separate from processor1710to perform at least some processing related to the display. In one embodiment, display subsystem1730includes a touch screen (or touch pad) device that provides both output and input to a user.

In some embodiments, computing device1700comprises I/O controller1740. I/O controller1740represents hardware devices and software components related to interaction with a user. I/O controller1740is operable to manage hardware that is part of audio subsystem1720and/or display subsystem1730. Additionally, I/O controller1740illustrates a connection point for additional devices that connect to computing device1700through which a user might interact with the system. For example, devices that can be attached to the computing device1700might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller1740can interact with audio subsystem1720and/or display subsystem1730. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device1700. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem1730includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller1740. There can also be additional buttons or switches on the computing device1700to provide I/O functions managed by I/O controller1740.

In some embodiments, computing device1700includes power management1750that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem1760includes memory devices for storing information in computing device1700. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem1760can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device1700.

In some embodiments, computing device1700comprises connectivity1770. Connectivity1770includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device1700to communicate with external devices. The computing device1700could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity1770can include multiple different types of connectivity. To generalize, the computing device1700is illustrated with cellular connectivity1772and wireless connectivity1774. Cellular connectivity1772refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)1774refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

In some embodiments, computing device1700comprises peripheral connections1780. Peripheral connections1780include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device1700could both be a peripheral device (“to”1782) to other computing devices, as well as have peripheral devices (“from”1784) connected to it. The computing device1700commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device1700. Additionally, a docking connector can allow computing device1700to connect to certain peripherals that allow the computing device1700to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device1700can make peripheral connections1780via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

Following examples illustrates various embodiments. The examples can be combined in any suitable manner.

Example 1: An apparatus comprising: a first structure comprising metal; a second structure comprising metal; a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures; and a fourth structure adjacent to the third structure, wherein the fourth structure comprises insulative material.

Example 2: The apparatus of example 1, wherein the insulative material includes an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N.

Example 3: The apparatus of example 1, wherein the insulative material has a thickness in a range of 5 A to 100 A.

Example 4: The apparatus of example 1 comprising a fifth structure adjacent to the first structure, wherein the fifth structure comprises a barrier material, which includes Ta and N.

Example 5: The apparatus of example 1 comprising a sixth structure adjacent to the fifth structure such that the fifth structure is between the first and sixth structures, wherein the sixth structure comprises metal including one or more of: Cu, Al, graphene, carbon nanotube, Au, Co, Ti, or N.

Example 6: The apparatus of example 1, wherein the ferroelectric material includes one or more of: Hf or Zr.

Example 7: The apparatus of example 1, wherein the ferroelectric material includes one or more of: Pb, Ti, Zr, Ba, N Si, La, Al, or Hf.

Example 8: The apparatus of example 1, wherein the ferroelectric material has a thickness in a range of 2 nm to 20 nm.

Example 9: The apparatus of example 1, wherein the ferroelectric material is a super lattice of a first material and a second material, wherein the first material includes one of: PbTiO3(PTO), SrZrO3, or FeO3, and wherein the second material includes one of: SrTiO3(STO), BaZrO3, or YTiO3.

Example 10: An apparatus comprising: a bit-line; a word-line; a transistor coupled to the bit-line and the word-line; and a capacitor over the bit-line (COB), wherein the COB is coupled to ground and the transistor, wherein the COB comprises: a first electrode comprising metal; a second electrode comprising metal; a first structure comprising ferroelectric material, wherein the first structure is between and adjacent to the first and second electrodes; and a second structure adjacent to the first structure, wherein the second structure comprises insulative material.

Example 11: The apparatus of example 10, wherein the insulative material includes an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N.

Example 12: The apparatus of example 10, wherein the insulative material has a thickness in a range of 5 A to 100 A.

Example 13: The apparatus of example 10 comprising: a first barrier structure adjacent to the first electrode, wherein the second barrier structure comprises Ta and N; and a second barrier structure adjacent to the second electrode, wherein the second barrier structure comprises Ta and N.

Example 14: The apparatus of example 10 comprising a first interconnect adjacent to the first barrier; and a second interconnect adjacent to the second barrier.

Example 15: The apparatus of example 10, wherein the first and second interconnect comprise metal including one or more of: Cu, Al, Au, Co, or Ti.

Example 16: The apparatus of example 10, wherein the ferroelectric material includes one or more of: Hf or Zr.

Example 17: A system comprising: a processor; and a memory coupled to the processor, wherein the memory includes: a ferroelectric material between two electrodes; an insulative material adjacent to the ferroelectric material; and a wireless interface to allow the processor to communicate with another device.

Example 18: The system of example 17, wherein the two electrodes comprise metal including one or more of: Cu, Al, Co, or Ti.

Example 19: The system of example 17 wherein the insulative material includes an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N, and wherein the insulative material has a thickness in a range of 5 A to 100 A.

Example 20: The system of example 17, wherein the ferroelectric material includes oxides of one or more of: Hf or Zr.