Method of demodulating a signal packet, a communication system and a lighting device

A method of demodulating a signal packet includes steps of: determining whether a pulse width of each of pulses of one of bits of the signal packet is associated with bit 0 or bit 1; updating first counting data associated with a number of the pulses that define bit 0, and determining whether the first counting data is greater than a first threshold value; deciding that said one of the bits of the signal packet is a bit 0; updating second counting data associated with a number of the pulses that define bit 1, and determining whether the second counting data is greater than the second threshold value; deciding that said one of the bits of the signal packet is a bit 1.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese Application No. 104128832, filed on Sep. 1, 2015.

FIELD

The disclosure relates to a communication method, a communication system and a lighting device, more particularly to a method of demodulating a signal packet, a communication system and a lighting device.

BACKGROUND

With the advance of technology, monitoring and control of a lighting device have become an important issue. Conventional light control and management are merely associated with controlling on and off of a lighting device. Operational parameters, such as voltage, current, circuit quality and failure rate of circuits of each lighting device are not made available for monitoring in real time. In the past, a light control system is usually constructed in a wired manner, which costs significantly and is difficult in maintenance. Even if a light control signal is transmitted in a wireless manner, relay stations are required for long-distance transmission of the light control signal. In addition, since the radio spectrum resources are limited, it is difficult to monitor and control all street lights which are widely spread.

In order to overcome this issue, a technology of Power Line Communication (PLC) has been developed. Considering that almost each corner of a house or an office building is provided with an alternating current (AC) power socket, more complicated communication of a control signal, such as a signal to change a pattern or a color of light emitted by a lighting instrument, may be achieved without the need to construct a new transmission line.

A communication interface adopted in a current light control system is a Digital Addressable Lighting Interface (DALI) interface. However, the DALI interface requires additional installation of signal lines which incurs further cost and complexity in constructing the light control system. If a power line, instead of the signal lines, is used to transmit a digital control signal and electric power, a pulse period or a pulse width of the digital control signal may be influenced by noise in the power line so that the digital control signal may not be demodulated correctly.

SUMMARY

Therefore, an object of the disclosure is to provide a method of demodulating a signal packet, a communication system and a lighting device that can alleviate at least one of the drawbacks of the prior art.

According to a first aspect of the disclosure, the method of demodulating a signal packet is to be implemented by a controller. The signal packet includes a plurality of bits each of which is represented by a plurality of pulses. The controller stores in advance a first pulse width associated with the pulses of the signal packet that define bit0, a first threshold value associated with bit0, a second pulse width associated with the pulses of the signal packet that define bit1, and a second threshold value associated with bit1. The method includes steps of:

after receiving the signal packet, determining, by the controller, whether a pulse width of each of the pulses of one of the bits of the signal packet is associated with bit0or bit1according to the first pulse width and the second pulse width;

when it is determined by the controller that the pulse width is associated with bit0, by the controller, updating first counting data associated with a number of the pulses that define bit0, and determining whether the first counting data is greater than the first threshold value;

when it is determined by the controller that the first counting data is greater than the first threshold value, deciding, by the controller, that said one of the bits of the signal packet is a bit0;

when it is determined by the controller that the pulse width is associated with bit1, by the controller, updating second counting data associated with a number of the pulses that define bit1, and determining whether the second counting data is greater than the second threshold value;

when it is determined by the controller that the second counting data is greater than the second threshold value, deciding, by the controller, that said one of the bits of the signal packet is a bit1.

According to a second aspect of the disclosure, the communication system is configured for transmission of a light control signal. The system includes a control device and a lighting device. The control device is configured to transmit a command packet and receive a return packet. The command packet and the return packet serve as the light control signal. The lighting device includes a light control protocol interface and a first controller connected electrically to the light control protocol interface. The first controller is configured to receive the command packet, to correct the command packet thus received, and to transmit the command packet thus corrected to the light control protocol interface. The light control protocol interface is configured to transmit a return command which is associated with lighting condition of the lighting unit to the first controller.

The first controller includes a digital pulse output unit, a digital pulse control unit connected electrically to the digital pulse output unit, and a digital pulse demodulation unit receiving the command packet. The digital pulse output unit receives the return command and outputs a plurality of digital pulses. The digital pulse control unit generates the return packet according to the plurality of digital pulses and transmits the return packet to the control device. The digital pulse demodulation unit demodulates the command packet so as to correct the command packet and transmits the command packet thus corrected to the light control protocol interface.

According to a third aspect of the disclosure, the lighting device includes a light control protocol interface, a controller and a lighting unit. The controller is connected electrically to the light control protocol interface and includes a digital pulse demodulation unit. The digital pulse demodulation unit receives a command packet, demodulates the command packet so as to correct the command packet and transmits the command packet thus corrected to the light control protocol interface. The lighting unit is connected to the light control protocol unit and is controlled by the light control protocol interface according to the command packet thus corrected.

An effect of this disclosure resides in that by virtue of the error correction capability of the digital pulse demodulation unit, adverse influence on the pulse period or the pulse width resulting from noise or parameter deviation of circuit elements in the power line may be prevented.

DETAILED DESCRIPTION

Referring toFIG. 1, a first embodiment of a method of demodulating a signal packet according to the disclosure is to be implemented by a communication system for transmission of a light control signal. The light control signal serves as the signal packet to be demodulated.

Referring toFIGS. 1 and 2, the communication system for transmission of the light control signal includes at least one lighting device2and a control device3. In the first embodiment, the at least one lighting device2and the control device3are connected in the manner of Digital Addressable Lighting Interface (DALI) buses. Multiple lighting devices2are illustrated inFIG. 1for explanatory purposes.

Each of the lighting devices2includes a light control protocol interface21, a first controller22connected electrically to the light control protocol interface21, and a lighting unit23connected electrically to the light control protocol interface21.

The light control protocol interface21transmits a return command, which is associated with lighting condition of the lighting unit23under control of the light control protocol interface21, to the first controller22. On the other hand, a command packet is corrected by the first controller22after receipt thereof, and is subsequently transmitted to the light control protocol interface21. Specifically, the control device3combines information associated with the lighting unit23desired to be controlled and action desired to be performed by the lighting unit23to generate the command packet, also known as a forward frame. Distortion may be found in the command packet after the command packet is transmitted via a power line transmission medium. When each of the lighting devices2receives the command packet, the first controller22of the lighting device2is configured to correct the command packet if it is distorted. In the first embodiment, the light control protocol interface21is a DALI interface.

The first controller22includes a digital pulse output unit221, a digital pulse control unit222connected electrically to the digital pulse output unit221, and a digital pulse demodulation unit223receiving and demodulating the command packet. The digital pulse output unit221receives the return command and outputs a plurality of digital pulses according to the return command. The digital pulse control unit222generates a return packet according to the plurality of digital pulses and transmits the return packet to the control device3. The return packet is also known as a backward frame. Information contained in the return packet includes the lighting condition of the lighting unit23. The digital pulse demodulation unit223includes a bit counter224configured to count a number of bits of the command packet, a first pulse counter225configured to count a number of pulses which have pulse widths belonging to bit0, and a second pulse counter226configured to count a number of pulses which have pulse widths belonging to bit1. The digital pulse demodulation unit223is configured to determine whether a pulse contained in the command packet is the last pulse, and after determining whether a pulse width of each of pulses of one bit of the command packet belongs to bit0or bit1, to determine whether a number of the pulses of the bit is greater than a threshold value. The digital pulse demodulation unit223demodulates the command packet so as to correct errors in the command packet, and transmits the command packet thus corrected to the light control protocol interface21. In a condition that the command packet is a query packet, the light control protocol interface21transmits the return command to the digital pulse output unit221.

The control device3includes a second controller31which transmits the command packet to at least one of the lighting devices2, and demodulates the return packet received from the first controller22of one of the lighting devices2via the power line transmission medium. It should be noted that the second controller31includes components similar to those of the first controller22. Since operations of the components of the second controller31upon receipt of the return packet are similar to the operations performed by the digital pulse output unit221, the digital pulse control unit222and the digital pulse demodulation unit223of the first controller22upon receipt of the command packet, detailed descriptions of the same are omitted herein for the sake of brevity. The control device3further includes a light control protocol interface (not shown) similar to the light control protocol interface21of each of the lighting devices2.

Referring toFIGS. 2 and 3, both the return packet outputted by the first controller22of one of the lighting devices2and the command packet outputted by the second controller31of the control device3are transmitted via the power line transmission medium. Referring toFIG. 4, the command packet includes a preamble, a DALI address, a DALI command and an End Of Frame (EOF). Referring toFIG. 5, the return packet also includes a preamble, a DALI command and an End Of Frame (EOF). In other words, both the return packet and the command packet are provided with the preamble and the EOF. When one of the lighting devices2and the control device3receives the signal packet (i.e., the command packet or the return packet) transmitted via the power line transmission medium, a corresponding one of the first controller22of the lighting device2and the second controller31of the control device3corrects the signal packet, and transmits the signal packet thus corrected to the corresponding light control protocol interface. Subsequently, the light control protocol interface of each of the control device3and the lighting device2determines whether the signal packet is a return packet or a command packet based on the number of bits of the signal packet. When it is determined that the signal packet is a command packet, the DALI address and the DALI command of the command packet is obtained. When it is determined that the signal packet is a return packet, the DALI command of the return packet is obtained.

Referring toFIGS. 2, 6 and 7, the first embodiment of the method of demodulating a signal packet according to the disclosure includes a step12of receiving the signal packet, a step13of initializing the bit counter224to start counting, a step14of making a determination on a pulse, a step15of determining a value held by the bit counter224, a step16of making a determination on a pulse width, a step17of determining the pulse width, a step18of determining an accumulated number of pulses, a step19of determining the accumulated number of pulses, a step41of determining a value held by the first pulse counter225, and a step42of determining a value held by the second pulse counter226.

In the first embodiment, Pulse Width Modulation (PWM) is adopted for generating the signal packet, the signal packet being either a command packet or a return packet. The signal packet includes a plurality of bits, each being a bit1or a bit0. Each of the bits is represented by a plurality of pulses. A first pulse width W0associated with the pulses of the signal packet that define bit0is different from a second pulse width W1associated with the pulses of the signal packet that define bit1(seeFIG. 7). In the first embodiment, the first pulse width W0associated with bit0is greater than the second pulse width W1associated with bit1.

In step12, a controller receives the signal packet. The controller is one of the first controller22and the second controller31. In this embodiment, a scenario that the first controller22of one of the lighting devices2receives the command packet is given as an example herein for the sake of explanation. That is to say, the digital pulse demodulation unit223of the first controller22receives the command packet outputted by the second controller31. In another scenario, it may be the second controller31that receives the return packet outputted by the first controller22, and practice of this disclosure is not limited to the scenario discussed in the first embodiment herein.

In step13, the digital pulse demodulation unit223initializes the bit counter224, and the bit counter224is able to count a bit cumulative value which is associated with an accumulated number of the bits of the command packet that have been decided by the controller.

In step14, the digital pulse demodulation unit223determines whether a pulse of the command packet is the last pulse of a last one of the bits of the command packet. When it is determined in step14that the pulse of the command packet is the last pulse of the last one of the bits of the command packet, step15is performed. Otherwise, when it is determined in step14that the pulse of the command packet is not the last pulse of the last one of the bits of the command packet, step16is performed.

In step15, the digital pulse demodulation unit223makes a determination as to whether the bit cumulative value of the bit counter224is greater than a specific value. The specific value is associated with a number of bits of an effective signal packet. When a result of the determination made in step15is affirmative, it means that the command packet has been corrected, and the command packet is transmitted by the digital pulse demodulation unit223to the light control protocol interface21. When the result of the determination made in step15is negative, it means that transmission failure of the command packet occurs and the command packet cannot be corrected, and the first controller22ignores the command packet. It should be noted that the specific value is decided according to a number of bits of the DALI address and the DALI command of the signal packet. In the first embodiment, the number of bits of the command packet is twenty two (seeFIG. 4). The command packet includes the preamble represented by five bits, the DALI address represented by eight bits, the DALI command represented by eight bits, and the EOF represented by one bit. Since the total number of bits of the DALI address and the DALI command is sixteen, the specific value for the command packet is sixteen. On the other hand, for the return packet, the specific value is set to eight. In this embodiment, the DALI protocol is used for deciding the specific values. However, in another embodiment, if a different protocol is adopted, the specific values should be decided based on the number of bits confined by the different protocol, and are not limited to the disclosure of this embodiment.

In step16, each of the bits includes a plurality of pulses having the same pulse width, and each of bit0and bit1is associated with a respective one of the first pulse width W0and the second pulse width W1. The digital pulse demodulation unit223stores in advance the first pulse width W0, a first threshold value associated with bit0, the second pulse width W1, and a second threshold value associated with bit1. Therefore, in step16, the digital pulse demodulation unit223makes a determination as to whether or not a pulse width of each of the pulses of one of the bits of the command packet is associated with one of bit0and the bit1according to the first pulse width W0and the second pulse width W1. When a result of the determination made in step16is affirmative, step17is performed. Otherwise, when the result of the determination made in step16is negative, it means that the pulse is no contributory to demodulation of the command packet, the pulse is therefore ignored, and the flow goes back to step14for determination of the next pulse.

In step17, the digital pulse demodulation unit223determines whether the pulse width of the pulse of said one of the bits of the command packet is associated with bit0or bit1. When it is determined by the digital pulse demodulation unit223in step17that the pulse width of the pulse is associated with bit0(i.e., equal to the first pulse width W0), the first pulse counter225updates first counting data associated with a number of the pulses that define bit0. In the first embodiment, the first counting data includes a first cumulative value P0that is associated with an accumulated number of the pulses which have the pulse width associated with bit0. In other words, the first pulse counter225increases the first cumulative value P0by one, and the flow proceeds to step18. When it is determined by the digital pulse demodulation unit223that the pulse width is associated with bit1(i.e., equal to the second pulse width W1), the second pulse counter226updates second counting data associated with a number of the pulses that define bit1. In this embodiment, the second counting data includes a second cumulative value P1that is associated with an accumulated number of the pulses which have the pulse width associated with bit1. In other words, the second pulse counter226increases the second cumulative value P1by one, and the flow proceeds to step19.

In step18, the digital pulse demodulation unit223makes a determination as to whether an accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16is greater than or equal to a first checkpoint value N1. The first checkpoint value N1is a serial number of a specific one of those pulses that define bit0. When a result of the determination made in step18is affirmative, step41is performed. Otherwise, when the result of the determination made in step18is negative, the flow goes back to step14for making a determination on the next pulse. It should be noted that the digital pulse demodulation unit223further includes a counter (not shown) for keeping the accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16, and this counter is reset to zero once said one of the bits has been decided to be a bit0or a bit1. Since the arrangement of the counter should be readily known to the skilled in the art, detailed descriptions of the same are omitted herein.

In step41, the digital pulse demodulation unit223determines whether the first cumulative value P0of the first pulse counter225is greater than the first threshold value. In the first embodiment, the first threshold value includes a first pulse number T1that is associated with the number of the pulses defining bit0. When it is determined in step41that the first cumulative value P0is greater than the first pulse number T1, it means that the number of the pulses of said one of the bits whose pulse widths are associated with bit0has reached a criteria of judgment. Therefore, the digital pulse demodulation unit223decides that said one of the bits of the command packet is a bit0, and resets the first cumulative value P0stored in the first pulse counter225to zero. In addition, the bit cumulative value of the bit counter224is increased by one, and the flow goes back to step14for making a determination on the next pulse. On the other hand, when it is determined in step41that the first cumulative value P0is not greater than the first pulse number T1, the flow directly goes back to step14.

In step19, the digital pulse demodulation unit223makes a determination as to whether the accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16is greater than or equal to a second checkpoint value N2. The second checkpoint value N2is a serial number of a specific one of the pulses that define bit1. When a result of the determination made in step19is affirmative, step42is performed. Otherwise, when the result of the determination made in step19is negative, the flow goes back to step14.

In step42, the digital pulse demodulation unit223determines whether the second cumulative value P1of the second pulse counter226is greater than the second threshold value. In the first embodiment, the second threshold value includes a second pulse number T2that is associated with the number of the pulses defining bit1. When it is determined in step42that the second cumulative value P1is greater than the second pulse number T2, it means that the number of the pulses of said one of the bits whose pulse widths are associated with bit1has reached another criteria of judgment. Therefore, the digital pulse demodulation unit223decides that said one of the bits of the command packet is a bit1, and resets the second cumulative value P1stored in the second pulse counter226to zero. In addition, the bit cumulative value of the bit counter224is increased by one, and the flow goes back to step14for making a determination on the next pulse. On the other hand, when it is determined in step42that the second cumulative value P1is not greater than the second pulse number T2, the flow directly goes back to step14.

It should be supplemented that the first embodiment further includes a step11(seeFIG. 8). In step11, the digital pulse output unit221outputs a plurality of pulses, the digital pulse control unit222generates the return packet according to the plurality of digital pulses. In this embodiment, a scenario that the first controller22outputs the return packet is provided for explanation purposes. However, step11is also applicable to a scenario that the second controller31outputs the command packet. Therefore, the disclosure is not limited to the embodiment herein.

It should be further supplemented that the first pulse number T1and the second pulse number T2are decided based on the following approach. In the first embodiment, the bit rate of the signal packet is 5.8 kbps. Since the first pulse width W0associated with bit0is relatively large, the pulses defining bit0has a relatively slow pulse rate of 139.2 kpps (pulses per second). Since the second pulse width W1associated with bit1is relatively small, the pulses defining bit1has a relatively high pulse rate of 145 kpps. Therefore, the number of pulses used to represent bit0or bit1may be obtained by dividing the pulse rate by the bit rate. That is to say, the number of pulses used to represent bit0is twenty four (i.e., 139.2 k/5.8 k=24). Similarly, the number of pulses used to represent bit1is twenty five (i.e., 145 k/5.8 k=25). The first pulse number T1and the second pulse number T2are preferably set to be greater than half of the number of pulses used to represent bit0and bit1, respectively. Accordingly, the first pulse number T1associated with bit0must be greater than 12, and the second pulse number T2associated with bit1must be greater than 12.5.

In addition, the aforementioned first checkpoint value N1and the second checkpoint value N2are set to be serial numbers of specific ones of the pulses that define bit0and bit1, respectively. For example, for bit0defined by twenty four pulses, the first checkpoint value may be set to be 18, or the last serial number of the pulses, i.e., 24, depending on practical design needs. When the first checkpoint value N1or the second checkpoint value N2is smaller than half of the number of pulses defining the corresponding bit, the first pulse number T1or the second pulse number T2should also be adjusted to be smaller than half of the number of pulses defining the corresponding bit. Therefore, the disclosure is not limited to the requirements of the first embodiment. The requirements include that the first pulse number T1and the second pulse number T2must be greater than half of the number of pulses used to represent bit0and bit1, respectively.

In a variation of the first embodiment, the first counting data includes a first consecutive value S1that is associated with a number of consecutive ones of the pulses which have pulse widths associated with bit0, and the first threshold value includes a first setting value C1that is associated with the pulses defining bit0. In step41, the digital pulse demodulation unit223determines whether the first consecutive value S1is greater than the first setting value C1. When it is determined in step41that the first consecutive value S1is greater than the first setting value C1, it means that the number of the pulses of said one of the bits whose pulse widths are associated with bit0has reached a criteria of judgment, so that said one of the bits is decided as a bit0. Subsequently, the bit counter224increases the bit cumulative value by one, and the flow goes back to step14for making a determination on the next pulse. Otherwise, when it is determined in step41that the first consecutive value S1is not greater than the first setting value C1, the flow directly goes back to step14.

Similarly, in the variation of the first embodiment, the second counting data includes a second consecutive value S2that is associated with a number of consecutive ones of the pulses which have the pulse widths associated with bit1, and the second threshold value includes a second setting value C2that is associated with the pulses defining bit1. In step42, the digital pulse demodulation unit223determines whether the second consecutive value S2is greater than the second setting value C2. When it is determined in step42that the second consecutive value S2is greater than the second setting value C2, it means that the number of the pulses of said one of the bits whose pulse widths are associated with bit1has reached another criteria of judgment, so that said one of the bits is decided as a bit1. Subsequently, the bit counter224increases the bit cumulative value by one, and the flow goes back to step14for making a determination on the next pulse. Otherwise, when it is determined in step42that the second consecutive value S2is not greater than the second setting value C2, the flow directly goes back to step14.

Referring toFIGS. 2 and 8, step11includes a sub-step111of making a determination on a bit to be outputted, a sub-step112of outputting pulses, a sub-step113of making a determination on a pulse thus outputted, a sub-step114of making a determination on the next bit to be outputted, a sub-step115of changing the setting of a pulse width of pulses to be outputted, a sub-step116of outputting pulses, a sub-step117of making a determination on a pulse thus outputted, a sub-step118of making a determination on the bit thus outputted, a sub-step119of making a determination on the next bit to be outputted, and a sub-step110of changing the setting of a pulse width of pulses thus outputted.

In sub-step111, the digital pulse control unit222determines whether a current bit to be outputted and associated with the plurality of digital pulses outputted by the digital pulse output unit221is bit0or a bit1. When it is determined in sub-step111that the bit to be outputted is a bit0, the flow proceeds to sub-step112. When it is determined in sub-step111that the bit to be outputted is a bit1, the flow proceeds to sub-step116.

In sub-step112, the digital pulse control unit222outputs a current pulse having the pulse width associated with bit0.

In sub-step113, the digital pulse control unit222makes a determination as to whether the pulse just outputted thereby is the last pulse of the bit (i.e., bit0). When a result of the determination made in sub-step113is negative, the flow goes back to sub-step112for outputting a pulse next in sequence (i.e., a next pulse) for the current bit. Otherwise, when the result of the determination made in sub-step113is positive, the flow proceeds to sub-step114.

In sub-step114, the digital pulse control unit222determines whether the next bit to be outputted is a bit0or a bit1. When it is determined in sub-step114that the next bit is a bit0, the flow goes back to sub-step112for outputting a pulse of the next bit. When it is determined in sub-step114that the next bit is a bit1, the flow proceeds to sub-step115.

In sub-step115, since the pulse width of the pulses defining bit1is different from that of the pulses defining bit0, the digital pulse control unit222changes the setting of the pulse width of pulses to be outputted for the next bit that is a bit1, for example, changing from the first pulse width W0to the second pulse width W1. and the flow proceeds to sub-step116.

In sub-step116, the digital pulse control unit222outputs a pulse having the pulse width associated with bit1.

In sub-step117, the digital pulse control unit222makes a determination as to whether the pulse just outputted thereby is the last pulse of the bit (i.e., bit1). When a result of the determination made in sub-step117is negative, the flow goes back to sub-step116for outputting the next pulse. Otherwise, when the result of the determination made in sub-step117is positive, the flow proceeds to sub-step118.

In sub-step118, the digital pulse control unit222makes a determination as to whether the bit thus outputted is the last bit. When a result of the determination made in sub-step118is affirmative, it means that the return packet has been outputted completely, and the digital pulse control unit222terminates the output process. Otherwise, when the result of the determination made in sub-step118is negative, the flow proceeds to sub-step119.

In sub-step119, the digital pulse control unit222determines whether the next bit to be outputted is a bit0or a bit1. When it is determined in sub-step119that the next bit is a bit1, the flow goes back to sub-step116for outputting the pulses of the next bit. When it is determined in sub-step119that the next bit is a bit0, the flow proceeds to sub-step110.

In sub-step110, since the pulse width of the pulses defining a bit0is different from that of the pulses defining a bit1, the digital pulse control unit222changes the setting on the pulse width of subsequent pulses to be outputted (for the next bit, which is a bit0), and the flow proceeds to sub-step112.

Referring toFIGS. 2, 9 and 10, a second embodiment of the method of demodulating a signal packet according to the disclosure is similar to the first embodiment, and is also to be implemented by the communication system used in the first embodiment for transmission of a light control signal. The second embodiment is different from the first embodiment in that a new step51of making a determination on the second counting data of the second pulse counter226is performed subsequent to step14, a new step52of making a determination on the second counting data of the second pulse counter226is performed subsequent to step18and prior to step41, and a new step53of making a determination on the first counting data of the first pulse counter225is performed subsequent to step19and prior to step42.

When it is determined in step14that the pulse of the command packet is not the last pulse of the last one of the bits of the command packet, step16is performed. Otherwise, when it is determined in step14that the pulse of the command packet is the last pulse of the last one of the bits of the command packet, step51is performed.

In step51, the digital pulse demodulation unit223determines whether the second cumulative value P1that is associated with an accumulated number of the pulses which have the pulse width belonging to the bit1is greater than the second pulse number T2. When it is determined in step51that the second cumulative value P1is greater than the second pulse number T2, the last one of the bits is decided as a bit1, the bit cumulative value of the bit counter224is increased by one, and step15is performed. Otherwise, when it is determined in step51that the second cumulative value P1is not greater than the second pulse number T2, the bit to which the last pulse belongs is ignored, and the flow directly proceeds to step15.

Bit0is given as an example for explanatory purposes hereinafter. When a result of the determination made in step18is affirmative, i.e., the accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16is greater than or equal to the first checkpoint value N1, the flow proceeds to step52.

In step52, the digital pulse demodulation unit223makes a determination as to whether or not the second cumulative value P1of the second pulse counter226is greater than or equal to a predetermined first base number E1and is smaller than or equal to the second pulse number T2, that is E1≦P1≦T2. When a result of the determination made in step52is affirmative, the digital pulse demodulation unit223decides that a preceding bit of said one of the bits of the command packet is a bit1. The bit counter224increases the bit cumulative value by one, and the second pulse counter226clears the second cumulative value P1stored therein. The flow subsequently proceeds to step41for determining whether the first cumulative value P0of the first pulse counter225is greater than the first pulse number T1. When it is determined in step41that the first cumulative value P0is not greater than the first pulse number T1(i.e., P0≦T1), the flow directly goes back to step14for making a determination on the next pulse. When it is determined in step41that the first cumulative value P0is greater than the first pulse number T1(i.e., P0>T1), it means that the number of the pulses of said one of the bits whose pulse widths are associated with bit0has reached the criteria of judgment. Therefore, the digital pulse demodulation unit223decides that said one of the bits of the command packet is a bit0, and resets the first cumulative value P0stored in the first pulse counter225to zero. In addition, the bit cumulative value of the bit counter224is increased by one, and the flow goes back to step14for making a determination on the next pulse.

When the result of the determination made in step52is negative, the second pulse counter226clears the second cumulative value P1stored therein, and the flow proceeds to step41for determining whether the first cumulative value P0is greater than the first pulse number T1, so as to decide whether said one of the bit is a bit0.

On the contrary, bit1is given as an example for explanatory purposes hereinafter. When the result of the determination made in step19is affirmative, i.e., the accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16is greater than or equal to the second checkpoint value N2, the flow proceeds to step53.

In step53, the digital pulse demodulation unit223makes a determination as to whether or not the first cumulative value P0of the first pulse counter225is greater than or equal to a predetermined second base number E2and is smaller than or equal to the first pulse number T1, that is E2≦P0≦T1. When a result of the determination made in step53is affirmative, the digital pulse demodulation unit223decides that a preceding bit of said one of the bits of the command packet is a bit0. The bit counter224increases the bit cumulative value by one, and the first pulse counter225clears the first cumulative value P0stored therein. The flow subsequently proceeds to step42for determining whether the second cumulative value P1of the second pulse counter226is greater than the second pulse number T2. When it is determined in step42that the second cumulative value P1is not greater than the second pulse number T2(i.e., P1≦T2), the flow directly goes back to step14for making a determination on the next pulse. When it is determined in step42that the second cumulative value P1is greater than the second pulse number T2(i.e., P1≧T2), it means that the number of the pulses of said one of the bits whose pulse widths are associated with bit1has reached the criteria of judgment. Therefore, the digital pulse demodulation unit223decides that said one of the bits of the command packet is a bit1, and resets the second cumulative value P1stored in the second pulse counter225to zero. In addition, the bit cumulative value of the bit counter224is increased by one, and the flow goes back to step14for making a determination on the next pulse.

When the result of the determination made in step53is negative, the first pulse counter225clears the first cumulative value P0stored therein, and the flow proceeds to step42for determining whether the second cumulative value P1is greater than the second pulse number T2, so as to decide whether said one of the bit is a bit1.

Referring toFIGS. 2, 9, 10 and 11, four scenarios are provided hereinafter for explaining the second embodiment of the disclosure.

In the first scenario, when it is determined in step42that the second cumulative value P1of the second pulse counter226is not greater than the second pulse number T2, the flow directly goes back to step14for making a determination on the next pulse. After the pulse width of the pulse of said one of the bits of the command packet is determined to be associated with bit0in step17, i.e., a change of pulse width occurs, subsequent to step18, the flow proceeds to step52for making the determination as to whether or not the second cumulative value P1of the second pulse counter226is greater than or equal to the predetermined first base number E1and is smaller than or equal to the second pulse number T2, that is E1≦P1≦T2. When the result of the determination made in step52is affirmative, the digital pulse demodulation unit223decides that a preceding bit of said one of the bits of the command packet is a bit1. The bit counter224increases the bit cumulative value by one, and the second pulse counter226clears the second cumulative value P1stored therein. When the result of the determination made in step52is negative, the second pulse counter226clears the second cumulative value P1stored therein. Regardless of whether the result of the determination made in step52is positive or negative, the flow eventually proceeds to step41for determining whether the first cumulative value P0of the first pulse counter225is greater than the first pulse number T1, so as to decide whether said one of the bit is a bit0.

Moreover, in this embodiment, whether said one of the bits of the command packet is a bit0is determined based on the determination associated with the first checkpoint value N1of step18and based on whether the first cumulative value P0is greater than the first pulse number T1of step41. In a variation of this embodiment, whether said one of the bits of the command packet is a bit0may also be determined based on the determination associated with the first checkpoint value N1and based on whether the first consecutive value S1that is associated with a number of consecutive ones of the pulses which have the pulse widths that are associated with bit0is greater than the first setting value C1. For example, if four consecutive pulses having pulse widths associated with bit0are received, there is a great chance that said one of the bits of the command packet is a bit0. Depending on the fault tolerant capability of the communication system, the first setting value C1may be adjusted to serve as a different threshold for the first consecutive value S1, and is thus not limited to the disclosure herein.

In the second scenario, when it is determined in step42that the second cumulative value P1of the second pulse counter226is greater than the second pulse number T2, that is T2<P1, said one of the bits of the command packet is determined as a bit1, and the bit cumulative value of the bit counter224is increased by one.

Similarly, in this embodiment, whether said one of the bits of the command packet is a bit1is determined based on the determination associated with the second checkpoint value N2of step19and based on whether the second cumulative value P1is greater than the second pulse number T2of step42. In a variation of this embodiment, whether said one of the bits of the command packet is a bit1may also be determined based on the determination associated with the second checkpoint value N2and based on whether the second consecutive value S2that is associated with a number of consecutive ones of the pulses which have the pulse widths associated with bit1is greater than the second setting value C2. For example, if four consecutive pulses having pulse widths associated with bit1are received, there is a great chance that said one of the bits of the command packet is a bit1. Depending on the fault tolerant capability of the communication system, the second setting value C2may be adjusted to serve as a different threshold for the second consecutive value S2, and is thus not limited to the disclosure herein.

In the third scenario, when it is determined in step42that the second cumulative value P1of the second pulse counter226is not greater than the second pulse number T2, that is P1≦T2, the flow goes back to step14for making a determination on the next pulse. In such precondition, the flow proceeds to step16and step17for determining whether a pulse width of the next pulse is associated with bit0or bit1. When the pulse width is determined as being associated with bit1in step17, step42will be performed. When it is determined in step42that the second cumulative value P1of the second pulse counter226is greater than the second pulse number T2, that is T2<P1, said one of the bits of the command packet is determined as the bit1, and the bit cumulative value of the bit counter224is increased by one.

In the fourth scenario, when it is determined in step14that the pulse of the command packet is the last pulse of a last one of the bits of the command packet, step51is performed for determining whether the second cumulative value P1of the second pulse counter226is greater than the second pulse number T2. This is because, for both of the command packet inFIG. 4and the return packet inFIG. 5, the last bit which serves as the EOF should be a bit1to represent the end of the packet. In this way, step51is performed to determine whether an accumulated number of the pulses of the last bit of the signal packet which have the pulse width associated with bit1(i.e., the second cumulative value P1of the second pulse counter226) is greater than the second pulse number T2. When a result of the determination made in step51is affirmative, the last bit is a bit1, and the bit cumulative value of the bit counter224is increased by one. When the result of the determination made in step51is negative, the bit to which the last pulse belongs is ignored, and the flow proceeds to step15for determining whether the bit cumulative value of the bit counter224is greater than the specific value, so as to determine whether the signal packet is completely received for subsequent transmission to the light control protocol interface.

For the first scenario, after the determinations on all pulses of one of the bits are finished, and the first cumulative value P0and the second cumulative value P1are not greater than the first pulse number T1and the second pulse number T2, respectively, the digital pulse demodulation unit223takes a next bit as reference in deciding said one of the bits. For example, bit1is represented by six pulses each having a pulse width of 5 μm, and bit0is represented by four pulses each having a pulse width of 8 μm. When a return packet contains information of three bits of “101”, the pulses of the return packet having pulse widths represented in numerals would be (555555 8888 555555). Due to the influence of noise and parameter deviation of circuit elements in the power line transmission medium, the pulses of the return packet received at the second controller31of the control device3may be (556541 8887 455555). When the second pulse number T2is set at three, after undergoing the steps shown inFIGS. 9 and 10, the second cumulative value P1that is associated with an accumulated number of the pulses which have the pulse width of 5 μm associated with the first bit1is three, which is not greater than the second pulse number T2. Accordingly, the digital pulse demodulation unit223takes the next bit (i.e., bit0) for reference. When the result of the determination associated with the first checkpoint value N1in step18is affirmative, in step52, the digital pulse demodulation unit223makes the determination as to whether or not the second cumulative value P1of the second pulse counter226is greater than or equal to the predetermined first base number E1and is smaller than or equal to the second pulse number T2. In this way, the first bit of the return packet may be decided as a bit1, and in the subsequent step41, the next bit is decided as a bit0. In a similar manner, the information of “101” contained in the return packet thus demodulated and corrected may be obtained.

To sum up, in the method of demodulating a signal packet according to the disclosure, when the digital pulse demodulation unit223is demodulating the signal packet, distortions associated with the pulses of the bits of the signal packet may be corrected by virtue of steps16-19,41and42. In step17, the determination as to whether the pulse width of each of the pulses of one of the bits of the signal packet is associated with bit0or bit1is made. In step18, the determination as to whether the accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16is greater than or equal to the first checkpoint value N1is made. When it is determined in step41that the number of the pulses of said one of the bits whose pulse widths associated with bit0(i.e., the first cumulative value P0) has reached the criteria of judgment according to the first pulse number T1, said one of the bits is decided as a bit0. On the other hand, in step19, the determination as to whether the accumulated number of the pulses of said one of the bits whose pulse widths have undergone the determination made in step16is greater than or equal to the second checkpoint value N2is made. When it is determined in step42that the number of the pulses of said one of the bits whose pulse widths associated with bit1(i.e., the second cumulative value P1) has reached the criteria of judgment according to the second pulse number T2, said one of the bits is decided as a bit1. When decision of said one of the bits to be a bit0or a bit1cannot be made because the first cumulative value P0or the second cumulative value P1is not greater than the first pulse number T1or the second pulse number T2, a next one of the bits may be used to make the decision. For example, in a situation that a bit level is switched from bit1to bit0, when determination on the first bit at a receiver end turns out to be indecisive, the next bit represented by pulses with a pulse width different from that of the pulses representing the first bit is to be decided, and the first bit may be decided during the process of deciding the next bit. If a distortion occurs at the second bit, the third bit is used for deciding the second bit, and so forth. In another situation of consecutive bits0or consecutive bits1, pulses of the next bit may be used for deciding a current bit.

Therefore, by virtue of the error correction capability of the digital pulse demodulation unit223, adverse influence on the pulse period or the pulse width resulting from noise or parameter deviation of circuit elements in the power line may be prevented.