Liquid crystal display having black matrix disconnected at portions thereof and method for fabricating the same

In a method of fabricating a thin film transistor array substrate, a black matrix with horizontal and vertical portions is first formed on a substrate with an opaque conductive material. A gate line assembly is formed on the black matrix, and buffer layers are formed between the separate portions of the black matrix. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited onto the substrate. And a data line assembly is formed on the ohmic contact layer. The ohmic contact layer exposed through the data line assembly is etched, and a protective layer is deposited onto the substrate. The protective layer, the gate insulating layer, and the semiconductor layer are patterned to form contact holes and opening portions exposing the insulating layer at pixel areas. The peripheral portions of the black matrix are also exposed through the opening portions. An indium tin oxide layer is deposited onto the substrate, and patterned to form pixel electrodes, subsidiary gate pads and subsidiary data pads that are connected to the drain electrodes, the gate pads and the data pads through the contact holes. Buffer conductive layers are formed at the same plane as the data line assembly or the pixel electrodes while being positioned over the semiconductor pattern between the neighboring data lines. Opening portions may be formed at a common electrode of the color filter substrate over the semiconductor pattern.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor (TFT) array substrate for liquid crystal displays and a method for fabricating the same and, more particularly, to a TFT array substrate of good performance characteristics.

(b) Description of the Related Art

Generally, a liquid crystal display (LCD) is formed with two glass substrates, and a liquid crystal sandwiched in-between the substrates.

One of the substrates has a common electrode, a color filter and a black matrix, and the other substrate has pixel electrodes and thin film transistors (TFTs). The former substrate is usally called the “color filter substrate,” and the latter substrate called the “TFT array substrate.”

The TFT array substrate is fabricated through forming a plurality of thin films, and performing photolithography with respect to the thin films. In photolithograpy, a number of masks are used for uniformly etching the thin films, involving complicated processing steps and increased production cost. Therefore, reduction in the number of masks becomes a critical factor in the fabrication of the TFT array substrate.

On the other hand, the color filter substrate is provided with a black matrix. The black matrix should be formed with a predetermined degree of marginal width considering the possible alignment error when assembling the color filter substrate and the TFT array substrate. However, the wider black matrix reduces the opening ratio. Therefore, it is required to increase the opening ratio of the black matrix while maintaining other performance characteristics in a stable manner.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method for fabricating a TFT array substrate for a LCD which involves reduced number of masks while simplifying the processing steps.

It is another object of the present invention to provide a method for fabricating a TFT array substrate with an increased device opening ratio.

These and other objects may be achieved in the following way.

A mesh-shaped black matrix is formed under the TFTs with opening portions at pixel areas. A gate insulating layer and a protective layer are etched at the step of forming a semiconductor pattern while forming contact holes for interconnecting conductive layers.

Specifically, a black matrix is formed on a first substrate while being mesh-shaped with opening portions at pixel areas. An insulating layer is formed on the substrate while covering the black matrix. A gate line assembly is formed on the insulating layer. The gate line assembly includes gate lines proceeding in the horizontal direction, and gate electrodes connected to the gate lines. A gate insulating layer, and a semiconductor layer are sequentially deposited onto the substrate. An ohmic contact layer is formed on the semiconductor layer, and a data line assembly is formed on the ohmic contact layer. The data line assembly includes source and drain electrodes separated from each other, and data lines connected to the source electrodes while crossing over the gate lines to define the pixel areas. A protective layer is deposited onto the substrate while covering the data line assembly and the gate line assembly. The protective layer, the gate insulating layer, and the semiconductor layer are patterned to thereby form opening portions exposing the insulating layer at the pixel areas.

Pixel electrodes are formed on the protective layer such that they are connected to the drain electrodes. First contact holes exposing the drain electrodes are formed at the step of forming the opening portions, and the connection of the pixel electrodes to the drain electrodes is made through the first contact holes.

The black matrix is separated into a number of portions, and buffer layers are positioned between the neighboring separate portions of the black matrix. The buffer layers are placed at the same plane as the gate line assembly or the data line assembly.

Each pixel electrode has a peripheral portion overlapped with the black matrix. The protective layer is formed in the same shape as the gate insulating pattern and the semiconductor pattern except the first contact holes. The borderlines of the protective layer, the gate insulating pattern, and the semiconductor pattern are placed over the black matrix except the area where the drain electrodes are present.

The gate line assembly further includes gate pads connected to the gate lines to receive scanning signals from the outside and transmit the scanning signals to the gate lines. The gate insultaing pattern, the semiconductor pattern and the protective layer have second contact holes exposing the gate pads.

The data line assembly further includes data pads connected to the data lines to receive picture signals from the outside and transmit the picture signals to the data lines. The gate insultaing pattern, the semiconductor pattern and the protective layer have third contact holes exposing the data pads.

Subsidiary gate and data pads may be formed at the same plane as the pixel electrodes such that the subsidiary gate and data pads are connected to the gate and data pads through the second and third contact holes.

Buffer conductive layers may be formed at the same plane as the data line assembly or the pixel electrodes while being positioned over the semiconductor pattern between the neighboring data lines.

In case the buffer conductive layer is placed at the same plane as the data line assembly, second contact holes are formed at the protective layer such that they expose the gate lines and the buffer conductive layers, and a connection pattern is formed at the same plane as the pixel electrodes. The connection pattern connects the gate lines to the buffer conductive layers through the second contact holes.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be explained with reference to the accompanying drawings.

FIG. 1is a plan view of a TFT array substrate for a liquid crystal display according to a preferred embodiment of the present invention, andFIG. 2is a cross sectional view of the TFT array substrate taken along the II—II′ line ofFIG. 1.

As shown in the drawings, a black matrix90is formed on the TFT array substrate10with opaque conductive material, chrome nitride, or molybdenum nitride. The black matrix90may have a single-layered structure or a multiple-layered structure. The black matrix90is mesh-shaped with opening portions at pixel areas. The black matrix90has horizontal portions92and vertical portions94separated from each other. The black matrix90has a role of preventing leakage of light between the pixel areas. The black matrix90may vary in shape to prevent the light incident upon a semiconductor pattern40for the TFTs. Separation of the horizontal and vertical portions92and94of the black matrix90is to prevent scanning signals transmitted to gate lines22overlapped with the horizontal portions92from being interfered with or delayed due to data signals transmitted to data lines62overlapped with the vertical portions94. In this preferred embodiment, such a separation is made through dividing the vertical portions94into plural numbers of sub-portions, but may be also made through dividing the horizontal portions92or dividing both of the horizontal and vertical portions92and94.

An insulating layer100is formed on the substrate10while covering the black matrix90. It is preferable that the insulating layer100is formed with silicon oxide having a lower dielectric constant of 3.0–4.0 while bearing a sufficient thickness of 0.5—3.0 μm. This is to minimize signal delays transmitted to a gate line assembly and a data line assembly due to the black matrix90.

The gate line assembly is formed on the insulating layer100with a conductive material or a metallic material such as Al, Al alloy, Mo, MoW, Cr, Ta, Cu, and Cu alloy while proceeding in the horizontal direction. The gate line assembly includes gate lines22overlapping with the horizontal portions92of the black matrix90, gate pads24for transmitting scanning signals or gate signals to the gate lines22, and gate electrodes26connected to the gate lines22to form the TFTs. The gate line assembly may overlap pixel electrodes82to form storage capacitors. In case such a structure do not produce sufficient storage capacity, additional storage capacitor lines may be provided at the same plane as the gate line assembly while overlapping the pixel electrodes82to form such storage capacitors. Buffer layers28are formed at the same plane as the gate line assembly between the horizontal and vertical portions92and94of the black matrix90while partially overlapping them.

A gate insulating pattern30is formed on the insulating layer100with silicon nitride while covering the gate line assembly and the buffer layers28. A semiconductor pattern40for the TFTs is formed on the gate insulating layer30with hydrogenated amorphous silicon. Ohmic contact layers55and56are formed on the semiconductor pattern40with amorphous silicon doped with n-type impurities such as phosphorous P, micro-crystallized silicon, or metal silicide while being separated from each other.

A data line assembly is formed on the ohmic contact layers55and56with a conductive material having a lower resistance based on aluminum, copper, or silver. The data line assembly includes data lines62proceeding in the vertical direction while defining the pixel areas together with the gate lines22, data pads68connected to one end of the data lines62to receive picture signals from the outside, source electrodes65branched from the data lines62to form the TFTs while positioning on one of the ohmic contact layers55, and drain electrodes66separated from the source electrodes65while interposing the gate electrodes26between them to form the TFTs. The drain electrodes66are positioned on the other ohmic contact layer56.

As with the gate line assembly, the data line assembly may be formed with a conductive material having a lower resistance while bearing a single-layered structure or a multiple-layered structure. When the data line assembly has a double-layered structure, it is preferable that one layer is formed with a material having a lower resistance, and the other layer with a material having a good contact characteristic with other materials.

The ohmic contact layers55and56has the same shape as the data line assembly. In case the horizontal portions92of the black matrix90are divided into a number of sub-portions, additional buffer layers may be provided at the same plane as the data line assembly to prevent light leakage at the gap between the sub-portions of the horizontal portions92.

A protective layer70is formed on the data line assembly. The protective layer70is formed with silicon nitride or acryl-based organic insulating material while bearing contact holes76exposing the drain electrodes66. The protective layer70has contact holes78exposing the data pads68, and contact holes74exposing the gate pads24together with the semiconductor pattern40and the gate insulating pattern30. The protective layer70is further provided with opening portions72exposing the gate insulating pattern30, the semiconductor pattern40, and the insulating layer100at the pixel areas. The opening portion72of the protective layer70at each pixel area reaches up to the periphery of the black matrix90except the portion of the protective layer70with the underlying drain electrode66.

The protective layer70is formed with an outline similar to the gate insulating pattern30and the semiconductor pattern40. Particularly, except the contact holes76and78, the protective layer70is formed with the same shape as the gate insulating pattern30and the semiconductor pattern40. The protective layer70, the gate insulating pattern30, and the semiconductor pattern40are shaped along the outlines of the gate line assembly and the data line assembly, and altogether have a shape similar to the black matrix90except the portion shaped along the outline of the drain electrodes66. In case additional storage capacitor lines are provided at the same plane as the gate line assembly, additional portions of the protective layer70covering the storage capacitor lines as well as the underlying gate insulating pattern and semiconductor pattern may be formed.

Pixel electrodes82are formed on the insulating layer100exposed through the opening portions72to receive picture signals from the TFTs and form electric fields together with a common electrode of the color filter substrate. The pixel electrodes82are formed with a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). The pixel electrodes82are coupled to the drain electrodes66through the contact holes76, and receives picture signals from the drain electrodes66. The pixel electrodes82may be overlapped with the neighboring gate lines22to form storage capacitors.

Meanwhile, subsidiary gate pads84and subsidiary data pads88are connected to the gate pads24and the data pads68through the contact holes74and78to strengthen adhesion thereof to external circuits while protecting them, but may be omitted.

In the above structure, since the black matrix90is formed at the TFT array substrate10with the pixel electrodes82, the width of the black matrix90may be minimized without considering the alignmenterror, enhacing the opening ratio.

Meanwhile, the black matrix90may be centrally provided with an opening portion while minimizing the overlapped area of the gate lines22and the data lines62to prevent signal transmission delay.

The above structure may be applied to various types of liquid crystal display devices such as an in-plane switching mode liquid crystal display where the common electrode and the pixel electrodes form electric fields parallel to the substrates, a vertical alignment mode liquid crystal display where liquid crystal molecules are aligned normal to the substrates with negative dielectric anisotropy, or a wide viewing angle liquid crystal display where the common electrode is patterned with opening or protruded portions, and the liquid crystal molecules are oriented in all directions due to fringe fields.

The method of fabricating the TFT array substrate will be now described with reference toFIGS. 3A to 6B.

As shown inFIGS. 3A and 3B, an opaque conductive material such as chrome is deposited onto the TFT array substrate10through sputtering, and dry or wet-etched to form a black matrix90with horizontal portions92and vertical portions94.

The conductive material for the black matrix90may be selected from aluminum, aluminum alloy, copper, copper alloy, silver, chrome, molybdenum, titanum, or chrome nitride.

As shown inFIGS. 4A and 4B, an insulating layer100is formed on the substrate10with an organic material having a good planar characteristic, or silicon nitride having a lower dielectric constant. Thereafter, a conductive material having a lower resistance such as Mo, MoW, Cr, Ta, Al, Al alloy, Cu, Cu alloy, and silver is deposited onto the insulating layer100through sputtering, and dry or wet-etched through photolithography to form a gate line assembly and buffer layers28. The gate line assembly includes gate lines22, gate electrodes26, and gate pads24. The gate line assembly has a double-layered structure with a chrome-based under-layer, and an aluminum-based over-layer.

Then, as shown inFIGS. 5A and 5B, a gate insulating layer30, a semiconductor layer40, and an ohmic contact layer50are sequentially deposited onto the substrate10through chemical vapor deposition. A conductive material as used in forming the gate line assembly is deposited onto the ohmic contact layer50, and dry or wet-etched through photolithography to form a data line assembly. The data line assembly includes data lines62defining the pixel areas while crossing over the gate lines22, source electrodes65branched from the data lines62while extending over the gate electrodes26, data pads68connected to one ends of the data lines62, and drain electrodes66separated from the source electrodes65while interposing the gate electrodes26between them. In case the horizontal portions92of the black matrix90are divided into a number of sub-portions, additional buffer layers may be formed between the sub-portions of the horizontal portions to prevent light leakage there. The data line assembly has a double-layered structure with a chrome-based under-layer and an aluminum-based over-layer.

Thereafter, the ohmic contact layer50exposed through the data line assembly is etched to be separated into ohmic contact patterns55and56around the gate electrode26while exposing the semiconductor layer40between them.

As shown inFIGS. 6A and 6B, a protective layer70is deposited onto the substrate10with silicon nitride, and dry-etched together with the gate insulating layer30and the semiconductor layer40to form a semiconductor pattern40and a gate insulating pattern30. The semiconductor pattern40and the gate insulating pattern30have contact holes74,76and78exposing the gate pads24, the drain electrodes66and the data pads68. At this time, opening portions72exposing the insulating layer100at the pixel areas are formed together such that they expose the peripheral portions of the black matrix90at the pixel areas.

Thereafter, as shownFIGS. 1 and 2, pixel electrodes82, subsidiary gate pads84, and subsidiary data pads88are formed at the substrate10through depositing and patterning an IZO-based layer such that the pixel electrodes are connected to the drain electrodes66through the contact holes76, and the subsidiary gate and data pads84and88are connected to the gate pads24and the data pads68through the contact holes74and78, respectively. In case the pixel electrodes82, the subsidiary gate pads84and the subsidiary data pads88are formed with ITO having a poor contact characteristic with aluminum, it is preferable that the neighboring aluminum-based layer is removed. In this preferred embodiment, since IZO is used for that purpose, the aluminum-based layer may be formed in contact with the IZO-based layer.

In the above process, the black matrix is formed at the TFT array substrate so that possible errors in aligning the TFT array substrate and the color filter substrate can be avoided while enhancing opening ratio. Furthermore, since the contact holes74and78exposing the pads and the semiconductor pattern are formed together, only five masks are required while simplifying the processing steps.

In case the protective layer70, the semiconductor pattern40and the gate insulating layer30are patterned along the outlines of the gate line assembly and the data line assembly to simplify the processing steps, the semiconductor pattern40is continuously formed over the gate line assembly22and26as shown inFIGS. 1 and 2. In this structure, when gate signals are applied to the gate line assembly22and26, channels may be formed at regions other than the channel regions between the source electrodes65and the drain electrodes66. That is, such channels are formed in the semiconductor pattern40at the A regions between the data lines62and the source electrodes65, and over the gate lines22between the neighboring data lines62.

Current may leak at the A regions due to the light incident from a blacklight (being a light source for the device). However, in this preferred embodiment, since the horizontal portions92of the black matrix90are formed under the semiconductor pattern40at the A regions, the light incident thereto from the bottom side can be intercepted. Therefore, current does not leak at the A regions.

Possible leakage of current occurring at the semiconductor pattern40over the gate lines22between the neighboring data lines62will be now explained in detail by way of simulation.

FIGS. 7,8and9schematically illustrate the structure of the gate line assembly between the neighboring data lines at one pixel area. In the drawings, the color filter substrate is illustrated together with the TFT array substrate.

As shown inFIG. 7, the TFT array substrate10is sequentially overlaid with the gate line assembly22and26, the gate insulating layer30, the semiconductor pattern40, the ohmic contact layer55and56, the data line assembly62,65and66, and the protective layer70.

Meanwhile, a common electrode210is formed at the entire surface of the color filter substrate200facing the TFT array substrate10.

As shown inFIG. 8, a buffer conductive layer69is formed over the semiconductor pattern40between the neighboring data lines62while being connected to the gate lines22through a connection pattern89. As shown inFIG. 9, an opening portion211is formed at the common electrode210over the semiconductor pattern40between the neighboring data lines62.

As shown inFIG. 7, since the semiconductor pattern40is formed at the channel region C over the gate electrode26as well as at the region D over the gate line22, current may leak at the semiconductor pattern40at the D region when scanning signals are applied to the gate line assembly22and26. However, as shown in the drawing, the channel region C is under the strong influence of the electric field due to the gate signals applied to the gate line assembly22and26, but such an influence of the electric field is weak at the D region far away from the drain electrodes66and the data lines62. As shown inFIG. 8, when the buffer conductive layer69connected to the gate line assembly22and26is formed over the semiconductor pattern40between the neighboring data lines62, the electric field due to the gate signals transmitted to the gate line assembly22and26does not influence the semiconductor pattern40. Therefore, as the current passage is not formed in the semiconductor pattern40at the D region, current does not leak there. In case the buffer conductive layer69is formed with an opaque material, it also intercepts the light incident upon the semiconductor pattern40through the upper substrate200so that leakage of current at the semiconductor pattern40due the incidence light can be minimized. The buffer conductive layer69may be formed at the same plane as the data line assembly, or at the same plane as the pixel electrodes82. In this preferred embodiment, the buffer conductive layer69is formed at the same plane as the data line assembly. The contact holes exposing the buffer conductive layer69and the gate lines22are formed at the step of forming the contact holes74,76and78, and the opening portions72. The connection pattern89electrically connecting the buffer conductive layer69to the gate lines22through the contact holes is formed at the step of forming the pixel electrode82. Of course, in case the buffer conductive layer69is formed at the same plane as the pixel electrodes82, the contact holes exposing the gate lines22are formed at the step of forming the contact holes74,76and78and the opening portions72, and the buffer conductive layer69is formed at the step of forming the pixel electrodes82. Furthermore, as shown inFIG. 9, in case the opening portion211is formed at the common electrode210over the semiconductor pattern40between the neighboring data lines62, the influence of the electric field to the semiconductor pattern40due to the gate signals can be further reduced while completely intercepting the passage of current leakage at the D region.

As described above, the black matrix is formed at the TFT array substrate with the pixel electrodes so that opening ratio of the device can be enhanced in a stable manner. The semiconductor pattern and the contact holes are formed together so that the processing steps can be simplified. Possible leakage of current can be prevented at the non-channel area using the black matrix. Furthermore, a buffer conductive layer is formed over the semiconductor pattern between the neighboring data lines, and an opening portion is formed at the common electrode over the semiconductor pattern so that current leakage can be completely prevented at the semiconductor pattern.