Single-ended to differential buffer circuit and method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs

A single-ended to differential buffer circuit is disclosed, adapted to couple at least an input analog signal to a receiving circuit. The buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The buffer circuit further comprises an input section comprising a first and a second switched capacitor, each adapted to sample said input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. In the buffer circuit the second sides of said first and second switched capacitors are controllably connectable/disconnectable to/from said first and second inputs of the differential amplifier respectively. Moreover, in the buffer circuit the second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from said second output and said first output respectively. A method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs is also disclosed.

TECHNICAL FIELD

The present disclosure relates to a buffer circuit, in particular to a single-ended to differential buffer circuit, and to a method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs.

BACKGROUND ART

In many applications there is the need to measure one or, usually, more single ended analog signals having relatively high source impedances. This is for example the case of mobile terminals, where there is the need to measure several operating parameters, such as the charge level of the battery, the temperature of the battery, the status of the connection to an external device, etc. Usually the analog signals that have to be measured are low frequency signals (for example from 0 to 500 Hz). A general purpose ADC (in short GPADC) is often used to convert the above mentioned signals from the analog to the digital domain while measuring them. In the latter case, the above conversion should be performed on the whole input signal dynamic range with the maximum accuracy of the ADC, i.e. with very low offset and gain error and low non-linearity errors (usually indicated with the acronyms INL—Integral Non Linearity—and DNL—Differential Non Linearity).

U.S. Pat. No. 7,397,287 discloses a sample hold circuit which can convert a single-ended signal into a differential signal intended to be fed to a differential analog to digital converter. The above indicated sample and hold circuit, which performs the function of an input buffer, comprises a differential operational amplifier, a first set of capacitors provided on an inverting side of the operational amplifier and a second set of capacitors provided on a non-inverting side of the operational amplifier. In the sample and hold circuit of U.S. Pat. No. 7,397,287 there is the need of keeping the operational amplifier in the ON state during the track-and-hold phase of the input signal. Moreover, if there is the need of managing more input signals to be provided to the analog to digital converter, the circuit of U.S. Pat. No. 7,397,287 must be replicated for each of said signals, thus requiring a significant increase in the area occupation.

SUMMARY OF THE INVENTION

In view of the above described problems, it is an object of the present invention is to provide a high input single-ended to differential buffer which is adapted to couple at least a single-ended input analog signal to a receiving circuit with differential inputs and which does not require the differential amplifier to be in power ON state during the sampling of the input signal.

The single-ended to differential buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The single-ended to differential buffer circuit comprises an input section comprising a first and a second switched capacitor, each adapted to sample the input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. The second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from the first and second inputs of the differential amplifier respectively. The second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from said second output and said first output respectively.

According to an embodiment, by providing a plurality of dedicated input sections of the above described kind, each associated to a respective input analog signal, adapted to be selectively connected to a temporally shared output section of the above described kind, it is possible to provide a multi-input single ended to differential buffer circuit which does not require a significant increase in the area occupation, because it does not need a differential amplifier for each of the input analog single-ended signals to be coupled to the receiving circuit.

A further object of the present invention is to provide a method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs, by means of an output section comprising a differential amplifier having a first and second input and a first and second output and by means of an input circuit section, associated to said single ended input analog signal, comprising a first and a second switched capacitor. The method comprises a step of sampling said input signal by controllably connecting said capacitors between a first node fed with said input signal and a second node fed with a reference voltage or connected to ground. The sampling step is such to establish an initial charge on said capacitors. The method comprises a subsequent step of connecting the first switched capacitor between said first input and said first output and connecting the second switched capacitor between said second input and said second output. The method comprises a subsequent step of restoring the initial charge on the switched capacitors by connecting said capacitors between said first output and said second output of the differential amplifier.

According to an embodiment, by providing a plurality of dedicated input sections of the above described kind, each associated to a respective input analog signal, and selectively connecting such input sections to a temporally shared output section of the above described kind, it is possible to provide a method that is adapted to couple a plurality of input single-ended analog signals to a receiving circuit with differential inputs and which can be implemented with a circuit which does not require a significant increase in the area occupation.

DETAILED DESCRIPTION

In the attached figures identical or similar elements will be indicated with the same reference numbers/symbols.

FIG. 1illustrates a very schematic view of an embodiment of mobile terminal1, such as for example a mobile phone, comprising a circuit system20. The circuit system20comprises a single-ended to differential buffer circuit21,22adapted to couple at least a single-ended analog signal to a receiving circuit24with differential inputs. In the particular example shown, the receiving circuit24is for example, and without for this reason introducing any limitation, a fully differential general purpose analog to digital converter (GPADC) operating at a prescribed sampling frequency.

According to an embodiment, the at least one single-ended analog signal comprises a plurality of slowly varying single-ended analog signals to be selectively coupled to the above mentioned GDADC24. As far as the present description is concerned, the expression slowly varying analog signal has to be interpreted with the meaning that the analog signal has a maximum frequency significantly lower than the operating frequency of the GPADC24or in general the operating frequency of the receiving circuit24. According to an embodiment, said maximum frequency is lower than 1/10 of the above mentioned operating frequency. According to a further embodiment, said maximum frequency is lower than 1/100 of the above mentioned operating frequency. According to a possible embodiment the above maximum frequency is 500 Hz.

According to an embodiment, the mobile terminal1comprises a circuit board5comprising a control and processing unit6coupled to the circuit system20, and more in particular to the GPADC24. The control and processing unit6is adapted to receive from the latter digital samples of the analog input signals and to process said signals for controlling the operation of the mobile terminal1. According to an exemplary embodiment, the control and processing unit6on the basis of the above mentioned digital samples is such to detect the status of an USB interface7of the mobile terminal1, to monitor the status of charge and the temperature of a battery2of the mobile terminal1, to monitor the status of an external accessory of the mobile terminal1, such for example an earphone or a battery charger removably connectable to a dedicated connection port3of the mobile terminal1. It is therefore clear that a plurality of input single-ended analog signal have to be selectively fed to the GPADC24. In general, in typical applications related to mobile terminals there is the need of coupling up to ten or fifteen input single-ended signals to the differential GPADC24. In general, such signals come from sources having relatively high output impedances.

As the general structure and the operation of a mobile terminal, such for example a mobile phone, are well known to a man skilled in the field, for sake of conciseness they will be not further detailed in the present description. On the contrary, the following description will be mainly focused on the circuit system20and in particular on the single-ended to differential buffer circuit21,22. It is important to remark the single-ended to differential buffer circuit21,22of the foregoing description can be also employed in systems and and/or devices different from a mobile terminal1, for example in products that contrary to mobile terminals don't have or require any remote connectivity, as it can be in general employed whenever there is the need of coupling at least one single-ended analog signal to a differential inputs receiving circuit.

FIG. 2shows a first embodiment of circuit system20comprising a single-ended to differential buffer circuit21,22adapted to couple one single-ended input analog signal Vinto a receiving circuit24with differential inputs, such as the GPADC24of the mobile terminal1ofFIG. 1. The input analog signal is a slowly varying analog signal. The particular example of buffer circuit21,22ofFIG. 2is adapted to couple only one single-ended input analog signal Vinto the GPADC20, but later in the description a different embodiment of circuit system will be also disclosed comprising a single-ended to differential buffer that is adapted to selectively couple a plurality of single-ended analog input signals to the same receiving circuit24.

With reference toFIG. 2, the single-ended to differential buffer circuit21,22comprises an output section22comprising a differential amplifier25having a first31and a second32input, a first41and a second42output. The first and second outputs are adapted to be connected to the receiving circuit24. According to the embodiment shown, the differential amplifier25is a resettable amplifier, to this end the output section22comprises a set, and in particular a couple, of controllable switches F2B. Such switches F2B are such to connect/disconnect the first input31to/from the first output41and to connect/disconnect the second input32to/from the second output42.

According to an actually preferred, but not for this reason limiting, embodiment the output section22further comprises a first and a second feedback capacitors CA1, CA2respectively connected between the first input31and the first output41and between the second input32and the second output42.

The single-ended to differential buffer circuit20, comprises an input section21comprising a first CS1and a second CS2switched capacitor, each adapted to sample the input analog signal Vin. In particular, the first switched capacitor CS1is adapted to sample the signal Vinand the second capacitor is adapted to sample the same signal as −Vin. InFIG. 2the input section21and the output section22have been shown separated by the dotted line23.

Each switched capacitor CS1, CS2has a first side p1′,p2′ and a second side p1″,p2″. The input section comprises a first51and second52input node for receiving respectively the input analog signal Vinand a reference voltage signal or ground. In the particular example shown inFIG. 2, the second input node52is connected to ground.

The first sides p1′, p2′ of the first and second switched capacitors CS1, CS2are controllably connectable/disconnectable to/from the first41and second42outputs of the differential amplifier25respectively. To this end, a set, and in particular a couple, of dedicated controllable switches F2C is provided in the input section21. The second sides p1″, p2″ of the first CS1and second CS2switched capacitors are controllably connectable/disconnectable to/from the first31and second32inputs of the differential amplifier25respectively. To this end, a set, and in particular a couple, of dedicated controllable switches F2A is provided in the input section21. Moreover, the second sides p1″, p2″ of the first and second switched capacitors CS1, CS2are controllably connectable/disconnectable to/from the second output42and the first output41respectively. To this end, a set, and in particular a couple, of dedicated controllable switches F3is provided in the input section21. It is important to observe that the sets of switches F2C and F3when are all in the closed state are such to connect each of the switched capacitors CS1, CS2between the first41and the second42output of the differential amplifier25.

According to the embodiment shown inFIG. 2, the first side p1′ of the first switched capacitor CS1is controllably connectable/disconnectable to/from the first input node51while the first side p2′ of the second switched capacitor CS2is controllably connectable/disconnectable to/from the second input node52. To this end, a set, and in particular a couple, of dedicated controllable switches F1B and F1A is provided in the input section21.

Moreover, according to the embodiment shown inFIG. 2, the second side p1″ of the first switched capacitor CS1is controllably connectable/disconnectable to/from the second input node52while the second side p2″ of the second switched capacitor CS2is controllably connectable/disconnectable to/from the first input node51. To this end, a set, and in particular a couple, of dedicated controllable switches F1A and F1B is provided in the input section21.

The single-ended to differential buffer circuit21,22is adapted to assume in sequence:

a sampling operating configuration in which each of the switched capacitors CS1, CS2is connected between the first input node51and the second input node52and therefore is adapted to be charged with an initial charge (switches F1A, F1B and F2B in the closed state, switches F2A, F2C and F3in the open state);

a storing operating configuration in which the first switched capacitor CS1is connected between the first input31and the first output41and in which the second switched capacitor CS2is connected between the second input32and the second output42(switches F2A and F2C in the closed state, switches F1A, F1B, F2B and F3in the open state);

a charge restoring configuration in which each of the switched capacitors CS1, CS2is connected between the first output41and the second output42in order to restore on said capacitors CS1, CS2the initial charge (switches F2C and F3in the closed state, and switches F1A, F1B and F2B in the open state).

With reference toFIGS. 2 and 3the operation of the above described single-ended to differential input buffer21,22will be described hereunder.

InFIG. 3T0indicates a time interval corresponding to an arbitrary initial condition. During interval T0the switched capacitors CS1, CS2sample the input signal Vin. In particular, CS1samples a voltage Vinand CS2samples the same voltage but as −Vin. The differential amplifier25is reset. During T0due to the voltages Vin, and −Vinthe switched capacitors CS1, CS2are charged to a given charge that we will indicate as “initial charge”. During T0switches F1A, F1B and F2B in the closed state while switches F2A, F2C and F3in the open state. If Vcmis the common mode voltage of the differential amplifier25, the output voltage Voof the amplifier25is Vo=Vo+−Vo−=Vcm−Vcm=0 V, where Vo+is the voltage of the first output41and Vo−is the voltage of the second output42.

Starting from the above described configuration during interval T0, at the beginning of interval T1switches F1A become open, and voltages Vinand −Vinremain stored on switched capacitors CS1and CS2respectively. In this way, signal dependent charge injection is avoided, at least at first order. The differential amplifier25is reset and the output voltage Voof the amplifier25is Vo=Vo+−Vo−=Vcm−Vcm=0 V.

Starting from the above described configuration during interval T1, at the beginning of interval T2switches F1B become open. Accordingly the switched capacitors CS1and CS2become fully floating. Voltages Vinand −Vinremain stored on switched capacitors CS1and CS2respectively. The differential amplifier25is reset and the output voltage Voof the amplifier25is Vo=Vo+−Vo−=Vcm−Vcm=0 V.

Starting from the above described configuration during interval T2, at the beginning of interval T3switches F2A become closed. Accordingly, the second sides p1″ and p2″ of the switched capacitors CS1and CS2are respectively connected to the first input31and the second input32of the differential amplifier25, such sides becoming therefore charged to Vcm. The differential amplifier25is reset and the output voltage Voof the amplifier25is Vo=Vo+−Vo−=Vcm−Vcm=0 V.

Starting from the above described configuration during interval T3, at the beginning of interval T4, switches F2B become open while switches F2C become closed. If all the capacitors CS1, CS2, CA1, CA2have the same capacitance the output voltage of the amplifier25is Vo=Vin. Without the capacitors CA1and CA2, which are optional, Vowould be 2*Vin. It is therefore clear that the feedback switches CA1, CA2perform a required attenuation, for example in the case in which the output voltage Vomight not be within the amplifier's output voltage range. During interval T4the output voltage Vocan be sampled by the differential GPADC24.

Starting from the above described configuration during interval T4, at the beginning of interval T5switches F2A become open and switches F3become closed. Each switched capacitor CS1, CS2is therefore connected between the first41and second42outputs of the differential amplifier25. This configuration is such to restore on switched capacitors CS1, CS2their initial charges.

Starting from the above described configuration during interval T5, at the beginning of interval T6switches F2C and F3become open, therefore the switched capacitors CS1, CS2become fully floating with the same initial charge that they had during interval T0(i.e. the charge determined by Vinon CS1and −Vinon CS2).

Starting from the above described configuration during interval T6, at the beginning of interval T7switches F1A and F2B become closed. The differential amplifier25is reset and the output voltage Vo of the amplifier25is Vo=Vo+-−Vo−=Vcm−Vcm=0 V.

Starting from the above described configuration during interval T7, at the beginning of interval T8switches F1B become closed. The single ended to differential buffer circuit21,22reaches therefore the same configuration of time period T0. Accordingly, the switched capacitors CS1and CS2are restored to their initial sampling configuration. The differential amplifier25is reset and the output voltage Voof the amplifier25is Vo=Vo+−Vo−=Vcm−Vcm=0 V.

It is clear from the above description of the operation of the single-ended to differential buffer circuit21,22, that if the analog input signal Vinis slowly varying, the amount of charge on the switched capacitors CS1and CS2is almost the same in the beginning and final configurations (corresponding respectively to the ones of time intervals T0and T8). Therefore, almost no charge transfer, i.e. current, is needed from the input signal Vin. This means that the single-ended to differential buffer circuit21,22is characterized by an high input impedance.

FIG. 5shows a partial view of a variant embodiment of the input section ofFIG. 2, in which the input section21ofFIG. 2has been replaced by a plurality of input sections21(1),21(2), . . . ,21(n)similar to the input section21ofFIG. 2, each dedicated to an associated input single-ended analog signal Vin(1), Vin(2), . . . , Vin(n)to be selectively coupled, one at time, to a same receiving circuit24with differential inputs. It is important to remark that said input sections21(1),21(2), . . . ,21(n)can be selectively and in a mutually exclusive way activated in order to cooperate with a same output section22similar to the one already described with reference toFIG. 2. In this way, it is advantageously possible to design a multi-input single-ended to differential buffer which, requiring only one shared differential amplifier25, does not require a significant increase in the occupied area compared to the single input embodiment.

With reference toFIGS. 3 and 4, it must be observed that the above description of the operation of the single-ended to differential buffer circuit21,22corresponds to the description of a method100for coupling at least a single-ended input analog signal Vin, and in particular a slowly varying signal, to a receiving circuit24with differential inputs, by means of:

an output section22comprising a differential amplifier25having a first31and second32input and a first41and second42output; and

an input circuit section21, associated to said single ended input analog signal Vin, comprising a first CS1and a second CS2switched capacitor.

The method100comprises in sequence the steps of:

Vin_Sam—time periods T0, T1, T2, T7(the latter as a preliminary period to the actual sampling operation), T8—sampling101the input signal Vinby controllably connecting the switched capacitors CS1, CS2between a first node51fed with the input signal Vinand a second node52fed with a reference voltage or connected to ground, the sampling step101being such to establish an initial charge on the switched capacitors CS1, CS2;

Vin_Hold—time periods T3and T4—connecting102the first switched capacitor CS1between the first input31and the first output41and connecting102the second switched capacitor CS2between the second input32and the second output42;

Ch_Rest—time periods T5, T6—restoring103the initial charge on switched capacitors CS1, CS2by connecting said capacitors between the first output41and the second42output.

As indicated inFIG. 4by the arrow110, after the restoring step103, the sampling101, connecting102and restoring step103can be cyclically performed.

a first operation of connecting the switched capacitors CS1, CS2to the second node52;

a second operation of connecting the switched capacitors CS1, CS2to the first node51;

a third operation of disconnecting the first and second switched capacitors CS1, CS2from nodes51,52leaving said switched capacitors CS1, CS2floating;

said first, second and third operations of the sampling step101being performed in sequence.

According to an embodiment, the above mentioned third operation comprises:

a first sub-operation of disconnecting the switched capacitors CS1, CS2from the second node52;

a second subsequent sub-operation of disconnecting said capacitors CS1, CS2from the first node51.

According to an embodiment, the connecting step102(Vin_hold) comprises a first operation of connecting the second sides p1″,p2″ of the switched capacitors CS1, CS2to the inputs31,32of the differential amplifier25and a second operation of connecting the first sides p1′, p2′ of said capacitors to the outputs41,42of the differential amplifier25. The first and second operations of the connecting step102are performed in sequence.

According to an embodiment, the charge restoring step103(Ch_Rest) comprises the operations of:

disconnecting the second side p1″ of the first switched capacitor CS1from the first input31and connecting it to the second output42;

disconnecting the second side p2″ of the second switched capacitor CS2from the second input32and connecting it to the first output41.

According to a variant embodiment, the method100is provided for selectively coupling a plurality of a single-ended input analog signals Vin(1), Vin(2), . . . , Vin(n)to the receiving circuit24. The input section21comprises a plurality of dedicated input sections21(1),21(2), . . . ,21(n)each associated to a corresponding input signal of said plurality. In this embodiment, the method100further comprises the step (not shown in the diagram ofFIG. 4), of selectively activating said dedicated input sections21(1),21(2), . . . ,21(n)in a mutually exclusive way in order to making them cooperate, one at time, with the same, and therefore temporally shared, output section22.

On the basis of the above disclosure, it can be seen how the objects of the present invention are fully reached. In particular, the above described buffer performs a single-ended to differential conversion, has a high input impedance and does not require the differential amplifier to be in the power ON state during the sampling step101(Vin_SAM). As already remarked, the multi-input embodiment is characterized by a relatively reduced area occupation.

Naturally, in order to satisfy contingent and specific requirements, a person skilled in the art may apply to the above-described single-ended to differential buffer many modifications and variations, all of which, however, are included within the scope of protection of the invention as defined by the following claims.