System and method of signal processing

An audio processor is disclosed and includes a sample rate converter and a digital phase-locked-loop module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of filters.

FIELD OF THE DISCLOSURE

The present disclosure is generally related to signal processing.

BACKGROUND

A signal processing system that experiences a change from a first data source input to a second data source input may result in an undesirable discontinuity in an output signal. As an example, when an audio signal is switched from a first source to a second source, the user may hear an undesirable pop or clicking sound. Hence there is a need for an improved system and method of signal processing.

DETAILED DESCRIPTION

In a particular embodiment, an audio processor is disclosed that includes a sample rate converter and a digital phase-locked-loop (DPLL) module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of digital filters.

In another embodiment, a system is disclosed that includes a first data source input, a second data source input, and a switch responsive to the first and second data source inputs. The system also includes a digital phase-locked-loop (DPLL) module including a phase accumulator and a sample rate converter (SRC) including a digital filter. The sample rate converter is responsive to SRC input data and responsive to the DPLL module. The phase accumulator is initialized with an initialized value based at least partially on a control value associated with the digital filter.

In another embodiment, a signal processing device is disclosed that includes a sample rate converter (SRC), a filter controller, and a digital phase locked loop (DPLL) module. The sample rate converter is adapted to receive an input signal and includes a plurality of interpolation filters and a fractional interpolator. The digital phase-locked loop (DPLL) module is configured to receive a system clock, a sample clock, a filter sequence address, and a source selection indicator. The digital phase-locked loop module is responsive to the filter controller and is configured to supply a rate control signal to the sample rate converter. The digital phase-locked loop module includes a phase accumulator having a phase accumulator initialization value determined based at least in part on the filter sequence address. The phase accumulator is configured to output a phase accumulator signal. The digital phase-locked loop module also includes a rate control module configured to input the phase accumulator signal, and to output the rate control signal.

In another embodiment, a method is disclosed that includes detecting a change in a data source from a first data source to a second data source. The method further includes determining a phase accumulator initialization value based on a filter sequence address of a filter receiving the data source as an input, wherein the filter sequence address includes a filter sequence value and a filter control sign bit. Additionally, the method includes initializing a phase accumulator of a digital phase locked loop (DPLL) module based on the phase accumulator initialization value and performing a sample rate conversion on data from the second data source using a sample rate value based on information received from the DPLL module.

Referring toFIG. 1, a particular embodiment of a signal processing system is illustrated and generally designated100. The system100includes a stereo demodulator106that is adapted to receive audio input signals, such as the analog audio input signal102, via an analog-to-digital converter (ADC)104. The stereo demodulator106provides a demodulated digital audio signal107to an audio processor108that outputs a processed signal114. The audio processor108provides the processed signal114to a source select switch116. In a particular embodiment, the source select switch116can also receive one or more digital input signals118from other sources. The source select switch116can output digital output signals122directly and can provide a switched audio signal120to the DAC converter124for conversion to an analog output signal126.

In a particular illustrative embodiment, an analog audio input signal102may be received from a source at the A/D converter104. The A/D converter104converts the analog audio input signal to a digital audio signal105and sends the digital audio signal105to the stereo demodulator106. In an illustrative embodiment, the stereo demodulator can demodulate the digital audio signal105, for example, by converting the frequency of the digital audio signal105to a frequency that the audio processor108can accept, and sends a demodulated signal107to the audio processor108.

In a particular embodiment, the audio processor108can include a digital phase-locked loop module (DPLL)110that communicates with a sample rate converter (SRC)112. The SRC112can include a plurality of digital filters that form a finite impulse response interpolation filter. For each sample of the demodulated digital audio signal107, the SRC112executes a filter sequence and provides filtered samples at a system sample rate to the source select switch116via the processed signal114. The DPLL110includes a phase accumulator having an initialization value that is determined based on a filter sequence address that includes a filter sequence value corresponding to a filter sequence state at a particular time. The filter sequence address can include, for example, contents of a state register of a filter control state machine associated with the plurality of digital filters of the SRC112.

In a particular embodiment, a change in the demodulated digital audio signal107, such as a change from a first demodulated signal to a second demodulated signal, may result in a change of signals received by the audio processor108and provided to the SRC112. The phase and sample rate of the second demodulated signal may not be the same as the phase and sample rate of the first demodulated signal. Therefore the initialization value associated with the phase accumulator of the DPLL110may be altered in response to the change of demodulated signals provided to the SRC112, for example, based on the filter sequence value sampled at a time with respect to a sample of the second demodulated signal. The DPLL module110can supply a control signal to the SRC112, where the control signal is determined at least in part by the altered phase accumulator initialization value. In response to receiving the control signal from the DPLL110, the SRC112can adjust an oversample rate, in order to reduce a phase error in the SRC112that may result from a change in the demodulated digital audio signal107. The reduction in phase error can reduce or eliminate popping, clicking or other undesirable sounds resulting from a change of audio signals.

Referring toFIG. 2, a second particular embodiment of a system to process an input signal is illustrated and generally designated200. A first source202and a second source204can be coupled to a switch206. In an illustrative embodiment, the first source202may be a source of a mono TV audio signal, and the second source204may be a source of a stereo TV audio signal. The switch206can be coupled to a sample rate converter (SRC)212. The switch206can also be coupled to a digital phase-locked loop module (DPLL)218that includes a phase accumulator. The DPLL module218and the SRC212can each be coupled to the other and to an output system222, such as a TV audio output device.

In a particular illustrative embodiment, the switch206can receive a first input signal203from the first source202and can provide data208corresponding to the first input signal203to the SRC212. In addition, the switch can provide a sample clock210to the DPLL218. In an illustrative embodiment, the DPLL module218can also receive a system clock224from the output system222. Based at least partially on the sample clock210and the output system clock224, the DPLL218can provide a rate control signal216to the SRC212.

In a particular embodiment, the data208provided to the SRC can indicate a change in an input signal from the first source signal203to a second source signal205provided by the second source204. The SRC212can produce the filter control value214based on an internal state of the SRC212evaluated at a time occurring subsequent to the change in the input signal from the first source signal203to the second source signal205, and can provide the filter control value214to the DPLL218. The DPLL218can determine a new phase accumulator initialization value based on the filter control value214corresponding to the second source signal205, and the DPLL218can send the rate control signal216to the SRC212. In a particular embodiment, the SRC212can adjust an oversample rate of the data208with respect to the system clock224provided to the DPLL218by the output system222. The adjustment of the oversample rate may result in a reduction of the phase error of the SRC212, thereby reducing audio clicking or popping sounds that may be present in the audio output due to a signal source change.

Referring toFIG. 3, a particular embodiment of a signal processing device is illustrated and generally designated300. The signal processing device300includes a sample rate converter (SRC)304coupled to a filter controller311and a digital phase-locked loop (DPLL) module332. The SRC304may include a plurality of interpolation filters306and a fractional interpolator310. In an illustrative embodiment, the plurality of interpolation filters306may include a finite impulse response (FIR) filter. The DPLL module332may include a phase accumulator326and a rate control module328. In a particular embodiment, the SRC304and the DPLL module332may be coupled to an output system314, such as an audio output device, which provides a system clock316to the DPLL module332. The fractional interpolator310may provide output samples313to the output system314at a system sample rate that is fixed with respect to the system clock316.

In a particular embodiment, the SRC304receives an input signal302. The plurality of interpolation filters306receive a filter control signal312from the filter controller311, which corresponds to a predetermined filter sequence to be applied at least once to each sample of the input signal302. The plurality of interpolation filters306provide filtered samples308to the fractional interpolator310at an oversample rate. The filter controller311also provides a filter sequence value324, a filter control sign bit322, and a too early signal320to the DPLL module332. The DPLL module332determines a phase accumulator initialization value based at least in part on the filter sequence value324. In an illustrative embodiment, the phase accumulator initialization value can be determined based at least partially on a filter sequence address that includes the filter sequence value324and the sign bit322.

In an illustrative embodiment, a source selection indicator318and sample clock319may be provided to the DPLL module332by one or more other sources. Alternatively, the source selection indicator318and the sample clock319may be derived from the input signal302. In a particular illustrative embodiment, the phase accumulator326may be adjusted in a predetermined sense at the oversample rate, and can be adjusted in a sense opposite to the predetermined sense at a subsequent time determined with respect to the sample clock319.

In a particular illustrative embodiment, the rate control module328of the DPLL module332may generate an oversample clock334at the oversample rate, based at least in part on the phase accumulator initialization value. The oversample clock334can also be based on a rate control value (not shown), which represents a number of oversample clock cycles to be generated for each system clock cycle. In a particular illustrative embodiment, the rate control value can have an integer part and a fractional part. The rate control value can be controlled by the rate control module328to reduce a phase error, as measured by the phase accumulator326.

The rate control module328of the DPLL module332can generate a fractional rate control signal330, which can include a fractional part of the rate control value. In a particular illustrative embodiment, the fractional rate control signal330can also be based on a sample time determined with respect to the sample clock319. The DPLL module332can provide the fractional rate control signal330to the fractional interpolator310of the SRC304.

In a particular illustrative embodiment, a change in the input signal302, such as a change from a first input signal to a second input signal, can be detected at the system300. The filter controller311determines a filter sequence value324based on a signal received from the second input signal and sends the filter sequence value324to the DPLL module332. Further, the filter controller311can send a filter control sign bit322and a too early signal320to the DPLL module332. The DPLL module332can determine a phase accumulator initialization value based on the filter sequence value324, the filter control sign bit322, the too early signal320, other data or signals, or any combination thereof.

In an illustrative embodiment, the phase accumulator initialization value may be determined based on the sign bit322concatenated with an inversion of the filter sequence value324to produce a 2's complement phase error value. The phase accumulator initialization value may be determined based on the 2's complement phase error value evaluated at a first time occurring subsequent to a change from a first input signal to a second input signal and the 2's complement phase error value evaluated at a next time subsequent to the change from the first input signal to the second input signal.

In a particular illustrative embodiment, the too early signal320can indicate that a phase error is too large because, for example, a first sample of the second input signal is received too soon after a last sample of the first input signal. The DPLL332can then wait for a subsequent sample of the second input signal before determining the filter sequence value324and the sign bit322to be used to determine the phase accumulator initialization value.

The DPLL module332can generate a rate control signal330and the oversample clock334, based at least in part on the phase accumulator initialization value corresponding to the second input signal. The DPLL module332can perform an adjustment of the oversample rate and send the rate control signal330and the oversample clock334to the SRC304. In a particular embodiment, the adjustment of the oversample rate may result in a reduction in a phase error of a sampled signal.

Referring toFIG. 4, an illustrative embodiment of a chart400illustrates Finite Impulse Response (FIR) filter sequence values. As illustrated, the chart400illustrates a plurality of filter sequence values402and a plurality of filter stages404-408. Chart400represents a complete filter sequence, which may be executed approximately once for each sample input to an interpolation filter module. Each filter sequence value402corresponds to a filter sequence410for one or more of the filter stages. During operation, the filter sequence value402progresses through a sequence from 0 to 15 as the filter sequences410of each of the filter stages404-408are executed.

Referring toFIG. 5, a particular embodiment of a method of processing a signal is illustrated. At block502, a change in a data source is detected. In an illustrative embodiment, a dedicated switch that receives an input command may detect the change in the data source. In another illustrative embodiment, a passive detection device may detect the change in the data source. In an illustrative embodiment, the data source may change from a first data source to a second data source, such as from a first TV audio source to a second TV audio source.

Proceeding to block504, a filter sequence value is determined for a plurality of interpolation filters within a sample rate converter (SRC). In a particular illustrative embodiment, the plurality of interpolation filters may include a finite impulse response (FIR) filter. Continuing to block506, a filter control sign bit is determined. Proceeding to block508, the filter sequence value is inverted, forming an inverted filter sequence value. Moving to block510, the filter control sign bit is concatenated with the inverted filter sequence value, producing a 2's complement phase error.

Proceeding to block512, a phase accumulator initialization value is set equal to the 2's complement phase error. Moving to block514, a phase accumulator is initialized. In a particular embodiment, the phase accumulator of a digital phase-locked loop (DPLL) module is initialized based on the phase accumulator initialization value. At block516, an oversample rate may be adjusted relative to a system rate within the sample rate converter, to reduce a phase error associated with the data from the second data source. The sample rate conversion on data from the second data source may use a sample rate value based on information received from the DPLL module. In a particular illustrative embodiment, the sample rate converter may receive a rate control signal from the DPLL module, the value of which may be based at least in part on an output of the phase accumulator. Moving to block518, a fractional interpolator produces output samples at the system rate. The method terminates at520.