Semiconductor devices including vertical channel transistors and methods of fabricating the same

Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0130810, filed on Dec. 20, 2010, in the Korean Intellectual Property Office (KIPO), the entire contents of which is incorporated herein by reference.

BACKGROUND

Example embodiments relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices including vertical transistors and methods of fabricating the same.

2. Description of Related Art

Semiconductor devices are very attractive in the electronic industry because of the relatively small size, multi-functional characteristics and/or low fabrication cost thereof. As the electronic industry becomes highly integrated, semiconductor devices have been more and more highly integrated. The line widths of the semiconductor devices have been gradually reduced to increase the integration density of the semiconductor devices. However, there may be some limitations in increasing the integration density of the semiconductor devices because new exposure techniques and/or high cost for the new exposure techniques are required in reduction of the line widths.

Transistors with a vertical channel have been proposed to increase the integration density of semiconductor devices. In the event that the transistors have a vertical channel, the source and drain of the respective transistors may be vertically stacked. Thus, planar areas that the transistors occupy may be reduced.

SUMMARY

Example embodiments of the inventive concepts include semiconductor devices with vertical transistors and methods of fabricating the same.

According to example embodiments, a method of fabricating a semiconductor device includes forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches in parallel extend in a direction. A gate dielectric layer is formed on upper inner sidewalls of the first trenches. A gate conductive layer filling the first trenches is formed on the substrate having the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars.

According to some example embodiments, the buried dielectric patterns may be formed using an oxidation process. Formation of the first trenches and the buried dielectric patterns may include forming upper trenches in the substrate, forming sacrificial spacers on inner sidewalls of the upper trenches, etching the substrate under the upper trenches using the sacrificial spacers as etching masks to form lower trenches, and applying an oxidation process to the substrate having the lower trenches to form the buried dielectric patterns. The sacrificial spacers may be removed after formation of the buried dielectric patterns, and the gate dielectric layer may be formed after removal of the sacrificial spacers. Alternatively, the sacrificial spacers may be removed prior to formation of the buried dielectric patterns, and the gate dielectric layer and the buried dielectric patterns may be simultaneously formed.

According to other example embodiments, formation of the first trenches and the buried dielectric patterns may include forming the first trenches in the substrate, depositing a dielectric layer filling the first trenches on the substrate including the first trenches, and etching the dielectric layer to form the buried dielectric patterns.

According to yet other example embodiments, the method may further include forming plug dielectric patterns in portions of the substrate under the second trenches, etching the substrate, the buried dielectric patterns and the plug dielectric patterns located under the second trenches to form interconnection trenches, forming lower dopant regions in lower portions of the active pillars, and forming buried interconnections in the interconnection trenches. Each of the lower dopant regions may be electrically connected to one of the pair of buried interconnections disposed at both sides of the lower dopant region. The method may further include forming separation dopant regions in the substrate located under the interconnection trenches.

The separation dopant regions may be simultaneously formed with the lower dopant regions, and each of the separation dopant regions may be connected to the pair of lower dopant regions located at both sides of each of the separation dopant regions. During formation of the second trenches, preliminary gate patterns filing the first trenches may be formed between the second trenches. In this case, the method may further include removing the preliminary gate patterns in ones selected from the first trenches to form gate patterns separated from each other, and forming word lines extending in the predetermined direction.

The gate patterns may fill non-selected ones of the first trenches, respectively. Each of the word lines may be electrically connected to the gate patterns which are arrayed in one row parallel to the predetermined direction. The method may further include forming upper dopant regions in upper portions of the active pillars, respectively, and forming data storage elements electrically connected to the upper dopant regions. The upper dopant regions may be upwardly spaced apart from the lower dopant regions.

According to still other example embodiments, a semiconductor device includes an active pillar upwardly protruding from a substrate, a lower dopant region and an upper dopant region disposed in the pillar, a gate electrode disposed on one sidewall of the active pillar, and a gate dielectric layer between the one sidewall of the active pillar and the gate electrode. The lower dopant region and the upper dopant region are vertically separated from each other. The lower dopant region is spaced apart from another sidewall of the active pillar.

According to some example embodiments, the semiconductor device may further include a buried interconnection electrically connected to the lower dopant region. A top surface of the buried interconnection may be located at a lower level than a top surface of the lower dopant region. The semiconductor device may further include a separation dopant region formed in the substrate under the buried interconnection. The separation dopant region may be doped with dopants having the same conductivity type as the lower dopant region. The separation dopant region may be connected to the lower dopant region.

According to other example embodiments, the semiconductor device may further include a void disposed in the gate electrode and a void-filling dielectric pattern filling at least a portion of the void. According to yet other example embodiments, the semiconductor device may further include a buried dielectric pattern disposed under the gate electrode. The buried dielectric pattern may include an oxide material formed by an oxidation process.

According to at least one embodiment, a method of fabricating a semiconductor device includes forming at least one fin pattern by forming a plurality of first trenches extending in parallel in a substrate, forming a plurality of buried dielectric patterns filling lower regions of the first trenches, forming a gate dielectric layer on upper sidewalls inside the first trenches, forming a gate conductive layer filling the first trenches on the substrate after the forming a gate dielectric layer, and forming a plurality of active pillars by patterning the gate conductive layer, the gate dielectric layer and the fin pattern to form second trenches crossing the first trenches.

According to at least one example embodiment, a semiconductor device includes an active pillar protruding from a substrate, a lower dopant region and an upper dopant region in the pillar, the lower dopant region vertically separated from the upper dopant region and separated from a first sidewall of the active pillar, a gate electrode on a second sidewall of the active pillar, and a gate dielectric layer between the second sidewall and the gate electrode.

According to at least one embodiment, a method of fabricating a semiconductor device includes forming a semiconductor fin in a substrate layer, forming a gate dielectric layer on the semiconductor fin, forming a gate conductive layer on the gate dielectric layer, forming a plurality of active pillars by removing a portion of the semiconductor fin, the gate dielectric layer and the gate conductive layer, and forming source and drain regions in the active pillars.

DETAILED DESCRIPTION

FIG. 1is a schematic circuit diagram illustrating vertical transistors of semiconductor devices according to example embodiments of the inventive concepts. Referring toFIG. 1, semiconductor devices according to example embodiments may include a plurality of transistor-pairs. For example, the respective semiconductor devices may include a first transistor-pair TRP1and a second transistor-pair TRP2. Each of the first and second transistor-pairs TRP1and TRP2may include a first vertical channel transistor FET1and a second vertical channel transistor FET2. Gate electrodes of the first and second vertical channel transistors FET1and FET2of the first transistor-pair TRP1may be electrically connected to a first word line WL1. The first and second vertical channel transistors FET1and FET2of the first transistor-pair TRP1may share the first word line WL1. Gate electrodes of the first and second vertical channel transistors FET1and FET2of the second transistor-pair TRP2may share a second word line WL2. The first and second word lines WL1and WL2may be independently controlled.

First source/drain terminals of the first vertical channel transistors FET1may be electrically connected to a first buried wiring BW1, and first source/drain terminals of the second vertical channel transistors FET2may be electrically connected to a second buried wiring BW2. The first and second buried wirings BW1and BW2may be independently controlled. The word lines WL1and WL2may cross the buried wirings BW1and BW2. The first source/drain terminal of the first vertical channel transistor FET1in the first transistor-pair TRP1may share the first buried wiring BW1with the first source/drain terminal of the first vertical channel transistor FET1in the second transistor-pair TRP2adjacent to the first transistor-pair TRP1.

The first source/drain terminal of the second vertical channel transistor FET2in the first transistor-pair TRP1may share the second buried wiring BW2with a first source/drain terminal of a second vertical channel transistor FET2in a third transistor-pair (not shown) adjacent to the first transistor-pair TRP1. According to at least one example embodiment, the first and second buried wirings BW1and BW2may correspond to bit lines. The first and second vertical channel transistors FET1and FET2in each of the transistor-pairs TRP1and TRP2may share a single word line WL1or WL2and may be electrically connected to a pair of buried wirings BW1and BW2, respectively. The adjacent two transistor-pairs TRP1and TRP2may share one of the buried wirings BW1and BW2.

According to at least one example embodiment, first data storage elements DS1may be electrically connected to second source/drain terminals of the first vertical channel transistors FET1, respectively. Second data storage elements DS2may be electrically connected to second source/drain terminals of the second vertical channel transistors FET2, respectively. One of the first vertical channel transistors FET1and the first data storage element DS1connected thereto may constitute a unit memory cell. One of the second vertical channel transistors FET2and the second data storage element DS2connected thereto may constitute another unit memory cell.

Each of the first and second vertical channel transistors FET1and FET2may be used as a switching device of the respective unit memory cells. Each of the first and second transistor-pairs TRP1and TRP2and the first and second data storage elements DS1and DS2connected thereto may constitute a pair of unit memory cells. The data storage elements DS1and DS2may be realized in various forms. For example, each of the data storage elements DS1and DS2may include a capacitor, a magnetic tunnel junction (MTJ) pattern and/or a variable resistor.

The semiconductor devices according to example embodiments may include a volatile memory device and/or a non-volatile memory device. The semiconductor devices according to example embodiments may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a magnetic random access memory (MRAM) device, a phase changeable random access memory (PRAM) device and/or a resistive random access memory (RRAM) device. However, the data storage elements DS1and DS2are not limited to the above memory devices. The data storage elements DS1and DS2may be realized in many different forms.

FIGS. 2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,12A,13A and14A are perspective diagrams illustrating methods of fabricating semiconductor devices according to example embodiments of the inventive concepts.FIGS. 2B,3B,4B,5B,6B,7B,8B,9B,10B,11B,12B,13B and14B include cross-sectional views ofFIGS. 2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,12A,13A and14A, respectively. Referring toFIGS. 2A and 2B, hard mask patterns102may be formed on a substrate100(e.g., a semiconductor substrate). The hard mask patterns102may be in parallel and extend in a first direction. The hard mask patterns102may be separated from each other in a second direction perpendicular to the first direction. The first and second directions may be parallel with a top surface of the substrate100. For example, the first direction may correspond to an x-axis direction (e.g., a direction parallel to an x-axis) inFIG. 2A, and the second direction may correspond to a y-axis direction (e.g., a direction parallel to a y-axis) inFIG. 2A. Each of the hard mask patterns102may include, for example, an oxide material, a nitride material and/or an oxynitride material. Each of the hard mask patterns102may be formed of a single-layered material or a multi-layered material. According to at least one example embodiment, the hard mask patterns102may include an oxide material.

The substrate100may be etched using the hard mask patterns102as etch masks. Upper trenches105may be formed in the substrate100. The upper trenches105may extend in the first direction. A sacrificial spacer layer (not shown) may be conformally formed on the substrate with the upper trenches105. The sacrificial spacer layer may be etched back until bottom surfaces of the upper trenches105are exposed, and may form sacrificial spacers107on both inner sidewalls of the upper trenches105. The sacrificial spacer layer may be formed of a single-layered material or a multi-layered material. For example, the sacrificial spacer layer may include an oxide material, a nitride material and/or an oxynitride material. According to at least one example embodiment, the sacrificial spacer layer may include an oxide layer and a nitride layer which are sequentially stacked. Each of the sacrificial spacers107may be formed of a double-layered material layer.

Referring toFIGS. 3A and 3B, the substrate100under the upper trenches105may be etched using the hard mask patterns102and the sacrificial spacers107as etch masks, forming lower trenches109under the upper trenches105. One of the lower trenches109and the upper trench105thereon may constitute a first trench110. The first trenches110may define fin patterns PT. Each of the fin patterns PT may correspond to a portion of the substrate100, which is located between adjacent two first trenches110. The fin patterns PT may also extend in the first direction. The fin patterns PT may be separated from each other in the second direction.

Referring toFIGS. 4A and 4B, a plurality of buried dielectric patterns112may be formed in lower regions of the first trenches110, respectively. For example, a first oxidation process may be applied to the substrate inside the first trenches110, thereby forming the buried dielectric patterns112. According to at least one example embodiment, the first oxidation process may be applied to the substrate including the sacrificial spacers107. Upper inner sidewalls of the first trenches110(e.g., sidewalls defining the first trenches110) may not be further oxidized, as illustrated inFIGS. 4A and 4B. This may be because the upper inner sidewalls of the first trenches110may be covered with the sacrificial spacers107. The buried dielectric patterns112may be formed to with a confined shape in the lower regions of the first trenches110. The first oxidation process may include a thermal oxidation process, a plasma oxidation process, a thermal/plasma oxidation process and/or a radical oxidation process.

Referring toFIGS. 5A and 5B, the sacrificial spacers107may be removed after formation of the buried dielectric patterns112. The upper inner sidewalls of the first trenches110may be exposed. A gate dielectric layer115may be formed on the upper inner sidewalls of the first trenches110. The gate dielectric layer115may be formed using a thermal oxidation technique. However, a method of forming the gate dielectric layer115is not limited to the thermal oxidation technique. The gate dielectric layer115may be formed using, for example, a chemical vapor deposition (CVD) technique and/or an atomic layer deposition (ALD) technique. The gate dielectric layer115may be formed of a single-layered material or a multi-layered material.

A gate conductive layer120may be formed on the substrate including the gate dielectric layer115. The gate conductive layer120may fill the first trenches110on the buried dielectric patterns112. According to at least one example embodiment, the gate conductive layer120may include a doped semiconductor layer. For example, the gate conductive layer120may be a doped silicon layer, a doped germanium layer and/or a doped silicon-germanium layer. However, the gate conductive layer120is not limited to the above doped semiconductor layers. For example, the gate conductive layer120may include at least one of a conductive metal nitride layer (e.g., a titanium nitride layer, a tantalum nitride layer and/or the like), a transition metal layer (e.g., a titanium layer, a tantalum layer and/or the like) and a metal layer (e.g., a tungsten layer and/or the like).

Referring toFIGS. 6A and 6B, a capping dielectric layer123may be formed on the gate conductive layer120. The capping dielectric layer123may be a single-layered material or a multi-layered material. For example, the capping dielectric layer123may include an oxide material, a nitride material and/or an oxynitride material. The capping dielectric layer123, the gate conductive layer120, the hard mask patterns102, fin patterns PT and the buried dielectric patterns112may be patterned to form second trenches125. The second trenches125may cross the first trenches110and may be in parallel. The second trenches125may extend in the second direction. A plurality of active pillars ACT may be defined by formation of the second trenches125. Each of the active pillars ACT may correspond to a portion of one of the fin patterns PT. The active pillars ACT may relatively protrude from the substrate100upwardly (e.g., may be protrusions of the substrate100). According to at least one example embodiment, each of the active pillars ACT may be a square pillar with four sidewalls. The active pillars ACT may be two-dimensionally arrayed along rows and columns in a plan view. The active pillars ACT may be doped with dopants of a first conductivity type.

Formation of the second trenches125may form preliminary gate patterns120a. Capping dielectric patterns123may be formed on the preliminary gate patterns120a. The preliminary gate patterns120amay correspond to portions of the gate conductive layer120. The preliminary gate patterns120amay extend in parallel with the second trenches125. The preliminary gate patterns120amay be separated from each other by the second trenches125. The preliminary gate patterns120amay include portions that fill the first trenches110. A bottom surface of the respective second trenches125may include first portions formed of the substrate100and second portions formed of the buried dielectric patterns112. According to at least one example embodiment, the first and second portions of the bottom surface of the respective second trenches125may be located at a lower level than bottom surfaces of the preliminary gate patterns120ain the first trenches110. According to at least one example embodiment, the first and second portions of the bottom surface of the respective second trenches125may be higher than bottom surfaces of the buried dielectric patterns112. The preliminary gate patterns120aand the second trenches125may be alternately and repeatedly arrayed in the first direction. The capping dielectric patterns123may correspond to portions of the capping dielectric layer.

Referring toFIGS. 7A and 7B, an oxidation preventing layer127may be conformally formed on the substrate including the second trenches125. For example, the oxidation preventing layer127may be formed to a substantially uniform thickness on inner surfaces of the second trenches125and on the capping dielectric patterns123. The oxidation preventing layer127may be formed of a single-layered material or a multi-layered material. For example, the oxidation preventing layer127may be formed of an oxide layer, a nitride layer and/or an oxynitride layer. According to at least one example embodiment, the oxidation preventing layer127may include an oxide layer formed using an oxidation process and a nitride layer formed using a deposition process which may be sequentially stacked.

A mask layer130filling the second trenches125may be formed on the oxidation preventing layer127. For example, the mask layer130may include a spin on hard mask (SOH) layer. However, the mask layer130is not limited to the SOH layer. The mask layer130may include another layer which is different from an SOH layer.

Referring toFIGS. 8A and 8B, the mask layer130may be patterned to form openings132. The openings132may expose portions of the oxidation preventing layer127located on the bottom surfaces of the second trenches125. A width of the openings132and the second trenches125may be in the first direction. The width of the respective openings132may be greater than that of the respective second trenches125. The bottom surface of the respective second trenches125may include the first portions formed of the substrate100and the second portions formed of the buried dielectric patterns112. The first portions and the second portions of the bottom surface of the respective second trenches125may be alternately and repeatedly arrayed in the second direction.

The openings132may be over portions selected from the first portions of the second trenches125. According to at least one example embodiment, the selected first portions may include odd-numbered first portions in the bottom surface of one of the pair of adjacent second trenches125and even-numbered first portions in the bottom surface of the other one of the pair of adjacent second trenches125. The openings132formed on the pair of adjacent second trenches125may be arrayed in a zigzag pattern in the second direction. Non-selected first portions of the bottom surfaces of the second trenches125(e.g., surfaces at the bottom of the second trenches125) may be covered with the oxidation preventing layer127.

The oxidation preventing layer127exposed by the openings132may be etched to expose the selected first portions of the bottom surfaces of the second trenches125. In this case, the oxidation preventing layer127formed on the inner sidewalls of the second trenches125and exposed by the openings132may still exist. The exposed first portions may be etched using the mask layer130with the openings132as an etch mask, thereby forming recessed regions135.

Referring toFIGS. 9A and 9B, the mask layer130may be removed after formation of the recessed regions135. A plurality of plug dielectric patterns137may be formed in the recessed regions135. The plug dielectric patterns137may be formed to fill the recessed regions135. For example, the plug dielectric patterns137may be formed using a second oxidation process which may be applied to the substrate exposed by the recessed regions135. During the second oxidation process, the substrate100covered with the oxidation preventing layer127and the hard mask patterns102may not be oxidized. The active pillars ACT may not be oxidized due to the presence of the oxidation preventing layer127during the second oxidation process. The plug dielectric patterns137may be laterally grown because the plug dielectric patterns137is formed using the second oxidation process (e.g., may consume some of the substrate100). A width of the plug dielectric patterns137in the first direction may be greater than that of the recessed regions135in the first direction. The plug dielectric patterns137may be under a bottom surface of the oxidation prevent layer127formed on the sidewalls of the second trenches125.

Referring toFIGS. 10A and 10B, the oxidation preventing layer127may be etched back to expose the bottom surfaces of the second trenches125. Sidewall spacers127amay be formed on both inner sidewalls of the respective second trenches125. The sidewall spacers127amay correspond to portions of the oxidation preventing layer127that exist after the oxidation preventing layer127is etched back. The capping dielectric patterns123may be exposed after formation of the sidewall spacers127a.

The substrate100, the plug dielectric patterns137, the buried dielectric patterns112under the second trenches125may be etched using the sidewall spacers127aand the capping dielectric patterns123as etch masks, forming interconnection trenches140. The interconnection trenches140may be formed under the second trenches125, respectively. The interconnection trenches140may be in parallel and extend in the second direction. Each of the interconnection trenches140may include a first region exposing the substrate100, a second region exposing the buried dielectric patterns112, and a third region exposing the plug dielectric patterns137.

The first regions of the interconnection trenches140may correspond to regions which are formed by etching the non-selected first portions under the second trenches125, and the second regions of the interconnection trenches140may correspond to regions which may be formed by etching the second portions under the second trenches125. The third regions of the interconnection trenches140may correspond to regions which are formed by etching the plug dielectric patterns137. The cross-sectional view ofFIG. 10Btaken along line10B-II-10B-II′ ofFIG. 10Aillustrates the first region of one of the interconnection trenches140and the third regions of the others of the interconnection trenches140. The cross sectional view ofFIG. 10Btaken along line10B-IV-10B-IV′ ofFIG. 10Aillustrates the second regions of the interconnection trenches140.

The third regions of the interconnection trenches140may be formed in the plug dielectric patterns137. Lower sidewalls of the active pillars ACT adjacent to the third regions of the interconnection trenches140may be protected by the plug dielectric patterns137. According to at least one example embodiment, lower sidewalls of the active pillars ACT adjacent to the first regions of the interconnection trenches140may be exposed by the first regions.

Dopants of a second conductivity type may be provided into the substrate100through the interconnection trenches140, forming lower dopant regions145in lower portions of the active pillars ACT. During formation of the lower dopant regions145, the dopants of the second conductivity type may be provided into the lower portions of the active pillars ACT through both the inner sidewalls of the first regions of the interconnection trenches140. In this case, the plug dielectric patterns137may act as a blocking layer that prevents the dopants of the second conductivity type from being provided into the lower portions of the active pillars ACT adjacent to the third regions of the interconnection trenches140. The dopants of the second conductivity type may not be provided into the active pillars ACT adjacent to the third regions.

While the lower dopant regions145are formed, separation dopant regions147may be formed under the bottom surfaces of the first regions of the interconnection trenches140, respectively. The pair of lower dopant regions145formed at both sides of each of the first regions of the interconnection trenches140may be connected to each other through the separation dopant region147therebetween. The pair of lower dopant regions145may contact both the inner sidewalls of each of the first regions, respectively, and the separation dopant regions147may be formed under the first regions of the interconnection trenches140.

Each of the first regions of the interconnection trenches140may be surrounded by the pair of adjacent lower dopant regions145and the separation dopant region147between the pair of adjacent lower dopant regions145. The pair of adjacent lower dopant regions145and the separation dopant region147therebetween may be connected to each other and constitute a single body. The separation dopant regions147may be simultaneously formed with the lower dopant regions145. The dopants of the second conductivity type may be injected into the lower portions of the active pillars ACT using, for example, an ion implantation process. In this case, the dopant ions may be implanted by a tilted implantation process and/or a non-tilted implantation process. According to at least one example embodiment, the dopants of the second conductivity type may be injected using, for example, a plasma doping process.

According to at least one example embodiment, the lower dopant region145may be horizontally separated from one sidewall of the active pillar ACT. For example, the lower dopant region145may be horizontally separated from the one sidewall of the active pillar ACT, which is adjacent to the third region of the interconnection trench140. The active pillar ACT may be between the pair of interconnection trenches140. The active pillar ACT may include a first sidewall and a second sidewall facing each other. The first and second sidewalls of the active pillar ACT may extend in the second direction. The first sidewall of the active pillar ACT may be adjacent to the first region of one of the pair of interconnection trenches140, and the second sidewall of the active pillar ACT may be adjacent to the third region of the other interconnection trench140. In this case, the lower dopant region145may be horizontally separated from the second sidewall of the active pillar ACT.

Example embodiments are not limited to the above example embodiments. In other example embodiments, the lower dopant regions145may be in contact with all sidewalls of the active pillars ACT.

Buried interconnections150may be formed in the interconnection trenches140. For example, an interconnection conductive layer (not shown) filling the interconnection trenches140may be formed on the substrate with the lower dopant regions145and the separation dopant regions147. The interconnection conductive layer may be etched to form the buried interconnections150. According to at least one example embodiment, top surfaces of the buried interconnections150may be located at a lower level than top surfaces of the lower dopant regions145. The buried interconnections150may be electrically connected to the lower dopant regions145. Each of the buried interconnections150may be in contact with the lower dopant regions145formed at both sides of the first regions of the respective interconnection trenches140.

Each of the buried interconnections150may be in contact with the separation dopant regions147under the respective interconnection trenches140. The first regions of the interconnection trenches140may be surrounded by the lower dopant regions145and the separation dopant regions147, and the lower dopant regions145and the separation dopant regions147may be of a different conductivity type than the substrate100. The buried interconnections150may be electrically isolated from the substrate100. The buried interconnections150in the third regions of the interconnection trenches140may be insulated from the lower dopant regions145adjacent to the third regions due to the presence of the plug dielectric patterns137. Each of the lower dopant regions145may be connected to one of the buried interconnections150. The buried interconnections150may include at least one of a metal layer (e.g., a tungsten layer), a conductive metal nitride layer (e.g., a titanium nitride layer and/or a tantalum nitride layer) and a transition metal layer (e.g., a titanium layer and/or a tantalum layer).

Referring toFIGS. 11A and 11B, a first filling dielectric layer153filling the second trenches125may be formed on the substrate including the buried interconnections150. The first filling dielectric layer153may include an oxide layer, a nitride layer and/or an oxynitride layer. According to at least one embodiment, the first filling dielectric layer153may be a nitride layer. The first filling dielectric layer153, the capping dielectric patterns123and the preliminary gate patterns120amay be patterned to form gate patterns120b. Each of the preliminary gate patterns120amay include portions filling the first trenches110. While the preliminary gate patterns120aare patterned, some portions of each of the preliminary gate patterns120amay be removed. The preliminary gate patterns120ain some of the first trenches110may be selectively removed while the preliminary gate patterns120aare patterned. The gate patterns120bmay fill only the non-selected first trenches110of all the first trenches110. The gate patterns120bmay be separated from each other.

Each of the gate patterns120bfilling the non-selected first trenches110may be disposed between the pair of active pillars ACT which are adjacent to each other in the second direction. Each of the gate patterns120bmay extend to cover top surfaces of the pair of active pillars ACT which are adjacent to each other in the second direction. The first trenches110adjacent to the gate patterns120bin the second direction may correspond to the selected first trenches110where the preliminary gate patterns120aare removed. The gate patterns120bat two sides of each of the second trenches125may be arrayed zigzag in the second direction. A second filling dielectric layer155may be formed to fill the selected first trenches110on the substrate including the gate patterns120b. The second filling dielectric layer155may be, for example, an oxide layer, a nitride layer and/or an oxynitride layer.

Referring toFIGS. 12A and 12B, the second filling dielectric layer155, the first filling dielectric layer153and the capping dielectric patterns123may be planarized until top surfaces of the gate patterns120bare exposed. First filling dielectric patterns153aand second filling dielectric patterns155amay be formed. The first filling dielectric patterns153amay fill the second trenches125, and the second filling dielectric patterns155amay fill the selected first trenches110where the preliminary gate patterns120aare removed.

Referring toFIGS. 13A and 13B, an upper conductive layer160and a gate capping layer163may be sequentially formed on the substrate including the first and second filling dielectric patterns153aand155a. The upper conductive layer160may be in contact with the gate patterns120b. The upper conductive layer160may be formed of a single-layered material layer or a multi-layered material layer. The upper conductive layer160may include a conductive layer of low resistivity. For example, the upper conductive layer160may include a conductive metal nitride layer (e.g., a titanium nitride layer and/or a tantalum nitride layer), a transition metal layer (e.g., a titanium layer and/or a tantalum layer), a metal layer (e.g., a tungsten layer and/or an aluminum layer) and/or a metal-semiconductor compound layer (e.g., a metal silicide layer). According to at least one example embodiment, the upper conductive layer160may include a semiconductor layer doped with dopants. The gate capping layer163may be formed of a single-layered dielectric layer or a multi-layered dielectric layer. For example, the gate capping layer163may include an oxide layer, a nitride layer and/or an oxynitride layer.

Referring toFIGS. 14A and 14B, the gate capping layer163, the upper conductive layer160and the gate patterns120bmay be patterned to form gate patterns extending in the first directions. Each of the gate patterns may include a gate electrode GE, a word line WL and gate capping pattern163awhich may be sequentially stacked. The word lines WL and the gate capping patterns163amay extend in the first direction. Each of the word lines WL may correspond to a portion of the upper conductive layer160. While the upper conductive layer160and the gate patterns120bare patterned, the gate patterns120bover the top surfaces of the active pillars ACT may be removed. The gate electrodes GE may be formed. Each of the gate electrodes GE may be disposed between the pair of adjacent active pillars ACT.

Dopants of the second conductivity type may be injected into upper portions of the active pillars ACT to form upper dopant regions165. The upper dopant regions165may be formed in the upper portions of the active pillars ACT. The upper dopant regions165may be vertically spaced apart from the lower dopant regions145. The active pillars ACT between the upper dopant regions165and the lower dopant regions145may correspond to channel bodies.

Each of the gate electrodes GE may correspond to the gates of the first and second vertical channel transistors FET1and FET2of each of the first and second transistor-pairs TRP1and TRP2illustrated inFIG. 1. Each of the gate electrodes GE may correspond to a common gate electrode that two vertical channel transistors share. The lower dopant regions145may correspond to the first source/drain terminals of the first and second vertical channel transistors FET1and FET2ofFIG. 1, and the upper dopant regions165may correspond to the second source/drain terminals of the first and second vertical channel transistors FET1and FET2ofFIG. 1. The word lines WL may correspond to the word lines WL1and WL2ofFIG. 1, and the buried interconnections150may correspond to the buried wirings BW1and BW2.

Referring toFIGS. 15A and 15B, Gate spacers167may be formed on both sidewalls of the word lines WL. Data storage elements DS may be formed on the substrate including the gate spacers167. The data storage elements DS may be electrically connected to the upper dopant regions165, respectively.

According to example embodiments including methods of fabricating semiconductor devices, the second trenches125may be formed after formation of the gate conductive layer120filling the first trenches110. The gate electrodes GE vertically extending on the sidewalls of the pillars may have reproducibility. Width variation of the gate electrodes GE may be minimized and/or reduced.

According to example embodiments including methods of fabricating semiconductor devices, the lower dopant regions145may be formed after formation of the gate dielectric layer115and the gate conductive layer120. The thermal budget with respect to the lower dopant regions145may be minimized and/or reduced. For example, the gate dielectric layer115may be formed using a thermal oxidation process. In this case, the lower dopant regions145may be free from a heat budget during formation of the gate dielectric layer115(e.g., the lower dopant regions145may not yet exist). As a result, diffusion of impurities into the lower dopant regions145may be significantly suppressed and/or reduced.

According to at least one example embodiment, each of the lower dopant regions145may be in contact with one sidewall of the respective active pillars ACT and may be horizontally spaced apart from the other sidewall of the respective active pillars ACT. The channel bodies in the active pillars ACT may be electrically connected to the substrate100through the portions of the active pillars ACT between the lower dopant regions145and the other sidewalls of the active pillars ACT. As a result, the channel bodies may be prevented from being electrically floated or a floating body effect may be reduced.

FIG. 15Ais a perspective diagram illustrating semiconductor devices according to some example embodiments of the inventive concepts.FIG. 15Bis a cross-sectional view taken along lines15B-I-15B-I′,15B-II-15B-II′,15B-III-15B-III′ and15B-IV-15B-IV′ ofFIG. 15A. Semiconductor device according to example embodiments may be described with reference toFIGS. 15A and 15B. The structural features of the semiconductor device according to some example embodiments may include features described with reference toFIGS. 2A-14B.

Referring toFIGS. 15A and 15B, a plurality of active pillars ACT may be on a substrate100. A configuration of each of the active pillars ACT may be a configuration in which the active pillars ACT upwardly protrude from the substrate100. The active pillars ACT may be two dimensionally arrayed along rows and columns in a plan view. The rows may be parallel to a first direction and the columns may be parallel to a second direction. The first and second directions may correspond to an x-axis direction and a y-axis direction inFIG. 15A, respectively. The active pillars ACT may be defined by first trenches110in parallel and extending in the first direction, and second trenches125in parallel and extending in the second direction to cross the first trenches110.

Lower dopant regions145and upper dopant regions165may be disposed in lower portions and upper portions of the active pillars ACT, respectively. The lower dopant regions145may be vertically spaced apart from the upper dopant regions165. Gate electrodes GE may be on one sidewall of each of the active pillars ACT, and a gate dielectric layer115may be between the gate electrodes GE and the active pillars ACT. Each of the gate electrodes GE may be between a pair of active pillars ACT which may be adjacent to each other in the second direction. A pair of vertical channel transistors including the pair of adjacent active pillars ACT may share any one of the gate electrodes GE. The gate electrodes GE in two adjacent columns may be arrayed in a zigzag pattern in the second direction. A plurality of buried dielectric patterns112may be disposed under the gate electrodes GE. Each of the buried dielectric patterns112may include an oxide material layer (e.g., formed by an oxidation process).

A plurality of plug dielectric patterns137may be under each of the second trenches125. A plurality of buried interconnections150may be in interconnection trenches140under the second trenches125. Each of the buried interconnections150may be in the substrate100and the plug dielectric patterns137which are located under the respective second trenches125. Each of the interconnection trenches140may correspond to a region where the substrate100and the plug dielectric patterns137under the second trench125are etched. The buried interconnections150may extend in the second direction.

A pair of active pillars ACT arrayed in the second direction may be between the pair of adjacent buried interconnections150, and one of the gate electrodes GE may be between the pair of active pillars ACT. In this case, one of the pair of adjacent buried interconnections150may be electrically connected to the lower dopant region145of one of the pair of active pillars ACT, and the other of the pair of adjacent buried interconnections150may be electrically connected to the lower dopant region145of another of pair of active pillars ACT.

Separation dopant regions147may be under portions of each of the buried interconnections150. One of the separation dopant regions147may be under the pair of adjacent lower dopant regions145. The buried interconnections150may be electrically isolated from the substrate100due to the presence of the lower dopant regions145and the separation dopant regions147. The pair of adjacent lower dopant regions145contacting both sidewalls of the respective buried interconnections150may be electrically connected to each other through the separation dopant region147between the pair of adjacent lower dopant regions145. The lower dopant regions145may be the same conductivity type as the separation dopant regions147.

According to at least one example embodiment, each of the lower dopant regions145may be horizontally spaced apart from another sidewall of the respective active pillars ACT. For example, first and second sidewalls of the respective active pillars ACT may extend in the second direction and face each other. Each of the lower dopant regions145may be in contact with the first sidewall of the respective active pillars ACT and may be horizontally spaced apart from the second sidewall of the respective active pillars ACT. A channel body between the lower dopant region145and the upper dopant region165may be electrically connected to the substrate100through a portion of the active pillar ACT between the lower dopant region145and the second sidewall of the active pillar ACT.

The channel body may be prevented from being electrically floated and/or a floating body effect may be reduced. The gate electrode GE may be on the one sidewall of the respective active pillars ACT. One sidewall of the respective active pillars ACT may extend in the first direction. The one sidewall of the respective active pillars ACT, which the gate electrode GE is on, may be perpendicular to the first and second sidewalls of the respective active pillars ACT.

First filling dielectric patterns153amay fill the second trenches125. Second filling dielectric patterns155amay fill regions between the active pillars ACT which are adjacent to each other in the second direction. The regions may correspond to empty spaces where the gate electrodes GE are not formed. Each column with the active pillars ACT arrayed in the second direction may include the gate electrodes GE and the second filling dielectric patterns155a. In each column, the gate electrodes GE and the second filling dielectric patterns155amay be alternately and repeatedly arrayed in the second direction. Word lines WL may be on the gate electrodes GE. The word lines WL may cross over the buried interconnections150. The gate electrodes GE arrayed in one row may be electrically connected to each other through one of the word lines WL.

A plurality of data storage elements DS may be electrically connected to the upper dopant regions165. The data storage elements DS may be electrically connected to the upper dopant regions165through contact plugs169. According to at least one example embodiment, each of the data storage elements DS may include a capacitor. For example, each of the data storage elements DS may include a first electrode170, a second electrode175and a capacitor dielectric layer (not shown) between the first and second electrodes170and175.

The data storage elements DS are not limited to capacitors. The data storage elements DS may be realized in different forms. According to at least one example embodiment, each of the data storage elements DS may include a phase change material. The phase change material may be transformed into one of a plurality of states with different resistivity values. The phase change material, for example, may include at least one of tellurium and selenium which correspond to chalcogenide elements. According to at least one example embodiment, each of the data storage elements DS may include a magnetic tunnel junction (MTJ) pattern. According to at least one example embodiment, each of the data storage elements DS may include a variable resistor whose electrical resistance varies according to the presence or absence of filaments. For example, each of the data storage elements DS may include a transition metal oxide material.

FIGS. 16A,17A and18A are perspective diagrams illustrating methods of fabricating semiconductor devices according to other example embodiments of the inventive concepts.FIGS. 16B,17B and18B include cross-sectional diagrams ofFIGS. 16A,17A and18A, respectively. Methods of fabricating a semiconductor device according to example embodiments illustrated inFIGS. 16A-18Bmay be similar to example embodiments described with reference toFIGS. 2A-15B. The same components as described in the first embodiment may be indicated by the same reference numerals. For the purpose of ease and convenience in explanation, the descriptions to the same components as in the first embodiment may be omitted or briefly mentioned.

Referring toFIGS. 16A and 16B, hard mask patterns102may be in parallel and formed on a substrate100. The hard mask patterns102may be formed to extend in a first direction. The substrate100may be etched using the hard mask patterns102as etch masks, forming upper trenches105. Sacrificial spacers107amay be formed on inner sidewalls of the upper trenches105, respectively. A width of the sacrificial spacers107amay be greater than the width of the sacrificial spacers107described with respect toFIGS. 2A-15B. The upper trenches105may extend in the first direction. The upper trenches105may be separated from each other in a second direction perpendicular to the first direction. The first direction and the second direction may correspond to the x-axis direction and the y-axis direction ofFIG. 16A, respectively.

The substrate100under the upper trenches105may be etched using the hard mask patterns102and the sacrificial spacers107a, thereby forming lower trenches109′ under the upper trenches105. A width of the lower trenches109′ may be less than that of the lower trenches109described with respect toFIGS. 2A-15B. The lower trench109′ and the upper trench105, which are vertically aligned, may constitute a single first trench110′. Referring toFIGS. 17A and 17B, the sacrificial spacers107amay be removed. All inner walls of the upper trenches105and the lower trenches109′ may be exposed.

Referring toFIGS. 18A and 18B, an oxidation process may be applied to the substrate where the sacrificial spacers107aare removed. Buried dielectric patterns112afilling lower regions of the first trenches110′ may be formed. While the buried dielectric patterns112aare formed, gate dielectric layer115may be formed on inner sidewalls of upper regions of the first trenches110′. The buried dielectric patterns112aand the gate dielectric layer115may be simultaneously formed during the oxidation process. A width W1of the upper portions of the buried dielectric patterns112amay be in the second direction.

The width W1of the buried dielectric patterns112amay be equal to or less than twice a width W2of the gate dielectric layer115. The buried dielectric patterns112amay completely fill the lower regions of the first trenches110′. The oxidation process may be, for example, a thermal oxidation process. A gate conductive layer120filling the first trenches110′ may be formed on the substrate including the gate dielectric layer115and the buried dielectric patterns112a. Subsequent processing may be performed by, for example, using the same or similar methods as described with reference toFIGS. 5A-15B.

The buried dielectric patterns112aand the gate dielectric layer115may be simultaneously formed using a single step of an oxidation process. The fabrication process of the semiconductor device may be simplified. A heat budget of the semiconductor device may be minimized and/or reduced to realize a high and/or improved reliability semiconductor device.

FIG. 19Ais a perspective diagram illustrating semiconductor devices according to still other example embodiments of the inventive concepts.FIG. 19Bincludes cross-sectional diagrams ofFIG. 19A. Referring toFIGS. 19A and 19B, word lines WL extending in a first direction may be connected to upper portions of the gate electrodes GE. A gate dielectric layer115may be between the gate electrodes GE and the active pillars ACT. Buried dielectric patterns112amay be under the gate electrodes GE. A width of the buried dielectric patterns112amay be equal to or less than twice a thickness of a width of the gate dielectric layer115. The second direction may be perpendicular to the first direction. The buried dielectric patterns112amay be formed of the same dielectric layer as the gate dielectric layer115. For example, the buried dielectric patterns112aand the gate dielectric layer115may be formed of an oxide material layer. The buried dielectric patterns112aand the gate dielectric layer115may include an oxide material layer which is formed using an oxidation process.

According to at least one example embodiment, the width of the buried dielectric patterns112amay be less than a width of the gate electrodes GE. A width of lower portions of the active pillars ACT in the second direction may be greater than a width of upper portions of the active pillars ACT in the second direction. Each of the gate electrodes GE may be on one sidewall the upper portion of each of the active pillars ACT. The semiconductor device illustrated inFIGS. 19A and 19Bmay include gate spacers167and data storage elements DS described with reference toFIGS. 15A and 15B. InFIGS. 19A and 19B, the gate spacers and the data storage elements are omitted for ease and convenience of explanation.

FIGS. 20A,21A and22A are perspective diagrams illustrating methods of fabricating semiconductor devices according to yet still other example embodiments of the inventive concepts.FIGS. 20B,21B and22B include cross-sectional diagrams ofFIGS. 20A,21A and22A, respectively. The same components as described with reference toFIGS. 2A-19Bmay be indicated by the same reference numerals. Referring toFIGS. 20A and 20B, hard mask patterns102may be in parallel and formed on a substrate100. The hard mask patterns102may be formed to extend in a first direction. The substrate100may be etched using the hard mask patterns102as etch masks, forming first trenches110awhich define a plurality of fin patterns PT. The fin patterns PT and the first trenches110amay extend in parallel with the first direction. The fin patterns PT and the first trenches110amay be alternately and repeatedly arrayed in a second direction crossing the first direction.

A buried dielectric layer111filling the first trenches110amay be formed on the substrate including the first trenches110a. The buried dielectric layer111may be formed of a single-layered material layer or a multi-layered material layer. For example, the buried dielectric layer111may be formed of an oxide layer, a nitride layer and/or an oxynitride layer. According to at least one example embodiment, the buried dielectric layer111may include an oxide layer. The buried dielectric layer111may be deposited using, for example, a chemical vapor deposition (CVD) process and/or an atomic layer deposition (ALD) process.

Referring toFIGS. 21A and 21B, the buried dielectric layer111may be etched to form buried dielectric patterns111ain the first trenches110a. The buried dielectric patterns111amay fill lower regions of the first trenches110a. Upper regions of the first trenches110amay be empty spaces after formation of the buried dielectric patterns111a. The buried dielectric layer111may be etched using, for example, an etch-back process. According to at least one example embodiment, the buried dielectric layer111may be etched using, for example, a wet etch process. According to at least one example embodiment, while the buried dielectric layer111is etched, the hard mask patterns102may be removed to expose top surfaces of the fin patterns PT.

Referring toFIGS. 22A and 22b, a gate dielectric layer115may be formed on inner sidewalls of the upper regions of the first trenches110a. The gate dielectric layer115may be formed using, for example, an oxidation process (e.g., a thermal oxidation process). A gate conductive layer120may be formed to fill the first trenches110a. Subsequent processes may be performed using the same or similar methods as described with reference toFIGS. 5A-15B.

According to at least one embodiment, in the event that the top surfaces of the fin patterns PT are exposed, the gate dielectric layer115may be formed on not only the inner sidewalls of the upper regions of the first trenches110abut also the top surfaces of the fin patterns PT.

FIG. 23Ais a perspective diagram illustrating semiconductor devices according to still yet other example embodiments of the inventive concepts.FIG. 23Bincludes cross-sectional diagrams ofFIG. 23A. Referring toFIGS. 23A and 23B, a void VD may be formed inside at least one of the gate electrodes GE. In this case, at least a portion of the void VD may be filled with a void-filling dielectric pattern25. According to at least one example embodiment, the void-filling dielectric pattern25may include a first portion20and a second portion22. The first portion20of the void-filling dielectric pattern25may include the same material as the sidewall spacers127awhich are on the inner sidewalls of the second trenches125.

The second portion22of the void-filling dielectric pattern25may include the same material as the first filling dielectric patterns153afilling the second trenches125. However, example embodiments are not so limited. For example, the void-filling dielectric pattern25may include only the first portion20. In the event that the void-filling dielectric pattern25includes only the first portion20, the first portion20of the void-filling dielectric pattern25may include the same material as at least a portion of the sidewall spacer127a.

For example, when the gate conductive layer120ofFIGS. 5A and 5Bare formed, the void VD may be formed inside the gate conductive layer120in the first trenches110. In this case, after formation of the second trenches125illustrated inFIGS. 6A and 6B, the void VD may be exposed by the second trenches125. The void VD may be filled with the oxidation preventing layer127ofFIGS. 7A and 7B. According to at least one example embodiment, the void VD may be filled with the oxidation preventing layer127ofFIGS. 7A and 7Bas well as the first filling dielectric layer153ofFIGS. 11A and 11B. The first portion20of the void-filling dielectric pattern25may include the same material as the sidewall spacers127a, and the second portion22may include the same material as the first filling dielectric patterns153a.

According to at least one example embodiment, when at least one of the gate electrodes GE include the void VD, the void VD may be partially or completely filled with the void-filling dielectric pattern25. Even though the void VD is formed, the void-filling dielectric pattern25in the void VD may suppress and/or reduce movement of the void VD. As a result, high and/or improved reliability semiconductor devices may be realized.

The semiconductor devices disclosed with respect toFIGS. 1-23Bmay be encapsulated using various packaging techniques. For example, the semiconductor devices according to example embodiments may be encapsulated using a package on package (POP) technique, a ball grid arrays (BGAs) technique, a chip scale packages (CSPs) technique, a plastic leaded chip carrier (PLCC) technique, a plastic dual in-line package (PDIP) technique, a die in waffle pack technique, a die in wafer form technique, a chip on board (COB) technique, a ceramic dual in-line package (CERDIP) technique, a plastic quad flat package (PQFP) technique, a thin quad flat package (TQFP) technique, a small outline package (SOIC) technique, a shrink small outline package (SSOP) technique, a thin small outline package (TSOP) technique, a thin quad flat package (TQFP) technique, a system in package (SIP) technique, a multi chip package (MCP) technique, a wafer-level fabricated package (WFP) technique and/or a wafer-level processed stack package (WSP) technique. The package according to example embodiments may include a controller and/or a logic device which controls the semiconductor device.

FIG. 24is a schematic block diagram illustrating electronic products including semiconductor devices according to example embodiments of the inventive concepts. Referring toFIG. 24, an electronic product1300according to example embodiments may include a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless telephone, a mobile phone, a digital music player, and/or a wireless and/or cable electronic equipment. The electronic product1300may include a controller1310, an input/output (I/O) unit1320, a memory1330and a wireless interface1340which communicate with each other through the data bus1350. The I/O unit1320may include, for example, a keypad, a keyboard and/or a display unit.

The controller1310, for example, may include a microprocessor, a digital signal processor, a microcontroller and/or the like. The memory1330may store commands which are executed by the controller1310. The memory1330may store user's data. The memory1330may include at least one of semiconductor devices with vertical channel transistors according to example embodiments of the inventive concepts, for example, as described with respect toFIGS. 1-23B. The electronic product1300may use the wireless interface1340to transmit electrical data to a wireless communication network that communicates using radio frequency (RF) signals and/or to receive electrical data from the wireless communication network. For example, the wireless interface1340may include an antenna and/or a wireless transceiver. The electronic product1300may be used in a communication interface protocol, for example, a third generation communication system. The third generation communication system may include CDMA, GSM, NADC, E-TDMA, WCDAM and/or CDMA2000.

FIG. 25is a schematic block diagram illustrating memory systems including semiconductor devices according to example embodiments of the inventive concepts. Referring toFIG. 25, semiconductor devices according to example embodiments may be used to realize a memory system1400. The memory system1400may include a memory1410for storing large capacity data and a memory controller1420. The memory controller1420may control the memory device1410to read out the data stored in the memory device1410and/or write new data into the memory device1410in response to signals from the host1430.

The memory controller1420may generate address mapping tables to transform addresses provided by the host1430, a mobile device and/or a computer system into a physical address of the memory device1410. The memory device1410may include at least one of semiconductor devices with vertical channel transistors according to example embodiments of the inventive concepts, for example, as described with respect toFIGS. 1-23B.