DETECTION APPARATUS AND DISPLAY APPARATUS

A detection apparatus includes a substrate, a plurality of first electrode blocks provided on the substrate, each of the first electrode blocks including a plurality of first electrodes, and a first electrode selection circuit configured to select at least one of the first electrode blocks in a time-division manner in a first detection period and select at least one of the first electrodes in a second detection period. The least one of the first electrode blocks selected by the first electrode selection circuit is supplied with a first drive signal in the first detection period, and the at least one of the first electrodes selected by the first electrode selection circuit is supplied with a second drive signal, a voltage level of the second drive signal different from a voltage level of the first drive signal in the second detection period.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Japanese Application No. 2017-192177, filed on Sep. 29, 2017, the contents of which are incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to a detection apparatus and a display apparatus.

2. Description of the Related Art

There have recently been demands for performing fingerprint detection for personal identification by a capacitance method, for example. To perform fingerprint detection, electrodes having a smaller area are used than those used to detect contact of hands and fingers. Even if signals are obtained from such smaller electrodes, satisfactory detection sensitivity can be provided by code division multiplexing drive. Code division multiplexing drive is a driving method of selecting a plurality of drive electrodes simultaneously and supplying drive signals having the phases determined based on a predetermined code to the respective selected drive electrodes (refer to Japanese Patent Application Laid-open Publication No. 2014-199605 (JP-A-2014-199605).

In the display apparatus with a touch detection function described in JP-A-2014-199605, shift registers are provided for respective drive electrode blocks. The shift registers operate to sequentially supply selection signals to the respective drive electrode blocks. As a result, the drive electrode blocks are selected one by one. With this configuration, however, an increase in the number of electrodes may possibly increase the circuit size of the shift registers and the other components. The size and the required resolution for an object to be detected differ between touch detection and fingerprint detection. Consequently, drive circuits used for touch detection may possibly fail to perform fingerprint detection satisfactorily.

SUMMARY

A detection apparatus according to one embodiment of the present disclosure includes

a substrate, a plurality of first electrode blocks provided on the substrate, each of the first electrode blocks including a plurality of first electrodes, and a first electrode selection circuit configured to select at least one of the first electrode blocks in a time-division manner in a first detection period and select at least one of the first electrodes in a second detection period. The least one of the first electrode blocks selected by the first electrode selection circuit is supplied with a first drive signal in the first detection period, and the at least one of the first electrodes selected by the first electrode selection circuit is supplied with a second drive signal, a voltage level of the second drive signal different from a voltage level of the first drive signal in the second detection period.

A detection apparatus according to one embodiment of the present disclosure includes a substrate, a plurality of the first electrode blocks provided on the first substrate, the first electrode blocks including a first one of the first electrode blocks and a second one of the first electrode blocks, each of the first electrode blocks including a plurality of first electrodes, and the first electrodes including a first one of the first electrode and a second one of the first electrode, and a first electrode selection circuit provided on the substrate and including a first selection circuit configured to provide a first selection signal having a phase determined for each of the first electrodes included in one first electrode block and a second selection circuit configured to provide a second selection signal for each of the first electrode blocks. The first selection circuit supplies same signal of the first selection signal to a first one of the first electrode included in the first one of the first electrode block and a first one of the first electrode included in the second one of the first electrode block, the second selection circuit supplies a same signal of the second selection signal to the first one of the first electrodes and the second one of the first electrodes included in the first one of the first electrode block, the detection apparatus supplies the first drive signal having a same first voltage to each of the first electrode blocks in a time-division manner based on the first selection signal and the second selection signal in a first detection period, and the detection apparatus supplies, to the first electrodes, a second drive signal having a phase determined for each of the first electrodes based on the first selection signal and the second selection signal and having a second voltage different from the first voltage in a second detection period.

A display apparatus according to one embodiment of the present disclosure includes the detection apparatus described above, and a display panel configured to display an image. The detection apparatus is provided on the display panel.

A display apparatus according to one embodiment of the present disclosure includes the detection apparatus described above, and a display panel configured to display an image. The first electrodes are common electrodes configured to supply a common potential to a plurality of pixels in the display panel.

DETAILED DESCRIPTION

Exemplary aspects (embodiments) to embody the present disclosure are described below in greater detail with reference to the accompanying drawings. The contents described in the embodiments are not intended to limit the present disclosure. Components described below include components easily conceivable by those skilled in the art and components substantially identical therewith. Furthermore, the components described below may be appropriately combined. What is disclosed herein is given by way of example only, and appropriate modifications made without departing from the spirit of the present disclosure and easily conceivable by those skilled in the art naturally fall within the scope of the disclosure. To simplify the explanation, the drawings may possibly illustrate the width, the thickness, the shape, and other elements of each component more schematically than the actual aspect. These elements, however, are given by way of example only and are not intended to limit interpretation of the present disclosure. In the present specification and the figures, components similar to those previously described with reference to previous figures are denoted by like reference numerals, and detailed explanation thereof may be appropriately omitted.

First Embodiment

FIG. 1is a plan view of a display apparatus including a detection apparatus according to a first embodiment of the present disclosure.FIG. 2is a sectional view along line II-IF inFIG. 1. As illustrated inFIGS. 1 and 2, a display apparatus100according to the present embodiment has a display region AA, a frame region GA, and a detection region FA. The display region AA is a region for displaying an image on a display panel30. The frame region GA is a region positioned outside the display region AA. The detection region FA is a region for detecting unevenness on the surface of a finger or the like in contact with or in proximity to the display apparatus100. The detection region FA overlaps the whole surface of the display region AA.

As illustrated inFIG. 2, the display apparatus100according to the present embodiment includes a cover member101, a detection apparatus1, and the display panel30. The cover member101is a plate-like member having a first surface101aand a second surface101bopposite to the first surface101a. The first surface101aof the cover member101serves as a detection surface that detects unevenness on the surface of a finger Fin or the like in contact with or in proximity to the display apparatus100and as a display surface that displays an image on the display panel30. The display panel30and a sensor10of the detection apparatus1are provided on the second surface101bside of the cover member101. The cover member101protects the sensor10and the display panel30and is provided to cover them. The cover member101is a glass substrate or a resin substrate, for example.

The cover member101, the sensor10, and the display panel30do not necessarily have a rectangular shape in planar view. The cover member101, the sensor10, and the display panel30may have a circular shape, an elliptical shape, or a deformed shape obtained by removing part of the outer shapes described above. The cover member101, the sensor10, and the display panel30may have different outer shapes. For example, the cover member101may have a circular shape, and the sensor10and the display panel30may have a regular polygonal shape. The cover member101does not necessarily have a flat plate shape. The display apparatus100may be a curved surface display having a curved surface in which the display region AA has a curved surface or in which the frame region GA is bent toward the display panel30, for example.

As illustrated inFIGS. 1 and 2, a decorative layer110is provided in the frame region GA on the second surface101bof the cover member101. The decorative layer110is a colored layer having light transmittance lower than that of the cover member101. The decorative layer110can prevent wiring, circuits, and other components provided overlapping the frame region GA from being visually recognized by an observer. While the decorative layer110is provided on the second surface101bin the example illustrated inFIG. 2, it may be provided on the first surface101a. The decorative layer110is not limited to a single layer and may have a multilayered structure including a plurality of layers.

The detection apparatus1includes the sensor10that detects unevenness on the surface of the finger Fin or the like in contact with or in proximity to the first surface101aof the cover member101. As illustrated inFIG. 2, the sensor10of the detection apparatus1is provided on the display panel30. In other words, the sensor10is provided between the cover member101and the display panel30and overlaps the display panel30when viewed in a direction perpendicular to the first surface101a. The sensor10is coupled to a flexible printed circuit board76. The flexible printed circuit board76can output detection signals received from the sensor10to the outside.

One surface of the sensor10is bonded to the cover member101with an adhesive layer71interposed therebetween. The other surface of the sensor10is bonded to a polarizing plate35of the display panel30with an adhesive layer72interposed therebetween. The adhesive layer71is an optical clear resin (OCR) or a liquid optically clear adhesive (LOCA) serving as a liquid UV-curable resin, for example. The adhesive layer72is an optical clear adhesive (OCA), for example.

The display panel30includes a first substrate31, a second substrate32, a polarizing plate34, and the polarizing plate35. The polarizing plate34is provided under the first substrate31. The polarizing plate35is provided on the second substrate32. The first substrate31is coupled to a flexible printed circuit board75. Liquid crystal display elements are provided between the first substrate31and the second substrate32to serve as a display layer. In other words, the display panel30is a liquid crystal panel. The display panel30is not limited thereto and may be an organic light-emitting diode (OLED), for example.

As illustrated inFIG. 2, the sensor10is disposed closer to the cover member101than the display panel30in a direction perpendicular to the second surface101bof the cover member101. This configuration can reduce the distance between detection electrodes for fingerprint detection and the first surface101aserving as a detection surface compared with a case where the detection electrodes are integrated with the display panel30, for example. Consequently, the display apparatus100including the detection apparatus1according to the present embodiment can improve the detection performance.

The following describes the configuration of the detection apparatus1in greater detail.FIG. 3is a block diagram of an exemplary configuration of the detection apparatus according to the first embodiment. As illustrated inFIG. 3, the detection apparatus1includes the sensor10, a detection controller11, a first electrode selection circuit15, a detection electrode selection circuit16, and a detector40.

The sensor10performs detection based on second drive signals Vtx2supplied from the first electrode selection circuit15by code division multiplexing drive (hereinafter, referred to as CDM drive). In other words, the sensor10selects a plurality of first electrodes Tx (refer toFIG. 5) simultaneously by operations of the first electrode selection circuit15. The first electrode selection circuit15supplies the second drive signals Vtx2having the phases determined based on a predetermined code to the respective selected first electrodes Tx. The sensor10detects unevenness on the surface of the finger Fin or a hand in contact with or in proximity to the detection apparatus1based on a mutual capacitance method, thereby detecting the shape of a fingerprint or a palm print.

The sensor10can also detect the position of the finger Fin or the like in contact with or in proximity to the detection apparatus1based on first drive signals Vtx1supplied from the first electrode selection circuit15by time division multiplexing drive (hereinafter, referred to as TDM drive). In TDM drive, the sensor10scans first electrode blocks BK each including a plurality of first electrodes Tx one by one, thereby performing detection on the whole detection region FA.

The detection controller11is a circuit that supplies control signals to the first electrode selection circuit15, the detection electrode selection circuit16, and the detector40to control their operations. The detection controller11includes a driver11aand a clock signal output unit11b. The driver11asupplies a power source voltage Vdd to the first electrode selection circuit15. The detection controller11supplies various control signals Vctr1to the first electrode selection circuit15based on clock signals supplied from the clock signal output unit11b.

The first electrode selection circuit15selects a plurality of first electrodes Tx simultaneously based on the various control signals Vctr1. The first electrode selection circuit15supplies the first drive signals Vtx1or the second drive signals Vtx2to the selected first electrodes Tx. The first electrode selection circuit15changes the state of selecting the first electrodes Tx, whereby the sensor10can perform a plurality of detection mode, that is, a first detection mode M1, a second detection mode M2, a third detection mode M3, and a fourth detection mode M4(refer toFIGS. 8 to 11). The first electrode selection circuit15includes a first electrode drive circuit170and a buffer166, which will be described later.

The detection electrode selection circuit16is a switch circuit that selects a plurality of second electrodes Rx (refer toFIG. 5) simultaneously. The detection electrode selection circuit16performs CDM drive based on second electrode selection signals Vhsel supplied from the detection controller11. As a result, the detection electrode selection circuit16selects a plurality of second electrodes Rx.

The detector40is a circuit that determines whether a touch is made at a fine pitch based on the control signals supplied from the detection controller11and on first detection signals Vdet1and second detection signals Vdet2supplied from the sensor10in CDM drive. The detector40includes a detection signal amplifier42, an analog/digital (A/D) converter43, a signal processor44, a coordinate extractor45, a storage46, and a detection timing controller47. The detection timing controller47controls the detection signal amplifier42, the A/D converter43, the signal processor44, and the coordinate extractor45such that they operate synchronously with one another based on the control signals supplied from the detection controller11. In the following description, the first detection signals Vdet1and the second detection signals Vdet2are simply referred to as detection signals Vdet when they need not be distinguished from each other.

The sensor10supplies the first detection signals Vdet1and the second detection signals Vdet2to the detection signal amplifier42. The detection signal amplifier42amplifies the first detection signals Vdet1and the second detection signals Vdet2. The A/D converter43converts analog signals output from the detection signal amplifier42into digital signals. A circuit having the functions of at least the detection signal amplifier42and the A/D converter43may be provided as an analog front end circuit (hereinafter, referred to as an AFE circuit), which will be described later.

The signal processor44is a logic circuit that determines whether a touch is made on the sensor10based on the output signals from the A/D converter43. The signal processor44receives the first detection signals Vdet1and the second detection signals Vdet2from the first electrodes Tx via the detection electrode selection circuit16and calculates third detection signals Vdet3. The signal processor44receives the calculated third detection signals Vdet3and performs decoding on them based on a predetermined code.

The detector40determines whether a touch is made based on the control signals supplied from the detection controller11and the detection signals Vdet supplied from the sensor10in TDM drive. In TDM drive, the signal processor44receives the detection signals Vdet from the first electrodes Tx via the detection electrode selection circuit16. The signal processor44performs processing of extracting a signal (absolute value |ΔV|) of difference between the detection signals Vdet caused by a finger. The signal processor44compares the absolute value |ΔV| with a predetermined threshold voltage. If the absolute value |ΔV| is lower than the threshold voltage, the signal processor44determines that an external proximity object is in a non-contact state. By contrast, if the absolute value |ΔV| is equal to or higher than the threshold voltage, the signal processor44determines that an external proximity object is in a contact state.

The storage46temporarily stores therein the calculated third detection signals Vdet3. The storage46is a random access memory (RAM), a read only memory (ROM), or a register circuit, for example.

The coordinate extractor45calculates the touch panel coordinates based on the signal of difference between the detection signals and outputs the obtained touch panel coordinates as sensor output Vo. The coordinate extractor45may output the decoded signals as the sensor output Vo without calculating the touch panel coordinates.

The detection apparatus1performs capacitance touch detection. The following describes mutual capacitance touch detection performed by the detection apparatus1according to the present embodiment with reference toFIG. 4.FIG. 4is a diagram for explaining mutual capacitance touch detection.FIG. 4also illustrates a detection circuit.

As illustrated inFIG. 4, a capacitance element C1includes a pair of electrodes, that is, a drive electrode E1and a detection electrode E2facing each other with a dielectric D interposed therebetween. The capacitance element C1generates fringe lines of electric force extending from ends of the drive electrode E1to the upper surface of the detection electrode E2besides lines of electric force (not illustrated) formed between the facing surfaces of the drive electrode E1and the detection electrode E2. A first end of the capacitance element C1is coupled to an alternating-current (AC) signal source (drive signal source), and a second end thereof is coupled to a voltage detector DET. The voltage detector DET is an integration circuit included in the detector40illustrated inFIG. 3, for example.

The AC signal source applies an AC rectangular wave Sg at a predetermined frequency (e.g., a frequency of the order of several kilohertz to several hundred kilohertz) to the drive electrode E1(first end of the capacitance element C1). An electric current corresponding to the capacitance value of the capacitance element C1flows through the voltage detector DET. The voltage detector DET converts fluctuations in the electric current depending on the AC rectangular wave Sg into fluctuations in the voltage.

When capacitance C2formed by a finger is in contact with the detection electrode E2or comes closer to the detection electrode E2close enough to consider it in contact therewith, the fringe lines of electric force between the drive electrode E1and the detection electrode E2are blocked by the conductor (finger). As a result, the capacitance element C1acts as a capacitance element having a capacitance value smaller than that in a non-contact state as the capacitance C2comes closer to the detection electrodes E2.

The amplitude of the voltage signals output from the voltage detector DET becomes smaller as unevenness or the like on the finger Fin approaches the contact state compared with the non-contact state. The absolute value |ΔV| of the voltage difference varies depending on an effect of an object to be detected in contact with or in proximity to the detection electrode E2. The detector40determines unevenness or the like on the finger Fin based on the absolute value |ΔV|. The detector40compares the absolute value |ΔV| with the predetermined threshold voltage, thereby determining whether the object to be detected is in the non-contact state or in the contact state or a proximity state. The detector40thus can perform mutual capacitance touch detection. The “contact state” includes a state where a finger is in contact with the detection surface or in proximity to the detection surface close enough to consider it in contact therewith. The “non-contact state” includes a state where a finger is neither in contact with the detection surface nor in proximity to the detection surface close enough to consider it in contact therewith.

The following describes the configuration of the first electrodes Tx and the second electrodes Rx in the detection apparatus1.FIG. 5is a plan view of the detection apparatus according to the first embodiment.FIG. 6is an enlarged plan view of part of the first electrodes and the second electrodes.FIG. 7is a sectional view along line VII-VII′ inFIG. 6.

As illustrated inFIG. 5, the detection apparatus1includes a sensor substrate21and a plurality of first electrodes Tx and second electrodes Rx provided on the sensor substrate21. The sensor substrate21is a translucent glass substrate that enables visible light to pass therethrough. Alternatively, the sensor substrate21may be a translucent resin substrate or resin film made of a resin, such as polyimide. The sensor10is a translucent sensor.

The first electrodes Tx extend in a first direction Dx and are arrayed in a second direction Dy. The second electrodes Rx extend in the second direction Dy and are arrayed in the first direction Dx. The second electrodes Rx extend in a direction intersecting the first electrodes Tx in planar view. The second electrodes Rx are coupled to a flexible printed circuit board76provided on a short side of the frame region GA on the sensor substrate21via frame wiring (not illustrated). The first electrodes Tx and the second electrodes Rx are provided in the detection region FA. The first electrodes Tx are made of a translucent conductive material, such as indium tin oxide (ITO). The second electrodes Rx are made of a metal material, such as aluminum or an aluminum alloy. Alternatively, the first electrodes Tx may be made of a metal material, and the second electrodes Rx may be made of ITO. The use of the second electrodes Rx made of a metal material can reduce resistance on the detection signals Vdet.

The first direction Dx is a direction in a plane parallel to the sensor substrate21and is a direction parallel to one side of the detection region FA, for example. The second direction Dy is a direction in a plane parallel to the sensor substrate21and is a direction orthogonal to the first direction Dx. The second direction Dy does not necessarily orthogonally intersect the first direction Dx. In the present specification, the “planar view” indicates a view seen in a direction perpendicular to the sensor substrate21.

Capacitance is formed at the intersections of the second electrodes Rx and the first electrodes Tx. To perform a mutual capacitance touch detection operation, the first electrode selection circuit15selects a plurality of first electrodes Tx in the sensor10and supplies the first drive signals Vtx1or the second drive signals Vtx2simultaneously to the selected first electrodes Tx. The second electrodes Rx output the detection signals Vdet corresponding to changes in capacitance caused by unevenness on the surface of a finger or the like in contact with or in proximity to the detection apparatus1. The detection apparatus1thus performs fingerprint detection. Alternatively, the second electrodes Rx output the detection signals Vdet corresponding to changes in capacitance caused by the finger or the like in contact with or in proximity to the detection apparatus1. The detection apparatus1thus performs touch detection.

As illustrated inFIG. 5, various circuits, such as the first electrode selection circuit15and the detection electrode selection circuit16, are provided in the frame region GA on the sensor substrate21. The first electrode selection circuit15includes a first selection circuit151, a second selection circuit152, a third selection circuit153, and a first electrode block selection circuit154. The configuration is given by way of example only. At least part of the various circuits may be included in a detection integrated circuit (IC) mounted on the flexible printed circuit board76. Alternatively, at least part of the various circuits may be provided on an external control substrate. The first selection circuit151, the second selection circuit152, the third selection circuit153, and the first electrode block selection circuit154are not necessarily provided as separated circuits. The first electrode selection circuit15may be provided as one integrated circuit having the functions of the first selection circuit151, the second selection circuit152, the third selection circuit153, and the first electrode block selection circuit154. The first electrode selection circuit15may be a semiconductor integrated circuit (IC).

The following describes the configuration of the first electrodes Tx and the second electrodes Rx. As illustrated inFIG. 6, the second electrode Rx is a zigzag line, and the long side of the second electrode Rx extends in the second direction Dy as a whole. The second electrode Rx includes a plurality of first linear portions26a, a plurality of second linear portion26b, and a plurality of bends26x, for example. The second linear portions26bextend in a direction intersecting the first linear portions26a. The bend26xcouples the first linear portion26aand the second linear portion26b.

The first linear portion26aextends in a direction intersecting the first direction Dx and the second direction Dy. The second linear portion26balso extends in a direction intersecting the first direction Dx and the second direction Dy. The first linear portion26aand the second linear portion26bare disposed symmetrically about a virtual line (not illustrated) parallel to the first direction Dx. In the second electrode Rx, the first linear portions26aand the second linear portions26bare alternately coupled in the second direction Dy.

In each of the second electrodes Rx, Pry denotes an arrangement interval of the bends26xin the second direction Dy. In the second electrodes Rx disposed side by side, Prx denotes an arrangement interval of the bends26xin the first direction Dx. In the configuration according to the present embodiment, Prx<Pry is preferably satisfied, for example. The second electrode Rx does not necessarily have a zigzag shape and may have another shape, such as a wavy shape or a linear shape.

As illustrated inFIG. 6, a plurality of first electrodes Tx-1, Tx-2, Tx-3, Tx-4, . . . each include a plurality of electrode portions23aor23band a plurality of couplers24. In the following description, the first electrodes Tx-1, Tx-2, Tx-3, Tx-4, . . . are simply referred to as the first electrodes Tx when they need not be distinguished from one another.

The first electrodes Tx-1and Tx-2intersecting the second linear portions26bof the second electrodes Rx include the electrode portions23ahaving two sides parallel to the second linear portions26b. The first electrodes Tx-3and Tx-4intersecting the first linear portions26aof the second electrodes Rx include the electrode portions23bhaving two sides parallel to the first linear portions26a. In other words, a plurality of electrode portions23aand23bare disposed along the second electrodes Rx. This configuration can make the distances between the zigzag second electrodes Rx and the electrode portions23aand23buniform in planar view. In the first electrodes Tx-1and Tx-2, the electrode portions23aare arrayed in the first direction Dx and separated from each other. In each of the first electrodes Tx, the coupler24couples the electrode portions23adisposed side by side out of the electrode portions23a. Each of the second electrodes Rx extends through a space between the electrode portions23adisposed side by side and intersects the couplers24in planar view. The first electrodes Tx-3and Tx-4also have the same configuration as described above. The second electrode Rx is a metal thin wire. The width of the second electrode Rx in the first direction Dx is smaller than that of the electrode portions23aand23bin the first direction Dx. This configuration reduces the area in which the first electrodes Tx and the second electrodes Rx overlap, thereby reducing stray capacitance.

Pt denotes an arrangement interval of the first electrodes Tx in the second direction Dy. The arrangement interval Pt is substantially one-half the arrangement interval Pry of the bends26xof the second electrodes Rx. The configuration is not limited thereto, and the arrangement interval Pt may be other than a half-integer multiple of the arrangement interval Pry. The arrangement interval Pt is 50 μm to 100 μm, for example. In one first electrode Tx, the couplers24disposed side by side in the first direction Dx are alternately disposed with an arrangement interval Pb interposed therebetween in the second direction Dy. While the electrode portions23aand23bhave a parallelogram shape, they may have another shape. The electrode portions23aand23bmay have a rectangular, polygonal, or deformed shape, for example.

The following describes the layer structure of the detection apparatus1with reference toFIG. 7. InFIG. 7, the section of the frame region GA is a section of a portion including a thin-film transistor Tr in the first electrode selection circuit15. To explain the relation between the layer structure of the detection region FA and that of the frame region GA,FIG. 7schematically illustrates the section along line VII-VII′ in the detection region FA and the section of the portion including the thin-film transistor Tr in the frame region GA in a continuous manner.

As illustrated inFIG. 7, the detection apparatus1includes the thin-film transistors Tr in the frame region GA. The thin-film transistor Tr includes a semiconductor layer61, a source electrode62, a drain electrode63, and a gate electrode64. The gate electrode64is provided on the sensor substrate21. A first interlayer insulating film81is provided on the sensor substrate21to cover the gate electrode64. The gate electrode64is made of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy of these metals. The first interlayer insulating film81is made of a silicon oxide film (SiO), a silicon nitride film (SiN), or a silicon oxynitride film (SiON). The first interlayer insulating film81is not necessarily a single layer and may be a multilayered film. The first interlayer insulating film81, for example, may be a multilayered film in which a silicon nitride film is formed on a silicon oxide film.

The semiconductor layer61is provided on the first interlayer insulating film81. A second interlayer insulating film82is provided on the first interlayer insulating film81to cover the semiconductor layer61. The semiconductor layer61is exposed on the bottom of a contact hole formed in the second interlayer insulating film82. The semiconductor layer61is made of polysilicon or an oxide semiconductor. The second interlayer insulating film82is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The second interlayer insulating film82is not necessarily a single layer and may be a multilayered film. The second interlayer insulating film82, for example, may be a multilayered film in which a silicon nitride film is formed on a silicon oxide film.

The source electrode62and the drain electrode63are provided on the second interlayer insulating film82. The source electrode62and the drain electrode63are coupled to the semiconductor layer61through the contact hole formed in the second interlayer insulating film82. The source electrode62, the drain electrode63, and the coupler24are made of titanium-aluminum (TiAl), which is an alloy of titanium and aluminum.

An insulating resin layer27and the electrode portion23band the coupler24of the first electrode Tx are provided on the second interlayer insulating film82. The resin layer27provided in the frame region GA covers the source electrode62and the drain electrode63. The drain electrode63is electrically coupled to the first electrode Tx through a contact hole formed in the resin layer27provided in the frame region GA.

The resin layer27provided in the detection region FA includes a first resin layer27A and a second resin layer27B thinner than the first resin layer27A. The first resin layer27A covers a portion of the coupler24positioned just under the second electrode Rx. The second resin layer27B provided in the detection region FA covers a portion of the coupler24positioned just under the electrode portion23b.

The second resin layer27B has contact holes H1and H2. In the detection region FA, peripheries of the electrode portions23bare coupled to the coupler24through the contact holes H1and H2. In this example, the electrode portion23bis in contact with the second interlayer insulating film82.

The second electrode Rx is provided on the first resin layer27A. The second electrode Rx includes a first metal layer141, a second metal layer142, and a third metal layer143, for example. The second metal layer142is provided on the third metal layer143, and the first metal layer141is provided on the second metal layer142. The first metal layer141and the third metal layer143are made of molybdenum or a molybdenum alloy, for example. The second metal layer142is made of aluminum or an aluminum alloy, for example. Molybdenum or a molybdenum alloy included in the first metal layer141has reflectance of visible light lower than that of aluminum or an aluminum alloy included in the second metal layer142. This structure can prevent the second electrode Rx from being visually recognized.

An insulating film83is provided on the resin layer27, the electrode portion23b, and the second electrode Rx. The insulating film83covers the upper surface and the side surfaces of the second electrode Rx. The insulating film83is a film having a high refractive index and low reflectance, such as a silicon nitride film.

With the configuration described above, the first electrodes Tx and the second electrodes Rx are provided on the single sensor substrate21. The first electrodes Tx and the second electrodes Rx are provided in different layers with the resin layers27serving as insulating layers interposed therebetween.

The following describes various detection modes of the detection apparatus1.FIG. 8is a view for explaining the first detection mode of the detection apparatus according to the first embodiment. As illustrated inFIG. 8, in the first detection mode M1, the detection apparatus1scans the whole surface of the detection region FA at a first detection pitch Pts larger than the pitch in the second detection mode M2(refer toFIG. 9), thereby detecting the finger Fin or the like. In the first detection mode M1, the first electrode selection circuit15collectively selects a plurality of first electrodes Tx and supplies the first drive signals Vtx1to the respective first electrode blocks BK (refer toFIG. 15). At least the first electrodes Tx included in one first electrode block BK are supplied with the same first drive signal Vtx1. As a result, in the first detection mode M1, the detection apparatus1can perform detection at the first detection pitch Pts larger than the pitch in the second detection mode M2, which will be described later. In the first detection mode M1, for example, the detection apparatus1can detect a touch made by the finger Fin or the like. In the first detection mode M1, the detection apparatus1may perform touch detection in units of the first electrode block BK by CDM drive or TDM drive.

FIG. 9is a view for explaining the second detection mode of the detection apparatus according to the first embodiment. As illustrated inFIG. 9, in the second detection mode M2, the detection apparatus1scans the whole surface of the detection region FA at a second detection pitch Pf smaller than the pitch in the first detection mode M1(refer toFIG. 8), thereby detecting the finger Fin or the like. In the second detection mode M2, the first electrode selection circuit15supplies the second drive signals Vtx2having the phases determined based on a predetermined code to the respective first electrodes Tx. As a result, in the second detection mode M2, the detection apparatus1can perform detection at the second detection pitch Pf smaller than the pitch in the first detection mode M1. In the second detection mode M2, for example, the detection apparatus1can detect the fingerprint of the finger Fin or the like by performing CDM drive.

In the second detection mode M2, the detection apparatus1performs detection on the whole surface of the detection region FA. Consequently, the detection apparatus1can detect not only a fingerprint but also a palm print, for example. Alternatively, the detection apparatus1can detect the shape of a hand in contact with or in proximity to the detection region FA and determine the position of a fingertip. In this case, the detection apparatus1can detect the fingerprint by performing signal processing and arithmetic processing on only the region with or to which the fingertip is in contact or in proximity.

FIG. 10is a view for explaining the third detection mode of the detection apparatus according to the first embodiment. As illustrated inFIG. 10, in the third detection mode M3, the detection apparatus1performs detection at the second detection pitch Pf in a first partial region FA1, which is part of the detection region FA. In the third detection mode M3, the first electrode selection circuit15supplies the second drive signals Vtx2having the phases determined based on a predetermined code to the respective first electrodes Tx included in the first partial region FA1. Also in the third detection mode M3, the detection apparatus1can perform detection at the second detection pitch Pf. In the third detection mode M3, for example, the detection apparatus1can detect the fingerprint of the finger Fin or the like by performing CDM drive. Performing detection on only the first partial region FA1can reduce the time required for detection and the amount of processing performed by the detector40(refer toFIG. 3). The first partial region FA1is a fixed region determined in advance. The position and the size of the first partial region FA1may be appropriately modified.

FIG. 11is a view for explaining the fourth detection mode of the detection apparatus according to the first embodiment. As illustrated inFIG. 11, the detection apparatus1performs touch detection in the first detection mode M1to detect the finger Fin or the like in contact with or in proximity to the detection region FA. If the finger Fin or the like is detected, the detection apparatus1performs detection in the fourth detection mode M4. In detection in the fourth detection mode M4, the detection apparatus1performs detection at the second detection pitch Pf in a second partial region FA2overlapping the position where the finger Fin or the like is detected. In the fourth detection mode M4, for example, the detection apparatus1detects the fingerprint of the finger Fin or the like by CDM drive. The position and the size of the second partial region FA2can be modified based on information on the detected finger Fin or the like. As described above, the detection apparatus1may perform fingerprint detection in the fourth detection mode M4based on the detection results in the first detection mode M1. This mechanism can reduce the area of the second partial region FA2, thereby reducing the time required for detection.

The detection apparatus1may switch the detection modes in response to an operation of selecting the detection mode performed by an operator, for example. Alternatively, the detection apparatus1may perform the detection modes in respective predetermined periods in a time-division manner. Still alternatively, the detection apparatus1does not necessarily perform any one of the first detection mode M1to the fourth detection mode M4.

The following describes CDM drive performed by the detection apparatus1.FIG. 12is a diagram for explaining an exemplary operation in code division multiplexing drive. To simplify the explanation,FIG. 12illustrates an exemplary operation in CDM drive performed on four first electrodes Tx-1, Tx-2, Tx-3, and Tx-4. As illustrated inFIG. 12, the first electrode selection circuit15(refer toFIG. 3) selects the four first electrodes Tx-1, Tx-2, Tx-3, and Tx-4of one first electrode block BK simultaneously. The first electrode selection circuit15supplies the second drive signals Vtx2having the phases determined based on a predetermined code to the respective first electrodes Tx. The predetermined code is defined by the square matrix in Expression (1), for example. The order of the square matrix is four, which is equal to the number of first electrodes Tx-1, Tx-2, Tx-3, and Tx-4. Diagonal elements “−1” of the square matrix in Expression (1) are different from elements “1” other than the diagonal elements of the square matrix. The first electrode selection circuit15applies the second drive signals Vtx2such that the phase of AC rectangular waves corresponding to the elements “1” other than the diagonal elements of the square matrix is opposite to the phase of AC rectangular waves corresponding to the diagonal elements “−1” of the square matrix based on the square matrix in Expression (1). The element “−1” is an element for supplying the second drive signal Vtx2determined to have a phase different from that of the element “1”.

If an external proximity object CQ, such as a finger, is present on the first electrode Tx-2out of the first electrodes Tx-1, Tx-2, Tx-3, and Tx-4, a voltage of difference due to the external proximity object CQ is generated by mutual induction (the voltage of difference is 20%, for example). In the example illustrated inFIG. 12, the third detection signal Vdet3, which is obtained by integrating the first detection signal Vdet1corresponding to the element “1” and the second detection signal Vdet2corresponding to the element “−1”, is output from the second electrode Rx. The third detection signal Vdet3detected by the detector40in the first period of time is calculated by: (−1)+(0.8)+(1)+(1)=1.8. The third detection signal Vdet3in the second period of time is calculated by: (1)+(−0.8)+(1)+(1)=2.2. The third detection signal Vdet3in the third period of time is calculated by: (1)+(0.8)+(−1)+(1)=1.8. The third detection signal Vdet3in the fourth period of time is calculated by: (1)+(0.8)+(1)+(−1)=1.8.

The signal processor44stores the third detection signals Vdet3detected in the respective periods of time in the storage46. The signal processor44multiplies the third detection signals Vdet3by the square matrix in Expression (1), thereby performing decoding. As a result, the signal processor44calculates Vdet4=“4.0, 3.2, 4.0, 4.0” as a decoded signal Vdet4. The detector40can detect the presence of the external proximity object CQ, such as a finger, or unevenness on the surface of the external proximity object CQ at the position of the first electrode Tx-2based on the decoded signal Vdet4. As described above, the detection apparatus1performs detection with detection sensitivity four times the detection sensitivity in time division multiplexing (TDM) drive without raising the voltage. The coordinate extractor45outputs the touch panel coordinates or the decoded signal Vdet4as the sensor output Vo.

FIG. 13is a diagram for explaining another exemplary operation in code division multiplexing drive. InFIG. 13, the second drive signals Vtx2are applied to the first electrodes Tx corresponding to the elements “1” of the square matrix and the first electrodes Tx corresponding to the elements “−1” of the square matrix in different periods of time. In this case, the phase of the AC rectangular waves corresponding to the elements “1” of the square matrix is the same as that of the AC rectangular waves corresponding to the elements “−1” of the square matrix. Specifically, in the first, the third, the fifth, and the seventh periods of time, the first electrode selection circuit15supplies the second drive signals Vtx2to the first electrodes Tx corresponding to the elements “1”. In the periods of time described above, the first electrode selection circuit15supplies no second drive signal Vtx2to the first electrodes Tx corresponding to the elements “−1”. By contrast, in the second, the fourth, the sixth, and the eighth periods of time, the first electrode selection circuit15supplies no second drive signal Vtx2to the first electrodes Tx corresponding to the elements “1” but supplies the second drive signals Vtx2to the first electrodes Tx corresponding to the elements “−1”.

The signal processor44calculates the difference between the first detection signal Vdet1=2.8 detected in the first period of time and the second detection signal Vdet2=1.0 detected in the second period of time as the third detection signal Vdet3=1.8. The signal processor44calculates the difference between the first detection signal Vdet1=3.0 detected in the third period of time and the second detection signal Vdet2=0.8 detected in the fourth period of time as the third detection signal Vdet3=2.2. The signal processor44performs the same operation as described above in and after the fifth period of time. The signal processor44decodes the calculated third detection signals Vdet3, thereby calculating Vdet4=“4.0, 3.2, 4.0, 4.0” as the decoded signal Vdet4.

If several hundred to one thousand or more first electrodes Tx are provided at a small array pitch, for example, the size of the circuits that supply the selection signals and the drive signals based on the predetermined code may possibly increase. In a method of sequentially transmitting the selection signals to the first electrodes Tx via shift registers or the like, the detection performance may possibly be degraded because of delay of the signals, for example. The first electrode selection circuit15according to the present embodiment includes the circuits that generate the signals having the phases determined based on the predetermined code simultaneously in parallel. This configuration can suppress an increase in circuit size and enable satisfactory fingerprint detection and touch detection.

The following describes the configuration of the first electrode selection circuit15.FIG. 14is a block diagram of the first electrode selection circuit according to the first embodiment. As illustrated inFIG. 14, the first electrode selection circuit15includes the first selection circuit151, the second selection circuit152, the third selection circuit153, and the first electrode block selection circuit154. InFIG. 14, the detection apparatus1includes four first electrode blocks BK1, BK2, BK3, and BK4. The first electrode blocks BK1, BK2, BK3, and BK4each include a plurality of first electrodes Tx (e.g., 64 first electrodes Tx-1to Tx-64) (refer toFIG. 15). In the following description, the first electrode blocks BK1, BK2, BK3, and BK4are referred to as the first electrode blocks BK when they need not be distinguished from one another. The detection apparatus1may include five or more first electrode blocks BK, for example.

The first selection circuit151provides first selection signals Vc having the phases determined based on a predetermined code for the respective first electrodes Tx. The first selection circuit151includes a third code generation circuit block14B provided for the respective first electrode blocks BK. The second selection circuit152supplies second selection signals Vg having the phases determined based on a predetermined code for the respective first electrode blocks BK. The third selection circuit153provides third selection signals Vk based on the first selection signals Vc and the second selection signals Vg. The first electrode block selection circuit154generates first electrode block selection signals Vh for selecting the first electrode blocks BK. The third selection circuit153supplies the first drive signals Vtx1or the second drive signals Vtx2to the respective first electrodes Tx included in the selected first electrode blocks BK based on the first electrode block selection signals Vh and the third selection signals Vk.

FIG. 15is a block diagram of the first selection circuit of the first electrode selection circuit. To simplify the explanation, the following describes one first electrode block BK with reference toFIG. 15. As illustrated inFIGS. 14 and 15, the first selection circuit151includes a first code generation circuit12, a second code generation circuit13, a third code generation circuit14, and a counter circuit17. The first selection signals Vc, which are not illustrated inFIG. 15, output from the third code generation circuit14are supplied to the first electrodes Tx via the third selection circuit153and a buffer166as illustrated inFIG. 14.

The first code generation circuit12and the second code generation circuit13are decoder circuits. The first code generation circuit12generates first partial selection signals Vd based on first control signals Va1, Va2, and Va3and supplies the first partial selection signals Vd to the third code generation circuit14. The second code generation circuit13generates second partial selection signals Vf based on second control signals Vb1, Vb2, and Vb3and supplies the second partial selection signals Vf to the third code generation circuit14. The third code generation circuit14is an exclusive OR (XOR) circuit, for example. The third code generation circuit14provides the first selection signals Vc based on the first partial selection signals Vd and the second partial selection signals Vf and supplies signals resulting from the first selection signals Vc to the first electrodes Tx. The counter circuit17generates the first control signals Va1, Va2, and Va3, the second control signals Vb1, Vb2, and Vb3, and an inversion control signal Vs based on a first reset signal FPS_RST and a first clock signal FPS_CLK supplied from the detection controller11(refer toFIG. 3).

As illustrated inFIG. 15, the first code generation circuit12, the second code generation circuit13, the third code generation circuit14, and the counter circuit17are provided on the sensor substrate21. The first code generation circuit12includes first input terminals A1, A2, and A3, a power source voltage terminal VDD, and first output terminals Ya1, Ya2, Ya3, Ya4, Ya5, Ya6, Ya7, and Ya8. In the following description, the first output terminals Ya1, Ya2, Ya3, Ya4, Ya5, Ya6, Ya7, and Ya8are simply referred to as first output terminals Ya when they need not be distinguished from one another. In the configuration according to the present embodiment, the number P of first output terminals Ya serving as output terminals of the first code generation circuit12is eight. The first input terminals A1, A2, and A3receive the first control signals Va1, Va2, and Va3, respectively, from the counter circuit17. The first code generation circuit12generates the first partial selection signals Vd based on the first control signals Va1, Va2, and Va3. The first output terminals Ya output the first partial selection signals Vd to respective first selection signal lines LSa1, LSa2, . . . , and LSa8.

The second code generation circuit13includes second input terminals B1, B2, B3, and S and second output terminals Yb1, Yb2, Yb3, Yb4, Yb5, Yb6, Yb7, and Yb8. In the following description, the second output terminals Yb1, Yb2, Yb3, Yb4, Yb5, Yb6, Yb7, and Yb8are simply referred to as second output terminals Yb when they need not be distinguished from one another. In the configuration according to the present embodiment, the number Q of second output terminals Yb serving as output terminals of the second code generation circuit13is eight. The second input terminals B1, B2, and B3receive the second control signals Vb1, Vb2, and Vb3, respectively, from the counter circuit17. The second input terminal S receives the inversion control signal Vs from the counter circuit17. The second code generation circuit13generates the second partial selection signals Vf based on the second control signals Vb1, Vb2, and Vb3and the inversion control signal Vs. The inversion control signal Vs is a signal for inverting the elements “1” and “−1” of the predetermined code. The second output terminals Yb output the second partial selection signals Vf to respective second selection signal lines LSb1, LSb2, . . . , and LSb8.

As illustrated inFIG. 15, a plurality of first electrode blocks BK each including a plurality of first electrodes Tx-1, Tx-2, Tx-3, . . . , and Tx-64are provided. In the configuration according to the present embodiment, the number N of first electrodes Tx included in one first electrode block BK is 64. Drive signal supply lines Ld1, Ld2, . . . , and Ld64are coupled to the respective first electrodes Tx. Drive signal supply line partial blocks sBKL1, sBKL2, sBKL3, sBKL4, sBKL5, sBKL6, sBKL7, and sBKL8each include eight drive signal supply lines Ld. The first electrode block BK is coupled to a drive signal supply line block BKL. The drive signal supply line block BKL includes eight drive signal supply line partial blocks sBKL the number of which corresponds to the number Q of second output terminals Yb.

The first selection signal lines LSa1, LSa2, . . . , and LSa8are coupled to the respective drive signal supply lines Ld in each of the drive signal supply line partial blocks sBKL. As a result, the first selection signal lines LSa1, LSa2, . . . , and LSa8are coupled to the drive signal supply line partial blocks sBKL1, sBKL2, sBKL3, sBKL4, sBKL5, sBKL6, sBKL7, and sBKL8in parallel. The first selection signal lines LSa1, LSa2, . . . , and LSa8are coupled to different drive signal supply lines Ld. In other words, the drive signal supply lines Ld included in one drive signal supply line partial block sBKL are coupled to the respective first selection signal lines LSa1, LSa2, . . . , and LSa8. The drive signal supply lines Ld1, Ld2, . . . , and Ld8included in the drive signal supply line partial block sBKL1, for example, are coupled to the first selection signal lines LSa1, LSa2, . . . , and LSa8, respectively. The drive signal supply line partial blocks sBKL2, sBKL3, . . . , and sBKL8have the same configuration as described above.

Third code generation circuits14-1,14-2, . . . , and14-8included in the third code generation circuit block14B are provided corresponding to the drive signal supply line blocks BKL1, BKL2, . . . , and BKL8, respectively. In other words, in the first electrode blocks BK disposed side by side, the first electrodes Tx included in respective the first electrode blocks and disposed at the same position in the direction in which the first electrode blocks BK are disposed side by side are coupled to the third code generation circuit14coupled to the same second selection signal line LSb. The second selection signal lines LSb1, LSb2, . . . , and LSb8are coupled to the third code generation circuits14-1,14-2, . . . , and14-8, respectively. In other words, the second selection signal lines LSb1, LSb2, . . . , and LSb8are coupled to the drive signal supply line partial blocks sBKL1, sBKL2, . . . , and sBKL8, respectively. To simplify the explanation, the third code generation circuit block14B illustrated inFIG. 15are divided into the third code generation circuits14-1,14-2, . . . , and14-8corresponding to the respective drive signal supply line partial blocks sBKL. The third code generation circuits14-1,14-2, . . . , and14-8may be provided as one circuit. A drive signal supply line block BKL0corresponds to a plurality of drive signal supply line partial blocks sBKL. The drive signal supply line block BKL0is coupled to a plurality of drive signal supply line blocks BKL1, BKL2, . . . , and BKLn. The drive signal supply line blocks BKL1, BKL2, . . . , and BKLn correspond to the first electrode blocks BK1, . . . , and BKn, respectively. With this configuration, the third code generation circuit block14B outputs the same signals to the first electrode blocks BK.

The following describes the operations performed by the counter circuit17, the first code generation circuit12, the second code generation circuit13, and the third code generation circuit14.FIG. 16is a timing waveform chart of an exemplary operation performed by the counter circuit. The counter circuit17illustrated inFIG. 15is a binary counter circuit, for example, and outputs binary numbers. The counter circuit17includes a plurality of flip-flop circuits18a,18b,18c,18d,18e,18f, and18g. The flip-flop circuits18a,18b,18c,18d,18e,18f, and18gare registers that can hold one-bit information. In the following description, the flip-flop circuits18a,18b,18c,18d,18e,18f, and18gare simply referred to as flip-flop circuits18when they need not be distinguished from one another. While the counter circuit17is provided on the sensor substrate21, the configuration is not limited thereto. The counter circuit17may be provided in the detection controller11or an external control substrate.

As illustrated inFIGS. 15 and 16, an output signal from the flip-flop circuit18ais supplied to the second input terminal S of the second code generation circuit13as the inversion control signal Vs. The output signal from the flip-flop circuit18ais also output to the next flip-flop circuit18b. The frequency of the inversion control signal Vs is one half the frequency of the first clock signal FPS_CLK. An output signal from the flip-flop circuit18bat the second stage is supplied to the second input terminal B3of the second code generation circuit13as the second control signal Vb3. The output signal from the flip-flop circuit18bis also output to the next flip-flop circuit18c. The frequency of the second control signal Vb3is one half the frequency of the inversion control signal Vs. Similarly, the flip-flop circuits18c,18d,18e,18f, and18goutput the second control signals Vb2and Vb1and the first control signals Va3, Va2, and Va1, respectively.

If the state of all the flip-flop circuits18is “1”, the flip-flop circuits18are reset to “0” based on the first reset signal FPS_RST.

FIG. 17is a circuit diagram of an example of the first code generation circuit.FIG. 18is a table indicating the relation between the first control signals and the first partial selection signals. As illustrated inFIG. 17, the first code generation circuit12includes a plurality of XOR circuits51-1,51-2, . . . , and51-7. The XOR circuits51-1,51-2, . . . , and51-7receive any one of the first control signals Va1, Va2, and Va3and the power source voltage Vdd or an output signal from another XOR circuit51. The first control signals Va1, Va2, and Va3are output signals from the counter circuit17illustrated inFIG. 15. The XOR circuits51-1,51-2, . . . , and51-7output the value of exclusive or (Xor) of the received signals as first partial selection signals Vd2, Vd3, . . . , and Vd8, respectively. The same signal as the power source voltage Vdd is output as a first partial selection signal Vd1.

The first code generation circuit12generates the first partial selection signals Vd1, Vd2, . . . , and Vd8corresponding to the first control signals Va1, Va2, and Va3and the power source voltage Vdd according to the truth table illustrated inFIG. 18. InFIG. 18, “1” is allocated if the signals are at a high-level voltage, and “0” is allocated if the signals are at a low-level voltage. The first code generation circuit12thus outputs the first partial selection signals Vd1, Vd2, and Vd8having the phases determined based on a predetermined code to the drive signal supply line partial blocks sBKL. The predetermined code is defined by the square matrix in Expression (2), for example. The order of the square matrix is eight, which is equal to the number of first output terminals Ya. The predetermined code is a square matrix the elements of which are either “1” or “−1” or “1” or “0” and certain two different rows of which are an orthogonal matrix. The predetermined code is based on a Hadamard matrix, for example.

The first code generation circuit12outputs the first partial selection signals Vd1, Vd2, and Vd8from the respective first output terminals Ya in each of periods ta1, ta2, . . . , and ta8. The combination patterns of turning-on and -off of the first partial selection signals Vd1, Vd2, and Vd8are different from one another between the periods ta1, ta2, . . . , and ta8. The number of combination patterns of turning-on and -off of the first partial selection signals Vd1, Vd2, and Vd8is eight, which is equal to the number of first output terminals Ya.

FIG. 19is a circuit diagram of an example of the second code generation circuit.FIG. 20is a table indicating the relation between the second control signals and the inversion control signal, and the second partial selection signals. As illustrated inFIG. 19, the second code generation circuit13includes a plurality of XOR circuits52-1,52-2, . . . , and52-7and an inverter53. The inverter53outputs a voltage signal obtained by inverting the inversion control signal Vs as a second partial selection signal Vf1. In other words, the inverter53outputs a low-level voltage signal if the inversion control signal Vs is at a high-level voltage and outputs a high-level voltage signal if the inversion control signal Vs is at a low-level voltage. The XOR circuits52-1,52-2, . . . , and52-7receive any one of the second control signals Vb1, Vb2, and Vb3and an output signal from the inverter53or an output signal from another XOR circuit52. The inversion control signal Vs and the second control signals Vb1, Vb2, and Vb3are output signals from the counter circuit17illustrated inFIG. 15. The XOR circuits52-1,52-2, . . . , and52-7output the value of Xor of the received signals as second partial selection signals Vf2, Vf3, . . . , and Vf8, respectively. The inverter53is not necessarily provided, and the second code generation circuit13may output the inversion control signal Vs as the second partial selection signal Vf1.

The second code generation circuit13generates the second partial selection signals Vf corresponding to the second control signals Vb1, Vb2, and Vb3and the inversion control signal Vs according to the truth table illustrated inFIG. 20. InFIG. 20, “1” is allocated if the signals are at a high-level voltage, and “0” is allocated if the signals are at a low-level voltage. The second code generation circuit13thus outputs the second partial selection signals Vf1, Vf2, and Vf8having the phases determined based on a predetermined code to the respective drive signal supply line partial blocks sBKL in each of periods tb1, tb2, . . . , and tb16. The predetermined code is defined by the square matrix in Expression (2), for example. If the inversion control signal Vs is turned off (“0”), the second code generation circuit13generates the second partial selection signals Vf1, Vf2, . . . , and Vf8corresponding to the elements “1” in the square matrix. If the inversion control signal Vs is turned on (“1”), the second code generation circuit13generates the second partial selection signals Vf1, Vf2, . . . , and Vf8corresponding to the elements “−1” in the square matrix. The order of the square matrix is eight, which is equal to the number of second output terminals Yb.

The second code generation circuit13outputs the second partial selection signals Vf1, Vf2, . . . , and Vf8from the respective second output terminals Yb in each of the periods tb1, tb2, . . . , and tb16. The combination patterns of turning-on and -off of the second partial selection signals Vf1, Vf2, . . . , and Vf8are different from one another between the periods tb1, tb2, and tb16.

The combination patterns described above include combination patterns obtained by inverting turning-on and -off of the second partial selection signals Vf1, Vf2, . . . , and Vf8because the second code generation circuit13receives the inversion control signal Vs. Specifically, the inversion control signal Vs is turned off in the periods tb1, tb3, tb5, tb7, tb9, tb11, tb13, and tb15and turned on in the periods tb2, tb4, tb6, tb8, tb10, tb12, tb14, and tb16. The periods Tb1and tb2, for example, have combination patterns of turning-on and -off of the second partial selection signals Vf1, Vf2, . . . , and Vf8opposite to each other. Similarly, each pair of periods from the period tb3to the period tb16also has combination patterns opposite to each other. The number of combination patterns of turning-on and -off of the second partial selection signals Vf1, Vf2, . . . , and Vf8is 16, which is twice the number of second output terminals Yb.

FIG. 21is a circuit diagram of an example of the third code generation circuit.FIG. 22illustrates an example of a pattern code generated by the third code generation circuit if the inversion control signal is at a high-level voltage.FIG. 23illustrates an example of a pattern code generated by the third code generation circuit if the inversion control signal is at a low-level voltage.FIG. 24is a table indicating the relation between the first control signals, the second control signals and the inversion control signal, and the detection signals.

FIG. 21illustrates the third code generation circuit14-1provided to the drive signal supply line partial block sBKL1out of the drive signal supply line partial blocks sBKL. As illustrated inFIG. 21, the third code generation circuit14-1includes a plurality of XOR circuits54-1,54-2, . . . , and54-8. The XOR circuits54-1,54-2, . . . , and54-8receive the first partial selection signals Vd1, Vd2, . . . , and Vd8, respectively, from the first output terminals Ya of the first code generation circuit12. The XOR circuits54-1,54-2, . . . , and54-8also receive the second partial selection signal Vf1from the second output terminal Yb1of the second code generation circuit13. The XOR circuits54-1,54-2, . . . , and54-8calculate Xor of the first partial selection signals Vd1, Vd2, . . . , and Vd8, respectively, and the second partial selection signal Vf1. The values calculated by the XOR circuits54-1,54-2, . . . , and54-8are supplied to the first electrodes Tx-1, Tx-2, . . . , and Tx-8via the drive signal supply lines Ld1, Ld2, . . . , and Ld8, respectively, as the first selection signals Vc.

As illustrated inFIG. 18, the number of combination patterns of the first partial selection signals Vd is eight. As illustrated inFIG. 20, the number of combination patterns of the second partial selection signals Vf is eight in both of the cases where the inversion control signal Vs is 0 and 1, that is, 16 in total. Consequently, as illustrated inFIG. 22, the order of the pattern code (predetermined code) of the first partial selection signal Vd generated by the third code generation circuit14is 8×8=64 if the inversion control signal Vs is 1. Similarly, as illustrated inFIG. 23, the order of the pattern code of the first partial selection signal Vd generated by the third code generation circuit14is 8×8=64 if the inversion control signal Vs is 0. The pattern code illustrated inFIG. 23is obtained by inverting “0” and “1” in the pattern code illustrated inFIG. 22.

The first code generation circuit12, the second code generation circuit13, and the third code generation circuit14provide first selection signals Vc1, . . . , and Vc64corresponding to the pattern codes illustrated inFIGS. 22 and 23according to the truth table illustrated inFIG. 24. The first selection signals Vc1, . . . , and Vc64are substantially simultaneously supplied to the first electrodes Tx-1to Tx-64, respectively. As illustrated inFIG. 24, if the inversion control signal Vs is 1, the second electrodes Rx output the first detection signals Vdet1. If the inversion control signal Vs is 0, the second electrodes Rx output the second detection signals Vdet2. The number of first detection signals Vdet1and the number of second detection signals Vdet2are 64 each, which corresponds to the order of the respective pattern codes.

The signal processor44(refer toFIG. 3) calculates the differences between the first detection signals Vdet1and the second detection signals Vdet2. As a result, 64 third detection signals Vdet3are calculated. The signal processor44decodes the third detection signals Vdet3based on the predetermined code corresponding to the pattern codes illustrated inFIGS. 22 and 23. Based on the decoded signals Vdet4calculated by the signal processor44, the detection apparatus1can detect contact or proximity of the external proximity object CQ or an uneven shape on the surface of the external proximity object CQ facing the detection surface.

As illustrated inFIG. 24, the detection apparatus1alternately performs the processing in the periods when the inversion control signal Vs is 1 and the processing in the periods when the inversion control signal Vs is 0. As a result, the interval between the detection times for the first detection signal Vdet1and the second detection signal Vdet2is shortened. If noise components enter from the outside, calculating the difference between the first detection signal Vdet1and the second detection signal Vdet2can cancel the noise components. Consequently, the detection apparatus1can increase the detection accuracy.

The order of combinations of the first partial selection signals Vd and the second partial selection signals Vf is not limited to that illustrated inFIG. 24. For example, the detection apparatus1may successively perform the processing in a plurality of periods when the inversion control signal Vs is 1 and then successively perform the processing in a plurality of periods when the inversion control signal Vs is 0.

As described above, the detection apparatus1according to the present embodiment includes the first code generation circuit12and the second code generation circuit13(refer toFIG. 15). Based on the first partial selection signals Vd output from the first code generation circuit12and the second partial selection signals Vf output from the second code generation circuit13, the first selection circuit151provides the first selection signals Vc having the phases determined based on the predetermined code for the respective first electrodes Tx. The detection apparatus1thus performs CDM drive on one first electrode block BK. The present embodiment can suppress delay of the signals and increase the detection accuracy compared with a case where shift registers supply the first selection signals Vc to all the first electrodes Tx, for example.

In the configuration according to the present embodiment, the counter circuit17provided on the sensor substrate21includes two external control terminals that receive the first clock signal FPS_CLK and the first reset signal FPS_RST. In other words, the configuration requires a smaller number of wires that couple the detection controller11and the counter circuit17on the sensor substrate21. The number of output terminals of the counter circuit17is equal to the sum of the number of first input terminals A1, A2, and A3of the first code generation circuit12and the number of second input terminals B1, B2, B3, and S of the second code generation circuit13. The counter circuit17can have a simpler configuration because the detection apparatus1includes the first code generation circuit12, the second code generation circuit13, and the third code generation circuit14. Specifically, the pattern codes with64order illustrated inFIGS. 22 and 23, for example, are generated based on the output signals from the flip-flop circuits18of seven stages in both of the cases where the inversion control signal Vs is turned on and off. With this configuration, the detection apparatus1can suppress delay of the signals in the counter circuit17and supply the first selection signals Vc corresponding to a large number of first electrodes Tx substantially simultaneously to the third selection circuit153.

The third code generation circuit14-1according to the present embodiment may calculate the negation of exclusive or (Xnor) of the first partial election signals Vd and the second partial selection signal Vf1. Alternatively, the third code generation circuit14-1may perform substantially the same arithmetic operation as the logical operation for Xor or Xnor. The configurations of the first code generation circuit12and the second code generation circuit13may be appropriately modified.

The following describes the second selection circuit152.FIG. 25is a block diagram of the second selection circuit of the first electrode selection circuit. As illustrated inFIG. 25, the second selection circuit152is a shift register including a plurality of transmission circuits and includes a plurality of flip-flop circuits161-1,161-2,161-3, . . . as the transmission circuits, for example. The second selection circuit152operates based on a code control signal CODE_STV, a code clock signal CODE_CKV, and a code reset signal CODE_RST.

The flip-flop circuits161-1,161-2, and161-3are logic circuits that sequentially transmit the code control signal CODE_STV to the next flip-flop circuits161-1,161-2, and161-3based on the code clock signal CODE_CKV. The flip-flop circuits161-1,161-2, and161-3provide second selection signals Vg1, Vg2, and Vg3, respectively, based on the code control signal CODE_STV and sequentially output the second selection signals Vg1, Vg2, and Vg3to respective latches162(refer toFIG. 14). The latch162is a circuit that temporarily stores therein the second selection signal Vg. If the code control signal CODE_STV is transmitted to all the flip-flop circuits161-1,161-2, and161-3, the flip-flop circuits161-1,161-2, and161-3are reset by the code reset signal CODE_RST.

As illustrated inFIG. 14, the flip-flop circuits161and the latches162included in the second selection circuit152are provided for the respective first electrode blocks BK. The code control signal CODE_STV is generated by an external component, such as the detection controller11(refer toFIG. 3). The code control signals CODE_STV have the phases determined based on a predetermined code for the respective first electrode blocks BK. In other words, the second selection signals Vg1, Vg2, and Vg3are control signals having the phases determined based on the predetermined code for the respective first electrode blocks BK.

If the second selection signals Vg are supplied to all the latches162, the latches162supply the second selection signals Vg substantially simultaneously to the third selection circuit153based on an enable signal OUT_ENB.

As illustrated inFIG. 14, the third selection circuit153includes a plurality of XOR circuits164and a plurality of negative AND (NAND) circuits165. The XOR circuits164and the NAND circuits165are provided for the respective first electrodes Tx. The third code generation circuits14of the first selection circuit151are disposed such that they supply the signals having different phases determined based on the predetermined code to the first electrodes Tx included in the respective first electrode blocks BK. In two first electrode blocks BK disposed side by side, the same signal is supplied to the first electrode blocks BK provided at the same position in the direction in which the first electrode blocks BK are disposed side by side. By contrast, common signals are output from the second selection circuit152and the first electrode block selection circuit154to the XOR circuits164and the NAND circuits165included in one first electrode block BK. The third code generation circuits14output the first selection signals Vc corresponding to the pattern codes illustrated inFIGS. 22 and 23to the XOR circuits164. The second selection circuit152outputs the second selection signals Vg to the XOR circuits164. The XOR circuits164output the value of Xor of the first selection signal Vc and the second selection signal Vg to the respective NAND circuits165as the third selection signal Vk.

In the second detection mode M2(refer toFIG. 9) or the third detection mode M3(refer toFIG. 10), the third code generation circuit14provides the first selection signals Vc having the phases based on the predetermined code for the respective first electrodes Tx. The third code generation circuits14provide the first selection signals Vc corresponding to the same pattern code for the respective first electrode blocks BK.

The second selection signals Vg have the phases determined based on the predetermined code for the respective first electrode blocks BK. The XOR circuits164calculate Xor of the first selection signal Vc and the second selection signal Vg, thereby providing different third selection signals Vk for the respective first electrode blocks BK. The third selection signal Vk is a signal for selecting the first electrodes Tx included in a plurality of first electrode blocks BK. The third selection circuit153supplies the second drive signals Vtx2having the phases determined based on the third selection signals Vk to a plurality of first electrodes Tx. The detection apparatus1thus can perform CDM drive on the whole detection region FA.

As illustrated inFIG. 14, the first electrode block selection circuit154is a shift register including a plurality of transmission circuits and includes a plurality of flip-flop circuits163as the transmission circuits, for example. The flip-flop circuits163are logic circuits provided for the respective first electrode blocks BK. The first electrode block selection circuit154operates based on a mask control signal MASK_STV, a mask clock signal MASK_CKV, and a mask reset signal MASK_RST. If the mask control signal MASK_STV is turned on (high-level voltage), the flip-flop circuit163outputs the first electrode block selection signal Vh at a high-level voltage to the third selection circuit153. As a result, the corresponding first electrode block BK is selected as a target to be driven. If the mask control signal MASK_STV is turned off (low-level voltage), the flip-flop circuit163outputs the first electrode block selection signal Vh at a low-level voltage to the third selection circuit153. As a result, the corresponding first electrode block BK is not selected.

The NAND circuit165of the third selection circuit153receives the first electrode block selection signal Vh and calculates negative and (nand) of the third selection signal Vk and the first electrode block selection signal Vh. In other words, if the first electrode block selection signal Vh is at a high-level voltage, the NAND circuit165outputs a first electrode selection signal Vsel corresponding to the third selection signal Vk to the buffer166. If the first electrode block selection signal Vh is at a low-level voltage, the NAND circuit165outputs the first electrode selection signal Vsel at a low-level voltage to the buffer166. The buffer166substantially simultaneously supplies the first drive signals Vtx1or the second drive signals Vtx2supplied from the first electrode drive circuit170to a plurality of first electrode blocks BK selected based on the first electrode selection signals Vsel.

By performing the operations described above, the third selection circuit153generates the drive signals Vtx (the first drive signals Vtx1or the second drive signals Vtx2) based on Expression (3).FIG. 26is a table indicating the relation between the first selection signal, the second selection signal, the first electrode block selection signal, and the drive signal. The first electrode selection circuit15generates the drive signals Vtx (the first drive signals Vtx1or the second drive signals Vtx2) corresponding to the first selection signals Vc, the second selection signals Vg, and the first electrode block selection signals Vh according to the truth table illustrated inFIG. 26.

The following describes exemplary operations performed by the first electrode selection circuit15in the respective detection modes.FIG. 27is a table indicating the relation between the first electrode blocks and the selection signals in the second detection mode.FIG. 28is a timing waveform chart of the first electrode selection circuit in the second detection mode. To simplify the explanation,FIG. 27illustrates four first electrode blocks BK1, BK2, BK3, and BK4. InFIG. 27, the first electrode blocks BK each include eight first electrodes Tx.

In the second detection mode M2(refer toFIG. 9), the detection apparatus1performs fingerprint detection on the whole surface of the detection region FA. As illustrated inFIG. 27, the first electrode block selection circuit154supplies the first electrode block selection signals Vh at a high-level voltage to the third selection circuit153based on the mask control signal MASK_STV. The first electrode block selection signals Vh corresponding to all the first electrode blocks BK are turned on (“1”). As a result, all the first electrode blocks BK are selected. The first selection circuit151and the second selection circuit152provide the first selection signals Vc and the second selection signals Vg, respectively, having the phases determined based on the predetermined code and supply the generated signals to the third selection circuit153. The third selection circuit153multiplies the first selection signals Vc by the second selection signals Vg, thereby generating the second drive signals Vtx2having the phases determined based on the predetermined code for the respective first electrodes Tx. The third selection circuit153supplies the second drive signals Vtx2to the respective first electrodes Tx. The detection apparatus1thus can perform CDM drive on the whole surface of the detection region FA.

As illustrated inFIG. 28, in a first period tc1, the first electrode block selection circuit154starts to operate using the mask reset signal MASK_RST as a trigger. The mask control signal MASK_STV at a high-level voltage is transmitted to all the flip-flop circuits163based on the mask clock signal MASK_CKV. The first electrode block selection circuit154generates the first electrode block selection signals Vh and turns on (“1”) the first electrode block selection signals Vh corresponding to all the first electrode blocks BK. As a result, all the first electrode blocks BK are selected.

In a second period tc2, the code control signal CODE_STV is supplied to the flip-flop circuits161in the second selection circuit152based on the code clock signal CODE_CKV. The second selection circuit152provides the second selection signals Vg having the phases determined based on the predetermined code for the respective first electrode blocks BK based on the code control signal CODE_STV. The second selection signals Vg output from the respective flip-flop circuits161are held in the respective latches162. If all the data of the code control signal CODE_STV is transmitted, the latches162output the second selection signals Vg to the third selection circuit153based on the enable signal OUT_ENB.

In a third period tc3, the first selection circuit151provides the first selection signals Vc having the phases determined based on the predetermined code for the respective first electrodes Tx based on the first reset signal FPS_RST and the first clock signal FPS_CLK. In the third period tc3, different combinations of the first selection signals Vc are supplied to the third selection circuit153corresponding to the number of pattern codes. In the example illustrated inFIG. 27, for example, the number of pattern codes is eight. In other words, the first selection circuit151provides different combinations of the first selection signals Vc eight times in the third period tc3. Combinations of the second drive signals Vtx2corresponding to the respective combinations of the first selection signals Vc are supplied to the respective first electrode blocks BK to perform detection eight times.

In a fourth period tc4, the second selection circuit152provides the second selection signals Vg having the phases determined based on the predetermined code, based on the code control signal CODE_STV different from that in the second period tc2. The processing in a fifth period tc5is the same as that in the third period tc3. By repeating the operations described above, the detection apparatus1performs detection using all the combinations of the first selection signals Vc generated by the first selection circuit151and the second selection signals Vg generated by the second selection circuit152. Let us assume a case where the number of combinations of the first selection signals Vc corresponding to the predetermined code (first code) is eight, for example. If the number of first electrode blocks BK is four, the number of combinations of the second selection signals Vg corresponding to the predetermined code (second code) is four. In this case, the number of second drive signals Vtx2corresponding to all the combinations is 32 (=4×8). Consequently, the number of periods for supplying all the second drive signals Vtx2is 32 in total. The detection apparatus1thus can perform CDM drive in the second detection mode M2. In this case, the detection apparatus1obtains the decoded signals Vdet4from the third detection signals Vdet3based on the first code and the second code. Specifically, the detection apparatus1obtains the decoded signals by performing inversion operations stepwise on a first Hadamard matrix corresponding to the first code and a second Hadamard matrix corresponding to the second code.

More specifically, the following describes a case where the second selection circuit152outputs the second selection signals Vg based on the predetermined code (second code) if the predetermined code (second code) is the Hadamard matrix represented by Expression 1.FIG. 29is a table indicating the second selection signals for the respective first electrode blocks in each holding period. As illustrated inFIG. 29, in a holding period tcg1, the second selection signal Vg for the first electrode block BK1is turned off (“0”), and the second selection signals Vg for the first electrode blocks BK2, BK3, and BK4are turned on (“1”). In a holding period tcg2, the second selection signal Vg for the first electrode block BK2is turned off (“0”), and the second selection signals Vg for the first electrode blocks BK1, BK3, and BK4are turned on (“1”). In a holding period tcg3, the second selection signal Vg for the first electrode block BK3is turned off (“0”), and the second selection signals Vg for the first electrode blocks BK1, BK2, and BK4are turned on (“1”). In a holding period tcg4, the second selection signal Vg for the first electrode block BK4is turned off (“0”), and the second selection signals Vg for the first electrode blocks BK1, BK2, and BK3are turned on (“1”). The holding period tcg1to the holding period tcg4correspond to the second period tc2and the fourth period tc4illustrated inFIG. 28andFIG. 32, which will be described later.

The second selection circuit152may perform inversion control.FIG. 30is a table indicating another example of the second selection signals for the respective first electrode blocks in each holding period. As illustrated inFIG. 30, the second selection circuit152may output second selection signals Vg1resulting from the predetermined code and second selection signals Vg2obtained by inverting the second selection signals Vg1.

More specifically, as illustrated inFIG. 30, the second selection circuit152may output signals corresponding to the second selection signals Vg1from a holding period tcg11to a holding period tcg14and output signals corresponding to the second selection signals Vg2from a holding period tcg21to a second holding period tcg24. While the second selection circuit152finishes outputting all the combination patterns included in the second selection signals Vg1and then outputs the combination patterns included in the second selection signals Vg2inFIG. 30, the present embodiment is not limited thereto. The second selection circuit152may output one combination pattern included in the second selection signals Vg1and then output the second selection signals Vg2obtained by inverting the combination pattern.

If the second selection circuit152performs inversion control as described above, the first selection circuit151and the second selection circuit152do not require any inversion control circuit, which will be described later. Specifically, the detection apparatus1does not require any circuit that generates and outputs the inversion control signal Vs as illustrated inFIG. 40, which will be described later, or an inversion control circuit155illustrated inFIG. 39.

FIG. 31is a table indicating the relation between the first electrode blocks and the selection signals in the third detection mode.FIG. 32is a timing waveform chart of the first electrode selection circuit in the third detection mode.

In the third detection mode M3(refer toFIG. 10), the detection apparatus1performs fingerprint detection on the first partial region FA1, which is part of the detection region FA. As illustrated inFIG. 31, the first electrode block selection circuit154turns on (“1”) the first electrode block selection signals Vh corresponding to the first electrode blocks BK2and BK3out of all the first electrode blocks BK based on the mask control signal MASK_STV. The first electrode block selection circuit154turns off (“0”) the first electrode block selection signals Vh corresponding to the first electrode blocks BK1and BK4. As a result, part of the first electrode blocks BK, that is, the first electrode blocks BK2and BK3are selected.

The second selection circuit152provides the second selection signals Vg corresponding to the selected first electrode blocks BK2and BK3. The first selection circuit151generates the first selection signals Vc in the same manner as illustrated inFIG. 27. The third selection circuit153multiplies the first selection signals Vc by the second selection signals Vg, thereby generating the second drive signals Vtx2. The third selection circuit153supplies the second drive signals Vtx2to the first electrode blocks BK2and BK3selected by the first electrode block selection circuit154. The detection apparatus1thus can perform CDM drive on the first partial region FA1, which is part of the detection region FA.

As illustrated inFIG. 32, in the first period tc1, the mask control signal MASK_STV at a high-level voltage is transmitted to the flip-flop circuits163corresponding to the first electrode blocks BK2and BK3in the first electrode block selection circuit154based on the mask clock signal MASK_CKV. As a result, the first electrode blocks BK2and BK3out of all the first electrode blocks BK are selected.

In the second period tc2and the fourth period tc4, the code control signal CODE_STV is supplied to the flip-flop circuits161corresponding to the first electrode blocks BK2and BK3in the second selection circuit152. The detection apparatus1thus performs CDM drive on the first electrode blocks BK2and BK3selected from all the first electrode blocks BK. The operations performed by the first selection circuit151in the third period tc3and the fifth period tc5are the same as those illustrated inFIG. 28.

FIG. 33is a table indicating the relation between the first electrode blocks and the selection signals in TDM drive in the first detection mode.FIG. 34is a timing waveform chart of the first electrode selection circuit in TDM drive in the first detection mode.

As illustrated inFIG. 33, in TDM drive in the first detection mode M1(refer toFIG. 8), the first selection circuit151turns off (“0”) all the first selection signals Vc. The second selection circuit152turns on (“1”) all the second selection signals Vg. As a result, CDM drive is not performed. The first electrode block selection circuit154turns on (“1”) the first electrode block selection signal Vh corresponding to the first electrode block BK2out of the first electrode blocks BK. As a result, the first drive signal Vtx1is supplied to the first electrode block BK2. The first electrode block selection circuit154sequentially selects the first electrode blocks BK1, BK2, BK3, and BK4. As a result, the third selection circuit153supplies the first drive signals Vtx1to the respective selected first electrode blocks BK in a time-division manner. InFIG. 33, the same first drive signal Vtx1is supplied to all the first electrodes Tx in the selected first electrode block BK2. The detection apparatus1thus can perform touch detection by TDM drive.

As illustrated inFIG. 34, in a first period td1, the code control signal CODE_STV is supplied to the flip-flop circuits161in the second selection circuit152based on the code clock signal CODE_CKV. As a result, all the first electrode blocks BK are selected. In a second period td2, the mask control signal MASK_STV at a high-level voltage is sequentially supplied to the flip-flop circuits163in the first electrode block selection circuit154based on the mask clock signal MASK_CKV. As a result, the first electrode block BK1is selected in the second period td2, for example. In and after a third period td3, the detection apparatus1performs the same operation as that performed in the second period td2, thereby sequentially selecting the first electrode blocks BK2, BK3, and BK4. The number of periods for supplying all the first drive signals Vtx1in the first detection mode M1is four, which is equal to the number of first electrode blocks BK.

As described above, the period in which the first electrode selection circuit15supplies all the second drive signals Vtx2based on the predetermined code to the first electrodes Tx in the second detection mode M2(refer toFIG. 28) is longer than the period in which the first electrode selection circuit15sequentially supplies the first drive signals Vtx1to all the first electrode blocks BK in the first detection mode M1(refer toFIG. 34). In the example illustrated inFIG. 28, the number of periods for supplying all the second drive signals Vtx2in the second detection mode M2is 32 in total. In the example illustrated inFIG. 34, the number of periods for supplying all the first drive signals Vtx1in the first detection mode M1is four.

InFIG. 33, the first electrode selection circuit15supplies the same first drive signal Vtx1to all the first electrodes Tx in the selected first electrode block BK2. The present embodiment is not limited thereto, and the first electrode selection circuit15may supply the first drive signal Vtx1to part of the first electrodes Tx in the selected first electrode block BK2. The first selection circuit151, for example, may provide the first selection signals Vc corresponding to the first electrodes Tx supplied with no first drive signal Vtx1in the first electrode block BK2, thereby performing thinned-out drive. Consequently, the detection apparatus1can reduce power consumption.

FIG. 35is a table indicating the relation between the first electrode blocks and the selection signals in CDM drive in the first detection mode.FIG. 36is a timing waveform chart of the first electrode selection circuit in CDM drive in the first detection mode.

As illustrated inFIG. 35, in CDM drive in the first detection mode M1(refer toFIG. 8), the first electrode block selection circuit154supplies the first electrode block selection signals Vh at a high-level voltage to the third selection circuit153. As a result, the first electrode block selection signals Vh corresponding to all the first electrode blocks BK are turned on (“1”), and all the first electrode blocks BK are selected. The first selection circuit151supplies the first selection signals Vc at a low-level voltage to the third selection circuit153. As a result, all the first selection signals Vc are turned off (“0”), and CDM drive is not performed in units of the first electrode Tx.

The second selection circuit152supplies, to the third selection circuit153, the second selection signals Vg having the phases determined based on the predetermined code for the respective first electrode blocks BK. As a result, the first drive signals Vtx1are supplied to the first electrode blocks BK selected based on the predetermined code. The second selection circuit152outputs the second selection signals Vg with different combination patterns of the second selection signals Vg for the respective first electrode blocks BK. The detection apparatus1thus performs touch detection by CDM drive.

As illustrated inFIG. 36, in the first period td1, the mask control signal MASK_STV at a high-level voltage is supplied to the flip-flop circuits163in the first electrode block selection circuit154based on the mask clock signal MASK_CKV. As a result, all the first electrode blocks BK are selected. In the second period td2, the first drive signals Vtx1are supplied to the respective first electrode blocks BK by the operations of the second selection circuit152. In and after the third period td3, the first drive signals Vtx1are supplied to another combination of the first electrode blocks BK different from that in the second period td2.

In the fourth detection mode M4, the detection apparatus1performs CDM drive in the same manner as that in the third detection mode M3on a partial region including the first electrode blocks BK in which an external proximity object is detected in the first detection mode M1. More specifically, the first electrode block selection circuit154outputs the first electrode block selection signals Vh so as to select the partial region including the first electrode blocks BK in which the external proximity object is detected in the first detection mode M1. Explanation of the operations performed by the first selection circuit, the second selection circuit, and the third selection circuit is omitted because the operations are the same as those in the third detection mode M3.

As described above, the first electrode selection circuit15includes the first selection circuit151, the second selection circuit152, the third selection circuit153, and the first electrode block selection circuit154. With this configuration, the detection apparatus1can satisfactorily perform the first detection mode M1and the second detection mode M2. Furthermore, the detection apparatus1can perform partial detection of performing detection on part of the detection region FA, for example, in the third detection mode M3and the fourth detection mode M4. The first electrode block selection circuit154and the second selection circuit152have functions of selecting the first electrode blocks BK in the first detection mode M1. With this configuration, the detection apparatus1does not require another control circuit for touch detection or another switching circuit that switches between touch detection and fingerprint detection. As a result, the circuit size can be reduced. The first selection circuit151provides the first selection signals Vc based on the predetermined code. This configuration requires a smaller number of external terminals and wires used to supply the control signals from the outside to the first selection circuit151.

While the first selection circuit151includes the counter circuit17as illustrated inFIGS. 14 and 15, the present embodiment is not limited thereto. The first selection circuit151does not necessarily include the counter circuit17but may include the first code generation circuit12, the second code generation circuit13, and the third code generation circuit14. In this case, the external detection controller11(refer toFIG. 3) may supply the inversion control signal Vs, the first control signals Va1, Va2, and Va3, and the second control signals Vb1, Vb2, and Vb3illustrated inFIG. 16to the first code generation circuit12and the second code generation circuit13.

FIG. 37is a circuit diagram for explaining the first electrode drive circuit.FIG. 38is a diagram for explaining the first drive signal and the second drive signal.FIG. 39is a graph schematically illustrating the relation between a voltage supplied to the first electrode and S/N.FIG. 40is a circuit diagram for explaining another example of the first electrode drive circuit.FIG. 41is a circuit diagram of the detection electrode selection circuit according to the first embodiment.FIG. 42is a circuit diagram of the AFE circuit according to the first embodiment.

A charge amount q detected by the detector40is determined by Expression (4) where d is the distance between the first electrode Tx and a proximity object (e.g., a finger), Stx is the area of the first electrode block BK or the individual first electrode Tx, V is the voltage value of the first drive signal Vtx1or the second drive signal Vtx2, and is the permittivity between the first electrode Tx and the proximity object (e.g., a finger), such as the permittivity of the cover member101or the combined permittivity of the cover member101and an air layer.

As illustrated inFIGS. 8 and 9, the first detection pitch Pts in the first detection mode M1is significantly different from the second detection pitch Pf in the second detection mode M2. The first detection pitch Pts is 4 mm or larger or 1 mm or larger, for example. The second detection pitch Pf is 50 μm or larger and 100 μm or smaller, for example. As a result, Stx significantly varies in Expression (4). With the same drive voltage and the same detector40, detection may possibly fail to be satisfactorily performed in one of the first detection mode M1and the second detection mode M2.

As illustrated inFIG. 37, the first electrode drive circuit170includes a first drive signal generator171, a second drive signal generator172, a first switching element Tr1, and a second switching element Tr2. The first drive signal generator171is a circuit that generates the first drive signals Vtx1of an AC rectangular wave and supplies them to a first wire L1. The second drive signal generator172is a circuit that generates the second drive signals Vtx2of an AC rectangular wave and supplies them to a second wire L2.

When the same drive voltage selection signal TP_VENB is supplied, the first switching element Tr1and a second switching element Tr2are turned on and off in an opposite manner. In other words, if the first switching element Tr1is turned on, the second switching element Tr2is turned off. If the first switching element Tr1is turned off, the second switching element Tr2is turned on.

In the first detection mode M1, the drive voltage selection signal TP_VENB at a high-level voltage is supplied. Due to the drive voltage selection signal TP_VENB, the first switching element Tr1is turned on, and the second switching element Tr2is turned off. As a result, the first drive signal generator171is coupled to the buffer166via the first wire L1and a third wire L3. The second drive signal generator172is decoupled from the buffer166. The first drive signals Vtx1are supplied to the selected first electrode blocks BK via the buffer166.

In the second detection mode M2or the third detection mode M3, the drive voltage selection signal TP_VENB at a low-level voltage is supplied. Due to the drive voltage selection signal TP_VENB, the first switching element Tr1is turned off, and the second switching element Tr2is turned on. As a result, the first drive signal generator171is decoupled from the buffer166. The second drive signal generator172is coupled to the buffer166via the second wire L2and the third wire L3. The second drive signals Vtx2are supplied to the selected first electrodes Tx via the buffer166.

As illustrated inFIG. 38, the first drive signal Vtx1is an AC rectangular wave in which a third voltage V3(e.g., a ground voltage GND) and a first voltage V1higher than the third voltage V3alternately appear. The second drive signal Vtx2is an AC rectangular wave in which a fourth voltage V4(e.g., the ground voltage GND) and a second voltage V2higher than the fourth voltage V4alternately appear. The second voltage V2is higher than the first voltage V1. In other words, the first drive signal Vtx1has a first potential difference ΔV1between the ground voltage GND corresponding to a low-level voltage and the first voltage V1corresponding to a high-level voltage. The second drive signal Vtx2has a second potential difference ΔV2between the ground voltage GND corresponding to a low-level voltage and the second voltage V2corresponding to a high-level voltage. The second potential difference ΔV2is larger than the first potential difference ΔV1.

Both of the low-level voltage (third voltage V3) of the first drive signal Vtx1and the low-level voltage (fourth voltage V4) of the second drive signal Vtx2are the ground voltage GND. The third voltage V3and the fourth voltage V4, however, may be different voltages if the second potential difference ΔV2is larger than the first potential difference ΔV1. The frequency of the first drive signal Vtx1is equal to that of the second drive signal Vtx2. A pulse width W1of one pulse of the first drive signal Vtx1is equal to a pulse width W2of one pulse of the second drive signal Vtx2. The present embodiment is not limited thereto, and the pulse width W2of the second drive signal Vtx2may be larger than the pulse width W1of the first drive signal Vtx1.

The first electrode drive circuit170operates to supply the first drive signals Vtx1to the first electrode blocks BK (refer toFIG. 14) in a first detection period td for performing the first detection mode M1. The first electrode drive circuit170operates to supply the second drive signals Vtx2at a voltage level different from that of the first drive signals Vtx1to the first electrodes Tx (refer toFIG. 15) in a second detection period tc for performing the second detection mode M2or the third detection mode M3. The second drive signal Vtx2has a voltage level (second voltage V2) higher than that of the first drive signal Vtx1. In other words, the detection apparatus1supplies the first drive signals Vtx1in the first detection period td for performing touch detection and supplies the second drive signals Vtx2in the second detection period tc for performing fingerprint detection.

FIG. 39illustrates the S/N ratio of the detection signals Vdet output from the sensor in the second detection mode M2. More specifically,FIG. 39illustrates the S/N ratio of the output signals from a second AFE circuit48B (refer toFIGS. 41 and 42) included in the detector40. As illustrated inFIG. 39, if the voltage of the second drive signal Vtx2in the second detection mode M2is set to the first voltage V1, which is the voltage of the first drive signal Vtx1, the S/N ratio is smaller than a reference value CL indicated by the dotted line. The present embodiment sets the voltage of the second drive signal Vtx2to the second voltage V2higher than the first voltage V1. As a result, the S/N ratio is larger than the reference value CL.

If the detection pitch differs between the first detection mode M1and the second detection mode M2, making the second voltage V2higher than the first voltage V1can reduce the difference of the charge amount q in Expression (4). Consequently, the detection apparatus1can satisfactorily perform detection in the first detection mode M1and the second detection mode M2using the same detector40.

As illustrated inFIG. 14, the first electrode drive circuit170is provided on the sensor substrate21. The configuration is not limited thereto, and part or all of the first electrode drive circuit170may be provided on an external control substrate or the flexible printed circuit board76(refer toFIG. 5).

The configuration of the first electrode drive circuit170illustrated inFIG. 37is given by way of example only and may be appropriately modified. As illustrated inFIG. 40, a first electrode drive circuit170A may include a first drive signal generator171A, a second drive signal generator172A, and switches SW1, SW2, and SW3. The first drive signal generator171A includes a first voltage generator173and a third voltage generator174. The second drive signal generator172A includes a second voltage generator175and a fourth voltage generator176.

The first voltage generator173is a circuit that generates DC voltage signals VDC1having the same potential as that of the first voltage V1(refer toFIG. 38). The third voltage generator174is a circuit that generates DC voltage signals VDC3having the same potential (e.g., the ground voltage GND) as that of the third voltage V3lower than the first voltage V1. The switch SW2is alternately turned on and off, whereby the first drive signal generator171A can generate the first drive signals Vtx1serving as AC signals.

The second voltage generator175is a circuit that generates DC voltage signals VDC2having the same potential as that of the second voltage V2(refer toFIG. 38). The fourth voltage generator176is a circuit that generates DC voltage signals VDC4having the same potential (e.g., the ground voltage GND) as that of the fourth voltage V4lower than the second voltage V2. The switch SW3is alternately turned on and off, whereby the second drive signal generator172A can generate the second drive signals Vtx2serving as AC signals.

The switch SW1is turned on and off by the drive voltage selection signal TP_VENB. The switch SW1may have the same configuration as that of the first switching element Tr1and the second switching element Tr2illustrated inFIG. 37, for example. In the first detection mode M1, the first drive signal generator171A is coupled to the buffer166by an operation of the switch SW1. The second drive signal generator172A is decoupled from the buffer166. The first drive signals Vtx1are thus supplied to the selected first electrode blocks BK via the buffer166. In the second detection mode M2, the first drive signal generator171A is decoupled from the buffer166by an operation of the switch SW1. The second drive signal generator172A is coupled to the buffer166. The second drive signals Vtx2are thus supplied to the selected first electrodes Tx via the buffer166.

FIG. 41is a circuit diagram of the detection electrode selection circuit according to the first embodiment.FIG. 42is a circuit diagram of the AFE circuit according to the first embodiment. As illustrated inFIG. 41, second electrode blocks BKR each include a plurality of second electrodes Rx-1, Rx-2, . . . , and Rx-8. InFIG. 41, 128 second electrodes Rx, that is, second electrodes Rx-1to Rx-128are provided. The detection electrode selection circuit16includes third switching elements Tr3, fourth switching elements Tr4, fifth switching elements Tr5, sixth switching elements Tr6, a reference potential supply line Lr0, second electrode selection signal lines Lr1, Lr2, . . . , and Lr8, first output signal lines Lsig1, and second output signal lines Lsig2. The second electrode blocks BKR are each coupled to two output signal lines, that is, the first output signal line Lsig1and the second output signal line Lsig2. The detection electrode selection circuit16selects the second electrodes Rx to be a target of detection based on the second electrode selection signals Vhsel.

The first output signal line Lsig1is coupled to a first AFE circuit (AFE-TP)48A via the fifth switching element Tr5and a first coupling wire Lout1. A plurality of first output signal lines Lsig1are coupled to one first coupling wire Lout1. In other words, a plurality of second electrode blocks BKR are collectively coupled to the first AFE circuit48A.

The second output signal line Lsig2is coupled to a second AFE circuit (AFE-FP)48B via the sixth switching element Tr6and a second coupling wire Lout2. One second output signal line Lsig2is coupled to one second coupling wire Lout2. In other words, a plurality of second AFE circuits48B are provided for the respective second electrode blocks BKR.

In the first detection mode M1, a first detection switching signal FP_ENB at a low-level voltage is supplied to the sixth switching elements Tr6. In other words, to perform touch detection, the first detection switching signal FP_ENB at a low-level voltage is supplied to the sixth switching elements Tr6. A second enable signal xFP_ENB at a high-level voltage is supplied to the fifth switching elements Tr5. As a result, the fifth switching elements Tr5are turned on, and the sixth switching elements Tr6are turned off. Consequently, in the first detection mode M1, a plurality of second electrode blocks BKR are collectively coupled to the first AFE circuit48A via the first coupling wire Lout1.

In the second detection mode M2or the third detection mode, the first detection switching signal FP_ENB at a high-level voltage is supplied to the sixth switching elements Tr6. In other words, the first detection switching signal FP_ENB at a high-level voltage is supplied to the sixth switching elements Tr6. The second enable signal xFP_ENB at a low-level voltage is supplied to the fifth switching elements Tr5. As a result, the fifth switching elements Tr5are turned off, and the sixth switching elements Tr6are turned on. Consequently, in the second detection mode M2, the second electrode blocks BKR are coupled to the respective second AFE circuits48B via the respective second coupling wires Lout2. The second enable signal xFP_ENB is an inversion signal of the first detection switching signal FP_ENB.

The second electrodes Rx are each coupled to the third switching element Tr3and the fourth switching element Tr4. Second electrode selection signals Vhsel are supplied to the third switching elements Tr3and the fourth switching elements Tr4via the second electrode selection signal lines Lr1, Lr2, . . . , and Lr8, respectively. When the same second electrode selection signal Vhsel is supplied, the third switching element Tr3and the fourth switching element Tr4are turned on and off in an opposite manner. In other words, if the third switching element Tr3is turned on, the fourth switching element Tr4is turned off. If the third switching element Tr3is turned off, the fourth switching element Tr4is turned on. The second electrode selection signals Vhsel can be generated based on various control signals supplied from the detection controller11, for example.

The third switching element Tr3and the fourth switching element Tr4operate to switch the coupling state of the corresponding second electrode Rx included in the second electrode block BKR to the first output signal line Lsig1and the second output signal line Lsig2. If the third switching element Tr3is turned on, the second electrode Rx is coupled to the first output signal line Lsig1and the second output signal line Lsig2. If the fourth switching element Tr4is turned on, the second electrode Rx is coupled to the reference potential supply line Lr0.

The second electrode selection signal Vhsel is a selection signal based on a predetermined code. The predetermined code is defined by the square matrix in Expression (2), for example. The second electrode selection signal Vhsel is generated by a circuit similar to the first code generation circuit12(refer toFIG. 17) or the second code generation circuit13(refer toFIG. 19). If the second electrode selection signal Vhsel corresponding to the elements “1” in Expression (2) is supplied, the third switching element Tr3is turned on. If the second electrode selection signal Vhsel corresponding to the elements “−1” in Expression (2) is supplied, the fourth switching element Tr4is turned on. As a result, the second electrodes Rx are selected based on the predetermined code similarly to CDM drive illustrated inFIG. 13.

Specifically, if a plurality of second electrodes Rx corresponding to the elements “1” in Expression (2) are selected, the selected second electrodes Rx are coupled to the second output signal line Lsig2. A first output signal Vout1obtained by integrating the first detection signals Vdet1from the selected second electrodes Rx is output from the second output signal line Lsig2. Non-selected second electrodes Rx are coupled to the reference potential supply line Lr0and supplied with a reference potential signal Vref. The reference potential signal Vref is a DC voltage signal having the same potential as that of the voltage signals supplied to the second electrodes Rx in detection. This mechanism can suppress capacitive coupling between the selected second electrodes Rx and the non-selected second electrodes Rx. Consequently, the present embodiment can reduce detection errors and suppress reduction in detection sensitivity.

If a plurality of second electrodes Rx corresponding to the elements “−1” in Expression (2) are selected, the selected second electrodes Rx are coupled to the second output signal line Lsig2. A second output signal Vout2obtained by integrating the second detection signals Vdet2from the selected second electrodes Rx is output from the second output signal line Lsig2. Non-selected second electrodes Rx are coupled to the reference potential supply line Lr0and supplied with the reference potential signal Vref. The signal processor44calculates a third output signal Vout3, which is the value of difference between the first output signal Vout1and the second output signal Vout2.

In the example represented by Expression (2), the order of the square matrix is eight, and eight combination patterns of the second electrodes Rx are obtained. In other words, eight third output signals Vout3are obtained corresponding to the different combination patterns of the second electrodes Rx. The signal processor44decodes the eight third output signals Vout3using a transpose of the square matrix in Expression (2). Based on the decoded signal resulting from the operation, the detection apparatus1can detect contact or proximity of the external proximity object CQ or unevenness on the surface of the external proximity object CQ facing the detection surface.

The detection apparatus1according to the present embodiment performs CDM drive on both of the first electrodes Tx and the second electrodes Rx. Consequently, if the arrangement interval Pt of the first electrodes Tx is small, and the area of the electrode portions23aand23bis small, or if the width (area) of the second electrodes Rx is small, the detection apparatus1can increase the detection sensitivity. The number of second electrodes Rx included in the second electrode block BKR may be seven or less or nine or more.

In TDM drive, fourth output signals Vout4from a plurality of second electrode blocks BKR are integrated and output to the first output signal lines Lsig1. Consequently, the detection apparatus1can appropriately set the detection resolution. In TDM drive, one or a plurality of second electrodes Rx in each of the second electrode blocks BKR may be brought into a non-selected state by the operations of the third switching elements Tr3and the fourth switching elements Tr4. The detection apparatus1thins out the second electrodes Rx in detection, thereby appropriately setting the signal intensity of the fourth output signals Vout4.

As illustrated inFIG. 42, the first AFE circuit48A and the second AFE circuit48B each include the detection signal amplifier42and the A/D converter43. The detection signal amplifier42includes an amplifier421, a capacitor49A, and a switch SW11. The detection signal amplifier42and the A/D converter43are included in the detector40illustrated inFIG. 3. The first AFE circuit48A and the second AFE circuit48B are analog signal processing circuits that convert the output signals Vout from the second electrode blocks BKR into digital signals and output them to the signal processor44. The output signal Vout illustrated inFIG. 42is any one of the first output signal Vout1, the second output signal Vout2, and the fourth output signal Vout4.

The capacitance of the capacitor49A in the first AFE circuit48A and the second AFE circuit48B is set depending on the voltage value of the output signals Vout. The detection signal amplifier42is reset by an operation of the switch SW11.

In the second detection mode M2, the first electrode drive circuit170(refer toFIG. 37) according to the present embodiment supplies the second drive signals Vtx2at a voltage level higher than that of the first drive signals Vtx1to the first electrodes Tx. This mechanism reduces the difference between the output signals Vout supplied to the first AFE circuit48A and the second AFE circuit48B. Consequently, the first AFE circuit48A and the second AFE circuit48B can have the same configuration.

The first AFE circuit48A and the second AFE circuit48B may have the respective capacitors49A having different capacitance. In the configuration according to the present embodiment, the capacitance value of the capacitor49A of the first AFE circuit48A is larger than that of the capacitor49A of the second AFE circuit48B.

FIG. 43is a circuit diagram of another example of the detection electrode selection circuit according to the first embodiment.FIG. 44is a circuit diagram of another example of the AFE circuit according to the first embodiment. As illustrated inFIG. 43, in a detection electrode selection circuit16A according to the present modification, the first coupling wire Lout1and the second coupling wires Lout2are coupled to a common AFE circuit48via a coupling switching circuit177.

The coupling switching circuit177is a switching circuit, such as a multiplexer. In the first detection mode M1, the coupling switching circuit177couples the first coupling wire Lout1to the AFE circuit48but does not couple the second coupling wires Lout2to the AFE circuit48. In other words, to perform touch detection, the coupling switching circuit177is coupled to a plurality of second electrode blocks BKR via the first coupling wire Lout1. The coupling switching circuit177integrates and outputs the output signals from the second electrode blocks BKR to the AFE circuit48. In the second detection mode M2or the third detection mode, the coupling switching circuit177couples the second coupling wires Lout2to the AFE circuit48but does not couple the first coupling wire Lout1to the AFE circuit48. In other words, to perform fingerprint detection, the coupling switching circuit177is coupled to a plurality of second electrode blocks BKR via the respective second coupling wires Lout2. The coupling switching circuit177outputs the output signals from the second electrode blocks BKR to the AFE circuit48in a time-division manner.

With this configuration, the first output signals Vout1, the second output signals Vout2, or the fourth output signals Vout4are supplied from the second electrode blocks BKR to the common AFE circuit48.

As illustrated inFIG. 44, the AFE circuit48includes a detection signal amplifier42A and the A/D converter43. The detection signal amplifier42A includes the amplifier421, a first capacitor49B, a second capacitor49C, the switch SW11, and a switch SW12. In the present modification, the first capacitor49B has a capacitance value larger than that of the second capacitor49C. One of the first capacitor49B and the second capacitor49C is coupled to the amplifier421by an operation of the switch SW12.

In the first detection mode M1, the output wire for the output signals Vout from the second electrodes Rx is coupled to the first capacitor49B by an operation of the switch SW12. In other words, to perform touch detection, the output wire for the output signals Vout from the second electrodes Rx is coupled to the first capacitor49B by an operation of the switch SW12. In the second detection mode M2or the third detection mode, the output wire for the output signals Vout from the second electrodes Rx is coupled to the second capacitor49C by an operation of the switch SW12. In other words, to perform fingerprint detection, the output wire for the output signals Vout from the second electrodes Rx is coupled to the second capacitor49C by an operation of the switch SW12. As a result, the first capacitor49B and the second capacitor49C are switched depending on the voltage of the output signals Vout supplied to the AFE circuit48. Consequently, the detection apparatus1can perform satisfactory detection if the detection pitch differs between the first detection mode M1and the second detection mode M2, for example.

The AFE circuit48illustrated inFIG. 44is given by way of example only and may be appropriately modified. The AFE circuit48, for example, may have the same configuration as that of the first AFE circuit48A or the second AFE circuit48B illustrated inFIG. 42. In this case, the AFE circuit48may include a variable capacitance element as the capacitor49A.

FIG. 45is a circuit diagram of still another example of the detection electrode selection circuit according to the first embodiment. A detection electrode selection circuit16B according to the present modification includes a counter circuit17A and a fourth selection circuit158. The counter circuit17A according to the present modification operates based on a clock signal CLK and a reset signal RST supplied from the detection controller11. The counter circuit17A includes the flip-flop circuits18a,18b,18c, and18dof four stages, for example. The counter circuit17A outputs an inversion control signal Vsa and a control signal Vba to the fourth selection circuit158.

The fourth selection circuit158has the same circuit configuration as that of the second code generation circuit13illustrated inFIG. 15, for example. The fourth selection circuit158generates the second electrode selection signals Vhsel based on the inversion control signal Vsa and the three control signals Vba. The second electrode selection signals Vhsel are supplied to the third switching elements Tr3and the fourth switching elements Tr4via the second electrode selection signal lines Lr1, Lr2, Lr3, . . . , and Lr8, respectively. The detection electrode selection circuit16B thus can perform CDM drive on the second electrodes Rx. In the present modification, the number of external input terminals of the detection electrode selection circuit16B is two, which is the number of input terminals of the counter circuit17A. This configuration can simplify the coupling between the detection electrode selection circuit16B and the detection controller11and reduce the circuit size. The fourth selection circuit158may have the same configuration as that of the first code generation circuit12and the second code generation circuit13. In other words, the detection electrode selection circuit16B may have the same circuit configuration as that of the first selection circuit151. The detection electrode selection circuit16B does not necessarily include the counter circuit17A and may be supplied with the control signals Vba1and Vba2from an external controller.

Second Embodiment

FIG. 46is a block diagram of the first electrode selection circuit according to a second embodiment of the present disclosure.FIG. 47is a block diagram of the first selection circuit of the first electrode selection circuit according to the second embodiment. As illustrated inFIG. 46, in a detection apparatus1A according to the present embodiment, a first electrode selection circuit15A includes the first selection circuit151, the second selection circuit152, the third selection circuit153, the first electrode block selection circuit154, and an inversion control circuit155. The inversion control circuit155inverts “1” and “0” of the predetermined code illustrated inFIG. 20, for example.

The inversion control circuit155includes a plurality of XOR circuits167. The XOR circuits167are provided for the respective first electrode blocks BK. The XOR circuit167calculates Xor of an inversion control signal VINV supplied from the outside and the second selection signal Vg supplied from the second selection circuit152. The inversion control circuit155outputs calculated fourth selection signals Vi to the third selection circuit153.

The XOR circuits164of the third selection circuit153output Xor of the fourth selection signal Vi and the first selection signal Vc to the respective NAND circuits165as the third selection signal Vk. The NAND circuit165receives the first electrode block selection signal Vh and calculates nand of the third selection signal Vk and the first electrode block selection signal Vh. In other words, if the first electrode block selection signal Vh is at a high-level voltage, the NAND circuit165outputs the first electrode selection signal Vsel corresponding to the third selection signal Vk to the buffer166. If the first electrode block selection signal Vh is at a low-level voltage, the NAND circuit165outputs the first electrode selection signal Vsel at a low-level voltage to the buffer166. The buffer166substantially simultaneously supplies the first drive signals Vtx1or the second drive signals Vtx2supplied from the first electrode drive circuit170to a plurality of first electrode blocks BK selected based on the first electrode selection signals Vsel. In other words, the third selection circuit153generates the drive signals Vtx (the first drive signals Vtx1or the second drive signals Vtx2) based on Expression (5).

The present embodiment includes the inversion control circuit155. With this configuration, as illustrated inFIG. 47, the second code generation circuit13does not require the second input terminal S (refer toFIG. 15) that receives the inversion control signal Vs. The counter circuit17includes the flip-flop circuits18a,18b,18c,18d,18e, and18fof six stages. The second code generation circuit13is supplied with the power source voltage Vdd instead of the inversion control signal Vs.

The output signal from the flip-flop circuit18ais supplied to the second input terminal B3of the second code generation circuit13as the second control signal Vb3. The output signal from the flip-flop circuit18bis supplied to the second input terminal B2of the second code generation circuit13as the second control signal Vb2. Similarly, the flip-flop circuits18c,18d,18e, and18foutput the second control signal Vb1and the first control signals Va3, Va2, and Va1, respectively.

The counter circuit17according to the present embodiment can have a simpler configuration than in the example illustrated inFIG. 15. Specifically, the present embodiment requires a smaller number of terminals and wires that couple the counter circuit17and the second code generation circuit13. Also in the configuration according to the present embodiment, the first code generation circuit12, the second code generation circuit13, and the third code generation circuit14can generate the pattern code with64order illustrated inFIG. 20, for example, based on the output signals from the flip-flop circuits18of six stages. The present embodiment can generate a pattern code obtained by replacing “1” with “0” in the pattern code illustrated inFIG. 20, for example, by the operations of the inversion control circuit155.

FIG. 48is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned off in the second detection mode. FIG.49is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned on in the second detection mode.

As illustrated inFIGS. 48 and 49, in the second detection mode M2(refer toFIG. 9), the first electrode block selection circuit154turns on (“1”) the first electrode block selection signals Vh corresponding to all the first electrode blocks BK based on the mask control signal MASK_STV. As a result, all the first electrode blocks BK are selected. The first selection circuit151and the second selection circuit152provide the first selection signals Vc and the second selection signals Vg, respectively, having the phases determined based on the predetermined code.

InFIG. 48, the inversion control signal VINV is turned off (“0”), whereby no inversion operation is performed. The third selection circuit153performs calculation based on Expression (5) to generate the second drive signals Vtx2. InFIG. 49, the inversion control signal VINV is turned on (“1”), whereby the predetermined code is inverted. The third selection circuit153performs calculation based on Expression (5) to generate second drive signals Vtx2obtained by inverting the second drive signals Vtx2illustrated inFIG. 48. In other words, if the inversion control signal VINV is turned on, the second drive signals Vtx2are supplied to the first electrodes Tx not selected when the inversion control signal VINV is turned off, but no second drive signal Vtx2is supplied to the first electrodes Tx selected when the inversion control signal VINV is turned off. The detection apparatus1A thus can perform CDM drive on the whole surface of the detection region FA.

FIG. 50is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned off in the third detection mode.FIG. 51is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned on in the third detection mode.

In the third detection mode M3(refer toFIG. 10), the detection apparatus1A performs fingerprint detection on the first partial region FA1, which is part of the detection region FA. As illustrated inFIG. 50, the first electrode block selection circuit154turns on (“1”) the first electrode block selection signals Vh corresponding to the first electrode blocks BK2and BK3out of all the first electrode blocks BK based on the mask control signal MASK_STV. The first electrode block selection circuit154turns off (“0”) the first electrode block selection signals Vh corresponding to the first electrode blocks BK1and BK4. As a result, part of the first electrode blocks BK, that is, the first electrode blocks BK2and BK3are selected.

The second selection circuit152provides the second selection signals Vg corresponding to the selected first electrode blocks BK2and BK3. The first selection circuit151generates the first selection signals Vc in the same manner as illustrated inFIGS. 48 and 49. InFIG. 50, the inversion control signal VINV is turned off (“0”), whereby no inversion operation is performed. The third selection circuit153performs calculation based on Expression (5) to generate the second drive signals Vtx2. The third selection circuit153supplies the second drive signals Vtx2to the selected first electrode blocks BK2and BK3. InFIG. 51, the inversion control signal VINV is turned on (“1”), whereby the predetermined code is inverted. The third selection circuit153performs calculation based on Expression (5) to generate second drive signals Vtx2having the phases opposite to those of the second drive signals Vtx2illustrated inFIG. 50. The detection apparatus1A thus can perform CDM drive on the first partial region FA1, which is part of the detection region FA.

FIG. 52is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned off in TDM drive in the first detection mode.FIG. 53is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned on in TDM drive in the first detection mode.

As illustrated inFIG. 52, in TDM drive in the first detection mode M1(refer toFIG. 8), the first selection circuit151turns off (“0”) all the first selection signals Vc. The second selection circuit152turns on (“1”) all the second selection signals Vg. As a result, CDM drive is not performed. The first electrode block selection circuit154turns on (“1”) the first electrode block selection signal Vh corresponding to the first electrode block BK2out of the first electrode blocks BK. InFIG. 52, the inversion control signal VINV is turned off (“0”), whereby no inversion operation is performed. As a result, the first drive signal Vtx1is supplied to the first electrode block BK2selected by the first electrode block selection circuit154. The first electrode block selection circuit154sequentially selects the first electrode blocks BK1, BK2, BK3, and BK4. As a result, the first drive signals Vtx1are sequentially supplied to the respective selected first electrode blocks BK. InFIG. 52, the same first drive signal Vtx1is supplied to all the first electrodes Tx in the selected first electrode block BK2. InFIG. 53, the inversion control signal VINV is turned on (“1”). As a result, no first drive signal Vtx1is supplied to the first electrode block BK2selected by the first electrode block selection circuit154. The detection apparatus1A thus can perform touch detection by TDM drive.

FIG. 54is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned off in CDM drive in the first detection mode.FIG. 55is a table indicating the relation between the first electrode blocks and the selection signals if the inversion control signal is turned on in CDM drive in the first detection mode.

As illustrated inFIG. 54, in CDM drive in the first detection mode M1(refer toFIG. 8), the first electrode block selection circuit154turns on (“1”) the first electrode block selection signals Vh corresponding to all the first electrode blocks BK. As a result, all the first electrode blocks BK are selected. The first selection circuit151turns off (“0”) all the first selection signals Vc. In other words, CDM drive is not performed in units of the first electrode Tx.

The second selection circuit152outputs the second selection signals Vg having the phases determined based on the predetermined code for the respective first electrode blocks BK. InFIG. 54, the inversion control signal VINV is turned off (“0”), whereby no inversion operation is performed. The third selection circuit153performs calculation based on Expression (5) to generate the second drive signals Vtx2. As a result, the first drive signals Vtx1are supplied to the first electrode blocks BK1and BK3selected based on the predetermined code. InFIG. 55, the inversion control signal VINV is turned on (“1”), whereby the predetermined code is inverted. The third selection circuit153performs calculation based on Expression (5) to generate the second drive signals Vtx2. As a result, the first drive signals Vtx1are supplied to the first electrode blocks BK2and BK4selected based on the predetermined code. The second selection circuit152outputs the second selection signals Vg with different combination patterns of the second selection signals Vg for the respective first electrode blocks BK. The detection apparatus1A thus performs touch detection by CDM drive.

Third Embodiment

FIG. 56is a block diagram of the first electrode selection circuit according to a third embodiment of the present disclosure. In a detection apparatus1B according to the present embodiment, a first electrode selection circuit15B includes the first selection circuit151, the second selection circuit152, and an operation mode selection circuit156. The first selection circuit151is the same as that according to the first and the second embodiments. The second selection circuit152sequentially selects the first electrode blocks BK one by one based on the code reset signal CODE_RST, the code control signal CODE_STV, and the code clock signal CODE_CKV. The second selection circuit152does not include the latches162(refer toFIG. 14).

The operation mode selection circuit156includes a plurality of coupling switching circuits168. The coupling switching circuits168switch coupling of the respective first electrode blocks BK to the first selection circuit151and the second selection circuit152based on a selection signal Tx_SEL. In the first detection mode M1(refer toFIG. 8), the coupling switching circuits168couple the respective first electrode blocks BK to the second selection circuit152based on the selection signal Tx_SEL. The second selection circuit152sequentially outputs the second selection signals Vg to the coupling switching circuits168based on the code control signal CODE_STV and the code clock signal CODE_CKV. As a result, the first electrode blocks BK are sequentially selected, and the first electrode selection circuit15B supplies the first drive signals Vtx1to the selected first electrode blocks BK.

In the second detection mode M2(refer toFIG. 9), the coupling switching circuits168couple the respective first electrode blocks BK to the first selection circuit151based on the selection signal Tx_SEL. The first selection circuit151provides the first selection signals Vc based on the first reset signal FPS_RST and the first clock signal FPS_CLK. The first selection signals Vc are voltage signals having the phases determined based on the predetermined code for the respective first electrodes Tx. The coupling switching circuits168output the second drive signals Vtx2based on the first selection signals Vc to the first electrodes Tx in the respective first electrode blocks BK. The detection apparatus1B thus can perform CDM drive on the whole surface of the detection region FA.

In the third detection mode M3(refer toFIG. 10), the coupling switching circuits168couple part of the first electrode blocks BK to the first selection circuit151based on the selection signal Tx_SEL. As a result, the first electrode selection circuit15B supplies the second drive signals Vtx2to the selected first electrode blocks BK. The detection apparatus1B thus performs fingerprint detection on the first partial region FA1, which is part of the detection region FA.

The configuration according to the present embodiment does not include the third selection circuit153and the first electrode block selection circuit154(refer toFIG. 14). Consequently, the configuration can reduce the circuit size of the first electrode selection circuit15B.

Fourth Embodiment

FIG. 57is a sectional view of a schematic sectional structure of the display apparatus including the detection apparatus according to a fourth embodiment of the present disclosure.FIG. 58is a plan view of the detection apparatus according to the fourth embodiment. A display apparatus100A according to the present embodiment is an apparatus in which the display panel30and a detection apparatus1C are integrated. An apparatus in which the display panel30and the detection apparatus1C are integrated means an apparatus in which part of substrates and electrodes are shared by the display panel30and the detection apparatus1C, for example.

Specifically, as illustrated inFIG. 57, the display apparatus100A includes a pixel substrate2, a counter substrate3, and a liquid crystal layer6. The counter substrate3is disposed facing the pixel substrate2. The liquid crystal layer6is provided between the pixel substrate2and the counter substrate3.

The pixel substrate2includes the first substrate31, a plurality of pixel electrodes39, a plurality of first electrodes TxA, and an insulating layer85. The first substrate31is a circuit board provided with thin-film transistors (TFT) and various kinds of wiring. The pixel electrodes39are arrayed in a matrix (row-column configuration) on the first substrate31. The first electrodes TxA are provided between the first substrate31and the pixel electrodes39. The insulating layer85insulates the pixel electrodes39from the first electrodes TxA. The polarizing plate34is provided under the first substrate31with an adhesive layer36interposed therebetween.

The counter substrate3includes the second substrate32, a color filter38, and second electrodes RxA. The color filter38is provided on one surface of the second substrate32. The second electrodes RxA are provided on the other surface of the second substrate32. An insulating layer84is provided on the second substrate32to cover the second electrodes RxA. The polarizing plate35is provided on the insulating layer84with an adhesive layer37interposed therebetween. The first substrate31and the second substrate32according to the present embodiment are glass substrates or resin substrates, for example.

The first substrate31is coupled to a driver IC19and a flexible printed circuit board75A. The second substrate32is coupled to a flexible printed circuit board75B. The driver IC19is a control circuit that controls display and detection in the display apparatus100A. Part of the first electrode selection circuit15and part or all of the functions of the detection controller11and the detector40may be included in the driver IC19or in another touch IC or another control substrate. At least any one of the counter circuit17, the first electrode drive circuit170, and the AFE circuit48, for example, may be provided in the driver IC19, another touch IC, or another control substrate.

The first substrate31and the second substrate32are disposed facing each other with a predetermined gap formed by a sealing portion86interposed therebetween. The liquid crystal layer6is provided in the space surrounded by the first substrate31, the second substrate32, and the sealing portion86. The liquid crystal layer6modulates light passing therethrough depending on the state of an electric field. The liquid crystal layer6, for example, includes liquid crystals in a lateral electric-field mode, such as the in-plane switching (IPS) mode including the fringe field switching (FFS) mode. Orientation films may be provided between the liquid crystal layer6and the pixel substrate2and between the liquid crystal layer6and the counter substrate3illustrated inFIG. 57.

An illuminator is provided under the first substrate31. The illuminator includes a light source, such as a light emitting diode (LED), and outputs light from the light source toward the first substrate31. The light output from the illuminator passes through the pixel substrate2. The display apparatus100A switches the portions that block and prevent the light from being output and the portions that allow the light to be output depending on the state of liquid crystals at the corresponding positions, thereby displaying an image on the display surface. If the display apparatus100A is a reflective liquid crystal display apparatus including reflective electrodes that reflect light entering from the second substrate32side as the pixel electrodes39and including translucent second electrodes RxA in the counter substrate3, the illuminator is not necessarily provided under the first substrate31. The reflective liquid crystal display apparatus may include a front light on the second substrate32. In this case, light entering from the second substrate32side is reflected by the reflective electrodes (pixel electrodes39), passes through the second substrate32, and reaches the eyes of an observer. If the display panel30(refer toFIG. 57) is an OLED, the display panel30includes self-luminous bodies for respective pixels. In this case, the display panel30displays an image by controlling the lighting quantities of the respective self-luminous bodies. Consequently, the display apparatus100A requires no illuminator. If the display panel30is an OLED, the display layer may be included in the pixel substrate2. A luminous layer serving as the display layer, for example, may be disposed between the first electrodes TxA and the pixel electrodes39.

As illustrated inFIG. 58, the display apparatus100A includes the first electrodes TxA and the second electrodes RxA in the region overlapping the display region AA. The first electrodes TxA extend in a direction (second direction Dy) along one side of the display region AA and are arrayed in a direction (first direction Dx) along the other side of the display region AA with a space interposed therebetween. The first electrodes TxA are coupled to a first electrode selection circuit15C. The first electrodes TxA are made of a translucent conductive material, such as ITO.

The second electrodes RxA extend in the first direction Dx and are arrayed in the second direction Dy with a space interposed therebetween. In other words, the first electrodes TxA and the second electrodes RxA intersect in planar view, and capacitance is formed at the overlapping portions. The second electrodes RxA are coupled to a detection electrode selection circuit16B. The second electrodes RxA are made of a metal material, for example. The second electrodes RxA may be made of a translucent conductive material, such as ITO.

The first substrate31is further provided with a gate driver120and a source driver121. The gate driver120has a function of sequentially selecting one horizontal line to be a target of display drive in the display panel30. The source driver121is a circuit that supplies pixel signals to the respective pixels in the display panel30.

In a display operation, the gate driver120sequentially selects one horizontal line out of the pixels as a target of display drive. The display apparatus100A causes the source driver121to supply the pixel signals to the pixels belonging to one horizontal line, thereby performing display in units of one horizontal line. The driver IC19applies display drive signals to all the first electrodes TxA. In other words, the first electrodes TxA serve as common electrodes that supply a common potential to a plurality of pixels.

In a detection operation, the first electrode selection circuit15C supplies the second drive signals Vtx2having the phases determined based on a predetermined code to the first electrodes TxA. The detection apparatus1C thus performs CDM drive. The first electrode selection circuit15C supplies the first drive signals Vtx1to the respective first electrode blocks BK. The first electrode selection circuit15C has the same configuration as that according to any one of the first to the third embodiments.

The second electrodes RxA output the signals corresponding to changes in capacitance between the first electrodes TxA and the second electrodes RxA. The detection electrode selection circuit16B selects the second electrodes RxA based on a predetermined code. The detection apparatus1C thus performs touch detection or fingerprint detection.

The display apparatus100A may perform the display operation and the detection operation in a time-division manner. The display apparatus100A may perform the display operation and the detection operation in any division manner. The display apparatus100A, for example, performs the touch detection operation and the display operation by dividing them into a plurality of sections in one frame period of the display panel30, that is, in a time required to display video information of one screen.

While exemplary embodiments according to the present disclosure have been described, the embodiments are not intended to limit the disclosure. The contents disclosed in the embodiments are given by way of example only, and various changes may be made without departing from the spirit of the disclosure. Appropriate modifications made without departing from the spirit of the present disclosure naturally fall within the technical scope of the disclosure.