Thin film transistor array substrate

A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

BACKGROUND OF INVENTION

1. Field of Invention

The present invention relates to a thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD). More particularly, the present invention relates to controlling the capacitance of a TFT-LCD storage capacitor.

2. Description of the Related Art

Liquid crystal display (LCD) has many advantages over other conventional types of displays including high display quality, small volume occupation, lightweight, low voltage driven and low power consumption. Hence, LCDs are widely used in small portable televisions, mobile telephones, video recording units, notebook computers, desktop monitors, projector televisions and so on. Therefore, LCD has gradually replaced the conventional cathode ray tube (CRT) as a mainstream display unit.

The gate dielectric layer of the thin film transistor in the TFT-LCD is generally a silicon nitride layer. When a source/drain stacked layer in a bottom gate structure or a gate in a top gate structure is formed on the gate dielectric layer, a short period of over-etching is performed to make sure that no residues are left on the gate dielectric layer. Since the area of the transparent substrate is very large, the thickness uniformity of the gate dielectric layer after over-etching on the entire transparent substrate is not good. Thus, the thickness uniformity of the storage capacitor dielectric layer in each pixel is also affected.

The storage electricity of the storage capacitor is used to compensate for the leakage current of the pixel electrode, and the pixel electrode voltage can therefore be maintained at a stable level to stabilize the arrangement of liquid crystal molecules to stabilize the display of LCD. If the capacitances of the capacitors on the transparent substrate are varied, the charging or discharging rates are also varied. Therefore, the TFT dimensions cannot be designed according to the ideal condition that each storage capacitor has the same capacitance. To insure that a storage capacitor with less sufficient capacitance can normally charge and discharge in a regular time period, the TFT dimensions have to be designed large enough to enable the poorest storage capacitor to function normally. Therefore, the stability of the TFT-LCD display can be maintained. However, the aperture ratio of each pixel in TFT-LCD is decreased.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

One aspect of the invention provides a method of controlling the capacitance of the TFT-LCD storage capacitor to control the uniformity of the storage capacitor's dielectric layer.

Another aspect of the invention provides a method of controlling the capacitance of the TFT-LCD storage capacitor to improve the uniformity of the storage capacitor's capacitance.

Another aspect of the invention provides a method of controlling the capacitance of the TFT-LCD storage capacitor to reduce TFTs' dimensions.

Still another aspect of the invention provides a method of controlling the capacitance of the TFT-LCD storage capacitor to elevate the aperture ratio of the liquid crystal display.

In one embodiment, a method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The method comprises the following steps. A first conductive layer is formed on a transparent substrate and then is patterned to form a gate and a bottom electrode. A first silicon nitride layer, a dielectric layer, a second silicon nitride layer, an undoped amorphous silicon layer, and a doped amorphous silicon layer are sequentially formed on the transparent substrate, and an etching selectivity ratio of amorphous silicon over a material of the dielectric layer is not less than about 5.0. The doped amorphous silicon layer, the undoped amorphous silicon layer, and the second silicon nitride layer are patterned to form a stacked layer on the dielectric layer over the gate. A second conductive layer is formed on the transparent substrate. Then, the second conductive layer and the doped amorphous silicon layer are patterned to form a source and a drain on either side of the gate. Next, a passivation layer is formed over the transparent substrate and then is patterned to form a contact window to expose the source or the drain. A transparent conductive layer is formed on the passivation layer and in the contact window. The transparent conductive layer then is patterned to form a pixel electrode to connect the exposed source or the drain through the contact window electrically, and a storage capacitor is formed by the overlap between the pixel electrode and the bottom electrode.

In another embodiment, a method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The method comprises the following steps. A first conductive layer is formed on a transparent substrate and then is patterned to form a gate and a bottom electrode on the transparent substrate. A first silicon nitride layer, a dielectric layer, a second silicon nitride layer, an undoped amorphous silicon layer, and an etching stop layer are sequentially formed on the transparent substrate, and an etching selectivity ratio of amorphous silicon over a material of the dielectric layer is not less than about 5.0. The etching stop layer is patterned to form an etching mask on the undoped amorphous silicon layer over the gate. A doped amorphous silicon layer and a second conductive layer are sequentially formed over the transparent substrate. Then, the second conductive layer, the doped amorphous silicon layer, the undoped amorphous silicon layer, and the second silicon nitride layer are sequentially patterned to form a source and a drain on either side of the gate, and the undoped amorphous silicon layer serves as a channel between the source and the drain. A passivation layer is formed over the transparent substrate and then is patterned to form a contact window therein to expose the source or the drain. A transparent conductive layer is formed on the passivation layer and in the contact window. Then, the transparent conductive layer is patterned to form a pixel electrode to connect the exposed source or drain electrically through the contact window, and a storage capacitor is formed by the overlap between the pixel electrode and the bottom electrode.

In still another embodiment, a method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The method comprises the following steps. An undoped amorphous silicon layer is formed on a transparent substrate and then is patterned to form a silicon island of the TFT and a bottom electrode of the storage capacitor on the transparent substrate. A first silicon nitride layer, a dielectric layer, a second silicon nitride layer, and a first conductive layer are sequentially formed on the transparent substrate, and an etching selectivity ratio of amorphous silicon over a material of the dielectric layer is not less than about 5.0. Then, the first conductive layer and the second silicon nitride layer are patterned to form a stacked layer on the central part of the silicon island, and the first conductive layer of the stacked layer serves as a gate of a thin film transistor. The gate is used as a mask to implant ions into the silicon island under both sides of the gate to form a source and a drain of the thin film transistor and implant ions into the bottom electrode. A passivation layer is formed over the transparent substrate. The passivation layer, the dielectric layer and the first silicon nitride layer then are patterned to form a first contact window to expose the source and a second contact window to expose the drain. A second conductive layer is formed over the transparent substrate and then is patterned to form a data line connecting the source through the first contact window. A transparent conductive layer is formed over the transparent substrate. The transparent conductive layer is patterned to form a pixel electrode connecting the drain through the second contact window, and a storage capacitor is formed by the overlap between the pixel electrode and the bottom electrode.

In various embodiments, the dielectric layer is, for example, a silicon oxide layer, a tantalum oxide layer, an aluminum oxide layer or a barium titanate layer.

Various inventive embodiments allow the dielectric layer to be an etch stop layer when the stacked layer is formed, and the remaining dielectric layer and the first silicon nitride layer thus have a uniform thickness. Therefore, the storage capacitor, which comprises overlapping parts of the bottom electrode, the first silicon nitride layer, the dielectric layer, the passivation layer and the pixel electrode, has a uniform dielectric layer, which comprises the first silicon nitride layer, the dielectric layer, and the passivation layer. As a result, the capacitance of the storage capacitor is also uniform to allow a smaller dimension of the thin film transistor. Hence, the aperture ratio of each pixel is increased to improve the display quality.

DESCRIPTION OF CERTAIN EMBODIMENTS

As described above, this invention provides a method of controlling the capacitance of the TFT-LCD storage capacitor. This method controls the thickness uniformity of the storage capacitor's dielectric layer and thereby the effects of increasing uniformity of the storage capacitor's capacitance, reducing the dimensions of TFT, and increasing the aperture ratio of the LCD are reached.

FIGS. 1A–1Dare schematic, cross-sectional views showing a process for controlling the capacitance of the TFT-LCD storage capacitor according to a first preferred embodiment of this invention. InFIG. 1A, a first conductive layer is formed on a transparent substrate100and then is patterned to form a gate105and a bottom electrode110respectively on the transparent substrate100. Then, a first silicon nitride layer115, a dielectric layer120, a second silicon nitride layer125, an undoped amorphous silicon layer130, and a doped amorphous silicon layer135are sequentially formed on the transparent substrate.

The material of the first conductive layer is, for example, copper, aluminum, chromium or alloy of molybdenum and tungsten, and the first conductive layer can be formed by a physical vapor deposition process such as sputtering. The first silicon nitride layer115and the second silicon nitride layer125can be formed by chemical vapor deposition; the preferable thicknesses of the first silicon nitride layer115and the second silicon nitride layer125are respectively about 1500–3500 Å and about 200–800 Å, and their more preferable thicknesses are respectively about 2000–3000 Å and about 400–600 Å. An etching selectivity ratio of amorphous silicon over the material of the dielectric layer120is not less than about 5.0. The material of the dielectric layer120is, for example, silicon oxide or dielectric material, such as tantalum oxide, aluminum oxide or barium titanate, having a dielectric constant larger than about 4.0. The dielectric layer120is formed by chemical vapor deposition; its preferable thickness is about 100–600 Å, and its more preferable thickness is about 200–400 Å.

InFIG. 1B, the doped amorphous silicon layer135, the undoped amorphous silicon layer130, and the second silicon nitride layer125are patterned to form a stacked layer on the dielectric layer120over the gate105. The stacked layer comprises the doped amorphous silicon layer135a, the undoped amorphous silicon layer130a, and the second silicon nitride layer125a. The patterning method is, for example, lithography and etching.

InFIG. 1C, a second conductive layer is formed on the transparent substrate100. Then, the second conductive layer is patterned to form source/drains140over both sides of the gate105. Then, the doped amorphous silicon layer135aexposed by opening145is etched to form lightly doped drains135b. The material of the second conductive layer is, for example, copper, aluminum, chromium or alloy of molybdenum and tungsten, and the second conductive layer is formed by a physical vapor deposition process such as sputtering.

InFIG. 1D, a passivation layer150is formed over the transparent substrate100and then is patterned to form a contact window155to expose the source/drain140on the right side. A transparent conductive layer is formed on the passivation layer150and in the contact window155. The transparent conductive layer then is patterned to form a pixel electrode160to connect the exposed source/drain140through the contact window155electrically. A storage capacitor of the thin film transistor is formed by the overlap between the pixel electrode160and the bottom electrode110, and hence the storage capacitor's dielectric layer includes the passivation layer150, the dielectric layer120, and the first silicon nitride layer115between the pixel electrode160and the bottom electrode110. The material of the above-mentioned transparent conductive layer is, for example, indium tin oxide or indium zinc oxide, and the transparent conductive layer is formed by, for example, a physical vapor deposition process such as reactive sputtering.

FIGS. 2A–2Care schematic, cross-sectional views showing a process for controlling the capacitance of the TFT-LCD storage capacitor according to a second Is preferred embodiment of this invention. InFIG. 2A, a first conductive layer is formed on a transparent substrate200and then is patterned to form a gate205and a bottom electrode210on the transparent substrate200. A first silicon nitride layer215, a dielectric layer220, a second silicon nitride layer225, an undoped amorphous silicon layer230, and an etching stop layer235are sequentially formed on the transparent substrate200.

The material of the first conductive layer is, for example, copper, aluminum, chromium or alloy of molybdenum and tungsten, and the first conductive layer is formed by a physical vapor deposition process such as sputtering. The first silicon nitride layer215and the second silicon nitride layer225is formed by chemical vapor deposition; the preferable thicknesses of the first silicon nitride layer215and the second silicon nitride layer225are respectively about 1500–3500 Å and about 200–800 Å, and their more preferable thicknesses are respectively about 2000–3000 Å and about 400–600 Å. An etching selectivity ratio of amorphous silicon over the material of the dielectric layer220is not less than 5.0. The material of the dielectric layer220is, for example, silicon oxide or dielectric material, such as tantalum oxide, aluminum oxide or barium titanate, having a dielectric constant larger than about 4.0. The dielectric layer220is formed by chemical vapor deposition; its preferable thickness is about 100–600 Å, and its more preferable thickness is about 200–400 Å. The etching stop layer235is formed by chemical vapor deposition, and it is, for example, a silicon nitride layer or a silicon oxide/silicon nitride composite layer. The preferable thickness of the etching stop layer235is about 200–400 Å.

InFIG. 2B, the etching stop layer235is patterned to form an etching mask235aon the undoped amorphous silicon layer230over the gate205. Then, a doped amorphous silicon layer240and a second conductive layer245are sequentially formed over the transparent substrate200. The material of the second conductive layer245is, for example, copper, aluminum, chromium or alloy of molybdenum and tungsten, and the second conductive layer is formed by a physical vapor deposition process such as sputtering.

InFIG. 2C, the second conductive layer245, the doped amorphous silicon layer240, the undoped amorphous silicon layer230, and the second silicon nitride layer225are sequentially patterned to form a stacked layer and an opening250in the stacked layer. The stacked layer comprises a second silicon nitride layer225a, a channel230a, two lightly doped drain240a, and two source/drains245a. Since the etching mask235aprotects the undoped amorphous silicon layer230a, the etching to form opening250can stop on the etching mask235ato avoid damaging the undoped amorphous silicon layer230a. The patterning method mentioned above is, for example, lithography and etching. The following processes are similar to those of Embodiment 1 and hence are omitted here.

FIGS. 3A–3Care schematic, cross-sectional views showing a process of controlling the capacitance of the TFT-LCD storage capacitor according to a third preferred embodiment of this invention. InFIG. 3A, an undoped amorphous silicon layer is formed on a transparent substrate300and then is patterned to form a silicon island305and a bottom electrode310on the transparent substrate300. A first silicon nitride layer315, a dielectric layer320, a second silicon nitride layer325, and a first conductive layer330are sequentially formed on the transparent substrate300.

The first silicon nitride layer315and the second silicon nitride layer325is formed by chemical vapor deposition; the preferable thicknesses of the first silicon nitride layer315and the second silicon nitride layer325are respectively about 1500–3500 Å and about 200–800 Å, and their more preferable thicknesses are respectively about 2000–3000 Å and about 400–600 Å. An etching selectivity ratio of the material of amorphous silicon over the dielectric layer320is not less than about 5.0. The material of the dielectric layer320is, for example, silicon oxide or a dielectric material, such as tantalum oxide, aluminum oxide or barium titanate, having a dielectric constant larger than about 4.0. The dielectric layer320is formed by chemical vapor deposition; its preferable thickness is about 100–600 Å, and its more preferable thickness is about 200–400 Å. The material of the first conductive layer is, for example, copper, aluminum, chromium or alloy of molybdenum and tungsten, and the first conductive layer is formed by a physical vapor deposition process such as sputtering.

InFIG. 3B, the first conductive layer330and the second silicon nitride layer325are patterned to form a stacked layer comprising a second silicon nitride layer325aand a gate330aon the central part of the silicon island305. Then, the gate330ais used as a mask to implant ions into the silicon island305under both sides of the gate330aand the bottom electrode310to form two source/drains305a, channel305bof the thin film transistor and the bottom electrode310a.

InFIG. 3C, a passivation layer335is formed over the transparent substrate300, and the passivation layer335, the dielectric layer320and the first silicon nitride layer315then are patterned to form contact windows340and350to expose both of the source/drains305a. Next, a second conductive layer is formed over the transparent substrate and is patterned to form a data line355connecting the source/drain305aon the left side through the contact window350. A transparent conductive layer is formed over the transparent substrate300. The transparent conductive layer is patterned to form a pixel electrode345connecting the source/drain305aon the right side through the contact window340. A storage capacitor of the thin film transistor is formed by the overlap between the pixel electrode345and the bottom electrode310a, and hence the storage capacitor's dielectric layer includes the passivation layer335, the dielectric layer320, and the first silicon nitride layer315between the pixel electrode345and the bottom electrode310a. The material of the above-mentioned transparent conductive layer is, for example, indium tin oxide or indium zinc oxide, and the transparent conductive layer is, for example, a physical vapor deposition process such as reactive sputtering.

From the preferred embodiments mentioned above, it is evident that the gate dielectric layer of the thin film transistor is replaced by the composite gate dielectric layer comprising the first silicon nitride layer, the dielectric layer and the second silicon nitride layer in this invention. Therefore, when the undoped amorphous silicon layer/doped amorphous silicon layer in the bottom gate design are etched to form the stacked layer or the conductive layer in the top gate design is etched to form the gate, the dielectric layer is used as an etching stop layer. Therefore, the thickness of the remaining gate dielectric layer over the entire transparent substrate is quite uniform after over-etching, and storage capacitors with uniform capacitance on the entire transparent substrate is obtained after the subsequent steps of depositing the passivation layer and forming the pixel electrodes.

The etching selectivity of an amorphous silicon layer over a silicon nitride layer is about 3.0–5.0, and the etching selectivity of an amorphous silicon layer over a silicon oxide layer is about 5.0–10.0. If the gate dielectric layer being a silicon nitride layer compares with the gate dielectric layer comprising a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in a bottom gate designed thin film transistor, the result after over-etching is as follows. In the case where the gate dielectric layer is a silicon nitride layer, the thickness uniformity is about 5% over entire transparent substrate after depositing the silicon nitride layer by chemical vapor deposition; the thickness uniformity is reduced to about 20% after over-etching. However, in the case where the gate dielectric layer comprising a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer, the thickness uniformity is about 5% over the entire transparent substrate after depositing the first silicon nitride layer, the silicon oxide layer and the second silicon nitride layer by chemical vapor deposition; the thickness uniformity is still maintained at about 5% after over-etching. In addition, the thickness uniformity is also about 5% after depositing the passivation layer, and the storage capacitor's capacitance is maintained at a quite good uniformity over the entire transparent substrate.

Furthermore, if a dielectric layer with a dielectric constant larger than 4.0 is used, the storage capacitor's capacitance is increased. Therefore, the dimensions of the thin film transistor is further reduced to increase the aperture ratio of the liquid crystal display to improve the display quality.