Impermeable encapsulation system for integrated circuits

An impermeable encapsulation system for integrated circuit chips utilizes a polyimide-siloxane block copolymer as an undercoat applied to the chip surface and an impermeable outer coat comprised either of a non-reactive metal, such as titanium, tantalum or aluminum, or an amorphous semiconductor material comprising silicon-boron. All of these materials may be effectively applied at temperatures sufficiently low to avoid damaging the chip.

The present invention relates to semiconductor packaging and more 
particularly to the protection of integrated circuit semiconductor devices 
from hostile environments. 
BACKGROUND OF THE INVENTION 
Considerable research is ongoing to identify packaging materials and 
encapsulation techniques for protecting integrated circuitry in an endless 
variety of applications ranging from outer space to implantations in the 
human body. Each unique application exposes the integrated circuitry to a 
different environment, which in most cases includes elements that are 
potentially harmful to integrated circuit chips. Many applications expose 
the integrated circuitry to trace chemicals which, in time, can permeate 
the chips to prejudice performance and operating life. Even the diffusion 
of ions into the chip semiconductor body has deleterious consequences. For 
example, when applied to implanted prostheses, integrated circuitry is 
exposed to extracellular fluid which approximates a 0.15 normal NaCl 
solution at 37.degree. C. and is quite hostile to semiconductor chip 
structures. 
In my U.S. Pat. No. 4,198,444, issued Apr. 15, 1980 and assigned to the 
instant assignee, the disclosure of which is specifically incorporated 
herein by reference, there is provided an encapsulation process for 
surface passivating and hermetically sealing large thyristors and other 
high voltage power semiconductor devices. As disclosed therein, a 
polyimide-siloxane block copolymer is applied to selected surface areas of 
the semiconductor device and cured to provide a tenaciously adherent 
passivation layer exhibiting good abrasion resistance and excellent 
dielectric properties. A layer of borosilicate or phosphosilicate glass is 
then applied by chemical vapor deposition over the copolymer layer as a 
primary hermetically sealing outer coating. To provide enhanced resistance 
to chemical attack and to further reduce moisture permeability, a 
secondary outer glass layer of silox or silicon dioxide is deposited as a 
top coat over the primary glass layer. 
While this multiple layer encapsulation approach of my above-cited U.S. 
Pat. No. 4,198,444 is sufficiently protective for most power semiconductor 
device applications, I have found that the afforded degree of 
impermeability is insufficient for extended operating life of integrated 
circuitry exposed to certain particularly hostile environments, such as, 
for example, in the case of human implanted prostheses. 
OBJECTS OF THE INVENTION 
It is accordingly an object of the present invention to provide enhanced 
environmental protection for integrated circuitry. 
A further object is to provide enhanced environmental protection for 
integrated circuit components by encapsulating the components with 
strongly adherent materials impermeable to hostile environmental elements. 
An additional object is to provide a dual layer encapsulation system for 
integrated circuit semiconductor devices. 
A still further object is to provide a method for processing semiconductor 
devices encapsulated in accordance with the present invention. 
Other objects of the invention will in part be obvious and in part appear 
hereinafter. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, an integrated circuit chip is 
undercoated with a layer of tenaciously adherent, dielectric material 
comprised of a polyimide-siloxane block copolymer and overcoated with a 
moisture and ion diffusion impervious layer selected from the group 
consisting of a non-reactive, anodizable metal, such as titanium, 
tantalum, and aluminum, and silicon-boron, an amorphous semiconductor 
material. The resulting two layer encapsulation system protects the IC 
chip while exposed to a wide variety of hostile environments. 
The invention accordingly comprises the features of construction, 
combination of elements, and arrangement of parts, and the method steps 
for achieving same, all of which will be exemplified in the construction 
and method hereinafter set forth, and the scope of the invention will be 
indicated in the claims.

Like reference numerals refer to corresponding parts throughout the several 
views of the drawing. 
DETAILED DESCRIPTION 
With reference to FIG. 1, there is shown an integrated circuit chip, 
generally indicated at 10, including a body 12 of suitable semiconductor 
material, such as silicon. Formed in this semiconductor body are plural 
active regions 14, 16 and 18 which are exposed at the upper surface 12a of 
the body. A thin insulative layer 20 of silicon dioxide or silicon nitride 
is formed over the body upper surface in conventional fashion. Windows 20a 
are opened in layer 20 to permit the deposition of metallization contact 
pads 22, typically of aluminum, in ohmic contact with active regions 16 
and 18. 
A layer 24 of a suitable polyimide-siloxane block copolymer, such as 
disclosed in my above-noted U.S. Pat. No, 4,198,444, as well as in Berger 
U.S. Pat. No. 4,051,163, issued Sept. 27, 1977 and Holub U.S. Pat. No. 
3,325,450, issued June 13, 1967, all of which are assigned to the instant 
assignee, is applied to the exposed surfaces of the chip 10, including the 
insulative layer 20 and the contact pads 22. This material is dissolved in 
a suitable solvent, such as, for example, N-methylpyrrolidone, 
N,N-dimethylformamide or N,N-dimethylacetamide, and applied as a polymer 
precursor by conventional means such as dipping, spraying, spinning, 
brushing, etc. The block copolymers are then dried in an initial heating 
step at temperatures of about 75.degree. to 125.degree. C. for sufficient 
time to drive off the solvent, followed by heating at temperatures of 
about 150.degree.-300.degree. C. to effect the desired conversion to the 
polyimide-siloxane block structure and then a final cure. 
A preferred curing cycle is as follows: 
(a) for 15 to 30 minutes at from 135.degree. C. to 150.degree. C. in dry 
nitrogen, 
(b) for 15 to 60 minutes at from 175.degree. to 190.degree. C. in dry 
nitrogen, and 
(c) for 1 to 3 hours at about 225.degree. in a vacuum. 
Sufficient material is applied to the integrated chip surface to provide 
layer 24 having a thickness of from 5 microns to 2 mils, with 5 to 10 
microns being a preferred range. The resulting layer is a tough, durable, 
highly insulative undercoat which, largely by virtue of its siloxane 
content, tenaciously adheres to the chip surface. 
While the polyimide-siloxane material of my above-noted U.S. Pat. No. 
4,198,444 is preferred for layer 24, alternative polyimide-siloxane block 
copolymer structures based on 4--4'bisphenol "A"-dianhydride and 
compounded with sufficient siloxane to achieve the requisite adhesion 
could be employed. 
To complete the impermeable encapsulation system of the present invention, 
the polyimide-siloxane block copolymer layer 24 is topcoated with a highly 
impervious, layer 26 of a suitable non-reactive material, such as 
tantalum, titanium, aluminum or a silicon-boron composition. All of these 
materials can be applied at sufficiently low temperatures, i.e., less than 
400.degree. C., so as not to harm chip 10, particularly its aluminum 
contact pads 22 and layer 24, or jeopardize adhesion of layer 24 to the 
chip surface. Moreover, a top coat of any of these materials is 
significantly less permeable to moisture and ion diffusion than the glass 
outer layers of my above-cited U.S. Pat. No. 4,198,444 when applied under 
the same temperature constraints. Tantalum, titanium and aluminum may be 
applied using conventional low temperature sputter coating or vacuum 
deposition techniques, while an amorphous semiconductor material comprised 
of silicon-boron may be applied using well-known chemical vapor deposition 
procedures. For example, a silicon-boron outer layer 26 may be deposited 
out onto layer 24 by flowing a mixture of diborane and silane gases in a 
nitrogen carrier through a hot wall quartz tube furnace. For example, in a 
nitrogen gas flowing at the rate of 50 standard liters per minute, silane 
gas is introduced at a rate of 200 standard cubic centimeters per minute 
in mixture with diborane gas of a concentration 0.6% that of the silane 
gas to deposit a silicon-boron outer layer 26 of 6000 Angstroms thickness 
in 20 minutes at a deposition temperature of 320.degree. C. Thicknesses of 
outer layer 26 may range from 5000 Angstroms to 2 microns; however, a 
thickness of less than 1 micron is preferred in order to avoid excessive 
stresses and cracking due to the expansion mismatch with the layer 24 
material. 
Having fully encapsulated integrated circuit chip 10, it then becomes 
necessary to provide access to the contact pads 24 for the connection 
thereto of external lead wires or metallization conductor runs (not 
shown). To this end, a layer 28 of positive photoresist is coated over 
outer layer 26 and is photolithographically patterned using a mask 30, as 
seen in FIG. 1. The photoresist layer is then selectively etched away in 
the patterned areas to create windows 28a therein in overlying registry 
with contact pads 22 (FIG. 2). Then, using the photoresist layer as a 
mask, the outer encapsulation layer 26 is etched away through windows 28a 
to create corresponding windows 26a therein (FIG. 3). In the case of a 
tantalum outer layer, these windows may be created using etchant solutions 
containing hydrofluoric acid or strong caustics, or by using a reactive 
ion etching process employing carbon tetrafluoride (CF.sub.4) or 
alternatively by using oxygen mixed with polychlorinated organic materials 
such as carbon tetrachloride (CCl.sub.4) or ethylene trichloride (C.sub.2 
HCl.sub.3). An outer layer of titanium or aluminum may be etched in the 
same manner by using higher concentrations of polychlorinated compounds in 
oxygen. In the case of a silicon-boron outer layer, windows 26a may be 
formed in a plasma reactor using a carbon tetrafluoride-oxygen mixture. 
Finally, windows 24a (FIG. 4) are created in the polyimide-siloxane 
primary or inner encapsulation layer 24 again using an oxygen plasma 
reactor with a more oxygen rich gas mixture. The photoresist layer 28 is 
removed in conventional manner, leaving the contact pads 22 exposed in 
windows 24a in layer 24 and windows 26a in overlying layer 26. It will be 
noted from FIG. 4 that these windows expose only the central portions of 
the contact pads, and thus there is a considerable bond interface between 
the contact material and the primary layer material to discourage moisture 
and ion penetration to the chip body 12. Moreover, since the thickness of 
primary layer 24 is preferably less than 1 micron, there is, in relation 
to the overall chip surface area, miniscule surface area of primary layer 
material exposed in windows 24a to such potentially harmful environmental 
elements. If desired, after the electrical connections to the contact pads 
22 have been made, these contact areas may be varnish coated for enhanced 
protection. However, it will be appreciated that the aluminum contact pads 
are inherently impermeable. In the case where the outer layer 26 is 
metallic, i.e., either tantalum, titanium or aluminum, it is preferred 
that it be anodized to create a protective, insulative oxide coating on 
its outer surface. Moreover, although a metallic outer layer limits the 
voltage rating of the IC chip, it affords the added benefit of 
electrostatic shielding. 
From the foregoing description it is seen that the objects set forth above, 
including those made apparent therein, are efficiently attained, and since 
certain changes may be made in the disclosed embodiment without departing 
from the scope of the invention, it is intended that all matters contained 
in the above description and shown in the accompanying drawing shall be 
interpreted as illustrative and not in a limiting sense.