Bonded structures

A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

BACKGROUND

Field of the Invention

The field generally relates to bonded structures, and in particular, to bonded structures that provide improved sealing between two elements (e.g., two semiconductor elements).

Description of the Related Art

In semiconductor device fabrication and packaging, some integrated devices are sealed from the outside environs in order to, e.g., reduce contamination, maintain vacuum or certain pressure or prevent damage to the integrated device. For example, some microelectromechanical systems (MEMS) devices include a cavity defined by a cap attached to a substrate with an adhesive such as solder. However, some adhesives may be permeable to gases, such that the gases can, over time, pass through the adhesive and into the cavity. Moisture or some gases, such as hydrogen or oxygen gas, can damage sensitive integrated devices. Other adhesives, such as solder, create their own long term reliability issues. Accordingly, there remains a continued need for improved seals for integrated devices.

DETAILED DESCRIPTION

Various embodiments disclosed herein relate to semiconductor elements with a conductive interface feature and a nonconductive feature. Various embodiments disclosed herein relate to interface structures that connect two elements (which may comprise semiconductor elements) in a manner that effectively seals integrated devices of the semiconductor elements from the outside environs. For example, in some embodiments, a semiconductor element can comprise a conductive interface feature (e.g., a copper, or Cu, layer) and a nonconductive interface feature (e.g., a silicon oxide layer). For example, in some embodiments, a bonded structure can comprise a plurality of semiconductor elements bonded to one another along an interface structure. An integrated device can be coupled to or formed with a semiconductor element. For example, in some embodiments, the bonded structure can comprise a microelectromechanical systems (MEMS) device in which a cap (a first semiconductor element) is bonded to a carrier (a second semiconductor element). A MEMS element (the integrated device) can be disposed in a cavity defined at least in part by the cap and the carrier.

In some embodiments, the conductive interface feature of the semiconductor element can comprise a recess, and a portion of the nonconductive interface feature can be disposed in the recess. In some embodiments, the recess in the conductive interface feature may prevent and/or mitigate hillock formation when the semiconductor element is annealed.

In some arrangements, the interface structure can comprise one or more conductive interface features disposed about the integrated device, and one or more non-conductive interface features to connect the first and second semiconductor elements and to define an effectively annular or effectively closed profile. In some embodiments, the interface structure can comprise a first conductive interface feature, a second conductive interface feature, and a solid state non-conductive interface feature disposed between the first and second conductive interface features. In some embodiments, each semiconductor element can comprise an associated conductive interface feature, and the conductive interface features can be directly bonded to one another to connect the two semiconductor elements.

FIG. 1Ais a schematic side sectional view of a bonded structure1, according to various embodiments.FIG. 2Ais a schematic sectional plan view of an interface structure10of the bonded structure1shown inFIGS. 1A-1B. The bonded structure1can include a first semiconductor element3bonded to a second semiconductor element2along the interface structure10. As explained herein, corresponding bonding layers11of the first and second semiconductor elements3,2can be directly bonded to one another without an intervening adhesive. As explained below, the interface structure10can include conductive interface features12embedded in a surrounding non-conductive interface feature14. As explained herein, the bonding layers11of each element3,2can include conductive and non-conductive interface features that can bond to define a seal. As shown inFIG. 1A, the interface features12,14can extend vertically into the semiconductor elements (e.g., into the bonding layers11), such that the interface features12,14can extend in a direction from one semiconductor element towards the other semiconductor element, e.g., vertically relative to the bonded structure. The first and second semiconductor elements can define a cavity5in which an integrated device4is at least partially disposed. In the illustrated embodiment, the first semiconductor element3can comprise a cap that is shaped to define the cavity, or that is disposed over a cavity in the second semiconductor element2. For example, the semiconductor element3can comprise a wall6disposed about the integrated device4and separating the cavity5from the outside environs. In other embodiments, integrated device4may be formed on or be a part of the bonding layer11of the second semiconductor element2, and resides inside the cavity5formed within the periphery of the walls6of the first semiconductor element3. In various embodiments, the wall6and cap can comprise a semiconductor material, such as silicon. In other embodiments, the wall6and cap can comprise a polymer, ceramic, glass, or other suitable material. The cavity5can comprise an air cavity, vacuum, or can be filled with a suitable filler material. Although the first and second elements2,3are described herein as semiconductor elements, in other embodiments, the first and second elements2,3can comprise any other suitable type of element, which may or may not comprise a semiconductor material. For example, the elements2,3can comprise various types of optical devices in some embodiments that may not comprise a semiconductor material.

The second semiconductor element2can comprise a carrier having an exterior surface9to which the first semiconductor element3is bonded. In some embodiments, the carrier can comprise a substrate, such as a semiconductor substrate (e.g., a silicon interposer with conductive interconnects), a printed circuit board (PCB), a ceramic substrate, a glass substrate, or any other suitable carrier. In such embodiments, the carrier can transfer signals between the integrated device4and a larger packaging structure or electronic system (not shown). In some embodiments, the carrier can comprise an integrated device die, such as a processor die configured to process signals transduced by the integrated device4. In the illustrated embodiment, the integrated device4comprises a MEMS element, such as a MEMS switch, an accelerometer, a gyroscope, etc. The integrated device4can be coupled to or formed with the first semiconductor element3or the second semiconductor element2.

In some configurations, it can be important to isolate or separate the integrated device die4from the outside environs, e.g., from exposure to gases and/or contaminants. For example, for some integrated devices, exposure to unwanted materials such as moisture or gases (such as hydrogen, oxygen gas, oxides of sulfur or nitrogen or various combinations thereof, etc.) can damage the integrated device4or other components. Accordingly, it can be important to provide an interface structure10that effectively or substantially seals (e.g., hermetically or near-hermetically seals) the cavity5and the integrated device4from unwanted materials. As shown inFIGS. 1A and 2A, the interface structure10can be arranged to prevent or substantially suppress unwanted materials from passing through the interface structure10from an outer surface8or outside environment of the structure1to an inner surface7of the structure1.

The disclosed embodiments can utilize materials that have low gas permeation rates and can arrange the materials so as to reduce or eliminate the entry of gases into the cavity5. In other embodiments, the cavity5can be filled with a different material, for example nitrogen, to maintain certain pressure for an optimum performance of the device4. In some embodiments, the permeation of this filler gas from inside the cavity to outside may be beneficial to be reduced or eliminated to maintain the pressure for the sustained performance of device4over the life of the product. For example, the permeation rate of some gases (such as hydrogen gas) through metals may be significantly less that the permeation rate of gases through other materials (such as dielectric materials or polymers). Hydrogen gas, for example, may dissociate into its component atoms at or near the outer surface8. The dissociated atoms may diffuse through the wall6or interface structure10and recombine at or near the inner surface7. The diffusion rate of hydrogen gas through metal can be approximately proportional to the square root of the pressure. Other gases, such as rare gases, may not permeate metals at all. By way of comparison, gases may pass through polymer or glass (silicon oxide) materials faster (e.g., proportional to the pressure) since the gas molecules may pass through without dissociating into atoms at the outer wall8.

Accordingly, the embodiments disclosed herein can beneficially employ metal that defines an effectively annular or closed pattern (seeFIGS. 2A-2E) about the integrated device4to seal an interior region of the bonded structure (e.g., the cavity5and/or integrated device4) from the outside environs and harmful gases. Beneficially, in some embodiments, the metal pattern can comprise a completely closed loop around the integrated device4, which may improve sealing relative to other arrangements. In some embodiments, the metal pattern can comprise an incompletely annular pattern, e.g., mostly or partially annular, about the device4, such that there may be one or more gaps in the metal. Since the permeation rate of gases through metals (such as copper) is significantly less than the permeation rate of gases through dielectric or non-conductive materials (such as silicon oxide, silicon nitride, etc.), the interface structure10can provide an improved seal for an interior region of the bonded structure1.

However, in some embodiments, it may be undesirable to utilize an interface structure10that includes only metal or a significant width of metal lines. When the interface structure10includes wide metal lines or patterns, the metal may experience significant dishing during chemical mechanical polishing (CMP) or other processing steps. Dishing of the metal lines can adversely affect ability to bond the metal lines of first semiconductor element3to the second semiconductor element2, particularly when employing direct metal-to-metal bonding techniques. Accordingly, in various embodiments, the interface structure10can include one or more conductive interface features12embedded with or otherwise adjacent to one or more non-conductive interface features14. The conductive interface features can provide an effective barrier so as to prevent or reduce the permeation of unwanted materials into the cavity5and/or to the integrated device4and/or to prevent or reduce the permeation of wanted gases filled in the cavity5to outside. Moreover, the conductive interface features can be made sufficiently thin and can be interspersed or embedded with the non-conductive interface features so as to reduce or eliminate the deleterious effects of dishing.

In some embodiments disclosed herein, the interface structure10can be defined by first interface features on the first semiconductor element and second interface features on the second semiconductor element. The first interface features (including conductive and non-conductive features) can be bonded to the corresponding second interface features to define the interface structure10. In some embodiments, the interface structure10can comprise a separate structure that is separately bonded to the first semiconductor element3and the second semiconductor element2. For example, in some embodiments, the wall6may be provided as a separate open frame with a generally planar semiconductor element3provided facing the frame. A second interface structure (not shown) can comprise an intervening structure that is directly bonded without an intervening adhesive between the open frame and semiconductor element3thereby forming a similar enclosed cavity5to that shown inFIG. 1A. The interface structure(s)10may provide mechanical and/or electrical connection between the first and second semiconductor elements3,2. In some embodiments, the interface structure10may provide only a mechanical connection between the elements3,2, which can act to seal the cavity5and/or the integrated device4from the outside environs. In other embodiments, the interface structure10may also provide an electrical connection between the elements3,2for, e.g., grounding and/or for the transmission of electrical signals. In other embodiments, the interface structure10may provide an optical connection between the elements3,2. As explained in more detail below in connection withFIGS. 3A-3C, the conductive interface features can be direct bonded to one another without an intervening adhesive and without application of external pressure or a voltage. For example, bonding surfaces (e.g., bonding layers11) of first and second interface features can be prepared. The bonding surfaces can be polished or planarized, activated, and terminated with a suitable species. For example, in various embodiments, one or both the bonding surfaces may comprise silicon based dielectric materials for example, silicon oxide. The bonding surfaces can be polished to a root-mean-square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The polished bonding surfaces can be activated by for example, a process comprising atmospheric or vacuum plasma method. In various embodiments, the bonding surfaces can be terminated with nitrogen, for example, by way of wet or dry etching (e.g., very slight etching (VSE)) using, for example, a nitrogen-containing solution or by using a plasma etch with nitrogen. As explained herein, the bonding surfaces can be brought into contact to form a direct bond at room temperature without application of external pressure. In some embodiments, the semiconductor elements3,2can be heated to a higher temperature to strengthen the bond, for example, a bond between the non-conductive features. The semiconductor elements3,2can be heated further to improve the bond strength between the opposing bonding surfaces of semiconductor3and2and to form reliable electrical and mechanical contact at interface10between the semiconductors3and2. Additional details of the direct bonding processes used in conjunction with each of the disclosed embodiments may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; 7,485,968; 8,735,219; 9,385,024; 9,391,143; 9,431,368; 9,953,941; and 10,032,068, and throughout U.S. Patent Application Publication No. 2017/0200711, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes. In some embodiments, the conductive interface features of both elements3,2and the non-conductive interface features of both elements3,2are simultaneously directly bonded to one another.

It should be appreciated that, although the illustrated embodiment is directed to a MEMS bonded structure, any suitable type of integrated device or structure can be used in conjunction with the disclosed embodiments. For example, in some embodiments, the first and second semiconductor elements can comprise integrated device dies, e.g., processor dies and/or memory dies. In addition, although the disclosed embodiment includes the cavity5, in other arrangements, there may not be a cavity. For example, the embodiments disclosed herein can be utilized with any suitable integrated device or integrated device die in which it may be desirable to seal active components from the outside environs, gases, liquids, plasma or unwanted materials. Moreover, the disclosed embodiments can be used to accomplish other objectives. For example, in some arrangements, the disclosed interface structure10can be used to provide an electromagnetic shield to reduce or prevent unwanted electromagnetic radiation from entering the structure1, and/or to prevent various types of signal leakage. Of course, the cavity may be filled with any suitable fluid, such as a liquid, gas, or other suitable substance which may improve the thermal, electrical or mechanical characteristics of the structure1.

FIGS. 1B-1Kare schematic, partial, sectional plan views of various embodiments of the interface structure10. It will be understood that the illustrated patterns can extend completely annularly or incompletely annularly (e.g., mostly annularly), around the protected region, such as the cavity5ofFIG. 1A, to define an effectively annular or effectively closed profile. As used herein, effectively annular structures may include round annular structures, as well as non-rounded annular structures that define an effectively closed profile (e.g., square or other polygon). As shown inFIGS. 1B-1K, the interface structure10can comprise one or a plurality of conductive interface features12and one or a plurality of non-conductive interface features14. As shown inFIG. 1A, the conductive and non-conductive features12,14can extend vertically through portions of the first and/or second semiconductor elements3,2, e.g., vertically through portions of the bonding layer11. For example, the conductive and non-conductive features12,14can extend vertically through the first and/or second semiconductor elements3,2(e.g., in a direction non-parallel or perpendicular to the major surface of the semiconductor elements3,2) by a vertical distance of at least 0.05 microns, at least 0.1 microns, at least 0.5 microns, or at least 1 micron. For example, the conductive and non-conductive features12,14can extend vertically through the first and/or second semiconductor elements3,2by a vertical distance in a range of 0.05 microns to 5 microns, in a range of 0.05 microns to 4 microns, in a range of 0.05 microns to 2 microns, or in a range of 0.1 microns to 5 microns. By extending the conductive and non-conductive features12,14through portions of the first and/or second semiconductor elements3,2, the conductive and non-conductive features12,14can provide a seal without gaps between the semiconductor elements3,2and the interface structure10. The conductive and non-conductive features12,14provided on semiconductor elements3,2may provide generally planar surfaces for bonding the two semiconductor elements.

The conductive interface feature12can comprise any suitable conductor, such as a metal. For example, the conductive interface feature12can comprise copper, aluminum, nickel, tungsten, titanium, tantalum or their various alloys or any other suitable metal that is sufficiently impermeable to fluids/gases, such as air, hydrogen, nitrogen, water, moisture, etc. The non-conductive interface feature14can comprise any suitable non-conductive material, such as a dielectric or semiconductor material. For example, the non-conducive interface feature14can comprise silicon oxide in some embodiments. In other embodiments, the non-conducive interface feature14can comprise silicon nitride, silicon carbide or silicon carbonitride. Although only one layer of non-conductive interface14is shown inFIG. 1A, it is understood that it may comprise one or more layers of non-conductive materials. For example, one or more layers of silicon oxide, silicon nitride, etc. Beneficially, the use of both a conductive interface feature12and a non-conductive interface feature14can provide improved sealing to prevent unwanted materials from passing from the outside environs into the cavity5and/or to the device4. As explained above, conductors such as metals may generally provide improved sealing for many gases. However, some non-conductive materials (e.g., dielectrics) may be less permeable to certain gases than conductors, metals, or semiconductors. Structurally mixing the conductive features12with the non-conductive features14may provide a robust seal to prevent many different types of unwanted materials such as gases, plasma, inorganic ions and fluids from entering the cavity and/or affecting the performance of the device4.

In the embodiment ofFIG. 1B, only one conductive interface feature12, which may be completely annular, is provided. The conductive interface feature12can be embedded in one or more non-conductive interface features14to define an effectively annular or effectively closed profile. For example, in some embodiments, the conductive interface feature12can be embedded in a bulk non-conductive material. In other applications the conductive interface feature12can be embedded in more than one layer (not shown). For example, a top portion of the conductive interface feature12may be embedded in the non-conductive interface feature14and a lower portion of the conductive interface feature12embedded in a different material. The different material below the non-conductive feature14may comprise a semiconductor material or other suitable materials. In other embodiments, layers of non-conductive material can be provided on one or opposing sides of the conductive interface feature12. As shown inFIG. 2A, the conductive interface feature12can extend around the cavity5and/or the integrated device4in a completely annular pattern. InFIG. 2A, for example, the conductive interface feature12extends in a complete annulus, or closed shape, about the cavity5and/or device4, such that the non-conductive material of the non-conductive feature14does not cross or intersect the conductive interface feature12. In other embodiments, however (for example, see description ofFIGS. 2D and 2Ebelow), there may be one or more gaps between portions of the conductive interface feature12, but without a direct path to the cavity5. Individual elements of the conductive interface feature12can be incompletely annular in some embodiments. For example, individual elements of the conductive interface feature12can be mostly annular, e.g., extend about the cavity5and/or the integrated device4by at least 90°, at least 180°, at least 270°, at least 350°, or at least 355° (e.g., 360°), while cooperating to define an effectively annular or closed interface structure10. Further, as explained above, the conductive interface feature12can extend vertically into and can be embedded in portions of the wall6and/or corresponding portions of the second semiconductor element2.

The structure ofFIG. 1A, including any of the example patterns ofFIGS. 1B-1K, can be formed, for example, by semiconductor fabrication techniques, such as by forming metal lines on a substrate by deposition, patterning and etching and depositing oxide thereover, or by damascene or dual damascene processing. Desirably, the metal lines to be bonded are formed flush with surrounding non-conductive material, or slightly (e.g., 0.5 nm to 20 nm) recessed or protruding from the non-conductive material. Annular or mostly annular patterns of metal lines can be formed on both semiconductor elements3,2using semiconductor processing, for directly bonding to one another and creating an effective metal seal against gas diffusion.

The interface structure10can have an interface width t0in a range of 1 micron to 1 mm. The conductive interface feature12can have a conductor width tcin a range of 0.1 microns to 50 microns. As explained above, the interface structure10disclosed inFIG. 1Bcan beneficially provide an effective seal against gases entering the cavity5and/or interacting with the device4or the gases exiting the cavity to outside. Moreover, the interface structure10disclosed herein can be thinner than other types of bonds or interfaces, which can advantageously reduce the overall package footprint.

Turning toFIG. 1C, the interface structure10can include a plurality of conductive interface features12and an intervening solid state (e.g., non-gaseous) non-conductive interface feature14disposed between adjacent conductive interface features12.FIG. 2Cis a schematic plan view of the interface structure10shown inFIG. 1C. As with the implementation ofFIG. 1B, the interface structure12can be disposed about the integrated device4and can comprise conductive features12arranged in an effectively annular or closed profile (e.g., a complete or incomplete annulus in various arrangements) to connect the first semiconductor element3and the second semiconductor element2. InFIGS. 1C and 2C, the conductive features12comprise at least one complete or absolute annulus. In other embodiments, the conductive features can be shaped differently, but can be arranged to define an effectively annular or closed profile. The use of multiple conductive features12can provide multiple layers of highly impermeable material so as to reduce the inflow of unwanted materials into the cavity5and/or outflow of gases or wanted materials from the cavity5to outside. Utilizing multiple thin conductive features12spaced by the non-conductive features14, compared to wider features, can reduce the effects of dishing due to polishing for a given degree of overall impermeability. Thus, in various embodiments, multiple conductive features12can be arranged around one another, for example concentrically, mostly or completely about the device4and/or the cavity5to provide an effective gas seal. In some embodiments, a width of one of the non-conductive features14disposed between the adjacent conductive features12can be less than 10 times the width tcof one of the multiple conductive features12, and preferably less than 5 times the width tcof the conductive feature. Also, a length of the multiple conductive features12and/or the non-conductive features14can be at least 10 times a width of the interface structure.

Moving toFIG. 1D, in some embodiments, the conductive interface features12can comprise a plurality of annular conductors12A disposed about the cavity5and/or device4in an effectively annular or closed pattern, and a plurality of crosswise conductors12B connecting adjacent annular conductors12A. Advantageously, the use of annular and crosswise conductors12A,12B can provide increased contact area for implementations that utilize direct bonding (explained below), can simplify CMP process by, for example, creating more uniform distribution of conductive features12and non-conductive features14, and can provide an improved gas seal due to the beneficial permeation properties of the conductive material. As with the embodiments ofFIGS. 1B-1C, inFIG. 1D, the conductive interface features12can delimit a closed loop such that the non-conductive features14do not intersect or cross the conductive features12.

FIGS. 1E-1Gillustrate conductive interface features12having a kinked, annular profile, in which a plurality of conductive segments112a-112care connected end-to-end and angled relative to adjacent segments. As with the embodiments ofFIGS. 1B-1D, the features12can be disposed about the cavity5and/or device4in an effectively annular or closed pattern, e.g., in a complete annulus. The kinked profiles illustrated inFIGS. 1E-1Gcan comprise a first segment112aand a second segment112cspaced apart from one another in a transverse direction. The first and second segments112a,112ccan be connected by an intervening transverse segment112b. The first and second segments112a,112ccan be oriented along a direction generally parallel to the at least partially annular pathway around the cavity5and/or integrated device4. The transverse segment112bcan be oriented transverse or non-parallel to the first and second segments112a,112c. In some embodiments, the non-conductive interface features14may not cross the conductive features12.

The kinked annular profile of the conductive interface features12can facilitate direct bonding with increased tolerance for misalignment in various implementations, as compared with features12that are straight or non-kinked, while maintaining the benefits of narrow lines with respect to the effects of dishing after polishing. For example, the zig-zag or kinked pattern may promote contact between misaligned contact structures on the two elements, in various embodiments. Moreover, the kinked profile may reduce the effects of dishing after chemical mechanical polishing (CMP), because the segments112aand112cmay be shorter along the length of the conductive features, as compared with conductive features that extend continuously around the interior of the bonded structure. The kinked profile can include any number of conductive interface features12. For example,FIG. 1Eillustrates a kinked profile with a single conductive interface feature12.FIG. 1Fillustrates a plurality of conductive interface features12spaced apart transversely by an intervening non-conductive interface feature14. As withFIG. 1D, inFIG. 1G, spaced apart annular conductors12A can be joined by crosswise conductors12B. Skilled artisans would appreciate that other patterns may be suitable.

FIGS. 1H-1Killustrate conductive interface features12having an irregular or zigzag annular profile, in which a plurality of conductive segments112a-112fare connected end-to-end and angled relative to adjacent segments by way of one or more bend regions11. As shown inFIGS. 1H-1K, the segments112a-112fmay be arranged in an irregular pattern, in which the segments112a-112fare angled at different orientations and/or have different lengths. In other arrangements, the segments112a-112fmay be arranged in a regular pattern at angles that are the same or periodic along the annular profile. In still other arrangements, the conductive features12can be curved or otherwise non-linear. These features may also increase tolerance for misalignment, relative to straight line segments, while still employing relatively narrow lines that are less susceptible to dishing and therefore earlier to employ in direct metal-to-metal bonding.

FIG. 2Bis a schematic sectional plan view of an interface structure10having one or more electrical interconnects extending through the interface structure10. As withFIG. 2A, the conductive feature(s)12can be disposed within the interface structure10about the cavity5and/or integrated device4to define an effectively annular or closed profile, e.g., a completely annular profile. The conductive feature(s)12can comprise elongate feature(s) with a length greater than a width (e.g., with a length of at least five times the width, or at least ten times the width). Unlike the interface structure10shown inFIG. 2A, however, the interface structure10ofFIG. 2Bincludes one or a plurality of electrical interconnects20extending vertically partially or fully through one or more non-conductive interface features14. The electrical interconnect20can be in electrical communication with the integrated device4and/or other components of the bonded structure1so as to transfer power or signals between the various components of the structure1. In some embodiments, the electrical interconnect20can extend from the first semiconductor element3to the second semiconductor element2. As shown inFIG. 2B, the electrical interconnect20can be spaced inwardly and electrically separated from the conductive interface feature12, which itself can also serve to electrically connect circuits in the first and second semiconductor elements3,2. In other embodiments, the electrical interconnect20can be spaced outwardly from the conductive interface feature12. In still other embodiments, as explained below, the electrical interconnect20can extend through intervening non-conductive interface features14disposed between a plurality of conductive interface features12.

The electrical interconnects20can provide electrical communication between the semiconductor elements3,2through the interface structure10. Providing the interconnects20in a direction non-parallel or transverse to the interface structure10can therefore enable the interface structure10to act as both a mechanical and electrical connection between the two semiconductor elements3,2. The interconnects20can comprise any suitable conductor, such as copper, gold, tungsten, titanium, tin, etc. The interconnects20can comprise conductive traces or through-silicon vias in various arrangements. Moreover, as noted above, the interface features12may also serve as annular or mostly annular electrical interconnects, with or without the conventional interconnects20.

FIG. 2Dis a schematic sectional plan view of an interface structure10having a plurality of conductive interface features12A,12B disposed about a cavity5to define an effectively annular or closed profile, with each conductive interface feature12A,12B comprising an incompletely annular feature, e.g., a mostly annular feature extending more than 180°. For example, as shown inFIG. 2D, each conductive interface feature12A,12B can comprise a U-shaped structure, with the feature12B disposed inwardly relative to the feature12A by a non-conductive gap39. Thus, inFIG. 2D, each conductive interface feature12A,12B may comprise a mostly annular profile, but with the gap39between the two interface features12A,12B such that any one of the interface features12A,12B does not necessarily define a closed loop. The structure10shown inFIG. 2Dmay still be effective at reducing the permeation of gases into cavity5and/or device4, since the pattern of conductive interface features12A,12B combine to create an effectively annular or effectively closed structure about the cavity5. Some gas may permeate through the gap39, but the gas would have a very long path through the non-conductive material before it could reach the cavity5and/or contact the device4, so as to overcome the higher diffusivity of gases in the non-conductive material14relative to the conductive material of the conductive interface features12A,12B. It should be appreciated that although two features12A,12B are shown herein, any suitable number of features12can be used. The conductive interface feature12A may be connected with the conductive interface feature12B by, for example, a gap bridging conductive interface feature12C. In some embodiments, multiple gap bridging conductive interface features12C may connect interface feature12A and interface feature12B to form an intertwining sealing structure at the bonding surface10. The gap bridging conductive interface features12C may be spaced with intervals. The intervals may be symmetrical or non-symmetrical over the bonding surface.

FIG. 2Eis a schematic sectional plan view of an interface structure10having a plurality of conductive interface features12disposed about a cavity5to define an effectively annular or closed profile, wherein the plurality of conductive features12comprises a plurality of segments spaced apart by non-conductive gaps39. The segments that define each conductive interface feature12shown inFIG. 2Ecomprise linear segments, but in other embodiments, the segments can be curved. InFIG. 2E, some or all conductive interface features12on their own may not define a mostly annular pattern. Taken together, however, the pattern defined by the illustrated arrangement of conductive interface features12may define an effectively annular or closed pattern. Thus, even though a particular conductive interface feature12may not be annular, the arrangement of multiple conductive interface features12can define an effectively annular or closed pattern to seal an interior region of the bonded structure from gas entering the interior region from the outside environs, as shown inFIG. 2E. As shown inFIG. 2D, the embodiment shown inFIG. 2Emay also include a gap bridging conductive interface feature that connects the plurality of conductive features12. In some embodiments, for example, as shown inFIGS. 2D and 2E, multiple patterns of conductive interface features12,12A,12B may be applied to form a maze-like structure including a plurality of turns. The maze-like structure can be a convoluted maze with or without the gap bridging conductive interface feature12C, in some embodiments.

The embodiments ofFIGS. 2A-2Ecan accordingly comprise interface structures10that include conductive and non-conductive interface features12,14that collectively define an effectively annular or closed diffusion barrier. For example, a particular conductive interface feature12can comprise a complete annulus or an incomplete annulus (e.g., mostly annular) that is arranged with other conductive and non-conductive interface features so as to define an effectively annular pattern or diffusion barrier. In some embodiments, the conductive interface feature can comprise other shapes, such as straight or curved segments, that are arranged about the cavity5and/or device4so as to define an effectively annular pattern or diffusion barrier. Moreover, the embodiments ofFIGS. 2D and 2Ecan advantageously provide multiple conductive segments that can each serve as separate electrical connections, for example, for separate signal line connections, ground line connections and power line connections. Together those segments can provide effectively annular conductive patterns to serve as diffusion barriers. The effectively annular patterns described herein can beneficially provide a longer distance over which gases travel to reach the sensitive components of the structure1, which can reduce the permeability of the structure1. In some embodiments, the width of the non-conductive feature14disposed between adjacent conductive feature12A and12B can be less than 10 times the width tcof conductive feature12A or12B, and preferably less than 5 times the width tcof the conductive features12. Also, the length of the conductive features12and/or the non-conductive features14can be at least 10 times the width of the conductive and non-conductive features.

FIG. 2Fis a schematic side sectional view of a bonded structure1, according to some embodiments.FIG. 2Fis similar toFIG. 1A, except inFIG. 2F, the first semiconductor element3can comprise one or a plurality of electronic components38formed or coupled with various portions of the semiconductor element3. For example, as illustrated, the semiconductor element3can comprise a plurality of electronic components38A-38C. The electronic components38A-38C can comprise any suitable type of electronic component. The electronic components38can comprise any suitable type of device, such as integrated circuitry (e.g., one or more transistors) or the like. In some embodiments, the electronic components38can communicate with the device4, the second semiconductor element2, and/or other components by way of the interconnects (seeFIG. 2B) and/or by the conductive interface features12. For example, the electronic components38can communicate with the second semiconductor element2by way of one or more conductive traces36that pass through the semiconductor element3. The electronic components38and the traces36can be defined by semiconductor processing techniques, such as deposition, lithography, etching, etc. and can be integrated with the semiconductor element3. The traces, for example, may be formed by conventional back-end-of-line interconnect metallization through multiple metal levels. Moreover, as shown inFIG. 2F, any of the embodiments disclosed herein can include one or a plurality of electronic components37formed (e.g., with semiconductor processing techniques) or coupled with the second semiconductor element2. The electronic components37can comprise any suitable type of device, such as integrated circuitry or the like, and can communicate with the device4, the first semiconductor element3, and/or other components. For example, in some embodiments, one or more electronic components37A can be defined within the semiconductor element2(e.g., buried within the semiconductor element2or exposed at the surface9). In some embodiments, one or more electronic components37B can be defined at, on or above the surface9of the semiconductor element2.

In some embodiments, the electronic components37,38may not be in electrical contact with the conductive interface features12. In such embodiments, the conductive interface features12may be used, for example, primarily for bonding the elements2,3. In some embodiments, the electronic components37,38may be in electrical connection with the device4via, for example, conductive lines through the elements2,3. In some embodiments, one or more of the electronic components37,38may be outside of the cavity5. In some embodiments, one or more of the electronic components37,38may be disposed outside of the conductive interface features12.

FIG. 2Gis a schematic side sectional view of a bonded structure1, according to various embodiments.FIG. 2Gis similar toFIGS. 1A and 2F, except inFIG. 2G, there may not be a cavity defined between the first and second semiconductor elements3,2. Rather, in the embodiment ofFIG. 2G, the first and second semiconductor elements3,2may be bonded to one another without an intervening cavity. In the illustrated embodiment, as with the embodiments described herein, the semiconductor elements3,2can be bonded to one another by way of an interface structure10that defines an effectively annular pattern or profile about the interior of the elements3,2. As explained herein, the semiconductor elements3,2can be directly bonded to one another along at least the interface structure10to define the effectively annular profile, with conductive and nonconductive interface features defined therein. The effectively annular profile of the interface structure10can comprise any of the patterns disclosed herein. Even though there may be no cavity in the bonded structure1ofFIG. 2G, the interface structure10may define an effective seal so as to protect sensitive electronic circuits or components37in the interior of the structure1from the outside environs, including, e.g., gases. It should be appreciated that any of the embodiments disclosed herein may be used in conjunction with bonded structures that do not include a cavity.

Moreover, as illustrated inFIG. 2G, the first semiconductor element3can comprise one or more electronic components38formed at or near the surface of the element3, and/or within the body of the element3. The second semiconductor element2can also include one or more electronic components37formed at or near the surface of the element2, and/or within the body of the second semiconductor element2. The electronic components37,38can comprise any suitable type of element, such as electronic circuitry that includes transistors, etc. The components37,38can be disposed throughout the elements3,2in any suitable arrangement. In the embodiment ofFIG. 2G, the first and second elements3,2can comprise any combination of device dies, such as any combination of processor dies, memory dies, sensor dies, passive elements etc. In the illustrated embodiment, the interface structure10can be disposed about the periphery of the bonded structure1so as to seal the interior of the bonded structure1from the outside environs. In various embodiments, therefore, the interior of the bonded structure1, e.g., the region within the effectively annular pattern defined by the interface structure10, may or may not be directly bonded. In the illustrated embodiment, some components37,38may be disposed within an interior region of the bonded structure1, e.g., within the effectively closed profile defined by the interface structure10. A first interconnect of the first semiconductor element3and a second interconnect of the second semiconductor element2can be directly bonded to one another within the interior region of the bonded structure1to connect components37,38in the respective elements3,2. In addition, additional components may be disposed outside the interior region defined by the interface structure10. Such additional components (such as integrated device dies) may also be directly bonded to one another outside the interior region.

FIG. 3Ais a schematic side cross-sectional view of a first semiconductor element3and a second semiconductor element2before the two elements3,2are brought together. The semiconductor elements3,2can comprise respective bonding layers11that comprise conductive interface features12comprising first and second conductive contact features12a,12b, and non-conductive interface features14comprising first and second non-conductive interface features14a,14b. As shown inFIG. 3A, the conductive interface features (or contact features)12a,12bcan be disposed below the upper and lower bonding surfaces11such that corresponding recessed spaces115a,115bare formed in the semiconductor elements3,2. The conductive features12a,12bcan be formed in the recessed spaces115a,115bin any suitable manner. For example, in some embodiments, the recessed conductive features12a,12bcan be formed using a damascene process. In such damascene processes, one or more trenches can be formed in the semiconductor element3,2(e.g., by etching), and conductive material can be supplied, for example, by way of deposition, in the trenches. The conductive material over field regions can be polished or otherwise removed to as to form the recessed contact features12a,12bofFIG. 3A. As explained above, the conductive features12a,12bcan comprise any suitable conductive material (e.g., copper (Cu)). The non-conductive features14a,14bcan comprise any suitable nonconductive or dielectric material (e.g., silicon oxide). As explained above, the bonding surfaces11can be prepared for direct bonding. For example, the bonding surfaces11can be polished, very slightly etched, and/or terminated with a desired species (such as nitrogen). Additional details of the direct bonding processes used in conjunction with each of the disclosed embodiments may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; 7,485,968, 8,735,219; 9,385,024; 9,391,143; 9,431,368; 9,953,941; and 10,032,068, and throughout U.S. Patent Application Publication No. 2017/0200711, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes.

FIG. 3Bis a schematic side cross-sectional view of an intermediate bonded structure1′ after the non-conductive features14a,14bare directly bonded together. When the non-conductive features14a,14bare brought into contact, the non-conductive features14a,14bcan be directly bonded together so as to form a chemical bond (e.g., a covalent bond) without an intervening adhesive. As explained above, the direct bonding can be conducted at room temperature and/or without the application of external pressure. After the non-conductive features14a,14bare directly bonded together, there may remain an initial gap120between the corresponding conductive features12a,12b. It will be understood that such a gap120can also be achieved after contacting the non-conductive features14a,14beven if the contacts on one side protrude.

FIG. 3Cis a schematic side cross-sectional view of a bonded structure1after the conductive features12a,12bare directly bonded together. In various embodiments, for example, the semiconductor elements3,2can be heated after directly bonding the non-conductive features14a,14b. In various embodiments, the semiconductor elements3,2can be heated in a range of 75° C. to 350° C., or more particularly, in a range of 100° C. to 250° C. Heating the semiconductor elements3,2may cause the conductive features12a,12bto expand to fill the gap120. Thus, after the conductive features12a,12bare directly bonded together, a directly bonded contact125can substantially fill the void between the two semiconductor elements3,2.

As shown inFIG. 3C, the bonding surfaces11can be directly bonded along an interface130. The interface130between the non-conductive features14a,14bcan extend substantially to the first and second conductive features12a,12b, i.e., to the directly bonded contact125. Thus, as shown inFIG. 3C, after the conductive features12a,12bare bonded together.

The distance of first and second conductive features12a,12bbelow the bonding surfaces11of the semiconductor elements3,2can be less than 20 nm and preferably less than 10 nm. Bonding followed by temperature increase can cause the conductive features12a,12bto expand, which may make a physical contact between the conductive features12a,12b, and increase the compressive force between conductive features12a,12bas they expand further and with the compressive forces and available thermal energy opposing metal grains in12aand12bexhibit intergrowth, which results in improved metal bonding, metal contact, metal interconnect, or conductance between conductive structures12. The slight distance of conductive features12a,12bbelow the respective bonding surfaces11can be an average distance over the extent of the conductive features12. The topography of the conductive features12may also include locations equal, above, and below the average distance. The total height variation of the conductive features12, given by the difference between the maximum and minimum height, may be substantially greater than the root-mean-square (RMS) variation. For example, a conductive feature with a RMS of 1 nm may have a total height variation of 10 nm.

Accordingly, although conductive features12a,12bmay be slightly below the bonding surfaces11, a portion of conductive features12a,12bmay extend above the bonding surfaces11, resulting in a mechanical connection between the conductive features12a,12bafter bonding of the bonding surfaces11. This mechanical connection may not result in an adequate electrical connection between conductive features12a,12bdue to an incomplete or non-uniform mechanical connection or native oxide or other contamination on conductive features12a,12b. Subsequent temperature increase may improve the metal bonding, metal contact, metal interconnect, and/or conductance between conductive features12a,12bas described above.

Alternatively, the temperature increase may result in mechanical contact and/or desired electrical interconnection between conductive features12a,12bif the highest portion of conductive features12a,12bis below bonding surfaces11and there is not a mechanical contact between conductive features12a,12bafter bonding.

Alternatively, conductive features12amay be recessed below the bonding surface11of the first element3and conductive features12bmay protrude above bonding surface11of the second element2, or conductive features12amay protrude above the bonding surface11of the first element3and conductive features12bmay be recessed below the bonding surface11of the second element2. Alternatively, the difference between the distances of the recessed conductive features12a,12bbelow the bonding surfaces11can be nominally zero or slightly negative. In some embodiments, the slightly negative recess may be preferable. A post-bond temperature increase may improve the metal bonding, metal contact, metal interconnect, conductance between conductive features12a,12bvia intergrowth of opposing grains as described above.

The height or depth of, for example, a protrusion or a recess of conductive features12a,12brelative to the bonding surfaces11of elements3,2can be controlled with a polishing process that forms the surfaces of elements3,2, for example using chemical mechanical polishing (CMP). The CMP process typically may have a number of process variables including but not limited to the type of polishing slurry, rate of slurry addition, polishing pad, polishing pad rotation rate, and polish pressure. The CMP process can be further dependent on the specific non-metal and metal materials comprising the semiconductor elements3,2, and the relative polishing rates of non-metal and metal materials comprising the bonding surfaces10. Alternate polishing techniques, for example slurry-less polishing, may also be used.

The height or depth of conductive features12a,12brelative to the bonding surfaces11may also be controlled with a slight dry etch of the material around conductive features12a,12bon the surfaces of semiconductor elements3,2, for example using a plasma or reactive ion etch using a mixture of CF4and O2, for the surfaces comprised of certain dielectric materials, for example silicon oxide, silicon nitride, or silicon oxynitride, preferably such that an increase in surface roughness, that would significantly decrease the bond energy between said surfaces, results. Alternatively, the height or depth of conductive features12a,12bmay be controlled by the formation of a very thin metal layer on the conductive features12a,12b. For example, electroless plating of some metals, for example a self-limiting thin layer of gold, approximately 5-50 nm may be coated over the conductive features12(for example nickel or nickel alloys). This method may have the additional advantage of terminating an oxidizing metal with very thin non-oxidizing metal, for example gold on nickel, to facilitate the formation of electrical connections.

FIG. 4Ais a graph generated by an atomic force microscope (AFM) showing measurements of surface levels of a copper (Cu) region204and oxide regions206of an element, at room temperature before annealing200and after annealing202. Both AFM measurements are performed at room temperature. A horizontal axis of the graph shows a horizontal measurement of a surface of the element and a vertical axis of the graph shows a vertical measurement of the surface. As shown inFIG. 4A, the Cu region204is comprised at around 35 μm to 50 μm on the horizontal axis and the oxide regions206are comprised below about 35 μm and above about 50 μm on the horizontal axis. The element used in this measurement comprises an oxide non-conductive bonding surface and has a 750 μm×750 μm shape with a Cu ring having a width of about 15 μm embedded in the element. The element was prepared with chemical mechanical polishing (CMP) before annealing200. The annealing was conducted in nitrogen gas for 2 hours at 300° C. Before annealing200, the Cu region of the graph measures about −12 nm on average on the vertical axis, i.e., about 12 nm below the bonding surface of a surface of the oxide region206. After annealing the element used in this measurement for 2 hours at 300° C., it was brought back to room temperature and the after annealing202AFM measurement was taken. After annealing202, the Cu region comprises a protrusion or hillock of about 70 nm above the bonding surface of the surface of the oxide region206. This change after annealing202was permanent and due at least in part to plastic deformation of Cu. With a large mismatch between coefficient of thermal expansion (CTE) between copper and silicon oxide, the lateral expansion of copper is constrained (as it is surrounded by oxide) and it mostly expands in the vertical direction. The hillock formation may be caused when a relatively large amount of Cu is annealed as the copper grain growth occurs at this high annealing temperature. Hillocks may form to some extent with a small amount of copper, but the effects of hillock formation may be magnified with larger and/or thicker pads. In some embodiments, a Cu pad that has a width of, for example, more than about 3 μm. In some other embodiments, a Cu pad that has the width of, for example, more than about 7 μm may be problematic. In some embodiments, the Cu pad that has a width in a range of, for example, 2 μm to 500 μm, in a range of, for example, 7 μm to 250 μm, in a range of, for example, 15 μm to 250 μm, in a range of, for example, 25 μm to 100 μm, etc. may be problematic. However, it may not be problematic when adequate thermal treatment protocols are utilized during the bonding operation. In some embodiments, a Cu pad that has a surface area of, for example, more than about 10 μm2may be problematic. In some other embodiments, a Cu pad that has the surface area of, for example, more than about 20 μm2may be problematic. In some embodiments, Cu pad that has a surface area in a range of, for example, 10 μm2to 0.25 mm2, in a range of, for example, 20 μm2to 0.25 mm2, in a range of, for example, 50 μm2to 0.2 mm2, in a range of, for example, 100 μm2to 0.2 mm2, etc. may be problematic. However, it should be understood that other factors, such as a thickness of the Cu pad and annealing temperatures, may contribute to the formation of the hillocks. A higher annealing temperature may cause a rougher surface and/or more hillocks on the exposed copper surface than a lower annealing temperature. In some embodiments, hillock formation in the Cu pad may be reduced or suppressed by annealing the Cu pad in vacuum environment. It was also measured that surface roughness of the element changed from about Rq=0.65 nm before annealing200to about Rq=33 nm after annealing202for the unbounded surface. In practice, during the higher thermal treatment of elements3and2ofFIG. 3B, the conductive features12a,12bare separate by the prevailing recess between the conductive features12a,12b. The conductive features12and12bare bounded or confined within the prevailing recess and the type of hillocks ofFIG. 4Ais not exhibited. When bonding a set of elements like that used in this measurement, the changes of the surface level of the Cu region after annealing202can create challenges to, for example, forming a reliable and/or uniform Cu to Cu direct bond.

For example, when the conductive features12a,12bofFIGS. 3A-3Ccomprise a relatively large or wide ring (e.g., a seal ring) disposed around an integrated device, annealing may cause the conductive features12a,12b(Cu) to protrude above the bonding surface, which can reduce the reliability of a direct bond. For example, for conductive features that have a lateral dimension (e.g., width) larger than about 5 microns (e.g. in a range of 5 microns to 15 microns), hillock formation after annealing can reduce bonding reliability. By contrast, for relatively small contacts (e.g., for conductive features with a lateral dimension or width less than about 5 microns), the conductive features may not form significant hillocks, resulting in a reliable direct bond. Moreover, CMP planarizing process for relatively small pads may not be challenging; and planarization becomes increasingly difficult as pad size increases.

FIGS. 4B and 4Cshow graphs showing measurements of surface levels of copper (Cu) regions204and oxide regions206of an element.FIG. 4Bshows the measurement of the element after CMP and before annealing.FIG. 4Cshows the measurement of the element after annealing at 300° C. for one hour. A horizontal axis of the graph shows a horizontal measurement of a surface of the element and a vertical axis of the graph shows a vertical measurement of the surface. The Cu region204comprises 1-micron width grid pattern. In some embodiments, this may be considered as a relatively small pad of Cu or trace. The measurements show recesses from top surfaces of the oxide regions206to bottom portions of the Cu regions204. In the measurement before annealing, as shown inFIG. 4B, the recess is about 6.8 nm in average and after annealing, as shown inFIG. 4C, the recess is about 6.6 nm in average. In some embodiments, this difference may be considered as not significant for a reliable direct bond. Referring back toFIGS. 3A and 3B, for conductive features12a,12bwith smaller widths, sidewalls of the corresponding recessed spaces115a,115btend to pin or suppress the expansion of the conductive features, as a result, much higher temperature may be needed to bond the elements3,2. While for conductive features12a,12bwith large widths, the sidewall of the corresponding recessed spaces115a,115bis less effective in suppressing metal protrusion or hillocks and lower bonding temperature, such as below 250° C., is effective in bonding the elements3,2.

FIG. 5is a schematic top sectional view of an element (e.g., the first or second semiconductor element3,2) having a conductive interface feature12and a nonconductive interface feature14disposed around a cavity5. The element3,2can include the cavity5as shown, but in other embodiments (such as that shown inFIG. 2G), no cavity may be provided. In some embodiments, one or more integrated device(s) may be disposed in the cavity5, or otherwise within the seal ring defined by the conductive feature12. The one or more of integrated device(s) may be coupled to or formed with the element3,2. The conductive interface feature12ofFIG. 5may have similar structural features as the conductive interface feature12ofFIGS. 2A-2G, so as to substantially seal the integrated device and/or the cavity5from the outside environs. For example, as explained above and as shown inFIG. 5, the conductive feature12can comprise a completely annular structure disposed about the cavity5. In other embodiments, such as those shown inFIGS. 2D-2E, the conductive feature12can comprise an incomplete annular structure such that there are gaps between portions of the conductive feature12.

The conductive interface feature12can comprise an elongate conductive feature that has a width w and a length l (along at least one side of the ring or annular structure) that is longer than the width w. In some embodiments, for example, the length l may be at least twice the width w. In some embodiments, the conductive interface feature12may have the width w in a range of, for example, 2 μm to 30 and the length l in a range of 50 μm to 20 mm. The conductive interface feature12may comprise a continuous ring that surrounds the cavity5as illustrated inFIG. 5. However, as explained above with respect to, for example,FIGS. 2A to 2G, the conductive interface feature12may have any suitable structure that effectively seals the interior of the bonded structure (e.g., the cavity5and/or integrated devices) from the outside environs.

Furthermore, although the conductive feature12shown herein comprises an annular structure or ring about the cavity5, other embodiments disclosed herein can be used in conjunction with conductive interface features that may not be disposed around an integrated device or cavity. For example, other embodiments disclosed herein may be used with other types of elongate contact features that are not formed in an annular pattern, but which have a length l greater than its width w. For example, the embodiments disclosed herein may also be used in conjunction with the elongate contact features disclosed throughout U.S. Pat. No. 9,852,988, the entire contents of which are incorporated by reference herein in their entirety and for all purposes. Indeed, the embodiments disclosed herein can be used in conjunction with any suitable conductive interface features that have a relatively large volume of conductive (e.g., metallic) material, for example, with conductive features having a lateral dimension (e.g., width) greater than about 5 microns.

FIG. 6Ais a cross sectional view of the semiconductor element3,2shown inFIG. 5, taken along the length of the conductive interface feature12, according to one embodiment. The conductive interface feature12may comprise any suitable material, such as, for example, copper (Cu). The conductive feature12includes recesses218on a back side220(e.g., opposite the bonding surface) of the conductive interface feature212. In some embodiments, the recesses218may be formed as a result of depositing metal over previously formed islands, such as dielectric posts50, as described in examples of formation below. The nonconductive interface feature14may comprise any suitable material, such as, for example, silicon oxide and/or silicon nitride. Other underlying portions52of the nonconductive feature14may be disposed along the back side220of the conductive feature12. Additionally, adjacent portions54of the nonconductive feature14may be disposed laterally adjacent the conductive feature12as shown above inFIG. 5. Thus, on a particular element3or2, the nonconductive feature14can include portions disposed adjacent the conductive feature12(e.g., as shown by the adjacent portions54inFIG. 5), portions disposed underneath the conductive feature12(e.g., the underlying portion52), and a nonconductive island, such as the illustrated dielectric post50, disposed in the recesses218. In some embodiments, different portions of the nonconductive feature14may comprise different materials. For example, the nonconductive feature14may comprise a silicon oxide layer and a silicon nitride layer. Example processes for forming the nonconductive islands and complementary conductive recesses are described below.

The recesses218may prevent or mitigate the hillock formation that is observed inFIG. 4Afor conductive features that are relatively large (e.g., for conductive features that have lateral dimensions greater than about 5 microns). For example, the recesses218may reduce a thickness of the conductive interface feature12measured from the back side220to a front side222opposite the back side which may prevent or mitigate the hillock formation. For example, the dielectric posts50can act as expansion constraints such that the conductive feature12may effectively expand in a vertical direction without causing hillocks, resulting in an improved direct bond. As mentioned earlier (e.g., in paragraph 70), for relatively small contacts, the conductive features may not form significant hillocks, for example, due to the constraint to its expansion in all 4 lateral dimensions due to the rigid silicon oxide and as it expands only in the vertical direction. For larger pads, as one or more lateral dimensions are relaxed, this may result in plastic deformation, hillock formation and significant increase in rms roughness of the contact pad, as depicted by202inFIG. 4. The recesses218may be formed in any suitable manner. For example, prior to providing the conductive interface feature12, portions of the nonconductive feature14may be etched such that the dielectric posts50are formed, for example, by damascene methods. In some embodiments, for example, to form the dielectric posts50, a mask may be formed on a first side of the nonconductive feature14. A cavity in the form of an initial trench49may be formed in the nonconductive feature14with a first mask by, for example, dry etching (e.g.,) reactive ion etching (ME) or wet etching method to remove portions of the nonconductive feature14to a first defined depth. In some embodiments, the first mask can be removed, and a second mask formed to exposes regions for post50. Similarly, portions of the nonconductive feature14is removed by RIE or wet etch methods to a second defined depth, where the second defined depth is shallower than the first defined depth.

After forming the trenches49with the dielectric posts50therein, the conductive interface feature12may be deposited into the trenches49etched into the nonconductive feature14. In some embodiments, a barrier layer and/or a seed layer may be applied over the nonconductive feature14and into the trenches49to cover the dielectric posts50, and then metal (such as copper) can fill the trenches49(such as by electroplating) and overlie the dielectric posts50, thus defining the recesses218of the conductive interface feature12. In some embodiments, after coating the conductive interface feature12, portions of the nonconductive feature14and the conductive feature12can be removed by, for example, planarization methods to form the bonding surface222. Still other ways of forming the dielectric posts50and other components may be suitable.

The conductive interface feature12has a thickness t1from the front side222to the back side220. In some embodiments, the thickness t1may be in a range of, for example, 0.5 μm to 5 μm. The recess218formed in the conductive interface feature12has a recess thickness t2from the back side220of the conductive interface feature to a recessed surface219, which can be about 50% of the thickness t1of the conductive interface feature12. In some embodiments, the thickness t2can be in a range of, for example, 10% to 90%, 20% to 80%, etc. of the conductive interface feature12. However, the dimension of the thickness t1may vary along different portions of the conductive interface feature12. Therefore, in some embodiments, cross sections of the conductive interface feature12along the length taken at different locations may vary. In some embodiments, a first cross section of the conductive interface feature12may have the recess218but a second cross section of the conductive interface feature12may not have the recess.

The conductive interface feature12can have a pitch or displacement dimension d1from one recess to a next recess, and the recess can have a lateral dimension d2in a horizontal direction. In some embodiments, the displacement dimension d1may depend on the number of recesses218that are formed in the conductive interface feature12. For example, the displacement dimension d1is less than the length l of the conductive interface feature12. The dimension d2of the recess218may be less than 50% of the length l of the conductive interface feature12. The dimension d2of the recess218may be more than 1 μm. In some embodiments, the dimension d2of the recess218may be in a range of, for example, 2 μm to 10 μm. However, the dimension of the dimensions d1and d2may vary along different portions of the conductive interface feature. Therefore, in some embodiments, cross sections of the conductive interface feature along the length taken at different locations may vary.

A skilled artisan will understand that, while the recess218shown inFIG. 6Ahas a polygonal shape (e.g., a trapezoid shape), the recess218may have any suitable shape, as viewed from a side cross-section. The shape of the recess may depend at least in part on the manufacturing process(es) used, in some embodiments. Further, the recesses may not have identical sizes in some embodiments. For example, the conductive interface feature12may have a varying width with differently sized recesses along the length of the length.

FIG. 6Bis a cross sectional view of the semiconductor element3,2ofFIG. 5, taken along a length of the conductive interface feature12, according to another embodiment. Instead of having two recesses218illustrated inFIG. 6A,FIG. 6Bshows more than two (e.g., nine) recesses formed through the back side220of the conductive interface feature12along its length. It should be understood that the number of recesses may be chosen based at least in part on the length l of the conductive interface feature12, the thickness t1of the conductive interface feature12, the recess thickness t2of the conductive interface feature12, and/or the dimension d2of the recess218. Having more recesses may reduce the amount of the conductive interface feature12and produce more constraint on the conductive interface feature12to expand in the vertical dimension used in the semiconductor element3,2.

FIG. 6Cis a cross sectional view of the semiconductor element3,2ofFIG. 5, taken along a length of the conductive interface feature12, according to another embodiment. Unlike the embodiments shown inFIGS. 6A and 6B, the recesses218ofFIG. 6Ccan be formed on the front side222of the conductive interface feature12. In such embodiments, unlike the embodiments ofFIGS. 6A and 6Bwhere the trench includes the posts50, the embodiment ofFIG. 6Ccan include dielectric islands51. The dielectric islands51may be formed, for example, after filling the conductive interface feature12(such as copper) into the trench49. At least a portion of the conductive interface feature12can be removed from the front side222and the dielectric can be disposed into the removed portion. In such embodiments, the trench includes the posts51. AlthoughFIG. 6Cshows the thickness t2of the dielectric island51as being smaller than thickness t1, in some other embodiments the thickness t2may be the same as the thickness t1. In some embodiments, a combination of a front side recess arrangement and a back side recess arrangement may be provided on a conductive interface feature12. As with the embodiments ofFIGS. 6A and 6B, the conductive interface feature may comprise any suitable number of recesses, and any suitable shapes of recesses formed therein. Embodiments shown inFIGS. 6A and 6B(andFIG. 6Cwhere the thickness t2is equal to the thickness t1) can be manufactured using, for example, a dual damascene process. Embodiment shown inFIG. 6Cmay be a single damascene process; a via can be made in the conductive trace, which can be back-filled by non-conductive material, e.g. silicon oxide, nitride or the combination of both.

FIG. 6Dis a top plan view of a portion of the conductive and non-conductive features12,14shown inFIG. 6C.FIG. 6Dshows the conductive interface feature12and the nonconductive feature14disposed in the recesses218. As shown inFIG. 6D, the dielectric islands51can be surrounded laterally by conductive material of the conductive interface feature12, which can improve the sealability provided by the conductive feature12. The recesses218shown inFIG. 6Dhave a dimension d3, which is measured along the lateral dimension of the conductive interface feature12, that is smaller than the width w, leaving portions of the conductive interface feature12on the front side222for forming a continuous periphery for sealing the cavity5when bonded to another element.

FIG. 7Ais a cross sectional view of the semiconductor element3,2ofFIG. 5, taken across a width of the conductive interface feature12, according to one embodiment.FIG. 7Ashows the conductive interface feature12and the nonconductive interface feature14underlying the conductive feature12. The illustrated cross section inFIG. 7A(seeFIG. 5for the location of the cross-section) does not include a recess. Rather, in the cross-section shown inFIG. 7A, the conductive interface feature12may have a generally constant thickness across the width of the element.

FIG. 7Bis a cross sectional view of the semiconductor element3,2ofFIG. 5, taken across a width of the conductive interface feature12at a different location along the length as compared with the cross-section ofFIG. 7A. The recess218has the dimension d3measured along the width of the conductive interface feature12that is perpendicular to the dimension d2. The dimension d3of the recess218may be in a range of 10% to 80% of the width w of the conductive feature12. In some embodiments, there may be a plurality of recesses along the width of the conductive interface feature212.

FIG. 8Ais a cross sectional view of a bonded structure1, taken along a length of the conductive interface feature12, according to one embodiment. The bonded structure1may comprise a first element3and a second element2directly bonded to the first element3without an intervening adhesive. The first and second elements3,2ofFIG. 8Amay include recesses218similar to those illustrated inFIGS. 6A and 6B, e.g., the recesses218may be provided in respective back sides220of the conductive features12(e.g., opposite the bonding surfaces of the elements3,2). The bonded structure1comprises a bonded conductive interface feature34that may comprise first and second conductive interface structures12a,12b, and first and second nonconductive interface features14a,14b.

The bonded conductive interface feature34may have recesses218. In some embodiments, as illustrated inFIG. 8A, the recesses218may be formed on a back side220aof the first conductive feature12aon the element3and/or on a back side220bof the second conductive feature12bof the element2of the bonded conductive interface feature34. The back sides220a,220bmay comprise recessed surface219. The bonded conductive interface feature34may have an overall thickness t3from the back side220aof the first element3to the back side220bof the second element2. The thickness t3may vary along the length l (and/or the width w) of the bonded conductive interface feature34. As used herein, the back sides220a,220bmay follow the contours along the back surface of the conductive features12a,12b, such that the overall thickness t3varies along the length and/or width of the bonded structure (e.g., the back sides220a,220bfollow the contours of the recessed surface219as well as the non-recessed surfaces and the angled surfaces between the recessed surface219and the non-recessed surfaces). For example, the thickness t3at recess portions (such as the portion shown in Region A inFIG. 8A) may be smaller than the thickness t3at portions that do not have the recess (such as the portion shown in Region B inFIG. 8A). In another embodiments, the recess218in element2and recess218in element3are on top of each other, hence t3would be even smaller than that shown in Region A inFIG. 8A.

FIG. 8Bis a cross sectional view of a bonded structure1taken along a length of the conductive interface feature12, according to another embodiment. The bonded structure1may comprise a first element3and a second element2directly bonded to the first element3without an intervening adhesive. The first and second elements3,2ofFIG. 8Bmay include recesses218similar to those illustrated inFIGS. 6C and 6D, e.g., the recesses218may be provided in respective front sides222of the conductive features12(e.g., along the bonding surfaces of the elements3,2). The bonded structure1comprises a bonded conductive interface feature34that may comprise first and second conductive interface structures12a,12b, and first and second nonconductive interface features14a,14b. The nonconductive interface features14a,14bin the recesses218illustrated inFIG. 8Bmay be isolated from portions of the nonconductive interface features14a,14bthat are disposed on the back sides220a,220bof the elements3,2. In some embodiments, the number of recesses218formed in the bonded structure1may vary along different portions of the conductive interface feature12. Therefore, in some embodiments, cross sections of the bonded conductive interface feature34along the length taken at different locations may vary. In some embodiments, a first cross section of the bonded structure1may have the recess218(Region A) but a second cross section of the conductive interface feature12may not have the recess (Region B). For example, as shown inFIG. 8B, in Region A, the overall or total thickness may be given by t4+t5along a particular cross-section. In Region B, the overall or total thickness may be t. Hence, at different locations or cross-sections along the length of the bonded structure, different amounts of the bonded conductive interface feature34may be formed. The different amounts of the bonded conductive interface feature at different locations along the length of the bonded conductive interface feature34may reduce the chance of before mentioned hillock formation. In some embodiments, the recesses218of the elements2,3may fully or partially overlap. For example, the respective recesses219,218of the first element3and the second element2may at least partially overlap to, for example, bond intimately contact during the bond process. The bonded recesses218,219secure the opposing conductive interface feature12a,12bof elements3,2in intimate contact for their bonding at subsequent times or subsequent higher temperature processing. As explained above, this is one of the additional benefits of having the recesses218,219.

FIG. 9Ais a cross sectional side view of a conductive interface feature12with recesses218formed therein. Portions44of the conductive interface feature12where the recesses218are formed have a shortened thickness defined by the thickness t1from a front side222to the back side220minus the recess thickness t2from the back side220of the conductive interface feature to a recessed surface219.

FIG. 9Bis a top-down plan view of the conductive interface feature12shown inFIG. 9A. The conductive interface feature12may have extended width portions44at the portions of the conductive interface feature12where the recesses218are formed to, for example, strengthen the bonding strength. The extended width portions44can extend laterally outwards from the conductive feature12. The increased surface area provided by the extended width portions44can improve sealability as well as mechanical strength of the portions of the conductive interface feature12overlying (or underlying) the recesses218. The extended width portions44may have an extended width w′ that is about 150% (e.g., 120% to 180%) of the width w of portions of the conductive interface feature12that do not include the recesses218.

FIG. 9Cis a bottom-up view of the conductive interface feature12shown inFIGS. 9A and 9B. The recesses218are disposed within the extended width portions44. In some embodiments, determination of the extended width w′ may depend at least in part on the horizontal dimensions d2, d3of the recesses218. Although recesses218and extended width portions44are shown to be square or rectangular shape, they may be of any other shape. e.g. circular, oval, etc.

FIG. 10is a cross sectional view of a portion of a semiconductor element100, according to various embodiments. The semiconductor element100includes a conductive interface feature12and a nonconductive interface feature14. The conductive interface feature12has a front side222and a back side220. The conductive interface feature12can have a recess218on the back side220. The nonconductive interface feature14can have a first portion50that is disposed laterally adjacent to the conductive interface feature12. The nonconductive interface feature14can also have a second portion that is disposed in the recess218. As used herein, the conductive interface features12can be formed in one level of metallization according to some embodiments.

In the embodiment ofFIG. 10, the conductive interface feature12can comprise a bond pad or other type of contact, which may be elongated (e.g., having a length greater than its width) or may not be elongated. In such embodiments, the conductive feature12may comprise a large amount of conductive (e.g., metallic) material, but may not extend around the integrated device in an annular seal structure. Accordingly, the embodiments disclosed herein can be utilized in embodiments in which a large amount of conductive material is used for bond pads (in addition to embodiments that utilize elongate conductive features and/or conductive features that define an effectively annular or closed profile). The conductive interface feature12ofFIG. 10may have a length x and a width y. In some embodiments, the length x can be in a range of 2 um to 50 um and the width y can be in a range of 0.2 um to 50 um. The recess218can allow for reduction of the amount of the conductive interface feature12used in the element100. Although one recess218is shown inFIG. 10, a skilled artisan will understand that more than one recesses218can be formed.

In one aspect, a bonded structure is disclosed. The bonded structure comprises a first element, a second element bonded to the first element along a bonding interface. The bonding interface comprises an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature comprises a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

In one aspect, a bonded structure is disclosed. The bonded structure includes a first element and a second element. The first element comprises a first conductive interface feature and a first nonconductive interface feature. The second element comprises a second conductive interface feature and a second nonconductive interface feature. The second element is bonded to the first element along a bonding interface. A first cross-section of the first conductive interface feature that is taken along a lateral dimension of the first conductive interface feature has a first overall thickness along a vertical dimension transverse to the lateral dimension. A second cross-section of the first conductive interface feature along the lateral dimension of the first conductive feature has a second overall thickness along the vertical dimension. The first overall thickness is different from the second overall thickness.

In one aspect, a semiconductor element is disclosed. The semiconductor element includes a metallic interface feature and a nonconductive interface feature. The metallic interface feature comprises a recess through a portion of a thickness of the metallic interface feature. The nonconductive interface feature comprises a first portion that is disposed laterally adjacent to the metallic interface feature and a second portion disposed in the recess. The semiconductor element further includes an integrated device coupled to or formed with the semiconductor element. The integrated device is in electrical communication with the metallic interface feature.

In one aspect, a method of forming an apparatus is disclosed. The method includes forming a first element comprises a first elongate conductive interface feature and a first nonconductive interface feature. The method also includes forming a second element that comprises a second elongate conductive interface feature and a second nonconductive interface feature. The method further includes bonding the first and second elements along a bonding interface. The bonding interface comprises the first and second elongate conductive interface features and the first and second nonconductive interface features. The first elongate conductive interface structure is formed over a nonconductive post in the first element.

In one aspect, a semiconductor element is disclosed. The semiconductor element includes a first elongate conductive layer that is embedded in a non-conductive layer. The first elongate conductive layer has a thickness that varies along its length. The semiconductor element also includes a second elongate conductive layer that is embedded in the non-conductive layer. The semiconductor element further includes an integrated device. The first and second elongate conductive layers are disposed around the integrated device. The first and second elongate conductive layers comprise a maze-like structure including a plurality of turns.

In one aspect, a bonded structure is disclosed. The bonded structure includes a first element that comprises a first conductive layer and a nonconductive interface feature. The first conductive layer has a thickness that varies along its length. The bonded structure also includes a second element that comprises a second conductive layer that is directly bonded to the first element. The first element comprises a first elongate conductive layer that is embedded in a first non-conductive layer of the first element. The bonded first and second elongate conductive layers of the first and second elements comprises a maze-like structure including a plurality of turns.

For purposes of summarizing the disclosed embodiments and the advantages achieved over the prior art, certain objects and advantages have been described herein. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

All of these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment(s) disclosed. Although this certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the disclosed implementations. Thus, it is intended that the scope of the subject matter herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.