Transmission device

A transmission device which cross connects channels on a synchronous multiplex transmission network which forms a ring, and which performs restoration of communication by looping back signals in a protection path when a failure occurs includes a memory area which stores information for determining whether an alarm indication signal needs to be inserted in a channel or not, wherein the size of the memory area corresponds to the number of channels targeted for the restoration, and a part which inserts said alarm indication signal in a channel by switching results of the determination according to predetermined information. Further, the transmission device may switch and recover a path without skipping an event which arises between polling accesses by a CPU of said transmission device. Furthermore, the transmission device may include a part, provided in each interface part, which performs phase adjusting of channel signals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a transmission device. More particularly, the present invention relates to a transmission device which adapts to various network configurations in a synchronous multiplex transmission network.

2. Description of the Related Art

Because of an increase of traffic, the use of synchronous multiplex transmission which utilizes optical communications for high-capacity transmission is in high demand. Especially, a synchronous multiplex transmission system which has a capability of transmission line switching in case of transmission line failure and which can form a ring, such as SONET, is widely used from the viewpoint of supporting diverse network configurations and ensuring reliability of a network.

An ADM (Add/Drop multiplexer) device, for example, is used as a transmission node of a synchronous multiplex ring transmission network. The ADM device can access a desired VT channel in an STS signal, where STS is a channel hierarchy of SONET.

FIGS. 1A and 1Bare conceptual diagrams for explaining UPSR which is a transmission line switching system in a SONET ring network. UPSR, an abbreviation of Unidirectional Path Switched Ring, is an example of a system in which a path is switched and is recovered by selecting, at a receiving node, either of two path signals which are sent in two different directions over the synchronous multiplex transmission network from a sending node. InFIGS. 1A and 1B, each of a node A1, a node B2, a node C3, and a node D4is a node which constitutes a SONET ring, andFIGS. 1Aand B show a case in which a signal enters the node A1and exits from the node C3.

InFIG. 1A, a signal which enters the node A1is sent along two routes, one of the routes going through the node A1, the node D4, and the node C3and another route going through the node A1, the node B2, and the node C3. Then, the signal from the route along the node A1, the node D4, and the node C3is selected under normal conditions at the node C3. A path in a route selected under normal conditions, such as the route along the node A1, the node D4, and the node C3in the case ofFIG. 1, will be called a default path hereinafter.

As shown inFIG. 1B, if a fault occurs in a path between the node A1and the node D4, which, fault will cause a communication interruption, the path is switched to a path in the route along the node A1, the node B2, and the node C3so that the communication continues. A path which is a destination of such a path switching from a default path, such as the path in the route along the node A1, the node B2, and the node C3, will be called a non-default path hereinafter. In addition, the above-mentioned capability will be called path protection switching hereinafter.

FIGS. 2A and 2Bare conceptual diagrams of BLSR in a SONET ring network. BLSR is an abbreviation of Bidirectional Line Switch Ring, and is an example of a system which carries out cross connecting on a synchronous multiplex ring transmission network and which restores communication by looping back a signal using a protection channel when a transmission line failure arises. InFIGS. 2A and 2B, each of the node A1, the node B2, the node C3, and the node D4is a node which constitutes a SONET ring, andFIGS. 2A and 2Bshow a case in which a signal enters the node A1and exits from the node C3.

As shown inFIG. 2A, initially, a signal which enters the node A1is sent to the node C3on the route along the node A1, the node D4, and the node C3. Then, when a transmission failure occurs between the node A1and the node D4, which transmission failure results in a communication interruption, the signal is transmitted through the node A1, the node B2, the node C3, the node D4, and the node C3by using a protection channel.

FIG. 3shows, as an example, a system block diagram of a transmission device5which accesses a desired VT channel in any STS signal of SONET, and mainly shows a part for carrying out channel cross connecting. The transmission device5includes an STS cross-connecting part10for cross connecting an STS signal, a VT cross-connecting part20for cross connecting a VT signal, interface (INF) parts301-30nfor inputting signals, and interface (INF) parts401-40nfor outputting signals. The STS cross-connecting part10includes STS TSI parts11,12,13for performing cross connection of an STS signal, STS PSW parts14,15for path protection switching in UPSR, and a selector (SEL)16for selecting either of a path accessed in the STS level or a path accessed in the VT level. The VT cross-connecting part20includes a VT SQL part21for performing VT squelch, a VT TSI part22for cross connecting a VT level signal, and a VT PSW part23for path protection switching in UPSR. Squelch is a process for inserting an alarm indication signal into an unrecoverable channel.

InFIG. 3, signals input from the INF parts301-30nbranch to STS level signals and VT level signals at a branchpoint24. The STS level signals enter the STS TSI part12, and are cross connected in terms of STS level, and, if selected at the SEL part16, the signals are output to the INF parts401-40nthrough the STS PSW part15. The VT level signals are cross connected in the STS TSI part11at STS level, and enter the VT cross-connecting part20which cross connects the entered signals at the VT level. Then, through the TSI PSW part23, the signals enter the STS TSI part13which cross connects the signals, and, if the signals are selected at the SEL part16, the signals are output to the INF parts401-40n. In addition, VT squelch is performed in the VT SQL part21in which an alarm indication signal (AIS) is inserted into a VT channel in which a misconnection occurs.

FIG. 4is a conceptual diagram of a VT access ring for explaining the VT squelch.FIG. 4shows a BLSR configuration which has two fibers, an inside one and an outside one. Each of the inside line and the outside line has a protection channel and an active channel of BLSR. As shown inFIG. 4, a VT signal added at the node C3goes through the node B2and is dropped at the node A1. In this case, the squelch table of the node A1includes “2” as an STS level source node ID, “2” as an STS level destination node ID, and “3” as a VT level source node ID. If a failure occurs between an E point6and an F point7, STS level squelch will not be carried out because the node A can recognize the node B in the STS level. As for the VT level, squelch will be carried out for the VT channel signal which has the source node ID “3” in the corresponding squelch table because the node A can not recognize the node C. A VT path AIS is inserted into the VT channel for which squelch is carried out.

FIG. 5is a block diagram of a conventional VT SQL part21for performing the above-mentioned VT squelch. A squelch table setting part60includes registers which accommodate 28 VT channels per each of STS channels601-60n, where data setting to each register is performed by a control part67. “Far End Node ID”, that is, the node ID of the farthest node among connected nodes to which data can be transmitted is sent to each of SQL decision parts621-62n. For example, in the network shown inFIG. 4, when a failure arises at the F point7, node ID “4” is sent from the node D to the node A. Each of the SQL decision parts621-62ndetermines whether VT squelch should be carried out or not on the basis of comparison between the “Far End Node ID” and the setting data in the squelch table setting part60. The result of the decision is stored in each of the latching parts641-64n. Then, a VT path AIS is inserted into channels which are applicable for squelch insertion in a squelch inserting (INS) part66.

FIG. 6is a block diagram of the STS PSW part14, or15, or VT PSW part23inFIG. 3, that is, a block diagram of a part for path protection switching of the above-mentioned UPSR. InFIG. 6, each of default side data77and non-default side data78is input into a selector (SEL)76, and either of those data is selected and output. Each alarm of default side data77and non-default side data78is input to an ALM detection part70of a default side and an ALM detection part71of a non-default side respectively.

Now, before a WTR control register74is described, WTR will be described. WTR, an abbreviation of “Wait To Restore”, is a process in which if a default path is switched to a non-default path by a network failure, the default path is recovered from the non-default path after a predetermined time passes from the time when the failure of the default path is fixed.

Information of a working time of the WTR timer is recorded in a WTR control register74from a CPU73. The CPU73reads the information and an alarm information stored in the ALM notification register72by a polling, and makes a decision on path selection. The PSW control part75outputs the path selection information to the selector (SEL)76which selects a path.

FIG. 7is a time chart showing the operation of the above-mentioned WTR. The CPU73periodically reads the ALM notification register72by polling so as to monitor an alarm of the default path. When an alarm is detected in the default side at the timing of polling2, the PSW control part switches the default path to the non-default side and keeps the state by the control of the WTR control register74. After the CPU73recognizes a default side alarm at polling2, when the CPU73recognizes disappearance of the alarm at polling3, the WTR timer starts and the switched path is recovered by the PSW control part75if a default side alarm is not detected during the predetermined time of n minutes, which event is recognized by polling6.

FIG. 8is a block diagram of a conventional part for generating an STS signal and performing cross connection. Signals input into each of interface (INF) parts801-80nare assembled into an STS frame in each of the interface (INF) parts801-80n, and the STS frame is output from each of interface (INF) parts811-81nafter phase adjusting and cross connection is performed in a common part90.

Since each of the interface (INF) parts801-80nhas the same configuration as that of the interface (INF) part801, only the interface (INF) part801will be described in the following. An STS frame generating part82generates an STS frame according to a timing pulse generated by a pulse generating part84. The generated STS frame is multiplexed by a MUX86and, sent to the common part90. The pulse generating part84and the MUX86operate by a clock from a PLL88. In addition, the PLL88receives a clock from a system clock100.

The STS signals sent to the common part90are out of phase in channels. Therefore, the phase of each channel will be adjusted by replacing a pointer in each of pointer parts921-92n. The phase adjusted signal of each channel is cross connected in a cross-connecting part94and sent to each of the interface (INF) parts821-82n. The cross-connecting part94and the pointer parts921-92nare operated by a timing pulse from a pulse generating part96which operates by receiving a clock from a PLL98.

FIG. 9is a time chart showing the operation of the above-mentioned phase adjusting. Each of frames1-n is generated by a timing pulse generated by the pulse generating part84in each of the interface (INF) parts801-80n. The phase of each frame is adjusted according to common part reference timing from the pulse generating part96with the pointer processing in the pointer part921-92n. InFIG. 9, A1is a head byte of a frame and J1is a head byte of a path. As shown inFIG. 9, the phase adjusting process by pointer replacement includes removing the frame which was made in the interface (INF) part from contained paths and accommodating the paths to a new frame.

Recently, as diversification of services is demanded, increased transmission capacity of a transmission device and diversification of a network configuration are demanded. In addition, for the transmission device, further downsizing such as miniaturization and low power consumption is required.

SUMMARY OF THE INVENTION

It is an object of the present invention to realize miniaturization of the transmission system and to improve the efficiency of the transmission device.

The above object of the present invention is achieved by a transmission device which cross connects channels on a synchronous multiplex transmission network which forms a ring, and which performs restoration of communication by looping back signals in a protection path when a failure occurs, the transmission device including:

a memory area which stores information for determining whether an alarm indication signal needs to be inserted in a channel or not, wherein the size of the memory area corresponds to the number of channels targeted for the restoration; and

a part which inserts the alarm indication signal in a channel by switching results of the determination according to predetermined information.

According to the above invention, an unnecessary memory area such as unnecessary registers is eliminated and circuits are eliminated. Therefore, miniaturization of the transmission device can be realized.

The above object of the present invention is achieved also by a transmission device which includes a part for switching and recovering a path by selecting either of two path signals on a synchronous multiplex transmission network which forms a ring, wherein the transmission device switches and recovers a path without skipping an event which arises between polling accesses by a CPU of said transmission device.

According to the above invention, it is unnecessary to increase the number of CPU polling accesses. Therefore, efficiency of CPU processing can be achieved.

The above object of the present invention is achieved also by a transmission device which performs cross connection on a synchronous multiplex transmission network, the transmission device including:

a part, provided in each interface part, which performs phase adjusting of channel signals.

According to the above invention, since a pointer replacement circuit for phase adjusting is unnecessary in a common part, circuit concentration in the common part can be avoided, and miniaturization the transmission device and reduction of power consumption can be realized.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the conventional configuration shown inFIG. 5, the transmission device needs to have VT squelch table registers for all VT channels of the line side, because some of the VT channels which are used for BLSR can be switched to any channel when being cross connected. Therefore, according to the conventional configuration, the transmission device needs to have unnecessary registers even when only some of the channels of the line side are used for BLSR.

Therefore, it is required to configure the transmission device so as to include only necessary VT squelch registers equivalent to the number of the VT channels used for BLSR, that is, so as to include only a necessary memory area for VT channels targeted for restoration.

FIG. 10is a block diagram of an embodiment of the present invention corresponding to the above requirement, which is a first requirement, and shows a part corresponding to the VT SQL21inFIG. 3. In this embodiment, 24 STS channels are used for BLSR in the transmission device.

A squelch table setting part110has registers for 28 VT channels per each of STS channel registers1101-11024where the register value of each VT channel is set from a control part117. The squelch table setting part110has only the capacity for channels targeted for BLSR. “Far End Node ID”, that is, the node ID of the farthest node among connected nodes is sent to each of SQL decision parts1121-11224which determine whether VT squelch should be carried out or not on the basis of comparison between the “Far End Node ID” and the setting data in the squelch table setting part110. The result of the decision is stored in each of the latching parts1141-11424.

The results which are input into a switching (SW), part116in parallel are switched by designating STS numbers from an ACM (address control memory)118which is set on the basis of STS cross-connect information by the control part117. Then, VT squelch is inserted into a corresponding VT channel in an squelch inserting (SQL INS) part119.

FIG. 11shows an example of the configuration of a transmission device120according to another embodiment. The transmission device120shown inFIG. 11includes 192 STS-1 channels of which 48 STS channels are used for BLSR. In this case, if the conventional method is applied, 5376 VT squelch table registers are necessary since a STS-1 channel includes 28 VT channels. On the other hand, according to the present invention, the transmission device120has only 1344 VT squelch table registers, because the number of STS-1 channels for use in BLSR is 48.

In the following, a second requirement will be described. The second requirement is related to recovery from the non-default path to the default path. In the time chart ofFIG. 7, if an alarm in the default path is raised and disappears between polling4and polling5, the WTR timer can not be reset because the operation of the CPU or software can not detect the alarm.

Therefore, the switched path recovers after a predetermined time starting from polling3, although the predetermined time should have started from polling5. This results in decreasing stability of communication. Reducing a polling interval as much as possible can solve this problem, but, it increases the load of the CPU. The second requirement is to solve this problem of skipping an alarm by the CPU without increasing the load of the CPU.

FIG. 12is a block diagram showing an embodiment of the present invention corresponding to the second requirement. The block diagram shown inFIG. 12corresponds to the STS PSW part14, or15, or VT PSW part23inFIG. 3, that is, a part for path protection switching of UPSR. InFIG. 12, each of default path side data146and non-default path side data148is input into a selector (SEL)144, and either of those data is selected by being controlled by a PSW control part142and is output to an output149. A default side ALM detection part130or a non-default side ALM detection part132detects an alarm when an alarm is raised in the default path side data146or the non-default path side data148respectively.

If the ALM detection part130of the default side or the ALM detection part132of the non-default side detects an alarm, the alarm is sent to an ALM notification register134. In addition, the ALM detection part130or the ALM detection part132notifies a PSW control part142of the alarm. If the ALM detection part130of the default side detects an alarm during communication, path switching to the non-default side will be performed by the selector (SEL)144according to the control of the PSW control part142.

A WTR timer information part136retains information of raising and disappearing of an alarm in the default path side. The WTR timer starts when a CPU138reads the information in the WTR timer information part136.

A WTR management part140receives alarm information of the default side from the ALM detection part130directly, and retains management information for keeping a switched path in the non-default side.

FIG. 13is a time chart showing the operation of the above-mentioned configuration. As shown inFIG. 13, the PSW control part142works so as to switch a path to the non-default side when an alarm is raised in the default side between polling1and polling2of the CPU138. When the alarm of the default side extinguishes between polling2and polling3, the WTR timer information part136retains information of the event. When the CPU138recognizes the information in the WTR timer information part136by polling3, the WTR timer starts. As shown inFIG. 13, an alarm in the default path is raised and disappears between polling4and polling5. Although the CPU138can not recognize this event, the event is notified to the WTR timer information part136directly. Then, the WTR timer information part136retains the information, and, when the WTR timer information part136is read by polling5, the WTR timer is reset and the monitoring period starts. After the monitoring period of n minutes have passed from the start of the timer, the PSW control part142works by polling8so as to recover the path to the default side.

FIG. 14is a block diagram showing a schematic hardware configuration corresponding toFIG. 12.FIG. 12shows an example of one channel processing andFIG. 14shows an example in which a plurality of channels are processed serially. Current states of an alarm of the default side and the non-default side (DEF alarm, non-DEF alarm) are input into an automatic switching (SW) control part150. In addition, a previous state of the alarm (ALM(t−1)) and a previous state of the path switch (state(t−1)) are input. A register152retains current information of the path switch and the alarm. The automatic SW control part150compares the current state and the previous state, and outputs a WTR timer start signal154and a path switch state signal156. For example, if an alarm was raised in the default side at the time of t−1 and the alarm has disappeared currently, a signal for starting the WTR timer is output.

In the following, a third requirement will be described. A third requirement relates to phase adjusting of STS channels when cross connection is performed, which was described withFIG. 8andFIG. 9. As shown inFIG. 8, the phase of each channel is adjusted in the common part according to the conventional technique. However, since the capacity of the transmission device is increasing and signal capacity from each interface (INF) part is increasing recently, the size and the number of the circuits of the pointer part are also increasing. Further, since there are some interface signals which do not require pointer replacement, the configuration shown inFIG. 8becomes inefficient. Thus, the third requirement is to avoid concentration of circuits in the common part so as to form an efficient configuration.

FIG. 15is a block diagram showing an embodiment of the present invention which corresponds to the third requirement. InFIG. 15, each signal input into each of interface (INF) parts1601-160nis assembled into an STS frame in the interface (INF) parts1601-160n. At this time, phase adjusting is also performed. Fine phase adjustment of each channel and cross connecting are performed in a common part170, and each channel is output to each of interface (INF) parts1611-161n. A system clock part180generates and distributes a reference clock in the transmission device. Each of the interface INF parts1601-160ngenerates the STS frame according to a reference timing pulse distributed from a pulse generating part176in the common part170, and outputs the STS frame to the common part170.

Since each of the interface (INF) parts1601-160nhas the same configuration as that of the interface (INF) part1601, only the interface (INF) part1601will be described in the following. An STS frame generating part162generates an STS frame according to a timing pulse after clock change which is generated by a synchronous pulse generating part164. The generated frame is multiplexed by a MUX166and sent to the common part170. A 1/n part (divider)169decreases the rate of the clock. A PLL168receives a clock from the system clock180.

Fine phase adjustment is performed on an STS signal sent to the common part170in a memory1721, and the signal is cross connected in a cross connecting part174and sent to the interface INF parts1611-161n. The cross-connecting part174and memories1721-172noperates according to a timing pulse from the pulse generating part176which receives a clock from the PLL178.

FIG. 16is a time chart showing the operation of the above-mentioned phase adjusting. As shown inFIG. 16, an STS frame is generated in each interface (INF) part according to the interface (INF) part reference timing (a) from the synchronous pulse generating part164. Even when the frame is generated by the reference timing, a slight phase shift of the output data from each of the interface (INF) parts may occur (Min. Delay-Max. Delay). Therefore, the phase is finely adjusted by storing the data in the memories1721-172nand reading out the data according to the common part reference timing (b) from the pulse generating part176.

FIG. 17is a block diagram showing in detail the synchronous pulse generating part164inFIG. 5. The synchronous pulse generating part164generates a timing pulse for assembling input data into an STS frame.

InFIG. 17, a write reference part190generates timing for delaying a timing pulse in order to perform clock change and generates reference timing for generating windows. A window1(192) and a window2(194) are dual window generating parts in which a selector (SEL)200switches the window. A timer196manages the monitoring time for switching these windows. A read reference part198generates timing for reading the delayed timing pulse and generates timing for phase monitoring. A comparing part (COMP)202monitors the window and the phase of the read timing. A S/P204carries out serial-parallel conversion and a P/S carries out parallel-serial conversion. A FF206is a flip-flop. InFIG. 17, the lines from TP IN and WRITE CLK correspond to “a” in the interface (INF) part1601FIG. 15, and the line from READ CLK corresponds to “b”, and the line from TP OUT corresponds to “c”.

FIG. 18is a time chart showing the operation of the configuration ofFIG. 17. The clock of the reading side is synchronized by the write reference timing, and a window is generated by the write reference timing. As shown inFIG. 18, during a monitoring period by the timer, since read timing is within the window1(narrower window), the window is switched to the window2(wider window) by the selector (SEL)200after the monitoring period. Thus, serial-parallel converted data is read according to the monitored read timing and is parallel-serial converted. If the comparing part202detects that the read timing is not within the window1, the timer is reset and the monitoring process restarts.

FIG. 19shows a configuration in which lock detection parts210,212and a lock monitoring part214are added to the configuration shown inFIG. 17. The lock detection parts210and212detect a lock state of a PLL circuit and the lock monitoring part214monitors lock detection. InFIG. 19, a PLL216corresponds to the PLL178inFIG. 15and a PLL218corresponds to the PLL168. In this configuration, the window will be switched when the locked state is detected instead of using a timer.

According to the configuration shown inFIG. 17, the two windows are prepared for phase comparison in order to perform stable clock change, and the read timing is monitored by the narrower window during the monitoring period, and, then, if the read timing is normal during the period, the window is switched to the wider one. Therefore, reading data at an unstable position can be avoided because enough margin is allowed. Further, according to the configuration shown inFIG. 19, the window will be switched to the wider one after a lock of a PLL is detected. Therefore, the clock change will be performed more reliably.

As mentioned above, according to the present invention corresponding to the first requirement, the transmission device determines VT channels for inserting therein the alarm indication signal by using the memory area for the squelch table which has only the capacity of the VT channels targeted for BLSR which uses protection channels along a loop back route for restoration of a signal in the case of line failure, and, then, inserts the alarm indication signal into the corresponding channel by using cross-connecting information of main signal data. Therefore, an unnecessary memory area such as unnecessary registers is eliminated such that circuits are eliminated and the miniaturization can be realized.

Further, according to the present invention corresponding to the second requirement, since path monitoring start information is recorded by hardware in the path protection switch, the CPU can start the path monitoring period by only reading the path monitoring start information. And, since the path monitoring state can be generated by the hardware and can be established immediately when the condition for the path monitoring state is satisfied, skipping an event between CPU polling accesses can be avoided. Further, skipping an event between CPU polling accesses can be avoided without increasing CPU load because it is unnecessary to increase the number of CPU polling accesses. Therefore, efficiency of CPU processing can be achieved.

Furthermore, according to the present invention corresponding to the third requirement, since the pointer replacement circuit for phase adjusting is unnecessary in the common part, circuit concentration in the common part can be avoided, and miniaturization of the size of the transmission device and reduction of power consumption can be realized. Further, since the window is switched by using a timer in clock change of distributed reference timing, reading a timing pulse at an unstable position can be avoided. Further, since the lock state of the PLL circuit is monitored and a window is switched to a wider one after PLL locking, reliable clock change will become possible.

Therefore, according to the present invention, miniaturization of the transmission device can be realized and a transmission device of high stability and high reliability can be provided.