Clock driver with duty cycle correction

A clock driver with duty cycle correction includes a first driver circuit, a second driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal and has parameters selected for a first frequency range of the clock input signal. The second driver circuit is nested with the first driver circuit and performs duty cycle correction on the clock input signal with parameters selected for a second frequency range of the clock input signal lower than the first frequency range. The correction logic circuit provides correction signals to a selected one of the first driver circuit and the second driver circuit. The clock driver provides a duty cycle corrected clock signal from the selected one of the first driver circuit and the second driver circuit based on a selected frequency range of the clock input signal.

BACKGROUND

This disclosure relates generally to clock circuits, and more specifically to clock driver circuits with duty cycle correction (DCC). Providing a symmetrical duty cycle clock signal is important for many high-speed interface designs. For example, modern dynamic random-access memories (DRAMs) based on the double data rate (DDR) family of standards promulgated by the Joint Electrical Design Engineering Conference (JEDEC) use high-speed data transmission between a data processor and a DDR memory. Currently supported data rates can require a clock or strobe signal having a frequency as high as a few giga-Hertz (GHz). DDR memories are also typically operated in lower memory power states during periods of low processor activity in which the data transmission frequency is lowered. Moreover, in DDR systems, data is captured on both low-to-high and high-to-low transitions of the data clock or data strobe signal, making it important for the data clock or data strobe signal to achieve a duty cycle very close to 50%. Any significant duty cycle error may close the data eye and prevent reliable data reception.

A traditional method of duty cycle correction is to use an analog negative feedback loop. However analog feedback loops are slow and difficult to stabilize, and require a continuously running clock signal for the loop to track and maintain the output duty cycle, increasing device power consumption. Analog feedback loops also suffer from burst mode and clock random jitter issues. In these systems, analog loops are shut down to save power during periods of inactivity, but can suddenly switch to periods of high activity, which causes power supply transients that affect the duty cycle of the clock signal.

Because of the problems with analog feedback loops, digital duty cycle correction (DCC) loops have been developed. However digital DCC loops can suffer from a least significant bit (LSB) step size problem when used in clock generation circuits that require wide frequency ranges, such as DDR memory systems. For example, if the frequency range-to-step size ratio is tuned for the highest supported frequency, then it may fail to properly correct duty cycle to an acceptable amount of accuracy at the lowest supported frequency, and vice versa. There exists no known solution for digital duty cycle correction circuits that provide the needed accuracy over wide frequency ranges such as those required for DDR memory systems.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well. The following Detailed Description is directed to electrical circuitry, and the description of a block shown in a drawing figure implies the implementation of the described function using suitable electronic circuitry, unless otherwise noted.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A clock driver with duty cycle correction includes a first driver circuit, a second driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal and has parameters selected for a first frequency range of the clock input signal. The second driver circuit is nested with the first driver circuit and performs duty cycle correction on the clock input signal with parameters selected for a second frequency range of the clock input signal lower than the first frequency range. The correction logic circuit provides correction signals to a selected one of the first driver circuit and the second driver circuit. The clock driver provides a duty cycle corrected clock signal from the selected one of the first driver circuit and the second driver circuit based on a selected frequency range of the clock input signal.

A clock driver with duty cycle correction includes a first driver circuit, at least one nested driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal with parameters selected for a first frequency range of the clock input signal. The at least one nested driver circuit is coupled to and nested with a preceding driver circuit, each nested driver circuit performs duty cycle correction on the clock input signal with parameters selected for corresponding additional frequency ranges of the clock input signal. The correction logic circuit provides correction signals to the first driver circuit and the at least one nested driver circuit. The clock driver provides a duty cycle corrected clock signal from a selected one of the first driver circuit and the at least one nested driver circuit based on a frequency range of the clock input signal.

A method includes performing duty cycle correction on a clock input signal using a first driver circuit having parameters selected for a first frequency range of the clock input signal. A second driver circuit is nested with the first driver circuit. Duty cycle correction on the clock input signal is performed using the second driver circuit, wherein the second driver circuit has parameters selected for a second frequency range of the clock input signal, the second frequency range different from the first frequency range. Correction signals are provided to a selected one of the first driver circuit and the second driver circuit. A duty cycle corrected clock signal is provided from an output of the first driver circuit if the clock input signal is in the first frequency range, and from the second driver circuit if the clock input signal is in the second frequency range.

FIG.1illustrates in block diagram form a clock driver circuit100known in the prior art. Clock driver circuit100includes generally a selector block110, an interpolator core120, an input clock select logic circuit130, a multiplexer140labelled “MUX”, a duty cycle correction inverter150, a programmable divider160, an output multiplexer170, and a single-ended to differential converter180labelled “S2D”.

Selector block110includes multiplexers111and112, each labelled “3:1 MUX”. Multiplexer111has inputs for receiving an in-phase clock labelled “iclk”, a complement of the in-phase clock labelled “iclkb”, and a delayed version of the in-phase clock labelled “iclk_dly”, a control input for receiving a select signal labeled “crs0<2:0>”, and an output. Multiplexer112has inputs for receiving a quadrature clock labelled “qclk”, a complement of the quadrature clock labelled “qclkb”, a value representative of a logic low voltage labelled “tielo”, a control input for receiving a select signal labeled “crs1<1:0>”, and an output. Selector block110allows a user to select from among a variety of clock sources to perform various functions. For example, in a radio application, the iclk and qclk signals form in-phase and quadrature signals of a data communication system, in which the clocks are ninety degrees out of phase so as to be able to modulate a signal to be transmitted or demodulate a signal to be received.

Interpolator core120has an in-phase input connected to the output of multiplexer111, a quadrature input connected to the output of multiplexer112, a control input for receiving a set of control bits labelled “fine<7:0>”, and an output.

Input clock select logic circuit130has inputs for receiving signals iclk, qclk, iclkb, and qclkb, a control input for receiving an enable signal labelled “glb_pi_bypass_en”, a control input for receiving a control signal labelled “pi_bypass_sel<1:0>, and an output. Input clock select logic circuit130is enabled when the glb_pi_bypass_en signal is active at a logic high, and is disabled when the glb_pi_bypass_en signal is inactive at a logic low. When active, the two-bit pi_bypass_sel<1:0> signal selects between the four inputs.

Multiplexer140has a first input for receiving a signal labelled “dly_line_clk”, a second input connected to the output of interpolator core120, a third input connected to the output of input clock select logic circuit130, control inputs for receiving signals labelled “glb_piclk_dlyclk_sel” and “glb_pi_bypass_en”, and an output. Multiplexer140selects its first input in response to the inactivation of the glb_pi_bypass_en signal and activation of glb_piclk_dlyclk_sel, its second input in response to the inactivation of the glb_piclk_dlyclk_sel and glb_pi_bypass_en signals, and its third input in response to the inactivation of the glb_piclk_dlyclk_sel signal and the activation of the glb_pi_bypass_en signal.

Duty cycle correction inverter150has an input connected to the output of multiplexer140, a control input for receiving an enable signal labelled “HF_EN”, and a duty cycle correction input for receiving signals labelled “UP<14:0>” and “DN<14:0>”, and an output. A signal generator circuit151associated with duty cycle correction inverter150includes a duty cycle control up/down selection logic circuit152labelled “DCC UP/DN Select Logic”, and a binary-to-thermometer encoder circuit153labelled “BIN2THERM”. Duty cycle control up/down selection logic circuit152has a first input for receiving a signal labelled “dcc_up<3:0>”, a second input for receiving a signal labelled “dcc_dn<3:0>”, a control input for receiving a control signal labelled “dcc_pi_dcc_bypass_en”, and an output. Binary-to-thermal converter153has an input connected to the output of duty cycle control up/down selection logic circuit152, and an output for providing the UP<14:0> and DN<14:0> signals.

Programmable divider160has an input connected to the output of multiplexer140, a control input for receiving a low frequency enable signal labelled “LF_EN”, and an inverting output.

Output multiplexer170has a first input connected to the output of programmable divider160, a second input connected to the output of duty cycle correction inverter150, a control input for receiving a control signal labelled “LF_EN/HF_EN”, and an output. Single-ended to differential converter180has an input connected to the output of output multiplexer170, a first output for providing a positive signal of a differential signal pair labelled “bclk_p”, and a second output for providing a negative signal of the differential signal pair labelled “bclk_n”.

In operation, duty cycle correction inverter150, programmable divider160, and output multiplexer170form a core clock driver circuit that can be used alone or in combination with other circuitry to achieve duty cycle correction. Clock driver circuit100illustrates an example of a conventional clock driver circuit that also provides interpolation and flexible selection between several clock sources. A clock driver duty cycle correction circuit, not shown inFIG.1, measures the actual duty cycle real-time and provides correction signals dcc_up<3:0> and dcc_dn<3:0> to compensate for duty cycle error caused by, for example, an imbalance between the P-channel pullup side and the N-channel pulldown side of duty cycle correction inverter150, power supply droop, temperature change, etc. Signal generator circuit151receives and latches the duty cycle control signals, and binary-to-thermometer encoder circuit153converts the duty cycle control signals to a form suitable for use in duty cycle correction inverter150. When inactive at a logic high state, the glb_pi_dcc_bypass_en signal allows the duty cycle correction to be disabled under certain conditions, such as test modes and for very low frequency operation when data eye closure due to clock duty cycle error is not likely to occur. When active in a logic low state, the glb_pi_dcc_bypass_en signal enables the dcc_up<3:0> and dcc_dn<3:0> signals to be passed to the control input of duty cycle correction inverter150. Binary-to-thermometer encoder circuit153then converts the dcc_up<3:0> and dcc_dn<3:0> signals to thermometer encoded signals, in which the UP<14:0> signals and DN<14:0> signals have ones in positions at or below the respective “thermometer” level, and zeros above the respective thermometer level.

In addition, clock driver circuit100provides some amount of flexibility in clock frequency due to the availability of either a high-frequency path through duty cycle correction inverter150enabled by the HF_EN signal, or a low-frequency path through programmable divider160. Duty cycle correction inverter150provides duty cycle correction in response to the dcc_up<3:0> and dcc_dn<3:0> signals that can be selected based on real-time measurements of the duty cycle, not shown inFIG.1but described below. Programmable divider160does not have explicit duty cycle correction, but inherently achieves duty cycle correction by forming a divided clock cycle based on whole cycles of the input clock signal, and thus is not affected by variations in the high and low times of the input clock signal.

Clock driver circuit100suffers from power consumption issues, because a low frequency output signal is derived using a high frequency input to programmable divider160. It also causes deterministic jitter issues due to the presence of a fundamental high frequency input along with divided output frequencies. On the other hand, clock driver circuit100, without programmable divider160, is also a feasible solution. However, the duty cycle correction range is limited because it suffers from the LSB step size issue. That is, if the LSB step size is optimized for the highest operating frequency, then it offers very limited LSB step size at the lowest operating frequency and vice-versa. A circuit that can be used to provide wideband digital duty cycle correction circuit across a wide operating frequency range will be described below.

FIG.2illustrates in partial block diagram and partial schematic form a duty cycle correction circuit200known in the prior art. Duty cycle correction circuit200includes generally a correction signal generator210and an accumulator220.

Correction signal generator210includes an input clock selection logic circuit211, a reference voltage generator212, a resistor213, and capacitor214, a comparator215, an inverter216, and a multiplexer217. Input clock selection logic circuit211has a first input for receiving an interpolator output labelled “PI Output clkp/n”, a second input for receiving the output of output multiplexer170ofFIG.1labelled “HS 2:1 SERIALIZER OUTPUT”, a selection input for receiving a selection signal labelled “clk_sel<1:0>, and an output. Voltage generation circuit212has an output for receiving a reference voltage, and as shown inFIG.2, and is represented as a resistor divider with tunable resistors connected in series between a power supply voltage terminal and a ground terminal. Resistor213has a first terminal connected to the output of input clock selection logic circuit211, and a second terminal. Capacitor214has a first terminal connected to the second terminal of resistor213, and a second terminal connected to the ground terminal. Comparator215has a negative input connected to the output of reference voltage generator212, a positive input connected to the first terminal of capacitor214, and an output. Inverter216has an input connected to the output of comparator215, and an output. Multiplexer217has a first input labelled “0” connected to the output of comparator215, a second input labelled “1” connected to the output of inverter216, a control input for receiving a signal labelled “dcc_chicken_bit”, and an output for providing a signal labelled “dcc_updn”.

Accumulator220is implemented with a digital finite state machine221that has an input connected to the output of multiplexer217, a clock input for receiving a clock signal labelled “dcc_fsm_loop_clk”, a first output for providing the dcc_up<3:0> signal, and a second output for providing the dcc_down<3:0> signal.

In operation, correction signal generator210forms the dcc_updn signal to indicate whether the duty cycle is measured at less than 50% or greater than 50%. The clk_sel<1:0> signal selects either the “p” or “n” portion of either the first or second input as the clock source. Reference voltage generator212provides an output that represents the midpoint of the power supply voltage measured with respect to ground. As shown inFIG.2, it has the ability to be tuned to provide the midpoint value as a precise voltage. Resistor213and capacitor214form a lowpass filter that provides an average voltage of the selected clock signal on the first terminal of capacitor214. If the average value exceeds the precise midpoint voltage, then the duty cycle of the high state is greater than 50%, whereas if the average value is less than the precise midpoint voltage, then the duty cycle of the high state is less than 50%. Multiplexer217is responsive to either the true output of comparator215if its control input is low, or the complement of the output of comparator215if its control input is high, based on its control input. Thus the dcc_updn signal represents the state of whether the duty cycle is above or below 50%.

Digital finite state machine221operates according to the dcc_fsm_loop_clock to capture the value of the dcc_updn signal. The dcc_fsm_loop_clock operates slower than the clock being switched to provide loop stability. In some embodiments, digital finite state machine221includes a digital noise filter that changes the values of dcc_up<3:0> signal relative to the dcc_dn<3:0> based on recent samples to avoid loop instability based on random fluctuations in the duty cycle. If the clock is precisely at a 50% duty cycle, the number of occurrences of dcc_updn=1 will equal the number of occurrences of dcc_updn=0. After counting a threshold number of occurrence of dcc_updn being in a certain logic state, it either increments or decrements the dcc_up<3:0> signal relative to the dcc_dn<3:0> signal as indicated by the logic state of dcc_updn.

FIG.3illustrates in schematic form a duty cycle correction inverter300that can be used as duty cycle correction inverter150in clock driver circuit100ofFIG.1according to the prior art. Duty cycle correction inverter300includes generally a first stage310and a second stage320, in which first stage310and second stage320are connected in parallel.

First stage310operates as a tunable impedance inverter and includes compound transistors311-314. Compound transistor311is a compound P-channel transistor having fifteen equally sized transistor segments, each having a source connected to the power supply voltage terminal, a gate for receiving an input signal labelled “CLK_IN”, and a drain. Compound transistor312is a compound P-channel transistor having fifteen equally sized transistor segments, each having a source connected to the drain of a corresponding transistor segment in compound transistor311, a gate for receiving a corresponding one of the DN<14:0> signal, and a drain for providing an output signal labelled “CLK_OUT”. Compound transistor313is a compound N-channel transistor having fifteen equally sized transistor segments, each having a drain connected to the drain of a corresponding transistor in compound transistor312, a gate for receiving a corresponding one of the UP<14:0> signals, and a source. Compound transistor314is a compound N-channel transistor having fifteen equally sized transistor segments, each having a drain connected to the source of a corresponding transistor in compound transistor313, a gate for receiving the CLK_IN signal, and a source connected to ground.

Second stage320operates an as constant-impedance inverter and includes transistors321-324. Transistor321is a P-channel transistor having a source connected to the power supply voltage terminal, a gate for receiving the CLK_IN signal, and a drain. Transistor322is a P-channel transistor having a source connected to the drain of transistor321, a gate for an active low enable signal labeled “”, and a drain connected to the drains of each transistor in compound transistor312. Transistor323in an N-channel transistor having a drain connected to the drain of transistor322, a gate for receiving an active high enable signal labelled “EN”, and a. Transistor324is an N-channel transistor having a drain connected to the source of transistor323, a gate for receiving the CLK_IN signal, and a source connected to ground. When used in clock driver circuit100ofFIG.1, the gates of transistors322and323receive a complement of the HF_EN signal and the HF_EN signal, respectively. The drains of all segments of transistors312,313,322, and323are connected together to form the CLK_OUT signal at the output of duty cycle correction inverter300.

Duty cycle correction inverter300allows the duty cycle to be corrected by adjusting the pullup and pulldown impedances in first stage310according to the DN<14:0> and UP<14:0> signals, respectively. Compound transistor311operates as a pullup transistor with segments connected to corresponding segments in compound transistor312in a cascode configuration. Each segment in compound transistor311has the same size as every other segment, and each segment in compound transistor312has the same size as every other segment. Likewise, compound transistor314operates as a pulldown transistor with segments connected to corresponding segments in compound transistor313in a cascode configuration. Each segment in compound transistor314has the same size as every other segment in compound transistor314, and each segment in compound transistor313has the same size as every other segment in compound transistor313. Thus, both the switching transistors and the cascode transistors can be physically matched to each other and provide uniform increases in impedance and rise- and fall-times as more cascode transistors are switched in.

When the CLK_IN signal switches from low to high, the CLK_OUT signal switches from high to low. The rate at which it switches depends on the load impedance and the effective cascode impedance. As more of the thermometer-encoded DN<14:0> signals become active, the pullup impedance decreases, effectively decreasing the high time and the duty cycle. Conversely, when the CLK_IN signal switches from high to low, the CLK_OUT signal switches from low to high. The rate at which it switches depends on the load impedance and the effective cascode impedance. As more of the thermometer-encoded UP<14:0> signals become active, the pulldown impedance increases, effectively decreasing the low time and increasing the duty cycle.

FIG.4illustrates in partial block diagram and partial schematic form a clock driver400with duty cycle correction according to some embodiments. Clock driver400is similar to clock driver circuit100ofFIG.1but does not include programmable divider160. Clock driver400includes a selector block410, an interpolator core420, an input clock select logic circuit430, a multiplexer440labelled “MUX”, and a single-ended to differential converter480corresponding to like numbered elements inFIG.1. There elements were discussed above and will not be described again.

However, clock driver400supports a wider range of operating frequencies than clock driver circuit100ofFIG.1without programmable divider160, and includes a driver circuit450implemented as a duty cycle correction inverter and a driver circuit460nested with driver circuit450.

Driver circuit460includes a tri-state inverter461, a transistor462, an inverter463, a duty cycle correction inverter464, a transistor465, an inverter466and a tri-state inverter467. Tri-state inverter461has an input connected to the output of multiplexer440, a control input for receiving the LF_EN signal, and an output. Transistor462has a drain connected to the output of tri-state inverter461, a gate for receiving the HF_EN signal, and a source connected to the ground terminal. Inverter463has an input connected to the output of tri-state inverter461, and an output. Duty cycle correction inverter464has an input connected to the output of inverter463, a control input for receiving an enable signal labelled “LF_EN”, a duty cycle correction input for receiving the UP<14:0> and DN<14:0> signals, and an output. Transistor465has a drain connected to the output of duty cycle correction inverter464, a gate for receiving the HF_EN signal, and a source connected to the ground terminal. Inverter466has an input connected to the output of duty cycle correction inverter464, and an output. Tri-state Inverter467has an input connected to the output of inverter466, a control input for receiving the LF_EN signal, and an output connected to the output of driver circuit450.

In operation, clock driver400is a wideband clock driver that provides better correction over wider frequency ranges by providing two driver circuits with duty cycle correction tailored for different frequency ranges in parallel. Driver circuit450is active in response to the HF_EN signal and is active to provide duty cycle compensation for a first frequency range. Driver circuit460is active in response to the LF_EN signal and is active to provide duty cycle compensation for a second frequency range lower than the first frequency range.

Driver circuit460includes a tri-state inverter461and an inverter463on the input side of duty cycle correction inverter464to prevent adding loading to the node at the input of driver circuit450. When LF_EN is low, driver circuit460is deselected, duty cycle correction inverter464and tri-state inverters461and467are all deselected. To prevent the input of inverter463from floating, transistor462receives the HF_EN signal and is activated to force the input of inverter463to a logic low state. Likewise, to prevent the input of inverter466from floating, transistor465receives the HF_EN signal and is activated to force the input of inverter466to a logic low state.

When LF_EN is high, HF_EN is low, and driver circuit450is inactive. Tri-state inverters461and467, inverters463and466are active, and duty cycle correction inverter464is also active. Transistors462and465are non-conductive. The output of single-ended to differential converter480is provided from the low frequency path.

Driver circuit460is nested with driver circuit450as follows. It has an input and an output connected to the input and the output of driver circuit450. However, it includes isolation to prevent loading the input terminal and contention on the output terminal of driver circuit450when driver circuit450is active. In this example, the isolation includes tri-state inverters461and467, inverters463and466, and transistors462and465. As will now be shown, the nesting can be extended to an arbitrary number of layers to support better wideband duty cycle correction.

FIG.5illustrates in partial block diagram and partial schematic form another clock driver500with duty cycle correction according to some embodiments. Clock driver500is a wideband clock driver similar to clock driver circuit100ofFIG.1but it supports an even wider range of operating frequencies than clock driver circuit100ofFIG.1without a programmable divider by nesting a third driver circuit570with a second driver circuit560and the first driver circuit550. Clock driver500is constructed the same as clock driver400, except it uses a combination of a first driver circuit550, a second driver circuit560, and a third driver circuit570.

Duty cycle correction inverter550has an input connected to the output of multiplexer440, an output, a control input for receiving the HF_EN signal, and a duty cycle correction input for receiving signals for controlling P- and N-channel transistors DN<14:0> and “UP<14:0>”, respectively. A signal generator circuit551associated with driver circuit550includes a duty cycle control up/down selection logic circuit552and a binary-to-thermometer encoder circuit553. Duty cycle control up/down selection logic circuit552has a first input for receiving the dcc_up<3:0> signal, a second input for receiving the dcc_dn<3:0> signal, a control input for receiving the dcc_pi_dcc_bypass_en signal, and an output. Binary-to-thermal converter553has an input connected to the output of duty cycle control up/down selection logic circuit552, and an output for providing the UP<14:0> and DN<14:0> signals.

Driver circuit560includes a tri-state inverter561, a transistor562, an inverter563, a duty cycle correction inverter564, a transistor565, an inverter566, and a tri-state inverter567. Tri-state inverter561has an input connected to the output of multiplexer440, a control input for receiving an enable signal labelled “MF_EN/LF_EN”, and an output. Transistor562has a drain connected to the output of tri-state inverter561, a gate for receiving the HF_EN signal, and a source connected to the ground terminal. Inverter563has an input connected to the output of tri-state inverter561, and an output. Duty cycle correction inverter564has an input connected to the output of inverter563, a control input for receiving an enable signal labelled “MF_EN”, a duty cycle correction input for receiving the UP<14:0> and DN<14:0> signals, and an output. Transistor565has a drain connected to the output of duty cycle correction inverter564, a gate for receiving the HF_EN signal, and a source connected to the ground terminal. Inverter566has an input connected to the output of duty cycle correction inverter564, and an output. Tri-state Inverter567has an input connected to the output of inverter566, a control input for receiving an enable signal labelled “MF_EN+LF_EN”, and an output connected to the output of driver circuit550.

Driver circuit570includes a tri-state inverter571, a transistor572, an inverter573, a duty cycle correction inverter574, a transistor575, an inverter576, and a tri-state inverter577. Tri-state Inverter571has an input connected to the output of inverter563, a control input for receiving the LF_EN signal, and an output. Transistor572has a drain connected to the output of tri-state inverter571, a gate for receiving an enable signal labelled “HF_EN+MF_EN”, and a source connected to the ground terminal. Inverter573has an input connected to the output of tri-state inverter571, and an output. Duty cycle correction inverter574has an input connected to the output of inverter573, a control input for receiving the LF_EN signal, a duty cycle correction input for receiving the UP<14:0> and DN<14:0> signals, and an output. Transistor575has a drain connected to the output of duty cycle correction inverter574, a gate for receiving the HF_EN+MF_EN signal, and a source connected to the ground terminal. Inverter576has an input connected to the output of duty cycle correction inverter574, and an output. Tri-state inverter577has an input connected to the output of inverter576, a control input for receiving the LF_EN signal, and an output connected to the output of duty cycle correction inverter564.

By including three levels of driver circuits with three different frequency ranges, clock driver500avoids the LSB step size problem over even greater ranges of clock frequency. Clock drivers400and500illustrate the pattern that can be used to extend the number of frequency ranges.

FIG.6illustrates a flow chart of a process600of performing duty cycle correction on a clock input signal according to some embodiments. Process600starts in an action box610. An action box620includes performing duty cycle correction on a clock input signal using a first driver circuit (e.g., driver circuit550) having parameters selected for a first frequency range of the clock input signal. An action box630includes nesting a second driver circuit (e.g., driver circuit560) with the first driver circuit (e.g., driver circuit550). An action box640includes performing duty cycle correction on the clock input signal using the second driver circuit (e.g., driver circuit560), wherein the second driver circuit (e.g., driver circuit560) has parameters selected for a second frequency range of the clock input signal, the second frequency range different from the first frequency range. An action box650includes providing correction signals to a selected one of the first driver circuit (e.g., driver circuit550) and the second driver circuit (e.g., driver circuit560). An action box660includes providing a duty cycle corrected clock signal from an output of the first driver circuit (e.g., driver circuit550) if the clock input signal is in the first frequency range and from the second driver circuit (e.g., driver circuit560) if the clock input signal is in the second frequency range. Process600ends in an action box670.

Thus, a wideband clock driver solves the LSB step size problem by including nested clock driver circuits to operate in different frequency ranges. The wideband clock driver provides various benefits and advantages compared to the conventional clock driver with duty cycle correction. First, it corrects duty cycle errors over a wide frequency range. Second, it is area efficient. Third, it provides significant performance and power benefits. Fourth, it allows the extension of protection against the LSB problem to and arbitrarily wide frequency range. Fifth, any nested stage provides minimal loading on the clock input signal. Sixth, it provides tunable range coverage and step size based on system requirements.

While particular embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. The duty cycle corrected clock driver circuit can be advantageously integrated with other circuits, such as an interpolator, to provide a desirable combination of functions. While the exemplary embodiment was a DDR memory interface, the duty cycle correction logic can be used in a variety of other applications in which clock drivers are used or needed. The number of nested duty cycle correction circuits can also be varied in different embodiments, because the architecture supports an arbitrary number of nested clock driver circuits operating in different frequency bands.

Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.