BRIDGING-RESISTANT MICROBUMP STRUCTURES AND METHODS OF FORMING THE SAME

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

BACKGROUND

Microbump structures may be used to provide electrical connection between a semiconductor die and an interconnection structure such as an interposer. Solder materials used to provide electrical connection between mating pairs of microbump structures are susceptible to bridging, in which neighboring pairs of solder material portions merge due to vibrations during a bonding process. As the solder material portions merge, unintended electrical connections are formed (i.e., electrical short circuits). Such bridging of solder material portions needs to be avoided to increase the bonding yield.

DETAILED DESCRIPTION

The present disclosure is directed to semiconductor devices, and particularly to semiconductor devices including bridging-resistant microbump structures. The bridging-resistant microbump structures may comprise embedded pad structures within openings in a dielectric material layer, and may be used for advanced packaging structures using fine pitch interconnects.

A dense fine pitch solder material array is generally prone to a bump shift and bridging problem, in which solder material portions are unintentionally attached to two or more bump pillars due to lateral movements, for example, due to vibrations. The bump shift and bridging problem causes unintended electrical connections between neighboring pairs of bump structures (i.e., electrical short circuit). The bridging-resistant microbump structures of the present disclosure remove, or mitigate against the bump shift bridging problem in fine pitch bump structures. The bridging-resistant microbump structures use a configuration in which a bottom lateral dimension of a bump structure is greater than a top lateral dimension of the bump structure, which may be used to restrict the range of bump shift and to avoid bump bridging. In some embodiment, a nickel-containing portion within a bridging-resistant microbump structure may be used to suppress tin diffusion, and to enhance the reliability of bonding. The bridging-resistant microbump structures of the present disclosure may be used to reduce the pitch of a microbump array, and to provide a high-density solder material array for advanced packaging structures. The bridging-resistant microbump structures of the present disclosure may be used for system-on-chip (SoC) dies and/or other high-density integrated devices, organic interposers, silicon interposers, and/or packaging substrates. The bridging-resistant microbump structures of the present disclosure may use a layer stack including a nickel-containing portion and a high-electrical-conductivity material portion including Cu, Ag, or Au.

Referring toFIGS.1A and1B, an intermediate structure according to an embodiment of the present disclosure may include a first carrier substrate310and interposers900formed on a front side surface of the first carrier substrate310. The first carrier substrate310may include an optically transparent substrate such as a glass substrate or a sapphire substrate. The diameter of the first carrier substrate310may be in a range from 150 mm to 290 mm, although lesser and greater diameters may be used. In addition, the thickness of the first carrier substrate310may be in a range from 500 microns to 2,000 microns, although lesser and greater thicknesses may also be used. Alternatively, the first carrier substrate310may be provided in a rectangular panel format. The dimensions of the first carrier in such alternative embodiments may be substantially the same.

A first adhesive layer311may be applied to the front-side surface of the first carrier substrate310. In one embodiment, the first adhesive layer311may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer may convert ultraviolet light to heat, which may cause the material of the LTHC layer to lose adhesion. Alternatively, the first adhesive layer311may include a thermally decomposing adhesive material. For example, the first adhesive layer311may include an acrylic pressure-sensitive adhesive that decomposes at an elevated temperature. The debonding temperature of the thermally decomposing adhesive material may be in a range from 150 degrees to 200 degrees Celsius.

Interposers900may be formed over the first adhesive layer311. Specifically, an interposer900may be formed within each unit area UA, which is the area of a repetition unit that may be repeated in a two-dimensional array over the first carrier substrate310. Each interposer900includes a respective portion of a redistribution structure920, which is a combination of redistribution dielectric layers922and redistribution wiring interconnects924. The redistribution dielectric layers922are dielectric materials embedding the redistribution wiring interconnects924. The redistribution dielectric layers922may be referred to as first dielectric layers or second dielectric layers. The redistribution dielectric layers922include a respective dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric polymer materials may be within the contemplated scope of disclosure. Each redistribution dielectric layer922may be formed by spin coating and drying of the respective dielectric polymer material. The thickness of each redistribution dielectric layer922may be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns. Each redistribution dielectric layer922may be patterned, for example, by applying and patterning a respective photoresist layer thereabove, and by transferring the pattern in the photoresist layer into the redistribution dielectric layer922using an etch process such as an anisotropic etch process. The photoresist layer may be subsequently removed, for example, by ashing.

The redistribution wiring interconnects924are metallic connection structures, i.e., metallic structures that provide electrical connection. The redistribution wiring interconnects924may be referred to as first metallic connection structures or second metallic connection structures in the claims of the instant application. Each of the redistribution wiring interconnects924may be formed by depositing a metallic seed layer by sputtering, by applying and patterning a photoresist layer over the metallic seed layer to form a pattern of openings through the photoresist layer, by electroplating a metallic fill material (such as copper, nickel, or a stack of copper and nickel), by removing the photoresist layer (for example, by ashing), and by etching portions of the metallic seed layer located between the electroplated metallic fill material portions. The metallic seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have thickness in a range from 50 nm to 500 nm, and the copper seed layer may have a thickness in a range from 50 nm to 500 nm. The metallic fill material for the redistribution wiring interconnects924may include copper, nickel, or copper and nickel. Other suitable metallic fill materials are within the contemplated scope of disclosure. The thickness of the metallic fill material that is deposited for each redistribution wiring interconnect924may be in a range from 2 microns to 40 microns, such as from 4 microns to 10 microns, although lesser or greater thicknesses may also be used. The total number of levels of wiring in each interposer900(i.e., the levels of the redistribution wiring interconnects924) may be in a range from 1 to 10. A periodic two-dimensional array (such as a rectangular array) of interposers900may be formed over the first carrier substrate310. Each interposer900may be formed within a unit area UA. The layer including all interposers900is herein referred to as an interposer layer. The interposer layer may include a two-dimensional array of interposers900. In one embodiment, the two-dimensional array of interposers900may be a rectangular periodic two-dimensional array of interposers900having a first periodicity along a first horizontal direction hd1and having a second periodicity along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1.

Referring toFIGS.2A and2B, at least one array of interposer-side bump structures938may be formed on the front surface of each interposer900, i.e., with a portion of the redistribution structure920located within a respective unit area UA. A single array of interposer-side bump structures938, or a plurality of arrays of interposer-side bump structures938, may be formed on each interposer900. In one embodiment, each array of interposer-side bump structures938may be formed as a respective periodic array such as a rectangular array.

According to an embodiment of the present disclosure, each interposer900may function as a first structure, the redistribution wiring interconnects924within each interposer900may function as first metallic connection structures, and portions of the redistribution dielectric layer922within each interposer900may function as first dielectric layers. In this embodiment, the interposer-side bump structures938may function as first metallic bump structures. According to an aspect of the present disclosure, the first metallic bump structures may be formed as bridging-resistant bump structures.FIGS.3A-3Hillustrate a region of the structure in which a first metallic bump structure20is formed as an interposer-side bump structure938according to an embodiment of the present disclosure.

Referring toFIG.3A, a region of the structure is shown after the processing steps ofFIGS.1A and1B. A subset of the redistribution wiring interconnects924that is located at the topmost level of the redistribution wiring interconnects924may be arranged in a configuration of an array of metal pads that are located at positions at which the interposer-side bump structures938are to be subsequently formed. The redistribution wiring interconnects924function as first metallic connection structures120. A redistribution dielectric layer922laterally surrounding the topmost redistribution wiring interconnects924is herein referred to as a topmost interconnect-level redistribution dielectric layer9227, which is a redistribution dielectric layer that is located at the topmost interconnect level within the redistribution structure920. The topmost interconnect-level redistribution dielectric layer9227may cover peripheral portions of each topmost redistribution wiring interconnect924. Thus, an opening19in the topmost interconnect-level redistribution dielectric layer9227may be present over each of the topmost redistribution wiring interconnects924. The lateral dimensions (such as a diameter of a circular opening or a side of a rectangular opening) may be in a range from 5 microns to 100 microns, such as from 10 microns to 50 microns, although lesser and greater lateral dimensions may also be used.

Referring toFIG.3B, a first metallic seed layer21may be deposited over the physically exposed surfaces of the topmost interconnect-level redistribution dielectric layer9227and the topmost redistribution wiring interconnects924. The first metallic seed layer21may include a metallic material that provides subsequent electroplating of another metallic material. The first metallic seed layer21may include, for example, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, or tungsten nitride. Other suitable metallic seed layer materials may be within the contemplated scope of disclosure. The first metallic seed layer21may be deposited by a first physical vapor deposition process. The thickness of a horizontally-extending portion of the first metallic seed layer21may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used.

Referring toFIG.3C, a first photoresist layer43may be applied over the first metallic seed layer21, and may be lithographically patterned to form an array of openings therein. Each opening in the first photoresist layer43may be located over a respective one of the topmost redistribution wiring interconnects924. In one embodiment, the lateral dimension of each opening in the photoresist layer43may be greater than the lateral dimension of a respective underlying topmost redistribution wiring interconnect924(which is a first metallic connection structure120). In one embodiment, each opening in the photoresist layer43may have a respective periphery that is laterally offset outward from a periphery of an underlying opening19in the topmost interconnect-level redistribution dielectric layer9227(which is one of first dielectric layers).

A nickel electroplating process may be performed to electroplate nickel on physically exposed surfaces of the first metallic seed layer21. A nickel plate portion24may be formed within each opening in the photoresist layer43. The thickness of the nickel plate portion24may be in a range from 200 nm to 5 microns, such as from 500 nm to 2 microns, although lesser and greater thicknesses may also be used.

Referring toFIG.3D, the first photoresist layer43may be removed, for example, by ashing. An etch process may be performed to remove unmasked portions of the first metallic seed layer21(i.e., portions of the first metallic seed layer21that are not covered by the nickel plate portions24). The etch process may comprise an isotropic etch process (such as a wet etch process) or an anisotropic etch process (such as a reactive ion etch process). The first metallic seed layer21is divided into a plurality of discrete first metallic seed layers21that underlie as respective nickel plate portion24. Each contiguous combination of a first metallic seed layer21and a nickel plate portion24forms a base portion of a first metallic bump structure, and is herein referred to as a base bump plate (21,24). Each base bump plate (21,24) may be formed on a top surface of a respective one of the first metallic connection structures120.

Referring toFIG.3E, a passivation dielectric layer9228may be formed over the nickel plate portions24. The passivation dielectric layer9228is formed at a bump level that overlies interconnect levels of the redistribution structures922. The passivation dielectric layer9228is a topmost one of the redistribution dielectric layers922, and may be formed directly on the topmost interconnect-level redistribution dielectric layer9227. The passivation dielectric layer9228may include a passivation dielectric material such as polyimide, silicon nitride, silicon carbide nitride, or any other passivation dielectric material known in the art. The thickness of the passivation dielectric layer9228may be in a range from 2 microns to 50 microns, such as from 4 microns to 30 microns, although lesser and greater thicknesses may also be used.

The passivation dielectric layer9228may be subsequently patterned to form openings over each nickel plate portion24. For example, a photoresist layer (not shown) may be applied over the passivation dielectric layer9228, and may be lithographically patterned to form openings over the nickel plate portions24. In one embodiment, each opening in the photoresist layer may overlie a respective nickel plate portion24, and may have a periphery that is laterally offset inward from the periphery of the respective nickel plate portion24is a plan view (such as a top-down view). An etch process (such as an anisotropic etch process) may be performed to etch portions of the passivation dielectric layer9228that are not masked by the photoresist layer. A top surface of the underlying nickel plate portion24may be physically exposed at the bottom of each opening through the passivation dielectric layer9228. The photoresist layer may be subsequently removed, for example, by ashing. In an alternative embodiment, the passivation dielectric layer9228may comprise a photosensitive passivation dielectric material such as photosensitive polyimide. In this embodiment, the passivation dielectric layer9228may be patterned by direct lithographic exposure and development.

Referring toFIG.3F, a second metallic seed layer25may be deposited over the physically exposed surfaces of the passivation dielectric layer9228and the base bump plates (21,24). The second metallic seed layer25includes a metallic material that provides subsequent electroplating of another metallic material. The second metallic seed layer25may include, for example, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, or tungsten nitride. Other suitable metallic seed layer materials may be within the contemplated scope of disclosure. The second metallic seed layer25may be deposited by a second physical vapor deposition process. The thickness of a horizontally-extending portion of the second metallic seed layer25may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used.

Referring toFIG.3G, a second photoresist layer47may be applied over the second metallic seed layer25, and may be lithographically patterned to form an array of openings therein. Each opening in the second photoresist layer47may be located over a respective one of the base bump plates (21,24). In one embodiment, the lateral dimension of each opening in the photoresist layer47may be greater than the lateral dimension of a respective underlying opening in the passivation dielectric layer9228, and may be laterally offset outward from a periphery of the respective underlying opening in the passivation dielectric layer9228.

A copper electroplating process may be performed to electroplate copper on physically exposed surfaces of the second metallic seed layer25. A copper plate portion26may be formed within each opening in the photoresist layer47. The thickness of the copper plate portion26may be in a range from 500 nm to 20 microns, such as from 1 micron to 10 microns, and/or from 1.5 microns to 5 microns, although lesser and greater thicknesses may also be used. Generally, the thickness of the copper plate portion26may be selected such that the lateral dimension of an unfilled cavity (such as a diameter of a circular cylindrical unfilled cavity or a side of a rectangular cylindrical unfilled cavity) is greater than a maximum lateral dimension of a second metallic bump structure to be provided on a semiconductor die that is to be attached to an interposer900. For example, the lateral dimension of an unfilled cavity that is laterally surrounded by a copper plate portion26may be in a range from 5 microns to 80 microns, such as from 10 microns to 40 microns, although lesser and greater lateral dimensions for the unfilled cavities may also be used.

Referring toFIG.3H, the second photoresist layer47may be removed, for example, by ashing. An etch process may be performed to remove unmasked portions of the second metallic seed layer25(i.e., portions of the second metallic seed layer25that are not covered by the copper plate portions26). The etch process may comprise an isotropic etch process (such as a wet etch process) or an anisotropic etch process (such as a reactive ion etch process). The second metallic seed layer25is divided into a plurality of discrete second metallic seed layers25that underlie as respective copper plate portion26. Each contiguous combination of a second metallic seed layer25and a copper plate portion26forms a contoured portion of a second metallic bump structure, and is herein referred to as a contoured bump plate (25,26). Each contoured bump plate (25,26) may be formed on a top surface of a respective one of the base bump plates (21,24). Each contiguous combination of a base bump plate (21,24) and a contoured bump plate (25,26) constitutes a first metallic bump structure20, which may be an interposer-side bump structure928shown inFIGS.2A and2B.

Generally speaking, a first structure (such as an interposer900) including first metallic connection structures120(such as redistribution wiring interconnects924) surrounded by first dielectric layers (such as redistribution dielectric layers922) may be provided. Base bump plates (21,24) may be formed on a top surface of a respective one of the first metallic connection structures120. A passivation dielectric layer9228including an array of openings therein may be formed over the base bump plates (21,24). The passivation dielectric layer9228may be incorporated into the first dielectric layers as a topmost first dielectric layer. Top surfaces of the base bump plates (21,24) are physically exposed within the array of openings in the passivation dielectric layer9228. Contoured bump plates (25,26) may be formed on the base bump plates (21,24) within, and over, the openings in the passivation dielectric layer9228. Each of the contoured bump plates (25,26) comprises a horizontally-extending bottom portion that is formed on a respective one of the base bump plates (21,24), and a tapered or vertically-extending portion contacting a tapered or vertical sidewall of a respective opening selected from the array of openings in the passivation dielectric layer9228, and an annular horizontal portion having an inner periphery that is adjoined to a top periphery of an outer sidewall of the tapered or vertically-extending portion and overlying a top surface of the passivation dielectric layer9228.

An array of first metallic bump structures20may be formed on each interposer900. Each first metallic bump structure20within the array of first metallic bump structures20comprises a respective one of the base bump plates (21,24) and comprises a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane HP1including a distal horizontal surface of the passivation dielectric layer9228and located within a respective opening selected from the array of openings in the passivation dielectric layer9228. In one embodiment, the first horizontal bonding surface segments comprise horizontal surface segments of the horizontally-extending bottom portions of the contoured bump plates (25,26).

Generally, the first metallic bump structures20may be formed in various configurations.FIGS.4A-4Dare vertical cross-sectional views of first alternative configurations for a first metallic bump structure20according to an embodiment of the present disclosure.

Referring toFIG.4A, an alternative configuration of the first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.3Hby electroplating a stack of a first copper plate portion22and a nickel plate portion24in lieu of a nickel plate portion24at a processing step that corresponds to the processing step ofFIG.3C. The thickness of the first copper plate portion22may be in a range from 200 nm to 3 microns, such as from 500 nm to 1 micron, although lesser and greater thicknesses may also be used. The thickness of the nickel plate portion24inFIG.4Amay be in a range from 200 nm to 3 microns, such as from 500 nm to 1 micron, although lesser and greater thicknesses may also be used. Each base bump plates (21,22,24) comprises a first metallic seed layer21, a first copper plate portion22, and a nickel plate portion24.

Further, an electrically-conductive-material plate portion126may be formed in lieu of a copper plate portion26at a processing step that corresponds to the processing step ofFIG.3G. The electrically-conductive-material plate portion126may comprise a highly electrically conductive material such as gold, silver, or copper. The thickness of the electrically-conductive-material plate portion126may be in a range from 500 nm to 20 microns, such as from 1 micron to 10 microns, and/or from 1.5 microns to 5 microns, although lesser and greater thicknesses may also be used. Generally, the thickness of the electrically-conductive-material plate portion126may be selected such that the lateral dimension of an unfilled cavity (such as a diameter of a circular cylindrical unfilled cavity or a side of a rectangular cylindrical unfilled cavity) is greater than a maximum lateral dimension of a second metallic bump structure to be provided on a semiconductor die that is to be attached to an interposer900. For example, the lateral dimension of an unfilled cavity that is laterally surrounded by a tapered or vertically-extending portion of the electrically-conductive-material plate portion126may be in a range from 5 microns to 80 microns, such as from 10 microns to 40 microns, although lesser and greater lateral dimensions for the unfilled cavities may also be used. Each contoured bump plate (25,126) comprises a combination of a second metallic seed layer25and an electrically-conductive-material plate portion126.

Referring toFIG.4B, an alternative configuration of the first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.4Aby electroplating a stack of a nickel plate portion24and an electrically-conductive-material plate portion122and in lieu of a nickel plate portion24at a processing step that corresponds to the processing step ofFIG.3C. The thickness of the nickel plate portion24inFIG.4Amay be in a range from 200 nm to 3 microns, such as from 500 nm to 1 micron, although lesser and greater thicknesses may also be used. The thickness of the electrically-conductive-material plate portion122may be in a range from 200 nm to 3 microns, such as from 500 nm to 1 micron, although lesser and greater thicknesses may also be used. Each base bump plates (21,24,122) comprises a first metallic seed layer21, a nickel plate portion24, and an electrically-conductive-material plate portion122.

Referring toFIG.4C, an alternative configuration of the first metallic bump structure20may be the same as the base bump plate (21,24) illustrated inFIG.3E. In this embodiment, the first metallic bump structure20may consist of a base bump structure (21,24). Each first metallic bump structure20within the array of first metallic bump structures20consists of a respective one of the base bump plates (21,24), and comprises a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane HP1including a distal horizontal surface of the passivation dielectric layer9228and located within a respective opening selected from the array of openings in the passivation dielectric layer9228. In one embodiment, the first horizontal bonding surface segments comprise horizontal surface segments of the top surface of the base bump plate (21,24). In one embodiment, the lateral dimension of an opening in the passivation dielectric layer9228may be in a range from 5 microns to 80 microns, such as from 10 microns to 40 microns, although lesser and greater lateral dimensions for the openings may also be used.

Referring toFIG.4D, an alternative configuration of the first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.4Bby omitting formation of a contoured bump plate (25,126). Each first metallic bump structure20within the array of first metallic bump structures20consists of a respective one of the base bump plates (21,24,122), and comprises a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane HP1including a distal horizontal surface of the passivation dielectric layer9228and located within a respective opening selected from the array of openings in the passivation dielectric layer9228. In one embodiment, the first horizontal bonding surface segments comprise horizontal surface segments of the top surface of the base bump plate (21,24,122). In one embodiment, the lateral dimension of an opening in the passivation dielectric layer9228may be in a range from 5 microns to 80 microns, such as from 10 microns to 40 microns, although lesser and greater lateral dimensions for the openings may also be used.

FIGS.5A-5Eare vertical cross-sectional views of second alternative configurations for a first metallic bump structure20according to an embodiment of the present disclosure.

Referring toFIG.5A, an alternative configuration for a first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.3Hby forming tapered openings through the passivation dielectric layer9228in lieu of openings having vertical sidewalls. The taper angle of the tapered openings, as measured between a vertical direction and a tapered surface of the tapered openings, may be in a range from 0.1 degree to 45 degrees, such as from 1 degree to 30 degrees and/or from 5 degrees to 20 degrees, although lesser and greater taper angles may also be used.

Referring toFIG.5B, an alternative configuration for a first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.4Aby forming tapered openings through the passivation dielectric layer9228in lieu of openings having vertical sidewalls in the same manner as described with reference toFIG.5A.

Referring toFIG.5C, an alternative configuration for a first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.4Bby forming tapered openings through the passivation dielectric layer9228in lieu of openings having vertical sidewalls in the same manner as described with reference toFIG.5A.

Referring toFIG.5D, an alternative configuration for a first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.4Cby forming tapered openings through the passivation dielectric layer9228in lieu of openings having vertical sidewalls in the same manner as described with reference toFIG.5A.

Referring toFIG.5E, an alternative configuration for a first metallic bump structure20may be derived from the first metallic bump structure20illustrated inFIG.4Dby forming tapered openings through the passivation dielectric layer9228in lieu of openings having vertical sidewalls in the same manner as described with reference toFIG.5A.

Referring toFIGS.6A and6B, a set of at least one semiconductor die (701,703) may be bonded to each redistribution structure920. In one embodiment, the redistribution structures920may be arranged as a two-dimensional periodic array, and multiple sets of at least one semiconductor die (701,703) may be bonded to the redistribution structures920as a two-dimensional periodic rectangular array of sets of the at least one semiconductor die (701,703). Each set of at least one semiconductor die (701,703) includes at least one semiconductor die. Each set of at least one semiconductor die (701,703) may include any set of at least one semiconductor die known in the art. In one embodiment, each set of at least one semiconductor die (701,703) may comprise a plurality of semiconductor dies (701,703). For example, each set of at least one semiconductor die (701,703) may include at least one system-on-chip (SoC) die701and/or at least one memory die703. Each SoC die701may comprise an application processor die, a central processing unit die, or a graphic processing unit die.

In one embodiment, the at least one memory die703may comprise a high bandwidth memory (HBM) die that includes a vertical stack of static random access memory dies. In one embodiment, the at least one semiconductor die (701,703) may include at least one system-on-chip (SoC) die and a high bandwidth memory (HBM) die including a vertical stack of static random access memory (SRAM) dies that are interconnected to one another through microbumps and are laterally surrounded by an epoxy molding material enclosure frame.

Each semiconductor die (701,703) may comprise a respective array of die-side bump structures780. Each of the semiconductor dies (701,703) may be positioned in a face-down position such that die-side bump structures780face the first solder material portions940. Each set of at least one semiconductor die (701,703) may be placed within a respective unit area UA. Placement of the semiconductor dies (701,703) may be performed using a pick and place apparatus such that each of the die-side bump structures780may be placed on a top surface of a respective one of the first solder material portions940.

Generally, a redistribution structure920including interposer-side bump structures938thereupon may be provided, and at least one semiconductor die (701,703) including a respective set of die-side bump structures780may be provided. The at least one semiconductor die (701,703) may be bonded to the redistribution structure920using first solder material portions940that are bonded to a respective interposer-side bump structure938and to a respective one of the die-side bump structures780.

Each set of at least one semiconductor die (701,703) may be attached to a respective redistribution structure920through a respective set of first solder material portions940. Each of the at least one cushioning film within a unit area UA may be located outside an area including the at least one semiconductor die (701,703) in the unit area UA in a plan view. The plan view is a view along a vertical direction, which is the direction that is perpendicular to the planar top surface of the redistribution structure layer.

Referring toFIG.6C, a high bandwidth memory (HBM) die810is illustrated, which may be used as a memory die703within the structures ofFIGS.6A and6B. The HBM die810may include a vertical stack of static random access memory dies (811,812,813,814,815) that are interconnected to one another through microbumps820and are laterally surrounded by an epoxy molding material enclosure frame816. The gaps between vertically neighboring pairs of the random access memory dies (811,812,813,814,815) may be filled with a HBM underfill material portions822that laterally surrounds a respective set of microbumps820. The HBM die810may comprise an array of die-side bump structures780configured to be bonded to a subset of an array of interposer-side bump structures938within a unit area UA. The HBM die810may, or may not, be configured to provide a high bandwidth as defined under JEDEC standards, i.e., standards defined by The JEDEC Solid State Technology Association.

FIGS.7A and7Bare sequential vertical cross-sectional views of a region of the structure ofFIGS.6A and6Bin which a first metallic bump structure20(comprising an interposer-side bump structure938) is bonded to a second metallic bump structure30(comprising a die-side bump structure780) according to an embodiment of the present disclosure.

Referring toFIG.7A, a region of the structure ofFIGS.6A and6Bis shown prior to bonding a semiconductor die (701or703) to an interposer900. The semiconductor die (701,703) functions as a second structure including second connection structures130surrounded by second dielectric layers722. The second connection structures130may be metal interconnect structures730of the semiconductor die (701or703). The second dielectric layers722may comprise the dielectric material layers of the semiconductor die (701or703) that embeds the metal interconnect structures730. A most distal dielectric layer selected from the second dielectric layers722may be a passivation dielectric layers.

The second metallic bump structure30(comprising the die-side bump structures780) may be formed by physically exposing top surfaces of a topmost subset of the second connection structures130(for example, by forming openings through a topmost layer selected from the second dielectric layers722), by depositing a metallic seed layer31, by forming a patterned photoresist layer having openings in areas of the topmost subset of the second connection structures130, and by sequentially electroplating metallic material portions (32,34,36) in each opening in the photoresist layer. In an illustrative example, each contiguous set of the metallic material portions (32,34,36) that is formed within a respective opening in the photoresist layer may comprise a first copper plate portion32, a nickel plate portion34, and a second copper plate portion36. The photoresist layer may be subsequently removed, for example, by ashing. Unmasked portions of the metallic seed layer31may be etched by performing an anisotropic etch process or an isotropic etch process. Each patterned portion of the metallic seed layer31may be located underneath a respective contiguous set of metallic material portions (32,34,36). Each contiguous set of a metallic seed layer31and metallic material portions (32,34,36) constitutes a second metallic bump structure30. In the illustrative example, a second metallic bump structure30may comprise a vertical stack of a metallic seed layer31, a first copper plate portion32, a nickel plate portion34, and a second copper plate portion36.

In an illustrative example, the metallic seed layer31may have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used. The first copper plate portion32may have a thickness in a range from 500 nm to microns, although lesser and greater thicknesses may also be used. The nickel plate portion34may have a thickness in a range from 500 nm to 20 microns, although lesser and greater thicknesses may also be used. The second copper plate portion32may have a thickness in a range from 500 nm to 80 microns, although lesser and greater thicknesses may also be used. The total height of each second metallic bump structure may be in a range from 10 microns to 100 microns, although lesser and greater heights may also be used. Each second metallic bump structure30may have a pillar configuration such that the first copper plate portion32, the nickel plate portion34, and the second copper plate portion36have a same horizontal cross-sectional shape. The same horizontal cross-sectional shape may be a circle, a square, a rounded square, or any two-dimensional curvilinear shape having a closed periphery. The lateral dimension of each second metallic bump structure30(such as a diameter or a lateral distance between parallel pairs of surface segments) is less than the lateral dimension of a cavity overlying a first horizontal bonding surface segment of a first metallic bump structure20described above. In an illustrative example, the lateral dimension of each second metallic bump structure30(such as a diameter or a lateral distance between parallel pairs of surface segments) may be in a range from 2 microns to 50 microns, such as from 6 microns to 30 microns, although lesser and greater lateral dimensions for the lateral dimension may also be used.

A solder material portion40(such as a first solder material portion940described above) may be applied to the second metallic bump structure30.

Referring toFIG.7B, a region of the structure ofFIGS.6A and6Bis shown after bonding the semiconductor die (701or703) to the interposer900. In this embodiment, the solder material portion40may be bonded to the first horizontal bonding surface segment of the first metallic bump structure20. In one embodiment, the solder material portion40may be positioned entirely within a cavity in the passivation dielectric layer9228.

In one embodiment, upon the array of first metallic bump structures20to the array of second metallic bump structures30, a horizontal dielectric surface of a first structure (such as an interposer900) that is most proximal to the second structure (such as a semiconductor die (701,703)) may be located within a first horizontal plane HP1, and a horizontal dielectric surface of the second structure (such as the semiconductor die (701,703)) that is most proximal to the first structure (such as the interposer900) is located within a second horizontal plane HP2. In one embodiment, the array of solder material portions40contact the first horizontal bonding surface segments of the first metallic bump structure20within a third horizontal plane HP3, and an entirety of the array of solder material portions40may be formed between the first horizontal plane HP1and the third horizontal plane HP3.

Generally, any of the configurations for the first metallic bump structure20may be used to provide bonding between a first structure (such as an interposer900) and a second structure (such as a semiconductor die (701,703)).

FIGS.8A-8Dare vertical cross-sectional views of first alternative configurations of a region of the structure in which a first metallic bump structure20is bonded to a second metallic bump structure30according to an embodiment of the present disclosure.

Referring toFIG.8A, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.4Aand a second metallic bump structure30to provide the bonding structure.

Referring toFIG.8B, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.4Band a second metallic bump structure30to provide the bonding structure.

Referring toFIG.8C, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.4Cand a second metallic bump structure30to provide the bonding structure.

Referring toFIG.8D, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.4Dand a second metallic bump structure30to provide the bonding structure.

FIGS.9A-9Eare vertical cross-sectional views of second alternative configurations of a region of the structure in which a first metallic bump structure20is bonded to a second metallic bump structure30according to an embodiment of the present disclosure.

Referring toFIG.9A, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.5Aand a second metallic bump structure30to provide the bonding structure.

Referring toFIG.9B, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.5Band a second metallic bump structure30to provide the bonding structure.

Referring toFIG.9C, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.5Cand a second metallic bump structure30to provide the bonding structure.

Referring toFIG.9D, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.5Dand a second metallic bump structure30to provide the bonding structure.

Referring toFIG.9E, an alternative configuration of a bonding structure is illustrated, which uses a configuration of the first metallic bump structure20illustrated inFIG.5Eand a second metallic bump structure30to provide the bonding structure.

While the present disclosure has been described using embodiments in which the first structure on which the first metallic bump structures20are formed is an interposer900and the second structure on which the second metallic bump structures are formed is a semiconductor die (701,703), embodiments of the present disclosure may be practiced such that the first structure on which the first metallic bump structures are formed is a semiconductor die (701,703) and the second structure on which the second metallic bump structures30are formed is an interposer900. In other words, the first metallic bump structures20may comprise die-side bump structures780, and the second metallic bump structures30may comprise interposer-side bump structures938. In this embodiment, the first connection structures120may be metal interconnect structures730within a semiconductor die (701,703), and the first dielectric layers of the first structure may be the dielectric material layers of the semiconductor die (701,703) that embeds the metal interconnect structures730. The second connection structures130may be the redistribution metal interconnects924within the interposer900, and the second dielectric layers of the second structure may be the redistribution dielectric layers922of the interposer900.

FIGS.10A-10Eare vertical cross-sectional views of third alternative configurations of a region of the structure in which a first metallic bump structure20is bonded to a second metallic bump structure30according to an embodiment of the present disclosure.

Referring toFIG.10A, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.7Bby exchanging locations of the first metallic bump structure20and the second metallic bump structure30. In other words, the first metallic bump structure20is formed on a semiconductor die (701,703) that functions as a first structure, and the second metallic bump structure30is formed on an interposer900that functions as a second structure. The first dielectric layers in the first structure includes a topmost interconnect-level dielectric material layer7227that laterally surrounds a topmost subset of the metal interconnect structures730, and a passivation dielectric layer7228that laterally surrounds the first metallic bump structure20.

In one embodiment, upon the array of first metallic bump structures20to the array of second metallic bump structures30, a horizontal dielectric surface of a first structure (such as a semiconductor die (701,703)) that is most proximal to the second structure (such as an interposer900) may be located within a first horizontal plane HP1, and a horizontal dielectric surface of the second structure (such as the interposer900) that is most proximal to the first structure (such as the semiconductor die (701,703)) is located within a second horizontal plane HP2. In one embodiment, the array of solder material portions40contact the first horizontal bonding surface segments of the first metallic bump structure20within a third horizontal plane HP3, and an entirety of the array of solder material portions40may be formed between the first horizontal plane HP1and the third horizontal plane HP3.

Referring toFIG.10B, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.8Aby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.10C, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.8Bby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.10D, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.8Cby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.10E, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.8Dby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

FIGS.11A-11Eare vertical cross-sectional views of fourth alternative configurations of a region of the structure in which a first metallic bump structure20is bonded to a second metallic bump structure30according to an embodiment of the present disclosure.

Referring toFIG.11A, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.9Aby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.11B, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.9Bby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.11C, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.9Cby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.11D, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.9Dby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

Referring toFIG.11E, an alternative configuration of a bonding structure is illustrated, which may be derived from the bonding structure illustrated inFIG.9Eby exchanging locations of the first metallic bump structure20and the second metallic bump structure30.

For each of the configurations illustrated inFIGS.10B-11E, the first dielectric layers in the first structure includes a topmost interconnect-level dielectric material layer7227that laterally surrounds a topmost subset of the metal interconnect structures730, and a passivation dielectric layer7228that laterally surrounds the first metallic bump structure20.

Further, upon the array of first metallic bump structures20to the array of second metallic bump structures30, a horizontal dielectric surface of a first structure (such as a semiconductor die (701,703)) that is most proximal to the second structure (such as an interposer900) may be located within a first horizontal plane HP1, and a horizontal dielectric surface of the second structure (such as the interposer900) that is most proximal to the first structure (such as the semiconductor die (701,703)) is located within a second horizontal plane HP2. In one embodiment, the array of solder material portions40contact the first horizontal bonding surface segments of the first metallic bump structure20within a third horizontal plane HP3, and an entirety of the array of solder material portions40may be formed between the first horizontal plane HP1and the third horizontal plane HP3.

Referring collectively toFIGS.6A-11E, a bonded assembly is provided, which comprises a first structure {interposer900or semiconductor die (701,703)} and a second structure {semiconductor die (701,703) or interposer900} that are bonded to each other. The first structure {interposer900or semiconductor die (701,703)} comprises first metallic connection structures120surrounded by first dielectric layers (922or722), a passivation dielectric layer (9228or7228) including an array of openings therein, and an array of first metallic bump structures20electrically connected to the first metallic connection structures120and having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane HP1including a distal horizontal surface of the passivation dielectric layer (9228,7228, or2628). The second structure {semiconductor die (701,703) or interposer900} comprises second metallic connection structures130surrounded by second dielectric layers (722or922), and an array of second metallic bump structures30electrically connected to the second metallic connection structures130and having a respective second horizontal bonding surface segment that protrudes from a second horizontal plane HP2including a distal horizontal surface of an dielectric layer selected from the second dielectric layers (722or922) that is most proximal to the first structure {interposer900or semiconductor die (701,703)} toward the first structure {interposer900or semiconductor die (701,703)}. The array of first metallic bump structures20is bonded to the array of second metallic bump structures30through an array of solder material portions40. As in each of the embodiment structures ofFIGS.8A-11E, the second metallic bump structure30may be inserted into an opening formed in the first metallic bump structure20, the second metallic bump structure30may also be referred to as a male metallic bump structure30, the first metallic bump structure20may also be referred to as a female metallic bump structure20.

In one embodiment, the first structure {interposer900or semiconductor die (701,703)} comprises first metallic connection structures120surrounded by first dielectric layers (922or722). Each of the base bump plates (21,22,24,122) is formed on a top surface of a respective one of the first metallic connection structures120. The second structure {(701,703) or900} comprises second metallic connection structures130surrounded by second dielectric layers (722or922). Each of the second metallic bump structures30may be formed on a top surface of a respective one of the second metallic connection structures130.

In one embodiment, bonding surfaces of the second metallic bump structures are more proximal to a third horizontal plane HP3including the first horizontal bonding surface segment than the first horizontal plane HP1is to the third horizontal plane HP3. In one embodiment, an entirety of the array of solder material portions40is located between the first horizontal plane HP1and the third horizontal plane HP3. In one embodiment, one of the second metallic bump structures30has a maximum lateral dimensional that is less than a maximum lateral dimension of one of the first horizontal bonding surface segments that the one of the second metallic bump structures30contacts. In one embodiment, one of the second metallic bump structures30has a maximum lateral dimension that is less than a minimum lateral dimension of an opening selected from the array of openings in the passivation dielectric layer (9228or7228) within which the one of the second metallic bump structures30is located.

In one embodiment, each first metallic bump structure20within the array of first metallic bump structures20comprises a respective base bump plate (21,22,24,122) having a bottom surface contacting a respective one of the first metallic connection structures120, and having a top surface that is spaced from the bottom surface. In one embodiment, each first metallic bump structure20within the array of first metallic bump structures20comprises a respective contoured bump plate (25,26,126) containing a horizontally-extending bottom portion in contact with the base bump plate (21,22,24,122) and a tapered or vertically-extending portion contacting a tapered or vertical sidewall of a respective opening selected from the array of openings in the passivation dielectric layer (9228or7228).

In one embodiment, the first horizontal bonding surface segments are surface segments of the horizontally-extending portions of the contoured bump plates (25,26,126). In one embodiment, the respective contoured bump plate (25,26,126) contains an annular horizontally-extending portion having an inner periphery that is adjoined to a top portion of the tapered or vertically-extending portion of the respective contoured bump plate (25,26,126).

In one embodiment, upon the array of first metallic bump structures20to the array of second metallic bump structures30, a horizontal dielectric surface of the first structure {900or (701,703, or200)} that is most proximal to the second structure {(701,703, or200) or900} is located within a first horizontal plane HP1, and a horizontal dielectric surface of the second structure {(701,703) or900} that is most proximal to the first structure {900or (701,703)} is located within a second horizontal plane HP2. In one embodiment, the array of solder material portions40contact the first horizontal bonding surface segments within a third horizontal plane HP3, and an entirety of the array of solder material portions is formed between the first horizontal plane HP1and the third horizontal plane HP3.

According to another aspect of the present disclosure, a bonded assembly is provided, which comprises a first structure {900or (701,703)} and a second structure {(701,703) or900} that are bonded to each other. The first structure {900or (701,703)} comprises an array of first metallic bump structures20. The second structure {(701,703) or900} comprises an array of second metallic bump structures30. Each first metallic bump structure20within the array of first metallic bump structures20has a respective first horizontal bonding surface segment that is vertically recessed away from the second structure {(701,703) or900} from a first horizontal plane HP1including a horizontal dielectric surface of the first structure {900or (701,703)} that is most proximal to the second structure {(701,703) or900} selected from horizontal dielectric surfaces of the first structure {900or (701,703)}. Each second metallic bump structure30within the array of second metallic bump structures30has a respective second horizontal bonding surface segment that protrudes toward the first structure {900or (701,703)} from a second horizontal plane HP2including a horizontal dielectric surface of the second structure {(701,703) or900} that is most proximal to the first structure {900or (701,703)} selected from horizontal dielectric surfaces of the second structure {(701,703) or900}. The array of first metallic bump structures20is bonded to the array of second metallic bump structures30through an array of solder material portions40.

In one embodiment, one of the first structure {900or (701,703)} and the second structure {(701,703) or900} comprises a semiconductor die (701or703); and another of the first structure {900or (701,703)} and the second structure {(701,703) or900} comprises an interposer900.

Referring toFIG.12, a first underfill material may be applied into each gap between the interposers900and sets of at least one semiconductor die (701,703) that are bonded to the interposers900. The first underfill material may comprise any underfill material known in the art. A first underfill material portion950may be formed within each unit area UA between an interposer900and an overlying set of at least one semiconductor die (701,703). The first underfill material portions950may be formed by injecting the first underfill material around a respective array of first solder material portions940in a respective unit area UA. Any known underfill material application method may be used, which may be, for example, the capillary underfill method, the molded underfill method, or the printed underfill method.

Within each unit area UA, a first underfill material portion950may laterally surround, and contact, each of the first solder material portions940within the unit area UA. The first underfill material portion950may be formed around, and contact, the first solder material portions940, the on-interposer bump structure938, and the on-die bump structures780in the unit area UA. The first underfill material portion950is formed between semiconductor dies (701,703) and an interposer900, and thus, is also referred to as a die-interposer (DI) underfill material portion, or a DI underfill material portion.

Each interposer900in a unit area UA comprises on-interposer bump structure938. At least one semiconductor die (701,703) comprising a respective set of on-die bump structures780is attached to the on-interposer bump structure938through a respective set of first solder material portions940within each unit area UA. Within each unit area UA, a first underfill material portion950laterally surrounds the on-interposer bump structure938and the on-die bump structures780of the at least one semiconductor die (701,703).

Generally, an underfill material portion950may be formed between each facing pair of the at least one interposer900and at least one set of the at least one semiconductor die (701,703). In one embodiment, each interposer900comprises on-interposer bump structures938located above the horizontal plane including the first horizontal surface901of the interposer900, and the horizontally-extending portion of the underfill material portion950is located above the horizontal plane including the first horizontal surface901of the interposer900.

FIGS.13A-13Hare vertical cross-sectional views of a region of various configurations of the structure that includes a bonded pair of a first metallic bump structure and a second metallic bump structure according to an embodiment of the present disclosure.

Referring toFIG.13A, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Acorresponds to the configuration illustrated inFIG.7B.

Referring toFIG.13B, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Bcorresponds to the configuration illustrated inFIG.9A.

Referring toFIG.13C, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Ccorresponds to the configuration illustrated inFIG.10A.

Referring toFIG.13D, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Dcorresponds to the configuration illustrated inFIG.11A.

Referring toFIG.13E, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Ecorresponds to the configuration illustrated inFIG.8C.

Referring toFIG.13F, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Fcorresponds to the configuration illustrated inFIG.9D.

Referring toFIG.13G, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Gcorresponds to the configuration illustrated inFIG.10D.

Referring toFIG.13H, a configuration of a region of a bonding structure in the structure at the processing steps ofFIG.12is illustrated. The configuration illustrated inFIG.13Hcorresponds to the configuration illustrated inFIG.11D.

Referring collectively toFIGS.12,13A,13B,13C, and13D, an underfill material portion950may laterally surrounding the array of solder material portions40(such as the first solder material portions940). In some embodiments, such as in embodiments illustrated inFIGS.13A,13C, and13E-13H, the underfill material portion950may be in contact with the first horizontal bonding surface segments of the first metallic bump structures20.

In some embodiments, such as in embodiments illustrated inFIGS.13A-13D, each first metallic bump structure20within the array of first metallic bump structures20comprises a respective contoured bump plate (25,26,126) contacting the passivation dielectric layer (9228or7228) at the openings in the passivation dielectric layer (9228or7228). In some embodiments, such as in embodiments illustrated inFIGS.13A-13D, each opening within the array of openings comprises a tapered or vertical dielectric surface of the passivation dielectric layer (9228or7228) that is spaced from the underfill material portion (950or292) by a respective one of the contoured bump plates (25,26,126). In some embodiments, such as in embodiments illustrated inFIGS.13E-13H, each opening within the array of openings comprises a tapered or vertical dielectric surface of the passivation dielectric layer (9228or7228) that contacts the underfill material portion (950or292). Configurations of the structure at the processing steps ofFIG.12that correspond to the configurations ofFIGS.8A,8B,8D,9B,9C,9E,10B,10C,10E,11B,11C, and11Eare expressly contemplated herein.

Referring toFIGS.14A and14B, an epoxy molding compound (EMC) may be applied to the gaps between contiguous assemblies of a respective set of semiconductor dies (701,703) and a first underfill material portion950.

The EMC may include an epoxy-containing compound that may be hardened (i.e., cured) to provide a dielectric material portion having sufficient stiffness and mechanical strength. The EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. The EMC may be provided in a liquid form or in a solid form depending on the viscosity and flowability. Liquid EMC provides better handling, good flowability, less voids, better fill, and less flow marks. Solid EMC provides less cure shrinkage, better stand-off, and less die drift. A high filler content (such as 85% in weight) within an EMC may shorten the time in mold, lower the mold shrinkage, and reduce the mold warpage. Uniform filler size distribution in the EMC may reduce flow marks, and may enhance flowability. The curing temperature of the EMC may be lower than the release (debonding) temperature of the first adhesive layer311in embodiments in which the adhesive layer includes a thermally debonding material. For example, the curing temperature of the EMC may be in a range from 125° C. to 150° C.

The EMC may be cured at a curing temperature to form an EMC matrix910M that laterally surrounds and embeds each assembly of a set of semiconductor dies (701,703) and a first underfill material portion950. The EMC matrix910M includes a plurality of epoxy molding compound (EMC) die frames that may be laterally adjoined to one another. Each EMC die frame is a portion of the EMC matrix910M that is located within a respective unit area UA. Thus, each EMC die frame laterally surrounds and embeds a respective a set of semiconductor dies (701,703) and a respective first underfill material portion950. Young's modulus of pure epoxy is about 3.35 GPa, and Young's modulus of the EMC may be higher than Young's modulus of pure epoxy by adding additives. Young's modulus of EMC may be greater than 3.5 GPa.

Portions of the EMC matrix910M that overlies the horizontal plane including the top surfaces of the semiconductor dies (701,703) may be removed by a planarization process. For example, the portions of the EMC matrix910M that overlies the horizontal plane may be removed using a chemical mechanical planarization (CMP). The combination of the remaining portion of the EMC matrix910M, the semiconductor dies (701,703), the first underfill material portions950, and the two-dimensional array of interposers900comprises a reconstituted wafer800W. Each portion of the EMC matrix910M located within a unit area UA constitutes an EMC die frame.

Referring toFIG.15, a second adhesive layer321may be applied to the physically exposed planar surface of the reconstituted wafer800W, i.e., the physically exposed surfaces of the EMC matrix910M, the semiconductor dies (701,703), and the first underfill material portions950. In one embodiment, the second adhesive layer321may comprise a same material as, or may comprise a different material from, the material of the first adhesive layer311. In embodiments in which the first adhesive layer311comprises a thermally decomposing adhesive material, the second adhesive layer321may comprise another thermally decomposing adhesive material that decomposes at a higher temperature, or may comprise a light-to-heat conversion material.

A second carrier substrate320may be attached to the second adhesive layer321. The second carrier substrate320may be attached to the opposite side of the reconstituted wafer800W relative to the first carrier substrate310. Generally, the second carrier substrate320may comprise any material that may be used for the first carrier substrate310. The thickness of the second carrier substrate320may be in a range from 500 microns to 2,000 microns, although lesser and greater thicknesses may also be used.

The first adhesive layer311may be decomposed by ultraviolet radiation or by a thermal anneal at a debonding temperature. In embodiments in which the first carrier substrate310includes an optically transparent material and the first adhesive layer311includes an LTHC layer, the first adhesive layer311may be decomposed by irradiating ultraviolet light through the transparent carrier substrate. The LTHC layer may be absorb the ultraviolet radiation and generate heat, which decomposes the material of the LTHC layer and cause the transparent first carrier substrate310to be detached from the reconstituted wafer800W. In embodiments in which the first adhesive layer311includes a thermally decomposing adhesive material, a thermal anneal process at a debonding temperature may be performed to detach the first carrier substrate310from the reconstituted wafer800W.

Referring toFIG.16, fan-out bonding pads928and second solder material portions290may be formed by depositing and patterning a stack of at least one metallic material that may function as metallic bumps and a solder material layer. The metallic fill material for the fan-out bonding pads928may include copper. Other suitable materials are within the contemplated scope of disclosure. The thickness of the fan-out bonding pads928may be in a range from 5 microns to 100 microns, although lesser or greater thicknesses may also be used. The fan-out bonding pads928and the second solder material portions290may have horizontal cross-sectional shapes of rectangles, rounded rectangles, or circles. Other suitable shapes are within the contemplated scope of disclosure. In embodiments in which the fan-out bonding pads928are formed as C4 (controlled collapse chip connection) pads, the thickness of the fan-out bonding pads928may be in a range from 5 microns to 50microns, although lesser or greater thicknesses may also be used. In some embodiments, the fan-out bonding pads928may be, or include, under bump metallurgy (UBM) structures. The configurations of the fan-out bonding pads928are not limited to be fan-out structures. Alternatively, the fan-out bonding pads928may be configured for microbump bonding (i.e., C2 bonding), and may have a thickness in a range from 30 microns to 100 microns, although lesser or greater thicknesses may also be used. In such an embodiment, the fan-out bonding pads928may be formed as an array of microbumps (such as copper pillars) having a lateral dimension in a range from 10 microns to 25 microns, and having a pitch in a range from microns to 50 microns.

The fan-out bonding pads928and the second solder material portions290may be formed on the opposite side of the EMC matrix910M and the two-dimensional array of sets of semiconductor dies (701,703) relative to the interposer layer. The interposer layer includes a three-dimensional array of interposers900. Each interposer900may be located within a respective unit area UA. Each interposer900may include redistribution dielectric layers922, redistribution wiring interconnects924embedded in the redistribution dielectric layers922, and fan-out bonding pads928. The fan-out bonding pads928may be located on an opposite side of the on-interposer bump structure938relative to the redistribution dielectric layers922, and may be electrically connected to a respective one of the on-interposer bump structure938.

According to an aspect of the present disclosure, the fan-out bonding pads928may be formed as second metallic bump structures30described above. In this embodiment, the interposer900may function as a second structure as far as the fan-out bonding pads928are concerned. In other words, the fan-out bonding pads928may be formed with the same structural characteristics as the second metallic bump structures described above, the interposer900functions as the second structure, and the redistribution dielectric layer922may function as second dielectric layers of the second structure. Formation of the fan-out bonding pads928as the second metallic bump structures30is optional, and may be performed independent of any geometry selected for the first metallic bonding structures20and the second metallic bonding structures that are formed for bonding between the interposer900and the semiconductor dies (701,703).

Referring toFIG.17, the second adhesive layer321may be decomposed by ultraviolet radiation or by a thermal anneal at a debonding temperature. In embodiments in which the second carrier substrate320includes an optically transparent material and the second adhesive layer321includes an LTHC layer, the second adhesive layer321may be decomposed by irradiating ultraviolet light through the transparent carrier substrate. In embodiments in which the second adhesive layer321includes a thermally decomposing adhesive material, a thermal anneal process at a debonding temperature may be performed to detach the second carrier substrate320from the reconstituted wafer800W.

Referring toFIG.18, the reconstituted wafer800W including the fan-out bonding pads928may be subsequently diced along dicing channels by performing a dicing process. The dicing channels correspond to the boundaries between neighboring pairs of die areas DA. Each diced unit from the reconstituted wafer800W may include a fan-out package800. In other words, each diced portion of the assembly of the two-dimensional array of sets of semiconductor dies (701,703), the two-dimensional array of first underfill material portions950, the EMC matrix910M, and the two-dimensional array of interposers900constitutes a fan-out package800. Each diced portion of the EMC matrix910M constitutes a molding compound die frame910. Each diced portion of the interposer layer (which includes the two-dimensional array of interposers900) constitutes an interposer900.

Referring toFIGS.19A and19B, a fan-out package800obtained by dicing the intermediate structure at the processing steps ofFIG.18is illustrated. The fan-out package800comprises an interposer900including on-interposer bump structure938, at least one semiconductor die (701,703) comprising a respective set of on-die bump structures780that is attached to the on-interposer bump structure938through a respective set of first solder material portions940, a first underfill material portion950laterally surrounding the on-interposer bump structure938and the on-die bump structures780of the at least one semiconductor die (701,703).

The fan-out package800may comprise a molding compound die frame910laterally surrounding the at least one semiconductor die (701,703) and comprising a molding compound material. In one embodiment, the molding compound die frame910may include sidewalls that are vertically coincident with sidewalls of the interposer900, i.e., located within same vertical planes as the sidewalls of the interposer900. Generally, the molding compound die frame910may be formed around the at least one semiconductor die (701,703) after formation of the first underfill material portion950within each fan-out package800. The molding compound material contacts a peripheral portion of a planar surface of the interposer900.

Referring toFIGS.20A and20B, a packaging substrate200is provided. The packaging substrate200may be a cored packaging substrate including a core substrate210, or a coreless packaging substrate that does not include a package core. Alternatively, the packaging substrate200may include a system-on-integrated packaging substrate (SoIS) including redistribution layers and/or dielectric interlayers, at least one embedded interposer (such as a silicon interposer). Such a system-integrated packaging substrate may include layer-to-layer interconnections using solder material portions, microbumps, underfill material portions (such as molded underfill material portions), and/or an adhesion film. While the present disclosure is described using an exemplary substrate package, it is understood that the scope of the present disclosure is not limited by any particular type of substrate package and may include an SoIS. The core substrate210may include a glass epoxy plate including an array of through-plate holes. An array of through-core via structures214including a metallic material may be provided in the through-plate holes. Each through-core via structure214may, or may not, include a cylindrical hollow therein. Optionally, dielectric liners212may be used to electrically isolate the through-core via structures214from the core substrate210.

The packaging substrate200may include board-side surface laminar circuit (SLC)240and a chip-side surface laminar circuit (SLC)260. The board-side SLC may include board-side insulating layers242embedding board-side wiring interconnects244. The chip-side SLC260may include chip-side insulating layers262embedding chip-side wiring interconnects264. The board-side insulating layers242and the chip-side insulating layers262may include a photosensitive epoxy material that may be lithographically patterned and subsequently cured. The board-side wiring interconnects244and the chip-side wiring interconnects264may include copper that may be deposited by electroplating within patterns in the board-side insulating layers242or the chip-side insulating layers262.

In one embodiment, the packaging substrate200includes a chip-side surface laminar circuit260comprising chip-side wiring interconnects264connected to an array of chip-side bonding pads268that may be bonded to the array of second solder material portions290, and a board-side surface laminar circuit240including board-side wiring interconnects244connected to an array of board-side bonding pads248. The array of board-side bonding pads248may be configured to allow bonding through solder balls. The array of chip-side bonding pads268may be configured to allow bonding through C4 solder balls. Generally, any type of packaging substrate200may be used. While the present disclosure is described using an embodiment in which the packaging substrate200includes a chip-side surface laminar circuit260and a board-side surface laminar circuit240, embodiments are expressly contemplated herein in which one of the chip-side surface laminar circuit260and the board-side surface laminar circuit240is omitted, or is replaced with an array of bonding structures such as microbumps. In an illustrative example, the chip-side surface laminar circuit260may be replaced with an array of microbumps or any other array of bonding structures.

In embodiments in which the fan-out bonding pads928are formed as second metallic bump structures30, the chip-side bonding pads268may be formed as first metallic bump structures20described above. In this embodiment, the packaging substrate200may function as a first structure as far as the chip-side bonding pads268are concerned. In other words, the chip-side bonding pads268may be formed with the same structural characteristics as the first metallic bump structures20described above, the packaging substrate200functions as the first structure, and the chip-side insulating layers262may function as first dielectric layers of the first structure. The chip-side wiring interconnects264may function as first connection structures120in the first structure. In one embodiment, the chip-side insulating layers262may comprise an interconnection-level insulating layer2627that laterally surrounds the chip-side wiring interconnects264, and a passivation dielectric layer2628that laterally surrounds the first metallic bump structures20(comprising the chip-side bonding pads268). Formation of the fan-out bonding pads928as the second metallic bump structures30and formation of the chip-side bonding pads268as the first metallic bump structures20is optional, and may be performed independent of any geometry selected for the first metallic bonding structures20and the second metallic bonding structures30that are formed for bonding between the interposer900and the semiconductor dies (701,703).

In an alternative embodiment, the fan-out bonding pads928are formed as first metallic bump structures20, and the chip-side bonding pads268may be formed as second metallic bump structures30described above. In other words, the positions of the first metallic bump structures20and the second metallic bump structures30may be reversed between the interposer900and the packaging substrate200. In this embodiment, the interposer900may function as a first structure, and the packaging substrate200may function as a second structure. The redistribution dielectric layers922may function as first dielectric layers of the first structure, the chip-side insulating layers262may function as second dielectric layers of the second structure. The redistribution wiring interconnects924may function as first connection structures120in the first structure. The chip-side wiring interconnects264may function as second connection structures130in the first structure. Formation of the fan-out bonding pads928as the first metallic bump structures20and formation of the chip-side bonding pads268as the second metallic bump structures30is optional, and may be performed independent of any geometry selected for the first metallic bonding structures20and the second metallic bonding structures30that are formed for bonding between the interposer900and the semiconductor dies (701,703).

Referring toFIG.21, the fan-out package800may be disposed over the packaging substrate200with an array of the second solder material portions290therebetween. In embodiments in which the second solder material portions290are formed on the fan-out bonding pads928of the fan-out package800, the second solder material portions290may be disposed on the chip-side bonding pads268of the packaging substrate200. A reflow process may be performed to reflow the second solder material portions290, thereby inducing bonding between the fan-out package800and the packaging substrate200. Each second solder material portion290may be bonded to a respective one of the fan-out bonding pads928and to a respective one of the chip-side bonding pads268. In one embodiment, the second solder material portions290may include C4 solder balls, and the fan-out package800may be attached to the packaging substrate200through an array of C4 solder balls. Generally, the fan-out package800may be bonded to the packaging substrate200such that the interposer900is bonded to the packaging substrate200by an array of solder material portions (such as the second solder material portions290).

Referring toFIGS.22, a second underfill material portion292may be formed around the second solder material portions290by applying and shaping a second underfill material. The second underfill material portion292may be formed by injecting the second underfill material around the array of second solder material portions290after the second solder material portions290are reflowed. Any known underfill material application method may be used, which may be, for example, the capillary underfill method, the molded underfill method, or the printed underfill method.

The second underfill material portion292may be formed between the interposer900and the packaging substrate200. The second underfill material portion292may contact each of the second solder material portions290(which may be C4 solder balls or C2 solder caps), and may contact vertical sidewalls of the fan-out package800. The second underfill material portion laterally surrounds, and contacts, the array of second solder material portions290and the fan-out package800.

Optionally, a stabilization structure294, such as a cap structure or a ring structure, may be attached to the assembly of the fan-out package800and the packaging substrate200to reduce deformation of the assembly during subsequent processing steps and/or during usage of the assembly. The stabilization structure294may comprise a stiffener structure, and may be attached to the packaging substrate200using a first adhesive layer293A and to the at least one semiconductor die (701,703) using a second adhesive layer293B.

In one embodiment, the fan-out package800comprises a molding compound die frame910that laterally surrounds the at least one semiconductor die (701,703) and contacting a peripheral portion of a top surface of the interposer900. The second underfill material portion292may be formed directly on sidewalls of the molding compound die frame910.

Referring toFIG.23, a printed circuit board (PCB)100including a PCB substrate110and PCB bonding pads180may be provided. The PCB100includes a printed circuitry (not shown) at least on one side of the PCB substrate110. An array of solder joints190may be formed to bond the array of board-side bonding pads248to the array of PCB bonding pads180. The solder joints190may be formed by disposing an array of solder balls between the array of board-side bonding pads248and the array of PCB bonding pads180, and by reflowing the array of solder balls. An underfill material portion192may be formed around the solder joints190by applying and shaping an underfill material. The packaging substrate200is attached to the PCB100through the array of solder joints190.

FIG.24is a flowchart illustrating steps for forming a bonded assembly according to an embodiment of the present disclosure.

Referring to step2410andFIGS.1A-3D,4A-4D, and5A-5E, and/orFIGS.20A and20B, base bump plates (21,22,24,122) are formed on a first structure {900or (701,703, or200)}.

Referring to step2420andFIGS.3E,4A-4D, and5A-5E, and/or FIGS. and20B, a passivation dielectric layer (9228,7228, or2628) including an array of openings therein is formed. Top surfaces of the base bump plates (21,22,24,122) are physically exposed within the array of openings.

Referring to step2430andFIGS.3F-3H,4A-4D, and5A-5E, and/orFIGS.20A and20B, an array of first metallic bump structures20is provided. Each first metallic bump structure20within the array of first metallic bump structures20comprises a respective one of the base bump plates (21,22,24,122) and comprises a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane HP1including a distal horizontal surface of the passivation dielectric layer (9228,7228, or2628) and located within a respective opening selected from the array of openings.

Referring to step2440andFIGS.6A-6C,7A,8A-8D,9A-9E,10A-10E, and11A-11E, and/orFIG.16, an array of second metallic bump structures30is formed on a second structure {(701,703, or200) or900}.

Referring to step2450andFIGS.7B,8A-8D,9A-9E,10A-10E,11A-11E,12,13A-13H, and14A-23, the array of first metallic bump structures20may be bonded to the array of second metallic bump structures30through an array of solder material portions40.

Referring to all drawings and according to various embodiments of the present disclosure, a bonded assembly is provided, which comprises a first structure {900or (701,703, or200)} and a second structure {(701,703, or200) or900} that are bonded to each other. The first structure {900or (701,703, or200)} comprises first metallic connection structures120surrounded by first dielectric layers {922or (722or262)}, the first dielectric layers {922or (722or262)} comprising a passivation dielectric layer (9228,7228, or2628) that includes an array of openings therein, and further comprises an array of first metallic bump structures20electrically connected to the first metallic connection structures120, comprising a respective nickel plate portion24having a peripheral region that is covered by the passivation dielectric layer (9228,7228, or2628) and having a center region that underlies a respective one of the openings in the passivation dielectric layer (9228,7228, or2628), and having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane HP1including a distal horizontal surface of the passivation dielectric layer (9228,7228, or2628). The second structure {(701,703, or200) or900} comprises second metallic connection structures130surrounded by second dielectric layers {(722or262) or922}, and second metallic bump structures30electrically connected to the second metallic connection structures130and having a respective second horizontal bonding surface segment that protrudes from a second horizontal plane HP2including a distal horizontal surface of an dielectric layer selected from the second dielectric layers {(722or262) or922} that is most proximal to the first structure {900or (701,703, or200)} toward the first structure {900or (701,703, or200)}. The array of first metallic bump structures20is bonded to the array of second metallic bump structures30through an array of solder material portions40.

In one embodiment, each second metallic bump structure30may comprise a first copper plate portion32, a nickel plate portion34, and a second copper plate portion36. In one embodiment, horizontal cross-sectional shapes of the first copper plate portion32, the nickel plate portion34, and the second copper plate portion36may be the congruent among one another, and may overlap with one another in a plan view. In one embodiment, the first copper plate portion32, the nickel plate portion34, and the second copper plate portion36may have vertically coincident sidewalls, i.e., sidewalls located within a same vertical plane such as a cylindrical vertical plane.

In one embodiment, the sidewalls of the first copper plate portion32, the nickel plate portion34, and the second copper plate portion36may contact an underfill material portion (950or290). In one embodiment, an entirety of the sidewall of the first copper plate portion32and the entirety of the nickel plate portion34may contact the underfill material portion (950or290). A predominant fraction (i.e., more than 50%) of the sidewall of the second copper plate portion36may contact the underfill material portion (950or290). In one embodiment, each second metallic bump structure may comprise a metallic seed layer31in contact with the first copper plate portion32and in contact with the underfill material portion (950or290).

One of the second dielectric material layers {(722or262) or922} contacts the underfill material portion (950or290). In some embodiments, the underfill material portion (950or290) may contact a cylindrical vertical sidewall or a tapered annular sidewall of the one of the second dielectric material layers {(722or262) or922}. In some embodiments, each of the second metallic bump structures20may contact a cylindrical vertical sidewall or a tapered annular sidewall of the one of the second dielectric material layers {(722or262) or922}.

In one embodiment, each of the second metallic bump structures20may comprise a copper plate portion26that contacts a respective solder material portion40. In one embodiment, each of the second metallic bump structures20may comprise a nickel plate portion24that contacts a respective solder material portion40. In one embodiment, each of the second metallic bump structures20may comprise an electrically-conductive-material plate portion (122,126) in contact with a respective solder material portion40. The electrically-conductive-material plate portion (122,126) may comprise a highly electrically conductive material such as gold, silver, or copper. The nickel plate portion24or the electrically-conductive-material plate portion122may be formed as a planar structure having a planar top surface and a planar bottom surface and having sidewalls that have a same vertical extent, which is the vertical spacing between the planar top surface and the planar bottom surface. The copper plate portion26or the electrically-conductive-material plate portion126may be formed as a non-planar structure having a horizontally-extending portion and a vertically-extending portion adjoined to a periphery of the horizontally-extending portion and having a vertical or tapered sidewall in contact with one of the second dielectric material layers {(722or262) or922}.

In one embodiment, bonding surfaces of the second metallic bump structures are more proximal to a third horizontal plane HP3including the first horizontal bonding surface segment than the first horizontal plane HP1is to the third horizontal plane HP3. In one embodiment, an entirety of the array of solder material portions40is located between the first horizontal plane HP1and the third horizontal plane HP3.

In one embodiment, one of the second metallic bump structures30has a maximum lateral dimensional that is less than a maximum lateral dimension of one of the first horizontal bonding surface segments that the one of the second metallic bump structures30contacts. In one embodiment, one of the second metallic bump structures has a maximum lateral dimension that is less than a minimum lateral dimension of an opening selected from the array of openings in the passivation dielectric layer (9228,7228, or2628) within which the one of the second metallic bump structures30is located.

In one embodiment, each first metallic bump structure2020within the array of first metallic bump structures20comprises a respective base bump plate (21,22,24,122) having a bottom surface contacting a respective one of the first metallic connection structures120, and having a top surface that is spaced from the bottom surface. In one embodiment, each first metallic bump structure20within the array of first metallic bump structures20comprises a respective contoured bump plate (25,26,126) containing a horizontally-extending bottom portion in contact with the base bump plate (21,22,24,122) and a tapered or vertically-extending portion contacting a tapered or vertical sidewall of a respective opening selected from the array of openings in the passivation dielectric layer (9228,7228, or2628).

In one embodiment, the first horizontal bonding surface segments are surface segments of the horizontally-extending portions of the contoured bump plates (25,26,126). In one embodiment, the respective contoured bump plate (25,26,126) contains an annular horizontally-extending portion having an inner periphery that is adjoined to a top portion of the tapered or vertically-extending portion of the respective contoured bump plate (25,26,126). In one embodiment, the first horizontal bonding surface segments are surface segments of the base bump plates (21,22,24,122).

In one embodiment, the bonded assembly comprises an underfill material portion (950or292) laterally surrounding the array of solder material portions40, wherein the underfill material portion (950or292) is in contact with the first horizontal bonding surface segments. In one embodiment, each first metallic bump structure20within the array of first metallic bump structures20comprises a respective contoured bump plate (25,26,126) contacting the passivation dielectric layer (9228,7228, or2628) at the openings in the passivation dielectric layer (9228,7228, or2628); and each opening within the array of openings comprises a tapered or vertical dielectric surface of the passivation dielectric layer (9228,7228, or2628) that is spaced from the underfill material portion (950or292) by a respective one of the contoured bump plates (25,26,126).

In one embodiment, each opening within the array of openings comprises a tapered or vertical dielectric surface of the passivation dielectric layer (9228,7228, or2628) that contacts the underfill material portion (950or292).

According to another aspect of the present disclosure, a bonded assembly is provided, which comprises a first structure {900or (701,703, or200)} and a second structure {(701,703, or200) or900} that are bonded to each other. In one embodiment, the first structure {900or (701,703, or200)} comprises first metallic bump structures20; the second structure {(701,703, or200) or900} comprises second metallic bump structures30; each first metallic bump structure20within the first metallic bump structures20comprises a respective nickel plate portion24having a peripheral region that is covered by a passivation dielectric layer (9228,7228, or2628) and having a center region that underlies a respective opening in the passivation dielectric layer (9228,7228, or2628), and has a respective first horizontal bonding surface segment that is vertically recessed away from the second structure {(701,703, or200) or900} from a first horizontal plane HP1including a horizontal dielectric surface of the first structure {900or (701,703, or200)} that is most proximal to the second structure {(701,703, or200) or900} selected from horizontal dielectric surfaces of the first structure {900or (701,703, or200)}; each second metallic bump structure within the second metallic bump structures30has a respective second horizontal bonding surface segment that protrudes toward the first structure {900or (701,703, or200)} from a second horizontal plane HP2including a horizontal dielectric surface of the second structure {(701,703, or200) or900} that is most proximal to the first structure {900or (701,703, or200)} selected from horizontal dielectric surfaces of the second structure {(701,703, or200) or900}; and the array of first metallic bump structures20is bonded to the array of second metallic bump structures30through an array of solder material portions40.

In one embodiment, one of the first structure {900or (701,703)} and the second structure {(701,703) or900} comprises a semiconductor die (701or703); and another of the first structure {900or (701,703)} and the second structure {(701,703) or900} comprises an interposer900.

The various embodiments of the present disclosure provide bridging-resistant bump structures that limits a bump shift range, and avoids bump bridging that leads to unintended electrical connection between bump structures. Particularly, the recessed first horizontal bonding surface segments of the first metallic bump structures20provide lateral confinement of second metallic bump structures30and solder material portions40. The various embodiments of the present disclosure widens the processing window for a bumping process, and provide fine pitch bumping. The various embodiments of the present disclosure provide low height, lightweight, short vertical interconnections with enhanced reliability and power integrity.