Individually biased transistor high frequency switch

A single-pole multiple-throw RF switch includes first and second FET arrangements, each having a gate and a controlled current path (CCP). One end of the CCP of each FET is connected to a common port by way of an arrangement which blocks DC flow between the FETs, but allows RF flow. Bias is applied to the gates of the FETs to enable RF flow through the CCP of a selected one and not through the others. One version uses a single bias source and cross-coupled resistors, and another version uses plural bias sources switched to the various FETs.

FIELD OF THE INVENTION

This invention relates to switches for use at high frequencies, and more particularly to such switches which use Field Effect Transistors (FETs).

BACKGROUND OF THE INVENTION

Field Effect Transistor (FET) high frequency switches are well known in the field of signal transmission. High power high frequency (e.g., radio frequency (RF)) switches using transistor technology are extremely desirable due to their low DC power consumption as compared to traditional PIN diode switches.

FIG. 1ais a simplified diagram, partially in block and partially in schematic form, illustrating a prior-art single-pole double-throw (SPDT) high-frequency or radio-frequency switch10. It is useful to note that the term “radio frequency” has a broad meaning, and encompasses essentially any frequency of alternating signal. In the past, the term “radio-frequency” related to the then-known frequencies which could be used to propagate radio waves, generally in the frequency range of a few kilohertz (KHz) to 1600 megahertz (MHz). Subsequent improvements in technology have made the upper limit of the term difficult to define, but the term may even include the frequencies of light waves. However, the meaning of RF does not include direct current (that is, signal having zero frequency).FIG. 1billustrates a conventional mechanical switch symbol8the single-pole double-throw function of switch10ofFIG. 1a. InFIG. 1b, a single movable “pole”10M is hinged about an axis11M for motion between two positions, the illustrated one of which causes throw10M to be in contact with, and therefore make electrical connection to, independent, individual or separate “port”62and not to individual “port”52, and the non-illustrated one of which results in connection of throw10M to common “port”52and not to port62. Thus, the single pole10M can be set to one of two different “throw” positions, one of which connects common port23to individual port52and not to62, and the other of which connects common port23to individual port62, and not to52.

InFIG. 1a, signal to be propagated is produced by a signal source designated generally as12, which is illustrated as including a conventional voltage source14and series resistance or impedance16. The signal produced by source12is intended to be selectively coupled to one of “load” resistances20and22by way of switch10. Those skilled in the art know that the values of load resistances20and22, and the internal resistance16of source12, should match the characteristic or “surge” impedance of the transmission lines through which signals flow. The characteristic impedance of ordinary transmission lines as used for RF signal propagation ranges from about 50 ohms to about 300 ohms, but specialized transmission lines may have impedances as low as about ten ohms and higher than 300 ohms.

Signal from source12ofFIG. 1ais applied by way of switch common node23, a direct current (DC) blocking capacitor18and a node24to field-effect transistor (FET) arrangements designated as30and40. FET arrangement30is illustrated as including a single FET32, including source, drain and gate electrodes32s,32d, and32g, respectively. Similarly, FET arrangement40is illustrated as including a single FET42, including source, drain and gate electrodes42s,42d, and42g, respectively. The symbol used to illustrate a FET, such as FET32, is intended to include any type of FET, and specifically to include both enhancement- and depletion-mode FETs. The source terminal32sof FET32is connected by way of a DC blocking capacitor50and an individual node52to load resistance20. Similarly, source terminal42sof FET42is connected by way of a DC blocking capacitor60and an individual node62to load resistance22.

Those skilled in the art know that a field-effect transistor includes a controllable path or “channel” extending from the source electrode (source) to the drain electrode (drain), in which the voltage between the gate electrode (gate) and the conductive path or channel controls the conduction of the path or channel.FIG. 1cis a simplified conceptual representation of FET32ofFIG. 1a. InFIG. 1c, the conductive “channel” of the FET is illustrated as an elongated region70extending from the source32sto the drain32d. The conduction of channel70is controlled by the electric field established between the conductive gate electrode72and the conductive channel70. As mentioned, the conduction of the conductive channel extending between the source32sand the drain32dis controlled by the bias voltage applied between the gate32gand the conductive channel70. Since the channel70is conductive to a greater or lesser degree under many operating conditions, the control voltage may be applied between (in the electrical sense, rather than mechanical or positional sense, of the word “between”) the conductive gate structure72and either the source32sor drain32d. InFIG. 1a, the controllable conductive paths or channels of transistors32and42are designated32pand42p, respectively.

All conductors, and especially semiconductors, include inherent resistance. Thus, the conductive channel70ofFIG. 1amay be represented by a resistance extending between the source32sand the drain32d. Such a resistance is illustrated as70′ inFIG. 1d. The value of resistance70will depend upon the biasing of the gate-to-path or -channel region, being relatively small when the FET is ON or conductive, and relatively large when the FET is OFF or nonconductive. In this context, “small” and “large” are relative to the characteristic impedance of the transmission lines through which the RF signal flows, which is typically 50 or 75 ohms. Consequently, a path resistance of, say, 450 ohms in a 50-ohm system or 675 ohms in a 75-ohm system would be “large,” in that such a resistance would result in 20 decibels (dB) of attenuation, while a path resistance of, say, three (3) ohms in a 50-ohm system or 4½ ohms in a 75 ohm system would be “small,” in that the resulting attenuation would be about 0.5 dB.

InFIG. 1a, gate32gof FET32is connected by way of a series resistance92to a node93, and gate42gof FET42is connected by way of a series resistance94to a node95. Resistances92and94may be provided in the form of discrete resistors, or in any suitable other form. Generally, such resistors have a relatively large resistance, on the order of 1000 ohms or more, so as to limit gate current in the event of a momentary short-circuit or arc. However, such resistances are small by comparison with the input resistance or impedance of the gate electrode, and large by comparison with the characteristic impedance of the transmission lines of the system.

InFIG. 1a, a control voltage or bias voltage (bias) arrangement designated generally as80includes a source of direct voltage82illustrated by a battery symbol. Source82has a positive (+) terminal and a negative (−) terminal. The terminals of source82are coupled by way of a switch illustrated as a mechanical double-pole double-throw (DPDT) switch84to the gate terminals32gand42gof FETs32and42. Those skilled in the art know that such mechanical representations are merely for the purpose of explanation, and that electronic switches are ordinarily used. The operation of DPDT switch84is straightforward, and merely has the effect of applying the positive voltage of source82to node93and the negative voltage to node95in one position of the switch, and of applying the negative voltage to node93and the positive voltage to node95in the other position of the switch. In effect, the operation of switch84merely connects the “battery” or source82to nodes93or95with mutually reversed polarities.

When the position of switch84ofFIG. 1ais as illustrated, the positive terminal of source82is connected to node93and the negative terminal is connected to node95, and in the other position of switch84, the positive terminal of source82is connected to node95and the negative terminal is connected to node93. In general, the conduction of the conductive path of a FET can be controlled with either a relatively positive or relatively negative voltage on the gate electrode, depending upon the design and doping of the channel, which is to say that it can operate in either an “enhancement” or “depletion” mode. A junction FET must be operated with the gate junction reverse-biased to maintain the high gate impedance. Forward bias of the gate junction in a junction FET at least lowers the gate impedance and decreases the voltage between the gate electrode and the conductive channel to one semiconductor junction offset voltage, generally referred to as Vg.

FIG. 1eis a simplified representation of those portions of the arrangement ofFIG. 1awhich are relevant to an analysis of the biasing of the FETs therein. Elements ofFIG. 1ecorresponding to those ofFIG. 1aare designated by like reference numerals. InFIG. 1e, there is a direct-current conduction path extending from node93to node95. The path includes, in order beginning from node93, the resistance92, the gate resistance or impedance of transistor32, the resistance of the conductive path extending through node24, the gate resistance or impedance of transistor42, and the resistance of resistor94. In this path, the resistance of the conductors extending through node24are very low. The resistances of resistors92and94are large, but do not control current flow in the gate circuit, because the gate resistance of at least one or the other of the FETs32or34is very high, and establishes the bias current flow from node93to node95regardless of the presence of resistances92and95. Both FETs32and42will exhibit very large impedances, regardless of the polarization of the gate bias voltage. In the case of JFETs, only that one of the gate-to-conductive paths which is reverse biased will have a very high resistance, while the other gate will be forward-biased and have a very low resistance. The gate-to-drain or gate-to-path resistances are so great that the presence of gate resistances93or95make no difference to the gate current or the gate-to-drain voltage. Thus, the gate resistances such as93and95may be ignored for purposes of analysis.

In one case, the two high resistances may be connected in series, as represented by gate-to-drain resistances Rgd32and Rgd42inFIG. 1f. In such a series connection, the voltage drops across the gate-to-conductive-paths of the two FETs will be inversely related to their resistances. If they have the same gate resistances, the applied bias voltage will be divided equally between the two gate-to-drain resistances of the transistors, so that the voltage at node24ofFIG. 1fwill be ½ of the total voltage across control voltage terminals93and95. If the gate-to-drain resistances Rgd32and Rgd42happen to be dissimilar, the bias voltage distribution across the two resistances will be unequal, and the voltage at node24will not be ½ the applied voltage, but some other ratio.

In the case of JFETs, one of the two FETs which is reverse biased will have a large resistance or impedance, and the other will have less than one volt of bias. This is illustrated inFIG. 1g, in which the series connection includes Rgd32, representing the large impedance of the reverse-biased semiconductor junction of FET32, while the forward-biased gate-to-drain junction of FET42is represented by a diode symbol designated Vgd. Thus, in the case of JFETs the total bias voltage available at terminal93, minus one Vgd, will appear across the reverse-biased gate-to-drain junction of that FETs which has a reverse-biased gate junction.

In the arrangement ofFIG. 1a, the bias applied to the pair of FETs32and42is such as to render the controllable conductive path of one of the transistors conductive, and the other nonconductive. That one of the controllable paths32p,42pwhich is rendered conductive by application of appropriate gate bias becomes conductive, and responsive to the applied RF signal, while the other one of the controllable paths is rendered nonconductive, and nominally nonresponsive to the applied RF. The one controllable conductive path which is controlled to conduction may be termed ON, and the one which is controlled to nonconduction may be termed OFF. In use, the ON transistor conducts the RF signal between its individual port and the common port, and the OFF transistor provides little, and ideally no conduction, between its individual port and the common port. Thus, if RF signal is applied from source12to node23, and transistor32is ON and transistor42is OFF, RF signal will be coupled to load resistor20at port52with little loss (so long as the resistance of the conductive path is small compared with the source resistance16and the load resistance20or22). The path from node23to load resistor22at individual port or node62will be quite lossy, because transistor42is OFF, meaning that its conductive channel has a large resistance. In this state, the SPDT switch10may be said to be in a state that couples the signal preferentially to individual port or node52, and not to port or node62. Similarly, if RF signal is applied from source12to node23, transistor42is ON and transistor32is OFF, RF signal will be coupled to load resistor22at port62with little loss, while the path from node23to load resistor20at individual port or node52will be quite lossy. In this state, the SPDT switch10may be said to be in a state that couples the signal preferentially to individual port or node62, and not to port or node52. It should be understood that the switch10can operate for RF conduction in the opposite direction, namely from individual port or node52to common port or node23(in one state of switch10) or from individual port or node62to common node23(in the other state of switch10).

It will be clear that during operation of RF switch10ofFIG. 1a, there is a significant bias-related voltage at junction24, and this bias voltage will, in general, be coupled through the path32p,42pof that one of the FET transistors32,42which happens to be rendered conductive to the source terminal32s,42sof that FET. Capacitors50and60prevent application to the load resistances20,22of this component of the direct bias voltage. This decoupling prevents changes in the bias applied to the RF switch10which might be attributable to the presence or absence of a load resistor at the independent, individual or separate ports of the switch, or to the use of load resistances which are of other than the design value.

FIG. 2is a simplified diagram in block and schematic form of a SPDT RF switch210, which is generally similar to switch10ofFIG. 1a. InFIG. 2, each FET arrangement30,40ofFIG. 1aincludes plural FETs arranged with their controlled current conducting paths in cascade. More particularly, inFIG. 2, FET arrangement30includes FETs321,322, and323. The drain323dof FET323is connected to the source322sof transistor322, and the drain322dof transistor322is connected to the source321sof transistor321. Thus, the conductive paths of the three transistors321,322, and323are connected in series. In effect, the three transistors32i,322, and323have been “combined” to form a composite transistor corresponding to transistor arrangement30, having as a source the source323sof transistor323, as a drain the drain321dof transistor321, and having a plurality of gates, namely gates321g,322g, and323gspaced along the composite controlled conductive path. As illustrated inFIG. 2, the gates321g,322g, and323gare connected in common to bias node93by way of individual resistors921,922, and923, for common biasing of the gates to the composite conductive path. Similarly, FET arrangement40includes FETs421,422, and423. The drain423gof FET423is connected to the source422sof transistor422, and the drain422dof transistor422is connected to the source421sof transistor421. Thus, the conductive paths of the three transistors421,422, and423are connected in series. In effect, the three transistors421,422, and423have been “combined” to form a composite transistor corresponding to transistor arrangement40, having as a source the source423sof transistor423, as a drain the drain421dof transistor421, and having a plurality of gates, namely gates421g,422g, and423gspaced along the composite controlled conductive path.

As illustrated inFIG. 2, the gates421g,422g, and423gare connected in common to bias node95by way of individual resistors941,942, and943, for common biasing of the gates to the composite conductive path. The multitransistor control arrangement ofFIG. 2by comparison with the single-transistor control ofFIG. 1aprovides the advantage of greater isolation between common port23and that individual port associated with the OFF path. It has the disadvantage that the loss in the ON path is greater than in the arrangement ofFIG. 1a. In general, the use of a single transistor for each side of the RF switch has advantages and disadvantages relative to the use of plural cascaded or series transistors, but the basic principles of operation of such a switch are not dependent upon the number of cascaded transistors on each side.

Improved RF switch arrangements are desired.

SUMMARY OF THE INVENTION

A switch according to an aspect of the invention is for switching radio-frequency electromagnetic signal between a common port and first and second individual ports. The switch comprises a first FET including a signal path extending from a source terminal to a drain terminal, and also including a gate terminal. The conduction of the signal path of the first FET is under control of a gate-to-path control voltage applied thereto. A second FET includes a signal path extending from a source terminal to a drain terminal, and also includes a gate terminal. The conduction of the signal path of the second FET is under control of a gate-to-path control voltage applied thereto. Connection means are coupled to the common port, to a first terminal of the signal path of the first FET, and to a first terminal of the signal path of the second FET, for coupling alternating current, but not direct current, between the common port and the first terminals of the signal paths of the first and second FETs. First further connection means are coupled to the second terminal of the signal path of the first FET and to the first individual port, for coupling alternating signal between the second signal terminal of the first FET and the first individual port. Second further connection means are coupled to the second terminal of the signal path of the second FET and to the second individual port, for coupling alternating signal between the second signal terminal of the second FET and the second individual port. At least one controllable source of control voltage is provided. The controllable source of control voltage is coupled to the first and second FETs to bias the first FET for conduction when the second FET is biased for nonconduction, and to bias the second FET for conduction when the first FET is biased for nonconduction.

In a particular embodiment of the switch according to an aspect of the invention, the at least one controllable source of the control voltage defines first and second control voltage terminals across which the control voltage is produced. The controllable source further comprises first conductive means coupled to the first control voltage terminal of the controllable source and to the gate electrode of the first FET, and second conductive means coupled to the first control voltage terminal of the controllable source and to one of the first and second electrodes of the second FET. In addition, third conductive means are coupled to the second control voltage terminal of the controllable source and to the gate electrode of the second FET, and fourth conductive means are coupled to the second control voltage terminal of the controllable source and to one of the first and second electrodes of the first FET. In particularly advantageous embodiments, at least one of the first FET and the second FET is a composite FET including plural cascaded FET sections.

According to an embodiment, a semiconductor switch comprises an input port; at least first and second output ports; a first set of transistors having gate, source and drain terminals and coupled to the first output port at the source terminal; and a second set of transistors having gate, source and drain terminals and coupled to the second output port at the source terminal. A first capacitor is coupled between the input port and the drain terminal associated with the first set of transistors, and a second capacitor is coupled between the input port and the drain terminal associated with the second set of transistors. A first resistor is coupled between the source terminal associated with the first set of transistors and another terminal associated with a controllable voltage signal, and a second resistor is coupled between the source terminal associated with the second set of transistors and another terminal associated with a controllable voltage signal. The switch further includes a controllable source for alternately biasing the first and second sets of transistors between ON and OFF states, wherein the first resistor cooperates with the first and second capacitors to provide a DC path bypassing the gate-drain terminal voltage drop associated with the first set of transistors when the first set is biased in the ON state, and wherein the second resistor cooperates with the first and second capacitors to provide a DC path bypassing the gate-drain terminal voltage drop associated with the second set of transistors when the second set is biased in the ON state.

The input power value at which the switch will begin to distort an input signal is determined by the following equation:
PPL=10 log10{125/Rs[2*N(Vpo+VCTRL)(N*Ron+RS+RL/(N*Ron+RL)]2},
where Vpois the pinchoff voltage of the first set of transistors, VCTRLis the control voltage applied to the gates of the second set of transistors, Ronis the combined “ON” resistance of the second set of transistors, RSis the voltage source resistance, RLis the load resistance, and N is the number of transistors in each of the first and second sets of transistors.

A method is disclosed for controlling a transistor switch comprising at least a first transistor arrangement including a signal path extending from a source terminal to a drain terminal, and also including a gate terminal, the conduction of the signal path being under control of a gate-to-path control voltage, and a second transistor arrangement including a signal path extending from a source terminal to a drain terminal, and also including a gate terminal, the conduction of the signal path being under control of a gate-to-path control voltage. The method comprises providing a first capacitor between the input port and the drain terminal associated with the first transistor arrangement, and a second capacitor between the input port and the drain terminal associated with the second transistor arrangement; providing a first resistor between the source terminal associated with the first transistor arrangement and another terminal, and a second resistor between the source terminal associated with the second transistor arrangement and another terminal; and alternately switching ON and OFF each of the first and second transistor arrangements, whereby a DC path is provided bypassing the gate-drain diode of the first transistor arrangement when said arrangement is in the ON condition, and whereby a DC path is provided bypassing the gate-drain diode of the second transistor arrangement when said arrangement is in the ON condition.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3ais a simplified schematic diagram of an RF switch according to an aspect of the invention. InFIG. 3a, a common node23is for coupling to a common source or sink of alternating or RF signal. For simplicity, the description is couched in terms of propagation from common port23to one or the other of independent, individual, or separate ports52or62, but those skilled in the art will recognize that, as to the RF signal, the circuit is reciprocal or independent of the direction of signal flow. In the case of an RF source connected to port23, the RF or other alternating signal arrives at a node224. From node224, the RF signal is coupled by way of a first capacitor218ato the drain32dof FET32, and by way of a second capacitor218bto the drain42dof FET42. Thus, the RF signal applied to “input” port23becomes available at the drains of both FETS32and42. This is equivalent to saying that the RF signal arrives at the drain end32dof the signal path32pof FET32and at the drain end42dof the signal path42pof FET42ofFIG. 3a. The bias conditions established between the gate electrodes of the FETs and their signal paths or channels determines whether the signal propagates to their source ends.

The biasing arrangement of SPDT switch310ofFIG. 3adiffers from that of SPDT switches10or210ofFIGS. 1aand2, respectively. InFIG. 3a, each terminal93,95to which bias voltage is applied from a control voltage source (not illustrated inFIG. 3a) has a connecting resistor92,94which couples the bias to the corresponding gate electrode32g,42g, respectively, as inFIGS. 1aand2. In addition, the arrangement ofFIG. 3aincludes a further resistor292connecting control bias terminal93to drain42dof FET42, and another resistor294connecting control bias terminal95to drain32dof FET32. The values of additional “cross-coupling” resistors292and294are of the same general order of magnitude as resistors92and94, respectively, so they have no significant effect on the propagation of RF signal through the RF signal paths of the switch310. However, the presence of resistors292and294has an effect on the biasing of the FETs32,42.

FIG. 3bis a simplified schematic diagram illustrating the biasing arrangement as it exists in the switch310ofFIG. 3a. InFIG. 3b, the presence of capacitors218aand218bprevents connection between the drain electrodes32d,42dof FETs32and42, respectively, for purposes of control bias. Examination of the bias available to the gate-to-path of FET32shows that its gate electrode32gis connected by way of resistor92to bias terminal93, and its drain electrode32dis connected by way of resistor294to the other bias terminal95. This biasing arrangement is illustrated inFIG. 3c. Since the resistors are deemed to be irrelevant to the biasing of a FET in which the gate-to-path junction is reverse-biased, the gate32gmay be considered to be connected directly to bias voltage terminal93and the drain32dto be connected directly to bias voltage terminal95. Consequently, the bias voltage available for application to the gate-to-path of transistor32is the full voltage of the supply, not reduced by any division with another FET or by subtraction of a Vgs. By symmetry, the voltage available to FET42is similarly the full bias supply voltage.

In the case in which one of the FETs32,42is a junction FET with a forward-biased junction, the junction voltage will again be 1 Vgs, and the current will be limited by the two resistors in the biasing current path. If it is transistor42which is forward biased, for example, the voltage between its gate42gand drain42dwill be approximately Vgd, and the remainder of the full bias voltage will appear or “be dropped” across series-connected resistors94and292.

It should be noted that inFIG. 3aor3b, only one of capacitors218aand218bis needed in principle in order to isolate the drains32d,42dof FETs32,42, respectively, from each other, so long as the RF source (not illustrated) has a high impedance to direct voltage. Most RF sources, however, have relatively low direct-current impedance or resistance, unless they incorporate a separate capacitor. The arrangement ofFIG. 4illustrates a rearrangement of capacitors on the common side of an RF SPDT switch410. Elements ofFIG. 4corresponding to those ofFIG. 3aor3bare designated by like reference numerals. InFIG. 4, capacitor218aoccupies the same location as inFIG. 3aor3b, namely between node224and the drain32dof FET32. Capacitor418is substituted for capacitor218b, and relocated to lie between node224and input node23. In the arrangement ofFIG. 4, the capacitors218aand418may be ignored for purposes of RF signal flow, so the RF signal is coupled from node23equally to drains32d,42d, as in the arrangement ofFIG. 3a. Direct-current isolation between the drains32dand42dof FETs32and42, and between them and the RF source (not illustrated) which may be connected to port or node23, is provided by capacitors218aand418. More particularly, capacitor218aisolates drain32dfrom drain42g, and capacitor418isolates drain42dfrom port or node23. By symmetry, capacitor218aofFIG. 4could be replaced by a conductor, and a further capacitor218bcould be placed in the path between capacitor418and the drain42dof FET42, with equivalent performance.

As the need arises to design a switch requiring minimum control voltages, the power handling of the switch is challenged only by the pinchoff limited power handling of the OFF transistors. In the present invention, a transistor switch is utilized which eliminates the voltage drop Vdacross the ON transistors, thus altering the equations for determining the input power at which the transistor switch will begin to distort the input signal. For example, the input power at which the transistor switch will begin to distort the input signal where the OFF transistors are pinchoff limited becomes:
PPL=10 log10{125/Rs[2*N(Vpo+VCTRL)(N*Ron+RS+RL/(N*Ron+RL)]2}
It will be noted that the above equation differs significantly from the prior art device equations for Pinl(PL)because additional DC blocking capacitors218a,218bare added at the input port23, thus allowing the independent biasing of the gates of the ON transistors32and the OFF transistors42, and eliminating the diode drop voltage component (Vd) from the equation.

FIG. 4is a simplified diagram in block and schematic form of an alternative arrangement according to an aspect of the invention, in which the connections of the “cross coupling” resistors are made to the sources32s,42sof FETs32and42, respectively, rather than to their drains. As mentioned, the signal paths32pand42pwhich extend from the sources32s,42sto the drains32d,42dof FETs32,42, respectively, may be considered to be resistors of relatively low nominal value, even in the OFF state of the corresponding FET. Consequently, so long as the resistance of the RF signal path is small, it is irrelevant whether the bias voltage is applied to the drain or to the gate, as the gate-to-path bias voltage will be about the same in both situations.FIG. 5illustrates an RF SPDT switch510similar to switch310ofFIG. 3a. Corresponding elements are designated by like reference numerals.FIG. 5differs fromFIG. 3aonly in that the “cross coupling” resistors are designated592and594, and in that they are coupled from control or bias voltage terminals93and95, respectively, to the sources32sand42s, respectively. The arrangement ofFIG. 5will perform generally in the same manner as the arrangements ofFIGS. 3aand4.

Instead of using a single “cross coupling” resistor for each bias connection, it is possible to use two or more connections.FIG. 6is similar toFIG. 3a, with the exception of additional “cross coupling” resistors692and694. Resistor692is connected between bias or control voltage terminal93and that end of the RF conductive path42pof FET42which is remote from that end of the path connected to resistor292. For the described electrode connections of the FET42, the end of resistor692remote from terminal93is connected to the source42sof FET42. Resistor694is connected between bias or control voltage terminal95and that end of the RF conductive path32pof FET32which is remote from that end of the path which is connected to resistor294. For the described electrode connections of the FET32, the end of resistor694remote from terminal95is connected to the source32sof FET32. Such an arrangement will tend to provide more symmetrical bias of the gate-to-path junction in the presence of path resistance.

As described in conjunction with the prior art ofFIG. 1a, each field-effect transistor arrangement30and40may include a single FET transistor, such as32and42, respectively. Alternatively, as described in conjunction with the prior art ofFIG. 2, each field-effect transistor arrangement30and40may be made up of a cascade of plural FETs, such as321,322,323, and421,422,423, respectively. In the cascade, the RF paths are connected end-to-end. This may be accomplished by connecting the drain of a FET in the interior of the cascade to the source of the next in line, and its source to the drain of the previous in line. However, it can be accomplished by connecting sources and drains in any order, if desired.FIG. 7illustrates an RF SPDT switch according to an aspect of the invention in which the interior FETs of a cascade are arranged in such an order. InFIG. 7, FET arrangement30includes a cascade of FETs includes FETs321,322,323, and324, and cascade30of FETs includes FETs421,422,423, and424. The source321sof FET321is connected to the source322sof FET322, the drain322dof FET322is connected to the drain322dof FET323, and the source323sof FET323is connected to the source324sof FET324. While the connections of FET transistor arrangement40could mirror or be symmetrical to the connections of arrangement30, they may be different. InFIG. 7, arrangement40of FETs includes a cascade of FETs421,422,423, and424. The drain421dof FET421is connected to the source422sof FET422, the drain422dof FET422is connected to the drain422dof FET423, and the source423sof FET423is connected to the source424sof FET424.

Also inFIG. 7, the “cross coupling” resistors are shown as being connected at locations lying between interior FETs in a cascade. More particularly, “cross-coupling” resistor592is connected at one end to control or bias voltage source terminal93, and at the other end to the junction of the drain421dof transistor421with the source422sof transistor422. Similarly, the one end of cross-coupling resistor594is connected to bias or control voltage source terminal95and at the other end to the junction between the source323sof FET323and the source324sof FET324. More than two such “cross coupling” resistors can be used, and in fact such a resistor may be connected to the non-cascaded end of end FETs of the cascade, and to each interior junction of the cascade, if desired.

U.S. Pat. No. 6,426,525, issued Jul. 30, 2002 in the name of Brindle, describes the use of harmonic reduction capacitors in conjunction with FETs, for improved harmonic noise rejection. Any of the arrangements according to the invention may include harmonic rejection capacitors such as those of the Brindle patent.

FIG. 8illustrates an arrangement according to an aspect of the invention in which harmonic suppression capacitors are used. InFIG. 8, the common RF port is23. The RF is coupled to the drain421dof a FET421by way of dc blocking capacitor418and node224. Similarly, the RF is coupled to the drain321dof a FET321by way of dc blocking capacitor418, node224, and further de blocking capacitor218a. The path321pof transistor321is cascaded with the path322pof transistor322by connecting the source321sof transistor321to the drain322dof transistor322. The path421pof transistor421is cascaded with the path422pof transistor422by connecting the source421sof transistor421to the drain422dof transistor422. The sources322sand422sof FETs322and422are connected by way of capacitors50and60, respectively, to individual ports52and62. Bias voltage is coupled from terminal93to the gates321gand322gof FETs321and322, respectively, by resistors8921and8922, respectively. Bias voltage is cross coupled from terminal93to the drain421dof FET421by a resistor8923, to the junction of the source421sof FET421with the drain422dof transistor422by a resistor8924, and to the source4322sof transistor4322by a resistor8925. Bias voltage is coupled from terminal95to the gates421gand422gof FETs421and422, respectively, by resistors8941and8942, respectively. Bias voltage is cross coupled from terminal95to the drain321dof FET321by a resistor8943, to the junction of the source321sof FET321with the drain322dof transistor322by a resistor8944, and to the source322sof transistor322by a resistor8945. It should be noted that, for purposes of RF, port or node23, node224, conductors801,802,803,804, and805are, in principle, at the same potential. Those skilled in the art will recognize that the potential may differ due to practical factors such as the electrical lengths of the conductors and their impedances. Assuming that the same potential exists throughout nodes23and224, and conductors801,802,803,804, and805harmonic suppression may be provided by additional RF coupling capacitors820connected between conductor804and the gate321gof FET321and capacitor822connected between conductor805and the gate421gof FET421. Similarly, harmonic suppression may be provided by additional RF coupling capacitors824connected between the gate322gand source322sof transistor322and826connected between the gate422gand source422sof FET422.

FIGS. 9aand9b, referred to together as “FIG.9”, is a simplified diagram in block and schematic form of a single-pole, multiple-throw RF switch910. InFIG. 9, an RF source12is assumed to be coupled to common port23(always remembering that a load can be connected to the common port23, and RF source(s) to one or more of the individual ports). In the arrangement ofFIG. 9, a plurality of controlled single-pole, single-throw RF switches designated generally as A, B, C, . . . D, E extend from common port23to individual ports952a,952b,952c, . . . ,952d,952e, respectively. Each single-pole, single-throw RF switch A, B, C, . . . D, E includes a controllable FET including source (s), drain (d), and gate (g) electrodes, and a controllable path p for the flow of RF signal between the common port23and one of the individual ports. More particularly, switch A includes the series combination of a dc blocking capacitor918a, the drain-to-source conductive path930apof a FET930a, and a further dc blocking capacitor950aextending between common port23and individual port952a. Switch B includes the series combination of a dc blocking capacitor918b, the drain-to-source conductive path930bpof a FET930b, and a further dc blocking capacitor950bextending between common port23and individual port952b. Switch C includes the series combination of a dc blocking capacitor918c, the drain-to-source conductive path930cpof a FET930c, and a further dc blocking capacitor950cextending between common port23and individual port952c. Switch D includes the series combination of a dc blocking capacitor918d, the drain-to-source conductive path930dpof a FET930d, and a further dc blocking capacitor950dextending between common port23and individual port952d, and switch E includes the series combination of a dc blocking capacitor918e, the drain-to-source conductive path930epof a FET930e, and a further dc blocking capacitor950eextending between common port23and individual port952e. Any number of such single-pole, single throw switches may be connected between common port23and additional individual ports (not illustrated).

In the arrangement of switch910ofFIG. 9, each FET is biased by a control voltage or bias applied between its gate electrode or terminal and the conductive path. In the particular embodiment ofFIG. 9, the conductive path is connected, for purposes of biasing, to a reference potential denoted by a conventional ground symbol. More particularly, the sources of FETs930a,930b,930c, . . . ,930d,930eare connected to ground by way of a resistor having a value which is high relative to the characteristic impedance of the RF transmission path, for reducing RF losses, and which is small relative to the gate-to-source impedance, for coupling most of the bias voltage to the gate-to-path junction. Specifically, the source s of FET930ais connected to ground by a resistor999a, the source s of FET930bis connected to ground by a resistor999b, the source s of FET930cis connected to ground by a resistor999c, . . . , the source s of FET930dis connected to ground by a resistor999d, and the source s of FET930eis connected to ground by a resistor999e. A reasonable value for each of the resistors999would be in the range around 1 to 10 kilohms (K). An ON bias voltage is applied to the gate of that one (or more than one, if desired) FET which is to be made conductive for RF, and an OFF bias voltage is applied to that one (or many) of the FETs which are to be OFF. For a single-pole, multiple-throw RF switch (five throws illustrated inFIG. 9), one FET is biased ON and all the other FETs are biased OFF.

The bias for control of the switch ofFIG. 9ais applied over a conductor and through a resistor to the gate of each FET. More particularly, bias for the gate of FET930ais provided by way of a conductive path994aand a gate resistor992a. Similarly, bias for the gate of FET930bis provided by way of a conductive path994band a gate resistor992b, bias for the gate of FET930cis provided by way of a conductive path994cand a gate resistor992c, . . . , bias for the gate of FET930dis provided by way of a conductive path994dand a gate resistor992d, and bias for the gate of FET930eis provided by way of a conductive path994eand a gate resistor992e. As mentioned, one of the biases will ordinarily be an ON bias and the remainder of the biases OFF biases.

Digital or electronic control of the bias voltages is well known to those skilled in the art, but explanations are ordinarily couched in terms of ordinary mechanical switches.FIG. 9billustrates a simplified mechanical switch equivalent which is useful for explaining the bias voltage generation for application to conductors994athrough994e. InFIG. 9b, first and second ganged rotary switch conductive sections984ON and984OFF rotate together. Rotary conductive section984ON has a protruding tab990, and conductive section984OFF has a recessed section995indexed to the same rotational position as tab990. Rotary switch section984ON has five associated fixed switch contacts designated a, b, c, . . . , d, and e, and rotary switch section984OFF has corresponding fixed switch contacts f, g, h, . . . , i, j, where contacts a and f are at the same rotational position, contacts b and g are at the same rotational position, and contact pairs c and h, d and i, and e and j are at the same rotational positions. Rotary switch section984ON makes contact with only one of its fixed contacts at a time, namely that one of the contacts on which tab990falls. Rotary switch section984OFF makes contact with all its associated fixed contacts except that one on which notch995falls.

A control bias source designated980inFIG. 9generates ON bias relative to reference potential and applies it to a contact element991, which makes contact with rotary switch section984ON at all times, so that ON bias is always available at tab990, and on that one of the switch contacts a, b, c, d, or e on which the tab falls. Control bias source980also generates an OFF bias relative to reference, and applies the OFF bias by way of a contact element996to rotary section984OFF. Thus, all switch contacts f, g, h, i, and j associated with rotary switch section984OFF receive OFF bias, except that one on which notch995falls. ON switch terminal a is connected by a conductive path to OFF switch terminal f and to conductive path994a, ON switch terminal b is connected by a conductive path to OFF switch terminal g and to conductive path994b, ON switch terminal c is connected by a conductive path to OFF switch terminal h and to conductive path994c, . . . , ON switch terminal d is connected by a conductive path to OFF switch terminal i and to conductive path994d, and ON switch terminal e is connected by a conductive path to OFF switch terminal j and to conductive path994e. At any rotational position of switch984, one of the conductors994a,994b,994c, . . . ,994d, or994eis connected by way of tab990and the rotational section984ON to the ON bias, and the remaining ones of conductors994a,994b,994c, . . . ,994d, and994eare connected by way of switch section984OFF and conductive element996to receive OFF bias. Thus, as the ganged sections984ON an d984OFF of switch984rotate relative to their fixed contacts, the tab and notch coact to apply ON bias to a selected one of the bias conductors for FETs930a,930b,930c, . . . ,930d, or930e, and OFF bias to the remaining ones of the FETs. Consequently, one, and only one of the FETs ofFIG. 9is turned ON, and the remainder are OFF.

Other embodiments of the invention will be apparent to those skilled in the art. For example, it is understood that multiple throw switches are also contemplated in the application, with control voltages applied to the switch as logical opposites.

Thus, a switch (10) according to an aspect of the invention is for switching radio-frequency electromagnetic signal between a common port (23) and first (52) and second (62) individual ports. The switch (10) comprises a first FET arrangement (30) including a signal path (32p:321p,324p) extending from a source terminal (32s) to a drain terminal (32d:324d), and also including a gate terminal (32g). The conduction of the signal path (32p:321p,324p) of the first FET arrangement (30) is under control of a gate-to-path control voltage applied thereto. A second FET arrangement (40) includes a signal path (42p:421p,424p) extending from a source terminal (42s:424s) to a drain terminal (42d), and also includes a gate terminal (42g). The conduction of the signal path (42p:421p,424p) of the second FET arrangement (40) is under control of a gate-to-path control voltage applied thereto. Connection means (218a,218b:218a,418) are coupled to the common port (23), to a first terminal (one of source and drain) of the signal path (32p:321p,324p) of the first FET arrangement (30), and to a first terminal (one of source and drain) of the signal path (42p) of the second FET arrangement (40), for coupling alternating current (AC or ac), but not direct current (DC or dc), between the common port (23) and the first terminals of the signal paths of the first (30) and second (40) FET arrangements. First further connection means (50) are coupled to the second terminal (the other one of source and drain) of the signal path (32p:321p,324p) of the first FET arrangement (30) and to the first individual port (52), for coupling alternating signal between the second signal terminal (the other one of the source and drain) of the first FET arrangement (30) and the first individual port (52). Second further connection means (60) are coupled to the second terminal (other one of the source and drain) of the signal path (42p:421p,424p) of the second FET arrangement (40) and to the second individual port (60), for coupling alternating signal between the second signal terminal (other one of the source and drain) of the second FET arrangement (40) and the second individual port (62). At least one controllable source of control voltage (80,93,95;980,984) is provided. The controllable source of control voltage (80,93,95;980,984) is coupled to the first (30) and second (40) FET arrangements to bias the first FET arrangement (30) for conduction when the second FET arrangement (40) is biased for nonconduction, and to bias the second FET arrangement (40) for conduction when the first FET arrangement (30) is biased for nonconduction.

In a particular embodiment of the switch (10) according to an aspect of the invention, the at least one controllable source of the control voltage (80,93,95) defines first (terminal93positive: ON) and second (terminal94positive: OFF) control voltage terminals at which control voltage is produced. The controllable source (80,93,95) further comprises first conductive means (92:8921) coupled to the first control voltage terminal (93;93) of the controllable source (80,93,95) and to the gate electrode (32g) of the first FET arrangement (30), and second conductive means (292:592:8924) coupled to the first control voltage terminal (93:93) of the controllable source and to one of the first (42d) and second (43s) electrodes of the second FET arrangement (40). In addition, third conductive means (94:8941) are coupled to the second control voltage terminal (95) of the controllable source (80,93,95) and to the gate electrode (42g) of the second FET arrangement (40), and fourth conductive means (294:594:8944) are coupled to the second control voltage terminal (95) of the controllable source (80,93,95) and to one of the first (32d) and second (32s) electrodes of the first FET arrangement (30). In particularly advantageous embodiments, at least one of the first FET arrangement (30) and the second FET arrangement (40) is a composite FET including plural cascaded FET sections (321,322:421,422).