Method and apparatus for reducing power spikes caused by clock networks

A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

TECHNICAL FIELD

An embodiment of the present invention relates to clock networks in devices implemented on target devices such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). More specifically, embodiments of the present invention relate to a method and apparatus for reducing power spikes caused by clock networks.

BACKGROUND

During circuit switching, transient currents can cause power supply collapse on very large scale integration (VLSI) devices. As current discharges, decoupling capacitance and the power distribution network may have difficulty supplying sufficient current. A current supply collapse may cause logic delay increase or other functional faults in the device. Typically in clocked circuits, the positive clock edge will arrive and cause a wave of activity and a corresponding current spike at each clock cycle. The current spike may create a voltage sag and prevent reliable operation of the target device.

FIG. 1aillustrates an exemplary logic circuit that represents an abstraction of a system implemented on a target device. As shown, a single inverter drives node N with equal capacitive loads C1and C2. The nominal reference terminals for C1and C2are Vdd and ground respectively. The capacitive loads, C1and C2, may be derived from logic and wire and metal capacitance, and shield wires on the target device. Also shown is inductance between the power supply and on-die circuits. As shown inFIG. 1ba rising transition on the load N causes C2to charge through the power supply path, and a falling transition on N causes C1to charge through the power supply path. A rising transition on N causes only internal power dissipation of the charge in C1, which does not affect the power supply. Similarly, a falling transition on N only causes internal power dissipation of the charge in C2.

FIG. 2aillustrates a clock pulse.FIG. 2billustrates the current waveform associated with logic on the device. As shown, the logic on a device typically has a large amount of activity shortly after a positive clock edge. The clock edge causes the flip-flops to switch and a subsequent wave of activity propagates through the combinatorial logic.FIG. 2cillustrates the current waveform associated with a clock network. As shown, the clock network exhibits a current waveform with two narrow spikes at the positive and negative edges of the clock waveform. This leads to a pair of unequal voltage transients at each clock edge as illustrated inFIG. 2d.

In the past, designers added decoupling capacitance on the device to address this problem. The decoupling capacitance required, however, would often need to be several times larger than the capacitive load on the original design. In addition to adding to the cost of the design, the decoupling capacitance had to be built in between Vdd and ground and required a large amount of area, which was undesirable.

Prior approaches used to address clock current did not rely on the details of the relationship of the clock current waveforms to the details of the power distribution network. The analysis inFIGS. 1a-band2a-dshow the details of how a logic transition to a voltage that is the same as the opposite terminal in the parasitic capacitcance causes current that flows completely within the integrated circuit, and therefore does not cause any transient current external to this chip. Since most of the power supply impedance lies off chip, this is the primary source of voltage noise on the chip. In contrast, prior approaches did not distinguish between on-chip and off chip currents. Therefore they considered all current created during a clocking transient to be important, neglecting the significant difference between on-chip and off-chip current. Furthermore these treatments did not consider the possibility of the parasitic clock capacitance to be distributed between Gnd and Vdd, but assumed that it was all connected to Gnd.

SUMMARY

According to an embodiment of the present invention, current spikes associated with a clocking network are adjusted to reduce voltage sags in a system. The current spike may be evenly spread or “smeared out” across the clock cycle or shifted towards a falling edge period of a clock cycle. The adjustments made to the current spikes may be achieved by adjusting clock polarities and/or adjusting the power supply rail to be used by clock lines for shielding. For FPGAs, clock activity program circuits may be used to configure a configurable clock polarity network to minimize noise.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that specific details in the description may not be required to practice the embodiments of the present invention. In other instances, well-known circuits, devices, and programs are shown in block diagram form to avoid obscuring embodiments of the present invention unnecessarily.

FIG. 3is a flow chart illustrating a method for designing a clock network for a system on a target device according to an embodiment of the present invention. At301, characteristics of current in the system are identified. According to an embodiment of the present invention, the characteristic of current for logic is identified. The characteristic may include information regarding whether the current is approximately the same (roughly balanced) across clock cycles or concentrated at the rising edge of the clock cycles. The identification may be achieved using simulations, statistical analysis, actual tests, or other techniques.

At302, if current is approximately the same across clock cycles, control proceeds to one of303and304. If current is not approximately the same across clock cycles, control proceeds to305.FIG. 4a-4dillustrates the current and voltage characteristics of a system having logic current roughly balanced across clock cycles.FIG. 4aillustrates the clock pulse for the system over time.FIG. 4billustrates the logic current for the system over time.FIG. 4cillustrates the clock current for the system over time. The clock network exhibits a current waveform with two narrow spikes at the positive and negative edges of the clock waveform respectively, when C1and C2are equal. This leads to a pair of equal voltage transients at each clock edge as illustrated inFIG. 4d.

At303and304, uniform current smearing is performed. If logic current is approximately equal during both rising and falling edges of clock cycles, it is preferred to balance the current generated by the clock. Uniform current smearing spreads the current generated by clock activity such that current in the clock network is evenly reduced during a clock cycle. According to an embodiment of the present invention, current may be smeared across both rising and falling edges of clock cycles by balancing the capacitive load, C1and C2(shown inFIG. 1), of the system. Balancing the capacitive load involves designing portions of the clock network to have a C1value larger than C2and designing other portions of the clock network to have a C2value larger than C1.

At303, current smearing is performed by using a mix of shield wires to Vdd and ground.FIG. 5aillustrates an exemplary portion of a clocking network500having alternating shields to ground and Vdd to distribute current spikes across a clock cycle. The clocking network500includes a clock line510of a first hierarchy. The clock line510is coupled to a plurality of clock activity program circuits511-514each of which feeds to a clock line521-524of a second hierarchy forming an H-tree structure. According to an embodiment of the present invention, the clock activity program circuits511-514are implemented by buffers which transmit an active high clock signal to clock lines521-524. Each of the clock lines521-524has corresponding shield wires. A first plurality of shield wires531-532corresponding to clock lines521-522are coupled to Vdd. A second plurality of shield wires533-534corresponding to clock lines523-524are coupled to ground.

At304, current smearing is performed by mixing active high and active low clock signals.FIG. 6illustrates an exemplary portion of a clocking network600having a mix of active high and active low clock wires to distribute current spikes across a clock cycle. The clocking network600includes a clock line610of a first hierarchy. The clock line610is coupled to a plurality of clock activity program circuits611-614each of which feeds to a clock line621-624of a second hierarchy forming an H-tree structure. According to an embodiment of the present invention, the clock activity program circuits611-612are implemented by inverters which transmit an active low clock signal (nclk) to clock lines621-622while clock activity program circuits613-614are implemented by buffers which transmit an active high clock signal (clk) to clock lines623-624. Each of the clock lines621-624has corresponding shield wires631-634. The shield wires631-634are coupled to ground.

FIG. 7illustrates an exemplary logic circuit that represents an abstraction of the system implemented on the target device after utilizing the clock network described inFIG. 6. The arrow represents the assertion of clk and nclk, which are rising and falling voltages respectively.

FIGS. 8a-8cillustrate the current and voltage characteristics of the system after utilizing the clock network described inFIG. 6.FIG. 8aillustrates the logic current for the system over time.FIG. 8billustrates the combination of currents for the active high and active low clocks. By arranging that more of the clock current is conducted on the falling edge of the clock vs the rising edge, the bulk of the clock current is shifted to the falling clock edge. Thus the sum of logic and clock currents on rising and falling edges is closer to being equal.FIG. 8cillustrates the power supply voltage for the system over time. It should be appreciated that the current and voltage characteristics illustrated inFIGS. 8a-care also achieved using the clock network described inFIG. 5.

Referring back to305, if current is concentrated at the rising edge of a clock, control proceeds to one of306-308. If current is not concentrated at the rising edge of a clock, control proceeds to309and terminates the procedure. As described previously,FIGS. 2a-2dillustrate the current and voltage characteristic of a system having logic current concentrated at the rising edge of the clock.

At306,307, and308, clock current spikes are shifted to the falling edges of clock cycles. If the logic current is identified to be concentrated at the rising edge of a clock cycle, it may be preferable to concentrate the clock current spike at the falling edge of the clock. This may be achieved by skewing the sizes of C1and C2and arranging node N to be either charged or discharged during the least active part of the clock cycle. According to an embodiment of the present invention, if a clock network is the same polarity as the nominal clock, then increasing C1and decreasing C2will achieve the desired effect. In an embodiment of the present invention where the clock network has an active low polarity, decreasing C1and increasing C2will achieve the desired effect. It should be appreciated that a mix of active high and active low clocks with mixed shield capacitance may also be implemented.

At306, shifting current in a clock network to the falling edge of a clock cycle is performed by using connecting shield wires to Vdd.FIG. 9illustrates an exemplary portion of a clocking network900having shield wires connected to Vdd to shift current spikes to a falling edges of clock cycles. The clocking network900includes a clock line910of a first hierarchy. The clock line910is coupled to a plurality of clock activity program circuits911-914each of which feeds to a clock line921-924of a second hierarchy forming an H-tree structure. According to an embodiment of the present invention, the clock activity program circuits911-914are implemented by buffers which transmit an active high clock signal to clock lines921-924. Each of the clock lines921-924has corresponding shield wires. All of the shield wires of the clock network are coupled to Vdd. This results in having C1increased and C2decreased, leading the current spike of the clock network to occur primarily on the falling edge of the clock.

Referring back toFIG. 3, at307, shifting current in a clock network to the falling edge of a clock cycle is performed by alternating shields to ground and Vdd and mixing active high and active low clocks.FIG. 10illustrates an exemplary portion of a clock network1000having alternating shields to ground and Vdd and mixed active high and active low clocks to concentrate the clock current spikes at the falling edge of the clock cycle according to an embodiment of the present invention. The clocking network1000includes a clock line1010of a first hierarchy. The clock line1010is coupled to a plurality of clock activity program circuits1011-1014each of which feeds to a clock line1021-1024of a second hierarchy forming an H-tree structure. According to an embodiment of the present invention, the clock activity program circuits1011-1012are implemented by inverters which transmit an active low clock signal to clock lines1021-1022while the clock activity program circuits1013-1014are implemented by buffers which transmit an active high clock signal to clock lines1023-1024. Each of the clock lines1021-1024has corresponding shield wires. A first plurality of shield wires1031-1032corresponding to clock lines1021-1022are coupled to ground. A second plurality of shield wires1033-1034corresponding to clock lines1023-1024are coupled to Vdd. This results in having C1increased and C2decreased, leading the current spike of the clock network to occur primarily on the falling edge of the clock.

Referring back toFIG. 3, at308, shifting current in a clock network to the falling edge of a clock cycle is performed by connecting shield wires to ground and transmitting an active low clock signal.FIG. 11illustrates an exemplary portion of a clock network1100having active low clock wires and shield wires connected to ground to shift the clock current spikes to the falling edge of the clock cycle according to an embodiment of the present invention. The clocking network1100includes a clock line1110of a first hierarchy. The clock line1110is coupled to a plurality of clock activity program circuits1111-1114each of which feeds to a clock line1121-1124of a second hierarchy forming an H-tree structure. According to an embodiment of the present invention, the clock activity program circuits1111-1114are implemented by inverters which transmit an active low clock signal to clock lines1121-1124. Each of the clock lines1121-1124has corresponding shield wires1131-1134. All of the shield wires of the clock network are coupled to ground. This results in having C1increased and C2decreased, leading the current spike of the clock network to occur primarily on the falling edge of the clock.

FIG. 12illustrates an exemplary logic circuit that represents an abstraction of the system implemented on the target device after utilizing the procedures described inFIG. 9.

FIGS. 13a-13cillustrate the current and voltage characteristics of the clock network after utilizing the structure described inFIG. 9.FIG. 13aillustrates the active high clock pulse for the system over time.FIG. 13billustrates the current for the clock network over time. As shown, a small current spike occurs during a rising edge of a clock signal and a larger spike occurs during a falling edge of a clock signal. By shifting the clock current to the falling edge of the clock cycle, a pair of unequal voltage transients of reduced magnitude at each clock edge as illustrated inFIG. 13c. It should be appreciated that the current and voltage characteristics illustrated inFIGS. 13b-13care also achieved using the clock network described inFIGS. 10 and 11.

FIG. 14illustrates a portion of a configurable clock polarity network1400according to an embodiment of the present invention. The configurable clock polarity network1400may be implemented on a target device such as an FPGA. FPGAs have routing resources that are pre-fabricated on a chip. The capacitance associated with each clock wire is typically connected to a fixed terminal, either Gnd or Vdd. In order to perform uniform current smearing or shift a clock current spike to a falling edge of a clock cycle on an FPGA, the clock polarities and polarities of components on the FPGA may be configured using the configurable clock polarity network1400. The configurable clock polarity network1400includes a clock line1410of a first hierarchy. The clock line1410is coupled to a plurality of clock activity program circuits1411-1414each of which feeds to a clock line1421-1424of a second hierarchy forming an H-tree structure. According to an embodiment of the present invention, each of the clock activity program circuits1411-1414includes a corresponding programmable clock inverter1441-1444. Each of the programmable clock inverters1441-1444includes a multiplexer programmable to select one of an inverted and non-inverted clock signal from clock line1410to be output onto its corresponding clock line.

Each of the clock lines1421-1424is connected to a plurality of configurable inverter circuits. A configurable inverter circuit couples a clock line to a component on the system. Clock line1421includes configurable inverter circuits1451-1454. Clock line1422includes configurable inverter circuits1461-1464. Clock line1423includes configurable inverter circuits1471-1474. Clock line1424includes configurable inverter circuits1481-1484. Each of the configurable inverter circuits includes a multiplexer programmable to select one of an inverted and non-inverted path to transmit a clock signal to a component.

In order to manage power spikes, the polarity of some segments in a clock network can be chosen to complement the current spikes in the logic network. This may be done be performing a timing and switching window analysis to determine the expected shape of the logic current waveform. The clock polarity can then be set either globally or on a regional basis such that its current spikes occur when the logic current waveform is smaller.

As illustrated inFIG. 14, configurable clock polarity network1400may adjust the polarity of various segments of the network to minimize total power supply network noise. Configurable inverters are available downstream of the global clock network to compensate for possible inversion on the global clock network.

According to an embodiment of the present invention, the configurable clock polarity network1400may be coupled to its FPGA's clock multiplexing circuitry that allows one of several clock lines to be selected for a given clock signal. In this embodiment, approximately half the clock lines in a given region may be skewed so that the larger current spike occurs for a rising transition using shield wires coupled to ground, and the other half can be skewed so that the larger spike occurs for a falling edge by using shield wires coupled to Vdd. When an EDA tool is performing routing on the FPGA and is determining which clock lines to use, it can be biased or constrained to select the clock lines in the region that produces the desired current spike behavior. For example, if in a given region the logic current waveform is higher at the falling clock edge, the router may select clock lines in the region that produce a current spike on a rising transition such as clock lines having shields connected to ground.

According to an embodiment of the present invention, an EDA tool selects clock lines that produce a current spike on a falling transition because that is the inactive edge of a clock. To accommodate this biased demand, a programmable inversion can be added at the clock source. This, combined with configurable inversions at the destination registers would allow the EDA tool to make use of clock lines that produce a current spike on a rising transition for a positive edge triggered clock domain. A rising transition through the clock network now corresponds with the negative (inactive) edge of the clock and would likely lower logic current demand.

FIG. 5billustrates an alternate embodiment of the present invention, the clock shield line can be configurably connected to either Vdd or Gnd by a buffer that configurably drives either a high or low voltage on each clock shield line. When the voltage driven is high, the buffer forms an electrical connection to Vdd and when the voltage driven is low, the buffer forms an electrical connection to Gnd. The same EDA flow used forFIG. 5amay be applied to the assignment of shield wire voltages.

FIG. 15is a flow chart illustrating a method for designing a clock network for a system on a target device according to an embodiment of the present invention. At1501, synthesis is performed on a design of a system. According to an embodiment of the present invention, synthesis generates an optimized logical representation of the system from a HDL design definition. The optimized logical representation of the system may include a representation that has a minimized number of functional blocks such as logic gates, logic elements, and registers required for the system

At1502, technology mapping is performed on the optimized logic design. Technology mapping includes determining how to implement logic gates and logic elements in the optimized logic representation with resources available on the target device. The resources available on the target device may be referred to as “cells” or “components” and may include logic-array blocks, registers, memories, digital signal processing blocks, input output elements, and/or other components. According to an embodiment of the present invention, an optimized technology-mapped netlist (cell netlist) is generated from the HDL.

At1503, the mapped logical system design is placed. Placement works on the optimized technology-mapped netlist to produce a placement for each of the functional blocks. According to an embodiment of the present invention, placement includes fitting the system on the target device by determining which resources available on the target device are to be used for specific function blocks in the optimized technology-mapped netlist. According to an embodiment of the present invention, placement may include clustering which involves grouping logic elements together to form the logic clusters present on the target device.

At1504, the system is routed. Routing the mapped logical system design involves determining which routing resources should be used to connect the components in the target device implementing the functional blocks of the system. During routing, routing resources on the target device are allocated to provide interconnections between logic gates, logic elements, and other components on the target device. The routing procedure may be performed by a router in an EDA tool that utilizes routing algorithms.

At1505, an analysis is performed on the solution generated from procedures1501-1504. According to an embodiment of the present invention, the analysis includes a timing analysis that determines the possible switching times for each node in the circuit. Current waveforms may be generated by adding a current draw proportional to the capacitance of each node at each point where it can switch. The current draw may be multiplied by a transition probability to weight the current draw. Transition probabilities can be calculated by various methods used to estimate power consumption. The analysis produces an estimate of logic current draw.

At1506, modifications are made to the clock network, when needed, in order to reduce power spikes. The modifications may be achieved by configuring the clock activity program circuits and/or configurable inverter circuits in the configurable clock polarity network of the target device.

At1507, an assembly procedure is performed. The assembly procedure involves creating a data file that includes some of the information determined by the procedure described by1501-1507. The data file may be a bit stream that may be used to program the target device. According to an embodiment of the present invention, when a target device is programmed, resources on the target device are physically transformed to implement components in the system. According to an embodiment of the present invention, the procedures illustrated inFIG. 1may be performed by an EDA tool executed on a first computer system. The data file generated may be transmitted to a second computer system to allow the design of the system to be further processed. Alternatively, the data file may be transmitted to a second computer system which may be used to program the target device according to the system design. It should be appreciated that the design of the system may also be output in other forms such as on a display device or other medium.

FIG. 16is a flow chart illustrating a method for configuring a configurable clock polarity network on a target device according to an embodiment of the present invention. The procedure illustrated inFIG. 16may be used at1506inFIG. 15. At1601, if it is determined that current levels are approximately the same across clock cycles, control proceeds to1602. If it is determined that current levels are not approximately the same across clock cycles, control proceeds to1604.

At1602, uniform current smearing is performed. If logic current is approximately equal during both rising and falling edges of clock cycles, it is preferred to balance the current generated by the clock. Uniform current smearing spreads the current generated by clock activity such that current in the clock network is evenly reduced during a clock cycle. According to an embodiment of the present invention, current may be smeared across both rising and falling edges of clock cycles by balancing the capacitive load, C1and C2(shown inFIG. 1), of the system. Balancing the capacitive load involves designing portions of the clock network to have a C1value larger than C2and designing other portions of the clock network to have a C2value larger than C1. According to an embodiment of the present invention where the configurable clock polarity network is implemented using the configuration illustrated inFIG. 14, a first plurality of clock activity program circuits is selected to invert a clock signal to output to a first plurality of clock lines in the target device and a second plurality of clock activity program circuit is selected to output a non-inverted clock signal to output to a second plurality of clock lines in the target device.

At1603, a first plurality of configurable inverter circuits corresponding to components on the first plurality of clock lines are configured to select an inverted path to change the inverted clock signal to a non-inverted signal to the components.

At1604, if it is determined that current levels are concentrated at the rising edge of a clock, control proceeds to1605. If it is determined that current levels are not concentrated at the rising edge of a clock, control proceeds to1607and terminates the procedure.

At1605, clock current spikes are shifted to the falling edges of clock cycles. If the logic current is identified to be concentrated at the rising edge of a clock cycle, it may be preferable to concentrate the clock current spike at the falling edge of the clock. This may be achieved by skewing the sizes of C1and C2and arranging node N to be either charged or discharged during the least active part of the clock cycle. According to an embodiment of the present invention, if a clock network is the same polarity as the nominal clock, then increasing C1and decreasing C2will achieve the desired effect. In an embodiment of the present invention where the clock network has an active low polarity, decreasing C1and increasing C2will achieve the desired effect. According to an embodiment of the present invention, shifting current in a clock network to the falling edge of a clock cycle is performed by configuring activity program circuits in the configurable clock polarity network to invert a clock signal to be transmitted to all the clock lines on the target device.

At1606, all of the configurable inverter circuits corresponding to components on the clock lines are configured to select an inverted path to change the inverted clock signal to a non-inverted signal to the components.

According to an alternate embodiment of the present invention,FIG. 20illustrates an alternate method for designing a clock network for a system on a target device. This method involves calculating a current waveform across a clock cycle, determining differences between current at a rising and falling edges of the clock, determining an amount of clock current to assign each clock edge, and adjusting the clock network to balance currents at rising and falling edges. If there is a small imbalance between rising and falling edges, then the clocks should be configured with a nearly equal cap to Vdd and Gnd to compensate.

At2001, a current waveform associated with the logic circuits is determined.

At2002, the waveform is examined to determine the imbalance between rising and falling edges.

At2003, the amount of current associated with the clock network transistions is determined.

At2004, the amount of clock current to associate with the rising and falling edges is determined.

At2005-2007, one or more of the methods of assigning shield capacitance to Vdd or Gnd, choosing a clock polarity, or configurably assigning a shield voltage is used to balance the current as much as possible within the constraints of the logic and clock current demands.

FIG. 17is a block diagram of an exemplary computer system1700in which an example embodiment of the present invention resides. The computer system1700may be used to implement a system designer as shown inFIG. 18. The computer system1700includes a processor1701that processes data signals. The processor1701is coupled to a CPU bus1710that transmits data signals between processor1701and other components in the computer system1700.

The computer system1700includes a memory1713. The memory1713may store instructions and code represented by data signals that may be executed by the processor1701.

A bridge memory controller1711is coupled to the CPU bus1710and the memory1713. The bridge memory controller1711directs data signals between the processor1701, the memory1713, and other components in the computer system1700and bridges the data signals between the CPU bus1710, the memory1713, and a first IO bus1720.

The first IO bus1720may be a single bus or a combination of multiple buses. The first IO bus1720provides communication links between components in the computer system1700. A network controller1721is coupled to the first IO bus1720. The network controller1721may link the computer system1700to a network of computers (not shown) and supports communication among the machines. A display device controller1722is coupled to the first IO bus1720. The display device controller1722allows coupling of a display device (not shown) to the computer system1700and acts as an interface between the display device and the computer system1700.

A second IO bus1730may be a single bus or a combination of multiple buses. The second IO bus1730provides communication links between components in the computer system1700. A data storage device1731is coupled to the second IO bus1730. The data storage device1731may be a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device or other mass storage device. An input interface1732is coupled to the second IO bus1730. The input interface1732may be, for example, a keyboard and/or mouse controller or other input interface. The input interface1732may be a dedicated device or can reside in another device such as a bus controller or other controller. The input interface1732allows coupling of an input device to the computer system1700and transmits data signals from an input device to the computer system1700. A bus bridge1723couples the first IO bus1720to the second IO bus1730. The bus bridge1723operates to buffer and bridge data signals between the first IO bus1720and the second IO bus1730. It should be appreciated that computer systems having a different architecture may also be used to implement the computer system1700.

A system designer1740, may reside in memory1713and be executed by processor1701. The system designer1740may operate to synthesize a system, map the system, place the system on a target device, route the system, perform analysis on a design for the system, and modify the clock network of the system to reduce power spikes if needed.

FIG. 18illustrates a system designer1800according to an embodiment of the present invention. The system designer1800may be an EDA tool for designing a system on a target device. The target device may be, for example, an FPGA, a PLD, or other circuitry. Furthermore the logic design may be implemented using semiconductor or nanoelectronic technology.FIG. 18illustrates software modules implementing an embodiment of the present invention. According to one embodiment, system design may be performed by a computer system executing sequences of instructions represented by the software modules shown inFIG. 18. Execution of the sequences of instructions causes the computer system to support system design as will be described hereafter. In alternate embodiments, hard-wire circuitry may be used in place of or in combination with software instructions to implement the present invention. Thus, the present invention is not limited to any specific combination of hardware circuitry and software. The system designer1800includes a designer manager1810. The designer manager1810receives a design for a system. The design may be described at a gate level or in a more abstract level. The design may be described in terms of an HDL such as VHDL or Verilog. The target device may be an ASIC, structured ASIC, FPGA, PLD, or other target device. The designer manager1810is connected to and transmits data between the components of the system designer1800.

Block1820represents a synthesis unit that performs synthesis. The synthesis unit1820generates a logic design of a system to be implemented in the target device. According to an embodiment of the system designer1800, the synthesis unit1820takes a conceptual HDL design definition and generates an optimized logical representation of the system. The optimized logical representation of the system generated by the synthesis unit1820may include a representation that has a minimized number of functional blocks and registers, such as logic gates and logic elements, required for the system. Alternatively, the optimized logical representation of the system generated by the synthesis unit1820may include a representation that has a reduced depth of logic and that generates a lower signal propagation delay.

Block1830represents a mapping unit. The mapping unit1830performs technology mapping. Technology mapping involves determining how to implement the functional blocks and registers in the optimized logic representation utilizing specific resources on a target device thus creating an optimized “technology-mapped” netlist. The technology-mapped netlist illustrates how the resources (components) on the target device are utilized to implement the system.

Block1840represents a placement unit that performs placement. The placement unit1840places the system on to the target device by determining which components or areas on the target device are to be used for specific functional blocks and registers. According to an embodiment of the system designer1800, the placement unit1840first determines how to implement portions of the optimized logic design in clusters. Clusters may represent a subset of the components on the logic design. A cluster may be represented, for example, by a number of standard cells grouped together. In this embodiment, after portions of the optimized logic design are implemented in clusters, the clusters may be placed by assigning the clusters to specific positions on the target device. The placement unit1840may utilize a cost function in order to determine a good assignment of resources on the target device.

Block1850represents a routing unit1850that determines the routing resources on the target device to use to provide interconnection between the components implementing functional blocks and registers of the logic design.

Block1860represents an analysis unit. The analysis unit1860may perform timing analysis to determine the possible switching times for each node in the system. Current waveforms may be generated by adding a current draw proportional to the capacitance of each node at each point where it can switch. The current draw may be multiplied by a transition probability to weight the current draw. Transition probabilities can be calculated by various methods used to estimate power consumption. The analysis produces an estimate of logic current draw.

Block1870represents a clock network configuration unit. The clock network configuration unit1870evaluates the analysis performed by the analysis unit1860and determines whether to make modifications on the clock network to reduce power spikes. The modifications may be achieved by configuring the clock activity program circuits and/or configurable inverter circuits in the configurable clock polarity network of the target device to perform uniform current smearing or shifting of clock current spikes to falling edges of clocks.

According to an embodiment of the system designer1800, the design manager1810also performs an assembly procedure that creates a data file that includes the design of the system generated by the system designer1800. The data file may be a bit stream that may be used to program the target device. The design manager1810may output the data file so that the data file may be stored or alternatively transmitted to a separate machine used to program the target device. It should be appreciated that the design manager1810may also output the design of the system in other forms such as on a display device or other medium.

FIG. 19illustrates an exemplary target device1900in which a system may be implemented on utilizing an FPGA according to an embodiment of the present invention. According to one embodiment, the target device1900is a chip having a hierarchical structure that may take advantage of wiring locality properties of circuits formed therein.

The target device1900includes a plurality of logic-array blocks (LABs). Each LAB may be formed from a plurality of logic blocks or logic elements, carry chains, shared arithmetic chains, LAB control signals, and register chain connection lines. A logic block is a small unit of logic providing efficient implementation of user logic functions. A logic block includes one or more LUT-based resources, logic gates, programmable registers, and a single output. Depending on its architecture, a logic block may also include dedicated adders, a carry chain, an arithmetic chain, and a register train. LABs are grouped into rows and columns across the target device1900. Columns of LABs are shown as1911-1916. It should be appreciated that the logic block may include additional or alternate components.

The target device1900includes memory blocks. The memory blocks may be, for example, dual port random access memory (RAM) blocks that provide dedicated true dual-port, simple dual-port, or single port memory up to various bits wide at up to various frequencies. The memory blocks may be grouped into columns across the target device in between selected LABs or located individually or in pairs within the target device900. Columns of memory blocks are shown as1921-1924.

The target device1900includes digital signal processing (DSP) blocks. The DSP blocks may be used to implement multipliers of various configurations with add or subtract features. The DSP blocks include shift registers, multipliers, adders, and accumulators. The DSP blocks may be grouped into columns across the target device1900and are shown as1931.

The target device1900includes a plurality of input/output elements (IOEs)1940. Each IOE feeds an I/O pin (not shown) on the target device1900. The IOEs are located at the end of LAB rows and columns around the periphery of the target device1900.

The target device1900includes LAB local interconnect lines (not shown) that transfer signals between LEs in the same LAB, a plurality of row interconnect lines (“H-type wires”) (not shown) that span fixed distances, and a plurality of column interconnect lines (“V-type wires”) (not shown) that operate similarly to route signals between components in the target device. The target device1900also includes a clock network (not shown) which transmits clock signals to components on the target device. The clock network may include the configurable clock polarity network which is shown in part onFIG. 14.

FIG. 19illustrates an exemplary embodiment of a target device. It should be appreciated that a system may include a plurality of target devices, such as that illustrated inFIG. 19, cascaded together. It should also be appreciated that the target device may include programmable logic devices arranged in a manner different than that on the target device1900. A target device may also include FPGA resources other than those described in reference to the target device1900. Thus, while the invention described herein may be utilized on the architecture described inFIG. 19, it should be appreciated that it may also be utilized on different architectures, such as those employed by Altera Corporation or Xilinx Inc.

FIGS. 3,15, and16are flow charts illustrating methods according to embodiments of the present invention. The techniques illustrated in these figures may be performed sequentially, in parallel or in an order other than that which is described. The techniques may be also be performed one or more times. It should be appreciated that not all of the techniques described are required to be performed, that additional techniques may be added, and that some of the illustrated techniques may be substituted with other techniques.

Embodiments of the present invention may be provided as a computer program product, or software, that may include an article of manufacture on a machine accessible or machine readable medium having instructions. The instructions on the machine accessible or machine readable medium may be used to program a computer system or other electronic device. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks or other type of media/machine-readable medium suitable for storing or transmitting electronic instructions. The techniques described herein are not limited to any particular software configuration. They may find applicability in any computing or processing environment. The terms “machine accessible medium” or “machine readable medium” used herein shall include any medium that is capable of storing, or encoding a sequence of instructions for execution by the machine and that cause the machine to perform any one of the methods described herein. Furthermore, it is common in the art to speak of software, in one form or another (e.g., program, procedure, process, application, module, unit, logic, and so on) as taking an action or causing a result. Such expressions are merely a shorthand way of stating that the execution of the software by a processing system causes the processor to perform an action to produce a result.

In the foregoing specification embodiments of the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments of the invention. For example, the configurable clock polarity network illustrated inFIG. 14is shown to have its shield wires connected to ground. It should be appreciated that some or all of the shield wires may be connected to Vdd. In these alternate embodiments, alternative methodolgies for configuring the configurable clock polarity network to perform uniform current smearing and shifting of clock current spikes may be performed in addition to those illustrated inFIG. 16to form configurations having characteristics similar to those illustrated inFIGS. 5,9, and10. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.