Current mode transconductance capacitance filter within a radio frequency digital to analog converter

A filter stage system, includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous time baseband filter generates a filtered current, and a mirroring component mirrors the filtered current to an output.

TECHNICAL FIELD

The subject disclosure relates to an integrated radio frequency digital to analog converter (RF DAC), and more specifically, utilizing a current mode transconductance-capacitance filter to generate a filtered current and provide a path to reuse current between the filter and adjacent stages in a signal chain.

BACKGROUND

Quantum computing is generally the use of quantum-mechanical phenomena to perform computing and information processing functions. Quantum computing can be viewed in contrast to classical computing, which generally operates on binary values with transistors. That is, while classical computers can operate on two basis states that are either 0 or 1, quantum computers operate on quantum bits that comprise superposition of both 0 and 1 based on probability, can entangle multiple quantum bits, and use interference. Quantum computing is emerging as a new paradigm to solve a wide class of problems that show unfavorable scaling on a conventional classical high-performance computer. Arbitrary waveform generation capability with variable amplitude and low distortion is desirable in multiple contexts, including in the control of qubits in the field of quantum computing. In particular, radio frequency digital to analog converters (RFDACs) is valuable in a variety of applications, including wireless transmitters and implementing control pulses for qubits. The filter implementation and the interface between the filter and the other elements of the signal chain are of significance in such designs. Continuous-time filters are well suited for high dynamic range, low power active filter implementations. Current mode signal processing is well suited for low distortion applications, as it reduces voltage swings at various nodes of interest. However, a traditional current mode input filter using an operational amplifier consumes a significant amount of power and has limitations with high frequency applications.

SUMMARY

The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements, delineate scope of particular embodiments or scope of claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, computer-implemented methods, apparatus and/or computer program products facilitate an integrated radio frequency digital to analog converter (RF DAC), and more specifically, utilizing a current mode transconductance-capacitance filter to generate a filtered current and provide a path to reuse current between the filter and adjacent stages in a signal chain.

In accordance with an embodiment, a system comprises a processor that executes the following system executable components stored in memory: a radio-frequency digital to analog converter (RFDAC) operating in current mode and a continuous-time baseband filter that comprises a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current.

In an optional aspect, a mirroring component, operating in the current mode, mirrors the filtered current to an output.

In accordance with an embodiment, a system implemented method, comprises: a radio-frequency digital to analog converter, to execute system executable components to perform the following acts: to operate in current mode along with a baseband filter wherein the inputs and outputs of system blocks are represented as currents.

In an optional aspect, the system implemented method further comprises mapping, by the system, a mirroring component, operating in the current mode, mirrors the filtered current to an output wherein it selectively changes a mirroring ratio to achieve a variable gain relative to a fine baseline step.

DETAILED DESCRIPTION

The following detailed description is merely illustrative and is not intended to limit embodiments and/or application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Summary section, or in the Detailed Description section. One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident; however, in various cases, that the one or more embodiments can be practiced without these specific details.

The subject disclosure relates generally to systems and methods that implement a current mode end-to-end path from radio frequency digital to analog converter (RF DAC) through output which enables realization of a favorable set of trade-offs regarding power consumption and distortion. The elements of a signal path are RFDAC, baseband filter, mirror, and an output stage. Benefits can be achieved by implementing an entire chain in current mode or implementing sub-elements of the chain in current mode.

Embodiments integrate a radio frequency digital to analog converter utilizing a current mode transconductance capacitance filter to generate a filtered current and provide a path to current reuse between the filter and adjacent stages in a signal chain. Current mode signal processing is well suited for low distortion applications, as it reduces voltage swings at various nodes of interest. However, traditional current mode input filters using an operational amplifier consume significant amount of power and have limitations to high frequency applications. Embodiments disclosed and claimed herein propose a promising solution to this problem by introducing a current mode signal path design in the implementation of an integrated digital to analog converter. Implementing an efficient current-mode filter stage offers multiple benefits in the context of a proposed end-to-end current mode analog signal path RF DAC architecture that has been developed for low-power, low-distortion arbitrary waveform generation applications. It provides a path to current reuse between the filter and adjacent stages in the signal chain. It also avoids introducing additional current-voltage conversions in the signal path (such conversions may be included in the feedback path), which helps limit undesirable distortion products and aligns well with low output amplitude requirements.

Quantum computation uses a qubit as its essential unit instead of a classical computing bit. A qubit (e.g., quantum binary digit) is a quantum-mechanical analog of a classical bit. Whereas classical bits can employ on only one of two basis states (e.g., 0 or 1), qubits can employ on superpositions of those basis states (e.g., α|0>+β|1>, where α and β are complex scalars such that |α|2+|β|2=1), allowing several qubits to theoretically hold exponentially more information than the same number of classical bits. Thus, quantum computers (e.g., computers that employ qubits instead of solely classical bits) can, in theory, quickly solve problems that can be extremely difficult for classical computers. The bits of a classical computer are simply binary digits, with a value of either 0 or 1. Almost any device with two distinct states can serve to represent a classical bit: a switch, a valve, a magnet, a coin, or similar binary-type state measure. Qubits, partaking of the quantum mystique, can occupy a superposition of 0 and 1 states. It's not that the qubit can have an intermediate value, such as 0.63; when the state of the qubit is measured, the result is either 0 or 1. But in the course of a computation, a qubit can act as if it were a mixture of states—for example: 63 percent 0 and 37 percent 1. General quantum programs require coordination of quantum and classical parts of a computation. One way to think about general quantum programs is to identify processes and abstractions involved in specifying a quantum algorithm, transforming the algorithm into executable form, running an experiment or simulation, and analyzing the results. A notion throughout these processes is the of intermediate representations. An intermediate representation (IR) of computation is neither its source language description nor the target machine instructions, but something in between. Compilers may use several IRs during the process of translating and optimizing a program. The input is a source code describing a quantum algorithm and compile time parameter(s). The output is a combined quantum/classical program expressed using a high-level IR. A distinction between quantum and classical computer is that the quantum computer is probabilistic, thus measurements of algorithmic outputs provide a proper solution within an algorithm specific confidence interval. The computation is then repeated until a satisfactory probable certainty of solution can be achieved.

By processing information using laws of quantum mechanics, quantum computers offer novel ways to perform computation tasks such as molecular calculations, optical photons, optimization, and many more. Many algorithms are introduced to perform such computational tasks efficiently. In particular, radio frequency digital to analog converters are valuable in a variety of applications, including wireless transmitters and implementing control pulses for qubits. There are few challenges with designs that use voltage mode representations for a signal path which includes high dynamic range requirements at block interfaces, leading to nonlinear behavior and generation of higher amplitude distortion products and independent power per block with no opportunity for power efficiency that comes from current reuse. Thus, embodiments herein propose an efficient current mode filter design in implementation of an integrated RF DAC solution to develop low-power distortion arbitrary waveform generation applications. This provides a path to reuse current between a filter and adjacent stages in a signal chain and avoid introducing additional current-voltage conversions in a signal path (e.g., such conversions may be included in a feedback path), which helps limit undesirable distortion products; and it also aligns well with low output amplitude requirements.

FIG.1illustrates a block diagram of an example system100that can access data and process that data using variable computing components depicted in accordance with one or more embodiments described herein. The system100can facilitate a process of assessing and identifying large amounts of various forms of data, using machine learning, and training a neural network or other type of model. The system100can also generate predictive recommendations to an individual level with context in accordance with one or more embodiments described herein. Aspects of systems (e.g., system100and the like), apparatuses or processes explained in this disclosure can constitute machine-executable component(s) embodied within machine(s), e.g., embodied in one or more computer readable mediums (or media) associated with one or more machines. Such component(s), when executed by the one or more machines, e.g., computer(s), computing device(s), virtual machine(s), etc. can cause the machine(s) to perform operations described herein. Repetitive description of like elements employed in one or more embodiments described herein is omitted for sake of brevity.

The system100facilitates an integrated radio frequency digital to analog converter (RFDAC) utilizing a current mode signal path. Embodiments relate to maintaining elements of a signal path, RFDAC, baseband filter, mirror, and an output stage. Benefits can be achieved by implementing an entire chain in current mode or implementing sub-elements of the chain in current mode.

System100can optionally include a server device, one or more networks and one or more devices (not shown). The system100can also include or otherwise be associated with a radio frequency digital to analog converter102operating in current mode which comprises a continuous-time baseband filter104operating in current mode wherein input and output of the system blocks are represented as currents. A mirroring component106mirrors the filtered current to an output108operating in current mode.

In an implementation, a current mode end-to-end path from radio frequency digital to analog converter through output108enables realization of low-power, low-distortion arbitrary waveform generation applications. The continuous-time baseband filter104comprises a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous time baseband filter generates a filtered current. The mirroring component106mirrors the filtered current to output108wherein it selectively changes a mirroring ratio to achieve a variable gain relative to a fine baseline step.

System100can be any suitable computing device or set of computing devices that can be communicatively coupled to devices, non-limiting examples of which can include, but are not limited to, a server computer, a computer, a mobile computer, a mainframe computer, an automated testing system, a network storage device, a communication device, a web server device, a network switching device, a network routing device, a gateway device, a network hub device, a network bridge device, a control system, or any other suitable computing device. A device can be any device that can communicate information with the system100and/or any other suitable device that can employ information provided by system100. It is to be appreciated that system100, components, models or devices can be equipped with communication components (not shown) that enable communication between the system, components, models, devices, etc. over one or more networks.

The various components of system100can be connected either directly or via one or more networks. Such networks can include wired and wireless networks, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), non-limiting examples of which include cellular, WAN, wireless fidelity (Wi-Fi), Wi-Max, WLAN, radio communication, microwave communication, satellite communication, optical communication, sonic communication, or any other suitable communication technology. Moreover, the aforementioned systems and/or devices have been described with respect to interaction between several components. It may be appreciated that such systems and components can include these components or sub-components specified therein, some of the specified components or sub-components, and/or additional components. Sub-components may also be implemented as components communicatively coupled to other components rather than included within parent components. Further yet, one or more components and/or sub-components can be combined into a single component providing aggregate functionality. The components can also interact with one or more other components not specifically described herein for the sake of brevity, but known by those of skill in the art.

The subject computer processing systems, methods apparatuses and/or computer program products can be employed to solve new problems that arise through advancements in technology, computer networks, the Internet and the like.

In today's digital world, one of the largest growth areas in electronics has been in applications of wireless communications. Modern radio frequency systems such as superconducting quantum bit controllers are based on wideband multi-channel architecture. The use of vector signal generators with IQ modulators and analog synthesizers for RF signal pose limitations due to its calibration complexity and cost. Thus, digital-to-analog converts are valuable to embody signal processing, modulation, and signal generation. Moreover, radiofrequency digital to analog converters (RF DACs) are valuable in a variety of applications, including wireless transmitters and implementing control pulses for qubits and address signal-to-noise ratio. In particular, RFDAC implementations ideally can target low distortion and while minimizing power consumption. In general, these objectives form a trade space that can be navigated in the course of design. Implementation of a RFDAC signal path can involve voltage mode signals, current mode signals, or a combination of both. Thus, embodiments propose a promising solution by introducing a current mode signal path design in an integrated digital to analog converter. An efficient current-mode filter offers multiple benefits in context of an end-to-end current mode analog signal path RFDAC architecture developed for low-power, low-distortion arbitrary waveform generation applications. It provides a path to reuse current between a filter and adjacent stages in a signal chain. It also avoids introducing additional current-voltage conversions in a signal path (e.g., such conversions may be included in a feedback path), which mitigates undesirable distortion products and aligns well with low output amplitude requirements.

FIG.2illustrates an example flowchart of an integrated radio frequency digital to analog converter utilizing a current mode transconductance-capacitance filter. As described in flowchart200, a system comprises a radio-frequency digital to analog converter (RFDAC) wherein a current-mode baseband filter is used. At202, a continuous-time baseband filter comprises a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole. At204, the continuous time baseband filter generates a filtered current. At206, a mirroring component selectively changes a mirroring ratio to achieve a variable gain relative to a fine baseline step. At208, a scaling component scales the input current of the feedback loop to facilitate coarse gains control. At210, a monitoring component monitors a scaled version of the input current to mitigate distortion interference with monitoring. A set of additional poles are placed between the continuous time baseband filter and the mirroring component facilitate high-order filtering and mitigate compromising the stability of the continuous time baseband filter. At212, a subset of the plurality of cascaded continuous time baseband filters provides low-pass, band-pass or high-pass characteristics with corner frequencies, quality factor, or gain control set by digital control. The output from this continuous time filter is current, and multiple such filters can be easily cascaded to realize higher order current mode filters. A filter can provide low-pass, band-pass, or high-pass characteristics, with the corner frequencies, quality factor, and gain steps set by digital control.

Wireless communication applications are challenging due to the speed and frequency-domain performance requirements of modern data converters. High speed digital to analog converters require fewer mixing and filtering stages to produce an effective output. Today's technological advancements face many challenges to meet increasing demand for bandwidth in a congested frequency spectrum. This increases signal chain complexity as frequency planning compromises size, power, and performance requirements. An ability to utilize a frequency spectrum creates enhanced user experiences and enables new system capabilities. Radio frequency converters are used to convert microwave signals into lower or higher frequency ranges for a wide range of processing options. Reducing size and cost of telecommunication and military systems is driving evolution of modern digital to analog converters to integrate more functionalities into a single chip. Certain high-speed digital to analog converters incorporate digital signal processing and conditioning functionalities such as filters, complex modulation, and numerically controlled oscillators. This enables direct generation of complex RF signals efficiently and compactly. In a traditional RFDAC architecture, information is processed from one frequency and translated to another frequency. Embodiments disclosed herein perform versatile signal processing at a low frequency and reduced power consumption.

FIG.3illustrates an example architecture of a radio frequency digital to analog converter (RFDAC) signal chain. One method to generate complex signals is to modulate a carrier signal frequency by a local oscillator using a vector modulator. In RF applications, baseband digital I and Q signals are generated using arbitrary waveform generators (AWG) which contain two or more synchronized digital to analog converters. An RFDAC chain architecture300has baseband digital BBI302and BBQ304signals. Multi-bit baseband digital to analog converters (DAC)306and308take digital bits and depending on bandwidth of a signal and sampling clock frequency, convert digital bits to an analog signal. This enables output of a current and provides a filtered and amplified current to mixers. Signals are processed through low pass filters306and308to reject an outer band noise component resulting from the digital to analog converter300. The filtered signals are mixed and thus upconverted, by mixers310and312, using two carriers (LO-Q and LO-I) having orthogonal phases 0 and 90 degrees for I and Q. Using a signal combiner311, the resulting signals are combined by creating a single side band signal representation. For example, if (x*y) function needs to be performed in a single side band representation, then variable x can be represented as a combination of 0 and 90 degrees and variable y can be represented as a combination of 0 and 90 degrees. These two variables can then be multiplied and added, similar to the scalar product of two vectors. An output of this function is processed through a driver DRV314. A matching network MN316is a component typically consisting of passive elements that do not provide distortions. The matching network316transfers resistance318(e.g., 50 ohms) to an impedance the driver requires, to maximize power transfer. An output320of these DACs is filtered, up-converted using I- and Q-channel mixers, and a resulting signal is combined and fed through a driver and matching network to a nominal load (e.g., 50 ohm) at output320. The filter implementation and the interface between the filter and the other elements of the signal chain are of significance in such designs. Continuous-time filters are well suited for high dynamic range, low power active filter implementations. Current mode signal processing is well suited for low distortion applications, as it reduces voltage swings at various nodes of interest. However, a traditional current mode input filter using an operational amplifier consumes significant amount of power and has limitations in high frequency applications. Continuous time gm-C filters typically provide a high input impedance, which leads to higher distortion products. A gm-C type filter is well suited for high frequency applications but is quite limited in terms of dynamic range it supports as an input is typically a voltage.

FIG.4illustrates an example block-level view architecture of a feedback based transconductance-capacitor baseband filter. Circuit architecture400has a DC power supply VDD402. The circuit400consists of a buffer BUF403and a high impedance Z404that provides output impedance from the load transistors. There are two transconductance blocks gm1410and gm2412. The two capacitance C1406and C2408with arrows show that C1and C2can be controlled together or independently. The ratio of the transconductances and the capacitors determine the quality factor of the filter. Current bleeder IBLD416is a current helper that provides different biasing such that the current taken by gm1410and the buffer BUF403can be different. A feedback loop would be the path through gm2, Z, BUF, gm1and it employs the following equation:

Q=gm1⁢c2gm2⁢c1
wherein Q is quality factor and it is a ratio of similar quantities, nearly constant over Process (P), Temperature (T) variations. Q factor can be varied by programming gm1, gm2, C1, C2using digital control. The feedback loop gain reduces distortion and bandwidth BW can be derived by employing the following equation:

B⁢W=12⁢⁢Π⁢gm⁢1⁢gm2C1⁢C2
A biasing strategy can be a sub-claim that optimizes performance wherein it biases from constant gmbias block and bias from 1/R bias (e.g., keeps filter poles tracking). A continuous-time baseband filter uses input current and provides an output current, and internal feedback mechanisms are carried out as a combination of current to voltage and voltage to current conversion. The feedback loop uses at least one high impedance node and at least one low impedance node, where the high impedance node provides a dominant pole, and the low impedance node provides a non-dominant pole. Pole splitting ensures stability, and biasing provides substantially constant separation between the dominant and the non-dominant poles to maintain adequate phase margin. The loop uses a mirroring device to mirror the filtered current to an output, and, by changing mirroring ratio, variable gain can be achieved to a fine baseline step. Coarse gain control can be achieved by scaling input current inside the feedback loop, and this auxiliary path can also be used as a path to monitor a scaled version of the input current without additional distortion. Additional poles can be placed between filter core stage and mirroring stage to achieve higher order filtering without compromising stability of the filter. This additional pole does not consume current and does not create distortion, and can be implemented using a resistor and capacitor. Output from this continuous time filter is a current, and multiple such filters can be easily cascaded to realize higher order current mode filters. A filter can provide low-pass, band-pass, or high-pass characteristics, with corner frequencies, quality factor, and gain steps set by digital control.

FIG.5illustrates an example transistor level drawing of a single ended implementation of filter500. The example embodiment is one of the construction methods of the filter. Transistors MPB502or MN1504can implement a DC offset compensation DAC. The filter500has a current mode input/output gm-C filter. A common mode of the input current506is set and the output current508is programmed via MNMXusing drain/gate/source switching elements. This is a negative feedback loop that consists of MNC1510and MN2512then MN1504wherein the three transistors are inside the loop. The other two transistors MPB502and MNB514are PMOS and NMOS bias transistors respectively. The baseband filter has a current mode input along with a negative feedback loop. The feedback loop consists of two capacitors C1516and C2518. C1516is associated with the dominant pole which is where node C1is connected and C2518is associated with a non-dominant pole. The feedback loop is connected to one dominant pole and one non-dominant pole. In this way, it provides room to optimize for phase margin and stability purposes. The dominant pole is formed by output conductance of transistors and the non-dominant pole is formed by transconductance of transistors. The third pole is with resistance R520and an input capacitance of device MNMX522. This provides three poles and the third pole can be realized without any additional consumption of current. The output is also a current iout508and it provides a filtering function and a gain function wherein gain is denoted by iout/iin. This filter500provides simultaneously the possibility of a lowpass or bandpass transfer function. By using current waveforms associated with iout/iin, a transfer function can be derived wherein it is a low pass response. Else, the transfer function of the current can be derived by i(MNC1)/iin, wherein it would be a bandpass response. Thus, this filter500provides both responses simultaneously; it has two poles which are complex conjugates of one another and a real pole that is formed outside the loop is given by resistance and input capacitance of MNMX. I1524and I2526which are digitally programmable using current mirrors via VP530and VN2532nets. MNC2528is used as an attenuator to handle input dynamic range. This is one representation of an example structure. If NMOS is turned into PMOS, then that could be another example representation.

FIG.6illustrates another example transistor level drawing of a single ended implementation of a filter architecture600that has a DC power supply VDD602. The filter600consists of two transistors MP1604and MP2608. Z1606and Z2610represent capacitors associated with dominant pole and non-dominant poles. Z1606and Z2610can be represented using series and parallel combination of at least one reactive element (e.g., capacitance, inductance). This feedback loop consists of transistors MPC1612, MP2604, MP1608that provide negative feedback using current mode signaling. A transfer function of variables of low pass and high pass filter HLPand HHPcan be represented by:

HLP⁡(s)=iout,LPii⁢⁢n=-α⁡(gm⁢⁢1⁢gm⁢⁢2C1⁢C2){s2+s⁡(gm⁢⁢2C2)+(gm⁢⁢1⁢gm⁢⁢2C1⁢C2)}HHP⁡(s)=iout,HPii⁢⁢n=s2+s⁡(gm⁢⁢2C2){s2+s⁡(gm⁢⁢2C2)+(gm⁢⁢1⁢gm⁢⁢2C1⁢C2)}
wherein gm1and gm2represent transconductances of transistors MP1604and MP2608. Iin, ioutrepresent input and output current and capacitance is represented as C1and C2. HP and LP represent low-pass and high-pass filters. α represents ratio between the two transistors MPMY614and MP1604, respectively. Poles are formed by a ratio of Gmtransconductance and capacitance, and a bias can be provided such that Gmcan be constant where Gmand C can be calibrated independently or can also be biased wherein it tracks Gm/C by itself. The biasing along with the filter600holds a unique place as well. The transistors MPMY614and MP1604can be biased in sub-threshold or in strong impulsion wherein one transistor can be sub-threshold and the other transistor can obtain strong impulsion. Similar permutation and combinations can be made with the transistors as described in the example above.

FIG.7illustrates another example transistor level drawing of an alternate filter arrangement of embodiments. There are many implementation combinations of the baseband filter and these embodiments propose one of such implementation methods. As shown in the illustration700A, gmrepresents the transconductance of the transistor and C represents the capacitor. The architecture700A has a DC power supply VDD702. In this configuration, impedance Z2706is associated with the dominant pole, and Z1704is associated with the non-dominant pole. Also, this configuration uses positive feedback using current mode signaling. Another example of embodiment is shown in the illustration700B. In this configuration, the impedance Z2708is coupled between the gate and the drain terminals of MP1710. This leads to a smaller size pole and Z1712is associated with the non-dominant pole. This configuration also uses positive feedback using current mode signaling.

FIG.8illustrates another example transistor level drawing of an alternate filter arrangement of a sample embodiment. There are many implementation combinations of the baseband filter and these embodiments propose one of such implementation methods. As shown in the illustration800A, the impedance Z2804is associated with the dominant pole and Z1802is associated with the non-dominant pole. This configuration uses negative feedback using current mode signaling. Similarly, the architecture shown in800B illustrates that additional current mode signaling leg is introduced within the feedback loop (MN1″806and Z3808). Depending on the signal scaling and polarity, the filter order can be increased.

FIG.9illustrates another example transistor level drawing of an alternate filter arrangement of embodiments. There are many implementation combinations of the baseband filter and these embodiments propose one of such implementation methods. As shown in the illustration900A, this configuration has impedance Z2902which is associated with the dominant pole and Z1904is associated with the non-dominant pole. This configuration uses negative feedback using current mode signaling. The impedance Z3906is inserted within the loop to achieve higher order filtering and consists of at least one passive element and Z3906can be placed at the gate of MN2904. Similarly, the illustration shown in900B has additional impedances wherein impedance Z2908is associated with the dominant pole and Z1910is associated with the non-dominant pole. This configuration uses positive feedback using current mode signaling.

FIG.10illustrates an example transistor level drawing of a differential filter transfer function of a sample embodiment. There are many implementation combinations of the baseband filter and these embodiments propose one of such implementation methods. As shown in the illustration1000A, this configuration has impedance Z21002is associated with the dominant pole and Z11004is associated with the non-dominant pole. This schematic diagram is a differential filter wherein the transistors are transferred to the differential side1006. In addition, the illustration shown in1000B is configured wherein impedance Z21008is associated with the dominant pole and Z11010is associated with the non-dominant pole. The additional series impedance at the input terminal leads to neutralization and can reduce the loading to the driving circuit. A neutralization network consists of at least one passive element.

A novelty of these embodiments is to use a current mode gm-C continuous time filter. This methodology can realize two poles inside a feedback loop. The feedback loop can realize a complex pair of poles. The feedback provides linearization leading to low distortion. A real pole is realized outside the loop. Moreover, the variable gain is implemented by using a plurality of current mirroring elements, and M out of N elements are enabled to implement the desired output current. The current can be shared between the mixer and the baseband filter output stage which reduces power. Three poles can be realized while incurring distortion of only one trans conductor stage. This concept can be extended by a seamless cascade of multiple current mode filter with common mode compatibility. The input stage can be shared with the previous stage output to further reduce power consumption. The output stage can be shared with the next stage input to further reduce power consumption. Complex filter implementation can be realized using delayed signals from I and Q.

FIG.11illustrates an example of simulation results of the current mode transconductance-capacitance filter. The simulation shows the frequency response1102at 3 dB cut-off frequency. The intermodulation results1104show the results that vary based on the frequency spectrum on the x-axis. The loop stability based on the varying frequency spectrum1106and the resulting output noise of this baseband filter1108. These simulations determine that this type of current mode baseband filter is necessary for the overall requirement of the right controller block in the quantum application. This can also be used in a generic sense for any transmitter such as a radio transmitter. The output results and intermodulation results show that this filter provides a path to current reuse between the filter and any adjacent stages in the signal chain. It avoids introducing additional current-voltage conversions in the signal path which helps limit undesirable distortion products. It also aligns well with low output amplitude requirements.

FIG.12illustrates an example of schematic extension of an array-based system. As shown in the illustration1200, the input is fed with baseband signals I and Q represented as BBI11202and BBQ11204. This can also be extended to n signals BBIN1206and BBQN1208. In this flow, the filter element is shared among multiple channels. With input and output as current, the current is taken from one filter to another filter1210and1212. Addition or subtraction1214can also be performed with any of these interfaces in the simplest way to produce an output1216with 50-ohm resistance. Another set of applications can also be performed wherein one filter in an array, one filter in a low pass construct and another filter with a band pass response can be used. Through this way, it provides different types of signals to different sensors or qubits. Higher order filtering can be realized by cascading a plurality of filters with common mode compatibility. Also, low distortion polyphase filtering can be implemented by cross-coupling quadrature phase filters.

FIG.13illustrates an example schematic of a cascaded extension of complementary stages. The illustration in block1300shows how cascades can be made wherein the filter1302is a 3rdorder filter but it can only consume current for 2ndorder filter. This can cause it to be in a loop. The output of an NMOS stage is directly coupled1304to the input of a PMOS stage1306. The filter shown in this illustration is a 3rdorder filter and the cascade is 6thorder resulting in using minimum power consumption and low distortion. This illustration is shown in a single-phase system, but loop construction can be made differential as well. The filter1306is also a 3rdorder filter and two similar filters can be used to construct high order filter without any loss of the dynamic range and thus it makes it simple to cascade these two filters. In the prior embodiments, the OTA based transimpedance filter was commonly used in wireless systems. This filter typically uses shunt-shunt feedback however the gain-bandwidth requirements lead to high power consumption. Both low and band-pass transfer function can be realized. This proposed structure can work with only one high impedance node in the feedback loop for a biquadratic function. It is compact due to a lack of resistor. The open loop cascade structure with common gate input is used in some cases and typically with a current to voltage converter. This proposed structure uses feedback to realize two complex poles thereby leading to two real poles. This has limited the reliability of the filter transfer function.

The current mode solution offers a path to reuse current and low distortion that is well-tuned to the requirements of cryogenic waveform generation. A novelty of these embodiments is in the use of the transconductance-capacitor filter (gm-C). The main contribution is the realization of a gm-C filter that provides low input impedance. The traditional gm-C filters have high input impedance and typically provide input voltage to output voltage transfer function. The implementation in commercially available CMOS technologies is entirely feasible. This circuit approach is valuable for implementing CMOS control pulse generation analog circuits to enable enhanced scalability of future quantum computing systems.

To provide a context for the various aspects of the disclosed subject matter,FIG.14as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented.FIG.14illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

With reference toFIG.14, a suitable operating environment1400for implementing various aspects of this disclosure can also include a computer1412. The computer1412can also include a processing unit1414, a system memory1416, and a system bus1418. The system bus1418couples system components including, but not limited to, the system memory1416to the processing unit1414. The processing unit1414can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit1414. The system bus1418can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

The system memory1416can also include volatile memory1420and non-volatile memory1422. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer1412, such as during start-up, is stored in non-volatile memory1422. Computer1412can also include removable/non-removable, volatile/non-volatile computer storage media.FIG.14illustrates, for example, a disk storage1424. Disk storage1424can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flash memory card, or memory stick. The disk storage1424also can include storage media separately or in combination with other storage media. To facilitate connection of the disk storage1424to the system bus1418, a removable or non-removable interface is typically used, such as interface1426.FIG.14also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment1400. Such software can also include, for example, an operating system1428. Operating system1428, which can be stored on disk storage1424, acts to control and allocate resources of the computer1412.

System applications1430take advantage of the management of resources by operating system1428through program modules1432and program data1434, e.g., stored either in system memory1416or on disk storage1424. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer1412through input device(s)1436. Input devices1436include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit1414through the system bus1418via interface port(s)1438. Interface port(s)1438include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s)1440use some of the same type of ports as input device(s)1436. Thus, for example, a USB port can be used to provide input to computer1412, and to output information from computer1412to an output device1440. Output adapter1442is provided to illustrate that there are some output devices1440like monitors, speakers, and printers, among other output devices1440, which require special adapters. The output adapters1442include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device1440and the system bus1418. It is to be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s)1444.

Computer1412can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s)1444. The remote computer(s)1444can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer1412. For purposes of brevity, only a memory storage device1446is illustrated with remote computer(s)1444. Remote computer(s)1444is logically connected to computer1412through a network interface1448and then physically connected via communication connection1450. Network interface1448encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s)1450refers to the hardware/software employed to connect the network interface1448to the system bus1418. While communication connection1450is shown for illustrative clarity inside computer1412, it can also be external to computer1412. The hardware/software for connection to the network interface1448can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

Referring now toFIG.15, an illustrative cloud computing environment1550is depicted. As shown, cloud computing environment1550includes one or more cloud computing nodes1510with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone1554A, desktop computer1554B, laptop computer1554C, and/or automobile computer system1554N may communicate. Although not illustrated inFIG.15, cloud computing nodes1510can further comprise a quantum platform (e.g., quantum computer, quantum hardware, quantum software, etc.) with which local computing devices used by cloud consumers can communicate. Nodes1510may communicate with one another. It may be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment1550to offer infrastructure, platforms and/or software as services for which a cloud consumer does not need to maintain resources on a local computing device. It is understood that the types of computing devices1554A-N shown inFIG.15are intended to be illustrative only and that computing nodes1510and cloud computing environment1550can communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).

Referring now toFIG.16, a set of functional abstraction layers provided by cloud computing environment1550(FIG.15) is shown. It should be understood in advance that the components, layers, and functions shown inFIG.16are intended to be illustrative only and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

Hardware and software layer1660includes hardware and software components. Examples of hardware components include: mainframes1661; RISC (Reduced Instruction Set Computer) architecture-based servers1662; servers1663; blade servers1664; storage devices1665; and networks and networking components1666. In some embodiments, software components include network application server software1667, quantum platform routing software1668, and/or quantum software (not illustrated inFIG.16).

Virtualization layer1670provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers1671; virtual storage1672; virtual networks1673, including virtual private networks; virtual applications and operating systems1674; and virtual clients1675.

In one example, management layer1680may provide the functions described below. Resource provisioning1681provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing1682provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal1683provides access to the cloud computing environment for consumers and system administrators. Service level management1684provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment1685provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.

Workloads layer1690provides examples of functionality for which the cloud computing environment may be utilized. Non-limiting examples of workloads and functions which may be provided from this layer include: mapping and navigation1691; software development and lifecycle management1692; virtual classroom education delivery1693; data analytics processing1694; transaction processing1695; and quantum state preparation software1696.