Schematic generation visualization aid for netlists comprising analog circuits

The invention concerns the generation of schematics from analog netlists. Various implementations of the invention provide that an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.

FIELD OF THE INVENTION

The invention relates to the field of electronic design automation. More particularly, various implementations of the invention are applicable to generating schematics from an analog netlist description of a circuit.

BACKGROUND OF THE INVENTION

Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).

Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit, i.e. that the logical design conforms to the specification. This analysis is sometimes referred to as “formal verification.”

After the logical design is verified, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed, often mathematically, to confirm that the circuit described by the device design conforms to the logical design, and as a result, the specification. This analysis is also sometimes referred to as formal verification.

Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. This type of design often is referred to as a “layout” design. The layout design is then used as a template to manufacture the integrated circuit. More particularly, the integrated circuit devices are manufactured, by for example an optical lithographic process, using the layout design as a template.

As indicated above, device designs may often be in the form of either a schematic or a netlist. As those of skill in the art can appreciate, a netlist details the parts, often referred to as hardware components, which make up a device design. In addition to listing the hardware components included in a device design, a netlist details the connectivity of the device design. Netlists are typically text based, and is often quite literally a list of the components and connections between the components of the device design.

Due to the complexity of modern electronic device designs, a device is not easily visualized by the designer from the netlist alone. As a result, tools are available that generate a schematic from a netlist. However, with the growing complexity of modern designs it has become increasing difficult to generate a schematic from a netlist that is “useful” to the designer. This is particularly true where the netlist includes hardware components that are transistors. One difficulty in generating a “useful” schematic is that often the generated schematic is not deterministic. That is, two netlists referencing the same hardware components and connectivity, but having a different sequence of listing the hardware components in the netlist will result in two different schematics.

Another difficulty in generating “useful” schematics is that prior art schematic generation tools often generate schematics that are not comparable to a manually drawn schematic. For example, in a manually drawn schematic, designers will often place a number of transistors that combined form a particular logic function near each other in such a manner that the logic function may be easily recognizable to a designer viewing the schematic. Additionally, components should “ideally” be organized so that the flow of current and the flow of signals through the schematic is apparent and that there are a minimum of bends and crossovers in the wires connecting various components.

SUMMARY OF THE INVENTION

Implementations of the invention provide methods and apparatuses for generating a schematic from an analog netlist. In various implementations of the invention, an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.

With various implementations of the invention, the netlist is partitioned into component groups by identifying hardware components that combined form a logic function, such as for example two transistors forming the AND function, forming a component group corresponding to the identified hardware components, and replacing the identified hardware components in the netlist with the component group. Subsequently, the components groups, and corresponding hardware components may be arranged, lines routed between the component groups, and a schematic generated based upon the arranged hardware components.

These and additional implementations of the invention will be further understood from the following detailed disclosure of illustrative embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE IMPLEMENTATIONS

Although the operations of the disclosed techniques are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Additionally, the detailed description sometimes uses terms like “determine” to describe the disclosed techniques. Such terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms may vary depending on the particular implementation.

Some of the techniques described herein can be implemented by software stored on one or more computer readable storage medium and executed on a computer. Additionally, some of the disclosed techniques may be implemented as part of a computer implemented electronic design automation (EDA) tool. The selected techniques could be executed on a single computer or a computer networked with another computer or computers. For clarity, only those aspects of the tools or computer germane to the disclosed techniques are described; product details well known in the art may be omitted.

Illustrative Computing Environment

As stated, various examples of the invention may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly,FIG. 1shows an illustrative example of a computing device101. As seen in this figure, the computing device101includes a computing unit103with a processing unit105and a system memory107. The processing unit105may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory107may include both a read-only memory (ROM)109and a random access memory (RAM)111. As will be appreciated by those of ordinary skill in the art, both the read-only memory109and the random access memory111may store software instructions for execution by the processing unit105.

The processing unit105and the system memory107are connected, either directly or indirectly, through a bus113or alternate communication structure, to one or more peripheral devices. For example, the processing unit105or the system memory107may be directly or indirectly connected to one or more additional memory storage devices115. The memory storage devices115may include, for example, a “hard” magnetic disk drive, a solid state disk drive, an optical disk drive, and a removable disk drive. The processing unit105and the system memory107also may be directly or indirectly connected to one or more input devices117and one or more output devices119. The input devices117may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices119may include, for example, a display device, a printer and speakers. With various examples of the computing device101, one or more of the peripheral devices115-119may be internally housed with the computing unit103. Alternately, one or more of the peripheral devices115-119may be external to the housing for the computing unit103and connected to the bus113through, for example, a Universal Serial Bus (USB) connection or a digital visual interface (DVI) connection.

With some implementations, the computing unit103may also be directly or indirectly connected to one or more network interfaces cards (NIC)121, for communicating with other devices making up a network. The network interface cards121translate data and control signals from the computing unit103into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface cards121may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection.

It should be appreciated that the computing device101is illustrated as an example only, and it not intended to be limiting. Various embodiments of the invention may be implemented using one or more computing devices that include the components of the computing device101illustrated inFIG. 1, which include only a subset of the components illustrated inFIG. 1, or which include an alternate combination of components, including components that are not shown inFIG. 1. For example, various embodiments of the invention may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

Illustrative Netlist and Device Design

As stated above, a netlist details hardware components and the interconnectivity between the hardware components that make up a device design.FIG. 2illustrates a netlist201. As can be seen from this figure, the netlist201is a text file that lists various hardware components and the connectivity between the hardware components that make up the device design entitled “Common-Base BJT Amplifier”. As can be further seen from this figure, the device design includes voltage sources V1and V2, resistors R1and R2and a transistor Q1. Each time a hardware component is referenced in a netlist, a name, such as for example V1, is used to identify the component. Additionally, the connectivity (often referred to as “nets” or “nodes”) of the components are defined. For example, the nodes for the component V1are listed as 0 and 1. Accordingly, the component V1is connected to the 0thand 1stnodes. Those of skill in the art can appreciate, that various standards and formats for netlists exist, such as for example the electronic design interchange format (EDIF).

Based upon the listed hardware components and their node connections, a corresponding schematic may be drawn.FIG. 3illustrates a schematic301that corresponds to the netlist201. As can be seen from this figure, the schematic301includes voltage sources V1and V2, resistors R1and R2as well as the transistor Q1. Additionally, the nodes or connectivity of the hardware components is also represented by the schematic301. For example, with respect to the hardware component R1, it is defined by the netlist201as having a resistance value of 800 ohms and being connected to nodes1and2, which is represented in the schematic301. Those of skill in the art can appreciate that the netlist201and the corresponding schematic301are a simple example of a device design. In practice modern device designs include thousands or more components. Accordingly, modern netlists are significantly more complex than the netlist201. As a result, generating a schematic is also more complex. As stated above, generating a schematic that is useful to a designer can be even more difficult.

Schematic Generation from a Netist

FIG. 4illustrates a method401for generating a schematic from an analog netlist according to various implementations of the present invention. As can be seen from this figure, the method401includes an operation403for initializing a netlist405. The method401further includes an operation407for partitioning the netlist405into component groups. More particularly, the operation407groups the hardware components listed in the netlist405into smaller collections of hardware components, referred to herein as component groups. Additionally, an operation409and an operation411are included for arranging the component groups and routing connections between the component groups respectively. Further still, an operation413and an operation415for arranging the hardware components within each component group and routing connecting between these hardware components is provided. Subsequently, as can be seen from this figure, an operation417is provided for generating a schematic419that corresponds to the netlist405.

Netlist Initialization

In various implementations of the invention, the operation403initializes the netlist405according to the method501shown inFIG. 5. As can be seen from this figure, the method501includes an operation503for identifying the analog components (i.e. resistors, capacitors, and transistors) within the netlist405, an operation505for sorting the analog components, an operation507for identifying selected nodes within the netist405, and an operation509for processing power and ground connected transistors within the netlist405. With some implementations, the operation505sorts the analog components based upon their name, such as for example, sorting the component in alphabetical order. Sorting the components results in a schematic that is deterministic. More particularly, due to sorting, schematics generated for two netlists having the same hardware components and connectivity will look the same irrespective of the ordering of the components within the netlist.

As stated, the operation507identifies selected nodes within the netlist405. In various implementations, the operation507identifies those nodes connected to power and ground, often referred to as power and ground nodes respectively. With some implementations, the operation507identifies those nodes connected to multiple hardware components. These nodes are often referred to as “bulk” nodes. In still various implementations, the operation507identifies the power, ground, and bulk nodes.

The operation509is provided for processing power and ground connected transistors within the netlist405. In various implementations of the invention, transistors that have their “drain” port connected to power or transistors that have their “source” port connected to ground are identified. Subsequently, the operation509may “flip” the ordering of the connections of these identified transistors. For example, for those components having their “drain” pins connected to power, the operation509may reverse the transistors pins such that the functioning and connectivity of the design is preserved, but a schematic generated from these reversed connections conforms to preferred practices.

Referring back toFIG. 4, as described, the method401includes the operation407for partitioning the netlist405. In various implementations of the invention, the operation407partitions the netlist405according to the method601illustrated inFIG. 6. As can be seen from this figure, the method601includes an operation603for identifying a group of hardware components from the netlist, which combined form a known circuit, and an operation605for forming a component group from the identified hardware components. The method601further includes an operation607for appending the component group to the netlist, an operation609for identifying a group of components from the netlist that combined form a known circuit, and an operation611for forming a component group from the identified components. As seen in this figure, if a grouping is identified by the operation609, the operation611is processed, and the method returns to the operation607for appending the component group to the netlist and proceeding to identify an additional group of components that form a known circuit (i.e. by the operation609). As illustrated, in various implementations, the method601may recursively processes the netlist to combine components within the netlist into “larger” component groups that represent certain known circuits, until no more combinable elements are identified.

In various implementations of the invention, the operation603or the operation609may identify a group of transistors connected either in series or parallel, which combined represent a logic function. For example,FIG. 7illustrates a circuit701, which includes transistors703and705, inputs707and709, and an output711. As can be seen form this figure, the transistors703and705are connected in series, which as those of skill in the art can appreciate, forms the logic function711=!(707&709) and is often represented by a NAND gate. Accordingly, transistors703and705may, in various implementations, be identified by the operation603or the operation609and subsequently included into a component group by the operation605or the operation611. With some implementations of the invention, the known circuit forms an OR gate. Accordingly, transistors connected in parallel, which as those of skill in the art can appreciate, may form an OR gate, may be identified and subsequently formed into a component group. In further implementations, the known circuit forms other gates, such as for example, an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, and a XNOR gate.

With various implementations of the invention, the operation603or the operation609may identify components where the output of the first is the input to the second. This configuration is often referred to as a cascade circuit. More particularly, transistors or component groups that are connected to the gate of another transistor or component group and also connected to the common node will be represented together. For example,FIG. 8illustrates a circuit801, which includes transistors803,805, and807, and resistors809and811. As can be seen from this figure, the transistors805and807are connected in “cascade” with the transistor803. Accordingly, in various implementations of the invention, these transistors may be identified and grouped into component groups by the method601.

With still various implementations of the invention, the operation603or the operation609may identify a group of components connected in series, where the source and the drain ports of the components are serially connected to an output. For example,FIG. 9illustrates a circuit901that includes transistors903through909. As can be seen from this figure, the transistors903and905have their source and drain respectively, serially connected to an output as do the transistors907and909. Accordingly, with various implementations, the transistor groups903and905and well and907and909may be identified and component groups may be formed for each set of identified transistors.

In some implementations of the invention, the operation603or the operation609may identify a group of components where the drain pins of a PMOS device and an NMOS device are connected and the source pins of the PMOS device and the NMOS device are connected and the input at the gate of these two devices is different. This configuration is referred to herein as a transmission gate. For example,FIG. 10illustrates a circuit1001, having a PMOS transistor1003and an NMOS transistor1005, as well as an input1007and an output1009. As can be seen from this figure, the PMOS device and the NMOS device have their source and drain pins connected, yet their gates are connected to different inputs. Accordingly, in various implementations, the transistors1003and1005may be identified and a component group formed that includes these transistors.

Illustrative Example of Netlist Partitioning

As described above, in various implementations of the invention, a netlist, such as for example the netlist201, may be partitioned into component groups, by for example the method601.FIG. 11throughFIG. 15illustrate an example of partitioning a netlist into component groups. Although reference is made herein to a netlist,FIGS. 11though15illustrate the netlist graphically, in schematic form, for clarity of presentation and for purposes of visualizing the component groups.

FIG. 11illustrates a netlist1101, as can be seen from this figure, a number of hardware components1103, such as for example, the transistor P5, the inverter I1, and the capacitor C, are included in the netlist1101. As can be appreciated from this figure, the connectivity between the hardware components1103is apparent. However, the logical functions represented by this circuit are not apparent.

As stated above, components may be identified and grouped according to various known circuits, such as for example the AND circuit. In various implementations of the invention, a number of hardware components may be identified and grouped into component groups because they combined form known circuits. More particularly, the component groups [P1, P2], [P3, P5], [M4, M5], [M1, M3], [P6, P7, P8], [P9, P10, P12], [M10, M11, M12], and [M6, M8, M9] may be created because they perform a logic function, specifically either the AND or OR function. Additionally, the transistor P11and the capacitor C may be included in a component group because they form a cascade grouping. These component groups may then be appended to the netlist. A netlist including these appended component groups is illustrated inFIG. 12. As can be seen from this figure, the hardware components included in each component groups have been replaced by the component group itself.

With various implementations of the invention, the netlist represented inFIG. 12may be further partitioned. For example, the following components may be identified and included in component groups, [[P3, P5], P4], [[M4, M5], M2], [[P9, P10, P12], [P11, C]] and [[M10, M11, M12], M7]. This further partitioning of the netlist is represented inFIG. 13. As can be seen fromFIG. 12andFIG. 13, a component group may be comprised of either hardware components, component groups, or a combination of both. AsFIG. 14illustrates, still further partitioning is possible. As can be seen fromFIG. 14, the component groups [P1, P2, P3, P4, P5], [M1, M2, M3, M4, M5], [P6, P7, P8, P9, P10, P11, P12, C] and [M6, M7, M8, M9M10, M11] may be formed.

Furthermore, component groups [[P1, P2, P3, P4, P5], [M1, M2, M3, M4, M5]] and [[P6, P7, P8, P9, P10, P11, P12, C], [M6, M7, M8, M9M10, M11]] may be identified as these components form driver blocks. As a result, a component group may be formed for each of these pairs of component groups. The resulting netlist is shown inFIG. 15. As can be seen from this figure, two component groups and the connectivity between the component groups is shown.

Component Group Placement and Routing

Referring back toFIG. 4, the method401for generating a schematic from a netlist includes operations for partitioning the netlist, arranging the partitioned components and routing connections between the partitioned components. More particularly, the operation409is provided for arranging the component groups, such as for example, the component groups shown in the netlists ofFIGS. 12 through 15.

FIG. 16illustrates a method1601for arranging component groups within a schematic. With various implementations of the invention, the operation409may arrange the components according to the method1601. As can be seen from this figure, the method1601includes an operation1603for forming grid based framework. In some implementations, the grid is formed by crossing horizontal and vertical lines, which may be referred to as columns and rows. The method1601further includes an operation1605for assigning each component group to a particular column in the grid according to a placement algorithm. For example, in various implementations, a depth-first search (DFS) algorithm may be used to identify each component group and assign columns to these components based upon their relative locations to each other.

The method1601additionally includes an operation1607for assigning each component group to a particular row in the grid. In various implementations, the operation1607applies a min-cut algorithm, followed by a simplex algorithm to vertically level the components within each column. The min-cut algorithm is described in detail in an article entitled An Efficient Heuristic Procedure for Partitioning Graphs, Bell Systems Technical Journal, 49(2), pp. 291-308, 1970, and authored by B. Kernighan and S. Lin, which article is incorporated entirely herein by reference. In various implementations of the invention, the operation1607arranges the component groups such that a minimum of node crossings and a minimum length of connections between nodes are achieved.

Returning toFIG. 4, the method401includes the operation411for routing connections between the component groups. In various implementations of the invention, the operation411routes connections between the component groups according to a left edge algorithm. The left edge algorithm is discussed in greater detail in an article entitledEfficient Algorithms For Channel-Routing, IEEE Transactions on CAD of ICs and Systems, CAD Vol. 1, January 1982, pp 25-35, and authored by Yoshimara and Kuh, which article is incorporated entirely herein by reference.

As indicated byFIG. 4, in various implementations of the invention, once the component groups are arranged and connections have been routed between them, the placement of hardware component within the component groups may be done. The operation413may arrange the hardware components from top to bottom in component group based upon current flow from power to ground. More particularly, with some implementations of the invention, the hardware components directly connected to power may be placed higher up in the column and row locations corresponding to the component group. Then hardware component connected to these power connected component may be placed next, proceeding down to the ground connected components, which will be placed lowest in the column and row locations corresponding to the component group. In various implementations of the invention, a fixed horizontal and vertical spacing is maintained between components.

In various implementations, the operation415for routing connections between the hardware components, routes connections such that symmetry within the component group is maximized.FIG. 17illustrates a schematic1701that has been generated according to various implementations of the present invention. The schematic1701corresponds to the netlist1101ofFIG. 11. As those of skill in the art can appreciate, the schematic1701conveys more information to a designer than does the netlist1101.

Apparatus for Schematic Generation from an Analog Netlist

FIG. 18illustrates a schematic generation tool1801. As can be seen from this figure, the schematic generation tool1801includes a netlist initialization module1803, a netlist partitioning module1805, a placement module1807, and a routing module1809. In various implementation of the invention, the schematic generation tool1801implemented as software executable by a computer.

In various implementations of the invention, the module1803is configured to access a netlist, and initialize the netlist, such as for example, by the method503shown inFIG. 5. With some implementations, the module1805is configured to partition the module according to the method601illustrated inFIG. 6. Still, in some implementations, the modules1807and1809may arrange and route connections between components, such as for example as described by reference toFIGS. 4 and 16. As can be seen fromFIG. 18, the modules1803-1809are connected by a bus1811.

CONCLUSION

Methods and apparatuses for generating a schematic from an analog netlist have been described. Particularly, as described by reference to various implementations of the invention, an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. Following which, the hardware components corresponding to each component group are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.

In various implementations of the invention, the netlist is partitioned into component groups by identifying hardware components that combined form a logic function, such as for example two transistors forming the AND function, forming a component group corresponding to the identified hardware components, and replacing the identified hardware components in the netlist with the component group. Subsequently, the components groups, and corresponding hardware components may be arranged, lines routed between the component groups, and a schematic generated based upon the arranged hardware components.

Although certain devices and methods have been described above in terms of the illustrative embodiments, the person of ordinary skill in the art will recognize that other embodiments, examples, substitutions, modification and alterations are possible. It is intended that the following claims cover such other embodiments, examples, substitutions, modifications and alterations within the spirit and scope of the claims.