Level shifter without DC current flow

A level shifter has a current mirror and a set of oppositely driven NMOS switch. A voltage holding module is added to help an output of the level shifter to work with a full-swing fashion. Additionally, a DC current switch is used to eliminate a DC current.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a level shifter, and more particularly, to a CMOS level shifter without DC current flow.

2. Description of the Prior Art

With advanced complementary metal oxide semiconductor (CMOS) technology, more and more circuits are integrated into a single chip. Therefore, the issue for heat dissipation of the chips is important. A simple way to reduce the heat is to decrease the working voltage of the chips. However, to increase the noise margin and avoid the noises from the external environment, the I/O circuits of the chips are usually applied higher voltage than the kernel circuits. Therefore, most of the chips are applied two working voltages. Level shifters, hence, are necessary to translate signals between two voltage supply domains.

Please refer toFIG. 1, which is a circuit diagram of a level shifter70according to the prior art. The level shifter70is used to translate signals between two voltage supply domains and has a current mirror structure. The level shifter70has an inverter2, a current mirror10, and a switch module20. The inverter2outputs an inverted signal by inverting an input signal from an input node1. The operation of the switch module20is controlled by the input signal from the input node1and the inverted signal from the output of the inverter2. The current mirror10is composed of two gate-coupled PMOS transistors111and12. The gate of the PMOS transistor11is further coupled to the drain of the PMOS transistor11. The current mirror10is controlled by the two nodes3and4. The switch module20comprises two NMOS transistors21and22. The drains of the two NMOS transistors are respectively coupled to the node3and the node4, and the gates of the two NMOS transistors are respectively biased by the input signal from the node1and the inverted signal from the output of the inverter2. When the voltage level of the input signal from the node1is pulled up from the grounded level to VDDAL, the NMOS transistor21is turned on and the NMOS transistor22is turned off. In such case, the NMOS transistor21can be taken as a small resistor. According to Ohm's law, the current flows through the NMOS transistor21is equal to (VDDAH−|VGS|)/R, where VGS is the voltage difference between the gate and the source of the PMOS transistor11, and R is the equivalent turn-on resistance of the NMOS transistor21. The current flowing through the NMOS transistor21is mirrored to the PMOS transistor12of the current mirror10so that the voltage levels of the node4and an output terminal9are pulled up to VDDAH. If the voltage level of the node1keeps at VDDAL, the level shifter70generates a DC current which flows from the power terminal VDDAH through PMOS transistor11and the NMOS transistor21to a grounding terminal GND. In addition, when the voltage level of the node is pulled down from VDDAL to the grounded level, the NMOS transistor21is turned off and the NMOS transistor22is turned on. Meanwhile, because the NMOS transistor21is turned off, no current flows through the PMOS transistor11. Therefore, the current mirror10and the PMOS transistor12are turned off. The voltage level of the output terminal, hence, is pulled down to grounded level via the turned on NMOS transistor22.

Please refer toFIG. 2, which is a circuit diagram of another level shifter80according to the prior art. The level shifter80is disclosed in U.S. Pat. No. 5,469,080 “LOW-POWER, LOGIC SIGNAL LEVEL CONVERTER”. The level shifter80uses a PMOS transistor6to control the electrical connection between the two nodes3and5. The gate of the PMOS transistor6is feedback controlled by the node4so that the DC current flow is eliminated in a specific situation. When the node1is low, i.e. grounding, the NMOS transistor22is turned on so that the voltage level of the node4is pulled down to the grounded level. Then, the PMOS transistor6is turned on. When the voltage level of the node1is pulled up from the grounded level to VDDAL, the NMOS transistor21is turned on and the NMOS transistor22is turned off. At the moment, because the PMOS transistor6is still turned on, a transient current flows from the power terminal VDDAH through the PMOS transistor11, the PMOS transistor6and the NMOS transistor21to the grounded terminal GND. The transient current is mirrored to the PMOS transistor12of the current mirror10so that the voltage level of the node4is pulled up to approach to VDDAH. Without concerning about the body effect of the transistors and assume all the PMOS transistors are identical, the PMOS transistor6is turned off when the voltage level of the node4is pulled up to (VDDAH−2Vtp), where Vtp is the threshold voltage of the PMOS transistors. However, when the PMOS transistor6is turned off, it is impossible to keep the current mirror10being turned on. In the situation, the voltage level of the node4stays at (VDDAH−2Vtp) and cannot be further pulled up to VDDAH. Therefore, the level shifter80is not a full-swing level shifter, and the circuits drived by the level shifter80may have DC current issues. Oppositely, when the voltage level of the node1is pulled down from VDDAL to the grounded level, the NMOS transistor21is turned off and the NMOS transistor22is turned on. Then, the voltage level of the node4is pulled down to the grounded level via the NMOS transistor22. In this situation, the PMOS transistor6is turned on by the node4, so it is impossible that NMOS transistor21and the PMOS transistor6are turned on at the same time. And, there is not any DC current generated.

Please refer toFIG. 3, which is a circuit diagram of another level shifter90according to the prior art. The level shifter90is disclosed in U.S. Pat. No. 6,480,050 “LEVEL SHIFTER WITHOUT QUIESCENT DC CURRENT FLOW”. The level shifter90is based on the level shifter70shown inFIG. 1. The level shifter90has all the elements of the level shifter70, moreover, a PMOS transistor34, two inverters31,32, and a PMOS transistor14. When the voltage level of the input node1is equal to VDDAL, because the inverters31and32are controlled by the node4, the PMOS transistor14is turned off to avoid DC current. Meanwhile, the PMOS transistor34is turned on, another DC current path is occurred, i.e. the dotted line inFIG. 3. A DC current I flows from the power terminal VDDAH through the PMOS transistor34, the PMOS transistor12, the PMOS transistor11, and the NMOS transistor21to the grounded terminal GND.

SUMMARY OF INVENTION

It is therefore a primary objective of the present invention to provide a novel level shifter to solve the above-mentioned problems.

The level shifter comprises a switch module, a power terminal, a current mirror, and a voltage holding module. The switch module has a first switch and a second switch. The switch module receives an input signal and turns on/off the first switch and the second switch according to the received input signal. The power terminal supplies a voltage to the level shifter. The current mirror is coupled to the power terminal and has a first node and a second node. The second node being coupled to the second switch. The voltage holding module has a control circuit and a third switch that is controlled by the control circuit. The control circuit is coupled to the third switch and the second node of the current mirror. The control circuit establishes electrical connection between the first switch and the first node of the current mirror by turning on the third switch.

According to another embodiment of the present invention, the level shifter comprises an input terminal, a first switch, a second switch, an inverter, a first power terminal, a second power terminal, a current mirror, and a voltage holding module. The input terminal receives an input signal. The first switch is connected to the input terminal. The inverter has an input connected to the input terminal and an output terminal connected to the second switch. The first power terminal supplies a first voltage to the level shifter. The second power terminal supplies a second voltage to the level shifter. The current mirror is coupled to the first power terminal and has a first node coupled to the first switch and a second node coupled to the second switch. The voltage holding module has a control circuit and a third switch that is controlled by the control circuit. The control circuit is coupled to the third switch and the second node of the current mirror. The control circuit establishes electrical connection between the first switch and the second power terminal by turning on the third switch.

According to another embodiment of the present invention, the level shifter has a switch module, a power terminal, a current mirror, and a voltage holding module. The switch module has a first switch and a second switch. The switch module receives an input signal and turns on/off the first switch and the second switch according to the received input signal. The power terminal for supplies a voltage to the level shifter. The current mirror is coupled to the power terminal and has a first control element, a second control element, a first node, and a second node. The first control element is coupled to the first switch via the first node, and the second control element is coupled to the second switch via the second node. The voltage holding module has a control circuit and a third switch that is controlled by the control circuit. The control circuit is coupled to the third switch and the second node of the current mirror. The control circuit establishes electrical connection between the first control element and the power terminal by turning on the third switch.

DETAILED DESCRIPTION

Please refer toFIG. 4, which is a first embodiment level shifter100according to the present invention. The level shifter100is used to translate signals between two voltage supply domains and has a current mirror10. The current mirror10is composed of two gate-coupled PMOS transistors11and12. The gate of the PMOS transistor11is coupled to the drain of the PMOS transistor11. The current mirror10is controlled via the two nodes4and5. The level shifter100further comprises an inverter2, a power terminal VDDAH, a switch module20, a voltage holding module30, and a grounded terminal GND. The inverter2outputs an inverted signal by inverting an input signal from the input node1. The switch module20has two switch NMOS transistors21and22that have drains respectively connected to the nodes3and4and gates biased by the nodes1and the output of inverter2. The power terminal VDDAH is used to provide a voltage source, and the grounded terminal is used to provide the grounded level. It is noted that the grounded terminal can be replaced by another power terminal for providing another voltage source which has lower voltage level than the power terminal VDDAH. A voltage holding module30of the level shifter100has an NMOS transistor7and control circuit40. The NMOS transistor7is controlled by the control circuit40. The control circuit40has an inverter41controlled by the node4and a feedback PMOS transistor42which has a source, a drain, and a gate respectively connected to the power terminal VDDAH, the input terminal of the inverter41, and the output terminal of the inverter41. The gate of NMOS transistor7is connected to the output of the inverter41, and the drain and the source of the NMOS transistor7are respectively coupled to the node5and the node3. In addition, a path is formed by the power terminal VDDAH, the PMOS transistor11, the NMOS transistor7, the NMOS transistor21, and the grounded terminal GND. Another path is formed by the power terminal VDDAH, the PMOS transistor12, the NMOS transistor22, and the grounded terminal GND. The control circuit40is connected between the two paths.

When the node1is low, i.e. grounded, the NMOS transistor21is turned off and the NMOS transistor22is turned on. The voltage level of the node4is pulled down to the grounded level. Then, the output of the inverter41is pulled up to VDDAH because of the grounded node4. Therefore, the NMOS transistor7is turned on by the inverter41. Oppositely, when the voltage level of the node1is pulled up from the grounded level to VDDAL, the NMOS transistor21is turned on and the NMOS transistor22is turned off. Meanwhile, because the NMOS transistor NMOS7is still turned on, a transient current flows from the power terminal VDDAH through the PMOS transistor11, the NMOS transistor7, and the NMOS transistor21to the grounded terminal GND. The transient current is mirrored to the PMOS transistor12of the current mirror10so that the voltage level of the node4is pulled up to VDDAH. When the voltage level of the node4is equal to VDDAH, the status of the inverter41is switched so that the NMOS transistor7is turned off. Therefore, there is no DC current generated. In addition, because the control circuit40is coupled to the power terminal VDDAH, the voltage level of the node4can be pulled up to VDDAH, i.e. not (VDDAH−2Vtp). Moreover, when the voltage level of the node1is pulled down from VDDAL to the grounded level, the NMOS transistor21is turned off and the NMOS transistor22is turned on. Meanwhile, the voltage level of the node4is pulled down to the grounded level via the NMOS transistor22, and the NMOS transistor7is turned on by the inverter41. In such case, the NMOS transistor21and the NMOS transistor7present an AND logic style. Moreover, because the NMOS transistor21and the NMOS transistor7cannot be turned on at the same time when the level shifter100operates in a stable state, there is not any DC current when the level shifter100operates. In other words, the electrical connection between the NMOS transistor21and the node5is well controlled by the NMOS transistor7to avoid any DC current.

According to the present invention, the main function of the PMOS transistor42of the control circuit40is to pull up the voltage level of the node4to VDDAH so as to provide the level shifter100with a greater ability to overcome the noise from the output terminal9. Therefore, as shown inFIG. 5, the PMOS transistor42of the level shifter100shown inFIG. 4can be replaced by an inverter43.FIG. 5is a circuit diagram of the second embodiment level shifter110according to the present invention. The control circuit40shown inFIG. 4is replaced by another control circuit50. Because the two inverters41and43are connected to the power terminal VDDAH, the function of the control circuit50is the same as the function of the control circuit40that makes the level shifter output a full-swing supply voltage without any DC current flow.

In addition, because the NMOS transistor21and the NMOS transistor7present an AND logic style, the positions of the two NMOS transistors21and7can be switched. Please refer toFIG. 6, which is a third embodiment level shifter120to indicate such situation. The control circuit40establishes the electrical connection between the node3and the grounded terminal GND by turning on the NMOS transistor7and abolishes the electrical connection between the node3and the grounded terminal GND by turning off the NMOS transistor7.

Moreover, because the PMOS transistor and the NMOS transistor are complementary elements, the NMOS transistor7of the voltage holding module30can be replaced by a PMOS transistor. Please refer toFIGS. 7–8, whichFIG. 7is a circuit diagram of a fourth embodiment level shifter130according to the present invention, andFIG. 8is a circuit diagram of a fifth embodiment level shifter140according to the present invention. The NMOS transistor7is replaced by a PMOS transistor6and an inverter8is added to the control circuit40to compose another control circuit60. The PMOS6of the level shifter130controls the electrical connection between the NMOS transistor21and the node5, and the PMOS6of the level shifter140controls the electrical connection between the PMOS transistor111and the power terminal VDDAH.

It is noted that the current mirror10can be not only a simple circuit that is composed of two PMOS transistors11and12, but also can be another kind of current mirror that has more complex circuit structure.

In the contrast to the prior art level shifter, the present invention provides a level shifter not only operates without generating any DC current flow, but also the output voltage supply is full-swing. Therefore, the wasted electric energy is less, and the ability to overcome the noise from the output terminal is greater.