CROSS-DOMAIN VOLTAGE BUS RESOURCE SHARING FOR IMPROVED POWER DELIVERY NETWORK

An apparatus, including: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first mode; and couple the bus resource to the second voltage bus based on a second mode.

FIELD

Aspects of the present disclosure relate generally to power delivery networks (PDNs) for integrated circuits (ICs), such as system on chip (SoC), and in particular, to a cross-domain voltage bus resource sharing for improved PDN.

BACKGROUND

An integrated circuit (IC), such as a system on chip (SoC), typically includes a set of cores (e.g., subsystems or circuits), such as a central processing unit (CPU), graphics processing unit (CPU), memory, neural signal processor (NSP), radio frequency (RF) transceiver, modem, input/output (I/O) core, security core, etc. A power management integrated circuit (PMIC) typically provides a set of supply voltages on a set of voltage buses coupled to the set of cores, respectively. The stability of the set of supply voltages including mitigating voltage transients therein is of interest in such power delivery network (PDN).

SUMMARY

An aspect of the disclosure relates to an apparatus. The apparatus includes: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first mode; and couple the bus resource to the second voltage bus based on a second mode.

Another aspect of the disclosure relates to a method. The method includes: coupling a bus resource of a first voltage bus to a second voltage bus in response to an actual or predicted voltage transient on the second voltage bus; and decoupling the bus resource from the second voltage bus in response to an absence of the actual or predicted voltage transient on the second voltage bus.

Another aspect of the disclosure relates to an apparatus. The apparatus includes: a power management integrated circuit (PMIC) including first and second voltage regulators; a first voltage bus coupled to the first voltage regulator of the PMIC; a second voltage bus coupled to the second voltage regulator of the PMIC; a first core coupled to the first voltage bus; a second core coupled to the second voltage bus; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first mode; and couple the bus resource to the second voltage bus based on a second mode.

Another aspect of the disclosure relates to an apparatus. The apparatus includes: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first priority allowing the first core to share the bus resource and a second priority allowing the second core to borrow the bus resource from the first core.

To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents.

DETAILED DESCRIPTION

FIG.1illustrates a block diagram of an example power delivery network (PDN)100in accordance with an aspect of the disclosure. The PDN100includes a battery VBATT, a power management integrated circuit (PMIC)110, and a system on chip (SoC)130, where the PMIC110and SoC130may be mounted on a printed circuit board (PCB)150. The PMIC110includes a set of voltage regulators (VRs)120-1to120-N configured to generate a set of supply voltages Vdd1to VddN based on the voltage VBATTgenerated by the battery. As an example, the set of voltage regulators (VRs)120-1to120-N may include switching regulators (SRs), low-dropout (LDO) regulators, and/or other types of voltage regulators.

The SoC130, in turn, includes a set of cores (e.g., subsystems or circuits)140-1to140-N. For example, the set of cores140-1to140-N may include a multimedia (MM) core, a neural signal processing (NSP) core, a graphics processing unit (GPU) core, a central processing unit (CPU) core, a security core, a radio frequency (RF) core, an input/output (I/O) core, and/or other cores. The set of cores140-1to140-N of the SoC130may be coupled to the set of voltage regulators (VRs)120-1to120-N via a set of transmission lines160-1to160-N on the PCB150, respectively. Accordingly, for power delivery purpose, the set of cores140-1to140-N may receive the set of supply voltages Vdd1to VddN from the set of voltage regulators (VRs)120-1to120-N via the set of transmission lines160-1to160-N, respectively.

FIG.2illustrates a block/schematic diagram of another example power delivery network (PDN)200in accordance with another aspect of the disclosure. The PDN200may be an example more detailed implementation of the SoC130side of the PDN100previously discussed. In particular, the PDN200includes a system on chip (SoC)205, an integrated circuit (IC) package230, and a printed circuit board (PCB)240. The SoC205may be mounted to and within the IC package230; and the IC package230, in turn, may be mounted on the PCB240.

In this example, the SoC205includes an input/output (I/O) core210and a graphics processing unit (GPU) core220. It shall be understood that the SoC205may include other different types of cores or a different set of cores. The I/O core210is coupled to a voltage (power) bus (rail)250-1to receive a supply voltage Vdd_io from, for example, a voltage regulator (VR) of a power management integrated circuit (PMIC), such as PMIC110. Similarly, the GPU core220is coupled to a voltage bus250-2to receive a supply voltage Vdd_gpu from, for example, another voltage regulator (VR) of the PMIC.

The steadiness or stability of the supply voltages Vdd_io and Vdd_gpu is of concern for proper operations of the I/O core210and GPU cores220, respectively. If the supply voltages Vdd_io and Vdd_gpu are subjected to voltage transients (e.g., voltage droops, glitches, spikes, undershoots, overshoots, and/or other voltage artifacts) due to different load demands from the I/O core210and GPU core220(as well as other sources of noise), the voltage transients may cause problems for the I/O core210and GPU core220, respectively. For example, such problems may cause a collapse of the SoC205, as well as failed operations of the I/O core210and GPU core220, and/or other cores of the SoC205.

To mitigate voltage transients on the voltage buses250-1to250-2, the PDN200may include various decoupling capacitors. For example, the SoC205includes a first set of one or more on-chip decoupling capacitors C11and C12coupled between the Vdd_io voltage bus250-1and ground (a negative voltage rail), and a second set of one or more on-chip decoupling capacitors C21and C22coupled between the Vdd_gpu voltage bus250-2and ground. Further, in this regard, the IC package230may include a first set of one or more IC package (off-chip) decoupling capacitors C13coupled between the Vdd_io voltage bus250-1and ground, and a second set of one or more IC package (off-chip) decoupling capacitors C23coupled between the Vdd_gpu voltage bus250-2and ground. In a similar vein, the PCB240may include a first set of one or more PCB (off-chip and off-package) decoupling capacitors C14coupled between the Vdd_io voltage bus250-1and ground, and a second set of one or more PCB (off-chip and off-package) decoupling capacitors C24coupled between the Vdd_gpu voltage bus250-2and ground.

For example, if there is a sudden high load demand from the I/O core210, the supply voltage Vdd_io may experience a voltage transient in the form of a voltage droop. As the decoupling capacitors C11, C12, C13, and C14are charged to the specified supply voltage Vdd_io, the voltage droop causes a discharging of the decoupling capacitors C11, C12, C13, and C14to provide charges to the Vdd_io voltage bus250-1to counter the voltage drop. Similarly, if there is a sudden reduction in the load demand from the I/O core210, the supply voltage Vdd_io may experience a voltage transient in the form of a voltage spike or overshoot. As the decoupling capacitors C11, C12, C13, and C14are charged to the specified supply voltage Vdd_io, the voltage overshoot causes a charging of the decoupling capacitors C11, C12, C13, and C14to remove charges from the Vdd_io voltage bus250-1to counter the voltage overshoot. In a similar manner, the decoupling capacitors C21, C22, C23, and C24provide voltage transient mitigation for the Vdd_gpu voltage bus250-2.

FIG.3illustrates a cross-sectional view of an example deep trench capacitor (DTC)300in accordance with another aspect of the disclosure. The DTC300may be an example of any of the decoupling capacitors discussed herein. In particular, the DTC300includes a substrate (e.g., silicon or p-doped silicon substrate)305, a well (e.g., an n-doped well)310formed at least partially within the substrate305, a first (lower) dielectric layer (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4))315formed at least partially within the well310, a first (lower) polysilicon layer320disposed over the first dielectric layer315at least partially within the well310, a second (upper) dielectric layer (e.g., SiO2or Si3N4)325disposed over the first polysilicon layer320at least partially within the well310, and a second (upper) polysilicon layer330disposed over the second dielectric layer325at least partially within the well310.

The DTC300may include a first metal electrode or terminal335(e.g., a metallized via hole through an insulating layer345) disposed over and electrically coupled to the second (upper) polysilicon layer330. Further, the DTC300may include a second metal electrode or terminal340(e.g., a metallized via hole through the insulating layer345) disposed and electrically coupled to the well310. The first metal electrode or terminal335may be the upper plate of the decoupling capacitor, which may be electrically coupled to the corresponding voltage bus, and the second metal electrode or terminal may be the bottom plate of the decoupling capacitor electrically coupled to ground.

An issue with the PDN200previously discussed is that typically the sets of decoupling capacitors C11-C14and C21-C24coupled to the Vdd_io and Vdd_gpu voltage busses250-1and250-2are typically fixed once the corresponding product is shipped. If the number of decoupling capacitors coupled to a voltage bus is not sufficient to properly mitigate voltage transients on the bus due to different load demands from the corresponding core, such voltage transients may impact the operation of the core and the corresponding SoC. Such PDN200may be designed to increase the number of decoupling capacitors coupled to a bus to improve the stability of the supply voltage, but that would consume more chip, package, and PCB area, which may not be desirable.

FIG.4illustrates a block diagram of an example cross-domain bus resource sharing power delivery network (PDN)400in accordance with another aspect of the disclosure. A concept herein is that if a voltage bus is experiencing or is about to experience high load demands that produce or likely to produce voltage transient, the voltage bus may temporarily borrow voltage transient mitigation resources from another voltage bus to better mitigate the actual or predicted voltage transient. Once the high load demand has ended, subsided, or is no longer a factor, the voltage transient mitigation resources may be returned to the sharing voltage bus. Thus, the PDN400may provide improved voltage transient mitigation for voltage buses through this bus resource borrowing/sharing technique without increasing the number of transient mitigating resources on each bus.

In particular, the PDN400includes a first core-1(e.g., subsystem or circuit)410, a second core-2(e.g., subsystem or circuit)420, a first voltage bus Vdd1_BUS460-1coupled to the first core-1410, and a second voltage bus Vdd2_BUS460-2coupled to the second core-2420. The PDN400further includes a first (Vdd1) voltage bus resource430coupled to the first voltage bus Vdd1_BUS460-1, and a second (Vdd2) voltage bus resource440coupled to the second voltage bus Vdd2_BUS460-2. As discussed in more detail further herein, each of the voltage bus resources430and440may include one or more decoupling capacitors, one or more clamps, electrostatic discharge (ESD) circuit (e.g., one or more ESD diodes), the corresponding supply voltage, and/or other transient mitigating bus resources.

The PDN400may further include a control circuit450and at least one switching device SW. The control circuit450may be configured to receive a signal Sb2indicating whether the supply voltage Vdd2on the second voltage bus Vdd2_BUS460-2is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand interval). Based on the signal Sb2indicating no such actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS460-2(e.g., default configuration or mode), the control circuit450generates a (e.g., deasserted) control signal CS to open the at least one switching device SW. In such default configuration or mode, the Vdd1bus resource430of the first voltage bus Vdd1_BUS460-1is not shared with the second voltage bus Vdd2_BUS460-2. In other words, the bus resources430and440deal with providing supply voltage stability and mitigating voltage transients on their assigned first and second voltage busses Vdd1_BUS460-1and Vdd2_BUS460-2, respectively.

Based on the signal Sb2indicating an actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS560-2(e.g., share/borrow configuration or mode), the control circuit450generates the (e.g., asserted) control signal CS to close the at least one switching device SW so that the Vdd1bus resource430of the first voltage bus Vdd1_BUS460-1is provided to the second voltage bus Vdd2_BUS460-2(as indicated by the dashed arrow) directly or via the Vdd2bus resource440to better mitigate the impact or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS460-2. Once the signal Sb2indicates that the actual or predicted impact on the supply voltage has ended, subsided, or is no longer a factor, the control circuit450generates the (e.g., deasserted) control signal CS to open the at least one switching device SW to return the Vdd1bus resource430to the first voltage bus Vdd1_BUS460-1per the default configuration or mode.

The PDN400may optionally include a communication link (e.g., I2S, or other)470from the control circuit450to the corresponding PMIC (e.g., PMIC110) to inform it of the bus resource sharing/borrowing event. The PMIC may use such information to modify its operations with respect to the supply voltages Vdd1and Vdd2for the first and/or second voltage buses460-1and460-2, respectively. For example, if there are frequent supply voltage impacting events for the second voltage bus460-2, the PMIC may provide additional resources on the second voltage bus460-2, as well as additional sharing resources for the first voltage bus460-1(e.g., increase its supply voltage). Although not explicitly shown in other PDNs described herein, such communication link470may be provided in such PDNs as well.

Although, in this example, the power domain of the first core-1410is sharing its Vdd1bus resource430with the power domain of the second core-2420(e.g., cross-domain resource sharing), it shall be understood that the PDN400may be configured to selectively implement bidirectional bus resource sharing between the first and second power domains, where the Vdd2bus resource440may be shared with the first voltage bus Vdd1_BUS460-1.

FIG.5illustrates a block/schematic diagram of an example cross-domain decoupling capacitor sharing power delivery network (PDN)500in accordance with another aspect of the disclosure. The PDN500may be an example of a specific implementation of the PDN400previously discussed. In this example, the voltage bus resource that is being shared/borrowed is one or more decoupling capacitors.

In particular, the PDN500includes a first core-1(e.g., subsystem or circuit)510, a second core-2(e.g., subsystem or circuit)520, a first voltage bus Vdd1_BUS560-1coupled to the first core-1510, and a second voltage bus Vdd2_BUS560-2coupled to the second core-2520. The PDN500further includes a first set of one or more decoupling capacitors C1including a top plate or terminal selectively coupled to the first voltage bus Vdd1_BUS560-1via a first switching device SW1, and selectively coupled to the second voltage bus Vdd2_BUS560-2via an optional diode D or a voltage level shifter (LS)530and a second switching device SW2. The first set of one or more decoupling capacitors C1includes a bottom plate or terminal coupled to ground. The PDN500further includes a second set of one or more capacitors C2coupled between the second voltage rail Vdd2_BUS560-2and ground. The first and second sets of one or more decoupling capacitors C1and C2may be one or more on-chip capacitors, one or more IC package (off-chip) capacitors, and/or one or more PCB (off-chip and off-package) capacitors.

The PDN500may further include a control circuit550configured to receive a signal Sb2indicating whether the supply voltage Vdd2on the second voltage bus Vdd2_BUS560-2is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand time interval). Based on the signal Sb2indicating no such actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS560-2(e.g., default configuration or mode), the control circuit550generates a first (e.g., asserted) control signal CS1to close the first switching device SW1and a second (e.g., deasserted) control signal CS2to open the second switching device SW2. In such default configuration or mode, the first set of one or more decoupling capacitors C1is coupled to the first voltage bus Vdd1_BUS560-1, and decoupled from the second voltage bus Vdd2_BUS560-2. Thus, the first set of one or more decoupling capacitors C1is mitigating voltage transients and providing stability to the supply voltage Vdd1on the first voltage bus Vdd1_560-1.

Based on the signal Sb2indicating an actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS560-2(e.g., share/borrow configuration or mode), the control circuit550generates the first (e.g., deasserted) control signal CS1to open the first switching device SW1and the second (e.g., asserted) control signal CS2to close the second switching device SW2. In such share/borrow configuration or mode, the first set of one or more decoupling capacitors C1is decoupled from the first voltage bus Vdd1_BUS560-1, and coupled to the second voltage bus Vdd2_BUS560-2to assist the second set of one or more decoupling capacitors C2in mitigating voltage transient and providing stability to the supply voltage Vdd2on the second voltage bus Vdd2_BUS560-2. Then, based on the signal Sb2indicating that the actual or predicted impact on the supply voltage Vdd2has ended, subsided, or is no longer a factor, the control circuit550generates the first (e.g., asserted) control signal CS1to close the first switching device SW1and the second (e.g., deasserted) control signal CS2to open the second switching device SW2to reconfigure the PDN500back to the default configuration or mode.

The supply voltage Vdd1on the first voltage bus Vdd1_BUS560-1(e.g., the sharing voltage bus) should be substantially the same or higher than the supply voltage Vdd2on the second voltage bus Vdd2_BUS560-2(e.g., the borrowing voltage bus) to improve the transient mitigation on the second voltage bus Vdd2_BUS560-2. The optional diode D or level shifter (LS)530may provide an appropriate voltage drop and unidirectional current for a smooth sharing of the decoupling capacitor C1with the second voltage bus Vdd2_BUS560-2.

Although, in this example, the power domain of the first core-1510is sharing its first set of one or more decoupling capacitors C1with the power domain of the second core-2520(e.g., cross-domain resource sharing), it shall be understood that the PDN500may be configured to selectively implement bidirectional bus resource (e.g., decoupling capacitors) sharing between the first and second power domains (e.g., the second set of one or more decoupling capacitors C2may be selectively coupled to the first voltage bus Vdd1_BUS560-1, and decoupled from the second voltage bus Vdd2_BUS560-2).

FIG.6illustrates a block/schematic diagram of another example cross-domain decoupling capacitor sharing power delivery network (PDN)600in accordance with another aspect of the disclosure. The PDN600is a variation of PDN500previously discussed, and includes many of the same/similar elements as indicated by the same reference indicators and numbers but with the most significant digit being a “6” for PDN600instead of a “5” as in PDN500. The PDN600differs from PDN500in that PDN600includes a selectable bank of decoupling capacitors C31to C3Npertaining to the power domain of the first voltage bus Vdd1_BUS660-1that may be shared with (borrowed by) the power domain of the second voltage bus Vdd2_BUS660-2.

More specifically, the set of decoupling capacitors C31to C3Nare coupled in series with a set of switching devices SW31to SW3Nbetween the first switching device SW1and ground, respectively. The control circuit650is configured to generate a set of control signals CS31to CS3Nseparately control the open/closed states of the set of switching devices SW31to SW3N, respectively. For example, in default configuration or mode as indicated by signal Sb2, the control circuit650may generate the control signals CS1, CS2, and CS31-CS3Nto close the first switching device SW1, to close the set of switching devices SW31to SW3N, and to open the second switching device SW2. In this default configuration or mode, the bank of decoupling capacitors C31to C3Nare fully coupled to the first voltage bus Vdd1_BUS660-1to deal with voltage transient in the first supply voltage Vdd1. It shall be understood that, in default configuration or mode, less than the entire set of decoupling capacitors C31to C3Nmay be coupled to the voltage bus Vdd1_BUS660-1by keeping one or more of the set of switching devices SW31to SW3Nopen

Based on the signal Sb2indicating an actual or predicted voltage transient on the supply voltage Vdd2on the second voltage bus Vdd2_BUS660-2, the control circuit650may generate the generate the control signals CS1, CS2, and CS31-CS3Nto open the first switching device SW1, to close one or more of the set of switching devices SW31to SW3N, and to close the second switching device SW2. In this share/borrow configuration or mode, one or more of the bank of decoupling capacitors C31to C3Nare coupled to the second voltage bus Vdd1_BUS660-2to assist the second set of one or more decoupling capacitors C2in mitigating the voltage transients in the second supply voltage Vdd2.

The number of switching devices SW31to SW3Nthat are closed may be based on different conditions (e.g., the voltage difference between Vdd1and Vdd2), and may also be dynamic. For example, if the signal Sb2indicates a fairly mild voltage transient on the second voltage bus Vdd2_BUS660-2, the control circuit650may generate the control signal CS31-CS3Nto close only one or a few of the switching devices SW31to SW3Nso that the corresponding one or few decoupling capacitors C31to C3Nare coupled to the second voltage bus Vdd2_BUS660-2to mitigate the mild voltage transient on the second voltage bus Vdd2_BUS660-2. Conversely, if the signal Sb2indicates an aggressive voltage transient on the second voltage bus Vdd2_BUS660-2, the control circuit650may generate the control signal CS31-CS3Nto close most or all of the switching devices SW31to SW3Nso that the corresponding most or all of the decoupling capacitors C31to C3Nare coupled to the second voltage bus Vdd2_BUS660-2to mitigate the harsh voltage transient on the second voltage bus Vdd2_BUS660-2.

As mentioned, the coupling of the set of decoupling capacitors C31to C3Nby closing the corresponding set of switching devices SW31to SW3Nmay be dynamic. For example, during a Vdd2transient mitigation event, the control circuit650may generate the control signal CS31-CS3Nto progressively close the set of switching devices SW31to SW3Nto provide a smooth progressive coupling of the set of decoupling capacitors C31to C3Nto the second voltage bus Vdd2_BUS660-2. When the signal Sb2indicates that the transient mitigation event has ended, subsided, or is no longer a factor, the control circuit650may generate the control signal CS31-CS3Nto progressively open the set of switching devices SW31to SW3Nto provide a smooth progressive decoupling of the set of decoupling capacitors C31to C3Nfrom the second voltage bus Vdd2_BUS660-2. Further, based on the signal Sb2indicating that the transient mitigation event has ended, subsided, or is no longer a factor, the control circuit650may generate the control signals CS1, CS2, and CS31-CS3Nto close the switching device SW1, open the switching device SW2, and close the number of switching devices SW31to SW3Npursuant to the default configuration or mode.

Although, in this example, the power domain of the first core-1610is sharing its selectable bank of decoupling capacitors C31to C3Nwith the power domain of the second core-2620(e.g., cross-domain resource sharing), it shall be understood that the PDN600may be configured to selectively implement bidirectional bus resource (e.g., bank of selectable decoupling capacitors) sharing between the first and second power domains (e.g., the second set of one or more decoupling capacitors C2may be implemented as a selectable bank of decoupling capacitors, which may be selectively coupled to the first voltage bus Vdd1_BUS660-1, and decoupled from the second voltage bus Vdd2_BUS660-2).

FIG.7illustrates a block/schematic diagram of an example cross-domain supply voltage sharing power delivery network (PDN)700in accordance with another aspect of the disclosure. The PDN700may be an example of a specific implementation of the PDN400previously discussed. In this example, the voltage bus resource that is being shared/borrowed is the supply voltage itself.

In particular, the PDN700includes a first core-1(e.g., subsystem or circuit)710, a second core-2(e.g., subsystem or circuit)720, a first voltage bus Vdd1_BUS760-1coupled to the first core-1710, and a second voltage bus Vdd2_BUS760-2coupled to the second core-2720. The PDN700further includes a set of one or more decoupling capacitors C including a top plate or terminal coupled to the second voltage bus Vdd2_BUS760-2. The set of one or more decoupling capacitors C may be one or more on-chip capacitors, one or more IC package (off-chip) capacitors, and/or one or more PCB (off-chip and off-package) capacitors. The PDN700further includes a first switching device SW1coupled between the first voltage bus Vdd1_BUS760-1and a bottom plate of the set of one or more decoupling capacitors C. Additionally, the PDN700includes a second switching device SW2coupled between the bottom plate of the set of one or more decoupling capacitors C and ground.

The PDN700may further include a control circuit750configured to receive a signal Sb2indicating whether the supply voltage Vdd2on the second voltage bus Vdd2_BUS760-2is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand time interval). Based on the signal Sb2indicating no such actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS760-2(e.g., default configuration or mode), the control circuit750generates a first (e.g., deasserted) control signal CS1to open the first switching device SW1and a second (e.g., asserted) control signal CS2to close the second switching device SW2. In such default configuration or mode, the first supply voltage Vdd1of the first voltage bus Vdd1_BUS760-1is not shared with the second voltage bus Vdd2_BUS760-2, and the set of one or more capacitors C each operate as a decoupling capacitor.

Based on the signal Sb2indicating an actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS760-2(e.g., share/borrow configuration or mode), the control circuit750generates the first (e.g., asserted) control signal CS1to close the first switching device SW1and the second (e.g., deasserted) control signal CS2to open the second switching device SW2. In such share/borrow configuration or mode, the first supply voltage Vdd1is provided to the bottom plate of the set of one or more capacitors C to boost the second supply voltage Vdd2on the second voltage bus Vdd2_BUS760-2by the first supply voltage Vdd1to assist in mitigating the voltage transient on the second voltage bus Vdd2_BUS760-2. In such case, each of the set of one or more capacitors C has been reconfigured as a voltage boosting capacitor.

Then, based on the signal Sb2indicating that the actual or predicted impact on the supply voltage Vdd2has ended, subsided, or no longer a factor, the control circuit750generates the first (e.g., deasserted) control signal CS1to open the first switching device SW1and the second (e.g., asserted) control signal CS2to close the second switching device SW2to reconfigure the PDN700back to the default configuration or mode.

Although, in this example, the power domain of the first core-1710is sharing its supply voltage Vdd1with the power domain of the second core-2720(e.g., cross-domain resource sharing), it shall be understood that the PDN700may be configured to selectively implement bidirectional bus resource (e.g., supply voltage) sharing between the first and second power domains (e.g., the supply voltage Vdd2selectively provided to the first voltage bus Vdd1_BUS760-1).

FIG.8illustrates a block/schematic diagram of an example cross-domain voltage clamp sharing power delivery network (PDN)800in accordance with another aspect of the disclosure. The PDN800may be an example of a specific implementation of the PDN400previously discussed. In this example, the voltage bus resource that is being shared/borrowed is a voltage clamp.

In particular, the PDN800includes a first core-1(e.g., subsystem or circuit)810, a second core-2(e.g., subsystem or circuit)820, a first voltage bus Vdd1_BUS860-1coupled to the first core-1810, and a second voltage bus Vdd2_BUS860-2coupled to the second core-2820. The PDN800further includes a voltage clamp830selectively coupled to the first voltage bus Vdd1_BUS860-1via a first switching device SW1, and selectively coupled to the second voltage bus Vdd2_BUS860-2via a second switching device SW2. The voltage clamp830is coupled between the first and second switching devices SW1and SW2and ground.

The PDN800may further include a control circuit850configured to receive a signal Sb2indicating whether the supply voltage Vdd2on the second voltage bus Vdd2_BUS860-2is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand time interval). Based on the signal Sb2indicating no such actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS860-2(e.g., default configuration or mode), the control circuit850generates a first (e.g., asserted) control signal CS1to close the first switching device SW1and a second (e.g., deasserted) control signal CS2to open the second switching device SW2. In such default configuration or mode, the voltage clamp830is coupled to the first voltage bus Vdd1_BUS860-1, and decoupled from the second voltage bus Vdd2_BUS860-2. Thus, the voltage clamp830may mitigate voltage transients (e.g., spikes or overshoots) in the supply voltage Vdd1on the first voltage bus Vdd1_BUS860-1.

Based on the signal Sb2indicating an actual or predicted impact on the supply voltage Vdd2on the second voltage bus Vdd2_BUS860-2(e.g., share/borrow configuration or mode), the control circuit850generates the first (e.g., deasserted) control signal CS1to open the first switching device SW1and the second (e.g., asserted) control signal CS2to close the second switching device SW2. In such share/borrow configuration or mode, the voltage clamp830is decoupled from the first voltage bus Vdd1_BUS860-1, and coupled to the second voltage bus Vdd2_BUS860-2to assist in mitigating voltage transients (e.g., spikes or overshoots) and provide stability to the supply voltage Vdd2on the second voltage bus Vdd2_BUS860-2. Then, based on the signal Sb2indicating that the actual or predicted impact on the supply voltage Vdd2has ended, subsided, or is no longer a factor, the control circuit850generates the first (e.g., asserted) control signal CS1to close the first switching device SW1and the second (e.g., deasserted) control signal CS2to open the second switching device SW2to reconfigure the PDN800back to the default configuration or mode.

Although, in this example, the power domain of the first core-1810is sharing its voltage clamp830with the power domain of the second core-2820(e.g., cross-domain resource sharing), it shall be understood that the PDN800may be configured to selectively implement bidirectional bus resource (e.g., voltage clamp) sharing between the first and second power domains (e.g., a voltage clamp assigned to the second voltage bus Vdd2_BUS860-2selectively coupled to the first voltage bus Vdd1_BUS860-1and decoupled from the second voltage bus Vdd2_BUS860-2).

FIG.9illustrates a block diagram of an example cross-domain bus resource sharing with voltage transient detection power delivery network (PDN)900in accordance with another aspect of the disclosure. The PDN900is a variation of PDN400previously discussed, and includes many of the same/similar elements as indicated by the same reference indicators and numbers but with the most significant digit being a “9” for PDN900instead of a “4” as in PDN400.

The PDN900further includes a voltage transient detector970configured to detect a voltage transient on the second voltage bus Vdd2_BUS960-2. In this regard, the voltage transient detector970includes an input coupled to the second voltage bus Vdd2_BUS960-2, and an output coupled to an input of the control circuit950to provide the signal Sb2thereto. In this example, the signal Sb2may indicate an actual voltage transient occurring on the second voltage bus Vdd2_BUS960-2, as opposed to a predicted voltage transient.

Accordingly, if the voltage transient detector970does not detect a voltage transient on the second voltage bus Vdd2_BUS960-2, the voltage transient detector970generates the (e.g., deasserted) signal Sb2. In response, the control circuit950generates the (e.g., deasserted) control signal CS to open the at least one switching device SW per the default configuration or mode. If the voltage transient detector970detects a voltage transient on the second voltage bus Vdd2_BUS960-2, the voltage transient detector970generates the (e.g., asserted) signal Sb2. In response, the control circuit950generates the (e.g., asserted) control signal CS to close the at least one switching device SW to couple the Vdd1bus resource to the second voltage bus Vdd2_BUS960-2to mitigate the voltage transient per the share/borrow configuration or mode. Once the transient is no longer present on the second voltage bus Vdd2_BUS960-2, the voltage transient detector970may deassert the signal Sb2; and in response, the control circuit950generates the (e.g., deasserted) control signal CS to open the at least one switching device SW to return back to the default configuration or mode.

Although, in this example, the power domain of the first core-1910is sharing its Vdd1bus resource930with the power domain of the second core-2920(e.g., cross-domain resource sharing), it shall be understood that the PDN900may be configured to selectively implement bidirectional bus resource sharing between the first and second power domains. For example, the PDN900may include another voltage transient detector including an input coupled to the first voltage bus Vdd1_BUS960to detect transient thereon, and an output coupled to the control circuit950to provide a signal Sb1indicative of whether a voltage transient has been detected on the first voltage bus Vdd1_BUS960. In response, the control circuit950may couple the Vdd2bus resource940to the first voltage bus Vdd1_BUS960.

FIG.10illustrates a block/schematic diagram of an example cross-domain bus resource sharing with reset timer power delivery network (PDN)1000in accordance with another aspect of the disclosure. The PDN1000is a variation of PDN400previously discussed, and includes many of the same/similar elements as indicated by the same reference indicators and numbers but with the most significant digit being a “10” for PDN1000instead of a “4” as in PDN400.

The PDN1000further includes a reset timer1070configured to generate a signal Sdfto instruct the control circuit1050to reconfigure the PDN1000in default configuration or mode. Thus, after the share/borrow configuration or mode has been initiated via the asserted signal Sb2, the reset timer1070initiates a timer to keep track of the elapse time from the initiation of the share/borrow configuration or mode. When the elapse time reaches a reset threshold, the reset timer1070generates (e.g., asserts) the reset time signal Sdfto cause the control circuit1050to reconfigure the PDN1000in default configuration or mode. The reset threshold may be dynamic, and may depend on the voltage transient or the supply voltage Vdd2on the second voltage bus Vdd2_BUS1060-2, and/or may depend on the end of a predicted high load demand interval associated with the second core-21020.

Although, in this example, the power domain of the first core-11010is sharing its Vdd1bus resource1030with the power domain of the second core-21020(e.g., cross-domain resource sharing), it shall be understood that the PDN1000may be configured to selectively implement bidirectional bus resource sharing between the first and second power domains. For example, the reset timer1070may dynamically set the reset threshold based on the voltage transient or the supply voltage Vdd1on the first voltage bus Vdd1_BUS1060-1, and/or the predicted high load demand interval associated with the first core-11010.

FIG.11Aillustrates a block diagram of an example task-based cross-domain bus resource sharing power delivery network (PDN)1100in accordance with another aspect of the disclosure. The PDN1100is a variation of PDN400previously discussed, and includes many of the same/similar elements as indicated by the same reference indicators and numbers but with the most significant digit being a “11” for PDN1100instead of a “4” as in PDN400.

The PDN1100further includes a central processing unit (CPU) (or other core)1170configured to generate a signal TSKiindicating the tasks or workload of the first core-11110and the second core-21120(as well as other cores) for a following ithtime interval. Based on the task signal TSKi, the control circuit1150generates the control signal CS to configure the PDN1100.

For example, if the task signal TSKiindicates that the task or workload of the second core-21120for the ithtime interval is none or requires a relatively small load demand, the control circuit1150generates the (e.g., deasserted) control signal CS to open the at least one switching device SW and not provide the Vdd1bus resource1130to the second voltage bus Vdd2_BUS1160-2during the ithtime interval per the default configuration or mode. If, on the other hand, the task signal TSKiindicates that the task or workload of the core-21120for the ithtime interval is significant or requires a relatively high load demand, the control circuit1150generates the (e.g., asserted) control signal CS to close the at least one switching device SW and provide the Vdd1bus resource1130to the second voltage bus Vdd2_BUS1160-2during the ithtime interval per the share/borrow configuration or mode.

Although, in this example, the power domain of the first core-11110is sharing its Vdd1bus resource1130with the power domain of the second core-21120(e.g., cross-domain resource sharing), it shall be understood that the PDN1100may be configured to selectively implement bidirectional bus resource sharing between the first and second power domains. For example, if the task signal TSKiindicates that the first core-11110will have a significant, relatively high load demand during the ithtime interval, the Vdd2bus resource1140may be provided to the first voltage bus Vdd1_BUS1160-1during the ithtime interval per the share/borrow configuration or mode. The following describes a more concrete example of the task-based, cross-domain resource sharing of the PDN1100.

FIG.11Billustrates a task timing diagram associated with the example task-based cross-domain bus resource sharing power delivery network (PDN)1100in accordance with another aspect of the disclosure. The horizontal axis of the task diagram represents time with an ithtime interval, followed by an (i+1)thtime interval, and that followed by an (i+2)thtime interval. As indicated by the time interval headings, the ithtask signal TSKiindicates a frame transfer task, the (i+1)thtask signal TSKi+1indicates a download task, and the (i+2)thtask signal TSKi+2indicates a gaming task.

In this example, the associated SoC includes the following core (e.g., subsystem or circuit) power domains: a double data rate (DDR) memory domain VDD_DDR, a neural signal processor (NSP) domain VDD_NSP, a multimedia (MM) domain VDD_MM, an input/output (I/O) domain VDD_IO, a radio frequency (RF) domain VDD_RF, a graphics processing unit (GPU) domain VDD_GPU, and an SoC security domain VDD_SCR.

Depending on the current task, the following priorities related to sharing/borrowing bus resources may be assigned to the various power domains: (1) priority P0is for critical domains, such as the SoC security domain VDD_SCR, that are not allowed to share or borrow bus resources regardless of the current task; (2) priority P1is for domains that are currently performing an operation, and, as a result, are not allowed to share its bus resources, but may borrow bus resources from a priority P3domain, as discussed further herein; (3) priority P2is for domains that may not be currently performing an operation, but may be (e.g., sporadically) expected to do so, and, as a result, are not allowed to share its bus resources, but may borrow bus resources from a priority P3domain; and (4) priority P3is for domains that are not currently performing or expected to perform an operations.

Referring again to the task timing diagram ofFIG.11B, the frame transfer task of the ithtime interval as indicated by the task signal TSKiinvolves a transfer of multimedia data from the DDR memory core to the multimedia core. Accordingly, the DDR memory domain VDD_DDR and the multimedia domain VDD_MM are assigned priority P1as they are currently involved in the data transfer; the GPU domain VDD_GPU is assigned priority P2as it may be called upon to process some of the transferred data; the NSP, I/O, and RF domains VDD_NSP, VDD_IO, and VDD_RF are assigned priority P3as they are not currently performing or expected to perform any operation; and the SoC security domain VDD_SCR is assigned the fixed priority P0as it is a critical domain. Accordingly, with reference toFIG.11A, the sharing domain core-11110may pertain to any of the P3domains VDD_NSP, VDD_IO, and VDD_RF, and the borrowing domain core-21120may pertain to any of the P1domains VDD_DDR and VDD_MM.

Referring again to the task timing diagram ofFIG.11B, the download task of the (i+1)thtime interval as indicated by the task signal TSKi+1involves a downloading of data. Accordingly, the DDR memory domain VDD_DDR, the multimedia domain VDD_MM, the I/O domain VDD_IO, and the RF domain VDD_RF are assigned priority P1as they are currently involved in the downloading, transferring, and processing of the data; the GPU domain VDD_GPU is assigned priority P2as it may be called upon to process some of the downloaded data; the NSP domain VDD_NSP is assigned priority P3as it is not currently performing or expected to perform any operation; and the SoC security domain VDD_SCR is assigned the critical priority P0. Accordingly, with reference toFIG.11A, the sharing domain core-11110may pertain to the P3domain VDD_NSP, and the borrowing domain core-21120may pertain to any of the P1domains VDD_DDR, VDD_MM, VDD_IO, and VDD_RF.

Referring again to the task timing diagram ofFIG.11B, the task of the (i+2)thtime interval as indicated by the task signal TSKi+2involves gaming. Accordingly, the NSP domain VDD_NSP, the multimedia domain VDD_MM, the RF domain VDD_RF, and the GPU domain VDD_GPU are assigned priority P1as they are currently involved in the gaming operation; the DDR memory domain VDD_DDR and the I/O domain VDD_IO are assigned priority P3as they are not currently performing or expected to perform any operation; and the SoC security domain VDD_SCR is assigned the critical priority P0. Accordingly, with reference toFIG.11A, the sharing domain core-11110may pertain to any of the P3domains VDD_DDR and VDD_IO, and the borrowing domain core-21120may pertain to any of the P1domains VDD_NSP, VDD_MM, VDD_RF, and VDD_GPU.

FIG.12illustrates a flow diagram of an example method1200of providing cross-domain power delivery in accordance with another aspect of the disclosure. The method1200includes coupling a bus resource of a first voltage bus to a second voltage bus in response to an actual or predicted voltage transient on the second voltage bus (block1210). The method1200further includes decoupling the bus resource from the second voltage bus in response to an absence of the actual or predicted voltage transient on the second voltage bus (block1220).

Aspect 1: An apparatus, comprising: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first signal indicating no actual or predicted voltage transient on the second voltage bus; and couple the bus resource to the second voltage bus based on the first signal indicating an actual or predicted voltage transient on the second voltage bus.

Aspect 2: The apparatus of aspect 1, wherein the first mode indicates an actual or predicted voltage transient on the second voltage bus, and the second mode indicates an absence of an actual or predicted voltage transient on the second voltage bus.

Aspect 3: The apparatus of aspect 1 or 2, wherein the bus resource comprises a set of one or more decoupling capacitors.

Aspect 4: The apparatus of aspect 3, wherein the set of one or more decoupling capacitors comprises one or more on-chip decoupling capacitors.

Aspect 5: The apparatus of aspect 3 or 4, wherein the set of one or more decoupling capacitors comprises one or more integrated circuit (IC) package decoupling capacitors.

Aspect 6: The apparatus of any one of aspects 3-5, wherein the set of one or more decoupling capacitors comprises one or more printed circuit board (PCB) decoupling capacitors.

Aspect 7: The apparatus of any one of aspects 3-6, wherein the set of one or more decoupling capacitors comprises one or more deep trench capacitors.

Aspect 8: The apparatus of any one of aspects 3-7, further comprising: a first switching device coupled between the set of one or more decoupling capacitors and the first voltage bus; and a second switching device coupled between the set of one or more decoupling capacitors and the second voltage bus; wherein the control circuit is configured to: close the first switching device and open the second switching device based on the first mode; and open the first switching device and close the second switching device based on the second mode.

Aspect 9: The apparatus of aspect 8, further comprising a diode or a voltage level shift circuit coupled in series with the second switching device between the set of one or more decoupling capacitors and the second voltage bus.

Aspect 10: The apparatus of aspect 8 or 9, wherein the set of one or more decoupling capacitors comprises a set of decoupling capacitors, and further comprising a set of switching devices coupled between the set of decoupling capacitors and ground, respectively, and wherein the control circuit is configured to open and close one or more of the set of switching devices based on the first or second mode.

Aspect 11: The apparatus of aspect 10, wherein the control circuit is configured to dynamically open and close a plurality of the set of switching devices based on the first or second mode.

Aspect 12: The apparatus of aspect 11, wherein the control circuit is configured to progressively close the plurality of the set of switching devices based on the first or second mode.

Aspect 13: The apparatus of aspect 11 or 12, wherein the control circuit is configured to progressively open the plurality of the set of switching devices based on the first or second mode.

Aspect 14: The apparatus of any one of aspects 1-13, wherein the bus resource comprises a voltage clamp or an electrostatic discharge (ESD) circuit.

Aspect 15: The apparatus of any one of aspects 1-14, wherein the bus resource comprises a first supply voltage on the first voltage bus.

Aspect 16: The apparatus of aspect 15, further comprising a circuit configured to boost a second supply voltage on the second voltage bus based on the first supply voltage.

Aspect 17: The apparatus of aspect 15 or 16, further comprising: a set of one or more capacitors each including an upper plate coupled to the second voltage bus; a first switching device coupled between the first voltage bus and a lower plate of each of the set of one or more capacitors; and a second switching device coupled between the lower plate of each of the set of one or more capacitors and ground; wherein the control circuit is configured to: open the first switching device and close the second switching device based on the first mode; and close the first switching device and open the second switching device based on the second mode.

Aspect 18: The apparatus of any one of aspects 1-17, further comprising a voltage transient detector including an input coupled to the second voltage bus, and an output coupled to the control circuit.

Aspect 19: The apparatus of any one of aspects 1-18, further comprising a reset timer configured to generate a signal related to an elapse time from the coupling of the bus resource to the second voltage bus, wherein the control circuit is configured to couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus in response to the signal indicating that the elapse time has reached a reset threshold.

Aspect 20: The apparatus of aspect 19, wherein the reset threshold is dynamic.

Aspect 21: The apparatus of any one of aspects 1-20, wherein the control circuit is configured to couple the bus resource to the second voltage bus during a first time interval based on a signal indicating that the first core is assigned a first priority allowing the first core to share the bus resource during the first time interval, and the second core is assigned a second priority allowing the second core to borrow the bus resource from the first core during the first time interval.

Aspect 22: The apparatus of aspect 21, wherein the control circuit is restricted from coupling the bus resource to the second voltage bus during a second time interval based on the signal indicating that the first core is assigned the second priority during the second time interval.

Aspect 23: The apparatus of aspect 22, wherein the first priority indicates that a corresponding core is not performing a task during a corresponding time interval, and the second priority indicates that the corresponding core is performing a task during the corresponding time interval.

Aspect 24: The apparatus of any one of aspects 1-23, wherein the first voltage bus is configured to receive a first supply voltage, wherein the second voltage bus is configured to receive a second supply voltage, and wherein the first supply voltage is substantially the same or greater than the second supply voltage.

Aspect 25: A method, comprising: coupling a bus resource of a first voltage bus to a second voltage bus in response to an actual or predicted voltage transient on the second voltage bus; and decoupling the bus resource from the second voltage bus in response to an absence of the actual or predicted voltage transient on the second voltage bus.

Aspect 26: The method of aspect 25, wherein the bus resource comprises one or more decoupling capacitors.

Aspect 27: The method of aspect 25 or 26, wherein the bus resource comprises a supply voltage or a voltage clamp.

Aspect 28: An apparatus, comprising: a power management integrated circuit (PMIC) including first and second voltage regulators; a first voltage bus coupled to the first voltage regulator of the PMIC; a second voltage bus coupled to the second voltage regulator of the PMIC; a first core coupled to the first voltage bus; a second core coupled to the second voltage bus; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first mode; and couple the bus resource to the second voltage bus based on a second mode.

Aspect 29: The apparatus of aspect 28, further comprising a system on chip (SoC) comprising the first core, the second core, and the control circuit.

Aspect 30: An apparatus, comprising: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first priority allowing the first core to share the bus resource and a second priority allowing the second core to borrow the bus resource from the first core.