Display panel

A display panel includes a display region and a peripheral region other than the display region. The display panel includes, in the peripheral region, a gate drive circuit and a first trunk line extending in a column direction. The first trunk line includes a first edge on a first side corresponding to the display region side in the row direction and a second edge on a second side corresponding to a side opposite to the display region in the row direction. The first trunk line includes a first portion and a second portion, each including the first edge and the second edge, and the first edge of the second portion is closer to the second side in the row direction than the first edge of the first portion. The first portion is not provided with an element, and the second portion includes a region provided with an element.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application Number 2022-168439 filed on Oct. 20, 2022. The entire contents of the above-identified application are hereby incorporated by reference.

BACKGROUND

Technical Field

The disclosure relates to a display panel.

Liquid crystal display panels are used in liquid crystal display devices for various applications, such as mobile terminal and television applications. Frame narrowing of a liquid crystal display panel is required from the viewpoint of reducing manufacturing costs and from the viewpoint of designability and functionality. By using a gate driver monolithic (GDM) technique in which a gate drive circuit (also referred to as a “gate driver”) is integrally formed on a TFT substrate, it is possible to reduce the cost for driver mounting and narrow the frame as compared to a case in which the gate drive circuit is mounted on the TFT substrate using chip on film (COF), chip on glass (COG), or the like. This GDM technique is sometimes referred to as gate on array (GOA).

WO 2011/104945, WO 2018/025412, and US 2021/272,949 disclose display devices to which the GDM technique is applied. In the display devices disclosed in WO 2011/104945, WO 2018/025412, and US 2021/272,949, a gate drive circuit and a trunk line group extending in a vertical direction and configured to supply signals to the gate drive circuit are provided in a region on the TFT substrate of the display panel corresponding to a region other than the display region of the display device (also referred to as a “peripheral region” or a “frame region”), that is, for example, a region on the left side and/or the right side of the display region.

SUMMARY

Improvement of the manufacturing yield of a display device to which a GDM technique is applied is in demand. As a factor that reduces the manufacturing yield, there is, for example, breakdown due to electrostatic discharge (ESD) in the manufacturing process of the display panel. Details will be described below.

An object of the disclosure is to provide a display panel in which the occurrence of a defect caused by ESD is suppressed.

According to embodiments of the disclosure, solutions described in the following items are provided.

A display panel includes a plurality of pixels arrayed in a matrix shape including a plurality of pixel rows and a plurality of pixel columns, a display region defined by the plurality of pixels, a peripheral region other than the display region, a gate drive circuit provided in the peripheral region and including a shift register including a plurality of stages respectively associated with the plurality of pixel rows, and a first trunk line provided in the peripheral region and extending in a column direction. The first trunk line includes, as edges on both sides of the first trunk line in a row direction, a first edge on a first side corresponding to the display region side in the row direction and a second edge on a second side corresponding to a side opposite to the display region in the row direction. The first trunk line includes a first portion and a second portion, each including the first edge and the second edge. The first edge of the second portion is closer to the second side in the row direction than the first edge of the first portion. The first portion is not provided with an element, and the second portion includes a region provided with an element.

The display panel according to item 1 further includes a second trunk line provided in the peripheral region, extending in the column direction, and positioned on a side of the first trunk line opposite to the display region. The first trunk line supplies a common signal to one or more first type stages included in the plurality of stages of the shift register. The second trunk line supplies another common signal to one or more second type stages included in the plurality of stages of the shift register. The second trunk line includes, as edges on both sides of the second trunk line in the row direction, a third edge on the display region side and a fourth edge on the side opposite to the display region. The second trunk line includes a third portion adjacent to the first portion of the first trunk line in the row direction and including the third edge and the fourth edge, and a fourth portion adjacent to the second portion of the first trunk line in the row direction and including the third edge and the fourth edge. The third portion includes a region provided with an element. The fourth portion is not provided with an element. The first trunk line supplies the common signal to the one or more first type stages via the element provided in the second portion. The second trunk line supplies the another common signal to the one or more second type stages via the element provided in the third portion.

In the display panel according to item 2, the second portion of the first trunk line is disposed in a formation region of one or more unit circuits respectively constituting the one or more first type stages, and the third portion of the second trunk line is disposed in a formation region of one or more unit circuits respectively constituting the one or more second type stages.

In the display panel according to item 2 or 3, a shape of the third edge of the second trunk line matches a shape of the second edge of the first trunk line, and a distance between the third edge of the second trunk line and the second edge of the first trunk line is substantially constant.

In the display panel according to any one of items 2 to 4, a width of the fourth portion of the second trunk line is smaller than a width of the third portion of the second trunk line.

In the display panel according to any one of items 1 to 5, the first trunk line further includes a coupling portion configured to couple the first portion and the second portion, the first portion and the second portion extend in the column direction, and the coupling portion extends in a direction different from the column direction.

In the display panel according to item 6, the first trunk line is bent between the first portion and the coupling portion and between the second portion and the coupling portion.

In the display panel according to any one of items 1 to 7, the first trunk line includes a plurality of electrostatic discharge (ESD) sacrificial portions protruding toward the display region side.

In the display panel according to item 8 citing item 7, the plurality of ESD sacrificial portions include an ESD sacrificial portion extending from a corner formed by the first portion and the coupling portion of the first trunk line toward the display region side.

In the display panel according to item 8 or 9, the plurality of ESD sacrificial portions are provided correspondingly to the plurality of stages of the shift register.

In the display panel according to any one of items 1 to 10, a width of the second portion of the first trunk line is equal to a width of the first portion of the first trunk line.

The display panel according to any one of items 1 to 11 further includes a substrate, a gate metal layer formed on the substrate, an insulating layer covering the gate metal layer, and a source metal layer formed on the insulating layer. The first trunk line is included in the gate metal layer.

In the display panel according to any one of items 1 to 12, the element is a thin film transistor (TFT) included in a unit circuit constituting the stage of the shift register.

According to an embodiment of the disclosure, provided is a display panel in which the occurrence of a defect caused by ESD is suppressed.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the disclosure will be described with reference to the accompanying drawings. Note that, although a liquid crystal display panel will be described below as an example of a display panel according to embodiments of the disclosure, the disclosure is not limited to the following embodiments. In the following drawings, constituent elements having substantially the same functions may be denoted by common reference signs, and description thereof may be omitted.

First Embodiment

A liquid crystal display panel1000aand a liquid crystal display device1100aincluding the liquid crystal display panel1000a(hereinafter also referred to as “display panel1000a” and “display device1100a”) according to the present embodiment will be described with reference toFIGS.1to4.FIG.1is a schematic view illustrating a configuration of the display device1100a.FIG.2is a schematic plan view of the display device1100a.FIG.3is a schematic plan view of the display panel1000a, and is a plan view schematically illustrating a portion of the display panel1000a.FIG.4is a schematic plan view of the display panel1000a, and is a plan view schematically illustrating a portion of a peripheral region NA and a display region AA.

As illustrated inFIGS.1and2, the display panel1000aincludes a plurality of pixels P arrayed in a matrix shape including a plurality of pixel rows and a plurality of pixel columns. Each pixel P is provided with a thin film transistor (TFT)1and a pixel electrode5electrically connected to the TFT. The pixel row is a plurality of the pixels P arrayed in a row direction (X direction inFIG.2), and the pixel column is a plurality of the pixels P arrayed in a column direction (Y direction inFIG.2). The display panel1000aincludes a TFT substrate101and a counter substrate201facing each other, and a liquid crystal layer provided between these substrates. The display panel1000aincludes a display region AA defined by the plurality of pixels P, and the peripheral region NA other than the display region AA. The peripheral region NA includes a first peripheral region NA1outward of the display region AA in the row direction, and a second peripheral region NA2outward of the display region AA in the column direction. The display device1100aincludes the display panel1000aand a circuit substrate510connected to the display panel1000a.

In this example, a gate bus line GL is associated with each of the plurality of pixel rows, and a source bus line SL is associated with each of the plurality of pixel columns. The TFT1of each pixel P is supplied with a gate signal from the corresponding gate bus line GL, and is supplied with a source signal from the corresponding source bus line SL. The pixel rows may be referred to as a first row, a second row, . . . , and an rx-th row in order from the top, and the gate bus line associated with the r-th pixel row (1≤r≤rx) may be referred to as a gate bus line GL (r) (seeFIG.1). Here, rx is the number of pixel rows included in the display panel1000a. The pixel in the r-th pixel row is selected by the scanning signal voltage supplied to the gate bus line GL (r). The gate bus line GL (r) associated with the r-th pixel row is connected to a gate electrode of the TFTs connected to the pixels included in the r-th pixel row. The pixel columns may be referred to as a first column, a second column, . . . , and a qy-th column in order from the left, and the source bus line SL associated with the q-th pixel column may be referred to as a source bus line SL (q). Here, qy is the number of pixel columns included in the display panel1000a. A display signal voltage is supplied from the source bus line SL (q) to the pixels in the q-th pixel column (1≤q≤qy). The source bus line SL (q) associated with the q-th pixel column is connected to a source electrode of the TFTs connected to the pixels included in the q-th pixel column.

The display panel1000aincludes a gate drive circuit GD. Herein, the gate drive circuit GD is integrally formed on the TFT substrate101(gate driver monolithic). The gate drive circuit GD is provided in the first peripheral region NA1of the display panel1000aand includes a shift register110provided with a plurality of stages respectively associated with the plurality of pixel rows. Outputs of each stage of the shift register110are connected to the gate bus lines GL respectively associated with the plurality of pixel rows. Typically, the shift register110includes rx stages and, given that the first stage, the second stage, . . . , and the rx-th stage are arranged in this order from the top, the output of the r-th stage (1≤r≤rx) is connected to the gate bus line GL (r). In addition to the rx stages, the shift register110may further include one or more dummy stages adjacent to the rx stages in the column direction and not contributing to display. The shift register110is configured by cascade-connecting a plurality of unit circuits QC. Each stage of the shift register110is configured by each unit circuit QC. The unit circuit QC constituting each stage of the shift register110includes at least one TFT (semiconductor element).

The display panel1000aincludes a first trunk line134provided in the peripheral region NA and extending in the column direction. The first trunk line134has a shape such as the following. The first trunk line134includes, among edges on both sides of the first trunk line134in the row direction, a first edge ea on the display region AA side and a second edge eb on the side opposite to the display region. In the row direction, the display region AA side may be referred to as a first side, and the other side opposite to the display region AA may be referred to as a second side. That is, the first edge ea is on the first side in the row direction, and the second edge eb is on the second side in the row direction. The first trunk line134includes a first portion134A and a second portion134B, each including the first edge ea and the second edge eb. The second portion134B can be regarded as positioned in the column direction of the first portion134A. In the present specification, the “column direction” includes a direction parallel to a +Y direction and a −Y direction unless otherwise specified. Here, the direction of the arrow of the Y axis in the drawing is referred to as the +Y direction, and the opposite direction is referred to as the −Y direction. Similarly, the “row direction” includes a direction parallel to a +X direction and a −X direction unless otherwise specified. Here, the direction of the arrow of the X axis in the drawing is referred to as the +X direction, and the opposite direction is referred to as the −X direction. In the illustrated example, in the peripheral region NA (FIGS.3and4) on the left side of the display region AA, the first side in the row direction is the +X direction, and the second side in the row direction is the −X direction. In the peripheral region NA on the right side of the display region AA, the first side in the row direction is the −X direction, and the second side in the row direction is the +X direction. The first edge ea of the second portion134B is farther on the second side in the row direction than the first edge ea of the first portion134A. For example, the first edge ea of the second portion134B is farther from the display region AA than the first edge ea of the first portion134A. The first portion134A is not provided with an element (here, a TFT included in the unit circuit QC). The second portion134B includes a region provided with an element (here, a TFT10bincluded in the unit circuit QC). The first portion134A and the second portion134B may not be continuous. In this example, the first trunk line134further includes a coupling portion134cbetween the first portion134A and the second portion134B. The first trunk line134may include portions other than the first portion134A, the second portion134B, and the coupling portion134c. Here, the TFT included in the unit circuit QC included in each of the plurality of stages of the shift register110is illustrated as an example of the element, but the element is not limited thereto and may be another circuit element (for example, a capacitance element).

The display panel1000afurther includes a second trunk line132provided in the peripheral region NA and extending in the column direction. The second trunk line132is positioned on the side of the first trunk line134opposite to the display region AA. That is, the first trunk line134is positioned between the display region AA and the second trunk line132. The first trunk line134and the second trunk line132are used to supply a signal to each of the plurality of stages of the shift register110. The first trunk line134supplies a common signal to one or more first type stages included in the plurality of stages. The second trunk line132supplies another common signal to one or more second type stages included in the plurality of stages. That is, among the plurality of stages included in the shift register110, a stage supplied with a signal from the first trunk line134is referred to as a “first type stage”, and a stage supplied with a signal from the second trunk line132is referred to as a “second type stage”. The first trunk line134and the second trunk line132are electrically independent from each other, making it possible to supply signals different from each other to the first type stages and the second type stages. The first trunk line134and the second trunk line132are used to supply a clear signal (reset signal) to each stage of the shift register110, for example. The gate start pulse signal GSP and/or the gate end pulse signal GEP may be used as the clear signal. For example, the gate end pulse signal GEP is supplied as the clear signal to the first type stage, and the gate start pulse signal GSP is supplied as the clear signal to the second type stage.

FIG.4illustrates an (n+1)th stage S(n+1) to an (n+4)th stage S(n+4) among the plurality of stages included in the shift register110. The first number x in the parenthesis after the reference numeral of the stage S corresponds to the x-th stage of the shift register110, and the letter (“A” or “B”) following the number x in the parenthesis indicates whether the x-th stage is the first type stage or the second type stage, indicating “B” when the x-th stage is the first type stage and “A” when the x-th stage is the second type stage. The unit circuit constituting each of the (n+3)th stage and the (n+4)th stage, which are the first type stages, includes the TFT10b, and the unit circuit constituting each of the (n+1)th stage and the (n+2)th stage, which are the second type stages, includes a TFT10a. The second portion134B of the first trunk line134includes a region provided with the TFT10b, that is, includes a portion constituting the TFT10b(for example, a portion functioning as a gate electrode of the TFT10b). Comb-shaped electrodes formed by electrodes36b,36dare a source electrode and a drain electrode of the TFT10bthat uses the first trunk line134as the gate electrode. The first trunk line134supplies a common signal to the first type stage via the TFT10bprovided in the second portion134B. The first portion134A of the first trunk line134is disposed, for example, in a formation region of the unit circuit QC constituting the second type stage. Further, the second portion134B of the first trunk line134is disposed, for example, in a formation region of the unit circuit QC constituting the first type stage. However, the first trunk line134may be provided farther on the second side (that is, the side opposite to the display region AA) in the row direction than the shift register110. Further, a portion of the first trunk line134disposed in the formation region of the unit circuit QC constituting the first type stage may include a portion other than the second portion134B (for example, a portion in which the position of the first edge ea in the row direction is the same as that of the first portion134A or a portion in which the position of the first edge ea in the row direction changes (coupling portion134c)). Similarly, the portion of the first trunk line134disposed in the formation region of the unit circuit QC constituting the second type stage may include a portion other than the first portion134A.

The second trunk line132includes a third portion132A adjacent to the first portion134A of the first trunk line134in the row direction and including a third edge ec and a fourth edge ed, and a fourth portion132B adjacent to the second portion134B of the first trunk line134in the row direction and including the third edge ec and the fourth edge ed. The third portion132A includes a region provided with the TFT10aincluded in the unit circuit QC. That is, the third portion132A includes a portion constituting the TFT10a(for example, a portion functioning as a gate electrode of the TFT10a). Comb-shaped electrodes formed by electrodes36a,36care a source electrode and a drain electrode of the TFT10athat uses the second trunk line132as the gate electrode. The fourth portion132B is not provided with a TFT included in the unit circuit QC. The second trunk line132supplies another common signal to the second type stage via the TFT10aprovided in the third portion132A. The third portion132A of the second trunk line132is disposed, for example, in the formation region of the unit circuit QC constituting the second type stage. Further, the fourth portion132B of the second trunk line132is disposed, for example, in the formation region of the unit circuit QC constituting the first type stage. However, the second trunk line132may be provided farther on the second side (that is, the side opposite to the display region AA) in the row direction than the shift register110. Further, a portion of the second trunk line132disposed in the formation region of the unit circuit QC constituting the second type stage may include a portion other than the third portion132A (for example, a portion in which the position of the third edge ec in the row direction is the same as that of the fourth portion132B or a portion in which the position of the third edge ec in the row direction changes (coupling portion132c)). Similarly, the portion of the second trunk line132disposed in the formation region of the unit circuit QC constituting the first type stage may include a portion other than the fourth portion132B.

The reason that the display panel1000acan suppress the occurrence of a defect caused by ESD will now be described while comparing the display panel1000awith a display panel of a comparative example.FIG.5is a schematic plan view of a display panel900aof a comparative example, and corresponds to the schematic plan view of the display panel1000aillustrated inFIG.4.FIGS.4and5partially illustrate the first peripheral region NA1disposed on the left side of the display region AA, and the display region AA. Hereinafter, the same applies to similar drawings. In the display panel900aof the comparative example, the shapes of a first trunk line934and a second trunk line932differ from those of the first trunk line134and the second trunk line132of the display panel1000a. According to a study by the present inventors, in the display panel900aof the comparative example, it is not possible to sufficiently suppress defects caused by ESD.

An insulating layer (gate insulating layer) and a semiconductor layer (34a,34b) are formed on a gate metal layer (first trunk line134or first trunk line934, second trunk line132or second trunk line932, conductive portion32a), and a source metal layer (electrodes36a,36b,36c,36d) is formed thereon.

For example, in the process of forming TFTs on the TFT substrate101within the process of manufacturing the substrate, when a gate insulating film and a semiconductor film are formed and patterned after formation of the gate metal layer on the substrate, ESD may occur between the patterns on the gate metal layer. In particular, when the display panel is large, the area occupied by the gate metal (portion where a conductor actually exists) of the gate metal layer increases, increasing the amount of charge accumulated in the gate metal. The charge accumulated in the gate metal provided in the display region AA of the gate metal layer jumps outwardly from the display region AA side (that is, toward the peripheral region side), fusing the gate metal on the side receiving the charge and breaking the insulating film. When a source metal is formed on the fused portion in a subsequent process, a short circuit occurs on the fused portion. When the charge accumulated in the gate metal (gate bus line GL) provided in the display region AA jumps to the first trunk line934(dotted arrow inFIG.5), a portion of the first trunk line934is fused and the insulating film is broken (ESD inFIG.5). This ESD occurs between adjacent patterns of the gate metal layer when the gate insulating film and the semiconductor film are formed and patterned after the gate metal layer is formed (that is, after the gate metal film is deposited and patterned). The probability of occurrence of ESD tends to increase as a distance between the patterns of the gate metal layer decreases. When the source metal is formed on the fused portion of the gate metal in a subsequent process, a short circuit between the source metal and the gate metal (hereinafter referred to as an “S-G short circuit” for simplicity) occurs on the fused portion. The probability that ESD occurs between the first trunk line934and the conductive portion32ais high, and thus an S-G short circuit is likely to occur in the TFT10bformed overlapping the first trunk line934. The conductive portion32ais a portion of the gate metal, and is disposed in the vicinity of the first edge ea of the first trunk line934. The conductive portion32ais not electrically connected to the gate bus line GL. The charge accumulated in the gate bus line GL repeatedly jumps to the gate metal disposed in close proximity but not electrically connected to the gate bus line GL, and thus the conductive portion32acan be a starting point of ESD to the first trunk line934.

In contrast, the display panel1000aaccording to the embodiment of the disclosure can suppress the occurrence of an S-G short circuit in the TFT10b. In the display panel1000a, the first edge ea of the second portion134B of the first trunk line134is farther from the display region AA than the first edge ea of the first portion134A, making it possible to suppress the S-G short circuit of the TFT10bcaused by ESD. The display panel1000acan improve the manufacturing yield.FIG.4illustrates a difference D1zbetween a distance between the second portion134B of the first trunk line134and the display region AA and a distance between the first portion134A of the first trunk line134and the display region AA. In the display panel1000a, the distance between the first trunk line134and the conductive portion32ais longer by D1zcompared to that of the display panel900aof the comparative example, making it possible to suppress the probability of occurrence of ESD between the first trunk line134and the conductive portion32a.

In this example, the first trunk line134further includes the coupling portion134ccoupling the first portion134A and the second portion134B. The first portion134A and the second portion134B extend in the column direction (Y direction in the drawing), and the coupling portion134ccoupling these portions extends in a direction different from the column direction. The first trunk line134is bent between the first portion134A and the coupling portion134cand between the second portion134B and the coupling portion134c. The widths of the first portion134A of the first trunk line134and the second portion134B of the first trunk line134may be, for example, equal to each other or may be different from each other. The shape of the first trunk line134is not limited to the example illustrated in the drawing, and only the difference D1zbetween the distance between the second portion134B of the first trunk line134and the display region AA and the distance between the first portion134A of the first trunk line134and the display region AA need be formed. For example, the first trunk line134may be smoothly curved between the second portion134B and the first portion134A. When the first trunk line134includes the coupling portion134c, the second trunk line132further includes a coupling portion132cadjacent to the coupling portion134cof the first trunk line134in the row direction.

Among edges on both sides of the second trunk line132in the row direction, an edge on the display region AA side is referred to as a third edge ec, and an edge on the side opposite to the display region AA is referred to as a fourth edge ed. A shape of the third edge ec of the second trunk line132matches a shape of the second edge eb of the first trunk line134. Accordingly, the third edge ec of the fourth portion132B of the second trunk line132is farther from the display region AA than the third edge ec of the third portion132A of the second trunk line132. A distance between the third edge ec of the second trunk line132and the second edge eb of the first trunk line134is substantially constant. Here, the distance between the third edge ec of the second trunk line132and the second edge eb of the first trunk line134is assumed to be the same as the distance between the third edge ec of the second trunk line932and the second edge eb of the first trunk line934of the display panel900aof the comparative example. A width D2bof the fourth portion132B of the second trunk line132is smaller than a width D2aof the third portion132A of the second trunk line132. With the second trunk line132having such a shape, the display panel1000acan suppress the occurrence of a defect caused by ESD while suppressing an increase in the area of the peripheral region NA (in particular, the first peripheral region NA1), that is, without sacrificing realization of frame narrowing of the display panel, as compared with the display panel900aof the comparative example.

Structures of the display panel1000aand the display device1100awill now be described in more detail.

As illustrated inFIG.2, the circuit substrate510includes a control circuit CNTL that supplies a control signal to the gate drive circuit GD. For example, the control circuit CNTL is mounted on the circuit substrate510. The circuit substrate510is connected to a terminal portion TP formed in the second peripheral region NA2of the display panel1000avia a source substrate520. The circuit substrate510is connected to the source substrate520via flexible printed circuits (FPCs)512. The terminal portion TP is provided with a terminal electrically connected to each trunk line for supplying a signal to the gate drive circuit GD. The circuit substrate510supplies, via the source substrate520, a signal from the terminal portion TP of the display panel1000ato each trunk line for supplying a signal to the gate drive circuit GD. In this example, the circuit substrate510is connected to the display panel1000avia a plurality of the source substrates520. Each of the source substrates520(printed wiring boards) is connected to the display panel1000avia a plurality of the flexible circuit boards522, and source drive circuits SD for supplying a display signal voltage to the source bus lines SL are mounted on the flexible circuit boards522. Note that, inFIG.2, the source bus lines SL are not illustrated for ease of understanding. The control circuit CNTL also supplies control signals to the source drive circuits SD, for example. The control signals supplied from the control circuit CNTL to the gate drive circuit GD include, for example, a gate start pulse signal GSP, a gate clock signal GCK, and a gate end pulse signal GEP. The control signals supplied from the control circuit CNTL to the source drive circuits SD include, for example, a source start pulse signal SSP and a source clock signal SCK. Note that the arrangement and connection method of the source drive circuits SD and the control circuit CNTL are not limited to those illustrated in the drawing. Further, although the gate drive circuit GD and the wiring lines for supplying signals to the gate drive circuit GD are provided on both the left and right sides of the display region AA inFIG.2, the gate drive circuit GD and the wiring lines for supplying signals to the gate drive circuit GD may be provided on only one of the left and right sides of the display region AA.

FIG.3illustrates the wiring lines for inputting signals to the shift register110in more detail. The display panel1000afurther includes the following wiring lines provided in the first peripheral region NA1for supplying signals to the gate drive circuit GD. Specifically, the display panel1000aincludes n clock trunk lines CKL1to CKLn, each extending in the column direction and supplying n types (where n is an integer of 2 or greater) of clock signals having phases different from each other to the plurality of stages of the shift register110, an outer trunk line122and an inner trunk line124, each extending in the column direction and supplying a common signal to the plurality of stages of the shift register110, and a plurality of branch wiring lines140, each electrically connecting the outer trunk line122and the inner trunk line124. The terminal portions TP in the second peripheral region NA2of the display panel1000aare provided with terminals (n clock trunk line terminals and n outer trunk line terminals) electrically connected to the n clock trunk lines CKL1to CKLn and the outer trunk line122, respectively. The n clock trunk lines CKL1to CKLn may be collectively referred to as clock trunk lines CKL.

In the example ofFIG.3, eight clock trunk lines CKL1to CKL8are provided as the n clock trunk lines CKL1to CKLn (n=8). Given that the gate clock signals GCK supplied from the clock trunk lines CKL1to CKL8are GCK1to GCK8, the gate clock signals GCK1to GCK8are, for example, oscillating voltages having a cycle of 8H (1H is one horizontal scanning period) and a duty ratio of 1:1 (of the 8Hs of one cycle, 4Hs are at high level, and 4Hs are at low level), and the phases differ for each 1H. For example, a low-level potential Vg1is −7 V and a high-level potential Vgh is 35 V. The terminal portions TP in the second peripheral region NA2of the display panel1000aare provided with terminals (eight clock trunk line terminals) electrically connected to the clock trunk lines CKL1to CKL8, respectively, and the control circuit CNTL respectively supplies the gate clock signals GCK1to GCK8to the clock trunk lines CKL1to CKL8connected via the clock trunk line terminals. The clock trunk lines CKL1to CKL8and the inputs (input terminals) of the stages of the shift register110are electrically connected to each other via wiring lines154extending in the row direction, and thus the gate clock signals GCK1to GCK8are supplied to the inputs of the stages of the shift register110. An example of a connection relationship between the input of each stage of the shift register110and the n clock trunk lines CKL1to CKLn is as follows. For example, the inputs of the first to eighth stages are supplied with the gate clock signals GCK1to GCK8from the clock trunk lines CKL1to CKL8, respectively, the inputs of the ninth to 16th stages are supplied with the gate clock signals GCK1to GCK8from the clock trunk lines CKL1to CKL8, respectively, the inputs of the 17th to 24th stages are supplied with the gate clock signals GCK1to GCK8from the clock trunk lines CKL1to CKL8, respectively, and so on. That is, the input of the {(a×n)+k}-th stage of the shift register110is supplied with the gate clock signal GCKk from the clock trunk line CKLk (where a is an integer of 0 or greater, and k is an integer from 0 to n−1).

The outer trunk line122and the inner trunk line124are for supplying, for example, a signal for applying a low-level potential (for example, VSS=−7 V) to the plurality of stages of the shift register110. A signal for applying a fixed potential (for example, a signal for applying the low-level potential VSS) is supplied from the control circuit CNTL to the outer trunk line122connected via the outer trunk line terminal. With the outer trunk line122and the inner trunk line124being electrically connected via the branch wiring lines140, and the inner trunk line124and the input (input terminal) of each stage of the shift register110being electrically connected via the wiring line152, a signal for applying the low-level potential VSS is supplied to the input of each stage of the shift register110.

The display panel1000amay further include an additional trunk line121provided in the first peripheral region NA1, extending in the column direction, and supplying another common signal to the plurality of stages of the shift register110. In this case, signals for applying two kinds of low-level potentials (for example, VSS1=−12 V and VSS2=−7 V) are supplied from the control circuit CNTL. The outer trunk line122and the inner trunk line124supply signals for applying the low-level potential VSS2to the plurality of stages of the shift register110, and the trunk line121supplies a signal for applying the low-level potential VSS1to the plurality of stages of the shift register110.

Note that the outer trunk line122and the inner trunk line124may be for supplying, for example, a signal VD for applying a high-level potential (which may be different from Vgh) to the plurality of stages of the shift register110. The signal VD for applying a high-level potential may be supplied from the control circuit CNTL to the outer trunk line122connected via the outer trunk line terminal.

In this example, the inner trunk line124is disposed farther from the display region AA than the shift register110, and the outer trunk line122is disposed farther from the display region AA than the inner trunk line124. The eight clock trunk lines CKL1to CKL8are provided between the outer trunk line122and the inner trunk line124. A width of the outer trunk line122in the row direction is typically larger than a width of the inner trunk line124in the row direction.

Second Embodiment

A display panel1000baccording to the present embodiment will now be described with reference toFIG.6.FIG.6is a schematic plan view of the display panel1000b, and is a plan view schematically illustrating a portion of the peripheral region NA and the display region AA.FIG.6is a view corresponding to the schematic plan view of the display panel1000aillustrated inFIG.4. The following mainly describes differences from the previous embodiment.

In the display panel1000b, the first trunk line134includes a plurality of ESD sacrificial portions134xprotruding toward the display region AA side. The plurality of ESD sacrificial portions134xare provided correspondingly to each stage of the shift register110, for example. The “ESD sacrificial portion” is an additional portion not necessary for a wiring line or an electrode to perform its function, and is provided at a position where an ESD defect is more likely to occur compared to a portion (wiring line main body or electrode main body) necessary for the wiring line or the electrode to perform its function.

The display panel1000bcan suppress the occurrence of a defect caused by ESD, similarly to the display panel1000a. The display panel1000bwill now be described while comparing the display panel1000bwith a display panel900bof a comparative example.FIG.7is a schematic plan view of the display panel900bof a comparative example, and is a schematic plan view schematically illustrating a portion of the peripheral region NA and the display region AA. In the display panel900bof the comparative example, the shapes of the first trunk line934and the second trunk line932differ from those of the first trunk line134and the second trunk line132of the display panel1000b.

A plurality of ESD sacrificial portions32xare also provided on the first trunk line934side (side opposite to the display region AA side) of the conductive portion32aso as to face the plurality of ESD sacrificial portions134xprovided on the first trunk line934. The ESD sacrificial portions134xof the first trunk line934and the ESD sacrificial portions32xof the conductive portion32aare in close proximity to each other, resulting in a high possibility that ESD occurs therebetween. That is, the charge accumulated in the gate metal provided in the display region AA is highly likely to jump to the ESD sacrificial portion134xof the first trunk line934. According to a study by the present inventors, when a charge that jumped to the ESD sacrificial portion134xof the first trunk line934further jumps to a portion of the TFT10bof the first trunk line934functioning as the gate electrode, a portion of the first trunk line934may be fused and the insulating film may break (ESD inFIG.7). When the source metal is formed on the fused portion of the gate metal in a subsequent process, an S-G short circuit occurs on the fused portion. In this way, an S-G short circuit may occur in the TFT10b.

In contrast, in the display panel1000b, the first edge ea of the second portion134B of the first trunk line134is farther from the display region AA than the first edge ea of the first portion134A. Accordingly, a distance from a tip of the ESD sacrificial portion134xprovided in the first trunk line134to the TFT10bis long, making it possible to suppress the S-G short circuit of the TFT10b. Preferably, the ESD sacrificial portion134xprovided in the first portion134A of the first trunk line134and the ESD sacrificial portion134xprovided in the second portion134B of the first trunk line134have the same distance from the tips thereof to the display region AA.

For example, when the display panel is large, the area occupied by the first trunk line134in the gate metal of the gate metal layer is large, and thus a charge is also accumulated in the first trunk line134, which may be one of the factors causing ESD. To suppress the charge from jumping from a corner formed by the first portion134A of the first trunk line134and the coupling portion134c, preferably the plurality of ESD sacrificial portions134xinclude an ESD sacrificial portion134xextending from a corner formed by the first portion134A of the first trunk line134and the coupling portion134cto the display region AA side.

The display panel according to the embodiments of the disclosure is widely applied to active matrix display panels such as a liquid crystal display panel and an organic EL display panel. When the display panel according to the embodiment of the disclosure is applied, the manufacturing yield of the active matrix display panel can be improved.