Driver and driving method, and display device

The present invention provides a driver, including: data lines disposed in parallel with each other; gate lines disposed in parallel with each other and at right angles to the data lines so as to be electrically insulated from the data lines; odd-numbered pixel cell connected to the odd-numbered data line from the head one, and the odd-numbered gate line from the head one; even-numbered pixel cell connected to the even-numbered data line from the head one, and the even-numbered gate line from the head one; driving means for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other; inputting means for inputting a signal having a predetermined potential to each of the odd-numbered gate lines and the even-numbered gate lines; and comparing means for comparing potentials of the each adjacent odd-numbered data line and even-numbered data line with each other, and outputting a comparison result.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2007-016582 filed in the Japan Patent Office on Jan. 26, 2007, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a driver and a driving method, and a display device, and more particularly to a driver and a driving method each of which is capable of more precisely detecting a fault caused on a semiconductor substrate or an insulating substrate having pixel cells disposed in matrix therein, and a display device.

2. Description of the Related Art

In recent years, an active matrix system has been widely adopted in liquid crystal display devices such as a liquid crystal projector device and a liquid crystal display device.

FIG. 1shows an example of a structure of a semiconductor substrate10of a liquid crystal display device adopting the active matrix system.

The semiconductor substrate10shown inFIG. 1is provided with a display circuit11, a data line driving circuit12, and a gate line driving circuit13. Note that, a portion about display of a region having nine pixels in total within a screen in which three pixels are horizontally disposed and three pixels are vertically disposed is described with reference toFIG. 1for the sake of convenience of the description. However, any other portion about display is structured similarly to the case of the portion about display shown inFIG. 1.

The display circuit11is structured such that pixel cells21-1to21-9are disposed in matrix within the screen in which three pixel cells are horizontally disposed, and three pixel cells are vertically disposed. It is noted that when there is no necessity for individually distinguishing the pixel cells21-1to21-9from one another in the following description, the pixel cells21-1to21-9are collectively referred to as “the pixel cells21”.

The pixel cells21are connected to the data line driving circuit12through data lines Dn−1, Dnand Dn+1(n: odd number), respectively, which are disposed in parallel on the semiconductor substrate10so as to be insulated from one another. Here, a suffix added to D represents what number the data line concerned belongs to in a direction from a left-hand side to a right-hand side in the figure (in a horizontal direction in the figure).

In addition, the pixel cell21is connected to the gate line driving circuit13through corresponding one of gate lines Gm−1, Gmand Gm+1(m: odd number) which are disposed in parallel on the semiconductor substrate10so as to be electrically insulated from the data lines Dn−1, Dnand Dn+1and so as to make right angles to the data lines Dn−1, Dnand Dn+1. Here, a suffix added to G represents what number the data line concerned belongs to in a direction from an upper side to a lower side in the figure (in a vertical direction in the figure).

It is noted that when there is no necessity for individually distinguishing the data lines Dn−1, Dnand Dn+1from one another in the following description, the data lines Dn−1, Dnand Dn+1are collectively referred to as “the data lines D”, and also when there is no necessity for individually distinguishing the gate lines Gm−1, Gmand Gm+1from one another in the following description, the gate lines Gm−1, Gmand Gm+1are collectively referred to as “the gate lines G”.

The pixel cell21-1is composed of a switch31, an electrode32, and a capacitor33. The switch31, for example, is constituted by a field effect transistor (FET). A gate of the switch31is connected to the gate line Gm−1, and a drain thereof is connected to the data line Dn−1. In addition, a source of the switch31is connected to each of the electrode32and one end of the capacitor33, and the other end of the capacitor33is connected to a common electrode.

In the pixel cell21-1, when the switch31is turned ON by drive of the gate line Gm−1, the charges are accumulated in the capacitor33based on a potential of a signal which is inputted to the switch31by drive of the data line Dn−1. That is to say, data is written to the capacitor33. Also, the switch31is turned OFF by stopping the drive of the gate line Gm−1, so that the capacitor33holds therein data thus written thereto.

At this time, a potential Pm−1n−1at the electrode32is one developed at the one terminal of the capacitor33connected to that electrode32. A liquid crystal held between the semiconductor substrate10and a counter substrate (not shown) makes a response to be exited in correspondence to a difference between the potential Pm−1n−1and a potential of the counter substrate. Here, the counter substrate is a semiconductor substrate which is disposed so as to face the semiconductor substrate10, and which has the common electrode. As a result, the pixel corresponding to the pixel cell21-1is activated for display. It is noted that while a description is omitted here for the sake of simplicity, each of the pixel cells21other than the pixel cell21-1is structured similarly to the case of the pixel cell21-1and similarly operates.

The data line driving circuit12, for example, is provided with a shift register and the like. The data line driving circuit12successively shifts data which is inputted thereto from the outside every horizontal line to scan the data lines D in the horizontal direction, thereby successively driving the data lines D.

The gate line driving circuit13, for example, is provided with a shift register and the like. The gate line driving circuit13successively shifts data which is inputted thereto for control for the scanning from the outside, thereby successively driving the gate lines Gm−1, Gmand Gm+1every period of time for the horizontal scanning. As a result, the switches31of the pixel cells21are turned ON in order in units of the switches31of the pixel cells21disposed in the horizontal direction, so that a horizontal line as a scanning object moves vertically.

The data line driving circuit12and the gate line driving circuit13carry out the drive in the manner as described above, which results in that the data is successively written to the capacitors33of the pixel cells21to excite the liquid crystal, thereby displaying a desired image on the screen.

Now, in such a semiconductor substrate, a line fault such as short circuit or disconnection may be caused in manufacturing processes. For this reason, it is inspected whether or not the line fault is caused on the semiconductor substrate in the manufacturing processes.

FIG. 2shows an example of a structure of a semiconductor substrate40which is provided with a detection circuit for detecting a fault for the inspection. It is noted that the same constituent elements as those shown inFIG. 1are designated with the same reference numerals, respectively, and a repeated description thereof is omitted here for the sake of simplicity.

In the semiconductor substrate40, a detection circuit41is provided across the display circuit11from the data line driving circuit12.

The detection circuit41detects the line fault caused on the semiconductor substrate40by utilizing a predetermined detecting method. The following detecting method, for example, is known in the art as this detecting method. That is to say, an AND gate is provided as a detection circuit, and a signal having a predetermined potential is applied across adjacent two data lines or gate lines. Also, the line fault caused on the semiconductor substrate40is detected based on a logical product of logical values corresponding to potentials of the adjacent two data lines or gate lines after application of the signal having the predetermined potential across them. This detecting method, for example, is described in Japanese Patent Laid-Open No. 2005-43661.

In addition, another detecting method is known in the art as follows. That is to say, the line fault caused on the semiconductor substrate40is detected based on a change in potential before and after an operation for reading out charges accumulated in the capacitor33in a phase of write of data to the data line D which has an arbitrary voltage applied thereto, and which is set in a high impedance state.

However, the recent liquid crystal display devices for which a high definition is advanced involve the following problem. That is to say, a ratio of a capacity of the capacitor33to a parasitic capacity of the data line is equal to or larger than 1:200. Also, the potential change before and after the reading-out operation is minute. As a result, the detection results are readily influenced by noises.

In order to cope with this problem, there is also devised a detecting method of detecting a line fault caused on a semiconductor substrate based on a comparison of potential changes, before and after an reading-out operation, appearing across adjacent two data lines or gate lines.

SUMMARY OF THE INVENTION

However, with this detecting method, the line fault in one of the data lines or gate lines may not be detected in some cases because the comparison results become identical to those when no line fault is caused.

The present invention has been made in the light of such circumstances, and it is therefore desirable to provide a driver and a driving method each of which is capable of more precisely detecting a fault caused on a semiconductor substrate or an insulating substrate having pixel cells disposed in matrix therein.

According to an embodiment of the present invention, there is provided a driver, including: at least two data lines disposed in parallel with each other; at least two gate lines disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines; odd-numbered pixel cells as at least one pixel cell connected to the odd-numbered data lines from the head one, and the odd-numbered gate lines from the head one; even-numbered pixel cells as at least one pixel cell connected to the even-numbered data lines from the head one, and the even-numbered gate lines from the head one. The driver further includes: driving means for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other; inputting means for inputting a signal having a predetermined potential to each of the odd-numbered gate lines and the even-numbered gate lines; and comparing means for comparing potentials of the each adjacent odd-numbered data line and even-numbered data line with each other, and outputting a comparison result. The odd-numbered pixel cells and the even-numbered pixel cells are disposed in matrix; each of the odd-numbered pixel cells and the even-numbered pixel cells includes accumulating means for accumulating therein charges based on a potential of a signal corresponding to pixel data inputted through corresponding one of the data lines connected thereto, and connecting means for connecting the corresponding one of the data lines connected thereto and the accumulating section to each other based on a potential of corresponding one of the data lines connected thereto. The driver further includes: the at least two data lines, the at least two gate lines, the odd-numbered pixel cells, the even-numbered pixel cells, the driving means, the inputting means, and the comparing means are disposed either on a semiconductor substrate or on an insulating substrate.

According to the embodiment of the present invention, the driver includes the at least two data lines disposed in parallel with each other, the at least two gate lines disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines, the odd-numbered pixel cells as at least one pixel cell connected to the odd-numbered data lines from the head one and the odd-numbered gate lines from the head one, and the even-number pixel cells as at least one pixel cell connected to the even-numbered data lines from the head one and the even-numbered gate lines from the head one. In addition, the odd-numbered gate lines and the even-numbered gate lines are driven independently of each other. The signal having the predetermined potential is inputted to each of the odd-numbered data lines and the even-numbered data lines. Also, the potentials of the each adjacent odd-numbered data line and even-numbered data line are compared with each other, and the comparison result is outputted.

According to another embodiment of the present invention, there is provided a driving method for a driver in which at least two data lines disposed in parallel with each other, at least two gate lines disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines, odd-numbered pixel cells as at least one pixel cell connected to the odd-numbered data lines from the head one and the odd-numbered gate lines from the head one, and even-numbered pixel cells as at least one pixel cell connected to the even-numbered data lines from the head one and the even-numbered gate lines from the head one are provided either on a semiconductor substrate or on an insulating substrate, the odd-numbered pixel cells and the even-numbered pixel cells being disposed in matrix. The driving method includes the steps of: driving the odd-numbered gate lines and the even-numbered gate lines adjacent thereto; accumulating charges in each of the odd-numbered pixel cells based on a first potential of each of the odd-numbered data lines, and accumulating charges in each of the even-numbered pixel cells based on a second potential of each of the even-numbered data lines in accordance with the drive; stopping the drive for the odd-numbered gate lines and the even-numbered gate lines adjacent thereto; stopping the accumulation of the charges in each of the odd-numbered pixel cells and the even-numbered pixel cells in accordance with the stop of the drive to hold the charges in each of the odd-numbered pixel cells and the even-numbered pixel cells. The driving method further includes the steps of: setting a potential of each of the odd-numbered data lines and the even-numbered data lines adjacent thereto at a predetermined potential; setting each of the odd-numbered data lines and the even-numbered data lines adjacent thereto in a high impedance state; driving ones of the odd-numbered gate lines and the even-numbered gate lines adjacent thereto as a drive object; outputting the charges accumulated in the odd-numbered pixel cells or the even-numbered pixel cells connected to the drive object to the odd-numbered data lines or the even-numbered data lines in accordance with the drive; comparing potentials of the each adjacent odd-numbered data line and even-numbered data line with each other; and executing one side processing as processing.

According to the another embodiment of the present invention, in the driving method for the driver, there are driven the odd-numbered gate lines from the head one of the at least two gate lines disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines disposed in parallel with each other, and the even-numbered gate lines from the head one adjacent thereto. In addition, the charges are accumulated in each of the odd-numbered pixel cells as the at least one pixel cell connected to the odd-numbered data lines from the head one and the odd-numbered gate lines from the head one based on the first potential of each of the odd-numbered data lines from the head one in accordance with that drive. Also, the charges are accumulated in each of the even-numbered pixel cells as the a least one pixel cell connected to the even-numbered data lines from the head one and the even-numbered gate lines from the head one based on the second potential of each of the even-numbered data lines from the head one in accordance with that drive. Also, the drive for the odd-numbered gate lines and the even-numbered gate lines adjacent thereto is stopped. The accumulation of the charges in each of the odd-numbered pixel cells and the even-numbered pixel cells in accordance with that drive to hold the charges in each of the odd-numbered pixel cells and the even-numbered pixel cells. The potential of each of the odd-numbered data lines and the even-numbered data lines is set at the predetermined potential. Each of the odd-numbered data lines and the even-numbered data lines is set in the high impedance state. Ones of the odd-numbered gate lines and the even-numbered gate lines adjacent thereto are driven as the drive object. The charges accumulated in the odd-numbered pixel cells or the even-numbered pixel cells connected to the drive object are outputted to the odd-numbered data lines or the even-numbered data lines in accordance with that drive. Also, the potentials of the each adjacent odd-numbered data lines and even-numbered data lines are compared with one another.

According to still another embodiment of the present invention, there is provided a liquid crystal display device, including: a first substrate as a semiconductor substrate or an insulating substrate; a second substrate, as a semiconductor substrate or an insulating substrate having a common electrode, disposed so as to face the first substrate; and a liquid crystal layer held between the first substrate and the second substrate. And the first substrate includes at least two data lines disposed in parallel with each other, at least two gate lines disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines, odd-numbered pixel cells as at least one pixel cell connected to the odd-numbered data lines from the head one, and the odd-numbered gate lines from the head one, even-numbered pixel cells as at least one pixel cell connected to the even-numbered data lines from the head one, and the even-numbered gate lines from the head one. The first substrate further includes driving means for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other, inputting means for inputting a signal having a predetermined potential to each of the odd-numbered data lines and the even-numbered data lines, and comparing means for comparing potentials of the each adjacent odd-numbered data line and even-numbered data line with each other, and outputting a comparison result. The odd-numbered pixel cells and the even-numbered pixel cells are disposed in matrix; and each of the odd-numbered pixel cells and the even-numbered pixel cells includes accumulating means for accumulating therein charges based on a potential of a signal corresponding to image data inputted through corresponding one of the data lines connected thereto, and connecting means for connecting the corresponding one of the data lines connected thereto and the accumulating section to each other based on a potential of corresponding one of the gate lines connected thereto.

According to the still another embodiment of the present invention, in the liquid crystal display device, the liquid crystal layer is held between the first substrate as the semiconductor substrate or the insulating substrate, and the second substrate, as the semiconductor substrate or the insulating substrate having the common electrode, disposed so as to face the first substrate. Note that, the first substrate includes the at least two data lines disposed in parallel with each other, the at least two gate lines disposed in parallel with each other ant at right angles to the at least two data lines so as to be electrically insulating from the at least two gate lines, the odd-numbered pixel cells as the at least one pixel cell connected to the odd-numbered data lines from the head one and the odd-numbered gate lines from the head one, the even-numbered pixel cells as the at least one pixel cell connected to the even-numbered data lines from the head one and the even-numbered gate lines from the head one, the driving means for the odd-numbered gate lines and the even-numbered gate lines independently of each other, the inputting means for inputting the signal having the predetermined potential to each of the odd-numbered data lines and the even-numbered data line, and the comparing means for comparing the potentials of the each adjacent odd-numbered data line and even-numbered data line, and outputting the comparison result. Also, the odd-numbered pixel cells and the even-numbered pixel cells are disposed in matrix.

As set forth hereinabove, according to the embodiments of the present invention, a fault caused on the semiconductor substrate or the insulating substrate having the pixel cells disposed in matrix therein can be more precisely detected.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although embodiments of the present invention will be described in detail hereinafter, a relationship of correspondence between the constitutional requirements of the present invention, and the embodiments described in the specification or the drawings is exemplified as follows. This description is given in order to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even when although being described in the specification or the drawings, the embodiment not described here exists as the embodiment corresponding to the constitutional requirements of the present invention, this does not mean that that embodiment does not correspond to the constitutional requirements of the present invention. Conversely, even when the embodiment is described here as one corresponding to the constitutional requirements, this does not mean that that embodiment does not correspond to the constitutional requirements other than those constitutional requirements.

A driver (for example, a liquid crystal display device50ofFIG. 3) according to a first embodiment mode of the present invention includes:

at least two data lines (for example, a data line Dn−1ofFIG. 3) disposed in parallel with each other;

at least two gate lines (for example, a gate line Gm′−1(A) ofFIG. 3) disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines;

odd-numbered pixel cells (for example, a pixel cell71-1ofFIG. 3) as at least one pixel cell connected to the odd-numbered data lines (for example, a data line Dn−1ofFIG. 3) from the head one and the odd-numbered gate lines (for example, a gate line Gm′−1(A) ofFIG. 3) from the head one;

even-numbered pixel cells (for example, a pixel cell71-2ofFIG. 3) as at least one pixel cell connected to the even-numbered data lines (for example, a data line DnofFIG. 3) from the head one, and the even-numbered gate lines (for example, a gate line Gm′−1(B) ofFIG. 3) from the head one;

driving means (for example, a gate line driving circuit63ofFIG. 3) for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other;

inputting means (for example, a switch101ofFIG. 3) for inputting a signal having a predetermined potential to each of the odd-numbered data lines and the even-numbered data lines; and

comparing means (for example, a comparator103ofFIG. 3) for comparing potentials of the each adjacent odd-numbered data lines and even-numbered data line with each other, and outputting a comparison result;

in which the odd-numbered pixel cells and the even-numbered pixel cells are disposed in matrix;

each of the odd-numbered pixel cells and the even-numbered pixel cells includesaccumulating means (for example, a capacitor83ofFIG. 3) for accumulating therein charges based on a potential of a signal corresponding to pixel data inputted through corresponding one of the data lines connected thereto, andconnecting means (for example, a switch81ofFIG. 3) for connecting corresponding one of the data lines connected thereto and the accumulating means to each other based on a potential of corresponding one of the gate lines connected thereto, and

the at least two data lines, the at least two gate lines, the odd-numbered pixel cells, the even-numbered pixel cells, the driving means, the inputting means, and the comparing means are disposed on a semiconductor substrate or an insulating substrate (for example, a substrate51ofFIG. 3).

The driver according to the first embodiment mode of the present invention further includes control means (for example, a control circuit105ofFIG. 3) for inputting a control signal in accordance with which the inputting means is controlled to the inputting means, and

the inputting means connects the each adjacent odd-numbered data line and even-numbered data line to each other in accordance with the control signal, thereby causing the potentials of the each adjacent odd-numbered data line and even-numbered data line to be an average value of the each adjacent odd-numbered data line and even-numbered data line.

The driver according to the first embodiment mode of the present invention further includes control means (for example, a control circuit105ofFIG. 11) for inputting a control signal in accordance with which the inputting means is controlled to the inputting means; and

the inputting means includesodd-numbered inputting means (for example, a switch211ofFIG. 11) for inputting the signal having the predetermined potential to each of the odd-numbered data lines in accordance with the control signal, andeven-numbered inputting means (for example, a switch212ofFIG. 11) for inputting the signal having the predetermined potential to each of the even-numbered data lines in accordance with the control signal.

A driving method according to a second embodiment mode of the present invention is one for a driver (for example, a liquid crystal display device50ofFIG. 3) in which at least two data lines (for example, a data line Dn−1ofFIG. 3) disposed in parallel with each other, at least two gate lines (for example, a gate line Gm′−1(A) ofFIG. 3) disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines, odd-numbered pixel cells (for example, a pixel cell71-1ofFIG. 3) as at least one pixel cell connected to the odd-numbered data lines (for example, a data line Dn−1ofFIG. 3) from the head one and the odd-numbered gate lines (for example, a gate line Gm′−1(A) ofFIG. 3) from the head one, and even-numbered pixel cells (for example, a pixel cell71-2ofFIG. 3) as at least one pixel cell connected to the even-numbered data lines (for example, a data line DnofFIG. 3) from the head one and the even-numbered gate lines (for example, a gate line Gm′−1(B) ofFIG. 3) from the head one are provided on a semiconductor substrate or an insulating substrate (for example, a substrate51), the odd-numbered pixel cells and the even-numbered pixel cells being disposed in matrix. In this case, the driving method for a driver according to the second embodiment mode of the present invention includes the steps of:

driving the odd-numbered gate lines and the even-numbered gate lines adjacent thereto (for example, Step S31ofFIG. 10);

accumulating charges in each of the odd-numbered pixel cells based on a first potential of each of the odd-numbered data lines, and accumulating charges in each of the even-numbered pixel cells based on a second potential of each of the even-numbered data lines in accordance with that drive (for example, Step S34of FIG.10);

stopping the drive for the odd-numbered gate lines and the even-numbered gate lines adjacent thereto (for example, Step S35ofFIG. 10);

stopping the accumulation of the charges in each of the odd-numbered pixel cells and the even-numbered pixel cells in accordance with the stop of that drive to hold the charges in each of the odd-numbered pixel cells and the even-numbered pixel cells (for example, Step S36ofFIG. 10);

setting a potential of each of the odd-numbered data lines and the even-numbered data lines at a predetermined potential (for example, Step S37ofFIG. 10);

setting each of the odd-numbered data lines and the even-numbered data lines in a high impedance state (for example, Step S39ofFIG. 10);

driving ones of the odd-numbered gate lines and the even-numbered gate lines adjacent thereto as a drive object (for example, Step S40ofFIG. 10);

outputting the charges accumulated in the odd-numbered pixel cells or the even-numbered pixel cells connected to that drive object to the odd-numbered data lines or the even-numbered data lines in accordance with that drive (for example, Step S41ofFIG. 10);

comparing potentials of the each adjacent odd-numbered data line and even-numbered data line with each other (for example, Step S43ofFIG. 10); and

The driving method according to the second embodiment mode of the present invention further includes the step of executing one changing processing (for example, reverse-polarity odd-number cell single reading-out processing) as processing for changing the potential of each of the odd-numbered data lines from the first potential to the second potential, and changing the potential of each of the even-numbered data lines from the second potential to the first potential in the one side processing (for example, Step S4ofFIG. 8).

The driving method according to the second embodiment mode of the present invention further includes the step of executing the other processing (for example, straight-polarity even-numbered cell single reading-out processing) as processing for changing the drive object from ones of the odd-numbered gate lines and the even-numbered gate lines adjacent thereto to the others thereof in the one processing (for example, Step S5ofFIG. 8).

In the driving method according to the second embodiment mode of the present invention, the first potential and the second potential are different in polarity from each other with respect to the predetermined potential. In this case, the driving method according to the second embodiment mode of the present invention further includes the step of executing the other changing processing (for example, reverse-polarity even-numbered cell single reading-out processing) as processing for changing the potential of each of the odd-numbered data lines from the first potential to the second potential, and changing the potential of each of the even-numbered data lines from the second potential to the first potential (for example, Step S6ofFIG. 8).

The driving method according to the second embodiment mode of the present invention further includes the step of executing both processing (for example, straight-polarity both reading-out processing) as processing for changing the drive object from ones of the odd-numbered gate lines and the even-numbered gate lines adjacent thereto to both of the odd-numbered gate lines and the even-numbered gate lines adjacent thereto in the one processing (for example, Step S1ofFIG. 8).

In the driving method according to the second embodiment mode of the present invention, the first potential and the second potential are different in polarity from each other with respect to the predetermined potential. In this case, the driving method according to the second embodiment mode of the present invention further includes the step of executing both changing processing (for example, reverse-polarity both reading-out processing) as processing for changing the potential of each of the odd-numbered data lines from the first potential to the second potential, and changing the potential of each of the even-numbered data lines from the second potential to the first potential in the both processing (for example, Step S2ofFIG. 8).

A liquid crystal display device according to a third embodiment mode of the present invention includes:

a first substrate (for example, a substrate51ofFIG. 3) as a semiconductor substrate or an insulating substrate;

a second substrate (for example, a counter substrate52ofFIG. 3), as a semiconductor substrate or an insulating substrate having a common electrode, disposed so as to face the first substrate; and

a liquid crystal layer (for example, a liquid crystal layer53ofFIG. 3) held between the first substrate and the second substrate;

in which the first substrate includesat least two data lines (for example, the data line Dn−1ofFIG. 3) disposed in parallel with each other,at least two gate lines (for example, the gate line Gm′−1(A) ofFIG. 3) disposed in parallel with each other and at right angles to the at least two data lines so as to be electrically insulated from the at least two data lines,odd-numbered pixel cells (for example, the pixel cell71-1ofFIG. 3) as at least one pixel cell connected to the odd-numbered data lines (for example, a data line Dn−1ofFIG. 3) from the head one and the odd-numbered gate lines (for example, the gate line Gm′−1(A) ofFIG. 3) from the head one,even-numbered pixel cells (for example, the pixel cell71-2ofFIG. 3) as at least one pixel cell connected to the even-numbered data lines (for example, a data line DnofFIG. 3) from the head one, and the even-numbered gate lines (for example, the gate line Gm′−1(B) ofFIG. 3) from the head one,driving means (for example, a gate line driving circuit63ofFIG. 3) for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other,inputting means (for example, the switch101ofFIG. 3) for inputting a signal having a predetermined potential to each of the odd-numbered data lines and the even-numbered data lines, andcomparing means (for example, the comparator103ofFIG. 3) for comparing potentials of the each adjacent odd-numbered data lines and even-numbered data line with each other, and outputting a comparison result,

in which the odd-numbered pixel cells and the even-numbered pixel cells are disposed in matrix; and

each of the odd-numbered pixel cells and the even-numbered pixel cells includesaccumulating means (for example, the capacitor83ofFIG. 3) for accumulating therein charges based on a potential of a signal corresponding to pixel data inputted through corresponding one of the data lines connected thereto, andconnecting means (for example, the switch81ofFIG. 3) for connecting corresponding one of the data lines connected thereto and the accumulating means to each other based on a potential of corresponding one of the gate lines connected thereto.

FIG. 3is a schematic circuit diagram showing a structure of a liquid crystal display device according to a first embodiment of the present invention.

A liquid crystal display device50shown inFIG. 3is composed of a substrate51as a semiconductor substrate or an insulating substrate, a counter substrate52, as a semiconductor substrate or an insulating substrate, disposed so as to face the substrate51, and a liquid crystal layer53held between the substrate51and the counter substrate52.

A display circuit61, a data line driving circuit62, a gate line driving circuit63, and a detection circuit64are disposed on the substrate51. It is noted that although a portion about display of a region having twelve pixels in total within a screen in which four pixels are horizontally disposed and three pixels are vertically disposed is described below with reference toFIG. 3for the sake of convenience of a description, any other portion about display is structured similarly to the case of the portion about display shown inFIG. 3.

The display circuit61is formed such that a plurality of pixel cells71-1to71-12are disposed in matrix so that four pixel cells are horizontally disposed and three pixel cells are vertically disposed. It is noted that when there is no necessity for individually distinguishing the plurality of pixel cells71-1to71-12from one another in the following description, they are collectively referred to as “the pixel cells71”.

The pixel cells71are connected to the data line driving circuit62through data lines Dn−1, Dn, Dn+1, and Dn+2, respectively, which are disposed in parallel with each other on the substrate51so as to be insulated from one another. In addition, the pixel cells71are connected to the gate line driving circuit63through gate lines Gm′−1(A), Gm′−1(B), Gm′(A), Gm′(B), and Gm′+1(A) and Gm′+1(B) (m′: odd number), respectively. Here, the gate lines Gm′−1(A), Gm′−1(B), Gm′(A), Gm′(B), and Gm′+1(A) and Gm′+1(B) are disposed in parallel with one another and at right angles to the data lines Dn−1, Dn, Dn+1, and Dn+2so as to be electrically insulated from the data lines Dn−1, D, Dn+1, and Dn+2.

Here, a suffix added to G represents what number the gate lines, disposed in units of two lines, including the gate line concerned belong to in a direction from an upper side to a lower side in the figure (in a vertical direction in the figure). In addition, (A) added to G represents that the gate line concerned is the odd-numbered gate line in the direction from the upper side to the lower side in the figure. On the other hand, (B) added to G represents that the gate line concerned is the even-numbered gate line in the direction from the upper side to the lower side in the figure. It is noted that when there is no necessity for individually distinguishing the gate lines Gm′−1(A), Gm′(A), and Gm′+1(A) from one another in the following description, they are collectively referred to as “the gate lines G(A)”. In addition, it is noted that when there is no necessity for individually distinguishing the gate lines Gm′−1(B), Gm′(B), and Gm′+1(B) from one another in the following description, they are collectively referred to as “the gate lines G(B)”.

The pixel cell71-1is composed of a switch81, an electrode82, and a capacitor83. The switch81, for example, is constituted by an FET. A gate of the switch81is connected to the odd-numbered gate line Gm′−1(A) from the upper side, and a drain thereof is connected to the odd-numbered data line Dn−1from the left-hand side. In addition, a source of the switch81is connected to each of the electrode82and one end of the capacitor83, and the other end of the capacitor83is connected to the common electrode.

In the pixel cell71-1, when the switch81is turned ON by drive of the gate line Gm′−1(A), the charges are accumulated in the capacitor83based on a voltage of a signal which is inputted to the switch81by drive of the data line Dn−1. That is to say, data is written to the capacitor83. Also, the switch81is turned OFF by stopping the drive of the gate line Gm′−1(A), so that the capacitor83holds therein the data written thereto.

At this time, a potential Pm′−1n−1at the electrode82is one developed at the one end of the capacitor83connected to the electrode82. The liquid crystal layer53is activated to be excited in correspondence to a difference between the potential Pm′−1n−1at the electrode82and a potential at the common electrode84which the counter substrate52has. As a result, the pixel corresponding to the pixel cell71-1is activated for display. Note that, while a description is omitted here for the sake of simplicity, each of the pixel cells71-5and71-9disposed in the same position in vertical direction as that of the pixel cell71-1, and the pixel cells71-3,71-7and71-11disposed on the right-hand side next but one thereto is structured similarly to the case of the pixel cell71-1, and performs the same operation as that of the pixel cell71-1.

In addition, the pixel cell71-2is composed of a switch91, an electrode92, and a capacitor93. The switch91, for example, is constituted by the FET. A gate of the switch91is connected to the even-numbered gate line Gm′−1(B) from the upper side, and a drain thereof is connected to the even-numbered data line Dnfrom the left-hand side. In addition, a source of the switch91is connected to each of the electrode92and one end of the capacitor93, and the other end of the capacitor93is connected to the common electrode.

In the pixel cell71-2, when the switch91is turned ON by drive of the gate line Gm′−1(B), the charges are accumulated in the capacitor93based on a voltage of a signal which is inputted to the switch91by drive of the data line Dn. That is to say, data is written to the capacitor93. Also, the switch91is turned OFF by stopping the drive of the gate line Gm′−1(B), so that the capacitor93holds therein the data written thereto.

At this time, a potential Pm′−1nat the electrode92is one developed at the one end of the capacitor93connected to the electrode92. The liquid crystal layer53is activated to be excited in correspondence to a difference between the potential Pm′−1nat the electrode92and a potential at the common electrode84which the counter substrate52has. As a result, the pixel corresponding to the pixel cell71-2is activated for display. Note that, while a description is omitted here for the sake of simplicity, each of the pixel cells71-6and71-10disposed in the same position in vertical direction as that of the pixel cell71-2, and the pixel cells71-4,71-8and71-12disposed on the right-hand side next but one thereto is structured similarly to the case of the pixel cell71-2, and performs the same operation as that of the pixel cell71-2.

As has been described above, the pixel cells71-1,71-5and71-9, and71-3,71-7and71-11which are connected to the odd-numbered data lines Dn−1and Dn+1from the left-hand side, respectively, are also connected to the odd-numbered gate lines Gm′−1(A), Gm′(A) and Gm′+1(A) from the upper side. On the other hand, the pixel cells71-2,72-6and71-10, and71-4,72-8and71-12which are connected to the even-numbered data lines Dnand Dn+2from the left-hand side, respectively, are also connected to the even-numbered gate lines Gm′−1(B), Gm′(B) and Gm′+1(B) from the upper side.

The data line driving circuit62, for example, is provided with a shift register and the like. The data line driving circuit62successively shifts the data which is inputted thereto every horizontal line from the outside, thereby successively driving the data lines D so that the data lines D is successively scanned in the horizontal direction. Here, the drive for the data lines D means that a signal having a potential corresponding to data inputted from the outside is successively inputted to the data lines D. In addition, the data line driving circuit62successively shifts data which is inputted from the outside and which is used to inspect a fault caused on the substrate51, thereby successively driving the data lines D.

The gate line driving circuit63, for example, is provided with a shift register and the like, and controls the gate lines G(A) and G(B) independently of each other. The gate line driving circuit63successively shifts data which is inputted thereto from the outside and which is used to control the scanning, thereby successively driving the gate lines G(A) and G(B) in units of two lines every period of time for the horizontal scanning. As a result, the switches81(91) of the pixel cells71are successively turned ON in units of the switches81(91) of the pixel cells71which are disposed in the horizontal direction, so that the horizontal line as the scanning object moves in the vertical direction. Here, the drive for the gate lines G(A) or G(B) means that drive pulses are successively inputted to the gate lines G(A) or G(B), respectively.

As has been described above, the data line driving circuit62successively drives the data lines D by using the shift register. Also, the gate line driving circuit63successively drives the gate lines G(A) and G(B) in units of two lines. As a result, the data is successively written to the capacitors83(93) of the pixel cells71, so that the liquid crystal layer53is excited, thereby displaying a desired image on the screen.

In addition, the gate line driving circuit63successively shifts the data which is inputted thereto from the outside and which is used to inspect a fault caused on the substrate51, thereby either driving the gate lines G(A) and G(B) in units of two lines or driving ones of the gate lines G(A) and G(B).

The detection circuit64is composed of switches101and102, comparators103and104, a control circuit105, and the like.

The switch101, for example, is constituted by the FET, and a gate of the switch101is connected to the control circuit105. A drain of the switch101is connected to the data line Dn−1, and a source thereof is connected to the data line Dnadjacent to the data line Dn−1. Also, the switch101connects the data line Dn−1and the data line Dnto each other in accordance with a control signal supplied from the control circuit105.

The switch102, for example, is constituted by the FET similarly to the case of the switch101, and a gate of the switch102is connected to the control circuit105. A drain of the switch102is connected to the data line Dn+1, and a source thereof is connected to the data line Dn+2adjacent to the data line Dn+1. Also, the switch102connects the data line Dn+1and the data line Dn+2to each other in accordance with a control signal supplied from the control circuit105.

The comparator103compares the potentials of the data lines Dn−1and Dnwith each other. The comparator103outputs a signal having a predetermined potential VS as an output signal having smaller one of the potentials of the data lines Dn−1and Dn, and outputs a signal having a predetermined potential VB as an output signal having larger one of the potentials of the data lines Dn−1and Dn. Note that, when the potentials of the data lines Dn−1and Dnare equal to each other, the comparator103outputs the signal having the potential VS as one output signal having one of the potentials of the data lines Dn−1and Dn, and outputs the output signal having the potential VB as the other output signal having the other of the potentials of the data lines Dn−1and Dnin accordance with its characteristics. This similarly applies to the comparator104which will be described below.

The comparator104compares the potentials of the data lines Dn+1and Dn+2with each other. The comparator104outputs a signal having a predetermined potential VS as an output signal having smaller one of the potentials of the data lines Dn+1and Dn+2, and outputs a signal having a predetermined potential VB as an output signal having larger one of the potentials of the data lines Dn+1and Dn+2. A user detects a fault, such as a line fault, short circuit or disconnection within the pixel cells71, or a fault in holding performance of the capacitors83(93), which is caused on the substrate51in accordance with the output signals sent from the comparators103and104, thereby specifying a faulty portion.

The control circuit105generates a control signal at a predetermined timing and outputs the control signal thus generated to each of the gates of the switches102and102.

Next, a description will now be given with respect to an example of the potentials of the signals inputted to the data lines D, respectively, when a fault caused on the substrate51is inspected with reference to a Table ofFIG. 4.

It is noted that in the Table ofFIG. 4, the reference symbols of the data lines D are described in the uppermost column, and the reference symbols of the gate lines G(A) and G(B) are described in a column at a left-hand end.

In addition, in the Table ofFIG. 4, in each of the columns in and after the second column from the upper side, the potential of the signal which is inputted to corresponding one of the data lines D having the reference symbol described in the uppermost column from the column concerned when the gate lines G(A) and G(B) having the respective reference symbols described in the column at the left-hand end from the column concerned is expressed in the form of either an H level (represented by “H” inFIG. 4) or an L level (represented by “L” inFIG. 4) having a polarity different from that of the H level with respect to a reference value Ve. The signal having the potential of the H level (hereinafter referred to as “the H level signal”), for example, corresponds to “1” of the data inputted from the outside to the data line driving circuit62. On the other hand, the signal having the potential of the L level (hereinafter referred to as “the L level signal”), for example, corresponds to “0” of the data inputted from the outside to the data line driving circuit62.

In the example shown in Table ofFIG. 4, when the gate lines Gm′−1(A) and Gm′−1(B) are driven in units of two lines, the data line driving circuit62inputs the H level signal, the L level signal, the H level signal, and the L level signal to the data line Dn−1, the data line Dn, the data line Dn+1, and the data line Dn+2, respectively. In addition, when the gate lines Gm′(A) and Gm′(B) are driven in units of two lines, the data line driving circuit62inputs the L level signal, the H level signal, the L level signal, and the H level signal to the data line Dn−1, the data line Dn, the data line Dn+1, and the data line Dn+2, respectively.

Also, when the gate lines Gm′+1(A) and Gm′+1(B) are driven in units of two lines, the data line driving circuit62inputs the H level signal, the L level signal, the H level signal, and the L level signal to the data line Dn−1, the data line Dn, the data line Dn+1, and the data line Dn+2, respectively.

As has been described above, in the inspection for a fault, the data line driving circuit62inputs the signals having the potentials different in polarity from each other to each adjacent two data lines D, respectively. Therefore, when no fault is caused on the substrate51, the charges originating from the potentials which are different in polarity from each other with respect to the reference value Ve are accumulated in the capacitors83and93of the pixel cells71which are adjacent to each other in the horizontal direction. On the other hand, when short circuit is caused between the adjacent two pixel cells71, the charges accumulated in the capacitors83and93of the pixel cells71which are adjacent to each other in the horizontal direction become ones originating from the same potential. Consequently, the user can detect the short circuit between the each adjacent two pixel cells based on the results of comparison in potential between the each adjacent two data lines D through which the charges accumulated in the capacitors83and93are outputted, respectively. Here, the comparison results are outputted from the comparators103(104), respectively.

Next, an inspection for the pixel cells71-5and71-6will now be described with reference to timing charts ofFIGS. 5 to 7. It is noted that in each of the timing charts ofFIGS. 5 to 7, an axis of abscissa represents a time, and axis of ordinate represents a potential. In addition, it is assumed that in an example shown in the time chart ofFIG. 5, no fault is caused.

Firstly, as shown inFIG. 5, the liquid crystal display device50carries out an operation for writing data to each of the pixel cells71-5and71-6, and an operation for reading out data from each of the pixel cells71-5and71-6.

More specifically, as shown by a waveform gABofFIG. 5, at a time TWS, the gate line driving circuit63drives the gate lines Gm′(A) and Gm′(B). That is to say, the gate line driving circuit63inputs drive pulses to the gate lines Gm′(A) and Gm′(B), respectively. As a result, each of the pixel cells71-5and71-6is held in an ON state while each of the drive pulses is held in an ON state.

In addition, at the time TWS, the data line driving circuit62inputs the L level signal to the data line Dn−1. As a result, as shown by a waveform dn−1ofFIG. 5, the potential of the data line Dn−1gradually increases from its initial value VDOto reach the L level. As has been described above, at the time TWS, the switch of the pixel cell71-5is turned ON. As a result, as shown by a waveform pm′n−1ofFIG. 5, a potential Pm′n−1at the electrode of the pixel cell71-5gradually increases from its initial value VPOto reach the L level.

Moreover, at the time TWS, the data line driving circuit62inputs the H level signal to the data line Dn. As a result, as shown by a waveform dnofFIG. 5, the potential of the data line Dngradually increases from its initial value VDOto reach the H level. As has been described above, at the time TWS, the switch of the pixel cell71-6is turned ON. As a result, as shown by a waveform pm′nofFIG. 5, a potential Pm′nat the electrode of the pixel cell71-6gradually increases from its initial value VPOto reach the H level.

The liquid crystal display device50carries out an operation for writing the data to each of the pixel cells71-5and71-6in the manner as described above.

Next, when at a time TWE, the drive for each of the gate lines Gm′(A) and Gm′(B) is stopped, that is, the drive pulses for the respective gate lines Gm′(A) and Gm′(B) are set to OFF, the switches of the pixel cells71-5and71-6are turned OFF, so that the capacitors of the pixel cells71-5and71-6hold the charges accumulated therein. As a result, as shown by the waveform pm′n−1ofFIG. 5, the potential Pm′n−1at the electrode of the pixel cell71-5is held at the L level. Also, the potential Pm′nat the electrode of the pixel cell71-6, as shown by the waveform pm′nofFIG. 5, is held at the H level. In addition, the data line driving circuit62stops the input of the signal to each of the data lines Dn−1and Dn.

After that time, at a time TS, the switch101is turned ON in accordance with the control signal supplied from the control circuit105. As a result, each of the potentials of the data lines Dn−1and Dngradually approaches the reference value Ve as an intermediate value between the H level and the L level, and both of them are stabilized at the reference value Ve. After that, the switch101is turned OFF in accordance with the control signal supplied from the control circuit105, and the data line driving circuit62sets each of the data lines Dn−1and Dnin a high impedance state.

Next, at a time TRS, as shown by the waveform gABofFIG. 5the gate line driving circuit63drives the gate lines Gm′(A) and Gm′(B). As a result, the switches of the pixel cells71-5and71-6are turned ON again.

Therefore, at the time TRS, as shown by the waveform dn−1ofFIG. 5, the potential of the data line Dn−1gradually drops from the reference value Ve due to the potential Pm′n−1at the electrode of the pixel cell71-5to become a value VL(VL<Ve). In addition, as shown by the waveform pm′n−1ofFIG. 5, the potential Pm′n−1at the electrode of the pixel cell71-5gradually increases due to the potential of the data line Dn−1to become the value VL.

On the other hand, as shown by the waveform dnofFIG. 5, the potential of the data line Dngradually increases from the reference value Ve due to the potential Pm′nat the electrode of the pixel cell71-6to become a value VH(VH>Ve). In addition, as shown by the waveform pm′nofFIG. 5, the potential Pm′nat the electrode of the pixel cell71-6gradually drops from the H level due to the potential of the data line Dnto become the value VH.

Next, when at a time TRE, the drive pulses for the respective gate lines Gm′(A) and Gm′(B) are set to OFF, the switches of the pixel cells71-5and71-6are turned OFF.

The liquid crystal display device50carries out an operation for reading out the data from the pixel cells71-5and71-6in the manner as described above.

After that time, the comparator103compares the potential VLof the data line Dn−1and the potential VHof the data line Dnwith each other. As a result, the comparator103outputs the signal having the potential VS as the output signal having the smaller potential of the data line Dn−1, and outputs the signal having the potential VB as the output signal having the larger potential of the data line Dn. The user judges whether or not a fault is caused by checking the output signals of the respective data lines Dn−1and Dn.

In the example ofFIG. 5, the L level signal and the H level signal are inputted to the data lines Dn−1and Dn, respectively. That is to say, the data corresponding to the L level signal is written to the capacitor of the pixel cell71-5, and the data corresponding to the H level signal is written to the capacitor of the pixel cell71-6. As a result, when no fault is caused, the potential of the output signal sent from the data line Dn−1becomes the potential VS, and the potential of the output signal sent from the data line Dnbecomes the potential VB. Therefore, when the potential of the output signal from the data line Dn−1is the potential VS and the potential of the output signal from the data line Dnis the potential VB as shown in the timing chart ofFIG. 5, the user judges that a fault is caused in none of the pixel cells71-5and71-6.

On the other hand, a detailed description will be given hereinafter with respect to the case where a fault is caused in the pixel cell71-5with reference to the timing chart ofFIG. 6. Note that, with regard to the fault caused in the pixel cell71-5, for example, there are given a fault in the switch of the pixel cell71-5(for example, the switch is caused to be a normally turned-ON or OFF state), an open fault in connection between the data line Dn−1and the switch of the pixel cell71-5, disconnection or short circuit on the electrode side (on the capacitor side) of the switch, disconnection or short circuit in the data line Dn−1connected to the pixel cell71-5, disconnection or short circuit in the gate line Gm′(A) connected to the pixel cell71-5, and the like. However, in the example ofFIG. 6, it is assumed that there is the fault in which the switch of the pixel cell71-5is caused to be the normally turned-ON state.

In this case, even when at the time TWS, the gate line Gm′(A) is driven, the switch of the pixel cell71-5is held in the OFF state. Therefore, as shown by a waveform p′m′n−1ofFIG. 6, at the time TWS, the potential Pm′n−1at the electrode of the pixel cell71-5is held at its initial value VPO. In addition, as shown by a waveform d′n−1ofFIG. 6, at the time TRS, the potential of the data line Dn−1is still held at the reference value Ve as shown by a waveform d′n−1ofFIG. 6because even when at the time TRS, the gate lines Gm′(A) is driven, the switch of the pixel cell71-5is held in the OFF state.

However, a magnitude relationship between the reference value Ve as the potential of the data line Dn−1and the value VHas the potential of the data line Dnis identical to that between the potential VLof the data line Dn−1and the potential VHof the data line Dnwhen no fault is caused. Thus, the output signal outputted from the comparator103becomes identical to that when a fault is caused in none of the pixel cells71-5and71-6. Therefore, the user judges that a fault is caused in none of the pixel cells71-5and71-6by mistake. That is to say, none of the faults in the pixel cells71-5and71-6is detected.

In order to cope with this situation, for example, the liquid crystal display device50, as shown inFIG. 7, also carries out an operation for writing the data to each of the pixel cells71-5and71-6, and an operation for reading out the data from the pixel cell71-5. Note that, in an example ofFIG. 7, it is assumed that the same fault as that of the example ofFIG. 6is caused in the pixel cell71-5.

More specifically, as shown by waveforms gAand gBofFIG. 7, at the time TWS, the gate line driving circuit63drives the gate lines Gm′(A) and Gm′(B). However, since the switch of the pixel cell71-5is still held in the OFF state, as shown by a waveform p′m′n−1ofFIG. 7, the potential Pm′n−1at the electrode of the pixel cell71-5is held at its initial value VPOsimilarly to the case ofFIG. 6. In addition, even when at the time TRS, the gate line Gm′(A) is driven, the switch of the pixel cell71-5is still held in the OFF state. Hence, at the time TRS, as shown by a waveform d′n−1ofFIG. 6, the potential of the data line Dn−1is still held at the reference value Ve.

On the other hand, in the case of the example shown inFIG. 7, unlike the case of the example shown inFIG. 6, since as shown by the waveform gBofFIG. 7, no gate line Gm′(B) is driven at the time TRS, no switch of the pixel cell71-6is turned ON. As a result, the potential Pm′nat the electrode of the pixel cell71-6is still held at the reference value Ve as shown by the waveform p′m′nofFIG. 7.

As has been described above, each of the potentials of the data lines Dn−1and Dnis set to the reference value Ve. Thus, the comparator103, for example, outputs the signal having the potential VB as the output signal sent from the data line Dn−1and outputs the signal having the potential VS as the output signal sent from the data line Dn.

On the other hand, when no fault is caused, the potential of the data line Dn−1does not become the reference value Ve, but becomes the value VLsmaller than reference value Ve. Hence, unlike the case of the example ofFIG. 7, the potential of the output signal from the data line Dn−1becomes the potential VS and the potential of the output signal from the data line Dnbecomes the potential VB. Consequently, in the example ofFIG. 7, the user can judge that the fault is caused in the pixel cell71-5by confirming whether or not the potentials of the output signals from the respective data lines Dn−1and Dnare different from those in the case where no fault is caused.

Next, a description will now be given with respect to the case where the liquid crystal display device50executes inspection processing for inspecting whether or not a fault is caused with reference to a flow chart ofFIG. 8. This inspection processing starts to be executed when data for the inspection is inputted from the outside to each of the data line driving circuit62and the gate line driving circuit63.

In Step S1, the liquid crystal display device50executes straight-polarity both reading-out processing. Here, in the straight-polarity both reading-out processing, the signals having the respective potentials shown inFIG. 4are inputted to the data lines D, respectively, and the write and read of the data to and from both of the adjacent two pixel cells71is carried out. The details of the straight-polarity both reading-out processing will be described later with reference to a flow chart ofFIG. 9.

In Step S2, the liquid crystal display device50executes reverse-polarity both reading-out processing. Here, in the reverse-polarity both reading-out processing, the signals having the respective potentials which are reverse in polarity to those shown inFIG. 4with respect to the reference value Ve are inputted to the data lines D, respectively, and the write and read of the data to and from both of the adjacent two pixel cells71are carried out.

In Step S3, the liquid crystal display device50executes straight-polarity odd-numbered cell single reading-out processing. Here, in the straight-polarity odd-numbered cell single reading-out processing, the signals having the respective potentials shown inFIG. 4are inputted to the data lines D, respectively, the write of the data to each of the adjacent two pixel cells71is carried out, and the read of the data from the odd-numbered pixel cell71from the left-hand side of the adjacent two pixel cells71is carried out. The details of the straight-polarity odd-numbered cell single reading-out processing will be described later with reference to a flow chart ofFIG. 10.

In Step S4, the liquid crystal display device50executes reverse-polarity odd-numbered cell single reading-out processing. Here, in the reverse-polarity odd-numbered cell single reading-out processing, the signals having the respective potentials which are reverse in polarity to those shown inFIG. 4with respect to the reference value Ve are inputted to the data lines D, respectively, the write of the data to each of the adjacent two pixel cells71is carried out, and the read of the data from the odd-numbered pixel cell71from the left-hand side of the adjacent two pixel cells71is carried out.

In Step S5, the liquid crystal display device50executes straight-polarity even-numbered cell single reading-out processing. Here, in the straight-polarity even-numbered cell single reading-out processing, the signals having the respective potentials shown inFIG. 4are inputted to the data lines D, respectively, the write of the data to each of the adjacent two pixel cells71is carried out, and the read of the data from the even-numbered pixel cell71from the left-hand side of the adjacent two pixel cells71is carried out.

In Step S6, the liquid crystal display device50executes reverse-polarity even-numbered cell single reading-out processing. Here, in the reverse-polarity even-numbered cell single reading-out processing, the signals having the respective potentials which are reverse in polarity to those shown inFIG. 4with respect to the reference value Ve are inputted to the data lines D, respectively, the write of the data to each of the adjacent two pixel cells71is carried out, and the read of the data from the even-numbered pixel cell71from the left-hand side of the adjacent two pixel cells71is carried out.

As has been described above, the liquid crystal display device50executes not only the straight-polarity both reading-out processing, straight-polarity odd-numbered cell single reading-out processing, and straight-polarity even-numbered cell single reading-out processing for inputting the signals having the respective potentials shown inFIG. 4to the data lines D, respectively, but also the reverse-polarity both reading-out processing, reverse-polarity odd-numbered cell single reading-out processing, and reverse-polarity even-numbered single reading-out processing for inputting the signals having the respective potentials which are reverse in polarity to those shown inFIG. 4with respect to the reference value Ve to the data lines D, respectively. As a result, the fault can be more precisely detected.

That is to say, when the potentials of the adjacent two data lines D are equal to each other, each of the comparators103and104outputs the signal having the potential VS as the output signal from one of the adjacent two data lines D, and output the signal having the potential VB as the output signal from the other of the adjacent two data lines D based on its characteristics. Therefore, even when a fault is caused, the potential of the output signal becomes identical to that of the output signal when no fault is caused. As a result, the user may judge that no fault is caused by mistake.

Even in such a case, however, the liquid crystal display device50inspects both the case where the potentials of the signals inputted to the respective data lines D are those of the signals each having the predetermined polarity with respect to the reference value Ve, and the case where the potentials of the signals inputted to the respective data lines D are those of the signals which are reverse in polarity to those of the signals shown inFIG. 4with respect to the reference value Ve. As a result, the user can judge that no fault is caused when the potential of the output signal outputted from the comparator103(104) and obtained from the inspection results about one of the two cases is different from that of the output signal outputted from the comparator103(104) and obtained from the inspection results about the other of them, that is, when the magnitude relationship between the output signals from the adjacent two data lines D changes depending on changes in polarity of the potentials of the signals inputted to the respective data lines D with respect to the reference value Ve. On the other hand, the user can judge that the fault is caused when the potentials of the output signals obtained from the inspection results about both of them are identical to each other.

In addition, in the liquid crystal display device50, the different gate lines G(A) and G(B) are connected to the adjacent pixel cells71, respectively, and the gate line driving circuit63controls the paired gate lines G(A) and G(B) independently of each other. Here, the liquid crystal display device50executes not only the straight-polarity both reading-out processing and reverse-polarity both reading-out processing for carrying out the write and read of the data to and from each of the adjacent two pixel cells71, but also the straight-polarity odd-numbered cell single reading-out processing, reverse-polarity odd-numbered cell single reading-out processing, straight-polarity even-numbered cell single reading-out processing, and reverse-polarity even-numbered cell single reading-out processing for carrying out the write of the data to each of the adjacent two pixel cells71, and carrying out the read of the data from one of the adjacent two pixel cells71. As a result, the fault can be more precisely detected.

For example, in the case where the magnitude relationship of one set of the potentials of the adjacent two data lines D is identical to that of the other set of the potentials of the adjacent two data lines D, even when the potentials of the respective data lines D are different from one another, the comparators103and104output the output signals identical to each other. Therefore, even when the fault is caused, the user may judge that no fault is caused by mistake because the potentials of the output signals are identical to those of the output signals when no fault is caused.

Even in such a case, the light liquid crystal display device50carries out the inspection for reading out the data only from one of the adjacent two pixel cells71, which results in that as the inspection results, the possibility that the potential of the output signal outputted from the comparator103(104) is different from that of the output signal outputted from the comparator103(104) when no fault is caused increases. As a result, the user can more precisely detect the fault.

As has been described above, since the user can more precisely detect the fault, he/she can narrow down the faulty portion in more detail. As a result, the user can specify the faulty portion in more detail.

Next, a description will now be given with respect to the details of the straight-polarity both reading-out processing in Step S1ofFIG. 8with reference to a flow chart ofFIG. 9. It is noted that although a description is given below with respect to the case where the gate lines Gm′−1(A) and Gm′−1(B) are driven with reference to the flow chart ofFIG. 9, the drive is successively performed for other gate lines G(A) and G(B) similarly to the case ofFIG. 9.

In Step S11, the gate line driving circuit63inputs the drive pulses to the gate lines Gm′−1(A) and Gm′−1(B), respectively. In Step S12, the switches of the pixel cells71-1,71-3, and71-2,71-4connected to the gate lines Gm′−1(A) and Gm′−1(B), respectively, are turned ON, thereby connecting the data lines D to the electrodes thereof, respectively.

In Step S13, as shown inFIG. 4, the data line driving circuit62inputs the H level signal to each of the odd-numbered data lines D from the left-hand side (hereinafter referred to as “the odd-numbered data lines”), and inputs the L level signals to each of the even-numbered data lines D from the left-hand side (hereinafter referred to as “the even-numbered data lines”).

In Step S14, the capacitors of the pixel cells71-1,71-3, and71-2,71-4connected to the gate lines Gm′−1(A) and Gm′−1(B), respectively, accumulate therein the charges based on the potentials of the signals inputted thereto from the data line driving circuit62through the respective switches.

In Step S15, the switches of the pixel cells71-1,71-3, and71-2,71-4connected to the gate lines Gm′−1(A) and Gm′−1(B), respectively, are turned OFF in response to the OFF state of the drive pulses inputted the gate lines Gm′−1(A) and Gm′−1(B), thereby disconnecting the electrodes of the pixel cells71-1,71-3, and71-2,71-4from the data lines D, respectively. As a result, the accumulation of the charges in the capacitors of the pixel cells71-1to71-4is stopped.

In Step S16, the capacitors of the pixel cells71-1to71-4hold the charges accumulated therein. In Step S17, the switches101and102connect the odd-numbered data lines and the even-numbered data lines adjacent thereto to each other in accordance with the control signals inputted thereto from the control circuit105, respectively. As a result, the potential of each of the odd-numbered data lines and the even-numbered data lines adjacent thereto becomes equal to the reference value Ve.

In Step S18, the switches101and102disconnect the odd-numbered data lines and the even-numbered data lines adjacent thereto from each other in accordance with control signals inputted thereto from the control circuit105, respectively. In Step S19, the data line driving circuit62sets each of the data lines D in a high impedance state.

In Step S20, the gate line driving circuit63inputs drive pulses to the gate lines Gm′−1(A) and Gm′−1(B), respectively. In Step S21, the switches of the pixel cells71-1to71-4are turned ON to connect the data lines D to the electrodes of the pixel cells71-1to71-4, respectively. As a result, the potentials of the capacitors of the pixel cells71-1to71-4become identical to those at the electrodes of the pixel cells71-1to71-4, respectively.

In Step S22, the switches of the pixel cells71-1to71-4are turned OFF in response to end of the drive pulses inputted to the gate lines Gm′−1(A) and Gm′−1(B), respectively, to disconnect the data lines D and the electrodes of the pixel cells71-1to71-4from each other. In Step S23, the comparator103compares the potentials of the odd-numbered data line Dn−1and the even-numbered data line Dnadjacent thereto with each other. Also, the comparator104compares the potentials of the odd-numbered data line Dn+1and the even-numbered data line Dn+2adjacent thereto with each other. In Step S24, the comparator103outputs a signal having a potential VS as an output signal having smaller one of the potentials of the odd-numbered data line Dn−1and the even-numbered data line Dnadjacent thereto, and outputs a signal having a potential VB as an output signal having larger one of the potentials of the odd-numbered data line Dn−1and the even-numbered data line Dnadjacent thereto. The comparator104outputs a signal having a potential VS as an output signal having smaller one of the potentials of the odd-numbered data line Dn+1and the even-numbered data line Dn+2adjacent thereto, and outputs a signal having a potential VB as an output signal having larger one of the potentials of the odd-numbered data line Dn+1and the even-numbered data line Dn+2adjacent thereto.

It is noted that while a description is omitted here for the sake of simplicity, the reverse-polarity both reading-out processing in Step S2ofFIG. 8is also executed similarly to the case of the straight-polarity both reading-out processing shown inFIG. 9. In this case, in Step S13ofFIG. 9, the data line driving circuit62inputs the L level signal to each of the odd-numbered data lines, and inputs the H level signal to each of the even-numbered data lines.

Next, a description will now be given with respect to the details of the straight-polarity odd-numbered cell single reading-out processing in Step S3ofFIG. 8with reference to a flow chart ofFIG. 10. It is noted that although a description is given below with respect to the case where the gate lines Gm′−1(A) and Gm′−1(B) are driven with reference toFIG. 10, the drive is successively performed for other gate lines G(A) and G(B) similarly to the case ofFIG. 10.

Since processing from Step S31to Step S39is the same as that from Step S11to Step S19ofFIG. 9, a description thereof is omitted here for the sake of simplicity.

In Step S40, the gate line driving circuit63inputs the drive pulse to the gate line Gm′−1(A). In Step S41, the switches of the pixel cells71-1and71-3connected to the gate line Gm′−1(A) are turned ON, thereby connecting the odd-numbered data lines to the electrodes of the pixel cells71-1and71-3, respectively. As a result, the charges accumulated in the capacitors of the pixel cells71-1and71-3are outputted to the odd-numbered data lines, respectively, so that the potentials of the pixel cells71-1and71-3become identical to those at the electrodes of the pixel cells71-1and71-3, respectively.

In Step S42, the switches of the pixel cells71-1and71-3are turned OFF in response to end of the drive pulse inputted to the gate line Gm′−1(A), thereby disconnecting the odd-numbered data lines and the electrodes of the pixel cells71-1and71-3from each other. In Step S43, the comparator103compares the potentials of the odd-numbered data line Dn−1and the even-numbered data line Dnadjacent thereto with each other. Also, the comparator104compares the potentials of the odd-numbered data line Dn+1and the even-numbered data line Dn+2adjacent thereto with each other. In Step S44, the comparator103outputs a signal having a potential VS as an output signal having smaller one of the potentials of the odd-numbered data line Dn−1and the even-numbered data line Dnadjacent thereto, and outputs a signal having a potential VB as an output signal having larger one of the potentials of the odd-numbered data line Dn−1and the even-numbered data line Dnadjacent thereto. The comparator104outputs the signal having the potential VS as an output signal having smaller one of the potentials of the odd-numbered data line Dn+1and the even-numbered data line Dn+2adjacent thereto, and outputs the signal having the potential VB as an output signal having larger one of the potentials of the odd-numbered data line Dn+1and the even-numbered data line Dn+2adjacent thereto.

It is noted that while a description is omitted here for the sake of simplicity, each of the reverse-polarity odd-numbered cell single reading-out processing in Step S4ofFIG. 8, the straight-polarity even-numbered cell single reading-out processing in Step S5ofFIG. 8, and the reverse-polarity even-numbered cell single reading-out processing in Step S6ofFIG. 8is also executed similarly to the case of the straight-polarity odd-numbered cell single reading-out processing shown inFIG. 10. However, in the reverse-polarity odd-numbered cell single reading-out processing in Step S4ofFIG. 8, in Step S33ofFIG. 10, the data line driving circuit62inputs the L level signal to each of the odd-numbered data lines, and inputs the H level signal to each of the even-numbered data lines. In addition, in the straight-polarity even-numbered cell single reading-out processing in Step S5ofFIG. 8, the gate line driving circuit63inputs the drive pulse to the gate line Gm′−1(B) in Step S40, the even-numbered data lines are connected to the electrodes, respectively, in Step S41, and the even-numbered data lines and the electrodes are disconnected from each other in Step S42.

Moreover, the reverse-polarity even-numbered cell single reading-out processing in Step S6ofFIG. 8, in Step S33ofFIG. 10, the same processing as the reserve-polarity odd-numbered cell single reading-out processing in Step S4ofFIG. 8is executed, and in Steps S40to S42, the same processing as the straight-polarity even-numbered cell single reading-out processing in Step S5ofFIG. 8is executed.

FIG. 11is a schematic circuit diagram showing a structure of a liquid crystal display device according to a second embodiment of the present invention.

In the liquid crystal display device200shown inFIG. 11, the display circuit61, the data line driving circuit62, the gate line driving circuit63, and a detection circuit201are disposed on the substrate51. It is noted that the same portions as those shown inFIG. 3are designated with the same reference numerals, respectively, and a repeated description thereof is omitted here for the sake of simplicity.

In the detection circuit201, switches211to214, and input terminals211A to214A are provided instead of providing the switches101and102shown inFIG. 3, and each of the potentials of the data lines D is set at the reference value Ve.

Each of the switches211to214, for example, is constituted by the FET. Gates of the switches211to214are each connected to the control circuit105. A drain of the switch211is connected to the input terminal211A having a potential of the reference value Ve, and a source thereof is connected to the data line Dn−1. The switch211connects the input terminal211A and the data line Dn−1to each other in accordance with a control signal supplied from the control circuit105, thereby setting the potential of the data line Dn−1at the reference value Ve.

In addition, a drain of the switch212is connected to the input terminal212A having a potential of the reference value Ve, and a source thereof is connected to the data line Dn. The switch212connects the input terminal212A and the data line Dnto each other in accordance with the control signal supplied from the control circuit105, thereby setting the potential of the data line Dnat the reference value Ve.

Moreover, a drain of the switch213is connected to the input terminal213A having a potential of the reference value Ve, and a source thereof is connected to the data line Dn+2. The switch213connects the input terminal213A and the data line Dn+2to each other in accordance with a control signal supplied from the control circuit105, thereby setting the potential of the data line Dn+2at the reference value Ve.

Also, a drain of the switch214is connected to the input terminal214A having a potential of the reference value Ve, and a source thereof is connected to the data line Dn+1. The switch214connects the input terminal214A and the data line Dn+1to each other in accordance with the control signal supplied from the control circuit105, thereby setting the potential of the data line Dn+1at the reference value Ve.

FIG. 12is a schematic circuit diagram showing a structure of a liquid crystal display device according to a third embodiment of the present invention.

In the liquid crystal display device300shown inFIG. 12, the display circuit61, the data line driving circuit62, the gate line driving circuit63, and a detection circuit301are disposed on the substrate51. It is noted that the same portions as those shown inFIG. 3orFIG. 11are designated with the same reference numerals, respectively, and a repeated description thereof is omitted here for the sake of simplicity.

The detection circuit301is obtained by combining the detection circuit64shown inFIG. 3, and the detection circuit201shown inFIG. 11with each other. That is to say, the detection circuit301is composed of the switches101and102, the comparators103and104, the control circuit105, the switches211to214, and the input terminals211A to214A.

In the detection circuit301, the switches211and212are turned ON in accordance with a control signal supplied from the control circuit105, so that each of the potentials of the data lines Dn−1and Dnbecomes equal to the reference value Ve. At the same time, the switch101is turned ON, so that the potentials of the data lines Dn−1and Dnbecome equal to each other.

Likewise, the switches213and214are turned ON in accordance with a control signal supplied from the control circuit105, so that each of the potentials of the data lines Dn+2and Dn+1becomes equal to the reference value Ve. At the same time, the switch102is turned ON, so that the potentials of the data lines Dn+2and Dn+1become equal to each other.

It is noted that although the user carries out the inspection for the fault by using the liquid crystal display device50in the above description, he/she can also carry out the inspection for the fault by using the substrate51. In this case, the fault can be found out before the liquid crystal layer53is held between the substrate51and the counter substrate52. Therefore, it is possible to reduce the assembly cost because the fault can be prevented from flowing out to the process for holding the liquid crystal layer53between the substrate51and the counter substrate52. Also, it is possible to reduce the number of man-hour necessary for a manufacture test because the fault can be discovered before an image quality test which is performed based on an image actually displayed.

In addition, in this specification, the step for describing the program to be stored in the program recording medium includes processing which is executed in parallel or individually although not being necessarily executed in a time series manner as well as processing which is executed in a time series manner in the described order.

Moreover, the embodiments of the present invention are not limited to those described above, and various changes thereof can be made without departing from the gist of the present invention.