Semiconductor device, integrated fan-out package and method of forming the same

A semiconductor device, an integrated fan-out package and a method of forming the same are disclosed. In some embodiments, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.

BACKGROUND

In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area.

These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of types of packages for semiconductors include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices, etc. Currently, integrated fan-out packages are becoming increasingly popular for their compactness. However, there are many challenges related to integrated fan-out packages.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG. 1AtoFIG. 1Fare cross-sectional views of a method of forming a semiconductor device in accordance with some embodiments.FIG. 2toFIG. 7are simplified top views of semiconductor devices in accordance with some embodiments, in which few elements such as a top metal layer, a passivation layer and an under bump metallization (UBM) layer are shown for simplicity and clarity of illustration.

Referring toFIG. 1A, at least one electronic component13is formed in a substrate12. In some embodiments, the substrate12includes a silicon-containing substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. In some embodiments, two electronic components13are embedded in a surface portion of the substrate12. In some embodiments, the electronic components13are integrated passive devices (IPD) including resistors, capacitors, inductors, resonators, filters, and/or the like. For example, the electronic components13are trench capacitors having same or different capacitance values, resonance frequencies, and/or sizes. However, the present disclosure is not limited thereto. In alternative embodiments, the electronic components13can be integrated active devices (IAD). In some embodiments, the substrate12may have isolation structures, through silicon vias (TSV) and/or doped regions upon the process requirements.

Referring toFIG. 1BandFIG. 1C, a conductive structure CS is formed over and electrically connected to the electronic components13. In some embodiments, the conductive structure CS is referred to as an interconnection structure. The conducive structure CS includes dielectric layers and conductive features. In some embodiments, the dielectric layers include silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material or a combination thereof and are formed by suitable processes such as chemical vapor deposition (CVD) or the like. Each of the dielectric layers may be a single layer or a multiple-layer structure. In some embodiments, the dielectric layers include a dielectric layer DL1and a dielectric layer DL2over the dielectric layer DL1. In some embodiments, the conductive features include conductive layers and vias. The conductive features include a metal-containing material, such as tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the conductive features and the dielectric layers to prevent the metal of the conductive features from migrating to the underlying electronic components13. The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example.

In some embodiments, as shown inFIG. 1B, a conductive layer M1is formed over and electrically connected to the electronic components13through the vias V1, and the conductive layer M1and the vias V1are embedded by the dielectric layer DL1. In some embodiments, the conductive layer M1and the vias V1are formed by a dual damascene process. Thereafter, as shown inFIG. 1C, a conductive layer M2is formed over and electrically connected to the conductive layer M1through the vias V2, and the conductive layer M2and the vias V2are embedded by the dielectric layer DL2. In some embodiments, the conductive layer M2and the vias V2are formed by a dual damascene process. However, the present disclosure is not limited thereto. Multiple single damascene processes or electroplating processes may be performed to form the conductive structure CS. The number of the dielectric layers or the conductive layers of the conductive structure CS is not limited by the present disclosure.

In some embodiments, the extending direction of the conductive layer M2is different from (e.g., perpendicular to) the extending direction of the conductive layer M1from a top view. In some embodiments, the conductive layer M2is a top metal layer having a plurality of line patterns MP substantially parallel to each other, as shown in the top views ofFIG. 2toFIG. 7. In some embodiments, the line patterns MP may be designed as power lines or ground lines.

In some embodiments, as shown inFIG. 2andFIG. 3, the line patterns MP are divided into first groups of line patterns and second groups of line groups alternately arranged, and each of the first and second groups includes, for example but not limited to, four line patterns MP. In some embodiments, the first groups of line patterns are power lines P, and the second groups of line patterns are ground lines G.

In alternative embodiments, as shown inFIG. 4andFIG. 5, the line patterns MP include a plurality of first line patterns MP1and a plurality of second line patterns MP2alternately arranged, and the first line patterns MP1are power lines P, and the second line patterns MP2are ground lines G.

In the embodiments ofFIG. 2toFIG. 5, the line patterns MP are designed as strips or bars. The strips may be straight strips or curve strips. The strips may have the same width. However, the present disclosure is not limited thereto. In some embodiments, upon the process requirements, each of the line patterns MP includes a plurality of wide parts WP and a plurality of narrow parts NP alternately arranged, as shown inFIG. 6andFIG. 7.

Afterwards, as shown inFIG. 1C, a passivation layer PA is formed over the conductive structure CS. In some embodiments, the passivation layer PA includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO) or a combination thereof, and is formed by a suitable process such as spin coating, CVD or the like. The passivation layer PA may be a single layer or a multiple-layer structure.

Referring toFIG. 1D, the passivation layer PA is patterned to form a plurality of openings OP therein. In some embodiments, the patterning operation includes performing photolithography and etching processes. In some embodiments, the openings OP penetrate through the passivation layer PA and expose portions of the line patterns MP of the conductive layer M2, as shown inFIG. 2toFIG. 7.

In some embodiments, as shown in the top view ofFIG. 2,FIG. 3,FIG. 6andFIG. 7, the openings OP of the passivation layer PA partially expose each of the line patterns MP of the conductive layer M2. However, the present disclosure is not limited thereto. In some embodiments, the openings OP of the passivation layer PA partially expose every other line pattern MP of the conductive layer M2, as shown inFIG. 4andFIG. 5.

In some embodiments, when each line pattern MP of the conductive layer M2has wide parts WP and narrow parts NP alternately arranged, the openings OP of the passivation layer PA partially expose the wide parts WP of the line patterns MP of the conductive layer M2, as shown inFIG. 6andFIG. 7.

The shapes of the openings OP of the passivation layer PA may be designed as needed. In some embodiments, the openings OP of the passivation layer PA are in a form of strips or bars, as shown inFIG. 2andFIG. 4. In some embodiments, the openings OP of the passivation layer PA are in a form of islands, as shown inFIG. 3andFIG. 5toFIG. 7. The islands may be circular, oval, triangular, square, rectangular, polygonal or a combination thereof. For example, the openings OP of the passivation layer PA are square, as shown inFIG. 3,FIG. 5andFIG. 6. For instance, the openings OP of the passivation layer PA are triangular, as shown in FIG.7. The shapes and configurations of the openings OP of the passivation layer PA are not limited to the present disclosure.

Referring toFIG. 1E, an under bump metallization (UBM) layer14is formed over the passivation layer PA and fills in the openings OP of the passivation layer PA. In some embodiments, the openings OP of the passivation layer PA are lined with the UBM layer14. Specifically, the UBM layer14is conformally formed on the top surface of the passivation layer PA and on the entire surfaces of the openings OP. The UBM layer14may include copper and/or titanium, and may be formed by a sputtering process.

Referring toFIG. 1EandFIG. 1F, bumps17are formed over the UBM layer14, and the bumps17fill in the openings OP of the passivation layer PA. In some embodiments, each of the bumps17includes a lower bump16and an upper bump18made by different materials. In some embodiments, as shown inFIG. 1E, a photoresist layer PR is formed on the UBM layer14. The photoresist layer PR is a dry film resist (DFR) and has openings that expose the intended locations for the subsequently formed bumps. Thereafter, as shown inFIG. 1F, lower bumps16are formed in the openings of the photoresist layer PR with an electrochemical plating (ECP) process. In some embodiments, the lower bumps16are plated in the openings of the photoresist layer PR by using the UBM layer14as a seed layer. In some embodiments, the lower bumps16include copper. Afterwards, upper bumps18are formed on the lower bumps16with evaporation, electroplating, ball drop, or screen printing. In some embodiments, the upper bumps18include solder. The bumps17including lower bumps16and upper bumps18are accordingly formed. The photoresist layer PR and the underlying UBM layer14are then removed. Therefore, the remaining UBM layer14is between the passivation layer PA and each of the lower bumps16of the bumps17. A bump structure BS including a bump17and an underlying UBM layer14is thus completed.

The structure of the semiconductor device of the present disclosure is illustrated below with reference to the cross-sectional view ofFIG. 1Fand the top views ofFIG. 2toFIG. 7.

In some embodiments, a semiconductor device10includes a substrate12, a conductive structure CS, a passivation layer PA and a bump structure BS. The substrate12has at least one electronic component13therein. In some embodiments, the at least one electronic component13includes an integrated passive device such as a trench capacitor. The conductive structure CS includes a conductive layer M1over and electrically connected to the at least one electronic component13, and a conductive layer M2over and electrically connected to the conductive layer M1. In some embodiments, the extending direction of the conductive layer M2is different from (e.g., perpendicular to) the extending direction of the conductive layer M1. Specifically, the conductive layer M2includes a plurality of lines patterns MP over and electrically connected to the at least one electronic component13. The passivation layer PA is over the conductive structure CS. The bump structure BS penetrates through the passivation layer PA and is electrically connected to the conductive layer M2.

In some embodiments, each bump structure BS includes a bump17and an UBM layer14between the bump17and the passivation layer PA. In some embodiments, the bump17includes a lower bump16and an upper bump18, and the lower bump16and the upper bump18include different materials. In some embodiments, as shown inFIG. 1F, each bump structure BS includes a main part M and a plurality of protruding parts P that protrude out from the main part M. The UBM layer14and a portion of the lower bump16constitute the protruding parts P of the bump structure BS. Specifically, the protruding parts P protrude out from the lower bump16of the bump17. The protruding parts P of the bump structure BS penetrate through the passivation layer PA and are electrically connected to the lines patterns MP of the conductive layer M2. From another point of view, each bump structure BS has a comb-like structure, the main part M is a comb shaft part, and the protruding parts P are comb tooth parts.

The protruding parts P of each bump structure BS are the parts filling in the corresponding openings PA of the passivation layer PA. Accordingly, the protruding parts P of the bump structure BS have a shape similar to that of the openings OP of the passivation layer PA, either from a cross-sectional view or from a top view. In some embodiments, the protruding parts P of each bump structure BS are in a form of islands or strips or combinations thereof. In some embodiments, as shown inFIG. 2toFIG. 6, the protruding parts P of each bump structure BS have a width W1and a length L1from a top view, and the ratio of the length L1to the width W1is about 1 or more, about 5 or more or about 10 or more.

The main part M of each bump structure BS is the part above the top surface of the passivation layer PA or the UBM layer14. The main part M of each bump structure BS has a shape similar to that of the UBM layer14from a top view. In some embodiments, as shown inFIG. 2toFIG. 6, the main parts M of each bump structure BS has a width W2and a length L2from a top view, and the ratio of the length L2to the width W2is about 1 or more, about 3 or more or about 5 or more.

In some embodiments, as shown in the top view ofFIG. 2,FIG. 3,FIG. 6andFIG. 7, the protruding parts P of the bumps structure BS partially expose each of the line patterns MP of the conductive layer M2. However, the present disclosure is not limited thereto. In some embodiments, the protruding parts P of the bumps structures BS partially expose every other line pattern MP of the conductive layer M2, as shown inFIG. 4andFIG. 5. In some embodiments, as shown inFIG. 6andFIG. 7, each of the line patterns MP has wide parts WP and narrow parts NP arranged alternately, and the protruding parts P of the bump structures BS physically contact the wide parts W of the line patterns MP. In some embodiments, from the top views ofFIG. 2toFIG. 7, the bump structures BS in adjacent columns are arranged in a staggered manner.

In the present disclosure, the conventional wide metal block is divided into multiple metal segments or lines, so the metal density and therefore the device cost are accordingly reduced. The semiconductor device of the present disclosure is a multi-terminal device such as a multi-terminal integrated passive device including capacitors. With such design, ESR (Equivalent Serial Resistance) and ESL (Equivalent Serial Inductance) properties of the device are reduced, and the reliability of the device is accordingly improved.

The multi-terminal semiconductor device of the present disclosure may be applied to various integrated circuits and/or printed circuit boards (PCBs) for operations as needed. The following embodiments in which the multi-terminal semiconductor device of the present disclosure is applied to an integrated fan-out package are provided for illustration purpose, and are not construed as limiting the present disclosure.

FIG. 8AtoFIG. 8Dare cross-sectional views of a method of forming an integrated fan-out packages in accordance with some embodiments.

Referring toFIG. 8A, a carrier C is provided with a semiconductor chip100and a plurality of through integrated fan-out vias TIV aside the semiconductor chip100. In some embodiments, the carrier C has a de-bonding layer DB and a dielectric layer DI formed thereon, and the de-bonding layer DB is between the carrier C and the dielectric layer DI. In some embodiments, the carrier C is a glass substrate, the de-bonding layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate, and the dielectric layer DI is a polymer layer formed on the de-bonding layer. For example, the dielectric layer DI includes polybenzoxazole (PBO), polyimide (PI), a suitable organic or inorganic material or the like. In some embodiments, the semiconductor chip100has a substrate100a, pads100bover the substrate100a, a passivation layer100cover the substrate100aand exposing portions of the pads100b, connectors100dover the passivation layer100cand electrically connected to the pads100b, and a protection layer100eover the passivation layer100cand aside the connectors100d. In some embodiments, the connectors100dinclude solder bumps, gold bumps, copper pillars or the like, and are formed by an electroplating process. In some embodiments, the protection layer100eincludes polybenzoxazole (PBO), polyimide (PI), a suitable organic or inorganic material or the like. In some embodiments, the through integrated fan-out vias TIV include copper and are formed by photolithography, plating, and photoresist stripping processes. In some embodiments, the semiconductor chip100is picked and placed on the carrier C with the backside thereof facing the dielectric layer DI, and the through integrated fan-out vias TIV are then formed on the carrier C. In some embodiments, a die attach film DAF is provided between the backside of the semiconductor chip100and the de-bonding layer DB of the carrier C.

Still referring toFIG. 8A, an encapsulant102is formed over the carrier C to encapsulate the semiconductor chip100and the through integrated fan-out vias TIV. In some embodiments, the encapsulant102surrounds the semiconductor chip100and the through integrated fan-out vias TIV, and exposes the surfaces of the through integrated fan-out vias TIV and the connectors100d. The encapsulant102includes a molding compound such as epoxy, a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI) or benzocyclobutene (BCB), a combination thereof or the like. The method of forming the encapsulant102includes forming an encapsulant material layer on the carrier C covering the semiconductor chip100and the through integrated fan-out vias TIV, and performing a grinding process to partially remove the encapsulant material layer until the surfaces of the through integrated fan-out vias TIV and the connectors100dare exposed.

Referring toFIG. 8B, a redistribution layer structure117is formed over and electrically connected to the semiconductor chip100. In some embodiments, the redistribution layer structure117is referred to as a front-side redistribution layer structure. In some embodiments, the redistribution layer structure117includes a plurality of polymer layers104,108,112and116and a plurality of redistribution layers106,110and114stacked alternately. Specifically, the redistribution layer106is electrically connected to the connectors100dand the through integrated fan-out vias TIV and penetrates through the polymer layer104, the redistribution layer110is electrically connected to the redistribution layer106and penetrates through the polymer layer108, the redistribution layer114is electrically connected to the redistribution layer110and penetrates through the polymer layer112, and the polymer layer116covers the redistribution layer114. In some embodiments, each of the polymer layers104,108,112and116includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, each of the redistribution layers106,110and114includes copper, nickel, titanium, a combination thereof or the like, and is formed by an electroplating process. The number of the polymer layers or the redistribution layers of the redistribution layer structure117is not limited by the present disclosure.

Still referring toFIG. 8B, a plurality of connection pads118aand a plurality of UBM pads118bare formed over the redistribution layer structure117. The connection pads118aand the UBM pads118bare electrically connected to the redistribution layer structure117. In some embodiments, the UBM pads118bsurround the connection pads118a. In some embodiments, the connection pads118aand the UBM pads118binclude copper, nickel, titanium, a combination thereof or the like, and are formed by an electroplating process. In some embodiments, the UBM pads118bhave a dimension greater than that of the connection pads118a.

Referring toFIG. 8C, at least one semiconductor device10is bonded to the connection pads118athrough the bump structures BS, and a plurality of bumps B1is placed on and electrically connected to the UBM pads118b. In some embodiments, the semiconductor device10having bump structures BS is bonded to the connection pads118awith the front side thereof facing the front-side redistribution layer structure117. In some embodiments, the semiconductor device10is an integrated passive device including resistors, capacitors, inductors, resonators, filters, and/or similar elements. In alternative embodiments, the semiconductor device10can be an integrated active device upon the process requirements. In some embodiments, the dimension of the bumps B1is greater than the dimension of the bump structures BS.

The material, element relationship and forming method of the bump structures BS have been described above, so the details are not iterated herein. The bumps B1may be solder bumps, and/or may include metal pillars (e.g., copper pillars), solder caps formed on metal pillars, and/or the like. The bumps B1may be formed respectively by a suitable process such as evaporation, electroplating, ball drop, or screen printing.

Referring toFIG. 8D, the carrier C is de-bonded from the backside of the structure ofFIG. 8C. In some embodiments, the de-bonding layer DB is decomposed under heat of light, and the carrier C is then released from the structure formed thereon.

As shown inFIG. 8D, the dielectric layer DI is patterned such that openings are formed to expose the bottom surfaces of the through integrated fan-out vias TIV. In some embodiments, the number of the openings correspond to the number of the through integrated fan-out vias TIV. In some embodiments, the openings of the dielectric layer DI are formed by a laser drilling process or another suitable patterning process.

Still referring toFIG. 8D, another package200is provided. In some embodiments, the package200includes a memory device or another suitable semiconductor device. In some embodiments, the package200has bumps B2on one side thereof. The bumps B2may be solder bumps, and/or may include metal pillars (e.g., copper pillars), solder caps formed on metal pillars, and/or the like. The bumps B2may be formed respectively by a suitable process such as evaporation, electroplating, ball drop, or screen printing. In some embodiments, the dimension of the bumps B2is between the dimension of the bump structures BS and the dimension of the bumps B1.

Thereafter, the bumps B2of the package200are inserted into the openings of the dielectric layer DI of the integrated fan-out package1, such that a package-on-package (POP) structure is fabricated.

The structure of the integrated fan-out package of the present disclosure is illustrated below with reference toFIG. 8Das well asFIG. 1FandFIGS. 2-7.

In some embodiments, an integrated fan-out package1includes a semiconductor chip100, a redistribution layer structure117, a plurality of connection pads118aand a semiconductor device10. The redistribution layer structure117is over and electrically connected to the semiconductor chip100. The connection pads118aare over and electrically connected to the redistribution layer structure117. The semiconductor device10is over and electrically connected to the connection pads118athrough a plurality of bump structures BS thereof. In some embodiments, each of the bump structures BS has a main part M and a plurality of protruding parts P extending from the main part M and embedded by a passivation layer PA of the semiconductor device10.

In some embodiments, as shown inFIG. 1F, the semiconductor device10includes a substrate12having at least one electronic component13therein, and a conductive layer M2having a plurality of lines patterns MP electrically connected to the at least one electronic component13. In some embodiments, the at least one electronic component13includes an integrated passive device such as a trench capacitor. In some embodiments, the line patterns MP of the conductive layer M2physically contact the protruding parts P of the bumps structures BS.

In some embodiments, the protruding parts P of each of the bump structures BS partially expose each of the line patterns MP of the conductive layer M2, as shown inFIG. 2,FIG. 3,FIG. 6andFIG. 7. In alternative embodiments, the protruding parts P of each of the bump structures BS partially expose every other line pattern MP of the conductive layer M2, as shown inFIG. 4andFIG. 5.

In some embodiments, the integrated fan-out package1further includes a plurality of UBM pads118band a plurality of bumps B1. The UBM pads118bare electrically connected to the redistribution layer structure117and surround the connection pads118a. The bumps B1are electrically connected to the UBM pads118a. In some embodiments, the dimension of the bumps B1is greater than the dimension of the bump structures BS of the semiconductor device10. In some embodiments, a plurality of through integrated fan-out vias TIV is further included in the integrated fan-out package1. The through integrated fan-out vias TIV are located around the semiconductor chip100.

In accordance with some embodiments of the present disclosure, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.

In accordance with alternative embodiments of the present disclosure, a method of forming an integrated fan-out package includes at least the following operations. At least one electronic component is formed in a substrate. A conductive structure is formed over and electrically connected to the at least one electronic component. A passivation layer is formed over the conductive structure. The passivation layer is patterned to form a plurality of openings therein. An under bump metallization (UBM) layer is formed on a top of the passivation layer and on surfaces of the openings. A bump is formed over the UBM layer, the bump filling in the openings of the passivation layer.

In accordance with yet alternative embodiments of the present disclosure, an integrated fan-out package includes a semiconductor chip, a redistribution layer structure, a plurality of connection pads and a semiconductor device. The redistribution layer structure is over and electrically connected to the semiconductor chip. The connection pads are over and electrically connected to the redistribution layer structure. The semiconductor device is over and electrically connected to the connection pads through a plurality of bump structures thereof. In some embodiments, each of the bump structures has a main part and a plurality of protruding parts extending from the main part and embedded by a passivation layer of the semiconductor device.