Post-grind die backside power delivery

Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.

TECHNICAL FIELD

Embodiments described generally herein relate to microelectronic packages. More particularly, embodiments described generally herein relate to power delivery features within microelectronic packages.

BACKGROUND

Microelectronics generally include a central processing unit (CPU). In order to enhance performance, CPU products are increasingly integrating multiple dies within the CPU package in a side-by-side or other multi-chip module (MCM) format.

DETAILED DESCRIPTION

Multichip modules may pack more than one integrated circuit (IC) into a package. Due to the ever advancing capabilities of the ICs. the tolerances for package limitations may be shrinking. One limitation may be the capability for wirebonds to delivery power to the IC with integrity to the desired voltage and against noise. Power delivery in the IC itself may be limited by the microscopic feature sizes of its production and through competition for space by functional gates.

As disclosed herein, power may be delivered within the IC through the addition of redistribution layer patterning in the post-grind step of the IC packaging. This redistribution layer may provide use to a surface on the backside of the IC to improve power delivery, integrity, and noise resistance. The redistribution layer may be a layer of material or may be series of strips or channels of material. For example, post-grind die backside features may be patterned on to the back of the die using simpler, less precise, and less risky patterning steps.

Turning now to the figures,FIG. 1illustrates a microelectronic package100. The microelectronic package100can include a first die102, a second die104, a package interconnect106, and substrate108. As shown inFIG. 1, the microelectronic package100can also include electrical connections110that can be used to power the first die102and the second die104and allow signals to pass between the first die102and the second die104. The electrical connections110can also be used to provide ground references. The package interconnect106can be surrounded by, or embedded in, the substrate108. In addition, the package interconnect106can include a silicon bridge, a silicon interposer, a fan-out wafer level package interconnect, a fan-out panel level package interconnect, and an organic dense multichip package interconnect. WhileFIG. 1illustrates an embedded multi-die interconnect bridge (EMIB), the various embodiments disclosed herein are not limited to EMIB technologies.

FIG. 2illustrates a die stack200using a zigzag wirebond, such as part of the microelectronics package100. The die stack200may include a first material layer202A, a second material layer202B, a third material layer202C, and a forth material layer202D (collectively material layers202). The material layers202may be located atop a substrate204. The material layers202may be electrically connected to the substrate204, directly or via another material layer. For example, the second material layer202B and the fourth material layer202D may be directly connected to the substrate204via wirebonds208and210, respectively, as shown inFIG. 2. The first material layer202A may be electrically connected to the second material layer202B and the third material layer202C may be electrically connected to the fourth material layer202D via wirebonds212and214, respectively.

The zigzag placement of the material layers202may result in a reduced Z-height, Z1, of the die stack200. In addition, a film over wire (FOW), not shown, may add additional height to the Z-height. The material layers202may be one or more dies that form the die stack200.

FIG. 3illustrates a die stack300using a stacked wirebond, such as part of the microelectronics package100. The die stack300may include a first material layer302A, a second material layer302B, a third material layer302C, and a fourth material layer302D (collectively material layers302). The material layers302may be located atop a substrate304. The material layers302may be electrically connected to the substrate304, directly or via another material layer. For example, the material layers302may be directly connected to the substrate304via wirebonds306and308.

The placement of the material layers302may result in an increase in a Z-height, Z2, of the die stack300due to space needed between the material layers202to accommodate the wirebonds306and308. In addition, a film over wire, not shown, may add additional height to the Z-height. The material layers302may be one or more dies that form the die stack300.

FIGS. 4A and 4Billustrate a top side402and a backside404, respectively, of a die400, such as part of the microelectronics package100. The die400may be manufactured from a semiconductor material such as silicon. In addition, the die400may be one of a plurality of dies, that are part of a silicon wafer as described herein.

The die400may include a plurality of vias406. The plurality of vias406may be through silicon vias (TSV). The plurality of vias406may pass partially or completely through the die400. The plurality of vias406may receiving an electrically conductive material, such as copper or aluminum, to facilitate electrical connections as disclosed herein.

The backside404of the die400may include a first metal channel408A, a second metal channel408B, a third metal channel408C, and a fourth metal channel408D (collectively metal channels408). The metal channels408may be formed of any electrically conductive material. In addition, the metal channels408may be formed via sputter coating or spin coating.

Each of the metal channels408may contact one or more of the plurality of vias406. As a result, the metal channels408may allow for electrical connection of one or more subsections of the plurality of vias408. In addition, the each of the plurality of metal channels408may have a width that is substantially wider than a width of a signal trace of the die400. For example, each of the plurality of metal channels408may have a width that is one or two orders of magnitude larger than the width of the signal traces. By having a width that is larger than the signal traces, the metal channels408may help shield the signal traces form interference such as electromagnetic interference. In addition, the metal channels408may help to minimize cross talk between dies that are stacked or otherwise located adjacent to one another. The metal channels408may be made of copper, gold, platinum, aluminum, et.

In addition, the die400may include a plurality of pad connections410. The plurality of pad connections410may allow power to flow from a substrate, such as substrate204or304, to the vias406. For example, the pad connections410may extend through the material layer and contact one or more of the metal channels408.

WhileFIGS. 4A and 4Bshow a single die400having a material layer and vias406, multiple dies may be stacked as disclosed herein. For example, a second material layer may be located on top of the die400. The various material layers may be separated by an insulator or other material that may allow the various material layers to be electrically isolated from one another. The second, or subsequent, material layer may include a top side and a backside connected by a plurality of vias and pad connections just as die400.

For example, a microelectronics package, such as microelectronics package100, may include a substrate, a first die and a second die. The first die may be at least partially embedded within the substrate and may include a first material layer, a first plurality of vias, and a first plurality of metal channels. The first material layer may have a first top side and a first backside. The first top side may include a first plurality of pad connections. The first plurality of vias may extend through the first material layer from the first top side to the first backside. The first plurality of metal channels may be in contact with the first backside. Each of the first plurality of metal channels may be in electrical communication with at least one of the first plurality of pad connections and at least one of the first plurality of vias.

The second die may include a second material layer, a second plurality of vias, and a second plurality of metal channels. The second material layer may have a second top side and a second backside. The second top side may include a second plurality of pad connections in electrical communication with the first plurality of pad connections. The second plurality of vias may extend through the second material layer from the second top side to the second backside. The second plurality of metal channels may be in contact with the second backside. Each of the second plurality of metal channels may be in electrical communication with at least one of the second plurality of pad connections and at least one of the second plurality of vias.

Furthermore, a third die may be included in the microelectronics package. The third die may be connected to the first die or the second die via a bridge or other electrical connections. One or more of the metal channels may form a reference plane. In addition, the dies may include IC electrically coupled to the metal channels, vias, pad connections, etc.

FIG. 5illustrates a method500for manufacturing a die, such as die400, in accordance with some embodiments disclosed herein. The method500may begin at stage502where a material layer may be received. The material layer, such as any one of material layers202or204, may have a top side and a backside as disclosed herein. Once received, a backside of the material layer may be ground to a desired or predetermined thickness (e.g., 30-300 microns).

From stage502, the method500may proceed to stage504where a plurality of holes may be formed in the material layer. For example, the plurality of holes may be formed using plasma etching. From stage504, the method500may proceed to stage506where a plurality of vias may be formed. For example, the plurality of vias may be formed by filling the plurality of holes with an electrically conductive material, such as copper, aluminum, gold, etc.

From stage506, the method500may proceed to stage508where the plurality of metal channels may be formed. To form the metal channels a mask may be applied to the backside of the material layer using photolithography or silkscreen printing. The mask may define the size, shape, and location of the metal channels. Once the mask is applied, the metal channels may be formed via sputter coating or spin coating the backside of the dia. Once the metal has been applied, the mask can be removed.

The mask does not need to be especially fine. For example, the mask may be on the order of 20 to 100 microns compared to the less than 1 micron feature size of the IC on the top side of the material layer. The die may be formed adjacent or proximate the die. For example, the die may be formed on a wafer material, such as silicon. Once the various dies are formed on the wafer, the dies may be separated from the wafer.

The method500may also be utilized to manufacture a microelectronics package, such as microelectronics100. For example, after a die is formed, the die may be embedded, partially or completely, into a substrate. The second die can be stacked on top of the first die and the first die can be electrically coupled to second die via the pad connections. In addition, a third die or more dies may be connected to the first die or the second die via the pad connections using wire bonding or other bridges.

FIGS. 6A-6Cillustrate a top side602, a first metal layer604, and a second metal layer606of a die600in accordance with some embodiments disclosed herein. The die600may include a material layer as disclosed herein. The material layer may define a plurality of vias608that may extend through the material layer. As shown inFIG. 6B, the first metal layer604may include a plurality of voids610. The voids610may allow a first subset of the vias608to pass through the first metal layer604and contact the second metal layer606. Thus, the first metal layer604and the second metal layer606may be at different potentials. For example, the first metal layer604may provide power to the die600and the second metal layer606may be a reference plane. The first metal layer604and the second metal layer606may be separated by a dielectric614or other insulating material. Pad connections612may allow power to be delivered to the die600.

The first metal layer604and the second metal layer606may form a capacitor. As shown inFIG. 6D, the grinding of the silicon backside may increase surface roughness, increase surface area, thereby increasing capacitance. The capacitance of the first metal layer604and the second metal layer606may be estimated as:

Where k is the dielectric constant (e.g. 6), ε0is 8.854E-12 F/m, A is the surface area of the metal layers, and d is the distance between the metal layers. The surface area may be estimated as the length times the width of the metal layers times a factor to account for the surface roughness. For example, assume the various ridges and troughs of the surface are at 45° then the adjustment factor may be 1.41 (the square root of 2). The rougher the surfaces of the metal layers, the greater the capacitance.

Faster data transfer rates, increased performance, and lithography technologies may increase capacitance demands on circuits. To meet this increased capacitance demand, discrete components may be integrated into the IC packaging, or placed board level. Integrating capacitance into the silicon may decrease the electrical length thereby increasing the circuit's reaction time, and reducing the BOM.

Depending on the circuit need and the cost benefit ratio of implementation, further metal layers may be added to increase capacitance and number of power delivery nets. For example, adding a third layer could increase the added capacitance by 100%, or provide capacitance for a different voltage needed by the integrated circuit.

WhileFIGS. 6A-6Drefer to a single die600, multiple dies may be created having a configuration as disclosed inFIGS. 6A-6D. The various dies may be stacked on top of one another or located adjacent one another. For example, a second die may include a second material layer, a second plurality of vias, a third metal layer, and a fourth metal layer that may be arranged in a similar manner as described with respect to the die600. In addition, the die600may be combined with the die400in forming a microelectronics package, such as microelectronics package100.

FIG. 7illustrates a method700for manufacturing a die, such as die600. The method700may begin at stage702where a material layer may be received. The material layer, such as any one of material layers202or204, may have a top side and a backside as disclosed herein. Once receive, a backside of the material layer may be ground to a desired or predetermined thickness (e.g., 30-300 microns).

From stage702, the method700may proceed to stage704where a plurality of holes may be formed in the material layer. For example, the plurality of holes may be formed using plasma etching. From stage704, the method700may proceed to stage706where a plurality of vias may be formed. For example, the plurality of vias may be formed by filling the plurality of holes with an electrically conductive material, such as copper, aluminum, gold, etc.

From stage706, the method700may proceed to stage708where a first metal layer may be formed. The first metal layer may be formed such that a subset of the vias contact the first metal layer as described herein. From stage708, the method700may proceed to stage710where a passive layer may be formed adjacent the first metal layer. For example, a dielectric material may be applied to an exposed surface of the first metal layer. The passive layer may be adjusted to result in a desired capacitance. For example, the dielectric material or the thickness of the passive layer may be selected to achieve a desired capacitance.

From stage710, the method700may proceed to stage712where a second metal layer may be formed adjacent the second metal layer. The second metal layer may contact a second subset of the vias. Formation of the first and second metal layer may be accomplished using sputter coating or spin coating. In addition, masks may be used in forming the metal layers such that openings within the metal layers may facilitate passage of the vias from the material layer to the various metal layers. In addition to a second metal layer, a third metal layer, or more metal layers, may be formed as disclosed herein.

In addition to forming dies, the method700may be part of a method for manufacturing microelectronics packages. For example, a die may be formed as disclosed above and embedded within a substrate. A second die, a third die, etc. may be formed as disclosed herein and stacked on top of the first die or located adjacent the first die to form a microelectronics package. The various dies can be electrically coupled via a plurality of pad connections as disclosed herein.

FIG. 8illustrates a system level diagram, according to one embodiment. For instance.FIG. 8depicts an example of an electronic device (e.g., system) including the microelectronics package100or the signaling system as described herein with reference toFIGS. 1-6B.FIG. 8is included to show an example of a higher level device application for embodiments disclosed herein. In one embodiment, system800includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system800is a system on a chip (SOC) system.

In one embodiment, processor810has one or more processing cores812and812Nc, where812Ncrepresents the Nth processor core inside processor810where Ncis a positive integer. In one embodiment, system800includes multiple processors including810and805, where processor805has logic similar or identical to the logic of processor810. In some embodiments, processing core812includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, and the like. In some embodiments, processor810has a cache memory816to cache instructions and/or data for system800. Cache memory816may be organized into a hierarchical structure including one or more levels of cache memory.

In some embodiments, processor810includes a memory controller814, which is operable to perform functions that enable the processor810to access and communicate with memory830that includes a volatile memory832and/or a non-volatile memory834. In some embodiments, processor810is coupled with memory830and chipset820. Processor810may also be coupled to an antenna878to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the antenna interface878operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory832includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), Rambus Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory834includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory830stores information and instructions to be executed by processor810. In one embodiment, memory830may also store temporary variables or other intermediate information while processor810is executing instructions. In the illustrated embodiment, chipset820connects with processor810via Point-to-Point (PtP or P-P) interfaces817and822. Chipset820enables processor810to connect to other elements in system800. In some embodiments, interfaces817and822operate in accordance with a PtP communication protocol such as the Intel QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset820is operable to communicate with processor810,805, display device840, and other devices872,876,874,860,862,864,866,877, etc. Chipset820may also be coupled to an antenna878to communicate with any device configured to transmit and/or receive wireless signals.

Chipset820connects to display device840via interface (I/F)826. Display840may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments, processor810and chipset820are merged into a single SOC. In addition, chipset820connects to one or more buses850and855that interconnect various elements874,860,862,864, and866. Buses850and855may be interconnected together via a bus bridge872. In one embodiment, chipset820couples with a non-volatile memory860, a mass storage device(s)862, a keyboard/mouse864, a network interface866, smart TV876, consumer electronics877, etc., via interface824.

While the modules shown inFIG. 8are depicted as separate blocks within the system800, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory816is depicted as a separate block within processor810, cache memory816(or selected aspects of816) can be incorporated into processor core812.

ADDITIONAL NOTES & EXAMPLES

Example 1 is a die comprising: a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection; a plurality of vias extending through the material layer from the top side to the backside; and a plurality of metal channels in contact with the backside, each of the plurality of metal channels in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias, at least one of the plurality of metal channels in electrical communication with the power connection.

In Example 2, the subject matter of Example 1 optionally includes wherein the material layer is comprised of a semiconductor material.

In Example 3, the subject matter of any one or more of Examples 1-2 optionally include wherein the die is one of a plurality of dies located on a semiconductor wafer.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the top side comprises integrated circuitry in electrical communication with the plurality of pad connections.

In Example 5, the subject matter of any one or more of Examples 1-4 optionally include wherein at least one of the plurality of metal channels is a reference plane.

In Example 6, the subject matter of any one or more of Examples 1-5 optionally include wherein each of the plurality of metal channels are substantially wider than a width of each of a plurality of signal traces located on the top side of the material layer.

In Example 7, the subject matter of any one or more of Examples 1-6 optionally include wherein each of the plurality of metal channels has a width at least one order of magnitude greater than a width of each of a plurality of signal traces located on the top side of the material layer.

In Example 8, the subject matter of any one or more of Examples 1-7 optionally include wherein the die is a component of a memory board, a motherboard, a sound card, or a video card.

In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the plurality of metal channels are manufactured from a metal selected from the group consisting of copper, gold, platinum, or aluminum.

In Example 10, the subject matter of any one or more of Examples 1-9 optionally include a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections connected to the plurality of pad connections; a second plurality of vias extending through the second material layer from the second top side to the second backside; and a second plurality of metal channels in contact with the second backside, each of the second plurality of metal channels in electrical communication with at least one of the second plurality of pad connections and at least one of the second plurality of vias.

Example 11 is a microelectronics package comprising: a substrate; a first die at least partially embedded within the substrate, the first die comprising: a first material layer having a first top side and a first backside, the first top side including a first plurality of pad connections, a first plurality of vias extending through the first material layer from the first top side to the first backside, and a first plurality of metal channels in contact with the first backside, each of the first plurality of metal channels in electrical communication with at least one of the first plurality of pad connections and at least one of the first plurality of vias; and a second die comprising: a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections in electrical communication with the first plurality of pad connections, a second plurality of vias extending through the second material layer from the second top side to the second backside, and a second plurality of metal channels in contact with the second backside, each of the second plurality of metal channels in electrical communication with at least one of the second plurality of pad connections and at least one of the second plurality of vias.

In Example 12, the subject matter of Example 11 optionally includes a third die; and a bridge electrically connecting third die to at least one of the first die and the second die.

In Example 13, the subject matter of any one or more of Examples 11-12 optionally include a third die; and a bridge electrically connecting third die to the first die.

In Example 14, the subject matter of any one or more of Examples 11-13 optionally include a third die; and a bridge electrically connecting third die to the second die.

In Example 15, the subject matter of any one or more of Examples 11-14 optionally include wherein the first material layer and the second material layer are comprised of a semiconductor based material.

In Example 16, the subject matter of any one or more of Examples 11-15 optionally include wherein the first top side comprises first integrated circuitry in electrical communication with the first plurality of pad connections.

In Example 17, the subject matter of any one or more of Examples 11-16 optionally include wherein the second top side comprises second integrated circuitry in electrical communication with the second plurality of pad connections.

In Example 18, the subject matter of any one or more of Examples 11-17 optionally include wherein the first plurality of metal channels is a reference plane.

In Example 19, the subject matter of any one or more of Examples 11-18 optionally include wherein each of the first plurality of metal channels are substantially wider than a width of each of a first plurality of signal traces located on the first top side of the first material layer.

In Example 20, the subject matter of any one or more of Examples 11-19 optionally include wherein each of the second plurality of metal channels are substantially wider than a width of each of a second plurality of signal traces located on the second top side of the second material layer.

In Example 21, the subject matter of any one or more of Examples 11-20 optionally include wherein each of the first plurality of metal channels has a width at least one order of magnitude greater than a width of each of a first plurality of signal traces located on the first top side of the first material layer.

In Example 22, the subject matter of any one or more of Examples 11-21 optionally include wherein each of the second plurality of metal channels has a width at least one order of magnitude greater than a width of each of a second plurality of signal traces located on the second top side of the second material layer.

In Example 23, the subject matter of any one or more of Examples 11-22 optionally include wherein the microelectronics package is a component of computing device.

In Example 24, the subject matter of any one or more of Examples 11-23 optionally include wherein the first plurality of metal channels and the second plurality of metal channels are manufactured from a metal selected from the group consisting of copper, gold, platinum, or aluminum.

Example 25 is a method of manufacturing a die, the method comprising: receiving a material layer having top side and a backside; forming a plurality of holes in the material layer; forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes; and forming a plurality of metal channels on the backside of the material layer, each of the plurality of metal channels electrically connecting a corresponding subset of the plurality of vias.

In Example 26, the subject matter of Example 25 optionally includes grinding the backside of the material layer until the material layer is a predetermined thickness.

In Example 27, the subject matter of any one or more of Examples 25-26 optionally include applying a mask to the backside of the material layer prior to forming the plurality of metal channels, the mask defining a location and shape for each of the plurality of metal channels.

In Example 28, the subject matter of any one or more of Examples 25-27 optionally include wherein forming the plurality of metal channels includes sputter coating or spin coating the backside with a metal.

In Example 29, the subject matter of any one or more of Examples 25-28 optionally include separating the material layer from a wafer.

In Example 30, the subject matter of any one or more of Examples 25-29 optionally include forming a second die proximate the die.

Example 31 is a method of manufacturing a microelectronics package, the method comprising: forming a substrate; forming a first die and a second die, wherein forming each of the first die and the second die comprises: plurality of holes in a material layer having a top side and a backside, forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes, and forming a plurality of metal channels on the backside of the material layer, each of the plurality of metal channels electrically connecting a corresponding subset of the plurality of vias; embedding, at least partially, the first die into the substrate; stacking the second die on top of the first die; and electrically coupling the first die to the second die via a plurality of pad connections.

In Example 32, the subject matter of Example 31 optionally includes wherein forming the first die and the second die further comprises grinding the backside of the material layer until the material layer is a predetermined thickness.

In Example 33, the subject matter of any one or more of Examples 31-32 optionally include wherein forming the first die and the second die further comprises applying a mask to the backside of the material layer prior to forming the plurality of metal channels, the mask defining a location and shape for each of the plurality of metal channels.

In Example 34, the subject matter of any one or more of Examples 31-33 optionally include wherein forming the plurality of metal channels includes sputter coating or spin coating the backside with a metal.

In Example 35, the subject matter of any one or more of Examples 31-34 optionally include wherein forming the first die and the second die further comprises separating the material layer from a wafer.

In Example 36, the subject matter of any one or more of Examples 31-35 optionally include attaching a third die to the substrate and electrically coupling the third die to the first die.

In Example 37, the subject matter of any one or more of Examples 31-36 optionally include attaching a third die to the substrate and electrically coupling the third die to the second die.

In Example 38, the subject matter of any one or more of Examples 31-37 optionally include attaching a third die to the substrate and electrically coupling the third die to the first die and the second die.

Example 39 is a die comprising: a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection; a plurality of vias extending through the material layer from the top side to the backside; a first metal layer in contact with the backside, the first metal layer in electrical communication with at least one of the plurality of pad connections and a first subset of the plurality of vias; and a second metal layer located adjacent to the first metal layer and separated by a dielectric, the second metal layer in electrical communication with a second subset of the plurality of vias, wherein the first metal layer or the second metal layer is in electrical communication with the power connection.

In Example 40, the subject matter of Example 39 optionally includes wherein the material layer is comprised of a semiconductor based material.

In Example 41, the subject matter of any one or more of Examples 39-40 optionally include wherein the die is one of a plurality of dies located on a semiconductor wafer.

In Example 42, the subject matter of any one or more of Examples 39-41 optionally include wherein the top side comprises integrated circuitry in electrical communication with the plurality of pad connections.

In Example 43, the subject matter of any one or more of Examples 39-42 optionally include wherein the second metal layer is reference planes.

In Example 44, the subject matter of any one or more of Examples 39-43 optionally include wherein the die is a component of a memory board, a motherboard, a sound card, or a video card.

In Example 45, the subject matter of any one or more of Examples 39-44 optionally include wherein the first metal layer and the second metal layer are manufactured from a metal selected from the group consisting of copper, gold, platinum, or aluminum.

In Example 46, the subject matter of any one or more of Examples 39-45 optionally include a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections connected to the plurality of pad connections; a second plurality of vias extending through the second material layer from the second top side to the second backside; a third metal layer in contact with the second backside, the third metal layer in electrical communication with at least one of the second plurality of pad connections and a first subset of the second plurality of vias; and a fourth metal layer located adjacent to the third metal layer and separated by a second dielectric, the fourth metal layer in electrical communication with a second subset of the second plurality of vias.

Example 47 is a microelectronics package comprising: a substrate; a first die at least partially embedded within the substrate, the first die comprising: a first material layer having a first top side and a second backside, the first top side including a first plurality of pad connections, a first plurality of vias extending through the first material layer from the first top side to the first backside, a first metal layer in contact with the first backside, the first metal layer in electrical communication with at least one of the first plurality of pad connections and a first subset of the first plurality of vias, and a second metal layer located adjacent to the first metal layer and separated by a first dielectric, the second metal layer in electrical communication with a second subset of the first plurality of vias; a second die comprising: a second material layer having a second top side and a second backside, the second top side including a second plurality of pad connections in electrical communication with the first plurality of pad connections, a second plurality of vias extending through the second material layer from the second top side to the second backside, and a third metal layer in contact with the second backside, the third metal layer in electrical communication with at least one of the second plurality of pad connections and a first subset of the second plurality of vias, and a fourth metal layer located adjacent to the third metal layer and separated by a second dielectric, the fourth metal layer in electrical communication with a second subset of the second plurality of vias.

In Example 48, the subject matter of Example 47 optionally includes a third die; and a bridge electrically connecting third die to at least one of the first die and the second die.

In Example 49, the subject matter of any one or more of Examples 47-48 optionally include a third die; and a bridge electrically connecting third die to the first die.

In Example 50, the subject matter of any one or more of Examples 47-49 optionally include a third die; and a bridge electrically connecting third die to the second die.

In Example 51, the subject matter of any one or more of Examples 47-50 optionally include wherein the first material layer and the second material layer are comprised of a semiconductor based material.

In Example 52, the subject matter of any one or more of Examples 47-51 optionally include wherein the first top side comprises first integrated circuitry in electrical communication with the first plurality of pad connections.

In Example 53, the subject matter of any one or more of Examples 47-52 optionally include wherein the second top side comprises second integrated circuitry in electrical communication with the second plurality of pad connections.

In Example 54, the subject matter of any one or more of Examples 47-53 optionally include wherein the first metal layer is a reference plane.

In Example 55, the subject matter of any one or more of Examples 47-54 optionally include wherein the third metal layer is a reference plane.

In Example 56, the subject matter of any one or more of Examples 47-55 optionally include wherein the second and fourth metal layers are reference plane.

In Example 57, the subject matter of any one or more of Examples 47-56 optionally include wherein the microelectronics package is a component of computing device.

In Example 58, the subject matter of any one or more of Examples 47-57 optionally include wherein the first, second, third, and fourth metal layers are manufactured from a metal selected from the group consisting of copper, gold, platinum, or aluminum.

Example 59 is a method of manufacturing a die, the method comprising: receiving a material layer having top side and a backside; forming a plurality of holes in the material layer; forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes; forming a first metal layer on the backside of the material layer, the metal layer electrically connecting a corresponding first subset of the plurality of vias; forming a passive layer adjacent the first metal layer; and forming a second metal layer on the passive layer, the second metal layer electrically connecting a corresponding second subset of the plurality of vias.

In Example 60, the subject matter of Example 59 optionally includes grinding the backside of the material layer until the material layer is a predetermined thickness.

In Example 61, the subject matter of any one or more of Examples 59-60 optionally include applying a mask to the backside of the material layer prior to forming the first metal layer, the mask defining a location for each of the first plurality second subset of the plurality of vias to pass through the first metal layer.

In Example 62, the subject matter of any one or more of Examples 59-61 optionally include wherein forming the first metal layer includes sputter coating or spin coating the backside with a metal.

In Example 63, the subject matter of any one or more of Examples 59-62 optionally include wherein forming the second metal layer includes sputter coating or spin coating one side of the passive layer.

In Example 64, the subject matter of any one or more of Examples 59-63 optionally include separating the material layer from a wafer.

In Example 65, the subject matter of any one or more of Examples 59-64 optionally include forming a second die proximate the die.

In Example 66, the subject matter of any one or more of Examples 59-65 optionally include grinding the first metal layer or the second metal layer to increase surface roughness.

Example 67 is a method of manufacturing a microelectronics package, the method comprising: forming a substrate; forming a first die and a second die, wherein forming each of the first die and the second die comprises: plurality of holes in a material layer having a top side and a backside, forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes, forming a first metal layer on the backside of the material layer, the first metal layer electrically connecting a corresponding first subset of the plurality of vias, forming a passive layer adjacent the first metal layer, and forming a second metal layer on a side of the passive layer, the second metal layer electrically connecting a corresponding second subset of the plurality of vias; embedding, at least partially, the first die into the substrate; stacking the second die on top of the first die; and electrically coupling the first die to the second die via a plurality of pad connections.

In Example 68, the subject matter of Example 67 optionally includes wherein forming the first die and the second die further comprises grinding the backside of the material layer until the material layer is a predetermined thickness.

In Example 69, the subject matter of any one or more of Examples 67-68 optionally include wherein forming the first die and the second die further comprises applying a mask to the backside of the material layer prior to forming the first metal layer, the mask defining a location for each of the first plurality second subset of the plurality of vias to pass through the first metal layer.

In Example 70, the subject matter of any one or more of Examples 67-69 optionally include wherein forming the first metal layer includes sputter coating or spin coating the backside with a metal.

In Example 71, the subject matter of any one or more of Examples 67-70 optionally include wherein forming the second metal layer includes sputter coating or spin coating one side of the passive layer.

In Example 72, the subject matter of any one or more of Examples 67-71 optionally include wherein forming the first die and the second die further comprises separating the material layer from a wafer.

In Example 73, the subject matter of any one or more of Examples 67-72 optionally include attaching a third die to the substrate and electrically coupling the third die to the first die.

In Example 74, the subject matter of any one or more of Examples 67-73 optionally include attaching a third die to the substrate and electrically coupling the third die to the second die.

In Example 75, the subject matter of any one or more of Examples 67-74 optionally include attaching a third die to the substrate and electrically coupling the third die to the first die and the second die.

In Example 76, the subject matter of any one or more of Examples 67-75 optionally include grinding the first metal layer or the second metal layer of the first die or the second die to increase surface roughness.