Offset trimming for differential amplifier

Apparatuses, systems, and methods are disclosed for offset trimming for differential amplifiers. An apparatus includes a differential amplifier. A differential amplifier includes a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider. A first variable current source is coupled to a non-inverting input, so that increasing a current from the first variable current source increases a voltage at the non-inverting input. A second variable current source is coupled to an inverting input, and to an output via a voltage divider, so that increasing a current from the second variable current source decreases a voltage at the output.

TECHNICAL FIELD

The present disclosure, in various embodiments, relates to differential amplifiers and more particularly relates to offset trimming for differential amplifiers.

BACKGROUND

Differential amplifiers, such as operational amplifiers, may be used for a variety of purposes. For example, certain types of non-volatile memory media may use differential amplifiers to produce word line voltages for reading or programming memory cells. In general, a differential amplifier may amplify a voltage difference between two inputs. However, an output from an amplifier may be offset from an expected or desired voltage for various reasons. For example, internal variations among amplifier components may result in an asymmetry between the two inputs, so that the output voltage is zero when a small but nonzero voltage difference exists at the inputs, rather than when the same voltage is applied to both inputs. Similarly, external or system offsets may cause an input voltage to be higher or lower than expected, causing a corresponding offset at an amplifier output.

SUMMARY

Apparatuses are presented for offset trimming for differential amplifiers. In one embodiment, an apparatus includes a differential amplifier. In a further embodiment, a differential amplifier includes a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider. In certain embodiments, a first variable current source is coupled to a non-inverting input. In further embodiments, increasing a current from a first variable current source increases a voltage at a non-inverting input. In various embodiments, a second variable current source is coupled to an inverting input, and to an output via a voltage divider. In further embodiments, increasing a current from a second variable current source decreases a voltage at an output.

Systems are presented for offset trimming for differential amplifiers. In one embodiment, a system includes one or more memory die. In a further embodiment, a memory die includes an array of non-volatile memory cells coupled to a plurality of word lines. In a certain embodiment, a memory die includes a plurality of differential amplifiers coupled to word lines to produce word line voltages. In a further embodiment, differential amplifiers include non-inverting inputs, inverting inputs, and outputs coupled to the inverting inputs via voltage dividers. In some embodiments, a plurality of first variable current sources are coupled to non-inverting inputs of differential amplifiers. In further embodiments, increasing a current from one of a plurality of first variable current sources increases a voltage at a corresponding non-inverting input. In various embodiments, a plurality of second variable current sources are coupled to inverting inputs of differential amplifiers, and to outputs via voltage dividers. In further embodiments, increasing a current from one of a plurality of second variable current sources decreases a voltage at a corresponding output.

An apparatus, in another embodiment, includes means for amplification of an input voltage to drive a word line voltage for a non-volatile memory array. In a certain embodiment, an apparatus includes means for providing a first current. In a further embodiment, a means for providing a first current may be coupled to a non-inverting input of a means for amplification, and coupled to ground via a load resistance, so that increasing the first current increases a word line voltage. In various embodiments, an apparatus includes means for providing a second current. In further embodiments, a means for providing a second current may be coupled to an inverting input of a means for amplification, coupled to an output of the means for amplification via a top resistor of a voltage divider, and coupled to ground via a bottom resistor of the voltage divider, so that increasing the second current decreases a word line voltage.

DETAILED DESCRIPTION

Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” “apparatus,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer readable storage media storing computer readable and/or executable program code.

Indeed, a module of executable code may include a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several memory devices, or the like. Where a module or portions of a module are implemented in software, the software portions may be stored on one or more computer readable and/or executable storage media. Any combination of one or more computer readable storage media may be utilized. A computer readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and/or executable storage medium may be any tangible and/or non-transitory medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

FIG. 1is a block diagram of one embodiment of a system100comprising word line drivers150for a non-volatile memory device120. The word line drivers150may be part of one or more non-volatile memory elements123or memory die, and may be in communication with one or more of a non-volatile memory media controller126, a non-volatile memory element123, a device driver, or the like. The word line drivers150may operate as part of a non-volatile memory system102of a computing device110, which may comprise a processor111, volatile memory112, and a communication interface113. The processor111may comprise one or more central processing units, one or more general-purpose processors, one or more application-specific processors, one or more virtual processors (e.g., the computing device110may be a virtual machine operating within a host), one or more processor cores, or the like. The communication interface113may comprise one or more network interfaces configured to communicatively couple the computing device110and/or non-volatile memory controller124to a communication network115, such as an Internet Protocol network, a Storage Area Network, or the like.

The non-volatile memory device120, in various embodiments, may be disposed in one or more different locations relative to the computing device110. In one embodiment, the non-volatile memory device120comprises one or more non-volatile memory elements123, such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, storage housings, and/or other mechanical and/or electrical support structures. For example, the non-volatile memory device120may comprise one or more direct inline memory module (DIMM) cards, one or more expansion cards and/or daughter cards, a solid-state-drive (SSD) or other hard drive device, and/or may have another memory and/or storage form factor. The non-volatile memory device120may be integrated with and/or mounted on a motherboard of the computing device110, installed in a port and/or slot of the computing device110, installed on a different computing device110and/or a dedicated storage appliance on the network115, in communication with the computing device110over an external bus (e.g., an external hard drive), or the like.

The non-volatile memory device120, in one embodiment, may be disposed on a memory bus of a processor111(e.g., on the same memory bus as the volatile memory112, on a different memory bus from the volatile memory112, in place of the volatile memory112, or the like). In a further embodiment, the non-volatile memory device120may be disposed on a peripheral bus of the computing device110, such as a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (SATA) bus, a parallel Advanced Technology Attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like. In another embodiment, the non-volatile memory device120may be disposed on a data network115, such as an Ethernet network, an Infiniband network, SCSI RDMA over a network115, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and/or wireless network115, or the like.

The computing device110may further comprise a non-transitory, computer readable storage medium114. The computer readable storage medium114may comprise executable instructions configured to cause the computing device110(e.g., processor111) to perform steps of one or more of the methods disclosed herein.

The non-volatile memory system102, in the depicted embodiment, includes one or more word line drivers150. A word line driver150, in one embodiment, is configured to apply a voltage to a word line of a non-volatile memory array. In certain embodiments, a word line driver150may include a differential amplifier that produces a word line voltage, a first variable current source capable of increasing an input voltage of the differential amplifier for trimming a negative voltage offset, and a second variable current source capable of decreasing an output voltage of the differential amplifier for trimming a positive voltage offset.

In general, in various embodiments, an amplifier offset may refer to a difference between an expected and an actual output voltage. In various embodiments, trimming an offset may refer to various types of adjustments to reduce or correct an output offset. Certain methods of amplifier offset trimming may rely on voltages well above ground voltage (0 V) at both inputs, and may be less effective with inputs near zero volts. Dynamic offset cancellation, such as in auto-zero or chopper-stabilized amplifiers, may introduce delays and residual or clock noise. Additionally, adding a clock for dynamic cancellation may increase design complexity and/or silicon area for an amplifier. By contrast, in certain embodiments, using two variable current sources for offset trimming may allow correction of positive and negative offsets, even when input voltages are near zero, while avoiding the added time, noise, or complexity associated with dynamic offset cancellation. The word line drivers150are described in greater detail below with regard toFIGS. 2-8.

In one embodiment, the word line drivers150may be controlled by logic hardware of one or more non-volatile memory devices120, such as a non-volatile memory media controller126, a non-volatile memory element123, a device controller, a field-programmable gate array (FPGA) or other programmable logic, firmware for an FPGA or other programmable logic, microcode for execution on a microcontroller, an application-specific integrated circuit (ASIC), or the like. In another embodiment, the word line drivers150may be controlled by executable software code, such as a device driver or the like, stored on the computer readable storage medium114for execution on the processor111. In a further embodiment, the word line drivers150may be controlled by a combination of both executable software code and logic hardware.

In one embodiment, the non-volatile memory device120is configured to receive requests from a device driver or other executable application via a bus125or the like. The non-volatile memory device120may be further configured to communicate with a device driver or other application via the bus125. Accordingly, the non-volatile memory device120, in some embodiments, may comprise and/or be in communication with one or more direct memory access (DMA) modules, remote DMA modules, bus controllers, bridges, buffers, and so on to facilitate communication of data. In another embodiment, the non-volatile memory device120may receive requests as an API call from a storage client116, as an IO-CTL command, or the like.

According to various embodiments, a non-volatile memory controller126may manage one or more non-volatile memory devices120and/or non-volatile memory elements123. The non-volatile memory device(s)120may comprise recording, memory, and/or storage devices, such as solid-state storage device(s) and/or semiconductor storage device(s) that are arranged and/or partitioned into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any quantity of physical storage media on a non-volatile memory device120). Memory units may include, but are not limited to: pages, memory divisions, blocks, sectors, collections or sets of physical storage locations (e.g., logical pages, logical blocks), or the like.

A device driver and/or the non-volatile memory media controller126, in certain embodiments, may present a logical address space134to the storage clients116. As used herein, a logical address space134refers to a logical representation of memory resources. The logical address space134may comprise a plurality (e.g., range) of logical addresses. As used herein, a logical address refers to any identifier for referencing a memory resource (e.g., data), including, but not limited to: a logical block address (LBA), cylinder/head/sector (CHS) address, a file name, an object identifier, an inode, a Universally Unique Identifier (UUID), a Globally Unique Identifier (GUID), a hash code, a signature, an index entry, a range, an extent, or the like.

A device driver for the non-volatile memory device120may maintain metadata135, such as a logical to physical address mapping structure, to map logical addresses of the logical address space134to media storage locations on the non-volatile memory device(s)120. A device driver may be configured to provide storage services to one or more storage clients116. The storage clients116may include local storage clients116operating on the computing device110and/or remote, storage clients116accessible via the network115and/or network interface113. The storage clients116may include, but are not limited to: operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

A device driver may be communicatively coupled to one or more non-volatile memory devices120. The one or more non-volatile memory devices120may include different types of non-volatile memory devices including, but not limited to: solid-state storage devices, semiconductor storage devices, SAN storage resources, or the like. The one or more non-volatile memory devices120may comprise one or more respective non-volatile memory media controllers126and non-volatile memory media122. A device driver may provide access to the one or more non-volatile memory devices120via a traditional block I/O interface131. Additionally, a device driver may provide access to enhanced functionality through the SCM interface132. The metadata135may be used to manage and/or track data operations performed through any of the Block I/O interface131, SCM interface132, cache interface133, or other, related interfaces.

The cache interface133may expose cache-specific features accessible via a device driver for the non-volatile memory device120. Also, in some embodiments, the SCM interface132presented to the storage clients116provides access to data transformations implemented by the one or more non-volatile memory devices120and/or the one or more non-volatile memory media controllers126.

A device driver may present a logical address space134to the storage clients116through one or more interfaces. As discussed above, the logical address space134may comprise a plurality of logical addresses, each corresponding to respective media locations the on one or more non-volatile memory devices120. A device driver may maintain metadata135comprising any-to-any mappings between logical addresses and media locations, or the like.

A device driver may further comprise and/or be in communication with a non-volatile memory device interface139configured to transfer data, commands, and/or queries to the one or more non-volatile memory devices120over a bus125, which may include, but is not limited to: a memory bus of a processor111, a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a small computer system interface (SCSI), FireWire, Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network115, Infiniband, SCSI RDMA, or the like. The non-volatile memory device interface139may communicate with the one or more non-volatile memory devices120using input-output control (IO-CTL) command(s), IO-CTL command extension(s), remote direct memory access, or the like.

The communication interface113may comprise one or more network interfaces configured to communicatively couple the computing device110and/or the non-volatile memory controller126to a network115and/or to one or more remote, network-accessible storage clients116. The storage clients116may include local storage clients116operating on the computing device110and/or remote, storage clients116accessible via the network115and/or the network interface113. The non-volatile memory controller126is part of and/or in communication with one or more non-volatile memory devices120. AlthoughFIG. 1depicts a single non-volatile memory device120, the disclosure is not limited in this regard and could be adapted to incorporate any number of non-volatile memory devices120.

While legacy technologies such as NAND flash may be block and/or page addressable, storage class memory, in one embodiment, is byte addressable. In further embodiments, storage class memory may be faster and/or have a longer life (e.g., endurance) than NAND flash; may have a lower cost, use less power, and/or have a higher storage density than DRAM; or offer one or more other benefits or improvements when compared to other technologies. For example, storage class memory may comprise one or more non-volatile memory elements123of ReRAM, Memristor memory, programmable metallization cell memory, phase-change memory, nano RAM, nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, and/or variations thereof.

While the non-volatile memory media122is referred to herein as “memory media,” in various embodiments, the non-volatile memory media122may more generally comprise a non-volatile recording media capable of recording data, which may be referred to as a non-volatile memory media, a non-volatile storage media, or the like. Further, the non-volatile memory device120, in various embodiments, may comprise a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like.

The non-volatile memory media122may comprise one or more non-volatile memory elements123, which may include, but are not limited to: chips, packages, planes, die, expansion cards, or the like. A non-volatile memory media controller126may be configured to manage data operations on the non-volatile memory media122, and may comprise one or more processors, programmable processors (e.g., FPGAs), ASICs, micro-controllers, or the like. In some embodiments, the non-volatile memory media controller126is configured to store data on and/or read data from the non-volatile memory media122, to transfer data to/from the non-volatile memory device120, and so on.

The non-volatile memory media controller126may be communicatively coupled to the non-volatile memory media122by way of a bus127. The bus127may comprise an I/O bus for communicating data to/from the non-volatile memory elements123. The bus127may further comprise a control bus for communicating addressing and other command and control information to the non-volatile memory elements123. In some embodiments, the bus127may communicatively couple the non-volatile memory elements123to the non-volatile memory media controller126in parallel. This parallel access may allow the non-volatile memory elements123to be managed as a group, forming a logical memory element129. The logical memory element may be partitioned into respective logical memory units (e.g., logical pages) and/or logical memory divisions (e.g., logical blocks). The logical memory units may be formed by logically combining physical memory units of each of the non-volatile memory elements.

The non-volatile memory controller126may comprise and/or be in communication with a device driver executing on the computing device110. A device driver may provide storage services to the storage clients116via one or more interfaces131,132, and/or133. In some embodiments, a device driver provides a block-device I/O interface131through which storage clients116perform block-level I/O operations. Alternatively, or in addition, a device driver may provide a storage class memory (SCM) interface132, which may provide other storage services to the storage clients116. In some embodiments, the SCM interface132may comprise extensions to the block device interface131(e.g., storage clients116may access the SCM interface132through extensions or additions to the block device interface131). Alternatively, or in addition, the SCM interface132may be provided as a separate API, service, and/or library. A device driver may be further configured to provide a cache interface133for caching data using the non-volatile memory system102.

A device driver may further comprise a non-volatile memory device interface139that is configured to transfer data, commands, and/or queries to the non-volatile memory media controller126over a bus125, as described above.

FIG. 2illustrates an embodiment of a non-volatile storage device210that may include one or more memory die or chips212. The non-volatile storage device210may be substantially similar to the non-volatile memory device120described with reference toFIG. 1. Memory die212, in some embodiments, includes an array (two-dimensional or three dimensional) of memory cells200, die controller220, and read/write circuits230A/230B. In one embodiment, access to the memory array200by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array, so that the densities of access lines and circuitry on each side are reduced by half. The read/write circuits230A/230B, in a further embodiment, include multiple sense blocks250which allow a page of memory cells to be read or programmed in parallel.

The memory array200, in various embodiments, is addressable by word lines via row decoders240A/240B and by bit lines via column decoders242A/242B. In some embodiments, a controller244is included in the same memory device210(e.g., a removable storage card or package) as the one or more memory die212. Commands and data are transferred between the host and controller244via lines232and between the controller and the one or more memory die212via lines234. One implementation can include multiple chips212.

Die controller220, in one embodiment, cooperates with the read/write circuits230A/230B to perform memory operations on the memory array200. The die controller220, in certain embodiments, includes a state machine222, an on-chip address decoder224, and a power control circuit226.

The state machine222, in one embodiment, provides chip-level control of memory operations. The on-chip address decoder224provides an address interface to convert between the address that is used by the host or a memory controller to the hardware address used by the decoders240A,240B,242A,242B. The power control circuit226controls the power and voltages supplied to the word lines and bit lines during memory operations. In one embodiment, power control circuit226includes one or more charge pumps that can create voltages larger than the supply voltage. The word line drivers150A,150B, which may be substantially similar to the word line drivers150described above with regard toFIG. 1, may produce, provide, control, and or drive word line voltages to word lines based on decoding of addresses by row decoders240A,240B.

FIG. 3depicts one embodiment of an apparatus300for accessing non-volatile memory. In the depicted embodiment, the apparatus300includes a bit line302, one or more NAND strings304, a sense amplifier306, word lines312, word line drivers150, and a source line316. The word line drivers150may be substantially similar to the word line drivers150described above with regard toFIGS. 1 and 2. The sense amplifier306may be part of a sense block250and the NAND strings may be part of a memory array200, as described above with regard toFIG. 2.

In the depicted embodiment, a NAND string304includes a plurality of floating gate transistors310. In a floating gate transistor310, a conductive “floating” gate is positioned over a channel region of a semiconductor substrate, between source and drain regions. A control gate is positioned over the floating gate. The floating gate is electrically isolated (e.g., by oxide layers) from the control gate and the substrate, and may store a charge. The charge on a floating gate may be increased (e.g., during programming) or decreased (e.g., during erasure) by Fowler-Nordheim tunneling, hot carrier injection, or the like. Because the floating gate is between the control gate and the substrate, the amount of charge on the floating gate may affect the “threshold voltage” Vtthat is sufficient to turn the floating gate transistor310“on” (e.g., to create a conductive channel between source and drain regions) when applied to the control gate. Thus, the amount of charge on the floating gate, or, equivalently, the threshold voltage Vtfor the floating gate transistor310may be manipulated to store data.

In one embodiment, in “single level cell” (SLC) NAND flash memory, a single read voltage threshold may be established for a floating gate transistor310, so that the floating gate transistor310is in an erased state (e.g., storing a binary “1”) if the threshold voltage Vtfor the cell is below the read voltage threshold, and in a programmed state (e.g., storing a binary “0”) if the threshold voltage Vtfor the cell is above the read voltage threshold. In another embodiment, for “multi level cell” (MLC), “triple level cell” (TLC) NAND flash memory, or the like, a range of possible threshold voltages Vtfor a floating gate transistor310may be divided into multiple states, so that the floating gate transistor310stores more than one bit of data. In general, in various embodiments, reading data from a floating gate transistor310may include determining which state the threshold voltage Vtof the floating gate transistor310is in, by applying a read voltage to the control gate and determining whether the floating gate transistor310conducts between source and drain terminals. Similarly, writing data to a floating gate transistor310may include applying program voltage pulses to the control gate, or applying erase voltage pulses to the substrate, to change the threshold voltage Vtof the floating gate transistor310. A word line driver150may apply a read voltage, a program voltage pulse, or the like, to a control gate of a floating gate transistor310.

Although data is stored in floating gate transistors310in the depicted embodiment, data in another embodiment may be stored by varying certain physical properties of other types of electrical components. For example, data may be stored by varying the resistance of a component in ReRAM, the phase of a component in PCM, or the like. A component, such as a floating gate transistor310, with a physical property that may be altered to store data may be referred to herein as a “storage cell,” a “memory cell” or the like. Thus, in the depicted embodiment, the memory array200ofFIG. 2may include multiple storage cells, comprising floating gate transistors310in NAND strings304. In another embodiment, however, the memory array200ofFIG. 2may include multiple storage cells of another type.

In the depicted embodiment, a NAND string304includes a series of floating gate transistors310, daisy chained source-to-drain. A source select transistor314couples the source end of the NAND string304to a source line316, and a drain select transistor308couples the drain end of the NAND string304to a bit line302. In a certain embodiment, the source line316may be maintained at a source voltage VSS(e.g., 0 V, or ground), and the bit line302voltage may be manipulated by the sense amplifier306to read or write data. Word lines312may couple control gates of corresponding floating gate transistors310across multiple NAND strings304. Thus, a full row of floating gate transistors310(e.g., a page of data for SLC NAND, or multiple pages of data for MLC or TLC NAND) may be addressed via a single word line312, with individual bits read or programmed via columns or bit lines302. In the depicted embodiment, a 3-dimensional NAND arrangement is shown, in which multiple NAND strings304are coupled to one bit line302, and a bit stored by a floating gate transistor310is physically addressed by row (e.g., word line312), column (e.g., bit line302), and string304, (e.g., selected via select transistors308,314). In another embodiment, in a 2-dimensional NAND arrangement, each NAND string304is coupled to a single bit line302, and a bit stored by a floating gate transistor310is physically addressed by row (e.g., word line312), and column (e.g., bit line302), without separately addressing a string304.

In the depicted embodiment, as described above, reading data from a floating gate transistor310may include applying a read voltage to the control gate of the floating gate transistor310and determining whether the floating gate transistor310conducts between source and drain terminals. When reading or writing data for a floating gate transistor310, the term “selected” may be used herein to refer to the floating gate transistor310in question, the NAND string304that includes the selected floating gate transistor310, the word line312coupled to the selected floating gate transistor310, and the like. Conversely, the term “unselected” may be used herein to refer to floating gate transistors310other than the selected floating gate transistor310, NAND strings304other than the selected NAND string304, word lines312other than the selected word line312, and the like.

In one embodiment, to read data from a selected floating gate transistor310, the sense amplifier306precharges the selected bit line302. The source select transistor314and the drain select transistor308for a selected string304may be turned on (e.g., a voltage may be applied to control gates so that the select transistors308,314are in a conducting state). Select transistors308,314for unselected strings304may be turned off (e.g., control gates may be at 0 V). A voltage sufficient to fully turn on the unselected floating gate transistors310is applied by word line drivers150for the unselected word lines312. A read voltage is applied to the selected floating gate transistor310by a word line driver150, via the selected word line312. If the threshold voltage Vtfor the selected floating gate transistor310is below the applied read voltage (e.g., the storage cell is in an erased state for SLC NAND), then the selected floating gate transistor310conducts, and the bit line302is discharged via the selected NAND string304coupling the bit line302to the source line316. Conversely, if the voltage threshold Vtfor the selected floating gate transistor310is above the applied read voltage (e.g., the storage cell is in a programmed state for SLC NAND), then the selected floating gate transistor310does not conduct, and the selected NAND string304does not discharge the bit line302. The sense amplifier306may sense an electrical property of the bit line302, such as a bit line voltage, a rate of change in a bit line voltage, a bit line current, or the like, to determine whether the bit line302discharges through the selected floating gate transistor310.

Applying a single read voltage may be sufficient to distinguish between programmed and erased states for SLC NAND; successive read voltages may be applied to distinguish between multiple states for MLC NAND, TLC NAND, or the like. As the number of states per cell increases, the number of read voltages that are applied to distinguish between the states may similarly increase. In one embodiment, a word line driver150may apply a series of fixed read voltages to floating gate transistors310on a selected word line312, and sense amplifiers306may sense electrical properties of bit lines302coupled to the floating gate transistors310to determine which storage cells are in which states. However, the time for sensing at each read voltage may increase the latency of a read operation. Thus, in another embodiment, a word line driver150may apply a ramping voltage (e.g., a voltage signal that increases linearly from 0 V to 12 V, or the like) to floating gate transistors310on a selected word line312, and sense amplifiers306may determine when (or at what voltage) the corresponding bit lines302discharge. In certain embodiment, sensing bit line302properties while applying a ramping voltage signal to a word line312may determine the state of multiple cells, and may avoid increased latency that would be associated with performing a separate sense operation at multiple read voltages.

In a certain embodiment, for writing as for reading, a string304may be selected by applying appropriate voltages to select transistors308,314, and unselected floating gate transistors310may be fully turned on by applying a sufficient voltage to unselected word lines312. One or more program voltage pulses may be applied to the control gate for the selected floating gate transistor310, via the selected word line312, to change the voltage threshold Vtfor the selected floating gate transistor310. Changes to the voltage threshold Vtfor the selected floating gate transistor310may be verified in a process similar to reading, by applying one or more program verify voltages (or a ramping program verify voltage signal) to the selected floating gate transistor310, and sensing whether (or when) the selected floating gate transistor310conducts.

In various embodiments, the degree to which a voltage threshold Vtfor a selected floating gate transistor310changes in response to a programming pulse depends on the size of voltage between the control gate and the drain. In one embodiment, to inhibit a cell from being programmed, a sense amplifier306may apply a high inhibit voltage to the drain of the selected floating gate transistor310, via the bit line302. In another embodiment, for fast programming, or for programming to a high voltage threshold Vt, a sense amplifier306may apply a low or zero voltage to the drain of the selected floating gate transistor310, via the bit line302. In certain embodiments, a sense amplifier306may apply a bias voltage to the drain of the selected floating gate transistor310, via the bit line302. In some embodiments, a small, but non-zero bias voltage may reduce program disturb phenomena that affect floating gate transistors310in nearby or adjacent unselected NAND strings304. In further embodiments, a bias voltage at some level between zero volts and the inhibit voltage may effectively reduce the size of the program voltage pulses, by reducing the voltage difference between the control gate and the drain of the selected floating gate transistor310, to slow programming, or to program the selected floating gate transistor310into a state with an intermediate threshold voltage Vt.

Read and program operations are described above in the context of reading or writing data to a single floating gate transistor310. However, in various embodiments, a word line312may couple control gates for a row of floating gate transistors310that spans multiple NAND strings304and bit lines302. Thus, a read voltage or a program voltage pulse may be applied to a word line312, and multiple bits of data may be communicated via multiple bit lines302, to read data from or write data to floating gate transistors310coupled to the selected word line312. In some embodiments, a subset of floating gate transistors310coupled to the selected word line312may be unselected. For example, in one embodiment, strings304may still be individually selected as described above if multiple strings304are coupled to one bit line302. In certain embodiments, a partial row may be programmed by selecting only even bit lines302, only odd bit lines302, or the like. However, in general, in various embodiments, data is programmed to or read from multiple floating gate transistors310in a row using one word line312and multiple bit lines302.

To read a page of data, a read voltage may be applied to a word line312, and sense amplifiers306may determine which bit lines302are discharged through floating gate transistors310coupled to the word line312. In certain embodiment, where the range of possible threshold voltages Vtfor a floating gate transistor310is divided into more than two states, multiple pages of data may be read from the same row of floating gate transistors310by applying successive read voltages or a ramping read voltage signal to the word line312.

Similarly, to program a page of data, one or more program pulses may be applied to a word line312and sense amplifiers306may apply different voltages to different bit lines302to program or inhibit floating gate transistors310coupled to the word line312. In one embodiment, multiple pages of data may be programmed to the same row of floating gate transistors310by applying inhibit voltages to different bit lines302at different times, or by applying different bias voltages to different bit lines302to affect programming speeds, so that different floating gate transistors310are programmed into different states.

In the depicted embodiment, the floating gate transistors310are NAND flash storage cells. However, in various embodiments, word lines312and bit lines302for other types of storage cells including resistive storage cells, magnetic storage cells, phase change storage cells, or the like, may be similarly arranged so that so that word line drivers150apply voltages (or other electrical signals) to rows of non-volatile storage cells. Word line drivers150are described in further detail below with regard toFIGS. 4-8.

FIG. 4depicts one embodiment of a word line driver150. The word line driver150may be substantially similar to the word line drivers150described above with regard toFIGS. 1-3. In the depicted embodiment, the word line driver150includes a variable voltage source402and an amplification component406. In general, as described above, the word line driver150is coupled to a word line312(which may be substantially similar to the word lines312described above with regard toFIG. 3) to produce a word line voltage. As used herein, a “word line voltage” may refer to any voltage signal applied to a word line312, such as a fixed read voltage, a ramping read voltage, a program voltage pulse, a program verify voltage, a program verify voltage ramp, or the like.

In general, in various embodiments, the variable voltage source402produces a reference voltage404, and the amplification component406amplifies the reference voltage404and applies the amplified voltage to the word line312. In various embodiments, a variable voltage source402may include any electrical component capable of being controlled to output a variable voltage, such as a voltage based digital-to-analog converter (“DAC”) which controls an analog voltage output based on a digital input, a potentiometer configured as a voltage divider, a controllable voltage regulator, or the like. Many types of components that output a variable voltage will be clear in view of this disclosure.

In the depicted embodiment, the output of the variable voltage source402is a reference voltage VREF404, which is received and amplified by the amplification component406. In one embodiment, VREF404may be a (piecewise) flat or constant voltage signal, which is amplified by the amplification component406to produce a fixed word line voltage (e.g., a read voltage). In a further embodiment, the variable voltage source402may be controlled to change the reference voltage VREF404, so that multiple read voltages may be produced by the word line driver150. In another embodiment, the variable voltage source402may be configured to produce a ramping voltage signal as the reference voltage VREF404, so that the word line driver150produces a ramping word line voltage.

In various embodiments, the amplification component406may include one or more electrical components configured to amplify the reference voltage VREF404. For example, the amplification component406may include a differential amplifier, an operational amplifier (“op amp”), an instrumentation amplifier, or the like. Various electrical components suitable for amplifying a reference voltage VREF404will be clear in view of this disclosure. One embodiment of an amplification component406is described in further detail below with regard toFIG. 7.

FIG. 5andFIG. 6are graphs500,600illustrating the output voltages from the variable voltage source402and the amplification component406ofFIG. 4, respectively. InFIG. 5, graph500depicts one embodiment of a reference voltage VREF404produced by the variable voltage source402. In the depicted embodiment, the reference voltage VREF404is a ramping voltage signal that ramps linearly from 0 V to 1.5 V. In various embodiments, a “ramping” voltage signal may refer to any voltage signal that increases or decreases from an initial voltage to a final voltage. For example, in one embodiment, a ramping voltage signal may increase linearly. In another embodiment, a ramping voltage signal may increase logarithmically. In a certain embodiment, a ramping voltage signal produced by a DAC may increase in piecewise constant steps as a digital input to the DAC increases. (In a further embodiment, a low-pass filter may smooth a voltage signal produced by a DAC to avoid high harmonics, or to produce a more approximately linear signal). In certain embodiments, a ramping voltage signal may decrease, rather than increasing. Various types of ramping voltage signals will be clear in view of this disclosure.

InFIG. 6, graph600depicts various embodiments of an output voltage602produced by the amplification component406, corresponding to the reference voltage VREF404inFIG. 5. In the depicted embodiment, output voltage602brepresents the output of an amplification component406without positive or negative offset. In the depicted embodiment, the amplification component406has a gain of 8, so the reference voltage VREF404that ramps from 0 V to 1.5 V is amplified to become an output voltage that ramps from 0 V to 12 V. In another embodiment, the gain of the amplification component406may be higher or lower than in the depicted embodiment. The output voltage602bis applied to the word line312. As described above with regard toFIG. 3, applying a ramping voltage signal to a word line312allows the state of cells coupled to the word line to be determined, for reading data. For example, for NAND memory cells where data is stored by manipulating the threshold voltage Vtof floating gate transistors, the threshold voltages Vtfor a row of memory cells may be determined by applying a ramping voltage signal to control gates of the floating gate transistors via a word line312, and determining when (or at what voltage) each floating gate transistor conducts (e.g., by sensing when corresponding bit lines are discharged). States of certain other types of memory cells may similarly be sensed by applying a ramping voltage signal to a word line312.

In a certain embodiment, the range of possible threshold voltages Vtfor NAND memory cells (or of another data-encoding physical property for another type of memory cell) may be divided into a number of states, corresponding to the number of bits stored by the cell. For example, for storing four bits per cell, a range of threshold voltages Vtmay be divided into sixteen states, so that each state corresponds to one of the sixteen possible binary values from 0000 to 1111. In a further embodiment, applying a ramping word line voltage to determine the threshold voltage Vtof a cell may be significantly faster than performing fifteen individual sense operations for fifteen different read voltages (at boundary voltages between states) to determine the state of the cell.

In certain embodiments, increasing the number of states per cell, to store more data, may decrease the size of the states. For example, if a NAND memory cell may have a threshold voltage Vtsomewhere between 0 V and 12 V, then dividing the range of possible threshold voltage Vtinto sixteen states to store four bits per cell results in states that are 0.75 V wide. With each state occupying a narrow voltage range, a small error in the applied read voltage may result in misidentifying the state of a cell, causing data errors.

In the graph600, output voltage602arepresents the output of an amplification component406with positive offset. Similarly, output voltage602crepresents the output of an amplification component406with negative offset. In general, in various embodiments, an amplifier offset may refer to a difference between an expected and an actual output voltage. The offset may refer to an actual voltage difference at an output, or may be “input referred” to refer to the size of a voltage change at an amplifier input that would compensate for the difference at the output. (Input referred offsets may be particularly useful for describing offsets caused by asymmetries between differential inputs). Various polarity conventions exist for referring to offsets. For example, the offset of one amplifier may be described as an input-referred offset in two different ways, with opposite polarities, to describe a compensating voltage change at an inverting input or a non-inverting input of the amplifier. As used herein, a “positive” offset refers to an offset where the output voltage of an amplifier is higher than an expected, desired, or target voltage, and a “negative” offset refers to an offset where the output voltage of an amplifier is lower than an expected, desired, or target voltage. However, the convention used herein for describing the polarity of an offset is for convenience in description, and is not intended as limiting.

In various embodiments, an offset may be caused by various factors internal or external to an amplification component604. For example, the positive offset of output voltage602aor the negative offset of output voltage602cmay be caused by internal asymmetries of the amplification component604. Alternatively, the positive offset of output voltage602aor the negative offset of output voltage602cmay be caused by external or system factors. For example, the reference voltage VREF404produced by the variable voltage source402may actually be higher or lower than depicted in the graph500ofFIG. 5.

In either case, applying an output voltage602from an amplifier component406to a word line may lead to errors in sensing the state of a cell (either for reading data or for verifying that a cell has been programmed to the right state) if the output voltage602is offset from an expected or target voltage. For example, in the graph600, the expected or target output voltage602bis represented by a solid line. The target output voltage602bmay be “expected” in the sense that it is the specified output of the amplification component406. In a further embodiment, other components may rely on the specified, target, or expected output of the amplification component406. For example, determining the threshold voltage Vtfor a non-volatile memory cell may involve identifying the specified output voltage602bfrom the amplification component406at a time when a bit line is discharged through the non-volatile memory cell. If the actual output voltage602is higher or lower than the specified output voltage602b, the state of the cell may be misidentified.

In certain embodiments, it may be difficult to detect or compensate for an amplifier offset at certain voltages. For example, an amplifier may be in a saturated state (e.g., at a maximum or minimum output voltage) with a 0 V input, due to a high gain applied to even a very small input-referred offset. The saturated output may indicate the polarity of the input-referred offset, but not the size of the input-referred offset. Certain types of amplifiers, such as complementary metal-oxide-semiconductor (“CMOS”) amplifiers, may produce output voltages with a maximum output voltage at or near a positive supply voltage, and a minimum output voltage at or near 0 V. In further embodiments, it may be difficult to determine whether a 0 V output voltage is due to a 0 V input, or whether an amplifier is in a saturated state at 0 V caused by a negative offset. For example, in the depicted embodiment in graph600, the output of the amplification component406is clamped at a 0 V minimum voltage, so the output voltage602cwith a negative offset remains at zero volts until the reference voltage VREF404is high enough to produce a positive output voltage602cdespite the negative offset. Trimming output offsets (e.g., output voltages602a,602c) for an amplification component406is described in further detail below with regard toFIGS. 7-9.

FIG. 7depicts one embodiment of an amplification component406. The amplification component406may be substantially similar to the amplification component406described above with regard toFIGS. 4-6. In general, as described above, the amplification component amplifies a reference voltage VREF404(e.g., from variable voltage source402), and applies the amplified reference voltage to a word line312. In the depicted embodiment, the amplification component406include a differential amplifier712, a first variable current source704, and a second variable current source726.

The differential amplifier712, in one embodiment, comprises a non-inverting input708, an inverting input710, and an output716. In general, in various embodiments, a differential amplifier712amplifies a voltage difference between the non-inverting input708and the inverting input710. Thus, in certain embodiments, a “non-inverting” input708may refer to an input of a differential amplifier712where increasing the voltage at the non-inverting input708increases the voltage at the output716(if the output voltage is not already at a maximum). Similarly, in further embodiments, an “inverting” input710may refer to an input of a differential amplifier712where increasing the voltage at the inverting input710decreases the voltage at the output716(if the output voltage is not already at a minimum). In certain embodiments, a differential amplifier712may be a fully differential amplifier (with differential outputs), an operational amplifier (with high gain and a single-ended output716), another type of electronic amplifier, or the like. In the depicted embodiment, the differential amplifier712is an operational amplifier (“op amp”). Various other or further types of differential amplifiers712suitable for use in an amplification component406will be clear in view of this disclosure.

In general, for an ideal differential amplifier712, the voltage at the output716is equal to an open-loop gain for the amplifier712, multiplied by the differential input voltage (e.g., the voltage at the non-inverting input708minus the voltage at the inverting input710). In certain embodiments, the voltage at the output716may be limited to maximum and minimum values, at which points the output716or the amplifier712may be referred to as “saturated.” Certain types of differential amplifiers712may be saturated at maximum and minimum voltages at or near high and low supply voltages. In the depicted embodiment, the amplifier712is coupled to a positive supply voltage Vs714, and to ground (defined to be 0 V). In a further embodiment, the output716may be saturated at a maximum voltage at or near the positive supply voltage Vs714, or at a minimum voltage at or near 0 V. In one embodiment, the amplifier712may be a complementary metal-oxide-semiconductor (“CMOS”) amplifier with a minimum output voltage of zero volts. In another embodiment, the amplifier712may be another type of amplifier with a positive maximum output voltage and a negative minimum output voltage. In certain embodiments, the open-loop gain of an amplifier712may be very large, so that even a small differential input voltage saturates the output716.

In general, for an ideal amplifier712, the voltage at the output716would be zero volts when the voltage at the non-inverting input708is equal to the voltage at the inverting input710. However, imperfections in the manufacturing or packaging processes may result in asymmetries between the non-inverting input708and the inverting input710, so that the voltage at the output716is nonzero (or saturated at a minimum voltage of zero volts) when the voltages at the inputs708,710match (e.g., the differential input voltage is zero). If the amplifier712has a large open-loop gain, the output716may even be saturated at a maximum or minimum output voltage when the voltages at the inputs708,710match. An amplifier712with an output offset caused by internal asymmetry may be modeled as an ideal amplifier with a small voltage source VOSin series with one of the inputs708,710, so that the output voltage is zero when the differential input voltage is VOS, rather than when the differential input voltage is zero. VOSmay be referred to as an “input referred” offset voltage for the amplifier, because it indicates an input voltage that compensates for an offset at the output716.

In a further embodiment, an output offset caused by factors external to the amplifier712may similarly be modeled as a small voltage source in series with one of the inputs708,710. For example, in the current embodiment, because the input voltage VREF404is coupled to the non-inverting input708, an error in the input voltage VREF404may be modeled as a small voltage source in series with the non-inverting input708.

In certain embodiments, the output716of a differential amplifier712may be directly or indirectly coupled to the inverting input710, to provide negative feedback. In a further embodiment, with the inverting input710controlled by the output716, the voltages at the output716and at the inverting input710may both be based on the voltage at the non-inverting input708. In particular, if the voltage at the non-inverting input708is fixed (e.g., at VREF404) and the output716is not saturated, then a stable equilibrium exists where the voltage at the output716pulls the voltage at the inverting input710to a point where the differential input voltage is consistent with the output voltage. In certain embodiments, where an amplifier712has a very large open-loop gain, any voltage at a non-saturated output716may indicate that the differential input voltage is very small, and the voltage at the inverting input710is approximately equal to the voltage at the non-inverting input708(plus or minus any internal input-referred offset voltage VOS).

In the depicted embodiment, the output716is coupled to the inverting input710via a voltage divider718. In general, in various embodiments, a voltage divider718may include any passive circuit that produces an output voltage at a fraction of an input voltage. In further embodiments, a voltage divider718may include two impedances in series, where an input voltage is applied across both impedances, and the output is the voltage across one of the impedances. In the depicted embodiment, where the amplifier712provides a DC voltage to a word line312, the voltage divider718comprises two resistors720,722. In another embodiment, where an amplifier712provides an oscillating voltage (e.g., to drive a load other than a word line312), impedances of a voltage divider718may include resistors capacitors, inductors, or the like.

In the depicted embodiment, the voltage divider718includes a top resistor720, with a resistance RTOP, coupled in series to a bottom resistor722, with resistance RBOT. Terms such as “top,” “bottom,” and “middle” are used herein for convenience in referring to a voltage divider718, without implying an actual spatial orientation. For example, the top resistor720may still be referred to as a “top” resistor even if the amplification component406(including the voltage divider718) is turned upside down. As used herein, the “bottom” of a voltage divider718is coupled directly to ground (or another reference voltage), the “middle” is coupled to the bottom via the bottom resistor722, and the “top” is coupled to the middle via the top resistor720. Thus, the voltage difference between the top and the bottom of the voltage divider718is the sum of the voltage differences across the top resistor720and the bottom resistor722, and the voltage difference between the middle and the bottom of the voltage divider718is the voltage across the bottom resistor722alone.

In the depicted embodiment, the top of the voltage divider718is coupled to the output716of the amplifier712, and the middle of the voltage divider718is coupled to the inverting input710of the amplifier712. As described above, the feedback from the output716to the inverting input710(via the voltage divider718) may bring the voltage at the inverting input710very close to the input voltage VREF404at the non-inverting input708(plus or minus an internal input-referred offset voltage VOS). Thus, the current through the bottom resistor722is approximately VREF/RBOT. In various embodiments, input impedance of the amplifier712at the inverting input710may be high, so that the current through the inverting input710is approximately zero. Thus, in a further embodiment, in the absence of current from the second variable current source726(e.g., without offset trimming), the current through the bottom resistor722may equal the current through the top resistor720, so that the voltage drop across the top resistor720is VREF*RTOP/RBOT, and the voltage at the top of the voltage divider718(e.g., the output voltage of the amplifier712) is VREF*(1+RTOP/RBOT). Thus, in the depicted embodiment, without offset trimming, the closed-loop gain of the amplifier712is (1+RTOP/RBOT). The top resistor720and the bottom resistor722may be selected by a manufacturer of the amplification component so that the individual resistances RTOPand RBOTare significantly less than the input impedance of the amplifier712at the inverting input710, and so that the ratio of resistances provides the desired closed-loop gain.

However, in certain embodiments, the voltage at the output716of the amplifier712may be higher or lower than a target voltage. For example, the voltage at the inverting input710may be higher or lower than the input voltage VREF404at the non-inverting input708by an input offset voltage VOS, causing the voltage at the output716to be correspondingly higher or lower. Similarly, system offsets may be caused by VREF404being higher or lower than a target input voltage for the target output voltage, by imprecise resistances for the top resistor720or the bottom resistor722, or the like. In certain embodiments, an offset may exist without affecting the output voltage at a particular input voltage. For example, if the minimum output voltage is zero and the input voltage VREF404is zero, a negative offset may not decrease the output voltage any further, but may become apparent if the minimum output voltage is still zero when the input voltage VREF404is small but positive.

In general, in various embodiments, the first variable current source704, with current INOS, is configured to compensate for a negative offset (e.g., an output voltage lower than expected). In certain embodiments, increasing the current INOSfrom the first variable current source704increases a voltage at the non-inverting input708of the amplifier712. For example, in the depicted embodiment, the first variable current source704is coupled directly to the non-inverting input708, and indirectly to ground via a load resistance RLOAD. InFIG. 7, the load resistance RLOADis depicted as a discrete resistor706within the amplification component. However, in various embodiments, the load resistance RLOADmay be an effective, equivalent, or resultant resistance for a current path between the non-inverting input708and another circuit node internal or external to the amplification component406. For example, in one embodiment, the load resistance RLOADmay comprise an output impedance of the variable voltage source402that produces the input voltage VREF404.

In a certain embodiment the current INOSfrom the first variable current source704increases the current through the load resistance RLOAD, which in turn increases the input voltage VREF404at the non-inverting input708of the amplifier712by INOS*RLOAD. Consequently, after amplification, the output voltage of the amplifier712is increased by INOS*RLOAD*(1+RTOP/RBOT). Thus, increasing the current INOSfrom the first variable current source704increases the voltage at both the non-inverting input708and the output716of the amplifier. Accordingly, in various embodiments, a negative offset for the amplifier712may be trimmed or compensated for by providing a positive current INOSfrom the first variable current source704to increase the output voltage.

Correspondingly, in various embodiments, the second variable current source726, with current IPOS, is configured to compensate for a positive offset (e.g., an output voltage higher than expected). In certain embodiments, the second variable current source726is coupled to the inverting input710, and to the output716via the voltage divider718, such that increasing a current IPOSfrom the second variable current source726decreases a voltage at the output716of the amplifier712. For example, in the depicted embodiment, the second variable current source726is coupled to the middle of the voltage divider718, so that the bottom resistor722couples the second variable current source726to ground, and the top resistor720couples the second variable current source726to the output. As described above, the current through the bottom resistor722is VREF/RBOT, based on the voltage at the inverting input710approximately matching the voltage input voltage VREF404at the non-inverting input708due to negative feedback. However, in a further embodiment that current VREF/RBOTthrough the bottom resistor722is the sum of the current through the top resistor720and the current IPOSfrom the second variable current source726. Thus, providing a current IPOSfrom the second variable current source726decreases the current through the top resistor720, and decreases the voltage at the output716by IPOS*RTOP. Accordingly, in various embodiments, a positive offset for the amplifier712may be trimmed or compensated for by providing a positive current IPOSfrom the second variable current source726to decrease the output voltage.

In various embodiments, the variable current sources704,726may include any electrical components capable of being controlled to produce a variable current, such as a current-based digital-to-analog converter (“DAC”) which controls an analog current output based on a digital input, set of current mirrors that can be individually coupled or decoupled from an input current, or the like. Many types of components that output a variable current will be clear in view of this disclosure. In further embodiments, negative trim control702and positive trim control724control the currents INOSand IPOSfrom the first voltage source704and the second voltage source726, respectively. In various embodiments, the trim controls702,724may include any electrical components capable of controlling the variable current sources704,726. For example, in one embodiment, one or more of the current sources704,726may include a thermometer-coded DAC that couples varying numbers of individual fixed-current sources to an output, and the corresponding trim control(s)702,724may include a thermometric (e.g., binary to unary) decoder that switches on the individual current sources based on a digital input. InFIG. 7, the positive and negative trim controls702,724are depicted as separate components. However, in another embodiment, a single component may control the currents from both current sources704,726. For example, in one embodiment, a five-bit thermometric decoder may control15current sources in a DAC for the first voltage source704and an additional15current sources in a DAC for the second voltage source726.

In a certain embodiment, for trimming a negative output offset, the current INOSfrom the first variable current source704is set at a nonzero, positive value and the current IPOSfrom the second variable current source726is set at zero. Thus, the output voltage is increased by INOS*RLOAD*(1+RTOP/RBOT). In another embodiment, for trimming a positive output offset, the current INOSfrom the first variable current source704is set at zero and the current IPOSfrom the second variable current source726is set at a nonzero, positive value. Thus, the output voltage is decreased by IPOS*RTOP.

In certain embodiments, the current INOSfrom the first variable current source704and the current IPOSfrom the second variable current source726may be controlled in predetermined increments, where the predetermined increments are fixed size steps. In a further embodiment, the resistances RLOADand RTOPmay be configured (e.g., the ratio between RLOADand RTOPmay be selected by a manufacturer) so that an output voltage change from increasing the current INOSfrom the first variable current source704by a predetermined increment is equal to an output voltage change from decreasing the current IPOSfrom the second variable current source726by the same predetermined increment. For example, the output voltage change INOS*RLOAD*(1+RTOP/RBOT) for negative offset trimming may be configured to be equal to the output voltage change for positive offset trimming IPOS*RTOPfor currents of the same size by choosing an appropriate ratio RLOADand RTOP(where the ratio between RTOPand RBOTis already fixed to establish the desired closed-loop gain). In another embodiment, the resistance RLOADmay be an output impedance of the variable voltage source402that produces the input voltage VREF404, while RTOPand RBOTmay be selected based on specifications of the differential amplifier712, but the step or increment sizes for changing the currents INOSand IPOSmay be independently selected so that an output voltage change from increasing the current INOSfrom the first variable current source704by a first predetermined increment is equal to an output voltage change from decreasing the current IPOSfrom the second variable current source726by a second predetermined increment. The second predetermined increment, in various embodiments, may be equal to or different from the first predetermined increment.

Additionally, in a certain embodiment, an output voltage change from changing the current INOSfrom the first variable current source704and/or the current IPOSfrom the second variable current source726is based on a ratio of temperature dependent resistances, such that the output voltage change is temperature independent. For example, in one embodiment, each current source704,726may provide a current based on a temperature-independent voltage (e.g., a bandgap voltage reference), divided by a temperature-dependent base resistance, and multiplied by a variable amplification factor. Temperature coefficients of RLOAD, RTOP, and/or RBOTmay be matched to the temperature coefficient of the base resistance, so that the temperature coefficients cancel and the output voltage change is temperature independent for negative and/or positive offset trimming.

In certain embodiments, trimming an amplifier offset using two current sources704,726may provide for accurate trimming at near-zero input or output voltages. For example, in certain embodiments, an input voltage VREF404may be subject to a minimum voltage of 0 V. Thus, increasing the current INOSfrom the first variable current source704may increase the input voltage VREF404to compensate for a negative output offset, but decreasing INOS, or providing a negative current INOS, may not decrease the input voltage VREF404to compensate for a positive output offset if the input voltage VREF404is already near zero. Additionally, certain methods of amplifier offset trimming may rely on voltages well above ground voltage (0 V) at both inputs. For example, trimming an amplifier by adjusting currents internal to the amplifier712may rely on voltages well above ground voltage (0 V) at both inputs to provide positive bias currents. By contrast, trimming an amplifier offset using two current sources704,726, as described herein, may allow accurate trimming with input voltages near zero.

In one embodiment, an integrated circuit die may include the differential amplifier712, the first variable current source704, and the second variable current source726. For example, where the amplification component406is a component of a word line driver150, a non-volatile memory die may include a plurality of word lines312, a plurality of differential amplifiers712coupled to the word lines, a plurality of first variable current sources704for negative offset trimming, a plurality of second variable current sources726for positive offset trimming, and a plurality of variable voltage sources402that provide ramping voltage signals for amplification by the differential amplifiers712. In another embodiment, an amplification component406with offset trimming may be used in a context outside a word line driver150, but may nevertheless include the differential amplifier712, the first variable current source704, and the second variable current source726on a single integrated circuit die.

In certain embodiments, a current from one of the current sources704,726may be zero while the current from the other current source704,726is nonzero, depending on whether the amplifier712has a positive or negative offset. If the direction of the offset were known at the time of manufacturing, one of the current sources704,726could be omitted. However, amplifier offsets may be positive or negative at random, based on random variations in the manufacturing process. Thus, providing both current sources704,726on the same integrated circuit as the amplifier712allows for positive and/or negative offset trimming. In a further embodiment, a manufacturer of the integrated circuit die may set the current INOSfrom the first variable current source704and the current IPOSfrom the second variable current source726. For example, the manufacturer of the integrated circuit die may measure amplifier offsets during die sorting, and may set the currents INOSand IPOSto trim the amplifier output voltage. In one embodiment, where the amplifier712is on the same integrated circuit die as the variable voltage source402that provides the input voltage VREF404, offset trimming by a manufacturer may compensate for internal and/or system offsets simultaneously, without burdening the user with a further trimming process.

In general, in various embodiments, the process of trimming an amplifier offset may include setting the current INOSfrom the first variable current source704and the current IPOSfrom the second variable current source726to produce a target output voltage at the output716of the differential amplifier712in response to a preset input voltage. For example, in a certain embodiment, a preset input voltage VREF404may be selected so that the output voltage, in the absence of any offset, would equal a target output voltage. The currents IPOSand INOSmay then be adjusted until the actual output voltage equals (or at least approximately equals) the target output voltage. In a certain embodiment (e.g., for a CMOS amplifier), a minimum output voltage for the amplifier712may be zero volts, and the target output voltage may be near zero. For example, the target output voltage may be 50 mV, or in a range between zero and 100 mV. With a low target output voltage, the input voltages may similarly be near zero, but the output offset may nevertheless be effectively trimmed as described herein.

In a certain embodiment, trimming may be done in a low voltage to high voltage direction. For example, the current IPOSfrom the second variable current source726may be set to a maximum current while the current INOSfrom the first variable current source704is set to zero, so that the output voltage is trimmed to a lowest trimmed output voltage (for the preset input voltage). The current IPOSfrom the second variable current source726may then be reduced incrementally, until the output voltage is sufficiently close to the target voltage (e.g., the difference between the output voltage and the target voltage may be less than or equal to half of a step size for trimming the output voltage.) If the current IPOSfrom the second variable current source726is reduced to zero without the output voltage becoming sufficiently close to the target voltage, then the current INOSfrom the first variable current source704may be increased incrementally for further trimming of the output voltage.

FIG. 8is a graph800illustrating one embodiment of an amplifier output voltage with offset trimming. In the depicted embodiment, the current sources704,726are controlled by a DAC input stage (e.g., a thermometric decoder). Output voltage trimming is done in a low voltage to high voltage direction as described above, so that the output voltage802increases in predetermined steps from maximum positive output trimming (lowest output voltage) to maximum negative output trimming (highest output voltage) as the DAC input increases.

In the depicted embodiment, at an intermediate DAC input (indicated by the dashed line), the currents from current sources704,726are both zero, and the output voltage is untrimmed. At higher DAC inputs, the current INOSfrom the first variable current source704is increased to increase the voltage at the non-inverting input708and the output716, for trimming negative voltage offsets. At lower DAC inputs, the current IPOSfrom the second variable current source726is increased to decrease the output voltage, for trimming positive voltage offsets. In certain embodiments, resistances (e.g., RLOADand RTOP) may be configured so that the output step size for positive output trimming equals the output step size for negative output trimming.

FIG. 9is a schematic flow chart diagram illustrating one embodiment of a method900for amplifier offset trimming. In a certain embodiment, the method900may be performed by a manufacturer of an integrated circuit die comprising an amplifier712, at a die sort time. The method900begins, and a preset input voltage, corresponding to a target output voltage, is applied902to the non-inverting input708of an amplifier712. Trim currents INOSand IPOSare set904for a lowest trimmed output voltage (e.g., maximum IPOSand minimum INOS). The output voltage is measured906, and compared908to the target voltage. If the output voltage equals the target voltage (to within a tolerance level, such as half of a step size for adjusting the output voltage), then the trim currents INOSand IPOSare finalized912, and the method900ends. If the output voltage does not equal the target voltage (to within the tolerance level), then the trim currents INOSand IPOSare adjusted910(e.g., by decreasing IPOSor increasing INOS) to increase the output voltage by a predetermined step. The increased output voltage is then measured906, and compared908to the target voltage, and the method900continues.

In various embodiments, a means for amplification of an input voltage to drive a word line voltage for a non-volatile memory array may include an amplifier712, an amplification component406, a word line driver150, a die controller220in communication with the word line driver150, peripheral or management circuits for a non-volatile memory element123, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for amplification of an input voltage.

In various embodiments, a means for providing a first current, such that increasing the first current increases the word line voltage, may include a first variable current source704, a current-based DAC, a negative trim control702, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for providing a first current.

In various embodiments, a means for providing a second current, such that increasing the second current decreases the word line voltage, may include a second variable current source726, a current-based DAC, a positive trim control724, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for providing a second current.

In various embodiments, a means for providing an input voltage for an amplifier712may include a variable voltage source402, a signal generator, a line coupling a variable voltage source402to the amplifier, a controller that controls the voltage of a variable voltage source402, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for providing an input voltage.

In various embodiments, a means for controlling the first current and the second current for an amplifier712may include a negative trim control702, a positive trim control724, a DAC input stage, a thermometric decoder, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for controlling currents.