Multilevel fault simulations for integrated circuits (IC)

Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.

FIELD

Embodiments of the present disclosure relate generally to the technical fields of testing and fault simulation of integrated circuits (IC), with particular applications to ICs used in computer assisted or autonomous driving.

BACKGROUND

An integrated circuit (IC) or monolithic integrated circuit (also referred to as a chip, or a microchip) includes a set of electronic circuits formed on a semiconductor material, normally silicon. ICs may perform various functions, e.g., functions in computer assisted or autonomous driving (CA/AD) vehicles, or other functions. Automatic test pattern generation (ATPG) is an electronic design automation method/technology used to find test vectors that, when applied to an IC, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. Fault coverage refers to the percentage of faults that can be detected by test vectors based on a fault model during the testing of an IC. Fault simulation is to detect the fault coverage based on the fault model during the testing of an IC.

DETAILED DESCRIPTION

An integrated circuits (IC) may be described at various levels of abstractions, e.g., by a gate level netlist, or a register transfer level (RTL) netlist, using a hardware design language, e.g., VHDL, Verilog, or other hardware design languages. Fault coverage refers to the percentage of some type of fault that can be detected by test vectors in an automatic test pattern generation (ATPG) process based on a fault model. Fault simulation is to determine the fault coverage of modeled faults detected by test vectors during the testing of a system, e.g., an IC.

A computer assisted or autonomous driving (CA/AD) vehicle may include many ICs or device components manufactured by different parties. Functional safety is an important consideration for CA/AD vehicles. Various standard bodies, e.g., the International Organization for Standardization (ISO), have developed standards for the CA/AD vehicle industry. For example, the ISO 26262 standard, titled “Road vehicles—Functional safety,” is an international standard for functional safety of electrical and/or electronic systems in computer assisted or autonomous driving vehicles. The ISO 26262 standard may specify various safety levels, e.g., Automotive Safety Integrity Level (ASIL) A, B, C or D.

Functional safety standards may specify fault injections based on a fault model to perform fault simulations at the gate level of an IC. Significant effort and costs may be used to construct a fault simulation environment at the gate level of an IC. Previous efforts to perform fault simulations based on RTL descriptions of an IC have not been successful in producing results that are correlated with gate level faults of the IC. Additional techniques, e.g., statistical sampling of a gate level fault list have not solved the problem.

Embodiments herein provides an effective way to accurately estimate fault coverage metrics for a gate level netlist of an IC without performing gate level fault simulations. Instead, fault simulations are performed on the RTL netlist using a subset of faults that can be shown to be functionally equivalent to faults in the gate level netlist. The accuracy of computed fault coverage metrics is closely aligned to the accuracy of the original gate level netlist faults.

In embodiments, a gate level fault list of a fault model extracted from a gate level netlist of an IC may be divided into one or more gate level fault groups, where each gate level fault group includes one or more gate level faults. The gate level faults in a gate level fault group is associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. Some gate level fault groups may have correlated RTL fault groups associated to a RTL circuit node of the RTL netlist, where the RTL circuit node corresponds to the gate level circuit element. RTL fault simulation is performed based on a fault simulation algorithm for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node, to measure a fault coverage metric of the fault class for the corresponding correlated RTL fault group. Afterwards, a fault coverage metric of the fault class for the IC may be derived by combining the fault coverage metrics of the fault class for the corresponding correlated RTL fault group and a fault distribution of the each gate level fault group of the total testable gate level faults.

In embodiments, an apparatus for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. The storage device stores a gate level netlist of the IC and a RTL netlist of the IC corresponding to the gate level netlist. The processing circuitry provides a gate level fault group including one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. In addition, the processing circuitry may determine, for the gate level fault group associated to the gate level circuit element, a correlated RTL fault group includes one or more RTL faults. The correlated RTL fault group is associated to a RTL circuit node of the RTL netlist, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element of the gate level netlist.

In embodiments, a method for testing an IC of an in-vehicle system of a CA/AD vehicle is to be performed. The method includes performing, with a simulator, RTL fault simulation based on a fault simulation algorithm for a RTL fault group associated with a RTL circuit node of a RTL netlist of the IC. The RTL circuit node corresponds to a gate level circuit element of a gate level netlist of the IC, and the RTL fault group corresponds to a gate level fault group of a fault model associated with the gate level circuit element to test the IC for compliance with a functional safety standard for the IC in the in-vehicle system of the CA/AD vehicle. The method further includes classifying RTL faults of the RTL fault group by a fault class to provide a fault coverage metric of the fault class for the RTL fault group.

In embodiments, one or more non-transitory computer-readable media comprises instructions that cause processing circuitry to perform fault simulation of an IC, in response to execution of the instructions by the processing circuitry, to: extract a gate level fault list of a fault model from a gate level netlist of the IC; prune the gate level fault list to exclude one or more untestable faults to obtain a pruned gate level fault list; and classify the pruned gate level fault list to obtain one or more gate level fault groups, where each gate level fault group of the one or more gate level fault groups includes one or more gate level faults associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. In addition, in response to execution of the instructions by the processing circuitry, the instructions further cause the processing circuitry to determine, for each gate level fault group of the one or more gate level fault groups associated to a gate level circuit element with a corresponding RTL circuit node of a RTL netlist of the IC, a corresponding correlated RTL fault group associated to the corresponding RTL circuit node that includes one or more RTL faults; perform RTL fault simulation based on the fault simulation algorithm for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node; classify a RTL fault in the corresponding correlated RTL fault group by a fault class; and measure a fault coverage metric of the fault class for the corresponding correlated RTL fault group.

As used herein, the term semi-autonomous driving is synonymous with computer-assisted driving. The term does not mean exactly 50% of the driving functions are automated. The percentage of automated driving functions may vary between 0% and 100%. In addition, it will be appreciated that the hardware, circuitry and/or software implementing the semi-autonomous driving may temporarily provide no automation, or 100% automation, such as in response to an emergency situation.

Operations of various methods may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiments. Various additional operations may be performed and/or described operations may be omitted, split or combined in additional embodiments.

For the purposes of the present disclosure, the phrase “A or B” and “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include plural forms as well, unless the context clearly indicates otherwise. The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specific the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operation, elements, components, and/or groups thereof.

The terms “coupled with” and “coupled to” and the like may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. By way of example and not limitation, “coupled” may mean two or more elements or devices are coupled by electrical connections on a printed circuit board such as a motherboard, for example. By way of example and not limitation, “coupled” may mean two or more elements/devices cooperate and/or interact through one or more network linkages such as wired and/or wireless networks. By way of example and not limitation, a computing apparatus may include two or more computing devices “coupled” on a motherboard or by one or more network linkages.

As used herein, the term “circuitry” refers to, is part of, or includes hardware components such as an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group), an Application Specific Integrated Circuit (ASIC), a field-programmable device (FPD), (for example, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high-capacity PLD (HCPLD), a structured ASIC, or a programmable System on Chip (SoC)), digital signal processors (DSPs), etc., that are configured to provide the described functionality. In some embodiments, the circuitry may execute one or more software or firmware programs to provide at least some of the described functionality.

As used herein, the term “processor circuitry” may refer to, is part of, or includes circuitry capable of sequentially and automatically carrying out a sequence of arithmetic or logical operations; recording, storing, and/or transferring digital data. The term “processor circuitry” may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core processor, a dual-core processor, a triple-core processor, a quad-core processor, and/or any other device capable of executing or otherwise operating computer-executable instructions, such as program code, software modules, and/or functional processes.

As used herein, the term “interface” or “interface circuitry” may refer to, is part of, or includes circuitry providing for the exchange of information between two or more components or devices. The term “interface circuitry” may refer to one or more hardware interfaces (for example, buses, input/output (I/O) interfaces, peripheral component interfaces, network interface cards, and/or the like).

As used herein, the term “computer device” may describe any physical hardware device capable of sequentially and automatically carrying out a sequence of arithmetic or logical operations, equipped to record/store data on a machine readable medium, and transmit and receive data from one or more other devices in a communications network. A computer device may be considered synonymous to, and may hereafter be occasionally referred to, as a computer, computing platform, computing device, etc. The term “computer system” may include any type interconnected electronic devices, computer devices, or components thereof. Additionally, the term “computer system” and/or “system” may refer to various components of a computer that are communicatively coupled with one another. Furthermore, the term “computer system” and/or “system” may refer to multiple computer devices and/or multiple computing systems that are communicatively coupled with one another and configured to share computing and/or networking resources. Examples of “computer devices”, “computer systems”, etc. may include cellular phones or smart phones, feature phones, tablet personal computers, wearable computing devices, an autonomous sensors, laptop computers, desktop personal computers, video game consoles, digital media players, handheld messaging devices, personal data assistants, an electronic book readers, augmented reality devices, server computer devices (e.g., stand-alone, rack-mounted, blade, etc.), cloud computing services/systems, network elements, in-vehicle infotainment (IVI), in-car entertainment (ICE) devices, an Instrument Cluster (IC), head-up display (HUD) devices, onboard diagnostic (OBD) devices, dashtop mobile equipment (DME), mobile data terminals (MDTs), Electronic Engine Management Systems (EEMSs), electronic/engine control units (ECUs), vehicle-embedded computer devices (VECDs), autonomous or semi-autonomous driving vehicle (hereinafter, simply ADV) systems, in-vehicle navigation systems, electronic/engine control modules (ECMs), embedded systems, microcontrollers, control modules, engine management systems (EMS), networked or “smart” appliances, machine-type communications (MTC) devices, machine-to-machine (M2M), Internet of Things (IoT) devices, and/or any other like electronic devices. Moreover, the term “vehicle-embedded computer device” may refer to any computer device and/or computer system physically mounted on, built in, or otherwise embedded in a vehicle.

As used herein, the term “network element” may be considered synonymous to and/or referred to as a networked computer, networking hardware, network equipment, router, switch, hub, bridge, radio network controller, radio access network device, gateway, server, and/or any other like device. The term “network element” may describe a physical computing device of a wired or wireless communication network and be configured to host a virtual machine. Furthermore, the term “network element” may describe equipment that provides radio baseband functions for data and/or voice connectivity between a network and one or more users. The term “network element” may be considered synonymous to and/or referred to as a “base station.” As used herein, the term “base station” may be considered synonymous to and/or referred to as a node B, an enhanced or evolved node B (eNB), next generation nodeB (gNB), base transceiver station (BTS), access point (AP), roadside unit (RSU), etc., and may describe equipment that provides the radio baseband functions for data and/or voice connectivity between a network and one or more users. As used herein, the terms “vehicle-to-vehicle” and “V2V” may refer to any communication involving a vehicle as a source or destination of a message. Additionally, the terms “vehicle-to-vehicle” and “V2V” as used herein may also encompass or be equivalent to vehicle-to-infrastructure (V2I) communications, vehicle-to-network (V2N) communications, vehicle-to-pedestrian (V2P) communications, or V2X communications.

As used herein, the term “channel” may refer to any transmission medium, either tangible or intangible, which is used to communicate data or a data stream. The term “channel” may be synonymous with and/or equivalent to “communications channel,” “data communications channel,” “transmission channel,” “data transmission channel,” “access channel,” “data access channel,” “link,” “data link,” “carrier,” “radiofrequency carrier,” and/or any other like term denoting a pathway or medium through which data is communicated. Additionally, the term “link” may refer to a connection between two devices through a Radio Access Technology (RAT) for the purpose of transmitting and receiving information.

FIG. 1illustrates an example CA/AD vehicle101including various ICs, in accordance with various embodiments. For clarity, features of the CA/AD vehicle101, and various ICs, e.g., an IC121, an IC124, an IC125, an IC126, or an IC127, are described below as an example for understanding an example CA/AD vehicle and various ICs. It is to be understood that there may be more or fewer components included in the CA/AD vehicle101and various ICs. Further, it is to be understood that one or more of the devices and components within the CA/AD vehicle101and various ICs may include additional and/or varying features from the description below, and may include any devices and components that one having ordinary skill in the art would consider and/or refer to as the CA/AD vehicle and various ICs.

In embodiments, the CA/AD vehicle101communicates with a roadside unit (RSU)103, and a cloud computing environment (“cloud” for short)105. [As used herein, unless the context clearly indicates otherwise, the term “cloud” does not refer to a visible mass of condensed water vapor floating in the atmosphere/sky.] The cloud105includes a number of cloud servers151, which may include e.g., an application server. The communication between the RSU103, the cloud105, or the cloud server151, and the CA/AD vehicle101may be a part of a vehicle-to-infrastructure (V2I) communications. For example, the CA/AD vehicle101may communicate with the RSU103, the cloud105, or the cloud server151, via a wireless technology131. The wireless technology131may include a selected one of dedicated short range communications (DSRC) technology, Bluetooth technology, wireless fidelity (WiFi) technology, wireless local network (WLAN), cellular wireless network technology, short range radio technology, or any other wireless technology. In addition, the RSU103may communicate with the cloud105by a link132, which may be a wireless or wired connection.

In embodiments, the CA/AD vehicle101includes a vehicle onboard unit (OBU)115, various sensors, e.g., a sensor111, a display114, and other components, not shown. Various ICs, e.g., the IC121, the IC124, the IC125, the IC126, or the IC127may be included in the sensor111, the display114, the OBU115, the RSU103, or the cloud server151, respectively, to perform various functions associated with the CA/AD vehicle101, the RSU103, or the cloud105.

In embodiments, the CA/AD vehicle101may be any type of motorized vehicle or device used for transportation of people or goods, which may be equipped with controls used for driving, parking, passenger comfort and/or safety, etc. The terms “motor”, “motorized”, etc., as used herein may refer to devices that convert one form of energy into mechanical energy, and may include internal combustion engines (ICE), compression combustion engines (CCE), electric motors, and hybrids (e.g., including an ICE/CCE and electric motor(s)). For example, the CA/AD vehicle101is a selected one of a commercial truck, a light duty car, a sport utility vehicle (SUV), a light vehicle, a heavy duty vehicle, a pickup truck, a van, a car, or a motorcycle.

In embodiments, the RSU103may be one or more hardware computer devices configured to provide wireless communication services to mobile devices (for example, OBU115in the CA/AD vehicle101or some other suitable device) within a coverage area or cell associated with the RSU103. The RSU103includes a transmitter/receiver (or alternatively, a transceiver) connected to one or more antennas, one or more memory devices, one or more processors, one or more network interface controllers, and/or other like components. The one or more transmitters/receivers are configured to transmit/receive data signals to/from one or more mobile devices via a link. Furthermore, one or more network interface controllers are configured to transmit/receive with various network elements (e.g., one or more servers within a core network, etc.) over another backhaul connection (not shown).

As an example, the RSU103may be a base station associated with a cellular network (e.g., an eNB in an LTE network, a gNB in a new radio access technology (NR) network, a WiMAX base station, etc.), a remote radio head, a relay radio device, a small cell base station (e.g., a femtocell, picocell, home evolved nodeB (HeNB), and the like), or other like network element. In addition, the RSU103may be a road embedded reflector, a smart street or traffic light, a road side tag, or a stationary user equipment (UE) type RSU.

In embodiments, the cloud105may represent the Internet, one or more cellular networks, a local area network (LAN) or a wide area network (WAN) including proprietary and/or enterprise networks, transfer control protocol (TCP)/internet protocol (IP)-based network, or combinations thereof. In such embodiments, the cloud105may be associated with network operator who owns or controls equipment and other elements necessary to provide network-related services, such as one or more base stations or access points (e.g., the RSU103), one or more servers for routing digital data or telephone calls (for example, a core network or backbone network), etc. Implementations, components, and protocols used to communicate via such services may be those known in the art and are omitted herein for the sake of brevity.

In some embodiments, the cloud105may be a system of computer devices (e.g., servers, storage devices, applications, etc. within or associated with a data center or data warehouse) that provides access to a pool of computing resources. The term “computing resource” refers to a physical or virtual component within a computing environment and/or within a particular computer device, such as memory space, processor time, electrical power, input/output operations, ports or network sockets, and the like. In these embodiments, the cloud105may be a private cloud, which offers cloud services to a single organization; a public cloud, which provides computing resources to the general public and shares computing resources across all customers/users; or a hybrid cloud or virtual private cloud, which uses a portion of resources to provide public cloud services while using other dedicated resources to provide private cloud services. For example, the hybrid cloud may include a private cloud service that also utilizes one or more public cloud services for certain applications or users, such as providing obtaining data from various data stores or data sources. In embodiments, a common cloud management platform (e.g., implemented as various virtual machines and applications hosted across the cloud105and database systems) may coordinate the delivery of data to the OBU115of the CA/AD vehicle101. Implementations, components, and protocols used to communicate via such services may be those known in the art and are omitted herein for the sake of brevity.

FIG. 2illustrates an example apparatus200for performing multilevel fault simulations for an IC205, in accordance with various embodiments. In embodiments, the IC205may be an example of the IC121, the IC124, the IC125, the IC126, or the IC127, of the CA/AD vehicle101, as described inFIG. 1. In some other embodiments, the IC205may be used in any other applications not related to the CA/AD vehicle101.

In embodiments, the apparatus200includes a storage device201, and processing circuitry203coupled with the storage device201, to perform multilevel fault simulations for the IC205. The storage device201stores a gate level netlist211of the IC205, and a RTL netlist213of the IC205corresponding to the gate level netlist211. The gate level netlist211includes one or more gate level circuit elements, e.g., a gate level circuit element212, and the RTL netlist213includes one or more RTL circuit nodes, e.g., a RTL circuit node214. The gate level circuit element212may be a selected one of a combinatorial logic gate, a flip-flop, a latch, a clock pin of a sequential logic circuit, a scan pin of a sequential logic circuit, a standard cell input pin, or a standard cell output pin. The RTL circuit node214corresponds to the gate level circuit element212, determined by logic equivalence checking, simulation-based equivalence checking, binary decision diagrams based equivalence checking, or conjunctive normal form satisfiability equivalence checking.

In embodiments, the processing circuitry203is to provide a gate level fault group234, which includes one or more gate level faults of a fault model associated to the gate level circuit element212. The one or more gate level faults of the gate level fault group234may have substantially same fault controllability or observability characteristics. The one or more gate level faults of the gate level fault group234are based on a same fault model, which may include stuck-at-fault, bridging fault, current leak fault, transistor stuck-at-fault, functional fault, memory fault, delay fault, or state transition fault.

In embodiments, the processing circuitry203determines a correlated RTL fault group244for the gate level fault group234associated to the gate level circuit element212. The correlated RTL fault group244includes one or more RTL faults. The correlated RTL fault group244is associated to the RTL circuit node214. The RTL circuit node214corresponds to the gate level circuit element212.

In embodiments, the processing circuitry203performs a RTL fault simulation, by a simulator241, based on a fault simulation algorithm243, for the correlated RTL fault group244associated to the RTL circuit node214. The simulator241may test the IC205for compliance with a functional safety standard for the IC205in an in-vehicle system of a CA/AD vehicle, e.g., the CA/AD vehicle101. In some other embodiments, the simulator241may perform fault simulation for the IC205based on other fault metrics. The fault simulation algorithm243may include a serial fault simulation algorithm, a parallel fault simulation algorithm, a deductive fault simulation algorithm, a concurrent fault simulation algorithm, or a differential fault simulation algorithm.

In embodiments, the processing circuitry203may further classify a RTL fault in the correlated RTL fault group244by a fault class, and measure a fault coverage metric248of the fault class for the correlated RTL fault group244. The fault class may include a detectable fault class, a potentially detectable fault class, or an observable but not detectable fault class.

FIG. 3illustrates another example apparatus300for performing multilevel fault simulations for an IC305, in accordance with various embodiments. In embodiments, the IC305may be an example of the IC121, the IC124, the IC125, the IC126, or the IC127, of the CA/AD vehicle101, as described forFIG. 1, or an example of the IC205as described forFIG. 2.

In embodiments, the apparatus300includes a storage device301, and processing circuitry303coupled with the storage device301, to perform multilevel fault simulations for the IC305. The storage device301stores a gate level netlist311of the IC305, and a RTL netlist313of the IC305corresponding to the gate level netlist311. The gate level netlist311includes one or more gate level circuit elements, e.g., a gate level circuit element312, and a gate level circuit element316, while the RTL netlist313includes one or more RTL circuit nodes, e.g., a RTL circuit node314. The RTL circuit node314corresponds to the gate level circuit element312, determined by an equivalence checking. Not all gate level circuit elements of the gate level netlist311has a corresponding RTL circuit node314. For example, the gate level circuit element316does not have a corresponding RTL circuit node, which may be called as a non-corresponding gate level circuit element.

In embodiments, the processing circuitry303is to extract a gate level fault list331of a fault model from the gate level netlist311, and prune the gate level fault list331to exclude one or more untestable faults to obtain a pruned gate level fault list333. The one or more untestable faults may include a blocked fault, a tied-off fault, a redundant fault, an unobservable fault, or an uncontrollable fault.

In embodiments, the processing circuitry303is to classify the pruned gate level fault list333to obtain one or more gate level fault groups, e.g., a gate level fault group332, a gate level fault group334, a gate level fault group336, and more. A gate level fault group, e.g., the gate level fault group332, the gate level fault group334, or the gate level fault group336, includes one or more gate level faults based on a same fault model. Each gate level fault group, e.g., the gate level fault group332, the gate level fault group334, or the gate level fault group336includes one or more gate level faults associated to a gate level circuit element of the gate level netlist311of the IC305with substantially same fault controllability or observability characteristics. For example, the gate level fault group332includes one or more gate level faults associated to the gate level circuit element312with substantially same fault controllability or observability characteristics. Similarly, the gate level fault group336includes one or more gate level faults associated to the gate level circuit element316with substantially same fault controllability or observability characteristics.

Each of the gate level fault groups, e.g., e.g., the gate level fault group332, the gate level fault group334, or the gate level fault group336has a fault distribution calculated based on the number of gate level faults in the gate level fault group. For example, the gate level fault group332has a fault distribution335, the gate level fault group334has a fault distribution337, and the gate level fault group336has a fault distribution339. The fault distribution of a gate level fault group, e.g., the gate level fault group332, the gate level fault group334, or the gate level fault group336, is determined by the percentage of the one or more gate level faults of the gate level fault group compared to the total number of gate level faults of the pruned gate level fault list333. For example, the fault distribution335of the gate level fault group332is determined by a percentage of the number of gate level faults in the gate level fault group332compared to the total number of gate level faults in the pruned gate level fault list333.

For example, the following table shows multiple gate level fault groups in the first column including one or more gate level faults associated to the gate level circuit element. The second column lists the number of gate level faults of the gate level fault group, while the third column lists the fault distribution of the gate level fault group compared to the total number of gate level faults in the pruned gate level fault list. For example, the second row includes a gate level fault group including 282862 gate level faults associated to a gate level circuit element, e.g., sequential ports—clk, with a fault distribution of 4.06%, calculated as (282862/6973718), where 6973718 is the total number of gate level faults in the pruned gate level fault list333.

In embodiments, the processing circuitry303is further to determine, for each gate level fault group associated to a gate level circuit element with a corresponding RTL circuit node, a corresponding correlated RTL fault group associated to the corresponding RTL circuit node. For example, the gate level fault group332includes one or more gate level faults associated to the gate level circuit element312, while the gate level circuit element312has corresponding RTL circuit node314. A RTL fault group344is determined as a corresponding correlated RTL fault group associated to the corresponding RTL circuit node314. The RTL fault group344includes one or more RTL faults associated to the corresponding RTL circuit node314. Similarly, the gate level fault group334has a corresponding correlated RTL fault group346including one or more RTL faults.

In embodiments, the gate level fault group336is a non-corresponding gate level fault group, which does not have a corresponding correlated RTL fault group. The gate level fault group336is associated with a non-corresponding gate level circuit element316of the gate level netlist311, and the non-corresponding gate level circuit element316does not have a corresponding RTL circuit node of the RTL netlist313.

In embodiments, the processing circuitry303is further to perform RTL fault simulation, by a simulator341, based on a fault simulation algorithm343for the corresponding correlated RTL fault groups associated to the corresponding RTL circuit nodes. For example, the processing circuitry303is to perform RTL fault simulation for the corresponding correlated RTL fault group344associated to the corresponding RTL circuit node314. Similarly, the processing circuitry303is to perform RTL fault simulation for the corresponding correlated RTL fault group346associated to a corresponding RTL circuit node. In embodiments, the RTL fault simulation performed for the corresponding correlated RTL fault group344associated to the corresponding RTL circuit node314may be similar to the RTL fault simulation performed for the correlated RTL fault group244associated to the corresponding RTL circuit node214, as described inFIG. 2.

In embodiments, the processing circuitry303is further to classify a RTL fault in the corresponding correlated RTL fault group by a fault class, and measure a fault coverage metric of the fault class for the corresponding correlated RTL fault group. The fault class may include a detectable fault class, a potentially detectable fault class, or an observable but not detectable fault class. For example, the processing circuitry303is to classify a RTL fault in the correlated RTL fault group344by a fault class, and measure a fault coverage metric348of the fault class for the correlated RTL fault group344. Similarly, the processing circuitry303is to classify a RTL fault in the correlated RTL fault group346by a fault class, and measure a fault coverage metric349of the fault class for the correlated RTL fault group346.

In embodiments, the processing circuitry303is further to derive a fault coverage metric351of the fault class for the IC305by combining the fault coverage metrics of the fault class for the corresponding correlated RTL fault group based on a fault distribution of the each gate level fault group, and the fault coverage metric of the fault class for the corresponding correlated RTL fault group. For example, for a fault class, the fault coverage metric351may be a sum of (fault coverage metric348*the fault distribution335), (fault coverage metric349*the fault distribution337), and other corresponding products of other fault coverage metric and fault distribution for other gate level fault groups, where the fault coverage metric348of the fault class is for the correlated RTL fault group344, the fault coverage metric349of the fault class is for the correlated RTL fault group346, the fault distribution335is for the gate level fault group332, and the fault distribution337is for the gate level fault group334.

In some embodiments, before performing the fault simulation by the simulator341, based on the fault simulation algorithm343for the corresponding correlated RTL fault groups, the processing circuitry303may estimate an accuracy of the fault coverage metric of the fault class for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node for the each gate level fault group associated to the gate level circuit element with the corresponding RTL circuit node. If the estimated accuracy of the fault coverage metric of the fault class is not acceptable based on a threshold, the processing circuitry203may generate one or more additional correlated RTL fault group, e.g., an additional correlated RTL fault group347. Additional fault simulation may be performed on the additional correlated RTL fault group, e.g., the additional correlated RTL fault group347, so that the final fault coverage metric351of the fault class for the IC305is acceptable by the threshold.

FIG. 4illustrates an example process400for performing multilevel fault simulations for an IC, in accordance with various embodiments. In embodiments, the process400may be a multilevel fault simulation process performed by the apparatus300for an IC, e.g., the IC121, the IC124, the IC125, the IC126, or the IC127, of the CA/AD vehicle101, as described forFIG. 1, the IC205as described forFIG. 2, or the IC305as described forFIG. 3.

The process400may start at an interaction401. During the interaction401, a gate level fault list of a fault model may be extracted from a gate level netlist of the IC. For example, at the interaction401, the gate level fault list331is extracted from the gate level netlist311.

During an interaction403, the gate level fault list may be pruned to exclude one or more untestable faults to obtain a pruned gate level fault list. For example, at the interaction403, the gate level fault list331is pruned to exclude one or more untestable faults to obtain the pruned gate level fault list333.

During an interaction405, the pruned gate level fault list may be classified to obtain one or more gate level fault groups, wherein each gate level fault group of the one or more gate level fault groups includes one or more gate level faults associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. For example, at the interaction405, the pruned gate level fault list333is classified to obtain the gate level fault group332, the gate level fault group334, and the gate level fault group336, each gate level fault group includes one or more gate level faults associated to a gate level circuit element of the gate level netlist311of the IC305with substantially same fault controllability or observability characteristics.

During an interaction407, for each gate level fault group of the one or more gate level fault groups associated to a gate level circuit element with a corresponding RTL circuit node of a RTL netlist of the IC, a corresponding correlated RTL fault group associated to the corresponding RTL circuit node is determined, where the corresponding correlated RTL fault group includes one or more RTL faults. For example, at the interaction407, for the gate level fault group332associated to the gate level circuit element312, a corresponding correlated RTL fault group344associated to the corresponding RTL circuit node314is determined. Similarly, for the gate level fault group334, a corresponding correlated RTL fault group346associated to a corresponding RTL circuit node is also determined.

During an interaction409, RTL fault simulation may be performed based on a fault simulation algorithm for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node. For example, at the interaction409, RTL fault simulation is performed based on a fault simulation algorithm343for the corresponding correlated RTL fault group344associated to the corresponding RTL circuit node314.

During an interaction411, a RTL fault in the corresponding correlated RTL fault group is classified by a fault class. For example, at the interaction411, a RTL fault in the corresponding correlated RTL fault group344is classified by a fault class.

During an interaction413, a fault coverage metric of the fault class for the corresponding correlated RTL fault group is measured. For example, at the interaction413, the fault coverage metric348of the fault class for the corresponding correlated RTL fault group344is measured.

FIG. 5illustrates a hardware component view of a computing platform500used in a CA/AD vehicle or an apparatus for performing multilevel fault simulations of an IC, in accordance with various embodiments. As shown, the computing platform500, which may be an in-vehicle system of the CA/AD vehicle101, the apparatus200ofFIG. 2, or the apparatus300ofFIG. 3, may include one or more SoCs502, ROM503and system memory504. Each SoCs502may include one or more processor cores (CPUs), one or more graphics processor units (GPU), one or more accelerators, such as computer vision (CV) and/or deep learning (DL) accelerators. ROM503may include BIOS505. CPUs, GPUs, and CV/DL accelerators may be any one of a number of these elements known in the art. Similarly, ROM503and basic input/output system services (BIOS)505may be any one of a number of ROM and BIOS known in the art, and system memory504may be any one of a number of volatile storage known in the art.

Additionally, computing platform500may include persistent storage devices506. Example of persistent storage devices506may include, but are not limited to, flash drives, hard drives, compact disc read-only memory (CD-ROM) and so forth. Further, computing platform500may include input/output devices508(such as display, keyboard, cursor control and so forth) and communication interfaces510(such as network interface cards, modems and so forth). In some embodiments, e.g., embodiments used for an in-vehicle system of the CA/AD vehicle101, computing platform500may further include a number of sensors520. Communication and I/O devices508may include any number of communication and I/O devices known in the art. Examples of communication devices may include, but are not limited to, networking interfaces for Bluetooth®, Near Field Communication (NFC), WiFi, Cellular communication (such as LTE, 4G, or 5G) and so forth. The elements may be coupled to each other via system bus512, which may represent one or more buses. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown). Sensors520may include light detection and ranging (LiDAR) sensors, geo-positioning sensors, gyroscopes, accelerometers, temperature sensors, humidity sensors, and so forth.

Each of these elements may perform its conventional functions known in the art. In particular, ROM503may include BIOS505having a boot loader. In embodiments, system memory504and mass storage devices506may be employed to store a working copy and a permanent copy of the programming instructions implementing the operations associated with the apparatus200, the apparatus300to perform multilevel fault simulations for an IC, collectively referred to as computational logic522. The various elements may be implemented by assembler instructions supported by processor core(s) of SoCs502or high-level languages, such as, for example, C, that can be compiled into such instructions. In embodiments, one or more ICs, e.g., SoCs502, ROM503, memory504, or ICs used in persistent storage506, communication interface510, I/O device interface508, and/or sensors520may be ICs having gone through functional and safety standard testing in accordance with the present disclosure, as earlier described.

FIG. 6illustrates a storage medium having instructions for practicing methods described with references toFIGS. 1-5, in accordance with various embodiments. As shown, non-transitory computer-readable storage medium602may include a number of programming instructions604. Programming instructions604may be configured to enable a device, e.g., computing platform500, in response to execution of the programming instructions, to implement (aspects of) operations associated with the apparatus200, the apparatus300to perform multilevel fault simulations for an IC. In alternate embodiments, programming instructions604may be disposed on multiple computer-readable non-transitory storage media602instead. In still other embodiments, programming instructions604may be disposed on computer-readable transitory storage media602, such as, signals.

Thus various example embodiments of the present disclosure have been described including, but are not limited to:

Example 1 may include an apparatus for testing an integrated circuit (IC) of an in-vehicle system of a computer-assisted or autonomous driving (CA/AD) vehicle, comprising: a storage device to store a gate level netlist of the IC and a register transfer level (RTL) netlist of the IC corresponding to the gate level netlist; processing circuitry, coupled with the storage device, the processing circuitry to: provide a gate level fault group includes one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics; and determine, for the gate level fault group associated to the gate level circuit element, a correlated RTL fault group associated to a RTL circuit node of the RTL netlist, wherein the RTL circuit node of the RTL netlist corresponds to the gate level circuit element of the gate level netlist, and the correlated RTL fault group includes one or more RTL faults.

Example 2 may include the apparatus of example 1 and/or some other examples herein, wherein the gate level circuit element includes a selected one of a combinatorial logic gate, a flip-flop, a latch, a clock pin of a sequential logic circuit, a scan pin of a sequential logic circuit, a standard cell input pin, or a standard cell output pin.

Example 3 may include the apparatus of example 1 and/or some other examples herein, wherein the fault model includes stuck-at-fault, bridging fault, current leak fault, transistor stuck-at-fault, functional fault, memory fault, delay fault, or state transition fault.

Example 4 may include the apparatus of example 1 and/or some other examples herein, wherein the RTL circuit node of the RTL netlist corresponding to the gate level circuit element of the gate level netlist is determined by logic equivalence checking, simulation-based equivalence checking, binary decision diagrams based equivalence checking, or conjunctive normal form satisfiability equivalence checking.

Example 5 may include the apparatus of example 1 and/or some other examples herein, wherein the processing circuitry is further to: perform a RTL fault simulation based on a fault simulation algorithm for the correlated RTL fault group associated to the RTL circuit node, to test the IC for compliance with a functional safety standard for the IC in the in-vehicle system of the CA/AD vehicle.

Example 6 may include the apparatus of example 5 and/or some other examples herein, wherein the fault simulation algorithm includes a serial fault simulation algorithm, a parallel fault simulation algorithm, a deductive fault simulation algorithm, a concurrent fault simulation algorithm, or a differential fault simulation algorithm.

Example 7 may include the apparatus of example 5 and/or some other examples herein, wherein the processing circuitry is further to: classify a RTL fault in the correlated RTL fault group by a fault class; and measure a fault coverage metric of the fault class for the correlated RTL fault group.

Example 8 may include the apparatus of example 7 and/or some other examples herein, wherein the fault class includes a detectable fault class, a potentially detectable fault class, or an observable but not detectable fault class.

Example 9 may include the apparatus of example 7 and/or some other examples herein, wherein the gate level fault group associated to the gate level circuit element is a first gate level fault group associated to a first gate level circuit element, and the processing circuitry is further to: extract a gate level fault list of the fault model from the gate level netlist of the IC; prune the gate level fault list to exclude one or more untestable faults to obtain a pruned gate level fault list; and classify the pruned gate level fault list to obtain one or more gate level fault groups, wherein the one or more gate level fault groups includes the first gate level fault group associated to the first gate level circuit element, each gate level fault group of the one or more gate level fault groups includes one or more gate level faults associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics.

Example 10 may include the apparatus of example 9 and/or some other examples herein, wherein the one or more untestable faults include a blocked fault, a tied-off fault, a redundant fault, an unobservable fault, or an uncontrollable fault.

Example 11 may include the apparatus of example 9 and/or some other examples herein, the processing circuitry is further to: determine, for each gate level fault group of the one or more gate level fault groups associated to a gate level circuit element with a corresponding RTL circuit node, a corresponding correlated RTL fault group associated to the corresponding RTL circuit node, wherein the corresponding correlated RTL fault group includes one or more RTL faults; perform RTL fault simulation based on a fault simulation algorithm for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node; classify a RTL fault in the corresponding correlated RTL fault group by a fault class; and measure a fault coverage metric of the fault class for the corresponding correlated RTL fault group.

Example 12 may include the apparatus of example 11 and/or some other examples herein, wherein there exists an non-corresponding gate level fault group of the one or more gate level fault groups, the non-corresponding gate level fault group is associated with an non-corresponding gate level circuit element of the gate level netlist, and the non-corresponding gate level circuit element does not have a corresponding RTL circuit node of the RTL netlist.

Example 13 may include the apparatus of example 11 and/or some other examples herein, the processing circuitry is further to: estimate an accuracy of the fault coverage metric of the fault class for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node for the each gate level fault group associated to the gate level circuit element with the corresponding RTL circuit node; generate additional correlated RTL fault groups for the one or more gate level fault groups based on the estimated accuracy and a threshold; and perform RTL fault simulation based on the fault simulation algorithm for the additional correlated RTL fault groups.

Example 14 may include the apparatus of example 11 and/or some other examples herein, wherein the processing circuitry is further to: derive a fault coverage metric of the fault class for the IC by combining the fault coverage metrics of the fault class for the corresponding correlated RTL fault group and a fault distribution of the each gate level fault group of the pruned gate level fault list.

Example 15 may include a method for testing an integrated circuit (IC) of an in-vehicle system of a computer-assisted or autonomous driving (CA/AD) vehicle, comprising: performing, with a simulator, RTL fault simulation based on a fault simulation algorithm for a RTL fault group associated with a RTL circuit node of a RTL netlist of the IC, the RTL circuit node corresponding to a gate level circuit element of a gate level netlist of the IC, the RTL fault group corresponding to a gate level fault group of a fault model associated with the gate level circuit element to test the IC for compliance with a functional safety standard for the IC in the in-vehicle system of the CA/AD vehicle; and classifying RTL faults of the RTL fault group by a fault class to provide a fault coverage metric of the fault class for the RTL fault group.

Example 16 may include the method of example 15 and/or some other examples herein, wherein: the fault class includes a detectable fault class, a potentially detectable fault class, or an observable but not detectable fault class; the fault model includes stuck-at-fault, bridging fault, current leak fault, transistor stuck-at-fault, functional fault, memory fault, delay fault, or state transition fault; and the RTL circuit node of the RTL netlist corresponding to the gate level circuit element of the gate level netlist is determined by logic equivalence checking, simulation-based equivalence checking, binary decision diagrams based equivalence checking, or conjunctive normal form satisfiability equivalence checking.

Example 17 may include the method of example 15 and/or some other examples herein, wherein the gate level fault group associated to the gate level circuit element is a first gate level fault group associated to a first gate level circuit element, and the method further comprises: extracting a gate level fault list of the fault model from the gate level netlist of the IC; pruning the gate level fault list to exclude one or more untestable faults to obtain a pruned gate level fault list; classify the pruned gate level fault list to obtain one or more gate level fault groups, wherein the one or more gate level fault groups includes the first gate level fault group associated to the first gate level circuit element, each gate level fault group of the one or more gate level fault groups includes one or more gate level faults associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics; determine, for each gate level fault group of the one or more gate level fault groups associated to a gate level circuit element with a corresponding RTL circuit node, a corresponding correlated RTL fault group associated to the corresponding RTL circuit node, wherein the corresponding correlated RTL fault group includes one or more RTL faults; perform RTL fault simulation based on a fault simulation algorithm for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node; classify a RTL fault in the corresponding correlated RTL fault group by a fault class; and measure a fault coverage metric of the fault class for the corresponding correlated RTL fault group.

Example 18 may include the method of example 17 and/or some other examples herein, further comprising: deriving a fault coverage metric of the fault class for the IC by combining the fault coverage metrics of the fault class for the corresponding correlated RTL fault group and a fault distribution of the each gate level fault group of the pruned gate level fault list.

Example 19 may include the method of example 17 and/or some other examples herein, further comprising: estimating an accuracy of the fault coverage metric for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node for the each gate level fault group associated to the gate level circuit element with the corresponding RTL circuit node; generating additional correlated RTL fault groups for the one or more gate level fault groups based on the estimated accuracy and a threshold; and performing RTL fault simulation based on the fault simulation algorithm for the additional correlated RTL fault groups.

Example 20 may include one or more non-transitory computer-readable media comprising instructions that cause processing circuitry to perform fault simulation of an integrated circuit (IC), in response to execution of the instructions by the processing circuitry, to: extract a gate level fault list of a fault model from a gate level netlist of the IC; prune the gate level fault list to exclude one or more untestable faults to obtain a pruned gate level fault list; classify the pruned gate level fault list to obtain one or more gate level fault groups, wherein each gate level fault group of the one or more gate level fault groups includes one or more gate level faults associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics; determine, for each gate level fault group of the one or more gate level fault groups associated to a gate level circuit element with a corresponding RTL circuit node of a RTL netlist of the IC, a corresponding correlated RTL fault group associated to the corresponding RTL circuit node that includes one or more RTL faults; perform RTL fault simulation based on the fault simulation algorithm for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node; classify a RTL fault in the corresponding correlated RTL fault group by a fault class; and measure a fault coverage metric of the fault class for the corresponding correlated RTL fault group.

Example 21 may include the one or more non-transitory computer-readable media of example 20 and/or some other examples herein, wherein the instructions further cause the processing circuitry, in response to execution of the instructions by the processing circuitry, to: derive a fault coverage metric of the fault class for the IC by combining the fault coverage metrics of the fault class for the corresponding correlated RTL fault group and a fault distribution of the each gate level fault group of the pruned gate level fault list.

Example 22 may include the one or more non-transitory computer-readable media of example 20 and/or some other examples herein, wherein the instructions further cause the processing circuitry, in response to execution of the instructions by the processing circuitry, to: estimate an accuracy of the fault coverage metric for the corresponding correlated RTL fault group associated to the corresponding RTL circuit node for the each gate level fault group associated to the gate level circuit element with the corresponding RTL circuit node; generate additional correlated RTL fault groups for the one or more gate level fault groups based on the estimated accuracy and a threshold; and perform RTL fault simulation based on the fault simulation algorithm for the additional correlated RTL fault groups.

Example 23 may include the one or more non-transitory computer-readable media of example 20 and/or some other examples herein, wherein the gate level netlist of the IC or the RTL netlist of the IC is described with Verilog, VHDL, or a hardware description language; and the fault class includes a detectable fault class, a potentially detectable fault class, or an observable but not detectable fault class.

Example 24 may include the one or more non-transitory computer-readable media of example 20 and/or some other examples herein, wherein: the fault model includes stuck-at-fault, bridging fault, current leak fault, transistor stuck-at-fault, functional fault, memory fault, delay fault, or state transition fault; the fault simulation algorithm includes a serial fault simulation algorithm, a parallel fault simulation algorithm, a deductive fault simulation algorithm, a concurrent fault simulation algorithm, or a differential fault simulation algorithm; and the RTL circuit node of the RTL netlist corresponding to the gate level circuit element of the gate level netlist is determined by logic equivalence checking, simulation-based equivalence checking, binary decision diagrams based equivalence checking, or conjunctive normal form satisfiability equivalence checking.

Example 25 may include the one or more non-transitory computer-readable media of example 20 and/or some other examples herein, wherein the gate level circuit element includes a selected one of a combinatorial logic gate, a flip-flop, a latch, a clock pin of a sequential logic circuit, a scan pin of a sequential logic circuit, a standard cell input pin, or a standard cell output pin.