System and method for enhancing receiver equalization

An information handling system with enhanced receiver equalization may include a processing unit with a dual in-line memory module (DIMM) controller. The DIMM controller is connected to a first DIMM and a second DIMM by a communication channel. A basic input/output system is configured to set an equalization of a data signal on the communication channel by applying a first equalization to a Nyquist frequency that is associated with a data rate of the data signal and by applying a second equalization to a standing wave reflection frequency that is associated with an additional loading in the communication channel. The additional loading may be due to presence of another DIMM in the same communication channel.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to enhancement of a receiver equalization.

BACKGROUND

SUMMARY

An information handling system may include a processing unit with a dual in-line memory module (DIMM) controller and hosts a basic input/output system (BIOS). The DIMM controller is connected to a first DIMM and a second DIMM by a communication channel. The BIOS is configured to set an equalization of a data signal on the communication channel by applying a first equalization to a Nyquist frequency that is associated with a data rate of the data signal and by applying a second equalization to a standing wave reflection frequency that is associated with a trace length between the first DIMM and the second DIMM.

DETAILED DESCRIPTION

Information handling system100can include devices or modules that embody one or more of the devices or modules described above. Information handling system100includes processors102and104, a chipset110, a memory120, a graphics adapter130, a basic input and output system/extensible firmware interface (BIOS/EFI) module140, a disk controller150, a disk emulator160, an input/output (I/O) interface170, and a network interface180. Processor102is connected to chipset110via processor interface106, and processor104is connected to the chipset via processor interface108. Memory120is connected to chipset110via a memory bus122. Graphics adapter130is connected to chipset110via a graphics interface132, and provides a video display output136to a video display134. In a particular embodiment, information handling system100includes separate memories that are dedicated to each of processors102and104via separate memory interfaces. An example of memory120includes random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/EFI module140, disk controller150, and I/O interface170are connected to chipset110via an I/O channel112. An example of I/O channel112includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. Chipset110can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer System Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/EFI module140includes BIOS/EFI code operable to detect resources within information handling system100, to provide drivers for the resources, initialize the resources, and access the resources.

Disk controller150includes a disk interface152that connects the disk controller to a hard disk drive (HDD)154, to an optical disk drive (ODD)156, and to disk emulator160. An example of disk interface152includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) interface such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator160permits a solid-state drive164to be connected to information handling system100via an external interface162. An example of external interface162includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive164can be disposed within information handling system100.

Network interface180represents a NIC disposed within information handling system100, on a main circuit board of the information handling system, integrated onto another component such as chipset110, in another suitable location, or a combination thereof. Network interface device180includes network channels182and184that provide interfaces to devices that are external to information handling system100. In a particular embodiment, network channels182and184are of a different type than peripheral channel172and network interface180translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels182and184includes InfiniBand™ channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels182and184can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

For the purposes of this disclosure, an example information handling system is a server. The server in turn may include other information handling systems. An example information handling system in a server may be a CPU device including a CPU in communication with one or more memory devices, such as dual in-line memory modules (DIMMs). A DIMM is a memory for data storage that includes a series of dynamic random-access memory integrated circuits. There has been a proliferation of the number of individual DIMMs supported by the CPU. As a result, there has been an increase in the connection length across sets of DIMMs such that the CPU to DIMM connection length increasingly varies. In addition, communication speeds between CPUs and DIMMs are increasing, increasing the difficulty of data transfer due to consequent problems with signal acquisition between DIMM and CPU.

Furthermore, there is also variance among DIMMs because different DIMMs may be manufactured by different manufacturers and used in a single information handling system or model of information handling system. For example, to differentiate DIMMs, DIMM manufacturers sometimes go beyond a DIMM specification to design DIMMs. This could be in terms of raw card improvement or printed circuit board (PCB) material improvement or silicon process improvement, for example. This is usually evident from the laboratory testing on DIMM products. For a given DIMM capacity and rank type, a DIMM manufactured by one DIMM manufacturer is better or a DIMM manufactured by another DIMM manufacturer is worse.

To communicate with DIMMs across all the above variances, equalization of communication channels may be ramped up to maximum to ensure signal and communication acquisition between the CPU and the DIMMs. Thus, the equalization settings in the CPU and the DIMMs may be static, and the equalization settings may be the same for each DIMM. That is, there may be a fixed equalization parameter indiscriminately applied across all DIMMs for the corresponding communication channels. The equalization of the communication channel may include the optimal settings of a transmitter filter in or a receiver filter to compensate for the loss in signal during data transfer. Optimal equalization without over compensating the signal will help both signal integrity and result in power savings. Furthermore, over-equalization of the communication channel relative to an individual DIMM may also diminish signal integrity for signal acquisition. Thus, the signal eye diagram of communications between the CPU and individual DIMM is sub-optimal for both over and under compensation.

FIG. 2shows a set of plots200a-200dindicating various eye diagrams for equalization between a CPU and individual DIMM. In plot200a, there is no equalization of the communication channel between the CPU and DIMM, and the eye diagram shows a small squinting eye suboptimal for signal acquisition. In plot200b, there is under equalization of the communication channel between the CPU and DIMM, and the eye diagram shows a small eye suboptimal for signal acquisition. In plot200c, there is over equalization of the communication channel between the CPU and DIMM, and the eye diagram shows a compressed eye suboptimal for signal acquisition. In plot200d, there has been an optimized equalization of the communication channel between CPU and DIMM, and the eye diagram shows a wide eye optimal for signal acquisition.

In an embodiment, the equalization settings of the individual communication channel between the CPU and the individual DIMM may be based on individual DIMM characteristics or properties. For example, information such as DIMM serial presence detect (SPD) information may indicate the IO voltage rating, loading capacity, DIMM type, and other DIMM properties. In this example, the SPD information may be stored on the individual DIMM and accessed and used to set the equalization settings for the communication channel between the CPU and the DIMM. In another embodiment, the equalization settings of the individual communication channel between the CPU and the individual DIMM may be based upon presence of standing wave reflections that include unwanted signals due to an impedance mismatch in the connecting communication channel. For example, the impedance mismatch can be generated by a discontinuity in the connecting communication channel. In this example, the discontinuity may be due to presence of another DIMM that can create an additional loading in the same communication channel.

An example CPU DIMM storage system300is shown inFIG. 3. System300includes a CPU310that may be in communication with a first DIMM330and a second DIMM350over a communication channel321. CPU310includes a core set311which is the set of processor cores of CPU310. One or more processor cores of the core set311may host a Basic Input/Output System (BIOS)312of the CPU310. The BIOS is firmware that can be used to perform hardware initialization during the booting process and provides an abstraction layer for the hardware. CPU310includes a CPU circuitry313and a memory controller such as a DIMM controller314. DIMM controller314includes a first transmitter component (TX)316and a first receiver component (RX)318for bidirectional communications with the first DIMM330and/or second DIMM350. The first TX316and the second RX318may utilize a first TX switch326and a first RX switch328, respectively, to connect with the communication channel321. The first TX316may further include transmitter modules such as a pre-emphasis component that may be adjusted to include one of pre-emphasis settings that can be supported by the first TX. The first RX318may include a first continuous time linear equalization (CTLE) module320including a Nyquist frequency (fN) control knob322and standing wave frequency (fSW) control knob324. The fNcontrol knob322and the fSWcontrol knob324may implement equalization settings during data reception by the first RX318. The CTLE module320may be one of the receiver modules in the first RX318. The other receiver modules of the first RX318may include automatic gain control (AGC) and decision feedback equalization (DFE) modules. Further information on the details and operation of the CTLE, AGC, and the DFE modules in a high speed serial channel may be found in U.S. Pat. No. 10,298,421, which is incorporated herein by reference in its entirety.

The first DIMM330may include a second TX336, a second RX338, and a memory345. The second TX336and the second RX338may utilize a second TX switch346and a second RX switch348, respectively, to connect with the communication channel321. The second TX336may further include transmitter modules such as the de-emphasis component that may be adjusted to include one of de-emphasis settings that can be supported by the second TX. The second RX338may include a CTLE module340including fNcontrol knob342and a fSWcontrol knob344. The fNcontrol knob342and the fSWcontrol knob344may implement equalization settings during data reception by the second RX338. The CTLE module320may be one of the receiver modules in the first RX318. The other receiver modules of the first RX318may include AGC and DFE modules. Similarly, the second DIMM350may include a third TX356, a third RX358, and a memory365. The third TX356and the third RX358may utilize a third TX switch366and a third RX switch368, respectively, to connect with the communication channel321. The third TX356may further include transmitter modules while the third RX358may include a CTLE module360including a fNcontrol knob362and a fSWcontrol knob364. The fNcontrol knob362and the fSWcontrol knob364may implement equalization settings during data reception by the third RX358.

The first DIMM330and the second DIMM350may form a DIMM pair and are connected to the CPU310generally, and to the DIMM controller314particularly, by the communication channel321. CPU310may access the first DIMM330and the second DIMM350over the communication channel321with the communication channel extended to a trace length370between the first DIMM330and the second DIMM350. That is, the length370may include the physical length of a conductive trace between a first point372at the side of the first DIMM330and a second point374at the side of the second DIMM350. Communications between the CPU310and the first and second DIMMs may be according to the double data rate fourth-generation (DDR4) standard, double data rate fifth-generation (DDR5) standard, or variants thereof.

The memory345may be an erasable programmable read-only memory (EPROM) or other non-volatile memory that stores SPD information347for the first DIMM330. Similarly, the memory365may be an EPROM or other non-volatile memory that stores SPD information367for the second DIMM350. When the storage system300is part of a server, a server baseboard management controller (BMC)380may be connected to memories345and365through channels382and384, respectively. The BMC380may access the SPD information for the first DIMM330and the second DIMM350in memories328and338, respectively, and provide the obtained SPD information to the CPU310and particularly, the BIOS312. With the obtained SPD information, the BIOS312and/or the DIMM controller314may configure each TX and RX of the DIMM controller314, first DIMM330, and the second DIMM350to provide a desired equalization of the communication channel321based on the individual SPD information.

In an embodiment, the CPU310may transmit data to the first DIMM330by closing the first TX switch326and the second RX switch348, and leaving the rest of the TX and RX switches disconnected from the communication channel321. In this embodiment, the hanging second DIMM350may create discontinuity and additional loading that generate standing wave reflections in the same communication channel321. The created discontinuity produces the impedance mismatch that may correspond to the length370of the communication channel between the first DIMM330and the second DIMM350. In this case, the equalization settings at the CTLE module340of the first DIMM330may include amplification of a frequency of interest between the CPU310and the first DIMM330, and suppression of the standing wave reflections between the first DIMM330and the second DIMM350. The amplification of frequency of interest may be implemented by adjusting the fNknob342while the suppression of the standing wave reflections may be performed by varying settings of the fSWknob344. The equalization settings in the first DIMM330may be performed during initialization of the information handling system or upon connecting of the first DIMM330to the CPU310. The transmission of data by the CPU310to the first DIMM330may represent one half of a bi-directional serial data link for communicating data. The other half of the bi-directional data link may include, for example, the first DIMM330transmitting data back to the CPU310.

The BIOS312may set up the equalization settings of the CTLEs320,340, and360based upon predetermined amount of standing wave reflections in the system300. In an embodiment and in the case of data transfer from the CPU310to the first DIMM330only, a data signal frequency response of the communication channel321may include the frequency of interest and the standing wave reflection in the same communication channel. The frequency of interest may include the Nyquist frequency which is associated with data rate in the communication channel and can include a value of half of a sampling rate. The standing wave reflection includes unwanted portions of the data signal due to presence of the second DIMM350. The frequency of interest includes a first set of signal components that are within a particular bandwidth at the Nyquist frequency of the data signal. The unwanted portion includes a second set of signal components that are within a different bandwidth at a resonant frequency of the standing wave reflection. The resonant frequency or standing wave reflection frequency includes the unwanted signals due to presence of additional loading in the same communication channel321. For example, the additional loading may be based from portions of the communication channel321that connects the first point372to second point374. In this example, the length370of the communication channel321may generate the discontinuity or the additional loading in the same communication channel321.

In some embodiments, the CPU310and particularly the DIMM controller314may be configured to determine the Nyquist frequency and the resonant frequency of the data signal frequency response for the data transfer between the CPU310and the first DIMM330. In this embodiment, the fNknob342and fSWknob244may be preconfigured to include equalization settings based upon the determined Nyquist frequency and the determined resonant frequency, respectively, in the communication channel321. In another embodiment, the CPU310characterizes the communication channel321and based upon the characterization, the fNknob342and fSWknob244may be dynamically adjusted. In another embodiment, the configuration of the fNknob342and fSWknob244may be further based upon the obtained SPD347. In these embodiments, the configuration of the fNknob342may amplify the determined Nyquist frequency while the configuration of the fSWknob342may suppress the standing wave reflection frequency. The amplification and the suppression may be implemented using a transfer function of the CTLE340.

The transfer function of the CTLE340may include an application of a first equalization and a second equalization to the signal components at the Nyquist frequency and the resonant frequency, respectively. The first equalization may be used to amplify the first set of signal components within a particular bandwidth at the Nyquist frequency. The second equalization may be used to suppress the second set of signal components of a different bandwidth and around the resonant frequency. For example, the first equalization may include a first set of poles and zero that coincide with the Nyquist frequency. In this example, the transfer function of the CTLE340to implement the first equalization is given in equation 1 (Eq. 1) below:

H⁡(s)=(swz+1)(swp⁢1+1)*(swp⁢2+1)⁢AD⁢⁢C(1)
where H(s) is the transfer function of the CTLE corresponding to the first equalization to amplify the first set of signal components within a certain bandwidth at Nyquist frequency, wzis a first zero that can provide high-frequency boost to open signal eye, wp1is the first pole that can provide a peak of signal eye, wp2is the second pole that can limit the bandwidth, ADCincludes an amplification gain, and s is a complex frequency.

From Eq. 1, the numerator polynomial can be set to zero to determine the root wz. Similarly, the denominator polynomial can be set to zero to determine the poles wp1and wp2. In an embodiment, the first set of roots wz, wp1and wp2coincide with the Nyquist frequency to amplify the first set of signal components. In this embodiment, the first set of roots includes the first set of poles and zero for the first equalization. In other embodiments, the amplification gain ADCis adjusted to minimize power consumption of the storage system300. In this other embodiment, the first set of roots wz, wp1and wp2may be adjusted correspondingly to generate the same amount of first equalization but with a lower amplification gain.

To suppress the second set of signal components at the resonant frequency, a second set of poles and zero for the second equalization may be added to the first set of poles and zero of the first equalization. For example, the CTLE340may utilize equation 2 (Eq. 2) below to obtain a new transfer function for the equalization of the communication channel321:

From Eq. 2, the numerator polynomial of the second part is set to zero to determine the root wzdof the second equalization. Similarly, the denominator polynomial of the second part is set to zero to determine the roots wpd1and wpd2of the second equalization. In an embodiment, the second set of roots wzd, wpd1and wpd2suppress the standing wave reflection signal by decreasing the magnitude of the signal components at the standing wave reflection frequency. In this embodiment, the second set of roots includes the second set of poles and zero for the second equalization. The second set of poles and zero may coincide with the standing wave reflection frequency to suppress the standing wave reflection frequency.

In an embodiment, the resonant frequency of the standing wave reflection during the data transfer between the CPU310and the first DIMM330can be derived using equation 3 (Eq. 3) below:

f=c∈r⁢14*Ld⁢⁢2⁢⁢d(3)
where f is the resonant frequency of the communication channel321when the third TX switch366and third RX switch368are left open while the first TX switch326and the second RX switch348switches are closed, C is speed of light, ϵris dielectric constant, and Ld2d is physical length or the length370between the first DIMM330and the second DIMM350. With the obtained resonant frequency, the DIMM controller314may use the fSWknob344to suppress the standing wave reflection frequency. For example, each of the fNknob342and the fSWknob344can support21equalizations setting or levels, which each prescribe a different amount of equalization from 0 dB to 10 dB, in 0.5 dB steps. In this example, the fSWknob344may be adjusted to the level that corresponds to the determined resonant frequency in Eq. 3.

FIG. 4shows a block diagram of the CPU DIMM storage system400including the CPU310that may be configured to transfer data to the second DIMM350. The operation and components of the system400and the system300are the same except that the system400may be configured to have the first TX switch326and the third RX switch368turned ON while the rest of the first switch RX328, second TX switch346, second RX switch348, and the third TX switch366may be left in open circuit. Furthermore, a new communication channel length470between a first point472and a second point474may be used to calculate the resonant frequency using Eq. 3.

In an embodiment and for the data transfer between the CPU310and the second DIMM350, the equalization settings of the CTLE360may be configured based upon the impedance mismatch in the communication channel321. The impedance mismatch, for example, may be derived by determining the resonant frequency based on the new length470. In this example, the DIMM controller314may use the fNknob362and the fSWknob364to amplify the Nyquist frequency and to suppress the determined resonant frequency, respectively.

In other embodiments, the amplification gain of the CTLE360may be adjusted based upon the determined resonant frequency. In this embodiment, the adjustment of the amplification gain may be combined with the variation in the settings of the fNknob362and the fSWknob364to obtain the desired equalization setting. In another embodiment such as where the second DIMM350is transmitting data back to the CPU310, the fNknob322and the fSWknob324of the CTLE320may be adjusted to configure equalization settings of the receiving first RX318.

FIG. 5shows a block diagram of the CTLE340including an equivalent transfer function550. In an embodiment and during the data transfer from the CPU310to the first DIMM330, the CTLE340may receive an input data signal510from the communication channel321. In this embodiment, the received data signal510undergoes the transfer function550to generate an output signal520, and the output signal may be further processed by another receiver module such as the AGC. The CTLE340includes a first portion502that is cascaded to a second portion504. The first portion502and the second portion504may be configured to implement the first equalization on the Nyquist frequency and the second equalization on the standing wave reflection frequency, respectively. For example, the first portion502includes the fNknob342that may be configured to adjust the resistor (Rs1) and capacitor (Cs1) components to generate the first set of roots wz, wp1and wp2that coincide with the Nyquist frequency. In this example, the first portion502of the receiver CTLE module500may be used to amplify the first set of signal components at the Nyquist frequency. Similarly, the second portion504includes the fSWknob344that may be configured to adjust a separate resistor (Rs2) and another capacitor (Cs2) components to generate the second set of roots wzd, wpd1and wpd2for suppressing of the signal components at and around the standing wave reflection frequency. By cascading the first portion502to the second portion504, the output530generates improved signal acquisition of the data signal in the same communication channel321. Approximations of the values for the first set of roots and the second set of roots are shown under the transfer function equation. The approximated values may be used by the fNknob322and the fSWknob324to adjust the step or level of the equalization settings.

In other embodiments, the first portion502and the second portion504are integrated as a single component to minimize number of components in the circuit.

FIG. 6shows a set of frequency response graph600of the data signal during the data transfer between the CPU310and the first DIMM330. The graph600illustrates a first frequency response graph610that includes the ideal no impedance mismatches in the communication channel321. That is, the graph610only includes a Nyquist frequency612with a bandwidth614. In this case, only the first equalization may be utilized by the CTLE340to amplify the Nyquist frequency612. The first equalization includes the first set of roots wp1and wp2, and wzthat coincide with the Nyquist frequency612. The zero wzmay be used to increase gain |H| while the poles wp1and wp2may be used to obtain the peak value and to limit the bandwidth614, respectively. In some embodiments, the amplified signal components within the bandwidth614include the frequency of interest for purposes of improving the signal acquisition.

The graph600further shows a second frequency response graph620including the Nyquist frequency612, a resonant frequency622, and a bandwidth624. For example, the resonant frequency622may be generated by the length370of the communication channel321. The length370includes the physical length of the communication channel321that was left hanging due to the open third switch368. In this example, the combination of the first and second equalizations may be utilized by the CTLE340to improve signal acquisition. The first equalization includes the first set of roots wp1and wp2, and wzthat coincide with the Nyquist frequency612to amplify the frequency of interest. The second equalization includes the second set of roots wpd1and wpd2, and wzdthat may be used to suppress the signal components at and around the standing wave reflection frequency622. The zero wzdmay be used to decrease the gain |H| while the poles wp1and wp2may be used to obtain the peak value and to define the bandwidth624, respectively. In some embodiments, the suppressed signal components within the bandwidth624include the unwanted standing wave reflections for purposes of improving the signal acquisition

FIG. 7shows a flowchart of a process700for setting the CTLE receiver module of the receiving DIMM, starting at block702. At block704, the BIOS312determines the Nyquist frequency to be used in the communication channel321. For example and for the data transfer between the CPU310and the first DIMM330, the BIOS312may determine the Nyquist frequency to be used as the data rate in the data transfer. At block706, the BIOS determines the standing wave reflection frequency in the communication channel. For example, the standing wave reflection frequency may be calculated using Eq. 3. At block708, the BIOS sets a first equalization to amplify the Nyquist frequency. For example, the first equalization includes the first part of the Hnew(s)in Eq. 2. At block710, the BIOS sets a second equalization to suppress the determined standing wave reflection frequency. For example, the second equalization includes the second part of the Hnew(s)in Eq. 2. At block712, the DIMM controller facilitates channel equalization by applying the first equalization to the Nyquist frequency and by applying the second equalization to the determined standing wave reflection frequency.

Processes700may be performed at an initialization of an information handling system such as a server including the CPU with DIMMs or upon connecting one or more DIMMs to the CPU. Thus there may be dynamic and individual setting of communication channel equalization of individual communication channels.