Method and apparatus for self-aligned MOS patterning

A method of forming a thin film stack on a substrate, wherein the thin film stack includes at least a polysilicon layer and an oxide layer; forming a hardmask layer on the thin film stack; forming an anti-reflective coating (ARC) layer on the hardmask layer; patterning the ARC layer; etching the hardmask layer using the patterned ARC layer as a mask; and etching the thin film stack using the hardmask layer as a mask.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor device fabrication, and in particular to lithography patterning of thin film stacks for lithography using light having a wavelength of 193 nm or less.

2. Discussion of Related Art

Present semiconductor fabrication techniques may be used to generate single electrode transistor gates using 193 nm wavelength lithography technology or dual electrode flash memory transistor gates using 248 nm wavelength lithography technology.

FIG. 1illustrates a flash memory transistor gate stack. The flash memory gate stack is formed on substrate100. The gate stack of the flash memory transistor consists of a control gate electrode layer108deposited over an inter-electrode dielectric106, over a floating gate layer104, over the gate dielectric102, on a substrate100. Source/drain spacer liner dielectric140is formed on either side of the flash memory gate stack. Source/drain spacer dielectric142is formed on either side of the gate stack on top of the source/drain spacer liner dielectric140.

FIG. 2illustrates the flash memory gate stack after the resist has been patterned using light280having a wavelength of 248 nm or greater. The thickness of the resist214is bounded by etch resistance and patterning resolution. The flash transistor gate is etched using a Self-Aligned MOS (SAMOS) process. The SAMOS process allows all layers of the flash transistor gate stack to be etched using the resist as a mask, including the gate dielectric202, the floating gate electrode204, the interelectrode dielectric206, and the control gate electrode208.

To achieve high resolution patterning with 193 nm (or less) lithography for flash transistors, a change in resist formulation is required. The resist formulation for 193 nm lithography compromises the ability of the resist to withstand the environment required to etch the SAMOS flash gate stack, and is not stable in etch chemistries. Thus, it is undesirable to use resist as a mask to etch the flash SAMOS gate stack using 193 nm or less lithography.

Hardmask materials that consist of similar elements to those found in the inter-poly dielectric layer, such as a nitride layer, are also undesirable for use as a SAMOS mask. These materials may be compromised during the etch process. Furthermore, the removal of a hardmask consisting of a similar material as the inter-poly dielectric layer may compromise the dielectric and lead to device failure.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following description, numerous specific details are set forth, such as exact process steps, in order to provide a through understanding of the present invention. It will be apparent, however, that these specific details need not be employed to practice the present invention. In other instances, well known components or methods have not been described in detail in order to avoid unnecessarily obscuring the present invention.

FIG. 3is a flow diagram300which illustrates a process in accordance with one embodiment of the present invention. Flow diagram300illustrates a general method of patterning and etching a thin film stack using a hardmask layer.

First, as shown in block302, a thin film stack is formed. The thin film stack may include at least a poly silicon layer and an oxide layer on a substrate. In one embodiment, the thin film stack may be a flash memory gate stack. For simplicity, the thin film stack describe herein and illustrated inFIGS. 1,2, and4–10is a flash memory gate stack, however, any thin film stack containing at least a polysilicon layer and an oxide layer may be substituted in other embodiments of the present invention.

FIG. 4illustrates an exemplary flash memory gate stack420. A gate dielectric layer402is grown or deposited on substrate400. Substrate400may be a silicon substrate. The substrate may be comprised of a material other than silicon, including, but not limited to, materials such as gallium arsenide, or silicon on insulator (SOI) substrates. In one embodiment, the gate dielectric may comprise a silicon oxide or silicon oxynitride. After the gate oxide layer402is formed, the floating gate electrode layer404is deposited. The floating gate layer404may comprise an n-type polysilicon layer. Next, the interelectrode dielectric406is formed. The interelectrode dielectric406may comprise an ONO (oxide-nitride-oxide) layer. Finally, the control gate electrode layer408is formed. The control gate electrode408may comprise polysilicon.

Next, as illustrated inFIG. 3, block304, a hardmask layer is formed over the thin film stack. The hardmask layer is illustrated inFIG. 4.FIG. 4shows the hardmask layer410formed over the top surface of thin film stack420, which in one embodiment may be a flash memory gate stack. The hardmask material must be resistant to both common polysilicon etch chemistries as well as oxide etch chemistries. The hardmask material must also have optical properties with a favorable extinction coefficient for 193 nm wavelength light. For future lithography nodes, the hardmask material must have optical properties that are favorable for light having wavelengths of less than 193 nm. In one embodiment, the hardmask layer may be a carbon-based layer, and may comprise a pure amorphous carbon layer. Applied Materials® Advanced Patterning Film™ (APF™) may be used for the hardmask. The hardmask layer may be formed to a thickness of 1000 to 3000 Å.

After the hardmask layer is formed, an anti-reflective coating (ARC) layer is formed over the hardmask layer, as illustrated inFIG. 3, block306.

FIG. 4illustrates the ARC layer412formed over the top surface of the hardmask layer. The ARC layer may be comprised of silicon dioxide, silicon oxynitride or a composite thereof. The ARC layer reduces undesirable light reflections by phase shift cancellation, which is dependent upon the extinction coefficient and the thickness of the film. The ARC material must have optical properties with a favorable extinction coefficient for 193 nm lithography. For future lithography nodes, the ARC material must have optical properties that are favorable for light having wavelengths of less than 193 nm. The ARC layer may be formed to a thickness of 100 to 500 Å.

Using photoresist, the ARC layer is then patterned to define the flash gate, as illustrated inFIG. 3, block308. The photoresist may be patterned using standard 193 nm wavelength light,480, as shown inFIG. 5. Lithography using light having a wavelength of less than 193 nm may also be used.

FIG. 5illustrates the thin film stack after the ARC layer412has been patterned with photoresist414. The resist formulation must be appropriate for 193 nm lithography. Resist414may be formed to a thickness of 2000 to 5000 Å. The resist thickness may be optimized for patterning resolution only, and does not require etch resistance consideration. Standard etch chemistries may be used to define the pattern in the ARC. Since the etch chemistry used typically will have a high selectivity to photoresist, this is also the pattern transfer step for the lithography. Because both the resist414and the hardmask410may be comprised of carbon, the ARC layer412prevents the hardmask410from being breached during the etch process.

After the ARC layer has been patterned, the hardmask layer and the thin film stack may be etched, as set forth inFIG. 3, block310.

FIG. 6illustrates the hardmask etch. The patterned ARC layer412is used as a mask to etch the hardmask layer410. A standard etch chemistry may be used to etch the hardmask. In one embodiment, the hardmask may be etched using an oxygen and argon etch chemistry. Much of the resist414may be removed by the hardmask etch process. This is because both the hardmask and the resist are composed of carbon based materials. An etch chemistry which etches the hardmask will also etch the resist.

After the pattern has been transferred from the ARC layer412to the hardmask layer410, the hardmask layer may be used as a mask to etch the remainder of the thin film stack because the hardmask material is selective to both the polysilicon and oxide etch chemistries.

FIG. 7illustrates the control gate etch. Hardmask410is used as a mask to pattern the control gate408. The hardmask is selective to the polysilicon etch chemistry, and remains intact after the control gate is etched.

The ARC layer needs to remain intact only for the duration of the hardmask etch, since the hardmask has a high selectivity to both the polysilicon and oxide etch chemistries. The ARC layer412may be completely removed by the first polysilicon etch process.

FIG. 8illustrates the interelectrode dielectric etch. Hardmask410is used as a mask to pattern the interelectrode dielectric406. The hardmask is selective to the dielectric etch chemistry, and remains intact after the interelectrode dielectric is etched. If any portion of the ARC layer remains on the top surface of the hardmask410after the first polysilicon etch process, it will be completely removed during the interelectrode dielectric etch. This is because the ARC layer and the interelectrode dielectric typically have similar physical properties and may be composed of similar materials.

FIG. 9illustrates the thin film stack after all layers have been etched, including the control gate408, interelectrode dielectric406, floating gate404, and gate dielectric402. The hardmask410is used as a mask for etching each of the layers. All layers may be etched during a single manufacturing step in the same chamber, however different etch chemistries may be required to etch different layers. The hardmask used to pattern each of the layers remains intact after the etch process is complete.

After the thin film stack has been etched, the hardmask layer may be removed. A conventional cleaning process, such as a standard resist removal process, may be used to volatize the hardmask material and prepare the surface for further processing. In one embodiment, the hardmask may be removed using an oxygen plasma ash.FIG. 10illustrates the thin film stack420after all layers have been etched and after the hardmask layer has been removed. The remaining etched thin film layers may comprise a flash memory gate stack, including control gate408, interelectrode dielectric406, floating gate404, and gate dielectric402.

The present invention may be implemented with various changes and substitutions to the illustrated embodiments. For example, the present invention may be implemented on various types of thin film stacks having different heights and comprising different materials. The present invention is not limited only to flash memory gate stacks. Furthermore, the present invention may be implemented on flash memory gates whose gate stacks vary from those described herein. For example, a flash memory gate stack may contain additional or different layers than those described herein.

Although specific embodiments, including specific parameters, methods, and materials have been described, it will be readily understood by those skilled in the art and having the benefit of this disclosure, that various other changes in the details, materials, and arrangements of the materials and steps which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of this invention as expressed in the subjoined claims.