User detection and recognition for electronic devices

In one example an electronic device comprises a proximity detector, a camera, and a controller, comprising logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that an object approaching the electronic device is within a predetermined distance while the electronic device is in a first low-power state, and in response to the indication, to activate the camera on the electronic device while the electronic device remains in a low-power state and determine whether an image input to the camera is a human while the electronic device remains in a low-power state. Other examples may be described.

BACKGROUND

The subject matter described herein relates generally to the field of electronic devices and more particularly to user detection and recognition for electronic devices.

Electronic devices such as laptop computers, tablet computing devices, electronic readers, mobile phones, and the like may enter a low-power state when unused for a period of time and then recover to a full power state when a user initiates use of the electronic device. Some electronic devices include sensors such as proximity sensors and/or cameras. Accordingly, techniques which enable an electronic device incorporate inputs from such sensors for user detection and recognition of the electronic device may find utility, e.g., in transitioning an electronic device between low-power states and full-power states, or vice-versa.

DETAILED DESCRIPTION

Described herein are exemplary systems and methods to implement a user detection and recognition in electronic devices. In the following description, numerous specific details are set forth to provide a thorough understanding of various examples. However, it will be understood by those skilled in the art that the various examples may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the particular examples.

As described above, it may be useful to provide electronic devices with techniques for user detection and recognition which may be used to implement techniques for transitioning an electronic device between low-power states and full-power states, or vice-versa. The subject matter described herein addresses these and other issues by providing user detection and recognition algorithms which may be implemented in logic on one or more controllers of the electronic device. In some examples, an electronic device includes one or more sensors, e.g., a proximity sensor and one or more cameras. Logic associated with the electronic device receives, from the proximity sensor, an indication that an object approaching the electronic device is within a predetermined distance while the electronic device is in a first low-power state, and in response to the indication, to activate the camera on the electronic device; and transition the electronic device from the first low-power state to a second low-power state. Additional logic may evaluate image inputs to the camera to determine whether the object(s) detected by the proximity sensor are human and/or an authorized user of the electronic device and may respond by placing the electronic device into a higher power state and/or an operating state

Additional features and operating characteristics of the user recognition and of electronic devices are described below with reference toFIGS. 1-10.

FIG. 1is a schematic illustration of an electronic device100which may be adapted to include user detection and recognition in accordance with some examples. In various examples, electronic device100may include or be coupled to one or more accompanying input/output devices including a display, one or more speakers, a keyboard, one or more other I/O device(s), a mouse, a camera, or the like. Other exemplary I/O device(s) may include a touch screen, a voice-activated input device, a track ball, a geolocation device, an accelerometer/gyroscope, biometric feature input devices, and any other device that allows the electronic device100to receive input from a user.

The electronic device100includes system hardware120and memory140, which may be implemented as random access memory and/or read-only memory. A file store may be communicatively coupled to electronic device100. The file store may be internal to electronic device100such as, e.g., eMMC, SSD, one or more hard drives, or other types of storage devices. Alternatively, the file store may also be external to electronic device100such as, e.g., one or more external hard drives, network attached storage, or a separate storage network.

System hardware120may include one or more processors122, graphics processors124, network interfaces126, and bus structures128. In one embodiment, processor122may be embodied as an Intel® Atom™ processors, Intel® Atom™ based System-on-a-Chip (SOC) or Intel® Cor2 Duo® or i3/i5/i7 series processor available from Intel Corporation, Santa Clara, Calif., USA. As used herein, the term “processor” means any type of computational element, such as but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processor or processing circuit.

Graphics processor(s)124may function as adjunct processor that manages graphics and/or video operations. Graphics processor(s)124may be integrated onto the motherboard of electronic device100or may be coupled via an expansion slot on the motherboard or may be located on the same die or same package as the Processing Unit.

In one embodiment, network interface126could be a wired interface such as an Ethernet interface (see, e.g., Institute of Electrical and Electronics Engineers/IEEE 802.3-2002) or a wireless interface such as an IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standard for IT-Telecommunications and information exchange between systems LAN/MAN-Part II: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, 802.11G-2003). Another example of a wireless interface would be a general packet radio service (GPRS) interface (see, e.g., Guidelines on GPRS Handset Requirements, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).

Bus structures128connect various components of system hardware128. In one embodiment, bus structures128may be one or more of several types of bus structure(s) including a memory bus, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, 11-bit bus, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), and Small Computer Systems Interface (SCSI), a High Speed Synchronous Serial Interface (HSI), a Serial Low-power Inter-chip Media Bus (SLIMbus®), or the like.

Electronic device100may include an RF transceiver130to transceive RF signals, a Near Field Communication (NFC) radio134, and a signal processing module132to process signals received by RF transceiver130. RF transceiver may implement a local wireless connection via a protocol such as, e.g., Bluetooth or 802.11X. IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standard for IT-Telecommunications and information exchange between systems LAN/MAN—Part II: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, 802.11G-2003). Another example of a wireless interface would be a WCDMA, LTE, general packet radio service (GPRS) interface (see, e.g., Guidelines on GPRS Handset Requirements, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).

Electronic device100may further include one or more input/output interfaces such as, e.g., a keypad136and a display138. In some examples electronic device100may not have a keypad and use the touch panel for input.

Memory140may include an operating system142for managing operations of electronic device100. In one embodiment, operating system142includes a hardware interface module154that provides an interface to system hardware120. In addition, operating system140may include a file system150that manages files used in the operation of electronic device100and a process control subsystem152that manages processes executing on electronic device100.

Operating system142may include (or manage) one or more communication interfaces146that may operate in conjunction with system hardware120to transceive data packets and/or data streams from a remote source. Operating system142may further include a system call interface module144that provides an interface between the operating system142and one or more application modules resident in memory130. Operating system142may be embodied as a UNIX operating system or any derivative thereof (e.g., Linux, Android, etc.) or as a Windows® brand operating system, or other operating systems.

In some examples an electronic device may include a controller170, which may comprise one or more controllers that are separate from the primary execution environment. The separation may be physical in the sense that the controller may be implemented in controllers which are physically separate from the main processors. Alternatively, the trusted execution environment may logical in the sense that the controller may be hosted on same chip or chipset that hosts the main processors.

By way of example, in some examples the controller170may be implemented as an independent integrated circuit located on the motherboard of the electronic device100, e.g., as a dedicated processor block on the same SOC die. In other examples the trusted execution engine may be implemented on a portion of the processor(s)122that is segregated from the rest of the processor(s) using hardware enforced mechanisms

In the embodiment depicted inFIG. 1the controller170comprises a processor172, a memory module174, a state manager176, and an I/O interface178. In some examples the memory module174may comprise a persistent flash memory module and the various functional modules may be implemented as logic instructions encoded in the persistent memory module, e.g., firmware or software. The I/O module178may comprise a serial I/O module or a parallel I/O module. Because the controller170is separate from the main processor(s)122and operating system142, the controller170may be made secure, i.e., inaccessible to hackers who typically mount software attacks from the host processor122. In some examples portions of the state manager176may reside in the memory140of electronic device100and may be executable on one or more of the processors122.

FIG. 2is a schematic illustration of another embodiment of an electronic device200which may be adapted to implement user detection and recognition, according to embodiments. In some embodiments electronic device210may be embodied as a mobile telephone, a personal digital assistant (PDA), a laptop computer, or the like. Electronic device200may include an RF transceiver220to transceive RF signals and a signal processing module222to process signals received by RF transceiver220.

RF transceiver220may implement a local wireless connection via a protocol such as, e.g., Bluetooth or 802.11X. IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standard for IT-Telecommunications and information exchange between systems LAN/MAN-Part II: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, 802.11G-2003). Another example of a wireless interface would be a general packet radio service (GPRS) interface (see, e.g., Guidelines on GPRS Handset Requirements, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).

Electronic device200may further include one or more processors224and a memory module240. As used herein, the term “processor” means any type of computational element, such as but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processor or processing circuit. In some embodiments, processor224may be one or more processors in the family of Intel® PXA27x processors available from Intel® Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used, such as Intel's Itanium®, XEON™, ATOM™, and Celeron® processors. Also, one or more processors from other manufactures may be utilized. Moreover, the processors may have a single or multi core design.

In some embodiments, memory module240includes random access memory (RAM); however, memory module240may be implemented using other memory types such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Memory240may comprise one or more applications which execute on the processor(s)222.

Electronic device210may further include one or more input/output interfaces such as, e.g., a keypad226and one or more displays228. In some embodiments electronic device210comprises one or more camera modules230and an image signal processor232and one or more location/motion devices234.

In some embodiments electronic device210may include a controller270which may be implemented in a manner analogous to that of controller170, described above. In the embodiment depicted inFIG. 2the adjunct controller270comprises one or more processor(s)272, a memory module274, a state manager276, an I/O module278. In some embodiments the memory module274may comprise a persistent flash memory module. The I/O module278may comprise a serial I/O module or a parallel I/O module. Again, because the adjunct controller270is physically separate from the main processor(s)224, the adjunct controller270may be made secure, i.e., inaccessible to hackers such that it cannot be tampered with. In some examples portions of the state manager276may reside in the memory240of electronic device200and may be executable on one or more of the processors222.

FIG. 3is a high-level schematic illustration of an exemplary architecture for a subsystem300which may be adapted to implement user detection and recognition in accordance with some embodiments. Referring toFIG. 3, in some examples the subsystem300comprises a controller320. Subsystem controller320may be implemented as a processor as described herein, or may be implemented as field programmable gate array (FPGA) or as a dedicated device, e.g., an application specific integrated circuit (ASIC).

Subsystem controller320may include logic defining one or more functional modules. In the example depicted inFIG. 3the subsystem controller320includes logic which defines a state manager330and a local memory340. State manager330may be communicatively coupled to one or more input devices such as proximity sensor(s)350and/or cameras352. In some example state manager330may correspond to state manager176depicted inFIG. 1or state manager276depicted inFIG. 2.

In some examples controller320may implement an interface compatible with the extensible host controller interface (xHCI) interface specification defined in the Universal Serial Bus (USB) 3.X (www.usb.org). Controller320may provide an interface to communication bus which may allow data to be passed between controller320and a host device, e.g., one or more processors in an electronic device such as device100or device200.

In some examples the state manager330on controller320implements operations to implement user detection and recognition for electronic devices. Having described various structures of a system to implement an user recognition in electronic devices, operating aspects of a system will be explained with reference toFIGS. 4-5, which are flowcharts illustrating operations in methods to implement user detection and recognition for electronic devices in accordance with some examples. The operations depicted in the flowcharts ofFIGS. 4A-4B and 5A-5Bmay be implemented by the state manager330, alone or in combination with other component of electronic devices100,200.

In some examples an electronic device such as electronic device100or200implements operations which may be used to manage a power state of an electronic device based at least in part on inputs from sensors such as a proximity sensor(s)350and/or camera(s)352. The operations depicted inFIG. 4depict an example in which the state manager330may implement a “wake on approach” algorithm which wakes an electronic device100/200based on inputs from proximity sensor(s)350and/or camera(s)352. The operations depicted inFIG. 4may be implemented when an electronic device100/200is in a low-power state (i.e., a sleep state in which the central processor(s) are running a low-power state). Referring toFIG. 4, at operation410the proximity sensor(s) detect an object approaching the electronic device100/200. The state manager330may receive outputs from the proximity sensor(s) and determine whether the object approaching the electronic device100/200is within a predetermined threshold. The threshold may be static (e.g., a fixed, predetermined distance) or may be adjusted dynamically in response to operation conditions or user settings. For example, the threshold may be set as a function of the power state in which the electronic device100/200is operating. Lower power states require more time to “wake” components of the electronic device. Thus, in some examples the distance threshold may be inversely proportional to the power state of the electronic device.

If the object approaching the electronic device is not within the predetermined distance, then control passes back to operation410and the state manager continues to monitor the output of the proximity sensor(s)350. By contrast, if at operation415the object is within the predetermined distance then control passes to operation420and the state manager330activates one or more cameras352on the electronic device100/200in order to collect image information collected by the one or more camera(s)352.

At operation425the state manager330activates one or more human recognition algorithms to determine whether an image input to the camera(s)352is a human. In some examples the human recognition algorithms convert image data collected by the camera(s)352into a histogram form without processing the image data in an image processor. This saves power and enhances the privacy of the electronic device.

At operation430the state manager330determines whether the image input to the camera(s)352is a human. By way of example, the histogram data generated by the image input to the camera(s)352may be compared to preconfigured histogram data characteristic of humanoid forms stored in local memory340. If, at operation430the comparison indicates that the image input to the camera(s)352is not human then control passes back to operation410.

By contrast, if at operation430the comparison indicates that the image input to the camera(s)352is human then control passes to operation435and the state manager migrates the electronic device100/200from the first low power state to an operating power state which may be higher power state than the first low power state in which the electronic device100/200was operating. At operation440the state manager330actives one or more face recognition algorithms to determine whether the image input to the camera(s)352represents the face of an authorized user of the electronic device100/200. In some examples the face recognition algorithms convert image data collected by the camera(s)352into a histogram form without processing the image data in an image processor. This saves power and enhances the privacy of the electronic device.

At operation445the state manager330determines whether the image input to the camera(s)352represents the face of an authorized user of the electronic device100/200. By way of example, the histogram data generated by the image input to the camera(s)352may be compared to preconfigured histogram data characteristic of human faces of authorized users stored in local memory340. If, at operation445the comparison indicates that the image input to the camera(s)352is not an authorized user then control passes to operation450and the state manager330may generate a signal which indicates that the person approaching the electronic device100/200is not an authorized user of the device100/200. At operation455the state manager330locks the electronic device and at operation460the state manager330migrates the electronic device100/200back to the first low-power state and control then passes back to operation410.

By contrast, if at operation445the comparison indicates that the image input to the camera(s)352represents the face of an authorized user then control passes to operation465and the state manager330allows the user to access the electronic device100/200.

Thus, the operations depicted inFIG. 4enable the state manager330to implement a “wake on approach” authorization scheme for an electronic device100/200.FIG. 5depicts operations in a “walk away lock” scheme for the electronic device100/200. Referring toFIG. 5, at operation510the state manager330detects that the operating system of the electronic device100/200has gone idle, e.g., due to inactivity for a predetermined period of time. At operation515the state manager330checks the output of the proximity sensor(s)350to determine whether the object proximate the electronic device100/200is within a predetermined threshold. Again, the threshold may be static (e.g., a fixed, predetermined distance) or may be adjusted dynamically in response to operation conditions or user settings. For example, the threshold may be set as a function of the power state in which the electronic device100/200is operating. Lower power states require more time to “wake” components of the electronic device. Thus, in some examples the distance threshold may be inversely proportional to the power state of the electronic device.

If the object proximate the electronic device is not within the predetermined distance, then control passes to operation525and the state manager330locks the electronic device and migrates the electronic device100/200to a low-power state. The state manager may then revert back to the operations depicted inFIG. 4.

By contrast, if at operation520the output of the proximity detector(s)350indicate that an object is within the predetermined distance then control passes to operation535and the state manager330monitors the outputs of the one or more cameras352on the electronic device100/200in order to collect image information collected by the one or more camera(s)352.

At operation535the state manager330activates one or more human recognition algorithms to determine whether an image input to the camera(s)352is a human. In some examples the human recognition algorithms convert image data collected by the camera(s)352into a histogram form without processing the image data in an image processor. This saves power and enhances the privacy of the electronic device.

At operation540the state manager330determines whether the image input to the camera(s)352is a human. By way of example, the histogram data generated by the image input to the camera(s)352may be compared to preconfigured histogram data characteristic of humanoid forms stored in local memory340. If, at operation540the comparison indicates that the image input to the camera(s)352is not human then control passes back to operation525and the state manager330migrates the electronic device100/200to a low-power state. The state manager may then revert back to the operations depicted inFIG. 4.

By contrast, if at operation540the comparison indicates that the image input to the camera(s)352is human then control passes to operation545and the state manager330actives one or more face recognition algorithms to determine whether the image input to the camera(s)352represents the face of an authorized user of the electronic device100/200. In some examples the face recognition algorithms convert image data collected by the camera(s)352into a histogram form without processing the image data in an image processor. This saves power and enhances the privacy of the electronic device.

At operation550the state manager330determines whether the image input to the camera(s)352represents the face of an authorized user of the electronic device100/200. By way of example, the histogram data generated by the image input to the camera(s)352may be compared to preconfigured histogram data characteristic of human faces of authorized users stored in local memory340. If, at operation550the comparison indicates that the image input to the camera(s)352is not an authorized user then control passes to operation555and the state manager330locks the electronic device100/200to deny access to the device100/200and migrates the electronic device to the low power state.

By contrast, if at operation550the comparison indicates that the image input to the camera(s)352represents the face of an authorized user then control passes to operation560and the state manager330allows the user to access the electronic device100/200.

As described above, in some examples the electronic device may be embodied as a computer system.FIG. 6illustrates a block diagram of a computing system600in accordance with an example. The computing system600may include one or more central processing unit(s)602or processors that communicate via an interconnection network (or bus)604. The processors602may include a general purpose processor, a network processor (that processes data communicated over a computer network603), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, the processors602may have a single or multiple core design. The processors602with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors602with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors. In an example, one or more of the processors602may be the same or similar to the processors102ofFIG. 1.

A chipset606may also communicate with the interconnection network604. The chipset606may include a memory control hub (MCH)608. The MCH608may include a memory controller610that communicates with a memory612. The memory412may store data, including sequences of instructions, that may be executed by the processor602, or any other device included in the computing system600. In one example, the memory612may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via the interconnection network604, such as multiple processor(s) and/or multiple system memories.

The MCH608may also include a graphics interface614that communicates with a display device616. In one example, the graphics interface614may communicate with the display device616via an accelerated graphics port (AGP). In an example, the display616(such as a flat panel display) may communicate with the graphics interface614through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display616. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display616.

A hub interface618may allow the MCH608and an input/output control hub (ICH)620to communicate. The ICH620may provide an interface to I/O device(s) that communicate with the computing system600. The ICH620may communicate with a bus622through a peripheral bridge (or controller)624, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers. The bridge624may provide a data path between the processor602and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH620, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with the ICH620may include, in various examples, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices.

The bus622may communicate with an audio device626, one or more disk drive(s)628, and a network interface device630(which is in communication with the computer network603). Other devices may communicate via the bus622. Also, various components (such as the network interface device630) may communicate with the MCH608in some examples. In addition, the processor602and one or more other components discussed herein may be combined to form a single chip (e.g., to provide a System on Chip (SOC)). Furthermore, the graphics accelerator616may be included within the MCH608in other examples.

Furthermore, the computing system600may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g.,628), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions).

FIG. 7illustrates a block diagram of a computing system700, according to an example. The system700may include one or more processors702-1through702-N (generally referred to herein as “processors702” or “processor702”). The processors702may communicate via an interconnection network or bus704. Each processor may include various components some of which are only discussed with reference to processor702-1for clarity. Accordingly, each of the remaining processors702-2through702-N may include the same or similar components discussed with reference to the processor702-1.

In an example, the processor702-1may include one or more processor cores706-1through706-M (referred to herein as “cores706” or more generally as “core706”), a shared cache708, a router710, and/or a processor control logic or unit720. The processor cores706may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches (such as cache708), buses or interconnections (such as a bus or interconnection network712), memory controllers, or other components.

In one example, the router710may be used to communicate between various components of the processor702-1and/or system700. Moreover, the processor702-1may include more than one router710. Furthermore, the multitude of routers710may be in communication to enable data routing between various components inside or outside of the processor702-1.

The shared cache708may store data (e.g., including instructions) that are utilized by one or more components of the processor702-1, such as the cores706. For example, the shared cache708may locally cache data stored in a memory714for faster access by components of the processor702. In an example, the cache708may include a mid-level cache (such as a level 2 (L2), a level 3 (L3), a level 4 (L4), or other levels of cache), a last level cache (LLC), and/or combinations thereof. Moreover, various components of the processor702-1may communicate with the shared cache708directly, through a bus (e.g., the bus712), and/or a memory controller or hub. As shown inFIG. 7, in some examples, one or more of the cores706may include a level 1 (L1) cache716-1(generally referred to herein as “L1 cache716”).

FIG. 8illustrates a block diagram of portions of a processor core706and other components of a computing system, according to an example. In one example, the arrows shown inFIG. 8illustrate the flow direction of instructions through the core706. One or more processor cores (such as the processor core706) may be implemented on a single integrated circuit chip (or die) such as discussed with reference toFIG. 7. Moreover, the chip may include one or more shared and/or private caches (e.g., cache708ofFIG. 7), interconnections (e.g., interconnections704and/or112ofFIG. 7), control units, memory controllers, or other components.

As illustrated inFIG. 8, the processor core706may include a fetch unit802to fetch instructions (including instructions with conditional branches) for execution by the core706. The instructions may be fetched from any storage devices such as the memory714. The core706may also include a decode unit804to decode the fetched instruction. For instance, the decode unit804may decode the fetched instruction into a plurality of uops (micro-operations).

Additionally, the core706may include a schedule unit806. The schedule unit806may perform various operations associated with storing decoded instructions (e.g., received from the decode unit804) until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one example, the schedule unit806may schedule and/or issue (or dispatch) decoded instructions to an execution unit808for execution. The execution unit808may execute the dispatched instructions after they are decoded (e.g., by the decode unit804) and dispatched (e.g., by the schedule unit806). In an example, the execution unit808may include more than one execution unit. The execution unit808may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an example, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit808.

Further, the execution unit808may execute instructions out-of-order. Hence, the processor core706may be an out-of-order processor core in one example. The core706may also include a retirement unit810. The retirement unit810may retire executed instructions after they are committed. In an example, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc.

The core706may also include a bus unit714to enable communication between components of the processor core706and other components (such as the components discussed with reference toFIG. 8) via one or more buses (e.g., buses804and/or812). The core706may also include one or more registers816to store data accessed by various components of the core706(such as values related to power consumption state settings).

Furthermore, even thoughFIG. 7illustrates the control unit720to be coupled to the core706via interconnect812, in various examples the control unit720may be located elsewhere such as inside the core706, coupled to the core via bus704, etc.

In some examples, one or more of the components discussed herein can be embodied as a System On Chip (SOC) device.FIG. 9illustrates a block diagram of an SOC package in accordance with an example. As illustrated inFIG. 9, SOC902includes one or more processor cores920, one or more graphics processor cores930, an Input/Output (I/O) interface940, and a memory controller942. Various components of the SOC package902may be coupled to an interconnect or bus such as discussed herein with reference to the other figures. Also, the SOC package902may include more or less components, such as those discussed herein with reference to the other figures. Further, each component of the SOC package902may include one or more other components, e.g., as discussed with reference to the other figures herein. In one example, SOC package902(and its components) is provided on one or more Integrated Circuit (IC) die, e.g., which are packaged into a single semiconductor device.

As illustrated inFIG. 9, SOC package902is coupled to a memory960(which may be similar to or the same as memory discussed herein with reference to the other figures) via the memory controller942. In an example, the memory960(or a portion of it) can be integrated on the SOC package902.

The I/O interface940may be coupled to one or more I/O devices970, e.g., via an interconnect and/or bus such as discussed herein with reference to other figures. I/O device(s)970may include one or more of a keyboard, a mouse, a touchpad, a display, an image/video capture device (such as a camera or camcorder/video recorder), a touch surface, a speaker, or the like.

FIG. 10illustrates a computing system1000that is arranged in a point-to-point (PtP) configuration, according to an example. In particular,FIG. 10shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces.

As illustrated inFIG. 10, the system1000may include several processors, of which only two, processors1002and1004are shown for clarity. The processors1002and1004may each include a local memory controller hub (MCH)1006and1008to enable communication with memories1010and1012.

In an example, the processors1002and1004may be one of the processors702discussed with reference toFIG. 7. The processors1002and1004may exchange data via a point-to-point (PtP) interface1014using PtP interface circuits1016and1018, respectively. Also, the processors1002and1004may each exchange data with a chipset1020via individual PtP interfaces1022and1024using point-to-point interface circuits1026,1028,1030, and1032. The chipset1020may further exchange data with a high-performance graphics circuit1034via a high-performance graphics interface1036, e.g., using a PtP interface circuit1037.

As shown inFIG. 10, one or more of the cores106and/or cache108ofFIG. 1may be located within the processors1004. Other examples, however, may exist in other circuits, logic units, or devices within the system1000ofFIG. 10. Furthermore, other examples may be distributed throughout several circuits, logic units, or devices illustrated inFIG. 10.

The chipset1020may communicate with a bus1040using a PtP interface circuit1041. The bus1040may have one or more devices that communicate with it, such as a bus bridge1042and I/O devices1043. Via a bus1044, the bus bridge1043may communicate with other devices such as a keyboard/mouse1045, communication devices1046(such as modems, network interface devices, or other communication devices that may communicate with the computer network1003), audio I/O device, and/or a data storage device1048. The data storage device1048(which may be a hard disk drive or a NAND flash based solid state drive) may store code1049that may be executed by the processors1004.

The following examples pertain to further examples.

Example 1 is electronic device, comprising a proximity detector, a camera, and a controller, comprising logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that an object approaching the electronic device is within a predetermined distance while the electronic device is in a first low-power state, and in response to the indication, to activate the camera on the electronic device while the electronic device remains in a low-power state and determine whether an image input to the camera is a human while the electronic device remains in a low-power state.

In Example 2, the subject matter of Example 1 can optionally include logic, at least partly including hardware logic, which, in response to a determination that the image input is a human, is to transition the electronic device back from the first low-power state to a second power state.

In Example 3, the subject matter of any one of Examples 1-2 can optionally include logic, at least partly including hardware logic, which, in response to a determination that the image is a human, is to activate at least one face-recognition module on the electronic device.

In Example 4, the subject matter of any one of Examples 1-3 can optionally include logic, at least partly including hardware logic, to determine whether an image input to the camera is a face of an authorized user of the electronic device, and in response to a determination that the image is not the face of an authorized user of the electronic device, to present an unrecognized user message on a display of the electronic device, and present a manual login option on the display.

In Example 5, the subject matter of any one of Examples 1-4 can optionally include logic, at least partly including hardware logic, to determine whether an image input to the camera is a face of an authorized user of the electronic device, and in response to a determination that the image is the face of an authorized user of the electronic device, to allow the authorized user to access the electronic device.

In Example 6, the subject matter of any one of Examples 1-5 can optionally include logic, at least partly including hardware logic, to detect that an operating system on the electronic device has gone idle due to inactivity, and in response thereto, to receive an input from the proximity sensor and the camera.

In Example 7, the subject matter of any one of Examples 1-6 can optionally include logic, at least partly including hardware logic, to determine, from the proximity sensor, an indication that there is not an object within a predetermined distance, and in response to the indication, to transition the electronic device from an operating power state to the first low-power state.

In Example 8, the subject matter of any one of Examples 1-7 can optionally include logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that there is an object within a predetermined distance, determine whether an image input to the camera is not a human, and in response to a determination that the image is not a human, to transition the electronic device from an operating power state to the first low-power state.

In Example 9, the subject matter of any one of Examples 1-8 can optionally include logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that there is an object within a predetermined distance, determine whether an image input to the camera is not a human, and in response to a determination that the image is not a human, to transition the electronic device from an operating power state to the first low-power state.

In Example 10, the subject matter of any one of Examples 1-9 can optionally include logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that there is an object within a predetermined distance, determine whether an image input to the camera is a face of an authorized user of the electronic device, and in response to a determination that the image is the face of an authorized user of the electronic device, to allow the authorized user to access the electronic device.

Example 11 is a controller, comprising logic, at least partly including hardware logic, to receive, from a proximity sensor, an indication that an object approaching an electronic device coupled to the controller is within a predetermined distance while the electronic device is in a first low-power state, and in response to the indication, to activate a camera on the electronic device while the electronic device remains in a low-power state, and determine whether an image input to the camera is a human while the electronic device remains in a low-power state.

In Example 12, the subject matter of Example 1 can optionally include logic, at least partly including hardware logic, which, in response to a determination that the image input is a human, is to transition the electronic device back from the first low-power state to a second power state.

In Example 13, the subject matter of any one of Examples 11-12 can optionally include logic, at least partly including hardware logic, which, in response to a determination that the image is a human, is to activate at least one face-recognition module on the electronic device.

In Example 14, the subject matter of any one of Examples 11-13 can optionally include logic, at least partly including hardware logic, to determine whether an image input to the camera is a face of an authorized user of the electronic device, and in response to a determination that the image is not the face of an authorized user of the electronic device, to present an unrecognized user message on a display of the electronic device, and present a manual login option on the display.

In Example 15, the subject matter of any one of Examples 11-14 can optionally include logic, at least partly including hardware logic, to determine whether an image input to the camera is a face of an authorized user of the electronic device, and in response to a determination that the image is the face of an authorized user of the electronic device, to allow the authorized user to access the electronic device.

In Example 16, the subject matter of any one of Examples 11-15 can optionally include logic, at least partly including hardware logic, to detect that an operating system on the electronic device has gone idle due to inactivity, and in response thereto, to receive an input from the proximity sensor and the camera.

In Example 17, the subject matter of any one of Examples 11-16 can optionally include logic, at least partly including hardware logic, to determine, from the proximity sensor, an indication that there is not an object within a predetermined distance, and in response to the indication, to transition the electronic device from an operating power state to the first low-power state.

In Example 18, the subject matter of any one of Examples 11-17 can optionally include logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that there is an object within a predetermined distance, determine whether an image input to the camera is not a human, and in response to a determination that the image is not a human, to transition the electronic device from an operating power state to the first low-power state.

In Example 19, the subject matter of any one of Examples 11-18 can optionally include logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that there is an object within a predetermined distance, determine whether an image input to the camera is not a human, and in response to a determination that the image is not a human, to transition the electronic device from an operating power state to the first low-power state.

In Example 20, the subject matter of any one of Examples 11-19 can optionally include logic, at least partly including hardware logic, to receive, from the proximity sensor, an indication that there is an object within a predetermined distance, determine whether an image input to the camera is a face of an authorized user of the electronic device, and in response to a determination that the image is the face of an authorized user of the electronic device, to allow the authorized user to access the electronic device.

The terms “logic instructions” as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and examples are not limited in this respect.

The terms “computer readable medium” as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and examples are not limited in this respect.

The term “logic” as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and examples are not limited in this respect.

Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.

In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular examples, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.

Reference in the specification to “one example” or “some examples” means that a particular feature, structure, or characteristic described in connection with the example is included in at least an implementation. The appearances of the phrase “in one example” in various places in the specification may or may not be all referring to the same example.