SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor module, a wiring substrate, a sealing member, and a thermal diffusion plate. The semiconductor module includes a semiconductor chip in which a semiconductor element is disposed. The wiring substrate is electrically connected to the semiconductor module. The sealing member seals the semiconductor module and the wiring substrate. The thermal diffusion plate is disposed between the semiconductor module and the wiring substrate, and has a thermal conductivity higher than a thermal conductivity of the sealing member. The thermal diffusion plate has a plate shape and is disposed in the sealing member in a state where a plane direction of the thermal diffusion plate is along a direction intersecting an arrangement direction of the semiconductor module and the wiring substrate.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims the benefit of priority from Japanese Patent Application No. 2023-067362 filed on Apr. 17, 2023. The entire disclosure of the above application is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND

Conventionally, there has been known a semiconductor device in which a semiconductor chip and a wiring substrate are sealed with a sealing member.

SUMMARY

The present disclosure provides a semiconductor device including a semiconductor module, a wiring substrate, a sealing member, and a thermal diffusion plate. The semiconductor module includes a semiconductor chip in which a semiconductor element is disposed. The wiring substrate is electrically connected to the semiconductor module. The sealing member seals the semiconductor module and the wiring substrate. The thermal diffusion plate is disposed between the semiconductor module and the wiring substrate, and has a thermal conductivity that is higher than a thermal conductivity of the sealing member. The thermal diffusion plate has a plate shape and is disposed in the sealing member in a state where a plane direction of the thermal diffusion plate is along a direction intersecting an arrangement direction of the semiconductor module and the wiring substrate.

DETAILED DESCRIPTION

Next, a relevant technology is described only for understanding the following embodiments. In a semiconductor device according to the relevant technology, a semiconductor chip in which a transistor and the like are formed is mounted on a lead frame. A wiring substrate is disposed on the lead frame so as to be separated from the semiconductor chip, and is electrically connected to the semiconductor chip. The semiconductor chip and the wiring substrate are integrally sealed with a sealing member made of a mold resin or the like.

In the semiconductor device described above, the heat generated in the semiconductor chip is transferred to the wiring substrate via the mold resin, so that the wiring substrate may be heated to a high temperature and the reliability of the wiring substrate may be reduced.

A semiconductor device according to an aspect of the present disclosure includes a semiconductor module, a wiring substrate, a sealing member, and a thermal diffusion plate. The semiconductor module includes a semiconductor chip in which a semiconductor element is disposed. The wiring substrate is electrically connected to the semiconductor module. The sealing member seals the semiconductor module and the wiring substrate. The thermal diffusion plate is disposed between the semiconductor module and the wiring substrate, and has a thermal conductivity that is higher than a thermal conductivity of the sealing member. The thermal diffusion plate has a plate shape and is disposed in the sealing member in a state where a plane direction of the thermal diffusion plate is along a direction intersecting an arrangement direction of the semiconductor module and the wiring substrate.

According to this configuration, the thermal diffusion plate is disposed between the semiconductor module including the semiconductor chip and the wiring substrate. Thus, the heat from the semiconductor chip can be radiated in the plane direction of the thermal diffusion plate by the thermal diffusion plate, and the wiring substrate can be restricted from becoming a high temperature. Therefore, it is possible to restrict a decrease in the reliability of the wiring substrate.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals.

First Embodiment

A configuration of a semiconductor device according to a first embodiment will be described with reference toFIGS.1to6. The semiconductor device of the present embodiment is preferably mounted on a vehicle such as an automobile and used to drive various electronic devices for the vehicle. In the present embodiment, as will be described later, a so-called 2-in-1 package semiconductor device in which a first semiconductor chip20and a second semiconductor chip30are sealed with a sealing member70will be described.

The semiconductor device of the present embodiment includes a support substrate10, the first semiconductor chip20, the second semiconductor chip30, first and second coupling members41and42, first to third connection terminals51to53, and the sealing member70.FIG.2is also a cross-sectional view of the semiconductor device taken along line II-II inFIGS.5and6,FIG.3is also a cross-sectional view of the semiconductor device taken along line III-III inFIGS.5and6, andFIG.4is also a cross-sectional view of the semiconductor device taken along line IV-IV inFIGS.5and6. InFIG.6, only an outer shape of a first sealing member71is shown for easy understanding, and a thermal diffusion plate90disposed in the first sealing member71is shown by a solid line as described later.

In the present embodiment, the support substrate10is formed of an active metal brazing (AMB) substrate. Specifically, the support substrate10includes an insulating substrate11having a front surface11aand a rear surface11b, a first metal film12formed on the front surface11aof the insulating substrate11, and a second metal film13formed on the rear surface11bof the insulating substrate11. The insulating substrate11is made of ceramic or the like, and the first metal film12and the second metal film13are made of copper or the like. Hereinafter, a surface of the support substrate10located on the first metal film12is also referred to as a first surface10aof the support substrate10, and a surface of the support substrate10located on the second metal film13is also referred to as a second surface10bof the support substrate10.

In the present embodiment, the first metal film12is patterned into a predetermined shape. Specifically, as shown inFIG.5, the first metal film12is divided into a first mounting portion121to which the first semiconductor chip20is mounted, a second mounting portion122to which the second semiconductor chip30is mounted, and connection portions123. Hereinafter, one direction in a plane direction of the support substrate10will be described as a first direction, and a direction intersecting the first direction and along the plane direction of the support substrate10will be described as a second direction.

The first mounting portion121has a rectangular planar shape. The second mounting portion122includes a main portion122ahaving a rectangular planar shape and disposed at a predetermined distance from the first mounting portion121in the first direction. The second mounting portion122further includes two auxiliary portions122bextending from the main portion122aand arranged to sandwich the first mounting portion121in the second direction. Two connection portions123are disposed so as to sandwich the first mounting portion121in the second direction.

Each of the first semiconductor chip20and the second semiconductor chip30includes a power element such as a metal oxide semiconductor field effect transistor (MOSFET) element or an insulated gate bipolar transistor (IGBT) element. As shown inFIGS.2to4, the first semiconductor chip20is disposed to the first mounting portion121via a bonding member101, and the second semiconductor chip30is disposed to the second mounting portion122via a bonding member102. The second semiconductor chip30is disposed to the main portion122aof the second mounting portion122.

The first coupling member41is disposed to the first semiconductor chip20via a bonding member103. Specifically, the first coupling member41has a length in the second direction longer than that of the first semiconductor chip20, and is disposed such that both end portions in the second direction protrude from the first semiconductor chip20. The end portions of the first coupling member41protruding from the first semiconductor chip20in the normal direction with respect to the plane direction of the support substrate10are electrically connected to the auxiliary portions122bof the second mounting portion122via a bonding member104. Hereinafter, the normal direction with respect to the plane direction of the support substrate10is also simply referred to as the normal direction.

The second coupling member42is disposed to the second semiconductor chip30via a bonding member105. Specifically, the second coupling member42has a length in the second direction longer than that of the second semiconductor chip30, and is disposed such that both end portions in the second direction protrude from the second semiconductor chip30. The end portions of the second coupling member42protruding from the second semiconductor chip30in the normal direction are electrically connected to the connection portions123via a bonding member106.

The first connection terminal51has a plate shape, is connected to the first mounting portion121via a bonding member107, and is disposed to extend from the first mounting portion121along the first direction opposite to the main portion122aof the second mounting portion122.

The second connection terminal52has a plate shape, is connected to the main portion122aof the second mounting portion122via a bonding member108, and is disposed to extend from the second mounting portion122along the first direction opposite to the first mounting portion121.

As shown inFIG.3andFIG.6, the third connection terminal53has a plate shape, is connected to both end portions of the second coupling member42in the second direction via a bonding member109, and is disposed to extend from the second coupling member42along the first direction opposite to the second connection terminal52. Note that the first to third connection terminals51to53of the present embodiment are arranged so as to partially protrude from the sealing member70as described later. The third connection terminal53is disposed such that a portion exposed from the sealing member70overlaps the first connection terminal51in the normal direction. However, the first connection terminal51and the third connection terminal53are disposed apart from each other by a predetermined distance. In addition, the third connection terminal53of the present embodiment has a shape in which a portion facing the first semiconductor chip20and the second semiconductor chip30is opened.

Hereinafter, an integrated body of the support substrate10, the first semiconductor chip20, the second semiconductor chip30, the first and second coupling members41and42, and the first to third connection terminals51to53is also referred to as a power module PM. In the present embodiment, the power module PM corresponds to a semiconductor module. Each of the bonding members101to109is made of, for example, solder or a silver sintered body.

A wiring substrate60is configured by a printed circuit board or the like having a first surface60aand a second surface60b, and is disposed such that the second surface60bfaces the first semiconductor chip20and the second semiconductor chip30. In the wiring substrate60, electronic components61such as a chip capacitor or a resistor are mounted to the first surface60avia a bonding member62, and a driving IC chip63for driving the first semiconductor chip20and the second semiconductor chip30is mounted to the second surface60bvia a bonding member (not shown). The types and arrangement positions of members mounted to the first surface60aand the second surface60bof the wiring substrate60can be appropriately changed. The wiring substrate60is electrically connected to the first semiconductor chip20and the second semiconductor chip30in a cross section different from the cross sections shown inFIGS.2to4.

The sealing member70is made of a molding resin, a potting resin, or the like, and is configured to seal the support substrate10, the first semiconductor chip20, the second semiconductor chip30, the first and second coupling members41and42, the first to third connection terminals51to53, the wiring substrate60, and the like.

In the present embodiment, the sealing member70includes a first sealing member71that seals the support substrate10, the first semiconductor chip20, the second semiconductor chip30, the first and second coupling members41and42, the first to third connection terminals51to53, and the like, and a second sealing member72that seals the wiring substrate60and the like.

More specifically, the first sealing member71has a substantially rectangular parallelepiped shape having a first surface71a, a second surface71bopposite to the first surface71a, and four side surfaces71cto71f. In the present embodiment, a pair of side surfaces having the first direction as a normal direction will be described as a first side surface71cand a third side surface71e, and a pair of side surfaces having the second direction as a normal direction will be described as a second side surface71dand a fourth side surface71f.

The first sealing member71is configured such that the second surface10bof the support substrate10is exposed from the second surface71b. The first sealing member71is disposed such that portions of the first and third connection terminals51and53protrude from the first side surface71c. The first sealing member71is configured such that a part of the second connection terminal52protrudes from the third side surface71e.

The second sealing member72has a substantially rectangular parallelepiped shape having a first surface72a, a second surface72bopposite to the first surface72a, and four side surfaces72cto72f. The wiring substrate60is disposed in the second sealing member72such that the first surface60ais substantially parallel to the first surface72aof the second sealing member72.

The first sealing member71and the second sealing member72are integrated by bonding the first surface71aof the first sealing member71and the second surface72bof the second sealing member72via a bonding layer80formed of underfill or the like.

The thermal diffusion plate90is made of a material having a higher thermal conductivity than the sealing member70, has a plate shape, and is disposed between the power module PM (that is, the first semiconductor chip20and the second semiconductor chip30) and the wiring substrate60. In the present embodiment, the thermal diffusion plate90is disposed in the first sealing member71. The thermal diffusion plate90is disposed so as to partially protrude from the second side surface71dand the fourth side surface71fof the first sealing member71, and is disposed so as not to protrude from the first side surface71cand the third side surface71e. That is, the thermal diffusion plate90is disposed so as to protrude from the second and fourth side surfaces71dand71fof the first sealing member71, which are different from the first side surface71cfrom which the first and third connection terminals51and53protrude and the third side surface71efrom which the second connection terminal52protrudes.

The thermal diffusion plate90is disposed in a state of being insulated from the first semiconductor chip20, the second semiconductor chip30, the wiring substrate60, and the like. As long as the thermal diffusion plate90is made of a material having a higher thermal conductivity than the sealing member70as described above, the detailed material can be appropriately changed. For example, the thermal diffusion plate90may be made of copper, aluminum, iron, an alloy thereof, or a laminated plate in which plate members made of these metal materials are laminated. In this case, since the thermal diffusion plate90is made of a magnetic material such as iron, the thermal diffusion plate90functions as an electromagnetic shield, and propagation of noise between the power module PM and the wiring substrate60can also be restricted. The thermal diffusion plate90is made of, for example, graphite having a higher thermal conductivity in a plane direction than in a thickness direction. Graphite has a thermal conductivity of 7 W/mK in the thickness direction and a thermal conductivity of 1700 W/mK in the plane direction. The thermal diffusion plate90may also be made of, for example, an insulating material such as ceramic.

The configuration of the semiconductor device according to the present embodiment has been described above. Next, the operation of the semiconductor device will be described, and the configuration of the thermal diffusion plate90will be described in more detail.

The semiconductor device as described above is used to constitute, for example, an inverter circuit, and the first semiconductor chip20and the second semiconductor chip30generate heat during use. When the wiring substrate60reaches a high temperature due to heat transfer from the first semiconductor chip20and the second semiconductor chip30, the reliability of the wiring substrate60decreases. However, in the present embodiment, the thermal diffusion plate90is disposed between the first semiconductor chip20and the second semiconductor chip30. Thus, the thermal diffusion plate90can spread the heat from the first semiconductor chip20and the second semiconductor chip30in the plane direction of the thermal diffusion plate90, and can restrict the wiring substrate60from reaching a high temperature.

The present inventors performed a simulation using a semiconductor device ofFIG.7, which is a simplified model of the above-described semiconductor device. In the semiconductor device ofFIG.7, a semiconductor chip21is disposed to a support substrate10via a bonding member110, and a connection terminal54is disposed to the semiconductor chip21via a bonding member111. Furthermore, in the semiconductor device shown inFIG.7, a thermal diffusion plate90is disposed above the connection terminal54in a state of being separated from the connection terminal54, and the wiring substrate60provided with the electronic components61and the driving IC chip63is disposed above the thermal diffusion plate90. The sealing member70is disposed so as to seal these components. Specifically, the support substrate10, the semiconductor chip21, and the thermal diffusion plate90are sealed with the first sealing member71, and the wiring substrate60is sealed with the second sealing member72. The semiconductor device is configured by bonding the first sealing member71and the second sealing member72via the bonding layer80.

The present inventors have diligently studied the configuration of thermal diffusion plate90using the above-described semiconductor device, and obtained the results shown inFIGS.8A to8C,9,10A,10B,11,12A to12C, and13. Each figure shows the result when the semiconductor chip21is set at 200° C. The temperatures inFIGS.9,11, and13indicate the temperature of the driving IC chip63.

First, the present inventors diligently studied an area of the thermal diffusion plate90and obtained the results shown inFIGS.8A to8CandFIG.9. Here, the area refers to an area of a surface whose plane direction intersects an arrangement direction of the semiconductor chip21and the thermal diffusion plate90. In other words, the area here is the area of a surface whose normal direction is the arrangement direction of the semiconductor chip21and the thermal diffusion plate90.FIGS.8A to8C and9show the results in a case where the thermal conductivity of the sealing member70is 0.9 W/mK, the thermal diffusion plate90is made of copper (that is, the thermal conductivity is 398 W/mK), and the thickness of thermal diffusion plate90is 0.5 mm.

As shown inFIGS.8A to8C and9, it is confirmed that the temperature of the driving IC chip63can be lowered with an increase in the area of the thermal diffusion plate90. Then, it is confirmed that the temperature of the driving IC chip63sharply decreases when the area of the thermal diffusion plate90is twice or more of the area of the semiconductor chip21. Therefore, it is preferable that the area of the thermal diffusion plate90is twice or more of the area of the semiconductor chip21. When multiple semiconductor chips such as the first semiconductor chip20and the second semiconductor chip30are provided as in the present embodiment, the area of the thermal diffusion plate90is preferably twice or more of the total area of the multiple semiconductor chips.

In addition, the present inventors have diligently studied the thermal conductivity of thermal diffusion plate90and obtained the results shown inFIGS.10A,10B, and11.FIGS.10A,10B, and11show the results when in a case where the thermal conductivity of the sealing member70is 0.9 W/mK, the thickness of the thermal diffusion plate90is 0.5 mm, and the area of the thermal diffusion plate90is four times the area of the semiconductor chip21.FIG.10Bshows a simulation result when the thermal diffusion plate90is made of copper (that is, the thermal conductivity is 398 W/mK) and the thermal conductivity of the thermal diffusion plate90is about 442 times the thermal conductivity of the sealing member70.

As shown inFIGS.10A,10B, and11, it is confirmed that the temperature of the driving IC chip63can be lowered with an increase in the thermal conductivity of the thermal diffusion plate90. In addition, it is confirmed that the temperature of the driving IC chip63sharply decreases when the thermal conductivity of the thermal diffusion plate90is 10 times or more of the thermal conductivity of the sealing member70. Therefore, the thermal conductivity of the thermal diffusion plate90is preferably 10 times or more of the thermal conductivity of the semiconductor chip21.

Furthermore, the present inventors diligently studied the thickness of the thermal diffusion plate90and obtained the results shown inFIGS.12A to12CandFIG.13. Note thatFIGS.12A to12CandFIG.13show the results in a case where the thermal conductivity of the sealing member70is 0.9 W/mK, the thermal diffusion plate90is made of copper (that is, the thermal conductivity is 398 W/mK), and the area of the thermal diffusion plate90is four times the area of the semiconductor chip21.

As shown inFIGS.12A to12CandFIG.13, it is confirmed that the temperature of the driving IC chip63can be lowered with a decrease in the thickness of the thermal diffusion plate90. Then, it is confirmed that the temperature of the driving IC chip63sharply decreases when the thickness of the thermal diffusion plate90is 1 mm or less. Therefore, the thickness of the thermal diffusion plate90is preferably 1 mm or less. When the thickness of the thermal diffusion plate90is in a range of 1 mm or more, it is confirmed that the heat transfer in the thickness direction also increases and the effect decreases. However, for example, as shown inFIG.9, when the thermal diffusion plate90is not provided, the temperature of the driving IC chip63becomes about 173° C. The case where the thermal diffusion plate90is not provided is a case where the area of the thermal diffusion plate/the area of the semiconductor chip is 0 inFIG.9. Therefore, it is confirmed that the temperature of the driving IC chip63can be lowered by providing the thermal diffusion plate90, although the effect is reduced when the thermal diffusion plate90is too thick.

From the above, it is preferable that the area of the thermal diffusion plate90is twice or more of the total area of the first semiconductor chip20and the second semiconductor chip30. It is preferable that the thermal conductivity of the thermal diffusion plate90is 10 times or more of the thermal conductivity of the sealing member70. It is preferable that the thermal diffusion plate90has a thickness of 1 mm or less.

The configuration of the semiconductor device according to the present embodiment has been described above. Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference toFIGS.14A to14D. Each ofFIGS.14A to14Dshows a cross section corresponding to the cross section shown inFIG.2.

First, as shown inFIG.14A, the power module PM is prepared in which the first semiconductor chip20and the second semiconductor chip30are disposed above the support substrate10, and the first to third connection terminals51to53and the first and second coupling members41and42are disposed. The second semiconductor chip30and the second coupling member42are arranged in a cross section different from that ofFIG.14A.

Subsequently, as shown inFIG.14B, a mold200in which a cavity203is formed by fitting a first mold201and a second mold202is prepared, and the power module PM and the thermal diffusion plate90are disposed in the mold200. In the present embodiment, the first mold201has a recessed portion201bat an inner portion of a surface201afitted to the second mold202. The inner portion of the surface201ais a portion close to the cavity203. The recessed portion201bhas a depth corresponding to the thickness of the thermal diffusion plate90.

Then, the power module PM is disposed in the first mold201such that the second surface10bof the support substrate10is in contact with the first mold201. In addition, the thermal diffusion plate90is disposed such that an outer edge portion of the thermal diffusion plate90is fitted into the recessed portion201bof the first mold201. The thermal diffusion plate90is sandwiched between the first mold201and the second mold202by fitting the first mold201and the second mold202.

Subsequently, as shown inFIG.14C, a molten resin is poured into the mold200and solidified to form the first sealing member71. Accordingly, the first sealing member71in which a part of the thermal diffusion plate90protrudes is formed.

Although not particularly illustrated, the second sealing member72in which the wiring substrate60is disposed is prepared. Then, as shown inFIG.14D, the semiconductor device is formed by bonding the first sealing member71and the second sealing member72via the bonding layer80.

According to the present embodiment described above, the thermal diffusion plate90is disposed between the wiring substrate60and the power module PM having the first semiconductor chip20and the second semiconductor chip30. Thus, the heat from the first semiconductor chip20and the second semiconductor chip30can be radiated in the plane direction of the thermal diffusion plate90by the thermal diffusion plate90, and the wiring substrate60can be restricted from reaching a high temperature. Therefore, it is possible to restrict a decrease in the reliability of the wiring substrate60.

In recent years, it has also been considered to form the first semiconductor chip20and the second semiconductor chip30using a silicon carbide substrate in order to reduce loss. In this case, since silicon carbide is a wide gap material, a semiconductor chip formed using the silicon carbide substrate has a use limit temperature of 200° C., for example. For example, when the semiconductor chip is formed using a silicon substrate, the use limit temperature is 150° C., for example. Therefore, by disposing the thermal diffusion plate90as in the present embodiment, even when the first semiconductor chip20and the second semiconductor chip30are formed of the silicon carbide substrate or the like and tend to reach a high temperature, it is possible to sufficiently restrict the wiring substrate60from reaching a high temperature. In other words, even when the first semiconductor chip20and the second semiconductor chip30are formed of the silicon carbide substrate or the like, it is not necessary to perform a special process on the wiring substrate60, and the same wiring substrate as that of the conventional art can be used as the wiring substrate60.

In the present embodiment, the sealing member70is formed by bonding the first sealing member71and the second sealing member72. Therefore, the first sealing member71and the second sealing member72may be separately prepared, and the design of each of the sealing members71and72can be easily changed.

In the present embodiment, the thermal diffusion plate90has the area twice or more of the total area of the first semiconductor chip20and the second semiconductor chip30, so that the wiring substrate60can be sufficiently restricted from reaching a high temperature.

In the present embodiment, the thermal conductivity of the thermal diffusion plate90is 10 times or more of the thermal conductivity of the sealing member70, so that the wiring substrate60can be sufficiently restricted from reaching a high temperature.

In the present embodiment, since the thickness of the thermal diffusion plate90is 1 mm or less, it is possible to sufficiently restrict the wiring substrate60from reaching a high temperature.

In the present embodiment, since the thermal diffusion plate90is made of graphite or the like having a higher thermal conductivity in the plane direction than in the thickness direction, the wiring substrate60can be further restricted from reaching a high temperature.

In the present embodiment, the thermal diffusion plate90is disposed so as to be exposed from the first sealing member71. Therefore, the first sealing member71can be easily disposed using the mold200or the like.

In the present embodiment, the thermal diffusion plate90is disposed so as to protrude from a surface different from the surface on which the first to third connection terminals51to53protrude from the first sealing member71. Therefore, a creepage distance can be easily secured as compared with a case where the surfaces of the first sealing member7from which the first to third connection terminals51to53protrude are the same as the surfaces of the first sealing member7from which the thermal diffusion plate90protrudes.

In the present embodiment, the thermal diffusion plate90is insulated from the first semiconductor chip20, the second semiconductor chip30, the wiring substrate60, and the like. Therefore, no current flows through the thermal diffusion plate90, and heat generation of the thermal diffusion plate90can be restricted. Therefore, the wiring substrate60can be restricted from reaching a high temperature by the heat of the thermal diffusion plate90.

Second Embodiment

The following describes a second embodiment. The present embodiment is different from the first embodiment in the configuration of the sealing member70. The other configurations of the present embodiment are similar to those of the first embodiment, and therefore a description of the similar configurations will not be repeated.

In the semiconductor device of the present embodiment, as shown inFIG.15, the sealing member70is formed so as to integrally seal the power module PM, the wiring substrate60, and the thermal diffusion plate90. Specifically, the first metal film12of the support substrate10includes fixing portions124. The fixing portions124are apart from the first mounting portion121, the second mounting portion122, and the connecting portions123, and are not electrically connected to any of the first mounting portion121, the second mounting portion122, and the connecting portions123. The fixing portions124are formed at four corners on the first surface10aof the support substrate10.

The wiring substrate60is mechanically connected to the support substrate10via support portions300connected to the fixing portions124. In the present embodiment, the support portions300are connected to four corners of the second surface60bof the wiring substrate60. The support portions300are formed by, for example, appropriately bending a copper plate.

The length of the thermal diffusion plate90in the first direction is shorter than the interval between the support portions300adjacent to each other in the first direction. The thermal diffusion plate90is disposed at a position between the support portions300adjacent to each other in the first direction.

The configuration of the semiconductor device according to the present embodiment has been described above. Next, a method of manufacturing the semiconductor device will be described with reference toFIGS.16A to16D.

First, as shown inFIG.16A, the wiring substrate60is bonded to the power module PM via the support portions300.

Next, as shown inFIG.16B, the power module PM and the thermal diffusion plate90are disposed in the mold200. As described above, the length of the thermal diffusion plate90in the first direction is shorter than the interval between the support portions300adjacent to each other in the first direction. Therefore, the thermal diffusion plate90is slid in the second direction so as to pass between the support portions300adjacent to each other in the first direction, and the thermal diffusion plate90is disposed so that the outer edge portion of the thermal diffusion plate90is fitted into the recessed portion201bof the first mold201.

Next, as shown inFIG.16C, the first mold201and the second mold202are fitted to each other, thereby sandwiching the thermal diffusion plate90between the first mold201and the second mold202.

Thereafter, as shown inFIG.16D, a molten resin is poured into the mold200and solidified to form the sealing member70, thereby manufacturing the semiconductor device.

According to the present embodiment described above, since the thermal diffusion plate90is disposed between the wiring substrate60and the power module PM having the first semiconductor chip20and the second semiconductor chip30, the same effects as those of the first embodiment can be obtained.

In the present embodiment, the power module PM and the wiring substrate100are fixed via the support portions300, and the sealing member70is integrally formed so as to seal the power module PM, the wiring substrate60, and the like. Therefore, the process of forming the sealing member70can be simplified.

Third Embodiment

The following describes a third embodiment. The present embodiment is different from the first embodiment in the configuration of the third connection terminal53. The other configurations of the present embodiment are similar to those of the first embodiment, and therefore a description of the similar configurations will not be repeated.

In the semiconductor device of the present embodiment, as shown inFIGS.17to19, the third connection terminal53is also disposed at a position facing the first semiconductor chip20and the second semiconductor chip30in the normal direction. Therefore, in the present embodiment, the third connection terminal53also functions as a thermal diffusion plate. The thermal diffusion plate90in the first embodiment is not disposed. As in the first embodiment, the second coupling member42is connected to the support substrate10via the bonding member106. Therefore, the third connection terminal53(that is, the thermal diffusion plate) is thermally connected to the support substrate10via the second coupling member42. In addition, since the thermal diffusion plate of the present embodiment is formed of the third connection terminal53, the thermal diffusion plate is formed of a material having conductivity.FIG.17is a cross-sectional view of the semiconductor device taken along line XVII-XVII inFIG.19, andFIG.18is a cross-sectional view of the semiconductor device taken along line XVIII-XVIII inFIG.19.

According to the present embodiment described above, the third connection terminal53functioning as the thermal diffusion plate90is disposed between the wiring substrate60and the power module PM including the first semiconductor chip20and the second semiconductor chip30. Therefore, effects similar to those of the first embodiment can be obtained.

In the present embodiment, the third connection terminal53is also disposed at a position facing the first semiconductor chip20and the second semiconductor chip30in the normal direction, and also functions as a thermal diffusion plate. Unlike the first embodiment, the thermal diffusion plate90formed of a member different from the third connection terminal53is not disposed. Therefore, since a space for disposing the thermal diffusion plate90in the first embodiment is not required, the thickness of the first sealing member71in the normal direction can be reduced, and the size of the semiconductor device can be reduced. Furthermore, since the thermal diffusion plate90different from the third connection terminal53is not required, the number of components can be reduced.

In the present embodiment, the third connection terminal53is connected to both end portions of the second coupling member42in the second direction via the bonding member109. The third connection terminal53is drawn out so as to be exposed from the first side surface71c. Therefore, first, as indicated by arrows A inFIG.18, in the third connection terminal53, currents flow to portions connected to both end portions of the second coupling member42in the second direction via the main portion122aof the second mounting portion122and the second semiconductor chip30. As indicated by arrows B inFIG.19, the currents flowing through the third connection terminal53tend to flow linearly from the joint portions with the second coupling member42to the portion protruding from the first sealing member71. Therefore, a portion of the third connection terminal53facing the first semiconductor chip20and a portion of the third connection terminal53facing the second semiconductor chip30are portions through which a current hardly flows. Therefore, the portions of the third connection terminal53facing the first semiconductor chip20and the second semiconductor chip30can be restricted from being heated to a high temperature by the current. Therefore, heat from the first semiconductor chip20and the second semiconductor chip30can be effectively absorbed.

In the present embodiment, the third connection terminal53is also connected to the connection portions123of the support substrate10via the second coupling member42. That is, the third connection terminal53is thermally connected to the support substrate10. Thus, it is also possible to release heat from the third connection terminal53to the support substrate10, and it is possible to restrict the third connection terminal53from reaching a high temperature. Therefore, heat from the first semiconductor chip20and the second semiconductor chip30can be more effectively absorbed.

Other Embodiments

Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure encompasses various modifications and variations within the scope of equivalents. Furthermore, various combinations and modes, and other combination and modes including only one, more or less element, fall within the spirit and scope of the present disclosure.

For example, in each of the above embodiments, the semiconductor device in which the first semiconductor chip20and the second semiconductor chip30are sealed with the sealing member70has been described. However, the semiconductor device may be configured such that only one semiconductor chip is sealed with the sealing member70, or may be configured such that three or more semiconductor chips are sealed with the sealing member70.

In the first and third embodiments, the configuration in which the thermal diffusion plate90is disposed in the first sealing member71has been described. However, the thermal diffusion plate90may also be disposed in the second sealing member72as long as the thermal diffusion plate90is disposed between the power module PM and the wiring substrate60.

Furthermore, in each of the above embodiments, the area, the thermal conductivity, the thickness, and the like of the thermal diffusion plate90can be appropriately changed.

In addition, each of the above embodiments can be combined as appropriate. For example, the second embodiment may be combined with the third embodiment so that the third connection terminal53also functions as the thermal diffusion plate90.