A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.

Not applicable.

BACKGROUND OF THE INVENTION

This invention is in the field of solid-state semiconductor memories. Embodiments of this invention are more specifically directed to memory cells and architectures for read-only memories.

Non-volatile solid-state memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. Mask-programmable read-only memories (ROMs) constitute one conventional type of non-volatile semiconductor memory. While read/write non-volatile memory technology such as electrically erasable programmable “read-only” memory (EEPROM) devices, “flash” EEPROMs, ferroelectric random-access memories (FRAMs) are currently available, mask-programmable ROMs continue to be attractive due to their extremely small cell sizes and fast read time (for purposes of this description, mask-programmable ROMs will be referred to herein simply as “ROMs”, it being understood that EEPROMs and other programmable memories also operate as “read-only” memories).

FIGS. 1aand1billustrate the arrangement of conventional mask-programmable ROM cells.FIG. 1ais a simplified electrical schematic of a 2×4 portion of a conventional ROM array, showing the arrangement of ROM cells20,0through21,3in two rows and four columns. In this conventional example of a ROM array, cells20,0through20,3are in the same row, and as such receive word line WL0for that row, while cells21,0through21,3are in the same row and receive word line WL1for that row. Cells20,0,21,0are in the same column, and are each coupled to bit line BL0, while cells20,1,21,1are coupled to bit line BL1for their column, cells20,2,21,2are coupled to bit line BL2for their column, and cells20,3,21,3are coupled to bit line BL3for their column. Bit lines BL0through BL3are each connected to sense amplifier6and precharge circuitry3via column decode multiplexer5. Alternatively, precharge circuitry3may be connected to all bit lines BL0through BL3(e.g., on their opposite ends from column decode multiplexer5). A word line decoder (not shown) drives one of word lines WL0, WL1according to a decoded row address. Column decode multiplexer5receives decoded address signals Y[0], Y[1], Y[2], Y[3], in response to each of which the corresponding one of bit lines BL0through BL3, respectively, is coupled to sense line SL and sense amplifier6.

In this conventional example, each of cells2is constructed as a single re-channel metal-oxide-semiconductor (MOS) transistor having its gate connected to the word line WL0, WL1for its row, and its source at ground (Vss). The drain of the MOS transistor of each cell2may or may not be connected to the bit line BLx for its column, depending on the programmed data state for that cell2. In the example ofFIG. 1a, cells20,1and21,0are each programmed to a “0” level, by virtue of their transistor drains being connected to bit lines BL1, BL0, respectively. Conversely, cells20,0and21,1are each programmed to a “1” level, by virtue of their transistor drains being left floating, and not connected to bit line BL0, BL1, respectively.

In the operation of the conventional example ofFIG. 1a, one of bit lines BL0through BL3is selected by column decode multiplexer5, for example in response to the two least significant bits of the column address; this selection similarly selects every fourth column throughout the array. At the beginning of a read cycle while word lines WL0, WL1remain inactive low, precharge circuitry3precharges the selected bit lines to a high voltage and then releases those selected bit lines, allowing them to electrically float. Following bit line precharge, one of word lines WL0, WL1is energized in response to the row address, turning on the n-channel MOS transistors of cells2in that row. Those cells2in the selected row and the selected columns that are programmed to the “0” state will begin pull their respective bit lines toward Vssfrom the precharged level. For example, if bit line BL1is selected and word line WL0is then driven active high, the n-channel transistor in cell20,1will discharge the precharged level at bit line BL1because cell20,1is programmed to its “0” state. Conversely, those cells2in the selected row and columns that are programmed to the “1” state are disconnected from their respective bit lines, and cannot pull those bit lines from their precharged voltage toward Vss. For the example of cell20,1inFIG. 1a,1fbit line BL1and word line WL1are selected, bit line BL1will remain at its precharged level because the “1” state has been programmed. After a sufficient time for the selected bit line BL0, BL1to reach its eventual level, sense amplifier6is enabled to detect the level at the selected bit line BL0, BL1.

As evident fromFIG. 1a, the construction of cells2is quite simple—each cell2consists of only a single transistor, with its drain either connected or not connected to bit line BLx for its column.FIG. 1billustrates, in plan (layout) view, the construction of four cells20,0through21,1according to a conventional approach. In this construction, each cell2is constructed within an active region (e.g., a p-type well, or a p-type region of the substrate surrounded by isolation dielectric in the conventional sense). Word lines WL0, WL1are constructed of polycrystalline silicon or another gate material, and extend across the active regions to serve as the gate electrode of the n-channel transistors of cells2in the corresponding rows. The active surfaces on either side of word lines WL0, WL1are doped n-type, to form source regions9sand drain regions9dof those transistors in the conventional self-aligned manner. A metal conductor providing ground voltage Vss extends across each row of cells2, parallel to word lines WL0, WL1, making contact to each source region9sthrough via13. Bit lines BL0, BL1are formed in a different metal layer from that providing ground voltage Vss, and extend perpendicularly across cells2in corresponding columns. In this example, bit line BL0extends vertically (in the view ofFIG. 1b) across cells20,0,21,0, and bit line BL1extends across cells21,0,21,1.

Each cell2is programmed by the presence or absence of a via11between its drain region9dand its corresponding bit line BL0, BL1. In this example, no via11is provided for cells20,0,21,1, and as such neither of those cells is connected to its corresponding bit line BL0, BL1; these cells20,0,21,1, are thus programmed to a “1” data state. Conversely, a via11is provided in each of cells20,1,21,0, connecting drain region9dto bit lines BL0, BL1, respectively. These cells20,1,21,0are thus programmed to a “0” data state.

In this conventional construction, the read performance of ROM cell2is determined by the current conducted by its n-channel transistor for the “0” data state, as it is this current that determines the time required for cell2to discharge the precharged bit line to a voltage that can be accurately and reliably sensed by sense amplifier6. As is fundamental in the MOS field, the current drive of the cell transistor is directly proportional to the transistor channel width/length ratio.FIG. 1bshows the transistor channel width CW and channel length (i.e., gate width) GW for cell20,0. For maximum device density, and thus minimum chip area required for the ROM resource, it is desirable to construct cells2using minimum size MOS transistors available for the manufacturing technology.

It has been observed, in connection with this invention, that the scaling of ROM transistors at technology nodes of 45 nm and smaller may be limited. One difficulty is the increased device variability at these small feature sizes, particularly in connection with the variability of threshold voltage. At these extremely small feature sizes, effects such as random dopant fluctuations, stress effects, and line edge roughness can cause significant variations in threshold voltage from transistor to transistor. This threshold voltage variability is reflected in significant variation in read current from cell-to-cell in the same array. This variation necessitates relaxation of design parameters to account for the worst case read current, for example by not scaling the ROM cell transistors along with the minimum transistor sizes of the manufacturing technology, or by reducing the bit line length, or both. These relaxed parameters result in reduced performance and larger chip area than would otherwise be expected at the available technology node.

BRIEF SUMMARY OF THE INVENTION

Embodiments of this invention provide a read-only memory (ROM) having both chip area and performance characteristics that are scalable with the minimum transistor feature sizes of the manufacturing technology.

Embodiments of this invention provide such a ROM in which such performance scaling can be attained with full length bit lines according to the desired memory organization.

Embodiments of this invention provide such a ROM in which such scaling can be attained in a manner that requires a minimum amount of decoding and multiplexer circuitry in the sense path.

Other objects and advantages of embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.

This invention may be implemented into a mask-programmable read-only memory (ROM) array in which each addressable memory cell stores two bits of data. Each cell is constructed as a single metal-oxide-semiconductor (MOS) transistor having three potential contact locations between the drain region of the transistor and first, second, and third bit lines. The two-bit data state is programmed by placing a contact or via at a single one or none of the first, second, and third contact locations for each cell. A column decode multiplexer coupled to the three bit lines enables sensing of a logical combination of a pair of the three bit lines to recover one of the data bits stored by the addressed cell, according to an encoding scheme. The second data bit stored by that cell can be retrieved by the column decode multiplexer enabling the sensing of a logical combination of a different pair of those three bit lines.

DETAILED DESCRIPTION OF THE INVENTION

This invention will be described in connection with one or more of its embodiments, namely as implemented into mask-programmable read-only memory (ROM) constructed according to a metal-oxide-semiconductor (MOS) technology, as it is contemplated that this invention is especially beneficial when implemented in that context. However, it is also contemplated that this invention can provide benefit in other circuit and structure applications. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.

FIG. 2illustrates an example of large-scale integrated circuit30, in the form of a so-called “system-on-a-chip” (“SoC”), as now popular in many electronic systems. Integrated circuit30is a single-chip integrated circuit into which an entire computer architecture is realized. As such, in this example, integrated circuit30includes a central processing unit of microprocessor32, which is connected to system bus SBUS. Various memory resources, including random access memory (RAM)38and read-only memory (ROM)39, reside on system bus SBUS and are thus accessible to microprocessor32. In this example, ROM39is realized as mask-programmable ROM, although additional “read-only” memory resources such as electrically erasable programmable read-only memory (EEPROM) may also be provided. ROM39typically serves as program memory, storing the program instructions executable by microprocessor32, while RAM38serves as data memory. In some cases, program instructions may reside in RAM38for recall and execution by microprocessor32. Other system functions are shown, in a generic sense, in integrated circuit30by way of system control34and input/output interface37.

Those skilled in the art having reference to this specification will recognize that integrated circuit30may include additional or alternative functions to those shown inFIG. 2, or may have its functions arranged according to a different architecture from that shown inFIG. 2. The architecture and functionality of integrated circuit30is thus provided only by way of example, and is not intended to limit the scope of this invention.

Embodiments of this invention may be realized in integrated circuit30by way of ROM39, an example of the construction of which is illustrated inFIG. 3. Alternatively, ROM39may correspond to a stand-alone memory integrated circuit, rather than as an embedded memory as shown inFIG. 2. Those skilled in the art having reference to this specification will comprehend that the memory architecture of ROM39inFIG. 3is provided by way of example only.

In this example, ROM39includes memory array40containing read-only memory cells arranged in rows and columns. While a single instance of memory array40is shown inFIG. 3, it is to be understood that ROM39may include multiple memory arrays40, each corresponding to a memory block within the address space of ROM39. In the example shown inFIG. 3, memory array40includes m rows and n columns of ROM cells, each of which store two bits of data. In embodiments of this invention, ROM cells in the same column share three bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0], and ROM cells in the same row share one of word lines WL[m-1:0]. Memory array40may be alternatively arranged to include multiple array blocks or sub-arrays of ROM cells, depending on the addressing space or memory architecture. Row decoder45receives a row address value indicating the row of memory array40to be accessed, and energizes the one of word lines WL[m-1:0] corresponding to that row address value, which couples the ROM cells in the corresponding row to bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0] for the associated columns, depending on the data state stored in those cells, as will be described in further detail below.

Column decoder46receives at least a portion of a column address value, decodes that column address value, and generates column select signals Y[MF-1:0], which are applied to column select circuit42. As will be described in further detail below column select circuit42responds to column select signals Y[MF-1:0] by coupling those bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0] that are associated with one or more columns selected by the column address value to one or more sense amplifiers44. As will be described in further detail below, column select circuit42is constructed as one or more multiplexers, each associated with a group of columns of memory array40, according to a multiplex factor MF and considering that each ROM cell stores two data bits in embodiments of this invention. Sense amplifiers44are constructed in the conventional manner, and communicate the sensed data states from the selected ROM cells to data bus DATA_OUT. Bit line precharge circuitry47is provided to apply a desired precharge voltage to bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0], in advance of each read operation. In this embodiment, precharge circuitry47couples to bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0] through column select circuit42. Alternatively, precharge circuitry47may alternatively be provided on the opposite side of array40from column select42, to directly precharge bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0].

FIG. 4illustrates a 2×2 portion of memory array40, in combination with corresponding portions of column select circuit42. In this illustration, four ROM cells50are shown. According to this embodiment of the invention, each ROM cell50stores two bits of digital data. ROM cell500,0resides in row 0 and column 0, and ROM cell500,1resides in row 0, and column 1. Similarly, ROM cells501,0and501,1reside in columns 0, 1, respectively, of row 1.

An example of the electrical construction of representative ROM cells500,0,500,1is shown inFIG. 4, it being understood that the other cells50in memory array40will be similarly constructed. According to this embodiment of the invention, ROM cells500,0,500,1each include an n-channel MOS transistor52with its source at ground voltage Vssand its gate connected to word line WL[0]. Referring to ROM cell500,0as an example, the drain of its transistor52is connected to switch54, which connects the drain of transistor52to one or none of the three bit lines BLA[0], BLB[0], BLC[0] associated with this column 0 of ROM cells50according to the programmed state of its ROM cell500,0. According to embodiments of this invention, switch54of each cell50will select at most one of bit lines BLA, BLB, BLC for its column, or will select none.

According to this embodiment of the invention, and as will be described below, switch54of cell500,0is realized by the presence or absence of a contact or via openings through an insulating layer between overlying conductors corresponding to bit lines BLA[0], BLB[0], BLC[0] and a connection to the drain region of transistor52. The term “contact” is commonly understood to refer to an opening through an insulator for a connection between metal or polysilicon in one level to silicon in another level, while the term “via” is commonly understood to refer to an opening through an insulator for a connection between two metal levels. For purposes of this specification, however, the term “contact opening” will be used to generically refer to both types of openings or connections, i.e., inclusive of both contacts to silicon and vias between metal layers. In this embodiment, at most one such contact opening will be present within a given ROM cell50.

The three bit lines BLA[0], BLB[0], BLC[0] associated with column 0 of memory array40are received by column select circuit420. In this embodiment, column select circuit420includes four MOS transistors55athrough55d, each of which has its source connected to sense line SL. Transistor55ahas its drain connected to bit line BLC[0] and its gate receiving column select signal Y[0], and transistor55bhas its drain connected to bit line BLA[0] and its gate also receiving column select signal Y[0]. Transistor55chas its drain connected to bit line BLB[0] and its gate receiving column select signal Y[1], and transistor55dhas its drain connected to bit line BLC[0] and its gate receiving column select signal Y[1]. In operation, both of transistors55a,55bare turned on by an active high level on column select signal Y[0] from column decoder46, resulting in a logical combination (in this case, a “wired-NOR”) of bit lines BLA[0] and BLC[0] at sense line SL (i.e., either of bit lines BLA[0] and BLC[0] at a low level will pull sense line SL low). Similarly, an active high level at column select signal Y[1] turns on both of transistors55c,55d, resulting in a wired-NOR of bit lines BLB[0] and BLC[0] at sense line SL. Alternatively, the architecture may be arranged to obtain a logical combination of the selected bit line pair other than a wired-NOR. Column select circuit421is similarly constructed and operates similarly as column select420, but receives column select signals Y[2], Y[3] representative of the column address of column 1, from column decoder46. Column select circuit421is also connected to the same sense line SL as column select circuit420. Indeed, the combination of column select circuits420,421may be considered and realized as a single multiplexer circuit.

In this embodiment of the invention, precharge circuit47is constructed as a p-channel MOS transistor with its source/drain path connected between sense line SL and power supply voltage Vdd, or another voltage level to which bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0] are to be precharged, and receives precharge control signal PRE at its gate. Alternatively, as mentioned above, bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0] may be directly precharged from the opposite side of array40, rather than through column select circuit42as in the example ofFIG. 4. In either case, “pull-down” n-channel MOS transistors (not shown) may be connected to bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0] on either side of column select circuits420,421, to restore a low level at the end of a read cycle; such pull-down devices are conventional in the art for precharge-high ROMs.

In operation, row decoder45and column decoder46receive the row and column addresses, respectively, of one or more ROM cells50to be read in the current read cycle. The row address will indicate which of word lines WL[m] will be energized to accomplish the read. In this embodiment of the invention, the column address will indicate which column select signal Y[0], Y[1], Y[2], Y[3] will be selected, for example according to the two least significant bits of a column address. The selected column select signal Y[0], Y[1], Y[2], Y[3] will in turn select the corresponding one of column select circuits420,421and its corresponding group of bit lines BLA[n-1:0], BLB[n-1:0], BLC[n-1:0].

Upon selection of the addressed column, precharge is accomplished by assertion of one of its column select signals Y. For example, column 0 is selected by column decoder46asserting column select signal Y[0] to an active high level, turning on transistors55a,55bof column select circuit420to connect bit lines BLA[0], BLC[0] to sense line SL. This selection is followed by control circuitry (not shown) driving precharge control signal PRE_ to an active low level, which applies power supply voltage Vddto bit lines BLA[0] and BLC[0]. After a time sufficient to raise the bit line voltage to the desired level, precharge control signal PRE_ is deactivated, allowing bit lines BLA[0] and BLC[0] to float at their precharged voltage. All word lines WL[m] have been at an inactive low level during this precharge operation, and column select signal Y[0] remains asserted.

Row decoder45then asserts the one of word lines WL[m] corresponding to the addressed row, which will turn on transistors52in each of ROM cells50in that corresponding row of array40. For example, if word line WL[0] is energized, transistors52in cells500,0and500,1will be turned on. Because cell500,0is in the selected column in this example, the programmed data state of its switch54will be communicated to its precharged bit lines BLA[0], BLC[0]. If switch54of ROM cell500,0is programmed to connect the drain of transistor52to bit line BLA0, bit line BLA[0] will be pulled low by transistor52. Precharged bit line BLC[0] will be pulled low by bit line BLA[0] going low, since both of transistors44a,44bare turned on by the asserted column select signal Y[0]. Similarly, if switch54of cell500,0is programmed to connect the drain of transistor52to bit line BLC[0], bit line BLC[0] will instead be discharged (as will bit line BLA[0] via column select circuit420). If switch54of ROM cell500,0is programmed to connect the drain of transistor52to bit line BLB[0] or to none of bit lines BLA[0], BLB[0], BLC[0], then both of precharged bit lines BLA[0], BLC[0] will remain at their precharged level upon word line WL[0] driven active high. Sense amplifier44is enabled after sufficient time for the voltage to develop at sense line SL, at which time the wired-NOR of bit lines BLA[0] and BLC[0] is sensed as data bit Q. Column select signal Y[0] and word line WL[0] are then de-energized. Data bit Q read in this cycle, with column select signal Y[0] asserted, corresponds to one of the two data bits stored by cell500,0in this embodiment of the invention, and may be communicated by sense amplifier44on data bus DATA_OUT.

At such time as the other data bit stored by cell500,0is desired to be read, this process is repeated but with column select signal Y[1] asserted by column decoder44, turning on transistors55cand55din column select circuit420and coupling bit-lines BLB[0] and BLC[0] to sense line SL. Precharge signal PRE is driven active low to apply power supply voltage Vddto these bit lines BLB[0] and BLC[0] for the desired precharge time, and is then released as before. Word line WL[0] is asserted, turning on transistor52in cells50in its row 0, including cell500,0; column select signal Y[1] remains asserted so that both of bit lines BLB[0], BLC[0] are connected to sense line SL. The programmed state of switch54in this selected cell500,0then determines whether bit lines BLB[0], BLC[0] are discharged through its transistor52. The wired-NOR of bit lines BLB[0] and BLC[0] at sense line SL is then sensed by sense amplifier46as data bit Q, and column select signal Y[1] and word line WL[0] are de-energized. Data bit Q that is read in this cycle, with column select signal Y[1] asserted, corresponds to the other one of the two data bits stored by cell500,0in this embodiment of the invention.

According to this embodiment of the invention, the encoding of the programmed position of switch54in ROM cell500,0into the two stored data bits correspond to the assignment of bit lines BLA[0], BLB[0], BLC[0] into the pairs selected by column select signals Y[0], Y[1]. In this example, the four available data states of the two data bits stored by ROM cell500,0corresponds to the following states of switch54:

Bit line connected toData bit Q forData bit Q fortransistor 52Y[0] assertedY[1] assertedBLC00BLB10BLA01none11
For example, if cell500,0is programmed to connect bit line BLC[0] to the drain of transistor52, sense line SL will be at a low level both when column select signal Y[0] is energized, and when column select signal Y[1] is energized. If cell500,0is programmed with bit line BLB[0] connected to transistor52, then sense line SL will remain high when column select signal Y[0] is energized, but will be pulled low when column select signal Y[1] is energized. If cell500,0is programmed with bit line BLA[0] connected to transistor52, then sense line SL will be pulled low with column select signal Y[0] energized, but will remain high when column select signal Y[1] is energized. And if transistor52of ROM cell500,0is connected to none of bit lines BLA[0], BLB[0], BLC[0], sense line SL will remain at its high level while both of column select signals Y[0] and Y[1] are respectively energized.

In this example, sense amplifier44is shared by columns 0 and 1 (and perhaps other columns). As such, during the sensing of column 0, column select signals Y[2], Y[3] remain inactive low, and the states of bit lines BLA[1], BLB[1], BLC[1] do not interfere with the level at sense line SL. In this example, column select circuits420,421together correspond to a 4:1 multiplexer (i.e., multiplex factor MF=4), considering that each cell50stores two data states, so that each physical column corresponds to two “logical” columns. The extent to which sense amplifiers44are shared (i.e., the number of separate sense amplifiers44for array40) depends on the desired data word width to be read in each cycle, as reflected by the column sense architecture. At one extreme, one sense amplifier44may be provided for each column for a maximum width data word; at the other extreme, one sense amplifier44may be shared by all columns in array40for a data word of two bits.

As mentioned above, each ROM cell50of memory array40is programmed (i.e., its switch54is set) by the presence or absence of a contact opening for a connection between the drain region of transistor52and at most one of three overlying conductors corresponding to bit lines BLA[1], BLB[1], BLC[1]. Referring now toFIGS. 5aand5bin combination withFIGS. 6athrough6c, an example of the physical construction of ROM cell50m,jaccording to an embodiment of the invention will now be described.FIGS. 5aand6aillustrate ROM cell50m,j, in plan and cross-sectional views, respectively, prior to the formation of bit lines BLA[j], BLB[j], BLC[j] for its column j.FIGS. 5b,6b, and6cillustrate ROM cell50m,j, after bit line formation.

Referring toFIGS. 5aand6a, ROM cell50m,jis formed at the surface of p-type well52, which in this example is a conventional well region of the desired dopant concentration formed into p-type substrate50. The active region at which cell50m,jis formed is defined by surrounding isolation dielectric structures55, for example silicon dioxide formed according to conventional shallow trench isolation techniques. Alternatively, p-type well52may be omitted, in which case ROM cell50m,jis formed at the surface of p-type substrate50itself.

An n-channel MOS transistor (corresponding to transistor52) is defined by polysilicon gate electrode56overlying the surface of p-type well52, separated from that surface by gate dielectric57. This transistor also includes n+ source and drain regions54s,54d, respectively, formed into p-type well52on either side of polysilicon gate electrode56, for example in the well-known self-aligned manner. If desired, sidewall dielectric59may be included, as shown inFIG. 6a, to define source and drain regions54s,54dwith lightly-doped drain extensions, as known in the art. Polysilicon gate electrode56corresponds to word line WL[m] in memory array40, and as such this element will extend across each of those cells50that are in the same row m as cell50m,j.

In this embodiment of the invention, source region54sis biased to ground voltage Vssby metal conductor58band contact openings53. Metal conductor58bruns parallel to gate electrode56in this example, and is separated from the surface of source region54sby interlevel dielectric layer62. Contact openings53are formed through dielectric layer62at selected locations overlying source region54s, through which the metal of conductor58bextends and makes ohmic contact to source region54s. In this embodiment of the invention, the same metal layer forms metal conductor58awithin the area of ROM cell50m,jand overlying drain region54d; contact openings53are also etched through dielectric layer62to allow metal conductor58ato make ohmic contact to drain region54d. Metal conductors58a,58b, and contact openings53through dielectric layer62are formed by conventional deposition and photolithography processes, as known in the art.

FIGS. 5b,6b, and6cillustrate ROM cell50m,jafter the formation of metal conductors60. As shown inFIG. 5b, three metal conductors60extend across the area of cell50m,j, in a direction perpendicular to gate electrode56(i.e., word line WLm). These three metal conductors60correspond to bit lines BLA[j], BLB[j], BLC[j], and all three extend across each of those cells50in the same column j as cell50m,j. In this embodiment of the invention, as shown inFIGS. 6band6c, metal conductors60are in a different metal level, in this case a higher metal level, than metal conductors58a,58b. Second interlevel dielectric layer64is disposed over metal conductors58a,58b, with metal conductors60formed in a metal level overlying that second interlevel dielectric layer64. Source/drain contact openings53through dielectric layer62are shown inFIGS. 6band6cin shadow, to clarify that metal conductors58a,58bare in contact with source/drain regions54n, but at a different depth into the page.

According to this embodiment of the invention, the data state stored by ROM cell50m,jis determined by the presence or absence of a connection between the drain region54dand at most one of bit lines BLA[j], BLB[j], BLC[j]. In this example, ROM cell50m,jhas been programmed by the placement of via61between the metal conductor60corresponding to bit line BLAj/kand metal conductor58a, which in turn is in contact with drain region54d. According to embodiments of this invention, this placement of at most one via61is accomplished by the generating of a photomask or reticle pattern for ROM cell50m,jat the appropriate via level that defines an opening to be present at the location at which metal conductor60associated with bit line BLA[j] crosses metal conductor58a, but does not define vias at locations61′ at which metal conductors60for bit lines BLB[j] and BLC[j] cross metal conductor58, as shown inFIG. 5b.

FIG. 6bshows, in cross-section, the location of via61through dielectric layer64, filled with a metal or other conductive material to form a conductive connection between metal conductor58aand metal conductor60. The fill metal within contact via61may be the same metal, deposited in the same layer, as that of metal conductor60. Alternatively, one or more layers of a fill metal or other conductor, such as tungsten, polysilicon, and the like, may be deposited within via61and then etched back as necessary. Conventional techniques for forming metal-to-metal connections through vias61are well-known in the art, and are suitable for this embodiment of the invention.

FIG. 6cshows, in cross-section, via location61′ at which metal conductor60for bit line BLB[j] crosses over metal conductor58, and at which no contact opening is formed. According to the truth table described above, the programming of ROM cell50m,jto have a connection between drain region54dand bit line BLA[j], but no connections between drain region54dand either of bit lines BLB[j], BLC[j], indicates that the two data bits read from ROM cell50m,jwhen selected will take the respective values of “0” and “1”.

Following the stage in the manufacture shown inFIGS. 5b,6b, and6c, deposition of additional dielectric material, etching of contact openings (i.e., vias), deposition of metal plugs, definition of metal conductors, and other “back-end” processing is performed as desired for the particular construction of the integrated circuit. As known in the art, the number of metal layers (and polysilicon layers, if desired) will be determined by the particular design and desired process technology and cost factors.

It is contemplated that variations and alternatives to the construction and arrangement of ROM cells described above will be apparent to those skilled in the art having reference to this specification, such variations and alternatives remaining within the scope of this invention. For example, p-channel MOS transistors may be used to realize the ROM cells, rather than the n-channel MOS transistors as described above. It is contemplated, however, that n-channel MOS transistors typically have larger current drive characteristics than p-channel devices according to current technology. Other variations and alternatives, particularly in the ROM cell construction, will be apparent to those skilled in the art having reference to this specification.

According to embodiments of this invention, a mask-programmable ROM cell is provided that can source strong read current while providing scalability as transistor feature sizes shrink at advanced technology nodes.FIG. 5aillustrates, by way of the example of ROM cell50m,j, that the n-channel MOS transistor has a channel width CW that is several times that of gate width GW, extending under all three of bit lines BLA[j], BLB[j], BLC[j]. The width/length ratio of this transistor is significant greater than that of conventional minimum feature size transistors, for example on the order of three times that of conventional ROM cells coupled to a single bit line structure, such as shown inFIG. 1bdescribed above. This improved read current enables the chip area required for the ROM memory array in an integrated circuit to scale with the technology node scaling factor, without requiring relaxation in performance requirements, reduction in permissible bit line lengths, or other less-preferred options. And while the overall size of the ROM cell is increased on a per-cell basis, each ROM cell according to embodiments of this invention stores two bits of data and is also scalable to minimum feature sizes for the technology node. It is therefore contemplated that the array density (bits per unit area) of embodiments of this invention will be at least that of conventional ROM arrays.

While this invention has been described according to its embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.