Trunk dialing converter

A digital FSK trunk dialing converter including M and E lead control is disclosed. The dialing converter further includes an FSK detector which is responsive to consecutive half period intervals of a received FSK signal, and a digital signal-to-noise (S/N) detector or estimator which operates to inhibit or keep the E-wire signal lead deactivated in the presence of noise signals which are received from the communications link in absence of acceptable FSK signals. The FSK detector is comprised of two digital circuits which generate pulses indicative of whether the received FSK signal is greater or less than the FSK center frequency. The pulses are integrated and used to trigger a flip-flop which provides a demodulated digital FSK output indicative of a received high or low FSK analog frequency. An E-wire control signal is generated in the receive logic circuitry in response to the demodulated FSK output. The S/N detector comprises a digital circuit coupled to the FSK detector and is responsive to the pulses generated thereby to generate reset signals which are coupled to logic circuitry when noise signals are received to prevent the generation of an E-wire signal when noise is present.

BACKGROUND OF THE INVENTION 
This invention relates generally to telephone communications apparatus and 
more particularly to a frequency shift keyed (FSK) trunk dialing converter 
for controlling two-way communications between telephone systems utilizing 
standard E and M lead control. 
Trunk dialing converters for connecting a local telephone set to a remote 
telephone set over a high frequency radio link, for example, are generally 
known. In such applications, a trunk dialing converter is located on each 
side of the link to couple the telephone sets through the respective 
telephone systems which could include PBX apparatus. Each trunk dialing 
converter includes circuit means for generating FSK seizing, dialing, 
answering, and clearing signals which are transmitted as voice frequency 
tones frequency modulated about a center frequency. Also included in each 
converter are a pair of separate voice path circuits, one for transmitting 
to and one for receiving voice communications from the link which may 
include, for example, a "Lincompex" system. The voice paths, however, are 
interrupted during FSK control signal transmission and reception. 
Typical examples of known prior art trunk systems are disclosed in the 
following patents: U.S. Pat. No. 3,261,923, entitled, "Frequency-Shift 
Dial Pulsing System", which issued to L. T. Anderson, et al. on July 19, 
1966; U.S. Pat. No. 3,349,191, entitled, "Talk-off Protection for In-band 
Telephone signaling Systems, which issued to H. Mann on Oct. 24, 1967; and 
U.S. Pat. No. 3,790,719, entitled, "Method and Means for Connecting Branch 
Exchanges", which issued to B. R. Montague, et al. on Feb. 5, 1974. 
Accordingly, it is an object of the present invention to provide an 
improvement in telephone communication apparatus. 
It is a further object of the invention to provide an improvement in trunk 
dialing apparatus. 
It is yet another further object of the invention to provide an improvement 
in digital trunk dialing apparatus. 
And it is still a further object of the invention to provide an improvement 
in digital frequency shift keyed (FSK) trunk dialing apparatus. 
SUMMARY 
Briefly, the foregoing and other objects of the invention are provided in 
digital trunk dialing converter apparatus including M and E lead control 
which converts DC signals on the M-wire or lead into voice frequency FM 
signals on the transmit path. These signals are then fed to a 
communications link in the same fashion as normal speech. The FM signals 
at the receiving end are then converted back into DC signals on the E-wire 
of a second identical trunk dialing converter. Both dialing converters 
also include a separate voice transmit and receive communications path, 
each having isolation switches which are respectively opened during 
seizing, dialing, answering and clearing control intervals. The present 
invention is directed to improved digital logic circuitry in the receive 
portion of the apparatus, a unique FSK detector which is responsive to 
consecutive half period intervals of a received FSK signal, and a digital 
signal-to-noise (S/N) detector or estimator which operates to inhibit or 
keep the E-wire signal lead deactivated in the presence of noise signals 
which are received from the communications link in absence of acceptable 
FSK signals. The FSK detector is comprised of two digital circuits which 
generate pulses indicative of whether the received FSK signal is greater 
or less than the FSK center frequency. The pulses are integrated and used 
to trigger a flip-flop which provides a demodulated digital FSK output 
indicative of a received high or low FSK analog frequency. An E-wire 
control signal is generated in the receive logic circuitry in response to 
the demodulated FSK output. The S/N detector comprises a digital circuit 
coupled to the FSK detector and responsive to the pulses generated thereby 
to generate reset signals which are coupled to the logic circuitry when 
noise signals are received to prevent the generation of an E-wire signal 
when noise is present.

DETAILED DESCRIPTION 
Referring now to the drawings and more particularly to FIG. 1, shown 
thereat is a block diagram of a conventional radio-telephone system 
whereby a local telephone set 10 can communicate with a remote telephone 
set 12 via a pair of identical trunk dialing converters 14 and 16, 
including the subject matter of the subject invention, which are located 
on either side of a wireless communications link. The link may be, for 
example, a high frequency full loop duplex radio link such as a digital 
"Lincompex" system, the latter comprising apparatus well known to those 
skilled in the art and disclosed, for example, in U.S. Pat. No. 4,271,499, 
J. Howard Leveque, the present inventor. Located between the telephone 
sets 10 and 12 and the respective trunk dialing converters 14 and 16 are 
conventional telephone systems 20 and 22 which may, when desirable, 
include private branch exchange (PBX) equipment. 
The trunk dialing converters 14 and 16 are identical in construction and 
comprise frequency shift keyed (FSK) units for providing two-way telephone 
communications over the high frequency radio link 18 utilizing 
conventional E and M wire or lead control. Such control techniques are 
also well known to those skilled in the art. 
Briefly, each of the trunk dialing converters 14 and 16 convert DC signals 
on their respective M-wire input leads into voice frequency FM signals 
which are coupled to the link 18 and are fed thereto in the same fashion 
as normal speech. The FM signals at the receiving end of the link are 
converted back into DC signals on their respective E-wire leads. The FM 
signals utilized comprise two frequency shift keyed signals f.+-..DELTA.f 
where f=1700 Hz and .DELTA.f=85 Hz. As shown in FIG. 2, the center 
frequency of 1700 Hz is located in the upper band of the voice spectrum 
with f-.DELTA.f=1615 Hz while f+.DELTA.f=1785 Hz. 
The typical operating sequence for the apparatus including this invention 
is illustrated in FIGS. 3A-3E. Considering these figures, in the "idle" 
state (FIG. 3A), the M-wire and E-wire circuits 24-1, 24-2 and 26-1, 26-2 
at both the calling end and called end are shown being open circuited. 
When a calling subscriber lifts his handset from the cradle, not shown, an 
"off-hook" condition exists whereupon the caller hears the dial tone from 
the telephone exchange 20 at the calling end. Next, and as shown in FIG. 
3B, the local exchange 20 causes the M-wire circuit 24-1 to change state, 
which is illustrated as a closure of a switch. A "seize" pulse train 28 
consisting of consecutive f+.DELTA.f and f-.DELTA.f FSK analog signals, 
i.e. tones modulated at 100 baud are generated and transmitted from trunk 
dialing converter 14 over the high frequency radio link 18 to the other 
dialing converter 16 for a period of 300 milliseconds (msec) followed by a 
continuous tone of f+.DELTA.f for another 300 msec, the beginning of the 
generation of "dialing" signals. A transmit voice path in the local trunk 
dialing converter 14 is "split" or opened during this interval. 
The trunk dialing converter 16 on the other side of the radio link 18 
responds to the FSK received from dialing converter 14 by closing the 
E-wire circuit 24-2 as shown by the closed switch condition at the called 
end. With the E-wire circuit 24-2 changing state, a dial tone 30 is 
generated and sent back to the calling end converter 14. The dial tone is 
received from the remote telephone system 22 whereupon the calling end 
converter 14 dials the number of the remote telephone set 12. 
This is represented by FIG. 3C wherein the M-wire 24-1 changes state in 
sympathy with the dial pulses 32 wherein a make (mark) and break (space) 
condition of the M wire switch is represented by f+.DELTA.f=1785 Hz and 
f-.DELTA.f=1615 Hz having intervals of 33 ms and 66 ms, respectively. The 
dial pulses are received at the called end converter 16 whereupon the 
E-wire circuit 24-2 responds in like fashion. The remote telephone system 
22 recognizes the number and accesses the subscriber of the remote 
telephone set 12. During this interval, the voice path circuit in the 
called end trunk dial converter 16 is also open. A ring tone 34 is then 
sent back to the calling end over the high frequency radio link 18. 
As shown in FIG. 3D, the M-wire circuit 26-2 at the remote end dialing 
converter 16 also changes state, causing a seize pulse train 36 of 
f+.DELTA.f and f-.DELTA.f to be sent back to the calling end converter 14 
which causes its E-wire circuit 26-1 to change state. Both the voice paths 
at either end are open circuited during the duration of this pulse 
signalling; however, with both E-wire circuits 26-1 and 26-2 having 
changed state along with the respective M-wire circuits 24-1 and 24-2, 
both transmit and receive voice paths are closed permitting a conversation 
to take place bidirectionally across the link 18 as evidenced by reference 
numerals 36 and 38. 
When the voice communication has ended, the calling party hangs up his 
telephone set 10 by again placing his handset on the cradle, whereupon an 
"on hook" condition occurs. This causes the M-wire circuit 24-1 to again 
change state, whereupon a forward "clear" pulse train 40 of f+.DELTA.f and 
f-.DELTA.f tones are transmitted to the far end for 600 msec. The voice 
transmit path of the calling end converter 14 is again open circuited for 
the duration of these pulses. The pulse train 40 is received, causing the 
E-wire circuit 26-2 of the converter 16 to change state. The called party 
hangs up, causing the M-wire circuit 24-2 to change state. A backward 
"clear" pulse train 42 is sent back to the calling end which is received, 
causing the E wire circuit 26-1 of dialing converter 16 to change state. 
Again during this pulse signalling, the respective voice transmit paths 
are opened. 
When E-wire and M-wire circuits 24-1, 24-2 and 26-1, 26-2 again revert back 
to an open state, the two dialing converters 14 and 16 return to the idle 
condition as shown in FIG. 3E. 
Referring now to the invention, shown in FIG. 5 is an electrical block 
diagram which is illustrative of one of the trunk dialing converters 14 
shown in FIG. 1, it being noted that apparatus 14 and 16 are both 
identical in construction. The trunk dialing converter 14 includes, among 
other things, a voice path circuit 44 for translating voice communication 
from the respective telephone system 20 to the radio link 18 and a 
separate voice path circuit 46 for receiving voice communication from the 
radio link 18 and coupling same back to the telephone system 20. 
As shown, transmit (T.sub.x) voice communication from the local telephone 
system 20, for example, is coupled to a balanced (two wire) to unbalanced 
(one wire) voice input circuit 48 which couples to one side of a transmit 
path isolation switch 50, which in turn is controlled by a digitally 
implemented transmit logic circuit 52 located in the modulator section 54 
of the transmit portion of the dialing converter. The other side of the 
switch 50 is coupled back to an unbalanced to balanced output circuit 56 
which provides a two wire output which is coupled to the high frequency 
radio link 18. 
With respect to receiving (R.sub.x) voice communication signal from the 
radio link 18, the voice path isolation circuit 46 includes a 
substantially identical balanced to unbalanced input circuit 58 which 
receives two wire voice communications from the high frequency radio link 
18. The circuit 58 is coupled to a receive path isolation switch 60 which 
is controlled by a receive logic circuit 62 located in the demodulator 
portion 64 located in the receive portion of the apparatus. The voice path 
isolation switch 60 is coupled back to an unbalanced to balanced output 
circuit 66 which provides a two wire connection signal back to the local 
telephone system 20. 
Thus two separate voice paths, one for transmission and one for reception, 
are included in each trunk dialing converter, with both paths having 
isolation switches which, as will be shown, are opened during respective 
FSK pulse transmission and reception. 
FSK control signal transmission by the trunk dialing converter shown in 
FIG. 5 is provided for in the transmit portion of the apparatus by the 
inclusion of a conventional M-wire change detector circuit 68 which is 
responsive to any change in the M-lead voltage level received from the 
telephone system 20. The output of the M-wire detector 68 is coupled to a 
digitally implemented transmit logic circuit 52 which operates, among 
other things, to open the transmit voice path isolation switch 50 and to 
control a frequency and baud rate conrol circuit 70. FSK signals of 1615 
Hz and 1785 Hz are generated digitally by an FSK generator 72 which is 
responsive to a clock input frequency from a clock generator 74 and 
control from the frequency and baud rate control circuit 70. The details 
of the latter circuits are not shown inasmuch as they comprise circuit 
designs well known to those skilled in the art. The FSK pulse output from 
the generator 72 is coupled to the voice output circuitry 56 through a 
digital band pass filter 76. 
Digital input data is also capable of being transmitted from the trunk 
dialing converter as shown in FIG. 5 via a data input lead 78 which is 
coupled to and controls the FSK generator 72 through transmit logic 
circuitry 52. The transmit logic circuitry 52 is also coupled to a keying 
relay 80 which is adapted to be opened and closed and provide an 
alternately open and grounded connection to the radio link 18. 
In the receive portion of the trunk dialing converter shown in FIG. 5, both 
voice and analog, i.e. sinusoidal 1785 Hz and 1615 Hz FSK signals are 
coupled to input circuit 58 from the radio link 18. Voice signals are fed 
to the output circuit 66 through the voice path isolation switch 60 while 
the analog FSK signals are fed through a FSK filter 80 to a zero crossing 
detector circuit 82 which transforms the sinusoidal high and low tone 
f.+-..DELTA.f signal 81 into a square wave signal of the same respective 
frequency as shown by reference numeral 83 of FIG. 4. This square wave 
output is fed to an FSK detector 84, the details of which are shown in 
FIGS. 6A and 6B. The output of the FSK detector 84 is coupled to a signal 
to noise (S/N) detector or estimator circuit 86, the details of which are 
shown in FIG. 7. The FSK detector output is also coupled to the receive 
logic circuit 62, the details of which are shown in FIG. 8. As will be 
explained in detail subsequently, the receive logic circuit 62 operates to 
either open isolation switch 60 of the receive voice path 46 or to 
activate an E-lead relay 88 which operates to change the state of the 
E-lead wire to the local telephone system 20 when valid or acceptable FSK 
control signals are received. 
Referring now to FIGS. 6A and 6B, the square wave output 83 (FIG. 4) from 
the zero crossing detector 82 comprises either a square wave pulse train 
of f+.DELTA.f=1785 Hz or f-.DELTA.f=1615 Hz centered about a center 
frequency f.sub.c =1700 Hz. The pulse train 83 is applied to input lead 84 
where it is commonly applied to the clock (C) input of a flip-flop 86 to 
one input of an exclusive NOR circuit 88. The output of circuit 88 
comprises an inversion 85 (FIG. 4) of the square wave 83 and is fed to the 
clock (C) input of flip-flop 90. The two clock inputs of the flip-flops 86 
and 90, accordingly, comprise square waves corresponding to the alternate 
half cycles of the output from zero crossing detector 82. The flip-flops 
86 and 90 are triggered by the leading edge of the respective square 
waves. Flip-Flops 86 and 90 have their Q outputs coupled to the D inputs 
of respective flip-flops 92 and 94 which have applied to their clock (C) 
inputs a clock frequency f.sub.1 and comprising, for example, a 792 KHz 
clock signal from the clock frequency divider 75 (FIG. 5). A system reset 
signal (R) is applied to the R inputs of both flip-flops 92 and 94 to 
initially reset the flip-flops. The Q outputs thereof are applied back to 
the R inputs of flip-flops 86 and 90 and to respective counter circuits 96 
and 98 which also have a count input applied thereto from flip-flops 100 
and 102 which in turn are clocked by the clock frequency f.sub.1. The 
combination of counters 96, 100 and 98, 102 form frequency dividers which 
divide f.sub.1 by a fixed number and which are triggered in response to 
the reception of the leading edges of square waves 83 and 85. The output 
count of the dividers is used to clock respective flip-flops 104 and 106. 
With respect to the flip-flop 104, its Q output is connected to a first 
AND gate 108 while its Q output is connected to a second AND gate 110. 
Gates 108 and 110 have their other inputs connected to the Q output of 
flip-flop 92 so as to be enabled by the received leading edge of 83. In a 
like manner, the Q and Q outputs of flip-flop 106 are coupled to a pair of 
AND gates 112 and 114 with a second input thereto being coupled to the Q 
output of flip-flop 94 so as to be enabled by the leading edge of square 
wave 85. 
The outputs of the AND gates 108 and 110 are first coupled to a NOR gate 
116 which is used to clock the (C) input of a flip-flop 118 whose Q output 
is connected to the D input of a second flip-flop 120 which is clocked by 
the f.sub.1 clock frequency signal. Likewise, the outputs of AND gates 112 
and 114 are coupled to a NOR gate 122 which is coupled to the (C) input of 
flip-flop 124 which in turn is coupled to the D input of flip-flop 126 
which is also clocked by the clock frequency f.sub.1. 
It is significant to note at this point that the outputs of AND gates 108 
and 112 of the upper and lower digital signal channels are coupled to the 
same NOR gate 128 while the outputs of AND gates 110 and 114 are coupled 
to the same NOR gate 130. 
Both the upper and lower channels operate in an identical fashion to 
provide a measure of the FSK frequency of the respective square wave 
inputs 83 and 85 applied thereto and whether the measure thereof is above 
or below the center frequency f.sub.c =1700 Hz i.e. at 1785 Hz or 1615 Hz. 
Considering the operation of the upper channel, for example, the f.sub.1 
=792 KHz clock signal is divided by 1700 for each leading edge of square 
wave 83, causing the flip-flop 104 to be triggered at a 1700 Hz rate by 
the counter 96. The Q and Q outputs of flip-flops 104 also change state 
alternately at a 1700 Hz rate; however, the leading edge trigger provided 
from the Q output of flip-flop 92 being applied to the other inputs of AND 
gates 108 and 110 cause respective pulse outputs to be generated which are 
indicative of whether the FSK frequency is greater than and less than the 
center frequency f.sub.c of 1700 Hz. The bottom channel signals appearing 
at the AND gates 112 and 114 provide the same frequency information for 
the alternate half cycle of the input, thereby providing twice as much 
information regarding the frequency of the input. 
Accordingly, the output of the NOR gate 128 provides an indication of 
whether the output of the zero crossing detector 82 is greater than the 
center frequency f.sub.c while the NOR gate 130 provides a signal output 
corresponding to whether or not the output of the zero crossing detector 
is less than f.sub.c. The flip-flops 118, 120 and 124, 126 provide a 
synchronized reset for the counters, 96, 100 and 98, 102 for each output 
of the AND gates 108, 110 and 112, 114. 
Referring now to FIG. 6B, the pulse signals f&gt;f.sub.c and f&lt;f.sub.c which 
respectively appear at the outputs of the NOR gates 128 and 130 are next 
applied to a pair of digital counters which divide and effectively 
integrate the respective number of pulses applied thereto by a 
predetermined division factor. The counters 130 and 132 are weighted i.e. 
have different division factors to account for the fact that a frequency 
f&gt;f.sub.c has a greater number of zero crossings than the lower frequency 
f&lt;f.sub.c so that equalized number of pulses appear at the respective 
outputs on leads 134 and 136 for an equal sampling period or increment. 
Thus, for example, during any one millisecond interval, the counters 130 
and 132 would provide the same number of pulse outputs for an uneven 
number of inputs due to their respective pulse frequency. 
The outputs of the counters 130 and 132 appearing on leads 134 and 136 are 
utilized to alternately trigger an FSK output flip-flop 138. This is 
provided by a pair of pulse amplifiers 140 and 142 being connected to the 
set(S) and reset(R) inputs of flip-flop 138. The counters 130 and 132 are 
reset each time an output pulse appears on leads 134 and 136 by means of 
an AND gate 144. Accordingly, the Q output state of flip-flop 138 will 
switch for each occurrence of an alternate high and low frequency output 
from the counters 130 and 132, thereby providing a demodulated digital 
square wave signal indicative of the FSK analog signals received from the 
radio link 18 (FIG. 1). 
Referring now to FIG. 7, shown thereat is a schematic diagram of the 
signal-to-noise ratio detector or estimator 86 which is provided by the 
subject invention in order to inhibit operation of the receive logic 
circuitry 62 when a noisey signal is received, for example, from the high 
frequency radio link 18 and/or where invalid, i.e. well defined analog FSK 
signals are not received. 
As shown, the two frequency signal outputs from the NOR gates 128 and 130 
(FIG. 6A) are coupled to the set(S) and reset(R) inputs to a flip-flop 146 
through a pair of exclusive NOR gates 148 and 150. They are relatively 
noisier digital signals than that of the output from the integrating 
counters 130 and 132 in that the logic levels at this point change more 
often. The circuitry of FIG. 7 additionally includes three pulse delay 
elements 152, 154 and 156. The input and output pulse of the first delay 
element 152 are coupled to an exclusive OR gate 158. The output of gate 
158 is connected to the clock (C) input of a flip-flop 160. The input and 
output of the third delay element 156 is commonly connected to the reset 
(R) input of flip-flop 160 and the counter 162 through an exclusive OR 
circuit 164. The counter 162 has a clock input f.sub.2 which comprises, 
for example, a 10 KHz clock signal from the clock generator frequency 
divider 75 shown in FIG. 5. 
In operation, the counter 162 begins to count pulses of the frequency 
f.sub.2 each time it is reset by the output of the exclusive OR circuit 
164. The clock (C) input of flip-flop 160 is also reset by the exclusive 
OR gate 164. Thus the first pulse output from the flip-flop 146 upon 
reaching the output of delay element 156 resets both the flip-flop 160 and 
the counter 162. The second pulse output of the flip-flop 146 triggers the 
flip-flop 160 via the exclusive OR gate 158. This transfers the logic 
output level, i.e. "1" or "0" to the (D) input of flip-flop 160 which is 
transferred to the Q output. Accordingly, when a valid FSK signal is gated 
out of the flip-flop 146, the counter 162 always reaches a predetermined 
logic level e.g. a logic "1". Therefore a constant "1" logic level appears 
at the Q output of the flip-flop 160 and the S/N lead 166. If, however, a 
noisey condition exists, then more than normal pulses will be applied to 
the flip-flop 146 from the NOR gates 128 and 130, causing a shorter 
elapsed time to exist between output pulses from the Q output of the 
flip-flop 146. This prevents the counter 162 from reaching its 
predetermined final count and therefore its two possible "1" and "0" logic 
states change more often. Accordingly, the Q output will appear as a pulse 
or series of binary pulses, depending upon the duration of the noise 
rather than a fixed "1" logic level. This pulse output appearing on the 
S/N lead 166 will be utilized as a reset signal for the receive logic 
circuitry shown in FIG. 8. 
Referring now to FIG. 8, the FSK detector output signal from circuit lead 
143 is first applied as an input to a counter 168 whose output is coupled 
to an AND gate 170. The counter 168 acts in combination with two other 
counters 172 and 174, with counter 172 having a clock input frequency 
f.sub.3 of, for example, 1 KHz applied thereto from the clock frequency 
divider 75 shown in FIG. 5. The output of counter 174 is coupled to the 
other input of AND gate 170. The purpose of the three counters 168, 172 
and 174 is to determine the presence of the first 300 msec of FSK 
received. Counter 168 is used to count 15 clock cycles of the received FSK 
while the combination of counters 172 and 174 determine that a 300 
millisecond count of FSK is really a count of 15 clock cycles and has 
arrived between 200 and 400 msec. The AND gate 170, therefore, receives 
two inputs, one of which indicates that 15 clock cycles of FSK have been 
counted and the other indicates that this conclusion was reached within a 
prescribed time interval of 200 to 400 msec. 
If this condition exists, meaning that 300 msec of FSK is present, the 
output of AND gate 170 clocks a flip-flop 176 whose Q output is connected 
to one of three inputs to a second AND gate 178. One other input to the 
AND gate 178 comprises the 1 KHz clock frequency f.sub.3, while the third 
input comprises an FSK signal input from a time delay element 180. Thus if 
FSK is present for a period of at least 24 msec following the first 300 
milliseconds msec of reception, the AND gate 178 provides an output which 
enables a pair of counters 182 and 184. 
The counters 182 and 184 determine if the 300 msec period following the 
initial 300 msec of FSK comprises a constant frequency or tone which is 
indicative of the reception of a valid "seize" pulse. Thus if the two 
conditions are met, at the end of 600 msec flip-flop 186 is clocked from 
counter 184, causing its Q output to change state. This change of state 
signal is coupled to an AND gate 190 along with the output from the delay 
element 180, and an E-wire change of state signal is provided on lead 188 
which is used to operate the relay 88 of FIG. 5. 
Enhanced operation of the trunk dialing converter is achieved by the 
presence of the signal-to-noise detector because the S/N pulse output 
appearing on circuit lead 166 during the presence of noise acts to 
constantly reset all of the counters 168, 170, 172, 182 and 184 as well as 
the flip-flop 176. Thus the E signal generation is inhibited during the 
presence of undesired noise and is only generated when acceptable FSK 
signals are received. 
It should also be noted that the Q output of the flip-flop 186 is also 
coupled back to an OR gate 192 for applying a reset signal to the counters 
when a valid "seize" signal is received. The remainder of the receive 
logic circuitry shown in FIG. 8 is directed to means for resetting the 
flip-flop 186. As shown, the reset(R) input to the flip-flop 186 is 
coupled from an OR gate 194. One input comprises an externally applied 
reset signal which is applied, for example, during system turn-on or a 
manual reset being effected from a front panel, not shown. The second 
input comprises a reset signal externally applied when the telephone 
operational mode is deactivated. The third input comprises the output from 
a logic gate 196 whose two inputs comprise the respective output from the 
counters 198 and 200. The counter 198 is coupled to and is responsive to 
the applied FSK signal from the FSK detector output lead 143 (FIG. 6B). 
The counter 198 is used to generate a "clear" control signal 600 msec 
after its associated telephone set is hung up. In absence of such a 
condition, the counter 198 is continually reset by either the Q output of 
the flip-flop 186, the signal-to-noise detector output on lead 204 or 
during the presence of dialing pulses which appears on lead 206. The reset 
signal on signal lead 206 is provided by an exclusive OR circuit 208 
coupled across the delay element 210 whose input comprises the FSK signal 
after it has been delayed by the delay element 180. 
The counter 200 provides a "time-out" circuit feature which generates a 
reset signal for the flip-flop 186 in the event that a complete link is 
not established within 100 seconds as counted from a clock frequency 
f.sub.4 which may be, for example, 50 Hz applied from the clock frequency 
divider 75 of FIG. 5. The counter 200 is initiated by the output of a NAND 
circuit 208 which has two inputs, an M-lead signal and an E-lead signal. 
And accordingly it is initiated only in the event that both an M-lead 
signal and an E-lead signal are present. Accordingly, this circuit simply 
times out and applies a reset signal through the gate 196 and the NOR gate 
194 in the event, for example, that the E-lead is seized and nothing 
further takes place. 
Thus what has been shown and described is an improved trunk dialing 
converter which includes a FSK demodulator having a digitally implemented 
FSK detector and signal-to-noise detector which operate to enhance the 
operation of the logic circuitry utilized to generate the E-wire relay 
control signal. 
Having thus shown and described what is at present considered to be the 
preferred embodiment of the invention, it should be noted that the same 
has been made by way of illustration and not limitation. Accordingly, all 
modifications, alterations and changes coming within the spirit and scope 
of the invention as set forth in the appended claims are herein meant to 
be included.