DISPLAY DEVICE

A display device includes: a plurality of pixels; a plurality of write signal lines to which a control signal for selecting a pixel row in which a data voltage is to be written is supplied; a WS signal gate driver that supplies the control signal; a plurality of data voltage lines for writing a data voltage; a data driver that supplies the data voltage; a selector circuit that switches a data voltage line to which the data voltage is supplied; a selector control line to which a control signal for controlling the selector circuit is supplied; and a controller that supplies the control signal. The plurality of pixels include a first pixel and a second pixel belonging to a same pixel row. The WS signal gate driver supplies the control signal in a first direction. The controller supplies the control signal in a second direction opposite to the first direction.

CROSS REFERENCE TO RELATED APPLICATION

The present application is based on and claims priority of Japanese Patent Application No. 2021-148848 filed on Sep. 13, 2021. The entire disclosure of the above-identified application, including the specification, drawings and claims is incorporated herein by reference in its entirety.

FIELD

The present disclosure relates to a display device.

BACKGROUND

Display devices including a data selector circuit that inputs data voltages corresponding to gradation values output from a data circuit (data driver) to signal lines in a time division manner via a plurality of switches (for example, RGB switches) are conventionally known. Patent Literature (PTL) 1 discloses a display device including such a data selector circuit and a pair of gate circuits (gate drivers) that are located at both ends of gate lines and output gate signals.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

In the display device disclosed in PTL 1, there is a possibility that luminance is not uniform in a plane. For example, a feedthrough voltage resulting from turnoff of a switch of a data selector circuit or a write transistor of a pixel can cause non-uniform in-plane luminance.

In view of this, the present disclosure provides a display device capable of preventing non-uniformity of in-plane luminance caused by feedthrough voltage.

Solution to Problem

A display device according to an aspect of the present disclosure includes: a plurality of pixels arranged in a matrix; a plurality of first gate control lines that are each located at a different pixel row in the plurality of pixels, and to which a first gate control signal is supplied, the first gate control signal being for selecting a pixel row to which a data voltage corresponding to image data is to be written; a first gate driver that supplies the first gate control signal to the plurality of first gate control lines; a plurality of data voltage lines that are each located at a different pixel column in the plurality of pixels, and used to write the data voltage corresponding to the image data; a data driver that supplies the data voltage to the plurality of data voltage lines; a selector circuit that is connected between the data driver and the plurality of data voltage lines, and switches a data voltage line to which the data voltage from the data driver is supplied among the plurality of data voltage lines; a first selector control line to which a selector control signal for controlling the selector circuit is supplied; and a controller that supplies the selector control signal to the first selector control line, wherein the plurality of pixels include a first pixel and a second pixel that belong to a same pixel row, the first gate driver supplies the first gate control signal to the plurality of first gate control lines to transfer the first gate control signal in a first direction from the first pixel to the second pixel, and the controller supplies the selector control signal to the first selector control line to transfer the selector control signal in a second direction from the second pixel to the first pixel.

Advantageous Effects

A display device according to an aspect of the present disclosure is capable of preventing non-uniformity of in-plane luminance caused by feedthrough voltage.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present disclosure will be described below, with reference to the drawings. The embodiments described below each show a specific example according to the present disclosure. The numerical values, shapes, materials, structural elements, the arrangement and connection of the structural elements, etc. shown in the following embodiments are mere examples, and do not limit the scope of the present disclosure. Of the structural elements in the embodiments described below, the structural elements not recited in any one of the independent claims in the present disclosure are described as optional structural elements.

Each drawing is a schematic and does not necessarily provide precise depiction. The substantially same structural elements are given the same reference signs throughout the drawings, and repeated description is omitted or simplified.

In the specification, the terms indicating the relationships between elements, such as “orthogonal”, “parallel”, and “equal”, the numerical values, and the numerical ranges are not expressions of strict meanings only, but are expressions of meanings including substantially equivalent ranges, for example, allowing for a difference of about several percent (e.g. about 10%).

[1-1. Structure of Display Device]

The structure of a display device according to this embodiment will be described below, with reference toFIG.1toFIG.3.FIG.1is a block diagram illustrating an example of the functional structure of display device1according to this embodiment.FIG.2is an enlarged diagram of a region including dashed line region R inFIG.1. Dashed line region R represents the structure of one pixel column. The structure of two pixel columns adjacent to each other is illustrated inFIG.2.

InFIG.2, pixel110in dashed line region R is first pixel110a, and pixel110connected to the same write signal line WS (for example, write signal line WS1) as first pixel110aand arranged side by side with first pixel110ais second pixel110b. First pixel110aand second pixel110bare pixels110belonging to the same pixel row, and are, for example, adjacent to each other. InFIG.2, each subpixel is indicated as “pixel” for convenience's sake.

In the following description, a signal and wiring for transmitting the signal are given the same reference sign in some cases for simplicity's sake.

As illustrated inFIG.1, display device1includes display panel10, controller20, and power source30. Display panel10includes display11, first gate driver12a, second gate driver12b, data driver13, and selector circuit (data selector circuit)120. Only pixels110(corresponding to subpixels110R illustrated inFIG.2) connected to data voltage line R_Sig from among data voltage lines B_Sig, G_Sig, and R_Sig are illustrated inFIG.1.

Display11includes a plurality of pixels110that are arranged in a matrix and each include light-emitting elements ELB, ELG, and ELR(seeFIG.3). The plurality of pixels110include the foregoing first pixel110aand second pixel110b. In each row of the matrix, a control signal line (gate control line) commonly connected to a plurality of pixels110arranged in the row is provided. In each column of the matrix, data voltage lines B_Sig, G_Sig, and R_Sig (hereafter also referred to as “data voltage line B_Sig, etc.”) commonly connected to a plurality of pixels110arranged in the column are provided.

Data voltage line B_Sig is connected to each subpixel110B belonging to a pixel column including one or more subpixels110B (seeFIG.2), and has a function of supplying data voltage Vdat_b (seeFIG.3) to each subpixel110B. Each subpixel110B is, for example, a blue light-emitting subpixel. These subpixels110B constitute one subpixel column.

Data voltage line G_Sig is connected to each subpixel110G belonging to a pixel column including one or more subpixels110G (seeFIG.2), and has a function of supplying a data voltage to each subpixel110G. Each subpixel110G is, for example, a green light-emitting subpixel. These subpixels110G constitute one subpixel column.

Data voltage line R_Sig is connected to each subpixel110R belonging to a pixel column including one or more subpixels110R, and has a function of supplying data voltage Vdat_r (seeFIG.3) to each subpixel110R. Each subpixel110R is, for example, a red light-emitting subpixel. These subpixels110R constitute one subpixel column.

Hereafter, subpixels110B,110G, and110R are also referred to as “subpixel110B, etc.”, and data voltages Vdat_b, Vdat_g, and Vdat_r are also referred to as “data voltage Vdat_b, etc.”.

Thus, data voltage line B_Sig, etc. are provided for each pixel column in the plurality of pixels110, to charge subpixel110B, etc. with data voltage Vdat_b, etc. corresponding to image data. Hereafter, charging is also referred to as “writing”.

As illustrated inFIG.2, selector circuit120is connected between data voltage line B_Sig, etc. and data driver13, and switches, in a time division manner, data voltage line B_Sig, etc. for supplying data voltage Vdat_b, etc. from data driver13. Selector circuit120includes a plurality of switch portions (for example, switch portions120aand120b). For example, switch portion120ais connected between data voltage line B_Sig, etc. and data integrated circuit (IC)13a, and has a function of selectively supplying data voltage Vdat_b, etc. from data IC13aincluded in data driver13to selected data voltage line B_Sig, etc.

Switch portion120ais provided for each pixel column, and includes selection transistors TSegB, TSegG, and TSegRwhich are thin-film transistors arranged for the respective subpixel columns. Selection transistors TSegB, TSegG, and TSegRare switching transistors for switching the connection between data voltage line B_Sig, etc. and data driver13.

One of the source electrode and the drain electrode of selection transistor TSegBis connected to data voltage line B_Sig, and the other one of the source electrode and the drain electrode is connected to data IC13a. The gate electrode of selection transistor TSegBis connected to selector control line SELL.

One of the source electrode and the drain electrode of selection transistor TSegGis connected to data voltage line G_Sig, and the other one of the source electrode and the drain electrode is connected to data IC13a. The gate electrode of selection transistor TSegGis connected to selector control line SEL2.

One of the source electrode and the drain electrode of selection transistor TSegRis connected to data voltage line R_Sig, and the other one of the source electrode and the drain electrode is connected to data IC13a. The gate electrode of selection transistor TSegRis connected to selector control line SEL3.

As a result of controller20controlling on and off of selection transistors TSegR, TSegG, and TSegRvia selector control lines SEL1, SEL2, and SEL3, selector circuit120supplies data voltage Vdat, etc. from data IC13a(data driver13) to data voltage line B_Sig, etc. In a time division manner. Selector circuit120is a column switching circuit (subpixel column switching circuit) that switches the electrical connection between data IC13aand any of data voltage line B_Sig, etc. Hereafter, selector control lines SEL1, SEL2, and SEL3are also simply referred to as “selector control lines SEL”.

Control signal SEL for controlling selector circuit120is supplied from controller20to each selector control line SEL. For example, selector control line SEL1is connected to the gate electrode of selection transistor TSegB, and control signal SEL1for controlling on and off of selection transistor TSegBis supplied from controller20to selector control line SELL. For example, selector control line SEL2is connected to the gate electrode of selection transistor TSegG, and control signal SEL2for controlling on and off of selection transistor TSegGis supplied from controller20to selector control line SEL2. For example, selector control line SEL3is connected to the gate electrode of selection transistor TSegR, and control signal SEL3for controlling on and off of selection transistor TSegRis supplied from controller20to selector control line SEL3. Selector control line SEL is an example of a first selector control line, and control signal SEL is an example of a selector control signal.

For example, when control signal SEL1input to selector control line SEL1transitions from low level to high level, selection transistor TSegRis turned on, and data voltage Vdat_b from data IC13ais supplied to data voltage line B_Sig. Following this, when control signal SEL1input to selector control line SEL1transitions from high level to low level and then control signal SEL2input to selector control line SEL2transitions from low level to high level, selection transistor TSegBis turned off and selection transistor TSegGis turned on, so that data voltage Vdat_g from data IC13ais supplied to data voltage line G_Sig. Following this, when control signal SEL2input to selector control line SEL2transitions from high level to low level and then control signal SEL3input to selector control line SEL3transitions from low level to high level, selection transistor TSegGis turned off and selection transistor TSegRis turned on, so that data voltage Vdat_r from data IC13ais supplied to data voltage line R_Sig.

Thus, switch portion120aperforms an operation of causing data voltage line B_Sig, etc. connected to switch portion120ato hold data voltage Vdat_b, etc. in a time division manner. In this way, one data IC13acan cause respective data voltage line B_Sig, etc. to hold data voltage Vdat_b, etc. corresponding to pixel currents supplied to light-emitting elements ELB, ELG, and ELR.

The structure of switch portion120bin selector circuit120is the same as that of switch portion120a, and accordingly its description is omitted. Switch portion120bis connected between data voltage line B_Sig, etc. and data IC13b, and has a function of selectively supplying data voltages from data IC13bincluded in data driver13to selected data voltage line B_Sig, etc.

In this embodiment, control signal SEL to selector control line SEL is transferred from right to left on the sheet of the drawing. In other words, controller20supplies control signal SEL to selector control line SEL from the second pixel110bside out of first pixel110aand second pixel110b. That is, controller20supplies control signal SEL to selector control line SEL so as to transfer control signal SEL in a second direction from second pixel110bto first pixel110a.

Selector control lines SEL1, SEL2, and SEL3respectively have input terminals TSb, TSg, and TSr connected to controller20, at the right end on the sheet of the drawing. Selector control lines SEL1, SEL2, and SEL3have no input terminals connected to controller20, at the left end on the sheet of the drawing (the end on the side where WS signal gate driver12a3is located). That is, in the example inFIG.1, the left end on the sheet of the drawing (an example of the end on the first pixel110aside) of selector control lines SEL1, SEL2, and SEL3is not connected to other controller20. Thus, control signal SEL is input to selector control lines SEL1, SEL2, and SEL3from one side.

Data voltage line B_Sig, etc. connected to first pixel110ain dashed line region R are an example of a first data voltage line, and data voltage line B_Sig, etc. connected to second pixel110bin the region adjacent to dashed line region R are an example of a second data voltage line. The first data voltage line and the second data voltage line are, for example, arranged adjacent to each other.

Switch portion120ais not limited to selectively switching between three data voltage lines B_Sig, etc., as long as switch portion120ais configured to selectively switch between two or more data voltage lines B_Sig, etc. Switch portion120aincludes as many selection transistors as data voltage lines B_Sig, etc. to be switched.

Referring back toFIG.1, controller20is a circuit that controls display panel10. Controller20receives a video signal from outside, and controls first gate driver12a, second gate driver12b, data driver13, and selector circuit120so that an image represented by the video signal will be displayed on display11. For example, controller20supplies control signal SEL for controlling selector circuit120, to selector control line SEL. Controller20is connected to only the end on the second pixel110bside (input terminals TSb, TSg, and TSr) of selector control line SEL out of the end on the first pixel110aside and the end on the second pixel110bside.

Power source30supplies operation power of display device1to each component in display device1. Power source30supplies, for example, operation power to display11, first gate driver12a, second gate driver12b, data driver13, controller20, and selector circuit120. Power source30supplies, for example, initialization voltage VINI, reference voltage VREF, positive power source voltage VCC, and negative power source voltage VCATH to display11.

First gate driver12aand second gate driver12bsupply various control signals for controlling the operations of pixels110, to pixels110via control signal lines. First gate driver12afunctions as a scan line drive circuit.

The control signal lines include write signal line WS, initialization signal line INI, and reference signal line REF. Write signal line WS is an example of a first gate control line. Write signal line WS is provided for each pixel row in the plurality of pixels110, and used to supply control signal WS for selecting a pixel row (for example, subpixel row) to which data voltage Vdat_b, etc. corresponding to image data are to be written. Initialization signal line INI is an example of a second gate control line. Initialization signal line INI is provided for each pixel row in the plurality of pixels110, and used to supply control signal INI for initializing the potentials of light-emitting elements ELB, ELG, and ELR. Reference signal line REF is an example of a third gate control line. Reference signal line REF is provided for each pixel row in the plurality of pixels110, and used to supply control signal REF for supplying reference voltage VREF to the gate electrodes of drive transistors TDB, TDG, and TDR(seeFIG.3).

First gate driver12aincludes INI signal gate driver12a1, Ref signal gate driver12a2, and WS signal gate driver12a3. INI signal gate driver12a1, Ref signal gate driver12a2, and WS signal gate driver12a3each include a plurality of shift registers. Each shift register includes, for example, a complementary metal-oxide-semiconductor (CMOS) circuit or a polysilicon thin-film transistor of n-channel type or p-channel type, although not limited to such.

Second gate driver12bincludes INI signal gate driver12b1and Ref signal gate driver12b2. Second gate driver12bdoes not include a WS signal gate driver. Second gate driver12blocated on the side where control signal SEL from controller20is input to selector control line SEL (the right side on the sheet of the drawing) does not include a WS signal gate driver. Thus, in display device1in this embodiment, WS signal gate driver12a3is included only in first gate driver12alocated on the side where control signal SEL from controller20is not input to selector circuit120(the left side on the sheet of the drawing).

INI signal gate drivers12a1and12b1are gate drivers that are connected to the respective gate electrodes of initialization transistors T1B, T1G, and T1R(seeFIG.3) via initialization signal line INI and perform an initialization operation of initializing the potentials of the respective electrodes (for example, anodes) of light-emitting elements ELB, ELG, and ELRincluded in pixel110. INI signal gate drivers12a1and12b1control on and off of initialization transistors T1B, T1G, and T1Rby control signal INI. INI signal gate drivers12a1and12b1input control signal INI from both sides of initialization signal line INI. Control signal INI is an example of a second gate control signal, and INI signal gate driver12a1is an example of a second gate driver. The initialization operation is performed before a threshold compensation operation.

Ref signal gate drivers12a2and12b2are gate drivers that are connected to the respective gate electrodes of compensation transistors T2B, T2G, and T2R(seeFIG.3) via reference signal line REF and perform a threshold compensation operation of compensating the threshold voltages of drive transistors TDB, TDG, and TDR. Ref signal gate drivers12a2and12b2control on and off of compensation transistors T2B, T2G, and T2Rby control signal REF.

Ref signal gate drivers12a2and12b2input control signal REF from both sides of reference signal line REF. Control signal REF is an example of a third gate control signal, and Ref signal gate driver12a2is an example of a third gate driver.

WS signal gate driver12a3is connected to the respective gate electrodes of write transistors T3B, T3G, and T3R(seeFIG.3) via write signal line WS, and cause holding capacitors CSB, CSG, and CSRto respectively hold data voltages Vdat_b, Vdat_g, and Vdat_r. WS signal gate driver12a3supplies control signal WS for controlling on and off of write transistors T3B, T3G, and T3R, to write signal line WS. WS signal gate driver12a3inputs control signal WS from one side of write signal line WS. WS signal gate driver12a3is connected to only the end of write signal line WS on the first pixel110aside out of the end on the first pixel110aside (input terminal TW1, etc.) and the end on the second pixel110bside. Control signal WS is an example of a first gate control signal.

Display device1thus has a structure of inputting the respective control signals to initialization signal line INI and reference signal line REF from both sides of display11and inputting control signal WS to write signal line WS from one side of display11, among write signal line WS, initialization signal line INI, and reference signal line REF. Since the component circuits can be reduced as compared with the case of inputting control signal WS to write signal line WS from both sides of display11, the frame of display device1can be reduced on at least one side.

In this embodiment, control signal WS to write signal line WS is transferred from left to right on the sheet of the drawing, as illustrated inFIG.2. In other words, WS signal gate driver12a3inputs control signal WS to write signal line WS from the left side on the sheet of the drawing, for example, from the first pixel110aside out of first pixel110aand second pixel110b. That is, WS signal gate driver12a3supplies control signal WS to write signal line WS so as to transfer control signal WS in a first direction from first pixel110ato second pixel110b.

The plurality of write signal lines WS each have an input terminal connected to first gate driver12a, at the left end on the sheet of the drawing. For example, of write signal lines WS of n rows (where n is an integer of 2 or more), write signal line WS1has input terminal TW1, write signal line WS2has input terminal TW2, write signal line WSn−1 has input terminal TWn−1, and write signal line WSn has input terminal TWn. The plurality of write signal lines WS each do not have an input terminal connected to second gate driver12b, at the right end on the sheet of the drawing. That is, in the example inFIG.1, the right end of each of the plurality of write signal lines WS on the sheet of the drawing (an example of the end on the second pixel110bside) is not connected to another WS signal gate driver.

Therefore, write signal line WS and selector control line SEL have their input terminals on the sides opposite to each other in the direction in which write signal line WS and selector control line SEL extend (i.e. the horizontal direction on the sheet of the drawing). The respective control signals are input to write signal line WS and selector control line SEL from the sides opposite to each other in the direction. The transfer direction of control signal WS in write signal line WS and the transfer direction of control signal SEL In selector control line SEL are opposite directions.

Referring back toFIG.1, data driver13supplies data voltage Vdat_b, etc. corresponding to luminance to pixel110via data voltage line B_Sig, etc. Data voltage Vdat_b, etc. are each a voltage signal based on display gradation of pixel110. Data driver13outputs data voltage Vdat_b, etc. to data voltage line B_Sig, etc. via selector circuit120in a time division manner, thus driving circuit elements in the light-emitting pixel. Data driver13functions as a signal line drive circuit.

The plurality of pixels110will be described below, with reference toFIG.3.FIG.3is a circuit diagram illustrating an example of the structure of a pixel circuit in display device1according to this embodiment.

As illustrated inFIG.3, pixel (pixel circuit)100includes subpixels (subpixel circuits)110B,110G, and110R. Subpixels110B,110G, and110R have the same structure, except light-emitting elements ELB, ELG, and ELR. The structure of the pixel circuit will be described below, using subpixel110R as an example.

Subpixel110R includes initialization transistor T1R, compensation transistor T2R, write transistor T3R, holding capacitor CSR, drive transistor TDR, and light-emitting element ELR. Initialization transistor T1R, compensation transistor T2R, write transistor T3R, and drive transistor TDRare an example of thin-film transistors included in pixel110. Subpixel110R also includes control signal lines (Initialization signal line INI, reference signal line REF, and write signal line WS), data voltage line R_Sig, positive power source line VCC, and cathode power source line VCATH. Initialization transistor T1Rand compensation transistor T2Rare not essential structural elements.

Initialization transistor T1Ris turned on according to control signal INI, and supplies initialization voltage VINI to the source electrode (source node) of drive transistor TDR. The gate electrode of initialization transistor T1Ris connected to each of INI signal gate drivers12a1and12b1.

Compensation transistor T2Ris turned on according to control signal REF, and supplies reference voltage VREF to the gate electrode (gate node) of drive transistor TDR. This initializes the potential of an electrode (for example, anode) of light-emitting element ELR. The gate electrode of compensation transistor T2Ris connected to each of Ref signal gate drivers12a2and12b2.

Write transistor T3Ris turned on according to control signal WS, and causes holding capacitor CSRto hold data voltage Vdat_r. The gate electrode of write transistor T3Ris connected to WS signal gate driver12a3.

Write transistor T3Ris connected between data voltage line R_Sig and the gate electrode of drive transistor TDR. Specifically, one of the source electrode and the drain electrode of write transistor T3Ris connected to data voltage line R_Sig, and the other one of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of compensation transistor T2Rand the gate electrode of drive transistor TDR.

Holding capacitor CSRholds data voltage Vdat_r supplied via data voltage line R_Sig.

Drive transistor TDRhas one of the source electrode and the drain electrode connected to positive power source line VCC and the other one of the source electrode and the drain electrode connected to the anode of light-emitting element ELR, and supplies current to light-emitting element ELRaccording to data voltage Vdat_r held in holding capacitor CSR. Consequently, light-emitting element ELRemits light at luminance corresponding to data voltage Vdat_r.

Light-emitting element ELRis a self light-emitting element. In this embodiment, light-emitting element ELRis an organic electroluminescent (EL) element. The anode electrode of light-emitting element ELRis connected to one of the source electrode and the drain electrode of drive transistor TDR. A cathode voltage (negative power source voltage) is applied to the cathode electrode of light-emitting element ELRby cathode power source line (negative power source line) VCATH.

InFIG.3, gate potential VgRrepresents the potential of the gate electrode of drive transistor TDR, and source potential VsRrepresents the potential of the source electrode of drive transistor TDR.

Each of the transistors described above is, for example, an n-type thin-film transistor (n-type TFT). Alternatively, each of the transistors may be a p-type thin-film transistor (p-type TFT).

[1-2. Mechanism of Occurrence of Luminance Unevenness and Mechanism of Prevention of Luminance Unevenness]

A mechanism of occurrence of luminance unevenness and a mechanism of prevention of luminance unevenness in display device1will be described below, with reference toFIG.4toFIG.8C.

First, waveform rounding that occurs in control signal WS will be described below, with reference toFIG.4.FIG.4is a diagram illustrating a timing chart of each type of control signal. Specifically, (a) inFIG.4illustrates a timing chart of gate control signals (control signals INI, REF, and WS), and (b) inFIG.4illustrates a timing chart of selector control signals (control signals SEL1to SEL3). The timing charts illustrated inFIG.4are timing charts in one pixel row.

In control signal WS illustrated in (a) inFIG.4, the solid line represents a waveform (pulse waveform) output from WS signal gate driver12a3, and the dashed line represents a waveform (waveform containing rounding) actually supplied to write signal line WS. In each of control signals SEL1, SEL2, and SEL3illustrated in (b) inFIG.4, the solid line represents a waveform (pulse waveform) output from controller20, and the dashed line represents a waveform (waveform containing rounding) actually supplied to selector control line SEL. The waveforms illustrated in (a) and (b) inFIG.4are examples, as the shape of the dashed line (the degree of waveform rounding) can vary depending on the position from the input terminal.

As illustrated in (a) inFIG.4, the period from time t1to time t4is a turnoff period. At time t1, control signal REF transitions from low level to high level to turn on compensation transistors T2B, T2G, and T2R, as a result of which the turnoff period starts. The period from time t2to time t3is an initialization period during which control signal REF is low level, control signal INI is high level, and an initialization operation is performed. The period from time t3to time t4is a threshold compensation period (Vt compensation period) during which control signal REF is high level, control signal INI is low level, and a threshold compensation operation is performed.

The period from time t4to time t5is a period during which data voltage Vdat_b, etc. are supplied to respective data voltage line B_Sig, etc. in time series. During the period from time t4to time t5, data voltage line B_Sig, etc. are selectively charged with data voltage Vdat_b, etc. by selector circuit120, before a data write period. For example, during the period from time t4to time t5, data voltage lines B_Sig, G_Sig, and R_Sig connected to data IC13aare selectively switched in synch with sequential output of data voltages Vdat_b, Vdat_g, and Vdat_r from data IC13aaccording to control signal SEL supplied from controller20, to charge data voltage lines B_Sig, G_Sig, and R_Sig respectively with data voltages Vdat_b, Vdat_g, and Vdat_r.

During the period from time t5to time t6, control signals SEL1, SEL2, and SEL3are each low level, so that data voltage line B_Sig, etc. are in a floating state. During the period from time t5to time t6, control signal WS is high level, so that write transistors T3B, T3G, and T3Rare turned on, and respective data voltage Vdat_b, etc. held in data voltage line B_Sig, etc. are written to holding capacitors CSB, CSG, and CSR. The period from time t5to time t6is a data write period. The data write period is a period that can directly influence pixel current (subpixel current) for controlling gradation display.

The turnoff period is a period for initial setting. Specifically, the turnoff period is a period during which each subpixel circuit is not on (i.e. black display). Suppose the number of pixel rows is n, and one horizontal period is 1H. Then, the turnoff period is, for example, a period of n×H. Herein, “black display” is not limited to complete black display (non-light emission), and includes substantial black display, such as display at less than or equal to predetermined luminance.

As illustrated in (a) inFIG.4, control signal WS has waveform rounding (WS waveform rounding in (a) inFIG.4) due to a signal delay of control signal WS. The waveform rounding in control signal WS is greater when the distance from WS signal gate driver12a3(for example, the distance from the input terminal of write signal line WS) is greater in write signal line WS. The waveform rounding in control signal WS can occur due to a signal delay caused by the parasitic capacitance of pixel110and the wiring resistance of write signal line WS. The parasitic capacitance of pixel110includes the sum of the respective parasitic capacitances between write transistors T3B, T3G, and T3Rand drive transistors TDB, TDG, and TDRin pixel110.

Feedthrough voltage ΔVfs_vg caused as a result of write transistor T3being turned off at time t6will be described below. Let Cws_CR (=Cws_tft/Ctot_vg) be a capacitance ratio where Ctot_vg is the whole parasitic capacitance of pixel110and Cws_tft is the capacitance between the gate of the write transistor (for example, write transistor T3R) in pixel110and a line of the write transistor (for example, the gate-drain capacitance of the write transistor). Feedthrough voltage ΔVfs_vg is calculated according to the following Formula 1, where ΔVws is the amplitude of control signal WS.

When write transistor T3is turned off at time t6, the voltage held in data voltage line B_Sig, etc. decreases from data voltage Vdat_b, etc. by feedthrough voltage ΔVfs_vg calculated according to Formula 1.

Formula 1 indicates feedthrough voltage ΔVfs_vg that occurs when control signal WS is a square wave, that is, when control signal WS has no rounding. In the case where waveform rounding occurs in control signal WS, feedthrough voltage ΔVfs_vg is smaller than in the case where control signal WS is a square wave. When the waveform rounding in control signal WS is greater, feedthrough voltage ΔVfs_vg is smaller. For example, in the case where data voltage Vdat_b, etc. of the same potential are supplied to data voltage line B_Sig, etc. from time t4to time t5, when the waveform rounding in control signal WS is greater, the voltages written to holding capacitors CSB, CSG, and CSRafter write transistor T3is turned off are closer to data voltage Vdat_b, etc. held in data voltage line B_Sig, etc.

Moreover, the waveform rounding in control signal WS is greater at a position farther from the output of WS signal gate driver12a3in write signal line WS, i.e. a position farther from input terminal TW1or the like in write signal line WS, than at a position closer to the output of WS signal gate driver12a3in write signal line WS, i.e. a position closer to input terminal TW1or the like in write signal line WS. Therefore, feedthrough voltage ΔVfs_vg at a position closer to the output of WS signal gate driver12a3in write signal line WS (for example, feedthrough voltages ΔVfs_vg1and ΔVfs_vg3illustrated inFIG.5) is larger than feedthrough voltage ΔVfs_vg at a position farther from the output of WS signal gate driver12a3in write signal line WS (for example, feedthrough voltage ΔVfs_vg2illustrated inFIG.5).

Consequently, in pixel110connected to data voltage line B_Sig, etc. at a position closer to the output of WS signal gate driver12a3in write signal line WS, the decrease in data voltage Vdat_b, etc. after write transistor T3is turned off is greater, which results in smaller pixel current (subpixel current). Meanwhile, in pixel110connected to data voltage line B_Sig, etc. at a position farther from the output of WS signal gate driver12a3in write signal line WS, the decrease in data voltage Vdat_b, etc. after write transistor T3is turned off is smaller, which results in larger pixel current. Thus, the difference in feedthrough voltage ΔVfs_vg depending on the position of pixel110leads to the difference in pixel current, which can cause luminance unevenness.

As illustrated in (b) inFIG.4, control signal SEL has waveform rounding (SEL waveform rounding in (b) inFIG.4) due to a signal delay of control signal SEL. This causes a charging delay of data voltage Vdat_b, etc. to data voltage line B_Sig, etc. The waveform rounding in control signal SEL is greater when the distance from the input terminal is greater in selector control line SEL. The waveform rounding in control signal SEL can occur due to a signal delay caused by the parasitic capacitance between data voltage line B_Sig, etc. and selector control line SEL, the parasitic capacitance of the switch portion (for example, switch portion120a), and the wiring resistance of selector control line SEL. The parasitic capacitance of the switch portion includes the respective gate-source/drain parasitic capacitances of selection transistors TSegB, TSegG, and TSegR.

Feedthrough voltage ΔVfs_sig caused as a result of each of selection transistors TSegB, TSegG, and TSegRbeing turned off in the period from time t4to time t5will be described below. Let Csel_CR (=Csel_tft/Ctot_sig) be a capacitance ratio where Ctot_sig is the whole parasitic capacitance (total parasitic capacitance) between data voltage line B_Sig, etc. and selector control line SEL and Csel_tft is the capacitance between the gate of the selection transistor (for example, selection transistor TSegR) and the source/drain of the selection transistor. Feedthrough voltage ΔVfs_sig is calculated according to the following Formula 2, where ΔVsel is the amplitude of control signal SEL.

When selection transistors TSegB, TSegG, and TSegRare turned off sequentially from time t4to time t5, the voltage held in data voltage line B_Sig, etc. decreases from data voltage Vdat_b, etc. supplied from data driver13by feedthrough voltage ΔVfs_sig calculated according to Formula 2.

Formula 2 indicates feedthrough voltage ΔVfs_sig that occurs when control signal SEL is a square wave, that is, when control signal SEL has no rounding. In the case where waveform rounding occurs in control signal SEL, feedthrough voltage ΔVfs_sig is smaller than in the case where control signal SEL is a square wave. When the waveform rounding in control signal SEL is greater, feedthrough voltage ΔVfs_sig is smaller. For example, in the case where data voltage Vdat_b, etc. of the same potential are output to data voltage line B_Sig, etc. from time t4to time t5, when the waveform rounding is greater, the voltages held in data voltage line B_Sig, etc. after selection transistors TSegB, TSegG, and TSegRare turned off are closer to data voltage Vdat_b, etc. output from data driver13.

Moreover, the waveform rounding in control signal SEL is greater at a position farther from input terminal TSb, etc. in selector control line SEL than at a position closer to input terminal TSb, etc. in selector control line SEL. Therefore, feedthrough voltage ΔVfs_sig at a position closer to input terminal TSb, etc. in selector control line SEL (for example, feedthrough voltages ΔVfs_sig1and ΔVfs_sig3illustrated inFIG.5) is larger than feedthrough voltage ΔVfs_sig at a position farther from input terminal TSb, etc. in selector control line SEL (for example, feedthrough voltage ΔVfs_sig2illustrated inFIG.5).

Consequently, the decrease in data voltage line B_Sig, etc. at a position closer to input terminal TSb, etc. in selector control line SEL after selection transistors TSegB, TSegG, and TSegRin switch portion120aare turned off is greater, which results in smaller pixel current (subpixel current). Meanwhile, the decrease in data voltage line B_Sig, etc. at a position farther from input terminal TSb, etc. in selector control line SEL after selection transistors TSegB, TSegG, and TSegRin switch portion120aare turned off is smaller, which results in larger pixel current. Thus, the difference in feedthrough voltage ΔVfs_sig depending on the position of pixel110leads to the difference in pixel current, which can cause luminance unevenness.

Luminance unevenness in a display device according to a comparative example will be described below, with reference toFIG.5toFIG.6C.FIG.5is a schematic diagram for explaining occurrence of luminance unevenness in the display device according to the comparative example.FIG.6Ais a diagram illustrating the magnitude of feedthrough voltage ΔVfs (ΔVfs_vg) at each pixel position in the display device according to the comparative example.FIG.6Bis a diagram illustrating the magnitude of feedthrough voltage ΔVfs (ΔVfs_sig) at each switch position in the display device according to the comparative example.FIG.6Cis a diagram illustrating the magnitude of feedthrough voltage ΔVfs (total feedthrough voltage) at each in-plane position in the display device according to the comparative example.

In the display device according to the comparative example, control signals are input to each of write signal line WS and selector control line SEL from both sides. The display device according to the comparative example includes WS signal gate drivers12a3and12b3on both sides of display11.

For example, data voltage lines Sig1and Sig3are data voltage lines located at both ends, and data voltage line Sig2is a data voltage line located between data voltage lines Sig1and Sig3, such as at the center of display11. Feedthrough voltages ΔVfs_vg1and ΔVfs_sig1represent feedthrough voltages that occur in pixel110connected to data voltage line Sig1. Feedthrough voltages ΔVfs_vg2and ΔVfs_sig2represent feedthrough voltages that occur in pixel110connected to data voltage line Sig2. Feedthrough voltages ΔVfs_vg3and ΔVfs_sig3represent feedthrough voltages that occur in pixel110connected to data voltage line Sig3.

InFIG.5, T3denotes a write transistor, TD denotes a drive transistor, and EL denotes a light-emitting element, for convenience's sake.

As illustrated inFIG.6A, feedthrough voltage ΔVfs_vg1(position: left) illustrated inFIG.5is large (inclination: steep) because the position is close to WS signal gate driver12a3(e.g. close to the input terminal to which control signal WS from WS signal gate driver12a3is input) and the waveform rounding in control signal WS is small. Likewise, feedthrough voltage ΔVfs_vg3(position: right) illustrated inFIG.5is large (inclination: steep) because the position is close to WS signal gate driver12b3(e.g. close to the input terminal to which control signal WS from WS signal gate driver12b3is input) and the waveform rounding in control signal WS is small. Herein, the “inclination” denotes the inclination of control signal WS, and a steeper inclination corresponds to smaller waveform rounding. The “position” denotes the position of pixel110in display11.

Feedthrough voltage ΔVfs_vg2(position: center) illustrated inFIG.5is smaller (inclination: intermediate) than both ends of write signal line WS because the position is an Intermediate position between WS signal gate drivers12a3and12b3(e.g. the center of display11in the horizontal direction) and the waveform rounding in control signal WS is larger than both ends of write signal line WS.

As illustrated inFIG.6B, feedthrough voltage ΔVfs_sig1(position: left) illustrated inFIG.5is large (inclination: steep) because the position is close to a controller (not illustrated) (e.g. close to the left input terminal of control signal SEL) and the waveform rounding in control signal SEL is small. Likewise, feedthrough voltage ΔVfs_sig3(position: right) illustrated inFIG.5is large (inclination: steep) because the position is close to a controller (not illustrated) (e.g. close to the right input terminal of control signal SEL) and the waveform rounding in control signal SEL is small.

Feedthrough voltage ΔVfs_sig2(position: center) illustrated inFIG.5is smaller (inclination: intermediate) than both ends of control signal SEL (inclination: intermediate) because the position is an intermediate position between the two controllers (e.g. intermediate between the left and right input terminals, such as at the center of display11in the horizontal direction) and the waveform rounding in control signal SEL is greater than in the pixels near the left and right input terminals.

As illustrated inFIG.6C, significant luminance unevenness can occur between the left and right regions and the center region in display11due to the results inFIG.6AandFIG.6B. For example, in the case where data driver13outputs data voltage Vdat_b, etc. of the same potential to each data voltage line including data voltage lines Sig1, Seg2, and Sig3, the luminance is supposed to be uniform in display11. In the display device according to the comparative example, however, the center region is brighter than the left and right regions. In the display device according to the comparative example, the pixel column (left and right pixel columns) with large feedthrough voltage ΔVfs_vg due to waveform rounding in control signal WS and the pixel column (left and right pixel columns) with large feedthrough voltage ΔVfs_sig due to waveform rounding in control signal SEL are the same, and the pixel column (center pixel column) with intermediate feedthrough voltage ΔVfs_vg due to waveform rounding in control signal WS and the pixel column (center pixel column) with intermediate feedthrough voltage ΔVfs_sig due to waveform rounding in control signal SEL are the same. Such feedthrough voltages ΔVfs_vg and &Vfs_sig overlap to cause significant total difference in feedthrough voltage ΔVfs of pixel110between the left and right regions and the center region. In the display device according to the comparative example, this significant difference in pixel current flowing through light-emitting element EL in each pixel110can lead to noticeable luminance unevenness.

As described above, the display device according to the comparative example is likely to have luminance unevenness resulting from overlap of luminance unevenness caused by a delay (signal delay) of control signal WS supplied from WS signal gate drivers12a3and12b3in the horizontal direction (the horizontal direction on the sheet of the drawing) and luminance unevenness caused by a delay (signal delay) of control signal SEL supplied from controller20in the horizontal direction (the horizontal direction on the sheet of the drawing).

Prevention of luminance unevenness in display device1according to this embodiment will be described below, with reference toFIG.7toFIG.8C.FIG.7is a schematic diagram for explaining prevention of luminance unevenness in display device1according to this embodiment.FIG.8Ais a diagram illustrating the magnitude of feedthrough voltage ΔVfs (ΔVfs_vg) at each pixel position in display device1according to this embodiment.FIG.8Bis a diagram illustrating the magnitude of feedthrough voltage ΔVfs (ΔVfs_sig) at each switch position in display device1according to this embodiment.FIG.8Cis a diagram illustrating the magnitude of feedthrough voltage ΔVfs (total feedthrough voltage) at each in-plane position in display device1according to this embodiment.

As illustrated inFIG.8A, feedthrough voltage ΔVfs_vg11(position: left) illustrated inFIG.7is large (inclination: steep) because the position is close to WS signal gate driver12a3(e.g. close to the input terminal to which control signal WS from WS signal gate driver12a3is input) and the waveform rounding in control signal WS is small. Feedthrough voltage ΔVfs_vg12(position: center) illustrated inFIG.7is smaller (inclination: intermediate) than the left end of write signal line WS because the position is the center of display11in the horizontal direction and the waveform rounding in control signal WS is larger than the left end of write signal line WS. That is, feedthrough voltage ΔVfs_vg12is smaller than feedthrough voltage ΔVfs_vg11. The respective magnitudes of feedthrough voltage ΔVfs_vg11and feedthrough voltage ΔVfs_vg12are similar to the respective magnitudes of feedthrough voltage ΔVfs_vg1and feedthrough voltage ΔVfs_vg2in the display device according to the comparative example.

Feedthrough voltage ΔVfs_vg13(position: right) illustrated inFIG.7is smaller than the center because the position is farther from WS signal gate driver12a3(e.g. farther from the input terminal to which control signal WS from WS signal gate driver12a3is input) and the waveform rounding in control signal WS is greater. The magnitude of feedthrough voltage ΔVfs_vg13is smaller than the magnitude of feedthrough voltage ΔVfs_vg12. The magnitude of feedthrough voltage ΔVfs_vg13is smaller than the magnitude of feedthrough voltage ΔVfs_vg3in the display device according to the comparative example.

Thus, in display device1, feedthrough voltage ΔVfs_vg decreases as the distance from WS signal gate driver12a3increases. In the example inFIG.7, feedthrough voltage ΔVfs_vg decreases in the rightward direction.

As illustrated inFIG.8B, feedthrough voltage ΔVfs_sig13(position: right) illustrated inFIG.7is large (inclination: steep) because the position is close to controller20(e.g. close to the input terminal of control signal SEL) and the waveform rounding in control signal WS is small. Feedthrough voltage ΔVfs_sig12(position: center) illustrated inFIG.7is smaller (inclination: intermediate) than in pixel110at the right end because the position is the center of display11in the horizontal direction and the waveform rounding in control signal SEL is greater than in pixel110near the input terminal. That is, feedthrough voltage ΔVfs_sig12Is smaller than feedthrough voltage ΔVfs_sig13. The respective magnitudes of feedthrough voltage ΔVfs_sig12and feedthrough voltage ΔVfs_sig13are similar to the respective magnitudes of feedthrough voltage ΔVfs_sig2and feedthrough voltage ΔVfs_sig3in the display device according to the comparative example.

Feedthrough voltage ΔVfs_sig11(position: left) illustrated inFIG.7is smaller than the center because the position is farther from controller20(e.g. farther from the input terminal of control signal SEL) and the waveform rounding in control signal SEL is greater. The magnitude of feedthrough voltage ΔVfs_sig11is smaller than the magnitude of feedthrough voltage ΔVfs_sig12. The magnitude of feedthrough voltage ΔVfs_sig11is smaller than the magnitude of feedthrough voltage ΔVfs_sig1in the display device according to the comparative example.

Thus, in display device1, feedthrough voltage ΔVfs_sig decreases as the distance from the input terminal connected to controller20increases. In the example inFIG.7, feedthrough voltage ΔVfs_sig decreases in the leftward direction.

As illustrated inFIG.7, in display device1, data voltage line Sig13at a position where the waveform rounding in control signal SEL of selector circuit120is minimum is orthogonal to write signal line WS at a point where the waveform rounding in control signal WS is maximum in write signal line WS (for example, position of rightmost pixel110in display11). As illustrated inFIG.7, in display device1, data voltage line Sig11at a position where the waveform rounding in control signal SEL of selector circuit120is maximum is orthogonal to write signal line WS at a point where the waveform rounding in control signal WS is minimum in write signal line WS (for example, position of leftmost pixel110in display11).

As illustrated inFIG.8C, luminance unevenness between the left and right regions and the center region in display11can be prevented in display device1due to the results inFIG.8AandFIG.8B. For example, in the case where data driver13outputs data voltage Vdat_b, etc. of the same potential to each data voltage line including data voltage lines Sig1, Seg2, and Sig3, the in-plane brightness is likely to be uniform in display device1as compared with the display device according to the comparative example. In display device1, the pixel column (for example, left pixel column) with large feedthrough voltage ΔVfs_vg due to waveform rounding in control signal WS and the pixel column (for example, left pixel column) with small feedthrough voltage ΔVfs_sig due to waveform rounding in control signal SEL overlap, the pixel column (for example, right pixel column) with small feedthrough voltage ΔVfs_vg and the pixel column (for example, right pixel column) with large feedthrough voltage ΔVfs_sig overlap, and the pixel column (for example, center pixel column) with intermediate feedthrough voltage ΔVfs_vg and the pixel column (for example, center pixel column) with intermediate feedthrough voltage ΔVfs_sig overlap. Accordingly, total feedthrough voltage ΔVfs in each pixel110resulting from such overlap of feedthrough voltages ΔVfs_vg and ΔVfs_sig can be made uniform. Thus, in display device1, uniform pixel current flows through light-emitting element EL in each pixel110, with it being possible to prevent luminance unevenness.

As described above, in display device1, the uniformity of in-plane luminance in display11can be improved with no need to incorporate a complex correction system (for example, arithmetic IC). Display device1can thus achieve both low cost and improved display quality.

As described above, display device1according to this embodiment includes: a plurality of pixels110arranged in a matrix; a plurality of write signal lines WS that are each located at a different pixel row in the plurality of pixels110, and to which control signal WS is supplied, control signal WS being for selecting a pixel row to which data voltage Vdat_b, etc. corresponding to image data is to be written; WS signal gate driver12a3that supplies control signal WS to the plurality of write signal lines WS; a plurality of data voltage lines B_Sig, etc. that are each located at a different pixel column in the plurality of pixels110, and used to write data voltage Vdat_b, etc. corresponding to the image data; data driver13that supplies data voltage Vdat_b, etc. to the plurality of data voltage lines B_Sig, etc.; selector circuit120that is connected between data driver13and the plurality of data voltage lines B_Sig, etc., and switches data voltage line B_Sig, etc. to which data voltage Vdat_b, etc. from data driver13is supplied among the plurality of data voltage lines B_Sig, etc.; selector control line SEL to which control signal SEL for controlling selector circuit120is supplied; and controller20that supplies control signal SEL to selector control line SEL. The plurality of pixels110include first pixel110aand second pixel110bthat belong to a same pixel row. WS signal gate driver12a3supplies control signal WS to the plurality of write signal lines WS to transfer control signal WS in a first direction from first pixel110ato second pixel110b, and controller20supplies control signal SEL to selector control line SEL to transfer control signal SEL in a second direction from second pixel110bto first pixel110a.

Thus, in display device1, the total value of feedthrough voltage ΔVfs in pixel110combining feedthrough voltage ΔVfs_sig due to waveform rounding in control signal SEL and feedthrough voltage ΔVfs_vg due to waveform rounding in control signal WS can be made uniform as compared with the display device according to the comparative example. For example, in the case of causing light-emitting elements ELB, ELG, and ELRto emit light by the same data voltage Vdat_b, etc., display device1can reduce the difference in pixel current flowing through light-emitting elements ELB, ELG, and ELRas compared with the display device according to the comparative example. Hence, display device1according to this embodiment can prevent non-uniformity of in-plane luminance caused by feedthrough voltage ΔVfs. That is, display device1can prevent luminance unevenness caused by feedthrough voltage ΔVfs.

WS signal gate driver12a3is connected to, out of respective ends of each of the plurality of write signal lines WS on a first pixel110aside and a second pixel110bside, only the end (e.g. input terminal) on the first pixel110aside, the first pixel110aside being a side closer to first pixel110a, the second pixel110bside being a side closer to second pixel110b. Controller20is connected to, out of respective ends of selector control line SEL on the first pixel110aside and the second pixel110bside, only the end (e.g. input terminal) on the second pixel110bside.

Thus, in display device1, the value of feedthrough voltage ΔVfs in pixel110can be made further uniform. Moreover, in display device1, the number of inputs of each of write signal line WS and selector control line SEL can be reduced as compared with the case where control signals are input from both sides of each of write signal line WS and selector control line SEL. Display device1that can further prevent non-uniformity of in-plane luminance caused by feedthrough voltage ΔVfs can therefore be provided at low cost.

The end of each of the plurality of write signal lines WS on the second pixel110bside is not connected to an other gate driver, and the end of selector control line SEL on the first pixel110aside is not connected to an other controller.

Thus, in display device1, the number of WS signal gate drivers for supplying control signal WS and the number of controllers for supplying control signal SEL can be reduced. For example, the number of ICs for control signal WS and the number of ICs for control signal SEL can be reduced. Display device1can therefore achieve both low cost and luminance unevenness prevention (i.e. improved display quality).

The light-emitting element EL is an organic EL element.

Thus, luminance unevenness in an organic EL display panel can be prevented.

[2-1. Structure of Display Device]

A display device according to this embodiment will be described below, with reference toFIG.9.FIG.9is a schematic diagram for explaining prevention of luminance unevenness in the display device according to this embodiment. The differences from Embodiment 1 will be mainly described below, while omitting or simplifying the description of the elements that are the same as or similar to those in Embodiment 1. The display device according to this embodiment differs from display device1according to Embodiment 1 in that WS signal gate driver12b3is included and in the input position of the control signal to the selector control line (first selector control line SELa and second selector control line SELb). The gate drivers other than the WS signal gate drivers are omitted inFIG.9.

As illustrated inFIG.9, the display device according to this embodiment includes WS signal gate drivers12a3and12b3on both sides of display11. The display device according to this embodiment supplies control signal WS from both sides of write signal line WS. Write signal line WS has respective input terminals connected to WS signal gate drivers12a3and12b3, at both ends. Specifically, write signal line WS has input terminal TWa connected to WS signal gate driver12a3and input terminal TWb connected to WS signal gate driver12b3.

WS signal gate driver12a3supplies control signal WS to write signal line WS so as to transfer control signal WS in a first direction from first pixel110ato second pixel110b. WS signal gate driver12b3supplies control signal WS to write signal line WS so as to transfer control signal WS in a second direction from second pixel110bto first pixel110a.

In this way, the waveform rounding in control signal WS is similar to that in the corresponding part of the display device according to the comparative example of Embodiment 1.

WS signal gate driver12b3is an example of a fourth gate driver.

Selector control line SEL for controlling selector circuit120includes first selector control line SELa and second selector control line SELb. First selector control line SELa has input terminal TS1for connecting to controller20. Second selector control line SELb has input terminal TS2for connecting to controller20. Input terminals TS1and TS2may be, for example, located near each other. Two controllers20are implemented by different ICs as an example.

First selector control line SELa is connected to controller20at a position between both ends of the pixel row (center position in the horizontal direction), and extends from the position toward the first pixel110aside.

Second selector control line SELb is connected to controller20at the position between both ends of the pixel row (center position in the horizontal direction), and extends from the position toward the second pixel110bside.

The position is, for example, the center position in the pixel row, although not limited to such. For example, first selector control line SELa and second selector control line SELb are transfer paths from the center to the left and right sides in the pixel row. The transfer direction of control signal SELa in first selector control line SELa and the transfer direction of control signal SELb in second selector control line SELb are opposite directions. For example, the transfer direction of control signal WS supplied from WS signal gate driver12a3and the transfer direction of control signal SELa in first selector control line SELa are opposite directions, and the transfer direction of control signal WS supplied from WS signal gate driver12b3and the transfer direction of control signal SELb in second selector control line SELb are opposite directions.

The same control signal is input to first selector control line SELa and second selector control line SELb. A control signal for supplying data voltage Vdat_b, etc. to the same data voltage line (data voltage line to which pixels110emitting light of the same color are connected) from among data voltage line B_Sig, etc. is input to first selector control line SELa and second selector control line SELb.

Although it appears inFIG.9that neither first selector control line SELa nor second selector control line SELb is connected to data voltage line Sig2, one of first selector control line SELa and second selector control line SELb is connected to data voltage line Sig2.

As described above, in the display device according to this embodiment, first selector control line SELa is connected to controller20at a position between both ends of the pixel row, and extends from the position toward the first pixel110aside. The display device further includes WS signal gate driver12b3that supplies control signal WS to the plurality of write signal lines WS from the second pixel110bside out of first pixel110aand second pixel110b, and second selector control line SELb that is connected to controller20at the position and extends from the position toward the second pixel110bside.

Thus, the display device supplies control signal WS from both sides of write signal line WS, and accordingly can achieve high performance such as high-speed operation. Moreover, since control signal SEL can be supplied to selector control line SEL from between both ends of the pixel row, luminance unevenness caused by feedthrough voltage ΔVfs can be prevented as compared with the case where control signal SEL is supplied from both ends. Display device1can therefore achieve both high performance and prevention of non-uniformity of in-plane luminance.

The position between both ends of the pixel row is a center position in the pixel row.

Thus, control signal SEL can be input from the center position in display11, so that first selector control line SELa and second selector control line SELb can be equal in length. That is, feedthrough voltage ΔVfs_sig that occurs in first selector control line SELa on the left side and feedthrough voltage ΔVfs_sig that occurs in second selector control line SELb on the right side can be made equal. Since display device1can prevent the difference in feedthrough voltage ΔVfs_sig caused by the difference in length between first selector control line SELa and second selector control line SELb, non-uniformity of in-plane luminance can be further prevented.

[3-1. Structure of Display Device]

A display device according to this embodiment will be described below, with reference toFIG.10.FIG.10is a block diagram illustrating an example of the functional structure of display device1aaccording to this embodiment. The differences from Embodiment 1 will be mainly described below, while omitting or simplifying the description of the elements that are the same as or similar to those in Embodiment 1. Display device1aaccording to this embodiment differs from display device1according to Embodiment 1 in that second gate driver12bis not included.

As illustrated inFIG.10, display panel10ain display device1aincludes first gate driver12aonly on one side of display11. Display device1adoes not include a control circuit such as a gate driver on the side (the right side of display11in the example inFIG.10) opposite to first gate driver12a. Display device1ais located only at the end on the first pixel110aside out of the first pixel110aside and the second pixel110bside.

WS signal gate driver12a3is an example of a first gate driver, INI signal gate driver12a1is an example of a second gate driver, and Ref signal gate driver12a2is an example of a third gate driver.

As described above, each of the plurality of pixels110included in display device1aaccording to this embodiment includes light-emitting element EL. Display device1afurther includes: drive transistor TD connected to an anode of light-emitting element EL; a plurality of initialization signal lines INI that are each located at a different pixel row in the plurality of pixels110, and to which control signal INI for Initializing potentials of light-emitting elements ELB, ELG, and ELRis supplied; INI signal gate driver12a1that supplies control signal INI to the plurality of initialization signal lines INI; a plurality of reference signal lines REF that are each located at a different pixel row in the plurality of pixels110, and to which control signal REF for supplying reference voltage VREF to a gate electrode of drive transistor TD is supplied; and Ref signal gate driver12a2that supplies control signal REF to the plurality of reference signal lines REF. WS signal gate driver12a3, INI signal gate driver12a1, and Ref signal gate driver12a2are located only on a side closer to first pixel110a, out of the side closer to first pixel110aand a side closer to second pixel110b.

Thus, three gate drivers are located only on one side of display panel10a. This makes it possible to reduce the layout area of drive circuitry around display11, so that narrow-frame display device1acan be provided. Since display device1ahas no gate driver on one side of its frame, the range of applications of display device1aas a product is expected to widen.

Other Embodiments

Although the display device according to the present disclosure has been described by way of each of the foregoing embodiments, the display device according to the present disclosure is not limited to the foregoing embodiments. Other embodiments obtained by combining any structural elements in the foregoing embodiments, modifications obtained by applying various changes conceivable by a person skilled in the art to the foregoing embodiments without departing from the scope of the present disclosure, and various appliances including any of the display devices according to the embodiments are also included in the present disclosure.

For example, display device1according to the present disclosure may be implemented as a flat display device as illustrated inFIG.11.FIG.11is a perspective diagram illustrating the appearance of display device1according to Embodiment 1. Such display device1can prevent luminance unevenness in display11. The display device according to Embodiment 2 and display device1aaccording to Embodiment 3 may each be equally implemented as such a flat display device. The display device according to the present disclosure is not limited to any particular use. The display device may be used in portable information terminals, personal computers, televisions, digital signage, and so on.

Although the foregoing embodiments each describe an example in which the light-emitting elements included in the display device are organic EL elements, the light-emitting elements are not limited to such. The light-emitting elements may be any other type of self light-emitting elements. For example, the light-emitting elements may be light-emitting elements using quantum-dot light-emitting diodes (QLEDs).

Although the foregoing embodiments each describe an example in which each pixel circuit includes a single-gate write transistor, the pixel circuit is not limited to such, and may include a double-gate write transistor. In such a case, for example, a first WS signal gate driver supplies, in a first direction, a control signal to a write signal line to which one write transistor of the double-gate write transistor is connected, and a second WS signal gate driver supplies, in a second direction opposite to the first direction, a control signal to a write signal line to which the other write transistor of the double-gate write transistor is connected. The display device may not include a selector circuit in this case.

Amplitudes ΔVsel and ΔVws in each of the foregoing embodiments may be the same. That is, the potential difference between low level and high level in a first gate control signal and the potential difference between low level and high level in a selector control signal may be equal.

Each of the structural elements such as the first gate driver, the second gate driver, the data driver, and the controller in each of the foregoing embodiments may be configured in the form of an exclusive hardware product, or may be realized by executing a software program suitable for the structural element. Each of the structural elements may be realized by means of a program executing unit, such as a CPU or a processor, reading and executing the software program recorded on a recording medium such as a hard disk or a semiconductor memory. The processor includes one or more electronic circuits including semiconductor integrated circuit (IC) or large scale integration (LSI). The IC may be directly mounted on a TFT substrate of a display panel by chip-on-glass (COG) technology, or mounted on a flexible wiring substrate such as a flexible flat cable (FFC) or a flexible printed cable (FPC) by chip-on-film (COF) technology.

The first gate driver in each of the foregoing embodiments may be implemented by one IC, or the WS signal gate driver, the Ref signal gate driver, and the INI signal gate driver may each be implemented by a different IC.

The second gate driver in each of Embodiments 1 and 3 may be implemented by one IC, or the Ref signal gate driver and the INI signal gate driver may each be implemented by a different IC.

The second gate driver in Embodiment 2 may be implemented by one IC, or the WS signal gate driver, the Ref signal gate driver, and the INI signal gate driver may each be implemented by a different IC.

The display device in Embodiment 2 may have a structure in which only the WS signal gate driver is located on both sides of the display and the Ref signal gate driver and the INI signal gate driver are located on one side of the display.

The controller and the data driver in each of the foregoing embodiments may be implemented by one IC, or may each be implemented by a different IC.

In each of the foregoing embodiments, for example, initialization transistors T1Gand T1Bmay have the same function and structure as initialization transistor T1R, compensation transistors T2Gand T2Bmay have the same function and structure as compensation transistor T2R, write transistors T3Gand T3Bmay have the same function and structure as write transistor T3R, and drive transistors TDGand TDBmay have the same function and structure as drive transistor TDR.

In each of the foregoing embodiments, for example, light-emitting elements ELGand ELBmay have the same function and structure as light-emitting element ELR.

In each of the foregoing embodiments, for example, holding capacitors CSGand CSBmay have the same function and structure as holding capacitor CSR.

Although the foregoing embodiments each describe an example in which the display device displays color images, the display device is not limited to such, and may display, for example, monochrome images.

In each of the foregoing embodiments, for example, the write signal lines and the selector control lines may be parallel to the pixel rows.

INDUSTRIAL APPLICABILITY

The presently disclosed techniques are useful, for example, for display devices including organic EL elements.