Code memory capable of code provision for a plurality of physical channels

The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to signal correlation, and more particularly to code storing codes for signal correlation.

2. Description of the Related Art

In a communications system such as a Global Positioning System (GPS), both a signal transmitter and a signal receiver must comprise a code generator for code provision. Before raw data is transmitted by a signal transmitter, the signal transmitter modulates the raw data according to a code to obtain a modulated signal. The signal transmitter than sends the modulated signal through the air to a signal receiver. After the signal receiver receives the modulated signal, the signal receiver must then demodulate the received signal before the received signal is further processed. The signal receiver correlates the received signal with a code to demodulate the received signal. Thus, both a transmitter and a receiver of a communication system must comprise a code generator for generating a code for signal processing.

In a GPS system, a code can be generated according to a predetermined algorithm. A code generator of a GPS system therefore has a simple structure for code generation. In one embodiment, a code generator of a GPS system comprises a linear feedback shift register generating a code. A Galileo system, however, adopts a pseudo random sequence as a code for signal processing, such as codes for E1-B and E1-C bands of a Galileo system. Because the E1-B band code and the E1-C band code of a Galileo system cannot be directly generated with a shift register, a code generator of a Galileo system must therefore comprise a code memory for storing the code, before the code generator can then retrieve the code from the code memory for signal processing.

When a signal processor of a receiver processes an input signal, a code with a specific phase is required. A code generator therefore must provide a code with a specific code phase as soon as possible. If the code generator can provide a code with a short delay period, signal processing of the signal processor can be accelerated, and performance of the receiver is improved. In addition, when the signal processor processes different segments of the input signal, code segments with different phases are required. The code generator must therefore provide the code segments with phase jumps therebetween. When the code generator provides the signal processor with a current code segment for correlation, the code generator can simultaneously prepare a subsequent code segment in advance. Thus, when the correlation of the current code segment is completed, the subsequent code segment can then be immediately provided to the signal processor without delay, improving system performance. Thus, a memory code generator capable of generating a correlation code with little delay is required.

In addition, when a receiver processes signals corresponding to a plurality of satellites, a code generator of the receiver must provide codes corresponding to the plurality of satellites. The code generator therefore must comprise a code memory storing a plurality of codes corresponding to the satellites. Because the receiver may simultaneously request the codes corresponding to different satellites, the code memory therefore must comprise a mechanism for handling the requests for codes corresponding to different satellites. A code memory capable of providing codes corresponding to a plurality of satellites is therefore required.

BRIEF SUMMARY OF THE INVENTION

The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a multiplexer circuit and a core memory module. The multiplexer circuit performs an OR operation on a plurality of addresses generated by the plurality of physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal.

The invention also provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

The invention provides a method for code provision for a plurality of physical channels. First, code data is stored in a core memory module. A plurality of addresses generated by the physical channels are then repeatedly latched according to a sequence of the physical channels to generate a code memory address signal. The code data is then retrieved according to the code memory address signal from the core memory module to generate a code memory data signal. A plurality of code segments requested by the physical channels is then retrieved from the code memory data signal according to the sequence of the physical channels. The code segments are then stored in a plurality of buffers.

DETAILED DESCRIPTION OF THE INVENTION

When a signal processor processes an input signal according to a code, a code generator must provide the signal processor with the code for correlation. A code generator may be required to provide a code with a fixed phase jump or a variable phase jump. Referring toFIG. 1, a schematic diagram of provided codes with different phase jumps is shown. A code generator provides code segments with different phases in different correlation regions. The phase difference between two adjacent code segments is referred to as a phase jump. In a first embodiment, a code generator is required to provide a code segment112corresponding to a current correlation region K and a code segment114corresponding to a next correlation region K+1. Compared to the code segment112comprising code samples (CN-1, . . . , C0), the code segment114comprising code samples (CN-1+G, . . . , CG) has a fixed phase jump of G samples.

In a second embodiment, the code generator is required to provide three code segments122a,122b, and122ccorresponding to a current correlation region K and three code segments124a,124b, and124ccorresponding to a next correlation region K+1. The phase jumps between the code segments122a˜122care of a width of one sample. The phase jump between the code segments122cand124a, however, is of a width of G samples. Thus, the code provided by the code generator in the second embodiment has a variable phase jump. In a third embodiment, the phase jump between the code segment132aand132bis of a width of one sample, but the phase jump between the code segments132band132cis of a width of 2 samples. Thus, the code provided by the code generator in the third embodiment also has a variable phase jump. A memory code generator must therefore comprise a mechanism for efficiently providing code segments with different phase jumps to meet system requirements.

Referring toFIG. 2, a block diagram of a memory code generator200providing a correlation code according to the invention is shown. The memory code generator200comprises a code memory202, a preparation buffer set204, and a correlation buffer set206. The preparation buffer set204is coupled between the code memory202and the correlation buffer set206. The code memory202stores code data. In one embodiment, the code data is for correlation of Galileo E1 band signal. The preparation buffer set204retrieves a code segment of the code data from the code memory, and shifting samples of the code segment, thus obtaining a code segment with a desired phase required by the correlation buffer set206. The correlation buffer set206then loads the code segment with a desired phase from the preparation buffer set, and directly provides a correlation code for correlation according to the loaded code segment.

When the correlation buffer set206is providing a correlation code for correlation according to a current code segment, the preparation buffer set204shifts a subsequent code segment to a desired phase. Thus, after correlation of the current code segment is completed, the preparation buffer set204can directly provide the correlation buffer set with the subsequent code segment with no delay, preventing breaks in correlation, to improve system performance.

Referring toFIG. 3, a block diagram of an embodiment of a memory code generator300according to the invention is shown. The memory code generator300comprises a code memory, two preparation buffers304aand304b, two correlation buffers306aand306b, and a code selector308. The code memory302stores code data. The preparation buffers304aand304bform the preparation buffer set204ofFIG. 2, and the correlation buffers306aand306bform the correlation buffer set206ofFIG. 2. Both the preparation buffers304aand304band the correlation buffers306aand306bare shift registers. In addition, the preparation buffers304aand304band the correlation buffers306aand306bhave a buffer width of N bits and can therefore store an N-bit code segment. In one embodiment, the buffer width N is a word length of the code memory302, and the preparation buffers304aand304bcan therefore directly load code words from the code memory302with one memory access.

The preparation buffer304bis coupled to a tail of the preparation buffer304a. Thus, after the preparation buffers304aand304bretrieve two adjacent code segments from the code memory302, the preparation buffers304aand304bcan shift phases of the adjacent code segments to a desired phase suitable for correlation. Accordingly, the correlation buffer306bis coupled to a tail of the correlation buffer306a. After the correlation buffers306aand306bload code segments from the preparation buffer set, the correlation buffers306aand306bcan still shift phases of the code segments to provide a correlation code with slightly changed code phases. The code selector308can then selects an output code (C0, . . . , CM-1) from code bits stored in the correlation buffers306aand306band then outputs the code (C0, . . . , CM-1) for correlation.

A coupling between the preparation buffer set and the correlation buffer set can be dynamically adjusted. The correlation buffers306aand306bare respectively coupled to the preparation buffers304aand304b. In a setup mode at initiation of a large phase jump, the correlation buffers306aand306bcan therefore directly load code segments with desired phases from preparation buffers304aand304b. In an intermediate mode subsequent to the setup mode, when all the code loaded to the correlation buffer306bis shifted to the correlation buffer306ato leave an empty correlation buffer306b, the correlation buffer306bloads a code segment from the preparation buffer304b. In a normal mode, the head of the preparation buffer304ais connected to the tail of the correlation buffer306b, and the code stored in the preparation buffer304ais shifted to the correlation buffer306band then to the correlation buffer306a. The operation of the preparation buffers304aand304band the correlation buffers306aand306bare illustrated inFIGS. 4A˜4FandFIG. 5.

FIG. 4A˜4Fare a series of schematic diagrams showing operations of the preparation buffers304aand304band the correlation buffers306aand306bofFIG. 3. Meanwhile,FIG. 5is a flowchart of a method500for operating the preparation buffers304aand304band the correlation buffers306aand306bofFIG. 3. As aforementioned descriptions, the memory code generator300has three operating modes including a setup mode, an intermediate mode, and a normal mode, whereinFIGS. 4A and 4Bcorrespond to the setup mode,FIGS. 4C and 4Dcorrespond to the intermediate mode, andFIGS. 4E and 4Fcorrespond to the normal mode.

When the memory code generator300is required to provide a code with a large phase jump, the operating mode of the memory code generator300is switched to a setup mode. Assume that the code memory302stores a series of code words401,402,403,404,405, and406. Referring toFIG. 4A, in a set-up mode, the preparation buffers304aand304bfirst respectively load a first code word401and a second code word402from the code memory302. The preparation buffers304aand304bthen shift the code words401and402to obtain a code segment with a code phase required for correlation (steps502and504), as shown inFIG. 4B.

When the code segment stored in the preparation buffers304aand304bhas a desired code phase for correlation, the memory code generator300is switched into a push-to-B operating mode. The correlation buffers306aand306bthen directly load the code segment from the preparation buffers304aand304b, and the preparation buffers304aand304brespectively load a fourth code word404and a third code word403from the code memory302(step506), as shown inFIG. 4C. The correlation buffers306aand306bthen gradually shifts the code segment stored therein to provide a correlation code. In one embodiment, the code selector308selects the code segment stored in the correlation buffer306aas an output correlation code. After all the code originally stored in the correlation buffer306bis shifted to the correlation buffer306a, the correlation buffer306bis empty (step510). The correlation buffer306bthen loads the third code word403from the preparation buffer304b(step512), as shown inFIG. 4D. The head of the preparation buffer304ais next connected to the tail of the correlation buffer306b.

Next, the memory code generator300is switched to a normal operating mode. Because the head of the preparation buffer304ais next connected to the tail of the correlation buffer306b, a chain comprising the preparation buffer304a, the correlation buffer306b, and correlation buffer306ais formed to shift code bits from the preparation buffer304ato the correlation buffer306a(step516). Thus, the code selector308can then continue to extract correlation codes with shifted phases from the correlation buffer306aand306b. Whenever the preparation code buffer304ais empty (step520), the preparation code buffer304adirectly loads a subsequent code word from the code memory302as a source shifted to the correlation buffer306b(step524), as shown inFIGS. 4E and 4F. Thus, the code selector308can continue to provide a code for correlation if a large phase jump is not required.

When a subsequent correlation code with a large phase jump is required, the memory code generator300is switched back to a setup mode (steps508,514,518, and522), and the preparation buffers304aand304bload a subsequent correlation code from the code memory302and shift the subsequent correlation code to a desired code phase required for correlation when the correlation buffer306ais still providing the code selector308with a current correlation code. Thus, when correlation of the current code is completed, the correlation buffer306aand306bcan directly load the subsequent code with a large phase jump from the preparation buffer304aand304bwithout delay, and system performance is therefore greatly improved.

There are three code generation situations inFIG. 1. For a first code generation situation ofFIG. 1, the memory code generator300can repeat operations of the setup mode shown inFIGS. 4A and 4Bto generate a memory code with fixed code phase jumps. For a second code generation situation ofFIG. 1, the memory code generator300can sequentially performs operations of the setup mode, the intermediate mode, and the normal mode shown inFIGS. 4A˜4Fto generate a memory code with variable code phase jumps. For a third code generation situation ofFIG. 1, a memory code with small code phase jumps is required. The memory code generator300then generates the memory code with small code phase jumps with the code selector308, which selects codes with required phase jumps as an output code.

The ping-pong concept for simultaneously operating a correlation buffer set and a preparation buffer set can be further applied to other embodiments of a memory code generator. Referring toFIG. 6A, a block diagram of an embodiment of a memory code generator600according to the invention is shown. The memory code generator600comprises a code memory602, a raw code allocator603, a plurality of code pipes605a˜605k, and a code selector608. The code memory602stores code data. The raw code allocator603sequentially retrieves a series of code segments of the code data from the code memory602and respectively allocates the code segments to one of the code pipes605a˜605k.

The code pipes605a˜605krespectively store the code segments allocated by the raw code allocator603. In one embodiment, the code pipes605a˜605kare shift registers. When the code pipes605a˜605kreceives code segments from the raw code allocator603, the code pipes605a˜605kshift the phases of the code segments to desired phases required by the code selector608for correlation. The code selector then retrieves the code segments from the code pipes605a˜605kaccording to the sequence of the code segments to provide a correlation code for correlation. The code pipes605a˜605k, however, do not operate at the same phases. When one of the code pipes605a˜605kis busy providing the code selector608with a current code segment as a correlation code as the correlation buffers306aand306bofFIG. 3, the other code pipes shift the code segments stored therein to obtain the code segments with desired code phases required by the code selector608as the preparation buffers304aand304bofFIG. 3. Thus, when correlation of the current code segment is completed, the code selector608can directly retrieve a next code segment with a desired phase from one of the code pipes with no delay. In other words, the code pipes605a˜605kdynamically switch between playing the roles of a preparation buffer and a correlation buffer to improve system performance.

FIGS. 7A˜7Care a series of schematic diagrams showing operation of the code pipes605a˜605kof the memory code generator600ofFIG. 6. Referring toFIG. 7A, a code pipe605ais playing a role of a correlation buffer providing a code segment stored therein to the code selector608. Other code pipes except for the correlation buffer605aplay a role of a preparation buffer preparing a code segment with a desired phase. Referring toFIG. 7B, the code pipe605ais delivering a partial correlation code segment to the code selector608, the code pipe605bis shifting the correlation code stored therein to a desired phase, and the code pipe605kis retrieving a raw code from the raw code allocator603. Each code pipe handles its correlation code independently, and when a code selector608requires a correlation code with a desired phase, one of the code pipes605a˜605kdirectly provide the code selector608with the correlation code without delay. Thus, after correlation of the code segment of the code pipe605ais completed, the code pipe605bwould then directly provide the code selector608with the subsequent code segment with a phase jump without delay.

A receiver sometimes handles signal processing of a plurality of satellites and requires a plurality of correlation codes corresponding to the satellites. Referring toFIG. 6B, a block diagram of another embodiment of a memory code generator650capable of providing correlation codes corresponding to a plurality of satellites according to the invention is shown. The memory code generator650comprises a code memory652, a raw code allocator653, a plurality of code pipe pairs655a1˜605k2, and a code selector658.

The code memory652comprises a plurality of memories652a˜652k. Each of the memories652a˜652kstores a code corresponding to one of a plurality of satellites. Thus, the code memory652stores codes corresponding to a plurality of satellites. Each of the code pipe pairs655a˜655kcomprises two code pipes. For example, the code pipe655acomprises code pipes655a1and655a2. In one embodiment, the code pipes655a1˜655k2are all shift registers. The raw code allocator653comprises a plurality of switches653a˜653k, each retrieving a series of code segments corresponding to a satellite from one of the memories652a˜652k, and alternately allocating the code segments to one of the two code pipes of a code pipe pair dedicated to the corresponding satellite.

The two code pipes of a code pipe pair switches between playing roles of a preparation buffer and a correlation buffer. When one of the two code pipes provides the code selector658with a shifted code segment with a desired phase, the other of the two code pipes shifts a raw code segment received from the raw code allocator653to obtain a shifted code segment with a desired phase required by the code selector658. The code selector658comprises a plurality of multiplexer658a˜658kand an end multiplexer659. Each of the multiplexers658a˜658kretrieves a shifted code segment from one of the code pipes of a corresponding code pipe pair. Thus, each code pipe pair provides a shifted code segment to the end multiplexer659. Finally, the end multiplexer659selects one of the shifted code segments as an output code for correlation, and the memory code generator650therefore can generate any code corresponding to the satellites.

To meet the requirement for handling signals from multiple satellites, a signal receiver often has a plurality of physical channels for respectively searching and tracking one of the multiple satellites. Each physical channel requires a correlation code dedicated to a corresponding satellite for correlation with an input signal received from the corresponding satellite. When a physical channel is for processing a GPS signal, a COMPASS signal, or a GLONASS signal, a code generator can directly generate a correlation code for a GPS signal, a COMPASS signal, or a GLONASS signal with a linear feedback shift register (LFSR). When a physical channel is for processing a Galileo E1 band signal, a correlation code for the Galileo E1 band signal is a pseudo random sequence which cannot be regenerated. A code memory therefore must store the correlation code in advance, before a code generator can then retrieve the correlation code from the code memory to provide the correlation code.

Referring toFIG. 8, a block diagram of a signal receiver800comprising a physical channel810is shown. In additional to the physical channel810, the signal receiver800further comprises a code memory820storing a correlation code. The physical channel810comprises a carrier mixer812, a correlator814, a memory816, a carrier numerical code oscillator (NCO)817, a code generator818, and a code numerical code oscillator (NCO)819. The carrier812mixes an input signal S1received by the physical channel810with a carrier wave T1to obtain a signal S2without a carrier component. The code generator818retrieves a correlation code C from the code memory820according to the code phase T2generated by the code NCO819. The correlator814then correlates the signal S2with the correlation code C to recover a signal S3without a correlation code component. The signal S3is next stored in a memory816for further processing.

A code memory has a high hardware cost. When a signal receiver has multiple channels, if the signal receiver has multiple code memories respectively storing correlation codes for the physical channels, the hardware cost of the signal receiver is too high for physically implementation. A code memory therefore must store correlation codes of multiple physical channels and serve as memory access for the multiple physical channels. Referring toFIG. 9, a block diagram of a signal receiver900comprising multiple physical channels9101˜910mand a code memory920is shown. The physical channels9101˜910mrespectively generate code requests to access the code memory920, and the code memory920then respectively generates the codes Ca, Cb, . . . , Cmdelivered to the physical channels9101˜910min response. The physical channels9101˜910mthen respectively correlate the input signal S1with the correlation codes Ca, Cb, . . . , Cmto obtain the signals S3a, S3b, . . . , S3msent to the processor908for further processing.

A code memory therefore requires a mechanism for handling code requests from multiple physical channels. Referring toFIG. 10, a block diagram of a code memory1000capable of code provision for a plurality of physical channels according to the invention is shown. The code memory1000comprises a multiplexer circuit1002and a core memory module1004. The core memory module1004stores code data corresponding to a plurality of satellites. In one embodiment, the code data stored in the core memory module1004is for Galileo E1 band signal correlation. When the multiple physical channels require code for signal correlation, the physical channels generate a plurality of addresses sent to the code memory to request code segments of the code data. The multiplexer circuit1002then sequentially selects one of the addresses as a segment of a code memory address signal. In one embodiment, the multiplexer circuit1002performs an OR operation on the addresses to obtain the code memory address signal. The core memory module1004then retrieves the code segments of the code data according to the code memory address signal to generate a code memory data signal. The physical channels then generate a plurality of latch signals to respectively retrieve previously requested code segments from the code memory data signal for further correlation.

Referring toFIG. 11, a schematic diagram of an embodiment of signals related to the code memory1000ofFIG. 11according to the invention is shown. Assume that a signal receiver comprises three physical channels, and the physical channels respectively generate requests for codes and addresses A1, A2, and A3corresponding to the requested codes at clock cycles t0, t1, and t2. The multiplexer circuit1002then performs an OR operation on the addresses sent by the physical channels to obtain a code memory address signal comprising the address A1at the clock cycle t0, the address A2at the clock cycle t2, and the address A3at the clock cycle t3. The core memory module1004then retrieves the code data stored therein according to the code memory address signal to generate a code memory data signal, wherein the code memory data signal comprises a code segment C1corresponding to the address A1at the clock cycle t1, a code segment C2corresponding to the address A2at the clock cycle t2, and a code segment C3corresponding to the address A3at the clock cycle t3. The physical channels then respectively generate latch signals respectively enabled at the clock cycles t1, t2, and t3to respectively latch on to the code segments C1, C2, and C3from the code memory data signal.

Although the code memory1000has a simple structure, the code memory1000still has limitations. Because the multiplexer circuit1002performs an OR operation on the addresses sent by the physical channels to generate the code memory address signal, the physical channels can not generate the addresses at the same clock cycle, otherwise the code memory address signal would be generated with errors. In addition, the physical channels cannot enable the latch signals at the same clock cycle to latch on to the requested code data from the code memory data signal. The physical channels therefore must have a mechanism, which prevents the addresses from being generated at the same time, complicating the circuit design of the physical channels.

A code memory capable of accepting memory accesses simultaneously generated by a plurality of physical channels is therefore required. Referring toFIG. 12, a block diagram of a code memory1200capable of code provision for a plurality of physical channels according to the invention is shown. The code memory1200comprises a selecting multiplexer1202, a core memory module1204, and a code buffer1206. Referring toFIG. 13, a schematic diagram of an embodiment of signals related to the code memory1200ofFIG. 12according to the invention is shown. Assume that a signal receiver comprises three physical channels, and the physical channels respectively generate requests for code segments and addresses A1, A2, and A3corresponding to the code segments at the same clock cycle ta1. Because the number of the physical channels are three, the addresses A1, A2, and A3have a duration equal to three times of a clock cycle.

After the physical channels send a plurality of addresses corresponding to the required code segments to the code memory1200, the selecting multiplexer1202repeatedly latches on to the addresses generated by the physical channels according to a predetermined sequence of the physical channels to generate a code memory address signal. For example, a series of clock cycles t1a, t2a, t3a, t1b, t2b, andt3bare generated, and the selecting multiplexer1202latches on to the address generated by a first channel at the clock cycles t1aand t1b, latches on to the address generated by a second channel at the clock cycles t2aand t2b, and latches on to the address generated by a third channel at the clock cycles t3aand t3b. Because the addresses generated by the physical channels have a duration of three clock cycles, the addresses can always be latched on to by the selecting multiplexer1202as a portion of the code memory address signal. Thus, the selecting multiplexer1202respectively latches on to the addresses A1, A2, and A3shown inFIG. 13at clock cycles t1a, t2a, andt3ato obtains a code memory address signal comprising the address A1at the clock cycle t1a, the address A2at the clock cycle t2a, the address A3at the clock cycle t3a.

The core memory module1204stores code data corresponding to the plurality of physical channels. In one embodiment, the code data stored in the core memory module1204is for a Galileo E1 band signal correlation. When the core memory module1204receives the code memory address signal, the core memory module1204retrieves the code data according to the code memory address signal to generate a code memory data signal. A code memory data signal shown inFIG. 13therefore comprises a code segment C1at the clock cycle t2a, a code segment C2at the clock cycle t3a, and a code segment C3at the clock cycle t1b, wherein the code segments C1, C2, and C3respectively corresponds to the addresses A1, A2, and A3.

The code buffer1206comprises a plurality of buffers respectively corresponding to the physical channels. When the code buffer1206receives the code memory data signal, the code buffer1206respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments in the corresponding buffers. For example, the code buffer1206retrieves a code segment C1from the code memory data signal at the clock cycle t2aand stores the code segment C1in a first buffer, as shown inFIG. 13. The code buffer1206then respectively retrieves code segments C2and C3from the code memory data signal at the clock cycles t3aand t1band respectively stores the code segments C2and C3in a second buffer and a third buffer, as shown inFIG. 13.

The physical channels then generate a plurality of latch signals to respectively retrieve the code segments C1, C2, and C3from the corresponding buffers. Because the duration of addresses A1, A2, and A3is extended to the clock cycle t3a, the physical channels enable the latch signals at the clock cycle t1bsubsequent to the clock cycle t3ato retrieve the code segments from the code buffer1206. The code buffer1206then clears the buffers at the clock cycle t2bafter the code segments are retrieved. Thus, although the physical channels generate code requests at the same clock cycle t1a, the code memory1200can still normally handle the code requests and generate the code segments. In addition, the physical channels can also generate latch signals to retrieve the code segments from the code memory1200at the same clock cycle t1b. The design of the physical channels is therefore simplified and hardware costs of the signal receiver are reduced.

Referring toFIG. 14, a flowchart of a method1400for code provision for a plurality of physical channels according to the invention is shown. First, code data is stored in a core memory module1204(step1401). The selecting multiplexer1202then repeatedly latches on to a plurality of addresses generated by a plurality of physical channels according to a sequence of the physical channels to generate a code memory address signal (step1402). The core memory module1204then retrieves the code data according to the code memory address signal from the core memory module to generate a code memory data signal (step1403). The code buffer1206then respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels (step1404). Finally, the code buffer1206stores the code segments in a plurality of buffers (step1405), and the physical channels respectively access the code segments from the buffers.