Adaptive ultra-low voltage memory

Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).

BACKGROUND

1. Field of the Invention

The present invention relates generally to computer memory.

2. Background Art

Conventional computer memories set a conservative minimum required supply voltage for the memory. This minimum memory supply voltage is typically determined by a voltage below which the first bitcell failure in the memory occurs.

When the memory is integrated with other circuit components (e.g., processor), the minimum memory supply voltage generally dictates the minimum supply voltage for the overall integrated circuit. (Though, the memory supply voltage may be separated from the supply voltage of the rest of the chip, doing so usually requires another supply regulator and impacts the timing of the memory). As such, the other circuit components are prevented from operating at voltages lower than the minimum memory supply voltage, even when the other circuit components are capable of or desire operating at lower voltages in reduced power/performance modes.

Further, even when a separate memory supply voltage is used, the minimum required memory supply voltage is typically set very conservatively that power savings can potentially be achieved by reducing the supply voltage below the minimum, before memory performance is affected in a significant way.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1illustrates a portion of an example computer system100. As shown inFIG. 1, computer system100includes a Central Processing Unit (CPU) chip102and a Power Management Unit (PMU)108.

CPU chip102includes a CPU104and a cache memory106. CPU104uses cache memory106to store and retrieve data and/or instructions that are repeatedly required to run programs. Cache memory106is faster than a main memory (not shown inFIG. 1) of computer system100, which allows computer system100to run at an improved overall system speed.

PMU108is a controller that performs several power-related functions within computer system100, including controlling and providing power to the various circuit components of computer system100. As such, PMU108provides power to CPU chip102. Typically, PMU108includes a switch regulator or DC-DC converter (not shown inFIG. 1). PMU108uses the switch regulator or DC-DC converter to regulate a DC voltage provided from a battery, for example, to generate and provide an appropriate voltage Vcc110to CPU chip102.

Generally, the value of Vcc110is bounded by a maximum value, defined by the process technology of CPU chip102, and a minimum value, Vcc(min). Typically, Vcc(min) for CPU chip102is determined by a voltage below which memory cells in cache memory106begin to fail. For example, Vcc(min) may be set at a guard level above the voltage for which the first memory bitcell failure occurs in cache memory106. Vcc(min) may be determined by testing cache memory106. In other implementations, a fixed portion of cache memory106is used to store error correction bits (the error correction bits are statically pre-allocated according to a fixed error correction scheme) for the rest of the data contained in cache memory106. As such, Vcc(min) will be determined by the voltage for which at least one bit corruption cannot be reliably corrected by the fixed error correction scheme (i.e., the voltage for which the correction scheme can no longer correct all bit corruptions).

CPU104, which is made of logic circuits, can operate reliably at voltages lower than Vcc(min). It is desirable to operate CPU104at lower voltages, to reduce power consumption, when high processor performance is not required. However, because of its integration with cache memory106, the minimum voltage at which CPU104can be operated is dictated by Vcc(min).

FIG. 2illustrates the behavior of an example memory array200as supply voltage is reduced below Vcc(min). Example array200is a memory array that comprises m×n bitcells. Each bitcell may be a bitcell like that shown as bitcell202. Bitcell202is a 6-transistor (6T) bitcell, which includes a cross-coupled inverter pair204,206, and two access transistors208and210. Bitcell202is accessed to read/write data using a bit line (BL) and a word line (WL). Transistor208may be the access transistor to read bitcell202, while transistor210may be the access transistor to write bitcell202, or vice versa.

As long as the supply voltage to memory array200is above Vcc(min), bitcell202remains stable, in the sense that the outputs of the cross-coupled inverter pair204,206remain either a solid logic 1 or a solid logic 0. However, as the supply voltage is reduced below Vcc(min), the stability of bitcell202becomes a concern, with the outputs of the inverter pair204,206becoming more prone to toggling (flipping) between a logic 1 and a logic 0. When bitcell202begins to toggle, bitcell202is considered failed because it can no longer hold a stable value.

Typically, the supply voltage value for which the first bitcell in memory array200begins to toggle is used to determine the Vcc(min) for memory array200. For example, Vcc(min) is set at a guard level above the voltage for which the first bitcell begins to toggle. Because of process and parameter variations, the bitcells of memory array200do not all begin to toggle at the same time, and thus do not fail all at once as the supply voltage to memory array200is reduced. Accordingly, in conventional designs, Vcc(min) is set in a very conservative manner.

Embodiments of the present invention, as further described below, recognize and exploit the fact that memory cell failures do not occur all at once as the supply voltage to a memory is reduced, and that, accordingly, a subset of the memory cells can be assumed to remain operational at lower voltages. As such, embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., speed, reliability, cache size, etc.).

In the following, example embodiments will be provided. These example embodiments are provided for the purpose of illustration and are not limiting. Embodiments will be described with reference to the particular example of a cache memory. However, embodiments are not limited to a cache memory, and can be extended to other types of memory as would be understood by a person of skill in the art based on the teachings herein. Further, embodiments will be described in the context of an example computer system. Embodiments are not limited by this example and can be applied to any device that may benefit from the embodiments described herein, as would be understood by a person of skill in the art based on the teachings herein.

FIG. 3illustrates a portion of an example computer system300with an adaptive cache memory according to an embodiment of the present invention. As shown inFIG. 3, computer system300includes a CPU chip302, PMU108, and a Memory Management Unit (MMU)306. CPU chip302includes a CPU104and a cache memory304.

PMU108provides a supply voltage Vcc110to CPU chip302. During a normal mode of operation of CPU104, Vcc110is above a Vcc(min) of CPU chip302. In this mode, cache memory304is useable to its full capacity (i.e., all bitcells are stable), and is thus used in its entirety to store data.

In a low power/performance mode of operation of CPU104, Vcc110is reduced below the Vcc(min) of CPU chip302. In embodiments, CPU104may have several low power/performance modes of operation (e.g., low, very low, ultra-low), each with a corresponding power and performance (e.g., processor speed) profile. Accordingly, Vcc110may be set to one of several voltage values below the Vcc(min), depending on the selected low power/performance mode in order to save power.

With Vcc110below the Vcc(min) of CPU chip302, some of the bitcells of cache memory304begin to fail, with some bitcell failures being predictable (i.e., that repeat for the same Vcc value) and others unpredictable. In an embodiment, cache memory304is characterized by a priori testing to determine a probability density function (PDF) of bitcell failure as a function of Vcc. Based on this PDF, a useable percentage of cache memory304can be predicted for a particular value of Vcc. For example, for Vcc at 30% below Vcc(min), 50% of cache memory304may still be useable. The same characterization can also be performed, alternatively or additionally, as a function of temperature. In another embodiment, cache memory304is characterized by testing so as to identify bitcells that consistently fail for particular values of Vcc. This type of characterization identifies repeatable bitcell failures. With one or both types of characterizations, the available capacity or useable portions of cache memory304can be determined, which allows cache memory304to be adapted as a function of Vcc, as further described below.

MMU306controls cache memory304via a control signal310to adapt cache memory304based on the mode of operation of CPU104. In an embodiment, MMU306receives a signal308from PMU108, which includes information about a scheduled mode of operation of CPU104. For example, signal308may include, without limitation, one or more of a Vcc value, a cache size requirement, and a desired hit/miss rate for the scheduled mode of operation. In addition, signal308may include a future time at which CPU104is expected to enter the scheduled mode of operation. In other embodiments, configuration of cache memory304is performed by a cache association logic, which would perform the same function as described herein with reference to MMU306

Based on signal308, MMU306determines an appropriate configuration of cache memory304to support CPU104for the selected mode of operation. As further described below, according to embodiments, cache memory304can be configured according to various configurations depending on the mode of operation of CPU104. This includes taking into account the desired power savings (e.g., the target Vcc(min)) and/or performance requirements (e.g., reliability, cache size, speed, etc.) of the CPU mode of operation. As the CPU mode of operation is adjusted, cache memory304can be adapted dynamically to enhance power savings and enable acceptable performance.

In the following, example embodiments for re-configuring a cache memory based on the CPU mode of operation are provided. These examples are provided for the purpose of illustration and are not limiting of embodiments. For example, the embodiments are described with respect to a cache memory having four ways. As would be understood by a person of skill in the art based on the teachings herein, embodiments can be applied to a cache memory of any size (i.e., number of ways) as well as to other types of memory, including, without limitation, random access memory (RAM), Static RAM (SRAM), Dynamic RAM (DRAM), read-only memory (ROM), programmable ROM (PROM), and one-time programmable (OTP) memory. Further, embodiments may be applied to memories having different types of logical segmentation than ways.

FIG. 4illustrates another example re-configuration400of an adaptive cache memory according to an embodiment of the present invention. For the purpose of illustration, example re-configuration400is described with reference to cache memory304, described above inFIG. 3. It is assumed, for the purpose of illustration, that cache memory304includes four ways402,404,406, and408, which provide a logical segmentation of cache memory304. As described above, embodiments are not limited to cache memory or to memory segmented into ways.

As shown inFIG. 4, cache memory304is initially operating in a normal mode of operation, where Vcc is above Vcc(min). In this mode, all four of ways402,404,406, and408of cache memory304are made available for data caching.

Subsequently, cache memory304is re-configured into a low power mode of operation, with Vcc reduced below Vcc(min). In an embodiment, cache memory304is re-configured based on information contained in control signal310provided by MMU306. In this example re-configuration, cache memory304is re-configured to have three data ways402,404, and406(i.e., ways dedicated for data caching) and one error correcting code (ECC) way408. In an embodiment, ECC way408includes error correcting codes for the data contained in ways402,404, and406. The size of cache memory304is accordingly reduced by 25% relative to the initial configuration to accommodate the ECC way.

Other configurations of cache memory304between data ways and ECC ways may be used. For example, the ratio of data ways to EEC ways may be different than described inFIG. 4. Also, the type and/or rate of the error correcting code may be varied from one configuration to another, and between ECC ways in a single configuration. For example, a lower rate code may be used for a higher ratio of data ways to ECC ways. Also, in a given configuration, some ECC ways may use stronger codes than others. This affects the error correction capability provided, and consequently the reliability of cache memory304.

According to embodiments, cache memory304may transition between various modes of operation, and thus adapt dynamically the ratio of data ways to ECC ways, as well as the type/rate of error correction used. For example, based on an increased desired cache reliability, cache memory304may be adapted to retain the same size but only adjust the ECC strength. Similarly, if CPU performance requires a larger cache size, cache memory304may be adapted to increase the number of data ways at the expense of lower error correction efficiency.

FIG. 5illustrates another example re-configuration500of an adaptive cache memory according to an embodiment of the present invention. For the purpose of illustration, example re-configuration500is described with reference to cache memory304, described above inFIG. 3. It is assumed, for the purpose of illustration, that cache memory304includes four ways402,404,406, and408, which provide a logical segmentation of cache memory304. As described above, embodiments are not limited to cache memory or to memory segmented into ways.

As shown inFIG. 5, cache memory304is initially operating in a normal mode of operation, where Vcc is above Vcc(min). In this mode, all four of ways402,404,406, and408of cache memory304are made available for data caching.

Subsequently, cache memory304is re-configured into a low power mode of operation, with Vcc reduced below Vcc(min). In an embodiment, cache memory304is re-configured based on information contained in control signal310provided by MMU306. In this example re-configuration, cache memory304is re-configured to have three data ways402,406, and408and one error correcting code (ECC) way404. ECC way404is dedicated to error correcting codes for the data contained in data way402.

In an embodiment, data way402is designated for high priority or critical data. In another embodiment, data way402may be identified during testing as having a higher bitcell failure rate than data ways406and408(e.g., data way402may use a different bitcell type). In either of these embodiment, a dedicated FCC way404may be used to protect the data contained in data way402. Alternatively or additionally, data redundancy as described inFIG. 4may be used for further reliability.

As described above, cache memory304is controlled by MMU306via control signal310. Thus, according to embodiments, control signal310may include any of the information described above, in order to configure or re-configure cache memory304. For example, control signal310may include, without limitation, information designating ways as data ways or ECC ways, information associating particular ECC ways with respective data ways, information about the error correction for each ECC way, and information partitioning ways between data and ECC bits.

FIG. 6illustrates an example re-configuration600of an adaptive cache memory according to an embodiment of the present invention. For the purpose of illustration, example re-configuration600is described with reference to cache memory304, described above inFIG. 3. It is assumed, for the purpose of illustration, that cache memory304includes four ways402,404,406, and408, which provide a logical segmentation of cache memory304. As described above, embodiments are not limited to cache memory or to memory segmented into ways.

As shown inFIG. 6, cache memory304is initially operating in a normal mode of operation, where Vcc is above Vcc(min). This may correspond, for example, to CPU104operating in a normal power mode. Because Vcc is above Vcc(min), it can be expected that no bitcell failures will occur. As such, in this mode, all four of ways402,404,406, and408of cache memory304are made available for data caching, thereby configuring cache memory304for a maximum cache size.

Subsequently, cache memory304is re-configured into a low power mode of operation, with Vcc reduced below Vcc(min). In an embodiment, cache memory304is re-configured based on information contained in control signal310provided by MMU306. In this example re-configuration, cache memory304is re-configured so that each of the ways402,404,406, and408is partitioned between data hits and ECC bits. In an embodiment, the ratio of data to ECC bits is a function of the used error correction code and the supply voltage provided to cache memory304. For example, if the supply voltage provided to cache memory304is only slightly below Vcc(min) and only single bit errors can be expected for this supply voltage, then Hamming codes can be used, with each way partitioned between m error correcting bits and 2m−m−1 data bits. As the bit failure rate increases (e.g., as the supply voltage is reduced further), each way can be (independently) configured to switch to a more aggressive error correction code, which reduces the data portion of the way.

In an embodiment, the error detection capability of an error correcting code is used to enable a feedback mechanism, based on which the error correction code used is adjusted. One property of error correcting codes is that they typically can detect more errors than they can correct. For example, a Hamming code can detect two bit failures but only correct one bit failure. As such, according to embodiments, the number of error detections versus the number of error corrections performed by the code can be used to refine the choice of error correcting code, and by consequence the ratio of data to ECC bits for each way. For example, when the error correcting code detects more errors than it can correct, this information is used as an indicator that a more aggressive error correction code may be needed. In embodiments, a first error correction code is used initially, and then adjusted based on the feedback information as appropriate to converge on the error correction code that optimizes the data to ECC bit allocation within the memory.

FIG. 7illustrates another example re-configuration700of an adaptive cache memory according to an embodiment of the present invention. For the purpose of illustration, example re-configuration700is described with reference to cache memory304, described above inFIG. 3. It is assumed, for the purpose of illustration, that cache memory304includes four ways702,704,706, and708, which provide a logical segmentation of cache memory304. As described above, embodiments are not limited to cache memory or to memory segmented into ways.

Further, cache memory304is designed such that way702is an ultra-low voltage memory array and was704,706, and708are normal voltage memory array. For example, way702may use physically larger voltage bitcells (i.e., that operate with larger voltages) than ways704,706, and708, which results in way702having higher stability than ways704,706, and708at Vcc below Vcc(min). Alternatively, or additionally, the bitcells of way702may use a more stable bitcell design (e.g., using more transistors) than the bitcells of ways704,706, and708. Accordingly, way702can operate reliably (i.e., with low bitcell failures) at lower voltages than ways704,706, and708. In an embodiment, way702may be slower than ways704,706, and708, and can be configured to take an extra cycle, for example, to access.

In an embodiment, as shown inFIG. 7, cache memory304is initially operating in a normal mode of operation, where Vcc is above Vcc(min). As such, in this mode, all four of ways702,704,706, and708of cache memory304are ON and made available for data caching. Thus, cache memory304is configured for maximum cache size.

Subsequently, cache memory304is re-configured into a low power mode of operation, with Vcc reduced below Vcc(min). In an embodiment, cache memory304is re-configured based on information contained in control signal310provided by MMU306. In this example re-configuration, cache memory304is re-configured to retain only way7020N and to turn ways704,706, and708OFF. Because way702is an ultra-low voltage memory array, it will continue to operate reliably in this low power mode. Ways704,706, and708, which may fail during this low power mode, are turned OFF to save power and/or because their reliability is anticipated to be very low in this mode. Accordingly, this reconfiguration trades off cache size for power savings, while maintaining high reliability for the operational portion of cache memory304.

Example re-configuration700may be suitable for ultra-low voltage modes of operation, where a high bitcell failure is anticipated for ways704,706, and708. As such, turning OFF ways704,706, and708is a better option than retaining them with low reliability. Alternatively or additionally, the mode of operation may only require a small cache size, provided sufficiently by way702. In another embodiment, when ways704,706, and708are turned off, way702is also re-configured from a write-back to a write-through writing policy, so that data written to the cache is synchronously also written to the main memory (whereas in write-back, data is written at some later time).

As would be understood by a person of skill in the art based on the teachings herein, other variants of example700may be used. For example, embodiments may use a mixed bitcell design (i.e., with ultra-low voltage and normal voltage arrays) as described inFIG. 7, and further apply any of the described way designation schemes (i.e., data versus ECC, redundancy, etc.). For example, in an embodiment, with a mixed bitcell design as described inFIG. 7, an ECC/redundancy scheme is applied to only one or more of the normal voltage memory arrays. Because no error correction is needed for the ultra-low voltage memory array, higher error correction efficiency can be provided for the normal voltage memory arrays, allowing both ultra-low voltage operation and high cache reliability.

In another variation of example700, the low power mode of operation may retain all four of ways702,704,706, and7080N, but provides a lower voltage to way702than to ways704,706, and708. Accordingly, power savings are achieved with respect to way702, and the reliability and cache size of the cache are maintained the same. In a further variation, ways702,704,706, and708have the same design (e.g., all normal voltage arrays). During testing, ways702,704,706, and708are characterized so as to determine, for each way, the minimum voltage at which bit cell failures start occurring. Subsequently, during operation, different voltages may be provided to ways702,704,706, and708, the voltages reduced as appropriate (independently for each way) based on the minimum voltages determined during testing.