Independently scaling selector and memory in memory cell

Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2017/054281, filed Sep. 29, 2017, entitled “INDEPENDENTLY SCALING SELECTOR AND MEMORY IN MEMORY CELL,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, independently scaled selectors and memory elements in a memory cell.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Embedded memory with non-volatile memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. A non-volatile memory device such as magnetic tunnel junction (MTJ) memory device or resistive random access memory (RRAM) device is coupled with selector element to form a memory cell. A large collection of memory cells forms a key component of non-volatile embedded memory. However, with scaling of memory devices, the technical challenges of assembling a vast number of memory cells presents formidable roadblocks to commercialization of this technology today.

DESCRIPTION OF THE EMBODIMENTS

A method and system of independently scaling selector and memory in memory cell are described. In the following description, numerous specific details are set forth, such as specific material and structural regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or more embodiments described herein are directed to hetero-structure material stacks for use as a selector for a non-volatile memory device. Embodiments may pertain to or include three-dimensional (3D) cross-point arrays, embedded non-volatile memory (eNVM), and selectors for eNVM. Approaches described herein may be implemented to realize high performance highly scaled eNVM cells, and potentially increase monolithic integration of eNVM in system-on-chips (SoCs) of future technology nodes.

To provide context, non-volatile memory devices such as a magnetic tunnel junction (MTJ) memory device or a resistive random access memory (RRAM) device depend on a phenomenon of resistance switching to store information. The non-volatile memory device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. A non-volatile memory device may be coupled with a selector element to form a memory cell. The selector may be a volatile switching element that is placed in series with the non-volatile memory device. A large collection of such memory cells forms a key component of non-volatile embedded memory.

For example, in an embodiment a conductive electrode may be disposed between the selector element and a memory element. The memory cell may further include a bitline disposed above the selector element. In an embodiment, a large collection of memory cells each including a selector element and a memory element are utilized to form a non-volatile memory array. The non-volatile memory array formed by a memory cell at each intersection of a wordline and a bitline is, herein, referred to as a non-volatile cross-point memory array. A non-volatile cross-point memory array can offer significant advantages for scaling to achieve high density memory.

As a first example of a conventional selector stack,FIG. 1Aillustrates a view of a 1 selector-1 resistor (1S-1R) memory cell. Referring toFIG. 1A, the memory cell100is shown comprising a selector element102disposed on a memory element104. Typically, the memory cell100is fabricated by depositing memory material followed by depositing selector material, and then etching them both. In this case, the resulting selector element102and memory element104have identical widths (width 1=width 2). Problems are encountered, however, when the selector element102and the memory element104need to be different sizes. This could arise when the memory element104needs to be larger or smaller than the selector element102, or the selector102needs to be smaller than a regular-sized memory element104.

One way to create a selector element102and a memory element104with different sizes using a state-of-the-art fabrication process requires a first lithography step to deposit the memory material and pattern the memory material to a certain size to form the memory element104. A dielectric material (not shown) may be optionally deposited on top of the memory element104and polished flat to the top of the memory material104. A second lithography step would then be used to deposit the selector material and to pattern the selector material to define the selector element102independently of the memory element104to achieve two different widths for the selector element102and the memory element104. This process, however, is inefficient in that it requires two lithography patterning steps, and the process may also lead to misalignment between the selector element102and the memory element104.

As a second example of a state-of-the-art selector stack,FIG. 1Billustrates a cross-sectional view of a selector stack in a phase change memory cell. The memory cell110is shown comprising a selector element112, such as an ovonic threshold switch (OTS), disposed on a phase change memory (PCM) element114. In this type of selector stack, a requirement that the selector element112be made smaller than the memory element114is not possible because selector material cannot be deposited over a via116in which the phase change memory element114is formed.

In accordance with the embodiments disclosed herein, a method is provided by which different widths may be obtained for a selector element and a memory element in a single lithography pattering step.FIGS. 2A and 2Baare diagrams of a memory cell200A,200B fabricated in accordance with the disclosed embodiments.

Referring toFIGS. 2A and 2B, the memory cell200A,200B is disposed above a substrate202and comprises a selector element204independently sized from the memory element206in a single lithography patterning step through the use of a spacer208.FIG. 2Ashows an embodiment where the selector element204is smaller width-wise than the memory element206, whileFIG. 2Bshows an embodiment where the memory element206is smaller width-wise than the selector element204. In both embodiments, the substrate202may include a metal layer (not shown) disposed thereon.

In the embodiment shown inFIG. 2A, the selector element202is located above the metal layer, the spacer208surrounds the selector element204, and the spacer width is larger than the selector element width. In this embodiment, the memory element206is located below both the selector element204and the spacer208. Due to the presence of the spacer208, the memory element206is in alignment with both the selector element204and the spacer208and has a width substantially identical to the spacer width.

In the embodiment shown inFIG. 2B, the memory cell200′ comprises a memory element206located above the metal layer, the spacer208surrounds the memory element206and the spacer width is larger than the memory element width. In this embodiment, the selector element204is located below both the memory element206and the spacer208. Due to the presence of the spacer208, the selector element204is in alignment with both the memory element206and the spacer208and has a width substantially identical to the spacer width. Accordingly, the embodiments shown inFIGS. 2A and 2Bprovide for a memory cell200A,200B, respectively, comprising a selector element204and a memory element206in alignment where one can be sized smaller than the other and where the smallest element is located above the larger element. In further detail. The memory cell200A,200B comprises a selector element204and a memory element206above a metal layer. A spacer208surrounds whichever one of the selector element204and the memory element206has the smallest width. Whichever element204206not surrounded by the spacer208has a width substantially identical to the spacer208and is also in alignment with the spacer208.

Described in other terms, the embodiments shown inFIGS. 2A and 2Bprovide for a memory cell200A,200B having a top element comprising a selector element204or a memory element206, where the top element has a top element width and a top element thickness. A spacer208surrounds the top element and the spacer208has a spacer width larger than the top element width and a thickness less than the top element. A bottom element below the spacer208and the top element comprises the selector element204or the memory element206not present in the top element, where the bottom element is in alignment with both the top element and the spacer208and has a bottom element width substantially identical to the spacer208.

In one embodiment, the selector element may comprise a monolayer selector element, a bilayer selector element, or a tri-layer selector element.FIGS. 3A and 3Bare diagrams illustrating a monolayer selector element and a bilayer selector element, respectively.

FIG. 3Aillustrates a cross-sectional view of a monolayer selector element including a material having a field-induced insulator metal transition. The selector element300includes an insulator metal transition (IMT) material layer302between a bottom electrode304and a top electrode306. In another embodiment, the monolayer selector element may include a semiconducting oxide material layer (not shown) in place of the (IMT) layer.

FIG. 3Billustrates a cross-sectional view of a bilayer selector element. The bilayer selector element310includes a bilayer312comprising a first material layer312A and a second material layer312B. The bilayer selector element312is between a bottom electrode304′ and a top electrode306′. One of the first or second material layers312A or312B may comprise PN junction (P-i-N) diodes, in silicon or germanium, oxide-based diodes such as HfO2, Al2O3, TiO2, Ta2O5, and the like sandwiched between metals (e.g. TiN/Ta2O5/TiN, Ni/TiO2/Ni, Pt/IZO/CoO/Pt/TiN or Pt/HfO2/ZrO2/TiN), silver-doped or copper-doped oxide such as SiO2 or HfO2 & ZrO2, vanadium (V) oxide, Ovonic threshold switching (OTS) or multicomponent chalcogenides, or a niobium oxide (NbxOy) in one embodiment. In one embodiment, the other of the first or second material layers312A or312B may comprise an IMT material or a semiconducting material layer.

In an exemplary implementation,FIGS. 4A-4Cillustrates a cross-sectional illustration of a memory cell400disposed above a substrate450in further detail. Referring toFIG. 4A, the memory cell400A includes a wordline402disposed above the substrate. In this embodiment, a bilayer selector element404is shown disposed above the wordline. In other embodiments, a monolayer or tri-layer selector element could be used. In an embodiment, a conductive electrode406is disposed on the bilayer selector element404. In an embodiment, a bipolar memory element408is disposed above the conductive electrode406, and a bit line410is disposed above the bipolar memory element408.

In an embodiment, the memory device408includes a magnetic tunnel junction (MTJ) memory device. In an embodiment, the memory device408includes a resistive random access memory (RRAM) device. In an embodiment, the memory device408includes a phase change memory (PCM) device.

In an embodiment, the bilayer selector element includes first402A and second402B material layers. One of the first402A and second402B material layers may be a ferroelectric oxide material layer. The other of the first402A and second402B material layers is an insulator metal transition material layer or a semiconducting oxide layer.

In an embodiment, the insulator metal transition material layer is selected from the group consisting of a vanadium oxide material and a niobium oxide material. In an embodiment, the insulator metal transition material layer is a single crystalline material. In another embodiment, the insulator metal transition material layer is an amorphous or a polycrystalline material. In an embodiment, the semiconducting oxide material layer is one such as, but not limited to, indium gallium zirconium oxide (IGZO), tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.

In an embodiment, the conductive electrode406is disposed on the bilayer selector element404. In an embodiment, the conductive electrode406includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the conductive electrode406has a thickness between 5 nanometers and 10 nanometers.

FIG. 4Billustrates a plan view of the memory cell400. In an embodiment, the wordline402and the bit line410are arranged in an orthogonal manner. An outline401of the bilayer selector element404, conductive electrode406and bipolar memory element408, relative to the bitline410and the wordline402is also illustrated inFIG. 4B. In an embodiment, the bilayer selector element404, the conductive electrode406and the bipolar memory element408are spatially confined to an intersection between the wordline402and the bitline408, which may be referred to as a cross point memory cell.

FIG. 4Cillustrates a cross-sectional illustration of a memory cell400C where the bipolar memory element408is disposed on the wordline402, a conductive electrode406is disposed on the bipolar memory element408and a bilayer selector element404is disposed above the conductive electrode406.

FIGS. 5A-5Gillustrate cross-sectional views representing various operations in a method of fabricating a memory cell in accordance with the embodiments disclosed herein.

FIG. 5Aillustrates a wordline500formed in an opening in a dielectric layer501formed above a substrate502.

In an embodiment, the substrate502includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate502includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

In an embodiment, the wordline500is formed in a dielectric layer501by a damascene or a dual damascene process that is well known in the art. In an embodiment, the wordline500includes a barrier layer, such as titanium nitride, ruthenium, tantalum, tantalum nitride, and a fill metal, such as copper, tungsten. In another embodiment, the wordline500includes a layer of a single material such as TiN or TaN. In an embodiment, the wordline500is fabricated using a subtractive etch process when materials other than copper are utilized. In one such embodiment, the wordline500includes a material such as but not limited to titanium nitride, ruthenium, tantalum, tantalum nitride. In an embodiment, the dielectric layer501includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer501has an uppermost surface substantially co-planar with an uppermost surface of the wordline500. In an embodiment, the dielectric layer501has a total thickness between 70 nm-300 nm. In an embodiment, wordline500is electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.

FIG. 5Billustrates the structure ofFIG. 5Afollowing the formation of a memory material layer stack513on the wordline500, formation of a conductive electrode layer511on memory material layer stack513, and formation of a selector material stack509on the conductive electrode layer511.

In an embodiment, the memory material layer stack513is blanket deposited on the wordline500and on the dielectric layer501using a PVD process. In an embodiment, when the memory material layer stack513includes layers for an MTJ memory element the memory material layer stack513is subjected to an annealing process performed at a temperature between 300-400 degrees Celsius.

In an embodiment, the conductive electrode layer511is blanket deposited by a PVD process. In an embodiment, the conductive electrode layer511is deposited to a thickness between 5 nm-10 nm.

In an embodiment, the selector material stack509is blanket deposited on the conductive electrode layer511by an evaporation process, an atomic layer deposition (ALD) process or by chemical vapor deposition (CVD) process. In an embodiment, the chemical vapor deposition process is enhanced by plasma techniques such as RF glow discharge (plasma enhanced CVD) to increase the density and uniformity of the film. In an embodiment, an uppermost layer of selector material layer stack509A may include an uppermost electrode layer that ultimately acts as a hardmask. In an embodiment, the uppermost electrode layer has a thickness between 70 nm-100 nm.

FIG. 5Cillustrates the structure ofFIG. 5Bfollowing a single lithography step that forms a photoresist mask507on an uppermost surface of the selector material layer stack509. In an embodiment, the photoresist mask507is formed at a minimum size required for either the selector element or the memory element, and defines a location where a memory cell will be subsequently formed. In the embodiment shown, the photoresist mask507is formed to the minimum size requirement of the selector element, since the selector element is over the memory element. In one embodiment, example minimum sizes for the resist could be in the range of 10 nm-100 nm.

FIG. 5Dillustrates the structure ofFIG. 5Cfollowing the patterning of the selector material stack509in alignment with the photoresist mask507. In an embodiment, a plasma etch process is utilized to pattern the selector material stack509down to the conductive electrode layer511to form a selector element510.

FIG. 5Eillustrates the structure ofFIG. 5Dfollowing the formation of a conformal film518on the conductive electrode layer511, which will become a spacer around the selector element510. The conformal film518may be deposited through thin film deposition, chemical vapor deposition (CVD), and ALD. Example non-conductive materials for the conformal film518may include silicon dioxide, silicon nitride, or some silicon dioxide base material like silicon oxi-nitride, aluminum oxide or any type of oxide. The thickness of the conformal film is less than the thickness of the selector material stack509.

FIG. 5Fillustrates the structure ofFIG. 5Efollowing the patterning of the conformal film518to a required size of the memory element via an etch process down to the conductive electrode layer511to form a spacer.

FIG. 5Gillustrates the structure ofFIG. 5Ffollowing the patterning the conductive electrode layer511and the memory material layer513via an etch process to form a conductive electrode512and a memory element518in alignment with the spacer516. In an embodiment, a plasma etch process is utilized to pattern the memory material layer stack513and the conductive electrode layer511.

Memory element518, the conductive electrode512, and the selector element516are herein referred to as an active memory device (as shown inFIGS. 2A-2B and 5G). In accordance with the embodiments disclosed herein, the selector element510and memory element518of the active memory device are sized independently of one another through a single lithography process.

According to one embodiment, the spacer516may be optionally removed at this point of the fabrication process depending on the application.

FIG. 5Hillustrates the structure ofFIG. 5Gfollowing deposition of a second dielectric layer and patterning of a bitline. The memory cell may be completed by removing the photoresist mask507and then forming a second dielectric layer520on the wordline500and on the dielectric layer501and on the active memory device (on the hardmask, on sidewalls of the selector element and on sidewalls of the memory element). The second dielectric letter520is planarized to expose an uppermost surface of the selector element510. Thereafter, a bitline522is patterned on the uppermost surface of the selector element510and on the uppermost surface of the second dielectric layer518to complete formation of the memory cell. In an embodiment, the bitline522may comprise conductive material such as W, TiN, TaN or Ru. In an embodiment, the bitline522is formed by using a dual damascene process (not shown) and includes a barrier layer such as Ru, Ta or Ti and a fill metal such as W or Cu.

It is to be appreciated that the layers and materials described in association with embodiments herein are typically formed on or above an underlying semiconductor substrate, e.g., as FEOL layer(s). In other embodiments, the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s). In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, structures described herein may be fabricated on underlying lower level back end of line (BEOL) interconnect layers. For example, in one embodiment, an embedded non-volatile memory structure is formed on a material composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In a particular embodiment, an embedded non-volatile memory structure is formed on a low-k dielectric layer of an underlying BEOL layer.

In an embodiment, interconnect lines (and, possibly, underlying via structures) described herein are composed of one or more metal or metal-containing conductive structures. The conductive interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the interconnect lines includes a barrier layer and a conductive fill material. In an embodiment, the barrier layer is composed of a metal nitride material, such as tantalum nitride or titanium nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

Interconnect lines described herein may be fabricated as a grating structure, where the term “grating” is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have conductive lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

In an embodiment, ILD materials described herein are composed of or include a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, patterning of trenches is achieved using lithographic operations performed using 193 nm immersion lithography (i193), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus,FIGS. 6A and 6Bare top views of a wafer and dies that include one or more embedded non-volatile memory structures having a bilayer selector, in accordance with one or more of the embodiments disclosed herein.

Referring toFIGS. 6A and 6B, a wafer600may be composed of semiconductor material and may include one or more dies602having integrated circuit (IC) structures formed on a surface of the wafer600. Each of the dies602may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a bilayer selector, such as described above. After the fabrication of the semiconductor product is complete, the wafer600may undergo a singulation process in which each of the dies602is separated from one another to provide discrete “chips” of the semiconductor product. In particular, structures that include embedded non-volatile memory structures having an independently scaled selector as disclosed herein may take the form of the wafer600(e.g., not singulated) or the form of the die602(e.g., singulated). The die602may include one or more embedded non-volatile memory structures based independently scaled selectors and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer600or the die602may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die602. For example, a memory array formed by multiple memory devices may be formed on a same die602as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 7illustrates a block diagram of an electronic system700, in accordance with an embodiment of the present disclosure. The electronic system700can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system700may include a microprocessor702(having a processor704and control unit706), a memory device708, and an input/output device710(it is to be appreciated that the electronic system700may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system700has a set of instructions that define operations which are to be performed on data by the processor704, as well as, other transactions between the processor704, the memory device708, and the input/output device710. The control unit706coordinates the operations of the processor704, the memory device708and the input/output device710by cycling through a set of operations that cause instructions to be retrieved from the memory device708and executed. The memory device708can include a non-volatile memory cell as described in the present description. In an embodiment, the memory device708is embedded in the microprocessor702, as depicted inFIG. 7. In an embodiment, the processor704, or another component of electronic system700, includes one or more embedded non-volatile memory structures having a bilayer selector, such as those described herein.

FIG. 8is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a bilayer selector, in accordance with one or more of the embodiments disclosed herein.

Referring toFIG. 8, an IC device assembly800includes components having one or more integrated circuit structures described herein. The IC device assembly800includes a number of components disposed on a circuit board802(which may be, e.g., a motherboard). The IC device assembly800includes components disposed on a first face840of the circuit board802and an opposing second face842of the circuit board802. Generally, components may be disposed on one or both faces840and842. In particular, any suitable ones of the components of the IC device assembly800may include a number of embedded non-volatile memory structures having a bilayer selector, such as disclosed herein.

In some embodiments, the circuit board802may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board802. In other embodiments, the circuit board802may be a non-PCB substrate.

The IC device assembly800illustrated inFIG. 8includes a package-on-interposer structure836coupled to the first face840of the circuit board802by coupling components816. The coupling components816may electrically and mechanically couple the package-on-interposer structure836to the circuit board802, and may include solder balls (as shown inFIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure836may include an IC package820coupled to an interposer804by coupling components818. The coupling components818may take any suitable form for the application, such as the forms discussed above with reference to the coupling components816. Although a single IC package820is shown inFIG. 8, multiple IC packages may be coupled to the interposer804. It is to be appreciated that additional interposers may be coupled to the interposer804. The interposer804may provide an intervening substrate used to bridge the circuit board802and the IC package820. The IC package820may be or include, for example, a die (the die702ofFIG. 7B), or any other suitable component. Generally, the interposer804may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer804may couple the IC package820(e.g., a die) to a ball grid array (BGA) of the coupling components816for coupling to the circuit board802. In the embodiment illustrated inFIG. 8, the IC package820and the circuit board802are attached to opposing sides of the interposer804. In other embodiments, the IC package820and the circuit board802may be attached to a same side of the interposer804. In some embodiments, three or more components may be interconnected by way of the interposer804.

The interposer804may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer804may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer804may include metal interconnects810and vias808, including but not limited to through-silicon vias (TSVs)806. The interposer804may further include embedded devices814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer804. The package-on-interposer structure836may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly800may include an IC package824coupled to the first face840of the circuit board802by coupling components822. The coupling components822may take the form of any of the embodiments discussed above with reference to the coupling components816, and the IC package824may take the form of any of the embodiments discussed above with reference to the IC package820.

The IC device assembly800illustrated inFIG. 8includes a package-on-package structure834coupled to the second face842of the circuit board802by coupling components828. The package-on-package structure834may include an IC package826and an IC package832coupled together by coupling components830such that the IC package826is disposed between the circuit board802and the IC package832. The coupling components828and830may take the form of any of the embodiments of the coupling components816discussed above, and the IC packages826and832may take the form of any of the embodiments of the IC package820discussed above. The package-on-package structure834may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 9illustrates a computing device900in accordance with one implementation of the disclosure. The computing device900houses a board902. The board902may include a number of components, including but not limited to a processor904and at least one communication chip906. The processor904is physically and electrically coupled to the board902. In some implementations the at least one communication chip906is also physically and electrically coupled to the board902. In further implementations, the communication chip906is part of the processor904.

The processor904of the computing device900includes an integrated circuit die packaged within the processor904. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a bilayer selector, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip906also includes an integrated circuit die packaged within the communication chip906. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures having a bilayer selector, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device900may contain an integrated circuit die that includes one or more embedded non-volatile memory structures having a bilayer selector, in accordance with implementations of embodiments of the disclosure.

Thus, embodiments described herein include embedded non-volatile memory structures having bilayer selector elements.

A memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.

The memory device of example embodiment 1, wherein the selector element is above the memory element.

The memory device of example embodiment 2, wherein the spacer surrounds the selector element and has a spacer width larger than a selector element width.

The memory device of example embodiment 2 or 3, wherein the selector element is smaller width-wise than the memory element.

The memory device of example embodiment 1, wherein the memory element is above the selector element.

The memory device of example embodiment 5, wherein the spacer surrounds the memory element and has a spacer width larger than a memory element width.

The memory device of example embodiment 5 or 6, wherein the memory element is smaller width-wise than the selector element.

The memory device of example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein further comprising a conductive electrode between the selector element and the memory element.

The memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, or 8 wherein the selector element comprises one of a monolayer selector element, a bilayer selector element, and a tri-layer selector element.

The memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the metal layer comprises a wordline.

The memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the memory element comprises a resistive random access memory (RRAM) device.

The memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or 11, wherein the memory element comprises a phase change memory (PCM) device.

A memory structure includes a first bitline, a top element below the bitline, the top element comprising one of a selector element and a memory element, the top element having a top element width and a top element thickness. A spacer surrounds the top element, the spacer having a spacer width larger than the top element width and a thickness less than the top element. A bottom element below the spacer and the top element, the bottom element comprising one of the selector element and the memory element not present in the top element, the bottom element in alignment with both the top element and the spacer and having a bottom element width substantially identical to the spacer. A wordline is below the bottom element.

The memory structure of example embodiment 15, wherein the selector element is above the memory element.

The memory structure of example embodiment 16, wherein the spacer surrounds the selector element and has a spacer width larger than a selector element width.

The memory structure of example embodiment 16 or 17, wherein the selector element is smaller width-wise than the memory element.

The memory structure of example embodiment 15, wherein the memory element is above the selector element.

The memory structure of example embodiment 19, wherein the spacer surrounds the memory element and has a spacer width larger than a memory element width.

The memory structure of example embodiment 19 or 20, wherein the memory element is smaller width-wise than the selector element.

The memory structure of example embodiment 15, 16, 17, 18, 19, 20, or 21, further comprising a conductive electrode between the selector element and the memory element.

The memory structure of example embodiment 15, 16, 17, 18, 19, 20, 21, or 22, wherein the selector element comprises one of a monolayer selector element, a bilayer selector element, and a tri-layer selector element.

A method of fabricating a memory device includes forming a wordline in a first dielectric layer above a substrate; forming a memory material layer stack above the wordline; forming a conductive electrode layer above the memory material layer stack; forming a selector material stack on the conductive electrode layer; forming a hardmask layer above the selector material stack; forming a photoresist mask on the hardmask layer above the selector material stack, the photoresist mask formed at a minimum size required for a selector element; patterning the selector material stack in alignment with the photoresist mask down to the conductive electrode layer to form the selector element; forming a conformal film on the conductive electrode layer; patterning the conductive electrode layer to form a conductive electrode; patterning the conformal film down to the conductive electrode layer to a size required for a memory element; patterning the conductive electrode layer and the memory material layer to form a conductive electrode and the memory element in alignment with the spacer; forming a second dielectric layer on the wordline, on the hardmask, on sidewalls of the selector element and on sidewalls of the memory element; planarizing the second dielectric layer to expose an uppermost surface of the selector element; and forming a bitline on the uppermost surface of the selector memory element and on an uppermost surface of the second dielectric layer. Example embodiment 25: The memory structure of example embodiment 24 further comprising forming the metal layer as a wordline.