Prefetcher for delinquent irregular loads

Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

FIELD OF THE INVENTION

The field of invention relates generally to computer processor architecture, and, more specifically, to a prefetcher for delinquent irregular loads.

BACKGROUND

As out-of-order cores become wider and deeper, microarchitectural performance tends to become more limited by two bottlenecks: cache misses and branch mispredictions. Prefetching of data can improve performance for many applications. Through a combination of hardware and software, prefetching data before the data is actually required can lead to reduced latency of memory accesses.

The impact of a cache miss can be mitigated in multiple ways, including: 1) hiding the latency of the miss through using out-of-order execution, 2) tailoring the cache replacement policy to better match applications' needs, and, 3) by prefetching the memory location before the actual demand occurs.

Load instructions can be classified into several categories, including: a) constant loads whose virtual addresses remains constant over multiple dynamic instances, b) striding loads with successive virtual addresses mainly in arithmetic progression, and, c) irregular loads that are neither constant loads nor strided loads.

Furthermore, as described herein, loads that miss in the cache frequently (i.e., greater than a threshold number of times, such as 100, 1000, 10,000, etc.) are called delinquent loads.

Prefetching delinquent irregular loads remains an open challenge.

DETAILED DESCRIPTION OF THE EMBODIMENTS

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a feature, structure, or characteristic is described about an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic about other embodiments if explicitly described.

Disclosed embodiments describe an improved system and method for generating application-specific custom prefetchers designed specifically for each delinquent, irregular load (DIRRL)—sometimes referred to as a hard-to-prefetch (HTP) or (HTP) load—using profiling and analysis performed, for example, by a runtime Binary Translator (BT). According to some embodiments, the BT analyzes the cycles in a backward slice of instructions (a.k.a. “backslice”) of the DIRRL to determine whether the DIRRL is prefetchable. If so, the BT either generates specific code containing prefetch hint instructions or configures a custom hardware prefetcher to prefetch one or more loads in a code region containing the DIRRL.

Unlike some failed approaches, disclosed embodiments avoid relying on large amounts of on-chip storage to record address patterns and to try to predict future addresses. Besides the exorbitant amounts of on-chip memory required, the difficulty in implementing such an approach in real hardware can be seen from its absence in commercially shipping processors.

Disclosed embodiments also avoid resource-intensive, computation-based prefetching approaches that use a separate helper thread to execute the instructions from the program ahead of time to prefetch delinquent loads. Moreover, it is hard to ensure that the helper thread is not so far ahead of the main thread that it actually ends up polluting the caches.

Disclosed embodiments improve a processor architecture and its prefetching performance in several ways. One advantage of disclosed embodiments is the potential for highly accurate prefetches with low overhead because the generated prefetcher is part of the main thread itself and there is no requirement for spare thread contexts or large memories. Moreover, since the prefetcher code (or custom hardware) is generated to stay a constant number of iterations ahead of the main computation, additional effort need not be expended to match the rates of the main thread and the prefetcher. Furthermore, with the prefetches inserted only at delinquent irregular load Instruction Pointers (IPs), cache and memory bandwidth interference are kept to a minimum.

In the course of describing the disclosed embodiments below, a number of terms are defined herein and are used as part of the descriptions of disclosed embodiments. As used herein, “delinquent” loads are those load instructions with the number of first level cache misses greater than a threshold (e.g., 1K, 10K, etc.). As further used herein, “address deltas” of a load instruction are defined as the numerical differences between the virtual addresses of its successive dynamic instances. Furthermore, in some embodiments, “irregular” loads are those load instructions having at least ten unique address deltas and the ten most popular unique deltas still covering less than 90% of all the deltas. Such a definition distinguishes regular patterns such as multidimensional arrays and other occasionally irregular (but predominantly striding) loads from irregular loads in the context of disclosed embodiments.

As described herein, and as illustrated with respect toFIG. 2, some disclosed embodiments consist of three parts: 1) a profiler, 2) an optimizer, and 3) a prefetcher.

Profiler

According to some embodiments, a profiler identifies delinquent irregular loads. In some embodiments, the profiler is a combination of both hardware and binary translator (BT) software. In such embodiments, the hardware tracks the data cache misses for each load instruction in flight in order to identify the delinquent loads. In some embodiments, the BT software runs a detailed address delta profiling on identified delinquent loads to classify them as regular or irregular loads.

When disclosed embodiments are incorporated into a processor that already has stride-detecting prefetchers, the address delta information natively available to the processor can also be passed on to the BT software for analysis. Incorporating disclosed embodiments into a processor may therefore improve the processor's prefetching performance without adding much if any cost.

The disclosed profiler in some embodiments operates online (at the same time as the thread being profiled), and in other embodiments operates offline (at a different time than the actual running time of the thread, for example by analyzing source code ahead of time).

Optimizer

Some disclosed embodiments further include an optimizer that analyzes the executing code to compute a backslice of the delinquent irregular load. As used herein, a backslice (a.k.a. backward slice) of the delinquent irregular load is a set of instructions in a program that are executed prior to, and contribute, either directly or indirectly, to the operands of a delinquent irregular load instruction. Based on the address deltas (received from the profiler) of instructions in the backslice, the optimizer then identifies “prefetchable” loads as those whose backslices are made entirely of non-memory operations or regular memory operations. The optimizer is then to generate custom prefetchers for a region of code that contains the prefetchable loads.

The custom prefetchers generated by the optimizer can be either in software (generated code with prefetch hint instructions; see, e.g.,FIG. 7A) or hardware (custom hardware that captures the dataflow of the address computation; see, e.g.,FIG. 7B).

It should be understood that the 1) profiler, 2) optimizer, and 3) prefetcher are described as separate components herein for the sake of simplicity. Indeed, in some embodiments, all three of the 1) profiler, 2) optimizer, and 3) prefetcher are incorporated in and part of what is broadly referred to as “execution circuitry.” The same is true regarding the binary translator described herein. In some embodiments, the binary translator is incorporated in “execution circuitry,” while in other embodiments, the BT is separate from and external to execution circuitry.

FIG. 1Ais a block diagram illustrating processing components for executing instructions, according to some embodiments. As illustrated, storage101stores instruction(s)103to be executed. As described further below, in some embodiments, computing system100is an SIMD processor to concurrently process multiple elements of packed-data vectors, such as matrices.

In operation, instruction(s)103is fetched from storage101by fetch circuitry105. Each fetched instruction107is decoded by decode circuitry109. The instruction(s) format is illustrated and described with respect toFIGS. 8A-B, and9A-D. Decode circuitry109decodes each fetched instruction107into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry117). The decode circuitry109also decodes instruction suffixes and prefixes (if used). Execution circuitry117is further described and illustrated below with respect toFIGS. 2-3, 11A-B and12A-B.

In some embodiments, register renaming, register allocation, and/or scheduling circuit113provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded SMM instruction111for execution on execution circuitry117out of an instruction pool (e.g., using a reservation station in some embodiments). Register rename/register allocation, and/or scheduling circuit113is optional, as indicated by its dashed border, insofar as the renaming, allocation, and/or scheduling may occur at a different time, or not at all.

Registers (register file) and/or memory115store data as operands of decoded instruction111to be operated on by execution circuitry117. In some embodiments, as shown, execution circuitry117includes binary translator118, which includes BT cache119, and which is further illustrated and described with respect toFIGS. 2-3. Binary translator118is optional, as indicated by its dashed border, insofar as it may be incorporated in execution circuitry117(as shown), might be external to execution circuitry117(as shown inFIG. 1B), might instead be implemented in software, or as a combination of hardware and software.

In some embodiments, register file and/or memory115includes a cache hierarchy, including L1, L2, and L3 (or LLC) caches. In some embodiments, the caches are unified and other embodiments have separate data and instruction caches. Exemplary register types include writemask registers, packed data registers, general purpose registers, and floating-point registers, as further described and illustrated below, at least with respect toFIG. 10.

In some embodiments, write back circuit120commits the result of the execution of the decoded instruction111. Execution circuitry117and system100are further illustrated and described with respect toFIGS. 2-3, 11A-B and12A-B.

FIG. 1Bis a block diagram illustrating processing components for executing instructions, according to some embodiments. As illustrated, storage151stores instruction(s)153to be executed. As described further below, in some embodiments, computing system150is an SIMD processor to concurrently process multiple elements of packed-data vectors, such as matrices.

In operation, instruction(s)153is fetched from storage151by fetch circuitry155. Each fetched instruction157is decoded by decode circuitry159. The instruction(s) format is illustrated and described with respect toFIGS. 8A-B, and9A-D. Decode circuitry159decodes each fetched instruction157into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry167). The decode circuitry159also decodes instruction suffixes and prefixes (if used). Execution circuitry167is further described and illustrated below with respect toFIGS. 2-3, 16A-B and17A-B.

In some embodiments, register renaming, register allocation, and/or scheduling circuit163provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded SMM instruction161for execution on execution circuitry167out of an instruction pool (e.g., using a reservation station in some embodiments). Register rename/register allocation, and/or scheduling circuit163is optional, as indicated by its dashed border, insofar as the renaming, allocation, and/or scheduling may occur at a different time, or not at all.

Registers (register file) and/or memory165store data as operands of decoded instruction161to be operated on by execution circuitry167. Also shown is binary translator168, which includes BT cache169, and which is further illustrated and described with respect toFIGS. 2-3. Binary translator168is optional, as indicated by its dashed border, insofar as it may be incorporated in execution circuitry167(as shown inFIG. 1A), might be external to execution circuitry167(as shown), might instead be implemented in software, or as a combination of hardware and software.

In some embodiments, register file and/or memory165includes a cache hierarchy, including L1, L2, and L3 (or LLC) caches. In some embodiments, the caches are unified and other embodiments have separate data and instruction caches. Exemplary register types include writemask registers, packed data registers, general purpose registers, and floating-point registers, as further described and illustrated below, at least with respect toFIG. 15.

In some embodiments, write back circuit170commits the result of the execution of the decoded instruction161. Execution circuitry167and system150are further illustrated and described with respect toFIGS. 2-3, 16A-B and17A-B.

FIG. 2is a block diagram of a system for generating application-specific custom prefetchers, according to some embodiments. As shown, system200includes profiler202, optimizer212, and prefetcher222. Profiler202, which receives load miss performance counters208, includes address delta profiling204and delinquent loads filter206, and identifies and sends candidate regions210to optimizer212. Optimizer212, which includes data row analysis214, cycle enumeration216, and prefetchable load identification218, generates and sends custom prefetchers220to prefetcher222. Prefetcher222includes generated code224or custom hardware226.

FIG. 3Ais a block flow diagram of operations performed by a processor to generate application-specific custom prefetchers, according to some embodiments. A processor is to perform flow300. As shown, at302, the processor is to fetch instructions from a memory using fetch circuitry, such as fetch circuitry105(FIG. 1). In some embodiments, that memory is an L1 instruction cache. In other embodiments, that memory is an L2 or higher level cache, and in yet other embodiments, that memory is main memory. At304, the processor is to decode the fetched instructions using decode circuitry such as decode circuitry109(FIG. 1). At306, the processor is to respond to decoded instructions with execution circuitry using a binary translator to perform the operations308-314. Specifically, at308, the processor is to store a stream of decoded instructions in a BT cache memory. In some embodiments, the BT cache memory is separate from the memory115shown inFIG. 1. At310, the processor is to track cache misses of load instructions to identify delinquent loads. At312, the processor is to profile address deltas of successive instances of the delinquent loads to identify a delinquent irregular load. At314, the processor is to determine, by analyzing a backslice between successive dynamic instances of the DIRRL, whether the DIRRL is prefetchable, and, if so, generate a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL. What is meant by a “backslice,” as used herein, is further illustrated and described with respect toFIGS. 4, 5A, and 6A.

FIG. 3Bis a block flow diagram of operations performed by a processor to generate application-specific custom prefetchers, according to some embodiments. A processor is to perform flow350. As shown, at352, the processor is to fetch instructions from a memory using fetch circuitry, such as fetch circuitry105(FIG. 1). In some embodiments, that memory is an L1 instruction cache. In other embodiments, that memory is an L2 or higher level cache, and in yet other embodiments, that memory is main memory. At354, the processor is to decode the fetched instructions using decode circuitry such as decode circuitry109(FIG. 1). At356, the processor is to respond to decoded instructions using a binary translator to perform the operations358-364. Specifically, at358, the processor is to store a stream of decoded instructions in a BT cache memory. In some embodiments, the BT cache memory is separate from the memory115shown inFIG. 1. At360, the processor is to track cache misses of load instructions to identify delinquent loads. At362, the processor is to profile address deltas of successive instances of the delinquent loads to identify a delinquent irregular load. At364, the processor is to determine, by analyzing a backslice between successive dynamic instances of the DIRRL, whether the DIRRL is prefetchable, and, if so, generate a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL. What is meant by a “backslice,” as used herein, is further illustrated and described with respect toFIGS. 4, 5A, and 6A.

FIG. 4Ais a code listing illustrating a backslice, according to some embodiments. As shown, code listing400defines an exemplary function, foo( ). For ease of discussion, the code listing is illustrated in a relatively easy-to-understand C programming language syntax. Some embodiments, for example those analyzing code segments offline and ahead of time, are able to generate application-specific custom prefetchers by analyzing code segments in a high-level programming language, such as C. But some embodiments, using a hardware binary translator dynamically and on-line to generate application specific custom prefetchers, analyze instructions having an assembly code format. For example, code segments with assembly instruction format are illustrated and described with respect toFIGS. 5A, 6A, and 7A. In some embodiments, the code to be analyzed consists of macro-operations generated by decode circuitry, such as decode circuitry109(FIG. 1).

As shown, the instruction at line0160is the target instruction402, and the “backslice” is to be computed leading up to the target instruction. A “backslice,” as used herein, is the set of all instructions that contribute, either directly or indirectly, to the computation conducted in the target instruction. In some embodiments, the instructions to be included in the backslice can be identified by working backwards from the target instruction402to identify all contributing instructions that make up backslice404. For example, the instruction at line0140directly contributes to the target instruction402because it sets an operand of the instruction. Working backwards from the instruction at0140, the instructions at lines0110,0090, and0070are to be included in backslice404because they indirectly contribute to the computation of the target instruction402. In some embodiments, as here, the target instruction402is part of a loop, and the backslice extends backward to, but stops at the start of a current iteration.

Notably, some of the instructions in code listing400do not directly or indirectly contribute to the computation of target instruction402and are therefore not included in the backslice404. Instructions at lines0080,0100,0120, and0150, for example, are not included in the backslice. Instructions at lines0130and0170, even though they affect an operand, ‘c,’ used in target instruction402, are not included in the backslice because the values of ‘c’ that are set by those instructions are overwritten before reaching target instruction402.

FIG. 4Bis a custom hardware prefetcher generated for the code listing ofFIG. 4A, according to some embodiments. As shown, custom hardware prefetcher420includes a first-in, first-out (FIFO) buffer421, which has pointers for a head422and a tail424, and in which the instructions at lines [0090], [0110], and [0140] from code listing400(FIG. 4A) have been enqueued. Also shown are custom hardware prefetch control circuitry426, arithmetic/logic unit (ALU)428, and memory load unit (MLU)430.

For simplicity, and to illustrate operation of disclosed embodiments, the instructions enqueued in FIFO421are shown according to the format of a high-level programming language, such as Basic, C, Fortran, or C++. In some embodiments, however, those instructions are to instead be stored as decoded micro-operations or macro-operations generated by decode circuitry, such as decode circuitry109(FIG. 1A) or159(FIG. 1B),

In operation, custom hardware prefetch control circuitry426is to cause one or more instructions within a region of instructions leading up to target instruction402(FIG. 4A) to be enqueued in FIFO421, and to subsequently cause the processor to perform resulting arithmetic operations, if any, using ALU428, and memory loads, if any, using MLU430.

In other embodiments, different instructions from code listing400are selected for inclusion in FIFO421. For example, if one of the instructions is identified as a “critical load,” as described below, control circuitry426could cause the processor to focus on that instruction by only enqueueing that instruction and no others. In some embodiments, the entire backslice404(FIG. 4A) is added to FIFO421and performed by the processor.

FIFO421, custom hardware prefetch control circuitry426, ALU428, and MLU430are all optional, as indicated by their dashed borders, insofar as they may use hardware resources already included in the processor, they may use firmware or software, or they may not be included at all. FIFO421, for example, could be implemented within a memory already available to the processor. Some embodiments implement FIFO421using registers in a register file of the processor. Some embodiments implement FIFO421using a few dedicated registers. Some embodiments use a different memory organization than FIFO421, for example a random-access memory. ALU428, for example, could include one or more dedicated ALUs to perform arithmetic operations. ALU428, in some embodiments, uses existing processor execution unit(s)1162within execution cluster(s)1160, as illustrated and described with respect toFIGS. 11A-B.

FIG. 4Cis a custom software prefetcher generated for the code listing ofFIG. 4A, according to some embodiments. As shown, custom software prefetcher440includes a first-in, first-out (FIFO) buffer441, which has pointers for a head442and a tail444, and in which the instructions at lines [0090], [0110], and [0140] from code listing400(FIG. 4A) have been enqueued. The enqueued instructions in FIFO441are meant to serve as prefetch hints. Also shown is custom software prefetch control circuitry446.

For simplicity, and to illustrate operation of disclosed embodiments, the instructions enqueued in FIFO441are shown according to the format of a high-level programming language, such as Basic, C, Fortran, or C++. In some embodiments, however, those instructions are to instead be stored as decoded micro-operations or macro-operations generated by decode circuitry, such as decode circuitry109(FIG. 1A) or159(FIG. 1B),

In operation, custom software prefetch control circuitry446is to cause one or more instructions within a region of instructions leading up to target instruction402(FIG. 4A) to be enqueued in FIFO441, and to subsequently serve as prefetch hints to be performed by the processor.

In other embodiments, different instructions from code listing400are selected for inclusion in FIFO441. For example, if one of the instructions is identified as a “critical load,” as described below, control circuitry446could cause the processor to focus on that instruction by only enqueueing that instruction and no others. In some embodiments, control circuitry446cause the processor, when performing the prefetching, to focus on the one or more critical loads by performing the critical loads before performing non-critical loads. In some embodiments, the entire backslice404(FIG. 4A) is added to FIFO441and performed by the processor.

FIFO441and custom software prefetch control circuitry446are optional, as indicated by their dashed borders, insofar as they may use resources already included in the processor, or they may not be included at all. FIFO441, for example, could be implemented within a memory already available to the processor. For example, the one or more hints enqueued in FIFO441could instead be stored among the instructions in the memory. Some embodiments implement FIFO441using registers in a register file of the processor. Some embodiments implement FIFO441using a few dedicated registers. Some embodiments use a different memory organization than FIFO441, for example a random-access memory. Control circuitry446in some embodiments, causes the processor to respond to the enqueued hints using its existing execution pipeline, as illustrated and described with respect toFIGS. 11A-B.

Identifying a Backslice of Exemplary Assembly Code Listing, Trace 1

FIG. 5Ais a code listing of instructions to be profiled by a profiler then optimized by an optimizer, according to some embodiments. As shown, each of the instructions in assembly code listing, Trace 1500, includes an address, an opcode, operands, and a comment indicating its instruction type. Trace 1500is sometimes referred to as a “hot region,” and here is a simple 17-instruction loop with the 17th instruction looping back to the 1st instruction, and with two exit branches to exit past the end of the loop (0xef1 and 0xef7) that are rarely taken. Trace 1500has two irregular loads (0xeea and 0xf05), two stores to the stack (0xef3 and 0xf00) and the remaining loads are constant address stack loads.

Also illustrated are arcs defining the backslice of Trace 1500. Starting with the last irregular load in the loop, at 0xf05, arcs A and B identify the dependencies on 0xf03 and 0xefb, respectively. Dashed lines are used here just to allow for more easily distinguishing among the seven arcs. Continuing backward from 0xf03, arcs C and D identify the dependencies on 0xeea and 0xefd, respectively. Continuing backward from 0xefb, arc E identifies the dependency on 0xee2. Finally, continuing backward from 0xeea, arcs F and G identify the dependencies on 0xee7 and 0xee4, respectively.

Figure SB illustrates the backslice of the flow of instructions ofFIG. 5Aas a block flow diagram. As shown, seven arcs, labeled A through G, identify the same seven arcs between the same eight backslice instructions of Trace1500, which are here represented by eight flow diagram nodes. Specifically, eight flow diagram nodes, labeled as522,524,526,528,530,532,534, and536correspond to the eight instructions at Trace 1500addresses 0xee4, 0xee7, 0xee2, 0xeea, 0xefd, 0xefb, 0xf03, and 0xf05, respectively.

In operation, according to some embodiments, as further described below with respect toFIGS. 5A-Band6A-B, a processor, having a binary translator (BT) having a BT cache, stores the stream of instructions of Trace 1500to the BT cache. The binary translator, using a profiler, identifies a delinquent irregular load (DIRRL). Then, using an optimizer, the BT determines, as described below, whether the DIRRL is prefetchable, and, if so, generates a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL. The generated custom prefetcher can be implemented in software and/or hardware.

Backslice Analysis and Prefetcher Generation for Exemplary Trace 2

FIG. 6Ais a code listing of assembly instructions to be profiled by a profiler then optimized by an optimizer, according to some embodiments. As shown, each of the instructions in assembly code listing, Trace 2600, includes an address, an opcode, and operands, and some have a comment indicating their instruction types. Trace 2600is sometimes referred to as a “hot region,” and here is also a loop (with 48 instructions) but with more complex control flow (shown inFIGS. 6B and 6C). It has two striding loads (0x765 and 0x770) and four irregular loads (0x7cb, 0x7dc, 0x7ea, 0x7fb), but no stores. It also has three branches with high misprediction rates on common branch prediction circuitry.

Also illustrated are arcs defining the backslice of Trace 2600. Starting with the last irregular load in the loop, the delinquent irregular load at 0x7fb, arcs A, B, D, E, F, R, and S identify the chain of dependencies all the way back through instructions at 0x7f4, 0x7f1, 0x7ee, 0x7bf, 0x765, 0x75e, 0x75b, and 0x7e6, respectively. Dashed lines are used here just to allow for more easily distinguishing among the arcs. Starting with the penultimate irregular load at 0x7ea, arcs G and J identified dependencies to 0x7cf and 0x7bf, respectively, arcs H, K, L, and M identify dependencies to 0x7dc, 0x7d5, 0x7d2, and 0x7bf, respectively, and arcs I, N, O, P, and Q identify dependencies to 0x7cb, 0x7c8, 0x7c5, 0x770, and 0x75e, respectively.

For ease of illustration and discussion, code listing Trace 2600has been divided into eight (8) regions, labeled A602, B604, C606, D608, E610, F612, G614and H616, each of which ends with a branch instruction. The illustrated8regions are further described and illustrated inFIG. 6B, which includes nodes in a block flow diagram for each of the regions.

FIG. 6Bis a control flow diagram illustrating the backslice of the regions of Trace 2600, as defined inFIG. 6A, as a block flow diagram. As shown, Trace 2 backslice620block flow diagram includes 9 nodes corresponding to the 8 nodes defined inFIG. 6A. Specifically, 8 nodes,622,624,626,628,630,632,634and636are labeled as A through H, and are bounded by the same instructions in each node as the regions inFIG. 6A.

FIG. 6Cillustrates the backslice of the flow of instructions of Trace 2 ofFIG. 6Aas a block flow diagram. As shown, Trace 2 backslice640block flow diagram includes 18 nodes,642,644,646,648,650,652,654,656,658,660,662,664,666,668,670,672,674, and676, corresponding to 18 backslice instructions, and 19 paths, labeled A through S, labeling dependencies among the backslice instructions. The illustrated paths among the nodes match the arcs among the instructions of Trace 2 inFIG. 6A.

The backslices of Trace 1 and Trace 2, as illustrated and described with respect toFIGS. 5B, 6B, and 6C, capture the dataflow between the successive iterations of an irregular load. A forward edge (from a lower instruction address to a higher instruction address) indicates the dataflow within an iteration while a backward edge (from a higher instruction address to a lower instruction address) indicates the dataflow from the previous iteration of the loop.

InFIGS. 5B and 6C, nodes representing regular and constant loads are marked with a “#” symbol and irregular loads are marked with a “*”. It can be seen that the number of instructions in the backslice of the irregular loads is significantly smaller than the size of the loop (8<17 in Trace 1 and 18<48 in Trace 2). Disclosed embodiments are therefore advantageously able to prefetch all relevant dependencies to a target irregular load without having to prefetch all data accessed by the program.

Another advantage of disclosed embodiments is that the cycles in this backslice capture the critical relationship between successive iterations of the irregular load. A cycle describes the case where the computation performed by a later instruction depends on the output of an earlier instruction, and produces a new value that itself is depended-on by the earlier instruction when it is subsequently executed. For example,FIG. 5Bexhibits two cycles; they are: (0xee7, 0xeea) and (0xee2, 0xefb). Of these, the latter is a trivial cycle consisting only of register moves and can be ignored. Similarly, there are three cycles in the region from Trace 2: (0x7e6), (0x765, 0x7bf) and (0x770, 0x7c5). These cycles capture the essential recurrence relationship between the virtual addresses of the successive dynamic instances of the irregular loads. It is to be noted that these cycles have significantly smaller number of instructions than the backslices themselves (4 vs. 8 in Trace 1 and 5 vs. 18 in Trace 2).

Optimizer Determines Whether “Prefetchable”

The optimizer determines whether a delinquent irregular load is prefetchable by analyzing a backslice of that instruction. “Prefetchable” loads are those whose backslices have cycles made entirely of non-memory operations or regular memory operations. If the irregular delinquent load is determined to be prefetchable, the optimizer generates custom prefetchers for a region of code that contains the prefetchable loads.

In some embodiments, all the cycles in the region from Trace 2 are made either of non-memory operations or regular memory operations. Since the backslices of 0x765 and 0x770 only contain a single cycle (0x7e6) with a single register increment, it is statically evident that they both are striding loads. Thus, the cycles (0x765, 0x7bf) and (0x770, 0x7c5) do not have any irregular memory operations.

Hence, these cycles can be “run” (by prefetching the striding loads) multiple iterations ahead of the main computation, as long as the loop executes long enough. On the other hand, the non-trivial cycle in Trace 1 (0xee7, 0xeea) has one constant address load (0xee7) but the other load (0xeea) is irregular. So, it is not possible to “run” this cycle by just prefetching 0xee7. In fact, 0xeea is a “pointer-chasing” load, whose latency to memory cannot be reduced, short of shifting that whole computation closer to memory. From the reasoning above, the region in Trace 2 is “prefetchable” while that in Trace 1 is not.

As described above, the optimizer performs dataflow analysis of the region with the irregular loads. It generates the dataflow graph for the integer dataflow of the address computation and enumerates all the elementary cycles in the graph. If none of the elementary cycles has any irregular memory ops, the optimizer determines the region as prefetchable and generates a custom prefetcher for it.

Another advantageous aspect of disclosed embodiments derives from that fact that a popular pattern in irregular loads is indirection from striding loads, i.e., the value of a striding load is used as the address of an irregular load with an optional linear transformation (K1*Address+K2 where K1 and K2 are constants). This occurs in indirect programmatic access patterns such as A [B[i]] where B is a contiguous array of indices. The technique applied in disclosed embodiments will not only determine such scenarios as prefetchable and generate custom prefetchers for them, but also is applicable to more general situations where the transformation can be any arbitrary function (not necessarily linear, i.e., A [f(B[i]] where f is an arbitrary function). For instance, such access patterns are popular in hash tables where f is the hashing function of interest.

Optimizer Generates Custom Prefetchers

According to disclosed embodiments, the next step after the identification of prefetchable loads is to generate the custom prefetchers for them. In some embodiments, the software profiler applies a heuristic approach to define custom prefetchers, either as software or hardware, to prefetch a calculated number of iterations worth of instructions from the loop, wherein the calculation involves estimating how long it will take to execute the instructions in the loop, and then prefetching enough iterations of the loop to establish a “look ahead” and stay enough ahead of the code instructions so as to hide the latency encountered by cache misses.

Furthermore, in some embodiments the software profiler identifies one or more “critical loads” in the loop that are expected to require a relatively higher number of cycles to execute, and then generates custom prefetchers targeting those critical load(s). Critical loads may include those that experience frequent cache misses. Critical loads may include those that are coupled with complex arithmetic operations. In some embodiments, the custom prefetchers cause the processor to focus on the critical loads, if any. To focus on critical loads, the custom prefetchers may cause the processor to perform those critical loads before non-critical operations.

In some embodiments, apart from register moves, operations performed in the backslice and selected for inclusion in custom prefetchers are loads and arithmetic and/or logical operations, which, in the case of hardware prefetchers, are all implemented using a few dedicated address generation units and ALUs. The selected arithmetic and/or logical operations, if any, include one or more of addition, subtraction, increment, decrement, multiply, divide, AND, OR, XOR, negate, and shift. In some embodiments, the selected arithmetic operations, In some embodiments, the selected arithmetic operations include complex operations, such as square root. In some embodiments, the selected arithmetic operations include trigonometric operations.

FIG. 7Aillustrates an exemplary application-specific custom software prefetcher, according to some embodiments. Illustrated is a custom software prefetcher generated for Trace 2 using the prefetch hint instruction ‘prefetch0/.’ The prefetch is implemented by inserting software prefetch snippet700right after the instruction at address 0x770 and stays two iterations ahead of the main loop. The disclosed embodiment assumes that % bn are the registers reserved for the BT's use and that the masking at instruction, “0x75e: and $0x1fff, % r13d,” of Trace 2 does not cause a wrap-around. So, in some embodiments, a one-time check for the wrap-around condition is inserted before BT-generated code before entering the loop with the custom prefetcher. In some embodiments, for the rare situation when the wrap-around condition is true, a separate version of the loop without the custom prefetcher is used. Also, software prefetch snippet700does not have any intervening stores between successive iterations of the loop. If there were intervening stores, speculative loads and alias checking support of the BT engine would be employed.

In some embodiments, all the loads in the custom software prefetch snippet700are made into speculative loads to ensure there is no change to the memory ordering of the application.

FIG. 7Billustrates an exemplary application-specific custom hardware prefetcher that corresponds to the custom software prefetcher ofFIG. 7A, according to some embodiments. Hardware prefetcher720is the hardware alternative of the prefetcher for Trace 2 and is implemented in custom hardware that is closely coupled with the CPU's striding load prefetchers (Strider 1722and Strider 2724inFIG. 7B). The inputs to the strider blocks are the striding load instructions (at addresses 0x765 and 0x770) for which the user wants to track the addresses. The ‘Value’ blocks726and728access the cache and the data translation lookaside buffer (DTLB), while the ‘+’ operations730and732, and the ‘&’ operations734and736are addition and bitwise AND operations, respectively. The ‘Address’ block738is an address generation unit that computes the virtual address742based on the value740and the base-index-scale inputs. For the purposes of clarity,FIG. 7Bshows the scenario where the prefetcher stays one iteration ahead of the main computation. However, this look-head can be increased by configuring the striders to correspondingly stay further ahead and by reusing the ALUs for multiple iterations of the look ahead. It is to be noted that this hardware in some embodiments is to be enabled on entry into the loop and disabled on exit from it.

Further Examples

Example 1 provides an exemplary processor including: a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory, and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a stream of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the stream, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Example 2 includes the substance of the exemplary processor of Example 1, wherein the DIRRL is a delinquent load that experiences greater than a first threshold number of cache misses on successive dynamic instances.

Example 3 includes the substance of the exemplary processor of Example 2, wherein the DIRRL is an irregular load having at least a second threshold number of address deltas among its successive dynamic instances, and wherein the second threshold number of address deltas covers less than a third threshold number of successive dynamic instances.

Example 4 includes the substance of the exemplary processor of Example 3, wherein the execution circuitry is to compute a backslice between two successive dynamic instances of the DIRRL, and to determine that the DIRRL is prefetchable when the backslice includes cycles made entirely of non-memory operations or regular memory operations.

Example 5 includes the substance of the exemplary processor of Example 4, wherein the custom prefetcher is to cause the processor to prefetch a single, critical load among the backslice.

Example 6 includes the substance of the exemplary processor of Example 4, wherein the custom prefetcher is to cause the processor to prefetch a plurality of irregular loads, the plurality to contain fewer instructions than are contained in the backslice.

Example 7 includes the substance of the exemplary processor of Example 1, wherein the custom prefetcher includes one or more prefetch hints stored among the stream of instructions in the memory.

Example 8 includes the substance of the exemplary processor of Example 1, wherein the custom prefetcher includes a hardware prefetcher using the execution circuitry.

Example 9 includes the substance of the exemplary processor of Example 1, wherein the BT is separate from the execution circuitry.

Example 10 includes the substance of the exemplary processor of Example 1, wherein the BT is incorporated into the execution circuitry.

Example 11 provides an exemplary method performed by a processor including: fetching and decoding instructions from a memory using fetch and decode circuitry, responding to decoded instructions with execution circuitry using a binary translator to: store a stream of decoded instructions in a BT cache memory, track cache misses of load instructions to identify delinquent loads, profile address deltas of successive instances of the delinquent loads to identify a delinquent irregular load (DIRRL), determine, by analyzing a backslice between successive dynamic instances of the DIRRL, whether the DIRRL is prefetchable, and, if so, generate a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Example 12 includes the substance of the exemplary method of Example 11, wherein the DIRRL is a delinquent load whose successive instances experience greater than a first threshold number of cache misses.

Example 13 includes the substance of the exemplary method of Example 12, wherein the DIRRL is further an irregular load having at least a second threshold number of address deltas among its successive dynamic instances, and wherein the second threshold number of address deltas covers less than a third threshold number of successive dynamic instances.

Example 14 includes the substance of the exemplary method of Example 11, wherein the DIRRL is determined to be prefetchable when the backslice includes instructions including entirely of non-memory operations or regular memory operations.

Example 15 includes the substance of the exemplary method of Example 11, wherein the custom prefetcher includes one or more prefetch hints stored in the memory among the stream of instructions in memory.

Example 16 includes the substance of the exemplary method of Example 11, wherein the custom prefetcher includes a custom hardware prefetcher using the execution circuitry.

Example 17 includes the substance of the exemplary processor of Example 11, wherein the custom prefetcher is to cause the processor to prefetch a single, critical load among the backslice.

Example 18 includes the substance of the exemplary processor of Example 11, wherein the custom prefetcher is to cause the processor to prefetch a plurality of irregular loads, the plurality to contain fewer instructions than are contained in the backslice.

Example 19 includes the substance of the exemplary method of Example 11, wherein the BT is separate from the execution circuitry.

Example 20 includes the substance of the exemplary method of Example 11, wherein the BT is incorporated into the execution circuitry.

Example 21 provides an exemplary processor comprising: a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory, and a binary translator (BT) to respond to the decoded instructions by: storing a plurality of the decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the stored instructions, determining whether the DIRRL is prefetchable, and if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Example 22 includes the substance of the exemplary processor of Example 21, wherein the DIRRL is a delinquent load that experiences greater than a first threshold number of cache misses on successive dynamic instances.

Example 23 includes the substance of the exemplary processor of Example 22, wherein the DIRRL is an irregular load having at least a second threshold number of address deltas among its successive dynamic instances, and wherein the second threshold number of address deltas covers less than a third threshold number of successive dynamic instances.

Example 24 includes the substance of the exemplary processor of Example 23, wherein the execution circuitry is to compute a backslice between two successive dynamic instances of the DIRRL, and to determine that the DIRRL is prefetchable when the backslice comprises cycles made entirely of non-memory operations or regular memory operations.

Example 25 includes the substance of the exemplary processor of Example 24, wherein the custom prefetcher is to cause the processor to prefetch one or more critical loads among the backslice.

Example 26 includes the substance of the exemplary processor of Example 24, wherein the custom prefetcher is to cause the processor to prefetch a plurality of irregular loads, the plurality to contain fewer instructions than are contained in the backslice.

Example 27 includes the substance of the exemplary processor of Example 21, wherein the custom prefetcher comprises one or more prefetch hints stored among the plurality of instructions in the memory.

Example 28 includes the substance of the exemplary processor of Example 21, wherein the custom prefetcher comprises a hardware prefetcher using the execution circuitry.

Example 29 includes the substance of the exemplary processor of Example 21, wherein the processor further includes execution circuitry, and wherein the BT is separate from the execution circuitry.

Example 30 includes the substance of the exemplary processor of Example 21, wherein the processor further includes execution circuitry, and wherein the BT is incorporated into the execution circuitry.

Example 31 provides an exemplary non-transitory computer-readable medium containing instructions that, when performed by a computing apparatus, cause the computing apparatus to respond by: fetching and decoding instructions from a memory using fetch and decode circuitry, and responding to decoded instructions using a binary translator (BT) to: store a plurality of decoded instructions in a BT cache memory, track cache misses of load instructions to identify delinquent loads, profile address deltas of successive instances of the delinquent loads to identify a delinquent irregular load (DIRRL), and determine, by analyzing a backslice between successive dynamic instances of the DIRRL, whether the DIRRL is prefetchable, and, if so, generate a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Example 32 includes the substance of the exemplary computer-readable medium of Example 31, wherein the DIRRL is a delinquent load whose successive instances experience greater than a first threshold number of cache misses.

Example 33 includes the substance of the exemplary computer-readable medium of Example 32, wherein the DIRRL has at least a second threshold number of address deltas among its successive dynamic instances, and wherein the second threshold number of address deltas covers less than a third threshold number of successive dynamic instances.

Example 34 includes the substance of the exemplary computer-readable medium of Example 31, wherein the DIRRL is determined to be prefetchable when the backslice comprises instructions comprising entirely of non-memory operations or regular memory operations.

Example 35 includes the substance of the exemplary computer-readable medium of Example 31, wherein the custom prefetcher comprises one or more prefetch hints stored in the memory among the plurality of instructions in memory.

Instruction Sets

Exemplary Instruction Formats

Generic Vector Friendly Instruction Format

FIGS. 8A-8Bare block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to some embodiments of the invention.FIG. 8Ais a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to some embodiments of the invention; whileFIG. 8Bis a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to some embodiments of the invention. Specifically, a generic vector friendly instruction format800for which are defined class A and class B instruction templates, both of which include no memory access805instruction templates and memory access820instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

The class A instruction templates inFIG. 8Ainclude: 1) within the no memory access805instruction templates there is shown a no memory access, full round control type operation810instruction template and a no memory access, data transform type operation815instruction template; and 2) within the memory access820instruction templates there is shown a memory access, temporal825instruction template and a memory access, non-temporal830instruction template. The class B instruction templates inFIG. 8Binclude: 1) within the no memory access805instruction templates there is shown a no memory access, write mask control, partial round control type operation812instruction template and a no memory access, write mask control, vsize type operation817instruction template; and 2) within the memory access820instruction templates there is shown a memory access, write mask control827instruction template.

The generic vector friendly instruction format800includes the following fields listed below in the order illustrated inFIGS. 8A-8B.

Base operation field842—its content distinguishes different base operations.

Augmentation operation field850—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In some embodiments, this field is divided into a class field868, an alpha field852, and a beta field854. The augmentation operation field850allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field860—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).

Displacement Field862A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).

Displacement Factor Field862B (note that the juxtaposition of displacement field862A directly over displacement factor field862B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field874(described later herein) and the data manipulation field854C. The displacement field862A and the displacement factor field862B are optional in the sense that they are not used for the no memory access805instruction templates and/or different embodiments may implement only one or none of the two.

Class field868—its content distinguishes between different classes of instructions. With reference toFIGS. 8A-B, the contents of this field select between class A and class B instructions. InFIGS. 8A-B, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A868A and class B868B for the class field868respectively inFIGS. 8A-B).

Instruction Templates of Class A

In the case of the non-memory access805instruction templates of class A, the alpha field852is interpreted as an RS field852A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round852A.1and data transform852A.2are respectively specified for the no memory access, round type operation810and the no memory access, data transform type operation815instruction templates), while the beta field854distinguishes which of the operations of the specified type is to be performed. In the no memory access805instruction templates, the scale field860, the displacement field862A, and the displacement scale filed862B are not present.

In the no memory access full round control type operation810instruction template, the beta field854is interpreted as a round control field854A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field854A includes a suppress all floating-point exceptions (SAE) field856and a round operation control field858, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field858).

SAE field856—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's856content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating-point exception handler.

In the no memory access data transform type operation815instruction template, the beta field854is interpreted as a data transform field854B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access820instruction template of class A, the alpha field852is interpreted as an eviction hint field852B, whose content distinguishes which one of the eviction hints is to be used (inFIG. 8A, temporal852B.1and non-temporal852B.2are respectively specified for the memory access, temporal825instruction template and the memory access, non-temporal830instruction template), while the beta field854is interpreted as a data manipulation field854C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access820instruction templates include the scale field860, and optionally the displacement field862A or the displacement scale field862B.

Memory Access Instruction Templates—Temporal

Memory Access Instruction Templates—Non-Temporal

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field852is interpreted as a write mask control (Z) field852C, whose content distinguishes whether the write masking controlled by the write mask field870should be a merging or a zeroing.

In the case of the non-memory access805instruction templates of class B, part of the beta field854is interpreted as an RL field857A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round857A.1and vector length (VSIZE)857A.2are respectively specified for the no memory access, write mask control, partial round control type operation812instruction template and the no memory access, write mask control, VSIZE type operation817instruction template), while the rest of the beta field854distinguishes which of the operations of the specified type is to be performed. In the no memory access805instruction templates, the scale field860, the displacement field862A, and the displacement scale filed862B are not present.

In the no memory access, write mask control, partial round control type operation810instruction template, the rest of the beta field854is interpreted as a round operation field859A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating-point exception handler).

Round operation control field859A—just as round operation control field858, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field859A allows for the changing of the rounding mode on a per instruction basis. In some embodiments where a processor includes a control register for specifying rounding modes, the round operation control field's850content overrides that register value.

In the no memory access, write mask control, VSIZE type operation817instruction template, the rest of the beta field854is interpreted as a vector length field859B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access820instruction template of class B, part of the beta field854is interpreted as a broadcast field857B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field854is interpreted the vector length field859B. The memory access820instruction templates include the scale field860, and optionally the displacement field862A or the displacement scale field862B.

With regard to the generic vector friendly instruction format800, a full opcode field874is shown including the format field840, the base operation field842, and the data element width field864. While one embodiment is shown where the full opcode field874includes all of these fields, the full opcode field874includes less than all of these fields in embodiments that do not support all of them. The full opcode field874provides the operation code (opcode).

The augmentation operation field850, the data element width field864, and the write mask field870allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

Exemplary Specific Vector Friendly Instruction Format

FIG. 9Ais a block diagram illustrating an exemplary specific vector friendly instruction format according to some embodiments of the invention.FIG. 9Ashows a specific vector friendly instruction format900that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format900may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD RIM field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields fromFIG. 8into which the fields fromFIG. 9Amap are illustrated.

It should be understood that, although embodiments of the invention are described with reference to the specific vector friendly instruction format900in the context of the generic vector friendly instruction format800for illustrative purposes, the invention is not limited to the specific vector friendly instruction format900except where claimed. For example, the generic vector friendly instruction format800contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format900is shown as having fields of specific sizes. By way of specific example, while the data element width field864is illustrated as a one bit field in the specific vector friendly instruction format900, the invention is not so limited (that is, the generic vector friendly instruction format800contemplates other sizes of the data element width field864).

The generic vector friendly instruction format800includes the following fields listed below in the order illustrated inFIG. 9A.

Format Field840(EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field840and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in some embodiments).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.

Data element width field864(EVEX byte 2, bit [7]—W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.0868Class field (EVEX byte 2, bit [2]—U)—If EVEX.0=0, it indicates class A or EVEX.U0; if EVEX.0=1, it indicates class B or EVEX.U1.

Alpha field852(EVEX byte 3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with α)—as previously described, this field is context specific.

Real Opcode Field930(Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field940(Byte 5) includes MOD field942, Reg field944, and R/M field946. As previously described, the MOD field's942content distinguishes between memory access and non-memory access operations. The role of Reg field944can be summarized to two situations: encoding either the destination register operand or a source register operand or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field946may include the following: encoding the instruction operand that references a memory address or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's850content is used for memory address generation. SIB.xxx954and SIB.bbb956—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field862A (Bytes 7-10)—when MOD field942contains 10, bytes 7-10 are the displacement field862A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Full Opcode Field

FIG. 9Bis a block diagram illustrating the fields of the specific vector friendly instruction format900that make up the full opcode field874according to some embodiments. Specifically, the full opcode field874includes the format field840, the base operation field842, and the data element width (W) field864. The base operation field842includes the prefix encoding field925, the opcode map field915, and the real opcode field930.

Register Index Field

FIG. 9Cis a block diagram illustrating the fields of the specific vector friendly instruction format900that make up the register index field844according to some embodiments. Specifically, the register index field844includes the REX field905, the REX′ field910, the MODR/M.reg field944, the MODR/M.r/m field946, the VVVV field920, xxx field954, and the bbb field956.

Augmentation Operation Field

FIG. 9Dis a block diagram illustrating the fields of the specific vector friendly instruction format900that make up the augmentation operation field850according to some embodiments. When the class (U) field868contains 0, it signifies EVEX.U0 (class A868A); when it contains 1, it signifies EVEX.U1 (class B868B). When U=0 and the MOD field942contains 11 (signifying a no memory access operation), the alpha field852(EVEX byte 3, bit [7]—EH) is interpreted as the rs field852A. When the rs field852A contains a 1 (round852A.1), the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as the round control field854A. The round control field854A includes a one bit SAE field856and a two bit round operation field858. When the rs field852A contains a 0 (data transform852A.2), the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data transform field854B. When U=0 and the MOD field942contains 00, 01, or 10 (signifying a memory access operation), the alpha field852(EVEX byte 3, bit [7]—EH) is interpreted as the eviction hint (EH) field852B and the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data manipulation field854C.

When U=1, the alpha field852(EVEX byte 3, bit [7]—EH) is interpreted as the write mask control (Z) field852C. When U=1 and the MOD field942contains 11 (signifying a no memory access operation), part of the beta field854(EVEX byte 3, bit [4]—S0) is interpreted as the RL field857A; when it contains a 1 (round857A.1) the rest of the beta field854(EVEX byte 3, bit [6-5]—S2-1) is interpreted as the round operation field859A, while when the RL field857A contains a 0 (VSIZE857.A2) the rest of the beta field854(EVEX byte 3, bit [6-5]—S2-1) is interpreted as the vector length field859B (EVEX byte 3, bit [6-5]—L1-0). When U=1 and the MOD field942contains 00, 01, or 10 (signifying a memory access operation), the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as the vector length field859B (EVEX byte 3, bit [6-5]—L1-0) and the broadcast field857B (EVEX byte 3, bit [4]—B).

Exemplary Register Architecture

FIG. 10is a block diagram of a register architecture1000according to some embodiments. In the embodiment illustrated, there are 32 vector registers1010that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format900operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field859B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field859B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format900operate on packed or scalar single/double-precision floating-point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers1015—in the embodiment illustrated, there are 8 write mask registers (k0 through k7), each 64 bits in size. In an alternate embodiment, the write mask registers1015are 16 bits in size. As previously described, in some embodiments, the vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask of 0xffff, effectively disabling write masking for that instruction.

Scalar floating-point stack register file (x87 stack)1045, on which is aliased the MMX packed integer flat register file1050—in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, less, or different register files and registers.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 11A, a processor pipeline1100includes a fetch stage1102, a length decode stage1104, a decode stage1106, an allocation stage1108, a renaming stage1110, a scheduling (also known as a dispatch or issue) stage1112, a register read/memory read stage1114, an execute stage1116, a write back/memory write stage1118, an exception handling stage1122, and a commit stage1124.

FIG. 11Bshows processor core1190including a front end unit1130coupled to an execution engine unit1150, and both are coupled to a memory unit1170. The core1190may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core1190may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit1130includes a branch prediction unit1132coupled to an instruction cache unit1134, which is coupled to an instruction translation lookaside buffer (TLB)1136, which is coupled to an instruction fetch unit1138, which is coupled to a decode unit1140. The decode unit1140(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit1140may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core1190includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit1140or otherwise within the front end unit1130). The decode unit1140is coupled to a rename/allocator unit1152in the execution engine unit1150.

The execution engine unit1150includes the rename/allocator unit1152coupled to a retirement unit1154and a set of one or more scheduler unit(s)1156. The scheduler unit(s)1156represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)1156is coupled to the physical register file(s) unit(s)1158. Each of the physical register file(s) units1158represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit1158comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)1158is overlapped by the retirement unit1154to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit1154and the physical register file(s) unit(s)1158are coupled to the execution cluster(s)1160. The execution cluster(s)1160includes a set of one or more execution units1162and a set of one or more memory access units1164. The execution units1162may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)1156, physical register file(s) unit(s)1158, and execution cluster(s)1160are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)1164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units1164is coupled to the memory unit1170, which includes a data TLB unit1172coupled to a data cache unit1174coupled to a level 2 (L2) cache unit1176. In one exemplary embodiment, the memory access units1164may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit1172in the memory unit1170. The instruction cache unit1134is further coupled to a level 2 (L2) cache unit1176in the memory unit1170. The L2 cache unit1176is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline1100as follows: 1) the instruction fetch1138performs the fetch and length decoding stages1102and1104; 2) the decode unit1140performs the decode stage1106; 3) the rename/allocator unit1152performs the allocation stage1108and renaming stage1110; 4) the scheduler unit(s)1156performs the schedule stage1112; 5) the physical register file(s) unit(s)1158and the memory unit1170perform the register read/memory read stage1114; the execution cluster1160perform the execute stage1116; 6) the memory unit1170and the physical register file(s) unit(s)1158perform the write back/memory write stage1118; 7) various units may be involved in the exception handling stage1122; and 8) the retirement unit1154and the physical register file(s) unit(s)1158perform the commit stage1124.

Specific Exemplary in-Order Core Architecture

FIG. 12Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network1202and with its local subset of the Level 2 (L2) cache1204, according to some embodiments of the invention. In one embodiment, an instruction decoder1200supports the x86 instruction set with a packed data instruction set extension. An L1 cache1206allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit1208and a vector unit1210use separate register sets (respectively, scalar registers1212and vector registers1214) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache1206, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 12Bis an expanded view of part of the processor core inFIG. 12Aaccording to some embodiments of the invention.FIG. 12Bincludes an L1 data cache1206A part of the L1 cache1204, as well as more detail regarding the vector unit1210and the vector registers1214. Specifically, the vector unit1210is a 16-wide vector processing unit (VPU) (see the 16-wide ALU1228), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit1220, numeric conversion with numeric convert units1222A-B, and replication with replication unit1224on the memory input. Write mask registers1226allow predicating resulting vector writes.

FIG. 13is a block diagram of a processor1300that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to some embodiments of the invention. The solid lined boxes inFIG. 13illustrate a processor1300with a single core1302A, a system agent1310, a set of one or more bus controller units1316, while the optional addition of the dashed lined boxes illustrates an alternative processor1300with multiple cores1302A-N, a set of one or more integrated memory controller unit(s)1314in the system agent unit1310, and special purpose logic1308.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units1306, and external memory (not shown) coupled to the set of integrated memory controller units1314. The set of shared cache units1306may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit1312interconnects the integrated graphics logic1308(integrated graphics logic1308is an example of and is also referred to herein as special purpose logic), the set of shared cache units1306, and the system agent unit1310/integrated memory controller unit(s)1314, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units1306and cores1302-A-N.

In some embodiments, one or more of the cores1302A-N are capable of multithreading. The system agent1310includes those components coordinating and operating cores1302A-N. The system agent unit1310may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1302A-N and the integrated graphics logic1308. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 14, shown is a block diagram of a system1400in accordance with one embodiment of the present invention. The system1400may include one or more processors1410,1415, which are coupled to a controller hub1420. In one embodiment the controller hub1420includes a graphics memory controller hub (GMCH)1490and an Input/Output Hub (IOH)1450(which may be on separate chips); the GMCH1490includes memory and graphics controllers to which are coupled memory1440and a coprocessor1445; the IOH1450couples input/output (I/O) devices1460to the GMCH1490. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1440and the coprocessor1445are coupled directly to the processor1410, and the controller hub1420in a single chip with the IOH1450.

The optional nature of additional processors1415is denoted inFIG. 14with broken lines. Each processor1410,1415may include one or more of the processing cores described herein and may be some version of the processor1300.

The memory1440may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1420communicates with the processor(s)1410,1415via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1495.

In one embodiment, the coprocessor1445is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1420may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1410,1415in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1410executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1410recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1445. Accordingly, the processor1410issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1445. Coprocessor(s)1445accept and execute the received coprocessor instructions.

Referring now toFIG. 15, shown is a block diagram of a first more specific exemplary system1500in accordance with an embodiment of the present invention. As shown inFIG. 15, multiprocessor system1500is a point-to-point interconnect system, and includes a first processor1570and a second processor1580coupled via a point-to-point interconnect1550. Each of processors1570and1580may be some version of the processor1300. In some embodiments, processors1570and1580are respectively processors1410and1415, while coprocessor1538is coprocessor1445. In another embodiment, processors1570and1580are respectively processor1410coprocessor1445.

Processors1570and1580are shown including integrated memory controller (IMC) units1572and1582, respectively. Processor1570also includes as part of its bus controller units point-to-point (P-P) interfaces1576and1578; similarly, second processor1580includes P-P interfaces1586and1588. Processors1570,1580may exchange information via a point-to-point (P-P) interface1550using P-P interface circuits1578,1588. As shown inFIG. 15, IMCs1572and1582couple the processors to respective memories, namely a memory1532and a memory1534, which may be portions of main memory locally attached to the respective processors.

Processors1570,1580may each exchange information with a chipset1590via individual P-P interfaces1552,1554using point to point interface circuits1576,1594,1586,1598. Chipset1590may optionally exchange information with the coprocessor1538via a high-performance interface1592. In one embodiment, the coprocessor1538is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1590may be coupled to a first bus1516via an interface1596. In one embodiment, first bus1516may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 15, various I/O devices1514may be coupled to first bus1516, along with a bus bridge1518which couples first bus1516to a second bus1520. In one embodiment, one or more additional processor(s)1515, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1516. In one embodiment, second bus1520may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1520including, for example, a keyboard and/or mouse1522, communication devices1527and a storage unit1528such as a disk drive or other mass storage device which may include instructions/code and data1530, in one embodiment. Further, an audio I/O1524may be coupled to the second bus1520. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 15, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 16, shown is a block diagram of a second more specific exemplary system1600in accordance with an embodiment of the present invention. Like elements inFIGS. 15 and 16bear like reference numerals, and certain aspects ofFIG. 15have been omitted fromFIG. 16in order to avoid obscuring other aspects ofFIG. 16.

FIG. 16illustrates that the processors1570,1580may include integrated memory and I/O control logic (“CL”)1572and1582, respectively. Thus, the CL1572,1582include integrated memory controller units and include I/O control logic.FIG. 16illustrates that not only are the memories1532,1534coupled to the CL1572,1582, but also that I/O devices1614are also coupled to the control logic1572,1582. Legacy I/O devices1615are coupled to the chipset1590.

Referring now toFIG. 17, shown is a block diagram of a SoC1700in accordance with an embodiment of the present invention. Similar elements inFIG. 13bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 17, an interconnect unit(s)1702is coupled to: an application processor1710which includes a set of one or more cores1302A-N, which include cache units1304A-N, and shared cache unit(s)1306; a system agent unit1310; a bus controller unit(s)1316; an integrated memory controller unit(s)1314; a set or one or more coprocessors1720which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1730; a direct memory access (DMA) unit1732; and a display unit1740for coupling to one or more external displays. In one embodiment, the coprocessor(s)1720include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.