According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC structures (such as three-dimensional transistors) and processing and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed. For example, device performance (such as device performance degradation associated with various defects) and fabrication cost of field-effect transistors become more challenging when device sizes continue to decrease. Although methods for addressing such a challenge have been generally adequate, they have not been entirely satisfactory in all aspects.

DETAILED DESCRIPTION

The present disclosure is generally related to semiconductor devices and the fabrication thereof, and more particularly to methods of fabricating field-effect transistors (FETs), particularly, as fin-like FETs (FinFETs). FinFET devices provide for improved device performance over planar transistors because in a finFET device, the gate surrounds three sides of the channel. Conventional methods for forming a finFET device involve forming a dummy gate over a set of fin structures running in parallel. Sidewall spacers are then formed on the sidewalls of the gate. After the sidewall spacers are formed, source/drain regions may be formed on the fin structures on both sides of the gate. After the source/drain regions are formed, and an interlayer Dielectric Layer (ILD) is formed over the source/drain regions, the dummy gate can be replaced with a real gate that includes a conductive material such as a metal material. However, as technology nodes move to smaller and smaller pitch sizes, it becomes difficult to form the dummy gate properly within the spaces between fin structures. Moreover, heavy etching is often required to remove the polysilicon residue from the spaces between the fin structures. This heavy etching can cause damage to the fin structures and thus limits the size and pitch of fin structures.

According to principles described herein, instead of forming the dummy gate between the fin structures, a sacrificial material is deposited within the space between the fin structures. Then, the dummy gate is formed as a planar structure along the top of the fin structures. After the sidewall structure is formed on that dummy gate structure, the sacrificial material underneath the sidewall structure may be laterally etched and replaced with a dielectric material. Then, at the appropriate time, when the dummy gate is removed, the sacrificial material underneath the dummy gate is removed as well. This exposes the space between the fin structures. Then, the real (e.g., metal) gate structure can then be formed over and between the fin structures.

FIGS.1A,1B,1C,1D,1E,1F,1G,1H,1I,1J,1K,1L,1M,1N,1O,1P,1Q,1R,1S, and1T are diagrams showing an illustrative process for forming a finFET structure with improved pitch scaling.FIG.1Aillustrates a set of fin structures104formed on a substrate102. In the present example, there are different clusters101of fin structures separated by spaces103. In general, the pitch of fin structures within a particular cluster101is substantially consistent and may be less than 24 nanometers. The space between fin structures may be within a range of about 5-10 nanometers. The height of the fin structures104may be greater than 50 nanometers or greater than 60 nanometers. Using the techniques described herein, a larger fin height is achieved in comparison to conventional processes. The larger fin height improves devices performance.

The semiconductor substrate102may be a silicon substrate. The semiconductor substrate may be part of a silicon wafer. Other semiconductor materials are contemplated. The substrate102may include an elementary (single element) semiconductor, such as silicon, germanium, and/or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The substrate102may be a single-layer material having a uniform composition. Alternatively, the substrate102may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate102may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, the substrate102may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof.

The fin structures104may be formed using a patterning process. For example, a hard mask layer106and a photoresist layer (not shown) may be deposited onto the substrate102. The hardmask layer106may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2). Other materials are contemplated. The photoresist may then be exposed to a light source through a photomask. The photoresist may then be developed such that the portions of the photoresist remain while other portions are removed. The pattern within the developed photomask is then transferred to the hard mask layer106, which is then transferred to the substrate102through an etching process. This forms the fin structures104as shown. The fin structures comprise elongated fin-like structures that run parallel to each other.FIG.1Aillustrates a view that is cut perpendicular to the direction in which the fin structures104run.

FIG.1Billustrates a process by which an isolation structure108is formed. The isolation structure may be, for example, a shallow trench isolation (STI) structure. The STI layer108may be a dielectric material that is used to electrically isolate one device from another. After the STI material is deposited, a Chemical Mechanical Polishing (CMP) process is applied to planarize the top surface of the workpiece such that the hard mask layer106is exposed. A CMP process involves applying a slurry to the surface of the workpiece. The slurry includes etching chemicals as well as solid particles. A polishing head is then moved across the surface of the workpiece and the chemical and mechanical forces on the workpiece result in removing material from the workpiece at a substantially similar rate so as to create a planar surface.

FIG.1Cillustrates a process by which the STI layer108is recessed. The STI layer108may be recessed to a point approximately halfway between a bottom and a top of the fin structure. However, in some examples, the STI layer108may be recessed to different heights along the height of the fin structures104.

FIG.1Dillustrates the formation of a sacrificial material110on and between the fin structures104. The sacrificial material110may be, for example, silicon nitride (SiN) or silicon germanium (SiGe). Such materials are easier to fit within the spaces between fin structures. In some examples, the sacrificial material is selectively deposited over the fin structures104so as to leave the spaces103between sets of fin structures exposed. In some examples, however, the sacrificial material110may be formed over the spaces103as well and then removed using a directional etching process such as a dry etching process. Such processes may be similar to spacer etching processes.

FIG.1Eillustrates the formation of a first dielectric layer112over the fin structures104and the spaces103between sets of fin structures101. The first dielectric layer112may be a low-k dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN). The first dielectric layer112is formed in a conformal manner along sidewalls of the space103between sets of fin structures101and along the bottom of the STI layer108.

FIG.1Fillustrates the formation of an oxide layer114over the first dielectric layer112and a CMP process to planarize the top surface of the work-piece. The CMP process also exposes the top surfaces of the fin structures104and the sacrificial material110.

FIG.1Gillustrates a process by which the oxide layer114is recessed. This may be done using a selective etching process. The selective etching process may be designed such that when applied, it removes the oxide layer114without substantially affecting the other layers, such as the first dielectric layer112, the fin structures104and the sacrificial material110.

FIG.1Hillustrates the formation of a second dielectric layer116on the oxide layer within the space created by the recessing process illustrated inFIG.1G. The second dielectric layer116may also be a low-k dielectric material. The second dielectric layer116may be, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN). In some examples, the second dielectric layer116may be a high-k dielectric such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium aluminum oxide (HfAlOx), hafnium silicon oxide (HfSiOx), or aluminum oxide (Al2O3). As will be shown in more detail below, the second dielectric layer116isolates the oxide layer114from the gate structure. In some examples, after the second dielectric layer116is formed, a CMP process is performed to planarize the surface of the workpiece.

FIG.1Iillustrates the formation of a dummy gate layer118, along with two hard mask layers120,122. The first hard mask layer120may be a silicon nitride layer and the second hard mask layer122may be an oxide layer. The dummy gate layer118is thus formed along a planar surface. In other words, the bottom surface of the dummy gate layer118directly contacts a planar line that includes top surfaces of the fin structures104, the sacrificial material110, the first dielectric layer112, and the second dielectric layer116. The dummy gate layer118may be a polysilicon layer. Because the polysilicon dummy gate layer118is deposited onto a planar surface, there are fewer issues (such as gaps in the polysilicon) resulting from fitting the polysilicon within the space between fin structures.

FIG.1Jillustrates the workpiece from a perspective view in which the dummy gate layer118and hard mask layers120,122have been patterned into a dummy gate structure. For example, the dummy gate layer118and hard mask layers120,122may be deposited in a uniform manner and then patterned using a photolithographic process. The patterning process exposes the fin structures104, the sacrificial material110, the first dielectric layer112, and the second dielectric layer116in regions other than where the dummy gate is formed (and ultimately where the real gate where be formed).

FIG.1Killustrates the formation of a sidewall spacer124on sidewalls of the dummy gate118. The sidewall spacer124may be a dielectric material. After the sidewall spacer124is formed, an etching process may be applied to remove portions of the fin structures104where source/drain regions are to be formed. This etching process may be done in accordance with photolithographic processes so that the appropriate portions of the workpiece are etched.

FIG.1Lillustrates a lateral removal process such as a lateral etching process in which a portion of the sacrificial material110is removed to leave a void110aunderneath the sidewall spacer124. The lateral etching process may be a unidirectional etching process such as a wet etching process. The wet etching process may use an acid-based etchant such as: sulfuric acid (H2SO4), perchloric acid (HClO4), hydroiodic acid (HI), hydrobromic acid (HBr), nitric acide (HNO3), hydrochloric acid (HCl), acetic acid (CH3COOH), citric acid (C6H8O7), potassium periodate (KIO4), tartaric acid (C4H6O6), benzoic acid (C6H5COOH), tetrafluoroboric acid (HBF4), carbonic acid (H2CO3), hydrogen cyanide (HCN), nitrous acid (HNO2), hydrofluoric acid (HF), or phosphoric acid (H3PO4). In some examples, an alkaline-based etchant may be used. Such etchants may include but are not limited to ammonium hydroxide (NH4OH) and potassium hydroxide (KOH).

In some examples, the void110amay have a depth that substantially matches the thickness of the sidewall spacer124. In some examples, the depth of the void110amay be greater than the thickness of the sidewall spacer124. In some examples, the depth of the void110amay be less than the thickness of the sidewall spacer. In some examples, the depth of the void110amay be within a range of about 4-10 nanometers. In some examples, the depth of the void110amay be within a range of about 5-15 nanometers.

FIG.1Millustrates the formation of a lower sidewall spacer126within the void110a. The lower sidewall spacer126will ultimately be disposed against the gate structure between the fin structures104. Thus, the top surface of the lower sidewall spacer126corresponds to and is thus on a same level as the top surface of the fin structures104. The lower sidewall spacer126may be a low-k dielectric layer such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN). In some examples, the lower sidewall spacer126may be a different material than the sidewall spacer124. The thickness of the lower sidewall spacer126may be similar to the depth of the void110a. The thickness of the lower sidewall spacer126may be within a range of about 4-10 nanometers.

To form the lower sidewall spacer126, the spacer material may be deposited onto the workpiece and then etched back. Specifically, a selective etching process may be designed such that it removes the lower sidewall spacer material directionally and does not substantially affect the other exposed portions of the workpiece. The portions of the lower sidewall structure126underneath the sidewall spacer124will thus be protected from the directional etching process.

FIG.1Nillustrates the formation of source/drain regions128within the spaces created by the etching process shown inFIG.1L. The source/drain regions128may be formed using an epitaxial growth process to form doped regions that will serve as the active regions of transistor devices.

FIG.1Oillustrates a process for forming an ILD layer130on the workpiece. The ILD layer is a dielectric material that isolates different components of an integrated circuit from each other. After the ILD layer130is deposited, a CMP process is performed to planarize the top surface of the workpiece. The CMP process may be applied so as to remove the hard mask layers120,122and expose the top surface of the dummy gate layer118.FIG.1Pillustrates the workpiece after the CMP process and along the dummy gate layer.

FIG.1Qillustrates a removal process in which the dummy gate material is removed. Although not shown in this view, the sidewall spacer124remains in place while the dummy gate structure118is removed. The dummy gate structure may be removed using an etching process. The etching process may be a unidirectional process such as a wet etching process that removes the dummy gate material118without substantially affecting the other materials.

FIG.1Rillustrates a removal process in which the sacrificial material is removed. The sacrificial material110may also be removed using a unidirectional etching process such as a wet etching process. The wet etching process may be selective so as to remove the sacrificial material110while leaving the fin structures104, first dielectric material112, and second dielectric material116substantially intact. By removing the sacrificial material110, the space between the fin structures104is exposed and thus allows for deposition of the metal gate.

FIG.1Sillustrates deposition of a high-k dielectric layer132over the fin structures. In some examples, an interfacial layer (not shown) may be deposited on the fin structures104before the high-k dielectric layer is deposited. The high-k dielectric layer may include, for example, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide. Other materials may be used as well. For example, other materials with a dielectric constant greater than 7 may be used.

FIG.1Tillustrates deposition of a real gate134that replaces the dummy gate. The real gate134may include a conductive material such as a metal material. The metal material is deposited to surround the sides of the fin structures104and thus form a finFET device. In some examples, the real gate134may include a workfunction layer (not shown). The workfunction layer may be a workfunction metal. Such metal is designed to metal gates the desired properties for ideal functionality. Various examples of a p-type workfunction metal may include, but are not limited to, tungsten carbon nitride (WCN), tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten sulfur nitride (WSN), tungsten (W), cobalt (Co), molybdenum (Mo), etc. Various examples of n-type workfunction metals include, but are not limited to, aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum silicon carbide (TiAlSiC), tantalum aluminum silicon carbide (TaAlSiC), and hafnium carbide (HfC). Using the techniques described herein, higher fin structures104are achievable as well as reduced scaling.

FIG.2is a diagram showing a finFET device along a gate spacer. Using principles described herein, the sidewall spacer of the gate has two components. Specifically, the sidewall spacer includes the upper portion spacer124that is on the upper portion of the gate and a lower portion spacer126that is on the lower portion of the gate. The top of the lower spacer126corresponds with the top surface of the fin structures104. In other words, the top surface of the fin structures104are coplanar with the top surface of the lower portion spacer126. Thus, the bottom surface of the upper portion spacer124is also coplanar with the top surface of the fin structures104. Furthermore, in the spaces between clusters of fins, the bottom of the upper spacer124directly contacts the dielectric layer116as well as portions of the dielectric layer112. The first dielectric layer112, the oxide layer114, and the second dielectric layer116form a dielectric stack.

FIG.3is a diagram showing an illustrative finFET device along a fin structure. As can be seen, the gate device134includes a sidewall spacer that has an upper portion124and a lower portion126. Both the upper sidewall spacer124and the lower sidewall spacer isolate the gate device from the source/drain regions128.

FIG.4is a flowchart showing an illustrative method400for forming a finFET structure with improved pitch scaling. According to the present example, the method400includes a process402for forming a first set of fin structures (e.g.,104) on a substrate (e.g.,102). The semiconductor substrate may be part of a silicon wafer. Other semiconductor materials are contemplated. The substrate may include an elementary (single element) semiconductor, such as silicon, germanium, and/or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The fin structures may be formed using a patterning process. For example, a hard mask layer and a photoresist layer may be deposited onto the substrate. The photoresist may then be exposed to a light source through a photomask. The photoresist may then be developed such that the portions of the photoresist remain while other portions are removed. The pattern within the developed photomask is then transferred to the hard mask layer, which is then transferred to the substrate through an etching process. The fin structures comprise elongated fin-like structures that run parallel to each other.

The method400further includes a process404for forming a sacrificial material (e.g.,110) between fin structures within the first set of fin structures. The sacrificial material may be, for example, silicon nitride (SiN) or silicon germanium (SiGe). Such materials are easier to fit within the spaces between fin structures. In some examples, the sacrificial material is selectively deposited over the fin structures so as to leave the areas where there are no fin structures exposed. In some examples, however, the sacrificial material may be formed over those areas as well and then removed using a directional etching process such as a dry etching process. Such processes may be similar to spacer etching processes.

The method400further includes a process406for forming a dummy gate (e.g.,118) with a planar bottom surface over the fin structures and the sacrificial material. The dummy gate layer may be formed along with two hard mask layers (e.g.,120,122). The first hard mask layer may be a silicon nitride layer and the second hard mask layer may be an oxide layer. The dummy gate layer is formed along a planar surface. In other words, the bottom surface of the dummy gate layer directly contacts a planar line that includes top surfaces of the fin structures and the sacrificial material. The dummy gate layer may be a polysilicon layer. Because the polysilicon dummy gate layer is deposited onto a planar surface, there are fewer issues (such as gaps in the polysilicon) resulting from fitting the polysilicon within the space between fin structures.

The method400further includes a process408for forming sidewall structures (e.g.,124) on the dummy gate. The sidewall structures may be a dielectric material. After the sidewall structures are formed, an etching process may be applied to remove portions of the fin structures where source/drain regions are to be formed. This etching process may be done in accordance with photolithographic processes so that the appropriate portions of the workpiece are etched.

The method400further includes a process410for laterally etching the sacrificial material underneath the sidewall structures. The lateral removal process removes a portion of the sacrificial material to leave a void underneath the sidewall spacer. The lateral etching process may be a unidirectional etching process such as a wet etching process. In some examples, the depth of the void may be greater than the thickness of the sidewall structures. In some examples, the depth of the void may be less than the thickness of the sidewall spacer. In some examples, the depth of the void may be within a range of about 4-10 nanometers. In some examples, the depth of the void may be within a range of about 5-15 nanometers.

The method400further includes a process412for depositing a lower sidewall structure (e.g.,126) where the sacrificial material was removed. The lower sidewall spacer will ultimately be disposed against the gate structure between the fin structures104. Thus, the top surface of the lower sidewall spacer corresponds to and is thus on a same level as the top surface of the fin structures. The lower sidewall spacer may be a low-k dielectric layer such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN). In some examples, the lower sidewall spacer may be a different material than the sidewall spacer. The thickness of the lower sidewall spacer may be similar to the depth of the void. The thickness of the lower sidewall spacer may be within a range of about 4-10 nanometers. To form the lower sidewall spacer, the spacer material may be deposited onto the workpiece and then etched back. Specifically, a selective etching process may be designed such that it removes the lower sidewall spacer material directionally and does not substantially affect the other exposed portions of the workpiece. The portions of the lower sidewall structure underneath the sidewall spacer will thus be protected from the directional etching process.

The method400further includes a process414for removing the dummy gate. The sidewall structures remain in place while the dummy gate structure is removed. The dummy gate structure may be removed using an etching process. The etching process may be a unidirectional process such as a wet etching process that removes the dummy gate material without substantially affecting the other materials.

The method400further includes a process416for removing the sacrificial material. The sacrificial material may also be removed using a unidirectional etching process such as a wet etching process. The wet etching process may be selective so as to remove the sacrificial material while leaving the fin structures substantially intact. By removing the sacrificial material, the space between the fin structures is exposed and thus allows for deposition of the metal gate.

The method400further includes a process418for forming a real gate (e.g.,134) over the fin structures. Forming the real gate may include forming a high-k dielectric layer (e.g.,132). In some examples, an interfacial layer may be deposited on the fin structures before the high-k dielectric layer is deposited. The high-k dielectric layer may include, for example, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide. Other materials may be used as well. The real gate may include a conductive material such as a metal material. The metal material is deposited to surround the sides of the fin structures and thus form a finFET device. In some examples, the real gate may include a workfunction layer (not shown). The workfunction layer may be a workfunction metal. Such metal is designed to metal gates the desired properties for ideal functionality. Various examples of a p-type workfunction metal may include, but are not limited to, tungsten carbon nitride (WCN), tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten sulfur nitride (WSN), tungsten (W), cobalt (Co), molybdenum (Mo), etc. Various examples of n-type workfunction metals include, but are not limited to, aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum silicon carbide (TiAlSiC), tantalum aluminum silicon carbide (TaAlSiC), and hafnium carbide (HfC). Using the techniques described herein, higher fin structures are achievable as well as reduced scaling.

According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, a dielectric stack positioned between the first set of fin structures and the second set of fin structures, the dielectric stack having a top surface at substantially a same level as top surfaces of the first and second sets of fin structures, the dielectric stack comprising: a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.

According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, a dielectric stack positioned between the first set of fin structures and the second set of fin structures, the dielectric stack having a top surface at substantially a same level as top surfaces of the first and second sets of fin structures, a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack. The gate structure includes a first dielectric sidewall structure on sidewalls of a lower portion of the gate structure, and a second dielectric sidewall structure on sidewalls of an upper portion of the gate structure.

According to one example, a method includes forming a first set of fin structures on a substrate, forming a sacrificial material between fin structures within the first set of fin structures, forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material, forming sidewall structures on the dummy gate, laterally etching the sacrificial material underneath the sidewall structures, depositing a lower sidewall structure where the sacrificial material was removed, removing the dummy gate, removing the sacrificial material, and forming a real gate over the fin structures.