Partial block erase for a three dimensional (3D) memory

A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.

FIELD OF THE DISCLOSURE

The present disclosure is generally related to a partial block erase for a three dimensional (3D) memory.

BACKGROUND

Non-volatile data storage devices, such as embedded memory devices (e.g., embedded MultiMedia Card (eMMC) devices) and removable memory devices (e.g., removable universal serial bus (USB) flash memory devices and other removable storage cards), have allowed for increased portability of data and software applications. Users of non-volatile data storage devices increasingly rely on the non-volatile storage devices to store and provide rapid access to a large amount of data.

In non-volatile data storage devices having a three dimensional (3D) memory, erasing a block of the 3D memory may include time consuming and power expending processes. Additionally, when erasing the block, each wordline of the block is erased regardless of whether the wordline is already in an erased state and regardless of whether the wordline is approaching an end-of-life (e.g., failure) condition.

SUMMARY

Techniques are disclosed to perform a partial block erase for a three dimensional (3D) memory. For example, a data storage device may include a 3D memory having one or more blocks. Each block may include a plurality of sub-blocks that are erasable independently of the other sub-blocks of the block. For example, the block can include one or more switches to electrically isolate sub-blocks during an erase operation.

By performing an erase operation on a sub-block, rather than on an entire block, of the 3D memory, the erase operation may be performed more quickly and less power may be used. Additionally, by being able to perform erase operations on sub-blocks of the 3D memory, wordlines that have been identified as nearing an end-of-life condition may be selectively isolated from an erase operation that is performed on the rest of the block. By selectively isolating the wordlines that have been identified, a life of the wordlines may be extended.

DETAILED DESCRIPTION

Particular embodiments of the present disclosure are described with reference to the drawings. In the description, common features are designated by common reference numbers throughout the drawings.

FIG. 1is a block diagram of a particular illustrative embodiment of a system100including a data storage device102and a host device130. The system100may be configured to enable the data storage device102to perform a partial block erase on a three dimensional (3D) memory.

The data storage device102may be embedded within the host device130, such as in accordance with an embedded MultiMedia Card (eMMC®) (trademark of Joint Electron Devices Engineering Council (JEDEC) Solid State Technology Association, Arlington, Va.) configuration. Alternatively, the data storage device102may be removable from (i.e., “removably” coupled to) the host device130. For example, the data storage device102may be removably coupled to the host device130in accordance with a removable universal serial bus (USB) configuration.

The data storage device102may be coupled to the host device130via a communication path110, such as a wired communication path and/or a wireless communication path. For example, the data storage device102may include an interface108(e.g., a host interface) that enables communication (via the communication path110) between the data storage device102and the host device130, such as when the interface108is coupled to the host device130.

The host device130may include a processor and a memory. The memory may be configured to store data and/or instructions that may be executable by the processor. The memory may be a single memory or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The host device130may issue one or more commands to the data storage device102, such as one or more requests to read data from or write data to a memory104of the data storage device102. For example, the host device130may send data, such as user data132to be written to the memory104of the data storage device102.

The data storage device102includes a controller120coupled to the memory104, such as a non-volatile memory (e.g., a flash memory). The controller120may be coupled to the memory104via a bus106, an interface, another structure, or a combination thereof. The memory104has a three dimensional (3D) memory configuration, as described further herein. The memory104may store data, such as the user data132.

The memory104may be included on a memory die103that is separate from the controller120and coupled to the controller120(e.g., via the bus106). However, in other implementations, the memory104and the controller120may be included on a common die. The memory104may include multiple blocks that each includes a plurality of wordlines. The wordlines may be arranged in one or more layers. Each block may also include multiple “strings” of storage elements where the strings extend through the one or more layers, such as through each wordline. For example, the memory104may include a representative string150, such as a vertical string (e.g., a NAND string). The string150may include a first portion152and a second portion156. The string150may also include (or be coupled to) a switch154that may be configurable to couple or decouple the first portion152and the second portion156. The switch154may be positioned (physically and/or electrically) between the first portion152and the second portion156, such as between a first storage element of the first portion512and a second storage element of the second portion156. For example, the switch154is configurable to selectively isolate the first portion152from the second portion156. In addition, while two portions152,156are shown inFIG. 1and a single switch154is also shown, it should be understood that the string150may include more than two portions and more than one switch. Thus, the string150includes multiple portions that are selectively coupled or decoupled based on the switch154. In some embodiments, the switch154may include a transistor, such as a metal-oxide semiconductor (MOS) transistor.

The memory die103may further include read circuitry140, write circuitry142, and erase circuitry144. Although illustrated as separate components, the read circuitry140, the write circuitry142, the erase circuitry144, and/or a combination thereof, may be included in a single component of the memory die103. The read circuitry140and the write circuitry142may be configured to enable operations of reading data from the memory104and writing data to the memory104, respectively.

The erase circuitry144may be configured to enable erase operations to be performed on the memory104. For example, the erase circuitry144may be configured to enable block erase operations and/or partial block erase operations (e.g., sub-block erase operations), as described herein. To perform an erase operation, the erase circuitry144may send a control signal134and an erase signal136to the memory104. The control signal134may cause one or more switches included in the memory104to operate (e.g., open and/or close). For example, the control signal134may cause the switch154to be in a closed position and couple the first portion152of the string150to the second portion156of the string150. The erase signal136may cause one or more erase voltages to be applied to at least part of the memory104and to erase data stored in the memory104. The data that is erased responsive to the erase signal136may depend on a configuration of the switch154and on portion of the memory104to which the erase voltage is applied.

To illustrate, during a first type of erase operation (e.g., a partial block erase operation), the first portion152may be isolated from the second portion156by the switch154being in an open state based on the control signal134. With the first type of erase operation being performed, an erase voltage may be applied to the second portion156of the string150based on the erase signal136. When the erase voltage is applied to the second portion156and the switch154is in the open state, data corresponding to the second portion156may be erased while data is maintained at the first portion152of the string150. During a second type of erase operation, the first portion152may be coupled to the second portion156by the switch154being in a closed state. During a second erase operation corresponding to the second type of erase operation (e.g., a full block erase operation), the first portion152and the second portion156may be biased together at substantially the same voltage level. Although the first type of erase operation (e.g., the partial block erase operation) and the second type of erase operation (e.g., a full block erase operation) have been described with reference to a single string150of a block, it is understood that during each of the first type of erase operation and the second type of erase operation, each string of the block may be configured as described with reference to the string150.

The memory104may also include one or more current sensors146. The current sensors146may be coupled to the memory104. For example, each current sensor (of the current sensors146) may be coupled to a different wordline of a portion of the memory104that is being erased. Each current sensor may determine an amount of current through a corresponding wordline when an erase operation is performed that is associated with the corresponding wordline. For example, during a particular erase operation to erase a particular wordline, a particular current sensor, such as one of the current sensors146that corresponds to the particular wordline may determine an amount of current through the particular wordline. Based on the particular amount of current, an indication of the amount of current, such as the current sensor data126, may be generated and provided to the controller120. The current sensor data126may enable the controller120to determine a health status of the particular wordline, as described further herein.

An illustrative example of the string150is illustrated and generally designated180. The example180depicts a cross-sectional elevation view of the string150having a vertical conducive channel structure extending through holes formed in a stack of wordlines to form a vertical column of storage elements. An example of a perspective view of a three dimensional (3D) memory is described with reference toFIGS. 5 and 6. The stack of wordlines may be associated with one or more physical layers (e.g., one or more physical levels).

The string150may be formed on a substrate182, such as a silicon (Si) substrate. The string150may include a plurality of storage elements. Each storage element (e.g., a memory cell) of the string150may include a bit cell, such as a representative bit cell174. The bit cell174may include (or be coupled to) a wordline, a portion of a charge trap, and a portion of a conductive channel. Each storage element (e.g., memory cell or bit cell) of the string150may be configured to store a data value, e.g., a bit value, such as “1” and “0,” or a multi-bit value, such as in a two bit-per-cell (2-BPC) implementation, a three bit-per-cell (3-BPC) implementation, or another BPC implementation.

The string150may include the first portion152and the second portion156. The first portion152may be associated with and/or correspond to a first set of storage elements (e.g., one or more storage elements) and the second portion156may be associated with and/or correspond to a second set of storage elements (e.g., one or more storage elements). The first portion152(e.g., the first set of wordlines) may correspond to a first sub-block of a block of the memory104that includes the string150. The second portion156(e.g., the second set of wordlines) may correspond to a second sub-block of a block of the memory104that includes the string150. The first set of storage elements and the second set of storage elements include the same number of storage elements or a different number of storage elements. In some embodiments, the first set of storage elements may include a single storage element, as an illustrative, non-limiting example.

The string150may include a conductive channel186(e.g., a vertical channel). The conductive channel186may be coupled the plurality of storage elements, such as the first set of storage elements and to the second set of storage elements. Each storage element of the plurality of storage elements may correspond to a different wordline. The first set of storage elements maybe included in a first group of (one or more) physical layers (e.g., a first physical level) and may correspond to a first set of wordlines including a representative first wordline188. A first charge trap layer170may be positioned between the first set of wordlines and the conductive channel186(e.g., forming a sheath around the conductive channel186). Although the first set of storage elements is illustrated as being above the substrate182with no intervening storage elements, another one or more other sets of storage elements may be between the substrate182and the first set of storage elements (e.g., another group of physical layers may be between the substrate182and the first group of physical layers).

The second group of storage elements may be included in a second group of (one or more) physical layers (e.g., a second physical level) and may correspond to a second set of wordlines including a representative second wordline198. A second charge trap layer176may be positioned between the second set of wordlines and the second conductive channel196. Although the first charge trap layer170and the second charge trap layer176are illustrate as separate layers, in other embodiments, the first charge trap layer170and the second charge trap layer176may be a single layer.

The switch154may be coupled to the string150. For example, the switch may be coupled to the conductive channel186. The switch154may be configurable to couple or decouple (e.g., electrically connect or electrically isolate) the first portion152of the string150to the second portion156of the string150. To illustrate, the switch154may couple or may decouple the first portion152and the second portion156based on the control signal134.

The string150(e.g., the conductive channel186) may be coupled to a plurality of terminals. For example, the plurality of terminals include a first bias terminal162, a second bias terminal164, a third bias terminal166, and a fourth bias terminal168. In the illustrated embodiment, the first bias terminal162is located at a first end of the first portion152and the second bias terminal164is located at a second end of the first portion152. The third bias terminal166is located a first end of the second portion156and the fourth bias terminal168is located at a second end of the second portion156.

The plurality of terminals may be configured to enable an erase voltage to be applied to at least a part of the string150(e.g., at least part of the conductive channel186) based on an erase signal, such as the erase signal136. For example, when the first portion152is isolated from the second portion156, a first erase operation may be performed on the second portion156of the string150to erase data at the second portion156while data is maintained at the first portion152of the string150. To erase the data at the second portion156, an erase voltage may be applied to the second portion156of the string150(e.g., to the third bias terminal166and/or the fourth bias terminal168) and a particular voltage may be applied to each wordline of the second set of wordlines (e.g., the second sub-block). To illustrate, to erase the storage elements corresponding to the second portion156of the string150, the particular voltage (applied to the second set of wordlines) may be associated with a first potential and the erase voltage may be associated with a second potential that is opposite of the first potential. For example, the first potential may be a positive voltage and the second potential may be a negative voltage or zero volts (e.g., a ground potential). A difference in the first potential and the second potential may erase a storage element (e.g., drain a charge that is stored at a charge trap of a bit cell).

The controller120is coupled to the memory104and is configured to determine whether to enable the switch154to couple the first portion152and the second portion156or to disable the switch154to decouple the first portion152from the second portion156. For example, the controller120may include hardware and/or software, such as a processor (not shown) to execute firmware to determine whether to enable or disable the switch154. The controller120may initiate different types of erase operations by sending a command172(e.g., an erase command) to the memory104. In a first type of an erase operation, the first portion152is decoupled from the second portion156while in other types of erase operations the first portion152is coupled to the second portion156(so data within both the first portion152and the second portion156may be erased). Thus, the controller120may selectively erase one or more particular portions of the string150.

The controller120may include a random access memory (RAM)122. The RAM122, such as a volatile memory, may be configured to store a tracking table124. The tracking table124may store current sensor data, such as the current sensor data126, received from the one or more current sensors146. The controller120may collect current data (e.g., such as the current sensor data126indicating an amount of current sensed through a particular wordline during an erase operation), corresponding to the particular wordline, for a period of time. The current data for the particular wordline over the period of time may enable the controller120to determine health data associated with the particular wordline. The health data may indicate if and when the particular wordline is nearing an end-of-life (e.g., a failure). For example, the controller120may determine that the particular wordline is nearing the end-of-life based on an increase in the amount of current (flowing through the wordline during erase operations) over time. If the particular wordline fails, the controller120may have to decommission (e.g., no longer use) a particular block that includes the particular wordline. When the controller120identifies the particular wordline as nearing the end-of-life, the controller120may send the command172to the memory104to configure the memory104(e.g., one or more switches) to isolate the particular wordline during erase operations performed on the particular block. By avoiding performing erase operations on the wordline (e.g., a sub-block of the particular block that includes the particular wordline), a life of the particular wordline may be extended and endurance (e.g., usability) of the particular block may be increased.

The controller120may be configured to receive data and commands (e.g., instructions) from the host device130and may access the memory104based on the received commands. The controller120may send one or more write requests (e.g., a write command128) to the memory104to store the data to a specified address of the memory104. The write request may specify a physical address of a portion of the memory104(e.g., a physical address of a word line of the memory104) that is to store the data. The controller120may be configured to send a read request to the memory104to access data from a specified address of the memory104. To illustrate, the controller120may send a read request (e.g., a read command126) to access the data stored in the memory104. The read request may specify the physical address of a portion of the memory104(e.g., a physical address of a word line storing the data).

During operation, the memory die103(e.g., the erase circuitry144) of the data storage device102may receive the command172from the controller120. The command172may instruct the erase circuitry144to configure a block of the memory104to erase the second sub-block (e.g., the second set of wordlines) corresponding to the second portion156of the string150.

Based on the command172, the erase circuitry144may send the control signal134to the memory104to cause the switch154to decouple the first portion152and the second portion156. When the first portion152and the second portion156are decoupled, the erase circuitry144may send the erase signal136to the memory104. The erase signal136may cause an erase voltage to be applied the second portion156of the string150, such as to the second sub-block. Based on the erase voltage applied to the second portion156, data stored at the second set of storage elements corresponding to the second portion156(e.g., the second sub-block) may be erased, while data is maintained at the first set of storage elements corresponding to the first portion152(e.g., the first sub-block).

Although the tracking table124is illustrated as a single table, the tracking table124may include multiple tables. Additionally or alternatively, although the tracking table124is illustrated as being stored at the RAM122included in the controller120, in other implementations at least a portion of the tracking table124may be stored at the memory104, at a memory of the host device130, at another memory that is coupled to the controller120, or a combination thereof. Additionally or alternatively, the controller120may include a single memory component, such as the RAM122, or may include multiple distinct memory components and/or multiple different types of memory components.

Additionally, the data storage device102may include an error correction code (ECC) engine (not shown). The ECC engine may be configured to receive data, such as the data132, and to generate one or more error correction code (ECC) codewords (e.g., including a data portion and a parity portion) based on the data. For example, the ECC engine may include an encoder configured to encode the data using an ECC encoding technique. The ECC engine may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, a turbo encoder, an encoder configured to encode the data according to one or more other ECC techniques, or a combination thereof, as illustrative, non-limiting examples.

The ECC engine may include a decoder configured to decode data read from the memory104to detect and correct bit errors that may be present in the data. For example, the ECC engine may correct a number of bit errors up to an error correction capability of an ECC technique used by the ECC engine. A number of errors identified by the ECC engine may be tracked by the controller120, such as by the ECC engine. For example, based on the number of errors, the ECC engine may determine a bit error rate (BER) associated with one or more blocks of the memory104that may be used to determine when one or more portion of the memory104may be approaching an end-of-life condition.

By selectively isolating the first portion152and the second portion156using the switch154, a partial block erase operation (e.g., a sub-block erase operation) may be performed on a block of a 3D memory that includes the string150. The partial block erase operation may advantageously be performed more quickly and use less power than a full block erase operation. Additionally, by being able to perform the partial block erase operation, wordlines (of the block) that have been identified as nearing an end-of-life may be selectively isolated during erase operations to increase a life of the wordlines and a usefulness of blocks that include the wordlines.

Referring toFIG. 2, a first example of a memory is illustrated and generally designated200. The memory may include or correspond to the memory104ofFIG. 1. The example200depicts a cross-sectional elevation view of the string150.

The string150may include a conductive channel206. The conductive channel206may include or correspond to the conductive channel186ofFIG. 1. It is noted that one or more charge trap layers of the string150are not illustrated for clarity of illustration. The conductive channel206may include the first portion152, the second portion156, and a third portion258. The first portion152may correspond to a first set of storage elements (e.g., one or more storage elements), the second portion156may correspond to a second set of storage elements (e.g., one or more storage elements), and the third portion258may correspond to a third set of storage elements (e.g., one or more storage elements). Although the string150is illustrated as including three portions, the string150may include more than three portions or fewer than three portions.

The string150may also include (or be coupled to) the switch154(e.g., a first switch) and a second switch204. The first switch154may be configurable to couple or decouple the first portion152and the second portion156. The second switch204may be configurable to couple or decouple the second portion156and the third portion258. For example, the first switch154and/or the second switch204may be selectively configured based on one or more control signals, such as the control signal134ofFIG. 1, received from the erase circuitry144.

The string150may be coupled to one or more terminals (e.g., one or more bias terminals). For example, the one or more terminals may include the first bias terminal162, the second bias terminal164, the third bias terminal166, the fourth bias terminal168, a fifth bias terminal270, and a sixth bias terminal272. To illustrate, the first bias terminal162may be located at a first end of the first portion152and the second bias terminal164may be located at a second end of the first portion152. The third bias terminal166may be located at a first end of the second portion156and the fourth bias terminal168may be located at a second end of the second portion156. The fifth bias terminal270may be located at a first end of the third portion258and the sixth bias terminal272may be located at a second end of the third portion258.

The first switch154and/or the second switch204may be selectively activated and/or deactivated to configure the string150for one or more erase operations. For example, the first switch154and the second switch204may couple and decouple one or more portions of the string150to configure the string150for a block erase operation or for sub-block erase operations.

To illustrate, prior to and during a first erase operation (corresponding to a first erase signal), the first switch154may be configured to decouple the first portion152and the second portion156and the second switch204may be configured to decouple the second portion156and the third portion258. Accordingly, each portion of the string150may be isolated from the other portions of the string150. The first erase operation may then be performed to erase a single sub-block, such as a single sub-block corresponding to the first portion152, a single sub-block corresponding to the second portion156, or a single sub-block corresponding to the third portion258. To erase the sub-block corresponding to the first portion152, a bias voltage (e.g., an erase voltage) may be applied to first bias terminal162and/or to the second bias terminal164, but not to the third, fourth, fifth and sixth bias terminals166-168,270-272. To erase the sub-block corresponding to the second portion156, a bias voltage (e.g., an erase voltage) may be applied to third bias terminal166and/or to the fourth bias terminal168, but not to the first, second, fifth and sixth bias terminals162-164,270-272. To erase the sub-block corresponding to the third portion258, a bias voltage (e.g., an erase voltage) may be applied to fifth bias terminal270and/or to the sixth bias terminal272, but not to the first, second, third, and fourth bias terminals162-168. It is also noted that a bias voltage (e.g., an erase voltage) may be concurrently applied to the first portion152and the third portion258, but not applied to the second portion156.

Prior to and during a second erase operation (corresponding to a second erase signal), the first switch154may be configured to couple the first portion152and the second portion156and the second switch204may be configured to couple the second portion156and the third portion258. Accordingly, each portion of the string150may be coupled together. The second erase operation may then be performed to erase a block, such as a block corresponding to the string150(including each of the sub-blocks corresponding to the first portion152, the second portion156, and the third portion258). To erase the block corresponding to the string150, a bias voltage (e.g., an erase voltage) may be applied to one or more of the bias terminals162-168,270-272.

Prior to and during a third erase operation (corresponding to a third erase signal), the second switch204may be configured to couple the second portion156and the third portion258. Additionally, prior to and during the third erase operation, the first switch154may be configured to decouple the first portion152and the second portion156. The third erase operation may then be performed to erase multiple sub-blocks that include a sub-block corresponding to the second portion156and a sub-block corresponding to the third portion258. To erase the multiple sub-blocks, a bias voltage (e.g., an erase voltage) may be applied to one or more of the third bias terminal166, the fourth bias terminal168, the fifth bias terminal270, and the sixth bias terminal272. It is also noted that when the second switch204is configured to couple the second portion156and the third portion258and the first switch is configured to decouple the first portion152and the second portion156, an erase operation may be performed to erase a single sub-block corresponding to the first portion152without erasing data corresponding to the sub-blocks that correspond to the second portion156and the third portion258.

Prior to and during a fourth erase operation (corresponding to a fourth erase signal), the second switch204may be configured to decouple the second portion156and the third portion258. Additionally, prior to and during the fourth erase operation, the first switch154may be configured to couple the first portion152and the second portion156. The fourth erase operation may then be performed to erase multiple sub-blocks that include a sub-block corresponding to the first portion152and a sub-block corresponding to the second portion156. To erase the multiple sub-blocks, a bias voltage (e.g., an erase voltage) may be applied to one or more of the first bias terminal162, the second bias terminal164, third bias terminal166, and the fourth bias terminal168. It is also noted that when the second switch204is configured to decouple the second portion156and the third portion258and the first switch is configured to couple the first portion152and the second portion156, an erase operation may be performed to erase a single sub-block corresponding to the third portion258without erasing data corresponding to the sub-blocks that correspond to the first portion152and the second portion156.

By selectively configuring the first switch154and/or the second switch204, an erase operation may be performed on less than an entire block (e.g., on one or more sub-blocks). By performing an erase operation on a sub-block of the 3D memory, rather than on an entire block, the erase operation may be performed more quickly and less power may be used.

Referring toFIG. 3, a second example of a memory is illustrated and generally designated300. The memory may include or correspond to the memory104ofFIG. 1. The example300depicts a cross-sectional elevation view of the string150.

The string150may include multiple sets of storage elements. For example, the string150may include a first set of storage elements352, a second set of storage elements356, and a third set of storage elements358. The first set of storage elements352may correspond to a first portion of string150, such as the first portion152ofFIG. 1. The second set of storage elements356may correspond to a second portion of string150, such as the second portion156ofFIG. 1. The third set of storage elements358may correspond to a third portion of string150, such as the third portion258ofFIG. 2. Each set of storage elements352,356,358may be coupled to a conductive channel of the string150, such as the conductive channel186ofFIG. 1. AlthoughFIG. 3illustrates three sets of storage elements352,356,358, the multiple sets of storage elements may include two sets of storage elements or more than three sets of storage elements.

The string150may be included in a block of the memory. Each of the multiple sets of storage elements352,356,358may correspond to a different sub-block of the block of the memory. Each of the sub-blocks may be erased independent of the other sub-blocks included in the block. Additionally, multiple sub-blocks may be erased during the same erase operation. For example, all of the sub-blocks or less than all of the sub-blocks may be erased during a single erase operation.

Each set of storage elements352,356,358may include multiple storage elements that are each coupled to a corresponding wordline. For example, a representative storage element388may be coupled to a wordline336. To illustrate, the storage element388may include or correspond to the bit cell174ofFIG. 1. Each wordline may be coupled to a corresponding current sensor. For example, each wordline may be coupled to a different current sensor. To illustrate, the wordline336may be coupled to a current sensor346. Each current sensor may be configured to generate current sensor data, such as the current sensor data126ofFIG. 1, during an erase operation performed on a corresponding wordline. The current sensor data may be provided to a controller, such as the controller120ofFIG. 1, and/or a memory, such as the memory104or the RAM122ofFIG. 1.

The multiple sets of storage elements352,356,358may be selectively coupled together by one or more switches, such as a first switch396and a second switch398. The first switch396may include or correspond to the switch154ofFIG. 1. The second switch398may include or correspond to the second switch204ofFIG. 2. The first switch396and/or the second switch398may be configured to selectively couple one or more sets of storage element based on one or more control signals, such as the control signal134ofFIG. 1.

The multiple sets of storage elements352,356,358may be coupled to a bit line304and to a source line306. For example, the multiple sets of storage elements352,356,358may be coupled to the bit line304through a first select gate322(e.g., a first driver), and the multiple sets of storage elements352,356,358may be coupled to the source line306through a second select gate324(e.g., a second driver). To illustrate, the first select gate322may be between the bit line304and the first set of storage elements352. The second select gate324may be between the third set of storage elements358and the source line306.

One or more terminals362-372may be coupled to the string150. The one or more terminals may include a first terminal362, a second terminal364, a third terminal366, a fourth terminal368, a fifth terminal370, and a sixth terminal372. The first terminal362may include or correspond to the first bias terminal162ofFIG. 1, the second terminal364may include or correspond to the second bias terminal164ofFIG. 1, the third terminal366may include or correspond to the third bias terminal166ofFIG. 1, the fourth terminal368may include or correspond to the fourth bias terminal168ofFIG. 1, the fifth terminal370may include or correspond to the fifth bias terminal270ofFIG. 2, and the sixth terminal372may include or correspond to the sixth bias terminal272ofFIG. 2. Although the string150is illustrated as being coupled to six terminals, the string150may be coupled to more than six terminals or fewer than six terminals.

Each of the terminals362-372may be coupled to erase circuitry344. The erase circuitry344may include or correspond to the erase circuitry144ofFIG. 1. The erase circuitry344may be configured to send one or more erase signals, such as the erase signal136ofFIG. 1, to one or more of the terminals362-372. The one or more erase signals may be used to apply a voltage (e.g., an erase voltage) to one or more terminals during an erase operation. Based on the configuration of the switches396,398, the erase voltage may be selectively applied to one or more portions of the string150. For example, when the switches396,398are in a first configuration (e.g., the first switch396is open and the first set of storage elements352is decoupled from the second set of storage elements356, a first erase signal may be applied to the first terminal362and/or to the second terminal364to erase the first set of storage elements352.

Referring toFIG. 4, an illustrative embodiment of a method400to enable a partial block erase of a three dimensional (3D) memory is shown. For example, the method400may be performed by at a data storage device, such as the data storage device102(e.g., the erase circuitry144) ofFIG. 1.

The method400includes providing a control signal to isolate a first portion of a string of a non-volatile memory from a second portion of the string, at402. The non-volatile memory may be a 3D memory, such as the memory104ofFIG. 1. The non-volatile memory may include at least one block that includes the string, such as the string150. The string may include a first portion and a second portion. The first portion of the string may correspond to a first sub-block of the block and the second portion of the string may correspond to a second sub-block of the block. The control signal, such as the control signal134ofFIG. 1, may be provided to a switch that is configurable to couple or decouple the first portion of the string to the second portion of the string. For example, the switch may include or correspond to the switch154ofFIG. 1.

The method400further includes providing an erase signal to erase the second portion of the string while data is maintained at the first portion of the string, at404. For example, the erase signal may include or correspond to the erase signal136ofFIG. 1.

In some embodiments, providing the first erase signal may include applying a first voltage level on one or more wordlines corresponding to the second portion of the string. Alternatively or additionally, providing the first erase signal may include applying a second voltage level on a portion of a conductive channel of the string. The portion of the conductive channel corresponds to the second portion of the string. The first voltage level may be associated with a first voltage potential and the second voltage level may be associated with a second voltage potential, such that the first voltage potential and the second voltage potential are opposite potentials. To illustrate, the first voltage potential may be a positive voltage potential and the second voltage potential may be a negative voltage potential or a ground potential.

The method400may enable a partial block erase of the non-volatile memory (e.g., a 3D memory) by isolating the first portion of each of the strings in a block from the second portion of each of the strings. Accordingly, during an erase operation corresponding to the erase signal, first data may be maintained at the first portion of the string while second data may be erased from the second portion of the string.

The method400ofFIG. 4may be initiated or controlled by an application-specific integrated circuit (ASIC), a processing unit, such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, a field-programmable gate array (FPGA) device, or any combination thereof. As an example, the method400ofFIG. 4can be initiated or controlled by one or more processors, such as one or more processors included in or coupled to a controller. A controller configured to perform the method400ofFIG. 4may be able to perform a partial block erase (e.g., a sub-block erase) of a 3D memory.

FIG. 5illustrates an embodiment of a 3D memory500in a NAND flash configuration. The 3D memory500may correspond to the memory104ofFIG. 1. The 3D memory500includes multiple physical layers, such as a first set of one or more physical layers501(e.g., a first set of physical levels) and a second set of one or more physical layers503(e.g., a second set of physical levels), that are monolithically formed above a substrate504, such as a silicon substrate. Storage elements (e.g., memory cells), such as a representative memory cell510, are arranged in arrays in the physical layers.

A representative string590may include the representative memory cell510and a conductive channel512. The string590may include or correspond to the string150ofFIG. 1. The representative memory cell510includes a charge trap structure514between a wordline/control gate (WL4)528and the conductive channel512. The charge trap may include or correspond to the first charge trap layer170or the second charge trap layer176ofFIG. 1. Charge may be injected into or drained from the charge trap structure514via biasing of the conductive channel512relative to the wordline528. For example, the charge trap structure514may include silicon nitride and may be separated from the wordline528and the conductive channel512by a gate dielectric, such as a silicon oxide. An amount of charge in the charge trap structure514affects an amount of current through the conductive channel512during a read operation of the memory cell510and indicates one or more bit values that are stored in the memory cell510. The conductive channel512may include or correspond to the conductive channel186ofFIG. 1.

The 3D memory500includes multiple erase blocks, including a first block (block 0)550, a second block (block 1)552, and a third block (block 2)554. Each block550-554includes a “vertical slice” of the physical layers502that includes a stack of wordlines, illustrated as a first wordline (WL0)520, a second wordline (WL1)522, a third wordline (WL2)524, a fourth wordline (WL3)526, a fifth wordline (WL4)528, a sixth wordline (WL5)570, a seventh wordline (WL6)572, an eighth wordline (WL7)574, a ninth wordline (WL8)576, and a tenth wordline (WL9)578. Multiple conductive channels (having a substantially vertical orientation with respect toFIG. 5) extend through the stack of wordlines. Each conductive channel may be associated with a different string, such as a NAND string. Each conductive channel is coupled to a storage element in each wordline520-528,570-578, forming a NAND string of storage elements.FIG. 5illustrates three blocks550-554, ten wordlines520-528,570-578in each block, and three conductive channels in each block for clarity of illustration. However, the 3D memory500may have more than three blocks, more than ten wordlines per block, and more than three conductive channels per block.

Read/write circuitry560is coupled to the conductive channels via multiple conductive lines, illustrated as a first bit line (BL0)530, a second bit line (BL1)532, and a third bit line (BL2)534at a “top” end of the conducive channels (e.g., farther from the substrate504) and a first source line (SL0)540, a second source line (SL1)542, and a third source line (SL2)544) at a “bottom” end of the conductive channels (e.g., nearer to or within the substrate504). The read/write circuitry560is illustrated as coupled to the bit lines530-534via “P” control lines, coupled to the source lines540-744via “M” control lines, and coupled to the wordlines520-528via “N” control lines. Each of P, M, and N may have a positive integer value based on the specific configuration of the 3D memory500. In the illustrative example ofFIG. 5, P=3, M=3, and N=10.

In a particular embodiment, each of the bit lines and each of the source lines may be coupled to the same end (e.g., the top end or the bottom end) of different conductive channels. For example, a particular bit line may be coupled to the top of a conductive channel592and a particular source line may be coupled to the top of the conductive channel512. The bottom of the conductive channel592may be coupled (e.g., electrically coupled) to the bottom of the conductive channel512. Accordingly, the conductive channel592and the conductive channel512may be coupled in series and may be coupled to the particular bit line and the particular source line.

Each of the conductive channels (e.g., each string) may be coupled to one or more corresponding switches, such as representative switches580-584. The representative switch584may be configurable to couple and/or decouple a first portion of the string590(corresponding to the first set of physical layers502) and a second portion of the string590(corresponding to the second set of physical layers503). The switch584may include or correspond to the switch154ofFIG. 1, the switch204ofFIG. 2, and/or the switches396,398ofFIG. 3. Each of the switches may be coupled to erase circuitry586. As illustrated inFIG. 5, only the switch584is depicted as being coupled to the erase circuitry586for clarity of illustration. The erase circuitry586may operate as described with respect to the erase circuitry144ofFIG. 1and/or the erase circuitry344ofFIG. 3.FIG. 5does not illustrate terminals (e.g., bias terminals) coupled to each of the conductive channels for clarity of illustration. It is understood that the 3D memory500may include one or more terminals coupled to each of the conductive channels, as described with reference to the terminals162-186ofFIG. 1, the terminals270-272ofFIG. 2, and/or the terminals362-372ofFIG. 3.

The read/write circuitry560may operate as described with respect to the read circuitry140and/or the write circuitry142ofFIG. 1. For example, data may be stored to storage elements coupled to the wordline528and the read/write circuitry560may read bit values from the storage elements. As another example, the read/write circuitry560may apply selection signals to control lines coupled to the wordlines520-528, the bit lines530-534, and the source lines540-542to cause a programming voltage (e.g., a voltage pulse or series of voltage pulses) to be applied across selected storage element(s) of the selected wordline (e.g., the fourth wordline528).

During a read operation, the controller120may receive a request from a host device, such as the host device130ofFIG. 1. The controller120may cause the read/write circuitry560to read bits from particular storage elements of the 3D memory500by applying appropriate signals to the control lines to cause storage elements of a selected wordline to be sensed. Accordingly, the 3D memory500having multiple conductive channels in a stacked configuration may be configured to read from and write data to one or more storage elements.

During an erase operation, such as a partial block erase operation, a block of the memory500to be erased may be identified. For example, the first block (block 0)550may be identified to have a first portion (e.g., a sub-block) of the first block (block 0)550erased. The first portion of the first block (block 0)550may correspond to the wordlines520-528that are associated with the first set of physical layers502. The erase circuitry586may send one or more control signals to disable the switches580-584. Accordingly, the first portion of the first block (block 0)550(e.g., a first portion of each of the strings included in the first block (block 0)550) may be isolated from a second portion (e.g., a second sub-block) of the first block (block 0)550that corresponds to the second set of physical layers503. An erase voltage may be applied to the first portion of the first block (block 0)550to erase the first sub-block. For example, the erase voltage may be applied to a first portion of each of the strings included in the first block (block 0)550.

FIG. 6is a diagram of a particular embodiment of a memory600. The memory600may be included in the data storage device102ofFIG. 1.FIG. 6illustrates a portion of a three dimensional architecture of the memory600, such as the memory104. In the embodiment illustrated inFIG. 6, the memory600is a vertical bit line Resistive Random Access Memory (ReRAM) with a plurality of conductive lines in physical layers over a substrate (e.g., substantially parallel to a surface of the substrate), such as representative wordlines620,621,622, and623(only a portion of which is shown inFIG. 6) and a plurality of vertical conductive lines through the physical layers, such as representative bit lines610,611,612, and613. The wordline622may include or correspond to a first set of one or more physical layers601and the wordlines620,621may include or correspond to a second set of one or more of physical layers602.

The memory600also includes a plurality of resistance-based storage elements (e.g., memory cells), such as representative storage elements630,631,632,640,641, and642, each of which is coupled to a bit line and a wordline in arrays of memory cells in multiple physical layers over the substrate (e.g., a silicon substrate). The memory600also includes read/write circuitry604, such as the read circuitry140and/or the write circuitry142ofFIG. 1. The read/write circuitry604is coupled to wordline drivers608and bit line drivers606.

In the embodiment illustrated inFIG. 6, each of the wordlines includes a plurality of fingers (e.g., a first wordline620includes fingers624,625,626, and627). Each finger may be coupled to more than one bit line. To illustrate, a first finger624of the first wordline620is coupled to a first bit line610via a first storage element630at a first end of the first finger624and is coupled to a second bit line611via a second storage element640at a second end of the first finger624.

In the embodiment illustrated inFIG. 6, each bit line may be coupled to more than one wordline. To illustrate, the first bit line610is coupled to the first wordline620via the first storage element630and is coupled to a third wordline622via a third storage element632.

In the embodiment illustrated inFIG. 6, each bit line, such as the representative bit lines610,611,612, and613, may be coupled to one or more corresponding switches, such as representative switches660-664. The representative switch660may be configurable to couple and/or decouple a first portion of the bit line610(corresponding to the first set of physical layers601) and a second portion of the bit line610(corresponding to the second set of physical layers602). The switch660may include or correspond to the switch154ofFIG. 1, the switch204ofFIG. 2, the switches396,398ofFIG. 3, and/or the switches580-584ofFIG. 5. Each of the switches may be coupled to erase circuitry668. As illustrated inFIG. 6, only the switch660is depicted as being coupled to the erase circuitry668for clarity of illustration. The erase circuitry668may operate as described with respect to the erase circuitry144ofFIG. 1, the erase circuitry344ofFIG. 3, and/or the erase circuitry586ofFIG. 5.FIG. 6does not illustrate terminals (e.g., bias terminals) coupled to each of the bit lines for clarity of illustration. It is understood that the memory600may include one or more terminals coupled to each of the conductive channels, as described with reference to the terminals162-186ofFIG. 1, the terminals270-272ofFIG. 2, and/or the terminals362-372ofFIG. 3.

During a write operation, the controller120may receive data from a host device, such as the host device130ofFIG. 1. The controller120may send the data (or a representation of the data) to the memory600. For example, the controller120may encode the data prior to sending the encoded data to the memory600.

The read/write circuitry604may write the data to storage elements corresponding to the destination of the data. For example, the read/write circuitry604may apply selection signals to selection control lines coupled to the wordline drivers608and the bit line drivers606to cause a write voltage to be applied across a selected storage element. For example, to select the first storage element630, the read/write circuitry604may activate the wordline drivers608and the bit line drivers606to drive a programming current (also referred to as a write current) through the first storage element630. To illustrate, a first write current may be used to write a first logical value (e.g., a value corresponding to a high-resistance state) to the first storage element630, and a second write current may be used to write a second logical value (e.g., a value corresponding to a low-resistance state) to the first storage element630. The programming current may be applied by generating a programming voltage across the first storage element630by applying a first voltage to the first bit line610and to wordlines other than the first wordline620and applying a second voltage to the first wordline620. In a particular embodiment, the first voltage is applied to other bit lines (e.g., the bit lines614,615) to reduce leakage current in the memory600.

During a read operation, the controller120may receive a request from a host device, such as the host device130ofFIG. 1. The controller120may cause the read/write circuitry604to read bits from particular storage elements of the memory600by applying selection signals to selection control lines coupled to the wordline drivers608and the bit line drivers606to cause a read voltage to be applied across a selected storage element. For example, to select the first storage element630, the read/write circuitry604may activate the wordline drivers608and the bit line drivers606to apply a first voltage (e.g., 0.7 volts (V)) to the first bit line610and to wordlines other than the first wordline620. A lower voltage (e.g., 0 V) may be applied to the first wordline620. Thus, a read voltage is applied across the first storage element630, and a read current corresponding to the read voltage may be detected at a sense amplifier of the read/write circuitry604. The read current corresponds (via Ohm's law) to a resistance state of the first storage element630, which corresponds to a logical value stored at the first storage element630. The logical value read from the first storage element630and other elements read during the read operation may be provided to the controller120. Accordingly, each of the bit lines610,611,612, and613may include multiple portions and the multiple portions of a particular bit line may be in a stacked configuration.

Although various components of the data storage device102and the host device130depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable the controller120and/or the memory (e.g., the read circuitry140, the write circuitry142, and/or the erase circuitry144) ofFIG. 1to perform operations described herein. One or more aspects of the controller120and/or the memory104(e.g., the read circuitry140, the write circuitry142, and/or the erase circuitry144) ofFIG. 1may be implemented using a microprocessor or microcontroller programmed to perform operations described herein, such as one or more operations of method400ofFIG. 4. In a particular embodiment, the controller120and/or the memory (e.g., the read circuitry140, the write circuitry142, and/or the erase circuitry144) ofFIG. 1includes a processor executing instructions that are stored at a memory, such as a non-volatile memory of the data storage device102or the host device130. Alternatively or additionally, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of the non-volatile memory, such as at a read-only memory (ROM) of the data storage device102or the host device130.

In an illustrative example, the processor may execute the instructions to provide a control signal to isolate a first portion of a string of a memory from a second portion of the string. The instructions to provide the control signal may include instructions to receive a command (e.g., an erase command) from a controller, instructions to identify one or more switches included in a memory (e.g., a 3D memory) to be enabled, instructions to identify one or more switches included in the memory to be disabled, instructions to identify a block of the memory to be erased, instructions to determine whether to initiate a full block erase operation or a partial block erase operation, and/or instructions to identify one or more sub-blocks to be erased, as illustrative, non-limiting examples. The processor may execute instructions to provide an erase signal to erase the second portion of the string while data is maintained at the first portion of the string. The instructions to provide the erase signal may include instructions to send the erase signal to the memory, instructions to identify one or more terminals to receive an erase voltage, instructions to identify one or more wordlines to be erased, and/or instructions to determine a current value for each wordline erased during an erase operation corresponding to the erase signal, as illustrative, non-limiting examples.

The data storage device102may be attached to or embedded within one or more host devices, such as within a housing of a host communication device, which may correspond to the host device130. The data storage device102may be within a packaged apparatus such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, a computer device (e.g., a tablet or a laptop), or other device that uses internal non-volatile memory. However, in other embodiments, the data storage device102may be a portable device configured to be selectively coupled to one or more external devices, such as the host device130. For example, the data storage device102may be a removable device such as a Universal Serial Bus (USB) flash drive or a removable memory card, as illustrative examples.

The host device130may correspond to a mobile telephone, a music player, a video player, a gaming device or console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop, a tablet, or a notebook computer, a portable navigation device, another electronic device, or a combination thereof. The host device130may operate in compliance with a JEDEC Solid State Technology Association industry specification, such as an embedded MultiMedia Card (eMMC) specification or a Universal Flash Storage (UFS) Host Controller Interface specification. The host device130may operate in compliance with one or more other specifications, such as a Secure Digital (SD) Host Controller specification, as an illustrative example. Alternatively, the host device130may communicate with the data storage device102in accordance with another communication protocol.

The data storage device102may be configured to be coupled to the host device130as embedded memory, such as in connection with an embedded MultiMedia Card (eMMC®) (trademark of JEDEC Solid State Technology Association, Arlington, Va.) configuration, as an illustrative example. The data storage device102may correspond to an eMMC device. As another example, the data storage device102may correspond to a memory card, such as a Secure Digital (SD®) card, a microSD® card, a miniSD™ card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). The data storage device102may operate in compliance with a JEDEC industry specification. For example, the data storage device102may operate in compliance with a JEDEC eMMC specification, a JEDEC Universal Flash Storage (UFS) specification, one or more other specifications, or a combination thereof.

Two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. To illustrate, each of the memory device levels may have a corresponding substrate thinned or removed before stacking the memory device levels to form memory arrays. Because each of the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

In some implementations, the memory104and/or the RAM122is a non-volatile memory having a three dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The active area of a memory cell may be an area of the memory cell that is conductively throttled by a charge trap portion of the memory cell. The data storage device102and/or the host device130may include circuitry, such as read circuitry, write circuitry, and/or erase circuitry, as an illustrative, non-limiting example, associated with operation of the memory cells.

Associated circuitry is typically used for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry for controlling and driving memory elements to perform functions such as programming and reading. The associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements

One of skill in the art will recognize that this disclosure is not limited to the two dimensional and three dimensional structures described but cover all relevant memory structures within the spirit and scope of the disclosure as described herein and as understood by one of skill in the art.

The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments.