SHARED FIFO DEVICE

According to one embodiment, a shared FIFO device includes a write pointer control circuit, a read pointer control circuit, a write pointer selection circuit, a read pointer selection circuit, a selection circuit, and a memory array. The shared FIFO device performs FIFO access through n transfer routes (where n is an integer of 2 or greater).

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-129632, filed on Jul. 16, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments discussed herein are related to a shared FIFO device.

BACKGROUND

A microcomputer, a microprocessor, and the like are equipped with a first-in, first-out (FIFO) device. A FIFO device has memory with a capacity required by the system specification. To transfer data between devices, each data transfer route needs a FIFO device.

A complicated system requires a large number of data transfer routes and hence a large number of FIFO devices, leading to a problem where the circuit scale of the FIFO devices increases.

DETAILED DESCRIPTION

According to one embodiment, a shared FIFO device performs FIFO access through n transfer routes (where n is an integer of 2 or greater) and includes a write pointer control circuit, a read pointer control circuit, a write pointer selection circuit, a read pointer selection circuit, a selection circuit, and a memory array. The write pointer control circuit selects one of n write pointers based on a write pointer update request, the write pointers being arranged independently for the respective transfer routes, and instructs the selected write pointer to update information held by the write pointer. The read pointer control circuit selects one of n read pointers based on a read pointer update request, the read pointers being arranged independently for the respective transfer routes, and instructs the selected read pointer to update information held by the read pointer. The write pointer selection circuit selects the information in one of the n write pointers based on a route write select instruction. The read pointer selection circuit selects the information in one of the n read pointers based on a route read select instruction. The selection circuit selects a selection result from the write pointer selection circuit based on a write select instruction, and selects a selection result from the read pointer selection circuit based on a read select instruction. The memory array has m FIFO buffer memories (where m is an integer of 2 or greater), each including a next-entry-number memory area and a data memory area to be accessed based on write pointer information and read pointer information.

More embodiments will be described below with reference to the drawings. Throughout the drawings, the same reference numerals denote the same or like portions.

A shared FIFO device according to a first embodiment is described with reference to some of the drawings.FIG. 1is a diagram illustrating the shared FIFO device.

The shared FIFO device of the first embodiment includes two write pointers, two read pointers, a write pointer selection circuit, a read pointer selection circuit, and a selection circuit to select a write operation or a read operation, and has two data transfer routes to decrease the circuit scale.

As illustrated inFIG. 1, a shared FIFO device100includes a request control circuit1, a write pointer control circuit2, a read pointer control circuit3, a data selection circuit7, a validity value selection circuit8, a word line decoder9, a memory array10, a validity bit section11, a write pointer21, a write pointer22, a read pointer23, a read pointer24, a write pointer selection circuit25, a read pointer selection circuit26, and a selection circuit27.

The shared FIFO device100is a FIFO device that includes two data transfer routes and is capable of using them in a shared manner. The shared FIFO device100is applied to a system with two synchronized data transfer routes (e.g., a system with a microcomputer, a microprocessor, or the like).

The shared FIFO device100is used in, for example, devices required to consume low power and have high functionality such as a wearable device, a healthcare device, an industrial safety device, and a humanoid robot.

The request control circuit1receives a route1write request, a route1read request, a route2write request, and a route2read request. The request control circuit1transmits a route request to the data selection. circuit7, the write pointer selection circuit25, and the read pointer selection. circuit26. The request control circuit1transmits a write or read select instruction to the validity value selection circuit8and the selection circuit27. The request control circuit1transmits a write pointer update request to the write pointer control circuit2. The request control circuit1transmits a read pointer update request to the read pointer control circuit3.

The data selection circuit7receives route1write data and route2write data, selects the route1write data or the route2write data based on the route request from the request control circuit1, and outputs the selected data to a corresponding data memory area DATA of the memory array10. The route1write data is data used for, for example, serial input/output (SIO) mode, whereas the route2write data is data used for, for example, a universal asynchronous receiver-transmitter (UART).

The validity value selection circuit8receives a validity value which is valid and a validity value1′b0which is invalid, selects one of the validity value 1′b1 and the validity value 1′b0 based on the write or read select instruction, and outputs the selected validity value to the validity bit section11.

The write pointer control circuit2receives a write pointer update request from the request control circuit1. Based on the write pointer update request from the request control circuit1, the write pointer control circuit2instructs the write pointer21(a first write pointer) or the write pointer22(a second write pointer) to update the write point. Based on the write pointer update request from the request control circuit1, the write pointer control circuit2specifies a next-entry-number memory area NEN in the memory array10.

The read pointer control circuit3receives a read pointer update request from the request control circuit1. Based on the read pointer update request from the request control circuit1, the read pointer control circuit3instructs the read pointer23(a first read pointer) or the read pointer24(a second read pointer) to update the read point.

Based on the write pointer control circuit2, the write pointer21updates the value held in itself. Based on the write pointer control circuit2, the write pointer22updates the value held in itself Based on the read pointer control circuit3, the read pointer23updates the value held in itself Based on the read pointer control circuit3, the read pointer24updates the value held in itself.

The write pointer selection circuit25receives the information held by the write pointer21and the information held by the write pointer22, and based on the route request from the request control circuit1, selects the information held by the write pointer21or the information held by the write pointer22.

The read pointer selection circuit26receives the information held by the read pointer23and the information held by the read pointer24, and based on the route request from the request control circuit1, selects the information held by the read pointer23or the information held by the read pointer24.

The selection circuit27receives a selection result from the write pointer selection circuit25and a selection result from the read pointer selection circuit26, and based on the write or read select instruction from the request control circuit1, selects the selection result from the write pointer selection circuit25or the selection result from the read pointer selection circuit26.

Although a multiplexer is used as the data selection circuit7, the validity value selection circuit8, the write pointer selection circuit25, the read pointer selection circuit26, and the selection circuit27herein, a selector or the like may be used instead.

The word line decoder9is provided between the selection circuit27and the memory array10. The word line decoder9receives a selection result from the selection circuit27, performs decoding processing on the selection result, and notifies the memory array10of a result of the decoding processing as one of entry requests E0S to E7S. Specifically the word line decoder9outputs a selection signal to a word line of the memory array10to which to write or from which to read data.

The memory array10includes in buffers20(where m is an integer of 2 or greater) each constituted by the next-entry-number memory area NEN and the data memory area DATA. The buffers20are FIFO buffer memories. Here, the memory array10includes eight buffers20-0to20-7.

Upon receipt of an instruction from the write pointer control circuit2and a decoding processing result from the word line decoder9, the next-entry-number memory area NEN updates the entry number of the corresponding word line. Upon receipt of a selection result from the data selection circuit7and a decoding processing result from the word line decoder9, the data memory area DATA updates data in the data memory area DATA on the corresponding word line.

The memory array10outputs the information in the data memory area DATA on the specified line. The memory array10outputs the information in the next-entry-number memory area NEN in which the next entry number is stored, to the read pointer control circuit3.

The validity bit section11includes m validity bits (where in is an. integer of 2 or greater). Here, the validity bit section11includes eight validity bits11-0to11-7. Based on a selection result from the validity value selection circuit8and the updated information in the data memory area DATA of the memory array10, the validity bit section11updates the information in the corresponding validity bit. The validity bit section11outputs valid/invalid information for a corresponding one of the entry requests E0S to E7S to the write pointer control circuit2and the read pointer control circuit3.

Here, read access to the buffers20is performed using a pre-updated pointer value. Write access to the next-entry-number memory area NEN is made based on pre-updated pointer values in the write pointer21and the write pointer22, and write access to the buffers20is made based on updated pointer values in the write pointer21and the write pointer22. The updated value in the read pointer23or the read pointer24is a copy of the value in the next-entry-number memory area NEN of the entry being read.

Next, operation of the shared FIFO device is described with reference toFIGS. 2 to 16.FIG. 2is a flowchart illustrating the operation of the shared FIFO device.

As illustrated inFIG. 2, the shared FIFO device100of the first embodiment performs a write operation at the route1, a write operation at the route2, a read operation at the route1, and a read operation at the route2. Steps of the operation of the shared FIFO device are described in detail. usingFIGS. 3 to 16.

As illustrated inFIG. 3, in the initial state, data in the write pointer21is set to “0”, data in the write pointer22is set to “1”, data in the read. pointer23is set to “0”, and data in the read pointer24is set to “1”. The data memory area DATA of the buffer20-0and the data memory area DATA of the buffer20-1are set to the reserved state (Step S1).

As illustrated inFIG. 4, for the first write operation at the route1, the request control circuit1receives a route1write request. The write pointer selection circuit25receives a route1write select instruction outputted from the request control circuit1. Based on the route1write select instruction from the request control circuit1, the write pointer selection circuit25selects “0”, which is the value of the write pointer21. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the select result (“0”) from the write pointer selection circuit25.

As a result, the data memory area DATA of the buffer20-0on the first word line is selected. Route1write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-0(the data is indicated as DATA1-1). Data in the validity bit11-0is set to valid information “1” based on1′b1outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-0. The valid information is transmitted to the write pointer control circuit2(Step S2).

As illustrated inFIG. 5, for the first write operation at the route2, the request control circuit1receives a route2write request. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction. from the request control circuit1, the write pointer selection circuit25selects “1” of the write pointer21. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the select result (“1”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, the data memory area DATA of the buffer20-1on the next word line is selected. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-1(the data is indicated as DATA2-1). Data in the validity bit11-1is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-1. The valid information is transmitted to the write pointer control circuit2(Step S3).

As illustrated inFIG. 6, for the second write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “1” to “2”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “2” of the write pointer22. The selection circuit27receives a write select instruction. outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“2”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, data in the next-entry-number memory area NEN of the buffer20-1is set to “2”. The data memory area DATA of the buffer20-2on the next word line is selected. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-2(the data is indicated as DATA2-2). Data in the validity bit11-2is set to valid information “1” based on 1′b1. outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-2. The valid information is transmitted to the write pointer control circuit2(Step S4).

As illustrated inFIG. 7, for the third write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “2” to “3”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “3” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“3”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, data in the next-entry-number memory area NEN of the buffer20-2is set to “3”. The data memory area DATA of the buffer20-3on the next word line is selected. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-3(the data is indicated as DATA2-3). Data in the validity bit11-3is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-3. The valid information is transmitted to the write pointer control circuit2(Step S5).

As illustrated inFIG. 8, for the second write operation at the route1, the request control circuit1receives a route1write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer21from “0” to “4”. The write pointer selection circuit25receives a route1write select instruction outputted from the request control circuit1. Based on the route1write select instruction from the request control circuit1, the write pointer selection circuit25selects “4” of the write pointer21. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“4”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, the data in the next-entry-number memory area NEN of the buffer20-0is set to “4”. The data memory area DATA of the buffer20-4on the next word line is selected. Route1write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-4(the data is indicated as DATA1-2). Data in the validity bit11-4is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-4. The valid information is transmitted to the write pointer control circuit2(Step S6).

As illustrated inFIG. 9, for the fourth write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “3” to “5”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “5” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“5”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, the data in the next-entry-number memory area NEN of the buffer20-3is set to “5”. The data memory area DATA of the buffer20-5on the next word line is selected. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-5(the data is indicated as DATA2-4). Data in the validity bit11-5is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-5. The valid information is transmitted to the write pointer control circuit2(Step S7).

As illustrated inFIG. 10, for the third write operation at the route1, the request control circuit1receives a route1write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer21from “4” to “6”. The write pointer selection circuit25receives a route1write select instruction outputted from the request control circuit1. Based on the route1write select instruction from the request control circuit1, the write pointer selection circuit25selects “6” of the write pointer21. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“6”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction of the write pointer control circuit2. As a result, the data in the next-entry-number memory area NEN of the buffer20-4is set to “6”. The data memory area DATA of the buffer20-6on the next word line is selected. Route1write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-6(the data is indicated as DATA1-3). Data in the validity bit11-6is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-6. The valid information is transmitted to the write pointer control circuit2(Step S8).

As illustrated inFIG. 11, for the fifth write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “5” to “7”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “7” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“7”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, the data in the next-entry-number memory area NEN of the buffer20-5is set to “7”. The data memory area DATA of the buffer20-7on the next word line is selected. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-7(the data is indicated as DATA2-5). Data in the validity bit11-7is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-7. The valid information is transmitted to the write pointer control circuit2(Step S9).

As illustrated inFIG. 12, for the first read operation at the route1, the request control circuit1receives a route1read request and transmits a read pointer update request to the read pointer control circuit3.

Based on the read pointer update request from the request control circuit1, the read pointer control circuit3updates the data held by the read pointer23from “0” to “4”. The read pointer selection circuit26receives a route1read select instruction outputted from the request control circuit1. Based on the route1read select instruction from the request control circuit1, the read pointer selection circuit26selects “0” of the read pointer23. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection result (“0”) from the read pointer selection circuit26.

According to the value in the read pointer23, the data (DATA1-1) stored in the data memory area DATA of the buffer20-0is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-0is read and transmitted to the read pointer control circuit3. The data stored in the data memory area DATA of the buffer20-0and the data in the next-entry-number memory area NEN of the buffer20-0are updated. The validity bit11-0is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-0is transmitted to the read. pointer control circuit3(Step S10).

As illustrated inFIG. 13, for the second. read operation at the route1, the request control circuit1receives a route1read request and transmits a read pointer update request to the read pointer control circuit3.

Based on the read pointer update request of the request control circuit1the read pointer control circuit3updates the data held by the read pointer23from “4” to “6”. The read pointer selection circuit26receives a route1read select instruction outputted from the request control circuit1. Based on the route1read select instruction from the request control circuit1, the read pointer selection circuit26selects “4” of the read pointer23. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection result (“4”) from the read pointer selection circuit26.

According to the value in the read pointer23, the data (DATA1-2) stored in the data memory area DATA of the buffer20-4is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-4is read and transmitted to the read pointer control circuit3. The data stored in the data memory area DATA of the buffer20-4and the data in the next-entry-number memory area NEN of the buffer20-4are updated. The validity bit11-4is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-4is transmitted to the read pointer control circuit3(Step S11).

As illustrated inFIG. 14, for the third read operation at the route1, the request control circuit1receives a route1read request.

The read pointer selection circuit26receives a route1read select instruction outputted from the request control circuit1. Based on the route1read select instruction from the request control circuit1., the read pointer selection circuit26selects “6” of the read pointer23. The selection circuit27receives a read select instruction outputted from the request control. circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection result (“6”) from the read pointer selection circuit26.

According to the value in the read pointer23, the data (DATA1-3) stored in the data memory area DATA of the buffer20-6is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-6is read and transmitted to the read pointer control circuit3. The data memory area DATA of the buffer20-6is set to the reserved state. The next-entry-number memory area NEN of the buffer20-6is available for the next entry. The validity bit11-6is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-6is transmitted to the read pointer control circuit3(Step S12).

As illustrated inFIG. 15, for the sixth write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “7” to “0”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “0” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“0”) from the write pointer selection circuit25.

The memory array10receives a decoding processing result from the word line decoder9and an instruction from the write pointer control circuit2. As a result, the data in the next-entry-number memory area NEN of the buffer20-7is set to “0”. The data memory area DATA of the buffer20-0on the next word line is selected. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-0(the data is indicated as DATA2-6). Data in the validity bit11-0is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-0. The valid information is transmitted to the write pointer control circuit2(Step S13).

As illustrated inFIG. 16, for the first read operation at the route2, the request control circuit1receives a route2read request and transmits a read pointer update request to the read pointer control circuit3.

Based on the read pointer update request from the request control circuit1, the read pointer control circuit3updates the data held by the read pointer24from “1” to “2”. The read pointer selection circuit26receives a route2read select instruction outputted from the request control circuit1. Based on the route2read select instruction from the request control circuit1, the read pointer selection circuit26selects “1” of the read pointer24. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection result (“1”) from the read pointer selection circuit26.

According to the value in the read pointer24, the data (DATA2-1) stored in the data memory area DATA of the buffer20-1is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-1is read and transmitted to the read pointer control circuit3. The data stored in the data memory area DATA of the buffer20-1and the data in the next-entry-number memory area NEN of the buffer20-1are updated. The validity bit11-1is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-1is transmitted to the read pointer control circuit3(Step S14).

Although the shared FIFO device100of the first embodiment includes two data transfer routes, the invention is not necessarily limited to such a case. The shared FIFO device may be provided with n transfer routes (where ii is an integer of 2 or greater). In such a case, the request control circuit receives n write requests and ii read requests. it is preferable that n write pointers and n read pointers are provided. it is also preferable that n pieces of write data are inputted to the data selection circuit7.

As described above, the shared FIFO device100of the first embodiment is provided with the request control circuit1, the write pointer control circuit2, the read pointer control circuit3, the data selection circuit7, the validity value selection circuit8, the word line decoder9, the memory array10, the validity bit section11, the write pointer21, the write pointer22, the read pointer23, the read pointer24, the write pointer selection circuit25, the read pointer selection circuit26, and the selection circuit27. The write pointer selection circuit25selects either data held by the write pointer21or data held by the write pointer22based on an instruction from the request control circuit1. The read pointer selection circuit26selects either data held by the read pointer23or data held by the read pointer24based on an instruction from the request control circuit1. The selection circuit27selects either a selection result from the write pointer selection circuit25or a selection result from the read pointer selection circuit26based on an instruction from the request control circuit1.

Thus, the shared FIFO device100can use a plurality of data transfer routes in a shared manner simultaneously. As a result, the circuit scale of the shared FIFO device100can be reduced. Further, unused memory in the shared FIFO device100can be put into effective use.

A shared FIFO device according to a second embodiment is described with reference to some of the drawings.FIG. 17is a diagram illustrating the shared FIFO device.

The shared FIFO device of the second embodiment includes a reservation control circuit, two write pointers, two read pointers, a write pointer selection circuit, a read pointer selection circuit, and a selection circuit to select a write or read operation. To reduce circuit scale, two data transfer routes are provided, and reservation of the next entry is performed at the same time as a data write operation.

As illustrated inFIG. 18, a shared FIFO device200includes the request control circuit1, the write pointer control circuit2, the read pointer control circuit3, the data selection circuit7, the validity value selection circuit8, the word line decoder9, the memory array10, the validity bit section11, a reservation control circuit12, the write pointer21, the write pointer22, the read pointer23, the read pointer24, the write pointer selection circuit25, the read pointer selection circuit26, and the selection circuit27.

The shared FIFO device200of the second embodiment is the shared. FIFO device100of the first embodiment additionally including the reservation control circuit12.

The same portions as those in the first embodiment are denoted by the same reference signs and are not described below. Only differences will be described.

The reservation control circuit12determines the entry number for the next write operation based on the value in the write pointer21, the value in the write pointer22, and the value in the validity bit section11, and outputs the number of the entry where the next data is to be stored (entry link information) to the next-entry-number memory area NEN of the memory array10.

In the first embodiment, the data memory area DATA and the next-entry-number memory area NEN of different entries need to be accessed in a write operation. For this reason, the first embodiment needs to access them independently or access them in two cycles.

In contrast, the shared FIFO device200of the second embodiment performs processing to write the entry number where the next data is to be written at the same time as a data write operation.

In the second embodiment, the values in the write pointer21and the write pointer22are updated after write access is made to the buffers20, and the values in the read pointer23and the read pointer24are updated after read access is made to the buffers20. Write access and read access to the buffers20-0to20-7are performed using pre-update pointer values.

Next, operation of the shared. FIFO device is described with reference toFIGS. 18 to 32.FIG. 18is a flowchart illustrating the operation of the shared FIFO device.FIGS. 19 to 32are diagrams illustrating the steps of the operation of the shared FIFO device,

As illustrated inFIG. 19, in the initial state, the reservation control circuit12has not received an instruction from the write pointer control circuit2. Data in the write pointer21is set to “0”, data in the write pointer22is set to “1”, data in the read pointer23is set to “0”, and data in the read pointer24is set to “1”. The data memory area DATA of the buffer20-0and the data memory area DATA of the buffer20-1are set to the reserved state (Step S21).

As illustrated inFIG. 20, for the first write operation at the route1, the request control circuit1receives a route1write request. The write pointer control circuit2receives a write pointer update request outputted from the request control circuit1. The reservation control circuit12stores “2” which is reservation information transmitted from the write pointer control circuit2. Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the information in the write pointer21from “0” to “2”.

The write pointer selection circuit25receives a route1write select instruction outputted from the request control circuit1. Based on the route write select instruction from the request control circuit1, the write pointer selection circuit25selects “0” which is the value in the write pointer21. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit2a selects the selection result (“0”) from the write pointer selection circuit25.

The memory array10receives the information “2” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “2” in the reservation control circuit12is written to the next-entry-number memory area NEN of the buffer20-0, and the data memory area DATA of the buffer20-2is set to the reserved state. Route1write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-0(the data is indicated as DATA1-1). Data in the validity bit11-0is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-0. The valid information is transmitted to the write pointer control circuit2(Step S22).

As illustrated inFIG. 21, for the first write operation at the route2, the request control circuit1receives a route2write request. The write pointer control circuit2receives a write pointer update request outputted from the request control circuit1. The reservation control circuit12stores reservation information “3” transmitted from the write pointer control circuit2. Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the value held by the write pointer22from “1” to “3”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “1” of the write pointer22.

The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction. from the request control circuit1, the selection circuit27selects the selection. result (“1”) from the write pointer selection circuit25.

The memory array10receives the information “3” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “3” in the reservation control circuit12is written to the next-entry-number memory area NEN of the buffer20-1, and the data memory area DATA of the buffer20-3is set to the reserved state. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-1(the data is indicated as DATA2-1). Data in the validity bit11-1is set to valid information “1” based 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-1. The valid information is transmitted to the write pointer control circuit2(Step S23).

As illustrated inFIG. 22, for the second write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12stores reservation information “4” transmitted from the write pointer control circuit2. Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the value held by the write pointer22from “3” to “4”.

The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “3” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control. circuit1. Based on the write select instruction from the request control. circuit1, the selection circuit27selects the selection result (“3”) from the write pointer selection circuit25.

The memory array10receives the information “4” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “4” in the reservation control circuit12is written to the next-entry-number memory area NEN of the buffer20-3, and the data memory area DATA of the buffer20-4is set to the reserved state. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-3(the data is indicated as DATA2-2). Data in the validity bit11-3is set to valid information “1” based on 1′b1 outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-3. The valid information is transmitted to the write pointer control circuit2(Step S24).

As illustrated inFIG. 23, for the third write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12stores reservation information “5” transmitted from the write pointer control circuit2. Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the value held by the write pointer22from “4” to “5”.

The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “4” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control. circuit1. Based on the write select instruction from the request control. circuit1, the selection circuit27selects the selection result (“4”) from the write pointer selection circuit25.

The memory array10receives the information “5” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “5” in the reservation control circuit12is written to the next-entry-number memory area NEN of the buffer20-4, and the data memory area DATA of the buffer20-5is set to the reserved state. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-4(the data is indicated as DATA2-3). Data in the validity bit11-4is set to valid information “1” based on1%1outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-4. The valid information is transmitted to the write pointer control circuit2(Step S25).

As illustrated inFIG. 24, for the second write operation at the route1, the request control circuit1receives a route1write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12stores reservation information “6” transmitted from the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer21from “2” to “6”. The write pointer selection circuit25receives a route1write select instruction outputted from the request control circuit1. Based on the route1write select instruction from the request control circuit1, the write pointer selection circuit25selects “2” of the write pointer21. The selection circuit27receives a write select instruction. outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“2”) from the write pointer selection circuit25.

The memory array10receives the information “6” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “6” in the reservation control circuit12is written to the next-entry-number memory area NEN of the buffer20-2, and the data memory area DATA of the buffer20-6is set to the reserved state, Route1write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-2(the data is indicated as DATA1-2). Data in the validity bit11-2is set to valid information “1” based on Pin outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-2. The valid information is transmitted to the write pointer control circuit2(Step S26).

As illustrated inFIG. 25, for the fourth write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12stores reservation information “7” transmitted from the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “5” to “7”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control. circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “5” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“5”) from the write pointer selection circuit25.

The memory array10receives the information “7” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “7” in the reservation control circuit12is written to the next-entry-number memory area NEN of the buffer20-5, and the data memory area DATA of the buffer20-7is set to the reserved state, Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-5(the data is indicated as DATA2-4). Data in the validity bit11-5is set to valid information “1” based on1%1outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-5. The valid information is transmitted to the write pointer control circuit2(Step S27).

As illustrated inFIG. 26, for the third write operation at the route1, the request control circuit1receives a route1write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12maintains the reservation information “7” transmitted from the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer21from “6” to “0”. The write pointer selection circuit25receives a route1write select instruction outputted from the request control. circuit1. Based on the route1write select instruction from the request control circuit1, the write pointer selection circuit25selects “0” of the write pointer21. The selection circuit27receives a write select instruction. outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“0”) from the write pointer selection circuit25.

The memory array10receives the information “7” in the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “0” in the write pointer21is written to the next-entry-number memory area NEN of the buffer20-6. Route1write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-6(the data is indicated as DATA1-3). Data in the validity bit11-6is set to valid information “1” based on1′b1outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-6. The valid information is transmitted to the write pointer control circuit2(Step S28).

As illustrated inFIG. 27, for the fifth write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12maintains reservation information “7” transmitted from the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “7” to “1”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control. circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “1” of the write pointer22. The selection circuit27receives a write select instruction. outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“1”) from the write pointer selection circuit25.

The memory array10receives the information “7” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “1” in the write pointer22is written to the next-entry-number memory area NEN of the buffer20-7. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-7(the data is indicated as DATA2-5). Data in the validity bit11-7is set to valid information “1” based on1′b1outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-7. The valid information is transmitted to the write pointer control circuit2(Step S29).

As illustrated inFIG. 28, for the first read operation at the route1, the request control circuit1receives a route1read request and transmits a read pointer update request to the read pointer control circuit3. The reservation control circuit12maintains reservation information “7” transmitted from the write pointer control circuit2.

Based on the read pointer update request from the request control circuit1, the read pointer control circuit3updates the data held by the read pointer23from “0” to “2”. The read pointer selection circuit26receives a route1read select instruction outputted from the request control circuit1. Based on the route1read select instruction from the request control circuit1, the read pointer selection circuit26selects “0” of the read pointer23. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection result (“0”) from the read pointer selection circuit26.

According to the value in the read pointer23, the data (DATA1-1) stored in the data memory area DATA of the buffer20-0is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-0is read and transmitted to the read pointer control circuit3. The data stored in the data memory area DATA of the buffer20-0and the data in the next-entry-number memory area NEN of the buffer20-0are updated. The validity bit11-0is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-0is transmitted to the read pointer control circuit3(Step S30).

As illustrated inFIG. 29, for the second read operation at the route1, the request control circuit1receives a route1read request and transmits a read pointer update request to the read pointer control circuit3. The reservation control circuit12does not hold any reservation information transmitted from the write pointer control circuit2.

The read pointer selection circuit26receives a route1read select instruction outputted from the request control circuit1. Based on the route1read select instruction from the request control circuit1, the read pointer selection circuit26updates the data held by the read pointer23from “2” to “6”. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection. result (“2”) from the read pointer selection circuit26.

According to the value in the read pointer23, the data (DATA1-2) stored in the data memory area DATA of the buffer20-2is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-2is read and transmitted to the read pointer control circuit3. The data stored in the data memory area DATA of the buffer20-2and the data in the next-entry-number memory area NEN of the buffer20-2are updated. The validity bit11-2is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-2is transmitted. to the read pointer control circuit3(Step S31).

As illustrated inFIG. 30, for the third read operation at the route1, the request control circuit1receives a route1read request and transmits a read pointer update request to the read pointer control circuit3. The reservation control circuit12does not hold any reservation information transmitted from the write pointer control circuit2.

The read pointer selection circuit26receives a route1read select instruction outputted from the request control circuit1. Based on the route1read select instruction from the request control circuit1, the read pointer selection circuit26updates the data held by the read pointer23from “6” to “0”. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection. result (“6”) from the read pointer selection circuit26.

According to the value in the read pointer23, the data (DATA1-3) stored in the data memory area DATA of the buffer20-6is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-6is read and transmitted to the read pointer control. circuit3. The data stored in the data memory area DATA of the buffer20-6and the data in the next-entry-number memory area NEN of the buffer20-6are updated. The validity bit11-6is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-6is transmitted to the read pointer control circuit3(Step S32).

As illustrated inFIG. 31, for the sixth write operation at the route2, the request control circuit1receives a route2write request and transmits a write pointer update request to the write pointer control circuit2. The reservation control circuit12stores reservation information “6” transmitted from the write pointer control circuit2.

Based on the write pointer update request from the request control circuit1, the write pointer control circuit2updates the data held by the write pointer22from “2” to “6”. The write pointer selection circuit25receives a route2write select instruction outputted from the request control circuit1. Based on the route2write select instruction from the request control circuit1, the write pointer selection circuit25selects “2” of the write pointer22. The selection circuit27receives a write select instruction outputted from the request control circuit1. Based on the write select instruction from the request control circuit1, the selection circuit27selects the selection result (“2”) from the write pointer selection circuit25.

The memory array10receives the information “6” outputted from the reservation control circuit12and a decoding processing result from the word line decoder9.

As a result, the information “6” is written to the next-entry-number memory area NEN of the buffer20-2. Route2write data outputted from the data selection circuit7is written to the data memory area DATA of the buffer20-2(the data is indicated as DATA2-6). Data in the validity bit11-2is set to valid information “1” based on1′b1outputted from the validity value selection circuit8and the write result from the data memory area DATA of the buffer20-2. The valid information is transmitted to the write pointer control circuit2(Step S33).

As illustrated inFIG. 32, for the first read operation at the route2, the request control circuit1receives a route2read request and transmits a read pointer update request to the read pointer control circuit3. The reservation control circuit12does not hold any reservation information transmitted from the write pointer control circuit2.

Based on the read pointer update request from the request control circuit1, the read pointer control circuit3updates the data held by the read pointer24from “1” to “3”. The read pointer selection circuit26receives a route2read select instruction outputted from the request control circuit1. Based on the route2read select instruction from the request control circuit1, the read pointer selection circuit26selects “1” of the read pointer24. The selection circuit27receives a read select instruction outputted from the request control circuit1. Based on the read select instruction from the request control circuit1, the selection circuit27selects the selection result (“1”) from the read pointer selection circuit26.

According to the value in the read pointer24, the data (DATA2-1) stored in the data memory area DATA of the buffer20-1is read and outputted to the outside. The data in the next-entry-number memory area NEN of the buffer20-1is read and transmitted to the read pointer control circuit3. The data stored in the data memory area DATA of the buffer20-1and the data in the next-entry-number memory area NEN of the buffer20-1are updated. The validity bit11-1is changed from the valid information “1” to invalid information “0”, and the data is cleared. Information indicative of the clearing concerning the validity bit11-1is transmitted to the read pointer control circuit3(Step S34).

As described above, the shared FIFO device200of the second embodiment is provided with the request control circuit1, the write pointer control circuit2, the read pointer control circuit3, the data selection circuit7, the validity value selection circuit8, the word line decoder9, the memory array10, the validity bit section11, the reservation control circuit12, the write pointer21, the write pointer22, the read pointer23, the read pointer24, the write pointer selection circuit25, the read pointer selection circuit26, and the selection circuit27. The reservation control circuit12determines the entry number for the next write operation based on the value in the write pointer21, the value in the write pointer22, and the value in the validity bit section11, and outputs the number of the entry where the next data is to be stored to the next-entry-number memory area NEN of the memory array10

Thus, in addition to the advantageous effects produced by the first embodiment, the shared FIFO device200can improve simplicity of the structure of the memory array10and access performance of the memory array10.

While certain embodiments have been described, these embodiments have been presented by way of example only and are not intend to limit the scope of the inventions. Indeed, the novel embodiments described herein. may be embodied in a variety of the other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.