Efficient wide range bit counter

An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.

BACKGROUND

This application relates to the counter circuits for recording the number of occurrences of an event on an integrated circuit.

Integrated circuits of many sorts of need to keep track of the number of occurrences of various events. For example, non-volatile memory circuits often need to track of the number of program-erase cycles or the number of times elements have been read for purposes of wear levelling or determining when to perform data scrub operations. In NAND flash memory, error bits counting is important for features such as: deciding the stop point of programming; deciding stop point of program verify; deciding programming start voltage; deciding error bits for test; deciding dynamic read levels; detecting word line failures; and so on.

In many such applications, the number of bits that need to be counted can be quite large. However the counting of these bits consumes test time or operation time, directly degrading system performance and increasing test cost. In these cases, the time to reach the count is often more important than having the count accurate to a high number of significant digits.

SUMMARY

An event counter circuit is formed on an integrated circuit includes first and second counters and logic circuitry. The first counter has a first capacity connected to count the number of occurrences of a first sub-set of a first event and the second counter has a second capacity connected to count the number of occurrences of a second sub-set of the first event. The logic circuitry is connected to the first and second counters and provides the count of the number of occurrences of the first event as the sum of the values of first and second counter when neither has reached their respective capacity. In response to one of the first and second counters reaching its respective capacity, the other of the first and second counters is used as an extension of the first one, where the logic circuitry then provides the count of the number of occurrences of the first event as the values of the first one of the first and second counters scaled according to their relative capacities.

Various aspects, advantages, features and embodiments are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.

DETAILED DESCRIPTION

Memory System

FIG. 1illustrates schematically the main hardware components of a memory system suitable for implementing the following. The memory system90typically operates with a host80through a host interface. The memory system may be in the form of a removable memory such as a memory card, or may be in the form of an embedded memory system. The memory system90includes a memory102whose operations are controlled by a controller100. The memory102comprises one or more array of non-volatile memory cells distributed over one or more integrated circuit chip. The controller100may include interface circuits110, a processor120, ROM (read-only-memory)122, RAM (random access memory)130, programmable nonvolatile memory124, and additional components. The controller is typically formed as an ASIC (application specific integrated circuit) and the components included in such an ASIC generally depend on the particular application.

It will be recognized that the following is not limited to the two dimensional and three dimensional exemplary structures described but cover all relevant memory structures within the spirit and scope as described herein.

Physical Memory Structure

FIG. 2illustrates schematically a non-volatile memory cell. The memory cell10can be implemented by a field-effect transistor having a charge storage unit20, such as a floating gate or a charge trapping (dielectric) layer. The memory cell10also includes a source14, a drain16, and a control gate30.

There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may employ different types of memory cells, each type having one or more charge storage element.

Typical non-volatile memory cells include EEPROM and flash EEPROM. Also, examples of memory devices utilizing dielectric storage elements.

In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.

Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to set the threshold voltage for a given memory state under test at the control gate and detect if the conduction current is lower or higher than a threshold current (cell-read reference current). In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line.

FIG. 3illustrates the relation between the source-drain current IDand the control gate voltage VCGfor four different charges Q1-Q4that the floating gate may be selectively storing at any one time. With fixed drain voltage bias, the four solid IDversus VCGcurves represent four of seven possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. As an example, the threshold voltage window of a population of cells may range from 0.5V to 3.5V. Seven possible programmed memory states “0”, “1”, “2”, “3”, “4”, “5”, “6”, and an erased state (not shown) may be demarcated by partitioning the threshold window into regions in intervals of 0.5V each. For example, if a reference current, IREF of 2 μA is used as shown, then the cell programmed with Q1may be considered to be in a memory state “1” since its curve intersects with IREFin the region of the threshold window demarcated by VCG=0.5V and 1.0V. Similarly, Q4is in a memory state “5”.

As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold window. For example, a memory device may have memory cells having a threshold window that ranges from −1.5V to 5V. This provides a maximum width of 6.5V. If the memory cell is to store 16 states, each state may occupy from 200 mV to 300 mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.

NAND Structure

FIG. 4illustrates schematically a string of memory cells organized into a NAND string. A NAND string50comprises a series of memory transistors M1, M2, . . . Mn (e.g., n=4, 8, 16 or higher) daisy-chained by their sources and drains. A pair of select transistors S1, S2controls the memory transistor chain's connection to the external world via the NAND string's source terminal54and drain terminal56respectively. In a memory array, when the source select transistor S1is turned on, the source terminal is coupled to a source line (seeFIG. 5). Similarly, when the drain select transistor S2is turned on, the drain terminal of the NAND string is coupled to a bit line of the memory array. Each memory transistor10in the chain acts as a memory cell. It has a charge storage element20to store a given amount of charge so as to represent an intended memory state. A control gate30of each memory transistor allows control over read and write operations. As will be seen inFIG. 5, the control gates30of corresponding memory transistors of a row of NAND string are all connected to the same word line. Similarly, a control gate32of each of the select transistors S1, S2provides control access to the NAND string via its source terminal54and drain terminal56respectively. Likewise, the control gates32of corresponding select transistors of a row of NAND string are all connected to the same select line.

When an addressed memory transistor10within a NAND string is read or is verified during programming, its control gate30is supplied with an appropriate voltage. At the same time, the rest of the non-addressed memory transistors in the NAND string50are fully turned on by application of sufficient voltage on their control gates. In this way, a conductive path is effectively created from the source of the individual memory transistor to the source terminal54of the NAND string and likewise for the drain of the individual memory transistor to the drain terminal56of the cell.

FIG. 5illustrates an example of a NAND array210of memory cells, constituted from NAND strings50such as that shown inFIG. 4. Along each column of NAND strings, a bit line such as bit line36is coupled to the drain terminal56of each NAND string. Along each bank of NAND strings, a source line such as source line34is coupled to the source terminals54of each NAND string. Also the control gates along a row of memory cells in a bank of NAND strings are connected to a word line such as word line42. The control gates along a row of select transistors in a bank of NAND strings are connected to a select line such as select line44. An entire row of memory cells in a bank of NAND strings can be addressed by appropriate voltages on the word lines and select lines of the bank of NAND strings.

FIG. 6illustrates a page of memory cells, organized in the NAND configuration, being sensed or programmed in parallel.FIG. 6essentially shows a bank of NAND strings50in the memory array210ofFIG. 5, where the detail of each NAND string is shown explicitly as inFIG. 4. A physical page, such as the page60, is a group of memory cells enabled to be sensed or programmed in parallel. This is accomplished by a corresponding page of sense amplifiers212. The sensed results are latched in a corresponding set of latches214. Each sense amplifier can be coupled to a NAND string via a bit line. The page is enabled by the control gates of the cells of the page connected in common to a word line42and each cell accessible by a sense amplifier accessible via a bit line36. As an example, when respectively sensing or programming the page of cells60, a sensing voltage or a programming voltage is respectively applied to the common word line WL3together with appropriate voltages on the bit lines.

Physical Organization of the Memory

One difference between flash memory and other of types of memory is that a cell is programmed from the erased state. That is, the floating gate is first emptied of charge. Programming then adds a desired amount of charge back to the floating gate. It does not support removing a portion of the charge from the floating gate to go from a more programmed state to a lesser one. This means that updated data cannot overwrite existing data and is written to a previous unwritten location.

Furthermore erasing is to empty all the charges from the floating gate and generally takes appreciable time. For that reason, it will be cumbersome and very slow to erase cell by cell or even page by page. In practice, the array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together. While aggregating a large number of cells in a block to be erased in parallel will improve erase performance, a large size block also entails dealing with a larger number of update and obsolete data.

Each block is typically divided into a number of physical pages. A logical page is a unit of programming or reading that contains a number of bits equal to the number of cells in a physical page. In a memory that stores one bit per cell, one physical page stores one logical page of data. In memories that store two bits per cell, a physical page stores two logical pages. The number of logical pages stored in a physical page thus reflects the number of bits stored per cell. In one embodiment, the individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation. One or more logical pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data.

FIG. 7A-7Cillustrate an example of programming a population of 4-state memory cells.FIG. 7Aillustrates the population of memory cells programmable into four distinct distributions of threshold voltages respectively representing memory states “0”, “1”, “2” and “3”.FIG. 7Billustrates the initial distribution of “erased” threshold voltages for an erased memory.FIG. 6Cillustrates an example of the memory after many of the memory cells have been programmed. Essentially, a cell initially has an “erased” threshold voltage and programming will move it to a higher value into one of the three zones demarcated by verify levels vV1, vV2and vV3. In this way, each memory cell can be programmed to one of the three programmed states “1”, “2” and “3” or remain un-programmed in the “erased” state. As the memory gets more programming, the initial distribution of the “erased” state as shown inFIG. 7Bwill become narrower and the erased state is represented by the “0” state.

A 2-bit code having a lower bit and an upper bit can be used to represent each of the four memory states. For example, the “0”, “1”, “2” and “3” states are respectively represented by “11”, “01”, “00” and “10”. The 2-bit data may be read from the memory by sensing in “full-sequence” mode where the two bits are sensed together by sensing relative to the read demarcation threshold values rV1, rV2and rV3in three sub-passes respectively.

An alternative arrangement to a conventional two-dimensional (2-D) NAND array is a three-dimensional (3-D) array. In contrast to 2-D NAND arrays, which are formed along a planar surface of a semiconductor wafer, 3-D arrays extend up from the wafer surface and generally include stacks, or columns, of memory cells extending upwards. Various 3-D arrangements are possible. In one arrangement a NAND string is formed vertically with one end (e.g. source) at the wafer surface and the other end (e.g. drain) on top. In another arrangement a NAND string is formed in a U-shape so that both ends of the NAND string are accessible on top, thus facilitating connections between such strings.

FIG. 8shows a first example of a NAND string701that extends in a vertical direction, i.e. extending in the z-direction, perpendicular to the x-y plane of the substrate. Memory cells are formed where a vertical bit line (local bit line)703passes through a word line (e.g. WL0, WL1, etc.). A charge trapping layer between the local bit line and the word line stores charge, which affects the threshold voltage of the transistor formed by the word line (gate) coupled to the vertical bit line (channel) that it encircles. Such memory cells may be formed by forming stacks of word lines and then etching memory holes where memory cells are to be formed. Memory holes are then lined with a charge trapping layer and filled with a suitable local bit line/channel material (with suitable dielectric layers for isolation).

As with planar NAND strings, select gates705,707, are located at either end of the string to allow the NAND string to be selectively connected to, or isolated from, external elements709,711. Such external elements are generally conductive lines such as common source lines or bit lines that serve large numbers of NAND strings. Vertical NAND strings may be operated in a similar manner to planar NAND strings and both SLC and MLC operation is possible. WhileFIG. 8shows an example of a NAND string that has 32 cells (0-31) connected in series, the number of cells in a NAND string may be any suitable number. Not all cells are shown for clarity. It will be understood that additional cells are formed where word lines3-29(not shown) intersect the local vertical bit line.

A 3D NAND array can, loosely speaking, be formed tilting up the respective structures50and210ofFIGS. 5 and 6to be perpendicular to the x-y plane. In this example, each y-z plane corresponds to the page structure ofFIG. 6, with m such plane at differing x locations. The (global) bit lines, BL1-m, each run across the top to an associated sense amp SA1-m. The word lines, WL1-n, and source and select lines SSL1-nand DSL1-n, then run in x direction, with the NAND string connected at bottom to a common source line CSL.

FIGS. 9-12look at a particular monolithic three dimensional (3D) memory array of the NAND type (more specifically of the “BiCS” type), where one or more memory device levels are formed above a single substrate, in more detail.FIG. 9is an oblique projection of part of such a structure, showing a portion corresponding to two of the page structures inFIG. 5, where, depending on the embodiment, each of these could correspond to a separate block or be different “fingers” of the same block. Here, instead to the NAND strings lying in a common y-z plane, they are squashed together in the y direction, so that the NAND strings are somewhat staggered in the x direction. On the top, the NAND strings are connected along global bit lines (BL) spanning multiple such sub-divisions of the array that run in the x direction. Here, global common source lines (SL) also run across multiple such structures in the x direction and are connect to the sources at the bottoms of the NAND string, which are connected by a local interconnect (LI) that serves as the local common source line of the individual finger. Depending on the embodiment, the global source lines can span the whole, or just a portion, of the array structure. Rather than use the local interconnect (LI), variations can include the NAND string being formed in a U type structure, where part of the string itself runs back up.

To the right ofFIG. 9is a representation of the elements of one of the vertical NAND strings from the structure to the left. Multiple memory cells are connected through a drain select gate SGD to the associated bit line BL at the top and connected through the associated source select gate SDS to the associated local source line LI to a global source line SL. It is often useful to have a select gate with a greater length than that of memory cells, where this can alternately be achieved by having several select gates in series (as described in U.S. patent application Ser. No. 13/925,662, filed on Jun. 24, 2013), making for more uniform processing of layers. Additionally, the select gates are programmable to have their threshold levels adjusted. This exemplary embodiment also includes several dummy cells at the ends that are not used to store user data, as their proximity to the select gates makes them more prone to disturbs.

FIG. 10shows a top view of the structure for two blocks in the exemplary embodiment. Two blocks (BLK0above, BLK1below) are shown, each having four fingers that run left to right. The word lines and select gate lines of each level also run left to right, with the word lines of the different fingers of the same block being commonly connected at a “terrace” and then on to receive their various voltage level through the word line select gates at WLTr. The word lines of a given layer in a block can also be commonly connected on the far side from the terrace. The selected gate lines can be individual for each level, rather common, allowing the fingers to be individually selected. The bit lines are shown running up and down the page and connect on to the sense amp circuits, where, depending on the embodiment, each sense amp can correspond to a single bit line or be multiplexed to several bit lines.

FIG. 11shows a side view of one block, again with four fingers. In this exemplary embodiment, the select gates SGD and SGS at either end of the NAND strings are formed of four layers, with the word lines WL in-between, all formed over a CPWELL. A given finger is selected by setting its select gates to a level VSG and the word lines are biased according to the operation, such as a read voltage (VCGRV) for the selected word lines and the read-pass voltage (VREAD) for the non-selected word lines. The non-selected fingers can then be cut off by setting their select gates accordingly.

FIG. 12illustrates some detail of an individual cell. A dielectric core runs in the vertical direction and is surrounded by a channel silicon layer, that is in turn surrounded a tunnel dielectric (TNL) and then the charge trapping dielectric layer (CTL). The gate of the cell is here formed of tungsten with which is surrounded by a metal barrier and is separated from the charge trapping layer by blocking (BLK) oxide and a high K layer.

Efficient Wide Range Bit Counter

In non-volatile memory circuits, such as those described above, and numerous other application, integrated circuits employ counter to track events. In the non-volatile flash memory context, the number of reads to a physical address or the number of program erase cycles are regularly tracked for scrub, wear leveling, and other purposes. Another important use a bit/byte counter in NAND memory is to keep count error bits, as these are often of great importance in deciding a stop point of programming or a program verify, deciding programming or verify start voltage (as used in smart verify techniques), deciding error bits for testing, deciding dynamic read level, detecting word line failures, and so on.

During operation or at test times, the circuit may need to count large numbers of bits. This consumes test time or operation time, directly degrading system performance and increasing test costs. For comparison purposes, it is often only the first or first several significant digits of these counts that are needed, while errors in lower count bits are often not important. Often, it is rather the time to reach the count that is more important. For many of the counters' uses, high counts are preferred because the result is less affected by noise levels. For example, deciding on a programming verify termination based upon a small bit count might be misguided by slow bits. Other examples include the tracking of cell threshold voltage (Vt) distributions, a technique to find optimal read levels based on these distributions, and erratic programming detection, that detects programming problems based on counts of cells in Vt intervals usually located at troughs of the Vt distribution. The following presents a scheme and circuit structure to count large number of bits quickly and a with small layout area, resulting in higher system performance, better memory endurance and lower costs.

The general idea can be illustrated with respect to the simple example illustrated inFIG. 13. In this example, a counter is formed of two 4-bit sub-counters, Counter0of bits0-3and Counter1of bits4-7. Each of these counts a subset of some event. For example, bits0-3of Counter0could track the number of error bits from the left side of a memory array and bits4-7could track the number of events coming from the right side. As long as neither counter saturates, the total count is just the sum of the value of Counter0plus the value of Counter1. If one of the counters overflows, the other of the counters is used to extend the one that has overflowed. For example, if Counter0overflows first, counter1is cleared and used as extension of counter0. The count is then taken as the value of the (extended) Counter0, increased by a factor of 2. Similarly, if Counter1overflows first, it would take over Counter0. If the count is maintained in the format of a significand×2exponentformat, the count is the value of the extended counter with the exponent increased by 1 (significand×2exponent+1).

Although the count determined in this way may not be completely accurate, it will save space and provide a good approximation, as long as the two sub-counts are reasonably similar, with half the counter space. Here two sub-counters are used, but more generally, the technique can be extended to more counters each tracking a corresponding sub-count. As the sub-counters overflow, the saturated counter can be extended with others of the sub-counts, with the resultant sub-count scaled accordingly to approximate the total count. Additionally, in a more general embodiment, the sub-counters can have differing capacities; for example, this sort of asymmetric arrangement could be used if the sub-counters are responsible for differing sized subsets of events or if they were different, but to some extent correlated, events.

FIG. 14is a block diagram of an implementation of the counter on a NAND memory circuit. The memory array, including any sensing circuitry or other circuitry involved in providing the count, is represented at1401. The counter1403is then is made up of the sub-counters each responsible for a corresponding event subset, as described with respect toFIG. 13. The count is then passed on to the accumulator1405, where prior to overflow this will reflect the sum of the counts and after overflow this will reflect the expanded count of the counter that over flowed. The block1407will reflect whether the count one of the counters has overflowed and that value in the1405needs to be adjusted (i.e., multiplied by 2) or not. At the Final Count Generator1409the count is determined either as the sum of the counts (if no overflow) or the expanded count scaled up by 2.

A timer control1411enables the accumulator. As described in subsequent figures, the count may be formed sequentially over a series of ranges, in which case a range counter1413can be included. If there is a range counter1413, this can also be enabled by the timer control1411as well. The range counter1413keeps track of how many of the ranges have been included by the accumulator, so that, if needed, the final count can be adjusted in1409based on how many of the ranges were covered in the count. The result is then compared in1415.

FIG. 15illustrates having multiple ranges doing the count. The count is broken up into 16 ranges in this example, where each range is scanned and counted sequentially. In the memory circuit example, each range could correspond to a set of bit lines arranged into “tiers” of the memory array of1401. Upon completion of each range, the count is swept from the counter1403into accumulator1405. The range counter1413is incremented by 1 and the process moves on the next range until the count is completed, unless terminated early. Upon early termination, whether due to an interrupt command, reaching a maximum time, overflow or the (expanded) counter, or improper shutdown, the scan is terminated. The final count result is generated with the count in accumulator1405, range counter1413, and bit-counter mantissa1407. The result of the accumulator1409is projected and compared with pass/fail criteria at1415and counting can be terminated.

In the case of a time-out request, the current scan will finish the range and then the final result is calculated. This is illustrated inFIG. 16A, where the time-out request comes in during the third range, which is then completed. The final result is then calculated by scaling up the three read ranges to yield the projected value of all of the ranges.

Upon abort request, the current scan aborts immediately and its result discarded, with the final result being calculated from the range completed. This is illustrated with respect toFIG. 16B, where the abort request comes in during the fourth range, which is then discarded and the final result projected from the three completed ranges.

A efficient techniques for generating the final result when the count is based on less than all of the ranges is schematically illustrated with respect toFIG. 17. The count from the accumulator is multiplied by an adder and then shifted, providing the final count. The number of times that the partial result is added to itself and the number of bits it is shifted, based on the number of ranges used, is shown in Table 1. The result, relative to 1 (no error) and the corresponding amount of error is also shown.

For example, a single tier (1/16) would just need to multiplied by 16, corresponding to a shift of 4 (i.e., 24) and would have no error. Similarly, for 2 tiers (2/16) the result needs to multiplied by 8, a shift of 3 bits, and have no error. For 3/16, the result if multiplied by adding it to itself 11 times, yield 11×(3/16)=33/16; which is then shifted by −1 to give 33/32=1.03, an error of −3%. To take another example, for 14/16, this is added to itself 19 times, shifted by −4 (i.e., multiplied by 2+4), so that the result is scaled by 19/16. As 13/16*19/16=249/256, the error is 2%.

Consequently, the techniques of this section can support a wide range of counts with scientific notation. It allows for the counting scheme to be dynamically altered to maintain a balance between accuracy and performance and can accommodate early termination to allow it to fit timing budget.

CONCLUSION

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the above to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to explain the principles involved and its practical application, to thereby enable others to best utilize the various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.