Two-dimensional discrete cosine transform using SIMD instructions

A method is disclosed for performing a discrete cosine transform (DCT) using a microprocessor having an instruction set that includes SIMD floating point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating point form so that the registers each hold two floating point row data values; and (c) using SIMD floating point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-DCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-DCT, two columns are preferably processed in parallel using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating point format.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to systems and methods for performing discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) operations. The invention also relates to digital video compression and decompression, and more particularly to a video encoder and decoder for performing two-dimensional discrete cosine transform and/or two-dimensional inverse discrete cosine transform using single-instruction, multiple-data (SIMD) instructions to obtain improved efficiency.

2. Description of the Related Art

DSP theory provides a host of tools for the analysis and representation of signal data. The discrete cosine transform and its inverse are among the more ubiquitous of these tools in multimedia applications. The discrete cosine transform (DCT) of a discrete function ƒ(j), j=0, 1, . . . , N−1 is defined asF⁡(k)=2⁢c⁡(k)N⁢∑j=0N-1⁢f⁡(j)·cos⁡[(2⁢j+1)⁢k⁢⁢π2⁢N],
where k=0, 1, . . . , N−1, andc⁡(k)={1/2for⁢⁢k=01for⁢⁢k≠0}.
The inverse discrete cosine transform (IDCT) is defined byf⁡(j)=∑k=0N-1⁢c⁡(k)⁢F⁡(k)⁢cos⁡[(2⁢j+1)⁢k⁢⁢π2⁢N],
where j=0, 1, . . . , N−1.

The discrete cosine transform may be used in a wide variety of applications and allows an arbitrary input array size. However, the straightforward DCT algorithm is often prohibitively time-consuming especially when executed on general purpose processors. In 1977, Chen et al. disclosed an efficient algorithm for performing the DCT in an article entitled “A Fast Computational Algorithm for the Discrete Cosine Transform”, published in IEEE Transactions on Communications, Vol. COM-25, No. 9, September 1977, authored by Wen-Hsiung Chen, C. Harrison Smith and S. C. Fralick, which is hereby incorporated by reference. Fast DCT algorithms such as that disclosed by Chen et al. are significantly more efficient than the straightforward DCT algorithm. Nevertheless, there remains room for improvement, particularly when the algorithm is employed in specific circumstances.

Traditional x86 processors are not well adapted for the types of calculations used in signal processing. Thus, signal processing software applications on traditional x86 processors have lagged behind what was realizable on other processor architectures. There have been various attempts to improve the signal processing performance of x86-based systems. For example, microcontrollers optimized for digital signal processing computations (DSPs) have been provided on plug-in cards or the motherboard. These microcontrollers operated essentially as hardwired coprocessors enabling the system to perform signal processing functions.

As multimedia applications become more sophisticated, the demands placed on computers are redoubled. Microprocessors are now routinely provided with enhanced support for these applications. For example, many processors now support single-instruction multiple-data (SIMD) commands such as MMX instructions. Advanced Micro Devices, Inc. (hereinafter referred to as AMD) has proposed and implemented 3DNow!™, a set of floating point SIMD instructions on x86 processors starting with the AMD-K6®-2. The AMD-K6®-2 is highly optimized to execute the 3DNow!™ instructions with minimum latency. Software applications written for execution on the AMD-K6®-2 may use these instructions to accomplish signal processing functions and the traditional x86 instructions to accomplish other desired functions.

The 3DNow! instructions, being SIMD commands, are “vectored” instructions in which a single operation is performed on multiple data operands. Such instructions are very efficient for graphics and audio applications where simple operations are repeated on each sample in a stream of data. SIMD commands invoke parallel execution in superscalar microprocessors where pipelining and/or multiple execution units are provided.

Vectored instructions typically have operands that are partitioned into separate sections, each of which is independently operated upon. For example, a vectored multiply instruction may operate upon a pair of 32-bit operands, each of which is partitioned into two 16-bit sections or four 8-bit sections. Upon execution of a vectored multiply instruction, corresponding sections of each operand are independently multiplied. So, for example, the result of a vectored multiplication of [3;5] and [7;11] would be [21;55]. To quickly execute vectored multiply instructions, microprocessors such as the AMD-K6®-2 use a number of multipliers in parallel.

FIG. 1illustrates one embodiment of a representative computer system100such as the AMD-K6®-2 which is configured to support the execution of general-purpose instructions and parallel floating-point instructions. Computer system100may comprise a microprocessor110, memory112, bus bridge114, peripheral bus116, and a plurality of peripheral devices P1–PN. Bus bridge114couples to microprocessor110, memory112and peripheral bus116. Bus bridge114mediates the exchange of data between microprocessor110, memory112and peripheral devices P1–PN.

Microprocessor110is a superscalar microprocessor configured to execute instructions in a variable length instruction set. A subset of the variable length instruction set is the set of SIMD (simultaneous-instruction multiple-data) floating-point instructions. Microprocessor110is optimized to execute the SIMD floating-point instructions in a single clock cycle. In addition, the variable length instruction set includes a set of x86 instructions (e.g. the instructions defined by the 80486 processor architecture).

Memory112stores program instructions which control the operation of microprocessor110. Memory112additionally stores input data to be operated on by microprocessor110, and output data generated by microprocessor110, in response to the program instructions. Peripheral devices P1–PN are representative of devices such as network interface cards (e.g. Ethernet cards), modems, sound cards, video acquisition boards, data acquisition cards, external storage media, etc. Computer system100may be a personal computer, a laptop computer, a portable computer, a television, a radio receiver and/or transmitter, etc.

FIG. 2illustrates one embodiment for microprocessor110. Microprocessor110may be configured with 3DNow!™ and MMX® technologies. Microprocessor110may comprise bus interface unit202, predecode unit204, instruction cache206, decode unit208, execution engine210, and data cache214. Microprocessor110may also include store queue212and an L2 cache216. Additionally, microprocessor110may include a branch prediction unit and a branch resolution unit (not shown) to allow efficient speculative execution.

Predecode unit204may be coupled to instruction cache206, which stores instructions received from memory112via bus interface unit202and predecode unit204. Instruction cache206may also contain a predecode cache (not shown) for storing predecode information. Decode unit208may receive instructions and predecode information from instruction cache206and decode the instructions into component pieces. The component pieces may be forwarded to execution engine210. The component pieces may be RISC operands. (Microprocessor110may be RISC-based superscalar microprocessor). RISC ops are fixed-format internal instructions, most of which are executable by microprocessor110in a single clock cycle. RISC operations may be combined to form every function of the x86 instruction set.

Execution engine210may execute the decoded instructions in response to the component pieces received from decode unit208. As shown inFIG. 3, execution engine210may include a scheduler buffer302coupled to receive input from decode unit208. Scheduler buffer302may be configured to convey decoded instructions to a plurality of execution pipelines306–314in accordance with input received from instruction control unit304. Execution pipelines306–314are representative, and in other embodiments, varying numbers and kinds of pipelines may be included.

Instruction control unit304contains the logic necessary to manage out of order execution of instructions stored in scheduler buffer302. Instruction control unit304also manages data forwarding, register renaming, simultaneous issue and retirement of RISC operations, and speculative execution. In one embodiment, scheduler buffer302holds up to 24 RISC operations at one time. When possible, instruction control unit304may simultaneously issue (from buffer302) a RISC operation to each available execution unit.

Execution pipelines306-315may include load unit306, store unit308, X pipeline310, Y pipeline312, and floating point unit314. Load unit306may receive input from data cache214, while store unit308may interface to data cache214via a store queue212. Store unit308and load unit306may be two-staged pipeline designs. Store unit308may perform memory writes. For a memory write operation, the store unit308may generate a physical address and the associated data bytes which are to be written to memory. These results (i.e. physical address and data bytes) may be entered into the store queue212. Memory read data may be supplied by data cache214or by an entry in store queue212(in the case of a recent store).

X pipeline310and Y pipeline312may each include a combination of integer, integer SIMD (e.g. MMX®), and floating-point SIMD (e.g. 3DNow!™) execution resources. Some of these resources may be shared between the two register pipelines. As suggested byFIG. 3, load unit306, store unit308, and pipelines310,312may be coupled to a set of registers316from which these units are configured to read source operands. In addition, load unit306and pipelines310,312may be configured to store destination result values to registers316. Registers316may include physical storage for a set of architected registers.

Floating point unit314may also include a set of floating point registers (not shown separately). Floating point unit314may execute floating point instructions (e.g. x87 floating point instructions, or IEEE 754/854 compliant floating point instructions) designed to accelerate the performance of scientific software. Floating point unit314may include an adder unit, a multiplier unit, and a divide/square-root unit, etc. Floating point unit314may operate in a coprocessor-like fashion, in which decode unit208directly dispatches the floating point instructions to unit314. The floating point instructions may still be allocated in scheduler buffer302to allow for in-order retirement of instructions. Unit314and scheduler buffer302may communicate to determine when a floating point instruction is ready for retirement.

Pipelines310,312include resources that allow them to perform scalar integer operations, SIMD integer operations, and SIMD floating point operations. The SIMD integer operations that are performed correspond to the MMX® instruction set architecture, and the SIMD floating point operations that are performed correspond to the 3DNow!™ instruction set. Any pair of operations which do not require a common resource may be simultaneously executed in the two pipelines (i.e. one operation per pipeline). Thus, the maximum rate of execution for the two pipelines taken together is equal to two operations per cycle.

Registers316may include registers which are configured to support packed integer and packed floating-point operations (e.g. registers denoted MM0through MMn which conform to the 3DNow!™ and MMX® instruction set architectures). In one embodiment of microprocessor110, there are eight MM registers, i.e. MM0through MM7, each having a 64 bit storage capacity. Two 32-bit floating point operands may be loaded into each MM register in a packed format. For example, suppose register MM0has been loaded with floating-point operands A and B, and register MM1has been loaded with floating-point operands C and D. In shorthand notation, this situation may be represented by the expressions MM0=[A:B] and MM1=[C:D], where the first argument in a bracketed pair represents the high-order 32 bits of a quadword register, and the second argument represents the low-order 32 bits of the quadword register. The 3DNow!™ instructions invoke parallel floating-point operations on the contents of the MM registers. For example, the 3DNow!™ multiply instruction given by the assembly language construct“pfmul MM0,MM1”
invokes a parallel floating-point multiply on corresponding components of MM0and MM1. The two floating-point resultant values of the parallel multiply are stored in register MM0. Thus, after the instruction has completed execution, register MM0may be represented by the expression MM0=[A*C:B*D]. As used herein, the assembly language construct“pfxxx MMdest, MMsrc”
implies that a 3DNow!™ operation corresponding to the mnemonic pfxxx uses registers MMdest and MMsrc as source operands, and register MMdest as a destination operand.

The assembly language construct“pfadd MM0,MM1”
invokes a parallel floating-point addition on corresponding components of registers MM0and MM1. Thus, after this instructions has completed execution, register MM0may be represented by the expression MM0=[A+C:B+D].

It is noted that alternate embodiments of microprocessor110are contemplated where the storage capacity of an MM register allows for more than two floating-point operands. For example, an embodiment of microprocessor110is contemplated where the MM registers are configured to store four 32-bit floating-point operands. In this case, the MM registers may have a size of 128-bits.

Multimedia applications demand increasing amounts of storage and transmission bandwidth. Thus, multimedia systems use various types of audio/visual compression algorithms to reduce the amount of necessary storage and transfer bandwidth. In general, different video compression methods exist for still graphic images and for full-motion video. Intraframe compression methods are used to compress data within a still image or single frame using spatial redundancies within the frame. Interframe compression methods are used to compress multiple frames, i.e., motion video, using the temporal redundancy between the frames. Interframe compression methods are used exclusively for motion video, either alone or in conjunction with intraframe compression methods.

Intraframe or still image compression techniques generally use frequency domain techniques, such as the two-dimensional discrete cosine transform (2D-DCT). The frequency domain characteristics of a picture frame generally allow for easy removal of spatial redundancy and efficient encoding of the frame. One video data compression standard for still graphic images is JPEG (Joint Photographic Experts Group) compression. JPEG compression is actually a group of related standards that use the discrete cosine transform (DCT) to provide either lossless (no image quality degradation) or lossy (imperceptible to severe degradation) compression. Although JPEG compression was originally designed for the compression of still images rather than video, JPEG compression is used in some motion video applications.

In contrast to compression algorithms for still images, most video compression algorithms are designed to compress full motion video. As mentioned above, video compression algorithms for motion video use a concept referred to as interframe compression to remove temporal redundancies between frames. Interframe compression involves storing only the differences between successive frames in the data file. Interframe compression stores the entire image of a key frame or reference frame, generally in a moderately compressed format. Successive frames are compared with the key frame, and only the differences between the key frame and the successive frames are stored. Periodically, such as when new scenes are displayed, new key frames are stored, and subsequent comparisons begin from this new reference point. The difference frames are further compressed by such techniques as the 2D-DCT. Examples of video compression which use an interframe compression technique are MPEG (Moving Pictures Experts Group), DVI and Indeo, among others.

MPEG compression is based on two types of redundancies in video sequences, these being spatial, which is the redundancy in an individual frame, and temporal, which is the redundancy between consecutive frames. Spatial compression is achieved by considering the frequency characteristics of a picture frame. Each frame is divided into non-overlapping blocks, and each block is transformed via the 2D-DCT. After the transformed blocks are converted to the “DCT domain”, each entry in the transformed block is quantized with respect to a set of quantization tables. The quantization step for each entry can vary, taking into account the sensitivity of the human visual system (HVS) to the frequency. Since the HVS is more sensitive to low frequencies, most of the high frequency entries are quantized to zero. In this step where the entries are quantized, information is lost and errors are introduced to the reconstructed image. Run length encoding is used to transmit the quantized values. To further enhance compression, the blocks are scanned in a zig-zag ordering that scans the lower frequency entries first, and the non-zero quantized values, along with the zero run lengths, are entropy encoded.

As discussed above, temporal compression makes use of the fact that most of the objects remain the same between consecutive picture frames, and the difference between objects or blocks in successive frames is their position in the frame as a result of motion (either due to object motion, camera motion or both). This relative encoding is achieved by the process of motion estimation. The difference image as a result of motion compensation is further compressed by means of the 2D-DCT, quantization and RLE entropy coding.

When an MPEG decoder receives an encoded stream, the MPEG decoder reverses the above operations. Thus the MPEG decoder performs inverse scanning to remove the zig zag ordering, inverse quantization to de-quantize the data, and the inverse 2D-DCT to convert the data from the frequency domain back to the pixel domain. The MPEG decoder also performs motion compensation using the transmitted motion vectors to re-create the temporally compressed frames.

Computation of the 2D-DCT as well as computation of the two-dimensional inverse discrete cosine transform (2D-IDCT) in multimedia systems generally require a large amount of processing. For example, hundreds of multiplication (or division) operations as well as hundreds of addition (or subtraction) operations may be required to perform the 2D-DCT or IDCT upon a single 8×8 array. Such computational requirements can be extremely time-consuming and resource intensive when hundred of thousands of 8×8 blocks are processed every second.

A new system and method are desired for efficiently computing the forward and/or inverse discrete cosine transform. It is particularly desirable to provide a system for computing the two-dimensional forward and/or inverse discrete cosine transform which reduces computational requirements in a general purpose computer system.

SUMMARY OF THE INVENTION

The problems discussed above are in large part addressed by a method of performing a discrete cosine transform (DCT) using a microprocessor having an instruction set that includes SIMD floating point instructions. In one embodiment, the method includes: (1) receiving a block of integer data; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating point form so that the registers each hold two floating point row data values; and (c) using SIMD floating point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-DCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-DCT, two columns are preferably processed in parallel using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating point format.

TERMINOLOGY

As used herein, the term multimedia instruction refers to the above described packed integer operations (e.g. operations such as those defined by the MMX instructions within the x86 instruction set) and to packed floating point operations optimized for three dimensional graphics calculations and/or physics calculations (e.g. operations such as those defined by the 3DNow! instructions). These instructions may be defined to operate, for example, on two 32-bit floating point numbers packed into a given multimedia register. Other packed floating point formats may be used as well.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The DCT and IDCT transforms discussed in the background can be extended to two dimensions. This may be done, for example, on a flat image to identify the spatial frequency components of the image. Typically, the image is expressed in terms of small picture elements, termed pixels, laid out in a rectangular grid and each assigned a single color value. (The color value may be expressed in terms of multiple components such as Red, Green and Blue intensities, but this is easily accounted for by repeating the process disclosed below for each component). To minimize hardware requirements, the image is generally divided into small, square blocks of pixels (e.g. 8×8 pixels forms a block), termed macroblocks, and the two-dimensional transforms are applied to each block separately.

Since the DCT and IDCT transforms are linear, when they are extended to two dimensions the horizontal and vertical transforms can be performed independently and in any order.FIG. 5shows a flowchart of one method for performing any linear transform in two dimensions. In the ensuing discussion, the method is applied to a two-dimensional block of data having Rmax+1 rows and Cmax+1 columns (i.e. the row indices range from 0 to Rmax, and the column indices range from 0 to Cmax). This method will be described with references toFIGS. 4A–4B, where the configuration of data is shown at various points in the flowchart. For clarity in these figures, the number of rows and columns are assumed to equal eight, but other values are also contemplated.

It is contemplated that the method ofFIG. 5may take the form of a subroutine. When this subroutine is called, it would be provided with an input block of data402such as that shown inFIG. 4A. Data block X has components XRC, where index R indicates the row number and index C indicates the column number. In the context of the DCT and IDCT transforms, each component XRCis preferably a 16-bit valued integer.

InFIG. 5, row index R is initialized to 0 in block502. Blocks504,506, and508form a loop in which one-by-one, the rows of data block X are individually transformed. In block504, the transform is performed on the current row as determined by row index R. In block506, the row index R is compared to Rmax, the highest row index in the data block. If the last row has not yet been transformed, then in block508the row index R is incremented and the loop is repeated until each row has been transformed.

As part of the DCT or IDCT transform being performed in block504, the data block components XRCare loaded (arrow404inFIG. 4A) into 64-bit processor registers and preferably converted to 32-bit floating point numbers (indicated by the expanded width of the components inFIG. 4A). It is expected that performing the transform using single-precision floating point operations will provide much greater accuracy than that obtainable using integer operations. The initial data block402is assumed to be packed 16-bit integers. InFIG. 4A, the register loading404may be accomplished as follows:

movqmm0, [InpBfr];put element X00 in register 0movqmm1, [InpBfr+14];put element X07 in register 1punpckldqmm1, mm0;put element X00&07 into reg 1pi2fwmm1, mm1;convert X00&07 to floating ptmovqmm0, [InpBfr+2];put element X01 in register 0movqmm2, [InpBfr+12];put element X06 in register 2punpckldqmm2, mm0;put element X01&06 into reg 2pi2fwmm2, mm2;convert X01&06 to floating ptmovqmm0, [InpBfr+4];put element X02 in register 0movqmm3, [InpBfr+10];put element X05 in register 3punpckldqmm3, mm0;put element X02&05 into reg 3pi2fwmm3, mm3;convert X02&05 to floating ptmovqmm0, [InpBfr+6];put element X03 in register 0movqmm4, [InpBfr+8];put element X04 in register 4punpckldqmm4, mm0;put element X03&04 into reg 4pi2fwmm4, mm4;convert X03&04 to floating pt
In words, the integer values are separately loaded into individual registers, then pairs of integer values are formed in each register, and finally the integer values are converted to 32-bit floating point values. This requires no more than an average of two operations per value.

After the initial conversion to 32-bits, the transform is carried out in four stages, each stage consisting of multiple pair-wise weighted rotations followed by reordering of the register values. InFIG. 4A, the weighted rotations are shown as “butterflys”. Referring momentarily toFIG. 6, a weighted rotation is an operation on two values X0, X1to produce two new values Y0, Y1according to the relationship:
Y0=A*X0+B*X1
Y1=−B*X0+A*X1
Returning toFIG. 4A, the first stage's four weighted rotations406may each be performed as follows:

movqmm5, Const—W0—W7;put B&A coefficients in reg 5. . .. . .;intervening instruction(s) toallow for load latencypswapmm0, mm1;put elements X07&00 in reg 0pfmulmm1, mm5;mm1=[B*X0;A*X1]pfmulmm0, mm5;mm0=[B*X1;A*X0]pfpnaccmm1, mm0;mm1=[A*X0+B*X1;−B*X0+A*X1]
In words, the coefficients are loaded into a register, and while that is happening a copy of the floating point values is made into a second register with the order of the values reversed. The original and reversed values are then vector multiplied by the coefficients, and then accumulated by the pfpnacc operation. This operation causes the high end of the destination register to be subtracted from the low end of the destination register, and stores the sum of the high and low end of the source register into the high end of the destination register. Note that the movq instruction may be performed before the pfpnacc instruction of the previous weighted rotation, so that the load latency effect is minimized.

The reordering indicated by arrow408can then be performed as follows:

This completes the first stage ofFIG. 4A. The weighted rotations410,414, and418are similarly performed, as are the reorderings412and416. As reordering420is performed, the row-transform components, denoted XRC′, are written to an intermediate buffer422(TmpBfr). Block504ofFIG. 5includes steps404–420, and accordingly, these steps are repeated for each row of the input block.

Returning toFIG. 5, after all the rows have been transformed, column index C is initialized to 0 in block510. Blocks512,514, and516form a second loop in which the columns of the intermediate result buffer are transformed two at a time. In block512, the transform is performed on the current two columns as indicated by the column index C and C+1. In block514, the column index C+1 is compared to Cmax, the largest column index in the data block. If the last column has not yet been transformed, then in block516the column index is incremented and the loop is repeated until each column has been transformed.

When the transform in block512is the subject DCT or IDCT transform, the operations are preferably performed using floating point operations. To this end, the intermediate result buffer422shown inFIGS. 4A and 4Bpreferably stores the row-transform components XRC′ in floating point form to avoid extra conversions between integer and floating point form. As the row-transform components are loaded into processor registers two columns at a time, no conversion is necessary.

The column transform block512includes steps424–440shown inFIG. 4B. Loading step424can be performed as follows:

movqmm2, [TmpBfr];put element X01&00 in reg 2movqmm3, [TmpBfr+112];put element X71&70 in reg 3
Unfortunately there are not enough registers for all the values to be loaded simulatneously. Consequently, the ordering424and reorderings428,432,436of the values inFIG. 4Bare not reflected in the arrangement of values in the registers. Load operations for the weighted rotation instructions will retrieve the values as necessary.

The first stage's four weighted rotations426may each be performed as follows (the load step424is included):

This completes the first stage ofFIG. 4B. The weighted rotations430,434and438are similarly performed. As the weighted rotations438are performed, the column transform components are converted to 16-bit integer form and written440to output buffer442. This may be accomplished in the following manner:

Block512ofFIG. 5includes steps424–440, and accordingly, these steps are repeated for each adjacent pair of columns. After the column transform is complete, the output buffer contains the now-two-dimensional transform components XRC″ in 16-bit integer form. The contents of this buffer are returned from the subroutine.

It is noted that several variations to the method ofFIG. 5are contemplated. For example, the column transforms may be performed before the row transforms. The rows may be transformed in any order, as may the column pairs. The intermediate result buffer may be written in column order and accessed in row order rather than written in row order and accessed in column order. The description ofFIG. 5is not intended to exclude such variations.

It is further noted that the transform methods described herein may be performed by a computer system as shown inFIGS. 1–3or a variant thereof. Specifically, the methods may be implemented in software stored in memory112and executed by microprocessor110to process multimedia data for presentation of images via a display or sound via a speaker. The transform methods described herein may be used to transform data indicative of images or sounds into a form more suitable for storage and transmission.

In various embodiments, the transform methods described in conjunction withFIGS. 4A–6may be embodied by software instructions received, sent or stored upon a carrier medium. Generally speaking, a carrier medium may include storage media or memory media such as magnetic or optical media, e.g., disk or CD-ROM, volatile or non-volatile media such as RAM (e.g. SDRAM, DDR SDRAM, RDRAM, SRAM, etc.), ROM, etc. as well as transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as network and/or a wireless link.

The following listing presents a subroutine for a two-dimensional DCT transform on 8×8 blocks of 16-bit-valued pixels, and a subroutine for the inverse two-dimensional DCT transform. These programs use the parallel computation methods described herein that advantageously exploit the structure and instruction set of modern processors to achieve a significantly improved performance.

These subroutines use various instructions that are described in greater detail in AMD's “3DNow! Technology Manual” and AMD's “AMD Extensions to the 3DNow! and MMX Instruction Sets Manual”, both of which are incorporated herein by reference.