Imager element, device and system with recessed transfer gate

An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer transistor having a recessed gate. The recessed gate is configured to couple the collection region to the floating diffusion region so that collected charge is transferred during activation. The recessed gate has an effective gate length greater than a physical gate length.

FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductor devices and more particularly, to a CMOS imager device having a transfer gate.

BACKGROUND OF THE INVENTION

The semiconductor industry currently uses different types of semiconductor-based imagers, including charge-coupled devices (CCD) and CMOS imager devices. Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low-cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits is beneficial for many digital applications.

A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, or a photodiode for accumulating photo-generated charge in a doped portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photo-generated charges, typically from a doped floating diffusion region, and produces an output signal which is periodically read-out through an optional row select access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the floating diffusion region or the floating diffusion region may be directly connected to or part of he photoconversion device. A transistor is also conventionally provided for resetting the diffusion region to a predetermined charge level before it receives the photoconverted charges.

Exemplary CMOS imaging circuits, processing steps for fabrication thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the foregoing patents are hereby incorporated by reference herein in their entirety.

In a conventional CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of signals representing the reset state and a pixel charge signal. The photo-generated charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node through a transfer transistor. The charge at the floating diffusion node is converted to a pixel output voltage by a source follower output transistor.

As illustrated inFIG. 1, a known CMOS active pixel sensor (APS)10design used in many applications contains a photodiode12for producing charges which are gated by a transfer transistor14from the photodiode12for storage at a diffusion region16. The transfer transistor14is illustrated as having an effective electrical length L for inhibiting current leakage of the photo-generated charge from the photodiode12to the diffusion region16when the transfer transistor14is inactive.

While CMOS sensors excel in photon-to-charge conversion under moderate lighting conditions, CMOS sensors suffer in low light conditions. CMOS sensor sensitivity to light is decreased because part of each pixel18is partially occupied with circuitry20other than the photodiode12. The percentage of a pixel devoted to collecting light is called the pixel's “fill factor.” While charge-coupled devices (CCDs) have nearly a 100% fill factor, CMOS sensors have much less. The lower the fill factor, the less sensitive the sensor becomes.

Another known problem with the conventional CMOS APS design is undesirable charge leakage that occurs between the photodiode and the diffusion region. As advances in resolution of imaging devices cause reductions in device dimensions, the charge leakage problem becomes even more pronounced. Furthermore, the charge leakage problem through the transfer transistor may not simply be addressed by proportionally increasing the area within the pixel that is allocated to the transfer transistor because the fill factor of the pixel is even further reduced.

There is a need, therefore, to have a CMOS sensor that exhibits reduced charge leakage between the photodiode and the floating diffusion region. There is also a need to have a transfer transistor that limits the amount of leakage between the photodiode and the diffusion region in a CMOS sensor while retaining an acceptable fill factor for the pixel.

DETAILED DESCRIPTION OF THE INVENTION

The terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” In the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium, or gallium arsenide, among others.

The term “pixel” refers to a picture element unit cell containing a photosensor and transistors for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein.

A sensor pixel, an image sensor element, an imaging device and an electronic imager system with a recessed transfer gate are disclosed, as is a method of fabricating an imager sensor pixel. In one embodiment of the present invention, an image sensor pixel includes a collection region and a floating diffusion region. The image sensor pixel further includes a transfer transistor including a recessed gate configured for coupling the collection region to the floating diffusion region for transferring collected charge when activated.

In another embodiment of the present invention, an image sensor element includes a transfer transistor including a first source/drain region including a charge collection region for collecting charge generated by light. The transfer transistor further includes a second source/drain region including a floating diffusion region. A gate is configured for coupling the collection region to the floating diffusion region to transfer the collected charge when the recessed gate is activated. The transfer transistor further includes a gate configured to include a longer effective gate length than the physical gate length.

In a further embodiment of the present invention, an imaging device includes a plurality of charge collection regions supported by a substrate and a corresponding plurality of floating diffusion regions. The imaging device further includes a corresponding plurality of transfer transistors including a corresponding plurality of recessed gates for transferring stored charge from the plurality of charge collection regions to the plurality of floating diffusion regions.

In yet another embodiment of the present invention, an electronic imager system includes an imaging device and at least one input/output device. The imaging device includes a plurality of image sensor pixels each including a recessed transfer gate for transferring stored charge from a plurality of charge collection regions to a plurality of floating diffusion regions in the plurality of image sensor pixels.

In a yet further embodiment of the present invention, a method of forming an imager sensor pixel is described. The method includes forming a collection region and forming a floating diffusion region. The method further includes forming a transfer transistor including a recessed gate configured for coupling the collection region to the floating diffusion region to transfer collected charge when activated.

FIG. 2illustrates a sectional view of a portion of a CMOS image sensor pixel40employing an n-type doped floating diffusion region42. The CMOS image sensor pixel40generally comprises a charge collection region44of a photodiode46for collecting charges generated by light incident on the pixel, and a transfer transistor48having a recessed gate50for transferring photoelectric charges from the charge collection region44to the floating diffusion region42. The floating diffusion region42is electrically connected via conductor52to a gate54of an output source follower transistor56. The pixel40also includes a reset transistor58having a gate60for resetting the floating diffusion region42to a predetermined voltage before charge is transferred thereto from the photodiode46. During the reading of a pixel, a source follower transistor56receives at the gate54an electrical signal from the floating diffusion region42and a row select transistor62selectively outputs a signal from the source follower transistor56to a column line64in response to a decoded row address driver signal applied to a gate66of the transistor62.

By way of example and not limitation, the pixel40ofFIG. 2employs a pinned photodiode46having charge collection region44for converting photons to electrical charge on a semiconductor substrate68. The depicted pinned photodiode46is termed such since the potential in the photodiode46is pinned to a constant value when the photodiode46is fully depleted. The pinned photodiode46has a photosensitive p-n junction region comprising a p+ type region70and an n-type photodiode charge collection region44within a p-type region72. The p-type region72is formed within semiconductor substrate68. The p+ region70and the p-type region72cause the n-type photodiode charge collection region44to be fully depleted at a pinning voltage. Impurity doped source/drain regions having n-type conductivity are provided about the transistor gates50and60. The floating diffusion region42adjacent to transfer transistor48and reset transistor58is a common source/drain region for the transfer transistor48having recessed gate50and the reset transistor58having gate60.

In a conventional CMOS image sensor, trench isolation regions74formed in a p-well active layer75and adjacent to the charge collection region44are used to isolate the pixels40. The stacked configuration of gate60for the reset transistor58may be formed before or after the trench isolation regions74are formed. The order of these preliminary process steps may be varied as is required for convenience or for a particular process flow.

A transparent insulating layer76is conventionally formed over the pixel40. Conventional processing methods are then carried out to form, for example, metal conductor52in the insulating layer to provide an electrical connection/contact to the floating diffusion region42, and other wiring to connect gate lines and other connections in pixel40. For example, the entire surface of substrate68may be covered with a passivation layer of e.g., silicon dioxide, BSG, PSG, or BPSG, as a transparent insulating layer76, which is planarized and etched to provide contact holes, which are then metalized to provide contacts to a diffusion node78.

In conventional CMOS image sensors, electrons are generated from light incident externally and accumulate in the n-type photodiode charge collection region44. These charges are transferred to the floating diffusion region42by the recessed gate50of the transfer transistor48. The source follower transistor56produces an output signal from the transferred charges.

During reading of the pixel, a maximum output signal is proportional to the number of electrons extracted from the n-type photodiode charge collection region44. The maximum output signal increases with increased electron capacitance or acceptability of the photodiode. The electron capacity of pinned photodiodes typically depends on doping levels and the dopants implanted to form regions70,72, and44. In particular, regions70and44dominate the capacitance of pinned photodiode46. Accordingly, increasing the capacitance of pinned photodiode46is useful to allow capture of greater levels of photoconverted charges.

The use of a recessed gate50for transfer transistor48results in an increased effective gate length Leffwhile reduction in the physical gate length Lphy. An increase in the effective gate length Leffof recessed gate50results in reduced charge leakage between the photodiode46and the floating diffusion region42when the transfer transistor48is in the off-state. Furthermore, the reduction in the physical gate length Lphyof recessed gate50results in the ability to either increase the fill factor of the pixel40by increasing the size of the photodiode46or decreasing the overall size of the pixel40to accommodate greater density or reduction in overall sensor array dimensions.

Transfer transistor48is constructed within the semiconductor substrate68and includes recessed gate50extending within the substrate68. A dielectric material80is formed between the recessed gate50and the substrate68with the transistor's source/drain regions including the charge collection region44and the floating diffusion region42. When activated, a channel region82having an effective length of Leffextends around a lowermost portion of the recessed gate50and interconnects the charge collection region44and the floating diffusion region42with one another.

A benefit of using a recessed gate as opposed to a non-recessed gate is the effective lengthening of the channel region82of the transfer transistor48as a result of the channel extending around a recessed portion of the recessed gate50. Such an effective lengthening of the channel region82reduces short-channel effects for the transfer transistor48as well as provides for an improved connection between the charge collection region44and transfer transistor48without requiring a significant angular implant for the formation of the charge collection region44. Exemplary processing steps for the formation of recessed gates are described, for example, in U.S. Pat. No. 6,844,591 to Tran, the disclosure of the foregoing patent being hereby incorporated by reference herein in its entirety.

FIG. 3illustrates a sectional view of a portion of a CMOS image sensor pixel40′, in accordance with another embodiment of the present invention. One of the challenges in fabricating integrated circuits is the proper alignment of the various levels of a structure to facilitate proper operation. One critical alignment occurs between gate areas and their corresponding source/drain regions. In the present embodiment of the invention, the illustrated portion of pixel40′ includes a transfer transistor48′ comprising a recessed gate50′.

Recessed gate50′ includes an extended portion86that extends above an upper surface to enable the formation of spacers84about the extended portion86of recessed gate50′. Spacers84enable a self-alignment process for the formation of a photodiode46′ and a floating diffusion region42′ in the source/drain regions of transfer transistor48′. The dimensions of spacers84may be adjusted according to specific processes to reduce the need for angled implantation of the charge collection region44′ as required in the formation of conventional collection regions adjacent to non-recessed gates. Other structures of pixel40′ including the reset transistor, the source follower transistor, trench isolation regions and the transparent insulating layer may be formed as described hereinabove.

FIG. 4is a sectional view of a portion of a CMOS image sensor pixel140, in accordance with another embodiment of the present invention. As described above with reference toFIG. 2, a CMOS image sensor pixel includes a reset transistor having a gate for resetting the floating diffusion region to a predetermined voltage before charge is transferred thereto from the photodiode. As fabrication processes utilize specific steps for forming the various devices, the present embodiment reuses existing processing steps for the formation of other similar devices.

Specifically inFIG. 4, the portion of CMOS image sensor pixel140utilizes existing processes for forming a transfer transistor48having a recessed gate50for the formation of a reset transistor158also having a recessed gate160which is formed using similar steps as those used to form the recessed gate transfer transistor in substrate168. When activated, the transfer transistor48, having a recessed gate50, transfers photoelectric charges from the charge collection region44to the floating diffusion region42. A diffusion node78provides a contact into the floating diffusion region42for sensing the transferred charge. Thereafter, reset transistor158having recessed gate160resets the floating diffusion region42to a predetermined voltage before a subsequent transfer of charge from the charge collection region44.

FIG. 5illustrates a block diagram for a CMOS imaging device100having a pixel array102incorporating pixels40,40′,140, constructed in the manner discussed above in relation toFIGS. 2-4. Pixel array102features a plurality of pixels arranged in columns and rows. The pixels of each row in pixel array102can all be turned on at the same time by a row select line and the pixels of each column are selectively output by a column select line. A plurality of row and column lines is provided for the entire pixel array102. The row lines are selectively activated by a row driver104in response to a row address decoder106and the column select lines are selectively activated by a column driver108in response to a column address decoder10. Thus, a row and column address is provided for each pixel.

The CMOS imaging device100is operated by a control circuit112which controls the row and column address decoders106,110for selecting the appropriate row and column lines for pixel readout, and the row and column drivers104,108which apply driving voltage to the drive transistors of the selected row and column lines. A memory114, e.g., a Flash memory or an SRAM, can be in communication with the pixel array102and control circuit112. A parallel-to-serial converter116can be in communication with the control circuit112.

Typically, the signal flow in the CMOS imaging device100would begin at the pixel array102upon receiving photo-input and generating a charge. The signal is output to a read-out circuit and then to an analog-to-digital conversion device. The digitized signal is transferred to a processor, then the parallel-to-serial converter116, and the serialized signal can be output from the imaging device to external hardware.

FIG. 6illustrates an electronic imager system, in accordance with an embodiment of the present invention. An electronic imager system200includes an imaging device100, illustrated inFIG. 5, as an input device to the electronic imager system200. The imaging device100may also receive control or other data from electronic imager system200. Examples of processor based systems, which may employ the imaging device100, include, without limitation, computer systems, camera systems, scanners, machine vision systems, vehicle navigation systems, video telephones, surveillance systems, auto focus systems, star tracker systems, motion detection systems, image stabilization systems, and others.

An electronic imager system200includes a central processing unit (CPU)202that communicates with various devices over a bus204. Some of the devices connected to the bus204provide communication into and out of the electronic imager system200, illustratively including an input/output (I/O) device206and imaging device100. Other devices connected to the bus204provide memory, illustratively including a random access memory (RAM)210, a hard drive212, and one or more removable memory devices, such as a floppy disk drive214, compact disk (CD) or digital video disk (DVD) drive216, Flash memory cards, etc. The imaging device100may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, in a single integrated circuit.

The processes and devices described above illustrate exemplary methods and devices out of many that may be used and produced according to the present invention. The above description and drawings illustrate embodiments which provide significant features and advantages of the present invention. It is not intended, however, that the present invention be strictly limited to the above-described and illustrated embodiments.

Although the present invention has been shown and described with reference to particular embodiments, various additions, deletions and modifications that will be apparent to a person of ordinary skill in the art to which the invention pertains, even if not shown or specifically described herein, are deemed to lie within the scope of the invention as encompassed by the following claims.