Controller for handling an abort command using a regeneration queue and operation method thereof

A controller for controlling a memory device includes: a command queue suitable for queuing two or more commands received from a host; a re-generation queue suitable for queuing, in response to an abort command for aborting an abort-target command, a re-generated command corresponding to a remaining command other than the abort-target command among the commands queued in the command queue; a processor suitable for resetting the command queue when queuing a command in the re-generation queue is completed, and queuing the re-generated command into the command queue.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority of Korean Patent Application No. 10-2019-0126614, filed on Oct. 14, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present invention relate to a controller for controlling a memory device.

2. Description of the Related Art

The computer environment paradigm has been transitioning to ubiquitous computing, which enables computing systems to be used anytime and anywhere. As a result, use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has rapidly increased. These portable electronic devices generally use a memory system having one or more memory devices for storing data. A memory system may be used as a main memory device or an auxiliary memory device of a portable electronic device.

Since they have no moving parts, memory systems provide advantages such as excellent stability and durability, high information access speed, and low power consumption. Examples of memory systems having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSD).

SUMMARY

Embodiments of the present invention are directed to a controller which ensures rapid processing of an abort command for a command queued therein, and a method for operating the controller.

In accordance with an embodiment of the present invention, a controller for controlling a memory device includes: a command queue suitable for queuing two or more commands received from a host; a re-generation queue suitable for queuing, in response to an abort command for aborting an abort-target command, a re-generated command corresponding to a remaining command other than the abort-target command among the commands queued in the command queue; a processor suitable for resetting the command queue when queuing a command in the re-generation queue is completed, and queuing the re-generated command into the command queue.

In accordance with another embodiment of the present invention, a method for operating a controller controlling a memory device includes: queuing two or more commands received from a host in a command queue; queuing, in response to an abort command for aborting an abort-target command, a re-generated command corresponding to a remaining command other than the abort-target command among the commands queued in the command queue; resetting the command queue when queuing a command in the re-generation queue is completed; and queuing the re-generated command into the command queue.

In accordance with another embodiment of the present invention, an operating method of a controller, the operating method includes: queueing first and second commands; generating, in response to an abort command for the second command, a third command including one or more sub-commands of the first command; removing the first and second commands; and controlling a memory device to perform an operation according to the third command.

DETAILED DESCRIPTION

Throughout the specification, reference to “an embodiment,” “another embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). Also, any open-ended transition term, such as “comprising,” “including” or the like, when used herein, does not preclude the existence or addition of one or more elements or operations in addition to those stated. Similarly, use of an indefinite article, i.e., “a” or “an,” is intended to mean one or more, unless the context clearly indicates that only one is intended.

Hereinafter, embodiments of the present invention are described in more detail with reference to the accompanying drawings.

FIG. 1is a block diagram illustrating a data processing system100in accordance with an embodiment of the present invention.

Referring toFIG. 1, the data processing system100may include a host102operatively coupled to a memory system110.

The host102may include any of various portable electronic devices such as a mobile phone, MP3 player and/or laptop computer, or any of various non-portable electronic devices such as a desktop computer, a game machine, a television (TV), and/or a projector.

The host102may include at least one operating system (OS), which may manage and control overall functions and operations of the host102, and provide operation between the host102and a user using the data processing system100or the memory system110. The OS may support functions and operations corresponding to the use purpose and usage of a user. For example, the OS may be divided into a general OS and a mobile OS, depending on the mobility of the host102. The general OS may be divided into a personal OS and an enterprise OS, depending on the environment of a user.

The memory system110may operate to store data for the host102in response to a request of the host102. Non-limiting examples of the memory system110include a solid state drive (SSD), a multi-media card (MMC), a secure digital (SD) card, a universal storage bus (USB) device, a universal flash storage (UFS) device, compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card and memory stick. The MMC may include an embedded MMC (eMMC), reduced size MMC (RS-MMC) and micro-MMC. The SD card may include a mini-SD card and micro-SD card.

The memory system110may be embodied by various types of storage devices. Examples of such storage devices may include, but are not limited to, volatile memory devices such as a dynamic random access memory (DRAM) and/or a static RAM (SRAM) and nonvolatile memory devices such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM or ReRAM) and/or a flash memory. The flash memory may have a 3-dimensional (3D) stack structure.

The host102may provide a command to the memory system110. The host102may provide another command to the memory system110even before a response to the command already provided to the memory system110is received. The memory system110may queue the commands received from the host102therein and perform command operations in the order that the commands are queued.

The memory system110may include a command buffer CMD_BUFFER that receives and buffers commands provided from the host102. The memory system110may include a command queue CMD_QUEUE that queues the commands that are buffered in the command buffer. Step S102ofFIG. 1represents an operation in which the memory system110moves a command buffered in the command buffer to a command queue CMD_QUEUE.FIG. 1illustrates a state in which the commands previously buffered in the command buffer have been moved to the command queue. As a result, first to third commands CMD1to CMD3are queued in the command queue. The memory system110may provide a response to the commands that are queued in the command queue to the host102and then remove the commands from the command queue.

The commands from the host102may include a normal command and an abort command. A normal command may refer to a command that the host102instructs the memory system110to perform a particular operation. Examples of a normal command include a read command, a write command, and the like. An abort command may refer to a command that the host102instructs the memory system110to abort one or more normal commands already provided.

The memory system110may ensure atomicity for commands provided from the host102. In other words, the memory system110may have to ensure successful processing of a normal command unless an abort command for the normal command is provided.

The processing of a command may mean that the memory system110perform an operation instructed by the command. For example, when the memory system110provides a response to a write command, all of the write data received from the host102in connection with the write command may have to be stored in the memory system110.

When the memory system110receives an abort command for a write command from the host102before providing a response to the write command, even though at least a portion of the write data is received from the host102associated with the write command, all the received data may have to be removed from the memory system110.

The memory system110may sequentially process the commands that are queued in the command queue according to a first-in-first-out (FIFO) scheme. The memory system110may allocate buffer resources to the corresponding commands to buffer data associated with the commands. The memory system110may improve operation performance by pre-allocating buffer resources corresponding to a command to be executed in the future as well as to the command that is currently being executed.

The host102may abort a command by providing an abort command to the memory system110after providing a normal command to the memory system110and before receiving a response to the normal command from the memory system110. Step S104ofFIG. 1represents an operation in which the host102provides the memory system110with an abort command ABORT_CMD2for a second command CMD2among the commands CMD1to CMD3that are queued in the command queue CMD_QUEUE. The shade shown in association with the second command CMD2ofFIG. 1indicates that the second command CMD2is an abort target command.

According to an embodiment of the present invention, when the memory system110queues a command queued in the command buffer CMD_BUFFER to the command queue CMD_QUEUE, the queuing order may be rearranged according to the priority order of the command. For example, the memory system110may arrange the commands in such a manner that the abort command is prioritized over a normal command. ABORT_CMD2may be processed ahead of the first to third commands that are queued earlier than ABORT_CMD2.

Also, when the memory system110removes only the second command from the command queue in response to ABORT_CMD2, the complexity and processing time of ABORT_CMD2imposed on the memory system110may increase.

In order to abort the second command, not only does the second command have to be removed from the command queue, but also the buffer resources allocated for the second command may have to be deallocated from the buffer. For example, the memory system110may have to perform an abort operation of examining whether buffer resources for storing data corresponding to the second command are allocated or not and, when the buffer resources are so allocated, marking data in the buffer resources that are already allocated for data corresponding to the second command as dummy data.

In the case of a high-performance memory system110using a multi-processor, the process of aborting a command may be very complicated. For example, the memory system110may include a host processor and a Flash Translation Layer (FTL) processor. The host processor may receive and queue a command from the host102and transfer or receive data associated with the command. The FTL processor may perform an operation corresponding to the queued command. When the host processor and the FTL processor are separated from each other, the memory system110may need to control the FTL processor to not perform an operation corresponding to a command aborted by the host processor. For example, an exclusion process may have to be implemented such that the FTL processor does not perform a command operation associated with the buffer resources marked as dummy data.

Also, when the memory system110receives an abort command for a plurality of commands, the abort process may have been performed for each of the commands. Therefore, when the memory system110removes only one command (an abort target command) from the command queue in response to the abort command, it is difficult to realize the performance characteristics indicated by the specification of the memory system110. That is, more time may be taken to abort the command in the memory system110than is allowed by the specification of the memory system110.

According to an embodiment of the present invention, the memory system110may move a re-generated command corresponding to a remaining command from the command queue CMD_QUEUE into a re-generation queue RE-GEN_QUEUE and may reset the command queue CMD_QUEUE and the buffer allocation in response to an abort command from the host102. The remaining command may refer to any command that is not an abort target of the abort command among the commands that are queued in the command queue.FIG. 1exemplifies that the second command CMD2is an abort target command and the first and third commands CMD1and CMD3are remaining commands. The re-generation queue may be a queue into which the remaining command(s) are moved to complete the processing for the remaining command(s) after resetting the command queue and the buffer allocation. The re-generated command may mean a command that is queued in the re-generation queue based on the remaining command(s). The re-generated command may or may not be the same as any of the remaining commands. The memory system110may generate a re-generated command by modifying the remaining command(s) if necessary. Step S106ofFIG. 1represents an operation of queuing a re-generated command corresponding to the first and third commands CMD1and CMD3(i.e., the remaining commands) to the re-generation queue in response to an abort command, e.g., ABORT_CMD2for the second command CMD2(i.e., the abort target command).

As a result of the reset operation, all the commands may be temporarily removed from the command queue. After the reset operation is completed, the memory system110may queue the re-generated command to the command queue. Step S108ofFIG. 1represents an operation of queuing a re-generated command corresponding to the first and third commands to the command queue. The memory system110may queue the commands of the re-generation queue to the command queue just as in the case of queuing the commands of the command buffer to the command queue. The memory system110may process re-generated commands that are queued in the command queue.

According to an embodiment of the present invention, when only some commands are aborted among a plurality of commands queued in the command queue, the remaining commands may be moved to re-generation queue, and the command queue and an allocated buffer resource may be all collectively reset. Therefore, it may take less time for the abort process and less system complexity than in the case where only some commands are removed from the command queue.

FIG. 2is a block diagram illustrating a memory system110in accordance with an embodiment of the present invention.

The memory system110may include a controller130and a memory device150. The memory device150may store data for the host102, and the controller130may control data storage into the memory device150.

The controller130and the memory device150may be integrated into a single semiconductor device. For example, the controller130and the memory device150may be integrated as one semiconductor device to constitute a solid state drive (SSD). When the memory system110is used as an SSD, the operating speed of the host102connected to the memory system110can be improved. In addition, the controller130and the memory device150may be integrated as one semiconductor device to constitute a memory card, such as a personal computer memory card international association (PCMCIA) card, compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC) including reduced size MMC (RS-MMC) and micro-MMC, secure digital (SD) card including mini-SD card, micro-SD card and SDHC card, or universal flash storage (UFS) device.

Non-limiting application examples of the memory system110include a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting/receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a Radio Frequency Identification (RFID) device, or one of various components constituting a computing system.

The memory device150may be a nonvolatile memory device that retains data stored therein even though power is not supplied. The memory device150may store data provided from the host102through a program operation, and provide data stored therein to the host102through a read operation. The memory device150may include a plurality of memory blocks, each of which may include a plurality of pages, and each of the pages may include a plurality of memory cells coupled to a word line. In an embodiment, the memory device150may be a flash memory. The flash memory may have a 3-dimensional (3D) stack structure.

The controller130may control the memory device150in response to a request from the host102. For example, the controller130may provide data read from the memory device150to the host102, and store data provided from the host102into the memory device150. For this operation, the controller130may control read, program and erase operations of the memory device150.

The controller130may include a host interface (I/F)132, an FTL processor (FCPU)134, a memory I/F136, a buffer manager138, and a memory140, all operatively coupled via an internal bus.

The host I/F132may be configured to process a command and data of the host102, and may communicate with the host102through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-e or PCIe), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), enhanced small disk interface (ESDI) and/or integrated drive electronics (IDE).

The host interface132may include a command buffer1322, a command queue1324, a re-generation queue1326, and a host processor (HCPU)1328.

The host processor1328may control overall operations of the host102and the memory system110exchanging commands and data. For example, the host processor1328may control the command buffer1322, the command queue1324, and the re-generation queue1326by driving firmware. The host processor1328may control a buffer manager138that manages a buffer for temporarily storing data exchanged with the host102.

When processing of a command received from the host102is completed, the host processor1328may provide the host102with a response corresponding to the command. For example, when all the write data associated with a write command are received from the host102in response to the write command, the host processor1328may provide a response to the host102indicating such receipt. The response to the write command may be provided when the write data are buffered in an internal buffer or when the write data are written in the memory device150. The host processor1328may provide a response to the host102after providing all the read data that are read from the memory device150to the host102in response to a read command. When an abort command is received, the host processor1328may abort the abort target command without providing a response to the abort target command.

The command buffer1322may correspond to the command buffer CMD_BUFFER described earlier with reference toFIG. 1, and the command buffer1322may buffer the commands received from the host102and provide a signal to the command queue1324. According to another embodiment of the present invention, the command buffer1322may be realized in hardware.

The command queue1324may correspond to the command queue CMD_QUEUE described earlier with reference toFIG. 1. The command queue1324may acquire and queue a command that is queued in the command buffer1322in response to a signal of the command buffer1322. The command queue1324may provide a command to the FTL processor134so that the memory system110performs an operation corresponding to the command of the host102. The command queue1324may remove the command when the host processor1328provides a response to the queued command to the host102. Although the command queue1324is illustrated as a constituent element separate from the host processor1328, the command queue1324may be realized as part of firmware that is driven by the host processor1328.

The re-generation queue1326may correspond to the re-generation queue RE-GEN_QUEUE described with reference toFIG. 1and it may queue a re-generated command corresponding to a remaining command in response to an abort command from the host102. Since the re-generation queue1326temporarily holds the re-generated command, the host processor1328may simply abort the abort target command by resetting all commands in the command queue1324and the allocated buffer resources. When the reset operation is completed, the re-generation queue1326may queue the queued re-generated command to the command queue1324.

The FTL processor134may perform a foreground operation in response to the queued command by driving firmware called FTL. For example, the FTL processor134may translate a logical address associated with the command into a physical address in response to a command received from the command queue1324. The FTL processor134may generate a command associated with the physical address and provide the generated command to the memory interface136.

Also, the FTL processor134may perform a background operation by driving the FTL. For example, the background operation may be any of a garbage collection (GC) operation, a wear leveling (WL) operation, a map flush operation, a bad block management operation, and the like.

The memory I/F136may serve as a memory/storage interface for interfacing the controller130and the memory device150such that the controller130controls the memory device150in response to a request from the host102. When the memory device150is a flash memory or specifically a NAND flash memory, the memory I/F136may be a flash controller. The memory I/F136may be connected to the memory device150through a channel including one or more signal lines.

The memory I/F136may provide the control signal to the memory device150based on the command received from the FTL processor134. The control signal may include a command and an address for controlling the memory device150. The memory interface134may provide data to the memory device150or receive data from the memory device150.

The memory140may serve as a working memory of the memory system110and the controller130, and store data for driving the memory system110and the controller130.

The memory140may be embodied by a volatile memory. For example, the memory140may be embodied by static random access memory (SRAM) or dynamic random access memory (DRAM). The memory140may be disposed within or externally to the controller130.FIG. 1exemplifies the memory140disposed within the controller130. In another embodiment, the memory140may be embodied by an external volatile memory having a memory interface transferring data between the memory140and the controller130.

The memory140may include a program memory, a data buffer, and the like. The program memory may store firmware driven by a processor such as the host processor1328, the FTL processor134, or the like. The data buffer may temporarily store write data received from the host102and to be written in the memory device150and read data read from the memory device150and to be transferred to the host102.

The buffer manager138may allocate a data buffer for temporarily storing data associated with the commands queued in the command queue1324under the control of the host processor1328. For example, the buffer manager138may divide the data buffer into a plurality of buffer areas and associate each area with an index. The buffer manager138may determine how many buffer areas are to be allocated to the command based on the size of the data associated with the command queued in the command queue1324, and allocate unallocated buffer areas with reference to their indices. The buffer manager138may pre-allocate buffer areas not only for a command currently being executed but also for a command to be executed in the future in order to improve the operating performance of the memory system110.

The host processor1328may provide a response to a command queued in the command queue1324to the host102based on the management information of the buffer manager138. For example, the host processor1328may provide the host102with a response that a write process is completed based on the information that all data are stored in the buffer area allocated for the associated write command. Even before the write data are programmed in the memory device150, the memory system110may provide the write data when the host102requests for the write data. As another example, the host processor1328may provide read data to the host102and then provide a response that a read process is completed to the host102based on the information that all the data are stored in the buffer area allocated for a read command.

FIGS. 3A to 4illustrate an operation of the memory system110in accordance with an embodiment of the present invention.

FIG. 3Ashows the state of memory system110before receiving an abort command.FIG. 3Aillustrates the states of the command buffer1322, the command queue1324, the re-generation queue1326, and the buffer manager138that are included in the memory system110. InFIG. 3A, other constituent elements that may form the memory system110are omitted.

FIG. 3Ashows the head and tail of each of the command buffer1322, the command queue1324, and the re-generation queue1326. Commands may be queued from head to tail in each queue or buffer.

The host processor1328may adjust the order among commands in such a manner that the command having the highest priority among the commands queued in the command queue1324is processed first. The host processor1328may sequentially process the command that is queued at the head of the command queue1324.

FIG. 3Aillustrates a state in which the first to fourth commands CMD1to CMD4are queued in the command queue1324. When the CMD1to CMD4are buffered in the command buffer1322, the host processor1328may acquire these commands and queue CMD1to CMD4in the command queue1324. In this example, once CMD1to CMD4are acquired from the command buffer1322and queued in the command queue1324, the command buffer1322may become empty. CMD1to CMD4may be queued in the order indicated by their numerical identifiers, i.e., from CMD1to CMD4, and the corresponding operations may be performed in that order. CMD1to CMD4may be normal commands.

The buffer manager138may allocate a data buffer (or area therein) for a command queued in the command queue1324. For example, the data buffer may include a plurality of buffer areas. The buffer manager138may map an index to each of the buffer areas.FIG. 3Aillustrates that the buffer manager138has 15 buffer areas identified by 1stto 15thindices respectively. The buffer manager138may determine which indexed buffer area(s) currently store data. The buffer manager138may allocate one or more buffer areas in which no data are stored in order to temporarily store data associated with a command.FIG. 3Aillustrates a state in which the buffer manager138allocates buffer areas corresponding to the first to fourth indices and storing no data for the first command CMD1. The buffer manager138may pre-allocate buffer areas corresponding to fifth to eighth indices for CMD2even before a first command process associated with CMD1is completed to improve the operation performance of the memory system110. Similarly, the buffer manager138may pre-allocate buffer areas corresponding to ninth through 12thindices for a third command.

The re-generation queue1326may be empty at this time.

FIG. 4is a flowchart describing an operation of the memory system110in accordance with an embodiment of the present invention.

In step S402, the command buffer1322may receive an abort command from the host102.

FIG. 3Bis a diagram illustrating a state change of the memory system110according to step S402. As inFIG. 3A, for clarity,FIG. 3Billustrates only those constituent elements of the memory system110pertinent to the processing described in connection withFIG. 4, i.e., the command buffer1322, the command queue1324, the re-generation queue1326, and the buffer manager138.

FIG. 3Billustrates a state in which an abort command ABORT_CMD2&3for CMD2and CMD3is buffered in the command buffer1322.

The host processor1328may queue the abort command ABORT_CMD2&3in the command queue1324. ABORT_CMD2&3may be processed with a higher priority than a normal command (i.e., any of CMD1to CMD4). The host processor1328may adjust the order in which the commands are queued in the command queue1324so that a command having a high priority is performed first.FIG. 3Billustrates a state where ABORT_CMD2&3is queued ahead of CMD1.

CMD1may be being processed when ABORT_CMD2&3is queued. For example, when CMD1is a write command, the host processor1328may queue ABORT_CMD2&3while a portion of write data corresponding to CMD1(or sub-command(s) thereof) is received from the host102and buffered in a buffer. As another example, when CMD1is a read command, the host processor1328may queue ABORT_CMD2&3while a portion of read data corresponding to CMD1(or sub-command(s) thereof) is read from the memory device150and buffered in the buffer.FIG. 3Billustrates a state in which a portion of data associated with CMD1(or sub-command(s) thereof) is received and buffered in the buffer areas corresponding to the first and second indexes when ABORT_CMD2&3is being queued. InFIG. 3B, the buffer areas in which data are buffered are shown with perimeter shading.

In step S404, a re-generated command corresponding to a remaining command of the command queue1324may be queued into the re-generation queue1326.

FIG. 3Cillustrates the state of the memory system110after the operation of step S404is performed. Referring toFIG. 3C, ABORT_CMD2&3for CMD2and CMD3that are queued at the head of the command queue1324may be executed first. The host processor1328may stop normal command processing and perform an abort process in response to ABORT CMD2&3.

In the example ofFIG. 3C, the host processor1328may stop the operation of buffering data associated with CMD1. The host processor1328may process a portion of the operations instructed by CMD1based on data that are already buffered. Processing a portion of a command (i.e., at least one sub-commands of the command) may mean performing a command operation on only a portion of the data associated with the command.

The host processor1328may queue a re-generated command corresponding to CMD1and CMD4, which are remaining commands, into the re-generation queue1326. The re-generated command and the remaining commands may be the same as or different from each other. For example, when retention remaining command has not been processed yet, the host processor1328may queue the remaining command as a re-generated command into the re-generation queue1326. When retention remaining command has been only partially processed, the host processor1328may generate a re-generated command corresponding to the unprocessed portion (i.e., the sub-command(s) that have not been executed) of the remaining command and queue the re-generated command into the re-generation queue1326. For example, the host processor1328may receive an abort command while receiving96kbof data in response to a write command to write128kbdata from the host102. On the side of host102, a portion of the write command corresponding to the received96kbdata is a processed portion or processed sub-command. On the other hand, a portion of the write command corresponding to remaining32kbdata is the unprocessed portion or unprocessed sub-command. The host processor1328may provide the FTL processor134with write command corresponding to the received96kbdata, generate re-generated command corresponding to the remaining32kbdata and queue the re-generated command in response to the abort command.

An example of an operation in which the host processor1328processes a portion (i.e., sub-commands) of a command and generates a re-generated command corresponding to the unprocessed portion (i.e., the unprocessed or unexecuted sub-commands) of the command is described below.

A normal command may include the size and address information of data to be stored in the memory device150or to be provided to the host102. For example, CMD1may be associated with data of four logical addresses from a logical address ‘100’. For example, assuming that a buffer area corresponding to one index is capable of buffering data represented by one logical address, data respectively corresponding to logical addresses ‘100’, ‘101’, ‘102’ and ‘103’ may be buffered in first to fourth buffer areas. In the example ofFIG. 3C, data corresponding to the logical addresses ‘100’ and ‘101’ may be already buffered.

The host processor1328may process a portion (i.e., one or more sub-commands) of CMD1based on the data that are already buffered before the re-generated command corresponding to CMD1is generated. For example, when CMD1is a write command, the host processor1328may provide a write command to an FTL processor134to program the data corresponding to the logical addresses ‘100’ and ‘101’ in the memory device150. When CMD1is a read command, the host processor1328may provide the data corresponding to the logical addresses ‘100’ and ‘101’ to the host102.

The host processor1328may also have to process the unprocessed portion (i.e., the unprocessed sub-command(s)) of CMD1after the abort process of CMD2and CMD3is completed to ensure atomicity for CMD1. The host processor1328may generate a fifth command CMD5instructing to write data for two logical addresses starting from the logical address ‘102’ and queue CMD5in the re-generation queue1326. CMD5is a re-generated command and may correspond to CMD1, which is a remaining command.

CMD4, which is a remaining command, is not entirely processed yet. The host processor1328may queue CMD4as a re-generated command in the re-generation queue1326.

In step S406, the host processor1328may reset the command queue1324and the buffer allocations of the buffer manager138.

FIG. 3Dillustrates the state of the memory system110after the operation of the step S406is performed.

The host processor1328may remove all commands queued in the command queue1324. The host processor1328may remove information associated with the buffer allocation of the buffer manager138. Referring toFIG. 3D, information representing that a buffer is allocated to CMD1to CMD3may be removed.

Although not shown in detail inFIG. 3D, a command currently being processed may be an abort target command. The host processor1328may remove buffer allocation and the data of the allocated buffer area even when at least a portion of the data associated with one or more sub-commands of the command is buffered in a buffer. Therefore, when the abort target command is currently being processed, the atomicity of the memory system110may be ensured by completely aborting the command.

By the operation of step S406, CMD2and CMD3queued in the command queue1324may be aborted. In step S406, CMD1and CMD4may also be removed from the command queue1324.

In step S408, the host processor1328may queue the re-generated commands CMD4and CMD5queued in the re-generation queue1326into the command queue1324. The host processor1328may ensure the atomicity for CMD1and CMD4by processing CMD4and CMD5which are queued in the command queue1324.

FIG. 3Eis a diagram illustrating a state of the memory system110after the operation of step S408is performed.

FIG. 3Eillustrates a state where CMD4and CMD5are queued in the command queue1324. CMD5may be a re-generated command corresponding to CMD1, and may be processed first by the host processor1328because it is queued ahead of CMD4.

FIG. 3Eillustrates a state in which the buffer manager138allocates a buffer area for CMD4and CMD5. A buffer area corresponding to the first and second indexes may be allocated for CMD5, and a buffer area corresponding to the third to sixth indexes may be allocated for CMD4. In the example ofFIG. 3C, CMD5may be a command associated with two logical addresses from the logical address ‘102’.

For example, when CMD1is a write command, the host processor1328may receive data corresponding to the logical addresses ‘102’ and ‘103’ from the host102in response to CMD5and provide a command to the FTL processor134so that the memory device150may write the data. When CMD1is a read command, the host processor1328may control the FTL processor134to read the data corresponding to the logical addresses ‘102’ and ‘103’ based on CMD5and provide the read data to the host102. Since CMD5corresponding to the unprocessed portion (i.e., unprocessed sub-command(s)) of CMD1is processed, the processing of CMD1may be completed.

According to an embodiment of the present invention, the host processor1328may queue the re-generated command corresponding to the remaining command into the re-generation queue1326in response to the abort command ABORT_CMD2&3, and reset the command queue and buffer allocation information. The host processor1328may abort the abort target command by collectively resetting the command queue and the buffer allocation information. The host processor1328may not have to perform a complicated operation for removing only the abort target command among the commands that are queued in the command queue1324and the lower queue. Similarly, the buffer manager1328may not have to perform any separate processing on the buffer area allocated for the abort target command. Thus, the time taken for the abort processing of the memory system110may be shortened, and the complexity of the implementation of the memory system110may be reduced.

According to embodiments of the present invention, it is possible to ensure rapid processing of an abort command for a command queued inside the controller.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. The present invention encompasses all such changes and modifications that fall within the scope of the claims.