Bridge rectifier circuit

A bridge rectifier circuit has first to fourth diode groups which are bridge-connected and each include a main diode and sub-diodes being enabled to be respectively connected in parallel to the main diode, first and second input terminals to which AC power is supplied, a first output terminal connected to the first input terminal via the first diode group and connected to the second input terminal via the second diode group, a second output terminal connected to the first input terminal via the third diode group and connected to the second input terminal via the fourth diode group, and a control circuit configured to detect a current flowing through at least one diode group and increases the number of sub-diodes connected in parallel to the main diode of the diode group through which the detected current flows in accordance with an increase in the detected current.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-223296, filed on Oct. 5, 2012, the entire contents of which are incorporated herein by reference.

FIELD

The present invention relates to a bridge rectifier circuit.

BACKGROUND

Energy harvesting which is currently attracting attention is technology in which surrounding microenergy that is unused and discarded is collected from light, heat, vibrations, electromagnetic waves, and the like to generate power. Examples of energy harvesting include vibration power generation in which power is generated by subjecting a piezoelectric device to distortion and radio-frequency power generation in which ambient radio waves are converted into power by an antenna. Normally, electrical energy created by vibration power generation or radio-frequency power generation is supplied to a load circuit using an AC-DC converter which generates a DC output voltage with a desired potential from AC power created by power generation.

An AC-DC converter includes a rectifier circuit, a DC-DC converter, and the like, and first rectifies AC voltage of the AC power to a DC voltage with the rectifier circuit and then generates an output voltage with a desired potential from the DC voltage with the DC-DC converter.

A bridge rectifier circuit using a plurality of diodes is known as the rectifier circuit included in the AC-DC converter. When designing a bridge rectifier circuit, generally, a size of diodes used in the bridge rectifier circuit is determined based on a density of a current that can be passed through the diodes which is, in turn, determined by a material of the diodes, and on a maximum current value of a current that is desirably passed through the diodes.

A combination of diodes and switches are disclosed in Japanese Patent Application Laid-open No. 2011-182191 and Japanese Patent Application Laid-open No. H6-295591

SUMMARY

However, when a diode is formed on a semiconductor substrate, a leakage current is generated which leaks from an N-well region in which the diode is formed to a P-substrate. The leakage current increases mainly in proportion to an area of a P-N junction of the diode. Therefore, when the density of a current that can be passed through the diode is constant, the higher the maximum current value that is desirably passed through the diode, the greater the size of the diode and the greater the leakage current.

In addition, energy obtained by energy harvesting fluctuates according to external environment conditions and a current that flows through diodes of a rectifier circuit also fluctuates. Therefore, when a weak current generated by energy harvesting flows through a diode with a large size based on the maximum current value, a ratio of the leakage current to a current which flows through the diode and which is created by energy harvesting increases. In particular, in an environment where microenergy is generated over a long period of time, a large ratio of leaking unused energy among the generated microenergy is undesirable.

An aspect of the embodiment is a bridge rectifier circuit having: first, second, third, and fourth diode groups which are bridge-connected and which each include a main diode and a single or a plurality of sub-diodes that are enabled to be respectively connected in parallel to the main diode via a switch; first and second input terminals to which AC power from an AC power source is supplied; a first output terminal which is connected to the first input terminal via the first diode group and which is connected to the second input terminal via the second diode group; a second output terminal which is connected to the first input terminal via the third diode group and which is connected to the second input terminal via the fourth diode group; and a control circuit configured to detect a current flowing through at least one diode group from among the first, second, third, and fourth diode groups and to control, based on the detected current, the switch of the diode group through which the detected current flows, wherein the control circuit increases the number of sub-diodes connected in parallel to the main diode of the diode group through which the detected current flows in accordance with an increase in the detected current.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a diagram illustrating an example of an AC-DC converter. An AC-DC converter10illustrated inFIG. 1includes a bridge rectifier circuit11using four diodes DA, DB, DC, and DD which are connected to an AC power source e and which convert an AC current from the AC power source e into a DC current IA, a capacitor CA which is connected to a terminal NA, and a DC-DC converter12which generates a desired voltage VB at a terminal NB from a voltage VA of the terminal NA, and generates the desired voltage VB from energy generated by the AC power source e and supplies the desired voltage VB to the load circuit14.

A unit for energy harvesting such as vibration power generation and wireless charging is used as the AC power source e. For example, when a piezoelectric device is used as the AC power source e, vibrational energy applied to a piezoelectric body is converted into electrical energy and an AC voltage is generated at nodes PZ1and PZ2. The vibrational energy applied to the piezoelectric body fluctuates according to a usage environment of the AC power source e. For example, in an environment where a vibration of a motor is applied to the piezoelectric body of the AC power source e, electrical energy generated by the AC power source e fluctuates according to how the motor vibrates in the case of a constant high-speed vibration or an intermittent vibration.

The DC-DC converter12includes switches SWA and SWB that are connected in series between the terminal NA and ground GND, an inductor LA that is connected between a connection node NC of the switches SWA and SWB and the terminal NB, a capacitor CB that is connected to the terminal NB, and a switching control circuit13that controls the switches SWA and SWB.

When vibrational energy is applied to the AC power source e and energy harvesting is performed, an AC current is converted into a DC current IA by the bridge rectifier circuit11. The DC current IA is then inputted to the terminal NA, an electrical charge is charged to the capacitor CA, and the voltage VA of the terminal NA increases. The switching control circuit13is not activated and the desired voltage VB is not outputted to the terminal NB until the voltage VA of the terminal NA reaches a predetermined voltage V0.

Once the voltage VA of the terminal NA reaches the predetermined voltage V0, the switching control circuit13turns on the switch SWA and turns off the switch SWB. Accordingly, the connection node NC rises to a same voltage VA as the terminal NA and an inductor current ILA gradually increases. Due to the inductor current ILA, the electrical charge charged to the input-side capacitor CA is transferred to the output-side capacitor CB.

After the lapse of a predetermined period of time, the switching control circuit13turns off the switch SWA and turns on the switch SWB. Accordingly, the connection node NC drops to a voltage that is lower than the ground voltage, the inductor LA continues passing the inductor current ILA in a forward direction due to accumulated electromagnetic energy, and charging of the capacitor CB is continued. However, the inductor current ILA decreases gradually. When the inductor current ILA assumes zero, the switching control circuit13turns off the switch SWB to prevent the inductor current ILA from flowing in a reverse direction.

As described above, due to the switching control circuit13controlling on and off states of the switches SWA and SWB, the electrical charge of the capacitor CA is charged to the capacitor CB and the voltage VA of the terminal NA drops. Therefore, the switching control circuit13turns off the switches SWA and SWB and suspends control of the switches SWA and SWB.

On the other hand, the dropped voltage VA of the terminal NA once again rises as an electrical charge continues to be charged to the capacitor CA by the AC power source e during the suspension of control of the switches SWA and SWB. In addition, when the voltage VA once again reaches the predetermined voltage V0, the switching control circuit13turns on the switch SWA and turns off the switch SWB for a predetermined period of time and subsequently turns off the switch SWA and turns on the switch SWB to charge an electrical charge to the capacitor CB.

As described above, due to the switching control circuit13repetitively controlling the switches SWA and SWB when the voltage VA of the terminal NA is equal to or higher than a predetermined voltage V0, the electrical charge is charged to the capacitor CB and the output voltage VB with a desired potential is generated at the terminal NB.

FIG. 2is a diagram illustrating an example of a diode formed on a semiconductor substrate. When the diodes DA to DD used in the bridge rectifier circuit11of the AC-DC converter10illustrated inFIG. 1is formed on a semiconductor substrate as illustrated inFIG. 2, a parasitic diode DS exists between an N-well region90and a P-substrate91. During an operation of the bridge rectifier circuit11, the parasitic diode DC enters an inversely-biased state and a reverse-direction leakage current Isub flows. Normally, since a leakage current increases mainly in proportion to an area of a P-N junction between the N-well region90and a P+ layer92above the N-well region90, the greater the size of the diode, the greater the leakage current Isub.

When designing a bridge rectifier circuit, a size of a diode is determined based on a density of a current that can be passed through the diode which is, in turn, determined by a semiconductor material, and on a maximum current value of a current that is desirably passed through the diode. In addition, a constant leakage current Isub is created at a diode with a determined size.

With energy harvesting such as that performed by the AC power source e illustrated inFIG. 1, since generated electrical energy fluctuates according to external environmental conditions, an input current Ifin of a diode fluctuates. Therefore, with the bridge rectifier circuit11illustrated inFIG. 1, while the input current Ifin that is inputted to a diode fluctuates, on the other hand, a leakage current Isub created at the diode is a constant current that depends on the diode size designed based on a maximum current value of a current that is desirably passed through the diode. Therefore, the smaller the input current Ifin, the greater the ratio of the leakage current Isub to the input current Ifin.

Normally, since energy generated by energy harvesting is weak, it is desirable that the generated energy is fully utilized. In consideration thereof, a bridge rectifier circuit which suppresses leakage current and improves power generation efficiency will be described below.

First Embodiment

FIG. 3is a diagram illustrating a first bridge rectifier circuit according to a first embodiment. A bridge rectifier circuit21illustrated inFIG. 3is a bridge rectifier circuit in which diode circuits22A to22D are bridge-connected in place of the diodes DA to DD included in the bridge rectifier circuit11illustrated inFIG. 1. Moreover, as will be described later, the diode circuits22A to22D include diode groups23A to23D which have a plurality of diodes and control circuits24A to24D which detect currents of the diode groups and control a total size of the diodes.

InFIG. 3, an input current Ifin that is an AC current outputted from the AC power source e flows in either a first rectification direction in an order of “AC power source e→input terminal PZ1→diode circuit22B→output terminal PZ4→capacitor CA→reference voltage GND→output terminal PZ3→diode circuit22C→input terminal PZ2→AC power source e” or a second rectification direction in an order of “AC power source e→input terminal PZ2→diode circuit22D→output terminal PZ4→capacitor CA→reference voltage GND→output terminal PZ3→diode circuit22A→input terminal PZ1→AC power source e”. Subsequently, the input current Ifin is rectified by the diodes included in each of the diode circuits22A to22D and converted into a DC current IA.

InFIG. 3, the diode circuits22A to22D (to be described later) each control sizes of diodes in their own diode groups based on the input current Ifin that is inputted to the diode groups using their own control circuits in order to control the leakage current Isub.

For example, when the input current Ifin is a weak current that is lower than a maximum current value, the diode circuits22A to22D reduce the sizes of diodes in their own diode groups to suppress the leakage current Isub. In addition, when generated energy of the AC power source e increases and the input current Ifin increases, the diode circuits22A to22D increase the sizes of diodes in their own diode groups to ensure that the leakage current Ifin flows without breaking the diodes.

FIG. 4is a diagram illustrating a first diode circuit according to a first embodiment. A diode circuit22illustrated inFIG. 4represents a configuration of the diode circuits22A to22D illustrated inFIG. 3. A diode group23represents a configuration of the diode groups23A to23D illustrated inFIG. 3. A control circuit24represents a configuration of the control circuits24A to24D illustrated inFIG. 3.

The diode circuit22includes the diode group23having, positioned between an input terminal N1and an output terminal N2, a main diode D1and a single or a plurality of sub-diodes that are controlled to be connected in parallel via a PMOS transistor (switch), and the control circuit24that detects an input current Ifin of the diode group23and controls the number of sub-diodes. FIG.4illustrates an exemplary configuration of the diode circuit22in which the diode group23has two sub-diodes D2and D3. The diode group23has a similar configuration as that illustrated inFIG. 4even when there is a single sub-diode or three or more sub-diodes.

The sub-diode D2is connected to the input terminal N1via a PMOS transistor P1and to the output terminal N2via a PMOS transistor P3. In a similar manner, the sub-diode D3is connected to the input terminal N1via a PMOS transistor P2and to the output terminal N2via a PMOS transistor P4.

The diodes D1, D2, and D3respectively have parasitic diodes DS1, DS2, and DS3. When a current flows in a forward direction of the diodes D1, D2, and D3, the parasitic diodes DS1, DS2, and DS3enter an inversely-biased state and reverse-direction leakage currents Isub1, Isub2, and Isub3respectively flow through the parasitic diodes DS1, DS2, and DS3.

In the control circuit24, an amplifier VAMP1amplifies a potential difference Vf between the input terminal N1and the output terminal N2and produces an output VA1. A comparator CMP3compares a voltage of the input terminal N1with a voltage of the output terminal N2and outputs an output signal R. A comparator CMP1compares the output VA1of the amplifier VAMP1with a reference voltage VREF1and outputs a comparison result /S1to a flip-flop F1. A comparator CMP2compares the output VA1of the amplifier VAMP1with a reference voltage VREF2that is higher than the reference voltage VREF1and outputs a comparison result /S2to a flip-flop F2. The flip-flop F1is a reset-dominant RS flip-flop which receives input of the output /S1of the comparator CMP1and the output R of the comparator CMP3and which outputs a drive signal G1to gates of the PMOS transistors P1and P3of the diode group23. The flip-flop F2is a reset-dominant RS flip-flop which receives input of the output /S2of the comparator CMP2and the output R of the comparator CMP3and which outputs a drive signal G2to gates of the PMOS transistors P2and P4.

In other words, at the control circuit24, when the input current Ifin increases, a forward potential difference Vf of the diodes rises and the output VA1of the amplifier VAMP1also increases. Therefore, the comparators CMP1and CMP2output comparison results /S1and /S2in accordance with the input current Ifin. As a result, the outputs G1and G2of the flip-flops F1and F2becomes low level subsequently in accordance with an increase of the input current Ifin.

Accordingly, when the input current Ifin is small, the control circuit24controls on-states or off-states of the PMOS transistors P1to P4so as to reduce the total size of the diodes, i.e. the number of the diodes, in the diode group23. In addition, when the input current Ifin is large, the control circuit24controls on-states or off-states of the PMOS transistors P1to P4so as to increase the total size of the diodes in the diode group23.

Next, specific operations of the diode circuit22illustrated inFIG. 4will be described with reference toFIGS. 5 to 7.

FIG. 5is a timing diagram of the first diode circuit according to the first embodiment.FIG. 6is a diagram illustrating a potential difference between input and output terminals of a diode group and an input current of the diode group corresponding to the potential difference according to the first embodiment.FIG. 7presents a truth table of the flip-flops F1and F2according to the first embodiment.

Returning toFIG. 5, until time T0, energy harvesting is not performed by the AC power source e, the potential difference Vf between the input terminal N1and the output terminal N2of the diode group23is zero volts (0 V), and the input current Ifin is zero amperes (0 A).

At this point, the output R of the comparator CMP3assumes an H level (a high-potential supply voltage; for example, a voltage VA). In addition, since the output of the amplifier VAMP1assumes zero volts (0 V), the outputs /S1and /S2of the comparators CMP1and CMP2both assume an H level. As a result, drive signals G1and G2that are respectively outputted from the flip-flops F1and F2both assume an H level (a record D inFIG. 7). In addition, an H level is supplied to the respective gates of the PMOS transistors P1to P4of the diode group23and the PMOS transistors P1to P4all enter an off-state. Therefore, when the potential difference Vf is zero volts (0 V), a diode size of the diode group23assumes a size of the main diode D1.

Subsequently, the AC power source e starts energy harvesting at time T0 and the potential difference Vf between the input terminal N1and the output terminal N2rises. However, since the potential difference Vf is lower than a forward voltage Vf0where the diodes enter an on-state, the input current Ifin is zero amperes (0 A) (A inFIG. 6).

At this point, since the output VA1of the amplifier VAMP1is lower than the reference voltage VREF1, the outputs /S1and /S2of the comparators CMP1and CMP2both remain at the H level. In addition, since the input terminal N1has a higher potential than the output terminal N2, the output of the comparator CMP3assumes an L level (a low-potential supply voltage; for example, 0 V). As a result, the drive signals G1and G2that are respectively outputted from the flip-flops F1and F2both remain at the H level that is a state prior to time T0 (a record C inFIG. 7). Therefore, the PMOS transistors P1to P4of the diode group23remain in an off-state. In other words, the size of diode group23remains at the size of the main diode D1.

When the potential difference Vf reaches the forward voltage Vf0of the main diode D1at time T1, an input current If0flows through the diode group23. In addition, subsequent to time T1, the input current If0increases as the potential difference Vf rises (B inFIG. 6). Furthermore, the output VA1of the amplifier VAMP1also rises.

When the input current Ifin flows through the main diode D1, since the parasitic diode DS1enters an inversely-biased state, a leakage current Isub1is created. Therefore, an output current Ifout of the diode group23assumes a current obtained by subtracting the leakage current Isub=Isub1from the input current Ifin. Moreover, since the leakage current Isub=Isub1is weak with respect to the input current Ifin, the output current Ifout is illustrated inFIG. 5so as to increase in a similar manner to the input current Ifin.

At time T2, when the output VA1of the amplifier VAMP1reaches the reference voltage VREF1(when Ifin=If1and Vf=Vf1inFIG. 6), the output /S1of the comparator CMP1changes from the H level to the L level. As a result, the drive signal G1that is outputted from the flip-flop F1changes from the H level to the L level (a record A inFIG. 7).

Accordingly, the PMOS transistors P1and P3of the diode group23are switched from an off-state to an on-state and the main diode D1and the sub-diode D2are connected in parallel. At the same time, as illustrated inFIG. 6, the potential difference Vf between the input terminal N1and the output terminal N2drops from Vf1to Vf1′ and the output VA1of the amplifier VAMP1also drops.

In this manner, the size of the diode group23is enlarged from the size of the main diode D1to a size (D1+D2) that combines the main diode D1and the sub-diode D2.

After time T2, the input current Ifin further increases as the potential difference Vf rises (C inFIG. 6). At the same time, the output VA1of the amplifier VAMP1also rises. While the output /S1of the comparator CMP1assumes an H level until the output VA1once again reaches the reference voltage VREF1, since the flip-flop F1retains the state at time T2 (the record C inFIG. 7), the drive signal G1remains at the L level. In addition, while the output /S1of the comparator CMP1changes from the H level to the L level when the reference voltage VREF1is reached, since the flip-flop F1outputs the drive signal G1at the same L level as at time T2 (the record A inFIG. 7), the drive signal G1remains at the L level. In this manner, after time T2, the PMOS transistors P1and P3enter the on-state and the parallel connection between the main diode D1and the sub-diode D2is maintained.

On the other hand, at the respective diodes D1and D2of the diode group23, the parasitic diodes DS1and DS2enter an inversely-biased state when the input current Ifin flows through the main diode D1and the sub-diode D2. Therefore, leakage currents Isub1and Isub2are created. As a result, the output current Ifout assumes a current obtained by subtracting the leakage current Isub=Isub1+Isub2from the input current Ifin. Moreover, since the leakage current Isub=Isub1+Isub2is weak with respect to the input current Ifin, the output current Ifout is illustrated inFIG. 5so as to increase in a similar manner to the input current Ifin.

At time T3, when the output VA1of the amplifier VAMP1reaches a reference voltage VREF2(when Ifin=If2and Vf=Vf2inFIG. 6), the output /S2of the comparator CMP2changes from the H level to the L level. As a result, the drive signal G2that is outputted from the flip-flop F2changes from the H level to the L level (the record A inFIG. 7).

Accordingly, the PMOS transistors P2and P4of the diode group23are switched from an off-state to an on-state and the main diode D1and the sub-diodes D2and D3are connected in parallel. At the same time, as illustrated inFIG. 6, the potential difference Vf between the input terminal N1and the output terminal N2drops from Vf2to Vf2′ and the output VA1of the amplifier VAMP1also drops.

In this manner, the size of the diode group23is enlarged from the size (D1+D2) that combines the main diode D1and the sub-diode D2to a size (D1+D2+D3) that combines the three diodes D1, D2, and D3.

After time T3, the input current Ifin further increases as the potential difference Vf rises (D inFIG. 6). At the same time, the output VA1of the amplifier VAMP1also rises. In addition, the drive signal G1is maintained at the L level in the same manner as between times T2 and T3 as described above.

Furthermore, as for the drive signal G2, while the output /S2of the comparator CMP2remains at the H level until the output VA1once again reaches the reference voltage VREF2, since the flip-flop F2maintains the state at time T3 (the record C inFIG. 7), the drive signal G2remains at the L level. Subsequently, when the output VA1reaches the reference voltage VREF2, while the output /S2of the comparator CMP2changes from the H level to the L level, since the flip-flop F2outputs an L-level drive signal G2(the record A inFIG. 7), the drive signal G2remains at the L level.

In this manner, after time T3, the drive signals G1and G2are maintained at the L level and the PMOS transistors P1to P4remain in the on-state. In other words, the parallel connection between the main diode D1and the sub-diodes D2and D3is maintained.

On the other hand, at the respective diodes D1to D3of the diode group23, the parasitic diodes DS1, DS2, and DS3enter an inversely-biased state when the input current Ifin flows through the main diode D1and the sub-diodes D2and D3of the diode group23. Therefore, leakage currents Isub1, Isub2, and Isub3are created. As a result, the output current Ifout assumes a current obtained by subtracting the leakage current Isub=Isub1+Isub2+Isub3from the input current Ifin. Moreover, since the leakage current Isub=Isub1+Isub2+Isub3is weak with respect to the input current Ifin, the output current Ifout is illustrated inFIG. 5so as to increase in a similar manner to the input current Ifin.

In this manner, when the input current Ifin is small, the control circuit24switches the PMOS transistors P1to P4to the off-state and reduces the size of the diode group23to suppress the leakage current Isub. In addition, as the input current Ifin increases, the control circuit24sequentially switches the PMOS transistors P1to P4to the on-state in order to increase the number of diodes in the diode group23to be connected in parallel. Accordingly, the size of the diode group23is increased and becomes capable of passing a large input current Ifin.

At time T4, the input current Ifin starts to decrease and the potential difference Vf drops. At the same time, the output VA1of the amplifier VAMP1also drops. The input current Ifin decreases until time T7 when the potential difference Vf drops to a forward voltage Vf0of the main diode D1and the input current Ifin assumes zero amperes (0 A).

Between times T4 and T5, the output VA1of the amplifier VAMP1is higher than the reference voltage VREF2. Therefore, the outputs /S1and /S2of the comparators CMP1and CMP2both assume the L level and the drive signals G1and G2are both maintained at the L level (A inFIG. 7). Accordingly, the PMOS transistors P1to P4remain in the on-state.

Between times T5 and T6, the output VA1of the amplifier VAMP1becomes equal to or lower than the reference voltage VREF2and equal to or higher than the reference voltage VREF1. Therefore, the output /S1of the comparator CMP1assumes the L level and the drive signal G1is maintained at the L level (A inFIG. 7). In addition, the output /S2of the comparator CMP2assumes the H level and the drive signal G2is also maintained at the L level (C inFIG. 7). Accordingly, the PMOS transistors P1to P4remain in the on-state.

Between times T6 and T7, the output VA1of the amplifier VAMP1becomes equal to or lower than the reference voltage VREF1. Therefore, the outputs /S1and /S2of the comparators CMP1and CMP2both assume the H level and the drive signals G1and G2are both maintained at the L level (C inFIG. 7). Accordingly, the PMOS transistors P1to P4remain in the on-state.

At time T7, the potential difference Vf drops to or below the forward voltage Vf0of the main diode D1and the input current Ifin decreases to zero amperes (0 A). Since the output VA1of the amplifier VAMP1is equal to or lower than the reference voltage VREF1, the PMOS transistors P1to P4remain in the on-state in a similar manner to between times T6 to T7.

Subsequently, when the potential difference Vf becomes zero volts (0 V) at time T8, the output R of the comparator CMP3assumes the H level. As a result, drive signals G1and G2that are outputted from the flip-flops F1and F2both change from the L level to the H level (D inFIG. 7). As a result, PMOS transistors P1to P4change to an off-state and the size of the diode group23assumes the size of the main diode D1.

In this manner, after time T4, even if the input current Ifin decreases, the control circuit24maintains the PMOS transistors P1to P4of the diode group23in the on-state. Subsequently, when the potential difference between the input terminal N1and the output terminal N2of the diode group23becomes zero volts (0 V), the control circuit24switches the PMOS transistors P1to P4to the off-state and resets the diode group23to the state prior to time T0.

FIG. 8is a diagram illustrating an example of a layout in which diodes are arranged on a P-substrate according to the first embodiment.FIG. 8illustrates a layout example on a P-substrate91in a case where sizes the respective diodes D1to D3illustrated inFIG. 4are in a descending order of diodes D3, D2, and D1. As described with reference toFIG. 2, since an object of the diode circuit22is to suppress leakage currents from N-well regions901,902, and903to the P-substrate91, the diodes D1to D3desirably separate and electrically insulate the respective N-well regions901,902, and903from one another as illustrated inFIG. 8.

FIG. 9is a diagram illustrating a second bridge rectifier circuit according to the first embodiment. A bridge rectifier circuit21illustrated inFIG. 9is configured such that the diode circuits22C and22D inFIG. 3are replaced by diode groups23C and23D which have the same configuration as that of the diode group23.

InFIG. 9, based on the input current Ifin of the diode group23B, the control circuit24B of the diode circuit22B outputs the drive signals G1and G2not only to the diode group23B but also to the diode group23C that is on a path of the first rectification direction in the order of “AC power source e→input terminal PZ1→diode circuit22B→output terminal PZ4→capacitor CA→reference voltage GND→output terminal PZ3→diode group23C→input terminal PZ2→AC power source e”. In other words, the control circuit24B controls sizes of diodes of the diode group23B and the diode group23C.

In a similar manner, based on the input current Ifin of the diode group23A, the control circuit24A of the diode circuit22A outputs the drive signals G1and G2not only to the diode group23A but also to the diode group23D that is on a path of the second rectification direction in an order of “AC power source e→input terminal PZ2→diode group23D→output terminal PZ4→capacitor CA→reference voltage GND→output terminal PZ3→diode circuit22A→input terminal PZ1→AC power source e”. In other words, the control circuit24A controls sizes of diodes of the diode group23A and the diode group23D.

Alternatively, the bridge rectifier circuit21may be configured as illustrated inFIGS. 10 and 11in a similar manner toFIG. 9.FIG. 10is a diagram illustrating a third bridge rectifier circuit according to the first embodiment. A bridge rectifier circuit21illustrated inFIG. 10is configured such that the diode circuits22A and22C inFIG. 3are replaced by diode groups23A and23C which have the same configuration as that of the diode group23.

The drive signals G1and G2outputted by the control circuit24B of the diode circuit22B are supplied not only to the diode group23B of the diode circuit22B but also to the diode group23C. In a similar manner, the drive signals G1and G2outputted by the control circuit24D of the diode circuit22D are supplied not only to the diode group23D of the diode circuit22D but also to the diode group23A.

FIG. 11is a diagram illustrating a fourth bridge rectifier circuit according to the first embodiment. A bridge rectifier circuit21illustrated inFIG. 11is configured such that the diode circuits22B and22D inFIG. 3are replaced by diode groups23B and23D which have the same configuration as that of the diode group23.

The drive signals G1and G2outputted by the control circuit24A of the diode circuit22A are supplied not only to the diode group23A of the diode circuit22A but also to the diode group23D. In a similar manner, the drive signals G1and G2outputted by the control circuit24C of the diode circuit22C are supplied not only to the diode group23C of the diode circuit22C but also to the diode group23B.

As illustrated inFIGS. 9 to 11, since a pair of diode groups, existing on a path of the first or second rectification direction along which the input current Ifin, flows each pass the same current, therefore, with respect to the pair of diode groups existing on a path of each rectification direction, a common control circuit controls sizes of diodes of the pair of diode groups through which the input current Ifin flows based on the input current Ifin of each diode group. Accordingly, the bridge rectifier circuit21illustrated inFIGS. 9 to 11is capable of reducing circuit area as compared to a case where a control circuit is provided per diode group as illustrated inFIG. 3.

FIG. 12is a diagram illustrating a second diode circuit according to the first embodiment. InFIG. 12, portions that overlap withFIG. 4are denoted by similar reference signs.

In this case, inFIGS. 4 and 5, the sub-diodes D2and D3are connected to the main diode D1in an order of D2and D3after time T0 when the AC power source e starts energy harvesting. On the other hand, the comparator CMP2performs a comparison operation from time T0 to time T3 when the output VA1of the amplifier VAMP1reaches the reference voltage VREF2of the comparator CMP2. Therefore, if the comparison operation of the comparator CMP2is originally started at time T2, there is no need to perform the comparison operation between times T0 and T2.

In consideration thereof, inFIG. 12, in the diode circuit22, the comparator CMP2starts a comparison operation after the sub-diode D2is connected to the main diode D1. As a result, the diode circuit22is capable of reducing current consumption by the comparator as compared to the configuration illustrated inFIG. 4.

UnlikeFIG. 4, the comparator CMP2illustrated inFIG. 12is supplied with an inversion signal of the drive signal G1as an enable signal. When the drive signal G1is at the H level, the comparator CMP2enters an inactive state and outputs a constant output /S2at the H level. When the drive signal G1assumes the L level or, in other words, when the sub-diode D2is connected to the main diode D1, the comparator CMP2enters an active state and performs a comparison operation.

In addition, the control circuit24illustrated inFIG. 12uses VREF1in a similar manner to the comparator CMP1instead of VREF2as the reference voltage to be connected to the inverting input terminal of the comparator CMP2. Since the comparator CMP2starts a comparison operation after the sub-diode D2is connected to the main diode D1, the control circuit24illustrated inFIG. 12is also capable of increasing the size of diodes in the diode group23in stages using one reference voltage.

FIG. 13is a timing diagram of the second diode circuit according to the first embodiment.FIG. 13illustrates a specific operation example of a diode circuit22illustrated inFIG. 12.

InFIG. 13, up to time T0, the potential difference Vf between the input terminal N1and the output terminal N2of the diode group23assumes zero volts (0 V), and the input current Ifin assumes zero amperes (0 A) in a similar manner toFIG. 5.

Therefore, in a similar manner toFIG. 5, the output R of the comparator CMP3assumes the H level, the output /S1of the comparator CMP1assumes the H level, and the drive signal G1that is an output of the flip-flop F1assumes the H level. Accordingly, the comparator CMP2does not perform a comparison operation and outputs a constant output /S2at the H level. In addition, the drive signal G2that is an output of the flip-flop F2assumes the H level (B inFIG. 7).

In this case, the H level is supplied to the respective gates of the PMOS transistors P1to P4of the diode group23and the PMOS transistors P1to P4all enter an off-state. Therefore, when the potential difference Vf is zero volts (0 V), the diode size of the diode group23assumes a size of the main diode D1.

In addition, after time T0, the comparator CMP1and the flip-flop F1operate in a similar manner to that illustrated inFIG. 5. However, since the drive signal G1is at the H level until time T2 when the output VA1of the amplifier VAMP1initially reaches the reference voltage VREF1, the comparator CMP2is non-active and the output /S2of the comparator CMP2is maintained at the H level. Accordingly, the flip-flop F2maintains the drive signal G2at the state prior to time T0 (C inFIG. 7). In this manner, between times T0 and T2, a comparison operation of the comparator CMP2is not performed and the PMOS transistors P1to P4remain in the off-state, and current consumption of the comparator CMP2is suppressed.

Since the drive signal G1changes from the H level to the L level at time T2, the comparator CMP2starts performing a comparison operation at time T2 and outputs an H-level output /S2. Accordingly, the flip-flop F2maintains the drive signal G2at the state of T2 or, in other words, at the H level (C inFIG. 7). Moreover, the size of the diodes of the diode group23at time T2 is increased to a size (D1+D2) that combines the main diode D1and the sub-diode D2in a similar manner toFIG. 5.

When the output VA1of the amplifier VAMP1once again reaches the reference voltage VREF1at time T3, the output /S2of the comparator CMP2changes from the H level to the L level. In addition, the drive signal G2that is outputted from the flip-flop F2changes from the H level to the L level (A inFIG. 7). Accordingly, the PMOS transistors P1to P4all assume the on-state. In other words, the size of the diodes of the diode group23is increased to a size (D1+D2+D3) that combines the main diode D1and the sub-diodes D2and D3in a similar manner toFIG. 5.

After time T3, the comparator CMP2operates in a similar manner to the comparator CMP1. In other words, the comparator CMP2operates in a similar manner to the comparator CMP1illustrated inFIG. 5. As a result, the drive signals G1and G2are maintained at the L level until time T8 when the potential difference Vf assumes zero volts (0 V). In other words, the size of the diode group23remains at the size (D1+D2+D3) that combines the main diode D1and the sub-diodes D2and D3.

In addition, as the output R of the comparator CMP3rises from the L level to the H level at time T8, the drive signals G1and G2are reset to the H level. In other words, the size of the diode group23is reset to the size of the main diode D1.

As described above, according to the first embodiment, the control circuit24of the diode circuit22illustrated inFIG. 4orFIG. 12reduces the size of the diodes of the diode group23down to the size of the main diode D1when the input current Ifin is small in order to suppress the leakage current Isub. In addition, as the input current Ifin increases, the control circuit24controls the PMOS transistors P1to P4so as to increase the number of sub-diodes to be connected in parallel to the main diode D1in order to increase the size of the diodes of the diode group23and enable a large input current Ifin to flow.

Second Embodiment

In the first embodiment, after time T4 described with reference toFIGS. 5 and 13, the size of the diodes of the diode group23inFIG. 4is maintained at a size combining the diodes D1to D3even if the input current Ifin decreases. Therefore, when the input current Ifin decreases, the ratio of the leakage current Isub increases. While the leakage current is suppressed when the input current Ifin decreases by further providing the control circuit24illustrated inFIG. 4with a circuit that reduces the size of the diodes of the diode group23in accordance with a decrease in VA1, this results in an increased size of the control circuit24.

In consideration thereof, in the second embodiment, the diode groups23A to23D illustrated inFIGS. 3 and 9to11share the configuration of a diode group33(to be described later) and the control circuits24A to24D share the configuration of a control circuit34(to be described later). Accordingly, the bridge rectifier circuit11illustrated inFIGS. 3 and 9to11is capable of reducing the size of the diodes and reducing the leakage current as the input current Ifin decreases.

FIG. 14is a diagram illustrating a first diode group and a control circuit according to the second embodiment. The diode group33illustrated inFIG. 14has a similar configuration to that of the diode group23according to the first embodiment illustrated inFIG. 4. Moreover, portions that overlap withFIG. 4are denoted by similar reference signs.

In the control circuit34, a sense resistor RS is provided between an input terminal N1and the diode group33, and an amplifier CAMP1for sensing current detects an input current Ifin based on a potential difference between both terminals of the sense resistor RS. In addition, a comparator CMP1compares an output CA1of the amplifier CAMP1with a reference voltage VREF1and outputs a drive signal G1to the gates of PMOS transistors P1and P3. Furthermore, a comparator CMP2compares the output CA1of the amplifier CAMP1with a reference voltage VREF2that is higher than the reference voltage VREF1and outputs a drive signal G2to the gates of PMOS transistors P2and P4.

Due to the configuration described above, as the input current Ifin increases, the control circuit34controls the PMOS transistors P1to P4from an off-state to an on-state in an order of P1and P3, P2and P4to increase the size of the diodes of the diode group33. In addition, as the input current Ifin decreases, the control circuit34controls the PMOS transistors P1to P4from the on-state to the off-state in an order of P2and P4, P1and P3to reduce the size of the diodes of the diode group33.

FIG. 15is a timing diagram of the first diode group and the control circuit according to the second embodiment. The timing diagram ofFIG. 15represents an output current Ifout of the output terminal N2, a leakage current Isub, the output CA1of the amplifier CAMP1, and the drive signals G1and G2when the input current Ifin increases or decreases as illustrated inFIG. 15from time T0 to time T6.

At time T0, since the potential difference between both terminals of the sense resistor RS increases as the input current Ifin increases, the output CA1of the amplifier CAMP1rises. At this point, since the output CA1is lower than the reference voltage VREF1, the comparators CMP1and CMP2respectively output H-level drive signals G1and G2.

Accordingly, the PMOS transistors P1to P4of the diode group33all enter the off-state and the diode size of the diode group33assumes the size of the main diode D1.

At this point, when the input current Ifin flows through the main diode D1, since a parasitic diode DS1enters an inversely-biased state, a leakage current Isub=Isub1is created. Therefore, the output current Ifout assumes a current obtained by subtracting the leakage current Isub=Isub1from the input current Ifin. Moreover, since the leakage current Isub=Isub1is weak with respect to the input current Ifin, the output current Ifout is illustrated inFIG. 15so as to increase in a similar manner to the input current Ifin.

At time T1, as the output CA1of the amplifier CAMP1reaches the reference voltage VREF1, the comparator CMP1changes the drive signal G1from the H level to the L level and the comparator CMP2maintains the H-level drive signal G2.

Accordingly, among the PMOS transistors P1to P4of the diode group33, the PMOS transistors P1and P3enter the on-state and the PMOS transistors P2and P4maintain the off-state. In other words, the size of the diodes of the diode group33is increased to a size (D1+D2) that combines the main diode D1and the sub-diode D2.

Subsequently, when the input current Ifin flows through the diodes D1and D2, since the parasitic diodes DS1and DS2enter an inversely-biased state, a leakage current Isub=Isub1+Isub2is created. As a result, the output current Ifout assumes a current obtained by subtracting the leakage current Isub=Isub1+Isub2from the input current Ifin. Moreover, since the leakage current Isub=Isub1+Isub2is weak with respect to the input current Ifin, the output current Ifout is illustrated inFIG. 15so as to increase in a similar manner to the input current Ifin.

At time T2, as the output CA1of the amplifier CAMP1reaches the reference voltage VREF2, the comparator CMP1maintains the drive signal G1at the L level and the comparator CMP2changes the drive signal G2from the H level to the L level.

Accordingly, the PMOS transistors P1to P4of the diode group33all enter the on-state. In other words, the diode size of the diode group33is increased to a size (D1+D2+D3) that combines the main diode D1and the sub-diodes D2and D3.

Subsequently, when the input current Ifin flows through the diodes D1to D3, since the parasitic diodes DS1to DS3enter an inversely-biased state, a leakage current Isub=Isub1+Isub2+Isub3is created. As a result, the output current Ifout assumes a current obtained by subtracting the leakage current Isub=Isub1+Isub2+Isub3from the input current Ifin. Moreover, since the leakage current Isub=Isub1+Isub2+Isub3is weak with respect to the input current Ifin, the output current Ifout is illustrated inFIG. 15so as to increase in a similar manner to the input current Ifin.

The input current Ifin starts decreasing from time T3 and, accordingly, the potential difference between both terminals of the sense resistor RS decreases. At the same time, the output CA1of the amplifier CAMP1also drops. In addition, at time T4, as the output CA1of the amplifier CAMP1decreases below the reference voltage VREF2, the comparator CMP1maintains the L-level drive signal G1but the comparator CMP2changes the drive signal G2from the L level to the H level.

Accordingly, although the PMOS transistors P1and P3of the diode group33remain in the on-state, the PMOS transistors P2and P4are changed to the off-state. In other words, the diode size of the diode group33is reduced to a size (D1+D2) that combines the main diode D1and the sub-diode D2. As a result, the leakage current created in the diode group33decreases to the leakage current Isub=Isub1+Isub2of the parasitic diodes DS1and DS2.

At time T5, as the output CA1of the amplifier CAMP1drops below the reference voltage VREF1, the comparator CMP1changes the drive signal G1from the L level to the H level and the comparator CMP2maintains the drive signal G2at the H level.

Accordingly, the PMOS transistors P1to P4of the diode group33all enter the off-state and the diode size of the diode group33is reduced to the size of the main diode D1. As a result, the leakage current created in the diode group33decreases to the leakage current Isub=Isub1of the parasitic diode DS1.

As described above, according to the second embodiment, the control circuit34controls a size of the diodes of the diode group33in accordance with the input current Ifin, with a relatively small-sized configuration which does not include the flip-flops F1and F2illustrated inFIGS. 4 and 12and which includes a single sense resistor SR, a single amplifier CAMP1, and two comparators CMP1and CMP2. In other words, as the input current Ifin increases, the control circuit34increases the size of the diodes and allows a larger input current Ifin to flow. In addition, as the input current Ifin decreases, the control circuit34reduces the size of the diodes to suppress the leakage current.

Furthermore, due to the diode groups23A to23D illustrated inFIGS. 3 and 9to11having the configuration of the diode group33illustrated inFIG. 14and the control circuits24A to24D having the configuration of the control circuit34, the bridge rectifier circuit11is able to suppress the leakage current and convert an AC current into a DC current IA.

FIG. 16is a diagram illustrating a second diode circuit according to the second embodiment. A control circuit34illustrated inFIG. 16is a modification of the control circuit34illustrated inFIG. 14. The control circuit34illustrated inFIG. 16includes a MOS transistor P5in place of the sense resistor RS. In addition, portions inFIG. 16which overlap withFIG. 14are denoted by similar reference signs.

In the case ofFIG. 16, a control signal G0is supplied to the gate of the transistor P5from the outside. Upon operation of the bridge rectifier circuit, the control signal G0assumes the L level and the transistor P5enters a non-saturated and conductive state. When an input current Ifin flows to the non-saturated transistor P5, based on an on-resistance of the transistor P5, a potential difference between both terminals of the transistor P5increases as the input current Ifin increases. Subsequently, as the input current Ifin decreases, the potential difference between both terminals of the transistor P5decreases. In addition, the control circuit34outputs the drive signals G1and G2based on the potential difference between both terminals of the transistor P5in a similar manner to the control circuit34illustrated inFIG. 14. As a result, the size of the diodes of the diode group33is increased as the input current Ifin increases and is reduced as the input current Ifin decreases in a similar manner to the diode group33illustrated inFIG. 14. Accordingly, the leakage current created in the diode group33is suppressed.

Third Embodiment

FIG. 17is a diagram illustrating a bridge rectifier circuit according to a third embodiment. In the first and second embodiments, a control circuit provided for each diode group as illustrated inFIG. 3controls a single corresponding diode group, and a control circuit provided on each path in a first rectification direction or a second rectification direction of an input current Ifin as illustrated inFIGS. 9 to 11controls a pair of diode groups on the path. In contrast, in the third embodiment, a single control circuit which is provided between input terminals PZ1and PZ2and which is connected to an AC power source e as illustrated inFIG. 17controls four diode groups based on a magnitude and a direction of flow of an input current Ifin outputted from the AC power source e. Accordingly, a circuit area of the control circuit is further reduced as compared to the first and second embodiments.

Specifically, inFIG. 17, an AC input current Ifin is outputted from the AC power source e. The input current Ifin flows in either a first rectification direction in an order of “AC power source e→input terminal PZ1→diode group42B→output terminal PZ4→capacitor CA→reference voltage GND→output terminal PZ3→diode group42C→input terminal PZ2→AC power source e” or a second rectification direction in an order of “AC power source e→input terminal PZ2→diode group42D→output terminal PZ4→capacitor CA→reference voltage GND→output terminal PZ3→diode group42A→input terminal PZ1→AC power source e”.

A single control circuit43is provided between the input terminals PZ1and PZ2. When the input current Ifin flows in the first rectification direction, the control circuit43controls a size of the diodes of the diode groups42B and42C through which the input current Ifin flows, based on a magnitude of the input current Ifin. In addition, when the input current Ifin flows in the second rectification direction, the control circuit43controls a size of the diodes of the diode groups42A and42D through which the input current Ifin flows, based on the magnitude of the input current Ifin.

FIG. 18is a diagram illustrating a diode group and a control circuit according to the third embodiment. The diode group42that represents a configuration of the diode groups42A to42D illustrated inFIG. 17has a similar configuration to the diode group23according to the first embodiment. Moreover, portions that overlap withFIG. 4are denoted by similar reference signs.

In the control circuit43, first, an amplifier CAMP1with a gain Av amplifies a potential difference between both terminals of a sense resistor RS provided between the input terminals PZ1and PZ2and produces an output CA1. Moreover, an offset voltage VOFF is provided between one terminal of the sense resistor RS and a non-inverting input terminal of the amplifier CAMP1.

In addition, comparators CMP1to CMP4compare the output CA of the amplifier CAMP1with reference voltages VREF1to VREF4that respectively connect to the comparators CMP1to CMP4and output drive signals G1to G4.

Moreover, the reference voltages have a descending order of potentials of VREF2, VREF1, VREF3, and VREF4(VREF2>VREF1>Vb>VREF3>VREF4). In addition, while the reference voltages VREF1and VREF2are connected to non-inverting input terminals of respectively corresponding comparators CMP1and CMP2, the reference voltages VREF3and VREF4are connected to inverting input terminals of respectively corresponding comparators CMP3and CMP4.

The drive signals G1and G2respectively outputted from the comparators CMP1and CMP2are supplied to the diode groups42B and42C in the first rectification direction of the input current Ifin. Specifically, the drive signal G1is supplied to the PMOS transistors P1and P3of the diode groups42B and42C, and the drive signal G2is supplied to the PMOS transistors P2and P4of the diode groups42B and42C.

In addition, the drive signals G3and G4respectively outputted from the comparators CMP3and CMP4are supplied to the diode groups42A and42D in the second rectification direction of the input current Ifin. Specifically, the drive signal G3is supplied to the PMOS transistors P1and P3of the diode groups42A and42D, and the drive signal G4is supplied to the PMOS transistors P2and P4of the diode groups42A and42D.

Accordingly, when the input current Ifin flows from the input terminal PZ2to the input terminal PZ1(the first rectification direction), the control circuit43controls the size of the diodes of the diode groups42B and42C based on the input current Ifin. Conversely, when the input current Ifin flows from the input terminal PZ1to the input terminal PZ2(the second rectification direction), the control circuit43controls the size of the diodes of the diode groups42A and42D based on the input current Ifin.

FIG. 19is a timing diagram of a diode group and a control circuit according to the third embodiment. The timing diagram ofFIG. 19represents leakage currents IsubA to IsubD of the diode groups42A to42D, the output CA of the amplifier CAMP1, and the drive signals G1to G4of the comparators CMP1to CMP4when the input current Ifin that flows through the control circuit43increases or decreases as illustrated inFIG. 19from time T0 to time T10. Moreover, inFIG. 19, it is assumed that a direction from the input terminal PZ2to the input terminal PZ1(the first rectification direction) is a positive direction of the input current Ifin.

At time T0, when the input current Ifin increases and flows in the first rectification direction (the positive direction), the potential difference between both terminals of the sense resistor RS increases. At the same time, the output CA of the amplifier CAMP1rises from a reference voltage Vb=VOFF×Av that is a product of the offset voltage VOFF multiplied by the gain Av of the amplifier CAMP1.

As a result, the drive signals G1to G4respectively outputted by the comparators CMP1to CMP4all assume the H level. Accordingly, the PMOS transistors P1to P4of the diode groups42A to42D all enter the off-state. In other words, the size of the diodes of the diode groups42A to42D assumes the size of the diode D1.

In each of the diode groups42B and42C, the parasitic diodes DS1enter an inversely-biased state when a current Ifin flows through the main diodes D1and a leakage current Isub=Isub1that is weak with respect to the input current Ifin is created. In other words, from time T0, the leakage current IsubB of the diode group42B and the leakage current IsubC of the diode group42C become Isub1.

At time T1, as the output CA of the amplifier CAMP1reaches the reference voltage VREF1, the drive signal G1outputted from the comparator CMP1changes from the H level to the L level. Accordingly, the PMOS transistors P1and P3of the diode groups42B and42C are switched from the off-state to the on-state. In other words, the size of the diodes of the diode groups42B and42C is increased to a size (D1+D2) that combines the main diode D1and the sub-diode D2.

In addition, in each of the diode groups42B and42C, the parasitic diodes DS1and DS2enter an inversely-biased state when a current Ifin flows through the main diodes D1and the sub-diodes D2and a leakage current Isub=Isub1+Isub2that is weak with respect to the input current Ifin is created. In other words, from time T1, the leakage current IsubB of the diode group42B and the leakage current IsubC of the diode group42C become Isub1+Isub2.

At time T2, as the output CA of the amplifier CAMP1reaches the reference voltage VREF2, the drive signal G2outputted from the comparator CMP2changes from the H level to the L level. Accordingly, the PMOS transistors P2and P4of the diode groups42B and42C are switched from the off-state to the on-state. In other words, the size of the diodes of the diode groups42B and42C is increased to a size (D1+D2+D3) that combines the main diode D1and the sub-diodes D2and D3.

In addition, in each of the diode groups42B and42C, the parasitic diodes DS1, DS2, and DS3enter an inversely-biased state when a current Ifin flows through the main diodes D1and the sub-diodes D2and D3and a leakage current Isub=Isub1+Isub2+Isub3that is weak with respect to the input current Ifin is created. In other words, from time T2, the leakage current IsubB of the diode group42B and the leakage current IsubC of the diode group42C become Isub1+Isub2+Isub3.

The input current Ifin starts decreasing between time T2 and T3. At the same time, the potential difference between both terminals of the sense resistor RS decreases and the output CA1of the amplifier CAMP1drops.

Subsequently, as the output CA1drops below the reference voltage VREF2at time T3, the drive signal G2outputted from the comparator CMP2changes from the L level to the H level. Accordingly, the PMOS transistors P2and P4of the diode groups42B and42C are switched from the on-state to the off-state. In other words, the size of the diodes of the diode groups42B and42C is reduced to a size (D1+D2) that combines the main diode D1and the sub-diode D2.

Accordingly, at the diode groups42B and42C, a leakage current Isub=Isub1+Isub2that is weak with respect to the input current Ifin is created. In other words, from time T3, the leakage current IsubB of the diode group42B and the leakage current IsubC of the diode group42C become Isub1+Isub2.

At time T4, as the output CA1of the amplifier CAMP1drops below the reference voltage VREF1, the drive signal G1outputted from the comparator CMP1changes from the L level to the H level. Accordingly, the PMOS transistors P1and P3of the diode groups42B and42C are switched from the on-state to the off-state. In other words, the size of the diodes of the diode groups42B and42C is reduced to the size of the main diode D1.

Accordingly, at the diode groups42B and42C, a leakage current Isub=Isub1that is weak with respect to the input current Ifin is created. In other words, from time T4, the leakage current IsubB of the diode group42B and the leakage current IsubC of the diode group42C become Isub1.

At time T5, as the input current Ifin starts to flow in the second rectification direction (negative direction), the potential difference between both terminals of the sense resistor RS further decreases in the negative direction and the output CA1of the amplifier CAMP1drops.

In addition, since a current does not flow through the diode groups42B and42C at this point, the leakage current IsubB of the diode group42B and the leakage current IsubC of the diode group42C both assume zero amperes (0 A).

On the other hand, since the drive signals G3and G4are maintained at the L level, the size of the diode groups42A and42D is the size of the main diode A. Therefore, in each of the diode groups42A and42D, the parasitic diodes DS1enter an inversely-biased state when a current Ifin flows through the main diodes D1and a leakage current Isub=Isub1that is weak with respect to the input current Ifin is created. In other words, from time T5, the leakage current IsubA of the diode group42A and the leakage current IsubD of the diode group42D become Isub1.

At time T6, as the output CA1of the amplifier CAMP1drops below the reference voltage VREF3, the drive signal G3outputted from the comparator CMP3changes from the H level to the L level. As a result, the PMOS transistors P1and P3of the diode groups42A and42D are switched from the off-state to the on-state. In other words, the size of the diodes of the diode groups42A and42D is increased to a size (D1+D2) that combines the main diode D1and the sub-diode D2.

Accordingly, in each of the diode groups42A and42D, the parasitic diodes DS1and DS2enter an inversely-biased state when a current Ifin flows through the main diodes D1and the sub-diodes D2and a leakage current Isub=Isub1+Isub2that is weak with respect to the input current Ifin is created. In other words, from time T6, the leakage current IsubA of the diode group42A and the leakage current IsubD of the diode group42D become Isub1+Isub2.

At time T7, as the output CA1of the amplifier CAMP1drops below the reference voltage VREF4, the drive signal G4outputted from the comparator CMP4changes from the H level to the L level. As a result, the PMOS transistors P2and P4of the diode groups42A and42D are switched from the off-state to the on-state. In other words, the size of the diodes of the diode groups42A and42D is increased to a size (D1+D2+D3) that combines the main diode D1and the sub-diodes D2and D3.

Accordingly, in each of the diode groups42A and42D, the parasitic diodes DS1, DS2, and DS3enter an inversely-biased state when a current Ifin flows through the main diodes D1and the sub-diodes D2and D3and a leakage current Isub=Isub1+Isub2+Isub3that is weak with respect to the input current Ifin is created. In other words, from time T7, the leakage current IsubA of the diode group42A and the leakage current IsubD of the diode group42D become Isub1+Isub2+Isub3.

The input current Ifin starts increasing between time T7 and T8. At the same time, the potential difference between both terminals of the sense resistor RS increases and the output CA1of the amplifier CAMP1rises.

Subsequently, as the output CA1reaches the reference voltage VREF4at time T8, the drive signal G4outputted from the comparator CMP4changes from the L level to the H level. Accordingly, the PMOS transistors P2and P4of the diode groups42A and42D are switched from the on-state to the off-state. In other words, the size of the diodes of the diode groups42A and42D is reduced to a size (D1+D2) that combines the main diode D1and the sub-diode D2.

Accordingly, at the diode groups42A and42D, a leakage current Isub=Isub1+Isub2that is weak with respect to the input current Ifin is created. In other words, from time T8, the leakage current IsubA of the diode group42A and the leakage current IsubD of the diode group42D become Isub1+Isub2.

As the output CA1reaches the reference voltage VREF3at time T9, the drive signal G3outputted from the comparator CMP3changes from the L level to the H level. Accordingly, the PMOS transistors P1and P3of the diode groups42A and42D are switched from the on-state to the off-state. In other words, the size of the diodes of the diode groups42A and42D is reduced to the size of the main diode D1.

Accordingly, at the diode groups42A and42D, a leakage current Isub=Isub1that is weak with respect to the input current Ifin is created. In other words, from time T9, the leakage current IsubA of the diode group42A and the leakage current IsubD of the diode group42D become Isub1.

At time T10, as the input current Ifin assumes zero amperes (0 V), the potential difference between both terminals of the sense resistor RS and the output CA1of the amplifier CAMP1become zero volts (0 V). As a result, at the diode groups42A and42D, the leakage current Isub changes from Isub1to zero amperes (0 A).

As described above, according to the third embodiment, the relatively small control circuit43including a single sense resistor RS, a single amplifier CAMP1, and four comparators CMP1to CMP4controls the size of the diodes of four diode groups42A to42D based on a magnitude and a direction of flow of an input current Ifin.

Specifically, when the input current Ifin is flowing in the first rectification direction, as the input current Ifin increases, the control circuit43increases the size of the diodes of the diode groups42B and42C that are on a path of the first rectification direction to allow a large input current Ifin to flow. In addition, as the input current Ifin decreases, the control circuit43reduces the size of the diodes of the diode groups42B and42C to reduce the leakage current Isub.

On the other hand, when the input current Ifin is flowing in the second rectification direction, as the input current Ifin increases, the control circuit43increases the size of the diodes of the diode groups42A and42D that are on a path of the second rectification direction to allow a large input current Ifin to flow. In addition, as the input current Ifin decreases, the control circuit43reduces the size of the diodes of the diode groups42A and42D to reduce the leakage current Isub.