Programmable I/O structure for FPGAs and the like having shared circuitry

A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

CROSS-REFERENCE TO RELATED APPLICATIONS

The subject matter of this application is related to U.S. patent application Ser. No. 10/671,378 filed on the same date as the present application, the teachings of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to programmable devices, such as field-programmable gate arrays (FPGAs), and, in particular, to the input/output (I/O) interfaces for such devices.

BACKGROUND

A field-programmable gate array is a programmable device typically having a logic core surrounded by a ring of input/output (I/O) buffers. As silicon technology migrates to smaller and smaller devices and as core logic densities increase, the ratio of core logic to I/O buffers increases. In general, however, the physical size of I/O buffers has not been shrinking as fast as the physical size of the core logic. One solution to this phenomenon has been to implement narrow, elongated I/O buffers around the periphery of newer devices. Unfortunately, this approach significantly increases the cost of the devices.

Another factor contributing to the relatively large size of I/O buffers is the trend towards providing I/O circuitry with multiple different types of buffers connected to individual pads, for example, in order to support multiple different signaling applications. Unfortunately, this increased amount of circuitry results in increased levels of capacitance as seen from the pads, which increased capacitance adversely affects the higher-performance signaling applications.

SUMMARY

Problems in the prior art are addressed in accordance with the principles of the present invention by implementing programmable I/O buffers with circuitry that is shared by multiple pads. In that case, certain subsets of the circuitry that are not currently being used for one pad can be simultaneously used for another pad, thereby increasing the efficiency of use of the available I/O circuitry. Moreover, by implementing the selectivity capability using transmission gates connected between the outputs of output buffers and the corresponding pads, the capacitive load at a pad is reduced when a particular output buffer is not being used to drive an outgoing signal to the pad by opening the corresponding transmission gate.

In one embodiment, the present invention is a programmable device having programmable input/output (I/O) circuitry and programmable logic connected to receive incoming signals from and provide outgoing signals to the I/O circuitry. The programmable device comprises a first pad, a second pad, and a programmable I/O circuit (PIC) associated with the first and second pad. The PIC comprises a first output buffer, a first switch, and a second switch. The first output buffer is adapted to selectively present a first outgoing signal at the first pad and adapted to selectively present the first outgoing signal at the second pad. The first switch is connected between the first pad and the first output buffer to selectively present the first outgoing signal at the first pad. The second switch connected between the second pad and the first output buffer to selectively present the first outgoing signal at the second pad.

DETAILED DESCRIPTION

FPGA Architecture

FIG. 1shows a high-level block diagram of the layout of an exemplary FPGA100of the present invention, having a logic core102surrounded by an input/output (I/O) ring104. Logic core102includes an array of programmable logic blocks (PLBs)106intersected by rows of block memory108. Each PLB contains circuitry that can be programmed to perform a variety of different functions. The memory blocks in each row are available to store data to be input to the PLBs and/or data generated by the PLBs. I/O ring104includes sets of I/O buffers110programmably connected to the logic core by multiplexor/demultiplexor (mux/demux) circuits112. The I/O buffers support external interfacing to FPGA100. Also located within the I/O ring are a number of phase-locked loop (PLL) circuits114that are capable of providing different timing signals for use by the various elements within FPGA100. Those skilled in the art will understand that FPGAs, such as FPGA100, will typically include other elements, such as configuration memory, that are not shown in the high-level block diagram ofFIG. 1. In addition, general routing resources, including clocks, buses, general-purpose routing, high-speed routing, etc. (also not shown inFIG. 1), are provided throughout the FPGA layout to programmably interconnect the various elements within FPGA100.

The layout of an FPGA, such as FPGA100ofFIG. 1, comprises multiple instances of a limited number of different types of blocks of circuitry. For example, an I/O ring may contain a number of instances of the same basic block of circuitry repeated around the periphery of the device. In the example of FPGA100, I/O ring104is made up of multiple instances of the same basic programmable I/O circuit (PIC), where each PIC provides a particular number (e.g., three) of the I/O buffers of the I/O ring.

FIG. 2shows a schematic diagram of a programmable I/O buffer (PIB)200for FPGA100ofFIG. 1, according to one embodiment of the present invention. As shown inFIG. 2, PIB200provides I/O circuitry associated with four I/O silicon pads A–D. In particular, PIB200has six push-pull output buffers202, four input receivers204–210, and a differential output buffer212, variously connected between pads A–D and other internal FPGA circuitry (not shown).

More particularly, input receiver204is connected to receive incoming signals from pad A, input30receiver206is connected to receive incoming signals from pad B, input receiver208is connected to receive incoming signals from pad C, and input receiver210is connected to receive incoming signals from pad D. In addition, the differential outputs from differential buffer212are connected to provide a differential outgoing signal to pads A and C. Furthermore, each of output buffers202a–cis connected to provide an outgoing signal to pads A and B via a corresponding pair of transmission gates214and216, respectively. Similarly, each output buffer202d–fis connected to provide an outgoing signal to pads C and D via a corresponding pair of transmission gates214and216, respectively. In a preferred implementation, each transmission gate214,216is independently controllable to be either on (closed) or off (open).

The circuitry of PIB200ofFIG. 2enables the four pads A–D to support a wide range of different operational modes. In theory, different possible modes of operation can be implemented from different combinations of the following capabilities for the four different pads A–D:

Pad AIncoming signal drives input receiver204;Differential buffer212drives half of differential outgoing signal; and/orAny combination of one or more output buffers202a–cdrives “combined” outgoing signal.

Pad BIncoming signal drives input receiver206; and/orAny combination of one or more output buffers202a–cdrives “combined” outgoing signal.

Pad CIncoming signal drives input receiver208;Differential buffer212drives other half of differential outgoing signal; and/orAny combination of one or more output buffers202d–fdrives “combined” outgoing signal.

Pad DIncoming signal drives input receiver210; and/orAny combination of one or more output buffers202d–fdrives “combined” outgoing signal.

One of the advantages of the design of PIB200is the efficient use of circuitry. For example, although pad A can be simultaneously driven by all three output buffers202a–c, if only a subset of those output buffers is used to drive pad A, the one or two “unused” output buffers can be simultaneously used to drive pad B, by appropriately setting the states of the corresponding transmission gates214and216. Moreover, if one or more of output buffers202a–care used to drive pad B, pad A can be simultaneously operated in a differential output mode via differential output buffer212or in an input mode via input receiver204. Thus, while circuitry is provided to enable pads A and C to be operated in a number of different input and output modes, certain subsets of that circuitry that are not currently used for pads A and C can be simultaneously used for pads B and D, thereby increasing the efficiency of use of the available circuitry.

FIG. 3shows a schematic diagram of a PIB300for FPGA100ofFIG. 1, according to another embodiment of the present invention. PIB300is similar to PIB200ofFIG. 2, except that, instead of having a unique input receiver for each pad, PIB300has shared input receivers. In particular, input receiver304is connected to receive an incoming signal from either pad A or pad B. Similarly, input receiver308is connected to receive an incoming signal from either pad C or pad D. The selection of which pad drives the input receiver is provided by muxes318. PIB300ofFIG. 3may be able to be implemented in a smaller area than PIB200ofFIG. 2, albeit with reduced functional capabilities.

FIG. 4shows a schematic diagram of a PIB400for FPGA100ofFIG. 1, according to yet another embodiment of the present invention. PIB400is similar to PIB300ofFIG. 3, except that, unlike differential output buffer312ofFIG. 3, which drives output pads A and C with the two legs of a differential output signal, positive and negative outputs420and422of differential output buffer412apply the two legs of a differential output signal to output leg circuitry424. Circuitry424enables the two legs of the differential output signal to be selectively applied either to pads A and C, respectively, or to pads B and D, respectively.

In one implementation, the selection of either pad pair A/C or pad pair B/D is mutually exclusive, such that PIB400supports three different operating modes for differential output buffer412: a first mode in which pad pair A/C is driven, a second mode in which pad pair B/D is driven, and a third mode in which neither pad pair is driven (e.g., when buffer412is turned off). Note that this mutual exclusivity is not necessary for all implementations. Such “non-exclusive” implementations may support a fourth operating mode in which both pad pairs are driven at the same time with a single differential output signal from buffer412. Furthermore, in alternative embodiments, the PIB could have two differential output buffers, where each buffer drives a different pad pair.

The “mutually exclusive” implementation can be used to enable the FPGA design to support both flip-chip and wire-bond packaging configurations in an efficient manner. Prior-art FPGA designs that support both flip-chip and wire-bond packaging configurations have differential output buffers in which each differential output leg has a single metallic structure that can support either a flip-chip bond or a wire bond. If the FPGA is packaged in a flip-chip configuration, then that portion of the metallic output leg structure strictly corresponding to the wire bond would essentially be unused. Similarly, if the FPGA is packaged in a wire-bond configuration, then that portion of the metallic output leg structure strictly corresponding to the flip-chip bond would essentially be unused. Although this prior-art solution supports both packaging configurations, the excess (i.e., unused) portions of the metallic output leg structures add undesirable capacitance at the output pads.

The principles of PIB400can be employed to support either flip-chip or wire-bond packaging configurations by using output leg circuitry424to drive, in a mutually exclusive manner, either pad pair A/C (e.g., associated with a flip-chip configuration) or pad pair B/D (e.g., associated with a wire-bond configuration), where each metallic structure connecting one of the two differential buffer outputs with a particular pad is designed to minimize capacitive loading at the pad. In particular, when output leg circuitry424is configured to drive one of the pad pairs, capacitance from the other pad pair is shielded from the selected pad pair, and vice versa.

FIG. 5shows a schematic diagram of output leg circuitry424according to one embodiment of the present invention. As shown inFIG. 5, output leg circuitry424has a positive current source502and a negative current source504separated by a configuration of transistors506,508and switches510,512. For example, switch510ais connected to the gate of transistor506a, and switch512ais connected to the gate of switch508a, while switch510bis connected to the gate of transistor506b, and switch512bis connected to the gate of switch508b. And analogously for transistors506c–d,508c–dand switches510c–d,512c–d. The node connecting transistors506aand508ais also connected to pad A, while the node connecting transistors506band508bis connected to pad B. Similarly, the node connecting transistors506cand508cis connected to pad C, while the node connecting transistors506dand508dis connected to pad D.

With switches510a,512a,510c, and512cclosed and switches510b,512b,510d, and512dopen, signals corresponding to the two differential legs420,422of a differential output signal from differential output buffer412ofFIG. 4will be presented at pads A and C, respectively. Similarly, with switches510a,512a,510c, and512copen and switches510b,512b,510d, and512dclosed, signals corresponding to the two differential legs420,422will be presented at pads B and D, respectively.

In a preferred implementation, output leg circuitry424also includes a second (optional) positive current source514configured in parallel with positive current source502. Current source514is controlled by op amp516which is differentially driven by common-mode voltage CMV and an appropriate reference voltage Vref. Mux518selects the appropriate common-mode voltage to apply to op amp516. In particular, when switches510,512are configured to drive pads A/C, mux518is configured to select the common-mode voltage between pad A and pad C. Alternatively, when switches510,512are configured to drive pads B/D, mux518is configured to select the common-mode voltage between pad B and pad D.

Operationally, current source514compensates for variations in the common-mode voltage by driving the output leg circuitry to keep the selected common-mode voltage equal to the reference voltage Vref. In alternative implementations, an analogous additional current source could be added in parallel with negative current source504, either in addition to or instead of current source514.

Although not shown in the figures, those skilled in the art will understand that pad A and pad C are separated by a series combination of two substantially equal resistors R, where the common-mode voltage between pads A and C is the voltage at the node connecting the two resistors. Similarly, pad B and pad D are separated by a series combination of two substantially equal resistors R, where the common-mode voltage between pads B and D is the voltage at the node connecting the two resistors. The value of each resistor R is preferably substantially larger (e.g., five times) than the external termination applied between each pad pair.

Note that, in PIB400, output leg circuitry424enables two different pairs of pads to be selectively driven with a differential output signal generated by an otherwise shared output buffer. In particular, no matter which output pad pair is selected, the same reference circuitry (which generates reference voltages Vref, Pref, and Nref) and pre-drive circuitry (represented collectively inFIG. 4by buffer412) are used to generate the signals on lines420and422, without any performance impact. Note, further, that relatively high capacitance at node520improves performance by absorbing jitter in the current, thereby compensating for instability in current source504.

Although PIB400and output leg circuitry424support two different pairs of pads, the principles of this circuitry can be extended to any number of pad pairs by providing additional sets of drive leg circuitry similar to that shown inFIG. 5. PIB400has differential output buffer412, which may be suitable for low-voltage differential signaling (LVDS) applications. The present invention can also be implemented in the context of a PIB having one or more output buffers of other types, either in addition to or instead of a differential output buffer, where each of the output buffers is able to drive different pairs of pads.

FIG. 6shows a schematic diagram of output leg circuitry600that can be used to support a current-mode logic (CML) output buffer for serial/deserial (SerDes) type applications. In one embodiment, output leg circuitry600replaces output leg circuitry424ofFIG. 4, when the PIB has a CML output buffer in place of differential output buffer412. In another embodiment, the PIB has a CML output buffer in addition to differential output buffer412, where output leg circuitry600is associated with the CML output buffer and each buffer is capable of driving either pad pair. Like output leg circuitry424, circuitry600has switches, transistors, and resistors that enable the CML output buffer to selectively drive either pad pair A/C or pad pair B/D based on a differential signal620,622received from pre-drive circuitry of the CML output buffer.

As with output leg circuitry424ofFIG. 4, the principles of output leg circuitry600can be expanded to support one or more additional pad pairs by adding one or more additional sets of output leg circuitry. Moreover, like output leg circuitry424, the principles of output leg circuitry600can be used to provide FPGA designs that efficiently support both flip-chip and wire-bond packaging configurations. The principles of output leg circuits424and600can be extended to any other suitable type of output buffer.

Transmission Gates

In addition to supporting the selective driving of different pads, the transmission gates provide another benefit of reducing capacitive load at the pads. For example, referring toFIG. 2, if output buffer202ais not used to drive either of pads A or B, setting both transmission gates214aand216ato their open state, reduces the capacitive load that appears at pads A and B that would otherwise be contributed by the circuitry of output buffer202a. This reduction in capacitive load may be significant, especially when the I/O buffers are configured for high-speed signaling applications.

FIG. 7shows a schematic diagram of a transmission gate702connected between the output of a push-pull buffer704and a pad P, such as may be used in any of the PIBs ofFIGS. 2–4. In particular, push-pull buffer704comprises N push-pull “sub-buffers” connected in parallel, each sub-buffer i comprising (1) a resistor RPi connected between a negatively driven transistor MPi and a shared node S of buffer704and (2) a resistor RNi connected between a positively driven transistor MNi and shared node S.

The resistors improve the linearity of the output impedance of buffer704as a function of pad voltage and also provide impedance matching with the board impedance. Transmission gate702isolates the parasitic capacitance of the resistors from pad P. Without transmission gate702, the pad capacitance would increase significantly due to the parasitic capacitance of the resistors, which would degrade the performance of high-speed buffers, such as differential output buffer212ofFIG. 2.

Transmission gate702comprises three switch devices TX1–3connected in parallel between push-pull buffer704and pad P. In particular, one side of the channel of each switch device is connected to node S and the other channel side is connected to pad P. Turning off each switch device will place transmission gate702in an open (i.e., off) state, in which a signal from transmission gate702is not presented at pad P. On the other hand, turning on any one or more of the switch devices will place transmission gate702in a closed (i.e., on) state in which a signal from transmission gate702is presented at pad P.

Although switch devices TX1–3isolate parasitic capacitance of the resistors from pad P, their sizes are preferably optimized to meet the relevant I/O specification of push-pull output buffer704across all process, voltage, and temperature corners. At the same time, their junction capacitances are preferably small. To meet these goals, the size of the transmission gates are optimized such that their junction capacitances are small and the resistances are about 20–30% of the resistance of the n-well or poly resistors. In addition, three different control signals (and their complements) are used to enable one or more of transmission gates TX1–3to compensate for variation of their own resistance due to process and temperature variations. Note that, while process variations are static, temperature variations may be dynamic, in which case the selection of the control signals for the different transmission gates can preferably be changed as needed as temperature changes.

In one possible implementation, if transmission gate702is not implemented, the total area of the resistors in push-pull buffer704is about (63 microns×63 microns) or about 4000 microns2. In current deep sub-micron technology, the area junction capacitance CJis about 1×10−3farads/meter2and side-wall capacitance CSWis about 1.2×10−10farads/meter. Thus, the total capacitance CRESseen by pad P will be:
CRES=(4000 μm^2×1e−3f/m^2)+(4×63μm×1.2e−10f/m)
=4pf+0.03pf
=4.03pf

When transmission gate702is implemented to provide isolation between single-ended buffer704and a differential output buffer, such as differential output buffer212ofFIG. 2, pad P will be exposed to the junction capacitance of transmission gate702rather than the capacitance CRESof buffer704. Transmission gate702can be sized to contribute about 20–30% or more of the resistance of n-well or poly resistors and still maintain sufficient linearity of the resistance. In one implementation, the total transmission gate size is about 5×(120+60) or 900 microns. The total capacitance CTGATEseen by pad P will then be:
CTGATE=(900μm×1.95μm×1e−3f/m^2)+(2×(1.95μm+900μm)×1.2e−10f/m)
=1.76pf+0.22pf
=1.98pf
where 1.95 microns is the window-to-edge distance in output transistors. This corresponds to about a 51% reduction in capacitance seen at pad P by incorporating transmission gate702.

Although transmission gate702ofFIG. 7is implemented using three switch devices connected in parallel, in theory, transmission gates of the present invention can be implemented using any suitable number of one or more switch devices.

Note that, as used in this specification, the terms “switch” and “switch device” are not necessarily equivalent. For example, transmission gate702is an example of a type of switch that is itself implemented using three different switch devices.

Although the PIBs of the present invention have been described in the context of implementations having push-pull output buffers, it will be understood that other types of single-ended output buffers could alternatively be used.

Although, for example, PIB200ofFIG. 2is implemented with two sets of three output buffers202, in general, PIBs according to the present invention may be implemented with any suitable number of one or more output buffers in each set. Similarly, although PIB200is implemented as being associated with four pads, in general, PIBs according to the present invention may be implemented with any suitable number of pads. Furthermore, PIBs of the present invention may be implemented without a differential output buffer, such as buffer212ofFIG. 2. In that case, the left and right sides of the circuitry shown inFIG. 2could be considered to form two different PIBs, each corresponding to a different pair of pads. Moreover, in theory, PIBs could be implemented without input receivers and/or without push-pull output buffers. It will also be understood that the capacitance-reducing advantage of using a transmission gate will still apply if a given output buffer is capable of driving only a single pad, where a transmission gate is implemented between that output buffer and that pad.

Although the present invention has been described in the context of FPGAs, those skilled in the art will understand that the present invention can be implemented in the context of other types of programmable devices, such as, without limitation, programmable logic devices (PLDs) and mask-programmable gate arrays (MPGAs).