Wear leveling and improved efficiency for a non-volatile memory device

Providing for improved cell longevity for two-terminal memory devices is described herein. By way of example, wear leveling and management of array operations is provided to reduce an average number of set or reset cycles employed for programming new data to a two-terminal memory device. Reduction in set and reset cycles can facilitate reduced wear over time, increasing longevity of the memory device and enabling larger numbers of lifetime array operations. Wear leveling can comprise comparing existing data stored within a target set of memory cells, to new data to be written to the target cells, and changing only cells having different values between the existing and new data. In some examples, new data can be inverted to reduce a number of program or erase pulses required to program the new data over the existing data, among other examples of disclosed wear leveling.

TECHNICAL FIELD

This disclosure relates generally to electronic memory; as one example, the disclosure describes an electronic memory comprising multiple banks of non-volatile memory with a high-speed interface and expanded command and address bus.

BACKGROUND

A recent innovation within the field of integrated circuit technology is two-terminal memory technology. Two-terminal memory technology is contrasted, for instance, with gate-controlled transistors in which conductivity between two terminals is mediated by a third terminal, called a gate terminal. Two-terminal memory devices can differ from three terminal devices in function as well as structure. For instance, some two-terminal devices can be constructed between a pair of conductive contacts, as opposed to having a third terminal that is adjacent to a set of conductive terminals. Rather than being operable through a stimulus applied to the third terminal, two-terminal memory devices can be controlled by applying a stimulus at one or both of the pair of conductive contacts. The inventor(s) of the present disclosure is further aware of a variety of two-terminal memory technologies, such as phase-change memory, magneto-resistive memory, conductive-bridging memory, as well as others.

One two-terminal memory worth noting is resistive memory. While much of resistive memory technology is in the development stage, various technological concepts for resistive memory have been demonstrated by the assignee of the present invention and are in one or more stages of verification to prove or disprove associated theory(ies). Even so, resistive memory technology promises to hold substantial advantages over competing technologies in the semiconductor electronics industry.

As models of resistive memory technology are tested and results obtained, the results are speculatively extrapolated to memory devices in which resistive memory replaces a conventional memory. For instance, the assignee of the present invention has conducted research related to software models of memory arrays comprising resistive memory instead of complementary metal-oxide semiconductor (CMOS) NAND or NOR memory. Software projections suggest that two-terminal memory arrays can provide significant benefits for electronic devices, including reduced power consumption, higher memory density, advanced technology nodes, or improved performance, among others.

In light of the above, the inventor(s) endeavors to discover applications where two-terminal memory can provide real-world benefits for electronic devices.

SUMMARY

The subject disclosure provides for improved cell longevity including wear leveling for a two-terminal memory device. In various disclosed embodiments, program operation management can be provided to reduce an average number of set or reset cycles applied to memory cells of the two-terminal memory device. Reduction in set and reset cycles can facilitate reduced wear in response to programming operations implemented over time, increasing longevity of the memory device.

In one or more embodiments, program operation management can comprise comparing existing data stored within a target set of memory cells, to new data to be written to the target cells. Cells that have different bits from the existing data to the new data are changed, whereas cells whose bits remain are not programmed or erased. In this manner, a subset of the target cells is affected by respective programming operations, and on average reducing a number of set or reset cycles for multiple programming events.

In further embodiments, program operation management can comprise sensing existing data and comparing existing data to new data to be written to a set of target cells. In one embodiment, if the existing data comprises more set states than reset states, the target cells can all be reset (e.g., erased) and then the set bits of the new data can be written to the respective subset of target cells. Likewise, if the existing data comprises more reset states, the target cells can all be set, and then reset bits of the new data can be written to respective ones of those target cells. In another embodiment, if the new data comprises more set states than reset states, the target cells can all be set, and the fewer reset states of the new data can be written to an associated subset of the target cells. Likewise, if the new data comprises more reset states, the target cells can all be reset, and the fewer set states can be programmed to respective ones of the target cells.

In further embodiments, the present disclosure can weight wear leveling operations toward a reset state, or toward a set state. The weight can be established based on physical characteristics of set operations or reset operations, in various embodiments. For instance, where reset power consumption is lower than set power consumption, wear leveling can weight toward the reset state. For two-terminal memory devices in which the reverse is true, wear leveling can be weighted to favor the set state.

In one or more additional embodiments, data can be inverted to facilitate weighting a reset or set state. Where a program operation would result in changing more bits of a target set of cells from an existing state to a new state than would remain the same, the data can be inverted, and an invert bit set to note the inversion of the target set of cells. After inversion, the fewer number of cells could be programmed to program the target set of cells to an inverted state of the new data. Where the program operation would result in fewer bits of the target cells being changed, the new data can be written directly to the fewer bits, without inverting the data and without setting the invert bit. The various disclosed techniques tend to reduce a number of bits that are affected by array operations, reducing average power utilized for array operations and, on average, reducing power consumption for an associated electronic device.

DETAILED DESCRIPTION

The present disclosure provides for data management techniques for improved longevity of two-terminal memory structures. Management of array operations to improve average cell longevity is often referred to as wear leveling. Non-volatile memory cells are often presumed to have a finite lifespan, for which data can be programmed to and reliably stored by the memory cells. Application of external stimulus to change data within these memory cells, while providing a mechanism for rewritable storage, can also affect physical characteristics of the memory cells. While these changes are small in response to single program or erase events, over time the changes can degrade the capacity to store data reliably. A memory cell that fails to meet a threshold probability of data retention has exhausted its useful lifespan, and is generally unusable and rendered inactive by controlling logic.

While an array of memory within a modern memory device has a very large number of memory cells, such that lifespan exhaustion (and inactivation) of a small percentage of memory cells may not noticeably affect the memory device, the inactivation of a few memory cells can be symptomatic of others being near end of useful life as well. Once a significant percentage of the array of memory cannot reliably store data, the memory device can also become unusable.

In some instances, the inventor(s) understands that a memory device can be detrimentally impacted by data management algorithms. For instance, some data stored at a memory device may be modified infrequently, whereas other data—such as maintenance or statistical data utilized to gauge efficacy of the memory device—may be updated quite regularly. If regularly updated data is written to a single block or blocks of memory cells of the memory device, these blocks will wear out quickly in terms of lifespan exhaustion. The inventor(s) is cognizant of wear leveling techniques that spread storage of regularly updated data over a much larger subset of a memory array than the size of the data, to spread out the program and erase operations associated with updating this data to the larger subset of the memory array. This type of wear leveling may extend memory device longevity, by mitigating early lifespan exhaustion of subsets of the memory array. (Matthew, what you're describing here is wear leveling technique done in flash. We are not doing that here. We are just minimizing the number of sets and rests in a cell. How frequent they're been accessed is not covered in this application; We're just minimizing the number of transitions; hence less wear and lower power.)

As an alternative to, or in addition to, the foregoing wear leveling techniques, the present disclosure provides for operational data management configured to reduce the average impact on memory cell longevity of respective program or erase operations. In various embodiments, the present disclosure can reduce impact of an array operation on a target subset of memory cells in response to changing a stored data pattern stored by the target subset of memory cells to a new data pattern. This can be accomplished, in some embodiments, by changing only memory cells that are different in the new data pattern from the stored data pattern. Because an x-bit (where x is a suitable positive integer) data pattern has a probability of having at least one bit in common with a new x-bit data pattern, changing only the bits that are not in common can reduce a number of program or erase cycles applied to individual memory cells to change the x-bit data pattern to the new x-bit data pattern. Reduction in number of program or erase cycles, as one example, is distinct from wear leveling techniques described above that do not affect a number of total write cycles, but rather spread out a given number of write cycles over larger sections of memory.

In still other embodiments, disclosed techniques can incorporate longevity-related characteristics of a memory device into data management techniques to extend memory cell longevity. Impact to longevity of a single program or erase cycle can be inversely related to power consumed by that program/erase cycle, or depending on technology, current consumption associated with the program or erase cycle. For resistive switching memory technologies, setting a bit to a low resistance state generally consumes significantly less current (and thus has lower impact on cell longevity) than resetting the bit to a high resistance state. Accordingly, various disclosed embodiments comprise weighting array operations toward resetting a memory cell, and away from setting the memory cell.

Referring now to the drawings,FIG. 1illustrates a block diagram of a sample two-terminal memory device100according to one or more embodiments of the present disclosure. Two-terminal memory device100can be integrated as part of an electronic device, providing non-volatile rewritable data storage (e.g., write/erase many, read many), or one-time programmable data storage (e.g., write once, read many), for such device. In other embodiments, two-terminal memory device100can be a removable memory product (e.g., thumb drive, universal serial bus (USB) memory device, mini-USB memory device, micro-USB memory device, nano-USB memory device, dual inline memory module, and so on), whereas in other embodiments two-terminal memory device100can be an embedded memory product.

Two-terminal memory device100can comprise a two-terminal memory cell array110, having one or more banks of memory (e.g., separately addressable and accessible subsets or arrays of memory) comprising a non-volatile, two-terminal memory cell technology. Examples of a suitable two-terminal memory cell technology can comprise resistive switching memory (e.g., resistive random access memory (RRAM)), phase-change memory, magneto-resistive memory, conductive bridging memory, organic memory, and others. Array operations can be implemented at two-terminal memory cell array100in response to program, erase, inhibit, etc., signals applied to addressable subsets thereof. Voltage generator logic120can be provided to form these or similar signals in response to suitable clock pulses (not depicted).

Additionally, two-terminal memory cell array110can comprise a sense amp140configured to receive signals stored by subsets of two-terminal memory cell array110, and measure a value of respective signals. Comparator logic130can be employed to interpret measured signal values into data (e.g., binary “0”s or “1”s). Additionally, a data latch150can receive data to be written to two-terminal memory cell array110, or data read from sense amps140and comparator logic130to be output to an external device. Such device can be accessed via one or more command/data interfaces160. Command/data interface(s)160can communicatively connect two-terminal memory device100with a control device, such as a memory controller, a computer, a host device, and so forth.

In some embodiments, disclosed data management techniques can be stored at an external control device. In such embodiments, instructions consistent with the data management techniques are generated by the external control device and provided to two-terminal memory device100over command/data interface(s)160. In other embodiments, two-terminal memory device100can store logic related to the data management techniques, and an onboard controller (not depicted, but seeFIGS. 17, 18, infra) can receive array operation commands over command/data interface(s)160, and translate or implement the commands consistent with the data management techniques described herein.

Referring toFIG. 2, there is illustrated a diagram of example state distributions200for a two-terminal memory device according to various embodiments of the present disclosure. The diagram for example state distributions200measures count of memory cells (e.g., number of memory cells within an array) on a vertical axis, and electrical current within a cell (e.g., in response to a specified voltage) on a horizontal axis. Three separate states are depicted: a suppressed state204, an off memory state206(e.g., 0 bit), and an on memory state208(e.g., 1 bit). Suppressed state204can represent a deactivated memory cell; this can occur, for instance, when a selection device associated with a memory cell has a high selection resistance, resulting in very low current through the memory cell (e.g., about 10E-14 amps at about 1.5 volts). Off memory state206can represent an activated memory cell, having a non-volatile device in a low memory state. This can be provided by the selector device being in an activated state having a low selection resistance, and the non-volatile device in the low memory state. This low memory state can exhibit about 1E-8 amps of current (e.g., at about 2 volts), and can be delineated by an off-state marker209A. On memory state208can represent an activated memory cell, having a non-volatile device in a high memory state. This can be provided by the selector device being in an activated state having low selection resistance, and the non-volatile device in a high memory state. The high memory state can exhibit about 1E-6 amps of current (e.g., at about 2 volts), and can be delineated by an on-state marker209B.

Examples of the low memory state and high memory state are illustrated by low state diagram214and high state diagram210. High state diagram210depicts a pair of electrodes, top electrode (TE) and bottom electrode (BE), with significant penetration of conductive particles between the TE and the BE, facilitating a relatively high conductance path212. The high conductance path212facilitates the relatively high 10E-6 current for the high memory state. Likewise, low state diagram214illustrates little penetration of conductive particles between the TE and the BE, resulting in a relatively low conductance path216. This low conductance path216facilitates the relatively low 10E-8 current for the low memory state.

It should be appreciated that example state distributions200are illustrative, and not intended to define or imply a scope of suitable memory devices to which the disclosed data management or wear leveling techniques can apply. As such, other state distributions associated with various memory devices can be employed for one or more disclosed embodiments. Further, some memory devices may not have a selector device, and thus the state distributions of such memory devices may have no suppressed state204, or can have different types of selection devices having different selection resistances, or can have multiple non-volatile cells activated or deactivated by a single selection device, and thus leakage current can result in different effective selection resistance per cell, and so on.

Though example state distributions200can vary according to memory cells employed for a memory device, they illustrate the difference in current consumption for an off memory state206and an on memory state208of some two-terminal memory technologies. This difference in current consumption can be leveraged by disclosed embodiments, to enhance longevity of memory cells. For instance, by managing memory array operations to favor switching from off memory state206to on memory state208, average current consumption can be reduced for respective array operations. This reduced current consumption can further increase memory cell longevity.

FIGS. 3A and 3Billustrate block diagrams of example circuit components300A,300B to facilitate wear leveling for an array operation according to embodiments of the present disclosure. Referring first toFIG. 3A, an existing data pattern302A is depicted, comprising a set of bits stored by two-terminal memory cells of a memory cell array, such as two-terminal memory cell array110ofFIG. 1, supra. Existing data pattern302A can be read into a set of sense amps (e.g., sense amps140) and bit values of existing data pattern302A determined by a comparator device (e.g., comparator logic130). Further, a new data pattern304A is depicted, to be written to the two-terminal memory cells. New data pattern304A can be received from a host or controller (e.g., over command/data interface(s)160) and stored in temporary memory (e.g., data latch150). Bit values of new data pattern304A can also be determined by the comparator device.

A first circuit component310A receives as inputs existing data pattern302A and new data pattern304A. Further, first circuit component310A can be configured to identify which bits of existing data pattern302A would have to be set to a “1” (e.g., programmed) from a “0”, to match corresponding bits of existing data pattern302A. An output of first circuit component310A is a group of set bits320A. Set bits320A are high (e.g., 1) for bits that are both “0” in existing data pattern302A and “1” in new data pattern304A, and low (e.g., “0”) for bits that are either not “0” in existing data pattern302A, or are not “1” in new data pattern304A. As depicted byFIG. 3A, a fifth bit from the left, bit322A, would be set from “0” to “1” to match new data pattern304A.

FIG. 3Billustrates a second circuit component310B also having inputs of existing data pattern302A and new data pattern304A. Second circuit component310B can be configured to identify which bits of existing data pattern302A would have to be reset to a “0” (e.g., erased) from a “1”, to match corresponding bits of existing data pattern304A. An output of second circuit component310B is a group of erase bits320B. Erase bits320B are low (e.g., “0”) for bits that are either not a “1” in existing data pattern302A, or are not a “0” in new data pattern304A, and are high (e.g., “1”) for bits that are both “1” in existing data pattern302A and “0” in new data pattern304A. Thus, for the example ofFIG. 3B, a third bit from the left322B and the right-most bit324B are high, and the other bits are low.

When taken together, set bits320A and erase bits320B identify which of the two terminal memory cells storing existing data pattern302A would need to be changed to write new data pattern304A to the two terminal memory cells. For the example ofFIGS. 3A and 3B, only three bits would need to be changed,322A,322B and324B, to write new data pattern304A to two-terminal memory cells storing existing data pattern302A. In conventional programming, all memory cells would be reset to 0 and new data would be programmed to the memory cells. For a 6-cell data set, this would involve six erase/program cycles. In various disclosed embodiments, only data required to be changed to match a new data pattern would receive a program or erase cycle; for the example ofFIGS. 3A and 3B, three program or erase cycles would be employed, significantly reducing the number of program/erase cycles required to write new data pattern304A to memory cells storing existing data pattern302A.

FIG. 4illustrates a diagram of an example memory device400associated with writing existing data pattern302A to new data pattern304A, according to embodiments of the present disclosure. Memory device400illustrates a set bits phase of the writing. As depicted, memory device400comprises a 6×6 cell array402of two-terminal memory cells, located at intersections of respective bitlines404and wordlines406of cell array402. Sense amps410can be employed to load data (e.g., read) from cells on one of wordlines406and comparator logic414for measuring bit values of the data loaded into sense amps410. Additionally, a data latch412can receive new data to be written to the cells of the wordline, and bit values of the new data can also be measured by comparator logic414.

Continuing the example ofFIGS. 3A and 3B, one memory cell408storing a “0” can be programmed to a “1”. The programming can be accomplished with a single program cycle of memory cell408, changing the data value stored by memory cell408to a “1”. For two-terminal memory cells such as resistive switching cells, this can be accomplished without first applying an erase pulse, in some embodiments.

Referring now toFIG. 5, a diagram of an example memory device500is depicted in an erase bits phase, according to further embodiments. Memory device500can be substantially similar to memory device400, including a 6×6 array of memory cells at intersections of respective bitlines404and wordlines406, and including sense amps410, data latch412and comparator logic414. Memory device500illustrates an erase phase of programming new data pattern304A to memory cells storing existing data pattern302A. Although the erase phase is illustrated as following program phase ofFIG. 4, supra, the erase phase can be implemented before the program phase, in various embodiments.

Two memory cells storing a “1” are changed to a “0” as part of the erase phase, including memory cell508A and memory cell508B. An erase cycle can be applied to each of these memory cells508A,508B, changing their bit values to “0”. The erase cycle can be facilitated with one erase pulse in various embodiments, depending on a technology employed for the memory cells of cell array402. As an example, resistive switching memory cells can be erased in response to a suitable negative voltage, though the negative voltage can comprise one or more sub-pulses of differing negative voltage values in some embodiments. Following the erase pulse depicted byFIG. 5and the program pulse depicted byFIG. 4, cell array402can be changed from existing data pattern302A to new data pattern304A with fewer program/erase pulses than would conventionally be employed. As a result, average longevity of memory cells on the target wordline can be increased by reducing overall exposure to program or erase pulses required to write new data over existing data.

As an addendum toFIGS. 4 and 5, it is noted that cell array402is illustrated as a one-transistor, many resistive (1TnR, where n is an integer greater than 1) cell array402. In such an arrangement, multiple memory cells are activated or deactivated by a single transistor. It should also be appreciated that the disclosed embodiments can be implemented with a one-transistor, one-resistor (1T1R) memory cell, in which each memory cells is activated or deactivated by its own transistor.

FIG. 6illustrates a diagram of an example set of programming sequences illustrating a selective write or erase programming, according to alternative or additional embodiments of the present disclosure. Selective write/erase programming can comprise determining whether an existing data pattern comprises more set bits (“1”s) than reset bits (“0”s). In the event of more set bits, the remainder of reset bits are set to make the existing data pattern comprised solely of set bits. In the event of more reset bits, the remainder of set bits are reset to make the existing data pattern comprised solely of reset bits (e.g., seeFIG. 9, infra, for an example flowchart of selective write/erase programming). From uniform set bits or uniform reset bits, a program phase is initiated in which “0”s (or “1”s) are programmed to respective ones of the uniform set bits (or reset bits) to match a new data pattern.

The set of programming sequences ofFIG. 6illustrate several set phase (or reset phase)—program phase combinations according to the selective write or erase programming. An initial erase state is illustrated by data set602. A set of new data 1-0-1-0-1-1 is received, and “1”s of the new data are programmed to the initial erase state resulting in data set604comprising the set of new data. Data set604comprises more “1”s than “0”s, and in response to receipt of a second new data set 0-1-0-1-0-0, a set phase is initiated and the two “0”s of data set604are set to “1”s, forming a uniform set data606. A program phase is initiated, resetting only bits that are “0” in the second new data set from “1” in the uniform set data606. The result is data set608. In response to a third new data set 1-1-0-0-1-1, data set608is analyzed to determine whether more “1”s or more “0”s exist in data set608. Since more “0”s exist, the “1”s are reset to form a uniform reset data610. Bits that are “1” in the third new data set are programmed from the uniform reset data610, to achieve data set612matching the third new data set. Because data set612has more “1”s than “0”s, the “0”s of data set612are programmed to “1”s in response to receipt of a fourth new data set 0-0-1-0-1-1, to form a uniform set data614. Bits that are “0” in the fourth new data set are erased from the uniform set data614, to achieve data set616matching the fourth new data set.

Selective write/erase programming600is an alternative mechanism to reduce a number of program/erase cycles involved in changing a data set to a new data set. As described above, conventional non-volatile programming first erases all cells of a target group of cells, then programs the target group of cells. In the event that most or all cells are programmed, the erasure of all cells applies an erase pulse to most or all cells of the target group. For the selective write/erase programming600, no more than half of a target group of cells can be subject to an erase pulse or program pulse, prior to subsequent programming. Accordingly, the selective write/erase programming600can reduce wear on the target group of cells, enhancing cell longevity.

In an alternative embodiment, selective program/erase programming600can determine whether new data has more “1”s or more “0”s, rather than existing data. In the alternative embodiment, respective “0” bits of existing data can be selectively set to achieve uniform set bits when the new data has more “1”s than “0”s. This ensures that the subsequent reset phase will apply an erase pulse to no more than half the bits. Likewise, respective “1” bits of existing data can be selectively reset to achieve uniform reset bits when the new data has more “0”s than “1”s. This ensures that a subsequent set phase will apply a program pulse to no more than half the bits. Accordingly, the selective program/erase programming can facilitate a reduction in average program or erase cycles to facilitate programming data to two-terminal memory cells.

FIG. 7illustrates a diagram of an example data comparator700to facilitate selective write or erase programming according to one or more embodiments of the present disclosure. As described atFIG. 6, selective write or erase programming can comprise determining whether existing data (or new data) comprises more “1”s than “0”s, and setting or resetting a data pattern to a uniform state before programming new data. In some embodiments, a set of existing data702is provided comprising a data pattern 0-1-1-1-0-1 (in other embodiments, set of existing data702can instead be a set of new data). Set bits of existing data702are identified in an erase bits710subgroup, which matches existing data702, and indicates a number of bits that would need to be erased to achieve uniform reset bits. In the example ofFIG. 7, erase bits710comprise four set bits, including bits712,714,716,718, which would require four bits to be reset to achieve the uniform reset bits. An inverter708is provided to generate a set bits720subgroup, which is an inversion of existing data702. The set bits subgroup720illustrates a number of bits that would have to be reset to achieve uniform set bits of existing data702. As indicated, only 2 bits, bits722and724, would be required to be set to “1” in existing data702to achieve the uniform set state. Accordingly, by selecting the uniform set state, a number of program or erase pulses required to achieve a uniform set or reset state can be reduced from four pulses (e.g., applied to712,714,716,718) to two pulses (e.g., applied to722,724).

In view of the exemplary diagrams described supra, process methods that can be implemented in accordance with the disclosed subject matter will be better appreciated with reference to the flow charts ofFIGS. 8-10, 15 and 16. While for purposes of simplicity of explanation, the methods ofFIGS. 8-10, 15 and 16are shown and described as a series of blocks, it is to be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders or concurrently with other blocks from what is depicted and described herein. Moreover, not all illustrated blocks are necessarily required to implement the methods described herein. Additionally, it should be further appreciated that some or all of the methods disclosed throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such methodologies to an electronic device. The term article of manufacture, as used, is intended to encompass a computer program accessible from any computer-readable device, device in conjunction with a carrier, or storage medium.

FIG. 8depicts a flowchart of an example method800for providing selective write/erase programming according to one or more disclosed embodiments. At802, method800can comprise receiving a command to program a subset of two-terminal memory with new data. At804, method800can comprise sensing existing data in the subset. At806, method800can comprise determining a number of set state bits or reset state bits in the new data. At808, method800can comprise determining whether more set state bits exist in the new data; method800can proceed to810if there are not more set bits in the new data, and can proceed to814if there are more set bits in the new data.

At810, method800can comprise erasing set states in existing data to erase states, resulting in the subset of memory cells all in a reset state. At812, method800can comprise programming suitable ones of the subset of memory cells to the set state that match set state bits of the new data. From812, method800can end at818.

At814, method800can comprise setting all erase state bits in the existing data to a set state, resulting in the subset of memory cells all in the set state. At816, method800can comprise erasing suitable ones of the subset of memory cells to the reset state to match reset state bits of the new data. At818, method800can end.

FIG. 9depicts a flowchart of a sample method900for providing selective write/erase programming according to alternative embodiments. At902, method900can comprise receiving a command to program a subset of two-terminal memory with new data. At904, method900can comprise sensing existing data in the subset of two-terminal memory. At906, method900can comprise determining a number of set state and erase state bits in the existing data. At908, method900can comprise determining whether the existing data has more set state bits or more reset state bits. If more set state bits, method900can proceed to914; otherwise, method900can proceed to910.

At910, method900can comprise erasing set state bits of the existing data to erase state bits, resulting in the subset of two-terminal memory being all in the reset state. At912, method900can comprise programming the set state bits of the new data to the subset of two-terminal memory. The new data is programmed to the subset of two-terminal memory following programming at912, and method900can proceed from912to918and end.

At914, method900can comprise setting all erase state bits in existing data to the set state, resulting in the subset of two-terminal memory being all in the set state. At916, method900can comprise erasing the reset state bits of the new data to the subset of two-terminal memory. Method900can proceed to918and end.

FIG. 10illustrates a diagram of an example set of write/erase sequences1000illustrating weighted write/erase programming according to alternative or additional embodiments of the present disclosure. The weighted write/erase programming can give preference to resetting bits or setting bits in advance of programming data to a subset of memory cells, depending on characteristics of a set pulse or reset pulse. For instance, where the reset pulse consumes less current or power than the set pulse, the weighted write/erase programming can reset any set bits of an existing data set, resulting in the subset of memory cells being in the reset state. Further, if the new data set comprises more set bit states, an invert memory bit can be set, and an inversion of the new data set can be written to the subset of memory cells. In this manner, no more than half the subset of memory cells will receive a set pulse when programming to the new data set. When the subset of memory cells is again reset, the invert memory bit can be reset.

The set of write/erase sequences1000begins with the subset of memory cells in a reset state1002. A first new data set 1-0-1-0-1-1 is received, having more set bit states than reset bit states. The invert bit is therefore set, and an inverted new data set is written to the subset of memory cells at1004. In response to receiving a second new data set 1-0-0-1-0-0, the subset of memory cells is again reset, requiring erasure of only two cells. The invert bit is reset, and because the second new data set has fewer set bits than reset bits, the two set bits are programmed to the subset of memory cells at1008. Following receipt of a third new data set 1-1-0-0-1-1, the two set bits from1008are reset during an erase phase at1010, and the invert bit is maintained in the reset state. Because the third new data set has more set bits than reset bits, the invert bit is set and an inverse of the third new data set is written to the subset of memory cells, again requiring only two program pulses at1012. The two set bits from1012are again reset at1014, along with the invert bit, in response to receipt of a fourth new data set 0-0-1-0-1-1. Because the number of set bits and reset bits is even, the fourth new data is written to the subset of memory cells with three program pulses at1016, and the invert bit is maintained in the reset state.

FIG. 11depicts a flowchart of an example method1100for providing weighted write/erase programming according to various embodiments. At1102, method1100can comprise receiving a command to program a subset of two terminal memory with new data. At1104, method1100can comprise sensing existing data in the subset of two terminal memory. At1106, method1100can comprise erasing set state bits of the subset of two terminal memory (if any) to a reset state and clearing an invert status bit. At1108, a determination is made as to whether more set state bits than reset state bits are in the new data. If the new data has more set state bits, method1100can proceed to1112; otherwise method1100can proceed to1110.

At1110, method1100can comprise programming set state bits of the new data to appropriate ones of the subset of two terminal memory. The programming can be accomplished by applying the program pulse to no more than half the subset of the two-terminal memory. From1110, method1100can proceed to1116and end.

At1112, method1100can comprise inverting the new data and programming set state bits of the inverted data to associated ones of the subset of two terminal memory. Additionally, at1114, the invert status bit is set. Again, the programming can be accomplished with programming no more than half the memory cells. In addition to the foregoing, to program additional data to the subset of two terminal memory, no more than half the memory cells will need to be erased to clear all of the subset of memory cells prior to the programming.

FIG. 12depicts a flowchart of an example method1200for providing weighted write/erase programming according to an alternative embodiment of the present disclosure. At1202, method1200can comprise receiving a command to program a subset of two terminal memory with new data. In some embodiments, the subset of two terminal memory can be erased prior to receiving the command, though in other embodiments existing data can be stored in the subset of two terminal memory. At1204, method1200can comprise sensing existing data in the subset of two terminal memory. At1206, method1200can comprise setting all erase state bits to a set state, and clearing an invert status bit. At1208, method1200can comprise determining whether more erase state bits than set state bits are contained in the new data. If the new data comprises more erase state bits, method1200can proceed to1212; otherwise method1200can proceed to1210.

At1210, method1200can comprise erasing appropriate ones of the subset of two terminal memory having reset bits in the new data. This results in the new data being written to the subset of two terminal memory utilizing such that no more than half the memory cells receive the erase pulse. Where the two terminal memory is a technology that consumes more current with the reset operation than with the set operation, setting all bits, then selectively resetting no more than half the bits to accomplish writing new data, can significantly increase longevity of the two terminal memory. From1210, method1200can proceed to1216and end.

At1212, method1200can comprise inverting the new data and erasing the reset state bits of the inverted new data to the subset of two terminal memory. At1214, method1200can comprise setting the invert status bit to indicate the data stored in the subset of two terminal memory is inverted data. By inverting the new data—even in the case where the new data comprises more reset bit states—the inverted new data is written to the subset of two terminal memory with erasing no more than half of those memory cells.

FIG. 13depicts a flowchart of a sample method1300for providing enhanced wear leveling and array management according to still other embodiments of the present disclosure. In one or more embodiments, method1300can combine benefits of previous disclose wear leveling and data management techniques. For instance, method1300can be configured to invert data requiring high current consumption operations, while programming or erasing only those bits required to change existing data to new data (or new inverted data).

At1302, method1300can comprise receiving a command to program a subset of two terminal memory with new data. The two terminal memory can be in an initial reset state (having all bits erased), or can store existing data. At1304, method1300can comprise sensing existing data in the subset of two terminal memory, and at1306, can comprise comparing existing data with the new data and outputting an exclusive-or (XOR) result of the comparison. At1308, a determination is made as to whether there are more set state bits than reset state bits in the exclusive-or result. If the exclusive-or output has more set state bits, method1300can proceed to1314; otherwise method1300can proceed to1310.

At1310, method1300can comprise programming bits that are set in the new data and reset in the existing data. At1312, method1300can comprise erasing bits that are reset in the new data and set in the existing data. From1312, method1300can proceed to1320and end.

At1314, method1300can comprise inverting new data and setting an invert status but. At1316, method1300can comprise programming bits that are set in the inverted data and erased in the existing data. At1318, method1300can comprise erasing bits that are reset in the inverted data and set in the existing data. From1318, method1300can proceed to1320and end.

FIG. 14depicts a diagram of example write/erase sequences1400associated with enhanced wear leveling and array management according to one or more disclosed embodiments. Write/erase sequences1400begin in an initial state, with all memory cells in a reset state1402. A first new data set 1-0-1-0-1-1 is received, and an exclusive-or comparison with reset state1402results in four set state bits for the exclusive-or comparison. Accordingly, the first new data is inverted, the invert status bit is set and two set bits in the inverted first new data are programmed to obtain inverted first new data set1404. A second new data set 1-0-0-1-0-0 is received and is compared in an exclusive-or comparison to inverted first new data set1404. The exclusive-or comparison comprises fewer set bits, and thus the invert status bit is cleared. A program phase is implemented, programming reset bits from inverted first new data set1404that are set in the second new data set, resulting in an intermediate data set1406. An erase phase then erases set bits from the inverted first new data set1404that are reset in the second new data set, resulting in the second new data set1408.

A third new data set 1-1-0-0-1-1 can be received, and compared in an exclusive-or to second new data set1408. The exclusive-or results in 5 set bits: bits that would have to be changed to transition from second new data set1408to the third new data set. Accordingly, the invert status is set and a program phase is implemented to program reset bits of second new data set1408that are set in inverted third new data set, resulting in a second intermediate data set1410. An erase phase erases set bits of second new data set1408that are reset in the inverted third new data set, resulting in an inverted third new data set1412. A fourth new data set 0-0-1-0-1-1 is compared in an exclusive-or to inverted third new data set1412. The exclusive-or has an equal number of set and reset bits (e.g., bits that need to be changed from inverted third new data set to achieve fourth new data set). Accordingly, in the embodiment depicted by write/erase sequences1400, the invert status bit is cleared and a program phase program reset bits of the inverted third new data set1412that are set in the fourth new data set for a third intermediate phase1414, and an erase phase erases set bits of the inverted third new data set that are reset in the fourth new data set, resulting in fourth new data set1416. In another embodiment, the invert bit status can be maintained in the set position and suitable write/erase sequences (not depicted by write/erase sequences1400) as described herein can be implemented for inverted third new data set1412to achieve new data set1416.

FIG. 15illustrates a flowchart of a sample method for providing wear leveling in one or more further embodiments of the present disclosure. At1502, method1500can comprise receiving a command to program a subset of two terminal memory with new data. At1504, method1500can comprise sensing existing data in the subset of two terminal memory, and at1506method1500can comprise comparing existing data of the subset of two terminal memory with the new data. In various embodiments, method1500can additionally comprise identifying reset bits in the existing data that are set bits in the new data, and identifying set bits in the existing data that are reset bits in the new data. At1508, method1500can comprise erasing bits that are reset in the new data and set in the existing data. At1510, method1500can comprise programming bits that are set in the new data and reset in the existing data.

FIG. 16illustrates a flowchart of a sample method1600according to further embodiments of the present disclosure. At1602, method1600can comprise receiving a command to program a subset of two terminal memory with new data. At1602, method1600can comprise sensing existing data in the subset of two terminal memory, and at1606, method1600can comprise comparing existing data with the new data. At1608, a determination is made as to whether more erase pulses are required to program the new data, or more program pulses. If more erase pulses are required and, e.g., erase pulses consume more current than program pulses, method1600can proceed to1614; otherwise, if more program pulses are required, method1600can proceed to1610.

In an alternative embodiment, the determination at reference number1608can incorporate a threshold criterion (e.g., a threshold number of erase pulses, a first threshold power consumption, etc.) in determining whether method1600proceeds to reference number1610or reference number1614. As a first example, the determination can be set to prefer a lower power pulse; a program pulse can be preferred over an erase pulse if the program pulse consumes less power, and vice versa. For resistive switching memory, a cycle in which a cell begins in a resistive state and ends in a conductive state can consume less power, since large current flow does not occur until the cell switches to the conductive state. If such a cycle describes a program operation, then the program operation can consume less power for the resistive switching memory, and vice versa where such a cycle describes an erase operation. In this case, the threshold criterion could favor the lower power operation by a number, x, of program versus erase pulses. Thus, where x is 0, an equal number of lower power pulses (e.g., program) and higher power pulses (e.g., erase) can satisfy the threshold criterion, potentially resulting in bit inversion at reference number1616, below. Where x is 1, one fewer lower power pulse than higher power pulses can satisfy the threshold criterion, where x is 2, two fewer lower power pulses than higher power pulses can satisfy the threshold criterion, and so on. As another example, the threshold criterion can be a power consumption criterion. In this case, where the number of high power pulses consumes the same or about the same total power as the number of low power pulses (presuming a smaller number of the high power pulses), then method1600can proceed to1610and avoid bit inversion. Where the high power pulses consumes more than the low power pulses, or some percentage y more power (e.g., 55% more power, 60% more power, 70% more power, etc.), the threshold criterion can be met, causing method1600to proceed to1614and possibly inverting bits.

At1610, method1600can comprise erasing “1”s in the existing data that are “0”s in the new data. At1612, method1600can comprise programming “0”s in the existing data that are “1”s in the new data. From1612, method1600can end at1622.

At1614, an optional determination is made as to whether a number of the erase pulses exceeds a second power consumption threshold. This step can be skipped in some embodiments, for instance, where power consumption is utilized as a threshold criterion at reference number1608, as described above. Where utilized, the power consumption threshold at1614can be an additional criterion (e.g., to a numerical criterion at1608that compares numbers of pulses, as one example) for bit inversion at1616. The second power consumption threshold can be similar to the first power consumption threshold, described above. In other embodiments, the second power consumption threshold can be an absolute power consumption (e.g., total electrical power consumed by the sum of the erase pulses), rather than a relative power consumption (e.g., power consumed by erase pulses vs. power consumed by program pulses). If the erase pulses do not exceed the second power consumption threshold, method1600can proceed to reference number1610, as described above; otherwise, method1600can proceed to1616and invert the existing data, and set an invert status bit. At1618, method1600can comprise programming “0”s in existing data that are “1”s in inverted new data. At1620, method1600can comprise erasing “1”s in the existing data that are “0”s in the inverted new data. Method1600can then end at1622.

FIG. 17illustrates a block diagram of an example operating and control environment1700for a memory array1702of a memory cell array according to aspects of the subject disclosure. In at least one aspect of the subject disclosure, memory array1702can comprise memory selected from a variety of memory cell technologies. In at least one embodiment, memory array1702can comprise a two-terminal memory technology, arranged in a compact two or three dimensional architecture. Suitable two-terminal memory technologies can include resistive-switching memory, conductive-bridging memory, phase-change memory, organic memory, magneto-resistive memory, or the like, or a suitable combination of the foregoing.

A column controller1706and sense amps1708can be formed adjacent to memory array1702. Moreover, column controller1706can be configured to activate (or identify for activation) a subset of bit lines of memory array1702. Column controller1706can utilize a control signal provided by a reference and control signal generator(s)1718to activate, as well as operate upon, respective ones of the subset of bitlines, applying suitable program, erase or read voltages to those bitlines. Non-activated bitlines can be kept at an inhibit voltage (also applied by reference and control signal generator(s)1718), to mitigate or avoid bit-disturb effects on these non-activated bitlines.

In addition, operating and control environment1700can comprise a row controller1704. Row controller1704can be formed adjacent to and electrically connected with word lines of memory array1702. Also utilizing control signals of reference and control signal generator(s)1718, row controller1704can select particular rows of memory cells with a suitable selection voltage. Moreover, row controller1704can facilitate program, erase or read operations by applying suitable voltages at selected word lines.

Sense amps1708can read data from, or write data to the activated memory cells of memory array1702, which are selected by column control1706and row control1704. Data read out from memory array1702can be provided to an input/output buffer1712. Likewise, data to be written to memory array1702can be received from the input/output buffer1712and written to the activated memory cells of memory array1702.

A clock source(s)1708can provide respective clock pulses to facilitate timing for read, write, and program operations of row controller1704and column controller1706. Clock source(s)1708can further facilitate selection of word lines or bit lines in response to external or internal commands received by operating and control environment1700. Input/output buffer1712can comprise a command and address input, as well as a bidirectional data input and output. Instructions are provided over the command and address input, and the data to be written to memory array1702as well as data read from memory array1702is conveyed on the bidirectional data input and output, facilitating connection to an external host apparatus, such as a computer or other processing device (not depicted, but see e.g., computer1102ofFIG. 11, infra).

Input/output buffer1712can be configured to receive write data, receive an erase instruction, receive a status or maintenance instruction, output readout data, output status information, and receive address data and command data, as well as address data for respective instructions. Address data can be transferred to row controller1704and column controller1706by an address register1710. In addition, input data is transmitted to memory array1702via signal input lines between sense amps1708and input/output buffer1712, and output data is received from memory array1702via signal output lines from sense amps1708to input/output buffer1712. Input data can be received from the host apparatus, and output data can be delivered to the host apparatus via the I/O bus.

Commands received from the host apparatus can be provided to a command interface1716. Command interface1716can be configured to receive external control signals from the host apparatus, and determine whether data input to the input/output buffer1712is write data, a command, or an address. Input commands can be transferred to a state machine1720.

State machine1720can be configured to manage programming and reprogramming of memory array1702(as well as other memory banks of a multi-bank memory array). Instructions provided to state machine1720are implemented according to control logic configurations, enabling state machine to manage read, write, erase, data input, data output, and other functionality associated with memory cell array1702. In some aspects, state machine1720can send and receive acknowledgments and negative acknowledgments regarding successful receipt or execution of various commands. In further embodiments, state machine1720can decode and implement status-related commands, decode and implement configuration commands, and so on.

To implement read, write, erase, input, output, etc., functionality, state machine1720can control clock source(s)1708or reference and control signal generator(s)1718. Control of clock source(s)1708can cause output pulses configured to facilitate row controller1704and column controller1706implementing the particular functionality. Output pulses can be transferred to selected bit lines by column controller1706, for instance, or word lines by row controller1704, for instance.

With reference toFIG. 18, a suitable operating environment1800for implementing various aspects of the claimed subject matter includes a computer1802. The computer1802includes a processing unit1804, a system memory1806, a codec1835, and a system bus1808. The system bus1808communicatively inter-connects system components including, but not limited to, the system memory1806to the processing unit1804. The processing unit1804can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit1804.

The system memory1806includes volatile memory1810and non-volatile memory1814, which can employ one or more of the disclosed memory architectures, in various embodiments. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer1802, such as during start-up, is stored in non-volatile memory1812. In addition, according to present innovations, codec1835may include at least one of an encoder or decoder, wherein the at least one of an encoder or decoder may consist of hardware, software, or a combination of hardware and software. Although, codec1835is depicted as a separate component, codec1835may be contained within non-volatile memory1812. By way of illustration, and not limitation, non-volatile memory1812can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), Flash memory, or two-terminal memory (e.g., resistive-switching memory). Non-volatile memory1812can employ one or more of the disclosed memory architectures, in at least some disclosed embodiments. Moreover, non-volatile memory1812can be computer memory (e.g., physically integrated with computer1802or a mainboard thereof), or removable memory. Examples of suitable removable memory with which disclosed embodiments can be implemented can include a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) memory stick, or the like. Volatile memory1810includes random access memory (RAM), which acts as external cache memory, and can also employ one or more disclosed memory architectures in various embodiments. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM), and so forth.

Computer1802may also include removable/non-removable, volatile/non-volatile computer storage medium.FIG. 18illustrates, for example, disk storage1814. Disk storage1814includes, but is not limited to, devices such as a magnetic disk drive, solid state disk (SSD) floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flash memory card, or memory stick. In addition, disk storage1814can include storage medium separately or in combination with other storage medium including, but not limited to, an optical disk drive such as a compact disk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RW Drive) or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of the disk storage1814to the system bus1808, a removable or non-removable interface is typically used, such as interface1816. It is appreciated that disk storage1814can store information related to a user. Such information might be stored at or provided to a server or to an application running on a user device. In one embodiment, the user can be notified (e.g., by way of output device(s)1836) of the types of information that are stored to disk storage1814and/or transmitted to the server or application. The user can be provided the opportunity to opt-in or opt-out of having such information collected and/or shared with the server or application (e.g., by way of input from input device(s)1828).

It is to be appreciated thatFIG. 18describes software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment1800. Such software includes an operating system1818. Operating system1818, which can be stored on disk storage1814, acts to control and allocate resources of the computer1802. Applications1820take advantage of the management of resources by operating system1818through program modules1824, and program data1826, such as the boot/shutdown transaction table and the like, stored either in system memory1806or on disk storage1814. It is to be appreciated that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.

A user enters commands or information into the computer1802through input device(s)1828. Input devices1828include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit1804through the system bus1808via interface port(s)1830. Interface port(s)1830include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s)1836use some of the same type of ports as input device(s)1828. Thus, for example, a USB port may be used to provide input to computer1802and to output information from computer1802to an output device1836. Output adapter1834is provided to illustrate that there are some output devices, such as monitors, speakers, and printers, among other output devices, which require special adapters. The output adapter1834can include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device1836and the system bus1808. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s)1838.

Computer1802can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s)1838. The remote computer(s)1838can be a personal computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device, a smart phone, a tablet, or other network node, and typically includes many of the elements described relative to computer1802. For purposes of brevity, only a memory storage device1840is illustrated with remote computer(s)1838. Remote computer(s)1838is logically connected to computer1802through a network interface1842and then connected via communication connection(s)1844. Network interface1842encompasses wire and/or wireless communication networks such as local-area networks (LAN) and wide-area networks (WAN) and cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL).

Communication connection(s)1844refers to the hardware/software employed to connect the network interface1842to the system bus1808. While communication connection1844is shown for illustrative clarity inside computer1802, it can also be external to computer1802. The hardware/software necessary for connection to the network interface1842includes, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

The illustrated aspects of the disclosure may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules or stored information, instructions, or the like can be located in local or remote memory storage devices.

Moreover, it is to be appreciated that various components described herein can include electrical circuit(s) that can include components and circuitry elements of suitable value in order to implement the embodiments of the subject disclosure. Furthermore, it can be appreciated that many of the various components can be implemented on one or more IC chips. For example, in one embodiment, a set of components can be implemented in a single IC chip. In other embodiments, one or more of respective components are fabricated or implemented on separate IC chips.

As utilized herein, terms “component,” “system,” “architecture” and the like are intended to refer to a computer or electronic-related entity, either hardware, a combination of hardware and software, software (e.g., in execution), or firmware. For example, a component can be one or more transistors, a memory cell, an arrangement of transistors or memory cells, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, a process running on the processor, an object, executable, program or application accessing or interfacing with semiconductor memory, a computer, or the like, or a suitable combination thereof. The component can include erasable programming (e.g., process instructions at least in part stored in erasable memory) or hard programming (e.g., process instructions burned into non-erasable memory at manufacture).

By way of illustration, both a process executed from memory and the processor can be a component. As another example, an architecture can include an arrangement of electronic hardware (e.g., parallel or serial transistors), processing instructions and a processor, which implement the processing instructions in a manner suitable to the arrangement of electronic hardware. In addition, an architecture can include a single component (e.g., a transistor, a gate array, . . . ) or an arrangement of components (e.g., a series or parallel arrangement of transistors, a gate array connected with program circuitry, power leads, electrical ground, input signal lines and output signal lines, and so on). A system can include one or more components as well as one or more architectures. One example system can include a switching block architecture comprising crossed input/output lines and pass gate transistors, as well as power source(s), signal generator(s), communication bus(ses), controllers, I/O interface, address registers, and so on. It is to be appreciated that some overlap in definitions is anticipated, and an architecture or a system can be a stand-alone component, or a component of another architecture, system, etc.

In addition to the foregoing, the disclosed subject matter can be implemented as a method, apparatus, or article of manufacture using typical manufacturing, programming or engineering techniques to produce hardware, firmware, software, or any suitable combination thereof to control an electronic device to implement the disclosed subject matter. The terms “apparatus” and “article of manufacture” where used herein are intended to encompass an electronic device, a semiconductor device, a computer, or a computer program accessible from any computer-readable device, carrier, or media. Computer-readable media can include hardware media, or software media. In addition, the media can include non-transitory media, or transport media. In one example, non-transitory media can include computer readable hardware media. Specific examples of computer readable hardware media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips . . . ), optical disks (e.g., compact disk (CD), digital versatile disk (DVD) . . . ), smart cards, and flash memory devices (e.g., card, stick, key drive . . . ). Computer-readable transport media can include carrier waves, or the like. Of course, those skilled in the art will recognize many modifications can be made to this configuration without departing from the scope or spirit of the disclosed subject matter.

What has been described above includes examples of the subject innovation. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the subject innovation, but one of ordinary skill in the art can recognize that many further combinations and permutations of the subject innovation are possible. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure. Furthermore, to the extent that a term “includes”, “including”, “has” or “having” and variants thereof is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.

Additionally, some portions of the detailed description have been presented in terms of algorithms or process operations on data bits within electronic memory. These process descriptions or representations are mechanisms employed by those cognizant in the art to effectively convey the substance of their work to others equally skilled. A process is here, generally, conceived to be a self-consistent sequence of acts leading to a desired result. The acts are those requiring physical manipulations of physical quantities. Typically, though not necessarily, these quantities take the form of electrical and/or magnetic signals capable of being stored, transferred, combined, compared, and/or otherwise manipulated.

It has proven convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise or apparent from the foregoing discussion, it is appreciated that throughout the disclosed subject matter, discussions utilizing terms such as processing, computing, replicating, mimicking, determining, or transmitting, and the like, refer to the action and processes of processing systems, and/or similar consumer or industrial electronic devices or machines, that manipulate or transform data or signals represented as physical (electrical or electronic) quantities within the circuits, registers or memories of the electronic device(s), into other data or signals similarly represented as physical quantities within the machine or computer system memories or registers or other such information storage, transmission and/or display devices.

In regard to the various functions performed by the above described components, architectures, circuits, processes and the like, the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., a functional equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary aspects of the embodiments. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. It will also be recognized that the embodiments include a system as well as a computer-readable medium having computer-executable instructions for performing the acts and/or events of the various processes.