Semiconductor device

A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110. Thus, there is provided a semiconductor device composed of a plurality of internally connected semiconductor chips, such that the semiconductor device is easy to produce and requires a reduced number of component elements.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly to a semiconductor device composed of a plurality of laminated semiconductor chips having substantially the same outer contour with one another, with an integrated circuit being formed on one of the principal faces of each semiconductor chip.

2. Description of the Background Art

In recent years, in the field of semiconductor devices, so-called “system-in-package” technology has gained more importance. According to system-in-package” technology, a single semiconductor device incorporating a plurality of semiconductor chips having different functions is constructed. In addition to being downsized, a semiconductor device constructed according to this technology can provide a realize a highly functional system where the semiconductor chips are able to mutually exchange data within the semiconductor device.

A conventional semiconductor device which is constructed according to system-in-package technology is disclosed in Japanese Patent Laid-Open Publication No. 2003-23136. As shown inFIG. 18, this conventional semiconductor device has a structure such that a memory chip1014and a microcomputer chip1015are attached to each other “back-to-back”, i.e., so that a face of each of the chips1014and1015having circuitry formed thereon is facing outwards. The metal wires taken out from the memory chip1014and the microcomputer chip1015are electrically connected to each other, via a conductive common lead1024. Thus, electrical conduction between the memory chip1014and the microcomputer chip1015is achieved.

However, in the conventional semiconductor device, the conductive common lead1024is composed as a separated element from external terminals1025and a die pad1017, and as such, needs to be affixed by means of an insulative piece1026as shown inFIG. 18, in order to be stabilized in place within the semiconductor device. This results in an increase in the number of component elements used in the semiconductor device. Furthermore, in order to connect the common lead1024to both the memory chip1014and the microcomputer chip1015by means of metal wires, it is necessary to position the common lead1024precisely with respect to both the memory chip1014and the microcomputer chip1015. Such a precise positioning for the common lead1024is a hindrance to a rapid assembling of the semiconductor device.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a semiconductor device composed of a plurality of interconnected semiconductor chips, such that the semiconductor device is easy to produce and requires a reduced number of component elements.

The present invention has the following features to attain the object mentioned above.

A first embodiment of the present invention is directed to a semiconductor device including a plurality of layers of semiconductor chips having substantially the same outer contour, with an integrated circuit being formed on a principal face of each semiconductor chip, comprising: anon-conductive layer having a conductive portion provided thereon, and an internal connection member for internally connecting the integrated circuits formed on the plurality of semiconductor chips via the conductive portion provided on the non-conductive layer, wherein the conductive portion provided on the non-conductive layer only mediates internal connection between the integrated circuits formed on the plurality of semiconductor chips.

According to a second aspect based on the first aspect, the plurality of semiconductor chips comprise a first semiconductor chip and a second semiconductor chip, and the internal connection member comprises: a first connection member for connecting the first semiconductor chip to the conductive portion; and a second connection member for connecting the second semiconductor chip to the conductive portion.

According to a third aspect based on the second aspect, the non-conductive layer has a circuit formed thereon, and the conductive portion comprises a conductive subportion which is connected to the first connection member and a conductive subportion which is connected to the second connection member, the conductive subportions being in electrical conduction by way of the circuit formed on the non-conductive layer.

According to a fourth aspect based on the third aspect, the non-conductive layer includes a circuit formed on each of two principal faces thereof.

According to a fifth aspect based on the second aspect, the non-conductive layer is layered between the first semiconductor chip and the second semiconductor chip.

According to a sixth aspect based on the fifth aspect, the first semiconductor chip and the second semiconductor chip are disposed so that the respective principal faces of the first and second semiconductor chips having the integrated circuits formed thereon face away from each other, with the non-conductive layer being interposed between the other principal faces of the first and second semiconductor chips.

According to a seventh aspect based on the sixth aspect, the conductive subportion which is connected to the first connection member is formed on a principal face of the non-conductive layer which is oriented in the same direction as the principal face of the first semiconductor chip on which the integrated circuit is formed.

According to an eighth aspect based on the first aspect, the non-conductive layer is a mount on which the plurality of semiconductor chips are placed.

According to a ninth aspect based on the first aspect, the conductive portion is formed by plating, with a conductive material, a portion of the non-conductive layer that lies outside of an outer contour of the plurality of semiconductor chips when the plurality of semiconductor chips and the non-conductive layer are layered in place.

According to a tenth aspect based on the ninth aspect, the conductive material is a metal.

According to an eleventh aspect based on the ninth aspect, the portion of the non-conductive layer that lies outside of the outer contour of the plurality of semiconductor chips is a protrusion from the non-conductive layer.

According to a twelfth aspect based on the ninth aspect, the plurality of semiconductor chips and the non-conductive layer are encased in a package, the non-conductive layer further includes a plurality of supporting legs for stabilizing to the package a portion of the non-conductive layer on which the plurality of semiconductor chips are placed, the plurality of supporting legs being connected to one another by a bridge, and the portion of the non-conductive layer that lies outside of the outer contour of the plurality of semiconductor chips forms the bridge.

According to a thirteenth aspect based on the first aspect, the conductive portion is composed of a conductive piece embedded in an aperture formed through a portion of the non-conductive layer that lies outside of an outer contour of the plurality of semiconductor chips when the plurality of semiconductor chips and the non-conductive layer are layered in place.

According to a fourteenth aspect based on the fifth aspect, the first connection member is composed of a conductive piece embedded in an aperture formed through the first semiconductor chip, the second connection member is composed of a conductive piece embedded in an aperture formed through the second semiconductor chip, the first connection member and the second connection member are formed in positions which coincide when the first semiconductor chip and the second semiconductor chip are layered in place, and the conductive portion comprises conductive pieces embedded in apertures formed through portions of the non-conductive layer that come in contact with the first connection member and the second connection member, respectively, when the first semiconductor chip and the second semiconductor chip are layered in place.

According to a fifteenth aspect based on the thirteenth or fourteenth aspect, the conductive pieces comprised by the conductive portion are metal pieces.

According to a sixteenth aspect based on the fourteenth aspect, the conductive piece composing the first connection member is a metal piece.

According to a seventeenth aspect based on the fifth aspect, the first connection member is composed of a conductive piece embedded in an aperture formed through the first semiconductor chip, the second connection member is composed of a conductive piece embedded in an aperture formed through the second semiconductor chip, and the conductive portion comprises: a conductive subportion composed of a conductive piece embedded in an aperture formed through a portion of the non-conductive layer that comes in contact with the first connection member when the first semiconductor chip and the second semiconductor chip are layered in place, and a circuit for electrically connecting the conductive subportion to a portion of the non-conductive layer that comes in contact with the second connection member when the first semiconductor chip and the second semiconductor chip are layered in place.

According to an eighteenth aspect based on the second aspect, the first semiconductor chip is disposed so that a principal face of the first semiconductor chip not bearing the integrated circuit opposes one of principal faces of the non-conductive layer, and the second semiconductor chip is disposed so that a principal face of the second semiconductor chip having the integrated circuit formed thereon opposes the other principal face of the non-conductive layer.

According to a nineteenth aspect based on the eighteenth aspect, the second connection member is a metal bump provided on the second semiconductor chip, the conductive portion including: a conductive subportion embedded in an aperture formed through a portion of the non-conductive layer that comes in contact with the bump when the second semiconductor chip and the non-conductive layer are layered in place, and a circuit, formed on the principal face of the non-conductive layer opposed by the first semiconductor chip, for electrically connecting the conductive subportion to the first connection member.

According to a twentieth aspect based on the second aspect, the second semiconductor chip is disposed so that a principal face of the second semiconductor chip not bearing the integrated circuit contacts a principal face of the non-conductive layer, the semiconductor device further comprising: a spacer having an outer contour which is smaller than an outer contour of the first semiconductor chip and the second semiconductor chip, the spacer being disposed on the principal face of the second semiconductor chip having the integrated circuit formed thereon, and the first semiconductor chip is disposed so that a principal face of the first semiconductor chip not bearing the integrated circuit contacts an upper face of the spacer.

A twenty-first aspect of the present invention is directed to a semiconductor device including a plurality of layers of semiconductor chips having substantially the same outer contour, with an integrated circuit being formed on a principal face of each semiconductor chip, comprising: a non-conductive layer having a first conductive portion and a second conductive portion provided thereon, and an internal connection member for internally connecting the integrated circuits formed on the plurality of semiconductor chips via the first conductive portion provided on the non-conductive layer, wherein the second conductive portion provided on the non-conductive layer is a terminal for connecting the integrated circuits formed on the plurality of semiconductor chips to an external circuit.

Thus, according to the first aspect above, a conductive portion is formed on the non-conductive piece so that it is unnecessary to pay particular attention to the positioning of the conductive portion when assembling the semiconductor chips and other elements. Since the conductive portion is provided on the non-conductive piece, the number of component elements used in the semiconductor device can be reduced. Since the conductive portion is not used for external connection of the semiconductor device, no external leads need to be wasted for internal connection purposes as in the case of conventional semiconductor devices.

According to the second aspect above, integrated circuits formed on the first semiconductor chip and the second semiconductor chip composing the semiconductor device can be internally connected.

According to the third aspect above, a circuit formed on a principal face of the non-conductive layer makes it possible to interconnect the conductive subportion which is connected to the first connection member and the conductive subportion which is connected to the second connection member even in the case where they are in distant positions. As a result, even if an output section of the integrated circuit on the first semiconductor chip and an output section of the integrated circuit on the second semiconductor chip are distant from each other, then can still be internally connected.

According to the fourth aspect above, the aforementioned circuit is formed on each of the two principal faces of the non-conductive layer, thus providing for a greater variety of internal connection methods. For example, a circuit which would otherwise have intersecting paths on the non-conductive layer can be split into non-intersecting sub-circuits separated on different principal faces.

According to the fifth aspect above, the thickness of the present semiconductor device can be reduced.

According to the sixth aspect above, the integrated circuits formed on the semiconductor chip are exposed, thus making it easier to connect wires to the integrated circuits for internal connection purposes.

According to the seventh aspect above, the connection members are connected to faces which are oriented in the same direction, so that the conductive portions can be easily connected to the integrated circuits by means of wires.

According to the eighth aspect above, the non-conductive layer serves as a mount, whereby the number of component elements can be reduced.

According to the tenth aspect above, the conductive portion is formed by plating, and as such, the conductive portion can be produced inexpensively and cheaply.

According to the eleventh aspect above, a protrusion from the non-conductive layer functions as the conductive portion, which is the close vicinity of the non-conductive layer itself. As a result, the distances between the integrated circuits on the semiconductor chips and the conductive portion can be reduced.

According to the twelfth aspect above, the conductive portion is disposed on abridge. The bridge, which is constructed so as to connect the plurality of supporting legs to one another, can have various shapes. This also introduces a greater variety for the disposition of the conductive portion.

According to the thirteenth aspect above, the conductive portion is composed of an embedded conductive piece. Therefore, the conductive portion is free from fluctuations which would result from a plating process, thereby providing for a better connectability between the first semiconductor chip and the second semiconductor chip.

According to the fourteenth aspect above, the first connection member and the second connection member are composed of conductive pieces embedded in apertures, so that these two connection members do not extend outside the semiconductor chips. As a result, the present semiconductor device can be made more compact than in the case where the first connection member and the second connection member are composed of wires or the like.

According to the seventeenth aspect above, the first connection member and the second connection member are composed of conductive pieces embedded in apertures, so that these two connection members do not extend outside the semiconductor chips. As a result, the present semiconductor device can be made more compact than in the case where the first connection member and the second connection member are composed of wires or the like. The circuit provided on the non-conductive layer allows the first semiconductor chip to be internally connected to the second semiconductor chip even in the case where the first connection member and the second connection member are formed in distant positions.

According to the eighteenth aspect above, the integrated circuits on the semiconductor devices can be internally connected to each other even in the case where they are formed on faces that are oriented in the same direction.

According to the nineteenth aspect above, the integrated circuits on the semiconductor devices can be internally connected to each other even in the case where they are formed on faces that are oriented in the same direction.

According to the twentieth aspect above, the two semiconductor chips can be internally connected to each other even in the case where the non-conductive layer is disposed underneath the two semiconductor chips.

According to the twenty-first aspect above, the conductive portion is provided on a terminal for connecting the integrated circuits to an external circuit. Therefore, the positioning of the conductive portion can be finalized as the positioning of this terminal is set. Since the conductive portion is made integral with the terminal, the number of component elements can be reduced.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device according to each embodiment of the present invention includes a plurality of bear semiconductor chips which are preferably encased in a common package. Each bear semiconductor chip has an integrated circuit formed on one of the two principal faces thereof (hereinafter, such a principal face of each semiconductor chip will be referred to as a “circuit face”). The circuit face of each semiconductor chip is internally connected to the circuit face(s) of the other semiconductor chip(s). As used herein, when a plurality of semiconductor chips composing a semiconductor device are said to be “internally connected” to one another, it is meant that the integrated circuits of the respective semiconductor chips are interconnected, within the semiconductor device, so that the integrated circuits can work in cooperation. Each of the embodiments below illustrates a semiconductor device incorporating such a plurality of semiconductor chips internally connected to one another.

A semiconductor device according to a first embodiment of the present invention will be described with reference toFIGS. 1A,1B,1C, andFIG. 2.

FIGS. 1A,1B, and1C are perspective views showing the outer appearance of component elements used in the semiconductor device according to the first embodiment of the present invention.FIG. 1Ashows a first semiconductor chip102.FIG. 1Bshows a die pad107.FIG. 1Cshows a second semiconductor chip103, with a front face being shown in the left-hand view, and a back face shown in the right-hand view. The semiconductor device according to the present embodiment is constructed by attaching the first semiconductor chip102shown inFIG. 1A, the die pad107shown inFIG. 1B, and the second semiconductor chip103shown inFIG. 1Cto one another. Hereinafter, each component element will be described in detail.

The first semiconductor chip102includes circuitry formed on a face shown upwards inFIG. 1A, and includes connection pads108formed on this circuit face. The connection pads108are used for external connection or for connection with the second semiconductor chip103. The die pad107serves as a non-conductive mount on which to place the first semiconductor chip102and the second semiconductor chip103. The die pad107includes a non-conductive mount portion111and conductive connection members110formed on the mount portion111. The mount portion111has substantially the same outer contour as that of the first semiconductor chip102and the second semiconductor chip103. The first semiconductor chip102is to be attached to the face of the mount portion111shown upwards inFIG. 1B, and the second semiconductor chip103is to be attached to the opposite face of the mount portion111. The conductive connection members110can be obtained by plating protrusions which are formed on a non-conductive piece composing the mount portion111. The second semiconductor chip103has substantially the same size as that of the first semiconductor chip102. The second semiconductor chip103includes circuitry formed on its back face shown in the right-hand view ofFIG. 1C, and includes connection pads109formed on this circuit face. The connection pads109are used for external connection or for connection with the first semiconductor chip102.

Now, the structure of the semiconductor device according to the present embodiment will be described.FIG. 2is a partially-cutaway perspective view showing the outer appearance of the semiconductor device according to the first embodiment of the present invention.

As shown inFIG. 2, the semiconductor device according to the present embodiment comprises a package101, the first semiconductor chip102shown inFIG. 1A, the second semiconductor chip103shown inFIG. 1C, inter-chip connection wires104aand104b, external connection wires105, external leads106, and the die pad107shown inFIG. 1B. InFIG. 2, the outer framework of the die pad107(FIG. 1B) is omitted from illustration because the framework is to be cut off after the semiconductor device is sealed with the package101. Moreover,FIG. 2is partially cutaway such that a portion of the package101is omitted to reveal the vicinity of the connection members110.

The package101is a case for protecting the first semiconductor chip102and the like. The inter-chip connection wires104aare conductive wires for connecting the connection pads108of the first semiconductor chip102to the respective connection members110. The inter-chip connection wires104bare conductive wires for connecting the connection pads109of the second semiconductor chip103to the respective connection members110. The external connection wires105are conductive wires for connecting the first semiconductor chip102or the second semiconductor chip103to the respective external leads106. The external leads106are leads for connecting the present semiconductor device to an external device. The connection members110are conductive portions obtained by plating protrusions which are formed on the die pad107, and realize connection between the first semiconductor chip102and the second semiconductor chip103.

Next, the internal connection between the first semiconductor chip102and the second semiconductor chip103in the semiconductor device having the above-described structure will be described.

The first semiconductor chip102is attached to a front face of the mount portion111of the die pad107so that its circuit face faces upwards inFIG. 1A,1B, or1C. The second semiconductor chip103is attached to a back face of the mount portion111of the die pad107so that its circuit face faces downwards inFIG. 1A,1B, or1C. In other words, the first semiconductor chip102and the second semiconductor chip103are attached to the die pad107“back-to-back”, i.e., so that their respective circuit faces face away from each other.

In order to internally connect the first semiconductor chip102and the second semiconductor chip103within the present semiconductor device, the connection pads108of the first semiconductor chip102and the respective connection members110are interconnected by the inter-chip connection wires104a. Preferably, each inter-chip connection wire104ais connected to a face of a corresponding connection member110that is oriented in the same direction as the circuit face of the first semiconductor chip102.

Furthermore, the connection members110and the respective connection pads109of the second semiconductor chip103are interconnected by the inter-chip connection wires104b. Preferably, each inter-chip connection wire104bis connected to a face of a corresponding connection member110that is oriented in the same direction as the circuit face of the second semiconductor chip103. Thus, the first semiconductor chip102and the second semiconductor chip103are internally connected via the connection members110.

Thus, in accordance with the semiconductor device of the present embodiment, the connection members110which realize internal connection between the first semiconductor chip102and the second semiconductor chip103are provided on the mount portion111of the die pad107. Therefore, it is unnecessary to employ any additional support member in order to introduce the connection members110. As a result, the number of component elements in the present semiconductor device can be reduced.

Furthermore, since the connection members110are provided on the mount portion111, the positioning between the connection members110and the connection pads108and109can be finalized at the time of producing the die pad107. This makes it unnecessary to pay further attention to such positioning during the assembly of the semiconductor device itself.

Moreover, the internal connection between the connection pads108on the first semiconductor chip102and the connection pads109on the second semiconductor chip103can be established without involving the external leads106. As a result, influences of surge are minimized.

Furthermore, in a preferred arrangement where each inter-chip connection wire104ais connected to a face of a corresponding connection member110that is oriented in the same direction as the circuit face of the first semiconductor chip102and each inter-chip connection wire104bis connected to a face of a corresponding connection member110that is oriented in the same direction as the circuit face of the second semiconductor chip103, the process of connecting the respective wires can be facilitated.

Although the connection members110of the semiconductor device according to the present embodiment are illustrated as protrusions, the shape of the connection members110is not limited thereto.

Although the present embodiment illustrates an example where the non-conductive piece to be interposed between the first semiconductor chip102and the second semiconductor chip103is a die pad107, the non-conductive piece is not limited to a die pad107. Specifically, as shown inFIG. 3B, the non-conductive piece may be a mere non-conductive piece which has connection members121(conductive portions) formed thereon and has substantially the same size as that of the first semiconductor chip102and the second semiconductor chip103. In this case, the first semiconductor chip102, the non-conductive piece120, and the second semiconductor chip103are stacked in this order, and the first semiconductor chip102and the second semiconductor chip103are interconnected with wires via the connection member121. In this manner, a semiconductor assembly is obtained which includes the first and second semiconductor chips102and103internally connected to one another. The semiconductor assembly thus obtained may be disposed on a die pad and connected to external leads, whereby a semiconductor device with a similar performance to that of the semiconductor device shown inFIG. 2can be obtained.

By employing a semiconductor assembly based on the non-conductive piece120as shown inFIGS. 3A to 3C, the first semiconductor chip102and the second semiconductor chip103are first attached to each other and then affixed to a die pad. This provides more liberty in the designing of a device which incorporates such a semiconductor assembly.

A semiconductor device according to a second embodiment of the present invention will be described with reference toFIGS. 4A,4B,4C, andFIG. 5.

FIGS. 4A,4B, and4C are perspective views showing the outer appearance of component elements used in the semiconductor device according to the second embodiment of the present invention.FIG. 4Ashows a first semiconductor chip202.FIG. 4Bshows a die pad207.FIG. 4Cshows a second semiconductor chip203, with a front face being shown in the left-hand view, and a back face shown in the right-hand view. The semiconductor device according to the present embodiment is constructed by attaching the first semiconductor chip202shown inFIG. 4A, the die pad207shown inFIG. 4B, and the second semiconductor chip203shown inFIG. 4Cto one another. Hereinafter, each component element will be described in detail.

The first semiconductor chip202and the second semiconductor chip203are identical to the first semiconductor chip102and the second semiconductor chip103according to the first embodiment, and the descriptions thereof are omitted. The die pad207serves as a non-conductive mount on which to place the first semiconductor chip202and the second semiconductor chip203. The die pad207includes a non-conductive mount portion212and a bridge210. The mount portion212is similar to the mount portion111according to the first embodiment, and the description thereof is omitted. The bridge210includes conductive connection members211formed thereon, which can be obtained by plating portions of the bridge210.

Now, the structure of the semiconductor device according to the present embodiment will be described.FIG. 5is a partially-cutaway perspective view showing the outer appearance of the semiconductor device according to the second embodiment of the present invention.

As shown inFIG. 5, the semiconductor device according to the present embodiment comprises a package201, the first semiconductor chip202, the second semiconductor chip203, inter-chip connection wires204aand204b, external connection wires205, external leads206, and the die pad207. InFIG. 5, the outer framework of the die pad207and a portion of the package201is omitted from illustration for the reasons described in the first embodiment.

The package201, the first semiconductor chip202, the second semiconductor chip203, the inter-chip connection wires204aand204b, the external connection wires205, the external leads206, the connection pads208, and the connection pads209are similar to those in the first embodiment, and the descriptions thereof are omitted.

The die pad207, which serves as a mount on which to place the semiconductor chips202and203(as does the die pad107according to the first embodiment), includes the bridge210. The bridge210is formed so as to interconnect the four legs which connect the mount portion212and the outer framework. The connection members211, which are conductive portions formed on the bridge210, realize internal connection between the first semiconductor chip202and the second semiconductor chip203.

Next, the internal connection between the first semiconductor chip202and the second semiconductor chip203in the semiconductor device having the above-described structure will be described.

The first semiconductor chip202is attached to a front face of the mount portion212of the die pad207so that its circuit face faces upwards inFIG. 4A,4B, or4C. The second semiconductor chip203is attached to a back face of the mount portion212of the die pad207so that its circuit face faces downwards inFIG. 4A,4B, or4C. In other words, the first semiconductor chip202and the second semiconductor chip203are attached to the die pad207“back-to-back”, i.e., so that their respective circuit faces face away from each other.

In order to internally connect the first semiconductor chip202and the second semiconductor chip203within the present semiconductor device, the connection pads208of the first semiconductor chip202and the respective connection members211are interconnected by the inter-chip connection wires204a. Preferably, each inter-chip connection wire204ais connected to a face of a corresponding connection member211that is oriented in the same direction as the circuit face of the first semiconductor chip202.

Furthermore, the connection members211and the respective connection pads209of the second semiconductor chip203are interconnected by the inter-chip connection wires204b. Preferably, each inter-chip connection wire204bis connected to a face of a corresponding connection member211that is oriented in the same direction as the circuit face of the second semiconductor chip203. Thus, the first semiconductor chip202and the second semiconductor chip203are internally connected via the connection members211.

Thus, in accordance with the semiconductor device of the present embodiment, the connection members211which realize internal connection between the first semiconductor chip202and the second semiconductor chip203are provided on the bridge210, which is a part of the die pad207. Therefore, it is unnecessary to employ any additional support member in order to introduce the connection members211. As a result, the number of component elements in the present semiconductor device can be reduced.

Furthermore, since the connection members211are provided on the bridge210, the positioning between the connection members211and the connection pads208and209can be finalized at the time of producing the die pad207. This makes it unnecessary to pay further attention to such positioning during the assembly of the semiconductor device itself, as in the case of the first embodiment.

Moreover, the internal connection between the first semiconductor chip202and the second semiconductor chip203can be established without involving the external leads206. As a result, influences of surge are minimized.

Furthermore, the process of connecting the respective wires can be facilitated in a preferred arrangement as described in the first embodiment.

Furthermore, in accordance with the semiconductor device of the present embodiment, the inter-chip connection based on the connection between the connection members211on the bridge210and the inter-chip connection wires204aand204ballows for a lot of liberty.

The semiconductor device according to the present embodiment may also be produced from a semiconductor assembly as described in the first embodiment.

A semiconductor device according to a third embodiment of the present invention will be described with reference toFIGS. 6A,6B,6C, andFIG. 7.

FIGS. 6A,6B, and6C are perspective views showing the outer appearance of component elements used in the semiconductor device according to the second embodiment of the present invention.FIG. 6Ashows a first semiconductor chip302.FIG. 6Bshows a die pad307.FIG. 6Cshows a second semiconductor chip303, with a front face being shown in the left-hand view, and a back face shown in the right-hand view. The semiconductor device according to the present embodiment is constructed by attaching the first semiconductor chip302shown inFIG. 6A, the die pad307shown inFIG. 6B, and the second semiconductor chip303shown inFIG. 6Cto one another. Hereinafter, each component element will be described in detail.

The first semiconductor chip302and the second semiconductor chip303are identical to the first semiconductor chip102and the second semiconductor chip103according to the first embodiment, and the descriptions thereof are omitted.

The die pad307serves as a non-conductive mount on which to place the first semiconductor chip302and the second semiconductor chip303. As shown inFIG. 6B, the die pad307includes a mount portion311on which to place the first semiconductor chip302and the second semiconductor chip303, the mount portion311being larger than the mount portions according to the first and second embodiments. Connection members310are provided near edges of the mount portion311. Specifically, the connection members310are formed by making holes near edges of the mount portion311, and placing metal pieces in the holes.

Now, the structure of the semiconductor device according to the present embodiment will be described.FIG. 7is a partially-cutaway perspective view showing the outer appearance of the semiconductor device according to the second embodiment of the present invention.

As shown inFIG. 7, the semiconductor device according to the present embodiment comprises a package301, the first semiconductor chip302, the second semiconductor chip303, inter-chip connection wires304aand304b, external connection wires305, external leads306, and the die pad307. InFIG. 7, the outer framework of the die pad307and a portion of the package301is omitted from illustration for the reasons described in the first embodiment.

The package301, the first semiconductor chip302, the second semiconductor chip303, the inter-chip connection wires304aand304b, the external connection wires305, the external leads306, the connection pads308, and the connection pads309are similar to those in the first embodiment, and the descriptions thereof are omitted.

The die pad307, which serves as a mount on which to place the semiconductor chips302and303(as does the die pad107according to the first embodiment), includes the connection members310. The first semiconductor chip302and the second semiconductor chip303are attached to the die pad307in such a manner that the connection members310lie outside of the first semiconductor chip302and the second semiconductor chip303. The connection members310realize internal connection between the first semiconductor chip302and the second semiconductor chip303as in the first embodiment.

Next, the internal connection between the first semiconductor chip302and the second semiconductor chip303in the semiconductor device having the above-described structure will be described.

The first semiconductor chip302is attached to a front face of the mount portion311of the die pad307so that its circuit face faces upwards inFIG. 6A,6B, or6C. The second semiconductor chip303is attached to a back face of the mount portion311of the die pad307so that its circuit face faces downwards inFIG. 6A,6B, or6C. In other words, the first semiconductor chip302and the second semiconductor chip303are attached to the die pad307“back-to-back”, i.e., so that their respective circuit faces face away from each other.

In order to internally connect the first semiconductor chip302and the second semiconductor chip303within the present semiconductor device, the connection pads308of the first semiconductor chip302and the respective connection members310are interconnected by the inter-chip connection wires304a. Preferably, each inter-chip connection wire304ais connected to a face of a corresponding connection member310that is oriented in the same direction as the circuit face of the first semiconductor chip302.

Furthermore, the connection members310and the respective connection pads309of the second semiconductor chip303are interconnected by the inter-chip connection wires304b. Preferably, each inter-chip connection wire304bis connected to a face of a corresponding connection member310that is oriented in the same direction as the circuit face of the second semiconductor chip303. Thus, the first semiconductor chip302and the second semiconductor chip303are internally connected via the connection members310.

Thus, in accordance with the semiconductor device of the present embodiment, the connection members310which realize internal connection between the first semiconductor chip302and the second semiconductor chip303are provided on the die pad307. Therefore, it is unnecessary to employ any additional support member in order to introduce the connection members310. As a result, the number of component elements in the present semiconductor device can be reduced.

Furthermore, since the connection members310are provided on the die pad307, the positioning between the connection members310and the connection pads308and309can be finalized at the time of producing the die pad307. This makes it unnecessary to pay further attention to such positioning during the assembly of the semiconductor device itself, as in the case of the first embodiment.

Moreover, the internal connection between the first semiconductor chip302and the second semiconductor chip303can be established without involving the external leads306. As a result, influences of surge are minimized.

Furthermore, the process of connecting the respective wires can be facilitated in a preferred arrangement as described in the first embodiment.

As described above, the connection members310according to the present embodiment are composed of metal pieces placed in holes formed in the die pad307. As such, the connection members310are free from fluctuations which would result from a plating process, thereby providing for a better connectability with the wires.

The semiconductor device according to the present embodiment may also be produced from a semiconductor assembly as described in the first embodiment.

Although the first to third embodiments above each illustrate an example where connection members for realizing internal connection between the first semiconductor chip and the second semiconductor chip are provided on a die pad, such connection members may be provided on any element other than the die pad. As a fourth embodiment, an example of such a semiconductor device will be described below.

A semiconductor device according to a fourth embodiment of the present invention will be described with reference toFIG. 8.

FIG. 8is a partially-cutaway perspective view showing the outer appearance of a semiconductor device according to the present embodiment of the present invention. The semiconductor device according to the present embodiment comprises a package401, a first semiconductor chip402, a second semiconductor chip403, inter-chip connection wires404aand404b, external connection wires405, external leads406, and a die pad407.

The package401, the inter-chip connection wires404aand404b, and the external connection wires405are identical to those in the first embodiment, and the descriptions thereof are omitted. As is the case with the first semiconductor chip102according to the first embodiment, the first semiconductor chip402includes circuitry formed on one face, and includes connection pads408formed on this circuit face. Similarly, as is the case with the second semiconductor chip103according to the first embodiment, the second semiconductor chip403includes circuitry formed on one face, and includes connection pads409formed on this circuit face.

The external leads406according to the present embodiment will be described. Each external lead406according to the present embodiment is composed of a non-conductive piece having a similar shape to that of the external leads106according to the first embodiment. A portion of the external lead406lying closer to the semiconductor device is plated to become a connection member410for realizing internal connection between the first semiconductor chip402and the second semiconductor chip403. Another portion of the external lead406is also plated to become an external connection member411for connecting the present semiconductor device to an external device. As shown inFIG. 8, the connection member410of each external lead406is insulated from the external connection member411by a non-conductive portion.

Next, the internal connection between the first semiconductor chip402and the second semiconductor chip403in the semiconductor device having the above-described structure will be described.

The first semiconductor chip402is attached to a front face of a mount portion of the die pad407so that its circuit face faces upwards inFIG. 8. The second semiconductor chip403is attached to a back face of the mount portion of the die pad407so that its circuit face faces downwards inFIG. 8. In other words, the first semiconductor chip402and the second semiconductor chip403are attached to the die pad407“back-to-back”, i.e., so that their respective circuit faces face away from each other.

In order to internally connect the first semiconductor chip402and the second semiconductor chip403within the present semiconductor device, the connection pads408of the first semiconductor chip402and the respective connection members410are interconnected by the inter-chip connection wires404a. Preferably, each inter-chip connection wire404ais connected to a face of a corresponding connection member410that is oriented in the same direction as the circuit face of the first semiconductor chip402.

Furthermore, the connection members410and the respective connection pads409of the second semiconductor chip403are interconnected by the inter-chip connection wires404b. Preferably, each inter-chip connection wire404bis connected to a face of a corresponding connection member410that is oriented in the same direction as the circuit face of the second semiconductor chip403. Thus, the first semiconductor chip402and the second semiconductor chip403are internally connected via the connection members410.

In accordance with the semiconductor device of the present embodiment, the connection members410and the external connection members411are formed by plating portions of the external leads406, which themselves are composed of non-conductive pieces. In other words, the connection members410are integral parts of the external leads406. Therefore, it is unnecessary to employ any additional support member in order to introduce the connection members410. As a result, the number of component elements in the present semiconductor device can be reduced, as in the first embodiment.

In accordance with the semiconductor device of the present embodiment, positioning of the connection members410can be finalized during the positioning of the external leads406. This makes it unnecessary to pay further attention to the positioning of the connection members410during the assembly of the semiconductor device itself.

Moreover, the internal connection between the first semiconductor chip402and the second semiconductor chip403can be established without involving the external leads206. As a result, influences of surge are minimized.

Furthermore, the process of connecting the respective wires can be facilitated in a preferred arrangement as described in the first embodiment.

According to the present embodiment, there is no need to design a special shape for the lead frame itself.

According to the first to fourth embodiments, the first semiconductor chip and the second semiconductor chip are internally connected via connection members, so that the connection pads of the first semiconductor chip and the connection pads of the second semiconductor device need to be placed in the neighborhood of the connection members. Therefore, in the case where the connection pads of the first semiconductor chip are distant from the connection pads of the second semiconductor chip, it might be difficult to connect them according to the first to fourth embodiments.

As a fifth embodiment, a semiconductor device which allows the connection pads of the first semiconductor chip to be connected to the connection pads of the second semiconductor chip even in the case where the connection pads of the first semiconductor chip and the second semiconductor chip are in distant positions will be described below.

A semiconductor device according to a fifth embodiment of the present invention will be described with reference toFIGS. 9A,9B,9C, andFIG. 10.

FIGS. 9A,9B, and9C are perspective views showing the outer appearance of component elements used in the semiconductor device according to the fifth embodiment of the present invention.FIG. 9Ashows a first semiconductor chip502.FIG. 9Bshows a die pad507.FIG. 9Cshows a second semiconductor chip503, with a front face being shown in the left-hand view, and a back face shown in the right-hand view. The semiconductor device according to the present embodiment is constructed by attaching the first semiconductor chip502shown inFIG. 9A, the die pad507shown inFIG. 9B, and the second semiconductor chip503shown inFIG. 9Cto one another. Hereinafter, each component element will be described in detail.

The first semiconductor chip502is identical to the first semiconductor chip102in the first embodiment, and the description thereof is omitted.

As shown inFIG. 9C, the second semiconductor chip503includes connection pads509aand509b. The second semiconductor chip503of the present embodiment is different from the second semiconductor chip103of the first embodiment in that the connection pads509aand509bdo not come in the neighborhoods of the connection pads508aand508bof the first semiconductor chip502when the first and second semiconductor chips502and503are stacked together.

The die pad507serves as a non-conductive mount on which to place the first semiconductor chip502and the second semiconductor chip503, and includes a mount portion512, connection members510a,510b,510c, and510d, and metal strips511aand511b. The connection members510ato510dand the metal strips511aand511bare formed on the mount portion512, on which the first semiconductor chip502and the second semiconductor chip503are to be placed. The connection members510ato510dare obtained by plating protrusions which are formed on a non-conductive piece composing the mount portion512. The connection member510ais to be connected to the connection pad508aof the first semiconductor chip502. The connection member510bis to be connected to the connection pad508bof the first semiconductor chip502. The connection member510cis to be connected to the connection pad509aof the second semiconductor chip503. The connection member510dis to be connected to the connection pad509bof the second semiconductor chip503.

The metal strip511a, which is a strip for interconnecting the connection member510aand the connection member510c, may be obtained through plating. The metal strip511b, which is a strip for interconnecting the connection member510band the connection member510d, may be obtained through plating.

Now, the structure of the semiconductor device according to the present embodiment will be described.FIG. 10is a perspective view showing the outer appearance of the semiconductor device according to the second embodiment of the present invention.

The semiconductor device according to the present embodiment comprises the first semiconductor chip502, the second semiconductor chip503, inter-chip connection wires504a,504b,504c(not shown inFIG. 10), and504d, external connection wires505, external leads506, and the die pad507. InFIG. 10, a portion of the die pad507and a package are omitted from illustration.

The external connection wire505and the external leads506are similar to those in the first embodiment, and the descriptions thereof are omitted.

According to the present embodiment, the inter-chip connection wire504aconnects the connection pad508ato the connection member510a. The inter-chip connection wire504bconnects the connection pad508bto the connection member510b. The inter-chip connection wire504c(not shown inFIG. 10) connects the connection pad509ato the connection member510c. The inter-chip connection wire504dconnects the connection pad509bto the connection member510d.

Next, the internal connection between the first semiconductor chip502and the second semiconductor chip503in the semiconductor device having the above-described structure will be described.

The first semiconductor chip502is attached to a front face of the mount portion512of the die pad507so that its circuit face faces upwards inFIG. 9A,9B, or9C. When the first semiconductor chip502and the die pad507are attached together, a non-conductive adhesive is used in order to prevent short-circuiting between the metal strips511aand511band the first semiconductor chip502.

The second semiconductor chip503is attached to a back face of the mount portion512of the die pad507so that its circuit face faces downwards inFIG. 9A,9B, or9C. In other words, the first semiconductor chip502and the second semiconductor chip503are attached to the die pad507“back-to-back”, i.e., so that their respective circuit faces face away from each other.

In order to internally connect the first semiconductor chip502and the second semiconductor chip503within the present semiconductor device, the connection pad508aof the first semiconductor chip502and the connection member510aare interconnected by the inter-chip connection wire504a. Furthermore, the connection member510cand the connection pad509aof the second semiconductor chip503are interconnected by the inter-chip connection wire504c(not shown inFIG. 10). As a result, the connection pad508aof the first semiconductor chip502is electrically connected to the connection pad509aof the second semiconductor chip503via the connection member510a, the metal strip511a, and the connection pad510c. Preferably, the inter-chip connection wire504ais connected to a face of the connection member510athat is oriented in the same direction as the circuit face of the first semiconductor chip502. Preferably, the inter-chip connection wire504c(not shown inFIG. 10) is connected to a face of the connection member510cthat is oriented in the same direction as the circuit face of the second semiconductor chip503.

In order to internally connect the first semiconductor chip502and the second semiconductor chip503within the present semiconductor device, the connection pad508bof the first semiconductor chip502and the connection member510bare interconnected by the inter-chip connection wire504b. Furthermore, the connection member510dand the connection pad509bof the second semiconductor chip503are interconnected by the inter-chip connection wire504d. As a result, the connection pad508bof the first semiconductor chip502is electrically connected to the connection pad509bof the second semiconductor chip503, via the connection member510b, the metal strip511b, and the connection pad510d. Preferably, the inter-chip connection wire504bis connected to a face of the connection member510bthat is oriented in the same direction as the circuit face of the first semiconductor chip502. Preferably, the inter-chip connection wire504dis connected to a face of the connection member510dthat is oriented in the same direction as the circuit face of the second semiconductor chip503.

Thus, the present embodiment not only provides the effects attained by the first embodiment but also provides an advantage in that the metal strips formed on the die pad507allow the connection pads of the first semiconductor chip502to be connected to the connection pads of the second semiconductor chip503even in the case where the connection pads of the first semiconductor chip and the second semiconductor chip are in distant positions.

Although the present embodiment illustrates an example where the first semiconductor chip502and the die pad507are attached together by using a non-conductive adhesive in order to prevent short-circuiting between the metal strips511aand511band the first semiconductor chip502, any other means for ensuring isolation between the metal strips511aand511bon the die pad507and the first semiconductor chip502may be used. For example, a non-conductive film may be attached to a principle face of the mount portion512having the metal strips511aand511bformed thereon, and thereafter the first semiconductor chip502may be attached onto the non-conductive film. Instead of a non-conductive film, a plate composed of the same non-conductive material as that composing the die pad507may be attached to the mount portion512having the metal strips511aand511bformed thereon.

Although the present embodiment illustrates an example where metal strips are provided on only one face of the die pad507, such metal strips may be formed on both faces of the die pad507, as shown inFIGS. 11A,11B, and11C.FIGS. 11A,11B, and11C are perspective views showing the outer appearance of component elements used in a variant of the semiconductor device according to the fifth embodiment of the present invention, where metal strips551aand551bare provided on the respective faces of the die pad507. As shown inFIG. 11B, the metal strip551ainterconnects the connection members510band510con one face of the die pad507, whereas the metal strip551binterconnects the connection members510aand510don the opposite face of the die pad507.

By thus providing metal strips on both faces of the die pad507, it may become possible to realize a straightforward arrangement for metal strips which would inevitably intersect one another if provided on only one face. This provides more liberty in the designing of the semiconductor device.

Although the present embodiment illustrates an example where metal strips are provided on the die pad of the semiconductor device according to the first embodiment, the concept of metal strips provided on a die pad can also be extended to the second or third embodiment, for example, without limitation. Furthermore, the same concept is also applicable to the semiconductor assembly described in the first to third embodiments.

In the first to fifth embodiments above, the connection between the connection pads of the first semiconductor chip connection members and the connection between the connection pads of the second semiconductor chip and the connection members are realized by means of wires.

However, these connections can be realized by other means besides wires. As a sixth embodiment, a semiconductor device in which semiconductor chips are interconnected without employing wires will be described below.

A semiconductor device according to a sixth embodiment of the present invention will be described with reference toFIGS. 12A,12B,12C, andFIG. 13.

FIGS. 12A,12B, and12C are perspective views showing the outer appearance of component elements used in the semiconductor device according to the sixth embodiment of the present invention.FIG. 12Ashows a first semiconductor chip601.FIG. 12Bshows a die pad602, with a front face being shown in the left-hand view, and a back face shown in the right-hand view. Note thatFIG. 12Bonly shows a mount portion of the die pad on which semiconductor chips are to be placed; other portions of the die pad are omitted from illustration.FIG. 12Cshows a second semiconductor chip603.FIG. 13is a perspective view showing the outer appearance of the semiconductor device, as constructed by assembling the first semiconductor chip601, the die pad602, and the second semiconductor chip603. InFIG. 13, external leads and a package are omitted from illustration.

The first semiconductor chip601includes circuitry formed on a face shown upwards inFIG. 12A. Furthermore, apertures are formed through the first semiconductor chip601, with metal pieces605a,605b, and605cembedded in the apertures.

Apertures are formed through the die pad602in portions which come into contact with the metal pieces605ato605cwhen the first semiconductor chip601is stacked onto the die pad602. Metal pieces606a,606b, and606care embedded in these apertures in the die pad602. On the back face of the die pad602, metal strip607a,607b, and607c, which are electrically connected to the metal pieces606a,606b, and606c, respectively, are formed by plating.

The second semiconductor chip603includes circuitry formed on a face shown downwards inFIG. 12C. Furthermore, apertures are formed through the second semiconductor chip603in portions which come into contact with the metal strips607ato607cwhen the die pad602is stacked onto the second semiconductor chip603. Metal pieces608a,608b, and608care embedded in these apertures in the second semiconductor chip603.

The semiconductor device comprising the first semiconductor chip601, the die pad602, and the second semiconductor chip603will be described with reference toFIG. 13.

The first semiconductor chip601is attached to a front face of the mount portion of the die pad602so that its circuit face faces upwards inFIG. 12A,12B, or12C. The second semiconductor chip603is attached to a back face of the mount portion of the die pad602so that its circuit face faces downwards inFIG. 12A,12B, or12C. In other words, the first semiconductor chip601and the second semiconductor chip603are attached to the die pad602“back-to-back”, i.e., so that their respective circuit faces face away from each other. The second semiconductor chip603and the die pad602are attached together by using a non-conductive adhesive in order to prevent short-circuiting between the metal strips607ato607cand the second semiconductor chip603.

As described above, the metal pieces605ato605cin the first semiconductor chip601are disposed so as to come in contact with the metal pieces606ato606c, respectively, in the die pad602. The metal strip607ato607con the die pad602are disposed so as to come in contact with the pieces608ato608c, respectively, in the second semiconductor chip603. Thus, when the semiconductor device as shown inFIG. 13is assembled, the first semiconductor chip601and the second semiconductor chip603are electrically interconnected within the semiconductor device.

Thus, the semiconductor device of the present embodiment not only provides the effects attained by the semiconductor device according to the first embodiment, but also has an advantage in that, since the first and second semiconductor chips601and603are interconnected by means of metal pieces and metal strips as described above, there are no wires projecting outside the semiconductor device. As a result, the present semiconductor device can be kept compact.

Although the first to sixth embodiments above illustrate examples where the first semiconductor chip and the second semiconductor chip are attached to each other “back-to-back”,i.e., so that their respective circuit faces face away from each other, the manner of attaching the first semiconductor chip and the second semiconductor chip together is not limited thereto.

As a seventh embodiment, a semiconductor device in which two semiconductor chips are attached together in a different manner from those described in the first to sixth embodiments will be described below.

A semiconductor device according to a seventh embodiment of the present invention will be described with reference toFIG. 14.FIG. 14is a cross-sectional view showing a semiconductor device according to the present embodiment of the present invention.

The semiconductor device according to the present embodiment comprises a package701, a first semiconductor chip702, a second semiconductor chip703, inter-chip connection wires704aand704b, external leads706, a die pad707, and a spacer715.

The package701, the inter-chip connection wires704aand704b, and the external leads706are similar to those according to the first embodiment, and the descriptions thereof are omitted.

The first semiconductor chip702includes circuitry formed on an upper principal face as shown inFIG. 14, and includes connection pads708formed on this circuit face. The second semiconductor chip703includes circuitry formed on an upper principal face as shown inFIG. 14, and includes connection pads709formed on this circuit face.

The die pad707serves as a non-conductive mount on which to place the first semiconductor chip702and the second semiconductor chip703, and includes connection members710formed on portions thereof. The die pad707has a larger outer contour than that of the first semiconductor chip702and the second semiconductor chip703.

The connection members710, which are formed by plating portions of the die pad707, realize connection between the first semiconductor chip702and the second semiconductor chip703. The spacer715serves to provide a space between the first semiconductor chip702and the second semiconductor chip703so as to allow inter-chip connection wires704bto be connected to the connection pads708of the second semiconductor chip703. The spacer715is composed of a non-conductive piece which is smaller than the first semiconductor chip702and the second semiconductor chip703.

Next, the internal connection between the first semiconductor chip702and the second semiconductor chip703in the semiconductor device having the above-described structure will be described.

The second semiconductor chip703is attached to the die pad707so that its circuit face faces upwards as shown inFIG. 14. Furthermore, the spacer715is placed on the second semiconductor chip703so as to leave the connection pads709exposed. The first semiconductor chip702is attached to the spacer715so that its circuit face faces upwards as shown inFIG. 14. Thus, the first semiconductor chip702and the second semiconductor chip703are stacked together.

Then, the connection pads708of the first semiconductor chip702are connected to the respective connection members710of the die pad707by inter-chip connection wires704a. Furthermore, the connection pads709of the second semiconductor chip703are connected to the respective connection members710of the die pad707by inter-chip connection wires704b. Thus, the first semiconductor chip702and the second semiconductor chip703are electrically interconnected via the connection members710.

Thus, the semiconductor device of the present embodiment not only provides the effects attained by the semiconductor device according to the first embodiment, but also has an advantage in that the first semiconductor chip702and the second semiconductor chip703can be easily interconnected even in the case where their circuit faces are oriented in the same direction, since the die pad707is placed underneath the first semiconductor chip702and the second semiconductor chip703, such that the first semiconductor chip702and the second semiconductor chip703are interconnected via the connection members710on the die pad707.

Although the present embodiment illustrates an example where the connection members710are provided on the die pad707, the connection members may be provided on any element other than the die pad707.

As an eighth embodiment, a variation of the seventh embodiment in which the connection members are provided on elements other than the die pad707will be described.

A semiconductor device according to an eighth embodiment of the present invention will be described with reference toFIG. 15.FIG. 15is a cross-sectional view showing a semiconductor device according to the present embodiment of the present invention.

The semiconductor device according to the present embodiment comprises a package801, a first semiconductor chip802, a second semiconductor chip803, inter-chip connection wires804aand804b, external leads806, a die pad807, and a spacer815.

The package801and the inter-chip connection wires804aand804bare similar to those according to the first embodiment, and the descriptions thereof are omitted.

The first semiconductor chip802, the second semiconductor chip803, connection pads808and809formed respectively on the upper faces of the first and second semiconductor chips802and803, and the spacer815are similar to those according to the seventh embodiment, and the descriptions thereof are omitted.

The die pad807serves as a non-conductive mount on which to place the first semiconductor chip802and the second semiconductor chip803.

Now, the external leads806according to the present embodiment will be described. The external leads806according to the present embodiment have a similar structure to that of the external leads406according to the fourth embodiment. Specifically, each external lead806is composed of a non-conductive piece having a similar shape to that of the external leads106according to the first embodiment. A portion of the external lead806lying closer to the semiconductor device is plated to become a connection member810for realizing internal connection between the first semiconductor chip802and the second semiconductor chip803. Another portion of the external lead806is also plated to become an external connection member811for connecting the present semiconductor device to an external device. As in the fourth embodiment, the connection member810of each external lead806is insulated from the external connection member811by a non-conductive portion.

Next, the internal connection between the first semiconductor chip802and the second semiconductor chip803in the semiconductor device having the above-described structure will be described.

The second semiconductor chip803is attached to the die pad807so that its circuit face faces upwards as shown inFIG. 15. Furthermore, the spacer815is placed on the second semiconductor chip803so as to leave the connection pads809exposed. The first semiconductor chip802is attached to the spacer815so that its circuit face faces upwards as shown inFIG. 15. Thus, the first semiconductor chip802and the second semiconductor chip803are stacked together.

Then, the connection pads808of the first semiconductor chip802are connected to the connection members810of the respective external leads806by inter-chip connection wires804a. Furthermore, the connection pads809of the second semiconductor chip803are connected to the connection members810of the respective external leads806by inter-chip connection wires804b. Thus, the first semiconductor chip802and the second semiconductor chip803are electrically interconnected via the connection members810.

Thus, the semiconductor device of the present embodiment not only provides the effects attained by the semiconductor device according to the first embodiment, but also has an advantage in that the first semiconductor chip802and the second semiconductor chip803can be easily interconnected even in the case where their circuit faces are oriented in the same direction, as in the seventh embodiment.

According to the present embodiment, there is no need to design a special shape for the lead frame itself, as in the fourth embodiment.

The seventh and eighth embodiments illustrate examples where two semiconductor chips are stacked so that their circuit faces are oriented in the same direction, with a die pad being placed underneath the second semiconductor chip.

However, the die pad may be positioned in any place other than underneath the second semiconductor chip in the case where, as in the seventh and eighth embodiments, two semiconductor chips are stacked so that their circuit faces are oriented in the same direction.

As a ninth embodiment, a variation of the seventh embodiment in which a die pad is positioned in a place other than underneath the second semiconductor chip will be described.

A semiconductor device according to a ninth embodiment of the present invention will be described with reference toFIGS. 16A,16B, and16C.

FIGS. 16A,16B, and16C are perspective views showing the outer appearance of component elements used in the semiconductor device according to the ninth embodiment of the present invention.FIG. 16Ashows a first semiconductor chip902.FIG. 16Bshows a die pad907.FIG. 16Cshows a second semiconductor chip903. The semiconductor device according to the present embodiment is constructed by attaching the first semiconductor chip902shown inFIG. 16A, the die pad907shown inFIG. 16B, and the second semiconductor chip903shown inFIG. 16Cto one another. Hereinafter, each component element will be described in detail.

The first semiconductor chip902includes circuitry formed on a face shown upwards inFIG. 16A, and includes connection pads908aand908bformed on this circuit face. The connection pads908aand908bare used for external connection or for connection with the second semiconductor chip903. The die pad907serves as a non-conductive mount on which to place the first semiconductor chip902and the second semiconductor chip903. The die pad907includes a non-conductive mount portion and an outer framework as in the first embodiment (only the mount portion is shown inFIG. 16B). The mount portion has an outer contour which is larger than that of the first semiconductor chip902and the second semiconductor chip903. The first semiconductor chip902is to be attached to the face of the mount portion shown upwards inFIG. 16B, and the second semiconductor chip903is to be attached to the opposite face of the mount portion. Near the edges of the mount portion, first connection members910aand910bare formed by plating. Also on the mount portion, metal strips912aand912bare formed by plating, so as to be electrically connected to the first connection members910aand910b, respectively. An aperture is formed through an end of each of the metal strips912aand912b, and metal pieces embedded in these apertures compose second connection members911aand911b, respectively. The second semiconductor chip903has substantially the same size as that of the first semiconductor chip902. The second semiconductor chip903includes circuitry formed on a face shown upwards inFIG. 16C, and includes, on this circuit face, bumps905aand905bto be electrically connected to the second connection members911aand911b, respectively. The bumps905aand905bare formed in portions of the second semiconductor chip903that come respectively in contact with the second connection members911aand911bof the die pad907when the second semiconductor chip903is stacked on the die pad907.

Now, the structure of the semiconductor device according to the present embodiment will be described.FIG. 17is a cross-sectional view showing the semiconductor device according to the present embodiment.

The semiconductor device according to the present embodiment comprises a package901, the first semiconductor chip902, the second semiconductor chip903, inter-chip connection wires904aand904b, the bumps905aand905b, external leads906, and the die pad907.

The package901, the first semiconductor chip902, the inter-chip connection wires904aand904b, and the external leads906are similar to those according to the first embodiment, and the descriptions thereof are omitted.

The first connection members910aand910b, the metal strips912aand912b, and the second connection members911aand911brealize connection between the first semiconductor chip902and the second semiconductor chip903.

Next, the internal connection between the first semiconductor chip902and the second semiconductor chip903in the semiconductor device having the above-described structure will be described.

The first semiconductor chip902is attached to a front face of the mount portion of the die pad907so that its circuit face faces upwards inFIG. 17. The first semiconductor chip902and the die pad907are attached together by using a non-conductive adhesive in order to prevent short-circuiting between the metal strips912aand912band the first semiconductor chip902.

In order to internally connect the first semiconductor chip902and the second semiconductor chip903within the present semiconductor device, the connection pad908aof the first semiconductor chip902and the first connection member910aare interconnected by the inter-chip connection wire904a. The connection pad908bof the first semiconductor chip902and the first connection member910bare interconnected by the inter-chip connection wire904b.

Next, the second semiconductor chip903is attached to a back face of the mount portion of the die pad907so that its circuit face faces upwards inFIG. 17, with the bumps905aand905binterposed between the second semiconductor chip903and the die pad907. Note that the second semiconductor chip903is attached to the die pad907so that the bumps905aand905bcoincide with the second connection members911aand911b, respectively. Thus, the first semiconductor chip902and the second semiconductor chip903are electrically interconnected via the first connection members910aand910b, the metal strips912aand912b, and the second connection members911aand911b.

Thus, the semiconductor device of the present embodiment not only provides the effects attained by the semiconductor device according to the first embodiment, but also has an advantage in that the first semiconductor chip902and the second semiconductor chip903can be interconnected even in the case where their circuit faces are oriented in the same direction with die pad907interposed therebetween, since the die pad907and the second semiconductor chip903are electrically interconnected by the bumps905aand905b.

The semiconductor device according to the present embodiment may also be produced from a semiconductor assembly as described in the first embodiment.

Although the present embodiment illustrates an example where the first semiconductor chip902and the die pad907are attached together by using a non-conductive adhesive in order to prevent short-circuiting between the metal strips912aand912band the first semiconductor chip902, any other means for ensuring isolation between the metal strips912aand912bon the die pad907and the first semiconductor chip902may be used. For example, a non-conductive film may be attached to a principle face of the mount portion having the metal strips912aand912bformed thereon, and thereafter the first semiconductor chip902may be attached onto the non-conductive film. Instead of a non-conductive film, a plate composed of the same non-conductive material as that composing the die pad907may be attached to the die pad907having the metal strips912aand912bformed thereon.

The present embodiment illustrates an example where the circuit face of the first semiconductor chip903and the circuit face of the second semiconductor chip903are oriented in the same direction. Alternatively, the two circuit faces may oppose each other, with the die pad907interposed therebetween. In this case, the first semiconductor chip902and the die pad907are to be interconnected via the bumps.

In the first to ninth embodiments above, the package may be a ceramic package formed so as to be hollow between leads, or a ceramic package formed so as not to be hollow between leads.

In the first to ninth embodiments, the first semiconductor chip and the second semiconductor chip are illustrated as being of substantially the same size. As used herein, the two semiconductor chips being “of substantially the same size” means that, when the first semiconductor chip and the second semiconductor chip are layered in place, the portion of the larger one of the semiconductor chips that lies outside of the smaller semiconductor chip is not large enough for accommodating any connection pads.

Although each of the first to ninth embodiments illustrates an example where two semiconductor chips are stacked, three or more semiconductor chips may be stacked to compose the semiconductor device, as realized by combining the layering methods according to the first to ninth embodiments.

Plating or embedded metal pieces described in any of the first to ninth embodiments above are mere examples of conductive elements. It will be appreciated that such elements may be replaced by, for example, pieces of resin which has been imparted with electrical conductivity.