Semiconductor device

A semiconductor device comprises a first memory cell comprising more than seven transistors and storing data in a latch circuit; and a second memory cell storing data in a capacitor; a sense amplifier having about the same circuit configuration of the first memory cell and detecting data stored in the second memory cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device including both a static random access memory (SRAM) and a dynamic random access memory (DRAM).

2. Description of Related Art

A semiconductor device comprising a semiconductor substrate both a SRAM and a DRAM are formed on is well known (for example, see Japanese Unexamined Patent Publication No. 10-041409). High-speed memory access can be obtained with the SRAM and large capacity with small area can be provided with the DRAM.FIG. 8shows a general circuit configuration of a SRAM cell, which is formed to like this semiconductor device.

As shown inFIG. 8, the SRAM cell generally consists of six transistors. This SRAM cell has a latch circuit89. The latch circuit89includes NMOS transistors81,82and PMOS transistors83,84. Further, the SRAM cell includes transfer transistors85,86. The transfer transistors85,86transfer data stored in the latch circuit89to bit lines BL and /BL.

In the SRAM cell formed as described above, threshold variation of transistors81-86becomes a great factor of malfunction according to progress in manufacturing miniaturization. Furthermore, because of lower control voltage for electric power saving, stability of operation gets worse. As a result, there is a problem that yield of manufacturing process becomes lower when the SRAM cell is formed to the semiconductor device. To improve the yield of manufacturing process, new approaches has been researched and developed. For one of the new approaches, a new configuration is applied to the SRAM cell as to obtain high stability even in low-voltage condition (for example, that is shown in “Approaches to control a SRAM variation for LSI are proposed in a stream”, Nikkei electronics, 2006.7, Vol. 17, p. 55-62).

On the other hand, semiconductor device, which the DRAM is formed on, has a sense amplifier. As shown inFIG. 9, the sense amplifier of the DRAM comprises NMOS transistors91,92, PMOS transistors93,94, and transfer transistors95,96. A bit line BL and a complemental bit line /BL of the DRAM cell are connected to nodes n7, n8inFIG. 9. A potential difference between the bit lines BL, /BL is amplified by the NMOS transistors91,92and the PMOS transistors93,94. The NMOS transistors91,92and the PMOS transistors93,94are electrically connected each other like as the latch circuit89. Data based on the amplified potential difference is transferred to a data bus Bus and /Bus by the transfer transistors95,96.

ComparingFIG. 8withFIG. 9, it can be seen that the NMOS transistors91,92of the sense amplifier correspond to the transistors81,82of the SRAM cell. The PMOS transistors93,94of the sense amplifier correspond to the transistors83,84of the SRAM cell. The transfer transistors95,96of the sense amplifier correspond to the transistors85,86of the SRAM. A circuit99(hereinafter, it is called as a latch circuit99) amplifying the potential difference between a pair of bit lines BL and /BL corresponds to the latch circuit89of the SRAM. This is, the sense amplifier of the DRAM has about the same configuration of the SRAM cell.

As described above, when a circuit configuration of the SRAM cell is changed as to save electric power and rein in the negative effect of manufacturing variation, for the semiconductor device including both the SRAM and the DRAM, a configuration of the SRAM cell does not correspond to the sense amplifier of the DRAM. Hence, a tuning window of the SRAM cell does not correspond to the sense amplifier of the DRAM. The tuning window means manufacturing condition in which minimum manufacturing variation can be obtained. When the semiconductor device is manufactured with the tuning window of the SRAM cell, the sense amplifier of the DRAM tends to have a defect. As described above, for the semiconductor device including both the DRAM and the SRAM, when electric power saving is aimed, mass productivity cannot be obtained.

SUMMARY

According to an aspect of the present invention, there is provided a semiconductor device that includes a semiconductor device comprising; a first memory cell comprising more than seven transistors and storing data in a latch circuit; and a second memory cell storing data in a capacitor; a sense amplifier having about the same circuit configuration of the first memory cell and detecting data stored in the second memory cell.

According to another aspect of the present invention, there is provided a semiconductor device comprising; a first memory cell comprising more than seven transistors and storing data in a latch circuit; and a second memory cell storing data in a capacitor; a sense amplifier having about the same circuit configuration of the first memory cell and detecting data stored in the second memory cell, wherein the first memory cell comprising a plurality of a first and a second conductivity type transistors, and wherein the sense amplifier comprising same number of the first and the second conductivity type transistors as the first memory cell.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to attached figures, preferable embodiments of this invention are described hereinafter.

First Embodiment

FIG. 1shows a block diagram of a whole configuration of a semiconductor device according to a first embodiment. This semiconductor device10includes a SRAM block and a DRAM block. The SRAM block includes a plurality of SRAM cells CELL1. The SRAM cell CELL1includes a latch circuit (not shown) storing data. The DRAM block includes a plurality of DRAM cells CELL2and a plurality of sense amplifiers SA. The DRAM cell CELL2has capacitors storing data and transistors (not shown). Data stored in the DRAM cell is read out and output by the sense amplifier SA.

FIG. 2shows a circuit configuration of the SRAM cell CELL1. This SRAM cell includes NMOS transistors21,22, PMOS transistors23,24, transfer transistors25,26, and read transistors27,28.

In the NMOS transistor21, a source is connected to a ground voltage supply GND, a drain is connected to a node n1, and a gate is connected to a node2. In the NMOS transistor22, a source is connected to the ground voltage supply GND, a drain is connected to the node n2, and a gate is connected to the node n1. In the PMOS transistor23, a source is connected to an electric power supply VDD, a drain is connected to the node n1, and a gate is connected to the node n2. In the PMOS transistor24, a source is connected to the electric power supply VDD, a drain is connected to the node n2, a gate is connected to the node n1. As described above, the latch circuit29is composed with NMOS transistors21,22and PMOS transistors23,24.

In the transfer transistor25, one terminal is connected to a bit line BL, the other terminal is connected to the node n1, and a gate is connected to a write word line WL (WRITE). In the transfer transistor26, one terminal is connected to a complemental bit line /BL, the other terminal is connected to the node n2, and a gate is connected to the write word line WL (WRITE). The read transistor27is connected to the read word line WL (READ), a drain is connected to the bit line BL, a gate is connected to the node. In the read transistor28, a source is connected to the read word line WL (READ), a drain is connected to the complemental bit line /BL, and a gate is connected to the node.

In the SRAM cell CELL1configured as described above, at writing data, high level is supplied to the write word line WL (WRITE) so that transfer transistors25,26turn on. Hence, a pair of bit lines (BL and /BL) is connected to the latch circuit29. The pair of bit lines is charged according to data for writing. Hence, the data is transferred to the latch circuit29. At reading data, voltage is supplied to the read word line WL (READ). Here, the read transistors27,28turn on/off according to the data stored in the latch circuit29. According to switching condition on/off of the read transistors27,28, voltage level of the read word line WL (READ) is transferred to the bit line BL or the complemental bit line /BL. In this way, the data stored in the SRAM cell is read out. That is to say, the bit lines BL, /BL perform as output line of data in the SRAM cell.

FIG. 3shows a circuit configuration of sense amplifier of the DRAM according to the first embodiment. This circuit has NMOS transistors31,32, PMOS transistors33,34, transfer transistors35,36, and transistors37,38. The transistors37,38correspond to the read transistors27,28ofFIG. 2. The transistors37,38are called as read transistors37,38hereinafter so thatFIG. 3corresponds toFIG. 2.

In the NMOS transistor31, a source is connected to complemental sense enable SEB, which has an inverted voltage level of sense enable SE, a drain is connected to a node n3, and a gate is connected to a node n4. In the NMOS transistor32, a source is connected to the complemental sense enable SEB, a drain is connected to the node n4, and the gate is connected to the node n3. In the PMOS transistor33, a source is connected to sense enable SE, a drain is connected to the node n3, a gate is connected to the node n4. In the PMOS transistor34, a source is connected to the sense enable SE, a drain is connected to the node n4, a gate is connected to the node n3. In the transfer transistor35, one terminal is connected to a data bus BUS, the other terminal is connected to the node n3, a gate is connected a Y-select line Y-SELECT. In the transfer transistor36, one terminal is connected to a data bus BUS′, the other terminal is connected to the node n4, a gate is connected to the Y-select line Y-SELECT. The node n3is connected to the bit line BL, and the node n4is connected to the complemental bit line /BL.

This circuit of the sense amplifier SA of the DRAM has the same configuration as the circuit of the SRAM cell CELL1of the SRAM as described above. NMOS transistors21,22; PMOS transistors23,24, transfer transistors25,26and read transistors27,28of the SRAM cell correspond to NMOS transistors31,32, PMOS transistors33,34, transfer transistors35,36and read transistors37,38of the sense amplifier SA of the DRAM.

In the sense amplifier of the DRAM configured as described above, the circuit39(the latch circuit) amplifying potential difference between the bit lines (BL, /BL) amplifies the potential difference based on charge storage stored in a capacitor (not shown). The capacitor is connected to the pair of bit lines. When high level is supplied to the Y-select line Y-SELECT, the transfer transistors35,36turn on. Hence, a voltage amplified by the latch circuit39is transferred to a data bus lines BUS, BUS′. The voltage transferred to the bus lines BUS, BUS′ is judged so that the data stored in the capacitor corresponding to the DRAM cell is read out. That is to say, for the configuration of the sense amplifier of the DRAM, the bus lines BUS, BUS′correspond to a data output line.

An advantage of the semiconductor device configured as explained above is described hereinafter. The conventional SRAM does not have the read transistors27,28. In the conventional SRAM, at reading data, data is read out based on a voltage level of the nodes n5, n6inFIG. 8, when the transfer transistors25,26turn on. For a circuit of the conventional SRAM at reading data, when the node n6is high level, both transfer transistor85and an NMOS transistor81turn on. At this time, if a resistance of the transfer transistor85is larger than a resistance of the NMOS transistor81because of manufacturing variation, current does not flow through the transfer transistor85but flow through the NMOS transistor81. As a result, data cannot be read out correctly in the conventional SRAM.

In the first embodiment, in consideration of the problem that there is reading error due to resistance ratio between the transfer transistor85and the NMOS transistor81, a configuration is designed so that data does not been transferred to the bit lines BL, /BL through the transfer transistors25,26. That is to say, as shown inFIG. 2, the read transistors27,28are formed in the SRAM. Hence, at reading data, data can be read out correctly through the transfer transistor27,28without relation to a resistance difference between the transfer transistor85and the NMOS transistor81. According to the design of the SRAM, the read transistors37,38corresponding to the read transistors27,28, are formed in the sense amplifier of the conventional DRAM (seeFIG. 9). As shown inFIG. 3, a tuning window of the SRAM can be matched to a tuning window of the DRAM, because the amplifier of the DRAM is formed as the same design as the SRAM cell CELL1. Even if the control voltage is set to be low and operation environment becomes unstable, the control accuracy of the SRAM cell CELL1is ensured, because of the configuration of the SRAM cell CELL1. Further, the sense amplifier of the DRAM has the same configuration as the SRAM cell CELL1, both the electric power saving and higher productivity of the semiconductor device10can be obtained.

Second Embodiment

FIG. 4shows a circuit diagram of a SRAM cell CELL1A of a semiconductor device according to a second embodiment. Whole configuration is the same asFIG. 1. The same number is numbered to a component having the same function to omit of explanation.

In the semiconductor device according to the second embodiment, a data protect transistor41is provided between the PMOS transistor23and the NMOS transistor21instead of the read transistor27of the first embodiment.

In the data protect transistor41, a source is connected to the node n1, a drain is connected to the NMOS transistor21, and a gate is connected to a gate control line REB as shown inFIG. 4.

For in the second embodiment, the gate of the transfer transistor25is connected to a write/read word line WL (WRITE/READ) and a gate of the transfer transistor26is connected to a write word line WL (WRITE).

In the SRAM cell CELL1A of the semiconductor device according to the second embodiment, at writing data, high level is supplied to the write word line WL (WRITE) and the read/write word line WL (READ/WRITE). Hence, the transfer transistors25,26turn on and data transferred from the bit lines BL, /BL is stored in the latch circuit29A.

At reading data, high level is supplied to the write/read word line WL (WRITE/READ) so that the transfer transistor25turns on. Low level is supplied to the write word line WL (WRITE) so that the transfer transistor26turns off. Low level is supplied to the gate control line REB so that the data protect transistor41turns off. As a result, according to a voltage level H/L of the node n1, level of the bit line BL is determined.

As described above, in the second embodiment, the data protect transistor41is provided between the PMOS transistor23and the NMOS transistor21. At reading data, when the data protect transistor turns off, a path between the NMOS transistor21and the transfer transistor25can be cut. As a result, a ratio-less can be obtained. The ratio-less means without relation to resistance ratio between the transfer transistor25and the NMOS transistor21, data can be read out.

A sense amplifier SAA of the DRAM is the same circuit configuration as the circuit inFIG. 4. When the circuit configuration inFIG. 4is applied as a sense amplifier of the DRAM, an electric power supply VDD inFIG. 4is changed to sense enable SE. A ground voltage supply GND is changed to the complemental sense enable. The complemental sense amplifier enable has inverted level of voltage to the sense enable SE. The bit line BL is changed to a data bus BUS and the complemental bit line /BL to a complemental data bus BUS′. The bit lines BL, /BL from the DRAM cell are connected to the nodes n1, n2inFIG. 4. The write/read word line WL (WRITE/READ) inFIG. 4is changed to a Y-select line Y-SELECT.

As described above, because of the data transistor41, incidence of the error due to the resistance ratio between the NMOS transistor21and the transfer transistor25can be prevented. It makes that a fine operation can be obtain even in low-voltage condition. Further, it makes yield ratio improved and high productivity can be obtained in the semiconductor device providing both SRAM and DRAM. When the configuration of the SRAM cell CELL1A is formed in much the same way as the sense amplifier of the DRAM like the first embodiment, a manufacturing optimum condition of the SRAM cell can be conformed to that of the sense amplifier. Hence, an effect of the manufacturing variation can be reduced.

Third Embodiment

FIG. 5shows a circuit diagram of SRAM cell CELL1B of a semiconductor device according to a third embodiment. Whole configuration is the same as the configuration inFIG. 1. In the SRAM cell CELL1B of the third embodiment, a back gate control line VPSUB is provided instead of the read transistor27of the first embodiment. The back gate control line VPSUB controls back gate voltage of the PMOS transistors23,24. The other configuration is the same as the first embodiment.

As shown inFIG. 5, the back gate control line VPSUB is connected to a back gate of the PMOS transistors23,24of SRAM cell CELL1B. In the SRAM cell configured as described above, at writing data, the back gate control line VPSUB is set to be high voltage. As a result, the PMOS transistors23,24are set to be difficult to turn on at writing data. At writing data, resistance of the PMOS transistors23,24is set to be high. Hence, a margin for writing can be maintained even at low voltage.

A sense amplifier SAB of the DRAM of the semiconductor device according to the third embodiment is formed as the same configuration as an equivalent circuit inFIG. 5. When the configuration inFIG. 5is applied to the sense amplifier of the DRAM, the electric power supply VDD inFIG. 5is changed to sense enable SE, and the ground voltage supply GND is set to be complemental sense amplifier enable. The complemental sense amplifier enable has inverted level of voltage to the sense enable SE. The bit line inFIG. 5is set to be a data bus BUS, and the complemental bit line /BL is to be a complemental data bus BUS′. The bit lines BL, /BL from the DRAM cell are connected to the nodes n1, n2inFIG. 5. The word line inFIG. 5is changed to the Y-select line Y-SELECT.

Herewith, it makes the margin for writing expanded and productivity improved in the semiconductor device.

Fourth Embodiment

FIG. 6shows an equivalent diagram of a SRAM cell CELL1C of the semiconductor device according to a fourth embodiment. Whole configuration is about the same as configuration inFIG. 1. In the SRAM cell CELL1C of the fourth embodiment, the bit line BL and the word line WL are provided for writing and reading individually.

The SRAM cell CELL1C provides NMOS transistors21,22, the PMOS transistors23,24, and the transfer transistors25,26in the first embodiment. The SRAM cell CELL1C further comprises read NMOS transistor61,62.

As shown inFIG. 6, in the read NMOS transistor61, a source is connected to a drain of the read NMOS transistor62, a gate is connected to the node n2, and a drain is connected to a read bit line BL (READ). In the read NMOS transistor62, a source is connected to the ground voltage supply GND, a drain is connected to the source of the read NMOS transistor61, a gate is connected to the read word line WL (READ). In the transfer transistor25, one terminal is connected to the write bit line BL (WRITE), the other terminal is connected to the node n1, and the gate is connected to the write word line WL (WRITE). In the transfer transistor26, one terminal is connected to the write bit line BL (WRITE), the other terminal is connected to the node n2, a gate is connected to the write word line WL (WRITE).

In the SRAM cell CELL1C configured as described above, at writing data, high level is supplied to the write word line WL (WRITE) so that the transfer transistors25,26turn on. Hence data for writing is transferred from the write bit line BL (WRITE) to the latch circuit29. On the other hand, at reading data, high level is supplied to the read word line WL (READ) so that the read transistor62turn on. Hence, the read transistor61turns on/off based on a voltage level of the node n2. A voltage level of the read bit line /BL (READ) is determined.

As described above, with providing the word line WL and the bit line BL for writing and reading individually, different transistor operates at reading and at writing. Hence, the ratio limit for reading is improved like the first and the second embodiment. Further, with providing the word line WL and the bit line BL for writing and reading individually, a change operation between reading and writing can be operated quickly.

The sense amplifier SAC of the DRAM of the semiconductor device according to the fourth embodiment is formed as the same configuration as the equivalent circuit inFIG. 6. When the configuration inFIG. 6is applied to the sense amplifier, the electric voltage supply VDD inFIG. 6is set to be sense enable SE, and the ground voltage supply GND is set to be complemental sense enable SEB. The complemental sense enable has the inverted voltage level to the sense enable SE. The bit line inFIG. 6is set to be a data bus BUS, and the complemental bit line /BL is set to be a complemental data bus BUS′. The bit lines BL, /BL from the DRAM cell are connected to the node n1, n2inFIG. 5. The write word line WL (WRITE) is changed to a Y-select line Y-SELECT.

Herewith, operation control and the ratio limit can be improved. Hence, productivity is improved in the semiconductor device including both SRAM and DRAM.

Fifth Embodiment

FIG. 7shows a circuit diagram of a SRAM cell CELL1D of the semiconductor device according to a fifth embodiment. Whole configuration is the same as the configuration inFIG. 1. For an aspect of the fifth embodiment, transfer gates71,72are provided instead of the transfer transistors25,26in the first embodiment. The transfer gate71is a NMOS transistor which gate is connected to a first word line WL1, and the transfer gate72is a PMOS transistor which gate is connected to a second word line WL2.

As described above, with providing the transfer gates71,72, a resistance value of the transfer gates71,72can be lower than the transfer transistors21,22which consist of one transistor. Hence, at writing data, a resistance value of the PMOS transistors23,24is higher than the transfer gates71,72. Current flows from the node n1through the NMOS transistor21. Hence, it makes an operation error lessen.

Here, the sense amplifier SAD of the DRAM of the semiconductor device according to the fifth embodiment is formed in much the same way as the equivalent circuit inFIG. 7. When the configuration inFIG. 7is applied to the DRAM, the electric power supply VDD is set to be sense enable SE and the ground voltage supply GND is set to be complemental sense enable SEB. The complemental sense enable SEB is inverted voltage level to the sense enable SE. The bit line BL inFIG. 7is changed to the data bus BUS and the complemental bit line /BL to complemental data bus BUS′. The bit lines BL, /BL from the DRAM cell are connected to the node n1, n2inFIG. 7. The write word line WL (WL1, WL2) inFIG. 7is changed to the Y-select line Y-SELECT.

As described above, a tolerance for variation of P/N ratio can be improved at reading and writing, because the resistance value of the transfer gate71,72is designed to be lower than the transistors21-24. The transistors21-24constitute the latch circuit. Hence, the productivity is improved in the semiconductor device providing both DRAM and SRAM.

As described above, in the embodiments from the first embodiment to the fifth embodiment, the SRAM cell is designed so that the margin for writing and reading of the SRAM is larger. The sense amplifier of DRAM is formed as to conform to the SRAM. However, only if the SRAM designed to improve the margin for writing and reading and the sense amplifier of the DRAM is formed according the design of the SRAM, the circuit configuration described in the first to the fifth embodiments is not limited. For a variety of the circuit configurations, the aspect of this invention can be obtained. As described above, in the embodiments from the first embodiment to the fifth embodiment, firstly the circuit is designed so that the margin for operation is larger and secondly the circuit configuration is applied to the sense amplifier of the DRAM. But, it may be the reverse method. That is to say, a circuit configuration designed for the sense amplifier of the DRAM may be applied to the SRAM cell. Even in this method, the aspect can be obtained that the tuning window of the SRAM is conformed to the tuning window of the DRAM.

It is apparent that the present invention is not limited to the above embodiment but may be modified and changed without departing from the scope and spirit of the invention.