Phase detecting module and related phase detecting method

A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase detecting result and a predetermined voltage to generate a comparing result. The counter is arranged to count one of the first input signal and the second input signal to generate a counting value. The phase detecting result and the counting value are reset if the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator if the counting value reaches a predetermined value.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a phase detecting module and phase detecting method thereof, and more particularly, to a phase detecting module capable of avoiding noise influence and a phase detecting method thereof.

2. Description of the Prior Art

Many signal processing circuits, e.g., phase locked loops (PLLs), usually comprise phase detectors each implemented for determining a phase relationship between two signals, and transmit the comparing result generated from the phase detector to other signal processing units for further processing.

FIG. 1is a block diagram illustrating a PLL100according to the prior art. As shown inFIG. 1, the conventional PLL100usually includes a phase detector101, a charge pump103, a low pass filter (LPF)105, a voltage-controlled oscillator (VCO)107, and a plurality of frequency dividers109and111. The frequency divider111is for frequency-dividing an input signal IS which has an input frequency Fin to form a reference signal RS which has a reference frequency Fr. The phase detector101is for comparing the reference signal RS with an output signal OUS which has an output frequency Fou to generate a phase detecting signal DS. The charge pump103determines to increase or decrease outputted charges according to the phase detecting signal DS which could be an up signal or a down signal. The voltage outputted by the charge pump103is processed via the LPF105to form a filtered control voltage VCF, and the VCO107thereby determines the outputted oscillation signal OS which has an oscillation frequency Fo according to the control signal VCF. The frequency divider109frequency-divides the oscillation signal OS to form the output signal OUS. As other detailed architecture and operations should be readily comprehended by those skilled in the art, further description is omitted for succinctness.

From the aforementioned description, the charge pump103primarily operates to raise or lower a following voltage according to the phase detecting result generated from the phase detector101. However, when the phase difference between two signals is very small, the phase detector101will not be able to determine the phase relationship between the two signals due to the noise or jitter attached onto the two signals, leading to a problem in the following signal processing.

SUMMARY OF THE INVENTION

Therefore, one of the objectives of the present invention is to provide a phase detecting module capable of avoiding misjudging the relationship between two signals due to noise or jitter attached onto the two signals.

In one embodiment of the present invention, a phase detecting module is disclosed. The phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is for comparing a first input signal and a second input signal to generate a phase detecting result. The comparator, coupled to the phase detecting unit, is for comparing the phase detecting result and a predetermined voltage to generate a comparing result. The counter is for counting one of the first input signal and the second input signal to generate a counting value, wherein the phase detecting result and the counting value are reset when the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator when the counting value reaches the predetermined value.

In another embodiment of the present invention, a phase detecting method is disclosed. The phase detecting method includes: (a) comparing a first input signal and a second input signal to generate a phase detecting result; (b) comparing the phase detecting result with a predetermined voltage to generate a comparing result; and (c) counting one of the first input signal and the second input signal to generate a counting value, wherein the phase detecting result and the counting value are reset when the counting value reaches a predetermined value, and the comparing result is outputted to a target device when the counting value reaches the predetermined value.

From the aforementioned embodiments, an influence from noise or jitter can be eliminated, and therefore a phase difference between two signals can be accurately detected.

DETAILED DESCRIPTION

FIG. 2is a diagram illustrating a phase detecting module200according to an embodiment of the present invention. As shown inFIG. 2, the phase detecting module200includes a phase detecting unit201, a counter203, a comparator205, a D flip-flop207(which can also be viewed as a register), a first switch209, a second switch211and a capacitor213. The phase detecting unit201is for comparing a first input signal1stand a second input signal2ndto generate a phase detecting result. In this embodiment, the phase detecting result is a control voltage VCTRLwhich is generated in response to a phase difference between the first input signal1stand the second input signal2nd, and is used to charge/discharge the capacitor213. In addition, the phase detector201includes a phase detector215and a charge pump217. The phase detector215compares the first input signal1stand the second input signal2nd, and outputs an up signal UP or a down signal DOWN to the charge pump217according to a phase difference between the first input signal1stand the second input signal2nd. Next, based on an output of the phase detector215, the charge pump217will charge or discharge the capacitor213accordingly.

The comparator205is for comparing the phase detecting result (i.e., VCTRL) with a predetermined voltage VREFto generate a comparing result OUT. The counter203is for counting one of the first input signal1stand the second input signal2nd(e.g., the second input signal2ndin this embodiment) to generate a counting value, wherein the phase detecting result is reset (i.e., the capacitor213is grounded via the first switch209) as well as the counting value when the counting value reaches a predetermined value, and the comparing result OUT is outputted to a target device (e.g., the D flip-flop207in this example) from the comparator205via the second switch211when the counting value reaches a predetermined value.

FIG. 3is a diagram illustrating signals of the phase detecting module200according to an embodiment of the present invention. Please refer toFIG. 3in conjunction withFIG. 2to acquire further comprehension of the phase detecting module proposed in the embodiment of the present invention. In the circuit shown inFIG. 2, the phase of the first input signal1stleads the phase of the second input signal2nd, and therefore the phase detecting unit201charges the capacitor213continuously to raise the control voltage VCTLL. When the control voltage VCTRLis lower than the predetermined voltage VREF, the comparing result OUT becomes “0” (i.e., a low level); on the other hand, when the control voltage VCTRLis higher than the predetermined voltage VREF, the comparing result OUT becomes “1” (i.e., a high level).

A control signal CS has a first level (“1” in this example) and a second level (“0” in this example). When the control signal CS is “1”, the first switch209is conducting and the second switch211is non-conducting; when the control signal is “0”, the first switch209is non-conducting and the second switch211is conducting. As shown inFIG. 2andFIG. 3, the counter203counts a number of periods of the second input signal2nd. After a counting value obtained by the counter203reaches a predetermined number (e.g., an integer N), a pulse with a level “1” is generated and then swiftly pulled back to a level “0”; in addition, the counting value is reset to zero. That is, under a general condition, the control signal CS is “0”, and the first switch209is non-conducting while the second switch211is conducting. As a result, the comparing result OUT is outputted to the D flip-flop207and then stored, as indicated by a signal Q shown inFIG. 3.

After the counter203counts a predetermined value (e.g., an integer N), the control signal CS becomes “1”, and the capacitor213will be grounded (i.e., coupled to a predetermined voltage) to make the control voltage VCTRLbecome 0 (i.e., the phase comparing result is reset). Meanwhile, the second switch211is non-conducting and therefore the comparing result OUT will not be output, and the D flip-flop207also latches the comparing result OUT. Afterward, the control signal CS will have a transition from level “1” to level “0” again, and the comparing result OUT will once more be output to the D flip-flop207and then stored. As described before, noise or jitter attached to signals might charge/discharge the capacitor213unnecessarily, which leads to an error in the control voltage VCTRL. With the help of the afore-mentioned mechanism capable of resetting the control voltage VCTRLafter a period of time, a misjudgment resulting from an error caused by long-term accumulated unnecessary charging/discharging can be avoided.

FIG. 4is a flowchart of a phase detecting method according to an embodiment of the present invention. As shown inFIG. 4, the phase detecting method according to the embodiment of the present invention includes the following steps:

Step401: Compare a first input signal1stand a second input signal2ndto generate a phase detecting result.

Step403: Compare a phase detecting result with a predetermined voltage to generate a comparing result.

Step405: Count one of the first input signal1stand the second input signal2ndto generate a counting value, wherein the phase detecting result and the counting value are reset when the counting value reaches a predetermined value, and the comparing result is output from the comparator to a target device when the counting value reaches the predetermined value.

As details of the phase detecting method according to the embodiment of the present invention are illustrated thoroughly inFIG. 2andFIG. 3, further description is not repeated here for the sake of brevity.

From the aforementioned embodiments, the influence of noise or jitter can be eliminated and the phase difference between two signals can be detected accurately.