Imaging system and endoscope system

An imaging system includes a camera unit and a main body. A clock detection circuit is configured to detect a first clock signal of the camera unit from first digital data transmitted from the camera unit. A phase comparator is configured to generate second digital data that represent a difference between a phase of the first clock signal and a phase of a second clock signal of the main body. A second communicator is configured to perform communication in a second direction in which the second digital data are transmitted to the camera unit in a blanking period. A first clock generation circuit is configured to generate the first clock signal synchronized with the second clock signal on the basis of the second digital data.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an imaging system and an endoscope system.

Description of Related Art

An imaging system that transmits an imaging signal by using a long cable has been developed. The imaging system includes a camera unit and a main body. In the imaging system, it is necessary to supply a clock signal to an imaging device that generates the imaging signal.

In a system disclosed in Japanese Unexamined Patent Application, First Publication No. HS-336425, a camera head and a main body (camera control unit) are connected together by two signal lines. The camera head corresponds to the camera unit. An image signal with which a clock signal of the camera head has been mixed is transmitted from the camera head to the main body. In the main body, the image signal and the clock signal are separated from each other. The clock signal of the camera head and a clock signal of the main body are compared with each other by a phase comparator. The difference between the two clock signals is transmitted to the camera head as a phase error signal. The phase error signal is a DC signal (direct current signal). The camera head performs feedback control on a PLL circuit by using the phase error signal and thus causes the clock signal of the camera head to be synchronized with the clock signal of the main body.

In an electronic endoscope device disclosed in Japanese Unexamined Patent Application. First Publication No. 2016-106902, a clock signal of a video scope is supplied from a processor. The video scope corresponds to the camera unit and the processor corresponds to the main body. A synchronization detection code is transmitted from the video scope to the processor in a blanking period. In the processor, processing for synchronization is executed on the basis of the synchronization detection code.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, an imaging system includes a camera unit and a main body. The camera unit includes a solid-state imaging device, a first clock generation circuit, a signal generation circuit, a data generation circuit, and a first communicator. The solid-state imaging device is configured to generate image data on the basis of a control signal. The first clock generation circuit is configured to generate a first clock signal. The signal generation circuit is configured to generate the control signal on the basis of the first clock signal. The data generation circuit is configured to generate first digital data by embedding the first clock signal into the image data. The first communicator is configured to perform communication in a first direction in which the first digital data are transmitted to the main body in a period different from a blanking period. The main body includes a second communicator, a clock detection circuit, a second clock generation circuit, and a phase comparator. The second communicator is configured to receive the first digital data transmitted from the camera unit. The clock detection circuit is configured to detect the first clock signal from the first digital data. The second clock generation circuit is configured to generate a second clock signal. The phase comparator is configured to compare a phase of the first clock signal with a phase of the second clock signal and generate second digital data that represent a difference between the phase of the first clock signal and the phase of the second clock signal. The second communicator is configured to perform communication in a second direction in which the second digital data are transmitted to the camera unit in the blanking period. The first communicator is configured to receive the second digital data transmitted from the main body in the blanking period. The camera unit and the main body are connected by a signal line through which the first digital data pass in the communication in the first direction and the second digital data pass in the communication in the second direction. The first clock generation circuit is configured to generate the first clock signal synchronized with the second clock signal on the basis of the second digital data.

According to a second aspect of the present invention, in the first aspect, the data generation circuit may be configured to generate an end code that represents a timing at which generation of the image data is intermittently stopped. The first communicator may be configured to transmit the end code to the main body when the generation of the image data is intermittently stopped. The second communicator may be configured to receive the end code transmitted from the camera unit. The second communicator may be configured to start transmission of the second digital data when the end code is received.

According to a third aspect of the present invention, in the second aspect, the main body may further include a code generation circuit configured to generate a start code that represents a timing at which the generation of the image data is started. The second communicator may be configured to transmit the start code to the camera unit in the blanking period. The first communicator may be configured to receive the start code transmitted from the main body in the blanking period. The signal generation circuit may be configured to generate the control signal for causing the solid-state imaging device to start the generation of the image data when the start code is received. The data generation circuit may be configured to start generation of the first digital data when the start code is received. The first communicator may be configured to start transmission of the first digital data when the start code is received.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the camera unit may further include a memory configured to hold the second digital data. The first clock generation circuit may be configured to generate the first clock signal on the basis of the second digital data held in the memory.

According to a fifth aspect of the present invention, in the first aspect, the main body may further include a frequency comparator configured to compare a frequency of the first clock signal with a frequency of the second clock signal and generate third digital data that represent a difference between the frequency of the first clock signal and the frequency of the second clock signal. The second communicator may be configured to transmit the third digital data to the camera unit in the blanking period. The first communicator may be configured to receive the third digital data transmitted from the main body in the blanking period. The first clock generation circuit may be configured to generate the first clock signal having the same frequency as the frequency of the second clock signal by adjusting the frequency of the first clock signal on the basis of the third digital data.

According to a sixth aspect of the present invention, in the fifth aspect, the second communicator may be configured to transmit the third digital data to the camera unit until the frequency comparator detects that the frequency of the first clock signal and the frequency of the second clock signal are the same. The second communicator may be configured to transmit the second digital data to the camera unit after the frequency comparator detects that the frequency of the first clock signal and the frequency of the second clock signal are the same.

According to a seventh aspect of the present invention, in the fifth aspect, the blanking period may include a first blanking period and a second blanking period after the first blanking period. The second communicator may be configured to transmit the third digital data to the camera unit in the first blanking period. The second communicator may be configured to transmit the second digital data to the camera unit in the second blanking period.

According to an eighth aspect of the present invention, in the fifth aspect, the second communicator may be configured to transmit a start code that represents a timing at which the generation of the image data is started to the camera unit in the blanking period. The first communicator may be configured to receive the start code transmitted from the main body in the blanking period. The signal generation circuit may be configured to generate the control signal for causing the solid-state imaging device to start the generation of the image data when the start code is received. The data generation circuit may be configured to start generation of the first digital data when the start code is received. The first communicator may be configured to start transmission of the first digital data when the start code is received. The first communicator may be configured to transmit an end code that represents a timing at which generation of data of one row included in the image data is completed to the main body when the solid-state imaging device completes the generation of the data of the one row. The second communicator may be configured to receive the end code transmitted from the camera unit. The frequency comparator may be configured to generate a count value by counting a pulse of the second clock signal in a counting period included in a horizontal reading period from a timing at which the start code is transmitted to a timing at which the end code is received. The frequency comparator may be configured to generate the third digital data on the basis of a result of comparing the count value with an estimation value calculated in advance. The estimation value is a count value that is assumed to be obtained by counting the pulse of the second clock signal in the counting period when it is assumed that the frequency of the first clock signal and the frequency of the second clock signal are the same.

According to a ninth aspect of the present invention, in the fifth aspect, the first clock generation circuit may include a ring oscillator circuit including at least four delay circuits. The frequency comparator may be configured to generate the third digital data including first frequency adjustment data and second frequency adjustment data. The first clock generation circuit may be configured to adjust the frequency of the first clock signal by adjusting a number of the delay circuits that are annularly connected together on the basis of the first frequency adjustment data and by adjusting an amount of current supplied to the delay circuits on the basis of the second frequency adjustment data.

According to a tenth aspect of the present invention, in the ninth aspect, the frequency comparator may be configured to generate the third digital data that include the first frequency adjustment data as an upper bit and include the second frequency adjustment data as a lower bit.

According to an eleventh aspect of the present invention, in any one of the fifth to tenth aspects, the signal generation circuit may include a digital-analog converter and a voltage-controlled oscillator. The digital-analog converter is configured to convert the third digital data into an analog voltage. The voltage-controlled oscillator is configured to generate the first clock signal on the basis of the analog voltage.

According to a twelfth aspect of the present invention, an imaging system includes a camera unit and a main body. The camera unit includes a solid-state imaging device, a first clock generation circuit, a signal generation circuit, a first communicator, and a phase comparator. The solid-state imaging device is configured to generate image data on the basis of a control signal. The first clock generation circuit is configured to generate a first clock signal. The signal generation circuit is configured to generate the control signal on the basis of the first clock signal. The first communicator is configured to transmit the image data to the main body in a period different from a blanking period. The phase comparator is configured to compare a phase of the first clock signal with a phase of a second clock signal and generate digital phase data that represent a difference between the phase of the first clock signal and the phase of the second clock signal. The main body includes a second communicator and a second clock generation circuit. The second communicator is configured to receive the image data transmitted from the camera unit. The second clock generation circuit is configured to generate the second clock signal. The second communicator is configured to transmit the second clock signal to the camera unit in the blanking period. The first communicator is configured to receive the second clock signal transmitted from the main body in the blanking period. The first communicator is configured to transmit the digital phase data to the main body in the blanking period. The second communicator is configured to receive the digital phase data transmitted from the camera unit in the blanking period. The second clock generation circuit is configured to generate the second clock signal synchronized with the first clock signal on the basis of the digital phase data.

According to a thirteenth aspect of the present invention, in the twelfth aspect, the camera unit may further include a frequency comparator configured to compare a frequency of the first clock signal with a frequency of the second clock signal and generate digital frequency data that represent a difference between the frequency of the first clock signal and the frequency of the second clock signal. The first communicator may be configured to transmit the digital frequency data to the main body in the blanking period. The second communicator may be configured to receive the digital frequency data transmitted from the camera unit in the blanking period. The second clock generation circuit may be configured to generate the second clock signal having the same frequency as the frequency of the first clock signal by adjusting the frequency of the second clock signal on the basis of the digital frequency data.

According to a fourteenth aspect of the present invention, in any one of the first to thirteenth aspects, an endoscope system includes a scope and the imaging system. The scope includes a tip end and a base end. The solid-state imaging device is disposed in the tip end. The main body is connected to the base end.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each of the embodiments will be described in detail by using an electronic endoscope system as an example of an imaging system.

First Embodiment

FIG. 1shows a configuration of an electronic endoscope system ES1according to a first embodiment of the present invention. The electronic endoscope system ES1shown inFIG. 1includes a scope1, a processor2, a cable3, and a display4.

The scope1is a camera unit. The scope1includes an imaging device10, a transmitter103, and a receiver104. The imaging device10includes a pixel unit101, a data generation circuit102, a memory105, a clock generation circuit106, and a signal generation circuit107. The processor2is a main body. The processor2includes a receiver201, an S/P converter202, an image processing circuit203, a clock generation circuit204, a clock data recovery circuit205, a phase comparator206, a transmitter207, and a frequency comparator210. Hereinafter, the clock data recovery circuit205is called a CDR circuit205.

A schematic configuration of the electronic endoscope system ES1will be described. The imaging device10is a solid-state imaging device. The imaging device generates image data on the basis of a control signal. The clock generation circuit106(first clock generation circuit) generates a first clock signal. The signal generation circuit107generates the control signal on the basis of the first clock signal. The data generation circuit102generates first digital data by embedding the first clock signal into the image data. The transmitter103(first transmitter) transmits the first digital data to the processor2. In this way, the transmitter103performs communication in a first direction. The first direction is a direction from the scope1toward the processor2. The receiver201(second receiver) receives the first digital data transmitted from the scope1. The CDR circuit205(clock detection circuit) detects the first clock signal from the first digital data. The clock generation circuit204(second clock generation circuit) generates a second clock signal. The phase comparator206compares the phase of the first clock signal with the phase of the second clock signal and generates second digital data that represent the difference between the phase of the first clock signal and the phase of the second clock signal. The transmitter207(second transmitter) transmits the second digital data to the scope1. In this way, the transmitter207performs communication in a second direction. The second direction is a direction from the processor2toward the scope1. The receiver104(first receiver) receives the second digital data transmitted from the processor2. The scope1and the processor2are connected by the cable3through which the first digital data pass in the communication in the first direction and the second digital data pass in the communication in the second direction. The clock generation circuit106generates the first clock signal synchronized with the second clock signal on the basis of the second digital data.

The frequency comparator210compares the frequency of the first clock signal with the frequency of the second clock signal and generates third digital data that represent the difference between the frequency of the first clock signal and the frequency of the second clock signal. The transmitter207transmits the third digital data to the scope1. The receiver104receives the third digital data transmitted from the processor2. The clock generation circuit106generates the first clock signal having the same frequency as the frequency of the second clock signal by adjusting the frequency of the first clock signal on the basis of the third digital data.

For example, the transmitter207transmits the third digital data to the scope1before transmitting the second digital data. After the frequency comparator210detects that the frequency of the first clock signal and the frequency of the second clock signal are the same, the transmitter207transmits the second digital data to the scope1.

The scope1includes a tip end11and a base end12. The imaging device10is disposed at the tip end11. The processor2is connected to the base end12.

A detailed configuration of the electronic endoscope system ES1will be described. The cable3electrically connects the scope1and the processor2together. The processor2is connected to the base end12of the scope1via the cable3. The cable3includes a signal line301and a signal line302. The transmitter103and the receiver201are connected to the signal line301. The receiver104and the transmitter207are connected to the signal line302.

The receiver104receives the second digital data and the third digital data transmitted by the transmitter207. The memory105holds the second digital data and the third digital data received by the receiver104. The memory105outputs the second digital data and the third digital data to the clock generation circuit106.

The clock generation circuit106generates the first clock signal on the basis of the second digital data and the third digital data held in the memory105. The first clock signal is synchronized with the second clock signal of the processor2. The phase of the first clock signal is controlled by using the second digital data. The frequency of the first clock signal is controlled by using the third digital data. The first clock signal generated by the clock generation circuit106is output to the signal generation circuit107and the data generation circuit102.

For example, the third digital data are received before the second digital data are received. When the third digital data are received, the clock generation circuit106adjusts the frequency of the first clock signal on the basis of the third digital data. When the second digital data are received, the clock generation circuit106adjusts the phase of the first clock signal on the basis of the second digital data. Therefore, after adjusting the frequency of the first clock signal on the basis of the third digital data, the clock generation circuit106adjusts the phase of the first clock signal on the basis of the second digital data.

The signal generation circuit107generates the control signal for controlling timings of operations of the pixel unit101, the data generation circuit102, and the transmitter103. The control signal generated by the signal generation circuit107is output to the pixel unit101, the data generation circuit102, and the transmitter103.

The pixel unit101generates a pixel signal at a timing that is based on the control signal output from the signal generation circuit107. The pixel signal output from the pixel unit101is converted into the image data. The data generation circuit102generates the first digital data at a timing that is based on the control signal output from the signal generation circuit107. The image data are serial data including multiple pieces of pixel data. For example, the data generation circuit102generates the first digital data by inserting data of the first clock signal between the multiple pieces of pixel data. A method of generating the first digital data is not limited to this method. The first digital data generated by the data generation circuit102are output to the transmitter103. The transmitter103transmits the first digital data to the processor2.

The first digital data transmitted from the transmitter103pass through the signal line301. The receiver201receives the first digital data transmitted by the transmitter103. The first digital data received by the receiver201are output to the S/P converter202and the CDR circuit205. The CDR circuit205reproduces the first clock signal from the first digital data. Reproduction of a clock signal is executed on the basis of a general clock-data-recovery technology. The first clock signal reproduced by the CDR circuit205is output to the receiver201, the S/P converter202, the phase comparator206, and the frequency comparator210. The receiver201receives the first digital data on the basis of the first clock signal. The S/P converter202converts the image data that are serial data into parallel data on the basis of the first clock signal. The image data are converted into the parallel data and are output to the image processing circuit203.

The clock generation circuit204includes a crystal oscillator208and a phase locked loop (PLL) circuit209. Hereinafter, the crystal oscillator208is called an XO208. The XO208includes a quartz crystal oscillator. The XO208and the PLL circuit209generate the second clock signal. The second clock signal generated by the XO208and the PLL circuit209is output to the image processing circuit203, the phase comparator206, and the frequency comparator210.

The image processing circuit203performs signal processing on the image data on the basis of the second clock signal. For example, the signal processing performed by the image processing circuit203is noise reduction, gamma correction, demosaicing processing, and the like. The image data are output from the image processing circuit203to the display4. The display4displays an image on the basis of the image data.

The frequency comparator210compares the frequency of the first clock signal with the frequency of the second clock signal. For example, the frequency comparator210includes a counter circuit and counts a pulse of the first clock signal and a pulse of the second clock signal in a predetermined period. Counting a pulse means counting the number of pulses. The count value (pulse number) of the first clock signal represents the frequency of the first clock signal. The count value (pulse number) of the second clock signal represents the frequency of the second clock signal. For example, the predetermined period corresponds to a horizontal reading period. In the horizontal reading period, the pixel signal is read from the pixel111of one row and data of one row included in the image data are output from the imaging device10.

While the data of one row included in the image data are received by the receiver201, the frequency comparator210counts a pulse of each of the first clock signal and the second clock signal. The frequency comparator210calculates the difference between the count value of the first clock signal and the count value of the second clock signal. The frequency comparator210generates the third digital data that represent the calculated difference. The third digital data generated by the frequency comparator210are output to the transmitter207. The transmitter207transmits the third digital data to the scope1. The third digital data transmitted from the transmitter207pass through the signal line302.

When the count value of the first clock signal and the count value of the second clock signal match each other, the frequency comparator210detects that the frequency of the first clock signal and the frequency of the second clock signal match each other. At this time, the frequency comparator210outputs a notification signal to the phase comparator206. The notification signal represents that the first clock signal having the same frequency as the frequency of the second clock signal has been generated.

After the notification signal is output from the frequency comparator210, the phase comparator206compares the phase of the first clock signal with the phase of the second clock signal. The phase comparator206generates the second digital data that represent the difference between the phase of the first clock signal and the phase of the second clock signal. The second digital data generated by the phase comparator206are output to the transmitter207. The transmitter207transmits the second digital data to the scope1. The second digital data transmitted from the transmitter207pass through the signal line302.

For example, a pixel signal is generated in a plurality of pixels disposed in an N-th row of the pixel unit101and the pixel signal is output from the pixel unit101. The numeral N is a natural number. Data of the N-th row included in the image data are generated on the basis of the pixel signal read from the plurality of pixels disposed in the N-th row. The data generation circuit102generates the first digital data including the data of the N-throw. The transmitter103transmits the first digital data including the data of the N-th row to the processor2. While the first digital data including the data of the N-th row are received by the receiver201, the frequency comparator210counts a pulse of each of the first clock signal and the second clock signal and generates the third digital data. After reception of the first digital data including the data of the N-th row is completed, the transmitter207transmits the third digital data to the scope1.

After the pixel signal is read from the plurality of pixels disposed in the N-th row, a pixel signal is generated in a plurality of pixels disposed in an (N+1)-th row of the pixel unit101and the pixel signal is output from the pixel unit101. Data of the (N+1)-th row included in the image data are generated on the basis of the pixel signal read from the plurality of pixels disposed in the (N+1)-th row. The data generation circuit102generates the first digital data including the data of the (N+1)-th row. The transmitter103transmits the first digital data including the data of the (N+1)-th row to the processor2. While the first digital data including the data of the (N+1)-th row are received by the receiver201, the frequency comparator210counts a pulse of each of the first clock signal and the second clock signal.

When the count value of the first clock signal and the count value of the second clock signal are not the same, the frequency comparator210generates the third digital data. After reception of the first digital data including the data of the (N+1)-th row is completed, the transmitter207transmits the third digital data to the scope1. The above-described operation is repeated until the count value of the first clock signal and the count value of the second clock signal match each other.

While the first digital data including the data of the (N+k)-th row are received by the receiver201, the frequency comparator210counts a pulse of each of the first clock signal and the second clock signal. The numeral k is a natural number. When the frequency of the first clock signal and the frequency of the second clock signal match each other, the frequency comparator210outputs a notification signal to the phase comparator206.

While the first digital data including the data of the (N+k+1)-th row are received by the receiver201, the phase comparator206compares the phase of the first clock signal with the phase of the second clock signal and generates the second digital data. After reception of the first digital data including the data of the (N+k+1)-th row is completed, the transmitter207transmits the second digital data to the scope1.

The transmitter103and the receiver201may perform optical communication. For example, the transmitter103includes a laser light source and the receiver201includes a light receiver. An optical fiber is used as the signal line301. Similarly, the transmitter207and the receiver104may perform optical communication. For example, the transmitter207includes a laser light source and the receiver104includes a light receiver. An optical fiber is used as the signal line302.

The transmitter103and the receiver201may perform wireless communication. For example, the transmitter103and the receiver201include an antenna and a wireless circuit. Similarly, the transmitter207and the receiver104may perform wireless communication. For example, the transmitter207and the receiver104include an antenna and a wireless circuit.

At least one of the data generation circuit102, the memory105, the clock generation circuit106, and the signal generation circuit107may be disposed outside the imaging device10. At least one of the transmitter103and the receiver104may be disposed inside the imaging device10.

FIG. 2shows a configuration of the imaging device10. An example in which the imaging device10is constituted by a CMOS image sensor will be described. The imaging device10shown inFIG. 2includes the pixel unit101, the data generation circuit102, the memory105, the clock generation circuit106, the signal generation circuit107, and a column circuit114.

The memory105is connected to a signal input terminal124. The signal input terminal124is connected to the receiver104. The second digital data and the third digital data received by the receiver104are input to the memory105via the signal input terminal124. The second digital data and the third digital data are stored on the memory105.

The pixel unit101includes a plurality of pixels111that are two-dimensionally disposed. Each of the plurality of pixels111includes a photoelectric conversion element and generates a pixel signal. The number of rows and columns in an array of the plurality of pixels111is two or more.

The signal generation circuit107includes a vertical scanning circuit112, a horizontal scanning circuit113, and a timing generation circuit116. The timing generation circuit116generates a timing signal on the basis of the first clock signal generated by the clock generation circuit106. For example, the timing signal includes a horizontal synchronizing signal and a vertical synchronizing signal. The timing signal generated by the timing generation circuit116is output to the vertical scanning circuit112, the horizontal scanning circuit113, and the data generation circuit102.

The vertical scanning circuit112and the horizontal scanning circuit113generate a control signal on the basis of the timing signal output from the timing generation circuit116. A pixel signal is read from the plurality of pixels111at a timing that is based on the control signal. The vertical scanning circuit112controls the timing at which the pixel signal is read from the plurality of pixels111for each row in the array of the plurality of pixels111. The vertical scanning circuit112outputs the control signal to a row control line121connected to the pixels111of each row. In this way, the vertical scanning circuit112controls the output of the control signal from the pixels111of each row to a vertical signal line122. The vertical signal line122is connected to the pixels111of each column.

A plurality of column circuits114are disposed. The column circuit114is connected to the vertical signal line122of each column. The column circuit114performs signal processing on the pixel signal output from the pixel111to the vertical signal line122. For example, the signal processing performed by the column circuit114is noise reduction, signal amplification, AD conversion, and the like. Therefore, the column circuit114is an AD conversion circuit that converts the pixel signal read from the plurality of pixels11into a digital pixel signal.

The horizontal scanning circuit113sequentially transfers a plurality of pixel signals read from the pixels111of plurality of columns to the data generation circuit102. The horizontal scanning circuit113outputs a control signal to the plurality of column circuits114. The horizontal scanning circuit113causes the plurality of column circuits114to sequentially output the digital pixel signal to a horizontal signal line123. The horizontal signal line123is connected to the plurality of column circuits114and the data generation circuit102. The digital pixel signal sequentially output from the plurality of column circuits114to the horizontal signal line123is transferred to the data generation circuit102by the horizontal signal line123.

The data generation circuit102includes an output circuit115. The output circuit115embeds the first clock signal into the digital pixel signal at a timing that is based on the timing signal output from the timing generation circuit116. In this way, the output circuit115generates the first digital data. The output circuit115converts the form of the first digital data into a form suitable for fast signal transmission. The output circuit115is connected to a signal output terminal125. The signal output terminal125is connected to the transmitter103. The first digital data generated by the output circuit115is output to the signal output terminal125. The first digital data is output to the transmitter103via the signal output terminal125.

FIG. 3shows a configuration of the clock generation circuit106. The clock generation circuit106shown inFIG. 3includes a DAC131and a ring oscillator132.

The DAC131is a digital-analog converter and converts the third digital data into an analog voltage. The ring oscillator132is a voltage-controlled oscillator (VCO) and generates a first clock signal CLKOUT on the basis of the analog voltage generated by the DAC131.

The third digital data held in the memory105includes frequency adjustment data FCTL. For example, the frequency adjustment data FCTL are data of 12 bits. The frequency adjustment data FCTL includes first frequency adjustment data FCTL and second frequency adjustment data FCTL2. For example, the first frequency adjustment data FCTL1are data of 2 bits and constitute the upper bits of the frequency adjustment data FCTL. For example, the second frequency adjustment data FCTL2are data of 10 bits and constitute the lower bits of the frequency adjustment data FCTL. The first frequency adjustment data FCTL1are output from the memory105to the ring oscillator132. The second frequency adjustment data FCTL2are output from the memory105to the DAC131. The DAC131generates a first voltage and a second voltage on the basis of the second frequency adjustment data FCTL2. The first voltage and the second voltage generated by the DAC131are output to the ring oscillator132.

The ring oscillator132consists of a ring oscillator circuit including at least four inverters INV (delay circuit). A reference numeral of one inverter INV is shown as a representative inFIG. 3. In the example shown inFIG. 3, sixteen inverters INV are disposed. The number of inverters INV is not limited to sixteen. The ring oscillator132further includes a NAND circuit ND1, a plurality of transistors Mip, a plurality of transistors Min, a selector SEL1, a selector SEL2, a selector SEL3, a selector SEL4, a selector SEL5, and a selector SEL6.

The NAND circuit ND1and a plurality of inverters RO are connected in series to each other. The inverter INV connected to an output terminal of the NAND circuit ND1is defined as a first inverter. The inverter INV connected to an output terminal of an N-th inverter is defined as an (N+)-th inverter. The numeral N is a natural number of any one of one to fifteen. An enable signal ENB and an output signal of the sixteenth inverter are input to the NAND circuit ND1. The enable signal ENB is output from the timing generation circuit116. When the state of the enable signal ENB changes, a pulse signal starts to be transmitted in the NAND circuit ND1and the plurality of inverters INV.

Each of the plurality of transistors Mip is connected to a first power source terminal of any one of the plurality of inverters INV. Each of the plurality of transistors Min is connected to a second power source terminal of any one of the plurality of inverters INV. The first voltage and the second voltage are output from the DAC131. The first voltage is applied to the plurality of transistors Mip and the second voltage is applied to the plurality of transistors Min. The current that is based on the first voltage and the second voltage is supplied to the plurality of inverters INV by the plurality of transistors Mip and the plurality of transistors Min. The delay time of the plurality of inverters INV changes on the basis of the first voltage and the second voltage.

A delay time t in each of the plurality of inverters INV is represented by following Expression (1).
t=Vth*Cin/Isupply  (1)

In Expression (1), a voltage Vth is a threshold value of each inverter INV. In Expression (1), a capacitance Cin is an input capacitance of each inverter IN. In Expression (1), a current amount Isupply is the amount of current supplied to each inverter INV. The current amount Isupply changes on the basis of the first voltage and the second voltage. The pulse signal has a cycle that is based on the delay time in one inverter NV the number of inverters INV, and the delay time in the NAND circuit ND. The frequency of the pulse signal changes on the basis of the first voltage and the second voltage.

The selector SEL1is connected to an output terminal of each of the fourth inverter, the eighth inverter, the twelfth inverter, and the sixteenth inverter. The pulse signal output from each of the fourth inverter, the eighth inverter, the twelfth inverter, and the sixteenth inverter is input to the selector SEL1. The first frequency adjustment data FCTL1are input to the selector SEL1. The selector SEL1selects anyone of a plurality of pulse signals on the basis of the first frequency adjustment data FCTL1. The selector SEL1outputs the selected pulse signal to the NAND circuit ND1.

The first frequency adjustment data FCTL1represent the number of inverters INV included in the ring oscillator circuit. In a case in which the selector SEL1outputs the pulse signal output from the fourth inverter, the NAND circuit ND1and four inverters INV are included in the ring oscillator circuit. In a case in which the selector SEL1outputs the pulse signal output from the eighth inverter, the NAND circuit ND1and eight inverters INV are included in the ring oscillator circuit. In a case in which the selector SEL1outputs the pulse signal output from the twelfth inverter, the NAND circuit ND1and twelve inverters INV are included in the ring oscillator circuit. In a case in which the selector SEL1outputs the pulse signal output from the sixteenth inverter, the NAND circuit ND1and sixteen inverters INV are included in the ring oscillator circuit.

The number of inverters INV included in the ring oscillator circuit is represented as4n. The numeral n is a natural number of any one of one to four. The first clock signal has a frequency that is based on the number of inverters INV that are annularly connected together. When the numeral n is changed from one to two, the number of inverters INV is changed from four to eight. For this reason, the frequency of the pulse passing through the NAND circuit ND1and the plurality of inverters INV becomes almost half.

The selector SEL2is connected to an output terminal of each of the first inverter, the second inverter, the third inverter, and the fourth inverter. The pulse signal output from each of the first inverter, the second inverter, the third inverter, and the fourth inverter is input to the selector SEL2. The phases of a plurality of pulse signals input to the selector SEL2are different from each other.

The selector SEL3is connected to an output terminal of each of the second inverter, the fourth inverter, the sixth inverter, and the eighth inverter. The pulse signal output from each of the second inverter, the fourth inverter, the sixth inverter, and the eighth inverter is input to the selector SEL3. The phases of a plurality of pulse signals input to the selector SEL3are different from each other.

The selector SEL4is connected to an output terminal of each of the third inverter, the sixth inverter, the ninth inverter, and the twelfth inverter. The pulse signal output from each of the third inverter, the sixth inverter, the ninth inverter, and the twelfth inverter is input to the selector SEL4. The phases of a plurality of pulse signals input to the selector SEL4are different from each other.

The selector SEL5is connected to an output terminal of each of the fourth inverter, the eighth inverter, the twelfth inverter, and the sixteenth inverter. The pulse signal output from each of the fourth inverter, the eighth inverter, the twelfth inverter, and the sixteenth inverter is input to the selector SEL5. The phases of a plurality of pulse signals input to the selector SEL5are different from each other.

The second digital data held in the memory105includes phase adjustment data PCTL. For example, the phase adjustment data PCTL are data of two bits. The phase adjustment data PCTL are output from the memory105to the ring oscillator132. The phase adjustment data PCTL are input to the selector SEL2, the selector SEL3, the selector SEL4, and the selector SEL5. Each of the selector SEL2, the selector SEL3, the selector SEL4, and the selector SEL5selects any one of the plurality of pulse signals on the basis of the phase adjustment data PCTL. Each of the selector SEL2, the selector SEL3, the selector SEL4, and the selector SEL5outputs the selected pulse signal.

The selector SEL6is connected to an output terminal of each of the selector SEL2, the selector SEL3, the selector SEL4, and the selector SEL5. The pulse signal output from each of the selector SEL2, the selector SEL3, the selector SEL4, and the selector SEL5is input to the selector SEL6. The first frequency adjustment data FCTL is input to the selector SEL6. The selector SEL6selects any one of the plurality of pulse signals on the basis of the first frequency adjustment data FCTL1. The selector SEL6outputs the selected pulse signal as the first clock signal CLKOUT.

In a case in which the selector SEL1outputs the pulse signal output from the fourth inverter, the selector SEL6outputs the pulse signal output from the selector SEL2. In a case in which the selector SEL1outputs the pulse signal output from the eighth inverter, the selector SEL6outputs the pulse signal output from the selector SEL3. In a case in which the selector SEL1outputs the pulse signal output from the twelfth inverter, the selector SEL6outputs the pulse signal output from the selector SEL4. In a case in which the selector SEL1outputs the pulse signal output from the sixteenth inverter, the selector SEL6outputs the pulse signal output from the selector SEL5.

The frequency comparator210generates the third digital data that include the first frequency adjustment data FCTL1as the upper bits and include the second frequency adjustment data FCTL2as the lower bits. The frequency comparator210may generate the third digital data that include the first frequency adjustment data FCTL1as the lower bits and include the second frequency adjustment data FCTL2as the upper bits. The clock generation circuit106adjusts the number of inverters INV that are annularly connected together on the basis of the first frequency adjustment data FCTL1and adjusts the amount of current supplied to the inverter INV on the basis of the second frequency adjustment data FCTL2. In this way, the clock generation circuit106adjusts the frequency of the first clock signal. The frequency comparator210can greatly change the frequency of the first clock signal by changing the number of inverters INV that are annularly connected together. The frequency comparator210can finely change the frequency of the first clock signal by changing the amount of current supplied to the inverter INV.

When the pulse is transferred in the ring oscillator132, the NAND circuit ND1and at least two inverters INV are annularly connected together. As long as the NAND circuit ND1and an even number of inverters INV are annularly connected together, the number of inverters INV that are annularly connected together is not limited to the above-described example.

FIG. 4shows an operation for adjusting the frequency and the phase of the first clock signal. In the example shown inFIG. 3, four, eight, twelve, or sixteen inverters INV are annularly connected together. An operation of the electronic endoscope system ES1will be described in a case in which twelve inverters INV are annularly connected together.

The frequency comparator210counts a pulse of each of the first clock signal and the second clock signal. For example, when the count value of the second clock signal becomes a predetermined number x, the frequency comparator210stops counting (Step S100).

After Step S100, the frequency comparator210determines whether or not the difference (x-n) between a count value n of the first clock signal and a count value x of the second clock signal is 0 (Step S105).

When the frequency comparator210determines that the difference (x-n) is 0 in Step S105, the frequency comparator210outputs the notification signal to the phase comparator206(Step S110). After Step S110, the phase comparator206compares the phase of the first clock signal with the phase of the second clock signal (Step S115).

After Step S115, the phase comparator206determines whether or not the phase of the first clock signal and the phase of the second clock signal are the same (Step S120).

When the phase comparator206determines that the phase of the first clock signal and the phase of the second clock signal are the same in Step S120, the processing shown inFIG. 4is completed. When the phase comparator206determines that the phase of the first clock signal and the phase of the second clock signal are not the same in Step S120, the phase comparator206generates the second digital data that represent the difference between the phase of the first clock signal and the phase of the second clock signal. The phase comparator206outputs the second digital data to the transmitter207. The transmitter207transmits the second digital data to the scope1(Step S140). After Step S140, Step S115is executed.

When the frequency comparator210determines that the difference (x-n) is not 0 in Step S105, the frequency comparator210calculates a ratio (n/x) between the count value n of the first clock signal and the count value x of the second clock signal. The frequency comparator210determines the range of the ratio (n/x)(Step S125).

In order to simplify the description, the delay time of the NAND circuit ND1is neglected. In a case in which sixteen inverters INV instead of twelve inverters INV are annularly connected together, the number of inverters INV becomes 16/12 times, that is, 1.33 times. For this reason, the frequency of the first clock signal becomes 12/16 times, that is, 0.75 times. In a case in which eight inverters INV instead of twelve inverters INV are annularly connected together, the number of inverters INV becomes 8/12 times, that is, 0.67 times. For this reason, the frequency of the first clock signal becomes 12/8 times, that is, 1.5 times.

In a case in which the ratio (n/x) is less than 0.67, the frequency of the first clock signal needs to be increased. In this case, eight or four inverters INV instead of twelve inverters INV need to be annularly connected together. In a case in which the ratio (n/x) is greater than 1.33, the frequency of the first clock signal needs to be decreased. In this case, sixteen inverters INV instead of twelve inverters INV need to be annularly connected together. When the ratio (n/x) is less than 0.67 or greater than 1.33, the frequency comparator210generates the third digital data including the first frequency adjustment data FCTL1on the basis of the ratio (n/x). The frequency comparator210outputs the third digital data to the transmitter207. The transmitter207transmits the third digital data to the scope1(Step S130). After Step S130, Step S100is executed.

In a case in which the ratio (n/x) is greater than 0.67 and less than 1.33, the frequency of the first clock signal needs to be finely changed. The frequency comparator210generates the third digital data including the second frequency adjustment data FCTL2on the basis of the difference (x-n). The frequency comparator210outputs the third digital data to the transmitter207. The transmitter207transmits the third digital data to the scope1(Step S135). After Step S135, Step S100is executed. The second frequency adjustment data FCTL2are data for changing the amount of current supplied to each inverter INV. When the amount of current changes, the delay time in the inverter INV changes in accordance with above-described Expression (1). For this reason, the frequency of the first clock signal changes.

The frequency comparator210shown inFIG. 1is not essential. The clock generation circuit106may generate the first clock signal on the basis of only the second digital data generated by the phase comparator206.

In the first embodiment, the scope1does not include a quartz crystal oscillator. For this reason, the electronic endoscope system ES1can miniaturize the scope1. The first clock signal is generated on the basis of the second digital data and the third digital data transmitted from the processor2. For this reason, the electronic endoscope system ES1can supply a clock signal having a stable frequency to the imaging device10. In the electronic endoscope system ES1, omission of frames is suppressed and a quality image is transmitted to the processor2.

A clock signal is not transmitted from the processor2to the scope1. The second digital data and the third digital data for controlling generation of a clock signal are transmitted from the processor2to the scope1. Compared to a case in which a high-speed clock signal is transmitted, the degree of influence due to the noise is small.

The clock generation circuit106controls the frequency of the first clock signal on the basis of the second digital data and the third digital data. For this reason, fluctuation of the frequency due to factors such as temperature and a power source voltage is suppressed. Since the clock generation circuit106includes a digital-analog converter and a voltage-controlled oscillator, the configuration of the clock generation circuit106is simplified.

The transmitter207does not need to always transmit the second digital data and the third digital data. The transmitter207may intermittently transmit the second digital data and the third digital data. Even in a period in which the second digital data and the third digital data are not transmitted, the second digital data and the third digital data are output from the memory105to the clock generation circuit106. For this reason, the clock generation circuit106can stably generate a clock signal.

The clock generation circuit106adjusts the frequency of the first clock signal on the basis of the third digital data generated by the frequency comparator210. Thereafter, the clock generation circuit106adjusts the phase of the first clock signal on the basis of the second digital data generated by the phase comparator206. In a case in which the frequency of the first clock signal greatly changes due to the influence of temperature, noise, and the like, the clock generation circuit106can promptly adjust the frequency. In addition, it is possible to prevent the phase of the first clock signal from being adjusted in a state in which the frequency of the first clock signal and the frequency of the second clock signal are shifted from each other.

The clock generation circuit106can greatly change the frequency of the first clock signal on the basis of the first frequency adjustment data FCTL1. The clock generation circuit106can finely change the frequency of the first clock signal on the basis of the second frequency adjustment data FCTL2.

Second Embodiment

FIG. 5shows a configuration of an electronic endoscope system ES2according to a second embodiment of the present invention. The same part as the part shown inFIG. 1will not be described.

The scope1shown inFIG. 1is changed to a scope1a. The scope1aincludes an imaging device10aand a communicator108. The imaging device10shown inFIG. 1is changed to the imaging device10a. The imaging device10aincludes a pixel unit101, a data generation circuit102, a memory105, a clock generation circuit106, a signal generation circuit107, and a code detector109.

The processor2shown inFIG. 1is changed to a processor2a. The processor2aincludes an S/P converter202, an image processing circuit203, a clock generation circuit204, a CDR circuit205, a phase comparator206, a frequency comparator210, a communicator211, a code detector212, and a code generation circuit213. In the processor2a, the receiver201shown inFIG. 1is changed to the communicator211. The processor2adoes not include the transmitter207shown inFIG. 1.

The communicator108(first communicator) transmits first digital data to the processor2ain a period excluding a blanking period. The communicator211(second communicator) receives the first digital data transmitted from the scope1a. The communicator211transmits second digital data to the scope1ain the blanking period. The communicator108receives the second digital data transmitted from the processor2ain the blanking period.

The imaging device10acompletes generation of image data in the blanking period. In the blanking period, the output of effective image data from the imaging device10ais stopped. The blanking period intermittently occurs. In a period between two blanking periods, the imaging device10agenerates image data that are based on a pixel signal read from a pixel111of one row.

The communicator211transmits third digital data to the scope1ain the blanking period. The communicator108receives the third digital data transmitted from the processor2ain the blanking period. For example, the second digital data and the third digital data are transmitted in respective blanking periods different from each other. For example, the communicator211transmits the third digital data to the scope1ain a first blanking period. The communicator211transmits the second digital data to the scope1ain a second blanking period after the first blanking period.

For example, between the first blanking period and the second blanking period, a pixel signal is read from the pixel111of at least one row and data of at least one row included in the image data are output from the imaging device10a. In a case in which a pixel signal is read from the pixel111of at least two rows between the first blanking period and the second blanking period, a blanking period is inserted each time a pixel signal is read from the pixel111of one row.

The data generation circuit102generates an end code that represents a timing at which generation of the image data is intermittently stopped. The end code represents a timing at which generation of data of one row included in the image data is completed and a blanking period is started. When generation of the image data is intermittently stopped, the communicator108transmits the end code to the processor2a. The communicator211receives the end code transmitted from the scope1a. When the end code is received, the communicator211starts transmission of the second digital data or the third digital data.

The code generation circuit213generates a start code that represents a timing at which generation of the image data is started. The start code represents a timing at which the blanking period is completed. The communicator211transmits the start code to the scope1ain the blanking period. The communicator108receives the start code transmitted from the processor2ain the blanking period. When the start code is received, the signal generation circuit107generates a control signal for causing the imaging device10ato start generation of the image data. When the start code is received, the data generation circuit102starts generation of the first digital data. When the start code is received, the communicator108starts transmission of the first digital data.

While the communicator108transmits the first digital data, the communicator211does not transmit the second digital data or the third digital data. While the communicator211transmits the second digital data or the third digital data, the communicator108does not transmit the first digital data.

When the imaging device10acompletes generation of data of one row included in the image data, the communicator108transmits the end code to the processor2a. The communicator211receives the end code transmitted from the scope1a. The frequency comparator210generates a count value by counting a pulse of the second clock signal in a counting period. The counting period is included in a horizontal reading period from the timing at which the start code is transmitted to the timing at which the end code is received. The frequency comparator210generates the third digital data on the basis of a result of comparing the count value with an estimation value calculated in advance. The estimation value is a count value that is assumed to be obtained by counting a pulse of the second clock signal in the counting period when it is assumed that the frequency of the first clock signal and the frequency of the second clock signal are the same.

The cable3shown inFIG. 1is changed to a cable3a. The cable3aincludes a signal line303. The communicator108and the communicator211are connected to the signal line303. The first digital data transmitted from the communicator108and the end code transmitted from the communicator108pass through the signal line303. The second digital data and the third digital data transmitted from the communicator211and the start code transmitted from the communicator211pass through the signal line303.

The communicator108and the communicator211may perform wireless communication. For example, the communicator108and the communicator211include an antenna and a wireless circuit.

The data generation circuit102outputs the end code to the communicator108after outputting the first digital data to the communicator108. The communicator108transmits the end code to the processor2aafter transmitting the first digital data to the processor2a.

The communicator211receives the end code transmitted by the communicator108after receiving the first digital data transmitted by the communicator108. A data sequence including the first digital data and the end code is output to the code detector212. The code detector212detects the end code from the data sequence received by the communicator211. When the end code is detected, the code detector212outputs a transmission start signal to the communicator211. The communicator211starts transmission of the second digital data or the third digital data on the basis of the transmission start signal.

The code generation circuit213generates the start code at a predetermined timing. For example, the predetermined timing is a timing at which a predetermined time passes from a timing at which the end code is detected. The predetermined timing may be determined by the processor2aat its discretion. The start code generated by the code generation circuit213is output to the phase comparator206, the frequency comparator210, and the communicator211. The communicator211transmits the start code to the scope1aafter transmitting the second digital data or the third digital data to the scope1a.

When the start code is output from the code generation circuit213, the frequency comparator210starts counting of a pulse of the second clock signal. While the communicator211receives the first digital data, the frequency comparator210counts a pulse of the second clock signal. When the end code is detected, the code detector212outputs the end code to the frequency comparator210. When the end code is output from the code detector212, the frequency comparator210stops counting of a pulse of the second clock signal.

The number of data of one row included in the image data is set in advance. For example, the data of one row include data generated on the basis of a pixel signal read from the pixel111of the M-th column. The numeral M is a natural number of two or more. For example, a start timing of the counting period is the same as a start timing of the horizontal reading period and an end timing of the counting period is the same as an end timing of the horizontal reading period.

It is possible to calculate the length of a period necessary for transmitting M pieces of data in advance when it is assumed that the imaging device10ais driven by using the first clock signal having the same frequency as the frequency of the second clock signal. A count value is calculated as the estimation value in advance when it is assumed that the frequency comparator210counts a pulse of the second clock signal in the period. For example, the processor2aincludes a circuit that calculates the above-described estimation value. For example, the processor2aincludes a memory that stores the calculated estimation value. The frequency comparator210reads the estimation value from the memory and compares the count value of the second clock signal with the estimation value. The frequency comparator210calculates the difference between the count value of the second clock signal and the estimation value and generates the third digital data on the basis of the difference. The frequency comparator210outputs the third digital data to the communicator211.

The start timing of the counting period may not be the same as the start timing of the horizontal reading period. The counting period may be started after the start timing of the horizontal reading period. The end timing of the counting period may not be the same as the end timing of the horizontal reading period. The counting period may be completed before the end timing of the horizontal reading period.

When the frequency of the first clock signal and the frequency of the second clock signal match each other, the frequency comparator210outputs a notification signal to the phase comparator206. The notification signal represents that the first clock signal having the same frequency as the frequency of the second clock signal has been generated. For example, in the horizontal reading period of data of the N-th row included in the image data, the notification signal is output to the phase comparator206. After the notification signal is output from the frequency comparator210, the start code is output from the code generation circuit213and the horizontal reading period of data of the (N+1)-th row included in the image data is started. At this time, the phase comparator206compares the phase of the first clock signal with the phase of the second clock signal and generates second digital data. The phase comparator206outputs the second digital data to the communicator211.

The communicator108receives the start code transmitted by the communicator211after receiving the second digital data or the third digital data transmitted by the communicator211. A data sequence including one of the second digital data and the third digital data and the start code is output to the code detector109. The code detector109detects the start code from the data sequence received by the communicator108. The code detector109outputs the second digital data or the third digital data excluding the start code to the memory105. The memory105holds the second digital data or the third digital data output from the code detector109.

When the start code is detected, the code detector109outputs a code detection signal to the signal generation circuit107. The signal generation circuit107generates a control signal for starting generation and transmission of the image data on the basis of the code detection signal. The control signal generated by the signal generation circuit107is output to the pixel unit101, the data generation circuit102, and the communicator108. The pixel unit101starts generation of the pixel signal on the basis of the control signal. The data generation circuit102starts generation of the first digital data on the basis of the control signal. The communicator108starts transmission of the first digital data on the basis of the control signal.

The end code may be embedded into the image data. The CDR circuit205may detect the end code by reproducing the end code from the first digital data.

FIG. 6shows a configuration of the imaging device10. The same part as the part shown inFIG. 2will not be described.

In the imaging device10a, a signal input/output terminal126is disposed instead of the signal input terminal124and the signal output terminal125. The code detector109and the output circuit115are connected to the signal input/output terminal126. The signal input/output terminal126is connected to the communicator108. The second digital data or the third digital data received by the communicator108and the start code received by the communicator108are input to the code detector109via the signal input/output terminal126. The output circuit115generates the first digital data and the end code. The first digital data generated by the output circuit115and the end code generated by the output circuit115are output to the signal input/output terminal126. The first digital data and the end code are output to the communicator108via the signal input/output terminal126.

FIG. 7shows an operation of the electronic endoscope system ES2. InFIG. 7, a waveform of a horizontal synchronizing signal generated by the timing generation circuit116is shown. InFIG. 7, a data sequence of the first digital data and an end code END output from the data generation circuit102is shown. InFIG. 7, a communication state of the processor2aand communication data of the processor2aare shown. The communication data of the processor2ainclude reception data received by the communicator211and transmission data transmitted by the communicator211. The reception data include the first digital data and the end code END, the transmission data include clock control data CLK and a start code START, the clock control data CLK are the second digital data or the third digital data. InFIG. 7, time passes in the right direction.

When the electronic endoscope system ES2is activated, for example, the clock generation circuit106generates the first clock signal on the basis of a predetermined voltage. The predetermined voltage is the voltage designed for the first clock signal to be synchronized with the second clock signal.

The pixel unit101outputs a pixel signal in a horizontal reading period T1. The data generation circuit102generates the first digital data in the horizontal reading period T1. The data to which a number is attached inFIG. 7are image data that are based on a pixel signal of each column in a predetermined row. The communicator108transmits the first digital data in the horizontal reading period T1. The length of the horizontal reading period T1is controlled on the basis of the timing signal, that is, the horizontal synchronizing signal generated by the signal generation circuit107.

The processor2ais in the reception state in the horizontal reading period T1. The communicator211receives the first digital data. The CDR circuit205reproduces the first clock signal from the first digital data. The frequency comparator210starts counting of a pulse of the second clock signal. The frequency comparator210counts a pulse of the second clock signal in the horizontal reading period T1.

When the horizontal reading period T1is completed, a blanking period T2is started. When the horizontal reading period T1is completed, the pixel unit101completes the output of the pixel signal. When the horizontal reading period T1is completed, the data generation circuit102generates the end code. The communicator108transmits the end code to the processor2a. After the end code is generated, the data generation circuit102is in a high impedance state.

The communicator211receives the end code. When the end code is received, the code detector212outputs the transmission start signal to the communicator211and outputs the end code to the frequency comparator210. The frequency comparator210stops counting of a pulse of the second clock signal. The frequency comparator210calculates the difference between the count value of the second clock signal and the estimation value and generates the third digital data on the basis of the difference. The frequency comparator210outputs the third digital data to the communicator211.

The communicator211starts transmission of the third digital data (clock control data CLK) on the basis of the transmission start signal. After the end code is received, the communication state of the processor2ais a transmission state. The communicator211transmits the third digital data in the blanking period T2.

The communicator108receives the third digital data in the blanking period T2. The code detector109outputs the third digital data to the memory105. The memory105holds the third digital data. The clock generation circuit106generates the first clock signal on the basis of the third digital data held in the memory105.

The code generation circuit213generates the start code at a predetermined timing. When the start code is generated, the communicator211completes transmission of the third digital data and transmits the start code to the scope1a.

The communicator108receives the start code. The code detector109detects the start code. When the start code is detected, a horizontal reading period T3is started. When the start code is detected, the signal generation circuit107generates a control signal for starting generation and transmission of the image data. The pixel unit101starts generation of the pixel signal on the basis of the control signal. The data generation circuit102starts generation of the first digital data on the basis of the control signal. The communicator108starts transmission of the first digital data on the basis of the control signal.

When the start code is output from the code generation circuit213, the frequency comparator210starts counting of a pulse of the second clock signal. An operation in the horizontal reading period T3is similar to the operation in the horizontal reading period T1. When the horizontal reading period T3is completed, a blanking period T4is started. An operation in the blanking period T4is similar to the operation in the blanking period T2.

The electronic endoscope system ES2executes an operation similar to the operation in each of the horizontal reading period T1and the blanking period T2until the frequency of the first clock signal and the frequency of the second clock signal match each other. InFIG. 7, an operation executed before the horizontal reading period T1is started is not shown. Before the horizontal reading period T1is started, an operation similar to the operation in each of the horizontal reading period T1and the blanking period T2is repeated.

An operation in a case in which the count value of the second clock signal obtained in the horizontal reading period T1matches the estimation value will be described. The frequency comparator210outputs the notification signal to the phase comparator206in the blanking period T2. The frequency comparator210generates the third digital data and outputs the third digital data to the communicator211. The communicator211transmits the third digital data to the scope1ain the blanking period T2. Since the frequency of the first clock signal and the frequency of the second clock signal are the same, generation and transmission of the third digital data may be omitted.

When the notification signal is output from the frequency comparator210, the phase comparator206waits in order to start comparison of phases. When the start code is output from the code generation circuit213, the phase comparator206starts comparing the phase of the first clock signal with the phase of the second clock signal. The phase comparator206generates the second digital data that represent the difference between the phase of the first clock signal and the phase of the second clock signal.

The communicator211receives the end code. When the end code is received, the code detector212outputs the transmission start signal to the communicator211and outputs the end code to the phase comparator206. The phase comparator206outputs the second digital data to the communicator211.

The communicator211starts transmission of the second digital data (clock control data CLK) on the basis of the transmission start signal. The communicator211transmits the second digital data to the scope1ain the blanking period T4.

The communicator108receives the second digital data in the blanking period T4. The code detector109outputs the second digital data to the memory105. The memory105holds the second digital data. The clock generation circuit106generates the first clock signal on the basis of the second digital data held in the memory105.

While the frequency comparator210counts a pulse of the second clock signal, the phase comparator206may stop its operation. While the phase comparator206compares the phase of the first clock signal with the phase of the second clock signal, the frequency comparator210may stop its operation.

The frequency comparator210and the phase comparator206may simultaneously operate. For example, the frequency comparator210starts counting of a pulse of the second clock signal and, at the same time, the phase comparator206starts comparing the phase of the first clock signal with the phase of the second clock signal. The phase comparator206keeps the output of the second digital data to the communicator211stopped until the notification signal is output from the frequency comparator210.

When the count value matches the estimation value, the frequency comparator210outputs the notification signal to the phase comparator206and stops the output of the third digital data to the communicator211. When the notification signal is output from the frequency comparator210and the end code is output from the code detector212, the phase comparator206outputs the second digital data to the communicator211. The communicator211transmits the second digital data to the scope1ain the blanking period. For example, when the count value of the second clock signal obtained in the horizontal reading period T1is the same as the estimation value, the communicator211transmits the second digital data to the scope1ain the blanking period T2.

In the above-described example, when the start code is output from the code generation circuit213, the frequency comparator210starts counting of a pulse of the second clock signal. Given the delay or the like in the cable3a, there is a possibility that a timing at which the start code is generated and a timing at which reception of the first digital data is started are not the same. The communicator108may transmit the start code to the processor2abefore transmitting the first digital data to the processor2a. The communicator211receives the start code transmitted by the communicator108. A data sequence including the start code is output to the code detector212. The code detector212detects the start code from the data sequence received by the communicator211. When the start code is detected by the code detector212, the frequency comparator210may start counting of a pulse of the second clock signal.

The frequency comparator210shown inFIG. 5is not essential. The clock generation circuit106may generate the first clock signal on the basis of only the second digital data generated by the phase comparator206.

The frequency comparator210may count a pulse of the first clock signal reproduced by the CDR circuit205. The frequency comparator210may calculate the difference between the count value of the first clock signal and the count value of the second clock signal and generate the third digital data.

In the second embodiment, the communicator108and the communicator211perform communication in a first direction in the horizontal reading period. The communicator108and the communicator211perform communication in a second direction in the blanking period. In case of wired communication, the number of signal lines connecting the scope1aand the processor2atogether is reduced. For this reason, the cable3becomes thin and the scope1ais miniaturized. In case of wireless communication, the number of communicators is reduced and the scope1ais miniaturized.

When generation of the image data is completed, the end code is transmitted from the scope1ato the processor2a. The processor2acan become aware of the start timing of the blanking period on the basis of the end code.

The start code is transmitted from the processor2ato the scope1aat a timing at which the blanking period is completed. The length of the blanking period is decided on the basis of the timing at which the start code is transmitted. The electronic endoscope system ES2can set a frame rate by adjusting the timing at which the start code is transmitted.

Since the frequency comparator210does not need to count a pulse of the first clock signal, the number of circuits using a high frequency signal is reduced. Consequently, the power consumption and the circuit scale are reduced.

Third Embodiment

FIG. 8shows a configuration of an electronic endoscope system ES3according to a third embodiment of the present invention. The same part as the part shown inFIG. 1will not be described.

The scope1shown inFIG. 1is changed to a scope1b. The scope1bincludes an imaging device10b, a transmitter103, and a receiver104. The imaging device10shown inFIG. 1is changed to the imaging device10b. The imaging device10bincludes a pixel unit101, a clock generation circuit106b, a signal generation circuit107, a phase comparator117, and a frequency comparator118. In the imaging device10b, the clock generation circuit106shown inFIG. 1is changed to the clock generation circuit106b. The imaging device10bdoes not include the data generation circuit102and the memory105shown inFIG. 1.

The processor2shown inFIG. 1is changed to a processor2b. The processor2bincludes a receiver201, an image processing circuit203, a clock generation circuit204b, a transmitter207, and a memory214. In the processor2b, the clock generation circuit204shown inFIG. 1is changed to the clock generation circuit204b. The processor2bdoes not include the S/P converter202, the CDR circuit205, the phase comparator206, and the frequency comparator210shown inFIG. 1.

The transmitter103(first communicator) transmits image data to the processor2bin a period excluding a blanking period. The phase comparator117compares the phase of a first clock signal with the phase of a second clock signal and generates digital phase data that represent the difference between the phase of the first clock signal and the phase of the second clock signal. The receiver201(second communicator) receives the image data transmitted from the scope1b. The clock generation circuit204bgenerates the second clock signal.

The transmitter207(second communicator) transmits the second clock signal to the scope1bin the blanking period. The receiver104(first communicator) receives the second clock signal transmitted from the processor2bin the blanking period. The transmitter103transmits the digital phase data to the processor2bin the blanking period. The receiver201receives the digital phase data transmitted from the scope1bin the blanking period. The clock generation circuit204bgenerates the second clock signal synchronized with the first clock signal on the basis of the digital phase data.

The frequency comparator118compares the frequency of the first clock signal with the frequency of the second clock signal and generates digital frequency data that represent the difference between the frequency of the first clock signal and the frequency of the second clock signal. The transmitter103transmits the digital frequency data to the processor2bin the blanking period. The receiver201receives the digital frequency data transmitted from the scope1bin the blanking period. The clock generation circuit204bgenerates the second clock signal having the same frequency as the frequency of the first clock signal by adjusting the frequency of the second clock signal on the basis of the digital frequency data.

The memory214holds the digital phase data and the digital frequency data received by the receiver201. The memory214outputs the digital phase data and the digital frequency data to the clock generation circuit204b.

The clock generation circuit106bincludes a configuration similar to the configuration of the clock generation circuit204shown inFIG. 1. For example, the clock generation circuit106bincludes a crystal oscillator and a PLL circuit. The clock generation circuit204bincludes a configuration similar to the configuration of the clock generation circuit106shown inFIG. 1. For example, the clock generation circuit204bincludes a DAC and a ring oscillator.

For example, after the frequency comparator118detects that the frequency of the first clock signal and the frequency of the second clock signal match each other, the phase comparator117compares the phase of the first clock signal with the phase of the second clock signal and generates the digital phase data. The clock generation circuit204badjusts the phase of the second clock signal on the basis of the digital phase data after adjusting the frequency of the second clock signal on the basis of the digital frequency data.

The second clock signal is generated on the basis of the digital phase data and the digital frequency data transmitted from the scope1b. For this reason, the electronic endoscope system ES3can generate the second clock signal synchronized with the first clock signal.