Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor memory devices and, more particularly, to techniques for providing a semiconductor memory device.

BACKGROUND OF THE DISCLOSURE

The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (e.g., double, triple gate, or surrounding gate), and Fin-FET devices.

A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating gate region wherein electrical charge may be stored. When excess majority electrical charges carriers are stored in the electrically floating gate region, the memory cell may store a logic high (e.g., binary “1” data state). When the electrical floating gate region is depleted of majority electrical charge carriers, the memory cell may store a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., a multiple gate device, a Fin-FET device, and a vertical pillar device).

There have been significant problems associated with conventional techniques for providing conventional semiconductor memory devices. For example, conventional semiconductor memory devices may have a channel length that may be susceptible to short-channel effects (SCE). Also, conventional semiconductor memory devices may experience interference between floating gates of adjacent memory cells. Further, conventional semiconductor memory devices may experience leakage of charge carriers stored in the memory cell due to memory cell noises and variations.

In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for providing a semiconductor memory device.

DETAILED DESCRIPTION OF EMBODIMENTS

Referring toFIG. 1, there is shown a block diagram of a semiconductor memory device10comprising a memory cell array20, data write and sense circuitry36, and memory cell selection and control circuitry38in accordance with an embodiment of the present disclosure. The memory cell array20may comprise a plurality of memory cells12each coupled to the memory cell selection and control circuitry38via a word line (WL)28and a carrier injection line (EP)34, and to the data write and sense circuitry36via a bit line (CN)30and a source line (EN)32. It may be appreciated that the bit line (CN)30and the source line (EN)32are designations used to distinguish between two signal lines and they may be used interchangeably.

The data write and sense circuitry36may read data from and may write data to selected memory cells12. In an embodiment, the data write and sense circuitry36may include a plurality of data sense amplifier circuits. Each data sense amplifier circuit may receive at least one bit line (CN)30and a current or voltage reference signal. For example, each data sense amplifier circuit may be a cross-coupled type sense amplifier to sense a data state stored in a memory cell12. The data write and sense circuitry36may include at least one multiplexer that may couple to a data sense amplifier circuit to at least one bit line (CN)30. In an embodiment, the multiplexer may couple a plurality of bit lines (CN)30to a data sense amplifier circuit.

Each data sense amplifier circuit may employ voltage and/or current sensing circuitry and/or techniques. In an embodiment, each data sense amplifier circuit may employ current sensing circuitry and/or techniques. For example, a current sense amplifier may compare current from a selected memory cell12to a reference current (e.g., the current of one or more reference cells). From that comparison, it may be determined whether the selected memory cell12stores a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). It may be appreciated by one having ordinary skill in the art that various types or forms of the data write and sense circuitry36(including one or more sense amplifiers, using voltage or current sensing techniques, to sense a data state stored in a memory cell12) may be employed to read data stored in the memory cells12.

The memory cell selection and control circuitry38may select and/or enable one or more predetermined memory cells12to facilitate reading data therefrom by applying control signals on one or more word lines (WL)28and/or carrier injection lines (EP)34. The memory cell selection and control circuitry38may generate such control signals from address signals, for example, row address signals. Moreover, the memory cell selection and control circuitry38may include a word line decoder and/or driver. For example, the memory cell selection and control circuitry38may include one or more different control/selection techniques (and circuitry thereof) to select and/or enable one or more predetermined memory cells12. Notably, all such control/selection techniques, and circuitry thereof, whether now known or later developed, are intended to fall within the scope of the present disclosure.

In an embodiment, the semiconductor memory device10may implement a two step write operation whereby all the memory cells12in a row of memory cells12may be written to a predetermined data state by first executing a “clear” or a logic low (e.g., binary “0” data state) write operation, whereby all of the memory cells12in the row of memory cells12are written to logic low (e.g., binary “0” data state). Thereafter, selected memory cells12in the row of memory cells12may be selectively written to the predetermined data state (e.g., a logic high (binary “1” data state)). The semiconductor memory device10may also implement a one step write operation whereby selected memory cells12in a row of memory cells12may be selectively written to either a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state) without first implementing a “clear” operation. The semiconductor memory device10may employ any of the writing, preparation, holding, refresh, and/or reading techniques described herein.

The memory cells12may comprise N-type, P-type and/or both types of transistors. Circuitry that is peripheral to the memory cell array20(for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may also include P-type and/or N-type transistors. Regardless of whether P-type or N-type transistors are employed in memory cells12in the memory cell array20, suitable voltage potentials (for example, positive or negative voltage potentials) for reading from the memory cells12will be described further herein.

Referring toFIG. 2, there is shown a top view of at least a portion of the memory cell array20shown inFIG. 1in accordance with an embodiment of the present disclosure. As illustrated in the top view, the memory cell array20may include a plurality of memory cells12arranged in a matrix of rows and columns including a plurality of word lines28(WL), a plurality of bit lines (CN)30, a source line plate (EN)32and/or a carrier injection line plate (EP)34. Each bit line (CN)30may extend in a first orientation along a first plane of the memory cell array20. The source line plate (EN)32may extend in the first orientation and a second orientation along a second plane of the memory cell array20. In an embodiment, the source line plate (EN)32may be formed of an N-type semiconductor material. The carrier injection line plate (EP)34may extend in the first orientation and the second orientation along a third plane of the memory cell array20. Each word line (WL)28may extend in the second orientation along a fourth plane of the memory cell array20. The first plane, the second plane, the third plane, and the fourth plane of the memory cell array20may be arranged in different planes parallel to each other.

The plurality of word lines (WL)28may be formed of a polycide material (e.g., a combination of a metal material and a silicon material), a metal material, and/or a combination of a polycide material and a metal material. In an embodiment, the word lines (WL)28may capacitively couple a voltage potential/current source of the memory cell selection and control circuitry38to the memory cells12. The word line (WL)28may be formed of a plurality layers. Each layer of the word line (WL)28may be formed of different materials. In an embodiment, the first layer of the word line (WL)28may be formed of a silicon material and the second layer of the word line (WL)28may be formed of a metal material.

The plurality of word lines (WL)28may comprise a plurality of gate lines. The plurality of gate lines may include a plurality of select gate (SG) lines234(not shown) and a plurality of control gate (CG) lines236(not shown). In an embodiment, the plurality of word lines (WL)28may comprise at least two select gate lines234a-b. The plurality of word lines (WL)28may comprise a predetermined number of control gate (CG) lines236(0-n). Each of the plurality of select gate (SG) lines234a-bmay be coupled to a corresponding select gate (SG) line contact226. Each of the plurality of control gate (CG) lines236(0-n) may be coupled to a corresponding control gate (CG) line contact228.

The plurality of control gate (CG) line contacts228(0-n) may be arranged between the plurality of select gate (SG) contacts234. The plurality of select gate (SG) line contacts226a-band the plurality of control gate (CG) line contacts228(0-n) may be arranged in the same plane. In an embodiment, the plurality select gate (SG) line contacts226and the plurality of control gate (CG) line contacts228may be arranged in the same plane as the bit line (CN)30. The plurality of select gate (SG) line contacts226and the plurality of control gate (CG) line contacts228may be arranged on a side portion of the memory cell array20.

Referring toFIG. 3, there are shown cross-sectional views of at least a portion of the memory cell array20as shown inFIG. 2in accordance with an embodiment of the present disclosure.FIG. 3illustrates a cross-sectional view of at least a portion of the memory cell array20along line A-A and a cross-sectional view of at least a portion of the memory cell array20along line B-B. The memory cells12of the memory cell array20may be implemented in a vertical configuration having various regions. For example, the memory cell12may comprise a source region320, a body region322, and a drain region324. The source region320, the body region322, and/or the drain region324may be disposed in a sequential contiguous relationship, and may extend vertically from a plane defined by a P+ region330and/or an N+ substrate332. The source region320of the memory cell12may be coupled to the source line (EN)32. The body region322may comprise a plurality of floating body regions14(0-n) and a plurality of corresponding floating gate regions302b(0-n) configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the plurality of word lines (WL)28. The drain region324of the memory cell12may be coupled to the bit line (CN)30.

The source region320of the memory cell12may be coupled to a corresponding source line (EN)32. In an embodiment, the source region320may be formed of a semiconductor material (e.g., silicon) comprising donor impurities. For example, the source region320may be formed of a silicon material doped with phosphorous or arsenic impurities. In an embodiment, the source region320may be formed of a silicon material doped with phosphorous or arsenic having a concentration of approximately 1020atoms/cm3or above. The source region320may comprise a plate having continuous planar region configured above the P+ region330and/or the N+ substrate332. The source region320may also comprise a plurality of protrusions formed on the continuous planar region of the plate. The plurality of protrusions of the source region320may be oriented in a column direction and/or a row direction of the memory cell array20. The plurality of protrusions of the source region320may form the base of the memory cell12.

In an embodiment, the source line (EN)32may be configured as the plate having continuous planar region of the source region320. In an embodiment, the source line (EN)32may be formed of an N+ doped silicon layer. In another embodiment, the source line (EN)32may be formed of a metal material. In other embodiments, the source line (EN)32may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). The source line (EN)32may couple a predetermined voltage potential to the memory cells12of the memory cell array20. For example, the source line (EN)32may be coupled to a plurality of memory cells12(e.g., a column or a row of memory cell array20).

The body region322of the memory cell12may be capacitively coupled to a corresponding word line (WL)28via the floating gate region302. In an embodiment, the body region322may be formed of undoped semiconductor material (e.g., intrinsic silicon). In another embodiment, the body region322may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the body region322may be formed of a silicon material doped with boron impurities. The body region322may be formed of a silicon material with acceptor impurities having a concentration of 1015atoms/cm3.

The body region322may comprise a plurality of floating body regions14(0-n) and a plurality of corresponding floating gate regions302b(0-n). For example, charge carriers may be accumulated/stored in the plurality of floating gate regions302b(0-n) corresponding to the plurality of floating body region14(0-n) in order to represent a data state (e.g., a logic low (e.g., binary “0” data state) and/or a logic high (e.g., binary “1” data state)). Each of the plurality of floating body regions14(0-n) may be capacitively coupled to a corresponding select gate (SG) line234or a corresponding control gate (CG) line236. In an embodiment, a first floating body region14(0) may be capacitively coupled to a corresponding first select gate (SG) line234a. The last floating body region14(n) may be capacitively coupled to a corresponding second select gate (SG) line234b. One or more intervening floating body regions14(1, . . . , n−1) may be capacitively coupled to a plurality of control gate (CG) lines236(0-n). The plurality of floating body regions14(0-n) may be accessible via the first select gate (SG) line234aand/or the second select gate (SG) line234b.

As discussed above, the plurality of word lines (WL)28may comprise a plurality of select gate (SG) line234and/or a plurality of control gate (CG) lines236(0-n). The plurality of select gate (SG) lines234and the plurality of control gate (CG) lines236(0-n) may be arranged in a sequential contiguous relationship extending from a vertical direction of the body region322. For example, the plurality of control gate (CG) lines236(0-n) may be arranged between the plurality of select gate (SG) lines234a-b. In an embodiment, the first select gate (SG) lines234amay be arranged contiguous to the source region320and the second select gate (SG) lines234bmay be arranged contiguous to the drain region324. The plurality of control gate (CG) lines236(0-n) may be arranged between the first select gate (SG) lines234aand the second select gate (SG) lines234b.

The plurality of select gate (SG) lines234may have different length in order to make contact with the plurality of select gate (SG) line contacts226. The length of the plurality of select gate (SG) lines234may be based at least in part on a location of the select gate (SG) lines234. For example, a first select gate (SG) line234may have a length shorter than a second select gate (SG) line234that is located below the first select gate (SG) line234. In an embodiment, the first select gate (SG) line234amay have a length longer than the second select gate (SG) line234b, when the first select gate (SG) line234ais located below the second select gate (SG) line234b. The plurality of control gate (CG) lines236(0-n) may have different length in order to make contact with the plurality of control gate (CG) line contact228(0-n). The length of the plurality of control gate (CG) lines236(0-n) may be based at least in part on a location of the control gate (CG) line236. For example, the length of the control gate (CG) lines236may increase as the control gate (CG) lines236are located closer to the source region320. In an embodiment, the first control gate (CG) line236(0) may have a length shorter than the second control gate (CG) line236(1). The second control gate (CG) line236(1) may have a length shorter than the third control gate (CG) line236(2), etc. Finally, the last control gate (CG) line236(n) may have the longest length of the plurality of control gate (CG) lines236.

The plurality of word lines (WL)28may be capacitively coupled to a plurality of memory cells12via the floating gate region302. The floating gate region302may comprise of two end portions302aand a middle portion302b. In an embodiment, the two end portions302aand the middle portion302bmay be formed of the same material. In another embodiment, different portions of the floating gate region302may be formed of different material. In an embodiment, the two end portions302aof the floating gate region302may be formed of an oxide and/or a thermal oxide material. The middle portion302bof the floating gate region302comprising a plurality of floating gate regions302b(0-n) may be formed of an oxide material, a thermal oxide material and/or a nitride material. For example, the middle portion302bof the floating gate region302may be formed of a nitride material embedded in an oxide material and/or a thermal oxide material. In an embodiment, the embedded nitride material of the middle portion302bof the floating gate region302may accumulate/store a predetermined amount of charge carriers in order to represent a data state (e.g., a logic low (e.g., binary “0” data state) and/or a logic high (e.g., binary “1” data state)). The two end portions302aof the floating gate region302may capacitively couple the plurality of select gate (SG) lines234to the body region322. The middle portion302bof the floating gate region302may capacitively couple the plurality of control gate (CG) lines236to the body region322.

The plurality of select gate (SG) lines234may be coupled to the plurality of select gate (SG) line contacts226and the plurality of control gate (CG) lines236may be coupled to the plurality of control gate (CG) line contacts228. The select gate (SG) line contacts226may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential and/or current to the select gate (SG) line234. The control gate (CG) line contacts228may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential and/or current to the control gate (CG) lines236. For example, the select gate (SG) line contacts226and the control gate (CG) line contact228may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof. The select gate (SG) line contacts226may have a height extending down to the select gate (SG) lines234. The control gate (CG) line contact228may have a height extending down to the control gate (CG) lines236.

The drain region324of the memory cell12may be coupled to a corresponding bit line (CN)30. In an embodiment, the drain region324of the memory cell12may be formed of a semiconductor material (e.g., silicon) comprising donor impurities. For example, the drain region324may be formed of a silicon material doped with phosphorous or arsenic impurities. In an embodiment, the drain region324may be formed of a silicon material doped with phosphorous or arsenic having a concentration of approximately 1020atoms/cm3or above.

The bit line (CN)30may be coupled to the drain region324of the memory cell12. The bit line (CN)30may be formed of a metal material. In another embodiment, the bit line (CN)30may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). In other embodiments, the bit line (CN)30may be formed of an N+ doped silicon layer. For example, the bit line (CN)30may be coupled to a plurality of memory cells12. The bit line (CN)30may be configured above the drain region324.

The bit line (CN)30may be connected to a plurality of memory cells12(e.g., a column of memory cells12) via a plurality of bit line contacts326. For example, each bit line contact326may correspond to a memory cell12along a column direction of the memory cell array20. Each bit line contact326may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential from the bit line (CN)30to the drain region324of the memory cell12. For example, the bit line contact326may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof. The bit line contact326may have a height extending from the bit line (CN)30to the drain region324of the memory cell12.

The p+ region330may be coupled to a corresponding carrier injection line plate (EP)34. In an embodiment, the P+ region330may be made of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the P+ region330may be made of a semiconductor material comprising boron impurities. In an embodiment, the P+ region330may be made of silicon comprising boron impurities having a concentration of approximately 1023atoms/cm3or above. Also, the P+ region330may be made in the form of a P-well region.

The carrier injection line plate (EP)34may be coupled to the P+ region330of the memory cell12. In an embodiment, the carrier injection line plate (EP)34may be formed of a P+ doped silicon layer. In another embodiment, the carrier injection line plate (EP)34may be formed of a metal material. In other embodiments, the carrier injection line plate (EP)34may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). For example, the carrier injection line plate (EP)34may be coupled to a plurality of memory cells12.

The N+ substrate332may be made of a semiconductor material (e.g., silicon) comprising donor impurities and may form a base of the memory cell array20. For example, the N+ substrate332may be made of a semiconductor material comprising phosphorous or arsenic impurities. In an embodiment, the N+ substrate332may be made of silicon comprising phosphorous or arsenic impurities having a concentration of approximately 1023atoms/cm3or above. In alternative embodiments, a plurality of N+ substrates332may form the base of the memory cell array20or a single N+ substrate330may form the base of the memory cell array20. Also, the N+ substrate332may be made in the form of an N-well substrate.

Referring toFIG. 4, there is shown voltage potential levels of various methods for performing a write operation and a read operation on a memory cell12as shown inFIGS. 1-3in accordance with an embodiment of the present disclosure. The write operation may include a write logic low (e.g., binary “0” data state) operation and a write logic high (e.g., binary “1” data state) operation. In an embodiment, the various methods of performing a write logic low (e.g., binary “0” data state) operation may be accomplished via an erase operation. In another embodiment, the various methods of performing a write logic high (e.g., binary “1” data state) operation may be accomplished via a program operation.

The erase operation may perform a write logic low (e.g., binary “0” data state) operation by depleting charge carriers (e.g., electrons) stored in the memory cell12. During the erase operation, a positive voltage potential may be applied to the N+ substrate332. In an embodiment, 1.0V may be applied to the N+ substrate332. The P+ region330may be coupled to an electrical ground (e.g., 0V). The plurality of bit lines (CN) may be decoupled from a voltage potential source and/or current source and may be electrical open or electrically floating. A negative voltage potential may be applied to the source region320. The negative voltage potential applied to the source region320may forward bias the junction between the source region320and the P+ region330. In an embodiment, the negative voltage potential applied to the source region320may be −1.0V. Simultaneously to or after forward biasing the junction between the source region320and the P+ region330, a plurality of negative voltage potentials may be applied to the plurality of word lines (WL)28(e.g., that may be capacitively coupled to the body region322). For example, different negative voltage potentials may be applied to the plurality of select gate (SG) lines234and the plurality of control gate (CG) lines236. In an embodiment, the negative voltage potentials applied to the plurality of select gate (SG) lines234may be −5.0V. The negative voltage potentials applied to the plurality of control gate (CG) lines236may be approximately −16.0V to −20.0V. The negative voltage potential applied to the plurality of word lines (WL)28may attract holes that are injected into the body region322via the forward biased junction between the source region320and the P+ region330. The attraction of the holes into the body region322may cause a removal of the electrons that may have accumulated/stored in the floating body region302b(e.g., the embedded nitride material) to represent that a logic low (e.g., binary “0” data state) may be written to the memory cell12.

The erase operation may perform a write logic low (e.g., binary “0” data state) operation by accumulate/store minority charge carriers (e.g., holes) in order to compensate for the majority charge carriers (e.g., electrons) that may have accumulated/stored in the memory cell12. During the erase operation, a positive voltage potential may be applied to the N+ substrate332. In an embodiment, 1.0V may be applied to the N+ substrate332. The P+ region330may be coupled to an electrical ground (e.g., 0V). The plurality of bit lines (CN) may be decoupled from a voltage potential source and/or current source and may be electrically open or electrically floating. A negative voltage potential may be applied to the source region320. The negative voltage potential applied to the source region320may forward bias the junction between the source region320and the P+ region330. In an embodiment, the negative voltage potential applied to the source region320may be −1.0V.

Simultaneously to or after forward bias the junction between the source region320and the P+ region330, a plurality of negative voltage potentials may be applied to the plurality of word lines (WL)28(e.g., that may be capacitively coupled to the body region322). For example, different negative voltage potentials may be applied to the plurality of select gate (SG) lines234and the plurality of control gate (CG) lines236. In an embodiment, the negative voltage potentials applied to the plurality of select gate (SG) lines234may be −5.0V. The negative voltage potentials applied to the plurality of control gate (CG) lines236may be approximately −16.0V to −20.0V.

Due to the forward biased junction between the P+ region330and the source region320and/or the negative voltage potentials applied to the plurality of word lines (WL)28, minority charge carriers (e.g., holes) may be injected into the body region322. The injection of the minority charge carriers (e.g., holes) into the body region322may cause an injection of minority charge carriers (e.g., holes) into the floating gate region302b(e.g., the embedded nitride material) to represent that a logic low (e.g., binary “0” data state) may be written to the memory cell12. A predetermined amount of minority charge carriers (e.g., holes) may be accumulated/stored in the floating gate region302bof the body region322of the memory cell12. The predetermined amount of minority charge carriers (e.g., holes) that may be accumulated/stored in the floating gate region302bof the body region322may outnumber the amount of majority charge carriers (e.g., electrons) that may be accumulated/stored in the floating gate region302bof the body region322. The predetermined amount of minority charge carriers (e.g., holes) accumulated/stored in the floating gate region302bof the body region322of the memory cell12may represent that a logic low (e.g., binary “0” data state) may be stored in the memory cell12.

The program operation may perform a write logic high (e.g., binary “1” data state) operation by accumulating/storing majority charge carriers (e.g., electrons) in the memory cell12. During the program operation, the N+ substrate332may be coupled to an electrical ground (e.g., 0V), the P+ region330may be coupled to an electrical ground (e.g., 0V), and/or the source region320may be coupled to an electrical ground (e.g., 0V). The junction between the P+ region330and the source region320may be reversed biased or weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage potential). A selected bit line (CN1)30may be coupled to an electrical ground (e.g., 0V), while a positive voltage potential may be applied to the unselected bit line (CN2)30. In an embodiment, the positive voltage potential applied to the unselected bit line (CN2)30may be 7.0V.

A positive voltage potential may be applied to the first select gate (SG) line234amay turn a select gate transistor (e.g., corresponding to the first floating body region14(0)) to an “ON” state to provide the majority charge carriers access to the floating body regions14(0-n). The second select gate (SG) line234bmay be coupled an electrical ground (e.g., 0V). For example, the grounded select gate (SG) line234bmay turn a select gate transistor (e.g., corresponding to the floating body region14(n)) to an “OFF” state to prevent inadvertent programming of the memory cell12via unselected bit lines (CN)30.

A positive voltage potential may be applied to the plurality of control gate (CG) lines236(0-n) that may be capacitively coupled to the plurality of floating body region14(1. . . n−1) of the body region322. The positive voltage potential applied to the selected control gate (CG1) line236(1) may be higher than the voltage potential applied to the unselected control gate (CG) lines236(0,2, . . . , n). For example, the positive voltage potential applied to the unselected control gate (CG) lines236(0,2, . . . , n) may be sufficient to invert a surface under the unselected control gate (CG) lines236(0,2, . . . , n) to provide a path for the majority charge carriers. In an embodiment, the positive voltage potential applied to the selected control gate (CG1) line236(1) may be approximately 16.0V to 20.0V and the positive voltage potential applied to the unselected control gate (CG) lines236(0,2, . . . , n) may be 7.0V. The majority charge carriers (e.g., electrons) may be attracted by the higher voltage potential applied to the selected control gate (CG) line236(1). The majority charge carriers (e.g., electrons) may flow from the drain region324to the floating body region14(2) that may be capacitively coupled to the selected control gate (CG) line236(1) via one or more floating body regions (e.g.,14(0) and14(1)) between the drain region324and the floating body region14(2). The predetermined amount of majority charge carriers (e.g., electrons) tunneled and stored in the selected floating gate region302b(1) (e.g., the embedded nitride region) of the selected floating body region14(2) of the body region322may represent that a logic high (e.g., binary “1” data state) is stored in the memory cell12.

A read operation may be performed to read a data state (e.g., a logic low (e.g., binary “0” data state) and/or a logic high (e.g., binary “1” data state)) stored in the memory cell12. During a read operation, the N+ substrate332may be coupled an electrically ground (e.g., 0V), the P+ region330may be coupled to an electrical ground (e.g., 0V), and the source region320may be coupled to an electrical ground (e.g., 0V). A positive voltage potential may be applied to the drain region324of the memory cell12via the bit line (CN)30. In an embodiment, the positive voltage potential applied to the drain region324may be 1.0V. A positive voltage potential may be applied to the plurality of select gate (SG) lines234a-b. In an embodiment, the positive voltage potential applied to the plurality of select gate (SG) lines234a-bmay be 5.0V. The positive voltage potential applied to the plurality of select gate (SG) lines234a-bmay enable the performance of a read operation of a plurality of floating body regions14capacitively coupled to the plurality of control gate (CG) lines236(0-n).

A positive voltage potential may be applied to a plurality of unselected control gate (CG) lines236(0,2, . . . , n). In an embodiment, the positive voltage potential applied to the plurality of unselected control gate (CG) lines236(0,2, . . . , n) may be 5.0V. The positive voltage potential applied to the plurality of unselected control gate (CG) lines236(0,2, . . . , n) may be sufficient to invert a surface of the floating body regions14that may be capacitively coupled to the plurality of unselected control gate (CG) lines236(0,2, . . . , n) and the drain region324. A selected control gate (CG) line236(1) may be coupled to an electrical ground (e.g., 0V). Under such biasing, the surface of the floating body region14(2) may be inverted when a small amount of or no majority charge carriers are stored in the floating gate region302b. Also, under such biasing, the surface of the floating body region14(2) may not be inverted when a predetermined amount of majority charge carriers are stored in the floating gate region302b. The majority charge carriers (e.g., electrons) may flow from the selected floating body region14(2) to the drain region324. In an embodiment, when a logic high (e.g., binary “1” data state) is stored in the memory cell12, no voltage potential and/or current may be detected at the drain region324. In another embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell12, a predetermined amount of voltage potential and/or current may be detected at the drain region324.

Referring toFIG. 5, there is shown a top view of at least a portion of the memory cell array20as shown inFIG. 1in accordance with an alternate embodiment of the present disclosure. The at least a portion of the memory cell array20as shown inFIG. 5is similar to the at least a portion of the memory cell array20as shown inFIG. 2, except that the memory cells12may be implemented in a horizontal configuration. As illustrated in the top view, the memory cell array20may include a plurality of memory cells12arranged in a matrix of rows and columns including a plurality of word lines (WL), a plurality of bit lines (CN)30, and/or a source line plate (EN)32. Each bit line (CN)30may extend in a first orientation along a plurality of planes of the memory cell array20. The source line strip (EN)32may extend in a second orientation along a second plane of the memory cell array20. Each word line (WL)28may extend in the second orientation along a third plane of the memory cell array20. The plurality of planes, the second plane, and the third plane of the memory cell array20may be arranged in different planes parallel to each other.

The plurality of word lines (WL)28may be formed of a polycide material (e.g., a combination of a metal material and a silicon material), a metal material, and/or a combination of a polycide material and a metal material. In an embodiment, the word lines (WL)28may capacitively couple a voltage potential/current source of the memory cell selection and control circuitry38to the memory cells12. The word line (WL)28may be formed of a plurality layers. Each layer of the word line (WL)28may be formed of different materials. In an embodiment, the first layer of the word line (WL)28may be formed of a silicon material and the second layer of the word line (WL)28may be formed of a metal material.

The plurality of word lines (WL)28may comprise a plurality of gate lines. The plurality of gate lines may include a plurality of select gate (SG) lines234(not shown) and a plurality of control gate (CG) lines236(not shown). In an embodiment, the plurality of word lines (WL)28may comprise at least two select gate lines234a-b. The plurality of word lines (WL)28may also comprise a predetermined number of control gate (CG) lines236(0-n). Each of the plurality of select gate (SG) lines234a-bmay be coupled to a corresponding select gate (SG) line contact226. Each of the plurality of control gate (CG) lines236(0-n) may be coupled to a corresponding control gate (CG) line contact228(0-n).

The plurality of control gate (CG) line contacts228(0-n) may be arranged between the plurality of select gate (SG) contacts226a-b. The plurality of select gate (SG) line contacts226a-band the plurality of control gate (CG) line contacts228(0-n) may be arranged in the same plane. The plurality of select gate (SG) line contacts226and the plurality of control gate (CG) line contacts228may be arranged above the memory cell array20.

Referring toFIG. 6, there is shown a cross-sectional view along line A-A of at least a portion of the memory cell array20as shown inFIG. 5in accordance with an embodiment of the present disclosure. The memory cells12of the memory cell array20may be implemented in a horizontal configuration having various regions. For example, the memory cell12may comprise a source region320, a body region322, and a drain region324. The source region320, the body region322, and/or the drain region324may be disposed in a sequential contiguous relationship, and may extend horizontally from a plane defined by a bit line (CN)30. The source region320of the memory cell12may be coupled to the source line (EN)32. The body region322may be an electrically floating body region of the memory cell12configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the plurality of word lines (WL)28. The drain region324of the memory cell12may be coupled to the bit line (CN)30.

The source region320of the memory cell12may be coupled to a corresponding source line (EN)32. In an embodiment, the source region320may be formed of a semiconductor material (e.g., silicon) comprising donor impurities. For example, the source region320may be formed of a silicon material doped with phosphorous or arsenic impurities. In an embodiment, the source region320may be formed of a silicon material doped with phosphorous or arsenic having a concentration of approximately 1020atoms/cm3or above.

In an embodiment, the source line (EN)32may be formed of an doped silicon layer. In another embodiment, the source line (EN)32may be formed of a metal material. In other embodiments, the source line (EN)32may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). The source line (EN)32may couple a predetermined voltage potential to the memory cells12of the memory cell array20. For example, the source line (EN)32may be coupled to a plurality of memory cells12(e.g., a column or a row of memory cell array20).

The source line (EN)32may be coupled to a plurality columns of memory cells12of the memory cell array20via a plurality of source line (EN) contacts334a-b. In an embodiment, the source line (EN)32may be coupled to the source regions320of the plurality columns of memory cells12of the memory cell array20via the plurality of source line (EN) contacts334a-b. The source line (EN)32may include a plurality of source line (EN) contacts334a-b. Each of the source line (EN) contacts334a-bmay be coupled to a disparate column of memory cells12of the memory cell array20. The source line (EN)32may be coupled to two contiguous columns of memory cells12of the memory cell array20via the plurality of source line (EN) contacts334a-b. For example, the first source line (EN) contact334amay be coupled to the source region320of the first column of memory cells12of the memory cell array20. The second source line (EN) contact334bmay be coupled to the source region324of the second column of memory cells12of the memory cell array20. The plurality of source line (EN) contacts334a-bmay have a height extending from the source line (EN)32to the plurality of source regions320of the memory cells12in a column of the memory cell array20.

The plurality of source line (EN) contacts334a-bmay be formed of a metal layer or a polysilicon layer in order to couple a voltage potential from the source line (EN)32to the source region320of the memory cell12. For example, the plurality of source line (EN) contacts334a-bmay be formed of tungsten, titanium, titanium nitride, polysilicon or combination thereof.

The body region322of the memory cell12may be capacitively coupled to a corresponding word line (WL)28. In an embodiment, the body region322may be formed of undoped semiconductor material (e.g., intrinsic silicon). In another embodiment, the body region322may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the body region322may be formed of a silicon material doped with boron impurities. The body region322may be formed of a silicon material with acceptor impurities having a concentration of 1015atoms/cm3.

The body region322may comprise a plurality of floating body regions14(0-n) and a plurality of corresponding floating gate regions302b(0-n). For example, charge carriers may be accumulated/stored in the plurality of floating gate regions302b(0-n) corresponding to the plurality of floating body region14(0-n) in order to represent a data state (e.g., a logic low (e.g., binary “0” data state) and/or a logic high (e.g., binary “1” data state)). Each of the plurality of floating body regions14(0-n) may be capacitively coupled to a corresponding select gate (SG) line234or a corresponding control gate (CG) line236. In an embodiment, a first floating body region14(0) may be capacitively coupled to a corresponding first select gate (SG) line234a. The last floating body region14(n) may be capacitively coupled to a corresponding second select gate (SG) line234b. One or more intervening floating body region14(1, . . . , n−1) may be capacitively coupled to the plurality of control gate (CG) lines236(0-n). The plurality of floating body regions14(0-n) may be accessible via the first select gate (SG) line234aand/or the second select gate (SG) line234b.

As discussed above, the plurality of word lines (WL)28may comprise a plurality of select gate (SG) lines234and/or a plurality of control gate (CG) lines236. The plurality of select gate (SG) lines234and the plurality of control gate (CG) lines236may be arranged in a sequential contiguous relationship extending in a vertical direction of the body region322. The plurality of select gate (SG) lines234and the plurality of control gate (CG) lines236may be capacitively coupled to a plurality of floating body regions14in the column direction of the memory cell array20. For example, the plurality of control gate (CG) lines236(0-n) may be arranged between the plurality of select gate (SG) lines234a-b. In an embodiment, the first select gate (SG) lines234amay be arranged contiguous to the source region320and the second select gate (SG) lines234bmay be arranged contiguous to the drain region324. The plurality of control gate (CG) lines236(0-n) may be arranged between the first select gate (SG) lines234aand the second select gate (SG) lines234b.

The plurality of select gate (SG) lines234may be coupled to the plurality of select gate (SG) line contacts226and the plurality of control gate (CG) lines236may be coupled to the plurality of control gate (CG) line contacts228. The select gate (SG) line contacts226may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential and/or current to the select gate (SG) lines234. The control gate (CG) line contacts228may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential and/or current to the control gate (CG) lines236. For example, the select gate (SG) line contacts226and the control gate (CG) line contact228may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof. The select gate (SG) line contacts226may have a height extending down to the select gate (SG) lines234. The control gate (CG) line contact228may have a height extending down to the control gate (CG) lines236.

A plurality of select gate (SG) line contacts226may be coupled to each other in order to simultaneously access a plurality of memory cells12. For example, a plurality of first select gate (SG) line contacts226amay be coupled to each other via a select gate (SG) coupling contact328. In another embodiment, a plurality of second select gate (SG) line contacts226bmay be coupled to each other via the select gate (SG) coupling contact328. The select gate (SG) coupling contact328may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof.

The drain region324of the memory cell12may be coupled to a corresponding bit line (CN)30. In an embodiment, the drain region324of the memory cell12may be formed of a semiconductor material (e.g., silicon) comprising donor impurities. For example, the drain region324may be formed of a silicon material doped with phosphorous or arsenic impurities. In an embodiment, the drain region324may be formed of a silicon material doped with phosphorous or arsenic having a concentration of approximately 102° atoms/cm3or above.

The bit line (CN)30may be coupled to the drain region324of the memory cell12. The bit line (CN)30may be formed of a metal material. In another embodiment, the bit line (CN)30may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). In other embodiments, the bit line (CN)30may be formed of an N+ doped silicon layer. For example, the bit line (CN)30may be coupled to a plurality of memory cells12. The bit line (CN)30may be configured on one or more side portions of the drain region324.

The plurality of bit lines (CN)30may have different length in order to make contact with the plurality of bit line (CN) contacts326. The length of the plurality of bit lines (CN)30may be based at least in part on a location of the bit lines (CN)30. For example, a first bit line (CN) line30may have a length shorter than a second bit line (CN)30that is located below the first bit line (CN)30. In an embodiment, the first bit line (CN)30may have a length shorter than the second bit line30. The second bit line (CN)30may have a length shorter than the third bit line30, etc. Finally, the last bit line (CN)30may have the longest length of the plurality of bit lines (CN)30.

The plurality of bit line (CN) contacts326may have different lengths in order to couple to the plurality of bit line (CN). The plurality of bit line (CN) contacts326may have a length based at least in part on the length of the bit line (CN)30. For example, a shorter bit line (CN) contact326may be coupled to a short bit line (CN)30, while a longer bit line (CN) contact326may be coupled to a longer bit line (CN)30. In an embodiment, the shortest bit line (CN) contact326may be coupled to the shortest bit line (CN)30and the longest bit line (CN) contact326may be coupled to the longest bit line (CN)30. Each bit line contact326may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential from the bit line (CN)30to the drain region324of the memory cell12. For example, the bit line contact326may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof. The bit line contact326may have a height extending from the bit line (CN)30to the drain region324of the memory cell12.

An insulating or dielectric layer336may be disposed between the plurality of bit lines (CN)30. The insulating or dielectric layer336may provide an electrical insulation between adjacent bit lines (CN)30. For example, the insulating or dielectric layer336may be formed from an oxide layer or a thermal oxide layer. The insulating or dielectric layer336may have a predetermined thickness in order to electrically insulating adjacent bit lines (CN)30.

In an embodiment, the P+ region330may be made of a semiconductor material (e.g., silicon) comprising acceptor impurities and may be disposed between two contiguous columns of memory cells12. For example, the P+ region330may be made of a semiconductor material comprising acceptor impurities. In an embodiment, the P+ region330may be made of silicon comprising boron impurities having a concentration of approximately 1020atoms/cm3or above. The P+ region330may be disposed between two contiguous columns of memory cells12and may be shared between the two contiguous columns of memory cells12. The P+ region330may be formed of an elongated strip region to be shared between two contiguous columns of memory cells12. In an embodiment, the P+ region330may provide minority charge carriers (e.g., holes) to the two contiguous columns of memory cells12during one or more operations. The P+ region330may be also disposed between the plurality of source line (EN) contacts334a-b.

Referring toFIG. 7, there is shown a cross-sectional view along line B-B of at least a portion of the memory cell array20as shown inFIG. 5in accordance with an embodiment of the present disclosure. As discussed above, a plurality of bit lines (CN(0-n))30may be coupled to a plurality of memory cells (e.g., a row of memory cell array20). The oxide layer336may form the base of the memory cell array20. In an embodiment, a plurality of oxide layer336may form the base of the memory cell array20. In another embodiment, a single oxide layer336may form the base of the memory cell array20. The oxide layer336may be disposed between the plurality of bit line (CN(0-n))30.

The word line (WL)28may be capacitively coupled to the body region322of the memory cell12via a floating gate region302. The floating gate region302may be formed above the plurality of bit lines (CN(0-n))30. In an embodiment, the floating gate region302may cover the plurality of bit lines (CN(0-n))30and the oxide layer336disposed between the plurality of bit lines (CN(0-n))30. The floating gate region302may comprise a plurality of layers formed of different material. In an embodiment, the floating gate region302may comprise a first layer302aand a second layer302bformed of different material. The first layer302aof the floating gate region302may be formed of an oxide material and/or a thermal oxide material. The second layer302bof the floating gate region302may be formed of a nitride material. The first layer302aof the floating gate region302may overlap and cover the second layer302bof the floating gate region302.

The plurality of word lines (WL)28may comprise a plurality of layers. For example, the word line (WL)28may comprise two layers formed of different material. In an embodiment, the first layer28aof the word line (WL)28may be formed of a polysilicon material. The second layer28bof the word line (WL)28may be formed of a metal material. The first layer28aof the word line (WL)28may overlap and cover the floating body region302and the second layer28bof the word line (WL)28may be disposed above the first layer28aof the word line (WL)28.

Referring toFIG. 8, there is shown a top view of at least a portion of the memory cell array20shown inFIG. 1in accordance with an alternate embodiment of the present disclosure. The at least a portion of the memory cell array20as shown inFIG. 8may be similar to the at least a portion of the memory cell array20as shown inFIG. 2, except that the source line plate (EN)32may be formed of P-type semiconductor material.

Referring toFIG. 9, there are shown cross-sectional views of at least a portion of the memory cell array20as shown inFIG. 8in accordance with an embodiment of the present disclosure.FIG. 9illustrates a cross-sectional view of at least a portion of the memory cell array20along line A-A and a cross-sectional view of at least a portion of the memory cell array20along line B-B. The sectional views as shown inFIG. 9may be similar to the sectional views as shown inFIG. 3, except that the source region320may be made of P-type semiconductor material. The source region320of the memory cell12may be coupled to a corresponding source line (EN)32. In an embodiment, the source region320may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the source region320may be formed of a silicon material doped with boron impurities. In an embodiment, the source region320may be formed of a silicon material doped with boron having a concentration of approximately 1020atoms/cm3or above. The source region320may comprise a plate having continuous planar region configured above the P+ region330and/or the N+ substrate332. The source region320may also comprise a plurality of protrusions formed on the continuous planar region of the plate. The plurality of protrusions of the source region320may be oriented in a column direction and/or a row direction of the memory cell array20. The plurality of protrusions of the source region320may form the base of the memory cell12.

Referring toFIG. 10, there is shown voltage potential levels of various methods for performing a write operation and a read operation on a memory cell12as shown inFIGS. 7-9in accordance with an embodiment of the present disclosure. The write operation may include a write logic low (e.g., binary “0” data state) operation and a write logic high (e.g., binary “1” data state) operation. In an embodiment, the various methods of performing a write logic low (e.g., binary “0” data state) operation may be accomplished via an erase operation. In another embodiment, the various methods of performing a write logic high (e.g., binary “1” data state) operation may be accomplished via a program operation.

The erase operation may perform a write logic low (e.g., binary “0” data state) operation by accumulate/store minority charge carriers (e.g., holes) in order to compensate for the majority charge carriers (e.g., electrons) that may have accumulated/stored in the memory cell12. During the erase operation, a positive voltage potential may be applied to the N+ substrate332. In an embodiment, 1.0V may be applied the N+ substrate332. A positive voltage potential may be applied to the P+ region330and the source region320. The same positive voltage potentials may be applied to the P+ region330and the source region320. In an embodiment, the positive voltage potential applied to the P+ region330and the source region320may be 1.0V. The plurality of bit lines (CN)30may be decoupled from a voltage potential source and/or current source and may be electrical open or electrically floating.

A plurality of negative voltage potentials may be applied to the plurality of select gate (SG) lines234(e.g., that may be capacitively coupled to plurality floating body regions14of the body region322). The negative voltage potential applied to the select gate (SG) lines234bmay forward bias the junction between the source region320and the floating body region14(n) of the body region322. In an embodiment, the plurality of negative voltage potentials applied to the select gate (SG) lines234may be −5.0V. Simultaneously to or after forward biasing the junction between the floating body region14(n) and the source region320, a plurality of negative voltage potentials may be applied to the plurality of control gate (CG) lines236(e.g., that may be capacitively coupled to the plurality of floating body regions14of the body region322). In an embodiment, the negative voltage potentials applied to the plurality of control gate (CG) lines236may be approximately −16.0V to −20.0V. The negative voltage potential applied to the plurality of word lines (WL)28may attract minority charge carriers (e.g., holes) to accumulate/store in the body region322via the forward biased junction between the source region320and floating body region14(n) of the body region322. A predetermined amount of minority charge carriers (e.g., holes) that may be tunneled into the floating gate region302bor a predetermined amount of majority charge carriers (e.g., electrons) may be tunneled back into the body region322. The predetermine amount of minority charge carriers (e.g., holes) accumulated/stored in the floating gate region302bof the memory cell12may represent that a logic low (e.g., binary “0” data state) may be stored in the memory cell12.

The program operation may perform a write logic high (e.g., binary “1” data state) operation by accumulating/storing majority charge carriers (e.g., electrons) in the memory cell12. During the program operation, the N+ substrate332may be coupled to an electrical ground (e.g., 0V), the P+ region330may be coupled to an electrical ground (e.g., 0V), and/or the source region320may be coupled to an electrical ground (e.g., 0V). The junction between the P+ region330and the source region320may be reversed biased or weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage potential). A selected bit line (CN1)30may be coupled to an electrical ground (e.g., 0V), while a positive voltage potential may be applied to the unselected bit line (CN2)30. In an embodiment, the positive voltage potential applied to the unselected bit line (CN2)30may be 5.0V (e.g., Vdd).

A positive voltage potential may be applied to the first select gate (SG) line234athat may be capacitively coupled to the first floating body region14(0) of the body region322. Also, a positive voltage potential may be applied to the second select gate (SG) lines234bthat may be capacitively coupled to the last floating body region14(n) of the body region322. In an embodiment, the positive voltage potential applied to the first select gate (SG) line234amay be approximately 5.0V. In another embodiment, the positive voltage potential applied to the second select gate (SG) line234bmay be approximately 5.0V. The positive voltage potential applied to the first select gate (SG) line234amay turn a select gate transistor (e.g., corresponding to the first floating body region14(0)) to an “ON” state to couple the drain region324to the floating body regions14(0-n). The positive voltage potential applied to the second select gate (SG) line234bmay turn a select gate transistor (e.g., corresponding to the floating body region14(n)) to an “OFF” state to decouple the source region320. A predetermined amount of majority charge carrier (e.g., electrons) may be injected into the first floating body region14(0) of the body region322.

A positive voltage potential may be applied to the plurality of control gate (CG) lines236(0-n) that may be capacitively coupled to the plurality of floating body region14(1, . . . , n−1) of the body region322. The positive voltage potential applied to the selected control gate (CG1) line236(1) may be higher than the voltage potential applied to the unselected control gate (CG) lines236(0,2, . . . , n). In an embodiment, the positive voltage potential applied to the selected control gate (CG1) line236(1) may be approximately 16.0V to 20.0V and the positive voltage potential applied to the unselected control gate (CG) lines236(0,2, . . . , n) may be 7.0V. The majority charge carriers (e.g., electrons) may be attracted by the higher voltage potential applied to the selected control gate (CG) line236(1). The majority charge carriers (e.g., electrons) may flow from the drain region324to the floating body region14(2) that may be capacitively coupled to the selected control gate (CG) line236(1) via one or more floating body regions (e.g.,14(0) and14(1)) between the drain region324and the floating body region14(2). The predetermined amount of majority charge carriers (e.g., electrons) tunneled from the selected floating body region14(2) into the floating gate region302bmay represent that a logic high (e.g., binary “1” data state) is stored in the memory cell12.

A read operation may be performed to read a data state (e.g., a logic low (e.g., binary “0” data state) and/or a logic high (e.g., binary “1” data state)) stored in the memory cell12. During a read operation, a plurality of positive voltage potentials may be applied to the N+ substrate332, the P+ region330, and/or the source region320. In an embodiment, the positive voltage potential applied to the N+ substrate332may be 1.0V, the positive voltage potential applied to the P+ region330may be 1.0V, and the positive voltage potential applied to the source region320may be 1.0V. The drain region324may be coupled to an electrical ground (e.g., 0V) via the bit line (CN)30. A positive voltage potential may be applied to the plurality of select gate (SG) lines234a-b. In an embodiment, the positive voltage potential applied to the plurality of select gate (SG) lines234a-bmay be 5.0V. The positive voltage potential applied to the plurality of select gate (SG) lines234a-bmay enable the performance of a read operation of a plurality of floating body regions14that may be capacitively coupled to the plurality of control gate (CG) lines236(0-n).

A positive voltage potential may be applied to a plurality of unselected control gate (CG) lines236(0,2, . . . , n). In an embodiment, the positive voltage potential applied to the plurality of unselected control gate (CG) lines236(0,2, . . . , n) may be 5.0V. The positive voltage potential applied to the plurality of unselected control gate (CG) lines236(0,2, . . . , n) may invert a surface of floating body regions14that may be capacitively coupled to the plurality of unselected control gate (CG) lines236(0,2, . . . , n). A selected control gate (CG) line236(1) may be coupled to an electrical ground (e.g., 0V). Under such biasing, the selected floating body region14(2) that may be capacitively coupled to the selected control gate (CG) line236(1) may turn to an “ON” state based at least in part on an amount of charge carriers stored in the floating gate region302b. The majority charge carriers (e.g., electrons) may flow through the selected floating body region14(2) from the drain region324. Similar, the minority charge carriers (e.g., holes) may flow through the selected floating body region14(2) from the source region320. In an embodiment, when a logic high (e.g., binary “1” data state) is stored in the memory cell12, no voltage potential and/or current may be detected at the drain region324. In another embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell12, a predetermined amount of voltage potential and/or current may be detected at the drain region324.

Referring toFIG. 11, there is shown a top view of at least a portion of the memory cell array20as shown inFIG. 1in accordance with an alternate embodiment of the present disclosure. The at least a portion of the memory cell array20as shown inFIG. 11is similar to the at least a portion of the memory cell array20as shown inFIG. 5, except that the source region320may be formed of a P-type semiconductor material. Also, the P+ region330as shown inFIG. 5, may be eliminated because the source region320may be formed of a P-type semiconductor material. The source region320may be disposed between adjacent columns of memory cells12of the memory cell array20. In an embodiment, the source region320may be disposed between two contiguous columns of memory cells12of the memory cell array20. The single source region320disposed between two contiguous columns of memory cells12may be the source region320for the memory cells12of the two contiguous columns of the memory cell array20.

Referring toFIG. 12, there is shown a cross-sectional view along line A-A of at least a portion of the memory cell array20as shown inFIG. 11in accordance with an embodiment of the present disclosure. The cross-sectional view as shown inFIG. 12may be similar to the cross-sectional view as shown inFIG. 6, except that the source region320may be made from a P-type semiconductor material. The source region320of the memory cell12may be coupled to a corresponding source line (EN)32. In an embodiment, the source region320may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the source region320may be formed of a silicon material doped with boron impurities. In an embodiment, the source region320may be formed of a silicon material doped with boron having a concentration of approximately 1020atoms/cm3or above.

In an embodiment, the source line (EN)32may be formed of a metal material. In another embodiment, the source line (EN) may be formed of a P+ doped silicon layer. In other embodiments, the source line (EN)32may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). The source line (EN)32may couple a predetermined voltage potential to the memory cells12of the memory cell array20. For example, the source line (EN)32may be coupled to a plurality of memory cells12(e.g., a column or a row of memory cell array20). The source region320may be formed of an elongated strip region to be shared between two contiguous columns of memory cells12. In an embodiment, the source region320may provide minority charge carriers (e.g., holes) to the two contiguous columns of memory cells12during one or more operations.

The source line (EN)32may be coupled to a plurality columns of memory cells12of the memory cell array20via a source line (EN) contact334. In an embodiment, the source line (EN)32may be coupled to the source regions320of the plurality columns of memory cells12of the memory cell array20via the source line (EN) contact334. The source line (EN) contact334may be coupled to a plurality columns of memory cells12of the memory cell array20. The source line (EN)32may be coupled to the two contiguous columns of memory cells12of the memory cell array20via the source line (EN) contact334. The source line (EN) contact334may have a height extending from the source line (EN)32to the plurality of source regions320of the memory cells12in a column of the memory cell array20.

The source line (EN) contact334may be formed of a metal layer or a polysilicon layer in order to couple a voltage potential from the source line (EN)32to the source region320of the memory cell12. For example, the source line (EN) contact334may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof.

Referring toFIG. 13, there is shown a cross-sectional view along line B-B of at least a portion of the memory cell array20as shown inFIG. 11in accordance with an embodiment of the present disclosure. The cross-sectional view as shown inFIG. 13, may be similar to the cross-sectional view as shown inFIG. 7, except that the source region320may be formed of a P-type semiconductor material.

At this point should be noted that techniques for providing a semiconductor memory device in accordance with the present disclosure as described above may involve the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, specific electronic components may be employed in a semiconductor memory device or similar or related circuitry for implementing the functions associated with providing a semiconductor memory device in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with providing a semiconductor memory device in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more non-transitory processor readable media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves.

The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of at least one particular implementation in at least one particular environment for at least one particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.