Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines

Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor memory devices and, more particularly, to techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines.

BACKGROUND OF THE DISCLOSURE

The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Semiconductor-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET devices.

A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein which electrical charges may be stored. The electrical charges stored in the electrically floating body region may represent a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated with semiconductor-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., multiple gate devices, Fin-FETs, recessed gates and pillars).

In one conventional technique, the memory cell of the semiconductor memory device may be read by applying a bias to a drain region of the memory transistor, as well as a bias to a gate of the memory transistor that is above a threshold voltage potential of the memory transistor. As such, a conventional reading technique may involve sensing an amount of current provided/generated by/in the electrically floating body region in response to the application of the drain region bias and the gate bias to determine a state of the memory cell. For example, the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state).

In another conventional technique, the memory cell of the semiconductor memory device may be written to by applying a bias to the memory transistor. As such, a conventional writing technique may result in an increase/decrease of majority charge carriers in the electrically floating body region of the memory cell. Such an excess of majority charge carriers may result from channel impact ionization, band-to-band tunneling (gate-induced drain leakage “GIDL”), or direct injection. Majority charge carriers may be removed via drain region hole removal, source region hole removal, or drain and source region hole removal, for example, using back gate pulsing.

Often, conventional reading and/or writing operations may lead to relatively large power consumption and large voltage potential swings which may cause disturbance to unselected memory cells in the semiconductor memory device. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of majority charge carriers in the electrically floating body region of the memory cell in the semiconductor memory device, which, in turn, may result in an inaccurate determination of the state of the memory cell. Furthermore, in the event that a bias is applied to the gate of the memory transistor that is below a threshold voltage potential of the memory transistor, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate as a result of the applied bias. As a result, the net quantity of majority charge carriers in the electrically floating body region may be reduced. This phenomenon, which is typically characterized as charge pumping, is problematic because the net quantity of majority charge carriers may be reduced in the electrically floating body region of the memory cell, which, in turn, may result in an inaccurate determination of the state of the memory cell.

In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for fabricating and/or operating semiconductor memory devices.

SUMMARY OF THE DISCLOSURE

Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus comprising a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.

In accordance with other aspects of the particular exemplary embodiment, the first region, the body region, and the second region may form a first bipolar transistor.

In accordance with further aspects of this particular exemplary embodiment, the body region, the second region, and the third region may form a second bipolar transistor.

In accordance with additional aspects of this particular exemplary embodiment, the carrier injection line may contact the third region.

In accordance with additional aspects of this particular exemplary embodiment, the constant voltage source may apply a positive bias to the third region via the carrier injection line.

In accordance with yet another aspect of this particular exemplary embodiment, the constant voltage source may apply 0V or a negative bias to the third region via the carrier injection line.

In accordance with other aspects of the particular exemplary embodiment, the constant voltage source may be coupled to a plurality of the carrier injection lines.

In accordance with further aspects of this particular exemplary embodiment, the bit line may extend from the first region perpendicular to at least one of the source line, the word line, and the carrier injection line.

In accordance with additional aspects of this particular exemplary embodiment, the word line may extend from near the body region horizontally parallel to the carrier injection line.

In accordance with yet another aspect of this particular exemplary embodiment, the source line may extend from the second region horizontally parallel to at least one of the word line and the carrier injection line.

In accordance with other aspects of the particular exemplary embodiment, the apparatus may further comprise a fourth region disposed between the third region and a substrate.

In accordance with further aspects of this particular exemplary embodiment, the fourth region may be N-doped region and the substrate is a P-type substrate.

In accordance with additional aspects of this particular exemplary embodiment, the first region and the second region may be N-doped regions.

In accordance with yet another aspect of this particular exemplary embodiment, the body region and the third region may be P-doped regions.

In another exemplary embodiment, the technique may be realized as a method for providing a direct injection semiconductor memory device. The method may comprise coupling a first region to a bit line and coupling a second region to a source line. The method may also comprise coupling a body region spaced apart from and capacitively to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The method may further comprise coupling a third region to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.

In accordance with other aspects of the particular exemplary embodiment, the constant voltage source may apply a positive bias to the third region via the carrier injection line.

In accordance with further aspects of this particular exemplary embodiment, the constant voltage source may apply 0V or a negative bias to the third region via the carrier injection line.

In accordance with additional aspects of this particular exemplary embodiment, the constant voltage source may be coupled to a plurality of the carrier injection lines.

In accordance with yet another aspect of this particular exemplary embodiment, the bit line may extend from the first region perpendicular to at least one of the source line, the word line, and the carrier injection line.

In accordance with other aspects of the particular exemplary embodiment, the word line may extend from near the body region horizontally parallel to the carrier injection line.

In accordance with further aspects of this particular exemplary embodiment, the source line may extend from the second region horizontally parallel to at least one of the word line and the carrier injection line.

In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise a fourth region disposed between the third region and a substrate.

In accordance with yet another aspect of this particular exemplary embodiment, the fourth region may be N-doped region and the substrate is a P-type substrate.

In accordance with other aspects of the particular exemplary embodiment, the first region and the second region may be N-doped regions.

In accordance with further aspects of this particular exemplary embodiment, the body region and the third region may be P-doped regions.

In another exemplary embodiment, the technique may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first region via a bit line and applying a second voltage potential to a second region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively to a body region that is electrically floating and disposed between the first region and the second region. The method may further comprise applying a constant voltage potential to a third region via a carrier injection line.

In accordance with other aspects of the particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a read operation.

In accordance with further aspects of this particular exemplary embodiment, the method may further comprise lowering the first voltage potential applied to the bit line from the first voltage potential applied to the bit line during a hold operation to perform a read operation.

In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a write logic low operation.

In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise lowering the first voltage potential applied to the first region via the bit line from the first voltage potential applied to the first region during a hold operation to perform a write logic low operation.

In accordance with other aspects of the particular exemplary embodiment, the method may further comprise lowering the second voltage potential applied to the second region via the source line from the second voltage potential applied to the second region during a hold operation to perform a write logic low operation.

In accordance with further aspects of this particular exemplary embodiment, the method may further comprise lowering the third voltage potential applied to the word line from the third voltage potential applied to the word line during a write logic low operation to perform a write logic high operation.

In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise maintaining the first voltage potential applied to the bit line from the first voltage potential applied to the bit line during a write logic low operation to perform a write logic high operation.

In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise maintaining the second voltage potential applied to the source line from the second voltage potential applied to the source line during a write logic low operation to perform a write logic high operation.

In another exemplary embodiment, the technique may be realized as an apparatus comprising a first P-doped region coupled to a bit line and a second P-doped region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, and wherein the body region may be electrically floating and disposed between the first P-doped region and the second P-doped region. The apparatus may further comprise a third N-doped region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second P-doped region.

In accordance with other aspects of the particular exemplary embodiment, the body region may be an N-doped region.

In accordance with other aspects of the particular exemplary embodiment, the constant voltage source may apply a positive bias to the third N-doped region via the carrier injection line.

In accordance with further aspects of this particular exemplary embodiment, the constant voltage source may apply 0V or a negative bias to the third N-doped region via the carrier injection line.

In accordance with additional aspects of this particular exemplary embodiment, the constant voltage source may be coupled to a plurality of the carrier injection lines.

In accordance with yet another aspect of this particular exemplary embodiment, the apparatus may further comprise a fourth region disposed between the third N-doped region and a substrate.

In another exemplary embodiment, the technique may be realized as a direct injection semiconductor memory device comprising a first region coupled to a bit line and a second region directly coupled to a source line and capacitively coupled to a field-effect transistor word line. The direct injection semiconductor memory device may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further comprise a third region coupled to a carrier injection line.

In another exemplary embodiment, the technique may be realized as a direct injection semiconductor memory device comprising a first region coupled to a bit line and a second region coupled to a source line. The direct injection semiconductor memory device may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further comprise a third region coupled to a carrier injection line, wherein at least a portion of the third region is directly coupled to the second region.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Referring toFIG. 1, there is shown a block diagram of a semiconductor memory device10comprising a memory cell array20, data write and sense circuitry36, and memory cell selection and control circuitry38in accordance with an embodiment of the present disclosure. The memory cell array20may comprise a plurality of memory cells12each coupled to the memory cell selection and control circuitry38via a word line (WL)28, a source line (CN)30, and a carrier injection line (EP)34, and to the data write and sense circuitry36via a bit line (EN)32. It may be appreciated that the source line (CN)30and the bit line (EN)32are designations used to distinguish between two signal lines and they may be used interchangeably. The data write and sense circuitry36may read data from and may write data to selected memory cells12. In an exemplary embodiment, the data write and sense circuitry36may include a plurality of data sense amplifiers. Each data sense amplifier may receive at least one bit line (EN)32and a current or voltage reference signal. For example, each data sense amplifier may be a cross-coupled type sense amplifier to sense a data state stored in a memory cell12.

Each data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In an exemplary embodiment, each data sense amplifier may employ current sensing circuitry and/or techniques. For example, a current sense amplifier may compare current from a selected memory cell12to a reference current (e.g., the current of one or more reference cells). From that comparison, it may be determined whether the selected memory cell12stores a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). It may be appreciated by one having ordinary skill in the art that various types or forms of the data write and sense circuitry36(including one or more sense amplifiers, using voltage or current sensing techniques, to sense a data state stored in a memory cell12) may be employed to read data stored in memory cells12and/or write data to memory cells12.

Also, the memory cell selection and control circuitry38may select and/or enable one or more predetermined memory cells to facilitate reading data therefrom and/or writing data thereto by applying control signals on one or more word lines (WL)28, source lines (CN)30, and/or carrier injection lines (EP)34. The memory cell selection and control circuitry38may generate such control signals from address signals, for example, row address signals. Moreover, the memory cell selection and control circuitry38may include a word line decoder and/or driver. For example, the memory cell selection and control circuitry38may include one or more different control/selection techniques (and circuitry therefor) to select and/or enable one or more predetermined memory cells12. Notably, all such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present disclosure.

In an exemplary embodiment, the semiconductor memory device may implement a two step write operation whereby all the memory cells12in a row of memory cells12may be written to a predetermined data state by first executing a “set” or a logic high (e.g., binary “1” data state) write operation, whereby all of the memory cells12in the row of memory cells12are written to logic high (e.g., binary “1” data state). Thereafter, selected memory cells12in the row of memory cells12may be selectively written to the predetermined data state (e.g., a logic low (binary “0” data state)). The semiconductor memory device10may also implement a one step write operation whereby selective memory cells12in a row of memory cells12may be selectively written to either a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state) without first implementing a “set” operation. The semiconductor memory device10may employ any of the exemplary writing, preparation, holding, refresh, and/or reading techniques described herein.

The memory cells12may comprise N-type, P-type and/or both types of transistors. Circuitry that is peripheral to the memory array20(for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may also include P-type and/or N-type transistors. Regardless of whether P-type or N-type transistors are employed in memory cells12in the memory cell array20, suitable voltage potentials (for example, positive or negative voltage potentials) for reading from and/or writing to the memory cells12should be well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, a discussion of such suitable voltage potentials will not be included herein.

Referring toFIG. 2, there is shown a schematic diagram of at least a portion of the memory cell array20having the plurality of memory cells12in accordance with an embodiment of the present disclosure. Each of the memory cells12may comprise a first bipolar transistor14aand a second bipolar transistor14bcoupled to each other. For example, the first bipolar transistor14aand/or the second bipolar transistor14bmay be an NPN bipolar transistor or an PNP bipolar transistor. As illustrated inFIG. 2, the first bipolar transistor14amay be an NPN bipolar transistor and the second bipolar transistor14bmay be an PNP bipolar transistor. In another exemplary embodiment, the first memory transistor14amay be an PNP bipolar transistor and the second memory transistor14bmay be an NPN bipolar transistor. Each memory cell12may be coupled to a respective word line (WL)28, a respective source line (CN)30, a respective bit line (EN)32, and a respective carrier injection line (EP)34. Data may be written to or read from a selected memory cell12by applying suitable control signals to a selected word line (WL)28, a selected source line (CN)30, a selected bit line (EN)32, and/or a selected carrier injection line (EP)34. In an exemplary embodiment, each word line (WL)28, each source line (CN)30, and carrier injection line (EP)34may extend horizontally parallel to each other in a row direction. Each bit line (EN)32may extend vertically in a column direction perpendicular to each word line (WL)28, source line (CN)30, and/or carrier injection line (EP)34.

In an exemplary embodiment, one or more respective bit line (EN)32may be coupled to one or more data sense amplifiers (not shown) of the data write and sense circuitry36to read data states of one or more memory cells. A data state may be read from one or more selected memory cells12by applied one or more control signals. A voltage and/or a current may be generated by the one or more selected memory cells12and outputted to the data write and sense circuitry36via a corresponding bit line (EN)32in order to read a data state stored in each selected memory cell12. Also, a data state may be written to one or more selected memory cells12by applying one or more control signals to one or more selected memory cells12via a selected word line (WL)28, a selected source line (CN)30, a selected bit line (EN)32, and/or a selected carrier injection line (EP)34. The one or more control signals applied to one or more selected memory cells12via a selected word line (WL)28, selected source line (CN)30, a selected bit line (EN)32, and/or a selected carrier injection line (EP)34may control the first bipolar transistor14aof each selected memory cell12in order to write a desired data state to each selected memory cell12. In the event that a data state is read from a selected memory cell12via the bit lines (EN)32, then only the bit line (EN)32may be coupled to the data sense amplifier of the data write and sense circuitry36while the source line (CN)30may be separately controlled via a voltage/current source (e.g., a voltage/current driver) of the memory cell selection and control circuitry38.

The carrier injection lines (EP)34corresponding to different rows of the memory cell array20may be coupled to each other. In an exemplary embodiment, the carrier injection lines (EP)34(e.g., EP<0>, EP<1>, and EP<2>) of the memory cell array20may be coupled together and driven by subcircuits of the memory cell selection and control circuitry38(e.g., driver, inverter, and/or logic circuits) or biased at a constant voltage potential. The subcircuits coupled to each carrier injection line (EP)34may be independent voltage drivers located within and/or integrated with the memory cell selection and control circuitry38. To reduce an amount of space taken by the subcircuits of the memory cell selection and control circuitry38, a plurality of carrier injection lines (EP)34of the memory cell array20may be coupled to a single subcircuit within the memory cell selection and control circuitry38. In other exemplary embodiments, a plurality of carrier injection lines (EP)34of the memory cell array may be coupled to a voltage potential generating circuit located outside of the memory cell selection and control circuitry38. In an exemplary embodiment, the subcircuits of the memory cell selection and control circuitry38may bias a plurality of carrier injection lines (EP)34coupled together to different voltage and/or current levels (e.g., 0V, 1.0V, etc).

As illustrated inFIG. 2, three rows of carrier injection lines (EP)34may be coupled together, however, it may be appreciated by one skilled in the art that the number of rows of carrier injection lines (EP)34coupled together within the memory cell array20may vary. For example, four rows of carrier injection lines (EP)34, sixteen rows of carrier injection lines (EP)34, thirty-two rows of carrier injection lines (EP)34, and/or sixty-four rows of carrier injection lines (EP)34may be coupled together.

Referring toFIG. 3, there is shown a cross-sectional view of two memory cells12along a column direction of the memory cell array20shown inFIG. 1in accordance with an embodiment of the present disclosure. As discussed above, each memory cell12may comprise two bipolar transistors. In an exemplary embodiment, the first bipolar transistor14amay be a NPN bipolar transistor and the second bipolar transistor14bmay be a PNP bipolar transistor. In an exemplary embodiment, the first bipolar transistor14aand the second bipolar transistor14bmay share one or more common regions. The first NPN bipolar transistor14amay comprise an N+ emitter region120, a P− base region122, and an N+ collector region124. The second PNP bipolar transistor14bmay comprise the P− collector region122, the N+ base region124, and an P+ emitter region126. The N+ region120, the P− region122, the N+ region124, and/or the P+ region126may be disposed in sequential contiguous relationship within a pillar or fin configuration that may extend vertically to a plane defined by an N-well region128and/or an P− substrate130. In an exemplary embodiment, the P− region122may be an electrically floating body region of the memory cell configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the word line (WL)28.

As shown inFIG. 3, the N+ emitter region120of the first bipolar transistor14amay be coupled to a corresponding bit line (EN)32. In an exemplary embodiment, the N+ emitter region120of the first bipolar transistor14amay be formed of a semiconductor material (e.g., silicon) comprising donor impurities and coupled to the bit line (EN)32. In an exemplary embodiment, the bit line (EN)32may be formed of a metal layer. In another exemplary embodiment, the bit line (EN)32may be formed of a polycide layer (e.g., a combination of a metal material and a silicon material). The bit line (EN)32may provide a means for accessing one or more selected memory cells12on a selected row.

As also shown inFIG. 3, the P− base region122of the first bipolar transistor14aor the P− collector region122of the second bipolar transistor14bmay be capacitively coupled to a corresponding word line (WL)28. The P− region122may be formed of a semiconductor material (e.g., intrinsic silicon) comprising acceptor impurities and capacitively coupled to the word line (WL)28. The P− region122and the word line (WL)28may be capacitively coupled via an insulating or dielectric material. Also, the word line (WL)28may be formed of a polycide layer or a metal layer extending in a row direction of the memory cell array20.

As further shown inFIG. 3, the N+ region124of the memory cell12may be coupled to a source line (CN)30. The N+ region124may be formed of a semiconductor material (e.g., silicon) comprising donor impurities. In an exemplary embodiment, the source line (CN)30may be formed of a polycide layer. In another exemplary embodiment, the source line (CN)30may be formed of a metal layer. The source line (CM)30may circumferentially surround the N+ region124of the memory cell12. The source line (CN)30may reduce a disturbance to the memory cell12. For example, the source line (CN)30may be formed of a metal layer and therefore may reduce a hole disturbance in the memory cell12. The source line (CN)30may extend horizontally in parallel to the word line (WL)28and/or the carrier injection line (EP)34, and may be coupled to a plurality of memory cells12(e.g., a row of memory cells12). For example, the source line (CN)30and the word line (WL)28and/or the carrier injection line (EP)34may be arranged in different planes and configured to be parallel to each other. In an exemplary embodiment, the source line (CN)30may be arranged in a plane between a plane containing the word line (WL)28and a plane containing the carrier injection line (EP)34.

As further shown inFIG. 3, the P+ emitter region126of the second bipolar transistor14amay be coupled to the carrier injection line (EP)34. The P+ region126may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities and directly coupled to the carrier injection line (EP)34. In an exemplary embodiment, the P+ region126may be configured as an input region for charges to be stored in the P− region122of the memory cell12. The charges to be stored in the P− region122of the memory cell12may be supplied by the carrier injection line (EP)34and input into the P− region122via the P+ region126.

The carrier injection line (EP)34may be formed of a polycide layer or a metal layer extending in a row direction of the memory cell array20. For example, the carrier injection line (EP)34may extend horizontally in parallel to the word line (WL)28and/or the source line (CN)30, and may be coupled to a plurality of memory cells12(e.g., a row of memory cells12). For example, the carrier injection line (EP)34and the word line (WL)28and/or the source line (CN)30may be arranged in different planes and configured to be parallel to each other. In an exemplary embodiment, the carrier injection line (EP)34may be arranged in a plane below a plane containing the word line (WL)28and a plane containing the source line (CN)30. In another exemplary embodiment, the carrier injection line (EP)34may be removed when the P+ region126may form a continuous plane for the entire memory cell array20.

As discussed above, carrier injection lines (EP)34corresponding to different rows of the memory cell array20may be coupled to each other in order to bias and/or access memory cells12in different rows of the memory cell array20. Thus, in an exemplary embodiment, P+ regions126of memory cells12in different rows of memory cell array20may be coupled to each other by coupling the carrier injection lines (EP)34corresponding to different rows of the memory cell array20. In another exemplary embodiment, carrier injection lines (EP)34corresponding to different rows of the memory cell array20may be coupled to each other via a carrier injection line plate, carrier injection grid, or a combination of a carrier injection line plate and a carrier injection grid.

As further shown inFIG. 3, the N-well region128may be disposed between the P+ region126and the P− substrate130. The N-well region128may be formed of a semiconductor material (e.g., silicon) comprising donor impurities and extending in a planar direction parallel to the P− substrate130. In an exemplary embodiment, the N-well region128may comprise a strip protruding portion corresponding to each row of the memory cell array20. For example, the strip protruding portion of the N-well region128may be configured to accommodate a row of memory cells12of the memory cell array20.

In an exemplary embodiment, the P− substrate130may be made of a semiconductor material (e.g., silicon) comprising acceptor impurities and form the base of the memory cell array20. In alternative exemplary embodiments, a plurality of P− substrates130may form the base of the memory cell array20or a single P− substrate130may form the entire base of the memory cell array20.

Referring toFIG. 4, there are shown control signal voltage waveforms for performing write and read operations on a memory cell in accordance with an embodiment of the present disclosure. A write operation may include a write logic high (e.g., binary “1” data state) operation and a write logic low (e.g., binary “0” data state) operation. Also, each write logic high (e.g., binary “1” data state) operation and write logic low (e.g., binary “0” data state) operation may include a plurality of steps of write operation. For example, a write logic high (e.g., binary “1” data state) operation may include a two step write operation. The first step write operation of the write logic high (e.g., binary “1” data state) may be a write logic low (e.g., binary “0” data state) operation and the second step write operation of the write logic high (e.g., binary “1” data state) may be a write logic high (e.g., binary “1” data state) operation. The first step (e.g., write logic low (binary “0” data state) operation) of the write logic high (e.g., binary “1” data state) operation may include control signals configured to “clear” majority charges stored in one or more selected memory cells12of one or more selected rows of the memory cell array20.

In an exemplary embodiment, a voltage potential applied to the word line (WL)28may be adjusted, such that the voltage potential at the P− region122(e.g., by capacitively coupling to the word line (WL)28) may be higher than a voltage potential applied to the bit line (EN)32and/or the source line (CN)30by a predetermined voltage potential. The predetermined voltage potential may be a threshold voltage potential or forward bias voltage potential of the first bipolar transistor14aand/or the second bipolar transistor14b. For example, the predetermined voltage potential may be approximately 0.7V.

In an exemplary embodiment, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be raised to 2.5V from 0V. Also, a voltage potential applied to the bit line (EN)32may be maintained at 0V, a voltage potential applied to the source line (CN)30may be maintained at 1.5V, and a voltage potential applied to the carrier injection line (EP)34may be maintained at 1.0V. In an exemplary embodiment, when the voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) is raised to 2.5V, the voltage potential applied to the N+ region120via the bit line (EN)32is maintained at 0V, the voltage potential applied to the N+ region124via the source line (CN)30is maintained at 1.5V, and the voltage potential applied to the P+ region126via the carrier injection line (EP)34is maintained at 1.0V, the first bipolar transistor14a(e.g., regions120-124) may be switched to an “ON” state to remove charges stored in the P− region122through the forward biased junction between the P− region122and the N+ region120in order to perform the first step (e.g., write logic low (binary “0” data state) operation) of the write logic high (e.g., binary “1” data state) operation.

In another exemplary embodiment, a write logic high (e.g., binary “1” data state) operation may be a single step write operation and may not include the first step write operation (e.g., write logic low (binary “0” data state) operation). For example, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be maintained at 0V and the junction between the P− region122and the N+ region120may not be forward biased and cause the first bipolar transistor14ato remain in an “OFF” state. The charges previously stored in the P− region122of the memory cell12may remain in the P− region122because the first bipolar transistor14amay remain in the “OFF” state.

During the second step of the write logic high (e.g., binary “1” data state) operation, a predetermined voltage potential may be applied to the word line (WL)28(e.g., capacitively coupled to the P− region122), the N+ region124via the source line (CN)30, the N+ region120via the bit line (EN)32, and/or the P+ region126via the carrier injection line (EP)34. The voltage potential applied to the N+ region124via the source line (CN)30may be lowered in order to forward bias the junction between the N+ region124and the + region126and switch the second bipolar transistor14bto an “ON” state. In an exemplary embodiment, a voltage potential applied to the N+ region124via the source line (CN)30may be lowered to 0V from 1.5V. Also, the voltage potential applied to the word line (WL)28may maintain at 2.5V, the voltage potential applied to the N+ region120via the bit line (EN)32may maintain at 0V, and the voltage potential applied to the P+ region126via the carrier injection line (EP)34may maintain at 1.0V.

As discussed above, when the voltage potential applied to the N+ region124may be lowered to 0V, the junction between the N+ region124and the P+ region126may be forward biased and charges may be injected into the floating P− region122via the P+ region126and a logic high (e.g., binary “1” data state) may be written to the memory cell12. The floating P− region122may be charged to approximately 0.7V because the voltage potential applied to the N+ region120via the bit line (EN)32may be maintained at 0V. For example, a voltage potential higher than 0.7V may forward bias the junction between the N+ region120and the floating P− region122and additional charges (e.g., higher than 0.7V) injected into the floating P− region122may be leaked via the N+ region120.

At the end of the write logic high (e.g., binary “1” data state) operation, the voltage potentials applied to the memory cells12may adjust the amount of charge (e.g., an indication of data state) stored in the memory cells12. In an exemplary embodiment, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the floating P− region122) may be lowered to 0V from 2.5V. As discussed above, the floating P− region122may be charged to approximately 0.7V above the voltage potential at the N+ region120during the second step of the write logic high (e.g., binary “1” data state) operation. The voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the floating P− region122) may be lowered to 0V and may determine an amount of charge (e.g., an indication of data state) stored in the floating P− region122of the memory cells12. In an exemplary embodiment, the floating P− region122of the memory cell12may be charged to approximately 0.7V when the voltage potential applied on the word line (WL)28is 2.5V, however, when the voltage potential on the word line (WL)28is lowered to 0V (e.g., a holding voltage potential) the voltage potential at the floating P− region122may be lowered by some fraction of 2.5V due to the capacitive coupling of the voltage potential to the word line (WL)28. Because the voltage potential at the floating P− region122may be lowered due to the capacitive coupling to the word line (WL)28, the charges may continue to be injected into the floating P− region122until the voltage potential at the floating P− region122is again approximately 0.7V above the voltage potential at the N+ region120.

Also, at the conclusion of the write logic high (e.g., binary “1” data state) operation, the voltage potential applied to the N+ region124may be raised to a predetermined voltage potential to stop the charge injection into the floating P− region122by eliminating the forward bias at the junction of the N+ region124and the P+ region126and switch the second bipolar transistor14bto an “OFF” state. In other exemplary embodiments, as more charges are accumulated in the floating P− region122, the voltage potential at the floating P− region122may increase to approximately 0.7V above the voltage potential at N+ region124. At this time, the first bipolar transistor14amay start to turn to an “ON” state and the current generated by the first bipolar transistor14amay increase the voltage potential at N+ region124due to resistive voltage potential drop on the source line (CN)30. The increase of the voltage potential at N+ region124may lead to a decrease of current flow in the second bipolar transistor14bwhich in term may cause a decrease in the current load on the carrier injection line (EP)34after the write logic high (e.g., binary “1” data state) operation has been completed. In another exemplary embodiment, the N+ region124may be floating after pre-charged to a predetermined voltage potential (e.g., 0V as discussed above) in order to reduce a current flow within the second bipolar transistor14b. Thus, during a write logic high (e.g., binary “1” data state) operation, the first bipolar transistor14amay easily increase the voltage potential at the N+ region124when the P− region122is fully charged.

After the completion of a write logic high (e.g., binary “1” data state) operation, voltage potentials applied to the memory cell12may be maintained at a holding voltage potential. In particular, the control signals may be configured to maximize a retention time of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell12. Also, the control signals for the hold operation may be configured to eliminate or reduce activities or field (e.g., electrical fields across junctions which may lead to leakage of charges) within the memory cell12. In an exemplary embodiment, during a hold operation, the voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the floating P− region122) and the N+ region120, may be maintained at 0V. Also, the voltage potential applied to the N+ region124via the source line (CN)30may be maintained at 1.5V and the P+ region126via the carrier injection line (EP)34may be maintained at 1.0V. During the hold operation, the junction between the N+ region124and the P− region122and the junction between the N+ region120and the P− region122may be reverse biased in order to retain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell12.

The write operation may also include a write logic low (e.g., binary “0” data state) operation. In an exemplary embodiment, a voltage potential applied to the word line (WL)28may be adjusted, such that the voltage potential at the P− region122(e.g., by capacitively coupling to the word line (WL)28) may be higher than a voltage potential applied to the bit line (EN)32and/or the source line (CN)30by a predetermined voltage potential. The predetermined voltage potential may be a threshold voltage potential or forward bias voltage potential of the first bipolar transistor14aand/or the second bipolar transistor14b. For example, the predetermined voltage potential may be approximately 0.7V.

In an exemplary embodiment, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be raised to 2.5V from 0V. Also, a voltage potential applied to the bit line (EN)32may be raised to 1.5V from 0V in order to reduce a bias (e.g., a current in the first bipolar transistor14a) of the first bipolar transistor14awhen the voltage potential applied to the word line (WL)28is raised. A voltage potential applied to the source line (CN)30may be maintained at 1.5V, and a voltage potential applied to the carrier injection line (EP)34may be maintained at 1.0V. In an exemplary embodiment, when the voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) is raised to 2.5V, the voltage potential applied to the N+ region120via the bit line (EN)32is raised to 1.5V, the voltage potential applied to the N+ region124via the source line (CN)30is maintained at 1.5V, and the voltage potential applied to the P+ region126via the carrier injection line (EP)34is maintained at 1.0V, the first bipolar transistor14a(e.g., regions120-124) may be switched to an “ON” state to remove charges stored in the P− region122through the forward biased junction between the P− region122and the N+ region120and the forward biased junction between the P− region122and the N+ region124in order to perform the first step (e.g., write logic low (binary “0” data state) operation) of the write logic high (e.g., binary “1” data state) operation.

After the completion of a write logic low (e.g., binary “1” data state) operation, the voltage potentials applied to the memory cell12may be returned to a holding voltage potential, as discussed above. Again, a write logic high (e.g., binary “1” data state) operation may be performed, as discussed above.

In another exemplary embodiment, a read operation where the control signals may be configured to read a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in one or more selected memory cells12of one or more selected rows of the memory cell array20may be performed. The control signals may be configured to a predetermined voltage potential to implement a read operation via the bit line (EN)32. In an exemplary embodiment, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be initially (e.g., at the start of the read operation) raised to a predetermined voltage potential. For example, the voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) may be raised to 2.5V from 0V. Also, a voltage potential applied to the bit line (EN)32may be maintained at 0V, a voltage potential applied to the source line (CN)30may be maintained at 1.5V, and a voltage potential applied to the carrier injection line (EP)34may be maintained at 1.0V. In an exemplary embodiment, when the voltage potential applied to the word line (WL)28may be raised to 2.5V, the junction between the P− region122and the N+ region120may become forward biased and switch the first bipolar transistor14ato an “ON” state. When the first bipolar transistor14aswitches to an “ON” state, a change in voltage potential and/or current may be generated in the memory cell12. This change in voltage potential and/or current may be outputted to and detected by a data sense amplifier via the bit line (EN)32coupled to the Ni+ region120. After the completion of a read operation, voltage potentials applied to the memory cells12may return to a holding voltage potential, as discussed above.

Further illustrated inFIG. 4, are exemplary voltage potentials at the P− region122corresponding to various operations (e.g., read operation or write operation) performed on the memory cell12.

Referring toFIG. 5, there are shown control signal voltage waveforms for write operations performed on different columns of a memory cell array20when the carrier injection line (EP) is biased high in accordance with an embodiment of the present disclosure. For example, during one or more write operations, a predetermined voltage potential may be applied to the carrier injection line (EP)34. For example, the predetermined voltage potential applied to the carrier injection line (EP)34may be high or low. In an exemplary embodiment, a high predetermined voltage potential may be applied to the carrier injection line (EP)34, for example, 1.0V. Write operations may be performed to one or more memory cells12(e.g., corresponding to different bit lines (EN)32) on a selected row (e.g., corresponding to different word lines (WL)28, source lines (CN)30, and/or carrier injection lines (EP)34) of the memory cell array20. For example, different write operations may be performed to different memory cells12on a selected row of the memory cell array20. In an exemplary embodiment, a write logic high (e.g., binary “1” data state) operation may be performed to a first memory cell12(e.g., corresponding to first bit line (EN<0>)32), while a write logic low (e.g., binary “0” data state) operation may be performed to a second memory cell12(e.g., corresponding to second bit line (EN<1>)32) on a selected row of the memory cell array20.

As illustrated inFIG. 5, a write logic high (e.g., binary “1” data state) operation may be performed to a first memory cell12corresponding to a first bit line (EN<0>)32and a write logic low (e.g., binary “0” data state) operation may be performed to a second memory cell12corresponding to a second bit line (EN<1>)32of a selected row of the memory cell array20. During a write logic high (e.g., binary win data state) operation, a predetermined voltage potential applied to the N+ region124via a corresponding source line (CN)30may be lowered to 0V from 2.5V (e.g., holding voltage potential). Also, a predetermined voltage potential applied to the N+ region120via the bit line (EN<0>)32may be lowered to 0V from 2.5V (e.g., holding voltage potential). In an exemplary embodiment, the predetermined voltage potential applied to the N+ region124and the predetermined voltage potential applied to the N+ region120may be lowered to 0V simultaneously from 2.5V. The lowered voltage potential applied to the N+ region124via the corresponding source line (CN)30may cause the junction between the N+ region124and the P+ region126to become forward biased and switch the second bipolar transistor14bto an “ON” state. The majority charge carriers (e.g., holes) may be injected into the P− region122via the forward biased junction between the N+ region124and the P+ region126and a corresponding carrier injection line (EP)34. An amount of majority charge carriers may be accumulated/stored in the P− region122to indicate that a logic high (e.g., binary “1” data state) is stored in the memory cell12. In an exemplary embodiment, an amount of majority charge carriers accumulated/stored in the P− region122may be approximately 0.7V and/or until forward biasing the junction between the P− region122and the N+ region124.

Thereafter, a predetermined voltage potential applied to the word line (WL)28may be adjusted, such that the voltage potential at the P− region122(e.g., by capacitively coupling to the word line (WL)28)) may cause the junction between the P− region122and the N+ region124to become forward biased and deplete the P− region122of excessive majority charge carriers (e.g., holes). In an exemplary embodiment, a predetermined voltage potential applied to the word line (WL)28may be raised to approximately 2.5V from 0V (e.g., hold voltage potential). Subsequently, the predetermined voltage potential applied to the N+ region124via the source line (CN)30may be raised back to approximately 2.5V from 0V and the junction between the N+ region124and the P+ region126may become reverse biased and the second bipolar transistor14bmay be switched to an “OFF” state. The injection of the majority charge carriers may be stopped by reverse biasing the junction between the N+ region124and the P+ region126. Also, the predetermined voltage potential applied to the N+ region120via the bit line (EN<0>) may be raised back to 2.5V from 0V in order to obtain a higher voltage potential at the P− region122. At the end of a write logic high (e.g., binary “1” data state) operation, the predetermined voltage potential applied to the word line (WL)28may be lowered back to 0V from 2.5V in order to maintain the logic high (e.g., binary “1” data state) stored in the memory cell12.

Also, illustrated inFIG. 5, a write logic low (e.g., binary “0” data state) operation may be performed to a second memory cell12corresponding to a second bit line (EN<1>)32, while the write logic high (e.g., binary “1” data state) operation may be performed to the first memory cell12corresponding to the first bit line (EN<0>)32of a selected row of the memory cell array20, as discussed above. The predetermined voltage potentials applied to the second memory cell12corresponding to the second bit line (EN<1>)32via the word line (WL)28, the source line (CN)30, the carrier injection line (EP)34, may be similar to the predetermined voltage potentials applied to the first memory cell12corresponding to the first bit line (EN<0>)32except for a predetermined voltage potential applied to the N+ region120via the second bit line (EN<1>)32.

In an exemplary embodiment, a predetermined voltage potential applied to the N+ region120via the second bit line (EN<1>)32may remain at 2.5V for the duration of the write logic low (e.g., binary “0” data state) operation. For example, a predetermined voltage potential applied to the N+ region120via the second bit line (EN<1>)32may remain at 2.5V in order to maintain the voltage potential at the P− region122at a lower voltage potential. In an exemplary embodiment, the P− region122may not be coupled to a higher voltage potential due a junction capacitance between the N+ region120and the P− region122caused by varying the voltage potential applied to the N+ region120.

In another exemplary embodiment, a write logic low (e.g., binary “0” data state) operation may be performed to a first memory cell12corresponding to a first bit line (EN<0>)32, while a write logic high (e.g., binary “1” data state) operation may be performed to a second memory cell12corresponding to a second bit line (EN<1>)32. The write logic low (e.g., binary “0” data state) operation and the write logic high (e.g., binary “1” data state) may comprise similar predetermined voltage potentials (e.g., the word line (WL)28, the source line (CN)30, and/or the carrier injection line (EP)34) as discussed above, except for the predetermined voltage potential applied to the bit line (EN)32. For example, the predetermined voltage potential applied to the first bit line (EN<0>)32may remain at 2.5V in order to perform a write logic low (e.g., binary “0” data state) operation and the predetermined voltage potential applied to the second bit line (EN<1>)32may be lowered to 0V and subsequently raised back to 2.5V in order to perform a write logic high (e.g., binary “1” data state).

Further illustrated inFIG. 5, are exemplary voltage potentials at the P− region122corresponding to write operations performed on different columns of the memory cell array20when the carrier injection line (EP)34is biased high.

Referring toFIG. 6, there are shown control signal voltage waveforms for write operations performed on different columns of a memory cell array when the carrier injection line is biased low in accordance with an embodiment of the present disclosure. For example, during one or more write operations, a predetermined voltage potential may be applied to the carrier injection line (EP)34. For example, the predetermined voltage potential applied to the carrier injection line (EP)34may be high or low. In an exemplary embodiment, a low predetermined voltage potential may be applied to the carrier injection line (EP)34, for example, 0V. Write operations may be performed to one or more memory cells12(e.g., corresponding to different bit lines (EN)32) on a selected row (e.g., corresponding to different word lines (WL)28, source lines (CN)30, and/or carrier injection lines (EP)34) of the memory cell array20. For example, different write operations may be performed to different memory cells12on a selected row of the memory cell array20. In an exemplary embodiment, a write logic high (e.g., binary “1” data state) operation may be performed to a first memory cell12(e.g., corresponding to first bit line (EN<0>)32), while a write logic low (e.g., binary “0” data state) operation may be performed to a second memory cell12(e.g., corresponding to second bit line (EN<1>)32) on a selected row of the memory cell array20.

As illustrated inFIG. 6, a write logic high (e.g., binary “1” data state) operation may be performed to a first memory cell12corresponding to a first bit line (EN<0>)32and a write logic low (e.g., binary “0” data state) operation may be performed to a second memory cell12corresponding to a second bit line (EN<1>)32of a selected row of the memory cell array20. During a write logic high (e.g., binary “1” data state) operation, a predetermined voltage potential applied to the N+ region124via a corresponding source line (CN)30may be lowered to −2.0V from 0V (e.g., holding voltage potential).

Also, a predetermined voltage potential applied to the N+ region120via the bit line (EN<0>)32may be lowered to −2.0V from 0V (e.g., holding voltage potential). In an exemplary embodiment, the predetermined voltage potential applied to the N+ region124and the predetermined voltage potential applied to the N+ region120may be lowered to −2.0V consecutively from 0V.

The lowered voltage potential applied to the N+ region124via the corresponding source line (CN)30may cause the junction between the N+ region124and the P+ region126to become forward biased and switch the second bipolar transistor14bto an “ON” state. The majority charge carriers (e.g., holes) may be injected into the P− region122via the forward biased junction between the N+ region124and the P+ region126and a corresponding carrier injection line (EP)34. An amount of majority charge carriers may be accumulated/stored in the P− region122to indicate that a logic high (e.g., binary “1” data state) is stored in the memory cell12. In an exemplary embodiment, an amount of majority charge carriers accumulated/stored in the P− region122may be approximately −1.3V and/or until forward biasing the junction between the P− region122and the N+ region124.

Thereafter, a predetermined voltage potential applied to the word line (WL)28may be adjusted, such that the voltage potential at the P− region122(e.g., by capacitively coupling to the word line (WL)28)) may cause the junction between the P− region122and the N+ region124to become forward biased and deplete the P− region122of excessive majority charge carriers (e.g., holes). In an exemplary embodiment, a predetermined voltage potential applied to the word line (WL)28may be raised to approximately 2.5V from 0V (e.g., hold voltage potential). Subsequently, the predetermined voltage potential applied to the N+ region124via the source line (CN)30may be raised back to approximately 0V from −2.0V and the junction between the N+ region124and the P+ region126may become reverse biased and the second bipolar transistor14bmay be switched to an “OFF” state. The injection of the majority charge carriers may be stopped by reverse biasing the junction between the N+ region124and the P+ region126. Subsequently, the predetermined voltage potential applied to the N+ region120via the bit line (EN<0>)32may be lowered to −2.0V from 0V in order to obtain a higher voltage potential at the P− region122. At the end of a write logic high (e.g., binary “1” data state) operation, the predetermined voltage potential applied to the word line (WL)28may be lowered back to 0V from 2.5V in order to maintain the logic high (e.g., binary “1” data state) stored in the memory cell12. Finally, the predetermined voltage potential applied to the N+ region120via the bit line (EN<0>)32may be raised back to 0V from −2.0V.

Also, illustrated inFIG. 6, a write logic low (e.g., binary “0” data state) operation may be performed to a second memory cell12corresponding to a second bit line (EN<1>)32, while the write logic high (e.g., binary “1” data state) operation may be performed to the first memory cell12corresponding to the first bit line (EN<0>)32of a selected row of the memory cell array20, as discussed above. The predetermined voltage potentials applied to the second memory cell12corresponding to the second bit line (EN<1>)32via the word line (WL)28, the source line (CN)30, the carrier injection line (EP)34, may be similar to the predetermined voltage potentials applied to the first memory cell12corresponding to the first bit line (EN<0>)32except for a predetermined voltage potential applied to the N+ region120via the second bit line (EN<1>)32.

In an exemplary embodiment, a predetermined voltage potential applied to the region120via the second bit line (EN<1>)32may remain at 0V for the duration of the write logic low (e.g., binary “0” data state) operation. For example, a predetermined voltage potential applied to the N+ region120via the second bit line (EN<1>)32may remain at 0V in order to maintain the voltage potential at the P− region122at a lower voltage potential. In an exemplary embodiment, the P− region122may not be coupled to a higher voltage potential due a junction capacitance between the N+ region120and the P− region122caused by varying the voltage potential applied to the region120.

In another exemplary embodiment, a write logic low (e.g., binary “0” data state) operation may be performed to a first memory cell12corresponding to a first bit line (EN<0>)32, while a write logic high (e.g., binary “1” data state) operation may be performed to a second memory cell12corresponding to a second bit line (EN<1>)32. The write logic low (e.g., binary “0” data state) operation and the write logic high (e.g., binary “1” data state) may comprise similar predetermined voltage potentials (e.g., the word line (WL)28, the source line (CN)30, and/or the carrier injection line (EP)34) as discussed above, except for the predetermined voltage potential applied to the bit line (EN)32. For example, the predetermined voltage potential applied to the first bit line (EN<0>)32may remain at 0V in order to perform a write logic low (e.g., binary “0” data state) operation and the predetermined voltage potential applied to the second bit line (EN<1>)32may be lowered to −2.0V and subsequently raised back to 0V in order to perform a write logic high (e.g., binary “1” data state).

Further illustrated inFIG. 6, are exemplary voltage potentials at the P− region122corresponding to write operations performed on different columns of a memory cell array when the carrier injection line (EP)34is based low.

Referring toFIG. 7, there are shown control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an embodiment of the present disclosure. For example, the refresh operation may include control signals configured to perform one or more operations. In an exemplary embodiment, the refresh operation may include a read operation, a write logic low (e.g., binary “0” data state) operation, a write logic high (e.g., binary “1” data state) operation, and/or preparation to end operation. Prior to performing a refresh operation, the control signals may be configured to perform a hold operation in order to maintain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell12. In particular, the control signals may be configured to perform a hold operation in order to maximize a retention time of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell12. Also, the control signals for the hold operation may be configured to eliminate or reduce activities or fields (e.g., electrical fields between junctions which may lead to leakage of charges) within the memory cell12. In an exemplary embodiment, during a hold operation, a negative voltage potential may be applied to the word line (WL)28that may be capacitively coupled to the P− region122of the memory cell12while voltage potential applied to other regions (e.g., the N+ region120, the N+ region124, and/or the P+ region126) may be maintained at approximately 1.2V. For example, the negative voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) may be −1.5V. During the hold operation, the junction between the N+ region124and the P− region122and the junction between the N+ region120and the P− region122may be reverse biased in order to retain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell12.

In an exemplary embodiment, a refresh operation may include a read operation where the control signals may be configured to read a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in one or more selected memory cells12of one or more selected rows of the memory cell array20. The control signals may be configured to a predetermined voltage potential to implement a read operation via the bit line (EN)32. In an exemplary embodiment, a voltage potential applied to the N+ region120via the bit line (EN)32may be lowered to a predetermined voltage potential. Subsequent to or simultaneous to lowering the voltage potential applied to the N+ region120via the bit line (EN)32, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be raised to a predetermined voltage potential. For example, the voltage potential applied to the N+ region120of the memory cell12may be lowered to 0V from 1.2V, while the voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) may be raised to −0.5V from −1.5V.

During a read operation, a voltage potential applied to the N+ region120via the bit line (EN)32may be lowered to 0V from 1.2V and subsequently or simultaneously, a voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) may be raised to −0.5V.

Under such biasing of the memory cell12, when a logic high (e.g., binary “1” data state) is stored in the memory cell12, the junction between the P− region122and the N+ region120may become forward biased. The voltage or current generated when forward biasing the junction between the P− region122and the N+ region120may be outputted to a data sense amplifier via the bit line (EN)32coupled to the N+ region120. In another exemplary embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell12, the junction between the P− region122and the N+ region120may remain reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage). No voltage or current may be generated when the junction between the P− region122and the N+ region120is reverse biased or weakly forward biased and a data sense amplifier may detect no voltage or current via the bit line (EN)32coupled to the N+ region120. The voltage potential applied during a read operation may not switch the second bipolar transistor14bto an “ON” state. The second bipolar transistor14bmay remain in an “OFF” state during the read operation.

In other exemplary embodiments, a refresh operation may include a write logic low (e.g., binary “0” data state) operation where the control signals may be configured to perform one or more write operations to one or more selected memory cells12of one or more selected rows of the memory cell array20. For example, the write logic low (e.g., binary “0” data state) operation may be performed on one or more selected rows of the memory cell array20or the entire memory cell array20and a subsequent write logic high (e.g., binary “1” data state) operation may be performed on one or more selected memory cells12. For example, a voltage potential applied to the N+ region124via the source line (CN)30may be lowered to 0V from 1.2V. Subsequent to or simultaneously to lowering the voltage potential applied to the N+ region124via the source line (CN)30, a voltage potential applied to the word line (WL)28may be adjusted, such that the voltage potential at the P− region122(e.g., by capacitively coupling to the word line (WL)28) may be higher than a voltage potential applied to the source line (CN) and/or the bit line (EN)32by a predetermined voltage potential. The predetermined voltage potential may be a threshold voltage potential or forward bias voltage potential of the first bipolar transistor14aand/or the second bipolar transistor14b. For example, the predetermined voltage potential may be approximately 0.7V.

In an exemplary embodiment, a voltage potential applied to the N+ region124via the source line (CN)30may be lowered to 0V from 1.2V. Also, a voltage potential applied to the bit line (EN)32may remain the same as the voltage potential applied during the read operation (e.g., 0V). Power may be saved by eliminating switching or maintaining the voltage potential applied via the bit line (EN)32during the read operation and the write logic low (e.g., binary “0” data state). In an exemplary embodiment, when the voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122of the memory cell12) is raised to 0.5V, the voltage potential applied to the N+ region124via the source line (CN)30is maintained at 0V, the voltage potential applied to the N+ region120via the bit line (EN)32is maintained at 0V, and a logic high (e.g., binary “1” data state) is stored in the memory cell12, the first bipolar transistor14a(e.g., regions120-124) may be switched to an “ON” state to remove majority charge carriers from the P− region122via the forward biased junction between the P− region122and the N+ region120and the junction between the P− region122and the N+ region124. In another exemplary embodiment, when the voltage potential applied to the N+ region124via the source line (CN)30, the voltage potential applied to the N+ region via the bit line (EN)32are maintained at 0V and a logic low (e.g., binary “0” data state) is stored in the memory cell12, the junction between the N+ region120and the P− region122may not be forward biased and the junction between the P− region122and the N+ region124may not be forward biased, thus the logic low (e.g., binary “0” data state) may be maintained in the memory cell12.

Also, when the voltage potential applied to the N+ region124via the source line (CN)30is lowered to 0V, the junction between N+ region120and the P− region122and the junction between the P− region122and the N+ region124may be forward biased and charges stored in the P− region122may be depleted via the N+ region120and/or the N+ region124. In other exemplary embodiments, the write logic low (e.g., binary “0” data state) operation may be performed via the word line (WL)28. For example, a voltage potential may be applied to the word line (WL)28to create a depletion region within the P− region122. The voltage potential applied to the word line (WL)28may be sufficient to create a depletion region within the P− region122that may extend from N+ region120to N+ region124within the P− region122. The depletion region within the P− region122may couple the N+ region120, the P− region122, and the N+ region124to each other and may create a single region including the N+ region120, the P− region122, and the N+ region124. The charges stored in the P− region122may be depleted via the N+ region120and/or the N+ region124.

In another exemplary embodiment, a refresh operation may include a write logic high (e.g., binary “1” data state) operation where the control signals may be configured to write a logic high (e.g., binary “1” data state) to the one or more selected memory cells12. For example, a predetermined voltage potential may be applied to the word line (WL)28(e.g., capacitively coupled to the P− region122), the N+ region124via the source line (CN)30, the N+ region120via the bit line (EN)32, and/or the P+ region via the carrier injection line (EP)34. In an exemplary embodiment, in preparation to perform the write logic high (e.g., binary “1” data state) operation, the voltage potential applied to the N+ region120and/or the N+ region124of the one or more selected memory cells12may be maintained at 0V. The voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be lowered to −1.0V.

Under such biasing, the P− region122may be positively charged via the forward biased junction between the N+ region120and the P− region122and the junction between the P− region122and the N+ region124so that a logic high (e.g., binary “1” data state) may be written to the P− region122(e.g., majority charge carrier injected into the P− region122from the P+ region126). As more majority charge carriers are accumulated in the P− region122, the voltage potential at the P− region122may increase to approximately 0.7V to 1.0V above the voltage potential at N+ region124.

In order to maintain a logic low (e.g., binary “0” data state) in one or more unselected memory cells12, a masking operation may be performed on the one or more selected memory cells12. For example, the voltage potential applied to the N+ region120and/or the N+ region124of the one or more unselected memory cells12may be raised to 0.7V or higher (e.g., 1.2V) in order to prevent majority charge carrier injection into the P− region122from the P+ region126via the N+ region124. Under such biasing, the junction between the N+ region120and the P− region122may not be forward biased and the junction between the P+ region126and the N+ region124may not be forward biased or weakly forward biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage) to prevent the majority charge carrier flow and the logic low (e.g., binary “0” data state) may be maintained in the memory cell12.

At the end of a write logic high (e.g., binary “1” data state) operation, the voltage potential applied to the N+ region120via the bit line (EN)32and/or the N+ region124via the source line (CN)30may be raised to a predetermined voltage potential in order to stop the majority chare carriers being injected into the P− region122.

The refresh operation may also include a preparation to end operation. During the preparation to end operation, the voltage potentials applied to the memory cells12may adjust the amount of majority charge carriers or data state stored in the P− region122of the memory cells12. As discussed above, the P− region122may be charged to approximately 0.7V above the voltage potential at the N+ region124during the write logic high (e.g., binary “1” data state) operation. The voltage potential applied to the word line (WL)28(e.g., capacitively coupled to the P− region122) may be lowered to −1.5V and may determine an amount of majority charge carriers or data state stored in the P− region122of the memory cells12. In an exemplary embodiment, the P− region122of the memory cell12may be charged to approximately 0.7V when the voltage potential applied on the word line (WL)28is −1.0V, however, when the voltage potential on the word line (WL)28is lowered to −1.5V (e.g., a holding voltage potential) the voltage potential at the P− region122may be lowered by some fraction of 0.5V due to the capacitive coupling of the voltage potential to the word line (WL)28.

The voltage potential applied to the word line (WL)28during the write logic high (e.g., binary “1” data state) may be selected based on one or more factors. For example, the one or more factors may include a disturbance (e.g., disturbance may increase with an increase in the amount of charge stored in the P− region122of the memory cells12), charge time (e.g., charge time may increase with an increase in the amount of charge stored in the P− region122of the memory cells12), and retention time (e.g., retention time may decrease with a decrease in the amount of charge stored in the P− region122of the memory cells12). Also, a voltage potential applied to the N+ region120via the bit line (EN)32and/or the N+ region124via the source line (CN)30may remain at 1.2V during the preparation to end operation in order to maintain the second bipolar transistor14bin the “OFF” state. After the refresh operation, the voltage potentials applied to the memory cells12may be returned to the hold operation in order to retain a data state (e.g., logic low (binary “0” data state) or logic high (binary “1” data state)).

Further illustrated inFIG. 7, are exemplary voltage potentials at the P− region122corresponding to various operations during a refresh operation performed on the memory cell12.

Referring toFIG. 8, there is shown a schematic diagram of at least a portion of the memory cell array20having the plurality of memory cells12in accordance with a first alternative embodiment of the present disclosure. For example, the memory cell array20shown inFIG. 8may be implemented with the structure and techniques similar to that of the memory cell array20shown inFIG. 2, except that each of the memory cells12may comprise a bipolar transistor14aand a diode14bcoupled to each other. For example, the bipolar transistor14amay be an NPN bipolar transistor or an PNP bipolar transistor and the diode14bmay be a PN junction diode. In an exemplary embodiment, the bipolar transistor14amay be an NPN bipolar transistor. As discussed above, each memory cell12may be coupled to a respective word line (WL)28, a respective source line (CN)30, a respective bit line (EN)32, and a respective carrier injection line (EP)34.

In an exemplary embodiment, the bipolar transistor14aand the diode14bmay share one or more common regions. The NPN bipolar transistor14amay comprise an N+ emitter region120, a P− base region122, and an N+collector region124. The diode14bmay comprise the N+ region124and a P+ region126. The N+ region120, the P− region122, the N+ region124, and/or the P+ region126may be disposed in sequential contiguous relationship within a pillar or fin configuration that may extend vertically from and/or perpendicularly to a plane defined by an N-well region128and/or an P− substrate130. In an exemplary embodiment, the P− region122may be an electrically floating body region of the memory cell12configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the word line (WL)28.

Referring toFIG. 9, there is shown a cross-sectional view of two memory cells12along a column direction of the memory cell array20shown inFIG. 8in accordance with a first alternative embodiment of the present disclosure. As discussed above with respect toFIG. 8, each of the memory cells12may comprise a bipolar transistor14aand a PN junction diode14bcoupled to each other. For example, the bipolar transistor14amay be an NPN bipolar transistor or an PNP bipolar transistor. As illustrated inFIG. 9, the bipolar transistor14amay be an NPN bipolar transistor and may share a common region (e.g., N-region) with the PN junction diode14b. In another exemplary embodiment, the memory transistor14amay be an PNP bipolar transistor and may share a common region (e.g., P-region) with the PN junction diode14b.

Referring toFIG. 10, there is shown a schematic diagram of at least a portion of the memory cell array20having the plurality of memory cells12in accordance with a second alternative embodiment of the present disclosure. For example, the memory cell array20shown inFIG. 10may be implemented with the structure and techniques similar to that of the memory cell array20shown inFIG. 2, except that each of the memory cells12may comprise a bipolar transistor14aand a metal-oxide-semiconductor field-effect transistor (MOSFET)14bcoupled to each other. For example, the bipolar transistor14amay be an NPN bipolar transistor or an PNP bipolar transistor. The metal-oxide-semiconductor field-effect transistor (MOSFET)14bmay be a N-type metal-oxide-semiconductor field-effect transistor (MOSFET) or a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

As illustrated inFIG. 10, the bipolar transistor14amay be an NPN bipolar transistor and the metal-oxide-semiconductor field-effect transistor (MOSFET)14bmay be an P-type metal-oxide-semiconductor field-effect transistor (MOSFET). Each memory cell12may be coupled to a respective word line (WL)28, a respective source line (CN)30, a respective bit line (EN)32, a respective carrier injection line (EP)34, and a respective field-effect transistor (FET) word line (WL-FET)40. Data may be written to or read from a selected memory cell12by applying suitable control signals to a selected word line (WL)28, a selected source line (CN)30, a selected bit line (EN)32, a selected carrier injection line (EP)34, and/or a field-effect transistor (FET) word line (WL-FET)40. In an exemplary embodiment, each word line (WL)28, each source line (CN)30, each carrier injection line (EP)34, and each field-effect transistor (FET) word line (WL-FET)40may extend horizontally parallel to each other in a row direction. Each bit line (EN)32may extend vertically in a column direction perpendicular to each word line (WL)28, source line (CN)30, carrier injection line (EP)34, and/or field-effect transistor (FET) word line (WL-FET)40.

A data state may be read from one or more selected memory cells12by applied one or more control signals. A voltage and/or a current may be generated by the one or more selected memory cells12and outputted to the data write and sense circuitry36via a corresponding bit line (EN)32in order to read a data state stored in each selected memory cell12. Also, a data state may be written to one or more selected memory cells by applying one or more control signals to one or more selected memory cells12via a selected word line (WL)28, a selected source line (CN)30, a selected bit line (EN)32, a selected carrier injection line (EP)34, and/or a selected field-effect transistor (FET) word line (WL-FET)40. The one or more control signals applied to one or more selected memory cells12via a selected word line (WL)28, a selected source line (CN)30, a selected bit line (EN)32, a selected carrier injection line (EP)34, and/or a selected field-effect transistor (FET) word line (WL-FET)40may control each selected memory cell12in order to write a desired data state to each selected memory cell12.

Referring toFIG. 11, there is shown a cross-sectional view of two memory cells12along a column direction of the memory cell array20shown inFIG. 10in accordance with an embodiment of the present disclosure. As discussed above, each memory cell12may comprise a bipolar transistor14aand a metal-oxide-semiconductor field-effect transistor (MOSFET)14b. In an exemplary embodiment, the first bipolar transistor14amay be a NPN bipolar transistor and the metal-oxide-semiconductor field-effect transistor (MOSFET)14bmay be a P-type metal-oxide-semiconductor field-effect transistor (MOSFET). In an exemplary embodiment, the bipolar transistor14aand the metal-oxide-semiconductor field-effect transistor (MOSFET)14bmay share one or more common regions. The NPN bipolar transistor14amay comprise an N+ emitter region120, a P− base region122, and an N+ collector region124. The P-type metal-oxide-semiconductor field-effect transistor (MOSFET)14bmay comprise the P− drain region122, the N+ gate region124, and an P+ source region126. The N+ region120, the P− region122, the N+ region124, and/or the P+ region126may be disposed in sequential contiguous relationship within a pillar or fin configuration that may extend vertically to a plane defined by an N-well region128and/or an P− substrate130. In an exemplary embodiment, the P− region122may be an electrically floating body region of the memory cell12configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the word line (WL)28.

As shown inFIG. 11, the N+ region124of the memory cell12may be coupled to a source line (CN)30. In an exemplary embodiment, the source line (CN)30may be configured on a side of the N+ region124of the memory cell12. In another exemplary embodiment, the field-effect transistor (FET) word line (WL-FET)40may be capacitively coupled to the N+ region124. The source line (CN)30may be disposed between the N+ region124and the field-effect transistor (FET) word line (WL-FET)40. For example, the field-effect transistor (FET) word line (WL-FET)40may circumferentially surround the N+ region124. The field-effect transistor (FET) word line (WL-FET))40may be formed of a polycide layer or a metal layer extending in a row direction of the memory cell array20. The field-effect transistor (FET) word line (WL-FET)40may extend horizontally in parallel to the word line (WL)28, the source line (CN)30, and/or the carrier injection line (EP)34, and may be coupled to a plurality of memory cells12(e.g., a row of memory cells12). For example, the field-effect transistor (FET) word line (WL-FET)40and the word line (WL)28and/or the carrier injection line (EP)34may be arranged in different planes and configured to be parallel to each other. The field-effect transistor (FET) word line (WL-FET)40may be arranged in a same plane as the source line (CN)30. In an exemplary embodiment, the field-effect transistor (FET) word line (WL-FET)40may be arranged in a plane between a plane containing the word line (WL)28and a plane containing the carrier injection line (EP)34.

Referring toFIG. 12, there is shown a schematic diagram of at least a portion of the memory cell array20having the plurality of memory cells12in accordance with a third alternative embodiment of the present disclosure. For example, the memory cell array20shown inFIG. 12may be implemented with the structure and techniques similar to that of the memory cell array20shown inFIG. 2, except that each of the memory cells12may comprise a bipolar transistor14aand a junction gate field-effect transistor (JFET)14bcoupled to each other. For example, the bipolar transistor14amay be an NPN bipolar transistor or an PNP bipolar transistor. The junction gate field-effect transistor (JFET)14bmay be a N-channel junction gate field-effect transistor (JFET) or a P-channel junction gate field-effect transistor (JFET). As illustrated inFIG. 12, the bipolar transistor14amay be an NPN bipolar transistor and the junction gate field-effect transistor (JFET)14bmay be a P-channel junction gate field-effect transistor (JFET). In another exemplary embodiment, the bipolar transistor14amay be an PNP bipolar transistor and the junction gate field-effect transistor14bmay be a N-channel junction gate field-effect transistor (JFET).

Each memory cell12may be coupled to a respective word line (WL)28, a respective source line (CN)30, a respective bit line (EN)32, and a respective carrier injection line (EP)34. Data may be written to or read from a selected memory cell12by applying suitable control signals to a selected word line (WL)28, a selected source line (CN)30, a selected bit line (EN)32, and/or a selected carrier injection line (EP)34. In an exemplary embodiment, each word line (WL)28, each source line (CN)30, and carrier injection line (EP)34may extend horizontally parallel to each other in a row direction. Each bit line (EN)32may extend vertically in a column direction perpendicular to each word line (WL)28, source line (CN)30, and/or carrier injection line (EP)34.

Referring toFIG. 13, there is shown a cross-sectional view of two memory cells12along a column direction of the memory cell array20shown inFIG. 12in accordance with a third alternative embodiment of the present disclosure. As discussed above, each memory cell12may comprise a bipolar transistor14aand a junction gate field-effect transistor (JFET)14b. In an exemplary embodiment, the bipolar transistor14amay be a NPN bipolar transistor and the junction gate field-effect transistor (JFET)14bmay be a P-channel junction gate field-effect transistor (JFET). In an exemplary embodiment, the bipolar transistor14aand the junction gate field-effect transistor14bmay share one or more common regions. The NPN bipolar transistor14amay comprise an N+ emitter region120, a P− base region122, and an N+collector region124. The P-channel junction gate field-effect transistor14bmay comprise the P− drain region122, the N+ gate region124, and an P+ source region126. The N+ region120, the P− region122, the N+ region124, and/or the P+ region126may be disposed in sequential contiguous relationship within a pillar or fin configuration that may extend vertically to a plane defined by an N-well region128and/or an P− substrate130. In an exemplary embodiment, the P− region122may be an electrically floating body region of the memory cell12configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the word line (WL)28.

As also shown inFIG. 13, the P− region122may be capacitively coupled to a corresponding word line (WL)28. In an exemplary embodiment, at least a portion of the P− region122may be directly coupled with the P+ region126. In another exemplary embodiment, the N+ region124may be disposed between a portion of the P− region122and the P+ region126. In other exemplary embodiments, the P− region122may be arranged to cover one or more side portions of the N+ region124. As further shown inFIG. 3, the N+ region124of the memory cell12may be coupled to a source line (CN)30. The source line (CN)30may be directly connected to a portion of the N+ region124of the memory cell12.

At this point it should be noted that providing a direct injection semiconductor memory device having ganged carrier injection lines in accordance with the present disclosure as described above typically involves the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, specific electronic components may be employed in a direct injection semiconductor memory device or similar or related circuitry for implementing the functions associated with providing a direct injection semiconductor memory device having ganged carrier injection lines in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with providing a direct injection semiconductor memory device having ganged carrier injection lines in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more processor readable media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves.