Systems and methods for soft decision generation in a solid state memory system

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory, a data de-randomizer circuit operable to de-randomize a read data set accessed from the solid state memory device, a soft data generation circuit operable to receive multiple instances of one or more elements the read data set and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to apply a soft decoding algorithm to the soft data to yield a decoded output. Each instance of a respective element may be read using a different reference value.

FIELD OF THE INVENTION

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.

BACKGROUND

Data in a solid state storage device decays over time requiring more error correction capability over time. To correct additional errors, enhanced error correction circuitry may be employed. However, such enhanced error correction circuitry increases access latency.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for maintaining data in a solid state storage device.

SUMMARY

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.

Various embodiments of the present invention provide data processing systems that include: a solid state memory, a data de-randomizer circuit, a soft data generation circuit, and a data decoder circuit. The data de-randomizer circuit operable to de-randomize a read data set accessed from the solid state memory device. The soft data generation circuit is operable to: receive multiple instances of one or more elements the read data set, where each instance of a respective element is read using a different reference value; and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data. The data decoder circuit is operable to apply one or more iterations of a data decoding algorithm to the soft data to yield a decoded output.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.

Various embodiments of the present invention provide data processing systems that include: a solid state memory, a data de-randomizer circuit, a soft data generation circuit, and a data decoder circuit. The data de-randomizer circuit operable to de-randomize a read data set accessed from the solid state memory device. The soft data generation circuit is operable to: receive multiple instances of one or more elements the read data set, where each instance of a respective element is read using a different reference value; and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data. The data decoder circuit is operable to apply a soft data decoding algorithm to the soft data to yield a decoded output. In some cases, the data decoding algorithm is a low density parity check decoding algorithm. In various cases, the data processing system is implemented on an integrated circuit. In one or more cases, the solid state memory is a flash memory.

In various instances of the aforementioned embodiments, the solid state memory is a single bit per cell flash memory. In some such instances, the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the one or more elements. A first portion of the soft data values correspond to data unmodified by the de-randomizer circuit, and a second portion of the soft data values correspond to data modified by the de-randomizer circuit.

In other instances of the aforementioned embodiments, the solid state memory is a multi-bit bit per cell flash memory, wherein the multiple instances of one or more elements the read data set include a first set of instances corresponding to a first bit in a cell of the multi-bit bit per cell flash memory, and a second set of instances corresponding to a second bit in the cell of the multi-bit bit per cell flash memory. In some such instances, the scramble compensating extended look up table includes a first set of soft data values corresponding to different possible values for the first set of instances, and a second set of soft data values corresponding to different possible values for the second set of instances. In some cases, the first portion of the first set of soft data values corresponds to data unmodified by the de-randomizer circuit, and a second portion of the first set of soft data values corresponds to data modified by the de-randomizer circuit. The second portion of the soft data values corresponds to either data modified by the de-randomizer circuit, or data unmodified by the de-randomizer circuit.

Other embodiments of the present invention provide methods for recovering data from a solid state memory device. The methods include: repeatedly accessing a cell of a solid state memory device using different reference voltage values yield multiple instances of a read; applying a de-randomizer algorithm using a de-randomizer circuit to each of the multiple instances of the read to yield corresponding de-randomized instances; and accessing a scramble compensating extended look up table using the de-randomized instances to receive corresponding soft data. In some cases, the methods further include applying a low density parity check decoding algorithm to the soft data to yield a decoded output.

In some instances of the aforementioned embodiments, the solid state memory is a single bit per cell flash memory. In some such instances, the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the one or more elements. A first portion of the soft data values correspond to data unmodified by the de-randomizer circuit, and a second portion of the soft data values correspond to data modified by the de-randomizer circuit.

In other instances of the aforementioned embodiments, the solid state memory is a multi-bit per cell flash memory, wherein the multiple instances of one or more elements the read data set include a first set of instances corresponding to a first bit in a cell of the multi-bit bit per cell flash memory, and a second set of instances corresponding to a second bit in the cell of the multi-bit bit per cell flash memory. In some such instances, the scramble compensating extended look up table includes a first set of soft data values corresponding to different possible values for the first set of instances, and a second set of soft data values corresponding to different possible values for the second set of instances. In some cases, the first portion of the first set of soft data values corresponds to data unmodified by the de-randomizer circuit, and a second portion of the first set of soft data values corresponds to data modified by the de-randomizer circuit. The second portion of the soft data values corresponds to either data modified by the de-randomizer circuit, or data unmodified by the de-randomizer circuit.

Turning toFIG. 1, a solid state storage device100including a soft data generation circuit180relying on a scramble compensating extended look up table186operable to compensate for internal randomizing circuitry in accordance with various embodiments of the present invention. Storage device100includes a host controller circuit160that directs read and write access to a solid stat memory device196. Solid state memory device196includes flash memory cells140that may be NAND flash memory cells or another type of solid state memory cells as are known in the art. Flash memory cells140are accessed via randomization circuitry that includes an internal randomizer circuit192and an internal de-randomizer circuit193. Internal randomizer circuit192randomizes write data194to yield randomized write data125that is provided to a write circuit130. In turn, write circuit converts randomized write data to a series corresponding write voltages135that are stored to flash memory cells at locations indicated by an address123. A read circuit150receives previously stored data as a series of read voltages145from locations indicated by address123, and converts read voltages145into corresponding randomized read data155. Randomized read data155is provided to internal de-randomizer circuit193that reverses the randomization originally applied by internal randomizer circuit192to yield read data195.

Referring toFIG. 4, one implementation of a combination of a randomizer and de-randomizer circuit is shown in accordance with various embodiments of the present invention. The randomizer and de-randomizer circuit includes a randomizer circuit405and a de-randomizer circuit455. Randomizer circuit405may be used in place of internal randomizer circuit192, and de-randomizer circuit455may be used in place of internal de-randomizer circuit193. As shown, randomizer circuit405includes a pseudo-random number generator412operable to generate a pseudo-random series of inputs to an XOR circuit414based upon a seed401. XOR circuit414applies an exclusive OR function to the pseudo-random numbers and the write data403to yield random data output407. As shown, de-randomizer circuit455includes a pseudo-random number generator422operable to generate a pseudo-random series of inputs to an XOR circuit424based upon seed401. XOR circuit424applies an exclusive OR function to the pseudo-random numbers and the read data457to yield data output409.

A data write is effectuated when host controller circuit160provides write data105to be written along with an address110indicating the location to be written. A memory access controller circuit120receives write data105and address110. Memory access controller120formats write data105and provides address123and an encoded data set as write data194to internal randomizer circuit192. As discussed above, internal randomizer circuit192randomizes the received data to yield write data125that is provided to a write circuit130. Write circuit130provides write voltage135corresponding to respective groupings of encoded write data125. For example, where flash memory cells are two bit cells (i.e., depending upon the read voltage, a value of ‘11’, ‘10’, ‘00’, or ‘01’ is returned), encoded write data125may be converted to one of four voltages as set forth in the following table:

Two Bit Data InputVoltage Output‘01’V3‘00’V2‘10’V1‘11’V0
Where V3 is greater than V2, V2 is greater than V1, and V1 is greater than V0.

A data read is effectuated when host controller circuit160provides address110along with a request to read data from the corresponding location in flash memory cells140. Memory access controller120provides address123as the location from which the data is to be read. In turn, flash memory cells140provides read voltages145from locations indicated by address123to read circuit150that converts the voltages to a series of randomized read data155. Using the same two bit example, the following multi-bit read data155results:

Voltage InputTwo Bit Data Output>VD‘01’>VC‘00’>VB‘10’<=VA‘11’
Where VD is greater than VC, VC is greater than VB, and VB is greater than VB. This multi-bit read data155is provided from memory access controller120as read data107to a data buffer circuit170.

In order to generate soft data for the particular location being read, the location is read multiple times, each time using a different threshold value by read circuit150to determine the actual level of read voltage145for the location. This results in multiple binary values being stored to data buffer circuit170for the particular location in flash memory cells140. In one particular embodiment of the present invention, each location is read five times, each time using a different threshold value by read circuit150to convert the data.

Turning toFIG. 5, an example of this multi-read process is shown. A voltage diagram500shows the voltage distributions of a two bit memory cell with each of the voltage distributions representing a different state (i.e., erase, state P1, state P2, state P3). Using the example in the table above, the erase state P3 corresponds to an output value from read circuit150of ‘11’, state P1 corresponds to an output value from read circuit150of ‘10’, state P2 corresponds to an output value from read circuit150of ‘00’, and state P3 corresponds to an output value from read circuit150of ‘01’.

Another voltage diagram550shows voltage diagram500where multiple threshold values (R1, R2, R3, R4, R5) are used to read the lower page (least significant bit) of the cell. In this case, assume the cell is programmed to be state P1 (‘01’), then successively reading the cell while successively changing the reference voltage used by read circuit150from R1 to R5 the values read extend from ‘1’ in a region A to a ‘0’ in region F as shown in the following table:

RepresentedR1R2R3R4R5RegionSoft Data11111ALLR_A (7)01111BLLR_B (4)00111CLLR_C (2)00011DLLR_D (−1)00001ELLR_E (−3)00000FLLR_F (−6)
The soft data values (LLR_A, LLR_B, LLR_C, LLR_D, LLR_E, and LLR_F) are used to map the results of the series of reads to soft data.

The aforementioned table assumes that the data written to the location is actually state P1 data. This may not be the case as internal randomizer circuit may have inverted the data. In such a case, the data may be one of the other states. Where the least significant bit was inverted (i.e., from a ‘1’ in the expected state P1 to a ‘0’ in the inverted state), the following reversed table would result from the multiple read:

RepresentedR1R2R3R4R5RegionSoft Data00000A??10000B??11000C??11100D??11110E??11111F??
The reversal of the table requires a different approach to assigning soft data values. Of note, where it is not known whether an inversion was applied by internal randomizer circuit192, the results from reading region A and region F are ambiguous, which is not particularly harmful to the soft decoder because region A and region F are usually assigned saturated LLR values. However, the results of from reading region B, region C, region D and region E can be discerned between the inverted and non-inverted condition. Using the lack of ambiguity as to the center regions (i.e., region B, region C, region D and region E) and the known increment from R1 to R5, the ambiguity of region A and region B can be resolved allowing for the assignment of soft data to each of the results possible in an inverted situation. These results are used to extend the table of soft data as follows:

RepresentedR1R2R3R4R5RegionSoft Data11111ALLR_A (7)01111BLLR_B (4)00111CLLR_C (2)00011DLLR_D (−1)00001ELLR_E (−3)00000FLLR_F (−6)10000BLLR_B (−4)11000CLLR_C (−2)11100DLLR_D (1)11110ELLR_E (3)
Of note, the magnitude for the soft data for corresponding regions is maintained because they originate from the same decision region (e.g., LLR_B(4) and LLR_B(−4)). However, the sign of the soft data is flipped (e.g., LLR_B(4) and LLR_B(−4)) because the soft data as the soft data is provided to a data processing circuit174that occurs after internal de-randomizer circuit193has reversed the prior bit inversion. This extended table is maintained as a map in a scramble compensating extended look up table186.

Another voltage diagram580shows voltage diagram500where multiple threshold values (R1, R2, R3, R4, R5) are used to read the upper page (in this example, also most significant bit) of the cell. In this case, assume the cell is programmed to be state P3 (‘10’), then successively reading the cell while successively changing the reference voltage used by read circuit150from R1 to R5 the values read extend from ‘1’ in a region A to a ‘0’ in region F as shown in the following table:

In the case of the upper page read, when an unknown randomization is applied by internal randomizer circuit192, ambiguity can occur between a number of the states A-J, and not just in states A and F as was the case in reading the lower page making it impossible to resolve the ambiguity without knowing whether or not the data was inverted by internal randomizer circuit192. Because it is not possible to resolve the ambiguity, the table for the upper page (i.e., most significant bit) is not extended. This upper page table is included with the extended lower page table in scramble compensating extended look up table186.

Referring again toFIG. 1, a soft data generation circuit180provides a read control output184to memory access controller circuit120that causes a repeated read of the location similar to that discussed above in relation toFIG. 5. The binary results of the repeated reads are received as read data107and stored to data buffer circuit170. The series of values for each location are accessed by soft data generation circuit180from data buffer circuit170. The combination of the read inputs accessed from data buffer circuit170are used to access scramble compensating extended look up table186which returns the corresponding soft data. Soft data generation circuit180provides the soft data retrieved from scramble compensating extended look up table186that maps to the series of values for each location read from flash memory cells140back to data buffer circuit170.

A data processing circuit174receives soft data178from data buffer circuit170and applies data processing thereto to correct any errors and yield the originally written data as read data175to the requesting host controller circuit160. Turning toFIG. 3, implementation of a data processing circuit300is shown that may be used in place of data processing circuit174in some embodiments of the present invention. Where data processing circuit300is used in place of data processing circuit174ofFIG. 1, soft data178is connected to a memory data325input, and read data175is connected to a hard decision output392.

Data processing circuit300receives memory data325where it is stored to a central memory circuit350. Once a decoder circuit370is available, a previously stored data set325is accessed from central memory circuit350as a decoder input352. In some embodiments of the present invention, the decoder circuit370is a low density parity check decoder circuit as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of decoder circuits that may be used in relation to various embodiments of the present invention. Decoder circuit370applies a data decoding algorithm to decoder input352to yield a decoded output371. Where decoded output371fails to converge (i.e., decoded output371includes errors), another iteration of the data decoding algorithm is applied to decoder input352guided by decoded output371. This process is repeated until either decoded output371converges (i.e., is error free) or a timeout condition is met. Alternatively, where decoded output371converges, it is provided as a decoded output372to a hard decision buffer circuit390. Hard decision buffer circuit390provides the hard decisions of decoded output372as a hard decision output392.

It should be noted that in some cases, solid state storage device100includes standard solid state data access circuitry including an error correction decoding circuit (not shown). In such cases, soft data generation circuit180and data processing circuit174may only operate when the standard data access circuitry fails to yield an error free result. Thus, standard access to flash memory cells140may be applied first, and when it fails, the combination of soft data generation circuit180and data processing circuit174apply soft data based processing in an attempt to recover the data.

Turning toFIG. 2, a solid state storage device200including a soft data generation circuit280relying on a scramble compensating extended look up table286operable to compensate for external randomizing circuitry in accordance with various embodiments of the present invention. Storage device200includes a host controller circuit260that directs read and write access to a solid stat memory device296. Solid state memory device296includes flash memory cells240that may be NAND flash memory cells or another type of solid state memory cells as are known in the art. Flash memory cells240are accessed via a solid state Plccess circuit297that includes a memory access controller circuit220, a write circuit230and a read circuit250.

Write data205is provided from host controller circuit260via an external randomizing circuit292that yields randomized write data194that is provided to memory access controller circuit220. Read data207is provided from memory access controller circuit220via an external de-randomizer circuit293. In particular, external de-randomizer circuit293receives randomized read data295and reverses the randomization originally applied by external randomizer circuit292to yield read data207.

Referring toFIG. 4, one implementation of a combination of a randomizer and de-randomizer circuit is shown in accordance with various embodiments of the present invention. The randomizer and de-randomizer circuit includes randomizer circuit405and de-randomizer circuit455. Randomizer circuit405may be used in place of external randomizer circuit292, and de-randomizer circuit455may be used in place of external de-randomizer circuit293. As shown, randomizer circuit405includes a pseudo-random noise generator412operable to generate a pseudo-random series of inputs to an XOR circuit414based upon a seed401. XOR circuit414applies an exclusive OR function to the pseudo-random numbers and the write data403to yield random data output407. As shown, de-randomizer circuit455includes a pseudo-random number generator422operable to generate a pseudo-random series of inputs to an XOR circuit424based upon seed401. XOR circuit424applies an exclusive OR function to the pseudo-random numbers and the read data457to yield data output409.

A data write is effectuated when host controller circuit260provides write data205to be written along with an address210indicating the location to be written. External randomizer circuit292randomizes the received data and provides randomized write data294to memory access controller circuit220. Memory access controller220formats randomized write data294and provides an address223and an encoded write data225to write circuit230. Write circuit230provides a write voltage235corresponding to respective groupings of encoded write data225that is used to charge respective flash memory cells addressed by address223. For example, where flash memory cells are two bit cells (i.e., depending upon the read voltage, a value of ‘11’, ‘10’, ‘00’, or ‘01’ is returned), the following voltages may be applied to store the data:

Two Bit Data InputVoltage Output‘01’V3‘00’V2‘10’V1‘11’V0
Where V3 is greater than V2, V2 is greater than V1, and V1 is greater than V0.

A data read is effectuated when host controller circuit260provides address210along with a request to read data from the corresponding location in flash memory cells240. Memory access controller220accesses a read voltage245from locations indicated by address223and compares the voltage to a threshold value to reduce the voltage to a multi-bit read data255. Using the same two bit example, the following multi-bit read data255results:

Voltage InputTwo Bit Data Output>VD‘01’>VC‘00’>VB‘10’<=VA‘11’
This multi-bit read data255is provided from memory access controller220as randomized read data295to external de-randomizer circuit293. External de-randomizer circuit293de-randomizes the received data to yield read data207. Read data207is stored to a data buffer circuit270.

In order to generate soft data for the particular location being read, the location is read multiple times, each time using a different threshold value by read circuit250to determine the actual level of read voltage245for the location. This results in multiple binary values being stored to data buffer circuit270for the particular location in flash memory cells240. In one particular embodiment of the present invention, each location is read five times, each time using a different threshold value by read circuit250to convert the data.

Turning toFIG. 5, an example of this multi-read process is shown. Voltage diagram500shows the voltage distributions of a two bit memory cell with each of the voltage distributions representing a different state (i.e., erase, state P1, state P2, state P3). Using the example in the table above, the erase state P3corresponds to an output value from read circuit250of ‘11’, state P1 corresponds to an output value from read circuit250of ‘10’, state P2 corresponds to an output value from read circuit250of ‘00’, and state P3 corresponds to an output value from read circuit250of ‘01’.

Another voltage diagram550shows voltage diagram500where multiple threshold values (VTHA, VTHB, VTHC, VTHD, VTHE) are used to read the lower page (least significant bit) of the cell. In this case, assume the cell is programmed to be state P1 (‘01’), then successively reading the cell while successively changing the reference voltage used by read circuit250from VTHA to VTHE the values read extend from ‘1’ in a region A to a ‘0’ in region F as shown in the following table:

The aforementioned table assumes that the data written to the location is actually state P1 data. This may not be the case as internal randomizer circuit may have inverted the data. In such a case, the data may be one of the other states. Where the least significant bit was inverted (i.e., from a ‘1’ in the expected state P1 to a ‘0’ in the inverted state), the following reversed table would result from the multiple read:

RepresentedVTHAVTHBVTHCVTHDVTHERegionSoft Data00000A??10000B??11000C??11100D??11110E??11111F??
The reversal of the table requires a different approach to assigning soft data values. Of note, where it is not known whether an inversion was applied by external randomizer circuit292, the results from reading region A and region F are ambiguous. However, the results of from reading region B, region C, region D and region E can be discerned between the inverted and non-inverted condition. Using the lack of ambiguity as to the center regions (i.e., region B, region C, region D and region E) and the known increment from VTHA to VTHE, the ambiguity of region A and region B can be resolved allowing for the assignment of soft data to each of the results possible in an inverted situation. These results are used to extend the table of soft data as follows:

Another voltage diagram580shows voltage diagram500where multiple threshold values (VTHA, VTHB, VTHC, VTHD, VTHE) are used to read the upper page (most significant bit) of the cell. In this case, assume the cell is programmed to be state P3 (‘10’), then successively reading the cell while successively changing the reference voltage used by read circuit250from VTHA to VTHE the values read extend from ‘1’ in a region A to a ‘0’ in region F as shown in the following table:

Referring again toFIG. 2, in the case of the upper page read, when an unknown randomization is applied by external randomizer circuit292, ambiguity can occur between a number of the states A-J, and not just in states A and F as was the case in reading the lower page making it impossible to resolve the ambiguity without knowing whether or not the data was inverted by external randomizer circuit292. Because it is not possible to resolve the ambiguity, the table for the upper page (i.e., most significant bit) is not extended. This upper page table is included with the extended lower page table in scramble compensating extended look up table286.

Referring again toFIG. 2, a soft generation circuit280provides a read control output284to memory access controller circuit220that causes a repeated read of the location similar to that discussed above in relation toFIG. 5. The binary results of the repeated reads are received as read data207and stored to data buffer circuit270. The series of values for each location are accessed by soft data generation circuit280from data buffer circuit270. The combination of the read inputs accessed from data buffer circuit270are used to access scramble compensating extended look up table286which returns the corresponding soft data. Soft data generation circuit280provides the soft data retrieved from scramble compensating extended look up table286that maps to the series of values for each location read from flash memory cells240back to data buffer circuit270.

A data processing circuit274receives soft data278from data buffer circuit270and applies data processing thereto to correct any errors and yield the originally written data as read data275to the requesting host controller circuit260. Turning toFIG. 3, implementation of a data processing circuit300is shown that may be used in place of data processing circuit274in some embodiments of the present invention. Where data processing circuit300is used in place of data processing circuit274ofFIG. 1, soft data278is connected to a memory data325input, and read data275is connected to a hard decision output392.

Data processing circuit300receives memory data325where it is stored to a central memory circuit350. Once a decoder circuit370is available, a previously stored data set325is accessed from central memory circuit350as a decoder input352. In some embodiments of the present invention, the decoder circuit370is a low density parity check decoder circuit as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of decoder circuits that may be used in relation to various embodiments of the present invention. Decoder circuit370applies a data decoding algorithm to decoder input352to yield a decoded output371. Where decoded output371fails to converge (i.e., decoded output371includes errors), another iteration of the data decoding algorithm is applied to decoder input352guided by decoded output371. This process is repeated until either decoded output371converges (i.e., is error free) or a timeout condition is met. Alternatively, where decoded output371converges, it is provided as a decoded output372to a hard decision buffer circuit390. Hard decision buffer circuit390provides the hard decisions of decoded output372as a hard decision output392.

It should be noted that in some cases, solid state storage device200includes standard solid state data access circuitry including an error correction decoding circuit (not shown). In such cases, soft data generation circuit280and data processing circuit274may only operate when the standard data access circuitry fails to yield an error free result. Thus, standard access to flash memory cells240may be applied first, and when it fails, the combination of soft data generation circuit280and data processing circuit274apply soft data based processing in an attempt to recover the data.

Turning toFIG. 6, a flow diagram600shows a method in accordance with some embodiments of the present invention for data processing using soft data generated using an extended look up table designed to account for read/write randomization. Following flow diagram600, it is determined whether a read request is received (block605). Where a read request is not received (block605), it is determined whether a write request has been received (block695). Where a write request is received (block695), data received is randomized, formatted and written to a location in the flash memory indicated by an address received as part of the write request (block697), and the process returns to block605.

Alternatively, when a read access is received (block605), it includes an address indicating a location from which the data is to be accessed. Data is then accessed from the flash memory at the location indicated by the read request (block610). As the data was randomized when it was written to the flash memory, the read data is in a scrambled form. The randomized read data is de-randomized by either an internal or external de-randomizing circuit, and standard error correction decoding is applied to correct one or more errors that exist in the data (block615). It is determined whether the resulting data is error free (block620). Where it is determined that the data is error free (block620), the retrieved data is provided as read data (block625). The process then returns to block605.

Otherwise, where it is determined that the data is not error free (block620), the cells of the flash memory corresponding to the failed data is repeatedly read using different reference values to yield multiple output values (block630). Turning toFIG. 5, an example of this multi-read process is shown. Voltage diagram500shows the voltage distributions of a two bit memory cell with each of the voltage distributions representing a different state (i.e., erase, state P1, state P2, state P3). Using the example in the table above, the erase state P3 corresponds to an output value from a read circuit of ‘11’, state P1 corresponds to an output value from the read circuit of ‘10’, state P2 corresponds to an output value from the read circuit of ‘00’, and state P3 corresponds to an output value from the read circuit of ‘01’.

Another voltage diagram550shows voltage diagram500where multiple threshold values (R1, R2, R3, R4, R5) are used to read the lower page (least significant bit) of the cell. In this case, assume the cell is programmed to be state P1 (‘01’), then successively reading the cell while successively changing the reference voltage used by the read circuit from R1 to R5 the values read extend from ‘1’ in a region A to a ‘0’ in region F as shown in the following table:

RepresentedR1R2R3R4R5RegionSoft Data11111ALLR_A (7)01111BLLR_B (4)00111CLLR_C (2)00011DLLR_D (−1)00001ELLR_E (−3)00000FLLR_F (−6)
The soft data values (LLR_A, LLR_B, LLR_C, LLR_D, LLR_E, and LLR_F) are used to map the results of the series of reads to soft data.

The aforementioned table assumes that the data written to the location is actually state P1 data. This may not be the case as a randomizer circuit may have inverted the data. In such a case, the data may be one of the other states. Where the least significant bit was inverted (i.e., from a ‘1’ in the expected state P1 to a ‘0’ in the inverted state), the following reversed table would result from the multiple read:

RepresentedR1R2R3R4R5RegionSoft Data00000A??10000B??11000C??11100D??11110E??11111F??
The reversal of the table requires a different approach to assigning soft data values. Of note, where it is not known whether an inversion was applied by a randomizer circuit, the results from reading region A and region F are ambiguous. However, the results of from reading region B, region C, region D and region E can be discerned between the inverted and non-inverted condition. Using the lack of ambiguity as to the center regions (i.e., region B, region C, region D and region E) and the known increment from R1 to R5, the ambiguity of region A and region B can be resolved allowing for the assignment of soft data to each of the results possible in an inverted situation. These results are used to extend the table of soft data as follows:

RepresentedR1R2R3R4R5RegionSoft Data11111ALLR_A (7)01111BLLR_B (4)00111CLLR_C (2)00011DLLR_D (−1)00001ELLR_E (−3)00000FLLR_F (−6)10000BLLR_B (−4)11000CLLR_C (−2)11100DLLR_D (1)11110ELLR_E (3)
Of note, the magnitude for the soft data for corresponding regions is maintained because they originate from the same state (e.g., LLR_B(4) and LLR_B(−4)). However, the sign of the soft data is flipped (e.g., LLR_B(4) and LLR_B(−4)) because the soft data as the soft data is provided to a data processing circuit that occurs after the de-randomizer circuit has reversed the prior bit inversion. This extended table is maintained as a map in a scramble compensating extended look up table.

Another voltage diagram580shows voltage diagram500where multiple threshold values (R1, R2, R3, R4, R5) are used to read the upper page (most significant bit) of the cell. In this case, assume the cell is programmed to be state P3 (‘10’), then successively reading the cell while successively changing the reference voltage used by the read circuit from R1 to R5 the values read extend from ‘1’ in a region A to a ‘0’ in region F as shown in the following table:

Referring again toFIG. 6, the multiple output values are used to access a scramble compensating extended look up table similar to that described above in relation toFIG. 5(block635). Accessing the scramble compensating extended look up table returns soft data values for each of the combinations of multiple output values. This soft data accessed from the scramble compensating extended look up table is stored to a central memory circuit (block640). It is then determined whether a data decoder circuit is available for processing the soft data (block650). Where the data decoder circuit is available for processing (block650), a previously stored soft data set is accessed from the central memory as a decoder input (block655). A data decoding algorithm is applied to the accessed soft data set to yield a decoded output (block660). Where available (i.e., for the second and later iterations), a previous decoded output is used to guide application of the data decoding algorithm. In some embodiments of the present invention, the data decoding algorithm is a low density parity check decoding algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoding algorithms that may be used in relation to different embodiments of the present invention.

It is determined whether the decoded output converged (block665). Where it is determined that the decoded output converged (block665), the decoded output is provided as read data (block670) and the process returns to block605. Alternatively, where it is determined that the decoded output failed to converge (block665). It is determined whether another iteration of the data decoding algorithm is allowed (block675). In some cases, a maximum number of iterations of the data decoding algorithm is fixed or programmable. This is effectively a timeout condition. In some cases, the maximum number of allowable iterations of the data decoding algorithm is one hundred. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other numbers of iterations that may be allowed in relation to different embodiments of the present invention. Where another local iteration is not allowed (block675), an error is indicated (block680), and the process returns to block605. Otherwise, where another iteration of the decoding algorithm is allowed (block675), the processes of blocks660-675are repeated.