SEMICONDUCTOR DEVICE, BATTERY MANAGEMENT SYSTEM AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE

In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.

BACKGROUND

A semiconductor package may include one or more semiconductor devices in a housing. The package may include a substrate or a leadframe which includes outer contacts which are used to mount the electronic component on a redistribution board such as a printed circuit board. The package also includes internal electrical connections from the semiconductor device to the substrate or leadframe. The housing may include a plastic molding compound which covers the semiconductor device and the internal electrical connections.

In order to reduce the size of the semiconductor package, so called chip sized/chip-scale packages have been developed. Chip sized packages may be fabricated by manufacturing a semiconductor wafer which comprises a plurality of semiconductor devices at component positions in the wafer and a non-device region, also known as a saw street or kerf or singulation region. The non-device regions may surround each device region and delineate the component positions. Typically, the device regions are formed in a regular array of rows and columns so that the non-device regions have the form of an orthogonal grid. After forming the relevant components of the device, the wafer is separated into single chips or dies, for example by dicing the wafer, for example by sawing, through the thickness of the wafer along the non-device regions.

WO 2017/148873 A1 discloses a method in which a trench is formed in the first surface of the semiconductor wafer in the non-device regions between the component positions. A first polymer layer is applied to the first surface such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer. Portions of the second opposing surface of the semiconductor wafer are removed to reveal portions of the first polymer layer in the non-device regions and the wafer is singulated by cutting through the first polymer layer in the non-device regions.

Further improvements to semiconductor devices and methods for fabricating semiconductor devices are desirable.

SUMMARY

According to the invention, a semiconductor device is provided that comprises a semiconductor die comprising a front side, a rear side opposing the front side and side faces. The semiconductor die further comprises a first transistor device comprising a first source pad and a first gate pad on the front side and a second transistor device comprising a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.

Since the central portion of the drain pad is covered by the first electrically insulating layer, this central portion does not act as a contact surface for forming an external electrical connection to the drain regions of the first and second transistor devices. The drain pad is electrically floating. This semiconductor device is, therefore, suitable for use in applications in which access to the common drain of the two transistor devices is not required. An example of such an application is a battery protection switch.

The central portion is at least 80% and in some embodiments is at least 90% of the area of the upper surface of the drain pad. In some embodiments, the first electrically insulating layer is in direct contact with at least the central portion of the upper surface of the drain pad. In some embodiments, the first electrically insulating layer is an organic layer.

The semiconductor device comprises a single semiconductor die that includes two vertical transistor devices in which the drift zone extends substantially perpendicularly to the front die. The two transistor devices share a common drain pad. The drains of the first and second transistor devices are, therefore, electrically coupled together by way of the drain pad. The drain is typically formed by a doped region of the semiconductor die positioned under the drift zone. The first and second transistor devices are arranged laterally adjacent one another in the semiconductor die and can be switched independently of one another.

In some embodiments, the semiconductor die comprises an epitaxial silicon layer formed on a monocrystalline silicon substrate. In these embodiments, the source region, body region, gate and drift zone of each of the first and second transistor devices are formed in the epitaxial layer and the silicon substrate forms the drain.

In some embodiments, the drain regions are separated from one another by an insulation region and only electrically coupled by the drain pad. The insulation region may be a trench that is filled with electrically insulating material that extends through the thickness of the die or an implanted region.

In some embodiments, the drain regions of the first and second transistor devices are formed by a single doped region that is electrically connected to and in contact with the drain pad. In these embodiments, the electrical connection between the drains of the first and second transistor devices is made by both the common doped drain region and the common drain pad. Since the resistance of the drain pad is typically less than the resistance of the doped drain region, the drain pad provides the major portion of the electrical connection.

In some embodiments, the first and second transistor devices are electrically separated from one another by one or more trenches formed in the transistor structure at the front side that surround at least one of the transistor devices, in particular the active area including the active transistor cells of at least one of the transistor devices. The trench may be filled with electrically insulating material or by conductive material that is connected to drain potential.

In some embodiments, the side faces of the semiconductor die that extend between the front and rear surfaces are exposed and not covered by an electrically insulating layer, for example are not covered by the first electrically insulating layer on the rear surface. In some embodiments, a separate passivation layer may be arranged on the side faces if additional protection is desired.

In some embodiments, the upper surface and side faces of the drain pad are entirely covered by the first electrically insulating layer. In some embodiments, the portions of the rear surface of the semiconductor die that are not occupied by the drain pad are covered by the first electrically insulating layer.

In other embodiments, the side faces of the drain pad are uncovered and the central portion of the upper surface of the drain pad is covered by the first electrically insulating layer. In other words, 80% to 100% or 90% to 100% of the upper surface of the drain pad is covered by the first electrically insulating layer and the side faces and the portions of the rear surface of the semiconductor die that are not occupied by the drain pad are uncovered by the first electrically insulating layer.

In some embodiments, the central portion corresponds to the area of the upper surface of the drain pad so that the entire upper surface is covered by the first electrically insulating layer. In other embodiments, the central portion has an area that is less than the area of the upper surface so that a peripheral region of the upper surface that surrounds the covered central portion and that is situated between the covered central portion and the uncovered side face is uncovered by the first electrically insulating layer. The uncovered peripheral region extends between the edge formed between the upper surface and side faces of the drain pad and the first electrically insulating layer position on the upper surface of the drain pad. The uncovered peripheral region comprises less than 20% or less than 10% of the upper surface of the drain pad.

In some embodiments, the semiconductor device further comprises a first pad finishing layer that extends over the rear side of the semiconductor die and is arranged between the rear side of the semiconductor die and the first electrically insulating layer. The first pad finishing layer further extends over the drain pad such that the first pad finishing layer is arranged between the drain pad and the first electrically insulating layer.

The first pad finishing layer may provide adhesion promotion as it is arranged between the first electrically insulating layer and the drain pad and, optionally, also between the rear side of the semiconductor die and the first electrically insulating layer. The pad finishing layer may also be referred to as an intermediate layer.

In some embodiments, the lateral extent of the first pad finishing layer corresponds to the lateral extent of the first electrically insulating layer. The first pad finishing layer may extend over the entire drain pad and over the side faces and upper surface of the drain pad.

In some embodiments, the lateral extent of the first pad finishing layer is larger than the lateral extent of the first electrically insulating layer. For example, in embodiments in which the rear surface of the die and the side faces and, optionally, the peripheral regions of the upper surface of the drain pad are uncovered by the first electrically insulating layer, these regions are covered by the first pad finishing layer. The portion of the first pad finishing layer arranged on these regions is also exposed from the first electrically insulating layer.

In embodiments including a first pad finishing layer, the first insulating layer is separated from the rear side and the drain pad by the intervening pad finishing layer and is only in contact with the first pad finishing layer and not the drain pad or the rear side of the semiconductor die.

In some embodiments, the first and second source pads, the drain pad and the first and second gate pads comprise copper. In some embodiments, the first and second source pads, the drain pad and the first and second gate pads have a multilayer structure with one or more barrier layers arranged on the front surface or rear surface and the copper layer arranged on the barrier layer(s).

It is desirable to mark a semiconductor package with product information. This marking is typically arranged on the rear surface of the package in the mold compound so as to allow this information to be discernible after mounting of the package. For a chip scale package with an exposed copper pad on its rear side, if a product marking is formed in the upper surface of a copper pad, for example by engraving the drain pad in the present device as this remains unused for electrical connections, oxidation of the outer surface means that the marking becomes less discernible over time. The first electrically insulating layer that covers at least the central portion of the drain pad provides an outer surface which is more stable and which reduces the likelihood of oxidation. Additionally, the first electrically insulating layer can serve as a surface for product marking without the risk of the product marking becoming less discernible over time due to oxidation of the surface.

In some embodiments, the first electrically insulating layer is an organic layer and is formed of epoxy or polyimide. These materials are easily structurable or patternable using photolithographic techniques and compatible with common pad finishing layers so that, if a pad finishing layer is used, improved adhesion between the pad finishing layer and the epoxy or polyimide can be achieved. This further improves the reliability of the protection provided by the first electrically insulation layer.

In some embodiments, the first pad finishing layer comprises one or more of Ni, a NiV alloy, an oxide and a nitride. These materials provide good adhesion the first electrically insulating layer, in particular with epoxy resins and polyimide and with copper.

In contrast to the drain pad, which is electrically floating, the first and second source pads and the first and second gate pad on the opposing front side of the semiconductor die provide contact areas that are electrically accessible externally to the device. At least central portions, that is at least 80% or at least 90% of the outer surface of the first and second source pads and the first and second gate pads remain exposed to allow electrical connections to the respective pad to be formed, for example by solder in the case of surface mounting or by an additional connector such as a bond wire, metallic clip or metallic ribbon.

In some embodiments, the semiconductor device further comprises a second electrically insulating layer that covers the front side of the semiconductor die in regions that are not occupied by the first and second source pads and the first and second gate pads and that covers at least side faces of the first and second source pads and of the first and second gate pads. At least a central portion of each of the first and second source pads and each of the first and second gate pads is exposed from the second electrically insulating layer. This allows the central portion to act as an electrical contact area and provide a contact to this area of the pad which has a low resistance.

In some embodiments the semiconductor device further comprises a second pad finishing layer that is arranged between the front side of the semiconductor die and the second electrically insulating layer. In some embodiments, the second pad finishing layer extends between at least side faces of the first and second source pads and of the first and second gate pads on the front side of the die and between the front side of the die and the second electrically insulating layer.

The lateral extent of the second pad finishing layer may correspond to the lateral extent of the second electrically insulating layer. In these embodiments, the second electrically insulating layer is not in direct contact with the first and second source pads and the first and second gate pads or the front side of the semiconductor die, but is only in direct contact with the second electrically insulating layer.

In some embodiments, at least the central portion of the first and second source pads and of the first and second gate pads is exposed from the second pad finishing layer and from the second electrically insulating layer. At least central portions, that is at least 80% or at least 90% of the outer surface of the first and second source pads and the first and second gate pads, remain exposed to allow electrical connections to the respective pad to be formed.

In some embodiments, the second electrically insulating layer is formed of epoxy or polyimide. In some embodiments, the first and second source pads and the first and second gate pads are formed of copper. In some embodiments, the second pad finishing layer comprises one or more of Ni, a NiV alloy, an oxide and a nitride.

The same combination of materials may be used on the front side and the rear side of the semiconductor device.

In some embodiments, the side faces of the semiconductor die are uncovered by the first pad finishing layer, if present on the rear side, and are uncovered by the first electrically insulating layer. The side faces of the semiconductor die are also uncovered by the second pad finishing layer and second electrically insulating layer, if present, on the front side of the semiconductor die.

In some embodiments, the semiconductor device further comprises a product marking formed in an outer surface of the first electrically insulating layer.

The product marking may represent product tracking information and product identity information. Product tracking information may include the wafer fabrication lot number, the date on which the wafer was fabricated, the assembly lot number and the date on which the package was assembled. This information allows the manufacturer to track the manufacturing process and may be used to assist in solving manufacturing problems. Product identity information may include designations for the product type, package type and performance, for example speed or voltage. Other types of information about the package or semiconductor device within the package can be included in this information or be derivable from the information marked on the outer surface of the package.

Since semiconductor packages, in particular chip sized packages, have a limited area on which the information may be positioned, the information may be marked in the form of an alphanumeric code or barcode or data code matrix which is readable so as to convey more information about the package within a smaller space.

In some embodiments, the product marking comprises at least one alphanumeric character. An alphanumeric character describes one of the numbers 0 to 9 and the letters of the Latin alphabet. Punctuation marks such as full stops, commas, colons, back slashes, forward slashes etc are excluded from this definition.

In some embodiments, the product marking may be a two-dimensional matrix.

In some embodiments, the semiconductor die that is formed of monocrystalline silicon or comprises an epitaxial silicon layer that is optionally formed on a monocrystalline silicon base substrate.

In some embodiments, the first and the second transistor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, an insulated gate bipolar transistor (IGBT) device or a Bipolar Junction Transistor (BJT).

The electrodes or terminals of the transistor device are referred to herein as source, drain and gate. As used herein, these terms also encompass the functionally equivalent terminals of other types of transistor devices, such as an insulated gate bipolar transistor (IGBT). For example, as used herein, the term “source” encompasses not only a source of a MOSFET device and of a superjunction device but also an emitter of an insulator gate bipolar transistor (IGBT) device and an emitter of a Bipolar Junction Transistor (BJT) device, the term “drain” encompasses not only a drain of a MOSFET device or of a superjunction device but also a collector of an insulator gate bipolar transistor (IGBT) device and a collector of a BJT device, and the term “gate” encompasses not only a gate of a MOSFET device or of a superjunction device but also a gate of an insulator gate bipolar transistor (IGBT) device and a base of a BJT device.

Each of the first and second transistor devices typically includes a plurality of transistor cells electrically connected in parallel, each transistor cell having a transistor structure having a doped drain region, a doped drift region, a doped body region and doped source region and also a gate electrode which comprises polysilicon or metal. The semiconductor die may have the first conductivity type and form the drift region.

In some embodiments, a drain region of the first conductivity is type is formed at the rear side, the drift region of the first conductivity is arranged on the drain region, a body region of the second conductivity type is arranged on the drift region and a source region of the first conductivity type is arranged on or in the body region. The source region and the drain region are more highly doped than the drift region. The source region may be arranged at or near the front surface. The first gate of the first transistor device and the second gate of the second transistor device may be formed on the front surface of the wafer to form a planar gate or in a trench that extends from the first surface of the wafer into the volume of the wafer.

In an embodiment, a battery management system is provided that comprises a battery protection circuit and a battery protection switch. The battery protection switch is provided by the semiconductor device of any one of the embodiments described herein.

According to the invention a method of producing a semiconductor device is provided. The method comprises providing a semiconductor wafer comprising a plurality of component positions separated from one another by singulation regions located at least one of adjacent to and between the component positions. Each component position comprises a front side and a rear side opposing the front side, a first transistor device comprising a first source pad and a first gate pad on the front side and a second transistor device comprising a second source pad and a second gate pad on the front side. A drain pad is formed on the rear side of the component positions that is electrically coupled to a drain of the first transistor device and a drain of the second transistor device. The method further comprises covering at least a central portion of an upper surface of the drain pad by a first electrically insulating layer. The wafer is then singulated along the singulation regions to produce a plurality of semiconductor devices.

During singulation at least the central portion of the upper surface of the drain pad is covered by the first electrically insulating layer so that in the final semiconductor device, at least the central portion of the upper surface of the drain pad is covered by the first electrically insulating layer. The central portion is at least 80% or at least 90% of the upper surface of the drain pad.

The wafer may be singulated by laser dicing or mechanical sawing, for example, to separate the plurality of devices from the wafer.

The drain of the first and second transistor device formed in the component position may be formed by a doped region of the semiconductor wafer that is situated at or near the rear surface or that forms the rear surface of the wafer.

Each of the first and second transistor devices typically includes a plurality of transistor cells electrically connected in parallel, each transistor cell having a transistor structure having a doped drain region, a doped drift region, a doped body region and doped source region and also a gate electrode which comprises polysilicon or metal. The semiconductor die may have the first conductivity type and form the drift region. A drain region of the first conductivity is type is formed at the rear side, a drift region of the first conductivity is arranged on the drain region, a body region of the second conductivity type is arranged on the drift region and a source region of the first conductivity type is arranged on or in the body region. The source region and the drain region are more highly doped than the drift region. The source region may be arranged at or near the front surface. The first gate of the first transistor device and the second gate of the second transistor device may be formed on the front surface of the wafer and be planar gates or in a trench that extends from the first surface of the wafer into the volume of the wafer to from a trench gate.

In some embodiments, the method further comprises, before applying the first electrically insulating layer, forming a first pad finishing layer on the rear side of the wafer that covers side faces and the upper surface of the drain pad. Then the portion of the first pad finishing layer that is formed on at least the central portion of the upper surface of the drain pad is covered with the first electrically insulating layer. In other words, the first electrically insulating layer is formed directly on the pad finishing layer that is positioned directly on at least the central portion of the upper surface of the drain pad.

In some embodiments, the first pad finishing layer is deposited on the entire rear side of the semiconductor wafer including the upper surface and side faces of the drain pad and the regions of the rear surface of the semiconductor wafer that are not occupied by the drain pad.

In some embodiments, the first electrically insulating layer entirely overs the drain pad and the rear surface of the semiconductor wafer.

In some embodiments, the first electrically insulating layer is selectively applied to the central portion of the upper surface of the drain pad and the side faces of the drain pad and the rear surface of the semiconductor wafer remain exposed from the first electrically insulating layer.

In some embodiments, the first electrically insulating layer initially entirely covers the drain pad and the rear surface of the semiconductor wafer and then is removed from side faces of the drain pad and the rear surface of the semiconductor wafer leaving at least the central portion of the drain pad covered.

In some embodiments, the method further comprises forming a second pad finishing layer on the front side of the wafer that covers at least the side faces of the first and source pads and at least the side faces of the first and second gate pads. Then the second pad finishing layer is covered with a second electrically insulating layer. At least a central portion of the first and second source pads and of the first and second gate pads is exposed from the second pad finishing layer and from the second electrically insulating layer. The central portion is at least 80% or at least 90% of the upper surface of the respective pad. The second pad insulating layer may be used to improve the adhesion between the second electrically insulating layer and the front surface of the semiconductor die and the side faces of the pads on the front surface and improve the protection provided by the second insulating layer.

The second pad finishing layer may be formed selectively so as to leave the central portion of the first and second source pads and of the first and second gate pads is exposed from the second pad finishing layer. In other embodiments, the second pad finishing layer is deposited so that it covers the front surface of the wafer entirely including the central portion of the first and second source pads and of the first and second gate pads. Portions of the second pad finishing layer are them removed so that least at least the central portion of the first and second source pads and of the first and second gate pads is exposed from the second pad finishing layer.

The second pad finishing layer may serve as an adhesion promotion layer between the second electrically insulating layer and the material of the source pads and gate pads and the front surface of the die that is unoccupied by the source pads and gate pads.

The stack of a pad finishing layer and an electrically insulating layer provides improved passivation or protection for the surface on which it is positioned. The stack of a pad finishing layer and an electrically insulating layer having any one of the arrangements described herein is not limited to use in a chip scale package having two transistors with a common drain and may also be used for semiconductor devices that include a single semiconductor device in a semiconductor die to provide a chip scale package.

According to an embodiment of the invention, a semiconductor device is provided that comprises a semiconductor die that comprises a front side, a rear side opposing the front side and side faces and at least one pad on the front side and at least one pad on the rear side. The at least one pad on the front side and the at least one pad on the rear side are at least partially covered by a pad finishing layer and are at least partially covered by an electrically insulating layer arranged on the pad finishing layer.

According to an embodiment of the invention, a semiconductor device is provided that comprises a semiconductor die that comprises a front side, a rear side opposing the front side and side faces and at least one pad on the front side or on the rear side. The at least one pad on the front side or the at least one pad on the rear side is at least partially covered by a pad finishing layer and is at least partially covered by an electrically insulating layer arranged on the pad finishing layer.

In some embodiments, at least 80% or at least 90% of the upper surface of the pad on the rear side and/or front side is uncovered by the pad finishing layer and the electrically insulating layer. The lateral extent of the pad finishing layer and the electrically insulating layer may be substantially the same.

In some embodiments, the side faces of the semiconductor die are uncovered by the pad finishing layer and the electrically insulating layer.

In embodiments in which at least one pad is arranged on the front side and at last one pad is arranged on the rear side, the semiconductor die may comprise a vertical device, for example a vertical diode or a vertical transistor device.

In embodiments in which the pad(s) are arranged on one side of the die, typically the front side, the semiconductor die may comprise a lateral device, for example a lateral diode or a lateral transistor device.

In some embodiments, the electrically insulating layer is formed of epoxy or polyimide, and/or the first pad finishing layer comprises one or more of Ni, a NiV alloy, an oxide and a nitride, and/or the second pad finishing layer comprises one or more of Ni, a NiV alloy, an oxide and a nitride and/or the pads are formed of copper.

In some embodiments, the transistor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, an insulated gate bipolar transistor (IGBT) device or a Bipolar Junction Transistor (BJT).

The electrodes or terminals of the transistor device are referred to herein as source, drain and gate. As used herein, these terms also encompass the functionally equivalent terminals of other types of transistor devices, such as an insulated gate bipolar transistor (IGBT). For example, as used herein, the term “source” encompasses not only a source of a MOSFET device and of a superjunction device but also an emitter of an insulator gate bipolar transistor (IGBT) device and an emitter of a Bipolar Junction Transistor (BJT) device, the term “drain” encompasses not only a drain of a MOSFET device or of a superjunction device but also a collector of an insulator gate bipolar transistor (IGBT) device and a collector of a BJT device, and the term “gate” encompasses not only a gate of a MOSFET device or of a superjunction device but also a gate of an insulator gate bipolar transistor (IGBT) device and a base of a BJT device.

In some embodiments, the semiconductor die is formed of monocrystalline silicon or an epitaxial silicon layer that is optionally formed on a monocrystalline silicon base wafer.

The transistor device typically includes a plurality of transistor cells electrically connected in parallel, each transistor cell having a transistor structure having a doped drain region, a doped drift region, a doped body region and doped source region and also a gate electrode which comprises polysilicon or metal. The semiconductor die may have the first conductivity type.

For a vertical transistor device, a drain region of the first conductivity is type is formed at the rear side, a drift region of the first conductivity is arranged on the drain region, a body region of the second conductivity type is arranged on the drift region and a source region of the first conductivity type is arranged on or in the body region. The source region and the drain region are more highly doped than the drift region. The source region may be arranged at or near the front surface. The gate of the transistor device may be formed on the front surface of the wafer to form a planar gate or in a trench that extends from the first surface of the wafer into the volume of the wafer to form a gate trench transistor.

DETAILED DESCRIPTION

A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.

As used herein, various device types and/or doped semiconductor regions may be identified as being of n type or p type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either n or p type and the second type then is either p or n type.

According to some embodiments, a battery protection switch (BPS) is provided that is a bi-directional switch with a low-ohmic common drain, which is electrically floating. The common drain is facilitated via a thick backside metal, e.g. prn Cu which may be deposited by electroplating techniques. The backside is exposed in the application for this kind of protection switches. Therefore, it is desirable to protect the backside metal (e.g. Cu) from oxidation or discoloration. Another challenge is the chip marking as there is no mold compound for such a device when it is provided as a chip-scale package/wafer-level-package. Consequently, chip marking, for example sales code, lot information, etc., on the backside of the chip would be desirable.

As the Cu backside metal is exposed, discolorations caused by oxidation of the Cu in air may be an issue for handling at the user, due to poorer chip detection, optical appearance for example. A high oxidation level of the exposed Cu backside metal can lead to electrical abnormalities.

According to embodiments described herein a combination of a pad finish (e.g. NiV, oxides, etc.) together with an organic layer is used on the rear side and covers the drain pad.

The pad finish acts as protection of the backside metal from discoloration and oxidation. Furthermore, the pad finish also acts as an adhesion layer for a subsequent organic layer. The pad finish layer is formed of a material that is selected to have a good adhesion and also to be processable on silicon or an optional seed layer (e.g. Ti), as the backside metal is removed in the kerf region to avoid issues during the dicing process.

For facilitating chip marking, an organic layer such as epoxy is beneficial due to its similarity to widely used mold-compounds, for which the marking process is well established. The organic layer enables laser marking, while ensuring that the metal protection provided by the underlying pad finishing layer stays intact. Organic layers such as epoxy or imide have similar physical properties as mold-compounds, which are widely used for chip-encapsulation and also for the product marking and may be used as the organic layer which covers the drain pad. Consequently, a common-drain Cu backside device can be provided in the form of a chip-scale package, e.g. a battery protection switch in a chip-scale package.

FIG.1illustrates a cross-sectional view of a semiconductor device10according to an embodiment. The semiconductor device10comprises a semiconductor die11comprising a front side12and a rear side13which opposes the front side12and side faces14which extend between the front side12and the rear side13. The semiconductor die11comprises a first transistor device15which comprises a first source pad16and a first gate pad17arranged on the front side12of the semiconductor die11. The semiconductor die11further comprises a second transistor device18which comprises a second source pad19and a second gate pad20which are arranged on the front side12. The second transistor device18is arranged laterally adjacent to the first transistor device15in the semiconductor die11.

The first transistor device15further includes a first drain21and the second transistor device18further comprises a second drain22. The first and second drains21,22may be formed by a highly doped region of the semiconductor die11which is situated at or near the recent rear surface13the semiconductor die11. The first and second drains21,22of the first and second transistor devices15,18are electrically coupled to a common drain pad23which is arranged on the rear side13of the semiconductor die11.

The first transistor device15and the second transistor device18have a vertical drift path that extends substantially perpendicularly to the front side12and may be referred to as a vertical transistor device. In some embodiments, the first and second transistor devices15,18are a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, an insulated gate bipolar transistor (IGBT) device or a Bipolar Junction Transistor (BJT).

The electrodes or terminals of the transistor device are referred to herein as source, drain and gate. As used herein, these terms also encompass the functionally equivalent terminals of other types of transistor devices, such as an insulated gate bipolar transistor (IGBT). For example, as used herein, the term “source” encompasses not only a source of a MOSFET device and of a superjunction device but also an emitter of an insulator gate bipolar transistor (IGBT) device and an emitter of a Bipolar Junction Transistor (BJT) device, the term “drain” encompasses not only a drain of a MOSFET device or of a superjunction device but also a collector of an insulator gate bipolar transistor (IGBT) device and a collector of a BJT device, and the term “gate” encompasses not only a gate of a MOSFET device or of a superjunction device but also a gate of an insulator gate bipolar transistor (IGBT) device and a base of a BJT device.

The semiconductor die11may be formed of silicon, for example a single crystal silicon or comprise an epitaxial layer of silicon.

The drain pad23has an upper surface24, which is substantially parallel to the rear side13of the semiconductor die11, and side faces25which extend from the upper surface24to the rear side13. In some embodiments, the drain pad23does not extend to the side faces14of the semiconductor die11but has an area which is slightly less than the area of the rear side13of the semiconductor die11.

At least a central portion26of the upper surface24of the drain pad23is covered by a first electrically insulating layer27, for example at least 80% or 90% of the upper surface24including the central portion is covered by the first electrically insulating layer27. In some embodiments, the peripheral region or rim of the upper surface24is uncovered by the first electrically insulating layer27. In some embodiments, such as that illustrated inFIG.1, the entire upper surface24is covered by the first electrically insulating layer27and the side faces25of the drain pad23remain uncovered by the first insulating layer27. In some embodiments, the entire upper surface24, the entire side faces25of the drain pad23and the regions of the rear side13that are not covered by the drain pad23are covered by the first insulating layer27.

The first insulating layer27prevents an electrical contact from being made to the drain pad23by a direct contact between an electrical connector, such as a bond wire or a contact clip or a solder connection and the upper surface24of the drain pad23. Therefore, the drain pad23does not form an outer contact of the semiconductor device10but does provide an electrical connection between the drains21,22of the first and second transistor devices15,28that is electrically floating. The first insulating layer provides protection of the drain pad23from the atmosphere and can be used to prevent discoloration and oxidation of the outer surfaces of the drain pad23.

In the embodiment illustrated inFIG.1, the semiconductor device10further comprises a first pad finishing layer28that extends over the rear side13of the semiconductor die11and which is arranged between the rear side13of the semiconductor die11and the first insulating layer27. The pad finishing layer28also extends over the drain pad23such that the first pad finishing layer28is arranged between the drain pad23and the first electrically insulating layer27. Referring toFIG.1, in some embodiments, the first pad finishing layer extends over the and is in direct contact with the upper surface24and the side faces25of the drain pad23and is in direct contact with the rear side13of the semiconductor die11in regions of the rear side13which are laterally adjacent the drain pad23and not occupied by the drain pad23.

The drain pad23as well as the first and second source pads16,19and the first and second gate pads17,20which are arranged on the front side12may be formed of copper or a copper alloy. The composition of the pad finishing layer28may be selected depending on the composition of the drain pad23and the first insulating layer27. In some embodiments, the pad finishing layer may comprise one or more of nickel, a nickel vanadium alloy, an oxide or a nitride and the first insulating layer27is formed of an organic material such as epoxy or polyimide.

In some embodiments, a seed layer29is arranged on the rear side13of the semiconductor die11and is in direct contact with the material of the rear side rear surface of the semiconductor die11. The drain pad23is in direct contact with the seed layer29. The seed layer29may be formed of a metal or alloy which is deposited by vacuum deposition techniques, for example by sputtering, onto the rear surface13and provides a conductive layer which acts as an electrode onto which the drain pad23can be deposited using galvanic or electroplating techniques. Galvanic and electroplating techniques have the advantage that a thicker drain pad23can be formed more quickly than in a vacuum deposition technique. The seed layer may be formed of Ti or Cu.

In some embodiments, a second seed layer30is also provided on the front side12of the semiconductor die11and the first source pad16, the first gate pad17, the second source pad19and the second gate pad20are arranged on the second seed layer30. In some embodiments, a second electrically insulating layer31is arranged on the front side12and extends between the first source pad16, first gate pad17, the second source pad19and the second gate pad20and may extend between the side faces33of the first source pad16, the first gate pad17, the second source pad19and the second gate pad20as illustrated inFIG.1. At least the central portion of each of the upper surface34of each of the first source pad16, the first gate pad17, the second source pad19and the second gate pad20remains exposed from and uncovered by the second electrically insulating layer31.

The first source pad16, the first gate pad17, the second source pad19and the second gate pad20provide the outer contact surfaces of the semiconductor device10with which the device10is mounted onto a higher-level circuit board. A solder connection can be used between the first source pad16, the first gate pad17, the second source pad19and the second gate pad20and corresponding pads on the circuit board. The semiconductor device10is, therefore, a surface mount device.

The thickness of the second insulating layer31may be less than the thickness of the first source pad16, the first gate pad17, the second source pad19and the second gate pad20such that the pads protrude above the surface of the second insulating layer. In other embodiments, the second insulating layer31is arranged on the peripheral regions of the upper surface34of first source pad16, first gate pad17, the second source pad19and the second gate pad20leaving the central portion of the pad exposed and providing an outer contact area.

The side faces14of the semiconductor die11may be remain exposed and uncovered by the first and second insulating layers27,31and first pad finishing layer28if present on the rear side13or may be covered by an additional thin passivation layer. The semiconductor device10can be considered to be a chip-sized or chip scale package.

A product marking32may be included on the outer surface of the first electrically insulating layer27. The product marking may be formed by engraving and may comprise indentations and/or protrusions corresponding to one or more alpha numeric characters in order to convey information about the product.

The front side metallization typically has a multilayer structure with the pads16,17,19,20being formed in the outermost conductive layer. Depending on the redistribution structure provided by the front side metallization, the arrangement of the pads may differ from the arrangement of the sources and gates of the two transistor devices15,18that are formed in the semiconductor die11. For example, in the semiconductor die11, each of the first and second transistor devices15,18includes a plurality of transistor cells in an active region, each transistor cell having a transistor structure with a gate and a source formed in the semiconductor die11at the front side12. For the first transistor device15, the gates are electrically connected by the front side metallization structure to the first gate pad17and the sources are electrically connected to the source pad16. For the second transistor device18, the sources are connected to the source pad19and the gates to the gate pad20.

The semiconductor device10illustrated inFIG.1may be used in a battery management system.FIGS.2A and2Billustrate a battery management system100for a battery101which comprises a battery protection circuit102and a battery protection switch103which comprises the semiconductor device10including two transistor devices having a common drain configuration according to any one of the embodiments described herein.

The battery management system (BMS)100is used to protect the battery101, typically a Lithium-ion battery, against faulty operation and to optimize the charging and discharging processes in order to avoid failures like thermal runaway, lithium plating, electrode decomposition, etc. A battery management system100is used to increase lifetime and efficiency of lithium batteries, also under stressful conditions. The battery protection circuit102disconnects the battery101from the load when a critical condition is observed, such as short circuit, undercharge, overcharge or overheating. Additionally, the battery protection circuit102manages current rushing into and out of the battery, such as during pre-charge or hotswap turn on.

The battery management system100comprises a battery protection switch103which conducts current in two directions and comprises two transistor devices Q1, Q2in a common drain configuration and a controller IC104protects rechargeable batteries101from operating outside of the safe operating area, for example protects the battery101from overcharge, over-discharge, overcurrent, etc. Depending on the operational mode, Q1and Q2can be turned on/turned off individually.

During charging of the battery104, both Q1and Q2of the battery protection switch103are turned on, or only Q2is turned on which leads to increased losses due to current flow through body-diode of Q1.

During discharging of the battery104, both Q1and Q2of the battery protection switch103are turned on, or only Q1is turned on which leads to increased losses due to current flow through body-diode of Q2.

Overcharge protection is provided when both Q1and Q2are turned off. Q1still allows current flow through body-diode therefore Q2is used to block the current flow. Overcharge protection is also provided when both Q1and Q2are turned off. Q1still allows current flow through body-diode therefore Q2is used to block the current flow. Over-discharge protection is provided when both Q1and Q2are turned off. Q2still allows current flow through body-diode therefore Q1is used to block the current flow.

FIGS.3A to3Dillustrate various embodiments of the semiconductor device10including two transistor devices15,18electrically connected in a common drain configuration, as illustrated inFIG.1, whereby in the views ofFIGS.3A to3Donly the first source pad16and the first gate pad17on the front side12the semiconductor die11can be seen.

Referring toFIG.3A, in some embodiments, the arrangement of the second insulating layer31on the front side12of the semiconductor die11differs from that illustrated inFIG.1in that the second insulating layer31is in contact not only with the side faces33of the first source pad16, the first gate pad17, the second source pad19and the second gate pad20and the front side12of the semiconductor die11but also extends over the peripheral region of the outermost surface34of each of the first source pad16, first the gate pad17, the second source pad19and the second gate pad20as can be seen inFIG.3Afor the first source pad16and the first gate pad17. The central portion of the outermost surface34of the first source pad16, the first gate pad17, the second source pad19and the second gate pad20remains uncovered by the second electrically insulating layer31and provide the outer contact surfaces of the device10. The central portion is at least 80% or at least 90% of the outermost surface34.

FIG.3Billustrates an embodiment which differs from that illustrated inFIGS.1and3Ain that the first electrically insulating layer27which is arranged on the rear side13of the semiconductor die11is positioned only on the upper surface24of the drain pad23such that the side faces25of the die pad23are uncovered by the first electrically insulating layer27. In this embodiment, the first pad finishing layer28is positioned on the side faces25and upper surface24of the die pad23as well as on the rear side13of the semiconductor die11. Therefore, the portions of the first pad finishing layer28which are arranged on the side faces25and the rear side13of the semiconductor die11are exposed from the first electrically insulating layer27.

A peripheral region36of the upper surface24of the die pad23that extends between the edge formed between the upper surface24and the side faces and the side wall of the first electrically insulating layer27remains uncovered by the first electrically insulating layer27. The peripheral region36is however covered by and in direct contact with the first pad finishing layer29. The peripheral region36comprises less than 20% or less than 10% of the area of the upper surface24.

FIG.3Cillustrates an embodiment of the semiconductor device10which differs from that illustrated inFIG.3Ain that the semiconductor device10further comprises a second pad finishing layer35which is positioned on the front side12of the semiconductor die11and on side faces33and peripheral regions of the outermost surface34of the first source pad16, the first gate pad17, the second source pad19and the second gate pad20positioned on the front side12of the semiconductor die11. The lateral extent of the second pad finishing layer35corresponds to that the lateral extent of the second electrically insulating layer31so that the second electrically insulating layer31is not in direct contact with either the front side12of the semiconductor die11or with the material of contact pads on the front side, as can be seen in the view ofFIG.3Cfor the first source pad16and the first gate pad17. The central portion of the upper surface34of first source pad16, the first gate pad17, the second source pad19and the second gate pad20, which is exposed from the second electrically insulating layer31, is also exposed from the second pad finishing layer35. In this embodiment, the first electrically insulating layer27covers the entire rear side13and is also not in direct contact with the rear side13of the semiconductor die11or with the drain pad23due to the intervening first pad finishing layer28. In contrast to the arrangement on the front side12, the first pad finishing layer28and the first electrically insulating layer27entirely covers the upper surface24and side faces25of the drain pad23.

FIG.3Dillustrates a semiconductor device10according to an embodiment which differs from that illustrated inFIG.3Cin that the first electrically insulating layer27is arranged only on the central portion of the outer surface24of the drain pad23so that the side faces25of the drain pad23and rear side13of the semiconductor die11, which is not occupied and covered by the drain pad23, are exposed from the first electrically insulating layer28as in the embodiment illustrated inFIG.3B.

FIGS.4A to4Cillustrate a method for fabricating a semiconductor device which may be used for fabricating the semiconductor device according to any one of the embodiments described herein. Typically, a plurality of semiconductor devices is fabricated using a semiconductor wafer at using the same processing steps.

FIG.4Aillustrates a cross-sectional view of a portion of a semiconductor wafer40which includes a plurality of component positions41that are separated from one another by singulation regions42. Typically, the component positions41are arranged in an array of rows and columns and the singulation regions42have the form of an orthogonal grid in plan view. One of the singulation regions42is located at least one of adjacent to and between the component positions41. Each component position41provides a comprises a front side43and a rear side44which opposes the front side43. The front side43of the individual component positions41and the rear side44of the individual component positions41is part of the front side43and rear side44, respectively, of the semiconductor wafer40. Each component position41further comprises a first transistor device45comprising a first source pad46and a first gate pad47on the front side43and a second transistor device48which comprises a second source pad49and a second gate pad50on the front side43. The first and second transistor devices45,48are arranged laterally adjacent one another in the component portion41.

The front side43also comprises an electrically insulating layer51which is positioned on the front side43between the first and second source pads46,49and the first and second gate pads47,50. In some embodiments, the insulating layer51is in contact with only the side faces of the first and second source pads46,49and with only the side faces of the first and second gate pads47,50. In some embodiments, the insulating layer51is arranged on the further arranged on the peripheral regions of the first and second source pads46,49and the first and second gate pads47,50. In some embodiments, a pad finishing layer is arranged on the front surface43between the insulating layer51and the first and second source pads46,49and first and second gate pads47,50and has the form of an interfacial layer, as example illustrated inFIGS.3C and3D. Processing of the front surface43and the metallisation structure thereon may be completed, before processing of the rear surface44is performed.

In some embodiments, the rear surface44of the wafer40is subjected to grinding to reduce the thickness of the semiconductor wafer40and expose the heavily doped drain region59that is common to both of the first and second transistor device45,48in the worked rear surface44′ of the semiconductor wafer40.

Referring toFIG.4B, a drain pad51is formed on the rear side44of the component positions41so that it is electrically coupled to drain region59of the first transistor device45and of the second transistor device48which is formed at the worked second rear surface44′. In some embodiments, a seed layer52is first deposited on the worked rear surface44′, for example by sputtering or another vacuum deposition technique, and the drain pad51is deposited on the seed layer52using galvanic or electroplating techniques. The seed layer52is used as an electrode when depositing the drain pad51using galvanic or electroplating techniques.

Referring toFIG.4C, a pad finishing layer53is then applied to the worked rear surface44′ which covers the upper surface54and side faces55of the drain pads51as well as the regions of the worked surface44′ which do not include a drain pad51such as in the singulation regions42. An electrically insulating layer56is applied which covers the entire worked rear surface44′ and the pad finishing layer so that the entire surfaces of the drain pads51, i.e. the side faces53and upper surface54, are covered by the insulating layer56. The insulating layer may be an organic layer such as an epoxy resin or polyimide.

Referring toFIG.4C, a singulation process is then carried out as indicated by the arrows57to singulate the wafer40along the singulation regions42and produce a plurality of separate semiconductor devices form the semiconductor wafer40. In some embodiments, the pad finishing layer53may be omitted and the insulating layer56is in direct contact with the upper surface54and side faces53of the drain pads51and the seed layer52or in embodiments in which the seed layer52is omitted, is in direct contact with the worked surface44′.

In some embodiments, after applying the insulating layer56such that it covers the entire worked rear surface44′ and the drain pads51, portions of the first electrically insulating layer56are removed to expose the side faces55of the die pads51and the worked rear surface44′ of the semiconductor wafer40, in regions which do not include a drain pad51. The central portion of the upper surface54of the drain pad51is, however, covered by the electrically insulating layer56. In some embodiments, only the side faces55remain uncovered by the insulating layer56or a minor portion of the peripheral region of the upper surface54and the side faces55may be uncovered by the insulating layer56.

In some embodiments, the first and second transistor devices45,48of each component position41may be electrically isolated from one another by an electrically insulating region.

In other embodiments, the isolation between the first and second transistor45,48in each component position41may be formed by sections of the transistor structure formed in the front surface43, for example, by trenches58similar to the field plate trenches of the transistor structure. These isolation structures58may be electrically connected to drain potential.

In some non-illustrated embodiments, the insulating region initially has the form of a trench which is inserted from the front surface43and which has a base positioned within the wafer40. The trench is filled with insulating material. In embodiments in which the rear side44is subjected to grinding and the thickness of the wafer40is reduced, the insulating material within the trench may be exposed in the rear surface44′ and the seed layer52and the drain pad51extends over this insulating material.

The drain pad51, the first and second source pads46,49and the gate pads47,50may comprise copper. The pad finishing layer, if used on one or both of the front and rear surfaces43,44, may comprise one or more of nickel, nickel vanadium alloy, an oxide and nitride. The insulating layers51,56arranged on the front side43and rear side44may be formed of epoxy or polyimide.

The stack of a pad finishing layer and electrically insulating layer may also be used in semiconductor devices in which the semiconductor die includes a single device, for example a single transistor device or a single diode.

FIG.5Aillustrates an embodiment of a semiconductor device70which includes a single transistor device71formed in a semiconductor die72having a front side73, a rear side74opposing the front side73and side faces75which extend between the front side73and the rear side74. The transistor device71further comprises a source pad76and gate pad77on the front side73and a drain pad78on the rear side74. The transistor device71may have a vertical drift path that extends between the front side73and rear side74and be referred to as a vertical transistor device.

The semiconductor device70further comprises a pad finishing layer79which is arranged on the rear side74in regions laterally adjacent the drain pad78and which extends over side faces80and the peripheral region of the outermost surface81of the drain pad78. An electrically insulating layer82is arranged on the rear side74which has a lateral extent which correspond substantially to the lateral extent of the pad finishing layer79. Consequently, the electrically insulating layer82is not in direct contact with the rear side74of the semiconductor die72or with the drain pad78due to the intervening pad finishing layer79.

In contrast to the embodiments illustrated inFIGS.1to3D, at least the central portion of the outer surface81of the drain pad78on the rear side74the semiconductor die72is exposed and uncovered by the electrically insulating layer82and the pad finishing layer78arranged on the rear side74of the semiconductor die72. The central portion is at least 80% or at least 90% of the area of the upper surface.

In this embodiment, the front side73is free of a pad finishing layer and an electrically insulating layer. However, the front side73may have an arrangement corresponding to the front side shown in figures any one of the embodiments described with reference toFIGS.1and3A to3D.

FIG.5Billustrates a semiconductor device90according to an embodiment which includes a single lateral transistor device91formed in the semiconductor die72in which the drift path extends parallel to the front side73. The source pad76, gate pad77and drain pad78are arranged on the front side73. The gate pad77may be arranged laterally between the source pad76and the drain pad78.

The semiconductor device90further comprises a pad finishing layer92which is arranged on the front side73in regions laterally adjacent the source pad76, the gate pad77and drain pad78. The pad finishing layer92also extends over the side faces80and the peripheral region of the outermost surface81of each of the source pad76, the gate pad77and the drain pad78. An electrically insulating layer93is arranged on the front side73which has a lateral arrangement which corresponds substantially to the lateral extent of the pad finishing layer79. Consequently, the electrically insulating layer93is not in direct contact with the front side73of the semiconductor die72or with the side faces and peripheral regions of the source pad76, the gate pad77and the drain pad78due to the intervening pad finishing layer92. The central portion of the upper surface81and the majority of the upper surface81of the source pad76, gate pad77and drain pad78remains uncovered by the pad finishing layer92and the electrically insulating layer93.

The front side metallization typically has a multilayer structure with the pads76,77,78being formed in the outermost conductive layer. Depending on the redistribution structure provided by the front side metallization, the arrangement of the pads76,77,78may differ from the arrangement of the source, gate and drain formed in the semiconductor die72. For example, in the semiconductor die91, the transistor structure may include a plurality of transistor cells, each having a gate arranged laterally between a source and a drain. The gates are electrically connected by the front side metallization structure to the gate pad77, which may be arranged in a corner of the front side or towards on edge of the front side73intermediate the width. The sources are electrically connected to the source pad76and the drains to the drain pad78.

The expression “and/or” should be interpreted to include all possible conjunctive and disjunctive combinations, unless expressly noted otherwise. For example, the expression “A and/or B” should be interpreted to mean only A, only B, or both A and B. The expression “at least one of” should be interpreted in the same manner as “and/or”, unless expressly noted otherwise. For example, the expression “at least one of A and B” should be interpreted to mean only A, only B, or both A and B.