Poly-emitter type bipolar junction transistor, bipolar CMOS DMOS device, and manufacturing methods of poly-emitter type bipolar junction transistor and bipolar CMOS DMOS device

A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.

The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0086324 (filed on Sep. 2, 2008), which is hereby incorporated by reference in its entirety.

BACKGROUND

A bipolar device, a CMOS (Complementary Metal Oxide Semiconductor), and a DMOS (Double diffusion MOS) can be formed in a single wafer by using a BCD process. Besides the bipolar device, the CMOS and the DMOS, a logic circuit, a PMOS, an NMOS, a resistor, a capacitor and a diode can be integrated in a single chip through the BCD process. For instance, a bipolar transistor can be manufactured while the CMOS and the DMOS are being manufactured through the BCD process.

The bipolar transistor has a structure employing a junction emitter. Therefore, in the case of the bipolar transistor manufactured through the related BCD process, it processes to improve the high frequency characteristics, to increase the amplification gain and breakdown voltage and to widen the operational range are limited.

SUMMARY

Embodiments relate to a poly-emitter type bipolar junction transistor, a BCD (Bipolar CMOS DMOS) device, a manufacturing method of the poly-emitter type bipolar junction transistor and a manufacturing method of the BCD device. Embodiments relate to a poly-emitter type bipolar junction transistor, a manufacturing method of the bipolar junction transistor by using the BCD process, a BCD device, and a manufacturing method of the BCD device by using the BCD process.

A poly-emitter type bipolar transistor according to embodiments may include a buried layer formed over an upper portion of a semiconductor substrate; an epitaxial layer formed over the semiconductor substrate; a collector area formed on the epitaxial layer and connected to the buried layer; a base area formed over an upper portion of the epitaxial layer; and a poly-emitter area formed over a surface of the semiconductor substrate in the base area and including a polysilicon material.

A BCD device according to embodiments may include a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material; and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.

A method for forming a poly-emitter type bipolar transistor according to embodiments may include forming a buried layer over an upper portion of a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate and forming a collector area connected to the buried layer on the epitaxial layer; forming an isolation layer that defines a base area and an emitter area; forming the base area on a substrate area below the isolation layer; forming a base electrode on a part of an upper portion of the base area; and forming a poly-emitter area including a polysilicon material on a part of an upper portion of the base area which is spaced apart from the base electrode by the isolation layer.

A method for manufacturing a BCD device through a BCD process according to embodiments may include forming a poly-emitter area of a bipolar transistor using a polysilicon material.

DESCRIPTION

Hereinafter, a poly-emitter type bipolar transistor, a BCD device, a method for manufacturing the poly-emitter type bipolar transistor, and a method for manufacturing the BCD device will be described in detail with reference to accompanying drawings.

ExampleFIG. 1is a side sectional view showing the BCD device including the poly-emitter type bipolar transistor according to embodiments. The BCD device according to embodiments is manufactured through the BCD process. In exampleFIG. 1, region “A” is a bipolar transistor region, region “B” is a CMOS region, and region “C” is a DMOS region.

Besides the poly-emitter type bipolar transistor, although not shown in exampleFIG. 1, a logic circuit, a PMOS, an NMOS, a high-voltage MOS, an intermediate-voltage MOS, a low-voltage MOS, a DEMOS (Drain Extended MOS), an LDMOS (Lateral Double diffused MOS), a resistor, a capacitor, and a diode can be integrated in a single chip according to the method for manufacturing the BCD of embodiments.

Referring to exampleFIG. 1, the poly-emitter type bipolar transistor includes a buried layer110, an epitaxial layer120, a collector area130, a base area140, a base electrode160, an isolation layer150, and a poly-emitter area170, which are formed on a substrate100in the bipolar transistor region A.

The CMOS includes a PMOS and an NMOS in the CMOS region B. The PMOS is isolated from the NMOS by an isolation layer150a. Each of the PMOS and the NMOS may include a buried layer110a, a heavily doped N-type well205, a P-type well200, an N-type well210, gates215and225, and source/drain areas220and230. The gates215and225may further include a gate insulating layer and a spacer.

The DMOS may include a buried layer110b, a heavily doped N-type well300, a P-type body305, an isolation layer150bfor isolating each area, a gate320, a P-type ion implantation area310and a first N-type ion implantation area315formed on the P-type body305, and a second N-type ion implantation area325formed on the other side of the gate320in the DMOS region C. The isolation layer150bformed between the gate320and the second N-type ion implantation area325may lengthen a current path between the P-type body305and the second N-type ion implantation area325, so that the DMOS may serve as a high-voltage device.

Hereinafter, a method for manufacturing the BCD device including the poly-emitter type bipolar transistor according to embodiments will be described in detail with reference to exampleFIGS. 1 to 7. In embodiments, the poly-emitter type bipolar transistor may be manufactured simultaneously with the BCD device, so the following description will be focused on the poly-emitter type bipolar transistor formed in the bipolar transistor region A. Each process to be described below may be a single process or a complex process for manufacturing one or at least two from the group including the poly-emitter type bipolar transistor, the logic circuit, the PMOS, the NMOS, the high-voltage MOS, the intermediate-voltage MOS, the low-voltage MOS, the DEMOS, the LDMOS, the resistor, the capacitor, and the diode.

ExampleFIGS. 2 to 7are sectional views showing the manufacturing procedure for the poly-emitter type bipolar transistor according to embodiments. First, the wafer-state semiconductor substrate100, for instance, a single-crystal silicon substrate may be cut to a predetermined thickness. A surface of the semiconductor substrate100may be polished such that the epitaxial layer120can be formed on the surface.

Then, as shown in exampleFIG. 2, an N type dopant may be implanted into a part of an upper portion of the semiconductor substrate100to form an N+ type buried layer110. Then, an ion implantation area may be diffused through a heat treatment process. At this time, the buried layers110aand110bmay also be formed in the CMOS area B and the DMOS area C of the substrate100, respectively. After forming the N+ type buried layer110, as shown in exampleFIG. 3, the epitaxial layer120may be formed by performing an epitaxial growth process with respect to the semiconductor substrate100.

After forming the epitaxial layer120, as shown in exampleFIG. 4, an N+ type diffusion area130connected to the N+ type buried layer110may be formed on the epitaxial layer120. The N+ type diffusion area130may serve as the collector area. At this time, heavily doped N-type wells205and300can be simultaneously formed.

Then, the isolation layer150may be formed. As shown in exampleFIG. 5, the isolation layer140defines the base area and the emitter area while isolating the base area from the emitter area. At this time, the isolation layers150aand150bcan be simultaneously formed in the CMOS region B and the DMOS region C. Then, an ion implantation mask process and an ion implantation process may be performed to form the P-type well200and the N-type well210in the CMOS region B and the P-type body305in the DMOS region C.

As shown in exampleFIG. 6, a P-type dopant may be implanted to form a P-type drift area140which serves as the base area. After forming the base area140, as shown in exampleFIG. 7, the base electrode160may be formed. Then, an implant process may be performed with respect to the active area including the CMOS, the DMOS, the low-voltage NMOS, and the low-voltage PMOS, thereby adjusting threshold voltage.

After that, a process for forming the CMOS and gates215,225and320of the DMOS is performed. At this time, the poly-emitter170of the poly-emitter type bipolar transistor according to embodiments may also be formed.

Then, the insulating layer may be formed over the entire surface of the substrate100. The insulating layer may be patterned so that the gate insulating layers are formed in the CMOS region B and the DMOS region C. At this time, the insulating layer of the bipolar transistor area A is completely removed.

After that, a polysilicon layer may be coated on the entire surface of the substrate. A photoresist pattern may be formed on the polysilicon layer. The photoresist pattern defines the CMOS, the gates215,225and320of the DMOS and the emitter area of the bipolar transistor. Then, the polysilicon layer is etched by using the photoresist pattern as an etch mask, thereby forming the gates215,225and320and the poly-emitter170.

The poly-emitter type bipolar transistor as shown in the region A of exampleFIG. 1may be obtained through the above processes. Then, an N-type LDD (lightly doped drain) area and a P-type LDD area may be formed in each MOS region. The sidewall and the spacer may be formed at both sides of the gates215,225and320.

After forming the spacer, the source/drain areas220and230may be formed in the CMOS region B. The P-type ion implantation area310, the first N-type ion implantation area315and the second N-type ion implantation area325may be formed in the DMOS region C.

Then, silicide may be formed on at least one of the poly-emitter170, the base electrode160, the gates215,225,320, the source/drain areas220and230, and the ion implantation areas310,315and325. In addition, processes for forming the insulating layer having a multi-layer structure, a contact plug, a metal interconnection and a protective layer can be further performed.

The BCD device including the poly-emitter type bipolar transistor according to embodiments can be obtained through the above processes. According to embodiments, the poly-emitter type bipolar transistor can be integrally formed with the BCD device in a single chip through the BCD process. Thus, a bipolar transistor having the superior frequency characteristics, high amplification gain and breakdown voltage, and wide operational range can be obtained.

It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.