Fluid ejection device

A fluid ejection device includes groups of firing cells, sharing a common fire signal and a common address selection mechanism, each firing cell having a drop generator for ejecting fluid and a dynamic memory addressable by the common address selection mechanism. Circuitry interfaces with the firing cells to allow the capture of data during two consecutive select cycles, then firing of all cells during a third cycle.

BACKGROUND

An inkjet printing system, as one embodiment of a fluid ejection system, can include a printhead, an ink supply that provides liquid ink to the printhead, and an electronic controller that controls the printhead. The printhead, as one embodiment of a fluid ejection device, ejects ink drops through a plurality of orifices or nozzles. The ink is projected toward a print medium, such as a sheet of paper, to print an image onto the print medium. The nozzles are typically arranged in one or more arrays, such that properly sequenced ejection of ink from the nozzles causes characters or other images to be printed on the print medium as the printhead and the print medium are moved relative to each other.

In a typical thermal inkjet printing system, the printhead ejects ink drops through nozzles by rapidly heating small volumes of ink located in vaporization chambers. The ink is heated with small electric heaters, such as thin film resistors referred to herein as firing resistors. Heating the ink causes the ink to vaporize and be ejected through the nozzles.

To eject one drop of ink, the electronic controller that controls the printhead activates an electrical current from a power supply external to the printhead. The electrical current is passed through a selected firing resistor to heat the ink in a corresponding selected vaporization chamber and eject the ink through a corresponding nozzle. Known drop generators include a firing resistor, a corresponding vaporization chamber, and a corresponding nozzle.

As inkjet printheads have evolved, the number of drop generators in a printhead has increased to improve printing speed and/or quality. The increase in the number of drop generators per printhead has resulted in a corresponding increase in the number of input pads required on a printhead die to energize the increased number of firing resistors. In one type of printhead, each firing resistor is coupled to a corresponding input pad to provide power to energize the firing resistor. One input pad per firing resistor becomes impractical as the number of firing resistors increases.

Manufacturers continue increasing the number of drop generators per input pad via reducing the number of input pads and/or increasing the number of drop generators on a printhead die. A printhead with fewer input pads typically costs less than a printhead with more input pads. Also, a printhead with more drop generators typically prints with higher quality and/or printing speed.

DETAILED DESCRIPTION

Reference will now be made to exemplary embodiments illustrated in the drawings, and specific language will be used herein to describe the same. As used herein, directional terms, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc, are used with reference to the orientation of the figures being described. Because components of various embodiments disclosed herein can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes only, and is not intended to be limiting. It is also to be understood that the exemplary embodiments illustrated in the drawings, and the specific language used herein to describe the same are not intended to limit the scope of the present disclosure. Alterations and further modifications of the features illustrated herein, and additional applications of the principles illustrated herein, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of this disclosure.

As used herein, the term “fluid ejection device” is intended to refer generally to any drop-on-demand fluid ejection system, and the terms “printhead” and “printer” are intended to refer to the same type of system. It is to be understood that where the description presented herein depicts or discusses an embodiment of an ink jet printing system, this is only one embodiment of a drop-on-demand fluid ejection system that can be configured in accordance with the present disclosure.

Where this disclosure refers to “ink”, that term is to be understood as just one example of a fluid that can be ejected from a drop-on-demand fluid ejection device in accordance with this disclosure. Many different kinds of liquid fluids can be ejected from drop-on-demand fluid ejection systems, such as food products, chemicals, pharmaceutical compounds, fuels, etc. The term “ink” is therefore not intended to limit the system to ink, but is only exemplary of a liquid that can be used. Additionally, the terms “print” or “printing” and “ink jet” are intended to generally refer to fluid ejection onto any substrate for any purpose, and are not limited to providing visible images on paper or the like.

FIG. 1illustrates one embodiment of an inkjet printing system20. Inkjet printing system20constitutes one embodiment of a fluid ejection system that includes a fluid ejection device, such as inkjet printhead assembly22, and a fluid supply assembly, such as ink supply assembly24having an ink reservoir38. The inkjet printing system20also includes a mounting assembly26, a media transport assembly28, and an electronic controller30. At least one power supply32provides power to the various electrical components of inkjet printing system20.

In one embodiment, inkjet printhead assembly22includes at least one printhead or printhead die40that ejects drops of ink through a plurality of orifices or nozzles34toward a print medium36so as to print onto print medium36. Printhead40is one embodiment of a fluid ejection device. Print medium36may be any type of suitable sheet material, such as paper, card stock, transparencies, Mylar, fabric, and the like. Typically, nozzles34are arranged in one or more columns or arrays such that properly sequenced ejection of ink from nozzles34causes characters, symbols, and/or other graphics or images to be printed upon print medium36as inkjet printhead assembly22and print medium36are moved relative to each other. While the following description refers to the ejection of ink from printhead assembly22, it is understood that other liquids, fluids or flowable materials, including clear fluid, may be ejected from printhead assembly22.

Mounting assembly26positions inkjet printhead assembly22relative to media transport assembly28and media transport assembly28positions print medium36relative to inkjet printhead assembly22. Thus, a print zone37is defined adjacent to nozzles34in an area between inkjet printhead assembly22and print medium36. In one embodiment, inkjet printhead assembly22is a scanning type printhead assembly. As such, mounting assembly26includes a carriage (not shown) for moving inkjet printhead assembly22relative to media transport assembly28to scan print medium36. In another embodiment, inkjet printhead assembly22is a non-scanning type printhead assembly. As such, mounting assembly26fixes inkjet printhead assembly22at a prescribed position relative to media transport assembly28. Thus, media transport assembly28positions print medium36relative to inkjet printhead assembly22.

Electronic controller or printer controller30typically includes a processor, firmware, and other electronics, or any combination thereof, for communicating with and controlling inkjet printhead assembly22, mounting assembly26, and media transport assembly28. Electronic controller30receives data39from a host system, such as a computer, and usually includes memory for temporarily storing data39. Typically, data39is sent to inkjet printing system20along an electronic, infrared, optical, or other information transfer path. Data39represents, for example, a document and/or file to be printed. As such, data39forms a print job for inkjet printing system20and includes one or more print job commands and/or command parameters.

In one embodiment, electronic controller30controls inkjet printhead assembly22for ejection of ink drops from nozzles34. As such, electronic controller30defines a pattern of ejected ink drops that form characters, symbols, and/or other graphics or images on print medium36. The pattern of ejected ink drops is determined by the print job commands and/or command parameters.

In one embodiment, inkjet printhead assembly22includes one printhead40. In another embodiment, inkjet printhead assembly22is a wide-array or multi-head printhead assembly. In one wide-array embodiment, inkjet printhead assembly22includes a carrier, which carries printhead dies40, provides electrical communication between printhead dies40and electronic controller30, and provides fluidic communication between printhead dies40and ink supply assembly24.

FIG. 2is a diagram illustrating a portion of one embodiment of a printhead die40. The printhead die40includes an array of printing or fluid ejecting elements42. Printing elements42are formed on a substrate44, which has an ink feed slot46formed therein. As such, ink feed slot46provides a supply of liquid ink to printing elements42. Ink feed slot46is one embodiment of a fluid feed source. Other embodiments of fluid feed sources include but are not limited to corresponding individual ink feed holes feeding corresponding vaporization chambers and multiple shorter ink feed trenches that each feed corresponding groups of fluid ejecting elements. A thin-film structure48has an ink feed channel54formed therein which communicates with ink feed slot46formed in substrate44. An orifice layer50has a front face50aand a nozzle opening34formed in front face50a. Orifice layer50also has a nozzle chamber or vaporization chamber56formed therein which communicates with nozzle opening34and ink feed channel54of thin-film structure48. A firing resistor52is positioned within vaporization chamber56and leads58electrically couple firing resistor52to circuitry controlling the application of electrical current through selected firing resistors. A drop generator60as referred to herein includes firing resistor52, nozzle chamber or vaporization chamber56and nozzle opening34.

During printing, ink flows from ink feed slot46to vaporization chamber56via ink feed channel54. Nozzle opening34is operatively associated with firing resistor52such that droplets of ink within vaporization chamber56are ejected through nozzle opening34(e.g., substantially normal to the plane of firing resistor52) and toward print medium36upon energization of firing resistor52.

Example embodiments of printhead dies40include a thermal printhead, a piezoelectric printhead, an electrostatic printhead, or any other type of fluid ejection device known in the art that can be integrated into a multi-layer structure. Substrate44is formed, for example, of silicon, glass, ceramic, or a stable polymer and thin-film structure48is formed to include one or more passivation or insulation layers of silicon dioxide, silicon carbide, silicon nitride, tantalum, polysilicon glass, or other suitable material. Thin-film structure48, also, includes at least one conductive layer, which defines firing resistor52and leads58. The conductive layer is made, for example, to include aluminum, gold, tantalum, tantalum-aluminum, or other metal or metal alloy. In one embodiment, firing cell circuitry, such as described in detail below, is implemented in substrate and thin-film layers, such as substrate44and thin-film structure48. Suitable materials and methods for fabricating the orifice layer are known to those of skill in the art.

FIG. 3is a diagram illustrating drop generators60located along ink feed slot46in one embodiment of printhead die40. Ink feed slot46includes opposing ink feed slot sides46aand46b. Drop generators60are disposed along each of the opposing ink feed slot sides46aand46b. A total of n drop generators60are located along ink feed slot46, with m drop generators60located along ink feed slot side46a, and n−m drop generators60located along ink feed slot side46b. In one embodiment, n equals 200 drop generators60located along ink feed slot46and m equals 100 drop generators60located along each of the opposing ink feed slot sides46aand46b. In other embodiments, any suitable number of drop generators60can be disposed along ink feed slot46. While the configuration shown inFIG. 3provides drop generators on both sides of the feed slot46, it is to be appreciated that other configurations can also be used. For example, drop generators can be provided on only one side of an associated feed slot. Alternatively, multiple ink feed slots (e.g. two or more) can be associated with a single printhead die, and these multiple slots can be individually coupled to separate fluid reservoirs (e.g. for multiple colors of ink), or share single reservoirs.

Ink feed slot46provides ink to each of the n drop generators60disposed along ink feed slot46. Each of the n drop generators60includes a firing resistor52, a vaporization chamber56and a nozzle34. Each of the n vaporization chambers56is fluidically coupled to ink feed slot46through at least one ink feed channel54. The firing resistors52of drop generators60are energized in a controlled sequence to eject fluid from vaporization chambers56and through nozzles34to print an image on print medium36.

FIG. 4is a high level diagram illustrating one embodiment of a firing cell70employed in one embodiment of printhead die40. Firing cell70includes a firing resistor52, a resistor drive switch72, and a memory circuit74. Firing resistor52is part of a drop generator60. Drive switch72and memory circuit74are part of the circuitry that controls the application of electrical current through firing resistor52. Firing cell70is formed in thin-film structure48and on substrate44.

In one embodiment, firing resistor52is a thin-film resistor and drive switch72is a field effect transistor (FET). Firing resistor52is electrically coupled to a fire line76and the drain-source path of drive switch72. The drain-source path of drive switch72is also electrically coupled to a reference line78that is coupled to a reference voltage, such as ground. The gate of drive switch72is electrically coupled to memory circuit74that controls the state of drive switch72.

Memory circuit74is electrically coupled to a data line80and enable lines82. Data line80receives a data signal that represents part of an image and enable lines82receive enable signals to control operation of memory circuit74. Memory circuit74stores one bit of data as it is enabled by the enable signals. The logic level of the stored data bit sets the state (e.g., on or off, conducting or non-conducting) of drive switch72. The enable signals can include one or more select signals and one or more address signals.

Fire line76receives an energy signal comprising energy pulses and provides an energy pulse to firing resistor52. In one embodiment, the energy pulses are provided by electronic controller30to have timed starting times and timed duration, resulting in timed end times, to provide a proper amount of energy to heat and vaporize fluid in the vaporization chamber56of a drop generator60. If drive switch72is on (conducting), the energy pulse heats firing resistor52to heat and eject fluid from drop generator60. If drive switch72is off (non-conducting), the energy pulse does not heat firing resistor52and the fluid remains in drop generator60.

Shown inFIG. 5is a lower level schematic diagram of one embodiment of a double data rate (DDR) firing cell120. The firing cell120includes a drive switch172electrically coupled to a firing resistor52. In one embodiment, drive switch172is a FET including a drain-source path electrically coupled at one end to one terminal of firing resistor52and at the other end to a reference line122. The reference line122is tied to a reference voltage, such as ground. The other terminal of firing resistor52is electrically coupled to a FIRE line124that delivers energy pulses to firing resistor52. The energy pulses energize firing resistor52if drive switch172is on (conducting).

The gate of drive switch172forms a storage node capacitance126that functions as a dynamic memory element to store data pursuant to the sequential activation of a pre-charge transistor128and a select transistor130. The storage node capacitance126is shown in dashed lines, as it is part of drive switch172. Alternatively, a capacitor separate from drive switch172can be used as a dynamic memory element.

The drain-source path and gate of pre-charge transistor128are electrically coupled to a pre-charge line132that receives a pre-charge signal. The gate of drive switch172is electrically coupled to the drain-source path of pre-charge transistor128and the drain-source path of select transistor130. The gate of select transistor130is electrically coupled to a select line134that receives a select signal SEL. A pre-charge signal PRE is one type of pulsed charge control signal. Another type of pulsed charge control signal is a discharge signal employed in embodiments of a discharged firing cell.

A data transistor136, a first address transistor138and a second address transistor140include drain-source paths that are electrically coupled in parallel. The parallel combination of data transistor136, first address transistor138and second address transistor140is electrically coupled between the drain-source path of select transistor130and reference line122. The serial circuit including select transistor130coupled to the parallel combination of data transistor136, first address transistor138and second address transistor140is electrically coupled across node capacitance126of drive switch172. The gate of data transistor136is electrically coupled to a latched data line166that receives a data signal ˜DATAIN. The gate of first address transistor138is electrically coupled to an address line144that receives address signals ˜ADDR1and the gate of second address transistor140is electrically coupled to a second address line146that receives address signals ˜ADDR2. The data signals ˜DATAIN and address signals ˜ADDR1and ˜ADDR2are active when low as indicated by the tilda (˜) at the beginning of the signal name. The node capacitance126, pre-charge transistor128, select transistor130, data transistor136, node capacitance168and address transistors138and140form a memory cell.

In operation, node capacitance126is pre-charged through pre-charge transistor128by providing a high level voltage pulse on pre-charge line132. In one embodiment, before or during the high level voltage pulse on pre-charge line132, a data signal ˜DATAIN is provided on data line164to set the state of data transistor136, and address signals ˜ADDR1and ˜ADDR2are provided on address lines144and146to set the states of first address transistor138and second address transistor140. A high level voltage pulse is provided on select line134to turn on select transistor130and node capacitance126discharges if data transistor136, first address transistor138and/or second address transistor140is on. Alternatively, node capacitance126remains charged if data transistor136, first address transistor138and second address transistor140are all off.

Firing cell120is an addressed firing cell if both address signals ˜ADDR1and ˜ADDR2are low and node capacitance126either discharges if data signal ˜DATAIN is high or remains charged if data signal ˜DATAIN is low. Pre-charged firing cell120is not an addressed firing cell if at least one of the address signals ˜ADDR1and ˜ADDR2is high and node capacitance126discharges regardless of the data signal ˜DATAIN voltage level. The first and second address transistors136and138comprise an address decoder, and data transistor136controls the voltage level on node capacitance126if firing cell120is addressed.

This firing cell embodiment includes a data latch transistor162that includes a drain-source path electrically coupled between data line164and latched data line166. The data line164receives a data signal ˜DATAIN, and data latch transistor162latches data into the firing cell to provide latched data signals ˜LDATIN. The ˜DATAIN and ˜LDATAIN signals are active when low as indicated by the tilde (˜) at the beginning of the signal name. The gate of data latch transistor162is electrically coupled to a data select line170that receives a data select signal DATASEL.

The data latch transistor162passes data from data line164to the latched data line166and a latched data storage node capacitance168via a high level data select signal. The data is latched onto the latched data line166and the latched data storage node capacitance168as the data select signal transitions from a high voltage level to a low voltage level. The latched data storage node capacitance168is shown in dashed lines, because it is part of data transistor136. Alternatively, a capacitor separate from data transistor136can be used to store latched data.

The data select line170can be electrically coupled to a select line such as the pre-charge line132. In other firing cells on the same printhead, the data select line170can be electrically coupled to other select lines that are not the pre-charge line132for the given firing cell. For example, in one embodiment, the gate of data latch transistor162can be electrically coupled to a pre-charge line of another fire group. In this embodiment, data signal ˜DATAIN is received by data line164and passed to latched data line166and latched data storage node capacitance168via data latch transistor162by providing a high level voltage pulse on the pre-charge line of the other fire group. Data latch transistor162is turned off to provide latched data signals ˜LDATAIN as the voltage pulse on the pre-charge line of the other fire group transitions from a high voltage level to a low level voltage. Storage node capacitance126is pre-charged through pre-charge transistor128via the high level voltage pulse on pre-charge line132. The high voltage pulse on pre-charge line132occurs after the transition of the voltage pulse on the pre-charge line of the other fire group from a high voltage level to a low voltage level.

In another embodiment, the gate of a data latch transistor, such as data latch transistor162, of a first pre-charged firing cell in the current fire group can be electrically coupled to a first pre-charge line of a first fire group that is different than the current fire group. Also, the gate of a data latch transistor, such as data latch transistor162, of a second pre-charged firing cell in the current fire group can be electrically coupled to a second pre-charge line of a second fire group that is different than the first fire group and the current fire group. Data line164provides data during the high voltage levels of the pre-charge signals of the first and second fire groups. Data latched into the first and second pre-charged firing cells is used via the pre-charge and select signals of the current fire group. Other aspects of the configuration and operation of a double data rate firing cell configured in this way are disclosed in United States Patent Application Publication no. 2007/0097178.

An array of double data rate firing cell circuits400is shown in the schematic diagram ofFIG. 6. This diagram represents only a subset of one fire group402, that might exist on a print head. It also shows an example row subgroup406containing a plurality of firing cells150that receive their address from the combination of first address signal414˜ADDR_1and second address signal416˜ADDR_2. The row subgroup406includes firing cells150a-150m. Other row subgroups would receive their first address and second address signals from a different combination of address lines. This array of double data rate firing cell circuits400also shows a clock latch circuit404.

Each of the firing cells150in fire group402are electrically coupled to data select line409to receive signal DATA SEL, pre-charge line408to receive pre-charge signal PRE, select line410to receive select signal SEL and fire line412to receive fire signal FIRE. Each of the firing cells150a-150min row subgroup406is electrically coupled to first address line414to receive first address signal ˜ADDR1and to second address line416to receive second address signal ˜ADDR2. The firing cells150receive signals and operate as described in the description ofFIG. 5.

The clock latch circuit404includes clock latch transistors418a-418n. The gate of each of the clock latch transistors418a-418nis electrically coupled to a clock line420to receive data clock signal DCLK. The drain-source path of each of the clock latch transistors418a-418nis electrically coupled to one of the data lines422a-422nto receive one of the data signals ˜D1-˜Dn, indicated at422. The other side of the drain source path of each of the clock latch transistors418a-418nis electrically coupled to firing cells150in fire group402and in all the other fire groups in double data rate firing cell circuit400via corresponding clock data lines424a-424n. Having all of the firing cells150in one data line group electrically coupled to a single one of the clock latch transistors418a-418nensures that there is enough capacitance on clocked data lines424a-424nto ensure that charge sharing by clocked data signals ˜DC1-˜DCn is small enough to maintain a minimum high voltage level in data latched into the firing cells150as the pre-charge signal transitions to a low voltage level and as the data clock signal DCLK at420transitions to a low voltage level.

Other aspects of the configuration and operation of a double data rate firing cell circuit configured like that shown inFIG. 6are disclosed in United States Patent Application Publication no. 2007/0097178. Each of the data signals ˜D1-˜Dn includes a first data bit during the first half of the high voltage pulse in data select signal DATASEL and a second data bit during the second, half of the high voltage pulse. Also, clock signal DCLK includes a high voltage pulse during the first half of the high voltage pulse in data select signal DATASEL. Thus the various double data rate firing cell circuit configurations latch two data bits from each of the data lines at each high voltage pulse in the data select signal.

Provided inFIG. 7is a schematic diagram of a fluid ejection firing array employing a plurality of dynamic memory based firing cells120. These firing cells can be like those ofFIG. 5. In the array ofFIG. 7, the firing cells are arranged in rows and columns in four fire groups W, X, Y, Z. For reference, the rows of the respective fire groups W, X, Y and Z are respectively identified as rows W0through W7, X0through X7, Y0through Y7and Z0through Z7. For convenience, the rows of firing cells are referred to as address rows or subgroups of firing cells, whereby each fire group includes a plurality of subgroups of firing cells.

Firing data signals are applied to data lines ˜D0through ˜D15that are associated with respective columns of all of the firing cells. The data lines are connected to the columns of the firing cell arrays via a first and second data bus454,456. While the data bus lines are shown as a single line, it is to be appreciated that this line represents a data bus including multiple individual data lines. The data lines provide direct driven signals and clocked data signals to alternating columns of the firing cell arrays. The clocked data signals are provided by the clock latch circuit452, which functions as described above with respect toFIG. 6. The data lines ˜D0through ˜D15provide the ˜DATAIN signal164that is shown inFIG. 5. Consequently, each of the data lines are connected to all of the gates of the data transistors of the firing cells120in an associated column, and each firing cell is connected to only one data line. Thus, each of the data lines provides energizing data to firing cells in multiple rows in multiple fire groups.

Address control signals are applied to address control lines ˜A0through ˜A4that are connected to the first and second address transistors (e.g. transistors138,140inFIG. 5) of the cells of the rows of the array. In this manner, rows of firing cells are addressed by suitable set up of the address control lines ˜A0through ˜A4. The address control lines can be connected to external control circuitry by appropriate interface pads. Alternatively, address generation can be provided by an address generator circuit450that is provided as part of the fluid ejection circuit array. In printer systems, on-board address generation involves providing an address generator on the printhead structure itself, rather than as part of the printer controller, and connected to the printhead by a plurality of address lines. Details regarding an on-board address generation system that can be used in the system disclosed herein are provided in U.S. patent application Ser. No. 10/827,163, which has been published as United States Patent Application Publication No. 2005/0230493, the disclosure of which is incorporated herein by reference in its entirety.

The address generator450comprises a cluster of circuits including a shift register, a programmable logic array, and direction control logic. The outputs from the address generator are provided on address lines ˜A0through ˜A4, which are typically routed to the firing cells in pairs. (e.g. ˜ADDR1and ˜ADDR2inFIG. 5). Six outputs from the Address Generator is a common number, but more or less can be used. Six addresses can be combined as pairs to create 15 different pair combinations (e.g. 1&2, 1&3, etc.).

Pre-charge signals PRE are applied via pre-charge select control lines PRE_W, PRE_X, PRE_Y AND PRE_Z that are associated with the respective fire groups W, X, Y AND Z, and are connected to external control circuitry by appropriate interface pads. Each of the precharge lines is connected to all of the precharge transistors (128inFIG. 5) in the associated fire group, and all firing cells in a fire group are connected to only one precharge line. This allows the state of the dynamic memory elements of all firing cells in a fire group to be set to a known condition prior to data being sampled. As can be seen inFIG. 7, the precharge lines for the firing groups W and X and groups Y and Z are tied together, and labeled PRE_W/X and PRE_Y/Z, respectively.

Select signals SEL are applied via select control lines SEL_W, SEL_X, SEL_Y and SEL_Z that are associated with the respective fire groups W, X, Y and Z, and are connected to external control circuitry. Each of the select control lines is connected to all of the select transistors (e.g. transistor130inFIG. 5) in the associated fire group, and all firing cells in a fire group are connected to only one select line. Thus, each row or subgroup of firing cells is connected to a common subset of the address and select control lines, namely the address control lines for the row position of the subgroup as well as the precharge select control line and the select control line for the fire group of the subgroup. Like the precharge lines, the select lines for the firing groups can also be tied together, and these are labeled SEL_W/X and SEL_Y/Z.

Heater resistor energizing FIRE signals are applied via fire lines FIRE_W, FIRE_X, FIRE_Y and FIRE_Z that are associated with the respective fire groups W, X, Y and Z, and each of the fire lines is connected to all of the heater resistors in the associated fire group. The fire lines are connected to external supply circuitry by appropriate interface pads, and all cells in a fire group share a common ground. Additionally, it can be seen that the fire lines for fire groups W and X are combined, as are the fire lines for groups Y and Z. The combination of these fire lines is made possible by a two cycle data capture method, as outlined more specifically below.

The PRE pulse is sent prior to assertion of the SEL signal. The PRE pulse defines a precharge time interval while the SEL signal defines a discharge time interval. Heater resistor energizing data is stored in the array one row of firing cells at time, one fire group at a time. The fire groups are selected iteratively. For each fire group a precharge pulse precedes a fire pulse.

A firing cell array like that ofFIG. 7can also be configured using firing cells having a different configuration than the firing cells ofFIGS. 4 and 5. For example, various embodiments of double data rate (DDR) firing cell control circuits can be used, such as are disclosed in United States Patent Application Publication no. 2007/0097178, The embodiments shown inFIGS. 9-15in the '178 application and the associated text are particularly relevant. The double data rate firing cell circuit configurations shown in the '178 application can latch two bits of data from each of the data lines at each high voltage pulse in a pre-charge signal. This allows nearly twice the number of firing resistors to be energized without changing the firing frequency or the number of input pads. This in turn allows a smaller number of data lines for a firing cell array having a given number of columns.

The firing array shown inFIG. 7embodies one approach to reducing the number of input pads on the pen in order to decrease the width of the pen relative to its length. For basic addressing of a minimum array of ink jet nozzles, a certain number of interconnects (pins) are used to provide the basic infrastructure to provide nozzle addressing capability. For example, viewingFIGS. 5 and 7together, each firing cell row includes connections to two address lines, and each column is connected to a unique data line. Further, each firing cell group inFIG. 7can be connected to unique precharge, select, datasel and fire lines. The provision of these connections affects the minimum number of interconnects for the fluid ejection device, which typically limits the smallest width of the device.

It has been recognized that reducing the minimum set of interconnects for basic addressing can allow for a smaller printhead width. There are a number of possible approaches that can be used for reducing the number of interconnects. The double data rate firing cell control circuits discussed above represent one approach to reducing the number of interconnects. The DDR circuit allows nearly twice the number of firing resistors to be energized without changing the firing frequency or the number of input pads. This in turn allows a smaller number of data lines for a firing cell array having a given number of columns. For example, a non DDR firing cell array having 8 data lines can be replaced with a DDR configuration having 4 data lines and 1 clock line.

Other approaches can include schemes to reduce the number of select lines while maintaining functionality. Under any approach, it is desired to increase the number of drop generators per input pad, which can allow a greater number of drop generators for a given width of the fluid ejection device. A printer, for example, with more drop generators typically prints with higher quality and/or printing speed. Also, a printhead with fewer input pads typically costs less to produce and to drive than a printhead with more input pads.

Shown inFIG. 8is a timing diagram outlining one method for controlling a fluid ejection cell array. This method allows a reduction in the number of FIRE lines for providing FIRE signals to a plurality of firing cell arrays. In the diagram ofFIG. 8, the blocks500along the top row represent data that is being transmitted to the firing cells in a double data rate (DDR) circuit. The indication C denotes clocked data, while the indication D represents direct driven data. The indication “a” represents data that is provided in the first half of the DDR latch sequence, and “b” denotes data that is provided in the second half of the latch sequence. Thus, Ca denotes clocked data that is provided during the first half of the DDR latch sequence, Da denotes direct driven data that is provided during the first half of the DDR latch sequence, and so on.

The labels S1-S5represent a group of select lines that are associated with the firing cell arrays. For example, in the configuration ofFIG. 7, four firing cell arrays are shown, each having a unique data-select line. The timing diagram ofFIG. 8is represents this configuration. The designations F3and F5on the left side of the figure represent two firing lines that are operable to provide FIRE signals for all data transmitted during select cycles S1-S4. The additional select line S5is provided because of the firing sequence. A nozzle cell is first precharged in one cycle, then discharged in the next cycle. Since the precharge of the next Fire group occurs at the same time as the select of the previous Fire group, these signals can be combined. However, there is always one more select line than Fire group because the precharge line of the first Fire group and the select line of the last Fire group cannot be combined with any contiguous Fire group.

The timing technique illustrated inFIG. 8allows the capture of data during two consecutive select cycles, then firing of all nozzles during a third cycle. The data latch timing is indicated by arrows502inFIG. 8. In this embodiment the first four bits of data for a given data line are captured and latched during the first two select cycles S1and S2via DDR, as indicated at502a-d. Likewise, the next four bits of data for a given data line are captured and latched during a second pair of select cycles S3and S4via, as indicated at502e-h. Following the first two select cycles, a FIRE signal F3, indicated at504, is given to fire the cells that captured data during the first two select cycles. A FIRE signal F5, indicated at506, is given to fire the cells that captured data during the second pair of select cycles. After the four data capture cycles and the corresponding fire cycles, the process repeats itself, as indicated by the new group of data500b.

The two consecutive data capture cycles represent twice the data that is typically captured before a FIRE cycle. In typical circuit addressing, data is usually passed to the printhead and latched during a select cycle just previous to the Fire pulse (S(n−1)). In the timing method shown inFIG. 8, data is also passed & latched on S(n−2). This data is latched and stored in the storage node capacitance (168inFIG. 5), which provides a memory node, during the S(n−1) cycle, until it is fired during S(n).

Referring toFIG. 5, the gate of the data transistor136can be provided with extra capacitance, so that sufficient charge can be stored for a sufficient length of time to be evaluated when the select transistor130is turned on. This provides the latched storage node capacitance168. A sufficient length of time for the data transistor to hold charge can be three select cycles, which covers the time for capture of five data bits. This will allow the nozzle arrays to store a first and second set of primitive data blocks before receiving a single Fire signal to drive both the first and second sets of primitives. For nozzles where data is latched during Sn−2, the “DATASEL” connection in this figure would be the n−2 Select signal. The state of the memory node (latched storage node capacitance168) will only affect the state of the drive transistor172when it is evaluated. This occurs when the select transistor130is turned on. With the select transistor turned on, a positive charge on the gate of the data transistor136will cause the drive transistor172to be discharged. If the charge on this gate is low, there would not be a discharge path for the drive transistor172, so it will remain charged.

The two-cycle data capture method for each fire group disclosed herein is used with a double data rate firing cell configuration. This two-cycle data capture method for each fire group enables a lower pin-count interface while still addressing enough nozzles because it reduces the number of FIRE lines. Specifically, this timing method allows the addressing of nozzles with fewer than select−1 Fire lines. This aspect is illustrated inFIG. 7, in which the FIRE lines FIRE_W and FIRE_X are combined through the connection to FIRE_3, and the FIRE lines FIRE_Y and FIRE_Z are combined through the connection to FIRE_5. Additionally, the precharge lines PRE_W and PRE_X are combined as PRE_W/X, as are PRE_Y and PRE_Z as PRE_Y/Z. The select lines SEL_W and SEL_X are combined as SEL_W/X, as are SEL_Y and SEL_Z as SEL_Y/Z. As another example, in one embodiment of a printhead that does not use the two-cycle data capture method outlined above, there would typically be 4 fire lines associated with 5 select lines. The two-cycle data capture method allows the same functionality with 5 select lines and only 2 fire lines. This is possible because the data latching circuit captures data for one fire line during multiple select cycles.

Another aspect of this data capture timing method is that it involves sending data with no fire pulse, and can involve sending a Fire pulse when no data was sent on one of two select cycles. The relationship of the Fire lines to the other aspects of a printer system is shown inFIG. 9. The system600generally includes a controller602that provides control signals604and data signals606to the firing array608of the printhead assembly610. The firing array can include multiple nozzle arrays612, labeled W-Z inFIG. 8. The controller is also interconnected to an energy supply circuit614, which provides Fire signals along Fire lines616in response to fire pulse initiation signals from the controller. As shown in this figure, each fire line can be associated with more than one firing array.

Typically, when no data is sent during a select cycle (i.e. no dots to print), the fire pulse is not initiated. In this system, the controller (e.g. an ASIC, Application Specific Integrated Circuit, associated therewith) can be programmed to send Fire pulse initiation signals even when data was not sent during the immediately preceding select cycle Sn−1, when data was sent on the prior select cycle (Sn−2).

The two-cycle data capture method disclosed herein allows a reduction in pincount (and thus a smaller printhead) because it allows the combination of previously separate FIRE lines. When this timing approach is combined with other firing cell circuit modifications that also reduce pincount, fluid ejection devices with very small pincounts are possible. The effect on pincount of the double data rate circuitry is discussed above. Another printhead circuit modification that facilitates pincount reduction is on-board address generation, which is discussed above.

Using a two-cycle data capture method as disclosed herein, in combination with onboard address generation, and the use of the double data rate clock latch circuit, the pincount for the printhead can be lower than otherwise. An example of a printhead700that employs all three of these pincount reduction strategies is shown inFIG. 10. This printhead includes a clock latch circuit702for the double data rate circuitry, and an address generator704for developing address signals on-board. Inputs to the address generator include the select lines716and the Csync line718. Outputs are Address lines that are typically routed to the nozzle arrays in pairs. (e.g. ˜ADDR1and ˜ADDR2inFIG. 5). Six outputs from the Address Generator is a common number, but more or less can be used. Six addresses can be combined as pairs to create 15 different pair combinations (e.g. 1&2, 1&3, etc.).

Since the outputs from an Address Generator are not always valid (sometimes the register is busy shifting, etc.), two Address Generators are used and configured such that one is always outputting valid address signals. This allows continuous printing, so that printing doesn't have to wait while the address generator is shifting. While the system prints using the nozzles associated with the “valid” address generator, the other is getting setup. The clock latch and address generation circuits provide data and control to multiple firing cell groups706, labeled W-Z, that are part of a firing array708.

In the embodiment ofFIG. 10, the two-cycle data capture method allows the use of two Fire lines710to control four firing cell groups, rather than four Fire lines. The use of the double data rate circuitry replaces a larger number of data lines with a smaller number of data lines712plus a data clock line714, and the on-board address generation replaces a larger number of address lines with a smaller number of select lines716and a CSYNC line718. Other lines that are shown, such as ground lines720, quiet ground line722, the TSR (thermal sense resistor) lines724, and the Identification line726perform functions that are understood by those of skill in the art.

In this embodiment, the printhead700has 18 total pins, and can address up to 336 ink jet nozzles in the firing array at an acceptable addressing frequency. In another embodiment, one of the data pins730is eliminated, and the firing array can still support204firing nozzles with 17 pins at an acceptable addressing frequency. As shown inFIG. 10, one half of the pins can be provided on one end of the printhead die, and the remainder on the opposing end, to further reduce the width of the die. More generally, the two-cycle data capture method disclosed herein, in combination with other pincount reduction approaches that allow fewer select lines and data lines, can allow fewer than 20 pins to drive more than 300 nozzles. This approach also allows addressing of small nozzle arrays (below ˜400 nozzles), with a very low interconnect count. Reduction in pincount also allows a favorable silicon aspect ratio. Because the pincount is low and the circuit layout is compact, the length-to-width ratio (L to W inFIG. 10) is larger—e.g. from more than 5:1 to more than 10:1 in a printhead circuit with Select and Fire lines.

It is to be understood that the above-referenced arrangements are illustrative of the application of the principles disclosed herein. It will be apparent to those of ordinary skill in the art that numerous modifications can be made without departing from the principles and concepts of this disclosure, as set forth in the claims.