Array substrate and manufacturing method thereof, display panel and manufacturing method thereof, and display device

The present disclosure provides an array substrate, a display panel, manufacturing methods thereof and a display device. The array substrate includes a display region and a non-display region. The non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The array substrate further includes a plurality of signal connection lines for connecting driving lines. The signal connection lines include a first connection line, a portion of which is arranged at the peripheral region and another portion of which is arranged at the sealant region.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is the U.S. national phase of PCT Application No. PCT/CN2015/079201 filed on May 18, 2015, which claims a priority of the Chinese Patent Application No. 201410735210.5 filed on Dec. 5, 2014, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof and a display device.

BACKGROUND

Thin film transistor liquid crystal display (TFT-LCD) mainly includes a color filter (CF) substrate, an array substrate and liquid crystals filled between the two substrates. A sealant is applied at peripheries of the two substrates so as to adhere them together and seal up the liquid crystals therebetween. Usually, the array substrate is of an area slightly greater than the color filter substrate, and corresponding room is left at its additional portion mainly for the bonding of a gate driving unit such as a gate integrated circuit (IC) and a source driving unit such as a source IC.

Referring toFIGS. 1-3,FIG. 1is a schematic view of an existing array substrate,FIG. 2is an enlarged view of a corner of the array substrate inFIG. 1, andFIG. 3is a sectional view taken along a plane A-A′ inFIG. 2.

As shown inFIG. 1, an array substrate100includes a display region101and a non-display region102arranged at a periphery of the display region. The non-display region102includes a sealant region1021arranged at a periphery of the display region101and a peripheral region1022arranged at a periphery of the sealant region1021. A peripheral layout gate (PLG) line202is arranged at the peripheral region1022. The PLG line202is a line for transmitting a voltage and a control signal desired for a gate electrode from a source driving unit such as a source IC to a gate driving unit such as a gate IC, so as to ensure a normal operation of the gate IC. InFIGS. 2-3, 201represents a base substrate,202represents the PLG line,203represents a passivation layer,204represents a PLG connection line, and205represents a via-hole in the passivation layer203. As shown inFIG. 3, the PLG connection line204is connected to the PLG line202through the via-hole205in the passivation layer203, so that the PLG line202is connected to the driving unit (the gate driving unit or the source driving unit). As shown inFIG. 1, an existing PLG line202is arranged at an edge of the array substrate and easily damaged due to such factors as external force, scratch or corrosion. As a result, it is impossible for the gate driving unit to receive the desired voltage and signal, and abnormal display will occur.

SUMMARY

In view of this, the present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof and a display device, to solve the problem that the existing PLG line is easily damaged.

In order to solve the above technical problem, the present disclosure provides in one embodiment an array substrate, including a display region and a non-display region. The non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The array substrate further includes a plurality of signal connection lines for connecting driving units. The signal connection lines include a first connection line, a portion of the first connection line is arranged at the peripheral region and another portion of the first connection line is arranged at the sealant region.

Alternatively, the array substrate further includes a passivation layer arranged at the non-display region, and the first connection line is arranged on the passivation layer.

Alternatively, the first connection line includes a first segment, a second segment and a third segment connected in sequence, the first segment and the third segment are arranged at the peripheral region, and the second segment is arranged at the sealant region.

Alternatively, the first connection line includes a first subsection and a second subsection spaced apart from each other, a portion of the first subsection and a portion of the second subsection are arranged at the peripheral region, and another portion of the first subsection and another portion of the second subsection are arranged at the sealant region.

Alternatively, the array substrate further includes a pixel electrode layer arranged at the display region, and the first connection line is arranged at a layer, and made of a material, identical to the pixel electrode layer.

Alternatively, the signal connection lines further include a second connection line arranged at the peripheral region and connected in parallel to the first connection line.

Alternatively, the array substrate further includes a plurality of conductive layers arranged at the display region, and the second connection line is arranged at a layer, and made of a material, identical to one of the conductive layers.

Alternatively, the conductive layers include a gate metal layer and a source-drain metal layer, the second connection line is arranged at a layer, and made of a material, identical to the gate metal layer or source-drain metal layer, and the second connection line is connected in parallel to the first connection line through a via-hole.

The present disclosure further provides in one embodiment a display panel including the above-mentioned array substrate, a color filter substrate, and a sealant arranged between the array substrate and the color filter substrate.

Alternatively, the array substrate further includes a passivation layer arranged at the non-display region, and the first connection line is arranged on the passivation layer.

Alternatively, the first connection line includes a first subsection and a second subsection spaced apart from each other, a portion of the first subsection and a portion of the second subsection are arranged at a peripheral region, and another portion of the first subsection and another portion of the second subsection are arranged at a sealant region, the color filter substrate further includes a display region, a sealant region arranged at a periphery of the display region and third connection lines arranged at the sealant region, and each of the third connection lines connects the first subsection and the second subsection of the first connection line through conductive metallic balls in the sealant.

Alternatively, the array substrate further includes a pixel electrode layer arranged at the display region of the array substrate, and the first connection line is arranged at a layer, and made of a material, identical to the pixel electrode layer.

Alternatively, the color filter substrate further includes a common electrode layer at the display region of the color filter substrate, and the third connection line is arranged at a layer, and made of a material, identical to the common electrode layer.

The present disclosure provides in one embodiment a method for manufacturing an array substrate. The array substrate includes a display region and a non-display region, and the non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The method includes a step of forming signal connection lines for connecting driving units. The signal connection lines include a first connection line, a portion of the first connection line is arranged at the peripheral region and another portion of the first connection line is arranged at the sealant region.

Alternatively, before forming the first connection line, the method further includes: forming a second connection line arranged at the peripheral region; forming a passivation layer arranged at the non-display region; and forming a via-hole through the passivation layer. The step of forming the first connection line includes forming the first connection line and a pixel electrode layer at the display region by a single patterning process, and the first connection line is connected in parallel to the second connection line through the via-hole.

Alternatively, the first connection line includes a first segment, a second segment and a third segment connected in sequence, the first segment and the third segment are arranged at the peripheral region, and the second segment is arranged at the sealant region.

Alternatively, the first connection line includes a first subsection and a second subsection spaced apart from each other, a portion of the first subsection and a portion of the second subsection are arranged at the peripheral region, and another portion of the first subsection and another portion of the second subsection are arranged at the sealant region.

The present disclosure provides in one embodiment a method for manufacturing a display panel, including steps of forming an array substrate using the above-mentioned method, and forming a color filter substrate.

Alternatively, the first connection line includes a first subsection and a second subsection spaced apart from each other, a portion of the first subsection and a portion of the second subsection are arranged at a peripheral region, and another portion of the first subsection and another portion of the second subsection are arranged at a sealant region, the step of forming the color filter substrate includes forming third connection lines at a sealant region of the color filter substrate. After forming the array substrate and the color filter substrate, the method further includes adhering the array substrate to the color filter substrate with a sealant containing conductive metallic balls, and each of the third connection lines connects the first subsection and the second subsection of the first connection line through the conductive metallic balls.

The present disclosure further provides in one embodiment a display device including the above-mentioned display panel.

The above technical solutions of the present disclosure have following benefits. A portion of the first connection line for connecting the driving units is arranged at the sealant region, and another portion thereof is arranged at the peripheral region. After the array substrate is arranged opposite to the color filter substrate to form a cell, the first connection line at the sealant region may be covered by the sealant at the sealant region. As a result, it is able to decrease the possibility of damaging the first connection line, thereby to reduce the phenomenon of abnormal display of the display device including the array substrate due to the damaged first connection line.

DETAILED DESCRIPTION

In order to make the technical problem to be solved, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in conjunction with the drawings and embodiments.

Referring toFIG. 4, which is a schematic view showing an array substrate according to a first embodiment of the present disclosure, the array substrate includes a display region101and a non-display region102. The non-display region102includes a sealant region1021arranged at a periphery of the display region101and a peripheral region1022arranged at a periphery of the sealant region1021. A sealant is arranged at the sealant region1021, so that the array substrate and a color filter substrate may be arranged opposite to each other to form a cell. The array substrate further includes a plurality of signal connection lines for connecting driving units400. The signal connection lines include a first connection line301. A portion of the first connection line301is arranged at the peripheral region1022and another portion of the first connection line301is arranged at the sealant region1021.

The driving units400include gate driving units and source driving units. The signal connection line may be configured to connect one gate driving unit and one source driving unit, or connect two source driving units or two gate driving units. Generally, one driving unit400arranged at an upper side of the array substrate is the source driving unit, while one driving unit400arranged at a left side of the array substrate is the gate driving unit.

Generally, signals transmitted via the signal connection lines include Start Vertical (STV, i.e., a start signal for one frame), a Clock Pulse Vertical (CPV, i.e., a start signal for one row), an Output Enable (OE), a VGH (i.e., a high voltage signal applied to a TFT), and a VGL (a low voltage signal applied to the TFT), and so on.

Since a portion of the first connection line301for connecting the driving units is arranged at the sealant region1021, thus, the first connection line301at the sealant region1021may be covered by the sealant at the sealant region1021after the array substrate is arranged opposite to the color filter substrate to form a cell. As a result, it is able to decrease the possibility of damaging the first connection line301, thereby to reduce the phenomenon of abnormal display of the display device including the array substrate due to the damaged first connection line301.

Generally, the array substrate further includes a passivation layer, and alternatively, the first connection line301is arranged on the passivation layer, so as to be connected to the driving units400conveniently.

In addition, the array substrate includes a pixel electrode layer arranged at the display region101. Alternatively, the first connection line301may be arranged at a layer, and made of a material, identical to the pixel electrode layer, i.e., the first connection line301and the pixel electrode layer may be formed by a single patterning process, so as to reduce process steps and improve the production efficiency. Of course, in some other embodiments of the present disclosure, the first connection line301may also be formed by a separate patterning process.

Alternatively, in some other embodiments of the present disclosure, the first connection line301may also be arranged under the passivation layer and connected to the driving units400through a via-hole.

As shown inFIG. 4, apart from the first connection line301, the signal connection lines for connecting the driving units further include a fourth connection line302arranged at the peripheral region. The signal connection line configured to connect the source driving unit and the gate driving unit is the first connection line301(a portion of which is arranged at the sealant region1021), while the signal connection line adopted at other position is the fourth connection line302at the peripheral region.

The array substrate further includes a plurality of conductive layers arranged at the display region101, and the fourth connection line302may be arranged at a layer, and made of a material, identical to one of the conductive layers. The conductive layer may be a gate metal layer or a source-drain metal layer. The fourth connection line302is connected to the driving unit400through a via-hole.

As shown inFIG. 4, merely the first connection line301(a portion of which is arranged at the sealant region1021) may be protected, while it is difficult to effectively protect the fourth connection line302at the peripheral region from being damaged due to such factors as external force, scratch or corrosion.

Referring toFIG. 5, which is a schematic view showing an array substrate according to a second embodiment of the present disclosure, all the signal connection lines are the first connection lines301. With this structure, all the signal connection lines may be protected. In addition, at this time a small area is occupied by the signal connection lines at the peripheral region1022, so it is able to reduce a size of the peripheral region1022of the array substrate, thereby to provide a narrow bezel.

Referring toFIG. 6, which is a schematic view showing an array substrate according to a third embodiment of the present disclosure, the array substrate differs from that inFIG. 4in that, the signal connection lines further include a second connection line303arranged at the peripheral region and connected in parallel to the first connection line301.

The array substrate further includes a passivation layer and a plurality of conductive layers arranged at the display region. Alternatively, the second connection line303may be arranged at a layer, and made of a material, identical to one of the conductive layers.

Alternatively, the conductive layers include a gate metal layer and a source-drain metal layer; the second connection line303may be arranged at a layer, and made of a material, identical to the gate metal layer or the source-drain metal layer. The second connection line303is connected in parallel to the first connection line301through a via-hole205.

With this structure, double assurance for signal transmission is provided, i.e., even if the second connection line303is damaged, the signal can still be transmitted normally via the first connection line301connected in parallel to the second connection line303; even if the first connection line301has a failure, the signal can still be transmitted normally via the second connection line303connected in parallel to the first connection line301.

As shown inFIG. 6, merely the signal connection line configured to connect the source driving unit and the gate driving unit is in form of the first connection line301and the second connection line303connected in parallel to each other, while the signal connection line at other position is the fourth connection line302at the peripheral region.

Referring toFIG. 7, which is a schematic view showing an array substrate according to a fourth embodiment of the present disclosure, each of the signal connection lines is in form of the first connection line301and the second connection line303connected in parallel to each other.

The present disclosure further provides in one embodiment a display panel including an array substrate and a color filter substrate. The array substrate may be any one of the array substrates of the above-mentioned embodiments.

Referring toFIGS. 8-9,FIG. 8is a schematic view showing a display panel according to a fifth embodiment of the present disclosure andFIG. 9is a sectional view taken along a plane B-B′ inFIG. 8, the display panel includes an array substrate100, a color filter substrate600, and a sealant500arranged therebetween. The array substrate100includes a display region101and a non-display region. The non-display region includes a sealant region1021arranged at a periphery of the display region101and a peripheral region1022arranged at a periphery of the sealant region1021. The sealant500is arranged at the sealant region1021, so that the array substrate100and the color filter substrate600may be arranged opposite to each other to form a cell. The array substrate further includes a plurality of signal connection lines for connecting driving units400. The signal connection lines include a first connection line301. The first connection line301includes a first segment3011, a second segment3012and a third segment3013which are connected in sequence. The first segment3011and the third segment3013are arranged at the peripheral region1022of the array substrate, and the second segment3012is arranged at the sealant region1021of the array substrate.

As shown inFIG. 9, the first connection line301at the sealant region1021may be covered by the sealant500, so as to be protected from being damaged due to such factors as external force, scratch or corrosion. InFIG. 9, 201represents a base substrate of the array substrate,203represents the passivation layer,301represents the first connection line,601represents a base substrate of the color filter substrate, and602represents a planarization layer.

In this embodiment, the signal connection lines further include a second connection line303arranged at the peripheral region1022and connected with the first connection line301. The second connection line303is connected in parallel to the first connection line301through a via-hole205.

Referring toFIGS. 10-11,FIG. 10is a schematic view showing a display panel according to a sixth embodiment andFIG. 11is a sectional view taken along a plane C-C′ inFIG. 10, in this embodiment, the display panel includes an array substrate100, a color filter substrate600, and a sealant500arranged therebetween. The array substrate100includes a display region (which is also referred as a first display region)101and a non-display region. The non-display region includes a sealant region (which is also referred as a first sealant region)1021arranged at a periphery of the display region101and a peripheral region1022arranged at a periphery of the sealant region1021. The sealant500is arranged at the sealant region1021, so that the array substrate100and the color filter substrate600may be arranged opposite to each other to form a cell. The array substrate further includes a plurality of signal connection lines for connecting driving units400. The signal connection lines include a first connection line301. The first connection line301includes a first subsection3014and a second subsection3015spaced apart from each other. A portion of the first subsection3014and a portion of the second subsection3015are arranged at the peripheral region1022, and another portion of the first subsection3014and another portion of the second subsection3015are arranged at the sealant region1021.

The color filter substrate600includes a second display region, a second sealant region arranged at a periphery of the second display region, and third connection lines603arranged at the second sealant region. Each of the third connection lines603connects the first subsection3014and the second subsection3015of the first connection line301through conductive metallic balls501in the sealant500.

With this structure, the conductive metallic balls501in the sealant500may enable the first connection line301arranged at the array substrate100to be electrically connected to the third connection line603arranged at the color filter substrate600. A signal applied to the second subsection3015of the first connection line301may be transmitted to the color filter substrate600through the conductive metallic balls501and then transmitted back to the first subsection3014at the array substrate100through the conductive metallic balls501.

The conductive metallic balls501may be conductive golden balls.

InFIG. 11, 201represents a base substrate of the array substrate,601represents a base substrate of the color filter substrate, and602represents a planarization layer. Alternatively, the array substrate100further includes a passivation layer203arranged at its non-display region, and the first connection line301is arranged on the passivation layer203. The array substrate further includes a pixel electrode layer arranged at its display region, and alternatively, the first connection line301is arranged at a layer, and made of a material, identical to the pixel electrode layer.

When the display panel is of a twisted nematic (TN) type, the color filter substrate600further includes a common electrode layer arranged at its display region. Alternatively, the third connection line603may be arranged at a layer, and made of a material, identical to the common electrode layer.

The present disclosure further provides in one embodiment a display device including the above-mentioned display panel.

The present disclosure further provides in one embodiment a method for manufacturing an array substrate. The array substrate includes a display region and a non-display region, and the non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The method includes a step of forming signal connection lines for connecting driving units. The signal connection lines include a first connection line. A portion of the first connection line is arranged at the peripheral region and another portion of the first connection line is arranged at the sealant region.

Alternatively, before forming the first connection line, the method further includes: forming a second connection line arranged at the peripheral region, forming a passivation layer arranged at the non-display region, and forming a via-hole through the passivation layer.

The step of forming the first connection line includes: forming the first connection line and a pixel electrode layer at the display region by a single patterning process, with the first connection line being connected in parallel to the second connection line through the via-hole.

The present disclosure further provides in one embodiment a method for manufacturing a display panel, including steps of forming an array substrate and forming a color filter substrate. The array substrate includes a display region and a non-display region, and the non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The step of forming the array substrate includes: forming signal connection lines for connecting driving units. The signal connection lines include a first connection line. A portion of the first connection line is arranged at the peripheral region and another portion of the first connection line is arranged at the sealant region.

Alternatively, the step of forming the first connection line includes forming the first connection line and a pixel electrode layer arranged at the display region by a single patterning process. The first connection line includes a first subsection and a second subsection spaced apart from each other. A portion of the first subsection and a portion of the second subsection are arranged at the peripheral region, and another portion of the first subsection and another portion of the second subsection are arranged at the sealant region.

The step of forming the color filter substrate includes forming third connection lines at a sealant region of the color filter substrate.

After forming the array substrate and the color filter substrate, the method further includes adhering the array substrate to the color filter substrate with a sealant containing conductive metallic balls, and each of the third connection lines connecting the first subsection and the second subsection of the first connection line through the conductive metallic balls.

Referring toFIG. 12, which is a flow chart of a method for manufacturing a display panel according to a seventh embodiment of the present disclosure, the method includes the following steps.

Step S121: at an array substrate side, forming a second connection line at a non-display region of the array substrate. The non-display region of the array substrate includes a sealant region and a peripheral region arranged at a periphery of the sealant region, and the second connection line is arranged at the peripheral region.

Step S122: forming a passivation layer at the non-display region of the array substrate, and forming a via-hole through the passivation layer.

Step S123: forming a first connection line on the passivation layer. The first connection line includes a first subsection and a second subsection spaced apart from each other, a portion of the first subsection and a portion of the second subsection are arranged at the peripheral region, and another portion of the first subsection and another portion of the second subsection are arranged at the sealant region. The first connection is connected in parallel to the second connection line through the via-hole.

The first connection line and the pixel electrode layer at the display region of the array substrate may be formed by a single patterning process.

Step S124: at a color filter substrate side, forming a third connection line at a non-display region of the color filter substrate. When the display panel is of a TN type, the third connection line and the common electrode layer on the color filter substrate by a single patterning process.

Step S125: arranging the array substrate and the color filter substrate opposite to each other to form a cell in vacuum during the procedure of One Drop Filling (ODF), and adhering the array substrate to the color filter substrate with a sealant. The sealant contains conductive metallic balls, and each of the third connection line connects the first subsection and the second subsection of the first connection line through the conductive metallic balls in the sealant.

With this structure, the conductive metallic balls in the sealant may enable the first connection line arranged at the array substrate to be electrically connected to the third connection line arranged at the color filter substrate. A signal applied to the second subsection of the first connection line may be transmitted to the color filter substrate through the conductive metallic balls and then transmitted back to the first subsection at the array substrate through the conductive metallic balls.

In this embodiment, the signal connection lines for transmitting the signals may be arranged at both the array substrate and the color filter substrate.

According to this embodiment, a portion of the first connection line at the array substrate is covered by the sealant, so it may be protected effectively. In addition, the array substrate include the first connection line and the second connection line connected in parallel to each other, so it is able to provide double assurance.

Referring toFIG. 13, which is a flow chart of a method for manufacturing a display panel according to an eighth embodiment of the present disclosure, the method includes the following steps.

Step S131: at an array substrate side, forming a second connection line at a non-display region of the array substrate. The non-display region of the array substrate includes a sealant region and a peripheral region arranged at a periphery of the sealant region, and the second connection line is arranged at the peripheral region.

Step S132: forming a passivation layer at the non-display region of the array substrate, and forming a via-hole through the passivation layer.

Step S133: forming a first connection line on the passivation layer. The first connection line includes a first segment, a second segment and a third segment connected in sequence. The first segment and the third segment are arranged at a peripheral region of the array substrate, and the second segment is arranged at a sealant region of the array substrate. The first connection line is connected in parallel to the second connection line through the via-hole.

The first connection line and the pixel electrode layer at the display region of the array substrate may be formed by a single patterning process.

Step S134: arranging the array substrate and the color filter substrate opposite to each other to form a cell in vacuum during the procedure of One Drop Filling (ODF), and adhering the array substrate to the color filter substrate with a sealant.

In this embodiment, the signal connection lines for transmitting signals are merely arranged at the array substrate.

According to this embodiment, a portion of the first connection line at the array substrate is covered by the sealant, so it may be protected effectively. In addition, the array substrate include the first connection line and the second connection line connected in parallel to each other, so it is able to provide double assurance.