Method of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells

A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a method for forming thin oxide regions 
particularly in electrically erasable and programmable read-only memory 
cells. 
2. Discussion of the Related Art 
In conventional electrically erasable and programmable read-only memory 
cells, technically known as EEPROMs, it is advantageous to delimit an 
oxide portion in which it is possible to grow a thinner oxide, so that the 
electric writing and erasure of the cell can occur through such portion. 
One of the problems encountered with these EEPROM devices is caused by the 
lithographic process. As is known to those skilled in the art, the 
dimensional limit for a given technology is set by the photolithographic 
method employed, through which it is possible to define structures whose 
dimensions exceed a given value. 
Furthermore, radiation-induced damage due to so-called "dry etching" often 
occurs in these devices. This type of etching does not allow removal of 
the gate oxide from a surface portion which is greater than the desired 
tunnel dimensions. 
In addition to the problem which arises from the type of etching, it is 
also very difficult to etch the oxide on limited areas, because one must 
work at the limit of what is technologically feasible. 
Another problem associated with conventional EEPROM cells is related to 
controlling the dimensions of the tunnel portion, whose variability 
affects the capacitive coupling of the cell and thus its electric 
performance. 
SUMMARY OF THE INVENTION 
Accordingly, an aim of the present invention is to substantially eliminate 
or substantially reduce the problems described above in connection with 
conventional EEPROM cells. 
Another aim is to provide a method for producing thin oxide structures for 
applications in EEPROM cells which substantially reduces, and possibly 
eliminates, the problems related to the limits of the photolithographic 
process. 
Within the scope of the above aims, an object of the present invention is 
to provide a method which improves efficiency in controlling the area of 
the thin oxide element. 
Another object of the present invention is to provide a method which is 
highly reliable, relatively easy to perform and can be performed at 
competitive costs. 
This aim, the objects mentioned and others which will become apparent 
hereinafter to those skilled in the art are achieved by a method for 
producing tunnel structures in EEPROM cells. The method includes the 
following steps: defining an active area on a doped silicon substratum by 
growing gate oxide regions; generating protective portions of a first 
layer of radiation-sensitive material on the active area and gate oxide 
regions; heavily doping the active area; removing the protective portions 
of the first layer of radiation-sensitive material; growing a first oxide 
layer on the active area; generating protective portions of a second layer 
of radiation sensitive-material which surround an opening in the active 
area; lightly doping the active area; removing a portion of the first 
oxide layer within the opening; removing the protective portions of the 
second layer of radiation-sensitive material; and growing a second oxide 
layer on the active area. 
Further characteristics and advantages of the invention will become 
apparent from a reading of the description of a preferred but not 
exclusive embodiment of a method for producing tunnel structures in 
electrically erasable and programmable read-only memory cells, in the 
particular example, with a single polysilicon level, illustrated only by 
way of a non-limiting example in the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION 
Hereinafter, the term "to mask" or "masking" defines the conventional 
photolithographic process by means of which the radiation-sensitive 
material is made soluble or insoluble by exposure to a source of radiation 
which is controlled and filtered by a mask which bears the layout of the 
individual layer. In most practical cases, the radiation-sensitive 
material is constituted by light-sensitive resin, technically termed 
photoresist, whereas the radiation source is usually an electromagnetic 
radiation source, generally in the visible-light range. The term "etching" 
defines the chemical incision of the layers of a calibration structure. 
The term "doping" defines the introduction of impurities by means of 
high-energy implantation, by means of gaseous diffusion or other 
equivalent implantation processes. 
With reference to FIGS. 1a to 1k, a conventional method for producing a 
tunnel structure includes the following steps: A preparation step, shown 
in FIG. 1a, wherein an active area 2 is delimited in EEPROM cells on a 
doped silicon substratum S by growing gate oxide regions 1; 
A first deposition step, shown in FIG. 1b, wherein a layer 3 of 
radiation-sensitive material is deposited on the device; the layer 3 is 
subsequently masked and its soluble portions are removed, leaving 
protective portions 3 on the gate oxide regions 1 which limit each EEPROM 
cell; 
A first doping step, shown in FIG. 1c, wherein a light n-doping is 
performed on the active area 2 of the EEPROM cells. 
A first cleaning step, shown in FIG. 1d, wherein the protective portions 3 
of radiation-sensitive material are removed from the gate oxide regions 1; 
A diffusion step, shown in FIG. 1e, wherein the lightly doped drains are 
diffused; 
A first growth step, shown in FIG. 1f, wherein a layer 4 of gate oxide is 
grown on the active area 2; 
A second deposition step, shown in FIG. 1g, wherein a layer 5 of 
radiation-sensitive material is deposited on the device and is 
subsequently masked; soluble portions thereof are then removed, leaving 
open a central portion 10 of the active area 2 of the cell; 
An etching step, shown in FIG. 1h, wherein the gate oxide 4 is removed from 
the open portion 10 exposed during the second deposition step; 
A second cleaning step, shown in FIG. 1i, wherein the protective portions 5 
of radiation-sensitive material are removed; 
A second growth step, shown in FIG. 1j, wherein another layer of oxide 6 is 
grown on the active area 2; and 
A third deposition step, shown in FIG. 1k, wherein a layer 7 of polysilicon 
is deposited on the device and subsequently masked and partially removed 
by etching yielding the floating gate electrode. 
With reference to FIGS. 2a to 2l, wherein like reference characters denote 
similar features to those of FIGS. 1a-1k, a method for producing tunnel 
structures according to the present invention includes the following 
steps: 
A preparation step (FIG. 2a) wherein an active area 2 is delimited on a 
doped silicon substratum S, by growing gate oxide regions 1, in the EEPROM 
cells; 
A first deposition step (FIG. 2b) wherein a layer 3 of radiation-sensitive 
material is deposited on the device and is subsequently masked; the 
soluble portions thereof are then removed, leaving protective portions 3 
on the active area 2 and on the gate oxide regions 1, limiting each EEPROM 
cell; 
A first doping step (FIG. 2c) wherein heavy doping is performed on the 
active area 2 of the EEPROM cells; 
A first cleaning step (FIG. 2d) wherein the protective portions 3 of 
radiation-sensitive material are removed from the active area 2 and from 
the gate oxide regions 1; 
A diffusion step (FIG. 2e) wherein the heavily doped drains are diffused; 
A first growth step (FIG. 2f) wherein a gate oxide layer 4 is grown on the 
active area 2; 
A second deposition step (FIG. 2g) wherein a layer 5 of radiation-sensitive 
material is deposited on the device and is subsequently masked; soluble 
portions thereof are then removed, leaving open a central portion 10 of 
the active area 2 of the cell; 
A second doping step (FIG. 2h) wherein light doping is performed on the 
active area 2 of each memory cell; 
An etching step (FIG. 2i) wherein the gate oxide 4 is removed from the 
central portion 10 exposed during the second deposition step; 
A second cleaning step (FIG. 2j) wherein the protective portions 5 of 
radiation-sensitive material are removed; 
A second growth step (FIG. 2k) wherein a further oxide layer 6 is grown on 
the active area 2; and 
A third deposition step (FIG. 2l) wherein a layer 7 of polysilicon is 
deposited on the device and is subsequently masked and partially removed 
by etching, yielding the floating gate electrode. 
In this manner a tunnel oxide portion 13 is obtained whose dimensions are 
smaller than the resolution of the photolithographic method used. 
The so-called "enhanced oxidation effect", is exploited during the 
definition of the tunnel oxide portion 13, i.e. the phenomenon by virtue 
of which greater oxidation occurs where substratum doping is higher. 
Accordingly, the gate oxide 14 which grows above the more heavily doped 
portions n+ is thicker than the oxide 15 grown upon the less heavily doped 
portions. The thickness of approximately 15 nanometers makes the oxide 14 
grown in this manner an excellent insulator. 
The high thickness of the gate oxide 14 above the more heavily doped 
portions n+ is achieved in the two following steps which are ensured by 
two different and easily controllable effects: the first step, which is 
the first doping step (FIG. 2c), wherein lateral diffusion of the heavy 
doping occurs; and the second step (FIG. 2k), which uses the enhanced 
oxidation effect wherein the oxide thickness is different above the 
heavily doped portions than above the portions with less heavy n- doping 
implantation. 
The electrical operating characteristics of the cell produced by the method 
of the present invention are better than those of a conventional cell. 
Advantageously, the tunnel oxide portions obtained with the method 
according to the invention have dimensions which are smaller than the 
resolution of the photolithographic method employed. 
The provision of a tunnel with such dimensions also leads to a benefit in 
the capacitive couplings of the cell, allowing a reduction in the overall 
dimensions of said cell. 
With the method of the present invention, silicon oxide etchings can be 
performed with a wet process, using known substances, such as, for 
example, hydrofluoric acid (HF:H.sub.2 O) or any other substance which can 
etch the oxide without damaging the surface of the device. These etchings 
allow removal of the gate oxide from a surface which is larger than the 
final dimensions of the tunnel portion. 
These results conveniently lead to a degree of manufacturing freedom which 
is absent in conventional cells. 
Practical tests have shown that the present invention achieves the intended 
aim and objects, including providing a method for defining thin oxide 
portions particularly for EEPROM cells with dimensions which are smaller 
than the resolution of the photolithographic method used. 
The method according to the present invention can have numerous 
modifications and variations and remain within the scope of the inventive 
concept. All of the details may be replaced with other technically 
equivalent elements as will be apparent to those skilled in the art. In 
practice, the materials employed, as well as the dimensions, may be any 
according to the particular requirements in specific applications. 
Having thus described one particular embodiment of the invention, various 
alterations, modifications, and improvements will readily occur to those 
skilled in the art. Such alterations, modifications, and improvements as 
are made obvious by this disclosure are intended to be part of this 
disclosure though not expressly stated herein, and are intended to be 
within the spirit and scope of the invention. Accordingly, the foregoing 
description is by way of example only and is not intended as limiting. The 
invention is limited only as defined in the following claims and the 
equivalents thereto.