Interposers for chip-scale packages and intermediates thereof

A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. The interposer may also include a rerouting element laminated over the remainder of the interposer and including one or more dielectric layers, as well as a conductive layer for rerouting the bond pad locations of a semiconductor device with which the interposer is to be assembled. The interposers may be fabricated on a “wafer scale.” Accordingly, a semiconductor device assembly may include a first, semiconductor device-carrying substrate and a second, interposer-comprising substrate. Regions of the second substrate that comprise the boundaries between adjacent interposers may be thinner than other regions of the second substrate, including the regions from which the interposers are formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to carrier substrates, or interposers, for use in chip-scale packages and to chip-scale packages including such carrier substrates. Particularly, the present invention relates to silicon carrier substrates. Methods of fabricating chip-scale packages are also within the scope of the present invention.

2. State of the Art

In conventional semiconductor device fabrication processes, a number of distinct semiconductor devices, such as memory chips or microprocessors, are fabricated on a semiconductor substrate, such as a silicon wafer. After the desired structures, circuitry, and other features of each of the semiconductor devices have been fabricated upon the semiconductor substrate, the substrate is typically singulated to separate the individual semiconductor devices from one another.

Various post-fabrication processes, such as testing the circuits of each of the semiconductor devices and burn-in processes, may be employed either prior to or following singulation of the semiconductor substrate. These post-fabrication processes may be employed to impart the semiconductor devices with their intended functionality and to determine whether or not each of the individual semiconductor devices meets quality control specifications.

The individual semiconductor devices may then be packaged. Along with the trend in the semiconductor industry to decrease semiconductor device sizes and increase the densities of semiconductor device features, package sizes are also ever-decreasing. One type of semiconductor device package, the so-called “chip-scale package” or “chip-sized package” (“CSP”), consumes about the same amount of real estate upon a carrier substrate as the bare semiconductor device itself. Such chip-scale packages typically include a carrier substrate, or interposer, having roughly the same surface area as the semiconductor device itself. As the interposer of such a chip-scale package is small, electrical connections between the semiconductor device and the carrier substrate are often made by flip-chip type bonds or tape-automated bonding (“TAB”). Due to the typical use of a carrier substrate that has a different coefficient of thermal expansion than that of the semiconductor substrate of the semiconductor device, these types of bonds may fail during operation of the semiconductor device.

In view of the potential for failure of the flip-chip or TAB electrical connections in chip-scale packages, chip-scale packages that include more flexible electrical connections, such as wire bonds, were developed. An exemplary chip-scale package that includes such flexible electrical connections is disclosed in U.S. Pat. No. 5,685,885 (hereinafter “the '885 Patent”), issued to Khandros et al. on Nov. 11, 1997. The chip-scale package of the '885 Patent may be assembled by orienting and disposing a sheet of interposer material over a wafer including a plurality of semiconductor devices thereon. The bond pads of the semiconductor devices may then be wire-bonded or otherwise flexibly bonded to corresponding contacts of the interposer. The wafer and interposer sheet may then be simultaneously singulated to separate individual semiconductor device packages from each other. The method and devices of the '885 Patent are, however, somewhat undesirable. In addition to including a semiconductor device and a carrier substrate therefor, the package of the '885 Patent includes another flexible, sheet-like dielectric interposer configured to be positioned between and aligned with both the semiconductor device and the carrier substrate. The double alignment of this additional interposer increases the likelihood that the resulting semiconductor device package will fail.

Following packaging, the packaged semiconductor devices may be retested or otherwise processed to ensure that no damage occurred during packaging. The testing of individual, packaged semiconductor devices is, however, somewhat undesirable since each package must be individually aligned with such testing or probing equipment.

Accordingly, there is a need for a semiconductor packaging process that facilitates testing, probing, and burn-in of semiconductor devices without requiring the alignment of individual semiconductor devices with probes or contacts of testing equipment and by which a plurality of reliable chip-scale packages may be substantially simultaneously assembled. An efficient chip-scale packaging process with a reduced incidence of semiconductor device failure is also needed. There is a further need for chip-scale packaged semiconductor devices that withstand repeated exposure to the operating conditions of the semiconductor devices thereof.

BRIEF SUMMARY OF THE INVENTION

A carrier substrate according to the present invention, which is also referred to herein as an interposer or simply as a carrier, is comprised of a semiconductor material and includes apertures defined substantially through the semiconductor material. The apertures of the carrier substrate are alignable with or may otherwise be positioned to communicate with corresponding bond pads of a semiconductor device to be secured to the carrier substrate. The apertures of the substrate are lined with electrically insulative material. Any of the exposed surfaces of the carrier substrate may also be covered with insulative material.

Conductive material may be disposed within and substantially fill the apertures so as to facilitate the transmission of signals to and from the bond pads of the semiconductor device through the carrier substrate. Alternatively, the insulator-lined apertures of the carrier substrate may be lined with conductive material by known metallization processes, such that conductive structures extending through the apertures each include a hollow portion. The hollow portion may be subsequently filled with a conductive bump material, such as solder. When the apertures are substantially filled with conductive material, an aperture and the conductive material therein collectively define an electrically conductive via, which is also referred to herein as a via for simplicity, through the carrier substrate.

The carrier substrate may also include conductive traces extending substantially laterally from selected ones of the electrically conductive vias. Preferably, each laterally extending conductive trace is carried by the carrier substrate proximate a surface opposite the surface to which a semiconductor device may be secured, which opposite surface is also referred to herein as a back side surface or simply as a back side of the carrier substrate. Such laterally extending conductive traces facilitate reconfiguration by the carrier substrate of the “footprint” formed by bond pads on the surface of the semiconductor device.

Contacts, which communicate with corresponding vias, may be disposed proximate to and are preferably exposed at the back side of the carrier substrate. If the carrier substrate includes any conductive traces that extend from the electrically conductive vias, a contact may be disposed proximate an end of a conductive trace, opposite the via from which the conductive trace extends and with which the conductive trace communicates. Alternatively, a contact may be positioned along the length of a conductive trace.

A conductive bump, such as a solder bump or a solder ball, may be placed adjacent each contact. Alternatively, if the apertures of the carrier substrate were lined with conductive material, a conductive bump may be placed substantially over selected apertures and permitted to substantially fill any remaining hollow portions of the apertures by capillary action or wicking.

The carrier substrate may also include insulative material on the back side thereof. The insulative material may be grown or deposited on the back side of the carrier substrate. If the back side of the carrier substrate has insulative material thereon, the contacts or conductive bumps are preferably exposed through the insulative material.

When the carrier substrate is employed in a chip-scale package, a semiconductor device is invertedly positioned over the carrier substrate such that bond pads on the active surface of the semiconductor device substantially align with corresponding vias of the carrier substrate. Thus, the vias through the carrier substrate communicate electrical signals to and from the corresponding bond pads of the semiconductor device. The carrier substrate and the semiconductor device may be secured to one another, at least in part, by bonding the conductive material of the vias to the material of the bond pads.

Alternatively, or in combination with bonds between the conductive material of the carrier substrate and bond pads of the semiconductor device, an intermediate layer may be disposed between the semiconductor device and the carrier substrate to secure the semiconductor device to the carrier substrate. Preferably, such an intermediate layer comprises an adhesive material securable to both the active surface of the semiconductor device and a surface of the carrier substrate.

In a preferred embodiment of the method of the present invention, apertures are defined through a first semiconductor wafer, such as a silicon wafer, which is also referred to herein as a substrate wafer or as a carrier substrate. The apertures through the substrate wafer may be defined by known processes, such as by laser drilling or by masking and etching. Preferably, the locations of the apertures of the carrier substrate or substrate wafer correspond substantially to bond pad locations of semiconductor devices fabricated on a second wafer including a plurality of semiconductor devices, which wafer is also referred to herein as a semiconductor device wafer.

The substrate wafer is aligned with the semiconductor device wafer so that corresponding apertures of the substrate wafer and bond pads of the semiconductor device wafer are substantially aligned with one another. A polymeric material or an adhesive material may be disposed on either an active surface of the semiconductor device wafer or on a surface of the substrate wafer to be positioned adjacent the semiconductor device wafer. The semiconductor device wafer and the substrate wafer are aligned and positioned adjacent one another.

A layer of insulative material may be grown or formed on any exposed surfaces of the substrate wafer, including the surfaces of the apertures formed through the substrate wafer, by known processes, such as by thermal oxidation techniques or chemical vapor deposition techniques. The insulative material may be disposed on the substrate wafer either prior to or after assembly thereof with the semiconductor device wafer.

Conductive material may be disposed in each of the apertures to define vias through the substrate wafer. As conductive material is disposed within each of the apertures, the conductive material and a material of the bond pad exposed to the aperture may diffuse and thereby at least partially secure the semiconductor device wafer and the substrate wafer to one another.

Any laterally extending conductive traces may be fabricated on the back side of the substrate wafer. Known techniques, such as metallization processes, masking processes, and etching processes, may be employed to fabricate these conductive traces.

Contact pads comprising under-bump metallurgy (“UBM”) or ball-limiting metallurgy (“BLM”), which are referred to herein as contacts for simplicity, may be fabricated on the back side of the substrate wafer. Preferably, each of these contacts corresponds to and communicates with a via of the carrier substrate or substrate wafer. The contacts may be fabricated by known processes, such as by known metallization, masking, and etching processes. A conductive bump, such as a solder bump or a solder ball, or other conductive structure (e.g., a pillar or column of electrically conductive material) may be disposed on each of the contacts by known processes.

An assembly that includes the semiconductor device wafer and the substrate wafer may be singulated by known processes. Upon singulation of individual semiconductor devices from the semiconductor device wafer and the substantially simultaneous singulation of the substrate wafer, individual chip-scale packages are separated from one another.

Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIG. 1, a carrier substrate10, which is also referred to herein as a semiconductor substrate or simply as a carrier, is illustrated. Carrier substrate10is a substantially planar structure, such as a wafer, that may be formed from a semiconductor material, such as silicon, gallium arsenide, or indium phosphide.

Carrier substrate10includes an array of apertures12defined therethrough. Each aperture12is lined with a layer13comprising an electrically insulative material. Preferably, apertures12are located in positions that correspond substantially to the positions of bond pads16(seeFIG. 3) of one or more semiconductor devices14to be assembled with carrier substrate10.

A chip-scale package30that includes carrier substrate10and an associated semiconductor device14is shown inFIG. 3. As depicted, carrier substrate10includes a quantity of conductive material18in each aperture12. The conductive material18within each aperture12defines an electrically conductive via20that extends substantially through carrier substrate10, through which electrical signals may be communicated to or from a corresponding bond pad16of semiconductor device14.

As shown inFIG. 12, carrier substrate10may also include conductive traces22that extend laterally across a surface (e.g., back side11) thereof from vias20to other locations on the surface of carrier substrate10. As illustrated, conductive traces22are carried upon or proximate a back side11of carrier substrate10. Alternatively, conductive traces22may extend internally through carrier substrate10.

Contacts24, such as the ball-limiting metallurgy or under-bump metallurgy structures known in the art, may communicate with vias20and be located on or proximate back side11of carrier substrate10. If carrier substrate10includes any laterally extending conductive traces22, contacts24may be placed on or in communication with such conductive traces22. Referring again toFIG. 3, contacts24that communicate with vias20that do not include laterally extending conductive traces22may be placed directly on such vias20. A conductive structure26, such as a bump, ball, column, or pillar of solder or another conductive material (e.g., a z-axis conductive elastomer), may be placed adjacent each contact24.

Carrier substrate10may also include insulative material on back side11. Insulative material may form a layer28that substantially covers back side11. The presence of a layer28comprising insulative material on back side11is especially preferred if carrier substrate10includes any conductive traces22that are carried upon or exposed at back side11. If carrier substrate10includes a layer28of insulative material on back side11, then one or more of vias20, contacts24, or conductive structures26, if present, are preferably exposed through layer28.

FIGS. 2 and 3illustrate a chip-scale package30that includes a semiconductor device14, shown in an inverted orientation, positioned adjacent to carrier substrate10. As illustrated, semiconductor device14is a flip-chip type semiconductor device that includes bond pads16disposed in an array over an active surface15thereof. Bond pads16of semiconductor device14and their corresponding vias20of carrier substrate10are substantially aligned, thereby facilitating communication between each bond pad16and its corresponding via20.

As shown inFIGS. 2 and 3, an intermediate layer32may be disposed between semiconductor device14and carrier substrate10. If chip-scale package30includes such an intermediate layer32, bond pads16and their corresponding vias20are preferably exposed or otherwise communicate with one another through intermediate layer32.

An alternative embodiment of chip-scale package30′ incorporating teachings of the present invention is shown inFIG. 4. As illustrated, chip-scale package30′ includes a leads-over-chip (LOC) type semiconductor device14′, which includes bond pads16arranged along one or more lines located at or near the center of active surface15′ of semiconductor device14′. Bond pads16of semiconductor device14′ and their corresponding vias20′ of a complementarily configured carrier substrate10′ are substantially aligned upon assembly of semiconductor device14′ with carrier substrate10′.

Turning now toFIGS. 5-17, an exemplary method for fabricating chip-scale packages30in accordance with teachings of the present invention is illustrated. The features of carrier substrate10and a chip-scale package30including carrier substrate10are also described in greater detail with reference toFIGS. 5-17.

FIG. 5illustrates a carrier substrate10including an array of apertures12. Carrier substrate10may be fabricated from a full or partial wafer formed from a semiconductor material, such as silicon, gallium arsenide, or indium phosphide, or from another suitable substrate, such as a silicon-on-glass (“SOG”), silicon-on-ceramic (“SOC”), silicon-on-sapphire (“SOS”), or other silicon-on-insulator (“SOI”) type substrate. Carrier substrate10may comprise a substantially chip-sized structure or may be part of a larger structure, such as a wafer36(seeFIG. 9).

Apertures12may be defined through carrier substrate10by known techniques, such as by known laser machining processes, which are also referred to herein as laser drilling techniques, or by known patterning processes (e.g., masking and etching). Each aperture12preferably extends substantially through carrier substrate10. The location of each aperture12preferably corresponds substantially to a location of a bond pad16(seeFIG. 6) of a semiconductor device14to be assembled with carrier substrate10.

Apertures12are lined with a layer13that includes electrically insulative material. Layer13may be formed by known processes, such as by use of known oxidation techniques to oxidize the semiconductor material at the surfaces of apertures12.

As shown inFIG. 6, a layer38comprising insulative material may be formed on back side11of carrier substrate10. Layer38may be formed by known processes, such as by growing a thermal oxide (e.g., a silicon oxide) layer on back side11and on any other exposed surfaces of carrier substrate10. A layer38comprising a thermally grown oxide may be formed during a furnacing process, such as during a thermal anneal of conductive material18(seeFIG. 10) to the portions of carrier substrate10exposed in apertures12. Alternatively, a layer38of electrically insulative material may be grown by other known processes or deposited onto back side11or any other exposed surfaces of carrier substrate10by known techniques, such as chemical vapor deposition (“CVD”) processes. If the insulative material of layer38is deposited, electrically insulative materials such as tetraethylorthosilicate (“TEOS”), silicon nitride, or glass (e.g., borophosphosilicate glass (“BPSG”), phosphosilicate glass (“PSG”), or borosilicate glass (“BSG”)) may be employed. As another alternative, layer38may be formed from spin-on glass (“SOG”), using known processes.

Layer38may be formed on carrier substrate10either prior to or after the assembly of carrier substrate10and semiconductor device14. The surfaces of carrier substrate10on which layer38is present depend, at least in part, on the fabrication method and on whether or not carrier substrate10has been assembled with semiconductor device14.

Carrier substrate10may be assembled with semiconductor device14either before or after apertures12are formed through carrier substrate10.

Referring toFIG. 7, carrier substrate10may be positioned adjacent to semiconductor device14in such a manner that each aperture12of carrier substrate10and its corresponding bond pad16of semiconductor device14are substantially aligned. Semiconductor device14and carrier substrate10preferably have substantially the same, or at least similar, coefficients of thermal expansion so as to maintain the integrity of a chip-scale package30(FIGS. 2 and 3) that includes semiconductor device14and carrier substrate10during operation of semiconductor device14.

The thicknesses of carrier substrate10and semiconductor device14may be similar or substantially the same. The thickness of semiconductor device14may, however, be greater than that of carrier substrate10since semiconductor device14includes integrated circuit devices that have been fabricated or built up on active surface15thereof.

As shown inFIG. 8, an intermediate layer32may be located between semiconductor device14and carrier substrate10. Intermediate layer32may include a polymeric material or an adhesive material, such as a polyimide, that adheres semiconductor device14and carrier substrate10to one another. Intermediate layer32may also insulate structures exposed at active surface15of semiconductor device14from carrier substrate10or structures thereof. Bond pads16and vias20are preferably exposed through intermediate layer32so as to facilitate the communication of signals to and from bond pads16through intermediate layer32and through vias20(seeFIG. 3). Intermediate layer32may be placed on active surface15of semiconductor device14or on a surface of carrier substrate10by known processes, such as by spin-on techniques or other known processes that may be used to fabricate or form a layer with a substantially planar surface and having a substantially uniform thickness over the surface of a semiconductor device.

With reference toFIG. 9, the assembly of carrier substrate10and semiconductor device14may occur on a wafer scale. Stated another way, a wafer34or other large-scale substrate (e.g., a silicon-on-insulator (SOI) type structure, such as silicon-on-ceramic (SOC), silicon-on-glass (SOG), or silicon-on-sapphire (SOS), or a partial wafer of semiconductive material, such as silicon, gallium arsenide, indium phosphide, etc.) including a plurality of semiconductor devices14(seeFIGS. 7 and 8), which is referred to herein as a semiconductor device wafer, may be assembled with another wafer36or other large-scale substrate (e.g., a silicon-on-insulator (SOI) type structure, such as silicon-on-ceramic (SOC), silicon-on-glass (SOG), or silicon-on-sapphire (SOS), or a partial wafer of semiconductive material, such as silicon, gallium arsenide, indium phosphide, etc.), which is referred to herein as a substrate wafer, from which the carrier substrate10of each chip-scale package30is defined.

If the removal of portions of layer38from carrier substrate10is desired, known processes, such as mask and etch techniques, may be employed. For example, it may be desirable to remove the insulative material of layer38from bond pads16or vias20. Thus, a mask including openings or apertures therethrough which are aligned over areas of layer38that are to be removed would be fabricated and used in combination with an etchant that etches the material of insulative layer38with selectivity over the conductive material of bond pads16or vias20or with selectivity over the semiconductor material of carrier substrate10.

Referring toFIG. 10, an assembly including semiconductor device14and carrier substrate10is shown. Apertures12, which are lined with a layer13of insulative material, are substantially filled with conductive material18. Conductive material18may be disposed in apertures12by known processes, such as by known physical vapor deposition (“PVD”) processes (e.g., sputtering) or known chemical vapor deposition (“CVD”) processes. Any excess conductive material18may be removed from back side11by known processes, such as by known etching techniques or known planarization processes (e.g., mechanical polishing or chemical-mechanical polishing (“CMP”)).

Preferably, as conductive material18is disposed in apertures12, conductive material18contacts bond pads16of semiconductor device14. As conductive material18may adhere to bond pads16, or conductive material18and the material or materials of bond pads16may diffuse, thereby forming a diffusion region or contact between conductive material18and the corresponding bond pad16, the introduction of conductive material18within apertures12may at least partially secure carrier substrate10and semiconductor device14to one another.

Referring toFIG. 11, it may be desirable to form a via20from two layers18aand18bof conductive material18. A first layer18aincludes a barrier-type material that reduces contact resistance. The material of first layer18amay reduce or prevent diffusion or “spiking” between the semiconductor material of carrier substrate10and the primary conductive material of the second layer18b, which diffusion could cause electrical shorts between adjacent vias20or increase the electrical resistance of a via20. Barrier materials that are known in the art, such as metal silicides, and that are known to be compatible with both the electrically insulative material of layers13that line apertures12of carrier substrate10and the conductive material of second layer18bmay be employed. For example, if the conductive material of second layer18bcomprises titanium, the barrier material of first layer18amay comprise titanium silicide. Such materials may be deposited by known processes, such as chemical vapor deposition or physical vapor deposition. These materials may either be blanket deposited or selectively deposited, as known in the art.

Of course, the insulative material of layer13electrically isolates conductive material18of one via20from other vias20of carrier substrate10. Conductive material18may be annealed to insulative layer13by known processes, such as by thermal anneal techniques.

Conductive material18(e.g., of either of layers18aor18b) that remains on back side11or any other regions of carrier substrate10where the presence of conductive material is undesirable may be removed by known processes. For example, known planarization techniques, such as chemical-mechanical planarization or chemical-mechanical polishing, may be employed to substantially completely remove the conductive material18from back side11. Alternatively, if the selective removal of any portion of conductive material18from back side11is desired, known patterning processes, such as mask and etch techniques, may be employed to pattern conductive material18.

With reference toFIG. 12, conductive traces22may be fabricated to reconfigure the footprint of bond pads16on active surface15of semiconductor device14to a different arrangement of contacts24on back side11. Conductive traces22, therefore, extend substantially laterally from their corresponding vias20, and may extend substantially internally through carrier substrate10or may be carried upon or exposed at back side11of carrier substrate10. Conductive traces22may be fabricated by known processes, such as by depositing one or more layers of conductive material onto a surface of carrier substrate10and patterning the layer or layers of conductive material. Alternatively, conductive traces22may be defined from layer18or layers18a,18bduring patterning of one or more of these layers.

Referring toFIG. 13and with continued reference toFIG. 12, contacts24, which communicate with bond pads16by means of vias20, may be carried upon back side11of carrier substrate10. Contacts24are preferably fabricated by known processes (e.g., fabricating the layers by PVD and patterning the layers by mask and etch processes), such as those employed to fabricate under-bump metallurgy or ball-limiting metallurgy structures. Accordingly, each contact24may include an adhesion layer adjacent the conductive material18of its corresponding via20, a solder wetting layer adjacent the adhesion layer, and an exposed, substantially nonoxidizable protective layer (e.g., gold or other noble metal) adjacent the solder wetting layer.

Alternatively, if conductive material18(or the material of second layer18b) is a solder-wettable material, contacts24may be patterned from the conductive material18disposed over back side11of carrier substrate10. Known processes, such as masking and etching, may be employed to define contacts24from conductive material18.

Turning now toFIG. 14, conductive structures26may be placed on selected contacts24. An exemplary material that may be employed to form conductive structures26of a chip-scale package30incorporating teachings of the present invention is solder. The material of a conductive structure26preferably bonds or adheres to an adjacent contact24and, thereby, facilitates electrical communication between each conductive structure26and its corresponding contact24. Alternatively, conductive structures26may be positioned directly against conductive material18of vias20.

With reference toFIG. 15, as an alternative to substantially filling apertures12with conductive material, as is shown inFIGS. 10 and 11, conductive material may be disposed in apertures12in one or more relatively thin layers18′, such that hollow or open regions19′ remain in at least some of apertures12. Preferably, the conductive material of layer18′ is wettable by a conductive bump material, such as molten solder, that is used to form conductive structure26of chip-scale package30. A layer of barrier-type material may be disposed between layer18′ and the adjacent surface of carrier substrate10to adhere the conductive material to carrier substrate10and to prevent diffusion of the semiconductor material of carrier substrate10with layer18′.

If layer18′ includes a barrier material, the barrier material may be disposed on the insulative layer13—lined surfaces of apertures12by known processes, such as by chemical vapor deposition or physical vapor deposition. The wettable conductive material of layer18′ may also be disposed over the insulative layer13—lined surface of each aperture12by known processes, such as chemical vapor deposition or physical vapor deposition. Excess barrier material or conductive material may be removed from back side11of carrier substrate10or other undesired regions thereof by known processes, such as by known patterning or planarization techniques.

As shown inFIGS. 16 and 17, a conductive structure26′ material, such as solder, may be disposed adjacent conductive layer18′. If layer18′ includes a material that is wettable by the conductive material employed, the conductive bump may be drawn into hollow region19′ by capillary action, or “wicking.”

With reference toFIG. 18, the chip-scale package30′ depicted inFIG. 4, which includes a carrier substrate10′ with contacts24′ that are arranged substantially linearly along a central location thereof, or any other type of semiconductor device, may be assembled with another substrate80that includes contacts84that are arranged to have a different “footprint” than that of contacts24′. As depicted, contacts84are arranged in an array over a surface82of substrate80.

As shown, substrate80includes a first layer86that is configured to be positioned adjacent an exposed surface29′ of chip-scale package30′, a conductive, second layer88including laterally extending electrically conductive traces89, and a third layer90located adjacent second layer88, opposite first layer86.

First layer86is preferably a thin film which may be formed from an electrically insulative material, such as a polyimide, glass, or ceramic, or from a semiconductive material with at least some surfaces thereof being coated with insulative material. First layer86includes apertures87formed therethrough. When substrate80is disposed on surface29′ of chip-scale package30′, each aperture87aligns with and receives a portion of a corresponding conductive structure26′ that protrudes from chip-scale package30′.

Second layer88includes distinct, electrically isolated conductive traces89. Each conductive trace89of second layer88corresponds to a conductive structure26′ of chip-scale package30′. Each conductive trace89extends laterally from aperture87formed through first layer86at least to a desired lateral position for a contact84. Thus, each conductive trace89reroutes the position of a bond pad16of a semiconductor device14′ of chip-scale package30′, as well as a position of a contact24′ of chip-scale package30′.

Third layer90provides electrical insulation over conductive traces89and includes apertures91formed therethrough, through which the portions of each conductive trace89that form contacts84are exposed. By way of example only, third layer90may be formed from a polyimide or other electrically insulative resin, from another electrically insulative material, such as glass or ceramic, or from a semiconductive material with at least some surfaces thereof being lined with an electrically insulative material.

Preferably, the materials from which substrate80is formed have substantially the same, or at least similar, coefficients of thermal expansion as those of the materials from which semiconductor device14′ and carrier substrate10′ of chip-scale package30′ are formed.

Substrate80may be fabricated on chip-scale package30′ or separately therefrom and subsequently assembled with chip-scale package30′. As illustrated inFIG. 19, a quantity of adhesive material or underfill material92may be introduced between surface29′ of chip-scale package30′ and first layer86of substrate80, securing the separately fabricated substrate80to chip-scale package30′.

In either event, known processes may be used to fabricate substrate80. For example, first layer86may be formed by known processes for forming a thin film from an electrically insulative resin, such as a polyimide. If a photoimageable resin is used, apertures87may be formed by selectively curing all of the areas of a layer of the photoimageable resin but those in which apertures87are to be located. If first layer86is formed and cured or otherwise solidified prior to the formation of apertures87, apertures87may be formed in first layer86by known processes, such as by use of known laser drilling techniques or mask and etch processes.

The conductive traces89of second layer88may also be formed by known processes. For example, conductive traces89may be preformed, then positioned at appropriate locations on first layer86. Alternatively, conductive traces89may be formed by depositing a layer of conductive material onto a surface of first layer86, as known in the art (e.g., by PVD or CVD), then patterning the layer of conductive material, as also known in the art (e.g., by mask and etch processes).

Third layer90may be formed over conductive traces89by known processes. If, for example, third layer90is formed from polyimide or another resin, the material may be applied to conductive traces89and the areas of first layer86that are exposed between conductive traces89by known techniques, such as spin coating or spray coating. Apertures91may be formed through third layer90by selective exposure, if third layer90is formed from a photoimageable material, while the material of third layer90is being cured, or following the hardening of third layer90by other known techniques, such as laser drilling or the use of a mask and a suitable etchant.

As another alternative, a tape-automated bonding-type tape may be used to form conductive traces89and one of first layer86and third layer90. Apertures87,91may be formed in the film portion of the TAB tape by known processes, such as by use of laser drilling techniques or mask and etch processes. The other layers86,90and the apertures87,91that extend therethrough may then be formed by the processes disclosed herein.

As chip-scale packages30incorporating teachings of the present invention may be fabricated on a wafer-scale, as depicted inFIG. 9, testing, probing, or burn-in of each of semiconductor device14of semiconductor device wafer34can be performed after packaging, but prior to severing or singulating semiconductor devices14from semiconductor device wafer34. Thus, the packaging method of the present invention eliminates the need to individually align separate semiconductor device packages with the probes or contacts of test equipment.

When semiconductor devices14of chip-scale packages30are tested, probed, or burned-in, semiconductor devices14and their corresponding carrier substrates10may be subjected to increased temperatures. Consequently, thermal mismatches between (i.e., different coefficients of thermal expansion (“CTEs”) of) semiconductor devices14and their corresponding carrier substrates10may cause mechanical stresses to be induced on one or both of semiconductor device wafer34and substrate wafer36. These potential mechanical stresses may be reduced following the assembly of semiconductor device wafer34and substrate wafer36, before or after the introduction of conductive material18into apertures12(FIGS. 10,11, and15) or before or after the fabrication of conductive traces22or contacts24by substantially severing one of semiconductor device wafer34and substrate wafer36at locations between adjacent semiconductor devices14and chip-scale packages30.

FIGS. 20-22depict an exemplary, energy (e.g., laser) ablation method for reducing the thickness of one or both of semiconductor device wafer34and substrate wafer36prior to testing, probing, or burning in of the semiconductor devices14of semiconductor device wafer34and before chip-scale packages30are physically separated from one another. As depicted, the thickness of at least substrate wafer36may be reduced at locations that overlie streets31of semiconductor device wafer34, which are located between adjacent semiconductor devices14of semiconductor device wafer34.

As shown inFIG. 20, a layer70of protective material may be disposed onto an exposed surface72of substrate wafer36, located opposite semiconductor device wafer34. The protective material of layer70is preferably substantially opaque to the wavelengths of electromagnetic radiation, or laser light, that will be used to reduce the thickness of substrate wafer36at locations that overlie streets31of semiconductor device wafer34. As an example, a layer70of opaque polyimide may be applied to surface72by spin coating or spray coating, then permitted to solidify by evaporation of solvent therefrom. Alternatively, an opaque, photoimageable or thermosetting-type material may be applied to surface72and cured by use of appropriate techniques. As another example, layer70may comprise a metal oxide of low reflectivity and that is substantially opaque to the wavelength or wavelengths of radiation emitted from a laser74(FIGS. 21 and 22) or other, suitable energy beam source that will be used to remove material of substrate wafer36. A layer70including such a metal oxide may be formed by known processes, such as by chemical vapor deposition. A layer70comprising a metal oxide may also be formed by first depositing the metal (by PVD or CVD), then oxidizing the metal (e.g., by exposing the metal to an increased temperature in an oxygen-rich atmosphere).

As shown inFIG. 21, the protective material of layer70may be removed by the same laser74or other suitable energy beam that will subsequently be used to remove material of substrate wafer36from locations that overlie streets31. Alternatively, known mask and etch processes may be used to remove protective material from the regions of layer70that overlie streets.

Next, as shown inFIG. 22, the portions of substrate wafer36that are exposed through layer70are irradiated with electromagnetic radiation from laser74, which may comprise a carbon dioxide laser, an Nd:YAG laser, an Nd:YLF laser, any other type of laser suitable for use in cutting or removing silicon, or any other suitable source of energy or electromagnetic radiation that may be used to cut or remove silicon. Upon irradiating the exposed regions of substrate wafer36, material is removed from locations of substrate wafer36that overlie streets31, thereby forming scribe lines in or “cutting” substrate wafer36at these locations. Layer70may prevent the circuitry and other components of semiconductor devices14from being exposed to scattered radiation of the wavelength or wavelengths that are emitted by laser74, thereby preventing laser-induced damage to semiconductor devices14during reduction of the thickness of substrate wafer36and the consequent formation of trenches76at the desired locations.

Once the thicknesses of the portions of substrate wafer36that overlie streets31of semiconductor device wafer34have been reduced, as desired, layer70may be substantially removed from surface72of substrate wafer36. A suitable removal process depends upon the type of protective material from which layer70is formed. For example, if an opaque polyimide, photoimageable material or other resin or epoxy is used, a solution including a suitable solvent for these materials may be used to substantially remove layer70from surface72. If, in the alternative, layer70is formed from a metal oxide that is opaque to the wavelength or wavelengths of radiation that are emitted by laser74, a suitable wet or dry etchant may be used to substantially remove layer70from surface72.

As another alternative, known semiconductor device structure patterning processes (e.g., masking and etching techniques) may be used to reduce a thickness of substrate wafer36at positions that are located over streets31of semiconductor device wafer34.

FIGS. 23 and 24depict an exemplary manner in which semiconductor devices14of chip-scale packages30may be tested, probed, or burned-in prior to singulation thereof from semiconductor device wafer34or another large-scale substrate.

As shown inFIG. 23, each semiconductor device14of a semiconductor device wafer34or other large-scale substrate may be probed, as known in the art, to evaluate the electrical properties of that semiconductor device14and to thereby determine whether or not that semiconductor device14is functional. In addition, the location of each functional semiconductor device14on semiconductor device wafer34or another large-scale substrate may be mapped using known techniques.

If probing is effected before conductive structures26are placed on contacts24(FIG. 14) or adjacent to layers18′ of conductive material (FIGS. 16 and 17), once the functional semiconductor devices14fabricated on semiconductor device wafer34have been identified and mapped, conductive structures26may be placed on contacts24or adjacent to layers18′ of each carrier substrate10that is positioned adjacent to a functional semiconductor device14, as described previously herein with reference toFIGS. 14,16, and17. Preferably, conductive structures26,26′ are not applied to contacts24or layers18′ of nonfunctional semiconductor device14. Alternatively, conductive structures26,26′ may be applied to each contact24or layer18′ of both the functional and nonfunctional semiconductor device14on semiconductor device wafer34or another large-scale substrate.

Turning now toFIG. 24, in testing, probing, or burning-in semiconductor devices14, the assembly of substrate wafer36and semiconductor device wafer34or another large-scale substrate upon which semiconductor devices14are carried is oriented within a test chuck50, which, in turn, is associated with a tester52(FIG. 25). As shown, conductive structures26protruding from contacts24of functional semiconductor devices14are disposed adjacent to and in electrical contact with corresponding test terminals51of test chuck50. Test terminals51of test chuck50facilitate communication between each functional semiconductor device14and tester52so that semiconductor devices14may be tested, probed, or burned-in in the desired manner.

The exemplary test chuck50illustrated inFIG. 24is a substantially planar member that includes an aperture54beneath each test terminal51so as to facilitate the insertion of probes55(FIG. 25) that communicate with tester52(FIG. 25) therethrough and into electrical contact with test terminals51while semiconductor devices14are being tested, probed, or burned-in. Preferably, apertures54and areas on a surface56of test chuck50that laterally surround test terminals51are lined with an electrically insulative material so as to prevent shorting of various electrical circuits that are formed during testing, probing, or burning-in of semiconductor devices14.

Test chuck50preferably includes a bulk silicon or another substrate that has a coefficient of thermal expansion that is similar to the CTEs of substrate wafer36and of semiconductor device wafer34or another large-scale substrate upon which semiconductor devices14are fabricated. When the coefficients of thermal expansion of test chuck50, substrate wafer36, and semiconductor device wafer34or another large-scale substrate that carries semiconductor devices14are substantially the same or similar, the likelihood is reduced that conductive structures26, carrier substrates10, and semiconductor devices14will be damaged during testing, probing, or burning-in of semiconductor devices14.

Of course, known, suitable semiconductor device fabrication techniques, including, without limitation, material deposition, oxide formation, and patterning processes, may be used to fabricate test chuck50.

Test chuck50may be used, as known in the art, in known, test, probe, or burn-in equipment to facilitate the testing, probing, or burning-in of a collection of chip-scale packages30incorporating teachings of the present invention.

As illustrated inFIG. 25a test chuck50may be positioned in an appropriate location within a receptacle62of a testing apparatus60, such that test terminals51are located in positions that facilitate the communication of corresponding probes55therewith. An assembly including semiconductor device wafer34and substrate wafer36is invertedly oriented over test chuck50, with conductive structures26being aligned with corresponding test terminals51of test chuck50. Preferably, test terminals51partially receive their corresponding conductive structures26so as to facilitate the formation of an adequate electrical connection between each test terminal51and its corresponding conductive structure26. The assembly of semiconductor device wafer34and substrate wafer36may be biased toward test chuck50so as to further ensure the formation of adequate electrical connections between conductive structures26and their corresponding test terminals51. For example, a lid66that is configured to be coupled with testing apparatus60may be positioned over the assembly of semiconductor device wafer34and substrate wafer36and secured to testing apparatus60in such a manner that lid66biases the assembly of semiconductor device wafer34and substrate wafer36to test chuck50.

Each chip-scale package30in the assembly of semiconductor device wafer34and substrate wafer36may then be tested, probed, or burned-in, as known in the art, by use of a suitable tester52or other equipment associated with testing apparatus60.

Turning now toFIG. 26, individual chip-scale packages30may be singulated from the assembly of semiconductor device wafer34(not shown) and substrate wafer36by known singulation processes, such as by the use of a wafer saw40. If trenches76have been formed in substrate wafer36, as shown inFIGS. 20-22, substrate wafer36and semiconductor device wafer34may be singulated along trenches76. Trenches76may also be used to ensure that the blade or blades of wafer saw40are properly aligned over the streets31located between the semiconductor devices14that have been fabricated on semiconductor device wafer34.

Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions, and modifications to the invention, as disclosed herein, which fall within the meaning of the claims are to be embraced thereby.