Method for manufacturing semiconductor device

A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2010-0106302 filed on Oct. 28, 2010 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119; the entire contents of this priority application are herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a reduced leakage current and improved channel conductivity, and a method for manufacturing the semiconductor device.

2. Description of the Related Art

Research is under way to increase the operation speed and packing density of semiconductor devices. A semiconductor increases discrete devices such as a metal oxide semiconductor (MOS) transistor. As an integration degree of the semiconductor device is increased, scaling down a gate of the MOS transistor is becoming a major challenge. In addition, a channel region located under the gate becomes shorter.

Accordingly, various methods are investigated to enhance channel conductivity by increasing the mobility of carriers in a channel region with respect to a predetermined channel length. One mechanism for increasing the mobility of carriers is to induce compressive stress to a channel region to thereby increase hole mobility in the channel, while inducing tensile stress to the channel region to improve electron mobility in the channel region.

The stress memorization technique (SMT) is one technique that has recently been used to induce stress to a channel, which may, however, result in an increase of leakage current.

SUMMARY OF THE INVENTION

Embodiments of the present invention include a semiconductor device having a reduced leakage current and improved channel conductivity, as well as a method for manufacturing a semiconductor device having a reduced leakage current and improved channel conductivity.

According to an aspect of the present invention, a semiconductor device including a gate pattern is formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate is formed at one side of the gate pattern.

According to another aspect of the present invention, a method for manufacturing a semiconductor device includes forming a gate pattern on a substrate, forming a mask on the substrate at one side of the gate pattern, forming an amorphous region by implanting impurities into the substrate, removing the mask, and forming a recrystallized region by forming a stress liner on the substrate to cover the gate pattern and crystallizing the amorphous region.

As described above, the mobility of carriers can be enhanced by increasing stress applied to a channel. In addition, the mobility of carriers can be more effectively enhanced by inducing more stress from a source region than from a drain region. Further, characteristics of the semiconductor device can be more enhanced by reducing a leakage current generated in the drain region.

DETAILED DESCRIPTION

Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views of the invention. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the embodiments of the invention are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions exemplified in figures have schematic properties; and shapes of regions shown in figures are exemplary and are not intended to limit aspects of the invention.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference toFIG. 1, which provides a cross-sectional view of the semiconductor device.

Referring toFIG. 1, the semiconductor device may include a gate pattern120, a recrystallized region130, a source region142and a drain region143. The semiconductor device may further include a gate spacer124and a lightly doped drain (LDD) region141.

The gate pattern120is formed on a substrate110, and a channel region is formed under the gate pattern120to allow a current to flow therethrough.

The substrate110may be a rigid substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a gallium arsenic substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, and a display glass substrate. Alternatively, the substrate110may be a flexible plastic substrate made of, for example, polyimide, polyester, polycarbonate (PC), polyethersulfone (PES), polymethyl methacrylate (PMMA), or polyethylene naphthalate (PEN), polyethylene terephthalate (PET).

The gate pattern120may include a gate insulating layer121and a gate electrode122. Although not shown inFIG. 1, a hard mask layer that protects the gate electrode122may be formed on the gate electrode122. The hard mask layer may be formed of silicon nitride (Si3N4) or silicon oxynitride (SiON), but is not limited thereto.

The gate insulating layer121may include a silicon oxide (e.g., SiO2) layer, a silicon nitride (e.g., Si3N4) layer, SiON, GexOyNz, GexSiyOz, a high-k dielectric material or a combination thereof, or a stacked layer having these materials sequentially stacked. Here, the high-k dielectric material may include, but not limited to, HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, a combination thereof.

The gate electrode122may be formed of, but not limited to, a single layer of poly-Si, poly-SiGe, doped poly-Si, a metal such as Ta, TaN, TaSiN, TiN, Mo, Ru, Ni, or NiSi, or a metal silicide, or a stacked layer having these materials sequentially stacked. In a case where the gate electrode122is formed of a metal or a metal silicide, low resistance can be realized with a fine line width, and doping impurities are not necessary.

The gate spacer124is formed on sidewalls of the gate pattern120and protects the gate electrode122. The gate spacer124may have a single-layered structure formed of silicon nitride or a silicon oxide or a multilayered structure including a combination of a silicon nitride layer and a silicon oxide layer.FIG. 1illustrates that the gate spacer124includes a first spacer124aand a second spacer124b. In detail, the first spacer124amay be formed of a silicon oxide layer, and the second spacer124bmay be formed of a silicon nitride layer.

The recrystallized region130is formed at one side of the substrate110in view of the gate pattern120. That is to say, the recrystallized region130is asymmetrically formed only at one side of the substrate110in view of the gate pattern120. The recrystallized region130applies tensile stress or compressive stress to the channel region to thereby enhance carrier mobility in the channel region.

The recrystallized region130has a stacking fault defect. The stacking fault defect may occur when locations of atomic layers are changed or part of a continuous layer is added or removed due to stress applied to an amorphous region in the course of recrystallizing the amorphous region. Due to the stacking fault defect, the stress applied by recrystallizing is retained at a recrystallized lattice even after the stress is eliminated, and compressive stress or tensile stress is applied to the channel region. As shown inFIG. 1, the stacking fault defect may be formed such that it becomes closer to the gate pattern120(that is, in a direction indicated by an arrow ‘C’) downwardly in the substrate110.

The closer to the channel region the stacking fault defect is formed, the more effectively the stress is applied to the channel region.

The LDD region141is formed by implanting low concentration impurity ions into the substrate on opposite sides of the gate pattern120. The LDD region141relaxes electric fields in the source region142and the drain region143and reduces leakage current.

The impurities may be implanted by an ion implantation process. For example, n-type impurities (e.g., P, As, or the like) may be implanted for a negative metal oxide semiconductor (NMOS) device; and p-type impurities (e.g., B, BF2, Ga, or the like), may be implanted for a positive metal oxide semiconductor (PMOS) device.

A portion of the LDD region141on the source region142is formed in the recrystallized region130, which is formed in the substrate110on one side of the gate pattern120

The source region142and the drain region143are spaced apart from each other in view of the gate pattern120and the gate spacer124, and are formed by implanting heavily doped impurities using the gate pattern120and the gate spacer124as masks. For an NMOS region, an n-type dopant such as phosphorus (P) or arsenic (As) may be implanted; and for a PMOS region, a p-type dopant such as boron (B) or gallium (Ga) may be implanted.

The source region142or the drain region143may be formed in the recrystallized region130. The source region142formed in the recrystallized region130may have a stacking fault defect. The drain region143is spaced apart from and faces the source region142in view of the gate pattern120while having no stacking fault defect.

In a case where the source region142or the drain region143is formed in the recrystallized region130having compressive stress or tensile stress retained in a lattice structure, the mobility of carriers can be enhanced by applying stress to the channel region. However, an end-of-range (EOR) defect may be generated around an amorphous region in the course of amorphizing the substrate110before crystallization, and gate-induced drain leakage (GIDL) may occur to the drain region143. The EOR defect may increase the GIDL. In embodiments of the semiconductor device, the source region142with a stacking fault defect can enhance the carrier mobility by increasing the stress applied to the channel region, while the drain region143without a stacking fault defect can reduce leakage current.

Each of the source region142and the drain region143may have an elevated structure raised from the substrate110. The elevated source and drain structures may have shallow junction structures (with a projected range, Rp) formed on a top surface of the substrate10by injecting impurities. Accordingly, undesired degradation of the device characteristics due to a short channel effect can be overcome.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference toFIGS. 2 and 3Ato3H.FIG. 2is a flow chart showing the process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, andFIGS. 3A to 3Hare cross-sectional views of the semiconductor device being manufactured with the process steps ofFIG. 2.

Referring toFIG. 2, a method for manufacturing the semiconductor device may include forming a gate pattern (step S10), forming a mask (step S20), asymmetrically amorphizing (step S30), removing the mask (step S40) and recrystallizing (step S50). The method for manufacturing the semiconductor device may further include forming an LDD region (step S60) and forming source and drain regions (step S70).

Referring toFIG. 3A, the device is shown after step S10, when a gate pattern120, including a gate insulating layer121and a gate electrode122, is formed on a substrate110.

In detail, an insulating layer for forming a gate insulating layer121and a layer for forming a gate electrode122are sequentially formed on the substrate110and patterned, thereby forming the gate pattern120having a stacked structure with the gate insulating layer121and the gate electrode122sequentially stacked.

Although a hard mask layer (not shown) may be formed on the gate electrode122, it may be skipped as demanded by one skilled in the art. In order to protect the gate pattern120, an insulating layer formed of a silicon oxide layer or a silicon nitride layer that is part of a gate spacer124may further be formed on sidewalls of the gate pattern120.

Referring toFIG. 3B, the device is shown after step S20, when a mask131is formed on the substrate110at one side of the gate pattern120. The mask131prevents impurities from being implanted into the substrate110below the mask131and being amorphized.

In detail, a hard mask layer or a photoresist layer is deposited to cover either side of the substrate110at opposite sides of the gate pattern120. The mask131is formed of a hard mask layer or a photoresist. The hard mask layer may be formed of an insulating layer, and the photoresist layer may be formed of any photoresist that is generally used in the art.

Referring toFIG. 3C, the device is shown in step S30, as an amorphous region130ais formed by implanting impurities into the substrate110.

In detail, if impurity ions are implanted on the substrate110using an ion implantation process, the impurity ions permeate into interstices of a crystal lattice, so that a crystalline region is changed into the amorphous region130a. The ion implantation process may be performed by a generally known method, and non-limiting examples of the impurities may include Si, Ge, Sb, In, As, P, BF2, Xe and Ar.

One side of the substrate110in view of the gate pattern120is covered by the mask131. Thus, amorphization asymmetrically occurs only at a region of the substrate that is not covered by the mask131.

During amorphization, the impurities may be implanted in a direction perpendicular to the substrate110, as indicated by A (as shown, the impurities A are implanted in a direction perpendicular to the substantially planar exposed surface of the amorphous region130a), or may be implanted at a predetermined angle (α) of inclination, as indicated by B, with respect to the direction perpendicular to the substrate. In the latter case, an amorphous region130a′ is formed much closer to a channel region, thereby further enhancing stress applied to the channel region.

The predetermined angle (α) may be in a range of 10 to 40 degrees, more particularly in a range of 20 to 30 degrees. When the predetermined angle (α) is in a range of 10 to 40 degrees, the amorphous region130amay be formed close to the channel region, and impurity ions may be implanted without interference considering a distance between gate patterns120.

Referring toFIG. 3D, the device is shown after step S40, when the mask131, which was formed on the substrate110only to one side of the gate pattern120, is removed.

In detail, amorphization is performed only on the substrate110at one side of the gate pattern120, where the mask131is not formed, by an ion implantation process, as discussed above; and the mask131is then removed. The mask131may be removed by ashing and cleaning.

Referring toFIGS. 3E and 3F, the device is shown during step S50, when a stress liner132is formed on the entire surface of the substrate110to cover the gate pattern120, and the amorphous region130ais recrystallized to form a recrystallized region130.

In detail, the stress liner132is deposited on the entire surface of the substrate110by chemical vapor deposition (CVD) to cover the gate pattern120and annealed, thereby recrystallizing the amorphous region130ain the substrate110into a solid phase epitaxy.

In order to apply stress to the amorphous region130ain the substrate110, the stress liner132may be made of a material having a thermal expansion coefficient that differs from that of the material that forms the substrate110. In a case where the channel region below the gate pattern120has p-type impurity ions, the stress liner132may be made of a material capable of applying tensile stress to the channel region. In a case where the channel region below the gate pattern120has n-type impurity ions, the stress liner132may be made of a material capable of applying compressive stress to the channel region. In detail, for an NMOS, for example, the stress liner132may be formed of a silicon nitride (SixNy) layer using a low-pressure chemical vapor deposition (LPCVD) process. For a PMOS, the stress liner132may be formed of silicon carbide (SiC) using a plasma-enhanced chemical vapor deposition (PECVD) process.

The annealing may include, but is not limited to, spike annealing, rapid thermal annealing, and the like, which may be quickly performed.

As described above, the annealing performed in the presence of the stress liner132brings about crystallization to the solid phase epitaxy in the amorphous region130a. A stacking fault defect may occur when part of a continuous layer is added or removed while crystals of the amorphous region130aregrow. Accordingly, the stress applied to the amorphous region130by the stress liner132is retained in the recrystallized region130even after the stress liner132is eliminated, thereby applying stress to the channel region and increasing the channel conductivity.

The stacking fault defect is formed such that it becomes closer to the gate pattern (that is, in a direction indicated by an arrow ‘C’) downwardly in the substrate110.

In addition, during the amorphization, if impurity ions are implanted at a predetermined angle of inclination such that some of the impurity ions extend under the gate pattern120(in the orientation shown) as impurity ions penetrate the substrate110; consequently, the amorphous region is formed much closer to the channel region and the stacking fault defect is formed much closer to the channel region, thereby further enhancing stress applied to the channel region.

After the recrystallized region130having a stacking fault defect is formed, the stress liner132is completely removed by, for example, etching. In addition, before forming the stress liner132, a silicon oxide layer (not shown) covering the entire surface of the substrate110may be formed. The silicon oxide layer may serve as an etch stop layer when etching the stress liner132, and is also completely removed after recrystallization.

Referring toFIG. 3G, which shows the device after step S60, when a lightly doped drain (LDD) region141is formed by implanting impurities into the substrate110at opposing sides of the gate pattern120.

In detail, the LDD region141is formed by performing an ion implantation process on the substrate110using the gate pattern120as a mask. In a case of an NMOS, an n-type dopant, such as phosphorus (P) or arsenic (As), may be used as the impurity, and in a case of a PMOS, a p-type dopant, such as boron (B) or gallium (Ga), may be used as the impurity.

The LDD region141reduces an electric field between the source region142and the drain region143and reduces leakage current. Formation of the LDD region141is optional; as the channel length is reduced, however, forming an LDD region is advantageous.

Referring toFIG. 3H, which shows the device after step S70, when the source region142and the drain region143are formed by implanting impurities into the substrate110at opposing sides of the gate pattern120and the gate spacer124.

In detail, a first spacer-forming insulating layer and a second spacer-forming insulating layer are sequentially formed on sidewalls of the gate pattern120and etched, thereby forming the gate spacer124including a first spacer124aand a second spacer124b. Then, impurities are implanted into the entire surface of the substrate110by performing an ion implantation process using the gate pattern120and the gate spacer124as masks, thereby forming the source region142and the drain region143. Here, the first spacer124amay be formed of a silicon oxide layer and the second spacer124bmay be formed of a silicon nitride layer.

In particular embodiments, the source region142is formed in the recrystallized region130and the drain region143is formed in a non-recrystallized region spaced apart from and facing the source region142with respect to the gate pattern120.

In step S30, an end-of-range (EOR) defect may be generated around the amorphous region130a. The EOR defect may also be generated around the LDD region141, providing the drain region143with further increased gate-induced drain leakage (GIDL). Thus, the drain region143may not be formed in the recrystallized region130, thereby suppressing the leakage current from increasing. Meanwhile, the source region142plays an important role in enhancing the mobility of carriers. The source region142is formed in the recrystallized region130, thereby increasing stress applied to the channel region.

As described above, according to the semiconductor device and the method for manufacturing the same, leakage current can be reduced and channel conductivity can be improved.