Wiring substrate and semiconductor device and method of manufacturing the same

In a wiring substrate of a semiconductor device, a hollow portion is provided under a pad wiring portion including a connection pad, and thus a wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring, and a semiconductor chip is flip-chip connected to the connection pad. The pad wiring portion including the connection pad is formed on a sacrifice layer which is filled in a recess portion in an interlayer insulating layer of the wiring substrate, then the semiconductor chip is flip-chip connected to the connection pad, and then the hollow portion is provided by removing the sacrifice layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority of Japanese Patent Application No. 2007-288890 filed on Nov. 6, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a wiring substrate and a semiconductor device and a method of manufacturing the same and, more particularly, a wiring substrate on which a semiconductor chip is flip-chip mounted, and a semiconductor device constructed by flip-chip mounting the semiconductor chip on the wiring substrate and a method of manufacturing the same.

2. Description of the Related Art

In the prior art, there is a semiconductor device that is constructed by flip-chip mounting a semiconductor on a wiring substrate. As shown inFIG. 1, in a wiring substrate100of a semiconductor device in the prior art, through holes TH are provided on a core substrate200to pass through there, and a through hole plating layer220is provided on inner surfaces of the through holes TH respectively. A resin240is filled in holes of the through holes TH.

Also, a first wiring layer300connected to the through hole plating layers220is formed on an upper surface side of the core substrate200. The first wiring layer300is connected to a lower wiring layer (not shown), which is formed on the lower surface side of the core substrate200, via the through hole plating layers220. Also, a first interlayer insulating layer400is formed on the first wiring layer300, and first via holes VH1whose depth is set to arrive at the first wiring layer300are formed in the first interlayer insulating layer400.

A second wiring layer320connected to the first wiring layer300via the first via holes VH1is formed on the first interlayer insulating layer400.

Also, similarly a second interlayer insulating layer420is formed on the second wiring layer320, and second via holes VH2whose depth is set to arrive at the second wiring layer320are provided in the second interlayer insulating layer420. Also, a third wiring layer340connected to the second wiring layer320via the second via holes VH2is formed on the second interlayer insulating layer420. A solder resist500in which opening portions500aare provided on connection portions respectively is formed on the third wiring layer340.

Also, solder bumps620of a semiconductor chip600are flip-chip connected to the connection portions of the third wiring layer340. Also, an underfill resin700is filled in a clearance between the semiconductor chip600and the wiring substrate100.

In Patent Literature 1 (Patent Application Publication (KOKAI) 2000-22317), it is set forth that, in a method of manufacturing a printed-wiring board to which an IC chip is flip-chip connected, by removing an oxide film on the surface of the solder resist and an organic residue on the metal surface of the pads exposed from opening portions in the solder resist by means of an oxygen plasma, the printed-wiring board that is excellent in connectivity and reliability can be obtained.

Meanwhile, in the above semiconductor device, a coefficient of thermal expansion is different between the wiring substrate100(a resin, a copper wiring, or the like) and the semiconductor chip (silicon chip)600. Therefore, a thermal stress is generated when a heat is applied to the semiconductor device, and accordingly a warp occurs in the semiconductor device in some cases.

In recent years, as the semiconductor chip600, the stained silicon technology has been employed for improving the performance, or the interlayer dielectric layer having low dielectric constant has been employed.

Such high-performance semiconductor chip is relatively weak against the stress, and thus deterioration of operating characteristics is easily caused due to the stress. In the prior art, the underfill resin700is employed as the buffer material that absorbs a difference in coefficient of thermal expansion between the wiring substrate100and the semiconductor chip600. However, it is becoming difficult to protect sufficiently the high-performance semiconductor chip, and it is probable that reliability of the semiconductor device becomes an issue.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a wiring substrate capable of ensuring sufficient reliability by preventing deterioration in performance of a semiconductor chip even when a high-performance semiconductor chip is flip-chip mounted, and a semiconductor device using this wiring substrate and a method of manufacturing the same.

The present invention is concerned with a wiring substrate, which comprises a wiring layer having a pad wiring portion including a connection pad for flip-chip connecting a semiconductor chip, formed on a surface layer side; wherein a hollow portion is provided under the pad wiring portion including the connection pads, thereby the wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring.

In one mode of the present invention, the wiring layers including the connection pads are formed on the insulating layer of the wiring substrate, and the recess portion is provided in the insulating layer under the pad wiring portions including the connection pads to constitute the hollow portion. In this manner, the wiring layers are constructed as the cantilever structure in which the pad wiring portions including the connection pads are formed as the aerial wirings.

Then, the semiconductor device is constructed by flip-chip connecting the semiconductor chip to the connection pads of the wiring substrate. As described above, when a heat is applied to the semiconductor device, a thermal stress is easily caused due to a difference in coefficients of thermal expansion between the wiring substrate and the semiconductor chip. Thus, in some cases the operating performance of the semiconductor chip is deteriorated and also reliability of connection in the semiconductor chip cannot be obtained.

In the present invention, the pad wiring portions including the connection pads to which the semiconductor chip is connected are constructed as the aerial wirings that do not contact the underlying layer. Therefore, the connection portions between the semiconductor chip and the connection pads are provided as the flexible structure that moves vertically like a spring. As a result, a thermal stress caused in the semiconductor chip can be relaxed, and reliability of the electrical connection can be improved.

Also, a stress applied to the semiconductor chip can be absorbed because the connection pads are moved. Therefore, even when the high-performance semiconductor chip that is weak against the stress is mounted, the semiconductor chip can be protected from the stress and deterioration in performance can be prevented.

In the above invention, the semiconductor chip may be hermetically sealed by providing the cap to the wiring substrate in constructing the semiconductor device.

Also, the present invention is concerned with a method of manufacturing a semiconductor device, which comprises the steps of: forming a recess portion in a member for forming a wiring layer on an upper surface; filling a sacrifice layer in the recess portion; forming the wiring layer to extend from the member to the sacrifice layer such that a pad wiring portion including a connection pad of the wiring layer is arranged on the sacrifice layer; flip-chip connecting a semiconductor chip to the connection pad; and providing a hollow portion under the pad wiring portion by removing the sacrifice layer selectively from the member and the wiring layer before or after the step of flip-chip connecting the semiconductor chip.

In the present invention, first, the recess portion is provided in the member (the insulating layer, or the like) on which the wiring layers are to be formed, and the sacrifice layer (the resist layer, or the like) is filled in the recess portion. Then, the wiring layers are formed such that the pad wiring portions including the connection pads are arranged on the sacrifice layer.

Then, in the preferred mode of the present invention, the semiconductor chip is flip-chip connected to the connection pads on the sacrifice layer, and then the hollow portion is constructed under the pad wiring portions by removing selectively the sacrifice layer.

In this mode, the semiconductor chip is mounted in a state that the connection pads are fixed on the sacrifice layer, and then the hollow portion is obtained by removing the sacrifice layer. Therefore, the above semiconductor device in which the semiconductor chip is flip-chip connected to the connection pads acting as the moving portion can be manufactured stably with good yield. Otherwise, the hollow portion may be provided before the semiconductor chip is mounted, and then the semiconductor chip may be flip-chip connected to the connection pads that are arranged on the hollow portion.

As described above, in the present invention, even when the high-performance semiconductor chip is mounted, deterioration of performance of the semiconductor chip can be prevented and thus sufficient reliability can be ensured.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be explained with reference to the accompanying drawings hereinafter.

First Embodiment

FIG. 2toFIG. 8are views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, andFIG. 9is a view showing the semiconductor device similarly.

In the method of manufacturing the semiconductor device of the present embodiment, first, a structure having a sectional structure shown inFIG. 2Ais prepared. Through holes TH are provided in a core substrate10to pass through it in a thickness direction, and a through hole plating layer12is formed on inner surfaces of the through holes TH. A resin11is filled in holes in the through holes TH.

First wiring layers20are formed on both surface sides of the core substrate10respectively such that both layers are connected mutually via the through hole plating layer12. As the core substrate10, a substrate made of a glass cloth that is impregnated with a resin, or the like, a silicon substrate, a glass substrate, or the like is preferably used. When the silicon substrate is employed, an insulating layer is formed on both surfaces of the silicon substrate and inner surfaces of the through holes.

In this case, the through electrode may be filled in all through holes TH, and the first wiring layers20on both surface sides may be connected mutually via the through electrodes.

Then, as shown inFIG. 2B, a first interlayer insulating layer30is formed on the first wiring layers20on both surface sides of the core substrate10respectively by pasting a resin film such as an epoxy resin, a ployimide resin, or the like. When the silicon substrate is employed as the core substrate10, a silicon oxide layer (SiO2), or the like may be formed by the CVD method as the first interlayer insulating layer30.

Also, the first interlayer insulating layer30on both surface sides is processed by a laser, an anisotropic dry etching (RIE, or the like). Thus, first via holes VH1whose depth arrives at the first wiring layers20are formed respectively.

Then, as shown inFIG. 2C, second wiring layers22connected to the first wiring layers20via the first via holes VH1are formed on the first interlayer insulating layer30on both surface sides of the core substrate10respectively. The second wiring layers22are formed by the semi-additive process, or the like.

Then, as shown inFIG. 3A, a second interlayer insulating layer32is formed on the second wiring layers22on both surface sides of the core substrate10respectively. Then, as shown inFIG. 3B, a recess portion C is formed by processing the second interlayer insulating layer32on the upper surface side of the core substrate10. The recess portion C is provided in an area in which the semiconductor chip is mounted (area in which pad wiring portions including connection pads of the wiring substrate are arranged), and is set to have an area that is larger than an area of the semiconductor chip.

In an example inFIG. 3B, the second interlayer insulating layer32still remains on the lower surface of the recess portion C and upper surfaces of the second wiring layers22. In this case, the recess portion C may be formed such that the upper surfaces of the second wiring layers22are exposed. Then, as also shown inFIG. 3D, second via holes VH2whose depth arrives at the second wiring layers22are formed respectively by processing the second interlayer insulating layer32on both surface sides of the core substrate10.

Then, as shown inFIG. 3C, a sacrifice resist layer14is filled in the recess portion C on the second interlayer insulating layer32. The sacrifice resist layer14functions as a dummy layer to shape the recess portion C as a hollow portion, as described later. The sacrifice resist layer14is filled selectively in the recess portion C by the dispenser, the screen printing, or the like.

Alternately, a sacrifice metal layer made of nickel, or the like may be filled in the recess portion C instead of the sacrifice resist layer14. When the sacrifice metal layer is employed, before the second via holes VH2are formed in the second interlayer insulating layer32but after the metal layer is formed like a blanket by the plating method, the sputter method, or the like to embed the recess portion C, the sacrifice metal layer is filled selectively in the recess portion C by polishing the metal layer by means of the CMP, or the like.

Then, as shown inFIG. 4A, a titanium (Ti) layer and a copper (Cu) layer are formed sequentially from the low side on the second interlayer insulating layer32and the sacrifice resist layer14and on the inner surfaces of the second via holes VH2by the sputter method. Thus, a seed layer24ais formed. Otherwise, a Cu layer may be formed by the electroless plating as the seed layer24a.

Then, as shown inFIG. 4B, a plating resist25in which an opening portion25ais provided in the portion in which a third wiring layers are to be arranged is formed on the seed layer24a. Then, a metal plating layer24bmade of Cu, or the like is formed in the opening portion25ain the plating resist25by the electroplating using the seed layer24aas a plating power feeding path. Then, the plating resist25is removed, and then the seed layer24ais etched by using the metal plating layer24bas a mask.

With the above, as shown inFIG. 5, third wiring layers24are formed on the second interlayer insulating layer32and the sacrifice resist layer14. InFIG. 5, the third wiring layers24are illustrated as a single layer, but actually is composed of the seed layer24aand the metal plating layer24b. The third wiring layers24are connected to the second wiring layers22via the second via holes VH2respectively.

Also, the third wiring layers24are extended from the second interlayer insulating layer32to the sacrifice resist layer14in a recess portion C, and thus pad wiring portions23including connection pads P respectively are arranged side by side on the peripheral side on the sacrifice resist layer14. When a state of the pad wiring portions23in a sectional view inFIG. 5is viewed from the top, as shown in a plan view inFIG. 5, the pad wiring portions23of the third wiring layers24are extended onto the sacrifice resist layer14filled in the recess portion C, and the connection pads P are arranged side by side in a peripheral type on the peripheral side on the sacrifice resist layer14.

Similarly, the third wiring layers24connected to the second wiring layers22via the second via holes VH2respectively are also formed on the second interlayer insulating layer32on the lower surface side of the core substrate10.

Then, as shown inFIG. 6, a solder resist26in which opening portions26aare provided on the connection pads P of the third wiring layers24respectively is formed. By reference to a plan view ofFIG. 6together, a ring-like etching opening portion E is formed at the same time on the solder resist26around the peripheral portion on the sacrifice resist layer14. Also, the solder resist26in which opening portions26aare provided on the connection pads P of the third wiring layer24respectively is formed on the lower surface side of the core substrate10. Also, a Ni/Au plating for the connection is applied to the connection pads P that are exposed from the opening portions26ain the solder resist26on both surface sides of the core substrate10.

Then, as shown inFIG. 7, bumps40aof a semiconductor chip40are flip-chip connected to the connection pads P of the third wiring layers24on the upper surface side of the core substrate10. Then, an elastic resin16is filled in a clearance between the semiconductor chip40and the underlying solder resist26. The elastic resin16is made of a polymeric substance that exhibits a rubber elasticity, and its Young's modulus is 100 to 500 MPa. As the elastic resin16, for example, a silicone rubber is used.

Then, as shown inFIG. 8, the sacrifice resist layer14located below the semiconductor chip40is removed by dipping the resultant structure inFIG. 7into a resist removing liquid, or the like. At this time, the resist removing liquid is passed through the etching opening portion E in the solder resist26and a space between the pad wiring portions23(see a plan view inFIG. 6), and is fed to the sacrifice resist layer14. Thus, the sacrifice resist layer14is removed. Since the solder resist26has been cured completely and has a resistance against the resist removing liquid, only the uncured sacrifice resist layer14is selectively removed.

Here, when the above-mentioned sacrifice metal layer is used instead of the sacrifice resist layer14, such sacrifice metal layer (Ni layer, or the like) is etched by using the wet etchant. This wet etchant has the etching selectivity against the third wiring layer24(Cu layer), the second interlayer insulating layer32(resin layer), and the like.

In this manner, as shown inFIG. 9, the sacrifice resist layer14in the recess portion C of the second interlayer insulating layer32is removed totally. Therefore, a hollow portion H is provided below the pad wiring portions23including the connection pads P to which the semiconductor chip40is flip-chip connected. As a result, the pad wiring portions23including the connection pads P to which the semiconductor chip40is connected are constructed as aerial wirings which are arranged on the hollow portion H respectively.

With the above, a semiconductor device1of the present embodiment is obtained.

In this case, in the above method of manufacturing the semiconductor device, in order to secure the stability of flip-chip connection, first, the semiconductor chip40is flip-chip connected to the connection pads P of a wiring substrate2, and then the hollow portion H is provided by removing the sacrifice resist layer14. In case the connection pads P provided on the hollow portion H can withstand the flip-chip connection when the length of the pad wiring portions23is shortened, or the like, it is possible to flip-chip connect the semiconductor chip40to the connection pads P after the hollow portion H is provided. In this case, the elastic resin16filled under the semiconductor chip40is omitted.

Also, in the present embodiment, an example where the hollow portion H is provided in the second interlayer insulating layer32under the third wiring layers24is illustrated. The hollow portion may be provided in the member under the pad wiring portions including the connection pads to which the semiconductor chip is flip-chip connected. Accordingly, for example, when the wiring layers having the connection pads are formed on the core substrate10, the similar hollow portion H is provided in the core substrate10.

As shown inFIG. 9, the semiconductor device1of the present embodiment is constructed basically by flip-chip connecting the semiconductor chip40to the connection pads P of the wiring substrate2. In the wiring substrate2, the through hole plating layer12is formed on the inner surfaces of the through holes TH provided in the core substrate10respectively, and the resin11is filled in holes in the through holes TH.

The first wiring layers20connected mutually via the through hole plating layers12are formed on both surface sides of the core substrate10respectively. The second wiring layers22are formed on the first wiring layers20on both surface sides of the core substrate10via the first interlayer insulating layer30respectively. The second wiring layers22are connected to the first wiring layers20via the first via holes VH1provided in the first interlayer insulating layer30respectively.

Also, the second interlayer insulating layer32is formed on the second wiring layers22on both surface sides of the core substrate10respectively. By reference to a perspective view inFIG. 9together, the recess portion C whose area is larger than an area of the semiconductor chip40is provided in the second interlayer insulating layer32on the upper surface side of the core substrate10under the semiconductor chip40. The recess portion C is shaped into the hollow portion H that is made empty like a hollowed-out shape.

Also, the second via holes VH2that reach the second wiring layers22respectively are provided in the second interlayer insulating layer32, and the third wiring layers24connected to the second wiring layers22via the second via holes VH2respectively are formed on the second interlayer insulating layer32. The third wiring layers24are extended from the second interlayer insulating layer32onto the hollow portion H, and the pad wiring portions23including the connection pads P are arranged on the hollow portion H. The connection pads P are arranged side by side in a peripheral type on the peripheral side of the hollow portion H (seeFIG. 6and a plan view inFIG. 7).

In this manner, one end sides of the third wiring layers24are fixed onto the second interlayer insulating layer32, while the pad wiring portions23including the connection pads P of the other end side are arranged as the aerial wiring on the hollow portion H. That is, in the third wiring layers24, the pad wiring portion23including the connection pads P has a cantilever structure acting as the aerial wiring (moving portion). A depth of the hollow portion H can be set to 20 to 100 μm, for example. Also, a length of the pad wiring portions23(length protruded from the side surface of the recess portion C toward the inner side) can be set to 50 μm to 1 mm, for example.

In this case, when an elastic force of the pad wiring portions23as the aerial wiring respectively should be enhanced further more, the third wiring layers24may be constructed by coating the side surfaces and the upper surface of the Cu layer with a Ni layer whose elasticity is strong. Also, the third wiring layers24may be formed of a single-layered Ni layer if such third wiring layers do not interfere with the electric characteristics.

Also, the third wiring layers24connected to the second wiring layers22via the second via holes VH2respectively are also formed on the second interlayer insulating layer32on the lower surface of the core substrate10.

Also, the solder resist26in which the opening portions26aare provided on the connection pads P is formed on the third wiring layers24on both surface sides of the core substrate10respectively. The ring-like etching opening portion E is provided around the peripheral portion of the hollow portion H in the solder resist26on the upper surface side of the core substrate10. As described above, the sacrifice resist layer14is removed through the etching opening portion E in the solder resist26, and the hollow portion H is formed.

Then, the bumps40aof the semiconductor chip40(LSI chip) are flip-chip connected to the connection pads P of the third wiring layers24on the upper surface side of the core substrate10. The elastic resin16is filled in a clearance between the semiconductor chip40and the wiring substrate2. In this case, the elastic resin16is not always provided.

In the semiconductor device1of the present embodiment, the third wiring layers24have such a cantilever structure that the pad wiring portion23is arranged on the hollow portion H respectively, and the connection pads P constitute the moving portions that can move vertically and have an elastic force. Also, the bumps40aof the semiconductor chip40are flip-chip connected to the connection pads P.

The wiring substrate2(resin, Cu wiring, or the like) and the semiconductor chip40(silicon) have mutually a different coefficient of thermal expansion. Therefore, when a heat is applied in applying the reliability test to the semiconductor device1or using actually the semiconductor device1, a thermal stress is caused due to a difference between the coefficients of thermal expansion, and thus a stress is applied to the semiconductor device1.

In the present embodiment, even when a stress is applied to the semiconductor device1, the pad wiring portions23(the connection pads P) move flexibly to accommodate to the stress and absorb the stress. Also, when the elastic resin16is filled under the semiconductor chip40, a stress applied to the semiconductor chip40can be further dispersed.

In this manner, in the semiconductor device1of the present embodiment, the connection portions between the wiring substrate2and the semiconductor chip40are formed as the flexible structure. Therefore, a thermal stress caused between both members can be relaxed, and reliability of the electrical connection between the semiconductor chip40and the wiring substrate2can be improved. Also, a stress applied to the semiconductor chip40itself can be relaxed. Therefore, even when the high-performance semiconductor chip that employs the stained silicon technology or the interlayer insulating layer of a low dielectric constant to improve the performance is mounted, the semiconductor chip40can be protected from a stress and its deterioration of performance can be prevented.

A semiconductor device1aaccording to a first variation of the present embodiment is shown inFIG. 10. In the semiconductor device1aof the first variation, a sealing cap50is provided to the wiring substrate2of the semiconductor device1inFIG. 9, and the semiconductor chip40is hermetically sealed in a housing portion S constructed by the sealing cap50and the wiring substrate2. In the semiconductor device1aof the first variation, reliability of the semiconductor chip40whose performance is readily deteriorated due to a moisture can be improved.

Also, a semiconductor device1baccording to a second variation of the present embodiment is shown inFIG. 11. In the semiconductor device1bof the second variation, the semiconductor chip40(the logic LSI, or the like) that generates easily a heat during the operation may be hermetically sealed by providing a radiation cap52made of a metal (Cu, or the like) of high thermal conductivity on the wiring substrate2. In this case, a thermally conductive adhesive54is provided between the upper surface of the semiconductor chip40and an inner surface of the radiation cap52.

Accordingly, a heat generated from the semiconductor chip40can be transferred to the radiation cap52side via the thermally conductive adhesive54. Therefore, the heat generation of the semiconductor chip40can be suppressed, and the semiconductor chip40can be stably operated.

Also, a semiconductor device1caccording to a third variation of the present embodiment is shown inFIG. 12. In the semiconductor device1cof the third variation, the solder resist26formed on the upper surface side of the core substrate10and described above inFIG. 9is omitted. In the case of this mode, the sacrifice resist layer14can also be removed by the dry ashing using an oxygen plasma, upon removing the above sacrifice resist layer14(FIG. 8).

The dry ashing is applied from a surface of the sacrifice resist layer14to an inside thereof, which is exposed from a ring-like peripheral portion D (a plan view inFIG. 12) located outside the semiconductor chip40, and thus the hollow portion H is provided. In this case, in the semiconductor device1cof the third variation inFIG. 12, the semiconductor chip40can be hermetically sealed by providing the sealing cap50or the radiation cap52, likeFIG. 10andFIG. 11.

As explained above, the solder resist26in which the opening portions26aare provided on individual connection pads P respectively is formed inFIG. 9. Alternately, a solder resist in which an opening portion for exposing collectively a plurality of connection pads P on the third wiring layer24is provided may be formed.

Second Embodiment

FIG. 13is a sectional view and a plan view showing a semiconductor device according to a second embodiment of the present invention.

In the above first embodiment, the connection pads P of the third wiring layers24are arranged on the peripheral side of the hollow portion H in a peripheral type. In the second embodiment, as shown inFIG. 13, the connection pads P of the third wiring layers24are arranged on the hollow portion H in an area-array type.

That is, the pad wiring portions23of a plurality of third wiring layers24are extended to not only the peripheral portion of the hollow portion H but also the center portion, and the connection pads P are arranged on the hollow portion H in grid-like fashion. Accordingly, like the first embodiment, the pad wiring portions23are formed as the aerial wiring that is arranged on the hollow portion H and moved vertically respectively.

Also, the bumps40aof the semiconductor chip40are arranged in an area-array type to correspond to the connection pads P on the third wiring layer24. Then, the bumps40aof the semiconductor chip40are flip-chip connected to the connection pads P on the third wiring layer24of the wiring substrate2, and the elastic resin16is filled under the semiconductor chip40.

In the second embodiment, a length of the pad wiring portions23is increased longer than that in the first embodiment, and a strength of the pad wiring portion23is relatively weak. Therefore, it is preferable that the method in which after the semiconductor chip40is mounted, the sacrifice resist layer14is removing is employed.

In addition, like the first embodiment inFIG. 10andFIG. 11, the semiconductor chip40may be hermetically sealed by providing the sealing cap50or the radiation cap52.

The second embodiment can achieve the similar advantages to those of the first embodiment.