Data output circuit of memory device

A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in response to a read command and outputting a plurality of output enable signals in response to a rising DLL clock and a falling DLL clock. The output driving unit drives data synchronously with respect to the rising DLL clock and the falling DLL clock in response to the output enable signals at a read mode. The output enable control unit disables the falling DLL clock when the output enable signals are all disabled. As a result, current consumption is reduced because the falling DLL clock is generated only when the output enable signal is generated.

BACKGROUND ART

1. Field of the Invention

The present invention generally relates to a data output circuit of a memory device, and more specifically, to a technology of generating a clock only when an output enable signal is generated to reduce current consumption.

2. Description of the Prior Art

FIG. 1is a block diagram illustrating a conventional data output circuit of a memory device. Here, a circuit having a burst length of 4 and a CAS latency of 6 is exemplified.

The conventional data output circuit of a memory device comprises a rising clock driving unit2, a falling clock driving unit4, an output enable signal generating unit6and an output driving unit8.

The rising clock driving unit drives an internal rising DLL clock IRCKDLL generated from a Delay Locked Loop (hereinafter, abbreviated as “DLL”) to generate a rising DLL clock RCKDLL. The falling clock driving unit4drives an internal falling DLL clock IFCKDLL generated from the DLL to generate a falling DLL clock FCKDLL.

The output enable signal generating unit6generates a reference output enable signal OE00in response to a read command RD, output enable signals OE10, OE20, OE30, OE40, OE50and OE60in response to the rising DLL clock RCKDLL, and output enable signals OE15, OE25, OE35, OE45and OE55in response to the falling DLL clock FCKDLL.

The output driving unit8drives data inputted synchronously with respect to the rising DLL clock RCKDLL and the falling DLL clock FCKDLL in response to enable signals OE00˜OE60when the data are read, and outputs the driven data to an input/output pad DQ.

FIG. 2is a timing diagram illustrating the operation of the data output circuit ofFIG. 1.

The reference output enable signal OE00is generated in response to the read command RD generated synchronously with respect to an external clock CLK inputted from a chip set.

Then, the output enable signals OE10˜OE60are sequentially generated in response to the rising DLL clock RCKDLL before the external clock CLK.

Also, the output enable signals OE15˜OE55are sequentially generated in response to the falling DLL clock CKDLL before a clock having an opposite phase to that of the external clock CLK.

Thereafter, first and third data DQ are outputted in response to the rising DLL clock RCKDLL (6.0and7.0), and second and fourth data DQ are outputted in response to the falling DLL clock FCKDLL (6.5and7.5).

The conventional data output circuit of a memory device, which includes a DLL, outputs the data DQ synchronously with respect to the rising DLL clock RCKDLL and the falling DLL clock FCKDLL. Here, the rising DLL clock RCKDLL is used in a replica delay block of the DLL, and the falling DLL clock FCKDLL is used only to output the corresponding data DQ. As a result, unnecessary operation current is consume when the corresponding data DQ are not outputted.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to generate a falling DLL clock at a read mode while data are outputted, thereby reducing operation current.

In an embodiment, a data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in response to a read command and outputting a plurality of output enable signals in response to a rising DLL clock and a falling DLL clock. The output driving unit drives data synchronously with respect to the rising DLL clock and the falling DLL clock in response to the output enable signals at a read mode. The output enable control unit disables the falling DLL clock when the output enable signals are all disabled.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3is a block diagram illustrating a data output circuit of a memory device according to an embodiment of the present invention. Here, a circuit having a burst length of 4 and a CAS latency of 6 is exemplified.

In an embodiment, a data output circuit of a memory device comprises a rising clock driving unit12, a falling clock driving unit14, an output enable signal generating unit16, an output driving unit18and an output enable control unit20.

The rising clock driving unit12drives an internal rising DLL clock IRCKDLL generated from a DLL, and generates a rising DLL clock RCKDLL. The falling clock driving unit14drives an internal falling DLL clock IFCKDLL generated from the DLL, and generates a falling DLL clock FCKDLL.

The output enable signal generating unit16generates a reference output enable signal OE00in response to a read command RD, output enable signals OE10, OE20, OE30, OE40, OE50and OE60in response to the rising DLL clock RCKDLL, and output enable signals OE15, OE25, OE35, OE45and OE55in response to the falling DLL clock FCKDLL.

The output driving unit18outputs data DQ synchronously with respect to the rising DLL clock RCKDLL and the falling DLL clock FCKDLL in response to the output enable signals OE00˜OE60at a read mode.

The output enable control unit20outputs a sum output enable signal OESUM obtained by summing the output enable signals OE00˜OE60outputted from the output enable signal generating unit16, and controls the falling clock driving unit14.

FIG. 4is a circuit diagram illustrating the falling clock driving unit14ofFIG. 3.

The falling clock driving unit14comprises a PMOS transistor PT1, NMOS transistors NT1and NT2, and a latch unit22. Here, the latch unit22includes inverters IV1and IV2.

The PMOS transistor PT1and the NMOS transistor NT1has a common gate to receive the internal falling DLL clock IFCLDLL, and the NMOS transistor NT2selectively connects a source of the NMOS transistor NT1to a ground terminal in response to the sum output enable signal OESUM.

The latch unit22latches a potential in a common drain of the PMOS transistor PT1and the NMOS transistor NT1, and outputs the falling DLL clock FCKDLL.

FIG. 5is a circuit diagram illustrating the output enable control unit20ofFIG. 3.

The output enable control unit20comprises a plurality of OR gates OR1˜OR4.

The first OR gate OR1performs an OR operation on the reference output enable signal OE00, the first output enable signal OE10and the second output enable signal OE20. The second OR gate OR2performs an OR operation on the third output enable signal OE30and the fourth output enable signal OE40. The third OR gate OR3performs an OR operation on the fifth output enable signal OE50and the sixth output enable signal OE60.

The fourth OR gate OR4performs an OR operation on output signals from the OR gates OR1, OR2and OR3to output the sum output enable signal OESUM.

FIG. 6is a timing diagram illustrating the operation of the data output circuit ofFIG. 3.

The reference output enable signal OE00is generated in response to the read command RD synchronously with respect to the external clock CLK inputted from a chip set.

The output enable signals OE10˜OE60are sequentially generated in response to the rising DLL clock RCKDLL before the external clock CLK.

Then, the output enable signals OE15˜OE55are sequentially outputted in response to the falling DLL clock FCKDLL before a clock having an opposite phase to that of the external clock CLK.

Thereafter, first and third data DQ are outputted in response to the rising DLL clock RCKDLL (6.0and7.0), and second and fourth data DQ are outputted in response to the falling DLL clock FCKDLL (6.5and7.5).

The sum output enable signal OESUM becomes ‘high’ when one of the output enable signals OE00˜OE60is enabled to a high level. Then, the falling clock driving unit14generates a falling DLL clock FCKDLL in response to the internal falling DLL clock IFCKDLL.

Meanwhile, the sum output enable signal OESUM becomes ‘low’ when all of the output enable signals OE00˜OE60are disabled to a low level, thereby maintaining the falling DLL clock FCKDLL at a low level.

As a result, the operation of all circuits that receives the falling DLL clock FCKDLL is stopped, thereby reducing operation current.

As discussed earlier, a data output circuit of a memory device according to an embodiment of the present invention generates a falling DLL clock only while an output enable signal is enabled to a high level, and stops the operation of all circuits that receives the falling DLL clock, thereby reducing operation current.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.