State maintenance pulsing for a memory device

State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.

FIELD OF THE INVENTION

One or more aspects of the invention generally relate to state maintenance of a memory cell and, more particularly, to state maintenance pulsing of identified memory cells more frequently than other memory cells.

BACKGROUND OF THE INVENTION

Conventionally, dynamic memories, such as dynamic random access memories (“DRAMs”) require a periodic refresh. For DRAMs, this conventionally means a destructive read is done, followed by a write back of the information read. Furthermore, some memory cells in an array of memory cells of a DRAM may need to be refreshed more often than other memory cells. This is generally due to some memory cells being more susceptible to charge leakage at various operating parameters.

To increase yield of DRAMs, as well as to affect overall refresh rate, it has been proposed by others to identify memory cells needing to be refreshed more often than other memory cells. These so-called weaker memory cells could then be refreshed more often than their counterpart stronger memory cells. Additional details regarding this proposed refresh approach may be found in U.S. Pat. No. 5,644,545 B1.

For a new type of memory cell known as a thyristor-based memory cell, no refreshing is used. In other words, there is no destructive read followed by a write back to refresh a memory cell back to its original state. Rather than refreshing, a thyristor-based memory cell is periodically pulsed. This pulsing is done at a frequency such that the thyristor-based memory cell maintains its current state. Additional details regarding periodically pulsing a thyristor-based memory cell may be found in Patent Cooperation Treaty (“PCT”) International Publication WO 02/082504.

Like DRAM cells, some thyristor-based memory cells may be more susceptible to charge leakage at various operating parameters due to defects or statistical variations of process parameters. Accordingly, it would be desirable and useful to provide means to maintain state of such thyristor-based memory cells more susceptible to charge leakage than other such thyristor-based memory cells of the same memory integrated circuit without spending the additional power to pulse all memory cells in an array at a frequency associated with those cells more susceptible to charge leakage, namely a “higher frequency.”

SUMMARY OF THE INVENTION

One or more aspects of the invention generally relate to state maintenance of a memory cell and, more particularly, to state maintenance pulsing of identified memory cells more frequently than other memory cells.

An aspect of the invention is an integrated circuit having memory. The memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. The first restore address is associated with a first line in the array of memory cells. The second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.

Another aspect of the invention is a method for maintaining state of stored data. A clock signal is provided. A selective restore mode is selectively activated. At least one selective restore address for the selective restore mode is provided and selected as a first wordline restore address for a first wordline in an array of memory cells. A restore pulse is applied to each memory cell associated with the first wordline responsive to the clock signal. The selective restore mode for a global restore mode is selectively deactivated.

Yet another aspect of the invention is an integrated circuit having memory, including: a memory array including an array of memory cells; and state maintenance circuitry coupled to the array of memory cells, where the state maintenance circuitry is configured to select between a selective address and a global address. The selective address is associated with at least one memory cell in the array of memory cells to be pulsed greater than a threshold amount, and the global address is associated with at least one other memory cell in the array of memory cells to be pulsed the threshold amount. The at least one memory cell and the at least one other memory cell are each configured such that pulsing with a short duration pulse maintains data state respectively thereof by application of a state maintenance pulse to at least one access wordline associated with the at least one memory cell and the at least one access wordline or another at least one access wordline associated with the at least one other memory cell.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well-known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items, however, in alternative embodiments the items may be different. Moreover, for purposes of clarity, a single signal or multiple signals may be referred to or illustratively shown as a signal to avoid encumbering the description with multiple signal lines. Moreover, along those same lines, a multiplexer or a register, among other circuit elements, may be referred to or illustratively shown as a single multiplexer or a single register though such reference or illustration may be representing multiples thereof. Furthermore, though particular signal bit widths, data rates, and frequencies are described herein for purposes of clarity by way of example, it should be understood that the scope of the description is not limited to these particular numerical examples as other values may be used.

FIG. 1Ais a schematic diagram depicting an exemplary embodiment of a memory array100. Memory array100includes thyristor-based memory cells101. Pairs of memory cells101may be commonly coupled at a bitline contact106for connection to a bitline110and may be commonly coupled at a supply voltage contact107for connection to a supply voltage line113. Notably, voltage on supply voltage line113is above both a logic low voltage reference level (“Vss”) and a logic high voltage reference level (“Vdd”), and this supply voltage may be used as an anodic voltage for memory cell101. Accordingly, reference to this supply voltage includes its anodic use, and as such it is referred to herein as “VDDA” to clearly distinguish it from Vdd. Thus, supply voltage line113is subsequently referred to herein as anode voltage line113, and supply voltage contact107is subsequent referred to herein as anode contact107.

Each memory cell101includes an access device (“transistor”)108; which may be a field effect transistor (“FET”), and a thyristor-based storage element102. Notably, access device108need not be a transistor; however, for purposes of clarity by way of example access device108shall be referred to herein as transistor108. Storage element102and transistor108may be commonly coupled at a node109. Node109may be a cathodic node of storage element102and a source/drain node of transistor108, and thus may be referred to hereafter as cathode node109.

Illustratively shown inFIG. 1Ais an equivalent circuit model of storage element102having cross coupled bi-polar junction transistors (“BJTs”)103and104, as well as capacitor105. Storage element102may be a type of a device known as Thin Capacity Coupled Thyristor (“TCCT”) device. Again, in this example, storage element102is coupled in series with an n-MOS transistor108to provide memory cell101. However, a p-MOS architecture may be used.

For each memory cell101, a gate of access transistor108is formed from a wordline (“WL1”)111in relation to an active area, as generally indicated inFIG. 1Aby small dots coupling gates of access transistors108to WL1s111. A control gate of storage element102, generally indicated as a plate of capacitor105, is formed with another wordline (“WL2”)112, as generally indicated by small dots coupling plates of capacitor105to WL2s112. Though only a few rows of memory cells101are illustratively shown inFIG. 1A, it should be appreciated that many more rows may be used. The exact number of memory cells or bits associated with a WL1111or a WL2112may vary from application to application. However, for purposes of clarity by way of example and not limitation, it shall be assumed that there are 144 memory cells coupled to each WL1111and 18 memory cells coupled to each WL2112, though other numbers for either or both may be used.

An emitter node of BJT103is coupled to anode voltage line113by anode contact107. A base of BJT103is coupled a collector of BJT104. An emitter of BJT104is coupled to cathode node109. A base of BJT104and a collector of BJT103are commonly coupled to a bottom plate of capacitor105, and this common coupling location may be generally referred to as storage node150.

FIG. 1Bis a cross-sectional view depicting an exemplary embodiment of a device structure for a memory cell101ofFIG. 1A. In this embodiment, memory cell101is formed using a silicon-on-insulator (“SOI”) wafer having a substrate layer120on which a buried oxide (“BOx”) layer130is formed. Formed on BOx layer130is an active silicon layer140. Though an SOI wafer is generally illustrated inFIG. 1B, other known types of semiconductor wafers may be used.

In active silicon layer140, anode region121, base region122, base region141, cathode region109, and bitline access region123are formed. Base region141is located between base region122and cathode region109of storage element102. Between cathode node109and access region123is access device body region142. In an embodiment, regions121,141, and142may be p-type regions, and regions109,122, and123may be n-type regions. Above regions141and142may respectively be formed one or more dielectric layers124and129. Above one or more dielectric layers124and129may respectively be formed wordlines111and112ofFIG. 1A, which in association with regions141and142are defined gates125and126, respectively. Notably one or more dielectric layers124and129may be the same or different sets of layers, and such gate dielectric as associated with gate126and one or more dielectric layers124may be thinner than such gate dielectric associated with gate125and dielectric layers129. Gate126is a gate of transistor108and an access gate of memory cell101, and gate125is a control gate of storage element102and a write gate of memory cell101. An anode contact107is coupled to anode region121, and a bitline contact106is coupled to access region123. Notably, access region123and cathode node109also serve as source/drain regions of transistor108. Other details regarding memory cell101, including silicides, extension regions, and spacers, among other known details, may be found in U.S. Pat. Nos. 6,767,770 B1 and 6,690,039 B1.

FIG. 2is a high-level block diagram depicting an exemplary embodiment of a thyristor-based memory200. Memory200includes input/output ring210, memory arrays100, redundant circuitry blocks202, periphery circuitry201. Periphery circuitry201may include restore circuitry203. In this exemplary embodiment, two redundant circuitry blocks202are illustratively shown for each memory array100, though only one such block may be used for each memory array100.

With continuing reference toFIG. 2, and renewed reference toFIG. 1A, memory200is further described. As is known, some of memory cells101of a memory array100may not store charge as long as other memory cells101of memory array100. Furthermore, as is known, some of memory cells101of a memory array100may be more likely to have charge leak into them than other memory cells of memory array100. Accordingly, each memory cell101may have a minimum threshold time for which it stores a logic level1and may have a minimum threshold time for which it stores a logic level0. Certain memory cells101which are more susceptible to charge leakage than other memory cells101of memory array100may be identified using known testing methodologies. Furthermore, memory cells101of memory array100which are more susceptible to charge leakage into such cells may be identified by known testing methodologies. Accordingly, an address of each “less stable” cell, namely each cell more susceptible to leakage on or off or both, may be identified and mapped into restore circuitry203. Notably, some of these weak cells may be on a same WL1111or WL2112.

Restore circuitry203may include non-volatile programmable memory, fuses, anti-fuses, or other known non-volatile programmable elements, which may be used for programming in one or more addresses of defective memory cells101of memory array100. Thus, these addresses could be registered as part of a power-up sequence for memory200. In this manner, yield of memory200may be increased, as it may be sufficient to “restore” such less stable memory cells more frequently than their counterpart more stable memory cells of memory array100. Notably, the term “restore” is used herein to refer to pulsing a memory cell to bring its level of charge up or down, depending on store state, to a more acceptable level without having to perform a read or write operation on such memory cell. Notably, restore pulsing is done prior to a memory cell reaching a change of state, and thus restore should not be interpreted as though state of a memory cell has changed. Moreover, such restore pulsing may be done prior to a memory cell reaching a metastable state.

FIG. 3is a graphical diagram depicting an exemplary embodiment of charge leakage and charge restoration in both positive and negative directions. With simultaneous reference toFIGS. 1A,1B, and3, the diagram ofFIG. 3is further described. For example, suppose the logic high level is VDDA301as associated with stored charge for storing a logic1, and suppose the logic low level is Vss302as associated with stored charge for a logic0. Thus, dashed line303indicates charge leakage from a memory cell101, and dashed line304indicates charge leakage into a memory cell101. Voltage levels associated with dashed lines303and304may not be allowed to reach metastable voltage levels305to prevent a memory cell101from becoming unstable. In order to restore a memory cell101, a short duration pulse306is applied to WL1111ofFIG. 1A.

Accordingly, a restoring pulse to WL1111with bitline110held at ground is applied prior to reaching metastable voltage levels305from either a positive or a negative direction such that a memory cell101has its charge appropriately restored. Thus, voltage levels associated with levels303and304before application of restore pulse306are heading toward metastable voltage levels305, and after application of restore pulse306such voltage levels are being drawn back to VDDA301and Vss302, respectively.

Thus, a logic0stored in a memory cell101is restored by a pull down operation. In other words, a logic0stored in a memory cell101is made more stable by application of a short duration pulse to gate access transistor108to temporarily couple p-base141to a logic low voltage level, such as ground, via bitline110. This helps maintain such a memory cell101in generally a current blocking state by pulling p-base141to ground for example. Like restoration of a logic0voltage level, a short duration pulse is applied to gate access transistor108to temporarily couple storage element102to ground via bitline110. However, in contrast to restoration of a logic0voltage level, because a memory cell101storing a logic1is generally in a current conducting state, storage element102progressively returns to a more stable conductive state responsive to this coupling of p-base141to ground for example. In this type of restore, p-base141may be brought at or near to a VDDA level.

FIG. 4is a high-level block diagram depicting an exemplary embodiment of a memory array block404such as of memory100ofFIG. 2. A portion of a memory array known as a “rib” may include two memory array blocks404in succession. Memory array block404includes eight MATs, or four MAT2s406. Each MAT2406includes eight tiles407. Separating two MAT2s406on each side of block404is a WL2predecoder405. Horizontally extending across memory array block404is rib control logic401. It should be understood that each tile407includes a WL2decoder402. Moreover, it should be understood that each MAT2includes a WL1decoder403. For purposes of clarity by way of example and not limitation it shall be assumed that a rib is2304bits wide by256bits deep, which is divided into 16 MATs. Thus, with renewed reference toFIG. 1A, each WL1111is coupled to 2304/16 or 144 memory cells or bits, and there are 256 rows of WL1s111.

FIG. 5is a signal diagram depicting an exemplary embodiment of a restore pulse cycling500. Restore cycles (“RCS”)501for less stable memory cells101are followed by restore cycles502for memory cells with acceptable stability. RCS501and502may be based upon cycles of a clock signal511, where an RCS signal513is toggled from a logic low to logic high level to be in either a mode for RCS501or502. Thus, memory cells101that do not have acceptable stability, but for additional restore pulsing, are restored repeatedly during each set of restore cycles501, and memory cells101having acceptable stability, as well as those memory cells not having acceptable stability, are restored during restore cycles502. Thus, continuing the above numerical example, a counter may count from 0 to 255 for each group of 256 WL1s111to provide 256 restore cycles or pulses502, namely one for each WL1111of the group of256. However, the number of restore cycles501may depend on the number of WL1s111within a grouping having at least one less stable memory cell. Notably, a counter counting for example from 0 to 255, may be paused for restore cycles501, and then restarted after completion of restore cycles501. So, for example, the counting for normal restore cycles for the above example would be from 0 to 255 followed by pause for restore cycles501, and then the counting would begin again at 256 to 511 after the restore cycles501. Notably, the same addresses for selective restore cycles501are repeatedly used during each set of restore cycles501. This would continue until each WL1111is pulsed. For the above example, the counter would roll over after 2303.

Continuing the above example of 16 MATs to a row, a numerical value associated therewith termed “numMAT” may be used to set either all 16 MATS of a rib or just a portion thereof to be addressed within a restore cycle. Thus, for example, numMAT may be set equal to values of 1, 2, 4, 8, and 16.

FIG. 6is a high-level signal diagram depicting an exemplary embodiment of read/write signal timing600with restore pulsing. To write a logic1, namely write one operation601, WL1voltage611is brought to a logic high level as generally indicate by pulse621and WL2voltage612is brought to a logic high level as generally indicated by pulse631. Notably, for a write one operation601, bitline voltage610is held at a logic low level. After WL1voltage611is de-asserted, a restore pulse620may be applied to WL1111with this WL1having just been used to complete a write one operation601or another WL1located anywhere in the array, including on the same bitline. Immediately following such a write one operation601and such read/write cycle interstitial restore pulse620, WL1voltage611may be brought to a logic level high again as generally indicated by pulse622for a read one operation602, namely to read the logic1previously written to a memory cell101associated with WL1voltage611being asserted. Waveform633of bitline voltage610generally indicates that a logic1was read from the memory cell101accessed. Between read one operation602and a write zero operation603, another interstitial restore pulse620may be asserted.

With continuing reference toFIG. 6and renewed reference toFIG. 1A, the timing examples ofFIG. 6are further described. For a write zero operation603following read one operation602, WL1voltage611is brought to a logic high level, as generally indicated by pulse623. Additionally, while pulse623is asserted, WL2voltage612is brought to a logic high level, as generally indicated by pulse632. Furthermore, for a write zero operation603, bitline voltage610is brought to a logic high level as generally indicated by pulse634. Thus, storage element102is coupled to bitline voltage610via access transistor108being in a conductive state. Moreover, storage element102is pulled high by bitline voltage610. Accordingly, storage element102is put into a substantially non-current-conductive state, namely a current blocking state. Subsequent to pulse623and prior to a subsequent read zero operation604, an interstitial restore pulse620may be asserted. For a read zero operation604, WL2voltage612is in a logic low state, and WL1voltage611is brought to a logic high level as generally indicated by pulse624. As indicated by bitline voltage610for a read zero operation604, a logic0voltage level is read, since the thyristor-based storage element102is in the non-current-conductive state which results in providing no current to pull up bitline voltage610. After assertion of pulse624and prior to another read or write operation of memory cell101, another interstitial restore pulse620may be asserted. Notably, restore pulses620do not need to be asserted after each write or after each read operation, as illustratively shown in this example. However, this example does clearly indicate that restore pulses may be included within read/write cycling of a memory cell101for successive write and read operations involving the same WL1111. Accordingly, it should be appreciated that restore pulsing may be done without having to resort to halting a write operation, halting a read operation, or any combination thereof. Moreover, it should be appreciated that interstitial restore pulses620may be inserted between successive write operations or successive read operations, though read-after-write operations are illustratively shown inFIG. 6.

FIG. 7is a high-level block diagram depicting an exemplary embodiment of memory200having selective restore circuitry203. In this example, rib400-0(“rib0”) and rib400-1(“rib1”) are illustratively shown. However, it should be appreciated that fewer or more ribs may be implemented. For clarity way of example and not limitation, a fuse bank750may be coupled to ribs, including ribs0and1. Fuse bank750may be used to store address locations to identify locations to be selectively restored. Moreover, as described elsewhere herein other circuit elements, other than fuses, may be used. Notably, fuse bank750may be partitioned such that portions thereof are respectively associated with ribs.

For each rib0and1, there are respective selective restore circuits702-0and702-1associated therewith. For example, rib0has associated therewith selective restore circuit702-0of restore circuitry203, and rib1associated therewith selective restore circuit702-1of restore circuitry203. Associated with each rib0and1is a WL1predecoder. Thus, for example, rib0has associated therewith WL1predecoder700-0, and rib1has associated therewith WL1predecoder701-1. WL1predecoders are configured to decode an address associated with a grouping of WL1s to select a WL1decoder, such as WL1decoder703-1of rib1ofFIG. 7. The decoder select signal provided from WL1predecoder701-1for example, thus may be used to select WL1decoder703-1, and the WL1decoder select signal received and decoded by WL1decoder703-1to access an associated WL1of the WL1s accessible by WL1decoder703-1. Rib0includes MATs710-0, and rib1includes MATs710-1. Each pair of MATs forms a MAT2, namely a pair of MATs, and between each pair of MATs is a WL1decoder. For example, a MAT2formed of associated MATs710-0A has located between such MATs WL1decoder703-0A. Notably, only eight MATs are illustratively shown for purposes of clarity, though fewer or more MATs may be implemented.

FIG. 8is a schematic/block diagram depicting an exemplary embodiment of memory200having selective restore circuit702-1for rib1. Selective restore circuit702-1includes multiplexers850and851, as well as selective restore register file block801. Selective restore register file block801includes selective restore register file address generator802. Address generator802may be implemented as a counter, and is referred to hereinafter as counter802. Output of counter802is register file address signal824. In this exemplary embodiment, register file address signal824is depicted as a 3-bit signal, though other bit widths may be used as will become apparent. This bit width is a count, such as anywhere from 0 to 7, which corresponds to 0 to 7 registered addresses. Notably, though the example of a maximum of eight addresses may be registered for a rib in a bank of registers803of selective restore register file block801, this number may be fewer or more than 8 depending on implementation. None, some or all of registers803may be used depending on the number of locations in a rib that are to be restored more frequently.

These registers803may be initialized with addresses from fuse bank750ofFIG. 7. For this initialization, provided to selective restore register file block801is load selective restore register files signal (“load SRRF”)812, hereinafter referred to as load signal812. Load signal812is used to load into register bank803addresses associated with identified WL1s having one or more memory cells101that need to be restored more frequently. Thus, at least one selective restore address signal831may be written to registers803responsive to write selective restore signal (“W_SEL_REST[10:0]”)823provided to selective restore register file block801. In the following description, it shall be assumed that this initialization of writing addresses to registers803has been done.

In a non-restore operation for a rib, a read/write address signal821, which is this exemplary embodiment is a 10-bit wide signal, is provided as data input to multiplexer851. Responsive to restore versus normal signal810, which is provided to multiplexer851as a control select input, a normal, i.e. non-restore operation, such as a read or a write of a memory cell, may take place. Thus, output of multiplexer851, which is address signal833, is a WL1address for WL1predecoder701-1for such a read or write operation. In this example, address signal833is a 10-bit wide signal. Selective restore enable signal813is provided to multiplexer850and selective restore register file block801.

For a global restore operation for a rib, selective restore enable signal813is disabled as a control select input to multiplexer850. For those memory cells associated with restore operations502, select restore enable signal813is used to select global restore address signal822for output832from multiplexer850. Global restore address signal822, which is provided as input to multiplexer850, is in this example a 10-bit wide signal. Output of multiplexer850, which is a restore address signal832, is provided as input to multiplexer851as a 10-bit wide signal in this example. For either a global or selective restore operation, restore versus normal signal810provided as a control select to multiplexer851selects output of multiplexer850for output as address signal833from multiplexer851.

Predecoded address signal833is provided to WL1predecoder701-1, which decodes address signal833to provide a WL1address834, which in this exemplary embodiment is a 10-bit wide signal. In this example, rib1is shown having WL1s111ranging from 0 to 2047. In this example, there are 256 WL1s111within each column860. Notably, WL1address signal834is provided to columns860via predecoder lines861, which are coupled to WL1decoders703-1.

For a restore mode which is not a global restore mode but rather is a selective restore mode, selective restore enable signal813is used to select output from register bank803, namely selective restore address signal831, as output of multiplexer850. Register file address signal824is provided to a bank of registers803. Again, in this example, register bank803is eight deep for storing up to eight selective restore addresses, though fewer or more addresses may be stored. In this example, write selective restore signal823is an 11-bit wide signal, where an extra bit is used for disabling a restore operation if that restore address register is not being used. In other words, not all registers in register bank803need be used. Accordingly, no registers in a register bank803need be used if there are no locations in a rib to be selectively restored. Thus, such a rib would have no selective restore operation performed on it.

Register file address signal824in a selective restore mode provides N register file addresses to register bank803. In this example N is equal to 8. For example, counter802counts from 0 to 7. A clock signal811is provided to selective restore circuit702-1, and in particular to selective restore register file block801. Thus, counter802is clocked responsive to clock811. A selective restore enable signal813is provided to restore register file block801, and used as a count enable signal to cause counter802to count through N clock cycles during a selective restore mode, such as restore cycles501ofFIG. 5, and not to count clock cycles during a global restore mode, such as restore cycles502ofFIG. 5. A count value output from counter802is provided to register bank803as register file address signal824, to subsequently output from 0 to 7.

Output of register bank803, in response to register file address signaling824, successively provides each selective restore address signal831registered, which in this exemplary embodiment is a 10-bit wide signal. Selective restore address signal831indicates a WL1address within rib1. Output of register bank803is output from multiplexer850responsive to selective restore enable signal813. Output from multiplexer850is selected for output from multiplexer851responsive to restore versus normal signal810being for a selective restore mode, where normal indicates a global restore mode. Again, both global and selective restore modes may overlap with read or write modes, and combinations thereof.

As the remainder of the description for such a select restore mode is the same as a previously described for global restore mode, it is not repeated here. However, it should be appreciated that a global restore mode is not active during a selective restore mode, and vice-versa, responsive to selective restore enable signal813. Furthermore, it should be appreciated that because, as previously described, restore pulses can be interlineated between read pulses, write pulses, or a combination thereof, read or write operations may occur during both selective restore and global restore modes.

Notably, in the example ofFIG. 8, the number of rows and columns is merely an example, and other array configurations may be used. Accordingly, other bit widths as mentioned above may be employed in accordance with the dimensions of the array, and the number of addresses that may be registered.

FIG. 9is a timing diagram depicting an exemplary embodiment of operation of memory200ofFIG. 2for selective restore modes901and903, and global restore mode902and a portion of global restore mode904. Clock signal811in this example cycles eight times for each selective restore mode901and903and cycles 256 times for each global restore mode, such as global restore mode902. Selective restore enable signal813is active high during each selective restore mode901and903, for selecting output from multiplexer850ofFIG. 8as previously described. During selective restore mode901, for example, global restore address signal822is a “don't care” because it is not selected for output by multiplexer850ofFIG. 8. Selective restore enable signal813is inactive low during global restore modes, including global restore mode902, as previously described with respect to output from multiplexer850ofFIG. 8.

Notably, it should be understood that the same global restore address signal822may be used for one or more ribs at a time, and generally two or more ribs are restored at the same time for both global and selective restore modes. For the example ofFIG. 9, it shall be assumed that more than one rib, such as ribs0and1, is being globally and selectively restored at the same time as indicated by a −0 or −1 respectively as part of the signal reference number, where signals811,813, and822are applied to both of ribs0and1. The remainderFIG. 9is described with additional reference toFIGS. 2,7and8.

Register file address signal824-0in this example outputs counts 0, 1, and 2, such that register bank803of rib0will output via selective restore address signal831three registered file addresses A, B, and C, respectively. Notably, if register bank803is not full of addresses, as in this example for rib0, then some number less than eight addresses, namely these three registered file addresses A, B, and C in this example, are selective restore addresses. A disable bit is set for register file locations3through7in this example. Register file address signal824-1in this example counts from 0 to 7, such that register bank803of rib1will output via selective restore address signal831all eight available registered file addresses D, E, F, G, H, I, J, and K, respectively. There is a one-to-one correspondence for both selective and global restore modes, as applicable depending on which of such modes is active, from signals824-0and824-1to signals831-0and831-1, respectively, and then from signals831-0and831-1to832-0and832-1, respectively.

Each restore pulse is associated with pulsing a particular selective restore address, such as pulse910on WL1address signal834-0for address A of selective restore address signal831-0and restore address signal832-0, and such as pulse911on WL1address signal834-1for address D of selective restore address signal831-1and restore address signal832-1. Thus, for example during selective restore mode901, restore address signal832-0and restore address signal832-1are respectively provided responsive to selective restore address signals831-0and831-1. However, as register file locations3through7are disabled in this example for rib0as indicated by selective restore address signal831-0, there are no associated restore pulses on WL1address signal834-0for those register file locations3through7.

During a selective restore mode901, a read/write address signal821may be asserted. For example, read/write addresses (“RW”)0and RW1of R/W address signal821may result in respective pulses912and913respectively on WL1address signal834-0and834-1. Accordingly, a read or a write operation may take place during selective restore mode901, and such read or write pulses may be located between restore pulses as illustratively shown inFIG. 9.

For global restore mode902, selective restore enable signal813is de-asserted by bringing it to a logic low level in this example, and global restore address signals822are used as the inputs to address832during global restore mode902. As a reminder, the term signal is used herein to refer to individual signals and a plurality of signals, such as a “bus of signals.” In this example,256cycles of clock signal811transpire during global restore mode902. During global restore mode902, signals824-0,824-1,831-0, and831-1are not used.

A counter of periphery circuitry201ofFIG. 2is used to count for each cycle of clock signal811during global restore mode902to incrementally restore wordlines. For example, during global restore mode902wordlines 0 through 255 of a column860are pulsed with restore pulses901on WL1address signals834-0and834-1responsive to a count. Notably, during global restore mode902, restore address signals832-0and832-1are equivalent to global restore address signal822. For each address of restore address signals832-0and832-1there is a respectively corresponding restore pulse respectively on WL1address signals834-0and834-1. Furthermore, for example, operations RW2and RW3of R/W address signal821, may be used to provide respective read or write pulses921and922respectively on WL1address signals834-0and834-1. Such read or write pulses may be between restore pulses as illustratively shown inFIG. 9.

After global restore mode902, another selective restore mode903takes place using the previously described signaling; notably, the same address or addresses provided from selective restore register file block801are repeatedly used for selective restore mode901. However, on a next global restore mode, such as shown in part in respect to global restore mode904, global restore address signal822, as well as restore address signals832-0and832-1, continue counting from where they left off on a prior global restore mode, namely global restore mode902. In the example ofFIG. 8, global restore address signal822would count from 0 to 2047 to count 2048 WL1s, or 2048 WL1addresses, before rolling over and beginning again at 0. Thus, for this example of 2048 WL1s to be pulsed in 256 cycle increments, it will take 8 global restore mode modes to pulse each of the memory cells associated with WL1s111of rib1ofFIG. 8at least one time. However, other WL1s111, as indicated with respect to selective restore address signals831-0and831-1, will be pulsed more frequently, namely 8 times more often in this example.

Notably, for a thyristor-based memory cell, it is possible to do a read and a restore at the same time. However, write operations preclude doing a restore during a write, and thus for reliability reasons, restore pulses are interleaved between read/write pulsing or vice versa.