Method and apparatus for deep sub-micron design of integrated circuits

A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuit (IC) design, and more particularly relates to metal filler patterns for deep sub-micron IC designs.

BACKGROUND OF THE INVENTION

Signal integrity is rapidly becoming one of the important issues in IC designs, especially in very large scale integration (VLSI) physical designs. As the chip size and performance are increasing, the process feature size is reducing. This can result in a higher parasitic induced capacitance on the signal lines which can result in having a very strong impact on the design functionality. Such noise may reduce performance or even introduce logic failures into the IC system.

In IC designs, filler metal polygons (electrically inactive areas) are added to chips in order to maintain an even distribution of metal density across a chip, which reduces the potential for defects on the chip due to uneven chemical-mechanical polishing (CMP) during the chip manufacturing process. Having a certain percentage of coverage for metal has been a general requirement for foundries. Typically, metal density is maintained in the range of about 20% to 80%.

In order to meet the metal coverage requirements, chip designers generally add filler metal polygons on each metal layer in a chip without giving any consideration to coupling capacitance between metal routes and added filler metal polygons. Exemplary metal routes include power routes, clock routes, and signal routes. Typically, the size of the filler metal polygons is about 3 microns×3 microns in size. The added filler metal polygons that violate minimum spacing requirements (between the added filler metal polygon and the metal route) are removed and then checked for metal density requirements. If the metal density requirements are not met, then the above process is repeated until the metal density requirements are met. In general, the above process can become very iterative and time consuming.

In addition, the above technique often leaves the added filler metal polygons too close to the metal routes due to the effort to increase the metal density. This can lead to increased parasitic capacitance, i.e., coupling capacitance between the metal routes and the added filler metal polygons. This in turn, can affect the performance of the chip, such as reducing the frequency of operation of the chip or can affect the functionality of the design. In some instances, the frequency degradation can be as much as 10%. Thus, in the deep sub-micron range, the characteristics of the metal routes (interconnect) and the filler metal polygons can significantly dominate the overall performance of a chip.

SUMMARY OF THE INVENTION

According to an aspect of the present invention there is provided a method for allocating filler metal polygons during manufacturing of integrated circuits (ICs). The method including the steps of computing a size of a filler metal polygon using chip design layout data, identifying one or more regions on the metal layers of the IC design that do not meet metal density requirement, and filling the identified one or more regions with one or more filler metal polygons as a function of the metal density requirement.

According to another aspect of the present invention there is provided a method for overlaying filler metal polygons in metal layers of a chip area of an IC design. The method including the steps of choosing a current rectangular region located at origin (0, 0) on the metal layer, computing a metal density of the current rectangular region, determining whether the computed metal density in the current rectangular region is less than a lowest metal density requirement, computing an amount of metal density that is required to make it equal to the lowest metal density requirement by subtracting the lowest metal density requirement with the computed metal density in the current rectangular region if the computed metal density is the current rectangular region is less than the lowest metal density requirement, filling the current rectangular region with the filler metal polygons by an amount equal to the determined amount of the metal density required to make it equal to the lowest metal density requirement, and choosing a next rectangular region that is at a predetermined distance from the origin (0, 0) in the metal layer and repeating the computing, determining, and filling steps until an entire area of the metal layer is covered.

DETAILED DESCRIPTION OF THE INVENTION

The terms “chip area” and “design area” are used interchangeably throughout the document. Further, the terms “overlaying the filler metal polygons” and “adding the filler metal polygons” are used interchangeably throughout the document. Furthermore, the term “poly” refers to polysilicon.

FIG. 1is a flowchart illustrating an example embodiment of a method100for adding filler metal polygons in metal layers of an IC design in a chip area. At step110, the method100in this example embodiment computes a size of a filler metal polygon using chip design layout data. Exemplary chip design layout data includes width and spacing information of metal, poly, via, diffusion and other layers. Further the exemplary chip design layout data include sizes of transistors represented visually through polygons and the like. In these embodiments, the metal width and spacing information translates into coupling capacitance information, which can include coupling capacitance between the filler metal polygons and various metal routes, such as power routes, clock routes, signal routes, metal-to-substrate, metal-to-metal, metal-to-filler metal polygons and so on. Similarly, the resistance information includes resistance between the filler metal polygons and the metal routes. In these embodiments, the filler metal polygon includes a diffusion layer, a polysilicon layer, at least one metal layer, contacts, vias, and the like. In some embodiments, the size of the filler metal polygon computed includes a computed area of a rectangular filler metal area and/or a polygon filler metal area.

In some embodiments, the filler metal polygons are rectangular in shape. In sub-micron IC designs, the size of the rectangular filler metal polygons is about 3 micrometers×3 micrometers. In some embodiments, the width of the rectangular filler metal polygons is computed as a function of the coupling capacitance information. The length of the rectangular filler metal polygon is calculated as a function of the coupling capacitance information in the chip design layout data, which includes test structure data, received from a chip manufacturer. The selection of the size of the filler metal polygons can directly reflect the metal coverage that can be obtained on the chip area.

Generally, it is desirable to select as large a size as the IC design allows for the filler metal polygons. In addition, the spacing between the filler metal polygons is chosen as small as possible to get a highest possible metal coverage on the chip area. Also, the spacing chosen between a filler metal polygon and a metal route can influence the width and coupling capacitance with the filler metal polygon. Therefore, the width of the filler metal polygon can vary based on the IC design topology. Further, the width of the filler metal polygon depends on an available metal area for overlaying the filler metal polygons in the chip area. The length of the filler metal polygon is an independent factor and it is generally in the range of about 1 micrometer to 3 micrometers. In addition, the length of the filler metal polygons can be tweaked based on the coupling capacitance between the filler metal polygons and the metal routes used in the IC design.

Referring now toFIG. 2, there is illustrated an example portion200in a chip area of an IC design and the inter-layer coupling capacitance picked up between the filler metal polygon and the one or more metal layers. The example portion of the chip area200includes a filler metal polygon210, metal routes220in metal layer1, and metal routes230in metal layer2. As shown inFIG. 2, it can be seen that the filler metal polygon210picks up the coupling capacitance240from the metal routes230in the metal layer2and also from the metal routes220disposed in the metal layer1. It can also be seen that the effect of the coupling capacitance240can be significant as the length of the filler metal polygon increases. Therefore, the length of the filler metal polygon has to be curtailed to reduce the effect of the parasitic capacitance between the filler metal polygons and the metal routes in one or more metal layers in the design area.

In some embodiments, the test structure data is derived from the IC design by drawing various polygon dimensions and spacing and extracting the associated parasitic information.

The number of test cases required can be determined from the following equation:
N=(((X!)/(2!*(X−2)!))+X)*S*W

Wherein “N” is a number of test structure cases for two metal routes in parallel, ‘S’ is a number of spacings, ‘W’ is a number of widths, and ‘X’ is a number of metal layers and applies to when X>2.

The IC design can have reference metal layers above and below (for example, a first metal layer can have poly as bottom reference layer and a second metal layer as top reference layer) which can become an individual test case. The above equation can be modified to include as many reference layers as needed in the IC design.

Referring back toFIG. 1, at step115, one or more regions on the metal layers of the IC design that do not meet a metal density requirement is then identified. In some embodiments, the metal density requirement is based on a metal density requirement of about 20% to 80% of metal in the one or more regions of the metal layers.

In some embodiments, a current rectangular region310located at origin (0, 0)320in metal layers of the chip area300as shown inFIG. 3is chosen: As shown inFIG. 3, the current rectangular region310includes one or more available metal areas330and one or more metal routes340. A metal density of the chosen current rectangular region310is then computed.

At step120, the method100checks to see whether the computed metal density of the current rectangular region meets the metal density requirement of the IC design. Based on the determination at120, the method100goes to step125and identifies the chosen current rectangular region as not meeting the metal density requirement set by a chip manufacturer and considers it for filling with the filler metal polygons if the metal density of the current rectangular region does not meet the metal density requirement and goes to step130. Based on the determination at120, if the computed metal density of the current rectangular region does meet the metal density requirement the method100goes to step130.

At step130, the method100checks to see whether there is another rectangular region in the metal layers that needs computation of the metal density. Based on the determination at130, if there is another rectangular region that needs computation of the metal density the method100goes to step135and repeats steps115-130. In these embodiments, the method100chooses a next rectangular region that is located at a predetermined distance from the origin. In some embodiments, the size of the rectangular region is about 200 micrometers×200 micrometers. In these embodiments, the predetermined distance is about 100 micrometers. Based on the determination at130, if there are no other rectangular regions in the metal layers the method100goes to step140.

At step140, the identified one or more regions are filled with filler metal polygons as a function of the metal density requirement set by the chip manufacturer. In some embodiments, an entire area of the current one of the identified one or more regions are filled with the computed filler metal polygons. At step145, available chip area for filling with the computed filler metal polygons is computed by subtracting the entire area of the current one of the identified one or more regions with associated overlapping metal routes.

In these embodiments, the metal density of the current one of the identified one or more regions that violate the metal density requirement set by the chip manufacturer is computed as follows:
RMD=EMD−CMD

Wherein RMD is a required metal density, EMD is an expected metal density and CMD is a current metal density.

In these embodiments, the following criteria is used to the meet density requirements,

Wherein RMDarea is the area equivalent to the RMD, spc is spacing between metal lines and/or layers, min is closest distance between the filler metal polygons and the metal lines, max is a farthest spacing between the filler metal polygons and the metal lines, and AAspc refers to the available area for a given region.

The sum of available area, across all spacing, is required to be greater than the RMDarea, so that the metal density can be met by adding the computed filler metal polygons. The AAspc used in one spacing cannot be accounted for use in another spacing. A similar approach can be used if the metal density is higher than the allowed limit due to addition of filler metal polygons and removal of the filler metal polygons.

At step150, the computed available chip area for filling the chip area with the filler metal polygons is reduced by a predetermined shrink factor. In some embodiments, the predetermined shrink factor is based on negating the metal routes. In these embodiments, the available chip area is reduced for a fixed spacing between the filler metal polygons that is derived from the test structure data received from the chip manufacturer for the IC design. Generally, the fixed spacing is in the range of about 0.2 micrometer to 2 micrometers for the sub-micron technology. The fixed spacing ensures that the filler metal polygons are located away from the signal metal routes to reduce the coupling capacitance between the metal routes and the filler metal polygons.

At step155, the portion of filler metal polygons that fall outside the reduced computed available chip area are removed, after comparing the reduced available chip are with an area of the current one of the identified one or more regions. At step160, a metal density of the reduced available chip area including remaining filler metal polygons is computed.

At step165, the method100determines whether the computed metal density in the reduced available chip area is less than the metal density requirement set by the chip manufacturer. Based on the determination at step165, if the computed metal density is less than the metal density requirement then the method goes to step150and repeats steps150-165. Based on the determination at step165, if the computed metal density is not less than the metal density requirement, then the method goes to step170.

At step170, the method100determines whether there is another one of the identified one or more regions that needs filling with the filler metal polygons. Based on the determination at step170, if there is another one of the identified one or more regions that needs filling with the filler metal polygons, then the method100goes to step140and repeats steps140-170. Based on the determination at step170, if there is no other one of the identified one or more regions that needs filling with the filler metal polygons, then the method100goes to step175and stops the filling of the filler metal polygon in the chip area of the IC design.

Referring now toFIG. 4, there is shown the filling of the filler metal polygons410in an available chip area of the current rectangular region310. Also, shown is a fixed space420provided between the metal routes340and the added filler metal polygons410.

FIG. 5is a flowchart illustrating another example embodiment of a method500for adding filler metal polygons in metal layers of an IC design. At step510, the method500in this example embodiment chooses a current rectangular region located at origin (0, 0) on a metal layer of a design area of an IC design. At step520, a metal density of the current rectangular region is computed.

At step530, the method500determines whether the computed metal density in the current rectangular region is less than a lowest metal density requirement received from a chip manufacturer for the IC design. Based on the determination at step530, if the computed metal density in the current rectangular region is not less than the lowest metal density requirement (i.e., the computed metal density in the current region is equal to or greater than the lowest metal density requirement), then the method500goes to step560.

At step560, the method500determines whether there is another rectangular region in the design area that needs to be chosen for computing the metal density or whether the entire design area is covered. Based on the determination at step560, if the entire design area is covered, then the method goes to step580and stops. Based on the determination at step560, if the entire design area is not covered, then the method500goes to step570and chooses a next rectangular region located at a predetermined distance from the origin (0, 0) and repeats steps520-560.

Based on the determination at step530, if the computed metal density in the current rectangular region is less than the lowest metal density requirement, then the method500goes to step540and computes an amount of metal density that is required to make the computed metal density in the current rectangular region to be equal to or greater than the metal density requirement by subtracting the lowest metal density requirement with the computed metal density in the current rectangular region. At step550, the current rectangular region is filled with the filler metal polygons by the computed amount of metal density required to make the metal density in the current rectangular region equal to or greater than the lowest of the metal density requirement. After completing the filling of the rectangular region with the filler metal polygons at step550, the method500goes to step560.

In some embodiments, the amount of the metal density requirement to make the computed metal density in the current rectangular region to be equal to or greater than the metal density requirement is as follows:

The available area (AA) in the current rectangular region is filled with the filler metal polygons in the order of a decreasing area. This technique facilitates in filling the current rectangular area with larger filler metal polygons first and then followed by filling with smaller filler metal polygons. Each time the available area is filled with the polygons, the added area is compared against the RMDarea. The filling is stopped when the computed metal density is equal to the lowest of the metal density requirement.

In these embodiments, a filler metal polygon (FMP) area, i.e., the area of a single polygon, is determined by using the equation:
FMParea=APA−PSAwherein APA is an available polygon area and PSA is a polygon space area.

For a given AA, the total filler metal polygon area is computed as below:
FMPtotarea=ΣFMParea in the given AA

To meet the above metal density criteria the following condition has to be met,

wherein spcarea=max to min means FMPtotarea for all AA that is to be added cumulatively in the order of decreasing area.

The above condition is checked for each window. If the metal density criteria is not met with the max spacing, the next available spacing is applied to the available area and the polygons are filled and checked again as described above for metal density criteria. The entire process is automated and can have no impact or very minimal impact on the parasitic capacitance of the signals without affecting the performance of the chip.

Various embodiments of the present invention can be implemented in software, which may be run in the environment shown inFIG. 6, which is described below or in any other suitable computing environment. The embodiments of the present invention are operable in a number of general-purpose or special-purpose computing environments. For example, these may include personal computers, general-purpose computers, server computers, hand-held devices (including, but not limited to, telephones and personal digital assistants (PDAs) of all types), laptop devices, multi-processors, microprocessors, set-top boxes, programmable consumer electronics, network computers, minicomputers, mainframe computers, distributed computing environments and the like to execute code stored on a computer-readable medium. Furthermore, embodiments of the present invention may be implemented in part or in whole as machine-executable instructions, such as program modules that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, and the like to perform particular tasks or to implement particular abstract data types. In a distributed computing environment, program modules may be located in local or remote storage devices.

FIG. 6shows an example of a suitable computing system environment for implementing embodiments of the present invention.FIG. 6and the following discussion are intended to provide a brief, general description of a suitable computing environment in which certain embodiments of the inventive concepts contained herein may be implemented.

A general computing device, in the form of a computer610, may include a processing unit602, memory604, removable storage601, and non-removable storage614. Computer610additionally includes a bus605and a network interface (NI)612.

Computer610may include or have access to a computing environment that includes one or more user input modules616, one or more output modules618, and one or more communication connections620such as a network interface card or a USB connection. The one or more output modules618can be a display device of a computer, computer monitor, TV screen, plasma display, LCD display, display on a digitizer, display on an electronic tablet, and the like. The computer610may operate in a networked environment using the communication connection620to connect to one or more remote computers. A remote computer may include a personal computer, server, router, network PC, a peer device or other network node, and/or the like. The communication connection may include a Local Area Network (LAN), a Wide Area Network (WAN), and/or other networks.

The memory604may include volatile memory606and non-volatile memory608. A variety of computer-readable media may be stored in and accessed from the memory elements of computer610, such as volatile memory606and non-volatile memory608, removable storage601and non-removable storage614. Computer memory elements can include any suitable memory device(s) for storing data and machine-readable instructions, such as read only memory (ROM), random access memory (RAM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), hard drive, removable media drive for handling compact disks (CDs), digital video disks (DVDs), diskettes, magnetic tape cartridges, memory cards, Memory Sticks™, and the like; chemical storage; biological storage; and other types of data storage.

“Processor” or “processing unit,” as used herein, means any type of computational circuit, such as, but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, explicitly parallel instruction computing (EPIC) microprocessor, a graphics processor, a digital signal processor, or any other type of processor or processing circuit. The term also includes embedded controllers, such as generic or programmable logic devices or arrays, application specific ICs, single-chip computers, smart cards, and the like.

Embodiments of the present invention may be implemented in conjunction with program modules, including functions, procedures, data structures, application programs, etc., for performing tasks, or defining abstract data types or low-level hardware contexts.

Machine-readable instructions stored on any of the above-mentioned storage media are executable by the processing unit602of the computer610. For example, a program module625may include machine-readable instructions capable of adding filler metal polygons on a chip area according to the teachings and herein described embodiments of the present invention. In one embodiment, the program module625may be included on a CD-ROM and loaded from the CD-ROM to a hard drive in non-volatile memory608. The machine-readable instructions cause the computer610to encode according to the various embodiments of the present invention. As shown, the program module625includes instructions to overlay filler metal polygons on metal layers of a design area in an IC design according to various embodiments of the present invention.

The operation of the computer system600for adding the filler metal polygons on the chip area is explained in more detail with reference toFIGS. 1 and 5.

The above-described methods and apparatus provide various techniques to overlay filler metal polygons on a chip area during an IC design. The above process significantly reduces parasitic capacitance induced as a result of adding the filler metal polygons while satisfying the metal density constraints imposed by the chip manufacturer. In addition, the above process achieves the improved addition of filler metal polygons on the chip area by keeping the size of the filler metal polygon as large as possible and reducing the spacing between the filler metal polygons as small as possible. The above process achieves an improved scheme for overlaying the filler metal polygons in a chip area by negating the metal routes from the metal area and shrinking the available metal area by a predetermined shrink factor to reduce coupling capacitance with the metal routes.

As shown herein, the present invention can be implemented in a number of different embodiments, including various methods, an apparatus, and a system. Other embodiments will be readily apparent to those of ordinary skill in the art. The elements, algorithms, and sequence of operations can all be varied to suit particular requirements. The operations described above with respect to the method illustrated inFIGS. 1 and 5can be performed in a different order from those shown and described herein.

FIGS. 1-6are merely representational and are not drawn to scale. Certain proportions thereof may be exaggerated, while others may be minimized.FIGS. 1-6illustrate various embodiments of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.

The above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those skilled in the art. The scope of the invention should therefore be determined by the appended claims, along with the full scope of equivalents to which such claims are entitled.