Digital-to-analog converter with programmable current control

A wide gain range current digital-to-analog converter (DAC) is presented that includes a unit current cell having a current source module biased by a current source voltage bias, a differential switch module, a main cascode module biased by a first bias voltage and an attenuation cascode module biased by a second bias voltage, configured such that a particular current gain range is obtained at the main cascode module output when a unit current cell current is at or above a current threshold. The output current at the attenuation cascode module output can be input into a current attenuator when the unit current cell current is below the current threshold to obtain additional current gain range. The current attenuator can include a plurality of attenuator cells that can be programmed to a desired level of current gain in linear decibels or linear step intervals. Smaller step sizes can be obtained by programming a current source within the step intervals.

BACKGROUND

The present invention is related to current digital-to-analog converters (DACs) with programmable output current for use in communication systems.

2. Related Art

Communication systems typically include a current digital-to-analog converter (DAC). In order to adjust system characteristics to channel variations, a programmable output current is normally required. One approach to implement a programmable output current is to vary a bias current entering the DAC.FIG. 1illustrates a common DAC bias that outputs a current source bias voltage114to one or more DAC unit current cells, such as unit current cell200shown inFIG. 2. When a DAC bias current103is changed, a total output current can change proportionately.

An important performance parameter of the DAC is its linearity. Linearity is a function of the matching of the current source transistors (such as transistor220ofFIG. 2) in the unit current cells. The matching depends on the size (e.g., width by length) of the current source transistors, as well as the biasing condition (e.g., Vgs-Vt). When DAC bias current103is reduced, the bias condition (e.g., Vgs-Vt) of the current source transistors is reduced. This results in a deteriorated current matching of the unit current cells. Thus, the maximum range in which DAC bias current103can be varied is limited. In a typical configuration, DAC bias current103cannot be varied more than 20–30 decibels (dB) before current source matching can dominate the overall performance of the DAC. This range is insufficient for many communication systems.

Therefore, what is needed is a current DAC with programmable current control such that a DAC current control range is extended.

SUMMARY

A wide gain range current digital-to-analog converter (DAC) is presented. An embodiment includes a differential DAC circuit including a unit current cell having a current source module, a differential switch module, a main cascode module and an attenuation cascode module. The current source module, differential switch module, main cascode module, and attenuation cascode module can be formed from transistors. The current source module is coupled to a current source voltage bias and a ground and provides a unit current cell current that mirrors a current source bias current. The differential switch module is coupled to the current source module. The main cascode module is coupled to the differential switch module and is biased by a first bias voltage. The attenuation cascode module is coupled to the differential switch module and is biased by a second bias voltage. The configuration of the current source module, differential switch module, main cascode module, attenuation cascode module, and bias voltages is such that a particular current gain range is obtained at the main cascode module output. When the unit current cell current is at or above a current threshold, the unit current cell current is routed to a main cascode output to obtain an initial current gain range. When the unit current cell current is below a current threshold, the unit current cell current is routed to an attenuation cascode output and through a current attenuator to obtain additional current gain range. The current attenuator can include a plurality of attenuator cells or groups of attenuator cells that can be programmed to a desired level of current gain in linear decibels or linear step intervals. Smaller step sizes can be obtained by programming a current source within the step intervals.

The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

Overview

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art(s) will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present invention. It will be apparent to a person skilled in the pertinent art(s) that this invention can also be employed in a variety of other applications.

Embodiments of the present invention provide a current DAC with programmable current control such that a maximum range in which a DAC bias current can be varied is increased. This can be accomplished by modifying one or more output cascode transistors of a conventional current DAC and also by including a current attenuator that can be switched into a signal path, or bypassed, depending on a required output current. The current attenuator can be used in conjunction with a variable DAC bias current in order to provide a smaller step size throughout the entire current control range.

Introduction

As stated earlier in the Background section, communication systems, e.g., an upstream burst transmitter in a cable modem, commonly include a current digital-to-analog converter (DAC). A programmable output current is normally required in order to adjust system characteristics to channel variations, for example. One approach to implement a programmable output current can be to vary a bias current entering the DAC.FIG. 1illustrates a common DAC bias circuit100that outputs a current source bias voltage114. DAC bias circuit100includes a transistor104and a current source102that supplies DAC bias current103. Transistor104has a source110coupled to a ground112, a drain106coupled to an output of current source102, and a gate108coupled to drain106. Current source bias voltage114is located at gate108. Note that although NMOS transistors are shown throughout the figures, other types of transistors can also be used (e.g., PMOS, bipolar, etc.), as would be understood by those skilled in the relevant art(s), without detracting from the scope of the invention.

A current DAC includes an array of unit current cells (e.g., an array of 256 unit current cells). A current DAC can include an array of unit current cells when it is fully segmented, and fractions of these unit current cells for any binary weighted elements. For simplicity of description, a single unit current cell200is shown inFIG. 2. Unit current cell200includes a current source transistor220, a switch pair consisting of switch transistors228and250, and a cascode pair consisting of cascode transistors238and258. Unit current cell200is shown as a differential circuit. However, a single-ended unit current cell can also be used as would be understood by those skilled in the relevant art(s).

Current source transistor220includes a source222coupled to ground112, a gate224coupled to gate108of transistor104(of DAC bias circuit100shown inFIG. 1), and a drain226coupled to a source230of switch transistor228and a source252of switch transistor250. Switch transistor228has a gate232coupled to a switch signal236aand a drain234coupled to a source240of cascode transistor238. Switch transistor250has a gate254coupled to a switch signal236band a drain256coupled to a source260of cascode transistor258. Cascode transistor238has a gate242coupled to a bias voltage246and a drain244providing output current248at an output247. Cascode transistor258has a gate262coupled to bias voltage246and a drain264providing output current266at an output265. Current source transistor220and switch transistors228and250can be thin oxide transistors, and cascode transistors238and258can be thick oxide transistors. The outputs247/265providing output currents248/266terminate into a high voltage (approximately 2.5 volts or higher) with a signal swing. Therefore, thick oxide cascode transistors238/258can protect thin oxide transistors220/228/250. Alternatively, transistors220,228,250,238and258can all be thin oxide transistors or can all be thick oxide transistors.

Current transistor220can be biased by DAC bias circuit100such that the reference current (DAC bias current103) is mirrored through current transistor220. The unit current through current transistor220will be approximately the same as DAC bias current103if current transistor220and transistor104are scaled one-to-one.

The unit current through current transistor220can be routed through switch transistor228or250, depending on the state of switch signals236aand236b, and therefore can run through either cascode transistor238or258(one or the other). The cascode transistors238/258allow for a high output impedance for the DAC and protect switch transistors228/250and current source transistor220from the high voltage swing at the outputs providing output currents248/266. The outputs247/265providing output currents248/266are parallel with those of other unit current cells, and they all terminate into a transformer and a resistive load at approximately 2.5 volts or higher.

As stated in the Background section, an important performance parameter of the DAC is its linearity. Linearity is a function of the matching of the current source transistors (such as transistor220ofFIG. 2) in the unit current cells. The matching depends on the size (e.g., width by length) of the current source transistors, as well as the biasing condition (e.g., Vgs-Vt). When DAC bias current103is reduced, the bias condition (e.g., Vgs-Vt) of the current source transistors is reduced. This results in a deteriorated current matching of the unit current cells. Thus, the maximum range in which DAC bias current103can be varied is limited. In a typical configuration, DAC bias current103cannot be varied more than 20–30 dB before current source matching can dominate the overall performance of the DAC. This range is insufficient for many communication systems.

In an example embodiment, there can be sixty-four (64) unit current cells represented by six (6) bits, and another four (4) bits that can be weighted differently, for a total of ten (10) bits of resolution in the DAC. When programmable DAC bias current103is changed through transistor104, the current through current source transistor220(and therefore the total output current248/266) can change proportionately. This can be done for a range of up to approximately 30 dB. A dynamic range higher than that cannot be obtained because when the DAC bias current103is decreased to a very low level, the output impedance and matching of the current mirror (between transistor104and current source transistor220) can deteriorate. The matching of the current mirror (transistors104/220), and the matching of a unit current cell compared to another unit current cell, is a function of the current. Thus, the more current, the better the matching. However, headroom is also limited in that the programmable DAC bias current103cannot be increased too high or problems with saturation of the transistor devices can arise. Therefore, there is an upper bound set by the available headroom, and a lower bound set by the matching of the current sources (through transistor104and current source transistor220).

Extension of Current Control Range

In order to extend a DAC current control range, unit current cells of a conventional current DAC architecture can be modified and, additionally, current attenuators can be used that can be switched into a signal path, or bypassed, depending on the required output current. For example, a range of 30 dB can be obtained in the conventional manner described above, and an extended amount (e.g., another 30 dB) can be obtained from splitting a DAC output current according to embodiments to now be described.

FIG. 3is a block diagram of a unit current cell of a current DAC, according to an embodiment of the present invention. Unit current cell300includes current source module315coupled to current source bias voltage114and ground112. Current source module315provides a unit current cell current that mirrors a current source bias current that can be provided by a DAC bias such as DAC bias100shown inFIG. 1. Unit current cell300also includes a differential switch module316coupled to current source module315for differential switching, if differential circuitry is implemented. Unit current cell300further includes a main cascode module317coupled to differential switch module316and a bias voltage246, and an attenuation cascode module318coupled to differential switch module316and a bias voltage380. When the unit current cell current is at or above a current threshold, the unit current cell current is routed to main cascode module317and to main cascode output347. This results in an initial current gain range. When the unit current cell current is below the current threshold, the unit current cell current is routed to attenuation cascode module318, to attenuation cascode output305, and through a current attenuator (not shown). This results in additional current gain range.

An embodiment of the present invention includes a current DAC consisting of an array of unit current cells, such as unit current cell300ofFIG. 3.FIG. 4depicts an example embodiment of unit current cell300in more detail. Unit current cell400includes current transistor220with current source bias voltage114as an input, and switch transistors228/250with switch signals236a/236bas an input, as described above. Cascode transistor238ofFIG. 2, however, can be modified into cascode transistors470and476. Cascode transistor470has a source472coupled to drain234of switch transistor228, a gate473coupled to bias voltage246, and a drain474providing an output current475pat an output347p. Cascode transistor476has a source477coupled to drain234of switch transistor228, a gate478coupled to bias voltage380, and a drain479providing an output current481pat an output305p. Similarly, cascode transistor258ofFIG. 2can be modified into cascode transistors482and486. Cascode transistor482has a source483coupled to drain256of switch transistor250, a gate484coupled to bias voltage246, and a drain485providing an output current475nat an output347n. Cascode transistor486has a source487coupled to drain256of switch transistor250, a gate488coupled to bias voltage380, and a drain489providing an output current481nat an output305n. Outputs305p/305ncan be coupled to an attenuator (described further below). In one embodiment, cascode transistors470,482,476, and486can be thick oxide transistors. In another embodiment, transistors470,482,476, and486can be thin oxide transistors.

Cascode transistors470and476are of differing sizes (i.e., widths), the total combined size being substantially the same as the size (width) of cascode transistor238(ofFIG. 2). Similarly, cascode transistors482and486are of differing sizes, the total combined size being substantially the same as the size (width) of cascode transistor258(ofFIG. 2). For example, cascode transistors470/482can each be sized at 80% of the width of cascode transistors238/258, and cascode transistors476/486can then each be sized at 20% of the width of cascode transistors238/258. The size differences are not to be limited to this percentage breakdown, and can be any breakdown as long as the total areas used by cascode transistors470and476, and by cascode transistors482and486, are substantially the same as the areas used by cascode transistors238and258(ofFIG. 2), respectively. Additionally, the cascode transistors (in this case, cascode transistors476/486) that are biased by bias voltage380should be of a smaller size than the cascode transistors (in this case, cascode transistors470/482) that are not biased by bias voltage380. The size breakdown chosen depends on the range of current that is to be accommodated.

Cascode transistors470and476, for example, can be thought of as a single transistor, but with a portion of that single transistor (represented by cascode transistor476) biased by bias voltage380instead of bias voltage246. Similarly, cascode transistors482and486can be thought of as a single transistor, but with a portion of that single transistor (represented by cascode transistor486) biased by bias voltage380instead of bias voltage246. At any given time, only one of bias voltage246and bias voltage380is biased to the desired operating condition. In other words, one of the bias voltages246/380is pulled to a low voltage (e.g. zero volts), and the other is biased to the desired voltage (e.g., 2 volts). Thus, an output current is switched through either output347p/347nor output305p/305n. The sizing of cascode transistors470/476and482/486is such that when DAC bias current103is a high current running through current source transistor220, bias voltage380is disabled, bias voltage246is enabled, and output347p/347nis used to provide output current475p/475nthrough the larger cascode transistors470/482. In the alternative, when DAC bias current103is a low current running through current source transistor220, bias voltage246is disabled and bias voltage380is enabled, routing the smaller current through cascode transistors476/486and providing output current481p/481nthrough output305p/305n. In other words, when DAC bias current103is low (i.e., the circuit path is at a high impedance), the current is routed through cascode transistors476/486instead of cascode transistors470/482.

As described above, only one of outputs347p/347nand305p/305nis intended to be active at any given time. This is achieved by switching bias voltage246and bias voltage380between two defined voltages, Vhighand Vlow. Vhighshould be defined such that a proper DC biasing of unit current cell switch transistors228/250is obtained. Vlowshould be defined such that the corresponding cascode transistor is in an ‘off’ state whenever Vlowis applied. For example, Vlowcan be defined as zero volts, and Vhighcan be defined as a typical power supply voltage sufficient to turn on transistors470/482. The voltages used to define Vlowand Vhighare not to be limited to these voltages. The values of Vlowand Vhighare arbitrary, depending on the implementation.

Usually when there is a high output current (high DAC bias current103), headroom issues might arise due to a large signal swing in the output. In this situation, anything that is in the signal path will contribute to distortion. By using this modified unit current cell, the current is routed through either output347p/347nor output305p/305n. There is nothing in the signal path added when in a high current mode, and the total amount of current continues straight to output347p/347n. When in low current mode, headroom is not an issue because the signal swing will be small.

A main purpose of this invention is to extend the current control range below a level that can be achieved by reducing bias current103. When DAC bias current103is set to its maximum level, cascode transistors470/482are made active. When DAC bias current103is reduced to a minimum acceptable level for device matching, cascode transistors476/486are made active. Further reduction in DAC output current is accomplished by splitting the output current481p/481nin an attenuator, which will now be discussed. Fine control of DAC bias current103will also be discussed.

FIG. 5illustrates the implementation of a current attenuator521within an output signal path of the DAC. The output signal paths are those output from unit current cells as described above with reference toFIG. 4. InFIG. 5, if DAC bias current103is a high current, and switch signals236a/236band bias voltages246and380are biased such that output347p/347ncarries the unit current cell output current, then current attenuator521would be bypassed. In this case, if output347p/347ncarries the unit current cell output current, then a system output current525p/525nis equal to output current475p/475n. In other words, for higher output current levels, the output currents of the DAC are directly routed to the output of the system. In this state, current attenuator521represents a high impedance output (‘tri-state’) and will not have a significant impact on the large signal performance of the DAC.

If, instead, DAC bias current103is a low current, and switch signals236a/236band bias voltages246and380are biased such that output305p/305ncarries the unit current cell output current, then that unit current cell output current signal would be received by current attenuator521. In this case, if output305p/305ncarries the unit current cell output current, then the system output current525p/525nis equal to output current481p/481nas altered by current attenuator521. In other words, for lower output current levels, the output current of the system is provided through the current attenuator.

Current attenuator521can be programmable through a control signal523. For example, control signal523can be implemented as a 5-bit control signal and represent a 30 dB current gain range, as described in more detail below. Control signal523is not to be limited to this, however. Other control signal lengths and gain ranges can be implemented without straying from the scope of the invention.

One purpose of using current attenuator521is to obtain lower and lower current values. The bias current can be lowered for a first gain range (e.g., 30 dB) while using a main signal path. Once the bias current is at a lowest acceptable level, the current signal path is switched to an attenuator signal path for further current reduction (e.g., another 30 dB of range). The smaller devices in the attenuator signal path carry less current output relative to the larger devices in the main signal path.

In an embodiment, current attenuator521can include a plurality of attenuator cells, such as attenuator cells637shown in current attenuator621inFIG. 6.FIG. 6depicts current attenuator621as a single-ended implementation for simplicity of description, however another similar circuit can be used for complementary input/output signals. Current attenuator621can be organized as a plurality of attenuator subgroups641,643,645,647,649, and651situated as a cascading array639. In the particular embodiment shown, attenuator subgroups641and643each include one attenuator cell637, attenuator subgroup645includes two attenuator cells637, attenuator subgroup647includes four attenuator cells637, attenuator subgroup649includes eight attenuator cells637, and attenuator subgroup651includes sixteen attenuator cells637. This grouping represents a binary weighting of system output current625as a function of control signal623.

Each attenuator cell637of current attenuator621receives as an input, input current681, bias voltage Von631, bias voltage Voff633, and a control signal bit ‘A’. Designated bits of control signal623each control a corresponding attenuator subgroup. For the embodiment of current attenuator621shown inFIG. 6, control signal623is a 5-bit control signal, for example. Thus, each bit of 5-bit control signal623controls a corresponding attenuator subgroup for a total of −30 dB current gain in −6 dB attenuation steps. It will be understood by those skilled in the relevant art(s) that any grouping and number of attenuator cells fits within the scope of the invention. Similarly, as stated earlier, other control signal lengths and gain ranges can be implemented.

In the example embodiment inFIG. 6, when control signal623is ‘00000’, all attenuator cells route an input current681from a unit current cell (e.g., current481p/481nof unit current cell400ofFIG. 4) at input605to system output653as system output current625. This results in an attenuation of 0 dB. Attenuator subgroup641, which includes one attenuator cell, is not associated with control signal623and remains on to prevent the creation of a high impedance point that would occur if all of the attenuator cells were turned off.

If control signal623is changed to ‘10000’, then the attenuator cells associated with attenuator subgroup651route 16/32 (or 50%) of input current681to dump output655as unneeded dump current635, which is routed to a power supply (e.g., a 2.5V power supply) (not shown). This results in the other 50% of input current681being output as system output current625, and represents a −6 dB current gain (6 dB attenuation). The attenuation of current can be further increased by setting control signal623to ‘11000’. In this state, attenuator subgroups651and649route a total of 24/32 (or 75%) of input current681to dump output655as dump current635. This results in the other 25% of input current681being output as system output current625, and represents a −12 dB current gain. Similarly, current gains of −18 dB, −24 dB, and −30 dB can be selected by setting control signal623to ‘11100’, ‘11110’, and ‘11111’, respectively.

At any given time, only one of attenuator cell transistors757and759is active. When control signal bit723is low (e.g., ‘0’), attenuator cell transistor759is active, and input current681is routed to system output653. Alternatively, when control signal bit723is high (e.g., ‘1’), attenuator cell transistor757is active, and input current681is routed to dump output655. Bias voltage Von631should be chosen such that bias conditions of all devices in the attenuator cell, as well as the DAC unit current cells, are sufficient to keep the devices in saturation (e.g., Von=2.5V). Bias voltage Voff633should be low enough to ensure that its respective attenuator cell transistor757/759does not conduct any current when coupled to bias voltage Voff633(e.g., Voff=ground).

By controlling the input control signals723to each of attenuator cells737of a current attenuator621, for example, each attenuator cell737can route the input current681to either system output653or dump output655. The embodiment shown and described in reference toFIG. 6uses thirty-two attenuator cells. (However, this number can be higher or lower depending on the requirements of the attenuator.) When all of input current681is flowing through attenuator cell transistor759in each of the thirty-two attenuator cells, all of input current681passes to system output653. If it is desired to have, for example, a 50% reduction of system output current625, then in sixteen of the thirty-two attenuator cells, input current681is routed through transistor757and dumped at dump output655. The other sixteen attenuator cells route input current681through attenuator cell transistor759to system output653. This effectively results in a 50% split in the output current, which, in this embodiment, provides −6 dB in attenuation. Because bias voltages Von631, Voff633, and the bias voltages at input605, system output653, and dump output655are respectively equal across all thirty-two attenuator cells, input current681is split evenly among all thirty-two attenuator cells.

It would be apparent to one skilled in the relevant art(s) that a gain control mechanism can be implemented in various ways without detracting from the scope of this invention. For example, the above-described implementation of current attenuator621represents a binary weighted implementation of gain control, resulting in −6 dB attenuation steps. However, current attenuator621is not limited to binary weighting of attenuator cells. In alternative embodiments, a current attenuator may be implemented using any number of attenuator cells and any grouping of attenuator cells. For example, instead of using thirty-two attenuator cells, a higher or lower number of attenuator cells can be used depending on the desired attenuation requirements. As another example of an alternative embodiment, the current attenuator can be implemented in a linear manner by switching one attenuator cell out at a time rather than by binary weighting. In this case, the attenuation would be linear, but the step size in decibels would not be linear. In yet another embodiment, current gain control, in particular the fine current gain control discussed below, does not need to be controlled via incremental steps. For example, it can be implemented using analog control.

As shown by the above description, the combination of changing bias currents in the DAC, bypassing an attenuator in a high-current mode, and routing current through an attenuator in low-current mode, can provide an additional current gain (e.g., −30 dB) in incremental steps (e.g., −6 dB steps). Smaller steps are also attainable, as will now be discussed.

A current splitting attenuator, such as current attenuator621, can provide incremental attenuation steps (e.g., 6 dB steps) in a low end of a gain control range. The current attenuator can be used in conjunction with a variable (or programmable) DAC bias current in order to provide an even smaller step size (e.g., 0.5 dB) throughout the entire current control range.FIG. 8is a graph showing coarse/fine current gain control, according to an embodiment of the present invention.

FIG. 8provides an example of 60 dB gain control in 0.5 dB steps. A fine step control is implemented by changing the DAC bias current (e.g., DAC bias current103) in 0.5 dB steps. This example shows 64 fine settings895. The maximum output current is defined as 0 dBFS and requires a fine control value of ‘63’. The range897from 0 dBFS down to −30 dBFS is realized by changing the DAC bias current fine control down to a value of ‘3’ with the coarse control (based on control signal623, for example) at 0 dB current gain (or ‘00000’). The next step down is found by increasing the DAC bias current fine control to ‘14’ with the coarse control at a current gain level of −6 dB (or ‘10000’), as described above with reference toFIG. 6. Throughout the remaining coarse attenuator step intervals (e.g., ‘11000’, ‘11100’, ‘11110’, and ‘11111’) also described above with reference toFIG. 6, the DAC bias current fine control is moved between ‘3’ and ‘14’ as a saw tooth shaped control signal. This combination of coarse and fine control realizes a constant gain step in the full 60 dB range.

A method900of controlling current gain according to the above-described embodiments is shown inFIG. 9. Method900starts at step902and immediately proceeds to step904. In step904, at least one unit current cell is biased with a current source bias voltage (such as current source bias voltage114) and current source bias current (such as DAC bias current103) such that a unit current cell current is mirrored with the current source bias current. In step906, it is determined whether the unit current cell current is at or above a current threshold. If the unit current cell current is at or above the current threshold, the method proceeds to step908where the unit current is routed to a first current output (such as output347p/347n) to obtain an initial current gain range. If the unit current cell current is below the current threshold, the method proceeds to step910where the unit current cell current is routed to a second current output (such as output305p/305n) and through a current attenuator (such as current attenuator621) to obtain an additional current gain range. Method900terminates at step912.

Step910can include attenuating the unit current cell current to a desired current gain level. In various embodiments, this can be done in incremental steps by switching attenuator cells (such as shown inFIGS. 6 and 7) on or off, for example. In one embodiment, attenuator cells can be switched on or off individually to provide a linear attenuation (i.e., a linear reduction in current flow). In another embodiment, binary weighted subgroups of attenuator cells can be switched on or off to provide coarse linear incremental current gain steps (in decibels). In a further embodiment, the current source bias current can be changed in small incremental steps within the desired current gain level (e.g., coarse step) to provide current gain control by fine incremental current gain steps that are smaller in size than the coarse steps.

The current attenuator can be programmed for the desired current gain level. This can be done by providing a control signal, for example (such as control signal623), although other methods of programming a current attenuator would be understood by those skilled in the relevant art(s). In an embodiment, each bit of control signal623can be used to control a specific attenuator cell or a specific group of attenuator cells (such as the binary weighted subgroups of attenuator cells as discussed above with reference toFIG. 6). As would be apparent to one skilled in the relevant art(s), control signal bit sequences (or any signal used as an on/off signal) can use ‘1’ s to enable and ‘0’ s to disable, or they can use ‘0’ s to enable and ‘1’ s to disable attenuator cells or groups of attenuator cells, depending on the chosen implementation of the circuit.

The current DAC embodiments described above provide a number of advantages. For example, they provide a wide range of current control with virtually no need for additional programmable current or voltage amplifiers or attenuators located after the current DAC. A related advantage is that a smaller chip area can be used for the current DAC. Power efficiency is also optimized such that when an output current is high, there is little to no current wasted.