GOA circuit

A GOA circuit comprises m cascaded GOA units, wherein a GOA unit comprises forward-reverse scan control module, first gate signal output module and second gate signal output module. The forward-reverse scan control module controls the GOA circuit to perform forward scanning or reverse scanning. The first gate signal output module comprises seventh TFT, ninth TFT and sixteenth TFT; a second terminal of the sixteenth TFT receives a high potential signal, and a first and a third terminal of the sixteenth TFT are connected to the first and second terminals of the seventh TFT, respectively. The second gate signal output module comprises twelfth TFT, thirteenth TFT and fifteenth TFT; a second terminal of the fifteenth TFT receives the high potential signal, and a first and a third terminal of the fifteenth TFT are connected to the first and second terminals of the twelfth TFT, respectively.

RELATED APPLICATIONS

The present application is a National Phase of International Application Number PCT/CN2017/113108, filed on Nov. 27, 2017, and claims the priority of China Application No. 201711147136.5, filed on Nov. 17, 2017.

FIELD OF THE DISCLOSURE

The disclosure relates to a display technical field, and more particularly to a GOA circuit.

BACKGROUND

As shown inFIG. 1andFIG. 2, in a normal cascaded (1 to 2) GOA (Gate Driver On Array, a technique using the existed process of manufacturing thin film transistor liquid crystal display array to manufacture a gate line scan driving signal circuit on an array substrate to realize a driving method scanning each gate line in sequence), waveforms of the node Q shown inFIG. 1while being interfered by signals are shown inFIG. 2.

The potentials of the nodes Qa and Qb are leaked to the node Q through the thin film transistor (TFT) NT7and the TFT NT12in the boost period, so that the boost potentials of the nodes Qa and Qb are decreased because the latency of the high potential signal VGH and the interfered potential of the node Q are not matched and the voltage between the gate and the source, either in the TFT NT7or the TFT NT12, is therefore greater than 0 volt (Vgs>0V) and resulting in the decrease of the boost potentials of the nodes Qa and Qb. As shown inFIG. 2, after the boost potentials of the nodes Qa and Qb are decreased, the potentials of the gates of the TFT NT9and TFT NT13are decreased, the output waveforms of the gate signals G(n) and G(n+2) become abnormal, and risk of failure of GOA cascaded transmission appears.

SUMMARY

In order to solve the technique problems mentioned above, the present invention provides a GOA circuit to decrease the risk of failure of GOA cascaded transmission.

The present invention provides a GOA circuit, which is used in a liquid crystal display panel, comprising m cascaded GOA units, wherein a nth-stage GOA unit comprises: a forward-reverse scan control module, a first gate signal output module and a second gate signal output module, wherein m≥n≥1;the forward-reverse scan control module is used for controlling the GOA circuit to perform a forward scanning or a reverse scanning in accordance with a forward scan control signal or a reverse scan control signal;the first gate signal output module comprises: a seventh thin film transistor (TFT), a ninth TFT and a sixteenth TFT; a third terminal of the seventh TFT receives a high potential signal, a first terminal of the seventh TFT is connected to an output terminal of the forward-reverse scan control module, and a second terminal of the seventh TFT is connected to a third terminal of the ninth TFT; a first terminal of the ninth TFT receives a nthclock signal, and a second terminal of the ninth TFT is for outputting a nthgate driving signal; a second terminal of the sixteenth TFT receives the high potential signal, a first terminal of the sixteenth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the sixteenth TFT is connected to the second terminal of the seventh TFT;the second gate signal output module comprises: a twelfth TFT, a thirteenth TFT and a fifteenth TFT; a third terminal of the twelfth TFT receives the high potential signal, a first terminal of the twelfth TFT is connected to the output terminal of the forward-reverse scan control module, and a second terminal of the twelfth TFT is connected to a third terminal of the thirteenth TFT; a first terminal of the thirteenth TFT receives a (n+2)thclock signal, and a second terminal of the thirteenth TFT is for outputting a (n+2)thgate driving signal; a second terminal of the fifteenth TFT receives the high potential signal, a first terminal of the fifteenth TFT is connected to the first terminal of the twelfth TFT, and a third terminal of the fifteenth TFT is connected to the second terminal of the twelfth TFT;wherein, the first terminal is one of source and drain, the second terminal is another one of source and drain, and the third terminal is gate.

Preferably, the forward-reverse scan control module comprises a first TFT and a second TFT;a first terminal of the first TFT receives the forward scan control signal, a first terminal of the second TFT receives the reverse scan control signal, a second terminal of the first TFT is connected to a second terminal of the second TFT and the first terminal of the seventh TFT, a third terminal of the first TFT receives a (n−2)thgate driving signal, and a third terminal of the second TFT receives a (n+4)thgate driving signal.

Preferably, the GOA unit further comprises a third TFT, a fourth TFT, an eighth TFT, a tenth TFT and a fourteenth TFT;a first terminal of the third TFT receives a (n+1)thclock signal, and a first terminal of the fourth TFT receives a (n−1)thclock signal;a second terminal of the third TFT is connected to a second terminal of the fourth TFT and a third terminal of the eighth TFT;a third terminal of the third TFT receives the forward scan control signal, and a third terminal of the fourth TFT receives the reverse scan control signal;a first terminal of the eighth TFT receives the high potential signal, and a second terminal of the eighth TFT is connected to a third terminal of the tenth TFT and a third terminal of the fourteenth TFT;a first terminal of the tenth TFT is connected to the second terminal of the ninth TFT, a first terminal of the fourteenth TFT is connected to the second terminal of the thirteenth TFT, and a second terminal of the tenth TFT and a second terminal of the fourteenth TFT both receive a low potential signal.

Preferably, the GOA unit further comprises an eleventh TFT, a second terminal of the eleventh TFT is connected to a third terminal of the eleventh TFT and receives a reset signal, and a first terminal of the eleventh TFT is connected to the third terminals of the tenth TFT and the fourteenth TFT.

Preferably, the GOA unit further comprises a sixth TFT, a third terminal of the sixth TFT is connected to the second terminal of the second TFT, a first terminal of the sixth TFT is connected to the third terminals of the tenth TFT and the fourteenth TFT, and a second terminal of the sixth TFT receives the low potential signal.

Preferably, the GOA unit further comprises a first capacitor and a second capacitor;a first terminal of the first capacitor is connected to the first terminal of the seventh TFT, and a second terminal of the first capacitor receives the low potential signal;a first terminal of the second capacitor is connected to the second terminal of the tenth TFT, and a second terminal of the second capacitor is connected to the third terminal of the tenth TFT.

Preferably, the GOA unit further comprises a fifth TFT, a second terminal of the fifth TFT receives the low potential signal, a first terminal of the fifth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the fifth TFT is connected to the second terminal of the eighth TFT.

Preferably, all the TFT's in the GOA unit are N-channel TFT's.

The present invention further provides a GOA circuit, which is used in a liquid crystal display panel, comprising m cascaded GOA units, wherein a nth-stage GOA unit comprises: a forward-reverse scan control module, a first gate signal output module and a second gate signal output module, wherein m≥n≥1;the forward-reverse scan control module is used for controlling the GOA circuit to perform a forward scanning or a reverse scanning in accordance with a forward scan control signal or a reverse scan control signal;the first gate signal output module comprises: a seventh thin film transistor (TFT), a ninth TFT and a sixteenth TFT; a third terminal of the seventh TFT receives a high potential signal, a first terminal of the seventh TFT is connected to an output terminal of the forward-reverse scan control module, and a second terminal of the seventh TFT is connected to a third terminal of the ninth TFT; a first terminal of the ninth TFT receives a nthclock signal, and a second terminal of the ninth TFT is for outputting a nthgate driving signal; a second terminal of the sixteenth TFT receives the high potential signal, a first terminal of the sixteenth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the sixteenth TFT is connected to the second terminal of the seventh TFT;

the second gate signal output module comprises: a twelfth TFT, a thirteenth TFT and a fifteenth TFT; a third terminal of the twelfth TFT receives the high potential signal, a first terminal of the twelfth TFT is connected to the output terminal of the forward-reverse scan control module, and a second terminal of the twelfth TFT is connected to a third terminal of the thirteenth TFT; a first terminal of the thirteenth TFT receives a (n+2)thclock signal, and a second terminal of the thirteenth TFT is for outputting a (n+2)thgate driving signal; a second terminal of the fifteenth TFT receives the high potential signal, a first terminal of the fifteenth TFT is connected to the first terminal of the twelfth TFT, and a third terminal of the fifteenth TFT is connected to the second terminal of the twelfth TFT;the forward-reverse scan control module comprises a first TFT and a second TFT;a first terminal of the first TFT receives the forward scan control signal, a first terminal of the second TFT receives the reverse scan control signal, a second terminal of the first TFT is connected to a second terminal of the second TFT and the first terminal of the seventh TFT, a third terminal of the first TFT receives a (n−2)thgate driving signal, and a third terminal of the second TFT receives a (n+4)thgate driving signal;wherein, the first terminal is one of source and drain, the second terminal is another one of source and drain, and the third terminal is gate.

Preferably, the GOA unit further comprises a third TFT, a fourth TFT, an eighth TFT, a tenth TFT and a fourteenth TFT;a first terminal of the third TFT receives a (n+1)thclock signal, and a first terminal of the fourth TFT receives a (n−1)thclock signal;a second terminal of the third TFT is connected to a second terminal of the fourth TFT and a third terminal of the eighth TFT;a third terminal of the third TFT receives the forward scan control signal, and a third terminal of the fourth TFT receives the reverse scan control signal;a first terminal of the eighth TFT receives the high potential signal, and a second terminal of the eighth TFT is connected to a third terminal of the tenth TFT and a third terminal of the fourteenth TFT;a first terminal of the tenth TFT is connected to the second terminal of the ninth TFT, a first terminal of the fourteenth TFT is connected to the second terminal of the thirteenth TFT, and a second terminal of the tenth TFT and a second terminal of the fourteenth TFT both receive a low potential signal.

Preferably, the GOA unit further comprises an eleventh TFT, a second terminal of the eleventh TFT is connected to a third terminal of the eleventh TFT and receives a reset signal, and a first terminal of the eleventh TFT is connected to the third terminals of the tenth TFT and the fourteenth TFT.

Preferably, the GOA unit further comprises a sixth TFT, a third terminal of the sixth TFT is connected to the second terminal of the second TFT, a first terminal of the sixth TFT is connected to the third terminals of the tenth TFT and the fourteenth TFT, and a second terminal of the sixth TFT receives the low potential signal.

Preferably, the GOA unit further comprises a first capacitor and a second capacitor;a first terminal of the first capacitor is connected to the first terminal of the seventh TFT, and a second terminal of the first capacitor receives the low potential signal;a first terminal of the second capacitor is connected to the second terminal of the tenth TFT, and a second terminal of the second capacitor is connected to the third terminal of the tenth TFT.

Preferably, the GOA unit further comprises a fifth TFT, a second terminal of the fifth TFT receives the low potential signal, a first terminal of the fifth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the fifth TFT is connected to the second terminal of the eighth TFT.

Preferably, all the TFT's in the GOA unit are N-channel TFT's.

The present invention further provides a GOA circuit, which is used in a liquid crystal display panel, comprising m cascaded GOA units, wherein a nth-stage GOA unit comprises: a forward-reverse scan control module, a first gate signal output module and a second gate signal output module, wherein m≥n≥1;the forward-reverse scan control module is used for controlling the GOA circuit to perform a forward scanning or a reverse scanning in accordance with a forward scan control signal or a reverse scan control signal;the first gate signal output module comprises: a seventh thin film transistor (TFT), a ninth TFT and a sixteenth TFT; a third terminal of the seventh TFT receives a high potential signal, a first terminal of the seventh TFT is connected to an output terminal of the forward-reverse scan control module, and a second terminal of the seventh TFT is connected to a third terminal of the ninth TFT; a first terminal of the ninth TFT receives a nthclock signal, and a second terminal of the ninth TFT is for outputting a nthgate driving signal; a second terminal of the sixteenth TFT receives the high potential signal, a first terminal of the sixteenth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the sixteenth TFT is connected to the second terminal of the seventh TFT;the second gate signal output module comprises: a twelfth TFT, a thirteenth TFT and a fifteenth TFT; a third terminal of the twelfth TFT receives the high potential signal, a first terminal of the twelfth TFT is connected to the output terminal of the forward-reverse scan control module, and a second terminal of the twelfth TFT is connected to a third terminal of the thirteenth TFT; a first terminal of the thirteenth TFT receives a (n+2)thclock signal, and a second terminal of the thirteenth TFT is for outputting a (n+2)thgate driving signal; a second terminal of the fifteenth TFT receives the high potential signal, a first terminal of the fifteenth TFT is connected to the first terminal of the twelfth TFT, and a third terminal of the fifteenth TFT is connected to the second terminal of the twelfth TFT;the GOA unit further comprises a third TFT, a fourth TFT, an eighth TFT, a tenth TFT and a fourteenth TFT;a first terminal of the third TFT receives a (n+1)thclock signal, and a first terminal of the fourth TFT receives a (n−1)thclock signal;a second terminal of the third TFT is connected to a second terminal of the fourth TFT and a third terminal of the eighth TFT;a third terminal of the third TFT receives the forward scan control signal, and a third terminal of the fourth TFT receives the reverse scan control signal;a first terminal of the eighth TFT receives the high potential signal, and a second terminal of the eighth TFT is connected to a third terminal of the tenth TFT and a third terminal of the fourteenth TFT;a first terminal of the tenth TFT is connected to the second terminal of the ninth TFT, a first terminal of the fourteenth TFT is connected to the second terminal of the thirteenth TFT, and a second terminal of the tenth TFT and a second terminal of the fourteenth TFT both receive a low potential signal;the GOA unit further comprises an eleventh TFT, a second terminal of the eleventh TFT is connected to a third terminal of the eleventh TFT and receives a reset signal, and a first terminal of the eleventh TFT is connected to the third terminals of the tenth TFT and the fourteenth TFT;wherein, the first terminal is one of source and drain, the second terminal is another one of source and drain, and the third terminal is gate.

Preferably, the forward-reverse scan control module comprises a first TFT and a second TFT;a first terminal of the first TFT receives the forward scan control signal, a first terminal of the second TFT receives the reverse scan control signal, a second terminal of the first TFT is connected to a second terminal of the second TFT and the first terminal of the seventh TFT, a third terminal of the first TFT receives a (n−2)thgate driving signal, and a third terminal of the second TFT receives a (n+4)thgate driving signal.

Preferably, the GOA unit further comprises a sixth TFT, a third terminal of the sixth TFT is connected to the second terminal of the second TFT, a first terminal of the sixth TFT is connected to the third terminals of the tenth TFT and the fourteenth TFT, and a second terminal of the sixth TFT receives the low potential signal.

Preferably, the GOA unit further comprises a first capacitor and a second capacitor;a first terminal of the first capacitor is connected to the first terminal of the seventh TFT, and a second terminal of the first capacitor receives the low potential signal;a first terminal of the second capacitor is connected to the second terminal of the tenth TFT, and a second terminal of the second capacitor is connected to the third terminal of the tenth TFT.

Preferably, the GOA unit further comprises a fifth TFT, a second terminal of the fifth TFT receives the low potential signal, a first terminal of the fifth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the fifth TFT is connected to the second terminal of the eighth TFT;all the TFT's in the GOA unit are N-channel TFT's.

Benefits of the present invention are as follows: Although there is risk existed in reversely leaking potentials of the nodes Qa and Qb through the seventh TFT and the twelfth TFT in the boost period when the connecting point Q connected to the output terminal of the forward-reverse scan control module, the first terminal of the seventh TFT and the first terminal of the twelfth TFT is interfered by signals, the potentials of the nodes Qa and Qb can be kept at normal level and the gate potentials of the ninth TFT and the thirteenth TFT can be kept at normal boost potential by turning on the fifteenth TFT and the sixteenth TFT in the boost period of the nodes Qa and Qb to charge the high potential signal VGH into the node Q to reduce the signal interference of the node Q. Finally, the output waveforms of the nthgate driving signal G(n) and the (n+2)thgate driving signal G(n+2) could be in normal status and the risk of failure of GOA cascaded transmission is reduced.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention provides a GOA circuit, which is used in a liquid crystal display panel. As shown inFIG. 3, the GOA circuit comprises m cascaded GOA units, a nth-stage GOA unit comprises: a forward-reverse scan control module300, a first gate signal output module100and a second gate signal output module200, wherein m≥n≥1.

The forward-reverse scan control module300is used for controlling the GOA circuit to perform a forward scanning or a reverse scanning in accordance with a forward scan control signal U2D or a reverse scan control signal D2U.

The first gate signal output module100comprises: a seventh thin film transistor (TFT) NT7, a ninth TFT NT9and a sixteenth TFT NT16. A third terminal of the seventh TFT NT7receives a high potential signal VGH, a first terminal of the seventh TFT NT7is connected to an output terminal of the forward-reverse scan control module300, and a second terminal of the seventh TFT NT7is connected to a third terminal of the ninth TFT NT9; a first terminal of the ninth TFT NT9receives a nthclock signal CK(n), and a second terminal of the ninth TFT NT9is for outputting a nthgate driving signal G(n); a second terminal of the sixteenth TFT NT16receives the high potential signal VGH, a first terminal of the sixteenth TFT NT16is connected to the first terminal of the seventh TFT NT7, and a third terminal of the sixteenth TFT NT16is connected to the second terminal of the seventh TFT NT7. The point connected between the seventh TFT NT7and the ninth TFT NT9is used as a node Qa.

The second gate signal output module200comprises: a twelfth TFT NT12, a thirteenth TFT NT13and a fifteenth TFT NT15. A third terminal of the twelfth TFT NT12receives the high potential signal VGH, a first terminal of the twelfth TFT NT12is connected to the output terminal of the forward-reverse scan control module300, and a second terminal of the twelfth TFT NT12is connected to a third terminal of the thirteenth TFT NT13; a first terminal of the thirteenth TFT NT13receives a (n+2)thclock signal, and a second terminal of the thirteenth TFT NT13is for outputting a (n+2)thgate driving signal G(n+2); a second terminal of the fifteenth TFT NT15receives the high potential signal VGH, a first terminal of the fifteenth TFT NT15is connected to the first terminal of the twelfth TFT NT12, and a third terminal of the fifteenth TFT NT15is connected to the second terminal of the twelfth TFT NT12; the point connected between the twelfth TFT NT12and the thirteenth TFT NT13is used as a node Qb.

The point connected to the output terminal of the forward-reverse control module30, the seventh TFT NT7and the twelfth TFT NT12is used as a node Q.

Wherein, the first terminal is one of source and drain, the second terminal is another one of source and drain, and the third terminal is gate.

There are four clock signals CK, that is, first clock signal, second clock signal, third clock signal and fourth clock signal, in the GOA circuit. When the (n+1)thclock signal CK(n+1) is the fourth clock signal, the (n+2)thclock signal should be the first clock signal. When the (n+1)thclock signal CK(n+1) is the second clock signal, the (n−1)thclock signal CK(n−1) should be the fourth clock signal. Furthermore, the forward-reverse scan control module300comprises a first TFT NT1and a second TFT NT2.

A first terminal of the first TFT NT1receives the forward scan control signal U2D, a first terminal of the second TFT NT2receives the reverse scan control signal D2U, a second terminal of the first TFT NT1is connected to a second terminal of the second TFT NT2and the first terminal of the seventh TFT NT7, a third terminal of the first TFT NT1receives a (n−2)thgate driving signal G(n−2), and a third terminal of the second TFT NT2receives a (n+4)thgate driving signal G(n+4). The second terminal of the first TFT NT1is further connected to the first terminal of the twelfth TFT NT12, and a point connected to the first TFT NT1, the seventh TFT NT7and the twelfth TFT NT12is the node Q.

When n≤2, the third terminal of the first TFT NT1receives a scan start-up signal STV. When n+4>m, the third terminal of the second TFT NT2receives the scan start-up signal STV. The scan star-up signal STV received by the third terminal of the first TFT NT1could be the same as or different from the scan star-up signal STV received by the third terminal of the second TFT NT2.

Furthermore, the GOA unit further comprises a third TFT NT3, a fourth TFT NT4, an eighth TFT NT8, a tenth TFT NT10and a fourteenth TFT NT14.

A first terminal of the third TFT NT3receives a (n+1)thclock signal CK(n+1), and a first terminal of the fourth TFT NT4receives a (n−1)thclock signal CK(n−1).

A second terminal of the third TFT NT3is connected to a second terminal of the fourth TFT NT4and a third terminal of the eighth TFT NT8.

A third terminal of the third TFT NT3receives the forward scan control signal U2D, and a third terminal of the fourth TFT NT4receives the reverse scan control signal D2U.

A first terminal of the eighth TFT NT8receives the high potential signal VGH, and a second terminal of the eighth TFT NT8is connected to a third terminal of the tenth TFT NT10and a third terminal of the fourteenth TFT NT14.

A first terminal of the tenth TFT NT10is connected to the second terminal of the ninth TFT NT9, a first terminal of the fourteenth TFT NT14is connected to the second terminal of the thirteenth TFT NT13, and a second terminal of the tenth TFT NT10and a second terminal of the fourteenth TFT NT14both receive a low potential signal VGL.

Furthermore, the GOA unit further comprises an eleventh TFT NT11. A second terminal of the eleventh TFT NT11is connected to a third terminal of the eleventh TFT NT11and receives a reset signal Reset, and a first terminal of the eleventh TFT NT11is connected to the third terminals of the tenth TFT NT10and the fourteenth TFT NT14.

Furthermore, the GOA unit further comprises a sixth TFT NT6. A third terminal of the sixth TFT NT6is connected to the second terminal of the second TFT NT2, a first terminal of the sixth TFT NT6is connected to the third terminals of the tenth TFT NT10and the fourteenth TFT NT14, and a second terminal of the sixth TFT NT6receives the low potential signal VGL.

Furthermore, the GOA unit further comprises a first capacitor1land a second capacitor C2.

A first terminal of the first capacitor C1is connected to the first terminals of the seventh TFT NT7and twelfth TFT NT12, and a second terminal of the first capacitor C2receives the low potential signa VGL.

One terminal of the second capacitor C2is connected to the second terminal of the tenth TFT NT10, and another terminal of the second capacitor C2is connected to the third terminal of the tenth TFT NT10.

Furthermore, the GOA unit further comprises a fifth TFT NT5. A second terminal of the fifth TFT NT5receives the low potential signal VGL, a first terminal of the fifth TFT NT5is connected to the first terminal of the seventh TFT NT7, and a third terminal of the fifth TFT NT5is connected to the second terminal of the eighth TFT NT8.

Furthermore, all the TFT's in the GOA unit are N-channel TFT's.

Although there is also risk existed in reversely leaking potentials of the nodes Qa and Qb through the seventh TFT and the twelfth TFT in the boost period when the connecting point Q is interfered by signals, the present invention adds the fifteenth TFT NT15and the sixteenth TFT NT16in the GOA unit so that, in the boost period of the nodes Qa and Qb, the fifteenth TFT NT15and the sixteenth TFT NT16are turned on through the potential pulled-up by boosting, and the high potential signal VGH is charged to the node Q to compensate the potential of the node Q so that the signal interference of the node Q is reduced. The waveform diagram of node Q is shown inFIG. 4. The potentials of the nodes Qa and Qb are kept at normal level and the gate potentials of the ninth TFT NT9and the thirteenth TFT NT13are kept at normal boost potential. Finally, the output waveforms of the nthgate driving signal G(n) and the (n+2)thgate driving signal G(n+2) could be in normal status and the risk of failure of GOA cascaded transmission is reduced.

The foregoing contents are detailed description of the disclosure in conjunction with specific preferred embodiments and concrete embodiments of the disclosure are not limited to these descriptions. For the person skilled in the art of the disclosure, without departing from the concept of the disclosure, simple deductions or substitutions can be made and should be included in the protection scope of the application.