Split contact structure and fabrication method thereof

A split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a first cell contact region in the major surface and being close to the first upwardly protruding structure; a second upwardly protruding structure disposed on the major surface; a second cell contact region in the major surface and being close to the second upwardly protruding structure; a first patterned layer stacked on the first upwardly protruding structure; a second patterned layer stacked on the first upwardly protruding structure; a first contact structure disposed on a sidewall of the first upwardly protruding structure and being in direct contact with the first cell contact region; and a second contact structure disposed on a sidewall of the second upwardly protruding structure and being in direct contact with the second cell contact region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a split contact structure and a dual-spacer process for fabricating such split contact structure.

2. Description of the Prior Art

As known in the art, dynamic random access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit.

Normally, each transistor of a DRAM cell comprises a gate, a drain region in a semiconductor substrate, and a source region spaced apart from the drain region. The gate is typically electrically connected to a word line. The source region is typically electrically connected to a digit line. The drain region is typically electrically connected to a capacitor through a cell contact structure.

Continued demand to shrink devices has facilitated the design of DRAM cells with greater density and smaller feature size and cell area. The dimension of the cell contact structure also shrinks dramatically, resulting in increased contact resistance and reduced process window.

Therefore, there is a need in this technical field to provide an improved cell contact structure for DRAM devices, which is capable of avoiding the above-mentioned prior art issues without increasing the complexity of the fabrication process.

SUMMARY OF THE INVENTION

It is one object of the invention to provide an improved split cell contact structure and fabrication method thereof in order to solve the above-mentioned prior art problems.

According to one aspect of the invention, a split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a first cell contact region in the major surface and being close to the first upwardly protruding structure; a second upwardly protruding structure disposed on the major surface; a second cell contact region in the major surface and being close to the second upwardly protruding structure; a first patterned layer stacked on the first upwardly protruding structure; a second patterned layer stacked on the first upwardly protruding structure; a first contact structure disposed on a sidewall of the first upwardly protruding structure and being in direct contact with the first cell contact region, wherein the first patterned layer protrudes from a top surface of the first contact structure; and a second contact structure disposed on a sidewall of the second upwardly protruding structure and being indirect contact with the second cell contact region, wherein the second patterned layer protrudes from a top surface of the second contact structure.

According to one embodiment, the first and second upwardly protruding structures extend along a first direction and the first and second patterned layers have a line-shaped pattern and extend along a second direction, wherein the first direction is perpendicular to the second direction.

It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations and process steps are not disclosed in detail, as these should be well-known to those skilled in the art.

Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and some dimensions are exaggerated in the figures for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with like reference numerals for ease of illustration and description thereof.

With regard to the fabrication of transistors and integrated circuits, the term “major surface” refers to that surface of the semiconductor layer in and above which a plurality of transistors are fabricated, e.g., in a planar process. As used herein, the term “vertical” means substantially orthogonal with respect to the major surface. Typically, the major surface is along a <100> plane of a monocrystalline silicon layer on which the field-effect transistor devices are fabricated.

FIG. 1toFIG. 9are schematic, cross-sectional diagrams showing an exemplary method for fabricating a split contact structure for DRAM devices in accordance with one embodiment of the invention. As shown inFIG. 1, a semiconductor substrate10such as a silicon substrate is provided. It is to be understood that the semiconductor substrate10may be composed of any suitable semiconductor materials or wafers known in the art. The semiconductor substrate10has a major surface10a, on which two upwardly protruding structures30and40are formed.

According to the illustrative embodiment, the two upwardly protruding structures30and40protrude from the major surface10aand are disposed in close proximity to each other. When viewed from above, the upwardly protruding structures30and40may extend along a first direction and arranged parallel to each other. When viewed from above, the upwardly protruding structures30and40may have a wave-shaped pattern. It is to be understood that only two upwardly protruding structures are illustrated for simplicity.

According to the illustrative embodiment, the upwardly protruding structure30may comprise a silicon lower portion300, a metal portion310directly on the silicon lower portion300, and a silicon nitride layer320stacked on the metal portion310and covering the sidewalls of the metal portion310. A silicon oxide layer330is stacked directly on the silicon nitride layer320. A silicon nitride liner340may be provided to cover the sidewalls of the silicon oxide layer330and the silicon nitride layer320. The upwardly protruding structure30has two opposite sidewall surfaces30aand30b.

According to the illustrative embodiment, the upwardly protruding structure40may comprise a silicon lower portion400, a metal portion410directly on the silicon lower portion400, and a silicon nitride layer420stacked on the metal portion410and covering the sidewalls of the metal portion410. A silicon oxide layer430is stacked directly on the silicon nitride layer420. A silicon nitride liner440may be provided to cover the sidewalls of the silicon oxide layer430and the silicon nitride layer420. The upwardly protruding structure40has two opposite sidewall surfaces40aand40b.

It is to be understood that the upwardly protruding structures30and40are for illustration purposes only. According to the illustrative embodiment, the metal portion310directly on the silicon lower portion300and the metal portion410directly on the silicon lower portion400may act as a digit line of the DRAM device, but not limited thereto.

When viewed from above, the silicon oxide layer330and the silicon oxide layer430may extend along a second direction and arranged parallel to each other. According to the illustrative embodiment, the first direction is perpendicular to the second direction, but not limited thereto. According to the illustrative embodiment, the silicon oxide layers330and430may be formed by using spin-on-dielectric (SOD) materials, but not limited thereto. The silicon oxide layers330and430are patterned layer and may both have a line-shaped pattern.

According to the illustrative embodiment, shallow trench isolation (STI) structure20and a plurality of trenched gate structures21,22,23, and24are provided in the semiconductor substrate10under the major surface10a.24. Each of the trenched gate structures21,22,23, and24may comprise a gate dielectric layer202, a conductive layer210, and a cap layer220.

According to the illustrative embodiment, a cell contact region230is provided adjacent to the trenched gate structure22and a cell contact region240is provided adjacent to the trenched gate structure23. It is to be understood that the arrangement of the STI structure20and the plurality of trenched gate structures21,22,23, and24are for illustration purposes only.

As shown inFIG. 2, according to the illustrative embodiment, a chemical vapor deposition (CVD) process may be carried out to deposit a polysilicon layer50on the semiconductor substrate10. The polysilicon layer50covers the two upwardly protruding structures30and40, the silicon oxide layers330and430, as well as the major surface10aincluding the STI structure20and the cell contact regions230and240.

As shown inFIG. 3, according to the illustrative embodiment, the polysilicon layer50is then etched back to reveal the silicon oxide layers330and430. After the etch back of the polysilicon layer50, a top surface50aof the polysilicon layer50may be flush with or lower than the oxide layers330and430. At this point, the oxide layers330and430protrude from the top surface50aof the polysilicon layer50.

As shown inFIG. 4, according to the illustrative embodiment, another CVD process is then performed to deposit a conformal spacer layer52such as a silicon nitride layer on the top surface50aof the polysilicon layer50and on the protrudent oxide layers330and430. The thickness of the deposited spacer layer52carefully controlled according to the desired target thickness of the cell contact to be formed in a later stage.

As shown inFIG. 5, subsequently, an anisotropic dry etching process is performed to etch the spacer layer52until the top surface50aof the polysilicon layer50is exposed, thereby forming spaces52aon two opposite sidewalls of the oxide layers330and430.

As shown inFIG. 6, according to the illustrative embodiment, another dry etching process may be performed, using the spacer layer52as an etching hard mask, to partially etch away a top portion of the polysilicon layer50not covered by the spacers52ain a self-aligned manner. After the partial etch of the polysilicon layer50, a recess54is formed in the polysilicon layer50.

As shown inFIG. 7, optionally, after the partial etch of the polysilicon layer50, according to the illustrative embodiment, a portion of the spacers52aand a portion of the oxide layers330and430may be etched away. According to the illustrative embodiment, the removal of the portion of the spacers52amay use wet etching methods known in the art, but not limited thereto.

As shown inFIG. 8, according to the illustrative embodiment, another CVD process may be carried out to deposit a spacer layer56on the spacers52aand in the recess54. According to the illustrative embodiment, the spacer layer56conformally covers spacers52a, the oxide layers330and430, and the interior surface of the recess54. The spacer layer56does not fill up the recess54. According to the illustrative embodiment, the spacer layer56may comprise silicon nitride, silicon oxynitride, silicon oxide, or silicon carbide, but not limited thereto.

As shown inFIG. 9, according to the illustrative embodiment, an anisotropic dry etching process is then performed to etch the spacer layer56, thereby forming spacers56aon the spacers52arespectively. Subsequently, using the spacers56aand the spacers52aas an etching hard mask, an etching process is then performed to etch the remaining polysilicon layer50not covered by the spacers56aand the spacers52auntil the STI structure20is revealed, thereby forming split cell contact structures50′ on the cell contact regions230and240respectively. Optionally, an over etch may be performed to form an inwardly curved sidewall profile60.