RADIO FREQUENCY INDUCTOR

An interconnect structure is formed, including a plurality of patterned metallization layers spaced apart by dielectric material on the semiconductor wafer. A radio frequency (RF) inductor device is formed on the interconnect structure. To this end, a copper inductor coil is formed on the interconnect structure by plating. The plated copper inductor coil is textured copper having at least 90% (111) orientation. The plated copper inductor coil is electrically connected with at least one patterned metallization layer of the interconnect structure. Upper domes may be formed on turns of the plated copper inductor coil.

BACKGROUND

The following relates to the semiconductor device and manufacturing arts, back end-of-line (BEOL) processing arts, radio frequency (RF) inductor arts, BEOL inductor arts, and related arts.

DETAILED DESCRIPTION

Radio frequency (RF) inductors are incorporated into the back end-of-line (BEOL) processing of integrated circuit (IC) chips for various purposes, such as obtaining improved quality factor (Q-factor) for RF signals. Placement of the RF inductor in the BEOL processing has some advantages over forming it on the semiconductor wafer during front end-of-line (FEOL) processing. An RF inductor is a relatively large-area device, and hence placing it on the semiconductor wafer can occupy valuable wafer area. A BEOL RF inductor can also be positioned closer to RF signal input/output (I/O) to/from the IC chip.

Various factors affect inductor performance, including proximity effect, skin effect, and others. The skin effect refers to the lack of RF penetration into the material, such that electric fields at RF frequencies are confined to the surface of an electrically conductive material. The skin depth δ of an RF signal in a conductive material is given by:

where f is the RF frequency, ρ is the electrical resistivity of the conductor, μ is the magnetic permeability of the conductor, and π denotes the mathematical “pi” constant. Reduced skin depth δ means that a smaller portion of the inductor (specifically, a thin surface portion of the turns of the inductor) carries the entire RF load. This can reduce RF coupling efficiency since most of the inductor material is shielded from RF coupling by the skin effect, and can potentially damage the inductor itself due to excessive Joule heating concentrated at the surface of the conductors of the inductor. One way to counter this is to employ a physically larger inductor so as to increase the total surface area of the inductor, but this makes IC chip miniaturization more difficult.

From Equation (1), it is seen that the skin depth δ decreases (and hence the detrimental skin effect increases) with increasing RF frequency f, and decreases with reduced electrical resistivity ρ. The RF frequency f is typically fixed for a given IC chip design, and so it is desirable to reduce the resistivity ρ, as lower electrical resistance of the inductor material results in reduced skin effect.

Embodiments disclosed herein advantageously provide inductors for BEOL processing that are made of low resistance copper. However, making a BEOL inductor from copper has its own disadvantages. Notably, due to the skin effect the RF currents are flowing on the outer skin of the copper inductor. This concentrates Joule heating on the surface, which can result in elevated operating temperatures that approach the melting point of copper (about 1084° C. for pure copper), leading to thermal instability.

To overcome these difficulties, some embodiments of the copper inductor disclosed herein employ textured copper having at least 90% (111) orientation, and in some embodiments at least 97% (111) orientation. In such high texture (111) copper material, the grains are predominantly oriented in the (111) orientation. This has several benefits. It results in predominantly low-angle grain boundaries since most grains have close to (111) orientations. The low-angle grain boundaries reduce the contribution of the grain boundaries to the electrical resistance of the high texture (111) copper material, thus resulting in the high texture (111) copper material having lower electrical resistivity p compared with other types of copper. High texture (111) copper material also exhibits improved hardness and electromigration and oxidation resistance compared with high texture copper material of other orientations (e.g., high texture (101) copper).

In some embodiments, the copper inductor coil is advantageously formed on an insulator layer by plating, which can produce high texture (111) copper material having at least 90% (111) orientation, and in some embodiments at least 97% (111) orientation. Characterization techniques such as X-ray diffraction (XRD), electron backscatter diffraction (EBSD), and cross-sectional scanning electron microscopy (SEM) can be used to quantitatively measure the percentage of the copper having the desired (111) orientation, thus enabling empirical determination of the percentage (111) orientation of the high texture (111) copper material. Plating parameters such as pulse current magnitude and frequency, and the plating temperature, can be empirically optimized using test runs characterized by XRD and/or EBSD to optimize the plating to obtain high texture (111) copper material having the desired at least 90% (111) orientation, or the desired least 97% (111) orientation. In some embodiments, the plating may employ both forward and reverse pulses during the plating process. The choice of seed layer can also impact the texture and can be similarly empirically optimized.

In some embodiments, the copper inductor coil is advantageously modified to include an upper dome on turns of the copper inductor coil. The upper dome increases the total surface area of the turns of the copper inductor coil, thus providing improved RF coupling by way of increased total surface area without a concomitant increase in the layout area occupied by the RF inductor.

In some embodiments, both of these features are combined: the copper inductor coil comprises textured copper having at least 90% (111) orientation, and in some embodiments at least 97% (111) orientation; and also includes an upper dome on the turns of the copper inductor coil. The resulting inductor advantageously has improved electrical performance (e.g., lower resistance and higher Q-factor) and improved hardness and thermal stability.

With reference now toFIGS.1and2, a radio frequency (RF) inductor device6is shown by a top view (FIG.1) and a sectional view shown inFIG.2taken along Section S-S line indicated inFIG.1. The RF inductor device6includes an insulator layer8and a copper inductor coil10(i.e., inductor10) disposed on the insulator layer8. The copper inductor coil10has a plurality of turns (illustrative four turns), but the number of turns can be one, two, three, illustrative four, five, six, or more turns. Typically, the inductance increases with an increasing number of turns (ideally, the inductance increases with the square of the number of turns, although this assumes perfect coupling between the turns which is usually not the case). It can be preferable in some IC chip designs to limit the number of turns, since increasing the number of turns increases the layout area of the inductor12, which can be undesirable if it is desired to miniaturize the IC chip. WhileFIG.1shows a top view of the RF inductor device6including the copper inductor coil10,FIG.2shows Section S-S including additional components that may be included, such as the aforementioned insulator layer8and one or more dielectric overlayers such as an insulating coating12disposed over the copper inductor coil10(and optionally over portions of the insulator layer8not covered by the copper inductor coil10), and a polyimide14encapsulating the copper inductor coil10(and its insulating coating12).

The copper inductor coil10is made of textured copper having at least 90% (111) orientation, and more preferably at least 97% (111) orientation. As already discussed, this high texture (111) copper has benefits over other forms of copper, as high texture (111) copper provides benefits such as reduced electrical resistance (for a given inductor coil layout/number of turns), and improved hardness and electromigration and oxidation resistance compared with other a coil of another type of copper. The use of high texture (111) copper can provide improvements in the RF performance and reliability of the inductor10, including improved electrical performance (e.g., lower resistance and higher Q-factor) and improved hardness and thermal stability. Typically, these benefits increase with increasing percentage having the (111) orientation. In some embodiments, at least 97% (111) orientation is preferred to obtain desired low electrical resistance and high thermal stability of the high texture (111) copper inductor coil10.

Without loss of generality,FIG.2illustrates dimensions of the high texture (111) copper inductor coil10including a height H1in a height direction that is transverse to the insulator layer8, a width W1of the turns of the high texture (111) copper inductor coil10, and a spacing S1between neighboring turns of the copper inductor coil10. As seen inFIG.2, the spacing S1is measured from one edge of one turn to the closest edge of the next turn. The dimensions H1, W1, and S1are selected for ease of processing/fabrication of the copper inductor coil10and for reliability of the copper inductor coil10. Based on these considerations, in some nonlimiting illustrative embodiments the coil height H1is in a range of one micron to 7 microns (that is, 1 μm≤H1≤7 μm), the turn width W2is in a range of one micron to 50 microns (that is, 1 μm≤W1≤50 μm), and the spacing S1is in a range of one micron to 50 microns (that is, 1 μm≤S1≤50 μm).

In the illustrative embodiment, the turns of the inductor10include footings16disposed on the insulator layer8and extending away a distance W2(indicated inFIG.2) from the opposite sides of each turn. In some nonlimiting illustrative embodiments, the distance W2is between 0.1 micron and one micron (that is, 0.1 μm≤W2≤1 μm). The footings16are optional (or, put another way, W2=0 is contemplated). The insulating coating12has a thickness W3indicated inFIG.2. In some nonlimiting illustrative embodiments, the thickness W3is in a range of 0.5 micron to two microns (that is, 0.5 μm≤W3≤2 μm). Again, these ranges for W2and W3are selected for ease of processing/fabrication of the copper inductor coil10and for reliability of the copper inductor coil10, and should be considered to be nonlimiting illustrative examples.

As seen inFIG.2, the turns of the copper inductor coil10have an upper dome18on turns of the copper inductor coil. The upper dome18of each turn is distal from the insulator layer8. As previously discussed, the upper dome18increases to the total surface area of the inductor10compared with the turns having planar top surfaces, thus advantageously increasing the total surface area for RF coupling so as to improve overall RF coupling of the inductor10. In some nonlimiting illustrative examples, the upper dome18may have a height H2in a range of between 0.2 microns and one micron (that is, 0.2 μm≤H2≤1 μm). The height H2is measured along the same height direction transverse to the insulator layer8along which the overall height H1of the coil10is measured, and as seen inFIG.2the overall height H1of the coil10includes the height H2of the dome18. As further seen inFIG.2, the polyimide14encapsulating the inductor10extends a height H3(again in the height direction) above the top of the domes18. In some nonlimiting illustrative embodiments, the height H3is in a range of one micron to seven microns (that is, 1 μm≤H3≤7 μm). Again, these ranges for H2and H3are selected for ease of processing/fabrication of the copper inductor coil10and for reliability of the copper inductor coil10, and should be considered to be nonlimiting illustrative examples.

The insulator layer8and the optional insulating coating12can comprise any suitable electrically insulating material, such as (by way of nonlimiting illustrative example) an oxide (e.g., stoichiometric SiO2or a nonstoichiometric SixOywhere 0<(x,y)<1), a nitride (e.g., stoichiometric Si3N4or nonstoichiometric SixNywhere 0<(x,y)<1), a silicon oxynitride, a multilayer of two or more insulator materials, or so forth.

With reference toFIG.3, the RF inductor device6ofFIGS.1and2is shown in sectional view in the context of BEOL processing. A typical manufacturing workflow for fabricating an integrated circuit (IC) includes front end-of-line (FEOL) processing and back end-of-line (BEOL) processing stages. During the FEOL processing, various electronic, optoelectronic, photonic, or other devices such as transistors, photodetectors, and/or so forth are fabricated on and/or in a semiconductor wafer30such as a silicon, silicon-on-insulator (SOI), germanium, gallium arsenide (GaAs), or other semiconductor wafer. This produces a layer or region of semiconductor devices32on a surface of the semiconductor wafer30. These devices may, for example, be RF signal processing devices, as a nonlimiting illustrative example.

The BEOL processing follows the FEOL processing, and includes forming a stack of patterned metallization layers34spaced apart by dielectric material36, sometimes referred to as intermetal dielectric (IMD) material36. The patterned metallization layers34may, by way of nonlimiting illustrative example, comprise an electrically conductive material such as copper, aluminum, a copper alloy, or an aluminum alloy. The patterned metallization layers34are typically not high texture (111) copper, although it is contemplated from the patterned metallization layers34to be high texture (111) copper. The IMD material36is typically an oxide, such as silicon dioxide (SiO2) formed by plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or another deposition technique. Electrically conductive vias38pass through the IMD material36to interconnect the patterned metallization layers34. The vias38may, for example, comprise tungsten, copper, or another electrically conductive material. A typical BEOL processing sequence entails successive iterations to build up the stack of patterned metallization layers34. Each iteration may, for example, include: depositing IMD material on the last patterned metallization layer (or, on the layer or region of semiconductor devices32in the case of the initial M0 metallization layer); photolithographic processing of the IMD material to form via openings passing through the IMD material to access the last patterned metallization layer (or the layer or region of semiconductor devices32in the case of the initial M0 metallization layer); followed by metal deposition to fill the via openings to form vias38; and deposition and photolithographic patterning of the next metallization layer. This process can be iteratively repeated to build up the stack of patterned metallization layers34. The stack of patterned metallization layers34and interconnecting vias38formed during BEOL processing provide electrically conductive circuitry for interconnecting transistors, photodetectors, and/or other devices of the layer or region of semiconductor devices32formed on a surface of the semiconductor wafer10during the FEOL processing.

The structure comprising the stack of patterned metallization layers34and the IMD material36may, for example, constitute an interconnect structure40. In some embodiments, a topmost patterned metallization layer34rserves as the contact surface for bonding the overall device (e.g., the device layer32and the interconnect structure40) to a printed circuit board, another IC chip, or the like (not shown). Bonding pads42(only one representative example of which is shown inFIG.3) may be formed on the top surface of the interconnect structure40(e.g., on the topmost patterned metallization layer34T) to serve as under-bump metallization (UBM) for bonding bumps (not shown) used to bond the IC chip to the printed circuit board, other IC chip, or the like. The bonding bumps may be solder bumps, copper balls, solder-coated copper balls, or the like.

Typically, the bonding bumps42are made of copper or a copper alloy. However, in some embodiments it is contemplated that the bonding pads42may also be made of high texture (111) copper, and in such embodiments the formation of the high texture (111) copper bonding bumps42may be performed at the same time as the formation of the high texture (111) copper inductor coil10, for example in a single plating process that forms both the high texture (111) copper bonding bumps42and the high texture (111) copper inductor coil10.

With continuing reference toFIG.3and with further reference back toFIGS.1and2, the high texture (111) copper inductor coil10is electrically connected with the interconnect structure40, e.g., with the topmost patterned metallization layer34T, by electrical vias44passing through the insulator layer8to contact the topmost patterned metallization layer34T. The vias44may be formed of the same high texture (111) copper material that formed the high texture (111) copper inductor coil10, and may, for example, be formed by the same process (e.g., plating) used to form the copper inductor coil10. That is, the plating process may operate to fill via openings photolithographically formed in the insulator layer8with high texture (111) copper to form the vias44and the plating process continues to form the high texture (111) copper inductor coil10. It is noted that the patterned metallization layer34T with which the high texture (111) copper inductor coil10is electrically connected by the vias44is typically not made of high texture (111) copper (that is, the connected metallization layer34T is typically not made of high texture (111) copper). However, it is alternatively contemplated for the connected metallization layer34to also be made of high texture (111) copper.

FIG.1illustrates possible locations for the vias44at opposite ends of the spiral coil10. (It is noted that the vias44are underneath the high texture (111) copper inductor coil10, and so they would not typically be visible in the top view ofFIG.1, hence the indicated locations of the vias44inFIG.1should be considered diagrammatic representations). However, it should be noted that the locations of the vias44shown inFIG.1is merely a nonlimiting illustrative example.

The RF inductor device6, and more particularly the high texture (111) copper inductor coil10, can serve various functions in the IC chip. For example, the high texture (111) copper inductor coil10can serve as the inductor in an LC (inductor-capacitor), RL (resistor-inductor), or RLC (resistor-inductor-capacitor) sub-circuit of RF circuitry of the IC chip. For example, an LC or RLC circuit can form a resonant circuit that can perform RF frequency filtering, improve the Q-factor of RF signal processing, or so forth. These are merely some nonlimiting illustrative examples.

In the example ofFIG.3, the RF inductor device6including the high texture (111) copper inductor coil10is formed on (and hence disposed at) a top surface of the interconnect structure40; that is, formed on/disposed at the surface of the interconnect structure40opposite from the layer or region of semiconductor devices32. However, it is contemplated to instead have the RF inductor device6embedded within the interconnect structure. For example, if the interconnect structure includes 10 patterned metallization layers34(enumerated, without loss of generality, as layers M0-M9), then as a nonlimiting example the first 5 patterned metallization layers34(i.e., layers M0-M4) could be formed, after which the RF inductor device6is formed and contacts the M4 patterned metallization layer by the vias44, followed by formation of the latter 5 patterned metallization layers (i.e., layers M5-M9).

With reference back toFIG.1, the illustrative high texture (111) copper inductor coil10is rectangular, and includes four turns. However, this is merely one nonlimiting illustrative example. Both number of turns and the geometrical shape of the turns can be chosen based on various factors such as the desired inductance, the acceptable layout area occupied by the high texture (111) copper inductor coil, and so forth. Typically, the inductance increases with the number of turns, e.g., ideally inductance increases with the square of the number of turns. On the other hand, more turns can increase the layout area for the inductor, which may be undesirable if IC chip miniaturization is a goal.

With reference toFIGS.4and5, two additional nonlimiting illustrative examples of suitable layouts for the high texture (111) copper inductor coil are shown. In the example ofFIG.4, a high texture (111) copper inductor coil10octis octagonal, that is, eight-sided. Put another way, the turns of the high texture (111) copper inductor coil10octofFIG.4are octagonal in shape. The illustrative high texture (111) copper inductor coil10octofFIG.4has nine (9) octagonal turns; however, the number of turns can be chosen for the desired application (e.g., the desired inductance and layout area).

In the example ofFIG.5, a high texture (111) copper inductor coil10HDis rectangular, that is, has rectangular turns, as in the embodiment ofFIG.1. However, the high texture (111) copper inductor coil10HDis has more turns than the high texture (111) copper inductor coil10ofFIG.1. The illustrative high texture (111) copper inductor coil10HDofFIG.5has eleven (11) rectangular turns. Moreover, the high texture (111) copper inductor coil10HDofFIG.5has these 11 turns packed with a higher density, by reducing the spacing S1between adjacent turns (where S1was defined previously with reference toFIG.2). There can be tradeoffs in such designs—for example, reducing the spacing S1can provide a more compact inductor, but if the inductor operates at high voltage then a small spacing S1can increase the possibility of a voltage arc across neighboring turns.

FIGS.4and5also illustrate different options for the locations of the vias44connecting the inductor with the underlying patterned metallization layer34T. In the embodiment ofFIG.4, the high texture (111) copper inductor coil10octhas connecting vias44distributed over the length of the octagonal coil. In the example ofFIG.5, the connecting vias44are grouped into four groups contacting the outermost fourth through tenth turns, along with five vias44contacting the end of the innermost turn and ten vias44contacting the end of the outermost turn. Again, it is to be understood that the locations of the vias44are diagrammatically indicated inFIGS.4and5—in practice, they are located underneath the respective high texture (111) copper inductor coils10octand10HDand hence are occluded from view in the top views ofFIGS.4and5.

Although not visible in the top views ofFIGS.4and5, it will be appreciated that these embodiments may optionally include the upper dome18on the turns of the respective high texture (111) copper inductor coils10octand10HD. In some embodiments, the high texture (111) copper material of the respective high texture (111) copper inductor coils10octand10HDhas at least 90% (111) orientation, and in some embodiments at least 97% (111) orientation.

Again, it is to be understood that the coil layout embodiments ofFIGS.1,4, and5are merely nonlimiting illustrative examples. More generally, the high texture (111) copper inductor coil can have turns of various geometries (e.g., rectangular, hexagonal, octagonal, or so forth) and can in general have any number of turns (e.g., one turn, two turns, three turns, five turns, ten turns, fifteen turns, et cetera).

With reference now toFIG.6, a suitable method for fabricating the RF inductor device6including the high texture (111) copper inductor coil10is described. The method ofFIG.6assumes the interconnect structure40ofFIG.3has been formed. That is, the method ofFIG.6starts after formation of the interconnect structure40. (However, if the RF inductor device6is to be embedded in the interconnect structure40then the method ofFIG.6could be performed after some, but not all, patterned metallization layers34are formed, after which the method ofFIG.6would be performed, followed by formation of the remaining patterned metallization layers34of the interconnect structure).

The method ofFIG.6starts with an operation50in which the insulator layer8is deposited on the interconnect structure40, and openings destined to be filled to form the vias44are opened in the insulator layer8by photolithographic processing. The operation50can entail forming the insulator layer8of a suitable electrically insulating material such as an oxide, a nitride, a silicon oxide, silicon nitride, or silicon oxynitride, a multilayer of two or more insulator materials, or so forth. The insulator layer8may be formed by any suitable deposition technique for depositing the insulating material, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or so forth. The openings for the vias44are suitably formed by photolithographic processing, i.e., a photoresist layer (not shown) is disposed on the blanket insulator layer8and exposed via a photomask and the exposed photoresist developed to form openings in the photoresist aligned with the openings to be formed in the insulator layer8, followed by suitable chemical etching that etches the openings in the insulator layer8through the openings in the photoresist, followed by photoresist stripping.

In an operation52, a patterned seed layer for subsequent plating of the high texture (111) copper inductor coil10is deposited by PVD, CVD, or another suitable technique. The seed layer may be copper, but could be another electrically conductive material that is suitable for seeding electroplating of high texture (111) copper. The patterned seed layer is typically thin, e.g. substantially thinner than the height H1of the plated high texture (111) copper inductor coil10(see definition of H1inFIG.2). The operation52may, for example, include depositing a blanket layer of the seed material and then photolithographically patterning the blanket layer to form the patterned seed layer of copper or another suitable plating seed material.

In an operation54, the high texture (111) copper inductor coil10is formed by plating. Parameters of the electroplating (also known in the art as electrochemical deposition, or electrodeposition) are chosen to form the high texture (111) copper material with the desired high texture (e.g., at least 90% (111) orientation, and in some embodiments at least 97% (111) orientation). As previously mentioned, the electroplating parameters, such as pulse current magnitude and frequency and the plating temperature, are suitably empirically optimized using test runs in which high texture (111) copper layers of the desired thickness (e.g., corresponding to the desired coil height H1as indicated inFIG.2) are formed with different electroplating parameters; and the textures of the respective test high texture (111) copper layers are characterized by XRD, EBSD, and/or SEM to determine the percentage (111) orientation in each test layer. The choice of patterned seed layer formed in the operation52can be similarly (co-) optimized. In some embodiments, the plating performed in the operation54may employ both forward and reverse pulses during the plating process, which can increase the (111) texture.

Notably, the area extent of the plating is limited to the patterned seed layer formed in the previous operation52. This is because the electrically insulating layer8is not a suitable conductor for the plating process. Hence, the layout of the high texture (111) copper inductor coil10(or, alternatively, of the high texture (111) copper inductor coil10octof the embodiment ofFIG.4or the high texture (111) copper inductor coil10HDof the embodiment ofFIG.5) is determined by the photolithographic patterning of the seed layer.

The bonding pads42may be made of a material such as aluminium or an aluminum alloy. In some contemplated embodiments, however, some or all of the bonding pads42(seeFIG.3and related discussion) may be formed of high texture (111) copper in the operations52and54. To do so, the patterning of the seed layer in the operation52includes forming seed layer portions corresponding to both the high texture (111) copper inductor coil10and the bonding pads42. In this way, the subsequent plating operation54plates the high texture (111) copper material both on the portion of the patterned seed layer corresponding to the coil thus forming the high texture (111) copper inductor coil10, and also on the portions of the patterned seed layer corresponding to the bonding pads42(thus forming the bonding pads42of the same plated high texture (111) copper material as forms the coil10). It will be appreciated that the bonding pads42can similarly benefit from being made of the high texture (111) copper material, thus conferring benefits for the bonding pads42such as reduced electrical resistance of the bonding pads42and improved thermal stability for the bonding pads42.

In embodiments in which the turns of the high texture (111) copper inductor coil10are to include the upper dome18, this can subsequently be formed in an operation56by a suitable etching process. In one nonlimiting illustrative approach, an isotropic etch can be applied which will preferentially etch the upper corner of the turn due to there being two exposed surfaces at the corner (namely the top surface and the side surface). This preferential etching of the corners forms the upper surfaces of the turns into the desired shape of the upper dome18. Again, empirical optimization can be performed, for example using cross-sectional SEM to directly image the shape of the domes18achieved for different etching parameters. It will be appreciated that the etching may also contribute to forming the optional footings16of the turns of the high texture (111) copper inductor coil10.

In an operation60, the optional insulating coating12is disposed on the high texture (111) copper inductor coil10(and optionally on portions of the surface of the insulator layer8between the turns of the copper inductor coil10). The insulating coating12can be formed by any suitable deposition technique (e.g., PVD, CVD, et cetera) and can comprise any suitable electrically insulating material, such as an oxide, a nitride, a silicon oxide, silicon nitride, or silicon oxynitride, a multilayer of two or more insulator materials, or so forth.

In an operation62, the optional encapsulating polyimide14is formed. In one approach, polyimide material is deposited up to a thickness of at least H1+H3(where H1and H3are defined as shown inFIG.2), followed by chemical-mechanical polishing to planarize the upper surface of the polyimide with the final thickness as shown inFIG.2(e.g., the thickness H3above the top of the upper domes18of the coil10).

In the illustrative method ofFIG.6, the high texture (111) copper inductor coil10is formed by plating in the operation54, with the high texture (111) copper being plated onto the patterned seed layer formed in the operation52. However, other methods for forming the high texture (111) copper inductor coil10are contemplated, such as sputtering as another nonlimiting illustrative example. In this illustrative alternative embodiment (not shown), the operations52and54would be replaced by a sputtering operation to form a blanket layer of high texture (111) copper, followed by suitable photolithographic patterning of the blanket high texture (111) copper to form the high texture (111) copper inductor coil10.

In the following, some further embodiments are described.

In a nonlimiting illustrative embodiment, a method of forming a radio frequency (RF) inductor device is disclosed. The method includes forming an insulator layer, and forming a copper inductor coil on the insulator layer by plating. The copper inductor coil comprises textured copper having at least 90% (111) orientation.

In a nonlimiting illustrative embodiment, a method of forming an RF inductor device is disclosed. The method comprises: forming semiconductor devices on a semiconductor wafer; after forming the semiconductor devices, forming an interconnect structure comprising a plurality of patterned metallization layers spaced apart by dielectric material on the semiconductor wafer; and forming a copper inductor coil on the interconnect structure by plating. The copper inductor coil comprises textured copper having at least 90% (111) orientation. The plated copper inductor coil is electrically connected with at least one patterned metallization layer of the interconnect structure.

In a nonlimiting illustrative embodiment, an RF inductor device includes an insulator layer, and a copper inductor coil having a plurality of turns disposed on the insulator layer. The copper inductor coil comprises textured copper having at least 90% (111) orientation.