Semiconductor component comprising interconnected cell strips

A semiconductor component comprises a semiconductor body including a front side and a number of cell strips. Each of the cell strips includes a terminal zone of a first type arranged on the front side of the semiconductor body and a terminal zone of a second type arranged on the front side of the semiconductor body. A patterned first metallization layer, a patterned second metallization layer, and a patterned third metallization layer are arranged successively on the front side. A first plurality of conductive lines are formed in the first metallization layer and a second plurality of conductive lines are formed in the second metallization layer. The second plurality of conductive lines cross the first plurality of conductive lines at crossover locations. The second plurality of conductive lines are electrically conductively connected to the first plurality of conductive lines at predetermined crossover locations.

CROSS-REFERENCE TO RELATED APPLICATIONS

This document claims priority from German patent application number 10 2005 047 104.8, filed on Sep. 30, 2005.

FIELD

The invention relates to a semiconductor component, in particular a power semiconductor component comprising interconnected cell strips.

BACKGROUND

In order to be able to carry higher currents, semiconductor components of this type have a plurality of cells that are electrically connected in parallel with one another. Each of the cells comprises a terminal zone of a first type, for example, a drain terminal of a DMOS cell, and a terminal zone of a second type, for example a source terminal of a DMOS cell. Usually a plurality of such cells are in each case connected together to form cell strips.

In order that two or more of such cell strips are electrically connected in parallel, with regard to all the cell strips to be connected in parallel firstly their terminal zones of the first type must be electrically conductively connected to one another and secondly their terminal zones of the second type must be electrically conductively connected to one another.

FIG. 1shows a section of such a semiconductor component in accordance with the prior art in a perspective view.

The semiconductor component comprises a semiconductor body10having two cell strips91,92having a cell strip width d (“pitch”), which each have a strip-shaped terminal zone7of a first type and a strip-shaped terminal zone8of a second type. The terminal zones7,8run in a first lateral direction x of the semiconductor body10and perpendicular to a second lateral direction y of the semiconductor body10.

By way of example, the terminal zones7of the first type are formed as drain terminal zones D and the terminal zones8of the second type are formed as source terminal zones S. The terminal zones7of the first type and terminal zones8of the second type are arranged alternately successively and parallel to one another.

A patterned first metallization layer1, a patterned second metallization layer2and a patterned third metallization layer3are arranged successively on the front side19of the semiconductor body10above the terminal zones7,8. The first and second metallization layers1,2are formed from aluminum and the third metallization layer3is formed from copper.

The third metallization layer3has a first section33and a second section34. All the terminal zones7of the first type are electrically conductively connected to the first section33and all the terminal zones8of the second type are electrically conductively connected to the second section34of the third metallization layer3.

The first and second metallization layers1,2are primarily required for feeding the necessary electrical drive signals to terminal zones (not illustrated inFIG. 1) for driving the cell strips91,92that is to say the gate terminal zones thereof, by way of example.

Since, for this reason, the first and the second metallization layer1,2cannot be dispensed with, sections of the first and the second metallization layer1,2are used for producing, together with plated-through holes41,51,61which are also referred to as “vias”, and also with further plated-through holes that are not discernible in this view, the electrically conductive connections between the terminal zones7of the first type and the first section33of the third metallization layer3and also between the terminal zones8of the second type and the second section34of the third metallization layer3.

For this purpose, the patterned first metallization layer1has conductive lines11,12,13,14spaced apart from one another and the patterned second metallization layer2has conductive lines21,22,23,24spaced apart from one another. The conductive lines11,12,13,14,21,22,23,24are formed in strip-shaped fashion and run parallel to one another and also parallel to the strip-shaped terminal zones7,8of the semiconductor body10.

Each of the terminal zones7,8forms a unit with two overlaying conductive lines, of which one belongs to the first metallization layer1and one belongs to the second metallization layer2, and is electrically conductively connected to these by means of plated-through holes. Arranged above the conductive lines21,23of the second metallization layer2are plated-through holes61which electrically connect the conductive lines21,23to the first section33of the third metallization layer3.

Correspondingly, arranged above the conductive lines22,24of the second metallization layer2are plated-through holes (not discernible inFIG. 1) which electrically connect the conductive lines22,24to the second section34of the third metallization layer3.

An intermetal dielectric is generally arranged between the semiconductor body10and the first metallization layer1, between the first metallization layer1and the second metallization layer2, between the second metallization layer2and the third metallization layer3, between the conductive lines11,12,13,14of the first metallization layer1, between the conductive lines21,22,23,24of the second metallization layer2, and also between the sections33,34of the third metallization layer3; the illustration of said intermetal dielectric has been dispensed with inFIG. 1for reasons of clarity.

FIG. 2shows a plan view of the semiconductor component in accordance withFIG. 1. This view reveals the conductive lines21,22,23and24of the second metallization layer, above which the sections33,34of the third metallization layer are arranged.

The positions of plated-through holes61,62arranged between the second and the third metallization layer2,3are indicated as dotted circles inFIG. 2.

In this case, the plated-through holes61connect the conductive lines21,23of a second metallization layer that are connected to the drain terminal zones to the first section33of the third metallization layer. The plated-through holes62correspondingly connect the conductive lines22,24of the second metallization layer that are connected to the source terminal zones to the second section34of the third metallization layer.

In the context of technical further development, the cell strip widths d decrease further and further whilst retaining the same current-carrying capacity, which, relative to the active chip area, leads to ever higher current densities in the component.

In such an arrangement with increasing current densities undesirably high voltages are dropped across the electrical line resistances between the terminal zones7and the section33of the third metallization layer3and also between the terminal zones8and the section34of the third metallization layer3.

SUMMARY

The semiconductor component according to at least one embodiment of the invention comprises a semiconductor body having a front side, in which a number of cell strips formed from DMOS cells for example, are arranged.

Each of the DMOS cell strips comprises a terminal zone of a first type, for example a drain terminal zone and a terminal zone of a second type, for example a source terminal zone. The terminal zones of the first type and the terminal zones of the second type are arranged on a front side of the semiconductor body.

In order to connect the cell strips in parallel, the terminal zones of the first type are electrically conductively connected to one another. Furthermore, the terminal zones of the second type are electrically conductively connected to one another.

For this purpose, a patterned first metallization layer, a patterned second metallization layer and a patterned third metallization layer are arranged successively on the front side, conductive lines being formed in each case in the first metallization layer and in the second metallization layer.

Conductive lines of the second metallization layer cross conductive lines of the first metallization layer at crossover locations and are electrically conductively connected at predetermined crossover locations to the crossed conductive lines of the first metallization layer for example by means of a plated-through hole (“via”).

On account of such an arrangement, the conductive lines of the first metallization layer and the conductive lines of the second metallization layer form together with the plated-through holes situated between them, a reticulated structure through which, unlike in the case of a semiconductor component in accordance with the prior art, a current flow is possible in two lateral directions of the semiconductor body, rather than only in one. The electrical resistance of the component is thus reduced as a result.

DESCRIPTION

In the figures—unless specified otherwise—identical reference symbols designate identical elements with the same meaning.

FIG. 3shows a perspective view of a section from the region of the active zone of a semiconductor component according to at least one embodiment of the invention.

The semiconductor component has a semiconductor body10extending in a first lateral direction x and in a second lateral direction y.

The semiconductor body10comprises DMOS cell strips91,92having a cell strip width d each having a drain terminal zone7and a source terminal zone8. The terminal zones7and8are arranged in a manner spaced apart from one another on a front side19of the semiconductor body10, said front side being parallel to the x-y plane, are formed in elongate fashion and run in the first lateral direction x. The drain terminal zones7and the source terminal zones8are furthermore arranged alternately successively in the second lateral direction y.

A first metallization layer1, a second metallization layer2and also a third metallization layer—not illustrated in this view for reasons of clarity—are arranged successively on the front side19of the semiconductor body10.

The first and the second metallization layer1,2are preferably formed from aluminum or an aluminum alloy, while the third metallization layer preferably comprises copper or a copper alloy.

The first metallization layer1comprises a multiplicity of conductive lines11,12,13,14having a width b1, which are formed in elongate fashion and run in the first lateral direction x and which are preferably spaced apart from one another at least above the active zone of the semiconductor component.

The second metallization layer2correspondingly has a multiplicity of conductive lines21,22,23,24,25,26,27,28,29,30,31having a width b2which are formed in elongate fashion and run in the second lateral direction y and are preferably spaced apart from one another at least above the active zone.

The conductive lines11,13of the first metallization layer1and the conductive lines21,23,25,27,29,31of the second metallization layer2are electrically conductively connected to the drain terminal zones7.

The conductive lines12,14of the first metallization layer1and the conductive lines22,24,26,28,30of the second metallization layer2are correspondingly electrically conductively connected to the source terminal zones8.

Within each of the metallization layers1,2the conductive lines11,13and21,23,25,27,29,31connected to the drain terminals7and the conductive lines12,14and22,24,26,28,30connected to the source terminals8are arranged alternately successively.

The conductive lines11to12,21to31are identified by letters “D” or “S”, depending on whether the relevant conductive line is electrically conductively connected to the drain terminal zones7(“D”) or to the source terminal zones8(“S”).

For producing the electrically conductive connections between the terminal zones7,8and the conductive lines11to14and21to31, plated-through holes are provided, of which only plated-through holes41,42and51are discernible in the present view.

The plated-through holes41are arranged above the drain terminal zones7between the front side19and the first metallization layer1and connect the drain terminal zones7to the conductive lines11,13of the first metallization layer1.

Furthermore, the plated-through holes42are arranged above the source terminal zones8between the front side19and the first metallization layer1and connect the source terminal zones8to the conductive lines12,14, of the first metallization layer1.

The plated-through holes51are arranged between the first and the second metallization layer1,2at crossover locations at which the conductive lines21,23,25,27,29,31of the second metallization layer2cross the conductive lines11,13of the first metallization layer1, and, at said crossover locations, connect the conductive lines11,13of the first metallization layer1to the conductive lines21,23,25,27,29,31of the second metallization layer2.

In a corresponding manner, plated-through holes—not discernible in the present view—are arranged between the first and the second metallization layer1,2at crossover locations at which the conductive lines22,24,26,28,30of the second metallization layer2cross the conductive lines12,14of the first metallization layer1, and, at said crossover locations connect the conductive lines12,14of the first metallization layer1to the conductive lines22,24,26,28,30of the second metallization layer2.

FIG. 4shows the arrangement in accordance withFIG. 3, the conductive lines23,26and31having been removed, as a result of which plated-through holes52are discernible, which are arranged between the conductive lines12,14of the first metallization layer1and the conductive lines22,24,26,28and30of the second metallization layer2and electrically conductively connect the conductive lines22,24,26,28,30to the conductive lines12,14at crossover locations.

FIG. 5shows the arrangement in accordance withFIG. 3in which plated-through holes61,62are arranged on the conductive lines21to31of the second metallization layer2, and serve for connecting the conductive lines21to31to sections (not illustrated) of the third metallization layer. In this case, the plated-through holes61are arranged on the conductive lines21,23,25,27,29,31connected to the drain terminal zones7and the plated-through holes62are arranged on the conductive lines22,24,26,28,30connected to the source terminal zones8.

FIG. 6shows a plan view of the arrangement in accordance withFIG. 5, which, however, additionally illustrates sections33,34of the third metallization layer above the second metallization layer2and above the plated-through holes61,62.

The section33of the third metallization layer is connected to the conductive lines21,23,25,27,29,31of the second metallization layer2by means of the plated-through holes61, the position of which is indicated by dashed lines.

Furthermore, the section34of the third metallization layer is connected to the conductive lines22,24,26,28,30of the second metallization layer2by means of the plated-through holes62, the position of which is likewise indicated by dashed lines.

In order to minimize the electrical resistance of the wiring formed from the conductive lines of the metallization layers and the plated-through holes, the sections33are provided with extensions33brunning parallel to one another and the sections34are provided with extensions34brunning parallel to one another, with the result that comblike structures arise. The extensions33bof the first section33and the extensions34bof the second section34intermesh in one another.

The extensions33bof the section33run in the first lateral direction x and are electrically connected to one another by means of partial sections33aof the section33which run in the second lateral direction y.

The extensions34bof the section34also run in the first lateral direction x. They are electrically connected to one another by means of partial sections34aof the section34which run in the second lateral direction y.

Since the electric currents flowing through the extensions33band34bcombine in the partial sections33aand34a, respectively, the width of the partial sections33aand34ais preferably chosen to be greater than the width of the extensions33band34b, respectively.

With a suitable arrangement of the extensions33band34b, said extensions may cross a plurality of the conductive lines21to31of the second metallization layer2and be electrically connected to one another at predetermined crossover locations by means of the plated-through holes61and62, respectively.

This results in an arrangement having a multiplicity of crossover and connection locations at which the first metallization layer is electrically connected to the second metallization layer and the second metallization layer is electrically connected to the third metallization layer. This multiplicity of connections gives rise to a reticulated structure so that a current between a specific location of a terminal zone and a specific location of that section of the third metallization layer which is connected to said terminal zone can be effected via a path which is generally shorter and has a lower resistance than the corresponding current path in an otherwise equivalent semiconductor component in accordance with the prior art.

A reticulated structure formed from the first, second and third metallization layers and the plated-through holes is thus responsible for the resistance-reducing property of the wiring.

What is crucial primarily is to realize, by means of the plated-through holes, a largest possible number of connection locations which are to be distributed as homogeneously as possible between the various metallization layers and terminal zones and also as homogeneously as possible between the conductive lines and sections of the three metallization layers that are connected to the terminal zones of the first type and of the second type.

In accordance with at least one suitable embodiment of the invention, an optimum current distribution and a lowest possible electrical resistance of the wiring can be achieved when double to quadruple, particularly preferably, triple, the width d of the cell strips91,92is chosen for the width b1of the conductive lines11,12,13,14, of the first metallization layer1and/or the width b2(seeFIG. 3) of the conductive lines21to31of the second metallization layer2.

In the present exemplary embodiment, the conductive lines11,12,13,14of the first metallization layer1and the conductive lines21to31of the second metallization layer2run perpendicular to one another. In principle, however, the conductive lines11,12,13,14of the first metallization layer1may form with the conductive lines21to31of the second metallization layer2an arbitrary angle different from 0° and from 180°, preferably an angle of 90°, or alternatively an angle of more than 0° and less than 90°. The only crucial factor is obtaining as many crossover locations as possible at which conductive lines of the second metallization layer2cross conductive lines of the first metallization layer1, conductive lines21to31of the second metallization layer2, if possible, advantageously crossing at least two conductive lines of the first metallization layer1and being connected to these crossed conductive lines.

FIG. 7shows a vertical section through the semiconductor component in accordance withFIG. 6in a sectional plane A illustrated inFIG. 6.

FIG. 8shows a vertical section through the semiconductor component in accordance withFIG. 6in a sectional plane B illustrated inFIG. 6.

FIGS. 7 and 8show the source terminal zones7and the drain terminal zones8, which are formed as doped zones in the semiconductor body10and extend as far as the front side19thereof.

The first metallization layer1, the second metallization layer2and the third metallization layer3are arranged successively on the front side19. The metallization layers1and2are patterned to form conductive lines, in which case from the conductive lines of the first metallization layer1, only the conductive line14is visible inFIG. 7and only the conductive line11is visible inFIG. 8.

FIG. 7shows a source terminal zone8connected to the conductive line14of the first metallization layer1by means of plated-through holes42and also to the conductive lines22,24,26,28,30of the second metallization layer2by means of further plated-through holes52.FIG. 8reveals that said conductive lines22,24,26,28,30of the second metallization layer2are electrically connected to the section34of the third metallization layer3by means of plated-through holes62.

FIG. 8furthermore shows a drain terminal zone7connected to the conductive line11of the first metallization layer1by means of plated-through holes41and also to the conductive lines21,23,25,27,29,31of the second metallization layer2by means of further plated-through holes51. Said conductive lines21,23,25,27,29,31of the second metallization layer2in turn are electrically connected to the section33of the third metallization layer3by means of plated-through holes61, which is revealed inFIG. 7.

An intermetal dielectric4is provided between the metallization layers1,2,3in order to increase the dielectric strength and mechanical stability of the semiconductor component.

Only two cell strips are illustrated by way of example in the section of a semiconductor component that is shown inFIGS. 3 to 8. In principle, however, a semiconductor component according to at least one embodiment of the invention may have not just two but any desired number of cell strips which are connected in parallel with one another in the manner described.

Furthermore, a power semiconductor component according to at least one embodiment of the invention may also have besides the first and second metallization layers even further metallization layers which are arranged between the semiconductor body and the third metallization layer and are interconnected with the metallization layers adjacent to them according to the interconnection of the first and second metallization layers. These further metallization layers preferably have the same dimensions and materials as the first and second metallization layers.

Moreover, besides the third metallization layer, one or more further metallization layers may also be provided which are arranged on the semiconductor body and are formed according to the third metallization layer with regard to their configuration, their materials and their electrical linking.

FIG. 9shows a plan view of a section of a semiconductor component according to at least one embodiment of the invention comprising an H bridge with four DMOS elements100,200,300and400. The DMOS elements100and200and also the DMOS elements300and400form a respective half-bridge.

The plan view corresponds to the arrangement in accordance withFIG. 6, the excerpt inFIG. 6showing a section with only one such DMOS element100,200,300and400.

The view shows the third metallization layer3, in particular. Said third metallization layer3comprises, for each of the four DMOS elements100,200,300and400, at least one section134,234,334and434, respectively, connected to the source terminal zones and also at least one section133,233,333and433, respectively, connected to the drain terminal zones.

The sections133,134,233,234,333,334,433,434have extensions133b,134b,233b,234b,333b,334b,433band434b, respectively which are connected to partial sections133a,134a,233a,234a,333a,334a,433aand434a, respectively, of the sections133,134,233,234,333,334,433and434, respectively. The partial sections133a,134a,233a,234a,333a,334a,433aand434aserve for taking up the current from their respective extensions133b,134b,233b,234b,333b,334b,433band434b, respectively.

The extensions133b,134b,233b,234b,333b,334b,433band434bassigned to the same partial section are arranged parallel to one another, run in the first lateral direction x and intermesh with the extensions134b,133b,234b,234b,334b,333b,434band433b, respectively, of the respective other partial section of the same DMOS element.

Since an H bridge semiconductor component is involved in the present case, two of the partial sections in each case are advantageously electrically conductively connected to one another by means of connecting sections512,523,534,541.

The partial sections133a,134a,233a,234a,333a,334a,433a,434aare formed in elongate fashion and extend in the second lateral direction y.

The width of the partial sections134a,233a,334aand433a, measured in the first lateral direction x, increases with increasing proximity to the connecting section512,523,534,541to which the relevant partial section134a,233a,334aand433ais connected, in order to be able to take up increasingly more current from the extensions134b,233b,334band433b, respectively. In this case, the width of the partial sections134a,233a,334aand433amay increase in particular monotonically or strictly monotonically with decreasing distance from the respective connecting section512,523,534,541.

LIST OF REFERENCE SYMBOLS

1First metallization layer2Second metallization layer3Third metallization layer4Intermetal dielectric7Terminal zone of the semiconductor body (drain)8Terminal zone of the semiconductor body (source)10Semiconductor body19Front side of the semiconductor body11-14Conductive line of the first metallization layer21-31Conductive line of the second metallization layer33Drain section of the third metallization layer33bExtension34Source section of the third metallization layer34aPartial section of the source section of the third metallization layer34bExtension41Plated-through hole between the semiconductor body and the first metallization layer (drain potential)42Plated-through hole between the semiconductor body and the first metallization layer (source potential)51Plated-through hole between the first and second metallization layers (drain potential)52Plated-through hole between the first and second metallization layers (source potential)61Plated-through hole between the second and third metallization layers (drain potential)62Plated-through hole between the second and third metallization layers (source potential)91,92Cell strips100First DMOS element133Drain section of the first DMOS element of the third metallization layer133aPartial section of the drain section of the first DMOS element of the third metallization layer133bExtension of the partial section of the drain section of the first DMOS element of the third metallization layer134Source section of the first DMOS element of the third metallization layer134aPartial section of the source section of the first DMOS element of the third metallization layer134bExtension of the partial section of the source section of the first DMOS element of the third metallization layer200Second DMOS element233Drain section of the second DMOS element of the third metallization layer233aPartial section of the drain section of the second DMOS element of the third metallization layer233bExtension of the partial section of the drain section of the second DMOS element of the third metallization layer234Source section of the second DMOS element of the third metallization layer234aPartial section of the source section of the second DMOS element of the third metallization layer234bExtension of the partial section of the source section of the second DMOS element of the third metallization layer300Third DMOS element333Drain section of the third DMOS element of the third metallization layer333aPartial section of the drain section of the third DMOS element of the third metallization layer333bExtension of the partial section of the drain section of the third DMOS element of the third metallization layer334Source section of the third DMOS element of the third metallization layer334aPartial section of the source section of the third DMOS element of the third metallization layer334bExtension of the partial section of the source section of the third DMOS element of the third metallization layer400Fourth DMOS element433Drain section of the fourth DMOS element of the third metallization layer433aPartial section of the drain section of the fourth DMOS element of the third metallization layer433bExtension of the partial section of the drain section of the fourth DMOS element of the third metallization layer434Source section of the fourth DMOS element of the third metallization layer434aPartial section of the source section of the fourth DMOS element of the third metallization layer434bExtension of the partial section of the source section of the fourth DMOS element of the third metallization layer512Connecting section523Connecting section534Connecting section541Connecting sectionb1Width of the conductive lines of the first metallization layerb2Width of the conductive lines of the second metallization layerd Cell strip width (pitch)x First lateral directiony Second lateral directionz Vertical directionA Sectional planeB Sectional planeD DrainS Source