Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 2011-140228, filed on Dec. 22, 2011 in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.

BACKGROUND

The present general inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present general inventive concept relates to a MOS capacitor having a large capacitance, a semiconductor device including the MOS capacitor, and a method of manufacturing the semiconductor device.

2. Description of the Related Art

Recently, according to high integration and large capacitance of a semiconductor device, an exterior component may be embedded therein. For example, in a case of a mobile display driving chip, a high-capacitance MOS capacitor for a decoupling capacitor or a boosting circuit may be embedded therein. The MOS capacitor may be required to have a high reliability and excellent electrical characteristics.

SUMMARY

The present general inventive concept provides semiconductor devices having a structure capable of preventing damage by plasma.

The present general inventive concept also provides methods of manufacturing the semiconductor device.

The foregoing and/or other features and utilities of the present general inventive concept may be achieved by providing a semiconductor device including a substrate including an active region having an isolated shape and a field region, a gate insulation layer provided on an upper surface of the active region of the substrate, a gate electrode provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region, and an impurity region provided under a surface of the active region that is exposed by the gate electrode.

In example embodiments, the impurity region may have an annular shape extending along the boundary of the gate electrode.

In example embodiments, the semiconductor device may be used as a MOS capacitor. The MOS capacitor may have an operation voltage of 3V to 7V.

In example embodiments, the gate insulation layer may have an equivalent oxide thickness of 50 Å to 200 Å.

In example embodiments, an isolation trench may be provided in the field region of the substrate and an isolation layer pattern may be provided within the isolation trench.

In example embodiments, the upper surface of the active region may include a first portion having a flat surface and a second portion having an angle of inclination in the boundary region adjacent to the field region.

In example embodiments, the gate insulation layer may have a relatively smaller thickness on the second portion of the active region than on the first portion of the active region.

In example embodiments, the semiconductor device may further include an insulation interlayer provided on the substrate to cover the gate electrode, first contact plugs penetrating the insulation interlayer to make contact with the impurity region, and second contact plugs electrically connected to the gate electrode.

In example embodiments, the first and second contact plugs may include a metal material.

In example embodiments, the semiconductor device may further include MOS transistors in another region of the substrate, such that MOS transistor may include a second gate insulation layer, a second gate electrode having a line width smaller than that of the gate electrode and extending across the active region and a second impurity region provided under a surface of the active region in both sides of the second gate electrode.

The gate electrode may be spaced apart from the boundary of the active region by 20 nm or more.

The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a method of manufacturing a semiconductor device, including performing an isolation process on a substrate to form an active region and a field region, forming a gate insulation layer on an upper surface of the active region of the substrate, forming a gate electrode on the gate insulation layer, such that the gate electrode is spaced apart from the boundary of the active region to cover the middle portion of the active region, and forming an impurity region under a surface of the active region that is exposed by the gate electrode.

In example embodiments, the gate insulation layer may have an equivalent oxide thickness of 50 Å to 200 Å.

In example embodiments, in order to perform the isolation process, the substrate may be partially etched to form an isolation trench, and an isolation layer pattern may be formed within the isolation trench.

The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a semiconductor device, including a substrate including an active region formed in a field region, a gate electrode formed over a center portion of the active region, an impurity region formed in the active region at portions exposed by the gate electrode, and a gate insulation layer formed between the gate electrode and the active region to cover the active region and the impurity region.

The respective end portions of the gate insulation layer may extend to respective outer portions of the impurity region.

The gate insulation layer may include a middle portion of uniform thickness, and a plurality of end portions having a decreasing thickness with respect to the middle portion.

An upper surface of the active region may include a first portion having a flat surface corresponding to the middle portion of the gate insulation layer and a second portion having an angle of inclination corresponding to the end portion of the gate insulation layer.

The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a semiconductor device, including a substrate including a plurality of active regions, a capacitor region, including a first impurity region adjacent to a first of the plurality of active regions, a first gate insulation layer disposed on an upper surface of the first of the plurality of active regions and the first impurity region, and a first gate electrode disposed on an upper surface of the first gate insulation layer and within a center portion of the first of the plurality of active regions.

The semiconductor device may further include a transistor region, including a second impurity region adjacent to a second of the plurality of active regions, a second gate insulation layer disposed on an upper surface of the second of the plurality of active regions and the second impurity region, and a second gate electrode disposed on an upper surface of the second gate insulation layer and within a center portion of the second of the plurality of active regions.

The capacitor region may further include a third impurity region adjacent to a third of the plurality of active regions, a third gate insulation layer disposed on an upper surface of the third of the plurality of active regions and the third impurity region, and another first gate electrode disposed on the upper surface of the third gate insulation layer and within a center portion of the third of the plurality of active regions.

The first impurity region may be N-type doped and the third impurity region may be P-type doped.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a plan view illustrating a metal-oxide semiconductor (MOS) capacitor in accordance with an example embodiment.FIG. 2Ais a cross-sectional view taken along the line I-I′ inFIG. 1.FIG. 2Bis a cross-sectional view taken along the line II-II′ inFIG. 1.FIG. 3is a perspective view illustrating the MOS capacitor inFIG. 1.

When processes having high density plasma are performed, a strong electric field may be generated between a substrate and a gate electrode that may cause serious damage to a gate insulation layer. The MOS capacitor ofFIG. 1may have a structure capable of preventing the damage to the gate insulation layer due to an effect of the high density plasma.

Referring toFIGS. 1 through 3, a MOS capacitor50may include a gate structure8formed on a substrate10, an impurity region22, a first insulation interlayer24, a second insulation interlayer28, and connection wirings26and30.

The substrate10may include a semiconductor material such as single-crystalline silicon, but is not limited thereto. The substrate10may include a field region6and an active region16.

An isolation trench12may be formed in the field region6of the substrate10. A sidewall of the isolation trench12may have a first angle of inclination with respect to a flat surface of the active region16. An upper surface of the active region16adjacent to the isolation trench12may have a rounded shape, and thus, a boundary of the upper surface of the active region16may have a second angle of inclination smaller than the first angle of inclination. Accordingly, the upper surface of the active region16may include a first portion (A) having a relatively flat surface and a second portion (B) having a relatively gentle angle of inclination in the boundary region adjacent to the isolation trench12.

An isolation layer pattern14may be provided in the isolation trench12. The isolation layer pattern14may include silicon oxide. The active region16may have an isolated shape. A MOS capacitor may be arranged in the isolated active region16.

The gate structure8may be provided on the active region16. The gate structure8may have a stacked structure of a gate insulation layer18and a gate electrode20.

The gate insulation layer18may include silicon oxide. The gate insulation layer18may have a first thickness on the first portion (A) of the active region16having a relatively flat surface and a second thickness smaller than the first thickness on the second portion (B) of the active region16having a relatively gentle angle of inclination.

As mentioned above, the MOS capacitor50may be optimized to prevent charging damage due to plasma.

When an equivalent oxide thickness of the gate insulation layer of the MOS capacitor50is over 200 angstroms (Å), the thickness of the gate insulation layer18may be relatively great so that the damage due to plasma may be insignificant to the gate insulation layer18, thereby protecting the substrate10. When an equivalent oxide thickness of the gate insulation layer18is less than 50 Å, most charges may penetrate the gate insulation layer18to move into the substrate10so that the damage due to plasma may be insignificant to the gate insulation layer18. On the other hand, when the gate insulation layer18of the MOS capacitor50has an equivalent oxide thickness of 50 Å to 200 Å, charges generated by plasma may cause damage to the gate insulation layer18so that the gate insulation layer18may break down or a leakage current may occur. Further, when the MOS capacitor50has an operation voltage of about 3V to 7V, the damage due to plasma may become more significant.

Thus, when the gate insulation layer18of the MOS capacitor50has an equivalent oxide thickness of 50 Å to 200 Å and an operation voltage of the MOS capacitor50ranges between about 3V to 7V, the MOS capacitor50may be most vulnerable to charges due to plasma. Therefore, the MOS capacitor50of the present embodiment may be more effective when the gate insulation layer18has an equivalent oxide thickness of 50 Å to 200 Å and an operation voltage ranges between about 3V to 7V.

The gate electrode20may be provided on the gate insulation layer18and may be arranged corresponding to the isolated active region16. In order to increase a capacitance of the MOS capacitor50, the gate electrode20may need to have a relatively wide surface area. When an upper surface of the gate electrode20has a rectangular shape, the width of the upper surface of the gate electrode20may be several micrometers (or several tens of micrometers) wide. Because the upper surface of the gate electrode20has a relatively wide surface area, the surface area of a conductor exposed by plasma may be relatively wide. Accordingly, the conductor may serve as an antenna for a current collector. As the surface area of the antenna is increased, damage by plasma may also be increased.

The gate electrode20may be formed not to extend to outer boundaries of the active region16. That is, the gate electrode20may be formed to be within the boundaries of the active region16. As such, the gate electrode20may cover a middle portion of the active region16, while not covering the entirety of the active region16. Accordingly, the gate electrode20may not overlap the isolation layer pattern14.

As illustrated inFIG. 1, in order to decrease charging damage by plasma, the gate electrode20may be formed to be spaced apart from the boundaries of the isolation layer pattern14by 20 nm or more (d). The gate electrode20may be formed within the first portion (A) corresponding to a flat surface of the active region16.

When the gate electrode20does not overlap the second portion (B) of the active region16, the portion of the gate insulation layer18that has a relatively small thickness within the second portion (B) may not function as an effective gate insulation layer in an operation of a MOS capacitor. Accordingly, other portions of the gate insulation layer18that function as an effective gate insulation layer may have an entirely uniform thickness.

The gate electrode20may include at least one of polysilicon, metal silicide, metal, etc., but is not limited thereto. The gate electrode20may have a single-layered structure or a multi-layered structure.

As mentioned above, the gate electrode20may be formed not to overlap the isolation layer pattern14, to thereby prevent charging damage due to high density plasma. Hereinafter, decreasing charging damages according to a relative position between the isolation layer pattern14and the gate electrode20will be explained in detail.

The impurity region22may be provided under the surface of the active region16that is exposed by the gate electrode20. Based on a conductive type of the MOS capacitor50, the impurity region22may be doped with N-type impurities or P-type impurities.

The gate electrode20may not extend across the entirety of the active region16. The impurity region22may not be separated by the gate electrode20to form a ring. Therefore, the impurity region22may have an annular shape extending along four sides of the gate electrode20.

The first insulation interlayer24may be provided on the substrate10to cover the gate electrode20. The first insulation interlayer24may include silicon oxide, but is not limited thereto.

The connection wirings26and30may include a first contact plug26and a second contact plug30.

The first contact plug26may penetrate the first insulation interlayer24to make contact with the impurity region22. The first contact plug26may include a barrier metal layer pattern and a metal layer pattern.

The second contact plug30may penetrate the second insulation interlayer28to make contact with the gate electrode20. A plurality of the first contact plugs26may be arranged in a row.

The second contact plug30may be provided on a periphery region of the upper surface of the gate electrode20. A plurality of the second contact plugs30may be arranged in a row.

Although it is not illustrated, a first wiring line may be provided to be electrically connected to the first contact plug26and a second wiring line may be provided to be electrically connected to the second contact plug30.

The boundary regions between the isolation layer pattern14and the active region16may have a tip shape such that an electric field is focused on the boundary regions. For example, while deposition and etching processes are performed using plasma, a strong electric field may be focused on the boundary regions having the tip shape between the isolation layer pattern14and the active region16. Further, the gate insulation layer18may have a relatively smaller thickness within the second portion (B) of the active region16adjacent to the isolation layer pattern14. Therefore, the gate insulation layer18disposed on the second portion (B) of the active region16may be damaged more severely than other portions, such as the first portion A, by the strong electric filed generated during a plasma process.

Referring toFIGS. 2A and 2B, the gate electrode20may not overlap the isolation layer pattern14. That is, the portion of the gate insulation layer18adjacent to the boundary of the isolation layer pattern14on which a strong electric field is focused, may not serve as a gate insulation layer in an operation of a MOS capacitor. Accordingly, the MOS capacitor50may be prevented from being damaged by a strong electric field generated during a plasma process.

Further, the gate insulation layer18formed on the second portion (B) of the active region16may not serve as an effective gate insulation layer of the MOS capacitor50. Accordingly, the gate insulation layer18may have a substantially uniform thickness over the entire active region16. Thus, the gate insulation layer18adjacent to the periphery region of the gate electrode20may not have a relatively smaller thickness, to thereby provide the MOS capacitor50having a high reliability and excellent electrical characteristics.

FIGS. 4 through 7are cross-sectional views illustrating a method of manufacturing the MOS capacitor50as illustrated inFIG. 1.

Referring toFIG. 4, a field region6of a substrate10may be selectively etched to form an isolation trench12. The isolation trench12may be filled up with an insulation material including silicon oxide to form an isolation layer pattern14. A sidewall of the isolation trench12and an upper surface of the active region16may form a first angle of inclination. The upper surface of the active region16adjacent to the isolation trench12may have a rounded shape, and thus, a boundary of the upper surface of the active region16may have a second angle of inclination smaller than the first angle of inclination. Accordingly, the upper surface of the active region16may include a first portion (A) having a relatively flat surface and a second portion (B) having a relatively gentle angle of inclination in the boundary region adjacent to the isolation trench12.

Referring toFIG. 5, a gate insulation layer18may be formed on the active region16of the substrate10. The gate insulation layer18may be formed by a thermal oxidation process. The gate insulation layer18may include silicon oxide. The gate insulation layer18may be formed to have an equivalent oxide thickness of 50 Å to 200 Å. When the gate insulation layer18is formed by a thermal oxidation process the second portion (B) of the active region16adjacent to the isolation layer pattern14may have a relative smaller thickness.

A gate electrode layer (not illustrated) may be formed on the gate insulation layer18. The gate electrode layer may include polysilicon, metal silicide, metal, etc., but is not limited thereto. The gate electrode layer may be formed to have a single-layered structure or a multi-layered structure.

A hard mask pattern (not illustrated) may be formed on the gate electrode layer, and then, the gate electrode layer may be patterned using the hard mask pattern an etching mask, to form a gate electrode20.

The gate electrode20may be formed not to extend to the boundaries of the active region16. The gate electrode20may be formed within the boundaries of the active region16. That is, the gate electrode20may not overlap the isolation layer pattern14.

For example, when the distance between the gate electrode20and the isolation layer pattern14is 20 nm or less, the gate electrode may be damaged while performing a following plasma process such as a plasma deposition process or a plasma etching process. Therefore, the gate electrode may be formed to be spaced apart from the isolation layer pattern by 20 nm or more. Additionally, the gate electrode20may be formed on the first portion having a flat surface of the active region16.

Referring toFIG. 6, impurities may be implanted into the substrate including the gate electrode20formed thereon to form an impurity region22. The impurity region22may be formed along respective sides of the gate electrode20to form a ring. When the gate electrode22is formed using polysilicon, the impurities may be implanted into the substrate as well as the gate electrode20.

Referring toFIG. 7, a first insulation interlayer24may be formed to cover the gate electrode20. The first insulation interlayer24may be partially etched to form first contact holes that expose an upper surface of the impurity region22. The first contact holes may be filled with a metal material to form first contact plugs26.

Then, a second insulation interlayer28may be formed on the first insulation interlayer24. The first insulation interlayer24and the second insulation interlayer28may be partially etched to form second contact holes that expose an upper surface of the gate electrode20. The second contact holes may be filled with a metal material to form a second contact plug30, as illustrated inFIG. 2A.

The etching processes of forming the first and second holes and the deposition processes of forming the first and second plugs may be performed using plasma. Additionally, sequential metal wiring processes may also be performed using plasma. As mentioned above, the gate electrode20may be formed not to overlap the isolation layer pattern14, to thereby prevent charging damage due to the generation of plasma.

FIG. 8is a plan view illustrating a semiconductor device in accordance with another example embodiment of the present general inventive concept,FIG. 9is a cross-sectional view illustrating the semiconductor device illustrated inFIG. 8.

Referring toFIGS. 8 and 9, the semiconductor device may include a MOS transistor150cand MOS capacitors150aand150b.

A substrate100may include a MOS transistor (MOS TR) region and a MOS capacitor (MOS CAP) region. An isolation trench102may be formed in a field region101of the substrate100. An isolation layer pattern104may be formed in the isolation trench102.

An N-type MOS capacitor150aand a P-type MOS capacitor150bmay be provided in the MOS CAP region of the substrate100.

The N-type capacitor150aand the P-type capacitor150bmay each have a layout and a stacked structure substantially the same as those of the MOS capacitor50ofFIG. 1. However, the N-type capacitor150amay include a first impurity region112ahaving N-type impurities and the P-type capacitor150bmay include a second impurity region112bhaving P-type impurities.

A first gate electrode110aof the N-type and P-type capacitors150a,150bmay be formed within the boundary of an active region106and may not overlap the isolation layer pattern104. The first impurity region112aand the second impurity region112bmay each have an annular shape extending along the boundary of the first gate electrode110a. A first gate insulation layer108aof the N-type and P-type capacitors150aand150b, respectively, may have an equivalent oxide thickness of 50 Å to 200 Å.

The MOS transistor150cmay be provided in the MOS TR region of the substrate100. The MOS transistor150cmay include a gate structure of a second gate insulation layer108band a second gate electrode110bformed on the second gate insulation layer108b, and a third impurity region112cin both sides of the gate structure.

The second gate insulation layer108bmay include the same material as the first gate insulation layer108aand may have the same thickness as the first gate insulation layer108a. For example, the first and second gate insulation layer108a,108bmay have an equivalent oxide thickness of 50 Å to 200 Å. The second gate electrode110bmay include a same material as the first gate electrode110aand may have a same thickness as the first gate electrode110a. The MOS transistor150cmay have a same operation voltage as the MOS capacitors150aand150b. For example, the MOS capacitors150aand150bmay have an operation voltage of about 3V to 7V.

The second gate electrode110bmay have a linear shape extending across the active region106. That is, the second gate electrode110bmay overlap the isolation layer pattern104. The third impurity regions112cmay be separated by the second gate electrode110b.

A line width of the second gate electrode110bmay be smaller than a line width of the first gate electrode110a. For example, the second gate electrode110bmay have a line width of several micrometers (or several tens of micrometers). The line width of the second gate electrode110band the surface area of the upper surface of the second gate electrode110bof the MOS transistor150cmay be relatively small as compared to the MOS capacitors150aand150b, respectively. Since the surface area of the second gate electrode110bfunctioning as an antenna is relatively small, an electric field generated between the substrate100and the second gate electrode110bduring a plasma process may be relatively small. Accordingly, even though the second gate electrode110boverlaps the isolation layer pattern104, damage by plasma may be minimized.

The third impurity region112cmay be doped with N-type impurities or P-type impurities. Referring toFIG. 8, the third impurity region112cmay be doped with N-type impurities.

A first insulation interlayer114may be provided on the substrate100to cover the first gate electrode110aand the second gate electrode110b. The first insulation interlayer114may include silicon oxide.

First contact plugs116amay be provided to penetrate the first insulation interlayer114to come in contact with the first impurity region112a. Second contact plugs116bmay be provided to penetrate the first insulation interlayer114to make contact with the second impurity region112b. The first and second contact plugs116aand116bmay each include a barrier metal layer pattern and a metal layer pattern.

A second insulation interlayer118may be provided on the first insulation interlayer114. Third contact plugs120amay be provided to penetrate the second insulation interlayer118to make contact with the first gate electrode110a. Fourth contact plugs120bmay be provided to penetrate the second insulation interlayer118to make contact with the second gate electrode110b. The third and fourth plugs120aand120bmay each include a barrier metal layer pattern and a metal layer pattern.

Although it is not illustrated, wirings may be provided to be electrically connected to the first and second contact plugs116aand116b, respectively, and wirings may be provided to be electrically connected to the third and fourth contact plugs120aand120b, respectively.

FIGS. 10 through 12are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated inFIGS. 8 and 9.

Referring toFIG. 10, a field region101of a substrate100may be partially etched to form an isolation trench102. The isolation trench102may be filled with an insulation material, such as silicon oxide, to form an isolation layer pattern104.

First gate insulation layer108aand second gate insulation layer108bmay be formed sequentially on the substrate100. The first and second gate insulation layers108aand108bmay each be formed using silicon oxide by a thermal oxidation process. The first and second gate insulation layers108aand108bmay each be formed to have an equivalent oxide thickness of 50 Å to 200 Å.

A gate electrode layer may be formed on the first and second gate insulation layers108aand108b. A hard mask pattern may be formed on the gate electrode layer, and then, the gate electrode layer may be patterned using the hard mask pattern as an etching mask to form a first gate electrode110ain the MOS CAP region and a second gate electrode110bin the MOS TR region.

The first gate electrode110amay be formed within boundaries of an active region106. The first gate electrode110amay be formed not to overlap the isolation layer pattern104.

The second gate electrode110bmay be formed to have a linear shape extending across the active region106. The second gate electrode110bmay overlap the isolation layer pattern104.

Referring toFIG. 11, an ion implantation mask (not illustrated) may be formed on the PMOS capacitor region to expose the MOS transistor region and the NMOS capacitor region. Then, N-type impurities may be implanted into under a surface of the substrate100to form first and third impurity regions112aand112c, respectively. The first impurity regions112amay have an annular shape extending along the boundary of the first gate electrode110a.

Then, an ion implantation mask may be formed on the MOS transistor region and the NMOS capacitor region to expose the PMOS capacitor region. P-type impurities may be implanted into under a surface of the substrate100to form a second impurity region112b. The second impurity region112bmay have an annular shape extend along the boundary of the first gate electrode110a.

Referring toFIG. 12, a first insulation interlayer114may be formed on the substrate100to cover the first and second gate electrodes110a,110b. The first insulation interlayer114may be partially etched to form first and second contact holes that expose the first and second impurity regions112aand112b, respectively. The first and second contact holes may be filled with a metal material to form a first contact plug116aand a second contact plug116b.

Then, as illustrated inFIGS. 9 and 10, a second insulation interlayer118may be formed on the first insulation interlayer114. The first insulation interlayer114and the second insulation interlayer may each be partially etched to form third and fourth contact holes that expose an upper surface of the first gate electrode110a. The third and fourth contact holes may be filled with a metal material to form a third contact plug120aand a fourth contact plug120b.

Thus, damage by plasma may be prevented to manufacture a semiconductor device having a high reliability.

FIG. 13is a plan view illustrating a MOS capacitor50ain accordance with yet another example embodiment.FIG. 14is a perspective view illustrating a portion of the MOS capacitor50aillustrated inFIG. 13.FIG. 14is an enlarged perspective view illustrating “C” portion inFIG. 13.

Referring toFIGS. 13 and 14, a MOS capacitor50amay include a gate structure formed on a substrate10, an impurity region22a, a first insulation interlayer24, a second insulation interlayer28, and connection wirings26and30.

The substrate10may include a semiconductor material such as single-crystalline silicon. The substrate10may include a field region6and an active region16. An isolation trench12amay be formed in the field region of the substrate10. An isolation layer pattern14amay be formed in an isolation trench12a. The active region16may have an isolated shape.

A gate structure8may have a stacked structure of a gate insulation layer18and a gate electrode20a. The gate electrode20amay have a linear shape extending across the active region16.

The active region16may have a first region and a second region. The first region of the active region16may overlap the gate electrode20a. The second region of the active region16may be exposed by the gate electrode20a, and may not overlap the gate electrode20a. The second regions of the active region16may be provided on the substrate in both sides of the gate electrode20a.

The boundary of the first region of the active region16may have a concave-convex shape. As illustrated inFIGS. 13 and 14, the boundary of the first region may have a concave portion and a convex portion that are arranged alternatively in correspondence with each other.

The boundary of the first region having a concave-convex shape may have a relatively longer distance compared to the boundary of the active region16having a linear shape. The boundary of the first region may face the boundary of the isolation layer pattern14a. Accordingly, the distance of the boundary of the isolation layer pattern14aoverlapping the gate electrode20amay be relatively increased.

The gate insulation layer18may include silicon oxide. The gate insulation layer18may have an equivalent oxide thickness of 50 Å to 200 Å. The MOS capacitor50amay have an operation voltage of about 3V to 7V. As explained in the embodiment ofFIG. 1, the gate insulation layer20amay have a relatively smaller thickness on a portion of the active region16adjacent to the isolation layer pattern14a.

The gate electrode20amay be provided on the gate insulation layer18to extend across the active region16to the boundary of the isolation layer pattern14a. As mentioned above, since the boundary of the first region of the active region16has a concave-convex shape, the distance of the boundary of the isolation layer pattern14aoverlapping the gate electrode20amay be relatively increased.

Referring toFIGS. 13 and 14, the overlapped portion between the gate electrode20aand the isolation layer pattern14amay be relatively increased, to prevent charging damage due to effects of a high density plasma process. Hereinafter, advantages of the present embodiment will be explained in detail.

The impurity region22amay be provided under a surface of the active region16exposed by the gate electrode20a. According to a conductive type of the MOS capacitor50a, the impurity region22amay be doped with N-type impurities or P-type impurities.

The first insulation interlayer24may be provided on the substrate10to cover the gate electrode20a. The first insulation interlayer24may include silicon oxide.

The connection wirings26and30may include a first contact plug26and a second contact plug30. The first contact plugs26may penetrate the first insulation interlayer24to make contact with the impurity region22a. The second contact plugs30may penetrate the second and first insulation interlayers28and24to make contact with the gate electrode20a.

Although it is not illustrated, a first wiring line may be provided to be electrically connected to the first contact plug26. A second wiring line may be provided to be electrically connected to the second contact plug.

As explained in the embodiment ofFIG. 1, an electric field may be focused on the boundary regions between the gate electrode20aand the isolation layer pattern14a. Accordingly, the boundary regions overlapped between the gate electrode20aand isolation layer pattern14amay be possibly damaged more severely than other portions by plasma.

Referring toFIGS. 13 and 14, the overlapped portion between the gate electrode20aand the isolation layer pattern14amay have a relatively long distance. Therefore, an electric field may be distributed uniformly over the overlapped portion between the gate electrode20aand the isolation layer pattern14a, not focused on any specific region. Accordingly, a strong electric field may be prevented from being generated and focused on the boundary region of the gate electrode20aduring a plasma process.

FIGS. 15 and 16are perspective views illustrating a method of manufacturing the MOS capacitor50aillustrated inFIGS. 13 and 14.

Referring toFIG. 15, a field region6of a substrate10may be partially etched to form an isolation trench12a.

As illustrated inFIG. 15, the boundary of the isolation trench12amay be formed to have a concave-convex shape. That is, the boundary of the isolation trench12amay have a concave portion and a convex portion arranged alternatively with correspondence to each other.

The isolation trench12amay be filled with an insulation material including silicon oxide to form an isolation layer pattern14a.

A gate insulation layer18may be formed on an active region16of the substrate10.

Referring toFIG. 10, a gate electrode layer (not illustrated) may be formed on the gate insulation layer18. A hard mask pattern (not illustrated) may be formed on the gate electrode layer, and then, the gate electrode layer may be patterned using the hard mask pattern as an etching mask to form a gate electrode20a.

The gate electrode20amay be formed to extend across the active region16. The gate electrode20amay be formed to be overlapped with the boundary of the isolation layer pattern14ahaving the concave-convex shape.

Processes the same as or similar to those explained with reference toFIGS. 5 and 6may be performed to form the MOS capacitor50ainFIGS. 13 and 14.

According to the above-mentioned processes, an electric field may be prevented from being focused on the boundary region of the gate electrode20aduring a plasma process, to thereby manufacture a semiconductor device having a high reliability.

FIG. 17is a plan view illustrating a semiconductor device in accordance with another example embodiment.

The semiconductor device ofFIG. 17is substantially the same as the embodiment as illustrated inFIG. 8, except for slight variations in a MOS capacitor.

Referring toFIG. 17, a semiconductor device may include a MOS transistor151cin a MOS TR region, a NMOS capacitor151ain a MOS CAP region and a PMOS capacitor151bin the MOS CAP region.

FIGS. 18 and 19are plan views illustrating a method of manufacturing the semiconductor device inFIGS. 16 and 17.

Referring toFIG. 18, a field region of a substrate may be partially etched to form an isolation trench. The isolation trench may be formed such that boundaries of a corresponding active region106aof a NMOS capacitor and a PMOS capacitor each have a concave-convex shape. The isolation trench may be filled with an insulation material including silicon oxide to form an isolation layer pattern.

Referring toFIG. 19, a gate insulation layer may be formed on the substrate. A gate electrode layer may be formed on the gate insulation layer.

A hard mask pattern may be formed on the gate electrode layer, and then, the gate electrode layer may be patterned using the hard mask pattern as an etching mask to form a first gate electrode111ain the MOS capacitor region and a second gate electrode111bin the MOS transistor region.

The first gate electrode111amay be formed to extend across the active region. The gate electrode111amay be formed to be overlapped with the boundary of the isolation layer pattern having the concave-convex shape.

Processes the same as or similar to those explained with reference toFIGS. 11 and 12may be performed on the substrate ofFIGS. 17 through 19. That is, impurities may be implanted into the substrate in both sides of the first gate electrode111aand the second gate electrode111bto form first, second and third impurity regions112a,112b, and112c, respectively. Following processes may be performed to form an insulation interlayer that covers the first gate electrode111a, the second gate electrode111b, the contact plug120a, and the contact plug120b, that penetrate the insulation interlayer. Thus, the semiconductor device inFIG. 17may be formed on the substrate.

According to the above-mentioned processes, an electric field may be prevented from being focused on the boundary region of the first gate electrode111aand the second gate electrode111bduring a plasma process, to thereby manufacture a semiconductor device having a high reliability.

The MOS capacitor according to an example embodiment of the present general inventive concept may be applied to a mobile display driving system.FIG. 20is a block diagram illustrating a display driving system including the MOS capacitor in accordance with an example embodiment of the present general inventive concept.

Referring toFIG. 20, a display driving system300may include a timing controller (T_CON)330, a scan driver340, a data driver310, a liquid crystal panel320and a charge pump350. The timing controller330may generate a control signal to control the scan driver340and the data driver310, and may receive an external image signal and transmit the image signal to the data driver310.

Examples of voltages required to drive a liquid crystal diode (LCD) may include a boosted voltage such as a source line driving voltage (AVDD) and a gate line high voltage (VGH) having a positive voltage higher than an external input voltage, a gate line low voltage (VGL) having a negative voltage smaller than a ground voltage (GND), etc., but are not limited thereto. The charge pump350may generate and provide a positively increased AVDD and VGH, and a negatively increased VGL to the scan driver340and the data driver310. The charge pump may include pumping capacitors to boost the input voltage. The pumping capacitor may be a MOS capacitor according to an example embodiment of the present general inventive concept.

The data driver310may receive AVDD from the charge pump350and supply a grey-scale voltage corresponding to the received image signal.

The scan driver340may receive VGH and VGL from the charge pump340to use an on-off voltage corresponding to thin film transistors.

As mentioned above, various semiconductor devices may include a MOS capacitor according to example embodiments. For example, the MOS capacitor according to example embodiments may be used in a mobile display driving IC (DDi). The mobile display driving IC may be applied to a mobile phone, a portable multimedia player (PMP), navigation device (e.g., a global positioning service), an ultra mobile PC (UMPC), etc., but is not limited thereto.

According to example embodiments of the present general inventive concept, a gate electrode of a semiconductor device may be arranged within a boundary of an active region of a substrate to cover a middle region of the active region. Accordingly, the gate electrode may not overlap a boundary of an isolation layer pattern, to thereby prevent a strong electric field from being focused on the boundary region of the isolation layer pattern during a plasma process. Thus, damage by plasma may be prevented during manufacture of a semiconductor device having a high reliability.