Load detecting device

A load detecting device for detecting whether a load is connected to a power supply device includes a no-load condition detector configured to detect a no-load condition using a sensing voltage having a frequency variant with a switching frequency of the power supply device, a circuit configured to acquire a signal having a waveform differing according to a connection or detachment between the load and the power supply device after the no-load condition is detected by the no-load condition detector, and a detachment detector configured to detect whether the load is detached by sensing the signal acquired by the circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from U.S. Patent Provisional Application No. 61/974,663, filed in the United States Patent & Trademark Offices (USPTO) on Apr. 3, 2014, and Korean Patent Application No. 10-2015-0047101, filed with the Korean Intellectual Property Office on Apr. 2, 2015, the entire contents of which are incorporated herein by reference.

BACKGROUND

Embodiments relate to a load detecting device and more particularly to a device for detecting whether a load is connected to or detached from a power supply device.

(b) Description of the Related Art

It is necessary to detect whether a load is connected or detached in a device (hereinafter referred to as a power supply device) electrically connected to the load and configured to supply power. For example, when power is supplied to the load through a port having polarity and into which a foreign material may be easily inserted, such as a universal serial bus (USB) cable, it is recognized that the load is connected when the foreign material is inserted in place of the load and therefore the power supply device may supply power. Then, excessive heat occurs in a port in which the foreign material and the power supply device are coupled and a fire may occur in the port due to the heat.

SUMMARY

A load detecting device capable of accurately detecting whether a power supply device is connected to a load is desired to be provided.

According to an embodiment, a load detecting device for detecting whether a load is connected to a power supply device includes: a no-load condition detector configured to detect a no-load condition using a sensing voltage having a frequency varying according to a switching frequency of the power supply device; a circuit configured to acquire a signal having a waveform differing according to a connection or detachment between the load and the power supply device after the no-load condition is detected by the no-load condition detector; and a detachment detector configured to detect whether the load is detached by sensing the signal acquired by the circuit.

The circuit may include a first transistor connected to a first node and configured to perform a switching operation based on an output of the no-load condition detector and a predetermined clock signal, a connection switch configured to transfer output power of the power supply device may be connected between the first node and the power supply device, and the first transistor and the connection switch may be alternately switched after the no-load condition is detected by the no-load condition detector.

The circuit may further include a clock generator configured to generate the clock signal; and a gate configured to receive an output of the no-load condition detector and the clock signal and perform a logical operation on the output of the no-load condition detector and the clock signal.

The detachment detector may detect a waveform of a voltage of the first node and detect that the load is detached when at least one of an increasing gradient or a decreasing gradient of the detected waveform is greater than or equal to a predetermined gradient.

The load detecting device may further include: an auxiliary power supply configured to generate auxiliary power using an output voltage of the power supply device, wherein, after the no-load condition is detected by the no-load condition detector, a signal having a waveform differing according to the connection or detachment between the load and the power supply device may increase or decrease based on an output voltage of the auxiliary power supply.

The circuit may include a first transistor connected to a first node and configured to perform a switching operation based on an output of the no-load condition detector and a predetermined clock signal, a connection switch configured to transfer output power of the power supply device may be connected between the first node and the power supply device, the output voltage of the auxiliary power supply may be supplied to the first node, and the first transistor may be switched and the connection switch may be turned off after the no-load condition is detected by the no-load condition detector.

The detachment detector may detect a waveform of a voltage of the first node and detect that the load is detached when at least one of an increasing gradient or a decreasing gradient of the detected waveform is greater than or equal to a predetermined gradient.

The load detecting device may further include: a charge pump configured to generate a voltage using an output voltage of the power supply device.

The circuit may include a first transistor connected to a first node and configured to perform a switching operation based on an output of the no-load condition detector and a predetermined clock signal; and a second transistor configured to supply an output voltage of the charge pump to the first node, and the first and second transistors may be alternately switched after the no-load condition is detected by the no-load condition detector.

The detachment detector may detect a waveform of a voltage of the first node and detect that the load is detached when at least one of an increasing gradient or a decreasing gradient of the detected waveform is greater than or equal to a predetermined gradient.

The circuit may include a current source configured to supply a current to a first node using an output voltage of the charge pump.

The detachment detector may detect that the load is detached when a voltage of the first node is less than a predetermined minimum voltage.

The circuit may include a current source configured to supply a current to a first node using an output voltage of the charge pump; a sensing resistor connected between an output port of the current source and the first node; a diode including an anode connected to the output port of the current source and a cathode connected to an input port of the charge pump; and a first transistor configured to perform a switching operation based on an output of the no-load condition detector and a predetermined clock signal and connected to the first node.

The detachment detector may detect that the load is detached when there is no voltage across the sensing resistor.

The load detecting device may further include: an auxiliary power supply configured to generate auxiliary power using an output voltage of the power supply device, wherein the circuit includes a current source configured to supply a current to a first node using an output voltage of the auxiliary power supply; a first transistor connected between an output port of the current source and a reference node and configured to perform a switching operation based on an output of the no-load condition detector and a predetermined clock signal; a sensing resistor connected between the reference node and a second node; and a third transistor connected between the reference node and the second node.

The detachment detector may detect that the load is detached when there is no voltage of the second node.

The circuit may include a current source configured to supply a current to a first node using an output voltage of the auxiliary power supply; a first transistor connected between an output port of the current source and a reference node and configured to perform a switching operation based on an output of the no-load condition detector and a predetermined clock signal; a sensing resistor connected between the first node and a second node; and a third transistor connected between the first node and the second node.

The detachment detector may detect that the load is detached when there is no voltage between the first node and the second node.

A connection switch configured to transfer output power of the power supply device may be connected between the first node and the power supply device, and the connection switch and the third transistor may be turned off after the no-load condition is detected by the no-load condition detector.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings to allow those of ordinary skill in the art to easily carry out the present invention. However, the embodiments of the invention may be implemented in various different forms, and the invention is not limited to the embodiments. To facilitate the entire understanding of the invention, the same reference symbols in the drawings denote the same elements, and elements which are not related to the description of the invention are omitted.

Throughout the specification, when it is described that one element is “coupled (or connected)” to the other element, the one element may be “directly coupled (or connected)” to the other element or “electrically coupled (or connected)” to the other element through a third element. Furthermore, when it is described that one element “includes (or comprises)” another element, it means that the one element does not exclude another element, but may further include other elements, unless otherwise described.

FIG. 1is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a first embodiment.

A power supply device1includes a load detecting device10, a capacitor CI, a primary-side winding W1, a secondary-side winding W2, a rectifying diode D1, a capacitor CO, a power switch M, two sensing resistors R1and R2, a switch control circuit20, a rectifying circuit30, and a connection switch SW.

Although the power supply device1illustrated inFIG. 1is implemented in a flyback type, the power supply device1may be implemented by other types of converters.

Also, in the embodiment, a transformer is used as a power transfer element for transferring power from an input to an output according to a switching operation of the power switch M. For example, a transformer implemented by the primary-side winding W1and the secondary-side winding W2insulated from the primary side is used as a power transfer means. However, the power transfer means connected to the power switch M is not limited thereto. An inductor may be used in place of the transformer according to a type of the converter applied to the power supply device1.

An alternating current (AC) input is rectified through the rectifying circuit30. The rectifying circuit30may be a full-bridge diode which is a full-wave rectifying circuit.

One electrode of the capacitor CI is connected to one end of the primary-side winding W1and the other electrode of the capacitor CI is connected to the primary-side ground. Noise of the rectified AC input may be filtered through the capacitor CI. A voltage input through the capacitor CI is referred to as an input voltage VI.

The input voltage VI is transferred to the one end of the primary-side winding W1and a drain of the power switch M is connected to the other end of the primary-side winding W1. A source of the power switch M is connected to the primary-side ground.

A gate voltage VG is input to a gate of the power switch M. The power switch M controls power to be transferred from the primary side to the secondary side. The primary side is insulated from the secondary side. Because the power switch M illustrated inFIG. 1is an n-channel transistor, a level of the gate voltage VG for turning on the power switch M is a high level and a level of the gate voltage VG for turning off the power switch M is a low level.

The secondary-side winding W2is electromagnetically connected to the primary-side winding W1. Two resistors R1and R2are connected in series between both ends of the secondary-side winding W2, an anode of the rectifying diode D1is connected to one end of the secondary-side winding W2, and a cathode of the rectifying diode D1is connected to one electrode of the capacitor CO and the source of the connection switch SW.

The voltage of the secondary-side winding W2is divided by the two resistors R1and R2; a sensing voltage VS is generated, and the sensing voltage VS may be used to sense a no-load condition. Although the two resistors R1and R2are illustrated inFIG. 1, the voltage of the secondary-side winding W2may be input as the sensing voltage VS without resistance when an output voltage VO is low.

When the power switch M is turned on, a primary-side current Ip increases and a current Ids flows through the power switch M. During a period in which the primary-side current Ip increases, energy is stored in a core by a flux induced by the primary-side winding W1. During this period, the rectifying diode D1is in a non-conductive state. When the power switch M is turned off and the rectifying diode D1is conducted, the energy stored in the core is transferred to the secondary-side winding W2and the current flows through the rectifying diode D1. In an OFF period of the power switch M, the primary-side current Ip decreases and no current Ids flows.

The connection switch SW externally transfers output power of the power supply device1. For example, when a load25is connected to the drain of the connection switch SW, the current is supplied from the power supply device1through the connection switch SW and an output voltage VO is supplied to the load25. The gate of the connection switch SW is connected to a connection pin P1of the load detecting device10. A gate voltage VG1is input to the gate of the connection switch SW through the connection pin P1. An output current IO to be supplied to the load25through the connection switch SW may be determined by a period in which the current flows through the rectifying diode D1and the current. The connection switch SW may be turned on during a period in which the load25is connected to the power supply device1and may be switched or turned off in a no-load condition in which the load25is not connected to the power supply device1.

InFIG. 1, because the connection switch SW is a p-channel transistor, the level of the gate voltage VG1for turning on the connection switch SW is the low level and the level of the gate voltage VG1for turning off the connection switch SW is the high level.

The load25may include an internal capacitor26, and, for example, may be a portable device.

According to an output voltage VO, the switch control circuit20may control a switching frequency or ON-duty of the power switch M. The switch control circuit20may acquire information about the output voltage VO in various ways. For example, a primary-side auxiliary winding (not illustrated) electromagnetically connected to the secondary-side winding W2may be used. The switch control circuit20may acquire information about the output voltage VO using a voltage across the auxiliary winding during an OFF period of the power switch M. Alternatively, the current flowing through a photo transistor forming an optocoupler along with a photodiode (not illustrated) connected to the output voltage VO may be used.

When the no-load condition is sensed according to the sensing voltage VS, the load detecting device10supplies power to the load25to sense a bus voltage VB generated in the load25and determines whether the load25is connected based on the sensed bus voltage VB. The load detecting device10includes a detachment detector12, a mode controller13, a clock generator14, a no-load condition detector15, an AND gate16, a transistor Q1, and a resistor R3. Although the AND gate is used as a logical operation unit in the embodiment, other logical operation units may be used according to input and output levels.

The no-load condition detector15detects a no-load condition using the sensing voltage VS. For example, when the no-load condition is reached, the switch control circuit20decreases the switching frequency of the power switch M or controls a switching operation according to a burst mode. The frequency of a voltage across the secondary-side winding W2differs according to the switching frequency of the power switch M or a cycle in which switching of the voltage across the secondary-side winding W2starts changes in the case of the burst mode. The no-load condition detector15may sense the load state by sensing the frequency or switching start cycle of the sensing voltage VS.

The no-load condition detector15may determine that the state is the no-load condition when the frequency of the sensing voltage VS is less than a predetermined threshold frequency or when the switching start cycle is longer than a predetermined threshold period. The threshold frequency may be set based on the frequency of the sensing voltage VS according to the switching frequency of the power switch M in the no-load condition, and the threshold period may be set based on the switching start cycle of the sensing voltage VS according to a burst mode cycle of the power switch M in the no-load condition. When the no-load condition is detected, the no-load condition detector15outputs a signal NL indicating the no-load condition. For example, a level of the signal NL indicating the no-load condition may be the high level.

The clock generator14generates a clock signal CLK having a predetermined frequency. The clock generator14may operate in order to detect whether the load is connected to the power supply device1. For example, the clock generator14starts an operation from the time at which the no-load condition detector15determines that the state is the no-load condition. That is, the clock generator14may operate when the high-level signal NL is input from the no-load condition detector15. In addition, the clock generator14may stop the operation when it is determined that the load is connected by the mode controller13.

The AND gate16generates the gate voltage VG1by performing an AND operation on the signal NL and the clock signal CLK. That is, the AND gate16generates a high-level gate voltage VG1when both of the two input signals NL and CLK have the high level and generates a low-level gate voltage VG1when at least one of the two input signals NL and CLK has the low level.

For example, when it is determined that the power supply device1is in the no-load condition, the signal NL has the high level and the AND gate16generates the high- or low-level gate voltage VG1according to the clock signal CLK. The AND gate16generates the high-level gate voltage VG1when the clock signal CLK has the high level and generates the low-level gate voltage VG1when the clock signal CLK has the low level.

A collector of the transistor Q1is connected to one end of the resistor R3, a base of the transistor Q1is connected to the AND gate16, and an emitter of the transistor Q1is connected to the secondary-side ground. Because the transistor Q1is implemented as an npn bipolar junction transistor (BJT), the transistor Q1is turned on when the gate voltage VG1, which is an output of the AND gate16, has the high level. The other end of the resistor R3is connected to a connection pin P2.

The detachment detector12receives the bus voltage VB through the connection pin P2and detects whether the load25is detached from the power supply device1by detecting a waveform of the bus voltage VB.

For example, the detachment detector12determines that the load25is not connected to, that is, detached from, the power supply device1when the waveform of the bus voltage VB increases at a predetermined first gradient or more or decreases at a predetermined second gradient or more. The detachment detector12transmits a signal indicating whether the load25is detached to the mode controller13.

The mode controller13generates and outputs a mode signal MDS according to whether the load25is connected according to the output of the detachment detector12. The mode controller13differently controls the level of the mode signal MDS according to whether the load25is connected.

When the load25is connected to the power supply device1, the load detecting device10turns on the connection switch SW according to the mode signal MDS of a first level. For example, the no-load condition detector15may generate the low-level signal NL by the mode signal MDS of the first level. Then, the gate voltage VG1, which is the output of the AND gate16, is fixed to the low level and the connection switch SW is maintained in the ON state.

When the load25is detached from the power supply device1, the load detecting device10maintains the load detection operation according to the mode signal MDS of a second level. The load detection operation means an operation of acquiring and sensing a signal having a waveform differing according to a connection or a detachment between the load and the power supply device.

For example, a voltage or current waveform, which rises and falls repeatedly at a predetermined frequency, is supplied to a specific node to which the load25and the power supply device1are connected and the voltage of the specific node may be sensed. Alternatively, the voltage of the specific node may be sensed after a predetermined voltage or current is supplied to the specific node. Alternatively, a resistor is connected between the load25and the power supply device1and a voltage across the resistor may be sensed.

In the first embodiment, a load detection operation includes an operation of alternately switching the connection switch SW and the transistor Q1according to the clock signal CLK, supplying a node N1with the signal waveform that rises and falls at the frequency according to the clock signal CLK, and sensing the bus voltage VB of the node N1. At an initial time of the load detection operation, the transistor Q1is turned on and the internal capacitor26may be discharged.

Specifically, the transistor Q1is turned on and the connection switch SW is turned off by the high-level gate voltage VG1, and the connection switch SW is turned on and the transistor Q1is turned off by the low-level gate voltage VG1. According to ON/OFF duty of the clock signal CLK, an ON/OFF period of each of the connection switch SW and the transistor Q1may be controlled.

If the load25is connected to the power supply device1, the internal capacitor26of the load25is charged with the output voltage VO during the ON period of the connection switch SW (or the OFF period of the transistor Q1). At this time, the increasing gradient of the bus voltage VB is determined according to a capacitance of the internal capacitor26of the load25. For example, the increasing gradient becomes more gradual when the capacitance of the internal capacitor26further increases. During the ON period of the transistor Q1(or the OFF period of the connection switch SW), the current flows from the load25to the secondary-side ground through the transistor Q1and the bus voltage VB decreases. At this time, the decreasing gradient of the bus voltage VB is determined according to the capacitance of the internal capacitor26of the load25. For example, the decreasing gradient becomes more gradual when the capacitance of the internal capacitor26further increases.

If the load25is detached from the power supply device1, the bus voltage VB steeply increases during the ON period of the connection switch SW and the bus voltage VB steeply decreases during the ON period of the transistor Q1. The above-described detachment detector12compares at least one of the rising gradient and the falling gradient of the bus voltage VB with a predetermined threshold value and determines that the load25is detached from the power supply device1when the at least one of the rising gradient and the falling gradient is greater than or equal to the threshold value.

The present invention is not limited to the above-described embodiment and various modifications are possible.

Hereinafter, the same reference symbols are used for the same elements and detailed description thereof will be omitted.

FIG. 2is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a second embodiment.

A load detecting device40according to the second embodiment further includes an auxiliary power supply41. It is necessary to satisfy a ripple spec for an input voltage to be applied to a load25, which is the output voltage of the power supply device. Although a connection switch SW has a characteristic of a low switching speed because the connection switch SW is for use in a large current, a switch used in the auxiliary power supply41may have a characteristic of a high switching frequency because the switch used in the auxiliary power supply41is for use in a small current. When a voltage is reduced to be less than or equal to a given lower threshold voltage which is a customer-desired ripple spec, it is possible to satisfy the ripple spec by rapidly operating the auxiliary power supply41.

Hereinafter, a redundant description of content described with reference toFIG. 1will be omitted.

The auxiliary power supply41generates auxiliary power using an output voltage VO and supplies the generated auxiliary power to the load25. The auxiliary power supply41may be connected to the load25through a connection pin P2. The auxiliary power supply41is activated according to a mode signal MDS.

When the load25is connected to the power supply device1, the auxiliary power supply41stops the operation by the mode signal MDS of a first level and the load detecting device40causes the connection switch SW to be turned on according to the mode signal MDS of the first level. When there is no power supplied from the auxiliary power supply41, the power to be supplied to the load25may be insufficient and therefore the power may be supplied to the load25by immediately turning on the connection switch SW.

When the load25is detached from the power supply device1, the auxiliary power supply41starts the operation by the mode signal MDS of a second level to generate power and the load detecting device40maintains a load detection operation according to the mode signal MDS of the second level.

In the second embodiment, the load detection operation includes an operation of switching a transistor Q1according to a clock signal CLK in a state in which the connection switch SW is turned off during a period in which the power is supplied from the auxiliary power supply41, supplying a node N1with a signal waveform which rises and falls at a frequency according to the clock signal CLK, and sensing a bus voltage VB of the node N1.

The signal waveform, which rises during an ON period of the connection switch SW and falls during the ON period of the transistor Q1based on the output voltage of the auxiliary power supply41, may be generated. Accordingly, the output voltage of the auxiliary power supply41may be an offset voltage for a voltage supplied to the load25.

FIG. 3is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a third embodiment.

In the third embodiment illustrated inFIG. 3, an auxiliary power supply51includes a charge pump52, and a load detecting device50further includes a transistor Q2and a resistor R4. In the third embodiment, a load detection operation includes an operation of alternately switching a transistor Q1and the transistor Q2according to a clock signal CLK during a period in which power is supplied from the auxiliary power supply51, supplying a node N1with a signal waveform which rises and falls at a frequency according to the clock signal CLK, and sensing a bus voltage VB of the node N1.

When a no-load condition detector15detects a no-load condition using a sensing voltage VS, a connection switch SW is turned off by a high-level output signal. In addition, when it is determined that a load25is connected to the power supply device1and a mode signal MDS of a first level is generated, the no-load condition detector15outputs a low-level signal NL and the connection switch SW is turned on.

A gate voltage VG1, which is an output of a NAND gate17, controls switching operations of the transistor Q2connected to the auxiliary power supply51and the transistor Q1. Although the NAND gate is used as a logical operation unit in the third embodiment, other logical operation units may be used according to input and output levels. Because the transistor Q2is a p-channel transistor as illustrated inFIG. 3, the transistor Q2is turned on by the low-level gate voltage VG1and turned off by the high-level gate voltage VG1. Accordingly, the transistors Q1and Q2are alternately switched.

The charge pump52generates a voltage of a predetermined level using an output voltage VO. When the load25is connected to the power supply device1, the output voltage of the charge pump52is supplied to the load25during the ON period of the transistor Q2. Then, an internal capacitor26is charged with an output voltage of the charge pump52and a bus voltage VB increases according to a predetermined increasing gradient. The resistor R4is connected between two capacitors to attenuate a peak current generated by a short-circuit between a capacitor C0and the internal capacitor26according to the switching operation of the transistor Q2. When the transistor Q2is turned off and the transistor Q1is turned on, the internal capacitor26is connected to the secondary-side ground and discharged and the bus voltage VB decreases according to a predetermined decreasing gradient.

As described above, the increasing gradient and the decreasing gradient are determined according to a capacitance of the internal capacitor26.

When the load25is detached from the power supply device1, the bus voltage VB steeply increases during the ON period of the transistor Q2and the bus voltage VB steeply decreases during the ON period of the transistor Q1. The detachment detector12may determine whether the detachment is made using at least one of the increasing gradient and the decreasing gradient of the bus voltage VB.

FIG. 4is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a fourth embodiment.

A load detecting device60according to the fourth embodiment illustrated inFIG. 4further includes a current source63without including the NAND gate17and the two transistors Q1and Q2described above. Even in the fourth embodiment, as in the above-described third embodiment, a connection switch SW performs a switching operation according to an output of a no-load condition detector15.

In the fourth embodiment, a load detection operation includes an operation of supplying a current of the current source63to a node N1during a period in which power is supplied from an auxiliary power supply61and sensing a bus voltage VB of the node N1.

The auxiliary power supply61includes a charge pump62. The charge pump62may be operated by a high-level signal NL. The charge pump62generates a voltage of a predetermined level using an output voltage VO. The current source63generates a current using a voltage supplied from the charge pump62. The auxiliary power supply61may operate only during a period in which the load detection operation is performed. A current of the current source63is output to the node N1through a connection pin P2.

The current source63supplies a minimum current necessary for a load. If a load25is detached from the power supply device1, the bus voltage VB is increased by large internal impedance coupled to the node N1. If the load25is connected, the impedance coupled to the node N1is decreased by the load and therefore the bus voltage VB decreases.

FIG. 5is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a fifth embodiment.

A load detecting device70according to the fifth embodiment illustrated inFIG. 5further includes a sensing resistor RS and a diode D2as compared with the fourth embodiment. Even in the fifth embodiment, a connection switch SW performs a switching operation according to an output of a no-load condition detector15. For example, when the no-load condition detector15detects a no-load condition using a sensing voltage VS, the connection switch SW is turned off by a high-level output signal. In addition, when it is determined that a load25is connected to the power supply device1and a mode signal MDS of a first level is generated, the no-load condition detector15outputs a low-level signal and the connection switch SW is turned on.

A gate voltage VG1, which is an output of a NAND gate17, controls a switching operation of a transistor Q1. Although the NAND gate is used as a logical operation unit in the fifth embodiment, other logical operation units may be used according to input and output levels.

In the fifth embodiment, a load detection operation includes an operation of switching the transistor Q1according to a clock signal CLK during a period in which power is supplied from an auxiliary power supply71, supplying a node N1with a signal waveform which rises and falls at a frequency according to the clock signal CLK, and sensing a bus voltage VB of the node N1.

The auxiliary power supply71includes a charge pump72. The charge pump72generates a predetermined level voltage using an output voltage VO.

A current source73generates a current using an output voltage of the charge pump72. The diode D2includes a cathode connected to an input port of the charge pump72, that is, the output voltage VO, and an anode connected to an output port of the current source73. When the load25is detached from the power supply device1, the current of the current source73flows to the charge pump72through the diode D2.

One end of the sensing resistor RS is connected to the output port of the current source73and the other end of the sensing resistor RS is connected to the node N1through a connection pin P2.

A detachment detector74detects whether the load25is detached from the power supply device1by sensing a voltage between one end and the other end of the sensing resistor RS.

When the load25is connected to the power supply device1, the transistor Q1is turned on by a high-level gate voltage VG1and an internal capacitor26is discharged through the transistor Q1. In addition, when the transistor Q1is turned off by a low-level gate voltage VG1, the current of the current source73is supplied to the internal capacitor26through the sensing resistor RS. That is, the current flows through the sensing resistor RS to generate a voltage. When the detachment detector74senses the voltage across the sensing resistor RS, it is possible to determine that the load25is connected to the power supply device1.

When the load25is detached from the power supply device1, the current of the current source73is free-wheeled to the charge pump72through the diode D2if the transistor Q1is turned off by the low-level gate voltage VG1. Accordingly, no current flows through the sensing resistor RS and there is no voltage across the sensing resistor RS. When there is no voltage across the sensing resistor RS, the detachment detector74may determine that the load25is detached from the power supply device1.

FIG. 6is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a sixth embodiment.

A load detecting device80illustrated inFIG. 6further includes an auxiliary switch Q3, and a sensing resistor RS1is connected between a load25and the secondary-side ground.

An auxiliary power supply81supplies a voltage to a current source82using an output voltage VO. The current source82generates a current using the output voltage of the auxiliary power supply81. The current of the current source82may be supplied to a load25through a connection pin P2.

In the sixth embodiment, a load detection operation includes an operation of sensing whether the current flows through the sensing resistor RS1to generate a voltage while switching a transistor Q1during a period in which power is supplied from the auxiliary power supply81.

The transistor Q1performs a switching operation at a predetermined frequency. As in the above-described embodiments, a gate voltage VG1based on a clock signal CLK is generated and the gate voltage VG1may be supplied to a base of the transistor Q1. A collector of the transistor Q1is connected to an output port of the current source82and an emitter of the transistor Q1is connected to the secondary-side ground and one end of the sensing resistor RS1through a connection pin P5. The secondary-side ground is only an example of a reference node and the embodiment is not limited thereto.

As a p-channel transistor, the transistor Q3is connected to two ends of the sensing resistor RS1through the connection pin P5and a connection pin P6. A signal NL is supplied to the gate of the transistor Q3. A source of the transistor Q3is connected to one end of the sensing resistor RS1through the connection pin P5and a drain of the transistor Q3is connected to the other end of the sensing resistor RS1through the connection pin P6.

A detachment detector83is connected to the other end of the sensing resistor RS1through the connection pin P6. The detachment detector83may detect whether the detachment is made by sensing a voltage across the sensing resistor RS1. The detachment detector83transmits a signal indicating whether the detachment is made to a mode controller13and the mode controller13determines a level of a mode signal MDS according to whether the detachment is made.

The auxiliary power supply81may maintain an operation according to the mode signal MDS of a second level and stop an operation according to the mode signal MDS of a first level. A no-load condition detector15may maintain the high-level signal NL according to the mode signal MDS of the second level and generate the low-level signal NL according to the mode signal MDS of the first level.

Before the transistor Q3is turned off by the signal NL which is an output of the no-load condition detector15, no current flows through the sensing resistor RS1because the two ends of the sensing resistor RS1are in a short-circuited state by the transistor Q3.

When the no-load condition detector15senses the no-load condition and the signal NL has the high level, the transistor Q3and a connection switch SW are turned off.

When the load25is connected to the power supply device1in the OFF states of the transistor Q3and the connection switch SW, the current of the current source82flows to the secondary-side ground through the transistor Q1during an ON period of the transistor Q1. Then, no current flows through the sensing resistor RS1and there is no voltage across the sensing resistor RS1. During the OFF period of the transistor Q1, the current of the current source82flows to the sensing resistor RS1through the load25and there is a voltage across the sensing resistor RS1. When the voltage across the sensing resistor RS1is sensed, the detachment detector83may detect that the load25is connected to the power supply device1.

When the load25is detached from the power supply device1in the OFF states of the transistor Q3and the connection switch SW, the current of the current source82flows to the secondary-side ground through the transistor Q1during the ON period of the transistor Q1. Then, no current flows through the sensing resistor RS1and there is no voltage across the sensing resistor RS1. Even in the OFF period of the transistor Q1, no current of the current source82flows through the sensing resistor RS1and there is no voltage across the sensing resistor RS1. When the voltage across the sensing resistor RS1is not sensed, the detachment detector83may detect that the load25is detached from the power supply device1.

FIG. 7is a diagram illustrating a load detecting device and a power supply device including the load detecting device according to a seventh embodiment.

Compared to the sixth embodiment illustrated inFIG. 6, a sensing resistor RS2and a transistor Q4are formed outside a load detecting device90. For example, one end of the sensing resistor RS2is connected to a drain of a connection switch SW and the other end of the sensing resistor RS2is connected to a load25. A signal NL is supplied to the connection switch SW and a gate of the transistor Q4, a source of the transistor Q4is connected to one end of the sensing resistor RS2, and a drain of the transistor Q4is connected to the other end of the sensing resistor RS2. Because two ends of the sensing resistor RS2are short-circuited during an ON period of the transistor Q4, there is no voltage across the resistor RS2.

In the seventh embodiment, a load detection operation includes an operation of sensing whether a current flows through the sensing resistor RS2to generate a voltage while switching a transistor Q1during a period in which power is supplied from an auxiliary power supply91.

A collector of the transistor Q1is connected to one end of the sensing resistor RS2through a connection pin P7, a gate voltage VG1is supplied to a base of the transistor Q1, and an emitter of the transistor Q1is connected to the secondary-side ground.

A detachment detector93is connected to the two ends of the sensing resistor RS2through the connection pin P7and a connection pin P8, a voltage across the sensing resistor RS2is sensed, and whether a detachment is made is detected according to the sensed voltage.

Because the other components and an inter-component connection relationship are the same as those of the sixth embodiment, detailed description thereof will be omitted.

When the load25is connected to the power supply device1in the OFF states of the transistor Q4and the connection switch SW, a current of a current source92flows to the secondary-side ground through the transistor Q1during the ON period of the transistor Q1. Then, no current flows through the sensing resistor RS2and there is no voltage across the sensing resistor RS2. During the OFF period of the transistor Q1, the current of the current source92flows to the load25through the sensing resistor RS2and a voltage across the sensing resistor RS2is generated. When the voltage across the sensing resistor RS2is sensed, the detachment detector93may detect that the load25is connected to the power supply device1.

When the load25is detached from the power supply device1in the OFF states of the transistor Q4and the connection switch SW, the current of the current source92flows to the secondary-side ground through the transistor Q1during the ON period of the transistor Q1. Then, no current flows through the sensing resistor RS2and there is no voltage across the sensing resistor RS2. Even in the OFF period of the transistor Q1, no current of the current source92flows through the sensing resistor RS2and there is no voltage across the sensing resistor RS2. When the voltage across the sensing resistor RS2is not sensed, the detachment detector93may detect that the load25is detached from the power supply device1.

According to various embodiments described above, it is possible to supply a voltage or current to a load using an auxiliary power supply when a no-load condition is detected and detect a connection or a detachment between the load and a power supply device using a voltage differing according to the connection or detachment of the load.

While embodiments of the invention have been described in detail above, the protection scope of the present invention is not limited to the foregoing embodiment, and it will be appreciated by those skilled in the art that various modifications and improvements using the basic concept of the invention defined in the appended claims are also included in the protection scope of the present invention.

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