Thin quad flat package with no leads (QFN) fabrication methods

Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Chinese Patent Application No. 200810034572.6, filed Mar. 13, 2008, naming Xiaochun Tan, Zhining Li, and Xiaolan Jiang as inventors.

BACKGROUND

The present invention relates to semiconductor package fabrication processes, and in particular, to thin quad flat package no leads (QFN) fabrication methods.

Consumers are demanding that devices such as cell phones, personal digital assistants, and music players be more reliable, compact, and affordable. For example, consumers are requiring that their cell phones be ultra thin and reliable. This requires thinner packaging and fewer defects. Additionally, these low profile applications may also require power electronics which require some level of thermal dissipation from the package. Of course, these package features need to be available at an affordable price.

Present QFN packages are fabricated using standard methods using a lead frame and a die attach pad. These methods limit the thinness of the device and may introduce additional process elements which may be an additional source of potential defects. These additional process elements may add additional cost to the package fabrication. Present QFN package heat dissipation may be limited and may require additional space for heat sinking on the printed circuit board or substrate.

Thus, there is a need for improved package assembly methods. The present invention solves these and other problems by providing chip scale package assembly methods.

SUMMARY

Embodiments of the present invention improve fabrication methods of packaging semiconductors. In one embodiment the present invention includes a method of packaging semiconductor devices. The method comprises the steps of molding a first surface of a wafer, sawing the wafer, attaching, molding an exposed area, and sawing into individual packaged devices The step of molding includes molding a first surface of a wafer with a first mold compound. This forms a continuous molded layer. The step of sawing includes sawing the wafer into individual semiconductor devices. Each individual semiconductor device has a molded layer corresponding to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to an adhesive surface. The step of molding includes molding an exposed area above the adhesive surface with a second mold compound. This forms a solid expanse of material. The step of sawing includes sawing the solid expanse of material. This forms a plurality of individual packaged semiconductor devices.

In one embodiment, the adhesive surface has a leadframe attached. The step of attaching the molded layer of the individual semiconductor devices to the adhesive surface includes placing the individual semiconductor devices within individual cavities of the leadframe.

In one embodiment, the method further comprises attaching a wire bond between a conductive pad of each individual semiconductor device to a conductive surface of a portion of a leadframe. The conductive surface corresponds to the conductive pad. The leadframe and the molded layer of the individual semiconductor device are attached to the adhesive surface.

In one embodiment, the step of molding an exposed area above the adhesive surface includes molding exposed areas of the individual semiconductor devices and a leadframe. A portion of the leadframe and a portion of the molded layer of the individual semiconductor devices are attached to the adhesive surface. Those portions remain unexposed.

In one embodiment, the first mold compound is the same as the second mold compound.

In one embodiment, portions of the second mold compound melds with portions of the first mold compound.

In one embodiment, portions of the second mold compound adheres with portions of the first mold compound.

In one embodiment, the invention includes a method of packaging semiconductor devices. The method comprises attaching a wafer, adding, sawing through the wafer, attaching devices, molding, and sawing to form a plurality of packaged semiconductor devices. The step of attaching includes attaching a first side of the wafer to a first adhesive surface. The step of adding includes adding a layer of metal to a second side of the wafer. The layer of metal forms a metalized surface of the wafer. The step of sawing the wafer includes sawing through a plurality of saw streets of the wafer. This establishes individual semiconductor devices. Each individual semiconductor device has a metalized surface corresponding to a portion of the metalized surface of the wafer. The step of attaching devices includes attaching the metalized surface of each of the individual semiconductor devices to a second adhesive surface. This makes the metalized surface unexposed. The step of molding includes molding an exposed area above the second adhesive surface. This forms a solid expanse of material. The step of sawing to form a plurality of packaged semiconductor devices includes sawing the solid expanse of material.

In one embodiment, the method further comprises sawing from the second side of the wafer. This establishes a notch. The step of adding the layer of metal forms a discernable channel within the notch. This provides surface details for alignment.

In one embodiment, the method further comprises sawing along the plurality of saw streets on the second side of a wafer prior to the sawing through the plurality of saw streets. This establishes a first cut having a height less than a thickness of the wafer.

In one embodiment, the step of sawing through the wafer creates a second cut having a width less than a width of the first cut. This forms a ledge.

In one embodiment, a leadframe tape includes the second adhesive surface. The leadframe tape has a leadframe attached. The step of attaching the metalized surface of each of the individual semiconductor devices to the second adhesive surface includes placing the individual semiconductor devices within individual cavities of the leadframe

In one embodiment, the step of molding the exposed area includes molding exposed portions of the individual semiconductor devices and the leadframe. A portion of the leadframe and the metal surface of the individual semiconductor devices are attached to the second adhesive surface. Therefore these portions remain unexposed.

In one embodiment, the method further comprises re-taping the individual semiconductor devices after the step of sawing through a plurality of saw streets. The step of re-taping includes attaching the metalized surface of the wafer to a third adhesive surface after the sawing through the plurality of saw streets, and removing the first adhesive surface from the first side of the wafer.

In one embodiment, the step of attaching the metalized surface of each of the individual semiconductor devices includes picking the individual semiconductor devices from the third adhesive surface.

Additional embodiments will be evident from the following detailed description and accompanying drawings, which provide a better understanding of the nature and advantages of the present invention.

DETAILED DESCRIPTION

FIG. 1illustrates a method100of fabricating a thin QFN package according to one embodiment of the present invention. The method100includes the steps of backside molding101, front side sawing102, die attaching103, wire bonding104, molding105, de-taping106, and singulation sawing107.

The step of backside molding101includes adhering a mold compound109to the back side of the wafer110. The molding101forms a continuous molded layer108having a thickness146.

The step of front side sawing102cuts through the front side137of the wafer110. This saws the wafer into individual devices (139,140, and113). Each individual semiconductor device (139,140, and113) has a molded layer (141,142, and114) corresponding to a portion of the continuous molded layer108. The wafer may be attached to a tape115during the step of front side sawing102, and the sawing may remove a portion of the tape115.

The step of die attaching103includes attaching molded layer141of individual semiconductor device117to adhesive surface143of tape121. Leadframe116may be already attached to the adhesive surface143of tape121. The attaching the molded layer141of individual semiconductor device117may include placing the individual semiconductor device117within individual cavity144of the leadframe116. Another individual semiconductor device119having a molded layer142attached to the adhesive surface143within an individual cavity145of the leadframe116is shown for clarity.

The step of wire bonding104includes connecting a wire122between a first conductive pad of individual semiconductor device117to a portion of a conductive surface of the leadframe116corresponding to the first conductive pad. Connected wires123,124, and125are shown for clarity. Wire123connects a second conductive pad of individual semiconductor device117to another portion of the conductive surface of the leadframe116corresponding to the second conductive pad. Wire124and125connect to the leadframe116and another individual die119in a manner similar to wire122and123.

The step of molding105includes molding an exposed area above the adhesive surface143using mold compound133. The molding105forms a solid expanse of material. The solid expanse of material may include mold compound109, mold compound133, the individual semiconductor devices (117,119), and portions of the leadframe116. The molding105of the exposed areas above the adhesive surface143may include molding exposed areas of the individual semiconductor devices (117and119) and leadframe116. A portion of the leadframe116and a portion of the molded layer (141and142) of the individual semiconductor devices (117and119) are attached to the adhesive surface143of tape121and are therefore unexposed. Mold compound109may be the same as mold compound133. Mold compound133may meld with previously exposed portions (126,127) of mold compound109of the molded layer of the individual semiconductor device117. Mold compound133may adhere with exposed portion of mold compound109of the individual semiconductor devices (117and199). Locations126and127are example regions around individual semiconductor device117in which the melding or the adhering may occur. Locations128and129are regions around another individual semiconductor device119and are shown for clarity.

The step of de-taping106removes the tape121used in the steps of die attaching103, wire bonding104, and molding105. This step may or may not be required prior to the step of singulation sawing107.

The step of singulation sawing107includes sawing through the wafer at location132between the devices (117and119) such that a plurality of chip scale packages are formed. Packaged device130and131are examples of the plurality of chip scale packages.

FIG. 2illustrates another method200of fabricating a QFN package according to another embodiment of the present invention. The method200includes the steps of taping201, first backside sawing202, adding back metal203, second backside sawing204, third backside sawing205, re-taping206, die attaching207, wire bonding208, molding209, singulation sawing210.

The step of taping201includes attaching the front side of wafer211to an adhesive surface of a tape212. The tape212may be referred to as wafer tape.

The step of first backside sawing202includes sawing from the backside241of the wafer211and establishing a notch216. Another notch217is shown for clarity. The sawing may be along a plurality of saw streets. The notch216adds surface detail to the backside of the wafer so that these details may be utilized for alignment after the step of adding back metal203. The notch216is a cut having a width and height large enough to add the surface detail required for alignment after the step of adding back metal203. The height and width of the required notch may be controlled by the attributes of the metallization such as thickness, for example.

The step of adding back metal203includes adding a layer of metal246(shown with angled hatched lines) to the backside241of the wafer211. The layer of metal246forms a metalized surface220of the wafer211. The layer of metal246forms a discernable channel221within notch216. Another discernable channel222within notch217is shown for clarity.

The step of second backside sawing204includes sawing along a plurality of saw streets on the back side241of the wafer211. The second backside sawing204results in a cut223which has a height and a width. Another cut224is shown for clarity. The cut223may be centered on notch216such that cut223replaces notch216. For example, cut223may have a larger width and height than notch216. Cut223may have a height that is greater than notch216but less than the thickness of the entire composite wafer, including metal, so that the cut does not penetrate the entire wafer. The step of second backside sawing204may include aligning the wafer according to the discernable channel (e.g.,221,222) prior to applying the saw to the wafer211.

The step of third backside sawing205includes sawing through a plurality of saw streets on the back side241of the wafer211. This establishes individual semiconductor devices (225,226, and227) each having a metalized surface corresponding to a portion of the metalized surface (218,219,220) of the wafer211. The step of third backside sawing205results in cut228. Another cut229is shown for clarity. Cut228may have a width narrower than the width of cut223. A difference of the widths of cut228and cut223may form a ledge241. This ledge241may aid in securing the semiconductor device226within the package after the step of molding209. The step of third backside sawing205may cut into a portion of the width of the wafer tape212, for example, but not through the entire tape thickness.

The step of re-taping206includes attaching the metalized surface (e.g.,218,219,220) to an adhesive surface of tape213and removing the wafer tape212from the front side of the wafer. This step provides corresponding spacing between individual semiconductor devices (225,226,227) on the wafer tape212and the individual semiconductor devices (227,226,225) on tape213in preparation for the step of die attaching207.

The step of die attaching207includes attaching the metalized surface219of the individual semiconductor device226to an adhesive surface242of tape214. The individual semiconductor device may have been picked from an array of devices attached to tape213and then placed onto tape214. Tape214may be a leadframe tape in which a leadframe230is already attached to the adhesive surface242. The attaching the metalized surface219of the individual semiconductor device226to an adhesive surface242includes placing the individual semiconductor device226within an individual cavity243of the leadframe230. Another individual semiconductor device227with a metalized surface220attached to the adhesive surface242in another individual cavity244of the leadframe230is shown for clarity.

The step of wire bonding208is similar to that discussed in step104of method100. Reference numbers117,119,122,123,124, and125ofFIG. 1correspond to reference numbers226,227,233,234,235, and236ofFIG. 2respectively.

The step of molding209includes molding an exposed area above the adhesive surface242using mold compound237. The molding209forms a solid expanse of material247. The solid expanse of material247may include mold compound237, portions of the layer of metal246, the individual semiconductor devices (e.g.,226,227), and portions of the leadframe230. The molding209the exposed areas above the adhesive surface242may include molding exposed areas of the individual semiconductor devices (226and227) and leadframe230. A portion of the leadframe230and a portion of the metalized surface (219and220) of the individual semiconductor devices (226and227) are attached to the adhesive surface242and are therefore unexposed. The ledge241may help to secure the individual semiconductor device226within the mold compound237.

The step of singulation saw210includes sawing through the wafer at location240between the devices (226and227) such that a plurality of chip scale packages are formed. Packaged device238and239are example elements of the plurality of chip scale packages.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. For example, switching systems and methods with current sensing according to the present invention may include some or all of the innovative features described above. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims.