Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same

Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0115384 filed on Sep. 8, 2017 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present disclosure generally relates to the field of electronics and, more particularly, a nonvolatile memory device and a method of fabricating the same.

Memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices may not retain data when a power is not provided, and nonvolatile memory devices may retain data even when the power is not provided.

In order to increase the degree of integration of nonvolatile memory devices, in particular, flash memory devices, three dimensional memory elements have been proposed. The three dimensional semiconductor memory elements may include vertically stacked memory cells and vertical channels.

SUMMARY

According to some embodiments of the present inventive concept, nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

According to some embodiments of the present inventive concept, methods of fabricating a nonvolatile memory device may include sequentially forming a lower insulating film and an etching stop film on a substrate and forming a mold structure on the etching stop film. The mold structure may include a plurality of sacrificial films and a plurality of interlayer insulating films stacked in an alternate sequence. The methods may also include forming a trench extending through the mold structure to expose the etching stop film, sequentially etching the etching stop film and the lower insulating film to form a channel hole, forming a channel structure in the channel hole, simultaneously removing the plurality of sacrificial films and the etching stop film to form a plurality of openings, and forming a plurality of conductive films in the plurality of openings, respectively. The channel hole may expose an upper surface of the substrate.

According to some embodiments of the present inventive concept, nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a first conductive film that is closest to the substrate among the plurality of conductive films. The first conductive film may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the first conductive film may have a profile different from a profile of a side of the lower portion of the first conductive film.

According to some embodiments of the present inventive concept, methods of fabricating a nonvolatile memory device may include sequentially forming a lower insulating film and an etching stop film on a substrate, and forming a mold structure on the etching stop film. The mold structure may include a plurality of sacrificial films and a plurality of interlayer insulating films stacked in an alternate sequence. The methods may also include forming a trench extending through the mold structure to expose the etching stop film, forming a dielectric film extending on an inner sidewall of the trench and on the etching stop film, sequentially etching a portion of the dielectric film on the etching stop film, the etching stop film, and the lower insulating film to form a channel hole, forming a dielectric material in the channel hole, simultaneously removing the plurality of sacrificial films and the etching stop film to form a plurality of openings, and forming a plurality of conductive films in the plurality of openings, respectively. The channel hole may expose an upper surface of the substrate.

According to some embodiments of the present inventive concept, methods of fabricating a nonvolatile memory device may include forming a stack including a plurality of gate lines and a plurality of insulating layers stacked in an alternate sequence on a substrate. The plurality of gate lines may include a lowermost gate line that is closest to the substrate among the plurality of gate lines. The lowermost gate line may include a lower portion and an upper portion sequentially stacked on the substrate, a side of the lower portion of the lowermost gate line has a first angle with respect to an upper surface of the substrate, and a side of the upper portion of the lowermost gate line has a second angle with respect to the upper surface of the substrate, and the first angle is greater than the second angle.

DETAILED DESCRIPTION

As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that “simultaneously removing” refers to removing in a same fabrication step, at approximately (but not necessarily exactly) the same time.

FIG. 1is a cross-sectional view of a nonvolatile memory device according to some embodiments of the present inventive concept.

FIG. 2is an enlarged view of the portion A ofFIG. 1.

Referring toFIGS. 1 and 2, a nonvolatile memory device according to some embodiments of the present inventive concept includes a substrate100, a lower insulating film102, interlayer insulating films108(e.g.,108a,108b,108c,108d,108e, and108f), conductive films180(e.g.,170,180a,180b,180c,180d,180e, and180f), a pad190, an upper insulating film196, a channel structure200, a conductive contact197, and a bit line198. The conductive films180are spaced apart from each other in a vertical direction (e.g., Y direction).

The substrate100may be, for example, bulk silicon or silicon-on-insulator (SOI). In some embodiments, the substrate100may be a silicon substrate or may include other materials, for example, silicon germanium, indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide and/or gallium antimonide. In some embodiments, the substrate100may include an epitaxial layer formed on a base substrate.

The lower insulating film102may be formed on the substrate100. The lower insulating film102may include, for example, but is not limited to, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The lower insulating film102may be directly adjacent to the substrate100. That is, no other component may be interposed between the lower insulating film102and the substrate100. In some embodiments, the lower insulating film102may directly contact the substrate100.

The conductive films180and the interlayer insulating films108may be alternately laminated on the lower insulating film102. In some embodiments, the conductive films180and the interlayer insulating films108may stacked on the lower insulating film102in an alternating sequence as illustrated inFIG. 1. The conductive films180may include a plurality of gate electrodes. In some embodiments, the conductive film180may include a selection line170(e.g., a gate selection line and a string selection line) and a plurality of gate lines180ato180eon the selection line170. In some embodiments, the selection line170is a gate selection line, and the selection line170will be referred to as a gate selection line. It, however, will be understood that the selection line170can be a string selection line.

The gate selection line170may be formed on the lower insulation film102. A gate selection signal for selecting a cell string included in the nonvolatile memory device of the present inventive concept may be applied to the gate selection line170.

The gate selection line170may include a conductive material and may include, for example, but is not limited to, at least one of tungsten, copper, metal silicide, doped silicon, or a conductive metal nitride film.

The gate selection line170may be directly adjacent to the lower insulating film102. In some embodiments, the gate selection line170may directly contact the lower insulating film102, as illustrated inFIG. 1. The gate selection line170of the conductive films180may be closest to the substrate100, and thus any one of the conductive films180may not be interposed between the gate selection line170and the substrate100or between the gate selection line170and the lower insulating film180. Therefore, the gate selection line170may be a gate electrode located at the lowermost level among the conductive films180.

Further, any one of the interlayer insulating films108may not be interposed between the gate selection line170and the lower insulating film102.

Referring toFIG. 2, the gate selection line170may include a lower part170aand an upper part170b. The lower part170aof the gate selection line170may directly abut on the lower insulating film102. The upper part170bof the gate selection line170may be on the upper part170aand may directly abut on the interlayer insulating film108a. In some embodiments, the lower part170aof the gate selection line170may directly contact an upper surface of the lower insulating film102, and the upper part170bof the gate selection line170may directly contact a lower surface of the lowermost interlayer insulating film108a, as illustrated inFIG. 2.

A lower sidewall171aof the gate selection line170may directly abut on the channel structure200and may directly abut on a dielectric film130as illustrated inFIG. 2. The lower sidewall171aof the gate selection line170may directly contact the channel structure200, specifically, a dielectric film130of the channel structure200, as illustrated inFIG. 2.

An upper sidewall171bof the gate selection line170may directly abut on the channel structure200and may directly abut on the dielectric film130as illustrated inFIG. 2. The upper sidewall171bof the gate selection line170may directly contact the channel structure200, specifically, the dielectric film130of the channel structure200, as illustrated inFIG. 2. In some embodiments, an upper portion of the channel structure200that contact the upper sidewall171bof the gate selection line170has a width in a horizontal direction (e.g., X direction) tapering toward the substrate100.

In some embodiments of the present inventive concept, the lower part170aand upper part170bof the gate selection line170may have different sidewall profiles.

In some embodiments, the lower sidewall171aof the gate selection line170may have a second angle θ2with respect to an upper surface100S of the substrate100, the upper sidewall171bof the gate selection line170may have a third angle θ3with respect to the upper surface100S of the substrate100, and the second angle θ2may be different from the third angle θ3, as illustrated inFIG. 2. In some embodiments, the second angle θ2may be greater than the third angle θ3. In some embodiments, the upper sidewall171bof the gate selection line170may have a negative slope, as illustrated inFIG. 2.

In some embodiments, the slope of the lower sidewall171aof the gate selection line170may be greater than the slope of the upper sidewall171bof the gate selection line170with respect to the upper surface100S of the substrate100.

In some embodiments, the second angle θ2is formed to be different from (e.g., greater than) the third angle θ3by processes of forming a channel hole CHH extending through the conductive films180and the interlayer insulating films108. Detailed description thereof will be provided later.

AlthoughFIGS. 1 and 2illustrate that the thickness of the gate selection line170is thicker than the thicknesses of the other gate lines180ato180e, the present inventive concept is not limited thereto. In some embodiments, the thickness of the gate selection line170may be the same as the thicknesses of other gate lines180ato180e.

In some embodiments, the sidewall of the lower insulating film102may have a first angle θ1with respect to the upper surface100S of the substrate100, and the first angle θ1may be the same as the third angle θ3.

The plurality of gate lines180ato180emay be laminated alternately with the plurality of interlayer insulating films108aon the gate selection line170.FIG. 1illustrates an example in which a total of six conductive films180including the gate selection line170and the gate lines180ato180eare formed, but this is merely an example, and thus the present inventive concept is not limited thereto. It will be understood that the number of laminated conductive films180may vary depending on the design of the nonvolatile memory device according to some embodiments of the present inventive concept.

The gate lines180ato180emay be the gate electrodes of the memory cell transistors included in the nonvolatile memory device according to some embodiments of the present inventive concept. In some embodiments, the uppermost gate line180eamong the laminated plurality of conductive films180may be a gate electrode of a string selection transistor, to which a string selection signal is provided.

The plurality of gate lines180athrough180emay include a conductive material and may include, for example, but is not limited to, at least one of tungsten, copper, metal silicide, doped silicon, or a conductive metal nitride film.

The interlayer insulating films108may be formed between the plurality of conductive films180to provide insulation between the plurality of conductive films180. The interlayer insulating film108may include, for example, but is not limited to, a silicon oxide film, a silicon nitride film, and/or a silicon oxynitride film.

InFIG. 1, the six interlayer insulating films108ato108fare illustrated to be laminated on the gate selection line170, but this is an example, and it will be understood that the number of laminated interlayer insulating films108ato108fmay vary depending on the design of the nonvolatile memory device according to some embodiments of the present inventive concept.

The channel hole CHH may be formed to extend through the interlayer insulating films108and the conductive films180that are alternately laminated (e.g., stacked). The channel hole CHH may expose the upper surface100S of the substrate100. As illustrated inFIG. 1, the channel hole CHH may have a shape in which the width decreases as it approaches the upper surface100S of the substrate. Therefore, a cross-section of the channel hole CHH may have an inverted trapezoidal shape.

The channel structure200may be in the channel hole CHH. In some embodiments, the channel structure200may fill the channel hole CHH. The channel structure200may include a dielectric film130, a channel film140, and a filling film150.

The dielectric film130may be formed along the inner sidewall of the channel hole CHH. The dielectric film130may extend along the inner sidewall of the channel hole CHH as illustrated inFIG. 10. The internal space of the channel hole CHH may be defined by the dielectric film130formed on the sidewalls of the channel hole CHH.

The dielectric film130may be formed along the profiles of the sidewalls of the conductive films180and the interlayer insulating film108that are alternately laminated. As described above, the profiles of the upper sidewall171band the lower sidewall171aof the gate selection line170may be different from each other. Therefore, the sidewall profiles of the dielectric film130formed on the upper sidewall171bof the gate selection line170and the dielectric film130formed on the lower sidewall171aof the gate selection line170may be different from each other.

The dielectric film130may include, for example, a tunnel film and/or a trap film. The tunnel film may be a portion through which charges pass and may be formed of, for example, a silicon oxide film or multiple layers (e.g., two layers) including a silicon oxide film and a silicon nitride film.

The trap film may be a portion in which charges that have passed through the tunnel film are stored and may include, for example, a nitride film and/or a high dielectric constant (high-k) film. The nitride film may include, for example, one or more of silicon nitride, silicon oxynitride, and/or hafnium oxynitride.

The channel film140may be formed on the dielectric film130. The channel film140may not completely fill the channel hole CHH and may expose the upper surface100S of the substrate. However, the present inventive concept is not limited thereto, and, in some embodiments, the channel film140may cover the upper surface100S of the substrate.

In some embodiments, the channel film140may include, for example, but is not limited to, polysilicon and/or amorphous silicon doped with impurities.

The filling film150may be on the channel film140. In some embodiments, the filling film150may completely fill the space defined by the upper surface100S of the substrate and the channel film140. The outer surface of the filling film150may be surrounded by the channel film140and the dielectric film130.

The filling film150may include an insulating material and may include, for example, silicon oxide.

The pad190may be formed in the channel hole CHH. The pad190may be formed on the dielectric film130, the channel film140, and the filling film150. The pad190may function as a drain node. The pad190may include, but is not limited to, at least one of, for example, doped semiconductors, metals, metal silicide, and metal nitrides.

The upper insulating film196may be formed on a laminated structure in which the interlayer insulating films108and the conductive films180are alternately laminated. The upper insulating film196may cover the upper surfaces of the uppermost interlayer insulating film108fand the pad190. The upper insulating film196may provide electrical insulation between the bit line198and the pad190.

The upper insulating film196may include, but is not limited to, an insulating material such as silicon oxide.

The conductive contact197may be formed in the upper insulating film196. The conductive contact197may penetrate through the upper insulating film196to electrically connect the pad190and the bit line198.

The conductive contact197may include a conductive material. The conductive contact197may include, but is not limited to, at least one of tungsten, copper, metal silicide, doped silicon, or a conductive metal nitride film.

FIG. 3is an enlarged view of the portion A ofFIG. 1according to some embodiments of the present inventive concept.

Referring toFIG. 3, the nonvolatile memory according to some embodiments of the present inventive concept may include a first recess R1and a second recess R2formed in the dielectric film130.

The first recess R1may be filled with the lower part170aof the gate selection line170, and the second recess R2may be filled with the upper part170bof the gate selection line170. Therefore, the side surface profiles of the lower part170aand the upper part170bof the gate selection line170may be formed along the inner wall profiles of the first recess R1and the second recess R2. Therefore, the side surface profile of the lower part170aof the gate selection line170may be different from the side surface profile of the upper part170bof the gate selection line170.

A first depth d1of the first recess R1and a second depth d2of the second recess R2may be different from each other, as illustrated inFIG. 3. In some embodiments, the first depth d1of the first recess R1may be larger (e.g., deeper) than the second depth d2of the second recess R2. It will be understood that the first depth d1and the second depth d2are depths in a horizontal direction that is parallel to the upper surface100S of the substrate100.

Since the first depth d1and the second depth d2of the first recess R1and the second recess R2are different from each other, the dielectric film130may include a protrusion176. The protrusion176may be a portion protruding to the outside of the dielectric film130from the first recess R1or the second recess R2. In some embodiments, the protrusion176may protrude into the gate selection line170as illustrated inFIG. 3.

The gate selection line170may include a concave portion166recessed toward the gate selection line170. The concave portion166may be located between the lower part170aand the upper part170bof the gate selection line170. The concave portion166may be a portion recessed toward the inside of the gate selection line170from the lower part170aor the upper part170bof the gate selection line170.

FIG. 4is a cross-sectional view of a nonvolatile memory device according to some embodiments of the present inventive concept, andFIG. 5is an enlarged view of the portion B ofFIG. 4.

Referring toFIGS. 4 and 5, the nonvolatile memory device according to some embodiments of the present inventive concept may include a channel structure200′ different from illustrated inFIGS. 1, 2 and 3. The description of the repeated parts will not be provided below, and differences will be mainly described.

A dielectric film130′ may not extend to the upper and lower sidewalls172band172aof the gate selection line170. Therefore, the sidewalls172aand172bof the gate selection line170may not be covered with the dielectric film130′. The sidewalls172aand172bof the gate selection line170may be covered with the channel film140. The sidewalls172aand172bof the gate selection line170may directly abut on the channel film140. The sidewalls172aand172bof the gate selection line170may directly contact the channel film140as illustrated inFIG. 4. Since the dielectric film130′ does not extend on the lower sidewall172aof the gate selection line170, the sidewalls of the lower insulating film102may also not be covered with the dielectric film130′. The sidewalls of the lower insulating film102may be covered with the channel film140. The sidewall of the lower insulating film102may directly abut on the channel film140. The sidewall of the lower insulating film102may directly contact the channel film140

In some embodiments, as illustrated inFIGS. 4 and 5, a second angle θ2′ of the lower sidewall172aof the gate selection line170with respect to the upper surface100S of the substrate100may be different from a third angle θ3′ of the upper sidewall172bof the gate selection line170with respect to the upper surface100S of the substrate100. In some embodiments, the second angle θ2′ may be greater than the third angle θ3′. In some embodiments, the sidewall of the lower insulating film102may have a first angle θ1′ with respect to the upper surface100S of the substrate100. In some embodiments, the second angle θ2may be greater than the third angle θ3. In some embodiments, the upper sidewall172bof the gate selection line170may have a negative slope, as illustrated inFIG. 5.

FIGS. 6 to 16are views illustrating a method of fabricating a nonvolatile memory device according to some embodiments of the present inventive concept.

Referring toFIG. 6, the lower insulating film102and an etching stop film104are formed on the substrate100.

The lower insulating film102may be provided by forming a material such as a silicon oxide film through processes, for example, a chemical vapor deposition (CVD), a plasma enhanced CVD (PECVD), and/or an atomic layer deposition (ALD).

The etching stop film104may include a material different from the lower insulating film102. The etching stop film104may include a material having an etching selectivity with respect to the lower insulating film102when a specific etching solution or a specific etching gas are used.

The etching stop film104may include an oxide film such as TiO, ZrO, AlO, WO, BeO, BO, MgO, HfO, YbO, CaO, PbO, SrO, BaO, and SnO, a carbide film such as C, SiC, and WC, and/or a nitride film such as TaN, AlN, and WN. In some embodiments, the etching stop film104may also include a mixture of one of the oxide film, the carbide film, and the nitride film, with silicon oxide and/or silicon nitride.

The etching stop film104may be formed on the lower insulating film102using a method such as CVD and ALD, but the present inventive concept is not limited thereto.

Referring toFIG. 7, a mold structure110in which sacrificial films106a,106b,106c,106d,106d,106f, and106fand interlayer insulating films108ato108f(collectively108) are alternately laminated (e.g., stacked) is formed on the etching stop film104. In some embodiments, the lowermost sacrificial film106amay be formed directly on the etching stop film104and thus may directly contact the etching stop film104as illustrated inFIG. 7.

The sacrificial films106ato106fmay include materials different from that of the etching stop film104. Specifically, the sacrificial films106ato106fmay include materials having an etching selectivity with respect to the etching stop film104when a specific etching solution or a specific etching gas are used. For example, the sacrificial films106ato106fmay include a silicon nitride film.

In some embodiments, interlayer insulating films108ato108fmay include the same material as the lower insulating film102. This is to leave only the lower insulating film102and the interlayer insulating films108by simultaneously removing the sacrificial films106ato106fand the etching stop film104later. However, the present inventive concept is not limited thereto, and the interlayer insulating films108may include a material which can have an etch selectivity with respect to the sacrificial films106ato106fand the etching stop film104. The interlayer insulating films108may include, for example, but is not limited to, a material such as a silicon oxide film.

The interlayer insulating films108and the etching stop film104may include different materials from each other. Specifically, the etching stop film104may include a material having an etching selectivity with respect to the lower insulating film102when a specific etching solution or a specific etching gas are used.

Referring toFIG. 8, the mold structure110is partially removed to form a trench120, and the top surface of the etching stop film104is exposed. The mold structure110may be partially removed using, for example, a dry etching process.

In the dry etching process for forming the trench120, the etching stop film104may have an etching selectivity with respect to the mold structure110. Therefore, the trench120does not penetrate to the upper surface100S of the substrate100and exposes the upper surface of the etching stop film104. The dry etching process may be stopped when the upper surface of the etching stop film104is exposed.

Referring toFIG. 9, the etching stop film104and the lower insulating film102exposed by the trench120are sequentially removed to form the channel hole CHH. The upper surface of the substrate100may be exposed by the channel hole CHH.

Removal of the etching stop film104may be etching of a portion of the etching stop film104exposed by the trench120using, for example, a dry etching process. Also, removal of the lower insulating film102may be performed using the same etching process as the process used to form the trench120. In some embodiments, the etching process of forming the trench120and the etching process of removing the lower insulating film102may use the same etchant.

As described with reference toFIGS. 8 and 9, in the method of fabricating the nonvolatile memory device according to some embodiments of the present inventive concept, to form channel hole CHH, the mold structure110may be etched until the etching stop film104is exposed and then the etching stop film104and the lower insulating film102are removed to expose the upper surface100S of the substrate100.

As the integration density of nonvolatile memory devices has recently increased, more memory cells are concentrated on a single vertical channel. Thus, the nonvolatile memory devices may include a channel hole CHH having a high aspect ratio and a channel structure200formed in the channel hole CHH having a high aspect ratio.

As appreciated by present inventors, an etching process of forming the channel holes CHHs having a deep depth may form recesses in the substrate100if the etching stop film104does not exist as the mold structure110is directly adjacent to the substrate100. Portions of the substrate100can be etched thereby forming recesses in the substrate100when the mold structure110is etched.

As appreciated by present inventors, it is difficult to control depths of the channel holes CHHs when the channel holes CHHs having high aspect ratios. Therefore, the depths of the recesses in the substrate100may be different from each other and may deteriorate performance of the device.

Methods of fabricating the nonvolatile memory device according to some embodiments of the present inventive concept, the mold structure110is etched until the etching stop film104is exposed, and then the etching stop film104and the lower insulating film102are removed through separate processes. Since removal of each of the etching stop film104and the lower insulating film102involve removal of the single film, it is relatively easy to control etch amount and variation of etch amounts.

That is, by using the etching stop film104and the lower insulating film102as a buffer film, the dispersion of the depths of the channel holes CHHs may be effectively controlled.

FIG. 10is an enlarged view of the portion A ofFIG. 9.

Referring toFIG. 10, the profile of the inner wall of the channel hole CHH is illustrated.

The inner wall of the channel hole CHH may be defined by the upper surface100S of the substrate100, and the sidewall of the lower insulating film102, the etching stop film104, the sacrificial films106ato106f, and the interlayer insulating films108. Therefore, the upper surface100S of the substrate100, and the sidewalls of the lower insulating film102, the etching stop film104, the sacrificial films106ato106f, and the interlayer insulating films108amay surround the channel hole CHH.

After the channel hole CHH is formed, the profile of the sidewall104S of the etching stop film104and the profile of the sidewall106S of the sacrificial films106ato106fmay be different from each other. In some embodiments, the sidewall104S of the etching stop film104may have a second angle θ2with respect to the upper surface100S of the substrate100, the sidewall106S of the lowermost sacrificial film106ahave a third angle θ3with respect to the upper surface100S of the substrate100, and the second angle θ2may be greater than the third angle θ3.

In some embodiments, the second angle θ2may be different from the third angle θ3because the etching stop film104and the lowermost sacrificial film106aare removed under different conditions (e.g., different etchants, and different temperatures).

That is, as described above, the etching stop film104may include an oxide film such as TiO and ZrO, a carbide film such as C and SiC, and/or a nitride film such as TaN and AlN, and the sacrificial film106amay include a silicon nitride film.

In some embodiments, reactivity of the etching stop film104against an etching solution or an etching gas may be higher than reactivity of the sacrificial film106aagainst the etching solution or etching gas. Accordingly, the second angle θ2may be greater than the third angle θ3.

FIG. 12is an enlarged view of the portion A ofFIG. 11. Referring toFIGS. 11 and 12, the dielectric film130, the channel film140, and the filling film150are formed in the channel hole CHH. In some embodiments, the dielectric film130, the channel film140, and the filling film150may fill the channel hole CHH.

The dielectric film130may be formed along the sidewall and the bottom surface of the channel hole CHH. In some embodiments, the dielectric film130on the bottom surface of the channel hole CHH may be removed by, for example, an etch-back process.

As described above, the dielectric film130may be formed of a plurality of films such as the tunnel film and the trap film. Formation of the dielectric film130including the plurality of films may include, for example, but is not limited to, any one of CVD, PECVD, and ALD processes.

The channel film140may be formed along the surface of the dielectric film130. In some embodiments, the dielectric film130is also formed on the upper surface100S of the substrate100, and a portion of the channel film140formed on the upper surface100S of the substrate100may be removed by, for example, an etch-back process.

The channel film140may be formed using, for example, polysilicon and/or amorphous silicon doped with impurities.

The filling film150may be formed in the channel hole CHH. In some embodiments, the filling film150may completely fill the channel hole CHH. The outer surface of the filling film150may be surrounded by the dielectric film130and the channel film140.

The filling film150may be formed of, for example, but is not limited to, a material such as a silicon oxide layer formed using one of CVD, PECVD, and ALD processes.

The channel structure200may be formed by forming the dielectric film130, the channel film140, and the filling film150. In some embodiments, the channel structure200may fill the channel hole CHH and may extend through the mold structure110.

FIG. 14is an enlarged view of the portion A ofFIG. 13. Referring toFIGS. 13 and 14, the sacrificial films106ato106fand the etching stop film104are removed to form a space165between the lower insulating film102and the lowermost interlayer insulating film108a, and spaces160between two adjacent ones the plurality of interlayer insulating films108.

The sacrificial films106ato106fand the etching stop film104may be removed by the same process. Therefore, the sacrificial films106ato106fand the etching stop film104may be simultaneously removed. Removal of the sacrificial films106ato106fand the etching stop film104may be performed using, for example, phosphoric acid, sulfuric acid, hydrochloric acid, or a mixed solution thereof.

After the etching stop film104and the sacrificial films106ato106fare removed, the channel structure200has a horizontal sectional area having a circle shape, and the interlayer insulating films108may be spaced apart from each other in a vertical direction, which is perpendicular to the upper surface100S of the substrate100. The channel structure200may extend through the interlayer insulating films108. Therefore, the interlayer insulating films108ato108fmay be supported by the channel structure200.

Referring toFIG. 15, a conductive films180may be formed in the spaces160and165formed by removing the sacrificial films106ato106fand the etching stop film104.

The conductive film180may include a gate selection line170formed directly adjacent to the lower insulating film102, and a plurality of gate lines180ato180eformed on the gate selection line170.

The gate selection line170is formed to fill the space165formed by removal of both the etching stop film104and the sacrificial film106a. Therefore, the gate selection line170may directly abut on the lower insulating film102. The gate selection line170may directly contact an upper surface of the lower insulating film102.

The gate lines180ato180eare formed to fill the spaces160, respectively, formed by removal of the sacrificial films106bto106f.

In summary, the etching stop film104and the lowermost sacrificial film106amay be replaced with the gate selection line170, and the sacrificial films106bto106fmay be replaced with the gate lines180ato180e, respectively.

The gate selection line170and the gate line180ato180emay be formed simultaneously. Specifically, the gate selection line170and the gate lines180ato180emay be formed by forming a conductive material using processes such as CVD, PECVD, and ALD.

The gate selection line170may completely fill the space165. Therefore, the sidewalls of the gate selection line170may have the same profile as the profiles of the sidewall104S of the etching stop film and the sidewall106S of the sacrificial film.

That is, as described above, the second angle θ2of the lower sidewall171aof the gate selection line170with respect to the upper surface100S of the substrate100may be different from the third angle θ3of the upper sidewall171bof the gate selection line170with respect to the upper surface100S of the substrate100.

Referring toFIG. 16, a upper portion of the channel structure200is removed by, for example, an etch-back process to form a trench195, and a pad190filling the trench195is formed.

The pad190may be formed in the channel hole CHH to cover the dielectric film130, the channel film140, and the filling film150. The pad190may include, for example, but is not limited to, at least one of doped semiconductors, metals, metal silicide, and metal nitrides.

Referring again toFIG. 1, the upper insulating film196is formed to cover the pad190, and a bit line198electrically connected to the conductive contact197is formed on the upper insulating film196.

FIGS. 17 to 18are views illustrating a method of fabricating the nonvolatile memory device illustrated inFIG. 3.

Referring toFIGS. 17 and 18illustrate a removal process of the etching stop film104and the lowermost sacrificial film106a. In some embodiments, the etching stop film104may be removed faster than the sacrificial films106athrough106f. That is, in an wet etching process of removing the etching stop film104and the sacrificial films106ato106f, the sacrificial films106ato106fmay have an etching selectivity with respect to the etching stop film104.

As a result, the etching stop film104may be etched faster than the lowermost sacrificial film106a. Subsequently, the outer wall of the dielectric film130is exposed to the etching solution E by the removal of the etching stop film104, and the outer wall of the dielectric film130may be etched. A first recess R1may be formed at the location of the dielectric film130which is exposed by etching the etching stop film104and is etched after the etching stop film104is etched.

In some embodiments, after etching of the lowermost sacrificial film106ais completed, etching of the outer wall of the dielectric film130proceeds to some degree, and the second recess R2may be formed in the dielectric film130, as illustrated inFIG. 18. That is, the first recess R1is formed on the outer wall of the dielectric film130which the etching stop film104contacted, and the second recess R2is formed on the outer wall of the dielectric film130which the sacrificial film106acontacted.

In some embodiments, the first depth d1of the first recess R1and the second depth d2of the second recess R2may be different from each other. Specifically, the first depth d1of the first recess R1may be larger (e.g., deeper) than the second depth d2of the second recess R2.

This is because the lowermost sacrificial film106ahas an etching selectivity with respect to the etching stop film104in the wet etching process for removing the lowermost sacrificial film106aand the etching stop film104as described above. The first recess R1exposed to the etching solution E for a longer time due to etching of the etching stop film104faster than the sacrificial film106amay be deeper than the second recess R2.

The dielectric film130may include a concave portion166between the first recess R1and the second recess R2.

Thereafter, as illustrated inFIG. 3, a gate selection line170which fills the first recess R1and the second recess R2is formed. After the gate selection line170is formed, the process similar to that illustrated inFIG. 16will be performed.

FIGS. 19 to 25are views illustrating a method of fabricating a nonvolatile memory device according to some embodiments of the present inventive concept. Since processes performed beforeFIG. 19are the same as or similar to the processes illustrated inFIGS. 6 to 8, those processes will not be described again.

Referring toFIG. 19, the dielectric film130is formed in the trench120. The dielectric film130may be formed along the sidewalls and bottom surface of the trench120. As described above, the dielectric film130may be formed of the plurality of films such as the tunnel film and the trap film. Formation of the dielectric film130including the plurality of films may include, for example, but is not limited to, any one of CVD, PECVD, and ALD processes.

The dielectric film130may not completely fill the inside of the trench120.

Referring toFIG. 20, the dielectric film130, the etching stop film104, and the lower insulating film102are removed to form the channel hole CHH. The upper surface of the substrate100may be exposed by the channel hole CHH.

The dielectric film130may be removed by an etch-back process. Through the above processes, a portion of the dielectric film130extending on the sidewall of the mold structure110may remain, and only a portion of the dielectric film130on the bottom surface of the trench120may be removed.

Removal of the etching stop film104may be etching of a portion of the etching stop film104exposed by the trench120using, for example, a dry etching process using etching gases. Also, removal of the lower insulating film102may use the same etching process (e.g., the same etchants) as the processes of forming the trench120described above.

Referring toFIG. 21, a channel film140and a filling film150are formed in the channel hole CHH. In some embodiments, the channel film140and the filling film150may fill the channel hole CHH.

The channel film140may be formed along a surface of the dielectric film130, and sidewalls of the etching stop film104and the lower insulating film102.

The sidewall of the etching stop film104may directly contact the channel film140. Unlike the aforementioned embodiment, the dielectric film130is not formed between the sidewall of the etching stop film104and the channel film140.

Further, the sidewall of the lower insulating film102may directly contact the channel film140. Unlike the aforementioned embodiment, the dielectric film130is not formed between the sidewall of the lower insulating film102and the channel film140.

In some embodiments, the dielectric film130is also formed on the upper surface100S of the substrate, and a portion of the channel film140formed on the upper surface100S of the substrate may be removed by an etch-back process.

The channel film140may be formed using, for example, polysilicon or amorphous silicon doped with impurities.

The filling film150may be formed in the channel hole CHH. In some embodiments, the filling film150may be formed to completely fill the channel hole CHH. The outer surface of the filling film150may be surrounded by the dielectric film130and the channel film140.

The filling film150may be formed of, for example, but is not limited to, a material such as a silicon oxide layer formed by one of CVD, PECVD, and ALD processes.

By forming the dielectric film130, the channel film140, and the filling film150, the vertical channel structure200may be formed. The vertical channel structure200may fill the inside of the channel hole CHH and may pass through the mold structure110.

FIG. 23is an enlarged view of the portion B ofFIG. 22. Referring toFIGS. 22 and 23, the sacrificial films106ato106fand the etching stop film104are removed to form a space165between the lower insulating film102and the lowermost interlayer insulating film108a, and spaces160between two adjacent ones of the plurality of interlayer insulating films108.

The sacrificial films106ato106fand the etching stop film104may be removed by the same process. Therefore, the sacrificial films106ato106fand the etching stop film104may be simultaneously removed. Removal of the sacrificial films106ato106fand the etching stop film104may use phosphoric acid, sulfuric acid, hydrochloric acid, or a mixture thereof.

While the sacrificial films106ato106fbeing removed, portions of the dielectric film130being in contact with the sidewalls of the sacrificial films106ato106fmay also be partially removed. Further, in some embodiments, While the sacrificial films106ato106fbeing removed, a portion of the dielectric film130contacting the lowermost sacrificial films106amay be removed.

As illustrated inFIG. 23, the dielectric film130does not extend to the upper surface of the substrate100. Therefore, the outer sidewalls173aand173bof the channel film140may be exposed by removal of the etching stop film104. The outer sidewalls173aand173bof the channel film may define the space165together with the insulating films108aand102.

Referring toFIGS. 24 and 25, conductive films180are formed in the spaces160and165formed by removing the sacrificial films106ato106fand the etching stop film104.

The conductive film180may include the gate selection line170formed adjacent to the lower insulating film102, and a plurality of gate lines180ato180eformed on the gate selection line170.

The gate selection line170is formed to fill the space165formed by the removal of both the etching stop film104and the sacrificial film106a. Therefore, the gate selection line170may directly abut on the lower insulating film102. The gate selection line170may directly contact an upper surface of the lower insulating film102as illustrated inFIG. 24.

The sidewalls172aand172bof the gate selection line170may not be covered with the dielectric film130. The sidewalls172aand172bof the gate selection line170may be covered with the channel film140. The sidewalls172aand172bof the gate selection line170may directly abut on the channel film140. In some embodiments, the sidewalls172aand172bof the gate selection line170may directly contact the channel film140as illustrated inFIG. 24.

The gate lines180ato180eare formed to fill the space160formed by the removal of the remaining sacrificial films106bto106f.

The gate selection line170and the gate line180ato180emay be formed at the same time. Specifically, the gate selection line170and the gate lines180ato180emay be formed of the conductive material by processes such as CVD, PECVD, and ALD.

The gate selection line170may completely fill the space165. Therefore, the sidewall of the gate selection line170may have the same profile as the profiles of the sidewall104S of the etching stop film104and the sidewall106S of the lowermost sacrificial film106a.

That is, as described above with respect toFIG. 5, the lower sidewall172aof the gate selection line170may have the second angle θ2with respect to the upper surface100S of the substrate100, the upper sidewall172bof the gate selection line170may have the third angle θ3with respect to the upper surface100S of the substrate100, and the second angle θ2may be different from the third angle θ3.

Referring toFIG. 25, a portion of the channel structure200is removed by the process such as an etch-back to form the trench195, and a pad190filling the trench195is formed.

The pad190may be formed to cover the dielectric film130, the channel film140, and the filling film150in the channel hole CHH. The pad190may include, but is not limited to, at least one of, for example, doped semiconductors, metals, metal silicide, and metal nitrides.

Next, referring again toFIG. 4, the upper insulating film196is formed to cover the pad190, and a bit line198electrically connected to the conductive contact197is formed on the upper insulating film196.