Complementary passive analog logic

Complementary passive analog logic (CPAL) devices and circuits involve low power characteristics, and have high speed integrated circuit technology that is analog in design yet mimics the low power characteristics of complementary metal oxide (CMOS) logic designs. CPAL acts like CMOS in a high or low logic clock condition, but is analog in nature when clocked. CPAL is a distributed charge pump that super-positions an analog transient on a digital bias voltage. The two add vectorially on the positive going clock pulse. Nominal direct current (DC) power supply voltage is approximately equal to the threshold voltage of an N-channel transistor. CPAL is completely synchronous in operation, and a virtual open circuit in a non-clocked more. This pertains to reducing the noise found today in most integrated circuits. The latch design is for circuits of approximately 1.2 microns, and multiple flip-flops are provided to recapture most of the lost energy in existing integrated circuit designs.

DETAILED DESCRIPTION OF THE INVENTION The circuitry shown in FIGS. 1 - 8 of the present invention provides complementary passive analog logic (CPAL) devices and circuits involving lower power characteristics, and having high speed integrated circuit technology that is analog in design yet mimics the low power characteristics of complementary metal oxide (CMOS) logic designs. More particularly, in the present invention, CPAL acts like CMOS in a high or low logic clock condition, but is analog in nature when clocked. CPAL is a distributed charge pump that super-positions an analog transient on a digital bias voltage. The two add vectorially on the positive going clock pulse. Nominal direct current (DC) power supply voltage is approximately equal to the threshold voltage of an N-channel transistor. CPAL is completely synchronous in operation, and a virtual open circuit in a non-clocked mode. This invention provides a means to reduce the noise found today in most integrated circuits. This noise is wasted energy that the circuit could be using for productive purposes, but instead is lost, and thus wasted. This invention recaptures the noise and converts it to productive energy. In an example embodiment, this latch 100 design is for circuits of approximately 1.2 microns, however this latch 100 design may be adapted by one of average skill in this art to higher or lower microns, depending upon its intended use, and such adaptations are intended to fall within the scope of this disclosure. Multiple latches form a flip-flop function, and multiple flip-flop functions will form a shift register 88 that can be used to recapture most of the lost energy in existing integrated circuit 500 designs. The latch 100 design of the present invention, when embodied in an integrated circuit 500 , provides positive cross coupled feedback 600 utilizing simultaneous analog and digital 92 , 93 signal processing 94 , thus reducing the noise found in most integrated circuit 500 designs. FIG. 1 is a schematic circuit diagram of a latch 100 . The latch has inputs A and inverse A ( 30 , 35 ), as well as outputs Q and inverse Q ( 40 , 45 ). The circuit has voltages Vcc 50 . A clock input 20 is provided at a clock circuit 2 to produce a clock output 10 . In FIG. 1 , the circuit is constructed with p-channel transistors 62 and n-channel transistors 64 . An exemplary gate-width 91 for each transistor 90 is shown in the drawings, and is based on its location and function. FIG. 2 shows the schematic circuit diagram of the substrate placement routing 200 for the latch 100 of FIG. 1 . The numbered transistors 90 of this figure correspond to the placement chart shown in FIG. 3 . FIG. 3 shows the schematic circuit diagram of transistor placement 300 , and the ground and voltage planes for the latch 100 of FIG. 1 . The numbered transistors 90 of this figure correspond to the numbered transistors 90 shown and numbered correspondingly in FIG. 2 . FIG. 4 shows the schematic circuit diagram of the latch 100 substrate switching static transistor configuration 400 . Descriptive labels are provided for the transistors 90 shown, including the n-channel/p-channel substrate 1 , clock 2 , signal path 3 , load data configuration 4 , latch data configuration 5 , direct current (D.C.) signal path 6 , load input data configuration 7 , 8 . The substrate 4 A.C. references to substrate 2 . Substrate 9 is the substrate 3 A.C. referenced to substrate 1 ; and substrate 10 is substrate 5 A.C. referenced to substrate 3 . FIGS. 5, 6 , 7 , and 8 show the latch 100 operations during the various clock 2 cycles. In FIG. 5 , there is no D.C. current path between Vcc A 53 and Vcc D 56 . No D.C. current path exists between GND C and GND C, E, and the circuit is charging 76 . In FIG. 6 , showing a static model, the CLK is low, the circuit is charging 76 , there is no D.C. current path between Vcc B 54 and Vcc D 56 , and there is no D.C. current path between GND A 57 and GND C and GND E. FIG. 7 is a static model showing the latch 100 operations during one of the various clock 2 cycles. In this figure, the clock 2 is rising from GND 49 to voltage Vcc 50 . FIG. 8 is a static model showing the latch 100 operations during one of the various clock 2 cycles. In this figure, the integrated circuit 500 is discharged, no D.C. current flows, Vcc B 54 is shorted to Vcc D 56 , GND A 57 is shorted to GND C and GND E, the clock 2 is logic Vcc A 53 , and no D.C. current paths exists between Vcc B 54 and Vcc D 56 . The invention being thus described, it will be evident that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention and all such modifications are intended to be included within the scope of the claims.