DISPLAY PANEL, DRIVING METHOD THEREOF AND DISPLAY DEVICE THEREOF

Display panel, driving method, and display device are provided. The display panel includes sub-pixels and data lines. A sub-pixel includes a pixel circuit and a light emitting element. The pixel circuit includes a data writing module electrically connected to a driving transistor, and a data line reset module. A first terminal of the data line reset module is electrically connected to a data line, a second terminal of the data line reset module is electrically connected to a data line reset signal terminal. An operation stage of the pixel circuit at least includes a data writing stage. In the data writing stage, the data writing module transmits a data voltage signal to the driving transistor. The operation stage also includes a data line reset stage. In the data line reset stage, the data line reset signal terminal transmits a data line reset signal to the data line.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Chinese Patent Application No. 202310913842.5, filed on Jul. 24, 2023, the entire content of which is hereby incorporated by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of display technology and, more particularly, relates to a display panel, a driving method thereof, and a display device thereof.

BACKGROUND

Organic Light Emitting Diodes (OLEDs) are one of the hot spots in the field of display research nowadays. Compared with Liquid Crystal Display (LCD), OLEDs are more and more used in high-performance display due to their characteristics such as self-illumination, fast responses, wide viewing angles, and capabilities to be produced on flexible substrates. Pixel circuit design is a core technical content of OLED display and has important research significance.

In existing panel design, the scanning turn-on time of each row may be short, and the writing time of the data voltage signal may be insufficient. Accordingly, compensation for the threshold value of the driving transistor in the pixel circuit may be insufficient, and display uniformity may thus be affected. Improvement of the display effects may result in an increase of power consumption. In addition, residual voltages on data lines of different display frames may cause crosstalk between three primary color (RGB) display data in the panel structure, and the display quality may thus be affected.

As such, providing a display panel, a driving method, and a display device that may not only improve display effects but also reduce power consumption is an urgent technical problem that needs to be solved.

SUMMARY

One aspect of the present disclosure includes a display panel. The display panel includes a plurality of sub-pixels and a plurality of data lines. A sub-pixel of the plurality of sub-pixels includes a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit includes a data writing module electrically connected to a driving transistor, and a data line reset module. A first terminal of the data line reset module is electrically connected to a data line of the plurality of data lines, a second terminal of the data line reset module is electrically connected to a data line reset signal terminal, and the data writing module is electrically connected to the data line. An operation stage of the pixel circuit at least includes a data writing stage, and in the data writing stage, the data writing module is turned on and transmits a data voltage signal of the data line to the driving transistor. Before the data writing stage, the operation stage also includes a data line reset stage, and in the data line reset stage, the data line reset module is turned on, and the data line reset signal terminal transmits a data line reset signal to the data line through the data line reset module.

Another aspect of the present disclosure includes driving method for a display panel. The driving method includes a data line reset stage and a data writing stage. The display panel includes a plurality of sub-pixels and a plurality of data lines. A sub-pixel of the plurality of sub-pixels includes a pixel circuit and a light emitting element electrically connected to the pixel circuit, the pixel circuit includes a data writing module electrically connected to a driving transistor and a data line reset module, a first terminal of the data line reset module is electrically connected to a data line of the plurality of data lines, a second terminal of the data line reset module is electrically connected to a data line reset signal terminal, and the data writing module is electrically connected to the data line. The data line reset stage is executed before the data writing stage. In the data line reset stage, the data line reset module is turned on, and the data line reset signal terminal transmits a data line reset signal to the data line through the data line reset module to reset the data line. In the data writing stage, the data writing module is turned on, and transmits a data voltage signal of the data line to the driving transistor.

Another aspect of the present disclosure includes a display device. The display device includes a display panel. The display panel includes a plurality of sub-pixels and a plurality of data lines. A sub-pixel of the plurality of sub-pixels includes a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit includes a data writing module electrically connected to a driving transistor, and a data line reset module. A first terminal of the data line reset module is electrically connected to a data line of the plurality of data lines, a second terminal of the data line reset module is electrically connected to a data line reset signal terminal, and the data writing module is electrically connected to the data line. An operation stage of the pixel circuit at least includes a data writing stage, and in the data writing stage, the data writing module is turned on and transmits a data voltage signal of the data line to the driving transistor. Before the data writing stage, the operation stage also includes a data line reset stage, and in the data line reset stage, the data line reset module is turned on, and the data line reset signal terminal transmits a data line reset signal to the data line through the data line reset module.

Other aspects of the present disclosure may be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

DETAILED DESCRIPTION

To make the objectives, technical solutions and advantages of the present disclosure clearer and more explicit, the present disclosure is described in further detail with accompanying drawings and embodiments. It should be understood that the specific exemplary embodiments described herein are only for explaining the present disclosure and are not intended to limit the present disclosure.

Technologies, methods, and equipment known to those of ordinary skill in relevant fields may not be discussed in detail, but where appropriate, these technologies, methods, and equipment should be regarded as part of the specification.

Reference will now be made in detail to embodiments of the present disclosure, which are illustrated in the accompanying drawings. Similar labels and letters designate similar items in the drawings. Once an item is defined in one drawing, the item may not be defined and discussed in subsequent drawings.

FIG.1illustrates a schematic diagram of a plan structure of a display panel consistent with the disclosed embodiments of the present disclosure.FIG.2illustrates a schematic diagram of an electrical connection structure of a sub-pixel inFIG.1. Referring toFIGS.1and2, the present disclosure provides a display panel000, including a plurality of sub-pixels P. The sub-pixel P includes an electrically connected pixel circuit10and a light emitting element20. The pixel circuit10includes a data writing module101and a data line reset module102electrically connected to a driving transistor DT.

The display panel000may also include a plurality of data lines S. A first terminal of the data line reset module102is electrically connected to the data line S. A second terminal of the data line reset module102is electrically connected to a data line reset signal terminal D. The data writing module101is electrically connected to the data line S.

An operation stage of the pixel circuit10at least includes a data writing stage. In the data writing stage, the data writing module101is turned on and transmits a data voltage signal Vdata of the data line S to the driving transistor DT.

Before the data writing stage, the operation stage may also include a data line reset stage. In the data line reset stage, the data line reset module102is turned on, and the data line reset signal terminal D transmits a data line reset signal to the data line S through the data line reset module102.

Specifically, in one embodiment, the display panel000may be an organic light emitting diode display panel. The display panel000may include a plurality of sub-pixels P. Optionally, the plurality of sub-pixels P may include a plurality of different colors (illustrated with different filling patterns inFIG.1). For example, the plurality of may at least include red sub-pixels, green sub-pixels, blue sub-pixels, and may also include white sub-pixels. The present disclosure does not limit specific colors of the sub-pixels. Optionally, the plurality of sub-pixels P may be arranged in an array on the display panel000, or may be arranged in other ways.FIG.1only takes an array arrangement of the sub-pixels P as an example for illustration. It may be understood that, inFIG.1, as an example, an orthographic projection shape of a sub-pixel P onto a light emitting surface of the display panel000is a strip. In specific implementation, the shape of the sub-pixel P includes but is not limited to a strip. For example, the sub-pixel may be designed as a circle or a polygon, and may be specifically designed according to actual needs.

Referring toFIG.2, in one embodiment, the sub-pixel P includes a pixel circuit10and a light emitting element20electrically connected to the pixel circuit10. Optionally, the light emitting element20may be an organic light emitting diode. The pixel circuit10included in the sub-pixel P may be used to transmit light emitting driving current to the light emitting element20under action of signals from driving signal lines (such as scanning lines, data lines, power signal lines, etc., not shown inFIG.2) on the display panel000. Accordingly, the driving current may be transmitted to the light emitting element20to make the light emitting element20to emit light. The present disclosure does not elaborate on the light emitting principle of the sub-pixel P in the display panel000.

In one embodiment, the display panel000includes a plurality of data lines S. Optionally, the display panel000may also include a plurality of scan lines G. Extension directions of the scan lines G and the data lines S may intersect or be perpendicular to each other. As shown inFIG.1, the scan line G extends along a first direction X, and the data line S extends along a second direction Y. The pixel circuit10includes a data writing module101electrically connected to the driving transistor DT. Optionally, one of the source or the drain of the driving transistor DT is electrically connected to one terminal of the data writing module101, and the other of the source or the drain of the driving transistor DT is electrically connected to the light emitting element20. The driving transistor DT of the pixel circuit10may be used to generate driving current for driving the light emitting element20to emit light, thereby realizing the light emitting function of the light emitting element20.

The data writing module101is electrically connected to the data line S. Optionally, a first terminal of the data writing module101may be electrically connected to one of the source or the drain of the driving transistor DT, and the second terminal of the data writing module101may be electrically connected to the data line S. In one embodiment, an operation stage of the pixel circuit10at least includes a data writing stage. In the data writing stage, the data writing module101is turned on, that is, the first terminal and the second terminal of the data writing module101are connected. A data voltage signal Vdata transmitted on the data line S may be transmitted to the driving transistor DT through the data line S. Optionally, the operation stage of the pixel circuit10may also include a light emitting stage located after the data writing stage. In the light emitting stage, the driving transistor DT generates the driving current to drive the light emitting element20to emit light, achieving the light emitting function of the light emitting element20.

In existing panel design, as the resolution of a display panel increases, the scanning turn-on time of each row of sub-pixels P controlled by the scanning line G may become shorter. As such, the writing time of the data voltage signal Vdata on the data line S may be insufficient, and threshold compensation for the driving transistor DT in the pixel circuit10may be insufficient. Accordingly, display uniformity may be affected. In existing technologies, to improve the display effect, the data writing time may be increased, and power consumption may thus be increased. Moreover, in different display frames of the display panel000, the residual voltage signal on the data line S after a previous frame is completed may affect the signal transmission of the data line S in a next frame. Accordingly, crosstalk between display data in the panel structure may appear, and display quality may be affected.

In one embodiment, the pixel circuit10also includes a data line reset module102. A first terminal of the data line reset module102is electrically connected to the data line S, and a second terminal of the data line reset module102is electrically connected to the data line reset signal terminal D. The data line reset signal terminal D may be used to provide a data line reset signal. In one embodiment, the operation stage of the pixel circuit10also includes a data line reset stage, and the data line reset stage may be performed before the data writing stage. When the pixel circuit10operates in the data line reset stage, the data line reset module102is turned on, that is, the first terminal and the second terminal of the data line reset module102are connected. The data line reset signal provided by the data line reset signal terminal D electrically connected to the second terminal of the data line reset module102may be transmitted to the data line S to reset the data line S. Accordingly, the data line reset signal provided by the data line reset signal terminal D may be used to clear the remaining data voltage value on the data line S of the previous frame before the next frame starts, so as to reset the data line S. As such, the data voltage signal Vdata provided on the data line S of the next frame may avoid the interference by the residual value of the previous frame as much as possible. Then, in the data writing stage of the next frame, the data voltage signal Vdata on the data line S may be fast and fully written into the driving transistor DT through the data writing module101. Accordingly, the problem of insufficient threshold compensation of the driving transistor DT in the pixel circuit10may be addressed, and display uniformity and display quality may be improved. Furthermore, the increase of the time of the data writing stage may not be needed, and power consumption may be reduced.

It may be understood that, in one embodiment, the reset signal terminal D of the data line may be connected to the signal wiring in the display panel000. The data line reset signal may be provided to the data line reset signal terminal D through the signal wiring provided in the display panel000. The present disclosure does not limit specific values of the data line reset signal, provided that the residual value of a previous frame on the data line S may be cleared such that the data line S may be reset.

It may be understood thatFIGS.1and2take the driving transistor DT as a P-type transistor as an example for illustration. In specific implementation, the driving transistor DT may also be an N-type transistor. The present disclosure does limit a specific type of the driving transistor DT.

It should be noted that the structure of the display panel000includes but is not limited to above-described structures. In specific implementation, the display panel000may also include other structures capable of realizing the display function, which will not be elaborated here.

Optionally, in one embodiment, the data line reset signal provided by the data line reset signal terminal D electrically connected to the second terminal of the data line reset module102may be a low voltage signal VD (ie, the data line reset signal), where VD<Vmin. The light emitting element20may include a blue light emitting element, and Vmin is a value of the data voltage signal Vdata-B required by the blue light emitting element at the highest brightness.

In one embodiment, to make the low-level data voltage signal Vdata transmitted on the data line S be normally written into the gate of the driving transistor DT in the data writing stage, the data line reset stage may be performed before the data writing stage. Accordingly, the first terminal and the second terminal of the data line reset module102are conducted, and the low voltage signal VD provided by the data line reset signal terminal D may be transmitted to the data line S to reset the data line S. Accordingly, the data line reset signal provided by the data line reset signal terminal D may be used to clear the residual data voltage value on the data line S of a previous frame before a next frame starts, so as to reset the data line S. As such, the data voltage signal Vdata provided on the data line S of the next frame may avoid the interference by the residual value of the previous frame as much as possible. Then, in the data writing stage of the next frame, the data voltage signal Vdata on the data line S may be fast and fully written into the driving transistor DT through the data writing module101. Accordingly, the problem of insufficient threshold compensation of the driving transistor DT in the pixel circuit10may be addressed, and display uniformity and display quality may be improved. Furthermore, the increase of the time of the data writing stage may not be needed, and power consumption may be reduced.

In one embodiment, the low voltage signal VD provided by the data line reset signal terminal D is smaller than Vmin, and Vmin is a value of the data voltage signal Vdata-B required by the blue light emitting element at the highest brightness. The plurality of light emitting elements20in the display panel000may include blue light emitting elements, red light emitting elements and green light emitting elements. When the value range of the data voltage signal transmitted on the data line S is defined as Vgsp-Vgmp, the smallest data voltage signal Vdata-min among different light emitting elements20corresponding to the display panel000at the highest brightness may be the value of the data voltage signal Vdata-B of the blue light emitting element. That is, Vmin is Vdata-min, which is the value of the data voltage signal Vdata-B required by the blue light emitting element at the highest brightness. When the value range of the data voltage signal transmitted on the data line S is defined as Vgsp-Vgmp, the relationship between the maximum value Vgmp, the minimum value Vgsp and Vmin of the data voltage signal transmitted on the data line S may be Vgsp<Vmin<Vgmp.

In one embodiment, the low voltage signal VD provided by the data line reset signal terminal D is at least less than Vmin, such that the reset effect of the data line reset module102on the data line S may be improved. For example, when the positive power supply voltage value Vpvdd that provides the positive power signal for the pixel circuit10in the display panel000is about 3.3V, the low voltage signal VD provided by the reset signal terminal D of the data line may be about 1V. By setting the low voltage signal VD at least smaller than the value of the data voltage signal Vdata-B required by the blue light emitting element at the highest brightness, the reset effect of the data line S before the data writing stage may be improved, and the display quality may be improved.

FIG.3illustrates a schematic diagram of another electrical connection structure of a sub-pixel inFIG.1. Referring toFIGS.1and3, in one embodiment, the pixel circuit10may also include a reset module100. A first terminal of the reset module100is electrically connected to a reference voltage signal terminal REF. A second terminal of the reset module100is electrically connected to the gate of the driving transistor DT. The data line reset signal terminal D is electrically connected to the reference voltage signal terminal REF.

In one embodiment, in each sub-pixel P of the display panel000, the pixel circuit10also includes a reset module100. The first terminal of the reset module100is electrically connected to the reference voltage signal terminal REF, and the second terminal of the reset module100is electrically connected to the gate of the driving transistor DT. The reset reference signal provided by the reference voltage signal terminal REF may be transmitted to the gate of the driving transistor DT. The reset reference signal provided by the reference voltage signal terminal REF may be a low-level signal. The low-level potential of the reset reference signal may be used to reset the gate of the driving transistor DT, and the conduction of the driving transistor DT after completing the reset operation may be achieved.

In one embodiment, the reset signal terminal D of the data line is electrically connected to the reference voltage signal terminal REF. The reset reference signal provided by the reference voltage signal terminal REF for resetting the gate of the driving transistor DT may be a low-level signal. The low-voltage signal VD provided by the reset signal terminal D of the data line may directly multiplex the reference voltage signal terminal REF included in the pixel circuit10in the display panel000. That is, the data line reset signal terminal D and the reference voltage signal terminal REF of the pixel circuit10may be shared. Accordingly, each pixel circuit10of the display panel000may save one signal terminal, and the quantity of signal terminals in the display panel000may be reduced. In addition, when the data line reset signal terminal D and the reference voltage signal terminal REF of the pixel circuit10are shared, the data line reset signal terminal D and the reference voltage signal terminal REF may be connected to a same reference voltage signal line. As such, the quantity of signal lines in the display panel000may be reduced, and the layout space may be saved.

FIG.4illustrates a schematic diagram of another plan structure of a display panel consistent with the disclosed embodiments of the present disclosure.FIG.5illustrates a schematic diagram of an electrical connection structure of a plurality of sub-pixels and a multiplexing circuit inFIG.4. Referring toFIGS.4and5, in one embodiment, the display panel000includes a multiplexing circuit30.

The first terminal of the data writing module101is electrically connected to the first electrode of the driving transistor DT. The second terminal of the data writing module101is electrically connected to one terminal of the data line S, and the other terminal of the data line S is electrically connected to the output terminal of the multiplexing circuit30. In the data writing stage, the conduction period of the multiplexing circuit30may overlap with the conduction period of the data writing module101.

The narrow frame design of existing display panels is mainly reflected in a narrow upper frame, a narrow left frame and a narrow right frame, while the narrow frame design of a lower frame may still be difficult. A main reason is that, as resolution requirements for display panels become higher and higher, a quantity of output pins of the driver chips may increase accordingly, resulting in an increase in a quantity of corresponding traces. The increase in the quantity of traces may make it difficult to reduce the fan-shaped area (Fan-out) used to lay out connecting lines (such as data lines) between the driver chip (or flexible circuit board) and the panel. As a result, the lower frame of the display panel may not achieve a narrow frame design like the upper frame and the left and right frames, affecting the appearance of the display panel.

To address above-described problems, in one embodiment, a multiplexing circuit30is provided in a non-display area NA of the display panel000. The multiplexing circuit30may be a demultiplexer (Demux). Optionally, the sub-pixels P may be located in the display area AA of the display panel000, and the multiplexing circuit30may be located in the non-display area NA of the display panel000. The first terminal of the data writing module101of the pixel circuit10may be electrically connected to the first electrode of the driving transistor DT, and the second terminal of the data writing module101may be electrically connected to one terminal of the data line S. The other terminal of the data line S may be electrically connected to the output terminal of the multiplexing circuit30. Optionally, the other terminal of the data line S may be electrically connected to the output terminal of the multiplexing circuit30through the fan-out trace F. Through the arrangement of the multiplexing circuit30, the second terminal of the data writing module101may be electrically connected to one terminal of the data line S. The other terminal of the data line S may be electrically connected to the output terminal of the multiplexing circuit30. Accordingly, while reducing the quantity of fan-out traces in the fan-shaped area (Fan-out) (traces used for electrically connecting the data line S of the display area AA to the driver chip or flexible circuit board that may be subsequently bound to the display panel000), writing of data voltage signals may be completed. As such, the space of the non-display area NA occupied by the fan-out traces may be reduced. Accordingly, the widths of the non-display area NA in the first direction X and the second direction Y may be reduced overall, and narrow design of the lower frame of the display panel000may be achieved.

It may be understood that the present disclosure does not elaborate on the connection structure of the multiplexing circuit30. In specific implementation, the connection structure of the electrical connection between the multiplexing circuit30, the data line S, and the subsequently bound driver chip or the flexible circuit board may be understood with reference to connection methods in subsequent embodiments.FIG.4only illustrates the multiplexing circuit30with a block diagram.

However, after the display panel uses the Demux structure, especially under the conditions of high refresh frequency and high resolution, the data writing time that may be allocated to each row of sub-pixels may be short. In existing technologies, when the data voltage signal is written, the Demux circuit may be first turned on, and the data voltage signal may be first written on the data line of the display area through the Demux circuit. The data writing module in the pixel circuit may be turned on after. After the data writing module is turned on, the data voltage signal that has been written on the data line may be written into the gate of the driving transistor. Although this method may reduce power consumption, turning on of the Demux circuit and conduction of the data writing module need to be completed within the scanning time of one row. Under conditions of high refresh frequency and high resolution, the scanning time of each row of sub-pixels may be short, and the data writing time that may be allocated to each row of sub-pixels may be also short. Accordingly, the data writing time may be insufficient, and the threshold compensation of the driving transistor may be insufficient. As such, the display uniformity may be affected, resulting in poor display effects. Increasing the time for data writing may improve display effects, but may in turn increase the power consumption of the display panel.

To solve above-described problems, in one embodiment, in the data writing stage, the conduction time period of the multiplexing circuit30overlaps with the conduction time period of the data writing module101. That is, while the first terminal and the second terminal of the data writing module101are conducted in the data writing stage, the multiplexing circuit30is also turned on. When the display panel000drives display, while the data voltage signal is transmitted to the data line S through the multiplexing circuit30, the data writing module101is also turned on, and the data voltage signal transmitted on the data line S may be synchronously written into the driving transistor DT. By configuring the multiplexing circuit30and directly writing the data voltage signal to the gate of the driving transistor DT, a narrow frame design may be realized, and long data writing time may be achieved. Accordingly, the threshold compensation of the driving transistor DT may be sufficient, good display uniformity may be obtained, and display quality may be improved.

FIG.6illustrates a schematic diagram of another electrical connection structure of a plurality of sub-pixels and a multiplexing circuit inFIG.4. Referring toFIGS.4-6, in one embodiment, the multiplexing circuit30includes a plurality of multiplexing units300. Each multiplexing unit300includes a plurality of control terminals301, a signal input terminal30in and a plurality of signal output terminals30out. The control terminal301is connected to control signals (CKH1, CKH2, CKH3as shown inFIG.6). The signal input terminal30in receives the data voltage signal Vdata, and the plurality of signal output terminals30out are connected to different data lines S respectively. In the multiplexing unit300, the ratio of the quantities of signal input terminals30in and signal output terminals30out is 1: N, where N is an integer and N≥2.

Optionally, the multiplexing unit300may include a plurality of switching transistors30T. Gates of the switching transistors30T are connected to the control terminals301, and the first electrodes of the switching transistors30T are connected to the signal input terminals30in. The second electrodes of the switching transistors30T are connected to the signal output terminals30out. The signal input terminals30in are connected to a part of conductive pads (not shown inFIG.6) in the bonding area through the fan-out trace F in the fan-out area. The output terminals30out are connected to the data lines S of the display area AA.

InFIG.6, the multiplexing circuit30adopts 1:3 demux as an example. Accordingly, the whole multiplexing circuit30may include three control terminals301(CKH1, CKH2, and CKH3as shown inFIG.6). In this configuration, three clock control signal lines40may extend from only one terminal of the multiplexing circuit30and connected to the three control terminals301of the multiplexing circuit30respectively (not shown inFIG.6). Three clock control signal lines40may extend from at least one terminal of the multiplexing circuit30and connected to the three control terminals301of the multiplexing circuit30respectively. Accordingly, the clock control signals provided by a part of conductive pads in the bonding area may be transmitted from at least one terminal of the multiplexing circuit30to the multiplexing circuit. As such, the data voltage signal may be transmitted through the multiplexing circuit30to reduce the width of the non-display area NA.

In one embodiment, the multiplexing circuit30includes a plurality of control terminals301. The plurality of conductive pads included in the bonding area may be connected to the plurality of control terminals301provided in the multiplexing circuit30through the plurality of clock control signal lines40in one-to-one correspondence. The clock control signal may be provided to the multiplexing circuit30through the clock control signal line40. The clock control signal transmitted on the clock control signal line40may be a pulse signal, and may be used to control the conduction and disconnection of the multiplexing circuit30.

When the display panel000displays different frames, the residual voltage signal on the data line S after a previous frame is completed may affect the signal transmission of the data line S in a next frame. Accordingly, crosstalk between display data in the panel structure may appear, and display quality may be affected. In existing technologies, when the display panel includes a multiplexing circuit, the clock control signal may be provided to the multiplexing circuit30through the clock control signal line40before the data voltage signal is written. In this way, the switching transistor30T in the multiplexing circuit30may be turned on first, to provide a low-level reset signal to the data line S to perform a data reset operation on the data line. However, this design method requires the reset operation to be performed by switching the clock control signal before the data voltage signal is written. Accordingly, the switching frequency of the clock control signal may be increased, resulting in increased power consumption.

In one embodiment, the pixel circuit10includes a data line reset module102. By setting the data line reset module102, the data line reset module102may be directly used to reset the data line S. As such, operation of turning on the multiplexing circuit30before the data writing stage to transmit the reset signal to reset the data line S may be simplified. That is, the clock control signal of the multiplexing circuit30does not need to be switched before the data writing stage, just waiting for the multiplexing circuit30to start transmitting the data voltage signal when the data writing module101is turned on in the data writing stage. In this way, the conductive pad in the bonding area may decrease one time of transmitting the data voltage signal used for reset, reducing the quantity of data voltage signal transitions. Accordingly, the driving power consumption of the multiplexing circuit30may be reduced, and the power consumption of the whole display panel000may be reduced. In the data writing stage, the conduction period of the multiplexing circuit30may be set to overlap with the conduction period of the data writing module101, such that the data writing time may be sufficient. As such, narrow frame design may be achieved, and display quality may be improved.

FIG.7illustrates a timing diagram of each clock control signal required for a data voltage signal and a multiplexing circuit in existing technology. Stage Z01′inFIG.7may be understood as the data line reset stage. In stage Z01′, clock control signals CKH1′, CKH2′, and CKH3′ provided by the clock control signal line control each of the switching transistors in the multiplexing circuit to turn on. The data voltage signal Vdata′ used for reset may be transmitted to the data line through the multiplexing circuit to reset the data line. The display panel then enters the data writing stage, such as stages Z02′, Z03′, and Z04′ inFIG.7. The clock control signals CKH1′, CKH2′, and CKH3′ provided by the clock control signal line sequentially control the conduction of different switching transistors in the multiplexing circuit, and write data voltage signals into different data lines respectively.

FIG.8illustrates a timing diagram of each clock control signal required for a data voltage signal, a data line reset signal and a multiplexing circuit, consistent with the disclosed embodiments of the present disclosure. Stage Z01inFIG.8may be understood as the data line reset stage. In stage Z01, clock control signals CKH1, CKH2, and CKH3provided by the clock control signal line40do not need to control the switching transistor30T in the multiplexing circuit30to turn on. That is, clock control signals CKH1, CKH2, and CKH3do not need to perform signal switching and only need to wait. The data reset module102is turned on, the data line reset signal VD is provided to the data line reset signal terminal D, and the data line reset signal VD is transmitted to the data line S to reset the data line. The display panel then enters the data writing stage. The multiplexing circuit30sequentially controls the different switching transistors30T in the multiplexing circuit30to turn on, through the clock control signals CKH1, CKH2, and CKH3provided by the clock control signal line40. Simultaneously, data writing module101is also turned on. In this way, the data writing time may be increased, the operation of writing the data voltage signal Vdata to different data lines S may be completed. Compared withFIG.7,FIG.8may reduce one time of inputting operation of the data voltage signal in the stage Z01and switching operation of the clock control signals CKH1, CKH2, and CKH3in the stage Z01. Accordingly, the conductive pad in the bonding area may reduce one time of transmitting the data voltage signal used for reset and may reduce one time of transmitting the clock control signal. Accordingly, the quantity of transitions of the data voltage signal and the clock control signal may be reduced, the driving power consumption of the multiplexing circuit30may be reduced, and the power consumption of the whole display panel000may be reduced.

It may be understood thatFIG.8only takes the switching transistor30T of the multiplexing circuit30as a P-type transistor as an example for illustration. In specific implementation, the switching transistor30T of the multiplexing circuit30may be an N-type transistor. The present disclosure does not limit a specific type of the switching transistor30T.

FIG.9illustrates a schematic diagram of another electrical connection structure of a plurality of sub-pixels and a multiplexing circuit, consistent with the disclosed embodiments of the present disclosure. Referring toFIGS.2and9, in one embodiment, the second terminals of the data writing modules101of the sub-pixels P in a same column may be connected to two different data lines S. The two different data lines S corresponding to the sub-pixels P in a same column include a first data line S1and a second data line S2.

Among the plurality of sub-pixels in a same column, the second terminal of the data writing module101of an n-th row sub-pixel P (n) is connected to the first data line S1, and a second terminal of the data writing module101of an (n+1)-th row sub-pixel P (n+1) is connected to the second data line S2, where n is a positive integer.

In one embodiment, the sub-pixels P in a same column in the display panel000may be connected to two data lines S, namely the first data line S1and the second data line S2. By setting the multiplexing circuit30, data voltage signals may be simultaneously written to the pixel circuits10of a same column of sub-pixels P through the first data line S1and the second data line S2. Specifically, the second terminals of the data writing modules101of the sub-pixels P in a same column may be connected to two different data lines S, namely the first data line S1and the second data line S2. Among a plurality of sub-pixels in a same column, the second terminal of the data writing module101of the n-th row sub-pixel P (n) is connected to the first data line S1, and the second terminal of the data writing module101of the (n+1)-th row sub-pixel P (n+1) is connected to the second data line S2. As such, when the multiplexing circuit30is turned on, the data writing module101is turned on, and the data voltage signal transmitted on the first data line S1may be directly written into the pixel circuit10of the n-th row sub-pixel P (n). The data voltage signal transmitted on the second data line S2may be directly written into the pixel circuit10of the (n+1)-th row sub-pixel P (n+1). Accordingly, the sub-pixel P in a current sub-pixel row has sufficient data writing time. Especially, even in a high-frequency driving mode with a high refresh frequency, the sub-pixel P may have sufficient charging time for data writing. As a result, the data voltage signal may be fully written, and the display quality of the display panel000in a high-frequency driving mode may be improved.

It may be understood thatFIG.9only illustrates an electrical connection structure of a plurality of sub-pixels and a multiplexing circuit. In specific implementation, the electrical connection methods between the sub-pixels and the multiplexing circuit may include but are not limited to the method described above, and may include other connection methods, provided that the sub-pixels P in a same column are connected to two data lines S. Details will not be described here.

FIG.10illustrates a schematic diagram of an electrical connection structure of a sub-pixel inFIG.4.FIG.11illustrates a schematic diagram of another electrical connection structure between a plurality of sub-pixels and a multiplexing circuit inFIG.4. Referring toFIGS.4,10, and11, in one embodiment, the first terminal of the data line reset module102is electrically connected to the first electrode of the driving transistor DT, and the first terminal of the data line reset module102is electrically connected to the first terminal of the data writing module101. In the data line reset stage, the data writing module101is turned on.

In one embodiment, in the pixel circuit10included in the sub-pixel P, the first electrode of the driving transistor DT is electrically connected to the first terminal of the data writing module101, and the first terminal of the data line reset module102is electrically connected to the first electrode of the driving transistor DT. That is, the first terminal of the data line reset module102is electrically connected to the first terminal of the data writing module101, and the second terminal of the data line reset module102is electrically connected to the data line reset signal terminal D. The second terminal of the data writing module101is connected to one terminal of the data line S, and the other terminal of the data line S is connected to the signal output terminal30out of the multiplexing circuit30. As such, a conductive path may be formed between the multiplexing circuit30, the data writing module101, the data line reset module102and the data line reset signal terminal D.

In one embodiment, in the data line reset stage, the data writing module101is turned on, that is, the data writing module101and the data line reset module102each are turned on in the data line reset stage. Resetting the data line S only needs to control each of the data writing module101and the data line reset module102to be turned on. The data line reset signal provided by the data line reset signal terminal D may be sequentially transmitted to the data line S through the data line reset module102and the data writing module101, thereby realizing the reset operation of the data line S. The operation of transmitting the reset signal of the data line to the data line S through the multiplexing circuit30may be reduced one time. Accordingly, the quantity of data voltage signal transitions may be reduced, and panel power consumption may be reduced. Moreover, since the first terminal of the data line reset module102is electrically connected to the first terminal of the data writing module101, connection nodes between the first terminal of the data line reset module102and the data line S may also be reduced. As such, the quantity of nodes in the pixel circuit10may be reduced, and the layout space of the panel may be saved.

FIG.12illustrates a schematic diagram of another electrical connection structure of a sub-pixel inFIG.4.FIG.13illustrates a schematic diagram of another electrical connection structure between a plurality of sub-pixels and a multiplexing circuit inFIG.4.FIG.14illustrates a timing diagram of each clock control signal required by a data voltage signal, a data line reset signal, each scan signal and a multiplexing circuit inFIG.13. ReferringFIGS.4,12,13, and14, in one embodiment, the data writing module101includes a first transistor T1. A gate of the first transistor T1is electrically connected to the first scan signal terminal1011, a first electrode of the first transistor T1is electrically connected to the first electrode of the driving transistor DT, and a second electrode of the first transistor T1is electrically connected to the data line S.

The data line reset module102includes a second transistor T2. A gate of the second transistor T2is electrically connected to a second scan signal terminal1021, a first electrode of the second transistor T2is electrically connected to the first electrode of the driving transistor DT, and a second electrode of the second transistor T2is electrically connected to the data line reset signal terminal D.

In the data line reset stage, the first scan signal terminal1011provides a first scan signal SCAN1to control the first transistor T1to turn on, and the second scan signal terminal1021provides a second scan signal SCAN2to control the second transistor T2to turn on. The data line reset signal VD may be transmitted to the data line S.

In the data writing stage, the first scan signal terminal1011provides the first scan signal SCAN1to control the first transistor T1to turn on, and the second scan signal terminal1021provides the second scan signal SCAN2to control the second transistor T2to turn off. The multiplexing circuit30is turned on. The data voltage signal Vdata of the data line S may be transmitted to the driving transistor DT.

In one embodiment, the data writing module101included in the pixel circuit10may include a first transistor T1, and the data line reset module102may include a second transistor T2. The gate of the first transistor T1is electrically connected to the first scan signal SCAN1provided by the first scan signal terminal1011to control the conduction and disconnection of the first transistor T1. The gate of the second transistor T2is electrically connected to the second scan signal SCAN2provided by the second scan signal terminal1021to control the conduction and disconnection of the second transistor T2. InFIGS.12and13, the first transistor T1and the second transistor T2each are P-type transistors as an example for illustration. That is, when the first scan signal SCAN1provided by the first scan signal terminal1011is a low potential signal, the first transistor T1is turned on. When the first scan signal SCAN1provided by the first scan signal terminal1011is a high potential signal, the first transistor T1is turned off. When the second scan signal SCAN2provided by the second scan signal terminal1021is a low potential signal, the second transistor T2is turned on. When the second scan signal SCAN2provided by the second scan signal terminal1021is a high potential signal, the second transistor T2is turned off.

In one embodiment, the data line reset stage is performed before the data writing stage. In the data line reset stage, such as the stage Z01inFIG.14, the first scan signal terminal1011provides the first scan signal SCAN1to control the first transistor T1to turn on. The second scan signal terminal1021provides the second scan signal SCAN2to control the second transistor T2to turn on. The data line reset signal VD provided by the data line reset signal terminal D may be transmitted to the data line S to perform a reset operation on the data line S. Then the display panel enters the data writing stage. In the data writing stage, such as the stage Z02, stage Z03, and stage Z04inFIG.14, the first scan signal terminal1011may provide the first scan signal SCAN1to control the first transistor T1to turn on. The second scan signal terminal1021may provide the second scan signal SCAN2to control the second transistor T2to turn off. The multiplexing circuit30may be turned on. The data voltage signal Vdata of the data line S may be transmitted to the driving transistor DT, and the data voltage signal Vdata may be written into the gate of the driving transistor DT.

In one embodiment, when the pixel circuit10is in operation, the first scanning signal SCAN1may be provided through the first scan signal terminal1011and the second scanning signal SCAN2may be provided through the second scanning signal terminal1021. The remaining data voltage value on the data line S of a previous frame may be cleared before a next frame starts. The data line reset signal VD provided by the data line reset signal terminal D may be transmitted to the data line S to reset the data line S. Accordingly, the data voltage signal Vdata provided on the data line S of the next frame may avoid the interference by the residual value of the previous frame as much as possible. In the data writing stage of the next frame, the data voltage signal Vdata on the data line S may be fast and fully written into the driving transistor DT through the data writing module101. As such, the problem of insufficient threshold compensation of the driving transistor DT in the pixel circuit10may be addressed, the display uniformity may be improved, and display quality may thus be improved. In addition, the increase of the time of the data writing stage may not be needed, the quantity of switching times of the clock control signal of the multiplexing circuit30may be reduced, and power consumption may thus be reduced.

FIG.15illustrates a schematic diagram of another electrical connection structure of a sub-pixel inFIG.4. Referring toFIGS.4and15, in one embodiment, the pixel circuit10also includes a first light emitting control module103, a second light emitting control module104, a first reset module105, a second reset module106, and a threshold compensation module107.

A first terminal of the first light emitting control module103is electrically connected to a first power signal terminal PVDD, and a second terminal of the first light emitting control module103is electrically connected to the first electrode of the driving transistor DT.

A first terminal of the second light emitting control module104is electrically connected to the second electrode of the driving transistor DT, and a second terminal of the second light emitting control module104is electrically connected to an anode of the light emitting element20. A cathode of the light emitting element20is connected to a second power signal terminal PVEE.

A first terminal of the first reset module105is electrically connected to a first reference voltage signal terminal REF1, and a second terminal of the first reset module105is electrically connected to the gate of the driving transistor DT.

A first terminal of the second reset module106is electrically connected to a second reference voltage signal terminal REF2, and a second terminal of the second reset module106is electrically connected to the anode of the light emitting element20.

The threshold compensation module107is electrically connected between the gate of the driving transistor DT and the second electrode of the driving transistor DT.

Optionally, the pixel circuit10also includes a memory module108. The memory module108is electrically connected between the first power signal terminal PVDD and the gate of the driving transistor DT.

In one embodiment, in addition to the driving transistor DT, the data writing module101, and the data line reset module100, the pixel circuit10in the display panel000may also include a first light emitting control module103, a second light emitting control module104, a first reset module105, a second reset module106, a threshold compensation module107, and a memory module108. Optionally, the pixel circuit10may also include other modules such as a bias module (not shown inFIG.15), etc. The present disclosure does not limit a specific module in the pixel circuit10. The control terminal of the first light emitting control module103may be electrically connected to the first light emitting control signal terminal EM1. The control terminal of the second light emitting control module104may be electrically connected to the second light emitting control signal terminal EM2. The first light emitting control signal terminal EM1and the second light emitting control signal terminal EM2may be connected to a same light emitting control signal line in the display panel000. The first light emitting control module103and the second light emitting control module104may be turned on simultaneously.

In the light emitting stage of the pixel circuit10, the first light emitting control signal VEM1provided by the first light emitting control signal terminal EM1may control the conduction and disconnection of the first terminal and the second terminal of the first light emitting control module103. When the first terminal and the second terminal of the first light emitting control module103are turned on, the first power signal Vpvdd provided by the first power signal terminal PVDD may be provided to the driving transistor DT. Optionally, the first power signal terminal PVDD may be electrically connected to the first power signal line in the display panel000. The second power signal terminal PVEE (used to provide the second power signal Vpvee) may be electrically connected to the second power signal line in the display panel000. The first power signal may be a positive power signal, and the second power signal may be a negative power signal.

The second light emitting control signal VEM2provided by the second light emitting control signal terminal EM2controls the conduction and disconnection of the first terminal and the second terminal of the second light emitting control module104. When the first terminal and the second terminal of the second light emitting control module104are conducted, the first power signal terminal PVDD and the second power signal terminal PVEE may form a conductive path for the first light emitting control module103, the driving transistor DT, and the second light emitting control module104. The driving current may drive the light emitting element20to emit light.

The memory module108may be used to stabilize the potential of the gate of the driving transistor DT, and the driving transistor DT may thus be kept being turned on. The first terminal of the first reset module105may be electrically connected to the first reference voltage signal terminal REF1. The first terminal of the second reset module106may be electrically connected to the second reference voltage signal terminal REF2. The first reference voltage signal terminal REF1and the second reference voltage signal terminal REF2may be connected to a same reference voltage signal line in the display panel000, or the first reference voltage signal terminal REF1and the second reference voltage signal terminal REF2may be connected to two different reference voltage signal lines in the display panel000. The present disclosure does not limit whether the first reference voltage signal terminal REF1and the second reference voltage signal terminal REF2are connected to a same reference voltage signal line.

A control terminal of the first reset module105may be electrically connected to the third scan signal terminal. The third scan signal SCAN3provided by the third scan signal terminal may control the conduction and disconnection of the first terminal and the second terminal of the first reset module105. When the first terminal and the second terminal of the first reset module105are connected, the first reset signal Vref1provided by the first reference voltage signal terminal REF1may be transmitted to the gate of the driving transistor DT to perform a reset operation on the gate of the driving transistor DT. The control terminal of the second reset module106may be electrically connected to the fourth scan signal terminal, and the fourth scan signal SCAN4provided by the fourth scan signal terminal may control the conduction and disconnection of the first terminal and the second terminal of the second reset module106. When the first terminal and the second terminal of the second reset module106are turned on, the second reset signal Vref2provided by the second reference voltage signal terminal REF2may be transmitted to the anode of the light emitting element20. The anode of the light emitting element20may be reset, and the anode of the light emitting element20may thus be initialized. Accordingly, in the display process, the residual display signal of a previous frame may be minimized, the afterimage phenomenon may be weakened, and the display effect may thus be improved.

The threshold compensation module107may be electrically connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT. The control terminal of the threshold compensation module107may be connected to a fifth scan signal terminal. The fifth scan signal SCAN5provided by the fifth scan signal terminal may control the conduction and disconnection of the first terminal and the second terminal of the threshold compensation module107. When the first terminal and the second terminal of the threshold compensation module107are turned on, the first terminal and the second terminal of the data writing module101may also be turned on. The threshold compensation voltage of the driving transistor DT may be captured through the data writing module101and the threshold compensation module107. The threshold voltage of the driving transistor DT may be compensated while writing the data voltage signal.

FIG.16illustrates a schematic diagram of a specific electrical connection structure of a sub-pixel inFIG.15.FIG.17illustrates a schematic diagram of an electrical connection structure of a plurality of sub-pixels and a multiplexing circuit inFIG.16.FIG.18illustrates an operation timing diagram of an electrical connection structure inFIG.17. Referring toFIGS.4,15,16,7and18, in one embodiment, the first light emitting control module103includes a third transistor T3. A gate of the third transistor T3is electrically connected to the first light emitting control signal terminal EM1. A first electrode of the third transistor T3is electrically connected to the first power signal terminal PVDD, and a second electrode of the third transistor T3is electrically connected to the first electrode of the driving transistor DT.

The second light emitting control module104includes a fourth transistor T4. A gate of the fourth transistor T4is electrically connected to the second light emitting control signal terminal EM2. A first electrode of the fourth transistor T4is electrically connected to the second electrode of the driving transistor DT, and a second electrode of the fourth transistor T4is electrically connected to the anode of the light emitting element20.

The first reset module105includes a fifth transistor T5. A gate of the fifth transistor T5is electrically connected to the third scan signal terminal. A first electrode of the fifth transistor T5is electrically connected to the first reference voltage signal terminal REF1, and a second electrode of the fifth transistor T5is electrically connected to the gate electrode of the driving transistor DT.

The second reset module106includes a sixth transistor T6. A gate of the sixth transistor T6is electrically connected to the fourth scan signal terminal. A first electrode of the sixth transistor T6is connected to the second reference voltage signal terminal REF2, and a second electrode of the sixth transistor T6is electrically connected to the anode of the light emitting element20. The cathode of the light emitting element20is connected to the second power signal terminal PVEE.

The threshold compensation module107includes a seventh transistor T7. A gate of the seventh transistor T7is electrically connected to the fifth scan signal terminal. A first electrode of the seventh transistor T7is electrically connected to the gate of the driving transistor DT, and a second electrode of the seventh transistor T7is electrically connected to the second electrode of the driving transistor DT.

The memory module108includes a first capacitor C1. A first electrode of the first capacitor C1is electrically connected to the gate of the driving transistor DT, and a second electrode of the first capacitor C1is electrically connected to the first power signal terminal PVDD.

In one embodiment, the pixel circuit10of each sub-pixel P in the display panel000may be a structure including a plurality of transistors and capacitors electrically connected. As shown inFIG.16, the pixel circuit10may be an electrical connection structure including eight transistors and one capacitor. One of the transistors is the driving transistor DT, and the remaining transistors are switching transistors. Specifically, the pixel circuit10includes a first transistor T1, a second transistor T2, the driving transistor DT, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7and a first capacitor C1.

As shown inFIG.16, in one embodiment, the pixel circuit10and the light emitting element20are electrically connected. The gate of the driving transistor DT represents the first node N1, the first electrode of the driving transistor DT represents the second node N2, and the second electrode of the driving transistor DT represents the third node N3. The anode of the light emitting element20serves as the fourth node N4. InFIG.16, the transistor is a P-type transistor as an example for illustration. Optionally, in one embodiment, the first transistor T1, the second transistor T2, the driving transistor DT, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7each are P-type low temperature polysilicon transistor. A low-temperature polysilicon transistors may have characteristics of high mobility and high driving speed. Accordingly, when the data writing module101writes the data voltage signal Vdata, the response speed of the driving transistor DT may be fast. As such, the data voltage signal Vdata may be quickly written, avoiding insufficient charging caused by the long turn-on time of the driving transistor DT.

The operation process of the circuit structure shown inFIG.17mainly includes 15 moments, including moments Z1, and Z1-Z14.

At moment Z0, the first light emitting control signal VEM1output by the first light emitting control signal terminal EM1is at a high level. The second light emitting control signal VEM2output by the second light emitting control signal terminal EM2is at a high level. The third transistor T3and the fourth transistor T4are each turned off, and the light emitting of a previous frame stops.

Moments Z1-Z6are a reset stage. Moments Z1-ZA are the reset stage of the first node N1and the third node N3.

At moment Z1, the third scan signal SCAN3output from the third scan signal terminal is at a low level. The fifth transistor T5is turned on, and other transistors are turned off. The first reset signal Vre1provided by the first reference voltage signal terminal REF1is written into the first node N1to reset the first node N1(that is, the gate of the driving transistor DT), and VN1=Vref1.

At moment Z2, the fifth scan signal SCAN5output from the fifth scan signal terminal is at a low level, and the seventh transistor T7is turned on. The first reset signal Vref1provided by the first reference voltage signal terminal REF1is written into the third node N3through the first node N1to reset the third node N3(ie, the second electrode of the driving transistor DT).

At moment Z3, the third scan signal SCAN3output from the third scan signal terminal is at a high level. The fifth transistor T5is turned off, and the reset of the first node N1and the third node N3ends.

Moments ZA-Z6are the reset stage of the data line, and the reset stage of the second node N2and the fourth node N4.

At moment Z4, the first scan signal SCAN1output from the first scan signal terminal is at a low level, and the first transistor T1is turned on.

At moment Z5, the second scan signal SCAN2output from the second scan signal terminal is at a low level, and the second transistor T2is turned on. The low-level data line reset signal VD provided by the data line reset signal terminal D is written into the second node N2through the second transistor T2, and resets the second node N2(i.e., the first electrode of the driving transistor DT). Simultaneously, the low-level data line reset signal VD provided by the data line reset signal terminal D is written into the data line S through the second transistor T2and the first transistor T1, and completes the reset for the data line S in the display area. Simultaneously, at moment Z5, the fourth scanning signal SCAN4output by the fourth scanning signal terminal is at a low level, and the sixth transistor T6is turned on. The second reset signal Vref2provided by the second reference voltage signal terminal REF2is written into the fourth node N4to reset the fourth node N4(i.e., the anode of the light emitting element20).

At moment Z6, the second scan signal SCAN2output from the second scan signal terminal is at a high level, and the second transistor T2is turned off. The fourth scan signal SCAN4output from the fourth scan signal terminal is at a high level, the sixth transistor T6is turned off, and the reset is completed.

Moments Z7-Z14are a threshold compensation and data writing stage.

At moment Z7, the clock control signals CKH1, CKH2, and CKH3of the multiplexing circuit30are written with a low level signal in sequence, and the switching transistors30T in the multiplexing circuit30are turned on in sequence. The data voltage signals Vdata required for sub-pixels P of different colors are sequentially written into the corresponding data lines S in the display area. Simultaneously, at moment Z7, the first scan signal SCAN1provided by the first scan signal terminal is at a low level, and the fifth scan signal SCAN5provided by the fifth scan signal terminal is at a low level. Accordingly, the first transistor T1, the driving transistor DT, and the seventh Transistor T7are turned on. The threshold-compensated data voltage signal on the data line S is written into the first node N1via the first transistor T1, the driving transistor DT, and the seventh transistor T7. Finally, at moment Z14, the fifth scanning signal SCAN5provided by the fifth scanning signal terminal is at a high level, and the first scanning signal SCAN1provided by the first scan signal terminal is at a high level. Accordingly, the first transistor T1and the seventh transistor T7are each turned off, and the respective first nodes N1in the sub-pixels P of different colors complete the threshold capture. At this moment, VN1=Vdata+Vth, where Vth is a threshold voltage of the driving transistor DT.

After moment Z15is the light emitting stage. The first light emitting control signal VEM1output from the first light emitting control signal terminal EM1is at a low level. The second light emitting control signal VEM2output from the second light emitting control signal terminal EM2is at a low level. The third transistor T3and the fourth transistor T4are turned on, and the display panel enters the light emitting stage.

It may be understood that in one embodiment, the cycle time of the clock control signals CKH1, CKH2, and CKH3of the multiplexing circuit30is theoretically1H.1H represents the ratio of one frame time of the display panel to the quantity of all sub-pixel rows in the display panel. The interval between the scanning driving signal of the pixel circuit in the current sub-pixel row and the scanning driving signal of the pixel circuit in the next sub-pixel row is1H. For the convenience of explanation, the timing diagram inFIG.18only draws the timing waveforms of the clock control signal from Z4to Z13.

In one embodiment, before the data writing stage, in the data line reset stage, the second scanning signal SCAN2provided by the second scanning signal terminal controls the second transistor T2to be turned on. The first scan signal SCAN1provided by the first scan signal terminal controls the first transistor T1to be turned on. Accordingly, the operation of turning on the multiplexing circuit30to transmit the reset signal to reset the data line S before the data writing stage may be simplified. That is, the multiplexing circuit30does not need to perform switching operations on the clock control signals (CKH1-CKH3) before the data writing stage (before moment Z7inFIG.18). The multiplexing circuit30may just wait until the first transistor T1is turned on in the data writing stage and the multiplexing circuit30is also turned on to transmit the data voltage signal. The conductive pad in the bonding area may reduce one time of transmitting the data voltage signal used for reset, and the quantity of the data voltage signal transitions may be reduced. As such, the driving power consumption of the multiplexing circuit30may be reduced, and the power consumption of the whole display panel000may be reduced. In the data writing stage (moments Z7-Z14inFIG.18), the conduction period of the multiplexing circuit30may be set to overlap with the conduction period of the first transistor T1, and the time for data writing may thus be sufficient. Accordingly, while achieving narrow frame design, display quality may be improved.

In one embodiment, the display panel000is an organic light emitting diode display panel. The sub-pixel P may include an electrical connection structure of a pixel circuit10, a light emitting element20, and a multiplexing circuit30. In specific implementation, the electrical connection structure of the pixel circuit10, the light emitting element20and the multiplexing circuit30included in the sub-pixel P may also include other implementation structures, which will not be elaborated here.

FIG.19illustrates a schematic diagram of another specific electrical connection structure of sub-pixels inFIG.15.FIG.20illustrates a schematic diagram of an electrical connection structure of a plurality of sub-pixels and a multiplexing circuit inFIG.15. FIG.21illustrates an operation timing diagram of an electrical connection structure inFIG.20. Referring toFIGS.4,15,19,20and21, in one embodiment, the pixel circuit10of each sub-pixel P in the display panel000may be a structure including a plurality of transistors and capacitors electrically connected.

As shown inFIG.19, the pixel circuit10may be an electrical connection structure including eight transistors and one capacitor. One of the transistors is the driving transistor DT, and the remaining transistors are switching transistors. Specifically, the pixel circuit10includes a first transistor T1, a second transistor T2, the driving transistor DT, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7and a first capacitor C1. As shown inFIG.19, in one embodiment, the pixel circuit10and the light emitting element20are electrically connected. The gate of the driving transistor DT represents the first node N1, the first electrode of the driving transistor DT represents the second node N2, the second electrode of the driving transistor DT represents the third node N3, and the anode of the light emitting element20represents the fourth node N4.

Optionally, the first transistor T1, the second transistor T2, the driving transistor DT, the third transistor T3, the fourth transistor T4, and the sixth transistor T6each are P-type low-temperature polysilicon transistors. The fifth transistor T5and the seventh transistor T7each are N-type oxide transistors, such as N-type indium gallium zinc oxide (IGZO) transistors. Since oxide transistors may have lower mobility and smaller leakage current than low-temperature polysilicon transistors, in one embodiment, the fifth transistor T5and the seventh transistor T7electrically connected to the gate of the driving transistor DT are configured as N-type IGZO transistors. Accordingly, the charge leakage of the driving transistor DT gate in low-frequency driving may be prevented, the leakage current problem in low-frequency driving may be addressed, and the pixel circuit10may be suitable for low-frequency driving. The transistors of other modules of the pixel circuit10may still be low-temperature polysilicon transistors. By using low-temperature polysilicon transistors, the pixel circuit00may still maintain strong driving capabilities under low-frequency driving. Accordingly, the power consumption of the display panel using the pixel circuit00may be reduced.

It may be understood that, in one embodiment, when other modules, such as the data writing module101, include the first transistor T1, the transistors of this module may still be designed as P-type low-temperature polysilicon transistors. As such, the pixel circuit10may maintain a strong driving capability by using low-temperature polysilicon transistors, provided that IGZO transistors are used for parts of the pixel circuit10that are prone to leakage (such as the part connected to the gate of the driving transistor DT). The pixel circuit10combines two types of thin film transistors: low-temperature polysilicon transistors and indium gallium zinc oxide transistor. Accordingly, the display panel using the pixel circuit00may have strong driving capability and low power consumption simultaneously, and may be suitable for high-frequency display and low-frequency display.

The present disclosure does not elaborate on the operation process of the circuit structure shown inFIG.20. Details may be understood by referring to the circuit structure ofFIG.17corresponding toFIG.18and the operation sequence shown inFIG.21. The difference between the operation sequence ofFIG.21and the operation sequence ofFIG.18is as follows. InFIG.18, the fifth transistor T5is turned on when the third scanning signal SCAN3provided by the third scanning signal terminal is at a low level, and the seventh transistor T7is turned on when the fifth scan signal SCAN5provided by the fifth scan signal terminal is at a low level. InFIG.21, the fifth transistor T5is turned on when the third scan signal SCAN3provided by the third scan signal terminal is at a high level, and the seventh transistor T7is turned on when the fifth scan signal SCAN5provided by the fifth scan signal terminal is at a high level. Phases of the third scanning signal SCAN3and the fifth scanning signal SCAN5inFIG.21are opposite to phases of the third scanning signal SCAN3and the fifth scanning signal SCAN5inFIG.18.

FIG.22illustrates a schematic diagram of another electrical connection structure of sub-pixels inFIG.4.FIG.23illustrates a schematic diagram of another electrical connection structure between a plurality of sub-pixels and a multiplexing circuit inFIG.4.FIG.24illustrates an operation timing diagram of an electrical connection structure inFIG.23. Referring toFIGS.4,22,23and24, in one embodiment, the pixel circuit10also includes a second reset module106. The second reset module106includes a sixth transistor T6. A gate of the sixth transistor T6is electrically connected to a second scan signal terminal1021. A first electrode of the sixth transistor T6is electrically connected to the second reference voltage signal terminal REF2. A second electrode of the sixth transistor T6is electrically connected to the anode of the light emitting element20. The cathode of the light emitting element20is connected to the second power signal terminal PVEE. The conduction period of the data line reset module102and the conduction period of the second reset module106at least partially overlap.

In one embodiment, the pixel circuit10also includes a second reset module106, and the second reset module106includes a sixth transistor T6. The first electrode of the sixth transistor T6is electrically connected to the second reference voltage signal terminal REF2. The second electrode of the sixth transistor T6is electrically connected to the anode of the light emitting element20. The cathode of the light emitting element20is connected to the second power signal terminal PVEE. In the reset stage, under the control signal provided by the gate of the sixth transistor T6, the second reset signal Vref2provided by the second reference voltage signal terminal REF2may be provided to the anode of the light emitting element20to reset the light emitting element20. As such, the light emitting element20anode may be initialized. Accordingly, the residue of the display signal of the previous frame in the display process may be reduced, the afterimage phenomenon may be weakened, and the display effect may be improved.

The data line reset module102includes a second transistor T2. A gate of the second transistor T2is electrically connected to the second scan signal terminal1021. The second transistor T2included in the data line reset module102may be used to, in the reset stage, under the control of the second scan signal SCAN2provided by the second scan signal terminal1021, provide the data line reset signal VD to the data line S to reset the data line S.

In one embodiment, the conduction period of the data line reset module102at least partially overlaps with the conduction period of the second reset module106. That is, the conduction time of the sixth transistor T6and the conduction time of the second transistor T2at least partially overlap. The reset time for the anode of the light emitting element20and the reset time for the data line S at least partially overlap. When the sixth transistor T6and the second transistor T2are of a same type, such as P-type transistors, the sixth transistor T6and the second transistor T2are each turned on under a low-potential signal. When the sixth transistor T6and the second transistor T2are of a same type, such as N-type transistors, the sixth transistor T6and the second transistor T2are each turned on under a high potential signal. Accordingly, the sixth transistor T6and the second transistor T2may share the second scan signal terminal1021. As such, the gate of the sixth transistor T6may be electrically connected to the second scan signal terminal1021. That is, the gate of the sixth transistor T6and the gate of the second transistor T2may be controlled by the second scan signal SCAN2provided by a same second scan signal terminal1021to turn on or not.

When arranging scan lines on the panel, the gate of the sixth transistor T6and the gate of the second transistor T2in the pixel circuits10of a same sub-pixel row may be connected to a same scan line. Accordingly, the quantity of driving signals may be reduced, the quantity of overall signal lines in the display panel000may be reduced, and layout space may be saved. As such, a larger space size for the layout of the pixel circuit10may be provided, a narrow frame of the panel may be realized, and panel transmittance may be increased by reducing the quantity of signal lines in the panel.

FIG.25illustrates a schematic diagram of another electrical connection structure of sub-pixels inFIG.4.FIG.26illustrates a schematic diagram of another electrical connection structure between a plurality of sub-pixels and a multiplexing circuit inFIG.4. Referring toFIGS.4,25and26, in one embodiment, the display panel000includes a bias adjustment module109. A first terminal of the bias adjustment module109is electrically connected to the first electrode of the driving transistor DT. A second terminal of the bias adjustment module109is electrically connected to the bias adjustment signal terminal Dbias.

In one embodiment, the pixel circuit10of the display panel000also includes a bias adjustment module109. The first terminal of the bias adjustment module109is electrically connected to the first electrode of the driving transistor DT, and the second terminal of the bias adjustment module109is electrically connected to the bias adjustment signal terminal Dbias. The bias adjustment signal terminal Dbias may be used to provide a bias adjustment signal Vbias for adjusting the bias state of the driving transistor DT. By controlling the bias adjustment module109to write the bias adjustment signal Vbias to the first electrode of the driving transistor DT in part of the operation time of the pixel circuit10, the bias state of the driving transistor DT may be adjusted. Accordingly, the threshold drift problem of the driving transistor DT may be addressed, and the display effect may be improved.

The present disclosure does not limit the operation time of the bias adjustment module109, provided that the operation of the bias adjustment module109is before the light emitting element20emits light. Optionally, in one embodiment, the bias adjustment signal Vbias may be provided by a bias signal line (not shown inFIG.25) in the display panel000. In some other optional embodiments, the bias adjustment signal Vbias may multiplex the driving signal included in the pixel circuit10. The present disclosure does not limit whether the bias adjustment signal Vbias is provided by a bias signal line.

FIG.27illustrates a schematic diagram of another electrical connection structure of a sub-pixel inFIG.4.FIG.28illustrates a schematic diagram of another electrical connection structure between a plurality of sub-pixels and a multiplexing circuit inFIG.4. Referring toFIGS.4,27and28, in one embodiment, the data line reset module102is multiplexed as the bias adjustment module109, and the data line reset signal terminal D is multiplexed as the bias adjustment signal terminal Dbias.

In one embodiment, the data line reset module102in the pixel circuit10may be multiplexed as the bias adjustment module109. That is, in the data line reset stage, when the second scan signal terminal controls the first terminal and the second terminal of the data line reset module102to be turned on, the low-voltage data line reset signal VD provided by the data line reset signal terminal D may be used to adjust the bias voltage of the drive transistor DT. Under the control of the second scan signal SCAN2provided by the second scan signal terminal, the data line reset signal VD may be provided to the first electrode of the drive transistor DT to adjust the bias state of the drive transistor DT. Accordingly, the drive transistor DT may be reverse biased, and the first and second electrodes of the driving transistor DT may be inverted. As such, the internal ion polarization of the driving transistor DT may be weakened, and the threshold voltage of the driving transistor DT may be reduced. Accordingly, the adjustment of the threshold voltage of the driving transistor DT may be realized by multiplexing the second transistor T2of the data line reset module102. The threshold voltage drift caused by the hysteresis effect of the driving transistor DT due to the forward-biased state of the driving transistor DT may be compensated. As such, effects on the display quality due to the hysteresis effect of the driving transistor DT in the display panel000may be weakened, and the display quality may be improved. Since the data line reset module102is multiplexed as the bias adjustment module109, the quantity of transistors in the pixel circuit10may be reduced. As such, the aperture ratio of sub-pixel00in the panel may be increased, and the panel layout space may be saved.

Still referring toFIGS.1and2, the present disclosure also provides a driving method for a display panel. This driving method may be used to drive the display panel000provided by the present disclosure. The driving method at least includes a data line reset stage and a data writing stage, and the data line reset stage is executed before the data writing stage.

In the data line reset stage, the data line reset module102is turned on. The data line reset signal terminal D transmits the data line reset signal VD to the data line S through the data line reset module102to reset the data line S. In the data writing stage, the data writing module101is turned on, and transmits the data voltage signal Vdata of the data line S to the driving transistor DT.

The driving method provided by the present disclosure may be applied to the display panel000illustrated inFIGS.1and2. In the structure of the display panel000, the pixel circuit10includes a data line reset module102. The first terminal of the data line reset module102is electrically connected to the data line S, and the second terminal of the data line reset module102is electrically connected to the data line reset signal terminal D. The data line reset signal terminal D may be used to provide the data line reset signal VD.

In the driving method, the data line reset stage is performed before the data writing stage. When the pixel circuit10of the display panel000operates in the data line reset stage, the data line reset module102is turned on. That is, the first terminal and the second terminal of the data line reset module102are conducted, and the data line reset signal provided by the data line reset signal terminal D electrically connected to the second terminal of the data line reset module102may be transmitted to the data line S, to reset the data line S. Accordingly, the data line reset signal VD provided by the data line reset signal terminal D may be used to clear the residual data voltage value on the data line S of a previous frame before the start of a next frame, to reset the data line S.

The driving method then proceeds to the data writing stage. The data voltage signal Vdata on the data line S may be written into the driving transistor DT, such that the data voltage signal Vdata provided by the data line S of the next frame may avoid the interference by the residual value of the previous frame as much as possible. Then, in the data writing stage of the next frame, the data voltage signal Vdata on the data line S may be fast and fully written into the driving transistor DT through the data writing module101. Accordingly, the problem of insufficient threshold compensation of the driving transistor DT in the pixel circuit10may be addressed, display uniformity may be improved, and display quality may be improved. In addition, the increase of the time of the data writing stage may not be needed, and power consumption may thus be reduced.

Still referring toFIGS.4-8, in some optional embodiments, the display panel000also includes a multiplexing circuit30. The first terminal of the data writing module101is electrically connected to the first electrode of the driving transistor DT, and the second terminal of the data writing module101is electrically connected to one terminal of the data line S. The other terminal of the data line S is electrically connected to the output terminal of the multiplexing circuit30.

In the data writing stage, the data writing module101is turned on and the data line reset module102is turned off. The multiplexing circuit30is turned on. The multiplexing circuit30may transmit the data voltage signal Vdata to the data line S, and then to the driving transistor DT through the data line S.

The driving method may be applied to the display panel000including the multiplexing circuit30. Narrow frames may be achieved for the display panel000including the multiplexing circuit30. Details may be understood with reference to the structure of the multiplexing circuit30described in the present disclosure, and will not be elaborated here.

Following the driving method, in the data writing stage, the data writing module101is turned on, the data line reset module102is turned off, and the multiplexing circuit30is turned on. The multiplexing circuit30may transmit the data voltage signal Vdata to the data line S. The data voltage signal Vdata may be directly transmitted to the driving transistor DT through the data line S. That is, in the data writing stage, the conduction period of the multiplexing circuit30overlaps with the conduction period of the data writing module101. That is, while the first terminal and the second terminal of the data writing module101are conducted in the data writing stage, the multiplexing circuit30is also turned on. While the data voltage signal is transmitted to the data line S through the multiplexing circuit30, the data writing module101is also turned on. Accordingly, the data voltage signal transmitted on the data line S may be synchronously written into the driving transistor DT. By arranging the multiplexing circuit30and the driving method of directly writing the data voltage signal to the gate of the driving transistor DT, a narrow frame design of the display panel000may be realized, and long data writing time may be achieved when the panel is driven. Accordingly, the threshold compensation of the driving transistor DT may be sufficient, display uniformity may be improved, and display quality may be improved.

Still referring toFIGS.4,15-18, in some embodiments, in the display panel000where the driving method is applied, the pixel circuit10also includes a first light emitting control module103, a second light emitting control module104, a first reset module105, a second reset module106, and a threshold compensation module107.

A first terminal of the first light emitting control module103is electrically connected to a first power signal terminal PVDD. A second terminal of the first light emitting control module103is electrically connected to the first electrode of the driving transistor DT.

A first terminal of the second light emitting control module104is electrically connected to the second electrode of the driving transistor DT. A second terminal of the second light emitting control module104is electrically connected to an anode of the light emitting element20. A cathode of the light emitting element20is electrically connected to a second power signal terminal PVEE.

A first terminal of the first reset module105is electrically connected to a first reference voltage signal terminal REF1. A second terminal of the first reset module105is electrically connected to the gate of the driving transistor DT.

A first terminal of the second reset module106is electrically connected to a second reference voltage signal terminal REF2. A second terminal of the second reset module106is electrically connected to the anode of the light emitting element20.

The threshold compensation module107is electrically connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

In one embodiment, the driving method also includes a first reset stage, a second reset stage and a light emitting stage. The data writing stage is executed between the second reset stage and the light emitting stage.

The first reset stage may be understood as a reset stage of the first node N1. At moments Z1-Z3shown inFIG.18, in the first reset stage, the first reset module105is turned on. The first reset signal Vref1provided by the first reference voltage signal terminal REF1is transmitted to the gate of the driving transistor DT (i.e., the first node N1) to reset the gate of the driving transistor DT.

The second reset stage may be understood as a reset stage of the fourth node N4. At moments Z5-Z6shown inFIG.18, in the second reset stage, the second reset module106is turned on. The second reset signal Vref2provided by the second reference voltage signal terminal REF2is transmitted to the anode of the light emitting element20(i.e., the fourth node N4) to reset the anode of the light emitting element20.

In the light emitting stage, after moment Z15shown inFIG.18, the first light emitting control module103, the second light emitting control module104, and the driving transistor DT are turned on. The driving current generated by the driving transistor DT is transmitted to the light emitting element20to drive the light emitting element20to emit light.

The threshold compensation module107may detect and self-compensate for the deviation of the threshold voltage of the driving transistor DT in the data writing stage. The moments Z7-Z14shown inFIG.18are the threshold compensation and data writing stage.

In the driving method, the execution period of the data line reset stage (moments ZA-Z6shown inFIG.18) and the execution period of the second reset stage (moments Z5-Z6shown inFIG.18) at least partially overlap. That is, the conduction time of the data line reset module102and the conduction time of the second reset module106may partially overlap. That is, the reset time for the anode of the light emitting element20and the reset time for the data line S at least partially overlap. Accordingly, the conduction control signal terminal of the data line reset module102and the conduction control signal terminal of the second reset module106may share a signal terminal. As such, the quantity of driving signals may be reduced, the overall quantity of signal lines in the display panel000may be reduced, and the layout space may be saved. The narrow frame of the panel may be achieved, and the panel transmittance may be increased by reducing the quantity of signal lines in the panel.

It may be understood that the above description only briefly illustrates the operation stages of the panel included in the driving method. Specific driving stages in panel operation may be understood with reference to descriptions in the present disclosure corresponding toFIG.18, and will not be elaborated here.

Still referring toFIGS.4,27and28, in some optional embodiments, the display panel000applying the driving method provided by the present disclosure may include a bias adjustment module. The first terminal of the bias adjustment module is electrically connected to the first electrode of the driving transistor DT. The second terminal of the bias adjustment module is electrically connected to the bias adjustment signal terminal. The data line reset module102may be multiplexed as a bias adjustment module. The data line reset signal terminal D may be multiplexed as a bias adjustment signal terminal. By using the data line reset module102multiplexed as the bias adjustment module, the bias adjustment signal (ie, the data line reset signal VD) may be written into the first electrode of the driving transistor DT in part of the operation time of the pixel circuit10. Accordingly, the bias state of the driving transistor DT may be adjusted, the threshold drift problem of the driving transistor DT may be addressed, and the display effect may be improved.

In one embodiment, the driving method also includes a first bias adjustment stage. The first bias adjustment stage is executed before the data writing stage. Since the data line reset module102may be multiplexed as the bias adjustment module, the execution time of the first bias adjustment stage may overlap with the execution time of the data line reset stage. In one embodiment, since the execution time of the first bias adjustment stage may overlap with the execution time of the data line reset stage, the driving time of the panel may be saved, the refresh frequency of the panel may be increased, and high-frequency driving may be achieved. That is, in the first bias adjustment stage, the data line reset module102is turned on, and the data line reset signal VD is provided to the first electrode of the driving transistor DT to adjust the bias state of the driving transistor. Simultaneously, the data line reset signal VD is transmitted to the data line S through the data line reset module102and the data writing module101to reset the data line S.

Following the driving method, in the data line reset stage, when the second scan signal terminal controls the first terminal and the second terminal of the data line reset module102to turn on, the low-voltage data line reset signal VD provided by the data line reset signal terminal D may be used to adjust the bias voltage of the drive transistor DT. Under the control of the second scan signal SCAN2provided by the second scan signal terminal, the data line reset signal VD may be provided to the first electrode of the drive transistor DT to adjust the bias state of the drive transistor DT. Accordingly, the drive transistor DT may be reversely biased, and the first electrode and the second electrode of the driving transistor DT may be inverted. As such, the internal ion polarization of the driving transistor DT may be weakened, and the threshold voltage of the driving transistor DT may be reduced. Accordingly, the adjustment of the threshold voltage of the driving transistor DT may be realized by multiplexing the second transistor T2of the data line reset module102. The threshold voltage drift caused by the hysteresis effect of the driving transistor DT due to the forward-biased state of the driving transistor DT may be compensated. As such, impacts on the display effect due to the hysteresis effect of the driving transistor DT in the display panel000may be reduced, and the display effect may thus be improved. Simultaneously, the data line reset signal VD may be transmitted to the data line S through the data line reset module102and the data writing module101to reset the data line S. Accordingly, the data voltage signal Vdata on the data line S of a next frame may avoid the interference by the residual value of a previous frame as much as possible. As such, in the data writing stage of the next frame, the data voltage signal Vdata on the data line S may be fast and fully written into the driving transistor DT through the data writing module101. As a result, the problem of insufficient threshold compensation of the driving transistor DT in the pixel circuit10may be addressed, the display uniformity may be improved, and display quality may be improved.

Referring toFIGS.4,24,27, and28, in one embodiment, the data line reset module102may be multiplexed as the bias adjustment module, and the reset signal terminal D of the data line may be multiplexed as the bias adjustment signal terminal. By using the data line reset module102multiplexed as the bias adjustment module, the bias adjustment signal (i.e., the data line reset signal VD) may be written into the first electrode of the driving transistor DT in part of the operation time of the pixel circuit10to adjust the bias state of the driving transistor DT. The threshold drift problem of the driving transistor DT may be addressed, and the display effect may be improved. The first bias adjustment stage is executed before the data writing stage, and the execution time of the first bias adjustment stage may overlap with the execution time of the data line reset stage. The first bias adjustment stage may be set to be executed after the first reset stage (after moment Z2shown inFIG.24). After the reset of the first node N1is completed in the first reset stage, the data line reset stage (moments Z4-Z6shown inFIG.24) may be executed, and the bias voltage adjustment may be completed simultaneously. Accordingly, the driving time of the panel may be saved, the refresh frequency of the panel may be increased, and high-frequency driving may be achieved.

FIG.29illustrates another operation timing diagram of an electrical connection structure inFIG.28. Referring toFIGS.4,27,28and29, in one embodiment, the driving method also includes a second bias adjustment stage at moments Z141-Z142as shown inFIG.29. The second bias adjustment stage may be executed between the data writing stage and the light emitting stage (executed between moment Z14and moment Z15). In the second bias adjustment stage, the data line reset module102is turned on. The data line reset signal VD may be provided to the first electrode of the driving transistor DT to adjust the bias state of the driving transistor DT.

In one embodiment, the driving method includes a second bias adjustment stage, and the second bias adjustment stage is executed between the data writing stage and the light emitting stage (executed between moment Z14time and moment Z15). That is, the second bias adjustment stage may be performed after the data writing module101completes writing the data voltage signal and before the light emitting stage. Optionally, the bias adjustment signal Vbias may be a DC positive voltage signal. Regardless of the picture displayed in the previous frame, when writing the data voltage of a current screen, and before the light emitting stage after writing the data voltage of the current screen, the driving transistor DT needs to be written with the bias adjustment signal Vbias for one time. Since the bias adjustment signal Vbias is a high positive voltage value, the bias effect of the previous display frame may be weakened, making the state of the driving transistor DT closer to the default when writing the current display frame. By setting at least two bias adjustment stages in the operation cycle of the pixel circuit10, the time for adjusting the bias state of the driving transistor DT in the driving cycle may be increased. Accordingly, the threshold voltage drift of the driving transistor DT caused by the hysteresis effect may be compensated. The difference in bias voltage of the driving transistor DT when displaying the current frame and the previous frame may be reduced. The threshold drift problem of the driving transistor DT may be addressed, and the display effect may be improved.

The present disclosure also provides a display device.FIG.30illustrates a schematic plan view of a display device consistent with the disclosed embodiments of the present disclosure. Referring toFIG.30, in one embodiment, the display device111includes a display panel000provided by the present disclosure.FIG.30only takes a mobile phone as an example to illustrate the display device111. It may be understood that the display device111provided by the present disclosure may be a computer, a television, a vehicle-mounted display device, or other display devices111with a display function. The present invention does not limit a specific type of display device. The display device111provided by the present disclosure has beneficial effects of the display panel000provided by the present disclosure. For details, reference may be made to specific descriptions of the display panel000in the present disclosure, which will not be elaborated here.

As disclosed, the technical solutions of the present disclosure have the following advantages.

The sub-pixel of the display panel provided by the present disclosure includes a pixel circuit and a light emitting element that are electrically connected. The pixel circuit includes a data writing module electrically connected to a driving transistor. The driving transistor may be used to generate driving current that drives the light emitting element to emit light, realizing the light emitting function of the light emitting element. The data writing module is electrically connected to the data line. The operation stage of the pixel circuit at least includes a data writing stage. In the data writing stage, the data writing module is turned on, and the data voltage signal transmitted on the data line is transmitted to the driving transistor.

The pixel circuit also includes a data line reset module. The first terminal of the data line reset module is electrically connected to the data line, and the second terminal of the data line reset module is electrically connected to a data line reset signal terminal. The data line reset signal terminal may be used to provide the data line reset signal. The operation stage of the pixel circuit also includes a data line reset stage. The data line reset stage is performed before the data writing stage. In the data line reset stage, the data line reset module is turned on, and the data line reset signal provided by the data line reset signal terminal may be transmitted to the data line to reset the data line. Accordingly, the data line reset signal provided by the data line reset signal terminal may be used to clear the residual data voltage value on the data line of a previous frame before a next frame starts to reset the data line. As such, the data voltage signal provided on the data line of the next frame may avoid interference by the residual value of the previous frame as much as possible. Then in the data writing stage of the next frame, the data voltage signal on the data line may be fast and fully written to the driving transistor through the data writing module. Accordingly, the problem of insufficient threshold compensation of drive transistors in the pixel circuit may be addressed, the display uniformity may be improved, and display quality may be improved. In addition, an increase of the time of the data writing stage may not be needed, and power consumption may thus be reduced.

The embodiments disclosed herein are exemplary only and not limiting the scope of the present disclosure. Various combinations, alternations, modifications, equivalents, or improvements to the technical solutions of the disclosed embodiments may be obvious to those skilled in the art. Without departing from the spirit and scope of this disclosure, such combinations, alternations, modifications, equivalents, or improvements to the disclosed embodiments are encompassed within the scope of the present disclosure.