Multiple threshold voltages in field effect transistor devices

A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device.

FIELD OF INVENTION

The present invention relates to semiconductor field effect transistors (FET), and particularly to threshold voltages in FET devices.

DESCRIPTION OF RELATED ART

A FinFET, Tri-Gate, and nanowire devices typically include a non-planar multiple gate transistor device. The device includes a conducting channel disposed on a silicon fin, nanowire, or similar linear structure.

Complimentary metal oxide semiconductor (CMOS) devices exhibit a threshold voltage (Vt). A voltage applied to the gate of an n-type device (gate voltage) that equals or exceeds the threshold voltage induces a low resistance conductive path between the source and drain regions of the device. While a gate voltage that is below the threshold voltage results in little or no conductive path between the source and drain regions.

In electronic circuits with CMOS devices, devices with different threshold voltages are used to realize circuit function. Previous methods of fabricating multiple devices with different threshold voltages included implanting different types of substrate dopants for FET devices that result in different threshold voltages.

BRIEF SUMMARY

In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel on a substrate, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region, a portion of the drain region, and a portion of the substrate, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device.

In another aspect of the present invention, a field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, an ion doped drain region connected to the first conductive channel and the second conductive channel.

DETAILED DESCRIPTION

FIGS. 1-7illustrate an exemplary method for fabricating a FET device having a variety of different threshold voltages (Vt). In this regard,FIG. 1illustrates a perspective view of a substrate102that may include, for example, silicon. A buried oxide (BOX) layer104is disposed on the substrate102. A plurality of conducting channels105a,105b,105c, and105dare arranged on the BOX layer104. The conducting channels105include a layer of silicon106formed on the BOX layer104, and a layer of silicon nitride108formed on the layer of silicon106. The layer of silicon106may also include SiN. The conducting channels may be formed by, for example, forming a layer of silicon on the BOX layer104and forming a layer of silicon nitride on the silicon layer. A lithographic patterning and etching process may be used to remove portions of the silicon and silicon nitride layers to form the conducting channels105. Following the patterning of the conducting channels105n-type dopants (e.g., phosphorus, arsenic, or antimony) or p-type dopants (e.g., boron or aluminum) may be implanted in portions of the conducting channels105to form a source region110and a drain region112connected to the conducting channels105of the device. Alternatively, the devices may be doped following the formation of the gate stacks described below.

Though the illustrated embodiment describes methods for forming a FinFET device (using conducting channels105), alternate embodiments may use similar methods in forming a nanowire FET device. FIGS.

FIG. 2illustrates a side cut-away view of the FET device along the line2-2ofFIG. 1.

Referring toFIG. 3, a layer302is formed over portions of the conducting channels105a,105b,105c, and105dand the BOX layer104. The layer302includes, for example, a high-K material or SiON. The layer302may be formed by, for example, a chemical vapor deposition (CVD) or a plasma-enhanced chemical vapor deposition (PECVD) process.

FIG. 4illustrates the formation of a layer402over the layer302. The layer402may include, for example, a metallic gate material such as, for example, tungsten, titanium, cobalt, or nickel that may be formed by a CVD or PECVD process. The layers302and402form the gate stacks401of FET devices405a,405b,405c, and405d.

It may be desirable to fabricate FET devices having different threshold voltages. For example, the FET405amay have a different threshold voltage than the FETs405b,405c, and405d.

In this regard, referring toFIG. 5, a masking layer502ais deposited over the FETs405b,405c, and405d, leaving the FET405aexposed. The masking layer502amay include, for example, a lithographically patterned layer of silicon nitride material. In the illustrated embodiment, the FET that will be formed with the FET405aremains exposed, however alternate embodiments may cover or expose any number of FET similar to405. Following the formation of the masking layer502a, the device is annealed to activate the implanted dopants. The annealing process changes the threshold voltage (Vt) of the exposed FET405a. The change in threshold voltage (ΔVt) will depend on the parameters used such as annealing temperature, time, ambient fluid, and dopant type will determine the ΔVt for the annealed device. For example, in the illustrated embodiment the annealing process includes heating the device to approximately 550° C. in ambient water vapor or oxygen. The annealing process may be performed, by example, at temperatures ranging from 350° C. to 800° C.; a partial pressure of oxygen or water vapor of between 1 Torr to 100 Torr; and a process time ranging from 30 seconds to 300 seconds. The annealing process results in the introduction of oxygen into the metal gate stack causing a reduction of oxygen vacancy in the stack. The introduction of oxygen in the annealing process results in a ΔVt of the FET405aof approximately +50 mV (for a nFET device) and approximately −50 mV (for a pFET) device.

FIG. 6illustrates the resultant structure following the patterning and removal of portions of the masking layer502a(ofFIG. 5) to expose the FET405bresulting in the masking layer502b. Following the exposure of the FET405bthe device may be annealed in a similar manner as described above; introducing additional oxygen into the exposed gate stacks. In the illustrated exemplary embodiment, the second annealing process uses similar parameters as discussed above resulting in a similar change in Vt for the FETs405aand405b. The resultant Vt for the devices may be described as Vt=x+ΔVt where x is a baseline threshold voltage of the device and n is the number of similar annealing processes performed on an exposed FET405. Thus, the Vt of the FET405amay be defined as Vta=x+(ΔVt*2) where n=2; while the Vt of the FET405bmay be defined as Vtb=x+ΔVt where n=1.

Though the illustrated embodiment uses similar annealing parameters for each annealing process, resulting in a similar ΔVt, different annealing parameters may be used for one or more of the annealing processes resulting in a different ΔVt. For example, if the FET405ais exposed to a first annealing process resulting in a ΔVt1and the FETs504aand405bare exposed to a second annealing process resulting in a ΔVt2, the Vt of the FET405amay be defined as Vta=x+ΔVt1+ΔVt2while the Vt of the FET405bmay be defined as Vtb=x+ΔVt2.

FIG. 7illustrates the resultant structure following the removal of the masking layer502b(ofFIG. 6) to expose the FETs405cand405d. Following the removal of the masking layer, another annealing process may be performed on the devices. For example, following the annealing of the exposed FETs405cand405d, the resultant voltage thresholds for the devices (where the ΔVt is similar for each of the annealing processes) may be defined as Vta=x+(ΔVt*3) where n=3; Vtb=x+(ΔVt*2) where n=2, and Vtc=Vtd=x+ΔVt where n=1.

Though the illustrated exemplary methods above describe forming a FinFET device (using conducting channels105), alternate embodiments may use similar methods in forming other multi-gate devices such as, for example, a nanowire FET device.FIGS. 8-10illustrate an alternate exemplary method for forming FET devices with different threshold voltages in a nanowire FET device.

FIG. 8illustrates a perspective view of a BOX layer104formed on a silicon substrate102. A plurality of nanowire FET devices805a,805b,805c, and805dare formed on the BOX layer104. The FET devices805a-dinclude a nanowire906conducting channel (shown inFIG. 9below) that may include, for example, a silicon material formed by a patterning and etching process. A gate stack is formed over the nanowire906that includes a high-K layer904(shown inFIG. 9below) that is formed on the nanowire906, and a metallic gate layer802is formed on the high-K layer904. The devices may be doped with ions in a similar manner as described above to form a source region810and a drain region812of the device. Once the nanowire FET devices805a-dare formed, similar masking and annealing methods as described above may be performed to vary the threshold voltage in the device.

In this regard,FIG. 9illustrates a side cut-away view of the device along the line9-9(ofFIG. 8). In the illustrated embodiment the masking layer902ais formed over the FET devices805b,805c, and805d. An annealing process similar to the process described above is performed to increase or decrease the threshold voltage of the FET device805a.

FIG. 10illustrates the removal of a portion of the masking layer902aresulting in the masking layer902bthat exposes the FET device805b. Following the exposure of the FET device805b, a second annealing process may be performed in a similar manner as described above.