Methods of making multi-state non-volatile memory cells

A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.

BACKGROUND

This disclosure relates generally to an integrated circuit memory, and more specifically, to a multi-state non-volatile memory cell integration and method of operation.

2. Related Art

One type of non-volatile memory uses traps in an insulating layer for charge storage. One material used in such a manner is silicon nitride. Typically, the nitride charge storage layer is surrounded by other insulating layers such as oxide forming an oxide-nitride-oxide (ONO) structure. Charge stored within the nitride is used to manipulate a threshold voltage of the transistor, and in this manner store data. Another type of non-volatile memory uses nanocrystals for charge storage. A conventional non-volatile memory gate cell typically exists in one of two states representing either a logical zero or a logical one. To increase the capacity of a memory device without significantly increasing the size of the memory, a multi-bit memory cell may be used that is capable of storing more than two states. Non-volatile memory cells of this type, referred to herein as multi-state memory cells, have been historically implemented by controlling the amount of charge that is injected into portions of the nitride charge storage layer.

Multi-state memory cells having nitride or nanocrystals for charge storage and that rely on localization of charge are relatively robust because charge migration is minimal. More specifically, the charge does not spread out through the nitride layer, causing the stored logic states to change. In multi-state non-volatile memory cells that use multiple independent floating gates, it has been necessary to use multiple non-self-aligned masking steps to fabricate the multiple floating gates, significantly increasing the cost of the device due to the increased process complexity and larger size of the memory cell.

Therefore, there is a need for a multi-state non-volatile memory device having good data retention capabilities while also being inexpensive to manufacture.

DETAILED DESCRIPTION

Generally, there is provided, a thin-film storage (TFS) multi-state non-volatile memory cell having multiple gates spaced relatively close together so that inversion layers in the channel regions overlap each other when adjacent gates are biased in a conductive state. There are no source/drain regions between the gates. Charge storage may be by nanocrystal or SONOS (semiconductor oxide nitride oxide semiconductor). There can be any number of gates, and in one embodiment, the number of stored states is equal to the number of gates plus one.

The semiconductor substrate described herein can be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

As used herein the term metal-oxide-semiconductor and the abbreviation MOS are to be interpreted broadly, in particular, it should be understood that they are not limited merely to structures that use “metal” and “oxide” but may employ any type of conductor including “metal” and any type of dielectric including “oxide”. The term field effect transistor is abbreviated as “FET”.

FIG. 1throughFIG. 10illustrate cross-sectional views of a multi-state non-volatile memory cell and a method for making the multi-state non-volatile memory cell in accordance with an embodiment.FIG. 1illustrates a cross-section of multi-state non-volatile memory cell10after charge storage layer16and conductive layer17are formed on semiconductor substrate12. Semiconductor substrate12can be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. Shallow trench isolation (STI)14is first formed in substrate12in accordance with a conventional isolation technique. In one embodiment, to form charge storage layer16, a dielectric stack is formed over substrate12and includes a first insulating layer, a charge storage layer, and a second insulating layer. The first insulating layer may be grown from substrate12. In one embodiment, charge may be stored using a plurality of discrete charge storage elements such as nanocrystals. In the illustrated embodiment, nanocrystals are represented by the small circles in charge storage layer16. These nanocrystals are typically formed of silicon, but the discrete storage elements may also be formed of clusters of material consisting of, for example, germanium, silicon carbide, any number of metals, or any combination of these. In another embodiment, the charge storage layer may be nitride or polysilicon. The second insulating layer is deposited on the charge storage layer. In one embodiment, the second insulating layer is a deposited oxide layer. Conductive layer17is formed over charge storage layer16. Conductive layer17can be any type of metal, such as aluminum or copper, or another type of conductive material such as polysilicon.

FIG. 2illustrates a cross-section of multi-state non-volatile memory cell10after a photo resist layer (not shown) is formed over metal layer17and patterned. Conductive layer17and charge storage layer16are then etched to form gates18,20, and22as lines in conductive layer17. The photoresist layer is then removed.

FIG. 3illustrates a cross-section of multi-state non-volatile memory cell10after an insulating layer24is formed over gates18,20,22, and over exposed portions of substrate12. In one embodiment, insulating layer24is deposited silicon dioxide.

FIG. 4illustrates a cross-section of multi-state non-volatile memory cell10after a conventional chemical mechanical polishing (CMP) procedure is used to remove a top portion of insulating layer24. As illustrated inFIG. 4, in one embodiment, insulating layer24is polished down to the tops of gates18,20, and22.

FIG. 5illustrates a cross-section of multi-state non-volatile memory cell10after a photoresist layer26is formed over insulating layer24and patterned to open an area between the outermost gates18and22.

FIG. 6illustrates a cross-section of multi-state non-volatile memory cell10after portions of insulating layer24are removed from between gates18and20and from between gates20and22.

FIG. 7illustrates a cross-section of multi-state non-volatile memory cell10after a conductive layer30is deposited over a charge storage layer28. Charge storage layer28is over gates18,20, and22, over substrate12between the gates, and over insulating layer24. Charge storage layer28is formed to be substantially the same as charge storage layer16. Conductive layer30may be formed from a metal or other conductive material such as polysilicon. Generally, in one embodiment, conductive layer30comprises the same type of material as in gates18,20, and22.

FIG. 8illustrates a cross-section of multi-state non-volatile memory cell10after a conventional CMP process is used to remove a portion of conductive layer30. In one embodiment, conductive layer30and charge storage layer28are removed to the tops of gates18,20, and22to form gates19and21. As can be seen inFIG. 8, gates18,19,20,21, and22are insulated from each other by only the insulating layers that form a portion of charge storage layers16and28.

FIG. 9illustrates a cross-section of multi-state non-volatile memory cell10after photoresist layer32is formed and patterned. Insulating layer24is then removed from areas not covered by patterned photoresist layer32using conventional etching techniques.

FIG. 10illustrates a cross-section of multi-state non-volatile memory cell10after further processing to form source region34, drain region36, and spacers38. Note that source region34and drain region36also include extensions under spacers38. Also formed, but not illustrated, are other features necessary to complete a device, such as for example, silicide, contacts, various implant and clean steps, and additional metal layers.

FIG. 11illustrates, in partial schematic diagram form, multi-state non-volatile memory cell40and a method for programming the non-volatile memory cell in accordance with an embodiment. Multi-state non-volatile memory cell40is a schematic representation of multi-state non-volatile memory cell10. Multi-state non-volatile memory cell40includes five gate terminals labeled G1-G5and includes state storage units42,44,46,48, and50. A resistor symbol under each of gates G1-G5indicates a channel portion controlled by each of the gates. Because the cells are separated only by charge storage layer28, inversion layers of the cell overlap. The overlapping inversion layers cause a continuous conductive channel to be formed between the source (S) and drain (D) terminals of memory cell40when all of gates G1-G5are biased correctly.

The voltages used to program various state storage units of multi-state non-volatile memory40are illustrated inFIG. 11. As illustrated, the source (S) and drain (D) are connected to power supply voltages VSS and VDD, respectively. In one embodiment, VSS is ground, and VDD is a positive power supply voltage. The gates will receive one of three voltages VP, V1, or V2. Programming voltage VP is a relatively high programming voltage. Voltage V1is applied to state storage units that have not been programmed and are not being programmed in the current programming cycle. Voltage V2is applied to state storage units that have already been programmed in a previous programming cycle. Voltage V1is a voltage level above a threshold voltage of the state storage unit (SSU) when the SSU is in the unprogrammed state. Voltage V2is a voltage level above a threshold voltage of the state storage unit when the SSU is in the programmed state. For simplicity, voltage V1can be set equal to voltage V2.

State storage units42,44,46,48, and50are programmed in order starting with SSU50. In the example ofFIG. 11, three state storage units are programmed using three programming cycles. Programming begins with all of the state storage units in an unprogrammed state, or erased state. To program SSU50, relatively high programming voltage VP is provided to gate G5while voltage V1is provided to gates G1-G4. Voltage VP is high enough to cause Fowler-Nordheim (F-N) tunneling of charge carriers. The actual voltages depend, at least in part, on the process technology used to manufacture the multi-state non-volatile memory. To program state storage unit48, programming voltage VP is provided to gate G4while voltage V1is provided to gates G1-G3and voltage V2is provided to gate G5. To program state storage unit46, programming voltage VP is provided to gate G3while voltage V1is provided to gates G1and G2and voltage V2is provided to gates G4and G5.

Multi-state memory cell40is read by applying a read voltage to all five gates G1-G5. The drain/source current is sensed to determine the stored logic state. Multi-state memory cell40can store up to six different logic states. Generally, in other embodiments having more or fewer gates, the multi-state memory cell can store a number of states equal to the number of gates plus one. The number of gates is limited by the ability of the comparator circuitry to sense and differentiate the currents among the various states.

Multi-state memory cell40is erased by applying a relatively high erase voltage VE to any or all five gates G1-G5with the source (S) and drain (D) connected to power supply voltage VSS. In one embodiment, VSS is ground and voltage VE is a negative voltage.

FIG. 12illustrates a top down view of a multi-state non-volatile memory cell in accordance with another embodiment. InFIG. 12, active regions13and15are surrounded by isolation region14. Gates18-22are formed over active regions13and15using lines of N+ polysilicon. The gates are separated by charge storage layer28. Source/drain regions34and36are formed adjacent to gate18and gate22. P− regions52-56are formed in the polysilicon between the N+ regions and over the isolation region14between active regions13and15. As discussed above regarding multi-state memory cells10and40, state storage units are formed by gates18-22and their underlying channel regions. Another memory cell is formed over active region15having gates18′-22′ formed in the same N+ polysilicon as gates18-22. InFIG. 12, additional state storage units are formed laterally in the polysilicon layers. For example, one state storage unit has a gate formed by P− region52, and a corresponding channel region in P− region53. The gate and channel region are separated by charge storage layer28. Source and drain regions are formed by N+ regions19and19′. Likewise, another state storage unit is formed laterally by P− region53(gate), charge storage layer28, P− region54(channel), and N+ regions20(source/drain) and20′ (source/drain). As can be seen inFIG. 12, four state storage units can be formed using the five N+ polysilicon gate conductors used to form gates18-22and gates18′-22′. Cross-sectional views of the multi-state non-volatile memory cell ofFIG. 12are illustrated along line13-13(FIG. 13) and along line25-25(FIG. 25).

FIG. 13illustrates a cross-sectional view of a portion of the multi-state non-volatile memory cell ofFIG. 12along the line13-13.FIG. 13shows substrate12and isolation region14formed thereon. Charge storage layers16and28and polysilicon gates52-56are formed as described below with reference toFIGS. 15-25. In operation, charge is stored in the more vertically positioned portions of charge storage layer28between the gates. Current flows orthogonal to the plane of the figure. Five gates are illustrated in FIG.13; however, in other embodiments a different number of gates can be formed. The number of additional state storage units formed this way is equal to the number of gates minus one. During a read operation, each vertical, programmed, charge storage region makes the adjacent polysilicon region harder to invert, thereby reducing cell current. Programming and erasing can be accomplished using F-N tunneling.

FIG. 14illustrates a schematic representation of a multi-state non-volatile memory cell59consistent with the embodiment illustrated inFIG. 12. Multi-state non-volatile memory cell59includes state storage units60-68. State storage units60-64are substantially the same as state storage units42,44,46,48, and50ofFIG. 11. State storage units65-68are formed laterally in the polysilicon layers used to form gates52-56.

Programming of state storage units60-64is the basically the same as described above regarding the embodiment ofFIG. 11. A method for programming one or more of state storage units65-68is described herein. To program, for example, SSU68, P− poly region56(gate) is provided with voltage VP, N+ poly region21(source) is set to VSS, N+ poly region21′ (drain) is set to VSS, and P− poly region55(channel) is set to VSS, N+ poly regions18-20and18′-20′ are set to VSS, and P− poly regions52-54are set to VSS. (In the illustrated embodiment, VSS is ground and VDD is a positive voltage.) VP is high enough for F-N tunneling. The actual voltages depend, at least in part, on the process technology used to manufacture the multi-state non-volatile memory. The P− poly region55channel contact acts as a well tie, and channel current conduction is along the sidewall of P− poly region55closest to P− poly region56. To avoid disturbing data stored in the horizontal state storage units, p-type substrate12receives a voltage of V1, where V1is a voltage between VP and VSS that is not high enough for F-N tunneling to VSS or VP. The N+ source and drain regions of the horizontal state storage units are set to V1to maintain low leakage.

To program state storage unit67after programming state storage unit68, P− poly regions55and56are set to VP (P− poly region55is the gate), N+ poly region20is set to VSS (source), N+ poly region20′ is set to VSS (drain), and P− poly region54is set to VSS (channel). N+ poly regions18,19,18′ and19′ are set to VSS, and P− poly regions52-53are set to VSS.

To erase, for example, SSU68, P− poly region56(gate) is set to an erase voltage (VE), and N+ poly region21, N+ poly region21′ and P− poly region55(channel) are set to VSS. N+ poly regions18-20and18′-20′ are set to VSS, and P− poly regions52-54are set to VSS. Erase voltage VE is high enough for F-N tunneling. The actual voltage depends, at least in part, on the process technology used to manufacture the multi-state non-volatile memory. The P− poly region55channel contact acts as a well tie. To avoid disturbing data stored in the horizontal state storage units, p-type substrate12receives a voltage of V2, where V2is a voltage between VE and VSS that is not high enough for F-N tunneling to VSS or VE. The N+ source and drain regions of the horizontal state storage units are set to V2to maintain low leakage.

To read, for example, state-storage unit68, P− poly region56(gate) is set to a low read voltage (VR), N+ poly region21(source) is set to VSS, N+ poly region21′ (drain) is set to approximately ½ VDD, and P− poly region55(channel) is set to VSS. N+ poly regions18-20and18′-20′ are set to VSS, and P− poly regions52-54are set to VSS. The P-poly region55channel contact acts as a well tie, and channel current conduction is along the sidewall of P− poly region55closest to P− poly region56. To minimize the impact of system noise and process variation, reads can be done from both sides of the same charge storage region and the output currents can be averaged. To avoid disturbing data stored in the horizontal state storage units, p-type substrate12and the N+ source and drain regions of the horizontal state storage units are set to VSS.

FIG. 15-FIG.25illustrate cross-sectional views of a multi-state non-volatile memory cell and a method for making the non-volatile memory cell in accordance with an embodiment.FIG. 15illustrates a cross-section of multi-state non-volatile memory cell80after charge storage layer86and polysilicon layer96are formed on semiconductor substrate82. Semiconductor substrate82can be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. Shallow trench isolation (STI)84is first formed in substrate82in accordance with a conventional isolation technique. In one embodiment, to form charge storage layer86, a dielectric stack is formed over substrate82and includes a first insulating layer, a charge storage layer, and a second insulating layer. The first insulating layer may be grown from substrate82. In one embodiment, charge may be stored using a plurality of discrete charge storage elements such as nanocrystals. In the illustrated embodiment, nanocrystals are represented by the small circles in charge storage layer86. These nanocrystals are typically formed of silicon, but the discrete storage elements may also be formed of clusters of material consisting of, for example, germanium, silicon carbide, any number of metals, or any combination of these. In another embodiment, the charge storage layer may include nitride or polysilicon instead of nanocrystals. The second insulating layer is deposited on the charge storage layer. In one embodiment, the second insulating layer is a deposited oxide layer. In one embodiment, polysilicon layer96is formed by depositing polysilicon over charge storage layer86.

FIG. 16illustrates a cross-section of multi-state non-volatile memory cell80after a photo resist layer (not shown) is formed over polysilicon layer96and patterned. Polysilicon layer96and charge storage layer86are then etched to form gates90,92, and94in polysilicon layer96. The photoresist layer is then removed.

FIG. 17illustrates a cross-section of multi-state non-volatile memory cell80after an insulating layer97is formed over gates90,92, and94, and over exposed portions of substrate82. In one embodiment, insulating layer97is deposited silicon dioxide.

FIG. 18illustrates a cross-section of multi-state non-volatile memory cell80after a conventional chemical mechanical polishing (CMP) procedure is used to remove a top portion of insulating layer97. As illustrated inFIG. 18, in one embodiment, insulating layer97is polished down to the tops of gates90,92, and94.

FIG. 19illustrates a cross-section of multi-state non-volatile memory cell80after a photoresist layer106is formed over insulating layer97and patterned to open an area between outermost gates90and94.

FIG. 20illustrates a cross-section of multi-state non-volatile memory cell80after portions of insulating layer97are removed from between gates90and92and from between gates92and94.

FIG. 21illustrates a cross-section of multi-state non-volatile memory cell80after a polysilicon layer89is deposited over a charge storage layer88. Charge storage layer88is over gates90,92, and94, over substrate82between the gates, and over insulating layer97. Charge storage layer88is formed to be substantially the same as charge storage layer86. Polysilicon layer89may be formed by depositing polysilicon. Generally, in one embodiment, polysilicon layer89comprises the same type of material used in gates90,92,94.

FIG. 22illustrates a cross-section of multi-state non-volatile memory cell80after a conventional CMP process is used to remove a portion of polysilicon layer89. In one embodiment, polysilicon layer89and charge storage layer88are removed to the tops of gates90,92, and94to form gates91and93. As can be seen inFIG. 22, gates90,91,92,93, and94are isolated from each other by only the insulating layers that form a portion of charge storage layers86and88.

FIG. 23illustrates a cross-section of multi-state non-volatile memory cell80after N+ source and drain regions100and102are implanted in substrate82. An upper portion of polysilicon gates90-94is removed using an etch selective to oxide and nitride, thereby leaving a portion of charge storage layer88exposed. Nitride sidewall spacers98are formed on the sides of the exposed portions of charge storage layer88and on exposed edges of insulating layer97over gates90and94. Nitride sidewall spacers are formed by first depositing a thin nitride layer. The thin nitride layer is etched to form spacers98.

FIG. 24illustrates a cross-section of multi-state non-volatile memory cell80after gates90-94, source region100, and drain region102are silicided with metal silicide104. Source/drain region100is silicided with silicide105and source/drain region102is silicided with silicide106. A silicide block layer (not shown) is first deposited on both sides of the regions to be silicided in a direction perpendicular to the plane ofFIG. 24so that the silicided regions are not shorted together. Spacers98prevent silicide bridging on the tops of gates90-94.

FIG. 25illustrates a cross-section of multi-state non-volatile memory cell80after additional polishing to remove spacers98and the exposed charge storage layer88. In another embodiment, the additional polishing step may not be performed. Normal processing is then performed to complete other features necessary to complete the device, such as for example, contacts and additional metal layers.

A multi-state non-volatile memory cell constructed in accordance with the above described embodiments provides significantly greater storage for a small amount of surface area and with good data retention.