Processor and method for accessing memory

A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a processor, and more particularly, to a method for a processor to access an external memory.

2. Description of the Prior Art

When a processor is operating, a plurality of internal circuitry modules reads data from or writes data to a Dynamic Random-Access Memory (DRAM). These circuitry modules send a plurality of read/write commands into a DRAM controller to request executing the operation of reading/writing the DRAM.

When the processor sends these read/write commands to the DRAM controller, it does not supply any DRAM-aware protocol scheduling for these read/write commands at the processor-end. Therefore, the burden of the back-end DRAM controller is increased, the efficiency for accessing data is lower, and a response time is longer.

SUMMARY OF THE INVENTION

One of the objectives of the present invention is to provide a processor and a method for accessing memory, which can arrange a sequence of read/write commands transmitted to a memory controller to solve the problems of the prior art.

According to an embodiment of the present invention, a processor comprising a plurality of storage modules and an arbiter is disclosed, wherein the plurality of storage modules are arranged to store and send a plurality of read/write commands at the same time, and the read/write commands are arranged to request reading/writing of a memory external to the processor; and the arbiter coupled to the plurality of storage modules is arranged to receive the plurality of read/write commands of the plurality of storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.

According to another embodiment of the present invention, a method for accessing a memory is disclosed, wherein the method comprises: receiving a plurality of read/write commands from a plurality of storage modules, wherein the plurality of read/write commands are arranged to request reading/writing of a memory; and arrange a sequence of the read/write commands for transmitting to a memory controller.

DETAILED DESCRIPTION

In the following description and in the claims, the term “couple” is intended to mean either an indirect or direct electrical connection.

FIG. 1is a diagram illustrating a processor according to an embodiment of the present invention. As shown inFIG. 1, the processor100comprises a plurality of storage modules, an arbiter110and a bus interface circuit120, a Translation Lookaside Buffer (TLB)132, an L1 data cache133, a write buffer134, and an L2 cache135. In this embodiment, the processor100and the peripheral component102may access a memory106(i.e. read/write the memory106) via a memory controller104, so the processor100and the peripheral component102transmit a plurality of read/write commands to the memory controller104, and the memory controller104reads/writes the memory106according to these read/write commands. The peripheral component102can directly access any peripheral device of the memory106via a Direct Memory Access (DMA) engine, a Peripheral Component Interconnect Express (PCIE) and/or Universal Serial Bus (USB) or other interface. In this embodiment, the processor100can be a related processor such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). In should be noted that the processor100shown inFIG. 1only depicts the parts pertinent to the present invention, and one skilled in the art should understand there are other necessary circuits in the processor100.

In this embodiment, the memory control104is a DRAM controller or an SDRAM controller, and the memory106is a DRAM or an SDRAM.

In the processor100shown inFIG. 1, the storage modules such as the L1 instruction cache130, the storage buffer131, the TLB132, the L1 data cache133, the write buffer134and the L2 cache135are arranged for storing read/write commands, wherein the read/write commands are arranged to request reading/ writing operations of the memory106. The arbiter110receives the read/write commands from these storage modules, and arranges a sequence of the read/write commands for transmitting to the memory controller104. Furthermore, the arbiter110arranges the sequence of the read/write commands for transmitting to the memory controller104according to bank addresses (the bank information140shown inFIG. 1) of the memory read/written by the read/write commands transmitted to the memory controller104so that bank conflicts are prevented.

For accessing the DRAM, when two consecutive accessing commands need to access different pages in the same bank, a longer waiting time is required. After achieving the operation of the first accessing command, the memory controller104first closes the opening page in the bank so that the page to be accessed issued from the second accessing command can be opened, then transmits the read/write commands to the memory106for the access operation. In addition, the above operations concerning opening page, closing page and transmitting read/write commands need a certain waiting time. The waiting time rule can be known by referring to the specifications of SDRAM such as JESD79F, JESD79-2C, and JESD79-3D. As mentioned above, since a longer waiting time is required when two consecutive accessing commands need to access different pages in the same bank, the efficiency of the memory controller104is degraded. In this embodiment, the processor100is further arranged to have a First In First Out (FIFO) register for storing bank addresses of the memory read/written by the read/write commands transmitted to the memory controller104. The arbiter110preferentially transmits the read/write commands for reading/writing to bank addresses different from those stored in the FIFO register to the memory controller104. In this way, bank conflict can be prevented and the efficiency of the memory controller104can be increased.

In another embodiment of the present invention, the arbiter110can be a multi-stage arbiter, wherein the detailed architecture is illustrated inFIG. 2, which is a diagram illustrating a processor according to another embodiment of the present invention. As shown inFIG. 2, the processor200comprises a plurality of storage modules, a plurality of arbiters and interface circuit220, wherein the storage modules at least comprise an L1 instruction cache230, a storage buffer231, a TLB232, an L1 data cache233, a write buffer234, and an L2 cache235. These components have the same functions as their counterparts inFIG. 1described above, except that the arbiters inFIG. 2comprise a plurality of first stage arbiter circuits211_1,211_2,211_3and211_4, and a second stage arbiter circuit212.

In the processor200shown inFIG. 2, the first stage arbiter circuit is only disposed in the storage modules needed to store the read commands, i.e. the storage buffer231and the write buffer234do not have the first stage arbiter circuit inside.

In the processor200shown inFIG. 2, the storage modules such as the L1 instruction cache230, the storage buffer231, the TLB232, the L1 data cache233, the write buffer234, and the L2 cache235are arranged to store the read/write commands, wherein the read/write commands are arranged to request reading/writing of the memory206. The first stage arbiter circuits211_1,211_2,211_3and211_4receive the read commands from the L1 instruction cache230, the TLB232, the L1 data cache233, and the L2 cache235, respectively, and arrange a sequence of the read commands for transmitting to the second stage arbiter circuit212; next, the second stage arbiter circuit212receives the plurality of read/write commands from the storage modules or the first stage arbiter circuit, and arranges a sequence of the read/write commands for transmitting to the memory controller204so as to prevent bank conflict.

FIG. 3is a diagram illustrating accessing physical addresses of the memory via the read/write command. As shown inFIG. 3, the physical address comprises row address information (page number), bank address and column address (page offset). The corresponding address field is different accordingly. In addition, the bank addresses of the read commands transmitted to the second stage arbiter circuit212from the first stage arbiter circuits211_1,211_2,211_3and211_4and the read/write commands transmitted to the memory controller204from the second stage arbiter circuit212are extracted as the bank information shown inFIG. 2to facilitate the first stage arbiter circuits211_1,211_2,211_3and211_4and the second stage arbiter circuit212to arrange the transmitting sequences.

FIG. 4is a diagram illustrating an arbiter circuit400according to an embodiment of the present invention, wherein the arbiter circuit400can be one of the first stage arbiter circuits211_1,211_2,211_3and211_4and the second stage arbiter circuit212shown inFIG. 2. More specifically, assume that the arbiter circuit400is the first stage arbiter circuit211_1, the un-processed read/write commands shown inFIG. 4are the read commands stored in the L1 instruction cache130, and the FIFO register410stores the bank addresses to be read by the read commands transmitted to the second stage arbiter circuit212from the first stage arbiter circuit211_1. For the operation of the arbiter circuit400, the bank address comparator420first compares the bank address to be read by the un-processed read/write commands with the bank addresses stored in the FIFO register410to preferentially select read commands for reading bank addresses different from the bank addresses stored in the FIFO register410. The arbiter circuit400arranges a sequence of the read commands stored in the L1 instruction buffer230for transmitting to the second stage arbiter circuit212according to the bank priority information provided by the bank address comparator420, wherein the arbiter circuit400reads as different banks as possible. This is meant to prevent consecutively transmitting read commands which read a same bank to the second stage arbiter circuit212.

FIG. 5is a diagram illustrating a first stage arbiter circuit and a second stage arbiter circuit according to an embodiment of the present invention, wherein the three bits of information shown inFIG. 5“010”, “001”, “000”, all represent bank addresses to be read by each read command. The first FIFO register510is arranged to store bank addresses in the read commands transmitted to the second stage arbiter circuit212from the first stage arbiter circuit211_1, and the second FIFO register520is arranged to store bank addresses in the read commands transmitted to the memory controller204from the second stage arbiter circuit212. In should be noted that a depth of the first FIFO register510is 2 and a depth of the second FIFO register is 3 in this embodiment, but this is only for illustrative purposes and not a limitation of the present invention. As shown inFIG. 5, it is assumed that the first stage arbiter circuit211_1transmits the read command for reading the bank “010” to the second stage arbiter circuit212first. Since the information stored in the bank address “010” has already been stored in the first FIFO register510, the first stage arbiter circuit211_1preferentially transmits the read command for reading the bank “001” to the second stage arbiter circuit212, then transmits a last read command for reading the bank “010” to the second stage arbiter circuit212.

With respect to the second stage arbiter circuit212, since the read command for reading the bank “010” from the first stage arbiter circuit211_1is sent to the second stage arbiter circuit212first, the second stage arbiter circuit212transmits the read command for reading the bank “010” to the memory controller204from the first stage arbiter circuit211_1. At the following time point, three read commands go to the second stage arbiter circuit212which are going to read the bank addresses “001”, “011”, and “010”, respectively. Since the second FIFO register520stores the bank address “010”, the second arbiter circuit212transmits the read commands for reading the banks “011”, “001” to the memory controller204, then transmits the read command for reading the bank “010” to the memory controller204; At the next time point, three read commands which are going to read the bank address “010”, “111”, “000” go to the second stage arbiter circuit212at the same time. Similarly, the second stage arbiter circuit212transmits the read commands for reading the banks “111”, “000” to the memory controller204then transmits the read command for reading the bank “010” to the memory controller204.

In other embodiments of the present invention, however, when most of the read commands read the same page of the same bank from a cache, the first stage arbiter circuit211_1,211_3and211_4may consecutively transmit the read commands for reading the same bank to increase the reading efficiency.

FIG. 6is a flowchart illustrating a hardware design flow of a processor according to an embodiment of the present invention. As shown inFIG. 6, in step600, the related information of the memory controller104/204and the corresponding bank address are desirable. Next, in step602, the multi-stage arbiter circuit configurative operation is performed. Finally, the Hardware Description Language (HDL) design is performed in step604.

FIG. 7is a flowchart illustrating a hardware design flow of a processor100/200according to another embodiment of the present invention, wherein in step700, the related information of the memory controller104/204and the corresponding bank address are desirable. Next, the HDL design with a configurable arbiter circuit is performed in step702. In the design flow shown inFIG. 7, the exacted bank address may be adjusted according to the corresponding memory controller104/204. Therefore, the designed processor100/200may correspond to different address mapping of memory controllers104/204.

Briefly summarized, the processor and the method for accessing memory provided by the present invention can rearrange a sequence of a plurality of read/write commands for transmitting to a memory controller via an arbiter circuit to prevent bank conflict and increase the efficiency of the memory controller when accessing the memory.