Circuits and Methods for I/O Circuitry TSV Coupling

According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.

The present disclosure is generally related to through-silicon vias (TSVs) at least partially coupled through input/output circuitry of integrated circuit devices.

II. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerful computing devices. For example, a variety of personal computing devices, including wireless telephones, such as mobile and smart phones, gaming consoles, tablets and laptop computers are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality, such as a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such devices can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these devices can include significant computing and networking capabilities. For such devices, there is an ever-increasing demand for greater area efficiency for memory storage capacity and read/write capabilities.

In a three-dimensional (3D) semiconductor stack, either full or partial through-silicon vias (TSVs) would be required to transmit signals out of the back portion of a semiconductor wafer (i.e., substrate). In this context, “full TSV” may be defined as a TSV traversing an entire BEOL (back end of line) stack, while “partial TSV” may be defined as a TSV traversing a portion of the BEOL stack. Currently, TSVs are positioned to go through layers of such devices at a top portion of the substrate and below the BEOL.

In the current state of the art, one or more TSVs are placed outside (e.g., positioned along a side portion) of the memory macro (i.e., a memory macro unit) (e.g., an SRAM memory macro). For example, with reference to larger macros of 3D stacks, such placement outside of the memory macro can displace a TSV required for connection (to another location above or below in a 3D stack) by hundreds of microns (e.g., the size of the larger macro itself). Consequently, such a displacement would cause significant disruption to input/output delay of the 3D stack. One solution to resolve TSV displacement issues may be to piece together a bigger memory macro from multiple smaller memory macros that would fit within the smaller memory macro's pitch. However, such smaller macros would have worse area efficiency (i.e., the bit-cell area/total macro area) due to relatively larger overhead of memory macro peripheral logic. Furthermore, it is also possible that the pitch of the TSVs for a particular technology can be so fine that it would not allow a macro of reasonable size to fit. Accordingly, especially as increasingly finer TSV pitches (i.e., below 10 μm) become viable, there is a need in the the art for more area efficiency in memory macro design.

IV. DETAILED DESCRIPTION

Particular implementations of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers throughout the drawings.

According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output (I/O) circuitry of the memory macro unit. In one example, the memory macro unit includes one or more word-line decoder blocks; two or more memory arrays coupled to the one or more word-line decoder blocks; control circuitry coupled to the one or more word-line decoder blocks and the two or more memory arrays; and respective input/output (I/O) circuitry for each of the two or more memory arrays, wherein each of the I/O circuitry comprises a region for shared: sense amplifier driver circuitry, precharge driver circuitry, and write driver control circuitry.

According to one implementation of the present disclosure, a method includes fabricating a memory macro unit, forming a through silicon via (TSV); and bonding the TSV vertically and at least partially through an input/output (I/O) circuitry of the memory macro unit.

According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.

Typical TSV placement requires a certain amount for “free” back-end and front-end space. However, existing memory macro designs are often too dense to accommodate such TSV placement. Advantageously, inventive aspects of the present invention allow for “feedthrough” TSV (Through Silicon Via) (i.e., configurable TSV) at least partially within an input/output (I/O) circuitry of memory macros (i.e., memory macro units) (e.g., SRAM memory macro) itself. Thus, there would be no need to break down larger memory instances to accommodate TSV placement. Additionally, the inventive aspects also further provide for suitable I/O circuitry placement sites for such TSV placement. The inventive circuits and methods can further be applicable for both face-to-face or face-to-back wafer stacking technologies, as well as monolithic integration technologies. In various implementations, to save area in the placement of TSVs for 3D stacked designs, the inventive aspects modify macros to support TSV channels to run through, at least partially, the input/output (I/O) circuitry of macros (as opposed to outside (i.e., running along a side portion) and adjacent of the semiconductor wafer (e.g., 3D semiconductor stacks)).

In certain schemes and techniques, as described herein, the inventive methods support memory compiler graphical user interfaces (GUI) to generate memory instances (i.e., macros, memory macro units) with TSV feedthrough capability. Moreover, a tiling engine of the memory compiler can support stitching such memory instances together to allow feedthrough TSVs with minimized area penalty. In various implementations, an area “keep out zone” (KOZ) may be included as a surrounding perimeter for TSV placement. Advantageously, such keep out zones may overlap over whitespaces within an input/output (I/O) circuitry of the memory macro. Hence, a higher area utilization may be realized at the system-on-chip (SoC) level. In various examples, the inventive circuits, systems, and methods can be utilized for TSV configuration within macros such as: SRAM, and other memory such as read-only memory (ROM), Dynamic Random Access Memory (DRAM), non-volatile memory (NVM), CAM, or register files.

Certain definitions have been provided herein for reference. The term “macro”, “macro unit” and “instance” have been utilized interchangeably—as in what is delivered from a memory compiler. A “macro” may have “butterfly architecture” (but not required), may be split into “banks”, “column-multiplexing”, and/or various other design features (e.g., power gating, redundancy, write mask) as per the decisions of a macro unit's (e.g., SRAM's) “architecture”. An instance may be “single-banked” or “multi-banked”. Also, each bank is a nearly-complete subset of the memory instance. And a large instance may be broken down into “smaller chunks” (each with separate control, word-line drivers, bit-cell array, and input/output) for substantially performance and power reasons. For a particular “architecture”, the “instance” can have varying number of rows, columns, and banks to achieve the desired capacity. Multiple “instances” can be stitched together to implement a cache at a system-on-chip (SoC) level. Column multiplexers (or column mux) may be as part of input/output (I/O) circuitry (as described herein), and the I/O circuitry may include several other blocks, including, but not limited to: sense amplifier driver circuitry, write driver control circuitry, and precharge device driver circuitry.

Referring toFIG.1, an example portion of an integrated circuit (e.g., a system-on-chip (SoC)) is shown. As illustrated, the integrated circuit may include a memory macro unit100(e.g., static random-access memory (S-RAM) memory macro section implementable on the SoC, ROM, non-volatile memory (NVM), CAM, or register file) and one or more through silicon vias (TSVs) (e.g.,136,138,172,180,182,184) at least partially coupled through the memory macro unit100. As described herein, surrounding each TSV is a respective keep-out-zone (KOZ) (e.g.,137,139,173,181,183). In certain implementations, the one or more TSVs may intersect the memory macro unit100in a substantially perpendicular orientation (i.e., direction) to extend vertically through a 3D memory stack. In particular aspects, the TSVs may be utilized by the SoC for power, ground, input/output signals, or address pre-decoding signals.

As depicted inFIG.1, the memory macro unit100(e.g., core array structure, “floor plan”) may include: a control circuitry (i.e., a control block)110, one or more core arrays120(e.g.,120a,120b, etc.) (i.e., one more bit-cell arrays, memory arrays), respective input/output circuitries (i.e., I/O blocks)130(e.g.,130a,130b), and a word-line decoder circuitry140(i.e., word line decoder block). In certain implementations, the control block110may be coupled to the one or more core arrays120, the respective I/O blocks130a,130b, and the word-line decoder block140. In various implementations, each of the I/O blocks130may include sense amplifier circuitry, a precharge circuitry, one or more column multiplexers, and input and output latches. As shown inFIG.1, as one illustrative example, the TSVs136and138may be placed completely within the respective I/O block130a,130bitself, while the TSVs180and182may be placed partially within the respective I/O block130a,130b.

As illustrated inFIG.1, the I/O block130(130a,130b) may be organized such that the TSVs136,138and corresponding “keep-out-zones” (KOZ) are located in a relative central location of the I/O block130(130a,130b). In other implementations, one or more TSVs and corresponding KOZs may be positioned in other locations of the I/O block including either a proximate end (e.g., region “Y”) or a distal end (e.g., region “X”) to the control circuit110. Likewise, in yet other implementations, one or more TSVs and corresponding KOZs may be positioned in other locations of the I/O block including either a proximate end (e.g., region “Z”) or a distal end (not shown) to the bitcells120(e.g.,120a,120b).

In some implementations, the word-line decoder block140may include first- and second-word line driver circuitries142,144, and a word line pre-decode circuitry146. Also, in an example, in certain candidate “white-space” regions148(i.e., a candidate region without circuitry in the wdx128_min+repeating wdx*_mid) of the word line decoder block140, a TSV172can be accommodated (as discussed in later paragraphs). Surrounding the TSV172, a KOZ173may be included to provide sufficient space between the various surrounding circuitry and the TSV172. As such, when a white space region is relatively large, such a region can be suitable where requirement of a keep-out zone is also relatively large.

In some implementations, adjacent to and surrounding the control block110, one or more other candidate white-space regions152,154, and156may be included. As examples, the white-space region152may be introduced overlapping the control block110and a first I/O block130a; the white-space region154may be introduced between the control block110and the word-line pre-decode block146; and white-space region156may be introduced overlapping the control block110and a second I/O block130b.

Furthermore, in such candidate white-space regions152,154, and156, respective TSVs180,182, and184may be accommodated (as discussed in later paragraphs). In addition, each of the TSVs180,182, and184would also have respective surrounding keep-out zones181,183, and185to provide sufficient space between the various surrounding circuitry and the TSVs180,182, and184.

Referring toFIG.2, an I/O block200is shown according to one example implementation. In certain instances, the I/O block200may correspond to I/O block130a,130b(or any other I/O block with reference toFIGS.3-6as described herein). As illustrated, in one example, the I/O block200(i.e., I/O circuitry) can include four column tiles (i.e., Colmux8_mod[0] to Colmux8_mod[3], “four column multiplexer I/O sections”) (e.g.,212,214,216,218) each of which includes a column multiplexer, sense amplifier, and write driver. In other implementations (not shown), a greater or fewer number of column tiles may be utilized. Advantageously, in one example, as shown, the I/O block200may be organized such that for every 4 bits, sense amplifier driver circuitry, pre-charge device driver circuitry, and write driver control circuitry would be shared and can be placed in one designated region220(i.e., shared circuitry region). By doing so, independent sense amplifier driver circuitry, pre-charge device driver circuitry, and write driver control circuitry would not be required for each column tile. As such, by consolidating the sense amplifier driver circuitry, pre-charge driver circuitry and write driver control circuitry, a region222(e.g., a white-space region, empty-space region) would now be available for a KOZ and respective TSV. Advantageously, the shared circuitry region220can provide additional flexibility to move a TSV and allow for SRAM placement offset, as well as the flexibility to change the TSV density and improve power delivery and IR drop (e.g., referring to voltage drop in the metal wires constituting a power grid before it reaches the power pins of the standard cells).

Referring toFIG.3, an example portion of an integrated circuit (e.g., a system-on-chip (SoC)) is shown. As illustrated, the integrated circuit may include a memory macro unit300(e.g., static random-access memory (S-RAM) memory macro section, a “butterfly architecture” implementable on the SoC, ROM, non-volatile memory (NVM), CAM, or register file) and one or more through silicon vias (TSVs) (e.g.,372,374,380,382) at least partially coupled through the memory macro unit300. In certain implementations, the integrated circuit may include a memory macro unit300and one or more TSVs at least partially coupled (e.g., fully coupled or partially coupled) through the I/O circuitry330(e.g.,330a,330b) of memory macro unit300. In certain implementations, the one or more TSVs may intersect the memory macro unit300in a substantially perpendicular orientation (i.e., direction) to extend vertically through a 3D memory stack.

As depicted inFIG.3, the memory macro unit300(e.g., core array structure, “floor plan”) may include: a control circuitry (i.e., a control block)310, one or more core arrays320(e.g.,320a,320b,320c,320d, etc.) (i.e., one more bit-cell arrays, memory arrays), respective input/output circuitries (i.e., I/O blocks)330(e.g.,330a,330b), and first and second word-line decoder circuitry (i.e., first and second word line decoder blocks)340a,340b. In certain implementations, the control block310may be coupled to the one or more core arrays320, the respective I/O blocks330a,330b, and the first and second word-line decoder blocks340a,340b.

In certain implementations, each of the I/O blocks330a,330bmay include respective shared regions (e.g.360,362) including shared: sense amplifier driver circuitry, precharge driver circuitry, and write driver control circuitry for column tiles352(e.g., colmux8_bot[0:35]) and column tiles354(e.g., colmux8_mod[0:35]) in I/O block330a, as well as column tiles356(e.g., colmux8_bot[0:35]) and column tiles358(e.g., colmux8_mod[0:35]) in I/O block330b. As illustrated, similar to other implementations, KOZs381and383would surround respective TSVs380and382, and are included to provide sufficient space between various surrounding circuitry and the TSVs380,382.

In some implementations, each of the first and second word-line decoder blocks340(340a340b) may include first and second word line driver circuitries (342,344;343,345) and a word line pre-decode circuitry (346,347). Also, in an example, in certain candidate “white-space” regions348,349(i.e., a candidate region without circuitry in the wdx128_min+repeating wdx*_mid) of the first and second word line decoder blocks340a,340b, a respective TSV372,374can be accommodated (as discussed in later paragraphs). Surrounding each of the TSVs372,374, a respective “keep-out zone”373,375would be included to provide sufficient space between the various surrounding circuitry and the TSVs372,374. As such, when white space regions are relatively large, such regions are suitable where requirement of a keep-out zone is also relatively large.

Referring toFIG.4, an example portion of an integrated circuit (e.g., a system-on-chip (SoC)) is shown. As illustrated, the integrated circuit may include a memory macro unit400(e.g., static random-access memory (S-RAM) memory macro section, a “butterfly architecture” implementable on the SoC, ROM, non-volatile memory (NVM), CAM, or register file) and one or more through silicon vias (TSVs) (e.g.,472,474,480,482,484,486) at least partially coupled through the memory macro unit400. In certain implementations, the integrated circuit may include a memory macro unit400and one or more TSVs at least partially coupled through the I/O circuitry430(e.g.,430a,430b) of memory macro unit400. In various implementations, the one or more TSVs may intersect the memory macro unit400in a substantially perpendicular orientation (i.e., direction) to extend vertically through a 3D memory stack.

As depicted inFIG.4, the memory macro unit400(e.g., core array structure, “floor plan”) may include: a control circuitry (i.e., a control block)410, one or more core arrays420(e.g.,420a,420b,420c,420d, etc.) (i.e., one more bit-cell arrays, memory arrays), respective input/output circuitries (i.e., I/O blocks)430(e.g.,430a,430b), and first and second word-line decoder circuitry (i.e., first and second word line decoder blocks)440(e.g.,440a,440b). In certain implementations, the control block410may be coupled to the one or more core arrays420, the respective I/O blocks430a,430b, and the first and second word-line decoder blocks440a,440b.

In certain implementations, each of the I/O blocks430(e.g.,430a,430b) may include respective shared regions (e.g.460,462) including shared: sense amplifier driver circuitry, precharge driver circuitry, and write driver control circuitry for column tiles463(e.g., colmux8_bot[0:35]) and column tiles465(e.g., colmux8_mod[0:35]) in I/O block430a, as well as column tiles467(e.g., colmux8_bot[0:35]) and column tiles469(e.g., colmux8_mod[0:35]) in I/O block430b. As illustrated, similar to other implementations, KOZs481and483would surround respective TSVs480and482, and are included to provide sufficient space between various surrounding circuitry and the TSVs480,482. Advantageously, the implementation ofFIG.4can be configured to accommodate several TSVs per memory macro unit.

In some implementations, each of the first and second word-line decoder blocks440(440a,440b) may include first and second word line driver circuitries (442,444;443,445) and a word line pre-decode circuitry (446,447). Also, in an example, in certain candidate “white-space” regions448,449(i.e., a candidate region without circuitry in the wdx128_min+repeating wdx*_mid) of the first and second word line decoder blocks440a,440b, a respective TSV472,474can be accommodated (as discussed in later paragraphs). Surrounding each of the TSVs472,474, a respective “keep-out zone”473,475would be included to provide sufficient space between the various surrounding circuitry and the TSVs472,474. As such, when white space regions are relatively large, such regions are suitable where requirement of a keep-out zone is also relatively large.

In some implementations, as illustrated inFIG.4, adjacent to and surrounding the control block410, one or more other candidate white-space regions452,454,456,458may be included. As examples, the white-space region452may be introduced between the control block410and a first I/O block430a; the white-space region454may be introduced between the control block410and the first word-line pre-decode block446; the white-space region456may be introduced between the control block410and a second I/O block430b; and the white space region458may be introduced between the control block410and the second word-line pre-decode block447.

Furthermore, in such candidate white-space regions452,454,456, and458, respective TSVs480,482,484, and486may at least partially be accommodated (as discussed in later paragraphs). In addition, each of the TSVs480,482,484, and486would also have respective surrounding keep-out zones (KOZs)481,483,485, and487to provide sufficient space between the various surrounding circuitry and the respective TSVs480,482,484, and486. In certain examples, the keep out zone (KOZ)481may partially be included in the white-space region452as well as the I/O block430a. Similarly, the keep out zone (KOZ)483may partially be included in the white-space region456as well as the I/O block430b. Advantageously, such candidate white-space regions allow for the accommodation of at least a few TSV per macro, and would still be more area efficient than potentially breaking a macro into smaller macros to fit into a desired TSV pitch.

Referring toFIG.5, an example portion of an integrated circuit (e.g., a system-on-chip (SoC)) is shown. As illustrated, the integrated circuit may include a memory macro unit500(e.g., static random-access memory (S-RAM) memory macro section, a “butterfly architecture” implementable on the SoC, ROM, non-volatile memory (NVM), CAM, or register file) and one or more through silicon vias (TSVs) (e.g.,572,574,580,582,584,586,592,594,596,598) at least partially coupled through the memory macro unit500. In certain implementations, the integrated circuit may include a memory macro unit500and one or more TSVs at least partially coupled through the I/O circuitry530(e.g.,530a,530b) of memory macro unit500. In various implementations, the one or more TSVs may intersect the memory macro unit500in a substantially perpendicular orientation (i.e., direction) to extend vertically through a 3D memory stack.

As depicted inFIG.5, the memory macro unit500(e.g., core array structure, “floor plan”) may include: a control circuitry (i.e., a control block)510, one or more core arrays520(e.g.,520a,520b,520c,520d, etc.) (i.e., one more bit-cell arrays, memory arrays), respective input/output circuitries (i.e., I/O blocks)530(e.g.,530a,530b), and first and second word-line decoder circuitry (i.e., first and second word line decoder blocks)540(e.g.,540a,540b). In certain implementations, the control block510may be coupled to the one or more core arrays520, the respective I/O blocks530a,530b, and the first and second word-line decoder blocks540a,540b.

In various implementations, each of the I/O blocks530(e.g.,530a,530b) may include respective shared regions (e.g.560,562) including shared: sense amplifier driver circuitry, precharge driver circuitry, and write driver control circuitry for column tiles563(e.g., colmux8_bot[0:35]) and column tiles565(e.g., colmux8_mod[0:35]) in I/O block430a, as well as column tiles567(e.g., colmux8_bot[0:35]) and column tiles569(e.g., colmux8_mod[0:35]) in I/O block530b. As illustrated, similar to other implementations, KOZs581and583would surround respective TSVs580and582, and are included to provide sufficient space between various surrounding circuitry and the TSVs580,582. Advantageously, the implementation ofFIG.5can be configured to accommodate several TSVs per memory macro unit.

As illustrated inFIG.5, each of the one or more core arrays520(e.g.,520a,520b,520c,520d) may be divided up into multiple sections by the inclusion of break cells (e.g.,523,525). As one example, first and second break cells523,525are included in each of the one or more core arrays520to separate each core array into four bit-cell sections (e.g.,522a,522b,522c,522d;524a,524b,524c,524d;526a,526b,526c,526d; and528a,528b,528c,528d). In some cases, the first break cells523may be utilized for substrate ground taps or bit-line resistive-capacitive (RC) optimization schemes involving specialized routing or hierarchy. In some cases, the second break cells525may be used for word-line re-buffering.

In doing so, a TSV (e.g.,592,594,596, and598) may be placed in a respective middle portion “white-space” of each of the core arrays520in alignment with the intersection of the first and second break cells523,525. Moreover, similar to other implementations, surrounding each of the TSVs592,594,596, and598, a respective “keep-out zone”593,595,597, and599would be included to provide sufficient space between the various surrounding circuitry and the TSVs592,594,596, and598.

Similar to other implementations, in some cases, each of the first and second word-line decoder blocks540(540a,540b) may include first and second word line driver circuitries (542,544;543,545) and a word line pre-decode circuitry (546,547). Also, in an example, in certain candidate “white-space” regions548,549(i.e., a candidate region without circuitry in the wdx128_min+repeating wdx*_mid) of the first and second word line decoder blocks540a,540b, a respective TSV572,574can be accommodated (as discussed in later paragraphs). Surrounding each of the TSVs572,574, a “keep-out zone”573,575would be included to provide sufficient space between the various surrounding circuitry and the respective TSV572,574.

In some implementations, as illustrated inFIG.5, adjacent to and surrounding the control block510, one or more other candidate white-space regions552,554,556,558may be included. As examples, the white-space region552may be introduced between the control block510and a first I/O block530a; the white-space region554may be introduced between the control block510and the first word-line pre-decode block546; the white-space region556may be introduced between the control block510and a second I/O block530b; and the white space region558may be introduced between the control block510and the second word-line pre-decode block547.

Furthermore, in such candidate white-space regions552,554,556, and558, respective TSVs580,582,584, and586may be at least partially accommodated (as discussed in later paragraphs). In addition, each of the TSVs580,582,584, and586would also have respective surrounding keep-out zones (KOZs)581,583,585, and587to provide sufficient space between the various surrounding circuitry and the respective TSVs580,582,584, and586. In certain examples, the keep out zone (KOZ)581may partially be included in the white-space region552as well as the I/O block530a. Similarly, the keep out zone (KOZ)583may partially be included in the white-space region556as well as the I/O block530b. Advantageously, such candidate white-space regions allow for the accommodation of at least a few TSV per macro, and would still be more area efficient than potentially breaking a macro into smaller macros to fit into a desired TSV pitch.

Referring toFIG.6, an example portion of an integrated circuit (e.g., a system-on-chip (SoC)) is shown. As illustrated, the integrated circuit may include one or more folded-pairs of a memory macro unit600(e.g., static random-access memory (S-RAM) memory macro section, a “butterfly architecture” implementable on the SoC, ROM, non-volatile memory (NVM), CAM, or register file) and one or more through silicon vias (TSVs) (e.g.,680,682,684) at least partially coupled through the memory macro unit600. In certain implementations, the integrated circuit may include a memory macro unit600and one or more TSVs at least partially coupled (e.g., fully coupled (as illustrated inFIG.6) or partially coupled (not shown inFIG.6, but illustrated inFIGS.4and5) through the I/O circuitry630(e.g.,630a,630b) of memory macro unit600.

In various implementations, the one or more TSVs may intersect the memory macro unit600in a substantially perpendicular orientation (i.e., direction) to extend vertically through a 3D memory stack. Advantageously, such folding of the memory macro unit600and the use of TSVs allow for the routing of critical global signals that can be extended to two or more tier levels of a 3D stack. Examples of such global signals may include the external clock, internal memory clock, the pre-decoded addresses, memory bank read output, and memory bank write input.

As depicted inFIG.6, on each tier, the memory macro unit600(e.g., core array structure, “floor plan”) may include: a control circuitry (i.e., a control block)610(e.g.,610a,610b), one or more core arrays620(e.g.,620a,620b,620c,620d, etc.) (i.e., one more bit-cell arrays, memory arrays), respective input/output circuitries (i.e., I/O blocks)630(e.g.,630a,630b), and first and second word-line decoder circuitry (i.e., first and second word line decoder blocks)640(e.g.,640a,640b(not shown but present). In certain implementations, on each tier, the control block610may be coupled to the one or more core arrays620, the respective I/O blocks630, and the first and second word-line decoder blocks640a,640b.

In various implementations, each of the I/O blocks630(e.g.,630a,630b),632(e.g.,632a,632b) may include respective shared regions (e.g.660a,660b,662a,662b) including shared: sense amplifier driver circuitry, precharge driver circuitry, and write driver control circuitry for column tiles663a,663b(e.g., colmux8_bot[0:35]) and column tiles665a,665b(e.g., colmux8_mod[0:35]) in I/O block630a,630b, as well as column tiles667a,667b(e.g., colmux8_bot[0:35]) and column tiles669a,669b(e.g., colmux8_mod[0:35]) in I/O block632a,632b. As illustrated, similar to other implementations, KOZs681a,681band683a,683bwould surround respective TSVs680and682, and are included to provide sufficient space between various surrounding circuitry and the TSVs680,682. Advantageously, the implementation ofFIG.5can be configured to accommodate several TSVs per memory macro unit.

Similar to other implementations, in some cases, on each of the first and second tiers of the memory macro500, each of the first and second word-line decoder blocks640(640a640b) may include first and second word line driver circuitries (642,644;643,645) and a word line pre-decode circuitry (646,647). Also, in an example, in certain candidate “white-space” regions648,649(i.e., a candidate region without circuitry in the wdx128_min+repeating wdx*_mid) of the first and second word line decoder blocks640a,640b, a respective TSV (not shown inFIG.6, but would be present in certain implementations) can be accommodated (as discussed in later paragraphs). Surrounding each of the TSVs, a “keep-out zone” (not shown inFIG.6, but would be present in certain implementations) would be included to provide sufficient space between the various surrounding circuitry and the respective TSV.

Similar to other implementations, in some cases, as illustrated inFIG.6, adjacent to and surrounding the control block610(610a,610b), one or more other candidate white-space regions652(652a,652b),654(654a,654b) and656(656a,656b) may be included. As examples, on a first tier, the white-space region652amay be introduced between the control block610and a first I/O block630a; the white-space region654amay be introduced between the control block610aand the first word-line pre-decode block646; and the white-space region656amay be introduced between the control block610aand a second I/O block630b. Moreover, on a second tier, the white-space region652bmay be introduced between the control block610band a first I/O block632aof a second tier; the white-space region654bmay be introduced between the control block610band the second word-line pre-decode block647; and the white-space region656bmay be introduced between the control block610band a second I/O block632b.

In one example, in a candidate white-space region654(654a,654b), a respective TSV584may be accommodated (as discussed in later paragraphs). In addition, as illustrated, respective TSVs680and682may be accommodated within the I/O blocks630(630a,630b) and632(632a,632b). In other implementations (not shown), TSV placement may be accommodated at least partially within the I/O block630(630a,630b) and white-space regions652(652a,652b), as well as at least partially within the I/O block632(632a,632b) and white-space regions656(656a,656b). Moreover, each of the TSVs680,682,684would also have respective surrounding keep-out zones681(681a,681b),683(683a,683b) and685(685a,685b) to provide sufficient space between the various surrounding circuitry and the TSVs680,682, and684.

Also, while not shown inFIG.6, similar toFIG.4, each of the one or more core arrays620(e.g.,620a,620b,620c,620d) may be divided up into multiple sections by the inclusion of break cells. As one example, first and second break cells can be included in each of the one or more core arrays620to separate each core array into four bit-cell sections. In some cases, the first break cells may be utilized for substrate ground taps or bit-line resistive-capacitive (RC) optimization schemes involving specialized routing or hierarchy. In some cases, the second break cells may be used for word-line re-buffering.

In doing so, a TSV may be placed in a respective middle portion “white-space” of each of the core arrays620in alignment with the intersection of the first and second break cells. Moreover, similar to other implementations, surrounding each of such TSVs, a respective “keep-out zone” would be included to provide sufficient space between the various surrounding circuitry and the TSVs.

Referring toFIG.7, a flowchart of an example formation method700(i.e., procedure) to for feedthrough TSV integration is shown. Advantageously, in various implementations, the method700depicts the fabrication method steps for a three-dimensional semiconductor stack. The method700may be implemented with reference to circuit implementations as shown inFIGS.1-6.

At block710, the method includes fabricating a memory macro unit. For instance, with reference to various implementations as described inFIGS.1-6, a memory macro unit (100,300,400,500,600) may be fabricated from a multi-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion, and junction isolation) during which electric circuits are gradually created on a wafer made of semiconducting material.

At block720, the method includes forming a through silicon via (TSV). For instance, with reference to various implementations as described inFIGS.1-6, a through silicon via (TSV) (e.g.,136,138,172,184,180,182,372,374,380,382,472,474,480,482,484,486,572,574,580,582,584,586,592,594,596,598,680,682,684) may be formed by etching a TSV trench from a substrate, filling the TSV trench with copper, and fabricating a back-end-of-line (BEOL) wiring to be coupled to the TSV.

At block630, the method includes bonding the TSV vertically and at least partially through an input/output circuitry of the memory macro unit. For instance, with reference to various implementations as described inFIGS.1-5, a through silicon via (TSV) (e.g.,136,138,172,184,180,182,372,374,380,382,472,474,480,482,484,486,572,574,580,582,584,586,592,594,596,598,680,682,684) may be bonded vertically and at least partially through an input/output circuitry (e.g.,130a,130b;200a,200b;330a,330b;430a,430b;530a,530b;630a,630b;632a,632b) of the memory macro unit (100,300,400,500,600).

Also, according to other aspects of the operational method, the TSV may be revealed by removing a layer from a back portion of a substrate (e.g., semiconductor wafer). In other aspects, the TSV may be adjoined to a back-end-of-line (BEOL) stack, where the BEOL stack can be coupled to a face-to-face semiconductor wafer bond.

As one consequence of TSV pitches increasingly becoming “finer” (e.g., below 10 μm) having size dimensions smaller than the memory macro itself, in the current state of the art, TSVs had to be placed outside of a memory macro. (In various design, having a finer TSV pitch is desirable for multiple reasons including superior signal connectivity, and favorable power distribution and heat removal capabilities.) However, outside TSV placement would be problematic for larger size dimension macros as doing so would displace a required TSV (for connection to another location above or below in a 3D stack) by hundreds of microns (e.g., the size of the macro unit itself), and thus cause I/O delay for the overall 3D stack. The below inventive method provides one solution for this concern.

Referring toFIG.8, a flowchart of an example operational method800(i.e., procedure) to automatically optimize a memory compiler is shown. Advantageously, in various implementations, the method800may flexibly account for area requirements of memory architecture in real-time. The method800may be implemented with reference to circuit implementations as shown inFIGS.1-6.

At block810, the method includes receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs). For instance, with reference to various implementations as described inFIGS.1-7, a central processing unit (as shown inFIG.9) may execute software instructions based on one or more of received user provided TSV size dimensions (i.e., one or more TSV pitch values).

At block820, the method includes determining whether dimensions of a memory macro unit is greater than a size threshold, where the size threshold corresponds to the received user input. For instance, with reference to various implementations as described inFIGS.1-6, a central processing unit (as shown inFIG.9) may execute software instructions (i.e., a memory compiler software program) to determine whether dimensions of a memory macro unit is greater than a size threshold, where the size threshold corresponds to the received user input (i.e., user provided/user input TSV pitch value(s) on the circuit design).

At block830, the method includes determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit. For instance, with reference to various implementations as described inFIGS.1-7, a central processing unit (as shown inFIG.9) may execute software instructions to determine one or more optimized TSV positionings at least partially in an input/output circuitry of the memory macro unit based on whether the determined dimensions of the memory macro unit is greater than the size threshold corresponding to the received user input.

Also, according to other aspects of the operational method, an output may be generated based on the determined optimized positioning. For example, with reference to various implementations as described inFIGS.1-6, an output (i.e., an integrated circuit design) (e.g., a memory architecture, multi-threshold offerings for memory compilers) may be generated based on the determined one or more optimized TSV positionings. In some implementations, the circuit design tool924(as described with reference toFIG.9) may allow users to input a TSV pitch value, and generate memory macro unit(s) that either fit within a predetermined TSV pitch or provide a feed-through TSV option (i.e., an option allowing for at least a partial coupling through (i.e., at least partially within) an input/output circuitry of the memory macro unit(s)).

FIG.9illustrates example hardware components in the computer system900that may be used to determine an optimized TSV positioning and to generate an integrated circuit design/memory architecture output. In certain implementations, the example computer system900(e.g., networked computer system and/or server) may include circuit design tool924) and execute software based on the procedure as described with reference to the method800inFIG.8. In certain implementations, the circuit design tool924may be included as a feature of an existing memory compiler software program allowing users to input a TSV pitch, and generate memory macros that either fit within the TSV pitch or provide a feed-through TSV option (i.e., an option allowing for at least a partial coupling through (i.e., at least partially within) the memory macro unit(s)).

The circuit design tool924may provide generated computer-aided physical layout designs for memory architecture. The procedure900may be stored as program code or as instructions917in the computer readable medium of the storage device916(or alternatively, in memory914) that may be executed by the computer910, or networked computers920,930, other networked electronic devices (not shown) or a combination thereof. In certain implementations, each of the computers910,920,930may be any type of computer, computer system, or other programmable electronic device. Further, each of the computers910,920,930may be implemented using one or more networked computers, e.g., in a cluster or other distributed computing system.

In certain implementations, the system900may be used with semiconductor integrated circuit (IC) designs that contain all standard cells, all blocks or a mixture of standard cells and blocks. In a particular example implementation, the system900may include in its database structures: a collection of cell libraries, one or more technology files, a plurality of cell library format files, a set of top design format files, one or more Open Artwork System Interchange Standard (OASIS/OASIS.MASK) files, and/or at least one EDIF file. The database of the system900may be stored in one or more of memory914or storage devices916of computer910or in networked computers920,930.

The system900may perform the following functions automatically, with variable user input: determination of read current requirements/thresholds, determination of leakage current requirements/thresholds, identification of logic designs (i.e., periphery circuit designs (i.e., logic threshold voltages, threshold voltage implant layers)), determination of a desired threshold voltage-combination, determination of minimum voltage assist requirements, identification of bit-cell types, determination of memory specific optimization modes (memory optimization mode), floor-planning, including generation of cell regions sufficient to place all standard cells; standard cell placement; power and ground net routing; global routing; detail routing and pad routing. In some instances, such functions may be performed substantially via user input control. Additionally, such functions can be used in conjunction with the manual capabilities of the system900to produce the target results that are required by a designer. In certain implementations, the system900may also provide for the capability to manually perform functions such as: cell region creation, block placement, pad and cell placement (before and after automatic placement), net routing before and after automatic routing and layout editing. Moreover, verification functions included in the system800may be used to determine the integrity of a design after, for example, manual editing, design rule checking (DRC) and layout versus schematic comparison (LVS).

In one implementation, the computer900includes a central processing unit (CPU)912having at least one hardware-based processor coupled to a memory914. The memory914may represent random access memory (RAM) devices of main storage of the computer910, supplemental levels of memory (e.g., cache memories, non-volatile or backup memories (e.g., programmable or flash memories)), read-only memories, or combinations thereof. In addition to the memory914, the computer system900may include other memory located elsewhere in the computer910, such as cache memory in the CPU912, as well as any storage capacity used as a virtual memory (e.g., as stored on a storage device916or on another computer coupled to the computer910).

The computer910may further be configured to communicate information externally. To interface with a user or operator (e.g., a circuit design engineer), the computer910may include a user interface (I/F)918incorporating one or more user input devices (e.g., a keyboard, a mouse, a touchpad, and/or a microphone, among others) and a display (e.g., a monitor, a liquid crystal display (LCD) panel, light emitting diode (LED), display panel, and/or a speaker, among others). In other examples, user input may be received via another computer or terminal. Furthermore, the computer910may include a network interface (UF)915which may be coupled to one or more networks940(e.g., a wireless network) to enable communication of information with other computers and electronic devices. The computer960may include analog and/or digital interfaces between the CPU912and each of the components914,915,916, and918. Further, other non-limiting hardware environments may be used within the context of example implementations.

The computer910may operate under the control of an operating system928and may execute or otherwise rely upon various computer software applications, components, programs, objects, modules, data structures, etc. (such as the programs associated with the procedure800and the method600and related software). The operating system928may be stored in the memory914. Operating systems include, but are not limited to, UNIX® (a registered trademark of The Open Group), Linux® (a registered trademark of Linus Torvalds), Windows® (a registered trademark of Microsoft Corporation, Redmond, WA, United States), AIX® (a registered trademark of International Business Machines (IBM) Corp., Armonk, NY, United States) i5/OS® (a registered trademark of IBM Corp.), and others as will occur to those of skill in the art. The operating system928in the example ofFIG.9is shown in the memory914, but components of the aforementioned software may also, or in addition, be stored at non-volatile memory (e.g., on storage device916(data storage) and/or the non-volatile memory (not shown). Moreover, various applications, components, programs, objects, modules, etc. may also execute on one or more processors in another computer coupled to the computer910via the network940(e.g., in a distributed or client-server computing environment) where the processing to implement the functions of a computer program may be allocated to multiple computers920,930over the network940.

In example implementations, circuit macro diagrams have been provided inFIGS.1-6, whose redundant description has not been duplicated in the related description of analogous circuit macro diagrams. It is expressly incorporated that the same cell layout diagrams with identical symbols and/or reference numerals are included in each of embodiments based on its corresponding figure(s).

Although one or more ofFIGS.1-9may illustrate systems, apparatuses, or methods according to the teachings of the disclosure, the disclosure is not limited to these illustrated systems, apparatuses, or methods. One or more functions or components of any ofFIGS.1-9as illustrated or described herein may be combined with one or more other portions of another ofFIGS.1-9. Accordingly, no single implementation described herein should be construed as limiting and implementations of the disclosure may be suitably combined without departing form the teachings of the disclosure.

These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus. The machine is an example of means for implementing the functions/acts specified in the flowchart and/or block diagrams. The computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the functions/acts specified in the flowchart and/or block diagrams.

The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to perform a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagrams.

Reference herein to “one example” means that one or more feature, structure, or characteristic described in connection with the example is included in at least one implementation. The phrase “one example” in various places in the specification may or may not be referring to the same example.

Illustrative, non-exhaustive examples, which may or may not be claimed, of the subject matter according to the present disclosure are provided below. Different examples of the device(s) and method(s) disclosed herein include a variety of components, features, and functionalities. It should be understood that the various examples of the device(s) and method(s) disclosed herein may include any of the components, features, and functionalities of any of the other examples of the device(s) and method(s) disclosed herein in any combination, and all of such possibilities are intended to be within the scope of the present disclosure. Many modifications of examples set forth herein will come to mind to one skilled in the art to which the present disclosure pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.