Method of qualifying a process tool with wafer defect maps

A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of evaluating equipment defects for qualifying process tools used in the manufacture of integrated circuit dies on semiconductor wafers.

2. Description of Related Art

In previous methods used for qualifying process tools used in the manufacture of integrated circuit dies, equipment defects are evaluated by counting the number of defective dies on a wafer, transferring the wafer to a process tool, processing the wafer in the process tool, returning the wafer from the process tool, counting the number of defects on the wafer again, and subtracting the first defect count from the second to obtain the number of defects that were added to the wafer by the process tool. If more than a predetermined number of defects, or “adders”, were added to a wafer during the qualification check, then the process tool fails the qualification check. An investigation into the cause of the performance is then conducted to find a repair solution. When the process tool has been repaired, the qualification test is repeated, and so on, until the process tool passes the qualification test. At that point, production runs may be made with minimum loss in yield due to the process tool performance. Disadvantageously, identifying the cause of a problem in the process tool performance may require a large amount of time, which translates into higher production costs.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

In another aspect of the present invention, a computer program product for qualifying a process tool includes:a medium for embodying a computer program for input to a computer; anda computer program embodied in the medium for causing the computer to perform steps of:(a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer;(b) subjecting the semiconductor wafer to processing by the process tool;(c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and(d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to point out distinctive features in the illustrated embodiments of the present invention.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 1illustrates a typical spreadsheet of the prior art for displaying the results of a process tool qualification check.

To generate the results shown in the example ofFIG. 1, two wafers are scanned by a laser beam. The wafers may be patterned with integrated circuit dies, or the wafers may be unpatterned. In either case, any particles or scratches on the surface of each wafer will deflect the scanning laser beam to a photodetector. The photodetector generates a pulse each time the laser beam is deflected that increments a total defect count for each wafer. The total defect count for each wafer is recorded in a “pre-scan” column corresponding to each wafer.

The two wafers are then inserted, for example, into slots #1and #50respectively of the process tool and are processed by the process tool. After processing, the wafers are returned from the process tool and are again scanned by the laser beam. The total defect count for each wafer is then recorded in the “post-scan” column corresponding to each wafer. The difference between the defect count in each pre-scan columns and the defect count in the corresponding post-scan column is calculated in the spreadsheet and inserted in the “adders” column for the corresponding wafer. The qualification test is then repeated several times, each time with a new pair of wafers. If the adder count exceeds a selected threshold in any of the repeated tests, the process tool fails the qualification check and is shut down to investigate the cause of the problem.

A disadvantage of the method of qualifying process tools illustrated by the spreadsheet ofFIG. 1is that only the number of defects added by the process tool is displayed, while valuable spatial information about the locations of the defects is lost. Also, it is possible for a tool to remove existing defects and to add new defects. To avoid this problem, clean test wafers are required. More testing is generally required to identify the locations of the defects, resulting in extended containment times and multiple equipment failures before a problem may be found and corrected.

In one aspect of the present invention, the progress of a process tool qualification test is advantageously displayed in a graphic plot that displays the added defects versus a failure threshold and wafer maps that display the spatial signature of pre-scan, post-scan, and added defects for each wafer tested. In one embodiment, a method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.

FIG. 2illustrates a flow chart200for a method of qualifying a process tool according to an embodiment of the present invention.

Step202is the entry point of the flow chart200.

In step204, pre-scan defect locations are found on the surface of a semiconductor wafer according to well-known techniques, for example, by a scanning laser beam or an optical microscope. The semiconductor wafer may be patterned with integrated circuit dies, or the semiconductor wafer may be unpatterned.

In step206, the semiconductor wafer is transferred to a process tool, typically on a wafer cassette.

In step208, the semiconductor wafer is subjected to processing by the process tool, for example, to form a layer of doped silicon on the semiconductor wafer.

In step210, the semiconductor wafer is returned from the process tool, typically on a wafer cassette.

In step212, post-scan defect locations on surface of the semiconductor wafer are found, for example, by the same method used to find the pre-scan defect locations in step204. Alternatively, different methods and different equipment may be used according to well-known techniques to find the post-scan defect locations on surface of the semiconductor wafer, especially if the test is performed on an actual product.

In step214, the defect locations added by the process tool are calculated from the pre-scan defect locations and the post-scan defect locations by a defect source analysis calculation.

In step216, an added defect map is generated from the added defect locations calculated in step214.

In step218, if the number of added defects is less than a selected failure threshold, then control is transferred to step220. If the number of added defects exceeds the selected failure threshold, then control is transferred to step222.

In step220, the process tool passes the qualification test, and control is transferred to step224.

In step222, the spatial signature of the added defects on the added defect map is analyzed to determine the cause of failure in the process tool.

Step224is the exit point of the flow chart200.

FIG. 3illustrates a diagram of a defect source analysis calculation according to an embodiment of the present invention. Shown inFIG. 3are a pre-test wafer map302, a post-test wafer map304, a summed overlay map306, an added defect map308, and defect locations310.

InFIG. 3, the pre-test wafer map302shows the defect locations310resulting from scratches and particles on the surface of the wafer that were detected by a laser scan as described above. The post-test wafer map304shows the defect locations310after the wafer was returned from the process tool. It is possible that some of the particles on the surface of the wafer that appear as defect locations310on the pre-test wafer map302become dislodged in the process tool and do not appear on the post-test wafer map304. A disadvantage of previous methods for calculating the number of defects added by the process tool is the failure to account for the removal of particles from the pre-test wafer map302. The method of the present invention overcomes this disadvantage by using the locations of the defects to determine which defects were added by the process tool.

The circled defect locations310in the summed overlay map306are in identical or nearly identical locations on both the pre-test wafer map302and the post-test wafer map304. The uncircled defect locations310in the lower left portion of the summed overlay map306represent the particles that were removed by the process tool and do not appear on the post-test wafer map304. The remaining defect locations310in the lower right portion of the summed overlay map306represent defects that were added by the process tool and do not appear in the pre-test wafer map302. The defect source analysis calculation of the present invention advantageously distinguishes defect locations310that are added by the process tool (adders) from defects that were not added by the process tool (non-adders) to generate the added defect map308.

FIGS. 4A–4Dillustrate a flow chart400of an example of a defect source analysis calculation that may be used to generate the added defect map308ofFIG. 3. Other methods of generating the added defect map308inFIG. 3may be used to practice various embodiments of the present invention within the scope of the appended claims.

Step402is the entry point of the flow chart400.

In step404, the defect locations310on the pre-test wafer302and the post-test wafer304are sorted in order according to the value of the X-coordinate of each defect location310. Defect locations310having the same X-coordinate are further sorted according to the value of the Y-coordinate. For example, the defect locations (2,6), (1,3), (4,5), (3,2), (5,1), and (3,1) would be sorted in the following order: (1,3), (2,6), (3,1), (3,2), (4,5), and (5,1). The sorted defect locations are stored in a first list of ordered defect locations from the pre-test wafer map302and in a second list of ordered defect locations from the post-test wafer map304. Alternatively, the first list of ordered defect locations may be sorted from the pre-test wafer map302and the second list of ordered defect locations may be sorted from the post-test wafer map304.

In step406, the first defect location in the first ordered list of defect locations is selected as a first point.

In step408, the first defect location in the second ordered list of defect locations is selected as a second point.

FIGS. 5A and 5Billustrate a first part of a calculation to determine whether a defect location in the pre-test wafer map302is an added defect on the post-test wafer map304ofFIG. 3. Shown inFIGS. 5A and 5Bare defect locations502and504on the pre-test wafer map, defect locations506,508,510and512on the post-test wafer map, and a registration tolerance514.

InFIG. 5A, the defect location502in the pre-test wafer map is selected as the first point. The defect location506in the post-test wafer map is selected as the second point.

In step410, the coordinate distance between the first point (x1, y1) and the second point (x2, y2) is calculated, for example, from a lookup table or from the distance formula [(x1−x2)2+(y1−y2)2]1/2.

In step412, if the distance between the first point and the second point is less than the registration tolerance, then control is transferred to step414. Otherwise, control is transferred to step416. The registration tolerance typically has a radius equal to a value of about 20 microns to 50 microns, if the wafer maps are aligned. If the wafer maps are subject to offset errors from scanning or inspection tool offset, then a higher registration tolerance may be used, for example, 1000 microns or more.

In step414, the defect location310in the post-wafer map304corresponding to the second point is marked as a non-adder, because it is considered to be identical to the first point on the pre-test wafer map302.

In the example ofFIGS. 5A and 5B, the registration tolerance514is compared to the coordinate distance calculated in step412between the defect location502and the defect location506. Because the coordinate distance between the defect location502and the defect location506falls inside the registration tolerance514, the defect locations502and506are considered to be the same defect on both the pre-test wafer amp and the post-test wafer map, therefore this defect is marked as a non-added defect on the post-test wafer map.

In step416, if each of the defect locations in the second list has been selected, then control is transferred to step422. Otherwise, control is transferred to step418.

In step418, the next defect location in the second ordered list is selected as the second point. In the example ofFIGS. 5A and 5B, the new second point is the defect location508in the post-test wafer map. The first point is still the defect location502in the pre-test wafer map.

In step420, if the difference in X-coordinates between the first point and the second point is less than or equal to the registration tolerance, then there may still be one or more defects on the post-test wafer map that may be marked as non-adders, so control is transferred back to step410. If the difference in X-coordinates between the first point and the second point is greater than the registration tolerance, then no subsequent defect locations in the second ordered list may be marked as non-adders, so control is transferred to step422. In the example ofFIGS. 5A and 5B, the difference in X-coordinates between defect locations502and508is less than the registration tolerance, so control is transferred back to step410.

In step422, if each of the defect locations in the first ordered list has been selected, then control is transferred to step426. Otherwise, control is transferred to step424.

In step424, the next defect location504in the first ordered list is selected as the first point, and control is transferred back to step410.

In step426, the pass from left to right through the ordered lists of the defect locations has been completed. In some cases, such as the example of,FIGS. 5A and 5B, there may be defect locations on the post-test wafer map that were omitted from a comparison on the left-to-right pass that would have marked a defect location on the post-test map as a non-adder. An example of such a possible omission is the defect location508. A second pass may be made from right to left through the first ordered list of defect locations and the second ordered list of defect locations, that is, in reverse order, to capture the omitted non-adders as follows. After completing the left-to-right pass, the last defect location in the first list of defect locations is the new first point, and the last defect location in the second list of defect locations is the new second point.

FIGS. 6A and 6Billustrate the second part of a calculation to determine whether a defect location in the pre-test wafer map302is an added defect on the post-test wafer map304ofFIG. 3. Shown inFIGS. 6A and 6Bare defect locations502and504on the pre-test wafer map, defect locations506,508,510and512on the post-test wafer map, and a registration tolerance514.

InFIG. 6A, the defect location504on the pre-test wafer map is now the selected first point, and the defect location512is now the selected second point.

In step428, the coordinate distance between the first point and the second point is calculated as described above.

In step430, if the distance between the first point and the second point is less than the selected registration tolerance, then control is transferred to step432. Otherwise, control is transferred to step434.

In the example ofFIGS. 6A and 6B, the registration tolerance514is compared to the coordinate distance calculated in step428between the defect location504on the pre-test wafer map and the defect location512on the post-test wafer map. Because the coordinate distance between the defect location504and the defect location512falls outside the registration tolerance514, the defect location512is an added defect on the post-test wafer map. Either the added defects, the non-added defects, or both may be marked on the list of post-test defect locations to calculate the added defect locations.

In step432, the corresponding defect location in the post-wafer map is marked as a non-added defect.

In step434, if each of the defect locations in the second ordered list have been selected on the second pass, then control is transferred to step442. Otherwise, control is transferred to step436.

In step436, the next right-most defect location in the second ordered list is selected as the new second point. In the example ofFIGS. 6A and 6B, the next defect location in the second ordered list is the defect location510.

In step438, if the defect location in the post-test wafer map corresponding to the second point was already marked as a non-adder, then control is passed to step434. Otherwise, control is passed to step440. In the example ofFIGS. 6A and 6B, the defect location510was already marked as a non-adder, so control is passed to step434.

In step440, if the difference in X-coordinates between the first point and the second point is less than the registration tolerance, then there may be additional defects on the post-test wafer map that may be marked as non-adders, so control is transferred to step428. Otherwise, control is transferred to step442. In the example ofFIGS. 6A and 6B, the difference in X-coordinates between defect locations504and512is less than the registration tolerance, so control is transferred to step428.

In step442, if each of the defect locations in the first sorted list have already been selected, then control is transferred to step446. Otherwise, control is transferred to step444.

In step444, the next defect location in the first ordered list is selected as the first point, and control is transferred to step428.

In step446, the pass from right to left through the lists of ordered coordinates has been completed, and a list of added defect locations in the post-test wafer map is generated as output from the marked defect locations.

Step448is the exit point of the flow chart400.

InFIG. 7, the added defects locations702are the defect locations on the post-test wafer map that remain after discarding the defect locations marked as non-adders by the defect source analysis calculation. The added defect locations702are illustrated in this example as darkened grid locations, however, other plotting symbols and colors may also be used to practice various embodiments of the present invention within the scope of the appended claims.

The added defect map700generated as described above may advantageously be used in conjunction with the pre-test wafer map, the post-test wafer map, and a scatter plot to qualify a process tool as follows.

FIG. 8illustrates a process tool qualification display800according to an embodiment of the present invention. Shown inFIG. 8are a scatter plot802, points804, a pre-test wafer map806, a post-test wafer map808, and an added defect map810.

The scatter plot802displays each point804that is representative of the total number of added defects calculated for each corresponding wafer subjected to processing by the process tool. If the point falls above a selected failure threshold, the process tool is shut down to find and correct the problem. The operator may select any point804to initiate a display of the pre-test wafer map806, the post-test wafer map808, and the added defect map810.

FIGS. 9A,9B and9C illustrate an example of how the process tool qualification display800ofFIG. 8may be used to analyze a process tool failure. Shown inFIGS. 9A,9B and9C are a scatter plot902, points904and906, and added defect maps908and910.

InFIGS. 9A,9B and9C, a process tool failure is indicated by the point904, which exceeds the selected failure threshold of35in this example. Clicking on or selecting the point904initiates the display of the added defect map908. The spatial signature of the added defects forming a horizontal line in the lower part of the added defect map908indicates a scratch that was caused by the process tool. The process tool is shut down and the cause of the scratch is found and repaired. When the process tool is re-tested, the added defect count906is still somewhat higher than the normal range of the previous added defect counts. Clicking on the point906initiates the display of the added defect map910. The spatial signature of the added defects in the same area in which the scratch was found before indicates that the malfunction in the process tool has not yet been fully corrected, even though the number of added defects is below the selected failure threshold. The wafer yield may therefore be further increased by re-examining the process tool to correct the malfunction that causes the scratch.

Although the method of the present invention illustrated by the flowchart descriptions above are described and shown with reference to specific steps performed in a specific order, these steps may be combined, sub-divided, or reordered without departing from the scope of the claims. Unless specifically indicated herein, the order and grouping of steps is not a limitation of the present invention.

The steps described above with regard to the flow chart200may also be implemented by instructions performed on a computer according to well-known programming techniques.

In another aspect of the present invention, a computer program product for qualifying a process tool includes:a medium for embodying a computer program for input to a computer; anda computer program embodied in the medium for causing the computer to perform steps of:(a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer;(b) subjecting the semiconductor wafer to processing by the process tool;(c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and(d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.