ERROR POLARITY DETECTION FOR TIMING SKEW CALIBRATION

An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.

BACKGROUND

Electronic systems can include analog-to-digital (A/D) converters (ADCs). ADCs are circuits that convert analog signals to digital quantities to allow processors of electronic systems to perform signal processing functions for the systems. To increase the speed of A/D conversions, ADCs can be time-interleaved. When multiple ADCs are time-interleaved, each ADC samples the analog input signal at a certain rate, and the outputs of all ADCs are combined to produce a digital output sequence whose rate corresponds to that of an individual ADC times the number of ADCs being time-interleaved. Accordingly, time-interleaved ADCs produce A/D conversions at a higher rate than individual ADCs operating in isolation. However, mismatches between the ADCs that make up a time-interleaved ADC create challenges to these systems.

OVERVIEW

This document relates generally to analog-to-digital converter (ADC) circuits, and in particular to improvements in the operation of time-interleaved ADCs. An example electronic circuit includes multiple ADCs, clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals, apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC of the multiple ADCs, and determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.

DETAILED DESCRIPTION

The rate of analog-to-digital (A/D) conversions can be increased by time-interleaving the conversions of multiple A/D converters (ADCs). For example, a first ADC circuit can be performing a conversion while a second ADC circuit is sampling the input. This eliminates the sampling time from the time for conversion. More than two ADCs can be time-interleaved with the phases of each of the multiple ADCs staggered with the phases of the other ADCs to create a conversion “pipeline” in which a conversion result is produced faster than the conversion rate of any one ADC. However, there can be challenges in time-interleaved A/D conversions that limit accuracy of the overall output of the system.

FIG. 1 is a diagram of an example two-way time-interleaved A/D conversion. ADCs 102 sample and convert one analog input signal x(t) into digital quantities. The ADCs 102 are time-interleaved and operate as phase shifted parallel A/D converters to provide a times-two decrease in the time needed to complete an A/D conversion. More ADCs 102 can be interleaved (e.g., 4, 5, 8, 12, 16, etc.) to further increase the overall A/D conversion rate.

FIG. 1 also illustrates the interleaving of the acquisition and conversion operating states of the ADCs 102. In the example, the sampling clocks of the two ADCs 102 are 180° out of phase (360°/N, where N=2. For N=4, the sampling clocks of the four ADCs would be 90° out of phase). A disadvantage to the time-interleaving is that the overall output sequence of the time-interleaved ADCs can introduce interleaving conversion artifacts due to mismatches between the ADCs. These artifacts can lead to errors in the A/D conversion. One source of errors is a timing mismatch between the sampling times of the time-interleaved ADCs. One cause of a timing mismatch is accuracy of the clock phases that are input to the ADCs.

FIG. 2 is a circuit diagram of an example of two time-interleaved ADCs 102 and the clock circuitry 206 that generates the clock signals (clk0(t) and clk1(t)) used by each of the ADCs 102 respectively to sample the analog input signal x(t). The ADCs 102 can be referred to sub-ADCs or ADC “slices.” In the example, the digital output sequences of the sub-ADCs are labeled y0[n] and y1[n]. FIG. 2 also shows example waveforms 208 of the clock signals and a timing skew error (τ) between their phases as shown. Without timing skew error, the transitions of the clock signals are aligned.

FIG. 3 is a graph that shows the desired A/D conversion of the analog input signal in the frequency domain and an artifact of the conversion due to clock timing skew. The desired conversion of the analog input signal is centered at the frequency of the input signal fx and the artifact occurs at (½fs−fx), where fs is the sampling frequency of the time-interleaved ADC (i.e., the sampling rate of each sub-ADC is given by ½fs).

FIG. 4 is a time-domain plot that illustrates the output samples of a two-way time interleaved ADC being obtained from the analog input signal x(t) when there is no timing skew error. The conversion values from the two slices of the interleaved A/D conversion are labeled Slice 0 (from ADC0) and Slice 1 (from ADC1). In the plot, the arrows show that the output of the slices from the two ADCs are evenly spaced apart in time. FIG. 5 is a time-domain plot almost identical to the plot of FIG. 4, except the plot of FIG. 5 accounts for the effect of timing skew error. The arrows show that the slices from the two ADCs are not evenly spaced apart. In the plot of FIG. 5, the Slice 0 conversions to the left of the Slice 1 conversions are closer to the Slice 1 conversions than the Slice 0 conversions to the right of the Slice 1 conversions. In FIGS. 4 and 5, three adjacent conversions are labeled y0[n], y1[n-1], and y0[n-1], where the subscript indicates to which slice each conversion corresponds. In FIG. 4, the adjacent pairs of conversions are evenly spaced in time when there is not timing skew error. Thus, y1[n-1] is as similar to y0[n] as to y0[n-1] on average for some input signals. In FIG. 5, the adjacent pairs of conversions are not evenly spaced in time due to the timing skew error. The result is that y1[n-1] is more similar to y0[n-1] than to y0[n] on average for some input signals.

FIG. 6 is a system diagram showing an example two-way time-interleaved A/D conversion and calibration circuitry 610 to calibrate the clock circuitry 206 to reduce timing skew error in the clock signals provided to the sub-ADCs 102. To reduce the clock skew, the calibration circuitry 610 determines the similarity between adjacent conversions by the sub-ADCs 102, and the calibration circuitry 610 adjusts the relative timing of the clock signals so that on average pairs of adjacent conversion are equally similar (e.g., so that y0[n-1] and y1[n-1] are as equally similar as y0[n] and y1[n-1]).

In some examples, the calibration circuitry 610 determines a first measure of similarity of an A/D conversion by ADC1 to the A/D conversion by ADC0 immediately preceding the A/D conversion by ADC1, and determines a second measure of similarity between the A/D conversion by ADC1 and the A/D conversion by ADC0 following the A/D conversion by ADC1. Different approaches can be used to determine similarity of A/D conversions, and the circuit diagram of FIG. 6 is only one example.

In the system diagram of FIG. 6, the first measure of similarity is c0[p] and the second measure of similarity is c1[p]. The calibration circuitry 610 includes digital delays (shown as z−1), multipliers 612, block average accumulators 614 (for which the output is divided by the number of accumulated samples N and the accumulators are reset after each accumulation), difference node 616, and an accumulator 618 with forward gain μt. The calibration circuitry 610 may also include a microcontroller, a processor (e.g., a microprocessor), an application specific integrated circuit (ASIC), programmable gate array (PGA), etc. One or more of the delays z−1, multipliers 612, block average accumulators 614, difference node 616, and accumulator 618 may be implemented by the microcontroller.

The multipliers 612 form products of the A/D conversions including y0[n-1]y1[n-1] and y0[n]y1[n-1]. Multiple products of N A/D conversions (e.g., N=1000) are summed and averaged by the block average accumulators 614. After N samples are averaged, the block average accumulators 614 are reset. The averaged products are the measures of similarity c0[p] and c1[p]. The difference between the measures of similarity is produced by the difference node 616. The accumulator 618 uses the difference in similarity measures to produce an estimate of the timing skew error τest[p], and the calibration circuitry 610 adjusts clock signal clk1(t) to reduce the effective timing skew error based on τest[p]. The waveforms 208 of the clock signals show the positive transition of clk1(t) lagging the negative transition of clk0(t), but the skew may also cause the positive transition of clk1(t) to lead the negative transition of clk0(t). The polarity of τest[p] determines whether the calibration circuitry 610 changes the clock signal to advance or delay the phase transition of clk1(t) to reduce the timing skew error.

The approach shown in FIG. 6 works when the frequencies of the input signal x(t) are within a known Nyquist zone of the time-interleaved ADC. In the example of FIG. 6, if the sub-ADCs are each 5 Giga-samples per second (5 GSPS) ADCs, time-interleaving the A/D conversion increases the first Nyquist zone from 2.5Hz to 5Hz. However, there may be implementations where the sub-ADCs receive input signals with frequencies above the first Nyquist zone of the time-interleaved ADC. In this situation, the difference in similarity measures may correspond to a noisy measure of the timing skew error times minus one, which would cause the estimated timing skew error τest[p] determined by the calibration circuitry 610 to deviate from its ideal value, and hence degrade performance. A/D conversions of signals that either fall in unknown Nyquist zones or fall in multiple Nyquist zones may incorrectly flip the polarity of the error measurements.

FIG. 7 is a system diagram of another example of two-way time-interleaved A/D conversion that injects dither into the phase of one of the clock signals. To reliably determine the polarity of the estimated timing skew error, in the example of FIG. 7 a known pseudorandom dither sequence d[n] is injected into the phase of the clk1τ(t) clock signal. The dither sequence d[n] may be a two-level zero-mean sequence that takes on values −1 and +1 with equal probability. Other dither sequences with other characteristics may also be used. With the injected dither sequence, the timing skew error is given by τ−τest[p]+Td[n], where T is the gain (e.g., in femtoseconds) experienced by the dither sequence d[n] when injected into the phase of the clock signal clk1(t). From the viewpoint of the output of the time-interleaved ADCs 102, the sequence Td[n] experiences the same gain A as the residual timing skew error τ−τest[p] that needs to be measured. Therefore, the polarity of the timing skew error measurement can be extracted from the polarity of the gain experienced by the dither sequence by the time-interleaved A/D conversion.

One approach to extracting the polarity of the gain experienced by the sequence Td[n] is to correlate the products of the multipliers 612 y0[n-1]y1[n-1] and y0[n]y1[n-1] with the dither sequence d[n]. The calibration circuitry of FIG. 7 includes multipliers 720 that produce the products d[n-1]y0[n-1]y1[n-1] and d[n-1]y0[n]y1[n-1], and includes a block average accumulator 724 to accumulate and average the difference of the products produced by difference node 722. The extracted gain Aest[p] is an estimate of gain A, which can be filtered to mitigate measurement noise. The extracted Aest[p] can be used to determine the polarity of the timing skew error measurement performed by the calibration circuitry 610, which results in the estimated timing skew error τest[p] being updated correctly.

FIG. 8 is a flow diagram of an example of a method 800 to determine and correct for timing skew errors in a two-way time-interleaved A/D conversion. The analog signal is converted to a sequence of digital values using a time-interleaved ADC. The method 800 can be performed using the circuitry of FIGS. 6 and 7. At block 805, the analog signal is converted to the sequence of digital values by time-interleaving A/D conversions of multiple ADCs according to multiple clock signals applied to the ADCs. The sampling clock signals having a defined phase relationship between them.

At block 810, the magnitude of timing skew error in the clock signals of the ADCs is determined. The timing skew error can be between any two clock signals applied to the ADCs.

At block 815, a dither sequence is applied to the phase of a first clock signal of the two clock signals having the timing skew error. The first clock signal is applied to a first ADC of the multiple ADCs and the second of the two clock signals is applied to another ADC. At block 820, the polarity of the gain experienced by the dither sequence at the output of the circuitry is determined. The polarity of the gain is the polarity of the timing skew error measurement. At block 825, the second clock signal is adjusted using a calibration loop. The determined magnitude and polarity of the timing skew error measurement is used to reduce the timing skew error.

The time-interleaved ADCs described herein operate with reduced timing skew error between the clock signals of the ADCs in the presence of input signals that may span multiple unknown Nyquist zones. The reduced timing skew error improves matching between slices of the interleaved ADC and reduces errors associated with interleaving A/D conversion.

ADDITIONAL DESCRIPTION AND EXAMPLES

A first Example (Example 1) includes subject matter (such as an electronic circuit) comprising multiple analog-to-digital converters (ADCs); clock circuitry configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions; and calibration circuitry. The calibration circuitry is configured to: determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC of the multiple ADCs; and determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.

In Example 2, the subject matter of Example 1 optionally includes calibration circuitry configured to adjust a phase relation of the first clock signal and a second clock signal of the two clock signals according to the determined magnitude and polarity of the timing skew error.

In Example 3, the subject matter of one or both of Examples 1 and 2 optionally includes calibration circuitry configured to determine a first measure of similarity of an A/D conversion by the first ADC to a preceding A/D conversion by another ADC, determine a second measure of similarity of the A/D conversion of the first ADC to a following A/D conversion by the other ADC, compute a difference between the first measure of similarity and the second measure of similarity as the magnitude of the timing skew error, and adjust the phase of the first clock signal relative to a phase of another clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.

In Example 4, the subject matter of Example 3 optionally includes calibration circuitry configured to determine multiple first products of A/D conversions of the first ADC and A/D conversions of the other ADC preceding the A/D conversions of the first ADC, determine multiple second products of the A/D conversions of the first ADC and A/D conversions of the other ADC following the A/D conversions of the first ADC, and average the multiple first products to determine the first measure of similarity and average the multiple second products to determine the second measure of similarity.

In Example 5, the subject matter of one or any combination of Examples 1-4 optionally includes calibration circuitry configured to apply the dither sequence to the calibration circuitry to change a phase of the first clock signal according to the dither sequence.

In Example 6, the subject matter of Example 5 optionally includes calibration circuitry configured to extract the gain experienced by the dither sequence by correlating a difference between pairs of A/D conversions to the dither sequence.

In Example 7, the subject matter of one or both of Examples 5 and 6 optionally includes calibration circuitry configured to determine a first product of an A/D conversion of the first ADC at a first sample time and an A/D conversion of the other ADC at a sample time previous to the first sample time, determining a second product of an A/D conversion of the first ADC at a first sample time and the A/D conversion of the other ADC at a sample time following the first sample time, and determine the polarity of the gain experienced by the dither sequence by correlating a value of the dither sequence to a difference of the first product and the second product.

In Example 8, the subject matter of one or any combination of Examples 1-7 optionally includes calibration circuitry configured to adjust a phase of the first clock signal by the determined magnitude of timing skew error relative to a phase of another clock signal according to the determined polarity of the gain experienced by the dither sequence.

In Example 9, the subject matter of one or any combination of Examples 1-8 optionally includes multiple ADCs produce time-interleaved A/D conversions of an input analog signal having signal components in multiple Nyquist zones.

Example 10 includes subject matter (such as a method of processing an analog signal) or can optionally be combined with one or any combination of Examples 1-9 to include such subject matter, comprising time-interleaving analog-to-digital (A/D) conversions of the analog signal using multiple analog-to-digital converters (ADCs) according to multiple clock signals applied to the multiple ADCs, determining a magnitude of a timing skew error between any two of the multiple clock signals, applying a dither sequence to phase of a first clock signal of the two clock signals, wherein the first clock signal is applied to a first ADC of the multiple ADCs, and determining a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence by the time-interleaved A/D conversions.

In Example 11, the subject matter of Example 10 optionally includes adjusting a phase of the first clock signal relative to a phase of a second clock signal of the two clock signals according to the determined magnitude and polarity of the timing skew error.

In Example 12, the subject matter of one or both of Examples 10 and 11 optionally includes determining a first measure of similarity of a time-interleaved A/D conversion of the first ADC to a previous time-interleaved A/D conversion of another ADC, determining a second measure of similarity of the time-interleaved A/D conversion of the first ADC to a following time-interleaved A/D conversion of the other ADC, computing a difference between the first measure of similarity and the second measure of similarity, and adjusting a phase of the first clock signal relative to a phase of another clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.

In Example 13, the subject matter of Example 12 optionally includes determining multiple first products of A/D conversions of the first ADC and A/D conversions of the other ADC preceding the A/D conversions of the first ADC, averaging the multiple first products to determine the first measure of similarity, determining multiple second products of the A/D conversions of the first ADC and A/D conversions of the other ADC following the A/D conversions of the first ADC, and averaging the multiple second products to determine the second measure of similarity.

In Example 14, the subject matter of one or any combination of Examples 10-13 optionally includes time-interleaving of A/D conversions of an input analog signal having signal components in multiple Nyquist zones.

In Example 15, the subject matter of one or any combination of Examples 10-14 optionally includes changing the phase of the first clock signal according to the dither sequence.

In Example 16, the subject matter of Example 15 optionally includes correlating the dither sequence with differences between adjacent pairs of interleaved A/D conversions.

In Example 17, the subject matter of one or both of Examples 15 and 16 optionally includes determining a first product of an A/D conversion of the other ADC at a first sample time and an A/D conversion of the first ADC at a previous sample time previous to the first sample time, determining a second product of an A/D conversion of the first ADC at the previous sample time and the A/D conversion of the other ADC at the previous sample time, and correlating a value of the dither sequence at the previous sample time to a difference of the first product and the second product.

In Example 18, the subject matter of one or any combination of Examples 10-17 optionally includes adjusting a phase of the first clock signal by the determined magnitude of timing skew error relative to a phase of another clock signal according to the determined polarity of the gain experienced by the dither sequence.

Example 19 includes subject matter (such as a time-interleaved analog-to-digital converter (ADC) circuit) or can optionally be combined with one or any combination of Examples 1-18 to include such subject matter, comprising a first sub-ADC, a second sub-ADC, clock circuitry configured to provide a first clock signal to the first sub-ADC and a second clock signal to a second sub-ADC to advance the first and second sub-ADCs through time-interleaved analog-to-digital (A/D) conversions, and calibration circuitry. The calibration circuitry is configured to apply a specified dither sequence to a clock phase of the second clock signal, extract a gain experienced by the dither sequence from the time interleaved A/D conversions, and adjust a phase relation of the first clock signal and the second clock signal according to a polarity of the extracted gain according to a polarity of the extracted gain.

In Example 20, the subject matter of Example 19 optionally includes calibration circuitry configured to determine a first measure of similarity of an A/D conversion by the second sub-ADC to a preceding A/D conversion by the first sub-ADC, determine a second measure of similarity of the A/D conversion of the second sub-ADC to a following A/D conversion by the first sub-ADC, compute a difference between the first measure of similarity and the second measure of similarity, and adjust the phase of the second clock signal according to the polarity of the extracted gain to minimize the difference between the first measure of similarity and the second measure of similarity.