Semiconductor device having a buffer material and stiffener

Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages.

BACKGROUND

Consumer electronic devices, in particular, mobile electronic devices such as smart phones, tablet computers, and so forth, increasingly employ smaller, more compact components to furnish their users with desired features. Such devices often employ three dimensional integrated circuit devices (3D IC). Three-dimensional integrated circuit devices are semiconductor devices that employ two or more layers of active electronic components. Through-silicon vias (TSV) interconnect electronic components on the different layers (e.g., different substrates) of the device allowing the devices to be integrated vertically as well as horizontally. Consequently, three-dimensional integrated circuit devices can provide increased functionality within a smaller, more compact footprint than do conventional two-dimensional integrated circuit devices.

SUMMARY

Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer) that include the removal of oxide on the dicing streets, a buffer material between the semiconductor wafer and adhesive layer, and including an underfill layer with a coefficient of thermal expansion (CTE) matched to the CTE of the buffer material. In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may subsequently be segmented into individual semiconductor chip packages.

DETAILED DESCRIPTION

Overview

Three-dimensional integrated circuit devices are commonly manufactured using die-on-wafer techniques wherein electronic components (e.g., circuits) are first fabricated on two or more semiconductor wafers. The individual die are aligned on and attached to semiconductor wafers and segmented to provide individual devices. Through-silicon vias (TSVs) can be built into wafers before they are attached or created in the wafer stack after attachment. However, wafer warpage and bowing of the semiconductor wafer may occur during fabrication of three-dimensional integrated circuit devices. This wafer warpage can prevent effective wafer handling as well as mechanical failure within the device, for example, causing delamination of layers within the device. Also, device packages that include through-silicon vias (TSVs) with thin silicon, chip-to-wafer bonding using a mold compound are highly susceptible to thermo-mechanical failure. Additionally, a semiconductor wafer may be segmented into individual dice and may chip on the backside and crack along the die edges during the singulation process. Further, materials with dissimilar coefficients of thermal expansion can cause device failures, for example chip-to-wafer solder joint cracking. These problems increase the cost of the devices and reduce device yield.

Accordingly, techniques are described for fabricating semiconductor devices having multiple, stacked die on a substrate (e.g., a semiconductor wafer) that include the removal of oxide on the dicing streets, a buffer material between the semiconductor wafer and adhesive layer, and including an underfill layer with a coefficient of thermal expansion (CTE) matched to the CTE of the buffer material. In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer; an integrated circuit chip placed on the semiconductor wafer; an underfill layer between the integrated circuit chip and the semiconductor wafer; a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip; an adhesive layer placed on the buffer layer and the integrated circuit chip; and a stiffener layer placed on the adhesive layer.

In implementations, a wafer-level package device that employs example techniques in accordance with the present disclosure includes placing an integrated circuit chip on a processed semiconductor wafer, where the semiconductor wafer includes at least one via and at least one dielectric layer, forming an underfill material layer between the integrated circuit chip and the semiconductor wafer, forming a buffer material layer on a portion of the underfill material layer, the dielectric layer, the semiconductor wafer, and adjacent to at least one side of the integrated circuit chip, forming an adhesive layer on the buffer material layer and a portion of the integrated circuit chip, placing a stiffener layer on the adhesive layer, and forming at least one solder bump on the semiconductor wafer. The processed semiconductor wafer may then be segmented into individual semiconductor devices.

Example Implementations

FIG. 1illustrates a semiconductor device100in accordance with example implementations of the present disclosure. As shown, the semiconductor device100is illustrated at wafer level prior to singulation. The semiconductor device100can include a semiconductor wafer102. The semiconductor wafer102includes one or more integrated circuits (not shown), which are formed within the semiconductor wafer102. The semiconductor wafer102includes a first (e.g., top or front) surface and a second (e.g., bottom or backside) surface. The integrated circuits are formed (e.g., fabricated) proximate to the first surface of the semiconductor wafer102. The second surface of the semiconductor wafer102may be configured to have at least one solder bump120formed thereon or attached thereto. It is contemplated that the first and/or the second surface of the semiconductor wafer102may be planarized or unplanarized.

The semiconductor wafer102includes a base material utilized to form one or more integrated circuit devices through various fabrication techniques such as photolithography, ion implantation, deposition, etching, and so forth. The semiconductor wafer102may be configured in a variety of ways. For example, the semiconductor wafer102may comprise an n-type silicon wafer or a p-type silicon wafer. In an implementation, the semiconductor wafer102may comprise group V elements (e.g., phosphorus, arsenic, antimony, etc.) configured to furnish n-type charge carrier elements. In another implementation, the semiconductor wafer102may comprise group IIIA elements (e.g., boron, etc.) configured to furnish p-type charge carrier elements. In some embodiments, the semiconductor wafer102includes an ultra-thin semiconductor wafer with a thickness of less than about 100 μm. Further, the integrated circuits may be configured in a variety of ways. For example, the integrated circuits may include digital integrated circuits, analog integrated circuits, mixed-signal circuits, and so forth. In one or more implementations, the integrated circuits may include digital logic devices, analog devices (e.g., amplifiers, etc.), combinations thereof, and so forth. As described above, the integrated circuits may be fabricated utilizing various fabrication techniques. For example, the integrated circuits may be fabricated via complimentary metal-oxide-semiconductor (CMOS) techniques, bi-polar semiconductor techniques, and so on.

As shown inFIG. 1, the semiconductor device100also includes at least one through-silicon via104formed in the semiconductor wafer102. Each through-silicon via104(“TSV”) extends through the semiconductor wafer102between a contact pad106on the first side to a contact pad106on the second side. As illustrated inFIG. 1, the through-silicon via104includes a conductive material that furnishes an electrical interconnection between the first side and the second side of the semiconductor wafer102. In one or more implementations, the conductive material included in the through-silicon via104may include a metal material (e.g., copper, aluminum, etc.). In embodiments, a contact pad106may include a metal pad or surface configured to furnish an electrical connection between two components (e.g., a solder bump, a redistribution layer, etc.). In some implementations, the contact pad106is not disposed directly over the through-silicon via104. In these implementations, the contact pad106and the through-silicon via104are offset from each other and are electrically coupled using a backside redistribution layer (BRDL).

Additionally, the semiconductor wafer102includes a dielectric layer122. In some implementations, the dielectric layer122includes an oxide layer. The dielectric layer122may be disposed on at least one side of the semiconductor wafer102while not covering a portion of the semiconductor where a dicing street124is located. A dicing street124may include an area where a portion of a wafer level package (e.g., between integrated circuits formed in the wafer) is cut away in order to segment the chip packages. In embodiments, the dicing street124is located at the edge of the semiconductor wafer102where the semiconductor device100will be singulated into individual chip packages. By removing and/or not forming the dielectric layer122on the dicing street(s)124, wafer chipping during a singulation process and potential oxide layer delamination is prevented.

The semiconductor device100includes an integrated circuit chip108attached to one side of the semiconductor wafer102. In embodiments, the integrated circuit chip108includes at least one solder bump110(e.g., a chip-to-wafer solder ball) that functions as an electrical connection between the integrated circuit chip108and the electrical interconnections of the semiconductor wafer102. In other embodiments, the integrated circuit chip108may be attached to the semiconductor wafer102using other methods, such as using an adhesive. Additionally, the integrated circuit chip108may be electrically connected to the semiconductor wafer102, for example, using bonding wires. In some implementations, the integrated circuit chip108may include a flip-chip where solder bumps are deposited on the integrated circuit chip108and the integrated circuit chip108is flipped over so that its top side faces down and is in contact with the semiconductor wafer102.

The semiconductor device100includes an underfill112disposed between the integrated circuit chip108and the dielectric layer122on the semiconductor wafer102. The underfill112may include a non-conductive material (e.g., an epoxy-based resin, etc.) that functions to protect the solder bumps110and a portion of the integrated circuit chip108from stress, moisture, contaminants, and other environmental hazards. In embodiments, the underfill112coefficient of thermal expansion (CTE) is matched to be similar to the CTE of the solder bumps110on the integrated circuit chip108and the CTE of the buffer material114. The underfill112with the matched CTE functions to eliminate solder joint fatigue and/or cracking.

As illustrated inFIG. 1, the semiconductor device100includes a buffer material114. In embodiments, the buffer material114includes an epoxy-based material that provides a thermo-mechanical buffer between the semiconductor wafer102and the adhesive116. The buffer material114is formed on a portion of the semiconductor wafer102, the dielectric layer122, the underfill layer112, and at least one side of the integrated circuit chip108, as shown inFIG. 1. In implementations, the buffer material114includes a material having an intermediate CTE (e.g., a CTE between the CTE of the solder bumps110and the adhesive116. In one embodiment, the buffer material114includes a liquid epoxy-based material. The buffer material114with the intermediate CTE provides a thermo-mechanical buffer and better dicing and temperature cycling performance.

The semiconductor device100includes an adhesive116, as shown inFIG. 1. The adhesive is formed on the buffer material114and the integrated circuit chip108. The adhesive material128is configured to bond a stiffener layer118to the semiconductor device100. In implementations, the adhesive material128has a high CTE (e.g., greater than about 100 ppm/C), a low glass transition temperature (e.g., less than about 100° C.), and a low flex modulus (e.g., less than about 1 GPa).

Additionally, a stiffener layer118may be attached to the adhesive116, as illustrated inFIG. 1. The stiffener layer118can function to structurally and environmentally protect the semiconductor device100. In embodiments, the stiffener layer118may include a silicon layer (e.g., a silicon wafer). In other embodiments, the stiffener layer118may include another alloy or support material. In embodiments, the stiffener layer118includes a material with a high modulus or mechanical strength to prevent wafer warpage (e.g. less than about 1 mm).

The semiconductor device100includes at least one solder bump120formed on a side of the semiconductor wafer102. Solder bumps120are provided to furnish mechanical and/or electrical interconnection between the semiconductor wafer102and corresponding pads (not shown) formed on the surface of a printed circuit board (not shown) or other semiconductor device. In one or more implementations, the solder bumps120may be fabricated of a lead-free solder such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on. In one specific implementation, at least one solder bump120is electrically coupled to the through-silicon via104by way of a redistribution layer (e.g., front side redistribution layer).

Once the fabrication is complete, suitable wafer-level packaging processes may be employed to segment and package the semiconductor device100. In one or more implementations, the segmented semiconductor devices may comprise wafer chip-scale package devices, which may further be attached to another device (e.g., a printed circuit board) to create an electronic device.

Example Fabrication Processes

FIG. 2illustrates an example process200that employs wafer-level packaging techniques to fabricate three-dimensional semiconductor devices, such as the semiconductor device100shown inFIG. 1.FIGS. 3A through 3Eillustrate sections of example wafers that may be utilized to fabricate semiconductor devices300(such as semiconductor device100) shown inFIG. 1. A semiconductor wafer302, as shown inFIG. 3A, includes a first surface (e.g., the top or frontside) and a second surface (e.g., the bottom or backside). The semiconductor wafer302includes one or more integrated circuits (not shown) formed proximate to the first surface. The integrated circuits are connected to one or more contact pads306(e.g., a metal pad, etc.) that are configured to provide electrical contacts through which the integrated circuits are interconnected to other components (e.g., other integrated circuits, printed circuit boards, other integrated circuit die, etc.) associated with semiconductor device300. Additionally, the semiconductor wafer302includes at least one through-silicon via304formed therein and a dielectric layer322(e.g., an oxide layer) formed on at least one surface of the semiconductor wafer302.

As illustrated inFIG. 3A, an integrated circuit chip is placed on a semiconductor wafer (Block202). In some implementations, placing an integrated circuit chip308on the semiconductor wafer302may include utilizing a pick-and-place process. Pick-and-place technology may include using automated machines to place surface-mount devices (e.g., the integrated circuit chip device308) onto a substrate (e.g., the semiconductor wafer302). A pick-and-place process may place and align the integrated circuit chip308with electrical interconnections (e.g., contact pads306) on the semiconductor wafer302.

As illustrated inFIG. 3B, an underfill is formed (Block204). In embodiments, forming an underfill312includes forming the underfill312between the integrated circuit chip308and the semiconductor wafer302. In implementations, forming the underfill312may include using a process that utilizes capillary action to fill the remaining open space between the semiconductor wafer302and the integrated circuit chip308. In an embodiment, the underfill312is applied in liquid form from a dispenser at one edge of the integrated circuit chip308. In this embodiment, the underfill312then flows into the narrow gap between the solder bumps310because of capillary action and spreads across the integrated circuit chip308until the space between the integrated circuit chip308and the semiconductor wafer302is filled.

A buffer material is formed on the semiconductor device (Block206). As illustrated inFIG. 3, a buffer material314is formed on the semiconductor wafer302, the dielectric layer322, a portion of the underfill312, and at least one side of the integrated circuit chip308. In an implementation, forming the buffer material314may include molding an epoxy-based material on the semiconductor wafer302, the dielectric layer322, a portion of the underfill312, and at least one side of the integrated circuit chip308and curing the epoxy-based material. In one embodiment, forming the buffer material314may include using transfer molding because of its capability to mold small components with complex features.

An adhesive layer is formed on the integrated circuit chip and the buffer material (Block208). As illustrated inFIG. 3D, an adhesive316is formed on the integrated circuit chip308and the buffer material314to function as a bonding material between the semiconductor device100and a stiffener layer318. Forming the adhesive316may include forming an adhesive material configured as an adhesive dielectric (e.g., benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), etc.).

Next, a stiffener layer is placed on the adhesive (Block210). As illustrated inFIG. 3E, placing the stiffener layer318includes placing the stiffener layer318on the adhesive316. In an implementation, placing the stiffener layer318includes placing a silicon wafer on the adhesive. In another implementation, placing the stiffener layer318includes placing an alloy layer on the adhesive316. It is contemplated that once the stiffener layer318is attached to the adhesive316, a curing process may be utilized to further harden and/or cure the adhesive316.

At least one solder bump is formed on the semiconductor wafer (Block212). The solder bump(s)320may be formed using various methods. In one implementation, the solder bumps320are formed using a ball drop process. It is contemplated that other techniques such as solder paste printing, evaporation, electroplating, jetting, stud bumping, and so on may be used to form the solder bumps320. In one implementation, forming solder bumps320includes applying solder paste to predetermined locations on the semiconductor wafer302, the solder bumps320configured to be subsequently reflowed and form the final connections between the wafer level package device and another component (e.g., printed circuit board, other integrated circuit chip, etc.). In another embodiment, forming at least one solder bump includes dropping at least one solid, pre-formed solder ball using a ball drop process. In another embodiment, forming at least one solder bump320on the semiconductor wafer302includes placing a solder ball in a liquid or molten form on the semiconductor wafer302. In these embodiments, the solder ball may be bonded to the semiconductor wafer302to form a solder bump320by heating the solder ball and the contact material.

Once the wafer fabrication process is complete, suitable wafer-level packaging processes may be employed to segment and package the individual semiconductor devices. In one or more implementations, the segmented semiconductor devices may comprise wafer chip-scale package devices.

CONCLUSION