Memory and multi-state sense amplifier thereof

The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to memories and more particularly to memories with changeable resistance.

2. Description of the Related Art

A Magnetic Random Access Memory (MRAM) is a non-volatile memory. Different from a conventional memory, which stores data in the form of charge or current, MRAM stores data with magnetic storage cells. Because MRAM has high cell density and high access speed, it is poised to emerge as the mainstream technology in the memory fabrication industry.

FIG. 1shows a conventional MRAM cell100. MRAM cell100comprises a transistor102, and two Magnetic Tunnel Junction (MTJ) devices104and106. The MTJ devices104and106are coupled in parallel between a read bit line RBL and a node108. MTJ devices typically comprise a plurality of interleaved ferromagnetic layers and insulating layers. A magnetic field applied to the MRAM cell100shifts the polarity of the ferromagnetic layers changing the resistance of the MTJ devices104and106. Thus, the MTJ devices104and106can be switched between two levels of resistance.

A transistor102is coupled between the node108and a ground. The gate of the transistor102is coupled to a word line WL. When a high voltage is applied to the word line WL to turn on the transistor102, the MTJ devices104and106are connected in parallel between the read bit line RBL and ground. The read bit line RBL is biased by a constant voltage and coupled to a sense amplifier, thus, the current level flowing through the read bit line RBL changes with the resistance of the MTJ devices104and106. The sense amplifier can then read data stored in MRAM cell100by detecting the current level. Because the size of the two MTJ devices104and106are different, the changeable resistance level of the MTJ devices is also different. For example, if the MTJ device104can be switched between resistance level R1maxand R1min, and the MTJ device106can be switched between resistance level R2maxand R2min, the total resistance of the MRAM cell100can then be switched between four levels of R1max//R2max, R1max//R2min, R1min//R2max, and R1min//R2min. Thus, the MRAM cell100has four memory states, each capable of storing 2 bits of data.FIG. 2is a table200showing the relationship between the resistance level of the MRAM cell100and corresponding data stored in the MRAM cell100. The four kinds of data stored in the MRAM cell100are respectively 11, 10, 01, and 00.

Because an MRAM comprises a plurality of MRAM cells100, an output circuit coupled must be coupled to the bit line to detect data stored in a specific MRAM cell. The design of the output circuit heavily affects access time and performance of the MRAM. If an output circuit detects the current or voltage of the bit line with a multi-state sense amplifier, the access time is greatly reduced and the performance of the MRAM is improved.

The multiple bit lines and word lines of a memory induce parasitic capacitance. When a memory cell is turned on, the memory cell is directly coupled to the multi-state sense amplifier, and the voltage drops across the MTJ devices induce a current flowing between the path between the memory cell and the multi-state sense amplifier. According to the charge conservation theorem Q=C×V=I×t, when the memory cell is turned on, the current cannot immediately charge the parasitic capacitance coupled to the current path to force the transistors of the sense amplifier into triode regions, and the output voltage of the sense amplifier is pulled up to a logic high level, increasing the access time of the MRAM.

A method is thus provided for ameliorating the described problems. The method couples the output terminals of reference cells to switches to be turned on only when the memory cell is turned on to clamp the voltage of the output terminals of the reference cells to a certain voltage. Thus, the voltages of transistors of the sense amplifier are prevented from being pulled up to the logic high level reducing access time by half.

BRIEF SUMMARY OF THE INVENTION

The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. An exemplary embodiment of the multi-state sense amplifier comprises a source follower, a source follower circuit, and a current mirror circuit. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thus generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

The invention also provides a memory. An exemplary embodiment of the memory comprises at least one memory cell, a plurality of reference cells, a multi-state sense amplifier, a comparator, and a decoder. The resistance of the memory cell is changeable. The reference cells have different resistance. The multi-state sense amplifier, coupled to the memory cell and the reference cells, generates a memory cell voltage and a plurality of reference voltages according to the resistance of the memory cell and the resistance of the reference cells. The comparator, coupled to the multi-state sense amplifier, compares the memory cell voltage and the reference voltages to obtain a comparison result signal. The decoder, coupled to the comparator, decodes the comparison result signals to obtain N bits of data stored in the memory cell.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3shows a portion of the circuits of an MRAM300according to the invention. MRAM300includes a four-state sense amplifier302, at least one four-state MRAM cell304, and reference cells306,308, and310. MRAM300comprises a plurality of MRAM cells304, each having a structure similar to MRAM cell100ofFIG. 1, and coupled between a bit line and a ground, wherein the bit line is further coupled to the sense amplifier302. When an MRAM cell304is selected by a word line, the transistor102of the selected MRAM cell304is turned on to couple the MTJ devices104and106between the sense amplifier302and the ground. Thus, the sense amplifier302can detect the resistance of the selected MRAM cell for reading stored data.

For brevity,FIG. 3shows only the selected MRAM cell304. Because the resistance of the MRAM cell304can be switched between four levels, the four resistors372,374,376, and378represents one of four resistance levels, R1max//R2max, R1max//R2min, R1min//R2max, and R1min//R2minrespectively. The gates of transistors371,372,375, and377are respectively coupled to word lines WL11, WL10, WL01, and WL00. Each word line is selected to turn on the corresponding transistor; the corresponding resistor372,374,376, or378is coupled between the ground and the sense amplifier302. For example, when the word line WL10is selected, the transistor373is turned on to couple the resistor374between the ground and the sense amplifier302, and the total resistance of the MRAM cell304is R1max//R2min. The simplified circuit of MRAM cell304shown inFIG. 3is provided for illustration only, the real circuit structure of the MRAM cell304may be similar to the MRAM cell100shown inFIG. 1.

Reference cells306,308, and310each having a different resistance that can be compared with the resistance of MRAM cell304to obtain stored data. Each of the reference cells is formed by multiple resistors coupled between the output terminals thereof and a ground. In one embodiment, each of the reference cells comprises two resistors respectively corresponding to one of the four resistances of the MRAM cell304. For example, the reference cell306comprises a resistor382having resistance of R1min//R2minand a resistor384having resistance of R1min//R2max, the reference cell308comprises a resistor386having resistance of R1min//R2maxand a resistor388having resistance of R1max//R2min, and the reference cell310comprises a resistor392having resistance of R1max//R2minand a resistor394having resistance of R1max//R2max. Because the MRAM cell304has four (22) resistance levels, the number of the reference cells is three (22−1=3). When one of the word lines WL11, WL10, WL01, WL00is selected, the word lines WL0and WL1are selected at the same time to couple the two resistors of the reference cells in parallel between the sense amplifier302and ground.

The sense amplifier302is a four-state sense amplifier and generates a memory cell voltage Vcelland a plurality of reference voltages VR1, VR2, and VR3according to the resistance of the MRAM cell304and the reference cells306,308, and310. A transistor322is coupled between the sense amplifier302and the bit line coupled to the output terminal of the MRAM cell304, and has a gate coupled to a read-word-line enable signal RWLEN which turns on the transistor322to couple the MRAM cell304to the sense amplifier302. Accordingly, transistors324,326, and328are coupled between the sense amplifier302and the reference cells306,308, and310, triggered by the read-word-line enable signal RWLEN to couple the reference cells306,308, and310to the sense amplifier302.

The sense amplifier302includes a source follower312, a source follower circuit316, a current mirror circuit314, and a pre-charge circuit318. The sense amplifier302is coupled to the output terminal of the MRAM cell304through the source follower312, which limits the voltage of the output terminal of the MRAM cell304to a certain level thus keeping the voltage drop across the MRAM cell304constant. The source follower312comprises an NMOS transistor362, having a gate coupled to a second clamp voltage VC2, a source coupled to the output terminal of the MRAM cell304through the transistor322, and a drain coupled to a first node323. The second clamp voltage VC2is about 0.7V. Because the voltage of the source of the NMOS transistor362is determined according to the clamp voltage VC2of about 0.7V, the voltage drop across the MRAM cell304is kept at a constant of about 0.3V. Thus, the memory cell current Icellflowing through the MRAM cell304is determined according to the resistance of the MRAM cell304.

The sense amplifier302is coupled to the output terminals of the reference cells306,308, and310through the source follower circuit316. The source follower circuit316clamps the voltages of the output terminals of the reference cells to keep the voltage drops across the reference cells306,308, and310identical to the voltage drop across the memory cell304. The source follower circuit316includes NMOS transistors364,366, and368, having gates coupled to the second clamp voltage VC2and sources coupled to the output terminals of the reference cells306,308, and310. Because the voltage of the sources of the NMOS transistor364,366, and368are determined according to the clamp voltage VC2of about 0.3V, the voltage drops across the reference cells306,308, and310are kept at a constant of about 0.3V. Thus, the reference currents IR1, IR2, and IR3flowing through the reference cells306,308, and310are determined according to the resistance of the reference cells306,308, and310.

The current mirror circuit314is coupled between a voltage source VDDand a first node323and second nodes325,327, and329. The current mirror circuit314includes PMOS transistors332,334,336, and338. The PMOS transistor332has a source coupled to the voltage source VDDand a gate and a drain coupled to the first node323. The PMOS transistor332receives the memory cell current Icelland generates a memory cell voltage Vcellat the first node323. The PMOS transistors334,336, and338have sources coupled to the voltage source VDD, gates coupled to the first node323, and drains coupled to the second nodes325,327, and329. Because the voltages of the sources and the gates of the PMOS transistors334,336, and338are respectively the voltage source VDDand the memory cell voltage Vcell, and the currents flowing through the drains of the PMOS transistors334,336, and338are respectively the reference currents IR1, IR2, and IR3, the currents flowing through the drains of the PMOS transistors334,336, and338therefore cause the voltage drops across the PMOS transistors334,336, and338and respectively generate the reference voltages VR1, VR2, and VR3at the second nodes325,327, and329. Thus, the reference voltages VR1, VR2, and VR3respectively reflect the resistance of the reference cells306,308, and310.

The pre-charge circuit318is coupled between the first node323and the second nodes325,327, and329. The pre-charge circuit318comprises a plurality of switches352,354, and356, respectively coupled between the first node323and one of the second nodes325,327, and329. The pre-charge circuit318turns on switches352,354, and356according to a pre-charge signal PRE to couple the first node323and the second nodes325,327, and329before the MRAM cell304is accessed, thus, resetting the memory cell voltage Vcelland the reference voltages VR1, VR2, and VR3. For example, when the pre-charge signal PRE turns on the switch352, the first node323is coupled with the second node325, keeping the voltages of the first node323and the second node325identical.

When the sense amplifier302generates the memory cell voltage Vcelland the reference voltages VR1, VR2, and VR3, the voltages Vcell, VR1, VR2, and VR3are processed by a comparator and a decoder to obtain the data bits stored in the MRAM cell304.FIG. 4shows the comparators402,404, and406and the decoder408comprised by the MRAM300according to the invention. The comparators402,404, and406compare the memory cell voltage Vcellwith the reference voltages VR1, VR2, and VR3to generate the comparison result signals DOUT1, DOUT2, and DOUT3. The decoder408then decodes the comparison results signals DOUT1, DOUT2, and DOUT3to obtain the 2-bit data D0and D1stored in the MRAM cell304.

The sense amplifier302, the reference sells306,308, and310, and the comparators402,404, and406, and the decoder408provided by the invention form an output circuit of a memory. When an MRAM cell is selected, the MRAM300transforms the resistance of the selected MRAM cell302to corresponding 2-bit data D0and D1with the sense amplifier302, the comparators402,404and406, and the decoder408. The output circuit is not only suitable for MRAM, but also suitable for any memory composed of memory cells with changeable resistance, such as Phase Change Memory (PCM), to improve the performance thereof. Additionally, the output circuit can be used in any multiple-state memory. In one embodiment, if any memory cell of the memory stores N-bit data, an output circuit comprising an 2N-state sense amplifier and (2N−1) reference cells and comparators can be used to extract the N-bit data stored in specific memory cell of the memory.

FIG. 5shows a portion of the circuits of an MRAM500according to the invention. Only the sense amplifier502of MRAM500is different from MRAM300inFIG. 3. The MRAM500includes a four-state sense amplifier502, at least one four-state MRAM cell504, and reference cells506,508, and510. The sense amplifier502generates a memory cell voltage Vcelland a plurality of reference voltages VR1, VR2, and VR3according to the resistance of the MRAM cell504and the reference cells506,508, and510. The MRAM500further comprises the comparators402,404, and406and the decoder408shown inFIG. 4. After the sense amplifier502generates the memory cell voltage Vcelland the reference voltages VR1, VR2, and VR3, the memory cell voltage Vcelland the reference voltages VR1, VR2, and VR3are processed by the comparators402,404, and406and the decoder408to obtain the data bits D0and D1stored in the MRAM cell504.

The sense amplifier502includes a source follower512, a source follower circuit516, a current mirror circuit514, a pre-charge circuit518, and a voltage clamp circuit520. The sense amplifier502is different from the sense amplifier302only in that the voltage clamp circuit520corrects the defect of the sense amplifier302.FIG. 6ashows a corresponding relationship between the memory cell voltage Vcelland the reference voltages VR1, VR2, and VR3generated by the sense amplifier302ofFIG. 3. During the periods602,604,606, and608, the read word line enable signal RWLEN is enabled to couple the MRAM cell304with the sense amplifier302. During the periods602,604,606, and608, the word lines WL11, WL10, WL01, and WL00are respectively enabled. Thus, the resistance of the MRAM cell304during the periods602,604,606, and608are respectively the resistance of resistors372,374,376, and378.

As periods602,604,606, and608begin, the reference voltages VR1, VR2, and VR3are pulled up the voltage source level VDDwhile MRAM cell304is coupled to the sense amplifier302, and the reference voltages are restored to the normal level being available for the decoder408to decode after waiting for tens of nano seconds. This is because the gates of the PMOS transistors336and338are coupled to the first node323, and the MRAM cell304must draw charge from the first node323to generate the memory cell current Icell, delaying the saturation of the PMOS transistors334,336, and338. Thus, the access time of the MRAM cell304is increased and the performance of the MRAM300is degraded.

To correct this defect, voltage clamp circuit520is added to the sense amplifier502. When the MRAM cell504is coupled to the sense amplifier502the voltage clamp circuit520couples to and clamps voltages of the second nodes525,527, and529to the first clamp voltage VC1according to a voltage clamp signal VB. Charge is thus drawn from the first node523to generate the memory cell current Icell. The voltage clamp circuit520comprises switches542,544, and546coupled between the first clamp voltage VC1and the second nodes525,527, and529. The voltage clamp signal VBturns on the switches542,544, and546to clamp the voltages of the second nodes525,527, and529at the first clamp voltage VC1. The voltages of the second nodes525,527, and529are thus prevented from being pulled up to the voltage source level VDDas shown inFIG. 6a.FIG. 6bshows a corresponding relationship between the memory cell voltage Vcelland the reference voltages VR1, VR2, and VR3generated by the sense amplifier502ofFIG. 5, wherein during the periods622,624,626, and628ofFIG. 6bthe operations of the sense amplifier502are executed correspondingly to the periods602,604,606, and608ofFIG. 6a. It is shown inFIG. 6bthat the reference voltages VR1, VR2, and VR3is not pulled up to the voltage source level VDDagain, decreasing the access time of the MRAM cell504by about 50 ns and improving performance of the MRAM500.

FIG. 7shows a portion of the circuits of an MRAM700according to the invention. The MRAM700is different from the MRAM500ofFIG. 5only in omission of the pre-charge circuit518. Because the pre-charge circuit518is not a necessary module for the sense amplifier702, the pre-charge circuit518is deleted from the sense amplifier702ofFIG. 7.

The invention provides an output circuit of a memory. The memory is composed of a plurality of memory cells with changeable resistance. The output circuit comprises a multi-state sense amplifier, at least one multiple-state memory cell, a plurality of reference cells, a plurality of comparators, and a decoder. Because the output circuit is equipped with the sense amplifier to facilitate memory cell access, access time of the memory cell is reduced.