Data processing device and data processing system

A data processing device includes a first CPU (Central Processing Unit), a first memory, a CAN (Controller Area Network) controller and a system bus coupled to the first CPU, the first memory and the CAN controller, wherein the CAN controller comprises a receive buffer that stores a plurality of messages each of which has a different ID, and a DMA (Direct Memory Access) controller that selects the latest message among messages having a fist ID stored in the receive buffer and transfers the selected latest message to the first memory, wherein the message is one of CAN, CAN FD and CAN XL messages.

BACKGROUND

The present invention relates to a data processing device and a data processing system, and more particularly, the present invention relates to a data processing device and a data processing system incorporating automobile communication techniques.

CAN (Controller Area Network) is widely used as a communication technique for automobiles. CAN have a standard called CAN 2.0A, 2.0B, CAN FD (CAN with Flexible Data rate). A standard called CAN XL (CAN extra Large payload) is also being developed. CAN is used for connecting between ECUs (Electronic Control Unit) mounted on automobiles, and transmission and reception of sensor information (water temperature, voltage, etc.) and data processed by ECUs are carried out through CAN.

Techniques relating to CAN are disclosed in Patent Document 1. Patent Document discloses techniques of replacing a CAN FD frame with an alternative data conforming to CAN 2.0B.

Patent Document

SUMMARY

In order for the CPU to process the message received by CAN controller in the data processing device (ECU or Microcontroller) equipped with CAN controller and the CPU, the received message must be transferred to a memory area accessible by the CPU. Messages received by CAN controller include sensor information (water temperature, voltages, etc.), diagnostic results of the ECUs, software update information, etc. The sensor information is transmitted from the sensor at every predetermined timing, but the CPU does not need all the sensor information and may need only the latest value. On the other hand, in the case of the ECU diagnostic results or software update information, the CPU needs all the transmitted messages. After all received messages have been transferred to the memory area, if the CPU chooses the required message, there is a problem that CPU load and a traffic of a bus, by which the CPU, memory, and CAN controller are connected, increases.

Other objects and novel features will become apparent from the description of the specification and drawings.

A data processing device according to an embodiment includes a first CPU (Central Processing Unit), a first memory, a CAN (Controller Area Network) controller and a system bus coupled to the first CPU, the first memory and the CAN controller, wherein the CAN controller comprises a receive buffer that stores a plurality of messages each of which has a different ID, and a DMA (Direct Memory Access) controller that selects the latest message among messages having a fist ID stored in the receive buffer and transfers the selected latest message to the first memory, wherein the message is one of CAN, CAN FD and CAN XL messages.

In a data-processing device according to an embodiment, an increase in CPU load and System bus traffic can be suppressed.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to an embodiment will be described in detail by referring to the drawings. In the specification and the drawings, the same or corresponding form elements are denoted by the same reference numerals, and a repetitive description thereof is omitted. In the drawings, for convenience of description, the configuration may be omitted or simplified. Also, at least some of the embodiments may be arbitrarily combined with each other.

First Embodiment

FIG.1is a block diagram showing a configuration of a data processing system100according to first embodiment.

As shown inFIG.1, data processing system100includes ECUs (Electronic Control Unit)1-7, which are data processing devices. The ECUs are connected via CAN XL bus113, CAN bus114, Ethernet switch115.

ECU1has a microcontroller101, CAN XL transceiver102, CAN transceiver103, Ethernet PHY104. Microcontroller101has a system bus105, CPU106, ROM107, RAM108, I/O109, CAN controller110,111, and Ethernet controller112. ECUs2to7may have the same configuration as that of ECU1, or may have a different configuration.

CPU106executes a program (software) stored in ROM107. The data required for the program execution and the data of the program execution result are stored in RAM108. ROM107stores programs for processing (e.g., engine control, brake control, sensor control, and fault diagnostics) to be implemented by the ECUs.

CAN XL Transceiver102transmits and receives signals between CAN XL bus113and CAN controller110. CAN Transceiver103transmits and receives signals between CAN bus114and CAN controller103. Ethernet PHY104transmits and receives signals between Ethernet switch115and Ethernet controller112.

CAN controller110and111are capable of transferring the data received through CAN XL bus113and CAN bus114to RAM108. Further, CAN controller110and111have a function of transmitting data to CAN XL bus113and CAN bus114according to an instruction from CPU106or the like. Ethernet controller112also has a function to transmit and receive data through Ethernet switch115.

In the first embodiment, CAN controller110,111, and RAM108are characterized. Other blocks are general and will not be described in detail. A detailed description of CAN controller110,111, and RAM108will be described below.

FIG.2is a schematic diagram of RAM108. As shown inFIG.2, RAM108has a Receive buffer200and a Receive queue201. Receive buffer200and Receive queue201have a predetermined addressing space. Details of these blocks will be described later.

CAN protocol engine300, based on the CAN communication protocol, creates the data to be transmitted to CAN XL bus113(CAN bus114) and interprets the received data from CAN XL bus113(CAN bus114). Specifically, based on the data (stored in Send buffer302) instructed by Send handler, CAN transmission data including message information such as CAN ID, DLC (Data Length Code), RTR (Remote Transmission Request), and Error state and payload is created. The message information and payload are extracted from the received CAN data. The extracted message information and payload are sent to Receive handler303. In the following, the term “message” includes information such as CAN ID, DLC, and RTR and payload.

Receive handler303stores the received message in Receive buffer305based on an instruction of Pointer304. Pointer304includes Head pointer and Tail pointer. Head pointer indicates an address of Receive buffer305in which the first message is stored at a given time. Tail pointer indicates an address of Receive buffer305in which the last message was stored at a predetermined time. Details will be described later.

Trigger generator307generates a transfer-initiation trigger signal based on Timer306, Receive handler303, software requests, and the like. Timer306measures a predetermined elapse of time.

When DMA controller308receives a transfer initiation trigger signal from Trigger generator307, it transfers the data stored in Receive buffer305over System bus105to RAM108without CPU106intervention. When transferring, DMA controller308refers to Transfer rule309. Transfer rule309is stored in a memory or a register in DMA controller. After the transfer is completed, DMA controller308notifies Interrupt controller310of the transfer completion. Details will be described later.

When Interrupt controller310receives a notification of transfer complete from DMA controller308, it generates an interrupt and notifies the software (CPU106) of transfer completion.

Next, the specific operation of CAN controller110(111) will be described with reference toFIGS.4to11. First, at reset (power-on), both Head pointer and Tail pointer of Pointer304shall be set to a start address of Receive buffer305.FIG.4is a flow chart showing the operation of Receive handler303. When Receive handler303receives the message, it stores the message at the address indicated by Tail pointer (step S100). After the message is stored, Tail pointer is incremented (step S101). Steps S100and S101are performed each time a message is received.

FIG.5shows, as a specific example, states of Receive buffer305, Head pointer, Tail pointer when six messages are received in order. The address indicated by Head pointer contains the first message (CAN ID101, water temperature 100 degrees). After the first message is stored, Tail pointer is moved down (incremented) one below Head pointer. The second message (CAN ID201, the diagnostic result of ECU2) is stored at the address indicated by Tail pointer, one below Head pointer. Subsequently, the third to sixth messages are stored in Receive buffer305as shown inFIG.5. The message to which CAN ID101is assigned is a message transmitted from the water temperature sensor. The water temperature sensor transmits the water temperature information at predetermined time intervals. The message to which CAN ID102is assigned is a message transmitted from the voltage monitor. Like the water temperature sensor, the voltage monitor transmits a voltage value at predetermined time intervals. Each of the diagnostic results of the ECUs is generated and transmitted by the corresponding ECU.

Next, the operation of DMA controller308when Trigger generator307generates the transfer-start trigger signal will be described. Here, it is assumed that Trigger generator307generates the transfer start trigger signal based on the output signal of Timer306, and Trigger generator307generates the transfer start trigger signal after receiving the six messages described above.

FIG.6is a flow chart showing the operation of DMA controller308when the transfer-start trigger signal is received. First, DMA controller308checks whether there is a received message (step S200). If there is a message received, DMA controller308transfers the message stored in Receive buffer305to Receive buffer200(step S201). DMA controller308also transfers the messages stored in Receive buffer305to Receive queue201(step S202). After message transferring is complete, the address indicated by Tail pointer is set to Head pointer (step S203).

FIG.7is a flow chart showing the detailed operation of the message transferring to Receive buffer200(step S201). First, CAN ID information is cleared (step S300). CAN ID information will be described later. Next, DMA controller308sequentially reads the messages stored in Receive buffer305from the address indicated by Tail pointer to the address indicated by Head pointer (step S301).

Next, DMA controller308determines whether to forward the read message to Receive buffer200based on Transfer rule309(step S302).FIG.8shows a specific embodiment of Transfer rule309. As shown inFIG.8, the transfer rule is that the messages to which CAN ID101and102are assigned are transferred to Receive buffer200. The transfer rule is also that messages with CAN ID201and202are transferred to Receive queue201.

Returning toFIG.7, the operation of DMA controller308will be described. As described above, DMA controller308reads out messages in order from the addresses indicated by Tail pointer. Therefore, DMA controller308reads out in order from the sixth message (CAN ID201, the diagnostic result of ECU4). Since the fourth message (CAN ID101, water temperature 99 degrees) is a message to be transferred to Receive buffer200(Y in step S302), DMA controller308checks whether CAN ID101of the fourth message is registered in CAN ID information (step S303). Since nothing is registered in CAN ID information (N in the step S303), DMA controller308transfers the fourth message to Receive buffer200(step S303) and registers CAN ID101in CAN ID information (step S304). DMA controller308then determines that the third message (CAN ID102, voltage 12V) is to be transferred to Receive buffer200. Since CAN ID102is not registered in CAN ID information, DMA controller308transfers the third message to Receive buffer200and registers CAN ID102in CAN ID information. DMA controller308then determines that the first message (CAN ID101, water temperature 100 degrees) is to be transferred to Receive buffer200. However, since CAN ID101has already been registered in CAN ID information, DMA controller308does not transfer the first message to Receive buffer200(Y in the step S303).

FIG.9shows the messages transferred to Receive buffer200as a result of the transfer described above. The fourth message and the third message are transferred to Receive buffer200. Now we focus on the first and fourth messages. Both the first and fourth messages have the CAN ID101and are informational about the water temperature. However, only the fourth message is transferred to Receive buffer200. This means that only the latest sensor information among the time-varying sensor information is transferred to Receive buffer200. The same applies to the voltage monitor to which CAN ID102is applied.

Next, the message transferring to Receive queue201(step S202) will be described in detail.

FIG.10is a flowchart showing the operation of the transfer to Receive queue201. DMA controller308sequentially reads the messages stored in Receive buffer305from the address indicated by Tail pointer to the address indicated by Head pointer (step S400). DMA controller308determines whether to transfer the read message to Receive queue201based on Transfer rule309(step S401). InFIGS.5and8, DMA controller308transfers the sixth, fifth, and third messages to Receive queue201(step S402).

FIG.11shows messages transferred to Receive queue201as a result of the transfer described above. As shown inFIG.11, all of the messages having CAN ID specified in Transfer rule are transferred to Receive queue201. This is the difference from the messages transferred to Receive buffer200. Since all messages are required for the diagnosis result of ECU, all received messages are transferred to Receive queue201.

DMA controller308notifies Interrupt controller310of the completion of the transfer after the completion of the message transfer to Receive buffer200and Receive queue201. When Interrupt controller310receives the notification of transfer complete, it generates an interrupt and notifies the software (CPU160) of transfer completion.

The operation of the above-described DMA controller308is performed each time a transfer-start trigger signal is received from Trigger generator307. Although Trigger generator307generates the transfer-start trigger signal based on Timer306output signal, but is not limited to this. The transfer start trigger signal may be generated based on the output signal of Receive handler303. For example, when Receive handler303receives a predetermined number of messages, the transfer start trigger signal may be generated. Alternatively, the transfer-start trigger signal may be generated in accordance with an instruction of a software program executed by CPU160.

As described above, based on Transfer rule309, CAN controller110transfers only the latest message to Receive buffer200and all messages to Receive queue201. This reduces CPU106workload and System bus105traffic.

Consider further a technique for transferring only the latest sensor information. For example, by providing a memory area (instead of Receive buffer305) that is constantly overwritten with the sensor information each time the sensor information (water temperature, voltage, etc.) is received, only the latest sensor information can be transferred. InFIG.5, the first message (CAN ID101, 100 degrees water temperature) is overwritten with the fourth message (CAN ID101, 99 degrees water temperature). If DMA controller308transfers the fourth message remaining in the memory area to Receive buffer200, the same result of first embodiment will be obtained. In order to provide the memory area that is constantly overwritten with sensor data, the memory area may be divided for each CAN ID. For example, by providing the memory area dedicated to CAN ID100, only the most recent message to which CAN ID100is assigned is stored in this memory area. However, in this method, the memory area must be provided for each CAN ID. In the CAN standard, CAN ID is 11 bits (standard format) or 29 bits (extended format). If the memory area is provided for each CAN ID, a large number of memory areas must be provided (an increase in memory capacity) and memory usage can be inefficient (such as unused or rarely used CAN ID). On the other hand, in the present first embodiment, such problems can be suppressed.

As described above, the data processing device (ECU)1according to first embodiment has CAN controller110, and CAN controller110has DMA controller308for transferring the latest CAN message to Receive buffer200based on Transfer rule309. This allows CPU106loads and System bus105traffic to be suppressed.

Second Embodiment

The data processing system100according to second embodiment is the same as inFIG.1. However, CAN controller110and111are replaced by CAN controller110aand111a.FIG.12is a diagram of a CAN controller110a(111a) according to second embodiment. The difference from first embodiment is that Receive rule311and Receive buffer312are added.

Receive handler303astores the received message in a Receive buffer305or Receive buffer312based on instructions of Receive rule311and Pointer304a. Pointer304ahas Head pointer1and Tail pointer1for Receive buffer305and Head pointer2and Tail pointer2for Receive buffer312.

Next, the specific operation of CAN controller110a(111a) will be described with reference toFIGS.13to15.FIG.13illustrates a specific embodiment of Receive rule311. As shown inFIG.13, the receive rule is that messages to which CAN ID101and102are assigned are stored in Receive buffer305. The receive rule is also that messages with CAN ID201and202are stored in Receive buffer312.FIG.14, like first embodiment, shows the states of Receive buffer305, Head pointer1, Tail pointer1, Receive buffer312, Head pointer2, Tail pointer2when six messages are received sequentially. Note that the basic operations of Receive handler303a, Head pointer1,2, Tail pointer1,2are the same as those of Receive handler303, Head pointer, Tail pointer described in first embodiment, and thus will not be described in detail.

DMA controller308atransfers the messages stored in Receive buffer305and312to Receive buffer200or Receive queue201based on Transfer rule309a.FIG.15shows a specific embodiment of Transfer rule303a. First embodiment specifies a destination for each CAN ID, but second embodiment specifies a source (Receive buffer305or312), a destination (Receive buffer200or Receive queue201), and a trigger (Timer, or On receipt). As shown inFIG.15, the messages stored in Receive buffer305, that is, the messages to which CAN ID101and102are assigned, are transferred to Receive buffer200by using Timer306output signal as a trigger signal. Therefore, DMA controller308aoperates in the same way as first embodiment and transfers only the latest message among the messages to which CAN ID101is assigned to Receive buffer200. The same applies to messages to which CAN ID102is assigned. On the other hand, the messages stored in Receive buffer312, that is, the messages to which CAN ID201and202are assigned, are transferred to Receive queue201at the time of reception.

As a result of the above-mentioned transfer, the same message transfer as first embodiment is executed in Receive buffer200and Receive queue201, as shown inFIGS.9and11.

As described above, the data processing device according to the second embodiment has the same effects as those of the data processing device according to first embodiment. Moreover, since Receive buffer305for processing the latest message and Receive buffer312for processing all the messages are separated, each transfer start trigger can be divided, and efficient message transfer can be performed.

Third Embodiment

The data processing system100according to third embodiment is the same as inFIG.1. However, Microcontroller101is replaced by Microcontroller101a.FIG.16is a block diagram of a Microcontroller101aaccording to third embodiment; Differences from first embodiment are CPUs106a,106b,106c, RAMs108a,108b,108c, and Redundant operation circuit116, Fast peripheral bus117, Peripheral bus118, Access controllers119to124.

This third embodiment includes several Virtual machines (VMs) on Microcontroller101a. CPU106aand RAM108aconfigure VM0. CPU106band RAM108bconfigure VM1. CPU106cand RAM108cconstitute a VM2. Different operating systems run on different VMs. A Hyper visor is assigned to VM0. Note that each VM does not comprise solely of CPU and RAM. In order to explain the features of the present third embodiment, other components such as ROM are omitted.

Access controllers119to124control accesses to resources. Each VM is required to guarantee FFT (Freedom From Interference) for each VM's independence. Access controllers119to124are control circuits for realizing the FFT. Access controller119determines whether access to RAM108ais permitted or not based on the ID (bus ID) of the access source. The same applies to Access controllers120and121. Access controller122determines whether access to CAN controller110is permitted or not based on the ID of the access source. Access controller123determines whether access to Redundant operation circuit116is permitted or not based on the ID of the access source. Access controller124determines whether access to I/O109is permitted or not based on the ID of the access source.

In a Microcontroller with more than one VM, one CAN message received by CAN controller110may be used by more than one VM. For example, the temperature data described in first and second embodiments may be used in several application programs running on a plurality of VMs. In order to cope with such a situation, CAN controller110(DMA controller308) according to third embodiment has a function of transferring one CAN message to a plurality of slave circuits (RAM108ato108c, Ethernet controller112, Redundant operation circuit116, I/O109). Specifically, DMA controller308transfers a message with an ID permitted by Access controller corresponding to a destination slave of the message. For example, assume that one CAN message (e.g., CAN ID101, water temperature 99 degrees) is transferred to VM1and VM2. Bus IDs permitted by Access controller119are X and Z. Bus IDs permitted by Access controller120are Y and Z. In this situation, DMA controller308can simultaneously transfer a CAN message to VM1and VM2by transferring the CAN message with the bus ID set to Z to System bus105. The CAN message reception by CAN controller110is the same as that of first and second embodiments. Therefore, a description thereof will be omitted.

Another way to transfer one CAN message to more than one VM is to use Hyper visor. In this case, DMA controller308transfers the message for VM1and VM2to Hyper visor (VM0). Hyper visor then transfers the received message to VM1and to VM2two times. However, in this situation, CPU106ais overloaded, and a latency for completion of the transfer is degraded. On the other hand, in third embodiment, since DMA controller308can transfer a message to a plurality of VMs at a time, such problems can be suppressed.

Here, Redundant operation circuit116will be further explained. Redundant operation circuit116is a circuit for calculating redundancy codes such as CRC (Cyclic Redundancy Check) and CMAC (Cipher-based Message Authentication Code). CRC and CMAC may be assigned to CAN communication messages in order to increase the security of communication. When CAN controller110receives a CAN message with CRC or CMAC, it forwards the CAN message with CRC or CMAC to Redundant operation circuit116. Redundant operation circuit116performs CRC and CMAC operations on the basis of the transferred message, and sends the operation result to CAN controller110. CAN controller110can determine the correctness and security of the received CAN message based on the received operation result.

As described above, CAN controller110(DMA controller308) can forward one CAN message to a plurality of slaves. For example, assume that a CAN message with CRC is transferred to VM1. Bus IDs permitted by Access controller123are X and Y. In this situation, DMA controller308can transfer the CAN message with the CRC to VM1and Redundant operation circuit116by transferring the CAN message with the CRC with the bus ID as X to System bus105and Peripheral bus118. Redundant operation circuit116calculators the CRC based on the transferred message and sends the computed result to CAN controller110. CAN controller110determines the correctness of the CAN message with CRC based on the received operation result. That is, CAN controller110can check CRC of the received CAN message while transferring the received CAN message with CRC to VM1. CRC operation can be performed by the destination VM1(CPU106b), but in this case, the CPU load and the processing time increase. In third embodiment, such problems can be suppressed.

Finally, I/O109will be described. For example, assuming that an external Flash memory is connected to I/O109. Communication logs may be stored in the external Flash memory. CAN controller110can then transmit the communication log to the Flash memory via I/O109while forwarding the CAN message to Ethernet via Ethernet controller.

As described above, the data processing device according to third embodiment has the same effects as those of the data processing first and second embodiments. Further, since CAN controller110transfers one CAN message to a plurality of slaves, an increase of the processing time associated with the transfer can be suppressed.

Fourth Embodiment

The data processing system100according to fourth embodiment is the same as inFIG.1. However, CAN controllers110and111are replaced by CAN controllers110band111b.FIG.17is a block diagram of CAN controller110b(111b) according to fourth embodiment. A difference from first and second embodiments is DMA controller308b. DMA controller308bhas a Protocol translator400.

Protocol translator400is used to convert communication protocols. Protocol translator400can convert between CAN, CAN FD, CAN XL, AVTP (Audio Video Transport Protocol. Standard in IEEE1722) protocols. For protocol conversion, the corresponding bits between CAN, CAN FD, CAN XL, AVTP protocols may be determined in advance.

The basic operation of CAN controller110b(111b) is the same as that of first and second embodiments. However, the operation of DMA controller308bdiffers from first and second embodiments. Based on Transfer rule309b, DMA controller308btranslates the received CAN message into the designated protocol and forwards the translated message to Receive buffer200or Receive queue201.

FIG.18shows a specific embodiment of Transfer rule309b. As shown inFIG.18, CAN FD message stored in Receive buffer305is converted to AVTP format by Protocol translator400, and the converted message is transferred to Receive buffer200. CAN FD message stored in Receive buffer312is converted to CAN XL format by Protocol translator400, and the converted message is transferred to Receive queue201. Since the reception and transmission of CAN/CAN FD/CAN XL messages other than protocol conversion are the same as those of second embodiment, detailed information will be omitted.

FIG.19shows respective formats of CAN 2.0B (standard ID), CAN FD and CAN XL. CAN protocol engine300determines the respective formats. Specifically, the distinction between CAN 2.0B and CAN FD is determined by whether the FDF-bit is Dominant (CAN) or Recessive (CAN FD). The distinction between CAN FD and CAN XL is determined by whether the FDF bit is followed by the res bit or the XLF bit. The decision is sent to Receive handler303aand DMA controller and is used during protocol-translation.

AVTP format is used to transmit small-sized payloads received in CAN 2.0B or CAN FD (and possibly CAN XL) on a Ethernet or CAN XL capable of communicating larger-sized payloads. This can be accomplished by concatenating several small sized payloads into a AVTP formatted payload and embedding AVTP formatted payload into Ethernet or CAN XL format.

When executing the protocol conversion described above in CPU106, the CPU load increases. Moreover, when multiple payloads are concatenated by CPU, System bus105traffic increases because multiple payloads must be transferred from DMA controller308bto RAM108over System bus105. This fourth embodiment can suppress the increase in CPU-load and System bus traffic.

As described above, in the data processing device according to present fourth embodiment, the same effects as those of the data processing first and second embodiments can be obtained. Further, since the protocol conversion is performed inside CAN controller, it is possible to suppress the increase in the CPU load and System bus traffic associated with the protocol conversion.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist thereof.