Array substrate, display panel and display apparatus having recesses on data lines or gate lines

An array substrate, a display panel and a display apparatus are disclosed. The array substrate includes a plurality of gate lines (10; 50) and a plurality of data lines (30; 51), and pixel units arranged in an array. Each of the pixel units includes one pixel electrode (41; 42) and one thin film transistor, the data line (30; 51) serve as a source electrode (31; 311) of the thin film transistor, the gate line (10; 50) serve as a gate electrode (11) of the thin film transistor, and a drain electrode (32; 321; 322) of the thin film transistor is electrically connected to the pixel electrode (41; 42), at least one of the gate lines (10; 50) and the data lines (30; 51) has a recess (363; 364) provided thereon aligned with a spacer for fixing. With the recess (363; 364), the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of PCT/CN2015/076293 filed on Apr. 10, 2015, which claims priority under 35 U.S.C. § 119 of Chinese Application No. 201420628360.1 filed on Oct. 27, 2014, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

Embodiments of the present invention relate to an array substrate, a display panel and a display apparatus.

BACKGROUND

Currently, the liquid crystal display technology has been widely applied to televisions, cell phones and display of public information, and is a widely used display technology. A liquid crystal display panel of a liquid crystal display includes a counter substrate and an array substrate that are disposed in opposition, as well as a liquid crystal layer located between the two substrates. In addition, in order to guarantee the stability of thickness of the liquid crystal layer, Post Spacers (PSs) playing a supporting role are also provided between the two substrates in general. The PSs are usually fixed on the array substrate, and the design of PSs affects the uniformity of thickness of the liquid crystal layer, and then affects the quality of liquid crystal display.

SUMMARY

According to embodiments of the invention, there are provided an array substrate, a display panel and a display apparatus. By means of providing a recess on a gate line and/or a data line of the array substrate, when a counter substrate and the array substrate are cell-aligned, the recess and a post spacer are fixed and disposed opposite to each other (i.e. the recess and a post spacer are aligned for fixing). This can guarantee the uniformity and stability of thickness of a liquid crystal layer, and at the same time, the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

An array substrate provided by at least one embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, pixel units that are provided on the array substrate and arranged in an array, wherein each of the pixel units includes a pixel electrode and a thin film transistor, one of the data lines serves as a source electrode of the thin film transistor, one of the gate lines serves as a gate electrode of the thin film transistor, and a drain electrode of the thin film transistor is electrically connected to the pixel electrode, a recess configured for fixing a spacer and disposed opposite to the spacer (i.e. a recess aligned with a spacer for fixing) is provided on at least one of the gate line and the data line.

A display panel provided by embodiments of the invention includes the array substrate as stated in the above embodiment of the invention.

A display apparatus provided by embodiments of the invention includes the display panel as stated in the above embodiment of the invention.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of the embodiments of the invention apparent, hereinafter, the technical solutions of the embodiments of the invention will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the invention. It is obvious that the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments of the invention, those ordinarily skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope sought for protection by the invention.

Thicknesses of film layers and size and shape of regions in the attached drawings do not reflect the true scale of components of an array substrate, and are merely aimed to exemplarily illustrate contents of the invention.

In a study, as noticed by inventor(s) of the present application, PSs are generally provided in a region corresponding to a black matrix on a counter substrate, and for the sake of simplifying the manufacturing process, heights of PSs provided on the counter substrate are usually equal to each other. Then, after the counter substrate and an array substrate is cell-aligned, PSs provided between the two substrates contact with both the two substrates, so as to provide a supporting force, and to guarantee the uniformity and stability of thickness of a liquid crystal layer. However, with this structure, when the liquid crystal panel is bent and deformed under a stronger external pressure exerted on it, a movement of PSs may affect a display region, and then affect display of the liquid crystal display.

An array substrate provided by an embodiment of the invention, includes a plurality of gate lines, a plurality of data lines, and pixel units that are provided on the array substrate and arranged in an array. Each of the pixel units includes a pixel electrode and a thin film transistor, a data line directly serves as a source electrode of the thin film transistor, a gate line directly serves as a gate electrode of the thin film transistor, a drain electrode of the thin film transistor is electrically connected to the pixel electrode, and a recess configured for fixing a spacer and disposed opposite to the spacer is provided on the gate line and/or the data line.

In embodiments of the invention, a drain electrode of the thin film transistor and the pixel electrode may be electrically connected through a via hole. But embodiments of the invention are not limited to this, and for example, a pixel electrode may be directly taped to a drain electrode of a thin film transistor.

Additionally, the spacer in embodiments of the invention may be a post spacer, and may also be a pacer of other shape, as long as a recess configured for fixing it and disposed opposite to it can be provided on the array substrate. In the following embodiments, a post spacer will be described as an example.

In the case that no recess configured for fixing a spacer and disposed opposite to the spacer is provided on an array substrate, an end of the spacer is fixed on a counter substrate, and the end of the spacer close to the array substrate is not fixed. In embodiments of the invention, with the aid of provision of a recess configured for fixing a spacer and disposed opposite to the spacer (namely, the recess and the spacer are disposed in opposition and the recess is useful for fixing the spacer), it can be achieved that, at least in a direction parallel to the plane in which the array substrate lies, the position of the end of the spacer close to the array substrate relative to the array substrate is fixed.

In the array substrate provided by embodiments of the invention, by means of providing a recess on a gate line and/or a data line of the array substrate, the recess and a post spacer are fixed and disposed opposite to each other when a counter substrate and the array substrate are cell-aligned, and thus the spacing between the counter substrate and the array substrate is longitudinally fixed and laterally fixed. This can guarantee the uniformity and stability of thickness of a liquid crystal layer, and at the same time, the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

In an array substrate provided by embodiments of the invention, the structure of the array substrate is shown inFIG. 1. As an example, consider the following: a pixel unit including a pixel electrode42is a first pixel unit, and a pixel unit including a pixel electrode41is a second pixel unit. In the first pixel unit, a thin film transistor is provided at the intersection point of the gate line10and the data line30, the gate electrode11of the thin film transistor and the gate line10are formed integrally, the source electrode31of the thin film transistor and the data line30are formed integrally, and a drain electrode32is electrically connected to the pixel electrode42through a via hole361; in the second pixel unit, a thin film transistor is provided at the intersection point of the gate line10and the data line30, the gate electrode11of the thin film transistor and the gate line10are formed integrally, the source electrode31of the thin film transistor and the data line30are formed integrally, and a drain electrode is electrically connected to the pixel electrode41through a via hole362. The first pixel unit and the second pixel unit share the source electrode31, and the structure of the source electrode31may be the structure shown inFIG. 1.

According to the array substrates provided by embodiments of the invention, the structure of another array substrate is shown inFIG. 2. As an example, consider the following: a pixel unit including a pixel electrode42is a first pixel unit, and a pixel unit including a pixel electrode41is a second pixel unit. In the first pixel unit, a thin film transistor is provided at the intersection point of the gate line10and the data line30, the gate electrode11of the thin film transistor and the gate line10are formed integrally, the source electrode31of the thin film transistor and the data line30are formed integrally, and a drain electrode32is electrically connected to the pixel electrode42through a via hole361; in the second pixel unit, a thin film transistor is provided at the intersection point of the gate line10and the data line30, the gate electrode11of the thin film transistor and the gate line10are formed integrally, the source electrode31of the thin film transistor and the data line30are formed integrally, and a drain electrode is electrically connected to the pixel electrode41through a via hole362. The first pixel unit and the second pixel unit share the source electrode31, and the structure of the source electrode31may be the structure shown inFIG. 2.

It is worth noting that, structure of a source electrode31may be the structure shown inFIG. 1, and may also be the structure shown inFIG. 2. Of course, it should be understood by those skilled in the art that, regarding the structure of a source electrode31, there may also be other structures, and they are not used to make specific limitations herein.

In a possible embodiment, in an array substrate provided by embodiments of the invention, at least two recesses are provided on a gate line and/or a data line, namely, at least two recesses are provided on the gate line or the data line, or total number of the recesses provided on the gate line and the data line is at least two.

In a possible embodiment, in an array substrate provided by embodiments of the invention, the at least two recesses are two recesses, which are provided on the gate line.

In a possible embodiment, in an array substrate provided by embodiments of the invention, the at least two recesses are two recesses, one is provided on the gate line, and the other one is provided on the data line.

In an array substrate provided by embodiments of the invention, a recess is provided on a gate line, and likewise, a recess may also be provided on a data line.

In an embodiment of the invention, the at least two recesses are two recesses, namely, referring toFIG. 1andFIG. 2, a circular recess363and a rectangular recess364are provided on the gate line10between the first pixel unit and the second pixel unit, but it needs to be explained that, corresponding position and number of recesses may be set according to setting requirements for the PS position.

Upon concrete implementation, as shown inFIG. 1orFIG. 2, a recess363and a recess364are provided on the gate line10, and a recess363and a recess364are provided directly above the gate line10. Certainly, the two recesses may also be provided on the data line30simultaneously, and it is also possible that, one is provided on a gate line10, and the other is provided on a data line.

It is to be noted that, recesses (the recess363and the recess364) provided on the gate line10may be formed synchronously with via holes (a via hole361and a via hole362). In this way, an additional mask is not required, and the original manufacturing process flow of an array substrate may be used, without additionally increasing the equipment cost.

In a possible embodiment, in an array substrate provided by embodiments of the invention, the recesses include a circular recess and/or a rectangular recess. It is to be noted that, the shape of the recesses includes but is not limited to a circular shape, and a polygonal shape (e.g. a rectangular shape), as long as the recess can fixa PS and is disposed opposite to the PS.

In a possible embodiment, in an array substrate provided by embodiments of the invention, the two recesses have different depths, so as to facilitate discrimination between primary and secondary PSs when the recesses and the PSs are fixed and disposed opposition to each other. For example, a depth of a recess for fixing the primary PS is smaller, that is, shallower; and a depth of a recess for fixing the secondary PS is bigger, that is, deeper.

Upon specific implementation, difference in depth of recesses may be achieved by gray-level exposure, and difference in depth of recesses may also be achieved by laying a pixel electrode in one of two recesses. The pixel electrode may be provided in one layer or multiple layers, so as to change depth of the recess.

Hereinafter, with the array substrate structure shown inFIG. 1as an example, the fabrication process for it will be described in detail in combination withFIG. 3andFIG. 4. Its fabrication process, for example, includes the following steps 1 to 6.

Step 1, a metal layer (e.g. of aluminum (Al)) is deposited by sputtering onto a base substrate1of an array substrate, and coating a photoresist, exposure, development and etching are conducted respectively, so as to form a pattern of a gate line, a gate electrode11and a common electrode line.

Step 2, a gate insulating layer21is deposited by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the material used comprises such as silicon nitride.

Step 3, a semiconductor layer is deposited, for example, amorphous silicon (a-Si) is deposited by PECVD or an Indium Gallium Zinc Oxide (IGZO) is deposited by sputtering; coating a photoresist, exposure, development and etching are conducted, so as to form pattern of an active layer22.

Step 4, depositing a metal layer (e.g. of aluminum (Al)) by sputtering, coating a photoresist, exposure, development and etching are conducted, so as to form a pattern of a data line, a source electrode311, a drain electrode321and a drain electrode322; wherein, the active layer22is located below the source electrode311, the drain electrode321and the drain electrode322, and located above the gate insulating layer21.

Step 5, a passivation layer23is deposited, for example, silicon nitride is deposited by PECVD or a resin layer is coated; coating a photoresist, exposure, development and etching are conducted, so as to form a via hole361and a via hole362; the drain electrode321of a thin film transistor is exposed by the via hole361, and the drain electrode322of a thin film transistor is exposed by the via hole362; while the via hole361and the via hole362are formed, a recess363and a recess364are also formed, and the position of the recess363and the recess364may be on a gate line and/or a data line.

Step 6, sputtering a conductive material layer of a transparent metal oxide (e.g. Indium Tin Oxide (ITO), which is an N-type oxide semiconductor), coating a photoresist, exposure, development and etching are conducted, so as to form a pixel electrode41and a pixel electrode42; wherein, the pixel electrode42is electrically connected to the drain electrode321of the thin film transistor through the via hole361, the pixel electrode41is electrically connected to the drain electrode322of the thin film transistor through the via hole362; and a layer of pixel electrode41may be provided in the recess363or the recess364. For example, as shown inFIG. 4, a layer of pixel electrode41is provided in the recess364, so as to change the depth of the recess, and this is aimed to make discrimination between the primary PS and the secondary PS when recesses and PSs are fixed and disposed opposite to each other.

It is worth noting that, in embodiments of the invention, the gate line and the data line may be fabricated by using a metallic material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W) or the like, and may also be fabricated by using an alloy of these materials; the gate line may be a single-layered structure, and may also adopt a multilayered structure, such as, Mo\Al\Mo, Ti\Cu\Ti, Mo\Ti\Cu. The gate insulating layer21may adopt silicon nitride or silicon oxide; the gate insulating layer21may be a single-layered structure, and may also be a multilayered structure, such as silicon oxide/silicon nitride. The active layer22may adopt amorphous silicon, or an oxide semiconductor. The passivation layer23may adopt an inorganic substance, such as silicon nitride, and may also adopt an organic substance, such as resin; the pixel electrode41and the pixel electrode42are fabricated by using a transparent conductive oxide indium zinc oxide (IZO), ITO or other transparent metal oxide conductive material.

The planar graph of manufacturing a complete array substrate is shown inFIG. 5, in which, a Black Matrix (BM) resin is coated on a gate line50and data line51, and a recess541and a recess542are provided on the gate line50. Of course, a recess543and a recess544may also be provided on the data line51, red (R), green (G) and blue (B) resins (R resin52, G resin53, B resin54) may be produced on the array substrate to be integrated with array circuits, and may also be produced on a counter substrate.

A display panel provided by embodiments of the invention includes the array substrate as stated in any of embodiments of the invention.

As shown inFIG. 6, for example, the display panel includes a counter substrate100and an array substrate200that are coupled in a sealing way with a sealant, and a liquid crystal layer and post spacers300configured for maintaining the cell thickness are provided between the counter substrate100and the array substrate200. For example, a gate insulating layer21and a passivation layer23are sequentially arranged on a gate line11in the array substrate, and recesses364are provided at a location corresponding to the gate line11in the passivation layer23, the recesses364being configured for fixing the post spacers300and disposed opposite to the post spacer300. It is to be noted that, only partial structures of the display panel is shown inFIG. 6.

In the display panel provided by embodiments of the invention, by means of providing a recess on a gate line and/or a data line of an array substrate, the recess and a post spacer are fixed and disposed opposite to each other when a counter substrate and the array substrate are cell-aligned, and thus the spacing between the counter substrate and the array substrate is longitudinally fixed and laterally fixed. This can guarantee the uniformity and stability of thickness of a liquid crystal layer, and at the same time, the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

A display apparatus provided by embodiments of the invention includes the display panel as stated in an embodiment of the invention.

In the above display apparatus provided by embodiments of the invention, by means of providing a recess on a gate line and/or a data line of an array substrate in the display panel, the recess and a post spacer are fixed and disposed opposite to each other when a counter substrate and the array substrate are cell-aligned, and thus the spacing between the counter substrate and the array substrate is longitudinally fixed and laterally fixed. When the recess and the post spacer are fixed and disposed opposite to each other, the uniformity and stability of thickness of a liquid crystal layer are ensured, at the same time, the post spacer is prevented from moving to has an impact on a display region when the substrate is bent and deformed under an external pressure, as compared to the case that no recess is provided on a gate line and/or a data line.

In a possible embodiment, in the display apparatus provided by embodiments of the invention, the display apparatus is a liquid crystal display apparatus.

The display apparatus provided by embodiments of the invention may be an electronic paper, an OLED panel, a cell phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any other product or component having a display function.

An array substrate, a display panel and a display apparatus are provided by embodiments of the invention. By means of providing a recess on a gate line and/or a data line of the array substrate, the recess and a post spacer are fixed and disposed opposite to each other when a counter substrate and the array substrate are cell-aligned, and thus the spacing between the counter substrate and the array substrate is longitudinally fixed and laterally fixed. This can guarantee the uniformity and stability of thickness of a liquid crystal layer, and at the same time, the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

The descriptions made above are merely exemplary embodiments of the invention, but are not used to limit the protection scope of the invention. The protection scope of the invention is defined by attached claims.

This application claims the benefit of priority from Chinese patent application No. 201420628360.1, filed on Oct. 27, 2014, the disclosure of which is incorporated herein in its entirety by reference as a part of the present application.