Method and computer program product and apparatus for handling sudden power off recovery

The invention introduces a non-transitory computer program product for handling a sudden power off recovery (SPOR) to include program code to: drive a flash access interface to read pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); mark the last correct page of the current block according to page read statuses for the current block; drive the flash access interface to read protection information of pages of a temporary block in sequence, so as to mark the first incorrect page of the temporary block; and drop data of the first incorrect page and pages thereafter of the temporary block.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Patent Application No. 201910664125.7, filed in China on Jul. 23, 2019; the entirety of which is incorporated herein by reference for all purposes.

BACKGROUND

The disclosure generally relates to flash memory and, more particularly, to methods and computer program products and apparatuses for handling sudden power off recovery (SPOR).

Flash memory devices typically include NOR flash devices and NAND flash devices. NOR flash devices are random access—a host accessing a NOR flash device can provide the device any address on its address pins and immediately retrieve data stored in that address on the device's data pins. NAND flash devices, on the other hand, are not random access but serial access. It is not possible for NAND to access any random address in the way described above. Instead, the host has to write into the device a sequence of bytes which identifies both the type of command requested (e.g. read, write, erase, etc.) and the address to be used for that command. The address identifies a page (the smallest chunk of flash memory that can be written in a single operation) or a block (the smallest chunk of flash memory that can be erased in a single operation), and not a single byte or word.

Data programming operations may be interrupted after a sudden power off (SPO) induced by a natural or man-made disaster. Thus, it is desirable to have methods and computer program products and apparatuses for handling SPOR, so as to recover the interrupted data programming operations.

SUMMARY

In an aspect of the invention, a method for handling a sudden power off recovery (SPOR) is performed by a processing unit when loading and executing relevant firmware or software code to include steps: reading pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); marking the last correct page of the current block according to page read statuses for the current block; reading protection information of pages of a temporary block in sequence, so as to mark the first incorrect page of the temporary block; and dropping data of the first incorrect page and pages thereafter of the temporary block. The current block is a multi-level cell (MLC) block or a triple level cell (TLC) block. The temporary block is a single-level cell (SLC) block. The protection information of the first incorrect page of the temporary block includes address information pointing to a page after the last correct page of the current block.

In another aspect of the invention, a computer program product for handling a SPOR is introduced to include program code when being loaded and executed by a processing unit to practice the method described above.

In a further aspect of the invention, an apparatus for handling a SPOR is introduced to include a flash access interface and a processing unit. The processing unit is arranged to operably perform operations of the method described above.

Both the foregoing general description and the following detailed description are examples and explanatory only, and are not restrictive of the invention as claimed.

DETAILED DESCRIPTION

Reference is made in detail to embodiments of the invention, which are illustrated in the accompanying drawings. The same reference numbers may be used throughout the drawings to refer to the same or like parts, components, or operations.

Refer toFIG. 1. The system architecture100may include a host110, a device130and a storage unit150. The system architecture may be practiced in a personal computer (PC), a laptop PC, a tablet computer, a mobile phone, a digital camera, a digital recorder, or other electronic consumer products. The device130may contain a processing unit133. The host110may communicate with the device130through a flash memory protocol, such as Universal Flash Storage (UFS). A flash memory controller133is electrically connected (coupled) to the host110through a data link (DL) layer132and a physical layer (PHY)131. The flash memory controller133may read user data of the storage unit150from a data buffer (no shown inFIG. 1) by a direct memory access (DMA) controller (no shown inFIG. 1) and serially clock the user data out to the host110through the DL layer132and the PHY131. The flash memory controller133may write user data to be programmed into the data buffer by a DMA controller (no shown inFIG. 1). The processing unit134may be implemented in numerous ways, such as with general-purpose hardware that is programmed when loading and executing relevant software or firmware instructions to perform the functions recited herein, such as a single-core processor, a multi-core processor with parallel computation capability, a Graphical Processing Unit (GPU), a lightweight general-purpose processor, or others. The flash memory controller133may be a UFS controller to communicate with the host110through UFS protocol. Although embodiments of the invention describe UFS as an exemplary communications protocol, those artisans may apply the invention to some other communications protocols, such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), etc.

The device130may further include a flash access interface (I/F)139to thereby enable the processing unit134to communication with the storage unit150, specifically, using a Double Data Rate (DDR) protocol, such as Open NAND Flash Interface (ONFI), DDR toggle, or others. The processing unit134writes user data into a designated address (a destination address) of the storage unit150and reads user data from a designated address (a source address) thereof through the flash access interface139. The flash access interface139may use several electronic signals including a data line, a clock signal line and control signal lines for coordinating command and data transfer between the processing unit134and the storage unit150. The data line may be used to transfer commands, addresses, read data and data to be programmed; and the control signal lines may be used to transfer control signals, such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), Write Enable (WE), etc.

The storage unit150may contain multiple storage sub-units and each storage sub-unit may use a respective access sub-interface to communicate with the processing unit134. One or more storage sub-units may be packaged in a single die. The flash access interface139may contain j access sub-interfaces and each access sub-interface may connect to i storage sub-units. Each access sub-interface and the connected storage sub-units behind may be referred to as a I/O channel collectively and each storage sub-unit may be identified by a Logical Unit Number (LUN). That is, i storage sub-units may share the same access sub-interface. For example, assume that the storage device130contains 4 I/O channels and each I/O channel connects to 4 storage sub-units: The storage device130may access 16 storage sub-units. The processing unit134may drive one of the access sub-interfaces to read data from the designated storage sub-unit. Each storage sub-unit has an independent CE control signal. That is, it is required to enable a corresponding CE control signal when attempting to perform data read or programming from or into a designated storage sub-unit via an associated access sub-interface. It is apparent that any number of I/O channels may be provided in the storage device130, and each I/O channel may include any number of storage sub-units, and the invention should not be limited thereto. Refer toFIG. 2. The processing unit134, through the access sub-interface139_0, may use independent CE control signals230_0to230_aAi to select one of the connected storage sub-units150_0to150_i, and then read data from or program data into the designated location of the selected storage sub-unit via the shared data line210.

Each storage sub-unit may include multiple data planes, each data plane may include multiple blocks and each block may include multiple pages. Refer toFIG. 3. Takes the storage sub-unit150_0as an example. The storage sub-unit150_0includes two data planes310and330. The data plane310includes blocks310_0to310_mand the data plane330includes blocks330_0to330_m. Each block includes n+1 pages. Each block may be configured as a single-level cell (SLC) block, a multi-level cell (MLC) block or a triple level cell (TLC) block. Each memory cell of the SLC, the MLC and the TLC blocks may store two, four and eight states, respectively. Each word line of the SLC block may store one page of data. Each word line of the MLC block may store two pages of data, including a most significant bit (MSB) page and a least significant bit (LSB) page. Each word line of the TLC block may store three pages of data, including a MSB page, a center significant bit (CSB) page and a LSB page.

Refer toFIG. 4. In the direct-write mode, a static random access memory (SRAM)136does not allocate cache for buffering a large number of host write commands with data to be programmed, but allocates limited space of a command queue and a data buffer410for storing several host write commands with data to be programmed. Different from the cache mode, the processing unit134under the direct-write mode completes a host write command after driving the flash access interface139to program data into the storage unit150according to the host write command. To deal with a variety of host write commands issued by the host110, the storage sub-unit150_0may allocate two blocks: a current block451; and a temporary block453. The current block451is configured as a MLC or TLC block and the temporary block453is configured as a SLC block. Assume that the minimum data unit managed by the host110is 4K bytes and a data length of each page (referred to as a page length) of the storage sub-unit150_0is 16K bytes: When a host write command instructs the device130to write data of one or more page lengths, the processing unit134drives the flash access I/F139to program the data into one or more empty pages of the current block451in the MLC or TLC mode. When a host write command instructs the device130to write data shorter than the page length, the processing unit134drives the flash access I/F139to program the data into one or more sectors of one empty page of the temporary block453in the SLC mode, where each sector stores data of 4K bytes. Once any page of the temporary block453is filled with data, the processing unit134may drive the flash access I/F139to program data of the whole page of the temporary block453into an empty page of the current block451in the MLC or TLC mode.

Since the current block451is an MLC or TLC block (that is, two or three pages of data are stored in the same word line), an occurrence of SPO during a data programming into the current block451may additionally damage page data that has been programmed into. For example, refer toFIG. 3. Suppose that the block310_0is an MLC block (as the current block), in which the page P #0 is an LSB page of a word line and the page P #3 is a MSB page of the same word line. The pages P #0 and P #3 may be referred to as a page pair. If a SPO happens during a data programming into the page P #3 of the block310_0, then it probably damages data of the page P #0 that has been programmed into. To prevent the problems as described above, refer toFIG. 4. The storage sub-unit150_0further allocate a backup block455configured as a SLC block. Before programming data into a MSB page (e.g. the page P #3) of the current block (e.g. the block310_0), the processing unit134drives the flash access I/F139to store (or backup) data of a LSB page corresponding to this MSB page of the current block in an empty page of the backup block455first, and then, program data into this MSB page of the current block.

Similarly, as to the current block being a TLC block, the processing unit134may drive the flash access I/F139to store (or backup) data of a CSB page corresponding to this MSB page of the current block in an empty page of the backup block455first, and then, program data into this MSB page of the current block. Or, the processing unit134may drive the flash access I/F139to store (or backup) data of an LSB page corresponding to this CSB page of the current block in an empty page of the backup block455first, and then, program data into this CSB page of the current block.

Those artisans may practice any of the current block451, the temporary block453and the backup block455in an arbitrary data plane (e.g. the data plane310or330as shown inFIG. 3).

To shorten the time for handling a SPOR, the processing unit134does not spend time as much as possible to reprogram data into the current block451, instead, reconstructs the current block451by obtaining corresponding data from the temporary block453and/or the backup block455. Embodiments of the invention describe ways of storing protection information in spare space of each page of the current block451, the temporary block453and the backup block455, which can be used in a possible SPOR. To maintain the order of storing page data of the current block451, the temporary block453and the backup block455in time, spare space of each page of the current block451may record address information pointing to the first empty page of the temporary block453(for example, storing the block number of the temporary block453and the page number of the first empty page thereof) at the time that the page data of the current block451was programmed, and spare space of each page of the temporary block453may record address information pointing to the first empty page of the current block451(for example, storing the block number of the current block451and the page number of the first empty page thereof) at the time that the page data of the temporary block453was programmed. Also, since data of the CSB page or the LSB page (referred to as a source page) of the current block451may be backed up in one page (referred to as a backup page) of the backup block455, therefore, spare space of one or more pages of the backup block455may record address information pointing to the first empty page of the current block451(for example, storing the block number of the current block451and the page number of the first empty page thereof), as well as address information pointing to the first empty page of the temporary block453(for example, storing the block number of the current block453and the page number of the first empty page thereof) at the time that the page data of the backup block455was programmed.

In some embodiments, spare space of each page of the current block451, the temporary block453and the backup block455has capacity for storing address information pointing to two or more pages. Refer toFIG. 5showing several use cases. Data of the N-th page of the current block451is backed up in the O-th page of the backup block455. The blocks in slashes as shown inFIG. 5represent empty pages. Spare space510of the N-th page of the current block451may store address information pointing to the (M+1)-th page of the temporary block453. Spare space530of the M-th page of the temporary block453may store address information pointing to the (N+1)-th page of the current block451. Spare space550aof the O-th page of the backup block455may store address information pointing to the (N+1)-th page of the current block451and spare space550bof the O-th page of the backup block455may store address information pointing to the (M+1)-th page of the temporary block453.

In alternative embodiments, spare space of each page of the current block451, the temporary block453and the backup block455has limited capacity for storing address information pointing to only one page. To completely record required protection information in spare space of the backup block455as described above, the processing unit134programs data into empty pages of the current blocks of the data plane310and the data plane330alternately and treats the two pages of the data plane310and the data plane330as a page group. For example, refer toFIG. 3. Assume that the block310_1is the current block of the data plane310and the block330_1is the current block of the data plane330: The processing unit134may program data into the page P #0 of the current block310_1, the page P #0 of the current block330_1, the page P #1 of the current block310_1and the page P #1 of the current block330_1in sequence, where the pages P #0 of the current blocks310_1and330_1form a page group and the pages P #1 of the current blocks310_1and330_1form another page group. Refer toFIG. 6showing several use cases. The current block451ais allocated on the data plane310and the current block451bis allocated on the data plane330. Data of the N-th page of the current block451ais backed up in the O-th page of the backup block455and data of the N-th page of the current block451bis backed up in the (O+1)-th page of the backup block455. The blocks in slashes as shown inFIG. 6represent empty pages. Spare space510aof the N-th page of the current block451amay store address information pointing to the M-th page of the temporary block453and spare space510bof the N-th page of the current block451bmay store nothing. Spare space530of the M-th page of the temporary block453may store address information pointing to the (N+1)-th page of the current block451. Spare space550aof the O-th page of the backup block455may store address information pointing to the (N+1)-th page of the current block451aand spare space550bof the (O+1)-th page of the current block455may store address information pointing to the M-th page of the temporary block453.

Refer toFIG. 7. The method as shown inFIG. 7may be performed by the processing unit134when loading and executing relevant firmware or software instructions. The processing unit134generates protection information of a temporary page, which includes address information at the time pointing to the first empty page of the current block, (step S730) after preparing data with a length (e.g. 4K, 8K or 12K) shorter than a page length that is to be programmed into an empty page (typically being the first empty page) of the temporary block according to a host write command of a command queue (step S710). For example, the processing unit134generates protection information that is to be programmed into the spare space530of the temporary block453as shown inFIG. 5or the spare space530aor530bof the temporary block453as shown inFIG. 6. Next, the processing unit134drives the flash access I/F139to program the data and the protection information into the first empty page of the temporary block (step S750).

Refer toFIG. 8. The method as shown inFIG. 8may be performed by the processing unit134when loading and executing relevant firmware or software instructions. The processing unit134prepares data of the whole page that is to be programmed into an empty page (typically being the first empty page) of the current block according to a host write command of a command queue (step S810). Those artisans will realize that the whole page of data may include data obtained from the temporary block, or exclude any therefrom. Next, the processing unit134determines whether the word line that the data is to be programmed into has another programmed page data (step S820), for example, if the word line has stored an LSB or CSB page data that was programmed for a previous host write command. If the determination is negative (the “No” path of step S820), for example, the page that the data is to be programmed into is an LSB page, or the programmed LSB or CSB page data of the word line is associated with the same host write command for the prepared data, the processing unit134generates protection information of the current page, including address information pointing to the first empty page of the temporary block (step S830). For example, the processing unit134generates protection information that is to be programmed into the spare space510of the current block451as shown inFIG. 5, or the spare space510aof the current block451aor the spare space510bof the current block451bas shown inFIG. 6. Next, the processing unit134drives the flash access I/F139to program the data and the protection information into the first empty page of the current block (step S840).

If the determination is positive (the “Yes” path of step S820), the processing unit134generates protection information of a backup page, including address information pointing to the first empty pages of the current block and the temporary block (step S850). For example, the processing unit134generates protection information that is to be programmed into the spare space550aand550bof the backup block455as shown inFIG. 5 or 6. The processing unit134drives the flash access I/F139to program the presented data and protection information of the word line into the first empty page of the backup block (step S860). Next, the processing unit134executes steps S830and S840as described above.

Since the SPO may damage page data that has been programmed or is being programmed, therefore, after a power restart subsequent to a SPO, the processing unit134may perform a SPOR process to mark correct data of the current block and the temporary block. Refer toFIG. 9. The method as shown inFIG. 9is performed by the processing unit134when loading and executing relevant firmware or software instructions. The processing unit134uses the variable i to record a page number that is currently scanned within the current block, initialized as 0 (step S910). Following that, the processing unit134repeatedly executes a loop (steps S920to S940) to find a page of the current block that is damaged resulting from the SPO. In each iteration, the processing unit134drives the flash access I/F139to read the i-th page of the current block (step S920) and performs two determinations (steps S930and S940). When the read page does not appear to be unrecoverable (the “No” path of step S930), or the read page cannot be recovered but has been backed up in the backup block (the “Yes” path of step S940following the “Yes” path of step S930), the processing unit134determines that data of the read page is correct, increases the variable i by one and proceeds to further determinations for the next page (step S935). When the read page appears to be unrecoverable (the “Yes” path of step S930) and does not backed up in the backup block (the “No” path of step S940), the processing unit134determines that data of the read page is incorrect and the loop ends. The read page appearing to be unrecoverable means that, although the processing unit134uses the error check and correction (ECC) code of the read page, error bits appeared in the read data cannot be fixed. The read page appearing to be unrecoverable is referred to as an uncorrectable ECC (UECC) page. After the loop ends, the processing unit134uses a variable v1=i−1 to record a specific number of the last correct page of the current block. In other words, the i-th page and the following pages of the current block have been damaged by the SPO. Those artisans may not implement the backup mechanism with the backup block, therefore, the determination of S940of the method described above may be omitted.

Next, the processing unit134uses the variable j to record a page number that is currently scanned within the temporary block, initialized as 0 (step S960). Following that, the processing unit134repeatedly executes a loop (steps S970to S980) to find correct pages of the temporary block. In each iteration, the processing unit134drives the flash access I/F139to read the protection information of the j-th page of the temporary block (step S970), and determines whether the protection information points to a page after the v1-th page of the current block (step S980). When the read protection information does not point to a page after the v1-th page of the current block, that is, points to the v1-th page of the current block or an earlier page (the “No” path of step S980), the processing unit134determines that the read page is correct, increases the variable j by one and proceeds to a further determination for next page (step S975). When the read protection information points to a page after the v1-th page of the current block (the “Yes” path of step S980), the processing unit134determines that the read page is incorrect and the loop ends. After the loop ends, the processing unit134uses the variable v2=j−1 to record a specific number of the last correct page of the temporary block. In other words, the j-th page (i.e. the first incorrect page) and the following pages of the temporary block have temporary data that cannot be used after the SPO.

In an aspect, embodiments of the invention introduce process steps performed by the processing unit134of the apparatus130when loading and executing relevant program code: driving the flash access I/F139to read pages of the current block451in sequence after a power restart subsequent to a SPO; marking the last correct page of the current block451according to page read statuses for the current block451; driving the flash access I/F139to read protection information of pages of the temporary block453in sequence, so as to mark the first incorrect page of the temporary block453whose protection information includes address information pointing to a page after the last correct page of the current block451; and dropping data of the first incorrect page and pages thereafter of the temporary block453. In a SPOR process, with droppings of all the pages that were stored later than that of the last correct page of the current block451with references made to the protection information of the temporary block453, it ensures the time order of recovered pages of the current block451and the temporary block453and avoids any unrecovered page is presented between recovered correct pages in time.

Refer to use cases as shown inFIG. 10. Assume that the current block451ais allocated on the data plane310, the current block451bis allocated on the data plane330, the (Q+1)-th page of the current block451ais also stored in the P-th page of the backup block455, the (Q+1)-th page of the current block451bis also stored in the (P+1)-th page of the backup block455, protection information1030of the R-th page of the temporary block453points to the (Q+3)-th page of the current blocks451aand451b, protection information1031of the (R+1)-th page of the temporary block453points to the (Q+4)-th page of the current blocks451aand451b: When detecting that the (Q+1)-th page of the current blocks451aand451bis an UECC page (the “Yes” path of step S930) and has been backed up in the temporary block455(the “Yes” path of step S940), the processing unit134replaces the data of the (Q+1)-th pages of the current blocks451aand451bwith the data of the P-th page and the (P+1)-th page of the temporary block455, respectively, and continues the next scanning. When detecting that the (Q+4)-th page of the current blocks451aand451bis an UECC page (the “Yes” path of step S930) and hasn't been backed up in the temporary block455(the “No” path of step S940), the processing unit134determines that the last correct pages of the current blocks451aand451bare the (Q+3)-th pages thereof (step S950).

Moreover, when detecting that protection information of the (R+1)-th page of the temporary block453points to a page after the last correct pages of the current blocks451aand451b(the “Yes” path of step S980), the processing unit134the last correct page of the temporary block453is the R-th page thereof (step S990).

Although data of the pages before the detected UECC page is all correct, the data retention of memory cells of physical wordlines and pages neighboring to the UECC page may be degraded, for example, available times that data thereon can be regularly read out are decreased, when an SPO occurs. Refer toFIG. 11showing a method that is performed by the processing unit134when loading and executing relevant firmware or software instructions. The processing unit134drives the flash access I/F139to duplicate data of the last correct page and its previous t−1 pages of the current block in empty pages of the temporary block (step S1110). t may be set to an arbitrary integer ranging from 2 to 5 depending on different system requirements. Next, the processing unit134may configure t pages after the UECC page of the current block as dummy pages (step S1130). In some embodiments, the processing unit134may drive the flash access I/F139to fill t pages after the detected UECC page of the current block with dummy values, for example, “0xFF”. Next, the processing unit134drives the flash access I/F139to program data stored in the temporary block into empty pages of a new current block, or empty pages after the last dummy page of this current block (step S1150).

Refer toFIG. 12following the use cases as shown inFIG. 10. Data and protection information1011ato1013bof the (Q+1)-th to the (Q+3)-th pages of the current blocks451aand451bare duplicated and programmed into the (Q+8)-th to the (Q+10)-th pages of the current blocks451aand451b(steps S1110and S1150). The (Q+5)-th to the (Q+7)-th pages of the current blocks451aand451bare configured as dummy pages (step S1130).

However, two or more SPOs may be occurred during data programming for the same current block, resulting in page data that has been moved to be mistakenly determined as correct page data. To address the aforementioned problems, a validity field is inserted into each record of a Flash-to-Host (F2H) table of the SRAM136, which is associated with the current block, to indicate whether data of a specific page of the current block is valid. Moreover, the method as shown inFIG. 11may be modified with that ofFIG. 13. After configuring dummy pages of the current block and migrating data of candidate pages to empty pages after the last dummy page of the current block successfully (steps S1300, S1130and S1310), the validity fields of the records of the F2H table, which are associated with the moved pages, the UECC page and the dummy pages of the current block, are set to invalid (step S1330). For example, with references made toFIG. 12, validity fields of the records of the F2H table, which are associated with the (Q+1)-th to the (Q+7)-th pages of the current blocks451aand451b, are set to invalid. Those artisans will realize that the host110may issue erase commands to the processing unit134to erase data of specific logical address(es). After address translations, the processing unit134knows which sector(s) of a specific page of the current block the logical address(es) maps to. When data of all sectors of a page of the current block is removed to respond to host erase command(s), the processing unit134may set the validity field of the record of the F2H table, which is associated with the removed page, to invalid.

Moreover, step S1110ofFIG. 11is modified with step S1300ofFIG. 13, in which the processing unit134examines the validities of the last correct page and its previous t−1 pages of the current block. If the last correct page and its previous t−1 pages of the current block are invalid pages, then the processing unit134does not perform the migration operations of steps S1310and S1330. In other words, the last correct page and its previous t−1 pages of the current block recited in step S1330are all valid.

Although the embodiments describe the quantities of the migrated pages and the dummy pages are the same, those artisans may set the quantity of the migrated pages to be different from the quantity of the dummy pages. For example, a total amount of the migrated pages is n2 and a total amount of the dummy pages is n1, where any of n1 and n2 is an arbitrary integer ranging from 2 to 5.

Process steps as shown inFIGS. 7-9, 11 and 13that are executed by the processing unit134may be practiced by computer program products composed of one or more function modules. The function modules are stored in nonvolatile storage device and can be loaded and executed by the processing unit134at relevant times. Some or all of the aforementioned embodiments of the method of the invention may be implemented in a computer program such as a driver or a firmware program for a dedicated hardware, or a software application program. Other types of programs may also be suitable, as previously explained. Since the implementation of the various embodiments of the present invention into a computer program can be achieved by the skilled person using his routine skills, such an implementation will not be discussed for reasons of brevity. The computer program implementing some or more embodiments of the method of the present invention may be stored on a suitable computer-readable data carrier such as a DVD, CD-ROM, USB stick, a hard disk, which may be located in a network server accessible via a network such as the Internet, or any other suitable carrier.

The computer program may be advantageously stored on computation equipment, such as a computer, a notebook computer, a tablet PC, a mobile phone, a digital camera, a consumer electronic equipment, or others, such that the user of the computation equipment benefits from the aforementioned embodiments of methods implemented by the computer program when running on the computation equipment. Such the computation equipment may be connected to peripheral devices for registering user actions such as a computer mouse, a keyboard, a touch-sensitive screen or pad and so on.

Although the embodiment has been described as having specific elements inFIGS. 1, 2 and 4, it should be noted that additional elements may be included to achieve better performance without departing from the spirit of the invention. Each element ofFIGS. 1, 2 and 4is composed of various circuits and arranged to operably perform the aforementioned operations. While the process flows described inFIGS. 7-9, 11 and 13include a number of operations that appear to occur in a specific order, it should be apparent that these processes can include more or fewer operations, which can be executed serially or in parallel (e.g., using parallel processors or a multi-threading environment).