Circuitry for implementing multi-mode redundancy and arithmetic functions

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

BACKGROUND

This invention relates to integrated circuits and, more particularly, to circuitry that implements multi-mode redundancy and arithmetic functions in integrated circuits.

Integrated circuits are subject to a phenomenon known as single event upset (SEU). A single event upset is a change of state caused by ions or electro-magnetic radiation. Cosmic rays or radioactive impurities embedded in integrated circuits and their packages may be responsible for generating such ions or electro-magnetic radiation. When ions or electro-magnetic radiation strike the silicon substrate on which the integrated circuit is implemented, the state of a node may change. For example, a single event upset may cause a logic “1” to change to a logic “0”.

Upset events in sequential elements (e.g., memory elements, latches, or registers) can have serious repercussions. Users who are concerned with detecting and correcting errors in a design or a portion of a design that is implemented in an integrated circuit often create multiple copies of that design or that portion of the design. A majority vote of the outputs produced by the different design copies may enable the detection of an upset event and indicate the location of the corrupted design copy. The technique of using multiple copies of a same design together with a majority vote is sometimes also referred to as multi-mode redundancy.

However, multi-mode redundancy requires multiple times the circuit area of a single design implementation plus the cost and delay associated with resources required for the implementation of the majority voting circuitry.

It would therefore be desirable to reduce the cost and delay associated with implementing multi-mode redundancy on an integrated circuit.

SUMMARY

In accordance with certain aspects of the invention, an integrated circuit such as a programmable integrated circuit may have first and second circuits. The second circuit may receive at least three signals from the first circuit, compute a sum of the at least three signals in an arithmetic mode, and produce a majority signal based on a majority vote function of the at least three signals in an error detect and correct mode.

The first circuit may include a plurality of sub-circuits. At least first and second sub-circuits may be duplicates of a third sub-circuit in the plurality of sub-circuits, and share at least one input.

It is appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or instructions executed on a programmable processor. Several inventive embodiments are described below.

In certain embodiments, the above-mentioned second circuit may further include an adder. The adder may receive first, second, and third signals of the at least three signals from the first circuit and compute a sum signal and a carry signal based on the received signals. In this embodiment, the computed carry signal may implement the majority vote function. A logic exclusive OR gate coupled to the adder may receive the carry signal and the sum signal and produce an error signal, wherein the error signal indicates the absence of an error when the at least three signals are identical.

If desired, the above-mentioned second circuit may further include an additional adder that is coupled between the first circuit and the adder. The additional adder may receive fourth and fifth signals of the at least three signals, while the adder receives the first signal from the additional adder and receives the second and third signals from the first circuit.

DETAILED DESCRIPTION

The present invention relates to integrated circuits such as programmable integrated circuits and more particularly to circuitry that implements multi-mode redundancy and arithmetic functions in integrated circuits.

As previously described, some users may create multiple copies of a same design and implement the multiple design copies in an integrated circuit together with a majority vote circuit. The combination of using multiple copies of the same design together with a majority vote circuit is sometimes also referred to as multi-mode redundancy.

However, multi-mode redundancy requires multiple times the circuit area of a single design implementation plus the cost and delay associated with resources required for the implementation of the majority voting circuitry.

It would therefore be desirable to provide a multi-mode redundancy implementation on an integrated circuit at a reduced cost. For example, portions of the majority voting circuit may be combined with existing arithmetic circuitry on the integrated circuit.

It will be recognized by one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

An illustrative embodiment of an integrated circuit such as a programmable logic device100in accordance with the present invention is shown inFIG. 1.

Programmable logic device100has input-output (I/O) circuitry110for driving signals off of device100and for receiving signals from other devices via input-output (I/O) pins120. Interconnection resources115such as global and local vertical and horizontal conductive lines and buses may be used to route signals on device100.

Input-output (I/O) circuitry110include conventional input-output (I/O) circuitry, serial data transceiver circuitry, differential receiver and transmitter circuitry, or other circuitry used to connect one integrated circuit to another integrated circuit.

Interconnection resources115include conductive lines and programmable connections between respective conductive lines and are therefore sometimes referred to as programmable interconnects115.

Programmable logic region140may include programmable components such as digital signal processing circuitry, storage circuitry, arithmetic circuitry such as adders arranged in carry chains, or other combinational and sequential logic circuitry such as configurable register circuitry. As an example, the configurable register circuitry may operate as a conventional register. Alternatively, the configurable register circuitry may operate as a random-access memory.

The programmable logic region140may be configured to perform a custom logic function. The programmable logic region140may also include specialized blocks that perform a given application and have limited configurability. For example, the programmable logic region140may include specialized blocks such as configurable storage blocks, configurable processing blocks, programmable phase-locked loop circuitry, programmable delay-locked loop circuitry, or other specialized blocks with limited configurability. The programmable interconnects115may also be considered to be a type of programmable logic region140.

Programmable logic device100contains programmable memory elements130. Memory elements130can be loaded with configuration data (also called programming data) using pins120and input-output (I/O) circuitry110. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated logic component in programmable logic region140. In a typical scenario, the outputs of the loaded memory elements130are applied to the gates of metal-oxide-semiconductor transistors in programmable logic region140to turn certain transistors on or off and thereby configure the logic in programmable logic region140and routing paths. Programmable logic circuit elements that may be controlled in this way include parts of multiplexers (e.g., multiplexers used for forming routing paths in programmable interconnects115), look-up tables, logic arrays, AND, OR, NAND, and NOR logic gates, pass gates, etc.

Memory elements130may use any suitable volatile and/or non-volatile memory structures such as random-access-memory (RAM) cells, fuses, antifuses, programmable read-only-memory memory cells, mask-programmed and laser-programmed structures, combinations of these structures, etc. Because memory elements130are loaded with configuration data during programming, memory elements130are sometimes referred to as configuration memory, configuration RAM, or programmable memory elements.

The circuitry of device100may be organized using any suitable architecture. As an example, the logic of programmable logic device100may be organized in a series of rows and columns of larger programmable logic regions each of which contains multiple smaller logic regions. The smaller regions may be, for example, regions of logic that are sometimes referred to as logic elements (LEs), each containing a look-up table, one or more registers, and programmable multiplexer circuitry. The smaller regions may also be, for example, regions of logic that are sometimes referred to as adaptive logic modules (ALMs), configurable logic blocks (CLBs), slice, half-slice, etc. Each adaptive logic module may include a pair of adders, a pair of associated registers and a look-up table or other block of shared combinational logic (i.e., resources from a pair of LEs—sometimes referred to as adaptive logic elements or ALEs in this context). The larger regions may be, for example, logic array blocks (LABs) or logic clusters of regions of logic containing for example multiple logic elements or multiple ALMs.

During device programming, configuration data is loaded into device100that configures the programmable logic regions140so that their logic resources perform desired logic functions. For example, the configuration data may configure a portion of the configurable register circuitry to operate as a conventional register. If desired, the configuration data may configure some of the configurable register circuitry to operate as a register with error detection and error correction capabilities.

FIG. 2shows an illustrative diagram of a logic region250. As shown inFIG. 2, logic region250may include logic elements260, adder circuitry265, register circuitry270, and configurable interconnect circuitry275. Logic elements260may include one or more configurable look-up tables. For example, logic elements may include four three-input look-up tables which may be configured to implement two independent four-input look-up tables, one five-input look-up table, or two five-input look-up tables which share at least two inputs, etc.

Adder circuitry265may include one or more adders. Each of these adders may implement a half-adder, a full-adder, a carry-save adder, a carry-select adder, a ripple-carry adder, a carry-lookahead adder, or any other suitable adder circuitry.

Register circuitry270may include registers, latches, time-borrowing flip-flops (TBFF), or any other synchronous circuitry that is controlled by a clock signal. If desired, register circuitry270may contain several different synchronous elements such as registers and latches, or registers and time-borrowing flip-flops, just to name a few combinations.

Internal interconnection resources280such as conductive lines and busses may be used to send data from one component to another component or to broadcast data from one component to one or more other components. External interconnection resources290such as conductive lines and busses may be used to communicate with external components. External interconnection resources290may convey data signals between logic region250and external components. If desired, external interconnection resources may also convey control signals such as clock signals, asynchronous reset signals, etc.

Configurable interconnect circuitry275couples logic elements260, adder circuitry265, and register circuitry270with each other through internal interconnection resources280and to external components through external interconnection resources290. Configurable interconnect circuitry275may include memory elements (e.g., memory elements130ofFIG. 1) which may be loaded with configuration data during device programming.

A single event upset (SEU) that causes a change of state in a programmable logic device such as programmable logic device100ofFIG. 1may not only modify the current signals stored in the programmable logic device, but also modify the behavior of the device (e.g., by flipping a bit of configuration data such as the configuration data stored in memory elements130ofFIG. 1).

As an example, consider that a look-up table (e.g., a look-up table in logic element260ofFIG. 2) implements a two-input logic NAND gate and that a single event upset (SEU) causes the memory element associated with inputs “00” to switch states from logic “1” to logic “0”. As a result, the look-up table may implement a two-input logic exclusive OR gate instead of the two-input logic NAND gate.

Multi-mode redundancy in which a combination of multiple copies of the same design is used together with a majority vote circuit may provide protection from single event upsets.FIG. 3shows a diagram of illustrative first and second circuits that implement triple-mode redundancy in accordance with an embodiment.

Circuit310may include three identical copies of a circuit (e.g., circuits330,340, and350). All three circuits may receive the same signals at the same inputs and produce independently of each other an output signal. The three output signals may be sent from circuit310to circuit320.

Circuit320may implement a majority function and an error function in a first mode. In a second mode, circuit320may implement an addition of the three input signals. As an example, circuit320may include adder circuit360and logic exclusive OR gate370. Adder circuit360may receive the three output signals from circuits330,340, and350and compute a sum and a carry of the three signals. As shown in TABLE 1 below, the carry of the three signals may also implement a majority signal produced by a majority function, which is logic “1” when the majority of the three signals is logic “1”. The majority function is sometimes also referred to as median operator.

Similarly, an error may be detected when at least one circuit of circuits330,340, and350produces a different output signal than the other two circuits. In other words, an error may be detected when not all circuits330,340, and350produce the same results. As shown in TABLE 1, performing a logic exclusive OR operation on the sum and the majority or carry (e.g., using logic exclusive OR gate370) may produce such an error signal.

As mentioned above, logic region250ofFIG. 2may be configured in various different ways. For example, circuits330,340, and350may be implemented in one or more logic regions250or in a portion of logic region250. An embodiment of a configuration of two logic regions is shown inFIG. 4. As shown, illustrative logic regions410and450may be coupled by a carry chain in which the outgoing carry connection447of logic region410may be coupled to the incoming carry connection482of logic region410. The two logic regions may be configured as two independent three-input adder circuits or as two triple-mode redundancy circuits in accordance with an embodiment.

If desired, some or all of look-up tables420,425,430, and435in logic region410may have any number of inputs. For example, look-up tables420,425,430, and435may all have less than four inputs (e.g., two inputs or three inputs) or more than four inputs (e.g., five, six, seven, eight, inputs, etc.). As another example, look-up tables420and425may have three inputs, look-up table430may have six inputs, and look-up table435may have two inputs.

As shown, adders440,445,480, and485may be single-bit adders with three inputs, a sum output, and a carry output. In other words, adders440,445,480, and485may receive one bit at a time at each of their three inputs. Adders440,445,480, and485may produce a ‘1’ at the sum output if an odd number of inputs are ‘1’. Adders440,445,480, and485may produce a ‘1’ at the carry output if two or more inputs are ‘1’. Adders440,445,480, and485may be coupled in a carry chain in which adders445,480, and485receive a carry signal or a majority vote signal directly from adders440,445, and480, respectively.

For example, adders440and445in logic region410may be configured as a three-input adder circuit. In this configuration, adder440may receive signal Y0 from look-up table425at both inputs and compute the carry signal for those two inputs, thereby essentially routing signal Y0 from look-up table425through the carry chain to adder445and thus preferably using a fast path through the existing carry chain. Alternatively, additional routing circuitry may be used to route signal Y0 from look-up table425to adder445.

Adder445may receive signal X1 from look-up table430, signal Y1 from look-up table435, and signal Y0 through the carry chain from adder440. Adder445may compute the sum of signals Y0, X1, and Y1 and provide the result at an output of logic region410. If desired, adder445may compute the carry signal resulting from the addition of Y0, X1, and Y1 and send the carry signal to adder480from which the carry signal may be routed from the sum output of adder480to an output of logic region450. Adder480may receive signal Y2 from look-up table465at both inputs and compute the carry signal for those two inputs, thereby essentially routing signal Y2 from look-up table465through the carry chain to adder485and thus preferably using a fast path through the existing carry chain. Alternatively, additional routing circuitry may be used to route signal Y2 from look-up table465to adder485.

Adder485may receive signal X3 from look-up table470, signal Y3 from look-up table475, and signal Y2 through the carry chain from adder480. Adder485may compute the sum of signals Y2, X3, and Y3 and provide the result at an output of logic region450. If desired, adder485may compute the carry signal resulting from the addition of Y2, X3, and Y3 and send the carry signal to another adder in a logic region below logic region450(not shown) from which the carry signal may be routed to an output of the logic region below logic region450.

In another example, adders440and445in logic region410and adders480and485in logic region450may be configured as two independent majority voting circuits in two triple-mode redundancy configurations. In this configuration, look-up tables425,430, and435may implement the same function and receive the same inputs, and look-up tables465,470, and475may implement the same function and receive the same inputs.

Adder440may receive signal Y0 from look-up table425at both inputs and compute the majority signal for those two inputs, thereby essentially routing signal Y0 from look-up table425through the carry chain to adder445. Adder445may receive signal X1 from look-up table430, signal Y1 from look-up table435, and signal Y0 through the carry chain from adder440. Adder445may compute the majority signal of Y0, X1, and Y1 and send the majority signal to adder480from which the majority signal may be routed to an output of logic region450.

Adder480may receive signal Y2 from look-up table465at both inputs and compute the majority signal for those two inputs, thereby essentially routing signal Y2 from look-up table465through the carry chain to adder485. Adder485may receive signal X3 from look-up table470, signal Y3 from look-up table475, and signal Y2 through the carry chain from adder480. Adder485may compute the majority signal of Y2, X3, and Y3 and send the majority signal to another adder in a logic region below logic region450(not shown) from which the majority signal may be routed to an output of the logic region below logic region450.

As shown inFIG. 4, look-up tables420and460of logic regions410and450, respectively, may implement portions of a user design that are unrelated to the triple-mode redundancy or the adder circuitry. If desired, look-up table420may be configured as a duplicate of look-up table425and a majority signal may be computed based on all look-up tables in logic region410and thus implement a quad-mode redundancy.

FIG. 5shows logic regions510and550that are coupled by a carry chain. As shown, logic region510may be configured as a four-input adder circuit or as a quad-mode redundancy circuit in accordance with an embodiment. In quad-mode redundancy, a majority may not be definite when half the signals are logic “1” and the other half is logic “0”, which is shown in TABLE 2.

As shown in TABLE 2, the majority signal may be equal to the carry signal whenever the majority signal is definite.

As shown, logic region510may include four-input look-up tables520,525,530, and535and adders540and545, and logic region550may include four-input look-up tables560,565,570, and575and adders580and585. Adders540,545,580, and585may be coupled in a carry chain in which adders545and530receive a carry signal or a majority vote signal from adders540and545, respectively.

For example, adders540and545in logic region510may be configured as a four-input adder circuit. A four-input adder adds two two-bit numbers (e.g., “X1 X0” and “Y1 Y0”) together and the result may be represented as a three-bit number. In this configuration, adder540may receive the two least significant bits X0 and Y0 of the two two-bit numbers from look-up tables520and525, respectively, and compute the sum and the carry signal for those two inputs. The sum of X0 and Y0 may be provided at an output of logic region510.

Adder545may receive the two most significant bits X1 and Y1 of the two two-bit numbers from look-up tables530and535, and the carry signal of the addition of X0 and Y0 through the carry chain from adder540. Adder545may compute the sum of signals X0, Y0, X1, and Y1 and provide the result at an output of logic region510. If desired, adder545may compute the carry signal resulting from the addition of X0, Y0, X1, and Y1 and send the carry signal to adder580from which the carry signal may be routed to an output of logic region550.

In another example, adders540and545in logic region510may be configured as majority voting circuits in quad-mode redundancy. In this configuration, look-up tables520,525,530, and535may implement the same function and receive the same inputs.

Adder540may receive signals X0 and Y0 from look-up tables520and525, respectively, and compute the carry signal for those two signals. Adder545may receive signal X1 from look-up table530, signal Y1 from look-up table535, and the carry signal of X0 and Y0 through the carry chain from adder540. Adder545may compute the majority signal of X0, Y0, X1, and Y1 and send the majority signal to adder580from which the majority signal may be routed to an output of logic region550.

The majority signal in this example and the carry signal from the previous example may use the same underlying circuitry, which may result in numerically identical numbers for the same inputs. Thus, the majority signal in this example inherently performs tie-breaking whenever the majority is indefinite as shown in TABLE 2.

If desired, logic region550may be configured to operate as a three-input adder, in triple-mode redundancy mode, or in any other mode that doesn't use the sum output of adder580. For example, four-input lock-up tables560,565,570, or575may implement any function of four inputs, and the outputs of look-up tables570and575may be added in adder585.

In the event that logic region510provides a path to route the carry signal of adder545to an output of logic region510without using adder580in logic region550, both logic regions (i.e., logic regions510and550) may be configured two independent four-input adder circuits or as two quad-mode redundancy circuits.

FIG. 6is a diagram of such logic regions, which may be configured as two independent adder circuits, one adder circuit, or as two quad-mode redundancy circuits in accordance with an embodiment.

As shown, logic region610may include four-input look-up tables620,625,630, and635and adders640and645, and logic region650may include four-input look-up tables660,665,670, and675and adders680and685. Adders640,645,680, and685may be coupled in a carry chain in which adders645,680, and685receive a carry signal or a majority vote signal from adders640,645, and680, respectively.

For example, consider that logic regions610and650are configured to implement two independent adders. In this example, the carry chain between adders645and680may be broken up. In other words, the carry input into logic region650may be set to ‘0’. For example, the carry input of logic region650may be coupled to select circuitry, which may select between the carry signal received over the carry chain from logic region610(i.e., the carry signal out of adder645) and a reset signal that sets the carry input signal into adder680to ‘0’.

Adders640and645may add two two-bit numbers (e.g., “X1 X0” and “Y1 Y0”) together and the result may be represented as a three-bit number. In this configuration, adder640may receive the two least significant bits X0 and Y0 of the two two-bit numbers from look-up tables620and625, respectively, and compute the sum and the carry signal for chose two input signals. The sum of X0 and Y0 may be provided at an output of logic region610.

Adder645may receive the two most significant bits X1 and Y1 of the two two-bit numbers from look-up tables630and635, and the carry signal of the addition of X0 and Y0 through the carry chain from adder640. Adder645may compute the sum of signals X0, Y0, X1, and Y1 and provide the result at an output of logic region610. If desired, adder645may compute the carry signal resulting from the addition of X0, Y0, X1, and Y1 and route the carry signal to an output of logic region610.

If desired, adders680and685in logic region650may be configured as an adder circuit that adds two-bit numbers “X3 X2” and “Y3 Y2” together and represents the result as a three-bit number. In this configuration, adder680may receive ‘0’ at the carry input and the two least significant bits X2 and Y2 of the two two-bit numbers from look-up tables660and665, respectively, and compute the sum and the carry signal for those signals. The sum of X2 and Y2 may be provided at an output of logic region650.

Adder635may receive the two most significant bits X3 and Y3 of the two two-bit numbers from look-up tables670and675, and the carry signal of the addition of X2 and Y2 through the carry chain from adder680. Adder685may compute the sum of signals X2, Y2, X3, and Y3 and provide the result at an output of logic region650. If desired, adder685may compute the carry signal resulting from the addition of X2, Y2, X3, and Y3 and route the carry signal to an output of logic region650.

Consider the scenario in which logic regions610and650are configured to implement an adder circuit that adds two four-bit numbers (e.g., “X3 X2 X1 X0” and “Y3 Y2 Y1 Y0”) together and in which the result may be represented as a five-bit number. In this scenario, adder640may receive the two least significant bits X0 and Y0 of the two four-bit numbers from look-up tables620and625, respectively, and compute the sum and the carry signal for those two input signals. The sum of X0 and Y0 may be provided as the first result bit at an output of logic region610.

Adder645may receive bits X1 and Y1 of the two four-bit numbers from look-up tables630and635and the carry signal of the addition of X0 and Y0 through the carry chain from adder640. Adder645may compute the second result bit based on signals X0, Y0, X1, and Y1 and provide the second result bit at an output of logic region610. Adder645may compute the carry signal resulting from the addition of X0, Y0, X1, and Y1 and route the carry signal to adder680in logic region650.

Adder680may receive bits X2 and Y2 of the two four-bit numbers from look-up tables660and665and the carry signal of the addition of X0, Y0, X1, and Y1 through the carry chain from adder645. Adder680may compute the third result bit based on signals X0, Y0, X1, Y1, X2, and Y2 and provide the third result bit at an output of logic region650. Adder680may compute the carry signal resulting from the addition of X0, Y0, X1, Y1, X2, and Y2 and route the carry signal to adder635.

Adder685may receive the two most significant bits X3 and Y3 of the two four-bit numbers from look-up tables670and675, and the carry signal of the addition of X0, Y0, X1, Y1, X2, and Y2 through the carry chain from adder680. Adder685may compute the fourth result bit based on signals X0, Y0, X1, Y1, X2, Y2, X3, and Y3 and provide the fourth result bit at an output of logic region650. If desired, adder685may compute the carry signal resulting from the addition of X0, Y0, X1, Y1, X2, Y2, X3, and Y3 as the fifth result bit and route the carry signal to an output of logic region650.

In another example, adders640and645in logic region610and adders680and685in logic region650may be configured as two independent majority voting circuits in two quad-mode redundancy configurations. In this configuration, look-up tables620,625,630, and635may implement the same first function and receive the same first set of input signals, and look-up tables660,665,670, and675may implement the same second function and receive the same second set of input signals.

Adder640may receive signals X0 and Y0 from look-up tables620and625, respectively, and compute the carry signal for those two signals. Adder645may receive signal X1 from look-up table630, signal Y1 from look-up table635, and the carry signal of X0 and Y0 through the carry chain from adder640. Adder645may compute the majority signal of X0, Y0, X1, and Y1, which may be routed to an output of logic region610.

Adder680may receive signals X2 and Y2 from look-up tables660and665, respectively, and compute the carry signal for those two signals. Adder685may receive signal X3 from lock-up table670, signal Y3 from look-up table675, and the carry signal of X2 and Y2 through the carry chain from adder680. Adder685may compute the majority signal of X2, Y2, X3, and Y3, which may be routed to an output of logic region650.

FIG. 7is a flow chart showing illustrative steps for implementing multi-mode redundancy on a programmable integrated circuit. During step710, a first logic element (e.g., look-up table425ofFIG. 4) may be configured to produce a first signal, and second and third logic elements (e.g., look-up tables430and435, respectively) may be configured as redundant logic elements of the first logic element. The second and third logic elements may produce second and third signals, respectively.

During step720, the first, second, and third logic elements may be coupled to first and second adders (e.g., adders440and445ofFIG. 4) that are arranged in a carry chain. During step730, first and second adders may compute a carry-out signal that is the result of a majority vote function and outputs logic one if the majority of the first, second and third signals is logic one. During step740, first and second adders may perform a logic exclusive OR operation of the first, second, and third signals to determine a sum signal.

Sum and carry-out signals may be used during step750to determine that one signal of the first, second, and third signals is different from the other two signals of the first, second, and third signals. For this purpose, a logic exclusive OR gate may perform a logic exclusive OR operation on the sum signal and the carry-out signal.

If desired, the carry-out signal and/or the sum signal may be routed to an output of a programmable logic region, respectively.

The method and apparatus described herein may be incorporated into any suitable electronic device or system of electronic devices. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessors or other ICs. Exemplary ICs include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), digital signal processors (DSPs), graphics processing units (GPUs), just to name a few.

The integrated circuit described herein may he part of a data processing system that includes one or more of the following components; a processor; memory; I/O circuitry; and peripheral devices. The integrated circuit can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using multi-mode redundancy is desirable.