Computer system, processor device, and method for controlling computer system

A computer system which significantly improves responsiveness to a sleep request includes: a processor device switching between an execution mode and a suspension mode; and an access controlling unit accessing a functional block in response to a command request received from the processor device, wherein, in response to a sleep request signal received from the external device, the processor device responds with a sleep response signal and asserts a suspension notification signal indicating a switch to the suspension mode, and the access controlling unit: masks an input of a further command request after receiving the command request from the processor device, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal; masks an input of a command request in the case where the processor device has not outputted the command request; and removes the mask when the suspension notification signal is negated.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to computer systems having a power reduction function, and more particularly to: a computer system including a processor device having an execution mode for receiving a supply of a clock signal and a suspension mode in which the supply of the clock signal is suspended by responding, with a sleep response signal, to a sleep request signal received from an external device; and a method for controlling the computer system.

(2) Description of the Related Art

In recent years, along with a rapid increase of the need for mobile communication appliances such as mobile phones, the need for Large-Scale Integrations (LSI) for the mobile communication appliances has also increased significantly. Further, as the mobile communication appliances become more highly-functioned, it is becoming popular for the LSI of the mobile communication appliances to have a processor capable of performing parallel processing or a multiprocessor having plural processors in a single LSI.

Patent Reference 1, Japanese Unexamined Patent Application Publication No. 11-305887, discloses a method for controlling a microcontroller which does not invalidate processing of a peripheral circuit when switching to a low-power consumption mode. With this controlling method, at first, it is judged whether or not the peripheral circuit is in operation. When it is judged that the peripheral circuit is not in operation, a clock signal for the Central Processing Unit (CPU) and a clock signal for the peripheral circuit are switched to the low-power consumption mode. On the other hand, when it is judged that the peripheral circuit is in operation, the clock signal for the peripheral circuit is switched to the low-power consumption mode after the operation of the peripheral circuit is completed. As a result, this method prevents the processing of the peripheral circuit from being invalidated.

In addition, Patent Reference 2, Japanese Patent No. 3000965, discloses a data processing apparatus which promptly switches from a stand-by mode to a normal operation mode. This data processing apparatus is incorporated in mobile phones and the like and provides a frequency dividing circuit with a frequency division control signal for setting an operating frequency of the clock signal in a halt mode. When a halt instruction is executed and the data processing apparatus switches to the halt mode, it switches the operating frequency of the clock signal, which is to be supplied to the peripheral processing unit, to a low frequency and supplies the clock signal having the switched operating frequency. As a result of this, the power used by the peripheral processing unit is reduced. Besides, when this data processing apparatus switches from the halt mode to the normal operation mode, the frequency of the peripheral processing unit is switched to the normal operation frequency, and therefore, the data processing apparatus can cause the mobile phone to promptly switch from a call stand-by mode to a calling mode.

However, the above described prior arts entail the following problems.

First, with Patent Reference 1, when the microcontroller is making access to a memory or the peripheral circuit, it is not possible to switch to the low-power consumption mode until the access is completed. Even with Patent Reference 2, it is also not possible to switch to the halt mode while the CPU is making access, because the halt instruction cannot be executed until the access is competed. Consequently, this causes a problem that the power consumption cannot be reduced until the access is completed. To put it differently, the time period of the low-power consumption mode or the halt mode is short, which results in a problem that the power consumption cannot be sufficiently reduced.

Second, with Patent Reference 2, a low-frequency clock signal is supplied to the peripheral processing unit in the halt mode, however, when the peripheral processing unit includes a timer or a counter, the time measurement cannot be performed accurately. As a consequence, there is a problem that when the data processing apparatus performs real-time processing, the timing to start the processing is delayed, and thus the processing performance cannot be guaranteed and the real-time processing cannot always be performed accurately.

SUMMARY OF THE INVENTION

In view of the above described problems, a first object of the present invention is to provide a computer system which significantly improves the responsiveness to a request from an external device for switching to the low-power consumption mode, thereby further reducing the power consumption.

Also, a second object of the present invention is to provide a computer system which does not cause performance degradation from switching to and from the low-power consumption mode.

In order to solve the above described problems, the computer system according to the present invention is a computer system comprising: a processor device having an execution mode and a suspension mode, the execution mode being a mode for executing a program, and the suspension mode being a mode for suspending the program execution by responding, with a sleep response signal, to a sleep request signal received from an external device; and an access controlling unit which accesses a functional block in response to a command request issued by the processor device, and asserts, to the processor device, a command reception signal responding to the command request, wherein, in response to the sleep request signal, the processor device responds to the external device with the sleep response signal, and asserts, to the access controlling unit, a suspension notification signal indicating a switch to the suspension mode, and when the suspension notification signal is received, the access controlling unit is which withholds asserting the command reception signal to the processor device as a response to the command request. With this structure, it is possible to achieve the first object. In other words, even when the processor device is waiting to receive a command reception signal at the time of receiving a sleep request signal, that is, even when the access control unit is currently making access at the time of receiving a sleep request signal, the processor device can immediately respond to the sleep request with a sleep response signal, and therefore, it is possible to significantly improve the responsiveness to the sleep request, and to further reduce the power consumption.

Here, it may be that the access controlling unit includes a masking unit which masks an input of a command request, and through which the access controlling unit: masks, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal, an input of a further command request after receiving the command request from the processor device; masks an input of a command request in the case where the processor device has not outputted the command request when the access controlling unit receives the suspension notification signal; and removes the mask when the suspension notification signal is negated. With this structure, receiving the suspension notification makes it possible for the access controlling unit to recognize that the processor device has entered the suspension mode, and further, masking the input of further command requests makes it possible for the access controlling unit to prevent acceptance of duplicated command requests by error. The access itself is executed by the access controlling unit, rather than by the processor device.

Here, it may be that supply of a clock signal to the processor device is suspended in the suspension mode.

Here, it may be that the access controlling unit asserts a suspension notification reception signal to the processor device in response to the suspension notification signal from the processor device, and in the case where the processor device has received the sleep request signal and is waiting to receive the command reception signal from the access controlling unit, the processor device responds with the sleep response signal after receiving the suspension notification reception signal from the access controlling unit as a response to the suspension notification signal. The assertion of the suspension notification reception signal may be delayed, only in the case where memory access of the processor device cannot be accepted since a memory accessing unit which accesses the memory is busy, for example.

Here, it may be that the computer system comprises: a host Central Processing Unit (CPU) which asserts the sleep request signal to the processor device, and receives the sleep response signal from the processor device; and a clock supplying unit which supplies a clock signal to the processor device, wherein, when the sleep response signal is received, the host CPU controls the clock supplying unit so that the clock supplying unit suspends the supply of the clock signal. With this structure, the processor device can immediately respond to the sleep request received from the host CPU, and thus it is possible to further reduce the power consumption.

Here, it may be that: the host CPU controls the clock supplying unit so that the clock supplying unit resumes the supply of the clock signal; and the host CPU negates the sleep request signal. With this structure, the host CPU can cause the processor device to switch back to the operation mode from the suspension mode with simple control.

Here, it may be that the access controlling unit includes: a command executing unit which receives the command request from the processor device and from at least an other processor device, and to execute access in response to the received command request; a shared buffer which holds read data accessed in response to the command request; and a judging unit which judges whether or not available capacity of the shared buffer is equal to or greater than a threshold, and defers the assertion of the suspension notification reception signal to the processor device in the case of judging that the available capacity is equal to or less than the threshold when the suspension notification signal is received. With this structure, in addition to the processor device, the computer system can include one or more processors accessing the memory, which improves the expandability of the computer system. In this case, the memory accessing unit executes the memory access for the processor device and of the one or more processors. The memory accessing unit may delay the assertion of the suspension notification reception signal, only in the case where command requests from the processor device cannot be accepted due to conflicts between plural command requests. Also, by using the buffer as a shared buffer instead of using it as a dedicated buffer of the processor device, it is possible to suppress expansion of the circuit size.

Here, it may be that in the case where the sleep request signal is negated and the processor device is waiting to receive the command reception signal, the processor device receives the command reception signal from the access controlling unit. With this structure, the processor device receives the command reception signal when the sleep request signal is negated, and thus the processor device can complete the processing associated with the command request issued prior to switching to the suspension mode.

Here, it may be that the computer system is a computer system comprising: a processor device having an execution mode and a first suspension mode, the execution mode being a mode for receiving supply of a first clock signal, and the first suspension mode being a mode in which the supply of the first clock signal is suspended by responding, with a sleep response signal, to a sleep request signal; a first clock supplying unit which supplies the first clock signal to the processor device; a host Central Processing Unit (CPU) which asserts the sleep request signal to the processor device, and causes the first clock supplying unit to suspend the supply of the first clock signal to the processor device when the sleep response signal is received as a response to the sleep request signal; and an access controlling unit which accesses a functional block in response to a command request issued by the processor device, and asserts, to the processor device, a command reception signal after the access is completed, wherein the processor device: asserts the sleep response signal in the case of receiving the sleep request signal and not waiting to receive the command reception signal from the access controlling unit; and responds to the sleep request with the sleep response signal and asserts, to the access controlling unit, a suspension notification signal indicating a switch to the first suspension mode, in the case of receiving the sleep request signal and waiting to receive the command reception signal from the access controlling unit, the processor device includes: a processor unit having the execution mode and a second suspension mode, the execution mode being a mode for executing programs by time division multiplexing and a mode in which the first clock signal is supplied, and the second suspension mode being a mode in which the supply of the first clock signal is suspended; a counting unit which counts a time period allocated to a currently executed program; a controlling unit which controls switching of the processor unit between the execution mode and the second suspension mode; and a second clock supplying unit which receives the first clock signal from the first clock supplying unit, and supplies the first clock signal and a second clock signal having a cycle K times as long as a cycle of the first clock signal, the controlling unit controls the second clock supplying unit so that the processor unit is switched to the second suspension mode when a remaining time of the counting unit is other than 0 and the currently executed program has completed necessary processing within the allocated time period, the second clock supplying unit, in the second suspension mode, suspends the supply of the first clock signal to the processor unit and supplies the second clock signal to the counting unit and the controlling unit, and the counting unit counts one by one in the execution mode, and K by K in the second suspension mode. With this structure, it is possible to achieve the second object in addition to the first object. The counting unit counts one by one in the operation mode, and counts K by K in the second suspension mode with the second clock signal which is K times as slow as the first clock signal. Consequently, the time counted in the second suspension mode approximately matches the time counted in the operation mode. As a result, when the real-time processing is performed in accordance with the time counted, it is possible to ensure the necessary performance without causing the performance degradation from switching to and from the low-power consumption mode.

Furthermore, the processor device according to the present invention may be a processor device comprising, a processor unit having an execution mode and a suspension mode, the execution mode being a mode for executing programs by time division multiplexing and a mode in which a first clock signal is supplied, and the suspension mode being a mode in which the supply of the first clock signal is suspended; a counting unit which counts a time period allocated to a currently executed program; a controlling unit which controls switching of the processor unit between the execution mode and the suspension mode; and a clock supplying unit which supplies the first clock signal and a second clock signal having a cycle K times as long as a cycle of the first clock signal, wherein the controlling unit controls the clock supplying unit so that the processor unit is switched to the suspension mode when a remaining time of the counting unit is other than 0 and the currently executed program has completed necessary processing within the allocated time period, the clock supplying unit, in the suspension mode, suspends the supply of the first clock signal to the processor unit and supplies the second clock signal to the counting unit and the controlling unit, and the counting unit counts one by one in the execution mode, and K by K in the suspension mode. With this structure, it is possible to achieve the second object. The counting unit counts one by one in the operation mode, and counts K by K in the second suspension mode using the second clock signal which is K times as slow as the first clock signal. Consequently, the time counted in the second suspension mode approximately matches the time counted in the operation mode. As a result, when the real-time processing is performed in accordance with the time counted, it is possible to ensure the necessary performance without causing the performance degradation from switching to and from the low-power consumption mode.

Here, it may be that the controlling unit switches the second clock signal to the first clock signal when a count value of the counting unit becomes less than K in the suspension mode, the second clock signal being supplied from the clock supplying unit to the counting unit, and the counting unit, when the count value becomes less than K, changes a subtraction number from K to 1 so as to subtract the count value one by one in the suspension mode. Consequently, the time counted in the second suspension mode approximately matches the time counted in the operation mode. As a result, this provides an adequate condition for performing real-time processing having stricter time restrictions.

Here, it may be that K is a power of 2. With this structure, it is possible to simplify the structure of the counting unit.

Here, it may be that the controlling unit includes a control register which can be set by the processor unit, and while the control register holds a predetermined flag value, the controlling unit does not switch from the second clock signal to the first clock signal and the counting unit does not change the subtraction number from K to 1 when the count value of the counting unit becomes less than K in the suspension mode. With this structure, it is possible to select whether to count one by one or to count K by K when the count value of the counting unit becomes less than K in the suspension mode, based on the flag value of the control register. As a result, depending on the processing performance requested by the program to be executed (whether or not the time restriction on the real-time performance is strict), it is possible to flexibly select the counting accuracy of the counting unit.

Here, it may be that the controlling unit, in the suspension mode: temporarily switches the second clock signal to the first clock signal and causes the clock supplying unit to temporarily supply the first clock signal to the processor unit, the second clock signal being supplied from the clock supplying unit to the counting unit; instructs the processor unit to execute context transfer; and switches, when the context transfer is completed, the first clock signal back to the second clock signal and causes the clock supplying unit to suspend the supply of the first clock signal to the processor unit, the first clock signal being supplied from the clock supplying unit to the counting unit. With this structure, it is possible to ensure the necessary performance without delaying the start timing of the program to be switched to, since the context transfer is performed at high speed in the suspension mode using the first clock signal.

Furthermore, the system LSI, the mobile phone, and the method for controlling the computer system according to the present invention are structured in a manner similar to the structure described above.

According to the present invention, firstly, it is possible to significantly improve the responsiveness to a request received from an external device for switching to the low-power consumption mode, and thus the power consumption can be further reduced. Also, the expandability of the computer system can be improved, and it is possible to suppress expansion of the circuit size.

Secondly, it is possible to prevent performance degradation caused by switching to and from the low-power consumption mode.

It is possible to approximately match the time counted in the suspension mode and the time counted in the operation mode.

It is also possible to completely match the time counted in the suspension mode and the time counted in the operation mode.

When the real-time processing is performed, it is possible to ensure the necessary performance without causing the performance degradation from switching to and from the low-power consumption mode.

This provides an adequate condition for performing real-time processing having stricter time restrictions.

Depending on the processing performance requested by the program to be executed (whether or not the time restriction on the real-time performance is strict), it is possible to flexibly select the counting accuracy of the counting unit.

The disclosure of Japanese Patent Application No. 2007-172886 filed on Jun. 29, 2007 including specification, drawings and claims is incorporated herein by reference in its entirety.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Hereinafter, with reference to the drawings, embodiments of the present invention shall be described in detail.

First Embodiment

A computer system according to a first embodiment is a system for performing computation, and mainly includes a processor device and an access controlling unit. The access controlling unit receives a command request issued by the processor device, and accesses functional blocks such as a memory and an input/output (I/O) device in response to the received command request. Further, the access controlling unit employs a split method in which the bus is temporarily released between the reception of the command request and the transmission and reception of data.

The processor device has an execution mode for receiving a supply of a clock signal and a first suspension mode in which the supply of the clock signal is suspended by responding, with a sleep response signal, to a sleep request signal received from an external device.

For a switch from the execution mode to the first suspension mode, the processor device, having received a sleep request signal from an external device, responds with a sleep response signal and outputs a suspension notification signal indicating a switch to the first suspension mode, even when it is in access to the access controlling unit.

In the case where the processor device had outputted a command request by the time when the access controlling unit receives the suspension notification signal, the access controlling unit masks the input of further command requests after receiving the outputted command request. In the case where the processor device had not outputted a command request, the access controlling unit masks the input of command requests. After that, when the suspension notification signal is negated, the access controlling unit removes the mask. Masking the input of command requests is to prevent reception of duplicated command requests by error.

As described above, the processor device can significantly improve the responsiveness to a sleep request signal because it immediately responds with a sleep response signal even while accessing the access controlling unit, and therefore, further reduction of the power consumption is possible. By receiving the suspension notification, the access controlling unit can recognize that the processor device has entered the first suspension mode, and thus the access is executed by the access controlling unit rather than the processor device. The suspension notification signal is transmitted in order to prevent the access controlling unit from outputting a signal requiring a handshake and the like to the processor device while the processor device is in the suspension mode.

FIG. 1is a functional block diagram illustrating an entire structure of the computer system according to the first embodiment of the present invention. As shown in the figure, a computer system1includes: a processor device100; a host CPU200; a bus controller300functioning as the access controlling unit; an interrupt controller400; a clock controller500functioning as a first clock supplying unit; and others such as processors100aand100b.

The processor device100has a first suspension mode and a second suspension mode as power-saving modes. The first suspension mode is also simply called a sleep mode. In the first suspension mode, the supply of a clock signal clk42is suspended by responding, with a sleep response signal12, to a sleep request signal11received from an external device. That is, the operation of the entire processor device100is suspended. Here, the sleep response signal12is used as a sleep acknowledge signal for acknowledging a sleep request. The second suspension mode is also called a microsleep mode. In the second suspension mode, the processor device100suspends the operations of a processor unit110and of a memory controller120. However, in the microsleep mode, the clock signal continues to be supplied to a Virtual Multi Processor (VMP) controller140so as to switch a program at every allocated time. The microsleep mode shall be described in detail in a second embodiment, and therefore shall not be described in the first embodiment.

The host CPU200outputs the sleep request signal11to the processor device100, and when the sleep response signal12is received as a response to the sleep request signal11, it suspends the supply of the first clock signal from the clock controller500to the processor device.

The bus controller300performs the following: receives a command request issued by the processor device100and the processors100aand100b; accesses the memory in response to the received command request; transmits a write data reception signal to the processor device100in the case of write accessing; and transmits read data and a read data valid signal to the processor device100in the case of read accessing. Note that the memory access includes, not only the memory reading and memory writing performed via a memory I/F1001, but also the I/O reading and I/O writing performed via an I/O controlling unit1002. Further, the target to be accessed is called a functional block. The memory I/F1001is connected to such a high-capacity memory as a Synchronous Dynamic Random Access Memory (SDRAM) as the functional block. The I/O controlling unit1002is connected to a Secure Digital (SD) memory card, an inputting apparatus, an outputting apparatus, and so on as functional blocks. Further, memory access is synonymous with bus access. The bus controller300, having received a suspension notification signal21from the processor device100, outputs a suspension notification reception signal22to the processor device100in the case where the bus controller300can accept suspension notification signal21. Whether or not the bus controller300can accept suspension notification signal21depends on whether or not a shared buffer305has an available capacity value equal to or greater than a threshold. The threshold may be the size of read data requested by the command request, or a predetermined value, for example.

The interrupt controller400notifies the processor device100of an interrupt from the host CPU200or an external I/O, as an interrupt signal31.

The clock controller500supplies or suspends supplying the clock signal clk42to a local clock controller130, under the control of the host CPU200.

The processor device100includes the processor unit110, the memory controller120, the local clock controller130, and the VMP controller140.

The processor unit110performs parallel processing by way of time division multiplexing, under the control of the VMP controller140.

The memory controller120issues a command request signal23to the bus controller300in response to the memory access signal from the processor unit110. When the access is completed, the memory controller120notifies the processor unit110of the access completion.

The following shall describe schematic procedures for switching the processor device100to the sleep mode. Firstly, the host CPU200asserts the sleep request signal11to the processor device100. When the sleep request signal11is asserted, the processor device100starts processing for suspending the execution of a program in the processor device100. Further, it is checked whether or not the processor device100is making outgoing access, that is, memory access to the bus controller300. In the case where the processor device100is making memory access, the processor device100outputs a suspension notification signal21to the bus controller300, and then asserts the sleep response signal12to the host CPU200. After the sleep response signal12is asserted, the host CPU200suspends the supply of the clock signal clk42to the processor device100via the clock controller500.

The VMP controller140includes a counter141and an interrupt detector142.

The VMP controller140is a context switching apparatus for switching contexts for the processor unit110to perform parallel processing by way of time division multiplexing. Here, contexts refer to information necessary for switching programs. More specifically, contexts refer to control information of a program counter, a flag register, a stack area, and the like, and to data information of a general-purpose register, and the like. The switching of the contexts refers to the operations of writing the contexts of the currently executed program to the memory (called “saving”) and reading the contexts of the next program to be executed from the memory (called “restoring”). The VMP controller140has a function to schedule the saving processing and the restoring processing, and the program to be executed, as the context switching apparatus.

The counter141counts the time allocated to each program for time division multiplexing.

The interrupt detector142receives an interrupt signal31from the interrupt controller400so as to detect an interrupt. This interrupt serves as a trigger to stop the microsleep mode.

FIG. 2is a timing chart illustrating the switching of the processor device100between the execution mode and the sleep mode. Further,FIG. 15is a diagram illustrating the mode switching of the processor device100.

At first, the following shall describe operations when the processor device100switches from a program execution mode600to a sleep mode601.

InFIG. 2, the host CPU200asserts the sleep request signal11to the processor device100which is in the program execution mode600, in order to suspend the program execution (timing T0). When the sleep request signal11is asserted, the processor device100performs processing to switch to the mode for suspending the program execution (the sleep mode601). Then, the processor device100asserts the sleep response signal12(timing T3) so as to switch to the sleep mode601.

In doing so, the processor device100asserts the suspension notification signal21to be outputted to the bus controller300(timing T1).

In the case where the suspension notification signal21is asserted during memory access, the bus controller300temporarily suspends the input and output of signals to and from the processor device100and the memory I/F1001and the I/O controlling unit1002, and asserts the suspension notification reception signal22(timing T2). At this point in time, in the case where the access data for the memory I/F1001or the I/O controlling unit1002needs to be held by the bus controller300, it is stored in the shared buffer305provided in the bus controller300. When the suspension notification reception signal22is asserted, the processor device100asserts the sleep response signal12to be outputted to the host CPU200(timing T3), so as to switch to the sleep mode601.

When the sleep response signal12is asserted, the host CPU200asserts a clock control signal41to the clock controller500(timing T4). When the clock control signal41is asserted, the clock controller500suspends the clock of the clock signal clk42supplied to the processor device100.

As described above, the present invention has a feature of suspending the supply of the clock signal to the processor device100, without waiting for the completion of the memory access.

Next, the following shall describe the operations when the processor device100switches back to the program execution mode600from the sleep mode601.

First, the host CPU200negates the clock control signal41(timing T5). At this timing, the clock controller500supplies the clock signal clk42to the processor device100. After that, the host CPU200negates the sleep request signal11outputted to the processor device100(timing T6). When the sleep request signal11is negated, the processor device100performs processing to switch to the program execution mode600from the sleep mode601. Here, in the case where the processor device100has not been asserting the suspension notification signal21, it negates the sleep response signal12(timing T7) after the completion of this processing, so as to switch to the program execution mode600.

On the other hand, in the case where the processor device100has been asserting the suspension notification signal21, it negates the suspension notification signal21outputted to the bus controller300(timing T8).

When the suspension notification signal21is negated, the bus controller300resumes the temporarily suspended input and output of signals to and from the processor device100and the memory I/F1001and the I/O controlling unit1002. Then, after the memory access for the processor device100is completed, the bus controller300negates the suspension notification reception signal22(timing T9) so as to switch to the program execution mode600.

FIG. 3is a schematic flow chart illustrating processing for causing the processor device100to switch from the program execution mode600to the sleep mode601and for suspending the clock signal clk42.

In the figure, when the processor device100receives the sleep request signal11from the host CPU200(S11), it judges whether or not bus access is currently in progress (S12). In the case of judging that bus access is currently in progress, the processor device100performs the following: asserts the suspension notification signal21to the bus controller300(S13); receives the suspension notification reception signal22asserted by the bus controller300(S14); and then makes a response to the host CPU200by asserting the sleep response signal12(S15). On the other hand, in the case of judging that bus access is not currently in progress, the processor device100immediately makes a response to the host CPU200by asserting the sleep response signal12(S15). Having received the sleep response signal12, the host CPU200controls the clock controller500so as to suspend the supply of the clock signal clk42(S16).

FIG. 4is a schematic flow chart illustrating processing for causing the processor device100to switch back to the program execution mode600from the sleep mode601.

In the figure, in order to stop the sleep mode of the processor device100, the host CPU200at first controls the clock controller500to resume the supply of the clock signal clk42(S21) and negates the sleep request signal11(S22). When the sleep request signal11is negated, the processor device100performs processing to switch to the program execution mode600from the sleep mode601(S23). Here, in the case where the processor device100has been asserting the suspension notification signal21, it negates the suspension notification signal21outputted to the bus controller300(S25).

FIG. 5is a block diagram illustrating a detailed structure of the bus controller300. As shown in the figure, the bus controller300includes the shared buffer305, a shared buffer judging unit306, and a command executing unit310. The command executing unit310includes command controlling units301and301a, a command arbitrating unit302, a write data controlling unit303, and a read data controlling unit304.

The shared buffer305temporarily holds read data accessed in response to a command request issued by the processor device100, the processor100a, and the processors100b. The shared buffer305is shared by processors connected to the bus controller300, such as the processor device100, and the processors100aand100b. The shared use of the shared buffer305allows reduction of the footprint of the bus controller300.

The shared buffer judging unit306judges whether or not the available capacity of the shared buffer is equal to or greater than a threshold. The threshold may be the size of read data requested by the most recent command request, or a predetermined value. When the suspension notification signal21is received, the shared buffer judging unit306immediately transmits the suspension notification reception signal22to the processor device100in the case where the available capacity is equal to or greater than the threshold. On the other hand, in the case where the available capacity is not equal to or greater than the threshold, the shared buffer judging unit306defers the transmission of the suspension notification reception signal22to the processor device100. Here, the bus controller300may include a buffer dedicated for the processor device100instead of the shared buffer305, and transmit the suspension notification reception signal22without the above described judgment.

The command executing unit310executes memory access in response to a command request from the processor device100, for example.

The command controlling unit310holds the command request issued by the processor device100. To be more specific, in the case where the processor device100is asserting a command request signal23when the command controlling unit301receives the suspension notification signal21, the command controlling unit301, after receiving (holding internally) the command request signal23, masks the input of further command request signals23. On the other hand, in the case where the processor device100is not asserting a command request signal23when the command controlling unit301receives the suspension notification signal21, the command controlling unit301masks the input of command request signals23. Subsequently, the command controlling unit301removes the mask after the suspension notification signal21is negated. A command controlling unit310ais the same as the command controlling unit310except that the command controlling unit310aholds command requests issued by the processor100a. The number of these command controlling units provided is the same as the number of the processors connected to the bus controller300.

The command arbitrating unit302arbitrates conflicts of command requests issued by the plural command controlling units, and selects a single command request as a result of the arbitration. The selected command request is outputted as an access control signal to the memory via the memory I/F1001or to the I/O via the I/O controlling unit1002.

In the case where the command request selected by the command arbitrating unit302is a request for write access, the write data controlling unit303selects write data which has been outputted by the processor device100, the processor100a, or the like and which corresponds to the selected command request.

The read data controlling unit304selects the data read from the memory via the memory I/F1001or from the I/O via the I/O controlling unit1002, and stores it in the shared buffer305.

FIG. 6is a flow chart illustrating in detail processing for causing the processor device100to switch from the program execution mode600to the sleep mode601and to further switch back to the program execution mode600. The first column from the left of the figure illustrates a flow of the processing performed by the host CPU200and the processor device100. The second column from the left illustrates a flow of command request control, performed by the bus controller300, common to read accesses and write accesses. The third column from the left illustrates a flow of read access control performed by the bus controller300. The fourth column from the left illustrates a flow of write access control performed by the bus controller300. The black circle in the figure denotes the start of the processing. The black circles surrounded by another circle denote the end of the processing. The thick bar with two inputs and one output (S113, for example) denotes that two signals or conditions become ready. The thick bars with one input and two outputs (S127, for example) denote that a single signal or condition is divided into two. The rhombuses with two inputs and one output (S105, for example) denote a passing point for one of the inputs. The rhombuses with one input and two outputs (S124, for example) denote a judgment. The functional block mentioned in the figure is either the memory I/F1001or the I/O controlling unit1002.

Description of the flow of the processing performed by the host CPU200and the processor device100illustrated in the first column from the left of the figure is omitted as it is almost the same as the flows of the processing illustrated inFIG. 3andFIG. 4. Here, the description shall center on the flow of the control performed by the bus controller300illustrated in the second through fourth columns from the left of the figure.

When the processor device100receives the sleep request signal11from the host CPU200during bus access, it asserts the suspension notification signal21(S103). When the suspension notification signal21is asserted, the bus controller300judges whether or not a command request signal23has been received from the processor device100(whether or not a command request signal23is held by the command controlling unit301) (S121). In the case of judging that the command request signal23has been received, the bus controller300masks the input of further command request signals23, and proceeds to S123. On the other hand, in the case of judging that the command request signal23has not been received at the time when the command request signal23is asserted, the bus controller300receives it (S122), then masks the input of command request signals23, before further proceeding to S123. Following Step S123, the command controlling unit301judges whether the received command request is a request for read access or write access (S124).

In the case of judging the received command request as a request for read access, the shared buffer judging unit306judges whether or not the shared buffer305has available capacity larger than the threshold (S125), and asserts the suspension notification reception signal22in the case of judging that the shared buffer305has available capacity larger than the threshold (S126). The asserted suspension notification reception signal22is notified to the processor device100(S127→S128→S105) as well as to the command controlling unit301(S127). While asserting the suspension notification reception signal22, the command executing unit310prohibits outputting of a signal responding to the command request signal23(that is, a command reception signal24, a write data reception signal26, and a read data valid signal27) to the processor device100. This is because the processor device100cannot recognize such signals while it is in the sleep mode.

The read command request held by the command controlling unit301is further outputted to the memory or the I/O by the command arbitrating unit302via the memory I/F1001or the I/O controlling unit1002as an access control signal (S129). Then, the output of read data from the memory or the I/O is waited for (S130).

In addition, when the read data is outputted from the memory or the I/O, the read data is stored in the shared buffer305via one of the memory I/F1001and the I/O controlling unit1002, and further via the read data controlling unit304. Then, the memory I/F1001or the I/O controlling unit1002is released (S131).

In the case of judging the received command request as a request for write access in S124, the shared buffer judging unit306asserts the suspension notification reception signal22(S133→S128→S105). The write command request held by the command controlling unit301is further outputted to the command arbitrating unit302. The command arbitrating unit302judges whether or not the processor device100has already outputted write data to the memory I/F1001or the I/O controlling unit1002(S135). Then, in the case of judging that the write data has already been outputted, the memory I/F1001or the I/O controlling unit1002writes the write data to the memory or the I/O unit (S136→S137). On the other hand, in the case of judging that the write data has not yet been outputted, the write access is not executed (S135→S137).

Further, the following shall describe the case where the processor device100switches from the sleep mode to the execution mode and negates the suspension notification signal21.

When the processor device100negates the suspension notification signal21, the command controlling unit301or301aoutputs a command reception signal24(S113→S141→S142). In the case of read access, the bus controller300outputs read data to the processor device100from the shared buffer305, and waits for a data reception signal28from the processor device100(S143→S144→S145).

With this, the processor device100obtains the read data. Also, in the case of write access, the bus controller300judges whether or not the processor device100has already outputted write data to the memory I/F1001or the I/O controlling unit1002(S146). Then, in the case of judging that the write data has already been outputted, it means that the write access is completed, and thus the bus controller300takes no action. On the other hand, in the case of judging that the write data has not yet been outputted, the bus controller300waits for the write data to be outputted from the processor device100(S147). When the write data is outputted, a data reception signal26is outputted to the processor device100(S148), and the write data is written to the memory via the memory I/F1001or to the I/O via the I/O controlling unit1002(S149).

In the manner as described, the processor device100switches to the sleep mode during bus access, and completes the bus access when the host CPU200negates the sleep request signal11.

As described up to this point, when the processor device100in the computer system1according to the first embodiment receives the sleep request signal11, it performs the following: outputs to the bus controller300the suspension notification signal21indicating a switch to the suspension mode; and after receiving the suspension notification reception signal22from the bus controller300as a response to the suspension notification signal21, responds to the sleep request signal11with the sleep response signal12. The suspension notification reception signal22is immediately asserted unless the shared buffer305has insufficient capacity, and thus it is possible for the processor device100to immediately respond to it with the sleep response signal. With this, the responsiveness to the sleep request can be significantly improved, and the power consumption can further be reduced. By receiving the suspension notification signal21, the bus controller300can recognize that the processor device100has entered the sleep mode, and thus avoids to output signals that require the processor device100in the sleep mode to respond.

Note that the above mentioned suspension notification reception signal22may be omitted depending on the situations. For example, the bus controller300may omit the suspension notification reception signal22in the case where the bus controller300has a buffer dedicated for the processor device100instead of the shared buffer305, or in the case where no processor other than the processor device100is connected to the bus controller300for executing access.

FIG. 7is a schematic flow chart illustrating processing for the switch to the sleep mode in the case where the suspension notification reception signal22is omitted. This figure is different fromFIG. 3in that Step S14is removed. Here, the description shall omit the common aspects and center on the different ones with respect toFIG. 3. InFIG. 7, the processor device100outputs the sleep response signal12to the host CPU200immediately after outputting the suspension notification signal21to the bus controller300. By doing so, the time period of the sleep mode matches the time period of the sleep mode requested by the host CPU200, thereby allowing the maximum reduction in the power consumption requested by the host CPU200.

FIG. 8is a detailed flow chart illustrating processing for the switch to the sleep mode in the case where the suspension notification reception signal22is omitted. This figure is different fromFIG. 6in that Steps S104and S105are replaced with Step S115, and that Steps S125to S128are removed. Here, the description shall omit the common aspects and center on the different ones with respect toFIG. 6.

In Step S115, the processor device100asserts the sleep response signal12to the host CPU200immediately after asserting the suspension notification signal21, without receiving the suspension notification reception signal22. By doing so, it is possible to match the timing to switch to the sleep mode with the timing requested by the host CPU200.

In addition, since there is no need for the bus controller300to respond to the suspension notification reception signal22, Steps S125to S128are removed, thereby allowing a reduction in the circuit size.

Second Embodiment

The following shall describe a computer system according to a second embodiment which includes a processor device150having a counter provided external to a processor unit. The processor device150is such that when it is in a microsleep mode and the processor unit is in the suspension mode, the clock signal is switched to a lower clock signal, and the counter can count the number of cycles at almost the same or completely the same accuracy as in the operation mode even in the static mode.

FIG. 9is a functional block diagram illustrating an entire structure of the computer system according to the second embodiment of the present invention. A computer system2inFIG. 9is different from the computer system1inFIG. 1in that the computer system2includes a processor device150and a clock controller501instead of the processor device100and the clock controller500. Hereinafter, the description shall omit the common aspects and center on the different ones with respect toFIG. 1.

The clock controller501supplies a clock signal clk L43to the processor device150, in addition to the clock signal clk42. The clock signal clk L43has a cycle K times as long as that of the clock signal clk42. It is desirable that K is a power of 2. In this case, K is assumed to be 8.

The processor device150is different from the processor device100in that the processor device150includes a local clock controller131and a VMP controller160instead of the local clock controller130and the VMP controller140.

The local clock controller131receives the clock signal clk42from the clock controller501, and supplies a clock signal clk_pe101to the processor unit110and a clock signal clk_vmp102to the VMP controller160. The clock signal clk_pe101has the same frequency as that of the clock signal clk42, and it is suspended in the suspension mode. The clock signal clk_vmp102has the same frequency as that of the clock signal clk42(hereinafter referred to as “normal clock”) in the operation mode. On the other hand, in the microsleep mode and when the normal clock is not needed, the clock signal clk_vmp102has the same frequency as that of the clock signal clk L43(hereinafter referred to as “slow clock”).

The VMP controller160is different from the VMP controller140in that the VMP controller160outputs a microsleep mode signal103and a normal clock request signal104to the local clock controller131. The microsleep mode signal103is a signal indicating that the processor device150is in the microsleep mode. The normal clock request signal104is a signal indicating whether to use the clock signal clk42or the clock signal clk L43as the clock signal clk_vmp102. While the normal clock request signal104is asserted, the local clock controller131outputs the normal clock signal clk42as the clock signal clk_vmp102.

FIG. 10is a block diagram illustrating a detailed structure of the VMP controller160. As the figure shows, the VMP controller160includes a counter161and a controlling unit162.

The counter161includes a holding unit151, a subtraction number selecting unit152, and a subtractor153, in order to count down the time allocated to the currently executed program to 0.

The holding unit151is a register holding the current count value.

A mode controlling unit145outputs a subtraction number selection signal154to the subtraction number selecting unit152. The subtraction number selection signal154is a signal indicating whether to select 1 or K as the subtraction number. The subtraction number selecting unit152selects 1 as the subtraction number when the processor device150is in the operation mode, and selects K as the subtraction number when the processor device150is in the microsleep mode.

The subtractor153subtracts the subtraction number notified by the subtraction number selecting unit152from the current count value. The result of the subtraction is held by the holding unit151.

In this manner, the counter161counts down one by one using the clock signal clk42when the processor device150is in the operation mode, and counts down K by K using the clock signal clk L43when the processor device150is in the microsleep mode and the normal clock request signal104is negated indicating that the clock signal L43is selected. The number of cycles or time counted in the microsleep mode results in being almost the same as the number of cycles or time counted in the operation mode (slower by (K−1) cycles at maximum).

Moreover, the counter161is capable of counting down one by one using the normal clock signal clk42when the count value of the holding unit151becomes less than K in the microsleep mode.

The controlling unit162controls the following: the scheduling of a virtual processor brought about by time division multiplexing; the switching of the processor device150between the execution mode and the microsleep mode; and the subtraction number and the clock signal of the counter161. In order to control them, the controlling unit162includes an interrupt detector142, a PUI/F143, a control register144, the mode controlling unit145, and a count value judging unit146.

The interrupt detector142receives an interrupt signal31from the interrupt controller400so as to detect an interrupt. This interrupt serves as a trigger to stop the microsleep mode.

The PUI/F143is an I/F for communication with the processor unit110. The processor unit110accesses the controlling unit162via the PUI/F143.

The control register144is a register capable of reading and writing through a program of the processor unit110. The control register144holds a mode flag indicating the operation mode of the counter161in the microsleep mode. The mode flag is set by the processor unit110, and when its flag value is 0, it indicates an operation mode for counting down one by one, instead of K by K using the normal clock signal clk42when the count value of the holding unit151becomes less than K in the microsleep mode. When its flag value is 1, it indicates prohibition to change the subtraction number from K to 1 when the count value of the counter161becomes less than K in the microsleep mode.

The count value judging unit146judges whether or not the count value held by the holding unit151is greater than K. To be more specific, the count value judging unit146negates a count value judgment signal when the count value is greater than K, whereas it asserts the count value judgment signal when the count value is equal to or less than K.

The mode controlling unit145controls the mode switching of the processor device150. The mode switching of the processor device150is as illustrated inFIG. 15. The mode controlling unit145asserts the microsleep mode signal103when the processor device150is in the microsleep mode602. While the processor device150is in the microsleep mode602and the count value judgment signal is negated (count value>K), the mode controlling unit145negates the normal clock request signal104(selects the slow clock), and asserts the subtraction number selection signal154(causes the subtraction number selecting unit152to select the subtraction number K). While the processor device150is in the microsleep mode602and the count value judgment signal is asserted (count value=<K), the mode controlling unit145asserts the normal clock request signal104(selects the normal clock), and negates the subtraction number selection signal154(causes the subtraction number selecting unit152to select the subtraction number 1).

Next, the following shall describe the operations of the computer system2according to the second embodiment of the present invention.

FIG. 11andFIG. 12illustrate timing charts of the case where switching of contexts does not take place before and after the processor device150switches to the microsleep mode602. The figures show, from the top, the mode of the processor device150, the microsleep mode signal103, the clock signal clk_pe101, the clock signal clk_vmp102, and a count value of the counter161.

The VMP controller160starts the operation for causing the processor device150to switch to the microsleep mode602, when it detects that there is no program to be executed by the processor unit110. In doing so, the VMP controller160asserts the microsleep mode signal103to be outputted to the local clock controller131(at the timing T20inFIG. 11).FIG. 11illustrates the case where the remaining number of cycles of the counter161, which counts the program execution time, is 1024 at this point. When the microsleep mode signal103is asserted, the local clock controller131suspends the supply of the clock signal clk_pe101, and switches the clock signal clk_vmp102to the clock signal clk L43to be supplied to the VMP controller160. Here, it is assumed that the frequency of the clock signal clk L43is one eighth of the frequency of the clock signal clk42. The VMP controller160counts the remaining time of the program execution time using the clock signal clk_vmp102. At this point, the number of cycles to be subtracted when the counter161performs the counting operation is changed to 8. The reason for changing the number of cycles to be subtracted to 8 is to counterbalance the impact of switching the clock frequency to a low frequency when counting the remaining number of cycles of the program execution.

When the remaining number of cycles of the counter161becomes 0, the VMP controller160negates the microsleep mode signal103(timing T21). When the microsleep mode signal103is negated, the local clock controller131switches the clock signal clk_pe101and the clock signal clk_vmp102to the clock signal clk42.

As describe above, through the operations illustrated inFIG. 11, the time counted in the microsleep mode can approximately match the time counted in the operation mode. This provides an adequate condition for performing real-time processing having strict time restrictions.

Note that in the case where there is no program which can be executed at the timing T21, the processor device150continues to be in the microsleep mode. In this case, the processor device150switches to the program execution mode when it becomes possible, later on, for another program to be executed.

FIG. 11illustrates the case where the number of remaining cycles is 1024 which is a multiple of 8. Now, with reference toFIG. 12, the following shall describe the operations in the case where the number of remaining cycles is not a multiple of 8.

FIG. 12illustrates the case where the number of remaining cycles of the counter161is 700. In such case, at the timing T22when the number of remaining cycles becomes 4 (in other words, when the number of remaining cycles becomes less than 8), the VMP controller160asserts the normal clock request signal104to be outputted to the local clock controller131(timing T23). While the normal clock request signal104is asserted, the local clock controller131switches the clock signal clk_vmp102to the clock signal clk42. After that, when the number of remaining cycles of the counter161becomes 0, the microsleep mode signal103and the normal clock request signal104are negated (timing T24). When the microsleep mode signal103is negated, the local clock controller131switches the clock signal clk_pe101and the clock signal clk_vmp102to the clock signal clk42, similarly to the operation ofFIG. 11.

As described above, through the operation ofFIG. 12, the time counted in the microsleep mode can completely match the time counted in the operation mode. As a result, this provides an adequate condition for performing real-time processing having stricter time restrictions.

Next, the following shall describe the case where context is transferred while the processor device150is in the microsleep mode602.

FIG. 13illustrates a timing chart of the case where context is transferred while the processor device150is in the microsleep mode602.

At the timing T25ofFIG. 13, the processor device100switches from the program execution mode600to the microsleep mode602. When context switching is necessary when switching back to the program execution mode600at the timing T28, context is transferred during the time between the timing T25and T28, as illustrated inFIG. 13. The mode for transferring the context is referred to as a context transfer mode603. InFIG. 13, the context transfer starts at the timing T26and ends at the timing T27. The start of the context transfer is determined by the VMP controller160. The VMP controller160determines the start of the context transfer as the need arises at the timing, for example, when a period of time elapses since the start of the microsleep mode, or when the count value counted in the microsleep mode becomes a predetermined value. In order to transfer the context, the VMP controller160negates the microsleep mode signal103, and switches the clock signal clk_pe101and the clock signal clk_vmp102to the clock signal clk42. In this manner, the context is transferred at high speed at the same frequency as the one at which the processor device150executes the program. At the timing T27when the context transfer is completed, the VMP controller160again asserts the microsleep mode signal103, suspends the supply of the clock signal clk_pe101, and switches the clock signal clk_vmp102to the clock signal clk L43.

As described, since the context transfer is performed at high speed in the microsleep mode using the normal clock signal, it is possible to ensure the processing performance without delaying the start timing of the program to be switched to.

As described, the VMP controller160is capable of optimally controlling the clock signal for the counter161and for the context transfer in the microsleep mode602.

Further, the processor device150also switches to the program execution mode600through the interrupt signal31being asserted in the microsleep mode602. A timing chart ofFIG. 14illustrates the operations in such a case. In the case where the context switching is necessary at the timing T29when the interrupt signal31is asserted, the processor device150switches to the context transfer mode603. In the case of switching to the program execution mode600through the interrupt signal31and the program execution is urgent, the processor device150immediately switches to the program execution mode600at the timing T30as illustrated inFIG. 14.

Note that the switching from the program execution mode602to the microsleep mode602may be performed in the following manner. When the currently executed program completes the necessary processing within the allocated time, the processor unit110at first makes a halt while the clock signal is being supplied, and immediately after that, switches to the microsleep mode602. As a result, the power consumption can be reduced by simply making the halt, and it can be further reduced by suspending the supply of the clock signal.

In the second embodiment, the clock signal clk L43is supplied from an external unit of the processor device150. Note, however, that the clock signal clk L43may be generated within the processor device150through frequency division of the clock signal clk42within the processor device150, for example.

Here, the supply of the clock signal to the processor unit110and the memory controller120is resumed when the processor device150is in the context transfer mode603. However, in the present embodiment where the processor device150switches to the context transfer mode603while it is in the microsleep mode602, there is no need to supply the clock signal to the entire processor unit110and the entire memory controller120, since the program is not executed in the context transfer mode603. Accordingly, the clock signal may be supplied only to the circuit involved in the context transfer.

Note that in the case where the processing is not urgent and a program, for which the reduction of power consumption is a priority higher than the real-time execution thereof, is to be executed, the following is also possible: to count the number of cycles of the context transfer mode603and the microsleep mode602using the clock signal clk L43without switching the above described clock signal clk_vmp102to the clock signal clk42. For this selection, the VMP controller160may have a selection register, and the user may make the setting by software.

Third Embodiment

FIG. 16is a functional block diagram illustrating an entire structure of a music reproduction function-equipped mobile phone device2000for which a computer system according to a third embodiment of the present invention is used.

AsFIG. 16illustrates, the music reproduction function-equipped mobile phone device2000includes a system LSI1000, an antenna2001, a high-frequency signal transmitting and receiving unit2002, an external memory2003, an input and output unit2004, and an SDRAM2005.

The system LSI1000includes the computer system1illustrated in the first embodiment or the computer system2illustrated in the second embodiment, the memory I/F1001, and the I/O controlling unit1002.

At first, the I/O controlling unit1002reads music data accumulated in the external memory2003, and stores the music data in the SDRAM2005. In order to reproduce the music data, the processor device100reads the music data from the SDRAM2005, and reproduces it. The reproduced data is again stored in the SDRAM2005.

The reproduced data accumulated in the SDRAM2005is read again by the I/O controlling unit1002via the memory I/F1001, and is transmitted to the input and output unit2004. The input and output unit2004is in a mobile phone with a built-in speaker. The user can listen to the reproduced music through the built-in speaker of the input and output unit2004.

During the reproduction of the music data, the processor device100is not always in an operation, and there is a time period during which no program execution is needed. During such a time period, the processor device100is caused to switch to the microsleep mode602for the purpose of reducing the power consumption of the mobile phone.

The method for switching to the microsleep mode602is as described in the second embodiment.

The following shall describe the operation performed by the music reproduction function-equipped mobile phone device2000in the case where radio waves for communication are received from the antenna2001while the processor device100is in the microsleep mode602.

When radio waves for communication are received from the antenna2001, the high-frequency signal transmitting and receiving unit2002detects this, and notifies the I/O controlling unit1002of the detection. Here, the I/O controlling unit1002outputs an interrupt signal to the interrupt controller400. Then, the interrupt controller400outputs an interrupt signal to the processor device100. When the interrupt signal is received, the processor device100at first switches from the microsleep mode602to the context transfer mode603so as to switch to the program execution mode600and perform communication. After transferring the context for the communication, the processor device100switches to the program execution mode600. The method for controlling the clock signal when the processor device100switches to the context transfer mode603is as described in the second embodiment.

INDUSTRIAL APPLICABILITY

The present invention is suitable for computer systems including a processor device having an execution mode for receiving a supply of a clock signal and a suspension mode in which the supply of the clock signal is suspended by responding, with a sleep response signal, to a sleep request signal received from an external device. The present invention is especially useful for appliances such as mobile phones for which a high level of power consumption reduction is required.