SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

A method for fabricating semiconductor devices includes forming a first semiconductor channel structure and a second semiconductor channel structure over a substrate; forming a metal gate structure, wherein the metal gate structure includes a first portion and a second portion straddling the first semiconductor channel structure and the second semiconductor channel structure, respectively; replacing a third portion of the metal gate structure between the first portion and the second portion with a first dielectric material to form a gate isolation structure, wherein a width of the gate isolation structure along the second direction decreases with an increasing depth of the gate isolation structure toward the substrate; and replacing a portion of the gate isolation structure, the second portion of the metal gate structure, and the second semiconductor channel structure with a second dielectric material to form an edge isolation structure.

BACKGROUND

Fin Field-Effect Transistor (FinFET) devices are becoming commonly used in integrated circuits. FinFET devices have a three-dimensional structure that comprises one or more fins protruding from a substrate. A gate structure, configured to control the flow of charge carriers within a conductive channel of the FinFET device, wraps around the one or more fins. For example, in a tri-gate FinFET device, the gate structure wraps around three sides of each of the one or more fins, thereby forming conductive channels on three sides of each of the one or more fins.

DETAILED DESCRIPTION

An integrated circuit typically includes a large number of devices (e.g., transistors). To fabricate these devices, a number of (e.g., planar and/or non-planar) active regions and a number of gate structures that intersect the active regions can be formed on a substrate or wafer to define such devices. To further configure those transistors to operate as certain circuits, some of the transistors can be operatively connected to or disconnected from each other. In general, to disconnect transistors in a relatively dense area of the substrate, an active (e.g., metal) gate structure overlaying multiple fin structures can be cut into multiple portions that overlay the respective fin structures of those disconnected devices. Such cut portions can be electrically isolated by a gate isolation structure. On the other hand, to disconnect transistors in a relatively sparse area of the substrate, an active (e.g., metal) gate structure overlaying multiple fin structures can be patterned, thereby removing a portion of the active gate structure that overlays one or more of the fin structures not configured as active channels (sometimes referred to as inactive channels) and removing the one or more inactive channels.

In the existing technologies, while removing a first portion of the metal gate structure (and the underlying inactive channel(s)) in the relatively sparse area, a second portion of the metal gate structure that overlays the fin structure(s) configured as active channels may be damaged, which damages a profile of the metal gate structure and in turn adversely impacts performance of the integrated circuit as a whole. For example, a certain portion of a gate isolation structure located between the first and second portions may also be removed, during the removal process of the first portion. While removing the portion of the gate isolation structure, an upper part of the gate isolation structure is typically (inadvertently) etched thinner. Such a thinned-down upper part can damage the profile of the metal gate structure that overlays the active channels, e.g., during the removal process of the first portion.

The present disclosure provides various embodiments of a semiconductor device that includes a number of transistors (e.g., FinFETs, gate-all-around (GAA) FETs), and a method for forming the same. In some embodiments, in a relatively sparse area of a substrate, a first gate isolation structure with a reverse-trapezoid profile (e.g., a wider upper portion and narrower lower portion) can be formed between two portions of a first active (e.g., metal) gate structure. In such embodiments, in a relatively dense area of the substrate, a second gate isolation structure formed between two portions of a second active (e.g., metal) gate structure can have nearly vertical sidewalls. In this way, while removing a first portion of the first metal gate structure that overlays an inactive channel, the wider upper portion of the first gate isolation structure can provide further buffer, thereby preventing etchants from penetrating to a second portion of first the metal gate structure that overlays an active channel. As such, the profiles and dimensions of an active gate structure can be accurately defined and reserved.

FIG.1illustrates a perspective view of an example FinFET device100, in accordance with various embodiments. The FinFET device100includes a substrate102and a fin104protruding above the substrate102. Isolation regions106are formed on opposing sides of the fin104, with the fin104protruding above the isolation regions106. A gate dielectric108is along sidewalls and over a top surface of the fin104, and a gate110is over the gate dielectric108. Source region112S and drain region112D are in (or extended from) the fin104and on opposing sides of the gate dielectric108and the gate110.FIG.1is provided as a reference to illustrate a number of cross-sections in subsequent figures. For example, cross-section B-B extends along a longitudinal axis of the gate110of the FinFET device100. Cross-section A-A is perpendicular to cross-section B-B and is along a longitudinal axis of the fin104and in a direction of, for example, a current flow between the source/drain regions112S/112D. Subsequent figures may sometimes refer to these reference cross-sections for clarity.

FIG.2illustrates a flowchart of a method200to form a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method200can be used to form a FinFET device (e.g., FinFET device100), a nanostructure transistor, like nanosheet transistor device, a nanowire transistor device, gate-all-around transistor, or the like. It is noted that the method200is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method200ofFIG.2, and that some other operations may only be briefly described herein. In some embodiments, operations of the method200may be associated with cross-sectional or top views of an example semiconductor device at various fabrication stages as shown inFIGS.3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18, and19, respectively, which will be discussed in further detail below.

In brief overview, the method200starts with operation202of providing a substrate. The method200continues to operation204of forming a number of semiconductor fin structures. The method200continues to operation206of forming an isolation structure. The method200continues to operation208of forming dummy gate structures over the fin structures. The method200continues to operation210of forming a gate spacer. The method200continues to operation212of growing source/drain structures. The method200continues to operation214of forming an interlayer dielectric (ILD). The method200continues to operation216of forming active gate structures. The method200continues to operation218of cutting the active gate structures. The method200proceeds to operation220of forming gate isolation structures. The method200proceeds to operation222of removing one of the semiconductor fin structures in one of the areas on the substrate. The method200continues to operation224of depositing a dielectric refill material.

As mentioned above,FIGS.3-19each illustrate, in a cross-sectional view, a portion of a semiconductor device300at various fabrication stages of the method200ofFIG.2. The semiconductor device300is similar to the FinFET device100shown inFIG.1, but with multiple gate structures and multiple fins. For example, the semiconductor device300can include a plural number of gate structures each of which can overlay one or more fins. AlthoughFIGS.3-19illustrate the semiconductor device300, it is understood the semiconductor device300may include a number of other devices such as inductors, fuses, capacitors, coils, etc., which are not shown inFIGS.3-19, for purposes of clarity of illustration.

Corresponding to operation202ofFIG.2,FIG.3is a cross-sectional view of the semiconductor device300including a semiconductor substrate302at one of the various stages of fabrication, in some embodiments. The cross-sectional view of the semiconductor device300inFIG.3is cut along the lengthwise direction of a gate structure, e.g., cross-section B-B (as indicated inFIG.1).

In some embodiments, the semiconductor device300can include areas302A and302B. The area302A can be configured to form a number of input/output (I/O) transistors (hereinafter “I/O area302A”); and the area302B can be configured to form a number of core transistors (hereinafter “core area302B”). The terms “I/O transistor” and “core transistor,” as used herein, may be generally referred to a transistor configured to operate under a relatively higher voltage (e.g., higher Vgs) and a transistor configured to operate under a relatively lower voltage (e.g., lower Vgs), respectively. Thus, it should be understood that the I/O transistor can include any of various other transistors operating under a relatively higher voltage and the core transistor can include any of various other transistors operating under a relatively lower voltage, while remaining within the scope of the present disclosure. The I/O transistor, when appropriately configured, may have a relatively thicker gate dielectric; and the core transistor, when appropriately configured, has a relatively thinner gate dielectric. Further, the I/O transistors may be formed in a first area of the substrate (e.g., I/O area302A) with a relatively lower density of transistors; and the core transistors may be formed in a second area of the substrate (e.g., core area302B) with a relatively higher density of transistors. As such, features (e.g., fins) in the I/O area302A may be more sparsely formed, when compared to the features (e.g., fins) formed in the core area302B.

As shown inFIG.3(and the following figures), the I/O area302A and core area302B are separated from each other by a symbolic divider303, which can include additional features/components/devices that are omitted for simplicity. It should be appreciated that some of the operations of the method200may be concurrently performed in the I/O area302A and core area302B. For purposes of illustration, some of the feature(s) formed in the I/O area302A and the core area302B are hereinafter shown in the same figure that corresponds to one of the operations of the method200.

Corresponding to operation204ofFIG.2,FIG.4is a cross-sectional view of the semiconductor device300including semiconductor fin structures404A,404B,404C, and404D at one of the various stages of fabrication. The cross-sectional view ofFIG.4is cut along the lengthwise direction of an active/dummy gate structure of the semiconductor device300(e.g., cross-section B-B indicated inFIG.1).

The semiconductor fin structures404A-B are formed in the I/O area302A, and the semiconductor fin structures404C-D are formed in the core area302B. Although two semiconductor fin structures are shown in each of the I/O area302A and core area302B, it should be appreciated that the semiconductor device300can include any number of semiconductor fin structures in each of the areas302A and302B while remaining within the scope of the present disclosure.

Some of the semiconductor fin structures404A-D, if still remains, may be each configured as an active fin, which will be adopted as an active (e.g., electrically functional) fin or channel in a completed FinFET. In the illustrated examples, the semiconductor fin structure404A may be configured as the active channel of a first input/output (I/O) transistor of the semiconductor device300(sometimes referred to as “active I/O channel404A”); the semiconductor fin structure404B may be later removed from the semiconductor device300(sometimes referred to as “inactive I/O channel404B”); the semiconductor fin structure404C may be configured as the active channel of a first core transistor of the semiconductor device300(sometimes referred to as “active core channel404C”); and the semiconductor fin structure404D may be configured as the active channel of a second core transistor of the semiconductor device300(sometimes referred to as “active core channel404D”).

The semiconductor fin structures404A-D are formed by patterning the substrate302using, for example, photolithography and etching techniques. For example, a mask layer, such as a pad oxide layer406and an overlying pad nitride layer408, is formed over the substrate302. The pad oxide layer406may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer406may act as an adhesion layer between the substrate302and the overlying pad nitride layer408. In some embodiments, the pad nitride layer408is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. Although only one pad nitride layer408is illustrated, a multilayer structure (e.g., a layer of silicon oxide on a layer of silicon nitride) may be formed as the pad nitride layer408. The pad nitride layer408may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example.

The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer406and pad nitride layer408to form a patterned mask410, as illustrated inFIG.4.

The patterned mask410is subsequently used to pattern exposed portions of the substrate302to form trenches (or openings)411, thereby defining the semiconductor fin structures404A-D between adjacent trenches411as illustrated inFIG.4. When multiple fin structures are formed, such a trench may be disposed between any adjacent ones of the fin structures. In some embodiments, the semiconductor fin structures404A-D are formed by etching trenches in the substrate302using, for example, reactive ion etch (ME), neutral beam etch (NBE), the like, or combinations thereof. The etch may be anisotropic. In some embodiments, the trenches411may be strips (viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches411may be continuous and surround the semiconductor fin structures404A-D.

As shown inFIG.4, the semiconductor fin structures404A-B in the I/O area302A are formed to be separated from each other with a first spacing417, and the semiconductor fin structures404C-D in the core area302B are formed to be separated from each other with a second spacing419. In various embodiments, the first spacing417can be substantially greater than the second spacing419. For example with a certain process node, the first spacing417can range from about 5 nanometers (nm) to about 500 nm, and the second spacing419can range from about 5 nm to about 500 nm.

FIGS.3and4illustrate an embodiment of forming the semiconductor fin structures404A-D, but a fin structure may be formed in various different processes. For example, a top portion of the substrate302may be replaced by a suitable material, such as an epitaxial material suitable for an intended type (e.g., N-type or P-type) of semiconductor devices to be formed. Thereafter, the substrate302, with epitaxial material on top, is patterned to form the semiconductor fin structures404A-D that include the epitaxial material.

As another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form one or more fin structures.

In yet another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form one or more fin structures.

In embodiments where epitaxial material(s) or epitaxial structures (e.g., the heteroepitaxial structures or the homoepitaxial structures) are grown, the grown material(s) or structures may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in an NMOS region different from the material in a PMOS region. In various embodiments, the semiconductor fin structures404A-D may include silicon germanium (SixGe1-x, where x can be between 0 and 1), silicon carbide, pure or pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Corresponding to operation206ofFIG.2,FIG.5is a cross-sectional view of the semiconductor device300including isolation regions500at one of the various stages of fabrication. The cross-sectional view ofFIG.5is cut along the lengthwise direction of an active/dummy gate structure of the semiconductor device300(e.g., cross-section B-B indicated inFIG.1).

The isolation regions500, which are formed of an insulation material, can electrically isolate neighboring fin structures from each other. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other insulation materials and/or other formation processes may be used. In an example, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP), may remove any excess insulation material and form top surfaces of the isolation regions500and a top surface of the fin structures404A-D that are coplanar (not shown). The patterned mask410(FIG.4) may also be removed by the planarization process.

In some embodiments, the isolation regions500include a liner, e.g., a liner oxide (not shown), at the interface between each of the isolation regions500and the substrate302(semiconductor fin structures404A-D). In some embodiments, the liner oxide is formed to reduce crystalline defects at the interface between the substrate302and the isolation region500. Similarly, the liner oxide may also be used to reduce crystalline defects at the interface between the fin structures404A-D and the isolation region500. The liner oxide (e.g., silicon oxide) may be a thermal oxide formed through a thermal oxidation of a surface layer of the substrate302, although other suitable method may also be used to form the liner oxide.

Next, the isolation regions500are recessed to form shallow trench isolation (STI) regions500, as shown inFIG.5. The isolation regions500are recessed such that the upper portions of the semiconductor fin structures404A-D protrude from between neighboring STI regions500. Respective top surfaces of the STI regions500may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or combinations thereof. The top surfaces of the STI regions500may be formed flat, convex, and/or concave by an appropriate etch. The isolation regions500may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation regions500. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation regions500.

In some other embodiments, at least one dummy fin structure (formed of a dielectric material) may be formed between the adjacent semiconductor fin structures404A and404B and/or between the adjacent semiconductor fin structures404C and404D, i.e., in the trench411. Such a dummy fin structure can be formed prior to, concurrently with, or subsequently to forming the STI regions500. Further, the dummy fin structure can have a bottom surface aligned with or disposed below the top surface of the STI region500(i.e., the bottom surface of the dummy fin structure is in contact with the substrate302), or have the bottom surface embedded in the STI region500(i.e., the bottom surface of the dummy fin structure is separated apart from the substrate302with the STI region500).

Corresponding to operation208ofFIG.2,FIG.6is a cross-sectional view of the semiconductor device300including a dummy gate structure600in the I/O area302A and a dummy gate structure620in the core area302B at one of the various stages of fabrication. The cross-sectional view ofFIG.6is cut along a lengthwise direction of the dummy gate structures600and620of the semiconductor device300(e.g., cross-section B-B indicated inFIG.1).

The dummy gate structure600is formed to overlay a respective portion of each of the fin structures (e.g., semiconductor fin structures400A-B) in the I/O area302A. Prior to, concurrently with, or subsequently to forming the dummy gate structure600in the I/O area302A, a dummy gate structure620may be formed in the core area302B to overlay a portion of each of the semiconductor fin structures404C-D. The dummy gate structure620is similar to the dummy gate structure600, except for its dimensions, and thus, the dummy gate structure620will be briefly discussed below.

The dummy gate structure600includes a dummy gate dielectric602and a dummy gate604, in some embodiments. A mask606may be formed over the dummy gate structure600. To form the dummy gate structure600, a dielectric layer is formed on the semiconductor fin structures404A-B. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like, and may be deposited or thermally grown. Similarly, the dummy gate structure620includes a dummy gate dielectric622and a dummy gate624, with a mask626formed thereon.

A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like.

After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using suitable lithography and etching techniques to form the mask606(626). The pattern of the mask606(626) then may be transferred to the gate layer and the dielectric layer by a suitable etching technique to form the dummy gate604(624) and the underlying dummy gate dielectric602(622), respectively. The dummy gate604and the dummy gate dielectric602cover a respective portion (e.g., a channel region) of each of the semiconductor fin structures404A-B; and the dummy gate1024and the dummy gate dielectric622cover a portion (e.g., a channel region) of the semiconductor fin structures404C-D. The dummy gate604(624) may also have a lengthwise direction (e.g., direction B-B ofFIG.1) perpendicular to the lengthwise direction (e.g., direction of A-A ofFIG.1) of the fin structures.

The dummy gate dielectric602is shown to be formed over the semiconductor fin structures404A-B (e.g., over the respective top surfaces and the sidewalls of the fin structures) and over the STI regions500in the example ofFIG.6. Similarly, the dummy gate dielectric622is formed to overlay the semiconductor fin structures404C-D (e.g., overlaying the respective top surfaces and the sidewalls of the fin structures). In other embodiments, the dummy gate dielectric602(622) may be formed by, e.g., thermal oxidization of a material of the semiconductor fin structures, and therefore, may be formed over the semiconductor fin structures but not over the STI regions500. It should be appreciated that these and other variations are still included within the scope of the present disclosure.

FIGS.7-9illustrate the cross-sectional views of further processing (or making) of the semiconductor device300along cross-section A-A of one of the semiconductor fin structures404A-D (as indicated inFIG.1). One dummy gate structure600is illustrated over the semiconductor fin structure404A, which is selected as a representative example, inFIGS.7-9. It should be appreciated that more than one dummy gate structure can be formed over the semiconductor fin structure404A (and each of the other semiconductor fin structures, e.g.,404B-D), while remaining within the scope of the present disclosure.

Corresponding to operation210ofFIG.2,FIG.7is a cross-sectional view of the semiconductor device300including gate spacer700formed around (e.g., along and contacting the sidewalls of) the dummy gate structure600. For example, the gate spacer700may be formed on opposing sidewalls of the dummy gate structure600. It should be understood that any number of gate spacers can be formed around the dummy gate structures600while remaining within the scope of the present disclosure.

The gate spacer700may be a low-k spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, or the like. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), or the like, may be used to form the gate spacer700. The shapes and formation methods of the gate spacer700as illustrated inFIG.7are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

Corresponding to operation212ofFIG.2,FIG.8is a cross-sectional view of the semiconductor device300including a number of source/drain regions800at one of the various stages of fabrication. The source/drain regions800are formed in recesses of the semiconductor fin structure404A adjacent to the dummy gate structures600, e.g., between adjacent dummy gate structures600and/or next to a dummy gate structure600. The recesses are formed by, e.g., an anisotropic etching process using the dummy gate structures600as an etching mask, in some embodiments, although any other suitable etching process may also be used.

The source/drain regions800are formed by epitaxially growing a semiconductor material in the recess, using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof.

As illustrated inFIG.8, the epitaxial source/drain structures800may have surfaces raised from respective surfaces of the semiconductor fin structure404A (e.g. raised above the non-recessed portions of the semiconductor fin structure404A) and may have facets. In some embodiments, the source/drain structures800of the adjacent semiconductor fin structures may merge to form a continuous epitaxial source/drain structure (not shown). In some embodiments, the source/drain structures800of the adjacent semiconductor fin structures may not merge together and remain separate source/drain structures800(not shown). In some embodiments, when the resulting FinFET device is an n-type FinFET, the source/drain structures800can include silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), or the like. In some embodiments, when the resulting FinFET device is a p-type FinFET, the source/drain structures800comprise SiGe, and a p-type impurity such as boron or indium.

The epitaxial source/drain structures800may be implanted with dopants to form source/drain structures800followed by an annealing process. The implanting process may include forming and patterning masks such as a photoresist to cover the regions of the semiconductor device300that are to be protected from the implanting process. The source/drain structures800may have an impurity (e.g., dopant) concentration in a range from about 1×1019cm−3to about 1×1021cm−3. P-type impurities, such as boron or indium, may be implanted in the source/drain structures800of a P-type transistor. N-type impurities, such as phosphorous or arsenide, may be implanted in the source/drain structures1200of an N-type transistor. In some embodiments, the epitaxial source/drain structures800may be in situ doped during their growth.

Corresponding to operation214ofFIG.2,FIG.9is a cross-sectional view of the semiconductor device300including an interlayer dielectric (ILD)900at one of the various stages of fabrication. In some embodiments, prior to forming the ILD900, a contact etch stop layer (CESL)902is formed over the structure, as illustrated inFIG.9. The CESL902can function as an etch stop layer in a subsequent etching process, and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be formed by a suitable formation method such as CVD, PVD, combinations thereof, or the like.

Next, the ILD900is formed over the CESL902and over the dummy gate structures1000. In some embodiments, the ILD900is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. After the ILD900is formed, an optional dielectric layer1304is formed over the ILD900. The dielectric layer904can function as a protection layer to prevent or reduces the loss of the ILD900in subsequent etching processes. The dielectric layer904may be formed of a suitable material, such as silicon nitride, silicon carbonitride, or the like, using a suitable method such as CVD, PECVD, or FCVD. After the dielectric layer904is formed, a planarization process, such as a CMP process, may be performed to achieve a level upper surface for the dielectric layer904. The CMP may also remove the mask606and portions of the CESL902disposed over the dummy gate604(FIG.8). After the planarization process, the upper surface of the dielectric layer904is level with the upper surface of the dummy gate604, in some embodiments.

Corresponding to operation216ofFIG.2,FIG.10is a cross-sectional view of the semiconductor device300in which active gate structures1000and1020replace the dummy gate structures600(in the I/O area302A) and620(in the core area302B), respectively, at one of the various stages of fabrication. The cross-sectional view ofFIG.10is cut along the lengthwise direction of the active gate structures1000and1020of the semiconductor device300(e.g., cross-section B-B indicated inFIG.1). For illustration, an example top view of the semiconductor device300(without the ILD900being displayed) is shown inFIG.11.

The active gate structure1000may be formed by replacing the dummy gate structure600(FIG.6); and the active gate structure1020may be formed by replacing the dummy gate structure620(FIG.6). As illustrated inFIGS.10-11, the active gate structure1000can straddle or otherwise overlay respective (e.g., central) portions of the semiconductor fin structures404A and404B; and the active gate structure1020can straddle or otherwise overlay respective (e.g., central) portions of the semiconductor fin structures404C and404D.

The active gate structures1000and1020can each include a gate dielectric layer (e.g.,1002,1022), a metal gate layer (1004,1024), and one or more other layers that are not shown for clarity. For example, each of the active gate structures1000and1020may further include a capping layer and a glue layer. The capping layer can protect the underlying work function layer from being oxidized. In some embodiments, the capping layer may be a silicon-containing layer, such as a layer of silicon, a layer of silicon oxide, or a layer of silicon nitride. The glue layer can function as an adhesion layer between the underlying layer and a subsequently formed gate electrode material (e.g., tungsten) over the glue layer. The glue layer may be formed of a suitable material, such as titanium nitride.

The gate dielectric layers1002and1022each include silicon oxide, silicon nitride, or multilayers thereof. In example embodiments, the gate dielectric layers1002and1022each include a high-k dielectric material, and in these embodiments, the gate dielectric layers1002and1022may each have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The formation methods of the gate dielectric layers1002and1022may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. A thickness of each of the gate dielectric layers1002and1022may be between about 8 angstroms (Å) and about 20 Å, as an example.

The metal gate layers1004and1024may each be a P-type work function layer, an N-type work function layer, multi-layers thereof, or combinations thereof, in some embodiments. Accordingly, the metal gate layers1004and1024may each be referred to as a work function layer, in some embodiments. In the discussion herein, a work function layer may also be referred to as a work function metal. Example P-type work function metals that may be included in the gate structures for P-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Example N-type work function metals that may be included in the gate structures for N-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.

A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process. The thickness of a P-type work function layer may be between about 8 Å and about 15 Å, and the thickness of an N-type work function layer may be between about 15 Å and about 30 Å, as an example.

Corresponding to operation218ofFIG.2,FIG.12is a cross-sectional view of the semiconductor device300in which the active gate structures1000and1020are respectively cut, intercepted, or otherwise disconnected to form a gate cut trench1200in the I/O area302A and a gate cut trench1250in the core area302B at one of the various stages of fabrication. The cross-sectional view ofFIG.12is cut along the lengthwise direction of the active gate structures1000and1020of the semiconductor device300(e.g., cross-section B-B indicated inFIG.1). For illustration, an example top view of the semiconductor device300(without the ILD900being displayed) is shown inFIG.13.

To form the gate cut trench1200, one or more etching processes may be performed to remove a portion of the metal gate1004and a portion of the gate dielectric1002that are interposed between the semiconductor fins404A and404B. Concurrently with forming the gate cut trench1200, the same etching process(es) may be performed to remove a portion of the metal gate1024and a portion of the gate dielectric1022that are interposed between the semiconductor fins404C and404D. The etching process(es) may stop when the top surfaces of the STI regions500in the I/O area302A and core area302B are respectively exposed.

Further, prior to the etching process(es), a mask1203may be formed over the active gate structures1000and1020to expose portions of the metal gates1004and1024desired to be removed by forming openings in the I/O area302A and the core area302B, respectively. Through the mask1203, the etching process(es) are performed to remove the respective portions of the active gate structures1000and1020. By using a certain characteristic of the etching process(es) (which will be discussed as follows), the gate cut trench1200can be formed to have a reverse-trapezoid profile, e.g., with a width of its upper portion (1201U) wider than a width of its lower portion width (1201L); and the gate cut trench1250can be formed to have a rectangular profile, e.g., with a width of its upper portion (1251U) about the same as a width of the lower portion width (1251L).

In various embodiments, the etching process(es) may have one or more stages, each of which can be characterized with a respective combination of anisotropic etching and isotropic etching. For example, a first stage may have more anisotropic etching than isotropic etching. In other words, the first stage can vertically (or along a certain direction) etch the active gate structures1000and1020more quickly than it laterally etches the active gate structures1000and1020. As such, after the first stage, the gate cut trenches1200and1250may each present a valley-shaped profile.

The first stage can include a plasma etching process. In such a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gaseous etchants such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gaseous etchants and combinations thereof can be used with passivation gases. The passivation gases can include nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the etchants and/or the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof.

As a non-limiting example, in the first stage, a source power P1(e.g., ranging from about 500 watts to about 800 watts) and a bias power P2(e.g., ranging from about 200 watts to 300 watts) may be applied during the first 60% of the first stage, under a pressure of 1 millitorr to 5 torr and an etch gas flow of 0 standard cubic centimeters per minute to 5000 standard cubic centimeters per minute. For the rest 40% of the first stage, while the source power P1may keep constant, the bias power may be reduced to about 0 watts. As such, during the first 60%, the first stage may present a higher amount/extent of the anisotropic etching, and during the rest 40%, the amount of anisotropic etching may be reduced to be comparable with an amount of the isotropic etching. However, it is noted that source powers (and their applied time durations), bias powers (and their applied time durations), pressures, and flow rates outside of these ranges can also be contemplated, while remaining within the scope of the present disclosure.

Following the first stage, a second stage performed may have a mixture of anisotropic etching and isotropic etching. In other words, the second stage can vertically (or along a certain direction) etch the active gate structures1000and1020while laterally etching the active gate structures1000and1020. The valley-shaped profiles of the gate cut trenches1200and1250can thus laterally extend until the gate cut trenches1200and1250expose the top surfaces of the STI regions500, respectively. As such, the gate cut trench1200can present a reverse-trapezoid profile and the gate cut trench1250can present a rectangular profile, as illustrated inFIG.12.

For example, the gate cut trench1200has its upper portion with a width,1201U, that is greater than the width1201L of its lower portion, and the gate cut trench1250has its upper portion with a width,1251U, that is about the same as the width1251L of its lower portion. Alternatively stated, the gate cut trench1200may have at least one of its sidewalls and the top surface of the STI region500(or the top surface of the substrate302) to form an acute angle, θ1, and the gate cut trench1250may have at least one of its sidewalls and the top surface of the STI region500(or the top surface of the substrate302) to form a nearly right angle, θ2. In a non-limiting example, the angle θ1may range between about 60 degrees and about 80 degrees, and the angle θ2may be about 90 degrees.

The second stage can include a plasma etching process. In such a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gaseous etchants such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gaseous etchants and combinations thereof can be used with passivation gases. The passivation gases can include nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the etchants and/or the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof.

As a non-limiting example, in the second stage, a source power P1(e.g., ranging from about 800 watts to about 1200 watts) and a bias power P2(e.g., ranging from about 200 watts to 300 watts) may be applied during the first 10% of the second stage, under a pressure of 1 millitorr to 5 torr and an etch gas flow of 0 standard cubic centimeters per minute to 5000 standard cubic centimeters per minute. For the next 40% of the second stage, the source power may be reduced to P3(e.g., ranging from about 120 watts to 160 watts), and the bias power may be reduced to about 0 watts. During the rest 50% of the second stage, the source power is reduced to about 0 watts, and the bias power is increased to P4, which ranges from about 80 watts to about 100 watts. As such, after the first 10% (the next 40%), the second stage may present a higher amount/extent of the isotropic etching than an amount of the anisotropic etching, which may result from a relatively high amount of radicals. During the rest 50%, the second stage may present a higher amount of the anisotropic etching than an amount of the isotropic etching. For example, in the rest 50%, the radicals can be pulled along a certain direction (e.g., a vertical direction) to further shape the valley-shaped profiles to present the profiles, as shown inFIG.12. However, it is noted that source powers (and their applied time durations), bias powers, pressures (and their applied time durations), and flow rates outside of these ranges can also be contemplated, while remaining within the scope of the present disclosure.

Corresponding to operation220ofFIG.2,FIG.14is a cross-sectional view of the FinFET device300including a gate isolation structure1400in the I/O area302A and a gate isolation structure1450in the core area302B at one of the various stages of fabrication. The cross-sectional view ofFIG.14is cut along the lengthwise direction of the active gate structures1000and1020of the FinFET device300(e.g., cross-section B-B indicated inFIG.1). For illustration, an example top view of the semiconductor device300(without the ILD900being displayed) is shown inFIG.15.

The gate isolation structures1400and1450are formed by filling the gate cut trenches1200and1250, respectively, with a dielectric material. As such, the gate isolation structures1400and1450can inherit the profiles (or dimensions) of the gate cut trenches1200and1250, respectively. For example, the gate isolation structure1400can have its sidewalls separated from each other by a distance (or a critical dimension) gradually decreasing with an increasing depth toward the substrate302. Alternatively stated, one sidewall of the gate isolation structure1400(e.g., the sidewall of the left-hand side inFIG.14) can tilt toward the semiconductor fin structure404A, and the other sidewall of the gate isolation structure1400(e.g., the sidewall of the right-hand side inFIG.14) can tilt toward the semiconductor fin structure404B. The gate isolation structure1450can have its sidewalls separated from each other by a distance (or a critical dimension), with a variation less than ±10%. Alternatively stated, both sidewalls of the gate isolation structure1450may be nearly perpendicular to the top surface of the substrate302.

The dielectric material that is used to form the gate isolation structures1400and1450may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or combinations thereof. The gate isolation structures1400and1450can be formed by depositing the dielectric material in the gate cut trenches1200and1250, respectively, using any suitable method, such as CVD, PECVD, or FCVD. After the deposition, a CMP may be performed to remove any excess dielectric material from the remaining active gate structures1000and1020.

Although the example ofFIG.14shows that the gate isolation structures1400and1450respectively fill the gate cut trenches1200and1250with a single dielectric piece (which can include one or more dielectric materials listed above), it is understood that the gate isolation structures1400and1450can each include multiple pieces. Each of the pieces may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or combinations thereof. For example, the gate isolation structures1400and1450may each include a first piece, which is formed as a conformal layer lining the respective gate cut trench, and a second piece, which fills the gate cut trench with the first piece coupled therebetween. In another example, the gate isolation structures1400and1450may each include a first piece, which fills a lower portion of the respective gate cut trench, and a second piece, which fills an upper portion of the gate cut trench.

Corresponding to operation222ofFIG.2,FIG.16is a cross-sectional view of the FinFET device300in which a cavity1601is formed at one of the various stages of fabrication. The cross-sectional view ofFIG.16is cut along the lengthwise direction of the active gate structures1000and1020of the FinFET device300(e.g., cross-section B-B indicated inFIG.1). For illustration, an example top view of the semiconductor device300(without the ILD900being displayed) is shown inFIG.17.

To form the cavity1601, which is configured to remove the semiconductor fin structure404B that functions as an inactive channel, at least some of the following operations may be performed: (i) forming a patterned mask over the workpiece that exposes a portion of the active gate structure1000overlaying the semiconductor fin structure404B and a portion of the gate isolation structure1400(FIG.14); (ii) performing a first etching process to remove the exposed portion of the active gate structure1000and the exposed portion of the gate isolation structure1400(thereby exposing the semiconductor fin structure404B); (iii) performing a second etching process to remove an upper portion of the semiconductor fin structure404B (e.g., the portion located above the top surface of the STI region500); and (iv) performing a third etching process to remove a lower portion of the semiconductor fin structure404B (e.g., the portion located below the top surface of the STI region500) and a portion of the substrate302(e.g., the portion located below a bottom surface of the STI region500). Such a series of operations to remove an inactive channel may sometimes be referred to as a Cut Poly Oxide Diffusion Edge (CPODE) process.

With the gate isolation structure1400(FIG.14) having the wider upper portion, etchants used in the CPODE process (e.g., chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), etc.) cannot easily penetrate through the gate isolation structure1400. As such, damage to the portion of the active gate structure1000that overlays the semiconductor fin structure404A (which functions as an active channel) can be minimized, which can well reserve its dimensions and profiles.

In various embodiments, a portion of the gate isolation structure1400′ may remain, as shown inFIG.16. For example, the remaining gate isolation structure1400′ can have one sidewall that contacts the remaining portion of the active gate structure1000reserved (i.e., unexposed), and the other sidewall exposed in the cavity1601. As such, the unexposed sidewall can still tilt toward the remaining portion of the active gate structure1000, and the exposed sidewall may also tilt toward the remaining portion of the active gate structure1000. In some embodiments, the sidewalls of the remaining gate isolation structure1400′ may be in parallel with each other. It should be understood that the exposed sidewall may be formed in any of various other profiles (e.g., nearly perpendicular to the top surface of the STI region500, tilted away from the remaining portion of the active gate structure1000, etc.), while remaining within the scope of the present disclosure. In some embodiments, the remaining gate isolation structure1400′ can have a uniform thickness, as shown inFIG.16. Alternatively stated, a distance between the sidewalls of the remaining gate isolation structure1400′ may remain the same, with the increasing height of the remaining gate isolation structure1400′.

Corresponding to operation224ofFIG.2,FIG.18is a cross-sectional view of the semiconductor device300in which the cavity1601(FIG.16) is filled with a dielectric refill material1802at one of the various stages of fabrication. The cross-sectional view ofFIG.18is cut along the lengthwise direction of the active gate structures1000and1020of the semiconductor device300(e.g., cross-section B-B indicated inFIG.1). For illustration, an example top view of the semiconductor device300(without the ILD900being displayed) is shown inFIG.19.

In various embodiments, the dielectric refill material1802may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like. The dielectric refill material1802can inherit the profiles and dimensions of the cavity1601(FIG.16). For example, the dielectric refill material1802can extend through the STI region500and into the substrate302; and the dielectric refill material1802can contact the sidewall of the remaining gate isolation structure1400′ that was exposed in the cavity1601. In some embodiments, the dielectric refill material1802filling the cavity1601can electrically disconnect or otherwise isolate neighboring transistors, which is sometimes referred to as an “edge isolation structure1802.”

In one aspect of the present disclosure, a method for fabricating semiconductor devices is disclosed. The method includes forming a first semiconductor channel structure and a second semiconductor channel structure over a substrate that both extend along a first direction. The method includes forming a metal gate structure that extends along a second direction perpendicular to the first direction, wherein the metal gate structure includes a first portion and a second portion straddling the first semiconductor channel structure and the second semiconductor channel structure, respectively. The method includes replacing a third portion of the metal gate structure between the first portion and the second portion with a first dielectric material to form a gate isolation structure, wherein a width of the gate isolation structure along the second direction decreases with an increasing depth of the gate isolation structure toward the substrate. The method includes replacing a portion of the gate isolation structure, the second portion of the metal gate structure, and the second semiconductor channel structure with a second dielectric material to form an edge isolation structure.

In another aspect of the present disclosure, a method for fabricating semiconductor devices is disclosed. The method includes forming a first semiconductor channel structure and a second semiconductor channel structure over a first area of a substrate. The method includes forming a third semiconductor channel structure and a fourth semiconductor channel structure over a second area of the substrate, wherein the first to fourth semiconductor channel structures all extend along a first direction. The method includes forming a first metal gate structure that extends along a second direction perpendicular to the first direction to straddle the first semiconductor channel structure and the second semiconductor channel structure. The method includes forming a second metal gate structure that extends along the second direction to straddle the third semiconductor channel structure and the fourth semiconductor channel structure. The method includes replacing a portion of the first metal gate structure interposed between the first and second semiconductor channel structures with a first gate isolation structure, wherein a width of the first gate isolation structure along the second direction decreases with an increasing depth of the first gate isolation structure toward the substrate. The method includes replacing a portion of the second metal gate structure interposed between the third and fourth semiconductor channel structures with a second gate isolation structure, wherein a width of the second gate isolation structure along the second direction remains constant with an increasing depth of the second gate isolation structure toward the substrate.

In yet another aspect of the present disclosure, a method for fabricating semiconductor devices is disclosed. The method includes forming a first semiconductor channel structure and a second semiconductor channel structure over a first area of a substrate. The method includes forming a third semiconductor channel structure and a fourth semiconductor channel structure over a second area of the substrate, wherein the first to fourth semiconductor channel structures all extend along a first direction. The method includes forming a first metal gate structure that extends along a second direction perpendicular to the first direction to straddle the first semiconductor channel structure and the second semiconductor channel structure. The method includes forming a second metal gate structure that extends along the second direction to straddle the third semiconductor channel structure and the fourth semiconductor channel structure. The method includes forming a first gate isolation structure by replacing a portion of the first metal gate structure interposed between the first and second semiconductor channel structures, wherein a width of the first gate isolation structure along the second direction decreases with an increasing depth of the first gate isolation structure toward the substrate. The method includes forming a second gate isolation structure by replacing a portion of the second metal gate structure interposed between the third and fourth semiconductor channel structures, wherein a width of the second gate isolation structure along the second direction remains constant with an increasing depth of the second gate isolation structure toward the substrate. The method includes forming an edge isolation structure by replacing another portion of the first metal gate structure straddling the second semiconductor channel structure, a portion of the first gate isolation structure, and the second semiconductor channel structure with a dielectric material.