Light emitting diode chip and display composed of light emitting diode chips

A light emitting diode chip comprises a light emitting diode chip core and a coating layer. The coating layer covers side surfaces of the light emitting diode chip core. And a display composed of the light emitting diode chips is also provided.

FIELD

The subject matter herein generally relates to a light emitting device.

BACKGROUND

Light emitting diodes are widely used as display components in a display field. The display component includes light emitting diode chips and a base. Each light emitting diode chip is formed on the base. Overcoming heat dissipation problems and wavelength deviations are problematic.

DETAILED DESCRIPTION

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale, and the proportions of certain parts may be exaggerated to illustrate details and features of the present disclosure better. The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

A light emitting diode chip is disclosed. The light emitting diode chip comprises:

a light emitting diode chip core; and

a coating layer covering side surfaces of the light emitting diode chip core.

The coating layer comprises graphite, diamond-like carbon, and silicone.

The coating layer is coated on the light emitting diode chip core.

The light emitting diode chip core comprises a substrate, an epitaxial layer, and an electrically connecting layer.

The epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer, the active layer, and the second semiconductor layer are formed sequentially on the substrate.

The electrically connecting layer comprises a first electrode, a second electrode and an insulating layer, and the insulating layer is formed between the first electrode and the second electrode.

The first electrode is formed on the first semiconductor layer, and the second electrode formed on the second semiconductor layer.

A plurality of first holes is defined by the second electrode.

At least one receiving portion is defined by the epitaxial layer, and each open end of the receiving portion corresponds to a first hole.

The receiving portion is defined through the second semiconductor layer and the active layer, and a bottom surface of the receiving portion is defined at the first semiconductor layer.

The insulating layer comprises a plurality of first insulating portions and a plurality of second insulating portions. The first insulating portions are formed on the second electrode and separated from each other, and the second insulating portions are positioned between two adjacent first insulating portions and extend downwardly from the first insulating portions to the bottom surfaces of the receiving portions.

The first electrode comprises a first electrode plate formed on the first insulating portion and a plurality of filling blocks received in the first holes and the receiving portions.

The filling blocks of the first electrode are electrically connected to the first semiconductor layer, and the filling blocks of the first electrode are electrically insulated from the second electrode, the second semiconductor layer, and the active layer by the second insulating portions.

The second electrode comprises a second electrode plate formed on the second semiconductor layer and an additional block defined by the second electrode plate. The additional block extends upwardly from the second electrode plate.

A gap is defined between the additional block and the first electrode plate of the first electrode, a part of the first insulating portion of the insulating layer extends through a bottom end of the gap, and the gap is defined on the first insulating portion.

The insulating layer further comprises a plurality of third insulating portions connected to the second insulating portions. The third insulating portions are formed on the bottom surface of the receiving portion, and the third insulating portions partly cover the bottom surface of the receiving portion.

A receiving recess is defined between two adjacent third insulating portions, and a bottom surface of the receiving recess is the bottom surface of the receiving portion.

The insulating layer further comprises a fourth insulating portion formed in the second electrode. The fourth insulating portion is connected to the first insulating portion, and the fourth insulating portion is positioned between the second electrode plate and the additional block.

At least one second hole is defined by the fourth insulating portion, and a part of the second insulating portion is received in the second hole for electrically connecting with the second electrode plate.

A display composed of light emitting diode chips comprises:a base;a plurality of light emitting diode chips formed on the base and each of the light emitting diode chips comprising:a light emitting diode chip core; anda coating layer covering side surfaces of the light emitting diode chip core;a plurality of wires electrically connected with the light emitting diode chips; anda plurality of electrically connecting plates electrically connected with the wires.

FIG. 1shows a light emitting diode chip100in accordance with an exemplary embodiment of the present disclosure.

The light emitting diode chip100comprises a light emitting diode chip core10and a coating layer20. The coating layer20covers side surfaces of the light emitting diode chip core10. The coating layer20can be made of graphite, diamond-like carbon, and silicone. The coating layer20can cover the light emitting diode chip core10by a coating process.

The light emitting diode chip core10comprises a substrate11, an epitaxial layer12, and an electrically connecting layer13. The epitaxial layer12is formed on the substrate11. The electrically connecting layer13is electrically connected with the epitaxial layer12. The electrically connecting layer13can be formed on the epitaxial layer12.

The substrate11can be made of sapphire, silicon carbide (SiC), pure silicon (Si), or gallium nitride (GaN), etc.

The epitaxial layer12comprises a first semiconductor layer121, an active layer122, and a second semiconductor layer123. The first semiconductor layer121, the active layer122and the second semiconductor layer123are formed on the substrate11in that sequence.

In at least one embodiment, the first semiconductor layer121can be an N-type doped semiconductor layer, and the second semiconductor layer123can be a P-type doped semiconductor layer. In an alternative embodiment, the first semiconductor layer121and the second semiconductor layer123can be a P-type doped semiconductor layer and an N-type doped semiconductor layer, respectively.

In one embodiment, the first semiconductor layer121is an N-type doped semiconductor layer, and the second semiconductor layer123is a P-type doped semiconductor layer.

The light emitting diode chip core10further comprises a buffer layer14. The buffer layer14is formed between the substrate11and the first semiconductor layer121.

The electrically connecting layer13comprises a first electrode131, a second electrode132, and an insulating layer133. The insulating layer133is formed between the first electrode131and the second electrode132. The first electrode131is electrically connected with the first semiconductor layer121. The first electrode131is formed on the first semiconductor layer121. The second electrode132is electrically connected with the second semiconductor layer123. The second electrode132is formed on the second semiconductor layer123. A plurality of first holes1323is defined by the second electrode132.

At least one receiving portion124is defined by the epitaxial layer12. Each open end of the receiving portion124corresponds to each first hole1323. The receiving portion124is defined through the second semiconductor layer123and the active layer122. A bottom surface of the receiving portion124can be defined at the first semiconductor layer121.

The first semiconductor layer121defines a first surface1211and a second surface1212opposite to the first surface1211. The first surface1211faces the active layer122. In at least one embodiment, the bottom surface of the receiving portion124can be the first surface1211. In an alternative embodiment, the bottom surface of the receiving portion124can be positioned between the first surface1211and the second surface1212. In this embodiment, the bottom surface of the receiving portion124is positioned between the first surface1211and the second surface1212.

The insulating layer133comprises a plurality of first insulating portions1331and a plurality of second insulating portions1332.

The first insulating portions1331are formed on the second electrode132. The first insulating portions1331are separate from each other.

The second insulating portions1332are positioned between two adjacent first insulating portions1331and extend downwardly from the first insulating portions1331to the bottom surfaces of the receiving portions124. A top end of the second insulating portion1332is connected to the first insulating portion1331, and a bottom end of the second insulating portion1332is connected to the bottom surface of the receiving portion124. The second insulating portion1332covers a side surface of the first hole1323and a side surface of the receiving portion124.

The insulating layer133further comprises a plurality of third insulating portions1333. The third insulating portions1333are connected to the second insulating portions1332. The third insulating portions1333are formed on the bottom surface of the receiving portion124. The third insulating portions1333partly cover the bottom surface of the receiving portion124. A receiving recess1334is defined between two adjacent third insulating portions1333. A bottom surface of the receiving recess1334is the bottom surface of the receiving portion124.

The first electrode131comprises a first electrode plate1311and a plurality of filling blocks1312. The first electrode plate1311is formed on the first insulating portion1331. The filling blocks1312are received in the first holes1323and the receiving portions124. The filling blocks1312of the first electrode131are electrically connected to the first semiconductor layer121. The filling blocks1312of the first electrode131are electrically insulated from the second electrode132, the second semiconductor layer123, and the active layer122by the second insulating portions1332.

In at least one embodiment, each the filling block1312can define a first portion1313and a second portion1314. The second portion1314is received in the receiving recess1334, and the first portion1313is formed on the second portion1314.

The second electrode132comprises a second electrode plate1321and an additional block1322. The second electrode plate1321is formed on the second semiconductor layer123. The additional block1322is defined by the second electrode plate1321and extends upwards from the second electrode plate1321. A gap1324is defined between the additional block1322and the first electrode plate1311of the first electrode131. A part of the first insulating portion1331of the insulating layer133extends to a bottom end of the gap1324. The gap1324is defined on the first insulating portion1331.

The insulating layer133can further comprise a fourth insulating portion1335. The fourth insulating portion1335is formed in the second electrode132. The fourth insulating portion1335is connected to the first insulating portion1331. The fourth insulating portion1335is positioned between the second electrode plate1321and the additional block1322. At least one second hole1336is defined by the fourth insulating portion1335. A part of second insulating portion1332is received in the second hole1336for electrically connecting with the second electrode plate1321.

Referring toFIGS. 2-3,FIG. 2shows a display200according to the present disclosure, andFIG. 3is a top view of the display200ofFIG. 2.

The display200can be used in a telephone, a computer, or an e-reader. The display200comprises a base201, the light emitting diode chips100, a plurality of wires202, and a plurality of electrically connecting plates203. The light emitting diode chips100, the wires202and the electrically connecting plates203are arranged on the base201.

The light emitting diode chips100are electrically connected with the electrically connecting plates203by the wires202. In at least one embodiment, the light emitting diode chips100can be in parallel electrically connected with each other by the wires202. In at least one embodiment, the light emitting diode chips100can be in series electrically connected with each other by the wires202. In an alternative embodiment, the light emitting diode chips100can be connected in series and in parallel by the wires202.

The wires202can be made of gold, copper, or silver.

The electrically connecting plates203can be made of gold, copper, silver, or aluminum.

An embodiment of a method for producing the display200comprises:

providing a base201;

cutting the light emitting diode pre-layer to generate the light emitting diode chip cores10;

applying the coating layers20on each light emitting diode chip core10to generate the light emitting diode chips100; and

forming the electrically connecting the electrically connecting plates203on the base201, and electrically connecting the electrically connecting plates203and the light emitting diode chips100.