Trench schottky diode and manufacturing method thereof

A trench Schottky diode and a manufacturing method thereof are provided. A plurality of trenches are formed in A semiconductor substrate. A plurality of doped regions are formed in the semiconductor substrate and under some of the trenches. A gate oxide layer is formed on a surface of the semiconductor substrate and the surfaces of the trenches. A polysilicon structure is formed on the gate oxide layer. Then, the polysilicon structure is etched, so that the gate oxide layer within the trenches is covered by the polysilicon structure. Then, a mask layer is formed to cover the polysilicon structure within a part of the trenches and a part of the gate oxide layer, and the semiconductor substrate uncovered by the mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate.

This application claims the benefit of Taiwan Patent Application No. 100104981, filed Feb. 15, 2011, the subject matter of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a trench Schottky diode, and more particularly to a trench Schottky diode with low reverse-biased leakage current, low forward voltage drop, high reverse voltage, and fast reverse recovery time. The present invention also relates to a method for manufacturing such a trench Schottky diode.

BACKGROUND OF THE INVENTION

A Schottky diode is a unipolar device using electrons as carriers, which is characterized by high switching speed and low forward voltage drop. The limitations of Schottky diodes are the relatively low reverse voltage tolerance and the relatively high reverse leakage current. The limitations are related to the Schottky barrier height determined by the metal work function of the metal electrode, and the band gap of the semiconductor, the type and concentration of dopants in the semiconductor layer, and other factors. Recently, a trench-MOS Schottky barrier diode has been disclosed. In the trench-MOS Schottky barrier diode, a trench filled with polysilicon or metallic material is used for pinching the reverse-biased leakage current and thus largely reducing the leakage current of the semiconductor device.

A trench-MOS Schottky barrier diode has been disclosed in U.S. Pat. No. 5,365,102, which is entitled “SCHOTTKY BARRIER RECTIFIER WITH MOS TRENCH”. Please refer toFIGS. 1A˜1F, which schematically illustrate a method of manufacturing a conventional trench MOS Schottky barrier diode.

Firstly, as shown inFIG. 1A, a semiconductor substrate12with an epitaxial layer thickness is provided. The substrate12has two surfaces12aand12b. A heavily-doped (N+ type) cathode region12cis adjacent to the surface12a. A lightly-doped (N type) drift region12dis extended from the heavily-doped (N+ type) cathode region12cto the surface12b. A silicon dioxide (SiO2) layer13is grown on the substrate12. A silicon nitride (Si3N4) layer15is grown on the silicon dioxide layer13. The formation of the silicon dioxide layer13may reduce the stress that is provided by the silicon nitride layer15. Moreover, a photoresist layer17is formed on the silicon nitride layer15.

Then, as shown inFIG. 1B, a photolithography and etching process is performed to pattern the photoresist layer17and partially remove the silicon nitride layer15, the silicon dioxide layer13and the substrate12. Consequently, a plurality of discrete mesas14are defined in the drift region12dof the substrate12. In addition, the etching step defines a plurality of trenches22. Each trench22has a specified depth and a specified width. Then, as shown inFIG. 10, a thermal oxide layer16is formed on a sidewall22aand a bottom22bof the trench22. Then, as shown inFIG. 1D, the remaining silicon nitride layer15and the remaining silicon dioxide layer13are removed. Then, as shown inFIG. 1E, a metallization layer23is formed over the resulting structure ofFIG. 1D. Then, as shown inFIG. 1F, a metallization process is performed to form another metallization layer (not shown) on the backside surface12a. After a sintering process is performed, the metallization layer23contacted with the discrete mesas14are connected with each other to define a single anode electrode layer23, and a cathode electrode20on the backside surface12a, and a cathode electrode layer20is formed on the backside surface12a. Since the anode electrode layer23is contacted with the mesas14, a so-called Schottky barrier results in a Schottky contact. Meanwhile, the trench MOS Schottky barrier diode is produced.

The trench MOS Schottky barrier rectifier (TMBR) fabricated by the above method has low forward voltage drop. Moreover, since the reverse-biased leakage current is pinched by the trench, the leakage current is reduced when compared with the Schottky diode having no trenches. Generally, for the trench MOS Schottky barrier rectifier to be with a reverse voltage of about 120V, its leakage current of is about several tens of microamps. In practice, the magnitude of the leakage current is also dependent on the chip size. Therefore, the present invention relates to a trench Schottky diode with high reverse voltage and low leakage current.

SUMMARY OF THE INVENTION

The present invention provides a trench Schottky diode with high reverse voltage and low leakage current.

An embodiment of the present invention provides a method for manufacturing a trench Schottky diode. Firstly, a semiconductor substrate is provided. Then, a plurality of first trenches and a plurality of second trenches are formed in the semiconductor substrate, wherein the opening width of the first trench is greater than the opening width of the second trench. Then, a plurality of doped regions are formed in the semiconductor substrate and under respective first trenches. A gate oxide layer is formed on a surface of the semiconductor substrate and surfaces of the first trenches and the second trenches. A polysilicon structure is formed on the gate oxide layer. Then, the polysilicon structure is etched, so that the gate oxide layer within the first trenches and the second trenches is covered by the polysilicon structure. Then, a mask layer is formed to cover the polysilicon structure within the first trenches and the gate oxide layer within the first trenches. Then, the semiconductor substrate is etched, so that the surface of the semiconductor substrate uncovered by the mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate, the polysilicon structure within the second trenches and a part of the mask layer.

Another embodiment of the present invention provides a trench Schottky diode. The trench Schottky diode includes a semiconductor substrate, a plurality of doped regions, a gate oxide layer, a plurality of polysilicon structures, a mask layer and a metal sputtering layer. The semiconductor substrate has a plurality of first trenches and a plurality of second trenches, wherein the opening width of the first trench is greater than the opening width of the second trench. The doped regions are formed in the semiconductor substrate and under respective first trenches. The gate oxide layer is formed on sidewalls and bottom surfaces of the first trenches and the second trenches and formed on a part of a surface of the semiconductor substrate. The polysilicon structures are formed on the gate oxide layer within the first trenches and the second trenches. The mask layer is formed on the polysilicon structures within the first trenches and the gate oxide layer. The metal sputtering layer covers a part of the surface of the semiconductor substrate, the polysilicon structures within the second trenches and a part of the mask layer.

A further embodiment of the present invention provides a method for manufacturing a trench Schottky diode. Firstly, a semiconductor substrate is provided. Then, a first oxide layer is formed on a surface of the semiconductor substrate. The first oxide layer is etched to form a first mask layer. At least one first trench and a plurality of second trenches are formed in the semiconductor substrate, wherein the opening width of the first trench is greater than the opening width of the second trench. A second oxide layer is formed on sidewalls and bottom surfaces of the first trench and the second trenches. The second oxide layer is removed. A third oxide layer is formed on the sidewalls and the bottom surfaces of the first trench and the second trenches. A polysilicon structure is formed to cover the third oxide layer and the first oxide layer. The polysilicon structure is etched, so that the third oxide layer within the second trenches and the sidewall of the first trench are covered by the polysilicon structure. The third oxide layer is etched, so that the third oxide layer within the first trench is thinned or eliminated. An ion implantation process and a drive-in process are performed to form a doped region under the first trenches. A second mask layer is formed to cover a part of the first oxide layer, a part of the polysilicon structure and the first trench. The semiconductor substrate is etched, so that the surface of the semiconductor substrate uncovered by the second mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate, the polysilicon structure within the second trenches and a part of the second mask layer.

A still embodiment of the present invention provides a trench Schottky diode. The trench Schottky diode includes a semiconductor substrate, a doped region, an oxide layer, a plurality of polysilicon structures, a mask layer and a metal sputtering layer. The semiconductor substrate has at least one first trench and a plurality of second trenches, wherein the opening width of the first trench is greater than the opening width of the second trench. The doped region is formed in the semiconductor substrate and under the first trench. The oxide layer is formed on sidewalls and bottom surfaces of the second trenches, formed on a sidewall and a part of a bottom surface of the first trench, and formed on a part of a surface of the semiconductor substrate. The polysilicon structures are formed on the oxide layer within the second trenches and formed on the oxide layer within the first trench. The mask layer is formed on the polysilicon structures within the first trench and a part of the oxide layer. The metal sputtering layer covers a part of the surface of the semiconductor substrate, the polysilicon structures within the second trenches and a part of the mask layer.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Please refer toFIGS. 2A˜2T, which schematically illustrate a method of manufacturing a trench Schottky diode according to a first embodiment of the present invention.

Firstly, as shown inFIG. 2A, a semiconductor substrate30is provided. The semiconductor substrate30comprises a heavily-doped (N+ type) silicon layer31and a lightly-doped (N type) epitaxial layer32. The lightly-doped epitaxial layer32is formed on the heavily-doped silicon layer31. Moreover, the lightly-doped epitaxial layer32has a specified thickness for facilitating defining a plurality of trenches in the subsequent etching process.

Then, a thermal oxidation process at a temperature of 90˜1000° C. or a chemical vapor deposition (CVD) process is carried out, and thus a first oxide layer41is formed on a surface32aof the lightly-doped epitaxial layer32. In this embodiment, the thickness of the first oxide layer41is about 6000 angstroms.

Then, as shown inFIG. 2B, a first photoresist layer B1with a first photoresist pattern is formed on the first oxide layer41. According to the first photoresist layer B1, the first oxide layer41is etched to have the first photoresist pattern. In this embodiment, the first photoresist pattern corresponds to the profiles of the trenches in the subsequent etching process. After the first oxide layer41is etched to have the first photoresist pattern, the first oxide layer41may be used as a hard mask for defining the trenches.

Then, as shown inFIG. 2C, the remaining first oxide layer41is served as a first mask layer. In an embodiment, the first oxide layer41is etched as the first mask layer by an etching process (e.g. a dry etching process). After the first mask layer is formed on the semiconductor substrate30, the first photoresist layer B1is removed, and the resulting structure is shown inFIG. 2D.

Then, as shown inFIG. 2E, by using the first oxide layer41as the first mask layer, a trench etching process is performed to form a plurality of trenches33aand33bin the semiconductor substrate30. The opening width of the right-side trench33ais about 2-3 times the opening width of the left-side trench33b. The right-side trenches33aare used as guard rings. The left-side trenches33bare used as the trench Schottky diode. Generally, the guard rings are located at the peripheral regions of the semiconductor substrate30. The inner region of the semiconductor substrate30is a device area, i.e. the trench Schottky diode.

After the trenches33aand33bare formed, rough edges may be formed on the bottom surfaces and the sidewalls of the trenches33aand33b.Then, a trench rounding process is performed to remove the rough edges so as to provide a better condition for the formation of associated oxide layers in the subsequent processes. In an embodiment, the trench rounding process is carried out by performing a dry etching process at a thickness of several hundred angstroms to modify the surfaces of the trenches33aand33b.Then, a second oxide layer42is formed on the surfaces (including the bottom surfaces and the sidewalls) of the trenches33aand33b. The second oxide layer42is served as a sacrificial oxide layer (seeFIG. 2F).

Then, as shown inFIG. 2G, a chemical vapor deposition process is performed to form a third oxide layer43. The narrow trenches33bare filled with the third oxide layer43. Whereas, the third oxide layer43are formed on the bottom surfaces and the sidewalls of the wide trenches33a. That is, the second oxide layer42within the trenches33aand33band the first oxide layer41are covered by the third oxide layer43.

Then, as shown inFIG. 2H, an etch-back process is performed to partially remove the third oxide layer43. Consequently, the third oxide layer43on the bottom surfaces of the wide trenches33ais thinned. Whereas, since the narrow trenches33bare filled with the third oxide layer43, the etch-back process fails to etch the bottom surface of the narrow trenches33b.

Then, as shown inFIG. 2I, an ion implantation process and a drive-in process are performed to dope the epitaxial layer32with P-type dopant through the wide trenches33a. Consequently, a plurality of P-type doped regions34are formed under the trenches33a(seeFIG. 2J).

Then, as shown inFIG. 2K, a wet etching process is performed with a hydrofluoric acid (HF) solution to remove the first oxide layer41, the second oxide layer42and the third oxide layer43.

Then, as shown inFIG. 2L, a thermal oxidation process is carried out at a temperature of 90˜1000° C., and thus a gate oxide layer35is formed on the surfaces of the trenches33aand33band the surface32aof the semiconductor substrate30.

Then, as shown inFIG. 2M, a polysilicon structure36is formed on the gate oxide layer35and filled in the trenches33aand33bby a chemical vapor deposition (CVD) process.

Then, as shown inFIG. 2N, an etch-back process is performed to remove the undesired part of the polysilicon structure36. That is, a dry etching process is performed to uniformly and downwardly etch the polysilicon structure36for a preset etching time without the need of using any photoresist pattern. As shown inFIG. 2N, the gate oxide layer35is exposed, and the polysilicon structure36is still remained in the trenches33aand33b.

Then, as shown inFIG. 2O, a chemical vapor deposition (CVD) process is performed to form a fourth oxide layer37on the gate oxide layer35and the polysilicon structure36.

After the fourth oxide layer37is formed, a second photoresist layer B2with a second photoresist pattern is formed on the fourth oxide layer37(seeFIG. 2P). Then, as shown inFIG. 2Q, the fourth oxide layer37and the gate oxide layer35uncovered by the second photoresist layer B2are removed by a contact etching process. Then, the second photoresist layer B2is removed. Meanwhile, the fourth oxide layer37is served as a second mask layer.

Then, as shown inFIG. 2R, a metal sputtering process is performed to form a metal sputtering layer50on the second mask layer, the surface32aof the semiconductor substrate30and the polysilicon structure36. In this embodiment, the metal sputtering layer50comprises a first metal layer51and a second metal layer52. The first metal layer51is made of titanium (Ti). The second metal layer52is sputtered on the first metal layer51. In addition, the second metal layer52is made of aluminum/silicon/copper (Al/Si/Cu) alloy.

After the first metal layer51of the metal sputtering layer50is in contact with the surface32aof the lightly-doped (N type) epitaxial layer32of the semiconductor substrate30, a Schottky contact is generated. Moreover, after this step is performed, a rapid thermal process (RTP) is optionally performed to facilitate formation of the Schottky contact.

Then, as shown inFIG. 2S, a third photoresist layer B3with a third photoresist pattern is formed on the metal sputtering layer50. Then, the metal sputtering layer50uncovered by the third photoresist layer B3(i.e. the right-side area of the wafer as shown inFIG. 2R) is removed by an etching process. After the etching process is completed, the third photoresist layer B3is removed. The resulting structure is shown inFIG. 2T. In this step, the etching process is a metal etching process to remove the first metal layer51and the second metal layer52of the metal sputtering layer50uncovered by the third photoresist layer B3. Consequently, the surface of the fourth oxide layer37(i.e. the second mask layer) at the right-side area of the wafer is exposed. In practice, due to the over-etching effect of the metal etching process, the exposed fourth oxide layer37is partially removed. That is, the thickness of the exposed fourth oxide layer37is slightly shrunk (seeFIG. 2T).

The finished trench Schottky diode according to the first embodiment of the present invention is shown inFIG. 2T. The outer area I is the guard ring. The inner area II is the device area. The P-type doped region34of the guard ring is effective to reduce the leakage current of the trench Schottky diode and increase the reverse voltage thereof. The experiments demonstrate that the reverse voltage of the trench Schottky diode can reach 160V. In a case that the trench Schottky diode of the present invention has the size similar to the conventional trench Schottky diode, the leakage current can be reduced to 10 microamperes or less.

In the first embodiment of the present invention, the trench Schottky diode comprises a semiconductor substrate30, a plurality of P-type doped regions34, a gate oxide layer35, a plurality of polysilicon structures36, a second mask layer (i.e. the fourth oxide layer37) and a metal sputtering layer50. A plurality of trenches33aand33bare formed in the semiconductor substrate30. These trenches are classified into two types, i.e. first trenches33aand second trenches33b. The opening width of the first trench33ais greater than the opening width of the second trench33b. The P-type doped regions34are formed in the semiconductor substrate30and located under the first trenches33a. The gate oxide layer35is formed on the sidewalls and the bottom surfaces of the trenches33aand33band formed on a part of a surface32aof the semiconductor substrate30. The polysilicon structures36are formed on the gate oxide layer35within the trenches33aand33b. The second mask layer37is formed on the polysilicon structures36within the first trenches33aand the gate oxide layer35. The metal sputtering layer50is formed on a part of the surface32aof the semiconductor substrate30, the polysilicon structures36within the second trenches36and a part of the mask layer37.

Please refer toFIGS. 3A˜3R, which schematically illustrate a method of manufacturing a trench Schottky diode according to a second embodiment of the present invention.

Firstly, as shown inFIG. 3A, a semiconductor substrate60is provided. The semiconductor substrate60comprises a heavily-doped (N+ type) silicon layer61and a lightly-doped (N type) epitaxial layer62. The lightly-doped epitaxial layer62is formed on the heavily-doped silicon layer61. Moreover, the lightly-doped epitaxial layer62has a specified thickness for facilitating defining a plurality of trenches in the subsequent etching process.

Then, a thermal oxidation process at a temperature of 90˜1000° C. or a chemical vapor deposition (CVD) process is carried out, and thus a first oxide layer71is formed on a surface62aof the lightly-doped epitaxial layer62. In this embodiment, the thickness of the first oxide layer61is about 6000 angstroms.

Then, as shown inFIG. 3B, a first photoresist layer B1with a first photoresist pattern is formed on the first oxide layer71. According to the first photoresist layer B1, the first oxide layer71is etched to have the first photoresist pattern. In this embodiment, the first photoresist pattern corresponds to the profiles of the trenches in the subsequent etching process.

After the first oxide layer71is etched to have the first photoresist pattern, the first oxide layer71may be used as a hard mask for defining the trenches.

Then, as shown inFIG. 3C, the remaining first oxide layer71is served as a first mask layer. In an embodiment, the first oxide layer71is etched as the first mask layer by an etching process (e.g. a dry etching process). After the first mask layer is formed on the semiconductor substrate60, the first photoresist layer B1is removed, and the resulting structure is shown inFIG. 3D.

Then, as shown inFIG. 3E, by using the first oxide layer71as the first mask layer, a trench etching process is performed to form a plurality of trenches63aand63bin the semiconductor substrate60. The opening width of the right-side trench63ais much wider than the opening width of the left-side trench63b. The right-side trench63ais used as a guard ring. The left-side trenches63bare used as the trench Schottky diode.

After the trenches63aand63bare formed, rough edges may be formed on the bottom surfaces and the sidewalls of the trenches63aand63b.Then, a trench rounding process is performed to remove the rough edges so as to provide a better condition for the formation of associated oxide layers in the subsequent processes. In an embodiment, the trench rounding process is carried out by performing a dry etching process at a thickness of several hundred angstroms to modify the surfaces of the trenches63aand63b.Then, a second oxide layer72is formed on the surfaces (including the bottom surfaces and the sidewalls) of the trenches63aand63b. The second oxide layer72is served as a sacrificial oxide layer (seeFIG. 3F).

Then, after a wet etching process is performed to remove the second oxide layer72and a part of the first oxide layer71, a third oxide layer73is grown on the bottom surfaces and the sidewalls of the trenches63aand63b(seeFIG. 3G).

Then, as shown inFIG. 3H, a polysilicon structure66is formed on the third oxide layer73and the first oxide layer71and filled in the left-side trenches63bby a chemical vapor deposition (CVD) process

Then, as shown inFIG. 3I, an etch-back process is performed to remove the undesired part of the polysilicon structure66. That is, a dry etching process is performed to uniformly and downwardly etch the polysilicon structure66for a preset etching time without the need of using any photoresist pattern. As shown inFIG. 3I, the polysilicon structure66is still remained in the trenches63aand63b.

Then, as shown inFIG. 3J, an etch-back process is performed to partially remove the third oxide layer73. Consequently, the third oxide layer73on the bottom surfaces of the wide trenches63ais thinned or eliminated. Whereas, since the narrow trenches63bare filled with the third oxide layer73, the etch-back process fails to etch the bottom surface of the narrow trenches63b.

Then, as shown inFIG. 3K, an ion implantation process and a drive-in process are performed to uniformly dope the epitaxial layer62with P-type dopant through the wide trench63aat a preset implanting depth. Consequently, a P-type doped region64is formed under the trench63a(seeFIG. 3L).

Then, as shown inFIG. 3M, a chemical vapor deposition (CVD) process is performed to form a fourth oxide layer67to cover the first oxide layer71, the third oxide layer73and the polysilicon structure66.

After the fourth oxide layer67is formed, a second photoresist layer B2with a second photoresist pattern is formed on the fourth oxide layer67(seeFIG. 3N).

Then, as shown inFIG. 3O, the fourth oxide layer67and the first oxide layer71uncovered by the second photoresist layer B2are removed by a contact etching process. Then, the second photoresist layer B2is removed. Meanwhile, the fourth oxide layer67is served as a second mask layer.

Then, as shown inFIG. 3P, a metal sputtering process is performed to form a metal sputtering layer80on the second mask layer, the surface62aof the semiconductor substrate60and the polysilicon structure66. In this embodiment, the metal sputtering layer80comprises a first metal layer81and a second metal layer82. The first metal layer81is made of titanium (Ti). The second metal layer82is sputtered on the first metal layer81. In addition, the second metal layer82is made of aluminum/silicon/copper (Al/Si/Cu) alloy.

After the first metal layer81of the metal sputtering layer80is in contact with the surface62aof the lightly-doped (N type) epitaxial layer62of the semiconductor substrate60, a Schottky contact is generated. Moreover, after this step is performed, a rapid thermal process (RTP) is optionally performed to facilitate formation of the Schottky contact.

Then, as shown inFIG. 3Q, a third photoresist layer B3with a third photoresist pattern is formed on the metal sputtering layer80. Then, the metal sputtering layer80uncovered by the third photoresist layer B3(i.e. the right-side area of the wafer as shown inFIG. 3Q) is removed by an etching process. After the etching process is completed, the third photoresist layer B3is removed. The resulting structure is shown inFIG. 3R. In this step, the etching process is a metal etching process to remove the first metal layer81and the second metal layer82of the metal sputtering layer80uncovered by the third photoresist layer B3. Consequently, the surface of the fourth oxide layer67(i.e. the second mask layer) at the right-side area of the wafer is exposed. In practice, due to the over-etching effect of the metal etching process, the exposed fourth oxide layer67is partially removed. That is, the thickness of the exposed fourth oxide layer67is slightly shrunk (seeFIG. 3R).

The finished trench Schottky diode according to the second embodiment of the present invention is shown inFIG. 3R. The outer area I is the guard ring. The inner area II is the device area. The P-type doped region64of the guard ring is effective to reduce the leakage current of the trench Schottky diode and increase the reverse voltage thereof. The experiments demonstrate that the reverse voltage of the trench Schottky diode can reach 160V. In a case that the trench Schottky diode of the present invention has the size similar to the conventional trench Schottky diode, the leakage current can be reduced to 10 microamperes or less.

In the second embodiment of the present invention, the trench Schottky diode comprises a semiconductor substrate60, a plurality of P-type doped regions64, an oxide layer (including a first oxide layer71and a second oxide layer73after various etching processes), a plurality of polysilicon structures66, a second mask layer (i.e. the fourth oxide layer67) and a metal sputtering layer80. A plurality of trenches63aand63bare formed in the semiconductor substrate60. These trenches are classified into two types, i.e. first trenches63aand second trenches63b. The opening width of the first trench63ais wider than the opening width of the second trench63b. The P-type doped regions64are formed in the semiconductor substrate60and located under the first trenches63a. The oxide layer is formed on the sidewalls and the bottom surfaces of the trenches63aand63band formed on a part of a surface62aof the semiconductor substrate60. The polysilicon structures66are formed on the oxide layer within the second trenches63band formed on the sidewalls of the first trenches63a. The second mask layer67is formed on the polysilicon structures66within the first trenches63aand the oxide layer. The metal sputtering layer80is formed on a part of the surface62aof the semiconductor substrate60, the polysilicon structures66within the second trenches66and a part of the mask layer67.

From the above description, the trench Schottky diode manufactured according to the present invention comprises an outer area I (i.e. the guard ring) and an inner part II (i.e. the device area). Since the Schottky contact is located at the device area (or the inner part II), the guard ring (or the outer area I) is effective to isolate the Schottky contact from the external environment. In other words, the guard ring can minimize the possibility of causing the leakage current and increase the reverse voltage. Consequently, by the trench Schottky diode and the manufacturing method of the present invention, the problems encountered from the prior art will be obviated.