Wiring board

A wiring board includes: a core layer having a through hole therethrough and comprising a first surface and a second surface opposite to the first surface; a first wiring layer formed on the first surface of the core layer and having a first opening which is communicated with the through hole, wherein an opening area of the first opening is larger than that of the through hole in a plan view; an electronic component disposed in the through hole and the first opening and having a first surface, and a second surface opposite to the first surface, the electronic component further having a pair of terminal on the first surface thereof; and a first resin layer filled in the through hole, the first opening and a gap between the pair of terminals so as to cover the second surface and the side surface of the electronic component.

This application claims priority from Japanese Patent Application No. 2012-190381, filed on Aug. 30, 2012, the entire contents of which are herein incorporated by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to a wiring board.

2. Description of the Related Art

A manufacturing method of a wiring board is known in which a filling resin is formed by filling resin paste into a gap between a ceramic sub-core and a core main body by supplying the resin paste from a first major surface side of the ceramic sub-core and the core main body by press printing using a rubber squeegee (see JP-A-2006-339482, for example).

Incidentally, the ceramic sub-core is fixed to the core main body by curing resin paste in a state that one open end of a sub-core housing portion formed in the core main body is closed by a sheet member and the ceramic sub-core that has been placed in the sub-core housing portion through the other open end is fastened to the sheet member.

However, when the sheet member is removed in a state that the ceramic sub-core is fixed to the core main body by a filling resin obtained by curing the resin paste, the ceramic sub-core may be kept fastened to the sheet member and come off the core main body due to insufficient strength of fixing by the filling resin.

This problem may occur in a case that the strength of fixing by the filling resin is weaker than the strength of fastening by the sheet member. That is, this problem may occur when the strength of holding by the filling resin is insufficient.

A similar problem due to insufficient strength of holding may also occur in a wiring board when an electronic component such as a chip capacitor, instead of a ceramic sub-core, is fixed by a filling resin in an opening that is formed in the core main body.

SUMMARY OF THE INVENTION

One or more aspects of the present invention are to provide a wiring board, which can increase the strength of holding an electronic component.

According to one or more aspects of the present invention, there is provided a wiring board. The wiring board comprises: a core layer having a through hole therethrough and comprising a first surface and a second surface opposite to the first surface; a first wiring layer formed on the first surface of the core layer and having a first opening which is communicated with the through hole, wherein an opening area of the first opening is larger than that of the through hole in a plan view, an electronic component disposed in the through hole and the first opening and comprising: a first surface; a second surface opposite to the first surface; and a side surface between the first surface and the second surface, the electronic component further comprising a pair of terminals on the first surface thereof, wherein the first surface of the electronic component is located on a side of the first surface of the core layer and the second surface of the electronic component is located on a side of the second surface of the core layer; and a first resin layer filled in the through hole, the first opening and a gap between the pair of terminals so as to cover the second surface and the side surface of the electronic component.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be hereafter described with reference to the drawings. The same constituent items in the drawings are given the same reference symbol, and the redundant descriptions may be omitted.

Before description of a wiring board and a manufacturing method of a wiring board according to an embodiment of the present invention, a wiring board and a manufacturing method of a wiring board of Comparative Example will be described with reference toFIGS. 1A and 1B.

Comparative Example

FIGS. 1A and 1Bshow a wiring board50of Comparative Example.FIG. 1Bis a plan view andFIG. 1Ais a sectional view as viewed from the direction of arrows A1 inFIG. 1B.

As shown inFIG. 1A, the wiring board50of Comparative Example includes a core10, wiring layers11A and11B, wiring layers11A and11B, wiring layers12A-12D, a through-hole13A, a buried resin13B, a chip capacitor14, and an insulating layer15.

The wiring board50also includes an insulating layer16, via electrodes17A-17C, wiring layers18A-18D, via electrodes19A and19B, and wiring layers20A-20D.

In the following description, for the sake of convenience, surfaces drawn in each drawing on the top side and the bottom side of each member, layer, or the like will be referred to as a top surface and a bottom surface, respectively, and the terms “above,” “over,” “below,” and “under” will be used. However, the terms “top surface,” “bottom surface,” “above,” “over,” “below,” “under,” “top side,” and “bottom side” do not refer to a universal top-bottom relationship and merely indicate a top-bottom relationship in each drawing.

For example, the core10is a member produced by impregnating a glass fabric base member with an epoxy resin. Copper foils are bonded to the two respective surfaces of the core10. The two copper foils are patterned into the wiring layers11A and11B and the wiring layers12A-12D, respectively.

A though-hole10P is formed at the center in the width direction (the horizontal direction inFIGS. 1A and 1B) of the core10so as to penetrate through the core10in its thickness direction (the vertical direction inFIG. 1A). An opening11P and an opening12P are formed through the respective wiring layers11A and12B over and under the though-hole10P so as to be continuous with the though-hole10P.

The wiring layers11A and11B are metal layers that are formed on the top surface of the core10by, for example, patterning the copper foil bonded to the top surface of the core10.

The opening11P is formed at the center in the width direction (the horizontal direction inFIGS. 1A and 1B) of the wiring layer11A. The opening11P is formed over the though-hole10P so as to be continuous with the though-hole10P. The opening11P has the same size as the though-hole10P in a plan view, and occupies the same area as the though-hole10P in a plan view.

The through-hole13A is connected to the wiring layer11B from below, and the via electrode17A is connected to the wiring layer11B from above. The wiring layer11B is connected to the wiring layer12A by the through-hole13A, and is connected to the wiring layer18A by the via electrode17A. A connection portion11B1between the via electrode17A and the wiring layer11B is shown inFIG. 1B.

The wiring layers12A-12D are metal layers that are formed on the bottom surface of the core10by, for example, patterning the copper foil bonded to the bottom surface of the core10.

The through-hole13A is connected to the wiring layer12A from above, and the via electrode19A is connected to the wiring layer12A from below. The wiring layer12A is connected to the wiring layer11B via the through-hole13A, and is connected to the wiring layer20A by the via electrode19A.

The opening12P is formed at the center in the width direction (the horizontal direction inFIGS. 1A and 1B) of the wiring layer12B. The opening12P is formed under the though-hole10P so as to be continuous with the though-hole10P. The opening12P has the same size as the though-hole10P and the opening11P in a plan view, and occupies the same area as the though-hole10P and the opening11P in a plan view.

The via electrode19B is connected to the wiring layer12C from below, and the wiring layer12C is connected to the wiring layer20D by the via electrode19B.

The through-hole13A penetrates through the core10in its thickness direction and connects the top wiring layer11B and the bottom wiring layer12A. For example, the through-hole13A is formed by forming a through-hole through the core10and forming a copper plating film on the inner wall surface of the thus-formed through-hole.

The buried resin13B is formed by filling the inside space of the through-hole13A with resin.

The chip capacitor14is a chip-shaped capacitor having a chip body14A and terminals14B and14C. In the chip capacitor14, the terminals14B and14C are connected to a pair of internal electrodes (not shown), respectively, and a prescribed capacitance is thereby obtained. The chip body14A is formed by covering the pair of electrodes with resin.

Each of the terminals14B and14C of the chip capacitor14is formed on the top surface, a side surface, and the bottom surface of the chip body14A so as to extend continuously, and the terminals14B and14C are insulated from each other. On the top surface of the chip body14A, a gap (groove) is formed between the terminals14B and14C and is occupied by an insulating layer16D.

Two via electrodes17B are connected to the terminal14B from above, and two via electrodes17C are connected to the terminal14C from above. Connection portions14B1and14B2between the terminal14B and the two via electrodes17B are shown inFIG. 1B. Connection portions14C1and14C2between the terminal14C and the two via electrodes17C are also shown inFIG. 1B.FIG. 1Ais a sectional view that is taken by a plane passing through one of the two via electrodes17B and one of the two via electrodes17C and that is as viewed from the direction of arrows A1 inFIG. 1B.

The outlines of the via electrodes17B and17C shown inFIG. 1Bare those of the top surfaces of the via electrodes17B and17C each having a truncated cone shape. The outlines of the connection portions14B1,14B2,14C1, and14C2shown inFIG. 1Bare those of the bottom surfaces of the via electrodes17B and17C.

The insulating layer15is formed so as to cover the bottom surfaces of the wiring layers12A-12D which are formed on the bottom surface of the core10, and to fill the inside spaces of the though-hole10P and the openings11P and12P.

The insulating layer15is formed by filling the inside spaces of the though-hole10P and the openings11P and12P and covering the bottom surfaces of the wiring layers12A-12D with heat-melted resin. For example, the insulating layer15is formed by thermally curing an epoxy, polyimide, or like resin material by heating and pressurizing it.

Via holes which are to be filled with the respective via electrodes19A and19B are formed through the insulating layer15.

The insulating layer15may be made of a filling resin material for a build-up board.

The insulating layer16is formed on the core10, the wiring layers11A and11B, and the chip capacitor14. For example, the insulating layer16may be made of the same resin material as the insulating layer15(epoxy, polyimide, or like resin material).

Each of the insulating layers15and16may be a prepreg which is in what is called a B-stage (half-set state), for example. An example of the prepreg is a one produced by impregnating a woven or non-woven fabric of glass fiber, carbon fiber, or the like with an epoxy, polyimide, or like insulative resin which is preferably a thermosetting resin.

Via holes which are to be filled with the respective via electrodes17A-17C are formed through the insulating layer16.

A part (insulating layer16A) of the insulating layer16is formed on the top surface of the chip body14A of the chip capacitor14in the groove (gap) formed between the terminals14B and14C.

The via electrodes17A-17C are formed in the respective via holes that are formed through the insulating layer16, and the via electrode17A, the via electrodes17B, and the via electrodes17C are connected to the wiring layer11B and the terminals14B and14C, respectively. The wiring layers18A,18C, and18D are connected to the via electrode17A, the via electrodes17B, and the via electrodes17C, respectively. The via electrodes17A-17C are copper plating films, for example.

The wiring layers18A-18D are formed on the top surface of the insulating layer16. Among the wiring layers18A-18D, the wiring layers18A,18C, and18D are connected to the via electrode17A, the via electrodes17B, and the via electrodes17C, respectively. The wiring layers18A-18D are copper plating films, for example.

The wiring layers18C and18D are connected to the terminals14B and14C of the chip capacitor14. Therefore, the wiring layers18C and18D are connected to the pair of internal electrodes that are incorporated in the chip body14A of the chip capacitor14, and are used as interconnections or terminals for charge/discharge of the chip capacitor14.

The via electrodes19A and19B are formed in the respective via holes that are formed through the insulating layer15, and are connected to the respective wiring layers12A and12C. The wiring layers20A and20D are connected to the bottom surfaces of the via electrodes19A and19B, respectively. The via electrodes19A and19B are copper plating films, for example.

The wiring layers20A-20D are formed on the bottom surface of the insulating layer15. Among the wiring layers20A-20D, the wiring layers20A and20D are connected to the respective via electrodes19A and19B. The wiring layers20A-20D are copper plating films, for example.

The above-described wiring board50of Comparative Example is what is called a build-up board in which the chip capacitor14is incorporated in the core10.

Next, a manufacturing method of the wiring board50of Comparative Example will be described.

FIGS.2A1-2C2to FIGS.4A1-4C2illustrate a manufacturing process of the wiring board50of Comparative Example.

First, as shown in FIGS.2A1and2A2, a through-hole13A having a copper plating film is formed through a core10and the inside space of the through-hole13A is filled with a buried resin13B. Wiring layers11and12are bonded to the top surface and the bottom surface of the core10, respectively. In this example, the wiring layers11and12are copper foils.

Then, as shown in FIGS.2B1and2B2, a through-hole10P and openings11P and12P are formed through the core10and the wiring layers11and12, respectively. The through-hole10P and the openings11P and12P, which penetrate through the core10and the wiring layers11and12, respectively, can be formed simultaneously by one piece of processing using a router or a die press machine. Therefore, the through-hole10P and the openings11P and12P have the same size and occupy the same area in a plan view.

Then, as shown in FIGS.2C1and2C2, the wiring layers11and12are patterned into wiring layers11A and11B and wiring layers12A-12D, respectively. As shown in FIG.2C2, the wiring layer11B is circular in a plan view. The bottom surface of the wiring layer11B is connected to the through-hole13A.

Then, as shown in FIGS.3A1and3A2, a temporary bonding tape30is bonded to the wiring layers11A and11B. The bottom surface of the temporary bonding tape30is formed with an adhesive layer30A. Then, a chip capacitor14is inserted into the through-hole10P and the opening11P through the opening12P which is located on the bottom surface side of the core10, and is bonded to the bottom surface of the temporary bonding tape30. The adhesive layer30A is thicker than the wiring layers11A and11B and the terminals14B and14C.

In this state, the top surfaces of the terminals14B and14C of the chip capacitor14are flush with the top surfaces of the wiring layers11A and11B. The wiring layers11A and11B and the terminals14B and14C are buried in the adhesive layer30A in a depth that is equal to about a half of the thickness of the adhesive layer30A. Over the top surface of the chip body14A, a groove (gap)14D is formed between the terminals14B and14C and is filled with part of the adhesive layer30A.

Then, as shown in FIGS.3B1and3B2, resin material such as an epoxy, polyimide or the like is supplied to the inside spaces of the through-hole10P and the openings11P and12P and the bottom surfaces of the wiring layers12A-12D, and is heated and pressurized. As a result, resin material such as the epoxy, polyimide or the like is thermally cured and turns to an insulting layer15.

The through-hole10P and the openings11P and12P are filled with the insulting layer15.

Then, as shown in FIGS.3C1and3C2, the temporary bonding tape30is removed, whereby as shown in FIG.3C2the wiring layers11A and11B, a part of the core10(the portion between the wiring layers11A and11B), a part of the insulating layer15(the portion around the chip capacitor14), and a part of the chip capacitor14(the groove14D between the terminals14B and14C) are exposed.

Then, as shown in FIGS.4A1and4A2, an insulating layer16is formed by bonding resin material such as an epoxy, polyimide or the like to the wiring layers11A and11B, the part of the core10(the portion between the wiring layers11A and11B), the part of the insulating layer15(the portion around the chip capacitor14), and the part of the chip capacitor14(the groove14D between the terminals14B and14C). An insulating layer16D which is part of the insulating layer16is formed in the groove14D. The insulating layer16is also formed between the wiring layer11A and the terminals14B and14C of the chip capacitor14(in the opening11P in a depth that is approximately equal to the thickness of the wiring layer11A).

The insulating layer16is formed by heating and pressurizing resin material such as epoxy, polyimide or the like.

Then, as shown in FIGS.4B1and4B2, via holes16A-16C are formed through the insulating layer16and via holes15B and15C are formed through the insulating layer15.

The via holes15B and15C and16A-16C may be formed by laser processing, for example.

Then, as shown in FIGS.4C1and4C2, via electrodes17A-17C, wiring layers18A-18D, via electrodes19A and19B, and wiring layers20A-20D are formed. This may be done by forming copper plating films by plating, more specifically, by, for example, a semi-additive method.

The via electrode17A, the via electrodes17B, and the via electrodes17C are formed in the via hole16A, the via holes16B, the via holes16C, respectively, by a semi-additive method. The wiring layers18A-18D are formed continuously with the plating for forming the via electrodes17A-17C.

The via electrodes19A and19B are formed in the respective via holes15B and15C by a semi-additive method. The wiring layers20A-20D are formed continuously with the plating for forming the via electrodes19A and19B.

A wiring board50of Comparative Example is thus completed.

Incidentally, in the manufacturing method of the wiring board50of Comparative Example, the following problem arises in the transition from the state of FIG.3B1to the state of FIG.3C1. This problem will be described below with reference toFIGS. 5A and 5B.

FIGS. 5A and 5Billustrate a problem of the manufacturing method of the wiring board50of Comparative Example.

FIG. 5Ais an enlarged sectional view of the chip capacitor14and its neighborhood shown in FIG.3B1.

The temporary bonding tape30is peeled off the surfaces of the wiring layers11A and11B in the state that as shown inFIG. 5Athe chip capacitor14is bonded to the temporary bonding tape30and the opening11P, the through-hole10P, and the opening12P are sealed by the insulating layer15.

In this state, the top surface of the chip capacitor14is bonded to the adhesive layer30A and its side surfaces are held by that part of the insulating layer15which fills the opening11P and the through-hole10P. That is, the chip capacitor14is held by the insulating layer15in the two side regions of the three regions indicated by broken-line ellipses inFIG. 5Aand is bonded to the adhesive layer30A in the other, central region.

When the temporary bonding tape30is peeled off the surfaces of the wiring layers11A and11B in this state, the following problem arises if the adhesion between the adhesive layer30A and the chip capacitor14exceeds the strength of holding the chip capacitor14by the insulating layer15.

As shown inFIG. 5B, the chip capacitor14may come off the insulating layer15being kept held by (bonded to) the temporary bonding tape30instead of being kept held by the insulating layer15. This results from the fact that the adhesion between the adhesive layer30A and the chip capacitor14exceeds the strength of holding the chip capacitor14by the insulating layer15.

A part of the insulating layer15which fills the through-hole10P holds the side surfaces of the chip capacitor14. Since the opening11P has the same size as the though-hole10P, the strength for the insulating layer to hold the chip capacitor14may be insufficient near the opening11P.

Therefore, the chip capacitor14may come off the insulating layer15as shown inFIG. 5Bwhen the temporary bonding tape30is removed, if the strength of holding of the chip capacitor14by the insulating layer15is weaker than the adhesion between the adhesive layer30A and the chip capacitor14.

If the chip capacitor14comes off the insulating layer15, a resulting wiring board50is unusable, that is, defective. As such, in the wiring board50of Comparative Example, a defective product may be manufactured through the above-described manufacturing process.

The same problem may also arise in the case where another kind of electronic component such as a semiconductor device is used instead of the chip capacitor14.

In summary, the wiring board50of Comparative Example has the problem that the strength of holding of an electronic component may be insufficient.

The wiring board50of Comparative Example has another problem that electric connection trouble may occur if the position of the chip capacitor14in the opening11P and the through-hole10P is deviated. This problem will be described below with reference toFIG. 6.

FIG. 6shows another problem of the manufacturing process of the wiring board50of Comparative Example.

FIG. 6is an enlarged sectional view, in the manufacturing step of FIG.4C1, of the chip capacitor14and its neighborhood which may cause electric connection trouble.

In this example, the problem shown inFIG. 5Bhas not occurred, that is, the temporary bonding tape30has been removed correctly and the chip capacitor14is held by the insulating layer15in the opening11P and the through-hole10P.

However, in the example ofFIG. 6, the chip capacitor14is deviated rightward from its position shown in FIG.4C1and the terminal14C is in contact with the wiring layer11A as shown in a broken-line circle. The terminal14C should only be connected to the via electrodes17C (see FIG.4C1) and should not be connected to the wiring layer11A.

If the position of the chip capacitor14is deviated and the terminal14C is connected to wiring layer11A, the chip capacitor14cannot be charged or discharged correctly, resulting in a problem that the reliability of the wiring board50is lowered.

As described above, the wiring board50of Comparative Example has the problems that the strength of holding of an electronic component may be insufficient and that its reliability is lowered.

An object of the embodiment described below is therefore to provide a wiring board that is increased in the strength of holding of an electronic component as well as in reliability.

Embodiment

FIGS. 7A-7Dare sectional views and a plan view of a wiring board100according to the embodiment.FIG. 7Bis a plan view andFIG. 7Ais a sectional view as viewed from the direction of arrows B1 inFIG. 7B.FIG. 7Cis a sectional view of a structure which is obtained by adding solder resist layers40A and40B to the structure ofFIG. 7A.FIG. 7Dis a sectional view of a structure which is obtained by adding an LSI (large scale integrated circuit) chip42to the structure ofFIG. 7C.

The wiring board100according to the embodiment is different from the wiring board50of Comparative Example in that an opening111P of a wiring layer111A which corresponds to the wiring layer11A of the wiring board50of Comparative Example is larger than and includes the top open end of a though-hole10P of a core10in a plan view.

Likewise, an opening112P of a wiring layer112B which corresponds to the wiring layer12B of the wiring board50of Comparative Example is larger than and includes the bottom open end of the though-hole10P of the core10in a plan view.

The other constituent elements of the wiring board100are the same as the corresponding ones of the wiring board50of Comparative Example, and hence are given the same reference symbols as the latter and will not be described in detail.

The wiring board100includes a core10, wiring layers111A and111B, wiring layers111A and111B, wiring layers112A-112D, a through-hole13A, a buried resin13B, a chip capacitor14, and an insulating layer15.

The wiring board100also includes an insulating layer16, via electrodes17A-17C, wiring layers18A-18D, via electrodes19A and19B, and wiring layers20A-20D.

In the following description, for the sake of convenience, surfaces drawn in each drawing on the top side and the bottom side of each member, layer, or the like will be referred to as a top surface and a bottom surface, respectively, and the terms “above,” “over,” “below,” and “under” will be used. However, the terms “top surface,” “bottom surface,” “above,” “over,” “below,” “under,” “top side,” and “bottom side” do not refer to a universal top-bottom relationship and merely indicate a top-bottom relationship in each drawing.

For example, the core10is a member produced by impregnating a glass fabric base member with an epoxy resin. Copper foils are bonded to the two respective surfaces of the core10. The two copper foils are patterned into the wiring layers111A and111B and the wiring layers112A-112D, respectively.

The core10is an example of a core layer. The wiring layers111A and111B are examples of a first wiring layer. The wiring layers112A-112D are examples of a second wiring layer.

An opening111P is formed through the wiring layer111A so as to be located over the though-hole10P. An opening112P is formed through the wiring layer112B so as to be located under the though-hole10P.

The opening111P is larger than the top open end of the though-hole10P. The opening111P includes the top open end of the though-hole10P of the core10in a plan view. The opening111P is an example of a first opening.

The opening112P is larger than the bottom open end of the though-hole10P of the core10. The opening112P includes the bottom open end of the though-hole10P of the core10in a plan view. The opening112P is an example of a second opening.

The wiring layers111A and111B are metal layers that are formed on the top surface of the core10by, for example, patterning the copper foil bonded to the top surface of the core10.

Between the wiring layers111A and111B, the wiring layer111B is the same as the wiring layer11B of the wiring board50of Comparative Example.

The opening111P is formed at the center in the width direction (the horizontal direction inFIGS. 7A-7D) of the wiring layer111A. As described above, the opening111P is larger than and includes the top open end of the though-hole10P of the core10in a plan view. That is, the opening111P includes the though-hole10P in a plan view.

The through-hole13A is connected to the wiring layer111B from below, and the via electrode17A is connected to the wiring layer111B from above. The wiring layer111B is connected to the wiring layer112A by the through-hole13A, and is connected to the wiring layer18A by the via electrode17A. A connection portion111B1between the via electrode17A and the wiring layer111B is shown inFIG. 7B. The difference between the sizes of the opening111P and the though-hole10P will be described later in a description of a manufacturing process.

The wiring layers112A-112D are metal layers that are formed on the bottom surface of the core10by, for example, patterning the copper foil bonded to the bottom surface of the core10.

Among the wiring layers112A-112D, the wiring layers112A,112C, and112D are the same as the wiring layers12A,12C, and12D of the wiring board50of Comparative Example.

The wiring later112A is connected to the wiring layer111B by the through-hole13A, and is connected to the wiring layer20A by the via electrode19A.

The opening112P is formed at the center in the width direction (the horizontal direction inFIGS. 7A-7D) of the wiring layer112B. The opening112P is formed under the though-hole10P. The opening112P is larger than and includes the bottom open end of the though-hole10P in a plan view.

The via electrode19B is connected to the wiring layer112C from below, and the wiring layer112C is connected to the wiring layer20D by the via electrode19B.

The through-hole13A penetrates through the core10in its thickness direction and connects the top wiring layer111B and the bottom wiring layer112A.

The insulating layer115is formed so as to cover the bottom surfaces of the wiring layers112A-112D which are formed on the bottom surface of the core10, and to fill the inside spaces of the though-hole10P and the openings111P and112P.

The insulating layer115is formed by filling the inside spaces of the though-hole10P and the openings111P and112P and covering the bottom surfaces of the wiring layers112A-112D with heat-melted resin. For example, the insulating layer115is formed by thermally curing an epoxy, polyimide, or like resin material by heating and pressurizing it.

Part (insulating layer115A) of the insulating layer115is formed on the top surface of the chip body14A of the chip capacitor14in a groove (gap)14D formed between the terminals14B and14C. The top surface of the chip capacitor14is an example of a first surface, and the bottom surface of the chip capacitor14is an example of a second surface.

In the embodiment, the opening111P is larger than and includes the though-hole10P in a plan view. Therefore, part (extension115D) of the insulating layer115extends outward alongside the outer periphery of the opening111P so as to be shaped like a rectangular ring in a plan view. The extension115D is located outside the top open end of the though-hole10P in a plan view. The insulating layers115and115A and the extension115D are examples of a first resin layer.

Via holes which are to be filled with the respective via electrodes19A and19B are formed through the insulating layer115.

The insulating layer16is formed on the core10, the wiring layers111A and111B, and the chip capacitor14. For example, the insulating layer16may be made of an epoxy, polyimide, or like resin material. The insulating layer16is an example of a second resin layer. The insulating layer16(an example of the second resin layer) is made of a different resin than the insulating layer115(an example of the first resin layer).

The insulating layer16may be a prepreg which is in what is called a B-stage (half-set state), for example. An example of the prepreg is produced by impregnating a woven or non-woven fabric such as glass fiber, carbon fiber or the like with insulating resin such as an epoxy, polyimide or the like which is preferably a thermosetting resin. The insulating layer16need not always contain a woven or non-woven fabric such as glass fiber, carbon fiber or the like.

Via holes which are to be filled with the respective via electrodes17A-17C are formed through the insulating layer16.

The via electrodes17A-17C are formed in the respective via holes that are formed through the insulating layer16, and the via electrode17A, the via electrodes17B, and the via electrodes17C are connected to the wiring layer111B and the terminals14B and14C, respectively. The wiring layers18A,18C, and18D are connected to the via electrode17A, the via electrodes17B, and the via electrodes17C, respectively. The via electrodes17A-17C are copper plating films, for example.

The via electrodes19A and19B are formed in the respective via holes that are formed through the insulating layer115, and are connected to the respective wiring layers112A and112C. The wiring layers20A and20D are connected to the bottom surfaces of the via electrodes19A and19B, respectively. The via electrodes19A and19B are copper plating films, for example.

The wiring layers20A-20D are formed on the bottom surface of the insulating layer115. Among the wiring layers20A-20D, the wiring layers20A and20D are connected to the respective via electrodes19A and19B. The wiring layers20A-20D are copper plating films, for example.

The above-described wiring board100according to the embodiment is what is called a build-up board in which the chip capacitor14is incorporated in the core10.

As shown inFIG. 7C, the wiring board100may further include solder resist layers40A and40B which are formed on the top surfaces of the wiring layers18A-18D and the bottom surfaces of the wiring layers20A-20D, respectively.

The solder resist layer40A is formed to expose portions of the top surfaces of the wiring layers18A-18D. Those portions of the wiring layers18A-18D which are exposed through the solder resist layer40A are used as terminals.

The solder resist layer40B is formed so as to expose portions of the bottom surfaces of the wiring layers20A-20D. Those portions of the wiring layers20A-20D which are exposed through the solder resist layer40B are used as terminals.

As shown inFIG. 7D, an LSI chip42is mounted on the wiring board100so as to be connected, via bumps41A, to those portions (terminals) of the wiring layers18A-18D which are exposed through the solder resist layer40A.

As shown inFIG. 7D, bumps41B are connected to those portions (terminals) of the wiring layers20A-20D which are exposed through the solder resist layer40B.

In this manner, the LSI chip42can be mounted on the wiring board100according to the embodiment.

Next, a manufacturing method of the wiring board100according to the embodiment will be described.

FIGS.8A1-8C2to FIGS.10A1-10C2illustrate a manufacturing process of the wiring board100according to the embodiment.

First, as shown in FIGS.8A1and8A2, a through-hole13A having a copper plating film is formed through a core10and the inside space of the through-hole13A is filled with a buried resin13B. Wiring layers111and112are bonded to the top surface and the bottom surface of the core10, respectively. In this example, the wiring layers111and112are copper foils.

Then, as shown in FIGS.8B1and8B2, the wiring layers111and112are patterned into wiring layers111A and111B and wiring layers112A-112D, respectively.

At this time, openings111P and112P are formed through the respective wiring layers111and112. The openings111P and112P have the same size and occupy the same area in a plan view.

As shown in FIG.8B2, the wiring layer111B is circular in a plan view. The bottom surface of the wiring layer111B is connected to the through-hole13A.

The wiring layers111A and111B, the wiring layers112A-112D, and the openings111P and112P are formed by patterning by wet-etching the wiring layers111and112using photoresist layers.

Then, as shown in FIGS.8C1and8C2, a through-hole10P is formed through the core10. The through-hole10P, which penetrate through the core10in its thickness direction, can be formed using a router or a die press machine.

The through-hole10P is smaller than and is included in each of the openings111P and112P in a plan view. The through-hole10P and the openings111P and112P are examples of cavities.

Then, as shown in FIGS.9A1and9A2, a temporary bonding tape30is bonded to the wiring layers111A and111B. The bottom surface of the temporary bonding tape30is formed with an adhesive layer30B. The temporary bonding tape30is an example of a tape member. The adhesive layer30B is thinner than the adhesive layer30A which is used in Comparative Example. The adhesive layer30B is formed by applying adhesive to the bottom surface of the temporary bonding tape30by such an amount that the adhesive does not flow into the groove14D of a chip capacitor14even when the adhesive is pressed in the thickness direction at the time of bonding of the chip capacitor14to the bottom surface of the temporary bonding tape30. For example, the adhesive layer30B is thinner than any of the wiring layers111A and111B and the terminals14B and14C. For example, the thickness of the adhesive layer30B may be about a half of the adhesive layer30A which is used in Comparative Example.

After bonding the temporary bonding tape30to the wiring layers111A and111B, the chip capacitor14is inserted into the through-hole10P and the opening111P through the opening112P which is located on the bottom surface side of the core10, and is bonded to the bottom surface of the temporary bonding tape30.

In this state, the top surfaces of the terminals14B and14C of the chip capacitor14are flush with the top surfaces of the wiring layers111A and111B. Over the top surface of the chip body14A, the groove (gap)14D is formed between the terminals14B and14C. The groove14D is an example of a first groove. In the state of FIGS.9A1and9A2, no part of the adhesive layer30B has flown into the groove14D and nothing is formed in the groove14D, that is, the groove14D is a cavity.

Then, as shown in FIGS.9B1and9B2, an epoxy, polyimide, or like resin material is supplied to the inside spaces of the through-hole10P and the openings11P and12P and the bottom surfaces of the wiring layers12A-12D, and is heated and pressurized. As a result, the epoxy, polyimide, or like resin material is set thermally and turns to an insulting layer115.

The through-hole10P and the openings111P and112P are filled with the insulting layer115, and the groove14D (see FIG.9A1) which is located over the top surface of the chip body14A is filled with an insulating layer115A.

An epoxy, polyimide, or like resin material is charged into the groove14D by pressurization, whereby the insulating layer115A is formed. The insulating layer115A is formed like a bridge on the top surface of the chip body14A between the terminals14B and14C.

In the embodiment, the opening111P is larger than and includes the through-hole10P in a plan view. Therefore, an extension115D which is a part of the insulating layer115extends outward alongside the outer periphery of the opening111P so as to be shaped like a rectangular ring in a plan view. The extension115D is located outside the top open end of the though-hole10P in a plan view.

In the step shown in FIGS.9B1and9B2, the though-hole10P and the openings111P and112P are closed by the core10and the wiring layers111A and112B in a plan view, respectively, and are closed by the temporary bonding tape30above. Therefore, no resin material such as the epoxy, polyimide or the like leaks to the top surfaces of the wiring layers111A and112B.

Then, as shown in FIGS.9C1and9C2, the temporary bonding tape30is removed, whereby as shown in FIG.9C2the wiring layers111A and111B, part of the core10(the portion between the wiring layers111A and111B), part of the insulating layer115(the portion around the chip capacitor14), the insulating layer115A, and the extension115D are exposed.

Then, as shown in FIGS.10A1and10A2, an insulating layer16is formed by bonding an epoxy, polyimide, or like resin material to the wiring layers111A and111B, the part of the core10(the portion between the wiring layers111A and111B), the part of the insulating layer115(the portion around the chip capacitor14), the insulating layer115A, and the extension115D.

The insulating layer16is formed by heating and pressurizing resin material such as the epoxy, polyimide or the like.

Then, as shown in FIGS.10B1and10B2, via holes16A-16C are formed through the insulating layer16and via holes115B and115C are formed through the insulating layer115.

The via holes115B and115C and16A-16C may be formed by laser processing, for example.

Then, as shown in FIGS.10C1and10C2, via electrodes17A-17C, wiring layers18A-18D, via electrodes19A and19B, and wiring layers20A-20D are formed. This may be done by forming copper plating films by plating, more specifically, by, for example, a semi-additive method.

The via electrode17A, the via electrodes17B, and the via electrodes17C are formed in the via hole16A, the via holes16B, the via holes16C, respectively, by a semi-additive method. The wiring layers18A-18D are formed continuously with the plating for forming the via electrodes17A-17C.

The via electrodes19A and19B are formed in the respective via holes115B and115C by a semi-additive method. The wiring layers20A-20D are formed continuously with the plating for forming the via electrodes19A and19B.

A wiring board100according to the embodiment is thus completed.

Advantages of the wiring board100according to the embodiment will be described below with reference toFIGS. 11A and 11BandFIG. 12.

FIGS. 11A and 11Billustrate an advantage of the manufacturing method of the wiring board100according to the embodiment.FIG. 11Ais an enlarged sectional view of the chip capacitor14and its neighborhood shown in FIG.9B1.FIG. 11Bshows a state that the temporary bonding tape30has been peeled off.

The temporary bonding tape30is peeled off the surfaces of the wiring layers111A and111B in the state that as shown inFIG. 11Athe chip capacitor14is bonded to the temporary bonding tape30and the opening111P, the through-hole10P, and the opening112P are sealed by the insulating layer115.

In this state, the top surface of the chip capacitor14is held by the insulating layer115A and its side surfaces are held by the insulating layer115which fills the opening111P and the through-hole10P.

The opening111P is larger than and includes the through-hole10P in a plan view. Therefore, the insulating layer115has the extension115D in the outer periphery of the opening111P (outside the though-hole10P in a plan view).

That is, the chip capacitor14is held by the insulating layers115and115A and the extension115D in the five regions indicated by broken-line ellipses inFIG. 11A.

Because of the presence of the extension115D which is shaped like a rectangular ring in a plan view, the side surfaces of a top portion of the chip capacitor14are held more strongly than in Comparative Example.

The length and the thickness of the extension115D which extends outward from the though-hole10P in a plan view may be set at proper values so that the strength of holding of the chip capacitor14by the insulating layers115and115A and the extension115D exceeds the adhesion of the temporary bonding tape30.

Therefore, when the temporary bonding tape30is peeled off the surfaces of the wiring layers111A and111B in this state, the strength of holding of the chip capacitor14by the insulating layers115and115A and the extension115D is not weaker than the adhesion of the temporary bonding tape30.

Therefore, when the temporary bonding tape30is peeled off in the state of FIG.9B1, as shown in FIGS.9C1and11B, only the temporary bonding tape30can be peeled off with the chip capacitor14kept held by the insulating layers115and115A and the extension115D.

That is, unlike in Comparative Example, an event that the chip capacitor14comes off the insulating layer115in a state that it is kept bonded to the temporary bonding tape30can be prevented. This is because the chip capacitor14is held by the insulating layers115and115A and the extension115D in the five regions indicated by the broken-line ellipses inFIG. 11A.

In the wiring board100according to the embodiment, the bridge-shaped insulating layer115A is reinforced by reinforcing, by the extension115D, a portion of the insulating layer115which exists around the side surfaces of a top portion of the chip capacitor14.

The insulating layer115extends like a bridge in the groove14D over the top surface of the chip capacitor14, and the side surfaces and the bottom surface of the chip capacitor14are held by the insulating layer115. That is, most of the bottom surface, the side surfaces, and the top surface of the chip capacitor14are directly held by the insulating layers115and115A. This prevents the chip capacitor14from being pulled out when the temporary bonding tape30is peeled off in a manufacturing process.

As is understood from the above discussion, in the wiring board100according to the embodiment, the chip capacitor14can be held with sufficient strength by the insulating layers115and115A and the extension115D. As a result, in the manufacturing method of the wiring board100according to the embodiment, the probability of occurrence of defective products can be made low.

Next, another advantage of the wiring board100according to the embodiment will be described with reference toFIG. 12.

FIG. 12illustrates another advantage of the wiring board100according to the embodiment.

The chip capacitor14is held in the opening111P and the through-hole10P by the insulating layers115and115A and the extension115D.

However, in the example ofFIG. 12, the chip capacitor14is deviated rightward from its position shown in FIG.10C1, as in the example described with reference toFIG. 6in Comparative Example.

In the wiring board100according to the embodiment, the opening111P of the wiring layer111A is larger than and includes the through-hole10P in a plan view. Therefore, part of the extension115D is formed on the destination side of the offset of the chip capacitor14with respect to the through-hole10P.

Therefore, as shown inFIG. 12, even if the position of the chip capacitor14is deviated rightward, the terminal14C of the chip capacitor14does not come into contact with the wiring layer111A.

The same is true of a case that the position of the chip capacitor14is deviated leftward inFIG. 12; the terminal14B does not come into contact with the wiring layer111A. Likewise, even if the position of the chip capacitor14is deviated toward the viewer's side or the deep side inFIG. 12, the terminal14B or14C does not come into contact with the wiring layer111A.

Therefore, in the wiring board100according to the embodiment, even if the position of the chip capacitor14is deviated, electric connection trouble of the chip capacitor14does not occur unlike in the wiring board50of Comparative Example. As such, the embodiment can provide a highly reliable wiring board100.

As described above, the wiring board100according to the embodiment provides the advantages that sufficient strength of holding of an electronic component and high reliability can be secured.

Thus, the embodiment can provide a wiring board100that is increased in the strength of holding of an electronic component as well as in reliability.

Furthermore, in manufacturing process of the wiring board100according to the embodiment, the thickness of the adhesive layer30B of the temporary bonding tape30may be about a half of that of the adhesive layer30A which is used in Comparative Example. The use of such a thin adhesive layer30B contributes to reduction of the manufacturing cost.

Whereas in the embodiment the wiring board100incorporates the chip capacitor14as an example electronic component, the wiring board100may incorporate another kind of electronic component such as a semiconductor device.

In the above-described embodiment, the opening112P is larger than and includes the bottom open end of the through-hole10P of the core10in a plan view. However, where as shown inFIG. 7Athe vertical range where the chip capacitor14exists is included in the vertical range where the through-hole10P plus the wiring layer111A exist and the bottom surfaces of the terminals14B and14C are located higher than the wiring layer112B, the opening112P may have the same size and occupy the same area as the through-hole10P in a plan view.

In the embodiment, no reference was made of the direction of peeling of the temporary bonding tape30. For example, the temporary bonding tape30(assumed to have a rectangular shape in a plan view) may be peeled off in such a manner as to be pulled up starting from its one sideline. When the temporary bonding tape30is peeled off, pulling force acts on the chip capacitor14from the temporary bonding tape30via the terminals14B and14C.

In this case, peeling off the temporary bonding tape30in the direction in which the insulating layer115A extends between the terminals14B and14C of the chip capacitor14(the vertical direction in FIG.9B2) is preferable to peeling it off in the horizontal direction in FIG.9B2.

This is because where the temporary bonding tape30is peeled off in the extending direction of the insulating layer115A (the vertical direction in FIG.9B2), the force acting on the chip capacitor14from the temporary bonding tape30can be made approximately constant in the interval where the temporary bonding tape30is in contact with the top surfaces of the insulating layers115and115A and the extension115D.

In contrast, where the temporary bonding tape30is peeled off in the horizontal direction in FIG.9B2, the force acting on the chip capacitor14from the temporary bonding tape30varies to a relatively large extent in the interval where the temporary bonding tape30is in contact with at least one of the top surfaces of the insulating layers115and115A and the extension115D, depending on whether it is in contact with the insulating layer115A.

It is therefore preferable to design the wiring board100so that the peeling direction of the temporary bonding tape30coincides with the extending direction of the insulating layer115A.

However, if the strength of holding the chip capacitor14by the insulating layers115and115A and the extension115D can be made so high that the peeling direction of the temporary bonding tape30is irrelevant, it is not necessary that the peeling direction of the temporary bonding tape30coincide with the extending direction of the insulating layer115A.

It is preferable to design the wiring board100so that the ratio of the sum of the widths of the insulating layers115and115A and the extension115D in the direction perpendicular to the peeling direction of the temporary bonding tape30to that of the terminals14B and14C in the same direction is made as large as possible. Alternatively, it is preferable to design the wiring board100so that the sum of the widths of the insulating layers115and115A and the extension115D in the direction perpendicular to the peeling direction of the temporary bonding tape30is made as large as possible.

This is because the force acting on the chip capacitor14from the temporary bonding tape30can be reduced if the temporary bonding tape30is peeled off in such a direction that the sum of the widths of the insulating layers115and115A and the extension115D in the direction perpendicular to it is large, whereby the chip capacitor14can be prevented from pulled out by the temporary bonding tape30.

If the aspect ratios of the insulating layer115and the extension115D are different from each other (e.g., see FIG.9B2), satisfactory results would be obtained by peeling the temporary bonding tape30in the direction in which their shorter sidelines extend.

However, if the strength of holding of the chip capacitor14by the insulating layers115and115A and the extension115D can be made so high that the peeling direction of the temporary bonding tape30is irrelevant, it is not necessary to set the above-described ratio of the sum of their widths large.

The epoxy, polyimide, or like resin material of the insulating layers115and115A and the extension115D may be different from that of the insulating layer16in melt viscosity or the coefficient of thermal expansion (CTE).

For example, the epoxy, polyimide, or like resin material of the insulating layers115and115A and the extension115D may be lower in melt viscosity and larger in the coefficient of thermal expansion that of the insulating layer16.

In this case, gaps can be filled efficiently that might otherwise be formed between the insulating layers115and115A and the extension115D in the opening111P, the groove14D, etc. and the insulating layer16when the insulating layer16is formed with resin material such as the epoxy, polyimide or the like after the insulating layers115and115A and the extension115D is formed with resin material such as the epoxy, polyimide or the like.

Furthermore, since the insulating layer16is formed with resin material such as an epoxy, polyimide or the like that is softer and has a larger coefficient of thermal expansion after the formation of the insulating layers115and115A and the extension115D, the flatness of the wiring board100as a whole can be increased.

In the wiring board100according to the embodiment, the chip capacitor14is disposed closer to one surface (the top surface) of the core10. Where the LSI chip42is mounted on the one surface of the core10(seeFIG. 7D), the distance between the chip capacitor14and the LSI chip42can be made short and hence the performance of the LSI chip42can be enhanced.

Grooves that communicate with the opening111P may be formed through the wiring layer111A.

FIG. 13is a plan view of a part of a wiring board100A according to a modification of the embodiment.FIG. 13corresponds to FIG.8C2which shows a manufacturing step.

As shown inFIG. 13, grooves111C1,111C2,111D1, and111D2may be formed through the wiring layer111A so as to communicate with the opening111P (extend from the four respective sidelines of the opening111P). Portions of the top surface of the core10are exposed at the bottoms of the respective grooves111C1,111C2,111D1, and111D2. The grooves111C1,111C2,111D1, and111D2are examples of a second groove.

The grooves111C1and111C2are formed so as to extend straightly outward from the two respective shorter sidelines of the opening111P which is generally rectangular in a plan view, in the directions that are perpendicular to those sidelines.

The grooves111D1and111D2are formed so as to extend in L-shaped form from the two respective longer sidelines of the opening111P.

Roots111D1A and111D2A where the grooves111D1and111D2are connected to the opening111P, respectively, are located at such positions as to be aligned with the groove14D of the chip capacitor14in the manufacturing step of FIGS.9A1and9A2. That is, the roots111D1A and111D2A of the grooves111D1and111D2are located on respective extensions of the groove14D. In other words, the line connecting the roots111D1A and111D2A of the grooves111D1and111D2is in the same direction as the extending direction of the groove14D.

The grooves111D1and111D2can serve as spaces for receiving an excess part of an epoxy, polyimide, or like resin material that is charged into the space closed by the wiring layer111A and the temporary bonding tape30by pressurization when the insulating layers115and115A and the extension115D are formed with the epoxy, polyimide, or like resin material (see FIGS.9B1and9B2).

If high charging pressure is exerted on the groove14D located between the terminals14B and14C of the chip capacitor14when resin is charged into the groove14D, the chip capacitor14directly pushes up the temporary bonding tape30and hence is likely separated from the temporary bonding tape30. The grooves111D1and111D2are formed in the vicinities of the groove14D to facilitate escape of the pressure that is exerted on the groove14D.

Since resin goes into the groove14D in the vertical direction inFIG. 13as indicated by an arrow, the groove14D which extends in this direction facilitates escape of the pressure more.

As such, the grooves111C1,111C2,111D1, and111D2can receive an excess part of an epoxy, polyimide, or like resin material when it is charged into the opening111P by pressurization.

In this action, since the grooves111C1and111C2are formed at the positions that are most distant from the groove14D of the chip capacitor14, they can receive an excess part of the epoxy, polyimide, or like resin material efficiently at the two shorter sidelines of the opening111P.

Since the roots111D1A and111D2A of the grooves111D1and111D2which are located on the respective extensions of the groove14D, they can receive an excess part of the epoxy, polyimide, or like resin material efficiently.

FIG. 13shows the mode in which the grooves111C1,111C2,111D1, and111D2are terminated at the deepest positions and formed independently of each other. Alternatively, at least two (e.g., three) of them may communicate with each other. All of the grooves111C1,111C2,111D1, and111D2may communicate with each other.

The wiring board and its manufacturing method according to the illustrative embodiment of the invention have been described above. However, the invention is not limited to the embodiment which has been disclosed above in a specific manner and various changes and modifications are possible without departing from the scope of the claims.