Semiconductor device and method of fabricating the same

An SiC film, a porous silica film as an interlayer dielectric film, another SiC film, an SiO2 film, an SiN film, and an antireflection film are formed in this order on an interlayer dielectric film and Cu film. The antireflection film is coated with an organic photosensitive ArF resist, and the resist is exposed and developed to form a resist mask in which a wiring trench pattern is formed. A trench is then formed in the porous silica film, the latter SiC film, the SiO2 film, and the SiN film. Plasma processing using a hydrogen-containing gas is performed on the side surfaces of the porous silica film, thereby forming a modified layer. The exposed portion of the former SiC film is etched away to allow the trench to reach the Cu film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-280155, filed on Jul. 25, 2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device suited to the formation of a wiring layer, and a method of fabricating the semiconductor device.

2. Description of the Related Art

Recently, a method using a three-layered hard mask is used when a wiring layer is to be formed by using the damascene method.FIGS. 8A to 8Dare sectional views showing a conventional semiconductor device fabrication method using the damascene method in order of steps.

In this conventional fabrication method, as shown inFIG. 8A, a Cu film102is buried in an interlayer dielectric film101. On these films, an SiC film103as a barrier film, a porous silica film104, an SiC film105as a cap film, an SiO2film106, an SiN film107, and an antireflection film108such as a BARC (Bottom Anti Reflection Coating) are formed in this order. In addition, a resist mask109made of an ArF resist is formed.

Subsequently, as shown inFIG. 8B, the resist mask109is used as a mask to etch the antireflection film108and SiN film107. Then, the resist mask109and antireflection film108are removed by ashing. After that, the SiN film107is used as a mask to etch the SiO2film106. The SiO2film106is then used as a mask to etch the SiC film105and remove the SiN film107.

As shown inFIG. 8C, the SiO2film106is used as a mask to etch the porous silica film104.

As shown inFIG. 8D, the SiO2film106is used as a mask to etch the SiC film103. After that, an interconnection is formed.

Conventionally, Cu interconnections are formed by the damascene method as described above, and fine low-resistance interconnections are obtained.

Unfortunately, in the above-mentioned damascene method, as shown inFIG. 8D, when the SiC film103as a barrier film is etched, the porous silica film104as a low-dielectric-constant film is processed by side etching. Consequently, the side portions of the porous silica film104recede. This phenomenon appears not only for a porous silica film but also for other inorganic low-dielectric-constant films, e.g., an SiOC film, SiOCN film, porous SiOC film, and porous SiOCN film.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device by which desired characteristics can be obtained by preventing side etching of an interlayer dielectric film when a trench (wiring trench) is formed, and a method of fabricating the semiconductor device.

The present inventor made extensive studies to achieve the above object, and has reached the aspects of the invention described below.

In a first semiconductor device fabrication method according to the present invention, an SiC barrier film is formed over an interconnection, and an interlayer dielectric film containing Si, C, and O is formed over this SiC barrier film. A hole reaching the SiC barrier film is then formed in the interlayer dielectric film, and plasma processing using a hydrogen-containing gas is performed on the side surfaces of the interlayer dielectric film. The side surfaces are exposed to the hole. The SiC barrier film is etched to allow the hole to reach the interconnection. A conductive material is buried in the hole.

In a second semiconductor device fabrication method according to the present invention, an SiC barrier film is formed over an interconnection, and an interlayer dielectric film containing Si, C, and O is formed over this SiC barrier film. A hole reaching the SiC barrier film is then formed in the interlayer dielectric film, and plasma processing is performed on the side surfaces of the interlayer dielectric film. The side surfaces are exposed to the hole. Thereby an organic film is formed on the side surfaces of the interlayer dielectric film. The SiC barrier film is etched to allow the hole to reach the interconnection. A conductive material is buried in the hole.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. For the sake of convenience, the structure of each semiconductor device will be explained together with its fabrication method.

The first embodiment of the present invention will be described below.FIGS. 1A to 1Jare sectional views showing a method of fabricating a semiconductor device according to the first embodiment of the present invention in order of steps. In this embodiment, a semiconductor device is fabricated by using the single damascene method.

First, an element such as a transistor is formed on the surface of a semiconductor substrate (not shown). After that, an interlayer dielectric film (not shown) is formed on the element, and a contact plug is formed in this interlayer dielectric film. In addition, an interlayer dielectric film1is formed on this interlayer dielectric film, as shown inFIG. 1A. A Cu film2(a conductive layer such as an interconnection or via plug) is buried in the interlayer dielectric film1, and an SiC film3is formed as an etching stopper film (barrier film) on the interlayer dielectric film1and Cu film2. The thickness of the SiC film3is, e.g., 30 nm. A porous silica film4is then formed as an interlayer dielectric film on the SiC film3. The thickness of the porous silica film4is, e.g., 200 nm. The porous silica film4is a porous low-dielectric-constant insulating film.

An SiC film5is formed as a cap film (first hard mask) on the porous silica film4, and an SiO2film6is formed as a second hard mask. The thicknesses of the SiC film5and Sio2film6are 30 and 150 nm, respectively. Subsequently, an SiN film7is formed as a third hard mask on the SiO2film6. The thickness of the SiN film7is, e.g., 70 nm. After that, an antireflection film8necessary for patterning is formed on the SiN film7. The antireflection film8is, e.g., an organic BARC. The antireflection film8is then coated with an organic photosensitive ArF resist, and the resist is exposed and developed to form a resist mask9in which a wiring trench pattern is formed. The width of a wiring trench is, e.g., about 100 nm. The thicknesses of the antireflection film8and resist mask9are, e.g., 80 and 300 nm, respectively.

As shown inFIG. 1B, the resist mask9is used as a mask to etch the antireflection film8and SiN film7. Then, the resist mask9and antireflection film8are removed by oxygen ashing. Since the porous silica film4is covered with the SiO2film6and SiC film5, the porous silica film4is not exposed to the oxygen plasma during ashing.

After that, as shown inFIG. 1C, the SiN film7is used as a mask to etch the SiO2film6. Subsequently, as shown inFIG. 1D, the SiN film7is used as a mask to etch the SiC film5. During this etching, the thickness of the SiN film7reduces. The SiN film7may also disappear by this etching.

As shown inFIG. 1E, the SiO2film6is used as a mask to etch the porous silica film4. This etching is performed using no oxygen. For example, this etching is performed by using a plasma etching apparatus at a pressure of 13.3 Pa (100 mTorr) and an RF power of 500 W by supplying CF4, CHF3, and N2at 100, 100, and 20 sccm, respectively, into the processing chamber. By this etching, a trench (wiring trench)10is formed in the porous silica film4.

As shown inFIG. 1F, hydrogen plasma processing is then performed to form a modified layer4aby modifying the exposed portions of the porous silica film4. For example, this hydrogen plasma processing is performed by using a plasma etching apparatus at a pressure of 13.3 Pa (100 mTorr) and an RF power of 200 W by supplying H2and N2at 200 and 100 sccm, respectively, into the processing chamber. The processing time is set to, e.g., 10 sec by which the thickness of the modified layer4adecreases to 10 nm or less. This hydrogen plasma processing increases the selectivity between the porous silicon film4including the modified film4aand the SiC film3. In the porous silica film4, the Si and C concentrations in the modified layer4aare higher than those in the other portion. Note that the concentration of only one of Si and C in the modified layer4amay also be higher than that in the other portion.

As shownFIG. 1G, the SiO2film6is used as a mask to etch away the exposed portion of the SiC film3and the SiC film7. This etching is performed using nitrogen without using any oxygen. For example, this etching is performed by using a plasma etching apparatus at a pressure of 3.99 Pa (30 mTorr) and an RF power of 200 W by supplying CF4, CH2F2, and N2at 20, 20, and 50 sccm, respectively, into the processing chamber. By this etching, the trench10reaches the underlying Cu film2. Subsequently, wet cleaning is performed on the entire surface.

A barrier metal film and Cu seed film (neither is shown) are then formed on the bottom portion and side portions of the trench10. As shown inFIG. 1H, a Cu film (wiring material)11is buried in the trench10by plating. As shown inFIG. 1I, the Cu film11is polished by CMP (Chemical Mechanical Polishing) until the SiC film5is exposed, thereby forming an interconnection12. After that, as shown inFIG. 1J, an SiC film14as a barrier film and an interlayer dielectric film13are formed, and an upper interconnection and the like are also formed to complete a semiconductor device.

In the first embodiment as described above, when the SiC film3as a barrier film is etched, the modified layer4ais formed on the side portions of the porous silica film4, so the porous silica film4does not recede by side etching. As a consequence, the designed structure and characteristics can be obtained.

The second embodiment of the present invention will be described below.FIGS. 2A to 2Care sectional views showing a method of fabricating a semiconductor device according to the second embodiment of the present invention in order of steps. In the first embodiment, the modified portion4aprevents side etching of the porous silica film4. However, the presence of the modified portion4amay increase the dielectric constant. The second embodiment is made in consideration of this problem. In the second embodiment, therefore, a film for protecting a porous silica film4is formed instead of the modified portion4a.

In this embodiment, as shown inFIG. 2A, processing up to etching of the porous silica film4is performed in the same manner as in the first embodiment. In this embodiment, however, an SiN film7disappears at this point as shown inFIG. 2A. Since the SiN film7is not used in the subsequent steps, it may also disappear in the first embodiment and remain in the second embodiment.

As shown inFIG. 2B, a polymer deposition film (organic film)21is formed on the side surfaces of the porous silica film4. The polymer deposition film21may also be simultaneously formed on an SiC film3. The formation conditions of the polymer deposition film21will be explained later.

As shown inFIG. 2C, an SiO2film6is used as a mask to etch away exposed portions of the SiC film3. By this etching, the polymer deposition film21almost disappears. After that, wet cleaning is performed on the entire surface. As a consequence, the polymer deposition film21is completely removed even if it remains before this step.

A Cu film11, other films and the like are formed in the same manner as in the first embodiment, thereby completing a semiconductor device.

In the second embodiment as described above, no modified portion4ais formed on the side portions of the porous silica film4, and the polymer deposition film21is completely removed before interconnections are formed. Accordingly, the designed structure and characteristics can be obtained more reliably.

The formation conditions of the polymer deposition film21will be described below.FIG. 3is a view showing the relationships between the plasma processing conditions and the shapes of the processed films.FIG. 4is a graph showing the relationships between the plasma processing conditions and the processed states of the processed films.FIGS. 3 and 4are obtained by changing the value of x when the plasma processing conditions are such that C4F6, O2, and Ar are supplied at x, 20, and (400−20−x) sccm, respectively, into the processing chamber, the pressure is 13.3 Pa (100 mTorr), and the RF power is 1,000 W.

As shown inFIG. 3, the shape of any of the SiC film, porous silica film, and SiO2film after the processing changes in accordance with the value of x. More specifically, the smaller the x value, the more easily the film is bowed (the side surfaces recede in the form of a bow) by side etching; the larger the x value, the more easily the porous deposited product deposits. Substantially vertical side surfaces are obtained under intermediate conditions. Also, C4F6flow rate ranges (x ranges) I, II, and III in which the side surfaces of the SiC film are substantially vertical, the side surfaces of the porous silica film are substantially vertical, and the side surfaces of the SiO2film are substantially vertical, respectively, increase in value in this order. Since the purpose of the present invention is to prevent side etching of the porous silica film, the C4F6flow rate must fall within the flow rate range II or larger. In addition, deposition of the polymer deposition product of the SiO2film is preferably avoided as much as possible. This is so because if this deposition occurs, the interior of the chamber and the semiconductor device itself may be contaminated. Therefore, the C4F6flow rate preferably falls within the flow rate range III or smaller. In the second embodiment, the plasma processing conditions are such that C4F6, O2, and Ar are supplied at 30, 20, and 350 sccm, respectively, into the processing chamber, the pressure is 13.3 Pa (100 mTorr), the RF power is 1,000 W, and the processing time is 4 sec.

As shown inFIG. 4, which of side etching or deposition of the polymer deposition product occurs substantially depends upon the conditions under which the etching rate is a maximum. Note thatFIG. 4shows not relationships obtained for the structure as shown inFIGS. 2A to 2C, but relationships obtained when an SiC film, porous silica film, and SiO2film are individually formed on substrates and subjected to plasma processing under the conditions as described above. Generally, when the deposition rate of the polymer deposition product is higher than the etching rate shown inFIG. 4, deposition of the polymer deposition product progresses to form a polymer deposition film. If the deposition rate of the polymer deposition product is lower than the etching rate, etching of the processed film progresses.

For example, after the SiO2film6is etched in the second embodiment, if the porous silica film4is etched under the conditions of the flow rate range II and the SiC film3is etched under the conditions of the same flow rate range II, the SiC film3is tapered as shown inFIG. 5A. Likewise, after the SiO2film6is etched in the second embodiment, if the porous silica film4is etched under the conditions of the flow rate range II and the SiC film3is etched under the conditions of the flow rate range I, the porous silica film4is bowed as shown inFIG. 5B. This state shown inFIG. 5Bis equivalent to the state shown inFIG. 8D.

The third embodiment of the present invention will be described below.FIGS. 6A to 6Qare sectional views showing a method of fabricating a semiconductor device according to the third embodiment of the present invention. In this embodiment, a semiconductor device is fabricated by the dual damascene method of a trench pre-exposure type.

First, as shown inFIG. 6A, an SiC film3as an etching stopper is formed on a Cu film2(conductive layer) formed in an interlayer dielectric film1. A porous silica film4as an interlayer dielectric film is formed on the SiC film3. On the porous silica film4, an SiC film5is formed as a cap film (first hard mask), and an SiO2film6is formed as a second hard mask. Subsequently, an SiN film7is formed as a third hard mask on the SiO2film6. After that, an antireflection film8necessary for patterning is formed on the SiN film7. The antireflection film8is, e.g., an organic BARC. The antireflection film8is coated with an organic photosensitive ArF resist, and this resist is exposed and developed to form a resist mask9in which a wiring trench pattern is formed.

As shown inFIG. 6B, the resist mask9is used as a mask to etch the antireflection film8.

As shown inFIG. 6C, the resist mask9is used as a mask to etch the SiN film7. As a consequence, the SiN film7is patterned into the wiring trench pattern.

After that, as shown inFIG. 6D, the resist mask9and antireflection film8are removed by ashing.

Subsequently, as shown inFIG. 6E, a lower resin film (organic film)31for planarization is formed to fill the steps of the SiN film7. On the lower resin film31, an SOG (Spin On Glass) film (inorganic film)32to be used as a mask when the lower resin film31is to be etched is formed. The SOG film32is then coated with an organic photosensitive resin, and this resin is exposed and developed to form a resist mask (photosensitive resist film)33in which a via hole pattern is formed.

As the photosensitive resist, it is possible to use, e.g., a material sensitive to a KrF laser (wavelength: 248 nm), a material sensitive to an ArF laser (wavelength: 193 nm), a material sensitive to an F2laser (wavelength: 157 nm), or a material sensitive to an electron beam.

As the material of the SOG film32, an SOG material such as organic silicate glass or an organic siloxane polymer can be used. An example of the material of the lower resin film31is a coating type organic resin material.

After that, as shown inFIG. 6F, the resist mask33is used as a mask to etch the SOG film32.

Subsequently, as shown inFIG. 6G, the SOG film32is used as a mask to etch the lower resin film31and at the same time remove the resist mask33. In this etching, the etching selectivity to the lower resin film31and resist mask33is at most about 1 because the lower resin film31is made of an organic material similar to that of the resist mask33. Therefore, if the film thickness of the resist mask33is much larger than that of the lower resin film31, the resist mask33may remain on the SOG film32even after etching of the lower resin film31is complete. For this reason, the film thickness of the resist mask33is desirably equal to or smaller than that of the lower resin film31.

As shown inFIG. 6H, the lower resin film31is used as a mask to etch the SiN film7and SiO2film6, thereby forming a via hole pattern in these films and removing the SOG film32.

As shown inFIG. 6I, the lower resin film31is removed by ashing. After that, as shown inFIG. 6J, the SiO2film6is used as a mask to etch the SiC film5. In this step, the SiN film7is also etched to reduce its thickness. Subsequently, as shown inFIG. 6K, the SiN film7and SiC film5are used as masks to etch the SiO2film6and porous silica film4. Etching of the porous silica film4is stopped in its middle portion in the direction of thickness. As a consequence, the wiring trench pattern is also formed in the SiO2film6. In addition, a hole formed in the porous silica film4by this etching functions as part of the via hole. As shown inFIG. 6L, the SiO2film6is used as a mask to etch away the exposed portions of the SiC film5and the SiN film7. Consequently, the wiring trench pattern is formed in the SiC film5.

The SiO2film6and SiC film5are then used as masks to etch the porous silica film4, which is an interlayer dielectric film. Consequently, as shown inFIG. 6M, wiring trenches34and a via hole35reaching the SiC film3are formed at the same time.

After that, as shown inFIG. 6N, a polymer deposition film21is formed on the side surfaces of the porous silica film4in the same manner as in the second embodiment. The polymer deposition film21may also be formed on the SiC film3. The formation conditions of the polymer deposition film21are the same as described previously.

Subsequently, as shown inFIG. 60, the SiO2film6is used as a mask to etch away the exposed portion of the SiC film3, thereby allowing the via hole35to reach the Cu film2. By this etching, the polymer deposition film21almost disappears. After that, wet cleaning is performed on the entire surface. As a consequence, the polymer deposition film21is completely removed even if it remains before this step.

A barrier metal film and Cu seed film (neither is shown) are formed on the bottom portions and side portions of the wiring trenches34and via hole35. After that, as shown inFIG. 6P, a Cu film (wiring material)11is buried in the wiring trenches34and via hole35by plating. Then, as shown inFIG. 6Q, the Cu film11is polished by CMP (Chemical Mechanical Polishing) until the SiC film5is exposed, thereby forming a contact via36and Cu interconnections37. Furthermore, interlayer dielectric films, upper interconnections, and the like are formed to complete a semiconductor device.

FIG. 7is a sectional view showing the structure of a semiconductor device fabricated by applying the third embodiment. In this example shown inFIG. 7, a multilayered interconnection having at least two layers is formed by the fabrication method according to the third embodiment. A passivation film41made of, e.g., SiN is formed on Cu interconnections37and a porous silica film4in the uppermost layer. On the passivation film41, a cover film made up of a silicon oxide film42and SiN film43is formed. Holes (not shown) for extracting pads are appropriately formed in this cover film.

As described above, even when the present invention is applied to the dual damascene method, it is possible to prevent deformation of the porous silica film4, and obtain the designed structure and characteristics. In the third embodiment, the dual damascene method is applied to the second embodiment. However, this dual damascene method may also be applied to the first embodiment.

The material of the interlayer dielectric film is not particularly limited as long as the material contains Si, C, and O. That is, it is also possible to use another low-dielectric-constant film such as an SiOC film, SiOCN film, porous SiOC film, or porous SiOCN film, instead of the porous silica film.

In the plasma processing for forming a modified layer or polymer deposition film, not only hydrogen plasma but also a plasma of a reducing gas containing hydrogen (element), e.g., ammonium plasma, may also be used. Alternatively, helium plasma can be used to give impact to the side surfaces of the interlayer dielectric film such as a porous silica film, thereby hardening the side surfaces.

Patent reference 1 (Japanese Patent Application Laid-Open No. 2003-124189) describes a method in which after a porous film is etched by using a resist mask as a mask, ashing is performed by O2/CO plasma, and an SiC film as a barrier film is etched. In this method, however, the porous film is damaged by the ashing process using the plasma. In contrast, the present invention can avoid this damage because the organic film such as a resist is removed before a hole is formed in the interlayer dielectric film, so the degree of the plasma processing can be properly controlled.

Patent reference 2 (Japanese Patent No. 3250518) describes a method in which when an organic low-dielectric-constant film is to be processed, a side-wall deposition product is formed on the side surfaces of the low-dielectric-constant film by using NH3or a gas system obtained by adding N2to H2, thereby preventing bowing of the pattern. In this method, however, the side-wall deposition product is removed by wet processing before a trench is allowed to reach a lower interconnection, so the low-dielectric-constant film cannot be protected when the trench is allowed to reach the lower interconnection. However, the necessity of protection is low since an organic film is used as the low-dielectric constant film and the selectivity when an SiC film is etched is high.

Patent reference 3 (Japanese Patent No. 3365554) describes a method in which in order to prevent the side surfaces of a porous film from becoming unstable after etching, an insulating film is formed on the surface by O2plasma processing, the surface is nitrided by plasma processing using NH3, N2, or N2O, and a dielectric undercoating is processed after that. However, when the side surfaces of the porous film are nitrided, the selectivity to the dielectric undercoating lowers, and this allows easy occurrence of side etching.

Patent reference 4 (Japanese Patent Application Laid-Open No. 2002-26121) describes a method by which O2plasma processing is performed for a low-density, low-dielectric-constant film. However, when this O2plasma processing is performed by using a general RIE (Reactive Ion Etching) apparatus, side etching occurs to cause the side surfaces of the low-density, low-dielectric-constant film to recede in some cases. In contrast, no such recession takes place when a plasma containing hydrogen but not containing oxygen is used as in the present invention.

In the first semiconductor device fabrication method, the selectivity to the SiC barrier film can be increased by modifying the side surfaces of the interlayer dielectric film by the plasma processing. Therefore, the interlayer dielectric film is not side-etched even when the SiC barrier film is etched after that. As a consequence, desired characteristics (designed characteristics) can be obtained.

In the second semiconductor device fabrication method, the organic film formed by the plasma processing functions as a protective film of the interlayer dielectric film. Therefore, the interlayer dielectric film is not side-etched even when the SiC barrier film is etched after that, so desired characteristics (designed characteristics) can be obtained.