Charge pump circuit and PLL circuit

A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit causes a current obtained by mirroring a reference current to flow to a first output terminal and a second output terminal. The first drive switch connects or disconnects the first output terminal and a charge pump output terminal. The switch circuit connects the capacitor either to a discharge path between the second output terminal and a node which provides a predetermined voltage or to a charge path between the charge pump output terminal and a GND.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the Japanese Patent Application No. 2017-179345 filed on Sep. 19, 2017, the entire contents of which are incorporated herein by reference.

FIELD

An embodiment described herein relates generally to a charge pump circuit and a PLL circuit.

BACKGROUND

Conventionally, there has been a PLL circuit in which a phase comparator, a charge pump circuit, a loop filter and a VCO are provided, and which outputs an output signal synchronized with a phase of an input frequency signal.

In the PLL circuit, particularly in the charge pump circuit, there is a case where noise such as flicker noise and thermal noise is superimposed on an output signal.

For example, the charge pump circuit includes a current mirror circuit, and there is a case where noise generated at a mirror source is superimposed on a current at a mirror destination in accordance with a mirror ratio. If a size of a mirror source transistor is made larger, a current flowing in the mirror source transistor is increased, and a mirror ratio is decreased, it is possible to suppress noise at the current mirror circuit.

While it is possible to suppress noise by making a size of the charge pump circuit larger, there is a problem that it is difficult to make the size smaller while trying to suppress noise.

DETAILED DESCRIPTION

Embodiment

A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit causes a current obtained by mirroring a reference current to flow to a first output terminal and a second output terminal. The first drive switch connects or disconnects the first output terminal and a charge pump output terminal. The switch circuit connects the capacitor either to a discharge path between the second output terminal and a node which provides a predetermined voltage or to a charge path between the charge pump output terminal and a GND.

The embodiment will be described below with reference to the drawings.

FIG. 1is a block diagram illustrating an example of a configuration of a PLL circuit (phase locked loop circuit)1according to the embodiment.

The PLL circuit1includes a delta sigma modulator2, a frequency divider3, a phase comparator4, a charge pump circuit5, a loop filter6and a VCO (voltage controlled oscillator)7.

The delta sigma modulator2is connected to an external frequency control apparatus which is not illustrated and the frequency divider3. The delta sigma modulator2performs delta sigma modulation to generate a frequency division control signal on the basis of a frequency control signal Fc input from the frequency control apparatus and a frequency division signal Fn returned from the frequency divider3and outputs the frequency division control signal to the frequency divider3.

The frequency divider3is connected to the VCO7and the phase comparator4. The frequency divider3divides a frequency of a VCO output signal Fout returned from the VCO7on the basis of the frequency division control signal input from the delta sigma modulator2and outputs the frequency division signal Fn to the phase comparator4.

The phase comparator4is connected to an external clock generator which is not illustrated and the charge pump circuit5. The phase comparator4compares phases to generate phase difference signals Pu and Pd in accordance with a phase difference on the basis of the frequency division signal Fn input from the frequency divider3and a reference clock signal Fr having a predetermined frequency, input from the clock generator and outputs the phase difference signals Pu and Pd to the charge pump circuit5.

The charge pump circuit5is connected to the loop filter6. The charge pump circuit5outputs an output current in accordance with the phase difference signals Pu and Pd to the loop filter6on the basis of the phase difference signals Pu and Pd input from the phase comparator4.

Here, if linearity of the output current with respect to the phase difference signals Pu and Pd is unfavorable, high frequency noise of the delta sigma modulator2is converted into a low frequency due to distortion, and noise shaping characteristics of the delta sigma modulator2deteriorate. If the output current is increased to improve linearity, noise and spurious of a clock also increase in proportion to the output current.

The loop filter6is connected to the VCO7. The loop filter6smooths the output current input from the charge pump circuit5to generate a loop filter output signal and outputs the loop filter output signal to the VCO7.

The VCO7generates a VCO output signal Fout having a frequency in accordance with a voltage of the loop filter output signal input from the loop filter6and outputs the VCO output signal Fout to outside.

Subsequently, the charge pump circuit5according to the embodiment will be described.

FIG. 2is a circuit diagram illustrating an example of the charge pump circuit5and the loop filter6of the PLL circuit1according to the embodiment.

The charge pump circuit5includes a main charge pump11and a sub charge pump21. The main charge pump11, an output current of which increases in accordance with the output current of the sub charge pump21, operates in a state where linearity is favorable.

The main charge pump11includes a constant current source12, a transistor T1which is a first transistor, a transistor T2which is a second transistor, a transistor T3which is a third transistor, a transistor T4which is a fourth transistor, a transistor T5which is a fifth transistor, a drive switch Sw1which is a first drive switch, and a drive switch Sw2which is a second drive switch. The transistors T1, T2and T3are configured with, for example, an NMOS. The transistors T4and T5are configured with, for example, a PMOS.

The constant current source12has one end connected to a power supply and the other end connected to the transistor T1. The constant current source12outputs a reference current Iref to the transistor T1.

The transistor T1has a drain connected to the constant current source12, a source connected to a GND, and a gate connected to the transistors T2and T3. The drain and the gate of the transistor T1are connected to each other.

The transistor T2has a drain connected to a drain of the transistor T4and a source connected to the GND.

The transistor T3has a drain connected to the drive switch Sw2and a source connected to the GND.

The transistors T1, T2and T3constitute a current mirror C1which is a first current mirror.

The transistor T4has a source connected to the power supply and a gate connected to the transistors T5and T6. A drain and the gate of the transistor T4are connected to each other.

The transistor T5has a source connected to the power supply and a drain connected to the drive switch Sw1. The drain of the transistor T5constitutes an output terminal D1which is a first output terminal.

The drive switches Sw1and Sw2are connected between the transistors T3and T5in series. Between the drive switches Sw1and Sw2, a charge pump output terminal Cout is connected. The drive switches Sw1and Sw2are configured with a semiconductor switch and is driven by the phase difference signals Pu and Pd input from the phase comparator4.

The drive switch Sw1has one end connected to a drain of the transistor T5and the other end connected to the charge pump output terminal Cout. The drive switch Sw1connects or disconnects the output terminal D1and the charge pump output terminal Cout in accordance with the phase difference signal Pu.

The drive switch Sw2has one end connected to the drain of the transistor T3and the other end connected to the charge pump output terminal Cout. The drive switch Sw2connects or disconnects the GND and the charge pump output terminal Cout via the transistor T3in accordance with the phase difference signal Pd.

The sub charge pump21includes a transistor T6which is a sixth transistor, a capacitor22, an amplifier23, a switch circuit Sw, a driver Dv and the charge pump output terminal Cout.

The transistor T6has a source connected to the power supply and a drain connected to the switch circuit Sw. The drain of the transistor T6constitutes an output terminal D2which is a second output terminal.

The transistors T4, T5and T6constitute a current mirror C2which is a second current mirror.

That is, the current mirrors C1and C2constitute a current mirror circuit Cr. The current mirrors C1and C2are connected to each other. The current mirror C1is configured with an NMOS, and connected to the constant current source12. The current mirror C2is configured with a PMOS and includes output terminals D1and D2.

Further, the current mirror circuit Cr causes currents I1and I2obtained by mirroring the reference current Iref of the constant current source12to flow to the output terminals D1and D2.

Further, the current mirror C1includes the transistors T1, T2and T3, gates of which are connected to one another, the drain of the transistor T1is connected to the gate and the constant current source12, respective drains of the transistor T2and the transistor T4are connected to each other, and the transistor T3has a source connected to the GND and a drain connected to the drive switch Sw2.

Further, the current mirror C2includes the transistors T4, T5and T6, gates of which are connected to one another, the transistor T5includes the output terminal D1, and the transistor T6includes the output terminal D2.

The capacitor22, which is connected to the switch circuit Sw, discharges electric charges by a current I2input from the output terminal D2and charges electric charges by a charge current Ic input from the loop filter6.

The amplifier23, in which an inverted input terminal and an amplifier output terminal are connected to each other, has a non-inverted input terminal connected to the charge pump output terminal Cout and the amplifier output terminal connected to a node N. The amplifier23constitutes a voltage follower circuit.

The switch circuit Sw connects the capacitor22either to a discharge path between the output terminal D2and the node N which provides a predetermined voltage or to a charge path between the charge pump output terminal Cout and the GND. The switch circuit Sw is configured with a semiconductor switch and is driven by the driver Dv. The switch circuit Sw includes discharge switches Sd1and Sd2, charge switches Sd1and Sc2and a ground switch Sg.

The discharge switch Sd1is provided between a first end22aof the capacitor22and the output terminal D2. The discharge switch Sd2is provided between a second end22bof the capacitor22and the node N. The discharge switches Sd1and Sd2connect or disconnect the first end22aand the output terminal D2, and the second end22band the node N.

The charge switch Sc1is provided between the first end22aand the GND. The charge switch Sc2is provided between the second end22band the charge pump output terminal Cout. The charge switches Sc1and Sc2connect or disconnect the first end22aand the GND, and the second end22band the charge pump output terminal Cout.

When the discharge switches Sd1and Sd2are put into a connection state, and the charge switches Sc1and Sc2are put into a disconnection state, the capacitor22is connected to the discharge path. When the discharge switches Sd1and Sd2are put into a disconnection state and the charge switches Sc1and Sc2are put into a connection state, the capacitor22is connected to the charge path.

The ground switch Sg, which is provided between the output terminal D2and the GND, connects or disconnects the output terminal D2and the GND.

The driver Dv drives the switch circuit Sw. Specifically, the driver Dv outputs drive signals to the discharge switches Sd1and Sd2, the charge switches Sc1and Sc2, and the ground switch Sg in accordance with predetermined order, and switches a state of each of the discharge switches Sd1and Sd2, the charge switches Sc1and Sc2and the ground switch Sg to either an ON state or an OFF state.

The charge pump output terminal Cout, which is connected between the other end of the drive switch Sw1and one end of the drive switch Sw2, outputs an output current to the loop filter6.

The loop filter6includes resistances31and32, capacitors33,34and35and a loop filter output terminal Lout.

The resistance31has one end connected to the charge pump output terminal Cout and the other end connected to the loop filter output terminal Lout.

The loop filter output terminal Lout is connected to the other end of the resistance31.

The resistance32has one end connected to the charge pump output terminal Cout and the resistance31and the other end connected to the capacitor33.

The capacitor33has one end connected to the resistance32and the other end connected to the GND.

The capacitor34has one end connected to the charge pump output terminal Cout and the resistance31and the other end connected to the GND.

The capacitor35has one end connected to the loop filter output terminal Lout and the resistance31and the other end connected to the GND.

The capacitors33,34and35charge electric charges when a current I1is output from the charge pump circuit5, and discharge electric charges when a charge current Ic is led by the charge pump circuit5.

Operation of the charge pump circuit5according to the present embodiment will be described.

At the charge pump circuit5, each cycle of a phase difference output cycle, a discharge cycle and a charge cycle is repeatedly performed in accordance with a predetermined period.

When the charge current Ic is input from the loop filter6to the charge pump circuit5, a voltage of the loop filter output signal decreases, and the PLL circuit1is locked in a state where a phase of the reference clock signal Fr is ahead of a phase of the frequency division signal Fn and in a state where a band is offset from a dead band and linearity of the output current is favorable.

The phase difference output cycle will be described.

FIG. 3AtoFIG. 4Care waveform diagrams illustrating waveforms of the PLL circuit1according to the embodiment.FIG. 3AandFIG. 4Aillustrate waveforms of the reference clock signal Fr,FIG. 3BandFIG. 4Billustrate waveforms of the frequency division signal Fn,FIG. 3Cillustrates a waveform of the phase difference signal Pu, andFIG. 4Cillustrates a waveform of the phase difference signal Pd. In the phase difference output cycle, a current I1in accordance with a phase difference between the reference clock signal Fr and the frequency division signal Fn is output to the loop filter6.

The driver Dv outputs a drive signal and puts the discharges switches Sd1and Sd2and the charge switches Sc1and Sc2into a disconnection state.

The driver Dv outputs a drive signal and connects the output terminal D2and the GND by the ground switch Sg to set the output terminal D2as ground potential. That is, the ground switch Sg connects the output terminal D2and the GND before the capacitor22is connected to the discharge path.

The phase comparator4compares a pulse of the reference clock signal Fr and a pulse of the frequency division signal Fn and outputs the phase difference signals Pu and Pd to the charge pump circuit5.

For example, as illustrated inFIG. 3AtoFIG. 3C, the phase comparator4puts the phase difference signal Pu into an ON state for a time period corresponding to a phase shift amount when a phase of the frequency division signal Fn lags behind a phase of the reference clock signal Fr. Specifically, during a time period Tu from falling of the reference clock signal Fr until falling of the frequency division signal Fn, the phase difference signal Pu is put into an ON state, and the drive switch Sw1connects the output terminal D1and the charge pump output terminal Cout.

On the other hand, as illustrated inFIG. 4AtoFIG. 4C, the phase comparator4puts the phase difference signal Pd into an ON state during a time period corresponding to a phase shift amount when the phase of the frequency division signal Fn is ahead of the phase of the reference clock signal Fr. Specifically, during a time period Td from falling of the frequency division signal Fn until falling of the reference clock signal Fr, the phase difference signal Pd is put into an ON state, and the drive switch Sw2connects the GND and the charge pump output terminal Cout via the transistor T3.

When the reference current Iref is input to the transistor T1from the constant current source12, in the current mirror C1, a voltage between the gate and the source of each of the transistors T1, T2and T3becomes the same, and a current Id obtained by mirroring the reference current Iref flows in the drain of the transistor T2. The current Id also flows in the drain of the transistor T4connected to the drain of the transistor T2.

FIG. 5is an explanatory diagram for explaining an example of the phase difference output cycle of the charge pump circuit5of the PLL circuit1according to the embodiment.

As illustrated inFIG. 5, when the phase difference signal Pu is put into an ON state, the drive switch Sw1connects the output terminal D1and the charge pump output terminal Cout. In the output terminal D1, a current I1flows so as to compensate for electric charges discharged from the loop filter6. Therefore, a pulse width of the current I1in accordance with a time period of a connection state of the drive switch Sw1becomes larger in accordance with leading of the charge current Ic from the loop filter6. The current I1is output to the loop filter6via the charge pump output terminal Cout. The electric charges of the current I1are charged to the capacitors33,34and35. That is, the pulse width of the current I1is made larger by leading of the charge current Ic so as to prevent linearity from deteriorating as a result of a response of the current I1being too late.

The discharge cycle will be described next.

FIG. 6is an explanatory diagram for explaining an example of the discharge cycle of the charge pump circuit5of the PLL circuit1according to the embodiment.

In the discharge cycle, after the current I1is output to the loop filter6via the charge pump output terminal Cout, electric charges of the capacitor22are discharged by the current I2output from the output terminal D2.

As illustrated inFIG. 6, the driver Dv outputs a drive signal, puts the discharge switches Sd1and Sd2into a connection state, puts the charge switches Sc1and Sc2into a disconnection state, and connects the capacitor22to the discharge path.

The current I2output from the output terminal D2flows in the amplifier23via the capacitor22and causes the electric charges of the capacitor22to be discharged. The electric charges discharged from the capacitor22flow into the amplifier23, and inflow to parasitic capacitance is suppressed.

The first end22aof the capacitor22is switched to the output terminal D2which is made the ground potential from the GND. The second end22bof the capacitor22is switched to the amplifier output terminal from the charge pump output terminal Cout. Therefore, potential of the first end22aand the second end22bof the capacitor22does not change even if a cycle is switched from the charge cycle to the discharge cycle, so that inflow of electric charges to the parasitic capacitance is suppressed.

The charge cycle will be described next.

FIG. 7is an explanatory diagram for explaining an example of the charge cycle of the charge pump circuit5of the PLL circuit1according to the embodiment.

In the charge cycle, after the electric charges of the capacitor22are discharged, electric charges are charged by the charge current Ic input from the loop filter6via the charge pump output terminal Cout.

As illustrated inFIG. 7, the driver Dv outputs a drive signal, puts the discharge switches Sd1and Sd2into a disconnection state, puts the charge switches Sc1and Sc2into a connection state and connects the capacitor22to the charge path.

The charge current Ic flows in the GND via the capacitor22. The capacitor22is charged by the charge current Ic.

The driver Dv may output a drive signal and connect the output terminal D2and the GND with the ground switch Sg to prepare for the charge cycle.

That is, the current I1is output to the charge pump output terminal Cout from the output terminal D1through driving of the drive switch Sw1, and after the current I1is output, the capacitor22is connected to the discharge path through driving of the switch circuit Sw, electric charges are discharged by the current I2output from the output terminal D2, and after the electric charges are discharged, the capacitor22is connected to the charge path through driving of the switch circuit Sw, and charged by the charge current Ic input from the charge pump output terminal Cout.

FIG. 8is a graph explaining an example of relationship between an output current flowing in the charge pump output terminal Cout of the charge pump circuit5and time according to the embodiment.

As illustrated inFIG. 8, a period between time t0and t1is the phase difference output cycle. In the phase difference output cycle, the current I1is output to the loop filter6.

A period between time t1and t2is the discharge cycle. In the discharge cycle, there is no change in the output current at the charge pump output terminal Cout. At the capacitor22, electric charges are discharged by the current I2obtained by mirroring the current Id.

A period between time t2and t3is the charge cycle. In the charge cycle, electric charges of the capacitor22are charged by the charge current Ic input from the charge pump output terminal Cout.

An average of the current I1is the same as an average of the charge current Ic. Further, the average of the charge current Ic is also the same as an average of the discharge current.

The current I2is output while mirroring the reference current Iref in a similar manner to the current I1. Noise generated at the constant current source12and the transistors T1, T2and T4is superimposed on each of the current I1and the current I2. By discharging being performed by the current I2and charging being performed by the current I1, the noise superimposed on the currents I1and I2is cancelled out from each other.

By this means, at the charge pump circuit5, it is possible to cancel out noise of the transistors T1and T2which are the NMOS where flicker noise is large. Further, at the charge pump circuit5, the drive switch Sw2is rarely put into an ON state after the PLL circuit is locked compared to the drive switch Sw1, so that generation of noise of the transistor T3which is the NMOS can be also suppressed. Further, at the charge pump circuit5, inflow of electric charges to parasitic capacitance when the cycle is switched from the charge cycle to the discharge cycle can be suppressed, so that it is possible to more reliably cancel out noise.

At the charge pump circuit5, a size of the transistors T1, T2and T4where noise is cancelled out is made smaller, and power is saved, and a size of the transistors T5and T6where noise is not cancelled out is also made smaller. If the size of the transistor T5is made smaller, operation speed is made higher as a result of drain capacitance being reduced, and the pulse width of the current I1can be made smaller, so that noise and spurious of the clock are reduced. That is, at the charge pump circuit5, it is possible to suppress noise of the transistors T2and T4without making the size of the transistors T2and T4larger.

According to the embodiment, it is possible to suppress generation of noise at the charge pump circuit5and the PLL circuit1and realize a further smaller size.

Note that, while, in the embodiment, the current mirror C1is configured with an NMOS, and the current mirror C2is configured with a PMOS, the current mirror C1may be configured with a PMOS, and the current mirror C2may be configured with an NMOS.

Note that, while, in the embodiment, the amplifier23is provided, and the amplifier output terminal is connected to the node N, in place of the amplifier23, the power supply having a predetermined voltage may be connected to the node N.

While the embodiment of the present invention has been described, this embodiment is provided as an example, and is not intended to limit the scope of the present invention. This new embodiment can be implemented in other various forms, and various omission, replacement and change can be made without departing from the gist of the invention. This embodiment and modifications are included in the scope and the gist of the invention and are also included in the scope of the invention recited in the claims and equivalence of the invention.