Reset circuit

A reset circuit includes: an output circuit that outputs a reset release signal for releasing reset of a reset target circuit that is to be applied with a power supply voltage, when a first voltage that rises with a rise in the power supply voltage reaches a first reference voltage that rises with a rise in the power supply voltage until the first reference voltage reaches a target level; and an inhibit circuit that inhibits the reset release signal from being output to the reset target circuit until the power supply voltage reaches a third level, the third level being higher than a first level at a time when the first reference voltage exceeds the first voltage, the third level being lower than a second level at a time when the first voltage reaches the target level.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority pursuant to 35 U.S.C. § 119 from Japanese Patent Application No. 2019-001051, filed on Jan. 8, 2019, the entire disclosure of which is hereby incorporated by reference herein.

BACKGROUND ART

Technical Field

The present disclosure relates to a reset circuit.

Related Art

In activating an integrated circuit including a digital circuit and/or a control circuit, known is a reset circuit that monitors a rise in a power supply voltage of the integrated circuit to prevent an unstable initial operation of the integrated circuit, and releases reset of the integrated circuit when the power supply voltage has risen to a stable voltage. For example, a reset circuit compares a divided voltage obtained by dividing a power supply voltage with a reference voltage and, when the divided voltage reaches the reference voltage, determines that the power supply voltage has stabilized and release the reset of an integrated circuit (for example, Japanese Patent Application Publication No. H8-84058).

However, in some configurations of a reference voltage generation circuit that generates the reference voltage, the divided voltage may exceed the reference voltage even before the power supply voltage reach a stable voltage, due to a difference in slope of rise between the divided voltage and the reference voltage. This may release the reset of the integrated circuit and cause a malfunction.

Thus, an object of the present disclosure is to provide a reset circuit that reliably inhibits a reset release signal from being output until a power supply voltage reaches a stable voltage.

SUMMARY

A main aspect of the present disclosure for solving an issue described above is a reset circuit comprising: an output circuit that outputs a reset release signal for releasing reset of a reset target circuit that is to be applied with a power supply voltage, when a first voltage that rises with a rise in the power supply voltage reaches a first reference voltage that rises with a rise in the power supply voltage until the first reference voltage reaches a target level; and an inhibit circuit that inhibits the reset release signal from being output to the reset target circuit until the power supply voltage reaches a third level, the third level being higher than a first level at a time when the first reference voltage exceeds the first voltage, the third level being lower than a second level at a time when the first voltage reaches the target level.

Other features of the present disclosure will become apparent from descriptions of the present specification and of the accompanying drawings.

With the present disclosure, it is possible to provide a reset circuit that reliably inhibits a reset release signal from being output until a power supply voltage reaches a stable voltage.

DETAILED DESCRIPTION

At least the following details will become apparent from descriptions of the present specification and of the accompanying drawings.

One Configuration Example of Integrated Circuit

FIG. 1is a block diagram illustrating one configuration example of an integrated circuit that employs a reset circuit according to an embodiment of the present disclosure.

An integrated circuit100detects a predetermined pressure generated in a pressure measurement target device (a vehicle-mounted electronic device, a home appliance, etc.), and digitally processes a detection result of the pressure, for example. The integrated circuit100includes a pressure sensor110, an amplifier120, an AD converter (ADC)130, a digital circuit140, a clock circuit150, and a reset circuit200.

The pressure sensor110detects a predetermined pressure IN generated in a pressure measurement target device, and is configured with, for example, a resistance bridge-type sensor that uses a semiconductor piezoelectric element. The semiconductor piezoelectric element has a structure in which a piezoresistor is formed, by a semiconductor processing technique, on a diaphragm that is obtained by partially processing a silicon substrate so as to be thin by etching or the like. When a pressure is applied to the semiconductor piezoelectric element from the outside, the piezoresistor receives stress caused by bending the diaphragm, thereby changing a resistance value. The pressure sensor110results in detecting a change in resistance value of the piezoresistor as a change in pressure.

The amplifier120amplifies a pressure detection value (analog value) output from the pressure sensor110by an amplification factor such that the ADC130on a subsequent stage can convert the pressure detection value into a digital value.

The ADC130converts the amplified pressure detection value output from the amplifier120into a digital value. The ADC130is configured with, for example, a ΔΣ AD converter.

The digital circuit140adjusts the digital value indicative of the pressure detection value output from the ADC130such that varied output characteristics of the pressure sensor110caused by variation at a manufacturing stage and the like will be desired output characteristics, and then converts a signal format into a signal format needed for a circuit (not illustrated) on a subsequent stage that is connected to the integrated circuit100, and outputs a digital signal OUT thereto.

The clock circuit150generates a clock signal used as a reference when the digital circuit140operates. The clock circuit150includes, for example, a free-running oscillator including a crystal resonator, and a frequency divider that performs frequency division until an oscillation signal output from the free-running oscillator achieves a clock signal at a frequency needed for digital processing in the digital circuit140.

A power supply voltage Vcc is applied to the pressure sensor110, the amplifier120, the ADC130, the digital circuit140, and the clock circuit150. In order to allow the digital circuit140to correctly perform digital processing, the reset circuit200resets the digital circuit140until the power supply voltage Vcc rises to a voltage at which the digital circuit140can normally operate, and releases the reset of the digital circuit140when the power supply voltage Vcc has risen to the voltage at which the digital circuit140can normally operate. The integrated circuit100may further include an output unit that outputs a signal indicative of a reset operation performed by the reset circuit200to the outside. A configuration example of the reset circuit200will be described below as first to sixth embodiments (reset circuits200A to200F).

First Embodiment

FIG. 2is a circuit block diagram illustrating a reset circuit according to the first embodiment.FIG. 3is a timing chart illustrating an operation of the reset circuit according to the first embodiment.

First, a configuration of the reset circuit200A will be described.

The reset circuit200A includes first voltage divider resistors201to203, a reference voltage generation circuit204, a first comparator205, a bias current generation circuit206, second voltage divider resistors207and208, a pull-up resistor209, an NMOS transistor210, an AND gate211, an inverter212, and a switch circuit213.

The first voltage divider resistors201to203are connected in series between the power supply voltage Vcc and the ground. The reference voltage generation circuit204is applied with the power supply voltage Vcc and generates a first reference voltage Vref1serving as a target level, and is configured with, for example, a bandgap reference voltage generation circuit. When the power supply voltage Vcc is applied, a first voltage V1that appears at a connection point of the first voltage divider resistors201and202rises with a rise in the power supply voltage Vcc, and the first reference voltage Vref1rises with the rise in the power supply voltage Vcc until the first reference voltage Vref1reaches the target level. Herein, resistance values of the first voltage divider resistors201to203and a value of the first reference voltage Vref1are previously set such that the first voltage V1is higher than the target level of the first reference voltage Vref1when the power supply voltage Vcc has risen to a stable voltage.

The first voltage V1is applied to a non-inverting input terminal (+) of the first comparator205. The first reference voltage Vref1is applied to an inverting input terminal (−) of the first comparator205. Then, the first comparator205outputs a detection signal Vdet1at a logic level “L” when the first voltage V1is lower than the first reference voltage Vref1, and outputs a detection signal Vdet1at a logic level “H” when the first voltage V1is higher than the first reference voltage Vref1. Note that the detection signal Vdet1at the logic level “H” is a reset release signal for releasing reset of the digital circuit140.

The bias current generation circuit206is applied with the power supply voltage Vcc and generates a bias current Ib for operating the first comparator205.

The second voltage divider resistors207and208are connected in series between the power supply voltage Vcc and the ground. The pull-up resistor209and the NMOS transistor210are connected in series between the power supply voltage Vcc and the ground. Then, a second voltage V2that appears at a connection point of the second voltage divider resistors207and208is applied to a gate of the NMOS transistor210.

The first reference voltage Vref1rises with a rise in the power supply voltage Vcc until the first reference voltage Vref1reaches the target level, but a slope when the first reference voltage Vref1rises varies with characteristics of an element constituting the reference voltage generation circuit204. Thus, the first voltage V1may exceed the first reference voltage Vref1even in a transition period in which the first reference voltage Vref1is rising toward the target level. In an embodiment of the present disclosure, the reference voltage generation circuit204generates such a first reference voltage Vref1as to cause a time period in which the first voltage V1exceeds the first reference voltage Vref1in the transition period in which the first reference voltage Vref1is rising toward the target level.

When the power supply voltage Vcc is applied, the second voltage V2rises with a rise in the power supply voltage Vcc, and the NMOS transistor210is turned on when the second voltage V2exceeds a gate-source threshold voltage (second reference voltage Vref2) of the NMOS transistor210. Herein, resistance values of the second voltage divider resistors207and208and the gate-source threshold voltage of the NMOS transistor210are previously set such that the second voltage V2does not exceed the gate-source threshold voltage of the NMOS transistor210until the power supply voltage Vcc reaches a third level L3. The third level L3is higher than a first level L1, which is a level at a time when the first reference voltage Vref1exceeds the first voltage V1and the third level L3is lower than a second level L2, which is a level at a time when the first voltage V1reaches the target level of the first reference voltage Vref1. The gate-source threshold voltage of the NMOS transistor210can be adjusted by, for example, changing a channel length and/or a voltage applied between a gate electrode and a back gate electrode.

Note that an NPN transistor (bipolar transistor: not illustrated) may be provided instead of the NMOS transistor210(MOS transistor), and a base-emitter voltage of the NPN transistor may be used as the second reference voltage Vref2. In this case, resistance values of the second voltage divider resistors207and208may be set such that the second voltage V2does not exceed the base-emitter voltage of the NPN transistor until the power supply voltage Vcc reaches the above-described third level L3.

A drain output of the NMOS transistor210is input to one of input terminals of the AND gate211via the inverter212. In other words, a detection signal Vdet2indicative of on and off state of the NMOS transistor210output from the inverter212is input to one of the input terminals of the AND gate211. Note that the detection signal Vdet2at the logic level “L” serves as an inhibiting signal for inhibiting the detection signal Vdet1at the logic level “H” (reset release signal) from being output to the digital circuit140. On the other hand, the detection signal Vdet1output from the first comparator205is input to the other input terminal of the AND gate211. In other words, the AND gate211passes and blocks the detection signal Vdet1output from the first comparator205in accordance with on and off of the NMOS transistor210, respectively. For example, when the NMOS transistor210is turned off, the inverter212outputs the detection signal Vdet2at the logic level “L”, and thus the AND gate211outputs a reset signal RESET at the logic level “L” regardless of a logic level of the detection signal Vdet1output from the first comparator205. The reset signal RESET at the logic level “L” is a signal for resetting the digital circuit140. On the other hand, when the NMOS transistor210is turned on, the inverter212outputs the detection signal Vdet2at the logic level “H”, and thus the AND gate211passes the detection signal Vdet1at the logic level “H” output from the first comparator205. The reset signal RESET at the logic level “H” is a signal for releasing reset of the digital circuit140.

The switch circuit213is connected in parallel to the first voltage divider resistor203. The switch circuit213is turned on and off in accordance with a logic level of the reset signal RESET output from the AND gate211. For example, when the reset signal RESET at the logic level “L” is output from the AND gate211, the switch circuit213is turned on, and short-circuits the first voltage divider resistor203. On the other hand, when the reset signal RESET at the logic level “H” is output from the AND gate211, the switch circuit213is turned off, and releases a short circuit of the first voltage divider resistor203. In other words, when a logic level of the reset signal RESET changes from “L” to “H” in order to release reset of the digital circuit140, the first voltage V1rises from a divided voltage value without consideration given to a resistance value of the first voltage divider resistor203, to a divided voltage value with consideration given to the resistance value of the first voltage divider resistor203. Accordingly, the switch circuit213functions as a setting circuit that sets the first voltage V1, which is to be compared with the first reference voltage Vref1in the first comparator205, up to a high voltage value with consideration given to the first voltage divider resistor203, upon releasing of the reset of the digital circuit140. The switch circuit213prevents a malfunction in which the first voltage V1is affected by chattering and exceeds the first reference voltage Vref1again after releasing the reset of the digital circuit140, and another malfunction in which the detection signal Vdet1of the first comparator205repeats transitions between the logic levels of “H” and “L” due to microvibration of the first reference voltage Vref1when the first voltage V1is at a level near the first reference voltage Vref1.

Next, an operation of the reset circuit200A will be described. It is assumed that, in an initial state when the power supply voltage Vcc is applied, the reset signal RESET at the logic level “L” is output from the AND gate211in response to OFF of the NMOS transistor210, and the first voltage divider resistor203is short-circuited in response to ON of the switch circuit213.

When the power supply voltage Vcc is applied, the first voltage V1and the first reference voltage Vref1start rising with a rise in the power supply voltage Vcc. As described above, the first reference voltage Vref1has such a value that the first voltage V1is higher than the first reference voltage Vref1until a time T1due to the characteristics of the element constituting the reference voltage generation circuit204. In other words, the detection signal Vdet1at the logic level “H” is output from the first comparator205until the time T1. On the other hand, when the power supply voltage Vcc is applied, the second voltage V2also starts rising with the rise in the power supply voltage Vcc. Herein, the NMOS transistor210remains off until the power supply voltage Vcc reaches the third level L3(time T2) that is higher than the first level L1(time T1) at a time when the first reference voltage Vref1exceeds the first voltage V1and is lower than the second level L2(time T3) at a time when the first voltage V1reaches the target level of the first reference voltage Vref1. Accordingly, the detection signal Vdet2at the logic level “L” is output from the inverter212, and thus the detection signal Vdet1at the logic level “H” output from the first comparator205is not allowed to pass through the AND gate211, and the reset signal RESET at the logic level “L” is output from the AND gate211. In this way, the digital circuit140remains in a reset state.

Since the first voltage V1is lower than the first reference voltage Vref1in a time period from the time T1to the time T3, the detection signal Vdet1at the logic level “L” is output from the first comparator205. Accordingly, the reset signal RESET at the logic level “L” is output from the AND gate211. Thus, the digital circuit140still remains in the reset state.

At the time T2between the time T1and the time T3, the NMOS transistor210is turned on, and the detection signal Vdet2at the logic level “H” is output from the inverter212. Accordingly, from the time T2, the reset signal RESET at the same logic level as the logic level output from the first comparator205is output from the AND gate211.

At the time T3, the detection signal Vdet1at the logic level “H” is output from the first comparator205. Since the detection signal Vdet2at the logic level “H” has been already output from the inverter212, the detection signal Vdet1at the logic level “H” is output as the reset signal RESET from the AND gate211. This releases the reset of the digital circuit140. At this time, the short circuit in the first voltage divider resistor203is released by turning the switch circuit213off, and the first voltage V1rises by an amount (dot-and-dash line) corresponding to the first voltage divider resistor203. Accordingly, even when the first voltage V1fluctuates due to chattering or the first reference voltage Vref1minutely vibrates, the first comparator205normally operates.

Second Embodiment

FIG. 4is a circuit block diagram illustrating a reset circuit according to a second embodiment. Note that elements of the reset circuit200B that are the same as those of the reset circuit200A are given the same reference numerals, and description of configurations and operations thereof is omitted.

The reset circuit200B is configured such that the first voltage divider resistors201to203in the reset circuit200A are replaced with first voltage divider resistors201to203and218, the second voltage divider resistors207and208in the reset circuit200A are eliminated, the NMOS transistor210in the reset circuit200A is replaced with an NMOS transistor210′, and a third voltage V3(>a first voltage V1) that appears at a connection point of the first voltage divider resistors218and201is applied to a gate of the NMOS transistor210′.

Then, resistance values of the first voltage divider resistors201to203and218and a gate-source threshold voltage of the NMOS transistor210′ are previously set such that the third voltage V3does not exceed the gate-source threshold voltage of the NMOS transistor210′ until a power supply voltage Vcc reaches a third level L3that is higher than a first level L1at a time when a first reference voltage Vref1exceeds the first voltage V1and is lower than a second level L2at a time when the first voltage V1reaches a target level of the first reference voltage Vref1. The gate-source threshold voltage of the NMOS transistor210′ can be adjusted by, for example, changing a channel length and/or a voltage applied between a gate electrode and a back gate electrode.

Third Embodiment

FIG. 5is a circuit block diagram illustrating a reset circuit according to a third embodiment. Note that elements of the reset circuit200C that are the same as those of the reset circuit200A are given the same reference numerals, and description of configurations and operations thereof is omitted.

The reset circuit200C includes a switch circuit214instead of the AND gate211in the reset circuit200A.

The switch circuit214is connected between an output terminal of a first comparator205and the ground, and is turned on and off in response to a detection signal Vdet2output from an inverter212. For example, when a second voltage V2does not reach a gate-source threshold voltage of an NMOS transistor210, the switch circuit214is turned on by the detection signal Vdet2at a logic level “L”. Accordingly, a reset signal RESET fixed at the logic level “L” is output regardless of a logic level of a detection signal Vdet1output from the first comparator205. This causes a digital circuit140to remain in a reset state. On the other hand, when the second voltage V2reaches the gate-source threshold voltage of an NMOS transistor210, the switch circuit214is turned off by the detection signal Vdet2at a logic level “H”. Accordingly, the detection signal Vdet1at the logic level output from the first comparator205is output as the reset signal RESET as it is. In this way, when the detection signal Vdet1at the logic level “H” is output from the first comparator205, the reset of the digital circuit140is released.

When a logic level of the detection signal Vdet1output from the first comparator205is “L”, the switch circuit213is turned on and short-circuits a first voltage divider resistor203. When the logic level of the detection signal Vdet1output from the first comparator205is “H”, the switch circuit213is turned off and releases the short circuit of the first voltage divider resistor203.

Fourth Embodiment

FIG. 6is a circuit block diagram illustrating a reset circuit according to a fourth embodiment. Note that elements of the reset circuit200D that are the same as those of the reset circuit200A are given the same reference numerals, and description of configurations and operations thereof is omitted.

The reset circuit200D is configured such that the first voltage divider resistors201to203in the reset circuit200A are replaced with first voltage divider resistors201to203and218, the second voltage divider resistors207and208in the reset circuit200A are eliminated, the NMOS transistor210in the reset circuit200A is replaced with an NMOS transistor210′, and a third voltage V3(>a first voltage V1) that appears at a connection point of the first voltage divider resistors218and201is applied to a gate of the NMOS transistor210′.

Furthermore, the reset circuit200D includes a switch circuit214instead of the AND gate211in the reset circuit200A. Note that the NMOS transistor210′ has been described in the second embodiment, and the switch circuit214has been described in the third embodiment, and thus the description thereof is omitted.

Fifth Embodiment

FIG. 7is a circuit block diagram illustrating a reset circuit according to a fifth embodiment. Note that elements of the reset circuit200E that are the same as those of the reset circuit200A are given the same reference numerals, and description of configurations and operations thereof is omitted.

The reset circuit200E includes a resistor215, a diode216including one or more stages, and a second comparator217instead of the pull-up resistor209, the NMOS transistor210, the AND gate211, and the inverter212in the reset circuit200A.

The resistor215and the diode216are connected in series between a power supply voltage Vcc and the ground. A second voltage V2that appears at a connection point of the second voltage divider resistors207and208is applied to a non-inverting input terminal of the second comparator217. A voltage that appears at a connection point of the resistor215and the diode216(a forward voltage that appears across the diode216) is applied as a second reference voltage Vref2to an inverting input terminal of the second comparator217. Then, the second comparator217outputs a detection signal Vdet2at a logic level “L” when the second voltage V2is lower than the second reference voltage Vref2, and outputs a detection signal Vdet2at a logic level “H” when the second voltage V2is higher than the second reference voltage Vref2.

When the power supply voltage Vcc is applied, the second voltage V2rises with a rise in the power supply voltage Vcc, and the second comparator217outputs the detection signal Vdet2at the logic level “H” when the second voltage V2exceeds the forward voltage that appears across the diode216. Herein, resistance values of the second voltage divider resistors207and208and the number of stages of the diode216are previously set such that the second voltage V2does not exceed the forward voltage that appears across the diode216until the power supply voltage Vcc reaches a third level L3that is higher than a first level L1at a time when a first reference voltage Vref1exceeds a first voltage V1and is lower than a second level L2at a time when the first voltage V1reaches a target level of the first reference voltage Vref1.

Note that a Zener diode (not illustrated) including one or more stages may be provided instead of the diode216, and a voltage across the Zener diode may be used as the second reference voltage Vref2. In this case, resistance values of the second voltage divider resistors207and208may be set such that the second voltage V2does not exceed the voltage across the Zener diode until the power supply voltage Vcc reaches the above-described third level L3.

The detection signal Vdet2output from the second comparator217is input to one of input terminals of an AND gate211, and a detection signal Vdet1output from a first comparator205is input to the other input terminal of the AND gate211. In other words, the AND gate211passes and blocks the detection signal Vdet1output from the first comparator205in accordance with a logic level of the detection signal Vdet2output from the second comparator217. For example, when the detection signal Vdet2at the logic level “L” is output from the second comparator217, the AND gate211outputs a reset signal RESET at the logic level “L” regardless of a logic level of the detection signal Vdet1output from the first comparator205. On the other hand, when the detection signal Vdet2at the logic level “H” is output from the second comparator217, the AND gate211outputs, as the reset signal RESET, the detection signal Vdet1at the logic level “H” output from the first comparator205. In this way, when the reset signal RESET at the logic level “H” is output from the AND gate211, the reset of the digital circuit140is released.

Sixth Embodiment

FIG. 8is a circuit block diagram illustrating a reset circuit according to a sixth embodiment. Note that elements of the reset circuit200F that are the same as those of the reset circuit200E are given the same reference numerals, and description of configurations and operations thereof is omitted.

The reset circuit200F includes a switch circuit214instead of the AND gate211in the reset circuit200E.

The switch circuit214is connected between an output terminal of a first comparator205and the ground, and is turned on and off in accordance with a logic level of a detection signal Vdet2output from a second comparator217. For example, when a second voltage V2does not reach a voltage across a diode216, the switch circuit214is turned on by the detection signal Vdet2at a logic level “L” output from the second comparator217. Accordingly, a reset signal RESET fixed at the logic level “L” is output regardless of a logic level of a detection signal Vdet1output from the first comparator205. This causes a digital circuit140to remain in a reset state. On the other hand, when the second voltage V2reaches the voltage across the diode216, the switch circuit214is turned off by the detection signal Vdet2at a logic level “H” output from the second comparator217. Accordingly, the detection signal Vdet1at the logic level output from the first comparator205is output as the reset signal RESET as it is. In this way, when the detection signal Vdet1at the logic level “H” is output from the first comparator205, the reset of the digital circuit140is released.

Summary

As has been described above, the reset circuits200A to200F according to embodiments of the present disclosure include: an output circuit outputs the detection signal Vdet1at the logic level “H” for releasing reset of the digital circuit140to be applied with the power supply voltage Vcc, when the first voltage V1that rises with a rise in the power supply voltage Vcc reaches the first reference voltage Vref1that rises with a rise in the power supply voltage Vcc until the first reference voltage Vref1reaches the target level; and an inhibit circuit that inhibits the detection signal Vdet1at the logic level “H” from being output to the digital circuit140until the power supply voltage Vcc reaches the third level L3that is higher than the first level L1at a time when the first reference voltage Vref1exceeds the first voltage V1and that is lower than the second level L2at a time when the first voltage V1reaches the target level. Then, it is possible to reliably inhibit releasing of the reset of the digital circuit140until the power supply voltage Vcc reaches a stable voltage at which the digital circuit140can normally operate, even when a time period in which the first voltage V1is higher than the first reference voltage Vref1occurs. This can prevent a digital signal OUT from being erroneously output due to unintentional reset operation, and prevent a signal indicative of unintentional reset operation from being output to the outside.

Further, the output circuit includes the first comparator205that compares the first voltage V1produced from the first voltage divider resistors201to203with the first reference voltage Vref1generated from the reference voltage generation circuit204, and outputs the detection signal Vdet1at the logic level “H” serving as a reset release signal for the digital circuit140, the first voltage divider resistors201to203and the reference voltage generation circuit204being configured to be applied with the power supply voltage Vcc. Accordingly, both of the first voltage V1and the first reference voltage Vref1rise with a rise in the power supply voltage Vcc, and thus the output circuit can output the detection signal Vdet1at the logic level “H” when the first voltage V1exceeds the first reference voltage Vref1.

Further, the inhibit circuit includes the NMOS transistor210that operates to inhibit the detection signal Vdet1at the logic level “H” from being output as a reset release signal to the digital circuit140until the second voltage V2produced from the second voltage divider resistors207and208to be applied with the power supply voltage Vcc reaches a threshold voltage set as the second reference voltage Vref2. At this time, each value of the second voltage divider resistors207and208and a threshold voltage of the NMOS transistor210is previously set to a value for inhibiting the detection signal Vdet1at the logic level “H” from being output to the digital circuit140until the power supply voltage Vcc reaches the third level L3. This enables the inhibit circuit to have a simple configuration in which the threshold voltage of the NMOS transistor210is set to the above-described value. Note that an NPN transistor may be provided instead of the NMOS transistor210.

Further, the inhibit circuit may include the NMOS transistor210′ that operates to inhibit the detection signal Vdet1at the logic level “H” from being output as a reset release signal to the digital circuit140until the third voltage V3produced from the connection point of the first voltage divider resistors201and218to be applied with the power supply voltage Vcc reaches a threshold voltage set as the second reference voltage Vref2. At this time, each value of the resistance values of the first voltage divider resistors201to203and218and a threshold voltage of the NMOS transistor210′ is previously set to a value for inhibiting the detection signal Vdet1at the logic level “H” from being output to the digital circuit140until the power supply voltage Vcc reaches the third level L3. This enables the inhibit circuit to have a simple configuration in which each value of the resistance values of the first voltage divider resistors201to203and218used for the first comparator205and the threshold voltage of the NMOS transistor210′ is set to a value described above, in addition to enabling elimination of the second voltage divider resistors207and208. Note that an NPN transistor may be provided instead of the NMOS transistor210′.

Further, the inhibit circuit includes the AND gate211that inhibits the detection signal Vdet1at the logic level

“H” from being output to the digital circuit140, based on the detection signal Vdet2at the logic level “L”. Accordingly, the AND gate211passes and blocks the detection signal Vdet1in accordance with a logic level of the detection signal Vdet2, and thus can output the reset signal RESET at a definite logic level to the digital circuit140.

Further, the inhibit circuit may include the switch circuit214that fixes, at “L”, a logic level of the detection signal Vdet1output from the first comparator205, based on the detection signal Vdet2at the logic level “L”. This makes it possible to output the reset signal RESET at a definite logic level to the digital circuit140.

Further, the inhibit circuit includes the second comparator217that compares the second voltage V2produced from the second voltage divider resistors207and208to be applied with the power supply voltage Vcc, with the voltage across the diode216set as the second reference voltage Vref2, and inhibits the detection signal Vdet1at the logic level “H” from being output to the digital circuit140. At this time, each value of the resistance values of the second voltage divider resistors207and208and the voltage across the diode216is previously set to a value for inhibiting the detection signal Vdet1at the logic level “H” from being output to the digital circuit140until the power supply voltage Vcc reaches the third level L3. This enables the inhibit circuit to have a simple configuration in which the voltage across the diode216is set to a value described above. Note that a Zener diode may be provided instead of the diode216.

Further, the inhibit circuit includes the AND gate211that inhibits the detection signal Vdet1at the logic level “H” from being output to the digital circuit140, based on the detection signal Vdet2at the logic level “L” output from the second comparator217. Accordingly, the AND gate211passes and blocks the detection signal Vdet1in accordance with a logic level of the detection signal Vdet2. This makes it possible to output the reset signal RESET at a definite logic level to the digital circuit140.

Further, the inhibit circuit may include the switch circuit214that fixes, at “L”, a logic level of the detection signal Vdet1output from the first comparator205, based on the detection signal Vdet2output from the second comparator217. This makes it possible to output the reset signal RESET at a definite logic level to the digital circuit140.

Further, the output circuit includes the switch circuit213that sets the first voltage V1to be higher by an amount corresponding to a resistance value of the first voltage divider resistor203, based on the reset signal RESET at the logic level “H” (=the detection signal Vdet1at the logic level “H”) output to the digital circuit140. Accordingly, even when the first voltage V1fluctuates by chattering after releasing the reset of the digital circuit140, a malfunction of the first comparator205can be prevented.

Further, when the digital circuit140, for example, digitally processes a detection output of the pressure sensor110, it is possible to reliably perform the digital processing needed for a pressure detection value of the pressure sensor110.

The above embodiments of the present disclosure are simply for facilitating the understanding of the present disclosure and are not in anyway to be construed as limiting the present disclosure. The present disclosure may variously be changed or altered without departing from its spirit and encompass equivalents thereof.