Continuous time linear equalizer of single-ended signal with input coupling capacitor

A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

BACKGROUND

Field

The technology disclosed relates to improving signals that have suffered channel loss. In particular, the technology disclosed relates to implementing a continuous time linear equalizer on a single-ended signal to compensate for channel loss and also relates to implementing an input buffer on a single-ended signal to compensate for channel loss.

Description of Related Art

Integrated circuits are often configured to receive high-speed data signals, such as double-data-rate DDR signals exceeding gigabits per second. For example, a high-speed receiver can be connected to an input/output pin on an integrated circuit, which is coupled to a transmission line for communication of data among chips.

As the data rates become higher, the pulse width of the input signals becomes smaller (e.g., pulse widths in the hundreds of picoseconds or less). The pulse width is a very important characteristic of some data signals, such as DDR signals where both the rising and falling edges are sensed.

FIG.1provides an illustration100of an ideal input102that has a pulse width of 300 picosecond (ps). As mentioned above, the ideal input102could be an ideal signal connected to an output pin on an integrated circuit. However, as the ideal input102is provided to a circuit103, channel loss104can cause the pulse width of the ideal input102to change from 300 ps to 200 ps. This channel loss is not ideal. A conventional continuous time linear equalizer (CTLE) circuit106can be implemented to correct for the channel loss and provide a much cleaner pulse width signal that has a 300 ps pulse width, which matches the ideal input102. However, conventional CTLE circuits106have a problem in that the AC gain that can be provided is limited by the DC gain that can be achieved by the circuit. Therefore, it is desirable to provide a CTLE circuit (or input buffer) that is suitable for use in integrated circuits, which is operable at high speeds, with low distortion and that can provide an AC gain that is not limited by the DC gain.

SUMMARY

A continuous time linear equalizer (CTLE) circuit is described. The CTLE circuit a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage. The CTLE circuit further includes a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

According to an embodiment, the second coupling capacitor can be connected between the source of the second transistor and ground.

According to a further embodiment, the CTLE circuit can further comprise a first drain-side capacitor connected between the drain of the first transistor and ground.

In another embodiment, the CTLE circuit can include a second drain-side capacitor connected between the drain of the second transistor and ground.

In an embodiment, a capacitance value of the first drain-side capacitor can be the same as or similar to a capacitance value of the second drain-side capacitor.

In a further embodiment, a capacitance value of the first coupling capacitor can be the same as or similar to a capacitance value of the second coupling capacitor.

According to another embodiment, the source of the first transistor can be connected to a first current source providing a first biasing current.

According to an embodiment, the source of the second transistor can be connected to a second current source providing a second biasing current that is the same as or different from the first biasing current.

In a further embodiment, a first differential output voltage of the differential pair is provided from the drain of the first transistor.

In another embodiment a second differential output voltage of the differential pair can be provided from the drain of the second transistor and the first differential output voltage can be a negative voltage component of the differential pair and the second differential output voltage can be a positive voltage component of the differential pair.

According to an embodiment, when the input voltage surpasses a frequency threshold, the first transistor can operate in a common gate mode and the first differential output voltage can provide an alternating current (AC) gain that is greater than a direct current (DC) gain of the CTLE circuit.

According to a further embodiment, the DC gain can be determined by setting a value of the source resistor to 0 ohms.

According to another embodiment, the amplifier architecture of the CTLE circuit can be used in operational amplifiers, such as a two-stage operational amplifier and a fold-cascade operational amplifier.

In a further embodiment, the first and second coupling capacitors can be one of a metal-oxide-semiconductor capacitor (MOSCAP), a metal-insulator-metal capacitor (MIMCAP) and a multi-layer ceramic capacitor (MLCC).

In another embodiment, a memory device is provided to include the above-described CTLE circuit as a receiver circuit.

According to an embodiment, the memory can be one of static random access memory (SRAM), NAND flash memory, NOR flash memory, resistive random access memory (RRAM), magnetoresistive random access memory (MRAM) and phase change random access memory (PCRAM).

According to a further embodiment, an input buffer circuit is provided. The input buffer circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected to a current source, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, and a coupling capacitor connected between the source of the second transistor and the input voltage.

In an embodiment, the input buffer circuit can further include a first drain-side capacitor connected between the drain of the first transistor and ground and a second drain-side capacitor connected between the drain of the second transistor and ground.

In another embodiment, in the input buffer circuit, a capacitance value of the first drain-side capacitor can be the same as or similar to a capacitance value of the second drain-side capacitor.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to theFIGS.1to14.

FIG.2is a dB (gain) vs. frequency diagram illustrating implementation of a CTLE to account for channel loss.

Specifically,FIG.2illustrates a dB (gain) vs. frequency diagram200, with dB gain on the y-axis and frequency on the x-axis. As illustrated, channel loss202can begin at a certain frequency203when a signal is transmitted and/or received from/by circuitry. In this example, the circuitry causing the channel loss202is essentially acting as a low-pass filter. Specifically, after frequency203the dB gain of the channel loss signal202drastically decreases. The diagram200also illustrates a frequency response204of an equalizer, such as an CTLE. As illustrated, the frequency response204of the equalizer actually further amplifies a signal between frequency203and frequency205. As further illustrated in the diagram200, by applying the equalizer to the channel loss signal202, the overall206output can be improved, such that dB loss does not appear until around frequency207.

FIG.3is a circuit diagram of an example of a conventional CTLE circuit.

Specifically,FIG.3illustrates a conventional CTLE circuit300that can be used to compensate for channel loss. The conventional CTLE circuit300includes a differential pair of transistors, including a first M1transistor304and a second M2transistor302. The first M1transistor304and the second M2transistor302are illustrated as MOSFET n-channel transistors. However, they can also be other types of transistors such as MOSFET p-channel transistors, JFET n- or p-channel transistors or any other type of transistors known to those skilled in the art.

As illustrated, a drain of the first M1transistor304is connected to a drain resistor RD308. In a similar manner, a drain of the second M2transistor302is connected to a drain resistor RD306. Typically, the drain resistor RD308and the drain resistor RD306have a same resistance value, but they can be different from one another. Both the drain resistor RD308and the drain resistor RD306are connected to a drain-side supply voltage node310that supplies a voltage of VDD.

A gate of the second M2transistor302is connected to VIN312, which is a (single ended) voltage input signal (or input voltage) for which continuous time liner equalization is to be applied by the CTLE circuit300. As an example, the input voltage signal can have values ranging from tens of millivolts (mVs) to hundreds of mVs at frequencies ranging from 1 gigahertz (GHz) to 10 GHz (although lower frequency operations can be common). A gate of the first M1transistor304is connected to VREF314, which is a reference voltage. In an example, VREF314can have different values depending on whether a center tapped termination (CTT) or a low tapped termination (LTT) is implemented. More specifically, for example, for a CTT implementation, VREF314can be the power supply voltage used by the circuit (VCCQ) divided by 2 and for an LTT implementation, VREF314can be VCCQ divided by 3.

The differential pair of transistors can provide a differential output signal (output voltage) including VOUTP316, which can be a positive portion of the differential output signal and including VOUTN318, which can be a negative portion of the differential output signal. Therefore, this conventional CTLE circuit300provides a differential output signal (output voltage) from a single-ended voltage input signal (voltage input) to compensate for channel loss. VOUTP316is connected to the drain of the M2transistor302(between the drain resistor RD306and the drain of the M2transistor302).

A capacitor CP320is also connected between the drain of the M2transistor302and ground. Similarly, VOUTN318is connected to the drain of the M1transistor304(between the drain resistor RD308and the drain of the M1transistor304). A capacitor CP322is also connected between the drain of the M1transistor304and ground.

A current I2324, such as a biasing current is applied to a source of the M2transistor302and a current I1326, such as a biasing current is applied to a source of the M1transistor304. The sources of both the M1transistor304and the M2transistor302are connected to a source resistor RS326and a source capacitor CS328, which are arranged in parallel. The values of source resistor RS326and a source capacitor CS328can be used to determine/set a zero frequency.

Alternatively, the conventional CTLE circuit300can receive a differential input, such that the gate of transistor M1transistor304receives one portion of a differential input signal, as opposed to VREF.

Characteristics and the transfer function of the conventional CTLE circuit300are defined as follows:

H⁡(s)=gmCp⁢s+1RS⁢CS(s+1+gm⁢RS2RS⁢CS)⁢(s+1RD⁢Cp),
where gmrepresents the known gain of the M1transistor304and the M2transistor302.

Accordingly, the DC gain of the CTLE circuit300can equal

gm⁢RD1+gm⁢RS/2,
and the ideal peak gain of the CTLE circuit300can equal gmRD(RS=0). Further, ideal peaking of the CTLE circuit300can equal

As mentioned above, a limitation of the conventional CTLE circuit300is that the AC gain cannot surpass the DC gain and amplification at higher frequencies is diminished (e.g., AC amplification is diminished at frequencies that surpass the wp2high-frequency pole (non-dominant pole)). For example, at frequencies that surpass the wp2, the frequency gain could be −20 db/decade. The value of the source resistor RS326can be adjusted to obtain different peak gains. Further, for simulation purposes, the DC gain can be determined by setting the value of the source resistor RS326 to 0 ohms. In the CTLE circuit300the maximum AC gain can only reach the gain that is achieved by setting the value of the source resistor RS326 to 0 ohms and (as described above) the AC gain diminishes at frequencies above the wp2.

FIG.4is a dB (gain) vs. frequency diagram illustrating DC gain and AC gain achieved by a conventional CTLE circuit.

Specifically,FIG.4illustrates a diagram400showing dB (gain) vs. frequency for a simulation representing DC gain and illustrates a diagram402showing dB (gain) vs. frequency representing AC gain. As explained above with reference toFIG.3, the DC gain can be determined by setting the value of the source resistor RS326 to 0 ohms. As illustrated in diagram400, the differential Vdbsignal404resulting from a combination of Vdb406and Vdb408provides a maximum DC gain410of about 14.4 dB, where the gain begins to diminish above 1 Ghz.

Further, as illustrated in diagram402, the differential Vdbsignal412resulting from a combination of Vdb414and Vdb416provides a maximum AC gain418of about 14.2 dB, which is less than the maximum DC gain410of about 14.4 dB, where the gain peaks around 500 Mhz.

Accordingly, there is a need for an improved CTLE circuit that is able to provide an AC gain that is higher than the DC gain, which cannot be achieved by the conventional CTLE circuit300.

FIG.5is a circuit diagram of an example of a CTLE circuit according to the technology disclosed.

Specifically,FIG.5illustrates a CTLE circuit500that includes two charge coupling capacitors CCP530and532. Before describing the coupling capacitors CCP530and532, other portions of the CTLE circuit will be described.

This improved CTLE circuit500includes a differential pair of transistors, including a first M1transistor504and a second M2transistor502. The first M1transistor504and the second M2transistor502are illustrated as MOSFET n-channel transistors. However, they can also be other types of transistors such as MOSFET p-channel transistors, JFET n- or p-channel transistors or any other type of transistors known to those skilled in the art.

As illustrated, a drain of the first M1transistor504is connected to a drain resistor RD508. In a similar manner, a drain of the second M2transistor502is connected to a drain resistor RD506. Typically, the drain resistor RD508and the drain resistor RD506have a same resistance value, but they can be different from one another. Both the drain resistor RD508and the drain resistor RD506are connected to a drain-side supply voltage node510that supplies a voltage of VDD. The drain resistors RD508and506can be variable resistors.

A gate of the second M2transistor502is connected to VIN512, which is a (single ended) voltage input signal (or input voltage) for which continuous time liner equalization is to be applied by the CTLE circuit500. The input voltage signal can typically have values ranging from tens of mVs to hundreds of mVs at frequencies ranging from 1 GHz to 10 GHz (although lower frequency operations can be implemented). A gate of the first M1transistor504is connected to VREF514, which is a reference voltage. In an example, VREF514can have different values depending on whether a CTT or an LTT is implemented. More specifically, for example, for a CTT implementation, VREF514can be VCCQ divided by 2 and for an LTT implementation, VREF514can be VCCQ divided by 3.

The differential pair of transistors can provide a differential output signal (output voltage) including VOUTP516, which can be a positive portion of the differential output signal and including VOUTN518, which can be a negative portion of the differential output signal. Therefore, this CTLE circuit500provides a differential output signal (output voltage) from a single-ended voltage input signal (voltage input) to compensate for channel loss. VOUTP516is connected to the drain of the M2transistor502(between the drain resistor RD506and the drain of the M2transistor502). A capacitor CP520is also connected between the drain of the M2transistor502and ground. Similarly, VOUTN518is connected to the drain of the M1transistor504(between the drain resistor RD508and the drain of the M1transistor504). A capacitor CP522is also connected between the drain of the M1transistor504and ground.

A current I2526, such as a biasing current is applied to a source of the M2transistor502and a current I1528, such as a biasing current is applied to a source of the M1transistor504. The biasing current of I2526can be the same as or different from the biasing current of I1528. Rather than using two current sources, such as current I2526and current I1528, as single (biasing) current can be applied to the sources of both the M1transistor504and the M2transistor502. The sources of both the M1transistor504and the M2transistor502are connected to a source resistor RS524.

A difference between the conventional CTLE circuit300and the CTLE circuit500, is that the CTLE circuit500does not include the source capacitor CS328, but rather includes the two coupling capacitors CCP530and532. The coupling capacitor CCP532is connected between VIN512and the source of the M1transistor504and in series with the source resistor RS524. The coupling capacitor CCP530is connected between ground and the source of the M2transistor502and in series with the source resistor RS524. The two coupling capacitors CCP530and532can have the same or similar capacitance values, can be selected to provide similar or different frequency responses within the CTLE circuit and can be selected to provide specific or similar electrical characteristics. The zero-pole (“zero”) frequency can be calculated as

ωZ=1RS⁢CC⁢P.
The coupling capacitors CCP530and532and the source resistor RS524can essentially form an RC element that inserts a zero in the frequency response of the circuit that enhances amplification of higher frequencies compared to lower frequencies, to compensate for the channel loss, wherein the “zero” can be moved around by adjusting the values of the coupling capacitors CCP530and532and the source resistor RS524.

When the input voltage VIN512surpasses a frequency threshold (which is dictated, in part, by the values of the coupling capacitors CCP530and532), the first M1transistor504operates in the common gate mode and the differential output voltages VOUTN518and VOUTP516provides an AC gain that is greater than a DC gain of the CTLE circuit500. Input voltages to place the first M1transistor504into a common gate mode will be apparent to those skilled in the art. When VIN512is at a high enough frequency, coupling capacitors CCP530and532act as a “short,” which will put M1transistor504in the common gate stage at the zero frequency (WZ). In other words, when VIN512is a low frequency signal (e.g., a DC signal), the coupling capacitors CCP530and532can act as an “open circuit,” such that VIN512does not couple to the reference side of the CTLE circuit500, but when VIN512is a sufficiently high frequency, VIN512does couple to the reference side, where the capacitor impedance of the coupling capacitor CCP532(for example) is

ZC=1jwC.
Based on the desired implementation, the frequency at which AC peak gain is achieved can be adjusted by changing the values of the coupling capacitors CCP530and532. For example, a higher value for the coupling capacitors CCP530and532will result is a lower frequency at which AC peak gain is achieved and a lower value for the coupling capacitors CCP530and532will result in a higher frequency at which AC peak gain is achieved. For further example, the peak AC gain can be calculated as (gm*RD)+(gm*RD), where gmcan be from, for example, M1transistor504. In other words, the peak AC gain can be (2*gm*RD). As discussed above, the DC gain of the CTLE circuit500can be obtained by setting the value of the source resistor RS524to 0 ohms. The DC gain can be calculated as gmRD/(1+gmRS/2).

The coupling capacitors CCP530and532can be one of a metal-oxide-semiconductor capacitor (MOSCAP), a metal-insulator-metal capacitor (MIMCAP) and a multi-layer ceramic capacitor (MLCC) or any other type of capacitor available to those of skill in the art.

FIG.6is a dB (gain) vs. frequency diagram illustrating DC gain and AC gain achieved by the CTLE circuit according to the technology disclosed.

Specifically,FIG.6illustrates a diagram600showing dB (gain) vs. frequency for a simulation representing DC gain and illustrates a diagram602showing dB (gain) vs. frequency representing AC gain. DC gain can be determined by setting the value of the source resistor RS524 to 0 ohms. As illustrated in diagram600, the differential Vdbsignal604resulting from a combination of Vdb606and Vdb608provides a maximum DC gain610of about 14.4 dB, where the gain begins to diminish above 1 Ghz.

Further, as illustrated in diagram602, the differential Vdbsignal612resulting from a combination of Vdb614and Vdb616provides a maximum AC gain618of about 19.3 dB, which is greater than the DC gain610of 14.4 dB, where the gain peaks just above 1 Ghz. The CTLE circuit500can thus achieve an AC gain that is greater than the DC gain, which cannot be achieved by a conventional CTLE circuit.

FIG.7illustrates an ideal input, channel loss, a result from applying the channel loss signal to a conventional CTLE circuit and a result from applying the channel loss signal to a CTLE circuit according to the technology disclosed.

Specifically,FIG.7illustrates a diagram700that includes an ideal input signal702, and a channel loss signal704resulting in channel loss to the ideal input signal702. As can be seen, the high and low values of the channel loss signal704are not ideal, which can result in incorrect or reduced frequencies.

The diagram700ofFIG.7further illustrates an output signal706resulting from the use of the conventional CTLE circuit300to correct for the channel loss. The diagram700also illustrates an improved output signal708that is provided by the improved CTLE circuit500. As illustrated, the transient time and the amplitudes of the improved output signal708are much better than the transient time and the amplitudes of the output signal706from the conventional CTLE circuit300.

FIG.8illustrates a process corners eye graph for both a conventional CTLE circuit and a CTLE circuit according to the technology disclosed.

Specifically,FIG.8illustrates a diagram800that provides eye graphs for both the conventional CTLE circuit300and the improved CTLE circuit500for various process corners, such as typical-typical (TT), fast-fast (FF) and slow-slow (SS). As illustrated, the upper row802of the diagram800provides eye graphs for the TT corner804, the FF corner806and the SS corner808, and the lower row810of the diagram800provides eye graphs for the TT corner812, the FF corner814and the SS corner816. In this example, the input data rate was 2.4 Gb/s. As illustrated in each of the TT corner804, the FF corner806and the SS corner808there is significant variation between signals, when compared to the variation between signals in the TT corner812, the FF corner814and the SS corner816.

Further, the width of TT corner804is 383 ps, the height of TT corner804is 179 mV, the width of FF corner806is 383 ps, the height of FF corner806is 180 mV, the width of SS corner808is 378 ps and the height of SS corner808is 176 mV. The width of TT corner812is 407 ps, the height of TT corner812is 244 mV, the width of FF corner814is 407 ps, the height of FF corner814is 241 mV, the width of SS corner816is 406 ps and the height of SS corner816is 242 mV. As illustrated, the widths of the improved CTLE circuit500having a range from 406 ps to 407 ps is better than the widths of the conventional CTLE circuit300having a range from 378 ps to 383 ps. Further, the high frequency AC gain (and DC gain) of the improved CTLE circuit500, which is exemplified by the heights of 241 mV to 244 mV, is better than the high frequency AC gain (and DC gain) of the conventional CTLE circuit300, which is exemplified by the heights of 176 mV to 180 mV.

FIG.9illustrates an input buffer that receives a single ended input signal and outputs a differential output signal.

Specifically,FIG.9illustrates an input buffer circuit900that can receive an input signal (e.g., an ideal pulse, small signal pulse, small swing signal, etc.). This input buffer circuit900includes a differential pair of transistors, including a first M1transistor904and a second M2transistor902. The first M1transistor904and the second M2transistor902are illustrated as MOSFET n-channel transistors. However, they can also be other types of transistors such as MOSFET p-channel transistors, JFET n- or p-channel transistors or any other type of transistors known to those skilled in the art.

As illustrated, a drain of the first M1transistor904is connected to a drain resistor RD908. In a similar manner, a drain of the second M2transistor902is connected to a drain resistor RD906. Typically, the drain resistor RD908and the drain resistor RD906have a same resistance value, but they can be different from one another. Both the drain resistor RD908and the drain resistor RD906are connected to a drain-side supply voltage node910that supplies a voltage of VDD.

A gate of the second M2transistor902is connected to VIN912, which is a (single ended) voltage input signal (or input voltage) for which signal amplification is to be applied by the input buffer circuit900. The input voltage signal can typically have values ranging from tens of m Vs to hundreds of mVs at frequencies ranging from hundreds of megahertz (MHz) to several GHz (in an example, the frequencies can be less than that received by CTLE circuits). A gate of the first M1transistor904is connected to VREF914, which is a reference voltage. In an example, VREF914can have different values depending on whether a CTT or an LTT is implemented. More specifically, for example, for a CTT implementation, VREF914can be VCCQ divided by 2 and for an LTT implementation, VREF914can be VCCQ divided by 3.

The differential pair of transistors can provide a differential output signal (output voltage) including VOUTP916, which can be a positive portion of the differential output signal and including VOUTN918, which can be a negative portion of the differential output signal. Therefore, this input buffer circuit900provides a differential output signal (output voltage) from a single-ended voltage input signal (voltage input). The output voltage can be provided to a next stage amplifier or a receiver circuit, for example. VOUTP916is connected to the drain of the M2transistor902(between the drain resistor RD906and the drain of the M2transistor902). A capacitor CP920is also connected between the drain of the M2transistor902and ground. Similarly, VOUTN918is connected to the drain of the M1transistor904(between the drain resistor RD908and the drain of the M1transistor904). A capacitor CP922is also connected between the drain of the M1transistor904and ground.

A current Ibias924is applied to a source of the M2transistor902as well as a source of the M1transistor904. The input buffer circuit900is able to amplify the VIN912signal to provide a differential voltage output signal as VOUTP916and VOUTN918that has an increased amplitude for certain frequencies. However, this input buffer circuit900is limited in the sense that at higher frequencies, the amplification is diminished and at higher frequencies the voltage output signals VOUTP916and VOUTN918are not balanced. For example, when the input buffer circuit900receives an input that is near the gigahertz range, the VOUTP916and VOUTN918will become unbalanced and cause eye diagram loss (discussed below). Because the Ibias924can have an effect of parasitic capacitance, it can affect a speed at which the VIN912is transmitted to VOUTP916and VOUTN918, resulting in (high-speed) operation distortion. More specifically, when VIN902changes, the source nodes of M1transistor904and M2transistor902will also change (e.g., in a same direction). Therefore, when VIN902rises, the source node will also rise to a certain voltage (e.g., when the frequency is not too fast), because the VGS of M2transistor902increases, VOUTP916will decrease, and the VGS of M1transistor904will decrease so that VOUTN918will increase, and vice versa if VIN902decreases. However, if the frequency is high enough (e.g., in the gigahertz range), the source side responses of M1transistor904and M2transistor902will be affected by the parasitic capacitance, and the response will be slow, which will lead to an unbalanced response between VOUTP916and VOUTN918

FIG.10illustrates an input buffer including a coupling capacitor that receives a single ended input signal and outputs a differential output signal according to the technology disclosed.

Specifically,FIG.10illustrates an improved input buffer circuit1000that includes a coupling capacitor that can receive an input signal (e.g., an ideal pulse, small signal pulse, small swing signal, etc.). This input buffer circuit1000includes a differential pair of transistors, including a first M1transistor1004and a second M2transistor1002. The first M1transistor1004and the second M2transistor1002are illustrated as MOSFET n-channel transistors. However, they can also be other types of transistors such as MOSFET p-channel transistors, JFET n- or p-channel transistors or any other type of transistors known to those skilled in the art.

As illustrated, a drain of the first M1transistor1004is connected to a drain resistor RD1008. In a similar manner, a drain of the second M2transistor1002is connected to a drain resistor RD1006. Typically, the drain resistor RD1008and the drain resistor RD1006have a same resistance value, but they can be different from one another. Both the drain resistor RD1008and the drain resistor RD1006are connected to a drain-side supply voltage node1010that supplies a voltage of VDD.

A gate of the second M2transistor1002is connected to VIN1012, which is a (single ended) voltage input signal (or input voltage) for which signal amplification is to be applied by the input buffer circuit1000. The input voltage signal can typically have values ranging from tens of mVs to hundreds of mVs at frequencies ranging from hundreds of megahertz (MHz) to several GHz (in an example, the frequencies can be less than that received by CTLE circuits). A gate of the first M1transistor1004is connected to VREF1014, which is a reference voltage. In an example, VREF1014can have different values depending on whether a CTT or an LTT is implemented. More specifically, for example, for a CTT implementation, VREF1014can be VCCQ divided by 2 and for an LTT implementation, VREF1014can be VCCQ divided by 3.

The differential pair of transistors can provide a differential output signal (output voltage) including VOUTP1016, which can be a positive portion of the differential output signal and including VOUTN1018, which can be a negative portion of the differential output signal. Therefore, this input buffer circuit1000provides a differential output signal (output voltage) from a single-ended voltage input signal (voltage input). The output voltage can be provided to a next stage amplifier or a receiver circuit, for example. VOUTP1016is connected to the drain of the M2transistor1002(between the drain resistor RD1006and the drain of the M2transistor1002). A capacitor CP1020is also connected between the drain of the M2transistor1002and ground. Similarly, VOUTN1018is connected to the drain of the M1transistor1004(between the drain resistor RD1008and the drain of the M1transistor1004). A capacitor CP1022is also connected between the drain of the M1transistor1004and ground.

A current Ibias1024is applied to a source of the M2transistor1002as well as a source of the M1transistor1004. A coupling capacitor CCP1026is connected between the gate and the source of the M2transistor1002, such that the coupling capacitor CCP1026receives VIN1012as it is applied to the gate of the M2transistor1002. The coupling capacitor CCP1026can be one of a metal-oxide-semiconductor capacitor (MOSCAP), a metal-insulator-metal capacitor (MIMCAP) and a multi-layer ceramic capacitor (MLCC), or any other type of capacitor available to those of skill in the art.

The coupling capacitor CCP1026provides a benefit, such that as VIN1012increases in frequency the coupling capacitor CCP1026acts as a short to the drain of the M2transistor1002and puts the M2transistor1002into a common gate mode, which will increase the AC gain applied to VIN1012. Additionally, this input buffer circuit1000provides a benefit of an input buffer circuit that has a more balanced differential outputs (VOUTN1018and VOUTP1016) at higher frequencies, which cannot be achieved by the input buffer circuit900. For example, as described above with reference toFIG.9, the input buffer circuit900provides an unbalanced response between VOUTP916and VOUTN918at higher frequencies (e.g., frequencies in the gigahertz range). The input buffer circuit900and the input buffer circuit1000can have the same or similar AD and DC gains, but the input buffer circuit1000can provide a more balanced output than the input buffer circuit900.

The use of the CCP1026can compensate the source for the M1transistor1004and M2transistor1002responses when operating at sufficiently high frequencies (e.g., frequencies in the low gigahertz range and/or high megahertz range). The parasitic capacitance effect of Ibias1024can be compensated by the CCP1026so that the input VIN1026response at high frequency is more balanced (i.e., VOUTP1016and VOUTN1018are more balanced) as opposed to the differential output of the input buffer circuit900, resulting in an eye diagram that is closer to the ideal pulse width.

Accordingly, the input buffer circuit1000is able to amplify the VIN1012signal and provide a differential voltage output signal as VOUTP1016and VOUTN1018that has an increased amplitude for certain frequencies with better balance.

FIG.11illustrates a process corners eye graph for both an input buffer and an input buffer with a coupling capacitor according to the technology disclosed.

Specifically,FIG.11illustrates a diagram1100that provides eye graphs for both the input buffer circuit900without a coupling capacitor and the input buffer circuit1000with the coupling capacitor for various process corners, such as typical-typical (TT), fast-fast (FF) and slow-slow (SS).FIG.11illustrates that the input buffer circuit1000provides a more balanced effect with an input data rate for the eye chart at 3.6 Gb/s and a pulse width of about 277.7 ps with minimal to no channel loss As illustrated, the upper row1102of the diagram1100provides eye graphs for the TT corner1104, the FF corner1106and the SS corner1108, and the lower row1110of the diagram1100provides eye graphs for the TT corner1112, the FF corner1114and the SS corner1116. As illustrated in each of the TT corner1104, the FF corner1106and the SS corner1108there is significant more variation between signals, when compared to the variation between signals in the TT corner1112, the FF corner1114and the SS corner1116corresponding to the input buffer circuit1000with the coupling capacitor.

Further, the width of TT corner1104is 266 ps, the height of TT corner1104is 777 mV, the width of FF corner1106is 265 ps, the height of FF corner1106is 686 mV, the width of SS corner1108is 267 ps and the height of SS corner1108is 828 mV. The width of TT corner1112is 271 ps, the height of TT corner1112is 756 mV, the width of FF corner1114is 272 ps, the height of FF corner1114is 798 mV, the width of SS corner1116is 272 ps and the height of SS corner1116is 818 mV. As illustrated, the widths of the input buffer circuit1000(row1110) with the coupling capacitor having a range from 271 ps to 272 ps is better than the widths of the input buffer circuit900(row1102) having a range from 265 ps to 267 ps.

FIG.12is a dB (gain) vs. frequency diagram illustrating a differential output (voutp, voutn) of a simulation of the input buffer ofFIG.9and the input buffer ofFIG.10that includes a coupling capacitor.

Specifically,FIG.12illustrates a dB (gain) vs. frequency diagram1200of (i) a conventional input buffer circuit, such as the input buffer circuit900, and (ii) a proposed input buffer circuit, such as the input buffer circuit1000(in response to a particular AC input). The diagram1200illustrates the differential outputs (combination of voutp and voutn) of, for example, the input buffer circuit900and the input buffer circuit1000. As illustrated the differential outputs of both circuits are very similar, if not identical. In other words, the AC gain for both the input buffer circuits900and1000are very similar, if not identical. However, as discussed below in more detail, the output of the input buffer circuit1000is more balanced than the output of the input buffer circuit900.

FIG.13is a dB (gain) vs. frequency diagram illustrating individual positive (Voutp) and negative (Voutn) output signals of a simulation of the input buffer ofFIG.9and the input buffer ofFIG.10that includes a coupling capacitor.

Specifically, the top graph ofFIG.13illustrates a dB (gain) vs. frequency diagram1300of (i) a positive component output (Voutp) of a conventional input buffer circuit, such as the input buffer circuit900and (ii) a positive component output (Voutp) of a proposed input buffer circuit, such as the input buffer circuit1000(in response to the same particular AC input referred to inFIG.12). As illustrated inFIG.13, even though the differential outputs of both circuits are the same (as explained above with reference toFIG.12), the Voutp of, for example, the input buffer circuit900, is different from the Voutp of, for example the input buffer circuit1000. The Voutp of the (conventional) input buffer circuit900is illustrated by a solid line and the Voutp of the (proposed) input buffer circuit1000is illustrated by a dashed line.

Additionally, the bottom graph ofFIG.13illustrates a dB (gain) vs. frequency diagram1300of (i) a negative component output (Voutn) of a conventional input buffer circuit, such as the input buffer circuit900and (ii) a negative component output (Voutn) of a proposed input buffer circuit, such as the input buffer circuit1000(in response to the same particular AC input referred to inFIG.12). As illustrated inFIG.13, even though the differential outputs of both circuits are the same (as explained above with reference toFIG.12), the Voutn of, for example, the input buffer circuit900, is different from the Voutn of, for example the input buffer circuit1000. The Voutn of the (conventional) input buffer circuit900is illustrated by a solid line and the Voutp of the (proposed) input buffer circuit1000is illustrated by a dashed line.

FIG.14is a dB (gain) vs. frequency diagram illustrating individual positive (voutp) and negative (voutn) output signals of a simulation of the input buffer ofFIG.9and the input buffer ofFIG.10that includes a coupling capacitor.

Specifically, the top graph ofFIG.14illustrates a dB (gain) vs. frequency diagram1400of (i) a positive component output (voutp) of a conventional input buffer circuit, such as the input buffer circuit900and (ii) a negative component output (voutn) of a proposed input buffer circuit, such as the input buffer circuit900(in response to the same particular AC input referred to inFIG.12). As illustrated inFIG.14, the voutn and the voutp of the input buffer circuit900become very unbalanced at higher frequencies.

Additionally, the bottom graph ofFIG.14illustrates a dB (gain) vs. frequency diagram1400of (i) a negative component output (voutn) of a proposed input buffer circuit, such as the input buffer circuit1000and (ii) a positive component output (voutp) of a proposed input buffer circuit, such as the input buffer circuit1000(in response to the same particular AC input referred to inFIG.12). As illustrated inFIG.14, the voutn and the voutp of the input buffer circuit1000are more balanced at higher frequencies than the voutn and the voutp of the input buffer circuit900.