Magnetic random access memory (MRAM) manufacturing process for a small magnetic tunnel junction (MTJ) design with a low programming current requirement

A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

FIELD OF THE INVENTION

The present invention relates generally to non-volatile magnetic random access memory and particularly to a method for manufacturing memory cells for non-volatile magnetic random access memory incorporating a small magnetic tunnel junction (MTJ).

DESCRIPTION OF THE PRIOR ART

Computers conventionally use rotating magnetic media, such as hard disk drives (HDDs), for data storage. Though widely used and commonly accepted, such media suffer from a variety of deficiencies, such as access latency, higher power dissipation, large physical size and inability to withstand any physical shock. Thus, there is a need for a new type of storage device devoid of such drawbacks.

Other dominant storage devices are dynamic random access memory (DRAM) and static RAM (SRAM) which are volatile and very costly but have fast random read/write access time. Solid state storage, such as solid-state-nonvolatile-memory (SSNVM) devices having memory structures made of NOR/NAND-based Flash memory, providing fast access time, increased input/output (IOP) speed, decreased power dissipation and physical size and increased reliability but at a higher cost which tends to be generally multiple times higher than hard disk drives (HDDs).

Although NAND-based flash memory is more costly than HDD's, it has replaced magnetic hard drives in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices due, at least in part, to its characteristic of being able to retain data even when power is disconnected. However, as memory dimension requirements are dictating decreased sizes, scalability is becoming an issue because the designs of NAND-based Flash memory and DRAM memory are becoming difficult to scale with smaller dimensions. For example, NAND-based flash memory has issues related to capacitive coupling, few electrons/bit, poor error-rate performance and reduced reliability due to decreased read-write endurance. Read-write endurance refers to the number of reading, writing and erase cycles before the memory starts to degrade in performance due primarily to the high voltages required in the program, erase cycles.

It is believed that NAND flash, especially multi-bit designs thereof, would be extremely difficult to scale below 45 nanometers. Likewise, DRAM has issues related to scaling of the trench capacitors leading to very complex designs which are becoming increasingly difficult to manufacture, leading to higher cost.

Currently, applications commonly employ combinations of EEPROM/NOR, NAND, HDD, and DRAM as a part of the memory in a system design. Design of different memory technology in a product adds to design complexity, time to market and increased costs. For example, in hand-held multi-media applications incorporating various memory technologies, such as NAND Flash, DRAM and EEPROM/NOR flash memory, complexity of design is increased as are manufacturing costs and time to market. Another disadvantage is the increase in size of a device that incorporates all of these types of memories therein.

There has been an extensive effort in development of alternative technologies such as Ovanic Ram (or phase-change memory), Ferromagnetic Ram (FeRAM), Magnetic Ram (MRAM), Nanochip, and others to replace memories used in current designs such as DRAM, SRAM, EEPROM/NOR flash, NAND flash and HDD in one form or another. Although these various memory/storage technologies have created many challenges, there have been advances made in this field in recent years. MRAM seems to lead the way in terms of its progress in the past few years to replace all types of memories in the system as a universal memory solution. MRAM provides the advantages of a high density memory, non-volatility and low power consumption.

MRAM presently faces scalability challenges. For wide adoption of MRAM as a universal memory solution, MRAM technology must be scaled down. Generally, smaller memory cells have the advantageous benefits of placing more memory cells in the same physical space, and the memory is likely to be faster.

A magnetic memory cell is comprised of two components; a magnetic tunnel junction (MTJ) and an access transistor.

A MTJ further consists of two layers of magnetic metal, such as cobalt-iron, separated by an ultrathin layer of insulator, made of magnesium oxide, with a thickness of about 1 nm. The insulating layer is so thin that electrons can tunnel through the barrier if a bias voltage is applied between the two metal electrodes. In MTJs the tunneling current depends on the relative orientation of magnetizations of the two magnetic metal layers, which can be changed by an applied magnetic field. This phenomenon is called tunneling magneto-resistance (TMR).

The access transistor consists of a source drain and a gate. An n-channel field-effect transistor (FET) is commonly used for accessing the MTJ.

The basic concept of MRAM is to use the magnetization direction in MTJs for information storage. “0” and “1” correspond to parallel and anti-parallel magnetizations orientation in a MTJ. The information bits can be written by passing a current through a MTJ, and they can be read out by measuring the resistance of the MTJ in comparison to a reference resistor or voltage or current. MRAM provides the advantages of a high density, non-volatility and low power consumption.

For MRAM to be competitive with other forms of alternative RAM technologies, especially DRAM, the MTJ must be made very small. Smaller MTJs advantageously program with smaller currents and produce smaller cell size. However, smaller MTJ designs are not without problems. Since a MTJ can be defined as a small island, a similarly small piece of photo-resist (PR) needs to be defined for the definition of the MTJ. Such a small resist column is very unstable, and is susceptible to easily toppling over. At the same time defining photo-resist columns or pillars are difficult and unreliable. It is difficult to reliably and consistently define oval shaped MTJs, without a big size variations and rough edges. Therefore it is important to find a way to change the mask polarity, and to define MTJs as holes in the photo-resist other than long columns. Another problem with having small MTJ size is that since they are at or smaller than the minimum design rule, one can not connect to them with s simple Via.

The area of the MTJ controls how much programming current is required. The larger the area of the MTJ the more programming current needed. Thus, it is advantageous to minimize the size of the MTJ in an effort to reduce its programming current requirement. The programming current is generally supplied to the MTJ by an access transistor coupled to the MTJ. To reduce the area of the MTJ, the length and width of the MTJ may be decreased, but an aspect ratio (the ratio of length to width) is typically greater than one. As the aspect ratio increases, so does the coercive field (Hc). A higher coercive field makes the MTJ more stable with time and temperature, but at the same time increases the required programming current. In fact, the relationship of time to de-stability t to Hc can be written as:
t=t0exp(D) whereD=Hc*V/KTEq. (1)

In this equation V is the volume of the free layer, T is the temperature in degrees Kelvin, K is the Boltezman's constant and t0 is around 1 nSec. For example, if the length and width of the MTJ are 85 and 60 nanometers respectively and MTJ thickness is 3 nanometers, then Hc=85 Oersted and D=50 at room temperature. With a MTJ of these dimensions (85×60 nanometers) it will take more than 100 years for this device to go unstable. Increasing aspect ratio will increase the coercive field, but at the same time makes the device more difficult to program with current.

Thus, the need arises for a manufacturing method for magnetic memory cells which yields a small substantially pillar-shaped MTJ design with a low programming current requirement.

BRIEF SUMMARY OF THE INVENTION

Briefly, a method of the present invention includes A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

The foregoing and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments which make reference to several figures of the drawing.

DETAILED DESCRIPTION

To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a manufacturing method for magnetic memory cells yielding a small MTJ design with a low programming current requirement.

Referring now toFIG. 1, shows a flow-chart of the MRAM manufacturing process100used to manufacture magnetic memory cells. In manufacturing MRAMs, a complimentary metal-oxide-semiconductor (CMOS) as well as logic or magnetic manufacturing processes are employed. That is, the magnetic memory is manufactured using magnetic processes and the logic or transistors used to cause connection with the magnetic memory and other logic for addressing and/or reading and writing to the magnetic memory is manufactured generally using CMOS processes. A plurality of these cells are constructed simultaneously on a single silicon wafer using the MRAM manufacturing process100ofFIG. 1.FIGS. 2-18show cross sections of a single magnetic memory cell as it progresses from Steps18-43.

FIG. 1is shown to include a Step10, during which a CMOS wafer is formed with a dielectric layer. A conductive layer, or M2layer, is also formed in Step10. The formation of this conductive layer (M2layer) may be done by ion beam deposition, electron beam evaporation, sputtering, or by the Cu damascene process. It is noted that other appropriate methods are known to one skilled in the art. In one embodiment of the present invention, the conductive layer is Copper (Cu). Alternatively, the conductive layer may also be made from tungsten, cobalt, titanium, or any other refractory metal, as traditionally used for making contacts.

At step12, alignment marks are etched in the inter-layer dielectric (ILD) for alignment of the MTJ1mask to the conductive layer (M2layer). To form the MTJ, the conductive layer is covered by several metallic layers. Although these layers are very thin, they form an opaque layer, which makes it difficult to see the underlying conductive layer and align the MTJ to the conductive layer. To overcome this problem, a mask and etch technique called a window mask is used. The mask is loosely aligned to the conductive layer, and by etching the oxide around the conductive layer, it creates a depression around the conductive layer in the appropriate MTJ alignment marks, making the metal edges of the conductive layer clearly visible after the deposition of the MTJ layers. Etching of the alignment marks uses the etch-back process, in which photo-resist is applied overtop the layer to be patterned. In an exemplary embodiment of the present invention, a positive photo-resist process is used. In the positive photo-resist process, first a photo-resist layer is applied atop the dielectric layer. Next, the photo-resist layer is exposed to ultraviolet (UV) light, which changes the chemical structure of the photo-resist, making it soluble in a developer. After development, the photo-resist layer shows the opposite pattern which is to remain after etching. Step12further includes oxide etching in which the unwanted dielectric layer is etched away. Plasma etching may be achieved in two possible ways: a physical process method and an assisted physical process method. In the physical process method no chemical agent is employed and there removal of unwanted material is completed by the physical impact of the ions knocking atoms off the material surface by physical force alone. This is called ion milling. In the assisted physical process method, (for example, reactive ion etching (RIE)) removal of material results from a combination of chemical reactions and physical impact. Most commonly, ions are accelerated by a voltage applied to gas plasma in a vacuum. The effect of the ion impact is assisted by the introduction of a chemical which reacts with the surface being etched. Reactive ion etching (RIE), is an example of the assisted physical process method. In an exemplary embodiment of the present invention, RIE is used to etch alignment marks in the ILD alignment of the MTJ1mask to the dielectric layer. Commonly, for RIE, the combination of a fluorine gas (like CF4), Cl2, O2, and argon (Ar) are used. The use of RIE allows for substantially precise removal of the unwanted portions of the dielectric layer, without substantially significant unwanted etching of the underlying silicon wafer.

At Step14, MTJ stack is deposited. The MTJ stack is deposited atop the dielectric layer and on top of conductive layer (M2layer). A minimum amount of copper (Cu) and a minimum amount of tantalum (Ta), typically below 100 nm, is then applied atop the MTJ stack. The Cu is used as a seed for depositing Cu by electrolysis. Tantalum is hard material used for connecting to the MTJ and used as hard mask for etching the MTJ layers. It also isolates the MTJ layer from the other layers on top, in a way that minimizes the impact of the layers on top to the magnetic layers. As alternatives to tantalum, other metals can also be used instead, and include titanium (Ti), ruthenium (Ru), RuCu, and most refractory metals. The MTJ stack includes a pinning layer, on top of which is formed a tunnel layer, and further on top of which is formed a free layer. The MTJ stack layers is further discussed in U.S. patent application Ser. No. 11/674,124, entitled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory,” filed Feb. 12, 2007, by Ranjan, et al.; U.S. patent application Ser. No. 11/678,515, entitled “A High Capacity Low Cost Multi-State Magnetic Memory,” filed Feb. 23, 2007, by Ranjan, et al.; and U.S. patent application Ser. No. 11/776,692, entitled “Non-Volatile Magnetic Memory Element with Graded Layer,” filed Jul. 12, 2007, by Ranjan et al., all of which are incorporated herein by reference as though set forth in full.

At Step16, an oxide layer is deposited atop the tantalum layer. The oxide layer may be deposited using chemical vapor deposition (CVD), sputtering, or any other appropriate method. In an exemplary embodiment of the present invention, silicon dioxide (SiO2), also known as SilOx, is used for the oxide layer. In another exemplary embodiment of the present invention, the thickness of the silicon dioxide layer is approximately 1500 Angstroms thick. In one embodiment, the silicon dioxide layer may alternatively be made of silicon nitride.

At Step17, a photo-resist layer is deposited atop substantially the entire surface of first oxide layer.

At Step18, a portion of the photo-resist layer is removed to form a trench.

At Step19, the oxide layer is etched, using the partial trench to access the oxide layer, to form a trench.

At Step20, the memory cell102is ashed to remove the remaining photo-resist layer.

At Step21, a hard mask layer is deposited. In an exemplary embodiment of the present invention, at Step21the hard mask layer is copper, and the Electrolysis Process is used for deposition. In this process, the underlying silicon dioxide is patterned with open trenches where the conductor will be located. A thick coating of copper that significantly overfills the trenches is deposited on the insulator, and chemical-mechanical planarization or chemical-mechanical polishing (CMP) is used to remove the copper to the level of the top of the insulating layer. Copper sunken within the trenches of the insulating layer is not removed and becomes the patterned conductor.

At Step22, a hard mask layer and an oxide layer are planarized. The planarization process is used to smooth the top surface of the hard mask layer, and make it level with the oxide layer. In an exemplary embodiment of the present invention, CMP is used to remove the copper to the level of the top of the silicon dioxide layer.

At Step23, oxide is etched, removing the oxide layer, while leaving the hard mask layer. In an embodiment of the present invention, the silicon dioxide is removed while the copper is preserved.

At Step24, the MTJ stack undergoes etching to remove MTJ areas not covered by the hard mask layer.

At Step25, a shielding layer is deposited atop the memory cell. In one embodiment of the present invention, silicon-nitride is used as the shielding layer. In yet another embodiment of the present invention, the silicon-nitride layer is 1500 Angstroms thick.

At Step26, a portion of the Silicon-Nitride layer is substantially reduced and flattened by a planarization process. In one exemplary embodiment of the present invention, CMP is used to remove a portion of and level the Silicon Nitride layer.

At Step27, a second oxide layer is deposited on top of the shielding layer. In one exemplary embodiment of the present invention, Step26is performed using a low temperature, silicon dioxide deposition.

At Step28, a second shielding layer is deposited, followed by the deposition of a third oxide layer. In an exemplary embodiment of the present invention, 100 Angstroms (A) to 1,000 A of nitride is used as a second shielding layer and silicon-dioxide is used as a third oxide layer. The silicon-dioxide layer is approximately 3000 A thick.

At Step29, a second photo-resist layer is applied to areas of the memory cell which are to be protected from the following etching process.

At Step30, a portion of the second photo-resist layer is removed to form two partial trenches.

At Step31, the third oxide layer is etched, using the two partial trenches and to access the third oxide layer, to form two trenches.

At Step32, the memory cell is exposed to remove the remaining second photo-resist layer99.

At Step33, a third photo-resist layer is deposited atop substantially the entire surface of the memory cell.

At Step34, a partial trench is formed down through the third photo-resist layer, stopping at the top of the second shielding layer.

At Step35, a trench is formed by etching the second shielding layer, second oxide layer, and shielding layer.

At Step36, the third photo-resist layer, is ashed to remove the remaining layer of the third photo-resist layer.

At Step37, a fourth photo-resist layer is deposited atop the second shielding layer and the third oxide layer, as well as the exposed portion of the conductive layer80.

At Step38, a partial trench is formed down through the fourth photo-resist layer, stopping at the second shielding layer.

At Step39, the second shielding layer and the second oxide layer are etched, using the partial trench to access the second shielding layer and the second oxide layer to form a trench.

At Step40, the fourth photo-resist layer is removed.

At Step41, a barrier metal layer is deposited and a second conductive layer is deposited by electrolysis. This layer is most commonly copper, and CMP is used to substantially level and remove the excess Cu. This process leaves Cu only in the trenches.

At Step42, a passivation nitride layer and a passivation oxide layer are deposited. Both depositions are applied in low temperature. The deposition temperature is below 300 C.

At Step43, a pad mask is applied.

At Step44, a passivation mask and a passivation etch are applied.

The MRAM manufacturing process100ofFIG. 1advantageously creates a small MTJ, on the scale of approximately 600 Angstroms wide, a heretofore unobtainable size. A MTJ of such a size benefits from having a lower programming current requirement, which can be supplied by the access transistor.

FIG. 2shows a cross sectional view of a single memory cell102after Step16(ofFIG. 1) is completed. The formation of memory cell102up to Step16is well known to those skilled in the art. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, and oxide layer82.

At Step16, oxide layer82is deposited atop tantalum layer84. Oxide layer82is deposited using a low temperature technique. The low temperature technique is used to deposit the oxide layer82since high temperature disturbs the magnetic layers. The oxide layer82is only used to generate a hard mask to form a copper hard mask for the purpose of the MTJ definition. A variety of material can be used for this purpose. This includes any material that can be deposited at low temperature and can be removed easily. In an alternative embodiment of the present invention, photoresist is used instead of oxide layer82. By using photoresist, the MRAM manufacturing process100ofFIG. 1can be shortened substantially. In those embodiments where a photoresist layer is used for the definition of the MTJ hard mask, steps16,22, and24can be eliminated.

InFIG. 2, the conductive layer80is shown to be Cu damascene fabricated as part of CMOS wafer86. MTJ stack88is formed to substantially cover the top of the conductive layer80and the exposed upper area of CMOS wafer86. Tantalum layer84is formed to substantially cover the top of the MTJ stack88. Finally, oxide layer82is formed to substantially cover the top of the tantalum layer84. In an exemplary embodiment of the present invention, silicon dioxide (SilOx or SiO2) is used to form oxide layer82, and oxide layer82is approximately 1500 Angstroms thick.

At Step17, photo-resist layer90is deposited atop substantially the entire surface of oxide layer82. The photo-resist layer90is then selectively exposed.

Accordingly, the photo-resist layer90is selectively exposed with the exposed area defined by the mask layer91. Exposure is done using known techniques, such as using the ASML 193 nm stepper machine, made by ASML of the Netherlands. This selective exposure defines which areas of the photo-resist layer90are removed. If positive photo resist is used the exposed area of the photo resist would develop away and is removed.

At Step18, a portion of the photo-resist layer90is removed to form partial trench89. Partial trench89, is formed by removing the portion of photo-resist layer90, and is formed substantially in the center of memory cell102. Further, partial trench89is formed such that the top of oxide layer82is exposed, and layer82forms the bottom of partial trench89.

At Step19, the oxide layer82is etched, using the partial trench89to access the oxide layer82, to form trench92. Trench92, is formed from the photo-resist layer90down through the oxide layer82and stops at the tantalum layer84. Trench92is located in substantially the center of memory cell102. The top of the tantalum layer84forms the bottom of trench92. In some embodiments, etching is performed using tetra-Fluoro-Carbon (CF4) with reactive ion etching (RIE). Etching the oxide layer82stops at tantalum layer84since Ta etches much slower than oxide in CF4. In exemplary embodiment of the present invention, the area of trench92is approximately 5525 nm2.

At Step20, the memory cell102is ashed in O2 plasma to remove the remaining photo-resist layer90. This is an exemplary of the present invention, other techniques other than plasma ashing can be used to remove the remaining photo-resist layer90.FIG. 3(d) shows memory cell102following the plasma ashing of the photoresist layer90. It should be noted that in a yet another embodiment the oxide layer82is removed and the photoresist layer90is formed directly on top of layer82.

FIG. 4shows a cross sectional view of a single memory cell102after Step21(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, oxide layer82, oxide mask layer93, and trench92.

At Step21, a hard mask layer is deposited. In an exemplary embodiment of the present invention, the hard mask layer is copper, and the Damascene Process is used for deposition. In this process, the underlying oxide layer82is patterned with open trenches where the hard mask layer93is deposited. A thick coating of the hard mask layer93, that significantly overfills the trench92is deposited on the oxide layer82. In one embodiment of the present invention, the hard mask layer is copper. Thereafter, a chemical-mechanical planarization or chemical-mechanical polishing (CMP) is used to remove the copper to the level of the top of the oxide layer (at Step22, and shown inFIG. 5). The hard mask layer93sunken within the trench92of the oxide layer is not removed and becomes the patterned conductor. The hard mask layer93is shown formed inside of the trench92and on top thereof and also on top of the oxide layer82.

In an exemplary embodiment of the present invention, trench92is approximately 650 Angstroms wide. This size is advantageously smaller than that of prior art. In prior art techniques, when resist pillar is used to etch the MTJ, the trench can not be very small, since an MTJ pillar with a very small base would topple over and would etch away during MTJ etch.

In another embodiment of the present invention, the hard mask layer93is made of tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum (TaNi) or any suitable metal of which contacts may be made. The MTJ may be alternatively embedded and made on any of the metal layers of the memory cell, such as but not limited to, M1, M2, . . . or embedded memory of system-on-chip (SOC).

FIG. 5shows a cross sectional view of memory cell102after Step22(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, oxide layer82, hard mask layer93, and trench92. After Step22, as a result of the chemical-mechanical polishing (CMP) process, the hard mask layer93is only present in trench92, and the hard mask layer93is substantially leveled such that it forms a substantially leveled single surface with oxide layer82.

At Step22, the hard mask layer93and oxide layer82are planarized. The planarization process is used to smooth the top surface of the hard mask layer93, and make it level with the oxide layer82. In one embodiment of the present invention, planarization is accomplished by the technique of CMP. CMP serves to substantially smooth the top surface of the hard mask layer93and oxide layer82. The planarization process used in Step22serves to level the hard mask layer such that the hard mask layer is no longer atop oxide layer82, and is only present in trench92.

FIG. 6shows a cross sectional view of memory cell102after Step23(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, uncovered Ta/MTJ stack layer94, and hard mask layer93. Blanket oxide etching is used to remove the oxide layer82to form an uncovered Ta/MTJ stack layer94thereby exposing the tantalum layer84where the layer oxide82resided. Uncovered Ta/MTJ stack layer94is shown to be the topmost layer of memory cell102, except where hard mask layer93sits atop layer94, in substantially the center of memory cell102.

At Step23, memory cell102undergoes a blanket oxide etching, removing the oxide layer82, while leaving the hard mask layer93. In one embodiment of the present invention, gas CF4 is used to remove the oxide82. CF4 does not substantially etch the Cu. Cu seed layer that is underneath of oxide can be etched with CH3OH or CO/NH3. The Ta on top of the MTJ has to be etched with CF4 again and CH3OH or CO/NH3 chemistry has to be used for the rest of the MTJ layers. Despite different gas requirements for etching these different layers, the layers can all be etched generally in one chamber or two etching chambers. After etching, hard mask layer93sits atop layer84in substantially the center of memory cell102. In an exemplary embodiment of the present invention, the hard mask layer93is made of copper, and is approximately 650 Angstroms wide and 1500 Angstroms tall.

FIG. 7shows a cross sectional view of memory cell102after Step24(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, and the hard mask layer93.

At Step24, the MTJ stack88undergoes etching to remove undesired areas of MTJ stack88, which are adjacent of hard mask layer93. At Step24, the uncovered Ta/MTJ stack layer94is removed by etching. More specifically, an etching process is performed on the structure ofFIG. 6to remove the layers84and88everywhere except that which is covered by the hard mask93. This process causes the shape of the hard mask93(inFIG. 7) to appear more as a dome-shaped structure on top due to erosion of sharp Cu edges during oxide etch, thereof than the more rectangular (or flat-top) structure ofFIG. 6. In an exemplary embodiment MTJ stack88is approximately 300 Angstroms tall and hard mask layer93is approximately 1000 Angstroms tall.

FIG. 8shows a cross sectional view of memory cell102after Step28(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, hard mask layer93, and shielding layer95.

At Step28, a shielding layer95is deposited atop memory cell102ofFIG. 7thereby covering the top of the conductive layer80, CMOS wafer86and hard mask93as well as the adjacent sides of the hard mask93and the adjacent sides of the MTJ stack88and tantalum layer84. Due to the dome-shaped structure of the layer93, the layer95is also dome-shaped following the shape of its under-layer (hard mask layer93). In an exemplary embodiment of the present invention, the shielding layer95is made of silicon-nitride (Si3N4). In another exemplary embodiment of the present invention, the shielding layer95is approximately 1500 Angstroms thick.

FIG. 9shows a cross sectional view of memory cell102after Step30(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, shielding layer95in which the shielding layer95is polished with CMP to render it flat. CMP is performed in such a way so as to cause removal of 1400 Angstrom (A) on top of the MTJ but only 500 A in the flat region of the shielding Nitride. This indicates that the thickness of the shielding silicon nitride on top of MTJ is approximately 100 A while in the flat areas, it is around 1000 A.

At Step32, second oxide layer96is deposited on top of the shielding layer95. The second oxide layer96is deposited atop memory cell102, substantially covering the shielding layer95after CMP. Since the shielding layer95, after CMP, is flat the second oxide layer96is also flat. In an exemplary embodiment of the present invention, Step32is performed using a low temperature, silicon-dioxide deposition. In another exemplary embodiment of the present invention, the second oxide layer96is approximately 3000 Angstroms thick. In some embodiments of the present invention, the second oxide layer is made of silicon-dioxide.

FIG. 10shows a cross sectional view of memory cell102after Step32(ofFIG. 1) is completed.FIG. 10-18show a more distant cross sectional view of memory cell102to further include the neighboring area of memory cell102. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, hard mask layer93, shielding layer95, and second oxide layer96.

At Step34, a second shielding layer97is deposited, followed by the deposition of a third oxide layer98. The second shielding layer97is deposited on top of the second oxide layer96(ofFIG. 10). Next, the third oxide layer98is formed (or deposited) on top of the layer97. In an exemplary embodiment of the present invention, the third oxide layer98is approximately 1750 Angstroms thick. In another exemplary embodiment of the present invention, the second shielding layer97is made of silicon-nitride (Si3N4). The second shielding layer97is an indicator that the first oxide is etched.

At step36, second photo-resist layer99is deposited atop substantially the entire surface of third oxide layer98. The second photo-resist layer99is then selectively exposed. That is, using one selective exposure technique.

Accordingly, the second photo-resist layer99is selectively exposed with the exposed area defined by the mask layer87. Exposure is done using known techniques, such as using ASML 193 exposure tool. This tool utilizes 193 nm ultra violet (UV) to expose the photo resist. This selective exposure defines which areas of the second photo-resist layer99are removed.

At Step37, a portion of the second photo-resist layer99is removed to form partial trench114and partial trench115. The partial trench114and partial trench115are formed down through the second photo-resist layer99. Partial trenches114and115, are formed by removing portions of the second photo-resist layer99, and are formed generally centered over the conductive layer80. Further, partial trenches114and115are formed such that the top of third oxide layer98is exposed, and layer98forms the bottom of partial trenches114and115.

At Step37, the third oxide layer98is etched, using the partial trenches114and115to access the third oxide layer98, to form oxide trenches101and103, as shown inFIG. 12. In some embodiments, etching is performed using tetra-fluoro-carbon (CF4) (or tetrafluoromethane) to form oxide trenches101and103, which are formed from the second photo-resist layer99down through the third oxide layer98, and stopping at the second shielding layer97. In some embodiments, RIE is used when performing the etching step. Etching of the third oxide layer98stops at the second shielding layer97due to the characteristics of the second shielding layer97. In an exemplary embodiment of the present invention, the second shielding layer97is made of silicon-nitride (Si3N4).

At Step37, the memory cell102is ashed to remove the remaining second photo-resist layer99. In one embodiment of the present invention plasma ashing is used to remove layer99. Ashing is the exposure of the photo resist to Oxygen plasma. During this plasma treatment, the ionic O burns the organic photo resist.

At Step38, third photo-resist layer105is deposited atop substantially the entire surface of memory cell102. Stated differently, the remainder of the third oxide layer98(ofFIG. 13) and the exposed portion of the second shielding layer97(ofFIG. 13) and the oxide trenches101and103(ofFIG. 13) are covered with third photo-resist layer105. The third photo-resist layer105is formed above the layers98and97and the top of the oxide trenches101and103to not only cover the tops thereof but to extend beyond the tops up to a suitable thickness there above. The third photo resist layer105is then exposed selectively to UV light by an exposing machine known in the semiconductor industry as stepper machines. Mask layer85, in some embodiments, is made of a very flat glass with via patterns formed on it with chromium (Cr). Generally, the via patterns on this mask is 4 to 5 times larger than the actual via's on the silicon wafer. The exposure machine creates the picture of this mask on the wafer, with correct dimensions and properly aligned with respect to the previous layers of the wafer.

Accordingly, the third photo-resist layer105is selectively exposed with the exposed area defined by the third photo-resist layer105. Exposure is done using known techniques, such as using ASM 193 stepper tool. This tool utilizes 193 nm UV to expose the photo-resist. This selective exposure defines which areas of the third photo-resist layer105are removed. Exposing the third photo-resist105at selective areas defined by the mask layer85forms the partial trench112(ofFIG. 14(a)).

At Step38, the partial trench112is formed down through the third photo-resist layer105, and stopping at the top of second shielding layer97. Partial trench112, is formed by removing portions of third photo-resist layer105, and is formed generally centered over the conductive layer80onto which the MTJ stack is not disposed. Further, partial trench112is formed such that the top of the second shielding layer97is exposed, and layer97forms the bottom of partial trench112.

At Step38, the trench is formed by etching the second shielding layer97, second oxide layer96, and shielding layer95only in an area defined by the width of via trench104, substantially in the middle of the conductive layer80but only affecting layer80in areas where no MTJ is formed, by etching from the top of the second shielding layer97down through to the shielding layer95, exposing the top of the layer80. The etching process of Step38stops at the top of the conductive layer80due to the characteristics of the material forming the layer80. In some embodiments, reactive ion etching (RIE) is used when performing the etching step

FIG. 15shows a cross sectional view of memory cell102after Step40(ofFIG. 1) is completed. Memory cell102is shown to include CMOS wafer86, conductive layer80, MTJ stack88, tantalum layer84, hard mask layer93, shielding layer95, second oxide layer96, second shielding layer97, third oxide layer98, and via trench104.

At Step40, the third photo-resist layer105, is exposed with MTJ-Via mask to remove the remaining layer105. In an exemplary embodiment of the present invention, plasma ashing is used to remove the remaining layer105. After removal of third photo-resist layer105, the top of memory cell102is shown to include layer98and layer97, except for via trench104which exposes conductive layer80.

At Step40, a fourth photo-resist layer107is deposited atop substantially the layers98,97(ofFIG. 15), as well as the exposed portion of the conductive layer80(ofFIG. 15). The fourth photo-resist layer107is then covered with a mask in areas that are to be selectively exposed. That is, using one selective exposure technique, a mask layer83is to expose the fourth photo-resist layer107in areas that are to be removed.

Accordingly, the fourth photo-resist layer107is selectively exposed with the exposed area defined by the mask layer83. Exposure is done using known techniques, such as using ASM 193 stepper tool. This tool utilizes 193 nm UV to expose the photo-resist. This selective exposure defines which areas of the fourth photo-resist layer107are removed. Exposing the fourth photo-resist layer107at selective areas defined by the mask layer83forms the partial trench113(ofFIG. 16(b)).

At Step40, the partial trench113is formed down through the fourth photo-resist layer107, and stopping at the top of second shielding layer97. Partial trench113, is formed by removing portions of the fourth photo-resist layer107, and is formed generally centered over the conductive layer80onto which the MTJ stack is disposed. Further, partial trench113is formed such that the top of the second shielding layer97is exposed, and layer97forms the bottom of partial trench113.

At Step40, the second shielding layer97and the second oxide layer96are etched, using the partial trench113(ofFIG. 16(b)) to access layers97and96, to form MTJ trench106. After etching, the trench106extends substantially downward such that the top “cap” of hard mask layer93is exposed, and the walls of trench106are comprised of second oxide layer96, second shielding layer97, and the fourth photo-resist layer107. In an exemplary embodiment of the present invention, MTJ trench106measures approximately 1000 Angstroms wide. In some embodiments, RIE is used when performing the etching step. Etching the second shielding layer97and the second oxide layer96stops at the hard mask layer93due to the characteristics of the hard mask layer93.

At Step40, the fourth photo-resist layer107is removed. The memory cell102is cleaned (or ashed) to remove the remaining fourth photo-resist layer107. In an exemplary embodiment of the present invention, plasma ashing is used to remove the remaining fourth photo-resist layer107.

At Step41, a barrier metal layer108is deposited on top of the wafer. The barrier metal layer108is necessary to prevent copper diffusion into the dielectric layer of CMOS wafer86. Next, a second conductive layer109is deposited by electrolysis. At Step41, a Dual Damascene process is used. In this process, both the MTJ trench111and via trench116are fabricated before the deposition of the second conductive layer109, thereby filling both the MTJ trench111and the partial trench112in a single step. Dual Damascene process is well known to those skilled in the art. Next, the CMP process is performed to substantially level the top of the third oxide layer98and the second conductive layer109. In an exemplary embodiment, the second conductive layer109is made of copper.

After Step44, a passivation nitride layer and a passivation oxide layer are deposited substantially atop memory cell102. Both depositions are applied in low temperature. The deposition temperature is below 300 C. This deposition temperature is lower than the normal deposition temperature of 470 C. Next, a pad mask is used to expose the photo-resist covering the memory cell102. Finally, a passivation etch is performed. The passivation process, and passivation etch steps listed above are well known to one skilled in the art.

In some embodiments, the memory cell102includes memory elements shown and discussed in U.S. patent application Ser. No. 11/674,124, entitled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory,” filed Feb. 12, 2007, by Ranjan, et al.; U.S. patent application Ser. No. 11/678,515, entitled “A High Capacity Low Cost Multi-State Magnetic Memory,” filed Feb. 23, 2007, by Ranjan, et al.; and U.S. patent application Ser. No. 11/776,692, entitled “Non-Volatile Magnetic Memory Element with Graded Layer,” filed Jul. 12, 2007, by Ranjan et al., all of which are incorporated herein by reference as though set forth in full.