Predicted parallel branch slicer and slicing method thereof

A predicted parallel branch slicer for use in an adaptive decision feedback equalizer includes Mk adders commonly receiving a signal to be processed and respectively receiving Mk preset values, and performing respective addition operations to generate Mk output signals; Mk slicers in communication with the Mk adders, receiving and processing the Mk output signals to obtain Mk signals of Mk levels, respectively; a multiplexer in communication with the Mk slicers, receiving the signals of the Mk levels; and k delay units interconnected with one another in series and being in communication with the multiplexer, and generating k selection signals of different delay time in response to an output of the multiplexer, the selection signals being provided for the multiplexer to select one of the signals of the Mk levels to be outputted.

FIELD OF THE INVENTION

The present invention relates to a predicted parallel branch slicer, and more particularly to a predicted parallel branch slicer for use in an adaptive decision feedback equalizer (DFE) for properly slicing signals. The present invention also relates to a slicing method of a predicted parallel branch slicer for use in an adaptive DFE.

BACKGROUND OF THE INVENTION

Recently, the Institute of Electric and Electronic Engineers stipulated a transmission standard of Gigabit Ethernet. In this transmission standard, four unshield twisted pair-category 5 (UTP-CAT5) transmission lines are used to transmit data at a rate of giga bits per second. For complying with such high speed transmission, the transceiver of each node has to overcome the noise problems resulting from, for example, inter-symbol interference (ISI), echo, near-end cross talk (NEXT) and far-end cross talk (FEXT) phenomena.

Please refer toFIG. 1Awhich is a functional block diagram schematically showing a transceiver of a node in a Gigabit Ethernet. In the signal receiving path, an analog signal is processed by the UTP-CAT5 transmission lines10, hybrid11, analog front end (AFE)12and analog-to-digital converter (ADC) into a digital data signal x(n) essentially suffered from the ISI phenomena (The FEXT phenomena can be ignored). The digital data signal x(n) is transmitted to the subsequent adaptive decision feedback equalizer (ADFE)16to be further processed in order to remove the ISI effect, and then transmitted to be processed by the downstream decoder17, packet and cell switch (PCS)18and medium access controller19. Finally, the processed digital data is transmitted to the network node itself, e.g. a personal computer. The PCS18also outputs some signals which pass through an adaptive echo canceller14and an adaptive NEXT canceller15and then enter the ADFE16.FIG. 1Bshows the waveform diagram of the channel impulse response of a digital data signal x(n). The left portion from the dash line is so called as precursor ISI, and the right portion from the dash line is so called as postcursor ISI.

Please refer toFIG. 2Awhich is a schematic functional block diagram of a conventional adaptive decision feedback equalizer. The conventional ADFE uses a feed forward equalizer (FFE)21and a feed back equalizer (FBE)22to eliminate the precursor ISI and postcursor ISI, respectively. The coefficients of the FEE21and FBE22are determined and refreshed by a first and a second coefficient refresher23and24according to the error signal e(n) and the previous values thereof. The slicer25quantizes the signal y(n) to recover the digital data signal d(n). The operational principle of the ADFE shown inFIG. 2Ais based on least-mean-square (LMS) algorithm, involving the following equations:

The data-processing rate of this ADFE is confined by the bandwidth of the decision feedback loop (DLP), and thus is limited within a certain level. In order to solve this problem, a pipeline method is developed, which is referred toFIG. 2B.FIG. 2Bshows another conventional adaptive decision feedback equalizer. The detailed description of the pipeline method is referred to Naresh R. Shanbhag, Keshab K. Parhi, “Pipelined adaptive DFE architectures using relaxed look-ahead,”IEEE Trans. Signal Processing,vol. 43, No. 6, pp. 1368-1385, June 1995, which is incorporated herein for reference. Different from the ADFE ofFIG. 2A, k delay units are additionally provided for the decision feedback loop (DLP). It is to be noted that the additional k delay units are shown outside the FBE22inFIG. 2Bfor simplifying the drawing. In practice, however, the additional k delay units are generally arranged inside the FBE22. Accordingly, the FBE22is divided into (k+1) groups of sub-circuits with a delay unit in each sub-circuit. The pipeline operation is performed with the (k+1) groups of sub-circuits, so as to improve the overall processing speed.

This pipeline method, although has relatively high processing rate, suffers from a low signal-to-noise ratio. Due to the increased delay time, the waveform response of the FBE22will become the one illustrated inFIG. 2C. Since the presence of the additional k delay units, the postcursor ISI relating to the delay time of preceding k delay units is limited to zero, as indicated by the arrow inFIG. 2C. Accordingly, the FBE cannot perform well, and so as to reduce the overall signal-to-noise ratio of the system and deteriorate the signal quality. Modification on the FFE21may alleviate the problem, but make the circuitry of the FFE21even more complicated. Moreover, the signal quality has not been significantly improved.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide an adaptive decision feedback equalizer, which has a high signal-to-noise ratio and a processing speed complying with the requirement of Gigabit Ethernet.

According to a first aspect of the present invention, a predicted parallel branch slicer for use in an adaptive decision feedback equalizer comprises adders of a number of an expression Mk, where M is a base greater than one and k is an exponent, commonly receiving a signal to be processed and respectively receiving Mkpreset values, and performing respective addition operations to generate Mkoutput signals; slicers of a number of the expression Mk, in communication with the Mkadders, receiving and processing the Mkoutput signals to obtain Mksignals of Mklevels, respectively; a multiplexer in communication with the Mkslicers, receiving the signals of the Mklevels; and delay units of a number k, interconnected with one another in series and being in communication with the multiplexer, and generating k selection signals of different delay time in response to an output of the multiplexer, the selection signals being provided for the multiplexer to select one of the signals of the Mklevels to be outputted.

Preferably, the Mkadders are Mkadders with constant coefficients.

Preferably, the signals of the Mklevels at least include a plurality of data signals of the Mklevels and a plurality of error signals of the Mklevels.

Preferably, the multiplexer is a combination of a first multiplexer and a second multiplexer, which are in communication with the Mkslicers and the k serially interconnected delay units. The first multiplexer receives the data signals of the Mklevels and the selection signals from the delay units, the second multiplexer receives the error signals of the Mklevels and the selections signal from the delay units, and the second multiplexer generates the at least one output according to an output of the first multiplexer.

In accordance with the present invention, the one of the signals of the Mklevels selected to be outputted by the multiplexer is the one including a data signal closest to the selection signals, which means the difference between the selected one and the corresponding selection signal is smallest.

In an embodiment, the one of the signals of the Mklevels selected to be outputted by the multiplexer is the one having an error signal closest to the selection signals, which means they are closet to each other than anyone of other signals of the Mklevels and anyone of other selection signals.

In another embodiment, the one of the signals of the Mklevels selected to be outputted by the multiplexer is the one which is closest to the selection signals, which means the differences between any other signals of the Mklevels and the selection signals is larger than the difference between the one and the selection signals.

Preferably, a value VeTT received by each of the Mkadders at a sampled point n is equal to the product of an optimal coefficient Ve=[C1, C2, . . . , Ck] and a value T of k preceding levels, where T=[a(n−1), a(n−2), . . . , a(n−k)]. More preferably, C1, C2, . . . , Ck are k constant coefficients realized according to a simulated waveform of a channel impulse response on a transmission line of Gigabit Ethernet stipulated by IEEE.

A second aspect of the present invention relates to a predicted parallel branch slicing method for use in an adaptive decision feedback equalizer. The method comprises steps of realizing the first k coefficients of a feed back equalizer according to a channel feature, and operating to obtain Mkpreset values, where M is a base greater than one and k is an exponent; receiving a signal to be processed and the Mkpreset values which are operated to obtain Mkoutput signals; respectively receiving and slicing the Mkoutput signals to obtain Mksignals of Mklevels; generating a sliced output signal according to the Mksignals of Mklevels; and generating a plurality of selection signals of k kinds of different delay time according to the sliced output signal and k different delay operations, and selecting one of the Mksignals of Mklevels to be outputted.

Compared to the prior art, the present invention performs a pipeline operation of the feed back equalizer by providing additional delay units so as to improve the processing speed. Further, a specially designed predicted parallel branch slicer is used to keep the signal-to-noise ratio at a satisfactory level so as to present from the possible deterioration of signal quality due to pipeline operation. Moreover, the complexity of the circuitry is acceptable (essentially only some slicer and multiplexers are additionally used).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Please refer toFIG. 3. The adaptive decision feedback equalizer according to a preferred embodiment of the present invention uses a predicted parallel branch slicer (PPBS)30to substitute for the simple slicers of the prior art in order to eliminate the effect of the additional k delay units on the signal-to-analog ratio of the system. In order to clarify the technique and principle of the present invention, please refer toFIGS. 4A˜4Dfirst, which are waveform diagrams showing the channel impulse responses obtained by using different lengths of unshield twisted pair-category 5 (UTP-CAT5) transmission lines according to the Gigabits Ethernet stipulated by IEEE. The lengths of the transmission lines shown inFIGS. 4A˜4Dare 25, 50, 75 and 100 meters, respectively. ForFIGS. 4A˜4D, the unit of the horizontal axis is time (such as second) and the unit of the vertical axis is voltage (such as volt). It is observed from the figures that the waveforms vary with the lengths of the transmission lines, but the variations are not significant. Therefore, k non-zero constants are preset according to observed waveforms, which are used for simulating the first k coefficients of the response waveform of the combined channel and feed forward equalizer (FFE)31. It is understood that the response waveform of the combined channel and FFE31is equivalent to the waveform entering the downstream feed back equalizer (FBE)32. By keeping the first k coefficients of the waveform unchanged, the other coefficients of the downstream FBE can be obtained according to the lease mean square (LMS) algorithm. Accordingly, the first k terms of the postcursor ISI can be eliminated by the first k constant coefficients of the FBE (referring to the PPBS30described later), and the rest postcursor ISI can be eliminated by the adaptive coefficients of the latter coefficients of the FBE (referring to the FBE32described later). For example, when k is equal to 2 and the constant coefficients are C1 and C2, the waveform entering the FBE will be similar to that shown inFIG. 5. The first k coefficients will be very close to the optimal values. Reminded that the first k coefficients of the FBE22ofFIG. 2Bare fixed at zero, which is far way from the practice, the signal-to-noise ratio is thus adversely reduced. By the present invention, this problem can be solved. Next, the equalizer with the first k constant coefficients is transformed into the predicted parallel branch slicer30to introduce pipeline process into the FBE.

Please refer toFIG. 6A, which is a schematic functional block diagram showing the predicted parallel branch slicer30in a preferred embodiment, wherein the number k of delay units is equal to 2, and the signal x(n) is a pulse amplitude modulation (PAM) signal with five levels, i.e. −2, −1, 0, 1 and 2. The predicted parallel branch slicer30includes twenty-five, i.e. 52, adders60and twenty-five slicers61of a parallel branch structure. The value VeTT received by the input end of each adder60is equal to the product of an optimal coefficient Ve=[C1, C2] and a value T of two preceding levels, where T=[a(n−1), a(n−2)]. In a 5-level case, the value T has 25 possible combinations. Two delay units62and63are additionally provided in the decision feedback loop (DLP) for use. It is apparent from the figure, the signal b(n) obtained by adding the output of the feed forward equalizer (FFE)31with the output of the feed back equalizer (FBE)32are further processed by addition and quantization operations with the 25 possible combinations so as to obtain 25 possible quantized data signals d and corresponding error signals e. The signals d and e are inputted to two 25-to-1 multiplexers64and65, respectively, to be selected. The multiplexers64and65make selections based on the outputs x(n−1) and x(n−2) of the delay units62and63. That is, that x(n−1) and x(n−2) are substantially which of the 25 possible combinations is determined to realize the selections of the multiplexers64and65. Ideally, x(n−1) or x(n−2) will be exactly the same as one of the 25 possible combinations. Futther explanation, please refer to the paper of the inventors: IEEE workshop on Signal Processing Systems (SIPS'02). Sam Diego, Calif., USA, Oct. 16-18, 2002. In practice, however, x(n−1) or x(n−2) will be very close to rather than exactly identical to one of the 25 possible combinations due to certain noises and/or errors. Under this circumstance, one of the 25 possible combinations, which is closest to x(n−1) or x(n−2) in level, is determined, and that combination is selected to be outputted by the multiplexers64and65. Herein, the term “closest to” could be viewed as the determined combination with a smallest difference among other combinations. In other words, the term “closest to” could be viewed as the following: the difference between the elements of the selected combination is smaller than the difference between the elements of any other combinations. The delay units62and63can be arranged in the FBE32so that the FBE32is divided into three groups of sub-circuits to perform pipeline operations, thereby speeding up the processing.

Please refer toFIG. 6B. In this embodiment of predicted parallel branch slicer30, k is equal to 3, and the signal x(n) is a pulse amplitude modulation (PAM) signal with two levels, i.e. −1 and 1. The predicted parallel branch slicer30includes eight, i.e. 23, adders70and eight slicers71of a parallel branch structure. The value VeTT received by the input end of each adder70is equal to the product of an optimal coefficient Ve=[C1, C2, C3] and a value T of three preceding levels, where T=[a(n−1), a(n−2), a(n−3)]. In a 2-level case, the value T has 8 possible combinations. Three delay units72,73and74are additionally provided in the decision feedback loop (DLP) for use. It is apparent from the figure, the signal b(n) outputted from the feed forward equalizer (FFE)31are processed by addition and quantization operations with the 8 possible combinations so as to obtain 8 possible quantized data signals d and corresponding error signals e. The signals d and e are inputted to two 8-to-1 multiplexers75and76, respectively, to be selected. The multiplexers64and65make selections based on the outputs x(n−1), x(n−2) and x(n−3) of the delay units72,73and74. That is, that x(n−1), x(n−2) and x(n−3) are which of the 8 possible combinations is determined to realize the selections of the multiplexers75and76. The delay units72,73and74can be arranged in the FBE32so that the FBE32is divided into four groups of sub-circuits to perform pipeline operations, thereby speeding up the processing.