Method, apparatus and article of manufacture for a transform module in a graphics processor

A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data. Memory is coupled to the multiplication logic unit and the arithmetic logic unit. The memory has stored therein a plurality of constants and variables for being used in conjunction with the input buffer, the multiplication logic unit, the arithmetic logic unit, the register unit, the inverse logic unit, and the conversion module for processing the vertex data. Finally, an output converter is coupled to the output of the arithmetic logic unit for being coupled to a lighting module to output the processed vertex data thereto.

FIELD OF THE INVENTION

The present invention relates generally to graphics processors and, more particularly, to a transform module of a graphics pipeline system.

BACKGROUND OF THE INVENTION

Prior ArtFIG. 1illustrates a general prior art system that implements a pipelined graphics processing system. In this system, data source10generates a stream of expanded vertices defining primitives. These vertices are passed, one at a time, through pipelined graphic system12via vertex memory13for storage purposes. Once the expanded vertices are received from the vertex memory13into the pipelined graphic system12, the vertices are transformed and lit by a transformation module14and a lighting module16, respectively, and further clipped and set-up for being rendered by a rasterizer18, thus generating rendered primitives that are then displayed on display device20.

During operation, the transform module14may be used for receiving vertices in model coordinates and transforming the three dimensional vertices from their model coordinates to the two dimensional window where they will ultimately be displayed. In order to achieve the transformation, standard transform parameters may be employed such as a view port, a viewing matrix, a world matrix, a projection matrix and so forth.

Together, the foregoing parameters allow geometric transformations to express the location of an object relative to another object, rotate, clip and size various objects, as well as change viewing positions, directions, and perspectives in the three dimensional scene. Coordinate transformations that transform the three dimensional vertices from their model coordinates to the two dimensional window where they will be displayed typically involve one or more of translation, rotation and scaling.

Prior art transform systems typically handle scalar and vector values that are generated during the transform process separately. For example, a position attribute, i.e. (X, Y, Z, W), may be processed via a vector operator such as multiplier, and/or an adder, thus rendering a scalar value. While a scalar operator may process such scalar value, it is typically not processed again by the vector operator. Until now there have been no attempts to integrate the processing of scalar and vector forms of processed vertex data during graphics pipeline processing.

Yet another process handled by the transform module14is blending, or “skinning.” Skinning refers to the process of adding realism to segmented polygonal objects by blending ajoint between the objects. Prior ArtFIG. 1Aillustrates a pair of objects22before and after skinning is performed.

Conventionally, the skinning process is carried out using a computer program and a general-purpose processor. As such, there have been no attempts to implement skinning on hardware for the purpose of incurring the benefits, i.e. speed, efficiency, etc., associated with dedicated circuitry.

DISCLOSURE OF THE INVENTION

A method, apparatus and article of manufacture are provided for a transform system for graphics processing. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit.

An inverse logic unit is also provided including an input coupled to the output of the arithmetic logic unit for performing an inverse or an inverse square root operation. In one embodiment, a method is provided for handling null W-attribute values in the inverse logic unit of the transform module. Handling null W-attribute values is of particular importance since a set-up module of a rasterizer is incapable of generating edge equations in screen space if the W-attribute is null because a divide by zero produces an useless infinity value. In use, upon receipt of the vertex data, the inverse logic unit of the transform module identifies a value of an W-attribute of the vertex data. If the identified value of the W-attribute is null, a divide operation involving the W-attribute of the vertex data is clamped to a minimum and a maximum exponent. It is this clamped value that the set-up module of the rasterizer uses to generate the edge equations.

Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data.

Memory is coupled to the multiplication logic unit and the arithmetic logic unit. The memory has stored therein a plurality of constants and variables for being used in conjunction with the input buffer, the multiplication logic unit, the arithmetic logic unit, the register unit, the inverse logic unit and the conversion module for processing the vertex data. Finally, an output converter is coupled to the output of the arithmetic logic unit for being coupled to a lighting module to output the processed vertex data thereto.

In one aspect of the present invention, the transform system may be adapted for handling both scalar and vector components during graphics processing. To accomplish this, vertex data is received in the form of vectors after which vector operations are performed on the vector vertex data. The arithmetic and multiplication logic unit or any other type of vector operation modules may implement such vector operations.

Next, scalar operations may be executed on an output of the vector operations, thereby rendering vertex data in the form of scalars. The inverse logic unit or any other type of scalar operation module may execute the scalar operations. Such scalar vertex data may then be converted to vector vertex data for performing vector operations thereon. The register for performing vector operations thereon also stores an output of the vector operations. As an option, the register may be equipped with a masking function to generate vector vertex data based on the output of the vector operations.

In yet another aspect of the present invention, a technique may be employed for providing a hardware implementation of a blending, or “skinning,” operation during graphics processing in a graphics pipeline. During processing in the pipeline, a plurality of matrices and a plurality of weight values each corresponding with one of the matrices are received. Also received is vertex data to be processed.

A sum of a plurality of products may then be calculated by the multiplication of the vertex data, one of the matrices, and the weight corresponding to the matrix. Such sum of products is then outputted for additional processing.

In one embodiment, the matrices may include model view matrices, and the additional processing may include a lighting operation. In this embodiment, a composite matrix for display purposes may also multiply the sum of products. Still yet, the matrices may include inverse matrices and the vertex data may include a normal vector. In such case, the additional processing may also include a lighting operation.

These and other advantages of the present invention will become apparent upon reading the following detailed description and studying the various figures of the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 and 1Ashow the prior art.FIGS. 1B–32Cshow a graphics pipeline system of the present invention.

FIG. 1Bis a flow diagram illustrating the various components of one embodiment of the present invention. As shown, the present invention is divided into four main modules including a vertex attribute buffer (VAB)50, a transform module52, a lighting module54, and a rasterization module56with a set-up module57. In one embodiment, each of the foregoing modules is situated on a single semiconductor platform in a manner that will be described hereinafter in greater detail. In the present description, the single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip.

The VAB50is included for gathering and maintaining a plurality of vertex attribute states such as position, normal, colors, texture coordinates, etc. Completed vertices are processed by the transform module52and then sent to the lighting module54. The transform module52generates vectors for the lighting module54to light. The output of the lighting module54is screen space data suitable for the set-up module which, in turn, sets up primitives. Thereafter, rasterization module56carries out rasterization of the primitives. It should be noted that the transform and lighting modules52and54might only stall on the command level such that a command is always finished once started.

In one embodiment, the present invention includes a hardware implementation that at least partially employs Open Graphics Library (OpenGL®) and D3D™ transform and lighting pipelines. OpenGL® is the computer industry's standard application program interface (API) for defining 2-D and 3-D graphic images. With OpenGL®, an application can create the same effects in any operating system using any OpenGL®-adhering graphics adapter. OpenGL® specifies a set of commands or immediately executed functions. Each command directs a drawing action or causes special effects.

FIG. 2is a schematic diagram of VAB50in accordance with one embodiment of the present invention. As shown, VAB50passes command bits200while storing data bits204representative of attributes of a vertex and mode bits202. In use VAB50receives the data bits204of vertices and drains the same.

The VAB50is adapted for receiving and storing a plurality of possible vertex attribute states via the data bits204. In use after such data bits204, or vertex data, is received and stored in VAB50, the vertex data is outputted from VAB50to a graphics-processing module, namely the transform module52. Further, the command bits200are passed by VAB50for determining a manner in which the vertex data is inputted to VAB50in addition to other processing which will be described in greater detail with reference toFIG. 2A. Such command bits200are received from a command bit source such as a microcontroller, CPU, data source or any other type of source which is capable of generating command bits200.

Further, mode bits202are passed which are indicative of the status of a plurality of modes of process operations. As such, mode bits202are adapted for determining a manner in which the vertex data is processed in the subsequent graphics-processing modules. Such mode bits202are received from a command bit source such as a microcontroller, CPU, data source or any other type of source which is capable of generating mode bits202.

It should be noted that the various functions associated with VAB50may be governed by way of dedicated hardware, software or any other type of logic. In various embodiments, 64, 128, 256 or any other number of mode bits202may be employed.

The VAB50also functions as a gathering point for the 64 bit data that needs to be converted into a 128-bit format. The VAB50input is 64 bits/cycle and the output is 128 bits/cycle. In other embodiments, VAB50may function as a gathering point for 128-bit data, and VAB50input may be 128 bits/cycle or any other combination. The VAB50further has reserved slots for a plurality of vertex attributes that are all IEEE 32 bit floats. The number of such slots may vary per the desires of the user. Table 1 illustrates exemplary vertex attributes employed by the present invention.

During operation, VAB50may operate assuming that the x, y data pair is written before the z,w data pair since this allows for defaulting the z,w pair to (0.0,1.0) at the time of the x,y write. This may be important for default components in OpenGL® and D3D™. It should be noted that the position, texture0, and texture1 slots default the third and fourth components to (0.0,1.0). Further, the diffuse color slot defaults the fourth component to (1.0) and the texture slots default the second component to (0.0).

The VAB50includes still another slot205used for assembling the data bits204that may be passed into or through the transform and lighting module52and54, respectively, without disturbing the data bits204. The data bits204in the slot205can be in a floating point or integer format. As mentioned earlier, the data bits204of each vertex has an associated set of mode bits202representative of the modes affecting the processing of the data bits204. These mode bits202are passed with the data bits204through the transform and lighting modules52and54, respectively, for purposes that will be set forth hereinafter in greater detail.

In one embodiment, there may be 18 valid VAB, transform, and lighting commands received by VAB50.FIG. 2Ais a chart illustrating the various commands that may be received by VAB50in accordance with one embodiment of the present invention. It should be understood that all load and read context commands, and the passthrough command shown in the chart ofFIG. 2Atransfer one data word of up to 128 bits or any other size.

Each command ofFIG. 2Amay contain control information dictating whether each set of data bits204is to be written into a high double word or low double word of one VAB address. In addition, a 2-bit write mask may be employed for providing control to the word level. Further, there may be a launch bit that informs VAB controller that all of the data bits204are present for a current command to be executed.

Each command has an associated stall field that allows a look-up to find information on whether the command is a read command in that it reads context memory or is a write command in that it writes context memory. By using the stall field of currently executing commands, the new command may be either held off in case of conflict or allowed to proceed.

In operation, VAB50can accept one input data word up to 128 bits (or any other size) per cycle and output one data word up to 128 bits (or any other size) per cycle. For the load commands, this means that it may take two cycles to load the data into VAB50to create a 128-bit quad-word and one cycle to drain it. For the scalar memories in the lighting module54, it is not necessary to accumulate a full quad-word, and these can be loaded in one cycle/address. For one vertex, it can take up to 14 cycles to load the 7 VAB slots while it only takes 7 cycles to drain them. It should be noted, however, that it is only necessary to update the vertex state that changes between executing vertex commands. This means that, in one case, the vertex position may be updated taking 2 cycles, while the draining of the vertex data takes 7 cycles. It should be noted that only 1 cycle may be required in the case of the x,y position.

FIG. 2Bis a flow chart illustrating one method of loading and draining vertex attributes to and from VAB50during graphics-processing. Initially, in operation210, at least one set of vertex attributes is received in VAB50for being processed. As mentioned earlier, each set of vertex attributes may be unique, and correspond to a single vertex.

In use the vertex attributes are stored in VAB50upon the receipt thereof in operation212. Further, each set of stored vertex attributes is transferred to a corresponding one of a plurality of input buffers of the transform module52. The received set of vertex attributes is also monitored in order to determine whether a received vertex attribute has a corresponding vertex attribute of a different set currently stored in VAB50, as indicated in operation216.

Upon it being determined that a stored vertex attribute corresponds to the received vertex attribute in decision217, the stored vertex attribute is outputted to the corresponding input buffer of the transform module52out of order. See operation218. Immediately upon the stored vertex attribute being outputted, the corresponding incoming vertex attribute may take its place in VAB50. If no correspondence is found, however, each set of the stored vertex attributes may be transferred to the corresponding input buffer of the transform module52in accordance with a regular predetermined sequence. Note operation219.

It should be noted that the stored vertex attribute might not be transferred in the aforementioned manner if it has an associated launch command. Further, in order for the foregoing method to work properly, the bandwidth of an output of VAB50must be at least the bandwidth of an input of VAB50.

FIG. 2Cis a schematic diagram illustrating the architecture of the present invention employed to implement the operations ofFIG. 2B. As shown, VAB50has a write data terminal WD, a read data terminal RD, a write address terminal WA, and a read address RA terminal. The read data terminal is coupled to a first clock-controlled buffer230for outputting the data bits204from VAB50.

Also included is a first multiplexer232having an output coupled to the read address terminal of VAB50and a second clock-controlled buffer234. A first input of the first multiplexer232is coupled to the write address terminal of VAB50while a second input of the first multiplexer232is coupled to an output of a second multiplexer236. A logic module238is coupled between the first and second multiplexers232and236, the write address terminal of VAB50, and an output of the second clock-controlled buffer234.

In use the logic module238serves to determine whether an incoming vertex attribute is pending to drain in VAB50. In one embodiment, this determination may be facilitated by monitoring a bit register that indicates whether a vertex attribute is pending or not. If it is determined that the incoming vertex attribute does have a match currently in VAB50, the logic module238controls the first multiplexer232in order to drain the matching vertex attribute so that the incoming vertex attribute may be immediately stored in its place. On the other hand, if it is determined that the incoming vertex attribute does not have a match currently in VAB50, the logic module238controls the first multiplexer232such that VAB50is drained and the incoming vertex attribute is loaded sequentially or in some other predetermined order, per the input of the second multiplexer236which may be updated by the logic module238.

As a result, there is no requirement for VAB50to drain multiple vertex attributes before a new incoming vertex attribute may be loaded. The pending vertex attribute forces out the corresponding VAB counterpart if possible, thus allowing it to proceed. As a result, VAB50can drain in an arbitrary order. Without this capability, it would take 7 cycles to drain VAB50and possibly 14 more cycles to load it. By overlapping the loading and draining, higher performance is achieved. It should be noted that this is only possible if an input buffer is empty and VAB50can drain into input buffers of the transform module52.

FIG. 3illustrates the mode bits associated with VAB50in accordance with one embodiment of the present invention. The transform/light mode information is stored in a register via mode bits202. Mode bits202are used to drive the sequencers of the transform module52and lighting module54in a manner that will be become apparent hereinafter. Each vertex has associated mode bits202that may be unique, and can therefore execute a specifically tailored program sequence. While, mode bits202may generally map directly to the graphics API, some of them may be derived.

In one embodiment, the active light bits (LIS) ofFIG. 3may be contiguous. Further, the pass-through bit (VPAS) is unique in that when it is turned on, the vertex data is passed through with scale and bias, and no transforms or lighting is done. Possible mode bits202used when VPAS is true are the texture divide bits (TDV0,1), and foggen bits (used to extract fog value in D3DT™). VPAS is thus used for pre-transformed data, and TDV0,1are used to deal with a cylindrical wrap mode in the context of D3D™.

FIG. 4illustrates the transform module of one embodiment of the present invention. As shown, the transform module52is connected to VAB50by way of 6 input buffers400. In one embodiment, each input buffer400might be 7*128b in size. The 6 input buffers400each is capable of storing 7 quad words. Such input buffers400follow the same layout as VAB50, except that the pass data is overlapped with the position data.

In one embodiment, a bit might be designated for each attribute of each input buffer400to indicate whether data has changed since the previous instance that the input buffer400was loaded. By this design, each input buffer400might be loaded only with changed data.

The transform module52is further connected to 6 output vertex buffers402in the lighting module54. The output buffers include a first buffer404, a second buffer406, and a third buffer408. As will become apparent hereinafter, the contents, i.e. position, texture coordinate data, etc., of the third buffer408are not used in the lighting module54. The first buffer404and second buffer406are both, however, used for inputting lighting and color data to the lighting module54. Two buffers are employed since the lighting module is adapted to handle two read inputs. It should be noted that the data might be arranged so as to avoid any problems with read conflicts, etc.

Further coupled to the transform module52is context memory410and micro-code ROM memory412. The transform module52serves to convert object space vertex data into screen space, and to generate any vectors required by the lighting module54. The transform module52also does processes skinning and texture coordinates. In one embodiment, the transform module52might be a 128-bit design processing 4 floats in parallel, and might be optimized for doing 4 term dot products.

FIG. 4Ais a flow chart illustrating a method of executing multiple threads in the transform module52in accordance with one embodiment of the present invention. In operation, the transform module52is capable of processing 3 vertices in parallel via interleaving. To this end, 3 commands can be simultaneously executed in parallel unless there are stall conditions between the commands such as writing and subsequently reading from the context memory410. The 3 execution threads are independent of each other and can be any command since all vertices contain unique corresponding mode bits202.

As shown inFIG. 4A, the method of executing multiple threads includes determining a current thread to be executed in operation420. This determination might be made by identifying a number of cycles that a graphics-processing module requires for completion of an operation, and tracking the cycles. By tracking the cycles, each thread can be assigned to a cycle, thus allowing determination of the current thread based on the current cycle. It should be noted, however, that such determination might be made in any desired manner that is deemed effective.

Next, in operation422, an instruction associated with a thread to be executed during a current cycle is retrieved using a corresponding program counter number. Thereafter, the instruction is executed on the graphics-processing module in operation424.

In one example of use, the instant method includes first accessing a first instruction, or code segment, per a first program counter. As mentioned earlier, such program counter is associated with a first execution thread. Next, the first code segment is executed in the graphics-processing module. As will soon become apparent, such graphics-processing module might take the form of an adder, a multiplier, or any other functional unit or combination thereof.

Since the graphics-processing module requires more than one clock cycle to complete the execution, a second code segment might be accessed per a second program counter immediately one clock cycle after the execution of the first code segment. The second program counter is associated with a second execution thread, wherein each of the execution threads process a unique vertex.

To this end, the second code segment might begin execution in the graphics-processing module prior to the completion of the execution of the first code segment in the graphics-processing module. In use the graphics-processing module requires a predetermined number of cycles for every thread to generate an output. Thus, the various steps of the present example might be repeated for every predetermined number of cycles.

This technique offers numerous advantages over the prior art. Of course, the functional units of the present invention are used more efficiently. Further, the governing code might be written more efficiently when the multiple threading scheme is assumed to be used.

For example, in the case where the graphics-processing module includes a multiplier that requires three clock cycles to output an answer, it would be necessary to include two no operation commands between subsequent operations such as a=b*c and d=e*a, since “a” would not be available until after the three clock cycles. In the present embodiment, however, the code might simply call d=e*a immediately subsequent a=b*c, because it can be assumed that such code will be executed as one of three execution threads that are called once every three clock cycles.

FIG. 4Bis a flow diagram illustrating a manner in which the method ofFIG. 4Ais carried out. As shown, each execution thread has an associated program counter450that is used to access instructions, or code segments, in instruction memory452. Such instructions might then be used to operate a graphics-processing module such as an adder456, a multiplier454, and/or an inverse logic unit or register459.

In order to accommodate a situation where at least two of the foregoing processing modules are used in tandem, at least one code segment delay457is employed between the graphics-processing modules. In the case where a three-thread framework is employed, a three-clock cycle code segment delay457is used. In one embodiment, the code segment delay457is used when a multiplication instruction is followed by an addition instruction. In such case, the addition instruction is not executed until three clock cycles after the execution of the multiplication instruction in order to ensure that time has elapsed which is sufficient for the multiplier456to generate an output.

After the execution of each instruction, the program counter450of the current execution thread is updated and the program counter of the next execution thread is called by module458in a round robin sequence to access an associated instruction. It should be noted that the program counters might be used in any fashion including, but not limited to incrementing, jumping, calling and returning, performing a table jump, and/or dispatching. Dispatching refers to determining a starting point of code segment execution based on a received parameter. Further, it important to understand that the principles associated with the present multiple thread execution framework might also be applied to the lighting module54of the graphics-processing pipeline of the present invention.

In the case where a three-thread framework is employed, each thread is allocated one input buffer and one output buffer at any one time. This allows loading of three more commands with data while processing three commands. The input buffers and output buffers are assigned in a round robin sequence in a manner that will be discussed later with reference toFIGS. 27 and 28.

The execution threads are thus temporally and functionally interleaved. This means that each function unit is pipelined into three stages and each thread occupies one stage at any one time. In one embodiment, the three-threads might be set to always execute in the same sequence, i.e. zero then one then three. Conceptually, the threads enter a function unit at t=clock modulo three. Once a function unit starts work, it takes three cycles to deliver the result (except the ILU that takes six), at which time the same thread is again active.

FIG. 5illustrates the functional units of the transform module52ofFIG. 4in accordance with one embodiment of the present invention. As shown, included are input buffers400that are adapted for being coupled to VAB50for receiving vertex data therefrom.

A memory logic unit (MLU)500has a first input coupled to an output of input buffers400. As an option, the output of MLU500might have a feedback loop502coupled to the first input thereof.

Also provided is an arithmetic logic unit (ALU)504having a first input coupled to an output of MLU500. The output of ALU504further has a feedback loop506connected to the second input thereof. Such feedback loop502may further have a delay508coupled thereto. Coupled to an output of ALU504is an input of a register unit510. It should be noted that the output of register unit510is coupled to the first and second inputs of MLU500.

An inverse logic unit (ILU)512is provided including an input coupled to the output of ALU504for performing an inverse or an inverse square root operation. In an alternate embodiment, ILU512might include an input coupled to the output of register unit510.

Further included is a conversion, or smearing, module514coupled between an output of ILU512and a second input of MLU500. In use the conversion module514serves to convert scalar vertex data to vector vertex data. This is accomplished by multiplying the scalar data by a vector so that the vector operators such as the multiplier and/or adder may process it. For example, a scalar A, after conversion, may become a vector (A,A,A,A). In an alternate embodiment, the smearing module514might be incorporated into the multiplexers associated with MLU500, or any other component of the present invention. As an option, a register516might be coupled between the output of ILU512and an input of the conversion unit514. Further, such register516might be threaded.

Memory410is coupled to the second input of MLU500and the output of ALU504. In particular, memory410has a read terminal coupled to the second input of MLU500. Further, memory410has a write terminal coupled to the output of ALU504.

The memory410has stored therein a plurality of constants and variables for being used in conjunction with the input buffer400, MLU500, ALU504, register unit510, ILU512, and the conversion module514for processing the vertex data. Such processing might include transforming object space vertex data into screen space vertex data, generating vectors, etc.

Finally, an output converter518is coupled to the output of ALU504. The output converter518serves for being coupled to a lighting module54via output buffers402to output the processed vertex data thereto. All data paths except for the ILU might be designed to be 128 bits wide or other data path widths may be used.

FIG. 6is a schematic diagram of MLU500of the transform module52ofFIG. 5in accordance with one embodiment of the present invention. As shown, MLU500of the transform module52includes four multipliers600that are coupled in parallel.

MLU500of transform module52is capable of multiplying two four component vectors in three different ways, or pass one four component vector. MLU500is capable of performing multiple operations. Table 2 illustrates such operations associated with MLU500of transform module52.

Possible A and B inputs are shown in Table 3.

Table 4 illustrates a vector rotate option capable of being used for cross products.

FIG. 7is a schematic diagram of ALU504of transform module52ofFIG. 5in accordance with one embodiment of the present invention. As shown, ALU504of transform module52includes three adders700coupled in parallel/series. In use ALU504of transform module52can add two three component vectors, pass one four component vector, or smear a vector component across the output. Table 5 illustrates various operations of which ALU504of transform module52is capable.

Table 6 illustrates the A and B inputs of ALU504of transform module52.

It is also possible to modify the sign bits of the A and B input by effecting no change, negation of B, negation of A, absolute value A,B. It should be noted that when ALU504outputs scalar vertex data, this scalar vertex data is smeared across the output in the sense that each output represents the scalar vertex data. The pass control signals of MLU500and ALU504are each capable of disabling all special value handling during operation.

FIG. 8is a schematic diagram of the vector register file510of transform module52ofFIG. 5in accordance with one embodiment of the present invention. As shown, the vector register file510includes four sets of registers800each having an output connected to a first input of a corresponding multiplexer802and an input coupled to a second input of the corresponding multiplexer802.

In one embodiment of the present invention, the vector register file510is threaded. That is, there are three copies of the vector register file510and each thread has its own copy. In one embodiment, each copy contains eight registers, each of which might be 128 bits in size and store four floats. The vector register file510is written from ALU504and the output is fed back to MLU500. The vector register file510has one write and one read per cycle.

In operation, it is also possible to individually mask a write operation to each register component. The vector register file510exhibits zero latency when the write address is the same as the read address due to a bypass path511from the input to the output. In this case, unmasked components would be taken from the registers and masked components would be bypassed. The vector register file510is thus very useful for building up vectors component by component, or for changing the order of vector components in conjunction with the ALU SMR operations (See Table 5). Temporary results might be also stored in the vector register file510.

FIG. 9is a schematic diagram of ILU512of transform module52ofFIG. 5in accordance with one embodiment of the present invention. As shown, ILU512of transform module52is capable of generating a floating-point reciprocal (1/D) and a reciprocal square root (1/D^(1/2)). To carry out such operations, either one of two iterative processes might be executed on a mantissa. Such processes might be executed with any desired dedicated hardware, and are shown below:

As shown, the two processes are similar, affording a straightforward design. It should be noted that the iterations might be repeated until a threshold precision is met.

In operation, ILU512performs two basic operations including an inverse operation and inverse square root operation. Unlike the other units, it requires six cycles to generate the output. The input is a scalar, and so is the output. As set forth earlier, the threaded holding register516at ILU512output is relied upon to latch the result until the next time a valid result is generated. Further, the scalar output is smeared into a vector before being fed into MLU500. The inverse unit512uses look-up tables and a two pass Newton-Raphson iteration to generate IEEE (Institute of Electrical and Electronics Engineers) outputs accurate to within about 22 mantissa bits. Table 7 illustrates the various operations that might be performed by ILU512of transform module52.

The foregoing range clamp inversion operation of Table 7 might be used to allow clipping operations to be handled by rasterization module56. Coordinates are transformed directly into screen space that can result in problems when the homogeneous clip space w is near 0.0. To avoid multiplying by 1.0/0.0 in the perspective divide, the 1/w calculation is clamped to a minimum and a maximum exponent.

In use the context memory410as shown inFIG. 5reads and writes only using quad-words. The memory can be read by MLU500or ALU504each cycle, and can be written by ALU504. Only one memory read is allowed per cycle. If a read is necessary, it is done at the start of an instruction and then pipelined down to ALU504three cycles later. Context memory410need not necessarily be threaded.

FIG. 10is a chart of the output addresses of output converter518of transform module52ofFIG. 5in accordance with one embodiment of the present invention. The output converter518is responsible for directing the outputs to proper destinations, changing the bit precision of data, and some data swizzling to increase performance. All data destined for lighting module54is rounded to a 22 bit floating point format organized as S1E8M13 (one sign, eight exponent, 13 mantissa bits). The destination buffers402as shown inFIG. 4in lighting module54are threaded.

Data swizzling is useful when generating vectors. Such technique allows the generation of a distance vector (1,d,d*d) without penalty when producing a vector. The distance vector is used for fog, point parameter and light attenuation. This is done with an eye vector and light direction vectors. Table 8 illustrates the various operations associated with such vectors. It should be noted that, in the following table, squaring the vector refers to d2=dot[(x,y,z), (x,y,z)], and storing d2in the w component of (x,y,z).

It should be noted that the math carried out in the present invention might not always be IEEE compliant. For example, it might be assumed that “0” multiplied by any number renders “0.” This is particularly beneficial when dealing with the equations such as d=d2*1/(d2)½, where d=0. Without making the foregoing assumption, such equation would afford an error, thus causing problems in making related computations.

FIG. 11is an illustration of the micro-code organization of transform module52ofFIG. 5in accordance with one embodiment of the present invention. The transform module micro-code might be arranged into 15 fields making up a total width of 44 bits. Fields might be delayed to match the data flow of the units. MLU500operations are executed at a delay of zero, ALU operations are executed at a delay of one, and RLU, output operations are executed at a delay of two. Each delay is equivalent to three cycles.

FIG. 12is a schematic diagram of sequencer1200of transform module52ofFIG. 5in accordance with one embodiment of the present invention. As shown inFIG. 12, sequencer1200of transform module52includes a buffer1202adapted for receiving the mode bits from VAB50that are indicative of the status of a plurality of modes of process operations.

Also included is memory412capable of storing code segments that each are adapted to carry out the process operations in accordance with the status of the modes. A sequencing module1206is coupled between memory412and a control vector module1205which is in turn coupled to buffer1202for identifying a plurality of addresses in memory412based on a control vector derived from mode bits202. The sequencing module1206is further adapted for accessing the addresses in memory412for retrieving the code segments that might be used to operate transform module52to transfer data to an output buffer1207.

FIG. 13is a flowchart delineating the various operations associated with use of sequencer1200of transform module52ofFIG. 12. As shown, sequencer1200is adapted for sequencing graphics-processing in a transform or lighting operation. In operation1320, mode bits202are first received which are indicative of the status of a plurality of modes of process operations. In one embodiment, mode bits202might be received from a software driver.

Then, in operation1322, pluralities of addresses are then identified in memory based on mode bits202. Such addresses are then accessed in the memory in operation1324for retrieving code segments that each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed with a transform or lighting module for processing vertex data. Note operation1326.

FIG. 14is a flow diagram delineating the operation of the sequencing module1206of sequencer1200of transform module52ofFIG. 12. As shown, a plurality of mode registers1430each include a unique set of mode bits202which in turn correspond to a single vertex. It should be noted that mode registers1430are polled in a round robin sequence in order to allow the execution of multiple execution threads in the manner set forth earlier during reference toFIGS. 4A and 4B.

Once the current execution thread is selected, a corresponding group of mode bits202are decoded in operation1432. Upon mode bits202being decoded in operation1432, a control vector is afforded which includes a plurality of bits each of which indicate whether a particular code segment is to be accessed in ROM1404for processing the corresponding vertex data.

Upon determining whether a code segment should be accessed in ROM1404and executed, a pointer operation1436increments the current thread pointer to start the next execution thread to obtain a second group mode bits202to continue a similar operation. This might be continued for each of the threads in a round robin sequence.

Once the control vector has been formed for a particular group of mode bits202, a priority encoder operation1438determines, or identifies, a next “1” or enabled, bit of the control vector. If such a bit is found, the priority encoder operation1438produces an address in ROM1404corresponding to the enabled bit of the control vector for execution purposes.

Upon returning to the initial group of mode bits202after handling the remaining threads, and after the mode bits have been decoded and the control vector is again available, a masking operation1434might be used to mask the previous “1”, or enabled, bit that was identified earlier. This allows analysis of all remaining bits after mask operation1434.

The foregoing process might be illustrated using the following tables. Table 9 shows a plurality of equations that might be executed on subject vertex data.

As shown, there are four possibilities of products that might be summed in addition to an inverse operation (a, b*c, d*e, f, and 1/x). Next, mode fields might be defined. Table 10 illustrates a pair of mode fields, mode.y and mode.z, each having assigned thereto a predetermined set of the operations of Table 9.

Thereafter, each of the operations might be positioned in memory with an associated address. Table 11 illustrates a plurality of memory addresses each having an associated operation. Also shown is a set of control vector definitions.

Table 12 illustrates the execution of an example.

TABLE 12R = a+d*e corresponds to:mode.y = 1;mode.z = 0;which in turn affords the following control vector:cv[0] = 1;cv[1] = 0;cv[2] = 1;cv[3] = 0;cv[4] = 0;executionfirst cycle:cv[0] is TRUE so execute ROM[0]more TRUE values in control vector, so do not terminateprogramsecond cycle:cv[1] is FALSE so keep lookingcv[2] is TRUE so executre ROM[2]no more TRUE values in control vector, so terminateprogram

As such, sequencer1200of transform module52steps through a threaded control vector which is derived from threaded mode bits202, and executes every ROM address whose corresponding control vector bit is set to “TRUE”. The control vector has the same length as the ROM. The sequencer1200is capable of stepping through an arbitrary control vector at the rate of one “1”, or enabled bit per a predetermined number of cycles. Commands that do not use mode bits202might be executed by on-the-fly micro-code generation due to the simplicity thereof.

By representing such statuses by way of a unique string of mode bits202, it is unnecessary to execute a plurality of if-then clauses in the graphics-processing hardware to determine the statuses of the various operations. Improved performance is thereby afforded. Conceptually, it is as if the if clauses in a program language had been moved to sequencer1200which in turn instantly skips instructions with a “FALSE” condition, as indicated by mode bits202.

As indicated earlier, code segments are stored in the ROM which are capable of handling the various statuses of the operations identified by the mode bits. In one embodiment a separate code segment might be retrieved for handling each operation indicated by the mode bits. In the alternative, a single comprehensive code segment might be written for handling each or some combinations of operations that are possible. It should be noted, however, that generating such large code segments for each combination of operations requires additional code space, and it therefore might be beneficial to modularize the code segments for only commonly used combinations of operations.

Since mode bits202do not change once the vertex commences execution, the control vector generation might only have to be done once per vertex before entering the sequencer. Exceptions to this might arise in some cases, however, such as lighting where operations might be repeated. When the last vertex instruction is found, an end of sequence (EOS) signal might be asserted. This in turn might be used to change the status of the input and output buffers, and to allow the start of the next command in a manner that will be set forth during reference toFIGS. 28A and 28B. It should be noted that the EOS signal is pipeline delayed for release of the destination buffer similar to the manner in which the instructions are handled. SeeFIG. 4B.

FIG. 14Ais a flow diagram illustrating the various functional components of the present invention employed for integrating the handling of scalar and vector vertex data during graphics-processing. As shown, one functional aspect1440includes inputting vector vertex data into a processing module, i.e. adder, multiplier, etc., for outputting vector vertex data. In another functional aspect1442, vector vertex data is processed by a vector processing module, i.e. adder, multiplier, etc., which outputs scalar vertex data that is in turn converted, or smeared, again into vector vertex data.

In yet another functional aspect1444, vector vertex data is masked, thereby converted to scalar vertex data, after which it is stored in memory, i.e. register logic unit, for the purpose of generating vector vertex data. In still yet another functional aspect1446, scalar vertex data is extracted by a vector processing module, i.e. adder, multiplier, etc., which in turn is processed by a scalar processing module, i.e. inverse logic unit, which renders scalar vertex data. This scalar vertex data is converted again into vector vertex data.

FIG. 14Bis a flow diagram illustrating one possible combination1451of the functional components of the present invention shown inFIG. 14Awhich corresponds to transform module52ofFIG. 5. It should be noted that functional aspects1444and1446might have delays associated therewith in a manner similar to that set forth earlier during reference toFIG. 4B.FIG. 14Cis a flow diagram illustrating yet another possible combination1453of the functional components of the present invention shown inFIG. 14A.

Multiplexers might accomplish the extraction of the scalar vertex data from the vector vertex data in the functional modules ofFIGS. 14A–14C. Such multiplexers might also be responsible for any data swizzling that might be required before processing by the various functional modules. In one embodiment, the multiplexers might be capable of passing and rotating vector vertex data, and rely on other graphics-processing modules such as an ALU for other processing. In yet another embodiment, the multiplexers might be capable of arbitrarily rearranging attributes independently without penalty.

FIG. 14Dillustrates a method in which the transform system is adapted for performing a blending, or skinning operation during graphics-processing in a graphics pipeline via a hardware implementation such as an application specific integrated circuit (ASIC). During processing in the pipeline, in operation1470, a plurality of matrices, a plurality of weight values each corresponding with one of the matrices, and vertex data are received. It should be noted that an additional set of matrices might be required for normal vertex data.

Subsequently, in operation1472, a sum of a plurality of products is then calculated with each product being calculated by the multiplication of the vertex data, one of the matrices and the weight corresponding to the matrix. Such sum of products is then outputted in operation1474for additional processing.

It should be noted that there are many ways to represent the weights w1set forth hereinabove. For example, in Equations #1 and #2 above, it might be said that i=1 . . . (x−1), leaving wx(w1where i=x) to be calculated by the equation 1−Σwi. By representing the weights w1in this way, it is ensured that all of the weights w sum to 1.

In one embodiment, the matrices might include model view matrices (M), and the sum of products (v′) might be outputted for additional processing by a lighting operation. See Equation #1. This sum of products (v′) might also be used to generate another sum of products (vs) for display purposes by using a composite matrix (C). See Equation #3. Still yet, the matrices might include inverse matrices (I) and the vertex data might include normal vector data (n). In such case, the additional processing might include a lighting operation. See Equation #2.

FIG. 15is a schematic diagram of lighting module54in accordance with one embodiment of the present invention. As shown, lighting module54includes buffers402to which transform module52outputs the vertex data. As shown, buffer408bypasses lighting module54by way of the pathway1501. Further coupled to lighting module54is a context memory1500and micro-code ROM memory1502.

The lighting module54is adapted for handling lighting in addition to fog and point parameters. In use lighting module54controls the buffer bypass pathway1501, and calculates the diffuse, point size, and specular output colors as well as the fog value. It should be noted that lighting module54employs the same mode bits202as transform module52.

The lighting module54further requires less precision with respect to transform module52, and therefore processes 22 bit floating point values (1.8.13 format) organized in tri-words. Since the data of third buffer408is 128 bits, it utilizes bypass pathway1501around lighting module54. The lighting module54is event driven and simultaneously executes three threads in a manner similar to transform module52as was set forth earlier with reference toFIGS. 4A and 4B. It should be noted that lighting module54might require command launch approval from an outside source.

FIG. 16is a schematic diagram showing the functional units of lighting module54ofFIG. 15in accordance with one embodiment of the present invention. As shown, included are input buffers402adapted for being coupled to a transform system for receiving vertex data therefrom. As set forth earlier, input buffers402include a first input buffer404, a second input406, and a third input buffer408. An input of first buffer404, second input buffer406, and third input buffer408are coupled to an output of transform module52. For bypass purposes, the output of third buffer408is coupled to the output of lighting module54via a delay1608.

Further included is a MLU1610having a first input coupled to an output of first input buffer404and a second input coupled to an output of second input buffer406. The output of MLU1610has a feedback loop1612coupled to the second input thereof. An arithmetic logic unit (ALU)1614has a first input coupled to an output of second input buffer406. ALU1614further has a second input coupled to an output of MLU1610. An output of ALU1614is coupled to the output of lighting module54. It should be noted that the output of ALU1614and the output of the third input buffer408are coupled to the output of lighting module54by way of multiplexer1616.

Next provided is a first register unit1618having an input coupled to the output of ALU1614and an output coupled to the first input of ALU1614. A second register unit1620has an input coupled to the output of ALU1614. Also, such second register1620has an output coupled to the first input and the second input of MLU1610.

A lighting logic unit (LLU)1622is also provided having a first input coupled to the output of ALU1614, a second input coupled to the output of the first input buffer404, and an output coupled to the first input of MLU1610. It should be noted that the second input of LLU1622is coupled to the output of the first input buffer404via a delay1624. Further, the output of LLU1622is coupled to the first input of MLU1610via a first-in first-out register unit1626. As shown inFIG. 16, the output of LLU1622is also coupled to the first input of MLU1610via a conversion module1628. In operation, such conversion module1628is adapted for converting scalar vertex data to vector vertex data in a manner similar to that of transform module52.

Finally, memory1500is coupled to at least one of the inputs of MLU1610and the output of arithmetic logic unit1614. In particular, memory1610has a read terminal coupled to the first and the second input of MLU1610. Further, memory1500has a write terminal coupled to the output of ALU1614.

The memory has stored therein a plurality of constants and variables for being used in conjunction with input buffers402, MLU1610, ALU1614, first register unit1618, second register unit1620, and LLU1622for processing the vertex data.

FIG. 17is a schematic diagram of MLU1610of lighting module54ofFIG. 16in accordance with one embodiment of the present invention. As shown, MLU1610of lighting module54includes three multipliers1700in parallel. In operation, the present MLU1610is adapted to multiply two three component vectors, or pass one three component vector. The multiplication of the three component vectors might be accomplished by way of a dot product or a parallel multiply. Table 13 illustrates the operations that MLU1610of lighting module54is capable of performing.

Table 14 illustrates the possible A and B inputs of MLU1610of lighting module54.

FIG. 18is a schematic diagram of ALU1614of lighting module54ofFIG. 16in accordance with one embodiment of the present invention. As shown, ALU1614includes three adders1800in parallel/series. In use ALU1614is capable of adding two three component vectors, or passing one three component vector. Table 15 illustrates the various operations of which ALU1614of lighting module54is capable.

Table 16 illustrates the possible A and B inputs to ALU1614of lighting module54.

FIG. 19is a schematic diagram of register units1618and1620of lighting module54ofFIG. 16in accordance with one embodiment of the present invention. As shown, register units1618and1620each include two sets of registers1900each having an output connected to a first input of a corresponding multiplexer1902and an input coupled to a second input of multiplexer1902.

Register units1618and1620of lighting module54are split into two registers for ALU1614and two registers for MLU1610. In one embodiment, the registers are threaded. The register units1618and1620exhibit zero latency when a write address is the same as a read address due to a bypass path from the input to the outputs.

FIG. 20is a schematic diagram of LLU1622of lighting module54ofFIG. 16in accordance with one embodiment of the present invention. LLU1622is the lighting unit of lighting module54. It is a scalar block that computes lighting coefficients later used to multiply the light+material colors. LLU1622includes two MAC's, an inverter, four small memories, and a flag register.

The flag register is used to implement the conditional parts of the lighting equations. The outputs are an ambient, diffuse, and specular coefficient. The scalar memories contain variables used for the specular approximations and constants. The first location of each memory contains 1.0 (for ctx0and ctx2) and 0.0 (for ctx1and ctx3). In one embodiment, these are hardwired and do not need to be loaded.

In use LLU1622fundamentally implements the equation: (x+L)/(M*x+N). This equation is used to approximate a specular lighting term. The inputs to LLU1622are from ALU1614of lighting module54and are the dot products used in the lighting equations. As set forth earlier, with respect toFIG. 16, there is an output FIFO1626between LLU1622and MLU1610which buffers coefficients until MLU1610needs them. In one embodiment, such FIFO1626might be threaded along with delays1608and1624, and registers1618and1620. Due to possible color material processing, it is unknown when the diffuse and specular outputs are consumed by MLU1610.

There is specially adapted hardware for dealing with the diffuse output alpha component since lighting module54only deals with R,G,B components. Such specially adapted hardware is capable of outputting two types of alpha components, namely vtx colorø α[Tbuffer], and stored ctx α[Ctx store]. The choice between the foregoing alpha components is governed by mode bits202.

In operation, LLU1622calculates ambient (Ca), diffuse (Cde), and specular (Cs) coefficients of lighting. These coefficients are then multiplied with the ambient, diffuse, and specular colors to generate a light's contribution to the vertex color. Table 16A includes a list of inputs received by LLU1622and the calculations carried out to generate the ambient (Ca), diffuse (Cde), and specular (Cs) coefficients of lighting. It should be noted that any desired hardware configuration might be employed to implement LLU1622. In one embodiment, the specific configuration shown inFIG. 20might be employed.

As set forth above, the mode bits controlling the vertex sequencer might not necessarily be changed by the vertex data itself or by any results derived from vertex data. To allow vertex data to modify vertex processing, LLU1622employs a flag register1623is provided. Setting bits to TRUE in this flag register allows clamping to 0.0 of calculation results if a flag is specified in the output control of the calculation. Another use of the flag register1623would be in setting a write mask for register writes.

The flag register1623is provided in LLU1622for performing the if/then/else clamping to 0.0 in the lighting equations at no performance penalty. The sign bit of various operands might set the flags. Table 16B illustrates the manner in which the flags in flag register1623are set and the resulting clamping.

FIG. 21is an illustration of the organizaiton of the flag register1623associated with lighting module54ofFIG. 16in accordance with one embodiment of the present invention. The flag register1623contains 8 one bit flags and are set by the sign bit of the ALU (IFLAG) or MAC0(MFLAG) outputs.

When LLU1622outputs a scalar value to MLU1610where it gets smeared into a tri-word, it specifies a mask for the flag register. If the register & mask is true, 0.0 replaces the output. Table 17 illustrates the various flags ofFIG. 21to be used in outputting ambient, diffuse, and specular attributes.

The approximation used for the specular term can go negative where the actual cos (theta)**n would go to 0.0. As a result, it is necessary to perform a clamping operation. For this, the T, U flags are used. Table 18 illustrates various operations of which a functional logic unit(FLU)1621of LLU1622is capable. NoteFIG. 20.

FIG. 22is an illustration of the micro-code fields associated with lighting module54ofFIG. 16in accordance with one embodiment of the present invention. As shown, the micro-code of lighting module54is arranged into 33 fields making up a total width of 85 bits. Fields are delayed to match the data flow of the units. The MLU operations are done at a delay of zero, ALU operations are done at a delay of one, and RLU, LLU output operations are done at a delay of two. Each delay is equivalent to three cycles.

FIG. 23is a schematic diagram of sequencer2300associated with lighting module54ofFIG. 16in accordance with one embodiment of the present invention. As shown, sequencer2300of lighting module54includes an input buffer2302adapted for receiving mode bits202which are indicative of the status of a plurality of modes of process operations. Also included is memory1502capable of storing code segments that each are adapted to carry out the process operations in accordance with the status of the modes.

A sequencing module2306is coupled between memory1502and buffer2302for identifying a plurality of addresses in memory1502based on a control vector2305derived from the mode bits. The sequencing module2306is further adapted for accessing the addresses in memory1502for retrieving the code segments that might be used to operate lighting module54.

The sequencer2300of lighting module54is similar to that of transform module52. In operation, sequencer2300of lighting module54steps through a threaded control vector that is derived from threaded mode bits202and executes every ROM address whose corresponding control vector bit is set to “1”. The control vector has the same number of bits as the ROM has words. The sequencer2300can step through an arbitrary control vector at the rate of a single “1” or enabled bit per a predetermined number of cycles for every thread. Commands that do not use mode bits202are executed by on-the-fly micro-code generation. The main difference between sequencer2300of lighting module54and sequencer1200of transform module52is that sequencer2300of lighting module54can loop back and execute the lighting code up to eight times.

The sequencer2300of lighting module54has a light counter that starts at zero for each new vertex and increments by one at the end of the micro-code sequence. If the LIS field of mode bits202contains a “1” in the matching bit field, sequencer2300goes back and starts over at the beginning of the lighting micro-code block. This continues until a zero is found in the LIS field or eight lights have been done. Color accumulation is done by incrementing (per light) the ALU registers that store the diffuse and specular color. Automatic memory address indexing is done using the light counter to fetch the correct parameters for each light.

FIG. 24is a flowchart delineating the method by which the sequencers of the transform and lighting modules52and54are capable of controlling the input and output of the associated buffers in accordance with one embodiment of the present invention. As shown, vertex data is initially received in a buffer of a first set of buffers in operation2420. The buffer in which the vertex data is received is based on a round robin sequence.

Subsequently, in operation2422, an empty buffer of a second set of buffers is identified also based on a round robin sequence. The transform module52is coupled between the first set of buffers and the second set of buffers. When the empty buffer of the second set of buffers is identified, the vertex data is processed in transform module and outputted from transform module to the identified empty buffer of the second set of buffers. Note operations2424and2426.

Similarly, an empty buffer of a third set of buffers, or slots or spaces in memory, are identified based on a round robin sequence in operation2428. The lighting module54is coupled between the second set of buffers and the third set of buffers. When the empty buffer of the third set of buffers is identified, the vertex data is processed in the lighting module, as indicated in operation2430. The vertex data is subsequently outputted from lighting module52to the identified empty buffer of the third set of buffers. See operation2432. It should be noted that the number of buffers, or slots in memory, is flexible and might be changed.

FIG. 25is a diagram illustrating the method by which the sequencers of the transform and lighting modules52and54are capable of controlling the input and output of the associated buffers in accordance with the method ofFIG. 24. As shown, the first set of buffers, or input buffers400, feed transform module52which in turn feed the second set of buffers, or intermediate buffers404,406. The second set of buffers404,406feed lighting module54that drains to memory2550.

In order carry out the method set forth inFIG. 25, the slots of memory2550and the buffers of the first and second set are each assigned a unique identifier upon initially receiving vertex data. Further, a current state of each buffer is tracked. Such state might include an allocated state, a valid state, an active state, or a done state.

The allocated state indicates that a buffer/slot is already allocated to receive an output of the previous graphics-processing module, i.e. transform module or lighting module. When a write pointer is scanning the buffers/slots in the round robin sequence, a buffer/slot in the allocated state cause such write pointer to increment to the next buffer or slot.

If a buffer/slot is in the valid state, the buffer/slot is available for receiving vertex data. On the other hand, the active state indicates that a buffer/slot is currently in an execution state, or receiving vertex data. This active status is maintained until a thread is done after which a read pointer increments, thus placing the buffer/slot back in the valid state. It should be noted that the first set of buffers400are only capable of being in the valid state since there is no previous graphics-processing module to allocate them.

An example of a sequence of states will now be set forth. Upon receiving vertex data in one of the first set of buffers400and a new set of command bits200, such buffer is placed in the valid state, after which one of the second set of buffers402,404is placed in the allocated state in anticipation of the output of transform module52.

If none of the second set of buffers404,406is available for allocation, the vertex data in the buffer of the first set400can not be processed. Further, a check might be done to determine whether the code segments to be executed will interfere with any other code segments that are to be simultaneously run. If so, the vertex data in the buffer of the first set400will not be processed and a stall condition initiated.

After one of the second set of buffers404,406is placed in the allocated state, the buffer of the first set400is placed in the active state. When transform module52is finished execution, the buffer of the second set404,406is read and then placed in the valid state. These state changes are similarly executed during the transfer of vertex data between the second set404,406and the slots of memory2550.

FIG. 25Billustrates the rasterizer module56that comprises a set-up module57and a traversal module58. The rasterizer module56is adapted for performing area-based rasterization in an alternating manner. In particular, a plurality of polygon-defining sense points are positioned on or near the primitive after which line equations are evaluated at the points to determine which pixels reside in the primitive. During operation, this evaluation is repeated as the points are moved in an alternating manner for efficiency purposes. Further, the rasterizer module56might be adapted to operate without any clipping procedure.

FIG. 26illustrates a schematic of the set-up module57of rasterization module56. As shown, the set-up module57includes a control section61that handles routing data and control signals to their appropriate finctional units in order to perform the desired floating-point calculations. The primitive sequencer62handles turning sequences of vertices into triangles, lines or points. Further, floating point data path section64includes the multiplexers and floating point computation units that perform the math required in the set-up unit.

With continuing reference toFIG. 26, output formatting section63handles converting the internal floating point format of edge slopes and edge values into integer formats suitable for the rasterizer since the rasterizer operates only with integer values. Of course, in alternate embodiments, the rasterizer might use a floating point thus obviating the need for output formatting section63.

In operation, output formatting section63executes a block floating point conversion. As is well known, with a given number, i.e. 2.34 e10, floating point format tracks a mantissa (2.34) and an exponent (10) thereof. Block floating point conversion essentially manipulates the decimal place of the mantissas of incoming data such that the exponents are the same. To this end, the exponent need not be handled in rasterizer module56.

FIG. 26Ais an illustration showing the various parameters calculated by set-up module57of rasterizer module56ofFIG. 25B. Such parameters are required for rasterizer module56to perform the associated functions. Upon receipt of a primitive2600, set-up module57calculates three values including slopes2601of the primitive2600, a starting position2602and a starting value2604.

The slopes2601are used to generate coefficients for line equations of the edges of the primitive2600to be used during rasterization. The slopes2601might, for example, be calculated by using equations #4 and #5 shown below.
slopeA=y0−y1
slopeB=x1−x0Equations #4 and #5where y0, y1and x0, x1are coordinates of vertices shown inFIG. 26A.

It should be noted that the slopes might also be calculated using the coordinates of the vertices by employing a simple rotation operation or the like.

The starting position2602indicates a starting point for area rasterization that will be set forth hereinafter in greater detail. The starting value2604is equal to the area of the shaded triangle shown inFIG. 26Aand is also used during the area-based rasterization process. Such starting value2604is selected so that stepping the raster position about the screen while adding the slope at each step will equal zero exactly when the raster position is on the edge. Calculation of the starting value2604might be accomplished using Equation #46 below:
starting_value=slopeA* (xs−x0)+slopeB* (ys−y0)  Equation #6
wherexs, ys=starting position2602slopeA, slopeB=slopes of one of the edges based on coordinates of vertices shown inFIG. 26Ax0, y0=coordinates of one of the vertices of the edges shown inFIG. 26A

It should be understood that the foregoing values might also be calculated for other types of primitives. For example, in the case of a line, an extra slope must be calculated for the four-sided bounding box. Such slope can be easily calculated by taking the reciprocal of the slope of an opposite side of the bounding box. In addition to the extra slope calculation, it is noted that another starting value needs to be calculated in the case of the line primitive.

FIG. 27illustrates the method by which rasterizer module56handles one of a plurality of primitives, e.g. triangles. In particular, an initial operation is first performed by set-up module57of rasterizer module56. Upon receipt of a primitive, line equation coefficients of line equations are determined for lines that define the primitive in operation2700using slopes2601ofFIG. 26Ain a manner that is well known to those with ordinary skill in the art. As is well known, three line equations are required to define a triangle. On the other hand, a primitive such as a line is drawn as a rectangle or parallelogram with four sides and four line equations.

Thereafter, in operation2702, the line equation coefficients are modified if any primitive vertex(es) has a negative W-coordinate. Additional information regarding this process will be set forth hereinafter in greater detail with reference toFIG. 32.

It should be noted that set-up module57of rasterizer module56also computes a bounding box of the primitive. For most triangles, the bounding box includes the minimum and maximum values of the three vertexes. For lines, the four parallelogram comers of the bounding box are calculated. For triangles or lines that have a vertex with a negative W-coordinate, an area that is to be drawn extends beyond the convex hull of the vertices.

One of the commands of OpenGL® is a scissor rectangle which defines a boundary outside of which is not to be drawn. The set-up module57of rasterizer module56calculates the intersection of the bounding box and the scissor rectangle. Since the scissor rectangle is a rectangle, four additional line equations are afforded. It should be noted that the line equations associated with the scissor rectangle have a trivial form, i.e. horizontal or vertical.

Furthermore, in 3-D space, the near plane and far plane are parallel and at right angles to the line of sight. In the case of the primitive being a triangle, three vertexes are included which define a plane that might have any orientation. The intersections of the plane of the primitive and the near and far planes include two lines with two associated line equations.

Accordingly, each primitive has a total of nine or ten line equations depending on whether it takes the form of a triangle or a line, respectively. Again, in the case of the triangle, such line equations include the three line equations which define the triangle, the four line equations defining the bounding box and the two line equations which define the intersections of the plane in which the primitive resides, and near and far planes.

With continuing reference toFIG. 27, the process progresses in operation2704by positioning a plurality of points on or near the primitive. The starting position2602dictates such positioning, as shown inFIG. 26A. Such points define an enclosed convex region and reside at comers of the convex region.FIG. 27Aillustrates such sense points2705that enclose convex region2707, e.g. a rectangle. In one embodiment, such rectangle might be 8×2 pixels in size. Further, the points might be initially positioned to enclose a top vertex of the primitive. As an option, this might be accomplished using truncation.

Once the primitive is positioned, the process is continued by traversal module58which begins in operation2706by processing rows of the primitive in a manner set forth below. After the processing of each row, it is determined whether a jump position has been found in decision2708. A jump position is a starting position for processing the next row and will be described hereinafter in greater detail. If it is determined in decision2708that a jump position has been found, the sense points that define the convex region are moved thereto in operation2710. If, however, it is determined that a jump position has not been found, the process is ended. It should be noted that, in an alternate embodiment, columns, diagonals or any other type of string might be processed in operation2706instead of rows.

FIG. 28is a flowchart illustrating a process of the present invention associated with the process row operation2706ofFIG. 27. As shown, the process begins by computing the sense points in operation2800in order to determine whether the polygon-defining sense points might be moved right in decision2801. Such decision is made based on the position of the rightmost sense points. If the rightmost sense points are not positioned outside the same edge or edges of the primitive, rightward movement is permitted and a position (X and Y coordinates) to the right of the current position is stored as a snap location in operation2802. If, however, both rightmost sense points are positioned outside one or more edges of the primitive, rightward movement is not permitted and operation2802is skipped.

Next, the line equations are evaluated at the points of the convex region, e.g. rectangle, in operation2804. The evaluation includes determining if the points reside in the primitive. Such determination as to whether the points reside in the primitive might include determining whether the evaluation of each of the line equations renders a positive value or a negative value at each of the sense points.

The line equations can be formulated to be positive inside the primitive and negative outside. Inclusive edges, for which pixels that lie exactly on the edge should be drawn, evaluate to zero and might be treated as positive. Exclusive edges, which should not be drawn, can be made negative by initially subtracting a value of one from the starting line equation value. Thus pixels on exclusive edges evaluate to a negative value (−1) instead of a positive zero. This permits the sense point interpretation to ignore the inclusive/exclusive policy and just test the line equation sign.

After the line equations are evaluated at the points, it is determined whether a current position of the sense points constitutes a jump position in decision2806. It should be noted that a jump position is stored only if the two bottom sense points are not both outside an edge. If it is determined in decision2806that a jump position has been found, the jump position is calculated and stored (or replaces a previously stored jump position if existent) in operation2808. If not, however, operation2808is skipped.

With continuing reference toFIG. 28, it is then determined in decision2810whether leftmost sense points are both outside an edge of the primitive. Again, this process entails determining whether the evaluation of the line equations at both of the leftmost sense points renders positive or negative values. In particular, upon computation of the coefficients of the nine or ten edge equations at the pertinent sense points, nine or ten values are rendered that have nine or ten sign bits. To determine if the current side is completely outside any edge, for example, the present invention AND's the ten sign bits from the two sense points together. If any bit(s) survive, then both points are outside that edge.

If it is determined that the leftmost sense points are not both outside an edge of the primitive, it is concluded that there still remains further portions of the primitive to be considered in the leftward direction, and the sense points are moved left in operation2812. If it is determined in decision2810that both leftmost sense points are indeed outside the edge of the primitive, it is concluded that there no longer remains further portions of the primitive to be considered in the leftward direction. Next, in decision2814, it is determined whether there is a snap location that resulted from operation2802.

If it is determined in decision2814that a snap location does not exist, the process is done. If, however, a snap location does exist, the sense points are moved to the snap location in operation2816. Thereafter, operations similar to those of operations2804–2812are executed to map a right side of the primitive. This begins in operation2818by the line equations being evaluated at the points of the convex region.

After the line equations are evaluated at the points, it is determined whether a current position of the sense points constitLites a jump position in decision2820. If it is determined in decision2806that a jump position has been found, the jump position is calculated and stored in operation2822. If not, however, operation2822is skipped.

With continuing reference toFIG. 28, it is then determined in decision2824whether rightmost sense points are both outside an edge of the primitive. If it is determined that the rightmost sense points are not both outside an edge of the primitive, it is concluded that there still remains further portions of the primitive in the rightward direction to be considered, and the sense points are moved right in operation2826. If it is determined in decision2824that both rightmost sense points are outside the edge of the primitive, it is concluded that there no longer remains further portions of the primitive to be considered in the rightward direction, and the instant process is done.

FIGS. 28A and 28Bare illustrations of the sequence in which the sense points of the present invention might be moved about the primitive2850. It should be noted that various alterations might include determining whether the points can go left in decision2800and proceeding right initially. Further, the line equations might be defined to indicate whether the points are inside or outside the primitive in any desired way.

To avoid stepping in a repeating loop, the present invention thus employs an overall direction of movement during rasterization. The initial implementation proceeds top-down, visiting every convex region on a row before stepping down to the next. By processing rows top-down as well as never stepping right then left or left then right, loops are thus avoided.

An example of the foregoing process might be shown with reference to the polygon-defining points, P1, P2, P3and P4ofFIG. 27A. In operation, pairs of adjacent sense points can be examined to determine whether stepping in their direction would be productive. For example, if both P3and P4inFIG. 27Awere outside of an edge of a polygon, but P1and/or P2are not, then clearly the drawable inside region lies to the left, not to the right. Thus the sense points should not move right. Conversely, if both P3and P4are inside all the edges, then there is a drawable area just beyond P3and P4, and stepping right is appropriate. Indeed, if P3and P4were not outside the same edge or edges, stepping right would be productive. This same logic applies to stepping upwards guided by P1and P3, or stepping left guided by P1and P2, or stepping downwards based on P2and P4.

The foregoing process thus moves, or steps, the convex region defined by the points around the inside of the primitive, using sense points as a guide. Since the convex region defined by the points might be large, many pixels might be tested simultaneously. During use, if all sense points are inside all edges of the primitive, then all the enclosed pixels must be drawable (assuming a convex primitive). A significant advantage is afforded by testing the comers, namely the ability of proving an arbitrary area of the primitive is inside, outside or split. Only in the latter case do the individual pixels in the convex region defined by the points need to be tested. In such case, the pixels in the convex region defined by the points might be tested one-by-one or by another method in order to determine whether they reside in the primitive. Furthermore, the sense points might reduce the amount of further testing required by defining which edges(s) split the area and which do not.

FIG. 29is a flowchart illustrating an alternate boustrophedonic process of the present invention associated with the process row operation2706ofFIG. 27. As shown, it is first determined in decision2900whether a previous movement was in a first or second direction. If there was not any actual previous movement, a default previous movement might be assumed. If it is determined in decision2900that the previous movement was in a second direction, the line equations are evaluated at the points of the convex region, e.g. a rectangle, in operation2902in a manner similar to operation2804ofFIG. 28.

With continuing reference toFIG. 29, it is subsequently determined in decision2904as to whether sense points of a first side of the rectangle are both outside an edge of the primitive. If not, the sense points are moved or stepped in the first direction in operation2906. Upon it being determined that the sense points of the first side of the rectangle are both outside an edge of the primitive, it is then determined in decision2905whether the points can be moved downwardly or, in other words, whether the current position constitutes ajump position. If so, ajump position is calculated and stored in operation2908after which the process is done.

On the other hand, if it is determined in decision2900that the previous movement was in a first direction, operations similar to those of operation2902–2908are carried out. In particular, the line equations are evaluated at the points of the convex region, e.g. a rectangle, in operation2910. It is then determined in decision2912as to whether sense points of a second side of the rectangle are both outside an edge of the primitive. If not, the sense points are moved or stepped in the second direction in operation2914. Upon it being determined that the sense points of the second side of the rectangle are both outside an edge of the primitive, it is then determined in decision2913whether the points can be moved downwardly or, in other words, whether the current position constitutes a jump position. If so, a jump position is calculated and stored in operation2916after which the process is done.

FIG. 29Ais an illustration of the sequence in which the sense points of the present invention are moved about the primitive in accordance with the boustrophedonic process ofFIG. 29. The foregoing boustrophedonic rasterization constrains the sequence to obey certain rules that offer better performance for hardware. As shown, the boustrophedonic rasterization affords a serpentine pattern that folds back and forth. A horizontal boustrophedonic sequence, for example, might generate all the pixels within a primitive triangle that are on one row from left to right, and then generate the next row right to left, and so on. Such a folded path ensures that an average distance from a generated pixel to recently previously generated pixels is relatively small.

Generating pixels that are near recently previously generated pixels is important when recent groups of pixels and/or their corresponding texture values are kept in memories of a limited size. The boustrophedonic sequence more often finds the pixels or texture values already loaded into such memories, and therefore repeating the memory load occurs less often.

As an option, at least one boundary might be used which divides the primitive into a plurality of portions prior to rasterization. In operation, the points might be moved in each of the portions separately. Further, the points might be moved through an entirety of a first one of the portions before being moved in a second one of the portions.

FIG. 30is a flowchart illustrating an alternate boustrophedonic process using boundaries. As an option, the decision whether to use boundaries might be based on a size of the primitive. As shown inFIG. 30, the boustrophedonic process which handles boundaries is similar to that ofFIG. 27with the exception of an additional operation3000wherein at least one boundary is defined which divides the primitive into a plurality of portions or swaths.

With continuing reference toFIG. 30, an additional decision3001follows the completion of every portion of the primitive. In particular, it is determined in decision3001whether a start position of an adjacent portion was found in operation3006. If so, the convex region defined by the sense points is moved to a start position of an adjacent portion of the primitive in operation3002and operations3004–3010are repeated for the new portion of the primitive. Further information relating to the determination of the start position in operation3006will be set forth in greater detail during reference toFIG. 31.

FIG. 31Ais an illustration of the process by which the convex region of the present invention is moved about the primitive in accordance with the boundary-based boustrophedonic process ofFIG. 30. As shown, the first portion that is processed is that which includes the topmost vertex of the primitive. During operation, a left neighboring portion is processed after which the adjacent left neighboring portion is processed and so on. This is continued until there are no remaining left neighboring portions. Next, a neighboring portion to the right of the first portion is processed after which the adjacent right neighboring portion is processed and so on until all of the right neighboring portions are processed. It should be appreciated that other types of ordering schemes might be utilized per the desires of the user.

FIG. 31is a flowchart showing the process associated with the process row operation3006ofFIG. 30. Such process is similar to the boustrophedonic process ofFIG. 29with the exception of decisions3118through3121. Decisions3118and3120both determine whether any of the sense points have passed any boundary. Only if it is determined that the sense points are still within the boundaries is the respective loop continued.

In operations3119and3121, starting positions of adjacent portions of the primitive are sought and stored when it is determined in decisions3118and3120that any sense points of the convex region have passed any boundary, respectively. As shown inFIG. 31A, such starting positions3126are each defined as being the topmost point of a portion of the primitive existent beyond a boundary. By storing this position, a starting point is provided when the process is repeated for the adjacent boundary-defined portion of the primitive.

It should be noted that operations3119and3121are both performed while processing the first portion of the primitive. While not expressly shown inFIG. 31, only a first one of such operations is performed when processing portions to the left of the first portion, while only a second one of such operation is performed when processing portions to the right of the first portion. In other words, when processing portions to the left of the first portion, starting positions are only determined when a leftmost boundary of the currently processed portion has been exceeded. Similarly, when processing portions to the right of the first portion, starting positions are only determined when a rightmost boundary of the currently processed portion has been exceeded.

Using boundaries during rasterization solves a very critical problem during pipeline processing. If a primitive is very wide, the storage associated with the pixels of a single row might not fit in a limited-size memory. Rasterization with boundaries divides the triangle into limited-width rows (or columns), and generates all the pixels within such a portion before moving on to the next portion.

For example, even if a triangle is 100 pixels wide, a limited-size pixel or texture memory might only hold information for the previous 20 pixels. Constraining the pixel sequence to stay within ten-pixel-wide vertical portions allows all the pixels on the previous and current rows to fit in the memory. This means that a boustrophedonic sequence within a boundary-defined portion would always have the previous pixel on the current row (if any) in the memory, as well as the pixels in the row above (if any) in the memory as well.

Most underlying memory systems transfer blocks of data with a certain overhead per block. Small accesses to the memory system are penalized heavily by this overhead. In order to be efficient, larger accesses are employed and the rest of the block is maintained in case it might be used next. Beyond that, a cache memory system keeps a plurality of these recent blocks, increasing the probability that memory accesses can be avoided.

The boustrophedonic sequence of the present invention exploits the single-retained-block concept when it reverses and handles pixels immediately below one end of the current line. Further, the boustrophedonic sequence exploits cache when it limits rasterization to portions of a particular size. Specifically, two scanlines within a portion should fit in the cache, so throughout the second scanline, benefits might be incurred from cache storage of the first scanline.

There is no constraint on the sequence or number of boundary-defined portions. Although the present description uses the example of vertical portions and a horizontal boustrophedonic pattern, similar principles might extend to horizontal portions, vertical boustrophedonic patterns or even to diagonal portions and patterns. In one embodiment, the length of the strings (e.g. rows, columns, diagonals, etc.) might be each limited to be less than a dimension of the primitive along which the string resides.

FIG. 32is a flowchart showing the process associated with operation2702ofFIG. 27. The instant process is designed to handle a primitive with portions that reside behind the eye. These outlying portions might cause problems in subsequent rasterization operations. To accomplish this, the instant process employs a variable, W that is commonly used for projection i.e., for viewing objects in perspective. The variable W is a number that the other coordinates, X, Y and Z, are divided by in order to make nearby things larger and far things smaller. The variable W is representative of a distance between a center of projection and the corresponding vertex.

As shown inFIG. 32, a primitive is first received that is defined by a plurality of vertices. Each of such vertices includes a W-value. Upon the receipt of the primitive, the set-up module serves to define lines that characterize the primitive based on the vertices. Note operation3200.

The W-values are then analyzed in decision3202. As shown, if one of the W-values is negative, a line equation for a line opposite the vertex having the negative value is flipped in operation3204. In other words, the coefficients of the line equation are multiplied by −1. Further, if two of the W-values are negative, line equations for lines connecting the vertex having a positive W-value and each of the vertexes having negative W-values are flipped in operation3206. If three of the W-values are negative, a cull condition3207occurs where the present invention culls the triangle. Still yet, if none of the W-values are negative, no additional action is taken.

FIGS. 32A–32Cillustrate the manner in which flipping line equations affects which portion of the screen is processed.FIG. 32Ashows the case where none of the W-values are negative and the line equations are left unaltered. As shown, an interior portion of the primitive is filled in such case.

FIG. 32Bshows the case where one of the W-values is negative and which of the line equations is flipped accordingly. As shown, the portion of the primitive opposite the vertex is filled in the present case. In particular, the area to be drawn is bounded by two lines that are co-linear with the two triangle sides sharing the −W vertex, and further bounded by a side of the triangle that shares the two +W vertexes.

FIG. 32Cshows the case where two of the W-values are negative and which of the line equations are flipped accordingly. As shown, the portion of the primitive opposite the vertexes is filled using the methods and/or processes set forth hereinabove with reference toFIGS. 27–32. In other words, the area to be drawn is bounded by two lines that are co-linear with the two triangle sides sharing the +W vertex, and further contiguous to the +W vertex.

The present invention is thus capable of handling all three of the foregoing cases. If part of the triangle is beyond the near and/or far plane, it draws only the portion within those planes. If the triangle has one or two negative Z vertexes, only the correct +Z portion is drawn.

Even if all vertexes are off-screen, and the triangle extends from behind the eye to beyond the far plane, whatever pixels are inside the triangle and on the screen and have Z between the near and far limits. The present invention ensures that little time is wasted exploring bad pixels. This is possible because all clipping, by screen edge or the near or far plane, always results in a convex region on-screen which can be explored easily.

A problem sometimes arises when the starting point is not inside the area to be filled. This can occur if the top vertex is off-screen or is clipped by the near or far plane. In this case, the traversal stage must search for the top point of the drawn region, starting from above. It can do this efficiently by being guided by the signs of the triangle edge slopes and the Z slope. It can test the triangle line equations to discover it is outside the drawn region and why. When it knows what edge(s) and/or Z limit it is outside of, it knows what direction(s) to step that brings it closer to that edge or limit. By moving horizontally in preference to vertically (when there is a choice), searching for the drawn region guarantees it finds the top drawable pixel if there is one. This problem also occurs with external (−W) triangles that open up. In this case, the drawn area extends above all three vertexes.

In one embodiment of the present invention, traversal proceeds from top to bottom of the triangle. The starting point is the top vertex of the triangle if none have a negative W-value and the top vertex is in the scissor rectangle. Otherwise, a point on the top of the scissor rectangle is chosen. Since traversal always begins within the scissor rectangle and never ventures out of it, only the portion of the triangle within the scissor rectangle is ever drawn, even if the area enclosed by the edges extends far beyond the scissor rectangle. In this way, simple scissor rectangle-edge clipping is effected.