Operational amplifier

An operational amplifier for canceling an offset and continuously generating an output signal. The operational amplifier includes a first operational amplification unit and a second operational amplification unit each having at least one electrical characteristic that is substantially the same as one another. One of the operational amplification units performs a canceling operation (holding operation and compensation operation) of the offset voltage while the other operational amplification unit performs a non-canceling operation and generates the output voltage by amplifying an input voltage. Both operational amplification units alternately perform the canceling operation and the non-canceling operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-039290, filed on Feb. 16, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to an operational amplifier, and more particularly, to an operational amplifier for canceling an offset from an output signal.

In recent years, an LSI incorporates a large number of operational amplifiers. An operational amplifier is a basic circuit mounted on an LSI. However, the output signal of the operational amplifier contains errors caused by characteristic variations in the transistors configuring the operational amplifier. Therefore, errors must be cancelled from the output signal through a simple method. Further, an output signal of the operational amplifier is used to monitor the output signal at any given point of time. Thus, an operational amplifier is required to continuously generate an output signal.

In the prior art, many operational amplifiers are used to amplify analog signals or amplify differential signals. However, since the output signal of an operational amplifier contains errors, the output signal is not 0 V even if an input signal is 0 V. Such an error in the output signal with respect to the input signal is referred to as an offset voltage. InFIG. 1, the offset voltage is represented by a voltage source2, which is connected to an input terminal of the operational amplifier1.

The output voltage Vo of the operational amplifier1, which is determined by an input voltage Vin, an input resistance R1, and a feedback resistance R2, is obtained from the equation shown below.
Vo=(1+R2/R2)×Vin

However, the offset voltage e1, which corresponds to the voltage source2shown inFIG. 1, is actually superimposed on the input voltage Vin. The output voltage Vo is thus obtained from the equation shown below using the offset voltage e1.
Vo=(1+R2/R2)×(Vin−e1)

In other words, the offset voltage e1is amplified together with the input voltage Vin. The offset voltage e1contained in the output voltage Vo is thus large when the input voltage Vin is small.

To cancel the offset voltage of the operational amplifier, the area of the elements configuring the operational amplifier may be increased. When the element area is increased by two times, this method generally reduces the output error (offset) to the square root of ½. However, elements with large areas are needed to minimize the offset. This increases costs.

A method proposed to cancel the offset voltage of the operational amplifier without having to increase element area includes short-circuiting the two input terminals of the operational amplifier, holding the output voltage of the operational amplifier as the offset voltage, and feeding back the held voltage to the operational amplifier.

For example, Japanese Laid-Open Patent Publication No. 8-18353 discloses an operational amplifier including a main amplifier, an auxiliary amplifier, and a holding means. The auxiliary amplifier receives the output signal of the main amplifier and operationally amplifies the output signal in a reverse direction of the main amplifier. The holding means holds the output signal of the auxiliary amplifier and feeds back the held voltage to the main amplifier. The operational amplifier reduces the offset error of the main amplifier to an inverse of the gain of the main amplifier.

Japanese Laid-Open Patent Publication No. 2001-292041 discloses another example of an operational amplifier. The operational amplifier accumulates voltage, which is amplified by an operational amplification circuit and contains an offset, in a capacitor. The voltage value of the operational amplifier is feedback controlled based on the accumulated voltage.

SUMMARY OF THE INVENTION

The output signal of the operational amplifier is an analog signal. An analog signal is normally used to monitor the analog signal at a given point of time. The operational amplifier is thus required to continuously generate the output signal. However, the operational amplifier disclosed in each of the above publications cancel the offset by holding or accumulating the offset voltage and feeding back the held or accumulated offset voltage to the operational amplifier. That is, the operation of holding or accumulating the offset voltage and the operation of canceling the offset are alternately repeated. The output signal thus becomes non-continuous with respect to the input signal. Such an output signal cannot be used for the above application.

The present invention provides an operational amplifier for canceling the offset of the output signal while maintaining continuity of the output signal.

One aspect of the present invention is an operational amplifier for generating an output voltage by amplifying an input voltage. The operational amplifier includes a first capacitor. A first operational amplification unit connected to the first capacitor has a first offset voltage. The first operational amplification unit accumulates charge corresponding to the first offset voltage in the first capacitor and alternately performs a canceling operation, for canceling the first offset voltage with the charge accumulated in the first capacitor, and a non-canceling operation, for generating a first output voltage by amplifying the input voltage. The operational amplifier further includes a second capacitor. A second operational amplification unit connected to the second capacitor has substantially the same electrical characteristic as the first operational amplification unit. The second operational amplification unit also has a second offset voltage. The second operational amplification unit accumulates charge corresponding to the second offset voltage in the second capacitor and alternately performs a canceling operation, for canceling the second offset voltage with the charge accumulated in the second capacitor, and a non-canceling operation, for generating a second output voltage by amplifying the input voltage. An output selection circuit, connected to the first and second operational amplification units, alternately selects the first output voltage and the second output voltage as the output voltage of the operational amplifier. The second operational amplification unit performs the non-canceling operation when the first operational amplification unit is performing the canceling operation, and the second operational amplification unit performs the canceling operation when the first operational amplification unit is performing the non-canceling operation.

Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating via example the principles of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The operational amplifier10according to a first embodiment of the present invention will now be described with reference to the drawings.

As shown inFIG. 2, the operational amplifier10includes a first operational amplification unit11aand a second operational amplification unit11b.The first operational amplification unit11aand the second operational amplification unit11bhave substantially the same electrical characteristic, and each of the operational amplification units11aand11breceives the same input voltage Vin. Specifically, a non-inverting input terminal of the first operational amplification unit11ais connected to a non-inverting input terminal of the second operational amplification unit11b,and an inverting input terminal of the first operational amplification unit11ais connected to an inverting input terminal of the second operational amplification unit11b.The input voltage Vin is supplied to the inverting input terminals and the non-inverting input terminals of the two operational amplification units11a,11b.The first operational amplification unit11aand the second operational amplification unit11bamplify the input voltage Vin and respectively generate output voltages Voa and Vob.

First and second capacitors C1aand C1b,which cancel offsets, are respectively connected to the first operational amplification unit11aand the second operational amplification unit11b.The first operational amplification unit11aaccumulates charge, which corresponds to its offset voltage Voff1(first offset voltage), in the capacitor C1aand cancels the offset of the output voltage Voa with the charge accumulated in the capacitor C1a.Similarly, the second operational amplification unit11baccumulates charge, which corresponds to its own offset voltage Voff2(second offset voltage), in the capacitor C1band cancels the offset of the output voltage Vob with the charge accumulated in the capacitor C1b.That is, the first operational amplification unit11aand the second operational amplification unit11brespectively perform holding operations for holding the offset voltages Voff1and Voff2in the capacitors C1aand C1b.Then, the first operational amplification unit11aand the second operational amplification unit11brespectively perform compensation operations for generating the output voltages Voa and Vob by canceling the offset with the offset voltages Voff1and Voff2held in the capacitors C1aand C1b.

A control signal SC is provided to the first operational amplification unit11afrom an external device100. An inverted control signal SCX, which is generated by inverting the control signal SC with an inverter circuit12, is provided to the second operational amplification unit11b.The first operational amplification unit11aperforms a canceling operation, which includes the holding operation and the compensation operation, when the control signal SC has a first level (e.g., an L level). Further, the first operational amplification unit11aperforms a non-canceling operation to generate the output voltage Voa (output voltage Vout of the operational amplifier10) when the control signal SC has a second level (e.g., an H level). Similarly, the second operational amplification unit11bperforms a canceling operation, which includes the holding operation and the compensation operation, when the inverted control signal SCX has a first level (e.g., an L level). The second operational amplification unit11bperforms a non-canceling operation to generate the output voltage Vob (output voltage Vout of operational amplifier10) when the inverted control signal SCX has a second level (e.g., H level).

The inverted control signal SCX is generated by inverting the logic of the control signal SC. Therefore, if the control signal SC has an H level, the inverted control signal SCX is set to an L level, and vice versa. That is, the inverted control signal SCX and the control signal SC are complementary signals. The first operational amplification unit11aand the second operational amplification unit11bthus operate complementary to each other. When the first operational amplification unit11aperforms the canceling operation (holding operation and compensation operation), the second operational amplification unit11bperforms the non-canceling operation (generation of output voltage Vout). When the second operational amplification unit11bperforms the canceling operation (holding operation and compensation operation), the first operational amplification unit11aperforms the non-canceling operation (generation of output voltage Vout).

An output terminal of the first operational amplification unit11aand an output terminal of the second operational amplification unit11bare connected to a switch SW1, which functions as an output selection circuit. The switch SW1includes a common terminal, a first switching terminal, and a second switching terminal. The first switching terminal is connected to the output terminal of the first operational amplification unit11a,and the second switching terminal is connected to the output terminal of the second operational amplification unit11b. The switch SW1connects the common terminal to either the first switching terminal or the second switching terminal in response to the control signal SC. In the first embodiment, the switch SW1connects the common terminal to the second switching terminal when the control signal SC has an L level and connects the common terminal to the first switching terminal when the control signal SC has an H level. Therefore, the common terminal is selectively connected to the output terminal of the first operational amplification unit11aand the output terminal and of the second operational amplification unit11b. Consequently, the operational amplifier10selects either the output voltage Voa of the first operational amplification unit11aor the output voltage Vob of the second operational amplification unit11bas the output voltage Vout. Accordingly, the output voltage Vout is continuously output.

In the above description andFIG. 2, the switch SW1is a so-called make before break (MBB) switch in which the common terminal connects to both the first and second switching terminals during switching. The MBB switch continuously generates the output voltage Vout even when the connection of the switch SW is being switched.

The configuration of the first operational amplification unit11awill now be described.

As shown inFIG. 4, the first operational amplification unit11aincludes an operational amplification circuit21, an offset adjustment circuit22, and an output circuit23.

The operational amplification circuit21includes a first differential input circuit31, a current mirror circuit32, and a constant current source33. The first differential input circuit31is formed by two transistors Q1and Q2. The two transistors Q1and Q2are each configured by an N-channel MOS transistor. The sources of the two transistors Q1and Q2are connected to each other and to a low potential power supply (e.g., ground GND) via the constant current source33.

The gate of the first transistor Q1is connected to a first switch SWa. The first switch SWa includes a common terminal, a first terminal, and a second terminal. The common terminal is connected to the gate of the transistor Q1. The first terminal is connected to the non-inverting input terminal (indicated as “+” inFIG. 4) of the first operational amplification unit11avia a resistor R1a.The second terminal is connected to the inverting input terminal (indicated as “−” inFIG. 4) of the first operational amplification unit11avia a resistor R1b.Specifically, the first terminal of the resistor R1ais connected to the first terminal of the first switch SWa, and the second terminal of the resistor R1ais connected to the non-inverting input terminal of the operational amplification unit11a.Further, the first terminal of the resistor R1bis connected to the second terminal of the first switch SWa, and the second terminal of the resistor R1bis connected to the inverting input terminal of the operational amplification unit11a. The resistors R1aand R1bhave substantially the same resistance in the first embodiment. The first switch SWa is controlled so that the common terminal connects to the second terminal during the holding operation for holding the offset voltage Voff1of the first operational amplification unit11a.The first switch SWa is further controlled so that the common terminal connects to the first terminal during the compensation operation for canceling the offset voltage Voff1of the first operational amplification unit11a.

The gate of the second transistor Q2is connected to the first terminal of the resistor R1bvia a voltage source Vf1. The voltage source Vf1, which represents the offset voltage in the operational amplification circuit21, is actually not connected to the gate of the second transistor Q2.

The current mirror circuit32is formed by two transistors Q3and Q4. The two transistors Q3and Q4are each configured by a P-channel MOS transistor. The drains of the two transistors Q3and Q4are respectively connected to the drains of the transistors Q1and Q2. The sources of the two transistors Q3and Q4are connected to a high potential power supply Vdd. The gates of the transistors Q3and Q4are connected to each other. The gate of the transistor Q3is also connected to the drain of the transistor Q3. Further, the drains of transistors Q3and Q4are connected to the offset adjustment circuit22.

The offset adjustment circuit22includes a second differential input circuit41and a constant current source42. The second differential input circuit41and the constant current source42are connected in parallel to the first differential input circuit31and the constant current source33of the operational amplification circuit21. Specifically, the second differential input circuit41is formed by two transistors Q5and Q6. The two transistors Q5and Q6are each configured by an N-channel MOS transistor. The sources of the two transistors Q5and Q6are connected to each other and to a low potential power supply (e.g., ground GND) via the constant current source42. The gate of the fifth transistor Q5is connected to the non-inverting input terminal of the first operational amplification unit11avia a second switch SWb and the resistor R1a.The gate of the sixth transistor Q6is connected to the inverting input terminal of the first operational amplification unit11avia a voltage source Vf2, a third switch SWc, and the resistor R1b.The voltage source Vf2, which represents the offset voltage in the offset adjustment circuit22, is actually not connected to the gate of the sixth transistor Q6. The voltage source Vf2has substantially the same voltage value as the voltage source Vf1.

The drains of the two transistors Q5and Q6are connected to the current mirror circuit32. Specifically, the drain of the transistor Q5is connected to the drain of the transistor Q3, and the drain of the transistor Q6is connected to the drain of the transistor Q4. The capacitor C1a,which functions as a holding means, is connected between the gate of the fifth transistor Q5and the gate of the sixth transistor Q6. Specifically, the first terminal of the capacitor C1ais connected to a node between the gate of the fifth transistor Q5and the second switch SWb, and the second terminal of the capacitor C1ais connected to a node between the voltage source Vf2(actually, the gate of sixth transistor Q6) and the third switch SWc.

The second switch SWb and the third switch SWc are each activated during the holding operation for holding the offset voltage Voff1of the first operational amplification unit11awith the capacitor C1a.Further, the second switch SWb and the third switch SWc are each inactivated during the compensation operation for canceling the offset voltage Voff1of the first operational amplification unit11a.

A node between the fourth transistor Q4and the second transistor Q2is connected to the gate of the transistor Q7, which forms the output circuit23. The transistor Q7, which is configured by a P-channel MOS transistor, includes a source connected to the high potential power supply Vdd and a drain connected to the low potential power supply (e.g., ground GND) via a constant current source51. A capacitor C2, which prevents oscillation, is connected between the gate and drain of the transistor Q7.

The gate of a transistor Q8, which forms a feedback resistor, is connected to a node between the transistor Q7and the constant current source51. The transistor Q8, which is configured by an N-channel MOS transistor, includes a source connected to the low potential power supply (e.g., ground GND) via a resistor R2and a drain connected to the first terminal of the resistor R1a.

A node between the transistor Q8and the resistor R2functions as an output terminal of the first operational amplification unit11a. The output terminal is connected to a load resistor R3(not shown inFIG. 2) and to a capacitor C3(not shown inFIG. 2), which holds an output, via the switch SW1.

The operation of the first operational amplification unit11awill now be discussed.

[Holding Operation for Holding Offset Voltage]

The common terminal of the first switch SWa is connected to the second terminal. This short-circuits the gates of the first transistor Q1and second transistor Q2, that is, the input terminals of the operational amplification circuit21are short-circuited. The second switch SWb is activated, and the gate of the fifth transistor Q5, that is, the first terminal of the capacitor C1a,is connected to the first terminal of the resistor R1avia the second switch SWb. Further, the third switch SWc is activated, and the gate of the sixth transistor Q6, that is, the second terminal of the capacitor C1a,is connected to the first terminal of the resistor R1b.

When the switches SWa to SWc are connected as described above, the gate voltage of the second transistor Q2becomes greater than the gate voltage of the first transistor Q1by the offset voltage by the voltage source Vf1. The current I1that flows between the operational amplification circuit21and the output circuit23is expressed by the following equation of the difference between the current Id1that flows to the first transistor Q1and the current Id2that flows to the second transistor Q2.
I1=Id1−Id2

The gate of the first transistor Q1and the gate of the second transistor Q2are short-circuited via the first switch SWa. Therefore, the current I1is expressed by the following equation of the product of a mutual conductance gm1of the operational amplification circuit21and the voltage source Vf1(offset voltage in the operational amplification circuit21).
I1=gm1×Vf1=Id1−Id2

The first terminal of the resistor R1ais connected to the output terminal of the first operational amplification unit11avia the transistor Q8. Thus, a potential difference is created between the first terminals of the resistors R1aand R1bdue to the offset voltage (voltage source Vf1). If the potential difference is V2, the gate voltage of the sixth transistor Q6becomes greater than the gate voltage of the fifth transistor Q5by the sum of the potential difference V2and the offset voltage Vf2. The current I2that flows between the offset adjustment circuit22and the output circuit23is expressed by the following equation of the difference between the current Id5, which flows to the fifth transistor Q5, and the current Id6, which flows to the sixth transistor Q6.
I2=Id5−Id6

Current I2is expressed by the equation shown below using the mutual conductance gm2of the offset adjustment circuit22, the voltage source Vf2(offset voltage in the offset adjustment circuit22), and the potential difference V2.
I2=gm2×(V2+Vf2)=Id5−Id6

The operational amplification circuit21and the offset adjustment circuit22are connected in parallel. Thus, charge is accumulated in the capacitor C1aso that the currents I1and I2become the same. That is, charge is accumulated in the capacitor C1aso that the potential difference between the two electrodes becomes equal to the offset voltage at the operational amplification circuit21and the offset adjustment circuit22.

FIG. 5is an equivalent circuit of the first operational amplification unit11aduring offset adjustment. In the equivalent circuit, an operational amplifier13is ideal and does not contain an offset voltage. The voltage source Vf1produces the offset voltage Voff1of the first operational amplification unit11a. InFIG. 5, the output voltage Voa is expressed by the equation shown below when R1a=R1b=R1is satisfied.
Voa=(1+(R2/R1))×(Vin−Vf1)

InFIG. 5, the capacitor C1aincludes two electrodes. The voltage at the first electrode of the capacitor C1a,which is connected to the non-inverting input terminal, is greater than the voltage at the inverting input terminal by the input voltage Vin. Further, the voltage at the second electrode of the capacitor C1ais obtained by dividing the output voltage Voa of the first operational amplification unit11aand the voltage at the inverting input terminal with the input resistor R1(R1a,R1b) and the feedback resistor R2. Thus, the voltage Vc1at the second electrode of the capacitor C1ais expressed by the equation shown below.
Vc1=(R1/(R1+R2))×Voa=Vin−Vf1

As described above, the voltage at the first electrode of the capacitor C1ais greater than the voltage at the inverting input terminal by the input voltage Vin. Therefore, the potential difference between the electrodes of the capacitor C1abecomes equal to the offset voltage (voltage source Vf1). That is, the capacitor C1ais charged to become equal to the offset voltage (voltage source Vf1) of the first operational amplification unit11a.

[Compensation Operation for Canceling Offset Voltage]

When the first operational amplification unit11ashown inFIG. 4performs the compensation operation, that is, when the offset voltage Voff1of the first operational amplification unit11ais canceled by the offset adjustment circuit22, the gate of the first transistor Q1is connected to the non-inverting input terminal via the resistor R1aby the first switch SWa. Further, the second switch SWb and the third switch SWc are both inactivated.

As a result, the first operational amplification unit11ashown inFIG. 4becomes as shown by the equivalent circuit ofFIG. 6. In the equivalent circuit, the capacitor C1ais connected in series to the voltage source Vf1. Charge having a potential difference in the reverse direction of the voltage of the voltage source Vf1(i.e., offset voltage) is accumulated in the capacitor C1a.Therefore, the offset voltage Voff1of the first operational amplification unit11ais canceled by the potential difference produced by the charge accumulated in the capacitor C1a,and the input voltage Vin is supplied to the operational amplifier13.

The operational amplifier10of the first embodiment includes the first operational amplification unit11a,which functions as channel1(ch1), and the second operational amplification unit11b, which functions as channel2(ch2). As shown inFIG. 3, channels ch1and ch2operate alternately. The second operational amplification unit11bhas the same configuration as the first operational amplification unit11aand thus will not be described.

InFig. 3, the first switch SWa connects the gates of the first transistor Q1and the second transistor Q2shown inFIG. 4when a SWa switching control signal has an L level. Further, the first switch SWa disconnects the gates of the first transistor Q1and the second transistor Q2when the SWa switching control signal has an H level. The second switch SWb and the third switch SWc are both inactivated when a SWb switching control signal has an L level and a SWc switching control signal has an L level. Further, the second switch SWb and the third switch SWc are both activated when the SWb switching control signal has an H level and the SWc switching control signal has an H level. The SWa switching control signal, the SWb switching control signal, and the SWc switching control signal are each generated based on the control signal SC.

InFIG. 3, the first operational amplification unit11a(ch1) performs the canceling operation and the second operational amplification unit11b(ch2) performs the non-canceling operation during a first period T1in which the control signal SC is set to an L level. The output voltage Vob generated by amplifying the input voltage Vin with ch2is selected as the output voltage Vout of the operational amplifier10. Simultaneously, switching is controlled for each switch SWa to SWc during the first period T1. Therefore, ch1sequentially performs the holding operation for amplifying its offset voltage Voff1and accumulating charge, which corresponds to the amplified voltage, in the capacitor C1aand the compensation operation for canceling the offset voltage Voff1with the charge accumulated in the capacitor C1aduring the holding operation. In this state, ch2generates the output voltage Vob that does not contain offset. The output voltage Vob is selected by the switch Sw1and output from the operational amplifier10.

Then, during a second period T2in which the control signal SC having an H level is provided, ch1performs the non-canceling operation, and the output voltage Voa generated by amplifying the input voltage Vin with ch1is selected as the output voltage Vout of the operational amplifier10. In the meanwhile, ch2performs the canceling operation.

Therefore, ch1and ch2alternately repeat the canceling operation and the non-canceling operation in a complementary manner in accordance with the control signal SC. That is, when one of the operational amplification circuits performs the canceling operation, the other one of the operational amplification circuit performs the non-canceling operation and generates the output voltage Vout (output voltage Voa or output voltage Vob). The operational amplifier10thus continuously generates the output voltage Vout that does not contain an offset.

As shown inFIG. 3, the switching from the canceling operation to the non-canceling operation is performed after a predetermined time elapses from when the first SWa switches the holding operation to the compensation operation during the canceling operation. The predetermined time is set to wait until the output voltage Vout (Voa or Vob) reaches the desirable voltage after the operation of each channel is changed to the compensation operation. That is, in the channel performing the holding operation, the input terminals of the operational amplification circuit21shown inFIG. 4are short-circuited, and the output voltage of the channel has a value obtained by amplifying the offset voltage. Therefore, after the operation state is switched from the holding operation to the compensation operation, the output voltage of the channel does not immediately reach the desired voltage. Thus, the output voltage Vout would not be continuous if it were switched to the non-canceling operation immediately after switching the operation of the channel to the compensation operation.

The operational amplifier10of the first embodiment has the advantages described below.

(1) The operational amplifier10includes a first operational amplification unit11aand a second operational amplification unit11bhaving substantially the same electrical characteristic. One of the operational amplification units (channels) performs a canceling operation (holding operation and compensation operation) on the offset voltage while the other one of the operational amplification units performs the non-canceling operation and generates the output voltage Vout (Voa or Vob). Both operational amplification units11aand11balternately perform the canceling operation and the non-canceling operation. Consequently, the offset voltages Voff1and Voff2of the operational amplification units11aand11bare cancelled and the output voltage Vout is continuously generated.

(2) The gates of the two transistors Q1and Q2, which form the differential input circuit31of the operational amplification circuit21, are short-circuited by the first switch SWa. Thus, the offset voltage Voff1contained in the output voltage (i.e., output voltage of the operational amplification unit11a) of the operational amplification circuit21is held by the capacitor C1aconnected between the gates of two transistors Q5and Q6, which form the differential input circuit41of the offset adjustment circuit22. The potential difference based on the held offset voltage Voff1is produced between the gates of the two transistors Q5and Q6. As a result, voltage having a potential difference in the reverse direction of the offset voltage Voff1is held by the capacitor C1a.The offset voltage is canceled irrespective of the gain of the operational amplifier10. Thus, the operational amplifier10may be set to have any gain.

(3) The first operational amplification unit11aand the second operational amplification unit11balternately perform the non-canceling operation. Thus, the capacitance of the capacitor C3, which holds the output and is arranged in the operational amplification units11aand11b, may be reduced. Alternatively, the capacitor C3may be omitted. Thus, the area occupied by the capacitor C3may be minimized and the area of the operational amplifier10does not have to be increased. This consequently reduces cost of the operational amplifier10.

(4) The capacitor C1of the operational amplification unit11ais separated from the inverting input terminal and the non-inverting input terminal by the second switch SW2and the third switch SW3in the compensation operation. Thus, the gate voltages of the fifth transistor Q5and the sixth transistor Q6forming the offset adjustment circuit22are not affected by the input voltage Vin. This prevents the input voltage Vin from fluctuating the gate voltages of the fifth transistor Q5and the sixth transistor Q6.

An operational amplifier60according to a second embodiment of the present invention will now be described with reference toFIG. 7.

As shown inFIG. 7, the operational amplifier60includes first and second operational amplification units61aand61b. The first operational amplification unit61aand the second operational amplification unit61bare configured by the same circuit elements as the operational amplification units11aand11bof the first embodiment shown inFIG. 2except for the resistors R1a,R1b,R2(seeFIG. 4).

The first operational amplification unit61aand the second operational amplification unit61bare connected in parallel to the input voltage Vin. Specifically, the non-inverting input terminal of the first operational amplification unit61ais connected to the first terminal of the resistor R11. The inverting input terminal of the first operational amplification unit61ais connected to the first terminal of each of resistors R12aand R12bvia a first switch SW11, which functions as an input selection circuit. The second terminals of the resistors R12aand R12bare short-circuited with each other, and the input voltage Vin is supplied between the second terminal of the resistor R11and the second terminals of the two resistors R12aand R12b.The first switch SW11switches the input resistor that is connected to the inverting input terminals of the first and second operational amplification units61aand61bbetween the resistor R12aand the resistor R12bin a complementary manner based on the control signal SC. Specifically, the first switch SW11connects the resistor R12ato the first operational amplification unit61aand the resistor R12bto the second operational amplification unit61bwhen the control signal SC has an H level. The first switch SW11connects the resistor R12ato the second operational amplification unit61band the resistor R12bto the first operational amplification unit61awhen the control signal SC has an L level.

The capacitor C1ais connected to the first operational amplification unit61ato hold the offset voltage Voff1of to the operational amplification unit61a. The capacitor C1bis connected to the second operational amplification unit61bto hold the offset voltage Voff2of the operational amplification unit61b.

The output terminals of the first and second operational amplification units61aand61bare connected to a second switch SW12, which functions as an output selection circuit. Feedback resistors R2aand R2bare connected to the second switch SW12. In the same manner as the first switch SW11, the second switch SW12switches the feedback resistor that is connected to the output terminal of each of the first and second operational amplification units61aand61bbetween the resistor R2aand the resistor R2bbased on the control signal SC. Specifically, the second switch SW12connects the first operational amplification unit61ato a resistor R2aand the second operational amplification unit61bto a resistor R2bwhen the control signal SC has an H level. The second switch SW12connects the first operational amplification unit61ato the resistor R2band the second operational amplification unit61bto the resistor R2awhen the control signal SC has an L level.

In the same manner as the switch SW1in the first embodiment, the first switch SW11and the second switch SW12are both make before break (MBB) switches.

A node between the second switch SW12and the resistor R2ais connected to ground via the resistor R3and the capacitor C3. The output voltage Vout is output from a node between the resistor R3and the capacitor C3.

In the operational amplifier60, the first operational amplification unit61aand the second operational amplification unit61beach perform the holding operation for holding charge corresponding to each of the offset voltages Voff1and Voff2with the associated capacitors C1aand C1b.Further, the first operational amplification unit61aand the second operational amplification unit61beach perform a compensation operation for canceling the offset voltages Voff1and Voff2of each operational amplification unit61aand61bwith the charge held by the associated capacitors C1aand C1b.In the same manner as the first embodiment, the first operational amplification unit61aand the second operational amplification unit61balternately perform the canceling operation, which includes the holding operation and the compensation operation, and the non-canceling operation, which generates the output voltage (Voa or Vob) by amplifying the input voltage Vin in response to the control signal SC.

The first operational amplification unit61aand the second operational amplification unit61buse the same input resistor and feedback resistor during the canceling operation and the non-canceling operation. More specifically, the inverting input terminals of the first operational amplification unit61aand the second operational amplification unit61bare connected to the resistor R12bduring the canceling operation and to the resistor R12aduring the non-canceling operation. In the same manner, the output terminals of the first operational amplification unit61aand the second operational amplification unit61bare connected to the resistor R2bduring the canceling operation and to the resistor R2aduring the non-canceling operation.

The first operational amplification unit61aand the second operational amplification unit61brespectively generate the output voltages Voa and Vob of substantially the same voltage by amplifying the input voltage Vin by an gain, which is determined by the resistances of the resistors R11, R12a,and R2a,during the non-canceling operation. That is, the gain of the first operational amplification unit61aand the second operational amplification unit61bare set to be substantially the same.

In the non-canceling operation, if the resistors connected to both of the first operational amplification unit61aand the second operational amplification unit61bhave different resistances, the resistances must be equalized. Therefore, highly accurate resistors become necessary. This is because different gains of the operational amplification units61aand61bdiffer the output voltages Voa and Vob and cause the output voltage Vout to become non-continuous.

Comparatively, in the second embodiment, the first operational amplification unit61aand the second operational amplification unit61beach have the same resistance during the non-canceling operation. Thus, the first and second operational amplification units61aand61bgenerate the output voltages Voa and Vob having substantially the same voltage values. Consequently, the output voltage Vout is continuously generated without using a highly accurate resistor. This lowers the cost of the resistors and lowers the cost of the operational amplifier.

In the canceling operation, the inverting input terminals of the operational amplification units61aand61bare connected to the resistor R12bby the first switch SW11, and the output terminals of the operational amplification units61aand61bare connected to the resistor R2bby the second switch SW12. The operational amplification units61aand61bdo not generate the output voltage during the canceling operation. Thus, the resistors R12band R2bdo not have to be highly accurate. Thus, the resistors R12b,R2bmay be reduced in size compared with the resistors R12aand R2a.This-suppresses increase in the area of the operational amplifier60.

In addition to the advantages of the first embodiment, the operational amplifier60of the second embodiment has the advantages described below.

The operational amplifier60includes a first operational amplification unit61aand a second operational amplification unit61bhaving substantially the same electrical characteristic. The resistors (input resistor, feedback resistor) connected to the two operational amplification units61aand61bare commonly used for the canceling operation and the non-canceling operation. Consequently, the gains of the first operational amplification unit61aand the second operational amplification unit61bare set to be substantially same. Therefore, the output voltage Vout is continuously generated without using a resistor controlled to have a highly accurate resistance.

In the first and second embodiments, each switch SW1and SW2may be a so-called break before make (BBM) switch in which a common terminal is not connect to the first and second switching terminal when a connection is switched. This is because the first operational amplification unit11aand the second operational amplification unit11b(or61aand61b) generate the output voltages Voa and Vob at substantially the same level, and the output voltage Vout is held by the voltage holding capacitor C3during the short period in which the switches SW1and SW2are switched. Thus, the output voltage Vout is continuously generated even if the BBM switch is used.

In the first and second embodiments, the operational amplifiers10and60is not limited to the two operational amplification units11aand11b(the operational amplification units61aand61bin the second embodiment) and may include three or more operational amplification circuits.

In the second embodiment, the first and second operational amplification units61aand61bmay commonly use only the input resistors R11, R12a,and R12b.Further, the first and second operational amplification units61aand61bmay commonly use only the feedback resistors R2aand R2b.