Fibrous laminate interface for security coatings

An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

BACKGROUND

The use of barrier coatings on microelectronic integrated circuits (ICs) and in printed wiring assemblies is challenged by the finer feature size that is the result of advancing circuit design technology. In general, barrier coatings are expected to offer some functionality for security, thermal management, physical protection, electrical isolation, electromagnetic impulse protection, and environmental isolation. However, high density circuitry in ICs and circuit card assemblies (CCAs) include fine metallization lines and stacked, fine-pitch interconnect. These fine metallization lines and stacked fine-pitch interconnects make it difficult to enabling coating applications and for meeting performance requirements of the coated hardware. Finer circuit features are more vulnerable to the mechanical stresses imposed by the coating during the applied coating cure, qualification testing, and throughout the operational life of the coated hardware. Moreover, full encapsulation of the finer circuit interconnect features are hampered by flow restrictions of the applied coating and filler through the fine pitch of wirebonds and similar interconnect features. The electronics systems industry, in particular, needs synergistic security enhancements built into the material advancements that can be used to solve the problems of coating applications in high density, fine-featured, circuit architecture.

SUMMARY

The above-mentioned problems of current systems are addressed by embodiments of the present invention and will be understood by reading and studying the following specification. The following summary is made by way of example and not by way of limitation. It is merely provided to aid the reader in understanding some of the aspects of the invention.

In one embodiment, an integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

DETAILED DESCRIPTION

Embodiments of the present invention include a fibrous coating interface layer that is embedded into a bond coat layer prior to fully curing the bond coat. In some embodiments, surface features of fibrous coating interface are embedded in the bond coat. The embedded fibrous coating interface layer provides security by preventing reverse engineering by simply separating the coating layers. Some embodiments also include an optional perimeter seal that enhances security and the performance of the barrier coating while reducing the risk of mechanical damage imposed by the coating on the circuitry throughout the life cycle of the coated hardware. The embedded fibrous coating layer also restricts the amount of mechanical stress imposed by the bond coat layer by the formation of a composite formulation that strengthens the bond coat, and alters the stress induced by differences in the coefficient of thermal expansion of the applied coating layers and the application specific integrated circuit (ASIC) substrate. Although, the application discusses ASIC the present invention can be applied to any type of integrated circuit (IC) or even discrete devices.

FIG. 1illustrates a top view of an integrated circuit (IC) package100of one embodiment. In this example, the IC package100is an advanced ceramic package100with a complex ASIC architecture. The IC package100includes a wire frame102and a ceramic substrate104formed thereon. The substrate104includes sidewalls106that form a cavity207in which IC devices are formed. The IC devices includes memory devices112,110, processor108and discrete devices114and116such as diodes and capacitors.

FIGS. 2A through 2Dillustrate the formation of security coatings of one embodiment on an ASIC package (or assembly) is illustrated. In particular,FIG. 2Aillustrated a substrate204having a sidewalls205that form a cavity207. The IC devices in this example, include processors208, memory devices206and discrete devices210. Also illustrated inFIG. 2Ais connects212. The IC devices are protected by the security coatings of the present invention.FIG. 2Billustrates the formation of a pre-coat214(or bond coat214). In one embodiment, the bond coat214is a high-flow layer applied to the surface of the ASIC assembly. The particle size of the filler and rheology of the bond coat214are designed to enable free-flow to encapsulate the features of the ASIC assembly while maintaining continuity of the filler dispersion to maintain the final properties of the bond coat214that are critical to successful performance of the coated hardware.

The bond coat214is applied to the full area (or a portion thereof) of the surface of the packaged ASIC assembly. In one embodiment, the bond coat214is applied to a point where the highest component (or device) in the packaged assembly is beneath about 20 mils of the bond coat214formulation (The 20 mil height is nominal in good practice for coatings in sealed packages). The bond coat layer214is comprised of adhesive resin and filler that forms a layer that has relatively high strength, is thermally conductive, is electrically insulating and is chemically resistant. The bond coat layer is further a thermoset adhesive. Moreover, the bond coat layer214also has an application viscosity which allows for uniform coating and the ability to embed the fibrous layer216.FIG. 3is a top view illustrating the bond coat layer214.

FIG. 2Cillustrates the formation of the fibrous coating embedded interface layer216. The fibrous layer216(or fibrous interface216) is a planer layer that is embedded into the bond coat layer214prior to fully curing the bond coat214. The embedded fibrous layer216restricts the amount of mechanical stress imposed by the bond coat layer by the formation of a composite formulation that strengthens the bond coat214, and alters the stress induced by differences in the coefficient of thermal expansion of the applied coating layers and the ASIC substrate204. The fibrous interface216is a lightweight, high strength weaved material with high chemical resistance. Fibrous materials which may be considered include, but are not limited to, aramid, silicon carbide, fiberglass, or carbon fiber.

In one embodiment of the present invention, the fibrous layer216is embedded in a plurality of support substrates. Moreover, in embodiments of the present invention the fibrous layer is embedded with woven polymer fiber, ceramic, metal or metal alloy in a predetermined distribution pattern. Still further in another embodiment, a layer is added to the fibrous interface that includes at least one of woven polymer fiber, optical fiber, ceramic, metal or metal alloy in a predetermined distribution pattern. Moreover, the fibrous layer (or pad)216is in one embodiment a standalone fibrous pad216. In another embodiment, the fibrous layer216is configured with a substrate wherein the fibrous pad can be embedded within the substrate, attached to the substrate. In still another embodiment, the substrate and fibrous pad216are integrated with an optical fiber sensor that provides an active sensor. Any of these configurations in the above embodiments including the fibrous layer216may be termed generally as the top-coat216. An example of a top view of an ASIC package illustrating the top-coat216is illustrated inFIG. 4.

For a security barrier, in one embodiment, a perimeter seal ring220is deposed around the edge of the border of the fibrous pad216or top-coat216. This is illustrated inFIG. 2D. This perimeter ring220permits curing at significantly higher temperature to enhance the resistance of the edge of the coated ASIC to attack (for reverse engineering). This is generally termed a deep-seal process. The optional perimeter seal220embodiment further enhances the performance of the barrier coating while reducing the risk of mechanical damage imposed by the coating on the circuitry throughout the life cycle of the coated hardware. A top view of the ASIC illustrating the seal ring220is illustrated inFIG. 5. In one embodiment, the perimeter seal ring220is comprised of a thermoset polymer that is cured with a heat source. In one embodiment, the heat source is from a line of sight heat gun. In another embodiment, a mask is used to shield the heat used to cure the perimeter seal from other areas of the ASIC package.

Layers that form a top-coat600of one embodiment are illustrated inFIG. 6. In this embodiment, the top coat600includes a fibrous pad (interface)602. In one embodiment, an optional porous fibrous (perforated hardcoat)604is used to allow for vacuum impregnation of the bond coat into a fibrous array (prior to cure) of the fibrous pad602. In this embodiment, the bond coat material may be applied to the top of the perforated hardcoat604to enhance filling of the pores after vacuum impregnation. The next layer is an optional seal ring606such as the seal ring220. The top-coat600will vary in thickness with respect to its application and functionality. For packaged ASIC applications, the top-coat600may need to be thin (e.g. nominal 10-60 mils) to permit the lid application and seal operations for the hermetic ASIC package. Handling difficulties with such thin top-coats600are addressed by another layer termed the handling layer. The handling layer is comprised of a mildly adherent release film608and bulk block of material (structure-weighted application cap)610that can be configured for auto-applicators or manual application. Following cure of the bond coat with the embedded fibrous array, the handling layer including the release film608and the structure-weight application cap610are pulled away.

Referring toFIGS. 7A-7D, an embodiment of a fibrous interface700of one embodiment of the present invention is illustrated. The fibrous interface700is similar to fibrous interface216. In this embodiment the fibrous interface700(or fibrous interface pad) includes an array of protruding surface features. The protruding surface features are made of a solvent-resistant, high tension fibers. In this example, the surface features are protruding bristles702. In one embodiment the bristles702are less than 20 mils in length. In another embodiment, the bristles have a length that is complementary to the critical height of the coating. In embodiments, the bristles702are encapsulated by the top-coat. The bristles have a stiffness such that will allow for complete, uniform penetration into the bond coat, as required by bond coat viscosity. Other types of protruding surface features are contemplated including but not limited to tubules, ridge pegs and furrows.

Another embodiment of the present invention is illustrated inFIGS. 8A through 8D. In this embodiment a module, such as a ceramic laminate multi-chip module (MCM-L) assembly800, is formed from a substrate802without sidewalls. In particular,FIG. 8Aillustrated a side view of the integrated circuit including circuit components804on a MCM-L substrate802. As illustrated, the substrate802does not have sidewalls in this embodiment. Referring toFIG. 8B, a bond coat806is formed to encase the circuit components804. A fibrous interface808is formed over the bond coat806. In one embodiment, the fibrous interface808has a portion embedded in the bond coat806. Further in one embodiment, surface features, such as those illustrated inFIG. 7A, of the fibrous interface808are embedded in the bond coat806.

In one embodiment, a perimeter seal810is formed that extends around the circuit components804. A cap812is then formed to cover the circuit. This is illustrated inFIG. 8C. In one embodiment, the material used to form the cap812has a coefficient of thermal expansion (CTE) that matches the CTE of the MCM-L substrate802. Similarly, the material of the fibrous interface808is also selected to match the CTE of the MCM-L substrate802. Hence thermal expansion in x, y and z directions throughout the material of the IC are the same. This reduces mechanical stress on the coated MCM assembly800during thermal cycles.FIG. 8Dillustrates an alternative formation of the MCM assembly. In this embodiment, the fibrous interface808is formed on the cap812before it is mated with the bond coat806, optional perimeter seal810and substrate802to form the MCM assembly800.