Integrated assemblies comprising stud-type capacitors

Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.

TECHNICAL FIELD

BACKGROUND

Capacitors may have many uses in integrated circuitry. For instance, capacitors may be incorporated into memory circuitry (e.g., dynamic random access memory (DRAM)), control circuitry, sensors, etc. Integrated capacitors generally have a storage node electrode, a dielectric material, and a plate electrode; with the dielectric material being between the storage node electrode and the plate electrode.

Two general types of capacitors are crown-type capacitors and stud-type (also referred to as pillar-type) capacitors. Crown-type capacitors have the storage node electrode configured in a container-shape, and may have the dielectric material and plate electrode extending into the container-shaped storage node. In contrast, stud-type capacitors have the storage node electrode configured as a pillar, and have the dielectric material and plate electrode extending around the pillar.

A continuing goal of integrated circuit fabrication is to increase integration density. A related goal is to develop capacitor architectures which consume a relatively small footprint over a semiconductor base, while still achieving suitable capacitive storage. Accordingly, capacitors may be formed to be increasingly tall and thin with increasing levels of integration.

As capacitors become increasingly tall and thin, the capacitors are subject to toppling. Stud-type capacitors may have increased structural stability as compared to crown-type capacitors, and accordingly may be more resistant to toppling than crown-type capacitors. However, difficulties have been encountered in obtaining consistent and uniform performance across arrays of highly integrated stud-type capacitors. It is desired to develop improved stud-type capacitor architectures.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include recognition that a problem with conventional stud-type capacitor configurations is that upper surfaces of the capacitor dielectric may become damaged during a fabrication process. Accordingly, some embodiments include stud-type capacitor architectures which effectively remove the upper regions of the capacitor dielectric from being incorporated into functioning portions of the stud-type capacitors. Such removal may be accomplished by vertically offsetting the upper surface of a capacitor plate electrode relative to the upper surface of a storage node electrode. Some embodiments additionally, or alternatively, include recognition that a problem with conventional stud-type capacitor configurations may be that lower surfaces of the capacitor dielectric may become damaged during a fabrication process, and such embodiments may effectively remove the lower regions of the capacitor dielectric from being incorporated into functioning portions of the stud-type capacitors by vertically offsetting the lower surface of a capacitor plate electrode relative to the lower surface of an outer periphery of the storage node electrode. Example embodiments are described below with reference toFIGS. 1-28.

Referring toFIG. 1, such illustrates a region of an integrated assembly10. The integrated assembly10includes a plurality of stud-type capacitors12supported over a base14. Although four example capacitors12are illustrated, it is to be understood that an actual memory array may comprise a very high number of capacitors; with the actual number of capacitors in some example memory arrays being hundreds, thousands, millions, billions, etc.

The base14may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base14may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base14may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

In the illustrated embodiment, the capacitors12are spaced from the base14by an intervening gap. Additional materials and structures may be within such gap. For instance, in the shown embodiment transistors16are diagrammatically illustrated as being within the gap.

Each of the capacitors12includes a storage node electrode18, a dielectric material20and a plate electrode22. In some embodiments, the storage node electrodes18may be referred to as first electrodes, and the plate electrodes22may be referred to as second electrodes.

In the illustrated embodiment, the first electrodes18comprise conductive pillars24and conductive liners26extending along outer lateral surfaces of the conductive pillars. The conductive pillars24have outer sidewalls25(only labeled relative to one of the capacitors12), and the conductive liners26are along and directly against such outer sidewalls. The conductive pillars24are viewed along a vertical cross-section inFIG. 1. Each of the conductive pillars24may have any suitable shape when viewed along a horizontal cross-section (i.e., a cross-section through the pillars and orthogonal to the vertical cross-section ofFIG. 1); such as, for example, circular, square, rectangular, elliptical, etc. The conductive liners26extend entirely around lateral peripheries of the conductive pillars24(as shown inFIGS. 25-28relative to example capacitor configurations in which the conductive pillars24have circular shapes when viewed along a horizontal cross-section).

The conductive pillar24and conductive liner26(e.g., the conductive structures of the first electrode18), and the second electrode22of each capacitor12may comprise any suitable electrically conductive composition or combination of compositions; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive liner26and the second electrode22of each capacitor12may comprise a same composition as one another. For instance, the conductive liner26and the second electrode22may both comprise metal nitride, such as, for example, titanium nitride. In some embodiments, the conductive liner26and the second electrode22of each capacitor12may comprise different compositions relative to one another. In some embodiments, the conductive liner26of each capacitor12may comprise metal nitride (e.g., titanium nitride), and the conductive pillar24of each capacitor may comprise metal (for instance, tungsten, titanium, etc.) and/or conductively-doped semiconductor (for instance, conductively-doped silicon, conductively-doped germanium, etc.).

The second electrode22and the liner26of each capacitor12may be formed to any suitable thicknesses; such as, for example, thicknesses within a range of from about 20 angstroms (Å) to about 50 Å. The conductive pillars24of the capacitors12may be formed to any suitable widths, W, along the cross-section section ofFIG. 1, including, for example, widths within a range of from about 5 nanometers (nm) to about 100 nm.

The dielectric material20(i.e., the capacitor dielectric material) may comprise any suitable composition or combination of compositions; such as, for example, one or more of zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, strontium titanate (STO), etc. In some embodiments, the dielectric material20may be considered to be configured as dielectric liners23along outer surfaces of the storage node electrodes18(i.e., laterally outward of conductive pillars24). The second electrodes22may be referred to as conductive liners that extend along the dielectric liners23.

The conductive pillars24have first upper surfaces31(only labeled relative to one of the capacitors12), the dielectric liners23have second upper surfaces33(only labeled relative to one of the capacitors12), and the conductive liners22have third upper surfaces35(only labeled relative to one of the capacitors12). The first upper surfaces31of the conductive pillars24are beneath the third upper surfaces35of the second electrodes22. The second upper surfaces33of the capacitor dielectric material20are above the first upper surfaces31of the conductive pillars24, and in the shown embodiment are substantially coplanar with the third upper surfaces35of the second electrodes22(with the term “substantially coplanar” meaning coplanar to within reasonable tolerances of fabrication and measurement).

The functional capacitive portions of the dielectric material20are the portions laterally between the first electrode24and the second electrode22(i.e., the portions of the dielectric material at or below the elevation height of the first upper surfaces31in the embodiment ofFIG. 1). Accordingly, regions36of the dielectric material20(only labeled relative to one of the capacitors) are not utilized as functional capacitive portions of the dielectric material. To the extent that there may be damage at the upper regions of the dielectric material20during fabrication of dielectric material20, such damage will likely be contained entirely within the regions36. Accordingly, the vertical offset of the first upper surfaces31of conductive pillar24relative to the second and third upper surfaces33and35of the capacitor dielectric material20and the second electrode22enables potentially-damaged portions of dielectric material20to be eliminated from the functional capacitive portions of the dielectric material utilized in the capacitors12. The damaged upper regions of capacitor dielectric material20may be responsible for inconsistent performance characteristics of capacitors across conventional memory arrays. Accordingly, elimination of the damaged upper regions from the functional capacitor dielectric of the capacitors may enable improved consistency of performance amongst the numerous capacitors of a memory array as compared to conventional constructions.

In the shown embodiment, insulative pads40are over the conductive pillars24and conductive liners26, and extend entirely across upper surfaces of the storage nodes18. Such insulative pads they comprise any suitable composition or combination of compositions; and some embodiments may comprise silicon dioxide.

The insulative pads40have fourth upper surfaces37(only labeled relative to one of the capacitors12), and such fourth upper surfaces37are substantially coplanar with the upper surfaces33of dielectric material20and the upper surfaces35of second electrodes22.

The insulative pads have thicknesses, T. Upper surfaces33of the dielectric liners23are offset from the upper surfaces31of the conductive pillars24by the thickness T. The thickness T may comprise any suitable dimension; and in some embodiments, may be at least about 10 Å, at least about 50 Å, etc.

A conductive lattice42extends around upper regions of the capacitors12and directly contacts outer lateral surfaces of the second electrodes22. The conductive lattice42may comprise any suitable conductive material, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive lattice42may comprise, consist essentially of, or consist of conductively-doped semiconductor material; such as, for example, one or both of conductively-doped silicon and conductively-doped germanium. The conductive doping may be n-type or p-type; and in some embodiments the conductive lattice42may comprise, consist essentially of, or consist of n-type doped silicon, n-type doped germanium or n-type doped silicon/germanium.

Conductive materials44and46are provided over the conductive lattice42. Such conductive materials may comprise any suitable electrically conductive compositions or combinations of electrically conductive compositions. In some embodiments, the conductive material44may comprise, consist essentially of, or consist of metal nitride (for instance, titanium nitride), and the conductive material46may comprise, consist essentially of, or consist of metal (for instance, tungsten). The conductive material44, conductive material46and conductive lattice42may be considered together to form a conductive plate48. The conductive plate48extends across the insulative pads40and outwardly from the conductive liners22, and electrically couples the conductive liners22of different capacitors12to one another. In some embodiments, the conductive lattice may be considered to be configured as a first conductive structure of the conductive plate48, the conductive material44may be considered to be configured as a second conductive structure of the conductive plate48, and the conductive structure46may be considered to be configured as a third conductive structure of the conductive plate48.

In some embodiments, the electrically conductive material44may be referred to as a conductive region that extends across the insulative pads40.

In some embodiments, the configuration ofFIG. 1may be considered to have the second electrodes22vertically overlapping conductive material of a conductive lattice42, and in addition vertically overlapping conductive materials44and46. In other embodiments, the second electrodes22may only vertically overlap the conductive material of lattice42rather than also vertically overlapping materials44and46(with an example of such other embodiments being described below with reference toFIG. 21). In the shown embodiment, the third upper surfaces35of the second electrodes22directly contact the electrically conductive material44.

The capacitors12extend through insulative materials50and52. Such insulative materials may comprise any suitable compositions or combinations of compositions. For instance, in some embodiments the insulative material50may comprise a silicate glass (e.g., borophosphosilicate glass (BPSG)), and the insulative material52may comprise silicon nitride.

In the shown embodiment, the conductive pillars24extend through the insulative material52and contact other materials (not shown) below such insulative material. The other materials may be electrically coupled with source/drain regions54of the illustrated transistors16. Other source/drain regions56of the transistors16may be electrically coupled with a bitline58. In some embodiments, the source/drain regions54may be referred to as first source/drain regions, and the source/drain regions56may be referred to as second source/drain regions. The transistors16have transistor gates which are electrically coupled with wordlines60(a-d). Each of the capacitors12is comprised by a memory cell62(a-d) of a memory array64; with each memory cell being uniquely addressed through one of the wordlines (60(a-d)) and the bitline58. In the shown embodiment, the capacitors12are connected to a common bitline58, as would occur if the capacitors are in a common column as one another. In other embodiments, the illustrated capacitors may be electrically connected to a common wordline (as would occur if the capacitors were in a common row as one another), rather than to a common bitline.

In the shown embodiment, the liners26may be referred to as first conductive liners and the liners22may be referred to as second conductive liners. The first conductive liners26have first bottom surfaces61, the dielectric liners23have second bottom surfaces63, and the second conductive liners22have third bottom surfaces65. The third bottom surfaces65are above the first and second bottom surfaces61and63. The first bottom surfaces61may be vertically offset from the third bottom surfaces65by any suitable dimension; and in some embodiments may be vertically offset by a distance of at least about 50 Å.

Lower regions67of the dielectric material20(only labeled relative to one of the capacitors) are not utilized as functional capacitive portions of the dielectric material. To the extent that there may be damage at the lower regions of the dielectric material20during fabrication of dielectric material20, such damage will likely be contained entirely within the regions67. Accordingly, the vertical offsets of the first, second and third lower surfaces61,63and65enables potentially-damaged portions of dielectric material20to be eliminated from the functional capacitive portions of the dielectric material utilized in the capacitors12. Such may improve consistency of performance amongst the numerous capacitors of the memory array as compared to conventional constructions.

FIG. 2shows an integrated assembly10awhich is similar to the integrated assembly10ofFIG. 1, except that the third upper surfaces35of the second electrodes22are recessed relative to the assembly10ofFIG. 1, and insulative spacers66are provided over such recessed third upper surfaces35. The insulative spacers66may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon nitride. The first, second and third upper surfaces31,33and35of the conductive pillar24, dielectric material20and second electrode22, respectively, are arranged differently in the integrated assembly10aofFIG. 2as compared to the integrated assembly10ofFIG. 1. Specifically, the integrated assembly10ahas the second upper surfaces33of dielectric material20above the first upper surfaces31of the conductive pillars24and the third upper surfaces35of the second electrodes22; and has the third upper surfaces35of the second electrodes22beneath the first upper surfaces31of the conductive pillars24. Although the first, second and third surfaces31,33and35are arranged differently in the integrated assembly10aofFIG. 2as compared to the integrated assembly10ofFIG. 1, a similar advantage is achieved in that upper regions of the dielectric material20(upper regions68inFIG. 2) are not utilized as functional capacitive portions of the dielectric material20. Such may enable improved consistency of performance amongst the numerous capacitors of a memory array (e.g., memory array64aofFIG. 2) as compared to conventional capacitor constructions.

In some embodiments, the insulative spacers66ofFIG. 2may be considered to have fifth upper surfaces39(only labeled relative to one of the capacitors12); with such fifth upper surfaces being substantially coplanar with the fourth upper surfaces37of insulative pads40and the second upper surfaces33of dielectric material20.

In the embodiment ofFIG. 2, each of the insulative spacers66has a lateral thickness which is about the same as the lateral thickness of the underlying second electrode22(with the term “about the same” meaning that the compared thicknesses are the same to within reasonable tolerances of fabrication and measurement).

The spacers66vertically overlap the material of conductive lattice42in the embodiment ofFIG. 2. In other embodiments, the spacers66may be entirely above the conductive lattice42(as described below with reference to an embodiment ofFIG. 23). In the embodiment ofFIG. 2, the spacers66also vertically overlap conductive materials44and46of the conductive plate48. In other embodiments, the spacers66may only vertically overlap material of conductive lattice42(as described below with reference toFIG. 24).

The assemblies ofFIGS. 1 and 2(and analogous assemblies described below with respect toFIGS. 21, 23 and 24) may be formed with any suitable processing. Example processing is described with reference toFIGS. 3-24.

Referring toFIG. 3, an assembly10comprises a stack80supported over the base14. The stack80comprises conductive lattice material82over the insulative materials50and52. The conductive lattice material82ultimately forms the conductive lattice42described above with reference toFIG. 1; and in some embodiments may comprise, consist essentially of, or consist of one or both of conductively-doped silicon and conductively-doped germanium. The insulative material50may comprise BPSG having a dopant gradient provided therein, or any other suitable insulative composition. The insulative material52may comprise silicon nitride, or any other suitable insulative composition.

A sacrificial material84is provided over the conductive lattice material82. Such sacrificial material may comprise any suitable composition; and in some embodiments may comprise silicon nitride.

Referring toFIG. 4, openings86are etched into stack80. Locations of the openings may be patterned with a photoresist mask (not shown) or with any other suitable methodology. The openings may be etched with any suitable etching chemistries, including, for example, one or more dry etches and/or one or more wet etches. The openings may have any suitable shapes and dimensions. In the shown embodiment, the openings have widths, W1; and such widths may be within a range of from about 20 nm to about 70 nm. The openings are separated from one another by spacing regions88, and such spacing regions have widths W2; which in some embodiments may be less than or equal to about 10 nm, less than or equal to about 5 nm, etc. The openings86are shown to have vertical sidewalls which are relatively straight (i.e., orthogonal to an upper surface of base14), at least along upper regions of the openings. Such may be desired in some embodiments. In other embodiments, the sidewalls may have other configurations.

The formation of openings86through conductive lattice material82patterns the material82into the conductive lattice42described above with reference toFIG. 1.

The openings86may be in any suitable arrangement.FIG. 5shows a top view of the assembly10ofFIG. 4, and shows the openings86in an hexagonally packed arrangement. The hexagonal packing may be desired in some applications in that such may achieve a very tight packing density of stud-type capacitors ultimately formed within the openings86.

Referring toFIG. 6, assembly10is shown at a processing stage following that ofFIG. 4. Conductive material90is formed within the openings86, and sacrificial material92is formed over the conductive material90. The conductive material90is ultimately patterned into the second electrodes22(FIG. 1), and accordingly may comprise any of the compositions described above relative to the second electrodes22. In some embodiments, the conductive material90comprises titanium nitride formed to a thickness within a range of from about 20 Å to about 50 Å.

The sacrificial material92may comprise any suitable composition or combination of compositions; and in some embodiments may comprise polycrystalline silicon formed to a thickness within a range of from about 20 Å to about 50 Å.

Referring toFIG. 7, masking material94is formed across the spacing regions88to partially block the openings86. The masking material94may comprise, for example, one or more of carbon, silicon nitride, silicon oxide, etc.; and may be non-conformally deposited.

The masking material94is utilized to pattern openings etched through sacrificial material92, and subsequently the conductive material90is etched back utilizing wet etching methodologies (for instance, utilizing ammonium hydroxide-based methodologies, or any other suitable methodologies).

FIG. 8shows a processing stage alternative to that ofFIG. 7. Specifically, the sacrificial masking material92may be initially etched to expose surfaces of conductive material90over the spacing regions88as well as at the bottoms of openings86. The masking material94may be subsequently provided over the spacing regions88, followed by wet etching of conductive material90.

FIG. 9shows a processing stage following that of eitherFIG. 7orFIG. 8; and specifically shows assembly10after the sacrificial material92(FIGS. 7 and 8) and masking material94(FIGS. 7 and 8) are removed.

Referring toFIG. 10, dielectric material20is formed over conductive material90and within openings86, and a conductive material96is formed over the dielectric material20. The dielectric material20may comprise any of the compositions described above with reference toFIG. 1. The conductive material96is ultimately patterned into the conductive liners26ofFIG. 1, and may comprise any of the compositions described above relative to such conductive liners. For instance, in some embodiments the conductive material96may comprise metal nitride; such as, for example, titanium nitride, tungsten nitride, etc. The dielectric material20may be formed to a thickness within a range of from about 40 Å to about 70 Å; and the conductive material96may be formed to a thickness within a range of from about 20 Å to about 50 Å.

Referring to the11, the conductive material96is removed from the horizontal surfaces (i.e., the tops of spacing regions88and the bottoms of openings86) with suitable etching (e.g., a punch etch).

Referring toFIG. 12, masking material98is formed across the spacing regions88to partially block the openings86. The masking material98may comprise, for example, one or more of carbon, silicon nitride, silicon oxide, etc.; and may be non-conformally deposited.

The masking material98is utilized to pattern openings etched through dielectric material20.

Referring toFIG. 14, openings86are extended through insulative material52with a suitable dry etch. The etching conditions may also remove materials90,20and96from over the spacing regions88, and may thin the sacrificial material84across the spacing regions88.

As the materials90,20and96are removed from over the spacing regions88, such are patterned into the liners ofFIG. 1. Specifically, material90is patterned into the conductive liners22corresponding to the second electrodes, the dielectric material20is patterned into the dielectric liners23, and the conductive material96is patterned into the conductive liners26.

Referring toFIG. 15, conductive material100is provided within openings86and patterned into the conductive pillars24. In some embodiments, conductive material100may be deposited within openings86and across spacing regions88; and may be patterned utilizing chemical-mechanical polishing (CMP) to remove excess conductive material100from over the spacing regions88.

Referring toFIG. 16, pillars24are recessed with appropriate etching. Such etching may also recess the conductive liners22and26.

Referring toFIG. 17, insulative material102is provided across the recessed pillars24and patterned into the insulative pads40. The insulative material102may comprise silicon dioxide, and may be formed with any suitable processing (for instance, spin-on processing, chemical vapor deposition, atomic layer deposition, etc.). The insulative material may be patterned into the pads40utilizing CMP.

Referring toFIG. 19, the conductive materials44and46are formed to extend across the undulating upper surface103(with such surface103being labeled inFIG. 18). The construction ofFIG. 19is identical to that ofFIG. 1, and comprises the capacitors12of the memory array64. The transistors beneath the capacitors (transistors16ofFIG. 1) are not shown inFIG. 19, but may be provided at any suitable processing stage, including, for example, a processing stage prior to formation of the stack80ofFIG. 3.

FIG. 20shows a processing stage alternative to that ofFIG. 18, with the construction10ofFIG. 20having a substantially planar upper surface103extending along an upper surface of the conductive lattice42, the upper surfaces37of insulative pads40, the upper surfaces33of dielectric liners23, and the upper surfaces35of conductive liners22. The term “substantially planar” means planar to within reasonable tolerances of fabrication and measurement.

FIG. 21shows a processing stage subsequent to that ofFIG. 20, and in which the conductive materials44and46are formed to extend across the substantially planar upper surface103.

FIG. 22shows a processing stage which may be subsequent to the processing stage ofFIG. 18, and which may be utilized to form the assembly10aofFIG. 2. Specifically,FIG. 22shows the insulative spacers66(described above with reference toFIG. 2) formed over upper surfaces of the conductive liners22. The insulative spacers66may be formed utilizing a process sequence in which upper regions of conductive liners22(with such upper regions being shown inFIG. 18) are removed to expose sidewalls of dielectric liners23. Subsequently, insulative material of the spacers66is deposited across assembly10and along the exposed sidewalls of the dielectric liners; and then subjected to an anisotropic etch to pattern such insulative material into the illustrated spacers66. In the shown embodiment, the spacers66have a lateral thickness which is substantially the same as the lateral thickness of the conductive liners22beneath such insulative spacers. In other embodiments, the insulative spacers may have lateral thicknesses greater than the lateral thicknesses of the conductive spacers22underlying such insulative spacers, or may have lateral thicknesses less than the lateral thicknesses of the conductive spacers22underlying such insulative spacers.

Referring toFIG. 23, the conductive materials44and46are formed to complete the fabrication of the assembly10aof the type described above with reference toFIG. 2. The assembly ofFIG. 23differs slightly from that ofFIG. 2in that the spacers66are formed to be entirely vertically above the conductive lattice42in the embodiment ofFIG. 23, whereas such spacers vertically overlapped the conductive lattice42in the embodiment ofFIG. 2. Whether or not the spacers66overlap the conductive lattice42may be determined, at least in part, by amount of the conductive liner22removed by the etch described above with reference toFIG. 22as being conducted prior to formation of the spacers66.

Referring toFIG. 24, such shows assembly10ain a configuration alternative to that ofFIG. 21, and specifically comprising a planar surface103extending across an upper surface the conductive lattice42, upper surfaces39(only one which is labeled) of spacers66and upper surfaces33(only one which is labeled) of insulative liners23. The conductive materials44and46extend across the planar surface103.

The transistors16are shown inFIG. 24in order to fully illustrate a region of the shown example memory array64a.

FIG. 25shows a horizontal cross-section along the line25-25ofFIG. 1(with the cross-section ofFIG. 1being along the line1-1ofFIG. 25). Current flow along the conductive lattice42is illustrated inFIG. 25. Such current flow advantageously serpentines around outer surfaces of the capacitors12as the current flows through the conductive lattice42of the plate48(FIG. 1).

FIG. 26shows a horizontal cross-section through several capacitors, and shows example dimensions relative to the capacitors. The capacitors have overall widths200which may be within a range of from about 20 nm to about 80 nm. The inner pillar24has a width202which may be within a range of from about 5 nm to about 25 nm. Adjacent capacitors may be separated by a distance204which may be less than 5 nm, less than 2 nm, or even less than 1 nm. A center to center distance206between adjacent capacitors may be within a range of from about 20 nm to about 80 nm.

In some embodiments, adjacent capacitors may merge together if portions of the openings86(FIG. 5) merge.FIGS. 27 and 26illustrate possible configurations which may result from merging of two or more of the stud-type capacitors with one another. Such may advantageously increase packing density.

The capacitors described herein may be utilized for memory (as shown in some of the embodiments described herein); including 1-transistor-1-capacitor (1T1C) memory, 2-transistor-1-capacitor (2T1C) memory, 2-transistor-2-capacitor (2T2C) memory, 3-transistor-1-capacitor (3T1C) memory, etc. The capacitor dielectric materials described above may include ferroelectric materials in some embodiments, and the capacitors may correspond to ferroelectric capacitors, or may be otherwise incorporated into ferroelectric memory. The capacitors described herein may also be utilized in other types of circuitry in addition to, or alternatively to, memory; including, for example, processor circuitry, sensor circuitry, etc.

The structures discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present.

Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included in a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces.

Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included in a first electrode of a capacitor and having a first upper surface. A dielectric liner is along an outer surface of the conductive pillar. The dielectric liner has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface which is beneath the first upper surface. An insulative spacer is over the third upper surface and has a fourth upper surface which is substantially coplanar with the second upper surface. An insulative material extends entirely across the first upper surface and has a vertical thickness. The second upper surface is above the first upper surface by a distance substantially equal to the vertical thickness. A conductive plate directly contacts the conductive liner, and extends over and entirely across the insulative material.

Some embodiments include an integrated assembly having conductive pillars supported by a base and being included within first electrodes of capacitors, with the conductive pillars having first upper surfaces. Dielectric liners are along outer surfaces of the conductive pillars, and have second upper surfaces. Conductive liners are along the dielectric liners and are included within second electrodes of the capacitors. The conductive liners have third upper surfaces. The third upper surfaces are beneath the first upper surfaces. Insulative pads are over the first upper surfaces and have fourth upper surfaces. Insulative spacers are over the conductive liners and have fifth upper surfaces. The second upper surfaces, fourth upper surfaces and fifth upper surfaces are substantially coplanar with one another. A conductive plate extends across the insulative pads and laterally outwardly from the conductive liners. The conductive plate electrically couples the conductive liners to one another.

Some embodiments include an integrated assembly having conductive pillars supported by a base and being included within first electrodes of capacitors, with the conductive pillars having first upper surfaces. Dielectric liners are along outer surfaces of the conductive pillars, and have second upper surfaces. Conductive liners are along the dielectric liners and are included within second electrodes of the capacitors. The conductive liners have third upper surfaces. The first upper surfaces are beneath the third upper surfaces. Insulative pads being are over the first upper surfaces and have fourth upper surfaces. The second upper surfaces, third upper surfaces and fourth upper surfaces are substantially coplanar with one another. A conductive plate extends across the insulative pads and laterally outwardly from the conductive liners. The conductive plate electrically couples the conductive liners to one another.