Method of writing into semiconductor memory device

An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the high resistance state, the gate voltage of the NMOS transistor 14 is set at a value which is equal to or greater than the total of the reset voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14 and is smaller than the total of the set voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14, whereby the voltage applied to the resistance memory element 10 is set at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

TECHNICAL FIELD

The present invention relates to a method of writing into a semiconductor memory device, more specifically, a method of writing into a semiconductor memory device using a resistance memory element having a plurality of resistance states of different resistance values.

BACKGROUND

Recently, as a new memory device, a semiconductor memory device called Resistance Random Access Memory (RRAM) is noted. The RRAM uses a resistance memory element which has a plurality of resistance states of different resistance values which are changed by electric stimulations applied from the outside and whose high resistance state and low resistance state are corresponded to, e.g., information “0” and “1” to be used as a memory element. The RRAM is considered prospective because of the high potentials of the high speed, large capacities, low electric power consumption, etc.

The resistance memory element has a resistance memory material whose resistance states are changed by the application of voltages sandwiched between a pair of electrodes. As the typical resistance memory material, oxide materials containing transition metals are known.

However, the conventional method of simply applying a voltage to the resistance memory element to thereby change the state of the resistance memory material from the low resistance state to the high resistance state applies an excessive voltage to the resistance memory element. There is a risk that such an excessive voltage might change the resistance state of the resistance memory element from the high resistance state again to the low resistance state, and the high resistance state could not be retained.

SUMMARY

According to one aspect of the present invention, there is provided a semiconductor memory device comprising: a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance by a voltage application; a transistor having one end connected to one end of the resistance memory element; and wherein when a voltage is applied to the resistance memory element via the transistor to switch the resistance memory element from the low resistance state to the high resistance state, a gate voltage of the transistor is set at a value which is equal to or greater than a total of a reset voltage necessary to reset the resistance memory element and a threshold voltage of the transistor and is smaller than a total of a set voltage necessary to set the resistance memory element and the threshold voltage, to thereby set the voltage applied to the resistance memory element at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

According to another aspect of the present invention, there is provided a method of writing into a semiconductor memory device comprising a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by a voltage application, the method comprising: providing a transistor having one end connected to one end of the resistance memory element; and when applying a voltage to the resistance memory element via the transistor to switch the resistance memory element from the low resistance state to the high resistance state, setting a gate voltage of the transistor at a value which is equal to or greater than a total of a reset voltage necessary to reset the resistance memory element and a threshold voltage of the transistor and is smaller than a total of a set voltage necessary to set the resistance memory element and the threshold voltage, to thereby set the voltage applied to the resistance memory element at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

According to further another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells arranged in a matrix and each including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by a voltage application, and a selective transistor having one end connected to one end of the resistance memory element; a plurality of first signal lines arranged in parallel with each other in a first direction and each connected to gate electrodes of the selective transistors of the memory cells arranged in the first direction; and a plurality of second signal lines arranged in parallel with each other in a second direction crossing the first direction and each connected to the other ends of the selective transistors of the memory cells arranged in the second direction, wherein a voltage which is equal to or greater than a total of a reset voltage necessary to reset the resistance memory element and a threshold voltage of the selective transistor and is smaller than a total of a set voltage necessary to set the resistance memory element and the threshold voltage is applied to the first signal line connected to a memory cell to be rewritten of said plurality of the memory cells, whose resistance memory element is to be rewritten from the low resistance state to the high resistance state, and a pulse voltage equal to or greater than the reset voltage is applied to the second signal line connected to the memory cell to be rewritten, with the voltage which is equal to or greater than the total of the reset voltage and the threshold voltage and is smaller than the total of the set voltage and the threshold voltage being applied to the first signal line connected to the memory cell to be rewritten, to thereby rewrite the resistance memory element of the memory cell to be rewritten from the low resistance state to the high resistance state.

According to further another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells arranged in a matrix and each including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by a voltage application, and a selective transistor having one end connected to one end of the resistance memory element; a plurality of first signal lines arranged in parallel with each other in a first direction and each connected to gate electrodes of the selective transistors of the memory cells arranged in the first direction; and a plurality of second signal lines arranged in parallel with each other in a second direction crossing the first direction and each connected to the other ends of the selective transistors of the memory cells arranged in the second direction, wherein a voltage equal to or greater than a reset voltage necessary to reset the resistance memory element is applied to the second signal line connected to a memory cell to be rewritten of said plurality of the memory cells, whose resistance memory element is to be rewritten from the low resistance state to the high resistance state, and a pulse voltage which is equal to or greater than a total of the reset voltage and a threshold voltage of the selective transistor and is smaller than a total of a set voltage necessary to set the resistance memory element and the threshold voltage is applied to the first signal line connected to the memory cell to be rewritten, with the voltage equal to or greater than the reset voltage being applied to the second signal line connected to the memory cell to be rewritten, to thereby rewrite the resistance memory element of the memory cell to be rewritten from the low resistance state to the high resistance state.

DETAILED DESCRIPTION OF THE INVENTION

A FIRST EMBODIMENT

First, the basic operation of the resistance memory element will be explained with reference toFIG. 1.

The resistance memory element includes a resistance memory material sandwiched between a pair of electrodes. Many of the resistance memory materials are oxide materials containing transition metals and can be classified roughly in two groups, depending on the electric characteristics difference.

One group includes materials which require voltages of the same polarity so as to change the resistance value between the high resistance state and the low resistance state, and oxides of single transition metals, such as NiOx, TiOx, and others fall into said one group. Such a resistance memory material which requires voltages of the same polarity to rewrite the resistance state is called a unipolar resistance memory material.

The other includes materials which require voltages of polarities different from each other so as to change the resistance state between the high resistance state and the low resistance state, and SrTiO3and SrZrO3doped with a trance of an impurity, such as chrome (Cr), etc. or Pr1-xCaxMnO3, La1-xCaxMnO3, etc., which exhibit CMR (Colossal Magneto-Resistance), fall into the other group. Such a resistance memory material which requires voltages of polarities different from each other to rewrite the resistance state is called a bipolar resistance memory material.

In the following explanation, the resistance memory element using the unipolar resistance memory material will be explained.

FIG. 1is a graph showing the current-voltage characteristics of the resistance memory element using the unipolar resistance memory material. This graph is of the case that TiOx, which is a typical unipolar resistance memory material, is used.

In the initial state, the resistance memory element is assumed to be in the high resistance state.

As the applied voltage is increased gradually from 0 V, the current changes in the arrowed direction along the curve a, and its absolute value gradually increases. The applied voltage is further increased, and when the applied voltage has exceeded a prescribed value, the resistance memory element is switched from the high resistance state to the low resistance state. In the following explanation, the operation of changing the resistance memory element from the high resistance state to the low resistance state is called “set”. Accompanying this, the absolute value of the current abruptly increases, and the current-voltage characteristics transit from the point A to the point B. InFIG. 1, the current value at the point B is constant, because the current restriction is made for the preventing of the breakage of the element by the abrupt current increase.

As the applied voltage is decreased gradually from the state at the point B, the current changes in the arrowed direction along the curve b, and its absolute value gradually decreases. When the applied voltage is returned to 0 V, the current also becomes 0 A.

Next, when the current restriction is released, and the applied voltage is increased gradually from 0 V, the current changes in the arrowed direction along the curve c, and its absolute value gradually increases. The applied voltage is further increased, and when the applied voltage has exceeded a prescribed value, the resistance memory element is switched from the low resistance state to the high resistance state. In the following explanation, the operation of changing the resistance memory element from the low resistance state to the high resistance state is called “reset”. Accompanying this, the absolute value of the current abruptly decreases, and the current-voltage characteristics transit from the point C to the point D.

As the applied voltage is decreased gradually from the state at the point D, its absolute value gradually decreases. When the applied voltage is returned to 0 V, the current also becomes 0 V.

The respective resistance states are stable at a prescribed voltage value or below and are retained even when the power source is turned off. That is, in the high resistance state, the applied voltage is below the voltage at the point A, the current-voltage characteristics change linearly along the curve a, and the high resistance state is retained. Similarly, in the low resistance state, when the applied voltage is below the voltage at the point C, the current-voltage characteristics change along the curve c, and the low resistance state is retained.

As described above, to set or reset the resistance memory element, a voltage necessary respectively for the set and reset may be applied. In the actual operation, however, when a voltage is simply applied to reset the resistance memory element from the low resistance state to the high resistance state, an inconvenience arises as follows.

FIG. 2Ais a circuit diagram showing the circuit constitution for applying a voltage to the resistance memory element. As shown, a resistance memory element10has one end connected to a pulse generator12for applying a pulse voltage and has the other end connected to a reference potential, e.g., 0 V, which is the ground potential.FIG. 2Bshows a pulse voltage of a voltage value Vpulseto be applied to the resistance memory element10by the pulse generator12.

FIGS. 3A and 3Bshow time charts of a voltage V1applied to the resistance memory element10when the pulse voltage is applied to the resistance memory element10in the circuit constitution ofFIG. 2.FIG. 3Ashows the time variation of the voltage V1when the resistance memory element10is set from the high resistance state to the low resistance state.FIG. 3Bshows the time variation of the voltage V1when the resistance memory element10is reset from the low resistance state to the high resistance state.

When the resistance memory element10is set, a pulse voltage of a voltage value (set voltage value Vset) necessary to set the resistance memory element10is applied to the resistance memory element10by the pulse generator12. At the time when this pulse voltage is applied to the resistance memory element10, a required voltage is applied to the resistance memory element10. Thus, the resistance memory element10is changed from the high resistance state to the low resistance state (FIG. 3A). When the resistance memory element10is changed to the low resistance state, most of the applied voltage is applied to the interior resistor of the pulse generator12or the resistor of the interconnection between the pulse generator12and the resistance memory element10. Resultantly, the voltage applied to the resistance memory element10is lowered.

On the other hand, when the resistance memory element10is reset, a pulse voltage of a voltage value (reset voltage Vreset) necessary to reset the resistance memory element10is applied to the resistance memory element10. At the time when this pulse voltage is applied to the resistance memory element10, a required voltage is applied to the resistance memory element10. Thus, the resistance memory element10is changed from the low resistance state to the high resistance state (FIG. 3B). However, in resetting the resistance memory element10, instantaneously with the resistance memory element10having changed to the high resistance state, almost all of the applied voltage is applied to the resistance memory element10. Accordingly, the voltage applied to the resistance memory element10exceeds the set voltage, and there is a risk that the resistance memory element10might be changed from the high resistance state to the low resistance state, and the high resistance state could not be retained.

The resetting method of the resistance memory element according to the present embodiment makes it possible to prevent the application of an excessive voltage to the resistance memory element when the resistance memory element is switched from the low resistance state to the high resistance state, and resultantly the resistance memory element is prevented from changing again to the low resistance state due to the application of the excessive voltage.

First, the circuit constitution for carrying out the resetting method of the resistance memory element according to the present embodiment will be explained with reference toFIG. 4.

As shown, the pulse generator12for applying a pulse voltage is connected to the drain terminal of an NMOS transistor14. To the source terminal of the NMOS transistor14, one end of the resistance memory element10is connected. The other end of the resistance memory element10is connected to the reference potential, e.g., 0 V, which is the ground potential.

The resistance memory element10includes a unipolar resistance memory material sandwiched between a pair of electrodes. The electrodes of the pair are both formed of, e.g., Pt. The unipolar resistance memory material is, e.g., TiOx.

Then, the rest method of the resistance memory element according to the present embodiment, which uses the circuit constitution ofFIG. 4, will be explained.

It is assumed that the resistance memory element10is in the low resistance state.

First, a DC voltage of a voltage value Vgis applied to the gate terminal of the NMOS transistor14. The voltage value Vgsatisfies the relationship of Vreset+Vth≦Vg<Vset+Vthwherein a voltage value necessary to set the resistance memory element10is Vset, a voltage value necessary to reset the resistance memory element10is Vreset, and a threshold voltage value of the NMOS transistor14is Vth. Thus, the value of the gate voltage of the NMOS transistor14is set at Vgwhich satisfies the relationship of Vreset+Vth≦Vg<Vset+Vth. Next, with the DC voltage of the voltage value Vgsatisfying the relationship of Vreset+Vth≦Vg<Vset+Vthbeing applied to the gate terminal of the NMOS transistor14, a pulse voltage of a voltage value Vpulseby the pulse generator12to the drain terminal of the NMOS transistor14. Here, the voltage value Vpulseis equal to or greater than the voltage value Vresetnecessary to reset the resistance memory element10.

To drain terminal of the NMOS transistor14having the value of the gate voltage set at Vgsatisfying the relationship of Vreset+Vth≦Vg<Vset+Vth, the pulse voltage of the voltage value Vpulseequal to or greater than Vresetis thus applied, whereby the pulse voltage is applied to the resistance memory element10connected to the source terminal of the NMOS transistor14. Thus, the resistance value of the resistance memory element10rises, and the resistance memory element10is reset from the low resistance state to the high resistance state.

As described above, the resetting method of the resistance memory element according to the present embodiment is characterized mainly in that the pulse voltage of the voltage value Vpulseequal to or greater than Vresetis applied to the drain terminal of the NMOS transistor14having the value of the gate voltage set at the Vgsatisfying the relationship of Vreset+Vth≦Vg<Vset+Vth, whereby the pulse voltage is applied to the resistance memory element10connected to the source terminal of the NMOS transistor14.

When the pulse voltage of the voltage value Vpulseequal to or greater than Vresetis applied to the drain terminal of the NMOS transistor14by the pulse generator12, the resistance value of the resistance memory element10rises. Accompanying this, the voltage V1applied to the resistance memory element10also rises.

Here, in the resetting method of the resistance memory element according to the present embodiment, the pulse voltage is applied to the resistance memory element10via the NMOS transistor14. Accordingly, the upper limit of the voltage V1applied to the resistance memory element10is determined by a value of the gate voltage of the NMOS transistor14. That is, because the value of the gate voltage of the NMOS transistor14set at Vgsatisfying the relationship of Vreset+Vth≦Vg<Vset+Vth, the voltage V1applied to the resistance memory element10is equal to or greater than Vresetbut never becomes equal to or greater than Vset. Accordingly, when the resistance memory element10is reset from the low resistance state to the high resistance state, the resistance memory element10which has been changed from the low resistance state to the high resistance state can retain the high resistance state without being changed again to the low resistance state.

The resistance memory element10using the resistance memory material of metal oxide takes longer time to be reset than to be set. A period of time in which the resistance memory element10changes the resistance state is shorter as the voltage applied to the resistance memory element10is larger. Accordingly, the period of time necessary for the resistance memory element10to be reset can be shortened by setting the voltage to be applied to the resistance memory element10when the resistance memory element10is reset to be as large as possible in the range of smaller than Vset. To this end, when the resistance memory element10is reset, the gate voltage Vgof the NMOS transistor14may be set to be as large as possible in the range of smaller than Vset+Vth.

FIG. 5is a graph showing the result of measuring the time variation of the voltage V1applied to the resistance memory element in the resetting method of the resistance memory element according to the present embodiment. In the graph, time is taken on the horizontal axis, and the voltage V1applied to the resistance memory element is taken on the vertical axis. The sample used in the measurement was a 5 μm-diameter resistance memory element including a lower electrode of Pt, a 20 nm-thickness resistance memory material layer of TiOxand an upper electrode of Pt. This sample had the current-voltage characteristics shown inFIG. 1, an about 1.8 V set voltage and an about 0.7 V reset voltage. The value Vthof the threshold voltage of the NMOS transistor was about 1.7 V. The value Vgof the DC voltage applied to the gate terminal of the NMOS transistor was 3 V. The voltage value Vpulseof the pulse voltage applied to the drain terminal of the NMOS transistor was 5 V, and the pulse width was 5 ms.

As shown inFIG. 5, the resistance memory element was reset after about 3 ms from the application of the pulse voltage to the drain terminal of the NMOS transistor. Accompanying this, the voltage V1applied to the resistance memory element rose, and then the voltage of 1.3 V was being applied to the resistance memory element until the application of the pulse voltage was finished. This 1.3 V voltage is smaller than the set voltage of the resistance memory element, and the resistance memory element is never set again. Based on this result, it has been confirmed that according to the present embodiment, the resistance memory element can be surely reset from the low resistance state to the high resistance state. The resistance value of the sample after the voltage change measurement ofFIG. 5was measured, and the resistance value of the high resistance state was measured.

As described above, according to the present embodiment, when the resistance memory element is switched from the low resistance state to the high resistance state, the voltage is applied to the resistance memory element via the transistor having the gate voltage set at the prescribed voltage value, whereby the application of an excessive voltage to the resistance memory element is prevented to thereby prevent the resistance memory element from being changed again to the low resistance state.

A SECOND EMBODIMENT

The resetting method of the resistance memory element according to a second embodiment of the present invention will be explained with reference toFIGS. 6 and 7. The same members of the present embodiment as those of the resetting method of the resistance memory element according to the first embodiment are represented by the same reference numbers not to repeat or to simplify their explanation.

First, the circuit constitution for carrying out the resetting method of the resistance memory element according to the present embodiment will be explained with reference toFIG. 6.

As shown, a pulse generator12for applying a pulse voltage is connected to the gate terminal of an NMOS transistor14. To the source terminal of the NMOS transistor14, one end of the resistance memory element10is connected. The other end of the resistance memory element10is connected to a reference voltage, e.g., 0 V, which is the ground voltage.

The resistance memory element10includes a unipolar resistance memory material sandwiched between a pair of electrodes. The electrodes of the pair are formed of, e.g., Pt. The unipolar resistance memory material is, e.g., TiOx.

Then, the resetting method of the resistance memory element according to the present embodiment using the circuit constitution shown inFIG. 6will be explained.

It is assumed that the resistance memory element10is in the low resistance state.

First, a DC voltage of a voltage value Vdis applied to the drain terminal of the NMOS transistor14. Here, the voltage value Vdis equal to or greater than a voltage value Vresetnecessary to reset the resistance memory element10.

Then, with the DC voltage of the voltage value Vdequal to or greater than Vresetbeing applied to the drain terminal of the NMOS transistor14, a pulse voltage of a voltage value Vpulseis applied to the gate terminal of the NMOS transistor14by the pulse generator12. Here, the voltage value Vpulsesatisfies the relationship of Vreset+Vth≦Vpulse<Vset+Vthwherein a voltage value necessary to set the resistance memory element10is Vset, a voltage value necessary to reset the resistance memory element10is Vreset, and a threshold voltage value of the NMOS transistor14is Vth. Thus, the value of the gate voltage of the NMOS transistor14is set at Vpulsewhich satisfies the relationship of Vreset+Vth≦Vpulse<Vset+Vthwhile the pulse voltage is being applied to the gate terminal.

Thus, the pulse voltage is applied to the resistance memory element10connected to the source terminal of the NMOS transistor14by applying the pulse voltage of the voltage value Vpulsesatisfying the relationship of Vreset+Vth≦Vpulse<Vset+Vthto the gate terminal of the NMOS transistor14with the DC voltage of the voltage value Vdequal to or greater than Vresetbeing applied to the drain terminal of the NMOS transistor14. Thus, the resistance value of the resistance memory element10rises, and the resistance memory element10is reset from the low resistance state to the high resistance state.

As described above, the resetting method of the resistance memory element according to the present embodiment is characterized mainly in that with the DC voltage of the voltage value Vdequal to or greater than Vresetbeing applied to the drain terminal of the NMOS transistor14, the pulse voltage of the voltage value Vpulsesatisfying the relationship of Vreset+Vth≦Vpulse<Vset+Vthis applied to the gate terminal of the NMOS transistor14, whereby the pulse voltage is applied to the resistance memory element10connected to the source terminal of the NMOS transistor14.

When the pulse voltage of the voltage value Vpulsesatisfying the relationship of Vreset+Vth≦Vpulse<Vset+Vthis applied to the gate terminal of the NMOS transistor14, the resistance value of the resistance memory element10rises because the DC voltage of the voltage value Vdequal to or greater than Vresetis applied to the drain terminal of the NMOS transistor14. Accompanying this, the voltage V1applied to the resistance memory element10also rises.

In the resetting method of the resistance memory element according to the present embodiment, the pulse voltage is applied to the resistance memory element10via the NMOS transistor14. Accordingly, the upper limit of the voltage V1applied to the resistance memory element10is determined by a value of the gate voltage of the NMOS transistor14. That is, the value of the gate voltage of the NMOS transistor14is set at the Vpulsesatisfying the relationship of Vreset+Vth≦Vpulse<Vset+Vthwhile the pulse voltage is being applied to the gate terminal by the pulse generator12. Accordingly, the voltage V1applied to the resistance memory element10is equal to or greater than Vresetand is smaller than Vset, and never becomes equal to or greater than Vset. Thus, when the resistance memory element10is reset from the low resistance state to the high resistance state, the resistance memory element which has been changed from the low resistance state to the high resistance state can retain the high resistance state without being changed again to the low resistance state.

In the present embodiment as well, in the same way as in the first embodiment, when the resistance memory element10is reset, the gate voltage Vgof the NMOS transistor14is set to be as large as possible in the range of smaller than Vset+Vth, whereby a voltage which is as large as possible in the range of smaller than Vsetcan be applied to the resistance memory element10. Thus, the period of time required for the reset can be shortened.

FIG. 7is a graph showing the result of measuring the time variation of the voltage V1applied to the resistance memory element in the resetting method of the resistance memory element according to the present embodiment. In the graph, time is taken on the horizontal axis, and the voltage V1applied to the resistance memory element is taken on the vertical axis. The resistance memory element, which is the sample used in the measurement, and the NMOS transistor were the same as those used in the first embodiment shown inFIG. 5. The value Vdof the DC voltage applied to the drain terminal of the NMOS transistor was 5 V. The voltage value Vpulseof the pulse voltage applied to the gate terminal of the NMOS transistor was 3 V, and the pulse width was 5 ms.

As shown inFIG. 7, the resistance memory element was reset about 300 μs later from the application of the pulse voltage to the gate terminal of the NMOS transistor. Accompanying this, the voltage V1applied to the resistance memory element rose, and then the voltage of 1.3 V was being applied to the resistance memory element until the application of the pulse voltage was finished. This voltage of 1.3 V is smaller than the set voltage of the resistance memory element, and the resistance memory element is never set again. Based on this result, it has been confirmed that according to the present embodiment, the resistance memory element can be surely reset from the low resistance state to the high resistance state. The resistance value of the sample after the voltage change measurement ofFIG. 7was measured, and the resistance value of the high resistance state was measured.

As described above, according to the present embodiment, when the resistance memory element is switched from the low resistance state to the high resistance state, the voltage is applied to the resistance memory element via the transistor having the gate voltage set at the prescribed voltage value, whereby the application of an excessive voltage to the resistance memory element can be prevented to thereby prevent the resistance memory element from being changed again to the low resistance state.

In the present embodiment, it is possible that the voltage value Vpulseof the pulse voltage applied to the gate terminal of the NMOS transistor14by the pulse generator12is set at a value equal to or greater than Vset+Vthin the initial period of time after the rise of the pulse voltage, i.e., in a prescribed period of time before the resistance memory element10is changed from the low resistance state to the high resistance state and then, in the same was as described above, is set at a value satisfying the relationship of Vreset+Vth≦Vpulse<Vset+Vthbefore the resistance memory element10is changed from the low resistance state to the high resistance state.

The application of such pulse voltage can make the voltage applied to the resistance memory element10sufficiently large before the resistance memory element10is changed from the low resistance state to the high resistance state. Specifically, the voltage value Vdof the DC voltage applied to the drain terminal of the NMOS transistor14is set at a value equal to or greater than Vset, whereby the voltage applied to the resistance memory element10can be equal to or greater than Vset. Thus, the current amount flowing to the resistance memory element10can be sufficiently ensured, and the period of time necessary to resetting the resistance memory element10can be shortened. Hereafter, the voltage applied to the resistance memory element10becomes equal to or greater than Vresetand smaller than Vsetbefore the resistance memory element10is changed from the low resistance state to the high resistance state. Thus, in the same way as described above, the resistance memory element10can be prevented from being changed from the high resistance state again to the low resistance state.

A THIRD EMBODIMENT

The nonvolatile semiconductor memory device and the method of writing into the nonvolatile semiconductor memory device according to a third embodiment of the present invention will be explained with reference toFIGS. 8 to 12D.

The memory cell16of the nonvolatile semiconductor memory device according to the present embodiment includes, as shown inFIG. 8, a resistance memory element18and a cell select transistor20. The resistance memory element18has one end connected to the drain terminal of the cell select transistor20and the other end connected to a source line SL. The cell select transistor20has the source terminal connected to a bit line BL and the gate terminal connected to a word line WL. The resistance memory element18is formed of a unipolar resistance memory material of, e.g., TiOxsandwiched between a pair of electrodes. The cell select transistor20is a MOS transistor whose threshold voltage is, e.g., 0.3-1 V.

FIG. 9is a circuit diagram of the memory cell array of the memory cells16arranged in a matrix. A plurality of the memory cells16are formed adjacent to each other column-wise (vertically in the drawing) and row-wise (transversely in the drawing).

A plurality of word lines WL0, WL1, . . . are arranged column-wise, forming common signal lines for the memory cells16arranged column-wise. Source lines SL0, SL1, . . . are arranged column-wise, forming common signal lines for the memory cells16arranged column-wise.

A plurality of bit lines BL0, BL1, . . . are arranged row-wise (transversely in the drawing), forming common signal lines for the memory cells16arranged row-wise.

Then, the method of writing into the nonvolatile semiconductor memory device according to the present embodiment shown inFIG. 9will be explained with reference toFIGS. 10A-11Dand11A-11D.

First, the rewriting operation from the high resistance state to the low resistance state, i.e., the setting operation will be explained with reference toFIG. 10A-10D. The memory cell16to be rewritten is a memory cell16connected to the word line WL0and the bit line BL0.

First, a prescribed voltage is applied to the word line WL0to turn on the cell select transistor20. At this time, the voltage applied to the word line WL0is controlled to be Vset+Vthwherein a set voltage necessary to set the resistance memory element18is Vset, and a threshold voltage of the cell select transistor20is Vth(FIG. 10A). The gate voltage of the cell select transistor20is thus set at Vset+Vthso that a voltage sufficient to set the resistance memory element18can be applied to the resistance memory element18.

The source line SL0is connected to a reference potential, e.g., 0 V, which is the ground potential.

Next, to the bit line BL0, a voltage Vccwhich is equal to or greater than the voltage Vsetnecessary to set the resistance memory element18is applied (FIG. 10B).

When the voltage is applied to the bit line BL0, a voltage is applied to the resistance memory element18from the bit line BL0via the cell select transistor20having the gate voltage set at Vset+Vth. Accordingly, the voltage V0applied to the resistance memory element18first becomes Vset. This decreases the resistance value of the resistance memory element18and the resistance memory element18is changed from the high resistance state to the low resistance state. Accompanying the decrease of the resistance value of the resistance memory element18, the voltage V0applied to the resistance memory element18decreases from Vset(FIG. 10C). The current flowing in the resistance memory element18increases as the resistance value of the resistance memory element18decreases (FIG. 10D).

Next, the voltage applied to the bit line BL0is returned to zero, and then the voltage applied to the word line WL0is turned off. Thus, the setting operation is completed.

Next, the rewriting operation from the low resistance state to the high resistance state, i.e., the resetting operation will be explained with reference toFIGS. 11A-11D. The memory cell16to be rewritten is a memory cell16connected to the word line WL0and the bit line BL0.

The rewriting operation from the low resistance state to the high resistance state in the present embodiment is made by the resetting method of the resistance memory element according to the first embodiment.

First, a prescribed voltage is applied to the word line WL0to turn on the cell select transistor20. At this time, the voltage VWLapplied to the word line WL0has a value satisfying the relationship of Vreset+Vth≦VWL<Vset+Vthwherein the set voltage necessary to set the resistance memory element18is Vset, a reset voltage necessary to reset the resistance memory element18is Vreset, and the threshold voltage of the cell select transistor20is Vth(FIG. 11A). Thus, the gate voltage Vgof the cell select transistor20is set at a value satisfying the relationship of Vreset+Vth≦Vg<Vset+Vthso that a voltage sufficient to reset the resistance memory element18can be applied to the resistance memory element18, and furthermore, the resistance memory element18cannot be reset even when the resistance value of the resistance memory element18rises.

The source line SL0is connected to a reference potential, e.g., 0 V, which is the ground potential.

Next, to the bit line BL0, a voltage Vccwhich is equal to or greater than the voltage Vresetnecessary to reset the resistance memory element18is applied (FIG. 11B).

When the voltage equal to or greater than Vresetis applied to the bit line BL0, a voltage is applied to the resistance memory element18from the bit line BL0via the cell select transistor20having the gate voltage Vgset at a value satisfying the relationship of Vreset+Vth≦Vg<Vset+Vth. Accordingly, the voltage V0applied to the resistance memory element18has a value equal to or greater than Vresetand smaller than Vset, and never becomes equal to or greater than Vset(FIG. 11C). This increases the resistance value of the resistance memory element18and the resistance memory element18is changed from the low resistance state to the high resistance state.

In the above-described resetting process, the instant the resistance value of the resistance memory element18rises, the current flowing in the resistance memory element18decreases, and the voltage V0applied to the resistance memory element18rises (FIGS. 11C and 11D). However, according to the present embodiment, even when the resistance value of the resistance memory element18rises, the voltage V0applied to the resistance memory element18is kept smaller than Vset, which permits the resistance memory element18which has been changed from the low resistance state to the high resistance state to be retained in the high resistance state without being changed again to the low resistance state.

Then, the voltage to be applied to the bit line BL0is returned to zero, and then the voltage applied to the word line WL0is turned off. Thus, the resetting operation is completed.

Next, the method of reading from the nonvolatile semiconductor memory device according to the present embodiment shown inFIG. 9will be explained with reference toFIG. 12A-12D. The memory cell16to be read is a memory cell16connected to the word line WL0and the bit line BL0.

First, a prescribed voltage is applied to the bit line BL0(FIG. 12B). The voltage Vreadapplied to the bit line BL0is set so that the resistance memory element18in either of the resistance states is not set or reset by the applied voltage.

The source line SL1is connected to a reference potential, e.g., 0 V, which is the ground potential.

Next, a prescribed voltage is applied to the word line WL0to turn on the cell select transistor20(FIG. 12A).

When such voltage is applied to the word line WL0, the voltage Vreadis applied to the resistance memory element18(FIG. 12C), and a current corresponding to the resistance value of the resistance memory element18flows in the bit line BL0(FIG. 12D).

The value of this current flowing in the bit line BL0is detected, whereby in which state of the high resistance state and the low resistance state the resistance memory element18is can be read. That is, whether data held in the memory cell16to be read is “0” or “1” can be read (FIG. 12D).

As described above, according to the present embodiment, when the resistance memory element is switched from the low resistance state to the high resistance state, the voltage is applied to the resistance memory element via the transistor having the gate voltage set at the prescribed voltage value, whereby the resistance memory element is prevented from being changed again to the low resistance state due to the application of an excessive voltage to the resistance memory element. Thus, data can be accurately written in the resistance memory element, and the reliability of the nonvolatile semiconductor memory device using the resistance memory element can be improved.

A FOURTH EMBODIMENT

The nonvolatile semiconductor memory device and the method of writing into the nonvolatile semiconductor memory device according to a fourth embodiment of the present invention will be explained with reference toFIGS. 13A to 14D. The same members of the present embodiment as those of the nonvolatile semiconductor memory device and the method of writing into the nonvolatile semiconductor memory device according to the third embodiment are represented by the same reference numbers not to repeat or to simplify their explanation.

The nonvolatile semiconductor memory device according to the present embodiment is the same as the nonvolatile semiconductor memory device according to the third embodiment shown inFIGS. 8 and 9. The method of writing into the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference toFIGS. 13A-13Dand14A-14D.

First, the rewriting operation from the high resistance state to the low resistance state, i.e., the setting operation will be explained with reference toFIG. 13A-13D. The memory cell16to be rewritten is a memory cell16connected to the word line WL0and the bit line BL0.

First, to the bit line BL0, a voltage Vccwhich is equal to or greater than the voltage Vsetnecessary to set the resistance memory element18is applied (FIG. 13B).

The source line SL0is connected to a reference potential, e.g., 0 V, which is the ground potential.

Next, a prescribed voltage is applied to the word line WL0to turn on the cell select transistor20. At this time, the voltage applied to the word line WL0is controlled to be Vset+Vthwherein a set voltage necessary to set the resistance memory element18is Vset, and a threshold voltage of the cell select transistor20is Vth(FIG. 13A).

When the cell select transistor20is turned on, a voltage is applied from the bit line BL0to the resistance memory element18via the cell select transistor20having the gate voltage set at Vset+Vth. Accordingly, the voltage V0applied to the resistance memory element18first becomes Vset. This decreases the resistance value of the resistance memory element18and the resistance memory element18is changed from the high resistance state to the low resistance state. Accompanying the decrease of the resistance value of the resistance memory element18, the voltage V0applied to the resistance memory element18decreases from the Vset(FIG. 13C). The current flowing in the resistance memory element18increases as the resistance value of the resistance memory element18decreases (FIG. 13D).

Next, the voltage applied to the bit line BL0is returned to zero, and then the voltage applied to the word line WL0is turned off. Thus, the setting operation is completed.

Next, the rewriting operation from the low resistance state to the high resistance state, i.e., the resetting operation will be explained with reference toFIGS. 14A-14D. The memory cell16to be rewritten is a memory cell16connected to the word line WL0and to the bit line BL0.

The rewriting operation from the low resistance state to the high resistance state according to the present embodiment is made by the resetting method of the resistance memory element according to the second embodiment.

First, to the bit line BL0, a voltage Vccwhich is equal to or greater than the voltage Vresetnecessary to reset the resistance memory element18is applied (FIG. 14B).

The source line SL0is connected to a reference potential, e.g., 0 V, which is the ground potential.

Next, a prescribed voltage is applied to the word line WL0to turn on the cell select transistor20. At this time, the voltage VWLapplied to the word line WL0has a value satisfying the relationship of Vreset+Vth≦VWL<Vset+Vthwherein the set voltage necessary to set the resistance memory element18is Vset, the reset voltage necessary to reset the resistance memory element18is Vreset, and the threshold voltage of the cell select transistor20is Vth(FIG. 14A).

When the cell select transistor20is turned on, to the resistance memory element18, a voltage is applied from the bit line BL0via the cell select transistor20having the gate voltage Vgset at a value satisfying the relationship of Vreset+Vth≦Vg<Vset+Vth. Accordingly, the voltage V0applied to the resistance memory element18never has a value equal to or greater than Vresetand smaller than Vset, and never becomes equal to or greater than Vset(FIG. 14C). This increases the resistance value of the resistance memory element18and the resistance memory element18is changed from the low resistance state to the high resistance state.

In the above-described resetting process, the instant the resistance value of the resistance memory element18rises, the current flowing in the resistance memory element18decreases, and the voltage V0applied to the resistance memory element18rises (FIG. 14CandFIG. 14D). However, according to the present embodiment, the voltage V0applied to the resistance memory element18is kept smaller than Vset, which permits the resistance memory element18which has been changed from the low resistance state to the high resistance state to be retained in the high resistance state without being changed again to the low resistance state.

Next, the voltage to be applied to the word line WL0is returned to zero, and then the voltage applied to the bit line BL0is turned off. Thus, the resetting operation is completed.

The method of reading from the nonvolatile semiconductor memory device according to the present embodiment is the same as that of the third embodiment.

As described above, according to the present embodiment, when the resistance memory element is switched from the low resistance state to the high resistance state, the voltage is applied to the resistance memory element via the transistor having the gate voltage set at the prescribed voltage value, whereby the resistance memory element can be prevented from being changed again to the low resistance state due to the application of an excessive voltage to the resistance memory element. Thus, data can be accurately written in the resistance memory element, and the reliability of the nonvolatile semiconductor memory device using the resistance memory element can be improved.

The method of writing into the nonvolatile semiconductor memory device according to a modification of the present embodiment will be explained with reference toFIGS. 15A-15D.FIGS. 15A-15Dare time charts showing the method of writing into the nonvolatile semiconductor memory device according to the present modification.

The method of writing into the nonvolatile semiconductor memory device according to the present modification sets the voltage applied to the word line WL0at a value equal to or greater than Vset+Vthbefore the resistance memory element18is reset from the voltage application start in above-described rewriting operation from the low resistance state to the high resistance state, whereby the period of time necessary to reset the resistance memory element18is shortened.

The rewriting operation from the low resistance state to the high resistance state of the present modification, i.e., the resetting operation will be explained below with reference toFIGS. 15A-15D. The memory cell16to be rewritten is a memory cell16connected to the word line WL0and to the bit line BL0.

First, to the bit line BL0, a voltage Vccwhich is equal to or greater than the voltage Vsetnecessary to set the resistance memory element18is applied (FIG. 15B).

The source line SL0is connected to a reference potential, e.g., 0 V, which is the ground potential.

Then, a prescribed voltage is applied to the word line WL0to turn on the cell select transistor20. At this time, in the present modification, the voltage VWLapplied to the word line WL0is set at a value equal to or greater than Vset+Vthin the initial period of time from the start of the voltage application (the initial period of time after the rise of the pulse voltage), i.e., a prescribed period of time before the resistance memory element18is changed from the low resistance state to the high resistance state and then is set at a value satisfying the relationship Vreset+Vth≦VWL<Vset+Vthas described above before the resistance memory element18is changed from the low resistance state to the high resistance state (FIG. 15A).

Thus, the voltage applied to the resistance memory element18becomes equal to or greater than Vsetbefore the resistance memory element18is changed from the low resistance state to the high resistance state and then becomes equal to or greater than Vresetand smaller than Vsetbefore the resistance memory element18is changed from the low resistance state to the high resistance state (FIG. 15C).

In the present modification, the voltage applied to the resistance memory element18becomes equal to or greater than Vsetbefore the resistance memory element18is changed from the low resistance state to the high resistance state, whereby the current amount flowing to the resistance memory element18can be sufficiently ensured. This allows the period of time necessary for the resistance memory element18to be reset to be shortened.

A FIFTH EMBODIMENT

The nonvolatile semiconductor memory device and the method of manufacturing the nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be explained with reference toFIGS. 16A to 17H.

In the present embodiment, the structure of the nonvolatile semiconductor memory device according to the third embodiment described above and the method for manufacturing the nonvolatile semiconductor memory device will be specifically explained.

First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference toFIGS. 16A and 16B.

As shown inFIG. 16B, a device isolation film24for defining device regions is formed in a silicon substrate22. In the device regions of the silicon substrate22, cell select transistors each including a gate electrode26and source/drain regions28,30are formed.

As shown inFIG. 16A, the gate electrodes26function also as the word lines WL commonly connecting the gate electrodes26of the selective transistors adjacent column-wise (vertically in the drawing).

Over the silicon substrate22with the cell select transistors formed on, an inter-layer insulating film36with contact plugs32electrically connected to the source/drain regions28and contact plugs34electrically connected to the source/drain regions30buried in is formed.

Over the inter-layer insulating film36with the contact plugs32,34buried in, the resistance memory elements44electrically connected to the source/drain regions30via the contact plugs34are formed.

The resistance memory elements44each includes a lower electrode38electrically connected to the contact plug34, a resistance memory material layer40formed on the lower electrode38, and an upper electrode42formed on the resistance memory material layer40.

Over the inter-layer insulating film36with the resistance memory elements44formed over, an inter-layer insulating film50with contact plugs46electrically connected to the contact plugs32, and contact plugs48electrically connected to the upper electrodes42of the resistance memory elements44buried in is formed.

Over the inter-layer insulating film50with the contact plugs46,48buried in, relay interconnections52electrically connected to the contact plugs46, and source lines54electrically connected to the upper electrodes42of the resistance memory elements44via the contact plugs48are formed.

Over the inter-layer insulating film50with the relay interconnections52and the source lines54formed over, an inter-layer insulating film58with contact plugs56electrically connected to the relay interconnections52buried in is formed.

Over the inter-layer insulating film58, the bit lines60are formed, electrically connected to the source/drain regions28via the contact plugs56, the relay interconnections52, the contact plugs46and the contact plugs32buried in the inter-layer insulating film58,50,36.

Thus, the nonvolatile semiconductor memory device according to the third embodiment shown inFIG. 9is constituted.

Next, the method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference toFIGS. 17A to 17H.

First, the device isolation film24for defining the device regions is formed in the silicon substrate22.

Then, in the device regions of the silicon substrate22, the cell select transistors each including the gate electrode26and the source/drain regions28,30are formed in the same way as in the method of manufacturing the usual MOS transistor (FIG. 17A).

Next, over the silicon substrate22with the cell select transistors formed on, a silicon oxide film is deposited by, e.g., CVD method to form the inter-layer insulating film36of the silicon oxide film.

Next, by lithography and dry etching, the contact holes are formed in the inter-layer insulating film36down to the source/drain regions28,30.

Then, a barrier metal and a tungsten film are deposited by, e.g., CVD method, and these conduction films are etched back to form in the inter-layer insulating film36the contact plugs32,34electrically connected to the source/drain regions28,30(FIG. 17B).

Next, over the inter-layer insulating film36with the contact plugs32,34buried in, a Pt film38, a TiOxfilm40and a Pt film42are sequentially formed (FIG. 17C).

Then, by lithography and dry etching, the Pt film38, the TiOxfilm40and the Pt film42are patterned to form the resistance memory elements44each including the lower electrode38of Pt, the resistance memory material layer40of TiOxand the upper electrode42of Pt (FIG. 17D).

Next, over the inter-layer insulating film36with the resistance memory elements44formed over, a silicon oxide film is deposited by, e.g., CVD method to form the inter-layer insulating film50of the silicon oxide film.

Then, by lithography and dry etching, the contact holes down to the contact plugs32and the contact holes down to the upper electrodes42of the resistance memory elements44are formed in the inter-layer insulating film50.

Next, a barrier metal and a tungsten film are deposited by, e.g., CVD method, and these conduction films are etched back to form in the inter-layer insulating film50the contact plugs46electrically connected to the contact plugs32and the contact plugs48electrically connected to the upper electrodes42of the resistance memory elements44(FIG. 17E).

Then, a conduction film is deposited over the inter-layer insulating film50with the contact plugs46,48buried in, and this conduction film is patterned by lithography and dry etching to form the relay interconnections52electrically connected to the contact plugs46and the source lines54electrically connected to the upper electrodes42of the resistance memory elements via the contact plugs48(FIG. 17F).

Next, over the inter-layer insulating film50with the relay interconnections52and the source lines54formed over, a silicon oxide film is deposited by, e.g., CVD method to form the inter-layer insulating film58of the silicon oxide film.

Then, by lithography and dry etching, the contact holes are formed in the inter-layer insulating film58down to the relay interconnections52.

Next, a barrier metal and a tungsten film are deposited by, e.g., CVD method, and these conduction films are etched back to form in the inter-layer insulating film58the contact plugs56electrically connected to the relay interconnections52(FIG. 17G).

Then, a conduction film is deposited over the inter-layer insulating film58with the contact plugs56buried in, and the conduction film is patterned by photolithography and dry etching to form the bit lines60electrically connected to the source/drain regions28via the contact plugs56, the relay interconnections52, the contact plugs46and the contact plugs32(FIG. 17H).

Then, upper interconnection layers are further formed as required, and the nonvolatile semiconductor memory device is completed.

MODIFIED EMBODIMENTS

The present invention is not limited to the above-described embodiments and can cover other various modifications.

For example, in the above-described embodiments, the resistance memory material of the resistance memory elements is TiOxbut is not limited to TiOx. For example, NiOx, etc. are applicable as the resistance memory material.

In the above-described embodiments, the electrodes of the resistance memory elements are formed of Pt, but the constituent material of the electrodes is not limited to Pt.

In the third and the fourth embodiments, a voltage is applied to the resistance memory element via the cell select transistor to thereby make a voltage applied to the resistance memory elements smaller than the set voltage. However, the nonvolatile semiconductor memory device may include, in addition to the cell select transistors, transistors for making a voltage to be applied to the resistance memory elements smaller than the set voltage.