Power supply wiring in a semiconductor memory device

The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

TECHNICAL FIELD

The present disclosure relates generally to the field of power supply wiring in a semiconductor device. More specifically, the present disclosure relates to routing of vias for power supply enhancing wiring.

BACKGROUND

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices have two states, often denoted by a logic “1” or a logic “0.” In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored information in the memory device. To store information, the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor.

Memory devices typically includes power supply lines throughout the device that provide power from a power supply to the venous transistors and other components that are included in the memory. The power supply lines are typically arranged in different metal layers associated with the device. The resistivity of these power supply lines can dissipate power and generate heat as power is transmitted from the power supply. The farther power travels along the power supply lines, the greater this power dissipation and heat generation can be. Additionally, some metal layer have greater resistivity than others. In some cases, lower metal layer have higher resistivity than upper metal layers. Thus, power that is transmitted on power supply lines located in lower metal layers may be more susceptible to dissipation than power that is transmitted on power supply lines that located in upper metal layers.

In order to reduce these power dissipation and heating issues, some memory devices include a redistribution layer that includes low resistivity lines that provide power to certain locations within the device. This layer may be referred to as an “iRDL layer” and may be formed in a semiconductor process that occurs before an assembly process. An iRDL layer may be an uppermost layer of the device, which may be the lowest resistivity layer in the device. In some cases, an iRDL layer is a metal 4 layer (M4) over the metal 3 layer (M3).

In order for power to be transferred from the iRDL layer to lower layers of a memory device, the memory device may include one or more vias, also known as contact plugs. A memory device may include one or more “iRDL vias” that provide conductive pathways between power distribution lines in the iRDL layer (“iRDL lines”) to wiring that is this located in an underlying metal layer. In one example, an iRDL via provides a conductive pathway between a metal 4 layer and a metal 3 layer. The memory device may also include additional vias that provide conductive pathways between other layers, such as M3-M2 vias.

Conventionally, a memory device includes a dedicated area for routing of iRDL vias. These dedicated areas are used to avoid interference with control signals or other wiring that may be present in areas that underlie the redistribution layer. These dedicated areas result in unwanted increases in chip size, power consumption and other disadvantages. Thus, there is a need in the art for improved iRDL via routing.

DETAILED DESCRIPTION

Embodiments of the present disclosure avoid conventional arrangements that include a dedicated iRDL layout region. Instead of using a dedicated region, present embodiments route iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. In some embodiments, an iRDL via is routed above a memory MAT that is located at an edge of a memory bank. As used herein, a “memory MAT” generally refers to a subunit of the memory bank having a plurality of memory cells. In other embodiments, iRDL vias may be routed above both an edge MAT and an adjacent column decoder. In other embodiments, iRDL vias may be routed above adjacent memory MATs.

Overview of Memory Architecture

FIG. 1is a schematic illustration of a portion of a memory100according to an embodiment of the present disclosure. The memory100includes an array104of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other type of memory cells. The memory100may be generally configured to operate in cooperation with a larger digital system that includes at least a processor configured to communicate with the memory100. In the present description, “external” refers to signals and operations outside of the memory100, and “internal” refers to signals and operations within the memory100. As an illustrative example, the memory100may be coupled to a microprocessor that provides external commands and clock signals to the memory100. Although examples in the present description are directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.

The memory100may be generally configured to execute read and/or write commands received from an external device. Read commands provide data stored in the array104to the external device across a data bus108. Write co ands receive data from the external device across the data bus108and store the data in the memory array104. The following discussion generally references read commands by way of example and not limitation. In processing a read command, the memory100receives an input clock signal CLK and generates an internal clock that synchronizes internal signals so as to provide output data on the data bus108with appropriate timing. Here, the memory device100uses a delay-locked loop112to synchronize internal signals including generating a data strobe signal114. The data strobe signal114is provided as output to the external controller and is asserted at a time when the requested read data is available on the data bus108for capture by the external controller.

The memory system100includes a command decoder116that receives memory commands through a command bus120. The command decoder116responds to memory commands applied to the command bus120by generating corresponding control signal to perform various operations on the memory array104. For example, the command decoder116may generate internal control signals to read data from and/or write data to the memory array104. Row and column address signals associated with a particular command are applied to the memory100through an address bus124. The address bus124provides the row and column address signals to an address register128. The address register128then outputs a separate column address and a separate row address to the memory array104.

As can be seen inFIG. 1, row and column addresses may be provided by the address register128to a row address decoder132and a column address decoder136, respectively. The column address decoder128selects bit lines extending through the array104corresponding to respective column addresses. The row address decoder132includes or is coupled to a word line driver or similar component that activates respective rows of memory cells in the array104corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry140to provide read data to a data output buffer or similar component via an input-output data bus108. Write data is applied to the memory array104through a data input buffer or similar component and the memory array read/write circuitry140.

The timing of signals external to the memory100may be determined by the external clock signal CLK. Operations within the memory100are typically synchronized to external operations. The delay-locked loop112is generally configured to receive the external clock signal CLK and generate a synchronized internal clock signal. The synchronized internal clock signal generated by the delay-locked look112may be provided to various internal memory components in order to facilitate the latching of command, address, and data signals in accordance with the external clock CLK. For example, data output may be placed on the data bus104of the memory100in synchronism with the external clock signal CLK so that the memory device100outputs data in a manner that allows the data to be captured by the external controller. To output data with proper timing, the delay-locked loop112develops an internal clock signal in response to the external clock signal and applies the internal clock signal to latches contained in the memory device100to clock data. The internal clock signal and external clock CLK are synchronized to ensure internal clock signal clocks the latches at the proper times to successfully capture the commands.

FIG. 2is a schematic diagram that illustrates an example layout for a semiconductor memory device200in accordance with the present disclosure. The semiconductor device200ofFIG. 2may correspond to the memory device ofFIG. 1. Certain components that are illustrated inFIG. 1are omitted fromFIG. 2in order to simply the drawing.FIG. 2includes a memory area204and a peripheral circuit area208. The memory area204may include a plurality of memory banks, which may correspond to the memory banks104illustrated inFIG. 1. The memory area204ofFIG. 2includes eight memory banks B0-B7, by way of example and not limitation. Among the memory banks B0to B7associated with the memory area204, the even memory banks (B0, B2, B4, B6), which are half of the memory banks, are arranged in this order along an X-direction in a left half of the semiconductor chip in a Y-direction. The odd memory banks (B1, B3, B5, B7), which are the remaining half of the memory banks are arranged in this order along the X-direction in a right half of the semiconductor chip in the Y-direction.

The memory area204may be operatively coupled to various circuit components that are provided within the peripheral circuit area208. The peripheral circuit area208may be positioned to one side of the memory area204in the Y-direction. The peripheral circuit area208may be a first pad area that is arranged along an edge of a semiconductor chip. Although not specifically shown inFIG. 2, memory array200may also be associated with a second peripheral circuit area that includes another pad area arranged along another edge of the semiconductor chip. The second peripheral circuit area may be arranged on an opposite side from the first peripheral circuit area208. It should be appreciated that semiconductor devices having pad areas located at chip edges are shown and described herein by way of example and not limitation. Implementations consistent with the present disclosure may use alternative configurations. For example, in some implementations, a pad area may be provided at or near a center or midline of a semiconductor chip.

The peripheral circuit area208may include one or more power generator blocks212, one or more DQ pad blocks216, one or more column address blocks220, and/or other components that are not specifically shown inFIG. 2. The DQ pad blocks216may include an input receiver that receives an address input via an address pin and an address latch circuit that latches the address. The DQ pad blocks216may also include an output buffer that outputs read data to a data I/O pin and/or an input receiver that receives write data supplied via the data I/O pin. The column address block220may include a column address decoder that selects bit lines extending through the memory area204corresponding to respective column addresses. A column address decoder of the column address block220may correspond to the column address decoder128ofFIG. 1. The power generator block212may include a power source that supplies power to various circuit and components associated with the memory200. The power generator block220may be provided in association with one or more transmission lines or other power distribution lines that supply power from the power distribution block208to the various components.

Each of the memory banks B0-B7provided in the memory area204includes a plurality of memory cells organized into a plurality of memory MATs. A “memory MAT” generally refers to a subunit of the memory bank. The memory area204additionally includes one or more supporting components such as a row decoder (XDEC)224provided adjacently to one side of each of the memory banks B0to B7in the X-direction. Column decoders (YDEC)228and main amplifiers (DSA)232may be provided adjacently to a side of the memory area204in the Y-direction.

The row decoder224is a circuit that drives a plurality of word lines to select particular memory cells within the memory area204based on a row address. The row decoder224may be configured to drive one or more main word lines (MWL)236, to which row decoders224may be directly coupled. For purposes of illustration, one main word line236is shown inFIG. 2. Although not shown inFIG. 2, the various main word lines236may be coupled to sub-word lines (SWL) that are arranged within the various memory MATs associated with the memory banks B0-B7. As described in greater detail below, this coupling may occur through various components that connect the main word lines236to the sub-word lines arranged within the various memory MATs.

The column decoder228is a circuit that selects a plurality of sense amplifiers contained in the memory cell area204on the basis of the column address. The column decoders228are coupled to the column address decoder220, which may correspond to the column address decoder of136ofFIG. 1. The column decoders228are configured to select a given plurality of sense amplifiers by driving column select (CS)240lines.FIG. 2includes one column select line240by way of example and not limitation. The selected sense amplifiers are connected to the main amplifiers232via a global input/output lines (GIO)244. The main amplifiers232are configured to transfer data between the DQ pads216and the adjacent memory bank B0-B7. The main amplifiers232are coupled to adjacent memory banks through the global input/output lines244. The main amplifiers232are coupled to the DQ pads216through a global bus (GBUS)248.FIG. 2includes two global input/output lines244and one global bus248by way of by way of example and not limitation.

FIG. 3is a schematic diagram that illustrates the configuration of an example memory bank300. The example memory bank ofFIG. 3may correspond to one of the memory banks B0-B7illustrated inFIG. 2. The memory bank300may include a column decoder (YDEC)304and a main amplifier (DSA)308. The column decoder304may correspond to the column decoder228ofFIG. 2. The main amplifier308may correspond to the main amplifier232ofFIG. 2. The memory bank300may include a plurality of memory mats MAT312a-n(collectively memory MATs312) arranged along the Y-direction. An adjacent circuit area316may be provided adjacent to the memory mats MAT312in the X-direction. The adjacent circuit area316may include a number of supporting components that are described in greater detail in connection withFIG. 4. A sense amplifier area (SAA)320may be provided between two memory MATs312that are adjacent to each other in the Y-direction.

The sense amplifier area320may include a plurality of sense amplifiers324.FIG. 3shows one sense amplifier324by way of example and not limitation. In some embodiments as shown inFIG. 3, a sense amplifier324may be coupled to a pair of bit lines BLT and BLB. A memory device in accordance with the present disclosure having such a configuration may be understood as having an open bit-line structure or architecture. Here, bit lines BLT and BLB included in a bit line pair connected to one sense amplifier324may be arranged in different memory mats MAT (that is, two memory mats MAT that are adjacent to each other in the Y-direction), respectively.

Memory MAT312aand memory MAT312n, which positioned in the Y-direction end portions, are so-called end mats. The memory mats MAT312aand MAT312nonly have half the number of bit lines of the other memory mats MATb to MATm. Therefore, even though N memory mats are arranged in the Y-direction, the capacity value is that of N−1 mats. As for both the end mats MAT312aand MAT312n, a sense amplifier area320is provided only on one Y-direction side. Therefore, the number of bit lines BL provided is one-half of the number of bit lines of a normal memory mat (e.g. MAT312b) in which sense amplifier areas320are provided on both sides.

A sense amplifier324amplifies a potential difference generated in pairs of the bit lines BLT and BLB. Read data amplified by the sense amplifier324is transferred to local input/output lines LIO (described below in connection withFIG. 4), and then further transferred to the global input/output lines (GIO)328. A main amplifier308may be coupled to sense amplifiers324in the sense amplifier area320via the global input-output lines328and components coupled to the global input/output lines328. As shown inFIG. 2, a main amplifier232may couple global input/output lines244to a global bus248, which, in turn, couples to a DQ pad216.

FIG. 3shows that a global input/output lines328may be laid out in the Y-direction over one or more of the memory MATs312and over one or more of the sense amplifier areas320. A number of global input/output lines328extending in the Y-direction may be provided in parallel to each other and may be connected to the main amplifier308. Although not specifically shown inFIG. 3, local input/output lines may extend in the X-direction, perpendicular to the global input/output lines328that extend in the Y-direction. The coupling between and among local input/output lines, sense amplifiers324, and global input/output lines328may be understood with reference toFIG. 4.

FIG. 4is a schematic diagram that illustrates a data path400that provides for transfer of data between an individual memory cell (MC)404and a DQ pad408. The memory cell404may be one of a plurality of memory cells that are arranged in a grid pattern within a memory MAT412. The memory MAT412may correspond to one of the memory MATs312that are illustrated inFIG. 3. As shown inFIG. 4, the memory mat412is an area in which sub-word lines (SWL)416and bit lines (BT)420extend. In a memory MAT412, memory cells404are arranged at respective intersections of sub-word lines416extending in the X-direction and bit lines420extending in the Y-direction. A memory cell404may have a configuration in which a cell transistor and a cell capacitor are connected in series between a corresponding one of the bit lines420and a plate wiring (such as a pre-charge line). The cell transistor may include an n-channel MOS transistor, and a gate electrode thereof may be connected to a corresponding one of the sub-word lines416.

A sub-word line416associated with the memory mat412may be driven by a sub-word driver (SWD)424.FIG. 4includes one sub-word driver424by way of example and not limitation. Each of the sub-word drivers424drive a corresponding one of the sub-word lines416according to the row address. As described above in connection withFIG. 2andFIG. 3, the row address is provided by a row decoder XDEC, which drives the row address onto main word lines (MWL). The sub-word drivers424provide a coupling between the main word lines (MWL) and the sub-word lines (SWL) and in so doing drive sub-word lines416with appropriate signals responsive to the row address provided by the row decoder (XDEC). One or more sub-word drivers424may be located in the adjacent circuit area316, which is illustrated inFIG. 3.FIG. 2shows an example main word line236, which provides input to one or more sub-word drivers424.

The data path400shown inFIG. 4additionally includes an example local input/output line (LIO)428and an example global input/output line (GIO)432. The local input/output lines428and the global input/output lines432are hierarchically structured input/output lines. The local input/output line428is used for transferring read data out from a memory cell404and/or write data to the memory cell404. The local input/output line428may be differential data input/output lines for transferring read data and write data by using a pair of lines. The global input/output lines432are used for transferring data between the main amplifier (DSA)436and the various memory MATs of a particular memory bank, which memory bank includes the memory MAT412shown inFIG. 4. Thus, the global input/output lines432are used for transferring data from the memory bank to the main amplifier436and transferring write data from the main amplifier436to the memory bank. The global input/output lines432may also be differential data input/output lines for transferring read data and write data by using a pair of lines.

The data path400shown inFIG. 4illustrates various components that are proximate to the memory MAT412and that facilitate transfer of data between the memory cell404and the local input/output line428. A sense amplifier440is coupled to the memory cell404via the bit line420. The sense amplifier440is configured to transfer data between the bit line420and the local input/output lines428via a column switch (YSW)444. The column switch444may be driven by a column select CS line (FIG. 2) that enables a particular sense amplifier440to transfer its data onto the local input output lines428. The local input lines428are received as input at a sub-amplifier (Sub Amp)448. The sub-amplifier448is generally configured to transfer data between the local input/output lines428and the global input/output lines432. One or more column switches444may be located in the sense amplifier area320, which is illustrated inFIG. 3. One or more sub-amplifiers448may be located in the adjacent circuit area316, which is illustrated inFIG. 3.

Redistribution Layer

Referring again toFIG. 2, a memory device200in accordance with the present disclosure may include a power generator block220that provides power to various components located in the memory area204of the memory device200. In this regard, the power generator blocks220may be provided in association with one or more transmission lines or other power distribution lines that supply power to the various memory device200components. One example of such a power distribution line is the iRDL line. As used herein, “iRDL” refers a redistribution layer formed in a semiconductor process before assembly process. In some cases, an iRDL line is in a metal 4 layer (M4) over a metal 3 layer (M3). An iRDL line may be provided in an uppermost layer, which may be the lowest resistivity layer in the device. An example of such an iRDL line is illustrated inFIG. 5.

FIG. 5is a schematic diagram that illustrates an example layout for a memory device500in accordance with the present disclosure. The memory device500ofFIG. 5may correspond to the memory device ofFIG. 2. Thus, the memory device500includes memory area504and a peripheral circuit508area. The memory area504may include a plurality of memory banks B0-B7, where a left side of the memory area504includes even-numbered memory banks (B0, B2, B4, B6) and a right side of the memory area504includes odd-numbered (B1, B3, B5, B7) memory banks. The peripheral circuit508area may include various circuit components such as one or more power generators512, one or more DQ pads516, and/or one or more column address blocks520. Within the memory area504, the memory device additionally includes row decoders (XDEC)524that drive main word lines) (MWL)536, column decoders (YDEC)528that drive column select (CS) lines540, and main amplifiers (DSA)532that provide coupling between global input/output lines (GIO)544and global buses (GBUS)548.

In order to reduce power dissipation and heating issues associated with power distribution, the memory device may include a redistribution layer that includes low resistivity lines that provide power to certain locations within the device. This layer may be referred to as an “iRDL layer” and may contain “iRDL lines.” The iRDL layer be formed in a semiconductor process that occurs before an assembly process. An iRDL layer may be an uppermost layer of the device, which may be the lowest resistivity layer in the device. In some cases, an iRDL layer is a metal 4 layer (M4) over the metal 3 layer (M3). The memory device500ofFIG. 5includes example iRDL lines502that are coupled to the power generator blocks520.FIG. 5show two iRDL lines502by way of example and not limitation. It should be appreciated a memory device500in accordance with the present disclosure may include more or less iRDL lines502depending on the implementation.

In order for power from the iRDL lines502to be provided to various memory device500components, the memory device500may include one or more vias that provide conductive pathways between various layers of the memory device500. Continuing with the example above where the iRDL lines are routed in a metal 4 layer, the memory device500may include one or more M4-M3 vias that provide a conductive pathways between the metal 4 layer and a metal 3 layer. Using the one or more M4-M3 vias, power may be, provided from the iRDL lines502to components in the metal 3 layer. In some cases, the metal 3 layer may contain a network of power distribution lines that distribute power to various points in the memory device500. Components that consume the power provided by this power distribution network may have power input couplings that are located in lower device layers, such as a metal 2 layer (M2). Thus, a memory device500may additionally include M3-M2 vias that provide a conductive pathways between the metal 3 layer and the metal 2 layer.

In determining locations for vias between layers of the memory device500, consideration is given to the location of other components that are located in, the various device layers. For example, the metal 3 layer may include wiring that implements various signal lines such as the input/output lines (GIO)544, global buses (GBUS)548, and/or various control signal lines for components such as the column decoder528, the main amplifier532, and so on. Thus, an M4-M3 via that provides a conductive pathway between the metal 4 layer and the metal 3 layer may be placed in an area of the memory device500that is otherwise free of signal wirings in the metal 3 layer. Such an M4 M3 via may provide a coupling between the iRDL lines502and a network of power distribution lines that distribute power to various points in the memory device500. This power distribution network may also couple to power lines or couplings that are located in the metal 2 layer. Accordingly, the memory device500may also include M3-M2 vias that may or may not be located proximate to the M4-M3 vias. In determining locations for the M3-M2 vias, consideration is given to the location of other wiring and components in the metal 2 layer. One example of a wiring that may be present in the metal 2 layer is the main word lines (MWL)536that are driven by the row decoders (XDEC)524.

Conventionally, a memory device includes a dedicated area for routing of iRDL vias. These dedicated areas are used to avoid interference with control signals or other wiring that may be present in areas that underlie the redistribution layer. These dedicated areas result in unwanted increases in chip size, power consumption and other disadvantages. Embodiments of the present disclosure avoid conventional arrangements that include a dedicated iRDL layout region. In this regard, present embodiments may route iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. Continuing with the example above where the iRDL layer is routed in a metal 4 layer, a memory device in accordance with present embodiments may include one or more M4-M3 vias that provides conductive pathways between iRDL lines and a power distribution network that is located at least partially in the metal 3 layer. The memory device may additionally include one or M3-M2 vias that further distribute power to lower layers of the power distribution network.

iRDL Vias Over Edge MATs

FIG. 5provides a first example of a memory device500in accordance with the present disclosure that routes iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. More specifically, the memory, device500ofFIG. 5routes iRDL vias above an edge MAT. As discussed in connection withFIG. 3, a memory mat MAT that is positioned at one end of a column of memory MATs is referred to as an “edge MAT.” An edge MAT typically has half the memory capacity as it is typically associated with only one sense amplifier area (SSA).FIG. 3shows a plurality of memory MATs312a-n, including a first edge MAT312aand a second edge MAT312n. The first edge MAT312ais the closest edge MAT to the main amplifier308. The second edge MAT312nis the farthest edge MAT from the main amplifier308.FIG. 3also shows global input/output lines328that are laid out in the Y-direction over one or more of the memory MATs312and over one or more of the sense amplifier areas320. As can be seen inFIG. 3, the global input/output lines328extend over all of the memory MATS except for the second edge MAT312nthat is farthest from the main amplifier308. It is this area, the area over the edge MAT farthest from the main amplifier (DSA), that an iRDL via may be routed in accordance with an embodiment of the present disclosure.

InFIG. 5, iRDL routing areas located in the even number memory banks (B0, B2, B4, B6) are generally indicated with reference number552. An iRDL routing area552generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier532associated with the memory bank to which the edge MAT belongs. As can be seen inFIG. 5(and more particularly inFIG. 3), global input/output lines544are not located in this iRDL routing area552. Because the iRDL routing area552lacks global input/output lines544or other metal 3 layer wiring at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area552. The routing of these one or more iRDL vias may be understood with reference toFIG. 6which includes an enlarged view of an iRDL routing area552.

FIG. 6is a plan view schematic diagram of an iRDL routing area600. The iRDL routing area600may correspond to the iRDL routing area552ofFIG. 5. The iRDL routing area600includes a sense amplifier area604and edge MAT608. Global bus lines612extend in the Y-direction across both the sense amplifier area604and the edge MAT608. Control signals616, such as for a column decoder (YDEC) and/or a main amplifier (DSA), extend in the Y-direction across both the sense amplifier area604and the edge MAT608. Global input/output (GIO) lines620extend in the Y-direction, but end at the sense amplifier area604such that they do not extend into the edge MAT608area. Main word lines (MWL)624extend across the edge MAT608in the X-direction. The global bus lines612, the control signal lines616, and the global input/output lines620may be routed in a metal 3 layer. The main word lines624may be routed in a metal 2 layer.

FIG. 6additionally includes iRDL lines628a-dthat extend in the Y-direction across both the sense amplifier area604and the edge MAT608.FIG. 6includes four iRDL lines628a-d(collectively iRDL lines628) by way of example and not limitation. As discussed in connection withFIG. 5, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines628ofFIG. 6include two outer iRDL lines628a,dand two inner iRDL lines628b,c. The iRDL lines628may be routed in a metal 4 layer.

The iRDL lines828may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL, line (M4 in one example). In order for power to be provided from the iRDL lines628to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias)632may provide coupling between the iRDL lines628and portions of the power distribution network that are boated in the metal 3 layer. In the embodiment ofFIG. 6, the iRDL vias632are located above the edge MAT608in areas that lack global input/output lines620or other M3 wiring. As shown inFIG. 6, the area above the edge MAT608and below the two outer iRDL, lines628a,dlacks global input/output lines620or other M3 wiring, while the area above the edge MAT608and below the two inner iRDL lines628b,cincludes M3 wiring such as the global bus lines612and the control signal lines616. Thus, in the embodiment ofFIG. 6, the iRDL vias632are located in the area above the edge MAT608and below the two outer iRDL lines628a,d.

As shown inFIG. 6, the iRDL vias632may be coupled to power distribution nodes636that are coupled to various power distribution wires. First power distribution wires640may be located in the metal 3 layer. First power distribution wires640may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory MAT604, as well as to memory banks that are adjacent in the X-direction. Second power distribution wires644may be located in the metal 2 layer. The second power distribution wires644may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires640to components that are located adjacently in the Y-direction. For example, the second power distribution wires644may transmit power from the first power distribution wires640to sense amplifiers are that located in the sense amplifier area604.

The power distribution network ofFIG. 6may additionally include M3-M2 vias that provide conductive pathways between components and wires in the metal 3 layer and the metal 2 layer. A first group of M3-M2 vias648provide a conductive pathway between the distribution nodes636and the first power distribution wires640.FIG. 6shows M3-M2 vias648between the distribution nodes636and particular first power distribution wires640by way of example and not limitation. In alternative embodiments, M3-M2 vias648may be provided between the distribution nodes636and any of the first power distribution wires640shown inFIG. 6. Possible M3-M2 vias648routing locations are generally indicated inFIG. 6by enclosed areas652. A second group of M3-M2 vias656provide a conductive pathway between the first power distribution wires640and the second distribution wires644. A third group of M3-M2 vias660provide a conductive pathway between the second distribution wires644and components in the sense amplifier area604.

FIG. 7is a cross-sectional view of the iRDL routing area600ofFIG. 6. The cross section700ofFIG. 6is taken with respect to the A-A line shown inFIG. 6.FIG. 7is given to provide a greater understanding of the relationship between the components discussed inFIG. 6.FIG. 7includes a cross-sectional view of the sense amplifier area604and the edge MAT608.FIG. 7also shows a portion of a full memory MAT704that is located on the opposite side of the sense amplifier area604from that of the edge MAT608. Additionally,FIG. 7includes cross-sectional portions of an outer iRDL line628a, a power distribution node636, first power distribution wires640, second power distribution wires644, global bus lines612, global input/output lines620, and main word lines624. It should be noted that the second power distribution wires644and global bus lines612are generally configured to run in the Y-direction, but the cross-sectional view ofFIG. 7captures a small portion of those lines that run in the X-direction. As show inFIG. 7, the iRDL line628ais routed in the metal 4 layer. The power distribution node636, the second power distribution wires644, the global bus lines612, and the global input/output lines620are routed in the metal 3 layer. The first power distribution wires640and the main word lines624are routed in the metal 2 layer.FIG. 7also shows an iRDL via632that couples the iRDL line628ato the power distribution node636and a first M3-M2 via648that couples the distribution node636to a first power distribution wire640. The second and third groups of M3-M2656,660are outside of the A-A cross section and thus not shown inFIG. 7.

Referring again toFIG. 5, the memory device500additionally includes iRDL routing areas located in odd numbered memory banks (B1, B3, B5, B7). iRDL routing areas located in the odd number memory banks (B1, B3, B5, B7) are generally indicated with reference number556. An iRDL routing area556generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier532associated with the memory bank to which the edge MAT belongs. As can be seen inFIG. 5(and more particularly inFIG. 3), global input/output lines544are not located in this iRDL routing area556. Additionally, global bus lines548are not located in this iRDL routing area556. Because the iRDL routing area556lacks global input/output lines544, global bus lines548or other metal 3 layer lines at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area556. The routing of these one or more iRDL vias may be understood with reference toFIG. 8which includes an enlarged view of an iRDL routing area556.

FIG. 8is a plan view schematic diagram of an iRDL routing area800. The iRDL routing area800may correspond to an iRDL routing area556ofFIG. 5The iRDL routing area800includes a sense amplifier area804and edge MAT808. Control signals816, such as for a column decoder (YDEC) and/or a main amplifier (DSA), extend in the Y-direction across both the sense amplifier area804and the edge MAT808. Global input/output (GIO) lines820extend in the Y-direction, but end at the sense amplifier area804such that they do not extend into the edge MAT808. Main word lines (MWL)824extend across the edge MAT808in the X-direction. The control signal lines816, and the global input/output lines820may be routed in a metal 3 layer. The main word lines824may be routed in a metal 2 layer.

FIG. 8additionally includes iRDL lines828a-dthat extend in the Y-direction across both the sense amplifier area804and the edge MAT808.FIG. 8includes four iRDL lines828a-d(collectively iRDL lines828) by way of example and not limitation. As discussed in connection withFIG. 5, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines828ofFIG. 8include two outer iRDL lines828a,dand two inner iRDL lines828b,c. The iRDL lines828may be routed in a metal 4 layer.

The iRDL lines828may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines828to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias)832may provide coupling between the iRDL lines828and portions of the power distribution network that are located in the metal 3 layer, in the embodiment ofFIG. 8, the iRDL vias832are located above the edge MAT808in areas that lack global input/output lines820or other M3 wiring. As shown inFIG. 8, the area above the edge MAT808and below the two outer iRDL lines828a,dlacks global input/output lines820or other M3 wiring. Additionally, the area above the edge MAT808and below one inner iRDL lines828balso lacks global input/output lines820or other M3 wiring, while the area above the edge MAT808and below other inner iRDL lines828cincludes M3 wiring such as the control signal lines816. Thus, in the embodiment ofFIG. 8, the iRDL vias832are located in the areas above the edge MAT808and below the two outer iRDL lines828a,dand the above the edge MAT808and below one inner iRDL lines828b.

As shown inFIG. 8, the iRDL vias832may be coupled to power distribution nodes836that are coupled to various power distribution wires. First power distribution wires840may be located in the metal 3 layer. First power distribution wires840may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory mat804, as well as to memory banks that are adjacent in the X-direction. Second power distribution wires844may be located in the metal 2 layer. The second power distribution wires844may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires840to components that are located adjacently in the Y-direction. For example, the second power distribution wires844may transmit power from the first power distribution wires840to sense amplifiers are that located in the sense amplifier area804.

The power distribution network ofFIG. 8may additionally M3-M2 vias that provide conductive pathways between components and wires in the metal 3 layer and the metal 2 layer. A first group of M3-M2 vias848provide a conductive pathway between the distribution nodes838and the first power distribution wires840.FIG. 8shows M3-M2 vias848between the distribution nodes836and particular first power distribution wires840by way of example and not limitation. In alternative embodiments, M3-M2 vias848may be provided between the distribution nodes836and any of the first power distribution wires840shown inFIG. 8. Possible M3-M2 vias848routing locations are generally indicated inFIG. 8by enclosed areas852. A second group of M3-M2 vias856provide a conductive pathway between the first power distribution wires840and the second distribution wires844. A third group of M3-M2 vias860provide a conductive pathway between the second distribution wires844and components in the sense amplifier area804.

iRDL Vias Over Edge MATs and Column Decoders

FIG. 9provides a second example of a memory device900in accordance with the present disclosure that routes iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. More specifically, the memory device900ofFIG. 5routes iRDL vias above both an edge MAT and a column decoder (YDEC).

FIG. 9is a schematic diagram that illustrates an example layout for a memory device900in accordance with the present disclosure. The memory device900ofFIG. 9may correspond to the memory device ofFIG. 2. Thus, the memory device900includes memory area904and a peripheral circuit908area. The memory area904may include a plurality of memory banks B0-B7, where a left side of the memory area904includes even-numbered memory banks (B0, B2, B4, B6) and a right side of the memory area904includes odd-numbered (B1, B3, B5, B7) memory banks. The peripheral circuit908area may include various circuit components such as one or more power generators912, one or more DQ pads916, and/or one or more column address blocks920. Within the memory area904, the memory device additionally includes row decoders (XDEC)924that drive main word lines (MWL)936, column decoders (YDEC)928that drive column select (CS) lines940, and main amplifiers (DSA)932that provide coupling between global input/output lines (GIO)944and global buses (GBUS)948.

The memory device900ofFIG. 9additionally includes example iRDL lines902that are coupled to the power generator blocks920.FIG. 9show two iRDL lines902by way of example and not limitation. It should be appreciated a memory device900in accordance with the present disclosure may include more or less iRDL lines902depending on the implementation. The iRDL lines902are generally configured to distribute power to various points within the memory area904. The memory device900includes iRDL routing areas962located in the even number memory banks (B0, B2, B4, B6). An iRDL routing area952generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier932associated with the memory bank to which the edge MAT belongs. An iRDL routing area952additionally includes the column decoder928that is adjacent to the edge MAT. As can be seen inFIG. 9(and more particularly inFIG. 3), global input/output lines944are not located in this iRDL routing area952. Because the iRDL routing area952lacks global input/output lines944or other metal 3 layer at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area952. The routing of these one or more iRDL vias may be understood with reference toFIG. 10which includes an enlarged view of an iRDL routing area952.

FIG. 10is a plan view schematic diagram of an iRDL routing area1000. The iRDL routing area1000may correspond to the iRDL routing area952ofFIG. 9The iRDL routing area1000includes a sense amplifier area1004, edge MAT1008, and column decoder1010. Global bus lines1012extend in the Y-direction across the sense amplifier area1004, the edge MAT1008, and the column decoder1010. Control signals1016, such as for the column decoder1010and/or a main amplifier (DSA), extend in the Y-direction across the sense amplifier area1004, the edge MAT1008, and the column decoder1010. Global input/output (GIO) lines1020extend in the Y-direction, but end at the sense amplifier area1004such that they do not extend into the edge MAT1008or into the column decoder1010. Main word lines (MWL)1024extend across the edge MAT1008in the X-direction. The global bus lines1012, the control signal lines1016, and the global input/output lines1020may be routed in a metal 3 layer. The main word lines1024may be routed in a metal 2 layer.

FIG. 10additionally includes iRDL lines1028a-dthat extend in the Y-direction across the sense amplifier area1004, the edge MAT1008, and the column decoder1010.FIG. 10includes four iRDL lines1028a-d(collectively lines1028) by way of example and not limitation. As discussed in connection withFIG. 9, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines1028ofFIG. 10include two outer iRDL lines1028a,dand two inner iRDL lines1028b,c. The iRDL lines1028may be routed in a metal 4 layer.

The iRDL lines1028may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines1028to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias)1032may provide coupling between the iRDL lines1028and portions of the power distribution network that are located in the metal 3 layer. In the embodiment ofFIG. 10, the iRDL vias1032are located above the edge MAT1008and the column decoder1010in areas that lack global input/output lines1020or other M3 wiring. As shown inFIG. 10, the area above the edge MAT1008and the column decoder1010and below the two outer iRDL lines1028a,dlacks global input/output lines1020or other M3 wiring, while the area above the edge MAT1008and the column decoder1010and below the two inner iRDL lines1028b,cincludes M3 wiring such as the global bus lines1012and the control signal lines1016. Thus, in the embodiment ofFIG. 10, the iRDL vias1032are located in the area above the edge MAT1008and the column decoder1010and below the two outer iRDL lines1028a,d.

As shown inFIG. 10, the iRDL visa1032may be coupled to power distribution nodes1036that are coupled to various power distribution wires. First power distribution wires1040may be located in the metal 3 layer. First power distribution wires1040may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory mat1004, as well as to memory banks that are adjacent in the X-direction. Second power distribution wires1044may be located in the metal 2 layer. The second power distribution wires1044may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires1040to components that are located adjacently in the Y-direction. For example, the second power distribution wires1044may transmit power from the first power distribution wires1040to sense amplifiers are that located in the sense amplifier area1004.

The power distribution network ofFIG. 10may additionally M3-M2 vias that provide conductive pathways between components and wires in the metal 3 layer and the metal 2 layer. A first group of M3-M2 vias1048provide a conductive pathway between the power distribution nodes1036and the first power distribution wires1040.FIG. 10shows M3-M2 vias1048between the distribution nodes1036and particular first power distribution wires1040by way of example and not limitation. In alternative embodiments, M3-M2 vias1048may be provided between the distribution nodes1036and any of the first power distribution wires1040shown inFIG. 10. Possible M3-M2 vias1048routing locations are generally indicated inFIG. 10by enclosed areas1052. A second group of M3-M2 vias1056provide a conductive pathway between the first power distribution wires1040and the second distribution wires1044. A third group of M3-M2 vias1060provide a conductive pathway between the second distribution wires1044and components in the sense amplifier area1004.

Referring again toFIG. 9, the memory device900additionally includes iRDL routing areas located in odd numbered memory banks (B1, B3, B5, B7). iRDL routing areas located in the odd number memory banks (B1, B3, B5, B7) are generally indicated with reference number956. An iRDL routing area956generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier932associated with the memory bank to which the edge MAT belongs. An iRDL routing area956additionally includes the column decoder928that is adjacent to edge MAT. As can be seen inFIG. 9(and more particularly inFIG. 3), global input/output lines944are not located in this iRDL routing area952. Additionally, global bus lines948are not located in this iRDL routing area956. Because the iRDL, routing area956lacks global input/output lines944, global bus lines948or other metal 3 layer at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area956. The routing of these one or more iRDL vias may be understood with reference toFIG. 11which includes an enlarged view of an iRDL routing area956.

FIG. 11is a plan view schematic diagram of an iRDL routing area1100. The iRDL routing area1100may correspond to the iRDL routing area956ofFIG. 9The iRDL routing area1100includes a sense amplifier area1104, edge MAT1108, and column decoder1110. Control signals1116, such as for the column decoder1110and/or a main amplifier (DSA), extend in the Y-direction across the sense amplifier area1104, the edge MAT1108, and the column decoder1110. Global input/output (GIO) lines1120extend in the Y-direction, but end at the sense amplifier area1104such that they do not extend into the edge MAT1108or into the column decoder1110. Main word lines (MWL)1124extend across the edge MAT1108in the X-direction. The control signal lines1116and the global input/output lines1120may be routed in a metal 3 layer. The main word lines1124may be routed in a metal 2 layer.

FIG. 11additionally includes iRDL lines1128a-d, that extend in the Y-direction across the sense amplifier area1104, the edge MAT1108, and the column decoder1110.FIG. 11includes four iRDL lines1128a-d(collectively, iRDL lines1128) by way of example and not limitation. As discussed in connection withFIG. 9, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines1128ofFIG. 11include two outer iRDL lines1128a,dand two inner iRDL lines1128b,c. The iRDL lines1128may be routed in a metal 4 layer.

The iRDL tines1128may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines1128to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias)1132may provide coupling between the iRDL lines1128and portions of the power distribution network that are located in the metal 3 layer. In the embodiment ofFIG. 10, the iRDL vias1132are located above the edge MAT1108and the column decoder1110in areas that lack global input/output lines1120or other M3 wiring. As shown inFIG. 11, the area above the edge MAT1108and the column decoder1110and below the two outer iRDL lines1128a,dlacks global input/output lines1120or other M3 wiring. Additionally, the area above the edge MAT1108and the column decoder and below one inner iRDL line1128balso lacks global input/output lines1120or other M3 wiring, while the area above the edge MAT1108and the and the column decoder1110and below the other inner iRDL line1128cincludes M3 wiring such as the control signal lines1116. Thus, in the embodiment ofFIG. 11, the iRDL vias1132are located in the areas above the edge MAT1108and the column decoder1110and below the two outer iRDL lines1128a,dand above the edge MAT1108and the column decoder1110and below the one inner iRDL line1128b.

As shown inFIG. 11, the iRDL vias1132may be coupled to power distribution nodes1136that are coupled to various power distribution wires. First power distribution wires1140may be located in the metal 3 layer. First power distribution wires1140may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory mat1104, as well as to memory banks that adjacent in the X-direction. Second power distribution wires1144may be located in the metal 2 layer. The second power distribution wires1144may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires1140to components that are located adjacently in the Y-direction. For example, the second power distribution wires1144may transmit power from the first power distribution wires1140to sense amplifiers that are located in the sense amplifier area1104.

The power distribution network ofFIG. 11may additionally include M3-M2 vias that provide conductive pathways between components and wires in the metal 3 layer and the metal 2 layer. A first group of M3-M2 vias1148provide a conductive pathway between the power distribution nodes1136and the first power distribution wires1140.FIG. 11shows M3-M2 vias1148between the distribution nodes1136and particular first power distribution wires1140by way of example and not limitation. In alternative embodiments, M3-M2 vias1148may be provided between the distribution nodes1136and any of the first power distribution wires1140shown inFIG. 11. Possible M3-M2 vias1148routing locations a generally indicated inFIG. 11by enclosed areas1152. A second group of M3-M2 vias1156provide a conductive pathway between the first power distribution wires1140and the second distribution wires1144. A third group of M3-M2 vias1160provide a conductive pathway between the second distribution wires1144and components in the sense amplifier area1104.

iRDL Vias Over Adjacent Edge MATs

FIG. 12provides a third example of a memory device1200in accordance with the present disclosure that routes iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. More specifically, the memory device1200ofFIG. 12routes iRDL vias above two adjacent edge MATs that face each other.

FIG. 12is a schematic diagram that illustrates an example layout for a memory device1200in accordance with the present disclosure. The memory device1200ofFIG. 12is an alternative configuration with some similarities to the memory device200ofFIG. 2. Thus, the memory device1200includes memory area1204and a peripheral circuit1208area. The memory area1204may include a plurality of memory banks, three of which are shown in the figure by way of example and limitation. The peripheral circuit1208area may include various circuit components such as one or more power generators, one or more DQ pads, and/or one or more column address blocks. The various components that may be included in the peripheral circuit1208area are omitted from the drawing in order to simply the figure. Within the memory area1204, the memory device additionally includes row decoders (XDEC)1224, column decoders (YDEC)1228, and main amplifiers (DSA)1232that provide coupling between global input/output lines (GIO)1244and global buses (GBUS). Global buses are also mitted from the omitted from the drawing in order to simply the figure.

The memory device1200includes iRDL, routing areas1252located above two adjacent edge MATs that face each other. An iRDL routing area1252generally corresponds to two edge MATs that face each other and that are located halfway between two main amplifiers1232associated with the memory bank to which the edge MATs belongs. As can be seen inFIG. 12, global input/output lines1244are not located in this iRDL routing area1252. Because the iRDL routing area1252lacks global input/output lines1244or other metal 3 layer at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area1252. The routing of these one or more iRDL vias may be understood with reference toFIG. 13which includes an enlarged view of an iRDL routing area1252.

FIG. 13is a plan view schematic diagram of an iRDL routing area1300. The iRDL routing area1300may correspond to the iRDL routing area1252ofFIG. 12. The iRDL routing area1300includes a sense amplifier areas1304and two edge MATs1308that face each other. Global bus lines1312extend in the Y-direction across the sense amplifier areas1304and the edge MATs1308Control signals, such as for a column decoder (YDEC) and/or a main amplifier (DSA), may also extend in the Y-direction across the sense amplifier areas1304and the edge MATs1308. Global input/output (GIO) lines1320extend in the Y-direction, but end at the sense amplifier areas1304such that they do not extend into the edge MATs1308. Main word lines (MWL)1324extend across the edges MAT1308in the X-direction. The global bus lines1312and the global input/output lines1320may be routed in a metal 3 layer. The main word lines1324may be routed in a metal 2 layer.

FIG. 13additionally includes iRDL lines1328a-dthat extend in the Y-direction across the sense amplifier areas1304and the edge MATs1308.FIG. 13includes four iRDL lines1328a-d(collectively iRDL lines1328) by way of example and not limitation. An iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines1328ofFIG. 13include two outer iRDL lines1328a,dand two inner iRDL lines1028b,c. The iRDL lines1328may be routed in a metal 4 layer.

The iRDL lines1328may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines1328to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias)1332may provide coupling between the iRDL lines1328and portions of the power distribution network that are located in the metal 3 layer. In the embodiment ofFIG. 13, the iRDL vias1332are located above the edge MATs1308in areas that lack global input/output lines1320or other M3 wiring. As shown inFIG. 13, the area above the edges MAT1308and below the two outer iRDL lines1328a,dlacks global input/output lines1320or other M3 wiring, while the area above the edge MAT1308and below the two inner iRDL lines1328b,cincludes M3 wiring such as the global bus lines1312. Thus, in the embodiment ofFIG. 13, the iRDL vias1332are located in the area above the edges MAT1308and below the two outer iRDL lines1328a,d.

As shown inFIG. 13, the iRDL vias1332may be coupled to power distribution nodes1336that may be coupled to various power distribution wires. The power distribution nodes1336, power distribution wires and related components may correspond to similar components described above in connection withFIGS. 6, 8, 10, and 11.

The foregoing description has broad application. The discussion of any embodiment is meant only to be explanatory and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples. In other words, while illustrative embodiments of the disclosure have been described in detail herein, the inventive concepts may be otherwise variously embodied and employed, and the appended claims are intended to be construed to include such variations, except as limited by the prior art.