Testing device and a circuit arrangement

A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

TECHNICAL FIELD

Various embodiments relate to a testing device and a circuit arrangement.

BACKGROUND

The number of devices-under-test (DUTs) that may be tested in parallel may depend on the hardware of the test equipment (e.g. a tester). It may be desirable to increase the number of DUTs that may be tested in parallel, which may, for example, decrease test time and/or test cost.

SUMMARY

A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test (DUTs), wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective DUT of the plurality of DUTs; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each DUT of the plurality of DUTs through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practised. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Various embodiments are described for structures or devices, and various embodiments are described for methods. It may be understood that one or more (e.g. all) embodiments described in connection with structures or devices may be equally applicable to the methods, and vice versa.

The terms “coupled” and/or “electrically coupled” and/or “connected” and/or “electrically connected”, used herein to describe a feature being connected to at least one other implied feature, are not meant to mean that the feature and the at least one other implied feature must be directly coupled or connected together; intervening features may be provided between the feature and at least one other implied feature.

Directional terminology, such as e.g. “upper”, “lower”, “top”, “bottom”, “left-hand”, “right-hand”, etc., may be used with reference to the orientation of figure(s) being described. Because components of the figure(s) may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that structural or logical changes may be made without departing from the scope of the invention.

Circuit testers may be provided to test the functionality of chips (or dies) and/or components prior to the insertion or installation of the chips (or dies) and/or components in an assembly, such as, for example, soldering on a printed circuit board. If any malfunction of a chip (or die) and/or component were only detectable on the board level (e.g. by a board tester), there may be a need to discard and/or reject the complete board, or at least the need for costly measures would arise, such as, for example, removal of the defective chip and/or component. Thus, testers may ensure that defective chips and/or components are detected in an early stage of assembly. This aspect may become more important with increasing integration, e.g., increasing package density of chips and/or components. Chips and/or components that are individually tested may be referred to as devices-under-test (DUTs).

Parallel testing, namely, testing more than one chip and/or component simultaneously may be a factor in order to save test time and/or test costs. To achieve this, each DUT to be tested may be connected with separate sources of the tester, and the required number of components may be provided to the tester hardware.

FIG. 1shows a block diagram including a tester112and a plurality of DUTs108a,108b,108c, in which parallel testing may be performed.

As shown inFIG. 1, the plurality of DUTs108a,108b,108cmay be connected to the tester112. The tester112may include a plurality of test pins112a,112b. At least one test pin of the plurality of test pins112a,112bmay be configured to provide a test signal114afor testing the plurality of DUTs108a,108b,108c. For example, test pins112amay be configured as output pins of the tester112, and may provide the test signal114ato each DUT of the plurality of DUTs108a,108b,108c. At least one test pin of the plurality of test pins112a,112bmay be configured to receive a test response signal114bfrom each DUT of the plurality of DUTs108a,108b,108c. For example, test pins112bmay be configured as input pins of the tester112, and may receive the test response signal114bfrom each DUT of the plurality of DUTs108a,108b,108c.

It may be seen inFIG. 1that the number of DUTs108a,108b,108cwhich may be tested in parallel may be limited by the resources of the tester112(e.g. the number of test pins112aof the tester112that are configured to provide the test signal114aand/or the number of test pins112bof the tester112that are configured to receive the test response signal114band/or the number of test signal sources in the tester112). In other words, the number of DUTs108a,108b,108cthat may be tested in parallel may depend on the number of sources and/or measurement channels (e.g test pins) included in the tester112. In addition, the number of DUTs108a,108b,108cthat may be tested in parallel may depend on the space available on the hardware of the tester112. Accordingly, it may be desirable to remove the dependency of the number of DUTs108a,108b,108cthat may be tested in parallel on the resources of the tester112. In other words, it may be desirable to increase the number of DUTs which may be tested in parallel, without having to redesign the tester112.

FIG. 2shows a block diagram of a testing device200according to various embodiments.

The testing device200shown inFIG. 2may be used to increase the number of DUTs which may be tested in parallel. Stated in another way, the testing device200may increase the number of DUTs that may be tested in parallel. For example, using the testing device200, the number of DUTs which may be tested in parallel may be greater than or equal to about 2, e.g. greater than or equal to about 5, e.g. greater than or equal to about 10, e.g. greater than or equal to about 30, e.g. greater than or equal to about 50, e.g. greater than or equal to about 100, e.g. greater than or equal to about 200, e.g. greater than or equal to about 500, e.g. greater than or equal to about 800, e.g. greater than or equal to about 1000, e.g. greater than or equal to about 1500, e.g. greater than or equal to about 2000, although other numbers may be possible as well in accordance with other embodiments. The manner in which the testing device200may increase the number of DUTs which may be tested in parallel is described below.

The testing device200may include a plurality of first terminals202a,202b,202c; a signal interface204; and circuit206.

The word “circuit” is used herein to mean any kind of a logic implementing entity, which may be special purpose circuit or processor executing software stored in a memory, firmware, or any combination thereof. Thus, in one or more examples, a “circuit” may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A “circuit” may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Different circuits can thus also be implemented by the same component, e.g. by a processor executing two different programs.

Only three first terminals202a,202b,202care shown as an example, however the number of first terminals202a,202b,202cmay be greater than three, and may, for example, be four, five, six, seven, eight, nine, or on the order of tens, hundreds, thousands of, or even more first terminals202a,202b,202cin some embodiments.

In one or more embodiments, the plurality of first terminals202a,202b,202cmay be configured to be connected to a plurality of DUTs208a,208b,208c. Only three DUTs208a,208b,208care shown as an example, however the number of DUTs may be greater than three, and may, for example, be four, five, six, seven, eight, nine, or on the order of tens, hundreds, thousands of, or even more DUTs in some embodiments.

In one or more embodiments, each first terminal of the plurality of first terminals202a,202b,202cmay be configured to be connected to a respective DUT of the plurality of DUTs208a,208b,208c. For example, as shown inFIG. 2, the first terminal202amay be configured to be connected to the DUT208a; the first terminal202bmay be configured to be connected to the DUT208b; and the first terminal202cmay be configured to be connected to the DUT208c. Stated differently, a respective first terminal of the plurality of first terminals202a,202b,202cmay be configured to be connected to a respective DUT of the plurality of DUTs208a,208b,208c. In one or more embodiments, each first terminal of the plurality of first terminals202a,202b,202cmay be configured to be connected to a different DUT of the plurality of DUTs208a,208b,208c.

In one or more embodiments, the respective first terminal may be configured to be connected to a respective pin of the respective DUT. For example, as shown inFIG. 2, the respective first terminal202amay be configured to be connected to a respective pin210aof the respective DUT208a. In like manner, the respective first terminal202bmay be configured to be connected to a respective pin210bof the respective DUT208b; and the respective first terminal202cmay be configured to be connected to a respective pin210cof the respective DUT208c.

In one or more embodiments, the respective pins210a,210b,210cof the respective DUTs208a,208b,208cmay be configured to provide the same (technical) function (e.g. for an identical technical use) in each respective DUT208a,208b,208c. In other words, the respective pins210a,210b,210cmay fulfill an identical function in the respective DUTs208a,208b,208c. For example, the respective pins210a,210b,210cmay each be configured as a non-inverting signal input for the respective DUTs208a,208b,208c. By way of another example, the respective pins210a,210b,210cmay each be configured as a power supply input for the respective DUTs208a,208b,208c. By way of yet another example, the respective pins210a,210b, and210cmay each be configured as a signal output for the respective DUTs208a,208b,208c. In one or more embodiments, the respective DUTs208a,208b,208cmay be identical to each other. Accordingly, the respective pins210a,210b,210cmay have labelled with the same name in each of the respective DUTs208a,208b,208c. For example, each of the respective pins210a,210b,210cmay be labelled as an “IN” pin in each of the respective DUTs208a,208b,208c(for example, shown inFIG. 5andFIG. 6).

Testing the plurality of DUTs208a,208b,208cmay include providing at least one signal to and/or receiving at least one signal from each DUT of the plurality of DUTs208a,208b,208c. In other words, testing the plurality of DUTs208a,208b,208cmay include the testing device200exchanging a signal with (e.g. providing a signal to and/or receiving a signal from) the plurality of DUTs208a,208b,208cthrough the plurality of first terminals202a,202b,202c.

In one or more embodiments, the circuit206of the testing device200may be configured to exchange an identical first signal214a,214b,214cwith each DUT of the plurality of DUTs208a,208b,208c. It is to be noted that the term “exchange” include, for example, a transmitting/receiving of a respective signal as well as e.g. a forcing, measuring or monitoring of a respective signal. The identical first signal214a,214b,214cmay be exchanged with each DUT of the plurality of DUTs208a,208b,208cvia (in other words through) the respective first terminal. For example, as shown inFIG. 2, the circuit206may exchange the first signal214awith the DUT208avia (in other words through) the respective first terminal202a. In like manner, the circuit206may exchange the first signal214b(which may be identical to the first signal214a) with the DUT208bthrough the respective first terminal202b; and the circuit206may exchange the first signal214c(which may be identical to the first signal214a) with the DUT208cthrough the respective first terminal202c. Therefore, in contrast toFIG. 1in which the tester112exchanges different types of signals (e.g. a test signal114aand a response signal114b) with the plurality of DUTs, the circuit206of the testing device200exchanges an identical signal with each DUT of the plurality of DUTs208a,208b,208c.

In one or more embodiments, the signal interface204of the testing device200may be configured to be connected to a tester212. In one or more embodiments, the circuit206may be configured to exchange at least one interface signal216with the tester212through the signal interface204. In one or more embodiments, the at least one interface signal216may in addition be provided to an additional logic circuit, e.g. one or more programmable logic circuits (such as e.g. one or more processores, e.g. one or more Personal Computers (PC), or one or more Application Specific Integrated Circuits (ASICs), or one or more Field Programmable Gate Arrays (FPGAs). In one or more embodiments, the identical first signal214a,214b,214cexchanged with each DUT of the plurality of DUTs208a,208b,208cmay depend on the at least one interface signal216exchanged with the tester212through the signal interface204. For example, the identical first signal214a,214b,214cexchanged with each DUT of the plurality of DUTs208a,208b,208cmay be a replication of the at least one interface signal216. In one or more embodiments, the converse may be true, namely, the at least one interface signal216exchanged with the tester212through the signal interface204may depend on the identical first signal214a,214b,214cexchanged with each DUT of the plurality of DUTs208a,208b,208c. For example, the at least one interface signal216may contain information about the identical first signal214a,214b,214c.

The tester212may include, or may be, an integrated circuit (IC) test system. The tester212may be configured to provide at least one signal to and/or receive at least one signal from one or more devices external to the tester212(e.g. the testing device200and/or the plurality of DUTs208a,208b,208c). In other words, the tester212may exchange at least one signal (e.g. the at least one interface signal216) with one or more devices external to the tester212(e.g. the testing device200and/or the plurality of DUTs208a,208b,208c). The tester212may include hardware and/or software that may be capable of generating the at least one signal (e.g. the at least one interface signal216) exchanged with the one or more devices external to the tester212.

The tester212may be capable of analyzing a response signal from one or more devices external to the tester212. The response signal may be a response by the one or more devices external to the tester212to at least one signal exchanged with these one or more devices external to the tester212. For example, the tester212may be capable of analyzing a response signal from the plurality of DUTs208a,208b,208c, wherein the response signal may be a response by the plurality of DUTs208a,208b,208cto the identical first signal214a,214b,214cprovided to the plurality of DUTs208a,208b,208cby, for example, the testing device200. Accordingly, at least one signal may be exchanged between the tester212and the plurality of DUTs208a,208b,208cvia the testing device200. In other words, the testing device200may mediate an exchange of signals and/or data between the tester212and the plurality of DUTs208a,208b,208c. Accordingly, the testing device200may be configured to send at least one signal (e.g. the at least one interface signal216) to and/or receive at least one signal (e.g. the at least one interface signal216) from the tester212. Similarly, the testing device200may be configured to send at least one signal (e.g. the identical first signal214a,214b,214c) to and/or receive at least one signal (e.g. the identical first signal214a,214b,214c) from the plurality of DUTs208a,208b,208c. The identical first signal214a,214b,214cexchanged between the testing device200and the plurality of DUTs208a,208b,208cmay, for example, be controlled by the tester212(e.g. by means of a controller, which may be included in the tester212).

As seen inFIG. 2, an aspect of the testing device200may be that the degree of parallelism no longer depends on the number of the sources and measuring channels provided by the tester212, and may, instead, depend on the testing device200. The testing device200may be implemented by means of an integrated chip (IC). One IC may also include a plurality of testing units200.

FIG. 3shows a block diagram of a circuit arrangement301according to various embodiments.

Reference signs inFIG. 3that are the same as inFIG. 2denote the same or similar elements as inFIG. 2. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 3andFIG. 2are described below.

In one or more embodiments, the circuit arrangement301may include a plurality of testing devices200-T,200-R; a plurality of DUTs208a,208b,208c,208d,208e; and a tester212.

Only two testing devices200-T,200-R are shown as an example, however the number of testing devices may be greater than two, and may, for example, be three, four, five, six, seven, eight, nine, or on the order of tens, hundreds, thousands of, or even more testing devices in some embodiments.

In like manner, only five DUTs208a,208b,208c,208d,208eare shown as an example, however the number of DUTs may be less than five (e.g. two, three, four) or may be greater than five, and may, for example, be six, seven, eight, nine, or on the order of tens, hundreds, thousands of, or even more DUTs in some embodiments.

In one or more embodiments, at least one testing device of the plurality of testing devices200-T,200-R may be used to provide an identical first signal to the plurality of DUTs208a,208b,208c,208d,208e. For example, inFIG. 3, the testing device200-T may be used to provide an identical first signal214-T to the plurality of DUTs208a,208b,208c,208d,208e. The identical first signal214-T may be provided to each DUT of the plurality of DUTs208a,208b,208c,208d,208ethrough a plurality of first terminals202-T. Each first terminal of the plurality of first terminals202-T may be connected to a respective DUT of the plurality of DUTs208a,208b,208c,208d,208e, as shown inFIG. 3.

In one or more embodiments, at least one testing device of the plurality of testing devices200-T,200-R, may be used to receive an identical first signal from the plurality of DUTs208a,208b,208c,208d,208e. For example, inFIG. 3, the testing device200-R may be used to receive an identical first signal214-R from the plurality of DUTs208a,208b,208c,208d,208e. The identical first signal214-R may be received from each DUT of the plurality of DUTs208a,208b,208c,208d,208ethrough a plurality of first terminals202-R. Each first terminal of the plurality of first terminals202-R may be connected to a respective DUT of the plurality of DUTs208a,208b,208c,208d,208e, as shown inFIG. 3.

In one or more embodiments, the plurality of testing devices200-T,200-R may be configured to exchange at least one interface signal216-T,216-R with the tester212. For example, the testing device200-T may be configured to exchange the at least one interface signal216-T with the tester212through the signal interface of the testing device200-T. In like manner, the testing device200-R may be configured to exchange the at least one interface signal216-R with the tester212through the signal interface of the testing device200-R. In one or more embodiments, a testing device of the plurality of testing devices200-T,200-R may be coupled (e.g. communicatively and/or electrically coupled) to at least one other testing device of the plurality of testing devices200-T,200-R. In one or more embodiments, the plurality of testing devices200-T,200-R may, for example, be connected together in sequence or in a ring (e.g. in a daisy chain). For instance, in the example shown inFIG. 3, the testing devices200-T and200-R may be coupled (e.g. communicatively and/or electrically coupled) to each other by means of a connection230. The connection230may include, or may be, a serial communications connection, e.g. a serial peripheral interface (SPI) communications connection, although other communications connections may be possible as well.

The circuit arrangement301shown inFIG. 3may be used to test the plurality of DUTs208a,208b,208c,208d,208e. For example, the testing device200-T may be used to provide identical test signals to each DUT of the plurality of DUTs208a,208b,208c,208d,208e, whilst the testing device200-R may be used to receive test response signals from each DUT of the plurality of DUTs208a,208b,208c,208d,208e. The test response signals may be the response of each DUT of the plurality of DUTs208a,208b,208c,208d,208eto the identical test signal provided to the plurality of DUTs208a,208b,208c,208d,208eby the testing device200-T.

Testing each DUT of the plurality of DUTs208a,208b,208c,208d,208emay require the tester212to determine and/or calculate the rise timing and/or fall timing and/or delay time and/or slew rate of each DUT of the plurality of DUTs208a,208b,208c,208d,208e. Testing of each DUT of the plurality of DUTs208a,208b,208c,208d,208emay require the tester212to determine and/or calculate other parameters as well. Therefore, the aforementioned timings and slew rates are merely examples, and not meant to be limiting.

In one or more embodiments, there may be a need for the plurality of testing devices200-T,200-R to be synchronized to the tester212. Therefore, in one or more embodiments, the at least one interface signal216-T,216-R, may include a synchronization signal configured to synchronize each testing device of the plurality of testing devices200-T,200-R with the tester212. Accordingly, the circuit of each testing device of the plurality of testing devices200-T,200-R may be configured to receive the synchronization signal from the tester212through its respective signal interface. In one or more embodiments, the synchronization signal may be further configured to synchronize the plurality of testing devices200-T,200-R with each other. Accordingly, any subsequent determination and/or calculation by the tester212of the rise timing and/or fall timing and/or delay time and/or slew rate of each DUT of the plurality of DUTs208a,208b,208c,208d,208emay be made with respect to a common time scale. In other words, timings for signals exchanged by the plurality of testing devices200-T,200-R and the tester212with the plurality of DUTs208a,208b,208c,208d,208emay share a common start time, i.e. a common t=0 point.

FIG. 4shows a detailed block diagram of a testing device400including a tester212according to various embodiments.

Reference signs inFIG. 4that are the same as inFIG. 2denote the same or similar elements as inFIG. 2. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 4andFIG. 2are described below.

In one or more embodiments, the testing device400shown inFIG. 4may be configured to provide identical first signals to each DUT of a plurality of DUTs (e.g. the testing device200-T shown inFIG. 3). In one or more embodiments, the testing device400shown inFIG. 4may be configured to receive identical first from each DUT of a plurality of DUTs (e.g. the testing device200-R shown inFIG. 3). The testing device400according to each of these embodiments are described below, beginning with embodiments in which the identical first signal is provided by the circuit206of the testing device400to each DUT of the plurality of DUTs.

In one or more embodiments, the circuit206of the testing device400may be configured to provide the identical first signal to each DUT of a plurality of DUTs through the respective first terminal202a,202b,202c. Only one circuit206is shown as an example, however, the number of circuits206may, for example, be two or more circuits206in some embodiments.

Only three first terminals202a,202b,202care shown as an example, however the number of first terminals202a,202b,202cmay be two or may be greater than three, and may, for example, be four, five, six, seven, eight, nine, or on the order of tens, hundreds, thousands of, or even more first terminals202a,202b,202cin some embodiments.

The identical first signal provided by the testing device400through the respective first terminal202a,202b,202cmay depend on a reference signal420that may be known to the circuit206. In one or more embodiments, the reference signal420known to the circuit206may be provided to the circuit by the tester212(as shown inFIG. 4). Therefore, in one or more embodiments, the at least one interface signal216exchanged with the tester212may include, or may be, the reference signal420, as shown inFIG. 4. Accordingly, the circuit206may be configured to receive the reference signal420from the tester212, as shown inFIG. 4. Stated differently, the reference signal420may be provided to the circuit206by the tester212through a signal interface (not shown inFIG. 4).

In one or more embodiments, the reference signal420known to the circuit206may be pre-programmed into the circuit206. For example, the circuit206may include a memory424(also indicated as “MEM” inFIG. 4). The memory424may store the reference signal420programmed into the circuit206of the testing device400.

In one or more embodiments, the identical first signal provided to each DUT may be a replication of the reference signal420. Accordingly, in one or more embodiments, the circuit206may include at least one signal replicator426configured to replicate the reference signal420to form the identical first signal exchanged with each DUT of the plurality of DUTs through the respective first terminal202a,202b,202c.FIG. 4shows only one output of the at least one signal replicator426, namely, the output to the first terminal202a. However, there may be other outputs of the at least one signal replicator426, each connecting to the other first terminals202b,202c.

In one or more embodiments, the identical first signal provided to each DUT may include, or may be, an identical test signal for testing each DUT of the plurality of DUTs. In other words, the identical test signal may be provided to each DUT of the plurality of DUTs as, or as part of, the identical first signal. Accordingly, the reference signal420known to the circuit206may include, or may be, a reference test signal for testing each DUT of the plurality of DUTs.

In one or more embodiments, the identical test signal provided to each DUT of the plurality of DUTs may include, or may be, at least one of an ascending ramp test signal, a descending ramp test signal, a step test signal, a trapezoidal test signal, and a plateau test signal, although other test signals may be possible as well in accordance with other embodiments.

In one or more embodiments, the testing device400may be configured to monitor the identical first signal provided to each DUT of the plurality of DUTs. Accordingly, in one or more embodiments, the circuit206may include at least one measurement device428configured to measure at least one of a voltage and a current of the identical first signal. For example, the circuit206may include at least one shunt resistor and/or a current shunt configured to measure the voltage and/or current of the identical first signal, as shown inFIG. 4. The testing device400may monitor the identical first signal provided to each DUT of the plurality of DUTs as part of the testing of each DUT of the plurality of DUTs. This is described below with respect toFIG. 5andFIG. 6.

In one or more embodiments, monitoring the identical first signal provided to each DUT of the plurality of DUTs through a respective first terminal202a,202b,202cmay include comparing the voltage and/or current of the identical first signal with at least one signal reference430(also indicated as Uref inFIG. 4). In one or more embodiments, the at least one signal reference430may be provided to the circuit206. For example, the at least one interface signal216may include the at least one signal reference430, as shown inFIG. 4. Accordingly, the circuit206may be configured to receive the at least one signal reference430from the tester through the signal interface. In one or more embodiments, the at least one signal reference may be pre-programmed into the circuit206of the testing device400. The at least one signal reference programmed into the circuit206is indicated as signal reference432inFIG. 4(also indicated as Iref inFIG. 4).

In one or more embodiments, comparing the voltage and/or current of the identical first signal214a,214b,214cwith the at least one signal reference430,432may be performed, for example, by means of at least one comparator434. In other words, the circuit206may include at least one comparator434configured to compare at least one of the voltage and the current of the identical first signal with the at least one signal reference430,432.

In one or more embodiments, the circuit206may include at least one voltage supply436configured to provide power to the circuit206. For example, the at least one voltage supply436may supply a power supply potential to at least one of the at least one comparator434and the at least one measurement428. In one or more embodiments, the power supply potential may include, or may be, at least one of a digital voltage and an analog voltage.

In one or more embodiments, the at least one voltage supply436may receive at least one power supply input436a. The at least one power supply input436amay, for example, be provided to the at least one voltage supply436by the tester212. In one or more embodiments, the interface signal216may include the at least one power supply input436a, as shown inFIG. 4.

In one or more embodiments, the testing device400may provide a power supply potential to each DUT of the plurality of DUTs, e.g. by means of the first terminals202a,202b,202c. For example, in one or more embodiments, a respective first terminal202a,202b,202cmay be configured to be connected to a respective DUT of the plurality of DUTs, and a power supply potential may be provided to each DUT of the plurality of DUTs by means of a respective first terminal202a,202b,202c.

In addition to the above, in one or more embodiments, the circuit may include a variable, transient voltage source and/or a controllable current source440.

In one or more embodiments, an input signal442to the variable transient voltage source and/or a controllable current source440may be provided by the tester212. Accordingly, in one or more embodiments, the interface signal216may include, or may be, the input signal442to the variable transient voltage source and/or a controllable current source440.

In one or more embodiments, the circuit206may include an internal ground potential444(also indicated as “Internal GND” inFIG. 4). The internal ground potential444may be a digital ground signal and/or an analog ground signal. The value of the internal ground potential444may depend on whether the plurality of first terminals202a,202b,202care providing the identical first signal or receiving the identical first signal. Accordingly, the internal ground potential444may include a sensing ground signal444a(also indicated as “GND S” inFIG. 4) configured to be used when the plurality of first terminals202a,202b,202care receiving the identical first signal. In like manner, the internal ground potential444may include a forcing ground signal444b(also indicated as “GND F” inFIG. 4) configured to be used when the plurality of first terminals202a,202b,202care providing the identical first signal.

In one or more embodiments, the circuit206may be configured to store at least one trigger time. The at least one trigger time may be defined as a time at which the voltage and/or the current of the identical first signal is at least substantially equal to at least one signal reference430,432provided to the circuit206(e.g. by means of the at least one interface signal216and/or by pre-programming).

In one or more embodiments, the memory424may store the at least one trigger time. For example, in one or more embodiments, the circuit206may include at least one clock446and at least one counter448. A value of the at least one counter448may be incremented by the clock446, and the value of the at least one counter448may be stored in the memory424. When the voltage and/or the current of the identical first signal is at least substantially equal to at least one signal reference430,432, the at least one comparator434may send an indication450to the memory424. The indication450may cause the value of the at least one counter448to be stored as the at least one trigger time.

As described above, the testing device400may be synchronized with the tester (e.g. by means of a synchronization signal448a). In one or more embodiments, the synchronization signal448amay be provided by a counter of the tester212to synchronize the counter of the tester212with the counter448of the testing device400. In one or more embodiments, the counter448of the testing device400may be set (e.g. set or reset to zero) by the tester212(e.g. by means of a controller, which may be included in the tester212).

In one or more embodiments, the indication450may also be provided to at least one digital device452(also indicated as “DIG” inFIG. 4), configured to flip a bit in response to the indication450. The at least one digital device452may generate a trigger signal454configured to indicate to the tester212that a trigger time has been stored in the memory424.

In one or more embodiments, the at least one trigger time may be required by the tester212to determine and/or calculate, for example, the rise timing and/or fall timing and/or delay time and/or slew rate of each DUT of the plurality of DUTs. In one or more embodiments, information about the at least one trigger time may be provided by the testing device400to the tester. For example, the at least one interface signal216may include the information about the at least one trigger time. For example, the information about the at least one trigger time may be provided to the tester as control signal456by a serial peripheral interface bus457. The interface signal216may include the control signal456, as shown inFIG. 4. The circuit206may include the serial peripheral interface bus457.

In one or more embodiments, the circuit206may include at least one controller458a,458b. The at least one controller458a,458bmay be configured to control the operation of the testing device400. For example, the at least one controller458a,458bmay control the functioning of the plurality of first terminals202a,202b,202c. For example, the at least one controller458a,458bmay control if the plurality of first terminals202a,202b,202cprovides and/or receives the identical first signal. In one or more embodiments, the at least one controller458a,458bmay be used to provide the testing device400with information about the plurality of DUTs. The operation of the at least one controller458a,458bmay be controlled by the control signal456, which may be exchanged with the tester212.

The at least one controller may be implemented by means of a peripheral controller. The peripheral controller may, for example, be implemented by means of a field programmable gate array (FPGA) or a microprocessor, or a Programmable Logic Device (PLD).

In one or more embodiments, the circuit206may include at least one built-in-self-test458(also indicated as “BIST” inFIG. 4). The at least one built-in-self-test458may be used by the testing device400to test the circuit206of the testing device400. In one or more embodiments, the circuit206may include at least differential load460. The at least one differential load460may include at least one of a pull-up and a pull-down differential load460.

The description above provides examples where the identical first signal may be provided by the circuit206of the testing device400to each DUT of the plurality of DUTs through the respective first terminal202a,202b,202c. This may be referred to as a driving mode of the testing device400. As described above, the testing device400may be used in embodiments in which the identical first signal is received by the circuit206of the testing device400from each DUT of the plurality of DUTs through the respective first terminal202a,202b,202c. Such an example may be referred to as a receiving mode of the testing device400. The description that follows provides examples of the receiving mode of the testing device400.

In one or more embodiments, receipt of the identical first signal from each DUT of the plurality of DUTs208a,208b,208cmay be controlled by means of the controller458a,458b.

In one or more embodiments, the identical first signal received from each DUT of the plurality of DUTs may include a test response signal. For example, the test response signal may be a response of a DUT of the plurality of DUTs to an identical test signal provided to each DUT of the plurality of DUTs. Accordingly, the first signals may be identical to each other in that each first signal may be a response to an identical test signal. In one or more embodiments, the identical test signal may be provided to each DUT of the plurality of DUTs by another testing device, namely, a testing device other than the testing device400. For example, as shown inFIG. 3, the testing device200-T may be configured to provide the signal214-T to each DUT of the plurality of DUTs208ato208e, while the testing device200-R may be configured to receive the signal214-R (e.g. a response to the test signal) from the plurality of DUTs208ato208e.

In one or more embodiments, the testing device400may be configured to monitor the identical first signal received from each DUT of the plurality of DUTs, for example, by means of the at least one measurement device434(e.g. at least one shunt resistor and/or current shunt).

In one or more embodiments, monitoring the identical first signal (e.g. test response signal) received from each DUT of the plurality of DUTs may include comparing the voltage and/or current of the identical first signal (e.g. by means of the at least one comparator434) with at least one signal reference430,432.

In one or more embodiments, the circuit206may be configured to store (e.g. in the memory424) at least one trigger time, namely the time at which the voltage and/or the current of the identical first signal (e.g. test response signal) is at least substantially equal to at least one signal reference430,432provided to the circuit206.

In one or more embodiments, the at least one interface signal216may include information about the at least one trigger time. Accordingly, the circuit206may be configured to provide the information about the at least one trigger time to the tester212. For example, the information about the at least one trigger time may be provided to the tester212as control signal456(which may be included in the interface signal216) by the serial peripheral interface bus457. The further features described above in respect of the testing device400providing the identical first signal may be applicable to the testing device400receiving the identical first signal.

FIG. 5Ashows a circuit arrangement501for testing various timings of each DUT of a plurality of DUTs according to various embodiments.

Reference signs inFIG. 5Athat are the same as inFIG. 4denote the same or similar elements as inFIG. 4. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 5AandFIG. 4are described below.

The circuit arrangement501may include a plurality of DUTs508a,508b,508c,508d; a tester512; and a plurality of testing devices500-1(also indicated as “TE-IC IN” inFIG. 5A),500-2(also indicated as “TE-IC INH” inFIG. 5A),500-3(also indicated as “TE-IC VS” inFIG. 5A),500-4(also indicated as “TE-IC GH” inFIG. 5A),500-5(also indicated as “TE-IC GL” inFIG. 5A). Each testing device500-1,500-2,500-3,500-4,500-5may be configured according to the testing device400shown inFIG. 4.

As shown inFIG. 5A, the DUT508aof the plurality of DUTs508a,508b,508c,508dmay include a plurality of pins510-1(also indicated as “IN” pin inFIG. 5A),510-2(also indicated as “INH” pin inFIG. 5A),510-3(also indicated as “VS” pin inFIG. 5A),510-4(also indicated as “GH” pin inFIG. 5A),510-5(also indicated as “GL” pin inFIG. 5A). Each pin of the DUT508amay be connected to a respective testing device. For example, the pin510-1may be connected to the testing device500-1; the pin510-2may be connected to the testing device500-2; the pin510-3may be connected to the testing device500-3; the pin510-4may be connected to the testing device500-4; the pin510-5may be connected to the testing device500-5.

Although not shown inFIG. 5A, the testing device500-1may also be connected to the IN pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. In like manner, the testing device500-2may also be connected to the INH pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. The testing device500-3may also be connected to the VS pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. The testing device500-4may also be connected to the GH pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. The testing device500-5may also be connected to the GL pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d.

The circuit arrangement501may be used for testing various timings of the plurality of DUTs508a,508b,508c,508d. For example, the testing device500-3may provide each DUT of the plurality of DUTs508a,508b,508c,508dwith a power supply potential. A digital source in the tester512may generate a reference test signal (e.g. a step signal) and may provide the testing device500-1with the reference test signal. The reference test signal may be included in the interface signal516-1exchanged between the tester512and the testing device500-1. An example of the reference test signal is shown inFIG. 5B, with the horizontal axis denoting time increasing from left to right, and the vertical axis denoting voltage (in volts) increasing from bottom to top. The curve ofFIG. 5Bis not drawn to scale.

The testing device500-1may replicate the reference test signal (e.g. by means of a signal replicator) to form an identical test signal for testing the plurality of DUTs508a,508b,508c,508d. The testing device500-1may simultaneously provide the identical test signal to each DUT of the plurality of DUTs508a,508b,508c,508d. For example, the testing device500-1may provide the identical test signal shown inFIG. 5Bto each “IN” pin of each DUT of the plurality of DUTs508a,508b,508c,508d. For the sake of simplicity and ease of understanding, the testing device500-1is shown to provide the identical test signal to the “IN” pin510-1of the DUT508ainFIG. 5A.

As described above, the testing device500-1may compare (e.g. by means of a comparator) the identical signal provided to each DUT of the plurality of DUTs508a,508b,508c,508dto at least one signal reference. For example, the at least one signal reference known to the testing device500-1may be a voltage v1(shown inFIG. 5B). Accordingly, the testing device500-1may be configured to store at least one trigger time, namely a time at which a voltage of the identical test signal (e.g. the test signal shown inFIG. 5B) is at least substantially equal to the voltage v1. As shown inFIG. 5B, the identical test signal may be at least substantially equal to the voltage v1at times t1and t6. Accordingly, testing device500-1may store times t1and t6as the at least one trigger time.

A response of each DUT to the identical test signal (e.g. the test signal shown inFIG. 5B) provided to the plurality of DUTs508a,508b,508c,508dmay be received by testing devices other than testing device500-1. For example, after a certain dead time, a test response signal from the GH pin of each DUT may be received. For example, the testing device500-4may be configured to receive the test response signal from the GH pin of each DUT of the plurality of DUTs508a,508b,508c,508d, as shown inFIG. 5. An example of the test response signal at the GH pin of the DUT508ais shown inFIG. 5C, with the horizontal axis denoting time increasing from left to right, and the vertical axis denoting voltage (in volts) increasing from bottom to top. The curve ofFIG. 5Cis not drawn to scale. The at least one signal reference known to the testing device500-4may be the voltages v2and v3(shown inFIG. 5C). Accordingly, the testing device500-4may be configured to store at least one trigger time, namely a time at which a voltage of the test response signal (e.g. the test response signal shown inFIG. 5C) is at least substantially equal to the voltage v2or the voltage v3. As shown inFIG. 5B, the test response signal may be at least substantially equal to the voltages v2or v3at times t2, t3, t9, and t10. Accordingly, the testing device500-4may store times t2, t3, t9, and t10as the at least one trigger time.

In like manner, after a certain dead time, a test response signal from the GL pin of each DUT may be received. For example, the testing device500-5may be configured to receive the test response signal from the GL pin of each DUT of the plurality of DUTs508a,508b,508c,508d, as shown inFIG. 5A. An example of the test response signal at the GL pin of the DUT508ais shown inFIG. 5D, with the horizontal axis denoting time increasing from left to right, and the vertical axis denoting voltage (in volts) increasing from bottom to top. The curve ofFIG. 5Dis not drawn to scale. The at least one signal reference known to the testing device500-5may be the voltages v4and v5(shown inFIG. 5D). Accordingly, the testing device500-5may be configured to store at least one trigger time, namely a time at which a voltage of the test response signal (e.g. the test response signal shown inFIG. 5D) is at least substantially equal to the voltage v4or the voltage v5. As shown inFIG. 5D, the test response signal may be at least substantially equal to the voltages v2or v3at times t4, t5, t7, and t8. Accordingly, the testing device500-5may store times t4, t5, t7, and t8as the at least one trigger time.

As described above in relation toFIG. 3, the plurality of testing devices500-1,500-2,500-3,500-4,500-5may be synchronized with each other and/or with the tester512. Further, information about the at least one trigger time of each of the testing devices may be provided to the tester512(e.g. by means of a serial peripheral interface bus). For example, the testing device500-1may provide the trigger times t1and t6to the tester512using the interface signal516-1. The testing device500-4may provide the trigger times t2, t3, t9, and t10to the tester512using the interface signal516-4. The testing device may provide the trigger times t4, t5, t7, and t8to the tester512using the interface signal516-5. Thereafter, various timings of each DUT of the plurality of DUTs508a,508b,508c,508dmay be calculated by the tester512and/or a processing circuit (e.g. a processing unit, e.g. a central processing unit), which may be included in the testing device.

For example, a delay time between the “IN” pin and the “GH” pin of the DUT508amay be calculated as t2−t1. A delay time for the “GL” pin of the DUT508amay be calculated as t7−t6. Another delay time of the “GL” pin of the DUT508amay be calculated as t4−t1. A rise time of the “GH” pin of the DUT508amay be calculated as t3−t2. A fall time of the “GL” pin of the DUT508amay be calculated as t8−t7. A dead time between the “GH” pin and the “GL” pin of the DUT508amay be calculated as t4−t3. A dead time between the “GL” pin and the “GH” pin of the DUT508amay be calculated as t9−t8. A delay time of the “GH” pin of the DUT508amay be calculated as t9−t6. A rise time of the “GL” pin of the DUT508amay be calculated as t5−t4. A fall time of the “GH” pin of the DUT508amay be calculated as t10−t9.

FIG. 6Ashows a circuit arrangement601for testing various timings of a plurality of DUTs according to various embodiments.

Reference signs inFIG. 6Athat are the same as inFIG. 5Adenote the same or similar elements as inFIG. 5A. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 6AandFIG. 5Aare described below.

The circuit arrangement601may include a plurality of DUTs508a,508b,508c,508d; a tester512; and a plurality of testing devices600-1(also indicated as “TE-IC IN” inFIG. 6A),600-2(also indicated as “TE-IC INH” inFIG. 6A),600-3(also indicated as “TE-IC VS” inFIG. 6A),600-4(also indicated as “TE-IC GL” inFIG. 6A). Each testing device600-1,600-2,600-3,600-4may be configured according to the testing device400shown inFIG. 4.

As shown inFIG. 6A, the DUT508aof the plurality of DUTs508a,508b,508c,508dmay include a plurality of pins610-1(also indicated as “IN” pin inFIG. 6A),610-2(also indicated as “INH” pin inFIG. 6A),610-3(also indicated as “VS” pin inFIG. 6A),610-4(also indicated as “GL” pin inFIG. 6A). Each pin of the DUT508amay be connected to a respective testing device. For example, the pin610-1may be connected to the testing device600-1; the pin610-2may be connected to the testing device600-2; the pin610-3may be connected to the testing device600-3; the pin610-4may be connected to the testing device600-4.

Although not shown inFIG. 6A, the testing device600-1may also be connected to the IN pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. In like manner, the testing device600-2may also be connected to the INH pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. The testing device600-3may also be connected to the VS pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d. The testing device600-4may also be connected to the GL pin of each of the other DUTs of the plurality of DUTs508a,508b,508c,508d.

The circuit arrangement601may be used for testing various timings of the plurality of DUTs508a,508b,508c,508d. For example, the testing device600-3may provide each DUT of the plurality of DUTs508a,508b,508c,508dwith a power supply potential (e.g. through a plurality of power supply terminals of the testing device600-3). A digital source in the tester512may generate a reference test signal (e.g. a ramp signal) and may provide the testing device600-1with the reference test signal. The reference test signal may be included in the interface signal616-1exchanged between the tester512and the testing device600-1. An example of the reference test signal is shown inFIG. 6B, with the horizontal axis denoting time increasing from left to right, and the vertical axis denoting voltage (in volts) increasing from bottom to top. The curve ofFIG. 6Bis not drawn to scale.

The testing device600-1may replicate the reference test signal (e.g. by means of a signal replicator) to form an identical test signal for testing the plurality of DUTs508a,508b,508c,508d. The testing device600-1may simultaneously provide the identical test signal to each DUT of the plurality of DUTs508a,508b,508c,508d. For example, the testing device600-1may provide the identical test signal shown inFIG. 6Bto each “IN” pin of each DUT of the plurality of DUTs508a,508b,508c,508d. For the sake of simplicity and ease of understanding, the testing device600-1is shown to provide the identical test signal to the “IN” pin610-1of the DUT508ainFIG. 6A.

As described above, the testing device600-1may compare (e.g. by means of a comparator) the identical signal provided to each DUT of the plurality of DUTs508a,508b,508c,508dto at least one signal reference. For example, the at least one signal reference known to the testing device600-1may be a voltage v1and a voltage v2(shown inFIG. 6B). Accordingly, the testing device500-1may be configured to store at least one trigger time, namely a time at which a voltage of the identical test signal (e.g. the test signal shown inFIG. 6B) is at least substantially equal to the voltage v1or the voltage v2. As shown inFIG. 6B, the identical test signal may be at least substantially equal to the voltage v1at times t2and t3, and may be at least substantially equal to the voltage v2at times t1and t4. Accordingly, testing device500-1may store times t1, t2, t3and t4as the at least one trigger time.

A response of each DUT to the identical test signal (e.g. the test signal shown inFIG. 6B) provided to the plurality of DUTs508a,508b,508c,508dmay be received by testing devices other than testing device600-1. For example, after a certain dead time, a test response signal from the GL pin of each DUT may be received. For example, the testing device600-4may be configured to receive the test response signal from the GL pin of each DUT of the plurality of DUTs508a,508b,508c,508d, as shown inFIG. 6A. An example of the test response signal at the GL pin of the DUT508ais shown inFIG. 6C, with the horizontal axis denoting time increasing from left to right, and the vertical axis denoting voltage (in volts) increasing from bottom to top. The curve ofFIG. 6Cis not drawn to scale.

The at least one signal reference known to the testing device600-4may be the voltage v3(shown inFIG. 6C). Accordingly, the testing device600-4may be configured to store at least one trigger time, namely a time at which a voltage of the test response signal (e.g. the test response signal shown inFIG. 6C) is at least substantially equal to the voltage v3. As shown inFIG. 6C, the test response signal may be at least substantially equal to the voltage v3at times t5and t6. Accordingly, the testing device500-4may store times t5and t6as the at least one trigger time.

As described above in relation toFIG. 3, the plurality of testing devices600-1,600-2,600-3,600-4,600-5may be synchronized with each other and/or with the tester512. For example, the plurality of testing devices600-1,600-2,600-3,600-4,600-5may be synchronized with each other by means of a connection (e.g. communicative and/or electrical connection) among the plurality of testing devices600-1,600-2,600-3,600-4,600-5(e.g. a daisy chain connection, which may connect the plurality of testing devices600-1,600-2,600-3,600-4,600-5). Further, information about the at least one trigger time of each of the testing devices may be provided to the tester512(e.g. by means of a serial peripheral interface bus). For example, the testing device600-1may provide the trigger times t1, t2, t3and t4to the tester512using the interface signal616-1. The testing device500-4may provide the trigger times t5and t6to the tester512using the interface signal616-4. Thereafter, various timings of each DUT of the plurality of DUTs508a,508b,508c,508dmay be calculated by the tester512and/or a processing circuit (e.g. a processing unit, e.g. a central processing unit), which may be included in the testing device. The various timings of each DUT of the plurality of DUTs508a,508b,508c,508dmay be calculated with respect to a common time scale.

For example, an ascending ramp slew rate of the DUT508amay be calculated as (v1−v2)/(t2−t1). A descending ramp slew rate of the DUT508amay be calculated as (v2−v1)/(t4−t3). An ascending input reference of the DUT508amay be calculated as [v2+ascending ramp slew rate*(t5−t1)]. A descending input reference of the DUT508amay be calculated as [v1+descending ramp slew rate*(t6−t3)].

FIG. 7shows a block diagram of a circuit arrangement701according to various embodiments.

The circuit arrangement shown inFIG. 7may include a plurality of testing devices700-1,700-2; a tester712; and a plurality of DUTs708a,708b,708c. As shown inFIG. 7, circuit of each testing device of the plurality of testing devices700-1,700-2may include at least one signal replicator726, at least one signal comparator734; and at least one controller758(e.g. a peripheral controller (PCU)).

In one or more embodiments, a testing device of the plurality of testing devices700-1,700-2may include a plurality of first terminals and a plurality of second terminals, each configured to be connected to the plurality of DUTs708a,708b,708c. For example, as shown inFIG. 7, the testing device700-1includes a plurality of first terminals (indicated as “F” inFIG. 7), and a plurality of second terminals (indicated as “S” inFIG. 7). In like manner, the testing device700-2includes a plurality of first terminals (indicated as “F” inFIG. 7), and a plurality of second terminals (indicated as “S” inFIG. 7). The plurality of first terminals may also be referred to as a plurality of force terminals and the plurality of second terminals may also be referred to as a plurality of sense terminals.

In one or more embodiments, each first terminal of the plurality of first terminals may be configured to be connected to a respective DUT. For example, as shown inFIG. 7, each first terminal (indicated as “F”) of the testing device700-1is connected to a respective DUT of the plurality of DUTs708a,708b,708c. In like manner, each second terminal (indicated as “S”) of the testing device700-1is connected to a respective DUT of the plurality of DUTs708a,708b,708c. A similar connection maybe observed between the testing device700-2and the plurality of DUTs708a,708b,708c.

In one or more embodiments, the circuit of the testing device700-1may be configured to provide an identical first signal714a-1to each DUT of the plurality of DUTs708a,708b,708cthrough the respective first terminal (indicated as “F”), and to receive an identical second signal714b-1from each DUT of the plurality of DUTs708a,708b,708cthrough a respective second terminal (indicated as “S”) of the plurality of second terminals. In a similar manner, the circuit of the testing device700-2may be configured to provide an identical first signal714a-2to each DUT of the plurality of DUTs708a,708b,708cthrough the respective first terminal (indicated as “F”), and to receive an identical second signal714b-2from each DUT of the plurality of DUTs708a,708b,708cthrough a respective second terminal (indicated as “S”) of the plurality of second terminals.

The examples provided above may describe embodiments where a testing device may exchange at least one interface signal with a tester and an identical first signal with each DUT of a plurality of DUTs. In other words, the embodiments described above may provide examples where the testing device may be configured to operate with a tester to test a plurality of DUTs. In one or more embodiments, the testing device may be configured to operate without a tester to test a plurality of DUTs. In such an embodiment, the testing device may be controlled by means of a control circuit, which may, for example, be external to the testing device and which may, for example, be included in a circuit arrangement (e.g. a motherboard). The testing device may, for example, be included in the circuit arrangement, e.g. and may be coupled (e.g. communicatively and/or electrically coupled) to the control circuit.

In one or more embodiments, the identical first signal may include, or may be, an identical test signal for testing each DUT of the plurality of DUTs708a,708b,708c. For example, in the testing device700-1, the identical first signal714a-1may be a test signal provided to the “IN” terminal of each DUT of the plurality of DUTs708a,708b,708c. In one or more embodiments, the identical second signal may include, or may be, a feedback signal of the identical test signal provided to each DUT of the plurality of DUTs708a,708b,708c. For example, in the testing device700-1, the identical second signal714b-1may be a feedback signal of the identical test signal714a-1provided to the plurality of DUTs708a,708b,708c. In this way, the testing device700-1may regulate the identical first signal714a-1(e.g. dentical test signal) provided to the plurality of DUTs708a,708b,708c. For example, the circuit may include at least one feedback controller configured to compare the identical second signal714b-1to at least one signal reference, and to adjust at least one of a voltage and a current of the identical first signal714a-1based on the result of the comparison of the identical second signal714b-1to the at least one signal reference.

A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test (DUTs), wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective DUT of the plurality of DUTs; a signal interface configured to be connected to a tester; and circuit configured to exchange an identical first signal with each DUT of the plurality of DUTs through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

In one or more embodiments, the respective first terminal may be configured to be connected to a respective pin of the respective DUT, wherein the respective pins of the respective DUTs may be configured to provide the same (technical) function (e.g. for an identical technical use) in each respective DUT.

In one or more embodiments, the circuit may be configured to provide the identical first signal to each DUT of the plurality of DUTs through the respective first terminal.

In one or more embodiments, the identical first signal may include an identical test signal for testing each DUT of the plurality of DUTs.

In one or more embodiments, the at least one interface signal may include a reference signal, wherein the circuit may be configured to receive the reference signal from the tester through the signal interface, and to replicate the reference signal to form the identical first signal exchanged with each DUT of the plurality of DUTs.

In one or more embodiments, the reference signal may include a reference test signal for testing each DUT of the plurality of DUTs.

In one or more embodiments, the circuit may include at least one signal replicator configured to replicate a reference signal to form the identical first signal exchanged with each DUT of the plurality of DUTs.

In one or more embodiments, the reference signal may be provided to the circuit by the tester through the signal interface.

In one or more embodiments, the reference signal may be pre-programmed into the circuit.

In one or more embodiments, the circuit may be configured to receive the identical first signal from each DUT of the plurality of DUTs through the respective first terminal.

In one or more embodiments, the identical first signal may include a test response signal, wherein the test response signal may be a response of a DUT of the plurality of DUTs to an identical test signal provided to each DUT of the plurality of DUTs.

In one or more embodiments, the at least one interface signal may include at least one signal reference, wherein the circuit may be configured to receive the at least one signal reference from the tester through the signal interface.

In one or more embodiments, the circuit may be further configured to store at least one trigger time, wherein the at least one trigger time may be a time at which a voltage and/or a current of the identical first signal may be at least substantially equal to at least one signal reference provided to the circuit.

In one or more embodiments, the circuit may include a memory for storing the at least one trigger time.

In one or more embodiments, the at least one interface signal may include information about the at least one trigger time, and wherein the circuit may be configured to provide the information about the at least one trigger time to the tester through the signal interface.

In one or more embodiments, the at least one interface signal may include a synchronization signal configured to synchronize the testing device with the tester, and wherein the circuit may be configured to receive the synchronization signal from the tester through the signal interface.

In one or more embodiments, the circuit may include at least one measurement device configured to measure at least one of a voltage and a current of the identical first signal.

In one or more embodiments, the circuit may include at least one comparator configured to compare at least one of a voltage and a current of the identical first signal with at least one signal reference provided to the circuit.

In one or more embodiments, the circuit may include a serial peripheral interface bus.

In one or more embodiments, the circuit may include a peripheral controller.

In one or more embodiments, the peripheral controller may include a field programmable gate array.

In one or more embodiments, the testing device may further include a plurality of second terminals configured to be connected to the plurality of DUTs, wherein each second terminal of the plurality of second terminals is configured to be connected to a respective DUT, wherein the circuit may be configured to provide the identical first signal to each DUT of the plurality of DUTs through the respective first terminal of the plurality of first terminals, and to receive an identical second signal from each DUT of the plurality of DUTs through a respective second terminal of the plurality of second terminals.

In one or more embodiments, the identical first signal may include an identical test signal for testing each DUT of the plurality of DUTs, and wherein the identical second signal may include a feedback signal of the identical test signal provided to each DUT of the plurality of DUTs.

In one or more embodiments, the circuit may include at least one feedback controller configured to compare the identical second signal to at least one signal reference, and to adjust at least one of a voltage and/or a current of the identical first signal based on the result of the comparison of the identical second signal to the at least one signal reference.

A circuit arrangement in accordance with various embodiments may include: a plurality of devices-under-test (DUTs); a tester; at least one first testing device configured to provide an identical first signal to the plurality of DUTs, and to exchange at least one first interface signal with the tester; and at least one second testing device configured to receive an identical second signal from the plurality of DUTs, and to exchange at least one second interface signal with the tester, wherein a testing device of at least one first testing device and the at least one second testing device includes a plurality of first terminals configured to be connected to the plurality of DUTs, wherein each first terminal of the plurality of first terminals is configured to be connected to a respective DUT of the plurality of DUTs. It is to be noted that in various embodiments, the interface signal may be configured in a daisy chain, i.e. one testing device may be connected to the other testing device and this will send out the signal over one or more interfaces to the tester. This might save input/output terminals at the tester.

A circuit arrangement in accordance with various embodiments may include: a plurality of devices-under-test; a control circuit; at least one first testing device configured to provide an identical first signal to the plurality of devices-under-test, and to exchange at least one first interface signal with the control circuit; and at least one second testing device configured to receive an identical second signal from the plurality of devices-under-test, and to exchange at least one second interface signal with the control circuit, wherein a testing device of at least one first testing device and the at least one second testing device comprises a plurality of first terminals configured to be connected to the plurality of devices-under-test, wherein each first terminal of the plurality of first terminals is configured to be connected to a respective device-under-test of the plurality of devices-under-test. It is to be noted that in various embodiments, the interface signal may be configured in a daisy chain, i.e. one testing device may be connected to the other testing device and this will send out the signal over one or more interfaces to the tester. This might save input/output terminals at the tester.