Semiconductor device and method of manufacturing the same

A semiconductor device includes conductive layers and interlayer insulating layers stacked alternately with each other, at least one first channel layer passing through the conductive layers and the interlayer insulating layers, at least one second channel layer coupled to the first channel layers and passing through the conductive layers and the interlayer insulating layers, a first insulating layer interposed between the at least one first channel layer and the conductive layers, and a second insulating layer interposed between the at least one second channel layer and the conductive layers and having a higher nitrogen concentration than the first insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean patent application number 10-2012-0116175 filed on Oct. 18, 2012, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

1. Technical Field

Various embodiments relate generally to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device and a method of manufacturing the same.

2. Related Art

A non-volatile memory device retains data stored therein even when not powered. Two-dimensional memory devices in which memory cells are fabricated on a single layer over a silicon substrate have reached physical limits in increasing their degree of integration. Accordingly, three-dimensional (3D) non-volatile memory devices in which memory cells are stacked in a vertical direction over a silicon substrate have been proposed.

A 3D non-volatile memory device includes memory cells and select transistors that are stacked over a substrate. These memory cells include a memory layer to store data. The memory layer may include a tunnel insulating layer, a charge storing layer, and a charge blocking layer.

When a 3D non-volatile memory device is manufactured, memory cells and select transistors are formed concurrently. The select transistors may also include a memory layer that acts as a gate insulating layer. However, when the memory layer is used as the gate insulating layer, a leakage current of the select transistors may increase.

BRIEF SUMMARY

Various embodiments relate to a semiconductor device and a method of manufacturing the same for preventing leakage current of a select transistor and controlling a threshold voltage thereof.

A semiconductor device according to an embodiment of the present invention includes conductive layers and interlayer insulating layers stacked alternately with each other, at least one first channel layer passing through the conductive layers and the interlayer insulating layers, at least one second channel layer coupled to the first channel layers and passing through the conductive layers and the interlayer insulating layers, a first insulating layer interposed between the at least one first channel layer and the conductive layers, and a second insulating layer interposed between the at least one second channel layer and the conductive layers and having a higher nitrogen concentration than the first insulating layer.

A method of manufacturing a semiconductor device according to another embodiment of the present invention includes alternately forming first material layers and second material layers, forming at least one channel hole by etching the first and second material layers, forming a first insulating layer along an inner wall of the at least one channel hole, forming a first channel layer over the first insulating layer, etching the first channel layer to expose a portion of the first insulating layer, nitriding an exposed portion of the first insulating layer, and forming a second channel layer over a nitrided portion of the first insulating layer.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, a thickness and a distance of components may be exaggerated compared to an actual physical thickness and interval for convenience of illustration. In the following description, detailed explanations of known related functions and constitutions may be omitted to avoid unnecessarily obscuring the subject manner of the present invention. Like reference numerals refer to like elements throughout the specification and drawings.

FIGS. 1A to 1Care cross-sectional views of the structure of a semiconductor device according to an embodiment of the present invention.

As illustrated inFIG. 1A, a semiconductor device according to an embodiment of the present invention may include conductive layers11and interlayer insulating layers12, at least one first channel layer13, at least one second channel layer14, a first insulating layer18A, and a second insulating layer18B. The conductive layers11and the interlayer insulating layers12may be stacked alternately with each other. The first channel layer13may pass through the conductive layers11and the interlayer insulating layers12. The second channel layer14may be coupled to the first channel layer13and pass through the conductive layers11and the interlayer insulating layers12. The first insulating layer18A may be interposed between the first channel layer13and the alternately stacked conductive layers11and interlayer insulating layers12. The second insulating layer18B may be interposed between the second channel layer14and the alternately stacked conductive layers11and interlayer insulating layers12and contain a higher nitrogen concentration than the first insulating layer18A.

Each of the conductive layers11may be configured as a word line or a select line. For example, each conductive layer11may include a polysilicon layer or a metal layer such as a tungsten layer or a silicide layer. In addition, each of the conductive layers11may be of the same or different thickness. For example, one or more of the uppermost conductive layers11may be configured as select lines, and the other conductive layers11may be configured as word lines. The conductive layer11configured as select lines may each have a greater thickness than the conductive layers11configured as word lines.

The interlayer insulating layers12may insulate stacked word lines or select lines from each other. For example, each of the interlayer insulating layers12may comprise a silicon oxide layer or a silicon nitride layer.

The first channel layer13may pass through the conductive layers11configured as word lines and the interlayer insulating layers12interposed therebetween. The first channel layer13may be formed in a tubular shape manner having an open central portion or in a pillar shape manner having a central portion completely filled.FIG. 1Aparticularly illustrates that the first channel layer13is formed in a tubular shape manner and is filled with a gap-fill insulating layer19.

The second channel layer14may pass through the conductive layers11configured as select lines and the interlayer insulating layers12interposed therebetween. The second channel layer14may be located on or under the first channel layer13and connected to the first channel layer13in a single body. Similar to the first channel layer13, the second channel layer14may be formed in a tubular shape manner having an open central portion or in a pillar shape manner having a central portion completely filled.FIG. 1Aparticularly illustrates that the second channel layer14is formed in a pillar shape manner, and in this example, a contact area between the second channel layer14and a contact plug (not illustrated) configured as a bit line to be formed by subsequent processes may be increased to thereby reduce contact resistance.

The first insulating layer18A may be interposed between the first channel layer13and the alternately stacked conductive layers11configured as word lines and the interlayer insulating layers12, and may be used as a memory layer of a memory cell. The first insulating layer18A may surround the first channel layer13and may include a tunnel insulating layer, a charge storing layer, and a charge blocking layer. For example, the first insulating layer18A may include a first tunnel insulating layer15A surrounding the first channel layer13, a first charge storing layer16A surrounding the first tunnel insulating layer15A, and a first charge blocking layer17A surrounding the first charge storing layer16A.

The second insulating layer18B may be interposed between the second channel layer14and the alternately stacked conductive layers11configured as select lines and the interlayer insulating layers12, and may be used as a gate insulating layer of a select transistor. The second insulating layer18B may surround the second channel layer14and may include a tunnel insulating layer, a charge storing layer, and a charge blocking layer. For example, the second insulating layer18B may include a second tunnel insulating layer15B surrounding the second channel layer14, a second charge storing layer16B surrounding the second tunnel insulating layer15B, and a second charge blocking layer17B surrounding the second charge storing layer16B.

The first and second charge blocking layers17A and17B may prevent charge from passing through the first and second charge storing layers16A and16B and moving to the conductive layers11configured as word lines. Each of the first and second charge blocking layers17A and17B may be an oxide layer formed through thermal oxidation or deposition. Each of the first and second tunnel insulating layers15A and15B may include an oxide layer such as a silicon oxide layer. The first and second charge storing layers16A and16B may be used as an actual data storage that stores data therein. In addition, the first and second charge storing layers16A and16B may include at least one of a floating gate formed of a polysilicon layer storing charge, a trap layer including a nitride layer trapping charge, and nanodots. The semiconductor device may also include first and second phase-change material layers instead of the first and second charge storing layers16A and16B.

In addition, the first insulating layer18A and the second insulating layer18B may be coupled integrally with each other to form a single layer. In this specification, a selectively nitrided portion of a single layer is referred to as the second insulating layer18B, and the remaining portion of the layer is referred to as the first insulating layer18A.

The second insulating layer18B may have a uniform nitrogen concentration or a nitrogen concentration gradient. For example, by controlling a depth at which nitrogen is injected in a horizontal direction during a nitriding process, the second insulating layer18B may have such a concentration gradient where a nitrogen concentration of the second insulating layer18B may increase as distance from the second channel layer14decreases or may decrease as distance therefrom increases. In another example, a nitrogen concentration at a specific location (e.g., second charge storing layer) may be increased by controlling a range (Rp) where nitrogen is injected.

For example, when nitrogen is injected at a depth corresponding to the second tunnel insulating layer15B, the second tunnel insulating layer15B may have a higher nitrogen concentration than the first tunnel insulating layer15A, and the second charge storing layer16B and the second charge blocking layer17B may have substantially similar nitrogen concentrations as the first charge storing layer16A and the first charge blocking layer17A, respectively. In another example, when nitrogen is injected at depths from the second tunnel insulating layer15B to the second charge storing layer16B, the second tunnel insulating layer15B may have a higher nitrogen concentration than the first tunnel insulating layer15A, the second charge storing layer16B may have a higher nitrogen concentration than the first charge storing layer16A, and the second charge blocking layer17B may have a substantially similar nitrogen concentration as the first charge blocking layer17A. In yet another example, when nitrogen is injected at depths from the second tunnel insulating layer15B to the second charge blocking layer17B through the second charge storing layer16B, the second tunnel insulating layer15B may have a higher nitrogen concentration than the first tunnel insulating layer15A, the second charge storing layer16B may have a higher nitrogen concentration than the first charge storing layer16A, and the second charge blocking layer17B may have a higher nitrogen concentration than the first charge blocking layer17A. In addition, the second charge storing layer16B may have a higher nitrogen concentration than the second tunnel insulating layer15B and the second charge blocking layer17B by controlling the range (Rp) where nitrogen is injected.

Hereinafter, structures of semiconductor devices according to other embodiments of the present invention may be illustrated with reference toFIGS. 1B and 1C. The semiconductor devices as illustrated inFIGS. 1B and 1Cmay have substantially similar structures with that of the semiconductor device described with reference toFIG. 1Aexcept for positions where the first and second insulating layers18A and18B are formed. Therefore, a description of the contents of the semiconductor devices illustrated inFIGS. 1B and 1Cthat are the same as those of the semiconductor device described with reference toFIG. 1Ais omitted. The key difference concerning the first and second insulating layers18A and18B will be mainly described.

As illustrated inFIG. 1B, the first insulating layer18A may include the first tunnel insulating layer15A, the first charge storing layer16A, and first charge blocking layer17A. The first tunnel insulating layer15A may surround the first channel layer13. The first charge storing layer16A may surround the first tunnel insulating layer15A. The first charge blocking layer17A may be interposed between the first charge storing layer16A and the conductive layers11and surround top and bottom surfaces of the conductive layers11.

Similarly, the second insulating layer18B may include the second tunnel insulating layer15B, the second charge storing layer16B, and the second charge blocking layer17B. The second tunnel insulating layer15B may surround the second channel layer14. The second charge storing layer16B may surround the second tunnel insulating layer15B. The second charge blocking layer17B may be interposed between the second charge storing layer16B and the conductive layers11and surround top and bottom surfaces of the conductive layers11.

As illustrated inFIG. 1C, first insulating layers18A may be interposed between the first channel layer13and the conductive layers11configured as word lines and may not be interposed between the first channel layer13and the interlayer insulating layers12. For example, the first insulating layer18A may include the first tunnel insulating layer15A, the first charge storing layer16A, and the first charge blocking layer17A. The first tunnel insulating layer15A may surround the first channel layer13. The first charge storing layer16A may surround the first tunnel insulating layer15A. The first charge blocking layer17A may surround the first charge storing layer16A.

Similarly, second insulating layers18B may be interposed between the second channel layer14and the conductive layers11configured as select lines and may not be interposed between the second channel layer14and the interlayer insulating layers12. For example, each second insulating layer18B may include the second tunnel insulating layer15B, the second charge storing layer16B, and the second charge blocking layer17B. The second tunnel insulating layer15B may surround the second channel layer14. The second charge storing layer16B may surround the second tunnel insulating layer15B. The second charge blocking layer17B may surround the second charge storing layer16B.

Considering the above-described structures, a threshold voltage of a select transistor may be easily controlled by adjusting a nitrogen concentration of a gate insulating layer. The gate insulating layer of the select transistor may have a higher nitrogen concentration than a memory layer of a memory cell. When the gate insulating layer has a higher nitrogen concentration, the number of trap sites of the gate insulating layer of the select transistor may increase, and therefore, the select transistor may have a higher threshold voltage than the memory cell. As a result, leakage current of the select transistor may be prevented.

FIGS. 2A to 2Dare cross-sectional views illustrating a process flow for manufacturing a semiconductor device according to an embodiment of the present invention.

As illustrated inFIG. 2A, first material layers21and second material layers22may be stacked alternately with each other. The first material layers21may be provided to form conductive layers such as word lines and select lines. The second material layers22may insulate stacked conductive layers from each other. For example, one or more of the uppermost first material layers21may be configured as select lines, and the other first material layers21may be configured as word lines. Each of the first material layers21configured as select lines may have a thickness greater than or equal to each of the material layers21configured as word lines.

For example, each of the first material layers21may include a conductive layer such as a polysilicon layer, and each of the second material layers22may include an insulating layer such as an oxide layer. In another example, each of the first material layers21may include a conductive layer such as a doped polysilicon layer or a doped amorphous silicon layer. Each of the second material layers22may include a sacrificial layer such as an undoped polysilicon layer or an undoped amorphous silicon layer. In yet another example, each of the first material layers21may include a sacrificial layer such as a nitride layer, and each of the second material layers22may include an insulating layer such as an oxide layer.

According toFIG. 2A, a description is made with reference to a case in which the first material layers21include sacrificial layers and the second material layers22include insulating layers.

Subsequently, the first material layers21and the second material layers22that are stacked alternately with each other may be etched to form at least one channel hole23. An insulating layer27may then be formed along an inner wall of the channel hole23. When the insulating layer27is formed, at least one of a charge blocking layer24, a charge storing layer25, and a tunnel insulating layer26may be sequentially formed along the inner wall of the channel hole23. For example, the charge storing layer25and the tunnel insulating layer26may be formed along the inner wall of the channel hole23.

Subsequently, a first channel layer28may be formed on the insulating layer27. For example, the first channel layer28may include a polysilicon layer. The first channel layer28may be formed in a tubular shape manner having an open central portion. Subsequently, the open central portion of the first channel layer28may be filled with a gap-fill insulating layer29. For example, the gap-fill insulating layer29may include an oxide layer.

A portion of the insulating layer27may be exposed by etching the gap-fill insulating layer29and the first channel layer28to a certain depth.

For example, the gap-fill insulating layer29and the first channel layer28may be etched so that top surfaces of the gap-fill insulating layer29and the first channel layer28may be higher than a top surface of the first material layer21configured as an uppermost word line. Here, the top surfaces of the gap-fill insulating layer29and the first channel layer28may be higher than a bottom surface of the first material layer21configured as a select line so as to partially expose the first material layer21configured as a select line.

The gap-fill insulating layer29and the first channel layer28may be removed by one of, or a combination of dry etching and wet etching. In addition, the gap-fill insulating layer29and the first channel layer28may be etched simultaneously or separately.

When the first channel layer28is formed in a pillar shape manner, a process of forming the gap-fill insulating layer29may be skipped. In this example, the first channel layer28may be etched to expose the first material layers21configured as a select line.

Hereinafter, for illustration purposes, an exposed portion of the insulating layer27is referred to as a second insulating layer27B, and an unexposed portion of the insulating layer27is referred to as a first insulating layer27A. The second insulating layer27B may include a second charge blocking layer24B, a second charge storing layer25B, and a second tunnel insulating layer26B. In addition, the first insulating layer27A may include a first charge blocking layer24A, a first charge storing layer25A, and a first tunnel insulating layer26A.

As illustrated inFIG. 2B, the second insulating layer27B may be nitrided (see reference numeral “30”). During a nitriding process, the first insulating layer27A may not be exposed since the first insulating layer27A is covered by the gap-fill insulating layer29and the first channel layer28. Therefore, selective nitridation may be performed to nitride only the second insulating layer27B, and accordingly the first insulating layer27A may have the same nitrogen concentration before and after nitridation. Therefore, the second insulating layer27B may have a higher nitrogen concentration than the first insulating layer27A.

The difference in nitrogen concentration between the first insulating layer27A and the second insulating layer27B may be controlled according to various nitriding processes. For example, the nitriding process may be performed using one of, or a combination of, a plasma nitriding process, a thermal treatment process using nitrogen gases, and an ion injection process using nitrogen ions. In addition, the nitriding process may be performed under a temperature condition ranging from 400° C. to 1000° C. and a pressure condition ranging from 0.1 Torr to 2 Torr and may be performed using one of, or a combination of, N2O gas, NO gas, and N2gas.

In addition, during nitridation of the second insulating layer27B, a depth by which the second insulating layer27B is nitrided may be controlled according to process conditions. For example, only the second tunnel insulating layer26B may be nitrided, or both the second tunnel insulating layer26B and the second charge storing layer25B may be nitrided. Otherwise, the second tunnel insulating layer26B, the second charge storing layer25B, and the second charge blocking layer24B may all be subject to nitridation.

A diffusion process such as a heat treatment process may be further performed. Nitrogen atoms included in the second insulating layer27B may be diffused into the first insulating layer27A by the diffusion process. Therefore, the first insulating layer27A may be partially nitrided.

As illustrated inFIG. 2C, a second channel layer31may be formed in the channel hole23. The second channel layer31may include a polysilicon layer. The second channel layer31may be formed in a tubular shape manner having an open central portion or in a pillar shape manner having a central portion completely filled.FIG. 2Cillustrates that the second channel layer31is formed in a pillar shape manner.

As illustrated inFIG. 2D, conductive layers32may replace the first material layers21. For example, the first material layers21and the second material layers22may be etched to form at least one slit33between neighboring channel holes23, and the first material layers21exposed through the slit33may be etched to form first recessed regions. Subsequently, the conductive layers32may be formed in the first recessed regions. Subsequently, the slit33may be filled with an insulating layer34. In this example, an air gap may be formed in the slit33by controlling a deposition thickness and a deposition method of the insulating layer34. As a result, the semiconductor device having the structure as illustrated inFIG. 1Amay be manufactured.

Prior to forming conductive layers in the first recessed regions, an insulating layer may be additionally formed along inner surfaces of the first recessed regions. In this example, when the insulating layer is formed, at least one of a charge blocking layer, a charge storing layer, and a tunnel insulating layer may be sequentially formed. The semiconductor device having the structure as illustrated inFIG. 1Bmay be manufactured by forming another charge blocking layer. The additionally formed charge blocking layer may be formed by stacking an oxide layer and a material layer with a high dielectric constant.

According to the aforementioned processes, a nitrogen concentration of a gate insulating layer of a select transistor may be easily controlled. Therefore, a threshold voltage of the select transistor may be controlled, and leakage current may be prevented.

Various changes may be made to the above-described processes, particularly the processes subsequent to forming the slit33, according to materials of the first and second material layers21and22.

When the first material layers21include conductive layers, and the second material layers22include interlayer insulating layers, the slit33may be formed, and the first material layers21exposed through the slit33may be silicided. Subsequently, the insulating layer34may be formed in the slit33.

In another example, when the first material layers21include conductive layers, and the second material layers22include sacrificial layers, the second material layers22exposed through the slit33may be removed to form second recessed regions. Subsequently, the first material layers21exposed through the slit33may be silicided, and an insulating layer may be formed in the second recessed regions. The first and second insulating layers27A and27B exposed through the second recessed regions may be etched before the insulating layer is formed in the second recessed regions. Subsequently, the insulating layer34may be formed in the slit33. In this example, the semiconductor device having the structure as illustrated inFIG. 1Cmay be manufactured.

FIG. 3is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

As illustrated inFIG. 3, a memory system100according to an embodiment of the present invention may include a non-volatile memory device120and a memory controller110.

The non-volatile memory device120may have the above-described structure. In addition, the non-volatile memory device120may be a multi-chip package composed of a plurality of flash memory chips.

The memory controller110may be configured to control the non-volatile memory device120. The memory controller110may include an SRAM111, a CPU112, a host interface113, an ECC114and a memory interface115. The SRAM111may function as an operation memory of the CPU112. The CPU112may perform the general control operation for data exchange of the memory controller110. The host interface113may include a data exchange protocol of a host being coupled to the memory system100. In addition, the ECC114may detect and correct errors included in a data read from the non-volatile memory device120. The memory interface115may interface with the non-volatile memory device120. The memory controller110may further include RCM that stores code data to interface with the host.

The memory system100having the above-described configuration may be a solid state disk (SSD) or a memory card in which the memory device120and the memory controller110are combined. For example, when the memory system100is an SSD, the memory controller110may communicate with an outside source (e.g., a host) through one of the interface protocols including USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI and IDE.

FIG. 4is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

As illustrated inFIG. 4, a computing system200according to an embodiment of the present invention may include a CPU220, RAM230, a user interface240, a modem250and a memory system210that are electrically coupled to a system bus260. In addition, when the computing system200is a mobile device, a battery may be further included to apply operating voltage to the computing system200. The computing system200may further include application chipsets, a Camera Image Processor (CIS) and a mobile DRAM.

As described above in connection withFIG. 3, the memory system210may include a non-volatile memory212and a memory controller211.

Since a gate insulating layer of a select transistor is selectively nitrided, a threshold voltage of the select transistor may be controlled, and leakage current may be reduced.