Converter and power conversion device using same

A converter includes a first diode having an anode and a cathode connected respectively to an input terminal and a first output terminal, a second diode having an anode and a cathode connected respectively to a second output terminal and the input terminal, a first transistor connected between the first output terminal and the input terminal, a second transistor connected between the input terminal and the second output terminal, and a bidirectional switch connected between the input terminal and a third output terminal and including third to sixth diodes and a third transistor. Each of the first diode, the second diode, and the third transistor is made of a wide bandgap semiconductor. Each of the first and second transistors and the third to sixth diodes is made of a semiconductor other than the wide bandgap semiconductor.

TECHNICAL FIELD

The present invention relates to a converter and a power conversion apparatus including the same, and particularly, to a converter that converts an AC voltage into first to third DC voltages and a power conversion apparatus including the converter.

BACKGROUND ART

Japanese Patent Laying-Open No. 2011-78296 (PTD 1) discloses a converter that includes four transistors and six diodes and converts an AC voltage into a high voltage, a low voltage, and an intermediate voltage. Two diodes that perform a reverse recovery operation among the six diodes are made of wide bandgap semiconductors, leading to a reduced recovery loss of the converter. Besides, the other four diodes that do not perform the reverse recovery operation are made of semiconductors other than wide bandgap semiconductors, leading to a reduced cost of the converter.

CITATION LIST

Patent Document

SUMMARY OF INVENTION

Technical Problem

A conventional converter includes a large number of semiconductor elements, which increases a device size, leading to high cost. The conventional converter also has a large loss resulting from the four transistors.

A main object of the present invention is therefore to provide a compact, inexpensive, and low-loss converter, and a power conversion apparatus including the same.

Solution to Problem

A converter according to the present invention is a converter that converts an AC voltage supplied to an input terminal into first to third DC voltages and outputs the first to third DC voltages respectively to first to third output terminals. The converter includes a first diode having an anode and a cathode connected respectively to the input terminal and a first output terminal, a second diode having an anode and a cathode connected respectively to a second output terminal and the input terminal, a first transistor connected between the first output terminal and the input terminal, a second transistor connected between the input terminal and the second output terminal, and a first bidirectional switch connected between the input terminal and the third output terminal. The first DC voltage is higher than the second DC voltage, and the third DC voltage is an intermediate voltage between the first and second DC voltages. The first bidirectional switch includes third to sixth diodes and a third transistor. The third and fourth diodes have anodes connected respectively to the input terminal and the third output terminal and cathodes connected together to a first electrode of the third transistor. The fifth and sixth diodes have cathodes connected respectively to the input terminal and the third output terminal and anodes connected together to a second electrode of the third transistor. Each of the first diode, the second diode, and the third transistor is made of a wide bandgap semiconductor. Each of the first transistor, the second transistor, and the third to sixth diodes is made of a semiconductor other than the wide bandgap semiconductor.

Advantageous Effects of Invention

The converter according to the present invention includes three transistors and six diodes. This converter accordingly has fewer semiconductor elements than a conventional converter, thus reducing the size and cost of the device. Further, the first and second diodes that perform the reverse recovery operation and the third transistor that switches a large current are made of wide bandgap semiconductors, thus reducing a switching loss and a recovery loss. The third to sixth diodes that do not perform the reverse recovery operation and the first and second transistors that switch a small current are made of semiconductors other than wide bandgap semiconductors, leading to a reduced cost.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a circuit diagram showing a configuration of a converter according to Embodiment 1 of the present invention. With reference toFIG. 1, this converter includes an input terminal T0, output terminals T1to T3(first to third output terminals), diodes D1to D6(first to sixth diodes), and transistors Q1to Q3(first to third transistors).

Input terminal T0receives an AC voltage VAC of a commercial frequency from, for example, a commercial AC power supply10. Output terminals T1and T3are connected respectively with the positive electrode and negative electrode of a battery B1. Output terminals T3and T2are connected respectively with the positive electrode and negative electrode of a battery B2. Each of batteries B1and B2stores DC power. Batteries B1and B2are charged with DC voltages having the same value.

When the voltages at output terminals T1, T2, and T3are respectively DC voltages V1, V2, and V3, V1>V3>V2, and V3=(V1+V2)/2. This converter converts AC voltage VAC applied to input terminal T0into DC voltages V1to V3and outputs DC voltages V1to V3respectively to output terminals T1to T3. If output terminal T3is grounded, DC voltages V1to V3are respectively a positive voltage, a negative voltage, and 0 V.

Diode D1has an anode connected to input terminal T0and a cathode connected to output terminal T1. Diode D2has an anode connected to output terminal T2and a cathode connected to input terminal T0. Transistor Q1has a collector connected to output terminal T1and an emitter connected to input terminal T0. Transistor Q2has a collector connected to input terminal T0and an emitter connected to output terminal T2.

Diodes D3and D4have anodes connected respectively to input terminal T0and output terminal T3and cathodes connected to each other. Diodes D5and D6have cathodes connected respectively5to input terminal T0and output terminal T3and anodes connected to each other.

Transistor Q3has a drain (first electrode) connected to the cathodes of diodes D3and D4and a source (second electrode) connected to the anodes of diodes D5and D6. Diodes D3to D6and transistor Q3constitute a first bidirectional switch connected between input terminal T0and output terminal T3.

Diode D1allows a current to flow from input terminal T0to output terminal T1during a period in which AC voltage VAC is a positive voltage, thereby charging battery B1. Diode D2allows a current to flow from output terminal T2to input terminal T0during a period in which AC voltage VAC is a negative voltage, thereby charging battery B2.

Since diodes D1and D2allow flows of the currents that charge batteries B1and B2, diodes D1and D2have rated currents set to relatively large values. The rated current of each of diodes D1and D2is, for example, 600 A, which is greater than the rated current of each of diodes D3to D6and transistors Q1to Q3. For reduced loss in diodes D1and D2, each of diodes D1and D2is made of silicon carbide (SiC) that is a wide bandgap semiconductor, which is, for example, a Schottky barrier diode.

In some cases, the power is regenerated from a load (not shown) such as a motor connected with batteries B1and B2, voltage V1at output terminal T1exceeds a rated voltage V1R, and voltage V2at output terminal T2falls below a rated voltage V2R. Rated voltage V1R is a voltage obtained by subtracting a threshold voltage of diode D1from a positive peak voltage of AC voltage VAC. Rated voltage V2R is a voltage obtained by adding a threshold voltage of diode D2to a negative peak voltage of AC voltage VAC.

When voltage V1at output terminal T1exceeds rated voltage V1R, transistor Q1allows a current to flow from output terminal T1to input terminal T0, thus reducing voltage V1at output terminal T1. When voltage V2at output terminal T2falls below rated voltage V2R, transistor Q2allows a current to flow from input terminal T0to output terminal T2, thus increasing voltage V2at output terminal T2.

Since this converter is used as a power conversion apparatus (e.g., uninterruptible power system) with small regenerated power, the rated currents of transistors Q1and Q2are set to relatively small values. The rated current of each of transistors Q1and Q2is, for example, 300 A, which is smaller than the rated current of each of diodes D1to D6and transistor Q3. Transistors Q1and Q2have a low loss, eliminating the need for forming transistors Q1and Q2using expensive wide bandgap semiconductors. Thus, for reduced device cost, each of transistors Q1and Q2is made of silicon (Si) that is a semiconductor other than the wide bandgap semiconductor, which is, for example, an insulated gate bipolar transistor (IGBT).

Diodes D3to D6and transistor Q3constitute a first bidirectional switch for setting voltage V3at output terminal T3to an intermediate voltage between voltages V1and V2. The rated current of each of diodes D3to D6and transistor Q3is set to a value smaller than the rated current of each of diodes D1and D2and greater than the rated current of each of transistors Q1and Q2. The rated current of each of diodes D3to D6is, for example, 450 A. The rated current of transistor Q3is, for example, 500 A.

Diodes D3to D6have a low loss, thus eliminating the need for forming diodes D3to D6using expensive wide bandgap semiconductors. For reduced device cost, thus, each of diodes D3to D6is made of silicon (Si) that is a semiconductor other than the wide bandgap semiconductor. For a reduced loss of transistor Q3, transistor Q3is made of silicon carbide (SiC) that is a wide bandgap semiconductor, which is, for example, an N-channel MOS transistor.

An operation of this converter will now be described. The gates of transistors Q1to Q3are supplied respectively with pulse width modulation (PWM) signals φ1to φ3from a controller (not shown).FIGS. 2 (a) to (d)show how PWM signals φ1to φ3are generated and also the waveforms of these signals. In particular,FIG. 2(a)shows the waveforms of a sine-wave command value signal CM, a positive-side triangular wave carrier signal CA1, and a negative-side triangular wave carrier signal CA2, andFIGS. 2(b) to (d)respectively show the waveforms of PWM signals φ2B, φ1B, and φ3. PWM signals φ2B and φ1B are respectively inversion signals of PWM signals φ2and φ1.

With reference toFIGS. 2(a) to (d), the frequency of sine-wave command value signal CM is, for example, a commercial frequency. The phase of sine-wave command value signal CM is the same as, for example, the phase of AC voltage VAC of the commercial frequency. Carrier signals CA1and CA2have the same cycle and phase. The cycles of carrier signals CA1and CA2are sufficiently smaller than the cycle of sine-wave command value signal CM.

The level of sine-wave command value signal CM is compared with the level of positive-side triangular wave carrier signal CA1. When the level of sine-wave command value signal CM is higher than the level of positive-side triangular wave carrier signal CA1, PWM signal φ1B is set to “L” level, and PWM signal φ1is set to “H” level. When the level of sine-wave command value signal CM is lower than the level of positive-side triangular wave carrier signal CAL PWM signal φ1B is set to “H” level, and PWM signal φ1is set to “L” level.

Thus, PWM signal φ1is set to “H” level and “L” level in synchronization with carrier signal CA1during a period in which the level of sine-wave command value signal CM is positive, and PWM signal φ1is fixed to “L” level during a period in which the level of sine-wave command value signal CM is negative.

The ratio between the time in which the PWM signal is set to “H” level in one cycle and the time of one cycle of the PWM signal is referred to as a duty ratio. During a period in which the level of sine-wave command value signal CM is positive, the duty ratio of PWM signal φ1is largest in the vicinity of a positive peak (90 degrees) of sine-wave command value signal CM, decreases as farther from the peak, and is smallest in the vicinity of 0 degrees and in the vicinity of 180 degrees. During a period in which the level of sine-wave command value signal CM is negative, the duty ratio of PWM signal φ1is fixed to 0.

The level of sine-wave command value signal CM is compared with the level of negative-side triangular wave carrier signal CA2. When the level of sine-wave command value signal CM is higher than the level of negative-side triangular wave carrier signal CA2, PWM signal φ2B is set to “H” level, and PWM signal φ2is set to “L” level. When the level of sine-wave command value signal CM is lower than the level of negative-side triangular wave carrier signal CA2, PWM signal φ2B is set to “L” level, and PWM signal φ2is set to “H” level.

During a period in which the level of sine-wave command value signal CM is positive, thus, PWM signal φ2is fixed to “L” level. During a period in which the level of sine-wave command value signal CM is negative, PWM signal φ2is set to “H” level and “L” level in synchronization with carrier signal CA2. During a period in which the level of sine-wave command value signal CM is negative, the duty ratio of PWM signal φ2is largest in the vicinity of a positive peak (270 degrees) of sine-wave command value signal CM, decreases as farther from the peak, and is smallest in the vicinity of 180 degrees and in the vicinity of 360 degrees. During a period in which the level of sine-wave command value signal CM is positive, the duty ratio of PWM signal φ2is fixed to 0.

PWM signal φ3is an AND signal of PWM signals φ2B and φ1B. PWM signal φ3is set to “H” level and “L” level in synchronization with carrier signals CA1and CA2. During a period in which the level of sine-wave command value signal CM is positive, the duty ratio of PWM signal φ3is smallest in the vicinity of a positive peak (90 degrees) of sine-wave command value signal CM, increases as farther from the peak, and is largest in the vicinity of 0 degrees and in the vicinity of 180 degrees. During a period in which the level of sine-wave command value signal CM is negative, the duty ratio of PWM signal φ3is smallest in the vicinity of a negative peak (270 degrees) of sine-wave command value signal CM, increases as farther from the peak, and is largest in the vicinity of 180 degrees and in the vicinity of 360 degrees.

A current flowing through each of diodes D1to D6and transistors Q1to Q3during the operation of the converter will now be described. It is assumed that the power factor is 1.0 and that sine-wave command value signal CM and AC voltage VAC match in phase. During a period in which the level of sine-wave command value signal CM is positive, PWM signals φ1and φ3are alternately set to “H” level, and PWM signal φ2is fixed to “L” level.

During this period, when DC voltage V1is lower than rated voltage V1R, and when PWM signals φ1and φ3are set respectively to “H” level and “L” level, transistor Q3is turned off and a current I1at a level that corresponds to the level of AC voltage VAC flows from input terminal T0via diode D1to output terminal T1. At this time, no current flows through transistor Q1.

During this period, when the power is regenerated from the load (not shown) to battery B1and DC voltage V1exceeds rated voltage V1R, and when PWM signals φ1and φ3are set respectively to “H” level and “L” level, transistor Q1is turned on and transistor Q3is turned off. This allows a current I1at a level that corresponds to the levels of DC voltage V1and AC voltage VAC to flow from output terminal T1via transistor Q1to input terminal T0, so that DC voltage V1decreases to rated voltage V1R.

When PWM signals φ1and φ3are set respectively to “L” level and “H” level, transistor Q1is turned off and transistor Q3is turned on, allowing a current I1A at a level that complements current I1to flow through a path from input terminal T0via diode D3, transistor Q3, and diode D6to output terminal T3.

During this period, the effective value of the current flowing through diode D1is largest among diodes D1to D6and transistors Q1to Q3, and a switching loss occurs in transistor Q3. A reverse bias voltage is applied to diode D1every time transistor Q3changes from on state to off state, so that diode D1performs a reverse recovery operation. During this period, no current flows through diodes D2, D4, and D5. Since DC voltage V1exceeds rated voltage V1R for a short period of time, a low loss occurs in transistor Q1.

During a period in which the level of sine-wave command value signal CM is negative, PWM signals φ2and φ3are alternately set to “H” level, and PWM signal φ1is fixed to “L” level. During this period, when DC voltage V2is higher than rated voltage V2R, and when PWM signals φ2and φ3are set respectively to “H” level and “L” level, transistor Q3is turned off, allowing a current I2at a level that corresponds to the levels of DC voltage V2and AC voltage VAC to flow from output terminal T2via diode D2to input terminal T0. At this time, no current flows through transistor Q2. Rated voltage V2R is a voltage that is a difference between the negative-side peak value of AC voltage VAC and the threshold voltage of diode D2.

During this period, when, for example, the power is regenerated from the load (not shown) to battery B2and DC voltage V2falls below rated voltage V2R, and when PWM signals φ2and φ3are set respectively to “H” level and “L” level, transistor Q2is turned on and transistor Q3is turned off. This allows a current I2at the level that corresponds to the levels of DC voltage V2and AC voltage VAC to flow from input terminal T0via transistor Q2to output terminal T2, so that DC voltage V2increases to rated voltage V2R.

When PWM signals φ2and φ3are set respectively to “L” level and “H” level, transistor Q2is turned off and transistor Q3is turned on, allowing a current I2A at a level that complements a current I2to flow through a path from output terminal T3via diode D4, transistor Q3, and diode D5to input terminal T0.

During this period, the effective value of the current flowing through diode D2is largest among diodes D1to D6and transistors Q1to Q3, and a switching loss occurs in transistor Q3. A reverse bias voltage is applied to diode D2every time transistor Q3changes from off state to on state, so that diode D2performs the reverse recovery operation. During this period, no current flows through diodes D1, D3, and D6. Since DC voltage V2falls below rated voltage V2R in a short period of time, the loss generated in transistor Q2is low.

In summary, a large current flows through diodes D1and D2, so that diodes D1and D2perform the reverse recovery operation. A current smaller than the current through diodes D1and D2flows through diodes D3to D6, so that diodes D3to D6do not perform the reverse recovery operation. A current flows through transistor Q3, and a switching loss occurs in transistor Q3. A current flows through transistors Q1and Q2in a short period of time, and losses that occur in transistors Q1and Q2are low.

Thus, Schottky barrier diodes that are made of SiC being a wide bandgap semiconductor and have a rated current of a large value (e.g., 600 A) are used as diodes D1and D2as described, thereby reducing a recovery loss during the reverse recovery operation. Diodes that are made of Si being a semiconductor other than the wide bandgap semiconductor and have a rated current of a small value (e.g., 450 A) are used as diodes D3to D6, thereby reducing cost.

Further, an N-channel MOS transistor that is made of SiC being a wide bandgap semiconductor and has a rated current of a large value (e.g., 500 A) is used as transistor Q3, thus reducing a switching loss. IGBTs that are made of Si being a semiconductor other than a wide bandgap semiconductor and have a rated current of a small value (e.g., 450 A) are used as transistors Q1and Q2, thereby reducing cost.

FIG. 3(a)is a time chart showing a switching operation of an N-channel MOS transistor (referred to as a Si transistor) made of Si, andFIG. 3(b)is a time chart showing a switching operation of an N-channel MOS transistor (referred to as a SiC transistor) made of SiC.

With reference toFIGS. 3(a) and (b), it is assumed that in the initial state, a gate signal (not shown) is set to “H” level to turn on the transistor, a constant current I flows through the transistor, and a drain-source voltage Vds is 0 V. When the gate signal is lowered from “H” level to “L” level to turn off the transistor at a certain time, current I decreases and voltage Vds increases.

As can be seen fromFIGS. 3(a) and (b), a time Ta taken for current I to start dropping to reach 0 A in the Si transistor is longer than a time Tb taken for current I to start dropping to reach 0 A in the SiC transistor. In the Si transistor, current I decreases rapidly down to a certain value but changes from the certain value to 0 A for a longer period of time. The current flowing while changing from a certain value to 0 A is referred to as a tail current.

In the SiC transistor, contrastingly, current I decreases rapidly, and a slight overshoot occurs. The switching loss of a transistor, which is the product of current I and voltage Vds, corresponds to the area of a hatched portion in the drawing. The switching loss of the SiC transistor is thus lower than the switching loss of the Si transistor.

FIG. 4shows the appearance of the converter shown inFIG. 1. With reference toFIG. 4, the converter includes one semiconductor module M1. Semiconductor module M1is internally provided with diodes D1to D4and transistors Q1to Q3. Semiconductor module M1is externally provided with input terminal T0and output terminals T1to T3. Although semiconductor module M1is externally provided with signal terminals for supplying PWM signals φ1to φ3to the gates of transistors Q1to Q3, the signal terminals are not shown for simplicity of the drawing.

FIG. 5is a circuit block diagram showing a configuration of an uninterruptible power system including the converter shown inFIG. 1. With reference toFIG. 5, the uninterruptible power system includes an input filter1, a converter2, a DC positive bus L1, a DC negative bus L2, a DC neutral point bus L3, capacitors C1and C2, an inverter3, an output filter4, and a controller5.

Input filter1, which is a low pass filter, allows the AC power of a commercial frequency from commercial AC power supply10to pass through input terminal T0of converter2and also prevents a signal of a carrier frequency generated in converter2from passing toward commercial AC power supply10.

DC positive bus L1, DC negative bus L2, and DC neutral point bus L3have first terminals connected respectively to output terminals T1, T2, and T3of converter2, and second terminals connected to three respective input terminals of inverter3. Capacitor C1is connected between buses L1and L3, and capacitor C2is connected between buses L3and L2. Buses L1and L3are connected respectively to the positive electrode and negative electrode of battery B1, and buses L3and L2are connected respectively to the positive electrode and negative electrode of battery B2.

During a normal operation in which AC power is supplied normally from commercial AC power supply10, converter2converts AC power supplied from commercial AC power supply10via input filter1into DC power and supplies the DC power to each of batteries B1and B2and also to inverter3. Each of batteries B1and B2stores the DC power.

In other words, converter2is controlled by PWM signals φ1to φ3supplied from controller5, generates DC voltages V1to V3based on AC voltage VAC supplied from commercial AC power supply10via input filter1, and supplies DC voltages V1to V3generated respectively to DC positive bus L1, DC negative bus L2, and DC neutral point bus L3. If output terminal T3is grounded, DC voltages V1to V3are respectively a positive voltage, a negative voltage, and 0 V. DC voltages V1to V3are smoothed by capacitors C1and C2. DC voltages V1to V3are supplied to batteries B1and B2and inverter3. During a power failure in which a supply of AC power from commercial AC power supply10is stopped, transistor Q1is fixed to off state, so that the operation of converter2is stopped.

Inverter3converts DC power generated in converter2into AC power during a normal operation in which commercial AC power supply10supplies AC power normally and converts DC power of batteries B1and B2into AC power during a power failure in which a supply of AC power from commercial AC power supply10is stopped.

In other words, inverter3generates an AC voltage at three levels based on DC voltages V1to V3supplied from converter2via buses L1to L3during a normal operation and generates AC voltage at three levels based on DC voltages V1to V3supplied from batteries B1and B2via buses L1to L3during a power failure.

Output filter4is connected between the output terminal of inverter3and load11. Output filter4, which is a low pass filter, allows the AC power having a commercial frequency of the AC power output from inverter3to pass through load11and prevents a signal having a carrier frequency which is generated in inverter3from passing toward load11. In other words, output filter4converts the output voltage of inverter3into a sine wave of a commercial frequency and supplies the sine wave to load11.

Controller5controls converter2and inverter3by supplying a PWM signal while monitoring, for example, the AC voltage from commercial AC power supply10, the AC voltage output to load11, and DC voltages V1to V3.

The operation of this uninterruptible power system will now be described. During a normal operation in which commercial AC power supply10supplies AC power normally, the AC power from commercial AC power supply10is supplied to converter2via input filter1and is converted into DC power by converter2. The DC power generated in converter2is stored in batteries B1and B2and is also supplied to inverter3, and is then converted into AC power of a commercial frequency by inverter3. The AC power generated in inverter3is supplied to load11via output filter4, thereby operating load11.

At the occurrence of regenerated power in load11, the regenerated power is returned to commercial AC power supply10via output filter4, inverter3, buses L1to L3, converter2, and input filter1.

During a power failure in which a supply of AC power from commercial AC power supply10is stopped, the operation of converter2is stopped, and the DC power of batteries B1and B2is supplied to inverter3and is then converted into AC power of a commercial frequency by inverter3. The AC power generated in inverter3is supplied to load11via output filter4, so that the operation of load11is continued.

Even when a power failure occurs, thus, the operation of load11is continued as long as batteries B1and B2store DC power. Upon restart of a supply of the AC power from commercial AC power supply10, converter2restarts the operation, and the DC power generated in converter2is supplied to batteries B1and B2and inverter3, returning to the original state.

As described above, since a converter is composed of three transistors Q1to Q3and six diodes D1to D6, fewer semiconductor elements can be used than in a conventional case, thereby reducing the size and cost of the device. Besides, since diodes D1and D2that perform the reverse recovery operation and transistor Q3that switches a current are made of wide bandgap semiconductors, a recovery loss and a switching loss can be reduced. Further, since diodes D3to D6that do not perform the reverse recovery operation and transistors Q1and Q2that allow a current to flow during only the regeneration operation are made of semiconductors other than wide bandgap semiconductors, thereby reducing cost.

Although SiC is used as the wide bandgap semiconductor in Embodiment 1, the present invention is not limited to this. Other semiconductors can be used as long as they are wide bandgap semiconductors. For example, gallium nitride (GaN) can be used as the wide bandgap semiconductor.

FIG. 6is a circuit block diagram showing a configuration of inverter3of an uninterruptible power system according to Embodiment 2 of the present invention. The general arrangement of the uninterruptible power system is as shown inFIG. 5. Converter2of the uninterruptible power system is the converter shown inFIG. 1. With reference toFIG. 6, inverter3includes input terminals T11to T13(first to third output terminals), an output terminal T14(fourth output terminal), transistors Q11to Q14(fourth to seventh transistors), and diodes D11to D14(seventh to tenth diodes).

Input terminals T11to T13are connected respectively to DC positive bus L1, DC negative bus L2, and DC neutral point bus L3ofFIG. 5. Input terminals T11and T13are connected respectively with the positive electrode and negative electrode of battery B1. Input terminals T13and T12are connected respectively with the positive electrode and negative electrode of battery B2. Each of batteries B1and B2outputs DC voltage. The output voltage of battery B1is equal to the output voltage of battery B2. Thus, DC voltages V1, V2, and V3are applied respectively to input terminals T11, T12, and T13, and V1>V3>V2and V3=(V1+V2)/2. This inverter converts DC voltages V1to V3applied to input terminals T11to T13into an AC voltage V4at three levels and then outputs AC voltage V4to output terminal T14. If input terminal T13is grounded, DC voltages V1to V3are respectively a positive voltage, a negative voltage, and 0 V.

Each of transistors Q11and Q12is made of silicon carbide (SiC) that is a wide bandgap semiconductor, which is an N-channel MOS transistor, for example. The rated current of each of transistors Q11and Q12is, for example, 600 A and is greater than the rated current of each of transistors Q13and Q14and diodes D11to D14. Each of transistors Q13and Q14is made of silicon (Si) that is a semiconductor other than a wide bandgap semiconductor, which is an IGBT, for example. The rated current of each of transistors Q13and Q14is 450 A, for example.

Each of diodes D11and D12is made of silicon (Si) made of a semiconductor other than a wide bandgap semiconductor. The rated current of each of diodes D11and D12is 300 A, for example.

Each of diodes D13and D14is a Schottky barrier diode made of silicon carbide (SiC) that is a wide bandgap semiconductor. The rated current of each of diodes D13and D14is 500 A, for example. The rated current of each of transistors Q11and Q12is greater than the rated current of each of transistors Q13and Q14and diodes D11to D14.

The reason why the specifications of transistors Q11and Q12differ from the specifications of transistors Q13and Q14and the specifications of diodes D11and D12differ from the specifications of diodes D13and D14will be described below.

Transistor Q11has a drain (first electrode) connected to input terminal T11and a source (second electrode) connected to output terminal T14. Diode D11has an anode connected to output terminal T14and a cathode connected to input terminal T11.

Transistor Q12has a drain connected to output terminal T14and a source connected to input terminal T12. Diode D12has an anode connected to input terminal T12and a cathode connected to output terminal T14. That is to say, diodes D11and D12are connected respectively in anti-parallel with transistors Q11and Q12.

Transistors Q13and Q14have collectors (first electrodes) connected to each other and emitters (second electrodes) connected respectively to input terminal T13and output terminal T14. Diodes D13and D14have cathodes connected together to the collectors of transistors Q13and Q14and anodes connected respectively to input terminal T13and output terminal T14. That is to say, diodes D13and D14are connected respectively in anti-parallel with transistors Q13and Q14. Transistors Q13and Q14and diodes D13and D14constitute a second bidirectional switch connected between input terminal T13and output terminal T14.

The operation of this inverter will now be described. The gates of transistors Q11to Q14are supplied respectively with PWM signals φ11to φ14from controller5.FIGS. 7(a) to (e)show how PWM signals φ11to φ14are generated and the waveforms of these signals. In particular,FIG. 7(a)shows the waveforms of sine-wave command value signal CM, positive-side triangular wave carrier signal CA1, and negative-side triangular wave carrier signal CA2, andFIGS. 7(b) to (e)respectively show the waveforms of PWM signals φ11, φ14, φ13, and φ12.

With reference toFIGS. 7(a) to (e), the frequency of sine-wave command value signal CM is, for example, a commercial frequency. Carrier signals CA1and CA2have the same cycle and phase. The cycles of carrier signals CA1and CA2are sufficiently smaller than the cycle of sine-wave command value signal CM.

The level of sine-wave command value signal CM is compared with the level of positive-side triangular wave carrier signal CA1. When the level of sine-wave command value signal CM is higher than the level of positive-side triangular wave carrier signal CA1, PWM signals φ11and φ13are set respectively to “H” level and “L” level. When the level of sine-wave command value signal CM is lower than the level of positive-side triangular wave carrier signal CA1, PWM signals φ11and φ13are set respectively to “L” level and “H” level.

During a period in which the level of sine-wave command value signal CM is positive, thus, PWM signals φ11and φ13are alternately set to “H” level in synchronization with carrier signal CA1, so that transistors Q11and Q13are alternately turned on. During a period in which the level of sine-wave command value signal CM is negative, PWM signals φ11and φ13are set respectively to “L” level and “H” level, and the transistor Q11is fixed to off state and transistor Q13is fixed to on state.

The level of sine-wave command value signal CM is compared with the level of negative-side triangular wave carrier signal CA2. When the level of sine-wave command value signal CM is higher than the level of negative-side triangular wave carrier signal CA2, PWM signals φ12and φ14are set respectively to “L” level and “H” level. When the level of sine-wave command value signal CM is lower than the level of negative-side triangular wave carrier signal CA2, PWM signals φ12and φ14are set respectively to “H” level and “L” level.

During a period in which the level of sine-wave command value signal CM is positive, thus, PWM signals φ12and φ14are set respectively to “L” level and “H” level, and transistor Q12is fixed to off state and transistor Q14is fixed to on state. During a period in which the level of sine-wave command value signal CM is negative, PWM signals φ12and φ14are alternately set to “H” level in synchronization with carrier signal CA2, so that transistors Q12and Q14are alternately turned on.

The ratio between the time in which the PWM signal is set to “H” level in one cycle and the time of one cycle of the PWM signal is referred to as a duty ratio. During a period in which the level of sine-wave command value signal CM is positive, the duty ratio of PWM signal φ11is largest in the vicinity of a positive peak (90 degrees) of sine-wave command value signal CM, decreases as farther from the peak, and is zero in the vicinity of 0 degrees and in the vicinity of 180 degrees. The duty ratio of PWM signal φ11is fixed to zero during a period in which the level of sine-wave command value signal CM is negative. PWM signal φ13is an inversion signal of PWM signal φ11.

The duty ratio of PWM signal φ12is fixed to zero during a period in which the level of sine-wave command value signal CM is positive. The duty ratio of PWM signal φ12is largest in the vicinity of a negative peak (270 degrees) of sine-wave command value signal CM, decreases as farther from the peak, and is zero in the vicinity of 180 degrees and in the vicinity of 360 degrees. The duty ratio of PWM signal φ12is fixed to zero during a period in which the level of sine-wave command value signal CM is positive. PWM signal φ14is an inversion signal of PWM signal φ12.

The current flowing through each of transistors Q11to Q14and diodes D11to D14during the operation of the inverter will now be described. It is assumed as shown inFIG. 8that the current flowing from input terminal T11to output terminal T14is I11, the current flowing from output terminal T14to input terminal T12is I12, the current flowing from input terminal T13to output terminal T14is I13, and the current flowing from output terminal T14to input terminal T13is I14.

FIGS. 9(a) to (i)are time charts showing the operation of the inverter. In particular,FIG. 9(a)shows the waveforms of sine-wave command value signal CM, positive-side triangular wave carrier signal CA1, and negative-side triangular wave carrier signal CA2,FIGS. 9(b), (d), (f), and (h)respectively show the waveforms of PWM signals φ11, φ14, φ13, and φ12, andFIGS. 9(c), (e), (g), and (i)respectively show the waveforms of currents I11, I14, I13, and I12. The positive currents of currents I11to I14show the currents flowing through transistor Q, and the negative currents thereof show the currents flowing through diode D. Shown here is the case in which the power factor is 1.0.

With reference toFIGS. 9(a) to (i), during a period in which the level of sine-wave command value signal CM is positive, PWM signals φ14and φ12are fixed respectively to “H” level and “L” level, and PWM signals φ11and φ13are alternately set to “H” level. Thus, transistors Q14and Q12are fixed respectively to on state and off state, so that transistors Q11and Q13are alternately turned on and DC voltages V1and V3alternately appear at output terminal T14.

During this period, current I11at the level that corresponds to on time of transistor Q11flows when transistor Q11is turned on, and current I13at the level that complements current I11flows through a path formed of diode D13and transistor Q14when transistor Q11is turned off.

Since transistor Q12is fixed to off state, no current flows through transistor Q12, and no switching loss occurs in transistor Q12. Since a current flows through diode D13and no current flows through transistor Q13though transistor Q13is turned on/off, no switching loss occurs in transistor Q13. Since transistor Q14is fixed to on state, a current flows through transistor Q14, but no switching loss occurs in transistor Q14. During this period, thus, the effective value of the current flowing through transistor Q11is largest and the switching loss in transistor Q11is largest among transistors Q11to Q14.

A reverse bias voltage is applied to diode D13every time transistor Q11changes from off state to on state, so that diode D13performs the reverse recovery operation. During this period, no current flows through diodes D11, D12, and D14.

During a period in which the level of sine-wave command value signal CM is negative, PWM signals φ13and φ11are fixed respectively to “H” level and “L” level, and PWM signals φ12and φ14are alternately set to “H” level. Thus, transistors Q13and Q11are fixed respectively to on state and off state, and transistors Q12and Q14are alternately turned on, so that DC voltages V2and V3alternately appear at output terminal T14.

During this period, current I12at the level that corresponds to on time of transistor Q12flows when transistor Q12is turned on, and current I13flows through a path formed of diode D14and transistor Q13when transistor Q12is turned off.

Since transistor Q11is fixed to off state, no current flows through transistor Q11, and no switching loss occurs in transistor Q11. Since a current flows through diode D14and no current flows through transistor Q14though transistor Q14is turned on/off, no switching loss occurs in transistor Q14. Since transistor Q13is fixed to on state, a current flows through transistor Q13but no switching loss occurs in transistor Q13. During this period, thus, the effective value of the current flowing through transistor Q12is largest and the switching loss in transistor Q12is largest among transistors Q11to Q14.

A reverse bias voltage is applied to diode D14every time transistor Q12changes from off state to on state, so that diode D14performs the reverse recovery operation. During this period, no current flow through diodes D11, D12, and D13.

In summary, a large current flows through transistors Q11and Q12, and a switching loss occurs in transistors Q11and Q12. A current smaller than the current through transistors Q11and Q12flows through transistors Q13and Q14, and no switching loss occurs in transistors Q13and Q14.

N-channel MOS transistors that are made of SiC being a wide bandgap semiconductor and have a rated current of a large value (e.g., 600 A) are used as transistors Q11and Q12as described above, thereby reducing switching loss. IGBTs that are made of Si being a semiconductor other than the wide bandgap semiconductor and have a rated current of a small value (e.g., 450 A) are used as transistors Q13and Q14, thereby reducing cost.

A current equivalent to the current through transistors Q13and Q14flows through diodes D13and D14, so that diodes D13and D14perform the reverse recovery operation. No current flows through diodes D11and D12. As is commonly known, diodes D11and D12are provided to protect transistors Q11and Q12from a voltage generated in an inductor when the inductor is used as the load.

Thus, Schottky barrier diodes that are made of SiC being a wide bandgap semiconductor and have a rated current of a value (e.g., 500 A) equivalent to that of transistors Q13and Q14are used as diodes D13and D14as described above, thereby reducing recovery loss during the reverse recovery operation. Diodes that are made of Si being a semiconductor other than the wide bandgap semiconductor and have a rated current of a small value (e.g., 300 A) are used as diodes D11and D12, thereby reducing cost.

FIG. 10shows the appearance of inverter3shown inFIG. 6. With reference toFIG. 10, inverter3includes one semiconductor module M2. Semiconductor module M2is internally provided with transistors Q1to Q14and diodes D11to D14. Semiconductor module M2is externally provided with input terminals T11to T13and output terminal T14. Further, although semiconductor module M2is externally provided with four signal terminals for supplying PWM signals φ11to φ14to the gates of transistors Q11to Q14, the four terminals are not shown for simplicity of the drawing.

As described above, N-channel MOS transistors made of wide bandgap semiconductors are used as transistors Q11and Q12that turn on/off current and IGBTs made of semiconductors other than wide bandgap semiconductors are used as transistors Q13and Q14that do not turn on/off current in Embodiment 2, thus reducing switching loss and cost.

Further, Schottky barrier diodes made of wide bandgap semiconductors are used as diodes D13and D14that perform the reverse recovery operation and diodes made of semiconductors other than wide bandgap semiconductors are used as diodes D11and D12that do not perform the reverse recovery operation, thus reducing the recovery loss and cost.

Although SiC is used as a wide bandgap semiconductor in Embodiment 2, the present invention is not limited to this. Any other semiconductor can be used as long as it is a wide bandgap semiconductor. For example, gallium nitride (GaN) can be used as the wide bandgap semiconductor.

FIG. 11is a circuit diagram showing a configuration of an inverter of an uninterruptible power system according to Embodiment 3 of the present invention, which is compared withFIG. 6. With reference toFIG. 11, this inverter differs from inverter3ofFIG. 6in that the parallel connection structure of transistor Q13and diode D13and the parallel connection structure of transistor Q14and diode D14are replaced. Transistors Q13and Q14have emitters connected to each other and collectors connected respectively to input terminal T13and output terminal T14. Transistors Q11to Q14are controlled respectively by PWM signals φ11to φ14. When DC voltages V1and V3are alternately output to output terminal T14, transistor Q14is turned on and transistors Q11and Q13are alternately turned on. When DC voltages V2and V3are alternately output to output terminal T14, transistor Q13is turned on and transistors Q12and Q14are alternately turned on.

Since the other configuration and operation are the same as those of Embodiment 2, description thereof will not be repeated. Embodiment 3 also achieves the same effects as those of Embodiment 2.

FIG. 12is a circuit diagram showing a configuration of an inverter of an uninterruptible power system according to Embodiment 4 of the present invention, which is compared withFIG. 6. With reference toFIG. 12, this inverter differs from inverter3ofFIG. 6in that the collectors of transistors Q13and Q14are isolated from the cathodes of diodes D13and D14, the collector of transistor Q13and the cathode of diode D14are connected, and the collector of transistor Q14and the cathode of diode D13are connected.

Transistors Q11to Q14are controlled respectively by PWM signals φ11to φ14. When DC voltages V1and V3are alternately output to output terminal T14, transistor Q14is turned on and transistors Q11and Q13are alternately turned on. When DC voltages V2and V3are alternately output to output terminal T14, transistor Q13is turned on and transistors Q12and Q14are alternately turned on.

Since the other configuration and operation are the same as those of Embodiment 2, description thereof will not be repeated. Embodiment 4 also achieves the same effects as those of Embodiment 2.

FIG. 13is a circuit block diagram showing a configuration of an uninterruptible power system according to Embodiment 5 of the present invention.FIG. 14is a circuit diagram showing configurations of a converter22and an inverter24shown inFIG. 13.FIG. 15is a circuit diagram showing a configuration of a bidirectional chopper23shown inFIG. 13. With reference toFIGS. 13 to 15, the uninterruptible power system includes an input filter21, converter22, a DC positive bus L1, a DC negative bus L2, a DC neutral point bus L3, capacitors C1and C2, bidirectional chopper23, inverter24, and an output filter25. For simplicity of the drawing, a controller that controls converter22, bidirectional chopper23, and inverter24will not be shown.

Input filter21includes reactors31to33and capacitors34to36. Reactors31to33have first terminals that respectively receive three-phase AC voltages VU, VV, and VW from commercial AC power supply20and second terminals connected respectively to input terminals T0ato T0cof converter22. Capacitors34to36have first electrodes connected respectively to the first terminals of reactors31to33and second electrodes connected together to neutral point NP. Reactors31to33and capacitors34to36constitute a low pass filter. Input filter21allows the three-phase AC power of a commercial frequency from commercial AC power supply20to pass through converter22and also prevents a signal of a carrier frequency generated in converter22from passing toward commercial AC power supply20.

DC positive bus L1, DC negative bus L2, and DC neutral point bus L3have first terminals connected respectively to output terminals T1, T2, and T3of converter22and second terminals connected respectively to input terminals T11, T12, and T13of inverter24. Capacitor C1is connected between buses L1and L3, and capacitor C2is connected between buses L3and L2. Buses L1to L3are connected to battery B11via bidirectional chopper23.

Diodes D1ato D1chave anodes connected respectively to input terminals T0ato T0cand cathodes connected together to output terminal T1. Diodes D2ato D2chave anodes connected together to output terminal T2and cathodes connected respectively to input terminals T0ato T0c.

Transistors Q1ato Q1chave collectors connected together to output terminal T1and emitters connected respectively to input terminals T0ato T0c. Transistors Q2ato Q2chave collectors connected respectively to input terminals T0ato T0cand emitters connected together to output terminal T2.

Transistors Q1ato Q1care connected respectively by PWM signals φ1a, φ1b, and φ1cfrom the controller (not shown). The waveforms of PWM signals φ1a, φ1b, and φ1care similar to the waveform of the inversion signal of PWM signal φ1B shown inFIG. 2(c). The phases of PWM signals φ1a, φ1b, and φ1care synchronized respectively with the phases of three-phase AC voltages VU, VV, and VW, and are shifted from each other by 120 degrees.

Transistors Q2ato Q2care controlled respectively by PWM signals φ2a, φ2b, and φ2cfrom the controller (not shown). The waveforms of PWM signals φ2a, φ2b, and φ2care similar to the waveform of the inversion signal of PWM signal φ2B shown inFIG. 2(b). The phases of PWM signals φ2a, φ2b, and φ2care synchronized respectively with the phases of three-phase AC voltages VU, VV, and VW and are shifted from each other by 120 degrees.

Bidirectional switches S1ato S1chave first terminals connected respectively to input terminals T0ato T0cand second terminals connected together to output terminal T3. Each of bidirectional switches S1ato S1cincludes diodes D3to D6and N-channel MOS transistor Q3as shown inFIG. 1.

The anode of diode D3and the cathode of diode D5are connected together to input terminal T0a(or T0bor T0c). The anode of diode D4and the cathode of diode D6are connected together to output terminal T3. The cathodes of diodes D3and D4are connected to each other, and the anodes of diodes D5and D6are connected to each other. The drain of transistor Q3is connected to the cathodes of diodes D3and D4, and the source of transistor Q3is connected to the anodes of diodes D5and D6.

Transistors Q3of bidirectional switches S1ato S1care controlled respectively by PWM signals φ3a, φ3b, and φ3cfrom the controller (not shown). The waveforms of PWM signals φ3a, φ3b, and φ3care similar to the waveform of PWM signal φ3shown inFIG. 2(d). The phases of PWM signals φ3a, φ3b, and φ3care synchronized respectively with the phases of three-phase AC voltages VU, VV, and VW and are shifted from each other by 120 degrees.

That is to say, input terminal T0a, output terminals T1to T3, diodes D1aand D2a, transistors Q1aand Q2a, and bidirectional switch S1aconstitute the converter shown inFIG. 1, and the converter converts AC voltage VU into DC voltages V1to V3and outputs these DC voltages to output terminals T1to T3. Input terminal T0b, output terminals T1to T3, diodes D1band D2b, transistors Q1band Q2b, and bidirectional switch S1bconstitute the converter shown inFIG. 1, and the converter converts AC voltage VV into DC voltages V1to V3and outputs these DC voltages to output terminals T1to T3.

Input terminal T0c, output terminals T1to T3, diodes D1cand D2c, transistors Q1cand Q2c, and bidirectional switch S1cconstitute the converter shown inFIG. 1, and the converter converts AC voltage VW into DC voltages V1to V3and outputs these DC voltages to output terminals T1to T3. Converter22converts three-phase AC voltages VU, VV, and VW into DC voltages V1to V3and outputs these DC voltages to output terminals T1to T3.

As described in Embodiment 1, diodes D1ato D1cand D2ato D2cand transistors Q3of bidirectional switches S1ato S1care made of wide bandgap semiconductors, and transistors Q1ato Q1cand Q2ato Q2cand diodes D3to D6of bidirectional switches S1ato S1care made of semiconductors other than the wide bandgap semiconductors. The rated current of each of diodes D1ato D1cand D2ato D2cis greater than the rated current of each of transistors Q1ato Q1cand Q2ato Q2c, diodes D3to D6, and transistor Q3. The rated current of each of transistors Q1ato Q1cand Q2ato Q2cis smaller than the rated current of each of diodes D1ato D1c, D2ato D2c, and D3to D6, and transistor Q3.

During the normal operation in which commercial AC power supply20supplies three-phase AC power normally, converter22converts the three-phase AC power supplied from commercial AC power supply20via input filter21into DC power and supplies the DC power to battery B11via bidirectional chopper23and also to inverter24. Battery B11stores DC power.

In other words, converter22is controlled by PWM signals φ1ato φ1c, φ2ato φ2c, and φ3ato φ3csupplied from the controller (not shown), generates DC voltages V1to V3based on three-phase AC voltages VU, VV, and VW supplied from commercial AC power supply20via input filter21, and supplies DC voltages V1to V3generated respectively to DC positive bus L1, DC negative bus L2, and DC neutral point bus L3. When output terminal T3is grounded, DC voltages V1to V3are respectively a positive voltage, a negative voltage, and 0 V.

When voltage V1at output terminal T1is higher than rated voltage V1R due to the regenerated power generated in load26, a current flows from output terminal T1via transistors Q1ato Q1cto input terminals T0ato T0c, so that voltage V1at output terminal T1decreases to rated voltage V1R. When voltage V2at output terminal T2falls below rated voltage V2R due to the regenerated power generated in load26, a current flows from input terminals T0ato T0cvia transistors Q2ato Q2cto output terminal T2, so that voltage V2at output terminal T2rises to rated voltage V2R.

DC voltages V1to V3are smoothed by capacitors C1and C2. DC voltages V1to V3are supplied to battery B11via bidirectional chopper23and are also supplied to inverter24. During a power failure in which a supply of AC power from commercial AC power supply20is stopped, transistors Q1ato Q1c, Q2ato Q2c, and Q3are set to off state, so that the operation of converter22is stopped.

Bidirectional chopper23supplies DC power from capacitors C1and C2to battery B11when three-phase AC power is supplied from commercial AC power supply20, and supplies DC power from battery B11to capacitors C1and C2when a supply of three-phase AC power is stopped from commercial AC power supply20, that is, during a power failure.

That is to say, as shown inFIG. 15, bidirectional chopper23includes terminals T21to T25, transistors Q21to Q24, diodes D21to D24, and a normal-mode reactor (DC reactor)40. Terminals T21to T23are connected respectively to DC positive bus L1, DC negative bus L2, and DC neutral point bus L3. Terminals T24and T25are connected respectively to the positive electrode and negative electrode of battery B11.

Transistors Q21and Q22are connected in series between terminals T21and T23, and transistors Q23and Q24are connected in series between terminals T23and T22. Diodes D21to D24are connected respectively in anti-parallel with transistors Q21to Q24. Normal-mode reactor40includes a coil41connected between a node between transistors Q21and Q22and terminal T24, and a coil42connected between terminal T25and a node between transistors Q23and Q24.

Each of transistors Q21to Q24is an IGBT made of silicon (Si) that is a semiconductor other than a wide bandgap semiconductor. Each of diodes D21to D24is made of silicon (Si) that is a semiconductor other than a wide bandgap semiconductor.

When three-phase AC power is supplied from commercial AC power supply20, DC power is supplied from capacitors C1and C2via bidirectional chopper23to battery B11, charging battery B11. In this case, transistors Q22and Q23are set to off state, and transistors Q21and Q24are alternately turned on.

That is to say, in the first battery charge mode, transistors Q22to Q24are turned off, and transistor Q21is turned on. Consequently, a current flows from terminal T21via transistor Q21, coil41, battery B11, coil42, and diode D23to terminal T23, discharging capacitor C1to charge battery B11.

In the third battery charge mode, transistors Q21to Q23are turned off, and transistor Q24is turned on. Consequently, a current flows from terminal T23via diode D22, coil41, battery B11, coil42, and transistor Q24to terminal T22, discharging capacitor C2to charge battery B11.

The first battery charge mode and the third battery charge mode are performed alternately. During a period between the first battery charge mode and the third battery charge mode, electromagnetic energy stored in coils41and42is released, and a current flows through a path formed of diode D22, coil41, battery B11, coil42, and diode D23, charging battery B11. In the second battery charge mode, the first battery charge mode and the third battery charge mode coincide with each other.

When a supply of three-phase AC power from commercial AC power supply20is stopped, DC power is supplied from battery B11via bidirectional chopper23to capacitors C1and C2, charging capacitors C1and C2. In this case, transistors Q21and Q24are fixed to off state, and transistors Q22and Q23are alternately turned on.

That is to say, in the first battery discharge mode, transistors Q21, Q23, and Q24are turned off, and transistor Q22is turned on. Consequently, a current flows from the positive electrode of battery B11via coil41, transistor Q22, capacitor C2, diode D24, and coil42to battery B11, discharging battery B11to charge capacitor C2.

In the second battery discharge mode, transistors Q21to Q24are turned off. Consequently, a current flows from the positive electrode of battery B11via coil41, diode D21, capacitors C1and C2, diode D24, and coil42to the negative electrode of battery B11, discharging battery B11to charge capacitors C1and C2.

In the third battery discharge mode, transistors Q21, Q22, and Q24are turned off, and transistor Q23is turned on. Consequently, a current flows from the positive electrode of battery B11via coil41, diode D21, capacitor C1, transistor Q23, and coil42to the negative electrode of battery B11, discharging battery B11to charge capacitor C1.

The first battery discharge mode and the third battery discharge mode are performed alternately. During a period between the first battery discharge mode and the third battery discharge mode, the second battery discharge mode is performed if the voltage between terminals T21and T22is lower than the voltage across battery B11.

Transistors Q11ato Q11chave drains connected together to input terminal T11and sources connected respectively to output terminals T14ato T14c. Transistors Q12ato Q12chave drains connected respectively to output terminals T14ato T14cand sources connected together to input terminal T12. Diodes D11ato D11cand D12ato D12care connected respectively in anti-parallel with transistors Q11ato Q11cand Q12ato Q12c.

Bidirectional switches S2ato S2chave first terminals connected together to input terminal T13and second terminals connected respectively to output terminals T14ato T14c. Each of bidirectional switches S2ato S2cincludes transistors Q13and Q14and diodes D13and D14, as shown inFIG. 6.

The collectors of transistors Q13and Q14are connected to each other, the emitter of transistor Q13is connected to input terminal T13, and the emitter of transistor Q14is connected to output terminal T14a(or T14bor T14c). Diodes D13and D14are connected respectively in anti-parallel with transistors Q13and Q14.

Transistors Q11ato Q11care controlled respectively by PWM signals φ11a, φ11b, and φ11cfrom the controller (not shown). The waveforms of PWM signals φ11a, φ11b, and φ11care similar to the waveform of PWM signal φ11shown inFIG. 7(b). The phases of PWM signals φ11a, φ11b, and φ11care synchronized respectively with the phases of three-phase AC voltages VU, VV, and VW and are shifted from each other by 120 degrees.

Transistors Q12ato Q12care controlled respectively by PWM signals φ12a, φ12b, and φ12cfrom the controller (not shown). The waveforms of PWM signals φ12a, φ12b, and φ12care similar to the waveform of PWM signal φ12shown inFIG. 7(e). The phases of PWM signals φ12a, φ12b, and φ12care synchronized respectively with the phases of three-phase AC voltages VU, VV, and VW and are shifted from each other by 120 degrees.

That is to say, input terminals T11to T13, output terminal T14a, transistors Q11aand Q12a, diodes D11aand D12a, and bidirectional switch S2aconstitute the inverter shown inFIG. 6, and the converter converts DC voltages V1to V3into AC voltage V4aand outputs it to output terminal T14a.

Input terminals T11to T13, output terminal T14b, transistors Q11band Q12b, diodes D11band D12b, and bidirectional switch S2bconstitute the inverter shown inFIG. 6, and the inverter converts DC voltages V1to V3into AC voltage V4band outputs it to output terminal T14b.

Input terminals T11to T13, output terminal T14c, transistors Q11cand Q12c, diodes D11cand D12c, and bidirectional switch S2cconstitute the inverter shown inFIG. 6, and the inverter converts DC voltages V1to V3into AC voltage V4cand outputs it to output terminal T14c. AC voltages V4ato V4cchange respectively in synchronization with three-phase AC voltages VU, VV, and VW, and the phases of AC voltages V4ato V4care shifted from each other by 120 degrees.

As described in Embodiment 2, transistors Q11ato Q11cand Q12ato Q12cand diodes D13and D14of bidirectional switches S2ato S2care made of wide bandgap semiconductors, and diodes D11ato D11cand D12ato D12cand transistors Q13and Q14of bidirectional switches S2ato S2care made of semiconductors other than wide bandgap semiconductors. The rated current of each of transistors Q11ato Q11cand Q12ato Q12cis greater than the rated current of each of transistors Q13and Q14and diodes D11ato D11c, D12ato D12c, D13, and D14.

Inverter24converts the DC power generated in converter22into three-phase AC power during a normal operation in which three-phase AC power is supplied normally from commercial AC power supply20and converts the DC power supplied from battery B11via bidirectional chopper23into three-phase AC power during a power failure in which a supply of AC power from commercial AC power supply20is stopped.

As shown inFIG. 13, output filter25includes reactors51to53and capacitors54to56. Reactors51to53have first terminals connected respectively to output terminals T14ato T14cof inverter24and second terminals connected together to load26. Capacitors54to56have first electrodes connected respectively to the second terminals of reactors51to53and second electrodes connected together to neutral point NP. Reactors51to53and capacitors54to56constitute a low pass filter.

Output filter25allows AC power having a commercial frequency of the AC power output from inverter24to pass through load26and also prevents a signal having a carrier frequency generated in inverter24from passing toward load26. In other words, output filter25converts output voltages V4ato V4cof inverter24into three-phase AC voltages VR, VS, and VT with a sinusoidal signal of a commercial frequency and supplies these voltages to load26. Load26is driven by three-phase AC voltages VR, VS, and VT.

The controller (not shown) controls converter22, bidirectional chopper23, and inverter24by supplying PWM signals while monitoring, for example, three-phase AC voltages VU, VV, and VW from commercial AC power supply20, three-phase AC voltages VR, VS, and VT output to load26, DC voltages V1to V3, and the voltage between terminals of battery B11.

The operation of this uninterruptible power system will now be described. During a normal operation in which commercial AC power supply20supplies three-phase AC power normally, AC power from commercial AC power supply20is supplied to converter22via input filter21and is converted into DC power by converter22. The DC power generated in converter22is stored in battery B11via bidirectional chopper23and is also supplied to inverter24, and is then converted into three-phase AC power of a commercial frequency by inverter24. The three-phase AC power generated in inverter24is supplied to load26via output filter25, so that load26is operated.

At the occurrence of regenerated power in load26, the regenerated power is returned to commercial AC power supply20via output filter25, inverter24, buses L1to L3, converter22, and input filter21.

During a power failure in which a supply of AC power from commercial AC power supply20is stopped, the operation of converter22is stopped, and simultaneously, the DC power of battery B11is supplied to inverter24via bidirectional chopper23and is converted into three-phase AC power of a commercial frequency by inverter24. The three-phase AC power generated in inverter24is supplied to load26via output filter25, so that the operation of load26is continued.

Even when a power failure occurs, thus, the operation of load26is continued as long as battery B11stores DC power. When commercial AC power supply20restarts supplying AC power, the operation of converter22is restarted, and the DC power generated in converter22is supplied to battery B11via bidirectional chopper23and also to inverter24, returning to its original state. Embodiment 5 also achieves the same effects as those of Embodiments 1 to 4.

It should be construed that the embodiments disclosed herein are given by way of illustration in all respects, not by way of limitation. It is therefore intended that the scope of the present invention is defined by claims, not only by the embodiments described above, and encompasses all modifications and variations equivalent in meaning and scope to the claims.

REFERENCE SIGNS LIST