Thin film transistor substrate having metal oxide and method for manufacturing

A thin film transistor substrate and a method for manufacturing the same are disclosed. The thin film transistor substrate includes a gate electrode disposed on a substrate, a gate insulating film disposed on the gate electrode, an active layer disposed on the gate insulating film and including metal oxide, a source electrode contacted with one side of the active layer and a pixel electrode contacted with the other side of the active layer; and an etch stopper interposed between the source electrode and the pixel electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Korean Patent Application No. 10-2012-0074171 filed on Jul. 6, 2012. which is incorporated herein by reference for all purposes as if fully set forth herein.

BACKGROUND

This document relates to a thin film transistor substrate having metal oxide and a manufacturing method thereof which is capable of reducing power consumption by reducing a channel length and being applied to high-resolution models by reducing a size of an area of the thin film transistor.

2. Related Art

Recently, according to the development of multimedia, the importance of a flat panel display (FPD) is increased. Accordingly, several displays have been commercialized, such as a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), an organic field light emitting device and the like.

Of these, the liquid crystal display device has an excellent visibility, small average power consumption and small heat dissipation, compared to a cathode ray tube. In addition, the field light emitting device is in the spotlight as a next-generation display device, since a response rate is high to be less than 1 ms, power consumption is low, and a viewing angle is very large by self-lighting.

Methods of driving the display device include a passive matrix method, and an active matrix using a thin film transistor. The passive matrix method is a way in that the display device is driven by forming at right angles an anode and a cathode and selecting lines, whereas the active matrix method is a way in that thin film transistors are connected to each of pixel electrodes and the display device is driven according to a voltage retained by capacity of a capacitor that is connected to a gate electrode of a thin film transistor.

It is very important to have durability and electrical reliability that can maintain a long life, as well as basic characteristics, such as mobility, leakage current and the like, of the thin film transistor. Here, an active layer of the thin film transistor is mainly formed by amorphous silicon or polycrystalline silicon. If the amorphous silicon is used, a film formation process is simpler and a manufacturing cost is low, but there is a problem in that the electrical reliability may not be ensured. In addition, if the polycrystalline silicon is used, there are problems in that it is very difficult to large-area applications due to a high temperature in the process, and uniformity is not secured according to a crystallization method.

On the other hand, if the active layer is formed as the metal oxide, high mobility can be obtained although the active layer is formed at a low temperature, and the desired properties can be easily obtained due to large change in resistance, depending on the oxygen content. Accordingly, applications to the thin film transistor have attracted great interest recently. In particular, a metal oxide semiconductor may be, for example, zinc oxide (ZnO), indium zinc oxide (InZnO), zinc tin oxide (ZnSnO), indium gallium zinc oxide (InGaZnO4) or the like.

FIG. 1is a cross-sectional view illustrating a thin film transistor substrate including metal oxide in the prior art. Referring toFIG. 1, a gate electrode15and a gate insulating film20are disposed on a substrate10, and an active layer25consisting of metal oxide is disposed on the gate insulating film20. An etch stopper30to protect the active layer25is disposed on the active layer25, and a source electrode35aand a drain electrode35bare disposed to be contacted with the active layer25on the etch stopper30to form the thin film transistor. In addition, a passivation film40to protect the thin film transistor and a pixel electrode45contacted with the drain electrode35bare disposed.

The thin film transistor is formed with the etch stopper30to prevent direct damage for the active layer25in a manufacturing process of the source electrode35aand the drain electrode35b. In this case, there is a problem in that a channel length of the active layer25is very long due to the etch stopper30. Accordingly, the channel length of the active layer consisting of amorphous silicon in the prior art is longer at about 5 μm, whereas the channel length of the active layer consisting of metal oxide in the prior art is longer at about 10 μm. As a result, since power consumption of a display device is increased and an area of the thin film transistor is increased, there is a problem in that resolution is reduced.

SUMMARY

The present invention has been made in an effort to provide a method of manufacturing a thin film transistor substrate which is capable reducing power consumption by reducing a channel length and being applied to high resolution models by reducing a size of an area of a thin film transistor.

In one aspect, there is a thin film transistor substrate including a gate electrode disposed on a substrate, a gate insulating film disposed on the gate electrode, an active layer disposed on the gate insulating film and including metal oxide, a source electrode contacted with one side of the active layer substantially parallel to the substrate and a pixel electrode contacted with another side of the active layer substantially parallel to the substrate; and an etch stopper interposed between the source electrode and the pixel electrode.

In another aspect, there is a method of manufacturing a thin film transistor substrate including forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, forming an active layer including metal oxide on the gate insulating film, forming a source electrode contacted with one side of the active layer and a pixel electrode contacted with the other side of the active layer and forming an etch stopper between the source electrode and the pixel electrode.

In another aspect, there is a thin film transistor substrate including a gate electrode disposed on a substrate, a gate insulating film disposed on the gate electrode, an active layer disposed on the gate insulating film and including metal oxide, an etch stopper overlapping at least a portion of the active layer, a source electrode that at least partially overlaps the etch stopper and the active layer, and a pixel electrode at least partially overlapped by the active layer and the etch stopper.

In another aspect, there is a thin film transistor substrate including a gate electrode disposed on a substrate, a gate insulating film disposed on the gate electrode, an active layer disposed on the gate insulating film and including metal oxide, an etch stopper at least partially overlapping the active layer, a pixel electrode that at least partially overlaps the etch stopper and the active layer, and a source electrode at least partially overlapped by the active layer and the etch stopper.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. It will be paid attention that detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the invention.

FIG. 2is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, andFIG. 3is a cross-sectional view taken along a line I-I′ in the thin film transistor substrate ofFIG. 2. Hereinafter, as an example of the thin film transistor substrate, the thin film transistor substrate used in a liquid crystal display of a fringe field way will be described, and in particular, one sub-pixel will be shown and described as an example.

Referring toFIGS. 2 and 3, a thin film transistor substrate110according to the first exemplary embodiment of the present invention includes a gate line117and a data line155that are intersected across a gate insulating film120on the substrate110, and a thin film transistor (T) formed for each of intersecting portions. In addition, a pixel area is defined by the intersecting structure of the gate line117and the data line155. The pixel area includes a pixel electrode125and a common electrode170, which are formed across a passivation film160and an etch stopper140to form a fringe field. The pixel electrode125has a roughly rectangular shape corresponding (for example, the shape of a plate) to the pixel area, and the common electrode170is formed in a shape having a plurality of parallel bands.

The common electrode170is connected to a common line177aligned with the gate line117. The common electrode170is supplied with a reference voltage (or common voltage) for LED driving through the common line177.

The thin film transistor (T) allows pixel signals of the data line155to be charged and maintained to the pixel electrode125in response to gate signals of the gate line117. To this purpose, the thin film transistor (T) includes a gate electrode115branched from the gate line117, a source electrode150branched from the data line155, the pixel electrode125opposed to the source electrode150, and an active layer130overlapped with the gate electrode115on a gate insulating film120and forming a channel between the source electrode150and the pixel electrode125. In addition, thin film transistor (T) may further include an ohmic contact layer for ohmic contact between the active layer130and the source electrode150, and between the active layer130and the pixel electrode125.

In particular, if the active layer130is formed as metal oxide, the thin film transistor substrate for large area in charging capacity is advantageous due to high charge mobility characteristics. However, metal oxide semiconductor materials further includes an etch stopper140on an upper surface for protection from etchant in order to ensure stability of elements. Specifically, the etch stopper140is formed to prevent the active layer130from being etched by the etchant introduced in forming the source electrode150by an etching process. In this embodiment of the present invention, the etch stopper140is formed on a front surface of the substrate110, and a contact hole145is formed to expose only a portion of an area of the active layer130.

One end of the gate line117is provided with a gate pad (GP) to receive a gate signal from the outside. The gate pad (GP) is in contacted with a gate pad terminal (GPT) through a gate pad contact hole (GPH) which is passed through the gate insulating film120, the etch stopper140and the passivation film160. On the other hand, one end of the data line155is provided with a data pad (DP) for receiving pixel signals from the outside. The data pad (DP) is in contacted with a data pad terminal (DPT) through a data pad contact hole (DPH), which is passed through the passivation film160.

In this embodiment of the present invention, the pixel electrode125is in contacted with the active layer130over the gate insulating film120, such that it functions as a pixel electrode and a drain electrode at the same time. On the other hand, the common electrode170is formed to be overlapped with the pixel electrode125across the etch stopper140covering the pixel electrode125and the passivation film160. Thus, an electric field is formed between the pixel electrode125and the common electrode, such that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and a color filter substrate are rotated by dielectric anisotropy. In addition, light transmissivity is changed depending on degrees of rotation of the liquid crystal molecules to implement gradation.

Hereinafter, the method of manufacturing the thin film transistor substrate ofFIGS. 2 and 3as described above will be described in detail. Herein, the same reference numerals denote the same elements as in the descriptions for the method of manufacturing the thin film transistor substrate inFIGS. 2 and 3described above, and thus the detailed descriptions of the same elements will be omitted.FIGS. 4ato4dare cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to an exemplary embodiment of the present invention, andFIG. 5is a plan view illustrating the thin film transistor substrate ofFIG. 3.

Referring toFIG. 4a, a gate metal is deposited on a transparent substrate110. The gate metal includes one selected from a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu), or low-resistance metallic materials such as alloys thereof The gate electrode115is formed by patterning the gate metal using a first mask. Although not shown in the drawings, the gate electrode115is formed while forming the gate line.

Subsequently, the gate insulating film120is formed on the substrate110including the gate electrode115. The gate insulating film120may use silicon oxide (SiOx) or silicon nitride (SiNx) and may be formed as multi-layers thereof Since then, materials of the pixel electrode are deposited on the gate insulating film120. The pixel electrode material may include indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode125is formed by patterning the pixel electrode material using a second mask. The pixel electrode125is formed in a shape of plate on the pixel region, and also formed on a portion region corresponding to the gate electrode115.

Next, referring toFIG. 4b, metal oxide is deposited on the substrate110formed with the pixel electrode125and patterned by using a third mask to form the active layer130overlapped with the gate electrode115. Here, the active layer130may be formed by the metal oxide, and the metal oxide may be, for example, zinc oxide (ZnO), indium zinc oxide (InZnO), zinc tin oxide (ZnSnO), indium gallium zinc oxide (InGaZnO4) or the like. In this case, the active layer130is overlapped with the gate electrode115and formed on the pixel electrode125to be in contacted with a portion of the pixel electrode125.

Subsequently, the etch stopper140is formed on top of the active layer130. The etch stopper140may be formed by silicon oxide (SiOx) or silicon nitride (SiNx). In addition, a contact hole145is formed to expose an upper portion of one side of the active layer130by etching a portion of the etch stopper140using a fourth mask.

Next, referring toFIG. 4c, a source metal is deposited on the substrate110formed with the etch stopper140, and the substrate110is patterned using a fifth mask, such that the source electrode150and the data pad terminal (DPT) are formed. The source metal includes one selected from a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu), or low-resistance metallic materials such as alloys thereof. The source electrode150is in contacted with an upper of one side of the active layer130through the contact hole145of the etch stopper140. Although not shown in the drawings, the source electrode150and the data line are formed at the same time.

Accordingly, the thin film transistor (T) is formed to include the gate electrode115, the active layer130, the pixel electrode125and the source electrode150. The pixel electrode125functions as the drain electrode and the pixel electrode at the same time.

Next, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on substrate110formed with the source electrode150and the data pad terminal (DPT) to form the passivation film160. In addition, a data pad contact hole (GPH) is formed to expose the data pad terminal (DPT) by etching a portion of the passivation film160using a sixth mask.

Subsequently, referring toFIG. 4d, indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited in a front of the substrate110and the substrate110is patterned using a seventh 7masks, such that a common electrode170, a common line177and a data pad (DP) are formed. The common electrode170is formed to be corresponded to the pixel electrode125in the pixel region, and the electrodes with several bar shapes parallel to each other have a shape arranged at regular intervals.

Referring toFIG. 5, in the thin film transistor as manufactured above according to the embodiment of the present invention, the source electrode and the pixel electrode contacted with the active layer are formed on different layers, such that the channel length of the active layer can be reduced. In addition, a channel (CH) of the active layer130is formed between the pixel electrode125directly contacted with a lower portion of one side of the active layer130and the source electrode150contacted with an upper portion of the other side of the active layer130through the contact hole145. In this case, since the length (L) of the channel (CH) is corresponded to a distance from a contact part of the source electrode150to a contact part of the pixel electrode125, the length (L) of the channel (CH) can be reduced greatly.

In one embodiment, the extent to which the source and pixel electrodes overlap the active layer130is large enough such that a length (L) of the channel (CH) is less than a majority of the length of the active layer in total. For example, the length (L) of the channel (CH) can be less than the extent (distance) of the overlap of the source electrode over (or under) the active layer130. Similarly, the length (L) of the channel (CH) can be less than the extent (distance) of the overlap of the pixel electrode over (or under) the active layer130.

In addition, since the source electrode150and the pixel electrode125can be formed on the different layers across active layer130, the active layer130can be reduced in overall size. Therefore, it has an advantage in that sizes of sub-pixels are reduced depending on reduction of the areas of the thin film transistor, thereby being applied to high-resolution models.

In addition, the source electrode150and the pixel electrode125can be formed on different layers across active layer130, and the thin film transistor can be manufactured using the same 7 sheets of masks as the conventional thin film transistor that is formed on the same layers with the source/drain electrodes. Accordingly, there is an advantage in that the length of the channel of the active layer can be reduced, without increasing the manufacturing cost and processing time.

In addition, according to the embodiment of the present invention, the pixel electrode125is formed which consists of transparent conductive materials, for example, metal oxide series such as ITO and functions of the pixel electrode125and the drain electrode are performed simultaneously. In particular, if the pixel electrode125is in directly contacted with the active layer130, metal oxides of the active layer130and the pixel electrode125are consisted of oxide-like series. Accordingly, there is an advantage in that electrical characteristics can be excellent since an ingress barrier of interface is lower, without having ohmic layers

On the other hand, the thin film transistor substrate can be formed to have different structures from these ofFIGS. 2 to 5as described above. Hereinafter, the same reference numerals denote the same elements as the structure shown inFIG. 3, and thus the detailed descriptions of the same elements will be omitted.FIG. 6is a cross-sectional view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring toFIG. 6, the gate electrode115is disposed on the substrate110, and the gate insulating film120is disposed on the gate electrode115. The source electrode150and the data pad terminal (DPT) are disposed on the gate insulating film120and contacted with one side of the source electrode150. In addition, the active layer130is formed which includes metal oxide over the gate insulating film120. The etch stopper140is disposed on the active layer130and on the data pad terminal (DPT), and the pixel electrode125is disposed on the etch stopper140. The pixel electrode125is in contacted with an other side of the active layer130through a via hole145formed on the etch stopper140.

In addition, the passivation film160is formed on the substrate110formed with the pixel electrode125, and the common electrode170, the common line177and the data pad (DP) are disposed on the passivation film170. The common electrode170is formed to be opposed to the above-mentioned pixel electrode125, and the data pad (DP) is connected to the data pad terminal (DPT) through the data pad contact hole (DPH) to expose the data pad terminal (DPT) by passing through the passivation film160and the etch stopper140

In the thin film transistor substrate100ofFIG. 6, the source electrode150and the pixel electrode125are disposed differently, unlike the above-mentioned structure ofFIG. 3. In other words, the source electrode150and the pixel electrode125are disposed on an upper portion and on a lower portion across the active layer130, respectively, in the structure ofFIG. 3. In contrast, the source electrode150and the pixel electrode125may be disposed on a lower portion and on the upper portion across the active layer130, respectively, in the structure ofFIG. 6.

FIG. 7is a plan view illustrating a thin film transistor substrate according to another exemplary embodiment of the present invention, andFIG. 8is a cross-sectional view taken along a line II-II′ in the thin film transistor substrate ofFIG. 6.

Hereinafter, the same reference numerals denote the elements that act the same as the foregoing embodiments, and thus it will be easy to understand the present invention.

Referring toFIGS. 7 and 8, according to another embodiment of the present invention, a thin film transistor substrate200includes a gate line117and a data line155intersected across the gate insulating film120on the substrate110, and a thin film transistor (T) formed on each of intersected portions. The pixel region is provided with the pixel electrode125and the common electrode170, which are formed across the passivation film160and the etch stopper140. The common electrode170is connected to a common line177aligned with the gate line117.

The thin film transistor (T) includes a gate electrode115branched from the gate line117, a source electrode150connected to the data line155, a pixel electrode125opposed to the source electrode150, and an active layer130overlapped with the gate electrode115on a gate insulating film120and forming a channel between the source electrode150and the pixel electrode125. The etch stopper140is formed on the active layer130, and the etch stopper140includes a first via hole165and a second via hole167to expose only a portion of region of the active layer130.

One end of the gate line117is provided with a gate pad (GP) to receive a gate signal from the outside. The gate pad (GP) is in contacted with a gate pad terminal (GPT) through a gate pad contact hole (GPH) which is passed through the gate insulating film120, the etch stopper140and the passivation film160. Meanwhile, one end of the data line155is provided with a data pad (DP) for receiving pixel signals from the outside. The data pad (DP) is in contacted with a data pad terminal (DPT) through a data pad contact hole (DPH) which is passed through the passivation film160.

The pixel electrode125according to the embodiment of the present invention is in contacted with the active layer130over the gate insulating film120, such that it functions as a pixel electrode and a drain electrode at the same time pixel electrode. On the other hand, the common electrode170is formed to be overlapped with the pixel electrode125across the etch stopper140covering the pixel electrode125and the passivation film160.

Hereinafter, the method of manufacturing the thin film transistor substrate ofFIGS. 7 and 8as described above will be described in detail.FIGS. 9ato9dare cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring toFIG. 9a, a gate metal is deposited on a transparent substrate110. The gate metal includes one selected from a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu), or low-resistance metallic materials such as alloys thereof The gate electrode115is formed by patterning the gate metal using a first mask. Although not shown in the drawings, the gate electrode115is formed while the gate line is formed.

Subsequently, the gate insulating film120is formed on the substrate110including the gate electrode115. The gate insulating film120may use silicon oxide (SiOx) or silicon nitride (SiNx) and may be formed as multi-layers thereof Since then, a pixel electrode material is deposited on the gate insulating film120. The pixel electrode material may include indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode125is formed by patterning the pixel electrode material using a second mask. The pixel electrode125is formed in a shape of plate in the pixel region, and also formed in a portion region corresponding to the gate electrode115.

Next, referring toFIG. 9b, metal oxide is deposited on the substrate110formed with the pixel electrode125and patterned by using a third mask to form the active layer130overlapped with the gate electrode115. Here, the active layer130may be formed by the metal oxide, and the metal oxide may be, for example, zinc oxide (ZnO), indium zinc oxide (InZnO), zinc tin oxide (ZnSnO), indium gallium zinc oxide (InGaZnO4) or the like. In this case, the active layer130is overlapped with the gate electrode115and formed on the pixel electrode125to be in contacted with a portion of the pixel electrode125.

Subsequently, an etch stopper140is formed in a front of the substrate110formed with the active layer130. The etch stopper140may be formed by silicon oxide (SiOx) or silicon nitride (SiNx). Next, metal oxide is deposited on the substrate110formed with the etch stopper140, and the substrate110is patterned using a fourth mask to form the data line155and the data pad terminal (DPT). The data metal includes one selected from a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu), or low-resistance metallic materials such as alloys thereof.

Next, referring toFIG. 9c, silicon oxide (SiOx) or silicon nitride (SiNx) are deposited on the substrate110formed with the data line155and the data pad terminal (DPT) to form the passivation film160. In addition, a portion of the etch stopper140and the passivation film160is etched using a fifth mask, such that a first via hole165to expose an upper of an other side of the active layer130is formed. At the same time, the passivation film160is etched, such that a second via hole167to expose the data line155is formed and data pad contact hole (DPH) to expose the data pad terminal (DPT) is formed.

Subsequently, referring toFIG. 9d, indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited in a front of the substrate110and the substrate110is patterned using a sixth mask, such that a common electrode170, a common line177, a data pad (DP) and source electrode150are formed. The common electrode170is formed to be corresponded to the pixel electrode125in the pixel region, and it has a shape arranged at regular intervals with electrodes with several bars parallel to each other. The source electrode150is in contacted with the active layer130and the data line155, respectively, through a first hole165to expose an other side of the active layer130and a second hole167to expose the data line155. Accordingly, the source electrode150is connected to the active layer130and the data line155to transmit data signals to the active layer130.

According to another embodiment of the present invention, of course, the thin film transistor substrate ofFIGS. 8 and 9manufactured as described above has the same effect as the above-mentioned embodiment ofFIGS. 3 and 4, however the thin film transistor substrate ofFIGS. 8 and 9can be manufactured using a total of 6 sheets reduced by one sheet as compared to the embodiments ofFIGS. 3 and 4. Specifically, only contact hole mask is used for the embodiments ofFIGS. 8 and 9, whereas two contact hole masks were used in the embodiments ofFIGS. 3 and 4. Accordingly, there is an advantage in that the manufacturing cost and processing time of the thin film transistor substrate can be reduced.