Electrostatic discharge protection devices

An electrostatic discharge protection device includes a first well region, a second well region, a first doped region, and a first heavily doped region. The first well region and the second well region are disposed in a semiconductor substrate. The first doped region is disposed in the first well region and the second well region. The first heavily doped region is disposed in the first doped region in the first well region. The first well region and the first doped region have a first conductivity type, and the second well region and the first heavily doped region have a second conductivity type that is the opposite of the first conductivity type.

BACKGROUND

Technical Field

The disclosure relates to electrostatic discharge protection devices, and more particularly, to the electrostatic discharge protection devices with low on-state resistance.

Description of the Related Art

As semiconductor manufacturing processes have developed, electrostatic discharge (ESD) protection has become one of the most critical reliability issues for integrated circuits (IC). Electrostatic discharge protection circuits generally protect integrated circuits (IC) from machine model (MM) or human body model (HBM) electrostatic discharge events. Commercial integrated circuits require high tolerance to accidental ESD and the dangers this can cause. Otherwise, the IC can easily become damaged by an accidental ESD event. Therefore, designers always research how to design ESD protection elements to effectively protect ICs.

SUMMARY

Some embodiments of the present disclosure provide an electrostatic discharge protection device. The electrostatic discharge protection device includes a first well region and a second well region disposed in a semiconductor substrate. The first well region has a first conductivity type, and the second well region has a second conductivity type that is the opposite of the first conductivity type. The electrostatic discharge protection device also includes a first doped region disposed in the first well region and the second well region. The first doped region has the first conductivity type. The electrostatic discharge protection device also includes a first heavily doped region disposed in the first doped region in the first well region. The first heavily doped region has the second conductivity type.

Some embodiments of the present disclosure provide an electrostatic discharge protection device. The electrostatic discharge protection device includes a first well region disposed in a semiconductor substrate. The electrostatic discharge protection device also includes a first doped region including a first portion in the first well region and a second portion outside the first well region. The electrostatic discharge protection device also includes a first heavily doped region disposed in the second portion of the first doped region. The electrostatic discharge protection device also includes a second heavily doped region disposed in the second well region. The first doped region has a first conductivity type, and the first well region, the first heavily doped region, and the second heavily doped region have a second conductivity type that is the opposite of the first conductivity type.

In order to make features and advantages of the present disclosure easy to understand, a detailed description is given in the following embodiments with reference to the accompanying drawings.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first component over or on a second component in the description that follows may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, such that the first and second components may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of some embodiments are discussed below. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

The embodiments of the present disclosure are related to an electrostatic discharge protection device. The electrostatic discharge protection device includes a parasitic bipolar junction transistor (BJT) which is formed from a heavily doped region, a moderately doped region, and a lightly doped well region. When an electrostatic discharge event occurs, the PN junction between the well region and the moderately doped region is broken down at a low voltage to generate a reverse current so that the electrostatic current is discharged through the BJT of the electrostatic discharge protection device without through semiconductor devices protected by the electrostatic discharge protection device. Therefore, the electrostatic discharge protection device protects the semiconductor devices from damage in the event of an electrostatic discharge.

FIG.1Aillustrates a cross-sectional view of an electrostatic discharge protection device100in accordance with some embodiments of the present disclosure, andFIG.1Billustrates an equivalent circuit diagram of the electrostatic discharge protection device100device ofFIG.1A.

The electrostatic discharge protection device100includes a semiconductor substrate102, as shown inFIG.1A, in accordance with some embodiments. The semiconductor substrate102includes an elementary semiconductor such as silicon (Si) substrate, in accordance with some embodiments. In some embodiments, the semiconductor substrate102includes an elementary semiconductor such as germanium (Ge); a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or a combination thereof.

The semiconductor substrate102is doped to have a first conductivity type or a second conductivity type that is the opposite of the first conductivity type, in accordance with some embodiments. The first conductivity type is N-type and the second conductivity type is P-type, in accordance with some embodiments. In some embodiments, the semiconductor substrate102has the first conductivity type (such as N-type), for example, the semiconductor substrate102may be doped with phosphorous (P) or arsenic (As). In some embodiment, the semiconductor substrate102has the second conductivity type (such as P-type), for example, the semiconductor substrate102may be doped with boron (B).

In addition to the electrostatic discharge protection device100, other semiconductor devices (not shown), such as active elements, passive elements (such as resistor or capacitor), or a combination thereof, are formed on the semiconductor substrate102, in accordance with some embodiments. In some embodiments, the active elements include transistors, metal oxide semiconductor field effect transistors (MOSFETs), metal insulator semiconductor FET (MISFETs), junction field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), or combinations thereof. The electrostatic discharge protection device100protects the semiconductor devices from damage in electrostatic discharge events.

The electrostatic discharge protection device100includes a first well region104and a second well region106, as shown inFIG.1A, in accordance with some embodiments. The first well region104and the second well region106are disposed in the semiconductor substrate102, in accordance with some embodiments. The first well region104and the second well region106extend downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments. The first well region104is in contact with the second well region106, in accordance with some embodiments.

The first well region104has a different conductivity type than the second well region106, in accordance with some embodiments. The first well region104has the first conductivity type (such as N-type), and the second well region106has the second conductivity type (such as P-type), in accordance with some embodiments. In some embodiments, the first conductivity type is N-type dopant such as phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb), or a combination thereof. In some embodiments, the second conductivity type is P-type dopant such as boron (B), gallium (Ga), aluminum (Al), indium (In), or a combination thereof. In some embodiments, the first well region104and the second well region106are formed by respective ion implantation processes.

The electrostatic discharge protection device100includes a first doped region108, as shown inFIG.1A, in accordance with some embodiments. The first doped region108has a first portion108A disposed in the first well region104and a second portion108B disposed in the second well region106, in accordance with some embodiments. The boundary between the first well region104and the second well region106passes through the first doped region108, in accordance with some embodiments. The first doped region108extends downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments.

The first doped region108has the first conductivity type (such as N-type), in accordance with some embodiments. The first doped region108has a doping concentration that is greater than the dopant concentration of the first well region104, in accordance with some embodiments. The first doped region108has a doping concentration that is greater than the dopant concentration of the second well region106, in accordance with some embodiments. In some embodiments, the first doped region108is formed by an ion implantation process.

The electrostatic discharge protection device100includes a second doped region110, as shown inFIG.1A, in accordance with some embodiments. The second doped region110is disposed in the second well region106, in accordance with some embodiments. The second doped region110extends downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments.

The second doped region110has the second conductivity type (such as P-type), in accordance with some embodiments. The second doped region110has a doping concentration that is greater than the doping concentration of the second well region106, in accordance with some embodiments. In some embodiments, the second doped region110is formed by an ion implantation process.

The electrostatic discharge protection device100includes a first heavily doped region132, as shown inFIG.1A, in accordance with some embodiments. The first heavily doped region132provides an ohmic contact for an interconnect structure (not shown, such as contact plugs) formed thereon, in accordance with some embodiments. The first heavily doped region132is disposed in the first well region104, in accordance with some embodiments. A portion of the first heavily doped region132is disposed in the first doped region108, in accordance with some embodiments. The first heavily doped region132extends downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments.

The first heavily doped region132has the first conductivity type (such as N-type), in accordance with some embodiments. The doping concentration of the first heavily doped region132is greater than the doping concentration of the first well region104and doping concentration of the first doped region108, in accordance with some embodiments. In some embodiments, the first heavily doped region132is formed by an ion implantation process.

The electrostatic discharge protection device100includes a second heavily doped region134, as shown inFIG.1A, in accordance with some embodiments. The second heavily doped region134provides an ohmic contact for the interconnect structure (not shown, such as contact plugs) formed thereon, in accordance with some embodiments. The second heavily doped region134is disposed in the first portion108A of the first doped region108, in accordance with some embodiments. The second heavily doped region134is entirely disposed in the first portion108A of the first doped region108, in accordance with some embodiments. The first heavily doped region132is in contact with the second heavily doped region134, in accordance with some embodiments. The second heavily doped region134extends downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments.

The second heavily doped region134has the second conductivity type (such as P-type), in accordance with some embodiments. The doping concentration of the second heavily doped region134is greater than the doping concentration of the first doped region108, in accordance with some embodiments. In some embodiments, the second heavily doped region134is formed by an ion implantation process.

The electrostatic discharge protection device100includes a third heavily doped region136, as shown inFIG.1A, in accordance with some embodiments. The third heavily doped region136provides an ohmic contact for the interconnect structure (not shown, such as contact plugs) formed thereon, in accordance with some embodiments. The third heavily doped region136is disposed in the second well region106outside the first doped region108, in accordance with some embodiments. The third heavily doped region136is entirely disposed in the second doped region110in the second well region106, in accordance with some embodiments. The third heavily doped region136extends downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments.

The third heavily doped region136has the second conductivity type (such as P-type), in accordance with some embodiments. The doping concentration of the third heavily doped region136is greater than the doping concentration of the second doped region110. In some embodiments, the third heavily doped region136is formed by an ion implantation process.

The electrostatic discharge protection device100includes isolation features121and123, as shown inFIG.1A, in accordance with some embodiments. The isolation features121and123extend downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments.

The isolation features121and123are used to define the area in the semiconductor substrate102where the electrostatic discharge protection device100is formed, in accordance with some embodiments. The isolation feature121is disposed at a side of the first well region104away from the second well region106, in accordance with some embodiments. The isolation feature123is disposed at a side of the second well region106away from the first well region104, in accordance with some embodiments.

In some embodiments, the isolation features121and123include field oxide (FOX), local oxide of silicon (LOCOS), or shallow trench isolation (STI) structure. In some embodiments, the isolation features121and123are made of silicon oxide, silicon nitride, silicon oxynitride, another suitable dielectric material, or a combination thereof. In some embodiments, the isolation features121and123are formed by a thermal oxidation process. In some embodiments, the isolation features121and123are formed by an etching process and a deposition process.

The first heavily doped region132and the second heavily doped region134are together electrically connected to a power line VDD, as shown inFIG.1A, in accordance with some embodiments. The third heavily doped region136is electrically connected to a ground line VSS, in accordance with some embodiments. The power line VDD and the ground line VSS respectively provide a high voltage and a low voltage to semiconductor devices that are protected by the electrostatic discharge protection device100, in accordance with some embodiments.

In some embodiments, the interconnect structure is formed over the semiconductor substrate102so that the first heavily doped region132and the second heavily doped region134are electrically connected to the power line VDD and the third heavily doped region136is electrically connected to the ground line VSS. In some embodiments, the interconnect structure includes contact plugs which land on the first heavily doped region132, the second heavily doped region134, and the third heavily doped region136. In some embodiments, the interconnect structure also includes conductive lines and vias formed over contact plugs.

A PN junction exists between the second heavily doped region134and the first doped region108, and a PN junction exists between the second well region106and the first doped region108, as shown inFIGS.1A and1B, in accordance with some embodiments. As a result, the second heavily doped region134, the first doped region108, and the second well region106form a parasitic bipolar junction transistor (BJT). The BJT is a PNP-type BJT, in accordance with some embodiments. The third heavily doped region136is a collector C of the BJT, the first doped region108is a base B of the BJT, the second heavily doped region134is an emitter E of the BJT, in accordance with some embodiments.

The PN junction between the second well region106and the first doped region108has a breakdown voltage that is lower than the operation voltage of the semiconductor devices protected by the electrostatic discharge protection device100, in accordance with some embodiments. When an electrostatic discharge event occurs from the power line VDD, because the PN junction between the second well region106and the first doped region108is broken down at a low voltage, the electrostatic current is discharged through the BJT of the electrostatic discharge protection device100rather than through the semiconductor devices protected by the electrostatic discharge protection device100. As a result, the electrostatic discharge protection device100protects the semiconductor devices from damage in the event of an electrostatic discharge.

Furthermore, once the PN junction between the second well region106and the first doped region108is broken down at a low voltage to generate a reverse current, the potential difference (VEB) between the emitter E (the second heavily doped region134) and the base B (the first doped region108) generates a large amount of emitter current (IE) that flows to the collector C (the third heavily doped region136), thereby reducing the on-resistance (RON) of the electrostatic discharge protection device100. As a result, the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device100.

Furthermore, the first doped region108is spaced apart from the third heavily doped region136by a distance D1, in accordance with some embodiments. If the distance D1is too small, the breakdown voltage of the PN junction between the second well region106and the first doped region108may be low. If the distance D1is too high, the on-resistance of the electrostatic discharge protection device100may increase. The second heavily doped region134in the first well region104is spaced apart from an edge of the first well region104by a distance D2, in accordance with some embodiments.

Furthermore, the on-resistance of the electrostatic discharge protection device100can be reduced further by forming the second doped region110in the second well region106so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device100.

FIG.2Aillustrates a cross-sectional view of an electrostatic discharge protection device200in accordance with some embodiments of the present disclosure, andFIG.2Billustrates an equivalent circuit diagram of the electrostatic discharge protection device200ofFIG.2A. Elements or layers inFIGS.2A and2Bthat are the same or similar to those inFIGS.1A and1Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.2A-BandFIGS.1A-Bis that the electrostatic discharge protection device200includes an isolation feature122.

The isolation feature122is disposed in the first well region104, in accordance with some embodiments. The isolation feature122is disposed between the first heavily doped region132and the second heavily doped region134, in accordance with some embodiments. The isolation feature122extends downwardly from the upper surface of the semiconductor substrate102, in accordance with some embodiments. The isolation feature122is disposed in the first well region104outside the first doped region108, in accordance with some embodiments. In some embodiments, the material and the formation method of the isolation feature122is the same as or similar to the isolation features121and123described above.

The first well region104provides a resistance R1between the first heavily doped region132and the first doped region108(the base B) by forming the isolation feature122, as shown inFIGS.2A and2B, in accordance with some embodiments. The resistance R1can be adjusted by changing the dimension D3of the isolation feature122. For example, the larger dimension D3results in the larger resistance R1and vice versa. If the dimension D3is too small, the resistance R1does not increase significantly. If the dimension D3is too large, the layout density of the semiconductor devices formed on the semiconductor substrate102is reduced.

Once the PN junction between the second well region106and the first doped region108is broken down at a low voltage to generate a reverse current, a potential difference (VEB) exists between the emitter E (the second heavily doped region134) and the base B (the first doped region108). The larger resistance R1results in the larger potential difference (VEB) between the emitter E and the base B, which further increases the emitter current (IE). As a result, the on-resistance of the electrostatic discharge protection device200can be reduced further by forming the isolation feature122so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device200.

FIG.3Aillustrates a cross-sectional view of an electrostatic discharge protection device300in accordance with some embodiments of the present disclosure, andFIG.3Billustrates an equivalent circuit diagram of the electrostatic discharge protection device300ofFIG.3A. Elements or layers inFIGS.3A and3Bthat are the same or similar to those inFIGS.1A and1Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.3A-BandFIGS.1A-Bis that the electrostatic discharge protection device300includes a gate structure138.

The gate structure138is disposed over the upper surface of the semiconductor substrate102, in accordance with some embodiments. The gate structure138partially covers the first well region104, the first doped region108, the second well region106, and the second doped region110, in accordance with some embodiments. The gate structure138is disposed between the second heavily doped region134and the third heavily doped region136, in accordance with some embodiments. The gate structure138does not cover the second heavily doped region134and the third heavily doped region136, in accordance with some embodiments.

The first heavily doped region132, the second heavily doped region134, and the gate structure138are together electrically connected to the power line VDD, and the third heavily doped region136is electrically connected to a ground line VSS, in accordance with some embodiments.

The gate structure138includes a gate dielectric layer140and a gate electrode142formed over the gate dielectric layer140, in accordance with some embodiments. In some embodiments, the gate dielectric layer140includes silicon oxide, silicon nitride, silicon oxynitride, or high-k (k value is greater than 3.9) dielectric material. In some embodiments, the high-k dielectric material includes LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, BaTiO3, SrTiO3, Al2O3, another applicable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer142is formed by an oxidation process (such as dry oxidation or wet oxidation), a deposition process (e.g., chemical vapor deposition (CVD) process, another applicable process, or a combination thereof.

In some embodiments, the gate electrode142includes a conductive material such as polysilicon or metal. In some embodiments, the polysilicon is doped. In some embodiments, the metal for gate electrode142includes tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), platinum (Pt), the like, or a combination thereof. In some embodiments, the gate electrode142is formed by forming a conductive material by CVD process, a physical vapor deposition process (PVD), an electroplating process, an atomic layer deposition process (ALD), another applicable process, or a combination thereof. The electrode material is then patterned by a photolithography process and an etching process to form the gate electrode142.

When an electrostatic discharge event occurs from the power line VDD, the gate structure138electrically connected to the power line VDD opens the channel region below the gate structure138, which further increases the collector current (IC). As a result, the on-resistance of the electrostatic discharge protection device300can be reduced further by forming the gate structure138so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device300.

FIG.4Aillustrates a cross-sectional view of an electrostatic discharge protection device400in accordance with some embodiments of the present disclosure, andFIG.4Billustrates an equivalent circuit diagram of the electrostatic discharge protection device400ofFIG.4A. Elements or layers inFIGS.4A and4Bthat are the same or similar to those inFIGS.3A and3Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.4A-BandFIGS.3A-Bis that the electrostatic discharge protection device400includes an isolation feature122as shown inFIG.2A.

Once the PN junction between the second well region106and the first doped region108is broken down at a low voltage to generate a reverse current, a potential difference (VEB) exists between the emitter E (the second heavily doped region134) and the base B (the first doped region108). The larger resistance R1results in the larger potential difference (VEB) between the emitter E and the base B, which further increases the emitter current (IE). As a result, the on-resistance of the electrostatic discharge protection device400can be reduced further by forming the isolation feature122so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device400.

FIG.5Aillustrates a cross-sectional view of an electrostatic discharge protection device500in accordance with some embodiments of the present disclosure, andFIG.5Billustrates an equivalent circuit diagram of the electrostatic discharge protection device400ofFIG.5A. Elements or layers inFIGS.5A and5Bthat are the same or similar to those inFIGS.1A and1Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.5A-BandFIGS.1A-Bis that the first conductivity type is P-type and the second conductivity type is N-type.

The first heavily doped region132and the second heavily doped region134are together electrically connected to a ground line VSS, as shown inFIG.5A, in accordance with some embodiments. The third heavily doped region136is electrically connected to a power line VDD, in accordance with some embodiments. The power line VDD and the ground line VSS respectively provide a high voltage and a low voltage to semiconductor devices that are protected by the electrostatic discharge protection device500.

A PN junction exists between the second heavily doped region134and the first doped region108, and a PN junction exists between the second well region106and the first doped region108, as shown inFIGS.5A and5B, in accordance with some embodiments. As a result, the second heavily doped region134, the first doped region108, and the second well region106form a BJT. The BJT is an NPN-type BJT, in accordance with some embodiments. The third heavily doped region136is a collector C of the BJT, the first doped region108is a base B of the BJT, the second heavily doped region134is an emitter E of the BJT, in accordance with some embodiments.

The PN junction between the second well region106and the first doped region108has a breakdown voltage that is lower than an operation voltage of semiconductor devices protected by the electrostatic discharge protection device500, in accordance with some embodiments. When an electrostatic discharge event occurs from the power line VDD, because the PN junction between the second well region106and the first doped region108is broken down at a low voltage, the electrostatic current is discharged through the BJT of the electrostatic discharge protection device500rather than through the semiconductor devices protected by the electrostatic discharge protection device500. As a result, the electrostatic discharge protection device500protects the semiconductor devices from damage in the event of an electrostatic discharge.

Furthermore, once the PN junction between the second well region106and the first doped region108is broken down at a low voltage to generate a reverse current, a potential difference (VEB) between the emitter E (the second heavily doped region134) and the base B (the first doped region108) generates a large amount of emitter current (IE) that flows to collector C (the third heavily doped region136), thereby reducing the on-resistance (RON) of the electrostatic discharge protection device500. As a result, the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device500.

FIG.6Aillustrates a cross-sectional view of an electrostatic discharge protection device600in accordance with some embodiments of the present disclosure, andFIG.6Billustrates an equivalent circuit diagram of the electrostatic discharge protection device600ofFIG.6A. Elements or layers inFIGS.6A and6Bthat are the same or similar to those inFIGS.5A and5Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.6A-BandFIGS.5A-Bis that the electrostatic discharge protection device600includes an isolation feature122as shown inFIG.2A.

The first well region104provides a resistance R2between the first heavily doped region132and the first doped region108(the base B) by forming the isolation feature122, as shown inFIGS.6A and6B, in accordance with some embodiments. The resistance R2can be adjusted by changing the dimension D3of the isolation feature122. For example, the larger dimension D3results in the larger resistance R2and vice versa.

Once the PN junction between the second well region106and the first doped region108is broken down at a low voltage to generate a reverse current, a potential difference (VEB) exists between the emitter E (the second heavily doped region134) and the base B (the first doped region108). The larger resistance R2results in the larger potential difference (VEB) between the emitter E and the base B, which further increases the emitter current (IE). As a result, the on-resistance of the electrostatic discharge protection device600can be reduced further by forming the isolation feature122so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device600.

FIG.7Aillustrates a cross-sectional view of an electrostatic discharge protection device700in accordance with some embodiments of the present disclosure, andFIG.7Billustrates an equivalent circuit diagram of the electrostatic discharge protection device700ofFIG.7A. Elements or layers inFIGS.7A and7Bthat are the same or similar to those inFIGS.5A and5Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.7A-BandFIGS.5A-Bis that the electrostatic discharge protection device700includes a gate structure138as shown inFIG.3A.

The first heavily doped region132, the second heavily doped region134and the gate structure138are together electrically connected to the ground line VSS, and the third heavily doped region136is electrically connected to a power line VDD, in accordance with some embodiments.

When an electrostatic discharge event occurs from the power line VDD, the gate structure138electrically connected to the ground line VSS opens a channel region below the gate structure138. As a result, the on-resistance of the electrostatic discharge protection device700can be reduced further by forming the gate structure138so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device700.

FIG.8Aillustrates a cross-sectional view of an electrostatic discharge protection device800in accordance with some embodiments of the present disclosure, andFIG.8Billustrates an equivalent circuit diagram of the electrostatic discharge protection device800ofFIG.8A. Elements or layers inFIGS.8A and8Bthat are the same or similar to those inFIGS.7A and7Bare denoted by like reference numerals that have the same meaning, and the description thereof will not be repeated for the sake of brevity. The difference between the embodiments shown inFIGS.8A-BandFIGS.7A-Bis that the electrostatic discharge protection device800includes an isolation feature122as shown inFIG.6A.

Once the PN junction between the second well region106and the first doped region108is broken down at a low voltage to generate a reverse current, a potential difference (VEB) exists between the emitter E (the second heavily doped region134) and the base B (the first doped region108). The larger resistance R1results in the larger potential difference (VEB) between the emitter E and the base B, which further increases the emitter current (IE). As a result, the on-resistance of the electrostatic discharge protection device800can be reduced further by forming the isolation feature122so that the electrostatic current can be rapidly discharged to the ground line VSS through the electrostatic discharge protection device800.

In summary, the embodiments of the present disclosure provide an electrostatic discharge protection device. The electrostatic discharge protection device includes a BJT which is formed from a heavily doped region, a moderately doped region, and a lightly doped well region. When an electrostatic discharge event occurs, the PN junction between the well region and the moderately doped region is broken down at a low voltage to generate a reverse current so that the electrostatic current is discharged through the BJT of the electrostatic discharge protection device without through the semiconductor devices protected by the electrostatic discharge protection device. Therefore, the electrostatic discharge protection device protects the semiconductor devices from damage in the event of an electrostatic discharge.