DATAFLOW GASKETS FOR HANDLING DATA STREAMS

Apparatus and methods for facilitating data movement among circuit blocks are disclosed. In certain embodiments, an integrated circuit (IC) includes a network of dataflow gaskets including a first dataflow gasket coupled to a first circuit block and a second dataflow gasket coupled to a second circuit block. The first circuit block can write to the second circuit block by programming output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket. The header can be provided by the first dataflow gasket to the second dataflow gasket over the network, and in response to the header reaching the second dataflow gasket, the second dataflow gasket can program the input stream registers of the second dataflow gasket for an incoming read stream.

FIELD OF THE DISCLOSURE

Embodiments of the invention relate to electronic systems, and more particularly to, dataflow gaskets for facilitating data movement among circuit blocks.

BACKGROUND

Various techniques can be used to move data between electronic circuits. For example, certain electronic systems use standard bussing for interconnecting circuit blocks for data movement. However, data traffic can be of many types (memory, peripheral, and/or computation) having varying characteristics. Thus, when standard bussing is designed for overall throughput, the bussing can stall at times while slower systems (i.e. off-chip memory) absorb high traffic periods.

In another example, point-to-point bussing can be used to connect each compute block to every other compute block. Point-to-point bussing can support any arbitrary data traffic between circuit blocks but can have unnecessary area and/or power overhead.

SUMMARY OF THE DISCLOSURE

Apparatus and methods for facilitating data movement among circuit blocks are disclosed. In certain embodiments, an integrated circuit (IC) includes a network of dataflow gaskets including a first dataflow gasket coupled to a first circuit block and a second dataflow gasket coupled to a second circuit block. The first circuit block can write to the second circuit block by programming output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket. The header can be provided by the first dataflow gasket to the second dataflow gasket over the network, and in response to the header reaching the second dataflow gasket, the second dataflow gasket can program the input stream registers of the second dataflow gasket for an incoming read stream. Thereafter, the first circuit block can provide write data to the second circuit block by way of the outgoing write stream of the first dataflow gasket and the incoming read stream of the second dataflow gasket.

In one aspect, an integrated circuit (IC) includes a plurality of circuit blocks including a first circuit block and a second circuit block, and a plurality of dataflow gaskets electrically connected by a network of gasket interconnect. The plurality of dataflow gaskets can include a first dataflow gasket comprising output stream registers and an output memory coupled to the first circuit block, and a second dataflow gasket comprising input stream registers and an input memory coupled to the second circuit block. The first circuit block can write data to the second circuit block by programming the output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket, and by the second dataflow gasket programming the input stream registers of the second dataflow gasket for an incoming read stream in response to the header reaching the second dataflow gasket over the network.

In another aspect, a method of dataflow in an IC is disclosed. The method can include initiating a write from a first circuit block of the IC to a second circuit block of the IC using the first circuit block and programming output stream registers of a first dataflow gasket of the IC for an outgoing write stream using the first circuit block, the first dataflow gasket including an output memory coupled to the first circuit block, and the outgoing write stream including a header identifying a second dataflow gasket of the IC that is electrically connected to the first dataflow gasket by a network of gasket interconnect. The method can further include programming input stream registers of the second dataflow gasket for an incoming read stream in response to the header reaching the second dataflow gasket over the network, the second dataflow gasket further including an input memory coupled to the second circuit block.

In another aspect, a network of dataflow gaskets can include a first dataflow gasket including output stream registers and an output memory configured to couple to a first circuit block. and a second dataflow gasket electrically connected to the first dataflow gasket by a network of gasket interconnect. The second dataflow gasket can include input stream registers and an input memory configured to couple to a second circuit block. The output stream registers of the first dataflow gasket can be programmable for an outgoing write stream that includes a header identifying the second dataflow gasket, and the input stream registers of the second dataflow gasket can be programmable for an incoming read stream in response to the header reaching the second dataflow gasket over the network.

DETAILED DESCRIPTION

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

As integrated circuit (IC) technology is scaled to smaller technology nodes, the transistor density (or number of transistors that can be integrated into a unit area of an IC) increases drastically. The increased density translates to heterogeneous complex chips in which multiple blocks with different architectures are combined into a single die to provide a System-on-Chip (SoC). For example, a single die can include a combination of central processing units (CPUs), digital signal processors (DSPs), and neural processing units (NPUs). An NPU is also referred to herein as a neural network engine (NNE).

On the other hand, in the past few years, neural networks such as convolution neural networks (CNNs), recurrent neural networks (RNNs), and multi-layer perception networks (MLPs) have been shown to outperform traditional DSP algorithms in many fields such as computer vision and speech recognition.

Accordingly, many current and future IC applications consist of DSP algorithms and neural network models. In these applications, while fast data converters (for example, high-speed analog-to-digital converters or ADCs) provide the data for processing, different parts of computational graphs are mapped onto different circuit blocks such as CPUs, DSPs and NPUs. Such mapping gives rise to significant data movement among different circuit blocks. Thus, data transfer between circuit blocks is key to achieving fast and efficient processing for these signal processing applications.

Certain ICs use standard bussing to build a network-on-chip (NoC) for interconnecting circuit blocks for data movement. However, a standard NoC has many types of traffic (memory, peripheral, and/or computation) having varying characteristics. Standard bussing is typically designed for overall throughput, and thus can stall at times while slower systems (i.e. off-chip memory) absorb high traffic periods.

In another example, point-to-point bussing can be used to connect each compute block to every other compute block. Point-to-point bussing can support any arbitrary data traffic between circuit blocks. However, in many domain-specific applications such as signal processing, only a handful of traffic patterns are generated during run time. Accordingly, such generality is not needed, but rather causes an inefficient usage of resources (transistors and wires) and leads to unnecessary area and/or power overhead. For example, point-to-point bussing is not scalable and requires exponentially more wires as the number of compute blocks increases.

Overview of Example Embodiments of Dataflow Gaskets

The following section provides an overview of example embodiments for dataflow gaskets. While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure. Any suitable combination of features of the embodiments described can be combined to provide further embodiments.

Dataflow gaskets for handling data streams are disclosed herein. The dataflow gaskets can be deployed in any number or arrangement to achieve efficient on-chip data movement among different circuit blocks of the die. Each dataflow gasket can be attached to a corresponding circuit block using tightly coupled memories to provide low latency and fast access to incoming and outgoing data streams. Furthermore, memory allocation and buffer management can be handled by the internal logic in the dataflow gasket to reduce or eliminate software development efforts.

In certain embodiments, an IC includes a network of dataflow gaskets including a first dataflow gasket coupled to a first circuit block and a second dataflow gasket coupled to a second circuit block. The first circuit block can write to the second circuit block by programming output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket. The header can be provided by the first dataflow gasket to the second dataflow gasket over the network, and in response to the header reaching the second dataflow gasket, the second dataflow gasket can program the input stream registers of the second dataflow gasket for an incoming read stream. Thereafter, the first circuit block can provide write data to the second circuit block by way of the outgoing write stream of the first dataflow gasket and the incoming read stream of the second dataflow gasket.

By using dataflow gaskets in this manner, fast and efficient transfer of data is achieved without the first circuit block and the second circuit block needing to directly communicate with one another and/or understand each other's internal memory addressing.

In addition to being configurable for a write operation, the dataflow gaskets can perform other operations including, but not limited to, read, register write, register read, stream merge, and/or stream forking operations.

The dataflow gaskets can have networking capabilities in which dataflow gaskets can be networked using fast internal interconnects. The internal interconnect topology can be customizable based on the traffic patterns that exist in the computational graph of a particular signal processing application. Accordingly, an efficient usage of resources used for interconnects is provided.

Furthermore, the dataflow gaskets can be integrated into an IC alongside of traditional NoCs in different configurations. Thus, the IC can include a network of dataflow gaskets alongside other levels of bussing providing varying performance levels, such as different degrees of connectivity, throughput and/or latency.

Description of Embodiments of Dataflow Gaskets shown in Figures

FIG.1is a schematic diagram of one embodiment of a dataflow gasket10. The dataflow gasket10is depicted as being coupled to a circuit block11, which can be, for example, a CPU, DSP, NNE, reconfigurable compute unit (for example, a field programmable gate array or FPGA), or other intellectual property (IP) circuit block. The dataflow gasket10includes a crossbar switch13, an input memory15, an output memory16, registers17, and a control circuit18. The dataflow gasket10can be interconnected with other dataflow gasket(s) on-chip as part of a larger NoC. Thus, dataflow gaskets can be arranged on an IC to form a desired NoC suitable for a particular IC design or application. An IC is also referred to herein as a semiconductor die or chip.

In the illustrated embodiment, the crossbar switch13includes an input-side that is coupled to input ports (also referred to herein as target ports) and to the output memory16. The input ports receive data packets from a network of dataflow gaskets. The crossbar switch13also includes an output-side that is coupled to output ports (also referred to herein as initiator ports) and to the input memory15. The output ports provide data packets to other dataflow gasket(s) in the network. The crossbar switch13is controlled by the control circuit18to provide desired switch connectivity between the input side and the output side.

Accordingly, the crossbar switch13can provide desired connections between the input side and the output side to thereby route data into and out of the dataflow gasket10. In a first example, data received on the input ports is routed by the crossbar switch13to the input memory15. In a second example, data received on the input ports is routed by the crossbar switch13to the output ports. In a third example, data from the output memory16is routed by the crossbar switch13to the output ports.

With continuing reference toFIG.1, the registers17(also referred to herein as a register file) are used to hold a variety of information, including, for example, gasket identification information for identifying the gasket within the network of dataflow gaskets, a routing table, input stream configuration for input stream(s), output stream configuration for output stream(s), and/or feature configuration data for controlling a variety of gasket features.

The input memory15receives data from the crossbar switch13, and is tightly coupled to the circuit block11. Additionally, the output memory16provides data to the crossbar switch13and is tightly coupled to the circuit block11. Both the circuit block11and the dataflow gasket10have access to the input memory15and the output memory16. In one example, the dataflow gasket10can write to the input memory15and read from the output memory16, while the circuit block11can read from the input memory15and write to the output memory16. However, other implementations are possible, such as configurations in which both the dataflow gasket10and the circuit block11can read and write to both the input memory15and the output memory16.

In certain implementations, the input memory15and/or the output memory16are implemented with a circular buffer to facilitate memory allocation and dataflow. By using circular buffer(s), complexity in reading and writing over the memory interface between the circuit block11and the dataflow gasket10is reduced. Accordingly, during design of an IC, a desired architecture of circuit blocks (CPUs, DSPs, NNEs, reconfigurable compute units, and/or other IP blocks) can be placed and easily interconnected to one another by a network of dataflow gaskets with little to no design overhead.

FIG.2Ais a schematic diagram of a one embodiment of an IC30including circuit blocks interconnected by dataflow gaskets.

In the illustrated embodiment, the IC30includes a first dataflow gasket21, a second dataflow gasket22, a third dataflow gasket23, a fourth dataflow gasket24, a first circuit block25, a second circuit block26, a third circuit block27, a fourth circuit block28, and interconnect forming an NoC29. Although four dataflow gaskets and four circuit blocks are depicted, more or fewer gaskets and circuit blocks can be included as indicated by the ellipsis.

As shown inFIG.2A, the NoC29interconnects the dataflow gaskets21-24to one another. Additionally, the dataflow gaskets21-24are connected to the circuit blocks25-28, respectively. The dataflow gaskets21-24and NoC29allow the efficient transfer of data between the depicted circuit blocks25-28.

Although one arrangement of dataflow gaskets is shown, dataflow gaskets can be connected in a wide variety of ways. Indeed, dataflow gaskets serve as building blocks for data flow that allow for implementing the NoC29to achieve standard topologies (for instance, mesh or ring) as well as any custom topology.

FIG.2Bis a schematic diagram of another embodiment of an IC50including circuit blocks interconnected by dataflow gaskets.

In the illustrated embodiment, the IC50includes dataflow gaskets41(G1),42(G2),43(G3),44(G4),45(G5),46(G6), and47(G7). The dataflow gaskets41-47are interconnected with one another using an example custom interconnect topology. As shown inFIG.2Bby the directional arrows, a particular gasket can communicate with a subset of the other gasket(s). Such communication can be unidirectional (read or write only) or bidirectional (read and write).

The gaskets41-47are each connected to a particular circuit block, which are of varying types of IP blocks, in this embodiment. In particular, the IC50includes a DSP51coupled to the dataflow gasket41, a memory52coupled to the dataflow gasket42, a digital-to-analog converter (DAC)53coupled to the dataflow gasket43, a memory54coupled to the dataflow gasket44, a fifth generation reduced instruction set computer (RISCV or RISC-V)55coupled to the dataflow gasket45, a fast Fourier transform (FFT) processor56coupled to the dataflow gasket46, and an ADC57coupled to the dataflow gasket47.

The IC50depicts one example application that can benefit from the use of dataflow gaskets to provide efficient transform of data between various circuit blocks. Although one example topology is shown, dataflow gaskets can be deployed in a wide variety of standard, semi-custom, or custom topologies to facilitate dataflow between any desired circuit blocks. Such dataflow can be further expanded by connection of one or more of the dataflow gaskets to backbone interconnect58, thereby allowing connectivity to further components.

FIG.3is a schematic diagram of another embodiment a dataflow gasket60. The dataflow gasket60is depicted as being coupled to a circuit block61, which can be, for example, a CPU, DSP, NNE, reconfigurable compute unit, or other IP circuit block such as any of those shown above with reference toFIG.2B. The dataflow gasket60includes a crossbar switch71, an input memory75, an output memory76, input stream registers77, and output stream registers78. Although not shown inFIG.3, the dataflow gasket60can include additional functional and control circuitry, which has not been depicted inFIG.3for clarity of the figure.

As shown inFIG.3, the crossbar switch71is connected to gasket interconnect62that is interconnected with other dataflow gasket(s) as part of an NoC. As shown inFIG.3, the gasket interconnect62is used to send and receive data packets, such as the data packet63, which has a stream identification (ID)64.

With continuing reference toFIG.3, the input memory75is tightly coupled to the circuit block61. Such tight coupling can be achieved in any suitable manner, including, but not limited to, using a custom or non-custom memory interface with a fixed latency read path.

In one example, a two-cycle pipelined bus performs a read operation by broadcasting a read transaction request on a first cycle, and returning data on a second cycle, in which the second cycle can contain another transaction request. The latency is substantially fixed between the read request and the delivery of the data. For instance, an Advanced High-performance Bus (AHB) can operate in this manner to provide tight coupling and enable one transfer per cycle.

As shown inFIG.3, data received from the gasket interconnect62can be provided from the crossbar switch71for writing to the input memory75. Such writing can be facilitated by the use of the input stream registers77. The input memory75includes a circular buffer81, which is used by the circuit block61for reading data from the input memory75. The circular buffer81simplifies memory addressing for the circuit block61, thereby providing a memory interface between the circuit block61and the dataflow gasket60that avoids a need for the circuit block61to understand the internal memory addressing of the input memory75. As shown inFIG.3, the circular buffer81also selectively activates an interrupt signal to alert the circuit block61as to when new data is available for reading.

In the illustrated embodiment, the output memory76is tightly coupled to the circuit block61, which can write data to the output memory76. Additionally, the output memory76can provide data in the form of data packets (for example, data packet83with stream ID84) to the gasket interconnect62by way of the crossbar switch71. The output of data from the output memory76can be facilitated by the use of the output stream registers78. The output memory76includes a circular buffer82, which is used by the circuit block62for writing data to the output memory76. The circular buffer82simplifies memory addressing for the circuit block61, thereby providing a memory interface between the circuit block61and the dataflow gasket60that avoids a need for the circuit block61to understand the internal memory addressing of the output memory76.

With general reference toFIGS.4A-6B, a network of interconnected dataflow gaskets enables communication of data stream traffic between circuit blocks. For example, each dataflow gaskets is connected to an associated circuit block using tightly coupled input and output memories, while the network of dataflow gaskets can perform operations including, but not limited to, write, read, register write, register read, stream merge, and/or stream forking operations. Such traffic can include a stream originating from a connected gasket that is directed to another gasket. When in route, the stream can pass through intervening gaskets until reaching the destination.

In certain implementations, when initially establishing a stream, a destination dataflow gasket can send an error response to a source dataflow gasket when the destination dataflow gasket has insufficient resources available to handle the request. Additionally, the source dataflow gasket can wait for an okay response on start of the header transaction before sending the rest of the data stream. Additionally or alternatively, a destination dataflow gasket can stall a data transfer when running low on resources.

FIG.4Ais a schematic diagram of one embodiment of a write data stream120using dataflow gaskets. As shown inFIG.4A, a source processing element (PE) or first circuit block105is connected to a first dataflow gasket101, and a destination processing element or second circuit block106is connected to a second dataflow gasket102. Additionally, the first dataflow gasket101and the second dataflow gasket102are connected to one another over gasket interconnect or NoC104, which can include any number of dataflow gaskets.

To perform a write operation between the first circuit block105and the second circuit block106, the first circuit block105programs output stream configuration registers112in the first dataflow gasket101to setup an outgoing write stream. The outgoing write stream identifies (by way of a header) the second dataflow gasket102as a destination. Additionally, the outgoing write stream can be provided from the output memory114of the first dataflow gasket101to the NoC104.

When the stream header reaches the second dataflow gasket102, the second dataflow gasket102uses the header data to program the input stream configuration registers115if the second dataflow gasket102to setup an incoming data stream. The incoming data stream is received by an input memory117of the second dataflow gasket102from the NoC104. Additionally, as data is received at the second dataflow gasket102, the second dataflow gasket102can interrupt the second circuit block106as desired to inform the second circuit block106of the arrival of data.

FIG.4Bis a schematic diagram of one embodiment of a read data stream130using dataflow gaskets. As shown inFIG.4B, a first circuit block105is connected to a first dataflow gasket101, and a second circuit block106is connected to a second dataflow gasket102. Additionally, the first dataflow gasket101and the second dataflow gasket102are connected to one another over NoC104.

To perform a read operation of the second circuit block106initiated by the first circuit block105, the first circuit block105can program input stream configuration registers111in the first dataflow gasket101to set an incoming read stream. Additionally, the first dataflow gasket101can send a stream over the NoC104with a header identifying the second dataflow gasket102as a destination. When the stream header reaches the second dataflow gasket102, the second dataflow gasket102can use the header data to program the output stream configuration registers116of the second dataflow gasket102to setup an outgoing data stream. The first dataflow gasket101thereafter initiates reads to the second dataflow gasket102, which returns data from the second dataflow gasket's output memory118using a circular buffer. The returned data is received by an input memory113of the first dataflow gasket101, which can interrupt the first circuit block105as desired to inform the first circuit block105of the arrival of data.

Thus, in certain implementations, a read stream can be implemented by setting a write stream in a reverse direction.

In the illustrated embodiment, the second circuit block106connected to the destination gasket102is aware of the output stream and the data needed to be sent.

With reference toFIGS.4A and4B, a source dataflow gasket can be used to set up one data stream, while a destination dataflow gasket sets up one corresponding stream or multiple data streams in the case of merging. In such implementations, circular buffers can be used for both the source dataflow gasket and the destination dataflow gasket.

FIG.5Ais a schematic diagram of one embodiment of a register write stream140using dataflow gaskets. As shown inFIG.5A, a first circuit block105is connected to a first dataflow gasket101, and a second circuit block106′ is connected to a second dataflow gasket102′. The second circuit block106′ is depicted as an attached memory (MEM), such as an attached static random-access memory (SRAM). However, in other implementations the second circuit block106′ can correspond to a processing element. The first dataflow gasket101and the second dataflow gasket102′ are connected to one another over NoC104.

A register write stream can be used to program any register in any dataflow gasket on the NoC104. For example, the first circuit block105can setup a register write stream by programming the output stream configuration registers112of the first dataflow gasket101that is connected to the first circuit block105.

The data written to the first dataflow gasket's circular buffer travels from the output memory114of the first dataflow gasket101to the second dataflow gasket102′, where the data is written to the second dataflow gasket's registers. In certain implementations, a register write stream uses an AXI write channel.

In the illustrated embodiment, the second dataflow gasket102′ has its own address space that includes multiple regions. The multiple regions include a register file131(with addresses ranging from Add A to Add B), an input random access memory (RAM)132(with addresses ranging from Add C to Add D), an output RAM133(with addresses ranging from Add E to Add F), and the attached memory106′ (with addresses ranging from Add G to Add H).

The address space of the second dataflow gasket102′ need not be connected to the address space of the PE105in any manner. Rather, the PE105can read or write data to the first dataflow gasket101directly and/or by way of circular buffers (implemented using the output RAM114), and thereafter the data transfer is stream based. Thus, the dataflow gaskets connect to each other using their own gasket interconnect/NOC, and provide a mechanism to connect different subsystems without being part of any PE's address space.

FIG.5Bis a schematic diagram of one embodiment of a register read stream150using dataflow gaskets. As shown inFIG.5B, a first circuit block105is connected to a first dataflow gasket101, and a second circuit block106′ is connected to a second dataflow gasket102′. The second circuit block106′ is depicted as an attached memory, but can be a processing element in other implementations. The first dataflow gasket101and the second dataflow gasket102′ are connected to one another over NoC104.

A register read stream can be used to read any register in any dataflow gasket on the NoC104. For example, the first circuit block105can setup a register read stream by programming input stream configuration registers111, which in certain implementations use an AXI read channel. For example, the first dataflow gasket101can issue AXI reads to the destination dataflow gasket102and store the returned data into the input memory113. After the requested data is received, an interrupt can be sent to the processing element105.

With reference toFIGS.5A and5B, a source dataflow gasket can be used to set up one data stream, while a destination dataflow gasket need not set up a corresponding stream since register streams can access all the resources mapped to the local address space of the gasket. For example, such local address space can include registers, local input and output memories, and/or external RAM connected to the gasket by way of an AHB port or other suitable interface. Thus, for register streams, circular buffers can be used by the source dataflow gasket but need not be used by the destination dataflow gasket.

FIG.6Ais a schematic diagram of one embodiment of data stream merging230using dataflow gaskets. As shown inFIG.6A, a first source IP circuit block201is connected to a first dataflow gasket211, a second source IP circuit block202is connected to a second dataflow gasket212, and a destination IP circuit block203is connected to a third dataflow gasket213. Additionally, the first dataflow gasket211, the second dataflow gasket212, and the third dataflow gasket213are connected to one another by gasket interconnect or NoC204.

In the illustrated embodiment, the first source IP circuit block201and the second source IP circuit block202each send data that is merged by the destination IP circuit block213.

For example, as shown inFIG.6A, first data from the first source IP circuit block201is provided to the output tightly coupled memory (TCM)215of the first dataflow gasket211. The output TCM215converts the data to packets (for example, packet221with stream ID223), which are sent by the first dataflow gasket211to the third dataflow gasket213over the gasket interconnect204. Additionally, second data from the second source IP circuit block202is provided to the output TCM216of the second dataflow gasket212. The output TCM216converts the data to packets (for example, packet222with stream ID224), which are sent by the second dataflow gasket212to the third dataflow gasket213over the gasket interconnect204.

The third dataflow gasket213receives the packets221/222, which can be identified by the third dataflow gasket213as being directed to the third dataflow gasket213by way of the stream IDs223/224. The third dataflow gasket213merges the first data and the second data into merged data that is stored in an input TCM217of the third dataflow gasket213. Pointers from the output stream registers218are used to direct storage of the received data packets221/222into a circular buffer219of the input TCM217.

The merged data is readable by the destination IP circuit block203. Additionally, the data is readable without the destination IP circuit block203needing to have an understanding of how the data was merged and/or is stored within the dataflow gasket213to which it is coupled.

FIG.6Bis a schematic diagram of one embodiment of data stream forking using dataflow gaskets. As shown inFIG.6B, a first destination IP circuit block231is connected to a first dataflow gasket241, a second destination IP circuit block232is connected to a second dataflow gasket242, and a source IP circuit block233is connected to a third dataflow gasket243. Additionally, the first dataflow gasket241, the second dataflow gasket242, and the third dataflow gasket243are connected to one another by gasket interconnect or NoC234.

In the illustrated embodiment, the source IP circuit block233outputs a data stream that is forked into a first data stream received by the first destination IP circuit block231and a second data stream received by the second destination IP circuit block232. In certain implementations, the first data stream and the second data stream carry identical data content but have different headers.

As shown inFIG.6B, a data stream from the source IP circuit block233is provided to the output TCM253of the third dataflow gasket243. The output TCM253includes a circular buffer257that cases complexities in addressing with respect to the source IP circuit block233writing data to the output TCM253. The output TCM253converts the data to packets (for example, packet258with stream ID259), which are sent by the third dataflow gasket243to the first dataflow gasket241and/or the second dataflow gasket242over the gasket interconnect204. By controlling the stream ID259, all or a portion of the data stream can be directed to the first dataflow gasket241and/or the second dataflow gasket242(and thus to the first destination IP circuit block231and/or the second destination IP circuit block232) as appropriate.

As shown inFIG.6B, the first dataflow gasket241includes an input TCM251for storing all or a portion of the data stream from data packets that are directed to the first dataflow gasket241. The input TCM251includes a circular buffer255, which allows the first destination IP circuit block231to access that data without needing to understand how the data was received and/or stored within the input TCM251. Likewise, the second dataflow gasket242includes an input TCM252for storing all or a portion of the data stream from data packets that are directed to the second dataflow gasket242. The input TCM252includes a circular buffer256, which allows the second destination IP circuit block232to access stored data within the input TCM252.

FIG.7is a schematic diagram of another embodiment of a dataflow gasket350. The dataflow gasket350includes a crossbar switch301, a packing handling circuit302, a memory circuit303(also referred to as a storage unit), a local device interconnect circuit304, asynchronous first-in first-out (FIFO) circuitry305, and a clock generation circuit306. The dataflow gasket350connects to an IP circuit block by way of local device interconnect345, and connects to gasket interconnect/NoC by way of input ports346and output ports347.

In the illustrated embodiment, the crossbar switch311includes an input-side switch311and an output-side switch312. Additionally, the packet handling circuit302includes a packet parser321, multicast/forking logic322, a packet generation circuit323, an arbitration and muxing circuit324, and a register file325providing a routing table. Furthermore, the memory circuit303includes input circular buffer logic331, input and time-stamping RAM332, merge logic333, output circular buffer logic334, output and time-stamping RAM335, and a register file336providing stream configuration and score boarding. Additionally, the local device interconnect unit304includes a local clock generation circuit344, an input asynchronous FIFO341, an output asynchronous FIFO342, and interface logic343.

With continuing reference toFIG.7, the data path of the dataflow gasket350generally includes two major sub-blocks including a routing unit and a stream unit. The routing unit can be sub-divided into the packing handling circuit302and the crossbar switch301. Additionally, the stream unit can be subdivided into the storage unit303and the local device interconnect unit304.

The crossbar switch301connects to the crossbar switches of other dataflow gaskets by way of gasket interconnect/NoC. In the illustrated embodiment, the dataflow gasket350communicates with other dataflow gaskets by way of a multi-cycle bus, which can have unfixed latency in some implementations.

In one example, the multi-cycle bus can correspond to an N-cycle bus that can perform component transactions (read address, write address, read data, write data, and write acknowledge) with arbitrary pipelining. An N-cycle bus allows one transfer per cycle, but operates with latency that is not fixed. For instance, an Advanced Extensible Interface (AXI) can operate in this manner.

In another example, a two cycle un-pipelined bus performs a read operation by broadcasting a read transaction request on a first cycle and returning data on a second cycle, in which the second cycle does not contain another transaction request. For instance, an Advanced Peripheral Bus (APB) can operate in this manner. Although various examples of bus architectures for gasket interconnect are provided, other implementations are possible.

As shown inFIG.7, the dataflow gasket350includes various register files. Such register files can be used to store routing unit information such as gasket ID and routing table. Additionally, the register files can include output stream configuration registers for running a desired number of output streams, and input stream configuration registers for running a desired number of input streams. Furthermore, the register files can include configuration registers used for enabling or disabling gasket features, such as those related to buffer allocation.

The input-side switch311serves to route incoming data through to the output-side switch312and/or to the storage unit303(by way of the packet parser321). The input-side switch311can provide a stream ID to the packet parser321, which can determine whether or not a particular received data packet is intended for the dataflow gasket350. The output-side switch312can provide data coming through from the input-side switch311or data from the packet generation circuit323to the output ports347.

With continuing reference toFIG.7, the multicast/forking logic322can work in combination with the arbitration/multiplexing circuit324to facilitate broadcast of a packet to multiple dataflow gaskets. For example, a source dataflow gasket can send a list of all receiving dataflow gaskets as part of a packet. Once received at a given dataflow gasket, the dataflow gasket can send a list of all recipients of the stream as part of the packet and remove its own ID from the header.

The input and timing stamping RAM332serves to store incoming data. In this example, timestamp access for a FIFO mode is provided. Such a FIFO mode can increment a write pointer for writes and a read pointer for reads. The pointers correspond to addresses to the RAM's and point to a particular location inside the circular buffer of a stream. Thus, working in combination with the circular buffer logic331, the input and timing stamping RAM332implements a circular buffer.

In the illustrated embodiment, merge logic333is included to facilitate a merge of data streams from multiple sources. For example, the merge logic333can facilitate the merge operation discussed earlier with respect toFIG.6A.

The output and timing stamping RAM335serves to store outgoing data. Working in combination with the circular buffer logic334, the output and timing stamping RAM335implements a circular buffer.

The storage unit303can operate with a first clock signal from the AXI clock generation circuit306, while the local device interconnect unit304can operate with a second clock signal from the local clock generation circuit344. The first and second clock signals can be asynchronous.

Accordingly, the input asynchronous FIFO341and the output asynchronous FIFO342are included and controlled by the interface logic343. The asynchronous FIFOs341/342aid in communicating data between the storage unit303and an IP circuit block coupled to the dataflow gasket350by way of the local device interconnect345.

CONCLUSION