Half-rate integrating decision feedback equalization with current steering

Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential signal and a second output differential signal, respectively. The first and second integrating summers alternately drive, during other clock signal phases of the clock signal and its complement, residual voltages of the first output differential signal and the second output differential signal, respectively, to a same voltage level. A first clock signal and a second clock signal are out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.

FIELD OF THE INVENTION

The following description relates to integrated circuit devices (“ICs”). More particularly, the following description relates to a half-rate integrating decision feedback equalization with current steering for an IC.

BACKGROUND

For transmission of wireline data, such transmitted data is conventionally attenuated, delayed and/or corrupted after propagating through a wireline communications channel. Along those lines, intersymbol interference (“ISI”) may occur as is known from transmission of wireline data through a wireline communications channel. Hence, it is desirable and useful to provide feedback equalization of received wireline data, including without limitation decision feedback equalization (“DFE”).

SUMMARY

An apparatus relates generally to a decision feedback equalizer. In such an apparatus, a first integrating summer and a second integrating summer each are configured to receive an input differential signal. A bias current circuit is configured for alternate biasing of the first integrating summer and the second integrating summer. The first integrating summer is configured for integrating during a first clock phase of a first clock signal for transconductance of the input differential signal to a first output differential signal and for resetting during a second clock phase of the first clock signal for driving residual voltages of the first output differential signal to a same voltage level. The second integrating summer is configured for integrating during a first clock phase of a second clock signal for transconductance of the input differential signal to a second output differential signal and for resetting during a second clock phase of the second clock signal for driving residual voltages of the second output differential signal to the same voltage level. The first clock signal and the second clock signal are configured to be out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.

A method relates generally to decision feedback equalization. In such a method, an input differential signal is obtained by a first integrating summer and a second integrating summer having a bias current circuit in common. First integrating is performed with the first integrating summer during a first clock phase of a clock signal for transconductance of the input differential signal to a first output differential signal. First resetting is performed with the second integrating summer during the first clock phase of the clock signal for driving residual voltages of a second output differential signal to the same voltage level. Second integrating is performed with the second integrating summer during a second clock phase of the clock signal for transconductance of the input differential signal to the second output differential signal. Second resetting is performed with the first integrating summer during the second clock phase of the clock signal for driving residual voltages of the first output differential signal to same voltage level.

An apparatus relates generally to decision feedback equalizer. In such an apparatus, a single stage integrating summer has a first integrating summer and a second integrating summer and has a bias current circuit in common as between the first integrating summer and the second integrating summer. Each of the first integrating summer and the second integrating summer are configured to receive a same input differential signal. The first integrating summer is configured for integrating during a first bit period for transconductance of the input differential signal to a first output differential signal and for resetting during a second bit period immediately following the first bit period for driving residual voltages of the first output differential signal to a same voltage level. The second integrating summer is configured for integrating during the second bit period for transconductance of the input differential signal to a second output differential signal and for resetting during a third bit period immediately following the second bit period for driving residual voltages of the second output differential signal to the same voltage level.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. It should be apparent, however, to one skilled in the art, that one or more other examples and/or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative examples the items may be different.

Exemplary apparatus(es) and/or method(s) are described herein. It should be understood that the word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any example or feature described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples or features.

Before describing the examples illustratively depicted in the several figures, a general introduction is provided to further understanding.FIG. 1-1is graphical diagram depicting an exemplary conventional transmission pulse and a corresponding reception and intersymbol interference (“ISI”) pulses. Transmission pulse12, as well as a corresponding reception or received pulse, namely a corresponding cursor pulse13, is respectively depicted along a time x-axis10versus an amplitude y-axis11. Generally, cursor pulse13is a delayed and attenuated version of transmission pulse12. Transmission pulse12may be encoded as a symbol prior to transmission, and during propagation through a wireline communications channel to a receiver, such transmission pulse may interfere and/or be interfered with by one or more other transmission pulses. This ISI may result in receiving one or more precursor ISI pulses, such as precursor ISI pulse14, and one or more postcursor ISI pulses, such as postcursor ISI pulses15, along with cursor pulse13.

FIG. 1-2is graphical diagram depicting an exemplary conventional stream of transmission pulses and corresponding reception and intersymbol interference (“ISI”) pulses. In this example, there are three positive followed by one negative transmission pulse in stream of transmission pulses16. While these transmission pulses result in corresponding reception pulses, as generally indicated by arrows18, such reception pulses may be superposed with one or more ISI pulses, such a precursor and/or one or more postcursor ISI pulses in this example, as generally indicated as stream of reception pulses17, namely superposed pulse responses. For a stream of transmission pulses16, in each sampling instance, one or more ISI pulses may be added to a received pulse, which may mislead detection by a receiver resulting in one or more errors.

FIG. 1-3is graphical diagram depicting an exemplary conventional stream of reception and ISI pulses without decision feedback equalization (“DFE”) for the superposed pulse responses ofFIG. 1-2. Received stream of pulses20may be a resultant response at a receiver after detection. However, in this example, an error19results from such detection.

DFE may be used to remove or at least substantially reduce postcursor ISI by adding data dependent correction voltages to a scaled version of a received input. A resultant voltage at a decision point of a detector receiving an input may thus have less corruption due to postcursor ISI yielding fewer errors, namely error probability is reduced.

FIG. 2-1is the graphical diagram ofFIG. 1-1with an exemplary DFE illustratively depicted as postcursor ISI counteracting pulses21. DFE taps, namely correction TAPs, may act as inverses of postcursor ISI pulses15. Removal or at least substantial reduction of postcursor ISI pulses15may assist a detector of a receiver in resolving a cursor pulse13. Along those lines, DFE taps of a decision feedback equalizer may be respectively weighted to match a channel response of a transmission communications channel to provide an inverse signal of postcursor ISI, positive or negative. After DFE, a resultant response at a receiver may just be a precursor ISI pulse14and a cursor pulse13.

FIG. 2-2is the graphical diagram ofFIG. 1-2after an exemplary DFE. In this example, postcursor ISI is removed by DFE, leaving received cursor pulses with or without precursor ISI pulses superposed thereon, namely stream of reception pulses22for stream of transmission pulses16received from a communications channel as generally indicated by arrows18.

FIG. 2-3is the graphical diagram ofFIG. 1-3after an exemplary DFE for the superposed pulse responses ofFIG. 2-2. Received stream of pulses23may be a resultant response at a receiver after DFE and after detection. However, in this example, an error19does not result from such detection. Use of DFE may reduce error probability by removing or substantially reducing signal corruption due to postcursor ISI.

FIG. 3is a schematic diagram depicting an exemplary embodiment of a conventional decision feedback equalizer30. DFE is implemented as a feedback loop35where input31, such as a received stream of reception pulses17prior to DFE or generally “input data”, is input to and amplified by an amplifier33. Output of amplifier33is provided onto a chain of correction circuits (“correction TAPs”). Such amplified input data output from amplifier33is progressively adjusted by summing over a positive integer number, N, of correction TAPs, provided by adjustable buffers38respectively coupled to a chain of adders32, to provide a summed signal34.

Each adjustable buffer38has a current sink capability, defined by an adjustable tap weight29. Inputs to adjustable buffers38respectively from delays of delay chain36define a signal of an applied current (i.e., if a current is sunk from a positive or negative line). Chain of adders32may be a “line” for adding currents to provide a summed signal34.

Summed signal34is input to a dynamic comparator or sampler (“L”)35for sampling to make decisions, namely to output digital data from an analog differential signal. For purposes of clarity and not limitation, a clock signal and other known details regarding operation of dynamic comparator35are not illustratively depicted.

Summed signal34is sampled by a dynamic comparator35, and a comparison result39for such sampling output from dynamic comparator35is output. Comparison results39may be generally referred to as “output data”. Each comparison result39may be fed back through delay chain36in order to define or refine correction TAP signals37provided to corresponding adders32. Decision feedback equalizer30is a nonlinear equalizer, as it uses previous decisions or comparison results to eliminate or reduce ISI on pulses currently being processed.

Each tap weight29may be defined by an adaptive algorithm in order to match accurately a communications channel ISI impulse response, as generally represented by adjustable buffers38, though implemented as multipliers coupled to receive respective weights29. Adjustable buffers38may be coupled to receive a progressively delayed comparison result39tapped out from delay chain36from a corresponding tap thereof. InFIG. 3, each delay in delay chain36may represent one unit interval (“1UI”) of delay. Outputs of adjustable buffers38may be output to corresponding correction adders/subtractors32associated with such adjustable buffers38for subtraction. As decision feedback equalizer30is well known, it is not described in unnecessary detail for purposes of clarity and not limitation.

In a decision feedback equalizer, such as decision feedback equalizer30for example, a significant contributor to power consumption is amplifier33and adjustable buffers38. A circuit used to amplify an input signal and provide correction TAPs is conventionally referred to as a “DFE summer” or “summing amplifier” and conventionally is implemented with a number N of transconductance pairs (“gm-pairs”) of transistors coupled in parallel for sharing a resistive load.

Power consumption in continuous time DFE summer may be set by output capacitance and settling time. Along those lines, a continuous time DFE summer is generally said to be fully settled or fully steered within 3 to 4 RC time constants in one bit period, namely half of a clock period or 1 unit interval (“1UI”), for an effective postcursor ISI correction. In other words, summed signal34is to be fully settled in 1UI. A bit of output differential voltage of output, namely comparison results39, has different timing constraints than summed signal34. If input31represents a string of bits, then each corresponding bit in summed signal34input to dynamic comparator35may be settled within 1UI. For a differential output change from logic 1 to logic 0, or vice versa, then voltage may have a rail-to-rail swing or transition in 1UI. Thus, such transitions are to be settled within 1UI, namely before sampling by dynamic comparator35.

Generally, output voltage swing, Vsw, is fixed, and output capacitance, Cout, is set by input gate sizes of dynamic comparator35, interconnection capacitance, and parasitic capacitance of correction TAPs. Power consumption may be generally adjusted by a resistance, R, as Vsw and Cout may be generally considered set values. Along those lines, bandwidth may define resistance R, as a time constant is defined by RC. A biasing current Ib (power) may then be defined by a value for resistance R to attain a target bandwidth for a specified voltage swing Vsw. In other words, resistance, R, may be considered Vsw divided by biasing current Ib output from current source of amplifier33. A minimum settling time may be approximately three RC time constants of a continuous time DFE summer, namely 3×RCout; however, longer settling times, such as higher multiples than three of an RC time constant, may be used in other implementations.

High current values, namely small resistances, may be used to achieve a 3×RC settling time in one bit period or 1UI. With these parameters, a bias current output from bias current source may be set equal to or greater than a 3×VswCout/1UI. Bias current may be increased above a 3× multiple to improve linearity and/or to increase current density, as may vary from application-to-application.

Unfortunately, a continuous time DFE summer is slowed by settling time and consumes significant power, which may preclude use of a continuous time DFE summer in high-speed applications and/or low power applications.

FIG. 4is a schematic diagram depicting an exemplary integrating DFE summer60.FIG. 4is further described with simultaneous reference toFIGS. 3 and 4.

Integrating DFE summer60replaces load resistors of a continuous time DFE summer with PMOS transistors forming a clocked reset switch61. Integrating DFE summer60is more power efficient than continuous time DFE summer.

Additionally, where a continuous time DFE summer may fully settle in a 3×RC equivalent to a 1UI for proper operation thereof, integrating DFE summer60integrates an input31during 1UI. This integration of an input in 1UI may be compared to settling in one RC time constant for unitary gain. With these parameters, a bias current, Ib, output from bias current source45may be set equal to or greater than a VswCout/1UI. Along those lines, bias current in DFE summer60may be reduced by a factor of 3 as compared with continuous time DFE summer.

DFE summer60is coupled between a supply voltage (“supply node”)41and a ground voltage (“ground node”)42. Input data31is a differential input, namely summer input, and input data is differentially provided to gates of a pair of transistors. In this example, NMOS transistors are illustratively depicted; however, these and/or other types of transistors may be used in other implementations. Along those lines, even though NMOS transistors are used another type of polarity, such as PMOS transistors, may be used though with source and ground nodes reversed.

A positive (“true”) input voltage side (“Vinp”)44-1of input data31is provided to a gate of transistor43-1, and a negative (“complement”) input voltage side (“Vinn”)44-2of input data31is provided to a gate of transistor43-2. Source nodes of transistors43-1and43-2are commonly coupled at source node46to receive a bias current from current source45, which current source45is coupled between ground node42and source node46. In this example, current source45is a fixed current source.

Drain nodes48-1and48-2respectively of transistors43-1and43-2are respectively coupled to drain nodes of PMOS transistors57-1and57-2, and source nodes of transistors57-1and57-2are commonly coupled at supply node41. Transistors57and transistors43may be thought of as amplifier33ofFIG. 3coupled to a current source45, where a differential output49from amplifier33is sourced from drain nodes48-1and48-2, or more generally DFE summer output nodes48-1and48-2. While current source45may be considered part of amplifier33, for purposes of clarity and not limitation current source45is considered separately from amplifier33. Moreover, transistors57may be considered a separate clocked reset switch61.

Drain nodes48-1and48-2for differential output49, respectively a positive side output voltage (“Vop”) and a negative side output voltage (“Von”), are respectively coupled to a positive side conductive line51-1and a negative side conductive line51-2for providing a differential DFE summer output or summed signal34. Chain of correction TAPs may be formed of a chain of current steering circuits50-1through50-N. Each of current steering circuits50-1through50-N includes a gm-pair of transistors coupled in parallel and an adjustable current source, so generally only current steering circuit50-1is described below in detail for purposes of clarity and not limitation.

Input differentially provided to gates of each pair of transistors, such as transistors53-1and53-2for example, coupled for transconductance is feedback from a delay chain, such as delay chain36ofFIG. 3, for differential feedback input of a differential voltage output, such as comparison results39. Along those lines, each current steering circuit50may include an adjustable current source55for adjustment, and thus each adjustable buffer38ofFIG. 3is effectively implement as a current steering source coupled to a pair of transconductance transistors inFIG. 4. In this example, NMOS transistors are illustratively depicted; however, these and/or other types of transistors may be used in other implementations.

A positive side52-1of a comparison result39, such as via a delay chain as previously described, may be provided to a gate of transistor53-1, and a negative side52-2of such a comparison result39may be provided to a gate of transistor53-2. Source nodes of transistors53-1and53-2are commonly coupled at source node56to receive an adjustable bias current from current source55, which current source55is coupled between ground node42and source node56. Drain nodes58-1and58-2respectively of transistors53-1and53-2are respectively coupled to conductive lines51-1and51-2, which are effectively respectively coupled to load transistors57-1and57-2at respective ends thereof. A positive or negative correction may thus be applied.

Current steering circuits50are configured only to subtract current for providing a summed signal34. However, a positive correction is obtained responsive to current subtracted from a negative output rail, and a negative correction is obtained responsive to current subtracted from a positive output rail.

Along those lines, using only subtraction, a positive or negative correction may be obtained from each pair of drain nodes58-1and58-2from each of current steering circuits50for progressive correction onto a differential output49obtained from DFE summer output nodes48-1and48-2for providing a differential DFE summer output or summed signal34. Along those lines, amplifier33and current steering circuits50share load of transistors57-1and57-2as respectively coupled to conductive lines51-1and51-2.

Even though a maximum differential voltage capable of being output from amplifier33is a voltage difference between supply node41and ground node42, less voltage drops due to resistive loads of transistors57, a maximum output swing for an integrating summer is generally limited to approximately ⅓ of supply voltage at supply node41in order to have sufficient linear behavior. One or more of current steering circuits50may be used to apply differential voltage to a voltage output from amplifier33by current steering. Current steering, namely adjustment of current sources55is respectively controlled by feedback, namely respective outputs of adjustable buffers38. Along those lines, voltage amplitude may be progressively adjusted to correct for a communications channel.

In order to save power, load resistors of a continuous time DFE summer are replaced by a PMOS clocked reset switch61in integrating DFE summer60. In this implementation, PMOS transistors57-1and57-2respectively replace transistors57-1and57-2.

For integrating DFE summer60, output capacitance may be charged to a supply voltage level, such as an analog Vtt voltage (“avtt”) for example, of supply node41during one UI and such capacitance may be discharged by a gm-pair current, namely current driven through transistors43-1and43-2, during the immediately next IU. Along those lines, gates of PMOS transistors57-1and57-2may be commonly coupled to receive a clock signal54to periodically electrically couple and decouple drain nodes48-1and48-2to and from an analog supply voltage, such as analog Vtt for example, sourced from supply node41. In brief, a gm-pair differential current is transconducted through transistors43for integrating through output capacitance when clocked reset switch61is open, namely clock signal54is at a high voltage level for electrically decoupling transistors43from supply node41for generating a differential voltage in differential output49proportional to a corresponding input differential voltage31.

However, during a reset phase, namely when transistors43are electrically coupled to supply node41through PMOS transistors57, namely when clock signal54is at a low voltage level, a data dependent residual differential voltage may be present on drain nodes48-1and48-2. This residual voltage may generate an offset in a next integrating period of DFE summer60, namely when next PMOS transistors57are in a substantially conductive state responsive to a low state of clock signal54. An amount of offset may depend on data present in integrating DFE summer60during a reset phase immediately prior to an integrating phase, and such offset may mislead a DFE decision of dynamic comparator35. Moreover, for high-speed operation, such offset may have less time to dissipate prior to a next sampling by dynamic comparator35. Thus, this offset may increase error probability. However, keeping such offset in a reset phase to an acceptably low level using just an integrating DFE summer60may involve a significant increase in size of PMOS transistors57, resulting in increased power consumption due to buffering of clock signal54.

As described below in additional detail, settling time is avoided by an integrating DFE summer though with substantially less data dependent residual differential voltage than integrating DFE summer60without a significant increase in the size. Along those lines, effectively an amplifier of integrating DFE summer60is duplicated, though with a common bias current circuit for half-rate (“odd-even”) operation.

An odd amplifier and an even amplifier are used for an integrating DFE summer for continuous bi-modal operation. Such continuous bi-modal operation of an integrating half-rate DFE summer allows for a less than a one RC time constant integrating phase with no residual offset after a reset phase. Along those lines, such a continuous bi-modal operation integrating DFE summer may have no settling time. Because there is no settling time, less current may be used, namely less power consumption, as such current does not need to be significantly increased to reduce settling time for high-frequency operation.

Moreover, such an integrating DFE summer may be used in an decision feedback equalizer with a first DFE correction TAP unrolled, as time limited paths of such speculation or unrolling may be operated within UI limits therefor due to having a less than one RC time constant integrating phase. For high frequency operation, a first tap correction of an integrating DFE summer may be implemented by an unrolled feedback DFE. Conventionally, two separate continuous time DFE summers were operated in parallel, namely an EVEN path and an ODD path, at the expense of approximately a doubling of current consumption. However, even this ODD/EVEN path implementation may have a residual data dependent error.

To reduce data dependent error over such a conventional configuration, a bias current circuit common to both EVEN and ODD paths may be used with continuous bi-modal operation of an integrating half-rate DFE summer. Moreover, an additional benefit to this bias current circuit common to both EVEN and ODD paths implementation is a reduction in power consumption.

With the above description borne in mind, various configurations for a continuous bi-modal operation integrating DFE summer are generally described below.

Along those lines,FIG. 5is a schematic diagram depicting an exemplary portion of an ODD-EVEN decision feedback equalizer100with a first tap correction unrolled. For purposes of clarity by way of example and not limitation, single lines are illustratively depicted inFIG. 5for differential voltages, though not all lines inFIG. 5are for differential voltages as shall be apparent from the following description.

A differential input31is provided to a DFE summer200of ODD-EVEN decision feedback equalizer100. DFE summer200includes an even DFE summer102and an odd DFE summer101, as described below in additional detail. Differential input31is simultaneously provided as inputs to both DFE summers101and102; however, DFE summers101and102share a bias current circuit, as described below in additional detail though not illustratively depicted in DFE summer200ofFIG. 5for purposes of clarity and not limitation. Along those lines, DFE summer200is a single stage with two differential voltage output channels, as DFE summer200includes a common bias current circuit for both odd and even paths of DFE summer200. Along those lines, differential output voltages of both channels may be fully reset by alternating or interleaving within such single stage integrating DFE summer200, as described below in additional detail. Furthermore, current steering may be provided between two or more paths for an integrating DFE summer200or other time interleavable device, even though the following description is for a half-rate interleaving.

A differential voltage output from even DFE summer102may be provided to unit threshold (“UT”) comparators111through114, and a differential voltage output from odd DFE summer101may be provided to comparators115through118. Comparators111through118may be latching comparators with a settable offset, such as a UT. Though an analog voltage, such as a differential voltage, may be input to comparators111through118, outputs of comparators111through118are digital decisions, such as a logic 1 for a positive comparison result and a logic 0 for a negative comparison result for example. comparators111through118are part of an unrolling of a first correction TAP for providing odd data (“d1”), even data (“d0”), odd data crossing (“x1”), and even data crossing (“x0”) values of a quadrature output, as described below in additional detail. To obtain a full-rate binary bitstream from two half-rate bitstreams, d0s and d1s may be interleaved, and x0s and x1s may be interleaved.

ODD/EVEN decision feedback equalizer100may be clocked for in phase opposition operation, though clock signals are not illustratively depicted for purposes of clarity and not limitation, and output even and odd data and crossing samples may be in quadrature. Moreover, a value of a UT may vary from operation to operation depending on size of swing of Vsw, as +UTs and −UTs are generally for determining where in amplitude of a differential voltage is. A UT may be the first correction TAP, and such a UT may be added by unrolling in order to meet high speed timing constraints. The value of a UT changes with an adaptation algorithm, but the value of a UT is not data dependent when operating in a steady state. Along those lines, voltage swing may generally be constant after adaptation is completed, namely generally once steady state operation is in effect.

Before a detailed description of unrolling circuitry ofFIG. 5is provided, a more detailed description of DFE summer200is provided for purposes of clarity.

FIG. 6is a schematic diagram depicting an exemplary amplifier210for a continuous bi-modal operation DFE summer200. DFE summer200is further described with simultaneous reference toFIGS. 4 through 6.

DFE summer200is coupled between a supply node41and a ground node42. Input data31is an analog differential input, namely summer input, and input data is differentially provided to gates of two pairs of transistors.

In this example, NMOS and PMOS transistors are illustratively depicted; however, in another implementation NMOS and PMOS transistors may be reversed along with a reversal of supply and ground nodes. Along those lines, an input common-mode voltage is high, namely the higher of a supply voltage divided by two. However, if a common-mode voltage input was low, then a reversed polarity implementation may be used as indicated above.

By bi-modal operation, it is generally meant that during operation a portion of DFE summer200is in an integrating mode or phase and another portion of DFE summer is in a reset mode or phase. By continuous bi-modal operation, it is generally meant that DFE summer operates by interleaving odd and even operations without having to pause between such operations.

DFE summer200includes an odd DFE summer101and an even DFE summer102. Along those lines, amplifier210is a single stage amplifier, with an “odd” amplifier211and an “even” amplifier212having a common current source circuit. For a continuous bi-modal operation, odd amplifier211is in a reset phase while even amplifier212is in an integrating phase, and odd amplifier211is in an integrating phase while even amplifier212is in a reset phase.

Odd amplifier211may be clocked with a clock signal54, and even amplifier212may be clocked with a clock signal254which is the inverse of clock signal54. In other words, clock signal254is the complement (“clkb”) of clock signal54(“clk”). Clock signals54and254may be sourced from a same clock signal by bifurcation of such same clock signal, namely: one clock signal source is provided to an inverting clock buffering path for producing clock signal254, and another clock signal source is provided to a non-inverting clock buffering path for producing clock signal54. Accordingly, clock signals54and254may be the same clock signal though 180 degrees out-of-phase with respect to one another.

Odd DFE summer101may include odd amplifier211and a bias current circuit when operating in an integrating mode for such odd stage, and even DFE summer102may include even amplifier212and a same bias current circuit when operating in an integrating mode for such even stage. In other words, DFE summers101and102may be operationally defined, as described below in additional detail.

A positive input voltage side (“Vinp”)44-1of differential voltage input data, such as input data31, is provided to gates of transistors43-1and243-1, respectively of amplifiers211and212. A negative input voltage side (“Vinn”)44-2of such differential voltage input data, such as input data31, is provided to gates of transistors43-2and243-2, respectively of amplifiers211and212. Along those lines, transistors43-1and243-1may be commonly gated for receiving Vinp44-1, and transistors43-2and243-2may be commonly gated for receiving Vinn44-2.

Source nodes of NMOS transistors43-1and43-2and a drain node of NMOS transistor205all of odd amplifier211may be commonly connected at “odd” bias node46to periodically receive a bias current from current source45. A gate of transistor205may be coupled to receive clock signal54, and a source node of transistor205may be commonly connected to a source node of NMOS transistor206of even amplifier212at a current source node204.

Source nodes of NMOS transistors243-1and243-2and a drain node of NMOS transistor206all of even amplifier212may be commonly connected at “even” bias node246to periodically receive a bias current from current source45. A gate of transistor206may be coupled to receive clock signal254.

Bias current from current source45may be coupled between ground node42and current source node204. In this example, current source45is a fixed current source. However, in another implementation, current source45may be an adjustable current source.

Because transistors205and206are respectively clocked with out-of-phase clock signals54and254, transistor205is in a substantially conductive state (“ON”) when transistor206is in a substantially non-conductive state (“OFF”), and vice versa. Likewise, because transistors57and257are respectively clocked with out-of-phase clock signals54and254, transistors54are ON when transistors257are OFF, and vice versa.

When bias current source45is electrically decoupled from source node246of even amplifier212by transistor206, bias current source45is electrically coupled to source node46of odd amplifier211by transistor205. Along those lines, odd amplifier211is in an integrating phase of operation when supplied with bias current from bias current source45, and even amplifier212is in a reset phase of operation when deprived of bias current from bias current source45.

Conversely, when bias current source45is electrically coupled to source node246of even amplifier212by transistor206, bias current source45is electrically decoupled from source node46of odd amplifier211by transistor205. Along those lines, odd amplifier211is in a reset phase of operation when not supplied with bias current from bias current source45, and even amplifier212is in an integrating phase of operation when supplied with bias current from bias current source45.

For odd amplifier211, drain nodes48-1and48-2respectively of transistors43-1and43-2are respectively coupled to drain nodes of PMOS resistors57-1and57-2. Drain nodes48-1and48-2may be for an odd amplifier211differential output49of positive side output voltage (“Vopodd”) and an odd stage negative side output voltage (“Vonodd”), as respectively associated with conductive lines or nodes51-1and51-2.

Source nodes of a clocked reset switch or circuit61formed of PMOS transistors57-1and57-2may be commonly coupled at supply node41. A differential output49from odd amplifier211of amplifier210may be sourced from drain nodes48-1and48-2, or more generally DFE summer200odd amplifier211output nodes48-1and48-2.

For even amplifier212, drain nodes248-1and248-2respectively of transistors243-1and243-2are respectively coupled to drain nodes of PMOS resistors257-1and257-2. Drain nodes248-1and248-2may be for an even amplifier212differential output249of positive side output voltage (“Vopeven”) and negative side output voltage (“Voneven”), as respectively associated with positive side and negative side conductive lines or nodes251-1and251-2.

Source nodes of a clocked reset switch or circuit61formed of PMOS transistors257-1and257-2may be commonly coupled at supply node41. A differential output249from even amplifier212of amplifier210may be sourced from drain nodes248-1and248-2, or more generally DFE summer200even amplifier212output nodes248-1and248-2.

An odd-even integrating DFE summer200may be more power efficient than a continuous time DFE summer, for reasons as previously described. An odd-even integrating DFE summer200separately integrates an odd interval of a differential input and an even interval of such differential input with each integration performed within 1UI. As only either an odd interval output or an even interval output may be used at a time, odd and even intervals of a data input31may be segregated; however, a common bias current circuit may be used to reduce power consumption by switching such bias current to between odd and even paths.

FIG. 7is a schematic diagram depicting another exemplary amplifier210for a continuous bi-modal operation DFE summer200. Amplifier210is the same inFIGS. 6 and 7, except that current source45ofFIG. 6is replaced with a current mirror circuit (“current mirror”)207inFIG. 7for a current source circuit in common for odd and even amplifiers211and212of amplifier210. Accordingly, some previously described details regarding DFE summer200are not repeated for purposes of clarity and not limitation.

Current mirror207includes NMOS transistors202and203in this example implementation. A bias voltage201may be provided to gates of transistors202and203, which may be commonly coupled to receive such bias voltage201. Source nodes of transistors202and203may be coupled to ground node42. A drain node of transistor202may be coupled to receive bias voltage201, and a drain node of transistor203may be coupled to current source node204.

FIG. 8is a flow diagram depicting an exemplary DFE summer operational flow800for DFE, such as for DFE summers200ofFIGS. 6 and 7. Accordingly, DFE summer operational flow800is further described with simultaneous reference toFIGS. 4, 5, 6 and 7

At801, an input differential signal, such as data input31, may be obtained by a first integrating summer, such as odd DFE summer101, and a second integrating summer, such as even DFE summer102, having a bias current circuit, such as bias current source45or current mirror207, in common. Even though both DFE summers101and102may simultaneously receive a same input differential signal, only one of such two DFE summers is in an integrating phase at a time, and the other of such two DFE summers is in a resetting phase during an integrating phase of the other DFE summer.

At802, first integrating may be performed with odd DFE summer101during a first clock phase of a first clock signal, such as a high voltage interval of clock signal54, for transconductance of data input31to a first output differential signal, such as a Vop-Von odd differential signal49at output nodes48of odd DFE summer101. Even though the above description is in terms of positive logic, in another implementation negative logic may be used.

At803, first resetting may be performed with even DFE summer102during such first clock phase of clock signal54for driving residual voltages of a second output differential signal, such as Vop-Von even differential signal249at output nodes248of even DFE summer102, to the same voltage level, such as a voltage level of supply node41. Thus, after resetting differential signal249is not differential, namely there is no operational difference between voltages at output nodes248. Moreover, first integrating at802and first resetting at803are performed at the same time.

Though such operations may be described with reference to a same phase of clock signal54, operationally first integrating and first resetting are respectively performed with reference to a phase of clock signal54and a corresponding phase of clock signal254. Because clock signals54and254are at least approximately 180 degrees out-of-phase with respect to one another, integrating and resetting by an odd DFE summer101may be described with respective reference to high and low voltage phases of clock signal54. Likewise, integrating and resetting by an even DFE summer102may be described with respective reference to high and low voltage phases of clock signal254.

At804, second integrating may be performed with even integrating summer102during a second clock phase of clock signal54for transconductance of data input31to the second output differential signal. At805, second resetting may be performed with odd integrating summer101during the second clock phase of clock signal54for driving residual voltages of the first output differential signal, such as Vop-Von odd differential signal49at output nodes48of odd DFE summer101, to the same voltage level, such as a voltage level of supply node41. Thus, after resetting differential signal49is not differential, namely there is no operational difference between voltages at output nodes48. Moreover, second integrating at803and second resetting at804are performed at the same time.

In other words, odd-even integrating-resetting takes place at the same time, and an odd-even integrating-resetting interval is immediately followed by even-odd integrating-resetting interval, where even-odd integrating-resetting takes place at the same time. Along those lines, integrating by on odd DFE summer101is interleaved or alternated with integrating with an even DFE summer102, and resetting by an even DFE summer102is interleaved or alternated with resetting by an odd DFE summer101. Thus, a combined data stream of odd and even integration results may be provided by interleaving such odd and even integration results with one another.

For first integrating at802, operations at811and812may be performed at the same time for odd DFE summer101. At811, a bias current from a bias current circuit, such as bias current source45or bias current mirror207, may be electrically coupled to an odd bias node46of a first amplifier, such as odd amplifier211, of odd DFE summer101. During an integrating phase of odd DFE summer101, clock signal54is at a high voltage level, which means PMOS transistors57are OFF and NMOS transistor205is ON. At812, the same voltage level, such as from supply node41, may be electrically decoupled from output nodes48of a first pair of transistors, such as transistors43, of the first amplifier, such as odd amplifier211.

A bias current applied to bias current node46, along with Vinn and Vinp applied to gates of transistors43-2and43-1, respectively, allows for transconductance of such differential input signal to drain nodes48-2and48-1, respectively, through a pair of transistors43for output on nodes48as a differential output voltage49. This differential output49at drain nodes48may integrate or discharge through output capacitance of odd DFE summer101, such as for an analog input to a dynamic comparator. However, for this integration to occur, output nodes48are electrically decoupled from supply node41by turning OFF PMOS transistors57.

For first resetting at803, operations813and814may be performed at the same time for even DFE summer102. At813, bias current from the bias current circuit, such as bias current source45or bias current mirror207, may be electrically decoupled from an even bias node, such as even bias node246, of a second amplifier, such as even amplifier212, of even DFE summer102. During a resetting phase of even DFE summer102, clock signal254is at a low voltage level, namely opposite the state of clock signal54, which means PMOS transistors257are ON, and NMOS transistor206is OFF.

At814, the same voltage level, such as of supply node41, may be electrically coupled to a second pair of transistors, such as transistors243, of the second amplifier, such as even amplifier212. In other words, supply voltage from supply node41may be coupled to drain nodes248-1and248-2respectively of transistors243-1and243-2respectively through channels of PMOS transistors257-1and257-2. As bias current is cut-off from bias node246, a differential input31applied to gates of transistors243is not transconducted to drain nodes248. In other words, with no bias current, no differential output is transconducted from a differential input.

However, some residual charge from a previous differential output may be present on nodes248and/or conductive lines251during an initiation of a reset phase of even DFE summer102. Any appreciable offset due to such residual charge, which may be stored for example in parasitic output capacitance, may be driven out by driving nodes248and conductive lines251to a same voltage level, namely a supply voltage level of supply node41such as an analog Vtt voltage level in this example. Because these nodes248and conductive lines251are at a same voltage level after resetting, there is no residual differential offset between them for operational purposes. By operational purposes, it is generally meant that if there is any offset remaining, such difference is negligible. Moreover, by driving output voltage nodes248and output conductive lines251to same voltage levels, a subsequent integrating operation may take place without any settling time, namely no pause needs to be asserted between consecutive odd and even integration operations.

For second integrating at804, operations at815and816may be performed at the same time for even DFE summer102. At815, a bias current from a bias current circuit, such as bias current source45or bias current mirror207, may be electrically coupled to an even bias node246of a second amplifier, such as even amplifier212, of even DFE summer102. During an integrating phase of even DFE summer102, clock signal254is at a high voltage level, which means PMOS transistors257are OFF and NMOS transistor206is ON. At816, the same voltage level, such as from supply node41, from a second pair of transistors, such as transistors243, of the second amplifier, such as even amplifier212, may be electrically decoupled from output nodes248.

A bias current applied to bias current node246, along with Vinn and Vinp applied to gates of transistors243-2and243-1, respectively, allows for transconductance of such differential input signal to drain nodes248-2and248-1, respectively, through a pair of transistors243for output on nodes248as a differential output voltage249. This differential output249at drain nodes248may integrate or discharge through output capacitance of even DFE summer102, such as for an analog input to a dynamic comparator. However, for this integration to occur, output nodes248are electrically decoupled from supply node41by turning OFF PMOS transistors257.

For second resetting at805, operations817and818may be performed at the same time for odd DFE summer101. At813, bias current from the bias current circuit, such as bias current source45or bias current mirror207, may be electrically decoupled from an odd bias node, such as odd bias node46, of a second amplifier, such as odd amplifier211, of odd DFE summer101. During a resetting phase of odd DFE summer101, clock signal54is logic at a low voltage level, namely opposite the state of clock signal254, which means PMOS transistors57are ON and NMOS transistor205is OFF.

At818, the same voltage level, such as of supply node41, may be electrically coupled to a second pair of transistors, such as transistors43, of the second amplifier, such as odd amplifier211. In other words, supply voltage from supply node41may be coupled to drain nodes48-1and48-2respectively of transistors43-1and43-2respectively through channels of PMOS transistors57-1and57-2. As bias current is cut-off from bias node46, a differential input applied to gates of transistors43is not transconducted to drain nodes48. In other words, with no bias current, no differential output is transconducted from a differential input. However, some residual charge from a previous differential output may be present on nodes48and/or conductive lines51during an initiation of a reset phase of odd DFE summer101.

Any offset effect due to such residual charge, which may be stored for example in parasitic output capacitance, may be driven out by driving nodes48and conductive lines51to a same voltage level, namely a supply voltage level of supply node41such as an analog Vtt voltage level in this example. Because these nodes48and conductive lines51are at a same voltage level after resetting, there is no residual differential offset between them for operational purposes. Moreover, by driving output voltage nodes48and output conductive lines51to same voltage levels, a subsequent integrating operation may take place without any settling time between consecutive integrating operations.

Accordingly, bias current may be steered between two integrating summers, removing or decoupling such bias current from one of such integrating summers during a reset phase to allow for true reset during such reset phase. By having odd-even integrating and resetting operations simultaneously performed interleaved with even-odd resetting and integrating operations simultaneously performed as previously described, DFE summer200may thus have no settling time between odd and even integrating operations. Moreover, DFE summer200may have no residual offset along without any settling time. Such odd and even integrating operations, as well as corresponding even and odd resetting operations, may be performed in alternating sequence one after another without memory effects due to residual charge reaching an operational level. Thus, each integrating operation of DFE summer200may be substantially within a UI for high-frequency operations, as delay is generally limited only by transconductance and propagation delay of differential input to differential output.

To recapitulate with reference toFIG. 7only for purposes of clarity and not limitation, amplifier210is biased by an input current from bias voltage201. As gate and drain nodes of NMOS transistor202are tied to a gate node of NMOS transistor203, and transistors202and203share a same source voltage of ground node42, input current from bias voltage201is mirrored to a drain node of transistor203. Current mirror207thus may provide a biasing current used by amplifier210for operation thereof, as previously described, where transistor203is a tail device operating as a current sink.

Coupled on top of a biasing current sink is a differential pair formed by NMOS transistors205and206. A gate of transistor205is coupled to an input clock signal54, and a gate of transistor206is coupled to an input clock254, namely a complementary version of clock signal54. Having clock signals54and254phase shifted by 180 degrees allows current supplied by a tail device, such as transistor203in this example, to be steered between drains of transistors205and206in each clock cycle, namely to either a drain of transistor205or a drain of transistor206depending on whether clock signal54is high or low. When clock signal54is high, clock signal254is low, and so current from transistor203flows through a channel of transistor205to an odd integrating DFE summer, namely odd amplifier211. When clock signal254is high, clock signal54is low, and so current from transistor203flows through a channel of transistor206to an even integrating DFE summer, namely even stage212.

These even and odd integrating DFE summers, namely even and odd stages212and211, have the same structure, and their operations are interleaved in time. Accordingly for purposes of clarity and not limitation, only odd amplifier211description of recapitulated. For odd amplifier211, input signals of a differential input31are respectively applied to gates of transistors43, where transistors43are connected as a differential pair. When clock signal54is high, transistors42steer current from transistor203between output nodes48.

PMOS transistors57are switches electrically coupling output nodes48of odd amplifier211to supply node41when clock signal54is low for a reset phase. This reset phase is to allow any residual voltage on output nodes48to be discharged, where such residual voltage may be from a differential current from transistors43differential pair when clock signal54was high. As a current in drain of transistor43-1may be different than a current in a drain of transistor43-2, voltages Vop_odd and Von_odd may be differential voltage which is integrated in odd amplifier211during an integrating phase when clock signal54is high.

Returning toFIG. 5with continued reference toFIGS. 6 and 7, output nodes48-1and48-2for an odd stage differential output respectively coupled to a positive side conductive line51-1and a negative side conductive line51-2may be for providing an odd DFE summer101output for an odd path signal, namely via conductive lines51, for subsequent sampling. Likewise, output nodes248-1and248-2for an even stage differential output respectively coupled to a positive side conductive line251-1and a negative side conductive line251-2may be for providing an even DFE summer102output for an even path signal, namely via conductive lines251, for subsequent sampling. An odd path differential output may be provided via conductive lines51to each of comparators115through118for sampling, and an even path differential output may be provided via conductive lines251to each of comparators111through114.

A positive UT may be compared against a sampled differential voltage output by comparators111,113,115, and117, and a negative UT may be compared by a sampled differential voltage output by comparators112,114,116, and118. Accordingly, such comparators111through118may be set with a UT value, namely a first correction TAP value. Alternatively, comparators111through118may be thought of as data slicers. Along those lines, differential voltages output by DFE summers101and102may be non-return-to-zero (“NRZ”) voltages or other differential signaling.

Comparators111and112may be for a clock 0 degree sampling point; comparators113and114may be for a clock 90 degree sampling point; comparators115and116may be for a clock 270 degree sampling point; and comparators117and118may be for a clock 180 degree sampling point. Outputs of comparators111through118may be single-ended digital values, namely either a logic 1 or 0 voltage level, such as Vcc and ground for example.

Outputs of comparators111and112may be data inputs to multiplexer121, and outputs of comparators113and114may be data inputs to multiplexer122. Outputs of comparators115and116may be data inputs to multiplexer123, and outputs of comparators117and118may be data inputs to multiplexer124.

A control select signal input to multiplexer121may be output of register or latch (“L”)135triggered responsive to a clock 0 degree sampling point. A control select signal input to multiplexer122may be output of register or latch (“L”)125triggered responsive to a clock 90 degree sampling point, where input to latch125is sourced from output of latch135.

A control select signal input to multiplexer124may be output of register or latch (“L”)132triggered responsive to a clock 180 degree sampling point. A control select signal input to multiplexer123may be output of register or latch (“L”)126triggered responsive to a clock 270 degree sampling point, where input to latch126is sourced from output of latch132.

Output of multiplexer121may be provided as an odd path143h2 coefficient or weight for DFE feedback, as well as being a data input to latch132and a rising edge triggered register or latch (“EL”)131triggered responsive to a clock 180 degree sampling point. Output of multiplexer122may be provided as a data input to latch133, which latch133may be triggered responsive to a clock 270 degree sampling point.

Output of multiplexer124may be provided as an even path144h2 coefficient or weight for DFE feedback, as well as being a data input to latch135and a falling edge triggered register or latch (“EL”)136triggered responsive to a clock 0 degree sampling point. Output of multiplexer123may be provided as a data input to latch134, which latch134may be triggered responsive to a clock 90 degree sampling point.

Output of latch131may be provided as an even path144h3 coefficient or weight for DFE feedback, as well as being a data input to latch141, which latch141may be triggered responsive to a clock 0 degree sampling point. Output of latch141may be provided as an odd path143h4 coefficient or weight for DFE feedback, as well as being a data input to latch151, which latch151may be triggered responsive to a clock 180 degree sampling point. Output of latch151may be provided as an even path144h5 coefficient or weight for DFE feedback.

Output of latch136may be provided as an odd path143h3 coefficient or weight for DFE feedback, as well as being a data input to latch142, which latch142may be triggered responsive to a clock 0 degree sampling point. Output of latch142may be provided as an even path144h4 coefficient or weight for DFE feedback, as well as being a data input to latch152, which latch152may be triggered responsive to a clock 180 degree sampling point. Output of latch152may be provided as an odd path143h5 coefficient or weight for DFE feedback.

Odd path143h2 through h5 coefficients may be bussed on bus171to comparators111through114for adjustment of a UT magnitude in accordance with DFE. Likewise, even path144h2 through h5 coefficients may be bussed on bus172to comparators115through118for adjustment of a UT magnitude in accordance with DFE.

Timing paths for such unrolling may be limiting. For example, a feedback path161from comparator111for an odd path143h2 coefficient back to comparator111may be limited to less than 2 UIs. A feedback path162from latch131to comparator112may be limited to less than 2 UIs. A feedback path163from latch131for an even path144h3 coefficient back to comparator117may be limited to less than 3 UIs. A feedback path164from latch132for loading latch135with an even path144h2 coefficient may be limited to less than 1UI.

FIG. 9is a signal diagram depicting exemplary waveforms900for signals of DFE summers200ofFIGS. 6 and 7. Differential data input31, ΔVi, includes differential data d0 through d11 for purposes of example; however, fewer or more differential data may be used. Along those lines, differential output is sampled at instants t0 through t11 for obtaining digital data from differential data d0 through d11, respectively. Sampling times or instants t0 through t11 coincide with integrating DFE summer200differential output peaks907, as generally indicated with vertical dashed lines906. Output peaks907may be for a full differential swing voltage, Vsw, to a high side thereof, and likewise valleys917may be for a full differential swing voltage, Vsw, to a low side thereof.

For clock signal54transitioning from low to high generally at911, PMOS transistors57are transitioning from ON to OFF, and NMOS transistor205is transitioning from OFF to ON. Accordingly, bias current is steered to NMOS transistors43for passing through such differential pair for transconducting data d1 of data input31to drain nodes48-1and48-2. This causes voltages Vop_odd901and Von_odd902to be drawn down from a supply voltage level within a time interval or bit period910generally associated with clock signal54being at a logic high level. In this integrating phase, current passing through transistors may come from output capacitance associated with output nodes48discharging with different currents on positive and negative sides. This discharge generally linearly causes voltages Vop_odd901and Von_odd902to decrease, generally respectively at913and914, during time interval910. Time interval910may be a half-period of clock signal54, namely 1UI.

After time interval910, clock signal54transitions from high to low generally at921in a next UI, namely time interval920. Accordingly, NMOS transistor205is transitioned from ON to OFF for electrically decoupling bias current from transistors43, and PMOS transistors57are transitioned from OFF to ON for coupling output nodes48to a supply voltage of supply node41. Thus, voltages Vop_odd901and Von_odd902respectively at output nodes48-1and48-2are generally linearly pulled up, generally at915and916respectively, to and maintained at such supply voltage level during time interval920.

Along the above lines, voltages Vop_odd901and Von_odd902may be combined to provide an odd differential voltage output, ΔVo_odd,49, having peaks907for during an odd integrating phase and valleys917during an odd reset phase. This cycle may repeat for other odd data values, such as d3, d5, d7, etc.

As clock signal254, voltages Vop_even903and Von_even904, and ΔVo_even249have the same operation though on alternating phases of clock signal54, namely high and low states of clock signal254, operation associated with such signals follows from the above description and is not provided in unnecessary detail for purposes of clarity and not limitation. Moreover, even though each instance of Vop_odd901drops lower than each instance of Von_odd902in this example, Von_odd902may drop lower than Vop_odd901as will vary with data of data input31. Likewise, even though each instance of Vop_even903drops lower than each instance of Von_even904in this example, Von_even904may drop lower than Vop_even903as will vary with data of data input31. The example of all differential data effectively being a logic 1 for data input31, though in NRZ for +Vhigh and −Vlow levels, is for purposes of clarity and not limitation.

Odd differential voltage output49and even differential voltage output249may be combined or interleaved to provide a full-rate differential output voltage, ΔVo,905from such half-rate differential voltage outputs. Full-rate differential output voltage905is for a full bitstream of NRZ differential data input31, where differential voltage outputs49and249are for separate interleavable halves of such full bitstream.

Such differential output voltage905does not have a settling period between peaks907thereof, and each peak907may be resolved within 1UI. Accordingly, voltage dependent problem previously described is resolved by removing a bias current from a differential gm-pair (i.e., pair of transistors) during a reset phase. Without differential current, no differential voltage is generated at differential output nodes, and output voltages may be truly reset to aVtt. More specifically, a biasing current is steered from an even DFE summer to an odd DFE summer during an even DFE summer reset phase and odd DFE summer integrating phase, and then this steering of biasing current is reversed in a next bit period where the same current source circuit is used for both even and odd paths. Along those lines, power consumption for a conventional separate odd and even continuous time DFE summers is approximately a multiple of 6 times larger than power consumption for integrating-resetting DFE summer200.

FIG. 10is a schematic diagram depicting another exemplary integrating DFE summer200.FIG. 10is further described with simultaneous reference toFIGS. 4 through 7.

Rather than unrolling a first correction TAP, such as inFIG. 5, one or more correction TAPs for forming a chain of correction TAPs232may be used. However, rather than current steering circuits50forming a chain of correction TAPs, each with a single pair of transconductance transistors43as inFIG. 4, chain of correction TAPs232may be formed of one or more integrating bi-modal current steering circuits250coupled to amplifier210and coupled to a delay chain (not shown in thisFIG. 10for purposes of clarity and not limitation) for feedback input, such feedback was previously described.

Along those lines, an amplifier210, such as previously described, may have an odd amplifier211for providing an odd differential output voltage49and an even amplifier212for providing an even differential output voltage249. Each bi-modal current steering circuit250may include an odd amplifier261, an even amplifier262, and an adjustable current source55in common to such odd and even amplifiers261and262.

Odd amplifier261and even amplifier262may have the same structure as odd amplifier211and even amplifier212, respectively, except PMOS transistors57and257of amplifier210may be common or shared among one or more current steering circuits250for odd and even resetting phases thereof. For a continuous bi-modal operation, odd amplifier261is in a reset phase while even amplifier262is in an integrating phase, and odd amplifier261is in an integrating phase while even amplifier262is in a reset phase. Again, in this example, NMOS and PMOS transistors are illustratively depicted; however, in another implementation NMOS and PMOS transistors may be reversed along with a reversal of supply and ground nodes. Parasitic capacitances are not illustratively depicted in this figure, but follow from the above description of parasitic capacitances for DFE summer60ofFIG. 4.

Odd amplifier261may be clocked with a clock signal54, and even amplifier262may be clocked with a clock signal254which is the inverse of clock signal54. In other words, clock signal254is the complement (“clkb”) of clock signal54(“clk”), as previously described.

For an HNcorrection TAP, for example an H2correction TAP, an odd and an even positive voltage side of differential voltage output data fed back, such as H2p_odd and H2p_even, may be respectively provided to gates of transistors53-1and253-1respectively of amplifiers261and262; and an odd and an even negative voltage side of such differential voltage output data fed back, such as H2n_odd and H2n_even, may be respectively provided to gates of transistors53-2and253-2respectively of amplifiers261and262. Thus, a differential feedback may include an H2p_odd and an H2n_odd differential voltage during an odd interval of such feedback and an H2p_even and an H2n_even differential voltage during an even interval of such feedback.

Source nodes of NMOS transistors53-1and53-2and a drain node of NMOS transistor285all of odd amplifier261may be commonly connected at “odd” bias node265to periodically receive an adjustable bias current from adjustable current source55. A gate of transistor285may be coupled to receive clock signal54, and a source node of transistor285may be commonly connected to a source node of NMOS transistor286of even amplifier262at a current source node267.

Source nodes of NMOS transistors253-1and253-2and a drain node of NMOS transistor286all of even amplifier262may be commonly connected at “even” bias node266to periodically receive a bias current from adjustable current source55. A gate of transistor286may be coupled to receive clock signal254.

A bias current from adjustable bias current source55may be coupled between ground node42and current source node267. Because transistors285and286are respectively clocked with complementary out-of-phase clock signals54and254, transistor285is in a substantially conductive state (“ON”) when transistor286is in a substantially non-conductive state (“OFF”), and vice versa. Likewise, as previously described, because transistors57and257are respectively clocked with complementary out-of-phase clock signals54and254, transistors54are ON when transistors257are OFF, and vice versa.

When adjustable bias current source55is electrically decoupled from source node or bias node266of even amplifier262by transistor286, adjustable bias current source55is electrically coupled to source node or bias node265of odd amplifier261by transistor285. Along those lines, odd amplifier261is in an integrating phase of operation when supplied with bias current from adjustable bias current source55, and even amplifier262is in a reset phase of operation when deprived of bias current from adjustable bias current source55.

Conversely, when bias adjustable current source55is electrically coupled to source node266of even amplifier262by transistor286, bias adjustable current source55is electrically decoupled from source node265of odd amplifier261by transistor285. Along those lines, odd amplifier261is in a reset phase of operation when not supplied with bias current from bias adjustable current source55, and even amplifier262is in an integrating phase of operation when supplied with bias current from bias adjustable current source55.

For odd amplifier261, drain nodes of transistors53-1and53-2, which may be respectively common with drain nodes48-1and48-2of transistors43-1and43-2, are respectively coupled to drain nodes of PMOS resistors57-1and57-2. Drain nodes of transistors53-1and53-2for an odd amplifier261may be coupled to differential output49on a positive side output voltage (“Vopodd”) and an odd stage negative side output voltage (“Vonodd”), respectively, as respectively associated with conductive lines or nodes51-1and51-2. A differential output from odd amplifier261may be applied to drain nodes48-1and48-2.

For even amplifier262, drain nodes of transistors253-1and253-2, which may be respectively common with drain nodes248-1and248-2of transistors253-1and253-2, are respectively coupled to drain nodes of PMOS resistors257-1and257-2. Drain nodes of transistors253-1and253-2for even amplifier262may be coupled to a differential output249of positive side output voltage (“Vopeven”) and negative side output voltage (“Voneven”), respectively, as respectively associated with positive side and negative side conductive lines or nodes251-1and251-2. A differential output from even amplifier262may be applied to drain nodes248-1and248-2.

An odd-even integrating DFE summer200may be more power efficient than a continuous time DFE summer by steering bias current to odd amplifier261and odd amplifier211in one bit period and then steering bias current to even amplifier262and even amplifier212in a next bit period for reasons as previously described. An odd-even integrating DFE summer200separately integrates an odd interval of a differential input and an even interval of such differential input with each integration performed within 1UI.

As only either an odd interval output or an even interval output may be used at a time, odd and even intervals of a data input31may be segregated; however, a common bias current circuit and one or more common adjustable bias current sources44may be used to reduce power consumption by switching such bias currents back and forth between odd and even paths. Other details for interleaved operation of integrating and resetting of odd amplifier261and even amplifier262follow from the above description of operation of odd amplifier211and even amplifier212, respectively, and thus are not repeated for purposes of clarity and not limitation.

Because one or more of the examples described herein may be implemented in an FPGA, a detailed description of such an IC is provided. However, it should be understood that other types of ICs may benefit from the technology described herein.

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.

As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG. 11illustrates an FPGA architecture1100that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)1101, configurable logic blocks (“CLBs”)1102, random access memory blocks (“BRAMs”)1103, input/output blocks (“IOBs”)1104, configuration and clocking logic (“CONFIG/CLOCKS”)1105, digital signal processing blocks (“DSPs”)1106, specialized input/output blocks (“I/O”)1107(e.g., configuration ports and clock ports), and other programmable logic1108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)1110.

For example, a CLB1102can include a configurable logic element (“CLE”)1112that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)1111. A BRAM1103can include a BRAM logic element (“BRL”)1113in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile1106can include a DSP logic element (“DSPL”)1114in addition to an appropriate number of programmable interconnect elements. An IOB1104can include, for example, two instances of an input/output logic element (“IOL”)1115in addition to one instance of the programmable interconnect element1111. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element1115typically are not confined to the area of the input/output logic element1115.

In the pictured embodiment, a horizontal area near the center of the die (shown inFIG. 11) is used for configuration, clock, and other control logic. Vertical columns1109extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 11include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block1110spans several columns of CLBs and BRAMs.

While the foregoing describes exemplary apparatus(es) and/or method(s), other and further examples in accordance with the one or more aspects described herein may be devised without departing from the scope hereof, which is determined by the claims that follow and equivalents thereof. For example, even though the above-description was in terms of half-rate DFE for purposes of clarity, more than two phases may be used in accordance with the above-description. Along those lines, a one third-rate, a one quarter-rate, or other fractional-rate operation may be used for current steering as described herein. Thus, speed of operation may be increased, along with a reduction in power consumption, for time-interleaved amplifiers and/or time-interleaved comparators, which may include analog-to-digital converters and/or digital-to-analog converters. Moreover, high-speed track and hold circuits may be biased with current steering as described herein.

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