Stacked Layer Memory Suitable for SRAM and Having a Long Cell.

A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

BACKGROUND

This invention generally relates to semiconductors and, more specifically, relates to semiconductor devices with memory having different types of transistors such as SRAM (static random-access memory) cells.

Static random-access memory (SRAM) may be used, for example, to temporarily store data in a computer system. An SRAM device includes an array of bitcells in which each bitcell retains a single bit of data during operation and is able to be programmed with a value for the single bit. Each SRAM bitcell may have a 6-transistor (6T) design that includes a pair of cross-coupled inverters and a pair of access transistors connecting the inverters to complementary bit lines. The two access transistors are controlled by word lines, which are used to select the SRAM memory cell for read or write operations. When continuously powered, the memory state of an SRAM persists without the need for data refresh operations.

The transistors in the SRAM cells may be formed from different semiconductor structures. A fin-type field-effect transistor (FinFET) is a non-planar device structure for a field-effect transistor that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET includes a fin, heavily-doped source/drain regions, and a gate electrode that wraps around the fin. During operation, a channel for carrier flow is formed in the fin between the source/drain regions. In comparison with planar field-effect transistors, the arrangement between the gate structure and fin improves control over the channel and reduces the leakage current when the FinFET is in its “Off” state. This, in turn, lowers threshold voltages in comparison with planar field-effect transistors, and results in improved performance and lowered power consumption.

Nanosheet field-effect transistors have been developed as an advanced type of FinFET that may permit additional increases in packing density in an integrated circuit. The body of a nanosheet field-effect transistor includes multiple nanosheet channel layers vertically stacked in a three-dimensional array. Sections of a gate stack may surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. The nanosheet channel layers are initially arranged in a layer stack with sacrificial layers composed of a material (e.g., silicon-germanium) that can be etched selectively to the material (e.g., silicon) constituting the nanosheet channel layers. The sacrificial layers are etched and removed in order to release the nanosheet channel layers, and to provide spaces for the formation of the gate stack.

A nanosheet field-effect transistor may be used as a base structure to form a complementary field-effect transistor. The source/drain regions of a nanosheet field-effect transistor may be epitaxially grown from the side surfaces of the nanosheet channel layers in spaces between adjacent layer stacks in an array of layer stacks. In a complementary field-effect transistor, epitaxial semiconductor layers of different conductivity type are grown with a stacked arrangement to provide source/drain regions for forming n-type and p-type field-effect transistors connected with each layer stack of nanosheet channel layers.

Improved structures and SRAM bitcells including complementary field effect transistors and methods of forming such structures and bitcells could be used.

SUMMARY

This section is meant to be exemplary and not meant to be limiting.

In an exemplary embodiment, a stacked layer memory for a static random-access memory is described, which comprises a first layer of the static random-access memory, wherein the first layer comprises a plurality of transistors of a first type. The stacked layer memory further comprises a second layer of the static random-access memory. The second layer comprises a plurality of transistors of a second type, and the first and second layers are different layers stacked vertically. A width of individual static random-access memory cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type.

In another exemplary embodiment, a method is disclosed for forming a stacked layer memory for a static random-access memory. The method includes forming a first layer of the static random-access memory, wherein the first layer comprises a plurality of transistors of a first type. The method also includes forming a second layer of the static random-access memory. The second layer comprises a plurality of transistors of a second type, and the first and second layers are different layers and are formed to be stacked vertically. A width of individual static random-access memory cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type.

DETAILED DESCRIPTION

Abbreviations that may be found in the specification and/or the drawing figures are defined below, at the end of the detailed description section.

FIG.1is a circuit diagram of an SRAM cell1, which is a six-transistor (6T) cell. The six transistors are as follows: T1, an access (or pass gate, PG) transistor PG130-1; T2, an access transistor PG230-2; T3, a pullup (PU) transistor PU140-1; T4, a pulldown (PD) transistor PD150-1; T5, a PD transistor PD250-2; and T6, a PU transistor PU240-2. S/Ds of the transistors PU140-1and PU240-2are connected to power (VDD) line70, the other S/D of transistor PU140-1is connected to Q60-1, and the other S/D of transistor PU240-2is connected to Qn60-2. The point Q60-1is connected to gates of transistors PU240-2and PD250-2, and to a S/D of transistors PD150-1, PG130-1, and PU140-1. The point Qn60-2is connected to gates of transistors PU140-1and PD150-1, and to a S/D of transistors PD250-2, PG230-2, and PU240-2. The other S/Ds of PD transistors50-1and50-2are connected to ground VSS line80. The transistor PG130-1has S/Ds coupled to Q60-1and a bit line (BL)20-1. The transistor PG230-2has S/Ds coupled to Qn60-2and a bit line (BL)20-2. Reference11-1indicates a cross-couple connection from point Q60-1to the gates for both transistors PU240-2and PD250-2, and reference11-2indicates a cross-couple connection from Qn60-2to the gates for both transistors PU140-1and PD150-1.

The PU transistors PU140-1and PU240-2are PFETs, while the PD transistors PD150-1and PD250-2are pulldown transistors and are NFETs, as are PG130-1and PG230-2. The transistors PU140-1and PD150-1form a complementary FET90-1, while the transistors PU140-2and PD150-2form a complementary FET90-2.

As used herein, the term “source/drain region”, “S/D region”, or just “S/D” means a doped region of semiconductor material that can function as either a source or a drain of a transistor (either nanosheet FET or FinFET).

Referring toFIG.2, this figure is a top view of a semiconductor implementation of the SRAM cell inFIG.1. This shows possible layout at a particular phase of processing of the semiconductor100and shows multiple layers that overlap each other. The cell101has a layout as indicated, where locations of each of the six transistors30-1,30-2,40-1,40-2,50-1, and50-2are indicated, as are the word line WL10, the two points Q60-1and Qn60-2, and the bit line BL and its inverse bit line, BLB. It is noted that BLB is equivalent to BL. Reference110illustrates gate regions, which formed are at the lowest level of the semiconductor100, relative to the levels at which references120and130are formed. Reference120indicates S/D regions, and is formed at a level above the level at which the gate regions110are formed. Reference130indicates conductive material areas used to support the word lines10, bit lines20, cross-couple connections11, ground (GND) VSS line80, and power (VDD) line70, and is at the highest level (a top level, e.g., of wiring) of the semiconductor100in this particular view.

FIG.3is a diagrammatic top view illustrating a conductive (e.g., routing) layer that is positioned on top the view shown inFIG.2. Locations for structure of the transistors30-1,30-2,40-1,40-2,50-1, and50-2are marked. Gate regions110, S/D regions120, contacts140, and metal150are shown. The cross-couple connections11-1and11-2are shown, too. The multiple lines between elements indicate a number of FinFets: e.g., the four lines from BL20-1to Q60-1are indicating (2) FinFETs, and the six lines between the ground (GND) VSS line80and Q60-1are indicating (3) FinFETs. For nanosheets, this would be the same number of lines (single wide NS), the but the width can be different between BL or GND connection if desired. An example width in a horizontal direction of 170 nm and a height in a vertical direction of 158 nm are shown inFIG.3.

This structure, however, can be improved. The examples here provide improvements and stacked nanosheet SRAMs (which are optional for FINFET too). These include NFET on one layer and PFET on a separate layer. Further, the SRAM cell width is defined by a single FET pitch, which is based on a device's active region and isolation width of the device.

Additionally, the following are other examples:1) An SRAM cell can be intermixed with logic cells in a standard circuit row without an interface gap;2) A bit line length may be equal to a FET pitch multiplied by the number of cells;3) NFET may be formed on a bottom layer and PFET formed on a top layer;4) NFET and PFET device edges can be offset in a relative position;5) NFET and PFET device widths can be different;6) SRAM cross-couple connections may be on a top layer;7) A bit line may run perpendicular to the patterned portions (e.g., the channel regions) of the nanosheet;8) Self aligned gate-to-gate connections and corresponding processes may be used;9) BL/BLB/GND connections may be made to the backside of the wafer; and/or10) A VDD connection may be made to the frontside of the wafer.

Benefits and advantages include one or more of the following:1) There is a very uniform and low complexity on the NFET layer, which may allow for improved density, e.g., by reducing device side-to-side pitch;2) BL length (e.g., capacitance) may be reduced by −40-50 percent; e.g., due to the cell width being a single FET pitch;3) Memory cells can be integrated with logic cells, due to a single FET width cell (e.g., a memory array may be embedded);4) Cross-couple connections11may be formed at a top level in an early wiring stage such as being made at PFET level with standard line and via at a relaxed wiring pitch; and/or5) BL/BLB/GND connections may be made from the backside, which allows very good FET access and low-resistance wiring and connections.

Referring toFIG.4, which is spread overFIGS.4-1and4-2, this figure illustrates a schematic top view of a stacked long cell nanosheet SRAM for two cells401-1and401-2. Reference405on the right side indicates a lower layer (an NFET layer, e.g., a bottom layer) of the part of the semiconductor wafer that forms the stacked long cell nanosheet SRAM, while reference480on the left side indicates an upper layer (a PFET layer, e.g., a top layer) above the NFET layer. Reference495shows a line where a cross-section is shown inFIGS.6and7. While most of the description herein assumes the PFET layer480is an upper layer relative to the lower NFET layer405, this could also be reversed, and the PFET layer480could be a lower layer.

The NFET layer405has the NFETs: pass gate transistors PG130-1and PG230-2; and pull down transistors PD150-1and PD50-2. A semiconductor wafer402is illustrated, and the layers shown are formed on top of or partly within that wafer. Reference411indicates the orientation of the patterned portions of the nanosheet, in particular the channel regions. The BL20-1and BLB20-2in this example run perpendicular to reference411and therefore perpendicular to the patterned portions of the nanosheet.

The BL20-1, ground (GND) VSS line80and BLB20-2can be at the lowest layer405, and in fact be connected to backside connections, as indicated by reference485, although this is not a requirement. References410indicate vias from the upper layer480. References110indicate gate regions, and references120indicate S/D regions. Reference486indicates a connection to power (VDD) line70may be made to the frontside of the wafer.

For ease of exposition, this will be described in reference toFIG.1also. InFIG.1, there is a path from the BL20-1, through the pass gate transistor PG130-1, through point Q60-1, and through pull down transistor PD150-1to ground (GND) VSS line80. For each cell401-1and401-2inFIG.4and in the lower layer405, there is a path from BL20-1, through S/D region120, to the gate region110of PG130-1(where part of the gate region110and the S/D region120is underneath reference420), through another S/D region120, past Q60-1(and its corresponding conductive material area130), to another S/D region120, through gate region110of the PD150-1, through another S/D region120, and to ground (GND) VSS line80.

InFIG.1, there is a path from the BL20-2, through the pass gate transistor PG230-1, through point Qn60-2, and through pull down transistor PD250-2to ground (GND) VSS line80. For each cell401-1and401-2inFIG.4and in the lower layer405, there is a path from BLB20-2, through S/D region120, to the gate region110of PG230-2(where part of the gate region110and the S/D region120is underneath reference420), through another S/D region120, past Qn60-2(and its corresponding conductive material area130), to another S/D region120, through gate region110of the PD250-2, through another S/D region120, and to ground (GND) VSS line80.

Regions420have conductive material to connect the vias410(and the WLs10and corresponding contact regions440in upper layer480) to corresponding pass gate transistors. These correspond to the WL10being coupled to the gates of PG130-1and PG230-2inFIG.1. For instance, inFIG.4, the regions420connect corresponding vias410to the gate regions110of the PG130-1for cells401-1and401-2. Similarly, the regions420connect corresponding vias410to the gate regions110of the PG230-2for cells401-1and401-2. The word lines10are also shown, extending from edge-to-edge for the cells401.

With respect to upper layer480, references440indicate the contact regions to the vias410to contact the word line10with underlying conductive material area420. In this example, the word lines10and the contact regions440are on the M3(third metal) layer, although this is not limiting. InFIG.1, the VDD (power) line70passes through the pull up transistor PU1to the point Q60-1. InFIG.4, for both cells401-1and401-2, the VDD (power) line70is coupled to the S/D regions120, through the PU140-1, through other S/D regions120and to the point Q60-1(and its conductive material area130). Further, for both cells401-1and401-2, the VDD70is coupled to the S/D regions120, through the PU240-2, through other S/D regions120and to the point Q60-1(and its conductive material area130).

In this example, the lines450,460, and10are on upper (e.g., top) layer480of the wafer402, that is, the upper layer of the wafer402that is used to define cells401. A cross-couple connection11-1is formed on the upper layer480at least by the conductive material areas130for Q60-1being coupled to contact areas470. In this example, the conductive material areas130for Q60-1are coupled to the S/D region120for the PU140-1, and underlie but electrically connect to the contact areas470. The contact areas470are connected through vias410to points Q60-1and their corresponding conductive material areas130on lower layer405. The points Q60-1on the lower layer405are electrically coupled to the S/D regions120of the PG130-1and the PD150-1. The points Q60-1therefore are three-dimensional points existing in both the lower layer405and the upper layer480. The cross-couple connection11-1is also connected to the gate regions of PU240-2and PD250-2(seeFIG.1also), and this is implemented on the upper layer480using the lines450that are electrically coupled to the gate regions110of the PU240-2, which are electrically coupled to the gates of PD250-2(on the lower layer405) using vias430.

Similar construction may be used for points Qn60-2and cross-couple connection11-2. The cross-couple connection11-2is formed on the upper layer480at least by the conductive material areas130for Qn60-2being coupled to contact areas470. In this example, the conductive material areas130for Qn60-2are coupled to the S/D region120for the PU240-2, and underlie but electrically connect to the contact areas470. The contact areas470are connected through vias410to points Qn60-2and their corresponding conductive material areas130on lower layer405. The points Qn60-2on the lower layer405are electrically coupled to the S/D regions120of the PG230-2and the PD250-2. The points Qn60-2therefore are three-dimensional points existing in both the lower layer405and the upper layer480. The cross-couple connection11-2is also connected to the gate regions of PU140-1and PD150-1(seeFIG.1also), and this is implemented on the upper layer480using the lines460that are electrically coupled to the gate regions110of the PU140-1, which are electrically coupled to the gates of PD150-1(on the lower layer405) using vias430.

Concerning the gate regions110of the PU140-1(on the upper layer480) that are electrically coupled to the gates of PD150-1(on the lower layer405) using vias430and corresponding contact regions440, the gate-to-gate connections may be formed using self-aligned gate-to-gate process.

It is further noted that reference461indicates a pitch of a single transistor of an NFET, in this case PG130-1, and this pitch461is equivalent to a width of a device active region (e.g., the gate region110) and an isolation width of the device. Although not marked onFIG.4, there is an isolator (e.g., an insulator or insulators such as SiO2and/or a dielectric such as SiN) between the active regions. This illustrates that a bit line20-1(or BLB20-2) length may be equal to a pitch461of a single transistor multiplied by a total number of cells in a circuit row. This example shows two pitches461in a circuit row462(containing transistors30-1from both cells401-1and401-2) for the two pass gates PG130-1and PG230-2, and the BL20-1length can be equivalent to twice the pitch461.

Reference491indicates a device edge for PU240-2, and reference492indicates a device edge of the PD250-2. The PFET device of PU240-2and the NFET device of PD50-2may be offset in a relative position, as shown onFIG.5. Turning toFIG.5, this figure illustrates an example where the PFET layer480overlaps the NFET layer405and is offset relative to the NFET layer405. The offset between layers is illustrated by reference505. This illustrates a single cell401. This also illustrates why reference is made to a “long cell”, as with both the NFET layer405and the PFET layer480being stacked on each other, and with both layers being laid out in a vertical direction, the length of the cell401along the long axis501is multiple times the length of the cell401along the short axis502.

The NFET layer405has edges in the horizontal axis corresponding to the edges515-1and515-2of the BL20-1and BLB20-2regions. In the vertical axis, edge520-1bisects the BL region20-2, and edge520-2bisects the BLB region20-2. For the PFET layer480, this has edges530-1and530-2corresponding to the VDD region70in the horizontal axis. In the vertical axis, edge540-1bisects the BL region20-2, and edge540-2bisects the BLB region20-2.

The NFET and PFET device edges can be offset in a relative position, as illustrated by reference491indicating a device edge for the PFET PU240-2, and reference492indicating a device edge of the NFET PD250-2. That is, along a vertical axis, the device edges491and492are offset as indicated by an amount510and they are offset relative to each other in the vertical axis.

FIG.6illustrates a cross-section of the stacked long cell nanosheet SRAM, where the cross-section is indicated by reference line495inFIG.4.FIG.6illustrates part of a semiconductor wafer600, comprising two cells401-1and401-2of a stacked long cell nanosheet SRAM. The NFET layer405is formed on a substrate610, and the PFET layer480is formed on the NFET layer405. The PFET pullup transistors40-1are on the PFET layer480, and the NFET pull down transistors50-1are on the NFET layer405. A backside of the wafer600is indicated by reference698, and a frontside of the wafer600is indicated by reference697. It is noted that other layers, which are not shown in this figure, are possible, such as those housing the backside connections from block485(toward the backside698) or the frontside connection(s) from block486(toward the frontside697). It is further noted that the offset510between the device edges is shown, this being an offset in the vertical axis between an outer edge of the sidewall material640of the PFET40-1and an outer edge of the sidewall material640of the NFET50-1. Note that reference510is shown in two different locations, both of which are between outer edges of sidewall material640

The layers615may be isolation layers. Reference630illustrates a patterned, stacked nanosheet comprising a layer640of an insulator (such as low k SiN) that performs electrical isolation, layers of gate material635, and layers semiconductor material650comprised of silicon that is used as nanosheet channel layers. Layers635and650are alternative. As is known, “low K” refers to a material with a small relative dielectric constant (the “K”) relative to silicon dioxide. Material620may be SiO2or another insulator and may be formed via a conformal process.

Both NFET layer405and the PFET layer480are layers that form their constituent transistors, and may be formed using multiple other layers. For instance, both of these use a patterned nanosheet630and a coating layer of material620, which may be considered to be a layer at least to the extent it provides a region between the NFET layer405and the PFET layer480.

This example has a minimum pitch P-P660, which can vary in nanometers (nm) depending on the pitch of the constituent components, and the minimum pitch660is between lines601and602. The minimum pitch660includes the following: a width606of 10-30 nm for gate material635on a right side of the channel region611; a width605of 10-200 nm of channel region611having the layers650in the patterned nanosheet630; a width604of 5-15 nm for the gate material635on the left side of the channel region611; a width603of 10-20 nm between the side edge of the gate material635for the cell401-2and a side edge of the gate material635for the cell401-1. For the width606, this gate material635is formed as part of a gate-to-gate connection612that connects to the channel region211of the NFET pull down transistor50-1, thereby coupling the gate region110of the pullup transistor40-1to the gate region110of the pull down transistor50-1. That is, the gate-to-gate connection612provides an electrical connection between FETs (NFET and PFET) on two levels.

The width603of 10-20 nm includes the insulators640and the insulator620, and indicates an isolation width of the PFET device. The device's active region corresponds to widths604,605, and606. It noted that the NFET50-1could have similar widths, within manufacturing tolerances, at least for some embodiments. The term “about” may therefore be used, as the widths603,604,605, and606could be slightly different than indicated due to manufacturing tolerances. Such tolerances can be quantified for a given technology.

FIG.6also illustrates pitch461of a single transistor of an NFET, in this case PD150-1, where another example of pitch461was illustrated inFIG.4. It is assumed that pitch461can be equivalent to pitch660.

The example inFIG.6uses gate material635to couple the gate regions110between the PFET pullup transistors40-1and the NFET pull down transistors50-1. Another example is illustrated inFIG.7, where instead of using gate material635, contact metal710is implemented for the gate-to-gate connections612, to couple and electrically connect the gate regions110(and gate material635on the right side of the gate) of the PFET pull up transistors40-1to the gate regions110(and gate material635on the top side of the gate) of the NFET pull down transistors50-1.

The minimum pitch660in this example is similar to the minimum pitch inFIG.6, so only the differences are described here. The width608of 10-12 nm includes the insulator640and the insulator620, and indicates an isolation width of the PFET device. The gate material635has symmetrical widths604and609on both sides of the channel region611, which can have a range of 5-15 nm. The width613of the gate-to-gate connections may have a range of 5-15 nm. The minimum pitch660in this example is shown, and may be slightly larger than the minimum pitch660inFIG.6. Further, the minimum pitch660inFIG.7can have a range that may be affected by manufacturing tolerances. The device's active region corresponds to widths604,605,609, and613.

Turning toFIG.8, this figure illustrates an intermixing of cells (bitcells)401with logic standard cells801. There are four cells (bitcells)401-1,401-2,401-3, and401-4, which are assumed to be similar to or the same as the cells previously described. Each cell (bitcell)401stores a single bit. Two logic standard cells801-1and801-2are shown, and this example lists these and NAND2 cells that are standard cell logic, e.g., basically a “packaged” cell, where each cell801has two NAND gates. Reference810indicates that there can be an intermixing of cells (bitcells)401with logic standard cells801in the same circuit row without any interface gap. In particular, by matching the cell heights H (and optionally the widths W) between logic and memory, the cells can be intermixed.

Referring toFIG.9, which is spread overFIGS.9A and9B, this figure is a flowchart of a method for forming a stacked layer memory. In block905, a first layer of the memory is formed, wherein the first layer comprises a plurality of transistors of a first type. In block910, s second layer of the memory is formed. The second layer comprises a plurality of transistors of a second type. The first and second layers are different layers and are formed to be stacked vertically. A width of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. Additional examples are as follows.

In block915, a bit line is formed so that a length of the bit line for multiple cells is equal to the pitch of the single transistor multiplied by a total number of the multiple cells. See the description above in relation toFIG.4and reference461.

In block920, the second layer is formed to be stacked on top of the first layer relative to a backside of a wafer upon which the first and second layers are formed. Block925is an example that builds on block920. Block925involves performing a self-aligned gate-to-gate process to form and align gate-to-gate connections between the gates of transistors of the first layer and the gates of transistors of the second layer.

For block930, widths of individual ones of the plurality of transistors of the first type are different from widths of individual ones of the plurality of transistors of the second type.

For block935, the stacked layer memory is formed in a standard circuit row also including a plurality of logic cells, wherein there is no interface gap formed between any stacked nanosheet memory and any logic cells of the plurality of logic cells. See alsoFIG.8and corresponding text.

Block940involves forming the stacked layer memory as SRAM. SRAM is one example, and other memories may use similar stacked layers. Blocks945and950further define block940. Block945involves forming a second layer to comprise first and second cross-couple connections (see reference11of the previous figures). Block950connects BL, BLB and GND to the backside of the wafer, see also block486ofFIG.4. Block955can depend from block950or from the general method (blocks905and910). In block955, the VDD (power) line is connected to the frontside of the wafer. See also block486ofFIG.4.

In block960, a length of a cell along a long axis of the cell is multiple times a length of the cell along a short axis of the cell. This is one exemplary description of a “long cell”.

In block965, pitch is equivalent to a width of an active region and an isolation width. For block970, the first type is n-type, and the second type is p-type.

Block975forms a stacked nanosheet memory, e.g., by forming and patterning a nanosheet and via other operations known to those skilled in the area. Block980further defines block975and entails forming the BL (and possibly the BLB) to run perpendicular to orientation of the patterned nanosheet. See, e.g.,FIG.4and alsoFIG.6for the nanosheet.

Block985involves forming a stacked fin-type FET memory. The steps for forming fin-type FET memory may include forming the first layer comprising forming the plurality of transistors of the first type as fin-type field-effect transistors of the first type, and forming the second layer comprising forming the plurality of transistors of the second type as fin-type field-effect transistors of the second type. Forming fin-type FETs is well known to those skilled in this area.

Block990involves forming edges of active regions for first and second layers to be offset. SeeFIGS.5and6for other description regarding this.

In the foregoing description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be appreciated by one of ordinary skill of the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may have been omitted or may have not been described in order to avoid obscuring the presented embodiments. It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly” over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.

Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “in direct contact”, “abutting”, “directly adjacent to”, “immediately adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:6T six-transistorBL bit lineBLB bit line inverse or inverse bit lineFET field-effect transistorFinFET fin-type field-effect transistorPD pulldownPFET p-type FETPG pass gatePU pullupM3third metal layerNFET n-type FETS/D source/drainSRAM static random-access memoryWL word line