Digital pixel and image sensor including the same

A digital pixel includes a photo diode connected to a first node and configured to generate an optical signal from an incident light, a storage diode configured to store the optical signal in a second node, a floating diffusion node configured to output a detection signal based on the optical signal, a first transmission transistor connected between the first and second nodes, and configured to transmit the optical signal from the first node to the second node, a second transmission transistor connected between the second node and the floating diffusion node, and configured to transmit the optical signal from the second node to the floating diffusion node, and a discharge transistor connected to the first node and configured to be turned on in a section in which the second transmission transistor is turned on to discharge a parasitic charge generated in the first node.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0078256, filed on Jun. 28, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the inventive concept relate to a digital pixel and an image sensor including the same.

DISCUSSION OF RELATED ART

An image sensor may convert an optical image into an electric signal. In recent years, due to development in the computer and communication industries, demand has increased for image sensors with enhanced performances in a variety of fields such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, medical micro cameras, and so on.

A related-art or conventional image sensor operates based on analog pixels. Analog signals may be outputted from the analog pixels according to incident light and converted into image data. However, since the above-described analog signals are vulnerable to noises or coupling in comparison to digital signals, the conventional image sensor has a problem when processing high-resolution image signals.

SUMMARY

According to an exemplary embodiment of the inventive concept, a digital pixel includes a photo diode connected to a first node and configured to generate an optical signal from an incident light, a storage diode configured to store the optical signal in a second node, a floating diffusion node configured to output a detection signal based on the optical signal, a first transmission transistor connected between the first and second nodes, and configured to transmit the optical signal from the first node to the second node, a second transmission transistor connected between the second node and the floating diffusion node, and configured to transmit the optical signal from the second node to the floating diffusion node, and a discharge transistor connected to the first node and configured to be turned on in a section in which the second transmission transistor is turned on to discharge a parasitic charge generated in the first node.

According to an exemplary embodiment of the inventive concept, a digital pixel includes an optical signal generator configured to generate a first optical signal from an incident light in a first section, an optical signal storage configured to receive the first optical signal from the optical signal generator and to store the first optical signal in a second section, a detection signal outputter configured to receive the first optical signal from the optical signal storage, and to output a detection signal based on the first optical signal in a third section, and a discharger configured to discharge a second optical signal generated from the optical signal generator in the third section.

According to an exemplary embodiment of the inventive concept, an image sensor includes a digital pixel array configured to sense an optical signal from an outside, and including a plurality of digital pixels each configured to output a digital pixel signal based on the optical signal, a pixel driver configured to output a control signal for controlling the digital pixel array, and a digital logic circuit configured to perform digital signal processing with respect to the digital pixel signal received from each of the plurality of digital pixels of the digital pixel array. Each of the plurality of digital pixels includes an optical signal generator configured to generate a first optical signal from an incident light in a first section, an optical signal storage configured to receive the first optical signal from the optical signal generator and to store the first optical signal in a second section, a detection signal outputter configured to receive the first optical signal from the optical signal storage, and to output a detection signal based on the first optical signal in a third section, and a discharger configured to discharge a second optical signal generated from the optical signal generator in the third section.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept provide a digital pixel and an image sensor including the same which have enhanced operating properties by preventing a parasitic charge from being transmitted to a storage node in a section in which an optical signal is transmitted to a floating diffusion node.

Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application.

FIG. 1is a view provided to explain an image sensor according to an exemplary embodiment of the inventive concept, andFIG. 2is a view provided to explain the image sensor ofFIG. 1in detail according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1, an image sensor100according to an exemplary embodiment of the inventive concept may include a digital pixel array1000, a pixel driver2000, and a digital logic circuit3000.

The digital pixel array1000may include digital pixels (DP)1100, each of which senses an optical signal from the outside, stores data corresponding to the sensed optical signal, and outputs a digital pixel signal DOUT digitally converted based on the sensed optical signal. The digital pixel1100may include an optical signal detector (photo detector) PDT1110, an analog-to-digital converted ADC1130, and memory cells (memory circuit) MC1150.

The optical signal detector PDT1110may detect the optical signal sensed from the outside and output a detection signal DET. The analog-to-digital converter ADC1130may convert the detection signal DET (an analog signal) detected by the optical signal detector1110into a digital signal, and output the digital pixel signal DOUT. In the present disclosure, the analog-to-digital converter1130may be referred to as a comparison circuit1130. The memory cells MC1150may store the digital pixel signal DOUT corresponding to the detection signal DET. The memory cells MC1150may output the stored digital pixel signal DOUT to the digital logic circuit3000.

The pixel driver2000may output a control signal CTRL for controlling the digital pixel array1000based on control of the digital logic circuit3000.

The digital logic circuit3000may perform digital signal processing with respect to the digital pixel signal DOUT received from the digital pixel array1000and provide a final image to an external device (for example, an image signal processor (ISP), an application processor (AP), etc.).

Unlike a conventional analog pixel, each of the digital pixels1100may store data corresponding to the detection signal DET detected by the optical signal detector1110, e.g., the digital pixel signal DOUT, at a pixel level. Accordingly, an area, a time, and power consumption that are required to store data in the digital pixel1100, read out stored data, or process the read-out data can be enhanced.

Referring toFIG. 2, the pixel driver2000may include a counter CNT, a row driver RDV, a ramp generator RAMP GEN, and a voltage generator V GER. The row driver RDV may select the digital pixels1100on a row-by-row basis. The row driver RDV may output an optical signal detector control signal CS_PD and a memory control signal CS_MC.

The counter CNT may initiate a counting operation with respect to the digital pixel signal DOUT based on a change of a voltage level VRAMP of a ramp signal RAMP, under control of the digital logic circuit3000. When the voltage level VRAMP of the ramp signal RAMP starts to be changed, the counter CNT may increase or reduce a value (e.g., a counting value) of a code CODE serially in every period of a clock signal. The value of the code CODE may change serially with time. The value of the code CODE may be in proportion to the voltage level VRAMP of the ramp signal RAMP.

The ramp generator RAMP GEN may output the ramp signal RAMP which is a signal decreasing or increasing constantly (for example, an increasing/decreasing signal having a constant slope) based on control of the digital logic circuit3000. The ramp signal RAMP may be referred to as a reference signal since it is compared with the detection signal DET detected by the optical signal detector1110. For example, the ramp generator RAMP GEN may be implemented by using an integrator.

The voltage generator V GER may generate various voltages for operating the image sensor100. The voltage generator V GER may supply analog voltages (for example, a power voltage VDDA, a bias voltage VB, etc.) to circuits processing analog signals in the digital pixels1100, and supply digital voltages to circuits processing digital signals in the digital pixels1100. The optical signal detector control signal CS_PD, the memory control signal CS_MC, the code CODE, and the ramp signal RAMP ofFIG. 2may be included in the control signal CTRL described with reference toFIG. 1.

According to an exemplary embodiment of the inventive concept, a size of the code CODE may be N-bit and the number of a plurality of transmission lines1300may be N. Accordingly, one bit may be transmitted per one transmission line. The digital pixel1100may receive the code CODE from the counter CNT through a first switch1210and the plurality of transmission lines1300. The digital pixel1100may latch and store a reset counting value and a signal counting value corresponding to a reset level and a signal level, respectively, of the detection signal DET detected by the optical signal detector1110, based on the code CODE. The reset counting value and the signal counting value may be used in correlated double sampling (CDS) performed by the digital logic circuit3000. The digital pixel1100may output, as the digital pixel signal DOUT, the reset counting value and the signal counting value to the digital logic circuit3000through the plurality of transmission lines1300and a second switch1230. The plurality of transmission lines1300may be arranged in a row direction and may extend in a column direction. The plurality of transmission lines1300may be shared by one or more digital pixels1100connected to the plurality of transmission lines1300.

The first switch1210may electrically connect the counter CNT and the plurality of transmission lines1300to transmit the code CODE to the digital pixel1100. The second switch1230may electrically connect the plurality of transmission lines1300and a sensing amplifier SA3100of the digital logic circuit3000to transmit the reset counting value and the signal counting value stored in the digital pixel1100to the sensing amplifier SA3100. Although it is illustrated inFIG. 2that the first switch1210is included in the digital pixel array1000, the first switch1210may be implemented in a different position of the image sensor100.

When the first switch1210electrically connects the counter CNT and the plurality of transmission lines1300, the second switch1230may not electrically connect the sensing amplifier3100and the plurality of transmission lines1300. To the contrary, when the second switch1230electrically connects the sensing amplifier3100and the plurality of transmission lines1300, the first switch1210may be turned off, and may not electrically connect the counter CNT and the plurality of transmission lines1300.

The first and second switches1210and1230may reduce the number of transmission lines which are used to transmit the code CODE to the digital pixel1100, and to read out the reset counting value and the signal counting value from the digital pixel1100.

The sensing amplifier3100may sense and amplify the digital pixel signal DOUT transmitted through the plurality of transmission lines1300. The plurality of transmission lines1300illustrated inFIG. 2may correspond to one group, the digital pixel array1000may have a plurality of groups of transmission lines arranged therein, and one or more sensing amplifiers3100may be implemented according to the number of the plurality of transmission lines1300.

FIG. 3is a view provided to explain a digital pixel ofFIG. 2according to an exemplary embodiment of the inventive concept.

Referring toFIG. 3, the digital pixel1100may operate in response to signals (for example, CS_PD) outputted from the pixel driver2000. The digital pixel1100may include the optical signal detector1110, the comparison circuit1130, and the memory circuit1150. The comparison circuit1130and the memory circuit1150ofFIG. 3may correspond to the ADC1130and the memory cells1150ofFIG. 1, respectively.

The optical signal detector1110may detect an optical signal entering from the outside and generate the detection signal DET corresponding to the detected optical signal. The detection signal DET may be an analog signal.

The comparison circuit1130may be a one-bit ADC or a differential amplifier, and compare the detection signal DET and the ramp signal RAMP. The comparison circuit1130may be referred to as a single-slope ADC. The comparison circuit1130may be an amplifier that receives the detection signal DET through a negative (−) input terminal and receives the ramp signal RAMP through a positive (+) input terminal. However, the polarities of the input terminals are merely examples. The voltage level VRAMP of the ramp signal RAMP may decrease or increase at a predetermined slope (linearly) during a predetermined time. When the voltage level VRAMP of the ramp signal RAMP reaches a voltage level VFD of the detection signal DET (when the voltage level VRAMP is lower or higher than the voltage level VFD), the comparison circuit1130may change a logic state (or phase) of a comparison signal CMP_OUT. When the voltage level VRAMP reaches a reset level and a signal level of the detection signal DET, the comparison circuit1130may change the logic state of the comparison signal CMP_OUT, such that the memory circuit1150latches a reset counting value and a signal counting value corresponding to the reset level and the signal level, respectively, of the detection signal DET. The operation of the comparison circuit1130will be described below with reference toFIG. 18.

The memory circuit1150may store the code CODE corresponding to the detection signal DET in response to the comparison signal CMP_OUT and the memory control signal CS_MC. The memory circuit1150may output the reset counting value and the signal counting value as the digital pixel signal DOUT in response to the memory control signal CS_MC.

FIG. 4is a circuit diagram provided to explain an optical signal detector included in the digital pixel ofFIG. 3according to an exemplary embodiment of the inventive concept.

Referring toFIG. 4, the optical signal detector1110may include a photo diode PD and one or more transistors TX1, TX2, TX3, RX1, RX2, and DX constituting a readout circuit.

The optical signal detector1110may include a photoelectric conversion element. The photoelectric conversion element may generate and accumulate electric charges in proportion to an amount of light entering from the outside. The photoelectric conversion element may convert incident light into an electric signal. For example, the photoelectric conversion element may be a photo diode (PD), a photo transistor, a photo gate, a pinned photo diode (PPD), or a combination thereof. AlthoughFIG. 4depicts that the photoelectric conversion element is the photo diode PD by way of an example, this should not be considered as limiting, and various types of photoelectric conversion elements may be implemented.

According to an exemplary embodiment of the inventive concept, the photo diode PD may be connected to a first node n1between a third transmission transistor TX3and a ground terminal, between a first reset transistor RX1and the ground terminal, or a discharge transistor DX and the ground terminal.

The first reset transistor RX1may be used to connect the photo diode PD to the power voltage VDDA based on a first reset signal RG1, and to remove photo charges accumulated in the photo diode PD.

A second transmission transistor TX2and the third transmission transistor TX3may transmit an electric charge between the photo diode PD and a storage diode SD. According to an exemplary embodiment of the inventive concept, the third transmission transistor TX3may be connected between the first node n1and a second node n2to transmit an electric charge between the photo diode PD and a second region SD2of the storage diode SD. According to an exemplary embodiment of the inventive concept, the second transmission transistor TX2may be connected between the second node n2and a third node n3to transmit an electric charge between the second region SD2and a first region SD1of the storage diode SD. The second transmission transistor TX2and the third transmission transistor TX3may be turned on or turned off by a second transmission signal TG2and a third transmission signal TG3, respectively. The third transmission transistor TX3may be referred to as a first sub transmission transistor and the second transmission transistor TX2may be referred to as a second sub transmission transistor.

The storage diode SD may temporarily store photo charges generated in the photo diode PD. AlthoughFIG. 4depicts the storage diode SD as an example of a light receiving element, the inventive concept is not limited thereto, and the light receiving element may be changed in any form. For example, the storage diode SD may be implemented by using a capacitor. According to an exemplary embodiment of the inventive concept, the storage diode SD may include the first region SD1and the second region SD2. For example, the first region SD1may be closer to a floating diffusion node FD than the second region SD2. According to an exemplary embodiment of the inventive concept, the photo charges accumulated in the photo diode PD may not be directly transmitted to the floating diffusion node FD and may be temporarily stored in the storage diode SD and then transmitted to the floating diffusion node FD, such that a global shutter operation of the image sensor100can be implemented. In other words, by accumulating information (for example, photo charges) stored in the plurality of digital pixels1100in the same section, and storing the same in the storage diode SD, the photo diode PD may be exposed at the same time even if an analog-to-digital converting operation is performed in different sections, and accordingly, the storage diode SD may operate as a global shutter.

A first transmission transistor TX1may electrically connect the third node n3and the floating diffusion node FD based on a first transmission signal TG1. The first transmission transistor TX1may be turned on or turned off by the first transmission signal TG1. The first transmission transistor TX1may transmit the charges accumulated in the storage diode SD to the floating diffusion node FD. The amount of the electric charges (Q) of the floating diffusion node FD transmitted through the first transmission transistor TX1may be converted into a voltage difference (=Q/CFD) by a capacitance CFD of the floating diffusion node FD. The voltage level VFD of the detection signal DET may correspond to a voltage level of the floating diffusion node FD.

A second reset transistor RX2may reset the floating diffusion node FD to the power voltage VDDA based on a second reset signal RG2. The second reset transistor RX2may discharge the electric charges accumulated in the floating diffusion node FD. The second reset transistor RX2may be turned on or turned off by the second reset signal RG2.

According to an exemplary embodiment of the inventive concept, when the second reset transistor RX2and the first to third transmission transistors TX1, TX2, and TX3are turned on, the electric charges of the photo diode PD may be discharged, and the photo diode PD may also be reset.

The discharge transistor DX may discharge the electric charges accumulated in the first node n1, e.g., in the photo diode PD, based on a discharge signal DG. The discharge transistor DX may be turned on or turned off by the discharge signal DG. The operation of the discharge transistor DX will be described below with reference toFIG. 8.

FIG. 5is a top view provided to explain the digital pixel ofFIGS. 3 and 4according to an exemplary embodiment of the inventive concept.FIG. 6is a cross-sectional view taken on line A-A′ ofFIG. 5according to an exemplary embodiment of the inventive concept.FIG. 7is a cross-sectional view taken on line B-B′ ofFIG. 5according to an exemplary embodiment of the inventive concept. For convenience of explanation, some elements of the digital pixel1100explained with reference toFIG. 4are omitted inFIGS. 5 to 7, but the digital pixel1100may include the omitted elements (for example, the first and second reset transistors RX1and RX2, etc.).

Referring toFIGS. 5 to 7, the digital pixel1100according to an exemplary embodiment of the inventive concept may include a substrate10, the first to third transmission transistors TX1, TX2, and TX3, the discharge transistor DX, the photo diode PD, the storage diode SD, the floating diffusion node FD, etc. The discharge transistor DX, the photo diode PD, the storage diode SD, and the floating diffusion node FD may be referred to as a discharger, an optical signal generator, an optical signal storage, and a detection signal outputter, respectively.

The substrate10may be, for example, a bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate10may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The substrate10may be a base substrate having an epitaxial layer formed thereon.

The first to third transmission transistors TX1, TX2, and TX3may include a conductive material, for example. The conductive material may be, for example, doped poly silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium (Ti), tantalum (Ta), or tungsten (W), although the inventive concept is not limited thereto.

The photo diode PD may be formed inside the substrate10. The photo diode PD may be formed with a plurality of doped regions stacked one on another. In this case, a lower portion of the photo diode PD may be formed by injecting an n+ type ion, and an upper portion thereof may be formed by injecting an n− type ion. The photo diode PD may function as a light sensing element, and simultaneously, may function as a storage region to store an electric charge generated by sensing an optical signal.

The photo diode PD may be formed adjacent to a rear surface of the substrate10. In addition, at least a part of the rear surface of the substrate10may be covered by a shielding film1116formed within a planarization film1115, but the rear surface of the substrate10overlapping the photo diode PD may be exposed by the shielding film1116. This is to transmit light collected from a lens to the photo diode PD.

The storage diode SD may be formed inside the substrate10. The storage diode SD may be formed with a plurality of doped regions stacked one on another. In this case, a lower portion of the storage diode SD may be formed by injecting an n+ type ion, and an upper portion thereof may be formed by injecting an n− type ion.

The second and third transmission transistors TX2and TX3may transmit electric charges stored in the photo diode PD to the storage diode SD. For example, the third transmission transistor TX3may be turned on by the third transmission signal TG3to connect the photo diode PD and the second region SD2of the storage diode SD. In other words, the photo diode PD may function as a source of the third transmission transistor TX3, and the second region SD2of the storage diode SD may function as a drain of the third transmission transistor TX3.

In addition, the second transmission transistor TX2may be turned on by the second transmission signal TG2to connect the second region SD2of the storage diode SD and the first region SD1. In other words, the second region SD2of the storage diode SD may function as a source of the second transmission transistor TX2, and the first region SD1of the storage diode SD may function as a drain of the second transmission transistor TX2. According to an exemplary embodiment of the inventive concept, the first region SD1of the storage diode SD may be relatively closer to the floating diffusion node FD than the second region SD2.

AlthoughFIGS. 5 to 7depict that the optical signal detector1110includes the second and third transmission transistors TX2and TX3, this should not be considered as limiting, and one transistor may be implemented to transmit an electric charge between the photo diode PD and the storage diode SD. In another example, the design may be changed to include three or more transistors to transmit the electric charge between the photo diode PD and the storage diode SD.

The first transmission transistor TX1may transmit the electric charge temporarily stored in the storage diode SD to the floating diffusion node FD. For example, the first transmission transistor TX1may be turned on by the first transmission signal TG1to connect the storage diode SD and the floating diffusion node FD.

Referring toFIG. 6, in the case of the cross-section taken on line A-A′, the photo diode PD may be surrounded by a deep trench isolation (DTI)1111and a DTI1112, and may not be connected with the storage diode SD. In addition, the storage diode SD may be surrounded by the DTI1112and a DTI1113and may not be connected with the photo diode PD. In other words, a channel may not be formed between the photo diode PD and the storage diode SD. The DTI1111, the DTI1112, and the DTI1113may be formed by a front-side deep trench isolation (FDTI) process.

Referring toFIG. 7, in the case of the cross-section taken on line B-B′, a first channel CH1may be formed between the photo diode PD and the storage diode SD. In other words, a DTI1114formed between the photo diode PD and the storage diode SD may not be extended to an upper surface of the substrate10, and may be extended only to a part of the substrate10in a height direction. Accordingly, the first channel CH1may be formed between the photo diode PD and the storage diode SD to transmit an electric charge. According to an exemplary embodiment of the inventive concept, the DTI1114may be formed by a back-side deep trench isolation (BDTI) process.

According to an exemplary embodiment of the inventive concept, in the optical signal detector1110of the digital pixel1100, the first channel CH1may be formed to transmit an electric charge between the photo diode PD and the storage diode SD, and a second channel CH2may be formed to transmit an electric charge between the storage diode SD and the floating diffusion node FD.

Referring back toFIG. 5, the discharge transistor DX according to an exemplary embodiment of the inventive concept may be disposed on the substrate10to discharge an electric charge generated in the photo diode PD in the process of transmitting the electric charge stored in the storage diode SD to the floating diffusion node FD. The discharge transistor DX may be disposed adjacent to the first channel CH1between the photo diode PD and the storage diode SD.

The digital pixel1100according to an exemplary embodiment of the inventive concept may operate to avoid transferring a parasitic charge, which is generated in the photo diode PD in the process of transmitting an optical signal to be obtained, to the storage diode SD, and to discharge the parasitic charge to a drain of the discharge transistor DX. Accordingly, the digital pixel1100can enhance parasitic light sensitivity (PLS) or shutter efficiency of the image sensor100. The operation of the discharge transistor DX will be described in detail with reference toFIGS. 8 to 15B.

FIG. 8is a timing chart provided to explain an operation of the optical signal detector ofFIG. 4according to an exemplary embodiment of the inventive concept.FIGS. 9A, 10A, 11A, 12A, 13A, 14A, and 15Aare top views illustrating the operation of the optical signal detector ofFIG. 8according to an exemplary embodiment of the inventive concept, andFIGS. 9B, 10B, 11B, 12B, 13B, 14B, and 15Bare views illustrating movement of an electric charge to explain the operation of the optical signal detector ofFIG. 8according to an exemplary embodiment of the inventive concept. Hereinafter, a process of accumulating photo charges TC in the photo diode PD, storing the photo charges TC in the storage diode SD through the first channel CH1, and transmitting the photo charges TC to the floating diffusion node FD through the second channel CH2will be described in detail with reference toFIGS. 8 to 15B.

Referring toFIG. 8, the first reset signal RG1having a voltage level VRG1is provided to the gate of the first reset transistor RX1at a first time t1. The first reset signal RG1may turn on the first reset transistor RX1, and connect the photo diode PD to the power voltage VDDA to reset charges accumulated in the photo diode PD.

Next, at a second time t2, the provision of the first reset signal RG1ends and an electric charge starts to be accumulated in the photo diode PD. In this case, voltages may not be provided to the gates of the first to third transmission transistors TX1, TX2, and TX3and the second reset transistor RX2. In other words, they may be turned off.

According to an exemplary embodiment of the inventive concept, a discharge signal DG having a first discharge voltage level VDG(0) may be applied to the gate of the discharge transistor DX from the first time t1at which the first reset transistor RX1is turned on to a second time t2. In other words, in the reset operation of the photo diode PD, not only the first reset transistor RX1but also the discharge transistor DX may be turned on and operated, and efficiency of the reset operation can be enhanced.

Next, electric charges may be accumulated in the photo diode PD from the second time t2to a fourth time t4. According to an exemplary embodiment of the inventive concept, the second reset signal RG2having a voltage level VRG2may be provided to the gate of the second reset transistor RX2at a third time t3. The second reset signal RG2may be applied to the gate of the second reset transistor RX2, and the power voltage VDDA may not be applied to a terminal of the second reset transistor RX2that is not connected with the floating diffusion node FD. In this case, a voltage level of the floating diffusion node FD may be low, and an electric charge may be prevented from flowing over to the floating diffusion node FD when an electric charge is transmitted from the photo diode PD to the storage diode SD afterward.

Referring toFIG. 8andFIGS. 9A and 9B, photo charges TC may be accumulated in the photo diode PD from the second time t2to the fourth time t4. InFIGS. 9A to 15A, the photo charge TC may refer to a charge for an image to be obtained, and a parasitic charge PC may refer to a charge which is accumulated in the photo diode PD in the process of transmitting the photo charge TC and causes a noise in the image to be generated.

Referring toFIG. 8andFIGS. 10A and 10B, the photo charges TC accumulated in the photo diode PD may be transmitted to the storage diode SD from the fourth time t4to a fifth time t5. For example, the second transmission signal TG2having a voltage level VTG2may be applied to the gate of the second transmission transistor TX2, and the third transmission signal TG3having a voltage level VTG3(0) may be applied to the gate of the third transmission transistor TX3, such that the second and third transmission transistors TX2and TX3are turned on. Accordingly, the first channel CH1may be formed between the photo diode PD and the storage diode SD, and the photo charges TC may be transmitted to the storage diode SD through the first channel CH1.FIG. 8illustrates that the second reset transistor RX2is turned on at the third time t3, before the photo charges TC are transmitted to the storage diode SD at the fourth time t4. However, the inventive concept is not limited thereto, and the second reset transistor RX2may be turned on at the fourth time t4.

Referring toFIG. 8andFIGS. 11A and 11B, from the fifth time t5to a sixth time t6, the photo charges TC may be transmitted to the storage diode SD, and the third transmission signal TG3having a voltage level VTG3(1) may be applied to the gate of the third transmission transistor TX3. In other words, the voltage level VTG3(1) lower than the voltage level VTG3(0) may be applied to the gate of the third transmission transistor TX3. According to an exemplary embodiment of the inventive concept, the second transmission transistor TX2may enable transmission to the first region SD1of the storage diode SD and control transmission to the second region SD2of the storage diode SD by the third transmission transistor TX3, and the first region SD1may be closer to the floating diffusion node FD than the second region SD2. The third transmission signal TG3having the voltage level VTG3(1) lower than the voltage level VTG3(0) may be applied to the gate of the third transmission transistor TX3, such that the photo charges TC can be stably stored in the first region SD1disposed relatively closer to the floating diffusion node FD.

Referring toFIG. 8andFIGS. 12A and 12B, the third transmission signal TG3applied to the third transmission transistor TX3may not be applied from the sixth time t6to a seventh time t7. In other words, the third transmission transistor TX3may be switched to a turn-off state. Accordingly, the photo charges TC may be stored in the first region SD1of the storage diode SD.

Referring toFIG. 8andFIGS. 13A and 13B, the second and third transmission transistors TX2and TX3may be turned off from the seventh time t7to an eighth time t8. In other words, after the photo charges TC are transmitted from the photo diode PD to the storage diode SD, the gate voltages applied to the second and third transmission transistors TX2and TX3may not be provided, and the photo charges TC may remain stored in the storage diode SD.

Referring toFIG. 8andFIGS. 14A and 14B, the photo charges TC stored in the storage diode SD may be transmitted to the floating diffusion node FD from the eighth time t8to a ninth time t9. For example, the first transmission signal TG1having a voltage level VTG1may be applied to the gate of the first transmission transistor TX1at the eighth time t8. Accordingly, the first transmission transistor TX1may be turned on, and the photo charges TC stored in the storage diode SD may be transmitted to the floating diffusion node FD.FIG. 8illustrates that the second reset transistor RX2is turned off at the eighth time t8. However, the inventive concept is not limited thereto, and the second reset transistor RX2may be turned on before the eighth time t8.

At the eighth time t8, the discharge signal DG having a voltage level VDG(1) may be applied to the gate of the discharge transistor DX, and accordingly, the discharge transistor DX may be turned on. As such, the parasitic charge PC generated in the photo diode PD may be discharged to a drain region of the discharge transistor DX through the discharge transistor DX. According to an exemplary embodiment of the inventive concept, in the process of transmitting the photo charges TC from the storage diode SD to the floating diffusion node FD, the discharge transistor DX may be turned on, and the parasitic charge PC generated in the photo diode PD may not be transmitted to the storage diode SD and may be discharged to the drain of the discharge transistor DX, such that a noise of an image, e.g., an image based on the photo charges TC, can be minimized.

Referring toFIG. 8andFIGS. 15A and 15B, the first transmission transistor TX1and the discharge transistor DX may be turned off after the ninth time t9. In other words, the photo charges TC may have been moved to the floating diffusion node FD, and the parasitic charge PC, generated in the photo diode PD in the process of transmitting the photo charges TC from the storage diode SD to the floating diffusion node FD, may have been discharged to the drain region of the discharge transistor DX. Thereafter, the detection signal DET may be outputted based on the photo charges TC transmitted to the floating diffusion node FD and may be inputted to the comparison circuit1130as an input.

FIG. 16is a circuit diagram provided to explain a digital pixel according to an exemplary embodiment of the inventive concept, andFIG. 17is a view illustrating the digital pixel ofFIG. 16according to an exemplary embodiment of the inventive concept. Hereinafter, a redundant explanation of the configuration and the operation of the optical signal detector1110described with reference toFIG. 4will be omitted.

Referring toFIG. 16, in an image sensor100A, the comparison circuit1130may include transistors MN1-MN4and MP1-MP3. Gates of the transistors MN1and MN2may be input terminals of the comparison circuit1130which is a differential amplifier and may receive the detection signal DET and the ramp signal RAMP. Sources of the transistors MN1and MN2may be electrically connected with each other, and may be biased by the transistor MN3which is a current source. A gate of the transistor MN3may be connected with the bias voltage VB, and a bias current may flow through the transistor MN3according to the bias voltage VB.

The transistor MP1may be connected between the power voltage VDDA and the drain of the transistor MN1. The transistor MP2may be connected between the power voltage VDDA and the drain of the transistor MN2. For example, the power voltage VDDA supplied to the comparison circuit1130may be an analog voltage, and may be different from digital power voltage(s) supplied to other elements MC1, MC2, SEL1, etc. The drain of the transistor MP1may be connected to the drain of the transistor MN1. The drain of the transistor MN1, the gate and the drain of the transistor MP1, and the gate of the transistor MP2may be connected with one another. The transistors MP1and MP2may constitute a current mirror load.

The transistors MN1, MN2, MN3, MP1, and MP2may amplify a difference between the voltage level VFD of the floating diffusion node FD and the voltage level VRAMP of the ramp signal RAMP. Voltage levels of the drains of the transistors MN2and MP2may be determined according to the voltage level VFD and the voltage level VRAMP of the ramp signal RAMP. The gate of the transistor MP3may receive voltage levels of the drains of the transistors MN2and MP2. The transistor MN4may operate similarly to the transistor MN3. The transistors MN4and MP3may generate the comparison signal CMP_OUT by reversing the voltage levels of the drains of the transistors MN2and MP2, similarly to an inverter. For example, when the voltage level VRAMP of the ramp signal RAMP is higher than the voltage level VFD of the floating diffusion node FD, the level of the comparison signal CMP_OUT may be the power voltage VDDA corresponding to logic high (for example, “1”). When the voltage level VRAMP of the ramp signal RAMP reaches the voltage level VFD of the floating diffusion node FD or becomes lower than the voltage level VFD of the floating diffusion node FD, the level of the comparison signal CMP_OUT may be switched from the power voltage VDDA to a power voltage GND corresponding to logic low (for example, “0”).

The types (P-type, N-type) of the above-described transistors MN1-MN4and MP1-MP3, and the voltage (logic) levels of the comparison signal CMP_OUT according to the voltage levels VRAMP and VFD are merely examples. According to an exemplary embodiment of the inventive concept, when a result of comparing the voltage level VRAMP of the ramp signal RAMP and the voltage level VFD of the floating diffusion node FD is changed, the level of the comparison signal CMP_OUT may also be changed. The number of the transistors constituting the comparison circuit1130is not limited to that illustrated inFIG. 16and may be implemented differently.

The memory circuit1150may operate in response to the comparison signal CMP_OUT and the memory control signal CS_MC. The memory circuit1150may include a first selection circuit SEL1, a second selection circuit SEL2, a first memory cell MC1, and a second memory cell MC2. The memory cell MC1may store a reset counting value corresponding to a reset level of the detection signal DET, and the memory cell MC2may store a signal counting value corresponding to a signal level of the detection signal DET.

Each of the first and second memory cells MC1and MC2may be a dynamic random access memory (DRAM) cell 1T-1C including a transistor TR and a capacitor C1. The transistor TR of the first memory cell MC1may electrically connect a first bit line BL1and the capacitor C1according to a signal of a first word line WL1. The transistor TR of the second memory cell MC2may electrically connect a second bit line BL2and the capacitor C1according to a signal of a second word line WL2. According to an exemplary embodiment of the inventive concept, each of the first and second memory cells MC1, MC2may store 1 bit. The number of the first memory cells MC1may be N (where N is a natural number), and the number of the second memory cells MC2may be N. For example, the number of the first memory cells MC1, the number of the second memory cells MC2, and the number of the plurality of transmission lines1300may be N, e.g., may be the same. However, the number of the first memory cells MC1, the number of the second memory cells MC2, and the number of the plurality of transmission lines1300may be implemented to be different from one another.

Referring toFIG. 17, the first selection circuit SEL1may control the first and second word lines WL1and WL2in response to the comparison signal CMP_OUT and the memory control signal CS_MC. The first selection circuit SEL1may include the first switch1210. Each of the first switches1210may provide a first voltage V1to any one of the first word line WL1and the second word line WL2in response to the comparison signal CMP_OUT and the memory control signal CS_MC. The first voltage V1may be a high voltage that turns on the respective transistors TR of the first and second memory cells MC1and MC2.

The memory control signal CS_MC may include first and second sampling signals SMP1and SMP2, and first and second readout signals RD1and RD2. The first sampling signal SMP1may be a signal for storing a reset sampling value in the first memory cell MC1, and the second sampling signal SMP2may be a signal for storing a signal sampling value in the second memory cell MC2. The first readout signal RD1may be a signal for outputting the reset sampling value stored in the first memory cell MC1as output data DOUT (e.g., the digital pixel signal DOUT), and the second readout signal RD2may be a signal for outputting the signal sampling value stored in the second memory cell MC2as the output data DOUT. However, the memory control signal CS_MC for controlling the memory circuit1150may be variously changed.

When the level of the comparison signal CMP_OUT is switched while the first sampling signal SMP1is being activated, the first switch1210may turn on the transistors TR of the first memory cell MC1and select (activate) the first memory cell M1, and may turn off the transistors TR of the second memory cell MC2and may avoid selecting the second memory cell MC2. The first switch1210may electrically connect the counter CNT and the plurality of transmission lines1300while the first sampling signal SMP1is being activated. The first memory cell MC1may store, as the reset sampling value, a value of the code CODE at the time when the level of the comparison signal CMP_OUT is switched while the first sampling signal SMP1is being activated.

When the level of the comparison signal CMP_OUT is switched while the second sampling signal SMP2is being activated, the first switch1210may turn on the transistors TR of the second memory cell MC2and select the second memory cell MC2, and may turn off the transistors TR of the first memory cell MC1and may avoid selecting the first memory cell MC1. The first switch1210may electrically connect the counter CNT and the plurality of transmission lines1300while the second sampling signal SMP2is being activated. The second memory cell MC2may store, as the signal sampling value, a value of the code CODE at the time when the level of the comparison signal CMP_OUT is switched while the second sampling signal SMP2is being activated.

When the first readout signal RD1is activated, the first selection circuit SEL1may select the first memory cell MC1and may avoid selecting the second memory cell MC2. When the second readout signal RD2is activated, the first selection circuit SEL1may select the second memory cell MC2and may avoid selecting the first memory cell MC1. When the first or second read-out signal RD1or RD2is activated, the second switch1230may electrically connect the plurality of transmission lines1300and the sensing amplifier SA. The reset sampling value stored in the first memory cell MC1may be outputted to the sensing amplifier SA. In addition, the signal sampling value stored in the second memory cell MC2may be outputted to the sensing amplifier SA. When the counting values stored in the first and second memory cells MC1and MC2are outputted, the first and second memory cells M1and MC2may be selected by the first and second readout signals RD1and RD2, respectively, regardless of the comparison signal CMP_OUT.

The second selection circuit SEL2may include the second switch1230to electrically connect the plurality of transmission lines1300and one of the first bit line BL1and the second bit line BL2in response to the memory control signal CS_MC. The second switch1230may perform a switching operation between the first bit line BL1, the second bit line BL2, and the plurality of transmission lines1300in response to the memory control signal CS_MC (for example, SMP1, SMP2, RD1, and RD2).

When the first sampling signal SMP1is activated, the second switch1230may connect the first bit line BL1to the plurality of transmission lines1300. The code CODE may be provided to the first memory cell MC1through the plurality of transmission lines1300, the second switch1230, and the first bit line BL1. When the second sampling signal SMP2is activated, the second switch1230may connect the second bit line BL2to the plurality of transmission lines1300. The code CODE may be provided to the second memory cell MC2through the plurality of transmission lines1300, the second switch1230, and the second bit line BL2.

When the first readout signal RD1is activated, the second switch1230may connect the first bit line BL1to the plurality of transmission lines1300. The reset sampling value stored in the first memory cell MC1may be outputted as the output data DOUT through the plurality of transmission lines1300. When the second readout signal RD2is activated, the second switch1230may connect the second bit line BL2to the plurality of transmission lines1300. The signal sampling value stored in the second memory cell MC2may be outputted as the output data DOUT through the plurality of transmission lines1300.

According to an exemplary embodiment of the inventive concept, the first and second selection circuits SEL1and SEL2may control a plurality of memory cells included in other digital pixels configured to operate at substantially the same timing. In other words, at least two digital pixels of the plurality of digital pixels may be configured to share the first and second selection circuits SEL1and SEL2that are provided separately. In this case, the first and second selection circuits SEL1and SEL2may be omitted in the memory circuit of each of the at least two digital pixels.

According to an exemplary embodiment of the inventive concept, one end (drain) of each of the transistors TR of the plurality of first memory cells MC1of the digital pixel1100may be connected with each of the plurality of transmission lines1300. One end (drain) of each of the transistors TR of the second memory cells MC2of the digital pixel1100may be connected with each of the plurality of transmission lines1300. According to an exemplary embodiment of the inventive concept, the two memory cells MC1and MC2may be connected with every one of the plurality of transmission lines1300. Only one of the two memory cells MC1, MC2connected to one transmission line may be selected by the first selection circuit SEL1, and the other one may not be selected. According to an exemplary embodiment of the inventive concept, the digital pixel1100may not include the second selection circuit SEL2unlike in the exemplary embodiment shown inFIG. 16.

FIG. 18is a timing chart provided to explain an operation of the digital pixel ofFIG. 16according to an exemplary embodiment of the inventive concept.

Before a 11th time T11, the photo diode PD, the storage diode SD, and the floating diffusion node FD may be reset, and the voltage level VFD of the detection signal DET may be set to a reset level. From the 11th time T11to a 13th time T13, the voltage level VRAMP of the ramp signal RAMP may decrease (or increase) at a predetermined slope. The first sampling signal SMP1may be activated from the 11th time T11to the 13th time T13. The time during which the first sampling signal SMP1is activated may correspond to a time during which the voltage level VRAMP decreases at the predetermined slope for the sake of reset level sampling. The voltage level VRAMP may start to be changed from the 11th time T11, and the counter CNT may initiate the counting operation from the 11th time T11. A counting value R of the code CODE may be in proportion (or inverse proportion) to the voltage level VRAMP which is changed with time and may correspond thereto.

At a 12th time T12, the voltage level VRAMP may reach the voltage level VFD, and, right after the 12th time T12, the voltage level VRAMP may be lower than the voltage level VFD. At the 12th time T12, the comparison signal CMP_OUT may be switched from logic high (or low) to logic low (or high). Respective bits of the counting value R of the code CODE, at the time T12when the level of the comparison signal CMP_OUT is switched while the first sampling signal SMP1is being activated, may be stored in the first memory cells MC1as a reset counting value.

A time from the 11th time T11to the 13th time T13may be to detect a reset level of the optical signal detector1110. At the 13th time T13, the voltage level VRAMP may be changed back to an initial (reset) level, and the voltage level of the comparison signal CMP_OUT may be changed back to an initial level.

At a 14th time T14, the first transmission signal TG1may be activated for a predetermined time, and the first transmission transistor TX1may be turned on to detect the signal level of the optical signal detector1110. Accordingly, the photo charges TC stored in the storage diode SD may be provided to the floating diffusion node FD through the first transmission transistor TX1, and the voltage level VFD of the floating diffusion node FD may be changed from a reset level to a signal level.

The 14th time T14may correspond to the 8th time t8ofFIG. 8. Accordingly, at the 14th time T14, the first transmission transistor TX1may be turned on, and also, the discharge transistor DX may be turned on, such that the parasitic charge PC generated in the photo diode PD is not transmitted to the storage diode SD and is discharged to the drain of the discharge transistor DX.

According to an exemplary embodiment of the inventive concept, the 4th time t4to 7th time t7ofFIG. 8during which the second and third transmission transistors TX2and TX3are turned on and the photo charges TC accumulated in the photo diode PD are transmitted to the storage diode SD may be before the 14th time ofFIG. 18.

From a 15th time T15to a 17th time T17, the voltage level VRAMP may decrease at the predetermined slope to detect the signal level of the optical signal detector1110. The second sampling signal SMP2may be activated from the 15th time T15to the 17th time T17. The time during which the second sampling signal SMP2is activated may correspond to a time during which the voltage level VRAMP decreases at the predetermined slope for the sake of signal level sampling. The voltage level VRAMP may start to be changed from the 15th time T15, and the counter CNT may initiate a counting operation again from the 15th time T15.

At a 16th time T16, the voltage level VRAMP may reach the voltage level VFD, and, right after the 16th time T16, the voltage level VRAMP may be lower than the voltage level VFD. At the 16th time T16, the comparison signal CMP_OUT may be switched from logic high to logic low. Respective bits of a counting value S of the code CODE, at the time T16when the level of the comparison signal CMP_OUT is switched while the second sampling signal SMP2, is being activated may be stored in the second memory cells MC2as a signal counting value.

A time from the 15th time T15to the 17th time T17may be to detect the signal level of the optical signal detector1110. At the 17th time T17, the voltage level VRAMP may be changed back to the initial level, and the level of the comparison signal CMP_OUT may be changed back to the initial level. The reset counting value and the signal counting value stored in the memory cells MC1and MC2may be read out, respectively, during the time from the 17th time T17to an 18th time T18. The reset counting value stored in the first memory cells MC1may be read out during a time when the first readout signal RD1is being activated. The signal counting value stored in the second memory cells MC2may be read out during a time when the second readout signal RD2is being activated. The order of reading out is not limited to that illustrated inFIG. 18, and the plurality of transmission lines1300used for reading out the reset counting value, and the plurality of transmission lines1300used for reading out the signal counting value may be the same as each other and may be shared. The digital pixel1100may repeat the operations performed from the 11th time T11to the 18th time T18.

FIG. 19is a circuit diagram provided to explain a digital pixel according to an exemplary embodiment of the inventive concept.

Referring toFIG. 19, in an image sensor100B, an optical signal detector1110′ may further include a source follower SF and an auto zero transistor AZX. In addition, the optical signal detector1110′ may further include a capacitor CAZconnected between the floating diffusion node FD and a fourth node n4. The capacitor CAZmay be a passive element, a metal oxide semiconductor (MOS) transistor, a metal insulator metal (MIM) capacitor, a cell capacitor, or the like. The capacitor CAZmay be used to cancel an offset voltage due to a mismatch of the comparison circuit1130, a difference in threshold voltages of the transistors, or a difference in geometry of the comparison circuit1130. The auto zero transistor ACX of the optical signal detector1110′ may short-circuit the fourth node n4, which is an input terminal of the comparison circuit1130, and an output terminal of the comparison circuit1130through which the comparison signal CMP_OUT is outputted, in response to an auto zero signal AZG. In this case, the auto zero signal AZG is applied to the gate of the auto zero transistor AZX, such that the auto zero transistor AZX is turned on, and accordingly, the comparison signal CMP_OUT is transmitted to the fourth node n4. An electric charge corresponding to an offset voltage of the comparison circuit1130may be stored in the capacitor CAZ. Since the detection signal DET, in which the voltage of the capacitor CAZis added to the voltage of the floating diffusion node FD, is inputted to the comparison circuit1130, the offset voltage of the comparison circuit1130may be removed.

FIG. 20is a view provided to explain a digital pixel array according to an exemplary embodiment of the inventive concept.

Referring toFIG. 20, the digital pixel1100according to an exemplary embodiment of the inventive concept may share one floating diffusion node FD and one comparison circuit1130B. For example, the digital pixel1100may include M optical signal detectors1110A,1110B, . . . ,1110C, the comparison circuit1130B, and a memory circuit1150B. The memory circuit1150B may include the first and second memory cells MC1and MC2each having N memory cells, the first selection circuit SEL1, and the second selection circuit SEL2. M is a natural number greater than or equal to 2. The plurality of optical signal detectors1110A,1110B, . . . ,1110C included in one digital pixel1100may include the same or different color filters.

According to an exemplary embodiment of the inventive concept, a reset counting value and a signal counting value of the optical signal detector1110A may be stored in the memory cells MC1and MC2, and the reset counting value and the signal counting value of the optical signal detector1110A may be read out from the next memory cells MC1and MC2. Similarly, a reset counting value and a signal counting value of the optical signal detector1110B may be stored in the memory cells MC1and MC2, and the reset counting value and the signal counting value of the optical signal detector1110B may be read out from the next memory cells MC1and MC2. In substantially the same way, the optical signal detectors including the last optical signal detector1110C which is the M-th optical signal detector may perform similar operations to those of the optical signal detector1110A and the optical signal detector1110B.

According to an exemplary embodiment of the inventive concept, the optical signal detectors1110A,1110B, . . . ,1110C share the floating diffusion node FD, and accordingly, integration of the image sensor100can be enhanced.

While the inventive has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that many variations and modifications in form and details may be made thereto without substantially departing from the spirit and scope of the inventive concept as set forth by the appended claims.