Dual-edge synchronized data sampler

A dual-edge synchronized sampler having an efficient implementation for high speed and high performance operation is described. The sampler receives a data input signal and a clock input signal and uses an asynchronous level mode state machine to sample the data input signal responsive to level changes in the clock input signal. In some embodiments, the sampler includes at least one differential logic block for implementing the asynchronous level mode state machine. The sampler has symmetric clock-to-Q propagation delays for both rising and falling edges of the clock input signal. The sampler may include toggle functionality, and may include edge control logic for configuring the sampler as one of a rising edge and falling edge sampler.

FIELD OF THE INVENTION

The invention relates to sampler circuits, and more particularly, to a dual-edged synchronized data sampler.

BACKGROUND OF THE INVENTION

One of the critical challenges for circuit designers is managing timing of their designs. Precise control over timing and clock signals can enable higher performance and more reliable designs. This challenge to manage timing, however, has become greater as circuits grow more complex and clock frequencies increase.

Dual or double data rate (DDR) applications and designs have become increasingly popular as clock rates continue to increase into the gigahertz range and beyond. At very high frequencies, distributing an accurate, jitter-free clock becomes increasingly difficult. A double data rate application mitigates this problem by using both rising and falling edges of a clock. Thus, a DDR application only requires a clock having half the frequency of the corresponding data rate. DDR interfaces are commonly used for memory interfaces, as well as many other applications.

Conventional DDR techniques typically use 2 or more conventional flip-flops to obtain the desired functionality. For instance, a simple DDR input may include two standard edge-triggered flip-flops. One flip-flop may be configured to latch data on rising edge and the other may be configured to latch data on falling edges. In some instances, an inverted clock may be provided to a rising edge-triggered flip-flop to provide falling edge functionality. The DDR data stream would then be provided to the input of both latches.

Conventional DDR circuits, however, may have certain disadvantages. As noted above, a conventional DDR interface includes at least two separate flip-flops, thereby occupying greater area than single data rate (SDR) interfaces, which may only have one flip-flop. Furthermore, conventional DDR circuits may not be capable of operating at the high speeds required by many modern applications. Also, a conventional DDR circuit can introduce asymmetry or other errors in a design.

Accordingly, there is a need for a dual-edge sampler that addresses these and other shortcomings of conventional DDR circuits.

SUMMARY OF THE INVENTION

A sampling circuit for sampling an data signal responsive to a clock signal is described. An exemplary embodiment includes a dual-edge sampler having a clock terminal for receiving the clock signal, a data input terminal for receiving the data signal, an output terminal for providing an output signal, and an asynchronous level mode state machine configured to sample the data signal at every edge of the clock signal and provide sampled data as the output signal. In some embodiments, the asynchronous level mode state machine may include one or more differential logic blocks for generating one or more intermediate results responsive to current state information and the data signal. In some embodiments, the sampling circuit may have a toggle function. In some embodiments the sampling circuit may include edge control logic for selectively configuring the sampler as a rising edge or falling edge triggered sampler responsive to an edge control signal.

Additional novel aspects and embodiments are described in the detailed description below. The appended claims, and not this summary, define the scope of the invention.

DETAILED DESCRIPTION

The present invention is believed to be applicable to a variety of integrated circuits and designs, including clock management circuits and memory interfaces. While the present invention is not so limited, an appreciation of the present invention is presented by way of specific examples. The specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one ordinarily skilled in the art that the present invention can be practiced without these specific details. In other instances, well-known circuits and devices may be omitted or presented in abstract form in order to avoid obscuring the present invention.

FIGS. 1A and 1Bshow a dual edge sampler100and a state diagram150of the dual-edge sampler in accordance with an embodiment of the present invention. As described in greater detail below, sampler100may be implemented as an asynchronous level mode state machine. In some embodiments, part or all of sampler100may include differential logic, such as differential cascode voltage switch logic (DCVSL). Sampler100includes input signals C and D corresponding to clock and data input signals, respectively, and an output signal Q. In some embodiments, complementary or differential clock signals C and C_b may be inputs to sampler100. Sampler100may optionally include a reset input signal R, and may optionally provide an inverted output signal Q_b. Sampler100samples the data input signal D at every clock edge (both rising and falling) of clock input signal C, and provides that sampled data as output Q.

The state machine150of sampler100generally operates as follows. While the logic level of clock input C does not change, sampler100maintains its current state, and thus maintains a constant output state for output signal Q. Upon a level change of clock input C, either from low to high or high to low, data input D is sampled and latched. The new state of output signal Q reflects the latched value of data input D. Sampler100then waits for the next level change in clock input C.

As shown inFIG. 1B, the state machine includes four states. State A corresponds to a state where the output signal Q is a logic low, and sampler100is waiting for a transition from logic low to logic high (e.g., a rising edge) at clock input C. State B corresponds to a state where the output signal Q is a logic high, and sampler100is waiting for a transition from logic high to logic low (e.g., a falling edge) at clock input C. State C corresponds to a state where the output signal Q is a logic low, and sampler100is waiting for a transition from logic high to logic low at clock input C to trigger a state change. State D corresponds to a state where the output signal Q is a logic high, and sampler100is waiting for a transition from logic low to logic high at clock input C. Upon detection of the appropriate transition at clock input C in each of states A–D, sampler100latches the data input D and moves to the appropriate state that has an output signal Q corresponding to the latched data input and that is waiting for an opposite transition at clock input C.

Sampler100may further include a reset input signal R for resetting the state machine. In some embodiments, the reset signal may be an asynchronous reset that forces sampler100to a reset state, such as state A or state C, when the reset signal is asserted. For instance, the reset signal R may reset state machine150to one of state A and state C (both corresponding to a logic log output Q) depending on the logic level of clock input signal C. Thus, state machine150may be reset to the appropriate state such that sampler100will be ready for the next clock edge when the reset signal R is de-asserted or released.

Furthermore, in certain applications, sampler100may be optimized by eliminating transitions denoted by the dashed lines inFIG. 1B. By eliminating the dashed transitions, states B and D can only be exited by asserting the reset signal R. That is, once the state machine enters either state B or D, indicating that a logic high data input signal has been sampled, the optimized sampler stops further sampling until the state machine is reset.

An optimized sampler may be useful, for example, for applications where once sampler100latches a logic high data input (e.g., indicating that a desired event has occurred) future changes in the data input signal may be safely ignored until the state machine is reset. For instance, sampler100may be coupled to a comparator that detects a match between two inputs and asserts a match signal. The match signal may then be sampled by sampler100. Thus, sampler100may stop sampling once a match has been detected. Therefore, the transitions for transitioning from states B and D, where the Q output signal is a logic high, to states A and C, where the Q output signal is a logic low, are not needed, so long as a reset signal is available for resetting the sampler (e.g., to one of states A or C). Another example of an application in which such an optimized sampler may be suitable is described in commonly assigned co-pending U.S. patent application entitled “Counter-Controlled Delay Line” by Alireza S. Kaviani, filed on the date hereof, which is incorporated by reference herein in its entirety. This optimization may result in a more efficient circuit that may occupy less area as will be described below in connection withFIG. 3.

FIG. 2shows a schematic diagram of a dual-edge sampler200in accordance with an embodiment of the present invention. Dual-edge sampler200is an embodiment of sampler100and receives a data input signal D, complementary clock signals C and C_b, and a reset input signal R, and produces complementary output signals Q and Q_b. Dual-edge sampler200is generally an embodiment of state machine150. Dual-edge sampler200includes two differential logic blocks210and230for implementing logic functions, and logic block290for generating next state information.

As shown inFIG. 2, each of differential logic blocks210and230provides a logic function based on differential signals Y1, Y2, and data input D and its complement signal D_b to produce differential intermediate results M and N. Note that Y1pand Y1ncorrespond to the positive and negative portions of differential signal Y1, and Y2pand Y2ncorrespond to the positive and negative portions of differential signal Y2. Differential logic blocks210and230include differential loads250and255. In some embodiments, differential loads250and255may include cross-coupled PMOS transistors251–252and256–257, respectively. Differential logic block210produces intermediate result M and its complement M_b. Intermediate result M may be gated by reset signal R via a NOR gate226to provide gated intermediate result MG_b, and intermediate result M_b may be gated by complement reset signal R_b via a NAND gate225to provide gated intermediate result MG. Signal R_b is the complement of reset signal R, and may be provided by an inverter276. Similarly, intermediate result N_b may be gated by complement reset signal R_b via a NAND gate245to provide gated intermediate result NG. An inverter246may be coupled to intermediate result N provided by differential logic block230in order to balance loading of the outputs. The complement of data input D is signal D_b, which may be provided by an inverter275. Differential logic block210may include NMOS transistors211–220, and differential logic block230may include NMOS transistors231–240, arranged as shown inFIG. 2to provide particular logic functions. Table 1 indicates the logic truth table for the logic functions provided by differential logic blocks210and230.

Gated intermediate result signals MG, MG_b, and NG are provided along with input clock signals C and C_b to logic block290to generate the output signals Q and Q_b and the next state information. The current state of dual-edge sampler200is encoded in the states of signals Y1and Y2. In particular, as shown in Table 2, each combination of Y1 and Y2 values corresponds to one of the four states A–D of state machine150described in connection withFIG. 1B. Furthermore, signal Y2pcorresponds to output signal Q_b, and likewise signal Y2ncorresponds to output signal Q. Input clock signal C_b is the complement of clock signal C, and in some embodiments may be provided by a differential clock source. In other embodiments, the complementary clock signals may be provided by an inverter. Logic block290includes AND gates260–263, NOR gates264–265, NAND gate267, and inverters266and268–270. Notably, the path from clock input C to the complementary outputs Q and Q_b passes through the same number of gates as the path from clock input C_b to outputs Q and Q_b. This means that dual-edge sampler200will have substantially symmetric clock-to-Q propagation delay for both rising and falling clock edges.

Table 2 is a truth table representation of the logic functions provided by logic blocks210,230, and290. In Table 2, the “State” column indicates the corresponding state A–D of state machine150, and the “Current Inputs” columns indicate the current state of sampler200(as indicated by signals Y1pand Y2p), and the values of data input signal D, clock input signal C, and reset signal R. The “Intermediate Result” columns indicate the values of signals M and N that are generated based on the given state and inputs of each row. Finally, the “Next State” columns indicate the next values of signals Y1pand Y2p, thereby indicating the next state transition. Note that the output signal Q corresponds to the Y2n signal (which is the complement of the Y2p signal).

As shown inFIG. 2, differential logic blocks210and230may be implemented as DCVSL blocks. In other embodiments, other forms of logic may be used. In the embodiment illustrated inFIG. 2, differential logic blocks210and230have identical circuit topologies. Similar or identical topologies may be used to implement other types of flip-flops, samplers, and other sequential circuits. Furthermore,FIG. 2shows logic block290implemented using single-ended logic. In other embodiments, logic block290may include differential logic gates. Differential logic may be used to achieve, for instance, better symmetry and higher performance at the possible expense of increased area and complexity. Note that the embodiment of dual-edge sampler200shown inFIG. 2has a positive hold time. In some embodiments, dual-edge sampler200may additionally provide level shifting functionality to shift input signals having a first voltage range to an output signal having a different voltage range. For example, supply voltage280may be at a different voltage than the supply voltage of the circuits providing the inputs to dual-edge sampler200. This allows separate power supplies to be used in different areas of a circuit.

FIG. 3shows schematic diagram of an optimized dual-edge sampler300in accordance with an embodiment of the present invention. As noted above, the logic and circuitry of a dual-edge sampler may be optimized depending on the specific requirements of the application in which it is being used. In particular, optimized dual-edge sampler300corresponds to the state transition diagram ofFIG. 1Bwithout the dashed transitions. Thus, optimized dual-edge sampler300may be reset by reset signal R to one of states A and C (depending on the value of clock input C). In states A and C, the output Q of optimized dual-edge sampler300is a logic low. At each edge of clock input C, the data input D of optimized dual-edge sampler300is sampled. When a logic high is sampled at data input D, optimized dual-edge sampler300transitions to one of states B and D. Thereafter, it remains in states B and D, regardless of the value of data input D, and provides a constant logic high output Q until reset signal R is asserted. As can be seen inFIG. 3, optimizing a dual-edge sampler in this way results in a more efficient circuit that uses less logic and thus requires less area.

Optimized dual-edge sampler300includes differential logic blocks310and330, which include differential loads350and355, respectively. Note that differential logic blocks310and330have reduced complexity when compared to differential logic blocks210and230of dual-edge sampler200. In particular, differential logic block310includes 6 NMOS transistors311–316, and differential logic block330includes 8 NMOS transistors331–338, as compared with 10 NMOS transistors for each of differential logic blocks210and230. Differential logic block310generates an intermediate result M and its complement M_b, and differential logic block330generates an intermediate signal N. Differential logic block330also generates an intermediate signal NR that is logically equivalent to N and may be generated via an inverter340. Signal R_b is the complement of reset signal R, and may be provided by an inverter376. Similarly, the complement of data input D is signal D_b, which may be provided by an inverter375. Table 3 indicates the logic truth table for the logic functions provided by differential logic blocks310and330. Note that Y1pand Y1ncorrespond to the positive and negative portions of differential signal Y1, and Y2pand Y2ncorrespond to the positive and negative portions of differential signal Y2.

Intermediate result signals M, M_b, N, and NR are provided along with input clock signals C and C_b to logic block390to generate the output signals Q and Q_b and the next state information. Similar to dual-edge sampler200, the current state of optimized dual-edge sampler300is encoded in the states of signals Y1and Y2. In particular, as shown in Table 4, each combination of Y1 and Y2 values corresponds to one of the four states A–D of state machine150described in connection withFIG. 1B. Furthermore, signal Y2pcorresponds to output signal Q_b, and likewise signal Y2ncorresponds to output signal Q. Input clock signal C_b is the complement of clock signal C, and in some embodiments may be provided by a differential clock source or by an inverter. Logic block390includes AND gates360–363, NOR gates364–365, NAND gate367, and inverters366,368and369. Note that as with dual-edge sampler200, the path from clock input C to the complementary outputs Q and Q_b is the same as the path from clock input C_b to outputs Q and Q_b for optimized dual-edge sampler300. This means that optimized dual-edge sampler300will also have substantially symmetric clock-to-Q propagation delay for both rising and falling clock edges.

Table 4 is a truth table representation of the logic functions provided by logic blocks310,330, and390. In Table 4, the “State” column indicates the corresponding state A–D (as described in connection with state machine150), and the “Current Inputs” columns indicate the current state of optimized dual-edge sampler300(as indicated by signals Y1pand Y2p), and the values of data input signal D, clock input signal C, and reset signal R. The “Intermediate Result” columns indicate the values of signals M and N that are generated based on the given state and inputs of each row. Finally, the “Next State” columns indicate the next values of signals Y1pand Y2p, thereby indicating the next state transition. As noted above, output signal Q corresponds to the Y2n signal (which is the complement of the Y2p signal).

As shown inFIG. 3, differential logic blocks310and330may be implemented as DCVSL blocks. In other embodiments, other forms of logic may be used.FIG. 3also shows logic block390implemented using single-ended logic. In other embodiments, logic block390may include differential logic. Differential logic may be used to achieve, for instance, better symmetry and higher performance at the possible expense of increased area and complexity. Note that the embodiment of optimized dual-edge sampler300shown inFIG. 3has a positive hold time. In some embodiments, optimized dual-edge sampler300may additionally provide level shifting functionality as described above with respect to dual-edge sampler200.

FIG. 4Ashows a toggle sampler400, andFIG. 4Bshows a corresponding schematic diagram of toggle sampler400in accordance with an embodiment of the present invention. As shown inFIG. 4A, toggle sampler400receives an active low toggle input T_b, a clock input C_b, and provides an output signal Q. In general, toggle sampler400samples input T_b on the falling edges of clock signal C_b, which correspond to rising edges of a complement clock signal C. If the sampled value of T_b is logic low (indicating that the toggle input is being asserted), the output Q is toggled from its current state. That is, if signal T_b is asserted when sampled, then if output signal Q is a logic high, it will switch to a logic low, and if output signal Q is a logic low, it will switch to a logic high. Otherwise, toggle sampler400maintains the current value of Q. Toggle sampler400may also receive a reset signal R for resetting to a known state (e.g., where the output Q is a logic low).

As shown inFIG. 4B, toggle sampler400includes a differential logic block410and a logic block490. Differential logic block410includes NMOS transistors411–420, and a differential load450, which may include cross-coupled PMOS transistors451and452. Differential logic block410generates an intermediate result signal M, and its complement M_b, based on input signals Y1p, Y1n, Y2p, Y2n, T and T_b. Note that signals Y1pand Y1nare positive and negative portions of a differential signal Y1, and that signals Y2pand Y2nare positive and negative portions of a differential signal Y2. Signal T is the complement of toggle input signal T_b, and may be provided by inverter475. Intermediate results M_b and M may be gated by reset signal R (and its complement R_b, which may be provided by inverter476) via NOR gate426and NAND gate425to provide gated intermediate result signals MG and MG_b, respectively. Table 5 indicates the logic truth table for the logic function provided by differential logic block410.

Signals MG, MG_b, Y1pand C_b are provided to logic block490to generate the output signal Q and the next state information. Note that the embodiment shown inFIGS. 4A and 4Bonly require a single clock input C_b, and a complement clock signal C may be generated internally via inverter477. Other embodiments may have different clock signal arrangements. Similar to samplers200and300, the current state of toggle sampler400is encoded in the states of signals Y1and Y2. In particular, as shown in Table 6, each combination of Y1 and Y2 values corresponds to one of four states A–D. The state of signal Y1ncorresponds to the output signal Q, thus as shown in Table 6, states A and C represent states where the output Q is a logic low, and states B and D represent states where the output Q is a logic high. In states A and D, toggle sampler400is waiting for a rising edge of clock signal C_b (i.e., a falling edge of complement clock signal C) to transition to the next state, and in states B and C, toggle sampler400is waiting for a falling edge of clock signal C_b. Logic block490includes AND gates460–463, NOR gates464–465, NAND gate467, and inverters466,468,469,477and478.

Table 6 is a truth table representation of the logic functions provided by logic blocks410and490. In Table 6, the “State” column indicates the corresponding state A–D (as described above with respect to toggle sampler400), and the “Current Inputs” columns indicate the current state of toggle sampler400(as indicated by signals Y1pand Y2p), and the values of data input signal T (which is the complement of clock input T_b), clock input signal C (which is the complement of clock input C_b), and reset signal R. The “Intermediate Result” column indicates the values of signal M that are generated based on the given state and inputs of each row. Finally, the “Next State” columns indicate the next values of signals Y1pand Y2p, thereby indicating the next state transition. As noted above, output signal Q corresponds to the Y1 n signal (which is the complement of the Y1 p signal).

As shown inFIG. 4, differential logic block410may be implemented as a DCVSL block and logic block490may be implemented using single-ended logic. In other embodiments, other forms of logic may be used for one or both of logic blocks410and490. As with samplers200and300, toggle sampler400has a positive hold time. Also as with samplers200and300, in some embodiments, toggle sampler400may additionally provide level shifting functionality by varying the power supply voltage480.

FIG. 5shows a schematic diagram of a sampler500with edge control in accordance with an embodiment of the present invention. Sampler500includes a dual-edge sampler520and edge control logic550. In some embodiments, dual-edge sampler may be implemented as sampler200or sampler300. Edge control logic550provides logic for gating a data input signal DIN with either a clock input CLK or its complement CLK_B, depending on the value of control signal EDGECTL. The gated data input is provided to the D input of dual-edge sampler520. Clock signals CLK and CLK_B are also provided to the C and C_b clock inputs, respectively, of dual-edge sampler520.

By gating the data input DIN, a programmable D flip-flop is formed where the EDGECTL control signal determines whether sampler500acts as a rising edge-triggered flip-flop or a falling edge-triggered flip-flop. In particular, when EDGECTL is a logic low, sampler500acts as a rising edge-triggered flip-flop that samples data input DIN on rising edges of clock input CLK (and corresponding falling edges of clock input CLK_B). Conversely, when EDGECTL is a logic high, sampler500acts as a falling edge-triggered flip-flop that samples data input DIN on falling edges of clock input CLK (and rising edges of clock input CLK_B). Thus, dual-edge sampler520coupled with edge control logic550forms a programmable sampler. In some embodiments, EDGECTL may be provided from a memory cell, such as a configuration memory cell of a programmable logic device, from an output of another circuit, or from any internal or external signal.

Edge control logic550includes an inverter513with signal EDGECTL coupled as its input and an output that drives an input of a NAND gate510. Clock signal CLK_B and data input signal DIN are also provided as inputs to NAND gate510. Edge control logic550further includes a NAND gate511having control signal EDGECTL, clock signal CLK, and data input signal DIN as inputs. The outputs of NAND gates510and511drive inputs of a NAND gate512, and the output of NAND gate512drives the D input of dual-edge sampler520.

FIG. 6shows a schematic diagram of an integrated circuit600including samplers in accordance with an embodiment of the present invention. Integrated circuit600includes a sampler500having edge control, a dual-edge sampler100, circuits610and620, and memory cell630. A data signal DATA1is coupled to sampler500to provide a data stream. Memory cell630stores a memory bit that is provided to edge control logic550of sampler500to configure sampler500for operation as either a rising or falling edge-triggered flip-flop. A clock signal CLK1, which may be a differential clock, is also provided to sampler500. An output of sampler500may be provided to a circuit610for further processing.

A second data signal DATA2, which may be a DDR data stream, is provided to the data input of dual-edge sampler100. Sampler100also receives a clock signal CLK2, which may be a differential clock. Note that samplers100and520are shown inFIG. 6with only one clock input for simplicity. In general, the clock inputs to the samplers may be single-ended or differential, and may therefore include one or more input terminals. The output Q of dual-edge sampler100may be provided to a circuit620for further processing. Although signals DATA1, CLK1, DATA2, and CLK2of integrated circuit600are shown as internal signals, it is to be understood that one or more of the signals may be provided by an external source. Similarly, one or both of circuits610and620may be external to integrated circuit600. In general, integrated circuit may be any device where samplers may be useful. In some embodiments, integrated circuit600may be a programmable device, such as an integrated circuit having programmable logic fabric, or a programmable logic device. One example of a programmable logic device is a field programmable gate array (FPGA). In such embodiments, memory cell630may be part of a configuration memory arrangement, and circuits610and620may include programmable logic.

Those having ordinary skill in the relevant arts of the invention will now perceive various modifications and additions that can be made as a result of the disclosure herein. For example, although certain circuits are described above as differential circuits, single-ended circuits having the same or similar functions may be substituted for those circuits, and vice versa.

Furthermore, capacitors, transistors, level shifters, PMOS transistors, NMOS transistors, and other components other than those described herein may be used to implement the invention. Active-high signals can be replaced with active-low signals by making straightforward alterations to the circuitry, such as are well known in the art of circuit design. Logic circuits can be replaced by their logical equivalents, as is also well known.

Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection establishes some desired electrical communication between two or more circuit nodes. Such communication can often be accomplished using a number of circuit configurations, as will be understood by those of ordinary skill in the art.

Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is defined only by the appended claims and their equivalents.