Method of forming semiconductor device

A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method of forming an integrated circuit, and more generally to a method of forming a semiconductor device.

2. Description of Related Art

In the field of integrated circuit devices, the dimensions of devices are often reduced to attain a higher operating speed and a lower power consumption. However, with the ever-increasing level of integration of devices, the miniaturization of devices has almost reached its limit. Strain engineering is one of the promising approaches to circumvent the scaling limit.

A method for strain control is utilizing materials having an identical crystal structure but different lattice constants to achieve the purpose of controlling the strain. If a transistor is an N-type transistor, implanted strain atoms are carbon atoms and formed into an epitaxial structure of silicon carbide (SiC). Since the lattice constant of carbon atoms is usually smaller than that of silicon atoms, if SiC is embedded in source and drain regions, a tensile stress can be generated in the channel to enhance the mobility of electrons so that the driving current of the device is increased. If a transistor is a P-type transistor, implanted strain atoms are germanium atoms and formed into an epitaxial structure of silicon germanium (SiGe). A compression stress can be generated in the channel to enhance the mobility of holes.

Therefore, controlling the strain in the channel region of a transistor is indeed a proposed solution to overcome the limitation imposed by the device miniaturization. However, it has been challenging to integrate the strain engineering into the existing CMOS process.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a method of forming a semiconductor structure, which successfully integrates the strain engineering into the existing CMOS process.

The present invention provides a method of forming a semiconductor device. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

In view of the above, when forming a disposable dual-spacer structure, the present invention adopts two deposition processes and two etching processes performed alternatively, so that each of the disposable double spacers of the invention is formed with an I-shape. The outer I-shaped disposable spacer (i.e. second disposable spacer) protects the inner I-shaped disposable spacer (i.e. first disposable spacer) from being damaged during the recess forming/enlarging step, so that undercuts at bottoms of the disposable spacers are not observed, and thus the process window and therefore the device performance are effectively improved.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A to 1Fare schematic cross-sectional views illustrating a method of forming a semiconductor structure according to an embodiment of the present invention.

Referring toFIG. 1A, at least one gate structure110is provided on a substrate100. The substrate100can be a semiconductor substrate, such as a silicon substrate. The gate structure110includes an interfacial layer102, a gate104and a cap layer106sequentially formed on the substrate100. The interfacial layer102includes silicon oxide, silicon oxynitride, a high-k material with a dielectric constant greater than 4, or a combination thereof. The high-k material can be metal oxide, such as rare earth metal oxide. The high-k material can be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate, (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1−xO3, PZT), and barium strontium titanate (BaxSr1−xTiO3, BST), wherein x is between 0 and 1. The gate104includes amorphous silicon, polysilicon, doped polysilicon or silicon-containing material such as SiGe. The cap layer106includes silicon nitride or a combination of silicon oxide and silicon nitride. In this embodiment, the gate structure110further includes a first spacer108formed on the sidewall of the gate104. The first spacer108includes silicon nitride.

The embodiment ofFIG. 1Ain which each of the interfacial layer102and the cap layer106is illustrated as a single layer is provided for illustration purposes and is not construed as limiting the invention. It should be appreciated by persons having ordinary skill in the art that each of the interfacial layer102and the cap layer106can be a composite layer or a multi-layer structure upon the process requirements.

The method of forming the gate structure110includes forming an interfacial material layer, a gate material layer and a cap material layer (not shown) sequentially on the substrate100, patterning the said layers to form at least one stacked structure, forming a first spacer material layer (not shown) on the substrate100covering the stacked structure, and performing an anisotropic etching process to etched the first spacer material layer.

In an embodiment, for a polysilicon gate process, the gate structure110may include a silicon oxide layer or a silicon oxynitride layer as an interfacial layer (or called a gate dielectric layer), a polysilicon layer as a gate and a silicon nitride layer as a cap layer.

In another embodiment, for a metal gate (high-k first) process, the gate structure110may include a composite layer (containing a lower silicon oxide layer and an upper high-k layer) as an interfacial layer, a polysilicon layer as a dummy gate and a silicon nitride layer as a cap layer. In addition, a barrier layer (not shown) is further disposed between the high-k layer and the polysilicon layer. The barrier layer includes TiN.

In yet another embodiment, for a metal gate (high-k last) process, the gate structure110may include a silicon oxide layer as an interfacial layer, a polysilicon layer as a dummy gate and a silicon nitride layer as a cap layer.

After forming the first spacer108, two lightly doped regions (not shown inFIG. 1A) are optionally formed in the substrate100beside the gate structure110by using the first spacer108as a mask. Or in another embodiment of the present invention, these two lightly doped regions are formed afterward.

Continue referring toFIG. 1A, a first disposable spacer material layer112is deposited on the substrate100covering the gate structure110. The first disposable spacer material layer112includes silicon oxide and can be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or a sputter deposition process.

Referring toFIG. 1B, the first disposable spacer material layer112is etched to form a first disposable spacer112aon the first spacer108. The method of etching the first disposable spacer material layer112includes performing an anisotropic dry etching process.

Afterwards, a second disposable spacer material layer114is deposited on the substrate100covering the gate structure110. The second disposable spacer material layer114includes silicon nitride and can be formed by an ALD process, a CVD process, a PVD process or a sputter deposition process.

Referring toFIG. 1C, the second disposable spacer material layer114is etched to form a second disposable spacer114aon the first disposable spacer112a. The method of etching the second disposable spacer material layer114includes performing an anisotropic dry etching process.

Thereafter, a portion of the substrate100is removed, by using the first and second disposable spacers112aand114aas a mask, so as to form two recesses116in the substrate100beside the gate structure110. In this embodiment, one recess116is formed in the substrate100between the adjacent gate structures110. The method of removing the portion of the substrate100includes performing a dry etching process and/or a wet etching process.

Referring toFIG. 1D, a middle width W2of a middle portion of each recess116is optionally enlarged through said etching process. The said etching process can use a dry etching step to form vertical sidewall of the recess116as shown inFIG. 1Cand use a wet etching step to enlarge the middle portion of the recess116. Specifically, each recess116has a middle width W2of the middle portion thereof between the top thereof and the bottom thereof, and the middle width W2is the maximum width of the recess116. In an embodiment, the top width W1is close to, or even substantially equal to, the bottom width W3of each recess116. In another embodiment, the top width W1can be different from the bottom width W3of each recess116.

It is noted that the conventional undercuts are not observed in areas A (marked as dotted lines inFIG. 1D) after the recess forming step and/or the recess enlarging step. Specifically, the conventional disposable dual-spacer structure is fabricated with two successive deposition processes and followed by one etching process. Thus, the inner disposable spacer adjacent to the gate structure has an L-shape, a vertical portion thereof covers the sidewall of the gate structure, and a lateral portion thereof extends from the bottom of the vertical portion over the substrate. However, one side of the lateral portion of the L-shaped inner disposable spacer is exposed after the etching process. Under such circumstance, during the subsequent recess forming step and/or the recess enlarging step, the etching gas or etchant permeates, through the exposed side, into the lateral portion of each L-shaped inner disposable spacer and therefore creates undercuts at areas A. Hence, the subsequently formed stress-inducing layer may be grown and extended into the undercuts, thereby causing leakage and device degradation.

On the other side, in the present invention, the disposable dual-spacer structure including the first and second disposable spacers112aand114ais fabricated with two deposition processes and two etching processes alternatively performed. Therefore, each of the first and second disposable spacers112aand114ais formed with an I-shape, and the outer second disposable spacer114acovers the inner first disposable spacer112aand protects the inner first disposable spacer112afrom being damaged by the etching gas or etchant used in the recess forming/enlarging step.

Referring toFIG. 1E, a stress-inducing layer118is formed in the recesses116. The stress-inducing layer118includes silicon carbide (SiC) or silicon germanium (SiGe), and the forming method thereof includes performing a selective epitaxy growth (SEG) process. In an embodiment, the surface of the stress-inducing layer118is higher than the surface of the substrate100, as shown inFIG. 1E. In another embodiment (not shown), the surface of the stress-inducing layer118can be substantially coplanar with the surface of the substrate100. Herein, since the conventional undercuts are not observed at bottoms of the first and second disposable spacers112aand114a, the stress-inducing layer118is formed without extending into the first and second disposable spacers112aand114a, and thus, leakage does not occur and the device performance is improved.

Referring toFIG. 1F, the first and second disposable spacers112aand114aare removed through an etching process. Thereafter, two lightly doped regions120are formed in the substrate100beside the gate structure110by using the first spacer108as a mask if these two lightly doped regions are not formed right after forming of the first spacer108. In this embodiment, two lightly doped regions120are formed in a portion of the substrate100and in a portion of the stress-inducing layer118between the adjacent gate structures110. The method of forming the lightly doped regions120includes performing an ion implantation process. When manufacturing an N-type transistor, the ion utilized is an N-type dopant such as phosphorous or arsenic. When manufacturing a P-type transistor, the ion utilized is a P-type dopant such as boron or boron fluoride.

Afterwards, a second spacer122is formed on the first spacer108. In an embodiment, the second spacer120can be a dual-spacer structure including an L-shaped inner spacer layer121on the first spacer108and an outer spacer layer123on the L-shaped inner layer121. The L-shaped inner spacer layer121includes a vertical portion covering the sidewall of the gate structure110, and a lateral portion extending from the bottom of the vertical portion over the substrate100. The L-shaped inner spacer layer121includes silicon oxide and the outer spacer layer123includes silicon nitride. The method of forming the second spacer122includes sequentially depositing a silicon oxide layer and a silicon nitride layer on the substrate100covering the gate structure110, and then performing an anisotropic dry etching step to remove a portion of the silicon oxide layer and a portion of the silicon nitride layer.

Then, two heavily doped regions124are formed in the stress-inducing layer118beside the gate structure110by using the second spacer122as a mask. The method of forming the heavily doped regions124includes performing an ion implantation process. In this embodiment, one heavily doped region124is formed in the substrate100(or in the stress-inducing layer118) between the adjacent gate structures110. When manufacturing an N-type transistor, the ion utilized is an N-type dopant such as phosphorous or arsenic. When manufacturing a P-type transistor, the ion utilized is a P-type dopant such as boron or boron fluoride.

In an embodiment, for a polysilicon gate process, the following process steps after forming the heavily doped regions124include forming contact plugs, forming interconnection metals etc. (not shown), which are well-known to persons having ordinary skill in the art and are not iterated herein.

In another embodiment, for a metal gate (high-k first) process, the following process steps after forming the heavily doped regions124include forming a dielectric layer (not shown) which exposes the top of each gate structure110on the substrate100, removing the cap layer106and the dummy gate104to form openings in the dielectric layer, and filling a composite metal layer including a work function metal layer (e.g. TiAl or TiN) and a low-resistivity metal layer (e.g. Al or Cu) in the openings. These steps are well-known to persons having ordinary skill in the art and are not iterated herein.

In yet another embodiment, for a metal gate (high-k last) process, the following process steps after forming the heavily doped regions124include forming a dielectric layer (not shown) which exposes the top of each gate structure110on the substrate100, removing the cap layer106, the dummy gate104and the interfacial layer102to form openings in the dielectric layer, and filling a gate dielectric layer (e.g. silicon oxide), a high-k layer (e.g. HfO2), a barrier layer (e.g. TiN) and a composite metal layer including a work function metal layer (e.g. TiAl or TiN) and a low-resistivity metal layer (e.g. Al or Cu) in the openings. These steps are well-known to persons having ordinary skill in the art and are not iterated herein.

In summary, when forming a disposable dual-spacer structure, the present invention adopts two deposition processes and two etching processes performed alternatively to replace the conventional two successive deposition processes and followed by one etching process. Therefore, each of the disposable double spacers of the invention is formed to have an I-shape rather than an L-shape. The outer I-shaped disposable spacer (i.e. second disposable spacer) protects the inner I-shaped disposable spacer (i.e. first disposable spacer) from being damaged during the recess forming/enlarging step, so that undercuts at bottoms of the disposable spacers are not observed, and thus the process window and therefore the device performance are effectively improved. Besides, with the method of the invention, it is easy to integate the strain engineering into the existing CMOS process, thereby achieving competitive advantages over competitors.

The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.