Method, apparatus, and system for an architecture for machine learning acceleration

A method, apparatus, and system for an architecture for machine learning acceleration is presented. An apparatus includes a plurality of processing elements, each including a tightly-coupled memory, and a memory system coupled to the processing elements. A global synchronization manager is coupled to the plurality of the processing elements and to the memory system. The processing elements do not implement a coherency protocol with respect to the memory system. The processing elements implement direct memory access with respect to the memory system, and the global synchronization manager is configured to synchronize operations of the plurality of processing elements through the TCMs.

BACKGROUND

Artificial Neural Networks (ANNs) are used to perform an increasing number and variety of tasks, such as, for example, object recognition, speech recognition, speech generation, providing recommendations, and predicting user behavior. Performing these tasks may be referred to as inferencing using an ANN model. To provide useful inferences, an ANN model needs to be designed and trained for the particular task. The ANN design establishes parameters such as the number of layers of the ANN model and the characteristics of each layer. The training of the ANN uses training data, inferencing using the ANN model, feedback based on evaluation of the inference, and backpropagation to adjust the weights of the ANN model in response to the feedback. After numerous training cycles of inferencing and backpropagation, the resultant model may provide satisfactory results in response to new input data. Note that many ANNs have multiple hidden layers between an input layer and an output layer and may consequently be referred to as Deep Neural Networks (DNNs).

To provide a satisfactory user experience, not only do the inference results need to be correct, but they also need to be provided fairly quickly—often within a fraction of a second (response latency within service level agreement). To do this, service providers use large arrays of inference accelerators located “in the cloud”—that is, communicatively coupled to, and located remotely from, a client device.

Client computer devices may include, for example, computers, automobiles, smartphones, smart wearable devices, and internet-of-things (IoT) devices. The so-called cloud may comprise a plurality of interconnected servers located at a data center and may be managed by a cloud provider entity such as, for example, Amazon.com, Inc. of Seattle, Wash. or Facebook, Inc., of Menlo Park, Calif. Each host server comprises a plurality of interconnected inference accelerators, which may be provided by an inference-accelerator provider entity. Each accelerator comprises processor and memory components.

The cloud may support many millions of neural network applications. A neural network application running on a client computer device communicates with the cloud to receive inference acceleration and/or assistance. For example, a speech-translation neural-network application (NNA) may transmit a raw or encoded audio snippet to the cloud for rapid translation and provision of the translation in response to the NNA. A media-recommendation program that recommends, e.g., songs or video—where the media may comprise many millions, or even billions, of options hosted by the cloud provider in the cloud—may communicate with the cloud to have the cloud perform an inference to generate a recommendation for provision to a user of the client computer device.

In the data center context, various heterogenous architectures have been employed to handle machine learning workloads. For example, cloud compute may use server-class central processing units (CPUs) or graphics processing units (GPUs) and may adapt their workloads to those architecture. However, these architectures may not be tailored to the specific characteristics of machine learning algorithms, with the effect that their performance is not as efficient as desired, and/or they consume more power to achieve a given level of performance than would be desirable. As there may be many millions of NNAs accessing the inference accelerators of the cloud at any one time, efficient inference accelerators would be beneficial for reducing power usage and/or reducing inference time.

Thus, it would be desirable to provide an inference-accelerator computing architecture that is scalable to cloud computing and data center application, while providing improved performance per watt when compared to existing server-class CPU and GPU-based solutions.

SUMMARY OF THE DISCLOSURE

In one aspect, an apparatus includes a plurality of processing elements, each including a tightly-coupled memory (TCM), and a memory system coupled to the processing elements. A global synchronization manager is coupled to the plurality of the processing elements and to the memory system. The processing elements do not implement a coherency protocol with respect to the memory system. The processing elements implement direct memory access with respect to the memory system, and the global synchronization manager is configured to synchronize operations of the plurality of processing elements through the TCMs.

In another aspect, an apparatus includes a plurality of processing elements and a first network coupling each processing elements of the plurality of processing elements to the other processing elements of the processing elements, the first network configured to perform multicast operations. The apparatus further includes a memory system and a second network, separate from the first network, coupling each processing element of the plurality of processing elements to the other processing elements of the plurality of processing elements and to the memory system.

In yet another aspect, a method comprises transforming a neural network into a directed acyclic graph by a compiler and transforming the directed acyclic graph into computation and/or data movement operations by the compiler. The method further comprises statically scheduling the computation and/or data movement operations for execution in parallel pipelines by the compiler. The computation and/or data movement operations may be dispatched in a plurality of portions in accordance with dispatch scaling.

Some advantages of the disclosed aspects may include providing a scalable architecture for cloud computing that provides improved interconnection between processing elements, and a compiler that produces a more efficient mapping of neural network operations onto available hardware.

DETAILED DESCRIPTION

FIG. 1is a simplified schematic diagram of an exemplary inference accelerator100in accordance with an embodiment of the disclosure. The inference accelerator100comprises a system-on-chip (SoC)190coupled to a first double data rate (DDR) dynamic random-access memory (DRAM)122and a second DDR DRAM126. The SoC190comprises a first processing element102, a second processing element104, a third processing element106, and a fourth processing element108. The processing elements102,104,106, and108are coupled together via a compute network-on-chip (NoC)142. Note that the terms “NoC” and “network” may be used interchangeably herein. Note that inference accelerators in accordance with this disclosure are not limited to any particular number of processing elements and alternative implementations may have more or fewer than four processing elements.

The SoC190further comprises a first memory interface112, a second memory interface114, a third memory interface116, a fourth memory interface118, and a PCI Express (PCIe) block134, all coupled to each other and to the processing elements102,104,106, and108via a system/memory (sys/mem) NoC144. The PCIe block134is an interface used by the inference accelerator100to receive the inputs for inferences (e.g., images, videos, audio clips, or other data tensors) received by the host server and to provide results back to the host server. The system-on-chip190further comprises a management controller132, which is coupled to the PCIe block134, the memory controllers112,114,116, and118, and the processing elements102,104,106, and108via the system/memory NoC144. Note that, in some implementations, the compute network142may also connect to the PCIe block134and/or the memory controllers112,114,116, and118.

Further, a global synchronization manager (GSM) module136is coupled to the PCIe block134and a local sync manager (seeFIG. 1A) in each processing element102,104,106, and108via a private NoC146. It should be noted that in alternative implementations, one or more of the compute NoC142, sys/mem NoC, and private NoC146may be replaced by a corresponding simple bus, or other communication fabric, other than a NoC. It should also be noted that in some alternative embodiments, the compute NoC and sys/mem NoC may be combined into a single combined compute/system/memory NoC. It should be further noted that some alternative implementations of the inference accelerator100do not include a private NoC and, instead, the GSM136communicates with other elements (e.g., the processing elements102,104,106, and108) via other means (e.g., sys/mem NoC144).

The processing elements102,104,106, and108may be neural processing units (NPUs), neural signal processors (NSPs), digital signal processors (DSPs), or any other suitable type of processor (e.g., CPUs or GPUs). In some homogenous embodiments (where the processing elements102,104,106, and108are substantially the same) each of the processing elements102,104,106, and108may include scalar, vector, matrix processing capabilities (e.g., multiplication, convolution, point-wise addition, point-wise multiplication), and data-movement capabilities (e.g., load, store, and direct memory access (DMA)). In some alternative embodiments, the scalar, vector, matrix, and data-movement processing capabilities may be distributed across different processing elements (in other words, the processing elements102,104,106, and108may be heterogeneous). Additionally, whichever of the processing elements102,104,106, and108provide matrix processing capabilities may further include floating point capabilities as part of the matrix processing capabilities. Providing these capabilities in each of the processing elements102,104,106, and108may enable a compiler for the inference accelerator100to more efficiently schedule code on the individual processing elements, as will be explained in greater detail with respect toFIG. 2.

FIG. 1Ais a simplified schematic diagram of an exemplary implementation of the processing element102ofFIG. 1. As noted above, in some embodiments, processing elements104,106, and108may be configured identically. The processing element102comprises tightly-coupled memory (TCM)150, vector processing module151, matrix processing module152, scalar processing (e.g., DSP) module153, memory processing module154, and an optional local synchronization manager (LSM)155. The TCM150is directly connected to at least the vector processing module151, the matrix processing module152, and the memory processing module154. The LSM155is directly connected to at least the scalar processing module153. The processing element102is connected to NoCs142,144, and146.

In some implementations, each LSM155of a processing element is connected to the GSM136ofFIG. 1, where the processing elements102,104,106, and108implement hardware memory synchronization using LSM155working with GSM136to coordinate and synchronize data transfers among the processing elements102,104,106, and108and the DRAMs122and126, by setting and resetting semaphores that allow or prohibit corresponding data operations. In this implementation, the LSM155may be referred to as a synchronization module. In some implementations, the GSM136works directly with the TCMs150of the processing elements102,104,106, and108(forgoing LSMs155) to set and reset values at known locations in the TCMs150, where those values similarly allow or prohibit corresponding data operations. In this implementation, the TCM150may be referred to as a synchronization module.

The processing element102may forgo implementing a memory coherency protocol. Implementing a memory coherency protocol typically includes having a shared cache connected to a plurality of clients and an interconnecting bus with a coherency protocol to ensure that each client is referencing the latest version of corresponding data. Using caches and implementing a coherency protocol are useful when data movement and sharing is not sequential and not deterministic—in other words, what is conventionally referred to as “random.” Caches and coherency are also useful where data movements and sharing are relatively fine-grained. Semaphores, on the other hand, use the setting and modifying of so-called semaphores to gate data movement among a plurality of clients and gate computations involving the data—without using a cache or a bus implementing a coherency protocol. Neural-network inferencing involves large movements of data, and calculations based on that data, whose pattern is known ahead of time. Consequently, the integrity of that data may be maintained using a relatively simple semaphore mechanism. Since implementing memory coherency protocols requires relatively significant power levels, substituting hardware synchronization for coherency allows the inference accelerator100to maintain the needed level of memory synchronization at a relatively reduced power level.

Returning toFIG. 1, the compute network142coupling the processing elements102,104,106, and108may be a relatively higher-bandwidth network (as compared to the sys/mem network144and the private network146), and may support multicast operations (i.e., sending data produced by a single processing element to multiple other processing elements of the inference accelerator100). The processing elements102,104,106, and108may each include tightly-coupled memory (e.g. TCM150ofFIG. 1A), and may interact with the first DRAM122and the second DRAM126via the sys/mem network144and the memory controllers112,114,116, and118. Both the compute network142and the sys/mem network144may support DMA operations from the TCMs (e.g. TCM150) of each of the processing elements102,104,106, and108, including read operations, write operations, and, in the case of the compute network142, multicast operations.

The private network146may be a relatively slower and lower-bandwidth network (as compared to the compute network142and the sys/mem network144), as its use may be limited to a configuration time (as opposed to run time) and, thus, would not have a specific performance requirement (as opposed to the compute network142and the sys/mem network144). Having separate networks for these specific purposes allows each of the networks to be designed to match its corresponding expected traffic type and allows each to be individually performance and power optimized to match.

For example, since the workloads handled by the inference accelerator100may often involve data words that are all zeros (but that must still be transmitted among the processing elements102,104,106, and108), the compute network142may implement a “zero” encoding protocol, where setting a single override bit on the network bus indicates that the value of the corresponding data word is zero, without having to actually set all the bits of the data bus for that data word to zero or read all of the corresponding bits of the data word. This may reduce power usage both directly and by allowing for the implementation of power-saving operations based on the override bit.

Further, as indicated above, the inference accelerator100does not implement a memory coherency protocol, instead managing dependencies that do occur using hardware semaphores and compiler design (as explained later with respect toFIG. 2) in accordance with the global sync manager136, which is configured to interact with the processing elements102,104,106, and108to provide hardware semaphore support. Essentially, each of the processing elements102,104,106, and108may set semaphores in the global sync manager136, which may be cleared by the other processing elements102,104,106, and108to allow for interdependencies in workloads being processing by the processing elements102,104,106, and108.

The latency involved in communications between the processing elements102,104,106, and108and the global sync manager136may be important for the overall performance of the inference accelerator100. Thus, the topology of the private network146providing connectivity between the global sync manager136and the processing elements102,104,106, and108may depend on the relative number of processing elements that will be coupled to the global sync manager136. In systems with relatively few processing elements, a ring topology may be used instead of the network146shown. In systems with larger numbers of processing elements, a star topology may be used. Those having skill in the art will recognize that the choice of topology may be informed by many factors involved in the overall system design, and the teachings of the present disclosure do not depend on the use of a particular topology.

FIG. 2is a hybrid schematic and flow diagram200for exemplary operation of a compiler which may be configured to schedule operations on inference accelerator100ofFIG. 1. A neural network description210is provided to the compiler, which, in a first phase, transforms, in step220, the neural network description210into a form that may be represented by directed acyclic graph230. A directed acyclic graph is a graph that has forward progress, without loopbacks, among its nodes (e.g., a tree structure progressing from the trunk to the leaves). The graph230comprises a plurality of tasks represented by graph nodes231,232,233,234,235,236, and237. Graph230shows that task231must be performed first, and then task232, but then any of tasks233,234, and235may be performed. In addition, graph230shows that both tasks234and235have to be completed before task236can be executed (in other words, task236is dependent on tasks234and235). Similarly, task237is dependent on tasks233and236.

In a second phase, in step240, the compiler converts the tasks231-237, shown in graph230, into command lists252,254,256, and258and schedules them for processing on corresponding hardware processing elements such as scalar, vector, matrix, and data movement blocks of the processing elements102,104,106, and108ofFIG. 1. In other words, command lists252,254,256, and258may correspond, respectively, to vector processing module151, matrix processing module152, scalar processing module153, and memory processing module154ofFIG. 1A. The scheduling may be optimized for factors such as, for example, time, power, or resource requirements.

The compiler may be optimized for use with neural networks, and thus it may generate “static” workloads. Specifically, since branching and iteration counts may be known ahead of time, they may be used to generate static workloads, as opposed to, for example, conventional CPU or GPU code, which may have unpredictable branching behavior and iteration counts and, consequently, would require generating dynamic workloads. Because these workloads are static, the command lists generated by the compiler may permit workload balancing in the computing device100by dispatching a portion of a total workload to be executed to the computing device100after which the computing device100may wait (and may possibly even enter a low-power state) for further instructions. This workload distribution and balancing is referred to herein as “dispatch scaling.” Note that, in generating parallel workloads, the compiler may direct the replication of data sets between processing elements, where the replication may be performed using the multicast capabilities of the compute network142.

The above is possible because, since the workload is static, dispatching one-fourth of a total workload (e.g., one fourth of the total operations), for example, will result in the one-fourth of the total workload being completed. This contrasts with a conventional CPU/GPU workload, in which it may be essentially impossible to predict ahead of time how much of a total workload may be completed by providing one-fourth of the workload to the computing device, and thus, in order to save power, conventional methods such a frequency and voltage scaling may be used. Further, instead of generating command lists, which would conventionally be interpreted by software running on the processing elements102,104,106, and108, the compiler may alternatively generate static code which is executed in sequence. Dispatch scaling may be used in either case (command lists or statically generated code).

Although the compiler attempts to generate command lists that are fully parallelizable and do not have interdependencies, sometimes this may not be feasible. In cases where interdependencies exist, since the computing device100does not implement coherency, the compiler will insert a synchronization indicator (e.g., a semaphore) that is mapped to a hardware semaphore resource. Different processing elements may interact, via, e.g., GSM136, using the semaphore to guarantee that dependencies are satisfied. The compiler may schedule tasks to command lists based on optimistic estimated completion times and the semaphores may be relied on to guarantee that dependencies are satisfied where actual completion times exceed the estimated completion times.

The aspects disclosed herein may be embodied in hardware and in instructions or design data that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. In the case of design data, the data may be an electronic representation of a physical design of a circuit, may be readable by integrated circuit fabrication equipment, and may be in a file format such as GDSII, GERBER, or the like. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.