An interconnection structure is disposed between a first conductive layer and a second conductive layer substantially parallel to each other. The conductive layer includes a signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the two conductive layers and is electrically connected to the signal trace of the first conductive layer. The shielding wall pillar is also disposed between the two conductive layers and located at a portion of an external region surrounding the conductor pillar and electrically coupled to the conductor pillar. The conductor pillar and the shielding wall pillar are disposed in pair or in group. The shielding wall pillar with a shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the special shape design thereof.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 100102523, filed Jan. 24, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The disclosure generally relates to an interconnection structure, an apparatus with the interconnection structure, and a method to prevent an interconnection structure from electromagnetic interference (EMI).

BACKGROUND

Currently, a via on a substrate plays a role of providing a vertical path between interconnections. Under a low frequency operation, the paths formed by the vias are not very necessary to control the impedance thereof since the dimension of the via is really quite small (for example, <0.1λ) relatively to the wavelength (λ) of low operation frequency. At the time, the vias can be respectively treated as a simple electrical connection point, the length of the via can be neglected and it affects the circuit inconsiderably.

When the operation frequency is increased however, the physical dimension of a via is near to the wavelength of the operation frequency (for example, 1λ. At the time, the via should be treated as an additional component for a circuit. Hence, the additional via component in the circuit needs to be designed and under control so that the circuit can normally function.

A traditional via connects one terminal only, so that a return path must be designed to accomplish the signal transmission. As a result, during the traditional via is fulfilling a signal transmission, at least two vias are often needed, wherein one is signal via and another is ground via and/or power via. The second via is for providing a return path and solving the problem related to signal transmission integrity, as shown inFIGS. 1A and 1B.

InFIG. 1A, for example, a printed circuit board (PCB) with four layers includes two up and down signal layers120and150and a ground layer130and a power layer140both located between the two layers120and150. A signal via110is disposed between the up signal layer120and the down signal layer150. InFIG. 1A, a current path102from a source to a load and a current return path104are shown. In order to improve the signal transmission integrity, at least two vias are often designed as shown byFIG. 1B, in which one is signal via110and another is ground via and/or power via. In the example, the return path is implemented by a ground via160. With the above-mentioned design, the length of the return path can be reduced and the signal integrity can be improved. In fact, the return path needs to be figured out with an effective design so as to achieve the design requirement of impedance match and reducing EMI.

SUMMARY

In an exemplary embodiment, an interconnection structure is introduced, which is disposed between a first conductive layer and a second conductive layer, in which the first conductive layer and the second conductive layer are substantially parallel to each other. The first conductive layer and the second conductive layer respectively include a first signal trace and a second signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the first conductive layer and the second conductive layer and is electrically connected to the first signal trace and the second signal trace. The shielding wall pillar is disposed between the first conductive layer and the second conductive layer and electrically connected to a reference conductive wire, in which the shielding wall pillar is located at a portion of an external region surrounding the conductor pillar between the first conductive layer and the second conductive layer and electrically coupled to the conductor pillar.

In an exemplary embodiment, a circuit structure is introduced, which includes a first conductive layer, a second conductive layer, a reference conductive wire, a conductor pillar and a shielding wall pillar. The first conductive layer includes a first signal trace. The second conductive layer includes a second signal trace, in which the second conductive layer is substantially parallel to the first conductive layer. The reference conductive wire is located between the first conductive layer and the second conductive layer. The conductor pillar goes through between the first conductive layer and the second conductive layer and is connected to the first signal trace of the first conductive layer and the second signal trace, but electrically isolated from the reference conductive wire. The shielding wall pillar is disposed between the first conductive layer and the second conductive layer and electrically connected to the reference conductive wire, in which the shielding wall pillar is located at a portion of an external region surrounding the conductor pillar between the first conductive layer and the second conductive layer and electrically coupled to the conductor pillar.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

Currently, the signal transmission on a substrate needs a corresponding return path. Hence, a signal via and a ground via and/or a power via are required during vertically transmitting a signal. Since a signal trace has a corresponding ground plane near to the trace and the distance between the ground plane and the signal trace is fixed, so that the required impedance control can be achieved.

When the signal has been transmitted to a signal via however, since no another corresponding vertical ground terminal or ground path to control the signal flowing through the signal via, so that the signal flowing the via has no nearby and directly available ground terminal or ground path, which makes impedance match failed. The problem would further cause various signal integrity troubles including reflection, EMI, discontinuity, crosstalk, etc. Even a ground via is located near by the signal via by design, there still is penetration of partial leakage field so as to cause the EMI problem, and the phenomena are specially serious when the substrate has a medium with low insulation property, for example, a silicon interposer substrate.

Referring toFIGS. 2A-2C, the diagrams illustrate a via structure and the signal integrity thereof. A signal trace210is connected to a signal via212and there is, for example, a ground via220at a side of the signal via212. According to a common design, the ground via has a fixed diameter or dimension to achieve the goal of reducing the current return path. However, in the prior art, the cross-sectional shapes of a signal via, a power via and a ground via are all circle shapes, so that it is unable to avoid random flux or dispersion of electrical field, and the phenomenon is one of disaster sources triggering the EMI effect. As shown byFIG. 2A, in addition to coupled electrical field lines214(for example, marked with solid lines), there are also other penetrating or scramble electrical field lines216(for example, marked with dotted lines) between the signal via212and the ground via220, which causes the dispersion of electrical field. The penetrating of the partial leakage field causes the EMI problem, which further leads to a noticeable distributed electrical field at a region230at the right side of the ground via220, as shown byFIG. 2B.FIG. 2Cfurther illustrates the distribution of the electrical field strength represented by gradient. For explanation convenience, the distribution of the electrical field is divided into several different regions according to the strength thereof, for example, the electrical field produced by the signal via212and the ground via220is divided into seven strength distribution regions I, II-VII. The electrical field strength of the region I is, for example, between 1.7098e+004 V/m and 3.5440e+004 V/m, i.e., 17098−35440 V/m. The electrical field strength of the region II is, for example, between 8.2485e+004 V/m and 1.7098e+004 V/m, i.e., 8248.5−17098 V/m. The distributed electrical field at the region230at the right side of the ground via220includes, for example, the region III, the region IV, the region V and the region VII respectively with a strength distribution from large one to small one, i.e. they are descended in stepped way respectively with 3.9794e+003−8.2485e+003V/m, 1.9198e+003−3.9794e+003 V/m, 9.2617e+002−1.9198e+003 V/m, 4.4682e002−9.2617e+002 V/m and 2.1556e+002−4.4682e002 V/m.

The position A inFIG. 2Cis located at the region III with a strength distribution roughly between 3.9794e+003 V/m and 8.2485e+003 V/m, in which the mid value thereof is roughly 6.1140e+003 V/m.

The disclosure provides an interconnection structure design. In an exemplary embodiment, the disclosure provides an interconnection structure disposed between a first conductive layer and a second conductive layer, where the first conductive layer and the second conductive layer are substantially parallel to each other. The first conductive layer and the second conductive layer respectively include a first signal trace and a second signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the first conductive layer and the second conductive layer and is electrically connected to the first signal trace and the second signal trace. The shielding wall pillar is disposed between the first conductive layer and the second conductive layer and electrically connected to a reference conductive wire, in which the shielding wall pillar is disposed at a portion of an external region surrounding the conductor pillar between the first conductive layer and the second conductive layer and electrically coupled to the conductor pillar.

The disclosure provides an interconnection structure design, which includes a conductor pillar and a shielding wall pillar with an in pair or in group architecture, in which in addition to the conductor pillar serves as a signal via, the architecture further includes a shielding wall pillar with a cross-sectional shape different from that of the conductor pillar, and the shielding wall pillar is connected to, for example, a ground layer or a power layer. The ground or power shielding wall pillar with a cross-sectional shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the specific or particular shape design of the shielding wall pillar, and would moreover solve, for example, the problem related to the signal integrity for the signal transmitted on the vertical via.

In one of some embodiments, the interconnection structure provided by the disclosure is located between a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer are substantially parallel to each other and respectively include a first signal trace and a second signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the first conductive layer and the second conductive layer and is electrically connected to the first signal trace and the second signal trace. The shielding wall pillar is disposed between the first conductive layer and the second conductive layer and electrically connected to a reference conductive wire. The shielding wall pillar is further disposed at a portion of an external region surrounding the conductor pillar between the first conductive layer and the second conductive layer, and electrically coupled to the conductor pillar.

In at least one of some embodiments, the reference conductive wire is electrically connected to one of the ground layer and the power layer. In the embodiments, the ground layer or the power layer is located at one of the first conductive layer and the second conductive layer. When the first conductive layer and the second conductive layer are substantially parallel to each other, the ground layer or the power layer may be located between the first conductive layer and the second conductive layer, or may be located at any position substantially parallel to the first conductive layer and the second conductive layer. In one of the embodiments, the reference conductive wire may be located on a plane same as the first conductive layer and/or the second conductive layer and electrically isolated from the second signal trace but electrically connected to one of the ground level or the power level.

The above-mentioned interconnection structure design can change the cross-sectional shapes of the conductor pillar and the shielding wall pillar according to the desire requirement so as to enhance the electromagnetic shielding effect and achieve the effect of the impedance control and design.

Referring toFIG. 3A, it is a diagram showing one of the plural embodiments. A signal trace310herein is connected to a conductor pillar312, and there is a shielding wall pillar320with, for example, semi-circle shape in cross-sectional view at a side of the conductor pillar312. A different signal trace310is connected to the conductor pillar312and there is a shielding wall pillar320with, for example, semi-circle shape at a side of the conductor pillar312, referring toFIG. 3B.

A conventional ground via with circle shape is unable to effectively block electrical field. As a result, abundant electrical field still exists at the right side of the shielding wall pillar. According to the interconnection structure design provided by the disclosure, however, the shielding wall pillar320is electrically coupled to the conductor pillar312as shown inFIG. 3A, and the shielding wall pillar320may be a structure of shielding wall pillar for shielding off the electric field lines314from the conductor pillar312to the shielding wall pillar320, and the shielding wall pillar320ofFIG. 3Ahas the same structure.

The above-mentioned disposition between the conductor pillar312and the shielding wall pillar320may have the effect of shielding off electrical field so as to control the dispersive electrical field and largely reduce the leakage field. As shown byFIGS. 3C and 3D, the electrical field strength at the right-side region330of the shielding wall pillar320is largely reduced.

In one of some embodiments, a provided interconnection structure design adopts semi-moon shape of shielding wall pillar, which encloses the whole conductor pillar to almost a half extent so as to control the electrical field direction and the strength thereof during a signal is flowing the conductor pillar, reduce the electrical field energy diffusing to the right side of the shielding wall pillar and achieve the ground shielding effect, as shown byFIG. 3Cand an enlarged diagramFIG. 3D.

Referring toFIG. 3D, the distribution of the electrical field herein is divided into different regions according to the strength thereof. Accordingly, the electrical field produced by the conductor pillar312and the shielding wall pillar320is divided into, for example, seven strength distribution regions I-VII. The region VII at the right-side region330of the shielding wall pillar320has the most strong distribution of the electrical field, where the electrical field strength is between 2.1556e+002 V/m and 4.4682e+002 V/m, i.e., 215.56−446.82 V/m.

Taking the position A inFIG. 2Cas an example, since the position A inFIG. 2Chas a strength distribution of the region III, the mid value thereof should be 6.1140e+003 V/m. However, the same position A inFIG. 3D, since it is located at the region VII, has a strength between 2.1556e+002 V/m and 4.4682e+002 V/m, i.e., 215.56−446.82 V/m with a mid value of 3.3119e+002 V/m. It can be seen from the above-mentioned comparison under the shielding field of the shielding wall pillar320, the electrical field strength for a same position drops from 6.1140e+003 V/m to 3.3119e+002 V/m.

In the interconnection structure provided by the disclosure, the conductor pillar and the shielding wall pillar may be disposed in pair or in group, which has, in addition to the conductor pillar, the shielding wall pillar with geometric shape in cross-sectional view different from that of the corresponding conductor pillar, and the shielding wall pillar is electrically connected to a ground layer or a power layer and serves as, for example, a ground via or a power via.

The shielding wall pillar with a geometric shape different from the geometric shape of the conductor pillar (usually, circle shape) makes the conductor pillar function as a vertical connection with a designed impedance and the capability of controlling impedance. For example, the conductor pillar serves as a signal via, the above-mentioned disposition may solve, for example, the problem related to the signal integrity on the vertical via. The shielding wall pillar is disposed surrounding the side wall of the above-mentioned conductor pillar and electrically coupled to at least a surrounding area of the side wall surface of the above-mentioned conductor, in which the value of the surrounding area is determined by the distribution of the electrical field produced by the conductor pillar during a current is flowing. The value of the surrounding area on the side wall surface of the conductor pillar where the shielding wall pillar is electrically coupled to is just the value of the coupling area, and the coupling area may be sufficiently large to shield off or isolate the electrical field strength located on another side surface of the shielding wall pillar facing the conductor pillar.

FIGS. 3E and 3Fare respectively a cross-sectional diagram and a three-dimensional side view diagram of a pair of disposed conductor pillar and shielding wall pillar in an interconnection structure provided by the disclosure according to an embodiment. Referring toFIGS. 3E and 3F, a shielding wall pillar350is disposed surrounding the side wall of the conductor pillar340. The projection area of the conductor pillar340facing the shielding wall pillar350is F and the area of the shielding wall pillar350facing the side wall352of the conductor pillar340is R, in which R is greater than F to a certain extent that the coupling area between the conductor pillar340and the shielding wall pillar350is greater than F. At the time, as shown byFIGS. 3E and 3F, any position point on the other direction region opposite to the region where the shielding wall pillar350faces the conductor pillar340, i.e., any position point on the region Z where the other side wall354of the shielding wall pillar350faces has the effect of reduced electrical field strength. Consequently, the disposition between the conductor pillar340and the shielding wall pillar350can serve as a connection with a designed impedance and the capability of controlling impedance and can solve, for example, the problem related to the signal integrity on the vertical via.

In following, a part of the plural exemplary embodiments in the disclosure accompanied with figures is described, which the disclosure is not limited to.

The Embodiment of FIGS.4A and4B

FIGS. 4A and 4Bare diagrams of an interconnection structure provided by the disclosure used in a combination with three conductive layers according to one of some embodiments. A combination with three conductive layers is built in an insulation plate, and the combination with three conductive layers from top to down is divided into a first conductive layer, a second conductive layer and a third conductive layer. The middle second conductive layer can be one of power layer and ground layer. The first conductive layer and the third conductive layer are substantially parallel to each other and respectively include a microstrip line type transmission line. Referring toFIGS. 4A and 4B, for example, the first conductive layer includes a signal trace430and the third conductive layer includes a signal trace450. The second conductive layer is, for example, a ground layer420. The ground layer420in the embodiment is located between the first conductive layer and the third conductive layer, but in other optional embodiments, the ground layer420may be located at any parallel position between or outside the first conductive layer and the third conductive layer. A non-conductor material layer410is between the signal trace430and the ground layer420and another non-conductor material layer412is between the ground layer420and the signal trace450. The insulation plate can include one of silicon, glass, PCB and ceramic substrates. In another embodiment, the insulation plate can also include organic substrate or flexible substrates.

The end of the signal trace430includes a conductor pillar structure. An end of the conductor pillar structure is a conductor pillar land432and a conductor pillar434going through the insulation layer410in the middle of the conductor pillar land432, and another end of the structure is another conductor pillar land436. The conductor pillar land436is located at the same height position as the ground layer420and includes a ground anti-ring422for electrically isolating from the ground layer420. Since the transmission line structure is a microstrip-line-type transmission line, so that the signal is transmitted from the signal trace430of the third conductive layer, via the conductor pillar434, then directly going through the insulation plate (including the non-conductor material layers410and412), to the signal trace450of the third conductive layer.

In the interconnection structure provided by the disclosure, the conductor pillar and the shielding wall pillar may be disposed in pair or in group, which has, in addition to the conductor pillar structure, the shielding wall pillar structure with a geometric shape different from that of the corresponding conductor pillar. The shielding wall pillar structure includes a shielding wall pillar land440, a shielding wall pillar442and another shielding wall pillar land located at the third conductive layer (not shown).

In practical applications, the dimensions of the above-mentioned shielding wall pillar land and shielding wall pillar are different from each other, and usually the dimension of the shielding wall pillar land is greater than the dimension of the shielding wall pillar. In the same way, the dimensions of the above-mentioned conductor pillar land and conductor pillar are different from each other in real applications. The conductor pillar and the shielding wall pillar may be hollow type, filling up type or that of adding a conductive filling of different materials. All the types belong to one of the scopes covered by the disclosure, which the disclosure is not limited to.

The electrical coupling between the first conductive layer, the third conductive layer and the middle ground layer is shown byFIG. 4A. The electrical field direction from the signal trace430to the ground layer420is marked by arrow462, while the electrical field direction from the signal trace450to the ground layer420is marked by arrow464.

When the conductor pillar and shielding wall pillar structure is respectively used in a signal via and a ground via, as the depiction above, when the operation frequency is increased however, the physical dimension of a via is near to the wavelength of the operation frequency, for example, 1λ(λ is the wavelength of the operation frequency). At the time, the via should be treated as an additional component for a circuit. Hence, the additional via component in the circuit needs to be designed and under control so that the circuit can normally function, and the conductor pillar434and the shielding wall pillar442are disposed in group along the vertical direction between the first conductive layer, the third conductive layer and the middle ground layer. In the embodiment, the geometric shape of the section of the shielding wall pillar442is semi-moon shape. The concave edge of the semi-moon shape faces or backs to the conductor pillar434so that the conductor pillar434is electrically coupled to the shielding wall pillar442and the coupling is able to shield off a part of the electrical field of the conductor pillar434distributed in the vertical direction.

The Embodiment of FIGS.5A and5B

FIGS. 5A and 5Bare diagrams of an interconnection structure provided by the disclosure used in a combination with three conductive layers according to an embodiment. A combination with three conductive layers is built in an insulation plate, and the combination with three conductive layers from top to down includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer and the third conductive layer are substantially parallel to each other and respectively include a symmetrical up-and-down microstrip line architecture. The second conductive layer can be one of power layer and ground layer and is in following, for example but not limited to, a ground layer. Referring toFIGS. 5A and 5B, the first conductive layer includes a signal trace530, the third conductive layer includes a signal trace550and the ground layer520is located between the first conductive layer and the third conductive layer. A non-conductor material layer510is between the signal trace530and the ground layer520and another non-conductor material layer512is between the ground layer520and the signal trace550. The insulation plate can include one of silicon, glass, PCB and ceramic substrate. In another embodiment, the insulation plate can also include organic substrate or flexible substrate.

The end of the signal trace530includes a conductor pillar structure. An end of the conductor pillar structure is a conductor pillar land532and a conductor pillar534going through the insulation layer510, and another end of the structure is another conductor pillar land536. The conductor pillar land536is located at the same position as the ground layer520and includes a ground anti-ring522for electrically isolating from the ground layer520. An end of the signal trace550also includes a conductor pillar structure, which includes a conductor pillar land552and a conductor pillar554going through the non-conductor material layer512in the middle of the conductor pillar land552, while another end is connected to the conductor pillar land536.

The above-mentioned conductor pillars534and554cab be a same conductor pillar directly going through the non-conductor material layers510and512and electrically connected to the signal trace530of the first conductive layer and the signal trace550of the third conductive layer.

Since the transmission line structure is a symmetrical up-and-down microstrip line architecture, so that during the signal is transmitting on an X-Y plane, the signal transmitting is performed through a current return path formed by the signal trace530plus the middle ground layer520.

In the embodiment of an interconnection structure provided by the disclosure, the conductor pillar and the shielding wall pillar may be disposed in pair or in group. As a result, as shown byFIGS. 5A and 5B, the first shielding wall pillar structure is disposed correspondingly to the conductor pillar534and the second shielding wall pillar structure is disposed correspondingly to the conductor pillar554, in which the first shielding wall pillar structure includes the shielding wall pillar land540and the shielding wall pillar542, and the second shielding wall pillar structure includes the shielding wall pillar land560and the shielding wall pillar562.

The geometric shapes of the sections of the shielding wall pillars542and562may be various different geometric shapes in a cross-sectional view. In the embodiment, the shapes are semi-moon shape. The concave edges of the semi-moon shapes respectively face or back to the conductor pillars534and554. The electrical coupling between the conductor pillars and the shielding wall pillars can shield the electrical fields of the conductor pillars distributed in the vertical direction.

The Embodiment of FIGS.6A and6B

FIGS. 6A and 6Bare diagrams of an interconnection structure provided by the disclosure used in a combination with three conductive layers according to an embodiment. A combination with three conductive layers is built in an insulation plate, and the combination with three conductive layers from top to down includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer and the third conductive layer are substantially parallel to each other and respectively include a symmetrical up-and-down microstrip line architecture. The second conductive layer can be one of power layer and ground layer and is, for example in following but not limited to, a ground layer.

Referring toFIGS. 6A and 6B, the first conductive layer includes a signal trace630, the third conductive layer includes a signal trace650. The ground layer620is located between the first conductive layer and the third conductive layer. A non-conductor material layer610is disposed between the signal trace630and the ground layer620and another non-conductor material layer612is disposed between the ground layer620and the signal trace650. The insulation plate may include one of silicon, glass, PCB and ceramic substrate. In another embodiment, the insulation plate may also include organic substrate or flexible substrate.

The end of the signal trace630includes a first conductor pillar structure. An end of the first conductor pillar structure is a conductor pillar land632and a conductor pillar634going through the insulation layer610, and another end of the structure is another conductor pillar land636. The conductor pillar land636is located at the same position as the ground layer620and includes a ground anti-ring622for electrically isolating from the ground layer620. An end of the signal trace650also includes a second conductor pillar structure, which includes a conductor pillar land (not shown) and a conductor pillar (not shown) going through the non-conductor material layer612in the middle of the conductor pillar land, while another end is connected to the conductor pillar land636shared by the first conductor pillar structure.

The above-mentioned conductor pillars634and654can be a same conductor pillar directly going through the non-conductor material layers610and612and respectively electrically connected to the signal trace630of the first conductive layer and the signal trace650of the third conductive layer.

Since the transmission line structure herein is a microstrip line architecture, so that the signal is transmitted from the signal trace630of the first conductive layer and the negative direction in the XYZ coordinates shown byFIGS. 6A and 6B, directly going through the substrate (including the non-conductor material layers610and612) through the conductor pillar634and then to the signal trace650of the third conductive layer and finally towards the positive Y direction.

In the embodiment of an interconnection structure provided by the disclosure, the conductor pillar and the shielding wall pillar are disposed in pair or in group. As a result, as shown byFIGS. 6A and 6B, the first shielding wall pillar structure is disposed correspondingly to the conductor pillar634and the second shielding wall pillar structure is disposed correspondingly to the conductor pillar654, in which the first shielding wall pillar structure includes the shielding wall pillar land640and the shielding wall pillar642, and the second shielding wall pillar structure includes the shielding wall pillar land660and the shielding wall pillar662.

The geometric shapes of the sections of the shielding wall pillars642and662can be various different shapes. In the embodiment, the shapes are semi-moon shape. The concave edges of the semi-moon shapes respectively face frontward or backward to the conductor pillars634and654. The electrical coupling between the conductor pillars and the shielding wall pillars may shield the electrical fields of the conductor pillars distributed in the vertical direction.

Many fabrication methods may be used to build the interconnection structure with three conductive layers as shown inFIGS. 6A and 6B. One of the methods is to use a bi-surfaces substrate serving as a core plate, in which the core plate includes two up/down whole metallic layers and an insulation medium between the two metallic layers. A plurality of holes are formed on the bi-surfaces substrate with a via drilling procedure or an etching procedure, followed by performing hole wall processing, for example, a desmearing and a flatness processing. Then, a metal implantation process, by using, for example, a sputtering process, is performed on the wall of the through hole, followed by performing plating on the conductor pillar. After that, a pattern defining process and a patterned etching are performed so as to complete the fabrications of the ground layer (the middle layer), the signal trace of the third conductive layer and the conductor pillar and shielding wall pillar both going through the core plate. Finally, the signal trace of the first conductive layer, the conductor pillar and the shielding wall pillar are completed by an adding layers process or a lamination process.

The Embodiment of FIGS.7A and7B

FIGS. 7A and 7Bare diagrams of an interconnection structure provided by the disclosure used in a combination with four conductive layers according to one of embodiments. Referring toFIGS. 7A and 7B, a combination with four conductive layers is built in an insulation plate, and the combination with four conductive layers from top to down includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer. The second and third conductive layers in between can respectively be one of power layer and ground layer or a combination thereof. The first and fourth conductive layers are arranged by a symmetrical up-and-down microstrip-line architecture. Referring toFIGS. 7A and 7B, the first conductive layer includes a signal trace730, the fourth conductive layer includes a signal trace760and the middle second and third conductive layers in the embodiment are, for example but not limited to, two ground layers720and724. The insulation plate can include one of silicon, glass, PCB and ceramic substrate. In another embodiment, the insulation plate can also include organic substrate or flexible substrate.

An end of the signal trace730includes a conductor pillar structure. The conductor pillar structure includes a conductor pillar land732, a conductor pillar734, a conductor pillar land736, a conductor pillar754, a conductor pillar land766, a conductor pillar764and a conductor pillar land762.

The above-mentioned conductor pillars734,754and764can be a same conductor pillar directly going through the insulation plate and respectively electrically connected to the signal trace730of the first conductive layer and the signal trace760of the fourth conductive layer.

Since the transmission line structure herein is a microstrip-line architecture, so that the signal is transmitted from the signal trace730of the first conductive layer, through the conductor pillar land732, the conductor pillar734, the conductor pillar land736, the conductor pillar754, the conductor pillar land766, the conductor pillar764and the conductor pillar land762, directly going through the insulation plate and then to the signal trace760of the fourth conductive layer.

In the embodiment of an interconnection structure provided by the disclosure, the conductor pillar and the shielding wall pillar may be disposed in pair or in group. As a result, as shown byFIGS. 7A and 7B, a shielding wall pillar structure is disposed correspondingly to the conductor pillar structure, in which the shielding wall pillar structure includes a shielding wall pillar land740and a shielding wall pillar742, a shielding wall pillar land743, a shielding wall pillar744, a shielding wall pillar land745, a shielding wall pillar746and a shielding wall pillar land748.

The geometric shapes of the sections of the shielding wall pillars742,744and746may be various different geometric shapes. In the embodiment, the shapes are semi-moon shape. The concave edges of the semi-moon shapes respectively face or back to the conductor pillars734,754and764. The electrical coupling between the conductor pillars and the shielding wall pillars may shield the electrical fields of the conductor pillars distributed in the vertical direction.

The fabrication method of the interconnection structure with four conductive layers is to use the middle two layers (power layers or ground layers) serving as core plates, and the process of fabricating vias on the core plates are completed, followed by performing a lamination process with appropriate prepreg. Then, a copper foil implantation process is performed on the first and fourth layers through up-and-down against-pressing two copper foils (one is at up and the other is at down). After that, an etching process and a conductor pillar drilling or etching process are performed to complete the components of the signal trace and the via.

The Embodiment of FIGS.8(A)-8(E)

In the embodiment of an interconnection structure provided by the disclosure, the conductor pillar and the shielding wall pillar may be disposed in pair or in group, in which in addition to a conductor pillar, the structure includes also a shielding wall pillar with a geometric shape different from that of the conductor pillar and the shielding wall pillar serves as, for example, a ground via or a power via.FIGS. 8(A)-8(E)are diagrams respectively illustrating different layouts of conductor pillars810a-810eand several corresponding shielding wall pillars.

As shown byFIG. 8(A), a conductor pillars goes through between the first conductive layer and the second conductive layer both substantially parallel to each other, in which the conductive layer has a circle shape section and is surrounded by a plurality of shielding wall pillars820a,822a,824aand826aall with semi-moon shape sections. The conductor pillar810aserves as a connection with a designed or predetermined impedance and the capability of controlling impedance. If the above-mentioned conductor pillar serves as a signal via, for example, the problem related to the signal integrity on the vertical via can be solved. The shielding wall pillars820a,822a,824aand826aare electrically coupled to a surrounding area on the side wall surface of the conductor pillar810aand the value of the surrounding area (i.e., the value of the coupling area) is greater than the area of projecting of the conductor pillar810aonto the surfaces of the shielding wall pillars820a,822a,824aand826aso that the other direction regions opposite to the regions where the shielding wall pillars820a,822a,824aand826aface the conductor pillar810acan be shield from the interference of the electrical field.

As shown byFIG. 8(B), a conductor pillar810bwith a circle shape section is surrounded by two shielding wall pillars820band822bwith section concave edges facing the conductor pillar810b. As shown byFIG. 8(C), a conductor pillar810cwith a circle shape section is surrounded by four shielding wall pillars820c,822c,824cand826cwith rectangular sections.

As shown byFIG. 8(D), there are a conductor pillar810dand a shielding wall pillar820both having their respective shape similar to semi-moon, in which the concave edges thereof face each other. InFIG. 8(E), a conductor pillar810eand a shielding wall pillar820both having shape similar to semi-moon are disposed against each other, and additional four shielding wall pillars830,832,834and836with shapes similar to semi-moon are disposed surrounding the conductor pillar810eand the shielding wall pillar820.

The shielding wall pillars are disposed surrounding the side wall of the above-mentioned conductor pillar and electrically coupled to at least a surrounding area on the side wall surface of the conductor pillar. The value of the surrounding area is determined by the distribution of the electrical field produced by the conductor pillar during a current is flowing. The value of the surrounding area on the side wall surface of the conductor pillar where the shielding wall pillar is electrically coupled to is just the value of the coupling area, and the coupling area must be greater than the area of projecting of the conductor pillar onto the surface of each shielding wall pillar, so that the other sides opposite to that facing the conductor pillar can be shielded from or block the interference of the electrical field.

The Embodiment of FIGS.9A-9H

The interconnection structure provided by the disclosure includes a structure of conductor pillar and shielding wall pillar disposed in pair or in group. The fabrication method in one of a plurality of embodiments can refer toFIGS. 9A-9H, in which a silicon substrate is selected as an example where a plurality of conductor pillars and a plurality of shielding wall pillars are disposed in pair or in group so as to form an interconnection structure provided by the disclosure.

Referring toFIG. 9A, a silicon wafer910is provided. A mask process is performed on the wafer to expose the parts to be etched later. Then, an etching process is performed to form a plurality of holes, in which there are at least two holes912and914serving as a conductor pillar and a shielding wall pillar. After that, the mask is removed. Using the above-mentioned procedures, the conductor pillar and shielding wall pillar with different shapes from each other can be defined so as to achieve the via structure provided by the disclosure.

Referring toFIG. 9B, a process of implantation of insulation layer is performed by using, for example, a thermal oxidation process. The procedure includes an oxidation procedure on the silicon wafer910to form a SiO2layer. In another embodiment, it can also use a plasma-enhanced chemical vapor deposition (PECVD) to deposit and form, for example, the SiO2layer. After the process of implantation of insulation layer, an insulation layer920is formed in the holes912and914.

Then referring toFIG. 9c, conductors are formed in the holes912and914, in which, for example, a sputtering process is used to form copper seed including Cu and Ti. Then, a plating process is used to fill up the hole912with metal. During the plating process, a mask process is used to expose the part to be plated later. After finishing the plating process, the mask is removed, followed by a micro-etching process to remove the thin seed metal on the front surface so as to form two via bump bodies930and932.

Referring toFIG. 9D, in order to obtain a flat TSV surface and a thinner surface conductor thickness, according to the real need, a chemical mechanical polishing (CMP) process is used for lapping to make the surface conductor thickness thinner.

After that referring toFIG. 9E, a lapping process on the bottom back surface of the silicon wafer910(i.e., the other corresponding surface opposite to the formed insulation layer920) is performed, in which, for example, a CMP process is used to expose the bottom surfaces of the conductor pillar structure and the shielding wall pillar structure of the silicon wafer910aafter lapping, for example, to expose the bottom surfaces of the conductor pillar935and the shielding wall pillar937. In this way, the whole chip thickness can be reduced a lot and the remained thickness reaches, for example, 50 μm, even 25 μm or thinner.

Referring toFIG. 9F, an oxidation procedure is performed to form an insulation layer940, for example SiO2layer, on the bottom back surface of the silicon wafer910. At the time, the original surface of the silicon wafer910(the surface originally forming the insulation layer920) must be protected with a mask or other temporary carrier to prevent the originally formed pattern from affecting or damage.

A CMP process on the bottom back surface of the silicon wafer910ais performed and the bottoms of the conductor pillar935and the shielding wall pillar937are exposed again and the exposed portions serve as the conductor pillar land and the shielding wall pillar land for electrical connections at the other ends of the conductor pillar935and the shielding wall pillar937. Then as shown byFIG. 9H, the conductor pillar land938and the shielding wall pillar land939are formed at the bottoms of the conductor pillar935and the shielding wall pillar937.

Conducting the above-mentioned processes as shown byFIGS. 9A-9H, the interconnection structure provided by the disclosure can be formed, which includes a pair, a plurality of pairs or a plurality of groups of conductor pillars and shielding wall pillars.

FIG. 9Iillustrates a structure with plural layers of the silicon wafer, in which there is an interconnection structure provided by the disclosure according to one of the embodiments, and the parts same as that inFIGS. 9A-9Hhave the same marks.

In the silicon wafer911, the interconnection structure includes a signal trace950formed on a surface of the insulation layer920, while the other surface of the insulation layer920faces into the silicon wafer911. The interconnection structure further includes a signal trace952located on one of the surfaces of the insulation layer922, while the other surface of the insulation layer922faces into the silicon wafer911. The signal trace950is electrically connected to the first conductor pillar structure and the signal trace952is electrically connected to the second conductor pillar structure. The first conductor pillar structure includes the conductor pillar935and the two conductor pillar lands934and938at both ends of the conductor pillar935. The second conductor pillar structure includes the conductor pillar975and the two conductor pillar lands974and978at both ends of the conductor pillar975. The first conductor pillar structure is electrically connected to the second conductor pillar structure though a conductor954.

The above-mentioned interconnection structure provided by the disclosure includes a structure of conductor pillar and shielding wall pillar disposed in pair or in group. Hence, the first conductor pillar structure has a corresponding first shielding wall pillar structure and the second conductor pillar structure has a corresponding second shielding wall pillar structure. As shown byFIG. 9I, the first shielding wall pillar structure includes a shielding wall pillar937and two shielding wall pillar lands936and939at both ends thereof. The second shielding wall pillar structure includes a shielding wall pillar977and two shielding wall pillar lands976and979at both ends thereof. The first shielding wall pillar structure and the second shielding wall pillar structure are electrically connected to a reference conductive layer, for example, one of a power layer and a ground layer.