Apparatus for reducing capacitor generated noise on a printed circuit board

Embodiments of the present invention provide an arrangement structure capable of reducing noise caused by a laminated ceramic capacitor mounted on a printed circuit board. A unit arrangement structure includes ceramic capacitors. Among the laminated ceramic capacitors, capacitors are arranged so that capacitor axes thereof extend along a first axis, while the other ceramic capacitors are arranged so that capacitor axes thereof extend along a second axis crossing the first axis. In accordance with such an arrangement structure, it is possible to effectively suppress noise even in the case of single-side mounting.

CLAIM OF PRIORITY

This application claims priority from Japanese Patent Application No 2008-206521, filed on Aug. 11, 2008, and which is fully incorporated by reference as if set forth herein.

FIELD OF THE INVENTION

The present invention generally relates to a technique for reducing noise generated by ceramic capacitors mounted on a printed circuit board.

BACKGROUND OF THE INVENTION

Examples of capacitors used in electronic apparatuses include ceramic capacitors, tantalum electrolytic capacitors, aluminum electrolytic capacitors, and film capacitors. Although there are single-layer ceramic capacitors which are constructed of a pair of electrodes, most ceramic capacitors are constructed of laminated ceramic capacitors having a structure in which a plurality of electrode pairs is laminated. The ceramic capacitors can be manufactured in a small size because of their dielectrics having high permittivity and are widely used in modern electronic apparatuses because of their capacitances exhibiting small changes with aging. The ceramic materials used in ceramic capacitors exhibit ferroelectric properties and so-called piezoelectric or electrostriction such that the ceramic materials are mechanically deformed when an electric voltage is applied to both ends of the capacitor.

In ceramic capacitors, high-permittivity ferroelectrics, which are mainly made of barium titanate (BaTiO3), are typically used. Such ferroelectrics have a perovskite crystal structure, so that, in their sintered state, spontaneous polarization occurs within them and crystal grains are oriented in random directions. Therefore, even when an external electric field is applied to the ferroelectrics being in such a state, piezoelectric effects of the respective crystal grains cancel out, whereby the ferroelectrics as a whole do not exhibit piezoelectric properties. When a high DC voltage is applied to the ferroelectrics, however, the respective crystal grains are polarized in the direction of the electric field, thereby exhibiting piezoelectric properties.

A DC-DC converter mounted on a computer supplies electric power to electronic devices by converting an input DC voltage into predetermined DC voltages appropriate for the respective electronic devices. In an input/output circuit of the DC-DC converter, a ripple voltage of an audible frequency range is generated due to its switching operation in the form of being superimposed on the DC voltage. A central processing unit (CPU) is also connected to the DC-DC converter as a load. When the computer is equipped with a UHCI_USB (Universal Host Controller Interface—Universal Serial Bus) master, the CPU transitions between C2 and C4 states every 1 ms in order to perform a power saving operation, and this transition appears as a ripple voltage of 1 KHz to the input/output circuit of the DC-DC converter.

The input/output circuit of the DC-DC converter or an IC chip is connected to a decoupling capacitor in order to reduce noise based on the switching operation. When the voltage of an audible frequency range superimposed on the DC voltage is applied to the decoupling capacitor, the capacitor exhibits a reverse piezoelectric effect in response to an alternating component of the electric field, so that the capacitor's body resonates with its natural frequency and vibrates. Therefore, when laminated ceramic capacitors are mounted on a printed circuit board (PCB) as decoupling capacitors, the capacitors' vibrations are transmitted to the PCB and generate noise.

Japanese Patent Application Laid-Open No. 2002-232110 teaches a technique for reducing vibration noise which is generated when vibrations of first and second ceramic capacitors generated due to a ripple component based on their charging/discharging operations are transmitted to a circuit board. The first and second ceramic capacitors are arranged so as to be aligned on one surface side of the circuit board, and the vibration waves transmitted to the circuit board have approximately equal amplitudes and opposite phases on one surface side of the circuit board.

Japanese Patent Application Laid-Open No. 2004-273935 teaches a ceramic capacitor having a structure capable of suppressing transmission of vibration to a circuit board. The ceramic capacitor element includes a dielectric base, a pair of terminal electrodes, and a plurality of internal electrodes. The pair of terminal electrodes is formed at opposite lateral ends of the dielectric base, and each of the plurality of internal electrodes has one end thereof being connected to the terminal electrode and the other end thereof being left as an open end. A pair of metal terminals has a respective board mounting portion and is connected to a corresponding terminal electrode. The board mounting portions are disposed on one mounting surface, and the mounting surface intersects the electrode face of the internal electrodes at approximately right angles. Owing to such a construction, the vibration transmitted via the metal terminals to the board can be reduced even when the ceramic capacitor element vibrates due to electrostriction phenomenon.

Japanese Patent Application Laid-Open No. 2003-324030 teaches a method of mounting a laminated ceramic capacitor on a circuit board capable of reducing noise generated due to piezoelectric phenomenon. In this method, two laminated ceramic capacitors connected in series are mounted at plane symmetry positions on top and back surfaces of a circuit board. According to this method, since two capacitors are connected in series, vibrations transmitted from respective capacitors to the circuit board cancel out, whereby the circuit board is prevented from resonating.

SUMMARY OF THE INVENTION

Embodiments of the present invention broadly contemplate an arrangement structure of a laminated ceramic capacitor on a circuit board, capable of effectively achieving noise reduction. Embodiments of the present invention provide an arrangement structure with a few restrictions for noise reduction. Embodiments of the present invention also provide an arrangement structure capable of achieving noise reduction via single-side mounting on a printed circuit board. Embodiments of the present invention also provide a printed circuit board mounting thereon a plurality of laminated ceramic capacitors having the arrangement structure.

In summary, one aspect of the invention provides an apparatus comprising: one or more processors; a printed circuit board in operative connection with the one or more processors; and one or more unit arrangements disposed on the printed circuit board, the one or more unit arrangements comprising: one or more capacitors situated on the printed circuit board along a first axis; and one or more capacitors situated on the printed circuit board along a second axis; wherein the first axis intersects with the second axis.

Furthermore, an additional aspect of the invention provides an apparatus comprising: a housing; a display device; one or more processors; one or more unit arrangements comprising a first and second plurality of capacitors; and a printed circuit board located within the housing, the printed circuit board operably engaging the one or more processors and having the one or more unit arrangements mounted thereon; wherein the first plurality of capacitors is situated along a first axis, the second plurality of capacitors is situated along a second axis, and the first axis and the second axis intersect each other; and wherein an external terminal of each capacitor of the first plurality of capacitors is connected to an external terminal of a capacitor of the second plurality of capacitors.

Moreover, another aspect of the invention provides an apparatus comprising: one or more unit arrangements disposed on a printed circuit board, the one or more unit arrangements comprising: one or more capacitors situated on the printed circuit board along a first axis; and one or more capacitors situated on the printed circuit board along a second axis; wherein the first axis intersects with the second axis.

DETAILED DESCRIPTION OF THE INVENTION

The illustrated embodiments of the invention will be best understood by reference to the drawings. The following description is intended only by way of example, and simply illustrates certain selected presently preferred embodiments of the invention as claimed herein.

The inventions disclosed in Japanese Patent Application Laid-Open Nos. 2002-232110 and 2003-324030 adjust the arrangement of two capacitors and the phase of electric current to cancel out the vibrations transmitted to the circuit board from the respective capacitors. However, it is necessary to strictly adjust the capacitor arrangement and the electric current phase in order to cancel out the vibrations. Moreover, in the case of portable computers having a narrow mounting space for a circuit board, it is difficult to mount capacitors on both sides of the circuit board, and thus the above inventions can be applied to limited applications. In the case of the invention disclosed in Japanese Patent Application Laid-Open No. 2004-273935, the capacitor size increases and the manufacturing cost increases.

Therefore, aspects of the present invention provide an arrangement structure of a laminated ceramic capacitor on a circuit board, capable of effectively achieving noise reduction. Aspects of the present invention also provide an arrangement structure with a few restrictions for noise reduction. Aspects of the present invention also provide an arrangement structure capable of achieving noise reduction via single-side mounting on a printed circuit board. Still further aspects of the present invention provide a printed circuit board mounting thereon a plurality of laminated ceramic capacitors having the arrangement structure.

At least one presently preferred embodiment of the invention provides systems and methods for mounting a plurality of laminated ceramic capacitors on a printed circuit board. Embodiments of the invention also provide an overall arrangement structure having a plurality of unit arrangement structures arranged thereon. In another preferred embodiment of the invention, an arrangement structure constructed of four laminated ceramic capacitors has two laminated ceramic capacitors arranged such that the capacitor axes thereof extend along a first axis, while the two other laminated ceramic capacitors are arranged such that capacitor axes thereof extend along a second axis crossing the first axis.

According to this unit arrangement structure, it is possible to achieve noise suppression even when the laminated ceramic capacitors are mounted on single side of the printed circuit board. The four laminated ceramic capacitors have respective external terminals being connected to each other in the proximity of a position where the first axis and the second axis cross each other so that they form two pairs of series-connected laminated ceramic capacitors. It is preferred that the first axis and the second axis intersect at right angles. When the four laminated ceramic capacitors are configured to have the same outside dimensions, it is preferred that a distance between two laminated ceramic capacitors, of which the respective external terminals oppose each other, is shorter than a length of each laminated ceramic capacitor in the direction of the capacitor axis thereof.

In accordance with an embodiment of the present invention, two unit arrangement structures may be arranged on top and back surfaces of the printed circuit board, respectively. In accordance with a first aspect of the overall arrangement structure using the unit arrangement structure, a plurality of unit arrangement structures may be arranged on the printed circuit board so that an arrangement axis thereof extends along the first axis or the second axis of each of the unit arrangement structures. In accordance with a second aspect of the overall arrangement structure, a plurality of unit arrangement structures may be arranged on the printed circuit board so that an arrangement axis thereof extends along a bisecting line of the first and second axes of each of the unit arrangement structures. In such a case, it is preferred that the unit arrangement structures are arranged at substantially equal intervals, or the overall arrangement structure is arranged on top and back surfaces of the printed circuit board.

FIG. 1illustrates a connection state between decoupling capacitors and a DC-DC converter mounted on a notebook personal computer (hereinafter, referred to as a note PC). A DC-DC converter15performs switching operations in order to convert an input voltage of DC 20 V supplied from an AC/DC adapter, for example, into an output voltage of DC 5 V. The DC-DC converter15has its secondary side being connected, directly or via another DC-DC converter, to processors, an LCD, and various electronic devices mounted on a motherboard and electric power can be supplied thereto.

The DC-DC converter15has its primary side being connected to a decoupling capacitor array11which is constructed of a plurality of laminated ceramic capacitors. The decoupling capacitors are also referred to as bypass capacitors, and are used for lowering a line impedance with respect to high-frequency voltages to restrict movement of charges along the line in response to the switching of the DC-DC converter15to a local range. Similarly, the DC-DC converter15has its secondary side being connected to a decoupling capacitor array13which is constructed of a plurality of laminated ceramic capacitors. The decoupling capacitor arrays11and13are surface-mounted on a PCB.

The note PC is equipped with a UHCI_USB master, and a ripple voltage generated at a frequency of 1 KHz from the DC-DC converter15is superimposed on the base voltage of DC 20 V or 5 V. Therefore, a ripple current of 1 KHz flows in the decoupling capacitor arrays11and13, and noise of 1 KHz is observed from the vicinity of the decoupling capacitor arrays11and13when a microphone is used.

FIG. 2Ais a perspective external view of a laminated ceramic capacitor20(hereinafter, simply referred to as capacitor), andFIG. 2Billustrates a mounting structure of the capacitor20on a PCB50. The capacitor20has an approximately rectangular outer shape, and includes a pair of external terminals51aand51b, a plurality of internal electrodes53aand53bconnected to the respective external terminals, and a dielectric55made of barium titanate (BaTiO3). The external terminals51aand51bdo not have polarity and the power-supply-side and ground-side wirings can be connected to any of the external terminals. The external terminals51aand51bare provided with connecting faces52aand52b, respectively.

In this specification, an axis connecting the central points of the two connecting faces52aand52bof the capacitor20will be referred to as a capacitor axis60. When the capacitor20is mounted on the PCB50, the connecting faces of the external terminals51aand51bare electrically coupled to solder fillets57aand57bwhich are formed on lands59aand59bprovided on a top surface of the PCB50as part of a wiring pattern by means of iron soldering or reflow soldering using lead-free solder. Therefore, vibration occurring in the capacitor20is transmitted to the PCB50via the external terminals51aand51b, the solder fillets57aand57b, and the lands59aand59b.

The PCB50is a rigid multi-layer board on which ten conductive layers are stacked. The PCB50is generally fixed to a housing or a metal frame of the note PC at a plurality of print settings but is structured to vibrate in a direction perpendicular to the plane of the PCB50at other positions thereof different from the fixation points. The capacitor20vibrates in a bending vibration mode when it is vibrating at an audible frequency range, thereby generating noise when the PCB50resonates with the vibration. When a plurality of the capacitors20is mounted on the PCB50, vibrations transmitted from individual capacitors are combined together in the PCB50, causing the PCB50to vibrate in a complex vibration mode.

In the present invention, the vibration of the PCB50is suppressed by a characteristic arrangement structure of the plural capacitors mounted thereon. In some cases, the decoupling capacitor arrays11and13described with reference toFIG. 1are constructed, for example, of about forty capacitors20, respectively. In general, the forty capacitors20are mounted on the PCB50in such a way that they are arranged at regular intervals on one straight line so that respective capacitor axes60intersect at right angles, or twenty capacitors each are arranged on two parallel straight lines so that respective capacitor axes60intersect at right angles. In the process of creating the present invention, the present inventors conducted experimental tests on the dependencies on an arrangement structure, of the audible frequency range vibration occurring in the PCB50so as to verify the hypothesis that noise can be suppressed by devising the above arrangement structure.

FIG. 3is a view for describing basic patterns of a plurality of arrangement structures that were tested. In connection with forming of the respective basic patterns shown inFIG. 3, the same electrical ratings, manufacturers, outside dimensions, application voltages, and connected loads of the respective capacitors20, and the same structure of the PCB50are used. Moreover, the method of soldering them to the PCB50is the same as that inFIG. 2B. Furthermore, the orientations of the internal electrodes53aand53bwith respect to the plane of the PCB50are randomly chosen. The tests were conducted in such a way that the respective basic patterns shown inFIGS. 3A to 3Kare periodically repeated in the directions of arrangement axes61and63so that forty capacitors in total are mounted on both or single side of the PCB50. InFIG. 3, the external terminals of the capacitors being connected to the ground side are illustrated as filled rectangles, while the external terminals connected to the power supply side are illustrated as outlined rectangles.

FIG. 3Aillustrates a basic arrangement structure which was conventionally employed, illustrating a basic pattern when twenty capacitors each are arranged on a top surface of the PCB50at equal intervals on arrangement axes61and63. The arrangement axes61and63pass through the central points in direction of the capacitor axes of the respective capacitors20. The capacitors20extending along the arrangement axis61and the capacitors20extending along the arrangement axis63have respective external terminals being arranged to oppose each other, so that the external terminals connected to the power supply side have the same orientations as the external terminals connected to the ground side. InFIG. 3Band subsequent figures, the arrangement axes61and63are omitted to avoid cluttering the figure.FIG. 3Billustrates the basic pattern ofFIG. 3Awhen the capacitors20on the arrangement axis63are arranged on the back surface of the PCB50so as to be substantially symmetrical to the capacitors20on the arrangement axis61with respect to the plane of the PCB.

FIG. 3Cillustrates the basic pattern ofFIG. 3Awhen the capacitors20on the arrangement axis61and the capacitors20on the arrangement axis63are arranged so that the respective external terminals connected to the ground side oppose each other.FIG. 3Dillustrates the basic pattern ofFIG. 3Awhen the respective capacitors20on the arrangement axes61and63are arranged so that the orientations of the external terminals connected to the power supply side and the external terminals connected to the ground side change alternately and the external terminals connected to the power supply side and the external terminals connected to the ground side oppose each other.FIG. 3Eillustrates the basic pattern ofFIG. 3Awhen the respective capacitors20on the arrangement axes61and63are arranged so as to be alternately shifted in the direction of their capacitor axis by a half of their length in direction of their capacitor axis.

FIG. 3Fillustrates the basic pattern ofFIG. 3Awhen the respective capacitors20on the arrangement axes61and63are arranged so as to be alternately shifted in the direction of their capacitor axis by one third of their length in direction of their capacitor axis.FIG. 3Gillustrates the basic pattern ofFIG. 3Awhen the capacitors20on the arrangement axis61are turned by 45 degrees to the left and the capacitors20on the arrangement axis63are turned by 45 degrees to the right.

FIG. 3Hillustrates a basic pattern when four capacitors20are arranged so as to form an X shape.FIG. 3Iillustrates a basic pattern when four capacitors20are arranged so as to form a cross shape. The detailed description of the arrangements shown inFIGS. 3H and 3Iwill be provided later.FIG. 3Jillustrates the basic pattern ofFIG. 3Awhen an opening65is formed on the PCB50so as to pass between adjacent capacitors.FIG. 3Killustrates the basic pattern ofFIG. 3Awhen the respective capacitors20on the arrangement axis63are shifted in the direction of their arrangement axis63so that the capacitor axes60are positioned at the central points between the adjacent capacitors20on the arrangement axis61. The basic patterns excluding that ofFIG. 3Bwere also tested for cases where the basic patterns are arranged on both top and back surfaces of the PCB50. In the case of double-side arrangement, twenty capacitors having the respective basic patterns were arranged on each side.

Sensory evaluation was conducted by three examiners to assess the noise occurrence state using four levels by applying a DC current to a load generating ripple voltages of an audible frequency component with the load being connected to forty capacitors20, respectively, arranged in the basic patterns ofFIGS. 3A to 3K. The results showed that for any basic pattern, the lowest noise was generated when the capacitors20were mounted on both sides of the PCB50and the next lowest noise was generated when the capacitors having the basic patterns ofFIGS. 3H and 3Iwere mounted on a single side. Therefore, it was found that mounting the capacitors on both sides of the PCB50was effective in reducing the noise.

Because differently from Japanese Patent Application Laid-Open No. 2003-324030, the above tests did not set the current phases to be reversed, the noise reduction effect by the double-side mounting is thought to result from a different principle than that of Japanese Patent Application Laid-Open No. 2003-324030 where vibrations cancel out due to the reversed phases. Although the vibration and noise can be reduced by the double-side mounting when a sufficient mounting space can be secured on the PCB50, the double-side mounting of capacitors is often difficult to be employed in a note PC because the note PC has a great limitation in increasing its thickness dimension within its housing. In the present embodiment, however, the noise can be effectively suppressed even with a single-side mounting by mounting a plurality of capacitors20to have the arrangement structure of the basic patterns ofFIGS. 3H and 3I.

FIG. 4is a view for describing a unit arrangement structure of the basic patterns shown inFIGS. 3H and 3I. The unit arrangement structure100is constructed of four capacitors101,103,105, and107having the same structure as the capacitors20. The same structure means that their forms, materials, electrical ratings, and outside dimensions are approximately the same. It should be noted, however, that the scope of the embodiments of the present invention is not limited to the case where the four capacitors have the same structure. The capacitors101and103are arranged so that a capacitor axis thereof extends along an axis201, and the capacitors105and107are arranged so that a capacitor axis thereof extends along an axis203. The axes201and203intersect at right angles. It should be noted, however, that the embodiments of the present invention are not limited to the case where the axes201and203intersect at perfect right angles.

The connecting face of an external terminal101band the connecting face of an external terminal103aoppose each other at a predetermined distance, and the connecting face of an external terminal105aand the connecting face of an external terminal107boppose each other at the same distance as the predetermined distance. This distance is preferably smaller than the length in direction of the capacitor axis of the capacitor20. The external terminals101a,101b,103a,103b,105a,105b,107a, and107bare connected to the lands formed on the PCB50by means of solder fillets102, respectively, as illustrated inFIG. 2. The external terminals101band105aare connected together via the wiring pattern of the PCB50, and the external terminals103aand107bare connected together via the wiring pattern of the PCB50.

In this unit arrangement structure100, the capacitors101and105are paired and connected in series and the capacitors103and107are paired and connected in series. When the unit arrangement structure100is connected to an input/output circuit of the DC-DC converter15, the external terminals101aand107aare connected to the power supply side, and the external terminals105band103bare connected to the ground side, for example. In this case, in each pair of capacitors, the external terminals connected to the power supply side and the external terminals connected to the ground side may be interchanged arbitrarily without being affected by other capacitor pairs.

FIGS. 5 and 6are views for describing a pattern used when forty capacitors are mounted on a single side of the PCB50using the unit arrangement structure100. InFIG. 5, five unit arrangement structures100are arranged at equal intervals along an arrangement axis71. Similarly, five unit arrangement structures100are arranged at equal intervals along an arrangement axis73parallel to the arrangement axis71. The unit arrangement structure axes201extend along the arrangement axes71and73, respectively. The number of arrangement axes may be one or three or more, and the maximum number of unit arrangement structures100arranged along each arrangement axis is not particularly limited.

InFIG. 6, five unit arrangement structures100are arranged at equal intervals along two parallel arrangement axes75and77. The unit arrangement structures100have their unit arrangement structure axes201and203being turned by 45 degrees from the pattern shown inFIG. 5. That is, a bisecting line of the unit arrangement structure axes201and203extends along the arrangement axis75or77. The arrangement structures shown inFIGS. 5 and 6generate less noise from the PCB50than the arrangement structure employing different basic patterns shown inFIG. 3even when they are mounted on a single side of the PCB50. Moreover, when a plurality of capacitors having the arrangement structures shown inFIGS. 5 and 6is mounted on both sides of the PCB50, the noise suppression effect can be further increased.

In the embodiments of the present invention, it is not necessary to limit the orientations of the internal electrodes53aand53bwith respect to the top surface of the PCB50and the polarities of voltages applied to a pair of series-connected capacitors. Moreover, in the case of double-side mounting, it is not necessary to arrange the capacitors so as to be strictly symmetrical with respect to a plane of the PCB and to connect the top-side capacitors and the back-side capacitors in series. Therefore, the mounting restrictions are reduced and embodiments of the present invention can be applied to broader applications. Furthermore, because it is not necessary to incorporates anti-vibration measures into capacitors per se, low-cost capacitors can be used.

Although embodiments of the present invention has been described so far in accordance with specific embodiments illustrated in drawings, the invention is not limited to the embodiments illustrated in the drawings. As a matter of course, any known configurations may be used as long as the functions of embodiments of the present invention are executed thereby.

Embodiments of the present invention can be applied to a printed circuit board mounting thereon a plurality of capacitors.

In accordance with the above-mentioned aspects of the present invention, it is possible to provide an arrangement structure of a laminated ceramic capacitor on a circuit board, capable of effectively achieving noise reduction. Moreover, it is possible to provide an arrangement structure with a few restrictions for noise reduction. Furthermore, it is possible to provide an arrangement structure capable of achieving noise reduction via single-side mounting on a printed circuit board. Furthermore, it is possible to provide a printed circuit board mounting thereon a plurality of laminated ceramic capacitors having the arrangement structure.

It should be understood and appreciated that arrangements of capacitors on printed circuit boards, as discussed and broadly contemplated herein, can be employed in a wide variety of operating environments, including but not limited to computers, cell phones, digital cameras, and other mobile devices. Thus, while the foregoing discussion presents a computer system as a possible operating environment for such arrangements according to embodiments of the invention, it of course should be understood that this is provided by way of a non-limiting example. Capacitors have multiple applications, such as signal tuning or voltage conversion, necessary to the function of most electronic devices.

In the drawings and specification there has been set forth a preferred embodiment of the invention and, although specific terms are used, the description thus given uses terminology in a generic and descriptive sense only and not for purposes of limitation.

If not otherwise stated herein, it is to be assumed that all patents, patent applications, patent publications and other publications (including web-based publications) mentioned and cited herein are hereby fully incorporated by reference herein as if set forth in their entirety.