Silicon carbide semiconductor device and method for manufacturing same

A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.

TECHNICAL FIELD

The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device.

BACKGROUND ART

Japanese Patent Laying-Open No. 2013-34007 (Patent Document 1) discloses a silicon carbide epitaxial wafer characterized in that there is no short step-bunching.

CITATION LIST

Patent Document

SUMMARY OF INVENTION

A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide epitaxial layer and a gate insulating film. The silicon carbide epitaxial layer includes a first impurity region, a second impurity region, and a third impurity region, the first impurity region having a first conductivity type, the second impurity region being provided in contact with the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being separated from the first impurity region by the second impurity region, the third impurity region having the first conductivity type. The gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.

A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present disclosure includes the following steps. There is prepared a silicon carbide epitaxial layer including a first impurity region, a second impurity region, and a third impurity region, the first impurity region having a first conductivity type, the second impurity region being provided on the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being separated from the first impurity region by the second impurity region, the third impurity region having the first conductivity type. A gate insulating film is formed in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.

DESCRIPTION OF EMBODIMENTS

Description of Embodiments of Present Disclosure

[1] A silicon carbide semiconductor device1000according to one embodiment of the present disclosure includes a silicon carbide epitaxial layer120and a gate insulating film57. Silicon carbide epitaxial layer120includes a first impurity region61, a second impurity region62, and a third impurity region63, first impurity region61having a first conductivity type, second impurity region62being provided in contact with first impurity region61, second impurity region62having a second conductivity type different from the first conductivity type, third impurity region63being separated from first impurity region61by second impurity region62, third impurity region63having the first conductivity type. Gate insulating film57is in contact with first impurity region61, second impurity region62, and third impurity region63. A groove portion20is formed in a surface161of first impurity region61, surface161being in contact with gate insulating film57, groove portion20extending in one direction along surface161, a width of groove portion20in the one direction being twice or more as large as a width of groove portion20in a direction perpendicular to the one direction, a maximum depth of groove portion20from surface161being not more than 10 nm.

Hereinafter, the width of groove portion20in the one direction will be referred to as “second width82”, the width of groove portion20in the direction perpendicular to the one direction will be referred to as “third width83”, and the maximum depth of groove portion20from surface161will be referred to as “second depth72”.

When forming a silicon carbide epitaxial layer on a silicon carbide substrate, minute pit portions30(seeFIG. 3andFIG. 5) may be formed in a main surface of the silicon carbide epitaxial layer. Each of such pit portions is formed due to a threading dislocation transferred from the silicon carbide substrate to the silicon carbide epitaxial layer, and is a depression having a depth of about several ten nm. The present inventor has found that: pit portions formed in a surface of a JFET (Junction Field Effect Transistor) region causes increase in variation in film thickness of a gate insulating film formed on the JFET region; and the variation in film thickness is one factor for decrease in long-term reliability of the silicon carbide semiconductor device.

The present inventor has found that the formation of pit portions can be suppressed under a specific epitaxial growth condition. According to the growth condition, the pit portions are reduced whereas a multiplicity of groove portions are formed which are shallower than the pit portions and which extend in one direction. However, it has been found that the groove portions are shallower than the pit portions and therefore have a smaller influence over the variation in film thickness of the gate insulating film than the influence of the pit portions.

In silicon carbide semiconductor device1000according to [1], groove portion20is formed in surface161of first impurity region61in contact with gate insulating film57, groove portion20extending in the one direction along surface161, second width82of groove portion20being twice or more as large as third width83, second depth72of groove portion20being not more than 10 nm. According to silicon carbide semiconductor device1000in which groove portion20is formed, variation in the film thickness of gate insulating film57can be reduced as compared with the conventional silicon carbide semiconductor device in which a multiplicity of pit portions are formed. Accordingly, in accordance with the silicon carbide semiconductor device according to [1], long-term reliability is improved as compared with the conventional silicon carbide semiconductor device.

The shape of the “groove portion” can be specified by observing surface161of JFET region61using a predetermined defect inspection device. For example, the defect inspection device can be employed to measure second width82and third width83of groove portion20in surface161of JFET region61after removing gate insulating film57from JFET region61. As the defect inspection device, WASAVI series “SICA 6X” provided by Lasertec Corporation (objective lens: ×10) can be used, for example. Moreover, the depth of the “groove portion” can be measured using an AFM (Atomic Force Microscope). It should be noted that the gate insulating film is desirably removed using diluted aqueous hydrogen fluoride (HF).

[2] In [1], a width of surface161of first impurity region61in a direction along a direction parallel to surface161of first impurity region61may be not less than 1.5 μm and not more than 3.5 μm. Hereinafter, the width of surface161of first impurity region61will be also referred to as “fifth width85”. By setting fifth width85at not less than 1.5 μm, it is possible to suppress significant increase of transistor resistance resulting from increase of JFET resistance. By setting fifth width85at not more than 3.5 μm, gate insulating film57on JFET region61is protected by depletion from second impurity region62, and increase of on resistance of the semiconductor device resulting from increase of unit cell area can be suppressed.

[3] In [1] or [2], a thickness157of gate insulating film57in a direction perpendicular to surface161of first impurity region61may be not less than 40 nm and not more than 100 nm. By setting thickness157of gate insulating film57at not less than 40 nm, reliability of gate insulating film57can be suppressed from being decreased. By setting thickness157of gate insulating film57at not more than 100 nm, it is possible to suppress increase of voltage applied between gate electrode51and source electrode52and required to turn on the transistor.

[4] In any one of [1] to [3], a density of nitrogen atoms may be not less than 1018cm−3in a boundary region between gate insulating film57and first impurity region61. Accordingly, reliability of gate insulating film57may be improved.

[5] In any one of [1] to [4], groove portion20may include a first groove portion21and a second groove portion22connected to first groove portion21. First groove portion21may be formed in one end portion of groove portion20in the one direction. Second groove portion22may extend in the one direction from first groove portion21to the other end portion opposite to the one end portion, and a depth of second groove portion22from surface161may be smaller than a maximum depth of first groove portion21.

Hereinafter, the depth of second groove portion22from surface161will be also referred to as “first depth71”.

[6] In [5], gate insulating film57may be provided on first groove portion21.

[7] In any one of [1] to [6], the silicon carbide semiconductor device may further include a silicon carbide substrate110having an off angle of not more than ±4° relative to a (0001) plane. Silicon carbide epitaxial layer120may be a layer epitaxially grown on silicon carbide substrate110. Groove portion20may be formed to extend from a threading dislocation40in silicon carbide epitaxial layer120in a step-flow growth direction that is along the off direction of the off angle.

Here, the expression “substrate having an off angle of not more than ±4° relative to a (0001) plane” refers to a substrate having two main surfaces, one of which has an off angle of not more than ±4° relative to the (0001) plane.

[8] In [7], the off direction may be in a range of not more than ±5° relative to a <11-20> direction.

[9] In [7], the off direction may be in a range of not more than ±5° relative to a <01-10> direction.

[10] A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present disclosure includes the following steps. There is prepared a silicon carbide epitaxial layer120including a first impurity region61, a second impurity region62, and a third impurity region63, first impurity region61having a first conductivity type, second impurity region62being provided on first impurity region61, second impurity region62having a second conductivity type different from the first conductivity type, third impurity region63being separated from first impurity region61by second impurity region62, third impurity region63having the first conductivity type. A gate insulating film57is formed in contact with first impurity region61, second impurity region62, and third impurity region63. A groove portion20is formed in a surface161of first impurity region61, surface161being in contact with gate insulating film57, groove portion20extending in one direction along surface161, a width (second width82) of groove portion20in the one direction being twice or more as large as a width (third width83) of groove portion20in a direction perpendicular to the one direction, a maximum depth (second depth72) of groove portion20from surface161being not more than 10 nm.

In accordance with the method for manufacturing the silicon carbide semiconductor device according to [10], gate insulating film57is formed on the surface of the impurity region in which a larger number of groove portions20are formed than the pit portions having a depth of several ten nm. Hence, in accordance with the manufacturing method according to [10], there can be manufactured a silicon carbide semiconductor device in which variation in film thickness of gate insulating film57is small. That is, in accordance with the manufacturing method according to [10], a silicon carbide semiconductor device having improved long-term reliability can be manufactured.

[11] The manufacturing method according to [10] may further include the step of heating gate insulating film57at a temperature of not less than 1100° C. in an atmosphere including nitrogen atoms after the step of forming gate insulating film57. Accordingly, reliability of gate insulating film57may be improved.

[12] The manufacturing method according to [10] or [11] may further include the step of preparing a silicon carbide substrate before the step of preparing the silicon carbide epitaxial layer. The step of preparing the silicon carbide epitaxial layer can include the steps of: forming a first epitaxial layer on the silicon carbide substrate using a source material gas having a C/Si ratio of less than 1; reconstructing a surface of the first epitaxial layer using a mixed gas including (i) a source material gas having a C/Si ratio of less than 1 and (ii) a hydrogen gas; and forming a second epitaxial layer on the reconstructed surface of the first epitaxial layer using a source material gas having a C/Si ratio of not less than 1.

In [12], the “C/Si ratio” represents a ratio of the number of carbon (C) atoms to the number of silicon (Si) atoms in the source material gas. The expression “reconstructing the surface” indicates to change a surface property of the first epitaxial layer through etching by the hydrogen gas and through epitaxial growth by the source material gas. Through the step of reconstructing, the thickness of the first epitaxial layer may be decreased, may be increased, or may be substantially unchanged.

In the step of reconstructing the surface, the ratio of the flow rate of the source material gas to the flow rate of the hydrogen gas may be reduced as compared with general epitaxial growth such that the etching by the hydrogen gas is comparable to the epitaxial growth by the source material gas. For example, it is considered to adjust the flow rate of the hydrogen gas and the flow rate of the source material gas to attain a film formation rate of about 0±0.5 μm/h.

The above-described threading dislocations include threading screw dislocations, threading edge dislocations, and composite dislocations in which these dislocations are mixed. These dislocations are expressed by Burgers vector b in the following manner: threading screw dislocations (b=<0001>); threading edge dislocations (b=⅓<11-20>); and composite dislocations (b=<0001>+⅓<11-20>). It is considered that the pit portions having an influence over reliability of the gate insulating film are formed due to the threading screw dislocations, the threading edge dislocations, and the composite dislocations. Pits formed due to the threading screw dislocations and composite dislocations both involving relatively large strain around the dislocations have deep depths.

In [12], the surface of the first epitaxial layer is reconstructed, whereby it can be expected to obtain an effect of attaining shallow pit portions formed due to threading screw dislocations and composite dislocations. In addition to this, the C/Si ratio of the source material gas is changed from a value of less than 1 to a value of not less than 1 and the second epitaxial layer is then grown. Accordingly, it is considered to increase the effect of attaining shallow pit portions resulting from threading screw dislocations and composite dislocations.

Details of Embodiments of Present Disclosure

Next, the following describes one embodiment (hereinafter, also referred to as “the present embodiment”) of the present disclosure with reference to figures. In the figures below, the same or corresponding elements are given the same reference characters and are not described repeatedly. In the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, and an individual plane is represented by ( ), and a group plane is represented by { }. Normally, a negative index is supposed to be crystallographically indicated by putting “−” (bar) above a numeral, but is indicated by putting the negative sign before the numeral in the present specification.

First, the following describes a structure of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which serves as a silicon carbide semiconductor device according to the present embodiment.

FIG. 1shows one unit cell of a MOSFET and its periphery. As shown inFIG. 1, a MOSFET1000is a vertical type MOSFET having a planar structure. In the present embodiment, a chip size, i.e., an effective area of a semiconductor chip constituted of a plurality of unit cells, is about 1 mm2to 100 mm2, for example. Here, the “effective area” refers to an area of a region of the semiconductor chip except a gate pad region for wire bonding, a gate runner, and a termination structure portion for holding a breakdown voltage.

MOSFET1000includes an epitaxial wafer100, gate insulating films57, gate electrodes51, source electrodes52, a drain electrode53, a source pad electrode54, a backside pad electrode55, and interlayer insulating films56.

Epitaxial wafer100has a silicon carbide substrate110, and a silicon carbide epitaxial layer120provided on silicon carbide substrate110. Silicon carbide substrate110has a second main surface102and a third main surface103opposite to second main surface102. Silicon carbide epitaxial layer120is formed on third main surface103. Silicon carbide epitaxial layer120has a first main surface101opposite to silicon carbide substrate110. Silicon carbide epitaxial layer120has a drift region60, body regions62, source regions63, and contact regions64.

Drift region60is provided on third main surface103. Drift region60includes an n type impurity such as nitrogen (N), and has n type conductivity (first conductivity type). Drift region60includes a JFET region61that is interposed between body regions62and that constitutes a portion of first main surface101when viewed in a cross section (when viewed in a direction parallel to first main surface101). Furthermore, drift region60includes: a region interposed between JFET region61and third main surface103; and a region interposed between each body region62and third main surface103. Drift region60and JFET region61include an n type impurity and have n type conductivity.

A width (fifth width85) of a surface161of JFET region61in a direction parallel to surface161of JFET region61may be not less than 1.5 μm and not more than 3.5 μm, or may be not less than 2 μm and not more than 3 μm.

For example, an n type impurity such as phosphorus (P) may be additionally added to the JFET region. The impurity may be added through ion implantation, for example. When the concentration of the n type impurity in the drift region is low and the breakdown voltage of the drift region is large, the concentration of the n type impurity may be adjusted in accordance with the width (fifth width85) of the JFET region. The concentration of the n type impurity is adjusted to fall within the range of about 7×1015cm−3to 1×1017cm−3, for example.

Body region62includes a p type impurity such as aluminum (Al) or boron (B), and has p type conductivity (second conductivity type) different from n type conductivity, for example. Body region62constitutes a portion of first main surface101. A region of body region62adjacent to gate insulating film57serves as a channel. Body region62is provided in contact with both JFET region61and drift region60.

Source region63includes an n type impurity such as phosphorus (P), and has n type conductivity, for example. Source region63constitutes a portion of first main surface101. Source region63is separated from JFET region61and drift region60by body region62. Each of the side surfaces and bottom surface of source region63is in contact with body region62. The concentration of the n type impurity included in source region63may be higher than the concentration of the n type impurity included in drift region60.

Contact region64includes a p type impurity such as aluminum (Al) and boron (B), and has p type conductivity, for example. Contact region64constitutes a portion of first main surface101. Contact region64extends through source region63, and connects source electrode52to body region62. The concentration of the p type impurity included in contact region64may be higher than the concentration of the p type impurity included in body region62.

In first main surface101, gate insulating film57is in contact with JFET region61, body region62, and source region63. Gate insulating film57is a gate oxide film composed of, for example, a material such as silicon dioxide. A thickness157of a portion of gate insulating film57in a direction perpendicular to surface161of JFET region61may be not less than 40 nm and not more than 100 nm, or may be not less than 45 nm and not more than 65 nm.

Gate electrode51is composed of a conductor such as aluminum or polysilicon having an impurity added therein, for example. Gate electrode51is provided on gate insulating film57, and is disposed to face JFET region61, body region62, and source region63.

In first main surface101, source electrode52is in contact with both source region63and contact region64. Preferably, source electrode52is in ohmic junction with source region63. More preferably, source electrode52is in ohmic junction with contact region64. Source electrode52is composed of a material such as nickel silicon (NixSiy), titanium silicon (TixSiy), aluminum silicon (AlxSiy), or titanium aluminum silicon (TixAlySiz, where x, y, z>0), for example.

Drain electrode53is formed in contact with second main surface102of silicon carbide substrate110. Drain electrode53is composed of a material capable of ohmic junction with silicon carbide having n type conductivity, such as nickel silicon, for example. Drain electrode53may be composed of the same material as that of source electrode52. Drain electrode53is electrically connected to silicon carbide substrate110. Interlayer insulating film56is composed of, for example, a material including silicon dioxide, and is formed to surround gate electrode51. Interlayer insulating film56electrically insulates between gate electrode51and source electrode52.

Source pad electrode54is formed to cover source electrode52and interlayer insulating film56. Source pad electrode54is composed of a material including aluminum (Al), for example. Source pad electrode54is electrically connected to source region63via source electrode52. Backside pad electrode55is composed of a material including aluminum (Al), for example. Backside pad electrode55is electrically connected to silicon carbide substrate110via drain electrode53.

The density of nitrogen atoms is not less than 1018cm−3in a boundary region200between gate insulating film57and JFET region61as shown inFIG. 2. Boundary region200between gate insulating film57and JFET region61refers to a region interposed between a first imaginary plane201and a second imaginary plane202, wherein first imaginary plane201is located to be displaced by 5 nm to the gate electrode51side and second imaginary plane202is located to be displaced by 5 nm to the silicon carbide substrate110side in the direction perpendicular to surface161, relative to surface161of JFET region61that is in contact with gate insulating film57. The density of the nitrogen atoms can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Preferably, the density of the nitrogen atoms in boundary region200is not less than 1018cm−3and not more than 1021cm−3.

Next, the following describes a configuration of epitaxial wafer100included in MOSFET1000according to the present embodiment.

As shown inFIG. 3, epitaxial wafer100according to the present embodiment has silicon carbide substrate110and silicon carbide epitaxial layer120. Silicon carbide substrate110is composed of a silicon carbide single crystal, for example. This silicon carbide single crystal has a hexagonal crystal structure and has a polytype of 4H, for example. Silicon carbide substrate110includes an n type impurity such as nitrogen (N) and therefore has n type conductivity.

Silicon carbide substrate110has second main surface102and third main surface103opposite to second main surface102. Third main surface103has a diameter of not less than 100 mm (not less than 4 inches), preferably, not less than 150 mm (not less than 6 inches), for example. Third main surface103may have a diameter of not more than 300 mm (not more than 12 inches). As shown inFIG. 1, silicon carbide epitaxial layer120is formed on third main surface103. Third main surface103has an off angle of not more than ±4° relative to a (0001) plane (hereinafter, referred to as “silicon (Si) plane”), for example. The off direction of this off angle may be in a range of not more than ±5° relative to a <11-20> direction or may be in a range of not more than ±5° relative to a <01-10> direction, for example.

The silicon carbide epitaxial layer has first main surface101opposite to silicon carbide substrate110.

Silicon carbide epitaxial layer120is a silicon carbide single crystal film formed on third main surface103of silicon carbide substrate110through vapor phase epitaxy, for example. More specifically, silicon carbide epitaxial layer120is an epitaxial growth layer formed by CVD (Chemical Vapor Deposition) employing silane (SiH4) and propane (C3H8) as a source material gas and nitrogen (N2) or ammonia (NH3) as a dopant gas. Silicon carbide epitaxial layer120includes nitrogen (N) atoms, which are generated through thermal decomposition of the nitrogen or ammonia, and therefore has n type conductivity type. Preferably, the concentration of the n type impurity included in silicon carbide epitaxial layer120is lower than the concentration of the n type impurity included in silicon carbide substrate110. Since third main surface103is angled off relative to the (0001) plane as described above, silicon carbide epitaxial layer120is formed through step-flow growth. Hence, silicon carbide epitaxial layer120is composed of silicon carbide having a polytype of 4H as with silicon carbide substrate110and therefore a different type of polytype is suppressed from being mixed therein. Silicon carbide epitaxial layer120has a thickness of approximately not less than 5 μm and not more than 150 μm, for example.

As shown inFIG. 4, a groove portion20is formed in surface161of JFET region61. Groove portion20extends in one direction along surface161when surface161is viewed in plan (field of view in the direction perpendicular to surface161). More specifically, groove portion20extends in a step-flow growth direction, which is along the off direction of the off angle relative to the (0001) plane. In other words, groove portion20extends in a direction in a range of not more than ±5° relative to the <11-20> direction or a direction in a range of not more than ±5° relative to the <01-10> direction.

It should be noted thatFIG. 3toFIG. 5are drawn such that the “step-flow growth direction” corresponds to the X-axis direction inFIG. 3toFIG. 5. In each ofFIG. 3toFIG. 5, the X-axis direction, Y-axis direction, and Z-axis direction are orthogonal to one another. The Y-axis direction shown in each ofFIG. 4andFIG. 5represents a direction perpendicular to the step-flow growth direction. The Z-axis direction shown inFIG. 3represents the thickness direction of the silicon carbide epitaxial layer.

The width (second width82) of groove portion20in the above-described one direction is twice or more as large as, preferably, five times or more as large as the width (third width83) thereof in the direction perpendicular to the one direction. Second width82is not less than 15 μm and not more than 50 μm, preferably, not less than 25 μm and not more than 35 μm. Third width83is not less than 1 μm and not more than 5 μm, preferably, not less than 2 μm and not more than 3 μm.

As shown inFIG. 3, groove portion20is formed to extend in the step-flow growth direction from a threading dislocation40included in silicon carbide epitaxial layer120. More specifically, groove portion20includes: a first groove portion21formed on threading dislocation40; and a second groove portion22formed to be connected to first groove portion21and extend from first groove portion21in the step-flow growth direction.

First groove portion21is formed at one end portion (left end portion inFIG. 3) of groove portion20in the step-flow growth direction. Moreover, the maximum depth (second depth72) of first groove portion21from first main surface101is not more than 10 nm. Second depth72is the maximum depth in the entire groove portion20as shown inFIG. 3. First groove portion21preferably has a width (first width81) of not more than 1 μm, and more preferably has a width (first width81) of not more than 0.5 μm.

As shown inFIG. 3, second groove portion22is formed to extend from its portion of connection with first groove portion21to the other end portion opposite to the above-described one end portion (right end portion inFIG. 3). Moreover, second groove portion22is formed such that a depth (first depth71) of second groove portion22from first main surface101is smaller than the maximum depth (second depth72) of first groove portion21. More specifically, second groove portion22extends in the step-flow growth direction while maintaining the depth shallower than the maximum depth (second depth72) of first groove portion21. First depth71is preferably not more than 3 nm, is more preferably not more than 2 nm, and is further preferably not more than 1 nm. Moreover, second groove portion22has a width (fourth width84) of, for example, not less than 20 μm, preferably, not less than 25 μm.

As shown inFIG. 1andFIG. 3, gate insulating film57is provided in contact with surface161of JFET region61, surface162of body region62, and surface163of source region63. Gate insulating film57is provided on groove portion20provided in surface161, and is preferably provided on first groove portion21. Gate insulating film57may be provided on second groove portion22provided in surface161, or may be provided on pit portion30. As shown inFIG. 3andFIG. 5, pit portion30may be provided in surface161. As shown inFIG. 3, pit portion30is formed due to threading dislocation40extending from silicon carbide substrate110into silicon carbide epitaxial layer120. The maximum depth (third depth73) of pit portion30is larger than 10 nm, more specifically, larger than 20 nm. As shown inFIG. 5, in a plan view, pit portion30may have a triangular shape. Gate insulating film57may be provided to fill first groove portion21and second groove portion22included in groove portion20.

[Method for Manufacturing Silicon Carbide Semiconductor Device]

Next, the following describes a method for manufacturing MOSFET1000according to the present embodiment.

First, as shown inFIG. 6, a silicon carbide epitaxial layer preparing step (S30) is performed. As shown inFIG. 7, the silicon carbide epitaxial layer preparing step (S30) includes: a step (S10) of preparing a silicon carbide substrate; a step (S21) of forming a first epitaxial layer; a step (S22) of reconstructing a surface of the first epitaxial layer; and a step (S23) of forming a second epitaxial layer on the reconstructed surface.

In the step (S10) of preparing the silicon carbide substrate, a silicon carbide ingot (not shown) having a polytype of 4H and obtained through crystal growth using a sublimation-recrystallization method is sliced into a predetermined thickness, thereby preparing silicon carbide substrate110(FIG. 10), for example. Silicon carbide substrate110has second main surface102and third main surface103opposite to second main surface102. As shown inFIG. 11, silicon carbide epitaxial layer120is formed on third main surface103. Third main surface103has an off angle of not more than ±4° relative to the (0001) plane, for example. The off direction of this off angle may be in a range of not more than ±5° relative to the <11-20> direction or may be in a range of not more than ±5° relative to the <01-10> direction, for example.

Next, as shown inFIG. 10, CVD is employed to epitaxially grow silicon carbide epitaxial layer120on third main surface103. Here, the configuration of an epitaxial growth device1will be described first with reference toFIG. 8andFIG. 9.FIG. 8is a side view of epitaxial growth device1.FIG. 9is a cross sectional view of epitaxial growth device1along a line segment IX-IX inFIG. 8.

As shown inFIG. 8andFIG. 9, epitaxial growth device1mainly includes heating elements6, a heat insulator5, a quartz tube4, and an induction heating coil3. Each of heating elements6is composed of a carbon material, for example. As shown inFIG. 9, heating element6has a semi-cylindrical hollow structure including a curved portion7and a flat portion8. Two heating elements6are provided and disposed such that their respective flat portions8face each other. A space surrounded by these flat portions8is a channel2serving as a space for performing a treatment to silicon carbide substrate110.

Heat insulator5is a member configured to thermally insulate channel2from the outside of epitaxial growth device1. Heat insulator5is provided to surround the outer circumference portions of heating elements6. Quartz tube4is provided to surround the outer circumference portion of heat insulator5. Induction heating coil3is wound at the outer circumference portion of quartz tube4.

Next, the following describes a crystal growth process employing epitaxial growth device1described above. First, silicon carbide substrate110prepared in the step (S10) is placed in channel2of epitaxial growth device1. More specifically, silicon carbide substrate110is placed on a susceptor (not shown) provided on one heating element6.

1. Step (S21) of Forming First Epitaxial Layer

Next, the step of forming the first epitaxial layer is performed. In this step, a source material gas having a C/Si ratio of less than 1 is used to form first epitaxial layer121(seeFIG. 3) on silicon carbide substrate110. First, after gas replacement in channel2, a pressure in channel2is adjusted to a predetermined pressure such as 60 mbar to 100 mbar (6 kPa to 10 kPa) while letting a carrier gas to flow. The carrier gas may be, for example, hydrogen (H2) gas, argon (Ar) gas, helium (He) gas, or the like. The flow rate of the carrier gas may be about 50 slm to 200 slm, for example. The unit for flow rate as used herein, i.e., “slm (Standard Liter per Minute)” represents “L/min” in a standard condition (0° C. and 101.3 kPa).

Next, a predetermined alternating current is supplied to the induction heating coil, thereby inductively heating elements6. Accordingly, channel2and the susceptor having silicon carbide substrate110placed thereon are heated to a predetermined reaction temperature. On this occasion, the susceptor is heated to about 1500° C. to 1750° C., for example.

Next, a source material gas is supplied. The source material gas includes a Si source gas and a C source gas. Examples of the Si source gas include silane (SiH4) gas, disilane (Si2H6) gas, dichlorosilane (SiH2Cl2) gas, trichlorosilane (SiHCl3) gas, silicon tetrachloride (SiCl4) gas, and the like. That is, the Si source gas may be at least one selected from a group consisting of silane gas, disilane gas, dichlorosilane gas, trichlorosilane gas and silicon tetrachloride gas.

Examples of the C source gas includes methane (CH4) gas, ethane (C2H6) gas, propane (C3H8) gas, acetylene (C2H2) gas, and the like. That is, the C source gas may be at least one selected from a group consisting of methane gas, ethane gas, propane gas, and acetylene gas.

The source material gas may include a dopant gas. Examples of the dopant gas include nitrogen gas, ammonia gas, and the like.

The source material gas in the step of forming the first epitaxial layer may be a mixed gas of silane gas and propane gas, for example. In the step of forming the first epitaxial layer, the C/Si ratio of the source material gas is adjusted to less than 1. For example, the C/Si ratio may be not less than 0.5, not less than 0.6, or not less than 0.7 as long as the C/Si ratio is less than 1. Moreover, for example, the C/Si ratio may be not more than 0.95, not more than 0.9, or not more than 0.8. The flow rate of the silane gas and the flow rate of the propane gas may be adjusted appropriately in a range of about 10 to 100 sccm to achieve a desired C/Si ratio, for example. The unit for flow rate as used herein, i.e., “sccm (Standard Cubic Centimeter per Minute)” represents “mL/min” in a standard condition (0° C. and 101.3 kPa).

A film formation rate in the step of forming the first epitaxial layer may be about not less than 3 μm/h and not more than 30 μm/h, for example. The first epitaxial layer has a thickness of not less than 0.1 μm and not more than 150 μm, for example. Moreover, the thickness of the first epitaxial layer may be not less than 0.2 μm, may be not less than 10 μm, and may be not less than 15 μm. Moreover, the thickness of the first epitaxial layer may be not more than 100 μm, may be not more than 75 μm, or may be not more than 50 μm.

2. Step (S22) of Reconstructing Surface of First Epitaxial Layer

Next, the step of reconstructing the surface of the first epitaxial layer is performed. The step of reconstructing the surface may be performed continuous to the step of forming the first epitaxial layer. Alternatively, a predetermined halt time may be provided between the step of forming the first epitaxial layer and the step of reconstructing the surface. In the step of reconstructing the surface, the temperature of the susceptor may be increased by about 10° C. to 30° C.

In the step of reconstructing the surface, a mixed gas including a source material gas having a C/Si ratio of less than 1 and hydrogen gas is used. The C/Si ratio of the source material gas may be lower than the C/Si ratio in the step of forming the first epitaxial layer. The C/Si ratio may be not less than 0.5, not less than 0.6, or not less than 0.7 as long as the C/Si ratio is less than 1. Moreover, for example, the C/Si ratio may be not more than 0.95, not more than 0.9, or not more than 0.8.

In the step of reconstructing the surface, there may be used a source material gas different from the source material gas used in each of the step of forming the first epitaxial layer and a below-described step of forming a second epitaxial layer. In this way, it is expected to increase an effect of attaining a shallow pit portion. For example, it is considered to configure such that in each of the step of forming the first epitaxial layer and the below-described step of forming the second epitaxial layer, silane gas and propane gas are used, whereas in the step of reconstructing the surface, dichlorosilane and acetylene are used.

In the step of reconstructing the surface, the ratio of the flow rate of the source material gas to the flow rate of the hydrogen gas may be decreased as compared with those in the step of forming the first epitaxial layer and the below-described step of forming the second epitaxial layer. Accordingly, it is expected to increase the effect of attaining a shallow pit portion.

The flow rate of the hydrogen gas in the mixed gas may be about not less than 100 slm and not more than 150 slm, for example. The flow rate of the hydrogen gas may be about 120 slm, for example. The flow rate of the Si source gas in the mixed gas may be not less than 1 sccm and not more than 5 sccm, for example. The lower limit of the flow rate of the Si source gas may be 2 sccm. The upper limit of the flow rate of the Si source gas may be 4 sccm. The flow rate of the C source gas in the mixed gas may be not less than 0.3 sccm and not more than 1.6 sccm, for example. The lower limit of the flow rate of the C source gas may be 0.5 sccm or 0.7 sccm. The upper limit of the C source gas may be 1.4 sccm or 1.2 sccm.

In the step of reconstructing the surface, it is desirable to adjust various conditions such that etching by the hydrogen gas is comparable to epitaxial growth by the source material gas. For example, it is considered to adjust the flow rate of the hydrogen gas and the flow rate of the source material gas to attain a film formation rate of about 0±0.5 μm/h. The film formation rate may be adjusted to about 0±0.4 μm/h, may be adjusted to about 0±0.3 μm/h, may be adjusted to about 0±0.2 μm/h, or may be adjusted to about 0±0.1 μm/h. Accordingly, it is expected to increase the effect of attaining a shallow pit portion.

A treatment time in the step of reconstructing the surface is about not less than 30 minutes and not more than 10 hours, for example. The treatment time may be not more than 8 hours, may be not more than 6 hours, may be not more than 4 hours, or may be not more than 2 hours.

3. Step (S23) of Forming Second Epitaxial Layer

After reconstructing the surface of the first epitaxial layer, the step of forming the second epitaxial layer on this surface is performed. Second epitaxial layer122(seeFIG. 3) is formed using a source material gas having a C/Si ratio of not less than 1. For example, the C/Si ratio may be not less than 1.05, may be not less than 1.1, may be not less than 1.2, may be not less than 1.3, or may be not less than 1.4 as long as the C/Si ratio is not less than 1. Moreover, the C/Si ratio may be not more than 2.0, may be not more than 1.8, or may be not more than 1.6.

The source material gas in the step of forming the second epitaxial layer may be the same as or different from the source material gas used in the step of forming the first epitaxial layer. The source material gas may be silane gas and propane gas, for example. The flow rate of the silane gas and the flow rate of the propane gas may be adjusted appropriately in a range of about 10 to 100 sccm to achieve a desired C/Si ratio, for example. The flow rate of the carrier gas may be about 50 slm to 200 slm, for example.

The film formation rate in the step of forming the second epitaxial layer may be about not less than 5 μm/h and not more than 100 μm/h, for example. The second epitaxial layer has a thickness of not less than 1 μm and not more than 150 μm, for example. Moreover, the thickness of the second epitaxial layer may be not less than 5 μm, may be not less than 10 μm, and may be not less than 15 μm. Moreover, the thickness of the second epitaxial layer may be not more than 100 μm, may be not more than 75 μm, or may be not more than 50 μm.

The thickness of second epitaxial layer122may be the same as or different from the thickness of first epitaxial layer121. Second epitaxial layer122may be thinner than first epitaxial layer121. For example, a ratio of the thickness of second epitaxial layer122to the thickness of first epitaxial layer121may be about not less than 0.01 and not more than 0.9. Here, the ratio of the thicknesses represents a value obtained by dividing the thickness of the second epitaxial layer by the thickness of the first epitaxial layer having been through the step of reconstructing the surface. The ratio of the thicknesses may be not more than 0.8, may be not more than 0.7, may be not more than 0.6, may be not more than 0.5, may be not more than 0.4, may be not more than 0.3, may be not more than 0.2, or may be not more than 0.1. Accordingly, it is expected to increase the effect of attaining a shallow pit portion.

In this way, as shown inFIG. 3, silicon carbide epitaxial layer120is formed which includes first epitaxial layer121and second epitaxial layer122. In the silicon carbide epitaxial layer, the first epitaxial layer and second epitaxial layer may be incorporated completely such that they cannot be distinguished from each other.

As shown inFIG. 4, groove portion20is formed in first main surface101of silicon carbide epitaxial layer120. Groove portion20extends in the one direction along first main surface101when viewed in plan. More specifically, groove portion20extends in the step-flow growth direction, which is along the off direction of the off angle relative to the (0001) plane. In other words, groove portion20extends in a direction in a range of not more than ±5° relative to the <11-20> direction or a direction in a range of not more than ±5° relative to the <01-10> direction.

The width (second width82) of groove portion20in the above-described one direction is twice or more as large as, preferably, five times or more as large as the width (third width83) thereof in the direction perpendicular to the one direction. Second width82is not less than 15 μm and not more than 50 μm, preferably, not less than 25 μm and not more than 35 μm. Third width83is not less than 1 μm and not more than 5 μm, preferably, not less than 2 μm and not more than 3 μm.

As shown inFIG. 3, groove portion20is formed to extend in the step-flow growth direction from threading dislocation40included in silicon carbide epitaxial layer120. More specifically, groove portion20includes: a first groove portion21formed on threading dislocation40; and a second groove portion22formed to be connected to first groove portion21and extend from first groove portion21in the step-flow growth direction.

First groove portion21is formed at one end portion (left end portion inFIG. 3) of groove portion20in the step-flow growth direction. Moreover, the maximum depth (second depth72) of first groove portion21from first main surface101is not more than 10 nm. Second depth72is the maximum depth in the entire groove portion20as shown inFIG. 3. Moreover, first groove portion21preferably has a width (first width81) of not more than 1 μm, and more preferably has a width (first width81) of not more than 0.5 μm.

As shown inFIG. 3, second groove portion22is formed to extend from its portion of connection with first groove portion21to the other end portion opposite to the above-described one end portion (right end portion inFIG. 3). Moreover, second groove portion22is formed such that the depth (first depth71) of second groove portion22from first main surface101is smaller than the maximum depth (second depth72) of first groove portion21. More specifically, second groove portion22extends in the step-flow growth direction while maintaining the depth shallower than the maximum depth (second depth72) of first groove portion21. First depth71is preferably not more than 3 nm, is more preferably not more than 2 nm, and is further preferably not more than 1 nm. Moreover, second groove portion22has a width (fourth width84) of, for example, not less than 20 μm, preferably, not less than 25 μm.

Next, as a step (S40), an ion implantation step is performed. In this step (S40), as shown inFIG. 11, for example, aluminum (Al) ions are implanted into silicon carbide epitaxial layer120from the first main surface101side, thereby forming body regions62. When viewed in cross section, a region interposed between body regions62is JFET region61. Surface161of JFET region61constitutes a portion of first main surface101. Preferably, body regions62are formed such that the width (fifth width85) of surface161of JFET region61becomes not less than 1.5 μm and not more than 3.5 μm. Preferably, each of body regions62is formed by ion implantation. An implantation mask used for the ion implantation has a width of not more than 2.4 μm, for example. Maximum ion implantation energy is suppressed to not more than 970 keV, for example. The impurity concentration of the portion of body region62in contact with first main surface101is, for example, not less than 1×1016cm−3and not more than 1×1018cm−3. Preferably, JFET region61is formed such that groove portion20is disposed in surface161. More preferably, JFET region61is formed such that first groove portion21is disposed in surface161.

Next, for example, phosphorus (P) ions are implanted into body region62, thereby forming source region63. Next, for example, aluminum (Al) ions are implanted into body region62, thereby forming contact region64adjacent to source region63. In silicon carbide epitaxial layer120, a region in which none of body region62, source region63, and contact region64is formed serves as drift region60. Drift region60includes JFET region61. JFET region61is a region that constitutes a portion of first main surface101and that is interposed between the portions of body regions62. Drift region60includes: a region interposed between JFET region61and silicon carbide substrate110; and a region interposed between each body region62and silicon carbide substrate110. First main surface101is constituted of surface161of JFET region61, surface162of body region62, surface163of source region63, and surface164of contact region64.

Next, an activation annealing step is performed as a step (S50). In this step (S50), for example, as shown inFIG. 11, silicon carbide epitaxial layer120is heated at about 1800° C. in an argon atmosphere, thereby activating each of the n type and p type impurities having been introduced in silicon carbide epitaxial layer120through ion implantation. Accordingly, desired carriers are generated in each of body region62, source region63, and contact region64within silicon carbide epitaxial layer120. In this way, silicon carbide epitaxial layer120is prepared which includes: JFET region61having n type conductivity; body region62provided on drift region60and having p type conductivity different from n type conductivity; and source region63separated from JFET region61by body region62and having n type conductivity.

Next, a gate insulating film forming step is performed as a step (S60). In this step (S60), for example, as shown inFIG. 12, epitaxial wafer100is thermally oxidized in an atmosphere including oxygen (O2), whereby gate insulating film57composed of a material including silicon dioxide (SiO2) is formed on first main surface101. Gate insulating film57is formed in contact with JFET region61, body region62, and source region63. In surface161of JFET region61in contact with gate insulating film57, groove portion20(seeFIG. 3) is formed. Groove portion20extends in one direction along surface161. Second width82of groove portion20, which is a width in one direction, is twice or more as large as third width83of groove portion20, which is a width in a direction perpendicular to the one direction. Second depth72of groove portion20, which is the maximum depth from surface161, is not more than 10 nm. That is, in surface161of JFET region61, pit portion30is suppressed from being formed (FIG. 3), thereby reducing variation in thickness of gate insulating film57formed on surface161of JFET region61. Gate insulating film57has an average film thickness of not less than 40 nm and not more than 100 nm, for example.

Next, a nitrogen annealing step is performed as a step (S65). Specifically, after the step of forming gate insulating film57, gate insulating film57is heated at a temperature of not less than 1100° C. in an atmosphere including nitrogen atoms. Examples of the atmosphere including nitrogen include nitrogen monoxide (NO), dinitrogen oxide (N2O), nitrogen dioxide (NO2), ammonia, and the like. Preferably, epitaxial wafer100having gate insulating film57formed thereon is held for about 1 hour at a temperature of not less than 1100° C. and not more than 1400° C. in a gas including nitrogen, for example.

Next, a gate electrode forming step is performed as a step (S70). In this step (S70), for example, LP (Low Pressure) CVD is employed to form gate electrode51that is in contact with gate insulating film57and that is composed of a conductive material including polysilicon having an impurity added therein. Gate electrode51is formed on gate insulating film57at a location facing surface161of JFET region61, surface162of body region62, and surface163of source region63.

Next, an interlayer insulating film forming step is performed as a step (S80). In this step (S80), for example, CVD is employed to form interlayer insulating film56on gate insulating film57to cover gate electrode51. Interlayer insulating film56is composed of a material including silicon dioxide, for example.

Next, an ohmic electrode forming step is performed as a step (S90). In this step (S90), with reference toFIG. 13, gate insulating film57and interlayer insulating film56are first removed by etching from the region in which source electrode52is to be formed. This leads to formation of a region in which source region63and contact region64are exposed. In this region, a metal film including Ti, Al, and Ni is formed in contact with both source region63and contact region64, for example. Next, the metal film is heated, whereby at least a portion of the metal film is silicided. Accordingly, on first main surface101, source electrode52is formed in contact with both source region63and contact region64.

Next, a pad electrode forming step is performed as a step (S100). In this step (S100), for example, vapor deposition is employed to form source pad electrode54composed of a conductor including aluminum, so as to cover source electrode52and interlayer insulating film56. Next, drain electrode53is formed in contact with second main surface102of silicon carbide substrate110. Next, for example, backside pad electrode55composed of a conductor including aluminum is formed in contact with drain electrode53.

Then, the wafer is divided into a plurality of semiconductor chips through predetermined dicing. In this way, a semiconductor chip including a plurality of unit cells as shown inFIG. 1, i.e., a silicon carbide semiconductor device is obtained.

In the above embodiment, it has been illustrated that the first conductivity type corresponds to n type conductivity and the second conductivity type corresponds to p type conductivity; however, the first conductivity type may correspond to p type conductivity and the second conductivity type may correspond to n type conductivity. Moreover, in the present embodiment, it has been illustrated that the silicon carbide semiconductor device is a planer type MOSFET; however, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor).

Next, the following describes function and effect of the MOSFET and the method for manufacturing the MOSFET according to the present embodiment.

In accordance with MOSFET1000according to the present embodiment, groove portion20is formed in surface161of first impurity region61, surface161being in contact with gate insulating film57, groove portion20extending in the one direction along surface161, second width82of groove portion20, which is the width in the one direction, being twice or more as large as third width83of groove portion20, which is the width in the direction perpendicular to the one direction, second depth72of groove portion20, which is the maximum depth from surface161, being not more than 10 nm. That is, in accordance with MOSFET1000according to the present embodiment, by controlling the conditions for epitaxial growth of silicon carbide epitaxial layer120and the like, a larger number of groove portions20are formed than the above-described pit portions each having a depth of several ten nm. Hence, in MOSFET1000according to the present embodiment, variation in film thickness of gate insulating film57can be reduced as compared with that in the conventional MOSFET in which the multiplicity of pit portions30are formed. As a result, long-term reliability of MOSFET1000is improved.

Moreover, in accordance with MOSFET1000according to the present embodiment, fifth width85is not less than 1.5 μm and not more than 3.5 μm, fifth width85being the width of surface161of JFET region61in the direction along the direction parallel to surface161of JFET region61. By setting fifth width85at not less than 1.5 μm, it is possible to suppress significant increase of transistor resistance resulting from increase of JFET resistance. By setting fifth width85at not more than 3.5 μm, gate insulating film57on JFET region61is protected by depletion from body region62, and increase of on resistance resulting from increase of unit cell area can be suppressed.

Moreover, in accordance with MOSFET1000according to the present embodiment, thickness157of gate insulating film57in the direction perpendicular to surface161of JFET region61is not less than 40 nm and not more than 100 nm. By setting thickness157at not less than 40 nm, reliability of gate insulating film57can be suppressed from being decreased. By setting thickness157at not more than 100 nm, it is possible to suppress increase of voltage applied between gate electrode51and source electrode52and required to turn on the transistor.

Further, in accordance with MOSFET1000according to the present embodiment, the density of nitrogen atoms in boundary region200between gate insulating film57and first impurity region61is not less than 1018cm−3. Accordingly, reliability of gate insulating film57can be improved.

Further, in accordance with MOSFET1000according to the present embodiment, groove portion20includes first groove portion21and second groove portion22connected to first groove portion21. First groove portion21is formed in one end portion of groove portion20in the one direction, and the maximum depth of first groove portion21from surface161is not more than 10 nm. Second groove portion22is formed to extend in the one direction from first groove portion21to the other end portion opposite to the one end portion, and is formed such that first depth71of second groove portion22, which is the depth from surface161, is smaller than the maximum depth of first groove portion21. In MOSFET1000in which groove portion20having the above structure is formed, the formation of pit portions that would have otherwise caused increase of variation in film thickness of gate insulating film57is suppressed. Accordingly, in accordance with MOSFET1000, variation in film thickness of gate insulating film57can be reduced. As a result, long-term reliability of MOSFET1000is improved.

Further, in accordance with MOSFET1000according to the present embodiment, gate insulating film57is provided on first groove portion21. In accordance with MOSFET1000, variation in film thickness of gate insulating film57can be reduced. As a result, long-term reliability of MOSFET1000is improved.

Further, MOSFET1000according to the present embodiment further includes silicon carbide substrate110having an off angle of not more than ±4° relative to the (0001) plane. Silicon carbide epitaxial layer120is a layer epitaxially grown on silicon carbide substrate110. Groove portion20is formed to extend from threading dislocation40in silicon carbide epitaxial layer120in the step-flow growth direction that is along the off direction of the off angle. As described above, groove portion20is formed to extend in the step-flow growth direction. In silicon carbide semiconductor device1000in which such a groove portion20is formed, formation of minute pits that would have otherwise caused decrease of long-term reliability of the device is suppressed. Accordingly, in accordance with MOSFET1000, variation in film thickness of gate insulating film57can be reduced. Accordingly, long-term reliability of MOSFET1000is improved.

Further, in accordance with MOSFET1000according to the present embodiment, the off direction is in a range of not more than ±5° relative to the <11-20> direction. Thus, third main surface103may be inclined relative to the (0001) plane in the predetermined off direction.

Further, in accordance with MOSFET1000according to the present embodiment, the off direction is in a range of not more than ±5° relative to the <01-10> direction. Thus, third main surface103may be inclined relative to the (0001) plane in the predetermined off direction.

In accordance with the method for manufacturing MOSFET1000according to the present embodiment, by controlling the conditions for epitaxial growth of silicon carbide epitaxial layer120and the like, a larger number of groove portions20are formed than the above-described pit portions each having a depth of several ten nm. Accordingly, in accordance with the method for manufacturing MOSFET1000, there can be manufactured MOSFET1000in which variation in film thickness of gate insulating film57is reduced as compared with that in the conventional MOSFET in which the multiplicity of pit portions are formed. That is, MOSFET1000with improved long-term reliability can be manufactured.

Moreover, the method for manufacturing MOSFET1000according to the present embodiment further includes the step of heating gate insulating film57at a temperature of not less than 1100° C. in the atmosphere including nitrogen atoms after the step of forming gate insulating film57. Accordingly, reliability of gate insulating film57can be improved.

1. Production of Sample

Silicon carbide substrates110each having a diameter of 150 mm were prepared. In each of silicon carbide substrates110, the off direction of third main surface103was the <11-20> direction and third main surface103had an off angle of 4° relative to the (0001) plane.

A sample 1 had an epitaxial layer formed using the manufacturing method according to the present disclosure. A sample 2 had an epitaxial layer formed using a manufacturing method obtained by omitting, from the manufacturing method according to the present disclosure, the step (S22) of reconstructing the surface of the first epitaxial layer. In each of sample 1 and sample 2, the epitaxial layer had a film thickness of 15 μm.

2. Evaluation of Shape of Groove Portion

In each sample, the shape of the groove portion formed in first main surface101of silicon carbide epitaxial layer120was evaluated using a defect inspection device and an AFM. The result is shown in Table 1. The defect inspection device as used herein was WASAVI series “SICA 6X” (Objective lens: ×10) provided by Lasertec Corporation.

The AFM as used herein may be “Dimension 300” provided by Veeco, for example. Moreover, for a cantilever (probe) of the AFM, “NCHV-10V” provided by Bruker may be used, for example. For measurement conditions of the AFM, a measurement mode was set at a tapping mode, a measurement area in the tapping mode was set at a square having each side of 20 μm, and a measurement depth was set at 1.0 μm. Moreover, sampling in the tapping mode was performed under conditions that scanning speed in the measurement area was set at 5 seconds for one cycle, the number of data for each scan line was set at 512 points, and the number of the scan lines was set at 512. Moreover, displacement control for the cantilever was set at 15.50 nm.

As shown in Table 1, in sample 1, groove portion20was detected in which second width82was twice or more as large as third width83. Second width82is a width that extends in the step-flow growth direction (i.e., “one direction”) along first main surface101and that is in the step-flow growth direction, and third width83is a width that is in the direction perpendicular to the step-flow growth direction.

Further, as a result of detailed inspection on the shape of groove portion20in sample 1, it was found that a portion exhibiting the maximum depth was included in one end portion within groove portion20. The depth of the portion exhibiting the maximum depth was 3 nm. The depth of a portion extending from this portion to the other end portion was not more than 1 nm. That is, groove portion20in sample 1 included first groove portion21and second groove portion22connected to first groove portion21, wherein first groove portion21was formed at one end portion of groove portion20in the step-flow growth direction, second groove portion22extends in the step-flow growth direction from first groove portion21to the other end portion opposite to the one end portion, and first depth71, which was the depth from first main surface101, was smaller than second depth72, which was the maximum depth of the first groove portion.

On the other hand, in sample 2, a multiplicity of groove portions, i.e., pit portions30, were detected in each of which second width82and third width83were substantially the same and second depth72, i.e., the maximum depth was more than 10 nm. In Table 1, for convenience, the maximum depth of the groove portion in sample 2 is illustrated in the column for the maximum depth of the first groove portion.

3. Evaluation of Variation in Film Thickness of Gate Insulating Film

For each of samples1and2, the ion implantation step (S40) and the activation annealing step (S50) were performed as described above, thereby forming the various impurity regions shown inFIG. 11.

By heating samples1and2in an atmosphere including oxygen, gate insulating film57was formed on first main surface101of silicon carbide epitaxial layer120.

Furthermore, the gate insulating film was observed with a transmission electron microscope to measure variation in film thickness of the gate insulating film. The result is shown in Table 2.

TABLE 2Sample 1Sample 2Film Thickness of Portion Having No5252Groove Portion (nm)Minimum Film Thickness in the5149Vicinity of Groove Portion (nm)Maximum Film Thickness in the5160Vicinity of Groove Portion (nm)Variation in Film Thickness (A/B)−1/−1+8/−3

In the column “Variation in Film Thickness” in Table 2, “A/B” is illustrated to represent a difference (A) between the maximum film thickness in the vicinity of the groove portion and the film thickness of the portion having no groove portion, as well as a difference (B) between the minimum film thickness in the vicinity of the groove portion and the film thickness of the portion having no groove portion. Here, it is indicated that as A and B are both smaller values, variation in film thickness is smaller. As shown in Table 2, the variation in film thickness in sample 1 was smaller than that in sample 2 and therefore sample 1 was excellent.

4. Evaluation of Reliability of Silicon Carbide Semiconductor Device

For each of sample 1 and sample 2, the gate electrode forming step (S70) to the pad electrode forming step (S100) were sequentially performed. Furthermore, the epitaxial wafer was diced, thereby manufacturing22silicon carbide semiconductor devices, serving as MOSFETs, in the form of chips from each sample.

Long-term reliability of each silicon carbide semiconductor device was evaluated using constant current TDDB (Time Dependent Dielectric Breakdown). The constant current TDDB was performed under an environment of 25° C. with a constant current density of 20 mA/cm2. The result is shown inFIG. 14.

FIG. 14is a Weibull plot showing the result of measurement of constant current TDDB. InFIG. 14, the vertical axis represents a cumulative failure rate plotted to a Weibull chart, whereas the horizontal axis represents a Charge to Breakdown (QBD). InFIG. 14, as QBD[unit: C/cm2] is larger, long-term reliability is more excellent. InFIG. 14, a group of plots constituted of circular legends represent the silicon carbide semiconductor devices manufactured from sample 1, whereas a group of plots constituted of quadrangular legends represent the silicon carbide semiconductor devices manufactured from sample 2.

As understood fromFIG. 14, the silicon carbide semiconductor devices manufactured from sample 1 have larger QBDand therefore have more excellent long-term reliability than the silicon carbide semiconductor devices manufactured from sample 2. This result is considered to be obtained because variation in film thickness of the gate insulating film in sample 1 is small.

REFERENCE SIGNS LIST