Dual edge adjusting digital phase-locked loop having one-half reference clock jitter

A digital phase-locked loop having a jitter limited to one-half of a period of the reference clock comprises a generator circuit and a control circuit. The input clock is defined by a plurality of rising edges and falling edges. The generator circuit receives a reference clock and generates the output clock. The phase of the output clock is one of a plurality of selectable phases such that the difference in phases between the output clock and the input clock is limited to one-half of a period of the reference clock once the DPLL locks to the input clock. The control circuit receives the input clock, the reference clock, and the output clock and provides a selection input to the generator circuit to make the phase of the output clock selectable upon each rising edge and upon each falling edge of the input clock.

FIELD OF THE INVENTION 
The present invention pertains to the field of digital communications. More 
particularly, the present invention relates to digital phase-locked loops 
used for providing an output signal which is locked to an input signal. 
BACKGROUND OF THE INVENTION 
Phase-locked loops (PLL's) are commonly used to perform a multitude of 
different functions in electrical and electronic systems. Such functions 
include tone decoding, demodulation of communication signals, frequency 
multiplication, frequency synthesis, pulse synchronization, and signal 
regeneration, for example. In a digital communication system, one 
application of a PLL may be to provide a "clean" clock signal which has 
the same frequency and phase as a received digital data signal that is to 
be decoded. Digital phase-locked loops (DPLL's) are often preferable to 
analog PLL's for this purpose, because they tend to require less time and 
effort to design. 
One problem associated with DPLL's, however, is that, as a result of their 
discrete nature, they normally cannot generate an output clock with a 
phase that is precisely locked to the phase of the input signal. A typical 
DPLL design makes use of a reference clock having a frequency that is much 
higher than that of the data signal to generate the output clock. However, 
a typical DPLL can only guarantee a phase lock to within one clock period 
of the reference clock. This error in the phase lock is referred to as 
"jitter". "Jitter" can be more precisely defined as any short-term 
variations of the significant instances of a digital signal from their 
ideal positions in time. In addition, a typical DPLL will only adjust its 
lock once for every clock cycle of the data signal or the output clock 
(e.g., on every rising edge of the data signal), which limits how quickly 
the DPLL can lock onto the input signal. Consequently, as design 
requirements for the maximum allowable jitter (accuracy of the phase lock) 
and the time-to-lock become more demanding, the required reference clock 
frequency increases. A high reference clock frequency may be undesirable 
for various different reasons, however. 
Therefore, it is desirable to provide a DPLL which has a maximum jitter 
that is less than one full period of the reference clock. It is further 
desirable to provide a DPLL that will adjust its phase lock more 
frequently than once for each period of the data signal or the output 
clock, so that the time required to achieve phase lock may be reduced. 
SUMMARY OF THE INVENTION 
A digital phase-locked loop (DPLL) for generating an output clock having a 
frequency and a phase which are locked to an input clock is described. The 
input clock has a plurality of rising edges and falling edges. The DPLL 
comprises a generator circuit and a control circuit. The generator circuit 
receives a reference clock and generates the output clock. The phase of 
the output clock is one of a plurality of selectable phases, such that the 
difference in phases between the output clock and the input clock is 
limited to one-half of a period of the reference clock once the DPLL is 
locked to the input clock. The control circuit receives the input clock, 
the reference clock, and the output clock and provides a selection input 
to the generator circuit. The control circuit, through the selection 
input, causes the phase of the output clock to be selectable upon each 
rising edge and upon each falling edge of the input clock. 
Other features of the present invention will be apparent from the 
accompanying drawings and from the detailed description which follows 
below.

DETAILED DESCRIPTION 
A digital phase-locked loop (DPLL) for generating an output clock having a 
frequency and a phase which are locked to an input clock is described. In 
the following description, for purposes of explanation, numerous specific 
details are set forth in order to provide a thorough understanding of the 
present invention. It will be evident, however, to one skilled in the art 
that the present invention may be practiced without these specific 
details. In other instances, well-known structures and devices are shown 
in block diagram form in order to avoid unnecessarily obscuring the 
present invention. 
FIG. 1 shows an embodiment of a digital phase locked loop (DPLL) 1 
according to the present invention. The DPLL 1 provides an output clock 
signal CLKOUT which is locked in frequency and phase to an input digital 
data signal DATA. The output clock signal CLKOUT is provided such that the 
difference in phase between the output clock signal CLKOUT and the input 
clock signal CLKIN does not exceed one-half of a period of the reference 
clock signal CLKREF once the lock has been achieved, as will be described 
in detail below. In addition, the DPLL 1 provides for adjustment of the 
phase of the output clock CLKOUT at every rising edge and every falling 
edge of the input clock CLKIN. 
The DPLL 1 is comprised of a generator circuit 100 and a control circuit 
200. The generator circuit receives as input a reference clock signal 
CLKREF and generates as output the output clock signal CLKOUT. The control 
circuit 200 receives as input an input clock signal CLKIN and the output 
clock signal CLKOUT. The control circuit 200 also receives as input the 
reference clock CLKREF and generates as an output a selection signal S to 
the generator circuit 100. The input clock signal CLKIN is the inverted 
form of the digital data signal (i.e., DATA). Consequently, the output 
clock signal CLKOUT will actually be locked 180 degrees out-of-phase with 
the digital data signal DATA and in-phase with the input clock signal 
CLKIN. The frequency of the data signal DATA in the illustrated embodiment 
is 4.096 MHz. The frequency of the reference clock is sixteen times the 
frequency of the data signal DATA, or approximately 65 MHz. Other 
embodiments of the present invention, however, may utilize different 
frequencies. 
The generator circuit 100 is comprised of two D-type flip-flops 110 and 
120, a multiplexor 130, and a frequency divider 140. The multiplexor 130 
has four inputs, one each to receive the outputs Q1 and Q1 of flip-flop 
110 and the Outputs Q2 and Q2 of flip-flop 120. The input of flip-flop 110 
is coupled to receive its output Q1. Similarly, the input of flip-flop 120 
is coupled to receive its output Q2. Flip-flop 110 is clocked by the 
reference clock CLKREF. Flip-flop 120 is clocked by the inverted form of 
the reference clock CLKREF. The multiplexor 130 outputs an intermediate 
clock signal CLKITM to frequency divider 140. The output CLKITM of the 
multiplexor 130 represents one of the four inputs Q1, Q2, Q1, and Q2, 
according to the state of the selection signal S. The frequency divider 
140 receives as input the intermediate clock signal CLKITM and generates 
the output clock signal CLKOUT. In the embodiment of FIG. 1, the frequency 
divider 140 divides the intermediate clock signal CLKITM by a factor of 8 
to produce the output clock signal CLKOUT. 
Referring now to FIG. 2, the control circuit 200 is shown in more detail. 
Control circuit 200 comprises a comparator 210, a state machine 220, and a 
D-type flip-flop 230. The comparator 210 receives the input clock signal 
CLKIN. In addition, the comparator 210 receives the output clock signal 
CLKOUT and a previous state signal PREVVAL. The previous state signal 
PREVVAL is received from the Q output of flip-flop 230. The comparator 210 
generates three output signals which are provided to the state machine 
220: a greater-than signal GT, a less-than signal LT, and an equal-to 
signal EQT. The state machine provides the selection signal S to the 
multiplexor 130. The selection signal S consists of four individual 
selection signals S1, S2, S3, and S4. The state machine also receives as 
input the reference clock CLKREF. The flip-flop 230 receives the output 
clock CLKOUT and is clocked by the reference clock CLKREF. Selection 
signals S1 through S4 correspond to inputs 1 through 4 of the multiplexor 
130, respectively. 
Referring now to FIG. 3, the comparator circuit 210 is shown in detail. The 
comparator circuit 210 is comprised of a comparator 211 and a comparator 
212. Comparators 211 and 212 each receive as input the input clock signal 
CLKIN and the output clock signal CLKOUT. The comparator circuit 210 also 
comprises AND gates 213, 214, 215, 216, and 219, and OR gates 217 and 218. 
Comparator 211 generates two outputs which are separately coupled to an 
input of AND gate 213 and an input of AND gate 214. The outputs of the 
comparator 211 are asserted as a logic high (i.e., logic "1") whenever the 
value of the output clock signal CLKOUT is greater than the value of the 
input clock signal CLKIN. In contrast, comparator 212 generates two 
outputs which are separately coupled to an input AND gate 215 and an input 
of AND gate 216. The outputs of comparator 212 are asserted as a logic 
high whenever the value of the output clock signal CLKOUT is less than the 
value of the input clock signal CLKIN. AND gate 213 also receives as input 
the previous state signal PREVVAL and generates an output coupled to an 
input of the OR gate 217. AND gate 214, in addition to receiving one of 
the outputs from comparator 211, receives as input the signal PREVVAL and 
generates an output which is coupled to one input of OR gate 218. AND gate 
215 receives as input the previous state signal PREVVAL and one of the 
outputs of comparator 212, and generates an output coupled to one of the 
inputs of OR gate 218. AND gate 216 receives one of the outputs of 
comparator 212 and the signal PREVVAL, and provides an output coupled to 
one of the inputs of 0R gate 217. The output of OR gate 217 is the 
greater-than signal GT. The output of OR gate 218 is the less-than signal 
LT. AND gate 218 receives as input the inverted greater-than signal GT and 
the inverted less-than signal LT, and generates as output the equal-to 
signal EQT. The greater-than signal GT, the less-than signal LT, and the 
equal-to signal EQT each are asserted as logic high. Hence, the signals 
GT, LT, and EQT are generated according to the following logic equations: 
EQU GT=((CLKOUT&gt;CLKIN).multidot.(PREVVAL))+((CLKOUT&lt;CLKIN).multidot.(PREVVAL))( 
1) 
EQU LT=((CLKOUT&gt;CLKIN).multidot.(PREVVAL))+((CLKOUT 
&lt;CLKIN).multidot.(PREVVAL))(2) 
EQU EQT=GTLT (3) 
where ".multidot." represents logic AND, and "+" represents logic OR. 
FIGS. 4A and 4B show the state machine 220 in detail with its connection to 
the multiplexor 130. Referring to FIG. 4A, the state machine 220 consists 
of four D-type flip-flops 221, 222, 223, and 224, each of which is clocked 
by the reference clock signal CLKREF. Flip-flops 221 through 224 output 
selection signals S1 through S4, respectively. Selection signals S1 
through S4 correspond to the inputs Q1, Q2, Q1, and Q2 of the multiplexor, 
respectively. The multiplexor outputs an intermediate clock signal CLKITM 
which is at a frequency of one-half the frequency of the reference clock 
signal CLKREF. The inputs to flip-flops 221 through 224 are provided as 
signals D1 through D4, respectively. 
Each of signals D1 through D4 is provided by one of four separate logic 
circuits 225. Logic circuit 225 is shown in FIG. 4B. Although there are 
actually four logic circuits 225, one for each of flip-flops 221 through 
224, only one logic circuit 225 is shown for purposes of clarity. Logic 
circuit 225 generates as output the signal D.sub.n where n equals one, 
two, three, or four, depending upon whether the logic circuit 225 is 
associated with flip-flop 221, 222, 223, or 224. Each of the four logic 
circuits 225 consists of three AND gates 226, 227, 228, and an OR gate 
229. OR gate 229 receives as input the outputs of AND gates 226, 227, and 
228, and generates as output the signal Dn. AND gate 226 receives as input 
the equal-to signal EQT and one of the selection signals S.sub.n 
corresponding to one of the outputs of the flip-flops 221 through 224. AND 
gate 227 receives as input the greater-than signal GT and one of the 
selection signals S.sub.(n+1) corresponding to an output of another one of 
the flip-flops 221 through 224. Similarly, AND gate 228 receives as input 
the less-than signal LT and one of the selection signals S.sub.(n-1) 
corresponding to an output of one of the flip-flops 221 through 224. Note 
that the values of n "wrap around", such that if "n"=1, then "n-1" is 4; 
likewise if "n"=4 then "n+1" is 1. Hence, each of the flip-flops 221 
through 224 is driven by one of four logic circuits 225 such that the 
inputs D1 through D4 are dependent upon the signals EQT, GT, and LT as 
well as the present state of that flip-flop and the present state of two 
of the other flip-flops 221 through 224. The function of the state machine 
220 is described by the state diagram shown in FIG. 5. The state machine 
220 has four states, Q1, Q2, Q1, and Q2 corresponding to the selection 
signals S1 through S4, respectively. The inputs D.sub.n to the flip-flops 
221 through 224 are generated according to the following equation: 
EQU Dn=(EQT.multidot.Sn)+(GT.multidot.S(n+))+(LT.multidot.S(n-1))(4) 
The operation of the DPLL 1 will now be described. Referring to FIGS. 1 and 
2, flip-flops 110 and 120 are coupled so that their respective outputs Q1, 
Q1, Q2, and Q2 each are provided at a frequency of one-half the frequency 
of the reference clock CLKREF. A further effect of the coupling of 
flip-flops 110 and 120 is that signals Q1, Q1, Q2, and Q2 are provided at 
phases that are spaced 90 degrees apart. Specifically, Q1 is in-phase with 
the reference clock CLKREF, while signal Q1 lags signal Q1 in phase by 90 
degrees. Similarly, signal Q2 lags signal Q1 in phase by 90 degrees and 
signal Q2 lags Q2 in phase by 90 degrees. The phase and frequency 
characteristics of signals Q1, Q1, Q2, and Q2 can be seen in the timing 
diagram of FIG. 7. The 90 degree phase difference between each of signals 
Q1, Q1, Q2, and Q2 is equal to a phase difference of one-half of a clock 
period of the reference clock CLKREF. Therefore, the multiplexor 130 
provides at its output one of four clock signals differing in phase by 
one-half of a period of the reference clock CLKREF, so that the maximum 
jitter when the DPLL 1 is phase-locked is one-half of a clock period of 
the reference clock CLKREF. 
The comparator circuit 210 generates signals GT, LT, and EQT according to 
equations (1), (2), and (3), above. Flip-flop 230 stores the last state of 
the output clock CLKOUT, which is output to the comparator circuit 210 as 
the previous state signal PREVVAL. The previous state signal PREVVAL is 
used by the comparator circuit 210 essentially as an indication of whether 
the next edge of the input clock signal CLKIN will be a rising edge or a 
falling edge. Specifically, a value of "0" for PREVVAL indicates that the 
next edge of the input clock CLKIN will be a rising edge, whereas a value 
of "1" for PREVVAL indicates that the next edge will be a falling edge. 
Referring again to FIG. 5, the state machine has four states, Q1, Q2, Q1, 
and Q2, as described earlier. An equal-to EQT output from the comparator 
circuit 210 indicates that the output clock signal CLKOUT and the input 
clock signal CLKIN have equal value. If the state machine receives an 
equal-to EQT input when it is clocked, then the state will remain the 
same, and whichever input of the multiplexor 130 (Q1, Q2, Q1, and Q2) is 
presently selected will remain selected. When the state machine is in 
state Q1, for example, a greater-than output GT from the comparator 
circuit 210 will cause the state machine to assert only signal S4, causing 
the Q2 input to the multiplexor 130 to be selected. Similarly, when the 
state Q2 has been selected, a greater-than GT output from the comparator 
circuit 210 will cause only the signal S3 to be asserted, causing the Q1 
input of the multiplexor to be selected, and so forth. If the state Q1 is 
presently selected, then a less-than LT output from the comparator circuit 
210 will cause only the signal S2 to be asserted, causing the input Q2 of 
the multiplexor 130 to be selected. Therefore, the state machine 220 
functions by selecting one of signals Q1, Q2, Q1, or Q2 to most closely 
match the phase of the input clock signal CLKIN. The DPLL 1 is accurate to 
within one-half of a clock period of the reference clock signal CLKREf 
FIG. 6 shows a timing diagram associated with the DPLL 1. The case is 
illustrated where DPLL 1 progresses from a condition where the output 
clock CLKOUT is completely out-of-phase with the input clock CLKIN and 
then progresses gradually to a locked state. This progression can be seen 
easily by the repeated assertion of less-than LT pulses until the output 
clock CLKOUT is locked in frequency and phase to the input clock CLKIN. 
The progression can further be seen by the gradual narrowing over time of 
less-than LT pulses and the consequent lengthening over time of the 
equal-to EQT pulses. The locked condition occurs at approximately time 
point 300 on the timing diagram of FIG. 6. At point 300, the less-than LT 
pulses have ceased to be asserted and the greater-than GT pulses GT begin 
to be asserted to hold the DPLL 1 in the locked condition. In the locked 
condition, the equal-to EQT signal will remain asserted most of the time, 
with occasional greater-than GT or less-than LT pulses being asserted in 
order to maintain the lock. 
FIG. 7 shows certain ones of the waveforms in FIG. 6 on an expanded time 
scale, corresponding to the period in FIG. 6 from time point 350 to time 
point 360 (after lock has been achieved). The inherent jitter of the DPLL 
1 is illustrated by the space between points 310 and 320 on the waveform 
of the output clock signal CLKIN. At point 310, the DPLL is in state Q2. 
At point 310, the input clock CLKOUT goes high but the output clock CLKOUT 
remains low, creating a phase difference between the two signals. The 
greater-than signal GT is asserted because the value of the input clock 
CLKIN is greater than the value of the output clock CLKOUT and a rising 
edge of the output clock CLKOUT is about to occur (see equation (1)). 
However, there is no change in state of the DPLL 1, because signal Q2 
(and, therefore, signal CLKOUT) goes high before the next rising edge of 
the reference clock CLKREF occurs. Note, however, that the jitter 
illustrated between points 310 and 320 does not exceed one-half of a clock 
period of the reference clock CLKREF. 
The next transition of the input clock CLKIN occurs at point 330. At point 
330, the output clock signal CLKOUT has not transitioned to a low state 
even though the input clock CLKIN already has. Consequently, a greater 
than signal GT is asserted at point 330. Upon the next rising edge of the 
reference clock CLKREF, which occurs at point 340, the DPLL 1 transitions 
from state Q2 to Q1, so that the phase of the output clock CLKouT is more 
closely matched to the phase of the input clock CLKIN. 
Hence, the DPLL 1 adjusts the phase of its output clock signal CLKOUT at 
each rising edge and at each falling edge of the input clock CLKIN. 
Furthermore, the DPLL 1 provides the output clock CLKOUT at the same 
frequency as the input data signal DATA with a phase lock having jitter 
that will not exceed one-half of a clock period of the reference clock 
CLKREF. 
Although the present invention has been described with reference to 
specific exemplary embodiments, it will be evident that various 
modifications and changes may be made to these embodiments without 
departing from the broader spirit and scope of the invention as set forth 
in the claims. Accordingly, the specification and drawings are to be 
regarded in an illustrative rather than a restrictive sense.