MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A memory device and its manufacturing method are provided. Memory cells of the memory device arranged in an array respectively include an access transistor and a storage capacitor connected to the access transistor through a capacitor contact (CC) structure. Based on a specific arrangement manner, the CC structures are closely arranged in pairs. Each pair of the CC structures are connected to a neighboring access transistor and isolated from each other through an isolation wall. Each isolation wall includes an inner wall and outer walls located on opposite sides of the inner wall. The inner wall has sufficient etch selectivity with respect to the outer walls. Despite etchants or reactive substances inevitably consume the outer walls during manufacturing, the etchants or the reactive substances may be blocked by the inner wall without penetrating the entire isolation wall. Therefore, an electrical isolation between the neighboring CC structures may be guaranteed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan patent application serial no. 112111166, filed on Mar. 24, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a memory device and a manufacturing method thereof; more particularly, the disclosure relates to a dynamic random access memory (DRAM) device and a manufacturing method thereof.

Description of Related Art

A dynamic random access memory (DRAM) is a volatile memory which has been widely applied. Each DRAM cell includes an access transistor and a storage capacitor connected to the access transistor. With the development of a manufacturing process of the DRAM, an integration density of the DRAM continues to increase. Such an increase in the integration density includes shortening pitches of active regions of the access transistors. Thereby, two capacitor contact (CC) structures configured to connect the adjacent access transistors to the corresponding storage capacitors become very close, thus leading to a short circuit issue.

SUMMARY

An embodiment of the disclosure provides a memory device that includes a semiconductor substrate, a first word line and a second word line, a first capacitor contact (CC) structure and a second CC structure, and an isolation wall. The semiconductor substrate has a first active region and a second active region separated by a trench isolation structure. The first word line and the second word line are embedded in the semiconductor substrate, where the first word line and the second word line are spaced from each other in a first direction and extend along a second direction substantially orthogonal to the first direction and penetrate the first active region and the second active region spaced from each other in the second direction The first CC structure and a second CC structure are disposed on the semiconductor substrate and located on opposite sides of the first word line and the second word line, where the first CC structure overlaps and is connected to the first active region, the second CC structure overlaps and is electrically connected to the second active region, and the first CC structure and the second CC structure are arranged along the first direction. Two opposite sides of the isolation wall contact the first CC structure and the second CC structure, and the isolation wall includes an inner wall and outer walls covering two opposite sides of the inner wall, where an insulation material of the inner wall has etch selectivity with respect to an insulation material of the outer walls.

Another embodiment of the disclosure provides a manufacturing method of a memory device, and the manufacturing method includes following steps. A trench isolation structure is formed in a semiconductor substrate to define a first active region and a second active region spaced from each other. A first word line and a second word line are formed in the semiconductor substrate, where the first word line and the second word line are spaced from each other in a first direction and, along a second direction substantially orthogonal to the first direction, penetrate the first active region and the second active region spaced from each other in the second direction. A first CC structure and a second CC structure are formed on the semiconductor substrate, where the first word line and the second word line extend between the first CC structure and the second CC structure, the first CC structure overlaps and is connected to the first active region, the second CC structure overlaps and is connected to the second active region, and the first CC structure and the second CC structure are arranged along the first direction. An isolation wall is set on the semiconductor substrate, where two opposite sides of the isolation wall contact the first CC structure and the second CC structure, the isolation wall includes an inner wall and outer walls covering two opposite sides of the inner wall, and an insulation material of the inner wall has etch selectivity with respect to an insulation material of the outer walls.

To make the above more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

DESCRIPTION OF THE EMBODIMENTS

FIG.1Ais a schematic plane view illustrating a portion of a memory device10according to some embodiments of the disclosure. A memory device10is a DRAM array that includes a plurality of DRAM cells. Each DRAM cell includes an access transistor and a storage capacitor connected to the access transistor. To clearly illustrate a CC structure configured to connect the access transistor to the storage capacitor,FIG.1Adoes not show the storage capacitor covering the CC structure. In addition,FIG.1Adoes not show most of the insulation components. At least one of the insulation components will be described with reference toFIG.1BandFIG.1C.

With reference toFIG.1A, the memory device10includes a plurality of active regions100. Each of the active regions100may be a portion of a semiconductor substrate (e.g., a semiconductor substrate114which will be described with reference toFIG.1BandFIG.1C). A trench isolation structure102formed in the semiconductor substrate laterally surrounds each of the active regions100, so that the neighboring active regions100are electrically isolated from each other.

The active regions100are arranged in an array along a direction D1and a direction D2which intersects (e.g., is orthogonal to) the direction D1. In addition, each of the active regions100may extend along a direction D3intersecting the direction D1and the direction D2. Moreover, the active regions100that are arranged in each column and along the direction D2may be mirror-symmetrical to the active regions100in the neighboring column.

Along the direction D2, a plurality of word lines104penetrate the active regions100arranged in an array. The access transistor of each DRAM cell is defined to be at an intersection of one of the word lines104and one of the active regions100. For each access transistor, the word line104passing through the access transistor serves used as a gate of the access transistor, and portions of the active region100which are located on two sides of the word line104and on which the access transistor is located serve as a drain and a source of the access transistor. In order to allow the two access transistors to share one active region100, each of the active regions100intersects a pair of word lines104. As such, a portion of each active region100located between the two word lines104intersecting the active region100may serve as a common drain/source of the two access transistors sharing the active region100.

A plurality of bit lines106extend above the semiconductor substrate along the direction D1and intersect one row of active regions100, respectively. The portion of each active region100acting as the common drain/source may be connected to an overlying bit line106through a bit line contact structure108. As mentioned above, the portion of each active region100acting as the common drain/source may be the portion located between the two word lines104intersecting the active region100. Therefore, each active region100may be overlapped with an overlying bit line contact structure108and an overlying bit line106through the portion located between the two word lines104intersecting the active region100.

On the other hand, the portions of each active region100which are located on two sides of the word line104intersecting the active region100are respectively connected to the overlying storage capacitor (not shown) through a CC structure110. In other words, each active region100and two CC structures110are overlapped. Since each active region100extends along the direction D3intersecting the direction D1(the row direction) and the direction D2(the column direction), the two CC structures110overlapping the active region100are also arranged along the direction D3. In addition, the active regions100in each column are mirror-symmetrical to the active regions100in the adjacent column, so that all CC structures110may be arranged in an array along the direction D1and the direction D2. In each row, the CC structures110are arranged in pairs. Each pair of the CC structures110overlap the neighboring active regions100in the same column and adjoin each other.

A plurality of isolation walls112arranged in an array are configured to provide electrical isolation between the CC structures110. Each isolation wall112is disposed on a pair of the neighboring CC structures110in the same row and may overlap two word lines104between the pair of the contact structures110. Since the pair of the neighboring CC structures110in the same row overlap the neighboring active regions100in the same column, the isolation wall112located between each pair of the CC structures110overlaps the trench isolation structure102extending between the active regions100. In addition, each isolation wall112is laterally spaced from the neighboring isolation walls112. As mentioned above, the CC structures110are arranged in an array along the direction D1and the direction D2. As such, the isolation wall112respectively located between the neighboring CC structures110arranged in pairs in each row is also arranged in an array along the direction D1and the direction D2. The isolation wall112in each column may be alternately arranged with a plurality of bit line contact structures108, and two CC structures110are disposed between the neighboring isolation walls112in each row.

FIG.1Bis a schematic cross-sectional view taken along a line X1-X1′ depicted inFIG.1A, andFIG.1Cis a schematic cross-sectional view taken along a line X2-X2′ depicted inFIG.1A. With reference toFIG.1AandFIG.1B, the trench isolation structure102extends from a top surface of the semiconductor substrate114into the semiconductor substrate114and defines a plurality of active regions100. It can be seen fromFIG.1Bthat the word lines104are embedded in the semiconductor substrate114and may pass through the trench isolation structure102. In addition, the word lines104may be formed at bottoms of trenches deep into the semiconductor substrate114, and upper portions of these trenches are filled with insulation plugs116. Besides, an inner surface of each trench may be lined with a gate dielectric layer118, so that the word line104and the insulation plug116therein are covered by the gate dielectric layer118.

FIG.1Balso shows two pairs of the CC structures110in the same row. The CC structures110are located above the semiconductor substrate114. It can be seen fromFIG.1AandFIG.1Bthat each pair of the CC structures110overlap two neighboring active regions100laterally separated by a portion of the trench isolation structure102, and the isolation wall112configured for separation covers the portion of the trench isolation structure102. In addition, a pair of the word lines104below each isolation wall112extend and pass through the trench isolation structure102, so that each isolation wall112also overlaps a pair of the word lines104and the surrounding insulation plugs116and the surrounding gate dielectric layers118.

Each isolation wall112includes an inner wall120and transistors. Thereby outer walls122covering two opposite sides of the inner wall120, so that the inner wall120laterally contacts a pair of the CC structures110through the outer walls122on both sides of the inner wall120. The inner wall120and the outer walls122are made of different insulation materials. In particular, the inner wall120has sufficient etch selectivity with respect to the outer walls122, so that etchants or reactive substances, even if they enter the outer walls122during manufacturing, may be blocked by the inner wall120without penetrating the entire isolation wall112. As such, the electrical isolation between the neighboring CC structures110may be guaranteed more effectively. In other words, the neighboring DRAM cells may be prevented from interfering with each other. As an example, a material of the outer walls122may include silicon oxide, while a material of the inner wall120may include silicon nitride. However, people skilled in the pertinent art may change the combination of the materials of the inner wall120and the outer walls122according to the manufacturing requirements, as long as the material of the inner wall120has sufficient ability to block the etchants that are able to etch the outer walls122.

In some embodiments, each isolation wall112further includes a liner layer124that covers outer surfaces of the outer walls122. In these embodiments, the inner wall120of each isolation wall112is in lateral contact with a pair of the CC structures110through the outer walls122and the liner layer124. The liner layer124is also made of an insulation material. For instance, a material of the liner layer124may be silicon oxide.

In some embodiments, a top surface of the inner wall120and top surfaces of the outer walls122(and a top surface of the liner layer124) are substantially coplanar and collectively define a top surface of the isolation wall112. Besides, in some embodiments, the top surface of the isolation wall112is substantially coplanar with a top surface of the CC structure110.

With reference toFIG.1AandFIG.1C, each active region100is penetrated by two word lines104(and the surrounding insulation plug116and the surrounding gate dielectric layer118) intersecting the active region100. A portion of each active region100located between the two word lines104intersecting the active region100may serve to define the common drain/source of the two access transistors located in the active region100and may be connected to one of the bit lines106through the overlying bit line contact structure108. In some embodiments, an insulation pattern126may be disposed between the neighboring bit line contact structures108, the bit line contact structures108and the insulation pattern126are embedded in a dielectric layer128, and the bit line106extends on the dielectric layer128. Although the bit line106is shown to have a double-layer structure, the bit line106may also have a single-layer structure or a multi-layer structure having at least three layers. Additionally, in some embodiments, the bit line106is covered by another dielectric layer130.

It may be seen fromFIG.1BandFIG.1Cthat a top surface of the bit line106may be lower than the top surfaces of the CC structures110and the top surface of the isolation wall112, and the bit line contact structures108are located below the bit line106.

Although more cross-sectional views are not provided for description, more insulation features may be disposed on the semiconductor substrate114to ensure the electrical insulation between the bit line contact structures108, the CC structures110, and the bit line106. In addition, although not shown in the drawings, the CC structures110are respectively connected to the overlying storage capacitors. In some embodiments, all of the storage capacitors may have respective lower electrodes but share the dielectric layer and the upper electrode.

FIG.2is a flowchart illustrating a method of forming the structure depicted inFIG.1AtoFIG.1Caccording to some embodiments of the disclosure.FIG.3AtoFIG.3Vare schematic cross-sectional views illustrating an intermediate structure during a period in which the method depicted inFIG.2is performed. In particular,FIG.3A,FIG.3C,FIG.3E,FIG.3G,FIG.3I,FIG.3K,FIG.3M,FIG.3O,FIG.3Q,FIG.3S, andFIG.3Uare schematic cross-sectional views taken along the line X1-X1′, respectively, andFIG.3B,FIG.3D,FIG.3F,FIG.3H,FIG.3J,FIG.3L,FIG.3N,FIG.3P,FIG.3R,FIG.3T, andFIG.3Vare schematic cross-sectional views taken along the line X2-X2′, respectively.

With reference toFIG.2,FIG.3AandFIG.3B, in step S200, an access transistor is formed in the semiconductor substrate114and the bit line contact structures108and the bit lines106are formed on the semiconductor substrate114through a series of manufacturing processes. The access transistor may be formed by forming the trench isolation structure102in the semiconductor substrate114to define an array of the active regions100, and a plurality of pairs of the word lines104(and the surrounding insulation plugs116and the gate dielectric layers118) penetrating the active regions100are formed along the direction D2. In addition, along with the formation of the bit line contact structures108and the bit lines106, the insulation patterns126and the dielectric layers128and130described with reference toFIG.1Care also formed on the semiconductor substrate114. In addition, the insulation layer300is further formed on the semiconductor substrate114. The insulation layer300fills the space between the bit lines106and may be formed at a height higher than the height of the dielectric layer130, so that the dielectric layer130is covered by a portion of the insulation layer300. Besides, a mask layer302may be further formed on the insulation layer300. In some embodiments, the mask layer302may have a multi-layer structure.

With reference toFIG.2,FIG.3C, andFIG.3D, in step S202, a plurality of trenches304are formed in the current structure. Each trench304extends continuously between a pair of the word lines104and overlaps the bit line contact structures108in one column. A method for forming the trenches304includes forming a photoresist pattern306on the mask layer302, where an opening of the photoresist pattern306defines positions of the trenches304, and performing an etching process by applying the photoresist pattern306as an etching mask. In addition, the photoresist pattern306may be removed by, for instance, performing an ashing process before performing the following operations.

As shown inFIG.3CandFIG.3D, the trenches304extend on the semiconductor substrate114but do not enter the semiconductor substrate114. In addition, each trench304may include a deep portion304dand a shallow portion304alternately arranged along the direction D2. As shown inFIG.3C, each deep portion304doverlaps the trench isolation structure102and penetrates the mask layer302and the insulation layer300to reach the top surface of the trench isolation structure102. On the other hand, as shown inFIG.3D, each shallow portion304soverlaps a portion of the active region100located between two word lines104intersecting the active region100and the overlying bit line contact structure108and the overlying bit line106and penetrates the mask layer302and the insulation layer300to reach the top surface of the dielectric layer130. Compared to bottoms of the deep portions304d, bottoms of the shallow portions304sare higher than the semiconductor substrate114.

With reference toFIG.2,FIG.3E, andFIG.3F, in step S204, the trenches304are filled with an insulation material308. In addition to filling the trenches304, the insulation material308may further extend to a top surface of the mask layer302.

With reference toFIG.2,FIG.3G, andFIG.3H, in step S206, the current structure is planarized until the top surface of the dielectric layer130is exposed. Thereby, the insulation material308, the insulation layer300, and the mask layer302located above the dielectric layer130are removed. As a result, the insulation material308is patterned to form a plurality of separate insulation structures308a.

With reference toFIG.2,FIG.3I, andFIG.3J, in step S208, a mask layer310and a photoresist pattern312are formed on the exposed insulation layer300and the dielectric layer130. In some embodiments, the mask layer310may have a multi-layer structure. On the other hand, the photoresist pattern312has a plurality of separate bar-shaped portions respectively overlapping a pair of the word lines104as well as an insulation structure308aand a bit line contact structure108which are alternately arranged above the pair of the word lines104, respectively. As shown inFIG.3I, a width of each bar-shaped portion of the photoresist pattern312is greater than a width of the overlapping insulation structure308a, so that portions of the insulation layer300located on both sides of each insulation structure308aare also covered by the photoresist pattern.312covers.

With reference toFIG.2,FIG.3K, andFIG.3L, in step S210, one or more etching processes are performed by applying the photoresist pattern312as a mask. Firstly, one portion of the mask layer310not covered by the photoresist pattern312is removed, and the other portion of the mask layer310overlapping the photoresist pattern312is kept to form a plurality of bar-shaped hard masks310a. As shown inFIG.3KandFIG.3L, one portion of each hard mask310acovers one insulation structure308aand the portions of the insulation layer300located on both sides of the insulation structure308a, and the other portion of each hard mask310acovers a portion of the dielectric layer130overlapping one bit line contact structure108. In the etching process, as shown inFIG.3K, one portion of the insulation layer300not covered by the hard mask310ais removed, while the other portion of the insulation layer300located on both sides of each insulation structure308aand covered by the hard mask310ais kept to form the insulation structure300a. On the other hand, as shown inFIG.3L, one portion of the dielectric layer130not covered by the hard mask310ais recessed downward with respect to the other portion of the dielectric layer130covered by the hard mask310a. As a result, a surface of the dielectric layer130has protruding structures each respectively overlapping one hard mask310a. Before the next step is performed, the photoresist pattern312is removed by, for instance, performing an ashing process, and the hard mask310ais left.

So far, a plurality of wall structures WS extending along the direction D2have been formed on the semiconductor substrate114and the dielectric layer130, and each of the wall structures WS includes one hard mask310a, the underlying insulation structures308aand300a, and the protruding structure of the dielectric layer130.

With reference toFIG.2,FIG.3M, andFIG.3N, in step S212, multiple pairs of liner layers314covering opposite sides of each wall structure WS are formed. Each pair of the liner layers314cover the opposite sides of one hard mask310aand extend to sides of the underlying insulation structure300aand the underlying protruding structure of the dielectric layer130. In some embodiments, the liner layers314do not extend along a top surface of the wall structure WS (i.e., the top surface of the hard mask310a) and the surface of the semiconductor substrate114. Before the liner layers314are formed, a cleaning process, e.g., a plasma cleaning process may be performed. During the cleaning process, reactive substances may etch outer insulation structures300aof the wall structures WS. However, based on the etch selectivity of inner insulation structures308aof the wall structures WS with respect to the etch selectivity of the outer insulation structures300a, the inner insulation structures308amay block the reactive substances and thereby prevent leakage paths that penetrate the wall structures WS from being formed. A method of forming the liner layers314may include forming a material layer covering the entire surface by performing a deposition process and removing a horizontal extension portion of the material layer by anisotropic etching, so that the material layer is patterned to form a liner layer14. In subsequent steps, the liner layers314are processed to form the liner layer124described with reference toFIG.1B.

With reference toFIG.2,FIG.3O, andFIG.3P, in step S214, the current structure is covered by a conductor material316. Specifically, the conductor material316may fill up the trench defined between the neighboring wall structures WS and may be further extended above the wall structures WS to cover the hard masks310a. In some embodiments, the conductor material316may be composed of polysilicon. In subsequent steps, the conductor material316is thinned down and patterned to form the CC structures110described with reference toFIG.1AandFIG.1B.

With reference toFIG.2,FIG.3Q, andFIG.3R, in step S216, a height of the conductor material316is reduced to be lower than the top surfaces of the wall structures WS, so that the top portions of the wall structures WS and the top portions of the liner layers314are exposed. Specifically, the top portions of the hard masks310aand the top portions of the liner layers314protrude from the thinned conductor material316. In some embodiments, the top surface of the conductor material316is currently lower than the top surfaces of the insulation structures300aand308a, so that the top portions of the insulation structures300aand308aalso protrude from the conductor material316. Furthermore, in some embodiments, a method for thinning down the conductor material316includes an etch-back process.

With reference toFIG.2,FIG.3S, andFIG.3T, in step S218, a mask layer318is formed on the current structure. The mask layer318covers the conductor material316and conformally covers portions of the wall structures WS and the liner layers314protruding from the conductor material316. Thereby, the horizontal extension portion of the mask layer318extends along the conductor material316and the top surfaces of the wall structures WS (i.e., the top surfaces of the hard masks310a), and a vertical extension portion of the mask layer318extends along the surfaces of the liner layers314protruding from the conductor material316.

With reference toFIG.2,FIG.3U, andFIG.3V, in step S220, the mask layer318and the conductor material316are patterned. One or more anisotropic etching processes may be performed to selectively remove a portion of the mask layer318and a portion of the conductor material316. During etching, the horizontal extension portion of the mask layer318covering the top surfaces of the hard masks310aand the conductor material316may be selectively removed at first, and the vertical extension portion of the mask layer318covering the liner layers314may be at least partially left, so as to form additional hard masks318aextending in pairs to two opposite sides of each wall structure WS. Subsequently, one portion of the conductor material316not covered by the hard masks318ais selectively removed to expose the underlying structure (e.g., the trench isolation structure102shown inFIG.3Uand the dielectric layer130shown inFIG.3V). On the other hand, the other portion of the conductor material316overlapping the hard masks318is left to form conductor structures316alocated on the two opposite sides of each wall structure WS.

At this time, each wall structure WS and the liner layers314and the conductor structures316aon both sides of the wall structure WS extend continuously along the direction D2. Here, each wall structure WS and the conductor structures316aon both sides of the wall structure WS have a relatively large height between the neighboring bit lines106(as shown inFIG.3U) and have a relatively small height above the bit lines106(as shown inFIG.3V).

Subsequently, in step S222, a planarization process is performed until the structure above the dielectric layer130is removed. The resultant structure is shown inFIG.1AtoFIG.1C. During the planarization process, the top portion of each wall structure WS (including the top portions of the hard masks310a, the top portions of the insulation structures308aand300a, and the protruding structure of the dielectric layer130) and the top portions of the liner layers314are removed and cut off to form a plurality of portions respectively located between the neighboring bit lines106. The remaining portions of the wall structures WS and the liner layers314form the isolation wall112shown inFIG.1AandFIG.1B. Here, the remaining portion of the insulation structure308aforms the inner wall120of the isolation wall112, the remaining portion of the insulation structure300aforms the outer walls122of the isolation wall112, and the remaining portions of the liner layers314form the liner layers124of the isolation wall112. In addition, while the wall structures WS and the liner layers314are patterned, the top portions of the conductor structures316aand the hard masks318aare removed. As a result, the remaining portions of the conductor structures316aform the CC structures110.

Although not shown in the drawings, the storage capacitors may be subsequently formed on the CC structures110to form a complete DRAM array.

To sum up, a memory device is provided in one or more embodiments of the disclosure. Each of the memory cells of the memory device arranged in an array respectively includes an access transistor and a storage capacitor. The access transistor of each memory cell is connected to the corresponding storage capacitor through the CC structure. Based on a specific arrangement manner, the CC structures are arranged in pairs and adjoin. Each pair of the neighboring CC structures are connected to the neighboring access transistor and physically and electrically isolation from each other through the isolation wall. Each isolation wall includes the inner wall and the outer walls extending to the two opposite sides of the inner wall. The inner wall has sufficient etch selectivity with respect to the etch selectivity of the outer walls. Even if the etchants or the reactive substances etch the outer walls during manufacturing, the etchants or the reactive substances may be blocked by the inner wall without penetrating the entire isolation wall. Therefore, the electrical isolation between the neighboring CC structures may be guaranteed, and the mutual interference of the adjacent memory cells may be effectively avoided.