Data storage devices and related methods to secure host memory buffers with low latency

Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller of a data storage device that is coupled to one or more memory devices is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a data storage device uses simultaneous memory sensing operations and validity checking operations to facilitate low latency.

Description of the Related Art

Host memory buffers (HMBs) of host devices used in conjunction with data storage devices, such as solid-state drives (SSDs), can be subjected to security attacks, such as network attacks including replay attacks and/or playback attacks. Such attacks can expose host devices and hinder performance. However, efforts to secure HMBs of host devices against such attacks can result in latency delays, such as latency delays of 4 μSec (microseconds) or more.

Therefore, there is a need in the art for data storage devices that practically and simply secure HMBs while facilitating reduced latency and heightened performance.

SUMMARY OF THE DISCLOSURE

Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller of a data storage device that is coupled to one or more memory devices is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.

In one embodiment, a data storage device comprises one or more memory devices, and a controller coupled to the one or more memory devices. The controller is configured to fetch a command from a host device, and the host device includes a host memory buffer (HMB). The controller is configured to fetch entry data from the HMB in response to the command from the host device. The controller is configured to fetch read data from the one or more memory devices using the entry data. The controller is configured to conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.

In one embodiment, a data storage device comprises one or more memory devices, and a controller coupled to the one or more memory devices. The controller is configured to fetch a command from a host device. The host device includes a host memory buffer (HMB), and the HMB includes a Merkle tree having a plurality of hashes. The controller is configured to fetch entry data from the HMB in response to the command from the host device. The controller is configured to fetch read data from the one or more memory devices using the entry data. The controller is configured to conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices. The validity check includes comparing a signature of a top level hash of the plurality of hashes to a stored signature that is stored within the controller, and determining if the signature is the same as or different from the stored signature.

In one embodiment, a data storage device comprises means for fetching a command from a host device, and the host device includes a host memory buffer (HMB). The data storage device includes means for fetching entry data from the HMB in response to the command from the host device. The data storage device includes means for fetching read data from one or more memory devices using the entry data. The data storage device includes means for conducting a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and means for transmitting validity result data to the host device.

DETAILED DESCRIPTION

Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller of a data storage device that is coupled to one or more memory devices is configured to receive a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.

FIG.1is a schematic view of a Merkle tree100, according to one implementation. The Merkle tree100includes data, such as entry data that corresponds to data stored in one or more memory devices. The data is stored in a plurality of data blocks101-104. The Merkle tree100is part of a host device, such as an operating system of a host device. The Merkle tree100includes a first plurality of hashes111-114of a first hash level110and a second plurality of hashes121,122of a second hash level120. The first plurality of hashes111-114are created using the plurality of data blocks101-104. Each hash of the first plurality of hashes111-114corresponds to a data block of the plurality of data blocks101-104. The second plurality of hashes121,122are created by combining hashes of the first plurality of hashes111-114. The Merkle tree100includes a top level hash131of a top hash level130. The top hash level130includes a signature that is created using all of the hashes of the Merkle tree100. The signature of the top level hash131is created by combining the two hashes121,122of the hash level (e.g., the second hash level120) that is disposed immediately below the top hash level130. The top hash level130includes a single hash (e.g., the top level hash131). As the Merkle tree100moves upward from the plurality of data blocks101-104and toward the top level hash131, the hashes of each hash level110,120are progressively combined until the signature of the single top level hash131is created for the top hash level130.

The Merkle tree100is used to secure and validate (such as by using a validity check) a portion of a host device. Due to the progressive nature of the hash levels110,120,130, the signature of the top level hash131is altered or corrupted if data of even one of the plurality of data blocks101-104is altered or corrupted, such as altered or corrupted during a network attack. The altered or corrupted signature of the top level hash131indicates that data of one or more of the data blocks101-104has been altered or corrupted. When data is written and stored in the data blocks101-104, the Merkle tree100and the signature of the top level hash131are created. The signature of the top level hash131is stored as a stored signature.

The present disclosure contemplates thatFIG.1is exemplary and can include more data blocks than the data blocks101-104illustrated inFIG.1, more hash levels than the hash levels110,120,130illustrated inFIG.1, and more hashes than the hashes111-114,121,122,131shown inFIG.1.

FIG.2is a schematic view of a data system200, according to one implementation. The data system200includes a data storage device201. In one embodiment, which can be combined with other embodiments, the data storage device201is a solid-state drive (SSD). The present disclosure contemplates that aspects of the data storage device201can be used in other data storage devices. The data storage device201includes a controller210coupled to one or more memory devices220(one is shown). In one embodiment, which can be combined with other embodiments, the one or more memory devices220are NAND devices. The present disclosure contemplates that aspects of the data storage device201can be used for other memory devices.

The disclosure contemplates that terms such as “couples,” “coupling,” “couple,” and “coupled” may include but are not limited to operable coupling, such as wired or wireless coupling for communication purposes. The disclosure contemplates that terms such as “couples,” “coupling,” “couple,” and “coupled” may include but are not limited to direct coupling and/or indirect coupling.

The controller210is coupled to a host memory buffer (HMB)231of a host device230of the data system200. The HMB231includes the Merkle tree100shown inFIG.1stored in the HMB231of the host device230. Each node of the Merkle tree100(shown inFIG.1) is stored in the HMB231except for the top level hash131of the top hash level130. The top level hash131and the associated stored signature is instead stored in the data storage device201and is not visible to the host device230.

The host device230stores internal databases in the HMB231, such as entry data that can include logical to physical (L2P) addresses. The HMB231is a part of a host memory242that is an external memory. As the HMB231is part of external memory, the Merkle tree100is used to secure the HMB231of the host device230, such as by using a validity check to determine if the HMB231has been altered or corrupted by a network attack, such as a replay attack and/or a playback attack. When data is initially written and stored in the data blocks101-104using the host device230, the Merkle tree100and the signature of the top level hash131are created, and the signature of the top level hash131is stored within the controller210as a stored signature. The present disclosure contemplates that the aspects disclosed herein may be used in conjunction with other security operations, such as security algorithms other than the Merkle tree100.

The controller210includes a host interface module211, a control path212having one or more processors, a direct memory access (DMA)213, an error correction code (ECC)214, and a flash interface module215. The DMA213, the control path212, and the ECC214are a part of a flash translation layer (FTL) of the controller210. The control path212is configured to control the one or more memory devices220and determine if the HMB231is secure. The control path212is also configured to control other aspects of the data storage device201. The host interface module211is configured to communicate with the HMB231of the host device230and the control path212. The host interface module211is configured to manage the HMB231. The DMA213is configured to communicate with the host interface module211and the control path212. The DMA213is configured to control transferring of data from the HMB231and to the controller210, and from the controller210and to the host memory242. The ECC214is configured to communicate with the DMA213and configured to encode and decode data for error correction in relation to the DMA213. The flash interface module215is configured to communicate with the one or more memory devices220. The controller210is configured to—in response to a command from the host device230—fetch data from the one or more memory devices220, simultaneously determine if the HMB231is secure, and forward the data from the one or more memory devices220on to the HMB231if the HMB231is secure. If the HMB231is insecure (such as altered or corrected), then forwarding of the data on to the HMB231is cancelled by the controller210.

The flash interface module215is coupled to the one or more memory devices220. The control path212is coupled to the one or more memory devices220through the flash interface module215. Each of the control path212, the flash interface module215, and the ECC214is coupled to the DMA213. The DMA213is coupled to the host interface module211. The one or more memory devices220are coupled to the DMA213through the flash interface module215. The host interface module211is coupled to the HMB231of the host device230. The control path212is coupled to the host interface module211, and the control path212is coupled to the HMB231through the host interface module211.

FIG.3is a schematic view of the data system200shown inFIG.2during an operation flow using the data system200. The operation flow occurs subsequently to the storing of the stored signature of the Merkle tree100in the host interface module211. The controller210is configured to conduct the operations described herein in relation to the operation flow illustrated inFIG.3.

In the operation flow, the control path212fetches a command from the host memory242of the host device230. The command is a random read command from the host device230. In response to the command from the host device230, the controller210fetches entry data from the HMB231of the host device230. In one embodiment, which can be combined with other embodiments, the entry data includes a logical to physical (L2P) address. The fetching of the entry data includes the control path212sending301a request to host interface module211to fetch the entry data from the HMB231, and the host interface module211sending302a read request to the HMB231. In response to the read request from the host interface module211, the HMB231sends303the entry data to the control path212through the host interface module211. In response to the entry data, the control path212speculatively uses the entry data and fetches read data from the one or more memory devices220using the entry data. In one embodiment, which can be combined with other embodiments, the read data fetched from the one or more memory devices220corresponds to the entry data, such as the L2P address.

The fetching of the read data from the one or more memory devices220includes the control path212sending304a sense request to the one or more memory devices220through the flash interface module215. While the read data is being fetched from the one or more memory devices220, the host interface module211conducts a validity check of the entry data fetched from the HMB231simultaneously with the fetching of the read data from the one or more memory devices220. The entry data fetched from the HMB231includes a signature of a top level hash of a plurality of hashes of the Merkle tree100of the HMB231. The validity check includes comparing the signature of the top level hash131of the plurality of hashes to the stored signature that is stored within the host interface module211of the controller210. The validity check also includes determining if the signature is the same as or different from the stored signature. The validity check includes fetching data, such as hashes, from the HMB231and/or calculating hashes for the HMB231. The validity check is executed by the host interface module211. In one embodiment, which can be combined with other embodiments, the sense request is sent to the one or more memory devices220prior to the determining if the signature is the same as or different from the stored signature in the validity check. The host interface module211sends305results of the validity check to the control path212. The control path212sends307the results received from the host interface module211to the DMA213. The one or more memory devices220send306the read data to the DMA213through the flash interface module215.

In response to the validity check and the results received by the DMA213, the DMA213determines whether to send the read data to the host memory242. If the results indicate that the signature analyzed in the validity check is the same as the stored signature, then the DMA213sends309instructions to the host interface module211to transmit308validity result data to the host memory242of the host device230, and the validity result data transmitted to the host memory242from the host interface module211includes the read data that was fetched from the one or more memory devices220. If the results indicate that the signature analyzed in the validity check is different from the stored signature, then the DMA213cancels sending of the read data to the host memory242and the DMA213sends309instructions to the host interface module211to transmit308validity result data to the host memory242of the host device230. The validity result data transmitted to the host memory242from the host interface module211includes garbage data that is different from the read data. In one embodiment, which can be combined with other embodiments, the garbage data includes a random iteration of 0's and 1's that is different from the read data and different from the other data stored on the one or more memory devices220.

The DMA213also sends instructions to the host interface module211to post310a completion message to the host memory242of the host device230, and the host interface module211posts310the completion message to the host memory242. If the DMA213determines that the signature is the same as the stored signature then the completion message includes a valid notification. The valid notification indicates to the host memory242of the host device230that the data stored in the HMB231is valid and has not been altered or corrupted (such as by a network attack). If the DMA213determines that the signature is different from the stored signature then the completion message includes an error notification. The error notification indicates to the host memory242of the host device230that the data stored in the HMB231is invalid and has been altered or corrupted (such as by a network attack).

FIG.4is a schematic view of a method400of operating a data system, according to one implementation. The method400includes operations, aspects, features, components, and/or properties of the operation flow shown inFIG.3. The present disclosure contemplates that the operation flow includes operations, aspects, features, components, and/or properties of the method400shown inFIG.4.

Operation401of the method400includes fetching a command, such as a random read command, from a host device. Operation403includes fetching entry data from a host memory buffer (HMB) of the host device. In one embodiment, which can be combined with other embodiments, the entry data includes logical to physical (L2P) address. Operation405includes conducting a validity check on the entry data fetched from the HMB. The conducting of the validity check includes comparing a signature of a top level hash of a plurality of hashes of a Merkle tree to a stored signature that was previously stored in relation to the Merkle tree. The conducting of the validity check also includes determining if the signature is the same as or different from the stored signature.

Simultaneously with the validity check conducted at operation405, fetching read data from one or more memory devices (such as one or more NAND devices) occurs at operation407. Operation409includes determining whether the validity check is passed. The validity check is passed if the signature of the top level hash is the same as the stored signature. The validity check is failed if the signature of the top level hash is different from the stored signature. If the validity check is passed, then the HMB is secure and has not been altered or corrupted (such as by a network attack). If the validity check is failed then the HMB is insecure and has been altered or corrupted (such as by a network attack).

If the validity check is passed, then the read data that is fetched from the one or more memory devices is transferred to a host memory of the host device at operation411, and a completion message having a valid notification is posted to the host memory of the host device at operation413.

If the validity check is failed, then the transferring of the read data to the host memory of the host device is cancelled at operation415, and garbage data is transferred to the host memory of the host device at operation415. If the validity check is failed, then operation417includes posting a completion message having an error notification to the host memory of the host device.

Benefits of the present disclosure include practically and simply securing HMBs of host devices while facilitating reduced latency, heightened performance, and operational efficiency. As an example, aspects described herein facilitate practically and simply implementing Merkle tree security on the HMB231with reduced latency. Using a Merkle tree to validate security of the HMB231otherwise may take 5 μSec (microseconds) or longer. However, using aspects described herein, using the Merkle tree100to validate the security of the HMB231is conducted simultaneously with the fetching of the read data from the one or more memory devices220(which can take 50 μSec (microseconds) or longer) to reduce latency and operational delays by 4-5 μSec (microseconds) or more.

It is contemplated that one or more aspects disclosed herein may be combined. Moreover, it is contemplated that one or more aspects disclosed herein may include some or all of the aforementioned benefits. As an example, operations, aspects, components, features, and/or properties of the data system200shown inFIG.2and the operation flow shown inFIG.3may be combined with the method400shown inFIG.4.

In one embodiment, a data storage device comprises one or more memory devices, and a controller coupled to the one or more memory devices. The controller is configured to fetch a command from a host device, and the host device includes a host memory buffer (HMB). The controller is configured to fetch entry data from the HMB in response to the command from the host device. The controller is configured to fetch read data from the one or more memory devices using the entry data. The controller is configured to conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device. The HMB includes a Merkle tree having a plurality of hashes. The validity check includes comparing a signature of a top level hash of the plurality of hashes to a stored signature that is stored within the controller, and determining if the signature is the same as or different from the stored signature. The validity result data transmitted to the host device includes the read data if the signature is the same as the stored signature. The validity result data transmitted to the host device includes garbage data if the signature is different from the stored signature. The controller is further configured to post a completion message to the host device. The completion message includes a valid notification if the signature is the same as the stored signature. The completion message includes an error notification if the signature is different from the stored signature. The fetching the read data from the one or more memory devices includes sending a sense request to the one or more memory devices prior to the determining if the signature is the same as or different from the stored signature. In one example, the one or more memory devices are one or more NAND devices.

In one embodiment, a data storage device comprises one or more memory devices, and a controller coupled to the one or more memory devices. The controller is configured to fetch a command from a host device. The host device includes a host memory buffer (HMB), and the HMB includes a Merkle tree having a plurality of hashes. The controller is configured to fetch entry data from the HMB in response to the command from the host device. The controller is configured to fetch read data from the one or more memory devices using the entry data. The controller is configured to conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices. The validity check includes comparing a signature of a top level hash of the plurality of hashes to a stored signature that is stored within the controller, and determining if the signature is the same as or different from the stored signature. The controller includes a control path including one or more processors, and the control path is configured to control the one or more memory devices. The controller includes a host interface module, and the host interface module is configured to communicate with the host device and the control path. The host interface module is configured to manage the HMB. The controller includes a direct memory access (DMA), and the DMA is configured to communicate with the host interface module and the control path. The controller includes an error correction code (ECC), and the ECC is configured to communicate with the DMA and configured to encode and decode data for error correction. The controller includes a flash interface module, and the flash interface module is configured to communicate with the one or more memory devices. The fetching the read data from the one or more memory devices includes the control path sending a sense request to the one or more memory devices. The host interface module executes the validity check. The DMA is configured to send instructions to the host interface module to transmit validity result data to the host device. The DMA is further configured to send instructions to the host interface module to post a completion message to the host device.

In one embodiment, a data storage device comprises means for fetching a command from a host device, and the host device includes a host memory buffer (HMB). The data storage device includes means for fetching entry data from the HMB in response to the command from the host device. The data storage device includes means for fetching read data from one or more memory devices using the entry data. The data storage device includes means for conducting a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and means for transmitting validity result data to the host device. The means for conducting the validity check of the entry data includes means for comparing a signature of a top level hash of a plurality of hashes stored in a Merkle tree of the HMB to a stored signature that is stored within the means for conducting the validity check of the entry data, and means for determining if the signature is the same as or different from the stored signature. The means for fetching the read data from the one or more memory devices is coupled to the one or more memory devices. The means for fetching the read data from the one or more memory devices is further coupled to the means for conducting the validity check of the entry data. The means for fetching the read data from the one or more memory devices is further coupled to a direct memory access (DMA).