METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device according to an embodiment includes forming a first mask material having a first opening on a surface of a silicon carbide layer, performing first ion implantation of forming a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask, forming, on the surface of the silicon carbide layer, a second mask material in which both end portions in a first direction parallel to the surface have second openings disposed inside both end portions in the first direction of the first carbon region, performing second ion implantation of forming a first impurity region by implanting a first impurity into the silicon carbide layer using the second mask material as a mask, and performing heat treatment at 1600° C. or higher.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-045395, filed on Mar. 22, 2022, and Japanese Patent Application No. 2022-107884, filed on Jul. 4, 2022, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

BACKGROUND

Silicon carbide (SiC) is expected as a material for next-generation semiconductor devices. As compared with silicon (Si), silicon carbide has excellent physical properties such as a band gap of about 3 times, a breakdown field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing this characteristic, a semiconductor device capable of operating at a low loss and a high temperature can be realized.

From the viewpoint of realizing scaling-down of a semiconductor device using silicon carbide, it is desirable to suppress diffusion of impurities ion-implanted into silicon carbide due to heat treatment. The heat treatment is, for example, high-temperature ion implantation of impurities or activation annealing of impurities.

DETAILED DESCRIPTION

A method for manufacturing a semiconductor device according to an embodiment includes forming a first mask material having a first opening on a surface of a silicon carbide layer; performing first ion implantation of forming a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; forming a second mask material having a second opening on the surface of the silicon carbide layer, both end portions of the second opening disposed inside of both end portions of the first carbon region in a first direction parallel to the surface; performing second ion implantation of forming a first impurity region by implanting a first impurity into the silicon carbide layer using the second mask material as a mask; and performing heat treatment at 1600° C. or higher.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, the same or similar members and the like are denoted by the same reference numerals, and the description of the members and the like once described is appropriately omitted.

In the following description, when there are notations of n+, n, and n−, and p+, p, and p−, a relative level of an impurity concentration in each conductivity type is represented. That is, n+indicates that the n-type impurity concentration is relatively higher than n, and n−indicates that the n-type impurity concentration is relatively lower than n. In addition, p+indicates that the p-type impurity concentration is relatively higher than p, and p−indicates that the p-type impurity concentration is relatively lower than p. In addition, an n+type and an n−type may be simply referred to as an n type, and a p+type and a p−type may be simply referred to as a p type. Unless otherwise specified, the impurity concentration of each region is represented by, for example, a value of an impurity concentration in a central portion of each region.

The impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). A relative level of the impurity concentration can also be determined from a level of a carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). The distance such as the width and depth of the impurity region can be obtained by, for example, SIMS. Moreover, the distance such as the width and depth of the impurity region can be obtained from, for example, the SCM image.

First Embodiment

A method for manufacturing a semiconductor device according to a first embodiment includes forming a first mask material having a first opening on a surface of a silicon carbide layer; performing first ion implantation of forming a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; forming a second mask material having a second opening on the surface of the silicon carbide layer, both end portions of the second opening disposed inside of both end portions of the first carbon region in a first direction parallel to the surface; performing second ion implantation of forming a first impurity region by implanting a first impurity into the silicon carbide layer using the second mask material as a mask; and performing heat treatment at 1600° C. or higher.

FIG.1is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment. The semiconductor device of the first embodiment is a merged PiN Schottky diode (MPS diode)100. The MPS diode100has a structure in which an SBD is sandwiched between PN diodes.

The MPS diode100includes a silicon carbide layer10, an anode electrode12, and a cathode electrode14.

The silicon carbide layer10includes an n+-type cathode region16, an n−-type drift region18, a p+-type anode region20, and an n-type carrier diffusion region22.

The n+-type cathode region16is provided on a back surface side of the silicon carbide layer10. The cathode region16contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the cathode region16is, for example, 1×1018cm−3or more and 1×1020cm−3or less.

The n−-type drift region18is provided on the cathode region16. The drift region18functions as a path of an on-current of the MPS diode100.

The drift region18contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region18is, for example, 1×1015cm−3or more and 1×1016cm−3or less.

The p+-type anode region20is provided on the drift region18. The anode region20is provided on the surface of the silicon carbide layer10. A plurality of anode regions20are provided spaced from one another in a first direction.

When the MPS diode100is in the OFF state, the space between the adjacent anode regions20is depleted. Therefore, a breakdown voltage of the MPS diode100is improved. By providing the anode region20, a high surge current can flow in the forward direction. Therefore, a surge current tolerance of the MPS diode100is improved.

The anode region20contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the anode region20is, for example, 1×1017cm−3or more and 1×1022cm−3or less.

The n-type carrier diffusion region22is provided between the drift region18and the anode region20. The carrier diffusion region22is provided at the bottom of the anode region20. By providing the carrier diffusion region22at the bottom of the anode region20, carriers are laterally diffused at the bottom of the anode region20. Therefore, the on-resistance of the MPS diode100is reduced.

The carrier diffusion region22contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the carrier diffusion region22is, for example, 5×1016cm−3or more and 1×1018cm−3or less.

The anode electrode12is provided on the front surface side of the silicon carbide layer10. The anode electrode12is electrically connected to the drift region18and the anode region20. The anode electrode12is in contact with the drift region18and the anode region20.

The junction between the anode electrode12and the drift region18is a Schottky junction. The junction between the anode electrode12and the anode region20is an ohmic junction.

The anode electrode12is, for example, a metal or a metal compound.

The cathode electrode14is provided on the back surface side of the silicon carbide layer10. The cathode electrode14is electrically connected to the cathode region16. The cathode electrode14is in contact with the cathode region16. The junction between the cathode electrode14and the cathode region16is an ohmic junction.

Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described.

FIGS.2,3,4,5,6,7,8, and9are explanatory diagrams of the method for manufacturing a semiconductor device according to the first embodiment.FIGS.2to7and9are cross-sectional views in the middle of manufacturing.FIG.8is a diagram illustrating a distribution of ion-implanted elements immediately after ion implantation.

First, a silicon carbide layer10is prepared (FIG.2). The silicon carbide layer10includes an n+-type cathode region16and an n−-type drift region18. The drift region18is formed on the cathode region16by, for example, an epitaxial growth method.

Next, a first mask material31having a first opening31ais formed on the surface of the silicon carbide layer10(FIG.3). The first mask material31is, for example, an insulator. The first mask material31is, for example, silicon oxide.

The first mask material31is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

Next, first ion implantation for implanting carbon (C) into the silicon carbide layer10is performed using the first mask material31as an ion implantation mask (FIG.4). A carbon region19is formed by the first ion implantation. The carbon region19is an example of the first carbon region.

The first ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The first ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or more and 1300° C. or less.

Next, the first mask material31is removed. The first mask material31is removed by, for example, wet etching.

Next, a second mask material32having a second opening32ais formed on the surface of the silicon carbide layer10(FIG.5). The second mask material32is, for example, an insulator. The second mask material32is, for example, silicon oxide.

Both end portions (E1inFIG.5) of the second opening32ain the first direction are disposed inside both end portions (E2inFIG.5) of the carbon region19in the first direction. A width of the second opening32ain the first direction is smaller than a width of the carbon region19in the first direction. The first direction is a direction parallel to the surface of the silicon carbide layer10.

Both end portions (E2inFIG.5) in the first direction of the carbon region19coincide with positions of both end portions in the first direction of the first opening31a.

The second mask material32is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

Next, second ion implantation of implanting aluminum (Al) into the silicon carbide layer10is performed using the second mask material32as an ion implantation mask (FIG.6). The anode region20is formed by the second ion implantation. Aluminum (Al) implanted by the second ion implantation is an example of the first impurity. The anode region20is an example of a first impurity region.

The second ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The second ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

Next, third ion implantation for implanting nitrogen (N) into the silicon carbide layer10is performed using the second mask material32as an ion implantation mask (FIG.7). The carrier diffusion region22is formed by the third ion implantation. Nitrogen (N) is an example of impurities. The carrier diffusion region22is an example of an impurity region.

The third ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The third ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

Next, the second mask material32is removed. The second mask material32is removed by, for example, wet etching.

FIG.8is a diagram illustrating element distribution immediately after the ion implantation.FIG.8illustrates a distribution of elements in the silicon carbide layer10in the depth direction.

FIG.8illustrates the distribution of carbon (C) implanted by the first ion implantation.FIG.8illustrates a carbon profile of the carbon region19formed by the first ion implantation. The distribution of carbon (C) implanted by the first ion implantation is determined by an ion implantation condition of the first ion implantation.

FIG.8illustrates the distribution of aluminum (Al) implanted by the second ion implantation.FIG.8illustrates an aluminum profile of the anode region20formed by the second ion implantation. The distribution of aluminum (Al) implanted by the second ion implantation is determined by an ion implantation condition of the second ion implantation.

FIG.8illustrates the distribution of nitrogen (N) implanted by the third ion implantation.FIG.8illustrates a nitrogen profile of the carrier diffusion region22formed by the third ion implantation. The distribution of nitrogen (N) implanted by the third ion implantation is determined by an ion implantation condition of the third ion implantation.

As illustrated inFIG.8, the depth of the carbon region19is deeper than the depth of the anode region20. The depth of the carbon region19is deeper than the depth of the carrier diffusion region22.

The depth of the carbon region19is determined by the ion implantation condition of the first ion implantation for ion-implanting carbon. Further, the depth of the anode region20is determined by the ion implantation condition of the second ion implantation for ion-implanting aluminum. In addition, the depth of the carrier diffusion region22is determined by the ion implantation condition of the third ion implantation for ion-implanting nitrogen.

As illustrated inFIG.8, a maximum concentration of carbon (C) in the carbon region19is higher than a maximum concentration of aluminum (Al) in the anode region20. The maximum concentration of carbon (C) in the carbon region19is higher than the maximum concentration of nitrogen (N) in the carrier diffusion region22.

The maximum concentration of carbon (C) in the carbon region19is determined by the ion implantation conditions of the first ion implantation for ion-implanting carbon. In addition, the maximum concentration of aluminum (Al) in the anode region20is determined by the ion implantation condition of the second ion implantation for ion-implanting aluminum. The maximum concentration of nitrogen (N) in the carrier diffusion region22is determined by the ion implantation condition of the third ion implantation for ion-implanting nitrogen.

A dose amount of carbon in the first ion implantation is, for example, 10 times or more a dose amount of aluminum (Al) in the second ion implantation. The dose amount of carbon in the first ion implantation is, for example, 10 times or more a dose amount of nitrogen (N) in the third ion implantation.

As illustrated inFIG.8, the concentration of carbon implanted by the first ion implantation on the surface of the silicon carbide layer10in the carbon region19is 1×1015cm−3or more and 1×1018cm−3or less. The concentration of carbon implanted by the first ion implantation on the surface of the silicon carbide layer10in the carbon region19is determined by the ion implantation condition of the first ion implantation for ion-implanting carbon.

Next, a carbon film30is formed on the surface of the silicon carbide layer10(FIG.9).

Next, heat treatment is performed. The heat treatment is performed, for example, at 1600° C. or more and 2000° C. or less. The heat treatment is performed in a non-oxidizing atmosphere. The heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

The heat treatment activates aluminum and nitrogen ion-implanted into the silicon carbide layer10. The heat treatment is activation annealing of aluminum and nitrogen. Further, interstitial carbon formed by carbon ion implantation into the silicon carbide layer10by heat treatment fills carbon vacancy in the silicon carbide layer10.

The widths of the anode region20and the carrier diffusion region22in the first direction after the heat treatment are first widths (w1inFIG.9). The depth of the carrier diffusion region22after the heat treatment is a first depth (d1inFIG.9).

The carbon film30suppresses desorption of silicon and carbon from the silicon carbide layer10into the atmosphere during the heat treatment. Further, the carbon film30absorbs excessive interstitial carbon in the silicon carbide layer10during the heat treatment.

Next, the carbon film30is removed. After that, the anode electrode12is formed on the surface of the silicon carbide layer10using a known process technique. In addition, the cathode electrode14is formed on the back surface of the silicon carbide layer10.

The MPS diode100illustrated inFIG.1is manufactured by the above manufacturing method.

Next, functions and effects of the method for manufacturing a semiconductor device according to the first embodiment will be described.

From the viewpoint of realizing scaling-down of a semiconductor device using silicon carbide, it is desirable to suppress diffusion of impurities ion-implanted into silicon carbide due to heat treatment. The heat treatment is, for example, high-temperature ion implantation of impurities or activation annealing of impurities.

In the method for manufacturing a semiconductor device according to the first embodiment, carbon (C) is introduced into a range wider than a range in which impurities are ion-implanted by ion implantation. By the above method, the density of carbon vacancies in the silicon carbide layer is reduced, and diffusion of impurities ion-implanted into silicon carbide due to heat treatment can be suppressed. Details will be described below.

FIG.10is an explanatory view of a method for manufacturing a semiconductor device of a comparative example. The method for manufacturing a semiconductor device of the comparative example is different from the method for manufacturing a semiconductor device of the first embodiment in that the first ion implantation for implanting carbon (C) into the silicon carbide layer10is not performed.

FIG.10is a cross-sectional view immediately after activation annealing.FIG.10is a diagram corresponding toFIG.9of the first embodiment.

As illustrated inFIG.10, the widths of the anode region20and the carrier diffusion region22in the first direction after the heat treatment are second widths (w2inFIG.10). The depth of the carrier diffusion region22after the heat treatment is a second depth (d2inFIG.10).

The second width w2increases as the diffusion of the impurities in the lateral direction (first direction) by the heat treatment increases. The second depth d2increases as the diffusion of the impurities in the depth direction by the heat treatment increases.

For example, as the second width w2increases, the distance between two adjacent anode regions20decreases. Therefore, the on-resistance of the MPS diode increases. Therefore, it is difficult to realize scaling-down of the MPS diode.

Furthermore, for example, when the second depth d2becomes deeper, the concentration of the carrier diffusion region22decreases, and the electrical resistance of the carrier diffusion region22increases. Therefore, diffusion of carriers in the lateral direction is suppressed at the bottom of the anode region20. Therefore, the on-resistance of the MPS diode increases.

According to the method for manufacturing a semiconductor device of the first embodiment, the first width w1of the anode region20and the carrier diffusion region22in the first direction after the heat treatment is smaller than the second width w2of the comparative example. Therefore, the on-resistance of the MPS diode100is reduced.

Diffusion of impurities in the silicon carbide layer10is promoted by carbon vacancies in the silicon carbide layer10. By forming the carbon region19by ion implantation of carbon, the density of carbon vacancies in the silicon carbide layer10is reduced. Therefore, diffusion of impurities is suppressed, and the first width w1decreases.

In particular, in the method for manufacturing a semiconductor device according to the first embodiment, when the second mask material32is formed, both end portions (E1inFIG.5) of the second opening32ain the first direction are formed so as to be disposed inside both end portions (E2inFIG.5) of the carbon region19in the first direction. Therefore, the anode region20and the carrier diffusion region22after the ion implantation are covered with the carbon region19in the lateral direction.

In the method for manufacturing a semiconductor device according to the first embodiment, the carbon region19is formed in a region where diffusion of impurities in the lateral direction is scheduled before the heat treatment for diffusing the impurities. Therefore, lateral diffusion of impurities is effectively suppressed.

In addition, according to the method for manufacturing a semiconductor device of the first embodiment, the first depth d1of the carrier diffusion region22after the heat treatment is smaller than the second depth d2of the comparative example. Therefore, the on-resistance of the MPS diode100is reduced.

Diffusion of impurities in the silicon carbide layer10is promoted by carbon vacancies in the silicon carbide layer10. By forming the carbon region19by ion implantation of carbon, the density of carbon vacancies in the silicon carbide layer10is reduced. Therefore, diffusion of impurities is suppressed, and the first depth d1decreases.

In particular, in the method for manufacturing a semiconductor device according to the first embodiment, the carbon region19is formed to be deeper than the carrier diffusion region22. Therefore, after the ion implantation, the carrier diffusion region22is covered with the carbon region19in the depth direction.

In the method for manufacturing a semiconductor device according to the first embodiment, the carbon region19is formed in a region where diffusion of the impurity in the depth direction is scheduled before the heat treatment for diffusing the impurity. Therefore, diffusion of impurities in the depth direction is effectively suppressed.

In the method for manufacturing a semiconductor device according to the first embodiment, carbon (C) is introduced into a range wider than a range in which impurities are ion-implanted by ion implantation. Therefore, diffusion of impurities ion-implanted into silicon carbide due to heat treatment can be effectively suppressed. Therefore, the scaling-down of the MPS diode100can be realized.

In addition, in the method for manufacturing a semiconductor device according to the first embodiment, when carbon is ion-implanted, a region where a Schottky junction is to be formed later is covered with the first mask material31. Therefore, ion implantation of carbon is not performed in a region where a Schottky junction is formed later. Therefore, for example, it is possible to suppress degradation of characteristics of the Schottky junction due to damage by ion implantation of carbon.

The depth of the carbon region19is preferably deeper than the depth of the anode region20from the viewpoint of suppressing diffusion of impurities in the depth direction, and the depth of the carbon region19is preferably deeper than the depth of the carrier diffusion region22from the viewpoint of suppressing diffusion of impurities in the depth direction.

The first ion implantation for implanting carbon is preferably performed at a temperature of 1000° C. or higher. By introducing carbon into the silicon carbide layer10at a temperature of 1000° C. or higher, interstitial carbon enters carbon vacancies during ion implantation, and the density of carbon vacancies can be reduced. Therefore, for example, diffusion of impurities when the subsequent ion implantation of impurities is performed at a high temperature can be suppressed.

In addition, ion implantation of carbon at a temperature of 1000° C. or higher can reduce damage due to ion implantation of carbon. Therefore, the characteristics of the MPS diode100are improved.

The second ion implantation for implanting aluminum (Al) and the third ion implantation for implanting nitrogen (N) are preferably performed at a temperature of 1000° C. or higher. Impurity ion implantation at a temperature of 1000° C. or higher can reduce damage due to impurity ion implantation. Since amorphization of the silicon carbide layer10due to damage can be suppressed and the crystallinity can be kept high, the activation efficiency after the activation annealing can be increased.

Since the crystallinity of the silicon carbide layer10can be maintained higher as the temperature of ion implantation is higher, the temperature of ion implantation is more preferably 1100° C. or higher. Meanwhile, a resist used as a mask for ion implantation has low heat resistance. The heat resistance of the resist is, for example, 500° C. or less. Therefore, when ion implantation is performed at a temperature of 1000° C. or higher, it is desirable to form a mask with a material having high heat resistance such as silicon oxide, silicon nitride, or aluminum nitride. From the viewpoint of heat resistance, for example, the temperature of ion implantation is preferably 1300° C. or lower when silicon oxide is used as the material of the mask, and is preferably 1400° C. or lower when silicon nitride or aluminum nitride is used. Considering an etching selectivity to the silicon carbide layer10and the like, it is preferable to use silicon oxide as a material of the mask. For ion implantation of impurities, silicon oxide is used as a material of a mask, and the temperature is preferably 1000° C. or more and 1300° C. or less, and more preferably 1100° C. or more and 1200 or less.

Since the carbon region19is formed by ion implantation of carbon prior to ion implantation of impurities, diffusion of impurities due to ion implantation at a high temperature can be suppressed.

From the viewpoint of suppressing diffusion of aluminum, the maximum concentration of carbon in the silicon carbide layer10implanted by the first ion implantation is preferably higher than the maximum concentration of aluminum in the silicon carbide layer10implanted by the second ion implantation. From the viewpoint of suppressing diffusion of nitrogen, the maximum concentration of carbon in the silicon carbide layer10implanted by the first ion implantation is preferably higher than the maximum concentration of nitrogen in the silicon carbide layer10implanted by the third ion implantation.

From the viewpoint of suppressing diffusion of aluminum, the dose amount of carbon in the first ion implantation is preferably 10 times or more, and more preferably 100 times or more the dose amount of aluminum in the second ion implantation. In addition, from the viewpoint of suppressing diffusion of nitrogen, the dose amount of carbon in the first ion implantation is preferably 10 times or more, and more preferably 100 times or more the dose amount of nitrogen in the third ion implantation.

From the viewpoint of suppressing diffusion of aluminum in the lateral direction, the concentration of the surface of the silicon carbide layer10of carbon implanted by the first ion implantation is preferably 1×1016cm−3or more, more preferably 1×1016cm−3or more, and still more preferably 1×1017cm−3or more.

The temperature of the heat treatment is preferably 1850° C. or higher. When the heat treatment is performed at 1850° C. or higher, the activation rate of impurities is improved. Since the carbon region19is formed by the ion implantation of carbon prior to ion implantation of impurities, diffusion of impurities can be suppressed even when the heat treatment is 1850° C. or higher.

A method for manufacturing a semiconductor device according to a first modification of the first embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in that the second mask material is formed by forming a sidewall material on a sidewall of the first opening.

FIGS.11and12are explanatory diagrams of the method for manufacturing a semiconductor device according to the first modification of the first embodiment.FIG.11is a cross-sectional view immediately after the second mask material32is formed.FIG.11is a diagram corresponding toFIG.5of the first embodiment.FIG.12is a diagram corresponding toFIG.6of the first embodiment.

As illustrated inFIG.11, the second mask material32is formed by forming a sidewall material on the sidewall of the first opening31aof the first mask material31. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching.

The sidewall material becomes the second mask material32. The opening formed by the sidewall material is the second opening32a. Both end portions (E1inFIG.11) of the second opening32ain the first direction are disposed inside both end portions (E2inFIG.11) of the carbon region19in the first direction. The sidewall material formed on the sidewall of first opening31ais an example of the first sidewall material.

Next, second ion implantation for implanting aluminum into the silicon carbide layer10is performed using the first mask material31and the second mask material32as ion implantation masks (FIG.12). The anode region20is formed by the second ion implantation. Aluminum implanted by the second ion implantation is an example of the first impurity.

After the anode region20is formed, the manufacturing method is the same as that of the first embodiment.

According to the method for manufacturing a semiconductor device of the first modification of the first embodiment, the second opening32acan be formed in a self-alignment manner with respect to the first opening31a.

Therefore, when second opening32ais formed, it is not necessary to consider a margin for alignment with carbon region19. Therefore, the scaling-down of the MPS diode can be further realized.

A method for manufacturing a semiconductor device according to a second modification of the first embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in that the third ion implantation of ion-implanting carbon using the second mask material as a mask is performed before the second ion implantation.

FIG.13is an explanatory diagram of the method for manufacturing a semiconductor device according to the second modification of the first embodiment.FIG.13is a cross-sectional view when carbon ion implantation is performed after the second mask material32is formed.

After the formation of the second mask material32, the third ion implantation for implanting carbon into the silicon carbide layer10is performed before second ion implantation for implanting aluminum. The carbon region21is formed by the third ion implantation for implanting carbon into the silicon carbide layer10.

Next, the second ion implantation for implanting aluminum into the silicon carbide layer10is performed. After the second ion implantation for implanting aluminum into the silicon carbide layer10, a manufacturing method similar to that of the first embodiment is employed.

After the formation of the second mask material32, the manufacturing method is similar to that of the first embodiment.

According to the method for manufacturing a semiconductor device according to the second modification of the first embodiment, diffusion of impurities can be further suppressed by ion implantation for adding carbon. Therefore, the scaling-down of the MPS diode can be further realized.

(Third Modification) A method for manufacturing a semiconductor device according to a third modification of the first embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in that the depth of the carbon region19is shallower than the depth of the anode region20and the depth of the carbon region19is shallower than the depth of the carrier diffusion region22.

FIGS.14,15, and16are explanatory diagrams of the method for manufacturing a semiconductor device according to the third modification of the first embodiment.FIG.14is a diagram corresponding toFIG.4of the first embodiment.FIG.15is a diagram corresponding toFIG.7of the first embodiment.FIG.16is a diagram corresponding toFIG.9of the first embodiment.

The first ion implantation for implanting carbon (C) into the silicon carbide layer10is performed using the first mask material31as an ion implantation mask (FIG.14). A carbon region19is formed by the first ion implantation. The depth of the carbon region19to be formed is shallower than that in the case of the first embodiment.

Since the depth of the carbon region19to be formed is shallow, the depth of the carbon region19is shallower than the depth of the anode region20, and the depth of the carbon region19is shallower than the depth of the carrier diffusion region22(FIG.15).

After the heat treatment, diffusion of the anode region20in the lateral direction on the surface of the silicon carbide layer10is suppressed (FIG.16). Only lateral diffusion of the anode region20on the surface of the silicon carbide layer10overlapping the carbon region19is suppressed.

As described above, according to the methods for manufacturing a semiconductor device of the first embodiment and the modifications, diffusion of impurities due to heat treatment can be suppressed by the ion implantation of carbon.

Second Embodiment

A method for manufacturing a semiconductor device of a second embodiment is different from the method for manufacturing a semiconductor device of the first embodiment in that a metal oxide semiconductor field effect transistor (MOSFET) is manufactured. Hereinafter, description of contents overlapping with the first embodiment may be partially omitted.

FIG.17is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device of the second embodiment is a MOSFET200.

The MOSFET200includes a silicon carbide layer10, a gate insulating layer40, a gate electrode42, an interlayer insulating film44, a source electrode46, and a drain electrode48.

The silicon carbide layer10includes an n+-type drain region50, an n−-type drift region52, a p-type well region54, an n+-type source region56, and a p+-type well contact region58.

The silicon carbide layer10is, for example, a single crystal of 4H-SiC. The silicon carbide layer10is disposed between the source electrode46and the drain electrode48.

The n+-type drain region50is provided on the back surface side of the silicon carbide layer10. The drain region50contains, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drain region50is, for example, 1×1018cm−3or more and 1×1020cm−3or less.

The n−-type drift region52is provided on the drain region50. The drift region52functions as a path of an on-current of the MOSFET200.

The drift region52contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region52is, for example, 1×1015cm−3or more and 1×1016cm−3or less.

The thickness of the drift region52is, for example, 5 μm or more and 100 μm or less.

The p-type well region54is provided on the drift region52. The well region54is disposed between the drift region52and the gate insulating layer40. The well region54functions as a channel region of the MOSFET200.

The well region54contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the well region54is, for example, 1×1016cm−3or more and 1×1020cm−3or less.

The n+-type source region56is provided on the well region54. The source region56contains, for example, phosphorus (P) as n-type impurities. The n-type impurity concentration of the source region56is, for example, 1×1018cm−3or more and 1×1022cm−3or less.

The p+-type well contact region58is provided on the well region54. The well contact region58is provided on the side of the source region56.

The well contact region58contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the well contact region58is, for example, 1×1018cm−3or more and 1×1022cm−3or less.

The gate insulating layer40is provided between the silicon carbide layer10and the gate electrode42. The gate insulating layer40contains, for example, silicon oxide.

The gate electrode42is provided on the gate insulating layer40. The gate electrode42is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

The interlayer insulating film44is formed on the gate electrode42. The interlayer insulating film44is disposed between the gate electrode42and the source electrode46. The interlayer insulating film44is, for example, a silicon oxide film.

The source electrode46is provided on the front surface side of the silicon carbide layer10. The source electrode46is electrically connected to the source region56and the well contact region58. The source electrode46is in contact with, for example, the source region56and the well contact region58.

The drain electrode48is provided on the side of the silicon carbide layer10opposite to the source electrode46, that is, on the back surface side. The drain electrode48is electrically connected to the drain region50. The drain electrode48is in contact with, for example, the drain region50.

Next, an example of a method for manufacturing a semiconductor device according to the second embodiment will be described.

FIGS.18,19,20,21,22,23,24,25,26, and27are explanatory diagrams of the method for manufacturing a semiconductor device according to the second embodiment.

FIGS.18to27are cross-sectional views in the middle of manufacturing.

First, the silicon carbide layer10is prepared (FIG.18). The silicon carbide layer10includes an n+-type drain region50and an n−-type drift region52. The drift region52is formed on the drain region50by, for example, an epitaxial growth method.

Next, the first mask material31having the first opening31ais formed on the surface of the silicon carbide layer10(FIG.19). The first mask material31is, for example, an insulator. The first mask material31is, for example, silicon oxide.

The first mask material31is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

Next, the first ion implantation for implanting carbon (C) into the silicon carbide layer10is performed using the first mask material31as an ion implantation mask (FIG.20). A carbon region19is formed by the first ion implantation.

The first ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The first ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or more and 1300° C. or less.

Next, the second mask material32having the second opening32ais formed on the surface of the silicon carbide layer10(FIG.21). The second mask material32is, for example, an insulator. The second mask material32is, for example, silicon oxide.

Both end portions (E1inFIG.21) of the second opening32ain the first direction are disposed inside both end portions (E2inFIG.21) of the carbon region19in the first direction. A width of the second opening32ain the first direction is smaller than a width of the carbon region19in the first direction. The first direction is a direction parallel to the surface of the silicon carbide layer10.

As illustrated inFIG.21, the second mask material32is formed by forming a sidewall material on the sidewall of the first opening31aof the first mask material31. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching.

Next, the second ion implantation of implanting aluminum (Al) into the silicon carbide layer10is performed using the first mask material31and the second mask material32as ion implantation masks (FIG.22). The well region54is formed by the second ion implantation. Aluminum (Al) implanted by the second ion implantation is an example of the first impurity. The well region54is an example of the first impurity region.

The second ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The second ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

Next, a third mask material33having a third opening33ais formed on the surface of the silicon carbide layer10(FIG.23). The third mask material33is, for example, an insulator. The third mask material33is, for example, silicon oxide.

As illustrated inFIG.23, the third mask material33is formed by forming a sidewall material on the sidewall of the second opening32aof the second mask material32. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching.

Next, the third ion implantation for implanting phosphorus (P) into the silicon carbide layer10is performed using the first mask material31, the second mask material32, and the third mask material33as ion implantation masks (FIG.24). The source region56is formed by the third ion implantation. Phosphorus (P) implanted by the third ion implantation is an example of the first impurity. The source region56is an example of the first impurity region.

The third ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The third ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

Next, a fourth mask material34having a fourth opening34ais formed on the surface of the silicon carbide layer10(FIG.25). The fourth mask material34is, for example, an insulator. The fourth mask material34is, for example, silicon oxide.

As illustrated inFIG.25, the fourth mask material34is formed by forming a sidewall material on the sidewall of the third opening33aof the third mask material33. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching.

Next, the fourth ion implantation of implanting aluminum into the silicon carbide layer10is performed using the first mask material31, the second mask material32, the third mask material33, and the fourth mask material34as ion implantation masks (FIG.26). The well contact region58is formed by the fourth ion implantation. Aluminum implanted in the fourth ion implantation is an example of the first impurity. The well contact region58is an example of a first impurity region.

The fourth ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The fourth ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

Next, the first mask material31, the second mask material32, the third mask material33, and the fourth mask material34are removed.

Next, the carbon film30is formed on the surface of the silicon carbide layer10(FIG.27).

Next, heat treatment is performed. The heat treatment is performed, for example, at 1600° C. or more and 2000° C. or less. The heat treatment is performed in a non-oxidizing atmosphere. The heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

The heat treatment activates aluminum and phosphorus ion-implanted into the silicon carbide layer10. The heat treatment is activation annealing of aluminum and phosphorus. Further, interstitial carbon formed by carbon ion implantation into the silicon carbide layer10by heat treatment fills carbon vacancy in the silicon carbide layer10.

Next, the carbon film30is removed. After that, the gate insulating layer40, the gate electrode42, the interlayer insulating film44, and the source electrode46are formed on the surface of the silicon carbide layer10using a known process technique. In addition, the drain electrode48is formed on the back surface of the silicon carbide layer10.

The MOSFET200illustrated inFIG.17is manufactured by the above manufacturing method.

In the method for manufacturing a semiconductor device according to the second embodiment, carbon (C) is introduced into a range wider than a range in which impurities are ion-implanted by ion implantation, similarly to the method for manufacturing a semiconductor device according to the first embodiment. By the above method, the density of carbon vacancies in the silicon carbide layer is reduced, and diffusion of impurities ion-implanted into silicon carbide due to heat treatment can be suppressed.

For example, in the MOSFET200, when the diffusion of the n-type impurity in the source region56in the lateral direction (first direction) increases, the channel length (L inFIG.17) of the MOSFET200decreases, and the threshold voltage of the MOSFET200decreases. Therefore, it is difficult to realize scaling-down of the MOSFET200.

According to the method for manufacturing a semiconductor device of the second embodiment, diffusion of n-type impurities in the source region56in the lateral direction (first direction) is suppressed. Therefore, it is possible to prevent the channel length L of the MOSFET200from being shortened. Therefore, the scaling-down of the MOSFET200can be realized.

In addition, in the MOSFET200, as the diffusion of the p-type impurity in the well region54in the lateral direction (first direction) increases, the variation in the channel length L of the MOSFET200increases. When the variation in the channel length L increases, a variation in the threshold voltage of the MOSFET200increases.

According to the method for manufacturing a semiconductor device of the second embodiment, diffusion of p-type impurities in the well region54in the lateral direction (first direction) is suppressed. Therefore, variations in the channel length L of the MOSFET200can be suppressed. Therefore, the variation in the threshold voltage of the MOSFET200is suppressed.

FIG.28is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a modification of the second embodiment.

A semiconductor device according to the modification of the second embodiment is a MOSFET201. The MOSFET201is different from the MOSFET200of the second embodiment in that a Schottky barrier diode (SBD) is incorporated. The MOSFET201is different from the MOSFET200of the second embodiment in that the silicon carbide layer10includes an n-type carrier diffusion region60.

The source electrode46of the MOSFET201includes a first portion46a. The first portion46ais in contact with the drift region52. A Schottky contact is formed between the first portion46aand the drift region52.

The first portion46aof the source electrode46, the drift region52, the drain region50, and the drain electrode48constitute an SBD incorporated in the MOSFET201. In addition, the source electrode46, the well contact region58, the well region54, the drift region52, the drain region50, and the drain electrode48constitute a pn junction diode incorporated in the MOSFET201.

For example, a case where the MOSFET201is used as a switching element connected to an inductive load will be considered. When the MOSFET201is turned off, a voltage that is positive with respect to the drain electrode48may be applied to the source electrode46due to an induced current caused by an inductive load. In this case, a forward current flows through the built-in diode. This state is also referred to as a reverse conduction state.

When the MOSFET201does not include the SBD, a forward current flows through the pn junction diode. The pn junction diode performs a bipolar operation. When a reflux current is caused to flow using a pn junction diode that performs a bipolar operation, a stacking fault grows in the silicon carbide layer due to recombination energy of carriers. When the stacking fault grows in the silicon carbide layer, there arises a problem that the on-resistance of the MOSFET201increases. An increase in the on-resistance of the MOSFET201leads to a decrease in the reliability of the MOSFET201.

The MOSFET201includes an SBD. A forward voltage (Vf) at which the forward current starts flowing through the SBD is lower than a forward voltage (Vf) of the pn junction diode. Therefore, a forward current flows through the SBD prior to the pn junction diode.

The SBD performs unipolar operation. Therefore, even when a forward current flows, the stacking fault does not grow in the silicon carbide layer10due to the recombination energy of the carrier. Therefore, an increase in the on-resistance of the MOSFET201is suppressed. Therefore, the reliability of the MOSFET201is improved.

The silicon carbide layer10of the MOSFET201includes an n-type carrier diffusion region60. The carrier diffusion region60is provided between the drift region52and the well region54. The carrier diffusion region60is provided at the bottom of the well region54.

The carrier diffusion region60contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the carrier diffusion region60is, for example, 5×1016cm−3or more and 1×1018cm−3or less.

By providing the carrier diffusion region60at the bottom of the well region54, carriers are laterally diffused at the bottom of the well region54. Since the carriers are diffused in the lateral direction at the bottom of the well region54, when the MOSFET201is in the reverse conduction state, it is difficult for the built-in pn junction diode to perform the on-operation. This is because the carriers are laterally diffused at the bottom of the well region54, so that the voltage applied between the built-in pn junction diodes is reduced, and the forward voltage (Vf) of the pn junction diodes is hardly exceeded. Since the on-operation of the pn junction diode built in the MOSFET201is suppressed, an increase in the on-resistance of the MOSFET is suppressed.

The method for manufacturing a semiconductor device according to a modification of the second embodiment is different from the method for manufacturing a semiconductor device according to the second embodiment in that after the second ion implantation of implanting aluminum (Al) into the silicon carbide layer10is performed using the first mask material31and the second mask material32as ion implantation masks, nitrogen (N) is implanted into the silicon carbide layer10using the first mask material31and the second mask material32as ion implantation masks.

FIG.29is an explanatory diagram of a method for manufacturing a semiconductor device according to a modification of the second embodiment.FIG.29is a cross-sectional view in the middle of manufacturing. After the second ion implantation of implanting aluminum (Al) into the silicon carbide layer10is performed using the first mask material31and the second mask material32as ion implantation masks (afterFIG.22of the second embodiment), nitrogen (N) is implanted into the silicon carbide layer10using the first mask material31and the second mask material32as ion implantation masks (FIG.29). The carrier diffusion region60is formed by ion implantation of nitrogen (N).

The ion implantation of nitrogen is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The ion implantation of nitrogen is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

After that, similarly to the second embodiment, a third mask material33having a third opening33ais formed on the surface of the silicon carbide layer10(FIG.23of the second embodiment). The subsequent steps are similar to those of the second embodiment except that, for example, the pattern of the gate electrode42is changed.

In the method for manufacturing a semiconductor device according to the modification of the second embodiment, the carbon region19is formed in a region where diffusion of impurities in the vertical direction is scheduled before the heat treatment for diffusing the impurities. Therefore, diffusion of impurities in the longitudinal direction is effectively suppressed. Specifically, the diffusion of nitrogen (N) forming the carrier diffusion region60in the longitudinal direction is effectively suppressed.

Therefore, the depth of the carrier diffusion region60becomes shallow, and the electrical resistance of the carrier diffusion region60becomes small. Therefore, when a forward current flows through the built-in SBD diode, lateral diffusion of carriers is promoted at the bottom of the well region54. Therefore, the on-operation of the pn junction diode built in the MOSFET201is further suppressed, and the increase in the on-resistance of the MOSFET201is suppressed.

As described above, according to the method for manufacturing a semiconductor device of the second embodiment and the modification, diffusion of impurities due to heat treatment can be suppressed by ion implantation of carbon.

Third Embodiment

A method for manufacturing a semiconductor device of a third embodiment is different from the method for manufacturing a semiconductor device of the second embodiment in that a MOSFET having a trench gate structure in which a gate electrode is provided in a trench is manufactured. Hereinafter, description of contents overlapping with the first embodiment or the second embodiment may be partially omitted.

FIG.30is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment. The semiconductor device of the third embodiment is a MOSFET300. The MOSFET300has a trench gate structure in which a gate electrode is provided in a trench.

The MOSFET300includes a silicon carbide layer10, a gate insulating layer40, a gate electrode42, an interlayer insulating film44, a source electrode46, and a drain electrode48.

The silicon carbide layer10includes a trench11, an n+-type drain region50, an n−-type drift region52, a p-type well region54, an n+-type source region56, and a p+-type well contact region58.

The silicon carbide layer10is, for example, a single crystal of 4H-SiC. The silicon carbide layer10is disposed between the source electrode46and the drain electrode48.

The trench11is provided on the source electrode46side of the silicon carbide layer10. The trench11is a groove provided on the surface of the silicon carbide layer10.

The n+-type drain region50is provided on the back surface side of the silicon carbide layer10. The drain region50contains, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drain region50is, for example, 1×1018cm−3or more and 1×1020cm−3or less.

The n−-type drift region52is provided on the drain region50. The drift region52functions as a path of an on-current of the MOSFET300.

The drift region52contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region52is, for example, 1×1015cm−3or more and 1×1016cm−3or less.

The thickness of the drift region52is, for example, 5 μm or more and 100 μm or less.

The p-type well region54is provided on the drift region52. The well region54is in contact with the side surface of the trench11. The well region54on the side surface of the trench11functions as a channel region of the MOSFET300.

The well region54contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the well region54is, for example, 1×1016cm−3or more and 1×1020cm−3or less.

The n+-type source region56is provided on the well region54. The source region56is in contact with the side surface of the trench11. The source region56contains, for example, phosphorus (P) as n-type impurities. The n-type impurity concentration of the source region56is, for example, 1×1018cm−3or more and 1×1022cm−3or less.

The p+-type well contact region58is provided on the well region54. The well contact region58is provided on the side of the source region56. The well contact region58is sandwiched between the two source regions56.

The well contact region58contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the well contact region58is, for example, 1×1018cm−3or more and 1×1022cm−3or less.

The gate insulating layer40is provided between the silicon carbide layer10and the gate electrode42. The gate insulating layer40is provided in the trench11. The gate insulating layer40contains, for example, silicon oxide.

The gate electrode42is provided on the gate insulating layer40. The gate electrode42is provided in the trench11. The gate electrode42is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

The interlayer insulating film44is formed on the gate electrode42. The interlayer insulating film44is disposed between the gate electrode42and the source electrode46. The interlayer insulating film44is, for example, a silicon oxide film.

The source electrode46is provided on the front surface side of the silicon carbide layer10. The source electrode46is electrically connected to the source region56and the well contact region58. The source electrode46is in contact with, for example, the source region56and the well contact region58.

The drain electrode48is provided on the side of the silicon carbide layer10opposite to the source electrode46, that is, on the back surface side. The drain electrode48is electrically connected to the drain region50. The drain electrode48is in contact with, for example, the drain region50.

Next, an example of the method for manufacturing a semiconductor device according to the third embodiment will be described.

FIGS.31,32,33,34,35,36,37,38, and39are explanatory diagrams of the method for manufacturing a semiconductor device according to the third embodiment.FIGS.31to39are cross-sectional views in the middle of manufacturing.

First, a silicon carbide layer10is prepared (FIG.31). The silicon carbide layer10includes an n+-type drain region50and an n−-type drift region52. The drift region52is formed on the drain region50by, for example, an epitaxial growth method.

Next, the well region54and the well contact region58are formed in the silicon carbide layer10(FIG.32). The well region54and the well contact region58are formed by ion-implanting aluminum (Al) from the surface of the silicon carbide layer10. Ion implantation of aluminum (Al) is performed using, for example, a mask material (not illustrated) as a mask.

Next, the first mask material31having the first opening31ais formed on the surface of the silicon carbide layer10(FIG.33). The first mask material31is, for example, an insulator. The first mask material31is, for example, silicon oxide.

The first mask material31is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

Next, the first ion implantation for implanting carbon (C) into the silicon carbide layer10is performed using the first mask material31as an ion implantation mask (FIG.34). A carbon region19is formed by the first ion implantation. The carbon region19is an example of the first carbon region.

The first ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The first ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or more and 1300° C. or less.

Next, a second mask material32having a second opening32ais formed on the surface of the silicon carbide layer10(FIG.35). The second mask material32is, for example, an insulator. The second mask material32is, for example, silicon oxide.

Both end portions (E1inFIG.35) of the second opening32ain the first direction are disposed inside both end portions (E2inFIG.35) of the carbon region19in the first direction. A width of the second opening32ain the first direction is smaller than a width of the carbon region19in the first direction. The first direction is a direction parallel to the surface of the silicon carbide layer10.

As illustrated inFIG.35, the second mask material32is formed by forming a sidewall material on the sidewall of the first opening31aof the first mask material31. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching. The sidewall material formed on the sidewall of the first opening31aof the first mask material31is an example of the first sidewall material.

Next, the second ion implantation for implanting phosphorus (P) into the silicon carbide layer10is performed using the first mask material31and the second mask material32as ion implantation masks (FIG.36). The source region56is formed by the second ion implantation. Phosphorus (P) implanted by the second ion implantation is an example of the first impurity. The source region56is an example of the first impurity region.

The second ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The second ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or higher and 1300° C. or lower.

Next, a third mask material33having a third opening33ais formed on the surface of the silicon carbide layer10(FIG.37). The third mask material33is, for example, an insulator. The third mask material33is, for example, silicon oxide.

As illustrated inFIG.37, the third mask material33is formed by forming a sidewall material on the sidewall of the second opening32aof the second mask material32. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching. The sidewall material formed on the sidewall of the second opening32aof the second mask material32is an example of the second sidewall material.

Next, the trench11is formed in the silicon carbide layer10using the first mask material31, the second mask material32, and the third mask material33as etching masks (FIG.38). The trench11is formed by using, for example, a reactive ion etching method.

Next, the first mask material31, the second mask material32, and the third mask material33are removed (FIG.39).

Next, a carbon film (not illustrated) is formed on the surface of the silicon carbide layer10.

Next, heat treatment is performed. The heat treatment is performed, for example, at 1600° C. or more and 2000° C. or less. The heat treatment is performed in a non-oxidizing atmosphere. The heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

The heat treatment activates aluminum and phosphorus ion-implanted into the silicon carbide layer10. The heat treatment is activation annealing of aluminum and phosphorus. Further, interstitial carbon formed by carbon ion implantation into the silicon carbide layer10by heat treatment fills carbon vacancy in the silicon carbide layer10.

Next, the carbon film is removed. After that, the gate insulating layer40, the gate electrode42, the interlayer insulating film44, and the source electrode46are formed on the surface of the silicon carbide layer10using a known process technique. In addition, the drain electrode48is formed on the back surface of the silicon carbide layer10.

The MOSFET300illustrated inFIG.30is manufactured by the above manufacturing method.

In the method for manufacturing a semiconductor device according to the third embodiment, carbon (C) is introduced into a range wider than a range in which impurities are ion-implanted by ion implantation, similarly to the method for manufacturing a semiconductor device according to the first and second embodiments. By the above method, the density of carbon vacancies in the silicon carbide layer is reduced, and diffusion of impurities ion-implanted into silicon carbide due to heat treatment can be suppressed.

For example, in the MOSFET300, when the diffusion of the n-type impurity in the source region56in the lateral direction (first direction) increases, the width in the first direction of the well contact region58between the adjacent trenches11or the width in the first direction of the well region54between the adjacent trenches11decreases. When the width in the first direction of the well contact region58between the adjacent trenches11or the width in the first direction of the well region54between the adjacent trenches11decreases, for example, avalanche withstand capability of the MOSFET300decreases. In addition, when the width of the well contact region58in the first direction or the width of the well region54in the first direction decreases, for example, an electric potential of the well region54becomes unstable, and the operation of the MOSFET300becomes unstable. Therefore, it is difficult to realize the scaling-down of the MOSFET300.

According to the method for manufacturing a semiconductor device of the third embodiment, diffusion of n-type impurities in the source region56in the lateral direction (first direction) is suppressed. Therefore, it is possible to suppress a decrease in the width of the well contact region58of the MOSFET300in the first direction or the width of the well region54in the first direction. Therefore, the scaling-down of the MOSFET300can be realized.

In addition, in the MOSFET300, as the diffusion of the n-type impurity in the source region56in the vertical direction increases, the channel length (L inFIG.30) of the MOSFET300decreases. When the channel length L decreases, the threshold voltage of the MOSFET300decreases.

According to the semiconductor device manufacturing method of the third embodiment, diffusion of n-type impurities in the source region56in the vertical direction is suppressed. Therefore, it is possible to prevent the channel length L of the MOSFET200from being shortened. Therefore, a decrease in the threshold voltage of the MOSFET300can be suppressed.

As described above, according to the method for manufacturing a semiconductor device of the third embodiment, diffusion of impurities due to heat treatment can be suppressed by ion implantation of carbon.

Fourth Embodiment

A method for manufacturing a semiconductor device of a fourth embodiment is different from the method for manufacturing a semiconductor device of the second embodiment in that a MOSFET having a super junction structure is manufactured. Hereinafter, description of contents overlapping with the first embodiment or the second embodiment may be partially omitted.

FIG.40is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment. The semiconductor device of the fourth embodiment is a MOSFET400. The MOSFET400has a super junction structure.

The MOSFET400includes a silicon carbide layer10, a gate insulating layer40, a gate electrode42, an interlayer insulating film44, a source electrode46, and a drain electrode48.

The silicon carbide layer10includes an n+-type drain region50, an n−-type drift region52, a p-type pillar region53, a p-type well region54, an n+-type source region56, and a p+-type well contact region58. The p-type pillar region53includes a first p-type region53a, a second p-type region53b, and a third p-type region53c.

The silicon carbide layer10is, for example, a single crystal of 4H-SiC. The silicon carbide layer10is disposed between the source electrode46and the drain electrode48.

The n+-type drain region50is provided on the back surface side of the silicon carbide layer10. The drain region50contains, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drain region50is, for example, 1×1018cm−3or more and 1×1020cm−3or less.

The n−-type drift region52is provided on the drain region50. The drift region52functions as a path of an on-current of the MOSFET300.

The drift region52contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region52is, for example, 1×1015cm−3or more and 1×1016cm−3or less.

The thickness of the drift region52is, for example, 5 μm or more and 100 μm or less.

The p-type pillar region53is provided between the drain region50and the well region54. The pillar regions53are repeatedly disposed in the first direction. The drift region52is provided between the adjacent pillar regions53.

The pillar regions53are alternately disposed with the drift region52in the first direction to form a so-called super junction structure. Since the MOSFET400has a super junction structure, the breakdown voltage is improved.

The pillar region53contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the pillar region53is, for example, 1×1016cm−3or more and 1×1020cm−3or less.

The p-type well region54is provided on the drift region52and the pillar region53. The well region54is disposed between the drift region52and the gate insulating layer40. The well region54functions as a channel region of the MOSFET400.

The well region54contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the well region54is, for example, 1×1016cm−3or more and 1×1020cm−3or less.

The n+-type source region56is provided on the well region54. The source region56contains, for example, phosphorus (P) as n-type impurities. The n-type impurity concentration of the source region56is, for example, 1×1018cm−3or more and 1×1022cm−3or less.

The p+-type well contact region58is provided on the well region54. The well contact region58is provided on the side of the source region56.

The well contact region58contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the well contact region58is, for example, 1×1018cm−3or more and 1×1022cm−3or less.

The gate insulating layer40is provided between the silicon carbide layer10and the gate electrode42. The gate insulating layer40contains, for example, silicon oxide.

The gate electrode42is provided on the gate insulating layer40. The gate electrode42is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

The interlayer insulating film44is formed on the gate electrode42. The interlayer insulating film44is disposed between the gate electrode42and the source electrode46. The interlayer insulating film44is, for example, a silicon oxide film.

The source electrode46is provided on the front surface side of the silicon carbide layer10. The source electrode46is electrically connected to the source region56and the well contact region58. The source electrode46is in contact with, for example, the source region56and the well contact region58.

The drain electrode48is provided on the side of the silicon carbide layer10opposite to the source electrode46, that is, on the back surface side. The drain electrode48is electrically connected to the drain region50. The drain electrode48is in contact with, for example, the drain region50.

Next, an example of a method for manufacturing a semiconductor device according to the fourth embodiment will be described.

FIGS.41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59, and60are explanatory diagrams of the method for manufacturing a semiconductor device according to the fourth embodiment.FIGS.41to60are cross-sectional views in the middle of manufacturing.

First, a silicon carbide layer10ais prepared (FIG.41). The silicon carbide layer10aincludes an n-type drain region50and an n−-type drift region52a. The drift region52ais formed on the drain region50by, for example, an epitaxial growth method.

Next, the first mask material31having the first opening31ais formed on the surface of the silicon carbide layer10a(FIG.42). The first mask material31is, for example, an insulator. The first mask material31is, for example, silicon oxide.

Next, the first ion implantation for implanting carbon (C) into the silicon carbide layer10ais performed using the first mask material31as an ion implantation mask (FIG.43). The first carbon region19ais formed by the first ion implantation.

The first ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The first ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10is 1000° C. or more and 1300° C. or less.

Next, a second mask material32having a second opening32ais formed on the surface of the silicon carbide layer10a(FIG.44). The second mask material32is, for example, an insulator. The second mask material32is, for example, silicon oxide.

As illustrated inFIG.44, the second mask material32is formed by forming a sidewall material on the sidewall of the first opening31aof the first mask material31. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching. The sidewall material formed on the sidewall of the first opening31aof the first mask material31is an example of the first sidewall material.

The sidewall material becomes the second mask material32. The opening formed by the sidewall material is the second opening32a. Both end portions (E1inFIG.44) of the second opening32ain the first direction are disposed inside both end portions (E2inFIG.44) of the first carbon region19ain the first direction.

Next, the second ion implantation for implanting aluminum into the silicon carbide layer10ais performed using the first mask material31and the second mask material32as ion implantation masks (FIG.45). The first p-type region53ais formed by the second ion implantation. Aluminum implanted by the second ion implantation is an example of the first impurity. The first p-type region53ais an example of a first impurity region.

The second ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The second ion implantation is performed, for example, in a state where the temperature of the silicon carbide layer10ais 1000° C. or higher and 1300° C. or lower.

Next, the first mask material31and the second mask material32are removed. The first mask material31and the second mask material32are removed by, for example, wet etching.

Next, heat treatment is performed (FIG.46). The heat treatment is performed, for example, at 1600° C. or more and 2000° C. or less. The heat treatment is performed in a non-oxidizing atmosphere. The heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

The heat treatment activates aluminum ion-implanted into the silicon carbide layer10a. The heat treatment is activation annealing of aluminum. Further, interstitial carbon formed by carbon ion implantation into the silicon carbide layer10aby the heat treatment fills the carbon vacancies in the silicon carbide layer10a. In addition, defects formed in the silicon carbide layer10aby ion implantation are repaired by the heat treatment. By forming the carbon layer on the silicon carbide layer10abefore the heat treatment, surface roughness of the silicon carbide layer10aduring the heat treatment can be suppressed. The carbon layer is removed by ashing after the heat treatment.

Next, an n-type first silicon carbide film10bis formed on the silicon carbide layer10a(FIG.47). The first silicon carbide film10bis formed by an epitaxial growth method.

Next, a third mask material33having a third opening33ais formed on the surface of the first silicon carbide film10b(FIG.48). The third mask material33is, for example, an insulator. The third mask material33is, for example, silicon oxide.

Next, the third ion implantation for implanting carbon (C) into the first silicon carbide film10bis performed using the third mask material33as an ion implantation mask (FIG.49). The second carbon region19bis formed by the third ion implantation.

The third ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The third ion implantation is performed, for example, in a state where the temperature of the first silicon carbide film10bis 1000° C. or more and 1300° C. or less.

Next, a fourth mask material34having a fourth opening34ais formed on the surface of the first silicon carbide film10b(FIG.50). The fourth mask material34is, for example, an insulator. The fourth mask material34is, for example, silicon oxide.

As illustrated inFIG.50, the fourth mask material34is formed by forming a sidewall material on the sidewall of the third opening33aof the third mask material33. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching. The sidewall material formed on the sidewall of the third opening33aof the third mask material33is an example of the second sidewall material.

The sidewall material becomes the fourth mask material34. The opening formed by the sidewall material is the fourth opening34a. Both end portions (E1inFIG.50) of the fourth opening34ain the first direction are disposed inside both end portions (E2inFIG.50) of the second carbon region19bin the first direction.

Next, the fourth ion implantation for implanting aluminum into the first silicon carbide film10bis performed using the third mask material33and the fourth mask material34as ion implantation masks (FIG.51). The second p-type region53bis formed by the fourth ion implantation. The second p-type region53bis in contact with the first p-type region53a. Aluminum implanted by the fourth ion implantation is an example of the second impurity. The first impurity and the second impurity have the same conductivity type. The second p-type region53bis an example of a second impurity region.

The fourth ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The fourth ion implantation is performed, for example, in a state where the temperature of the first silicon carbide film10bis 1000° C. or more and 1300° C. or less.

Next, the third mask material33and the fourth mask material34are removed. The third mask material33and the fourth mask material34are removed by, for example, wet etching.

Next, heat treatment is performed (FIG.52). The heat treatment is performed, for example, at 1600° C. or more and 2000° C. or less. The heat treatment is performed in a non-oxidizing atmosphere. The heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

Aluminum ion-implanted into the first silicon carbide film10bis activated by the heat treatment. The heat treatment is activation annealing of aluminum. Further, interstitial carbon formed by carbon ion implantation into the first silicon carbide film10bby the heat treatment fills carbon vacancies in the first silicon carbide film10b. In addition, defects formed in first silicon carbide film10bby ion implantation are repaired by the heat treatment. By forming a carbon layer on first silicon carbide film10bbefore the heat treatment, surface roughness of first silicon carbide film10bduring the heat treatment can be suppressed. The carbon layer is removed by ashing after the heat treatment.

Next, an n-type second silicon carbide film10cis formed on the first silicon carbide film10b(FIG.53). The second silicon carbide film10cis formed by an epitaxial growth method.

Next, a fifth mask material35having a fifth opening35ais formed on the surface of the second silicon carbide film10c(FIG.54). The fifth mask material35is, for example, an insulator. The fifth mask material35is, for example, silicon oxide.

Next, the fifth ion implantation for implanting carbon (C) into the second silicon carbide film10cis performed using the fifth mask material35as an ion implantation mask (FIG.55). The third carbon region19cis formed by the fifth ion implantation.

The fifth ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The fifth ion implantation is performed, for example, in a state where the temperature of the second silicon carbide film10cis 1000° C. or more and 1300° C. or less.

Next, a sixth mask material36having a sixth opening36ais formed on the surface of the second silicon carbide film10c(FIG.56). The sixth mask material36is, for example, an insulator. The sixth mask material36is, for example, silicon oxide.

As illustrated inFIG.56, the sixth mask material36is formed by forming a sidewall material on the sidewall of the fifth opening35aof the fifth mask material35. The sidewall material can be formed by, for example, deposition of an insulating film serving as a sidewall material and anisotropic etching.

The sidewall material becomes the sixth mask material36. The opening formed by the sidewall material is the sixth opening36a. Both end portions (E1inFIG.56) of the sixth opening36ain the first direction are disposed inside both end portions (E2inFIG.56) of the third carbon region19cin the first direction.

Next, sixth ion implantation of implanting aluminum into the second silicon carbide film10cis performed using the fifth mask material35and the sixth mask material36as ion implantation masks (FIG.57). The third p-type region53cis formed by the sixth ion implantation. The third p-type region53cis in contact with the second p-type region53b.

The sixth ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The sixth ion implantation is performed, for example, in a state where the temperature of the second silicon carbide film10cis 1000° C. or more and 1300° C. or less.

Next, the fifth mask material35and the sixth mask material36are removed. The fifth mask material35and the sixth mask material36are removed by, for example, wet etching.

Next, heat treatment is performed (FIG.58). The heat treatment is performed, for example, at 1600° C. or more and 2000° C. or less. The heat treatment is performed in a non-oxidizing atmosphere. The heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

Aluminum ion-implanted into the second silicon carbide film10cis activated by the heat treatment. The heat treatment is activation annealing of aluminum. Further, interstitial carbon formed by carbon ion implantation into the second silicon carbide film10cby the heat treatment fills the carbon vacancies in the second silicon carbide film10c. In addition, defects formed in second silicon carbide film10cby ion implantation are repaired by the heat treatment. By forming a carbon layer on second silicon carbide film10cbefore the heat treatment, surface roughness of second silicon carbide film10cduring the heat treatment can be suppressed. The carbon layer is removed by ashing after the heat treatment.

Next, an n-type third silicon carbide film10dis formed on the second silicon carbide film10c(FIG.59). The third silicon carbide film10dis formed by an epitaxial growth method.

Next, for example, the p-type well region54, the n+-type source region56, and the p+-type well contact region58are formed in the third silicon carbide film10dusing a manufacturing method similar to the manufacturing method of the second embodiment.

After that, the gate insulating layer40, the gate electrode42, the interlayer insulating film44, and the source electrode46are formed on the surface of the silicon carbide layer10using a known process technique. In addition, the drain electrode48is formed on the back surface of the silicon carbide layer10.

The MOSFET400illustrated inFIG.40is manufactured by the above manufacturing method.

In the method for manufacturing a semiconductor device according to the fourth embodiment, carbon (C) is introduced into a range wider than a range in which impurities are ion-implanted by ion implantation, similarly to the methods for manufacturing a semiconductor device according to the first to third embodiments. By the above method, the density of carbon vacancies in the silicon carbide layer is reduced, and diffusion of impurities ion-implanted into silicon carbide due to heat treatment can be suppressed.

For example, in the MOSFET400, when the diffusion of the p-type impurity in the pillar region53in the lateral direction (first direction) increases, the width in the first direction of the drift region52between the pillar regions53adjacent to each other decreases. When the width of the drift region52in the first direction decreases, the on-resistance of the MOSFET400increases. Therefore, it is difficult to the scaling-down of the MOSFET400.

According to the method for manufacturing a semiconductor device of the fourth embodiment, diffusion of p-type impurities in the pillar regions53in the lateral direction (first direction) is suppressed. Therefore, it is possible to suppress a decrease in the width of the drift region52of the MOSFET400in the first direction. Therefore, the scaling-down of the MOSFET400can be realized.

As described above, according to the method for manufacturing a semiconductor device of the fourth embodiment, diffusion of impurities due to heat treatment can be suppressed by ion implantation of carbon.

In the first to fourth embodiments, the n-type impurity is, for example, nitrogen or phosphorus. Arsenic (As) or antimony (Sb) can also be applied as the n-type impurity.

In the first to fourth embodiments, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be applied as the p-type impurity.

As described above, in the first to fourth embodiments, the case of 4H-SiC has been described as an example of the crystal structure of silicon carbide, but the present disclosure can also be applied to silicon carbide of other crystal structures such as 6H-SiC and 3C-SiC.