Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires

A method of manufacturing silicon nano wires including forming microgrooves on a surface of a silicon substrate, forming a first doping layer doped with a first dopant on the silicon substrate and forming a second doping layer doped with a second dopant between the first doping layer and a surface of the silicon substrate, forming a metal layer on the silicon substrate, forming catalysts by heating the metal layer within the microgrooves of the silicon substrate and growing the nano wires between the catalysts and the silicon substrate using a thermal process.

This application claims priority to Korean Patent Application Nos. 10-2005-0016184 and 10-2006-0009821, filed on Feb. 25, 2005 and Feb. 1, 2006, respectively, and all the benefits accruing therefrom under 35 U.S.C. §119, the contents of which are incorporated herein in their entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to silicon nano wires, a semiconductor device including the same, and a method of manufacturing the silicon nano wires.

More particularly, the present invention relates to nano wires having a p-n junction structure in which the size and distribution of nucleation regions for forming the nano wires are accurately controlled when forming silicon nano wires, and a method of manufacturing the same.

2. Description of the Related Art

Nano wires are currently being widely researched, and are a next-generation technology used in various devices such as optical devices, transistors, and memory devices. Materials used in conventional nano wires include silicon, zinc oxide, and gallium nitride, which is a light emitting semiconductor. The conventional nano wire manufacturing technique is sufficiently developed to be used for altering of the length and width of nano wires.

Quantum dots or nano light emitting devices using quantum dots are used in conventional nano light emitting devices. Organic electroluminescent (EL) devices using quantum dots have high radiative recombination efficiency but low carrier injection efficiency. Gallium nitride light-emitting diodes (GaN LEDs), which use quantum wells, have relatively high radiative recombination efficiency and carrier injection efficiency. However, it is very difficult to mass produce GaN LED due to a defect caused by the difference in the crystallization structures of the GaN LED and a commonly used sapphire substrate. Thus the manufacturing costs of GaN LEDs are relatively high. A nano light emitting device using nano wires has very high radiative recombination efficiency and relatively high carrier injection efficiency. In addition, the manufacturing process of a nano light emitting device is simpler and a nano light emitting device can be formed to have a crystallization structure that is practically similar to that of a substrate. Thus it is easier to mass produce the nano light emitting device.

FIGS. 1A through 1Dare cross-sectional views illustrating a vapor-liquid-solid (VLS) method, which is a conventional method of manufacturing nano wires.

Thereafter, referring toFIG. 1B, a metal layer12is formed on top of the substrate11by spreading a metal such as Au.

Then, referring toFIG. 1C, the resultant structure is thermally processed at approximately 500° C. As a result, materials in the metal layer12are agglomerated, thereby forming catalysts13. The sizes of the catalysts13may be irregular, that is, they have random sizes such as varying thickness and width.

After forming the catalysts13as described above, nano wires14are formed as the catalysts13as nucleation regions, as illustrated inFIG. 1D. The nano wires14are formed by supplying, for example, silane (SiH4), which is a compound of silicon and hydrogen, to the catalysts13to induce nucleation of Si of silane at the locations where the catalysts13are formed. When silane is continually supplied, the nano wires14can continuously grow from the bottom of the catalysts13, as illustrated inFIG. 1D.

As described above, nano wires with desired lengths can be easily formed by appropriately controlling the amount of supplied material gas such as silane. However, the growth of nano wires can be limited by the diameters and distribution, (such as the arrangement, location, formation regions, spacing or density) of the catalysts. Thus it is difficult to accurately control the thickness and distribution of nano wires. In addition, nano wire doping as described above may be performed by mixing a supply gas and a doping material, but nano wires cannot be formed to have a p-n junction structure.

SUMMARY OF THE INVENTION

The present invention provides silicon nano wires including a p-n junction structure and a method of manufacturing the nano wires in which the p-n junction structure have desired sizes and distribution by controlling the diameters and distribution of the silicon nano wires, a semiconductor device including the silicon nano wires, and a method of manufacturing the silicon nano wires.

In an exemplary embodiment, a method of manufacturing silicon nano wires includes forming microgrooves on a silicon substrate, forming a first doping layer doped with a first dopant on the silicon substrate, and forming a second doping layer doped with a second dopant between the first doping layer and a surface of the silicon substrate, forming a metal layer on the silicon substrate, forming catalysts by heating the metal layer within the microgrooves and growing the nano wires between the catalysts and the silicon substrate using a thermal process.

In another exemplary embodiment, a semiconductor device includes a semiconductor substrate including a plurality of microgrooves, nano wires formed in each of the microgrooves and extending in a direction substantially perpendicular to the semiconductor substrate, and having a p-n junction structure in which a first doping region and a second doping region are formed and a metal catalyst formed on one end of each of the nano wires.

In another exemplary embodiment, a silicon nano wire structure includes a p-n junction structure in which a first doping region and a second doping region are formed and a metal catalyst on one end of each of the nano wires.

DETAILED DESCRIPTION OF THE INVENTION

For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

Before explaining for forming of silicon nano wires having a p-n junction structure, the structure of nano wires and a method of manufacturing the same will be described.FIG. 2is a cross-sectional view of nano wires22formed on a semiconductor substrate according to an embodiment of the present invention. Referring toFIG. 2, microgrooves including a plurality of microcavities are formed in the surface of a substrate21. The nano wires22grown in a vertical direction are formed in the microgrooves, and a catalyst23is formed on one end of each of the nano wires22. The microgrooves formed in the surface of the substrate21are formed to a desired dimension, such as width and/or depth, and the sizes (such as width, diameter or thickness) and distribution of the nano wires22formed on the substrate21are substantially determined according to the dimensions and distribution of the microgrooves. The microgrooves may be formed in any of a number of shapes and profiles such as is suitable for the purpose described herein. Exemplary embodiment of the microgrooves include a substantially concave or rounded shape or generally a “V” shape.

An exemplary embodiment of a method of forming the microgrooves including the microcavities in the surface of the substrate21will be described below together with a method of manufacturing the nano wires22.

FIGS. 3A through 3Dare cross-sectional views illustrating an exemplary embodiment of a method of manufacturing nano wires according to the present invention.

Referring toFIG. 3A, first, a substrate31having microgrooves36in its surface is provided. The microgrooves36having widths “d” are formed in the substrate31. The microgrooves having the microcavities may be formed as follows.

First, a dry oxidation process is performed on a surface of the silicon substrate31, in which microgrooves having microcavities are to be ultimately formed, to form a silicon oxide layer (SiO2) (not shown) on the surface of the silicon substrate31. The oxidation process may be performed by a dry oxidation process under an oxygen (O2) and chlorine gas (Cl2) atmosphere, and nitrogen gas (N2) can be further added to control the pressure within a process chamber. The dry oxidation process is performed at a high temperature of about 1150° C. for a relatively long period of time (i.e., several hours to tens of hours). In alternative exemplary embodiments, the silicon oxide layer can be formed using a wet oxidation process. The pressure inside the process chamber is determined by oxygen and nitrogen gas, and chlorine gas may be added in a smaller ratio than oxygen.

Chlorine gas increases the oxidation rate during the dry oxidation process. That is, chlorine gas accelerates the reaction or diffusion of oxidants at an interface between the silicon oxide layer and the substrate31which is a silicon layer. In addition, chlorine gas traps and neutralizes sodium in the oxide layer, and getters may be added to absorb metallic impurities and prevent stacking faults from the silicon layer. Excess chlorine beyond the threshold concentration causes the formation of additional phases between the oxide layer and the silicon layer due to the accumulation of gaseous oxidation products, thereby making the interface (SiO2/Si) between the oxide layer and the silicon layer rougher, or generally irregular.

Since, chlorine causes the interface between the silicon oxide layer and the silicon layer of the substrate31to be rougher, microgrooves are formed, thereby enabling formation of a superior quality silicon oxide layer. Thereafter, when the silicon oxide layer on the surface of the substrate31is removed through an etching process, a microgroove structure including microcavities as illustrated inFIG. 3Ais formed.

Referring toFIGS. 6A through 6D, AFM images include exemplary embodiments of surfaces of substrates to which different amounts of chlorine gas is injected.FIGS. 6A through 6Drespectively illustrate where 0, 80, 160, and 240 standard cubic centimeters per minute (sccm) of chlorine gas are injected into the process chamber. As the amount of injected chlorine gas increases, the surface gets rougher, thereby increasing the width “d” of the microgrooves.

FIG. 6Eis a graph illustrating an exemplary embodiment of surface roughness in nanometers (nm) of a cross section of the substrate after being injected with 240 sccm of chlorine gas. The left and right sections of the graph are shown distorted, but it can be seen that a microgroove surface with relatively regular grooves and having an illumination of several nm is obtained. That is, microgrooves formed at intervals of several nm can have a microcavity structure.

Referring again toFIGS. 3A-3E, after forming the microgrooves having microcavities with substantially uniform, or regular, arrangement in the substrate31as described above, a metal layer32is formed on top of the substrate31, as illustrated inFIG. 3B. The metal layer32may be made of a material which can act as a catalyst to form nano wires that are to be grown. The material may include, but is not limited to a transition metal such as Au, Ni, Ti, or Fe. The metal layer32is formed relatively thinly to a thickness of several nm. The metal layer32includes microgrooves (having microcavities) with a relatively regular arrangement, generally corresponding to the shape or profile of the surface of the substrate31formed below the metal layer32.

Next, referring toFIG. 3C, the metal layer32is heated to induce agglomeration of the metal layer32. In exemplary embodiments, it may be sufficient if the metal layer32is heated to about 500° C. The material composing the metal layer32is agglomerated within the microgrooves on the surface of the substrate31due to the heat and forms catalysts33that are nano-sized. In other words, the microgrooves formed in the surface of the substrate31at the beginning are for controlling the locations at which the catalysts33, which are formed by agglomerating the metal layer32, are to be formed and the sizes such as width and thickness of the catalysts33. As a result, regions in which the catalysts33are formed are limited by the microgrooves and the sizes such as the material quantity, thickness or width of the catalysts33can be substantially controlled by the dimensions of the microgrooves.

Thereafter, referring toFIG. 3D, nano wires34are formed where the catalysts33, which act as nucleation regions, are formed. The nano wires34are formed by inducing nucleation of Si in the microgrooves of the substrate31where the catalysts33are formed at a temperature higher than the eutectic temperature (about 363° C. in the case of Au). The nano wires34can grow to a desired length as measured in a substantially vertical direction (or a direction perpendicular to a surface of the substrate31including the microgrooves) inFIG. 3D, by controlling the temperature, the atmospheric pressure, and time. In exemplary embodiments, the temperature can range from about 500° C. to about 1100° C., and the pressure can range from 100 Torr to normal atmospheric pressure.

Consequently, the thickness (or width) of the nano wires34as measured in a direction substantially perpendicular to the length can be controlled by forming microgrooves of a desired dimension or width with microcavities in the surface of the substrate31, and the nano wires34can be grown with relatively uniform widths.

Referring toFIG. 3E, in another exemplary embodiment, an oxidation process can be additionally performed to control the widths of the nano wires34. That is, when the oxidation process is performed after the nano wires34are formed, the formation of silicon oxide layers35is accelerated, especially on sides of the nano wires34, thereby further enabling the controlling of the thickness of the nano wires34.

An exemplary embodiment of a method of manufacturing a semiconductor device including the silicon nano wires according to the present invention, which uses the method of manufacturing the nano wires described with reference toFIGS. 3A through 3E, will now be described with reference toFIGS. 4A through 4D.

Referring toFIG. 4A, a first doping layer41is formed on a substrate31in which microgrooves with microcavities are formed. A second doping layer42is formed on top of the first doping layer41and between the first doping layer41and the substrate31. In exemplary embodiments, if the first doping layer41is doped with a p-type dopant, the second doping layer42may be doped with an n-type dopant, and vice versa. The first and second doping layers41and42are formed by injecting p- and n-type dopants into different locations of the substrate in which microgrooves are formed.

Thereafter, referring toFIG. 4B, a metal layer43is formed on the second doping layer42. The metal layer43may be composed of a material which can act as a catalyst to form nano wires. In more detail, the material may include, but is not limited to, a transition metal such as Au, Ni, Ti, or Fe.

Next, referring toFIG. 4C, the metal layer43is heated to induce agglomeration and aggregation of the metal layer43so that catalysts44are formed in the microgrooves having microcavities. The catalysts44are formed in the microgrooves, and thus the sizes and distribution of the catalysts44are substantially defined by the widths and formation regions of the microgrooves.

Thereafter, referring toFIG. 4D, nano wires are formed where the catalysts44are formed in the microgrooves by inducing nucleation with Si elements and heating the catalysts44to a temperature higher than the eutectic temperature. In exemplary embodiments, the process may be performed with a temperature ranging from about 500° C. to about 1,100° C. A dopant of the second doping layer42is distributed to nano wire regions below the catalysts44where the nano wires are to be formed to form second nano wires42′. In exemplary embodiment, where the nano wires are continually grown, a dopant of the first doping layer41is injected into the lower portion of the second nano wires42′, thereby forming first nano wires41′. As a result, a p-n junction structure is formed in the nano wires.

FIG. 5is a cross-sectional view of an exemplary embodiment of a semiconductor device including the nano wires having the p-n junction structure manufactured through the method illustrated inFIGS. 4A through 4D.

Referring toFIG. 5, photoresist layers55are formed between the nano wires having the p-n junction structure illustrated inFIG. 4Dby depositing a photoresist. The p-n junction nano wires are formed on a portion of a substrate51using catalyst54and include a second nano wire53and a first nano wire52. A first electrode56is formed on another portion of the substrate51located a distance away from the p-n junction nano wires. A second electrode57is formed on top of the nano wires. Such a structure can be used in nano light emitting devices using nano wires, and has an advantage of having a very high radiative recombination efficiency and a relatively high carrier injection efficiency, as mentioned above.

According to the present invention, the widths and distribution of nano wires to be formed may be substantially limited and controlled by the dimensions and distribution of microgrooves of a substrate, by manufacturing the nano wires on the substrate in which the microgrooves having microcavities are formed. The dimension and distribution of the microgrooves on the substrate may also be controlled. Nano-sized p-n junction diodes that include the pn-n junction nano wires can be used as nano light emitting devices or electronic devices which have very high radiative recombination efficiency and relatively high carrier injection efficiency. The p-n junction structure may be easily formed in the nano wires by applying the method of manufacturing the nano wires according to the present invention.