Compensation for device property variation according to wafer location

Methods and devices are disclosed for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input. The second device is located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input.

FIELD OF DISCLOSURE

This disclosure relates to devices, particularly amplifiers, fabricated on wafers, such as wafers of SiC. The disclosure relates more particularly to techniques, methods, and circuit designs that can compensate for inhomogeneities in device properties occurring when devices are fabricated on different portions of the wafers.

BACKGROUND

Certain devices fabricated on silicon-based wafers can have properties that depend on the area or portion of the wafer on which they are fabricated. For example, the same amplifier fabricated close to the center of the wafer may produce a different output (e.g., gain) in response to the same input as its counterpart fabricated near the wafer's edge. This can happen for a number of reasons, including that the properties (e.g., chemical and/or surface properties) of the wafer itself having lateral inhomogeneities. Devices formed by epitaxial layer growth on the wafer may be subject to these changes in wafer properties including epitaxial layer doping and layer thickness known in the art. In addition or alternatively, epitaxial processes that create device layers may themselves vary when applied at different parts of the wafer.

The inhomogeneities can lead to a lack of a precise understanding and control of device properties. In some cases, they may result in devices being inadvertently be driven under inappropriate conditions (e.g., excessive input currents, etc.) Such can lead to out-of-specification components, and even system-wide failures.

Electronic Components Formed on SiC Wafers

SiC wafers can be used to form electronic components in lieu of using traditional Si (or other) wafers. In particular, SiC is suitable for applications requiring high temperature and/or high voltage performance specifications beyond those that can be realized with silicon-based devices. SiC's relatively wider band gap energy, lower intrinsic carrier concentration, higher breakdown electric field, higher thermal conductivity, and lower chemical reactivity means that SiC devices can operate under higher electric fields and higher temperatures advantageous to various electronic systems. This can improve device and component integrity under extreme conditions. SiC wafers also tend to have high resistance to thermal shock, meaning they can operate under harsh conditions without breaking or cracking.

Yet electrical devices formed on SiC substrate can be subject to the property variations described above. Epitaxial layer or other inhomogeneities on the wafer can alter performance to devices fabricated on different portions of the wafer. For example, field effect transistors (FETs) requiring channel grown epitaxially (e.g., silicon carbide (SiC) n-channel depletion mode junction field effect transistors (JFETs), which require an epitaxially grown n-channel) may have key device properties quantitatively undesirably vary with wafer position. These JFETs can have different zero body-bias threshold voltages (VTOs) resulting in different threshold voltages (VTs) depending on die position relative to the distance from the center of the wafer. Authors observed (including in Ref. [P1]) that, in such systems, as die extraction extends from the center of the die towards the edge of the wafer, the magnitude of VTO/VT increases. Such variations in VTO/VT can degrade device performance and/or make device performance less predictable which in turn can make circuit implementation and manufacturing yield more challenging to accomplish.

FET Current Source

FIG. 1shows a common n-type FET current source. Specifically, an n-type, depletion mode FET (“Q”) is configured to self-bias (i.e., by connecting its gate terminal (G) to source (S)) to produce a constant drain (D) current Id. Idis closely approximated by Equation 1:
Id=KP·(Vgs−VT)2(Equation 1)
where KP is the transconductance of the FET Q in A/V2, VT is the threshold voltage of the FET Q at a given (not necessarily zero) body bias and Vgsis Idtimes the value of resistor R in the source circuit. Thus, for a given FET, Equation 1 shows that Idis both a function of R and VT, both of which may vary on the surface of a SiC or other wafer.

TABLE 1 shows measured variation of Idin commercial FET current sources/current limiters across Diode Part Numbers, which vary in distance from the center of the wafer.

The data in Table 1 demonstrate a need for methods that compensate for changes in device properties that may occur in different portions of the wafer and temperature. Understanding how to provide such compensation could facilitate devices that operate similarly regardless of temperature or radius.

SUMMARY

Compensation methods and devices are illustrated and analog and mixed signal constructs are developed for addressing property variation in devices fabricated on a wafer. Although examples are given that apply specifically to devices fabricated on SiC wafers, it is to be understood that the principles and methods described herein are general. They may apply to other types of devices constructed on other types of wafers, including more traditional Si wafers.

A method is disclosed herein for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input, the second device located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input. The altering may comprise biasing a voltage input to the first device or adding a current source to the first device. The altering may be based on compensating for differences in properties of the wafer at the position of the first device from properties of the wafer at the position of the second device. The differences in properties may be differences in chemical properties of the wafer. The first and second devices may comprise amplifiers. The wafer may comprise SiC. The difference between the output of the first device and the output of the second device may arise at least in part from a difference in a threshold voltage for the first device and a voltage threshold for the second device.

This disclosure further describes a device designed by a method comprising determining an output of a first device based on an input. The method further comprises determining an output of a second device based on the input, the second device located at a different position with respect to a center of a wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input. The altering may comprise biasing a voltage input to the first device or adding a current source to the first device. The first and second devices may comprise amplifiers such as one or more operational amplifiers. The wafer may comprise SiC. The difference between the output of the first device and the output of the second device may arise at least in part from a difference in a threshold voltage for the first device and a voltage threshold for the second device. The outputs of the first and second device may depend on a current, e.g., drain current, associated with a device.

These and other embodiments of the invention are described in detail below.

DETAILED DESCRIPTION

Determination of Drain Voltage Dependency on Wafer Location

In order to inform their compensation methods and circuits, Authors performed simulations in the LTspice platform. The simulations model JFET and resistor (“RJFET”) performance at differing distances from the center of a SiC wafer and different temperature.

The Authors' first simulation explores Idthrough a SiC JFET as a function of sweeping the difference between the gate to source voltage (Vgs).FIGS. 2A-2Dshow the circuit topographies for this first test. Common source circuits210,220, and230inFIG. 2A, reflect a 25° C. models of components (JFETs and resistors) at distances from center of SiC wafer (herein referred to as “radius”) of 10 mm, 20 mm, and 30 mm respectively. Common source circuits240and250inFIG. 2B, reflect a 300° C. model at a radius of 10 mm and 20 mm, respectively. Common source circuits260and270inFIG. 2C, reflect a 460° C. model at a radius of 10 mm and 20 mm, respectively. Common source circuits280,290, and295inFIG. 2D, reflect a 500° C. model at a radius of 10 mm, 20 mm, and 30 mm respectively. In the study, Vgatein circuits210-295was swept from −2 to −12 V.

Components inFIGS. 2A-2Dare represented in LTspice using the NASA GRC SiC “NASA Glenn 500” C Durable JFET Technical User Guide.1The details of the models for both JFETs and are described in Exhibit A. Briefly, SiC JFETs and SiC resistors are modeled in LTspice simulations using NMOS (n-type MOSFET) parameterization. The use of a MOSFET to model JFETs and resistors is purely an expedient, and an artifact of the modeling process. The LTspice MOSFET models offers sufficient latitude with regard to parameterization to represent the complexity of JFET and resistor response to radius and temperature. The JFET and resistor components being simulated do not have MOSFET structures. Rather, they have typical JFETs and resistor structures. Use of MOSFET parameterization is not to be taken as implying anything about the structure of the JFETs and resistors being modeled. https://sic.grc.nasa.gov/jfetictechguide/

The model parameterizes JFET properties for both radius and temperature. See, e.g., Exhibit A at 12. In other words, properties of JFETs that vary with radius and temperature are directly added to the n-type MOSFET model in LTspice simulations such that the model performs as the JFET would at a particular radius and temperature. Similarly, resistor property variation with temperature is parameterized using the same n-type MOSFET models in LTspice simulations as for the JFETs, as described above. Due to the fabrication process employed present studies, resistor resistances possess minimal variation with radius and, therefore, are not parameterized by radius.

In the figures that accompany this disclosure, JFET models are given the name JFETTTTCRRv12, where ITT is temperature in ° C., and RR is radius in mm. Resistor models in schematics are given as RJFETTTTCv12, where TTT is temperature in ° C. “v12” stands for version 12. It refers to the model version used, as described in Exhibit A.

InFIGS. 2A-3D, JFET and Resistor components are represented with standard JFET and resistor symbols respectively. However, inFIGS. 3E-11, both JFET and resistor models are represented the LTspice program symbol for n-type MOSFETs that was used to generate the simulation results. The latter symbolic representation is simply a modeling expedient/artifact and, as discussed above, not meant to imply anything about the structure of the JFETs or resistors being modeled. Despite their symbolic representation, JFETs and resistors inFIGS. 3E-11have standard structure, the same structure as the JFETs and resistors inFIGS. 2A-3D. The same labeling scheme described above is also used inFIGS. 3E-11to identify these components. See, e.g., seeFIG. 6with JFET500Cr10v12 (M39), which is a model of a JFET located at a radius of 10 mm and operating at 500° C. Despite their different symbols, JFET500Cr10v12 (M39) inFIG. 6has the same model as JFET500Cr10v12 (M1) inFIG. 2D.FIG. 6also shows a RJFET500Cv12 (M7). The latter is a model of a resistor operating at a temperature of 500° C. Despite their different symbols, RJFET500Cv12 (M7) inFIG. 6has the same model as RJFET500Cv12 (M19) inFIG. 2D. Both JFET500Cr10v12 (M39) and RJFET500Cv12 (M7) are represented inFIG. 6using the n-type MOSFET symbol purely for convenience sake.

In the figures of this disclosure, each JFET is given a unique, individual designation that has the format “MX,” where “X” is an individual JFET designation number. For example, the three JFETs inFIG. 2A, JFET25Cr10v12, JFET25Cr20v12, and JFET25Cr30v12, are designated M8, M9, and M10, respectively. The JFETs in the figures herein also include a separate “M” designation, which describes the number of singular “unit-layout-cell” devices in parallel. Details for an exemplary unit-layout-cell device are provided at p. 13 of Exhibit A. For example, the three JFETs inFIG. 2Aare all “M=2” modules which means that each individual transistor is comprised of two active devices in parallel. Page 13 of Exhibit A illustrates the physical layout of an “M=4” JFET comprised of 4 unit-layout-cell modules. Additional details are explained in Exhibit A.

In the figures of this disclosure, each resistor (or RJFET) is given a unique, individual designation that also has the format “MX,” where “X” is an individual resistor designation number. The three resistors inFIG. 2A, for example, each labeled RJFET25Cv12, are designated M11, M12, and M13. Note that the resistor types are the same at each radius, r=10, 20, and 30 mm, because resistor resistance values vary with temperature, not radius. The resistors in the figures herein also include a numerical value that corresponds to the “number of squares,” contained in the physical layout of the resistor. The overall resistance of the resistor scales with the number of squares. For example, the three resistors inFIG. 2A, each resistor labeled RJFET25Cv12, all have value “300,” or 300 squares. The three top resistors inFIG. 3F, RJFET25Cv12 (M88), RJFET25Cv12 (M91), and RJFET25Cv12 (M92), are, like the resistors M11, M12, and M13ofFIG. 2A, models of resistance at T=25° C. However, the three resistors M88, M91, and M92ofFIG. 3Fare labeled “150” because they have half as many squares in their physical layout as the resistors M11, M12, and M13, which are labeled as “300.” As an example, a RJFET500Cv12 single-square resistor, referenced to ground, substrate and gate tied to −25 Volts, with 1 μAmp of current flowing through it, represents approximately 20,733Ω. Note that the electrical bias (potential) of a resistor in a circuit relative to the wafer/substrate electrical bias (potential) affects its actual resistance value due to body effect to be described below. However, it is to be understood that the relationship between the number of squares and actual resistance depends on the specific component. This relationship is not unique to this disclosure. The disclosure may apply to different components and different component types than the ones described explicitly herein.

Results of simulations involving the circuits inFIGS. 2A-2Dare shown inFIGS. 2E and 2F. Traces inFIG. 2Eshow the current (Id) through the 1Ω sense resistor “R” in each drain circuit inFIGS. 2A-2D. Each trace is labeled according to radius. The y-axis of each plot indicates the temperature being tested.

As shown inFIG. 2E, as radius in each increases at a given temperature (e.g., as radius increases from 10-30 mm over 280, 290, and 295), the negative magnitude of the threshold voltage of the respective JFET increases. As temperature increases, Idat threshold voltage decreases. As temperature increases for a given radius (see traces210-280representing r=10 mm for temperatures 25=500° C.), the negative magnitude of the threshold voltage increases.

The data inFIG. 2Eindicate that changes in threshold voltage with radius are fairly consistent regardless of temperature. This is best observed by fitting to the threshold voltage for Vgateaccording to the data inFIG. 2E. The fits show that the threshold voltage (VT) changes by about 1.65 volts between r=10 mm and r=20 mm. See, for example, DV1 inFIG. 2F, which is the difference between VT for circuit220(“VT220”) for r=20 mm and circuit210(“VT210”) at r=10 mm. Table 2 summarizes DV1 for each temperature described above.

TABLE 2DV1, the VT difference between circuits at r = 10 mmand r = 20 mm from the center of thewafer, at various temperatures.TemperatureDV1 (VTr=20mm − VTr=10mm)(° C.)(V)251.643001.644601.655001.65

The data inFIG. 2Ealso show that the threshold voltage (VT) changes by about 3.06 volts between r=20 mm and r=30 mm. See, for example, DV2 inFIG. 2F, which is the difference between VT for circuit220(“VT220”) at r=20 mm and230(“VT230”) for r=30 mm. Table 2 summarizes DV2 for each temperature described above.

TABLE 3DV2, the VT difference between circuits at r = 20 mm andr = 30 mm from the center of the wafer, at various temperatures.TemperatureDV2 (VTr=30mm − VTr=20mm)(° C.)(V)253.055003.06

These results show a substantial change in VT with both distance from center of wafer (radius) and temperature. They suggest compensation for these changes in VT may allow differently located JFETs to function similarly, regardless of inhomogeneities of the wafer or epitaxial layers on the wafer. For example, the difference DV1 in VT for devices at r=10 mm and r=20 mm, regardless of temperature, of around 1.65 V (see Table 2) may be accounted for by biasing the circuit to offset DV1. Biasing might also offset the difference DV2 in VT for devices at r=20 mm and r=30 mm, which also appears to be stable with temperature. The latter is closer to 3.06 V (see Table 3).

The VT shifts DV1 and DV2 shown in the simulation results in Tables 2 and 3, which implies that a simple current source value will change over radius. In order for circuits to operate similarly regardless of location on the wafer, some form of self-regulation is needed to make these circuits behave similarly. The next sections of this disclosure concern several methods to provide this self-regulation or compensation.

Mediation Via Current Source

In this section of this disclosure, the Authors discuss using a current source to mediate the differential operating results based on radius and temperature discussed above.

The following drain voltage changes and source voltage changes (labeled as “DIFF” inFIG. 3A) are observed:

Note that DV1 and DV2 are relatively consistent with previous results (i.e., the results shown in TABLES 2 and 3, respectively). For example DV1 in TABLE 5 is about 1.57 V, approximately equal to the 1.66 V average change in TABLE 2. Further, DV2 in TABLE 4 is 2.5-2.7 V, close also to the previously observed 3.06 V value in TABLE 3. Therefore, DV1 and DV2 are relatively consistent in both transconductance and current source configurations, suggesting that current sources may be used to offset changes in VT with radius.

However, Authors also observed that drain currents in circuits310,320, and330differ according to distance from center of the wafer. This suggests that merely offsetting bias alone may not always be sufficient for compensating for VT changes with radius.

For example, the drain current Idfor in the case of the 500° C. circuits at 10 mm (i.e., circuit340inFIG. 3B) is 2.6 μA and 20 mm (i.e., circuit350inFIG. 3B) is 3.09 uA. This represents a difference in Idfor circuits340and350of about 15.9%. We refer to the difference in Idbetween the circuits at r=20 and r=10 (e.g., circuits350and340, respectively inFIG. 3B) as DI1 and the difference in Idbetween the circuits at r=30 and r=20 (e.g., circuits360and350, respectively inFIG. 3B) as DI2. The current differences appear in Table 5.

FIG. 3Cillustrates an attempt to use biasing in the circuits ofFIG. 3B(circuits340,350, and360) to decrease the changes in Idwith distance from the center of the wafer. More specifically, bias circuits340a,350a, and360ahave been added to circuits340,350, and360, respectively. Each includes a voltage source with a −8.75 V bias (V10, V13, and V14, respectively), by generating around 5 μA of current. Current matching between circuits340,350, and360is improved by the addition of bias circuits340a,350a, and360a. For example, the difference between the current flowing through resistor R in circuit340(4.72 μA) and the same current in circuit360(5.52 μA), a difference in radius from 10 mm to 30 mm, respectively, is now around 14.5%. The DI1 and DI2 values are given in TABLE 6.

FIG. 3Dillustrates the same circuits inFIG. 3Cwith additional biases on circuits350and360added, in part, to even out Id. Biases350b(V8) and360b(V9) augment the gate voltage set point of the JFETs M52and M53, respectively.350baugments the gate voltage of M52by 1.572 V and 360b augments the gate voltage of M53by 4.11 V.

Authors observed the additional biasing provided by350band360bimproved current matching across radius. More specifically, the360bbias decreases Idflowing through R in circuit360to 4.833 μA (from 5.52 μA in the configuration shown inFIG. 3C). Since Idin circuit340remains the same at 4.72 μA, this means that the difference between Idin circuits240and260, associated with an increase in r from 10 mm to 30 mm, is now down to 2.34%, as opposed to 14.5% for the configuration inFIG. 3C. Similarly, the difference between Idin circuit340(4.72 μA) and350(4.736 μA) (i.e., between r=10 mm and 20 mm) is now 0.34%. The DI1 and DI2 values are given in Table 7.

FIG. 3Eillustrates2another realization in which the voltage sources340a-360aand350band360bare replaced by circuits340c,250c, and360c. Circuits340c,250c, and360care the same current source circuits as those shown inFIG. 3B. The circuit inFIG. 3Eleads to a similar lowering of differences in Idacross R in340,350, and360as the circuits inFIG. 3D. Specifically, the currents appear below in TABLE 8.2As discussed above, fromFIG. 3Eonward, both JFETs and RJFETs will be represented in the figures using LTspice program symbols for an n-channel MOSFET. The n-channel MOSFET symbol is merely meant to reflect how the model is parameterized. It is to be understood that these components are JFETs and RJFETs, not MOSFETs.

FIG. 3Fillustrates the drain voltage bias positioning ofFIG. 3Eapplied to the 25° C. case (i.e., the circuits inFIG. 3A). These results indicate that the technique is robust for maintaining both VT and Idover different temperatures. See Tables 9 and 10 below, which also show results for 300° C. and 400° C.

Other devices may offer more gain than the circuits discussed above. These include, for example, devices with a common source amplifier. A common source amplifier used to derive the gate bias voltage for the current source should have a gain of unity. However, such other devices may be subject to inhomogeneities in performance with temperature and radius due to variations in the wafer as well as other variations. In addition, such devices may also be subject to the body effect, which impacts both device (e.g., transistor, resistor) and circuit (e.g., gain, bandwidth, etc.) parameters. This section explores methods for addressing the body effect on such devices.

Generally, the body effect refers to the change in the transistor electrical performance properties (including VT) resulting from a voltage difference between the transistor source and body. Often, as is the case for the SiC JFET ICs we have fabricated, the transistor body terminal is physically the semiconductor wafer. Ref. [P1] describes the body effect for the SiC JFETs we have fabricated and used to construct SiC ICs. Various devices integrated onto a common semiconductor wafer substrate will have differing source-to-body biases in functional integrated circuits. The body effect can also implicate more devices other than just transistors, as described in Ref [P2]. Because the voltage difference between the source and body affects the VT, the body can be thought of as a second gate that helps determine how the transistor turns on and off. As shown in Ref. [P1], the relationship between JFET threshold voltage VT and zero-body-bias FET threshold voltage VTO is closely approximated by the following equation:
VT=VTO+GAMMA(√{square root over (2·PHIB−VS)}−√{square root over (2−PHIB)})  (Equation 2)

Wherein GAMMA is the body effect coefficient, PHIB is the built-in potential of the source-to-substrate pn junction, and VS is the source-to-body bias of the device. The calculation of GAMMA and PHIB from physical/structural SiC JFET parameters (e.g., device dimensions and doping) is detailed in Ref. [P1].

The body bias can be supplied from an external (off-chip) source or an internal (on-chip) source. The SiC JFET and resistor (“RFJET”) models described in Refs [P1] and [P2] account for the body effect.

FIG. 4illustrates the body effect for a temperature of 500° C. and r=10 and r=20 mm on the circuits340and350inFIG. 3E.

With regard to circuit340(r=10 mm), measurements reveal that the drain resistor for340c[RJFET500v12 (M40)], has an effective value of about Vdrain/I=8.751 V/2.6 μA=3.36 MΩ. The source resistor for340c[RJFET500v12 (M43)], has a value of about Vsource/I=7.63 V/2.6 μA=2.93MΩ. This yields a gain, or difference in effective resistance, of Vsource/Idrain=0.872. Yet both resistors should be the same—both have a value of 200 squares and are parameterized for the same temperature (i.e., 500° C.). The difference in effective resistance is likely accounted for by the body effect.

With regard to circuit350(r=20 mm), the corresponding measurements [for circuit350c, drain resistor RJFET500v12 (M41) and source resistor RJFET500v12 (M44)] reveal a gain of Vsource/Vdrain=9.118 V/10.322 V=0.883. Again, both resistors should be the same. Both have a nominal value of 200 squares and are parametrized for the same temperature (i.e., 500° C.). Again the difference is likely due to the body effect on both resistors.

These results appear in Table 11 below. They show, collectively, that gain differs at 500° C. for r=10 and r=20 mm due to the body effect.

Note that this results in a substantial difference between the quiescent operating points at the drain resistor [R231(circuit350) and R221(circuit340), respectively] of:
Difference in Drain Resistor Operating Points=(10.27 V−10.22 V)/10.27 V=0.49%
Such a difference would likely cause the outputs of circuits350and340to diverge in potentially unexpected ways.

FIG. 5presents a solution addressing the observed body effect and its resulting radius dependence on resistor gain. Specifically, the circuits340and350inFIG. 5trim the resistance values of the source resistors RJFET500v12 (M43) and RJFET500v12 (M44) to bring them into agreement with RJFET500v12 (M40) and RJFET500v12 (M41), in spite of the body effect. As shown inFIGS. 5, M43and M44have been trimmed from 200 to 190 squares, or from a resistance of ˜5.139 M1to a resistance of ˜4.8999 M1.FIG. 5shows that this resistor trimming results in a substantially lower difference between the quiescent operating points at the drain resistor (R231and R221, respectively):
Difference in Drain Resistor Operating Points=10.487 V−10.4712 V)/10.487 V=0.15%.

In other words, the operating point differences have been lowered from 0.49 to 0.15, or by around ⅓. This three-fold increase in performance results from reducing the resistor values most susceptible to the body effect. Although not shown, trimming the resistors M43and M44also results in an increased Idbecause of the decrease in overall resistance. Since the increase in Idoccurs for both circuits340and350, this may be a desirable result.

Note that similar results (i.e., similar decrease in the difference between quiescent operating points at drain resistors R231and R221) could also be accomplished by increasing the size (squares) of the drain resistors M40and M41, rather than decreasing source resistors M43and M44. This is because doing so would similarly decrease the fractional contribution of the source resistors M43and M44, the resistors most susceptible to the body effect. The latter technique, increasing drain resistors M40and M41, would not result in an increase in Id. It may actually decrease Id, which may be advantageous under certain conditions.

FIG. 6shows the decreased source resistor solution applied to the r=30 mm case in which T=500° C. More specifically, source resistor M7inFIG. 6has been lowered from 200 to 190 squares. As shown inFIG. 6, this results in a quiescent operating point at the drain resistor (R421) of 10.1289 V. This represents a significant change in operating point from the r=20 mm case (10.4712 V,FIG. 5, R231). It represents a change in gate bias voltage for current source in the r=30 mm and r=20 mm cases (i.e., a difference in gate bias on M52inFIG. 6and M49inFIG. 5=13.23 V−10.8167 V=2.4 V). A comparison of this value with DV2 (VTr=30mm−VTr=20mm) in Table 3 (i.e., the difference in gate threshold voltage for r=20 and 30 mm at 500° C.) shows that it is lower by around 20%. In other words, the additional components inFIG. 6do not completely make up for the effect of radius on device performance.

FIGS. 7A, 7B, and 8show applying the source resistor trimming effect to temperature configurations for r=10 mm and r=20 mm at 25° C., 300° C., and 460° C., respectively. Table 12 summarizes the results.

TABLE 12Gain for the self-biased current source circuits340c and 350c at 500° C. in FIG. 4.Drain ResistorsDifference in QuiescentTemp.inOperating Points(° C.)CircuitsCurrent Sourceat Drain Resistor (%)25710 and 720R25 and R260.10300730 and 750R28 and R290.12460810 and 820R30 and R310.14

The results show a decrease of around ⅓ in difference in drain resistor operating points compared to the case shown inFIG. 4without resistance trimming (i.e., 0.49%). Therefore, the results show that the resistor technique is effective at decreasing the body effect at these temperatures as well.

Application of Design Principles to Amplifiers

In a common source configuration, the gain of a JFET amplifier can be expressed as:
JFET Gain=−(gm)Rd(Equation 3)
Where: gm=the JFET conductance and Rd=the resistance of the drain resistor. In the circuits discussed so far in this disclosure, a maximum of 300 squares resistance has been used. The maximum resistor topography is M=96. However, it is to be understood that these methods and principles apply to any suitable resistance or topography values.

As an example, authors applied the above principles to a single output differential amplifier using the current sources and bias scheme ofFIG. 7Afor T=25° C. The amplifier900is shown inFIG. 9. As can be seen inFIG. 9, the amplifier900has a portion900acorresponding to r=10 mm and another portion900bcorresponding to r=20 mm. Portion900aencompasses circuits710and710cfromFIG. 7. Portion900bencompasses circuits720and720cfromFIG. 7. In other words, the single output differential amplifiers900aand900butilize the current sources and the bias scheme of the circuits inFIG. 7.

Amplifier900was tested with a 1 mV peak-to-peak sine wave as input (vsine). This input is shown as “vsine” inFIG. 10A. The output of amplifier900ais labeled “vout25r10.” The output of amplifier900bis labeled “vout25r20.”

Inset10ainFIG. 10Ashows a calculation of gain for circuit900a(r=10 mm) based on vout25r10. More specifically, the gain is the vertical difference between cursor positions at a bias of 12.275 V, divided by vsine, or ˜137.7 V/V. Inset10binFIG. 10Bshows the similarly calculated the gain of the r=20 mm circuit (900b). That gain is ˜132.35 V/V, biased at approximately 12.29 V. In other words, the difference in operation of circuits310and320(r=10 vs. 20 mm) is rather small. Therefore, amplifiers900aand900bwill function similarly thanks to compensation provided by circuits310cand320c, despite their differing locations from the center of the wafer (i.e., radius).

FIG. 11shows application of similar current source biasing to an operational amplifier1100at T=500° C. and r=10 mm, incorporating the circuit340cfromFIG. 5.FIG. 12shows the same amplifier1200at T=500° C. and r=20 mm, incorporating the circuit350cfromFIG. 5. Both amplifiers1100and1200have an open loop gain configuration. The inverting inputs to each amplifier (“−”) are tied to ground. The non-inverting inputs (“+”) are each driven by a sine wave (“v_in”). In the test, three different sine waves v_in_1, v_in_2, and v_in_3, are input, shown inFIGS. 13, 14, and 15, respectively. v_in_1 has a peak-to-peak amplitude of 200 μV, v_in_2 has a peak-to-peak amplitude of 1 mF, and v_in_3 has a peak-to-peak amplitude of 20 mV. Each ofFIGS. 13, 14, and 15calculates the amplifier gain “Avol” equal to Voutput/Vinput. The results are summarized in Table 13 below.

FIGS. 16 and 17show two examples of closed-loop operational amplifiers according to aspects of the present disclosure.FIG. 16shows an operational amplifier1600at T=500° C. and r=10 mm, incorporating the circuit340cfromFIG. 5.FIG. 17shows a similar operational amplifier1700at T=500° C. and r=20 mm, incorporating the circuit350cfromFIG. 5.

Both amplifiers1600and1700have a closed loop, unity gain configuration in which the output of the amplifier (v_out_r10 for1600and v_out_r20 for1700) is tied to the inverting input (“−”). The non-inverting inputs (“+”) are each driven by a sine wave (“v_in”) that is 2V peak-to-peak.

The input and output signals are shown inFIG. 18. The gain (Av), which is the same for both amplifiers1600and1700, is shown in Table 14.

Therefore, these results illustrate that the gain between amplifiers1600and1700, at r=10 mm and 20 mm, respectively, is essentially identical.

Note that gain in the above amplifiers900,1100,1200,1600, and1700is limited by the transistor size. Specifically, we have a practical maximum M at 96 for the present prototype generation of JFET ICs presently under fabrication by NASA. The limitation is due to layout constraints such as maximum device junction area that have been conservatively defined so that parasitic junction leakage currents at 500° C. will not become large enough to interfere with desired signal currents. This limitation may be somewhat overcome by further future improvements to the SiC JFET fabrication technology as well as less-conservative layout rule constraints depending upon the specific circuit and application.