Pulse width modulation controllers for hybrid converters

Pulse width modulation (PWM) controllers for hybrid converters are provided herein. In certain embodiments, a PWM controller for a hybrid converter includes a threshold generation circuit for generating a threshold signal based on an output voltage of the hybrid converter, a threshold adjustment circuit for generating an adjusted threshold signal based on sensing a voltage of a flying capacitor of the hybrid converter, and a comparator that generates a comparison signal based on comparing the adjusted threshold signal to an indication of an inductor current of the hybrid converter. The output of the comparator is used for generating PWM control signals used for turning on and off the switches (for instance, power transistors) of the hybrid converter.

FIELD OF THE DISCLOSURE

Embodiments of the invention relate to electronic systems, and more particularly, to electronic power conversion.

BACKGROUND

A voltage regulator serves to generate a substantially constant output voltage from a poorly-specified and/or fluctuating supply voltage or other input voltage source. Series regulators and switching regulators are two common types of voltage regulators. Low dropout (LDO) series regulators provide good regulation with very low noise, however, the current supply from the regulated output comes directly from the supply voltage. Thus, an LDO series regulator's efficiency is limited by the ratio of the output voltage to the supply voltage, and thus the efficiency of the LDO series regulator drops rapidly as the supply voltage increases relative to the output voltage.

Switching regulators are generally more efficient than series regulators. A switching regulator employs one or more switches (for instance, power transistors) coupled in series and/or parallel with an output terminal that provides an output voltage to a load. Additionally, a controller turns the switches ON and OFF to control delivery of current pulses to the output terminal. One or more energy storage elements, such as inductor(s) and/or capacitor(s), can be used to convert the switched current pulses into a steady load current.

SUMMARY OF THE DISCLOSURE

Pulse width modulation (PWM) controllers for hybrid converters are provided herein. In certain embodiments, a PWM controller for a hybrid converter includes a threshold generation circuit for generating a threshold signal based on an output voltage of the hybrid converter, a threshold adjustment circuit for generating an adjusted threshold signal based on sensing a voltage of a flying capacitor of the hybrid converter, and a comparator that generates a comparison signal based on comparing the adjusted threshold signal to an indication of an inductor current of the hybrid converter. The output of the comparator is used for generating PWM control signals used for turning on and off the switches (for instance, power transistors) of the hybrid converter. By implementing the PWM controller in this manner, stable operation of the hybrid converter is achieved even when power stage mismatches are present and/or the PWM controller has asymmetries in circuitry used for generating the PWM controls signals of the hybrid converter's power stage(s).

In one aspect, a power conversion system includes a power converter and a PWM controller. The power converter is configured to generate a regulated output voltage based on an input voltage, and includes a first inductor, a first capacitor, and a first group of switches configured to control electrical connectivity of the first inductor and the first capacitor. The PWM controller includes a threshold generation circuit configured to generate a threshold signal based on the regulated output voltage, a first threshold adjustment circuit configured to generate a first adjusted threshold signal by adjusting the threshold signal based on the input voltage and a voltage of the first capacitor, a first comparator configured to compare a current through the first inductor to the first adjusted threshold signal, and a switch control circuit configured to generate at least one control signal for controlling the first group of switches based on an output of the first comparator.

In another aspect, a method of power conversion includes generating a regulated output voltage based on an input voltage using a power converter that includes a first inductor, a first capacitor, and a first group of switches for controlling electrical connectivity of the first inductor and the first capacitor, generating a threshold signal based on the regulated output voltage using a threshold generation circuit, generating a first adjusted threshold signal by adjusting the threshold signal based on the input voltage and a voltage of the first capacitor using a first threshold adjustment circuit, comparing a current through the first inductor to the first adjusted threshold signal using a first comparator, and controlling the first group of switches based on an output of the first comparator.

In another aspect, a PWM controller includes a threshold generation circuit configured to generate a threshold signal based on a regulated output voltage of a power converter, a first threshold adjustment circuit configured to generate a first adjusted threshold signal by adjusting the threshold signal based on an input voltage of the power converter and a first capacitor voltage of the power converter, a first comparator configured to compare a first inductor current of the power converter to the first adjusted threshold signal, and a switch control circuit configured to generate at least one switch control signal for the power converter based on an output of the first comparator.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

FIG.1Ais a schematic diagram of one example of a buck converter10.FIG.1Bis a graph showing one example of control signal and inductor current waveforms for the buck converter10ofFIG.1A.FIG.1Cis a graph showing one example of transistor drain current, transistor drain-to-source voltage, and transistor power loss for the buck converter10ofFIG.1A.

The buck converter10includes a top power transistor M1, a bottom power transistor M2, an inductor L, and an output capacitor COUT. The buck converter receives an input voltage VINand generates an output voltage VOthat is less than the input voltage VIN. The output voltage VOis provided to an external load (LOAD), in this example. The top power transistor M1is connected between the input voltage VINand the switch node SW, the bottom power transistor M2is connected between the switch node SW and ground, the inductor L is connected between the switch node SW and the output voltage VO, and the output capacitor COUTis connected between the output voltage VOand ground.

In the example ofFIG.1A, the top power transistor M1is controlled by a top control signal T, and the bottom power transistor M2is controlled by a bottom control signal B. By adjusting or modulating the width of the top control signal T and the bottom control signal B, regulation of the output voltage VOis achieved.

For example, the top power transistor M1is turned on when the top control signal T is high, while the bottom power transistor M2is turned on when the complimentary bottom control signal B is high. When the top power transistor M1is on, the input voltage VINis applied to the switch node SW and the current iLthrough the inductor L ramps up. When the bottom power transistor M2is on, the ground potential is applied to the switch node SW and the inductor current iLramps down.

This operation repeats periodically, and the switching period is TSW. The ratio of the on-time of top power transistor M1over the switching period TSWis referred to as duty cycle.

Since the ramp up slope of the inductor current iLis determined by the voltage difference between the switch node SW and the output voltage VO, larger current ripple amplitude is present at lower switching frequency. Thus, to support a given DC output load current, a larger-sized inductor L is selected to avoid inductor saturation at peak current.

The on/off transition of a power transistor for a power converter cannot be done in zero time. During the transition time, the drain to source voltage and current through the power transistor are both non-zero. This leads to the switching loss of the power transistor for each transition from on to off, or from off to on state. The higher the drain to source voltage that the power transistor blocks, the higher the switching loss that the power transistor has each time it switches.

For instance, in the example ofFIG.1C, waveforms for the voltage, current, and power loss of the top power transistor M1are shown for one example state transition.

The switching loss limits the practical maximum switching frequency. However, high switching frequency is desired for a compact size power supply.

FIG.2Ais a schematic diagram of one embodiment of a hybrid converter111.FIG.2Bis a schematic diagram of one embodiment of control logic circuitry for the hybrid converter111ofFIG.2A.FIG.2Cis a schematic diagram of one example of low duty cycle regulation for the hybrid converter111ofFIG.2A.FIG.2Dis a schematic diagram of one example of high duty cycle regulation for the hybrid converter111ofFIG.2A.

The hybrid converter111includes a first half power stage P1including a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, a fourth power transistor Q4, a first inductor L1, and a first switched capacitor Cfly1(also referred to herein as a flying capacitor). The hybrid converter111further includes a second half power stage P2including a fifth power transistor Q5, a sixth power transistor Q6, a seventh power transistor Q7, an eight power transistor Q8, a second inductor L2, and a second flying capacitor Cfly2. The hybrid converter111provides regulation using at least one inductor and at least one switched capacitor, and thus is a hybrid converter.

As shown inFIG.2A, the hybrid converter111receives an input voltage VINfrom an input terminal and provides an output voltage VOto an output terminal that is connected to an output capacitor COUT. Although not shown inFIG.2A, the output terminal of the hybrid converter111can be coupled to any desired load. The hybrid converter111operates with a duty cycle d that changes in relation to a ratio of 2VO/VIN, in this embodiment.

As shown inFIG.2A, the first power transistor Q1and the second power transistor Q2are connected in series between the input voltage VINand a middle node MID, while the first flying capacitor Cfly1is connected between a source of the first power transistor Q1and a first switch node SW1. The fourth power transistor Q4is connected between the first switch node SW1and ground, while the first inductor L1is connected between the first switch node SW1and the output voltage VO. The fifth power transistor Q5and the sixth power transistor Q6are connected in series between the input voltage VINand the middle node MID, while the second flying capacitor Cfly5is connected between a source of the fifth power transistor Q5and a second switch node SW2. The eighth power transistor Q8is connected between the second switch node SW2and ground, while the second inductor L2is connected between the second switch node SW2and the output voltage VO. The third power transistor Q3is connected between the first switch node SW1and the middle node MID, while the seventh power transistor Q7is connected between the second switch node SW2and the middle node MID.

In comparison to the buck converter10ofFIG.1A, the hybrid converter111ofFIG.2Aoperates with reduced switching loss of the power transistors, thereby allowing operation at higher frequency. Moreover, the hybrid converter111operates with high efficiency, even when VOis a large step down voltage from VIN(for instance, when stepping down with a ratio of 4:1 or more, for instance, from 48V to 12V).

As shown inFIGS.2A-2D, the first through eighth power transistors Q1-Q8are controlled by control signals A, A′, B, B′, C and D, where A′ is complimentary signal of A and B′ is complimentary signal of B. Since this example implements the power transistors using n-type field-effect transistors (NFETs), when a given control signal is high, the corresponding power transistor is on. However, implementations using p-type transistors, n-type and p-type transistors, and/or other types of switches are also possible. As shown in the example ofFIG.2B, D is generated by (B AND A′) using a first AND gate, while C is generated by (A AND B′) using a second AND gate.

When operating in the steady state and when the hybrid converter111is stable, the flying capacitors hold a DC voltage equal to about ½ of VIN.

FIG.3Ais a schematic diagram of a first operating phase of the hybrid converter111ofFIG.2Afor low duty cycle regulation according to one embodiment.

As shown inFIG.3A, power transistors Q2, Q4, Q5, and Q7are turned on, while the remaining power transistors are turned off. Thus, the second flying capacitor Cfly2and the first flying capacitor Cfly1are connected in series between the input voltage VINand ground. Additionally, the current through inductor L1ramps down while the current through inductor L2ramps up.

FIG.3Bis a schematic diagram of a second and fourth operating phase of the hybrid converter111ofFIG.2Afor low duty cycle regulation according to one embodiment.

As shown inFIG.3B, the power transistors Q4and Q8are turned on, while the remaining power transistors are turned off. Thus, the current through inductor L1and the current through inductor L2both ramp down.

FIG.3Cis a schematic diagram of a third operating phase of the hybrid converter111ofFIG.2Afor low duty cycle regulation according to one embodiment.

As shown inFIG.3C, power transistors Q1, Q3, Q6, and Q8are turned on, while the remaining power transistors are turned off. Thus, the first flying capacitor Cfly1and the second flying capacitor Cfly2are connected in series between the input voltage VINand ground. Additionally, the current through inductor L1ramps up while the current through inductor L2ramps down.

With reference toFIGS.3A-3C, the hybrid converter111can provide regulation by cycling the hybrid converter111through the first operating phase (FIG.3A), the second operating phase (FIG.3B), the third operating phase (FIG.3C), and the fourth operating phase (FIG.3B). Additionally, the regulation cycle can be repeated by returning to the first operating phase (FIG.3A) from the fourth operating phase (FIG.3B). Such operation can correspond to low duty cycle (d) operation, for instance, d less than fifty percent.

FIG.4Ais a schematic diagram of a first operating phase of the hybrid converter111ofFIG.2Afor high duty cycle regulation according to one embodiment.

As shown inFIG.4A, power transistors Q2, Q4, Q5, and Q7are turned on, while the remaining power transistors are turned off. Thus, the second flying capacitor Cfly2and the first flying capacitor Cfly1are connected in series between the input voltage VINand ground. Additionally, the current through inductor L1ramps down while the current through inductor L2ramps up.

FIG.4Bis a schematic diagram of a second and fourth operating phase of the hybrid converter111ofFIG.2Afor high duty cycle regulation according to one embodiment.

As shown inFIG.4B, the power transistors Q1, Q3, Q5, and Q7are turned on, while the remaining power transistors are turned off. Thus, the current through inductor L1and the current through inductor L2both ramp up. Furthermore, a path through power transistors is Q3and Q7is provided to connect the second end of the first flying capacitor Cfly1to the second end of the second flying capacitor Cfly2.

FIG.4Cis a schematic diagram of a third operating phase of the hybrid converter111ofFIG.2Afor high duty cycle regulation according to one embodiment.

As shown inFIG.4C, power transistors Q1, Q3, Q6, and Q8are turned on, while the remaining power transistors are turned off. Thus, the first flying capacitor Cfly1and the second flying capacitor Cfly2are connected in series between the input voltage VINand ground. Additionally, the current through inductor L1ramps up while the current through inductor L2ramps down.

With reference toFIGS.4A-4C, the hybrid converter111can provide by regulation by cycling the hybrid converter111through the first operating phase (FIG.4A), the second operating phase (FIG.4B), the third operating phase (FIG.4C), and the fourth operating phase (FIG.4B). Additionally, the regulation cycle can be repeated by returning to the first operating phase (FIG.4A) from the fourth operating phase (FIG.4B). Such operation can correspond to high duty cycle (d) operation, for instance, d greater than or equal to fifty percent.

FIG.5is a schematic diagram of a hybrid power conversion system110according to one embodiment. The hybrid power conversion system110includes a hybrid converter111and a PWM controller102. As shown inFIG.5, the output voltage VOof the hybrid converter111is provided to a load and also sensed by the PWM controller102to aid in generating control signals for the hybrid converter's power transistors.

In the illustrated embodiment, the PWM controller102includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, an error amplifier EA, a first comparator PWMCMP1, and a second comparator PWMCMP2.

The PWM controller102provides closed loop feedback to the hybrid converter111. For example, the first resistor R1and the second resistor R2serve as a voltage divider to generate a feedback voltage FB based on dividing down the output voltage VO. The error amplifier EA amplifies the error between the feedback voltage FB and a DC reference voltage REF to generate a comparison threshold signal COMP.

The first comparator PWMCMP1generates a first PWM control signal A based on comparing the comparison threshold signal COMP to a first sawtooth ramp signal RAMP1, while the second comparator PWMCMP2generates a second PWM control signal B based on comparing the comparison threshold signal COMP to a second sawtooth ramp signal RAMP2. A third PWM control signal C and a fourth PWM control signal D can be generated using the configuration ofFIG.2B, while inverters can be used to generate logically inverted versions of any of the PWM control signals.

With continuing reference toFIG.5, the first and second sawtooth ramp signals RAMP1and RAMP2can be generated in a wide variety of ways, and can have a phase difference of about 180 degrees and correspond to a sensed amount of current flowing through the first inductor L1and the second inductor L2, respectively.

When the feedback voltage FB is lower than the DC reference voltage REF, the comparison threshold signal COMP goes up and the duty cycle d increases. In contrast, when the feedback voltage FB is higher than the DC reference voltage RF, the comparison threshold signal COMP goes down and the duty cycle d decreases. Accordingly, regulation of the output voltage VOis provided. To provide stability compensation, the PWM controller102includes the third resistor R3, the fourth resistor R4, the first capacitor C1, the second capacitor C2, and the third capacitor C3.

FIG.6Ais one example of a transient performance simulation without power stage mismatch for the hybrid power conversion system110ofFIG.5.FIG.6Bis an expanded portion of the transient performance simulation ofFIG.6A.

The simulation observes the transient response of the hybrid converter111under a load current step change (current step in ILOAD) in which the capacitances of the first flying capacitor Cfly1and the second flying capacitor Cfly2are equal and in which the inductances of the first inductor L1and the second inductor L2are equal, and the comparators in PWM controller102have the same delay and input offset.

As shown inFIGS.6A and6B, the output voltage VOsettles down after a brief and momentary deviation and returns to voltage regulation without oscillation. Thus, the stability compensation is properly operating under the simulated conditions.

FIG.7Ais one example of a transient performance simulation with power stage mismatch for the hybrid power conversion system110ofFIG.5.FIG.7Bis an expanded portion of the transient performance simulation ofFIG.7A.

In reality, the hardware circuit components of a hybrid converter are never exactly identical. Thus, the first half power stage P1and the second half power stage P2of the hybrid converter111ofFIGS.2A and5can suffer from a number of mismatches including, but not limited to, imbalance in comparator delays, differences in the capacitances of the first flying capacitor Cfly1and the second flying capacitor Cfly2, and/or differences in the inductances of the first inductor L1and the second inductor L2.

The simulations ofFIGS.7A and7Bare identical to the simulations ofFIGS.6A and6B, except that the inductance of the first inductor L1is less than the inductance of the second inductor L2in the simulations ofFIGS.7A and7B.

As shown inFIGS.7A and7B, the inductor mismatch results in the voltages across the first flying capacitor Cfly1and the second flying capacitor Cfly2of the hybrid converter111running away and the currents through the first inductor L1and the second inductor L2being non-equal. This in turn can cause excessive power loss on the hybrid converter111, give rise to reliability problems, and/or lead to immediate circuit damage (for instance, circuit blow up) due to electrical overstress on capacitors and/or power transistors.

PWM controllers for hybrid converters are provided herein. In certain embodiments, a PWM controller for a hybrid converter includes a threshold generation circuit for generating a threshold signal based on an output voltage of the hybrid converter, a threshold adjustment circuit for generating an adjusted threshold signal based on sensing a voltage of a flying capacitor of the hybrid converter, and a comparator that generates a comparison signal based on comparing the adjusted threshold signal to an indication of an inductor current of the hybrid converter. The output of the comparator is used for generating PWM control signals used for turning on and off the switches (for instance, power transistors) of the hybrid converter.

By implementing the PWM controller in this manner, stable operation of the hybrid converter is achieved even when power stage mismatches are present and/or the PWM controller has asymmetries in circuitry used for generating the PWM controls signals of the hybrid converter's power stage(s).

FIG.8is a schematic diagram of a hybrid power conversion system120according to another embodiment. The hybrid power conversion system120includes a hybrid converter111and a PWM controller112.

In the illustrated embodiment, the PWM controller112includes a threshold generation circuit113, a threshold adjustment circuit114, a first comparator115, a second comparator116, and a switch control circuit117.

The threshold generation circuit113generates a threshold signal THRESH based on the output voltage VO. The threshold signal THRESH can be generated in a wide variety of ways including, but not limited to, using an error amplifier that compares a fraction of the output voltage VOto a reference signal. The threshold signal THRESH is provided to the first comparator115and the second comparator116, in this example.

As shown inFIG.8, the PWM controller112includes the threshold adjustment circuit114for adjusting the comparison threshold of the first comparator115based on the first flying capacitor voltage VCfly1and the input voltage VIN. Such adjustment can be based on a comparison of the first flying capacitor voltage VCfly1to a fraction of the input voltage VIN.

Although an example with adjustment of the threshold of the first comparator114is shown, the teachings herein are also applicable to configurations in which the threshold of the second comparator116is adjusted as well as to configurations in which both the threshold of the first comparator115and the second comparator116are separately adjusted. For example, the adjusted threshold of the second comparator116can be based on a comparison of the second flying capacitor voltage VCfly2to a fraction of the input voltage VIN.

The first comparator115compares the adjusted threshold to the sensed current through the first inductor L1. Additionally, the second comparator116compares the threshold signal THRESH to the sensed current through the second inductor L2.

The current through the first inductor L1and the current through the second inductor L2can be sensed in any suitable way. In a first example, a small resistor is included in series with an inductor, and the detected voltage across the small resistor is used to sense the current through the inductor. In a second example, DC resistance (DCR) sensing of an inductor is used to sense the current through the inductor. DCR sensing can include connecting a resistor-capacitor (RC) network in parallel to the inductor, and sizing the product of the resistance and capacitance values of the RC network to be about equal to the ratio of the inductor's inductance to the inductor's parasitic resistance. When configured in this manner, a voltage across the capacitor of the RC network is proportional to the current through the inductor.

Although two examples of inductor current sensing have been provided, any suitable technique for measuring inductor current can be used.

The switch control circuit117generates various controls signals (A, A′, B, B′, C, and D, in this example) for turning on or off the power transistors of the hybrid converter111. The pulse widths of the control signals are controlled based on results of the comparisons generated from the first comparator115and the second comparator116.

By implementing the PWM controller112with threshold adjustment, compensation for asymmetries between the first half power stage and the second half power stage is provided. Such asymmetry can include mismatch between CFly1/Cfly2, mismatch between L1/L2, and/or mismatch in delays of the first comparator115and the second comparator116.

In certain embodiments herein, a PWM controller (for instance, the PWM controller112ofFIG.8) is implemented on a semiconductor die. Additionally, a hybrid converter (for instance, the hybrid converter111ofFIG.8) may be implemented in part using off-chip components, such as discrete power transistors for enhanced power handling and/or heat dissipation capabilities.

FIG.9is a schematic diagram of a hybrid power conversion system150according to another embodiment. The hybrid power conversion system150includes a hybrid converter121and a PWM controller122.

The hybrid converter121ofFIG.9is similar to the hybrid converter111ofFIG.2A, except that the hybrid converter121further includes a first current sensing circuit123for sensing the current through the first inductor L1and a second current sensing circuit124for sensing the current through inductor L2. The first current sensing circuit123and the second current sensing current124can provide current sensing in a wide variety of ways, including, but not limited to, DCR sensing and/or by sensing a voltage across a series resistor.

In the illustrated embodiment, the PWM controller122includes a first resistor R1, a second resistor R2, an error amplifier EA, a first half-range limiter125, a second half-range limiter126, a first controlled voltage source127, a second controlled voltage source128, an amplifier stability network129, a first comparator CMP1, a second comparator CMP2, a first set/reset (S/R) latch RS1, a second S/R latch RS2, a top voltage divider resistor R5, a bottom voltage divider resistor R6, a first sampling switch131, a second sampling switch132, a first sampling capacitor C1, a second sampling capacitor C2, a first gain circuit GAIN1, and a second gain circuit GAIN2. Although one embodiment of a PWM controller122implemented is depicted, the teachings herein are applicable to PWM controllers implemented in a wide variety of ways. Accordingly, other implementations are possible.

As shown inFIG.9, the top voltage divider resistor R5and the bottom voltage divider resistor R6are connected as a resistor divider that generates a voltage signal HALFVIN that is about equal to about half the input voltage VIN. Thus, R5and R6can have nominally equal resistance values.

In the illustrated embodiment, the first sampling switch131and the second sampling switch132are connected between the middle node MID and the first sampling capacitor C1and the second sampling capacitor C2, respectively.

When the power transistor Q2is turned on by the control signal C (as shown inFIGS.2C and2Dthe power transistor Q4is also turned on by A′ when C is active), the first sampling switch131is also turned on to store the voltage of the first flying capacitor Cfly1on the first sampling capacitor C1. Additionally, the difference between the sampled voltage of the first sampling capacitor C1and the voltage signal HALFVIN is amplified by the first gain circuit GAIN1. The first half limiter125serves to limit the output of the first gain circuit GAIN1. In particular, when the output of the first gain circuit GAIN1is negative, the output of the first half limiter125is zero. However, when the output of the first gain circuit GAIN1is positive, the output of the first half limiter125tracks the input of the first half limiter125until reaching the maximum allowed output value. The output of the first half limiter125controls a first controlled voltage source127to adjust the threshold ITH generated by the error amplifier EA. Thus, the first controlled voltage source127generates a first adjusted threshold ITH1equal to about ITH minus a first adjustment voltage set by the first half limiter125.

Symmetrically, when the power transistor Q6is turned on by the control signal D (as shown inFIGS.2C and2Dthe power transistor Q8is also turned on by B′ when D is active), the second sampling switch132is also turned on to store the voltage of the second flying capacitor Cfly2on the second sampling capacitor C2. Additionally, the difference between the sampled voltage of the second sampling capacitor C2and the voltage signal HALFVIN is amplified by the second gain circuit GAIN2. The second half limiter126serves to limit the output of the second gain circuit GAIN2by outputting zero when the output of the second gain circuit GAIN2is negative and by tracking the output of the second gain circuit GAIN2up to a maximum allowed output value when the output of the second gain circuit GAIN2is positive. The second controlled voltage source128generates a second adjusted threshold ITH2equal to about ITH minus a second adjustment voltage set by the second half limiter126.

With continuing reference toFIG.9, the output voltage VOis divided down to generate a feedback signal FB using a resistor divider formed by the first resistor R1and the second resistor R2. The feedback signal FB couples to the inverting input of the error amplifier EA, which can be implemented as a transconductance amplifier. A reference DC voltage REF is coupled to the non-inverting input of the error amplifier EA, and the error between FB and REF is converted as a current output used to set the threshold ITH. The amplifier stability network129can be implemented in a wide variety of ways, such as using a resistor-capacitor (RC) compensation network for providing stability compensation.

The first comparator CMP1compares an indication of the current of the first inductor L1(provided by the first current sensing circuit123) to the first adjusted threshold ITH1, while the second comparator CMP2compares an indication of the current of the second inductor L2(provided by the second current sensing circuit124) to the second adjusted threshold ITH2.

The first SR latch RS1outputs a first PWM control signal A that is set when the first clock signal CLK1is applied. When the first sensed inductor current signal is higher than ITH1, the output of the first comparator CMP1resets the first PWM control signal A, which is the control signal of the first power transistor Q1and the third power transistor Q3. Furthermore, the first PWM control signal A can be logically inverted to control the fourth power transistor Q4.

With continuing reference toFIG.9, the second SR latch RS2outputs a second PWM control signal B that is set when the second clock signal CLK2is applied. In certain implementations, the second clock signal CLK2has about a 180 degree phase shift with the first clock signal CLK1. When the second sensed inductor current signal is higher than ITH2, the output of the second comparator CMP2resets the second PWM control signal B, which is the control signal of the fifth power transistor Q5and the seventh power transistor Q7. Furthermore, the second PWM control signal B can be logically inverted to control the eighth power transistor Q8. Moreover, digital logic operations (see for example, the configurationFIG.2B) can be used to generate a third PWM control signal C for controlling the second power transistor Q2and a fourth PWM control signal D for controlling the sixth power transistor Q6.

FIG.10Ais one example of a transient performance simulation with flying capacitor mismatch for the hybrid power conversion system150ofFIG.9.

The simulation results are depicted for a simulation in which CFLY1≠CFLY2. As shown inFIG.10A, the flying capacitor voltages are both well locked at ½VIN, and inductor currents are also closely matched, even when the dynamic load is applied to the output of the hybrid converter121.

FIG.10Bis one example of a transient performance simulation with comparator mismatch for the hybrid power conversion system150ofFIG.9.

The simulation results are depicted for a simulation in which the current comparators have mismatched input offset. As shown in theFIG.10B, the PWM controller122serves to adjust ITH1and ITH2to ensure that Vcfly1=Vcfly2=½VIN, and that iL1=iL2.

FIG.11is one example of a transient performance simulation with inductor mismatch for the hybrid power conversion system150ofFIG.9.

The simulation results are depicted for a simulation in which L1≠L2. As shown inFIG.11, the flying capacitor voltages are both well locked at ½VIN, and inductor currents are also closely matched, even when the dynamic load is applied.

FIG.12is a schematic diagram of a hybrid power conversion system160according to another embodiment. The hybrid power conversion system160includes a hybrid converter121and a PWM controller152.

The PWM controller152ofFIG.12is similar to the PWM controller122ofFIG.9, except that the embodiment ofFIG.12illustrates a different implementation of the first sampling switch131and the second sampling switch132. In particular, the first sampling switch131is directly connected between a first end of the first flying capacitor Cfly1and the first sampling capacitor C1and controlled by control signal A′, while the second sampling switch132is directly connected between a first end of the second flying capacitor Cfly2and the second sampling capacitor C2and controlled by control signal B′. Implementing the PWM controller152ofFIG.12in this manner provides longer sampling time (see for example, the timing diagrams ofFIGS.2C and2D) relative to the PWM controller122ofFIG.9.

FIG.13is a schematic diagram of a hybrid power conversion system170according to another embodiment. The hybrid power conversion system170includes a hybrid converter121and a PWM controller162.

The PWM controller162ofFIG.13is similar to the PWM controller122ofFIG.9, except that the PWM controller162ofFIG.13omits the sampling switches131and132and the sampling capacitors C1and C2in favor of including a first differential amplifier DIFF1and a second differential amplifier DIFF2. As shown inFIG.13, the first differential amplifier DIFF1has a differential input coupled across the first flying capacitor Cfly1and an output coupled to a non-inverting input of the first gain circuit GAIN1. Additionally, the second differential amplifier DIFF2has a differential input coupled across the second flying capacitor Cfly2and an output coupled to a non-inverting input of the second gain circuit GAIN2. The first gain circuit GAIN1and the second gain circuit GAIN2each include an inverting input that receives HALFVIN.

By implementing the PWM controller162in this manner, enhanced tracking of the flying capacitor voltages is achieved at the expense of an increase in complexity. For example, the first differential amplifier DIFF1and the second differential amplifier DIFF2provide a continuous indication of the voltages across the first flying capacitor Cfly1and the second flying capacitor Cfly2, respectively, but operate with a wide input voltage range.

FIG.14is a schematic diagram of a hybrid power conversion system180according to another embodiment. The hybrid power conversion system180includes a hybrid converter121and a PWM controller172.

The PWM controller172ofFIG.14is similar to the PWM controller162ofFIG.13, except that the PWM controller172omits the second differential amplifier DIFF2, the second gain circuit GAIN2, the second half limiter126, and the second controlled voltage source128. Furthermore, the PWM controller172omits the first half limiter125in favor of including a full limiter173.

By using the full limiter173to control the first controlled voltage source127, adjustment of the threshold voltage ITH1is provided to maintain the voltage across the first flying capacitor Cfly1about equal to ½VIN.

FIG.15is a schematic diagram of a hybrid power conversion system190according to another embodiment. The hybrid power conversion system190includes a hybrid converter121and a PWM controller182.

The PWM controller182ofFIG.15is similar to the PWM controller172ofFIG.14, except that the PWM controller182omits resistors R5and R6in favor of including the second differential amplifier DIFF2. As shown inFIG.15, the first gain circuit GAIN1compares an output of the first differential amplifier DIFF1to an output of the second differential amplifier DIFF2.

FIG.16is a schematic diagram of a hybrid power conversion system200according to another embodiment. The hybrid power conversion system200includes a hybrid converter121and a PWM controller192.

The PWM controller192ofFIG.16is similar to the PWM controller162ofFIG.13, except that the PWM controller192is implemented such that the first half limiter125controls the second controlled voltage source128and the second half limiter126controls the first controlled voltage source127.

FIG.17is a schematic diagram of a hybrid power conversion system310according to another embodiment. The hybrid power conversion system310includes a hybrid converter300, a first PWM controller301, a second PWM controller302, a first resistor R1, and a second resistor R2. The PWM controllers ofFIG.17can be implemented in accordance with any of the embodiments herein.

In the illustrated embodiment, the hybrid converter300includes a first half power stage P1and a second half power stage P2, which are implemented in a manner similar to that of the hybrid converter111ofFIG.2A. The first half power stage P1and the second half power stage P2form a first power stage. Nodes SW1, SW2, and MID1and a first output capacitor COUT1are also present for these half stages. The first PWM controller301generates PWM control signals A, A′, B, B′, C, and D for the first half power stage P1and the second half power stage P2. Although not shown inFIG.17, current sensing circuits for the first inductor L1and the second inductor L2can also be included.

The hybrid converter310further includes a third half power stage P3and a fourth half power stage P4. The third half power stage P3and the fourth power stage P4form a second power stage, and thus the hybrid converter310is implemented using two stages, in this embodiment.

The third half power stage P3includes a ninth power transistor Q9, a tenth power transistor Q10, an eleventh power transistor Q11, a twelfth power transistor Q12, a third inductor L3, and a third flying capacitor Cfly3. Additionally, the fourth half power stage P4includes a thirteenth power transistor Q13, a fourteenth power transistor Q14, a fifteenth power transistor Q15, a sixteenth power transistor Q16, a fourth inductor L4, and a fourth flying capacitor Cfly4. Nodes SW3, SW4, and MID2and a second output capacitor COUT2are also present for these half stages. The second PWM controller302generates PWM control signals E, E′, F, F′, G, and H for the third half power stage P3and the fourth half power stage P4. Although not shown inFIG.17, current sensing circuits for the third inductor L3and the fourth inductor L4can also be included. All four half power stages P1-P4operate with a shared VINand a shared VO, in this embodiment.

The teachings herein are applicable to hybrid converters including not only two power stages (for instance, two power stages in the embodiment ofFIG.17), but also other number of power stages.

The first PWM controller301and the second PWM controller302operate with a common ITH (prior to adjustment by threshold adjustment circuits), a shared soft start (SS) signal, and a shared feedback signal FB generated by the output voltage divider formed by resistors R1and R2. The first PWM controller301also provides a clock signal from an output CLKOUT to an input CLKIN of the second PWM controller302to aid in coordinating timing of PWM signals and to match regulator switching frequency. The SS signal can be used to provide soft-start. For instance, a current source can be included in each PWM controller, and can connect to an off-chip capacitor to allow the SS signal voltage to ramp up smoothly. Furthermore, a voltage regulation loop regulates the feedback FB to SS or an internal reference REF, whichever is lower, so that output voltage ramps up linearly. Although one example of soft-start is described, other implementations are possible. Any of the embodiments herein can operate with soft start.

FIG.18is one example of a transient performance simulation with inductor mismatch, flying capacitor mismatch, comparator mismatch, and current sensing gain mismatch for the hybrid power conversion system310ofFIG.17.

As shown inFIG.18, the hybrid power conversion system310provides stable regulation in the presence of a load current step.

FIG.19Ais a schematic diagram of a hybrid power conversion system420according to another embodiment. The hybrid power conversion system420includes a hybrid converter411and a PWM controller112.

The hybrid power conversion system420ofFIG.19Ais similar to the hybrid power conversion system420ofFIG.8, except that the hybrid power conversion system420illustrates a different implementation of a hybrid converter. In particular, in comparison to the hybrid converter111shown inFIG.8, the hybrid converter411ofFIG.19Afurther includes a capacitor COPTconnected between the middle node MID and ground.

The PWM control schemes herein are applicable to hybrid converters implemented in a wide variety of ways.

FIG.19Bis a schematic diagram of a hybrid power conversion system430according to another embodiment. The hybrid power conversion system430includes a hybrid converter421and a PWM controller112.

In comparison to the hybrid converter111ofFIG.8, the hybrid converter421ofFIG.19Bincludes a first conductor MID1connecting the source of power transistor Q2and the drain of power transistor Q7, and a second conductor MID2connecting the source of power transistor Q6and the drain of power transistor Q3. Implementing the hybrid converter421in this manner enhances converter balancing between half stages.

FIG.19Cis a schematic diagram of a hybrid power conversion system440according to another embodiment. The hybrid power conversion system440includes a hybrid converter431and a PWM controller112.

In comparison to the hybrid converter421ofFIG.19B, the hybrid converter431ofFIG.19Cincludes a first capacitor COPT1connected between MID1and ground, and a second capacitor COPT2connected between MID2and ground.

Applications

Devices employing the above described schemes can be implemented into various electronic devices in a wide range of applications including, but not limited to, bus converters, high current distributed power systems, telecom systems, datacom systems, storage systems, and automotive systems. Thus, examples of electronic devices that can be implemented with the hybrid power conversion systems herein include, but are not limited to, communication systems, consumer electronic products, electronic test equipment, communication infrastructure, servers, automobiles, etc.

Conclusion

Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.