Semiconductor device and programming method therefor

In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a National Stage of International Application No. PCT/JP2017/032606, filed Sep. 11, 2017, claiming priority based on Japanese Patent Application No. 2016-178734, filed Sep. 13, 2016, the contents of all of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to a semiconductor device and programming method therefor. Particularly, the present invention relates to a semiconductor device equipped with a variable-resistance nonvolatile element and a programming method therefor.

BACKGROUND ART

With the miniaturization of the semiconductor integrated circuits, an integration degree of field effect transistors has risen at a pace of quadrupling in three years, thus allowing costs for photomask and design verification necessary for manufacturing integrated circuits to grow. As a result, a development cost of an application specific integrated circuit (ASIC) in which a user designs a fixed function in a custom-design manner in advance is rapidly increasing. In such a situation, a semiconductor device with which a designer can electrically program a desired circuit on a manufactured semiconductor chip, such as a field programmable gate array (FPGA), is drawing attention.

Incidentally, an FPGA has a problem that area efficiency is low and power consumption is large because the FPGA needs ten times or more of transistors compared with an ASIC in order to achieve the same function. In order to solve such a problem, research and development aiming to reduce an overhead of an FPGA and to reduce power consumption is being conducted. One of solutions to the above-described problem is to achieve a programmable wiring mounted with a variable resistance element (also called variable-resistance nonvolatile element) inside a multilayer wiring layer. The variable resistance elements include a resistance random access memory (ReRAM) using transition metal dioxide, a Nano Bridge (registered trademark) using an ion conductor, and the like.

PTL 1 discloses a variable resistance element using a solid ion conductor. The variable resistance element of PTL 1 includes an ion conductive layer, and a first electrode and a second electrode that are arranged adjacently to a counter surface of the ion conductive layer. The first electrode of the variable resistance element of PTL 1 is configured with a metal that can be ionized more easily than the second electrode, and the ion conductive layer is constituted of an electrolyte material including a metal ion of metal configuring the first electrode. In the variable resistance element of PTL 1, a resistance value of the ion conductor is adjusted by changing a polarity of applied voltage, thereby controlling a conductive state between the two electrodes.

An example inFIG. 14is a crossbar circuit100in which a variable resistance element110of PTL 1 is arranged at an intersection point of buses in a crossbar. The crossbar circuit100ofFIG. 14includes a configuration in which variable resistance elements110are arranged at intersection points of a plurality of first wirings121to126and a plurality of second wirings131to136. InFIG. 14, an element in an on-state is illustrated with a black square, and an element in an off-state is illustrated with a white square. The crossbar circuit100ofFIG. 14illustrates a wiring as a crossbar realized by putting variable resistance elements110on a diagonal line into the on-state.

PTL 2 discloses a crossbar switch using a variable resistance element as an ultra-large scale integration (ULSI). In the crossbar switch in PTL 2, it is disclosed that a variable resistance element is connected in series and used as a unit element.

An example inFIG. 17is a crossbar circuit200in which a unit element210of PTL 2 is arranged at an intersection point of buses of a crossbar. The crossbar circuit200ofFIG. 17has a configuration in which unit elements210are arranged at intersection points of a plurality of first wirings221to226and a plurality of second wirings231to236. InFIG. 17, an element in an on-state is illustrated with a black square, and an element in an off-state is illustrated with a white square. In the crossbar circuit200ofFIG. 17, the unit element210is turned to the on-state by putting both of two variable resistance elements constituting the unit element210into the on-state, and the unit element210is turned to the off-state by putting both of the two variable resistance elements into the off-state. The crossbar circuit200ofFIG. 17illustrates a wiring as a crossbar realized by putting the unit elements210on a diagonal line into the on-state.

PTL 3 discloses a nonvolatile resistance network aggregate including two resistance networks in which a plurality of nonvolatile resistance elements are connected. The nonvolatile resistance network aggregate of PTL 3 performs writing in such a way that combined resistance values of the two resistor networks are different by using write means for writing into the two resistor networks.

PTL 4 discloses a content addressable memory cell using a variable-resistance nonvolatile storage element. The content addressable memory cell of PTL 4 includes a logical circuit that selects a current path in response to input data and a variable-resistance nonvolatile storage element that stores storage data, and includes a resistance network that changes a resistance value in response to a result of logical operation of input data and storage data. In addition, the content addressable memory cell of PTL 4 includes a charging/discharging circuit that changes delay time until outputting a signal input from a match line in response to the result of logical operation of input data and storage data.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

The crossbar circuit using the variable resistance element of PTL 1 has following problems.

FIG. 15illustrates a state in which 1 bit of open failure occurs on a variable resistance element110arranged at an intersection point of a first wiring123and a second wiring133in the crossbar circuit100ofFIG. 14. When the open failure as illustrated inFIG. 15occurs, an input from the first wiring123is not transferred as an output of the second wiring133.

FIG. 16illustrates a state in which 1 bit of short circuit occurs on a variable resistance element110arranged at an intersection point of a first wiring125and a second wiring133in the crossbar circuit100ofFIG. 14. When the short circuit as illustrated inFIG. 16occurs, an input from the first wiring123and an input from the first wiring125collides, and an output from the second wiring133and an output from the second wiring135become uncertain.

In addition, the crossbar circuit using the variable resistance element of PTL 2 has following problems.

FIG. 18illustrates a state in which 1 bit of open failure occurs on a unit element210arranged at an intersection point of a first wiring223and a second wiring233in the crossbar circuit200ofFIG. 17. Occurrence of the open failure as illustrated inFIG. 18leads to a malfunction of the circuit.FIG. 19illustrates a state in which 1 bit of short circuit occurs on a unit element210arranged at an intersection point of a first wiring225and the second wiring233in the crossbar circuit200ofFIG. 17. Occurrence of the short circuit as illustrated inFIG. 19does not affect a circuit operation of the crossbar circuit200.

In other words, the crossbar circuits of PTLs 1 and 2 arranged with variable resistance elements have a problem that a failure of 1 bit may prevent the circuit from operating.

In addition, although techniques for preventing an error are disclosed in PTL 3 and PTL 4, a technique for recovering from an error is not disclosed.

An objective of the present invention is to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element in order to solve any of the above-mentioned problems.

Solution to Problem

A semiconductor device according to an aspect of the present invention includes a first wiring being extended to a first direction, a second wiring being extended to a second direction that crosses the first direction, a unit element group having a configuration in which at least two unit elements are arranged in parallel, the unit element including at least two variable-resistance two-terminal elements being connected in series, the unit element group being connected to the first wiring and the second wiring, a first programming driver that changes a resistive state of a two-terminal element constituting the unit element group via the first wiring, a first selection transistor in which one of a source terminal and a drain terminal is connected to the first wiring and the other terminal is connected to the first programming driver, a second programming driver that changes a resistive state of a two-terminal element constituting the unit element group via the second wiring, and a second selection transistor in which one of a source terminal and a drain terminal is connected to the second wiring and the other terminal is connected to the second programming driver.

In a programming method according to an aspect of the present invention, a programming is performed on a crossbar circuit including a first wiring being extended to a first direction, a second wiring being extended to a second direction that crosses the first direction, a third wiring being paired with the first wiring and extended to the first direction, and at least two unit element groups in each of which at least two unit elements are arranged in parallel, the unit element including at least two variable-resistance two-terminal elements being connected in series via an intermediate node, the unit element group being arranged between the first wiring and the second wiring and between the third wiring and the second wiring, by changing a resistive state of a two-terminal element of a unit element being a target of programming by applying a voltage that exceeds a reference value between at least one of the first wiring, the second wiring, and the third wiring, and the intermediate node.

Advantageous Effects of Invention

The present invention can provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element.

EXAMPLE EMBODIMENT

Hereinafter, with reference to the figures, the example embodiments of the present invention are described in detail. Although the example embodiments are described with a technically preferable limitation, the example embodiments are not intended to limit the scope of the invention. In all figures used for the description of the example embodiments, like reference numerals are assigned to the similar parts unless there is a particular reason. In addition, in the example embodiments, a repeated description about a similar configuration and an operation may be omitted.

First Example Embodiment

With reference to the figures, the semiconductor device according to the first example embodiment of the present invention is described.FIG. 1is a conceptual diagram illustrating a configuration of a semiconductor device1according to the example embodiment.FIG. 2is a conceptual diagram illustrating a unit element group10included in the semiconductor device1ofFIG. 1.

As illustrated inFIG. 1, the semiconductor device1includes a unit element group10that includes a first unit element11and a second unit element12, a first wiring21and a second wiring22. The semiconductor device1also includes an intermediate node selection transistor30, a first selection transistor35, and a second selection transistor36. The semiconductor device1further includes a first programming driver41, a second programming driver42and an intermediate node programming driver45. The semiconductor device1also includes an intermediate node program line33, a first decode signal line51and a second decode signal line52.

The semiconductor device1is a crossbar circuit having a configuration in which a plurality of unit element groups10that are arranged in an array are connected to the first wiring21and the second wiring22. The first wiring21is extended to a first direction. The second wiring22is extended to a second direction that crosses the first direction.

The array configuration of the semiconductor device1is configured by two groups. A first group is a group that includes the first wiring21, the first selection transistor35and the first decode signal line51. A second group is a group that includes the second wiring22, the second selection transistor36, the second decode signal line52, the intermediate node program line33and the intermediate node common selection transistor34. The semiconductor device1may include at least one first group and one second group. However, in the following example, the semiconductor device1includes a plurality of first groups and second groups.

The semiconductor device1has a configuration in which a unit element group10is arranged at a position where the first wiring21and the second wiring22cross when a plurality of first wirings21and a plurality of second wirings22are arranged in such a way as to cross in planar view. In the example ofFIG. 1, the first wiring21and the second wiring22are configured in such a way as to cross at right angles in planar view. InFIG. 1, only a part of the semiconductor device1is illustrated, and similar configurations are omitted.

The unit element group10has a configuration in which at least two variable-resistance two-terminal elements (hereinafter referred to as variable resistance elements) are connected in series via an intermediate node15. The variable resistance element is also referred to as a variable-resistance nonvolatile element.

The unit element group10has a configuration in which the first unit element11and the second unit element12are connected in parallel. The unit element group10is arranged at an intersection point of a crossbar configured by the first wiring21and the second wiring22. According to the design of the crossbar circuit, the unit element group10may not be arranged at all of the intersection points of the crossbar, and an intersection point at which a unit element group10is not arranged may exist.

As illustrated inFIG. 2, the first unit element11has a configuration in which a variable resistance element11-1and a variable resistance element11-2are connected in series. The variable resistance element11-1and the variable resistance element11-2are connected in series via an intermediate node16. Similarly, the second unit element12has a configuration in which a variable resistance element12-1and a variable resistance element12-2are connected in series. The variable resistance element12-1and the variable resistance element12-2are connected in series via an intermediate node17. The variable resistance elements11-1,11-2,12-1and12-2are variable-resistance two-terminal elements whose resistive state changes when an applied voltage exceeds a reference value.

One end of the first unit element11is connected to the first wiring21via a terminal18-1. Similarly, one end of the second unit element12is connected to the first wiring21via a terminal18-2. The other ends of the first unit element11and the second unit element12are connected to the second wiring22via a terminal19. Although not illustrated, the other ends of the first unit element11and the second unit element12may be connected to the second wiring22via separate terminals.

The intermediate node16and the intermediate node17illustrated inFIG. 2are connected to the intermediate node15illustrated inFIG. 1. As illustrated inFIG. 1, the intermediate node15is connected to the intermediate node program line33and the first decode signal line51via the intermediate node selection transistor30.

As illustrated inFIG. 1, the intermediate node selection transistor30is arranged for each unit element group10. One of a source terminal and a drain terminal of the intermediate node selection transistor30is connected to the intermediate node15, and the other terminal is connected to the intermediate node program line33. A gate terminal of the intermediate node selection transistor30is connected to the first decode signal line51.

The intermediate node program line33is connected to the intermediate node programming driver45via the intermediate node common selection transistor34.

One of a source terminal and a drain terminal of the intermediate node common selection transistor34is connected to the intermediate node program line33. The other of the source terminal and the drain terminal of the intermediate node common selection transistor34is connected to the intermediate node programming driver45. A gate terminal of the intermediate node common selection transistor34is connected to the second decode signal line52.

One of a source terminal and a drain terminal of the first selection transistor35is connected to the first wiring21. The other of the source terminal and the drain terminal of the first selection transistor35is connected to the first programming driver41. The gate terminal of the first selection transistor35is connected to the first decode signal line51that is common with the gate terminal of the intermediate node selection transistor30.

One of a source terminal and a drain terminal of the second selection transistor36is connected to the second wiring22. The other of the source terminal and the drain terminal of the second selection transistor36is connected to the second programming driver42. A gate terminal of the second selection transistor36is connected to the second decode signal line52that is common with the gate terminal of the intermediate node common selection transistor34.

The first programming driver41is connected to the first wiring21via the first selection transistor35. The first programming driver41changes the resistive state of the variable resistance element configuring the unit element group10via the first wiring21.

The second programming driver42is connected to the second wiring22via the second selection transistor36. The second programming driver42changes the resistive state of the variable resistance element configuring the unit element group10via the second wiring22.

The intermediate node programming driver45is connected to one of a source terminal and a drain terminal of the intermediate node common selection transistor34. The intermediate node programming driver45changes the resistive state of the variable resistance element configuring the unit element group10via the intermediate node program line33.

Here, the first programming driver41, the second programming driver42and the intermediate node programming driver45are described in detail.

FIG. 3is a conceptual diagram of the programming driver400that achieves the first programming driver41, the second programming driver42and the intermediate node programming driver45. The programming driver400changes the resistive state of a switch. The programming driver400provides a state in which a set voltage Vset, a reset voltage Vrst, an intermediate voltage Vmidand a ground voltage Gnd of the first unit element11and the second unit element12are provided, and a high impedance state.

Each power supply line of the set voltage Vset, reset voltage Vrst, intermediate voltage Vmidand ground voltage Gnd is connected to an external selection switching element via a constant current transistor401, output voltage selection transistor402and an output transistor403.

The constant current transistor401operates as a constant current source by controlling the gate voltage in the saturated region. The constant current transistor401controls the current in a constant value in response to the input signal from the current control terminal404.

Each output voltage selection transistor402is a transistor for selecting one of the set voltage Vset, reset voltage Vrst, intermediate voltage Vmidand ground voltage Gnd. Each output voltage selection transistor402is controlled by an input signal from the output voltage selection terminal405in such a way that one of the transistors is in an on-state and the other transistors are in an off-state.

The output transistor403puts the programming driver400into a voltage output state or the high impedance state. The output transistor403is controlled by an input signal from the enable terminal406.

Here, with reference to the figures, an example in which a failure occurs when operating the unit element group10included in the semiconductor device according to the first example embodiment of the present invention is described.FIG. 4toFIG. 7are conceptual diagrams for comparing the operation state of the unit element group10in the normal operation state and a state in which a failure occurs.

FIG. 4illustrates an example in which one end of the first unit element11and one end of the second unit element12are connected by a terminal18, and the other ends are connected by a terminal19. The unit element group10is connected to the first wiring21via the terminal18, and connected to the second wiring22via the terminal19. The semiconductor device1operates normally when an open failure or a short circuit occurs to one arbitrary variable resistance element out of four variable resistance elements configuring the unit element group10.

For example, as illustrated inFIG. 4, when all the variable resistance elements (variable resistance elements11-1,11-2,12-1and12-2) are in an off-state, the unit element group10operates as being in the off-state. Moreover, as illustrated inFIG. 5, when all the variable resistance elements (variable resistance elements11-1,11-2,12-1and12-2) are in an on-state, the unit element group10operates as being in the on-state.

By the way, as illustrated inFIG. 6, when a short circuit occurs to one arbitrary element (the variable resistance element12-2inFIG. 6), the unit element group10maintains the off-state. Moreover, as illustrated inFIG. 7, when an open failure occurs to one arbitrary element (the variable resistance element12-2inFIG. 7), the unit element group10maintains the on-state.

As described above, according to the example embodiment, when a failure of 1 bit occurs when bit-accessing in order to read an element state, the correct resistive state can be acquired from the other 3 bits. Thus, the expected value can be written back on the bit with failure. In the example embodiment, by including the modes of detection of resistive state and writing back in the operation mode, the redundancy of the crossbar circuit is not lost.

Moreover, when 2 bits of failure occurs, the correct resistive state cannot be acquired, however, the detection of failure is still possible. That is to say, by using the unit element group10of the example embodiment, a safe mode that assures a minimum operation can be provided by reporting the detection result to the system.

InFIG. 4toFIG. 7, the degree of parallelism of unit elements is 2, however, as illustrated inFIG. 8, the degree of parallelism may be 3 or more.FIG. 8illustrates an example with unit element groups10-2having the degree of parallelism of 3 or more. In the case ofFIG. 8, when failures occur to more variable resistance elements, the unit element group10operates normally.

As described above, the unit element group of the example embodiment has a configuration in which a plurality of unit elements are connected in parallel, in each of which variable resistance elements are connected in series. As a result, the crossbar circuit using the unit element group of the example embodiment operates normally when an open failure or short circuit of 1 bit occurs to a variable-resistance element.

Here, a procedure for putting a unit element that is arranged at an intersection point of a desired first wiring21and a second wiring22into an on-state when all the unit elements configuring the semiconductor device1arranged in an array are in an off-state is described. The variable resistance element included in the unit element group10is assumed to be a bipolar type element. In addition, each variable resistance element has an active electrode and an inactive electrode. In order to put the variable resistance element into a low resistive state, a high voltage is applied to the active electrode. On the other hand, in order to put the variable resistance element into a high resistive state, a high voltage is applied to the inactive electrode. Here, the active electrode of each variable resistance element is connected to one of the side of the first wiring21and the side of the second wiring22, and the inactive electrode of each variable resistance element is connected to the side of the intermediate node15.

The first programming driver41, the second programming driver42and the intermediate node programming driver45are set to output an intermediate voltage Vmid.

Then, all the first selection transistor35are put into a conductive state by all the first decode signal lines51, and all the first wirings21are set to the intermediate voltage Vmid. Moreover, all the second selection transistors36are put into a conductive state by all the second decode signal lines52, and all the second wirings22are set to an intermediate voltage Vmid. In addition, all the intermediate node selection transistor30are put into a conductive state by all the first decode signal lines51and all the second decode signal lines52, and all the intermediate nodes15are set to the intermediate voltage Vmid.

Moreover, all the first selection transistors35, all the second selection transistors36, and all the intermediate node selection transistors30are put into a non-conductive state.

Then, the first programming driver41is set to output a set voltage Vset, the intermediate node programming driver45is set to output a ground voltage Gnd, and the second programming driver42is put into a high impedance state.

Then, a selection level (High level in this example) is applied to the first decode signal line51and the second decode signal line52that are related to a unit element that is the target of programming, and the intermediate node selection transistor30that is connected to the unit element that is the target of programming is put into a conductive state. As a result, a set voltage Vsetis applied to the variable resistance element that is connected to the side of the first wiring21of each unit element. The above-described procedures allow the variable resistance element to transfer to the on-state.

In a unit element that is not the target of programming, at least one of the intermediate node selection transistor30and the intermediate node common selection transistor34is in the unselected state. As a result, since the intermediate node15is not biased to the Gnd electric potential and the program voltage is not applied, an unintended miswriting is prevented.

Then, the programming of the variable resistance element that is connected to the side of the second wiring22of each unit element is performed by the similar procedure.

In other words, all the first selection transistors35, all the second selection transistors36and all the intermediate node selection transistor30are returned to the non-conductive state. The settings of the first programming driver41, the second programming driver42and the intermediate node programming driver45are restored to output the intermediate voltage Vmid.

Moreover, all the first selection transistors35, all the second selection transistors36and all the intermediate node selection transistors30are put into the conductive state, and all the first wirings21, all the second wirings22and all the intermediate nodes15are set to output the intermediate voltage Vmid.

In addition, the first programming driver41is put into a high impedance state, the intermediate node programming driver45is set to output the Gnd, and the second programming driver42is set to output the Vset.

Then, a selection level (High level in this example) is applied to the first decode signal line51or the second decode signal line52of a unit element that is the target of programming, and the selection transistor that is connected to the unit element that is the target of programming is put into a conductive state. As a result, a set voltage Vsetis applied to the variable resistance element connected to the side of the second wiring22of the unit element. The above-described procedures allow the variable resistance element to transfer to the on-state.

With the above procedures, all the variable resistance elements of the target unit elements are put into the on-state, the programming can be completed.

In the example embodiment, the variable resistance element is a bipolar variable resistance element. However, the variable resistance element may be a unipolar variable resistance element or a combination of a unipolar variable resistance element and a bipolar variable resistance element. The polarity of the bipolar variable resistance elements may be aligned and connected, or the bipolar variable resistance elements may be connected in such a way that the polarities thereof are the opposite. The degree of parallelism of unit elements is 2 in the description, however, a degree of parallelism may be 3 or more.

As described above, the semiconductor device of the example embodiment can provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element.

Second Example Embodiment

With reference to the figures, the semiconductor device according to the second example embodiment of the present invention is described. Detailed description of the configuration similar to the first example embodiment is omitted.

FIG. 9is a conceptual diagram illustrating a configuration of a semiconductor device2according to the example embodiment. In the semiconductor device2of the example embodiment, an intermediate node16of a first unit element11and an intermediate node17of a second unit element12are connected to an intermediate node program line33and a first decode signal line51respectively, unlike the semiconductor device1of the first example embodiment. Therefore, the semiconductor device2includes two intermediate node selection transistors (a first intermediate node selection transistor31and a second intermediate node selection transistor32).

As illustrated inFIG. 9, the intermediate node16of the first unit element11is connected to the intermediate node program line33and the first decode signal line51via the first intermediate node selection transistor31. One of a source terminal and a drain terminal of the first intermediate node selection transistor31is connected to the intermediate node16, and the other terminal is connected to the intermediate node program line33. A gate terminal of the first intermediate node selection transistor31is connected to the first decode signal line51.

Similarly, the intermediate node17of the second unit element12is connected to the intermediate node program line33and the first decode signal line51via the second intermediate node selection transistor32. One of a source terminal and a drain terminal of the second intermediate node selection transistor32is connected to the intermediate node17, and the other terminal is connected to the intermediate node program line33. A gate terminal of the second intermediate node selection transistor32is connected to the first decode signal line51.

As described above, in the semiconductor device of the example embodiment, an intermediate node selection transistor is arranged for each unit element configuring a unit element group. The similar effect as the semiconductor device of the first example embodiment can be obtained with the configuration of the semiconductor device of the example embodiment since the resistive state of each variable resistance element configuring the unit cell group can be set to the same state.

Third Example Embodiment

With reference to the figures, the semiconductor device according to the third example embodiment of the present invention is described. Detailed description for the configuration similar to the first and second example embodiments is omitted.

FIG. 10is a conceptual diagram illustrating a configuration of a semiconductor device3according to the example embodiment.FIG. 11is a conceptual diagram illustrating a unit element group10included in the semiconductor device3ofFIG. 10. The semiconductor device3of the example embodiment includes a third wiring23in addition to a first wiring21and a second wiring22, unlike the semiconductor device1of the first example embodiment. The third wiring23is paired with the first wiring21and is extended to a first direction.

The semiconductor device3includes the third wiring23, a third selection transistor37, a third decode signal line53and a pass transistor60in addition to the semiconductor device2of the second example embodiment.

The third wiring23is paired with the first wiring21, and arranged in parallel. The third wiring23is arranged in such a way as to cross the second wiring22, in the similar way as the first wiring21. The first wiring21and the third wiring23are connected by the pass transistor60.

The first unit element11is arranged at an intersection point of the first wiring21and the second wiring22. The second unit element12is arranged at an intersection point of the second wiring22and the third wiring23. As illustrated inFIG. 11, one end of the first unit element11is connected to the first wiring21via a terminal18-1. On the other hand, one end of the second unit element12is connected to the third wiring23via a terminal18-3. The other ends of the first unit element11and the second unit element12are connected to the second wiring22via a terminal19.

The intermediate node16of the first unit element11is connected to the intermediate node program line33and the first decode signal line51via the first intermediate node selection transistor31.

One of a source terminal and a drain terminal of the first intermediate node selection transistor31is connected to the intermediate node16, and the other terminal is connected to the intermediate node program line33. A gate terminal of the first intermediate node selection transistor31is connected to the first decode signal line51.

The intermediate node17of the second unit element12is connected to the intermediate node program line33and the third decode signal line53via the second intermediate node selection transistor32.

One of a source terminal and a drain terminal of the second intermediate node selection transistor32is connected to the intermediate node17, and the other terminal is connected to the intermediate node program line33. A gate terminal of the second intermediate node selection transistor32is connected to the third decode signal line53.

One of source terminal and the drain terminal of the first selection transistor35is connected to the first wiring21, and the other terminal is connected to the first programming driver41. One of the source terminal and the drain terminal of the third selection transistor37is connected to the third wiring23, and the other terminal is connected to the first programming driver41.

The pass transistor60is connected to the first wiring21and the third wiring23. When the semiconductor device3operates as a crossbar circuit (when no programming is performed), the pass transistor60is put into a conductive state. By putting the pass transistor60into the conductive state, the first wiring21and the third wiring23become the substantially common signal lines. On the other hand, when a programming is performed, the pass transistor60is put into a non-conductive state. By putting the pass transistor60into the non-conductive state, all the variable resistance elements can be uniquely addressed, and the operation state of each variable resistance element can be individually set.

With the semiconductor device of the example embodiment, a unit element can be programmed in the similar programming method described in the first example embodiment. Moreover, the semiconductor device of the example embodiment allows an individual programming of each unit element. That is to say, in the semiconductor device of the example embodiment, a group of the first wiring and the first decode signal line and a group of the third wiring and the third decode signal line can be individually programmed. Thus, a characteristic of the semiconductor device of the example embodiment is that all the variable resistance elements can be uniquely addressed. This characteristic is helpful for reducing a write disturbance and for increasing precision of reading a resistive state.

The pass transistor is put into a conductive state when providing a function as a crossbar circuit provided by the semiconductor device of the example embodiment. As a result, the first wiring and the third wiring become the substantially common signal lines, and the circuit becomes equal to the example embodiment 1 in which two unit elements are connected in parallel at an intersection point in the crossbar. Therefore, the example embodiment can improve the reliability of the crossbar circuit provided by the semiconductor device even more.

Fourth Example Embodiment

With reference to the figures, the semiconductor device (hereinafter referred to as a reconfiguration logical circuit) according to the fourth example embodiment of the present invention is described. A reconfiguration logical circuit4uses a crossbar circuit included in the semiconductor devices1to3disclosed in the first to third example embodiments.

As illustrated inFIG. 12, the reconfiguration logical circuit4includes a crossbar circuit501, a pass transistor502, a lookup table circuit503, a flip flop504and a selector505. The lookup table circuit503, flip flop504and the selector505form a logic block507. The crossbar circuit501includes an input508, and using the crossbar circuit501, an arbitrary input is connected to the lookup table circuit503.

Here, in the crossbar circuit501illustrated inFIG. 12, various elements of the crossbar circuit described in each example embodiment that are necessary for programming are omitted. The connection function of the crossbar circuit501is achieved by turning on/off the unit element to which a variable resistance element is serially connected.

When operating as a crossbar circuit501, the pass transistor502is put into a conductive state. In addition, as a suitable example, the output506of the logic block507is fed back to the lookup table circuit503via the crossbar circuit501.

According to the example embodiment, by expanding a circuit illustrated inFIG. 12, and by linking a large number of circuits, a function as a reconfiguration circuit in a larger scale can be provided.

Fifth Example Embodiment

With reference to the figures, the semiconductor device (hereinafter referred to as a reconfiguration logical circuit) according to the fifth example embodiment of the present invention is described. A reconfiguration logical circuit5has a unit element whose degree of parallelism is 3, and includes a triple modular redundant (TMR) circuit instead of the pass transistor of the fourth example embodiment. For example, the TMR circuit is a circuit that achieves a majority logic that gives an output expressed by a Boolean expression of (A and B) or (B and C) or (C and A) when three values of A, B and C are input.

As illustrated inFIG. 13, the reconfiguration logical circuit5includes a crossbar circuit551, a TMR circuit552, a lookup table circuit553, a flip flop554and a selector555. The lookup table circuit553, the flip flop554and the selector555form a logic block557. The crossbar circuit551includes an input558, and using the crossbar circuit551, an arbitrary input is connected to the lookup table circuit553.

Here, in the crossbar circuit551ofFIG. 13, various elements of the crossbar circuit described in each example embodiment that are necessary for programming are omitted. The connection function of the crossbar circuit551is achieved by turning on/off the unit element to which a variable resistance element is serially connected.

When operating as a crossbar circuit551, the TMR circuit552is put into a conductive state. In addition, as a suitable example, the output556of the logic block557is fed back to the lookup table circuit553via the crossbar circuit551.

According to the example embodiment, by expanding the circuit illustrated inFIG. 13, and by linking a large number of circuits, a function as a reconfiguration circuit in a larger scale can be provided.

The semiconductor device of each example embodiment can be applied not only to a crossbar circuit but also to a semiconductor device including a memory circuit, a semiconductor device including a logical circuit, or a wiring of a board or a package equipped with the circuits or devices. Examples of a semiconductor device including a memory circuit include a dynamic random access memory (DRAM) and a static random access memory (SRAM). Examples of a semiconductor device including a memory circuit include a ferroelectric random access memory (FeRAM) and a magnetic random access memory (MRAM). Examples of a semiconductor device including a memory circuit include a flash memory and a bipolar transistor. A microprocessor can be given as a semiconductor device including a logical circuit. The method of each example embodiment of the present invention may be applied to a wiring of a board or a package equipped with the above-described circuit or the semiconductor device.

The unit element of the present invention can be applied to an electronic circuit device and an optical circuit device used for a semiconductor device, and a switching device such as a micro electro mechanical systems (MEMS).

The present invention has been described above with the example embodiments, however, the present invention is not limited to the above-described embodiments. Within the scope of the present invention, the present invention may be applied with various changes that may be understood by a person skilled in the art.

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