Device and method for driving a display panel

A processing system includes a timing controller and source driver circuitry. The timing controller is configured to stop scanning of a plurality of gate lines of a display panel in response to a detection of a communication failure between the processing system and a controller. The source driver circuitry is configured to update a plurality of display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure. The timing controller may be further configured to resume the scanning of the plurality of gate lines in response to the expiration of the time limit.

FIELD

The disclosed technology generally relates to a device and method for driving a display panel.

BACKGROUND

A display device configured to display an image on a display panel (e.g., a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, and other types of display panels) may be controlled by an external controller. In such implementations, a communication failure between the display device and the external controller may cause a corrupted display image.

SUMMARY

In one or more embodiments, a processing system is provided. The processing system includes a timing controller and source driver circuitry. The timing controller is configured to stop scanning of a plurality of gate lines of a display panel in response to a detection of a communication failure between the processing system and an external controller. The source driver circuitry is configured to update a plurality of display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure.

In one or more embodiments, a display device is provided. The display device includes a display panel and a processing system. The display panel includes a plurality of display elements. The processing system includes a timing controller and source driver circuitry. The timing controller is configured to stop scanning of a plurality of gate lines of the display panel in response to a detection of a communication failure between the processing system and an external controller. The source driver circuitry is configured to update the plurality of display elements to cause a black display in response to expiration of a time limit after the detection of the communication failure.

In one or more embodiments, a method for driving a display panel is provided. The method includes stopping scanning of a plurality of gate lines of a display panel in response to a detection of a communication failure between an external controller and a processing system configured to drive the display panel. The method further includes updating a plurality of display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure.

Other aspects of the embodiments will be apparent from the following description and the appended claims.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. Suffixes may be attached to reference numerals for distinguishing identical elements from each other. The drawings referred to herein should not be understood as being drawn to scale unless specifically noted. Also, the drawings are often simplified and details or components omitted for clarity of presentation and explanation. The drawings and discussion serve to explain principles discussed below, where like designations denote like elements.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, or the following detailed description.

A display panel (e.g., an LCD panel, an OLED display panel, and other types of display panels) may be driven by a processing system that may include one or more integrated circuits (ICs), such as a display driver integrated circuit (DDIC), a touch and display driver integrated circuit (TDDI) or other types of ICs. The processing system may be configured to display a desired image on the display panel under control of an external controller coupled to the processing system via a communication link. The term “coupled” as used herein means connected directly to or connected through one or more intervening components or circuits. Examples of the external controller include a host, an application processor, or other types of controller or processor configured to control the processing system. In various implementations, the external controller is configured to provide image data to the processing system, and the processing system is configured to drive the display panel based on the image data. The external controller may be further configured to provide sync signals (e.g., a horizontal sync signal and a vertical sync signal) to the processing system, and the processing system may be configured to generate one or more internal sync signals (e.g., an internal horizontal sync signal and an internal vertical sync signal) in synchronization with the sync signals received from the external controller. The generated internal sync signals may be used for timing control in the processing system.

A communication failure between the processing system and the external controller may cause a corrupted display image on the display panel. The communication failure may be an unplanned interruption in the transmission of data between the processing system and the external controller. Examples of events that cause the communication failure may include an electrostatic discharge (ESD) strike, noise, unintended disconnection of a physical cable of the communication link. The ESD strike may be an event in which a current spike caused by ESD is applied to the processing system, the external controller, and/or the communication link between the processing system and the external controller. When the communication failure causes unsuccessful reception of image data, the processing system cannot update display elements with proper drive voltages, causing a corrupted display image. The communication failure may also cause unsuccessful reception of the sync signals, which may make it impossible to generate internal sync signals (e.g., an internal horizontal sync signal and an internal vertical sync signal) at proper timing in the processing system. The lack of internal sync signals may cause display image corruption.

The time duration during which the communication failure lasts may depend on the cause of the communication failure. An ESD-related communication failure typically lasts for several to several tens to milliseconds. Meanwhile, a communication failure resulting from unintended disconnection of the physical cable may last for several minutes or longer.

The present disclosure provides an improved scheme to mitigate undesired effects of the communication failure depending on the time duration of the communication failure. In various embodiments, a processing system is configured to stop scanning of gate lines of the display panel in response to a detection of a communication failure between the processing system and an external controller. Stopping the scanning of the gate lines allows keeping the display image unchanged on the display panel, avoiding the display panel being updated with a corrupted image. The stop of the scanning of the gate lines may however cause charge retention in display elements of the display panel, which may cause deterioration (e.g., burn-in) of the display panel. To mitigate the charge retention, source driver circuitry may be configured to drive the display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure. Updating the display elements to cause the black display may discharge at least part of charges retained by the display elements, effectively suppressing the deterioration of the display panel.

FIG. 1illustrates an example implementation of a display device10, according to one or more embodiments. In the illustrated embodiment, the display device10is coupled to a controller20that is external to the display device10. The controller20is configured to control the display device10. The display device10may be configured as a central information display (CID) used in automobile applications. Alternatively, the display device10may be a different type of display, such as a computer monitor display, a television, and so forth. The controller20may be configured to provide image data and control signals (e.g., a sync signal, a clock signal, and a data enable signal) to the display device10. The controller20may be a host, an application processor, or other types of controller or processor.

A physical cable12is used to provide a communication link between the display device10and the controller20. The physical cable12includes a first connector14detachably coupled to the display device10at one end, and a second connector16detachably coupled to the controller20. In one implementation, the physical cable12may be, but not limited to, a high-definition multimedia interface (HDMI) cable adapted to communications based on low voltage differential signaling (LVDS). Other types of cables may be used instead. In other embodiments, the communication link between the display device10and the controller20may be wireless.

FIG. 2illustrates an example configuration of the display device10, according to one or more embodiments. In the illustrated embodiment, the display device10includes a display panel100and a processing system200. The display panel100may be an LCD panel, an OLED display panel, or a different type of display panel. The processing system200may include one or more integrated circuits (ICs), such as a display driver integrated circuit (DDIC), a touch and display driver integrated circuit (TDDI) or other types of ICs.

The display panel100includes a display region (or active region)110. The display region110may include a plurality of display elements112, a plurality of source lines114(which may be also referred to as data lines), and a plurality of gate lines116(which may be also referred to as scan lines). Each display element112may be coupled to a corresponding source line114and gate line116. In embodiments where an LCD panel is used as the display panel100, the display elements112may each comprise a pixel electrode, a select transistor, and a hold capacitor. In embodiments where an OLED display panel is used as the display panel100, the display elements112may each comprise a light emitting element, a select transistor, and a hold capacitor.

In the following, a set of display elements112coupled to a gate line116may be collectively referred to as “horizontal line.” The display elements112of the display panel100are updated on a “horizontal line” basis. Update of display elements112of a horizontal line may be achieved by selecting the corresponding gate line116and providing drive voltages to the display elements112coupled to the selected gate line116.

The display panel100may further include gate driver circuitry120configured to scan the gate lines116during the update of the display elements112of the display panel100. The scanning of the gate lines116may include sequentially selecting or asserting the gate lines116. The gate driver circuitry120is configured to scan the gate lines116in response to a set of gate control signals GOUT received from the processing system200. The display panel100may include various interconnections other than the source lines114and the gate lines116depending on the configuration of the display elements112. In some implementations, the display panel100may further include a plurality of multiplexers each associated with two or more source lines114and configured to selectively connect one of the associated source lines114to the processing system200.

The display panel100may further include a plurality of sensor electrodes118coupled to the processing system200. The sensor electrodes118may be used for proximity sensing to detect an input object in a sensing region of the display panel100, where the sensing region may be defined to overlap or coincide with the display region110. Examples of the input object includes user's fingers and styli. While eight sensor electrodes118are illustrated, those skilled in the art would appreciate the display panel100may include more than or less than eight sensor electrodes118. The sensor electrodes118may also be used for display updating. For example, in embodiments where the display panel100is configured as an LCD panel, the sensor electrodes118may also be used as common electrodes. In such embodiments, the sensor electrodes118may be driven with a common voltage VCOMin updating the display panel100.

The processing system200is configured to update the display panel100based on image data received from the controller20. The image data may include graylevels defined for the respective display elements112of the display panel100. A graylevel for a display element112may correspond to desired brightness of the display element112. In various embodiments, the processing system200is configured to update the respective display elements112of the display panel100with drive voltages corresponding to the graylevels specified by the image data for the respective display elements112. In one implementation, the processing system200is configured to output the drive voltages to the respective display elements112from a set of source outputs S1to Sm (four source outputs S1to S4are illustrated inFIG. 2).

The processing system200is further configured to provide the gate control signals GOUT to the gate driver circuitry120. The gate control signals GOUT may include a gate start pulse signal that indicates a start of scanning of the gate lines116and a set of multi-phase gate clocks used for clocking of the scanning of the gate lines116.

The processing system200may be further configured to detect a contact or approach of an input object to the sensing region (which may overlap or coincide with the display region110) of the display panel100through proximity sensing. The proximity sensing may be based on resulting signals acquired or received from the sensor electrodes118. The proximity sensing may be achieved through absolute capacitance sensing (or self-capacitance sensing) based on the absolute capacitances (or self-capacitances) of the sensor electrodes118, the absolute capacitances being determined based on the resulting signals. The display panel100may further comprise transmitter electrodes that are not illustrated. In such embodiments, the proximity sensing may be achieved through transcapacitance sensing (or mutual capacitance sensing) based on transcapacitances (or mutual capacitances) between the transmitter electrodes and the sensor electrodes118, the transcapacitances being determined based on the resulting signals. In other embodiments, the proximity sensing may be achieved through hybrid sensing that is based on both the absolute capacitance sensing and the transcapacitance sensing.

The operation of the processing system200may be controlled based on control signals and/or control data received from the controller20. The control signals may include sync signals (e.g., an external vertical sync signal and an external horizontal sync signal), a data enable signal, and/or a clock signal. The control data may include commands that indicate desired operations of the processing system200. In one implementation, the control data may include a mode command that specifies an operation mode of the processing system200, and the processing system200may be configured to be placed into the operation mode as specified by the mode command.

The controller20may be configured to embed the image data, the control signals and/or the control data in low-voltage differential signals and provide the differential signals to the processing system200. The processing system200may be configured to reproduce the image data, the control signals and/or the control data from the differential signals.

FIG. 3illustrates an example configuration of the processing system200according to one or more embodiments. In the illustrated embodiment, the processing system200includes a TDDI202and a non-volatile memory204configured to store a firmware used to control the TDDI202. The non-volatile memory204may be further configured to store setting parameters, control data and/or other information used to control the TDDI202. In other embodiments, the non-volatile memory204may be incorporated in the TDDI202. In still other embodiments, components of the TDDI202may be distributed in a plurality of integrated circuit (IC) chips.

In the illustrated embodiment, the TDDI202includes a display driver block206and a proximity sensing block208. The display driver block206is configured to drive or update the display panel100, and the proximity sensing block208configured to detect one or more input objects in the sensing region of the display panel100through proximity sensing.

In one or more embodiments, the display driver block206includes an LVDS receiver210, a first-in-first-out (FIFO) circuit212, image processing circuitry214, a line buffer216, source driver circuitry218, internal Vsync/Hsync generator220, a timing controller222, panel interface (I/F) circuitry224, an oscillator226, parameters and status registers circuitry228, and a display command controller230.

The LVDS receiver210is configured to receive the differential signals from the controller20and reproduce the image data from the received differential signals. The LVDS receiver210is further configured to forward the reproduced image data to the FIFO212. The LVDS receiver210is further configured to reproduce control signals from the differential signals. In one implementation, the reproduced control signals may include an external vertical sync signal LVDS_Vsync, an external horizontal sync signal LVDS_Hsync, a data enable signal LVDS_DE, and a recovered clock signal LVDS_CLK. A different type of receiver may be used to receive signals that carry the image data, the control data, and the control signals in place of the LVDS receiver210.

In various embodiments, the LVDS receiver210includes clock recovery circuitry configured to generate the recovered clock signal LVDS_CLK from the LVDS differential signals through clock recovery. The recovered clock signal LVDS_CLK is “phase-locked” or simply “locked” when the recovered clock signal LVDS_CLK is made synchronous with the LVDS differential signals. The terms “locked” referred herein may mean the state in which the phase of the recovered clock signal LVDS_CLK is stably regulated. The clock recovery circuitry may include, for example, a phase-locked loop (PLL) or a delay-locked loop (DLL).

The LVDS receiver210may be further configured to monitor communications between the controller20and the processing system200and detect a communication failure. Since a communication failure between the controller20and the processing system200causes the recovered clock signal LVDS_CLK to be “unlocked”, the detection of the communication failure may be based on whether the recovered clock signal LVDS_CLK is “unlocked.” The term “unlocked” referred herein may mean the state in which the phase of the recovered clock signal LVDS_CLK is unstable. In one implementation, the communication failure between the controller20and the processing system200may be detected by detecting the “unlocking” of the recovered clock signal LVDS_CLK.

The LVDS receiver210may be configured to provide an unlocked state flag flag_lockoff that indicates the unlocking of the recovered clock signal LVDS_CLK to the timing controller222. The unlocked state flag flag_lockoff may be set in response to the detection of the unlocking of the recovered clock signal LVDS_CLK. The unlocked state flag flag_lockoff may be reset in response to a detection of re-locking of the recovered clock signal LVDS_CLK. Since recovery from the communication failure causes re-locking of the recovered clock signal LVDS_CLK, in one implementation, the recovery from the communication failure may be detected based on the re-locking of the recovered clock signal LVDS_CLK.

The FIFO212is configured to receive and store the image data from the LVDS receiver210. The FIFO212is further configured to forward the image data to the image processing circuitry214in an FIFO manner.

The image processing circuitry214is configured to process the image data received from the FIFO212and provide the processed image data to the line buffer216. The processing performed by the image processing circuitry214may include color adjustment, image scaling, gamma transformation, subpixel rendering and/or other processes. In other embodiments, the image data stored in the FIFO212may be forwarded to the line buffer216without modification.

The line buffer216is configured to transfer the processed image data from the image processing circuitry214to the source driver circuitry218on a “horizontal line” basis, where the horizontal line referred herein corresponds to a set of display elements112coupled to one gate line116(also seeFIG. 2). In one implementation, the line buffer216has a capacity to store image data for one horizontal line and is configured to successively update the stored image data with the processed image data successively received from the image processing circuitry214.

The line buffer216is further configured to provide the source driver circuitry218with image data specifying graylevels corresponding to “black” for all the display elements112of the horizontal line of interest, independently of the processed image data received from the image processing circuitry214. The line buffer216may be configured such that image data specifying the graylevel corresponding to “black” for all the display elements112of the horizontal line of interest are set to the line buffer216in response to an assertion of a black display instruction signal Black_Display received from the timing controller222. The line buffer216may further provide the source driver circuitry218with the image data corresponding to “black” in response to the assertion of the black display instruction signal Black_Display. The graylevel corresponding to “black” may be the minimum graylevel (e.g., zero.) In embodiments where the display panel100is an LCD panel, the minimum graylevel may correspond to one of the allowed drive voltages closest to the common voltage Vcom supplied to one or more common electrodes of the LCD panel. In various implementations, a black display on the display panel100may be achieved by providing the image data corresponding to “black” to the source driver circuitry218by using the line buffer216, as describe later in detail.

The source driver circuitry218is configured to update the display elements112of the display panel100based on the image data received from the line buffer216(e.g., the processed image data or the image data specifying graylevels corresponding to “black” for all the display elements). The source driver circuitry218may be configured to update the display elements112of the display panel100with drive voltages corresponding to the graylevels specified for the respective display elements112by the image data received from the line buffer216.

The internal Vsync/Hsync generator220is configured to generate an internal vertical sync signal int_Vsync and an internal horizontal sync signal int_Hsync based on the external vertical sync signal LVDS_Vsync, the external horizontal sync signal LVDS_Hsync, and the recovered clock signal LVDS_CLK. The internal vertical sync signal int_Vsync may define frame periods (or vertical sync periods) during each of which the display elements112of the entire display panel100are updated. The internal horizontal sync signal int_Hsync may define horizontal sync periods during each of which display elements112of one horizontal line are updated. The internal vertical sync signal int_Vsync may be generated in synchronization with the external vertical sync signal LVDS_Vsync, and the internal horizontal sync signal int_Hsync may be generated in synchronization with the external horizontal sync signal LVDS_Hsync. The recovered clock signal LVDS_CLK may be used for clocking in the generation of the internal vertical sync signal int_Vsync and the internal horizontal sync signal int_Hsync.

The timing controller222is configured to offer overall control of the processing system200in synchronization with the internal vertical sync signal int_Vsync and the internal horizontal sync signal int_Hsync received from the internal Vsync/Hsync generator220. More specifically, the timing controller222may be configured to provide timing control for components disposed in the processing system200(e.g., the FIFO212, the image processing circuitry214, the line buffer216, the source driver circuitry218, the panel interface circuitry224and other components). The timing controller222may be further configured to generate and provide the black display instruction signal Black_Display to the line buffer216. The timing controller222may be further configured to generate and provide an interrupt request and a proximity sensing enable signal to the proximity sensing block208.

The panel interface circuitry224is configured to generate and provide the gate control signals GOUT to the gate driver circuitry120of the display panel100under the control of the timing controller222. In various implementations, the panel interface circuitry224may be configured to control start and stop of the scanning of the gate lines116with the gate control signals GOUT under the control of the timing controller222. The scanning of the gate lines116may be started by starting driving the gate control signals GOUT and stopped by keeping the signal levels of the gate control signals GOUT unchanged.

The oscillator226is configured to generate an internal oscillation signal. As described later in detail, the internal oscillation signal may be used to generate the internal vertical sync signal int_Vsync and the internal horizontal sync signal int_Hsync in cases where the external vertical sync signal LVDS_Vsync and the external horizontal sync signal LVDS_Hsync are not successfully reproduced due to a communication failure between the controller20and the processing system200.

The parameters and status registers circuitry228is configured to store parameters, register values, and/or other information used to control the processing system200. In various implementations, the parameters and status registers circuitry228may be configured to store a register value that indicates the operation mode of the processing system200, and the processing system200may be placed in the operation mode specified by the register value. The parameters and status registers circuitry228may be further configured to store a gate scan stop flag flag_stop_gate_scan that indicates whether the scanning of the gate lines116is currently stopped. The gate scan stop flag flag_stop_gate_scan may be set in response to stop of the scanning of the gate lines116.

The parameters and status registers circuitry228is further configured to provide interface between the display driver block206and the proximity sensing block208. The proximity sensing block208may be configured to recognize the status of the display driver block206(e.g., whether the scanning of the gate lines116is currently stopped) based on one or more register values stored in the parameters and status registers circuitry228and control the operation of the display driver block206by updating one or more register values stored in the parameters and status registers circuitry228.

The display command controller230is configured to control the overall operation of the processing system200based on a command received from the controller20. The display command controller230may be configured to update the parameters and/or register values stored in the parameters and status registers circuitry228based on the received command. In one implementation, the display command controller230may be configured to control the operation mode of the processing system200by updating one or more register values stored in the parameters and status registers circuitry228in response a mode command received from the controller20.

In one or more embodiments, the proximity sensing block208includes a proximity sensing analog front end (AFE)232, a processor234, system interface (I/F) circuitry236, and a random access memory238. The proximity sensing AFE232is configured to receive resulting signals from the sensor electrodes118and generate analog-to-digital conversion (ADC) data corresponding to the resulting signals. Generating the ADC data may include conditioning (filtering, baseline compensation, and/or other analog processing) of the resulting signals and analog-to-digital conversion of the conditioned resulting signals. In embodiments where the resulting signals from the sensor electrodes118are acquired in a time divisional manner, the proximity sensing AFE232may be configured to provide guarding voltage Vguard to sensor electrodes118from which resulting signals are not currently acquired. In embodiments where the proximity sensing is achieved through transcapacitive sensing, the proximity sensing AFE232may be configured to provide transmitter signals to transmitter electrodes disposed in the sensing region of the display panel100. The operation of the proximity sensing AFE232may be controlled based on one or more register values received from the processor234.

The processor234is configured to generate positional information of one or more input objects in the sensing region of the display panel100based on the resulting signals acquired from the sensor electrodes118. In one implementation, the processor234may be configured to process the ADC data, which correspond to the resulting signals acquired from the sensor electrodes118, to generate the positional information. Examples of the processor234include a micro control unit (MCU), a central processing unit (CPU) and other types of processors.

The processor234may be further configured to control the overall operation of the proximity sensing block208. More specifically, the processor234may be configured to perform proximity sensing to detect one or more input object in response to an assertion of the proximity sensing enable signal received from the timing controller222. The processor234may be configured to control the proximity sensing AFE232by providing register values to the proximity sensing AFE232.

The processor234may be further configured to control the operation of the display driver block206. More specifically, the processor234may be configured to receive an interrupt request from the timing controller222of the display driver block206and access the parameters and status registers circuitry228in response to the interrupt request to recognize the current status of the display driver block206by referring to one or more register values stored in the parameters and status registers circuitry228. The processor234may be further configured to control the operation mode of the display driver block206based on the recognized current status.

The processor234may include a timer234a. The timer234amay be a hardware-based timer or a software-based timer. As described later in detail, the timer234amay be used to detect expiration of a predetermined time limit after a detection of a communication failure between the controller20and the processing system200. In one implementation, the timer234amay include a counter configured to start counting in response to the detection of the communication failure. In such embodiments, the timer234amay be configured to detect the expiration of the time limit based on occurrence of an overflow of the counter.

The operation of the processor234may be based on the firmware stored in the non-volatile memory204. In one implementation, the processor234may be configured to retrieve program codes of the firmware upon start-up and/or reset of the processing system200and store the program codes in the RAM238. The processor234may be further configured to execute the program codes stored in the RAM238.

The system interface (I/F) circuitry236is configured to provide interface between the controller20and the processor234. The system interface circuitry236may be configured to forward the positional information from the processor234to the controller20. The system interface circuitry236may be further configured to forward instructions from the controller20to the processor234.

FIG. 4illustrated an example operation of the processing system200in the case where an ESD strike occurs, according to one or more embodiments. InFIG. 4(and other figures), “VBP” stands for a vertical back porch period that starts upon an assertion of the external vertical sync signal LVDS_Vsync, “DE” stands for a display update period that follows the vertical back porch period, and “VFP” stands for a vertical front porch period that follows the display update period. The display update period may be a period during which image data for the display elements112are transferred from the controller20to the processing system200. The numbers in the “Updated H Line” section indicate the horizontal line which is being updated. The number “0” in the “Updated H Line” section indicates that the horizontal line identified by the horizontal line identification (ID) “0” is being updated, and the number “1” in the “Updated H Line” section indicates that the horizontal line identified by the horizontal line ID “1” is being updated. The same goes for other numbers in the “Updated H Line” section.

Initially, the processing system200is placed in a video RAM mode (or a first mode) in which the processing system200updates the display elements112of the display panel100based on a stream of image data received from the controller20.

In the embodiment illustrated inFIG. 4, the ESD strike causes a short-term communication failure between the controller20and the processing system200, where the period of the communication failure falls in one frame period. The communication failure may cause unsuccessful reproduction of the image data and also cause unlocking of the recovered clock signal LVDS_CLK, resulting in unsuccessful reproduction of the external horizontal sync signal LVDS_Hsync and the data enable signal LVDS_DE. The unlocking of the recovered clock signal LVDS_CLK is indicated by “Unlocked” inFIG. 4. The unsuccessful reproduction of the image data, the external horizontal sync signal LVDS_Hsync and the data enable signal LVDS_DE may potentially cause display of a corrupted image on the display panel100.

The LVDS receiver210detects the communication failure caused by ESD strike. In the embodiment illustrated inFIG. 4, in response to the detection of the communication failure between the controller20and the processing system200, the timing controller222causes the panel interface circuitry224to stop scanning of the gate lines116of the display panel100. The stop of the scanning of the gate lines116causes the display image to remain unchanged, avoiding a corrupted image being displayed on the display panel100.

More specifically, in one implementation, the LVDS receiver210may detect the unlocking of the recovered clock signal LVDS_CLK and set the unlocked state flag flag_lockoff in response to the detection of the unlocking. The timing controller222may place the processing system200into a gate scan stop mode (or a second mode) in response to the unlocked state flag flag_lockoff being set. Placing the processing system200into the gate scan stop mode may include setting the gate scan stop flag flag_stop_gate_scan stored in the parameters and status registers circuitry228. In response to the processing system200being placed into the gate scan stop mode, the panel interface circuitry224may keep the signal levels of the gate control signals GOUT unchanged, causing the gate driver circuitry120of the display panel100to stop scanning of the gate lines116.

The timing controller222further may cause the source driver circuitry218to stop outputting the drive voltages in response to the processing system200being placed into the gate scan stop mode. In one implementation, the source driver circuitry218may keep the voltage levels on the source outputs S1to Sm unchanged in response to the processing system200being placed into the gate scan stop mode.

The timing controller222may further cause the proximity sensing block208to stop the proximity sensing in the gate scan stop mode. In one implementation, the timing controller222may deassert the proximity sensing enable signal in the gate scan stop mode, and the processor234may stop the proximity sensing in response to the deassertion of the proximity sensing enable signal.

Meanwhile, the processor234starts the timer234a, which has a predetermined time limit, in response to the detection of the communication failure between the controller20and the processing system200. In one implementation, the timing controller222may issue an interrupt request to the processor234and thereby prompt the processor234to access the parameters and status registers circuitry228. The processor234may recognize that the gate scan stop flag flag_stop_gate_scan stored in the parameters and status registers circuitry228is set and start the timer234ain response to the gate scan stop flag flag_stop_gate_scan being set.

In the operation illustrated inFIG. 4, the communication failure is recovered before expiration of the time limit set on the timer234a, since the communication failure, which results from the ESD strike, lasts only for a short time (e.g., within one frame period). In response to the recovery from the communication failure, the timing controller222causes the processing system200to resume updating the display elements112of the display panel100based on the image data.

More specifically, in one implementation, the LVDS receiver210may detect the recovery from the communication failure based on detection of re-locking of the recovered clock signal LVDS_CLK. In response to the detection of the re-locking of the recovered clock signal LVDS_CLK, the LVDS receiver210may reset the unlocked state flag flag_lockoff, and the timing controller222may return the processing system200from the gate scan stop mode to the video RAM mode (or the first mode) in response to the unlocked state flag flag_lockoff being reset. In the embodiment illustrated inFIG. 4, the gate scan stop mode lasts during the rest of the frame period in which the communication failure is detected and the next frame period, and the processing system200returns to the video RAM mode at the beginning of the second next frame period to the frame period in which the communication failure is detected.

Returning the processing system200to the video RAM mode may include resetting the gate scan stop flag flag_stop_gate_scan stored in the parameters and status registers circuitry228. In response to the gate scan stop flag flag_stop_gate_scan being reset, the panel interface circuitry224may resume driving the gate control signals GOUT, causing the gate driver circuitry120of the display panel100to resume scanning of the gate lines116. The timing controller222may further cause the source driver circuitry218to resume outputting the drive voltages to the display elements112based on the processed image data received from the line buffer216in response to the processing system200being placed into the video RAM mode. The resuming of the scanning of the gate lines116and the outputting of the drive voltages to the display elements112achieves resuming the updates of the display elements112based on the image data received from the controller20.

The timing controller222may further cause the proximity sensing block208to resume the proximity sensing in response to the recovery from the communication failure. In one implementation, the timing controller222may assert the proximity sensing enable signal in response to the unlocked state flag flag_lockoff being reset, and the processor234may resume the proximity sensing in response to the assertion of the proximity sensing enable signal.

It is noted that the processing system200may perform the same operation as illustrated inFIG. 4when a short-time communication failure resulting from a cause other than the ESD strike (e.g., noise or other type of interference) occurs.

FIG. 5illustrates an example operation of the processing system200in the case where the physical cable12is disconnected from the display device10and/or the controller20, according to one or more embodiments. The disconnection of the physical cable12causes a communication failure between the controller20and the processing system200and therefore the processing system200operates similarly as described in relation toFIG. 4. More specifically, in response to the detection of the communication failure between the controller20and the processing system200, the timing controller222may place the processing system200into the gate scan stop mode and cause the panel interface circuitry224to stop scanning of the gate lines116of the display panel100. The timing controller222may further cause the source driver circuitry218to stop outputting the drive voltages in the gate scan stop mode. In one implementation, the source driver circuitry218may keep the voltage levels on the source outputs S1to Sm unchanged in response to the processing system200being placed into the gate scan stop mode. The timing controller222may further cause the proximity sensing block208to stop the proximity sensing in the gate scan stop mode. Meanwhile, the processor234starts the timer234ain response to the detection of the communication failure between the controller20and the processing system200.

It is noted that the disconnection of the physical cable12from the display device10and/or the controller20possibly causes a long-term communication failure which may last for several minutes or longer. Under such situations, stopping the scanning of the gate lines116may cause deterioration (e.g., burn-in) of the display panel100due to charge retention in the display elements112of the display panel100.

To avoid the deterioration of the display panel100potentially caused by the charge retention, as illustrated in the right part ofFIG. 5, the processing system200is configured to update the display elements112of the display panel100to cause a black display in response to expiration of a predetermined time limit after the detection of the communication failure. In embodiments where the timer234ahas the time limit and the processor234is configured to start the timer234ain response to the detection of the communication failure, the updating of the display elements112to cause the black display may be responsive to an elapse of the timer234a. Updating the display elements112to cause the black display may discharge at least part of charges retained by the display elements112, suppressing or avoiding the deterioration of the display panel100. The time limit may be preset such that the deterioration of the display elements112is effectively suppressed or avoided.

In one implementation, in response to expiration of the time limit set on the timer234a, the processor234may switch the operation mode of the processing system200from the gate scan stop mode to a black display mode (or a third mode). The black display mode may be one of command modes. The command mode referred herein may be an operation mode in which the processing system200is controlled by commands issued by the controller20and/or the processor234. The switching of the operation mode from the gate scan stop mode to the black display mode may be achieved by updating one or more register values stored in the parameters and status registers circuitry228, the one or more register values specifying the operation mode of the processing system200.

In response to the processing system200being placed into the black display mode, the timing controller222may further deassert the gate scan stop flag flag_stop_gate_scan to resume scanning of the gate lines116. It is noted that the external vertical sync signal LVDS_Vsync and the external horizontal sync signal LVDS_Hsync are not being successfully reproduced at this moment due to the communication failure. Accordingly, the timing controller222may cause the internal Vsync/Hsync generator220to generate the internal vertical sync signal int_Vsync and the internal horizontal sync signal int_Hsync using the internal oscillator226disposed in the processing system200without control from the controller20. The panel interface circuitry224may generate and provide the gate control signals GOUT to the gate driver circuitry120of the display panel100in synchronization with the internal vertical sync signal int_Vsync and the internal horizontal signal int_Hsync thus generated in response to the deassertion of the gate scan stop flag flag_stop_gate_scan, causing the gate driver circuitry120resume scanning of the gate lines116.

The timing controller222may further set a display status register value stored in the parameters and status registers circuitry228, which is indicated by “Display Status” inFIG. 5(and other figures), to a value that indicates an abnormal display state that represents that the display device10is not currently normally displaying an image on the display panel100. The timing controller222may further issue an interrupt request to the processor234. The processor234may access the parameters and status registers circuitry228and recognize the display status register value.

The timing controller222may further control the source driver circuitry218to achieve the black display on the display panel100while the gate lines116are scanned. In one implementation, the timing controller222may further assert the black display instruction signal Black_Display in the black display mode to cause the line buffer216to provide image data corresponding to “black” to the source driver circuitry218. The source driver circuitry218may output drive voltages corresponding to “black” to the display elements112of the display panel100as specified by the image data received from the line buffer216. As a result, the display elements112of the display panel100are updated to achieve the black display on the display panel100.

In other embodiments in which the display panel100is an LCD panel, the black display may be achieved by causing the source driver circuitry218to output the common voltage Vcom to the display elements112while the gate lines116are being scanned. The common voltage Vcom may be a voltage supplied to one or more common electrodes of the LCD panel. In embodiments where the sensor electrodes118are used as the common electrodes, the common voltage Vcom may be provided to the sensor electrodes118while the display elements112are updated.

The timing controller222may further cause the proximity sensing block208to resume the proximity sensing in response to the processing system200being placed into the black display mode. In one implementation, the timing controller222may assert the proximity sensing enable signal in the black display mode, and the processor234may resume the proximity sensing in response to the assertion of the proximity sensing enable signal. Resuming the proximity sensing allows the processing system200to receive a user input and respond to the user input in the black display mode.

The black display is continued until the communication failure is recovered. In embodiments where the communication failure results from disconnection of the physical cable12from the display device10and/or the controller20, the communication failure may be recovered by connecting the physical cable12to the display device10and/or the controller20.

FIG. 6illustrates an example operation of the processing system200in the case where the communication failure is recovered by connecting the physical cable12to the display device10and the controller20while the processing system200is in the black display mode, according to one or more embodiments. In response to the recovery from the communication failure, the timing controller222causes the processing system200to resume updating the display elements112of the display panel100based on the image data received from the controller20. More specifically, the LVDS receiver210may detect the recovery from the communication failure based on detection of re-locking of the recovered clock signal LVDS_CLK. In response to the detection of the re-locking of the recovered clock signal LVDS_CLK, the LVDS receiver210may reset the unlocked state flag flag_lockoff, and the timing controller222may return the processing system200from the black display mode (or the third mode) to the video RAM mode (or the first mode) in response to the unlocked state flag flag_lockoff being reset. The timing controller222may set the display status register value stored in the parameters and status registers circuitry228to the value that indicates the normal display state. The timing controller222may further issues an interrupt request to the processor234. The processor234may access the parameters and status registers circuitry228in response to the interrupt request and recognize the display status register value. In response to the display status register value being set to the value that indicates the normal display state, the processor234may switch the processing system200from the black display mode to the video RAM mode. The timing controller222may further deassert the black display instruction signal in response to the processing system200being placed into the video RAM mode to allow the line buffer216to receive the processed image data from the image processing circuitry214. The line buffer216may start providing the processed image data to the source driver circuitry218, allowing the source driver circuitry218to resume outputting the drive voltages to the display elements112based on the image data received from the controller20.

It is noted that the processing system200may perform the same operation as illustrated inFIGS. 5 and 6when a long-time communication failure resulting from a cause other than the disconnection of the physical cable12(e.g., noise or other type of interference) occurs.

FIG. 7illustrates an example configuration of the processing system200, according to other embodiments. In the embodiment illustrated inFIG. 7, the timing controller222includes a timer222ahaving a predetermined time limit, while the rest of the processing system200ofFIG. 7is configured similarly to the processing system200ofFIG. 3.

In one implementation, the timing controller222may be configured to switch the operation mode of the processing system200from the gate scan stop mode to the black display mode using the timer222a. The timing controller222may be configured to start the timer222ain response to a detection of the communication failure between the controller20and the processing system200. The timing controller222may be further configured to switch the operation mode of the processing system200from the gate scan stop mode to the black display mode in response to expiration of a time limit after the detection of the communication failure. In embodiments where the timer222ahas the time limit, the switching of the operation mode from the gate scan stop mode to the black display mode may be responsive to an elapse of the timer222a. The switching of the operation mode may include setting the gate scan stop flag flag_stop_gate_scan. The timing controller222may be further configured to switch the operation mode from the black display mode to the video RAM mode in response to the detection of recovery from the communication failure.

Method800ofFIG. 8illustrates steps for driving a display panel (e.g., the display panel100illustrated inFIGS. 1 and 2). At step802, a processing system configured to drive a display panel (e.g., the processing system200illustrated inFIGS. 2 and 3) monitors communications between an external controller (e.g., the controller20illustrated inFIGS. 1 to 3) and the processing system. At step804, the processing system stops scanning of a plurality of gate lines (e.g., the gate lines116) of the display panel in response to a detection of a communication failure between the external controller and the processing system. Stopping the scanning of the gate lines may allow keeping the display image unchanged on the display panel, avoiding the display panel being updated with a corrupted image. At step806, the processing system updates a plurality of display elements (e.g., the display elements112illustrated inFIG. 2) of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure. Updating the display elements to cause the black display may discharge at least part of charges retained by the display elements, effectively suppressing the deterioration of the display panel.

While many embodiments have been described, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope. Accordingly, the scope of the invention should be limited only by the attached claims.