Memory devices and methods for managing use history

A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0151008, filed in the Korean Intellectual Property Office on Nov. 11, 2022, and the entire contents of the above-identified application are incorporated by reference herein.

BACKGROUND

The present disclosure relates to memory devices and to methods for managing use history.

(b) Description of the Related Art

Due to use of specified workloads, such as compression, encryption, and artificial intelligence, and the rapid increase in data capacity, demand is increasing for heterogeneous computing in which an accelerator developed for a special purpose operates together with a general purpose processor.

Such an accelerator may require or utilize a high performance connection with a processor, such that it is ideal for the accelerator and processor to share a memory space to reduce an overhead and latency. Therefore, studies have been performed on inter-chip connection protocols which maintain a memory and cache consistency by connecting the processor to various accelerators, and on reliability of memory devices used therefor.

SUMMARY

Some embodiments of the present disclosure provide methods for managing use history and memory devices using the same, which may improve a reliability of the memory devices.

According to some examples of embodiments, a memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

The time counter may include a timer which is configured to output the count signal according to the predetermined time interval.

The time counter may be configured to output the count signal according to the predetermined time interval based on a clock signal.

The use history circuit may include a counter circuit which is configured to increase the operating time value when the count signal is received.

The memory device may further include an encryption circuit which is configured to encrypt the operating time value and the validation value, resulting in an encrypted operating time value and encrypted validation value, and the memory device may further include a decryption circuit which is configured to decrypt the encrypted operating time value and the encrypted validation value.

When the count signal is received, the use history circuit may be configured to decrypt the encrypted operating time using the decryption circuit and increase the decrypted operating time, thereby updating the operating time value, and the use history circuit may be configured to encrypt the updated operating time using the encryption circuit.

The use history circuit may be configured to update the validation value based on the updated operating time value and encrypt the updated validation value using the encryption circuit.

The memory device may further include a read only memory (ROM), which is configured to store an encryption code and a decryption code. The encryption circuit may be configured to encrypt the operating time value and the validation value using the encryption code, and the decryption circuit may be configured to decrypt the encrypted operating time value and the encrypted validation value using the decryption code.

The use history circuit may be configured to output the written operating time value and the written validation value in response to an operating time request command received from an external source.

The use history circuit may be configured to decrypt an encrypted written operating time value and encrypted written validation value prior to outputting the written operating time value and the written validation value.

The use history circuit may be configured to generate the validation value using the operating time value, a serial number, and a manufacturer code associated with the serial number.

According to some examples of embodiments, a memory device may include a command counter which is configured to output a count signal when a command is received; a use history circuit which is configured to write a number of processed commands based on the count signal and generate and write a validation value corresponding to the number of processed commands; and a command decoder which is configured to receive a first instruction from a memory controller. The first instruction may be according to an operation mode that is determined based on the number of processed commands and the validation value.

The received command may be at least one of a read command and a write command.

The command counter may be connected to the command decoder and the command decoder may be configured to decode a second instruction received from the memory controller to obtain and output the command to the command counter.

The memory device may further include: an encryption circuit which is configured to encrypt the number of processed commands and the validation value; and a decryption circuit which is configured to decrypt the encrypted number of processed commands and the encrypted validation value.

When the count signal is received, the use history circuit may be configured to decrypt the encrypted number of processed commands using the decryption circuit and increase the decrypted number of processed commands, thereby updating the number of processed commands, and the use history circuit may be configured to encrypt the updated number of processed commands using the encryption circuit.

The use history circuit may be configured to update the validation value based on the updated number of processed commands and encrypt the updated validation value using the encryption circuit.

The use history circuit may be configured to output the written number of processed commands and the written validation value in response to a request command for the number of processed commands received from an external source.

The use history circuit may be configured to generate the validation value using the number of processed commands, a serial number, and a manufacturer code associated with the serial number.

According to some examples of embodiments, a method for managing a use history of a memory device may include: obtaining a second use history by decrypting a stored first use history when a count signal is received; obtaining a third use history by updating the second use history; encrypting and storing the third use history; generating a validation value based on the third use history; and encrypting and storing the validation value, the third use history and the validation value are used to determine an operation mode of the memory device.

DETAILED DESCRIPTION

In the following detailed description, only some examples of embodiments of the present inventive concepts have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present inventive concepts.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In the flowchart described with reference to the drawing, an operation order may be changed, several operations may be combined, or any operation may be separated, and a specific operation may not be performed.

Further, an expression described in a singular form may be interpreted as a singular form or plural form unless an explicit expression such as “one” or “single” is used. Terms including ordinal numbers such as first or second may be used to describe various constituent elements, but the constituent element is not limited by the terms. These terms may be used to distinguish one constituent element from the other constituent element.

FIG.1is a schematic block diagram of a memory system according to some examples of embodiments.

Referring toFIG.1, a memory system10includes a memory controller100and a memory device200.

The memory controller100may control an overall operation of the memory system10. The memory controller100may write data in the memory device200and/or read out data from the memory device200using a command and an address. For example, the memory controller100and the memory device200may be connected using an individual pin and an individual transmission line (or a plurality of pins and transmission lines) to exchange a command, an address, or data. According to some embodiments, the memory system10includes a plurality of memory devices200and the plurality of memory devices200communicates with the memory controller100.

The memory controller100may control the memory device200in response to an instruction of the host (not shown). The host may request a data processing operation of the memory system10, for example, a data reading operation, a data writing program operation, and/or a data erasing operation. For example, the host may be a central processing unit (CPU), a graphic processing unit (GPU), and a microprocessor, or an application processor (AP).

The host may communicate with the memory controller100using an interface protocol such as a peripheral component interconnect express (PCIe), an advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), serial attached SCSI (SAS), or compute eXpress link (CXL). Further, the interface protocol between the host and the memory controller100is not limited to the above-described examples and may be implemented by any one of a number of interface protocols, such as a universal serial bus (USB), a multi-media card (MMC), an enhanced small disk interface (ESDI), or integrated drive electronics (IDE), as non-limiting examples.

The memory device200may be a volatile memory or a non-volatile memory.

For example, the memory device200may be a dynamic random access memory (DRAM) such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a lower power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, lower power DDR (LPDDR), or a Rambus dynamic random access memory (RDRAM).

As another example, the memory device200may be a static random access memory (SRAM), a NAND flash memory, a vertical NAND (VNAND) flash memory, a bonding vertical NAND (BVNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAIVI), a phase-change RAM (PRAM), a magneto resistive RAM (MRAM), a ferroelectric RAM (FRAM), a spinimplant spin transfer torque RAM (STT-RAM), or a conductive bridging RAM (CBRAM).

The memory device200may generate a use history. The use history may be about a time (e.g., operating time) or a command. For example, the memory device200may count and store at least one of an operating time of the memory device200and/or a number of commands processed by the and memory device200. The memory device200may encrypt and store the use history.

The memory device200may transmit the use history to the memory controller100. The memory device200may decrypt (or decode) the encrypted use history to provide the decrypted use history to the memory controller100. The memory controller100may determine and/or set a level of the memory device200based on the use history of the memory device200. For example, if the operating time of the memory device200is relatively short or a number of processed commands is relatively small, the memory controller100may determine or set the level of the memory device200as a first level. If the operating time of the memory device200is relatively long or a number of processed commands is relatively large, the memory controller100may determine or set the level of the memory device200as a second level. The first level may be higher than the second level.

The memory controller100may determine an operation mode of the memory device200according to the determined or set level of the memory device200. For example, if the level of the memory device200is high (e.g., the first level), the memory controller100may use the memory device200as a memory for an accelerator, since use as an accelerator may require a relatively faster speed. If the level of the memory device200is low (e.g., the second level), the memory controller100may use the memory device200as a memory for storing (or storage memory), since use as a storage memory may require relatively higher reliability. The memory controller100may perform more refresh (e.g., a greater number of refresh operations) in a memory device200having a low level than in a memory device200having a high level.

The memory device200may generate a validation value. For example, the memory device200may generate a validation value according to the use history. The memory device200may encrypt and store the validation value. The memory device200may decrypt the encrypted validation value and may provide the decrypted validation value to the memory controller100.

The memory controller100may also generate a validation value for the memory device200based on the decrypted use history. The memory controller100may determine or compare whether the validation value (or a restored value) generated by the memory controller100based on the decrypted use history matches with the decrypted verification value provided by the memory device200. If it is determined that the validation values match, the memory controller100may determine or set the level of the memory device200based on the decrypted use history. If it is determined that the validation values do not match, the memory controller100may determine or set the level of the memory device200to a lowest level. For example, the memory controller100may use memory devices200determined or set to have the lowest level as a storing memory. According to some embodiments, an operation of determining a level and an operation mode of the memory device200may be performed by another element outside the memory device200. In some instances, where the validation values do not match, it may indicated that there has been a hacking attempt.

FIG.2is a schematic block diagram of a memory device according to some examples of embodiments.

Referring toFIG.2, a memory device300according to some examples of embodiments may manage a use history about time (e.g., operation time), and may include a time counter310, a use history circuit (odometer)320, an encryption circuit330, a decryption circuit335, a read only memory (ROM)340, and a cell350. The use history about the time may refer to an operating time of the memory device300. The memory device300may be used as the memory device200ofFIG.1.

The time counter310may output a count signal to the use history circuit320in a predetermined time interval. In some embodiments, the time counter310may output a count signal in a time interval which is determined in advance (or predetermined) using a timer. In some embodiments, the time counter310may output a count signal in a predetermined time interval based on a clock signal. The time counter310may receive the clock signal from the memory controller100or use a clock signal which is internally generated by the memory device300. For example, when the clock signal is toggled a predetermined number of times (e.g., as many as the predetermined number of times), the time counter310may output the count signal.

The use history circuit320may manage an operating time based on the count signal of the time counter310. For example, the use history circuit320may include a counter circuit and may increase the counter circuit in response to the count signal. A value of the counter circuit represents an operating time. Incrementing the value of the counter circuit by one may indicate an increase of one unit in the operating time of the memory device300.

The use history circuit320may encrypt and store the operating time. For example, the use history circuit320may be implemented as a non-volatile memory. The use history circuit320may encrypt the operating time using the encryption circuit330. The use history circuit320may transmit the encryption code stored in the ROM340to the encryption circuit330. According to some embodiments, the encryption circuit330may directly use the encryption code stored in the ROM340. For example, the encryption circuit330may use a Rivest Shamir Adleman (RSA) algorithm or a Caesar cipher algorithm.

When the use history circuit320receives a count signal from the time counter310, the use history circuit may decrypt the encrypted and stored operating time. The use history circuit320may decrypt the encrypted operating time using the decryption circuit335. The use history circuit320may transmit the decryption code stored in the ROM340to the decryption circuit335. According to some embodiments, the decryption circuit335may directly use the decryption code stored in the ROM340. Each memory device300may have a different encryption code and decryption code stored in the ROM340therein. The use history circuit320may increase the decrypted operating time by one (e.g., one unit) in response to the count signal. The use history circuit320may again encrypt and store the updated operating time using the encryption circuit330.

Further, when the use history circuit320receives an operating time request command from the memory controller100, the use history circuit320may decrypt the encrypted and stored operating time. The use history circuit320may decrypt the encrypted operating time using the decryption circuit335. The use history circuit320may transmit the decryption code stored in the ROM340to the decryption circuit335. According to some embodiments, the decryption circuit335may directly use the decryption code stored in the ROM340. The use history circuit320may transmit the decrypted operating time to the memory controller100. The memory controller100may determine or set a level of the memory device300based on the operating time. The memory controller100may determine an operation mode of the memory device300according to the determined or set level of the memory device300.

The use history circuit320may generate a validation value based on the operating time. For example, the use history circuit320may generate the validation value using the operating time, a serial number, and a code. A manufacturer may assign a one-to-one corresponding (or respective) serial number to every use history circuit of memory devices300and may generate and manage a code table for the code, which may be generated according to the serial number.

In some embodiments, the use history circuit320may generate a validation value using Equation 1.
Validation=(counter+serial number)% code  (Equation 1)

Here, Validation represents a validation value, the counter represents a value of the counter circuit (that is, an indicator of the operating time of the memory device300) of the use history circuit320, the serial number represents a number which respectively corresponds to the use history circuit320, the code is associated with the serial number and is determined in advance by the manufacturer of the memory device300, and % may represent a remainder operation (that is, a modular operation).

In some embodiments, the use history circuit320may generate a validation value using Equation 2.
Validation=(counter+f(serial number))% code  (Equation 2)

Here, Validation represents a validation value, the counter represents a value of the counter circuit (that is, an indicator of the operating time of the memory device300) of the use history circuit320, the serial number represents a number which respectively corresponds to the use history circuit320, f represents a function for transforming a serial number, the code is associated with the serial number and is determined in advance by the manufacturer of the memory device300, and % may represent a remainder operation. For example, the function f may be a function which converts a serial number into bits and then shuffles it.

In some embodiments, the use history circuit320may generate the validation value using Equation 3.
Validation=(f1(counter)+f2(serial number))% code  (Equation 3)

Here, Validation represents a validation value, the counter represents a value of the counter circuit (that is, an indicator of the operating time of the memory device300) of the use history circuit320, the serial number represents a number which respectively corresponds to the use history circuit320, f1represents a function for transforming the value of the counter circuit and f2represents a function for transforming the serial number, the code is associated with the serial number and is determined in advance by the manufacturer of the memory device300, and % may represent a remainder operation.

The use history circuit320may encrypt and store the validation value. The use history circuit320may encrypt the validation value using the encryption circuit330. The use history circuit320may transmit the encryption code stored in the ROM340to the encryption circuit330. According to some embodiments, the encryption circuit330may directly use the encryption code stored in the ROM340. For example, the encryption circuit330may use the RSA algorithm and Caesar cipher algorithm.

When the use history circuit320receives a validation value request command from the memory controller100, the use history circuit may decrypt the encrypted and stored validation value. The use history circuit320may decrypt the encrypted validation value using the decryption circuit335. The use history circuit320may transmit the decryption code stored in the ROM340to the decryption circuit335. According to some embodiments, the decryption circuit335may directly use the decryption code stored in the ROM340. The use history circuit320may transmit the decrypted validation value to the memory controller100.

The memory controller100may calculate the validation value using the decrypted operating time. The memory controller100may calculate the validation value using a method (e.g., one of Equations 1-3) used by the use history circuit320to generate the validation value. The memory controller100may determine or compare whether the validation value calculated by the memory controller100matches with the decrypted validation value received from the use history circuit320. If it is determined that the validation values match, the memory controller100may determine or set the level of the memory device300based on the decrypted operating time. If it is determined that the validation values do not match, the memory controller100may determine or set the level of the memory device300as a lowest level. When the validation values do not match, it may indicate that there has been a hacking attempt.

The cell350may perform refresh operations, store operations (e.g., writes), transmit operations (e.g., reads), and/or erase operations on data according to the commands of the memory controller100. The cell350may operate separately from the time counter310and the use history circuit320.

InFIG.2, it is illustrated that the memory device300has a time counter310, a use history circuit320, an encryption circuit330, a decryption circuit335, a ROM340, and a cell350, but it and the present disclosure are not limited thereto. Therefore, it should be understood that the memory device300may include a command decoder, a row decoder, a column decoder, and a refresh circuit for the operation of the cell350, which are not shown inFIG.2. For example, the command decoder may receive an instruction from a memory controller (e.g., memory controller100ofFIG.1), where the instruction is according to an operation mode that is determined by the memory controller based on the operating time and the validation value of the memory device300.

FIG.3is a schematic block diagram of a memory device according to some examples of embodiments.

Referring toFIG.3, a memory device400according to some embodiments may manage a use history about commands, and may include a command decoder405, a command counter410, a use history circuit420, an encryption circuit430, a decryption circuit435, a ROM440, and a cell450. The use history about commands may refer to a number of commands processed by the memory device400(hereinafter, referred to as a processed command number). The memory device400may be used as the memory device200ofFIG.1.

The command decoder405may decode the command received from the memory controller100. For example, the command may include one or more of a chip selection signal, a clock enable signal, an address strobe signal, a refresh signal, a data read-out signal, a data write signal, and a data erase signal, but the present disclosure is not limited thereto. The memory device400may operate with respect to the cell450according to the command which is decoded by the command decoder405, and to this end, the memory device400may further include a row decoder, a column decoder, and a refresh circuit (not shown inFIG.4). The command decoder405may output the decoded command to the command counter410.

If the decoded command is a read command or a write command (or includes at least one of a read command or a write command), the command counter410may output the count signal to the use history circuit420. In some embodiments, the command counter410is configured to output the count signal when the command counter receives the read command. In some embodiments, the command counter410is configured to output the count signal when the command counter receives the write command. In some embodiments, the command counter is configured to output the count signal when the command counter receives the read command or the write command.

The use history circuit420may manage the processed command number based on the count signal of the command counter410. For example, the use history circuit420may include a counter circuit and may increase the counter circuit in response to the count signal. The value of the counter circuit may represent the processed command number. Incrementing the value of the counter circuit by one may indicate an additional performance of one or more commands (e.g., read commands, write commands) by the memory device400.

The use history circuit420may encrypt and store the processed command number. For example, the use history circuit420may be implemented by a non-volatile memory. The use history circuit420may encrypt the processed command number using the encryption circuit430. The use history circuit420may transmit the encryption code stored in the ROM440to the encryption circuit430. According to some embodiments, the encryption circuit430may directly use the encryption code stored in the ROM440. For example, the encryption circuit430uses a Rivest Shamir Adleman (RSA) algorithm or a Caesar cipher algorithm.

When the use history circuit420receives a count signal from the command counter410, the use history circuit may decrypt the encrypted and stored processed command number. The use history circuit420may decrypt the encrypted processed command number using the decryption circuit435. The use history circuit420may transmit the decryption code stored in the ROM440to the decryption circuit435. According to some embodiments, the decryption circuit435may directly use the decryption code stored in the ROM440. Each memory device400may have a different encryption code and decryption code stored in the ROM440therein. The use history circuit420may increase the decrypted processed command number by one in response to the count signal. The use history circuit420may again encrypt and store the updated processed command number using the encryption circuit430.

Further, when the use history circuit420receives a processed command number request command from the memory controller100, the use history circuit420may decrypt the encrypted and stored processed command number. The use history circuit420may decrypt the encrypted processed command number using the decryption circuit435. The use history circuit420may transmit the decryption code stored in the ROM440to the decryption circuit435. According to some embodiments, the decryption circuit435may directly use the decryption code stored in the ROM440. The use history circuit420may transmit the decrypted processed command number to the memory controller100. The memory controller100may determine or set a level of the memory device400based on the processed command number. The memory controller100may determine an operation mode of the memory device400according to the level of the memory device400.

The use history circuit420may generate a validation value based on the processed command number. For example, the use history circuit420may generate the validation value using the processed command number, a serial number, and a code.

In some embodiments, the use history circuit420may generate a validation value using Equation 4.
Validation=(counter+serial number)% code  (Equation 4)

Here, Validation represents a validation value, the counter represents a value of the counter circuit (that is, an indicator of the processed command number of the memory device400) of the use history circuit420, the serial number represents a number which respectively corresponds to the use history circuit420, the code is associated with the serial number and is determined in advance by the manufacturer of the memory device400, and % may represent a remainder operation.

In some embodiments, the use history circuit420generates a validation value using Equation 5.
Validation=(counter+f(serial number))% code  (Equation 5)

Here, Validation represents a validation value, the counter represents a value of the counter circuit (that is, an indicator of the processed command number of the memory device400) of the use history circuit420, the serial number represents a number which respectively corresponds to the use history circuit420, f represents a function for transforming a serial number, the code is associated with the serial number and is determined in advance by the manufacturer of the memory device400, and % may represent a remainder operation. For example, the function f may be a function which converts a serial number into bits and then shuffles it.

In some embodiments, the use history circuit420generates the validation value using Equation 6.
Validation=(f1(counter)+f2(serial number))% code  (Equation 6)

Here, Validation represents a validation value, the counter represents a value of the counter circuit (that is, an indicator of the processed command number of the memory device400) of the use history circuit420, the serial number represents a number which respectively corresponds to the use history circuit420, f1represents a function for transforming the value of the counter circuit and f2represents a function for transforming the serial number, the code is associated with the serial number and is determined in advance by the manufacturer of the memory device400, and % may represent a remainder operation.

The use history circuit420may encrypt and store the validation value. The use history circuit420may encrypt the validation value using the encryption circuit430. The use history circuit420may transmit the encryption code stored in the ROM440to the encryption circuit430. According to some embodiments, the encryption circuit430may directly use the encryption code stored in the ROM440. For example, the encryption circuit430may use the RSA algorithm and Caesar cipher algorithm.

When the use history circuit420receives a validation value request command from the memory controller100, the use history circuit may decrypt the encrypted and stored validation value. The use history circuit420may decrypt the encrypted validation value using the decryption circuit435. The use history circuit420may transmit the decryption code stored in the ROM440to the decryption circuit435. According to some embodiments, the decryption circuit435may directly use the decryption code stored in the ROM440. The use history circuit420may transmit the decrypted validation value to the memory controller100.

The memory controller100may calculate a validation value using the decrypted processed command number. The memory controller100may calculate the validation value using a method (e.g., one of Equations 4-6) used by the use history circuit420to generate the validation value. The memory controller100may determine or compare whether the validation value calculated by the memory controller100matches with the decrypted validation value received from the use history circuit420. If it is determined that the validation values match, the memory controller100may determine or set the level of the memory device400based on the decrypted processed command number. If it is determined that the validation values do not match, the memory controller100may determine or set the level of the memory device400as a lowest level. When the validation values do not match, it may indicate that there has been a hacking attempt.

The cell450may perform refresh operations, store operations, transmit operations, and/or erase operations on data according to the commands of the memory controller100. In some embodiments, the command decoder405may receive an instruction from a memory controller (e.g., memory controller100ofFIG.1), where the instruction is according to an operation mode that is determined by the memory controller based on the number of processed commands and the validation value of the memory device400.

FIG.4is a schematic block diagram of a memory device according to some examples of embodiments.

Referring toFIG.4, a memory device500according to some embodiments may manage a use history about commands, and may include a command decoder505, a command counter510, a buffer515, a use history circuit520, an encryption circuit530, a decryption circuit535, a ROM540, and a cell550. The use history about commands may refer to a number of commands processed by the memory device500(hereinafter, referred to as a processed command number). The memory device500may be used as the memory device200ofFIG.1.

The same description of the command decoder405, the command counter410, the user history circuit420, the encryption circuit430, the decryption circuit435, the ROM440, and the cell450ofFIG.3may be applied in the same way to the command decoder505, the command counter510, the user history circuit520, the encryption circuit530, the decryption circuit535, the ROM540, and the cell550ofFIG.4. Accordingly, inFIG.4, the buffer515and the command counter510and the use history circuit520connected to the buffer515will be mainly described.

If a command decoded by the command decoder505is at least one of a read command and a write command, the command counter510outputs a first count signal to the buffer515. In some embodiments, the command counter510is configured to output a first count signal when the command counter receives the read command. In some embodiments, the command counter510is configured to output the first count signal when the command counter receives the write command. In some embodiments, the command counter is configured to output the first count signal when the command counter receives the read command or the write command.

If the buffer515receives a predetermined number of first count signals, the use history circuit520may output a second count signal. For example, the predetermined number may be implemented as 100, 1000, or 10000, but is not necessarily limited thereto.

The use history circuit520may manage the processed command number based on the second count signal. For example, the use history circuit520may include a counter circuit and may increase the counter circuit in response to the second count signal. A value obtained by multiplying a value of the counter circuit with a predetermined number (e.g., the predetermined number used by the buffer515) may represent a processed command number. The same description for the use history circuit420ofFIG.3may be applied in the same way to the configuration of the use history circuit520ofFIG.4for generating, encrypting, storing, and decrypting the processed command number and the validation value.

FIG.5is a schematic block diagram of a memory device according to some examples of embodiments.

Referring toFIG.5, a memory device600according to some embodiments may manage a use history and may include a command decoder605, a time counter610, a command counter615, a use history circuit620, an encryption circuit630, a decryption circuit635, a ROM640, and a cell650. The use history may include an operating time and a processed command number. The memory device600may be used as the memory device200ofFIG.1.

The description of the command decoder405, the command counter410, the encryption circuit430, the decryption circuit435, the ROM440, and the cell450ofFIG.3may be applied in the same way to the command decoder605, the command counter615, the encryption circuit630, the decryption circuit635, the ROM640, and the cell650ofFIG.5. Further, the description of the time counter310ofFIG.2may be applied in the same way to the description of the time counter610ofFIG.5.

Accordingly, inFIG.5, the use history circuit620and the time counter610and the command counter615connected to the use history circuit620will be mainly described. The use history circuit620may manage an operating time, a first validation value for the operating time, a processed command number, and a second validation value for the processed command number. The use history circuit620may include a first counter circuit for managing the operating time and a second counter circuit for managing a processed command number.

The time counter610may output a third count signal to the use history circuit620in a predetermined time interval. In some embodiments, the time counter610may output the third count signal in a predetermined time interval using a timer. In some embodiments, the time counter610may output the third count signal in a predetermined time interval based on a clock signal. The time counter610may receive a clock signal from the memory controller100or use a clock signal which is internally generated by the memory device600. For example, when the clock signal is toggled a predetermined number of times (e.g., as many as a predetermined number of times), the time counter610may output the count signal.

The use history circuit620may manage an operating time based on the third count signal of the time counter610. For example, the use history circuit620may increase the first counter circuit in response to the third count signal. A value of the first counter circuit represents an operating time. Incrementing the value of the first counter circuit by one may indicate an increase of one unit in the operating time of the memory device300.

If a command decoded by the command decoder605is at least one of a read command and a write command, the command counter615may output a fourth count signal to the use history circuit620. In some embodiments, the command counter615is configured to output the fourth count signal when the command counter receives the read command. In some embodiments, the command counter615is configured to output the fourth count signal when the command counter receives the write command. In some embodiments, the command counter615is configured to output the fourth count signal when the command counter receives the read command or the write command.

The use history circuit620may manage the processed command number based on the fourth count signal of the command counter615. For example, the use history circuit620may increase the second counter circuit in response to the fourth count signal. The value of the second counter circuit may represent the processed command number. Incrementing the value of the second counter circuit by one may indicate an additional performance of one or more commands (e.g., read commands, write commands) by the memory device400.

According to some embodiments, the memory device600may be implemented to further include a buffer between the command counter615and the use history circuit620. The buffer may be similar to the buffer515ofFIG.4, and may be configured to output a fifth count signal to the user history circuit620when a predetermined number of fourth count signals from the command counter615is received. The use history circuit620may increase the second counter circuit in response to the fifth count signal.

The use history circuit620may encrypt and store the operating time and the processed command number.

The use history circuit620may generate a first validation value based on the operating time and generate a second validation value based on the processed command number. The use history circuit620may generate the first validation value and the second validation value using at least one of the above-described Equations 1 to 6.

The use history circuit620may encrypt and store the first validation value and the second validation value.

The use history circuit620may encrypt or decrypt the operating time, the processed command number, the first verification value, and the second verification value using the encryption circuit630and the decryption circuit635. When the encryption circuit630performs the encryption, an encryption code stored in the ROM640may be used. When the decryption circuit635performs the decryption, a decryption code stored in the ROM640may be used.

FIG.6illustrates a flowchart of a method for managing a use history according to some examples of embodiments.

Referring toFIG.6, the method for managing a use history according to some embodiments may be applied to the memory device. The memory device may include a use history circuit which manages the use history.

When the use history circuit according to some embodiments receives a count signal, the use history circuit may obtain the use history in step S610. The use history circuit may encrypt and store the use history. When the use history circuit receives the count signal, the use history circuit may decrypt the encrypted and stored use history to obtain the use history. The use history circuit may perform the encryption and the decryption using the encryption circuit and the decryption circuit. The use history circuit may use an encryption code and a decryption code stored in the ROM of the memory device. The use history may be at least one of the operating time of the memory device and a number of commands processed by the memory device. When the use history is the operating time, the use history circuit may receive a count signal in a predetermined time interval. When the use history is a processed command number, the use history circuit may receive the count signal based on commands received from the memory controller. For example, when the command received from the memory controller is at least one of the read command and the write command, the use history circuit may receive a count signal. The count signal may indicate one or more units of operating time and/or one or more commands have been performed by the memory device.

The use history circuit may update, encrypt, and store the decrypted use history in step S620. The use history circuit may update the decrypted use history by increasing a value of the counter circuit by 1. The use history circuit may encrypt and store again the updated use history.

The use history circuit may generate the validation value based on the updated use history S630. For example, the use history circuit may generate the validation value using the updated use history, a serial number of the use history circuit, and a manufacturer code associated with the serial number. A manufacturer may assigns a one-to-one corresponding (e.g., respectively corresponding) serial number to every use history circuit of the memory devices, and may generate and manage a code table for the code which is generated according to the serial number.

The use history circuit may encrypt and store the validation value in step S640. An encryption algorithm used to encrypt the use history and an encryption algorithm used to encrypt the validation value may be the same, or may be different. The use history and the validation value may be used to determine an operation mode of the memory device by another element outside the memory device.

FIG.7is a block diagram illustrating a computer system according to some examples of embodiments.

Referring toFIG.7, the computer system700includes a host710, a memory720, at least one compute eXpress link (CXL) device750, and a CXL interface740. At least one CXL device750includes first to n-th CXL devices (750_1-750_n; n is a natural number of 1 or larger). In some embodiments, the computer system700may be included in user devices such as a personal computer (PC), a laptop computer, a server, a media player, or a digital camera, or an automotive device such as a navigation, a black box, or an automotive electronic device. In some embodiments, the computer system700may be a mobile system such as a portable communication terminal (mobile phone), a smart phone, a tablet personal computer (tablet PC), a wearable device, a healthcare device, or an internet of things (IOT) device.

The host710may control the overall operation of the computer system700. In some embodiments, the host710may one of various processors such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a data processing unit (DPU). In some embodiments, the host710may include a signal core processor or a multi-core processor.

In some embodiments, at least one CXL device750operates as a cache buffer of the host710. That is, the host710may use the memories753_1to753_nof at least one of the CXL device750as a cache buffer.

The host710may generate a signal for at least one CXL device750and/or the memory720. The signal may include a command and an address. In some embodiments, commands may include commands such as write commands or read commands. In some embodiments, the command may include activation instructions, and read/write instructions. In some embodiments, the command may further include a precharge instruction.

An activation instruction may be an instruction which switches a target row of the memories753_1to753_nof at least one CXL device750to an active state to write data in at least one CXL device750or read data from the at least one CXL device750. Alternatively, the activation instruction may be an instruction which switches the target row in the memory720to an active state to write data in the memory720or read data from the memory720. The at least one CXL device750and/or the memory720may activate (for example, drive) a memory cell of the target row in response to the activation instruction. The read/write instruction may be an instruction which performs a read or write operation in the target memory cell of the row which is switched to the active state.

The memory720may be used as a main memory or a system memory of the computer system700. In some embodiments, the memory720may be a dynamic random access memory (DRAM) device or may have a form factor of a dual in-line memory module (DIMM). However, the present disclosure is not limited thereto and the memory720may include a non-volatile memory such as a flash memory, a PRAM, a RRAM, or an MRAM.

In some embodiments, the host710may be directly connected to the memory720. In some embodiments, the memory720may communicate directly with the host710via a DDR interface. In some embodiments, the host710may include a memory controller configured to control the memory720. However, the present disclosure is not limited thereto and the memory720may communicate with the host710via various interfaces.

The at least one CXL device750may include CXL controllers751_1to751_nand memories753_1to753_n. Each CXL device750may include a respective CXL controller751and memory753. In some embodiments, the memories753_1to753_nmay operate as cache buffers of at least one CXL device750. That is, at least one CXL device750may use each memory753_1to753_nas a cache buffer.

The CXL controllers751_1to751_nmay include an intellectual property (IP) circuit designed to implement an application specific integrated circuit (ASIC) and/or a field programmable gate array (FPGA). In some embodiments, the CXL controllers751_1to751_nmay be implemented to support the CXL protocol (for example, a CXL 2.0 protocol or other arbitrary version). The CXL controller751_1to751_nmay convert CXL packets and signals of the memory interface of the memory720.

In some embodiments, at least one CXL device750may be implemented by an individual memory device or memory module. At least one CXL device750may be connected to the CXL interface740through different physical ports. That is, at least one CXL device750is connected to the CXL interface740so that a memory area managed by the host710may be highly capacitive and/or has a large capacity.

The memories753_1to753_nmay include one of a dynamic random access memory (DRAM), a Not-AND NAND flash, a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an optane DIMM, a non-volatile DIMM (NVMDIMM), a double data Rate synchronous DRAM (DDR SDRAM), or a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), or a combination thereof.

In some embodiments, the host710and at least one CXL device750may be configured to share the same interface. For example, the host710and at least one CXL device750may communicate with each other via the CXL interface740. In some embodiments, the CXL interface (compute link interface)740may indicate a low latency and high bandwidth link which supports the coherency, memory access, and dynamic protocol multiplexing of the input/output protocol (10 protocol) to enable various connections between accelerators, memory devices, and various electronic devices.

InFIG.7, even though it has been described that the host710and the at least one CXL device750communicate with each other via the CXL interface740, the present disclosure is not necessarily limited thereto. For example, the host710and at least one CXL device750may communicate with each other based on various computing interfaces, such as a GEN-Z protocol, a NVLink protocol, a CCIX protocol, or an open CAPI protocol, as non-limiting examples.

FIG.8is a block diagram illustrating a computer system according to some examples of embodiments.

Referring toFIG.8, a computer system1000may include a first CPU1010a, a second CPU1010b, a GPU1030, an NPU1040, a CXL switch1015, a CXL memory1050, a CXL storage1052, a PCIe device1054, and an accelerator (CXL device)1056.

The first CPU1010a, the second CPU1010b, the GPU1030, the NPU1040, the CXL memory1050, the CXL storage1052, the PCIe device1054, and the accelerator1056may be commonly connected to the CXL switch1015and communicate with each other through the CXL switch1015.

In some embodiments, the first CPU1010a, the second CPU1010b, the GPU1030, and the NPU1040may be hosts which have been described with reference toFIGS.1to7, and may be directly connected to the individual memories1020a,1020b,1020c,1020d, and1020e.

In some embodiments, the CXL memory1050and the CXL storage1052may be CXL devices which have been described with reference toFIGS.1to7, and at least partial area of the memories1060aand1060bof the CXL memory1050and the CXL storage1052may be allocated as at least one cache buffer of the first CPU1010a, the second CPU1010b, the GPU1030, the NPU1040, the CXL memory1050, the CXL storage1052, the PCIe device1054, and the accelerator1056by at least one or more of the first CPU1010a, the second CPU1010b, the GPU1030, and the NPU1040.

In some embodiments, the CXL switch1015may be connected to the PCIe device1054and/or the accelerator1056, which may be configured to support various functions. The PCIe device1054or the accelerator1056may communicate with the first CPU1010a, the second CPU1010b, the GPU1030, and/or the NPU1040via the CXL switch1015and/or access the CXL memory1050and the CXL storage1052.

In some embodiments, the CXL switch1015may be connected to an external network1060or a fabric, and may be configured to communicate with an external server via the external network1060or the fabric.

FIG.9is a block diagram illustrating a server system according to some examples of embodiments.

Referring toFIG.9, a data center1100may be a facility which collects various data and provides services and may also be referred to as a data storage center. For example, the data center1100may be a system for operating a search engine or database, and/or may be a computer system used in enterprises such as banks or government agencies. The data center1100may include application servers1110a, . . . ,1110hand storage servers1120a, . . . ,1120h. A number of application servers1110and a number of storage servers1120may be selected in various ways and the number of application servers1110and the number of storage servers1120may be different.

Hereinafter, a configuration of the first storage server1120awill be mainly described. Application servers1110a, . . . ,1110hand storage servers1120a, . . . ,1120hmay have similar structures and the application servers1110a, . . . ,1110hand the storage servers1120a, . . . ,1120hmay communicate with each other via a network NI.

The first storage server1120amay include a processor1121, a memory1122, a switch1123, a storage1125, a CXL memory1124, and a network interface card (NIC)2216. The processor1121may control an overall operation of the first storage server1120aand may access the memory1122to execute instructions loaded in the memory1122and/or process data. The processor1121and the memory1122may be directly connected and a number of processors1121and a number of memories1122included in one storage server1120amay be selected and configured in various ways.

In some embodiments, the processor1121and the memory1122may provide a processor-memory pair. In some embodiments, the number of processors1121and the number of memories1122may be different. The processor1121may include a single core processor or a multi-core processor. The detailed description of the storage server1120may be applied to the application servers1110a, . . . ,1110hin a similar way.

The switch1123may be configured to relay or route communications between various configurations and components included in the first storage server1120a. In some embodiments, the switch1123may be a CXL switch described with reference toFIG.8. That is, the switch1123may be a switch implemented based on the CXL protocol.

The CXL memory1124and the storage device1125may be CXL devices which have been described with reference toFIGS.7and8.

The CXL memory1124may be connected to the switch1123. The storage device1125may include a CXL interface circuit (CXL IF), a controller (CTRL), and a NAND flash. The storage device1125may store data and/or output stored data according to the request of the processor1121.

In some embodiments, the application servers1110a, . . . ,1110hmay not include the storage device1125.

The network interface card (NIC)1126may be connected to the CXL switch1123. The NIC1126may communicate with other storage servers1120a, . . . ,1120hor other application servers1110a, . . . ,1110hvia the network NI.

In some embodiments, the NIC1126may include a network interface card or a network adaptor. The NIC1126may be connected to the network NI by a wired interface, a wireless interface, a Bluetooth interface, and an optical interface. The NIC1126may include an internal memory, a digital signal processor (DSP), and a host bus interface and may be connected to the processor1121and/or the switch1123via the host bus interface. In some embodiments, the NIC1126may be integrated with at least one of the processor1121, the switch1123, and the storage device1125.

In some embodiments, the network (NI) may be implemented using a fibre channel (FC) or Ethernet. FC may be a medium which is used for relatively higher speed data transfer and may use an optical switch, which may provide high performance/high applicability. According to the access method of the network (NI), the storage servers1120a, . . . ,1120hmay be provided as a file storage, a block storage, or an object storage.

In some embodiments, the network (NI) may be a storage exclusive network such as a storage area network (SAN). For example, the SAN may be a FC-SAN which uses a FC network and is implemented according to a FC protocol (FCP). As another example, the SAN may be IP-SAN which uses a TCP/IP network and is implemented according to SCSI over TCP/IP or internet SCSI (iSCSI) protocol. In some embodiments, the network (NI) may be a general network such as a TCP/IP network. For example, the network (NI) may be implemented according to a protocol such as a FC over Ethernet (FCoE), a network attached storage (NAS), or a NVMe over Fabrics (NVMe-oF).

In some embodiments, at least one of the application servers1110a, . . . ,1110hmay provide data which is requested by a user or a client to be stored in one of storage servers1120a, . . .1120hthrough the network NI. At least one of application servers1110a, . . . ,1110hmay obtain data which is requested by the user or the client to be read from one of the storage servers1120a, . . . ,1120hthrough the network NI. For example, at least one of the application servers1110a, . . . ,1110hmay be implemented by a web server or a database management system (DBMS).

In some embodiments, at least one of the application servers1110a, . . . ,1110hmay access the memory, the CXL memory, or the storage device included in another application server through the network NI or access the memories, the CXL memories, or the storage devices included in the storage servers1120a, . . . ,1120hthrough the network NI. By doing this, at least one of the application servers1110a, . . . ,1110hmay perform various operations on data stored in the another application servers1110a, . . . ,1110hand/or the storage servers1120a, . . . ,1120h. For example, at least one of the application servers1110a, . . . ,1110hmay execute an instruction to move or copy data between the other application servers1110a, . . . ,1110hand/or storage servers1120a, . . . ,1120h. The data may move from the storage device of the storage servers1120a, . . . ,1120hto the memory or the CXL memory of the application servers1110a, . . . ,1110hdirectly or via the memories or CXL memories of the storage servers1120a, . . . ,1120h. Data which moves through the network NI may be encrypted data for the purpose of security or privacy.

In some embodiments, each constituent element or a combination of two or more constituent elements which have been described with reference toFIGS.1to9may be implemented by a digital circuit, a programmable or non-programmable logic device, an array, or an application specific integrated circuit (ASIC).

While the inventive concepts have been described in connection with what is presently considered to be practical examples of embodiments, it is to be understood that the inventive concepts are not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.