Apparatus for time to digital conversion

A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

FIELD

The embodiments described herein relate generally to a time-to-digital converter device and associated methodology for improved measurement accuracy and resolution.

BACKGROUND

A commercial gamma ray detector includes an array of scintillator crystals coupled to a transparent light guide, which distributes scintillation light over an array of photomultiplier tubes (PMTs) arranged over the transparent light guide. Signals from the PMTs in a same area are generally summed in the analog domain, and then timing is measured based on the leading edge of the summed signal, or event.

A Time-to-Digital-Converter (TDC) is often used to measure timing in a gamma ray detector. A TDC accurately converts the realization of an event into a number than can be related to the time the event occurred. Various methods exist to perform this task. Amongst others, counting a large number of very fast logic transitions between coarse clock cycles has been used to perform this task. In some cases, it may be desirable to indicate the occurrence of a series of events known to be generated sequentially. For instance, time marks a rising signal takes to reach a pre-determined set of threshold values can be very useful information.

Time-to-digital converters (TDCs) have also been implemented with a variety of architectures. A first conventional architecture is a classic delay chain having a single chain of identical delay elements connected in series. The classic delay chain also includes a set of single bit memory elements, each connected to an output of one of the delay elements. A start signal is supplied to the input of the chain of delay elements to indicate a beginning of the time period to be measured. The start signal propagates through the chain of delay elements. The end of the time period to be measured is indicated by a stop signal that is simultaneously provided to the clock inputs of all of the memory elements in order to capture the position of the propagated start signal within the chain of delay elements. The captured position is then thermometer-decoded to compute the delay between the start and stop signals, and this delay is used to compute the length of the time period to be measured as a multiple of the delay imparted by each of the delay elements.

Therefore, the resolution of the classic delay chain is limited to the time-delay of each delay element in the delay chain. For example, if each delay element in the chain imparts a delay of “tu”, then the resolution of the classic delay chain is “tu”. As such, in a physical implementation of the classic delay chain, such as in a semiconductor device, the minimum value of tuis limited by the physical properties of the semiconductor. As sampling is performed at the same point in time for each delay element in the classic delay chain, the physical limitations on the delay tugive rise to the limits of measurement resolution.

Another conventional delay chain is the Vernier delay chain. As in the classic delay chain, the Vernier delay chain includes a chain of identical delay elements connected in series and a set of single bit memory elements, each connected to the output of one of the delay elements. However, the Vernier delay chain also includes a second delay chain of identical delay elements connected in series. The output of each of the delay elements in the second delay chain is connected to a clock input of one of the memory elements. Further, the delays elements in the first delay chain each impart a delay of tu, and the delay elements of the second delay chain each impart a delay of tc, where tc<tu.

In operation, the start signal is supplied to the first delay chain of the Vernier delay chain, and the stop signal is supplied to the second delay chain. As the delay imparted by the elements of the second delay chain is less than that of the elements of the first delay chain, the stop signal will eventually overtake the start signal. When the stop signal overtakes the start signal, the propagation of the start signal in the first delay chain is captured by the memory elements and thermometer-decoded to determine the time interval between the start and stop signals. The time period to be measured is then calculated as a multiple of the difference between the delays of the first delay chain and the delays of the second delay chain, or tu−tc.

As with the classic delay chain, the delays in the Vernier delay chain are limited by the physical properties of the semiconductor device on which it is implemented. Therefore, there is a minimum delay difference (tu−tc) (i.e. resolution) that can be achieved using the Vernier delay chain. Thus, it is difficult to make precise time period measurements using the Vernier delay chain.

Accordingly, a need exists for an apparatus and associated methodology that improves upon the limitations of the classic and Vernier delay chains, and that achieves improved accuracy and resolution.

DETAILED DESCRIPTION

In general, time-to-digital converter device according to exemplary embodiments of the present advancements includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views,FIG. 1is a schematic drawing of a time-to-digital converter device according to an exemplary embodiment of the present advancements. InFIG. 1, multiple delay chains15. . . N are connected to terminal11to receive a start signal, and to terminal12to receive a stop signal. Clock inputs15b,16b. . . Nb of delay chains15,16. . . N are directly connected to terminal12, but only delay chain15is directly connected to terminal11. Delay chain16is connected to terminal11via delay element13, and delay chain N is connected to terminal11via delay elements13through n. The outputs of delay chains15,16. . . N are connected to combiner18, which generates an overall output of the time-to-digital converter device and provides the overall output to terminal19.

Further, inFIG. 1, each delay chain15,16. . . N have a substantially similar structure and a similar resolution, as will be described in detail below. Delay elements13. . . n provide substantially the same delay amount as a function of the resolution of delay chains15,16. . . N. For example, if each delay chain has a resolution of “R”, each delay element13. . . n provides a delay amount of R/N, and as a result, the overall resolution of the time-to-digital converter device is R/N.

As one of ordinary skill in the art would recognize, the time-to-digital converter device ofFIG. 1may include any number of delay chains15,16. . . N, and a corresponding number of delay elements13. . . n. Further, combiner18may be a single combiner with sufficient inputs to accommodate all delay chains15,16. . . N included in the time-to-digital converter, or may be implemented as a series of cascaded combiners, which in the aggregate have sufficient inputs to accommodate all of the delay chains15,16. . . N. Combiner18may also combine the outputs of delay chains15,16. . . N by addition or may average the outputs of delay chains15,16. . . N. Any other combination of outputs of delay chains15,16. . . N in combiner18is also possible as one of ordinary skill in the art would recognize.

The time-to-digital converter device ofFIG. 1may be implemented as discrete logic gates, as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Complex Programmable Logic Device (CPLD). An FPGA or CPLD implementation, the time-to-digital converter may be coded in VHDL, Verilog or any other hardware description language as a set of computer-readable instructions, and the computer-readable instructions may be stored in electronic memory directly in the FPGA or CPLD, or as separate electronic memory. Further, the electronic memory may be non-volatile, such as a ROM, EPROM, EEPROM or FLASH memory. The electronic memory may also be volatile, such as static or dynamic RAM, and a processor, such as a microcontroller or microprocessor, may be provided to manage the electronic memory as well as the interaction between the FPGA or CPLD and the electronic memory.

FIG. 2is a schematic diagram of an exemplary delay chain structure for delay chains15,16. . . N. InFIG. 2, a plurality of delay chain elements203. . .210are connected in series with terminal201. Each of the delay chain elements203. . .210impart the same delay, for example, a delay tu. A single-bit memory element211. . .218is connected to the output of each one of the delay chain elements203. . .210, and the clock inputs of the memory elements are connected in common to terminal202. The outputs of the memory elements211. . .218are connected to a thermometer decoder circuit219whose output corresponds to the output of the delay chain.

Though eight delay chain elements203. . .210are shown inFIG. 2, one of ordinary skill in the art would recognize that a delay chain having more than eight delay chain elements or fewer than eight delay chain elements are possible without departing from the scope of the present advancements. In addition, though positive logic elements are shown inFIG. 2, one of ordinary skill in the art would recognize as being within the scope of the present advancements an implementation of the delay chain ofFIG. 2using negative logic elements. Further, as thermometer circuits are known, a description of the thermometer circuit219is omitted for the sake of brevity.

In operation, the start signal is provided to the terminal201ofFIG. 2at the start of the time period to be measured. The start signal then propagates through the delay chain elements203. . .210, where each delay element delays the start signal by tu. A stop signal indicating the end of the time period to be measured is applied to the clock inputs of each of the memory elements211. . .218via the terminal202. The outputs of the memory elements211. . .218are then provided to the thermometer decoder219, which generates a value indicative of the time period to be measured and provides the value to terminal220.

As one of ordinary skill in the art will recognize, propagation of the start signal through the delay chain elements203. . .210is measured at the delay boundaries. In other words, the propagated start signal is sampled at the outputs of each of the delay chain elements203. . .210. Thus, the start signal is captured after an integer number of delays tuimparted by the delay chain elements203. . .210. Fractions of tuare not measured. As such the resolution of the delay chain inFIG. 2is the delay amount imparted by each delay chain element203. . .210or tu.

FIG. 3is a schematic diagram of another exemplary delay chain structure for delay chains15,16. . . N. InFIG. 3, delay chain elements203. . .210are connected in series with terminal201, and the outputs of delay chain elements203. . .210are sampled by single-bit memory elements211. . .218. The outputs of memory elements211. . .218are connected to a thermometer decoder219. As the delay chain elements203. . .210, memory elements211. . .218and thermometer decoder219were described with reference toFIG. 2above, further description of these elements is omitted for brevity.

InFIG. 3, delay elements321. . .327are connected in series between terminal202and the clock inputs of memory elements211. . .218. Specifically, the clock input of memory element211is directly connected to terminal202, the clock input of memory element212is connected to terminal202via delay element321, the clock input of memory element213is connected to terminal202via delay element321and delay element322, and so on. Thus, the clock input of memory element218is connected to terminal202via all of the delay elements321. . .327. Each of the delay elements321. . .327inFIG. 3impart the same delay amount of tc, which is less than the delay tuimparted by delay chain elements203. . .210.

In operation, the start signal is applied to delay chain elements203. . .210via terminal201at the beginning of the time period to be measured and the stop signal is applied to the terminal202at the end of the time to be measured. The start signal propagates through the delay chain elements203. . .210, and the stop signal propagates through the delay chain elements321. . .327. As the delay of delay elements321. . .327is less than the delay of delay chain elements203. . .210, the stop signal will eventually overtake the start signal. When the propagation of the stop signal arrives at the output of delay element327, the outputs of memory elements211. . .218are provided to the thermometer decoder219, and a resulting output representative of the time period to be measured is provided to terminal220. The delay chain ofFIG. 3has a resolution of tu−tc.

As withFIG. 2, one of ordinary skill in the art will recognize that the delay chain ofFIG. 3may be implemented with fewer or more delay chain elements203. . .210and associated memory elements211. . .218and delay elements321. . .327without departing from the scope of the present advancements.

Next an exemplary implementation of the time-to-digital converter circuit will be described with reference toFIG. 4. The time-to-digital converter device ofFIG. 4includes two delay chains42and43. The delay chains42and43may both be either the delay chain ofFIG. 2or the delay chain ofFIG. 3described above. Of course, one of ordinary skill in the art will recognize that other delay chain structures are possible without departing from the scope of the present advancements.

InFIG. 4, delay chain42is directly connected to terminal11, while delay chain43is connected to terminal11via delay element40. Further, delay element40provides a delay equal to tu/2 in the event that the delay chain ofFIG. 2is used as delay chains42and43, and the delay element40provides a delay of (tu−tc)/2 in the event that the delay chain ofFIG. 3is used as delay chains42and43.

Terminal12is directly connected to the clock inputs42band43bof delay chains42and43respectively. The outputs of delay chains42and43are combined in combiner41and provided to output terminal19.

Next, the operation of the time-to-digital conversion device ofFIG. 4is described with reference to the flow chart ofFIG. 5. At step S1inFIG. 5, the start signal is applied to terminal11, which provides the start signal to delay chain42and delay element40. After the delay of delay element40has elapsed, the start signal is also provided to delay chain43. As such, the start signal propagates through delay chain42and43at an equal rate, but the start signal is delayed, or offset, in delay chain43by a delay of delay element40.

At step S2inFIG. 5, the stop signal is supplied to terminal12, and thereby to delay chains42and43simultaneously. As S3, the location of the start signal in the respective delay chains is processed as described above with respect toFIGS. 2 and 3, and each delay chain42and43provides a corresponding output to combiner41. Combiner41then combines the outputs of delay chains42and43into an overall output of the time-to-digital converter at step S4.

Next, the timing diagram ofFIG. 6will be described.FIG. 6is a timing diagram of the process described above with reference toFIGS. 4 and 5. InFIG. 6, delay chain43receives the start signal61after a delay of tu/2, while delay chain42receives the start signal61without delay. As the start signal61propagates through delay chain42, the output of each delay element b1. . . b8transitions from a “low” state to a “high” state. After the delay of tu/2 imparted by the delay element40, the start signal61bpropagates through delay chain43causing the output b9. . . b16of each of the delay chain elements therein to transition from a low to a high state.

At a predetermined time, a stop signal60is applied to stop terminal12. The stop signal60is directly applied to both delay chains42,43without delay. At time65, the stop signal causes the delay chains to “capture” the current value of each of their respective delay chain elements b1. . . b16. For example, at time65b1. . . b4are high and b5. . . b8are low in delay chain42, while b9. . . b11are high and b12. . . b16are low in delay chain43. Thus, the captured chain value for delay chain42is “11110000”, or four, and the captured value for delay chain43is “11100000” or three. The computed time difference is then the sum of these values divided by the delay imparted by delay element40.

As can be appreciated, the delay chains42,43, start signals61,61band stop signal60inFIG. 6are exemplary, and other values and configurations are possible. For example, other levels and relative timings among the signals are possible without departing from the scope of the present advancements. Likewise,FIG. 6is illustrated in positive logic wherein a larger, positive voltage indicates a logic “high” and a zero or smaller voltage indicates a logic “low.” However, negative logic, wherein a small or zero voltage denotes a logic “high” and a large, positive voltage denotes a logic “low” can also be used.

Next, a gamma ray detection system according to an exemplary embodiment of the present advancements is described with reference toFIG. 7. InFIG. 7, photomultiplier tubes135and140are arranged over light guide130, and the array of scintillation crystals105is arranged beneath the light guide130. A second array of scintillation crystals125is disposed opposite the scintillation crystals105with light guide115and photomultiplier tubes (PMTs)195and110arranged thereover.

InFIG. 7, when gamma rays are emitted from a body under test (not shown), the gamma rays travel in opposite directions, approximately 180° from each other. Gamma ray detection occurs simultaneously at scintillation crystals100and120, and a scintillation event is determined when the gamma rays are detected at scintillation crystals100and120within a predefined time limit. Thus, the gamma ray timing detection system detects gamma rays simultaneously at scintillation crystals100and120. However, for simplicity only, gamma ray detection is described relative to scintillation crystal100. One of ordinary skill in the art will recognize, however, that the description given herein with respect to scintillation crystal100is equally applicable to gamma ray detection at scintillation crystal120.

Each photomultiplier tube110,135,140and195is respectively connected to variable gain amplifiers, or VGA,150,152,154, and156. The VGAs150,152,154and156act as signal buffers and allow the acquisition system to be adjusted to accommodate variation in PMT gain, such as occurs naturally as part of the PMT manufacturing process and occurs due to aging of the PMTs. The signal output from each VGA150,152,154or156is split into two separate electronic paths.

One electronics path for is used for measuring the arrival time of the gamma ray. The signal for this path is typically formed by summing two or more signals from the same detector in a summing amplifier184or186. The act of summing multiple signals from the same detector can improve the signal to noise ratio for the timing estimate and reduce the number of required electronic components. After summing, the signal is passed to a discriminator187or188. The discriminator187or188, which typically has an adjustable threshold, produces a precisely timed electronic pulse when the summed signal passes the threshold setting. The output of the discriminator triggers a time-to-digital converter, or TDC,189and190. The TDC189or190produces a digital output which encodes the time of the discriminator pulse relative to a system clock (not shown). For a time-of-flight PET system, the TDC189or190typically produces a time stamp with an accuracy of 15 to 25 ps.

For each PMT110,135,140and195there is an independent electronics path which is used to measure the amplitude of the signal on each PMT110,135,140and195. This path consists of a filter160,162,164,166and an analog to digital converter, or ADC,176,177,178,179. The filter160,162,164or166, typically a bandpass filter, is used to optimize the signal to noise ratio of the measurement and performs an anti-aliasing function prior to conversion to a digital signal by the ADC176,177,178or179. The ADC176,177,178or179can be a free-running type, running at 100 MHz, for example, in which case the central processing unit, or CPU,170, performs a digital integration, or the ADC can be a peak-sensing type. The ADC and TDC outputs are provided to a CPU,170, for processing. The processing consists of estimating an energy and position from the ADC outputs and an arrival time from the TDC output for each event, and may include the application of a many correction steps, based on prior calibrations, to improve the accuracy of the energy, position, and time estimates.

As one of ordinary skill in the art would recognize, the CPU170can be implemented as discrete logic gates, as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Complex Programmable Logic Device (CPLD). An FPGA or CPLD implementation may be coded in VHDL, Verilog or any other hardware description language and the code may be stored in an electronic memory directly within the FPGA or CPLD, or as a separate electronic memory. Further, the electronic memory may be non-volatile, such as ROM, EPROM, EEPROM or FLASH memory. The electronic memory may also be volatile, such as static or dynamic RAM, and a processor, such as a microcontroller or microprocessor, may be provided to manage the electronic memory as well as the interaction between the FPGA or CPLD and the electronic memory.

Alternatively, the CPU170may be implemented as a set of computer-readable instructions stored in any of the above-described electronic memories and/or a hard disk drive, CD, DVD, FLASH drive or any other known storage media. Further, the computer-readable instructions may be provided as a utility application, background daemon, or component of an operating system, or combination thereof, executing in conjunction with a processor, such as a Xenon processor from Intel of America or an Opteron processor from AMD of America and an operating system, such as Microsoft VISTA, UNIX, Solaris, LINUX, Apple, MAC-OS and other operating systems known to those skilled in the art.

Once processed by the CPU170, the processed signals are stored in electronic storage180, and/or displayed on display145. As one of ordinary skill in the art would recognize, electronic storage180may be a hard disk drive, CD-ROM drive, DVD drive, FLASH drive, RAM, ROM or any other electronic storage known in the art. Display145may be implemented as an LCD display, CRT display, plasma display, OLED, LED or any other display known in the art. As such, the descriptions of the electronic storage180and the display145provided herein are merely exemplary and in no way limit the scope of the present advancements.

FIG. 7also includes an interface175through which the gamma ray detection system interfaces with other external devices and/or a user. For example, interface175may be a USB interface, PCMCIA interface, Ethernet interface or any other interface known in the art. Interface175may also be wired or wireless and may include a keyboard and/or mouse or other human interface devices known in the art for interacting with a user.

In the above descriptions, any processes, descriptions or blocks in flowcharts should be understood as representing modules, segments or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process, and alternate implementations are included within the scope of the exemplary embodiments of the present advancements in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending upon the functionality involved, as would be understood by those skilled in the art.