Channel selecting apparatus for a television receiver with an electronic tuner

In a channel selecting apparatus for a television receiver having a tuner with a voltage-controlled variable reactance device as its tuning element; digital codes representing or identifying respective channels are stored at respective addresses in a memory, and a digital-to-analog converter provides an analog control voltage for the variable reactance device in correspondence to each digital code selectively read out of the memory in a channel selecting mode of the apparatus. Further, in a programming mode of the apparatus, the changing digitally coded counts of a counter which is counting sweep pulses are applied to the digital-to-analog converter for similarly controlling the variable reactance device and selected counts of the counter, for example, those which result in the appearance on the receiver screen of pictures or test patterns broadcast by selected television stations or channels, are written at selected addresses in the memory as the channel identifying digital codes. Preferably, the digital-to-analog converter is constituted by a pulse-width modulator which produces a chain of pulses at a constant repetition rate with the widths of such pulses being varied in dependence on the absence of coincidence between a circulating digital code and the digitally coded count from the counter as established either by read out of a channel identifying digital code from the memory or by counting of the sweep pulses, and the output of the modulator is passed through a low-pass filter to provide the analog control voltage in dependence on the modulated pulse width.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates generally to channel selecting apparatus for a 
television receiver, and more particularly is directed to a channel 
selecting apparatus for a television receiver having a so-called 
electronic tuner employing, as its tuning element, a varactor or 
voltage-controlled, variable reactance device, such as, a variable 
capacitance diode. 
2. Description of the Prior Art 
Most existing television receivers employ electro-mechanical tuners in 
which a channel-selecting knob is manually rotatable through various 
positions established by a detent mechanism and which respectively 
correspond to the twelve vhf channels. At each of such positions of the 
knob, suitable switch contacts are engaged to activate a respective 
circuit by which the receiving frequency for the designated channel is 
obtained. Such electro-mechanical tuners are susceptible to failure 
because of loose or dirty switch contacts and defects in the detent 
mechanism. Furthermore, electro-mechanical tuners of the described type 
become extremely complex and even more unreliable when designed to tune 
the uhf channels in addition to the vhf channels. 
In order to overcome the above problems of electro-mechanical tuners, 
so-called electronic tuners have been proposed for television receivers. 
In these proposed electronic tuners, a varactor, that is, an analog 
voltage-controlled, variable reactance device, such as, a variable 
capacitance diode, is employed as the tuning element, and the control 
voltage therefor is obtained either by means of a potentiometer array or a 
phase-locked loop arrangement. In the case of the potentiometer array, a 
number of potentiometers are connected between a stable voltage supply and 
ground, and each potentiometer is adjusted to provide a voltage which, 
when applied to the varactor by way of a respective solid state switch, 
will tune the receiver to a respective one of the local channels. Further, 
manually operable switches are provided to control the solid state 
switches associated with the several potentiometers. In the foregoing 
arrangement, it is difficult and costly to obtain stable potentiometers, 
and rather elaborate mechanical assemblies are required to provide for the 
adjustment of the several potentiometers so as to correspond to respective 
local channels. 
In the existing electronic tuners employing a varactor with a phase-locked 
loop, the variable frequency output of the varactor controlled tuner is 
applied through an amplifier to a prescaler which divides such output 
frequency by a fixed number, and the resulting divided frequency is then 
further divided, in a variable counter or divider, by a number that is 
determined by a preset logic controlled by manually operable 
channel-selector switches. The output of the variable counter or divider 
is then compared, in a phase comparator, with a stable reference frequency 
obtained, for example, from a crystal-controlled oscillator, with the 
resulting error signal being used to control or vary the control voltage 
for the varactor. The foregoing phase-locked loop arrangement is 
disadvantageous in that the amplifier used to raise the low level of the 
output of the tuner for driving the digital prescaler may be costly, and 
further in that such prescaler has to operate at an undesirably high input 
frequency. 
OBJECTS AND SUMMARY OF THE INVENTION 
Accordingly, it is an object of this invention to provide an improved 
channel selecting apparatus for a television receiver having a tuner with 
a varactor or voltage-controlled variable reactance device as its tuning 
element, and in which the above described problems and disadvantages of 
the previously proposed channel selecting apparatus for electronic tuners 
are avoided. 
More particularly, it is an object of this invention to provide a channel 
selecting apparatus, as aforesaid, which can be easily and inexpensively 
formed as an integrated circuit, and which is capable of tuning the 
associated television receiver to any desired channel with very high 
accuracy and reliability. 
Another object is to provide a channel selecting apparatus, as aforesaid, 
which is devoid of any potentiometers or variable resistors for 
establishing the control voltage of the varactor, thereby to avoid the 
problems that may arise from the high contact resistance or changes in the 
resistance value of potentiometers that can occur due to vibration, 
temperature variations or simply with time. 
Still another object is to provide a channel selecting apparatus, as 
aforesaid, which may be very simply preset or programmed for determining 
the local channels that are to be received. 
In accordance with an aspect of this invention, in a channel-selecting 
apparatus for a television receiver having a tuner with a varactor as its 
tuning element, digital codes representing or identifying respective 
channels are stored at respective addresses in a memory, and a 
digital-to-analog converter provides an analog control voltage for the 
varactor in correspondence to each digital code selectively read out of 
the memory in a channel selecting mode of the apparatus. Further, in a 
programming mode of the apparatus, changing, digitally coded counts of a 
counter which is counting sweep pulses are applied to the 
digital-to-analog converter for similarly controlling the varactor and 
selected counts of the counter, for example, those which result in the 
appearance on the receiver screen of pictures or test patterns broadcast 
on selected local channels, are written at selected addresses in the 
memory as the channel identifying codes. 
In preferred apparatus according to this invention, the digital-to-analog 
converter is constituted by a pulse-width modulator which produces a chain 
of pulses at a constant repetition rate with the widths of such pulses 
being varied in dependence on the absence of coincidence between a 
circulating digital code and the digitally coded count from the counter as 
established either by read out of a channel identifying digital code from 
the memory or by counting of the sweep pulses, and the output of the 
pulse-width modulator is passed through a low pass filter to provide the 
analog control voltage of the varactor in dependence on the modulated 
pulse width. 
The above, and other objects, features and advantages of the invention, 
will be apparent in the following detailed description of illustrative 
embodiments thereof which is to be read in connection with the 
accompanying drawings.

DESCRIPTION OF PREFERRED EMBODIMENTS 
Referring to the drawings in detail, and initially to FIG. 1 thereof, it 
will be seen that a channel selecting apparatus according to this 
invention is there illustrated to generally comprise a generator 10 of a 
clock pulse A.sub.o which is applied to a timing counter 20 for producing 
a circulating digital or binary code A.sub.1, A.sub.2, A.sub.3 -A.sub.14 ; 
a sweep pulse generating circuit 30 which is manually controllable to 
selectively produce up-sweep pulses P.sub.U or down-sweep pulses P.sub.D ; 
and an up-down counter 40 which, in a programming mode of the apparatus, 
counts the sweep pulses P.sub.U or P.sub.D to establish channel 
identifying digital codes B.sub.1, B.sub.2, B.sub.3 -B.sub.14 
corresponding to the changing counts of counter 40 and which may be 
selectively written at selected addresses in a memory 50. Further, the 
channel selecting apparatus according to this invention, as shown on FIG. 
1, generally comprises a memory control circuit 60 for selectively 
establishing the previously mentioned programming mode of operation or a 
channel selecting mode in which a channel identifying digital code 
previously written or stored at a selected address in memory 50 is read 
out therefrom, as indicated at C.sub.1, C.sub.2, C.sub.3 -C.sub.14, with 
such read out code being applied to counter 40 for establishing the 
corresponding count in the latter; an address selecting circuit 70 that is 
manually controllable for activating a selected address in memory 50 for 
either the writing of a selected channel identifying code at such address 
or the reading out of a previously stored channel identifying code from 
the selected address during the programming or channel selecting modes, 
respectively; and a band indicating signal forming circuit 80 which, in 
the programming mode of operation, is selectively operable to produce a 
signal indicating the band of the channel indicating code then being 
written or stored at a selected address of memory 50, with such band 
indicating signal being also written or stored at the respective address. 
Finally, the channel selecting apparatus according to this invention, as 
shown on FIG. 1, generally comprises a digital-to-analog converter 90 
which provides an analog control voltage for the varactor of a selected 
band in an electronic tuner 100 in correspondence to the count of counter 
40 established by a channel identifying digital code selectively read out 
of memory 50 in a channel selecting mode of the apparatus, or in 
correspondence to the changing counts of counter 40 produced when the 
latter counts sweep pulses from generating circuit 30 in the programming 
mode of the apparatus; and a video intermediate frequency amplifier 110 
which receives the tuned frequency output of tuner 100. 
In the channel selecting apparatus as generally described above, the clock 
pulse A.sub.o from generator 10 may have a frequency of, for example, 4 
MHz resulting in a period .tau. of 0.25 .mu. sec. In the timing counter 
20, such clock pulse A.sub.o is counted to produce pulses A.sub.1 to 
A.sub.14 which are frequency-divided in sequence so as to range from the 
pulses A.sub.1 having a period of 0.5 .mu. sec. and a pulse width of 0.25 
.mu. sec., to the pulses A.sub.14 having a period of 4.096 m.sec. and a 
pulse width of 2.048 m.sec., thereby to form a 14-bit circulating digital 
code constituted by the pulses A.sub.1, A.sub.2, A.sub.3 -A.sub.14. It 
will be apparent that such 14-bit circulating digital code changes its 
state 2.sup.14 times, that is, 16,384 times, within the circulating or 
repeating period of T=2.sup.14 .tau.=4.096 m.sec. (FIGS. 4A and B). 
In the sweep pulse generating circuit 30 as shown on FIG. 1, a fine 
up-sweep switch 31FU, a fine down-sweep switch 31FD, a coarse up-sweep 
switch 31CU and a coarse downsweep switch 31CD are connected in series 
circuits with respective resistors 32.sub.1, 32.sub.2, 32.sub.3 and 
32.sub.4, and such series circuits are connected in parallel between a 
voltage source 45V and ground. The switches 31FU, 31FD, 31CU and 31CD are 
normally open, as shown, to provide signals at the relatively high level 
"1" at the junctions of such switches with the respective resistors 
32.sub.1, 32.sub.2, 32.sub.3 and 32.sub.4. Further, the switches 31FU, 
31FD, 31CU and 31CD are adapted to be selectively manually displaced to 
the closed condition thereof for providing a signal at the low level "0" 
at the junction of the closed switch with the respective resistor 32.sub.1 
-32.sub.4. Such signals "1" or "0" from switches 31FU, 31FD, 31CU and 31CD 
are applied through inverters 33.sub.1, 33.sub.2 33.sub.3 and 33.sub.4 to 
first inputs of NAND circuits 34.sub.1, 34.sub.2, 34.sub.3 and 34.sub.4, 
respectively. The pulses A.sub.14 having a period of 4.096 m.sec. are 
applied from timing counter 20, as coarse sweep pulses, to second inputs 
of NAND circuits 34.sub.3 and 34.sub.4. Further, the pulses A.sub.14 from 
timing counter 20 are applied to a frequency divider 35 so as to be 
divided in the latter, for example, by 64, for providing fine sweep pulses 
having a period of 262.144 m.sec. and such fine sweep pulses are applied 
to second inputs of NAND circuits 34.sub.1 and 34.sub.2. The outputs of 
NAND circuits 34.sub.1 and 34.sub.3 are connected to first and second 
inputs of a NAND circuit 36 which has its output applied to an inverter 37 
for producing either the fine or coarse up-sweep pulses P.sub.U, while the 
outputs of NAND circuits 34.sub.2 and 34.sub.4 are similarly connected to 
first and second inputs of a NAND circuit 38 which has its output applied 
to an inverter 39 for producing either the fine or coarse down-sweep 
pulses P.sub.D. 
As shown schematically on FIG. 2, the counter 40 may be a conventional 
14-bit up-down counter having 14 flip-flops 41.sub.1, 41.sub.2,-41.sub.14 
which have their states changed sequentially in the up or down direction 
when counting the up-sweep pulses P.sub.U or the down-sweep pulses 
P.sub.D, respectively, in the programming mode of operation to establish 
the respective bits of sequentially changing 14-bit channel identifying 
codes B.sub.1, B.sub.2 -B.sub.14. In such programming mode of operation, 
the channel identifying codes are applied from counter 40 to memory 50 for 
writing or storage of a selected one of such codes at a selectively 
activated address in the memory, and the sequentially changing channel 
identifying codes are also applied from counter 40 to digital-to-analog 
converter 90 for providing a correspondingly varied control voltage for 
the varactor in a selected band of electronic tuner 100. The flip-flops 
41.sub.1 -41.sub.14 of counter 40 are further adapted, in the channel 
selecting mode of operation, to have their respective states established 
by the respective bits C.sub.1 -C.sub.14 of a memorized channel 
identifying code which are read out of a selectively activated address in 
memory 50 to AND circuits 42.sub.1 -42.sub.14 which also receive a load 
pulse P.sub.B during the channel selecting operation for passing the bits 
read out of the memory, as hereinafter described in detail, and which have 
their ourputs respectively connected to flip-flops 41.sub.1 -41.sub.14. 
As also shown on FIG. 2, the memory 50 may be desirably comprised of 16 
memory units 51.sub.1, 51.sub.2,-51.sub.16 at respective addresses in 
memory 50, with the memory unit at each address being capable of storing 
16-bits of digital information, that is, the 14-bits of a selected channel 
identifying code from counter 40 and 2-bits from an encoder 52 for the 
band indicating signal received from circuit 80 for indicating whether the 
channel identified by the 14-bit digital code being stored at the 
respective address is a vhf of uhf channel, and, if it is a vhf channel, 
whether it is a low channel or a high channel in such broadcast band, 
respectively. Further, the memory 50 is schematically shown to include a 
decoder 53 which, in the programming and channel selecting modes of 
operation, receives the 2-bits of digital information representing the 
band of the channels identified by the 14-bit codes being applied to, or 
read out from, respectively, the memory units for providing a 
corresponding band identifying signal applied to electronic tuner 100 for 
selecting the corresponding band of the latter. Finally, the memory 50 is 
schematically shown to include a decoder 54 which receives a 4-bit digital 
code from the address selecting circuit 70, as hereinafter described in 
detail, and which is effective to activate or address the corresponding 
one of the memory units 51.sub.1, 51.sub.2 -51.sub.16. Preferably, the 
memory units of memory 50 are composed of non-volatile cells, such as, 
metal-nitride-oxide-silicon (MNOS) elements, so that the contents thereof, 
while being electrically alterable, are held unchanged during periods when 
memory 50 is disconnected from a source of power. 
Returning again to FIG. 1, it will be seen that the memory control 60 
includes a mode change-over switch 61 having a movable contact that is 
manually actuable to selectively engage fixed contacts a and b. The fixed 
contact a is connected to a voltage source +5V so that, when the movable 
contact of switch 61 engages fixed contact a to establish the programming 
mode of operation, a signal P.sub.A at the relatively high level "1" is 
obtained from switch 61. On the other hand, the fixed contact b of switch 
61 is connected to ground so that, when the movable contact of switch 61 
is engaged with fixed contact b for establishing the channel selecting 
mode of operation, the signal P.sub.A is at the relatively low level "0. " 
Memory control 60 is further shown to have a normally open switch 62 which 
is connected in series with a resistor 62a between a voltage source +5V 
and ground. The signal P.sub.A from mode change-over switch 61 is shown to 
be applied to one input of a NAND circuit 63 which has its other input 
connected through an inverter 64 with a junction in the connection between 
switch 62 and resistor 62a. It will be apparent that, when switch 62 is in 
its normally open position, as shown, the output of inverter 64 will be at 
the low level "0," whereas, when switch 62 is manually closed to effect a 
writing operation with the apparatus in its programming mode, the output 
of inverter 64 will be at the relatively high level "1." The output of 
NAND circuit 63 is shown to be applied to an instruction signal forming 
circuit 65 which, when the output of NAND circuit 63 is at the low level 
"0," supplies an erasing pulse P.sub.E and then a writing pulse P.sub.WR 
to the memory unit at a selected address in memory 50 so as to erase the 
previously stored contents in such memory unit and, thereafter, to write 
in the selected memory unit the 14-bit channel identifying code then being 
received from counter 40 and the 2-bit code which represents the band of 
the channel identified by the code being written in the respective memory 
unit. On the other hand, when the output of NAND circuit 63 is at the high 
level "1," instruction signal forming circuit 65 applies a read pulse 
P.sub.R to memory unit 50 so as to effect the read out of the contents 
stored in the memory unit which is then selected. 
The band indicating signal forming circuit 80 is shown to include normally 
open switches S.sub.L, S.sub.H and S.sub.U which are connected in series 
with respective resistors 81.sub.L, 81.sub.H and 81.sub.U between a 
voltage source +5V and ground. Junctions between switches S.sub.L, S.sub.H 
and S.sub.U and the respective resistors are connected to inverters 
82.sub.L, 82.sub.H and 82.sub.U, respectively, which have their outputs 
connected to first inputs of NAND circuits 83.sub.L, 83.sub.H and 
83.sub.U, respectively, while the second inputs of such NAND circuits 
receive the signal P.sub.A from mode change-over switch 61. The outputs of 
NAND circuits 83.sub.L, 83.sub.H and 83.sub.U are applied to a band memory 
84 which is effective to apply a band indicating signal P.sub.L, P.sub.H 
or P.sub.U to encoder 52 in memory 50 in response to a low level or "0" 
output from the NAND circuit 83.sub.L, 83.sub.H or 83.sub.U, respectively. 
It will be apparent that, in the programming mode of operation established 
by engagement of switch 61 with its fixed contact a to provide the signal 
P.sub.A with the high value "1," the output of the NAND circuit 83.sub.L, 
83.sub.H or 83.sub.U has the low value "0" only when the respective switch 
S.sub.L, S.sub.H or S.sub.U is manually closed for indicating that the 
channel identified by the 14-bit code to be written at a selected address 
in memory 50 is a low vhf channel, a high vhf channel or a uhf channel, 
respectively. 
The address selecting circuit 70 of the illustrated channel selecting 
apparatus according to this invention includes 16 normally open address 
selecting switches S.sub.1, S.sub.2 -S.sub.16 which are each selectively 
manually actuable to the closed condition for selecting a corresponding 
one of the 16 addresses or memory units in memory 50 to be activated 
during a programming operation or channel selecting operation of the 
apparatus. The address selecting circuit 70 is further shown to include 
neon tubes or other indicators N.sub.1, N.sub.2 -N.sub.16 corresponding to 
the switches S.sub.1, S.sub.2 -S.sub.16, an address counter 71 which, in 
response to the closing of a selected one of the switches S.sub.1 
-S.sub.16, produces a corresponding 4-bit addressing code applied to the 
decoder 54 in memory 50 for addressing the corresponding memory unit in 
the latter, and a decoder 72 which receives the coded output of address 
counter 71 and, in response thereto, provides a "0" output signal on a 
respective one of 16 output lines L.sub.1, L.sub.2 -L.sub.16. The switches 
S.sub.1 -S.sub.16 are connected, at one side, in common, through series 
resistors 73 and 74 to ground, while the opposite sides of switches 
S.sub.1 -S.sub.16 are connected to lines L.sub.1 -L.sub.16, respectively. 
Further, the lines L.sub.1 -L.sub.16 are connected through resistors 
75.sub.1 -75.sub.16, respectively, and a common resistor 76a with a 
voltage source +100V, while the neon tubes or indicators N.sub.1 -N.sub.16 
are connected between the lines L.sub.1 -L.sub.16, respectively, and the 
same voltage source +100V through a common resistor 76b. The junction 
between series-connected resistors 73 and 74 is connected to the base 
electrode of a switching transistor 77 having its emitter electrode 
connected to ground and its collector electrode connected to a voltage 
source +V.sub.cc and to an inverter 78. The output of inverter 78 is 
connected to one input of a NAND circuit 79 which, at its other input, 
receives the pulses A.sub.9 produced by timing counter 20 and having a 
period of 0.128 m.sec. Finally, the output of NAND circuit 79 is applied 
to address counter 71 which is operative to count each "0" output of NAND 
circuit 79. 
In order to provide the load pulse P.sub.B to AND circuits 42.sub.1 
-42.sub.14 of counter 40 for read out to the latter of the channel 
identifying code C.sub.1 -C.sub.14 stored in a selected memory unit of 
memory 50 in the channel selecting mode of operation, the illustrated 
apparatus according to this invention is further shown to include an 
inverter 43 receiving the signal P.sub.A from memory control 60 and having 
its output connected to one of the inputs of a NAND circuit 44 which, at 
its other input, is connected to the output of a monostable multivibrator 
45 which is triggered by a relatively high collector output "1" from 
transistor 77 or from a transistor 46 of a time constant circuit 47. The 
output of NAND circuit 44 is connected to an inverter 48 which, in turn, 
has its output connected to AND circuits 42.sub.1 -42.sub.14 of counter 40 
so that the load pulse P.sub.B is produced when the output of NAND circuit 
44 is "0," that is, when signal P.sub.A has the value "0" for the channel 
selecting mode of operation and monostable multivibrator 45 is triggered 
to produce a pulse having the value "1" for a predetermined period of, for 
example, 50 m.sec. In the time constant circuit 47, the base electrode of 
transistor 46 is shown to be connected between a capacitor 46a and a 
resistor 46b which are connected, in series, between the voltage source 
+V.sub.cc and ground, while the collector of transistor 46 is connected 
through a resistor 46c with the voltage source and the emitter electrode 
of transistor 46 is connected to ground. Therefore, when the apparatus is 
initially connected to a power source, transistor 46 is made conductive 
and, hence its collector output is "0." After a predetermined lapse of 
time, for example, of 50 m.sec., transistor 46 is turned off so that its 
collector output rises to the value "1" for triggering monostable 
multivibrator 45 which then provides its output for the predetermined time 
of 50 m.sec. 
In the channel selecting apparatus according to this invention, the 
digital-to-analog converter 90 preferably includes a pulse-width modulator 
91 operative to produce a chain of pulses at a predetermined repetition 
rate with the width of each of such pulses being dependent on the channel 
identifying code B.sub.1,B.sub.2,-B.sub.14 obtained from counter 40 either 
in response to the counting by the latter of the sweep pulses from 
generating circuit 30 or in response to the read out of a channel 
identifying code stored at a selected address in memory 50, and a low pass 
filter 92 which receives the chain of pulses from modulator 91 for 
providing the anaolog control voltage for a varactor of electronic tuner 
100 in dependence on the modulated width of the pulses. More particularly, 
the pulse-width modulator 91 determines the pulse width of the chain of 
pulses applied to low pass filter 92 in dependence on the absence of 
coincidence between the channel identifying code B.sub.1,B.sub.2 -B.sub.14 
obtained from counter 40 and the circulating digital code A.sub.1,A.sub.2 
-A.sub.14 applied to modulator 91 from timing counter 20. 
As shown on FIG. 3, the pulse-width modulator 90 may advantageously include 
14 exclusive OR circuits 901,902,-914 having first and second inputs which 
respectively receive the bits or pulses A.sub.1,A.sub.2 -A.sub.14 of the 
circulating code and the bits B.sub.1,B.sub.2 -B.sub.14 of the channel 
identifying code. The outputs of all of the exclusive OR circuits 901-914 
are applied through an OR circuit 93 to the reset terminal R of a 
flip-flop 94 which has the pulse A.sub.14 with a period of 4.096 m.sec. 
applied from timing counter 20 to the set terminal S of flip-flop 94. The 
flip-flop 94 is adapted to be set by the falling edge or side of each 
pulse A.sub.14 so as to provide an output of value "1" at its output 
terminal Q, that is, to initiate an output pulse P.sub.W. Further, 
flip-flop 94 is reset to terminate the output pulse P.sub.W, that is, to 
return the output voltage to "0," in response to the falling edge or side 
of an output P.sub.O from OR circuit 93. 
As is apparent from FIGS. 4B-4E, an output pulse P.sub.W is initiated at 
the output Q of flip-flop 94 when the circulating code A.sub.1,A.sub.2 
-A.sub.14 returns from the state (11111111111111) to the state 
(00000000000000). So long as the circulating code A.sub.1,A.sub.2 
-A.sub.14 is not coincident in level with the channel identifying code 
then being applied to pulse-width modulator 91, one or more of the 
exclusive OR circuits 901-914 produces an output "1" with the result that 
the output P.sub.O of OR circuit 93 remains at the level "1" (FIG. 4B). 
Upon the coincidence of all bits of the circulating code A.sub.1,A.sub.2 
-A.sub.14 with the corresponding bits of the channel identifying code 
B.sub.1,B.sub.2 -B.sub.14 during each circulating period T of the 
circulating code, the outputs of all of the exclusive OR circuits 901-914 
attain the value "0," with the result that the output P.sub.O of OR 
circuit 93 falls from the value "1" to the value "0" so as to reset 
flip-flop 94 and thereby return the output of the latter to the value "0." 
Thus, during each circulating period T of the circulating code 
A.sub.1,A.sub.2 -A.sub.14 from timing counter 20 an output pulse P.sub.W, 
that is, an output of the value "1," is obtained from flip-flop 94 during 
the time interval between the return of the circulating code 
A.sub.1,A.sub.2 -A.sub.14 from the state (11111111111111) to the state 
(00000000000000) and the coincidence of the circulating code with the 
channel identifying code B.sub.1,B.sub.2 -B.sub.14. Therefore, when a 
change is effected in the channel identifying code B.sub.1,B.sub.2 
-B.sub.14 being applied to pulse-width modulator 91, a corresponding 
change occurs in the width of the output pulse P.sub.W obtained from 
modulator 91 during each circulating period of the circulating code. 
For example, as shown on the left-hand portions of FIGS. 4A-4E, if the 
channel identifying code B.sub.1,B.sub.2,-B.sub.14 applied to pulse-width 
modulator 91 is (00000000000001) the output pulse P.sub.W produced during 
each circulating period of the circulating code A.sub.1,A.sub.2 -A.sub.14 
commences at the beginning of the circulating period, that is, when the 
circulating code returns from the state (11111111111111) to the state 
(00000000000000), and each such output pulse P.sub.W terminates at the 
commencement of the first pulse A.sub.1, at which time the circulating 
code (00000000000000) coincides with the received channel identifying code 
(00000000000000) to cause the output P.sub.O of OR circuit 93 to fall from 
"1" to "0." Thus, the output pulse P.sub.W produced during each 
circulating period of the circulating code has a pulse width of .tau.. On 
the other hand, as shown on the middle portions of FIGS. 4A-4E, if the 
channel identifying code B.sub.1,B.sub.2 -B.sub.14 being received by the 
pulse-width modulator 91 is (00000000000010), the coincidence of that 
channel identifying code with the circulating code A.sub.1,A.sub.2 
-A.sub.14 occurs, during each circulating period of the circulating code, 
at the commencement of the first pulse A.sub.2, so that the resulting 
output pulse P.sub.W obtained during each circulating period has a width 
of 2.tau.. Similarly, as shown at the right-hand portions of FIGS. 4A-4E, 
if the channel identifying code B.sub.1,B.sub.2 -B.sub.14 received by 
modulator 91 during each circulating period is (00000000000011), the 
coincidence of such channel identifying code with the circulating code 
A.sub.1,A.sub.2 -A.sub.14 during each circulating period of the latter 
occurs at the commencement of the pulse A.sub.1 appearing during the 
existence of the first pulse A.sub.2 so that the resulting output pulse 
P.sub.W obtained during each circulating period has a pulse-width of 3 
.tau.. 
Thus, the output pulses P.sub.W produced by modulator 91 during the 
successive circulating periods T of the circulating code A.sub.1,A.sub.2 
-A.sub.14 have their pulse-widths determined by the channel identifying 
code B.sub.1,B.sub.2 -B.sub.14 then being received by the modulator, and 
the low pass filter 92 is effective to smooth such output pulses P.sub.W 
from modulator 91 and to deliver an analog or DC voltage having a value 
that corresponds to the width of the pulses P.sub.W. 
In the electronic tuner 100 a signal V.sub.H,V.sub.L or U received from 
decoder 53 of memory 50 selects either the high band or the low band of a 
vhf tuning section or the uhf tuning section, respectively, for operation, 
with the voltage controlled variable reactance element or varactor, such 
as, a variable capacitance diode, of the selected tuning section being 
controlled by the analog or DC control voltage from low pass filter 92 for 
determining the receiving frequency. Finally, such receiving frequency is 
applied to the video intermediate frequency amplifier circuit 110 and the 
output of the latter is applied to a video detector circuit (not shown) as 
in a conventional color television receiver. 
The above described channel selecting apparatus according to this invention 
operates as follows: 
PROGRAMMING MODE OF OPERATION 
When it is desired to program the channel selecting apparatus, that is, to 
store at the various addresses in memory 50 channel identifying codes 
corresponding to various channels that are receivable in the region where 
the television receiver is located so that, thereafter, such channels can 
be received or selected merely by actuation of the switches S.sub.1 
-S.sub.16 corresponding to the respective addresses, the mode change-over 
switch 61 is engaged with its fixed contact a for selecting the 
programming mode of operation. If it is desired, for example, to store at 
the address or memory unit 51.sub.1 of memory 50 a channel identifying 
code corresponding to the receiving frequency for channel "one" in the 
Tokyo area of Japan, the address selecting switch S.sub.1 is manually 
closed. Closing of switch S.sub.1 turns ON transistor 77 in address 
selecting circuit 70 so that the collector output of such transistor has 
the value "0." Thus, the output of inverter 78 becomes "1" with the result 
that NAND circuit 79 provides a "0" output on receiving each of the pulses 
A.sub.9 from timing counter 20. The address counter 71 counts each of the 
"0" outputs from NAND circuit 79. When the resulting 4-bit code from 
address counter 7 corresponds to the address or memory unit 51.sub.1 
selected by the closing of switch S.sub.1, the decoder 72 responds to such 
4-bit code from address counter 71 to provide a "0" output on the 
corresponding output line L.sub.1. In response to such "0" output on line 
L.sub.1, transistor 77 is turned OFF with the result that the output of 
NAND circuit 79 remains at "1" and address counter 71 ceases counting. 
Accordingly, the 4-bit code corresponding to switch S.sub.1 is applied to 
memory 50 for selecting or activating the address or memory unit 51.sub.1 
corresponding to switch S.sub.1. 
Since channel "one" in the Tokyo area, that is, a low vhf channel, is to be 
programmed in memory unit 51.sub.1, switch S.sub.L of the band indicating 
signal forming circuit 80 is closed to provide an output "1" from the 
respective inverter 82.sub.L. Since mode change-over switch 61 is engaged 
with its fixed contact a, its output P.sub.A is "1" and, therefore, the 
output of NAND circuit 83.sub.L becomes "0." Band memory 84 responds to 
such "0" output from NAND circuit 83.sub.L to provide the band selecting 
pulse P.sub.L which, through encoder 52 and decoder 53 of memory 50 
provides the signal V.sub.L for selecting the low band or channel of the 
vhf tuning section in tuner 100. 
Having selected the address or memory unit of memory 50 at which a channel 
identifying code is to be programmed and the band or section of tuner 100 
which is appropriate for the channel to be programmed at such selected 
address, the sweep pulse generating circuit 30 is made operative, for 
example, by manually actuating the coarse up-sweep switch 31CU and holding 
the latter in its closed position. The closing of switch 31CU causes the 
associated inverter 33.sub.3 to provide the output "1" to NAND circuit 
34.sub.3. Therefore, at each "0" state of the pulses A.sub.14 from timing 
counter 20, which pulses have a period of 4.096 m.sec., NAND circuit 
34.sub.3 provides an output "1." Since the fine up-sweep switch 31FU is 
open, the output of its associated inverter 33.sub.1 is "0" and the output 
of the respective NAND circuit 34.sub.1 is "1." Therefore, the output of 
the NAND circuit 36 becomes "0" at every "1" output from NAND circuit 
34.sub.3, that is, at every "0" state of the pulses A.sub.14. Accordingly, 
an up-sweep pulse P.sub.U appears at the output of inverter 37 at every 
"0" state of the pulses A.sub.14 from timing counter 20. Since such pulses 
A.sub.14 have a relatively short period of 4.096 m.sec., the pulses 
P.sub.U appearing while switch 31 CU is held in its closed condition may 
be considered coarse up-sweep pulses which, when being counted by counter 
40, cause relatively rapid changes in the count of such counter 40. In 
other words, when counting the coarse up-sweep pulses P.sub.U from 
generating circuit 30, the count of counter 40 is changed, in sequence, in 
the upward direction to similarly change the resulting channel identifying 
code B.sub.1 ,B.sub.2 -B.sub.14 obtained from counter 40 at every 
circulating period of the circulating code A.sub.1,A.sub.2 -A.sub.14 from 
timing counter 20, starting from the state (00000000000000), as shown on 
FIG. 4C. The changing channel identifying code from counter 40 and the 
circulating code from timing counter 20 are applied to pulse-width 
modulator 91 in the programming mode of operation. Since the circulating 
code A.sub.1,A.sub.2 -A.sub.14 changes at every time .tau. = 0.25 .mu.sec. 
which is the width of the pulses A.sub.1, the width of the output pulse 
P.sub.W from modulator 91 is increased by .tau. at every circulating 
period T of the circulating code starting from a pulse width of zero. 
Thus, so long as switch 31CU of sweep pulse generating circuit 30 is held 
in its closed condition, the channel selecting or control voltage from low 
pass filter 92 is increased progressively, for example, by about 2 m.V at 
every period T=4.096 m.sec. of the circulating code, and hence the 
receiving frequency established by tuner 100 increases progressively. 
When a video picture being broadcast or transmitted by channel "one" 
appears on the screen of the televison receiver, the coarse up-sweep 
switch 31CU is released by the operator so as to return to its normal open 
condition. Upon opening of switch 31CU, the supplying of the coarse 
up-sweep pulses P.sub.U to counter 40 is terminated so that counter 40 
ceases its counting action and the channel identifying code 
B.sub.1,B.sub.2 -B.sub.14 then obtained from counter 40 determines the 
approximate value of the receiving frequency of tuner 100 for the desired 
channel. Thereafter, the fine up-sweep switch 31FU may be manually 
actuated and held in its closed condition to provide fine up-sweep pulses 
P.sub.U from inverter 37, which fine up-sweep pulses have a period 64 
times that of the coarse up-sweep pulses by reason of the divider 35. In 
counting the fine up-sweep pulses, the counter 40 sequentially changes the 
resulting channel identifying code B.sub.1,B.sub.2 -B.sub.14 at every 
period 64T=262.144 m.sec. Thus, the width of the output pulses P.sub.W 
from pulse-width modulator 91 is increased by .tau. at every period 64T 
and, accordingly, the channel selecting or control voltage from low pass 
filter 92 is increased by about 2 mV at every period 64T for similarly 
changing the receiving frequency by tuner 100. When viewing of the picture 
on the screen of the television receiver indicates that fine tuning has 
been achieved in respect to the video signal broadcast by the desired 
channel, switch 31FU is released to return to its open condition and 
thereby halt the supplying of the fine up-sweep pulses to counter 40. 
Accordingly, counter 40 stops counting with the resulting channel 
identifying code B.sub.1,B.sub.2 -B.sub.14 corresponding to a value of the 
analog control voltage applied from digital-to-analog converter 90 to 
tuner 100 corresponding to a receiving frequency for the fine-tuned 
reception of channel "one." Thereafter, the writing switch 62 is manually 
closed so that the associated inverter 64 provides the output "1." Since 
the mode change-over switch 61 remains engaged with its fixed contact a to 
provide the output P.sub.A with the value "1," the NAND circuit 63 
provides the output "0." As a result of such "0" output from NAND circuit 
63, the instruction signal forming circuit 65 first supplies an erasing 
pulse P.sub.E to memory 50 so as to erase any contents previously stored 
in the memory unit 51.sub.1 selected by the closing of switch S.sub.1. 
Then, circuit 65 applies a writing pulse P.sub.WR to memory unit 51.sub.1 
with the result that the channel identifying code B.sub.1,B.sub.2 
-B.sub.14 established by counter 40 for fine-tuning of channel "one" and 
the band identifying signal P.sub.L from band memory 84 are then written 
in the respective cells of memory unit 51.sub.1. 
Following the programming of memory unit 51.sub.1 with a channel 
identifying code and a band indicating code corresponding to channel 
"one," the other memory units 51.sub.2 -51.sub.16 of memory 50 may be 
similarly programmed with coded information corresponding to other vhf 
and/or uhf channels that are receivable in the region where the television 
receiver is located. Thus, for example, if it is desired to program memory 
unit 51.sub.2 with coded information corresponding to channel "three" in 
the Tokyo area, mode change-over switch 61 is kept in engagement with its 
fixed contact a for establishing the programming mode of operation, and 
address selecting switch S.sub.2 is closed for addressing memory unit 
51.sub.2. Since channel "three" is also a low vhf channel, switch S.sub.L 
of band indicating signal forming circuit 80 is again closed and, for 
example, coarse up-sweep switch 31CU of the sweep-pulse generating circuit 
is held in its closed position until counter 40, in counting the resulting 
up-sweep pulses, has changed the channel identifying code 
B.sub.1,B.sub.2,-B.sub.14 from the code for fine tuning of channel "one" 
to the code for approximate tuning of channel "three." After the channel 
identifying code has been further modified by fine tuning, as described 
above, writing switch 62 is again closed for effecting the writing in 
memory 51.sub.2 of the channel identifying and band indicating codes for 
the desired channel "three". Thus, at each of the addresses of memory 50 
there can be sequentially written or stored the channel identifying and 
band indicating codes corresponding to a respective desired channel. 
Although the programming of the channel selecting apparatus according to 
this invention has been described above as being effected by the 
sequential closing of the coarse up-sweep switch 31CU and the fine 
up-sweep switch 31FU, in which case, the coarse or fine up-sweep pulses 
P.sub.U are counted in the upward direction by counter 40 for 
progressively increasing the receiving frequency of tuner 100, it will be 
apparent that the programming operations can be similarly effected by the 
successive closing of the coarse down-sweep switch 31CD and the fine 
down-sweep switch 31FD so that counter 40 is made to count in the downward 
direction for progressively decreasing the receiving frequency of tuner 
100. Whether counter 40 is made to count in the upward direction or in the 
downward direction, as aforesaid, is merely dependent upon the 
relationship of the receiving frequency for a channel which is to be 
programmed relative to the receiving frequency for the channel which has 
been previously programmed and, in each case, the direction in which 
counter 40 is made to count is selected so as to minimize the time 
required for the programming operation. 
CHANNEL SELECTING MODE OF OPERATION 
After the programming of memory 50 has been completed, as described above, 
the mode change-over switch 61 is manually actuated to engage its fixed 
contact b and thereby provide the output P.sub.A with the value "0" for 
establishing the channel selecting mode of operation for the apparatus. 
Since writing switch 62 remains in its open position, the output of the 
associated inverter 64 is "0" and, accordingly, NAND circuit 63 provides 
the output "1" to instruction signal forming circuit 65 so that the latter 
supplies the reading pulse P.sub.R to memory 50. 
Preferably, when the power source for the channel selecting apparatus is 
initially turned ON, the address counter 71 of address selecting circuit 
70 is reset thereby so that the 4-bit code issuing from counter 71 will 
activate or address the memory unit 51.sub.1 in memory 50. 
When the power source for the channel selecting apparatus is initially 
turned ON, the transistor 46 in time constant circuit 47 is made 
conductive so that its collector output is "0" for a predetermined period 
of, for example, 50 m.sec., whereupon transistor 46 is turned OFF and its 
collector output rises to the value "1." Such rise in the collector output 
of transistor 46 triggers the monostable multivibrator 45 to provide an 
output pulse from the latter at the level "1" for the predetermined time 
of 50 m.sec. Since the output P.sub.A from mode change-over switch 61 is 
"0" for the channel selecting mode of operation, the output from inverter 
43 is "1" and, therefore, the output from NAND circuit 44 is "0" for the 
predetermined time or period of the output pulse from monostable 
multivibrator 45. Such "0" output from NAND circuit 44 causes the inverter 
48 to produce the output "1," that is, the load pulse P.sub.B for the 
period of the output pulse from monostable multivibrator 45. The load 
pulse P.sub.B, when applied to AND circuits 42.sub.1 -42.sub.14 in counter 
40, allows the read out to counter 40 from memory unit 51.sub.1 of the 
channel identifying code C.sub.1,C.sub.2 -C.sub.14 previously stored 
therein and which, in the example described above, represents channel 
"one" in the Tokyo area. At the same time, the band indicating code stored 
in the respective cells of memory unit 51.sub.1 is read out from the 
latter to decoder 53 so that, in the described example, the signal V.sub.L 
is applied to tuner 100 for selecting the low band of the vhf tuning 
section. During the existence of load pulse P.sub.B, the bits C.sub.1 
-C.sub.14 of the read out channel identifying code are applied to the 
respective flip-flops 41.sub.1 -41.sub.14 of counter 40 with the result 
that such flip-flops assume the states for providing the channel 
identifying code B.sub.1 -B.sub.14 from counter 40 to pulse-width 
modulator 91 which corresponds to a control voltage for tuner 100 suitable 
for fine tuning of the receiving frequency to that of channel "one." 
Therefore, upon the initial supplying of power to the channel selecting 
apparatus, the latter tunes the television receiver for the reception of 
the channel which has been programmed into the first address or memory 
unit 51.sub.1 of memory 50. 
Thereafter, if it is desired to receive a channel programmed in a memory 
unit of memory 50 other than the first address or memory unit 51.sub.1, 
for example, if it is desired to receive channel "three" programmed in the 
second memory unit 51.sub.2, as described above, the switch S.sub.2 of the 
address selecting circuit 70 is manually closed and, as previously 
described in connection with the programming mode of operation, the 
address counter 71 counts the pulses A.sub.9 until the 4-bit code from 
address counter 71 addresses the second memory unit 51.sub.2 for causing 
read out of the channel identifying code and band indicating code stored 
in that memory unit during the programming of channel "three" in memory 
unit during the programming of channel "three" in memory unit 51.sub.2. 
When the code from address counter 71 addresses the memory unit 
corresponding to closed switch S.sub.2, decoder 72 provides the signal "0" 
on the respective output line L.sub.2 so that transistor 77 is turned OFF 
and its collector output rises from " 0" to "1." Such rise in the 
collector output of transistor 77 triggers monostable multivibrator 45 
and, as previously described, the output from monostable multivibrator 45 
results in the production of a load pulse P.sub.B from inverter 48. In 
response to the load pulse P.sub.B, the channel identifying code being 
read out of memory unit 51.sub.2 correspondingly changes the states of the 
flip-flops of counter 40 so that the latter provides the corresponding 
channel identifying code B.sub.1,B.sub.2 -B.sub.14 to pulse width 
modulator 91. Therefore, the output pulse P.sub.W obtained from modulator 
91 during each circulating period of the circulating code A.sub.1,A.sub.2 
-A.sub.14 has its width determined by the channel identifying code so as 
to result in an analog control voltage from low pass filter 92 to tuner 
100 sufficient to cause the latter to establish the receiving frequency 
for channel "three." 
It will be apparent that the channels programmed in the other memory units 
51.sub.3 -51.sub.16 may be similarly selectively received merely by manual 
closing of a respective one of the address selecting switches S.sub.1 
-S.sub.16. 
Referring now to FIG. 5, it will be seen that a channel selecting apparatus 
according to another embodiment of the present invention is there shown to 
be generally similar to that described above with reference to FIG. 1, and 
has its components and parts identified by the same reference numerals as 
were employed for identifying the corresponding components and parts of 
the first described embodiment. It will be apparent that the channel 
selecting apparatus of FIG. 5 differs from that described above with 
reference to FIG. 1 only in respect to the arrangement and operation of 
its sweep-pulse generating circuit 130 which replaces the sweep-pulse 
generating circuit 30 of FIG. 1. More particularly, the sweep-pulse 
generating circuit 130 is shown to comprise only a single up-sweep switch 
131U and a single down-sweep switch 131D associated with inverters 
132.sub.I and 132.sub.2, respectively, to provide a signal "1" at the 
output of the associated inverter upon the closing of the switch 131U or 
131D. The output of inverter 132.sub.1 is supplied to NAND circuits 
133.sub.1 and 133.sub.2, while the output of inverter 132.sub.2 is 
supplied to NAND circuits 133.sub.3 and 133.sub.4. The switches 131U and 
131D are further connected to a NAND circuit 135 so that, when one or the 
other of the switches 131U and 131D is closed to provide a "0" output to 
NAND circuit 135 (FIG. 6A) the output from NAND circuit 135 will trigger a 
monostable multivibrator 136 to produce an output pulse P.sub.M (FIG. 6C) 
having a predetermined pulse width, for example, of about 5 seconds. The 
pulse P.sub.M is applied to NAND circuits 133.sub.1 and 133.sub.3, and is 
further supplied from monostable multivibrator 136 to an inverter 137 for 
providing an inverted pulse P.sub.M (FIG. 6D) which is applied to NAND 
circuits 133.sub.2 and 133.sub.4. The pulses A.sub.14 (FIG. 6F) from 
timing counter 20 are applied as coarse-sweep pulses to NAND circuits 
133.sub.2 and 133.sub.4 and also applied to a frequency divider 133 by 
which the frequency of the pulses A.sub.14 is divided by 64. Such 
frequency-divided pulses (FIG. 6E) from divider 138 are applied as 
fine-sweep pulses to the NAND circuits 133.sub.1 and 133.sub.3. Finally, 
the outputs of NAND circuits 133.sub.1 and 133.sub.2 are applied to a NAND 
circuit 139U for producing up-sweep pulses P.sub.U, while the outputs of 
NAND circuits 133.sub.3 and 133.sub.4 are applied to a NAND circuit 139D 
for producing down-sweep pulses P.sub.D. As previously described with 
reference to the embodiment of FIG. 1, the sweep pulses P.sub.U and 
P.sub.D are selectively applied to counter 40 so as to be counted up or 
down, respectively, by the counter 40 in the programming mode of operation 
of the apparatus. 
More particularly, in the programming mode of operation of the apparatus 
illustrated on FIG. 5, the address selecting circuit 70 and the band 
indicating signal forming circuit 80 are initially operated for selecting 
the memory unit of memory 50 in which a desired channel is to be 
programmed and for selecting the band of tuner 100 which is suitable for 
such channel, whereupon one of the switches 131U and 131D, for example, 
the switch 131U, is closed at the time t.sub.1 (FIG. 6A) so as to 
simultaneously provide the output "1" from the associated inverter 
132.sub.1 (FIG. 6B). The closing of switch 131U further causes the output 
of NAND circuit 135 to rise from "0" to "1" and thereby trigger monostable 
multivibrator 136 to produce the pulse P.sub.M (FIG. 6C). The pulse 
P.sub.M is maintained at the level "1" for a period of 5 seconds from the 
time t.sub.1 while the output of inverter 132.sub.1 is also "1." Thus, 
during the period of five seconds from the time t.sub.1 to the time 
t.sub.2, the output of NAND circuit 133.sub.1 is "0" (FIG. 6G) each time 
the pulses from frequency divider 138 (FIG. 6E) become "1." However, after 
the time t.sub.2, that is, after five seconds from the time t.sub.1 when 
switch 131U is initially closed, pulse P.sub.M from monostable 
multivibrator 136 terminates so that the output of NAND circuit 133.sub.1 
remains at the level "1" (FIG. 6G). At the time t.sub.2, the output 
P.sub.M (FIG. 6D) of inverter 137 becomes "1" so that, from the time 
t.sub.2 to the later time t.sub.3 when switch 131U is released for return 
to its normal open condition, the output (FIG. 6H) of NAND circuit 
133.sub.2 becomes "0" whenever the pulses A.sub.14 (FIG. 6F) attain the 
level "1." As a result, the NAND circuit 139U produces a fine up-sweep 
pulse from the time t.sub.1 to the time t.sub.2, that is, for a period of 
five seconds after initial closing of switch 131U, and, thereafter, NAND 
circuit 139U produces a coarse up-sweep pulse until the time t.sub.3 when 
switch 131U is released for return to its open condition (FIG. 6I). 
In a manner similar to that described above with reference to the switch 
131U, it will be apparent that, when the down-sweep switch 131D is closed, 
a fine down-sweep pulse is obtained from NAND circuit 139D for the first 5 
seconds following the closing of switch 131D and, thereafter, a coarse 
down-sweep pulse is obtained from NAND circuit 139D until switch 131D is 
released to return to its open condition. 
It will be apparent that, when programming memory 50 of the channel 
selecting apparatus, for example, to provide the channel identifying code 
for channel "one" at the first address or memory unit in memory 50, the 
switch 131U may be manually closed to produce the fine and then coarse 
up-sweep pulses P.sub.U to be counted by counter 40. If, during such 
counting of the up-sweep pulses P.sub.U, the count of counter 40 goes 
beyond that for establishing the optimum channel identifying codes 
B.sub.1, B.sub.2 -B.sub.14 for the reception of channel "one," then the 
down-sweep switch 131D may be closed for causing fine down-sweep pulses 
P.sub.D to be supplied to counter 40 for a period of up to 5 seconds from 
the closing of switch 131D. During the down counting by the counter 40 of 
the fine down-sweep pulses, the channel identifying code issuing from 
counter 40 can be easily returned to the optimum value for reception of 
channel "one." Accordingly, by the selective operation of only the two 
switches 131U and 131D, the optimum codes for any desired channels can be 
readily obtained for programming or storage in respective memory units of 
memory 50. 
It will be apparent that, in the channel selecting apparatus according to 
this invention, as described above, digital codes representing or 
identifying respective channels, and which are produced by the counting of 
sweep pulses, are stored at respective addresses in a memory during 
programming operations of the apparatus, and a digital-to-analog converter 
provides an analog control voltage for a varactor of an electronic tuner 
in correspondence to each digital code selectively read out of the memory 
in a channel selecting mode of operation of the apparatus. Thus, the 
apparatus according to this invention does not require potentiometers or 
variable resistors with movable contacts for selectively establishing the 
control voltage for the electronic tuner, which potentiometers or variable 
resistors are unreliable in that the values thereof may change due to 
vibration, temperature variations and/or merely with time. Accordingly, 
the apparatus according to this invention provides improved reliability 
and accuracy in tuning for reception of the desired channels, and may 
easily be formed as an integrated circuit with consequent savings in the 
cost thereof. 
Furthermore, the apparatus according to this invention may be easily 
programmed for selection of any of the channels that may be received in 
the region where the television receiver is located. 
Although illustrative embodiments of the invention have been described in 
detail herein with reference to the accompanying drawings, it is to be 
understood that the invention is not limited to those precise embodiments, 
and that various changes and modifications may be effected therein by one 
skilled in the art without departing from the scope or spirit of the 
invention as defined in the appended claims.