Delay of initialization at memory die

Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and more particularly, to apparatuses and methods related to delaying, at a memory die, initialization of the memory die.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to delaying, at a memory die, initialization of the memory die of a memory device. As described herein, delaying, at a memory die of a memory device, initialization of that memory die can include modifying a timing of providing signaling associated with initialization of the memory die to initialization circuitry of the memory die as compared to a default timing of providing signaling associated with initialization of a memory die of a different memory device. As used herein, “initialization circuitry” refers to logic circuitry of a memory die configured to perform operations associated with initialization of the memory die. For example, initialization circuitry can control and/or provide internal voltage level ramping, impedance calibration, clock training, input/output (I/O) training, internal functionality checks, reading of states of fuse arrays and/or distribution thereof, and adjustment of repair settings. As used herein, a “fuse array” refers to an array of programmable elements. The programmable elements of a fuse array can include fuse elements. As used herein, a “fuse element” refers to fuses and anti-fuse elements.

Initialization of a memory device can include signaling being provided to a pin of the memory device, such as a reset pin. As used herein, “initialization” of a memory device or memory die of a memory device refers to internal reset operations and at least a portion of internal initialization operation of memory dies subsequent to the reset operation. Initialization of a memory die can prepare the memory die to receive external commands and/or to meet functionality and/or performance requirements of the memory die.

A host, for example, can provide the signaling, or cause the signaling to be provided, the pin of the memory device. A memory device, such as a memory sub-system, can include multiple memory dies. In response to receipt of the signaling at the pin, memory dies of the memory device can provide signaling and/or perform operations internally associated with initializing the memory dies. Non-limiting examples of internal operations associated with initialization of a memory die include internal voltage level ramping, impedance calibration, clock training, input/output (I/O) training, internal functionality checks, and adjustment of repair settings.

The pin (e.g., the reset pin) can be shared by multiple memory dies of the memory device. When the pin is shared by at least two memory dies of a memory device, in some previous approaches, the two or more memory dies may initialize concurrently. As used herein, “concurrently” refers to performing an operation performed by two or more components at approximately or nearly the same time and does not require the components to commence and/or cease performance of the operation at the same time. In some examples, “concurrently” refers to operations performed within a common time period or number of clock cycles defined by an industry standard, specification, datasheet, or the like.

In some previous approaches, in response to a memory device receiving signaling at a reset pin, memory dies of a channel of the memory device may initialize concurrently. As used herein, a “channel” of a memory device refers to a set of memory dies that share an input/output (I/O) pin of the memory device. Initialization of memory dies of a channel of a memory device may include providing signaling and/or performing operations internally associated with initializing the memory dies of the channel concurrently. Concurrent initialization of multiple memory dies may cause the memory device to experience a spike in power consumption (hereinafter referred to as a power spike). A power spike may strain a power delivery network of a memory device. As used herein, a “power delivery network” refers to one or more components of a memory device via which power is provided to memory dies of the memory device. A power spike may strain a power delivery network in its ability to provide power to meet the power needs of the memory dies during the spike in power consumption. A power spike may cause interference with memory cells of a memory die and/or memory cells of neighboring memory dies. As used herein, “neighboring memory dies” refers to memory dies that are in close, physical proximity to one another. For example, neighboring memory dies can be memory dies that are physically adjacent to one another. Neighboring memory dies can be memory dies of a rank of the memory device that are physically adjacent to a different rank of memory dies of the memory device. As used herein, a “rank” of a memory device refers to a set of memory dies that are coupled to a same chip select such that the memory dies are accessed concurrently and share a command/address pin of the memory device. Neighboring memory dies can be memory dies of a channel of a memory device that are physically adjacent to memory dies of a different channel of the memory sub-system.

Embodiments of the present disclosure address the above deficiencies and other deficiencies of previous approaches by initializing memory dies of a memory device asynchronously. In contrast to some previous approaches that may initialize multiple memory dies of a memory device in association with initialization of the memory device, a delay can be introduced in timing of signals associated with initialization of respective memory dies of a memory device so that the respective memory dies are initialized in a staggered or asynchronous manner. Initializing memory dies of a memory device in a staggered or asynchronous manner, as described herein, may increase an elapsed amount of time to initialize the memory device. However, an elapsed time to initialize a memory device in accordance with the present disclosure, which may be longer than that of some previous approaches, satisfies (e.g., falls within) a maximum amount of time (e.g., 4 milliseconds) to complete initialization of a memory device as defined by a specification of the memory device.

Embodiments of the present disclosure can reduce, or eliminate, power spikes (e.g., instantaneous power spikes), which can reduce interference between memory cells of different (e.g., neighboring) memory dies. Embodiments of the present disclosure can reduce, or eliminate, droop of a supply voltage (e.g., VDD) provided to memory dies of a memory device by a power management integrated circuit (PMIC), for example. Because the initialization operations are performed asynchronously, a resulting instantaneous current draw has a lesser amplitude than previous approaches. Embodiments of the present disclosure can improve an efficiency of initializing the memory dies. For instance, system power management can include an on-die and/or on-module power delivery network.

As used herein, the singular forms “a,” “an,” and “the” include singular and plural referents unless the content clearly dictates otherwise. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, mean “including, but not limited to.” The term “coupled” means directly or indirectly connected.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. Analogous elements within a figure may be referenced with a hyphen and extra numeral or letter. See, for example, elements123-1, . . . ,123-S inFIG.1. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be taken in a limiting sense.

FIG.1is a block diagram of an apparatus in the form of a computing system100including a memory sub-system104including memory dies108-1, . . . ,108-S and108-S+1, . . . ,108-M in accordance with a number of embodiments of the present disclosure. The memory devices108-1, . . . ,108-S and108-S+1, . . . ,108-M are collectively referred to as the memory dies108. Each of the memory dies108can be referred to as a chip. As used herein, the computing system100, a host102, the memory sub-system104, and/or the memory dies108, for example, might also be separately considered to be an “apparatus.”

As illustrated byFIG.1, the computing system100can include the host102coupled to the memory system104via an interface. The interface can communicate control signals, address signals, data, and/or other signals between the memory sub-system104and the host102. The interface can include a command/address bus112and data buses116-1, . . . ,116-N (collectively referred to as the data buses116) that couples the memory system104to the host102via one or more pins119. The memory dies108-1, . . . ,108-S can be coupled to the data bus116-1. The memory dies108-S+1, . . . ,108-M can be coupled to the data bus116-N. The data buses116can provide data for read/write operations between the host102and the memory sub-system104. In some embodiments, the command/address bus112can include separate command and address buses. In some embodiments, the command/address bus112and the data buses116can be part of a common bus. The command/address bus112can communicate signals from the host102to a controller106of the memory sub-system104such as clock signals for timing, reset signals, chip selects, addresses for the memory dies108, parity information, etc. The command/address bus112can be used by the controller106to send alert signals to the host102. The command/address bus112can be operated according to a protocol. The interface can be a physical interface employing a suitable protocol. Such a protocol may be custom or proprietary, or the interface may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z interconnect, cache coherent interconnect for accelerators (CCIX), etc. In some embodiments, the controller106is a serial presence detect (SPD) hub or simply “hub,” which may include a temperature sensor, clock functionality, isolation circuitry (e.g., an ability to isolate a bus on the module, such as a bus or buses114-1, . . . ,114-S and114-2, . . . ,114-M (collectively referred to as the buses114) from other buses or from the host102, such as via the command/address bus112and/or the data buses116). In some embodiments, the controller106is a register clock driver (RCD), such as RCD employed on an RDIMM or LRDIMM.

The memory sub-system104can include a PMIC105. The PMIC105can be configured to output one or more voltages for various operations performed by the memory sub-system104. The voltages to be output by the PMIC105can be determined based on conversion of the PMIC supply voltage to one or more reduced voltages corresponding to voltages compatible with operation of one or more components of the memory sub-system104, such as the controller106, memory components such as the memory dies108, and/or circuitry associated therewith, such as control circuitry, input/output (I/O) circuitry, address circuitry, etc. The PMIC105can apply one or more voltages to memory cells of one or more of the memory dies108. Connections between the memory dies108and the PMIC105are not illustrated byFIG.1for clarity. AlthoughFIG.1illustrates the PMIC105on the same side of the memory sub-system104as the controller106, embodiments of the present disclosure are not so limited. For example, the PMIC105can be on a opposite side of the memory sub-system104than the controller106.

The pins119can be components of the memory sub-system104. The memory system104can receive signaling indicative of commands from the host102via the pins119. For example, the memory system104can receive, via the data buses112and/or the buses116, control signals, address signals, data, and/or other signals via the pins119. The pins119can physically couple the memory system104to the computing system100. The pins119provides an interface for communication between the memory sub-system104and the computing system100. The pins119can comprises one or more metal materials, such as copper, nickel, and/or gold, among other metal materials. The pins119can include top pins (as shown) and bottom pins (not shown). The top pins and the bottom pins can include pins formed on either side of a circuit board and are not intended to limit the orientation of the pins on the memory sub-system104.

The computing system100can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Internet-of-Things (IoT) enabled device, among various other types of systems. For clarity, the computing system100has been simplified to focus on features with particular relevance to the present disclosure. The host102can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing the memory sub-system104.

The memory sub-system104can provide main memory for the computing system100or could be used as additional memory or storage for the computing system100. By way of example, the memory sub-system104can be a dual in-line memory module (DIMM) including the memory dies108operated as double data rate (DDR) DRAM, such as DDR5, a graphics DDR DRAM, such as GDDR6, or another type of memory system. Embodiments of the present disclosure are not limited to a particular type of memory of the memory sub-system104. Non-limiting examples of types of the memory dies108include RAM, ROM, SDRAM, PCRAM, RRAM, flash memory, and three-dimensional cross-point, among others. In some embodiments, the memory sub-system104can include multiple different types of memory.

A three-dimensional (3-D) cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. A 3-D cross-point array can include resistive, phase-change, or similar memory cells. A storage material of the memory cells can be a chalcogenide material, for example, in a cross-point configuration between a word line and a bit line and can be in series with a select device and/or select device material.

The controller106can be coupled to the memory dies108via respective buses114-1, . . . ,114-S and114-2, . . . ,114-M. The buses114can be referred to as internal command/address buses114(e.g., internal to the memory sub-system104) in contrast to the command/address bus112that couples the memory sub-system104to the external host102. The buses114-1, . . . ,114-S can be a shared command bus and the buses114-2, . . . ,114-M can be another shared command bus. The memory dies108can be addressed individually and independently via the buses114. A subset of the memory dies108, such as a rank or channel of the memory sub-system104, can be addressed independently via the buses114.

The controller106can be implemented as hardware, firmware, and/or software. For example, the controller106can be an application specific integrated circuit (ASIC) coupled to a printed circuit board including a physical interface. The controller106can relay command and/or address signals, clock signals, select signals, and other related signals from the host102via the command/address bus112and/or the buses114to the memory dies108. However, embodiments of the present disclosure are not so limited. In some embodiments, the memory sub-system104does not have a controller or control circuitry. Rather commands received by the memory sub-system104can be communicated, via the command/address bus112and/or the buses114, to the memory dies108. In some embodiments, a controller or control circuitry of a memory system, including the memory sub-system104, can be a component of (e.g., located on the same substrate as) the memory sub-system104such that the controller106includes the controller or control circuitry of the memory system. A controller or control circuitry of a memory system can generate command and/or address signals, which can then be relayed to the memory dies108via the command/address bus112and/or the buses114. In some embodiments, the memory sub-system104does not have a controller or control circuitry. In some embodiments, the controller106can include a registered clock driver (RCD). The RCD can buffer addresses, chip selects, clock, and reset signals, for example, received from a controller of a memory system, including the memory sub-system104, that is external to (e.g., off-module, off-substrate) the memory sub-system104.

The controller106can operate the buses114with a same or different protocol than that with which the command/address bus112is operated. The controller106command and/or address signals, clock signals, select signals, and other related signals to the memory dies108via the buses114. The memory dies108can communicate error signals, reset signals, and other related signals to the controller106via the buses114. The controller106can provide the host102with access to the memory dies108. Non-limiting examples of the commands for the memory dies108include read, write, and erase commands for data stored on the memory dies108. The memory sub-system104can include the controller106and the memory dies108on separate integrated circuits or a same integrated circuit.

As illustrated byFIG.1, each of the memory dies108can include a respective array of fuses (hereinafter “fuse arrays”)123-1, . . . ,123-S and123-S+1, . . . ,123-M. The fuse arrays123-1, . . . ,123-S and123-S+1, . . . ,123-M can be referred to collectively as the fuse arrays123. As used herein, the term “fuse” includes both fuses and antifuses. A fuse is conductive in an initial state and, when programmed (e.g., by being subjected to excessive current), makes a transition to an insulated state (e.g., the electrically conductive path breaks or is “blown”). An antifuse is insulated in an initial state and, when programmed (e.g., by being subjected to dielectric breakdown), makes a transition to a conductive state. After transition, a fuse or antifuse cannot return to its initial state and is referred to as being one-time-programmable. In some embodiments, the fuse can be a gate oxide fuse, which can be one-time-programmable by breaking a gate oxide in a metal oxide semiconductor device. Other examples of fuses include one resistor—one transistor cells and one resistor—one diode cells, among others.

Each of the fuse arrays123is a collection of addressable fuses located somewhere on a memory die (e.g., the memory die108-1). In some embodiments, there is only one fuse array123per memory die. The fuse arrays123can store manufacturing settings (e.g., repair addresses, voltage trims, timing trims, die identification, die config settings, speed settings, functions, etc.). The host102can comprise a programming module103, which can be used to, for example, program the fuse arrays123. The fuse arrays123can be programmed by a manufacturer, of the memory sub-system104prior to a deployment and/or a sale of the memory sub-system104and/or the computing system100, for example. On powerup or reset, the fuses are sensed with fuse logic circuitry (not specifically illustrated) one set at a time and broadcast on fuse bus routes (not specifically illustrated) around the die. The fuse states are then latched locally on the memory die108. The fuse arrays123can be physically separate from circuitry (not shown) in which the fuse states are latched. The circuitry can include fuse latches. The fuse latches can be latches (e.g., flip flops) that store the fuse states near other circuitry that the fuse states are used to adjust. According to at least one embodiment of the present disclosure, the fuse latches can enable/disable a delay in an initialization path based on the latched states from the fuse arrays123.

The controller106can be configured to distribute received commands to the memory dies108. Example command types include die-specific commands and all-die commands. An all-die command is a command that is intended to be executed by all the memory dies108of the memory sub-system104. In contrast, a command that is intended to be executed by a subset (one or more but not all) of the memory dies108can have a die select signal associated therewith. Commands can be received via the interface112from a host102. Typically, execution of an all-die command, such as a command associated with initializing the memory dies108(e.g., an initialization command), occurs simultaneously such that performance of operations by the memory dies108in association with execution of the all-die command occurs at least partially concurrently. However, according to at least one embodiment of the present disclosure, each fuse array123can be programmed with a different respective delay state for each respective conductive path of the memory dies108via which voltages associated with powering up the memory sub-system104are applied. The delay state can correspond to a particular amount of time in which signaling associated with initializing a memory die is provided to initialization circuitry of a memory die. The initialization circuitry (not illustrated byFIG.1) can be located at the periphery of the memory die. As used herein, “particular” refers to a specific value. For instance, a fuse array of a memory die can be programmed to cause a delay in providing signaling associated with initialization operations to initialization circuitry by a particular amount time.

Memory dies of a memory device can be organized into one or more ranks and/or one or more channels. As illustrated byFIG.1, the memory dies108of the memory sub-system104are organized into two ranks117-1and117-2. The ranks117-1and117-2can be referred to collectively as the ranks117. The rank117-1includes the memory dies108-1, . . . ,108-S and the rank117-2includes the memory dies108-2, . . . ,108-M. The memory dies of a rank can share a command path from a controller to the memory dies of that rank. Thus, the memory dies108-1, . . . ,108-S of the rank117-1can share a command path from the controller106and the memory dies108-2, . . . ,108-M of the rank117-2can share a different command path from the controller106. However, memory dies of a rank can be individually addressed via a shared command path.

The memory dies108of the memory sub-system104are organized into two channels118-1and118-2. The channel118-1includes the ranks117-1and117-2and the memory dies associated therewith. Although not fully illustrated byFIG.1, the channel118-2includes the ranks of memory sub-system104physically located on the opposite side of the memory sub-system108from the channel118-1.

FIG.2illustrates an example of an initialization path230in accordance with a number of embodiments of the present disclosure. The initialization path230includes an input231and an output232. The input and output can be on any portion of an initialization path of a memory die (e.g., the memory die108-1described in association withFIG.1). Between the input and output are three delay blocks236-1,236-2, and236-3(referred to collectively as the delay blocks236). The initialization path230also includes a delay trim input233. The delay trim input233represents the latched fuse states, which are used to select an amount of delay in the initialization path230. The delay trim input233can select or activate any combination of the delay blocks236via selector blocks234-1,234-2, and234-3. The delay trim input233is illustrated as being connected to three different delay selector blocks234-1,234-2, and234-3, any combination of which can be selected with the delay trim input233to vary the total delay applied between the input231and the output232. As illustrated, eight different individual delays are selectable with three different delay states235. Embodiments are not limited to three delay states as other quantities of delay states are possible.

By way of example, the delay blocks236can represent inverters added in series to delay a signal, however embodiments are not limited to this example. The delay trim input233can activate the selector blocks234, which can be multiplexed with the delay blocks236to effectively create an addressable or selectable variable delay path between the input231and the output232.

FIG.3illustrates an example flow diagram of a method340for delaying, at a memory die, initialization of the memory die in accordance with a number of embodiments of the present disclosure. The method340can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or combinations thereof. In some embodiments, the method340is performed by one or more memory dies108of a memory sub-system104described in association withFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block342, the method340can include receiving, by a memory device, signaling indicative of a command to initialize a plurality of memory dies of the memory device.

At block344, the method340can include delaying, at a memory die of the plurality of memory dies and based on fuse states of an array of fuses of the memory die, initialization of the memory die by an amount of time relative to receipt of the signaling by the memory device. Delaying the initialization of the memory die can include programming the array of fuses so as to cause providing signaling associated with initialization operations to initialization circuitry of the memory die to be delayed by the amount of time.

Although not specifically illustrated byFIG.3, the method340can include delaying, at a different memory die of the plurality of memory dies and based on fuse states of a different array of fuses of the different memory die, initialization of the different memory die by a different particular amount of time relative to receipt of the signaling by the memory device. The method340can include delaying, at a different memory die of the plurality of memory dies and based on fuse states of a different array of fuses of the different memory die, initialization of the different memory die by the particular amount of time subsequent to initialization of the memory die.

FIG.4illustrates an example flow diagram of a method450for delaying, at a memory die, initialization of the memory die in accordance with a number of embodiments of the present disclosure. The method450can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or combinations thereof. In some embodiments, the method450is performed by one or more memory dies108of a memory sub-system104described in association withFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block451, the method450can include providing first signaling associated with initializing a memory device to a first memory die of a memory device and a second memory die of the memory device concurrently.

At block452, the method450can include providing, based on fuse states of a first array of fuses of the first memory die, second signaling associated with internal initialization operations to initialization circuitry of the first memory die.

At block453, the method450can include providing, based on fuse states of a second array of fuses of the second memory die, third signaling associated with internal initialization operations to initialization circuitry of the second memory die subsequent to a first amount of time relative to providing the second signaling.

Although not specifically illustrated byFIG.4, the method450can include propagating the second signaling via a first initialization path of the first memory die in a second amount of time. The second amount of time can be different than the first amount of time. The method450can include propagating the third signaling via a second initialization path of the second memory die in the first amount of time. The method450can include providing the first signaling to the first and second memory dies in response to signaling indicative of an initialization command being received by the memory device. The method450can include providing the first signaling to the first memory die, the second memory die, and a third memory die of the memory device concurrently. Fourth signaling associated with internal initialization operations can be provided to initialization circuitry of the third memory die, based on fuse states of a third array of fuses of the third memory die, subsequent to a second amount of time relative to providing the third signaling. The second amount of time can be different than the first amount of time. The method450can include propagating the fourth signaling via a third initialization path of the third memory die in the second amount of time.

FIG.5illustrates an example flow diagram of a method560for fabricating a memory device in accordance with a number of embodiments of the present disclosure. The method560can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or combinations thereof. One or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block562, the method560can include fabricating memory dies, each including a respective fuse array. The memory dies can be mass produced and then coupled into any number of memory packages as desired. The memory dies include memory arrays. The fuse arrays can be fabricated generically (e.g., without specific programming) and later programmed with device-specific settings. The memory dies can be fabricated with latches configured to store settings that are programmed into the fuse arrays.

At block564, the method560can include programming the fuse arrays with a respective delay state for initialization of each of the plurality of memory dies asynchronously. Programming a fuse array can include changing a conductive state of at least one element (e.g., fuse or anti-fuse) of the array. The fuse array can be programmed (e.g., by a manufacturer of the memory package, or by an intermediate party between the manufacturer and the end-user) prior to shipping the memory package. This allows the fuse arrays to be fabricated generically (at least with respect to programmed delay states) to facilitate efficient production. Subsequently, the delay states can be programmed into the fuse array as desired for any specific memory package or series of memory packages (such as a line of products). The fuse arrays can also store other operational settings for the dies.

FIG.6illustrates an example a computer system690within which a set of instructions, for causing the machine to perform various methodologies discussed herein, can be executed. In various embodiments, the computer system690can correspond to a system (e.g., the computing system100described in association withFIG.1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system104). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The example computer system690includes a processing device691, a main memory693(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory697(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system698, which communicate with each other via a bus696.

The data storage system698can include a machine-readable storage medium699(also known as a computer-readable medium) on which is stored one or more sets of instructions692or software embodying any one or more of the methodologies or functions described herein. The instructions692can also reside, completely or at least partially, within the main memory693and/or within the processing device691during execution thereof by the computer system690, the main memory693and the processing device691also constituting machine-readable storage media.