Semiconductor device

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure. At least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along a length direction of the longitudinal gap.

BACKGROUND

A key component in semiconductor application is a solid-state switch. As an example, switches turn loads of automotive applications or industrial applications on and off. Solid-state switches typically comprise, for example, field effect transistors (FETs) like metal-oxide-semiconductor FETs (MOSFETs) or insulated gate bipolar transistors (IGBTs).

In these applications, a damage of a gate dielectric between gate and source of the transistors may be caused by an electrostatic discharge event between a gate contact area and a source contact area of the semiconductor device. To protect the gate dielectric from an electrostatic discharge event, electrostatic discharge (ESD) protection structures are provided, which protect the transistors from electrostatic discharge during assembly or operation, for example. These ESD protection structures require non-negligible area within the integrated semiconductor device.

It is therefore desirable to provide a semiconductor device structure with enhanced ESD protection characteristic and optimized area efficiency.

SUMMARY

According to an embodiment, a semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises a transistor structure in the semiconductor body. A source contact structure is overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure. At least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along a length direction of the longitudinal gap.

DETAILED DESCRIPTION

The term “electrically connected” describes a permanent low ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element (s) adapted for signal transmission may be provided between the electrically coupled elements, for example resistors, resistive elements or elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.

FIG. 1is a schematic perspective view of a portion of a semiconductor device in accordance with an embodiment.

The semiconductor device10comprises a semiconductor body100having a first surface101and a second surface102opposite to the first surface101. The semiconductor device10further comprises a transistor structure1000in the semiconductor body100. A source contact structure700is provided, which overlaps the transistor structure1000. The source contact structure700is electrically connected to source regions150of the transistor structure1000. The source contact structure may comprise a source pad. A gate contact structure500is provided, which has a part separated from the source contact structure700by a longitudinal gap G within a lateral plane. Gate interconnecting structures320bridge or overlap the longitudinal gap G and are electrically coupled between the gate contact structure500and the gate electrode330of the transistor structure1000. In addition, electrostatic discharge protection structures310are provided, which bridge or overlap the longitudinal gap G. The electrostatic discharge protection structures310are electrically coupled between the gate contact structure500and the source contact structure700. At least one of the gate interconnecting structures320is between two of the electrostatic discharge protection structures310along the length direction L of the longitudinal gap G.

By providing at least one of the gate interconnecting structures320between two of the electrostatic discharge protection structures310along the length direction L of the longitudinal gap G, a gate current from the gate contact structure500via the gate interconnecting structures320to the gate electrode330can still distribute homogenously all over the active area of the gate electrode330, while maximizing, at the same time, the total diode width of the electrostatic discharge protection structures310. According to an embodiment, at least one of the electrostatic discharge protection structures310may be between two of the gate interconnecting structures320along the length direction L of the longitudinal gap G.

FIG. 2is a schematic plan view of a portion of the semiconductor device10in accordance with an embodiment.

The semiconductor device10may comprise power semiconductor elements such as IGBTs (insulated gate bipolar transistors), e.g. RC-IGBIs (reverse-conducting IGBTs), RB-IGBT (reverse-blocking IGBTs), and IGFETs (insulated gate field effect transistors) including MOSFETs (metal oxide semiconductor field effect transistors). The semiconductor device10may also comprise a superjunction transistor, a trench field effect transistor, or any further transistor device controlling a load current via a gate terminal. When reducing the chip size of the semiconductor device10, a smaller input capacitance results in an enhanced risk of damage caused by an electrostatic discharge event between the gate and the source of the semiconductor device10.

In the plan view ofFIG. 2, the longitudinal gap G is extended between an edge portion of the source contact structure700and an edge portion of the gate contact structure500. The normal to the first and second surfaces101,102defines a vertical direction and directions orthogonal to the normal direction are lateral directions within the lateral plane. The longitudinal gap G is extended along the length direction L, wherein the length direction L of the longitudinal gap G has to be understood as a direction parallel to a straight line, which does not cross parts of the source contact structure700and/or the gate contact structure500in a lateral plane. In other words, the longitudinal gap G has a bigger extension in a lateral plane parallel to edge portions of the source contact structure700and the gate contact structure500in comparison to its extension along a direction orthogonal to or facing the edge portions of the source contact structure700and the gate contact structure500.

FIGS. 3 and 4are schematic cross-sectional views of portions of a semiconductor device taken along the section planes B-B′ and A-A′ ofFIG. 2, respectively.

The semiconductor body100may be provided from a single-crystalline semiconductor material, for example silicon Si, silicon carbide SiC, germanium Ge, a silicon germanium crystal SiGe, gallium nitride GaN or gallium arsenide GaAs. A distance between the first and second surfaces101,102is selected to achieve a specified voltage blocking capability and may be at least 5 μm, or may be at least 20 μm, for example at least 50 μm. Other embodiments may provide a semiconductor body100with a thickness of several 100 μm. The semiconductor body100may have a rectangular shape with an edge length in the range of 500 μm up to several millimeters.

The semiconductor body100may comprise, as will be further described in view ofFIG. 5, a drain region110and a drift region120. The semiconductor device10may comprise a first isolation layer200on the first surface101of the semiconductor body100, wherein the electrostatic discharge protection structures310and the gate interconnection structures320are abutting the first isolation layer200. The first isolation layer200may be formed on the first surface101of the semiconductor body100. The first isolation layer200may include any dielectric or a combination of dielectrics adapted to isolate the semiconductor body100from the electrostatic discharge protection structures310, the gate interconnecting structures320or the gate electrode330on the first isolation layer200. The first isolation layer200may include one or any combination of an oxide, nitride, oxynitride, a high-k material, an imide, an insulating resin or glass, for example. The first isolation layer200may include a field oxide formed e.g. by thermal oxidation or deposition or by a local oxidation of silicon (LOGOS) process or STI (shallow trench isolation).

As can be seen fromFIGS. 3 and 4, the first isolation layer200may comprise a field dielectric layer210. In particular, the first isolation layer200may include a field dielectric, such as a field oxide in an overlap area between the electrostatic discharge protection structures310or the gate interconnecting structures320and the semiconductor body100and may further include a gate dielectric such as a gate oxide in an overlap area between the source contact structure700and the semiconductor body100within an area of the transistor structure1000. The thickness of the field dielectric of the first isolation layer200may be in a range of 0.5 μm to 5 μm or 1 μm to 3 μm, the thickness of the gate dielectric of the first isolation layer200may be in a range of 5 nm to 200 nm or 40 nm to 120 nm.

The semiconductor device10may further comprise a second isolation layer400on the electrostatic discharge protection structures310and the gate interconnecting' structures320, wherein the source contact structure700and the gate contact structure500are formed on the second isolation layer400. The second isolation layer400may be formed on the electrostatic discharge protection structures310, the gate interconnecting structures320and the gate electrode330. The second isolation layer400may comprise a stack of dielectric layers. Herein, a first dielectric layer of the second isolation layer400may include a tetraethylorthosilicate (TEOS)/undoped silicate glass (USG) film. The thickness of the first dielectric layer of the second isolation layer400may be in a range of 50 nm to 500 nm. A second dielectric layer of the second isolation layer400may include a phosphosilicate glass (PSG) or a borophosphosilicate glass (BPSG). The thickness of the second dielectric layer of the second isolation layer400may be in a range of 200 nm to 2 μm.

The gate contact structure500may be formed on the second isolation layer400. Next to the gate contact structure500, the source contact structure700may be formed on the second isolation layer400, which is spaced apart from a part of the gate contact structure500by the longitudinal gap G. On the gate contact structure500and the source contact structure700, a further passivation layer may be formed, which may include one or any combination of an imide, a nitride, an oxide or an oxynitride, for example.

As can be further seen fromFIGS. 3 and 4, first terminals312of the electrostatic discharge protection structures310and terminals322of the gate interconnecting structures320may be electrically connected with the gate contact structure500by a first electric contact structure610. In addition, second terminals314of the electrostatic discharge protection structures310may be electrically connected with the source contact structure700by second electric contact structures620. The first and second electric contact structures610,620may extend along a vertical direction through the second isolation layer400. As can be seen fromFIG. 5, third electric contact structures630may be provided to interconnect the source contact structure700with the source regions150of the transistor structure1000.

The gate contact structure500may comprise a metal. In addition, the source contact structure700may comprise a metal. The source contact structure700and the gate contact structure500may be patterned parts of a same conductive material. The gate contact structure500and the source contact structure700may be separate parts, e.g. due to lithographic patterning, of a common metal wiring layer or stacked layer. The gate contact structure500and the source contact structure700may be formed as a metal layer structure including the first to third electric contact structures610,620and630. Such a metal layer structure may consist of or contain, as main constituent(s), aluminum Al, copper Cu or alloys of aluminum or copper, for example AlSi, AlCu, or AlSiCu. According to other embodiments, the gate contact structure500and the source contact structure700may contain one, two, three or more sub-layers, each sub-layer containing, as a main constituent, at least one of nickel Ni, titanium Ti, silver Ag, gold Au, tungsten W, platinum Pt and palladium Pd. For example, a sub-layer may contain a metal nitride or a metal alloy containing Ni, Ti, Ag, Au, W, Pt, Pd and/or Co.

The gate interconnecting structures320may comprise a polysilicon layer300. Herein, the gate interconnecting structures320and the electrostatic discharge protection structures310may be distinct parts of a same patterned polysilicon layer300. It is, however, also possible that the gate interconnecting structures320and the electrostatic discharge protection structures310are formed in different depositing steps. As can be seen from the plan view ofFIG. 2, the gate interconnecting structures320and the gate electrode330may be integrally formed as a same electrode layer of polysilicon. Herein, the gate interconnecting structures320may be formed as comb segments protruding from the electrode layer of the gate electrode330in the lateral plane. In such a structure, the electrostatic discharge protection structures310may be arranged between the gate interconnecting structures320constituting the comb segments protruding from the electrode layer of the gate electrode330in the lateral plane. The electrostatic discharge protection structures310and the gate interconnecting structures320are not necessarily arranged in an alternating order. However, at least one of the gate interconnecting structures320is between two of the electrostatic discharge protection structures310along the length direction L of the longitudinal gap G.

As can be seen fromFIG. 3, the electrostatic discharge protection structures310may comprise the polysilicon layer300having first and second regions316,318of opposite conductivity type alternatingly arranged along a lateral direction being perpendicular to the length direction L of the longitudinal gap G. Thus, the electrostatic discharge protection structures310may include at least one polysilicon diode having the first and second regions316,318connected in series. Herein, the resulting diode may be bidirectional, having an odd number of first and second regions316,318, e.g. a n-p-n- . . . -p-n structure. The resulting diode may also be unidirectional, having an even number of first and second regions316,318, e.g. a n-p-n- . . . -p structure.

In detail, the electrostatic discharge protection structures310may be manufactured by forming the polysilicon layer300of a first conductivity type on the first isolation layer200. After forming the polysilicon layer300, a mask layer (not shown), e.g. a hard mask layer or a resist layer is formed on the polysilicon layer300and is patterned by a lithographic process, such that the second regions318are not covered by the mask layer. In a subsequent implantation process, dopants of a second conductivity type are introduced into the exposed second regions318not covered by the mask layer on the polysilicon layer300, to form the second regions318of the second conductivity type. Thus, each of the first regions316and second regions318comprises first dopants of the first conductivity type, and the second regions318further comprise second dopants of the second conductivity type overcompensating the first dopants of the first conductivity type. In another embodiment, each of the first regions316may comprise first dopants of the first conductivity type and the second regions318may comprise second dopants of the second conductivity type only, without overcompensating the first dopants of the first conductivity type. Herein, the first dopants are introduced into the first regions316and the second dopants are introduced into the second regions318, respectively, in a separate process, e.g. by ion implantation and/or diffusion, wherein overlapping regions between the first and second regions316,318may comprise first and second dopants due to diffusion of the dopants.

As a result, a polysilicon diode chain or string arranged in a lateral direction having alternating pn-junctions (diodes) at the region boundaries of the first and second regions316,318in the polysilicon layer300is formed. In an embodiment, the doping concentrations of the first and second regions316,318are adapted such that a series connections of Zener diodes are formed within the polysilicon layer300. By the number of consecutive diodes each including a first region316and a second region318, the breakdown voltage of the electrostatic discharge protection structures310can be adjusted.

FIG. 5is a schematic cross-sectional view of a portion of a semiconductor device10taken along the section plane A-A″ ofFIG. 2. As can be seen fromFIG. 2, the part of the semiconductor device10taken along the section plane A-A″ illustrates the transistor structure1000of the semiconductor device10. The transistor structure1000comprises transistor cells1100arranged in an overlapping area between the source contact structure700and the semiconductor body100. Each of the transistor cells1100comprise the gate electrode330formed on the first isolation layer200constituting a gate dielectric layer220, the source regions150being in contact with the first surface101of the semiconductor body100and extending into the semiconductor body100, and body regions160, in which the source regions150are embedded. The source regions150are of the first conductivity type and the body regions160are of the second conductivity type. Furthermore, the drain region110of the first conductivity type is provided at the second surface102of the semiconductor body100. The drift region120is formed between the drain region110and the body regions160and is of a first conductivity type. In case of a superjunction device, columns or bubbles of the first conductivity type and the second conductivity type can be implemented both beneath the active transistor cell field of the transistor structure1000and an edge termination area900, as will be discussed in more detail with regard toFIGS. 9 and 10.

According to an embodiment, the gate electrode330is formed simultaneously with the gate interconnection structures320and may be part of the polysilicon layer300. According to a further embodiment, the gate electrode330may be formed simultaneously with the gate interconnecting structures320and the electrostatic discharge protection structures310and may be part of the polysilicon layer300. The third electric contact structure630may electrically couple the source regions150to the source contact structure700.

As can be seen fromFIGS. 2 to 5, a semiconductor device10is provided, in which the connection structure between a gate contact structure500and a gate electrode330is optimized in view of the electrostatic discharge protection capabilities. Due to the provision of a plurality of electrostatic discharge protection structures310and gate interconnecting structures320, the total diode width being the summed up width of all electrostatic discharge protection structures310is maximized, wherein at the same time, a homogeneous distribution of gate current from the gate contact structure500to the gate electrode330is preserved.

According to an embodiment, at least two gate interconnecting structures320and at least three electrostatic discharge protection structures310may be arranged along the length direction L of the longitudinal gap G. According to another embodiment, at least three gate interconnecting structures320and at least four electrostatic discharge protection structures310may be arranged along the length direction L of the longitudinal gap G. According to yet another embodiment, at least four gate interconnecting structures320and at least five electrostatic discharge protection structures310may be arranged along the length direction L of the longitudinal gap G.

According to an embodiment, an extension of each of the electrostatic discharge protection structures310along the length direction L of the longitudinal gap G may be below 10000 μm, or may be below 1000 μm, or may be below 800 μm, or may be below 500 μm, or may be below 200 μm, or may be below 100 μm, or may be below 50 μm, or may be below 10 μm.

The gate interconnecting structures320and the electrostatic discharge protection structures310may have a same extension along the length direction L of the longitudinal gap G.

Although not shown inFIG. 2, the transistor structure1000may also be formed in an overlapping area between the gate contact structure500and the second surface102of the semiconductor body100. That means that also the area under the gate contact structure500may be used as an active transistor and hence further reducing the total chip size.

FIG. 6is a schematic plan view of a portion of the semiconductor device10in accordance with an embodiment. As can be seen fromFIG. 6, the gate contact structure500may comprise a gate line510and a gate pad520. The gate pad520and the gate line510may be formed of a metal. According to the embodiment ofFIG. 6, the source contact structure700, the gate contact structure500comprising the gate line510and the gate pad520, as well as a drain line800may be formed as separate parts of a patterned metal wiring layer or metal wiring stacked layer.

As can be further seen fromFIG. 6, there are different parts of the gate contact structure500, in which a longitudinal gap G between the gate contact structure500and the source contact structure700may be formed. In the following, two detailed portions C and D will be explained hereinafter. However, it should be emphasized that the two described locations of the longitudinal gap G in the sections C and D shall not be understood as restrictive. Rather, the longitudinal gap G within the lateral plane parallel to the first surface101may be arranged between a part of the gate pad520and the source contact structure700. However, as will be discussed in all detail later, the longitudinal gap G may also be arranged between a part of the gate line510and the source contact structure700. The gate line510may be a so-called gate runner structure at an edge portion of the semiconductor device10. The gate line510may, however, also be a gate finger structure arranged within a transistor cell array of the semiconductor device10. According to an embodiment, the gate line510may surround at least partly the source contact structure700within the lateral plane. Herein, the longitudinal gap G may be formed in an edge termination area900, as can be seen, for example inFIGS. 9 and 10.

As can be further seen fromFIG. 6, there are six parts of the gate contact structure500and the source contact structure700, at which longitudinal gaps G may be formed, since at these portions, the edge portions of the gate contact structure500and the source contact structure700are extended in a parallel direction. Furthermore, the gate contact structure500and the source contact structure700may be spaced apart equidistantly, leading to longitudinal gaps G having a constant extension along a direction orthogonal to the length direction L of a respective longitudinal gap G.

As can be seen fromFIG. 6, the six longitudinal gaps G are connected to form a closed loop of longitudinal gaps G. The closed loop of gaps G form a total gap TG. The total gap TG is, however, not restricted to be a closed loop. The total gap TG may also comprise all parts of gaps or longitudinal gaps G, which are formed between the gate contact structure500and the source contact structure700.

According to an embodiment, all longitudinal parts of the total gap TG may be used for implementing an alternating structure of gate interconnecting structures320and electrostatic discharge protection structures310. Due to the concept of providing a plurality of electrostatic discharge protection structures310each having a diode width smaller than 50 μm, instead of employing a small number of electrostatic discharge protection structures310having a diode width greater than, for example, 100 μm, a homogeneous distribution of the gate current from the gate line510into the gate electrode330of the transistor structure1000may be achieved, while maximizing, at the same time, the total diode width of all electrostatic discharge protection structures310interconnected between the gate contact structure500and the source contact structure700along the total gap TG at parts of the gate contact structure500, which form a longitudinal gap G with the source contact structure700. The maximal length of a longitudinal gap G along an edge part of the semiconductor device10may be in a range between 500 μm and 10000 μm, the maximal length of the total gap TG may be in a range between 2000 μm and 40000 μm.

According to an embodiment, the ratio of total diode width of all electrostatic discharge protection structures310arranged along the total gap TG and the total width of all gate interconnecting structures320arranged along the total gap TG may be bigger than 30%, or may be bigger than 40%, or may be bigger than 50%, or may be bigger than 60%, or may be bigger than 70%, or may be bigger than 60%. The total diode width of the electrostatic discharge protection structures310shall be defined as the sum of all singular extensions along a direction parallel to the length direction L of a respective longitudinal gap G bridged by the respective electrostatic discharge protection structures310to be summed up over the total gap TG. The total width of all gate interconnecting structures320shall be defined as the sum of all singular extensions of gate interconnecting structures320along a direction parallel to the length direction L of a respective longitudinal gap G bridged by a respective gate interconnecting structure320within the total gap TG.

The number of gate interconnecting structures320arranged along the total gap TG, i.e. along all longitudinal gaps G between the gate contact structure500and the source contact structure700, may be equal to or higher than 3, or may be equal to or higher than 5, or may be equal to or higher than 7, or may be equal to or higher than 10, or may be equal to or higher than 15, or may be equal to or higher than 20, or may be equal to or higher than 50, or may be equal to or higher than 100.

The number of electrostatic discharge protection structures310arranged along the total gap TG, i.e. along all longitudinal gaps G between the gate contact structure500and the source contact structure700, may be equal to or higher than 3, or may be equal to or higher than 5, or may be equal to or higher than 7, or may be equal to or higher than 10, or may be equal to or higher than 15, or may be equal to or higher than 20, or may be equal to or higher than 50, or may be equal to or higher than 100.

According to an embodiment, the total number of the electrostatic discharge protection structures (310) arranged along all gaps or longitudinal gaps (G) forming the total gap (TG) is equal to or higher than 3, or 5, or 7, or 10, or 15, or 20, or 50, or 100, and wherein the total number of the gate interconnecting structures320arranged along all gaps or longitudinal gaps (G) forming a total gap (TG) is equal to or higher than 3 or 5, or 7, or 10, or 15, or 20, or 50, or 100.

Thus, according to an embodiment, electrostatic discharge protection structures310are not only integrated in a gate pad region of the gate pad520, but are also prolongated into an edge termination area900. According to an embodiment, a monolithic integration of a polysilicon Zener diode between source and gate runner metallization in a high voltage edge termination area of a power device is provided without spending additional chip area or at least with minimized area adder. For the modelling and for reliability of switching behaviour of the power chips it is important, that the capacitive and resistive network of the power chip system (metallization, contacts, gate runner, gate polysilicon stripes) stays unchanged when selling products with and without Zener diodes to the market. Therefore, a design of a Zener diode in an edge termination area between gate runner and source metal pad is proposed that alternates with interruptions of the Zener diode, where the regular gate poly connects the metal gate runner with the gate poly in an active chip area.

FIGS. 7 and 8are schematic plan views of sectional portions C and D of a semiconductor device10ofFIG. 6. In these Figures, the layout principle of the construction according to an embodiment is demonstrated. The electrostatic discharge protection structure310, which may be formed as a Zener diode (Zener polysilicon with n- and p-implants) may be contacted between the gate line510or gate ring and the source contact structure700or source via the first and second electric contact structures610,620, which may be formed as poly plugs or metal contacts. In order to allow a gate signal flow from the gate line510or gate runner to the active gate polysilicon of the gate electrode330via the gate interconnecting structures320comprising polysilicon, the electrostatic discharge protection structure310have to be interrupted in regular intervals by the gate interconnecting structures320. Since there is at least 10 μm wide polysilicon layer in the gate electrode330before the small polysilicon bridges of gate current distributing cells910, the gate current can still distribute homogeneously all over the active area of the gate electrode330as in a standard edge design without an electrostatic discharge protection structure.

The gate current distributing cells910comprise third electric contact structures630between a source contact structure700and a well region920, as can be seen from.FIGS. 9 and 10. As can be further seen from comparison ofFIG. 7andFIG. 8, the third electric contact structures630for connecting the source contact structure700with the source regions150are formed as interrupted stripes being extended perpendicular to a first lateral direction x, whereas the gate current distributing cells910are arranged as longitudinally extended third electric contact structures630being arranged in parallel to corresponding gate interconnecting structures320and electrostatic discharge protection structures310.

Thus, according toFIG. 7showing a detailed section C ofFIG. 6, the layout construction of the electrostatic discharge protection structures310and the gate interconnection structures320is such in the edge termination area900that the gate line510or gate runner being extended along the first lateral direction x is perpendicular to the stripes of the third electric contact structure630of the transistor cells1100of the transistor structure1000.

According toFIG. 8showing a detailed section D ofFIG. 6, the layout construction of the electrostatic discharge protection structures310and the gate interconnecting structures320is such that the gate line510or the gate runner extended along a second lateral direction y (being perpendicular to the first lateral direction x) is parallel to the stripes of the third electric contact structures630of the transistor cells1100of the transistor structure1000.

FIGS. 9 and 10are schematic cross-sectional views of portions of a semiconductor device10taken along the section planes E-E′ and F-F′ ofFIG. 8, respectively. As can be seen from the comparison ofFIGS. 9 and 10,FIG. 9depicts a cross-sectional view of a portion including one of the electrostatic discharge protection structures310, whereasFIG. 10depicts a cross-sectional view of a portion including one of the gate interconnecting structures320. In the following, only features of the semiconductor device10, which have not yet been described with regard toFIG. 2 to 5, will be described.

As can be seen fromFIG. 9andFIG. 10, the third electric contact structures630vertically extend along the vertical direction z through the second isolation layer400and the gate electrode330, which is formed by the polysilicon layer300, and the first isolation layer200into the semiconductor body100, to electrically connect the source contact structure700with the source regions150. To prevent a shortcut between the third electric contact structures630and the gate electrode330, contact holes being extended through the gate electrode330are further isolated by an dielectric lining layer410.

The third electric contact structures630of the gate current distributing cells910are extended through the second isolation layer400, the gate electrode330having the dielectric lining layer410for insulating the third electric contact structure630from the gate electrode330, and the first isolation layer200into the semiconductor body100, to contact the source contact structure700with the well region920of a second conductivity type. The conductivity types of the source regions150, the body regions160or further structures of the transistor cells1100may be as described above with regard toFIG. 5.

As can be further seen fromFIGS. 9 and 10, the electrostatic discharge protection structures310and the gate interconnection structures320are formed on the field dielectric, layer210within the edge termination area900of the semiconductor device10. In other words, the first isolation layer200is formed as a gate dielectric220within the active area of the transistor structure1000, whereas the first isolation layer200is formed as a field dielectric layer210within the edge termination area900. Furthermore, columns or bubbles1010of the first conductivity type and columns or bubbles1020of the second conductivity type may be implemented beneath the active transistor cell field of the transistor structure1000. In addition, columns or bubbles930of the first conductivity type and columns or bubbles940of the second conductivity type may be implemented beneath the well region920of the edge termination area900.

FIGS. 9 and 10show thus principle cross-sectional views of an edge termination construction with an integrated Zener diode and an alternating interruption of the diode, where the gate ring or gate runner or gate line510is connected to the active gate polysilicon layer or gate electrode330in the active area of the transistor structure1000such as in a standard edge termination area. In the region of the gate current distributing cells910, the active gate polysilicon layer of the gate electrode330is arranged in stripes that allow for source contacts.

The alternating sequence of Zener diode and gate connection can be used around the whole chip and enables much higher diode width than in the case where the diode is arranged only around 2 or 3 sides of the gate pad520. The increased diode width leads to enhanced ESD-HBM (electrostatic discharge—human body model) capability at the same or at least nearly the same chip area in case the diode length has to be chosen so that the standard edge termination length as not increased. Assuming a breakdown current of 1 mA per μm diode width, a robustness of the electrostatic discharge protection structures310with respect to HBM (Human Body Model) tests may be in a range of 200 V to 5 kV.

According to an embodiment, edge portions of the gate interconnecting structures320and edge portions of the electrostatic discharge protection structures310are each arranged along a same line parallel to the length direction L of the longitudinal gap G. By providing edge portions of the gate interconnecting structures320and the electrostatic discharge protection structures310being flush with each other, a homogenous termination of the polysilicon layer300constituting the gate interconnecting structures320and the electrostatic discharge protection structures310and forming, at the same time, a field plate structure, may be achieved. Thus, a homogenous electric field in the edge termination area900may be achieved.

In addition, the first electric contact structure610electrically connecting the first terminals312of the electrostatic discharge protection structures310and the terminals322of the gate interconnecting structures320with the gate contact structure500may be longitudinally extended along the length direction L of the longitudinal gap G while being interrupted along the length direction L of the longitudinal gap G to separately electrically contact the electrostatic discharge protection structures310and the gate interconnecting structures320. Thus, the first contact structure610may be longitudinally extended and interrupted along the length direction L of the longitudinal gap G to separately electrically contact the electrostatic discharge protection structures310and the gate interconnecting structures320. By providing the first electrical contact structure610being longitudinally extended along the length direction L of the longitudinal gap G, a homogenous electrical contact structure of the gate interconnecting structures320and the electrostatic discharge protection structures310may be achieved. Thus, a homogenous electric field in the edge termination area900may be achieved.

As can be further seen fromFIGS. 9 and 10, the drain line800is connected to a drain connection column820within the semiconductor body100by means of a fourth electric contact structure810, which is vertically extended through the second isolation layer400, the polysilicon layer300and the first isolation layer200into the semiconductor body100. The drain connection column820are of a first conductivity type and are extended from the first surface101to the second surface102of the semiconductor body100, to contact the drain region110on the second surface102with the drain line800formed over the first surface101of the semiconductor body100.

FIG. 11is a schematic flow diagram for illustrating a method2000of manufacturing a semiconductor device.

It will be appreciated that while method2000is illustrated and described below as a series of acts or events, the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects of embodiments of the disclosure herein. Also, one or more of the acts depicted herein may be carried out in one or more separate act and/or phases.

A schematic flow diagram for illustrating a method2000of manufacturing a semiconductor device is depicted inFIG. 11.

Process feature S100comprises forming a transistor structure in a semiconductor body having a first surface and a second surface opposite to the first surface.

Process feature S110comprises forming a source contact structure overlapping the transistor structure, wherein the source contact structure is electrically connected to source regions of the transistor structure.

Process feature S120comprises forming a gate contact structure having a part separated from the source contact structure by a longitudinal gap within a lateral plane.

Process feature S130comprises forming gate interconnecting structures bridging the longitudinal gap and electrically coupled between the gate contact structure and a gate electrode of the transistor structure.

Process feature S140comprises forming electrostatic discharge protection structures bridging the longitudinal gap and electrically coupled between the gate contact structure and the source contact structure, wherein at least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along the length direction of the longitudinal gap.

One advantage of the possible integration of the electrostatic discharge protection structures310in the edge termination area900and not around the gate pad520may be the fact that the gate pad520could also be arranged on a gate oxide or gate dielectric layer220or be even used as an active gate pad. An active gate pad structure is an embodiment of a semiconductor device, in which the semiconductor device10further comprises a transistor structure1000formed in an overlapping area of the gate contact structure500and the second surface102of the semiconductor body100. By such a structure, the total chip size is further reduced keeping the same electrical performance like before.

According to an embodiment, electrostatic discharge protection structures310are monolithically integrated in a high voltage edge termination. The diode width can be at least 50% or 30% of the edge termination width, which provides high HBM-ESD-capabilities (>1 kV; even for small product chips with an active area of 0.5 mm2. Thus, the electrostatic discharge protection capability is significantly larger as compared to electrostatic discharge protection structures integrated only in a gate pad520between source and gate metallization. Since such an embodiment is a pure design measure, there is no increase in process cost.

A former edge termination topology and total chip area of a semiconductor device10stays nearly unchanged due to the nearly identical RC gate network of gate polysilicon, metallization and contact topology of the transistor layout. This has advantages concerning the—identical—switching behaviour of power MOSFET devices both with and without Zener diodes.

The edge termination structure according to an embodiment with integrated electrostatic discharge protection structures310is also applicable for power technology with trench gates and IGBT's. An additional advantage can be seen in that the electrostatic discharge protection structures310are placed in the transistor high voltage edge termination area900. Because of this, the gate pad region needs no field oxide anymore. This means, that active gate pad devices can be integrated even with very high ESD robustness.