An oscillation-stop detection circuit includes a switching unit that repeats turning on and off based on a cycle of an oscillation signal from an outside; a capacitor that is charged when the switching unit is turned on, and discharged when the switching unit is turned off; a first MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged; a discharge cutoff unit that cuts off a discharge path for the discharge current to flow, for a predetermined time right after a power is turned on; and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor.

BACKGROUND OF THE INVENTION

1) Field of the Invention

The present invention relates to a technology for detecting a stop of oscillation of an internal oscillation circuit of an electronic device.

2) Description of the Related Art

Normally, an electronic device including an internal oscillation circuit is provided with an oscillation-stop detection system. As for a clock driven by a battery, for example, a clock integrated-circuit (IC) employs a crystal oscillation circuit. While the crystal oscillation circuit is in an oscillation state, a regulated voltage obtained by dropping a power supply voltage of the clock IC using a regulator is used as a power supply of the crystal oscillation circuit. This is intended to reduce current consumption.

On the other hand, when restarting the crystal oscillation circuit that is in an oscillation stop state, the power supply voltage of the clock IC is used for a prompt and certain start of the oscillation. After restarting the oscillation, the crystal oscillation circuit is driven by the regulated voltage. For this mechanism to work, the oscillation-stop detection system detects a stop of oscillation of the crystal oscillation circuit, and generates a signal necessary to control switching of the power supply for driving the crystal oscillation circuit.

FIG. 11is a circuit diagram of a configuration of a conventional oscillation detecting circuit. In the oscillation detecting circuit100shown inFIG. 11, an N-channel MOS transistor101is repeatedly turned on and off based on a potential of an oscillation signal CK supplied from an oscillation circuit (not shown). A capacitor102is connected between a high voltage power supply potential VDD and a low voltage power supply potential VSS and charged while the N-channel MOS transistor101is turned on. In addition, the capacitor102is slightly discharged by a leak current carried across a pull-up resistor103while the N-channel MOS transistor101is turned off. However, the capacitor102is charged again when the N-channel MOS transistor101is turned on. By repetition of the charge and discharge, a potential of an input terminal of an inverter104is stabilized to the low voltage power supply potential VSS.

Accordingly, while the oscillation signal CK is supplied, a potential of an oscillation-stop detection signal OSCST output from the inverter104is at a “high (H)” level at which the potential thereof is relatively high. If the supply of the oscillation signal CK is stopped in this state, the capacitor102is then continuously discharged according to a time constant CR and the potential of the input terminal of the inverter104starts rising toward the high voltage power supply potential VDD, accordingly. If the potential of the input terminal of the inverter104is higher than a threshold of the inverter104, the potential of the oscillation-stop detection signal OSCST output from the inverter104is switched from the “H” level to a “low (L)” level at which the potential thereof is relatively low. In this way, the oscillation detecting circuit100detects whether the oscillation circuit oscillates based on the potential of the oscillation-stop detection signal OSCST.

The conventional oscillation detecting circuit requires the pull-up resistor103to have a high resistance of about several hundreds of megaohms to about several gigaohms so as to set a discharge time to an appropriate time. However, if such a high resistance is formed within an IC chip, the following problems occur. First, an occupied area of the resistance relative to the IC chip is extremely large, resulting in an increase in a size of the IC chip. Second, because of a large fluctuation in manufacturing process, an absolute accuracy of the resistance is deteriorated. Accordingly, a desired discharge time cannot be obtained and the oscillation detecting circuit cannot often accurately detect whether the oscillation circuit oscillates. Furthermore, the resistance tends to change due to an influence of an external environment such as a light and a temperature. For this reason, for example, when the resistance decreases, a discharge current then increases and the oscillation detecting circuit may possibly erroneously detect that the oscillation of the oscillation circuit is stopped.

Considering these problems, an oscillation detecting circuit200configured as shown inFIG. 12is proposed (see, for example, Japanese Patent Application Laid-open No. 2000-332585 (FIG. 1)). The oscillation detecting circuit200includes a constant-current source201and a current-mirror circuit as units that discharge the capacitor102. One P-channel MOS transistor202that constitutes the current-mirror circuit is connected to the constant-current source201and applies a constant current thereto. The other P-channel MOS transistor203that constitutes the current-mirror circuit applies a discharge current proportional to the constant current carried across the one P-channel MOS transistor202.

In the oscillation detecting circuit200, similarly to the oscillation detecting circuit100configured as shown inFIG. 11, the N-channel MOS transistor101is repeatedly turned on and off while the oscillation signal CK is supplied thereto, and the charge and the slight discharge of the capacitor102are repeated. In this state, the potential of the input terminal of the inverter104is stabilized to the low voltage power supply potential VSS, and the “H” level oscillation-stop detection signal OSCST is output from the inverter104. When the oscillation is stopped, the capacitor102is continuously discharged by the discharge current carried across the other P-channel MOS transistor203. The potential of the input terminal of the inverter104is thereby made higher than the threshold of the inverter104, and the “L” level oscillation-stop detection signal OSCST is output from the inverter104.

With the configuration in which the pull-up resistor is used as the unit that discharges the capacitor (seeFIG. 11), however, the oscillation detecting circuit requires the pull-up resistor to have a high resistance of about several hundreds of megaohms to about several gigaohms so as to set the discharge time at the appropriate time. If such a high resistance is formed within an IC chip, the two problems described above occur. The oscillation detecting circuit may possibly erroneously detect that the oscillation is stopped.

Furthermore, the circuit disclosed in Japanese Patent Application Laid-open No. 2000-332585 has the following disadvantages. In the clock or the other electronic device, a transient period after the power is turned on before the clock or the other electronic device is turned into a stable state is normally an unstable period in which potentials of the respective units of the circuits, a current carried across the respective units, and the like are unstable. In the unstable period, currents in current amounts different from those in the stable state are carried to the constant-current source and the current-mirror circuit. For example, if the discharge current is excessively carried, the oscillation detecting circuit may perform an unfavorable operation such as an erroneous detection of the oscillation stop although the oscillation is continued.

Moreover, with the configuration in which the constant-current source and the P-channel MOS transistors connected to the capacitor in parallel are used as the capacitor discharging units (seeFIG. 12), the oscillation detecting circuit is required to considerably increase ON resistances of the P-channel MOS transistors connected to the capacitor in parallel so as to set the discharge time at the appropriate time. To do so, it is necessary to make a gate length of each P-channel MOS transistor large. This, in turn, disadvantageously increases a gate capacity of each P-channel MOS transistor. Accordingly, an operation of the constant-current source is made slow when the oscillation is started. The electronic device including the oscillation detecting circuit disadvantageously takes a longer time before it is started.

SUMMARY OF THE INVENTION

It is an object of the present invention to solve at least the above problems in the conventional technology.

An oscillation-stop detection circuit according to one aspect of the present invention includes a switching unit that repeats turning on and off based on a cycle of an oscillation signal from an outside; a capacitor that is charged when the switching unit is turned on, and discharged when the switching unit is turned off; a first MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged; a discharge cutoff unit that cuts off a discharge path for the discharge current to flow, for a predetermined time right after a power is turned on; and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor.

An oscillation-stop detection system according to another aspect of the present invention includes an oscillation-stop detection circuit that includes a switching unit that repeats turning on and off based on a cycle of an oscillation signal from an outside, a capacitor that is charged when the switching unit is turned on, and discharged when the switching unit is turned off, a first MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged, a discharge cutoff unit that cuts off a discharge path for the discharge current to flow, for a predetermined time right after a power is turned on, and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor; and a constant-voltage source that applies a gate bias of a constant potential to a gate of the first MOS transistor.

An oscillation-stop detection system according to still another aspect of the present invention includes an oscillation-stop detection circuit that includes a switching unit that repeats turning on and off based on a cycle of an oscillation signal from an outside, a capacitor that is charged when the switching unit is turned on, and discharged when the switching unit is turned off, a MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged, and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor; and a constant-voltage source that applies a gate bias of a constant potential to a gate of the MOS transistor.

An electronic device according to still another aspect of the present invention includes an oscillation circuit that outputs an oscillation signal; an oscillation-stop detection circuit that detects a status of the oscillation, and that outputs an oscillation-stop detection signal upon detecting that the oscillation is stopped; a regulator that drops a power supply potential to output a regulated voltage having a constant potential; and a switching unit that switches a voltage applied to the oscillation circuit between the regulated voltage and the power supply voltage, based on the oscillation-stop detection signal.

An electronic device according to still another aspect of the present invention includes an oscillation circuit that outputs an oscillation signal; an oscillation-stop detection circuit that includes a first switching unit that repeats turning on and off based on a cycle of the oscillation signal, a capacitor that is charged when the first switching unit is turned on, and discharged when the first switching unit is turned off, a first MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged, a second MOS transistor that cuts off a discharge path for the discharge current to flow, for a predetermined time right after a power is turned on, and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor; a regulator that includes a reference circuit that generates a predetermined reference potential based on a power supply voltage, a potential generating circuit that generates a positive predetermined potential, and an operational amplifier that includes a negative input terminal to which the reference potential from the reference circuit is input, a positive input terminal to which the positive predetermined potential is input, and an output terminal from which a regulated potential is output, the regulator applying the positive predetermined potential to a gate of the first MOS transistor and the reference potential to a gate of the second MOS transistor; and a second switching unit that switches a voltage applied to the oscillation circuit between the regulated voltage and the power supply voltage based on the oscillation-stop detection signal.

An oscillation-stop detection method according to still another aspect of the present invention includes cutting off a discharge path for a discharge current to flow when a capacitor is discharged, for a predetermined time right after a power is turned on; charging the capacitor based on a cycle of an oscillation signal; discharging an electric charge of the capacitor at a constant current amount; and detecting a status of the oscillation signal based on a voltage of the capacitor.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1is a circuit diagram of a configuration of an oscillation-stop detection system according to a first embodiment of the present invention. As shown inFIG. 1, the oscillation-stop detection system includes an oscillation-stop detection circuit1and a regulator2that constitutes a constant-current source. The oscillation-stop detection circuit1includes, for example, two inverters11and12, a first N-channel MOS transistor13that constitutes a switching unit, a first capacitor14that constitutes a capacitor, a first P-channel MOS transistor15, and a buffer16that constitutes a detecting unit.

The first inverter11inputs an oscillation signal CK supplied from an external oscillation circuit or the like (not shown), and outputs an inverted signal of the oscillation signal CK. The second inverter12inputs a signal output from the first inverter11and outputs an inverted signal of the output signal of the first inverter11. A source terminal of the first N-channel MOS transistor13is connected to an output terminal of the second inverter12. A gate terminal of the first N-channel MOS transistor13is connected to an output terminal of the first inverter11. The first N-channel MOS transistor13is, therefore, repeatedly turned on and off per half cycle of the oscillation signal CK.

A drain terminal of the first N-channel MOS transistor13is connected to one electrode (hereinafter, “low voltage electrode”) of the first capacitor14, a drain terminal of the first P-channel MOS transistor15, and an input terminal of the buffer16. A high voltage power supply potential VDD is applied to the other electrode of the first capacitor14and a source terminal of the first P-channel MOS transistor15. The first capacitor14is charged while the first N-channel MOS transistor13is turned on, and discharged while the first N-channel MOS transistor13is turned off.

A gate bias potential VREF that is a constant potential supplied from the regulator2is applied to a gate terminal of the first N-channel MOS transistor15. Accordingly, the first P-channel MOS transistor15operates as the constant-current source that carries a discharge current for the first capacitor14when the first capacitor14is in a discharged state. The gate bias potential VREF is a potential so as to suppress the discharge current to be a low and constant current. The buffer16outputs an oscillation-stop detection signal OSCST based on a potential of a signal input to the buffer16(hereinafter, “buffer input signal OSCST_NB”), i.e., a potential of the low voltage electrode of the first capacitor14.

The regulator2includes a reference circuit3, an operational amplifier4, and an output stage5. The reference circuit3includes two P-channel MOS transistors (second and third P-channel MOS transistors)31and32, two N-channel MOS transistors (second and third N-channel MOS transistors)33and34, and a resistance element35. A high voltage power supply potential VDD is applied to one end of the resistance element35and a source terminal of the third P-channel MOS transistor32. The other end of the resistance element35is connected to a source terminal of the second P-channel MOS transistor31. A gate terminal of the second P-channel MOS transistor31is connected to a gate terminal and a drain terminal of the third P-channel MOS transistor32, and to a drain terminal of the third N-channel MOS transistor34.

A drain terminal of the second P-channel MOS transistor31is connected to a drain terminal and a gate terminal of the second N-channel MOS transistor33, and to a gate terminal of the third N-channel MOS transistor34. The low voltage power supply potential VSS is applied to a source terminal of the second N-channel MOS transistor33and a source terminal of the third N-channel MOS transistor34. A reference potential PREF is output from the drain terminal of the third P-channel MOS transistor32. The reference potential PREF is a potential dropped from the high voltage power supply potential VDD by as much as a potential difference between the high voltage power supply potential VDD and a threshold of the P-channel MOS transistor.

The operational amplifier4includes three P-channel MOS transistors (fourth, fifth, and sixth P-channel MOS transistors)41,42, and43and two N-channel MOS transistors (fourth and fifth N-channel MOS transistors)44and45. The high voltage power supply potential VDD is applied to a source terminal of the fourth P-channel MOS transistor41serving as a current limiting transistor. The reference potential PREF output from the reference circuit3is applied to a gate terminal of the fourth P-channel MOS transistor41. A drain terminal of the fourth P-channel MOS transistor41is connected to a source terminal of the fifth P-channel MOS transistor42and a source terminal of the sixth P-channel MOS transistor43. The reference potential PREF is applied to a gate terminal of the fifth P-channel MOS transistor42.

A drain terminal of the fifth P-channel MOS transistor42is connected to a drain terminal of the fourth N-channel MOS transistor44. A gate terminal of the fourth N-channel MOS transistor44is connected to a drain terminal of the sixth P-channel MOS transistor43and to a drain terminal and a gate terminal of the fifth N-channel MOS transistor45. The low voltage power supply potential VSS is applied to the source terminal of the fourth N-channel MOS transistor44and a source terminal of the fifth N-channel MOS transistor45. A potential (VREF) dropped from the high voltage power supply potential VDD by as much as the potential difference between the low voltage power supply potential VSS and a threshold of the N-channel MOS transistor is applied to a gate terminal of the sixth P-channel MOS transistor43from a sixth N-channel MOS transistor52of the output stage5to be explained next.

The output stage5includes a seventh P-channel MOS transistor51serving as a pull-up transistor, the sixth N-channel transistor52that constitutes a potential generating circuit, a seventh N-channel MOS transistor53that constitutes an actuator, and a second capacitor54serving as a phase compensation capacitor. The high voltage power supply potential VDD is applied to a source terminal of the seventh P-channel MOS transistor51. A reference potential PREF is applied to a gate terminal of the seventh P-channel MOS transistor51.

A drain terminal of the seventh P-channel MOS transistor51is connected to a drain terminal and a gate terminal of the sixth N-channel MOS transistor52, and to the gate terminal of the sixth P-channel MOS transistor43of the operational amplifier4. The gate bias potential VREF of the first P-channel MOS transistor15of the oscillation-stop detection circuit1is output from the drain terminal of the sixth N-channel MOS transistor52. The gate bias potential VREF is a potential dropped from the high voltage power supply potential VDD by as much as the potential difference between the low voltage power supply potential VSS and the threshold of the N-channel MOS transistor.

A source terminal and a bulk of the sixth N-channel MOS transistor52are connected to the drain terminal of the seventh P-channel MOS transistor51. The gate terminal of the seventh P-channel MOS transistor51is connected to the drain terminal of the fifth P-channel MOS transistor42of the operational amplifier4. The low voltage power supply potential VSS is applied to the source terminal of the seventh N-channel MOS transistor53. The second capacitor54is connected between the drain terminal and the gate terminal of the seventh N-channel MOS transistor53. A regulated potential VREG is output from the drain terminal of the seventh N-channel MOS transistor53.

In the regulator2configured as explained above, the reference potential PREF, that is, the potential dropped from the high voltage power supply potential VDD by as much as the potential difference between the high voltage power supply potential VDD and the threshold of the P-channel MOS transistor is applied to a negative input terminal of the operational amplifier4. In addition, the potential dropped from the high voltage power supply potential VDD by as much as the potential difference between the low voltage power supply potential VSS and the threshold of the N-channel MOS transistor is applied to a positive input terminal of the operational amplifier4. Accordingly, the operational amplifier4operates to keep the regulated potential VREG to a potential obtained by adding the two potentials input to the both input terminals of the operational amplifier4, i.e., by adding the potential difference between the high voltage power supply potential VDD and the threshold of the P-channel MOS transistor and the potential difference between the low voltage power supply potential VSS and the threshold of the N-channel MOS transistor to a negative side relative to the high voltage power supply potential VDD. This operation is a regulator operation.

Operations performed by the oscillation-stop detection system configured as shown inFIG. 1will be explained next.FIG. 2is a timing chart for explaining the operations. As shown inFIG. 2, it is assumed as follows. At a time T1, the oscillation signal CK is stopped while the first N-channel MOS transistor13is turned off. At a time T2, an oscillation is started. At a time T3, the oscillation signal CK is stopped while the first N-channel MOS transistor13is turned off. At a time T4, the oscillation-stop detection circuit1detects that the oscillation is stopped. The operations at the respective times will be explained. It is assumed herein that the oscillation signal CK has the low voltage power supply potential VSS although the oscillation signal CK is not constant when the oscillation is stopped.

In a period from the time T1to the time T2, the first capacitor14of the oscillation-stop detection circuit1is completely discharged. Therefore, the potential of the low voltage electrode of the first capacitor14, i.e., the potential of the buffer input signal OSCST_NB is equal to the high voltage power supply potential VDD. The potential of the oscillation-stop detection signal OSCST is equal to the high voltage power supply potential VDD, accordingly. The reference potential PREF, the gate bias potential VREF, and the regulated potential VREG are constant whether the oscillation circuit oscillates. In addition, the regulated potential VREG is a potential obtained by adding up the reference potential PREF and the gate bias potential VREF.

At the time T2, the oscillation is started, whereby the first N-channel MOS transistor13of the oscillation-stop detection circuit1is turned on. Accordingly, the low voltage power supply potential VSS is applied to the low voltage electrode of the first capacitor14and the first capacitor14starts to be charged. When the first capacitor14is sufficiently charged, the potential of the low voltage electrode of the first capacitor14, i.e., the potential of the buffer input signal OSCST_NB is equal to the low voltage power supply potential VSS. The potential of the oscillation-stop detection signal OSCST is, therefore, equal to the low voltage power supply potential VSS.

In a period from the time T2to the time T3, the first N-channel MOS transistor13is repeatedly turned on and off according to a change in the potential of the oscillation signal CK. While the first N-channel MOS transistor13is turned off, the electric charge accumulated in the first capacitor14is carried across the first P-channel MOS transistor15as the discharge current. Namely, the first capacity14starts to be discharged and the potential of the low voltage electrode of the first capacitor14starts to rise toward the high voltage power supply potential VDD. As explained above, the discharge current carried at this time is low and constant current.

Accordingly, before the potential of the low voltage electrode of the first capacitor14(the potential of the buffer input signal OSCST_NB) reaches a threshold of the buffer16, the potential of the oscillation signal CK is inverted, the first N-channel MOS transistor13is turned on, and the first capacitor14is charged again. In the period from the time T2to the time T3, therefore, the first capacitor14is always in a state in which the first capacitor14is sufficiently charged, and the potential of the oscillation-stop detection signal OSCST is equal to the low voltage power supply potential VSS. That is, while the oscillation is continued, the oscillation-stop detection circuit1outputs the “L” level oscillation-stop detection signal OSCST.

When the oscillation is stopped at the time T3, the discharge current is carried across the first P-channel MOS transistor15and the first capacitor14starts to be discharged. Accordingly, the potential of the low voltage electrode of the first capacitor14starts to rise toward the high voltage power supply potential VDD. Since the oscillation is stopped, the discharge current is continuously carried, so that the potential of the low voltage electrode of the first capacitor14continues to rise toward the high voltage power supply potential VDD. At the time T4, when the potential of the low voltage electrode of the first capacitor14exceeds the threshold of the buffer16(which is ½ VSS inFIG. 2), the potential of the oscillation-stop detection signal OSCST output from the buffer16is inverted and turns “H” level. At this moment, the oscillation-stop detection circuit1detects that the oscillation is stopped.

If the oscillation is not resumed, the potential of the low voltage electrode of the first capacitor14continues to rise and eventually reaches the high voltage power supply potential VDD, and the first capacitor14is completely discharged. Accordingly, while the oscillation is stopped, the oscillation-stop detection circuit1outputs the “H” level oscillation-stop detection signal OSCST. In order to prevent the oscillation-stop detection circuit1from erroneously detecting that the oscillation is stopped in the period in which the oscillation is continued, it is necessary to control the gate bias potential VREF to be low and to suppress the discharge current to be low so that a time from a point (time T3) at which the oscillation is stopped to a point (time T4) at which the potential of the oscillation-stop detection signal OSCST is switched to the “H” level, i.e., an oscillation stop detection time is sufficiently longer than a cycle of the oscillation signal CK.

If the electronic device including the oscillation-stop detection system thus configured is the clock, though not limited thereto, the oscillation-stop detection system can be configured as follows. As the oscillation signal CK, a signal obtained by dividing a frequency of an output signal of a crystal oscillation circuit employed in the clock IC can be normally used. As the regulator2, a regulator included in the clock can be normally used.

Furthermore, the oscillation-stop detection system can be constituted so that the high voltage power supply potential VDD is set at 0 volt, the low voltage power supply potential VSS is set at −1.5 volts, and the oscillation-stop detection system operates at a negative power supply voltage. In addition, the threshold of the P-channel MOS transistor can be set at −0.4 volt and that of the N-channel MOS transistor can be set at −1.1 volts. If so setting, the potential difference between the high voltage power supply potential VDD and the threshold of the P-channel MOS transistor is 0.4 volt, and that between the low voltage power supply potential VSS and the threshold of the P-channel MOS transistor is also 0.4 volt. The regulator2, therefore, outputs the regulated voltage VREG of −0.8 volt.

An example of sizes of relevant elements of the oscillation-stop detection system, though not limited thereto, will be explained. A capacity of the first capacitor14is about 10 picofarads. The first P-channel MOS transistor15has a gate width of about 4 micrometers and a gate length of about 198 micrometers.

As shown in a modification of the first embodiment inFIG. 3, an eighth P-channel MOS transistor55may be employed as a source follower in the actuator of the output stage5of the regulator2. If so, a gate terminal of the eighth P-channel MOS transistor55is connected to the drain terminal of the sixth P-channel MOS transistor43and one of the electrodes of the phase compensation second capacitor54. A source terminal of the eighth P-channel MOS transistor55is connected to an output terminal of the regulated potential VREG, to the source terminal of the sixth N-channel MOS transistor52, and to the other electrode of the second capacitor54. The low voltage power supply potential VSS and the high voltage power supply potential VDD are applied to a drain terminal and a bulk of the eighth P-channel MOS transistor55, respectively. Furthermore, the gate terminal of the fourth N-channel MOS transistor44is connected to the drain terminal of the fourth N-channel MOS transistor44, the drain terminal of the fifth P-channel MOS transistor42, and to the gate terminal of the fifth N-channel MOS transistor45.

With the configuration shown inFIG. 3, in the eighth P-channel MOS transistor55, a parasitic capacitance is generated between the gate and the bulk thereof. Therefore, even if the low voltage power supply potential VSS changes, the change is absorbed by the drain of the eighth P-channel MOS transistor55. Accordingly, the regulated potential VREG is output from the output terminal of the regulated potential VREG without any influence of a change in the low voltage power supply potential VSS. Namely, it is possible to prevent the regulated potential VREG from changing. As long as the regulated potential VREG is constant, the gate bias potential VREF does not change, so that the stable gate bias potential VREF can be achieved. In other words, the stable oscillation stop detection time can be achieved.

According to the first embodiment, while the oscillation is continued, the “L” level oscillation-stop detection signal OSCST is output from the oscillation-stop detection circuit1. If the oscillation is stopped for the time longer than the predetermined oscillation stop detection time, the “H” level oscillation-stop detection signal OSCST is output from the oscillation-stop detection circuit1. The oscillation-stop detection system can, therefore, accurately detect that the oscillation of the oscillation circuit is stopped.

FIG. 4is a circuit diagram of a configuration of the oscillation-stop detection system according to a second embodiment of the present invention. As shown inFIG. 4, the oscillation-stop detection system includes an oscillation-stop detection circuit1and a regulator2that constitutes a constant-current source. The oscillation-stop detection circuit1includes, for example, two inverters11and12, the first N-channel MOS transistor13that constitutes the switching unit, the first capacitor14that constitutes the capacitor, the first P-channel MOS transistor15that serves as a discharge path, the buffer16that constitutes the detecting unit, and a ninth P-channel MOS transistor17that constitutes a discharge cutoff unit.

A drain terminal of the first N-channel MOS transistor13is connected to one electrode (hereinafter, “low voltage electrode”) of the first capacitor14, a drain terminal of the first P-channel MOS transistor15, and an input terminal of the buffer16. The high voltage power supply potential VDD is applied to the other electrode of the first capacitor14and a source terminal of the first P-channel MOS transistor15. A drain terminal of the ninth P-channel MOS transistor17is connected to a source terminal of the first P-channel MOS transistor15. The first capacitor14is charged when the first N-channel MOS transistor13is turned on, and discharged when the first N-channel MOS transistor13is turned off.

The gate bias potential VREF that is a constant potential supplied from the regulator2is applied to a gate terminal of the ninth P-channel MOS transistor17. The reference potential PREF is set at a potential for turning off the ninth P-channel MOS transistor17while the potentials and currents of the respective units are unstable right after the power is turned on. In addition, the reference potential PREF is set at a potential for turning on the ninth P-channel MOS transistor17in a stable state in which the potentials and the currents of the respective units are stable. Accordingly, the ninth P-channel MOS transistor17is turned off to cut off the discharge path when the gate bias of the first P-channel MOS transistor15is unstable, and turned on when the gate bias thereof is stable.

The gate bias potential VREF that is the constant potential supplied from the regulator2is applied to a gate terminal of the first P-channel MOS transistor15. Accordingly, the first P-channel MOS transistor15operates as the constant-current source that carries a discharge current for the first capacitor14when the first capacitor14is in a discharged state. The gate bias potential VREF is set at a potential so as to suppress this discharge current to have a low constant current amount. The buffer16outputs the oscillation-stop detection signal OSCST based on a potential of a signal input to the buffer16(hereinafter, “buffer input signal OSCST_NB”), i.e., a potential of the low voltage electrode of the first capacitor14.

A ratio of a gate width to a gate length of the ninth P-channel MOS transistor17is sufficiently higher than that of the first P-channel MOS transistor15. In other words, an ON resistance of the ninth P-channel MOS transistor17is sufficiently lower than that of the first P-channel MOS transistor15. In the stable state, therefore, both the first P-channel MOS transistor15and the ninth P-channel MOS transistor17are turned on. The current amount of the discharge current is not limited by the ninth P-channel MOS transistor17when the discharge current is carried. Namely, by controlling the gate bias of the first P-channel MOS transistor15, the drain current of the first P-channel MOS transistor15is controlled, and the current amount of the discharge current is also controlled.

Since other configurations are the same as those according to the first embodiment shown inFIG. 1, they will not be explained herein.

Operations performed by the oscillation-stop detection system configured as shown inFIG. 4will be explained next. The operations in a stable state will be explained first with reference toFIG. 2, similarly to the first embodiment. As shown inFIG. 2, it is assumed as follows. At the time T1, the oscillation signal CK is stopped while the first N-channel MOS transistor13is turned off. At the time T2, an oscillation is started. At the time T3, the oscillation signal CK is stopped while the first N-channel MOS transistor13is turned off. At the time T4, the oscillation-stop detection circuit1detects that the oscillation is stopped. The operations at the respective times will be explained. It is assumed herein that the oscillation signal CK has the low voltage power supply potential VSS although the oscillation signal CK is not constant when the oscillation is stopped.

In the period from the time T1to the time T2, the first capacitor14of the oscillation-stop detection circuit1is completely discharged. Therefore, the potential of the low voltage electrode of the first capacitor14, i.e., the potential of the buffer input signal OSCST_NB is equal to the high voltage power supply potential VDD. The potential of the oscillation-stop detection signal OSCST is equal to the high voltage power supply potential VDD, accordingly. In the stable state, the reference potential PREF and the gate bias potential VREF are stable whether the oscillation circuit oscillates, and are potentials for turning on the ninth P-channel MOS transistor17and the first P-channel MOS transistor15, respectively. In the stable state, therefore, the first P-channel MOS transistor15and the ninth P-channel MOS transistor17are always turned on. The regulated potential VREG is a potential obtained by adding the reference potential PREF and the gate bias potential VREF, and constant in the stable state whether the oscillation circuit oscillates.

An example of sizes of important elements of the oscillation-stop detection system, though not limited thereto, will be explained. A capacity of the first capacitor14is about 10 picofarads. The first P-channel MOS transistor15has a gate width of about 4 micrometers and a gate length of about 198 micrometers. The ninth P-channel MOS transistor17has a gate width of about 100 micrometers and a gate length of about 1 micrometer.

Since other configurations are the same as those according to the second embodiment shown inFIG. 2, they will not be explained herein.

The operations performed by the oscillation-stop detection system configured as shown inFIG. 4right after the power is turned on will be explained.FIG. 5is a timing chart for explaining the operations. As shown inFIG. 5, it is assumed as follows. At a time T0, the power is not turned on. At a time T01, the power is turned on. At a time T02, an oscillation is started. At a time03, the system is stabilized to the stable state. Subsequently, the oscillation is continued. The operations at the respective times will be explained.

In a period before the time T01in which the power is not turned on, an applied potential of the input terminal of the oscillation signal CK, a potential of a wiring applied with the lower voltage power supply potential VSS, the reference potential PREF, the gate bias potential VREF, the regulated potential VREG, the potential of the buffer input signal OSCST_NB, and the potential of the oscillation-stop detection signal OSCST are all set at a grounding potential, i.e., the high voltage power supply potential. At the time T01, the power is turned on, whereby the applied potential of the input terminal of the oscillation signal CK and the potential of the wiring applied with the low voltage power supply potential VSS are switched to the low voltage power supply potential VSS. Thereafter, the potential of the wiring applied with the low voltage power supply potential VSS remains the low voltage power supply potential VSS until the power is turned off.

The reference potential PREF gradually falls from the high voltage power supply potential VDD right after the power is turned on. At the time T03, the reference potential PREF is stabilized to a potential dropped from the high voltage power supply potential VDD by as much as the potential difference between the high In an unstable period from the time T01to the time T03, the reference potential PREF is a potential close to the high voltage power supply potential VDD. The ninth P-channel MOS transistor17of the oscillation-stop detection circuit1is, therefore, turned off.

The gate bias potential VREF temporarily falls down to a potential close to the low voltage power supply potential VSS when the power is turned on. At the time T03, the gate bias potential VREF is stabilized to a potential dropped from the high voltage power supply potential VDD by as much as the potential difference between the low voltage power supply potential VSS and the threshold of the N-channel MOS transistor. Even in the unstable period from the time T01to the time T03, the gate bias potential VREF is lower than the threshold of the P-channel MOS transistor. The first P-channel MOS transistor15of the oscillation-stop detection circuit1is, therefore, turned on.

However, as explained above, since the ninth P-channel MOS transistor17is turned off, the oscillation is started at the time T02in the unstable period. In addition, even if the first capacitor14of the oscillation-stop detection circuit1is charged, the discharge path for discharging the electric charge thus accumulated is cut off, so that the first capacitor14is not discharged. Following the start of the oscillation at the time T02, therefore, the respective potentials of the buffer input signal OSCST_NB and the oscillation-stop detection signal OSCST turn “L” level and remain “L” level until the time T03.

The regulated potential VREG changes similarly to the gate bias potential VREF. Right after the power is turned on at the time T01, the regulated potential VREG is a potential close to the low voltage power supply potential VSS. Thereafter, at the time T03, the regulated potential VREG is stabilized to a potential obtained by adding the potential difference between the high voltage power supply potential VDD and the threshold of the P-channel MOS transistor and the potential difference between the low voltage power supply potential VSS and the threshold of the N-channel MOS transistor to the negative side relative to the high voltage power supply potential VDD. In a stable period after the time T03, the oscillation-stop detection system operates in the stable state as explained above with reference toFIG. 2.

Provided that the oscillation-stop detection system does not include the ninth P-channel MOS transistor17, the following problems occur in the unstable period between the time T01and the time T03. As shown inFIG. 6, in the unstable period, the gate bias potential VREF is a potential close to the low voltage power supply potential VSS. Accordingly, when the oscillation is started at the time T02, the gate bias of the first P-channel MOS transistor15that serves as the discharge path increases and the drain current considerably increases, accordingly. If so, the discharge current is excessively carried. Accordingly, even if the oscillation is continued, the discharge of the first capacitor14is then completed between pulses of the oscillation signal CK, and the oscillation-stop detection circuit1erroneously detects that the oscillation is stopped. This problem continuously occurs in the unstable period.

Furthermore, when the discharge of the first capacitor14is completed between the pulses of the oscillation signal CK, the potential of the buffer input signal OSCST_NB exceeds the threshold of the buffer16(which is ½ VSS inFIG. 6). A through current is carried across the buffer16, accordingly. This problem also continuously occurs in the unstable period, so that the current consumption is greatly increased. This problem is a serious disadvantage for the IC, e.g., the clock IC, required to realize a low current consumption. According to the second embodiment, by providing the ninth P-channel MOS transistor17and shutting off the discharge path of the first capacitor14in the unstable period, these problems can be avoided. Alternatively, the first P-channel MOS transistor15may be controlled to cut off the discharge path without using the ninth P-channel MOS transistor17. In the alternative, since the first P-channel MOS transistor15cut off the discharge path, it is unnecessary to provide the ninth P-channel MOS transistor17.

As shown in a modification of the second embodiment inFIG. 7, the eighth P-channel MOS transistor55may be employed as a source follower in the actuator of the output stage5of the regulator2. If so, a gate terminal of the eighth P-channel MOS transistor55is connected to the drain terminal of the sixth P-channel MOS transistor43and one of the electrodes of the phase compensation second capacitor54. A source terminal of the eighth P-channel MOS transistor55is connected to an output terminal of the regulated potential VREG, to the source terminal of the sixth N-channel MOS transistor52, and to the other electrode of the second capacitor54. The low voltage power supply potential VSS and the high voltage power supply potential VDD are applied to the drain terminal and the bulk of the eighth P-channel MOS transistor55, respectively. Furthermore, the gate terminal of the fourth N-channel MOS transistor44is connected to the drain terminal of the fourth N-channel MOS transistor44, the drain terminal of the fifth P-channel MOS transistor42, and to the gate terminal of the fifth N-channel MOS transistor45.

With the configuration shown inFIG. 7, in the eighth P-channel MOS transistor55, a parasitic capacitance is generated between the gate and the bulk thereof. Therefore, even if the low voltage power supply potential VSS changes, the change is absorbed by the drain of the eighth P-channel MOS transistor55. Accordingly, the regulated potential VREG is output from the output terminal of the regulated potential VREG without any influence of the change in the low voltage power supply potential VSS. Namely, it is possible to prevent the regulated potential VREG from changing. As long as the regulated potential VREG is constant, the gate bias potential VREF does not change, so that the stable gate bias potential VREF can be achieved. In other words, the stable oscillation stop detection time can be achieved.

According to the second embodiment, in the period after the power is turned on until the gate bias potential VREF of the first P-channel MOS transistor15serving as the discharge path is stabilized, no discharge current flows. Therefore, in the unstable transient period after the power is turned on until the system is turned into the stable state, it is possible to prevent an unfavorable operation such as an erroneous detection of the oscillation stop due to the temporary excessive flow of the discharge current although the oscillation is continued. Furthermore, in the stable state, while the oscillation is continued, the “L” level oscillation-stop detection signal OSCST is output from the oscillation-stop detection circuit1. If the oscillation is stopped for the time longer than the predetermined oscillation stop detection time, the “H” level oscillation-stop detection signal OSCST is output from the oscillation-stop detection circuit1. The oscillation-stop detection system can, therefore, accurately detect that the oscillation of the oscillation circuit is stopped.

FIG. 8is a block diagram of a schematic configuration of an electronic device according to a third embodiment of the present invention. A case that the electronic device is a clock, though not limited thereto, will be explained. It is assumed herein that the clock includes the oscillation-stop detection system according to the first or the second embodiment. The potential of the oscillation-stop detection signal OSCST output from the oscillation-stop detection circuit1is, therefore, at the “L” level while the oscillation is continued, and at the “H” level while the oscillation is stopped.

As shown inFIG. 8, the electronic device that is the clock includes, for example, the oscillation-stop detection circuit1, the regulator2, an internal circuit6, a motor driving circuit7, two inverters (third and fourth inverters)81and82, and two N-channel MOS transistors (eighth and ninth N-channel MOS transistors)83and84that constitute switching elements, respectively. The internal circuit6includes an oscillation circuit61and a logic circuit62. Although the clock includes various other circuit blocks, only typical blocks are shown inFIG. 8and other ones are not shown therein.

The oscillation-stop detection circuit1, the regulator2, and the motor driving circuit7are driven by a power supply voltage configured by the high voltage power supply potential VDD and the low voltage power supply potential VSS. When the oscillation circuit61and the logic circuit62in the internal circuit6are operated normally, they are driven by a regulated voltage configured by the high voltage power supply potential VDD and the regulated potential VREG output from the regulator2. If the oscillation of the oscillation circuit61is stopped, the power supply voltage configured by the high voltage power supply potential VDD and the low voltage power supply potential VSS is supplied to the oscillation circuit61and the logic circuit62so as to promptly start the oscillation.

The third inverter81inputs the oscillation-stop detection signal OSCST output from the oscillation-stop detection circuit1, and outputs an inverted signal of the oscillation-stop detection signal OSCST. A signal output from the third inverter81is supplied to a gate terminal of the eighth N-channel MOS transistor83. The regulated potential VREG output from the regulator2is applied to a source terminal of the eighth N-channel MOS transistor83. A drain terminal of the eighth N-channel MOS transistor83is connected to low voltage power supply wirings of the oscillation circuit61and the logic circuit62, respectively. Therefore, while the eight N-channel MOS transistor83is turned on, the low voltage power supply potential (hereinafter, “internal circuit power supply potential VSS2”) of each of the oscillation circuit61and the logic circuit62is equal to the regulated potential VREG.

The fourth inverter82inputs the output signal of the third inverter81, and outputs an inverted signal of the output signal of the third inverter81. A signal output from the fourth inverter82is supplied to a gate terminal of the ninth N-channel MOS transistor84. The low voltage power supply potential VSS is applied to a source terminal of the ninth N-channel MOS transistor84. A drain terminal of the ninth N-channel MOS transistor84is connected to the low voltage power supply wirings of the oscillation circuit61and the logic circuit62, respectively. Therefore, while the ninth N-channel MOS transistor84is turned on, the internal circuit power supply potential VSS2of each of the oscillation circuit61and the logic circuit62is equal to the low voltage power supply potential VSS.

Operations performed by the electronic device configured as shown inFIG. 8will be explained next.FIG. 9is a timing chart for explaining the operations. As shown inFIG. 9, it is assumed as follows. At a time T11, the oscillation circuit61is stopped and the oscillation signal CK obtained by dividing a frequency of the output signal of the oscillation circuit61is, therefore, stopped. At a time T12, the oscillation of the oscillation circuit61is started to thereby supply the oscillation signal CK. At a time T13, the oscillation of the oscillation circuit61is stopped and the oscillation signal CK is stopped. At a time T14, the oscillation-stop detection circuit1detects that the oscillation is stopped. The operations at the respective times will be explained. If the operation timings of the electronic device are tuned to those of the oscillation-stop detection system according to the first embodiment, the times T11, T12, T13, and T14according to the third embodiment correspond to the times T1, T2, T3, and T4according to the first embodiment, respectively.

In a period from the time T11to the time T12, the oscillation signal CK is stopped. The potential of the oscillation-stop detection signal OSCST output from the oscillation-stop detection circuit1is, therefore, equal to the high voltage power supply potential VDD. If so, a gate potential of the eighth N-channel MOS transistor83is equal to the low voltage power supply potential VSS, and the eighth N-channel MOS transistor83is, therefore, turned off. On the other hand, since a gate potential of the ninth N-channel MOS transistor84is equal to the high voltage power supply potential VDD, the ninth N-channel MOS transistor84is turned on. Accordingly, the low voltage power supply potential VSS is applied to the oscillation circuit61and the logic circuit62through the ninth N-channel MOS transistor84, so that the internal circuit power supply potential VSS2is equal to the low voltage power supply potential VSS.

At the time T12, the potential of the oscillation-stop detection signal OSCST is switched from the high voltage power supply potential VDD to the low voltage power supply potential VSS in response to the start of the oscillation. Accordingly, the gate potential of the eighth N-channel MOS transistor83is switched from the low voltage power supply potential VSS to the high voltage power supply potential VDD, and the eighth N-channel MOS transistor83is turned on. The gate potential of the ninth N-channel MOS transistor84is switched from the high voltage power supply potential VDD to the low voltage power supply potential VSS, and the ninth N-channel MOS transistor84is, therefore, turned off.

In a period from the time T12to the time T13, the potential of the oscillation-stop detection signal OSCST remains the low voltage power supply potential VSS. The eighth N-channel MOS transistor83is, therefore, kept to be turned on. Since the ninth N-channel MOS transistor84is kept to be turned off, the regulated potential VREG is applied to the oscillation circuit61and the logic circuit62through the eighth N-channel MOS transistor83. The internal circuit power supply potential VSS2is, therefore, equal to the regulated potential VREG.

Even if the oscillation is stopped at the time T13, the potential of the oscillation-stop detection signal OSCST, the gate potential of the eighth N-channel MOS transistor83, and the gate potential of the ninth N-channel MOS transistor84do not change until the oscillation-stop detection circuit1detects that the oscillation is stopped at the time T14. The internal circuit power supply potential VSS2, therefore, remains the regulated potential VREG.

When the oscillation-stop detection circuit1detects that the oscillation is stopped at the time T14, the potential of the oscillation-stop detection signal OSCST is switched from the low voltage power supply potential VSS to the high voltage power supply potential VDD. The eighth N-channel MOS transistor83is turned off and the ninth N-channel MOS transistor84is turned on, accordingly. Therefore, the low voltage power supply potential VSS is applied to the oscillation circuit61and the logic circuit62, so that the internal circuit power supply potential VSS2is switched to the low voltage power supply potential VSS. Before the oscillation is resumed, the internal circuit power supply potential VSS2remains the low voltage power supply potential VSS.

In the internal circuit6, the logic circuit62may be constituted to be driven by the power supply potential configured by the high voltage power supply potential VDD and the low voltage power supply potential VSS or the power supply potential configured by the high voltage power supply potential VDD and the regulated potential VREG whether the oscillation is present. Namely, as shown in a modification of the third embodiment inFIG. 10, the internal circuit6may be constituted as follows. Only the oscillation circuit61is driven by a regulated voltage configured by the high voltage power supply potential VDD and the regulated potential VREG in normal operation, and driven by the power supply voltage configured by the high voltage power supply potential VDD and the low voltage power supply potential VSS at the resumption of the oscillation. If so, the regulated potential VREG is applied to a low voltage power supply wiring of the logic circuit62, and the drain terminal of the eighth N-channel MOS transistor83is connected to a low voltage power supply wiring of the oscillation circuit61.

According to the third embodiment, while the oscillation circuit61oscillates, the oscillation circuit61and the logic circuit62are driven by the regulated voltage configured by the high voltage power supply potential VDD and the regulated potential VREG. In addition, when the oscillation is stopped, the oscillation circuit61is driven by the power supply voltage configured by the high voltage power supply potential VDD and the low voltage power supply potential VSS. It is, therefore, possible to realize low current consumption and to promptly resume the oscillation of the oscillation circuit61. It is also possible to prevent the oscillation-stop detection circuit1from erroneously detecting that the oscillation of the oscillation circuit61is stopped in the unstable period right after the power is turned on. Furthermore, for reasons to be explained next, the oscillation-stop detection circuit1can accurately detect that the oscillation of the oscillation circuit61is stopped, thereby making it possible to ensure resuming the oscillation.

Provided that the electronic device does not include the eight N-channel MOS transistor83and the ninth N-channel MOS transistor84, and that the regulated potential VREG is set at the low voltage power supply potential VSS during resumption of the oscillation, for example, a short-circuit switching element is provided in parallel to the actuator of the regulator2and the regulated potential VREG is forced to be set at the low voltage power supply potential VSS by operating the short-circuit switching element, the following problems occur. If the regulated potential VREG is short-circuited to the low voltage power supply potential VSS, the gate bias potential VREF (seeFIG. 1) output from the oscillation-stop detection circuit1changes toward the low voltage power supply potential VSS.

If so, the gate potential of the first P-channel MOS transistor15of the oscillation-stop detection circuit1is close to the low voltage power supply potential VSS, and the drain current for the first P-channel MOS transistor15, i.e., the discharge current for the first capacitor14is excessively carried. Accordingly, although the oscillation circuit61oscillates, the oscillation-stop detection circuit1may possibly erroneously detect that the oscillation of the oscillation circuit61is stopped. According to the third embodiment, by contrast, the regulated potential VREG is not short-circuited to the low voltage power supply potential VSS. Therefore, the gate bias potential VREF is stable and the oscillation-stop detection circuit1can accurately detect that the oscillation of the oscillation circuit61is stopped.

The present invention is not limited to the embodiments explained so far, and various changes and modifications can be made to the present invention. For example, in the first embodiment, a constant voltage may be applied from another constant-voltage source to the gate terminal of the first P-channel MOS transistor15instead of fetching the gate bias of the first P-channel MOS transistor15of the oscillation-stop detection circuit1from the regulator2. In addition, the detecting unit is not limited to the buffer16, but may be constituted differently from the buffer16. For example, the detecting unit can be constituted using an inverter.

Furthermore, in the second embodiment, constant voltages may be applied to the gate terminal of the first P-channel MOS transistor15and that of the ninth P-channel MOS transistor17from another constant-voltage source instead of fetching the respective gate biases of the first P-channel MOS transistor15and the ninth P-channel MOS transistor17of the oscillation-stop detection circuit1from the regulator2. In addition, the detecting unit is not limited to the buffer16, but may be constituted differently from the buffer16. For example, the detecting unit can be constituted using an inverter.

The oscillation-stop detection circuit, the oscillation-stop detection system, or the oscillation-stop detection method according to the present invention exhibits advantages in that it is possible to prevent the erroneous operation in the unstable period right after the power is turned on and to accurately detect that the oscillation of the oscillation circuit is stopped. In addition, the electronic device according to the present invention exhibits advantages in that it is possible to accurately and promptly resume the oscillation by preventing the erroneous operation in the unstable period right after the power is turned on and accurately detecting that the oscillation of the oscillation circuit is stopped.

The present document incorporates by reference the entire contents of Japanese priority documents, 2004-063038 filed in Japan on Mar. 5, 2004 and Japanese priority documents, 2004-064397 filed in Japan on Mar. 8, 2004.