Method of fabricating transistor for semiconductor device

A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention claims priority of Korean patent application number 10-2008-0135584, filed on Dec. 29, 2008, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor fabrication technology, and more particularly, to a method of fabricating a transistor for use in a semiconductor device.

As semiconductor devices are being highly integrated, one of important issues is to fabricate transistors that can ensure a high current drivability and a short channel margin even at small dimensions.

Recently, extensive studies have been conducted to increase carrier mobility in order to ensure a high current drivability. Carrier mobility may be increased by applying a certain stress to a channel region defined under a gate, leading to improving current characteristic of transistors. To this end, various transistor structures and fabrication methods thereof have been proposed, and one such example is illustrated inFIGS. 1A to 1D.

FIGS. 1A to 1Dare cross-sectional views explaining a structure of a conventional PMOS transistor and a fabrication method thereof.

Referring toFIG. 1A, a device isolation layer11is formed on a substrate10to define an active region.

A gate pattern12having a stacked structure of a gate insulation layer, a gate electrode and a gate hard mask is formed on the substrate10, and a gate spacer13is formed on a sidewall of the gate pattern12.

Referring toFIG. 1B, the substrate10on either side of the gate spacer13is etched to a certain depth to form a trench T. Reference numeral11A represents an etched device isolation layer.

Referring toFIG. 1C, an epitaxial layer14is grown within the trench T by using a sidewall and/or bottom of the trench T as a seed layer.

The epitaxial layer14is used to apply a stress to the channel region of the substrate10. In the case of the PMOS transistor, a compression stress is applied in a direction parallel to the channel region in order to increase the mobility of majority carriers, i.e., holes. Thus, the epitaxial layer14is formed of a material having a larger lattice constant than the substrate10. For example, when the substrate10is a Si substrate, the epitaxial layer14may be a SiGe epitaxial layer.

Referring toFIG. 1D, an initial source/drain region15is formed by ion implantation of P-type dopants such as boron (B).

Referring toFIG. 1E, a thermal treatment is performed for dopant activation. As a result, the dopants are diffused to form a final source/drain region15A. In this manner, a PMOS transistor having a structure ofFIG. 1Eis completed.

However, there are the following limitations on the structure of the conventional PMOS transistor and the fabrication method thereof.

When the epitaxial layer14such as SiGe is grown, it is grown not uniformly but in a convex shape (seeFIGS. 1C to 1E). Due to the shape of the epitaxial layer14, the dopants for forming the source/drain region in a subsequent process are relatively more ion-implanted into edges of the gate pattern12than other positions (seeFIG. 1D). From the profile of the final source/drain region15A when the dopants are diffused by the subsequent thermal treatment, it can be seen that lateral diffusion of the dopants is so active that the side of the final source/drain region15A penetrates even under the gate pattern12, whereas the bottom of the final source/drain region15A is relatively shallow.

If the side of the final source/drain region15A penetrates even under the gate pattern12, the short channel margin of the transistor is degraded and, in particular, Drain Induced Barrier Lowering (DIBL) is degraded.

Furthermore, if the bottom of the final source/drain region15A is shallow, leakage current characteristic is degraded due to interface defect between the substrate10and the epitaxial layer14.

Therefore, there is a need for a method of fabricating a new transistor capable of solving the above-mentioned limitations.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to providing a method of fabricating a transistor for use in a semiconductor device. In the method, a source/drain region is formed before growth of an epitaxial layer. At this point, by forming the source/drain region in a state that a trench has been formed by etching a substrate, the source/drain region is sufficiently deep, and the overlap between the side of the source/drain region and a gate pattern is reduced, leading to improving a leakage current characteristic of the transistor and preventing a short channel effect.

In accordance with an aspect of the present invention, there is provided a method of fabricating a transistor for use in a semiconductor device. The method includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

In accordance with another aspect of the present invention, there is provided a method of fabricating a transistor for use in a semiconductor device. The method including: forming a first trench by etching a substrate on a side of a gate structure to a first depth, forming a material layer over the resulting substrate structure, etching the material layer to partially expose the substrate covered by the material layer and leave a continuous layer of the material spacer over a sidewall of the gate structure and an area of the first trench, and after forming a source/drain region underneath the first trench, etching the substrate underneath the first trench to a second depth larger than the first depth to form a second trench.

In accordance with another aspect of the present invention, there is provided a method of fabricating a transistor for use in a semiconductor device. The method including: forming an isolation layer defining an active region on a substrate, forming a gate structure over the substrate having the isolation layer, etching a portion of the active region between the gate structure and the isolation layer to form a first trench to a first depth, forming a material layer over the resulting substrate structure, etching the material layer to partially expose the substrate covered by the material layer and leave a discontinuous layer of the material spacer over a sidewall of the gate structure and a sidewall of the isolation layer, and after forming a source/drain region underneath the first trench, etching the substrate underneath the first trench to a second depth larger than the first depth to form a second trench.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Other objects and advantages of the present invention can be understood by the following description, and become apparent with reference to the embodiments of the present invention.

Referring to the drawings, the illustrated thickness of layers and regions are exemplary only and may not be exact. When a first layer is referred to as being “on” a second layer or “on” a substrate, it could mean that the first layer is formed directly on the second layer or the substrate, or it could also mean that a third layer may exist between the first layer and the substrate. Furthermore, the same or like reference numerals represent the same or like constituent elements, although they appear in different embodiments or drawings of the present invention.

FIGS. 2A to 2Hare cross-sectional views describing a method of fabricating a transistor in accordance with an embodiment of the present invention. In particular, a method of fabricating a PMOS transistor using epitaxial growth is illustrated inFIGS. 2A to 2H.

Referring toFIG. 2A, a device isolation layer21is formed on a substrate20to define an active region.

A gate pattern22having a stacked structure of a gate insulation layer, a gate electrode and a gate hard mask is formed on the substrate20, and a gate spacer23is formed on a sidewall of the gate pattern22.

Referring toFIG. 2B, the substrate20on either side of the gate spacer23is etched to a first depth D1to form a first trench T1. The first depth D1may be in a range from about 50 Å to about 500 Å. Reference numeral21A represents an etched device isolation layer.

The first trench T1is formed for a subsequent source/drain region, whereas the trench T of the prior art is formed for growth of the epitaxial layer. The formation of the first trench T1aims to improving leakage current characteristic caused by possible interface defect between the substrate20and a subsequent epitaxial layer by making the subsequent source/drain region sufficiently deep, which will be described later in detail.

Referring toFIGS. 2C and 2D, a material layer24is formed over a resulting structure where the gate pattern22, the gate spacer23and the first trench T1are formed, and the material layer24is anisotropically etched to form a material spacer24A on a sidewall of the first trench T1and/or a sidewall of the gate spacer23.

The material spacer24A is additionally formed in order to reduce the penetration of the dopants under the gate pattern22after being diffused laterally when forming the subsequent source/drain region. This process may be omitted. The material spacer24A may be formed of nitride.

Referring toFIG. 2E, a source/drain region25is formed by ion-implanting P-type dopants such as boron (B) and performing a thermal treatment such as rapid thermal annealing (RTA) for dopant activation.

As described above, since the dopant ion-implantation for formation of the source/drain region25and the thermal treatment are performed on the substrate20where the first trench T1is already formed, the source/drain region is sufficiently deeper than the channel region, leading to improved leakage current characteristic.

In the prior art, the source/drain region15is formed after an uneven epitaxial layer is grown. However, in accordance with the embodiment of the present invention, the source/drain region25is formed, before the growth of the epitaxial layer, within the substrate20where the first trench T1having a uniform depth is formed. Thus, compared with the prior art, the side of the source/drain region25penetrates, to a lesser extent, under the gate pattern22. That is, the overlap between the gate pattern22and the source/drain region25is reduced. Therefore, a short channel margin of the transistor is improved, and in particular, DIBL is improved.

Referring toFIG. 2F, a remaining material spacer24A is removed, and a counter doping region26is formed on the surface of the source/drain region25by performing a counter doping to tilted-ion-implant N-type dopants such as arsenic (As).

The process of forming the counter doping region26on the surface of the source/drain region25may be omitted.

Referring toFIG. 2G, the substrate20on either side of the gate spacer23, where the first trench T1is formed, is etched to a second depth D2to form a second trench T2deeper than the first trench T1. The second depth D2may be in a range from about 100 Å to about 1,000 Å, which is greater than the value of the first depth D1. Reference numerals25A and26A represent an etched side of the source-drain region and an etched counter doping region, respectively.

The second trench T2is formed for growth of a subsequent epitaxial layer.

Referring toFIG. 2H, an epitaxial layer27is formed within the second trench T2by using a sidewall and/or bottom of the second trench T2as a seed layer. At this point, P-type impurities (for example, boron) for forming the etched source/drain region25A are doped in-situ during the growth of the epitaxial layer27.

The epitaxial layer27is used to apply a stress to the channel region of the substrate20. In the case of the PMOS transistor, a compression stress is applied in a direction parallel to the channel region in order to increase the mobility of majority carriers, i.e., holes. Thus, the epitaxial layer27is formed of a material having a larger lattice constant than the substrate20. For example, when the substrate20is a Si substrate, the epitaxial layer27may be a SiGe epitaxial layer.

Through the processes ofFIGS. 2A to 2H, the overlap between the side of the source/drain region25and the gate pattern22is reduced while making the bottom of the source/drain region25sufficiently deep, thus improving leakage current characteristic of the transistor and preventing a short channel effect.

In the method of fabricating the transistor for use in the semiconductor device in accordance with the embodiment of the present invention, the source/drain region is formed before growth of the epitaxial layer. At this point, by forming the source/drain region in a state that the trench has been formed by etching the substrate, the source/drain region is sufficiently deep, and the overlap between the side of the source/drain region and the gate pattern is reduced, leading to improving the leakage current characteristic of the transistor and preventing the short channel effect.