Semiconductor device and method of manufacturing the same

A semiconductor device includes: solder balls provided on an upper package; and pads provided on a lower package and directly connected to the solder balls, wherein at least one of the pads serves as a fiducial mark. Further, a shape of at least one of the pads is different from that of other pads and an area of at least one of the pads is substantially equal to that of the other pads.

This application is based on and claims priority from Japanese Patent Application No. 2006-333998, filed on Dec. 12, 2006, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device formed by directly connecting a solder ball of an upper package to a pad of a lower package and a manufacturing method thereof.

2. Background Art

There is a Package on Package (PoP) technique as one of the important element techniques for downsizing, thinning, etc. in electronic equipment. As a typical example of the PoP technique, a configuration of directly connecting a solder ball of an upper package to a pad of a lower package is given, and a semiconductor device with high density and high performance can be achieved.

In the PoP technique, accuracy of recognition of a package position in the case of mutually bonding packages has an influence on quality of a semiconductor device, so that the accuracy becomes very important. Here, JP-A-9-321086 discloses an example of a manufacturing method of a conventional semiconductor device (seeFIG. 6). According to the method, metal wirings121,122, . . . are formed on a mounting substrate111, and an insulating layer113where an opening114intersecting with each of the metal wirings121,122, . . . is formed is formed. Together with the metal wirings121,122, . . . , a first square alignment mark116is formed and also an opening for partially overlapping with this alignment mark116is formed in the insulating layer113to form a second alignment mark117. Pads151,152, . . . are formed at intersections of the opening114with each of the metal wirings121,122, . . . to form a bump electrode, and a displacement of the pads151,152, . . . can be recognized by recognition of a displacement of the identified corners (corner A, corner B) of the alignment marks116and117.

Further, JP-A-2005-93839 discloses as another example of a manufacturing method of the conventional semiconductor device (seeFIG. 7). According to the method, a circuit element having an electrode on one principal surface and a substrate201having an electrode203for a recognition bump213and an electrode202for a connection bump212disposed on one principal surface are prepared, and the connection bump212and the recognition bump213are respectively formed in the electrode202and the electrode203using a wire bonding method. Based on an image of the recognition bump213photographed using optical means, a position of the recognition bump213is detected and, based on the position, the circuit element is bonded on the substrate201through the connection bump212. Since the top of the recognition bump213has a protrusion shape, it is easy to obtain contrast to the electrode203and thus a position of the recognition bump213can be detected accurately. (See e.g., JP-A-9-321086 and JP-A-2005-93839)

Nowadays, downsizing and thinning in electronic equipment are more advancing and a demand for downsizing and density growth in a semiconductor device is more increasing. However, in the PoP technique for downsizing the semiconductor device, for example, like the conventional semiconductor device shown inFIG. 7, the configuration where the recognition bump etc. for recognizing a package position in a manufacturing process hinders downsizing of the semiconductor device.

SUMMARY OF THE INVENTION

The present invention has been achieved in view of the above, and an object of the present invention is to provide, in particular, small semiconductor device and a manufacturing method thereof and also effectively solve problems such as variations in strength of a bonding part, occurring in the fabrication process.

The present invention solves the above-described problems by the following solution means.

According to a first aspect of the present invention, a semiconductor device comprises:

solder balls provided on an upper package; and

pads provided on a lower package and directly connected to the solder balls, wherein at least one of the pads serves as a fiducial mark (recognition mark).

According to a second aspect of the present invention, a shape of at least one of the pads may be different from that of other pads and an area of at least one of the pads may be substantially equal to that of the other pads.

According to a third aspect of the present invention, at least one of the pads may be provided in two places in diagonal positions on the lower package.

According to a fourth aspect of the present invention, at least one of the pads may be provided in three places in positions forming a triangle on the lower package.

According to a fifth aspect of the present invention, a method of manufacturing a semiconductor device comprises:a) recognizing a position of a lower package placed in a carrier using at least one of pads provided on the lower package and serving as a fiducial mark;b) performing an alignment between solder balls provided on an upper package and the pads provided on the lower package based on the recognized position; andc) directly connecting the pads and the solder balls to form the semiconductor device.

According to the first aspect of the present invention, one pad for serving as a fiducial mark (hereinafter called fiducial mark pad) has effects of functioning as a pad and also functioning as a fiducial mark. Therefore, it becomes unnecessary to separately provide a region for forming a dedicated fiducial mark in the inner periphery or the outer periphery of a pad region as shown in the conventional semiconductor device, so that a substrate and a lower package can be downsized.

According to the second aspect of the present invention, a fiducial mark pad is formed in a shape different from other pads, so that a position of the fiducial mark pad can be recognized while distinguishing the fiducial mark pad from the other pads by a recognition device. Further, the fiducial mark pad and the other pads are formed such that an area of the fiducial mark pad is substantially equal to an area of the other pads, so that the areas, where solder in the fiducial mark pad and the other pads wetly spreads in bonding an upper package to a lower package, can be substantially equalized, and bonding strength and a formation shape of the solder is not adversely affected and a uniform bonding without variations can be achieved.

According to the third and fourth aspects of the present invention, accuracy of position recognition of a lower package can be improved by a configuration in which fiducial mark pads are provided in plural places, for example, in two places in diagonal positions or in three places in positions forming a triangle.

According to the fifth aspect of the present invention, a step for forming a dedicated fiducial mark can be omitted, and a work period and material cost necessary for the formation can be reduced. Also, a substrate and a lower package can be formed smaller than those of the conventional art and the number of packages capable of being placed in a carrier can be increased, so that production efficiency of a semiconductor device can be improved.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the invention will hereinafter be described in detail with reference to the drawings.FIG. 1is a sectional view showing one example of a semiconductor device1according to an embodiment of the invention. Also,FIG. 2is a schematic view showing a configuration of a lower package3of the semiconductor device1.FIG. 3is a schematic view showing a configuration of an upper package2of the semiconductor device1.FIGS. 4A to 4Care schematic views describing a manufacturing method of the semiconductor device according to the embodiment of the invention.FIG. 5is a schematic view showing a configuration of a lower package3of a semiconductor device1according to a second embodiment of the invention. In addition, in numerals of the drawings, numeral17is used as a generic term of numerals17ato17e.

The semiconductor device1as shown inFIG. 1is configured by directly connecting solder balls11of an upper package2to pads16(and fiducial mark pads17as described below) of a lower package3. This is a configuration designated as the so-called Package on Package (PoP).

In the upper package2, a semiconductor chip12is buried in a substrate10and a periphery of the semiconductor chip12is covered with resin as one example (FIG. 1). Also, the solder balls11electrically connected to the semiconductor chip12are provided on a surface opposed to the lower package3in the upper package2.

As shown inFIG. 2etc., in the lower package3, a semiconductor chip18is flip chip mounted on a substrate15as one example. The pads16and pads20(not shown) are provided on a surface of the lower package3. The pads20are electrically connected to the semiconductor chip18. Electrical connection between the semiconductor chip18and external terminals (solder balls11of the upper package2in the present embodiment) is performed through the pads16.

The pad16has a circle shape with the diameter of about 0.3 mm as one example. Of course, the pad16is not limited to the shape and size. Also, the number of pads16provided on the surface of the lower package3depends on a kind of a package, and its arrangement is generally formed in parallel two line shape (FIG. 2) or three line shape in the outer periphery of the lower package3.

For example, as shown inFIG. 2etc., when normal pads16are formed in a circle shape, a part of the pads are formed in a shape other than the circle shape. A pad having the shape other than this circle shape is used as a fiducial mark pad17. A fiducial mark is provided on the surface of the lower package and is a mark used for recognizing a position of the lower package. The position of the lower package is understood by recognizing the mark. Mounting position coordinates of the upper package are decided in accordance with the position of the lower package. The fiducial mark pad17in the embodiment also serves as a terminal in the case of electrically connecting the upper package2to the lower package3as well as the pad16while serving as the fiducial mark. In addition, a shape of the fiducial mark pad17may be any shape as long as the shape is not the same as a shape of the pad16, but it is necessary to differ from the shape of the pad16capable of recognizing as the fiducial mark.

In the embodiment, the fiducial mark pad17is provided as a quadrangle shape (FIGS. 2 and 5). Of course, the shape may be a triangle, a hexagon, etc. Also, according to arrangement and the number of fiducial mark pads17, as a first example, it is preferable that the pads17are provided in two places in diagonal positions on the lower package3like numerals17aand17bshown inFIG. 2. In addition, the arrangement is not limited to the diagonal positions and may be any arrangement as long as a position of the lower package3can be recognized. Also, as a second example, it is preferable that the pads17are provided in three places in positions forming a triangle on the lower package like numerals17c,17dand17eshown inFIG. 5. In addition, the arrangement is not limited to arrangement in the corners and may be any arrangement as long as a position of the lower package3can be recognized. In any case, it is not limited to such examples and it is contemplated to form various arrangements by providing a plurality of fiducial mark pads17.

Also, the fiducial mark pad17is formed so that its area becomes substantially equal to the area of the pad16. Here, “substantially” means that a shape having the physically complete identical area cannot be formed, and also means that an area range (described below) does not affect the strength of bonding to the solder balls11.

Subsequently, effects according to the above configuration will be described. In the semiconductor device1according to the present invention, the fiducial mark pads17are provided on the lower package3. Consequently, one fiducial mark pad17has two effects of serving as an electrical connection terminal and a fiducial mark serving as position recognition of the lower package3upon connecting the upper package2to the lower package3. Particularly, the fiducial mark pad17is formed in a shape different from the pad16, so that a position of the fiducial mark pad17can be recognized while distinguishing the fiducial mark pad17from the other pads16by a lower package position recognition device (not shown). Further, accuracy of the position recognition of the lower package3can be improved in such a manner that the fiducial mark pads17are provided in a plurality of (at least two or more) places.

Moreover, according to the semiconductor device1of the present invention where the fiducial mark pad17is provided, it is not necessary to separately provide a dedicated region for forming a fiducial mark as compared with a configuration in which a fiducial mark pad is provided in the inner periphery or the outer periphery of a pad region as shown in the conventional semiconductor device. Therefore, the substrate15and thus the lower package3can be downsized. Also, by downsizing the lower package3, the number of packages (the number of lower packages3) capable of being placed in a carrier31can be increased, so that production efficiency of the semiconductor device1can be improved.

However, when the fiducial mark pad17is formed from the viewpoint of merely serving as a pad and a fiducial mark, the following bad effect may be caused. Namely, in the case of bonding the upper package2to the lower package3when the fiducial mark pad17differs from the pad16in area with a difference in shape, the fiducial mark pad17differs from the pad16in area in which solder of the solder balls11wetly spreads and then variations are caused in bonding strength and a formation shape of the solder after bonding. Thus, one solder bonding part is likely to break. More specifically, as a cause of the variations, when areas of the mutual pads differ from each other and an area of a pad is wider than that of the other pads, solder much wetly spreads on the pad upon reflow and then the solder portion remaining on the original substrate becomes thin (fine). On the other hand, when an area of a pad is narrower than that of the other pad, solder much remains on the original substrate upon reflow and then the solder portion wetly spreading on the pad becomes thin (fine).

The present invention solves the above-described problem by adopting a configuration in which the fiducial mark pad17and the other normal pads16are formed in such a manner that an area of the pad17is substantially equal to that of the pad16. Namely, by such a configuration, when the fiducial mark pad17is used as a pad for electrical connection, the areas where solder wetly spreads can be substantially equalized upon bonding the upper package2to the lower package3using the fiducial mark pad17and the pad16. Further, bonding strength and a formation shape of the solder is not adversely affected and thus a uniform bonding without variations can be achieved. Therefore, quality of the semiconductor device1is stable and percent defective resulting from poor bonding can be reduced.

Namely, based on a technical idea of the semiconductor device1according to the present invention, a range of (area difference between the fiducial mark pad17and the pad16) the extent to which bonding strength and a formation shape of the solder is not adversely affected in bonding the upper package2to the lower package3is defined as a range in which the areas are substantially equal.

Next, a manufacturing method of the semiconductor device1according to the present invention will be described with reference toFIGS. 4A to 4C. After the upper package2and the lower package3including the configuration as described above are prepared and the lower package3is placed in the carrier31(FIG. 4A), a position of the lower package3in the carrier31is recognized based on the fiducial mark pads17provided on the lower package3using a lower package position recognition device (not shown). Based on the position of the lower package3recognized therein, the solder balls11of the upper package2are aligned with the pads16and the fiducial mark pads17of the lower package3and are directly connected to the pads16, and the pads17(FIG. 4B), so that the semiconductor device1is formed (FIG. 4C). Then, the fiducial mark pad17is formed so that the shape differs from that of the other pad16and the area is substantially equal to that of the other pad16. In addition, as one example, the direct connection is performed by reflowing the solder balls11. Thereafter, a step of filling an under fill material (not shown) between the upper package2and the lower package3generally follows.

Subsequently, effects by the manufacturing method will be described.

For example, in the conventional semiconductor device as shown inFIG. 7, the recognition bumps213as dedicated fiducial marks are formed on a surface of the substrate201constructing the lower package and a position of the lower package (substrate201) is recognized based on the dedicated fiducial marks (recognition bumps213). Meanwhile, according to embodiments of the present invention, a position of the lower package3can be recognized based on the fiducial mark pads17for serving as the pads. Therefore, a step of formation of the dedicated fiducial marks can be omitted, and a work period and material cost necessary for the formation can be reduced.

Further, the substrate15and the lower package3can be formed smaller than those of the conventional semiconductor device. Therefore, the number of packages (the number of lower packages3) capable of being placed in the carrier31can be increased, so that production efficiency of the semiconductor device1can also be improved.

As described above, in accordance with the semiconductor device and the manufacturing method thereof according to the present invention, in the technical field of the semiconductor device where downsizing is particularly important and its demand is remarkable, remarkable downsizing of the semiconductor device formed by a package on package configuration can be achieved, and also a work period and material cost can be reduced and further, the semiconductor device with stable quality is provided and percent defective resulting from poor bonding can be reduced.

In addition, the semiconductor device and the manufacturing method thereof according to the present invention are not limited to the case using a solder bump process, and can also be applied to the case using a pressure welding process.