Power gating circuit and electronic system including the same

A power gating circuit including a first chain buffer that generates a first sleep signal by buffering an input sleep signal, a second chain buffer that generates a second sleep signal by buffering the first sleep signal, and a first switch block including a plurality of first switch cells controlled according to the first sleep signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2013-0149652 filed on Dec. 4, 2013, the disclosure of which is hereby incorporated by reference.

BACKGROUND

One or more aspects of the inventive concept relate to a power gating circuit and an electronic system including same.

A System-on-Chip (hereinafter referred to as ‘SoC’) is a technology-intensive semiconductor technique whereby the certain complicated systems having various functions may be integrated into a single “on-chip” system. A SoC typically includes a processor configured to control the system as well as various “intellectual properties” or “IPs” controlled by the processor. Here, the term ‘IP’ denotes one or more circuit(s), logic element(s), and/or combination(s) of same commonly integrated on a semiconductor fabrication layout that implemented the SoC. Programming code may be stored in one or more circuit(s) of the SoC.

Mobile devices including a SoC having multiple IPs operate us battery-supplied power, and therefore must be designed when power conservation in mind. So-called “power-gating” is a technique used to decrease power consumption in certain mobile devices. Power-gating essentially blocks current consumption by an IP when it is not currently in use.

Power-gating may be performed by arranging a plurality of switch cells in each IP and controlling the plurality of switch cells with a control signal. A high fanout net (HFN), a daisy chain method, a fishbone method, and the like may be used to generate the control signal. Among these methods, a final acknowledgement (ACK) signal is difficult to generate when the HFN or the fishbone method is used in contrast with the daisy chain method. Thus, the daisy chain method is commonly used. However, in the daisy chain method, one buffer is typically configured with each switch cell, and thus leakage consumption is high due to the relatively large number of buffers as compared to implementations wherein the HFN is used.

SUMMARY

According to an aspect of the inventive concept, a power gating circuit configured to perform power gating of an element comprises; a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit, and a first switch block including a plurality of first switch cells controlled by the first sleep signal, and a second chain buffer that generates a second sleep signal by buffering the first sleep signal, and a second switch block including a plurality of second switch cells controlled by the second sleep signal, wherein the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element.

According to another aspect of the inventive concept, a power gating circuit configured to perform power gating of an element comprises; a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit and a first switch block that receive the first sleep signal, and a second chain buffer that generates a second sleep signal by buffering the first sleep signal and a second switch block that receive the second sleep signal. The first switch block comprises a first drive buffer configured to generate a third sleep signal by buffering the first sleep signal and a plurality of first switch cells that receives the third sleep signal. The second switch block comprises a second drive buffer configured to generate a fourth sleep signal by buffering the second sleep signal and a plurality of second switch cells that receives the fourth sleep signal. The second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element.

DETAILED DESCRIPTION

Embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements.

FIG. 1is a block diagram of an electronic system1according to an embodiment of the inventive concept.

Referring toFIG. 1, the electronic system1may be embodied as (or as part of) a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal/portable navigation device (PND), a handheld game console, or a handheld device such as e-book.

The electronic system1generally comprises a system-on-chip (SoC)10, an external memory30, and a display device20.

The SoC10comprises a plurality of intellectual properties (IPs), for example, a central processing unit (CPU)100, a read only memory (ROM)110, a random access memory (RAM)120, a timer130, a display controller140, a graphics processing unit (GPU)150, a memory controller160, a clock management unit (CMU)170, and a bus180.

The SoC10may further include some additional IPs. For example, although not shown inFIG. 1, the SoC10may further comprise a multi-format codec (MFC), a video module (e.g., a camera interface, a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer, etc.), an audio system, a driver, a volatile memory device, a non-volatile memory device, a cache memory, a serial port, an analog-to-digital converter, etc.

The SoC10illustrated inFIG. 1also comprises an internally-disposed power management unit (PMU)190. However, those skilled in the art will appreciate that the PMU190may be externally disposed relative to the SoC10.

The PMU190may be variously connected to the constituent elements of the SoC10(e.g., elements100,110,120,130,140,150160and170(or “elements100through170”), noted above) in order to provide one or more appropriate power supply voltage(s). For example, the PMU190may be used to provide one or more controlled power supply voltage(s) to the elements100through170using one or more techniques, such as dynamic voltage frequency scaling (DVFS), clock gating, and/or power gating.

The CPU100(or “processor”) may be used to receive and process externally provide commands/instructions that control the execution of various data access operations (e.g., read, write (or program), and erase) directed the external memory30. The CPU100may also be used to control the execution of certain housekeeping operations associated with the SoC10and/or external memory30. Thus, the CPU100may control the execution of certain operations synchronously performed in relation to one or more clock signal(s) provided by the CMU170.

In certain embodiments of the inventive concept, the CPU100may be embodied as a multi-core processor, where the term “multi-core processor” is used to denote a class of unitary (single chip) computational elements including two or more independently operated processors (or processing cores, or ‘cores’), each capable in the context of the embodiment illustrated inFIG. 1of controlling the execution of a data access operation in response to corresponding commands/instructions.

The execution of program commands/instruction by the CPU100may involve reading certain “programming information” (e.g., code) stored in the ROM110, RAM120, and/or external memory30. Further, “data” either generated by, related to, or communicated nu execution of programming information by the CPU100may be variously stored in the ROM110, RAM120and/or the external memory30.

Thus, the ROM110may be used to store programming information and/or related data in a nonvolatile manner. Here, the ROM110may be embodied, for example, as an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM) or flash memory.

The RAM120may be used to temporarily store programming information and/or data. For example, programming information (e.g., code) and/or data initially stored in the ROM110or the external memory30may be moved and temporarily stored in the RAM120under control of the CPU100in response to execution of booting code stored in the ROM110. The RAM120may be embodied as a dynamic RAM (DRAM) or a static RAM (SRAM).

The timer130may be used to generate a count value variously used as a timing signal by one or more of the elements100through170time. In certain embodiments, count value or derived timing signal will be generated in response to one or more clock signal(s) provided by the CMU170.

The GPU150may be used to transform data—such as data read from the external memory30by the memory controller160—into one or more data signals appropriately defined in relation to the display device20.

As previously noted, the CMU170may be used to generate one or more clock signal(s). In certain embodiments, the CMU170will include a clock signal generation device, such as a phase locked loop (PLL), a delayed locked loop (DLL), or a crystal oscillator.

One or more of the clock signals generated by the CMU170may be provided to the GPU150, CPU100, memory controller160, and/or other elements of the SoC10. In certain embodiments, at least one of the one or more clock signals generated by the CMU170will be variable in its frequency.

The memory controller160serves as an interface between the SoC10and the external memory30and may be used to control the overall operation of the external memory30and the exchange of data between a host (not shown), the SoC10, and the external memory30. For example, the memory controller160may be used to control the specific execution of read, write (or program) and erase operations directed to the external memory30in response to a request received from the host. Here, the host may be a master device similar to the CPU100, GPU150, and/or display controller140.

The external memory30may take many different forms as a storage medium for data provided by the SoC10. Data may be read from, erased from, and/or written or programmed to the external memory30in response to commands/instructions generated by an operating system (OS), various application programs, and/or various data. The external memory30may be implemented, wholly or in part, as a volatile memory (e.g., one or more DRAM), but might also be implemented, wholly or in part, as a nonvolatile memory (e.g., a flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM

(RRAM), ferroelectric RAM (FeRAM), embedded multimedia card (eMMC), universal flash storage (UFS) etc.). In certain embodiments of the inventive concept, the external memory30will be implemented as a “built-in memory” of the SoC10.

The elements100through170are configured to communicate with one another via the bus180.

The display device20may be variously configured to display images in response to received image data signals provided (e.g.,) by the display controller140, where the display controller140is used to control the overall operation of the display device20. In various embodiments, the display device20may a liquid crystal display (LCD), light emitting diode (LED) display, organic LED (OLED) display, active-matrix OLED (AMOLED) display, flexible display, etc.

Hereafter, certain exemplary embodiments of the inventive concept will be described in the context of a power-gated by the PMU190version of the GPU150. However, this is just one example. Those skilled in the art will recognize form the novel teaching of the subject application that any one or more of the IPs100,110,120,130,140,160, and170might be similarly power-gated by the PMU190.

FIG. 2is a circuit diagram illustrating by way of a comparative example a power gating circuit200having a daisy chain structure, andFIG. 3is a layout diagram of an IP including the power gating circuit200ofFIG. 2.

Thus, referring toFIGS. 2 and 3, GPU150′ is assumed to include the power gating circuit200ofFIG. 2. The power gating circuit200receives an input sleep signal (I_SLEEP). In some aspects, the input sleep signal will be provided by a related power management unit.

The input sleep signal is essentially a type of control signal that blocks power from being supplied by (e.g.,) a power management unit to an associated element (e.g., GPU150′). Thus, according to one set of signal definitions, a logically “high” input sleep signal will enable a supply power to the GPU150′, while a logically “low” input sleep signal will disable the supply.

InFIG. 2, the power gating circuit200includes series-connected first through Nth buffers (e.g., a first buffer210-1through an Nthbuffer210-N), where ‘N’ is a natural number greater than 1. The first buffer210-1through the N-1thbuffer210-(N-1) respectively output first sleep signal (D1) through (N-1)thsleep signal (D(N-1)), while the Nthbuffer210-N outputs a final sleep signal (ACK), where the final sleep signal is output to a power management unit to indicate whether the power gating of the GPU150is complete. The power gating circuit200ofFIG. 2further includes first switch cell220-1through Nthswitch cell220-N, respectively associated with each one of first buffer210-1through Nthbuffer210-N.

With reference toFIG. 3, it is assumed that the GPU150′ includes a plurality of power rails (230-1,230-2, etc.), and that each one of the power rails is formed from a metal or similar conductive material(s). A first reference voltage (VDD) and a second reference voltage (VSS) are alternately applied to opposing ends of the power rails. (The GPU150′ might also include a power mesh (not shown) capable of receiving external power). With this configuration, each one of a plurality of switch cells220-1to220-N may control an electrical connection between the power mesh and one of the power rails.

In one specific arrangement, each of the first switch cell220-1through Nthswitch cell220-N is formed by P-type Metal Oxide Semiconductor (PMOS) transistor that is capable of selectively connecting the power mesh with odd-numbered power rails (e.g.,230-1,230-3, etc.).

For example, a source and drain of the first switch cell220-1may be connected to the power mesh and the first power rail230-1, respectively, and the first sleep signal D1may be supplied to a gate of the first switch cell220-1. Thus, external power received via the power mesh will not supplied to the first power rail230-1of the GPU150′ when the first sleep signal D1is high, but will be supplied to the first power rail230-1of the GPU150′ when the first sleep signal D1is low.

In another specific arrangement, each of the first switch cell220-1to the Nthswitch cell220-N is formed by an N-type MOS (NMOS) transistor that is capable of selectively connecting the power mesh with even-numbered power rail (e.g.,230-2,230-4, etc.).

The semiconductor substrate area existing in a gap between adjacent power rails (e.g., the first power rail230-1and second power rail230-2) in the foregoing arrangement are commonly referred to as a cell rows. A plurality of standard cell libraries (not shown) may be disposed in the cell rows, where the standard cell libraries have the same height and may include various elements such as logic gates, inverters, buffers, etc. An application-specific integrated circuit (ASIC) may be designed by connecting the plurality of standard cell libraries.

Thus, in the daisy chain structure described above, small-sized buffers may be used to reduce leakage. That is, since leakage is generally proportional to buffer size, a relatively smaller buffer will result in less leakage. However, assuming a relatively large-sized buffer by way of comparison, the corresponding maximum capacitance that an associated output pin is capable of driving is also large. Thus, a relatively large-sized buffer may effectively be used to drive a large number of fan-outs. Accordingly, if it is assumed that the number of switches to be connected remains the same, the total area and total amount of leakage may be relatively reduced for cases where a large number of switches is connected to a large-sized buffer, as compared with cases where the same number of switches is connected to small-sized buffers.

FIG. 4is a logic diagram illustrating a power gating circuit300according to an embodiment of the inventive concept.

Referring toFIGS. 1 and 4, the power gating circuit300comprises a chain of buffers (e.g., first chain buffer310-1through Nthchain buffer310-N), wherein each buffer in the chain of buffers is operationally associated with a respective switch block (e.g., first switch block320-1through Nthswitch block320-N. Here, each of the plurality of switch blocks is assumed to include two or more switch cells.

The first chain buffer310-1of the chain of buffers shown inFIG. 4receives an input sleep signal (I_SLEEP) from a corresponding power management unit (e.g., the PMU190ofFIG. 1), and in response, generates a first sleep signal (S1) by buffering the input sleep signal I. From here, and as will be appreciated fromFIG. 4, each Kthchain buffer310-K disposed between the first chain buffer310-1and the (last) Nthchain buffer310-N will receive a sleep signal generated by a preceding chain buffer (a Kth-1 sleep signal) S(K-1)), and will in response, generate a corresponding Kthsleep signal (SK), where ‘K’ ranges from 2 to N-1. In this manner, the Nthchain buffer310-N will ultimately generate a final sleep signal (O_SLEEP) that is provided to the PMU190as a feedback signal indicating that the power gating of the GPU150is complete.

The plurality of switch cells included in each of the first switch block320-1through Nthswitch block320-N may be controlled according to a respective first through Nthsleep signals (S1through O_SLEEP), and may be variously configured from PMOS and/or NMOS transistors.

With this configuration, the power gating circuit300may have a grid type switch cell array structure. That is, the switch cells of the power gating circuit300may be arranged in cell rows that are spaced apart by a predetermined distance from one another, like (e.g.,) the arrangement shown inFIG. 3.

In one specific embodiment of the inventive concept, the power gating circuit300will have a ring type switch cell array structure. That is, the switch cells of the power gating circuit300may be arranged to surround one or more edge(s) of a particular IP layout.

FIG. 5is a logic diagram further illustrating in one example (300a) the power gating circuit300ofFIG. 4.FIG. 6is a layout diagram of an IP including the power gating circuit300aofFIG. 5.

Referring toFIGS. 1, 5, and 6, an IP, e.g., a GPU150a, is assumed to include the power gating circuit300a.

Here, the power gating circuit300aincludes a first chain buffer410-1, a second chain buffer410-2, a first switch block420-1, and a second switch block420-2. Although any reasonable number (‘N’) of chain buffers and switch blocks may be used in various embodiments of the inventive concept,FIG. 5show only two (2) each of such for the sake of brevity of description.

The first switch block420-1includes three (3) switch cells421,422and423, and the second switch block420-2similarly includes three (3) switch cells424,425and426. However, any reasonable number of switch cells greater than 1 switch cell may be used in a switch block incorporated in an embodiments of the inventive concept. Further, the number of switch cells need not be the same as between respective switch blocks arranged in a power gating circuit consistent with embodiments of the inventive concept.

With reference toFIG. 6, the GPU150aagain includes a plurality of metal (or conductive) power rails (e.g.,430-1,430-2, etc.). A first reference voltage (VDD) and a second reference voltage (VSS) may applied to alternate (odd/even) power rails. Gaps between adjacent power rails (e.g., a first power rail430-1and a second power rail430-2) will be referred to as “cell rows”. Here again, a plurality of standard cell libraries may be disposed in cell rows.

The GPU150aofFIG. 6further includes a power mesh6that may be variously configured to receive external power, where the first and second switch blocks520-1and520-2(and constituent switch cells421through426) may be used to control various electrical connection(s) between the power mesh and one or more power rails430-1,430-2, etc.

The GPU150amay be further understood as including a plurality of column regions C1, C2, etc., wherein the switch cells421through426of the first and second switch blocks520-1and520-2are arranged in a columnar relationship at predetermined intervals.

In certain embodiments of the inventive concept, a particular set of switch cells (e.g.,421through426) may be arranged in an aligned pattern (the direction of ‘alignment’ being arbitrarily defined) within a column region (e.g., C1). In other embodiments of the inventive concept, the particular set of switch cells (e.g.,421through426) may be arranged in a staggered pattern across two adjacent column regions (C1and C2).

The first chain buffer410-1may be used to receive an input sleep signal (I_SLEEP) from the PMU190, and in response, to generate a first sleep signal SA1by buffering the input sleep signal. Thus, the first chain buffer410-1will output the first sleep signal SA1in accordance with the ON/OFF transistor state(s) of the switch cells421,422and423. In similar manner, the second chain buffer410-2may be used to generate a second sleep signal SA2by buffering the first sleep signal SA1in accordance with the ON/OFF transistor states of the switch cells424,425and426.

Thus, as illustrated in the example ofFIG. 6, the first chain buffer410-1may be disposed adjacent to one of its switch cells (e.g.,421) and proximate to its other switch cells (e.g.,422and423), while the second chain buffer410-2may be disposed adjacent to one of its switch cells (e.g.,424) and proximate to its other switch cells (e.g.,425and426). However, other dispositional arrangements relative to chain buffers and associated switch cells may be made.

In certain embodiments of the inventive concept, the first chain buffer410-1and the second chain buffer410-2may have a larger size each one of the first buffer210-1through Nthbuffer210-N ofFIG. 2so as to better drive a plurality of switch cells.

That is, the more switch cells included in each respective switch block, the greater the output load on the preceding buffer. And when an output loads are relatively high, a maximum transition time violation (MTTV) may occur with respect to the second sleep signal SA2in a cascade of related sleep signals. Thus, in order to ensure stable operation of a power gating circuit according to an embodiment of the inventive concept, the number of switch cells included in each one of a plurality of daisy-chained switch blocks should be set according to MTTV possibilities, where the MTTV such possibilities are defined in accordance with a standard cell library, and may be related to the slope of an input signal of a switch cell when the input signal transitions from logical high to low, or from logical low to high.

FIG. 7is a logic diagram further illustrating in another example (300b) the power gating circuit300ofFIG. 4, andFIG. 8is a layout diagram of an IP including the power gating circuit300bofFIG. 7. The structures of the power gating circuit300bofFIG. 7and the IP ofFIG. 8are substantially the same as those of the power gating circuit300aofFIG. 5and the IP ofFIG. 6with certain exceptions discussed in detail hereafter.

Referring toFIGS. 1, 7, and 8, the power gating circuit300bcomprises a first chain buffer510-1, a second chain buffer510-2, a first switch block520-1, and a second switch block520-2. Here again, the first chain buffer510-1receives the input sleep signal (I_SLEEP) from the PMU190, and generate the a first sleep signal SB1by buffering the input sleep signal. Thus, the first chain buffer510-1outputs the first sleep signal SB1to the first switch block520-1and the second chain buffer510-2.

The second chain buffer510-2similarly generates a second sleep signal SB2by buffering the first sleep signal SB1, and outputs the second sleep signal SB2to the second switch block520-2and the PMU190, assuming only two (2) chain buffers and two (2) switch blocks in the illustrated example.

The first switch block520-1includes a first drive buffer521and a plurality of first switch cells522,523and524, and the second switch block520-2includes a second drive buffer526and a plurality of second switch cells527,528and529. The number of the first switch cells522to524and the number of the second switch cells527to529may be the same or different from each other.

The first drive buffer521generates a third sleep signal SB3by buffering the first sleep signal SB1, and output the third sleep signal SB3to the first switch cells522to524.

The second drive buffer526may generate a fourth sleep signal SB4by buffering the second sleep signal SB2, and output the fourth sleep signal SB4to the second switch cells527to529.

The first drive buffer521may be disposed adjacent to one of the first switch cells522to524, and the first chain buffer510-1may be disposed adjacent to the first drive buffer521. The second drive buffer526may be disposed adjacent to one of the second switch cells527to529, and the second chain buffer510-2may be disposed adjacent to the second drive buffer526.

In order to drive the first switch cells522to524, the size of the first drive buffer521may be larger than that of the first chain buffer510-1, and in order to drive the second switch cells527to529, the size of the second drive buffer526may be larger than that of the second chain buffer510-2

The size of the first drive buffer521, the size of the first chain buffer510-1, and the number of the first switch cells522to524may be set according to an available wire capacity of each particular layout as well as the capacity of the first switch cells522to524.

In this context, the term “wire capacity” may be understood as the capacity of a wire connected between the first drive buffer521, the first chain buffer510-1, and the first switch cells522to524. The capacity of the first switch cells522to524may be a capacity between a gate, drain, source, and body of a transistor when the first switch cells522to524are each embodied as, for example, a transistor.

As the number of the first switch cells522to524increases, the distance between the first chain buffer510-1and the second chain buffer510-2increases on a layout, thereby increasing the capacity of a wire connecting the first chain buffer510-1and the second chain buffer510-2. Thus, the size of the first chain buffer510-1may be set according to the number of the first switch cells522to524. For example, the greater the number of the first switch cells522to524, the greater the size of the first chain buffer510-1may be set.

According to the embodiment described above, the possibility of MTTV may be reduced by adjusting the slopes of the first and second sleep signals SB1and SB2using the first and second chain buffers510-1and510-2, where the second sleep signal SB2may be used as a final sleep signal SB2(or ACK) indicating completion of power gating for the GPU150b. Also, the total number of buffers may be reduced by connecting a plurality of switches using the first and second drive buffers521and526. Also, since the number of buffers connected in series may be less than when a standard daisy chain arrangement is used, the time required to generate the final sleep signal SB2(or ACK) may be decreased.

FIG. 9is a logic diagram further illustrating in yet another example (300c) the power gating circuit300ofFIG. 4, andFIG. 10is a layout diagram of an IP including the power gating circuit300cofFIG. 9. The structures of the power gating circuit300cof FIG.

9and the IP ofFIG. 10are substantially the same as those of the power gating circuit300bofFIG. 7and the IP ofFIG. 8, with certain exceptions described below.

Referring toFIGS. 1, 9, and 10, the power gating circuit300ccomprises a first chain buffer610-1, a second chain buffer610-2, a first switch block620-1, and a second switch block620-2.

The first chain buffer610-1again receives the input sleep signal (I_SLEEP) from the PMU190and generates a first sleep signal SC1by buffering the input sleep signal. The first chain buffer610-1outputs the first sleep signal SC1to the first switch block620-1and the second chain buffer610-2.

The second chain buffer610-2generates a second sleep signal SC2by buffering the first sleep signal SC1, and outputs the second sleep signal SC2to the second switch block620-2and the PMU190.

The first switch block620-1comprises a first drive buffer621, a third drive buffer626, a plurality of first switch cells622to624, and a plurality of third switch cells627to629. The second switch block620-2may have the same structure as the first switch block620-1, or a different structure.

The first drive buffer621generates a third sleep signal SC3by buffering the first sleep signal SC1, and outputs the third sleep signal SC3to the first switch cells622to624.

The third drive buffer626generates a fifth sleep signal SC5by buffering the first sleep signal SC1, and outputs the fifth sleep signal SC5to the third switch cells627to629. The third drive buffer626may be disposed adjacent to one of the third switch cells627to629.

The respective sizes of the first drive buffer621and third drive buffer626may be the same as or greater than the size of the first chain buffer610-1.

AlthoughFIGS. 9 and 10illustrate an embodiment in which each of the first switch block620-1and the second switch block620-2includes two drive buffers, each of the first switch block620-1and the second switch block620-2may include three or more drive buffers.

FIG. 11is a block diagram illustrating an electronic system including the SoC according to certain embodiments of the inventive concept. Referring toFIG. 11, the electronic system may be implemented as a laptop computer, cellular phone, smartphone, tablet personal computer (PC), personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), portable navigation device(PND), handheld game console, e(electronic)-book device, etc.

The electronic system comprises the SoC10, a power source910, storage device920, memory930, input/output (I/O) ports940, expansion card950, network device960, and display device970. In some embodiments, the electronic system may further include a camera module980.

The SoC10may similar to the SoC10described in relation toFIG. 1. The SoC10may control the operation of at least one of the elements910through980. The power source910may supply an operating voltage to at least one of the elements10, and910through980. According to some embodiments, the power source910may be controlled by the PMU190illustrated inFIG. 1.

The storage device920may be implemented by a hard disk drive (HDD) or a solid state drive (SSD).

The memory930may be implemented by a volatile or non-volatile memory. The memory930may correspond to the external memory30illustrated inFIG. 1. A memory controller (not shown) that controls a data access operation, e.g., a read operation, a write operation (or a program operation), or an erase operation, on the memory930may be integrated into or embedded in the SoC10. Alternatively, the memory controller may be provided between the SoC10and the memory930.

The I/O ports940are ports that receive data transmitted to the electronic system or transmit data from the electronic system to an external device. For instance, the I/O ports940may include a port connecting with a pointing device such as a computer mouse, a port connecting with a printer, and a port connecting with a USB drive.

The expansion card950may be implemented as a secure digital (SD) card or a multimedia card (MMC). The expansion card950may be a subscriber identity module (SIM) card or a universal SIM (USIM) card.

The network device960enables the electronic system to be connected with a wired or wireless network. The display device970displays data output from the storage device920, the memory930, the I/O ports940, the expansion card950, or the network device960. The display device970may be the display device20illustrated inFIG. 1.

The camera module980converts optical images into electrical images.

Accordingly, the electrical images output from the camera module980may be stored in the storage module920, the memory930, or the expansion card950. Also, the electrical images output from the camera module980may be displayed through the display device970.

According to certain embodiments of the inventive concept, a power gating circuit may be provided using relatively few buffers to generate a final sleep (or acknowledge or ACK) signal while at the same time reducing the size of and leakage from the power gating circuit.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made to the illustrated embodiment without departing from the scope of the following claims.