Semiconductor devices having a gate electrode and methods of fabricating the same

An integrated circuit device includes an integrated circuit substrate and a first gate pattern on the substrate. A non-conductive barrier layer pattern is on the first gate pattern. The barrier layer pattern has openings at selected locations therein extending to the first gate pattern. A second gate pattern is on the barrier layer pattern and extends into the opening in the barrier layer pattern to electrically connect the second gate pattern to the first gate pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to and claims priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2006-112966, filed Nov. 15, 2006, the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having a gate electrode and methods of fabricating the same.

As semiconductor devices become more highly integrated, a channel length (e.g., a width of a gate electrode) of a metal-oxide-semiconductor (MOS) transistor therein has generally been reduced. The reduction of the channel length may lead to an increase of electrical resistance of the gate electrode. A multi-layered conductive film has been widely used as the material of the gate electrode to reduce the electrical resistance thereof. For example, the gate electrode may be formed of a combination layer, such as a polycide layer that includes a polysilicon layer and a metal silicide layer having a low resistivity. However, when the gate electrode is formed as a polycide layer, the polycide layer may exhibit a non uniform interface profile between the polysilicon layer and the metal silicide layer in a subsequent annealing process.

In general, the gate electrode is formed by patterning the polycide layer using a photolithography process and an etch process, and a re-oxidation annealing process is performed to cure etch damage caused to a gate insulating layer under the gate electrode during the etch process for forming the gate electrode. However, the gate electrode may lean during the re-oxidation annealing process. The gate leaning phenomenon may be illustrated using an oxidation enhanced silicon consumption model. The oxidation enhanced silicon consumption model may include two components, e.g., a silicon consumption component and a silicon pumping component.

The silicon consumption component relates to a phenomenon that silicon atoms in the polysilicon layer are consumed at an interface between the polysilicon layer and the metal silicide layer during the re-oxidation annealing process. The silicon consumption may occur when the metal silicide layer is a metal rich silicide layer. The silicon pumping component relates to a phenomenon that silicon atoms in the polysilicon layer are moved to form an oxide layer of the metal silicide layer during the re-oxidation process. In other words, when the metal silicide layer is oxidized, metal atoms and silicon atoms in the metal silicide layer are not consumed. Also, the silicon atoms in the polysilicon layer are generally moved by grain boundary diffusion during the re-oxidation process.

When the gate leaning phenomenon occurs, two adjacent gate electrodes may be electrically connected and voids may be generated in an interlayer insulating layer that is formed on the gate electrodes. This gate leaning phenomenon may be more severe when fabricating a MOS transistor having a recessed channel (e.g., a recessed gate). The MOS transistor having a recessed channel has been proposed to suppress a short channel effect of the MOS transistor without any area penalty. The recessed channel may be formed by etching a portion of an active region, and a gate electrode may be formed by stacking a polysilicon layer filling the recessed channel and a metal silicide layer on the polysilicon layer. In this case, a profile of the recessed channel may be transferred to an interface between the polysilicon layer and the metal silicide layer. Thus, the gate leaning phenomenon may more readily occur during fabrication of the MOS transistor having the recessed channel.

SUMMARY OF THE INVENTION

In some embodiments, an integrated circuit device includes an integrated circuit substrate and a first gate pattern on the substrate. A non-conductive silicon atom transfer barrier layer pattern is on the first gate pattern. The barrier layer pattern has openings at selected locations therein extending to the first gate pattern. A second gate pattern is on the barrier layer pattern and extends into the opening in the barrier layer pattern to electrically connect the second gate pattern to the first gate pattern.

In other embodiments, the first gate pattern is a polysilicon layer and the second gate pattern is a metal silicide layer. The barrier layer pattern may be a material layer that limits movement of silicon atoms from the first gate pattern into the second gate pattern. The barrier layer pattern may be a silicon nitride layer, a silicon oxynitride layer and/or a silicon oxide layer.

In further embodiments, the second gate pattern is a tungsten silicide layer, a combination of tungsten silicide and tungsten nitride, or a combination of tungsten, tungsten nitride and tungsten silicide. The barrier layer pattern may be a plurality of sub-barrier layer patterns that are separated from one another to define the openings in the barrier layer pattern and a portion of the first gate pattern is exposed by at least one of spaces between the sub-barrier layer patterns.

In other embodiments an integrated circuit device includes an integrated circuit substrate and an isolation layer in the substrate that defines a plurality of active regions. A first gate pattern is disposed on the active regions and the isolation layer that extends along a gate pattern direction. A second gate pattern is on the first gate pattern and a barrier layer pattern is between the first and second gate patterns. The barrier layer pattern is configured to electrically connect the first gate pattern to the second gate pattern.

In further embodiments, the device further includes at least one recessed region in each of the active regions and the first gate pattern fills the recessed region in each of the active regions. The first gate pattern may be a polysilicon layer and the second gate pattern may be a metal silicide layer. The barrier layer pattern may be a silicon nitride layer, a silicon oxynitride layer and/or a silicon oxide layer. The second gate pattern may be a tungsten silicide layer, a combination of tungsten silicide and tungsten nitride, or a combination of tungsten, tungsten nitride and tungsten silicide.

In further embodiments the barrier layer pattern is a plurality of sub-barrier layer patterns that are separated from one another and a portion of the first gate pattern is exposed by at least one of spaces between the sub-barrier layer patterns. The barrier layer pattern may have an opening that exposes a portion of the first gate pattern.

In yet further embodiments, a method of fabricating an integrated circuit device includes forming a first gate conductive layer on an integrated circuit substrate. A non-conductive silicon atom transfer barrier layer is formed on the first gate conductive layer, the barrier layer having an opening that exposes a portion of the first gate conductive layer. A second gate conductive layer is formed on the barrier layer and extending into the opening to electrically connect the second gate conductive layer to the first gate conductive layer. The second gate conductive layer, the barrier layer and the first gate conductive layer are patterned to form a first gate pattern, a barrier layer pattern disposed on the first gate pattern, and a second gate pattern disposed on the barrier layer pattern and extending into the opening to contact the first gate pattern.

In other embodiments, forming the first gate conductive layer is preceded by forming an isolation layer in the integrated circuit to define an active region and etching a portion of the active region to form at least one recess region in the active region. Forming the first gate conductive layer includes forming the first gate conductive layer to fill the recessed region and to cover the active region and the isolation layer. Forming the barrier layer may include forming the opening over the active region and/or the isolation layer.

In further embodiments, the first gate conductive layer is a polysilicon layer and the second gate conductive layer is a metal silicide layer. The barrier layer may be a silicon nitride layer, a silicon oxynitride layer and/or a silicon oxide layer. Forming the barrier layer may include forming a plurality of sub-barrier layer patterns that are separated from one another to define the opening in the barrier layer pattern and a portion of the first gate pattern is exposed by at least one of spaces between the sub-barrier layer patterns.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Some embodiments will now be described that are directed to a semiconductor device including a recessed gate that has a bottom surface lower than a top surface of a semiconductor substrate and a method of fabricating the same. However, the present invention is not limited to such semiconductor devices having a recessed gate. For example, some embodiments of the present invention may be applied to a conductive pattern on a flat surface without any recessed profile and/or a gate electrode of a planar MOS transistor without any recessed channel. Further, even though some embodiments of the present invention are described in conjunction with the gate electrode including a polysilicon layer and a metal silicide layer, embodiments of the present invention may be applied to other conductive patterns, for example, those including three or more layers of stacked structure.

FIG. 1is a plan view illustrating an integrated circuit device, in particular a semiconductor device having a recessed gate, according to some embodiments of the present invention. Referring toFIG. 1, active regions60are provided in an integrated circuit substrate such as a semiconductor substrate. The active regions60may have a specific configuration, as shown inFIG. 1. However, the active regions60may have a different configuration from that shown inFIG. 1. The active regions60may be separated from one another by an isolation layer110. A plurality of gates175extend across and over the active regions60. For example, two of the plurality of gates175may be disposed to intersect one of the active regions60as shown inFIG. 1. This arrangement of the gates175is shown for exemplary purposes and the present invention is not limited to such an arrangement.

The gates175may be parallel to a y-axis (column) and the active regions60may be parallel to an “m” direction. The active regions60may be disposed to intersect an x-axis (row). In other embodiments, however, the active regions60may be disposed, for example, to be parallel to the x-axis. The x-axis and the y-axis are axes of coordinates that cross at a right angle. For the purpose of convenience in explanation, a line which is parallel to the “m” direction is referred to as an inclined row hereinafter. Both edges of the active regions60in a specific inclined row may overlap with both edges of the active regions60in another inclined row that is adjacent to the specific inclined row.

The gates175may intersect the active regions60at a predetermined angle α. In some embodiments, the angle α may be a right angle, an acute angle or an obtuse angle.

Each of the gates175may comprise a first gate pattern and a second gate pattern, which are sequentially stacked. Each gate175may further comprise a barrier layer pattern disposed between the first and second gate patterns. The barrier layer pattern may expose a portion of the first gate pattern. Accordingly, the second gate pattern may be electrically connected to the first gate pattern.

The barrier layer pattern, according to some embodiments, will be described in more detail with reference toFIGS. 2A to 2C. To simplify the drawings, the second gate patterns on the barrier layer patterns are not shown inFIGS. 2A to 2C.

FIG. 2Ais a plan view illustrating barrier layer patterns150aaccording to some embodiment of the present invention. Referring toFIG. 2A, the first gate patterns140aare disposed to be parallel to the columns. The barrier layer patterns150aare disposed on the first gate patterns140a, respectively. Each of the barrier layer patterns150aincludes openings155athat expose some portions of the first gate pattern140a. In the illustrated embodiments ofFIG. 2A, the openings155amay be located over the active regions60. Accordingly, the first gate pattern140a(e.g., polysilicon pattern) may be in contact with the second gate pattern (e.g., metal silicide pattern) through the openings155a. The position and the number of the openings155amay be varied by those skilled in the art without departing from the spirit and scope of the present invention. For example, the openings155amay be located over the isolation layer or both the active region and the isolation layer.

FIG. 2Bis a plan view illustrating a barrier layer pattern150baccording to further embodiments of the present invention. Referring toFIG. 2B, the barrier layer patterns150bis disposed on each of the first gate patterns140a. The barrier layer pattern150bmay comprise a plurality of sub-barrier layer patterns that are separated from one another to provide spaces155btherebetween. Thus, some portions of the first gate pattern140amay be exposed by the spaces155b, and the spaces155bmay overlap with the active regions60. Accordingly, the first gate pattern140a(e.g., polysilicon pattern) may be in contact with the second gate pattern (e.g., metal silicide pattern) through the spaces155b.

The sub-barrier layer patterns shown inFIG. 2Bmay extend onto the active regions60as illustrated inFIG. 2C. In this case, the contact area between the first and second gate patterns may be reduced as compared to the embodiments shown inFIG. 2B. Referring toFIG. 2C, the barrier layer pattern150cmay also comprise a plurality of sub-barrier layer patterns that are separated from one another and the sub-barrier layer patterns may be located over the isolation layer. Spaces155cbetween the sub-barrier layer patterns may be located over the active regions60. However, the spaces155cmay be narrower (relative to the first gate pattern140a) than the spaces155bof the embodiments shown inFIG. 2B. The first gate pattern140a(e.g., polysilicon pattern) may be in contact with the second gate pattern (e.g., metal silicide pattern) through the spaces155c.

According to some embodiments as described above, the barrier layer patterns150a,150bor150care disposed between the first and second gate patterns, and the first and second gate patterns may contact each other through the openings155aor the spaces155bor155cthat are defined by the barrier layer patterns150a,150bor150c. Thus, the reaction between the first and second gate patterns may be significantly suppressed due to the presence of the barrier layer patterns150a,150bor150ctherebetween. In other words, the barrier layer patterns150a,150bor150ccan suppress a silicon migration phenomenon where silicon atoms in the first gate patterns move into the second gate patterns. This may be the case as the barrier layer patterns150a,150band/or150creduce the contact area between the first and second gate patterns.

FIG. 3is a cross sectional view taken along the lines I-I′, II-II′ and III-III′ ofFIG. 1, to further illustrate gate structures according to some embodiments of the present invention. Referring toFIG. 3, a pair of recessed regions120are provided in an active region60. A gate insulating layer pattern130ais disposed on a sidewall and a bottom surface of each recessed region120. Two recessed gates175are disposed to cross over the active region60. Each of the recessed gates175includes a first gate pattern140a, a second gate pattern160aand a barrier layer pattern150atherebetween. The first gate pattern140amay comprise a polysilicon layer and fill the recessed region120. The second gate pattern160amay comprise a metal silicide layer and contact the first gate pattern140athrough openings155athat penetrate the barrier layer pattern150a. The barrier layer pattern150amay comprise a material layer that limits or even prevents silicon atoms in the first gate pattern140afrom being diffused into the second gate pattern160a. For example, the barrier layer pattern150amay comprise a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and/or a combination layer thereof. The silicon atoms in the first gate pattern140amay be diffused into the second gate pattern160asubstantially only through the openings155ain the barrier layer pattern150aduring a subsequent annealing process.

The second gate pattern160amay comprise a single layer, for example, of tungsten silicide, a combination layer of tungsten silicide and tungsten nitride, and/or a combination layer of tungsten, tungsten nitride and tungsten silicide.

A hard mask pattern170ais disposed on the recessed gate175, e.g., the second gate pattern160a. The hard mask pattern170amay comprise, for example, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer and/or a combination layer thereof.

The openings155amay be located over the active regions60, e.g, the recessed regions120. However, the position and the number of the openings155amay be varied without departing from the spirit and scope of the present invention. For example, the openings155amay be located over the isolation layer or both the active region and the isolation layer.

In other embodiments, the barrier layer pattern150amay be replaced with the barrier layer pattern150bhaving the spaces155bdescribed with reference toFIG. 2Band/or the barrier layer pattern150chaving the spaces155cdescribed with reference toFIG. 2C.

FIGS. 4A to 4Eare cross sectional views illustrating a method of fabricating the semiconductor device shown inFIG. 1according to some embodiments of the present invention.FIGS. 4A to 4Eare cross sectional views taken along the lines I-I′, II-II′ and III-III′ ofFIG. 1.

Referring toFIG. 4A, an isolation layer110is formed in a semiconductor substrate100to define active regions110. The isolation layer110may be formed, for example, using a shallow trench isolation (STI) technique. The active regions110may be etched to form recessed regions120in the active regions110. Lower corners of the recessed regions120may be rounded using, for example, a wet cleaning process and/or a dry cleaning process. The wet cleaning process may be performed using a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and de-ionized water (H2O).

As shown inFIG. 4B, a gate insulating layer130ais formed on the substrate having the recessed regions120. A polysilicon layer140is formed on the gate insulating layer130a. The polysilicon layer140may be formed, for example, to a thickness of about 500 to 1500 Å. The polysilicon layer140is formed to fill the recessed regions120. A barrier layer150is formed on the polysilicon layer140. The barrier layer150may be formed, for example, to a thickness of about 10 to 250 Å.

In some embodiments, the barrier layer150may be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer or a combination layer thereof. When the barrier layer150is formed of a silicon oxide layer, the barrier layer150(e.g., the silicon oxide layer) may be formed, for example, to a thickness of about 10 to 250 Å using, for example, a thermal oxidation technique and/or a chemical vapor deposition technique.

A mask pattern200, for example, a photoresist pattern, is formed on the barrier layer150. The mask pattern200may be formed to have various shapes as illustrated inFIGS. 5 and 6.

Referring toFIGS. 5 and 6, the mask pattern200may be formed to have line-shaped openings205. Each of the line-shaped openings205may overlap with the active regions60which are arrayed in a specific inclined row, as shown inFIG. 5. In some embodiments, each of the line-shaped openings205may be formed to be parallel to the x-axis and to intersect the active regions60, as shown inFIG. 6. In other embodiments, the mask pattern200may be formed to have hole-shaped openings207(FIG. 7), which are located over the recessed regions120. InFIGS. 5,6and7, reference numerals175indicated by dotted lines represent gate patterns to be formed in a subsequent process.

Referring toFIG. 4C, the barrier layer150may be etched, using the mask pattern200as an etching mask, thereby forming openings153that penetrate the barrier layer150and expose some portions of the polysilicon layer140. The mask pattern150is then removed.

Referring toFIG. 4D, a metal silicide layer160is formed on the barrier layer150and the polysilicon layer140exposed by the openings153. The metal silicide layer160may be formed to a thickness of about 500 to 2000 Å. The metal silicide layer160may be formed, for example, of a tungsten silicide layer, a combination layer of tungsten silicide and tungsten nitride, or a combination layer of tungsten, tungsten nitride and tungsten silicide. A plurality of hard mask patterns170aare shown formed on the metal silicide layer160. The hard mask patterns170amay be formed to cross over the active regions60and overlap with the recessed regions120. The hard mask patterns170amay be formed, for example, of a silicon nitride layer and/or a silicon oxynitride layer.

Referring toFIG. 4E, the metal silicide layer160, the barrier layer150and the polysilicon layer140are, for example, successively etched using the hard mask patterns170aas etching masks, thereby forming a plurality of recessed gates175. A thermal oxidation process may be carried out to cure etch damage caused to the active regions60during the etch process for forming the recessed gates175.

Although not shown inFIG. 4E, impurity ions may be implanted into the active regions60using the recessed gates175as ion implantation masks, thereby forming lightly doped drain (LDD) regions at both sides of each of the recessed gates175. Gate spacers may be then formed on sidewalls of the recessed gates175. Impurity ions may then be implanted into the active regions60using the gates175and the gate spacers as ion implantation masks, thereby forming high concentration (highly doped) source/drain regions.

An etch stop layer and an interlayer insulating layer may be sequentially formed on the substrate having the high concentration source/drain regions. The etch stop layer may be formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer. For example, when the interlayer insulating layer is formed of a silicon oxide layer, the etch stop layer may be formed of a silicon nitride layer. The interlayer insulating layer and the etch stop layer may be patterned to form contact holes that expose the high concentration source/drain regions. The contact holes may be formed using the gate spacers as etch top layers. In this case, the contact holes may be self-aligned contact holes.

According to some embodiments as described above, a barrier layer between first and second gate patterns may suppress a silicon consumption phenomenon and a silicon pumping phenomenon where silicon atoms in the first gate pattern are segregated into the second gate pattern during an annealing process. Further, even though the silicon atoms in the first gate pattern are segregated into the second gate pattern through openings in the barrier layer, the barrier layer on both edges of the first gate pattern may act as a support layer to limit or even prevent leaning of the first and second gate patterns.

As described above, in some embodiments, a semiconductor device includes first and second gate patterns sequentially stacked on a semiconductor substrate. A barrier layer pattern is disposed between the first and second gate patterns. The barrier layer pattern is configured to electrically connect the first gate pattern to the second gate pattern.

In some embodiments, the first gate pattern may comprise a polysilicon layer and the second gate pattern may comprise a metal silicide layer. The barrier layer pattern may comprise a material layer that prevents silicon atoms in the first gate pattern from being segregated into the second gate pattern. For example, the barrier layer pattern may comprise a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer or a combination thereof. The second gate pattern may comprise a tungsten silicide layer, a combination of tungsten silicide and tungsten nitride, or a combination of tungsten, tungsten nitride and tungsten silicide.

In other embodiments, the barrier layer pattern may comprise a plurality of sub-barrier layer patterns that are separated from one another. A portion of the first gate pattern may be exposed by at least one of spaces between the sub-barrier layer patterns.

In still other embodiments, the barrier layer pattern may have an opening that exposes a portion of the first gate pattern.

In other embodiments, the semiconductor device includes an isolation layer formed in a semiconductor substrate to define a plurality of active regions. A first gate pattern is disposed on the active regions and the isolation layer to extend along a first direction. A second gate pattern is stacked on the first gate pattern and a barrier layer pattern is disposed between the first and second gate patterns. The barrier layer pattern is configured to electrically connect the first gate pattern to the second gate pattern.

In some embodiments, at least one recessed region may be additionally provided in each of the active regions. The first gate pattern may fill the recessed region.

In other embodiments, the first gate pattern may comprise a polysilicon layer and the second gate pattern may comprise a metal silicide layer. For example, the second gate pattern may comprise a tungsten silicide layer, a combination of tungsten silicide and tungsten nitride, or a combination of tungsten, tungsten nitride and tungsten silicide. The barrier layer pattern may comprise a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer or a combination thereof.

In still other embodiments, the barrier layer pattern may comprise a plurality of sub-barrier layer patterns that are separated from one another, and a portion of the first gate pattern may be exposed by at least one of spaces between the sub-barrier layer patterns.

In yet other embodiments, the barrier layer pattern may have an opening that exposes a portion of the first gate pattern.

In still other embodiments, the present invention is directed to a method of fabricating a semiconductor device. The method includes forming a first gate conductive layer on a semiconductor device. A barrier layer is formed on the first gate conductive layer. The barrier layer has an opening that exposes a portion of the first gate conductive layer. A second gate conductive layer is formed on the barrier layer and the exposed portion of the first gate conductive layer. The second gate conductive layer, the barrier layer and the first gate conductive layer are patterned to form a first gate pattern, a barrier layer pattern disposed on the first gate pattern to have the opening, and a second gate pattern disposed on the barrier layer pattern to contact the first gate pattern through the opening.

In some embodiments, an isolation layer may be formed in the semiconductor substrate to define an active region, prior to formation of the first gate conductive layer. A portion of the active region may be then etched to form at least one recess region in the active region. The first gate conductive layer may be formed to fill the recessed region and to cover the active region and the isolation layer. The opening may be formed over at least one of the active region and the isolation layer.

In other embodiments, the first gate conductive layer may comprise a polysilicon layer and the second gate conductive layer comprises a metal silicide layer.

In still other embodiments, the barrier layer may comprise a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer or a combination thereof.