Methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers

Embodiments of the present invention provide methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers. A copper region is formed in a dielectric layer. A diffusion barrier comprising a self-assembled monolayer is deposited over the copper region. A capping layer is deposited over the self-assembled monolayer. In some embodiments, the capping layer and self-assembled monolayer are deposited in the same process chamber.

FIELD OF THE INVENTION

This invention relates generally to the field of semiconductors, and more particularly, to methods of in-situ vapor phase deposition of self-assembled monolayers.

BACKGROUND

As integrated circuit device size continues to shrink in order to achieve higher operating frequencies, lower power consumption, and overall higher productivity, fabricating reliable interconnections has become increasingly difficult with respect to both manufacturing and performance.

In order to fabricate a reliable device with a fast operating speed, copper (Cu) is becoming a material of choice for forming the interconnection lines since it has lower electrical resistance compared with that of aluminum and is less prone to electromigration and stress migration.

However, Cu has various shortcomings. For example, Cu has bad adhesive strength to SiO2 and other dielectric materials. Hence, reliable diffusion barriers and adhesion promoters are needed to make copper interconnects feasible. Some currently used interfacial barrier layer materials include tantalum (Ta), tantalum nitride (TaN) and titanium (TiN). When these layers are deposited by conventional methods, they are difficult to form as uniform and continuous layers. This is especially true when the layers to be deposited are less than 10 nanometers thick, and when the layers are formed in high aspect ratio (e.g., depth to width) features such as vias. The Cu/capping layer interface has been known to contribute to electromigration (EM) failure, so optimizing the Cu/cap interface is critical for EM reliability performance. It is therefore desirable to have improved methods for forming copper adhesion promoters and diffusion barriers.

SUMMARY

In general, embodiments of the invention provide a method for in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers. A copper region is formed in a dielectric layer. A diffusion barrier made of a self-assembled monolayer is deposited over the copper region. A capping layer is deposited over the self-assembled monolayer. In some embodiments, the capping layer and self-assembled monolayer are deposited in the same process chamber. Embodiments of the present invention may provide advantages such as reduced risk of unwanted oxidation of the copper region during the fabrication process, reduced material waste, and improved adhesion and effectiveness of the barrier layer between the copper region and the capping layer, as compared to prior art barrier layer materials.

One aspect of the present invention includes a method of forming a semiconductor structure. The method includes forming a via in a dielectric layer; forming a first barrier layer in the via; forming a copper region in the via; depositing a second barrier layer over the copper region; and depositing a capping layer over the second barrier layer. Depositing a second barrier layer includes depositing a self-assembled monolayer in a chamber of a chemical vapor deposition tool.

Another aspect of the present invention includes a method of forming a semiconductor structure. The method includes forming a via in a dielectric layer; forming a first barrier layer in the via; forming a copper region in the via; depositing a second barrier layer over the copper region; and depositing a capping layer over the second barrier layer. Depositing a second barrier layer includes depositing a self-assembled monolayer in a chamber of an atomic layer deposition tool.

Another aspect of the present invention includes a method of forming a semiconductor structure. The method includes forming a via in a dielectric layer; forming a first barrier layer in the via; forming a copper region in the via; depositing a second barrier layer over the copper region; and depositing a capping layer over the second barrier layer. Depositing a second barrier layer includes depositing a self-assembled monolayer in a chamber of a plasma enhanced chemical vapor deposition tool.

DETAILED DESCRIPTION

Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. Exemplary embodiments of the invention provide approaches for deposition of self-assembled monolayer (SAM) films using in-situ vapor phase deposition techniques. In some embodiments, a SAM film is formed over a copper region, and a capping layer is in turn formed over the SAM film in the same processing chamber. This reduces the risk of undesirable copper oxidation during the fabrication process. Furthermore, the strong interfacial bonding can immobilize Cu, and reduce Cu ion injection into the ILD interface, therefore lowering the time-dependent dielectric breakdown (TDDB) risk.

It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.

With reference again to the figures,FIG. 1shows a semiconductor structure100at a starting point for an embodiment of the present invention. Semiconductor structure100includes a dielectric layer102. Dielectric layer102may be an interlevel dielectric layer (ILD). The ILD may contain multiple dielectric layers and optionally, one or more etch stop layers.

FIG. 2shows a semiconductor structure200after a subsequent processing step of forming a via104in the dielectric layer102. The via may be formed using industry-standard etching and lithographic techniques.

FIG. 3shows a semiconductor structure300after a subsequent processing step of forming a first barrier layer106on the interior surfaces of the via104. The first barrier layer may be a metal layer, such as a tantalum based layer. The first barrier layer may be formed by any suitable deposition method, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

FIG. 4shows a semiconductor structure400after a subsequent processing step of forming a copper region108, filling the via (compare with104ofFIG. 3). The copper region108may be formed by any suitable deposition method, including, but not limited to, electroplating. After deposition of copper region108, Cu is annealed to stabilize the crystal structure, and then a planarization process, such as a chemical mechanical polish (CMP) may be performed to make the copper region108planar with the first barrier layer106and dielectric layer102.

FIG. 5shows a semiconductor structure500after a subsequent processing step of forming a second barrier layer110. The second barrier layer is a self-assembled monolayer (SAM), and is deposited via in-situ vapor phase deposition techniques. In one embodiment, the SAM layer110is deposited via a chemical vapor deposition tool. In another embodiment, the SAM layer110is deposited via a plasma enhanced chemical vapor deposition tool. In embodiments, the SAM layer110has a thickness T ranging from about 10 angstroms to about 30 angstroms. Embodiments of the present invention may utilize a variety of SAMs, including, but not limited to, amino-silanes, mercapto-silanes, and organosilanes with aromatic rings.

Some of the amino-silane SAMs that may be used include:

4-aminophenyltrimethoxysilane; and

Some of the mercapto-silane SAMs that may be used include:

Organosilanes with an aromatic ring may include (CH2)n-Si(OCH3)3.

Parameters for the deposition may include a reaction temperature in the range of about 50 degrees Celsius to about 120 degrees Celsius, a silane precursor vapor pressure ranging from about 0.1 Torr to about 10 Torr, and a reaction time ranging from about 1 minute to about 30 minutes.

FIG. 6shows a semiconductor structure600after a subsequent processing step of forming a capping layer112. In embodiments, the capping layer112may include silicon carbide or silicon carbide nitride. In embodiments, the capping layer112may be deposited in the same chamber as the second barrier layer110. This provides the advantage of preventing the formation of oxide on copper region108, as it limits the exposure of copper region108to ambient air. Other advantages may include reduction of the generation of contaminated effluents and polymerized products, and efficient coating of high-aspect-ratio structures. In other embodiments, a first chamber may be used for depositing the second barrier layer110and a second chamber used for depositing the capping layer112. A transfer chamber may be used to transport wafers between the first and second chambers. In these embodiments, the second barrier layer110may be deposited from an atomic layer deposition (ALD) chamber, or a plasma-enhanced ALD (PEALD) chamber.

FIG. 7shows a flowchart700according to illustrative embodiments. In process step750, a via is formed (see104ofFIG. 2). In process step752, a first barrier region is formed (see106ofFIG. 3). In some embodiments, the first barrier region may be of a metal or metal compound, such as tantalum or a tantalum based compound. In other embodiments, the first barrier region may include a self-assembled monolayer. In some embodiments, the first barrier region may be of the same material as the second barrier region. In process step754, a copper region is formed (see108ofFIG. 5). In process step756, a second barrier region is formed (see110ofFIG. 5). The second barrier region is a self-assembled monolayer, and is deposited via in-situ vapor deposition, using a tool such as a chemical vapor deposition (CVD) tool, plasma enhanced chemical vapor deposition (PECVD) tool, ALD tool or PEALD tool. In process step758, a capping layer is deposited (see112ofFIG. 6). In embodiments, the capping layer112may include silicon carbide or silicon carbide nitride. In embodiments, the capping layer112may be deposited in the same chamber as the second barrier layer110in subsequent processing steps. Therefore, both the second barrier layer110and capping layer112are deposited on the semiconductor structure without the semiconductor structure (e.g. wafer) leaving the chamber in between the deposition of the second barrier layer110and the deposition of the capping layer112.

FIG. 8shows a portion of a deposition tool800for carrying out illustrative embodiments. Deposition tool800includes a processing chamber870. Disposed within chamber870is a wafer872, which is supported by a pedestal874. A reaction gas is applied evenly to the wafer872via gas inlet876. The pressure within the processing chamber870is controlled via regulating valve878. By depositing both the second barrier layer110and the capping layer112in chamber870, the problem of unwanted oxidation on copper region108is mitigated (seeFIG. 6), and thus, the semiconductor fabrication process is improved.

In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also include hardware, software or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application-specific integrated circuits (ASIC), programmable logic arrays (PLA)s, logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.

It is apparent that there has been provided approaches for in-situ vapor phase deposition of self-assembled monolayers. While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.