Inverted multilayer semiconductor device assembly

An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with an active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.

FIELD OF THE INVENTION

The invention relates to stacked circuits, and more particularly to a stacked circuit having an inverted device and to a stacked circuit having an inverted device with a different crystal orientation.

BACKGROUND DESCRIPTION

SOI (Silicon On Insulator) technology reduces or eliminates bulk CMOS latch-up problems. Additionally, SOI technology reduces junction capacitance and allows circuits to operate at higher speeds. Accordingly, SOI technology allows a higher circuit density to be achieved on a silicon wafer.

A multiple layer device structure can be created using SOI technology. Each level of a multilevel structure created using SOI may be interconnected using vertical plugs. Metal connections can be used at any level. In a multilevel device, NMOS and PMOS devices may each be restricted to a separate level, or NMOS and PMOS devices may be intermixed on a single level. However, having multiple levels where each level requires a set of separate metal connections may result in a large number of metal connections, increasing the complexity and costs of the chip. Furthermore, a layer of a multilevel device may inhibit cooling of adjacent layers by limiting heat transfer therefrom.

For some types of semiconductor devices, it is advantageous to have multiple layers of similar semiconductor material, where each layer has a crystal orientation different from the adjoining layers. When multi-layer devices are formed from a common semiconductor layer they will have the same crystal orientation from one level to the next. This limitation on the crystal orientation across multiple levels of an integrated circuit results from constraints imposed by the fabrication process.

In particular, semiconductor material is traditionally grown from a pre-existing layer of semiconductor material. During the material growth process, the atoms of the newly formed layer have a strong tendency to orient themselves to the pre-existing substrate's crystal structure as they are laid down. Thus, it becomes very difficult to create a new layer of similar semiconductor material having a crystal orientation which is different from the underlying layer.

SUMMARY OF THE INVENTION

In a first aspect of the invention, a method of forming a semiconductor device assembly includes forming a first semiconductor device having a first crystal region and a second semiconductor device having a second crystal region. The first semiconductor device is placed in contact with the second semiconductor device.

In another aspect of the invention, the method includes forming a first semiconductor device having a first crystal orientation in a substrate and forming a second semiconductor device having a second crystal orientation in a substrate. The first semiconductor device is placed in contact with the second semiconductor device.

In yet another aspect of the invention, the semiconductor device assembly includes an NMOS device having a first crystal orientation and a PMOS device having a second crystal orientation inverted on a surface of the NMOS device.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In embodiments of the invention, a first CMOS device, such as a pFET, is formed having a first crystal orientation in the active region of the device, and a second CMOS device, such as an nFET, is formed having a second crystal orientation in the active region of the second device. After both devices are formed, the second device is flipped over and bonded to the first device with a bonding layer such as SiO2forming an inverted stacked or an inverted multi-layered arrangement. At lease one of the contacts of the first device is aligned with the corresponding contact of the second device, and the two contacts are brought into electrical contact with one another during bonding. Because the two devices are bonded in an inverted stacked arrangement, the devices are easily interconnected along the boundary between the two devices. Thus, it is possible to form stacked layers of CMOS devices where each layer has either the same or a different crystal orientation in the active region as a layer below it and/or a layer above it, and the combination of devices has a reduced number of connections.

Referring toFIG. 1, a first device100has silicon (Si) substrate105with a crystal orientation of [110] and a first SiO2layer107formed on top of the first Si substrate105. A first Si layer120also having a crystal orientation of [110] is formed on the SiO2layer107. Trenches are etched and filled with an insulating material such as an oxide to form shallow trench isolations110on either side of the active region of the first Si layer120. Source/drain regions115are formed next to shallow trench isolations110in the first Si layer120. The source/drain regions115are formed by any of the methods well known in the art for forming source/drain regions.

The upper surface of the first Si layer120is planarized after the source/drain regions115are formed using any of the methods well known in the art to planarize a Si layer. A second SiO2layer125is formed over a surface of the first Si layer120. A polysilicon gate130is formed on top of the second SiO2layer125such that a portion of the second SiO2layer125forms a gate oxide for the first gate130of the first device100.

A CA gate contact140is formed on the gate130and a metal (M1) contact155is formed on the gate contact140. Source/drain CA contacts135and145are formed on the source/drains115. Source/drain MI160and150and gate metal155are formed thereon, respectively.

A dielectric165is formed over the top of the first device100, and the top of the dielectric165is planarized. Additionally, the dielectric165may be etched so that the gate metal155and the source/drain metal150are slightly higher than the surrounding dielectric165to facilitate making positive contact thereon during a later bonding process. Such an etching process may include etching the top surface of the dielectric165with an etchant which selectively removes dielectric material, but does not remove the material of the gate metal155and source/drain metals150. Alternatively, the gate metal155and drain/source metal150may be protected by a mask while the top surface of the dielectric165is etched.

Another method to raise the gate metal155and source/drain metal150above the top surface of the dielectric165may include planarizing the dielectric165, a gate metal155and source/drain metal150, and building up the gate metal155and source/drain metal150to stand slightly above the top surface of the dielectric165. Such a build-up process may include masking the surrounding dielectric165to leave the gate metal155and source/drain metal150exposed, and depositing or growing a suitable conductive material on the exposed gate metal155and source/drain metal150.

Referring toFIG. 2, a second device200is also formed using similar Fabrication methods appropriate for producing the second device200. However, the second device200may have a crystal orientation in its active region different from the first device100. This is possible due to the separate fabrication processes of each of the devices, prior to inverting the second device200bonding. Accordingly, a second Si substrate205having a crystal orientation of [100] has a second SiO2layer207formed thereon. The second SiO2layer207has a second Si layer220formed on top. The second Si layer220is formed to include an active region of the second device200and is arranged over the second Si layer207.

Trenches are etched into the second Si layer207and filled with an insulator such as an oxide using any of the methods well known in the art for forming and filling a trench to create shallow trench isolations210. Source/drain regions215are formed on each side of an active region225. The source/drain regions215of the second device200are formed by any of the methods well known in the art for forming source/drain regions215. A portion of the N-well212lies between the shallow trench isolation210and the source/drain regions215.

After the source/drain regions215are formed in the second device200, a gate oxide225is formed on top of the active region of the second Si layer220. The gate oxide225may be formed by any of the techniques well known in the art for forming a gate oxide. After the gate oxide225is formed, a polysilicon gate230is formed over the gate oxide225. A CA contact240is formed on the poly gate230and a metal (M1)255is formed on the CA contact240. Source/drain M1contacts235and245are formed on the source/drains215. Source/drain metals260and250are formed thereon, respectively.

A dielectric265is formed over the top of the first device. As discussed with the first device,100, the second device is formed so that the gate metal255and source/drain metal250protrude slightly above the dielectric265surface. For example, the top of the dielectric is planarized and then etched to leave the tops of the gate metal255and a source/drain metal250slightly protruding above the surrounding surface, depending on the connection.

Referring toFIG. 3, once the first device100and the second device200are formed, the second device200is inverted and bonded to the top of the first device100with a bonding layer305. The bonding layer305attaches a top of the first device100to the top of the second device200. The first and second devices,100and200, are aligned with one another so that the first source/drain metal of each device150and250align with one another to make electrical contact there between. Also, the gate metal,155and255, of each device is also aligned and put in electrical contact with one another. The first and second devices,100and200, may be fabricated and bonded in virtually any appropriate manner to align virtually any metal contact of the first device100with a metal contact of the second device200as desired.

The bonding layer305bonds the second device200to the first device100using methods and materials well known in the art for bonding one device to another. The bonding layer305may include any insulating substance capable of bonding a first semiconductor device to a second semiconductor device, such as, for example, a nanocleave method. Other examples of bonding layers include contact adhesive and expoxies. Further examples of bonding layers include certain oxides used for bonding purposes well know in the art.

The bonding layer305should be applied so as not to interfere with the electrical connection or gate interconnect310between the two gate metals155and255and the electrical connection or source/drain interconnect315between the two source/drain metals150and250. This may include applying the bonding layer305so it is clear of the gate metals155and255and the source/drain metals150and250. Where appropriate, the bonding layer may also be applied in a viscous state so that it flows from the gate metal,155and255, and source/drain metal,150and250, surfaces when the surfaces make contact with one another.

As an alternative to a bonding layer, the first device100may be clamped to the second device200with an external clamping force. The external clamping force may obviate the need to use a bonding layer between the two devices (also represented as reference numeral305).

After the first device100and the second device200are bonded to one another, metal plugs may be formed to the interconnections,310and315, the first and second devices,100and200. For example, the source/drain interconnection315may be connected to a metal plug. Similarly the source/drain of the lower device may be connected to a voltage source Vss. The gate interconnection310may be connected to a metal plug to receive a voltage input Vin. The separate source/drain metals,160and260may be separately connected to respective wire or plugs.

In operation, the inverted multilayer device300ofFIG. 3, where the first device100is a pFET and the second device200is an nFET, is configured to function as a CMOS inverter. The CMOS inverter is configured to occupy half the surface area on an IC chip due to its inverted multilayer structure. The first and second devices,100and200, of the CMOS device300are internally connected to one another with a minimum number of metal wires due to the inverted position of the second device, thereby simplifying the input and output leads to the CMOS device300. Additionally, because the second device200is inverted or flipped over, the respective substrates,105and205, of each device are exposed thereby enhancing the heat dissipation from each device. Also, in this manner, since the first and second devices100and200are formed separately, and then combined, it is possible to obtain a stacked structure with an inverted layer or device having a different crystal orientation in its active region relative to the other layer or device.

In other words,FIG. 3shows an embodiment of an inverted multilayer device in accordance with the invention, and may equally represent a fabrication process or an apparatus or device. The multilayer device300includes a first device100, for example, a pFET, onto which a second device200, for example, an nFET, is bonded in an inverted position. The first device100and the second device200each have a different crystal orientation from one another in the active region of the multilayer device300. Thus, the method and apparatus includes forming an integrated circuit having two semiconductor layers bonded together, where a semiconductor layer is rotated 180 degrees with respect to the other semiconductor layer, and each semiconductor layer has a crystal orientation different from the other. Rotating and bonding the semiconductor layers improves the connectability and heat transfer properties of the final structure.

Other advantages of the inverted multilayer SOI device include a reduction of about 50% of the area needed to create a circuit and using different crystal orientations for different devices. Additionally, where inverted multilayer devices are symmetrical, photolithography masks may be shared.

While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.