Methods for fabricating transistors including one or more circular trenches

A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench.

BACKGROUND

During the past few decades, there has been an increasing interest in semiconductor devices, such as power metal oxide semiconductor field effective transistors (MOSFETs) used in various applications. The power MOSFET may usually have a polysilicon layer. The polysilicon layer can be used, for example, as a gate electrode or gate runner of the power MOSFET.

The power MOSFET may have two structures, e.g., a vertical diffused MOSFET (VDMOS) and a trench MOSFET in different applications. The VDMOS became available in mid-1970 due to the availability of planar technology. By late 1980, the trench MOSFET started to penetrate power MOSFET markets utilizing DRAM trench technology, which has improved Specific On Resistance (RDSON). However, the blockage voltage or breakdown voltage of trench MOSFET may be limited to low voltage (<600 V) due to more curvatures and stress of trench MOSFET structures. Also, the electrical field density tends to be higher in trench MOSFET due to positive curvature diode doping profiles, which may reduce the breakdown voltage. Besides breakdown issues, the threshold voltage and RDSON may be limited and cannot be easily further improved with the updated new and scale down semiconductor technologies.

SUMMARY

An embodiment of the present disclosure relates to a transistor. The transistor may include an epitaxial layer and at least one trench having a circular cross-section including a trench surface defined by said epitaxial layer, a gate oxide disposed over said trench surface, and a gate conductor deposited within said trench.

Another embodiment of the present disclosure relates to a power conversion system. The power conversion system may include at least one switch, wherein the switch comprises a transistor. The transistor may include an epitaxial layer and at least one trench having a circular cross-section, wherein the trench includes a trench surface defined by the epitaxial layer, a gate oxide disposed over the trench surface, and a gate conductor deposited within the trench.

A further embodiment of the present disclosure relates to a method of fabricating a transistor. The method may include growing an epitaxial layer on a substrate, depositing an oxide on the epitaxial layer, coating a photo resist over the oxide and patterning the photo resist. The method may also include etching the oxide and epitaxial layer to form at least one circular trench, wherein the trench surfaces may be defined by the epitaxial layer, growing a second oxide layer on the trench surfaces, and forming a gate conductor within the at least one trench.

DETAILED DESCRIPTION

In the following detailed description presented herein, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processes, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “coating,” “depositing,” “etching,” “fabricating,” “siliciding,” “implanting,” “metalizing,” “titanizing” or the like, refer to actions and processes of semiconductor device fabrication.

It is understood that the figures are not drawn to scale, and only portions of the structures depicted, as well as the various layers that form those structures, are shown.

Furthermore, other fabrication processes and steps may be performed along with the processes and steps discussed herein; that is, there may be a number of processes and steps before, in between and/or after the steps shown and described herein. Embodiments described herein can be implemented in conjunction with these other processes and steps without significantly perturbing them. Generally speaking, the various embodiments of the present invention can replace portions of a conventional process without significantly affecting peripheral processes and steps.

A conventional trench MOSFET (metal oxide semiconductor field effective transistor) mask may include square opening structures, a top view of which is illustrated inFIG. 1aand in the cross-sectional view ofFIG. 1b. For example, the trench MOSFET10may include a trench12etched into an epitaxial layer14at a given depth. A gate oxide16and polycrystalline silicon18may be used to form the gate electrodes. The mesa area between trench matrixes may have square shaped plateaus on which N+ source20and P+ contact regions22are deposited or implanted. Interlayer dielectric material, metal and passivation layers may be deposited and patterned for end users.

In one embodiment, the present disclosure provides a MOSFET including circular trench openings forming the gate trenches, wherein several trench MOSFETs may share one P+ contact opening.FIG. 2illustrates a top view of an embodiment of a trench MOSFET200including four trenches, wherein the trenches212share one P+ contact opening222. More or less trenches may be present relative to a single P+ contact222. In some embodiments, the number of trench transistors and the number of contacts may be present in the range of 1:1 to 6:1, including 4:1, or 5:1, depending on the uninterrupted switching (UIS)/avalanche current requirements. Regions226of the upper portion220of the MOSFET200may be implanted with N+ type dopants, which may partially or completely surround the P+ contact openings222and/or trenches212. The trenches212are circular in cross-section, meaning that upon viewing the trenches212from the top or the upper portion220, the trenches appear circular in nature.

FIGS. 3 through 8illustrate one embodiment of a fabrication sequence of a circular trench metal oxide semiconductor field effect transistor (MOSFET) in accordance with one embodiment of this disclosure. The fabrication sequence of the circular trench MOSFET inFIGS. 3 through 8is for illustrative purposes and is not intended to be limiting.

InFIG. 3, an epitaxial layer304may be grown on a semiconductor substrate302, e.g., an N-type heavily doped (N+) substrate, of the MOSFET300. The N-type doping may include, for example arsenic or red phosphorous. A relatively hard mask oxide306may be grown on the epitaxial layer304. The hard mask oxide may include, for example, thermal SiO2or Low Temperature Oxide. The relatively hard mask oxide may be harder than the hardness of the photo resist. The hard oxide mask306may be patterned, wherein a photo resist308may then be coated over the hard oxide mask306and selectively cured or removed using photo lithography. The oxide mask306and the epitaxial layer304may then be etched, removing a portion of the oxide mask306and epitaxial layer304to define or form trenches312within the epitaxial layer304and the oxide layer306. The cross-sectional area of each trench may be circular in shape. Therefore, upon viewing the trenches from the “top” of the MOSFET300, the trenches define a circular geometry. Etching may be performed using processes such as lithography or plasma etching. In addition, the chemical plasma used to etch the oxide mask306may be different from the chemical plasma for the epitaxial layer304. After etching, the photo resist308may then be stripped away and the wafer300may be cleaned and dried.

As illustrated inFIG. 4, a sacrificial oxide414may be grown in the inter-surfaces of the oxide mask406and silicon mesa as well as the side walls of trenches412. In some embodiments, the sacrificial oxide may include silicon oxide. The sacrificial oxide414may then be etched, for example, by buffered oxide etchant (BOE). InFIG. 5, gate oxide516may be grown in the trenches512on the trench surfaces defined by the epitaxial layer. In some examples, the gate oxide516may be thermally grown after sacrificial oxide is etched. A gate conductor material such as, for example, polysilicon, tungsten, germanium, gallium nitride (GaN), or silicon carbide (SiC), may be deposited forming a gate conductor518within the trench. The gate conductor518may be etched to the end point of the mesa oxide516, that is, etching off the gat materials may be ended once the top surface of the mesa oxide is reached. Additional etching of the gate conductor518may occur over time forming a recess in the trench512.

InFIG. 6, a P-well624may be formed around the trenches612, wherein the configuration of the P-well may depend on the termination process design. The P-well may be formed by implanting one or more P-type dopants, such as boron, and driving the P-type dopants into the epitaxial layer604to a given depth or range of depths under the surface of the epitaxial layer604. This may be followed by annealing, which may be facilitated in a furnace. A patterned photo resist layer may be applied and N+ type dopants are implanted according to the patterned photo resist into the epitaxial layer to form an N+ layer626, followed by annealing. The N+ type dopant may include, for example, arsenic. The N+ layer626may be formed over the P-well624near the upper surface of the epitaxial layer604. The photo resist may then be then stripped and low temperature oxide (LTO) and boron-phosphorus-silicate glass (BPSG) may be deposited to form a layer628over the N+ doped portion626of the epitaxial layer604. In one embodiment, the BPSG may be deposited after depositing the LTO. The low temperature oxide may be, for example, silicon oxide. The BGSP/LTO surface may be patterned and P-type dopants, such as boron, may be implanted into epitaxial layer604and annealed forming a P+ contacts630.

InFIG. 7 through 9illustrate front bi-metal system layers. InFIG. 7, the front bi-metal system layers including W-plug, first metal, interlayer dielectric (ILD) and top metal deposited over the low temperature oxide and boron-phosphorus-silicate glass728are schematically illustrated. The bi-metal system layers may include a first metal for forming gate electrodes, which may include gate runners740a,740b,740c,740dconnecting the gate conductors718to gate pads (not illustrated). The bi-metal system layers also include a top metal for connecting the P+ contacts730to a source pad (not illustrated). A drain metal746may also be applied to a surface of the substrate702opposing the epitaxial layer704. Non-limiting examples of drain metals may include titanium, nickel, gold or alloys thereof.

FIG. 8aandFIG. 8billustrate cross-sectional views of embodiments of a MOSFET800taken across line C-C ofFIG. 7. InFIG. 8atungsten plug technology may be used to deposit tungsten and chemical mechanical polish (CMP) tungsten to form plugs850a,850b,851connecting the gate conductor818to the gate runners842a,842band the P+ contact832to the source pad852. That is, contact holes may be etched and tungsten may then be deposited in the holes forming the tungsten plugs. This may be followed with tungsten chemical-mechanical planarization wherein abrasive slurry is provided and a polishing pad is used to remove excess tungsten. The first metal for the gate runners842a,842bis then deposited.

InFIG. 8btungsten plug technology may be used to deposit tungsten and chemical mechanical polish (CMP) tungsten to form plugs850a,850b,850cconnecting the gate conductor818to the gate runners842a,842band the P+ contact832to the gate runner842c. The gate runner842cmay, in turn, be connected the source pad852via plug851also formed using tungsten plug technology.

After depositing the first metal, in the embodiments ofFIGS. 8aand8b, an interlayer dielectric material854may be deposited and patterned. The top metal layer may then be deposited and patterned forming the source electrode or source pad852. Finally, a passivation layer may be deposited and patterned on the gate source areas, ending the front side process. Then the wafers may be ground to certain thickness in order to reduce RDSON and improve heat dissipation. After that, back metal layers may be sputtered, which may complete the fabrication process for the trench MOSFET.

FIGS. 9aand9billustrate cross-sectional views of embodiments of a MOSFET900near the gate pad region taken along line C-C ofFIG. 7. Again, as illustrated inFIG. 9a, tungsten plug technology, as described above, may be used to deposit tungsten plugs950a,950bconnecting the gate conductor918to the gate runners942a,942b. In addition, tungsten plug technology may be used to deposit tungsten plug951aand connecting the P+ contact932to the source pad952. This may be followed with tungsten chemical-mechanical planarization. The first metal for the gate runners942a,942bmay then be deposited. An additional tungsten plug may be deposited951bconnecting the gate runners942ato the gate pad956. The gate runners and gate pads may be partially or completely interconnected.

As illustrated inFIG. 9b, tungsten plug technology, as described above, may be used to deposit tungsten plugs950a,950bconnecting the gate conductor918to the gate runners942a,942band tungsten plug950cconnecting the P+ contact932to gate runner942c. This may be followed with tungsten chemical-mechanical planarization. The first metal for the gate runners942a,942b,942cmay then be deposited. An additional tungsten plug951amay be deposited connecting the gate runner942cwith the source pad952and a tungsten plug951bmay be deposited connecting gate runner942ato the gate pad956. The gate runners942a,942band gate pads may be partially or completely interconnected.

After depositing the first metal, an interlayer dielectric material954may be deposited and patterned. A gate pad956may then be deposited and a top metal layer may be deposited and patterned forming the source electrode or source pad952. Finally, a passivation layer may be deposited and patterned. The passivation layer may include, for example, low temperature oxide, nitride or combinations thereof. Patterning may depend upon application to end the front side processes. The wafers may then be ground to certain thickness in order to reduce RDSON and improve heat dissipation. After, the back metal layers may be sputtered completing the fabrication process for the trench MOSFET.

FIGS. 10 through 15billustrate cross-sectional perspective views of a fabrication sequence of a circular trench metal oxide semiconductor field effect transistor (MOSFET) in accordance with another embodiment. The fabrication sequence of the circular trench MOSFET inFIGS. 10 through 15bis for illustrative purposes and is not intended to be limiting.

InFIG. 10, a relatively thick hard mask oxide1006may be grown onto an epitaxial layer1004formed over an N+ doped substrate wafer1002. The mask oxide thickness may be 5,000 Angstroms or greater. Again, the N+ dopant may include, for example, arsenic or red phosphorous. A photo resist1008may be coated on the mask oxide1006and patterned with a trench mask. The mask oxide1006and epitaxial layer1004may be etched forming circular trenches1012therein. Different chemical plasmas may be used to etch each layer. The photo resist may then be stripped and the wafer1000may be cleaned and dried.

InFIG. 11, a sacrificial oxide layer may be grown and etched using buffered oxide etchant, which may remove surface defects. A portion of the relatively thick hard oxide mask1106may remain at the top of the mesa area to provide electrical isolation between the gate conductors and epitaxial layer. Gate oxide1114may then be thermally grown within the trenches. Gate conductor material, such as polysilicon, may be deposited and etched back in the trenches1112forming gate conductors1118.

A P-well1124may be formed around the trenches1112, the configuration depending on the application. The P-well may be formed by implanting one or more P-type dopants, such as boron, and driving the P-type dopants into the epitaxial layer1104to a given depth under the surface of the epitaxial layer1104. This may be followed by annealing, which may be facilitated in a furnace. A patterned photo resist layer may be applied and N+ type dopants may be implanted according to the patterned photo resist into the epitaxial layer to form an N+ layer1126followed by annealing. A non-limiting example of an N+ type dopant may include arsenic. The N+ layer may include arsenic and may be formed over the P-well1124near the upper surface of the epitaxial layer1104.

InFIG. 12, a second gate conductor material, such as polysilicon, may be deposited, patterned by lithography and etched with plasma to form a runner1242over the mesa area connecting the gate conductors1218together. The first gate conductor material (forming the gate conductor) and the second gate conductor material (forming the runners) may be the same or similar materials in some embodiments. In other embodiments, the first and second gate conductor materials may be different. After, P-Well, N+Source, and contact implant and/or anneal may be performed. The low temperature oxide (LTO) and boron phosphorus silicate glass (BPSG) may be deposited and patterned for single metal sputtering and patterning including W-Plug, which is illustrated schematically.

FIG. 13, which is a cross-section ofFIG. 12taken at the dotted line D-D, illustrates that low temperature oxide (LTO) and boron-phosphorus-silicate glass (BPSG) may be deposited to form a layer1328over the N+ doped portion1326of the epitaxial layer1304. In some embodiments, the LTO may be deposited first and then the BPSG may be deposited over the LTO. The low temperature oxide may be, for example, silicon oxide. Then P-type dopants, such as boron, may be implanted into the oxide mask1306and the epitaxial layer1304and annealed to form a P+ contact1332. Such arrangement may lead to improved breakdown voltage. After contact patterning, tungsten plug technology may be used to deposit tungsten plugs1351, which may be followed by chemical mechanical planarization. A source pad may then be deposited1352over the low temperature oxide and boro-phospho-silicate glass1328.

FIG. 14illustrates a cross-sectional view of the MOSFET near the gate pad region taken along dotted line D-D ofFIG. 12. As illustrated, an additional tungsten plug1450may be provided to connect the gate conductor1418to the gate pad1456through gate runners formed by the second gate conductor material1442. In addition, tungsten plug1451may be provided to connect the P+ contact1432with the source pad1452. The various gate conductors1418on the MOSFET1400may be wholly or partially interconnected. Front metal layers may be deposited and patterned. In one embodiment, a first metal for the gate pad1456and a second metal for the source pad1452. A passivation layer may be deposited over the source pad and gate pad and patterned followed by wafer grinding and back metallization may be performed to form the drain1440.

FIG. 15aillustrates a top view the MOSFET1500after the tungsten plug addition step. The tungsten plugs1550for the gate and the tungsten plugs for the source1551are illustrated and a number of gate runners1540are provided. The outlined portions illustrate the gate pad peripheral1556and the source pad peripheral1552locations after metallization patterning.FIG. 15billustrates a top view of the MOSFET1500after metallization patterning of the source pad1552and the gate pad1556.FIG. 15cillustrates the conventional source pad1552′ and gate pad1556′ technology. As can be seen, inFIG. 15c, a conventional gate pad1556′ requires the addition of gate pad runners1556a′ and1556b′. The embodiment described inFIGS. 10-15bmay eliminate the need for such runners, cutting down on the total amount of space the gate pad1556requires and the amount of material necessary to provide the gate pad1556.

In some embodiments, the circular trench MOSFETs may provide for easier incorporation of trench bottom oxides. In other embodiments, the circular trench MOSFETs with high electron mobility transistors (HEMT) may provide easier fabrication with compounds such as SiC and GaN.

Circular trench MOSFETs may also provide the following additional benefits. Unlike nano-wire or multi-pillar vertical transistors, the circular boundaries may provide a uniform and outwardly irradiative electrical field line density, which does not have localized electrical field crowding that may trigger premature voltage breakdown. The circular boundaries may also provide less stress along the side walls and trench bottom corners reducing localized stresses that may also trigger premature voltage breakdown. Thus, the breakdown voltage may be higher in circular trench MOSFETs. In addition, with proper reduced surface (RESURF) termination and negative curve doping (NCD), the breakdown voltage may go up to 1,000 V or more.

Another potential benefit includes the elimination of gate runners around the outside of the peripheral of core chips/dies present in conventional trench MOSFET design. The gate pad may be connected directly onto the gate through gate electrodes formed, for example, of metal or polycrystalline silicon. The direct contact of the gate may provide higher packing density to provide more chips/dies out per wafer.

A further potential benefit includes lower threshold voltages compared to conventional square trench MOSFET as the electrical field lines of the circular trench MOSFET radiate outward from the gate cylinder center. The RDSON may be reduced further due to lower threshold voltage.

In addition, the relatively wider trench openings and circular shape may lead to etching the trench depth in a uniform manner relatively easily with little plasma loading effect due to wider trench openings and circular shape. The wider trench openings and circular shape may also lead to easily oxidizing in a uniform manner the trench bottom forming trench bottom oxide (TBO). The wider trench openings and circular shape may further lead to use of all semiconductor materials such as Si, Ge, GaN, SiC and so on to make the trench MOSFET or high electron mobility transistor (HEMT) relatively easily.

The fabrication sequence disclosed inFIGS. 3 through 8may utilize an extra metal mask and interlayer dielectric material for the due metal system compared to other systems. In addition, the fabrication sequence disclosed inFIGS. 9 through 13may require an extra polysilicon mask compared to other systems. It is possible that these additional layers may increase costs; however, the increase in cost may be compensated by the relatively higher voltage breakdown capability and relatively lower RDSON performance.

FIG. 16illustrates a diagram of a power conversion system1600in accordance with one embodiment. The power conversion system1600can convert an input voltage to an output voltage. The power conversion system1600can be direct current to direct current (DC-DC) converter, an alternating current to direct current (AC-DC) converter, or a DC-AC converter. The power conversion system1600can include one or more switches1610. In one embodiment, the switch1610may be, but is not limited to, a circular trench MOSFET (e.g.,800inFIG. 8or1300inFIG. 13) fabricated by the manufacturing process and steps shown inFIGS. 3 through 9orFIGS. 10 through 14.

In one embodiment, as illustrated inFIG. 17, the present disclosure provides an insulated gate bipolar transistor (IGBT) with circular trenches. The transistor1700may be formed utilizing either embodiment described above with respect toFIGS. 3 through 9and10through14, except that the N+ doped substrate may be exchanged with a P+ doped substrate1702. Referring again toFIG. 16, the IGBT may be used as switch1610in a power conversion system1600. In some embodiments, the IGBT may be utilized in smart grid applications, wherein the electrical network may be monitored by overlying the electrical network with two-way communication capabilities. Such capabilities may provide sensing, measurement and control of devices operably coupled to the network.

As alluded to above, a method of fabricating a transistor may be provided as illustrated inFIG. 18a. The method may generally include growing an epitaxial layer on a substrate1802, depositing an oxide, such as the hard oxide, on the epitaxial layer1804, patterning the oxide1806, etching the oxide and epitaxial layer to form at least one circular trench1808, wherein the trench surfaces are defined by the epitaxial layer. The method may also include growing an oxide layer on the trench surfaces1810and forming a gate conductor within the at least one trench1812.

P-well formation1814may follow the formation of the gate conductors as illustrated inFIGS. 18band18c. In some embodiments, prior to P-well formation, the substrate may be patterned. P-well formation may then occur via implantation and driving of the P-well dopant into the epitaxial layer. After P-well formation1814, the N+ layer may then be formed1816. In some embodiments, prior to forming the N+ layer the surface of the substrate may be patterned and after formation of the N+ layer, the photoresist may be stripped.

In some embodiments, BPSG/LTO may then be deposited over the epitaxial layer1818and patterned. The BPSG/LTO may be patterned and the oxide etched1820to provide for contacts. Tungsten plugs may optionally be provided. Metalization layers may then be sputtered1822over the BPSG/LTO. As illustrated inFIG. 18c, the passivation of the metalized layer may be provided1824, which may in some embodiments, end the front side process. The wafer may then be ground1826, which may reduce RDSON and improve heat dissipation. After that, the back metal layers of the substrate may be sputtered1828. Thus, the process for fabricating a trench MOSFET may be completed.

Another embodiment of a method of fabricating a transistor may be provided as illustrated inFIGS. 19athrough19c. As illustrated inFIG. 19a, the method may generally include growing an epitaxial layer on a substrate1902, depositing an oxide, such as the hard oxide, on the epitaxial layer1904, patterning the oxide1906, etching the oxide and epitaxial layer to form at least one circular trench1908, wherein the trench surfaces are defined by the epitaxial layer. The method may also include growing an oxide layer on the trench surfaces1910and forming a gate conductor within the at least one trench1912.

P-well formation1914may follow the formation of the gate conductors as illustrated inFIGS. 19band19c. In some embodiments, prior to P-well formation, the substrate may be patterned. P-well formation may then occur via implantation and driving of the P-well dopant into the epitaxial layer. After P-well formation1914, the N+ layer may then be formed1916. In some embodiments, prior to forming the N+ layer the surface of the substrate may be patterned and after formation of the N+ layer, the photoresist may be stripped.

Prior to depositing BPSG/LTO over the epitaxial layer1920, a second gate conductor material, such as polysilicon, may be deposited and patterned1918. After the BPSG/LTO is deposited1920and patterned, the oxide may be etched1922to provide for contacts. Tungsten plugs may optionally be provided. Metalization layers may then be sputtered1924over the BPSG/LTO. As illustrated inFIG. 19c, the passivation of the metalized layer may be provided1926, which may in some embodiments, end the front side process. The wafer may then be ground1928, which may reduce RDSON and improve heat dissipation. After that, the back metal layers of the substrate may be sputtered1930. Thus, the process for fabricating a trench MOSFET may be completed.

The foregoing description of several methods and embodiments has been presented for purposes of illustration. It is not intended to be exhaustive or to limit the claims to the precise steps and/or forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be defined by the claims appended hereto.