Semiconductor device with stripe-shaped trench gate structures, transistor mesas and diode mesas

A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction.

PRIORITY CLAIM

This application claims priority to German Patent Application No. 10 2014 119 465.9 filed on 22 Dec. 2014, the content of said application incorporated herein by reference in its entirety.

BACKGROUND

Power semiconductor switches that are able to withstand a blocking voltage of several hundred Volts at high current rating are typically implemented as vertical transistors with a gate electrode formed in trenches in a semiconductor body, wherein the semiconductor body is based on a semiconducting material such as silicon (Si) or silicon carbide (SiC), by way of example.

It is desirable to improve the reliability of power semiconductor devices such as power semiconductor switches.

SUMMARY

According to an embodiment a semiconductor device includes stripe-shaped trench gate structures extending in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions forming first pn junctions with a drift structure and second pn junctions with source zones, respectively. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas include at least portions of diode regions that form third pn junctions with the drift structure and that directly adjoin two neighboring trench gate structures, respectively. The transistor and diode mesas alternate at least along the first horizontal direction.

According to another embodiment a semiconductor device includes stripe-shaped trench gate structures in a semiconductor body from silicon carbide of a 4H polytype. The semiconductor body has a staggered first surface with first surface sections parallel to a crystal plane and second surface sections tilted to the first surface sections. The trench gate structures extend along a first horizontal direction orthogonal to steps formed by edges between the first and second surface sections. Transistor mesas between neighboring trench gate structures include body regions forming first pn junctions with a drift structure and second pn junctions with source zones, respectively. Diode mesas include at least portions of diode regions that form third pn junctions with the drift structure and that directly adjoin two neighboring trench gate structures, respectively. The transistor and diode mesas alternate at least along the first horizontal direction.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. Other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. The present invention may include such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appending claims.

The drawings are not to scale and are for illustrative purposes only. For clarity, the same or similar elements have been designated by corresponding references in the different drawings if not stated otherwise.

The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may be provided between the electrically coupled elements, for example elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.

FIGS. 1A to 1Drefer to a semiconductor device500including transistor cells TC. The semiconductor device500may be or may include an IGFET (insulated gate field effect transistor), for example an MOSFET (metal oxide semiconductor FET) in the usual meaning including FETs with metal gates as well as FETs with non-metal gates, an IGBT (insulated gate bipolar transistor), or an MCD (MOS controlled diode), by way of example.

The semiconductor device500is based on a semiconductor body100from crystalline semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs) or any other AIIIBVsemiconductor. According to an embodiment, the semiconductor body100is made of a single crystalline semiconductor material having a band gap of 2.0 eV or higher such as gallium nitride (GaN) or silicon carbide (SiC), for example 2H—SiC (SiC of the 2H polytype), 6H—SiC or 15R—SiC. According to an embodiment, the semiconductor material has a hexagonal crystal structure, e.g., silicon carbide of the 4H polytype (4H—SiC).

At a front side the semiconductor body100has a first surface101, which may include approximately coplanar surface sections or which may include staggered, parallel surface sections tilted to a mean surface plane, respectively. On the back, an opposite second surface102may extend parallel to the coplanar surface sections of the first surface101, parallel or tilted to the mean surface plane or may include staggered, parallel surface sections parallel to surface sections of the first surface101. A distance between the first surface101at the front side and the second surface102on the back is selected to achieve a blocking voltage the semiconductor device is specified for and may be in the range of several hundred nm to several hundred μm. The normal to the first surface101defines a vertical direction. Directions parallel to the first surface101are horizontal directions.

The transistor cells TC are formed along stripe-shaped trench gate structures150, which longitudinal axes extend along a first horizontal direction, and which extend along the vertical direction from the first surface101into the semiconductor body100. The trench gate structures150may be equally spaced and may form a regular pattern, wherein a pitch (center-to-center distance) of the trench gate structures may be in a range from 1 μm to 10 μm, e.g., from 2 μm to 5 μm.

The trench gate structures150include a conductive gate electrode155which may include or consist of a heavily doped polycrystalline silicon layer or a metal-containing layer. The trench gate structures150further include a gate dielectric151separating the gate electrode155from the semiconductor body100. The gate dielectric151capacitively couples the gate electrode155to the body zones115and may include or consist of a semiconductor dielectric, for example thermally grown or deposited semiconductor oxide, e.g., silicon oxide, a semiconductor nitride, for example deposited or thermally grown silicon nitride, a semiconductor oxynitride, for example silicon oxynitride, or any combination thereof.

Mesa portions of the semiconductor body100between neighboring trench gate structures150form transistor mesas170that include semiconducting portions of the transistor cells TC as well as diode mesas180that may include at least portions of a body diode.

The transistor mesas170include source zones110that are oriented to the front side and that may directly adjoin the first surface101. The source zones110directly adjoin both neighboring trench gate structures150on opposite sides of the concerned transistor mesa170. For example, each transistor mesa170includes two source zones110, each of them directly adjoining one of the neighboring trench gate structures150and separated from each other by a contact structure or a p-doped region, which may be connected to the body zone115. According to another embodiment, each source zone110may extend from one of the trench gate structures150adjoining the concerned transistor mesa170to the other, opposite trench gate structure150.

The transistor mesas170further include body zones115that separate the source zones110from a drift structure120, wherein the body zones115form first pn junctions pn1with the drift structure120and second pn junctions pn2with the source zones110. Each body zone115extends from one of the trench gate structures150adjoining the concerned transistor mesa170to the other, opposite trench gate structure150. Both the first pn junctions pn1and the second pn junction pn2may extend over the whole width of the transistor mesa170between the two trench gate structures150sandwiching the concerned transistor mesa170. Both the source zones110and the body zones115are electrically connected to a first load electrode310at the front side.

The diode mesas180include at least portions of diode regions116that form third pn junctions pn3with the drift structure120and that are electrically connected or coupled to the first load electrode310. The diode region116of a diode mesa180extends from one of the neighboring trench gate structures150to the opposite one. The diode regions116may include portions outside the semiconductor mesas formed between neighboring trench gate structures150, wherein a vertical extension of the diode regions116is greater than a vertical extension of the trench gate structures150.

As illustrated inFIGS. 1B to 1D, the diode regions116may vertically overlap with the trench gate structures150such that portions of the diode regions116are formed in the vertical projection of the trench gate structures150but spaced from the transistor mesas170along the horizontal direction. A distance between opposing edges of neighboring diode regions116may be in a range from 2 μm to 3 μm, by way of example.

The transistor mesas170and the diode mesas180alternate along the first horizontal direction or along both the first horizontal direction and the second horizontal direction, which is orthogonal to the first horizontal direction, wherein neighboring transistor and diode mesas170,180directly adjoin to each other along the first horizontal direction and are separated from each other by intermediate trench gate structures150along the second horizontal direction.

The source zones110and at least portions of the diode regions116may result from complementary, masked implants using complementary implant masks. Since the trench gate structures150separate the transistor and diode mesas170,180along the second horizontal direction, an alignment between the two implant masks is less critical along the second horizontal direction and the cell pitch along the second horizontal direction can be reduced.

According to another embodiment, a first implant for forming the source zones110may be unmasked, i.e., effective in both the transistor mesas170and the diode mesas180and a second, masked implant locally counterdopes the first implant in the diode mesas180. Again, the alignment of the implant mask for the second implant is less critical along the second horizontal direction such that the cell pitch along the second horizontal direction can be reduced.

The drift structure120is oriented to the back, may directly adjoin the second surface102and may be electrically connected or coupled to a second load electrode320through an ohmic contact or a further pn junction. The drift structure120may include a lightly doped drift zone121that may form the first and third pn junctions pn1, pn3as well as a heavily doped contact layer129between the drift zone121and the second surface102. The net dopant concentration in the drift zone121may be in a range from 1E14 cm−3to 1E16 cm−3in case the semiconductor body100is formed from silicon carbide.

A mean dopant concentration in the contact layer129is sufficiently high to ensure an ohmic contact with the second load electrode320that directly adjoins the second surface102. In case the semiconductor device500is a semiconductor diode or an IGFET, the contact layer129has the same conductivity type as the drift zone121. In case the semiconductor device500is an IGBT, the contact layer129has the complementary conductivity type of the drift zone121or includes zones of the complementary conductivity type.

Each of the first and second load electrodes310,320may consist of or contain, as main constituent(s), aluminum (Al), copper (Cu), or alloys of aluminum or copper such as AlSi, AlCu or AlSiCu. According to other embodiments, at least one of the first and second load electrodes310,320may contain, as main constituent(s), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), Vanadium (V), silver (Ag), gold (Au), tin (Sn), platinum (Pt), and/or palladium (Pd). One of the first and second load electrodes310,320or both may include two or more sub-layers, wherein each sub-layer contains one or more of Ni, Ti, V, Ag, Au, W, Sn, Pt, and Pd as main constituent(s), e.g., a silicide, a nitride and/or an alloy.

The first load electrode310may form or may be electrically connected or coupled to a first load terminal L1, which may be an anode terminal of an MCD, a source terminal of an IGFET or an emitter terminal of an IGBT. The second load electrode320may form or may be electrically connected or coupled to a second load terminal L2, which may be a cathode terminal of an MCD, a drain terminal of an IGFET or a collector terminal of an IGBT.

According to an embodiment, the transistor cells TC are n-channel FET cells with p-doped body regions115and n-doped source zones110, wherein the diode regions116are p-doped and the drift zone121is n-doped. According to another embodiment, the transistor cells TC are p-channel FET cells with n-doped body regions115and p-doped source zones110, wherein the diode regions116are n-doped and the drift zone121is p-doped.

When a potential at the gate electrode155exceeds or falls below a threshold voltage of the semiconductor device500, minority charge carriers in the body zones115form inversion channels connecting the source zones110with the drift structure120, thereby turning on the semiconductor device500. In the on-state, a load current flows through the semiconductor body100approximately along the vertical direction between the first and second load electrodes310,320.

The third pn junctions pn3between the diode regions116and the drift zone121form a body diode that is conductive when the semiconductor device500is reverse biased with a negative voltage applied between the second load electrode320and the first load electrode310or under avalanche conditions. The body diode feature is useful, e.g., in applications switching inductive loads, for instance, in a half bridge circuit or in a full bridge circuit.

In the blocking state depletion zones extending from the vertical edges of the diode regions116below the trench gate structures150along the horizontal direction may completely deplete portions of the drift structure120in the vertical projection of the transistor mesas170and may shield active portions of the gate dielectric151of the transistor cells TC against the blocking voltage applied to the second load electrode320. In this way, the diode regions116reduce the electric field across the gate dielectric151such that device reliability is increased and DIBL (drain-induced barrier lowering) is reduced.

Further, the diode regions116directly adjoin the body regions115along the first horizontal direction and electrically connect the body regions115with the first load electrode310without formation of deep contacts through the source zones110to the body zones115, which formation may be a rather complex task in some semiconductor materials such as SiC and which safe alignment to the trench gate structures150may require a greater minimum pitch along the second horizontal direction.

In the on-state, minority charge carriers in the body zones115form two inversion channels on both sides of the each transistor mesa170such that in each transistor cell TC two inversion channels or MOS gated channels facilitate a unipolar current flow through the body zones115between the source zones110and the drift structure120. Compared to layouts using only one sidewall of a transistor mesa for the formation of MOS gated channels, the active channel area is increased and, as a consequence, the on-state resistance reduced.

FIGS. 2A to 2Drefer to an embodiment in which the transistor mesas170alternate with the diode mesas180exclusively along the first horizontal direction. Along the second horizontal direction the transistor mesas170of neighboring semiconductor mesas may be aligned to each other such that along the second horizontal direction the transistor mesas170are formed along lines separated by lines along which the diode mesas180are formed. According to other embodiments, the transistor mesas170in neighboring semiconductor mesas may be shifted to each other, e.g., by half a longitudinal extension of the transistor mesas170along the first horizontal direction or by any other fraction of the longitudinal extension.

The first surface101is a planar surface spanned by coplanar surface sections. For further details, reference is made to the detailed description of the semiconductor device500ofFIGS. 1A to 1D. Each of the individual features of the semiconductor device500ofFIGS. 2A to 2Dcan be combined with the further features of the semiconductor device500ofFIGS. 1A to 1D.

The first surface101of the semiconductor body100as well as at least one of the sidewalls of the trench gate structures150may coincide with regular crystal planes or may be tilted at angles between 0 degree and 45 degree with respect to crystal planes, respectively. According to an embodiment, charge carrier mobility, e.g., electron mobility in case the transistor cells TC are n-channel FET cells, is equal in both crystal planes forming the sidewalls of the trench gate structures150along the longitudinal axes.

FIG. 3Ashows the crystal planes of the hexagonal crystal of 4H—SiC. Typically, a 4H—SiC wafer may be cut in or tilted to the basal (0001) plane. For example, a 4H—SiC crystal ingot is cut and/or a top surface of a 4H—SiC wafer obtained from a 4H—SiC crystal ingot may be polished at an off-axis angle in a range from 2 degree to 8 degree with respect to the basal plane such that the top surface of the 4H—SiC wafer shows long, flat, and slightly tilted terraces between short steep steps. During step-controlled epitaxy, silicon and carbon atoms impinging on the top surface grow onto the crystal, wherein the crystal growth starts at the steps. A top surface of an epitaxial layer grown on the top surface of a 4H—SiC wafer images steps of the 4H—SiC wafer substrate.

FIG. 3Bshows a top surface of a 4H—SiC wafer501cut and/or polished at an off-axis angle α between 2 degree and 8 degree, e.g., approximately 4 degree, with respect to the (0001) basal plane. The right-hand side ofFIG. 3Bshows a top view on a unit cell of a hexagonal crystal for illustrating the orientations of the crystal planes. The flat503on the periphery of the 4H—SiC wafer501marks the <11-20> crystal direction orthogonal to the (11-20) crystal planes. The <11-20> crystal direction is orthogonal to the <0001> crystal direction.

Due to wafer cut and polishing tilted by the off-axis angle a, the top surface101z of the wafer includes long sections parallel to the <11-20> crystal direction and short sections parallel to the <0001> crystal direction as illustrated inFIG. 3C.

The steps are symmetric with respect to a mean surface plane101x, which is tilted to the <11-20> crystal direction at the off-axis angle αa. A trench150afor a trench gate structure extends from the mean surface plane101xinto the semiconductor body100and may taper with increasing distance to the top surface101zat a taper angle β with respect to the vertical direction. If the taper angle β and the off axis angle α are equal, a first sidewall104of the trench150ais parallel to the (11-20) crystal planes, whereas an opposite second sidewall105is tilted to the (11-20) crystal planes by an angular misalignment γ=α+β.

Since electron mobility strongly depends on the crystal orientation, an inversion channel formed along the second sidewall105is significantly less effective than an inversion channel formed along the first sidewalls104.

In addition, the first and second sidewalls104,105are only smooth and without steps if the horizontal direction along which they extend is perfectly parallel to the (11-20 ) crystal planes. At a slight angular misalignment between the crystal planes and the longitudinal axis of the trench150a, the first and second sidewalls104,105cut the (11-20 ) crystal planes. Then a high temperature process that precedes the formation of the gate dielectric151, e.g., a doping activation anneal or a surface smoothing treatment, may form steps compensating the deviation of the longitudinal axis of the trench150afrom the (11-20) crystal planes. Such steps may locally change the characteristics of the inversion channels and may degrade device reliability.

According to an embodiment, the semiconductor body100with trench gate structures150, transistor mesas170and diode mesas180as illustrated inFIGS. 1A to 1Dis obtained from a 4H—SiC wafer which mean surface plane101xhas an off-axis angle a with respect to the basal plane. The trench gate structures150may be formed, by way of example, along the <11-20> crystal direction perpendicular to the (11-20 ) crystal plane. Sidewalls of the trench gate structures150have an angle of 90 degree with respect to the mean surface plane101x.

As a result, one of the trench sidewalls is an (1-100) crystal plane and the other one a (−1100) crystal plane as shown inFIGS. 3D and 3E. Both sidewalls104,105of the trench150ahave identical surface properties such that both trench sidewalls104,105are identical with respect to the charge carrier mobility. Along both sidewalls104,105a current density is equal and overall current distribution more uniform. The availability of both trench sidewalls compensates the inherently reduced electron mobility at the (−1100) and the (1-100) crystal planes, which is about 20% less than along the (11-20 ) crystal planes.

FIG. 3Fshows that steps may be formed at the bottom106of the trenches150abut the smoothness of the longitudinal sidewalls104,105of the trenches150aand of the trench gate structures formed in the trenches150ais not affected by the tilt at the top surface.

The semiconductor device500ofFIGS. 4A to 4Dis a silicon carbide IGFET based on the semiconductor device500ofFIGS. 1A to 1D, wherein a first surface101of the semiconductor body100is a staggered surface with staggered first surface sections101aformed by crystal planes and second surface sections101btilted to the first surface sections101aand connecting the first surface sections101a. The longitudinal axes of the trench gate structures150run orthogonal to steps108resulting from the different orientations of the first and second surface sections101a,101bin the staggered first surface101.

According to the embodiment illustrated inFIG. 4Cthe first surface sections101amay be (0001) crystal planes, a mean surface plane101xcutting the steps108at half step height may be tilted to the <11-20> crystal direction at an off-axis angle α from 2 degree to 8 degree, and sidewalls of the transistor and diode mesas (170,180) may be (−1100) and (1-100) crystal planes.

In addition, the diode regions116include shielding portions116b, which directly adjoin the drift structure120, and contact portions116aconnecting the shielding portions116bwith the first load electrode310, respectively. A mean net dopant concentration in the contact portions116ais at least twice as high as a mean net dopant concentration in the shielding portions116b. The shielding portions116bmay include sections in a with respect to the first surface101vertical projection of the trench gate structures150but do not include portions in the vertical projection of the transistor mesas170. A distance between neighboring shielding portions116bmay be between 2 μm and 3 μm, by way of example.

The drift structure120may include current spread zones122between the body zones115and the drift zone121, wherein the current spread zones122may be sandwiched between the body zones115and the drift zone121or may be spaced from the body zones115. A mean dopant concentration in the current spread zones122is at least twice, for example at least ten times as high as the mean dopant concentration in the drift zone121. The reduced lateral ohmic resistance in the current spread zones122spreads the charge carrier flow through the body zones115along the horizontal directions such that a more uniform current distribution is achieved in the semiconductor body100even at a low dopant concentration in the drift zone121.

According to the illustrated embodiment the current spread zones122directly adjoin the body zones115and are formed between neighboring shielding portions116b. Unipolar homojunctions between the current spread zones122and the drift zone121may have a greater distance to the first surface101than the third pn junctions pn3formed between the diode regions116and the drift zone121. The current spread zones122may be formed exclusively in the horizontal projection of the adjoining diode regions116or may overlap with the shielding portions116bsuch that portions of the current spread zones122are formed in the vertical projection of the shielding portions116b. According to another embodiment, the current spread zones122may form a contiguous layer between the shielding portions116band the drift zone121.

The shielding portions116bmay be formed on top of the drift zone121in the same implant step as the contact portions116a. According to other embodiments, the shielding portions116bare formed independently from the contact portions116a, for example by using another lithographic mask.

FIGS. 5A to 5Dillustrate a semiconductor device500with the shielding portions116bformed as a layer with point-symmetric openings centered to the transistor mesas170.

FIG. 5Ashows a horizontal cross-sectional view in a plane cutting through the shielding portions116b. The shielding portions116bform a contiguous shielding layer with openings117centered to the transistor mesas170. The openings117may be point-symmetric with respect to the center of the transistor mesas170such that a width z1of the openings117orthogonal to the first horizontal direction is equal to a width z2of the openings117along the first horizontal direction. In the blocking mode depletion zones extend along all four horizontal directions into the direction of the transistor mesas170and effectively shield the active portions of the gate dielectric151. The openings117may be point-symmetric, for example squares, octagons or other regular polygons.

The horizontal cross-sectional are of the diode mesas180can be significantly reduced without reducing the shielding effect of the diode regions116and, as a consequence, the effective transistor area can be increased.

FIGS. 5B to 5Dfurther show an interlayer dielectric210sandwiched between the first load electrode310and the gate electrode155. The interlayer dielectric210dielectrically insulates the first load electrode310from the gate electrode155and may include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass), by way of example.

FIG. 6Ashows a semiconductor device500which shielding portions116bform a contiguous shielding layer with hexagonal openings117.