Commutation delay generator for a multiphase brushless DC motor

A commutation control circuit provides a substantially periodic series of commutation signals to a conventional motor sequencer. The control circuit includes a frequency-to-current converter that receives the series of commutation signals and outputs a current that has a magnitude proportional to the average period of the series of commutation signals. The proportional current is then used to charge and/or discharge a known capacitance after a back-EMF sensor determines the appropriate starting time of a delay period. The capacitance and the proportional current are selected such that the proportional current charges the capacitance to a selected voltage level to trigger a commutation signal after the appropriate delay period.

CROSS-REFERENCE TO RELATED APPLICATIONS 
The present application is related to application Ser. No. 08/594,676, 
filed herewith, entitled "Frequency-To-Current Converter," by Giao M. 
Pham, which is incorporated herein by this reference. 
BACKGROUND 
1. Field of the Invention 
This invention relates generally to commutation circuits for electric 
motors. 
2. Description of Related Technology 
Hard disk drive systems ("hard drives") are a predominant mechanism for 
providing large volumes of low-cost, computer-accessible memory. A typical 
hard drive includes a spin motor for rotating one or more magnetic storage 
disks during data read and write operations. An electronic control and 
driving circuit is coupled between the spin motor and a host 
microprocessor interface to provide drive signals to power the motor 
windings. 
FIG. 1 is a schematic diagram of conventional motor and drive circuitry 7, 
which includes a portion of a three-phase brushless spin motor 10 
connected to a conventional commutation sequencer 18 via a motor driver 
20. For the example illustrated herein, spin motor 10 is assumed to 
include three sets of phase windings, each of which is selectively driven 
at a predetermined phase. In FIG. 1, the three sets of windings are 
represented by phase windings 12, 14, and 16, which are arranged around a 
rotor shaft (not shown) and have a common connection at a center tap 11. 
As known to those skilled in the art, sequencer 18 and a motor driver 20 
collectively operate to selectively drive pairs of phase windings 12, 14, 
and 16 to induce rotation of the rotor shaft of motor 10. Diodes D.sub.1 
-D.sub.6 protect motor and drive circuitry 7 from extreme voltages on 
nodes A, B, and C that would otherwise result due to the inductances of 
windings 12, 14, and 16. 
Referring next to FIG. 2A in conjunction with FIG. 1, traces 1, 2, and 3 
illustrate the motor torque generated when a constant current flows 
through selected pairs of phase windings 12, 14, and 16. Trace 1 shows the 
motor torque curve with respect to electrical degrees when transistors 20a 
and 20f are turned on (20b through 20e turned off), resulting in current 
flow through phase-A winding 12 and phase-C winding 16. Similarly, trace 2 
shows the motor torque curve on the common horizontal axis when 
transistors 20a and 20d are turned on, resulting in current flow through 
phase-A winding 12 and phase-B winding 14. Finally, trace 3 shows the 
motor torque curve when transistors 20d and 20e are turned on, resulting 
in current flow through phase-C winding 16 and phase-B winding 14. The 
maximum torque points occur 60 electrical degrees apart. For an eight-pole 
motor, 60 electrical degrees correspond equivalently to 15.degree. of 
mechanical rotation of the rotor shaft. 
To spin a rotor shaft of a motor continuously in one direction, the motor 
torque should be either continuously positive or continuously negative. A 
continuously positive motor torque, for example, can be provided by 
designing and controlling sequencer 18 and motor driver 20 to transfer 
current to selected pairs of windings in a predetermined and precisely 
timed sequence so that the overall torque curve of the motor is defined 
along the maximum segments connecting points a1 through a7 of FIG. 2A. The 
act of transferring current from one pair of windings to the next is 
conventionally called "commutation." 
The overall torque curve defined by the curves connecting points a1 through 
a7 results in maximum torque with the least ripple, and thus is considered 
the result of optimal commutation timing. The predetermined sequence 
required for turning on the transistors 20a through 20f, as controlled by 
sequencer 18, is as follows: 
Sequence 1: Transistors 20a and 20f are on so that current flows from node 
A through windings 12 and 16 to node C, generating torque segment a1 to 
a2; 
Sequence 2: Transistors 20a and 20d are on so that current flows from node 
A through windings 12 and 14 to node B, generating torque segment a2 to 
a3; 
Sequence 3: Transistors 20d and 20e are on so that current flows from node 
C through windings 16 and 14 to terminal B, generating torque segment a3 
to a4; 
Sequence 4: Transistors 20b and 20e are on so that current flows from node 
C through windings 16 and 12 to node A, generating torque segment a4 to 
a5; 
Sequence 5: Transistors 20b and 20c are on so that current flows from node 
B through windings 14 and 12 to node A, generating torque segment a5 to 
a6; and 
Sequence 6: Transistors 20c and 20f are on so that current flows from node 
B through windings 14 and 16 to node C, generating torque segment a6 to 
a7. 
In early hard drives, commutation timing of brushless motors was controlled 
using Hall Effect sensors that were placed within the motor. As hard 
drives became smaller, the Hall sensors were removed to save space. To 
facilitate this removal, a method of determining optimal commutation 
timing was developed that did not require Hall sensors. This method 
involves the phenomenon of back electromotive force (BEMF), whereby a 
changing voltage is induced in the windings as a result of the windings 
moving through magnetic flux within the motor. The BEMF signals generated 
for a three-phase motor when measured with respect to center tap 11 are 
shown as signals A, B, and C in FIG. 2B. Comparing FIGS. 2A and 2B, it is 
evident that the BEMF signals cross the zero-voltage axis when the motor 
torques are at their maximum values. To provide the least amount of torque 
ripple, the motor is commutated at 30 electrical degrees before and after 
the maximum torque points. These ideal motor commutation times are shown 
both in FIG. 2C and in FIG. 3A as the signal "FCOM," which conventionally 
stands for "frequency of commutation." In the vernacular of motor 
engineers, the individual pulses of the FCOM signal may be referred to as 
"FCOM pulses." 
Analog comparators are connected across each phase winding 12, 14, and 16 
of the motor to determine when each of the BEMF signals is greater than 
zero. The output signals generated by these comparators are shown in FIGS. 
3B through 3D. The comparator signals of FIGS. 3B through 3D are logically 
decoded, using conventional means, to generate the tachometer signal shown 
in FIG. 3E. It is noted that the optimal motor commutation times are shown 
to occur at the midpoint of each high and low state of the tachometer 
signal as represented at points X and Y, respectively, of FIG. 3E. 
The midpoints X and Y of each high and low state of the tachometer signal 
are determined in accordance with the circuits of FIGS. 4A and 4B. The 
voltage waveforms generated across capacitors 22 and 28 of the circuits 
are shown in FIGS. 3F and 3G, respectively. To generate the waveform of 
FIG. 3F, capacitor 22 is charged with a conventional constant-current 
source 24 during the high period of the tachometer signal and is then 
discharged at twice the rate with a second conventional constant-current 
sink 26 after the tachometer signal changes states. When the spin motor is 
running at nominal speed, the capacitor 22 reaches its lowest level at 
point Y, which is the desired time to commutate the motor. Capacitor 22 is 
combined with conventional sensing and triggering circuitry (not shown) 
connected to the sequencer 18 to thereby commutate the motor driver 20 to 
the next phase. 
Capacitor 28 of FIG. 4B is provided to determine the commutation points 
labeled X. This is accomplished by charging capacitor 28 with a 
constant-current source 27 during the time at which capacitor 22 is being 
discharged, and then holding the voltage charged until the tachometer 
signal changes to a high state. At this time, capacitor 28 is discharged 
with a constant-current sink 29 that provides a current equal in magnitude 
but opposite in polarity as compared to the output current of 
constant-current source 27. When the capacitor 28 reaches its minimum 
voltage level, conventional sensing and triggering circuitry (not shown) 
senses the minimum voltage condition and issues an FCOM pulse to sequencer 
18, thereby causing sequencer 18 to select the next phase state (i.e., the 
next pair of windings). 
The above-described BEMF technique for determining commutation timing works 
well in that when the spin motor is first starting up the commutation 
points are not fixed in time. If the values of capacitors 22 and 28 are 
chosen correctly, the method can be used to commutate the motor even 
during the initial spin-up of the motor, during which time the frequency 
of the tachometer signal varies. The upper charge levels of capacitors 22 
and 28 are not critical; if the period is longer, the capacitors 22 and 28 
simply charge to a higher level. When the tachometer signal changes states 
due to a zero-crossing of the BEMF signal, the respective capacitor 22 or 
28 will be discharged. When the lowest voltage level or some other 
predetermined voltage threshold level is reached, the sensing and 
triggering electronics sequences the motor to the next commutation state. 
Although the technique is seemingly ideal, it is not without practical 
problems. For example, the tach signal of FIG. 3E is not exactly 
symmetrical due to e.g. errors in the spacing between magnetic poles of 
windings or random noise that cause erroneous determinations of BEMF 
zero-cross times. Because the timing of a given FCOM pulse is a function 
of the time period between two prior BEMF zero-cross times, any such 
variation in the measured spacing between preceding zero-crossing times 
may cause the motor to commutate to the next phase at the wrong time. Such 
erroneous commutation timing results in repetitive instants of sub-optimum 
torque, which in turn result in an undesirable phenomenon commonly known 
as "jitter." 
For the foregoing reasons, there is a need for a commutation delay 
generator that provides a consistent commutation delay that is relatively 
insensitive to short-term variations in BEMF zero-cross timing. 
SUMMARY 
The present invention addresses the aforementioned need by providing an 
inventive commutation control circuit that is insensitive to short-term 
variations in BEMF zero-cross timing. The commutation control circuit 
includes a frequency-to-current converter that receives the periodic 
series of commutation signals as input and outputs a delay current of a 
magnitude that is inversely proportional to the average period of the 
series of commutation signals (i.e., the average FCOM period). This 
proportional current is used to charge a delay capacitance of known value 
to provide a selected voltage change across the delay capacitance. 
Because the delay current used to charge the capacitance is proportional to 
the average commutation period, the charging time of the capacitance is 
also proportional to the average commutation period. For example, if the 
delay current were to double, the charge time of the delay capacitance 
would decrease by a factor of two. Similarly, if the delay current were to 
decrease by a factor of two, the charge time of the delay capacitance 
would double. 
The commutation delay generator also includes a back-EMF sensor that senses 
the back EMF induced in an unpowered winding of the motor. The level of 
the back EMF provides an indication of the position of the rotor. When the 
back EMF across the unpowered winding equals zero, the delay circuit 
begins to charge the delay capacitance with the delay current. When the 
voltage change across the delay capacitance reaches a selected threshold 
(thereby indicating that the delay period has expired), the delay circuit 
issues an FCOM pulse to commutate the motor. 
In one embodiment of the invention, the delay capacitance is alternately 
charged and discharged a number of times to provide an increased total 
voltage change without requiring an increased supply voltage. This 
embodiment allows for the use of a relatively small capacitor to provide 
the delay capacitance.

DETAILED DESCRIPTION 
FIG. 5 is a block diagram of a commutation control circuit 50 in accordance 
with the present invention coupled to the conventional motor and select 
circuitry 7 of FIG. 1. Control circuit 50 includes a delay circuit 70 that 
provides a substantially periodic series of FCOM pulses to motor and 
select circuitry 7 and to an averaging circuit 80. The FCOM pulses cause 
motor and select circuitry 7 to commutate from one phase to the next in 
the manner explained above with respect to the conventional motor and 
select circuitry 7 of FIG. 1. 
Averaging circuit 80 receives the FCOM pulses and outputs a delay signal on 
line 84 to delay circuit 70. In one embodiment, the delay signal is a 
current level of a magnitude proportional to the frequency (and therefore 
inversely proportional to the period) of the incoming series of FCOM 
pulses: the higher the commutation frequency, the higher the magnitude of 
the current level of the delay signal. 
Conventional logic from motor and select circuitry 7 causes BEMF sensor 90 
to select the center tap and the node of the unpowered winding (i.e., A, 
B, or C) so that the BEMF voltage developed across the unpowered winding 
is present across nodes POS and NEG. An input signal from sequencer 18 to 
terminal REVERSE ensures that center tap 11 and the node of the unpowered 
winding are selected such that the voltage on node POS is moving in a 
generally positive direction relative to the voltage on node NEG. Thus 
configured, delay circuit 70 detects a "zero cross" (i.e., when the BEMF 
voltage across the unpowered winding is zero) when the voltage on node POS 
is equal to the voltage on node NEG. Delay circuit 70 then uses the timing 
of the zero cross and the current level of the delay signal on line 84 to 
establish the appropriate timing for a subsequent FCOM pulse. 
FIG. 6 is a schematic diagram of commutation control circuit 50 of FIG. 5, 
including averaging circuit 80, BEMF sensor 90, and delay circuit 70. BEMF 
sensor 90 receives a number of input signals from motor and select 
circuitry 7. Nodes A, B, and C are electrically the same nodes as nodes A, 
B, and C, respectively, of FIG. 1. As explained above with respect to FIG. 
5, the voltage levels on nodes A, B, and C, when measured with respect to 
the voltage level on center tap 11, provide an indication of zero-cross 
timing. A resistor network 99 includes four resistors that combine with 
capacitors 96 and 98 to create a pair of low-pass filters for the BEMF of 
the unpowered windings. The resistors of resistor network 99 are typically 
200 K.OMEGA. each, while capacitors 96 and 98 are typically 20 pF each. 
As explained above in connection with FIGS. 1 and 2B, when phase A is 
unpowered the BEMF voltage between node A and center tap 11 crosses the 
zero-voltage axis when the motor torque is at a maximum value. And, to 
provide the least amount of torque ripple, the motor must be commutated at 
30 electrical degrees after this maximum. To this end, delay circuit 70 
senses the BEMF voltage across nodes POS and NEG to determine the timing 
of a zero cross. Then, delay circuit 70, using the zero cross as a timing 
reference, waits for a delay period T.sub.DLY equal to approximately 30 
electrical degrees (i.e., approximately T.sub.FCOM /2) and outputs an FCOM 
pulse to motor and select circuitry 7, averaging circuit 80, and sequencer 
18. 
Averaging circuit 80 includes a frequency-to-current converter 82 that 
outputs a delay current I.sub.delay on line 84. After start-up, the 
magnitude of current I.sub.delay is inversely proportional to the average 
period of the FCOM signal from delay circuit 70. Stated mathematically, 
##EQU1## 
where T.sub.FCOM is the average period of e.g. one hundred FCOM pulses and 
.alpha. is the gain factor of frequency-to-current converter 80. Typical 
values for .alpha. and T.sub.FCOM are 3.47 nC and 347 .mu.s, respectively, 
resulting in a delay current I.sub.delay of approximately 10 .mu.A. 
Averaging circuit 80 may be any conventional frequency-to-current converter 
that is configured to provide an output current proportional to the 
average commutation period T.sub.FCOM of the commutation signal on 
terminal FCOM. Because of inherent spacing errors between motor stators, 
it is recommended that the number of FCOM periods averaged be equal to at 
least the number of FCOM pulses for a single mechanical rotation, which is 
e.g. 24 in a eight-pole motor. The upper limit of the number of FCOM 
periods averaged is quite high, (e.g., one thousand), for the average FCOM 
period T.sub.FCOM is very small compared to the acceleration time constant 
of a typical motor. If the number is too high, the commutation timing will 
be slow to respond to changes in motor speed. 
The commutation delay period T.sub.DLY is calculated using the equation: 
##EQU2## 
where .increment.V.sub.DLY represents the total change in voltage across 
capacitance C.sub.DLY. Substituting for I.sub.delay in accordance with 
equation (1) above, the commutation delay period T.sub.DLY becomes: 
##EQU3## 
By selecting the values of C.sub.DLY, .increment.V.sub.DLY, and the 
constant .alpha. so that the factor C.sub.DLY .increment.V.sub.DLY 
/.alpha.=1/2, the FCOM delay period T.sub.DLY is set to exactly one half 
of the average FCOM period T.sub.FCOM, or T.sub.FCOM /2. If the factor 
C.sub.DLY .increment.V.sub.DLY /.alpha. is greater than one half, the 
delay period T.sub.DLY will be greater than T.sub.FCOM /2, causing a phase 
delay on the commutation. Conversely, if the factor C.sub.DLY 
.increment.V.sub.DLY /.alpha. is less than one half, the result will be a 
phase advance on the commutation. 
Delay circuit 70 includes a current-controlled transconductance amplifier 
72 and a delay capacitance C.sub.DLY. Amplifier 72 receives the BEMF 
signal POS-NEG (i.e., the voltage difference between nodes POS and NEG) 
and the delay current I.sub.DLY on line 84. When the voltage on node POS 
exceeds the voltage on node NEG (i.e., when a zero-crossing occurs), 
amplifier 72 outputs a delay current on node V.sub.DLY that is equal in 
magnitude to that of the delay current I.sub.delay on line 84. The current 
on node V.sub.DLY charges (or discharges) delay capacitor C.sub.DLY until 
the factor C.sub.DLY .increment.V.sub.DLY /.alpha.=1/2, at which time 
delay circuit 70 outputs an FCOM pulse. 
As explained above, each FCOM pulse is developed after delay period 
T.sub.DLY that is established using the average FCOM period T.sub.FCOM. 
This is problematic, as there are no FCOM periods to average when the 
motor is initially started up. To solve this problem, averaging circuit 80 
is configured to provide some minimum level of delay current when the 
commutation signal on terminal FCOM has a frequency of between e.g. zero 
and 150 Hz. This minimum delay current develops FCOM pulses of a 
predetermined frequency when the motor is first started up until the 
commutation frequency reaches a level sufficient to develop a delay 
current I.sub.delay greater than the offset current. Once delay current 
I.sub.delay is greater than the offset current, averaging circuit 80 gains 
control of delay period T.sub.dly so that the delay period T.sub.DLY will 
behave in accordance with equation (1). In one embodiment, averaging 
circuit 80 is a frequency-to-current converter with an offset current of 
approximately 500 nA, and is of the type described in the above-referenced 
application entitled "Frequency-To-Current Converter". 
In accordance with the embodiment of FIG. 6, the value (and therefore 
physical size) of delay capacitance C.sub.DLY is minimized to allow for 
easier, more economical integration of the capacitance. The method and 
circuitry used to minimize capacitance C.sub.DLY is described below in 
connection with FIGS. 6 through 11. 
For a given capacitance C with a constant charging current I.sub.C, the 
time constant .tau..sub.C of capacitance C is proportional to the product 
of the change in voltage .increment.V and the capacitance C divided by the 
charging current I.sub.C. This relationship may be expressed 
mathematically as: 
##EQU4## 
According to equation (4), for a given time constant .tau..sub.C the 
necessary value of the capacitance C (and thus the physical area required 
to integrate such a capacitance) may be minimized by either increasing 
.increment.V or decreasing the current I.sub.C. 
Unfortunately, there is a lower limit to the level of current I.sub.C that 
may be used to charge the capacitance C, for when the current is too low, 
noise and leakage result in unacceptably poor accuracy in defining the 
time constant .tau..sub.C. Moreover, increasing .increment.V is not a 
simple matter because it is not practical to substantially increase the 
power supply voltages for integrated circuits to increase the time 
constant of a particular capacitor. For these reasons, Applicant invented 
a technique that allows for an effective increase in the change of voltage 
on delay capacitance C.sub.DLY without requiring increased voltage 
potentials. According to this aspect of the invention, the desired voltage 
range is "folded" into a number of smaller voltage ranges. For a detailed 
discussion of a similar folding technique used to increase the effective 
value of a capacitance, see the related application entitled 
"Frequency-to-Current Converter," which is incorporated herein by 
reference. 
According to the inventive folding technique, a 16-volt .increment.V on 
node V.sub.DLY is folded into e.g. four segments, two decreasing and two 
increasing. That is, instead of charging capacitance C.sub.DLY from e.g. 
one to 17 volts to obtain a .increment.V of 16 volts, capacitance 
C.sub.DLY is charged and discharged between one and five volts four times 
(i.e., four 4-volt changes), for a total .increment.V of 16 volts. In this 
way, the necessary value of delay capacitance C.sub.DLY is decreased by a 
factor of four. This decrease in capacitance translates into a similar 
decrease in physical size that advantageously allows delay capacitance 
C.sub.DLY to be more readily integrated. 
In the embodiment of FIG. 6, the commutation delay period T.sub.DLY may be 
adjusted by changing the reference voltage on terminal V.sub.DAC, and 
therefore the voltage range .increment.V of node V.sub.DLY, using a 
conventional 6-bit digital-to-analog converter 79. Of course, other 
adjustable or fixed voltage references may also be used. However, 
embodiments that include adjustable phase delay advantageously allow users 
to optimize the delay period T.sub.DLY for particular applications. 
FIG. 7 is a schematic diagram of transconductance amplifier 72 coupled to 
delay capacitance C.sub.DLY and voltage clamp 73. The purpose of amplifier 
72 is to charge and discharge delay capacitance C.sub.DLY at a rate 
established by the delay current I.sub.delay. Recall that a zero cross is 
detected when the voltage on node POS "crosses" the voltage on node NEG, 
and that an FCOM pulse should be developed after a delay period T.sub.DLY 
equal to one-half of the average FCOM period T.sub.FCOM, or T.sub.FCOM /2. 
Recall also that the current I.sub.delay is inversely proportional to the 
average FCOM period T.sub.FCOM, and is therefore also inversely 
proportional to a delay of T.sub.FCOM /2. Because of this proportionality, 
the delay period T.sub.DLY can be established by charging and discharging 
capacitance C.sub.DLY a predetermined number of times using the delay 
current I.sub.delay. 
Transconductance amplifier 72 includes input transistors 106A and 106B, 
which receive inputs on lines POS and NEG from BEMF sensor 90. Transistors 
106A and 106B are level-shift transistors that are biased by current 
sources 107A and 107B, respectively. Transconductance amplifier 72 also 
includes a POS-NEG lockout circuit 100 that causes amplifier 72 to ignore 
the signals on terminals POS and NEG when counter circuit 78 outputs a 
logic one on line LOCK. The purpose for the lock signal is described below 
in connection with FIGS. 8 and 9. For the present, assume that the lock 
signal on line LOCK is a logic zero, in which case transistors 102B and 
102C are off and POS-NEG lockout circuit 100 is therefore deactivated. 
When the signal on line UP is a logic one, indicating that delay 
capacitance C.sub.DLY is to be charged "up," delay current I.sub.delay is 
mirrored first by transistors 103A and 103B then by transistors 104A and 
104B to provide a current substantially equal to the delay current 
I.sub.delay through either transistors 108A and 110A or transistors 108B 
and 112A, the current path depending on the relative signal levels on 
terminals POS and NEG. If the voltage on node POS is more positive than 
the voltage on node NEG, then the current equal to the delay current 
I.sub.delay will pass through transistors 108B and 112A, and will 
consequently be mirrored by transistor 112B (because the voltage on line 
XUP is a logic zero, the output of AND gate 134 will be a logic zero; 
thus, transistor 116B, and therefore transistor 112C, cannot conduct). The 
current through transistor 112B will be mirrored by transistors 120A and 
120B so that delay capacitance C.sub.DLY will be charged by a current 
substantially equal to the delay current I.sub.delay ; consequently, the 
voltage on node V.sub.DLY will increase. If, on the other hand, the 
voltage on node POS is more negative than the voltage on node NEG, then a 
current equal to the delay current I.sub.delay will pass through 
transistors 108A and 110A, and will consequently be mirrored by transistor 
110C (because the voltage on line XUP is a logic zero, transistor 116A, 
and therefore transistor 110B, cannot conduct). Transistor 110C will draw 
charge from C.sub.DLY, thereby decreasing the voltage on node V.sub.DLY. 
Amplifier 72 exhibits the opposite behavior when the signal on line UP is a 
logic zero, indicating that delay capacitance C.sub.DLY is to be 
discharged by a current substantially equal to the delay current 
I.sub.delay. In that case, a voltage on node POS that is more positive 
than that on node NEG will cause delay capacitance C.sub.DLY to discharge 
at a rate determined by a discharge current substantially equal to the 
delay current I.sub.delay. Further, a voltage on node POS that is more 
negative than that on node NEG will cause delay capacitance C.sub.DLY to 
charge at a rate determined by a current substantially equal to delay 
current I.sub.delay. This behavior allows for the "folding" of delay 
capacitance C.sub.DLY and the consequent reduction in the necessary value 
of capacitance C.sub.DLY. 
A logic one on line LOCK activates POS-NEG lockout circuit 100, causing 
amplifier 72 to ignore the voltages on nodes POS and NEG. The inverted 
lock signal on line LOCK, through AND gates 132 and 134, turns off 
transistors 116A, 116B, 118A, and 118B, while the lock signal turns on 
transistor 102B and, consequently, transistor 101B. In this condition, 
transistors 101B and 102B constantly draw a current substantially equal to 
the delay current I.sub.delay through transistor 120A. The current is 
mirrored by transistor 120B to charge delay capacitor C.sub.DLY. 
Transistors 101C and 102C have multiplication factors M of two (M=2), as 
compared to the multiplication factors of one (M=1) for transistors 101A, 
101B, 102A, and 102B. Consequently, when transistor 102C is activated 
(i.e., when line XUP is at a logic one), transistors 101C and 102C draw a 
current of approximately twice the delay current I.sub.delay from delay 
capacitor C.sub.DLY. Because delay capacitor is charged via transistors 
101B and 102B with a current approximately equal to I.sub.delay, the net 
result is that delay capacitance C.sub.DLY is discharged with a discharge 
current substantially equal to I.sub.delay. Thus, when the signal on line 
LOCK is a logic one, the logic level on line UP alone determines whether 
delay capacitance C.sub.DLY is charged or discharged: the inputs to 
terminals POS and NEG are ignored. 
Also shown in FIG. 7, nodes POS and NEG are connected to the inverting and 
non-inverting inputs, respectively, of a comparator 140, which has an 
output node XSIGN. The voltage on node XSIGN is a logic one when the 
voltage on node POS is less than the voltage on node NEG, and is a logic 
zero when the voltage on node POS is greater than the voltage on node NEG. 
The signal on node XSIGN is used to control whether counter circuit 78 of 
FIG. 6 increments or decrements. 
FIG. 8 is a schematic diagram of counter circuit 78 of FIG. 6. Counter 
circuit 78 receives signals from state machine 76 (on increment line INC 
and decrement line DEC) that allow counter circuit 78 to count the number 
of times delay capacitor C.sub.DLY charges and discharges. A delay period 
T.sub.DLY is established by multiplying the charge and discharge times of 
capacitance C.sub.DLY by the number of counts stored in counter circuit 
78. This delay period T.sub.DLY is used to determine the timing of the 
FCOM pulse following each detected zero-cross. 
Counter circuit 78 includes a one-bit up/down counter 150 and an up counter 
152. Up/down counter 150 and up counter 152 combined count the number of 
times delay capacitance C.sub.DLY charges; up/down counter 150 stores the 
least-significant digit of the count and up counter 152 stores the 
remaining two significant digits. Counter circuit 78 also includes AND 
gates 154 and 157, each of which has an input connected to node 
COMP.UND.sub.-- L from comparator circuit 74 and an input connected to up 
counter 152 via a line "CNT=2+2." AND gate 157 includes an additional 
input connected to line LOCK.sub.-- 1. The output of AND gate 154 is 
connected to the input of a twenty-five-microsecond one shot 156. 
Up/down counter 150 has two output terminals, LOCK.sub.-- 1 and LOCK.sub.-- 
2, both of which are coupled to the inputs of a two-input multiplexer 158. 
The select input S of multiplexer 158 is coupled to a programmable logic 
level via a line PRG.sub.-- LOCK, and the output of multiplexer 158 is 
coupled to an input of an OR gate 160. OR gate 160 also receives an input 
from amplifier 72 of FIG. 7 via line XSIGN and provides an output to state 
machine 76 via a line SIGN. 
Positive-going input pulses on lines INC and DEC cause up/down counter 150 
to increment and decrement, respectively. When the count stored by counter 
150 is less than one, counter 150 outputs a logic zero on line LOCK.sub.-- 
1, and when the count is less than two, counter 150 outputs a logic zero 
on line LOCK.sub.-- 2. A logic zero on line LOCK.sub.-- 2 disables up 
counter 152. This logic zero is also provided through multiplexer 158 to 
one input of OR gate 160. Consequently, when the count is less than two 
the logic level on node SIGN will be the inverted signal on node XSIGN 
from amplifier 72. That is, if the voltage on node POS is more positive 
than that on node NEG, the voltage on node SIGN will be a logic one, and 
if the voltage on node NEG is more positive than that on node POS, the 
voltage on node SIGN will be a logic zero. 
Up/down counter 150 is used to integrate the signal on node V.sub.DLY for a 
selected period following a zero-cross detection. For this reason, up/down 
counter 150 is designed to count backward, as may be necessary when the 
count is greater than zero and a noise spike causes the signal POS-NEG to 
go below zero. Once the count is greater than two the signal on line 
LOCK.sub.-- 2 disables the output of differential amplifier 140 by 
providing a constant logic one to an input of OR gate 160 so that 
subsequent negative noise spikes of signal POS-NEG are ignored. 
Up/down counter 150 establishes a window during which capacitance C.sub.DLY 
integrates the signal on node V.sub.DLY. Upon reaching a count of either 
one or two, depending on which of lines LOCK.sub.-- 1 and LOCK.sub.-- 2 
are selected by the logic level on line PRG.sub.-- LOCK, multiplexer 158 
outputs a logic one to an input of OR gate 160. The logic level on 
program-lock line PRG.sub.-- LOCK is programmable, allowing users of the 
inventive delay circuit to select the desired time period after which 
amplifier 72 will ignore noise spikes on nodes POS and NEG. Assuming, for 
example, a logic zero on program-lock line PRG.sub.-- LOCK, noise spikes 
that cause the voltage POS-NEG to go below zero will not effect the value 
of the voltage on node SIGN once up/down counter 150 reaches a count of 
two. Consequently, such noise spikes will not effect the charge and 
discharge rates of capacitance C.sub.dly. 
FIG. 9 shows a state diagram that provides a functional description of 
one-bit up/down counter 150. Counter 150 receives as inputs an increment 
signal on line INC and a decrement signal on line DEC. When commutation 
control circuit 50 is reset or develops a commutation pulse, counter 150 
is reset to state 000. Upon the positive edge of an increment pulse on 
line INC, counter 150 increments to state 001 and outputs a logic one on 
line LOCK.sub.-- 1. Then, on the trailing edge of the same increment 
pulse, counter 150 transitions to state 011. From state 011, counter 150 
can either be decremented so that the signal on line LOCK.sub.-- 1 returns 
to zero, or incremented so that line LOCK.sub.-- 2 transitions to a logic 
one. 
Once the signal on line LOCK.sub.-- 2 is a logic one (i.e., once the count 
stored in up/down counter 150 is two), the logic one on line LOCK.sub.-- 2 
enables up counter 152 so that counter circuit 78 can continue counting 
beyond two. Then, once up counter 152 reaches a predetermined number of 
charge/discharge cycles (two in the present example) and the voltage on 
node V.sub.DLY drops below the reference voltage on node V.sub.MIN causing 
the signal on node COMP.UND.sub.-- L to go high, AND gate 154 provides an 
output pulse that, after being extended to 25 microseconds by one shot 
156, is output as an FCOM pulse on node FCOM. 
FIG. 10 shows a state diagram that provides a functional description of 
state machine 76. The inputs to state machine 76 are the signals on nodes 
OVER.sub.-- H, UNDER.sub.-- L, SIGN, and FCOM. A logic one on node 
OVER.sub.-- H indicates that the voltage on node V.sub.DLY is greater than 
the voltage on node V.sub.dac. A logic one on node UNDER.sub.-- L, the 
output of AND gate 157 of FIG. 8, indicates that: 
1. the voltage on node V.sub.DLY is below the voltage on node V.sub.MIN, as 
evidenced by a logic one on line COMP.UND.sub.-- L; 
2. the count stored in up/down counter 150 is greater than one, as 
evidenced by a logic one on line LOCK.sub.-- 1; and 
3. the count stored in up counter 152 is less than two, as evidenced by a 
logic zero on line CNT=2+2. 
Finally, as described above in connection with FIG. 7, a logic one on node 
SIGN indicates that the voltage on node POS is more positive than the 
voltage on node NEG. 
Referring to the waveforms of FIG. 11, the time Z.sub.C represents the 
instant that the BEMF signal POS-NEG crosses the zero-voltage axis. The 
BEMF signal POS-NEG crosses zero at other times due to noise; however, for 
purposes of the following description, the time Z.sub.C represents the 
true zero cross. Delay circuit 70 operates to provide an FCOM pulse a 
delay period T.sub.DLY (i.e., a delay of one half the average FCOM period 
T.sub.FCOM) after the zero cross at time Z.sub.C. 
State machine 76 receives as inputs the digital (binary) signals on lines 
OVER.sub.-- H, UNDER.sub.-- L, SIGN, and FCOM, and outputs a digital 
signal on line UP to amplifier 72 and digital signals on increment line 
INC and decrement line DEC to counter 78. After each FCOM pulse (and when 
commutation control circuit 50 is reset or powered up), state machine 76 
is reset to state 000 and counter circuit 78 is configured to store a 
count of zero. In state 000, state machine 76 outputs a logic one on line 
UP to amplifier 72. As explained above in connection with FIG. 7, when the 
voltage on line UP is positive, amplifier 72 charges delay capacitance 
C.sub.DLY when the voltage on node POS is more positive than the voltage 
on node NEG, and discharges delay capacitance C.sub.DLY when the voltage 
on node POS is more negative than the voltage on node NEG. 
Before the zero crossing at time Z.sub.C, BEMF signal POS-NEG will be 
negative in the absence of positive noise spikes. As such, the voltage on 
node V.sub.DLY will remain low. When a noise spike, such as spike 200, 
causes BEMF signal POS-NEG to go above zero, the logic level on node SIGN 
will change from low to high and the voltage on node V.sub.DLY will begin 
to increase. As shown in FIG. 11, when spike 200 decreases to zero volts, 
the logic level on node SIGN returns to a logic low, causing the voltage 
on node V.sub.DLY to decrease. 
At time Z.sub.C BEMF signal POS-NEG again crosses zero. Consequently, the 
signal on node SIGN becomes a logic one and the voltage on node V.sub.DLY 
begins to climb once again. When the voltage on node V.sub.DLY increases 
above the voltage on node V.sub.MIN, comparator 74 will output a logic 
zero on node UNDER.sub.-- L. Thus, during the positive-going segment 202 
of the voltage on node V.sub.DLY, the inputs on nodes OVER.sub.-- H, 
UNDER.sub.-- L, and SIGN will be 0, 0, and 1, respectively. 
While the voltage on line UP remains a logic one, any negative noise spikes 
that go below zero will reverse the direction of voltage change on node 
V.sub.DLY. For example, during a negative noise spike 204, the voltage on 
node V.sub.DLY decreases along a negative-going segment 206. Once noise 
spike 204 returns to a voltage greater than zero, the voltage on node 
V.sub.DLY will again increase. Eventually, the voltage on node V.sub.DLY 
will rise above the reference voltage on node V.sub.DAC causing comparator 
74 to output a logic one on node OVER.sub.-- H. At this point, the inputs 
on nodes OVER.sub.-- H, UNDER.sub.-- L, and SIGN will be 1, 0, and 1, 
respectively. These inputs will cause state machine 76 to transition from 
state 000 to state 001 so that state machine 76 outputs a logic zero on 
line UP. As described above in connection with FIG. 6, providing a logic 
zero on the line UP to amplifier 72 reverses the behavior of amplifier 72 
with respect to BEMF signal POS-NEG. That is, when the voltage on node POS 
is more positive than that on node NEG, amplifier 72 discharges delay 
capacitor C.sub.DLY, causing the voltage on node V.sub.DLY to decrease. 
And, when the voltage on node POS is more negative than that on node NEG, 
amplifier 72 charges delay capacitor C.sub.DLY, causing the voltage on 
node V.sub.DLY to begin to increase. 
Shortly after capacitance C.sub.DLY begins to discharge, the voltage on 
node V.sub.DLY will fall below the voltage on node V.sub.DAC so that the 
signal on node OVER.sub.-- H will return to a logic zero. Assuming that 
BEMF signal POS-NEG remains positive, state machine 76 will receive the 
inputs 0, 0, and 1 on input nodes OVER.sub.-- H, UNDER.sub.-- L, and SIGN, 
respectively, and will consequently move from state 001 to state 011. 
State machine 76 will then output a logic one on node INC causing the 
count stored in counter circuit 78 to increment. In the present case, the 
count increases from zero to one, as indicated by the signal COUNT of FIG. 
11. 
For brevity, only a few of the eight possible states of state machine 76 
are described above. The remaining states, as shown in state diagram of 
FIG. 10, will be readily understood by those skilled in the art. 
Capacitance C.sub.DLY will charge and discharge in the manner described 
above until the count stored by counter circuit 78 reaches a predetermined 
number. In the example of FIG. 11, for example, counter circuit 78 is 
configured to issue an FCOM pulse when the count is four (i.e., the count 
of up/down counter 150 is two and the count of up counter 152 is two) and 
the signal on node UNDER.sub.-- L is one. The FCOM pulse on node FCOM is 
conveyed to sequencer 18 to initiate a commutation and also to reset both 
state machine 76 and counter circuit 78. The above-described process is 
then repeated for each subsequent zero cross so that an FCOM pulse is 
consistently developed after a delay of approximately 30 electrical 
degrees from each zero cross. 
Commutation delay generators in accordance with the present invention are 
not limited to the particular applications described above. For example, 
the electric motors that can benefit from such delay generators are not 
limited to disk drive motors. In addition, timing references from which to 
begin a delay period may be derived from sources other than BEMF sensors, 
such as Hall effect sensors. Therefore, the scope of the appended claims 
should not be limited to the description of the preferred versions 
described herein.