Systems and methods for pushing data

A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

BACKGROUND

Modern computing environments generally provide for multiple sets of computer instructions to execute concurrently. For example, a computing environment may permit a single program to spawn two or more “threads,” where the treads execute in parallel, or tow processes may execute concurrently on two different processors. When the instructions execute concurrently, it is frequently the case that these different sets of instructions may require shared access to particular data, such as a cache line. For example, two processors executing two different threads of a program may both need to read from, and write to, a data structure located within the systems main memory or on one or more processors' cache. Concurrency control policies thus can be implemented as one way to enforce limits on access to a resource, such as where there are many threads of execution. For instance, a lock is one way of enforcing a concurrency control policies that prevents other threads running on other processors from accessing a resource. Locks and other concurrency control mechanisms may result in increased latency for access to resources.

DETAILED DESCRIPTION

FIG. 1depicts an example of a system100for pushing data. The system100includes a push engine102. The push engine102could be implemented, for example, as a processor, or a process running on a processor with instructions for performing certain operations. Alternatively, the push engine102could be implemented as operation code (e.g., “opcode”). The push engine102determines a next consumer104of a block of data. The next consumer104could be implemented, for example, as a processor, a controller, such as an input/output (I/O) controller or an I/O device (e.g., a graphics processing unit (GPU), or an Ethernet controller). There may be more than one next consumer of the block data. As used herein, the term “next” as applied to a data consumer, is not intended to require a particular order. That is, the next consumer104of the block of data need not be the immediately succeeding consumer of the block of data, but rather an expected consumer of the block data that may execute an instruction that employs the block of data sometime in the future. The block of data could be implemented as data in at least one cache line (“block of data”), although the block of data can correspond to any unit of data that can be pushed according to system requirements.

The push engine102can determine the next consumer104in the absence of detecting a request from the next consumer104for the block of data. The block of data can be pushed to the next consumer104, for example, when one or more instructions being executed in the system100cause the block of data to become temporarily inaccessible to the next consumer104. For instance, a concurrency control mechanism can be implemented to prevent concurrent access to resources, such as the block of data. The concurrency control mechanism can be employed at the source node, for example, as a lock mechanism (e.g., seqlock instructions) to prevent, temporarily, concurrent access to the block of data. Pushing the block of data to the next consumer104can reduce latency by decreasing the access time of the block of data for next consumer104. One skilled in the art will appreciate other processes and/or situations where pushing data can be beneficial. As used herein, the term “push” and variations thereof are intended to encompass any transfer of a block of data to one or more potential consumer nodes that occurs in the absence of detecting a request (e.g., a read request, write request, etc.) from the potential consumer for such block of data. That is, a request for the block of data may be issued, but such request does not directly cause the source node108to push the data.

The push engine102can provide means for determining the next consumer104of the block of data in the absence of detecting a request for the block of data from the next consumer104. The particular way that the push engine102determines the next consumer104could be based on the particular needs of the system100being implemented. For example, the push engine102could determine the next consumer104based on an examination of an instruction in an instruction queue or based on information contained in a process table employed by the operating system. Similarly, a queue of processes waiting for a lock may be inspected, or historical usage information may be used to determine if and when to push data. One skilled in the art will appreciate the alternate structure and methodologies for implementing the push engine102.

The push engine102causes the block of data to be pushed to target memory106that is associated with the next consumer104. The target memory106could be implemented for example, as one or more structures accessible at least by the next consumer104, such as a local cache, a shared cache or local memory bank. InFIG. 1, the target memory106is illustrated as being internal to the next consumer104, but it will be appreciated by those skilled in the art that the target memory106could be external to the next consumer104(e.g., an external cache). Additionally, it is to be understood that the target memory106could be implemented as a memory structure that is accessible by multiple processors, such as a shared cache memory. For purposes of simplification of explanation in this example, it will be understood that the next consumer104includes the target memory106.

Additionally, the push engine102can identify a source node108that stores a coherent copy of the block of data that is to be pushed. The source node108could be implemented, for example, as a processor having at least one associated cache, wherein the at least one associated cache stores the coherent copy of the block of data. Those skilled in the art will understand and appreciate various means that can be employed to identify the source node108, which means may vary according to the protocol being implemented in the system100. For example, the push engine102could access a directory, such as a coherency directory, to identify the source node108if a directory based coherency protocol is employed by the system100. In yet another example, the push engine102could identify the source node108by snooping a set of one or more processor nodes, including the source node108. Additionally or alternatively, the push engine102could make the determination of the next consumer104based on an examination of an operating system (OS) process table.

When the next consumer104has been identified, the push engine102can operate as means for causing a coherent copy of the block of data to be pushed from the source node108to the target memory106associated with the next consumer104. The push engine can cause the block of data to be pushed to target memory that resides in closer proximity to the next consumer than the memory at the source node from which the data is pushed. As a result, latency can be reduced when the next consumer accesses the block of data.

The push engine102can also cause the source node108to provided the block of data to a particular memory location, such as to a particular cache level of the next consumer104. In this regard, push engine102can further provide means for determining which level of cache associated with the next consumer104the block of data is to be pushed. The level of cache can indicate proximity of the cache relative to the next consumer104. Additionally or alternatively, the push engine102could specify a maximum cache level (e.g., a cache level at a maximum proximity) to which the block of data is to be pushed, which maximum cache level could be a cache level lower than the cache level of a coherency directory in a system that employs a coherency based protocol. Alternatively, the determination as to the level of cache to which block of data is pushed could be made by the source node108and/or the next consumer104.

In certain circumstances, the block of data being pushed may be written back to system memory110. The system memory110could be implemented, for example, as random access memory (RAM), such as static RAM or dynamic RAM. The source node108and/or the next consumer104can provide means for updating the system memory110after ownership of the block of data has been transferred to the target memory106. For instance, the source node108can writeback the block of data to the system memory110depending on the coherency state associated with the block of data. As a further example, if the system100employs a directory based cache coherency protocol such as the MESI coherency protocol, the block of data could have an associated state of ‘M’ or ‘E’ that could indicate that the block of data is exclusively owned (and modified or unmodified) by the source node108. It is to be understood that other coherency protocols could be employed. It is to be understood that the particular coherency state of the block of data and state transitions at the source node108and the next consumer104can vary based on the coherency protocol implemented.

When the next consumer104executes the examined instruction (e.g., the instruction that employs the block of data), typically, the next consumer104can attempt to read the block of data from a local cache, such as L1, L2, and L3 caches associated with the next consumer104. Since the block of data has been pushed from the source node108to the target memory106that is accessible by the next consumer104, next consumer104can receive a cache hit for the block of data. Since the next consumer104receives a hit for the block of data, the next consumer104can execute the examined instruction that employs the block of data with reduced latency compared to a situation when the next consumer would have received the data from the source node108(or from the system memory110) in response to a request for such data.

FIG. 2illustrates an example of a data flow diagram, such as may correspond to the system100illustrated inFIG. 1. For purposes of simplification of explanation, the same reference numbers that are used inFIG. 1are used inFIG. 2to identify corresponding parts. InFIG. 2, the block of data has an associated cache coherency state that indicates that the cache line is exclusively owned and unmodified (‘E’ state) or modified (‘M’ state) by the source node108. The push engine102provides the source node108with a push instruction that causes the source node108to push the block of data to the target memory106. Additionally, the source node108can transfer ownership of the block of data to the target memory106and change the coherency state of the block of data at the source node108from exclusive and unmodified state (‘E’ state) or modified state (‘M’ state) to an invalid state (‘I’ state) after the block of data has been pushed to the target memory106. In connection with the source node108pushing the block of data to the target memory106, the source node108can perform a data writeback to the system memory110. The data writeback can ensure that the system memory110receives and maintains a coherent copy of the block of data in conjunction with ownership of the block of data being transferred to the target memory106.

Alternatively, the source node108can change the block of data from an exclusive unmodified state (‘E’ state) to a shared state (‘S’ state). In such a situation, the block of data could be changed to the shared state (‘S’ state) and the source node108could process the push instruction in a manner described above with respect toFIG. 1. Particular state changes may vary according to the cache coherency protocol being implemented. One of ordinary skill in the art will appreciate the various state changes that could be implemented.

FIG. 3illustrates an example of a multiprocessor system300that can implement pushing data from a processor's cache to one or more next consumer. The system300includes a plurality of cells302and304that are communicatively coupled to each other via a system interconnect306. The system interconnect306could be implemented, for example, one or more wires and/or switches that provide for electrical communication between the cells302and304. For purposes of simplification of explanation, only cell302is shown in detail, but it is to be understood that other cells (e.g., cell(s)304) could be implemented in a similar fashion. Alternatively, the other cell(s)304could be implemented in a different manner from the cell302.

The cell302can include a plurality of processor cores indicated at PROC. 1-PROC.4 (308). Although the cell302is shown to have four processor cores308, it is to be understood that the cell302could include one or more processor cores308. The processors cores308could be implemented, for example as microprocessor cores that execute computer instructions. Each processor core308can include a cache hierarchy of two or more levels of cache. In the example illustrated inFIG. 3, each processor core308includes three hierarchical levels of local cache, namely L1 cache310, L2 cache312and L3 cache314, respectively. Each hierarchical level of cache indicates a relative proximity (or distance) of the cache to the respective cache's associated processor core308. In the present example, the L1 cache310and L2 cache312are shown to be internal to the processor cores308. Additionally, in the present example, the L3 cache314is shown to be an external cache, but it is to be understood that the L3 cache314could be internal as well. Furthermore, although three levels of cache are shown, it is to be understood that each of the processors cores308could have greater or fewer levels of cache. However, one skilled in the art would appreciate that the L1 cache310and/or the L2 caches312could be external to the processor cores308as well.

The processors cores308can communicate with each other over a cell interconnect316. The cell interconnect316could be implemented, for example, as one or more wires and/or switches (e.g., a processor bus or backplane) that provide for electrical communication between the processors to a L4 shared cache318. The L4 shared cache318could be implemented, for example as static RAM or dynamic RAM that is accessible to the processor cores308. The cell interconnect316can also communicatively couple the processors to a memory controller320and an I/O controller322. The memory controller320processes data transfer to and from a system memory324. The system memory324could be implemented as RAM, such as static RAM or dynamic RAM. The I/O controller can processes data transfers to and from external devices (not shown), such as a GPU, an Ether controller and non-volatile memory storage (e.g., a hard disk).

Each processor core308can include a push engine326running as a process on the associated processor core308. The push engine326could not be implemented, for example, as opcode that is executed on one or more of the processors core308. AlthoughFIG. 3depicts a push engine326running on each of the processor cores308, it is to be understood that the push engine326could run on fewer than all of the processors cores308or otherwise be distributed in the system or implemented as separate hardware for each cell.

As one example, the push engine326can continually or selectively examine instructions in a queue to determine the next consumer of a block of data. The queue could be implemented, for example, as an instruction pipeline, a data queue, a linked list, or a register that stores computer executable instructions. The push engine326can determine the next consumer of a block of data associated with an instruction in the queue that has not yet been execute. The push engine and the examination of the instruction could implemented in conjunction with the execution of one or more instructions associated with a lock instruction structure. For example, the push engine can be implemented as opcode that is executed at or near the end of the lock instruction structure such as, for example, during an unlock (or lock freeing) operation. As is known lock instruction could, for example, prevent processors other than the processor executing the lock instruction from accessing the particular block of data.

The determination by the push engine326of the next consumer of the block of data could be implemented in a number of different ways, such as discussed with respect toFIGS. 4 and 5. Additionally, the push engine326can determine at least one target memory associated with the next consumer. The at least one target memory could be implemented, for example, as local or shared cache associated with the next consumer, such as in the case of the next consumer being implemented as a processor. As an example, if the next consumer is implemented as one of the processor cores308, the at least one target memory could be implemented as one or more of the local caches (L1, L2 and L3)310,312and314associated with the respective processor core308. Additionally or alternatively, the at least one target memory could include the L4 shared cache318accessible by all of the processor cores308. Additionally or alternatively, the at least one target memory could be a memory bank associated with the next consumer, such as in the case of the next consumer being implemented as an I/O controller or an I/O device.

Additionally, the push engine326(e.g., running as opcode) could identify a source node and cache level that stores a coherent copy of the block of data. The push engine326, for example, can identify the source node by querying a coherency directory in the system300, such as if a directory based coherency protocol is implemented. As yet another example, the source node could be identified via a snoop instruction, for example, if the system300implements a non-directory based cache coherency protocol. The source node could be implemented, for example, as one of the processors308and the processor's associated caches310,312,314. For instance, the coherent copy of the block of data could be stored in one or more lines of cache of an associated cache of the source node.

After the source and at least one target memory for the block of data are ascertained by the push engine326, the push engine326causes (e.g., by a push instruction) the source processor to push the coherent copy of the block data to the at least one target memory. The data can be provided as pushed data having a unique identifier that enable s the destination to receive and store the block of data in the target memory in the absence of issuing a request for the block of data.

In one example, the push engine326can provide information to the source node that indicates a particular cache level (e.g., L1, L2, or L3) associated with the next consumer to which the coherent copy of the block of data is to be pushed.

Additionally or alternatively, the push engine326could provide information to the source node that indicates a maximum cache level in the cache hierarchy to which the block of data is to be pushed (e.g., maximum proximity to the next consumer). The maximum cache level could be, for example, a cache level lower than a coherency directory, such as could be provided in a system that implements a directory based coherency protocol. Accordingly, the consumer receiving the pushed block of data can store the block of data in the maximum level or nay lower level of cache in the processor's cache hierarchy.

As a further example, the source node and/or the next consumer could determine the appropriate level of cache to which the block of data is pushed, for example, by examining the size (e.g., number of bytes) of the coherent copy of the block data. For instance, the L1 cache310could have a smaller storage space than the L3 cache314, etc. If the block of data is sufficiently large, the block of data could exceed the maximum size of a particular cache level, and as such, the block of data could be written to a cache level that has sufficient size to store the block of data (e.g., a higher cache level).

If the source node determines that the coherent copy of the block of data is stored in the L4 shared cache318, the source node or the push engine could be configured to ignore the push, since the next consumer could access the L4 shared cache318without requesting the block of data associated with the examined instruction form the source node. Alternatively, the source node could still push the block of data to a lower lever of cache in the cache hierarchy so that the data will end up in a cache level more proximate to the next consumer.

Ownership of the coherent copy of the data may be transferred to the consumer to which the block of data is pushed (see, e.g.,FIG. 2). Alternatively, the source node could change the one or more cache lines that store the coherent copy of the block data from the ‘E’ state the ‘M’ state to a shared state (‘S’ state), which indicates that more than one cache stores a coherent copy of the block of data. It is to be understood that the particular coherency states of the block of data can vary based on the coherency protocol being implemented. One skilled in the art will appreciate the multiple of possible implementations for transferring ownership of the block of data.

In conjunction with the source node pushing the coherent copy of the block of data to the at least one target memory, the source node can perform a data writeback to the memory controller320. The memory controller320can store the coherent copy of the data to the system memory324. As an example, the writeback can be performed by the source node if the one or more cache lines that store the coherent copy of the data is/are in the ‘E’ state or ‘M’ state. The data writeback can ensure that the system memory324receives a copy of the block of data. Additionally or alternatively, the next consumer may also perform a data writeback of the coherent copy of the block of data to the memory controller320. It is to be understood and appreciated that, although the present example utilizes coherency states of the MESI protocol, the particular coherency states can vary based on the coherency protocol implemented. One skilled in the art will appreciate the possible implementations of a writeback of the block of data.

When the next consumer executes instructions that employ the block of data (e.g., the examined instruction), typically, the next consumer can search local and shared memory structures (e.g., local and shared caches310,312,314,318) that are associated with such next consumer. Since the block of data has been pushed to a more local or shared memory structure(s), the next consumer can receive a “cache hit” for the pushed data. Thus, the next consumer can execute the instruction that employs the block of data without requesting the block of data from another node, thus reducing latency of the next consumer accessing the block of data. It is to be understood that the next consumer need not actually employ the block of data for the present system to be implemented. As an alternative example, the next consumer could evict the block of data from the at least one target memory, or simply never execute the examined instructions.

FIG. 4illustrates an example approach for implementing a push engine400. The push engine400could be executed on or more processor cores, such as shown and described with respect toFIGS. 1-3. The push engine400can interact with an operating system402executing on a system. It is to be understood that the operating system402could be executed on one or more of the processor cores. The operating system402can, for example, control operations of one or more of the cells (e.g., cells302and304illustrated inFIG. 3). The operating system402can include an instruction queue404. The instruction queue404could be implemented as an instruction pipeline, a data queue, a linked list, a data register or other memory structure. The instruction queue404can include, for example, INSTRUCTION1through INSTRUCTION M, where each instruction can be implemented as a computer executable instruction, where M is an integer grater than or equal to one. In the present example, the instruction queue404stores instructions that have not yet been executed by one of the processor cores308. In such an example, an instruction can be removed from the instruction queue404after the instruction has been executed by one of the processor cores308.

Each of the M number of instructions can include an associated PROCESSOR ID, the PROCESSOR ID identifying a processor that is associated with the corresponding instruction. The PROCESSOR ID could be implemented, for example, as an argument of the corresponding instruction, or as a data field. In the present example, the PROCESSOR ID can indicate the particular processor that will execute the instruction, however one skilled in the art will appreciate that other implementations of the instruction queue404are possible.

The push engine400can include a PROCESSOR ID that identifies the particular processor that executes the one or more instructions associated with the push engine400. As an example, the push engine400includes N line of push engine instructions, where N is an integer greater than or equal to one. Each instruction could include, for example, an opcode (e.g., and operator) indicated at P.E. OPCODE1through P.E. OPCODE N and an associated operand, indicated at OPERAND1through OPERAND N. Each operand could identify, for example, a block of data on which the corresponding line of opcode operates.

As an example, the push engine400can be configured to query the instruction queue404to determine a PROCESSOR ID associated with a particular instruction. The particular implementation of the query can vary based on the implementation of the instruction queue. As one example, the push engine400can access and examine an instruction (“the examined instruction”) and the associated PROCESSOR ID. The examined instruction could be, for example, a top most instruction of the instruction queue404. From the PROCESSOR ID associated with the examined instruction, the push engine400can be configured to identify the next consumer of a block of data, which block of data could be an operand associated with the examined instruction. By way of example, the opcode associated with the push engine400can be implemented as one or more instructions, such as instructions for implementing a locking mechanism or other concurrency control mechanism. Thus, the push engine400can employ the information in the instruction queue404to determine the next consumer of the block of data.

FIG. 5illustrates another approach for implementing a push engine500. The push engine500could be executing on or more processor cores. The push engine500can interact with an operating system502executing on a system, such as could be executed on one or more of the processor cores. The operating system502can, for example, control operations of one or more of cells (e.g., cells302and304illustrated inFIG. 3). The operating system502can include a process table504. The process table504could be implemented as an instruction pipeline, a data queue, a linked list, a data register or other data structure. The process table504can include, for example, PROCESS1through PROCESS K, where each process can be implemented as one or more computer instructions (e.g., a thread) executing on a processor, where K is an integer greater than or equal to one.

Each process (PROCESS1-PROCESS K) can include an associated PROCESSOR ID, the PROCESS ID identifying a processor that is associated with the corresponding process. The processor could be the processor that currently executes computer instructions associated with the process. The PROCESSOR ID could be implemented, for example, as a data field or data flag. In the present example, the PROCESSOR ID can indicate the particular processor that is and/or will execute program instructions associated with the corresponding process.

The path engine500can include a PROCESSOR ID that identifies the particular processor that executes the one or more instructions associated with the push engine500. As an example, the push engine500includes L lines of push engine instructions, where L is an integer greater than or equal to one. Each instruction could include, for example, an opcode (e.g., an operator) indicated at P.E. OPCODE1through P.E. OPCODE L and an associated operand, indicated at OPERAND1through OPERAND L. Each operand could identify, for example, data on which the corresponding line of opcode operates.

As an example, the P.E. OPCODE can be configured to query the process table504to determine a PROCESSOR ID of the next consumer of a block of data. The particular implementation of the query can vary based on the implementation of the process table504. As one example, the push engine500(via the P.E. OPCODE) could provide the process table504with an identification of a block of data, and the process table505or associated hardware and/or software (not shown) could parse the process table504for an instruction that employs the identified block of data. The process table504could then identify the process that is associated with the instruction (e.g., one of PROCESS1-PROCESS K). Accordingly, the process table504could provide the PROCESS ID associated with the process that is associated with the instruction that employs the identified block of data. From the PROCESSOR ID provided by the process table504, the push engine500can be configured to identify the next consumer of the block of data. By way of example, opcode associated with the push engine500can be implemented as one or more instructions associated with one or more other instructions, such as a locking mechanism. Thusly, the push engine500can determine the next consumer of the block of data.

FIGS. 6 and 7illustrate examples of methods that can be employed to push data to next consumer. It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions. Moreover, not all illustrated features may be required to implement a process. The methods ofFIGS. 6 and 7could be implemented, for example, as a process (e.g., one or more lines of computer executable instructions, such as opcode) that is executed by a processor.

FIG. 6illustrates a flow chart of a method. At600, the method determined a next consumer of a block of data in the absence of detecting a request for the block of data from the next consumer. At610, a coherent copy of the block of data is pushed from a source node to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

FIG. 7illustrates a flowchart of another method for pushing data. At700, a push engine examines in instruction (“the examined instruction”). The instruction could be examined, for example, during the execution of one or more instructions associated with a lock instruction structure. The examined instruction could be the next instruction to be executed in an instruction queue. The instruction queue could be implemented, for example, as a processor pipeline, a data queue, a linked list, a data register or other memory structure. The process proceeds to710.

At710, the push engine identifies a next consumer of data associated with the examined instruction. The data could be implemented, for example, as one or more cache lines of data. The next consumer could be, for example, a processor or I/O device that is associated with one or more memory banks, such a cache or a local memory bank. The next consumer could be identified, for example, by the examined instruction, such as by an argument of the examined instruction. Alternatively, the next consumer could be identified by an OS process table that identifies processors and/or I/O devices that are associated with a particular thread, the examined instruction being associated with a thread. The process proceeds to720. At720, a source of the data associated with the examined instruction is identified. The source of the data could be a location of memory (e.g. a memory address) that stores a coherent copy of the data. As an example, the source of the data could be a local cache of a processor. The source of the data could be identified via snooping, or additionally or alternatively, the source of the data could be identified using a directory, such as a coherency directory in a system that employs a directory based coherency protocol, such as the MESI protocol.

At730, the push engine instructs the source of the data to push the data to a memory location associated with the next consumer. The memory location could be implemented as a cache associated with the next consumer, for example, if the next consumer is implemented as a processor. Alternatively, the memory location could be implemented as a RAM (e.g., static RAM or dynamic RAM) associated with the next consumer if, for example, the next consumer is implemented as an I/O device, such as a GPU or non-volatile memory storage controller. Additionally, the push engine could be configured to also include information that identifies a particular level of proximity to which the data is to be pushed. For example, the push engine could specify a cache level to which the source of the data is to push the data, if the next consumer is implemented as a processor with an associated cache. Additionally or alternatively, the push engine could specify a maximum level of cache to which the data is to be pushed, such as a level of cache lower than a cache directory, for example, if a system implements a directory based coherency protocol. Alternatively, the push engine could instruct the source of the data to push the data to a shared memory structure. The shared memory structure could be implemented as a memory structure that is accessible to the next consumer (e.g., a shared cache). The process proceeds to740.

At740, the source of the data pushes the data to the memory location associated with the next consumer. In one example, the source of the data could determine the particular cache level of proximity to which the data is to be pushed. The determination of the level of proximity could vary based on the size of the data. The process proceeds to750.

At750, the next consumer of the data executes the examined instruction. Typically, when executing the examined instruction, the next consumer can look to a local memory (e.g., a local cache) for the data associated with the examined instruction. In the present process, since the data has been pushed to a local memory of the next consumer, the next consumer can find the data in the local memory and can executed the examined instruction without needing to request the data from another source. This is as if the source core caused the data to be prefetched on behalf of the consumer, such as may correspond to a separate core or I/O. This approach is particularly useful in concurrency control applications, such as locking of data structures or message passing.