MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND FABRICATING METHODS THEREOF

Three-dimensional (3D) semiconductor devices and fabricating methods are disclosed. The semiconductor device includes an array of vertical transistors. Each vertical transistor includes a semiconductor body extending in a vertical direction, and an all-around gate structure laterally surrounding the semiconductor body. Each row of the vertical transistors in a first lateral direction share a common word line extending in the first lateral direction and comprising the all-around gate structures of the row of the vertical transistors. Adjacent rows of the vertical transistors are misaligned along a second lateral direction perpendicular with the first lateral direction. The array of vertical transistors are aligned along a third lateral direction different from the first lateral direction and the second lateral direction.

TECHNICAL FIELD

The present disclosure generally relates to the field of semiconductor technology, and more particularly, to memory devices and fabrication methods thereof.

BACKGROUND

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array.

SUMMARY

In one implementation, a semiconductor device, comprising: an array of vertical transistors each comprising: a semiconductor body extending in a vertical direction, and an all-around gate structure laterally surrounding the semiconductor body; wherein each row of the vertical transistors in a first lateral direction share a common word line extending in the first lateral direction and comprising the all-around gate structures of the row of the vertical transistors, and adjacent rows of the vertical transistors are misaligned along a second lateral direction perpendicular with the first lateral direction.

In one implementation, the array of vertical transistors are aligned along a third lateral direction different from the first lateral direction and the second lateral direction.

In one implementation, a lateral cross section of the semiconductor body has a longitudinal axis along the third lateral direction.

In one implementation, the lateral cross section of the semiconductor body has an oval-like shape.

In one implementation, the lateral cross section of the semiconductor body has rounded corners.

In one implementation, the semiconductor device further comprises: a plurality of spacers each extending along the first lateral direction between rows of the vertical transistors to separate adjacent word lines.

In one implementation, the plurality of spacers comprise: a plurality of first spacers and second spacers alternatively arranged along the second lateral direction, a first depth of the first spacers is greater than a second depth of the second spacers.

In one implementation, two adjacent vertical transistors along the third lateral direction and separated by one second spacer share a common source/drain at a joint first end of the semiconductor bodies of the two adjacent vertical transistors and connected to a bit line extending along the second lateral direction; and two adjacent vertical transistors along the third lateral direction and separated by one first spacer are connected to adjacent two bit lines, respectively.

In one implementation, each vertical transistor further comprises: a gate dielectric layer between the all-around gate structure and the semiconductor body.

In one implementation, the semiconductor device further comprises: an array of memory cells, each memory cell comprising: one of the array of vertical transistors; and a capacitor in electrical connection with a separated source/drain at a second end of the one of the array of vertical transistors, wherein the first end is opposite to the joint first end.

In one implementation, a method of forming a semiconductor device comprises: forming an array of semiconductor bodies comprising rows of semiconductor bodies aligned along a first lateral direction, wherein adjacent rows of semiconductor bodies are misaligned along a second lateral direction perpendicular to the first lateral direction, and the array of semiconductor bodies are also aligned along a third lateral direction different from the first lateral direction and the second lateral direction; forming a conductive structure laterally surrounding each of the array of semiconductor bodies; and forming a plurality of spacers each extending along the first lateral direction to separate adjacent rows of the semiconductor bodies.

In one implementation, forming the array of semiconductor bodies comprises: forming a plurality of third trenches in a semiconductor layer each extending along the third lateral direction; and forming a plurality of first trenches and second trenches in the semiconductor layer each extending along the first lateral direction, wherein the plurality of first trenches and second trenches are alternatively arranged along the second lateral direction, a first depth of the first trenches is greater than a second depth of the second trenches.

In one implementation, forming the array of semiconductor bodies further comprises: removing portions each of the array of semiconductor bodies to make each semiconductor body having a curved sidewall.

In one implementation, forming the array of semiconductor bodies further comprises: removing portions each of the array of semiconductor pillars to make a lateral cross section of each semiconductor body having an oval-like shape with a longitudinal axis along the third lateral direction.

In one implementation, forming the plurality of conductive structures comprises: forming a gate dielectric layer on a sidewall of each of the array of semiconductor bodies; forming a lower trench isolation structure on a bottom of the plurality of first trenches, second trenches, and third trenches; and forming the conductive structure to laterally surround the gate dielectric layer on the sidewall of each of the array of semiconductor bodies.

In one implementation, forming the plurality of spacers comprises: forming a plurality of first spacers in the first trenches; and forming a plurality of second spacers in the second trenches; wherein the conductive structure is separated by the plurality of first and second spacers into a plurality of all-round gate structure each extending along the first lateral direction and surrounding each of a corresponding row of the semiconductor bodies.

In one implementation, the method further comprises: removing an upper portions of the conductive structure; forming a filling dielectric structure above the conductive structure; forming a first doped region at a first end of each semiconductor body; forming a capacitor in electrical connection with the first doped region.

In one implementation, the method further comprises: thinning the semiconductor layer, such that two adjacent semiconductor bodies next to one first spacer is separated while a pair of semiconductor bodies next to one second spacer is connected at a connected second end of the pair of semiconductor bodies; forming a common second doped region at the connected second end of the pair of semiconductor bodies; and forming a bit line in electrical connection with the common second doped region.

In one implementation, a memory system comprises: a memory device comprising an array of memory cells, each memory cell comprising: a capacitor, and a vertical transistor comprising: a semiconductor body extending in a vertical direction, and an all-around gate structure laterally surrounding the semiconductor body; wherein each row of the vertical transistors in a first lateral direction share a common word line extending in the first lateral direction and comprising the plurality of all-around gate structures of the row of the vertical transistors, and adjacent rows of vertical transistors are misaligned along a second lateral direction perpendicular with the first lateral direction; and a memory controller configured to control the memory device.

In one implementation, a lateral cross section of the semiconductor body has an oval shape with a longitudinal axis along a third lateral direction different from the first lateral direction and the second lateral direction; and the array of vertical transistors are aligned along the third lateral direction.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

Transistors are used as the switch or selecting devices in the memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM). However, the planar transistors commonly used in existing memory cells usually have a horizontal structure with buried word lines in the substrate and bit lines above the substrate. Since the source and drain of a planar transistor are disposed laterally at different locations, which increases the area occupied by the transistor. The design of planar transistors also complicates the arrangement of interconnected structures, such as word lines and bit lines, coupled to the memory cells, for example, limiting the pitches of the word lines and/or bit lines, thereby increasing the fabrication complexity and reducing the production yield. Moreover, because the bit lines and the storage units (e.g., capacitors or PCM elements) are arranged on the same side of the planar transistors (above the transistors and substrate), the bit line process margin is limited by the storage units, and the coupling capacitance between the bit lines and storage units, such as capacitors, are increased. Planar transistors may also suffer from a high leakage current as the saturated drain current keeps increasing, which is undesirable for the performance of memory devices.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which vertical transistors replace the conventional planar transistors as the switch and selecting devices in a memory cell array of memory devices (e.g., DRAM, PCM, and FRAM). In the following descriptions, DRAM is used as a non-exclusive example of the present disclosure. Compared with planar transistors, the vertically arranged transistors (i.e., the drain and source are overlapped in the plan view) can reduce the area of the transistor as well as simplify the layout of the interconnect structures, e.g., metal wiring the word lines and bit lines, which can reduce the fabrication complexity and improve the yield. For example, the pitches of word lines and/or bit lines can be reduced for ease of fabrication. The vertical structures of the transistors also allow the bit lines and storage units, such as capacitors, to be arranged on opposite sides of the transistors in the vertical direction (e.g., one above and one below the transistors), such that the process margin of the bit lines can be increased and the coupling capacitance between the bit lines and the storage units can be decreased.

Consistent with the scope of the present disclosure, according to some implementations of the present disclosure, the memory cell array having vertical transistors each comprising a semiconductor body extending in a vertical direction, and a gate structure beside the semiconductor structure. In some implementations, the word lines and bit lines connected to the vertical transistors are arranged along a first lateral direction and a second direction, respectively. The semiconductor bodies of the array of vertical transistors are aligned along a third lateral direction different from the first and second lateral directions. By using such an arrangement, memory area efficiency can be increased. Further, the memory cell array and the peripheral circuits can be formed separately on different wafers, such that the fabricating processes of the memory cell array and the peripheral circuits do not affect each other, and the memory area efficiency can be further increased.

FIG.1illustrates a schematic diagram of an exemplary memory device100having an array of memory cells each having a vertical transistor, according to some implementations of the present disclosure. Memory device100can include a memory cell array in which each memory cell110includes a vertical transistor120and a storage unit coupled to vertical transistor120. In some implementations as shown inFIG.1, the memory cell array is a DRAM cell array, and the storage unit is a capacitor130for storing charge as the binary information stored by the respective DRAM cell. In some other implementations not shown in the figures, the memory cell array is a PCM cell array, and the storage unit can be a PCM element (e.g., including chalcogenide alloys) for storing binary information of the respective PCM cell based on the different resistivities of the PCM element in the amorphous phase and the crystalline phase. In some implementations not shown in the figures, the memory cell array is a FRAM cell array, and the storage unit can be a ferroelectric capacitor for storing binary information of the respective FRAM cell based on the switch between two polarization states of ferroelectric materials under an external electric field.

As shown inFIG.1, memory cells110can be arranged in a two-dimensional (2D) array having rows and columns. Memory device100can include word lines150coupling the memory cell array to peripheral circuits for controlling the switch of vertical transistors120in memory cells110located in a row, as well as bit lines160coupling the memory cell array to peripheral circuits for sending data to and/or receiving data from memory cells110located in a column. That is, each word line150is coupled to a respective row of memory cells110, and each bit line160is coupled to one or more respective logic columns of memory cells110. In some implementations, the gate of vertical transistor120is coupled to word line150, one of the source and the drain of vertical transistor120is coupled to bit line160, the other one of the source and the drain of vertical transistor120is coupled to one electrode of capacitor130, and the other electrode of capacitor130is coupled to the ground.

Consistent with the scope of the present disclosure, vertical transistors120, such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs), can replace the conventional planar transistors as the pass transistors of memory cells110to reduce the area occupied by the pass transistors, the coupling capacitance, as well as the interconnect routing complexity, as described below in detail.

FIGS.2A-2Ceach illustrates a schematic plan view of an array of memory cells each including a vertical transistor in an exemplary memory device, according to various implementations of the present disclosure. As shown inFIGS.2A-2C, memory device200A/200B/200C can include a plurality of word lines250each extending in a first lateral direction (the x-direction, referred to as the word line direction). Memory device200A/200B/200C can also include a plurality of bit lines260each extending in a second lateral direction perpendicular to the first lateral direction (the y-direction, referred to as the bit line direction). It is understood thatFIGS.2A-2Cdo not illustrate cross-section views of memory device200A/200B/200C in the same lateral plane, and word lines250and bit lines260may be formed in different lateral planes for ease of routing as described below in detail.

In some implementations, each memory cell210includes a storage unit and a vertical transistor220having a semiconductor body222and a gate structure225. Each row of vertical transistors220are aligned along a first lateral direction (i.e., x-direction), and the gate structures225of each row of vertical transistors220are connected with each other to form a word line250extending along the first lateral direction. In some implementations, the bit lines260extend in parallel along a second lateral direction (i.e., y-direction) and are connected with the vertical transistors220. In some implementations, the array of vertical transistors220are also aligned along a third lateral direction (i.e., w-direction) different from the first and second lateral direction. Two adjacent vertical transistors220along the third lateral direction can share a common source/drain, which is connected to a corresponding bit line260, and can be referred to as a pair of vertical transistors220. The two adjacent memory cells210including the pair of vertical transistors220sharing a same bit line260can be referred to a pair of memory cells210.FIG.2Dillustrates a schematic side view of a cross-section of a pair of memory cells210in each of the 3D memory devices, as shown inFIGS.2A-2C, according to some implementations of the present disclosure. It is noted thatFIG.2Dillustrates a cross-sectional side view of BB′ line of a pair of memory cells210inFIGS.2A-2Calong the third lateral direction, and some components shown inFIG.2Dare omitted inFIGS.2A-2C.

Referring toFIGS.2A-2D, semiconductor body222can extend in the vertical direction (i.e., z-direction) perpendicular to the first, second, and third lateral directions. Different from planar transistors in which the active regions are formed in the substrates, vertical transistor220includes a semiconductor body222extending vertically (in the z-direction). It is understood that semiconductor body222may have any suitable 3D shape, such as polyhedron shapes or a cylinder shape. That is, the cross-section of semiconductor body222in the plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, a partial circular shape, an oval shape, a partial oval shape, or any other suitable shapes.

In a first example as shown inFIG.2A, the cross-section of two semiconductor bodies222of a pair of vertical transistors220(included by dotted lines) can be portions of a rectangle-like shape with a longitudinal axis along the third lateral direction (w-direction) and with rounded corners. In some implementations, semiconductor bodies222between adjacent pairs of vertical transistors220along the second lateral direction (y-direction) can be laterally separated by a first spacer270, and the two semiconductor bodies222within a pair of vertical transistors220can be laterally separated by a second spacer280. The plurality of first spacers270and second spacers280extend in parallel along the first lateral direction, and are alternatively arranged along the second lateral direction.

In some implementations, each vertical transistor220can also include a gate structure225located at one side of the semiconductor body222. The gate structure225of adjacent vertical transistors220in the first lateral direction (i.e., the word line direction or the x-direction) are continuous, e.g., parts of a continuous conductive layer having the gate structures225. That is, multiple gate structures225of a row (e.g.,211-214) of vertical transistors220can be connected with each other and extending along the first lateral direction to form a word line250of the row of vertical transistors220.

The two word lines250of two adjacent rows of vertical transistors220that form pairs of vertical transistors can be embedded in a same second spacer280separating the two adjacent rows of vertical transistors220, as shown inFIG.2A. Gate structures225can include any suitable conductive materials, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, gate structures225may include doped polysilicon, i.e., a gate poly. In some implementations, gate structures225includes multiple conductive layers, such as a W layer over a TiN layer. In some implementations, a gate dielectric224is laterally between the gate structure225and the semiconductor body222. Gate dielectric224can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. For example, gate dielectric224may include silicon oxide, i.e., gate oxide.

In some implementations, the plurality of first spacers270and second spacers280can include any suitable dielectric material, such as silicon oxide. In some implementations, each of the plurality of first spacers270and second spacers280can further include one or more air gaps (not shown) embedded in the dielectric material. As described below with respect to the fabrication process, the air gaps may be formed due to the relatively small pitches of word lines250(and rows of memory cells210) along the second lateral direction. On the other hand, the relatively large dielectric constant of air in air gaps (e.g., about 4 times the dielectric constant of silicon oxide) can improve the insulation effect between word lines250(and rows of memory cells210) compared with some dielectrics (e.g., silicon oxide).

In a second example as shown inFIG.2B, the cross-section of two semiconductor bodies222of a pair of vertical transistors220(included by dotted lines) can be portions of an oval-like shape with a longitudinal axis along the third lateral direction (w-direction). In some implementations, semiconductor bodies222between adjacent pairs of vertical transistors220along the second lateral direction (y-direction) can be laterally separated by a first spacer270, and the two semiconductor bodies222within a pair of vertical transistors220can be laterally separated by a second spacer280. The plurality of first spacers270and second spacers280extend in parallel along the first lateral direction, and are alternatively arranged along the second lateral direction. That is, each semiconductor body222can include a flat sidewall facing the second spacer280and a curved sidewall facing the first spacer270.

In some implementations, the gate structure225of each vertical transistor220is located beside the flat sidewall of the semiconductor body222. The gate structures225of each row of vertical transistors220along the first lateral direction (x-direction) are connected with each other and form a word line250extending along the first lateral direction. The two word lines250of two adjacent rows of vertical transistors220that form pairs of vertical transistors can be embedded in a same second spacer280separating the two adjacent rows of vertical transistors220, as shown inFIG.2B. In some implementations, a gate dielectric224is laterally between the gate structure225and the flat sidewall of the semiconductor body222.

In a third example as shown inFIG.2C, the cross-section of two semiconductor bodies222of two adjacent vertical transistors220separated by a second spacer280can be portions of an oval-like shape with a longitudinal axis along the third lateral direction (w-direction). In some implementations, adjacent vertical transistors220in the second lateral direction separated by a first spacer270can form a pair of vertical transistors (included in the dotted lines) sharing a common source/drain. The plurality of first spacers270and second spacers280extend in parallel along the first lateral direction, and are alternatively arranged along the second lateral direction.

As shown inFIG.2C, the plurality of first spacers270and second spacers280are alternatively arranged along the second lateral direction. Each first spacer270is located between the curved sidewalls of the semiconductor bodies222of two adjacent rows of vertical transistors220. Each second spacer280is located between the flat sidewalls of the semiconductor bodies222of two adjacent rows of vertical transistors220. That is, each semiconductor body222can include a flat sidewall facing the second spacer280and a curved sidewall facing the first spacer270.

In some implementations, the gate structure225of each vertical transistor220can surround multiple sides of semiconductor body222, i.e., surrounding the active region in which channels are formed from multiple lateral directions. In other words, the active region of vertical transistor220, i.e., semiconductor body222, can be at least partially surrounded by gate structure225. For example, as shown inFIG.2C, the vertical transistor can be a three-sided gate transistor in which gate structure225surrounds semiconductor body222from three lateral directions. The three-sided gate structure225can surround the curved sidewall of the semiconductor body222. Thus, a larger active channel region can be formed between the source and drain in operation to generate a larger gate control area for achieving better channel control with a smaller subthreshold swing. During the off state, since the channel is fully depleted, the leakage current (Ioff) of vertical transistor220can be significantly reduced.

As shown inFIG.2C, the three-sided gate structure225of adjacent vertical transistors220in the first lateral direction (i.e., the word line direction or the x-direction) are continuous, e.g., parts of a continuous conductive layer having three-sided gate structure225. That is, multiple three-sided gate structures225of a row (e.g.,211-216) of vertical transistors220can be connected with each other and extending along the first lateral direction to form a word line250of the row of vertical transistors220. In some implementations, a gate dielectric224is laterally between the three-sided gate structure225and the curved sidewall of the semiconductor body222. The gate dielectrics224of adjacent vertical transistors220in the word line direction are separate, e.g., not parts of a continuous dielectric layer having gate dielectrics224.

As shown inFIGS.2A-2C, in some implementations, the semiconductor bodies222are aligned along the third lateral direction (w-direction) with non-zero angles with respect to the first lateral direction and the second lateral direction. As described in detail with the fabricating processed below, the semiconductor bodies222of a pair of vertical transistors220can be portions of a semiconductor pillar separated by a second spacer280. The semiconductor pillar can have a rectangular-like shape or an oval shape with a longitudinal axis along the third lateral direction.

In some implementations, a first angle between the first lateral direction (x-direction) and the third lateral direction (w-direction), as well as a second angle between the second lateral direction (y-direction) and the third lateral direction (w-direction), can be determined by a first distance between adjacent bit lines260and a second distance between adjacent word lines250. Specifically, a cotangent function of the first angle, or a tangent function of the second angle, can be approximately proportional to a first distance between adjacent bit lines, and reversely proportional to a double value of a second distance between adjacent word lines.

By aligning the semiconductor bodies222along the third lateral direction different from the first and second lateral direction, the first distance between adjacent bit lines260and the second distance between adjacent word lines250can be reduced to increase memory area inefficiencies. For example, when the first distance decreases by about 30%, the second angle can be about 25°, and the memory area can be reduced by about 25% to contain a same number of memory cells210. As another example, when the first distance decreases by about 50%, the second angle can be about 22°, and the memory area can be reduced by about 30% to contain a same number of memory cells210.

Referring toFIG.2D, a schematic side view of a cross-section of a pair of memory cells210is shown according to some implementations of the present disclosure. It is noted that, the cross-section200D can be a pair of memory cells210in any one of the 3D memory devices200A,200B, and200C as shown inFIGS.2A-2C. It is also noted that, the cross-section200D is a vertical plane along the third lateral direction (the BB′ line inFIGS.2A-2C) and the vertical direction (z-direction). In the third lateral direction, the gate structures225of a pair of vertical transistors220are located between the two semiconductor bodies222, and are separated by first spacer270or second spacer280with one or more air gaps embedded therein.

As shown inFIG.2D, each vertical transistor220can include a pair of a source and a drain227,228(S/D, dope regions, a.k.a., source electrode and drain electrode) formed at the two ends of semiconductor body222in the vertical direction (the z-direction), respectively. The source and drain227,228can be doped with any suitable P-type dopants, such as boron (B) or Gallium (Ga), or any suitable N-type dopants, such as phosphorus (P) or arsenic (As). In each vertical transistor220, the source and drain227,228can be separated at two ends of the semiconductor body222in the vertical direction (the z-direction). Gate structure225is formed vertically corresponding to the portion of the semiconductor body222between the source and drain227,228. As a result, the channel of the vertical transistor220can be formed in semiconductor body222vertically between the source and drain227,228when a gate voltage applied to the gate structure225is above the threshold voltage of the vertical transistor220.

As shown inFIG.2D, a pair of vertical transistors220can have separated sources/drains228connected to a storage unit (e.g., a capacitor290) through a storage unit contact298, and can also have a common source/drain227connected to a bit line260through a bit line contact296. It is noted that the storage unit can include any devices that are capable of storing binary data (e.g., 0 and 1), including but not limited to, capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some implementations, each vertical transistor220controls the selection and/or the state switch of the respective storage unit coupled to vertical transistor220.

In some implementations as shown inFIG.2D, the storage unit is a capacitor290including a first electrode (not shown) coupled with the source/drain228of vertical transistor220. Capacitor290can also include a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. That is, capacitor290can be a vertical capacitor in which two electrodes and the capacitor dielectric in between are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the two electrodes. In some implementations, each first electrode can be coupled to the source/drain228of a respective vertical transistor220in the same DRAM cell, while all second electrodes can be parts of a common plate coupled to the ground, e.g., a common ground. In some implementations, the capacitor dielectric includes dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectrics including, but not limited to, Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some implementations, the two electrodes can include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof.

It is understood that the capacitor290may include any suitable structure and configuration, such as a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor. That is, capacitor290can be a vertical capacitor in which two electrodes and the capacitor dielectric in between are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the two electrodes. In some implementations, each first electrode can be coupled to the source/drain228of a respective vertical transistor220in the same DRAM cell, while all second electrodes can be parts of a common plate coupled to the ground, e.g., a common ground.

In some implementations, one or more peripheral circuits (not shown) can be coupled to the memory cell array shown in200A/200B/200C through bit lines260, word lines250, and any other suitable metal wirings. It is noted that the one or more peripheral circuits can include any suitable circuits for facilitating the operations of memory cell array200A/200B/200C by applying and sensing voltage signals and/or current signals through word lines250and bit lines260to and from each memory cell210. The one or more peripheral circuits can include various types of peripheral circuits formed using CMOS technologies.

FIGS.3A-3Beach illustrates a schematic plan view of an array of memory cells each including a vertical transistor in an exemplary memory device, according to various implementations of the present disclosure.FIG.3Cillustrates a schematic side view of a cross-section of a pair of memory cells210along the BB′ line ofFIG.3A or3B, according to some implementations of the present disclosure.

In a fourth example as shown inFIG.3A, the cross-section of two semiconductor bodies222of a pair of vertical transistors220(included in the dotted lines) separated by a second spacer280can be portions of an oval-like shape with a longitudinal axis along the third lateral direction (w-direction). In some implementations, adjacent pairs of vertical transistors220can be separated by a first spacer270in the second lateral direction. The plurality of first spacers270and second spacers280extend in parallel along the first lateral direction, and are alternatively arranged along the second lateral direction.

As shown inFIG.3A, the plurality of first spacers270and second spacers280are alternatively arranged along the second lateral direction. Each first spacer270is located between the curved sidewalls of the semiconductor bodies222of two adjacent rows of vertical transistors220. Each second spacer280is located between the flat sidewalls of the semiconductor bodies222of two adjacent rows of vertical transistors220. That is, each semiconductor body222can include a flat sidewall facing the second spacer280and a curved sidewall facing the first spacer270.

In some implementations, the gate structure225of each vertical transistor220can surround multiple sides of semiconductor body222, i.e., surrounding the active region in which channels are formed from multiple lateral directions. In other words, the active region of vertical transistor220, i.e., semiconductor body222, can be at least partially surrounded by gate structure225. For example, as shown inFIG.3A, the vertical transistor can be a three-sided gate transistor in which gate structure225surrounds the semiconductor body222from three lateral directions. The three-sided gate structure225can surround the curved sidewall of the semiconductor body222. Thus, a larger active channel region can be formed between the source and drain in operation to generate a larger gate control area for achieving better channel control with a smaller subthreshold swing. During the off state, since the channel is fully depleted, the leakage current (Ioff) of vertical transistor220can be significantly reduced.

As shown inFIG.3A, the three-sided gate structure225of adjacent vertical transistors220in the first lateral direction (i.e., the word line direction or the x-direction) are continuous, e.g., parts of a continuous conductive layer having three-sided gate structure225. That is, multiple three-sided gate structures225of a row (e.g.,211-216) of vertical transistors220can be connected with each other and extending along the first lateral direction to form a word line250of the row of vertical transistors220. In some implementations, a gate dielectric224is laterally between the three-sided gate structure225and the curved sidewall of the semiconductor body222. The gate dielectrics224of adjacent vertical transistors220in the word line direction are separate, e.g., not parts of a continuous dielectric layer having gate dielectrics224.

In a fifth example as shown inFIG.3B, the cross-section of two semiconductor bodies222of two adjacent vertical transistors220in the third lateral direction and laterally separated by a second spacer280can be portions of an oval-like shape with a longitudinal axis along the third lateral direction (w-direction). That is, the two semiconductor bodies222within a pair of vertical transistors220can be laterally separated by a first spacer270, and the semiconductor bodies222between adjacent pairs of vertical transistors220along the second lateral direction (y-direction) can be laterally separated by a second spacer280. The plurality of first spacers270and second spacers280extend in parallel along the first lateral direction, and are alternatively arranged along the second lateral direction. That is, each semiconductor body222can include a flat sidewall facing the second spacer280and a curved sidewall facing the first spacer270.

In some implementations, the gate structure225of each vertical transistor220is located beside the flat sidewall of the semiconductor body222. The gate structures225of each row of vertical transistors220along the first lateral direction (x-direction) are connected with each other and form a word line250extending along the first lateral direction. The two word lines250of two adjacent rows of vertical transistors220that form pairs of vertical transistors can be embedded in a same second spacer280separating the two adjacent rows of vertical transistors220, as shown inFIG.3B. In some implementations, a gate dielectric224is laterally between the gate structure225and the flat sidewall of the semiconductor body222.

In some implementations as shown inFIGS.3A-3B, the semiconductor bodies222are aligned along the third lateral direction (w-direction) with non-zero angles in respect to the first lateral direction and the second lateral direction. As described in detail with the fabricating processed below, the semiconductor bodies222of a pair of vertical transistors220can be portions of a semiconductor pillar separated by a second spacer280. The semiconductor pillar can have a rectangular-like shape or an oval shape with a longitudinal axis along the third lateral direction.

In some implementations, a first angle between the first lateral direction (x-direction) and the third lateral direction (w-direction), as well as a second angle between the second lateral direction (y-direction) and the third lateral direction (w-direction), can be determined by a first distance between adjacent bit lines260and a second distance between adjacent word lines250. Specifically, a cotangent function of the first angle, or a tangent function of the second angle, can be approximately proportional to a first distance between adjacent bit lines, and reversely proportional to a double value of a second distance between adjacent word lines.

By aligning the semiconductor bodies222along the third lateral direction different from the first and second lateral direction, the first distance between adjacent bit lines260and the second distance between adjacent word lines250can be reduced to increase memory area inefficiencies. For example, when the first distance decreases by about 30%, the second angle can be about 25°, and the memory area can be reduced by about 25% to contain a same number of memory cells210. As another example, when the first distance decreases by about 50%, the second angle can be about 22°, and the memory area can be reduced by about 30% to contain a same number of memory cells210.

Referring toFIG.3C, a schematic side view of a cross-section of a pair of memory cells210is shown according to some implementations of the present disclosure. It is noted that, the cross-section300C can be a pair of memory cells210in any one of the 3D memory devices300A and300B, as shown inFIGS.3A-3B. It is also noted that, the cross-section300C is a vertical plane along the third lateral direction (the BB′ line inFIGS.3A-3B) and the vertical direction (z-direction). In the third lateral direction, the two semiconductor bodies222of a pair of vertical transistors220are located between the two gate structures225, and are separated by first spacer270or second spacer280with one or more air gaps embedded therein.

As shown inFIG.3C, each vertical transistor220can include a pair of a source and a drain227,228(S/D, dope regions, a.k.a., source electrode and drain electrode) formed at the two ends of semiconductor body222in the vertical direction (the z-direction), respectively. The source and drain227,228can be doped with any suitable P-type dopants, such as boron (B) or Gallium (Ga), or any suitable N-type dopants, such as phosphorus (P) or arsenic (As). In each vertical transistor220, the source and drain227,228can be separated at two ends of the semiconductor body222in the vertical direction (the z-direction). Gate structure225is formed vertically corresponding to the portion of the semiconductor body222between the source and drain227,228. As a result, the channel of the vertical transistor220can be formed in semiconductor body222vertically between the source and drain227,228when a gate voltage applied to the gate structure225is above the threshold voltage of the vertical transistor220.

As shown inFIG.3C, a pair of vertical transistors220can have separated sources/drains228connected to a storage unit (e.g., a capacitor290) through a storage unit contact298, and can also have a common source/drain227connected to a bit line260through a bit line contact296. It is noted that the storage unit can include any devices that are capable of storing binary data (e.g., 0 and 1), including but not limited to, capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some implementations, each vertical transistor220controls the selection and/or the state switch of the respective storage unit coupled to vertical transistor220.

In some implementations as shown inFIG.3C, the storage unit is a capacitor290including a first electrode (not shown) coupled with the source/drain228of vertical transistor220. Capacitor290can also include a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. That is, capacitor290can be a vertical capacitor in which two electrodes and the capacitor dielectric in between are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the two electrodes. In some implementations, each first electrode can be coupled to the source/drain228of a respective vertical transistor220in the same DRAM cell, while all second electrodes can be parts of a common plate coupled to the ground, e.g., a common ground. In some implementations, the capacitor dielectric includes dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectrics including, but not limited to, Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some implementations, the two electrodes can include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof.

It is understood that the capacitor290may include any suitable structure and configuration, such as a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor. That is, capacitor290can be a vertical capacitor in which two electrodes and the capacitor dielectric in between are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the two electrodes. In some implementations, each first electrode can be coupled to the source/drain228of a respective vertical transistor220in the same DRAM cell, while all second electrodes can be parts of a common plate coupled to the ground, e.g., a common ground.

In some implementations, one or more peripheral circuits (not shown) can be coupled to memory cell array300A/300B through bit lines260, word lines250, and any other suitable metal wirings. It is noted that the one or more peripheral circuits can include any suitable circuits for facilitating the operations of memory cell array300A/200B/200C by applying and sensing voltage signals and/or current signals through word lines250and bit lines260to and from each memory cell210. The one or more peripheral circuits can include various types of peripheral circuits formed using CMOS technologies.

FIG.4Aillustrates a schematic plan view of an array of memory cells each including a vertical transistor in an exemplary memory device, according to some implementations of the present disclosure.FIG.4Billustrates a schematic side view of a cross-section of a pair of memory cells210along the BB′ line ofFIG.4A, according to some implementations of the present disclosure.

In a sixth example as shown inFIG.4A, the cross-section of each semiconductor body222of a vertical transistor220can be an oval-like shape with a longitudinal axis along the third lateral direction (w-direction). In some implementations, a pair of vertical transistors220(included in the dotted lines) can share a common source/drain connected to a bit line260. Adjacent rows of vertical transistors220that form pairs of vertical transistors220can sandwich a first spacer270extending in parallel along the first lateral direction (x-direction). Adjacent pairs of vertical transistors220along the second lateral direction (y-direction) can be separated by a second spacer280extending in parallel along the first lateral direction. A plurality of first spacers270and second spacers280can be alternatively arranged along the second lateral direction.

In some implementations, the gate structure225of each vertical transistor220can be an all-round gate structure laterally surrounding the semiconductor body222, i.e., surrounding the active region in which a channel is formed from all lateral directions. In other words, the active region of vertical transistor220, i.e., semiconductor body222, can be entirely surrounded by the all-around gate structure225. Thus, a larger active channel region can be formed between the source and drain in operation to generate a larger gate control area for achieving better channel control with a smaller subthreshold swing. During the off state, since the channel is fully depleted, the leakage current (Ioff) of vertical transistor220can be significantly reduced. In some implementations, a gate dielectric224is laterally between the all-round gate structure225and the semiconductor body222.

In some implementations as shown inFIG.4A, the semiconductor bodies222are aligned along the third lateral direction (w-direction) with non-zero angles in respect to the first lateral direction and the second lateral direction. In some implementations, a first angle between the first lateral direction (x-direction) and the third lateral direction (w-direction) as well as a second angle between the second lateral direction (y-direction) and the third lateral direction (w′-direction) can be determined by a first distance between adjacent bit lines260and a second distance between adjacent word lines250. Specifically, a cotangent function of the first angle, or a tangent function of the second angle, can be approximately proportional to a first distance between adjacent bit lines, and reversely proportional to a double value of a second distance between adjacent word lines.

By aligning the semiconductor bodies222along the third lateral direction different from the first and second lateral direction, the first distance between adjacent bit lines260and the second distance between adjacent word lines250can be reduced to increase memory area inefficiencies. For example, when the first distance decreases by about 30%, the second angle can be about 25°, and the memory area can be reduced by about 25% to contain a same number of memory cells210. As another example, when the first distance decreases by about 50%, the second angle can be about 22°, and the memory area can be reduced by about 30% to contain a same number of memory cells210.

Referring toFIG.4B, a schematic side view of a cross-section of a pair of memory cells210of the 3D memory device400A is shown according to some implementations of the present disclosure. The cross-section400B is a vertical plane along the third lateral direction (the BB′ line inFIG.4A) and the vertical direction (z-direction). In the third lateral direction, the gate structures225are located at both sides of the two semiconductor bodies222of a pair of vertical transistors220. The pair of vertical transistors220are separated by first spacer270with one or more air gaps embedded therein.

As shown inFIG.4B, each vertical transistor220can include a pair of a source and a drain227,228(S/D, dope regions, a.k.a., source electrode and drain electrode) formed at the two ends of semiconductor body222in the vertical direction (the z-direction), respectively. The source and drain227,228can be doped with any suitable P-type dopants, such as boron (B) or Gallium (Ga), or any suitable N-type dopants, such as phosphorus (P) or arsenic (As). In each vertical transistor220, the source and drain227,228can be separated at two ends of the semiconductor body222in the vertical direction (the z-direction). Gate structure225is formed vertically corresponding to the portion of the semiconductor body222between the source and drain227,228. As a result, the channel of the vertical transistor220can be formed in semiconductor body222vertically between the source and drain227,228when a gate voltage applied to the gate structure225is above the threshold voltage of the vertical transistor220.

As shown inFIG.4B, a pair of vertical transistors220can have separated sources/drains228connected to a storage unit (e.g., a capacitor290) through a storage unit contact298, and can also have a common source/drain227connected to a bit line260through a bit line contact296. It is noted that the storage unit can include any devices that are capable of storing binary data (e.g., 0 and 1), including but not limited to, capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some implementations, each vertical transistor220controls the selection and/or the state switch of the respective storage unit coupled to vertical transistor220.

In some implementations as shown inFIG.4B, the storage unit is a capacitor290including a first electrode (not shown) coupled with the source/drain228of vertical transistor220. Capacitor290can also include a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. That is, capacitor290can be a vertical capacitor in which two electrodes and the capacitor dielectric in between are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the two electrodes. In some implementations, each first electrode can be coupled to the source/drain228of a respective vertical transistor220in the same DRAM cell, while all second electrodes can be parts of a common plate coupled to the ground, e.g., a common ground. In some implementations, the capacitor dielectric includes dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectrics including, but not limited to, Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some implementations, the two electrodes can include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof.

It is understood that the capacitor290may include any suitable structure and configuration, such as a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor. That is, capacitor290can be a vertical capacitor in which two electrodes and the capacitor dielectric in between are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the two electrodes. In some implementations, each first electrode can be coupled to the source/drain228of a respective vertical transistor220in the same DRAM cell, while all second electrodes can be parts of a common plate coupled to the ground, e.g., a common ground.

In some implementations, one or more peripheral circuits (not shown) can be coupled to memory cell array300A/300B through bit lines260, word lines250, and any other suitable metal wirings. It is noted that the one or more peripheral circuits can include any suitable circuits for facilitating the operations of memory cell array300A/200B/200C by applying and sensing voltage signals and/or current signals through word lines250and bit lines260to and from each memory cell210. The one or more peripheral circuits can include various types of peripheral circuits formed using CMOS technologies.

FIG.5illustrates a block diagram of a system500having a memory device, according to some implementations of the present disclosure. System500can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown inFIG.5, system500can include a host508and a memory system502having one or more memory devices504and a memory controller506. Host508can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host508can be configured to send or receive the data to or from memory devices504. Memory device504can be any memory devices disclosed herein, such as memory device100. In some implementations, memory device504includes an array of memory cells shown in200A/200B/200C/300A/300B/400A each including a vertical transistor220, as described above in detail.

Memory controller506is coupled to memory device504and host508and is configured to control memory device504, according to some implementations. Memory controller506can manage the data stored in memory device504and communicate with host508. Memory controller506can be configured to control operations of memory device504, such as read, write, and refresh operations. Memory controller506can also be configured to manage various functions with respect to the data stored or to be stored in memory device504including, but not limited to refresh and timing control, command/request translation, buffer and schedule, and power management. In some implementations, memory controller506is further configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Any other suitable functions may be performed by memory controller506as well. Memory controller506can communicate with an external device (e.g., host508) according to a particular communication protocol. For example, memory controller506may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

FIG.6illustrates a flowchart of an exemplary fabricating method600for forming a 3D memory device including vertical transistors, such as memory device200B described above in connection withFIGS.2B and2D, according to some implementations of the present disclosure.FIGS.7A-7B,8A-8B,9A-9B,10A-10B, and11A-11Billustrate schematic plan views and schematic side cross-sectional views of an exemplary 3D memory device at certain fabricating stages of the method600shown inFIG.6, according to various implementations of the present disclosure. It is understood that the operations shown in method600are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.6.

As shown inFIG.6, method600can start at operation601, in which an array of semiconductor pillars can be formed. In some embodiments, the array of semiconductor pillars can be formed in an upper portion of a semiconductor layer. Each semiconductor pillar can extend vertically (in the z-direction) and have any suitable 3D shape, such as polyhedron shapes or a cylinder shape. That is, the cross-section of each semiconductor pillar in the plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, an oval shape, or any other suitable shapes.

In some implementations, forming the array of semiconductor pillars can include forming a plurality of semiconductor walls720separated by a plurality of parallel third spacers730, as shown inFIGS.7A and7B. The plurality of semiconductor walls720and third spacers730each laterally extends along a third lateral direction (w-direction). Forming the plurality of semiconductor walls720and the plurality of parallel third spacers730can include forming a plurality of third trenches vertically extend into an upper portion of a semiconductor layer710(e.g., a silicon substrate) as illustrated in a side view ofFIG.7Balong AA′ line shown inFIG.7A. The remaining portions of the upper portion of the semiconductor layer710form the plurality of semiconductor walls720.

In some implementations, a lithography process is performed to pattern the plurality of third trenches using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed to etch the plurality of third trenches in the upper portion of the semiconductor layer710. Since semiconductor walls720are formed by etching semiconductor layer710, semiconductor walls720can have the same material as semiconductor layer710, such as single crystalline silicon. Then the third spacers730can be formed by depositing a dielectric material, such as silicon oxide, to fill the third trenches, using a thin film deposition process including, but not limited to, CVD, PVD, ALD, or any combination thereof. A planarization process can be performed to remove excess dielectric over the top surface of semiconductor layer710.

In some implementations, forming the array of semiconductor pillars can further include forming a plurality of parallel first trenches810extending along a first lateral direction (x-direction), as shown inFIGS.8A and8B. The plurality of parallel first trenches810can vertically extend into upper portions of the semiconductor layer710as illustrated in a side view ofFIG.8Balong CC′ line (along the w-direction) shown inFIG.8A. The plurality of the semiconductor walls720can be separated by the plurality of first trenches810into an array of semiconductor pillars820. In some implementations, a lithography process is performed to pattern the plurality of first trenches using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed to etch the plurality of third trenches in the upper portion of the semiconductor layer710.

Referring back toFIG.6, method600can proceed to operation603, in which two conductive structures can be formed in each first trench. In some implementations, each conductive structure can be isolated from an adjacent row of semiconductor pillars by a gate dielectric layer.

In some implementations, before forming the conductive structure, a lower trench isolation structure can be formed in the bottom of the first trenches. As shown inFIG.9B, a lower trench isolation structure935is formed at a bottom of each first trench810. In some implementations, a dielectric, such as silicon oxide, is deposited to fully fill the first trenches810using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, a spin coating process, or any combination thereof. In some implementations, an etch-back process, is performed to remove upper portions of the dielectric, such that the remaining portion of the dielectric form the lower trench isolation structure935located at a bottom portion of the first trenches810.

In some implementations, a gate dielectric layer920can be formed to cover the exposed sidewalls of the semiconductor pillars820. As illustrated inFIGS.9A and9B, the gate dielectric layer920can cover the sidewalls of each semiconductor pillar820exposed by the first trenches810. In some implementations, the gate dielectric layer920is formed by depositing a layer of dielectric, such as silicon oxide, over the sidewalls of each semiconductor pillar820using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. It some other implementations, the gate dielectric layer920is formed by a wet oxidation and/or a dry oxidation process, such as in situ steam generation (ISSG) oxidation, is performed to form native oxide (e.g., silicon oxide) on exposed sidewalls of the semiconductor pillars820(e.g., single crystalline silicon) as the gate dielectric layer920.

After forming the gate dielectric layer, a conductive layer is formed in the first trenches810. In some implementations, to form the conductive layer, one or more conductive films are deposited in the first trenches810and over the gate dielectric layer920. In some implementations, the conductive layer can be formed by depositing one or more conductive materials, such as metal and/or metal compounds (e.g., W and TiN), over the gate dielectric layer920using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, to partially fill the first trenches810. For example, layers of TiN and W may be sequentially deposited to form the conductive structure. A planarization process, e.g., CMP, can be performed to remove the excess conductive materials over the top surface of semiconductor layer710.

After forming the conductive layer, a plurality of second spacers930each extending along the first lateral direction (x-direction) can be formed to separate the conductor layer into two conductive structures910each extending along the first lateral direction. In some implementations, to form the plurality of second spacers930, the conductive layer is patterned and etched to form a plurality of third trenches (not shown) each vertically extending between adjacent sidewalls of the conductive layer on the sidewalls of each first trench810, and laterally extending parallel along the first lateral direction (x-direction). In some implementations, the conductive structures910are etched back, for example, using dry etch and/or wet etch (e.g., RIE), to form dents, such that the upper end of the conductive structure910is below the top surface of semiconductor pillars820. In some implementations, as the gate dielectric layer920is not etched back, the upper end of the conductive structure910is below the upper end of the gate dielectric layer920as well, which is flush with the top surface of semiconductor pillars820.

In some implementations, as shown inFIGS.9A and9B, a dielectric material, such as silicon oxide, is deposited in the remaining space of third trenches as well as the dents (not shown) to form the plurality of third spacers930, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, forming the plurality of third spacers930can include forming one or more air gaps (not shown) embedded in the dielectric material. The one or more air gaps can be formed due to the relatively small pitches of the third spacers in the second lateral direction. The relatively large dielectric constant of air in air gaps (e.g., about 4 times the dielectric constant of silicon oxide) can improve the insulation effect between separated conductive material(s) and semiconductive material(s) compared with some dielectrics (e.g., silicon oxide).

Referring back toFIG.6, method600can then proceed to operation605, in which a plurality of first spacers each extending along the first lateral direction can be formed to separate each row of the array of semiconductor pillars to form two rows of semiconductor bodies.

In some implementations as shown inFIGS.10A and10B, forming the plurality of first spacers includes forming a plurality of fourth trenches1010each extending along the first lateral direction (x-direction) to separate each row of the array of semiconductor pillars820into two rows of semiconductor bodies1020. In some implementations, a lithography process can be applied to pattern the fourth trenches on the array of semiconductor pillars820using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed on the array of semiconductor pillars820to etch the fourth trenches1010. The etching can be controlled such that a depth of the fourth trenches can be greater than the depth of the first trenches810.

In some implementations as shown inFIGS.11A and11B, after forming the fourth trenches1010, portions of the third spacers730exposed by the fourth trenches1010can be removed, and portions of each of the array of semiconductor bodies1020can be removed by one or more etching processes, such as wet etching, such that the lateral corners of each semiconductor body1020exposed by the fourth trench1010are rounded. As such, each of the array of semiconductor pillars1120has a curved sidewall exposed by the fourth trenches1010. Next, a plurality of first spacers1110can be formed to fill the plurality of fourth trenches1010, for example, by depositing a dielectric material, such as silicon oxide, to fill the third and fourth trenches, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

In some implementations, forming the plurality of first spacers1110can include forming one or more air gaps (not shown) embedded in the dielectric material. The one or more air gaps can be formed due to the relatively small pitches of the first spacers1110in the second lateral direction. The relatively large dielectric constant of air in air gaps (e.g., about 4 times the dielectric constant of silicon oxide) can improve the insulation effect between separated conductive material(s) and semiconductive material(s) compared with some dielectrics (e.g., silicon oxide).

It is noted that, any suitable operations can be performed about operation605to further fabricating the memory device. For example, both ends of the semiconductor body1120can be doped to form the source and drain. As another example, a plurality of storage units, such as a plurality of capacitors can be formed to electrically coupled with one of source/drain of each semiconductor body1120. As yet another example, a plurality of bit lines can be formed to electrically coupled with the other one of source/drain of each semiconductor body1120.

FIG.12illustrates a flowchart of an exemplary fabricating method1200for forming a 3D memory device including vertical transistors, such as memory device300B described above in connection withFIGS.3B and3C, according to some implementations of the present disclosure.FIGS.13A-13B,14A-14B,15A-15B,16A-16B and17A-17Billustrate schematic plan views and schematic side cross-sectional views of an exemplary 3D memory device at certain fabricating stages of the method1200shown inFIG.12, according to various implementations of the present disclosure. It is understood that the operations shown in method1200are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.12.

As shown inFIG.12, method1200can start at operation1201, in which an array of semiconductor pillars can be formed. In some embodiments, the array of semiconductor pillars can be formed in an upper portion of a semiconductor layer. Each semiconductor pillar can extend vertically (in the z-direction) and have any suitable 3D shape, such as polyhedron shapes or a cylinder shape. That is, the cross-section of each semiconductor pillar in the plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, an oval shape, or any other suitable shapes.

In some implementations, forming the array of semiconductor pillars can include forming a plurality of semiconductor walls1320separated by a plurality of parallel third spacers1330, as shown inFIGS.13A and13B. The plurality of semiconductor walls1320and third spacers1330each laterally extends along a third lateral direction (w-direction). Forming the plurality of semiconductor walls720and the plurality of parallel third spacers1330can include forming a plurality of third trenches vertically extend into an upper portion of a semiconductor layer710(e.g., a silicon substrate) as illustrated in a side view ofFIG.13Balong AA′ line shown inFIG.13A. The remaining portions of the upper portion of the semiconductor layer1310form the plurality of semiconductor walls1320.

In some implementations, a lithography process is performed to pattern the plurality of third trenches using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed to etch the plurality of third trenches in the upper portion of the semiconductor layer1310. Since semiconductor walls1320are formed by etching semiconductor layer1310, semiconductor walls1320can have the same material as semiconductor layer1310, such as single crystalline silicon. Then the third spacers1330can be formed by depositing a dielectric material, such as silicon oxide, to fill the third trenches, using a thin film deposition process including, but not limited to, CVD, PVD, ALD, or any combination thereof. A planarization process can be performed to remove excess dielectric over the top surface of the semiconductor layer1310.

In some implementations, forming the array of semiconductor pillars can further include forming a plurality of parallel first trenches1410extending along a first lateral direction (x-direction), as shown inFIGS.14A and14B. The plurality of parallel first trenches1410can vertically extend into upper portions of the semiconductor layer1310as illustrated in a side view ofFIG.14Balong CC′ line (along the w-direction) shown inFIG.14A. The plurality of the semiconductor walls1320can be separated by the plurality of first trenches1410into an array of semiconductor pillars1420. In some implementations, a lithography process is performed to pattern the plurality of first trenches using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed to etch the plurality of third trenches in the upper portion of the semiconductor layer1310.

In some implementations as shown inFIGS.15A and15B, portions of the third spacers1330exposed by the first trenches1410can be removed to form the enlarged first trenches1510. Portions of each of the array of semiconductor pillars1420exposed can be removed by one or more etching processes, such as wet etching, such that the lateral corners of each semiconductor pillar1420exposed by the first trenches1410are rounded. As such, each of the array of rounded semiconductor pillars1520has an oval-like shape having two curved sidewalls exposed by adjacent two enlarged first trenches1510.

Referring back toFIG.12, method1200can proceed to operation1203, in which two conductive structures can be formed in each enlarged first trench. In some implementations, each conductive structure can be isolated from an adjacent row of semiconductor pillars by a gate dielectric layer. In some implementations, the conductive structure can at least partially surround the semiconductor pillar. For example, the conductive structure can surround a curved sidewall of the semiconductor pillar from three lateral directions.

In some implementations, a gate dielectric layer1530can be formed to cover the exposed sidewalls of the rounded semiconductor pillars1520. As illustrated inFIGS.15A and15B, the gate dielectric layer1530can cover the curved sidewalls of each rounded semiconductor pillars1520exposed by the enlarged first trenches1510. In some implementations, the gate dielectric layer1530is formed by depositing a layer of dielectric, such as silicon oxide, over the sidewalls of each rounded semiconductor pillars1520using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. It some other implementations, the gate dielectric layer1530is formed by a wet oxidation and/or a dry oxidation process, such as in situ steam generation (ISSG) oxidation, which is performed to form native oxide (e.g., silicon oxide) on exposed sidewalls of the rounded semiconductor pillars1520(e.g., single crystalline silicon) as the gate dielectric layer1530.

In some implementations, a lower trench isolation structure can be formed in the bottom of the enlarged first trenches1510. As shown inFIG.16B, a lower trench isolation structure1610is formed at a bottom of each enlarged first trench1510. In some implementations, a dielectric, such as silicon oxide, is deposited to fully fill the enlarged first trenches1510using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, a spin coating process, or any combination thereof. In some implementations, an etch-back process, is performed to remove upper portions of the dielectric, such that the remaining portion of the dielectric form the lower trench isolation structure1610located at a bottom portion of the enlarged first trenches1510.

After forming the lower trench isolation structure1610, a conductive layer can be formed in each enlarged first trench1510. In some implementations, to form the conductive layer, one or more conductive layers are deposited in the enlarged first trenches1510and over the gate dielectric layer1530and the lower trench isolation structure1610. In some implementations, the conductive layer can be formed by depositing one or more conductive materials, such as metal and/or metal compounds (e.g., W and TiN), over the gate dielectric layer1530and the lower trench isolation structure1610using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, to partially fill the enlarged first trenches1510. For example, layers of TiN and W may be sequentially deposited to form the conductive layer. A planarization process, e.g., CMP, can be performed to remove the excess conductive materials over the top surface of semiconductor layer1310.

After forming the conductive layer, a plurality of first spacers1640each extending along the first lateral direction (x-direction) can be formed to separate the conductor layer into two conductive structures1620. In some implementations, to form the plurality of first spacers1640, the conductive layer is patterned and etched to form a plurality of second trenches (not shown) each vertically extending between adjacent sidewalls of the conductive layer on the sidewalls of each enlarged first trench1510, and laterally extending parallel along the first lateral direction (x-direction). As such, the conductive layer in each enlarged first trench1510is separated into two conductive structures1620. Each conductive structure1620can surround the curved sidewall of each rounded semiconductor pillar1520from three lateral directions. In some implementations, the conductive structures1620are etched back, for example, using dry etch and/or wet etch (e.g., RIE), to form dents, such that the upper end of the conductive structure1620is below the top surface of rounded semiconductor pillars1520. In some implementations, as the gate dielectric layer1530is not etched back, the upper end of the conductive structure1620is below the upper end of the gate dielectric layer1530as well, which is flush with the top surface of rounded semiconductor pillars1520.

In some implementations, as shown inFIGS.15A and15B, a dielectric material, such as silicon oxide, is deposited in the remaining space of second trenches as well as the dents (not shown) to form the plurality of first spacers1640, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, forming the plurality of first spacers1640can include forming one or more air gaps (not shown) embedded in the dielectric material. The one or more air gaps can be formed due to the relatively small pitches of the third spacers in the second lateral direction. The relatively large dielectric constant of air in air gaps (e.g., about 4 times the dielectric constant of silicon oxide) can improve the insulation effect between separated conductive material(s) and semiconductive material(s) compared with some dielectrics (e.g., silicon oxide).

Referring back toFIG.12, method1200can then proceed to operation1205, in which a plurality of second spacers each extending along a first lateral direction can be formed to separate each row of the rounded semiconductor pillars into two rows of semiconductor bodies.

In some implementations as shown inFIGS.17A and17B, forming the plurality of second spacers comprises forming a plurality of fourth trenches (not shown) each extending along the first lateral direction (x-direction) to separate each row of the array of rounded semiconductor pillars1520into two rows of semiconductor bodies1720. In some implementations, a lithography process can be applied to pattern the fourth trenches on the array of rounded semiconductor pillars1520using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed on the array rounded of semiconductor pillars1520to etch the fourth trenches. The etching can be controlled such that a depth of the fourth trenches can be greater than the depth of the first trenches1510. A plurality of second spacers1710can be formed to fill the plurality of fourth trenches, for example, by depositing a dielectric material, such as silicon oxide, to fill the third and fourth trenches, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

In some implementations, forming the plurality of second spacers1710can include forming one or more air gaps (not shown) embedded in the dielectric material. The one or more air gaps can be formed due to the relatively small pitches of the second spacers1710in the second lateral direction. The relatively large dielectric constant of air in air gaps (e.g., about 4 times the dielectric constant of silicon oxide) can improve the insulation effect between separated conductive material(s) and semiconductive material(s) compared with some dielectrics (e.g., silicon oxide).

It is noted that, any suitable operations can be performed about operation1205to further fabricate the memory device. For example, both ends of the semiconductor body1720can be doped to form the source and drain. As another example, a plurality of storage units, such as a plurality of capacitors can be formed to electrically coupled with one of source/drain of each semiconductor body1720. As yet another example, a plurality of bit lines can be formed to electrically coupled with the other one of source/drain of each semiconductor body1720.

FIG.18illustrates a flowchart of an exemplary fabricating method1800for forming a 3D memory device including vertical transistors, such as 3D memory device400A described above in connection withFIGS.4A and4B, according to some implementations of the present disclosure.FIGS.19A-19B,20A-20B,21A-21B,22A-22B,23A-23B and24A-24Billustrate schematic plan views and schematic side cross-sectional views of an exemplary 3D memory device at certain fabricating stages of the method1800shown inFIG.18, according to various implementations of the present disclosure. It is understood that the operations shown in method1800are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.18.

As shown inFIG.18, method1800can start at operation1801, in which an array of semiconductor pillars can be formed. In some embodiments, the array of semiconductor pillars can be formed in an upper portion of a semiconductor layer. Each semiconductor pillar can extend vertically (in the z-direction) and have any suitable 3D shape, such as polyhedron shapes or a cylinder shape. That is, the cross-section of each semiconductor pillar in the plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, an oval shape, or any other suitable shapes.

In some implementations, forming the array of semiconductor pillars can include forming a plurality of semiconductor walls1920separated by a plurality of parallel third spacers1930, as shown inFIGS.19A and19B. The plurality of semiconductor walls1920and third spacers1930each laterally extends along a third lateral direction (w-direction). Forming the plurality of semiconductor walls1920and the plurality of parallel third spacers19730can include forming a plurality of third trenches vertically extend into an upper portion of a semiconductor layer710(e.g., a silicon substrate) as illustrated in a side view ofFIG.19Balong AA′ line shown inFIG.19A. The remaining portions of the upper portion of the semiconductor layer1910form the plurality of semiconductor walls1920.

In some implementations, a lithography process is performed to pattern the plurality of third trenches using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed to etch the plurality of third trenches in the upper portion of the semiconductor layer1910. Since semiconductor walls1920are formed by etching semiconductor layer1910, semiconductor walls1920can have the same material as semiconductor layer1910, such as single crystalline silicon. Then the third spacers1930can be formed by depositing a dielectric material, such as silicon oxide, to fill the third trenches, using a thin film deposition process including, but not limited to, CVD, PVD, ALD, or any combination thereof. A planarization process can be performed to remove excess dielectric over the top surface of the semiconductor layer1910.

In some implementations, forming the array of semiconductor pillars can further include forming a plurality of parallel first sacrificial structures2010extending along a first lateral direction (x-direction), as shown inFIGS.20A and20B. The plurality of parallel first sacrificial structures2010can vertically extend into upper portions of the semiconductor layer1910as illustrated in a side view ofFIG.20Balong CC′ line (along the w-direction) shown inFIG.20A. The plurality of the semiconductor walls1920can be separated by the plurality of first sacrificial structures2010into an array of semiconductor pillars2020. In some implementations, a lithography process is performed to pattern the plurality of first trenches using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed to etch the plurality of third trenches in the upper portion of the semiconductor layer1910.

Referring back toFIG.18, method1800can then proceed to operation1803, in which a plurality of second sacrificial structures each extending along the first lateral direction can be formed to separate each row of the array of semiconductor pillars into two rows of semiconductor bodies.

In some implementations as shown inFIGS.21A and21B, forming the plurality of second sacrificial structures2120comprises forming a plurality of second trenches each extending along the first lateral direction (x-direction) to separate each row of the array of semiconductor pillars2020into two rows of semiconductor bodies2130. In some implementations, a lithography process can be applied to pattern the second trenches on the array of semiconductor pillars2020using an etch mask (e.g., a photoresist mask and/or a hard mask), and one or more dry etching and/or wet etching processes, such as RIE, are performed on the array of semiconductor pillars820to etch the second trenches. The etching can be controlled such that a depth of the second trenches can be less than the depth of the first trenches. After forming the second trenches, a plurality of second sacrificial structures2120can be formed to fill the plurality of second trenches by depositing a sacrificial material. As shown inFIG.21B, a depth of second sacrificial structures2120is less than a depth of first sacrificial structures2010.

Referring back toFIG.18, method1800can then proceed to operation1805, in which the plurality of first and second sacrificial structures, and the third spacers, can be removed to form a plurality of first, second, and third trenches. Portions of each of the array of semiconductor pillars can be removed to round the lateral corners of each semiconductor pillar.

As shown inFIGS.22A and22B, the plurality of first sacrificial structures2010, second sacrificial structures2120, and the third spacers1930can be removed by any suitable process, such as one or more selective etching processes. As such, the plurality of first trenches2210, second trenches2220, and third trenches2240can be formed. The plurality of first trenches2210and second trenches2220can be alternatively arranged in the second lateral direction (y-direction), and each extends along the first lateral direction (x-direction). A depth of the second trenches2220can be less than the depth of the first trenches2210. The plurality of third trenches2240can each extend along the third lateral direction (w-direction).

In some implementations as shown inFIGS.23A and23B, portions of each of the array of semiconductor bodies2130can be removed by one or more etching processes, such as wet etching, such that the lateral corners of each semiconductor body2130exposed by the first, second, and third trenches2210,2220,2240are rounded. As such, a cross-section of each semiconductor body2130in the lateral plane can have an oval-like shape with a longitudinal axis along the third lateral direction (w-direction). Each of the array of semiconductor bodies2130has a curved sidewall exposed by the first, second, and third trenches2210,2220,2240.

Referring back toFIG.18, method1800can proceed to operation1807, in which a plurality of conductive structures can be formed. Each conductive structure can surround each of a row of semiconductor bodies aligned along the first direction. In some implementations, each conductive structure can be isolated from an adjacent row of semiconductor pillars by a gate dielectric layer.

In some implementations, before forming the conductive structure, a lower trench isolation structure2440can be formed at the bottom of the first, second, and third trenches2210,2220,2240. As shown inFIG.24B, a lower trench isolation structure2440is formed at a bottom of the first, second, and third trenches2210,2220,2240. In some implementations, a dielectric, such as silicon oxide, is deposited to fully fill the first, second, and third trenches2210,2220,2240using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, a spin coating process, or any combination thereof. In some implementations, an etch-back process, is performed to remove upper portions of the dielectric, such that the remaining portion of the dielectric form the lower trench isolation structure2440located at a bottom portion of the first, second, and third trenches2210,2220,2240.

A conductive layer is formed in the first, second, and third trenches2210,2220,2240. In some implementations, to form the conductive layer, one or more conductive films are deposited in the first, second, and third trenches2210,2220,2240, and over the gate dielectric layer2350and the lower trench isolation structure2440. In some implementations, the conductive layer can be formed by depositing one or more conductive materials, such as metal and/or metal compounds (e.g., W and TiN), over the gate dielectric layer2350and the lower trench isolation structure2440using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, to partially fill the first, second, and third trenches2210,2220,2240. For example, layers of TiN and W may be sequentially deposited to form the conductive structure. A planarization process, e.g., CMP, can be performed to remove the excess conductive materials over the top surface of semiconductor layer1910.

After forming the conductive layer, a plurality of first spacers2410and second spacers2420each extending along the first lateral direction (x-direction) can be formed to separate the conductor layer into a plurality of conductive structures2430each extending along the first lateral direction. In some implementations, to form the plurality of first spacers2410and second spacers2420, the conductive layer is patterned and etched to form a plurality of fourth trenches (not shown) each vertically extending between adjacent sidewalls of the conductive layer on the sidewalls of each first trench2210, and to form a plurality of fifth trenches (not shown) each vertically extending between adjacent sidewalls of the conductive layer on the sidewalls of each second trench2220.

The formed plurality of conductive structures2430can be laterally separated from each other in the second lateral direction (y-direction) by the fourth and fifth trenches. Each conductive structure2430can extend along the first lateral direction (x-direction) and laterally surround each of a corresponding row of semiconductor bodies2320. The conductive structure2430is separated from the semiconductor bodies2320by the gate dielectric layer2350. In some implementations, the conductive structures2430are etched back, for example, using dry etch and/or wet etch (e.g., RIE), to form dents, such that the upper end of the conductive structure2430is below the top surface of semiconductor body2320. In some implementations, as the gate dielectric layer2350is not etched back, the upper end of the conductive structure2430is below the upper end of the gate dielectric layer2350as well, which is flush with the top surface of semiconductor body2320.

A dielectric material, such as silicon oxide, is deposited in the remaining space of fourth and fifth trenches as well as the dents (not shown) to form the plurality of first spacers2410and second spacers2420, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, forming the plurality of first spacers2410and second spacers2420can include forming one or more air gaps (not shown) embedded in the dielectric material. The one or more air gaps can be formed due to the relatively small pitches of the third spacers in the second lateral direction. The relatively large dielectric constant of air in air gaps (e.g., about 4 times the dielectric constant of silicon oxide) can improve the insulation effect between separated conductive material(s) and semiconductive material(s) compared with some dielectrics (e.g., silicon oxide).

It is noted that, any suitable operations can be performed about operation1807to further fabricate the memory device. For example, both ends of semiconductor body2320can be doped to form the source and drain. As another example, a plurality of storage units, such as a plurality of capacitors can be formed to electrically coupled with one of source/drain of each semiconductor body2320. As yet another example, a plurality of bit lines can be formed to electrically coupled with the other one of source/drain of each semiconductor body2320. Specifically, in some implementations not shown in the figures, since the depth of the first spacers2410is greater than the depth of the second spacers of2420, after the semiconductor layer1910is thinned from the backside, the adjacent two semiconductor bodies2320next to the first spacer2410can be separated while the adjacent two semiconductor bodies2320next to the second spacer2420can connected on the lower ends. After doping the connected lower ends of the semiconductor bodies2320, pairs of vertical transistors sharing a common source/drain can be formed, and each bit line can be coupled with the common sources/drains of a column of pairs of vertical transistors.