Phase locked loop with lock/unlock detector

A phase locked loop is disclosed comprising: a phase detector, a loop filter, a frequency controller oscillator and a lock detector. The phase detector is operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal. The loop filter is configured to provide a control signal derived from the binary phase error signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The lock/unlock detector is configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 16174626.8, filed on Jun. 15, 2016, the contents of which are incorporated by reference herein.

FIELD

The present disclosure relates to a method of detecting lock and/or unlock in a phase locked loop, and a phase locked loop comprising a lock/unlock detector.

BACKGROUND

Phase locked loops (or PLLs) are used to generate an output signal with a defined phase and frequency relationship to an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In a digital phase locked loop, the phase detector outputs a digital signal. The output from the phase detector (indicating phase error) is received by a loop filter. The loop filter in turn provides an output signal to a frequency controlled oscillator. In an all-digital phase locked loop, the phase detector may output a digital signal, the loop filter may be a digital loop filter, and the frequency controlled oscillator may be a digitally controlled oscillator.

Phase locked loops may operate in a linear mode, in which the phase detector provides a signal that varies in a linear relationship with the phase error. A phase locked loop may also operate in a “bang-bang” mode, in which the phase detector provides a binary signal, indicating only that the phase error is positive or negative.

It is often desirable to know whether a PLL has achieved phase lock. For instance, in the context of a PLL being used to generate a local oscillator (LO) signal for a tuner, it is desirable to know if and when the PLL reaches a locked state after a tuning action. It is further desirable to know when the system is out of lock, for example, due to temperature drift or an unsuccessful tuning action.

SUMMARY

According to a first aspect, there is provided a phase locked loop comprising:

a phase detector, operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal;

a loop filter configured to provide a control signal derived from the binary phase error signal;

a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; and

a lock/unlock detector configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.

The lock detector may comprise a high pass filter configured to receive the phase error signal, and to pass frequencies that correspond with a phase locked state of the phase locked loop.

The lock detector may comprise a rectifier for rectifying the output from the high pass filter to produce a rectified signal.

The lock detector may comprise a low pass filter arranged to receive a signal derived from the rectified signal.

The lock detector may comprise a programmable gain element arranged to receive the rectified signal, and to provide a modified rectified signal to the low pass filter.

The low pass filter and/or high pass filter may be configured such that a filter parameter of the low pass filter and/or the high pass filter can be varied using a control signal.

The low pass filter may be configured to be reset in response to a signal indicating an unlock condition.

The lock detector may comprise an input enable device, configured not to pass the binary phase error signal when a signal indicating an unlock condition is present.

The signal indicating an unlock condition may comprise at least one of: an indication that the phase locked loop is not in bang-bang mode, and an indication that the phase error signal has exceeded a predetermined threshold.

The lock detector may further comprise a comparator configured to compare an output signal from the low pass filter with at least one threshold value, and to output a signal, derived from the comparison, that indicates a criterion for phase lock is met (or that criteria are met).

The lock detector may comprise a timer, the timer configured to output a signal indicative of phase lock only when a signal, indicating a criterion for phase lock is met, has been in a predetermined state for a predetermined period.

The lock detector may comprise a latch that is set by the signal from the timer, and reset by a signal that indicates an unlock condition.

The lock detector may comprise an edge detector, configured to detect edges of the phase error signal.

The lock detector may comprise a low pass filter configured to receive a signal derived from the output of the edge detector.

According to a second aspect, there is provided a receiver comprising the phase locked loop of any preceding claim.

According to a third aspect, there is provided the lock detector of the first aspect.

According to a fourth aspect, there is provided a method of detecting phase lock in a phase locked loop operating in bang-bang mode, comprising determining at least one of duty cycle or a spectral content of a phase error signal.

Each feature of each aspect may be combined with the features of each other aspect, as appropriate. For instance, the lock detector of the fourth aspect may include any of the optional features of the lock detector described with respect to the first aspect.

DETAILED DESCRIPTION OF EMBODIMENTS

In some applications (such as tuners) it is important to know the quality of a local oscillator (LO) signal produced by a phase locked loop (PLL). For example, it may be important to understand if a phase locked loop reaches a lock state after a tuning action, or if the system is out of lock (e.g. due to unsuccessful tuning or a temperature drift). If a tuner comprises a phase locked loop that generates a local oscillator signal, it may be important to minimise the tuning time (i.e. the time for the local oscillator signal to lock onto a new desired frequency and/or phase).

In case of analogue reception like AM/FM the audio is typically muted during a tuning action or background scanning. If the muting interval gets too long it gets audible. Improved lock detection means that reception could start earlier and provide some additional time for background scanning of more channels or for data reception.

In the case of digital reception schemes such as DAB (digital audio broadcasting), a locked state of a PLL generating a LO signal may be determined by identifying that the phase error is below a threshold that is sufficient to avoid lost symbols and date re-synchronization.

FIG. 1is a block diagram of an all-digital phase locked loop (ADPLL)100. The phase locked loop100comprises: a reference phase generator110, phase detector104, loop filter108, digitally controlled oscillator (DCO)109, control block105, lock detector105, time to digital converter (TDC)107, feedback divider111, feedback register112and clock103.

The clock103is an optional part of the ADPLL100, and provides a reference frequency signal123(e.g. 46.65 MHz). In other embodiments the reference frequency123may simply be provided to the ADPLL100(e.g. by an external clock).

The reference phase generator110comprises an adder101and register102, arranged to integrate an input frequency control word FCW, and thereby provide a reference phase ramp φref.

A phase detector104compares the reference phase ramp φrefwith a feedback ramp φfbderived from the output127of the DCO109, and outputs a phase error signal Δφ. The feedback ramp φvis determined by combining (e.g. by fixed point concatenation) the output from the feedback register112and the TDC107. The phase detector104is operable in a “bang-bang” mode, in which the output phase error signal Δφ is binary, either indicating a negative phase error or a positive phase error (e.g. −0.5 and +0.5 as normalised values respectively). The phase detector104may also be operable in a linear mode, in which the phase error signal Δφ is proportional to the phase error.

The loop filter108receives the phase error signal Δφ, and performs a filtering operation. The loop filter108in this example is controlled by a control block105, which may vary the configuration of the loop filter108(e.g. depending on the set FCW, and the loop state). The control block105may for example provide proportional gain kpand integral gain parameters kito the loop filter108when in tracking mode.

The loop filter108provides three output signals for controlling the DCO109, these being a process voltage temperature control signal PVT, an acquisition control signal ACQ, and a tracking signal TR. Each of these control signals may control a different switched capacitor bank of the DCO109, so as to vary the output frequency of the DCO109. In alternative arrangements a frequency controlled oscillator may be used comprising a digital to analog converter and a varactor.

The output from the DCO109is received by the feedback divider111and the TDC107. The TDC107measures and quantizes the timing difference between transitions of the reference frequency123and the transitions of the ADPLL output signal127. The feedback register112accumulates a count of the transitions in the frequency divided output of the ADPLL in each reference period. The output φffrom the TDC107is combined with the output φifrom the feedback register112, for instance by concatenation.

As an illustrative example, the output from the DCO109may have a frequency of around 4.5 GHz (e.g. 4.665 GHz). The PVT capacitor bank of the DCO109may have a tuning resolution of around 10 MHz, the ACQ capacitor bank may have a tuning resolution of around 0.5 to 1 MHz, and the TR capacitor bank may have a tuning resolution on the order of 10 to 50 kHz. The TR mode may be able to handle a 1 MHz frequency offset.

When a new frequency control word FCW is input to the ADPLL100, the control block105sequentially applies the correct loop filter parameters (e.g. kiand kp) to the loop filter108so that first the PVT output, then the ACQ output, and finally the TR output can settle. The lock sequence starts with a PVT mode in which the loop filter108generates the PVT control signal, with the ACQ and TR control signals set to a neutral value (e.g. 0, where the ACQ and TR signals can be positive and negative).

When the PVT phase is accomplished, the PVT control signal is frozen, and the loop continues in ACQ mode. When the ACQ mode is accomplished, the ACQ word is frozen and the loop enters TR mode. In PVT and ACQ mode, the phase detector104may operate in a linear mode. When the loop enters TR mode, the phase detector104switches to a bang-bang mode of operation (as described above).

When the phase detector104is operating in bang-bang mode, the loop filter108may be configured (e.g. in response to a control signal from the control block105) to change the TR output by a small and constant increment (positive or negative) for each clock cycle that there is a (positive or negative) phase error. A settling period (e.g. with some ringing) may occur when the loop filter108is switched to bang-bang mode. In bang-bang mode the ADPLL is not tuning between two states of the phase detector104(as in linear mode), but instead around a state (i.e. zero phase error). This means that the phase modulation is smaller than in linear mode, and hence the in-band phase noise performance is considerably better in bang-bang mode than in linear mode.

The phase locked loop100further comprises a lock detector150, configured to determine when the ADPLL100is locked and unlocked.

The lock detector150is shown in more detail inFIG. 2, and comprises: input enable switch151, detector core200, timer154, latch155, and logic and comparator blocks153,152,156,157.

The input enable switch151passes through the phase error125to the rest of the lock detector150, unless the logic gate152indicates that the ADPLL is not in bang-bang mode, in which case a null signal ‘0’ is provided. In the present example, the logic gate152receives aTRsignal162, which indicates (e.g. is high) when the ADPLL100is not in TR mode, and a |Δφ|>0.5 signal161, which indicates (e.g. is high) when the magnitude of the phase error Δφ is greater than 0.5 (in units that correspond with the −0.5 and +0.5 binary bang-bang mode phase error outputs). In the present example, the logic gate152is an OR gate, but other arrangements are possible. The output from the logic gate152indicates when the ADPLL100is not in TR mode, and if the phase error Δφ is outside the bang-bang range of +/−0.5. The output signal163from the input enable switch151is therefore zero if the ADPLL is not in TR mode and if the phase error is outside +/−0.5.

The detector core200receives the output from the input enable switch151and determines whether the spectral characteristics and/or duty cycle of the phase error is indicative of phase lock. When the ADPLL is in phase lock in bang-bang mode, the phase error will comprise a high frequency signal with a duty cycle of approximately 50%. Either or both of these criteria may be detected by the detector core200to indicate phase lock in bang-bang mode.

An example embodiment of a detector core200is shown inFIG. 3, in which both the spectral content and the duty cycle of the phase error is used to indicate phase lock. The detector core200comprises a high pass (HP) filter220, rectifier202, gain block203, low pass (LP) filter220and comparator205.

The HP filter220passes high frequency content (e.g. at the expected frequency with which the bang-bang phase error will switch between +/−0.5 in phase lock) and attenuates lower frequencies (associated with a settling phase).

An example of a suitable architecture for the HP filter220is shown inFIG. 4, and comprises a first summing block221, gain block222, second summing block223, unit delay224and third summing block225. The first summing block221subtracts the output of the unit delay224from the input signal163. The gain block222receives the output from the first summing block221, and multiplies this by a programmable gain factor khp, which may be equal to 20 . . . −8(i.e. may be selectable in the range 20to 2−8). The second summing block223adds the output from the gain block222to the output of the unit delay224. The unit delay operates on the output from the second summing block223. The third summing block225subtracts the input signal163from the output of the unit delay block224, to produce the edge signal211. Other arrangements are possible for the HP filter220.

Returning toFIG. 3, the rectifier202receives the HP filtered signal211from the HP filter220, and rectifies it, and provides a rectified signal212to the programmable gain block203. The gain block203multiplies the rectified signal212by a programmable lock sensitivity factor, lock_det_sensitivity (e.g. 20 . . . 7), to produce an input signal213for the low pass filter230.

An example architecture for the LP filter230is shown inFIG. 4, comprising a first order infinite impulse response (IIR) filter. Any architecture that produces a low pass frequency response may be used, e.g. moving average, etc. The forward path of the low pass filter230ofFIG. 4comprises (in order) a first summing block231, multiplier232, second summing block233and unit delay234. The output from the unit delay234is fed-back to the first summing block231, where it is subtracted from the input signal to the filter230, and to the second summing block233, where it is added to the output of the multiplier232. The multiplier232applies a gain factor (klp) to the output of the first summing block233, and passes the result to the second summing block233. The gain factor klp may be selectable in the range 20to 2−15.

Returning toFIG. 3, the low pass filter230may be reset in response to a reset signal (rst). In this example the reset signal rst is provided by logic gate206. The inputs to logic gate206(which may be an OR gate) are theTRsignal162and the |Δφ|>0.5 signal161, as described already with reference to the input enable logic gate152.

The LP filtered signal214from the LP filter230is provided to a comparator205that determines whether the LP filtered signal214has met a predetermined threshold condition (indicative of lock). In the present example, the comparator205provides an output signal that indicates when the filtered signal (lp) is within an envelope defined by a low threshold (lock_det_threshold_l) and a high threshold (lock_det_threshold_h), i.e.
Ip>lock_det_threshold_l AND Ip<lock_det_threshold_h

In this example, when this condition is true the comparator output signal164indicates this (e.g. by going high). In other embodiments a single threshold may be used, and an output provided when this is exceeded. The present example has a low threshold of around 0.2, and a high threshold of around 0.4 (normalised values compared with 0.25 for a bang-bang ADPLL in which the phase error is varying between −0.5 and +0.5 with a duty cycle of 50%).

The output164from the detector core200is a signal that indicates that the spectral content and/or duty cycle of the phase error125meets a criterion (or criteria) indicative of phase lock in bang-bang mode.

Other arrangements and variations for the detector core200are possible. For example, the HP filter201may, in some embodiments, be replaced by an edge detector. In other embodiments, the detector core200may comprise counters that detect and count high and low events of the phase error125. The count of high and low within an interval can be compared and if they are sufficiently similar, that may indicate phase lock. The count results may be filtered to avoid false detection of phase lock. One advantage of the embodiment ofFIG. 3is flexibility: it can be adjusted (e.g. by varying parameters) to suit a wide range of applications.

The timer154and latch155are optional features of the lock detector150that improve the reliability of lock indication, helping to prevent false indications of lock. The timer154is configured to provide an output that indicates whether the detector core200output signal164has indicated lock for a predetermined threshold period. The latch155is set by the timer output signal165, and reset in response to: the detector core200criterion (or criteria) not being met (indicated by the output from the inverter156); aTRsignal162; or a |Δφ|>0.5 signal161.

The output166from the latch156is the lock detection signal, and reliably indicates whether lock has been achieved. Furthermore, it will may also rapidly indicate that when unlock occurs.

FIG. 5illustrates the operation of the example embodiment ofFIGS. 1 to 4, showing a time history of: phase error125, edge/zero crossing output211, rectifier output signal212, low pass filter output signal214, comparator output signal164(indicating the lock criterion is met), and the latch output166.

From t=0 ms to around t=0.09 ms, the ADPLL goes through PVT and ACQ mode, finally entering TR mode just before t=0.1 ms. During PVT and ACQ mode the input enable switch151prevents the lock detector150receiving any phase error signals, so there is no potential for a false lock indication during this period. When the ADPLL enters TR mode, there is some ringing of the loop filter108before it settles. During this ringing period, the amplitude of the phase error125is generally greater than 0.5, so the input enable switch151does not generally pass any signal to the detector core200. The ringing of the loop filter108generates some non-zero output values from the high pass filter201(as it crosses zero), but these are of very short duration, and subsequently do not result in a significant change in the low pass filter output signal214.

At around t=0.3, the phase error has largely settled to within the bang-bang limits of +/−0.5, but comprises largely low frequency spectral content, which does not result in a consistent response from the HP filter201. When the ADPLL enters bang-bang mode, at around t=0.45 ms, the phase error starts to vary between −0.5 and +0.5 with a duty cycle of approximately 50%, at high frequency, and this phase error signal125is passed through the HP filter201and the rectifier202. The LP filter204consequently receives a signal with a DC component, resulting in significant change in the LP filter output signal214. At t˜0.47 ms, the LP output signal214is within the envelope criteria of the comparator205. The comparator output signal164consequently goes high, to indicate that the lock criteria are currently met. This high signal triggers the timer154, which latches the lock detector output126after the output signal126has indicated that the lock criteria251,252have been met for a predetermined period, at t˜0.55 ms. The timer can be reset by logic157if conditions indicating unlock occur.

One application for a PLL according to the invention may be a communications device, such as a satellite or AM/FM radio receiver. A further application may be a radar chirp generator, e.g. for use in a vehicle proximity detector.

For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, and reference signs in the claims shall not be construed as limiting the scope of the claims.