Chip package structure and manufacturing method thereof

A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.

BACKGROUND

Technical Field

The disclosure relates to a package structure and a manufacturing method thereof, and particularly, to a chip package structure and a manufacturing method thereof.

Description of Related Art

In the well-known coreless manufacturing process, the edge of part of the carrier board and the edge of part of the circuit board are first combined by adhesive or copper-plated edge sealing. In another conventional method, the carrier board includes a thin substrate (e.g., with a thickness of 100 microns) which contains glass fiber cloth, each of the both sides is connected to a piece of copper foil, and peelable ultra-thin copper foil (e.g. with a thickness ranging from 3 microns to 5 microns) is attached to the thin substrate. After the circuit board has undergone multiple processes, the part with the adhesive or the copper-plated edges between the carrier board and the circuit board is cut off to obtain the circuit board for the packaging process. However, in the well-known coreless manufacturing process, part of the carrier board and part of the circuit board need to be cut off. Therefore, the size of the circuit board may be reduced, and the cut-off carrier board cannot be reused, resulting in increased manufacturing costs.

To solve the above problems, in a conventional solution, a stainless steel plate is adopted as the base of the carrier board. In processing the circuit structure, the stainless steel plate not only provides good stability but requires no cutting when the board is removed, so it can be reused, which in turn can effectively save the manufacturing costs. However, the stainless steel plate is heavy, so during the processing, handling and moving are often difficult. Moreover, the edges and corners of the stainless steel plate are relatively sharp, often causing damages to the equipment.

In addition, in the conventional manufacturing method of the chip package structure, an over molded step is applied to a die, with copper pillars on its electrodes, placed on top of a glass substrate; then a grinding process is used to expose the top of the pillars; the interconnections are formed on the molding surface after grinding. There are die shifts, temperature constraints, and substrate warpage issues, and the process is therefore complicated and costly.

SUMMARY

The disclosure provides a chip package structure and a manufacturing method thereof, which are simple and straightforward in processing and are capable of effectively reducing the manufacturing costs and improving the product yield.

A manufacturing method of a chip package structure in the disclosure includes the following steps. A carrier board is disposed. The carrier board has an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate including the inside the cavity area. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.

In an embodiment of the disclosure, a material of the substrate includes a sheet-shaped glass fiber resin substrate, a roll-shaped glass fiber resin substrate, or a roll-shaped stainless steel substrate.

In an embodiment of the disclosure, the manufacturing method of the chip package structure further includes steps of forming a metal layer on the stainless steel layer before disposing the chip in the accommodating cavity of the carrier board and removing the metal layer at its interface with the stainless steel layer when removing the carrier board.

In an embodiment of the disclosure, the step of forming the circuit structure layer on the carrier board includes forming a first patterned photoresist layer on the metal layer. The first patterned photoresist layer exposes the electrodes of the chip and part of the metal layer. A thin first metal layer and the second metal layer on the first metal layer are sputtered on the first patterned photoresist layer as the plating base, on the exposed electrode of the chip, and on the exposed metal layer. A second patterned photoresist layer is formed on the second metal layer, and the second patterned photoresist layer is disposed above the first patterned photoresist layer and exposes part of the second metal layer. An electroplating process is performed to form a conductive material layer on the second patterned photoresist layer and the exposed second metal layer. The first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer, and part of the second metal layer are removed to form a circuit structure layer; and the metal layer is exposed. The patterned circuit of the circuit structure layer includes multiple inner pins and multiple outer pins to connect to the outside world. The inner pins are separated from one another and disposed above the chip. The outer pins are connected to the inner pins and extendedly disposed on the metal layer.

In an embodiment of the disclosure, the encapsulant covers part of the metal layer and the active surface of the chip and encapsulates the inner pins and the conductive vias.

In an embodiment of the disclosure, the manufacturing method of the chip package structure further includes steps of exposing the metal layer on the back surface of the chip when removing the carrier board and forming a surface treatment layer on the metal layer on the back side of the chip.

In an embodiment of the disclosure, the carrier board further includes multiple indentations, the indentations surround the accommodating cavity, and the stainless steel layer and the substrate are conformally disposed.

In an embodiment of the disclosure, the manufacturing method of the chip package structure further includes the following steps. A metal layer is formed on the stainless steel layer before disposing the chip in the accommodating cavity of the carrier board. The metal layer fills the indentations to define multiple conductive bumps. When removing the carrier board, both the conductive bumps on the bottom surface of the encapsulant and part of the metal layer on the back surface of the chip are exposed.

In an embodiment of the disclosure, the step of forming the circuit structure layer on the carrier board includes forming a first patterned photoresist layer on the metal layer. The first patterned photoresist layer exposes the electrodes of the chip and part of the metal layer. The first metal layer and the second metal layer on the first metal layer are sputtered on the first patterned photoresist layer, on the exposed electrode of the chip, and on the metal layer. A second patterned photoresist layer is formed on the second metal layer, and the second patterned photoresist layer is disposed above the first patterned photoresist layer and exposes part of the second metal layer. An electroplating process is performed to form a conductive material layer on the second patterned photoresist layer and the exposed second metal layer. The first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer, and part of the second metal layer are removed to form a circuit structure layer, and the metal layer is exposed.

In an embodiment of the disclosure, the encapsulant covers the metal layer and the active surface of the chip and encapsulates the patterned circuit and the conductive vias.

In an embodiment of the disclosure, the manufacturing method of the chip package structure further includes the step of forming a surface treatment layer on a peripheral surface of the conductive bumps and the metal layer on the back surface of the chip after removing the carrier board.

The chip package structure of the disclosure includes a circuit structure layer, a chip, and an encapsulant. The circuit structure layer includes a patterned circuit and multiple conductive vias. The chip includes an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. The encapsulant covers the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar.

In an embodiment of the disclosure, the patterned circuit includes multiple inner pins and multiple outer pins. The inner pins are separated from one another and disposed above the chip. The encapsulant encapsulates the inner pins and the conductive vias, and the outer pins are connected to the inner pins and extend beyond the encapsulant.

In an embodiment of the disclosure, the chip package structure further includes a surface treatment layer disposed on the back surface of the chip and a metal layer on a side surface of the chip connected to the back surface.

In an embodiment of the disclosure, the chip package structure further includes multiple conductive bumps disposed on the bottom surface of the encapsulant and electronically connected to the patterned circuit through the conductive vias.

In an embodiment of the disclosure, the chip package structure further includes a surface treatment layer disposed on the back surface of the chip, on a side surface of the chip connected to the back surface, and on a peripheral surface of the conductive bumps.

Based on the above, in the manufacturing method of the chip package structure in the disclosure, the stainless steel layer is formed on the substrate of the carrier board by sputtering. Therefore, in processing the circuit structure layer, good stability can be provided. Furthermore, compared to conventional stainless steel plates, the stainless steel layer formed by sputtering has a smaller volume and weight and retains the feature that the stainless steel film and the copper-plated film thereon can be separated mechanically. Moreover, it is safer and simpler in operation. In addition, cutting is not required when separating the carrier board to expose the circuit structure layer, so the carrier board can be reused, thereby effectively saving the manufacturing costs.

In order to make the features and the advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail below.

DESCRIPTION OF THE EMBODIMENTS

References of the exemplary embodiments of the disclosure are to be made in detail. Examples of the exemplary embodiments are illustrated in the drawings. If applicable, the same reference numerals in the drawings and the descriptions indicate the same or similar parts.

FIG. 1AtoFIG. 1Iare schematic cross-sectional views illustrating a manufacturing method of a chip package structure according to an embodiment of the disclosure. Regarding the manufacturing method of the chip package structure in the embodiment, first referring toFIG. 1A, a carrier board110ais disposed; and the carrier board110ahas an accommodating cavity C and includes a substrate112and a stainless steel layer114sputtered on the substrate112. Meanwhile, the substrate112may be a rigid substrate including a glass fiber resin substrate and copper foil disposed on opposite sides of the glass fiber resin substrate; alternatively a roll-shaped glass fiber resin substrate, or a roll-shaped stainless steel substrate; or a glass substrate that has been electroplated with a titanium layer and a copper layer, and all of which belong to the scope of the disclosure. The material of the stainless steel layer114may be SUS 304 stainless steel or other suitable models of stainless steel, for example. The thickness of the stainless steel layer114ranges from 0.05 μm to 0.5 μm, for example. In other words, the stainless steel layer114can be regarded as a stainless steel film.

Next, referring toFIG. 1Aagain, a metal layer120is formed on the stainless steel layer114. Meanwhile, the metal layer120and the carrier board110aare conformally disposed, and the material of the metal layer120is copper, for example, but the disclosure is not limited thereto.

Next, referring toFIG. 1B, a chip130is disposed in the accommodating cavity C of the carrier board110a. The chip130has an active surface131, a back surface133opposite to the active surface131, and multiple electrodes132disposed on the active surface131. Meanwhile, the chip130is disposed on the metal layer120corresponding to the accommodating cavity C of the carrier board110a, and the material of the electrode132is aluminum, for example, but the disclosure is not limited thereto.

Next, referring toFIG. 1C, a first patterned photoresist layer P1is formed on the metal layer120, and the first patterned photoresist layer P1exposes the electrodes132of the chip130and part of the metal layer120.

Next, referring toFIG. 1D, a first metal layer140and a second metal layer145on the first metal layer140are sputtered on the first patterned photoresist layer P1, on the exposed electrodes132of the chip130, and on the exposed metal layer120. Meanwhile, the first metal layer140is a titanium layer, for example; and the second metal layer145is a copper layer, for example. Alternatively, the first metal layer140is a chromium layer, for example; and the second metal layer145is a copper layer, for example.

Next, referring toFIG. 1E, a second patterned photoresist layer P2is formed on the second metal layer145, the second patterned photoresist layer P2is disposed above the first patterned photoresist layer P1, and part of the second metal layer145is exposed. Meanwhile, the pattern of the first patterned photoresist layer P1is different from the pattern of the second patterned photoresist layer P2.

Next, referring toFIG. 1F, the second metal layer145is served as an electroplating seed layer to perform an electroplating process to form a conductive material layer150aon the second patterned photoresist layer P2and the exposed second metal layer145.

Next, referring to bothFIG. 1FandFIG. 1G, the first patterned photoresist layer P1, the second patterned photoresist layer P2, part of the first metal layer140, and part of the second metal layer145are removed; a circuit structure layer150is formed; and the metal layer120is exposed. At this phase, the circuit structure layer150has been formed on the carrier board110a, the circuit structure layer150includes a patterned circuit152and multiple conductive vias154, and the patterned circuit152is electrically connected to the electrode132of the chip130through the conductive via154. Meanwhile, the patterned circuit152of the circuit structure layer150includes multiple inner pins153and multiple outer pins155, the inner pins153are separated from one another and disposed above the chip130, and the outer pins155are connected to the inner pins153and are extendedly disposed on the metal layer120. Moreover, the conductive via154is formed by the remaining first metal layer140, the remaining second metal layer145, and part of the conductive material layer150a. According to the foregoing description, the dielectric layer is not adopted to process the circuit structure layer in the embodiment, but by removing the photoresist, part of the circuit is suspended to form an air bridge structure. At this phase, the circuit structure layer150may be regarded as a kind of lead frame.

Subsequently, referring toFIG. 1H, an encapsulant160is formed to cover the active surface131of the chip130and the circuit structure layer150. The active surface131of the chip130and a bottom surface162of the encapsulant160are coplanar. Meanwhile, the encapsulant160covers part of the metal layer120and the active surface131of the chip130and encapsulates the inner pins153and the conductive vias154.

Finally, referring to bothFIG. 1HandFIG. 1I, the carrier board110aand part of the metal layer120are removed to expose the bottom surface162of the encapsulant160. Meanwhile, the method for removing the carrier board110ais that the encapsulant160is disposed on a vacuum platform (not shown) in a facing down manner, for example; and the encapsulant160is held firmly by a vacuum. Moreover, the encapsulant160is fixed by a mechanism and is separated from the metal layer120on the carrier board110aalong the interface of the stainless steel layer114. Compared to the conventional method for removing the carrier board, the carrier board110ain the embodiment requires no cutting, so the carrier board110acan be reused, thereby effectively saving the manufacturing costs. Moreover, the method for removing the metal layer120is etching, for example. At this phase, the processing of a lead frame type of chip package structure100alhas been completed.

In terms of structure, referring toFIG. 1Iagain, the chip package structure100alincludes the circuit structure layer150, the chip130, and the encapsulant160. The circuit structure layer150includes the patterned circuit152and the conductive vias154. The chip130has the active surface131, the back surface133opposite to the active surface131, and the electrodes132disposed on the active surface131. The patterned circuit152includes the inner pins153and the outer pins155, the inner pins153are separated from one another and disposed above the chip130, and the inner pins153of the patterned circuit152are electrically connected to the electrodes132of the chip130through the conductive vias154. The encapsulant160covers the active surface131of the chip130and the circuit structure layer150, the encapsulant160encapsulates the inner pins153and the conductive vias154, and the outer pins155are connected to the inner pins153and extend beyond the encapsulant160. Specifically, the active surface131of the chip130and the bottom surface162of the encapsulant160are coplanar.

In short, in the manufacturing method of the chip package structure100alof the embodiment, the stainless steel layer114is formed on the substrate112of the carrier board110aby sputtering. Therefore, in processing the circuit structure layer150, good stability can be provided. Furthermore, the stainless steel layer114formed by sputtering can have a smaller volume and weight compared to those of the conventional stainless steel plate, and it is safer and simpler in operation. In addition, the carrier board110arequires no cutting when being separated, so the carrier board110acan be reused, thereby effectively saving the manufacturing cost.

FIG. 1Jis a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the disclosure. In the embodiment, the reference numerals and a part of the contents of the above embodiments are used, the same reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the above embodiments, and details are not iterated in the embodiment.

Referring toFIG. 1J, inFIG. 1H, only part of the metal layer120is removed after the carrier board110ais removed, and the metal layers on a side surface135and the back surface133of the chip130are remained and become a metal layer170. Then, a surface treatment layer172is formed on the metal layer170on the back surface133of the chip130, and on the surface of the outer pin155. Meanwhile, the material of the surface treatment layer172is tin, for example, but the disclosure is not limited thereto. At this phase, the processing of a lead frame type of chip package structure100a2has been completed. At this phase, the processing of a lead frame type of chip package structure100a2has been completed.

Since the chip package structure100a2in the embodiment has the metal layer170disposed on the back surface133of the chip130, the metal layer170can be directly served as a shielding layer for preventing electromagnetic interference. Compared to conventional shielding plates or grounding plates which are additionally disposed as requirements, the chip package structure100a2in the embodiment can have a thinner package thickness and contribute to the reduction of the manufacturing costs.

FIG. 2AtoFIG. 2Iare schematic cross-sectional views illustrating a manufacturing method of a chip package structure according to another embodiment of the disclosure. Regarding the manufacturing method of the chip package in the embodiment, first referring toFIG. 2A, a carrier board110bis disposed, and the carrier board110bhas an accommodating cavity C′ and multiple indentations C1surrounding the accommodating cavity C′. The carrier board110bincludes a substrate112′ and a stainless steel layer114′ sputtered on the substrate112′. Meanwhile, the stainless steel layer114′ and the substrate112′ are conformally disposed. Meanwhile, the substrate112′ may be a rigid substrate including a glass fiber resin substrate and copper foil disposed on opposite sides of the glass fiber resin substrate; alternatively a roll-shaped glass fiber resin substrate, or a roll-shaped stainless steel substrate; or a glass substrate that has been electroplated with a titanium layer and a copper layer, and all of which belong to the scope of the disclosure. The material of the stainless steel layer114′ may be SUS 304 stainless steel or other suitable models of stainless steel, for example. The thickness of the stainless steel layer114′ ranges from 0.05 μm to 0.5 μm, for example. In other words, the stainless steel layer114′ may be regarded as a stainless steel film.

Next, referring toFIG. 2B, a metal layer120′ is formed on the stainless steel layer114′, and the metal layer120′ fills the indentations C1to define multiple conductive bumps T. Meanwhile, the material of the metal layer120′ is copper, for example, but the disclosure is not limited thereto.

Next, referring toFIG. 2Bagain, the chip130is disposed in the accommodating cavity C′ of the carrier board110b. The chip130has the active surface131, the back surface133opposite to the active surface131, and the multiple electrodes132disposed on the active surface131. Meanwhile, the chip130is disposed on the metal layer120′ corresponding to the accommodating cavity C′ of the carrier board110b, and the material of the electrode132is aluminum, for example, but the disclosure is not limited thereto.

Next, referring toFIG. 2C, a first patterned photoresist layer P1′ is formed on the metal layer120, and the first patterned photoresist layer P1′ exposes the electrodes132of the chip130and part of the metal layer120′.

Next, referring toFIG. 2D, the first metal layer140and the second metal layer145on the first metal layer140are sputtered on the first patterned photoresist layer P1′, on the exposed electrodes132of the chip130, and on the exposed metal layer120′. Meanwhile, the first metal layer140is a titanium layer, for example; and the second metal layer145is a copper layer, for example. Alternatively, the first metal layer140is a chromium layer, for example; and the second metal layer145is a copper layer, for example.

Next, referring toFIG. 2E, a second patterned photoresist layer P2′ is formed on the second metal layer145, the second patterned photoresist layer P2′ is disposed above the first patterned photoresist layer P1′, and part of the second metal layer145is exposed. Meanwhile, the pattern of the first patterned photoresist layer P1′ is different from the pattern of the second patterned photoresist layer P2′.

Next, referring toFIG. 2F, the second metal layer145is served as an electroplating seed layer to perform an electroplating process to form a conductive material layer150a′ on the second patterned photoresist layer P2′ and the exposed second metal layer145.

Next, referring to bothFIG. 2FandFIG. 2G, the first patterned photoresist layer P1′, the second patterned photoresist layer P2′, part of the first metal layer140, and part of the second metal layer145are removed, a circuit structure layer150′ is formed, and the metal layer120′ is exposed. The circuit structure layer150′ includes a patterned circuit152′ and multiple conductive vias154′, and the patterned circuit152′ is electrically connected to the electrode132of the chip130through the conductive via154′. Meanwhile, the conductive via154′ is formed by the remaining first metal layer140, the remaining second metal layer145, and part of the conductive material layer150a′. At this phase, the circuit structure layer150′ has been formed on the carrier board110b.

Subsequently, referring toFIG. 2H, an encapsulant160′ is formed to cover the active surface131of the chip130and the circuit structure layer150′. The active surface131of the chip130and a bottom surface162′ of the encapsulant160′ are coplanar.

Finally, referring to bothFIG. 2HandFIG. 2I, when the carrier board110bis removed, both the conductive bumps T on the bottom surface162′ of the encapsulant160′ and part of the metal layer120′ on the back surface133of the chip130are exposed. Meanwhile, the encapsulant160′ covers the metal layer120′ and the active surface131of the chip130and encapsulates the patterned circuit152′ and the conductive vias154′.

Meanwhile, the method for removing the carrier board110bis that the encapsulant160′ is disposed on a vacuum platform (not shown) in a facing down manner, for example; and the encapsulant160′ is held firmly by a vacuum. Moreover, the encapsulant160′ is fixed by a mechanism and is separated from the metal layer120′ on the carrier board110balong the interface of the stainless steel layer114. Compared to the conventional method for removing the carrier board, the carrier board110bin the embodiment requires no cutting, so the carrier board110bcan be reused, thereby effectively saving the manufacturing costs. Moreover, the method for removing the metal layer120′ is etching, for example. At this phase, the processing of a quad flat no-lead (QFN) type of chip package structure100b1has been completed.

In terms of structure, referring toFIG. 2Iagain, the chip package structure100b1includes the circuit structure layer150′, the chip130, and the encapsulant160′. The circuit structure layer150′ includes the patterned circuit152′ and the conductive vias154′. The chip130has the active surface131, the back surface133opposite to the active surface131, and the electrodes132disposed on the active surface131. The patterned circuit152′ is electrically connected to the electrodes132of the chip130through the conductive vias154′. The encapsulant160′ covers the active surface131of the chip130and the circuit structure layer150′. Specifically, the active surface131of the chip130and the bottom surface162′ of the encapsulant160′ are coplanar. In addition, the chip package structure100b1in the embodiment further includes the conductive bumps T, and the conductive bumps T are disposed on the bottom surface162′ of the encapsulant160′ and are electrically connected to the patterned circuit152′ through the conductive vias154.

FIG. 2Jis a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the disclosure. In the embodiment, the reference numerals and a part of the contents of the above embodiments are used, the same reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the above embodiments, and details are not iterated in the embodiment.

Referring toFIG. 2J, after the step ofFIG. 2I, a surface treatment layer170′ may also be formed on a peripheral surface S of the conductive bumps T and on the metal layer120′ on the back surface133of the chip130. Meanwhile, the material of the surface treatment layer170′ is tin, for example, but the disclosure is not limited thereto. At this phase, the processing of a quad flat no-lead (QFN) type of chip package structure100b2has been completed.

Since the chip package structure100b2in the embodiment has the surface treatment layer170′ disposed on the back surface133of the chip130, on the side surface135of the chip130connected to the back surface133and the active surface131, and on the peripheral surface S of the conductive bumps T, the surface treatment layer170′ can be directly served as a shielding layer for preventing electromagnetic interference. Compared to conventional shielding plates or grounding plates which are additionally disposed as requirements, the chip package structure100b2in the embodiment can have a thinner package thickness and contribute to the reduction of the manufacturing costs.

Based on the above, in the manufacturing method of the chip package structure in the disclosure, the stainless steel layer is formed on the substrate of the carrier board by sputtering. Therefore, in processing the circuit structure layer, good stability can be provided. Furthermore, the stainless steel layer formed by sputtering can have a smaller volume and weight compared to those of the conventional stainless steel plate, and it is safer and simpler in operation. In addition, the carrier board requires no cutting when being separated to expose the circuit structure layer, so the carrier board can be reused, thereby effectively saving the manufacturing costs. Moreover, in some embodiments of the chip package structure in the disclosure, a surface treatment layer may also be added to serve as a shielding layer for preventing electromagnetic interference, which contributes to a thinner package thickness and reduction of the manufacturing costs.