Semiconductor device and method for manufacturing same

A method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer; and forming a first interconnect by selectively etching the metal layer. The first interconnect is electrically connected to the semiconductor layer and has a loop configuration. The method includes forming a first mask layer covering the first interconnect and the insulating layer; and forming a second mask layer on the first mask layer. The second mask layer has a first opening over a portion of the first interconnect. The method further includes exposing the portion of the first interconnect by selectively removing the first mask layer using the second mask layer; and forming a second interconnect by selectively removing the portion of the first interconnect using the first mask layer. The second interconnect has two ends and is electrically connected to the semiconductor layer.

FIELD

Embodiments are generally related to a semiconductor device and a method for manufacturing the same.

BACKGROUND

As the integration degree in a semiconductor device becomes higher, interconnect spacing inside the device becomes narrower. Accordingly, a manufacturing method thereof is required to have higher precision. For example, in the side wall process, which is used for forming interconnects, a loop shaped metal layer on a insulating layer is cut by etching, providing two interconnects that are adjacent to one another and electrically isolated. In this process, the etching is desired to be suppressed in the insulating layer.

DETAILED DESCRIPTION

According to an embodiment, a method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer; and forming a first interconnect by selectively etching the metal layer. The first interconnect is electrically connected to the semiconductor layer and has a loop configuration. The method includes forming a first mask layer covering the first interconnect and the insulating layer; and forming a second mask layer on the first mask layer. The second mask layer has a first opening over a portion of the first interconnect. The method further includes exposing the portion of the first interconnect by selectively removing the first mask layer using the second mask layer; and forming a second interconnect by selectively removing the portion of the first interconnect using the first mask layer. The second interconnect has two ends and is electrically connected to the semiconductor layer.

Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.

FIGS. 1A and 1Bare schematic cross-sectional views showing a semiconductor device1according to an embodiment.FIG. 1Ais a cross-sectional view along line A-A shown in FIG.1B; andFIG. 1Bis a cross section along line B-B shown inFIG. 1A.

The semiconductor device1is, for example, a NAND semiconductor memory device. As shown inFIG. 1A, the semiconductor device1includes multiple memory transistors MTr, a selection transistor STS, and a selection transistor STD arranged on a semiconductor layer10. The semiconductor layer10is, for example, a portion of a semiconductor layer or a well layer provided on a silicon substrate.

As shown inFIG. 1A, the memory transistor MTr includes a word line20and a charge storage layer25. The charge storage layer25is provided between the semiconductor layer10and the word line20. The charge storage layer25includes, for example, polysilicon and is electrically insulated from the semiconductor layer10and the word line20. Multiple memory transistors MTr are provided between the selection transistors STS and STD. Each of the selection transistors STS and STD includes a selection gate30.

An inter-layer insulating layer40is provided on the memory transistors MTr and the selection transistors STS and STD. The inter-layer insulating layer40includes a source line50, a source contact body55, and a drain contact body65. The inter-layer insulating layer40is, for example, a silicon oxide layer.

For example, the source contact body55extends in the Z-direction through the inter-layer insulating layer and electrically connects the semiconductor layer10to the source line50. For example, the source contact body55contacts the semiconductor layer10on the source side of the selection transistor STS.

The semiconductor device1further includes a bit line60provided on the inter-layer insulating layer40. The bit line60extends in, for example, the X-direction on the inter-layer insulating layer40. The bit line60is electrically connected to the semiconductor layer10by the drain contact body65. The drain contact body65extends in the Z-direction through the inter-layer insulating layer40. For example, the drain contact body65contacts the semiconductor layer10on the drain side of the selection transistor STD.

As shown inFIG. 1B, the semiconductor layer10includes the multiple semiconductor layers10and the multiple bit lines60. The multiple semiconductor layers10are arranged in the Y-direction. The word line20extends in the Y-direction over the multiple semiconductor layers10. The charge storage layer25is provided between the word line20and a semiconductor layer10at a portion where the word line20crosses the semiconductor layer10. Also, the selection gate30extends in the Y-direction over the multiple semiconductor layers10.

The multiple bit lines60are arranged in the Y-direction on the inter-layer insulating layer40. Each of the multiple bit lines60is electrically connected via the drain contact body65to the semiconductor layer10disposed below the drain contact body65.

A method for manufacturing the multiple bit lines60will now be described with reference toFIGS. 2A to 11B.FIGS. 2A to 11Bare schematic views showing the manufacturing processes of the bit lines60. Hereinbelow,FIGS. 3B, 4B, 5B, 6B, and 11Bare top views; and the other drawings are Y-Z cross-sectional views.

As shown inFIG. 2A, a metal layer101is formed on the inter-layer insulating layer40. The inter-layer insulating layer40is, for example, a silicon oxide layer formed using CVD (Chemical Vapor Deposition). The metal layer101is, for example, a tungsten layer that is deposited on the inter-layer insulating layer40using CVD. For example, the metal layer101may have a multilayered structure including titanium nitride and tungsten. The metal layer101is electrically connected to the semiconductor layer10by the drain contact body65.

As shown inFIG. 2B, first insulating layers103are formed on the metal layer101. The first insulating layers103are, for example, silicon nitride layers formed using CVD. For example, the first insulating layers103are formed in a line-and-space configuration using photolithography. Each of the first insulating layers103extends in the X-direction.

As shown inFIG. 2C, second insulating layers105that cover the side surfaces of the first insulating layers103are formed. The second insulating layers105are so-called sidewalls and are formed using, for example, CVD and anisotropic RIE (Reactive Ion Etching). Specifically, a silicon oxide layer is formed using CVD to cover the first insulating layers103on the metal layer101. Then, the silicon oxide layer is removed using anisotropic RIE, leaving the portions on the side surfaces of the first insulating layers103, which are the second insulating layers105.

As shown inFIG. 3A, the first insulating layers103are selectively removed; and the second insulating layers105remain on the metal layer101. For example, the second insulating layers105remain on the metal layer101after the silicon nitride layers are selectively removed by etching using phosphoric acid.

FIG. 3Ais, for example, a cross section along line C-C shown inFIG. 3B. As shown inFIG. 3B, the second insulating layers105are formed in loop configurations extending in the X-direction. In other words, the sidewalls that are formed on the side surfaces of the first insulating layers103remain with the stripe configurations extending in the X-direction.

As shown inFIGS. 4A and 4B, first interconnects160that have loop configurations are formed on the inter-layer insulating layer40. The first interconnects160are formed by selectively etching the metal layer101using the second insulating layers105as a mask.

The metal layer101is removed using, for example, anisotropic RIE. The first interconnects160include first portions160a, second portions160b, and end portions160e. The first portions160aand the second portions160bextend in the X-direction. The end portions160elink the first portions160ato the second portions160b.

For example, the first portions160aand the second portions160bare positioned on the drain contacts65exposed at the top surface of the inter-layer insulating layer40. The first interconnects160are electrically connected to the semiconductor layer10via the drain contact bodies65.

As shown inFIGS. 5A and 5B, a first mask layer107and a second mask layer109are formed on the inter-layer insulating layer40. The first mask layer107covers the first interconnects160on the inter-layer insulating layer40. The second mask layer109is formed on the first mask layer107.

The first mask layer107includes, for example, a material having a slower etching rate than an etching rate of the first interconnects160for prescribed etching conditions. The first mask layer is, for example, a carbon layer which includes carbon and a matrix material. For example, the first mask layer is provided on the inter-layer insulating layer40using CVD or spin coating. The second mask layer109is, for example, a silicon oxide layer or a silicon nitride layer formed using CVD.

As shown inFIGS. 6A and 6B, a resist mask113is formed on the second mask layer109.FIG. 6Ais a cross-sectional view along line E-E shown inFIG. 6B. The resist mask113is, for example, a photoresist.

As shown inFIG. 6B, the resist mask113has openings110aand110b. For example, the openings110aand110bextend in the X-direction, and each crosses the first interconnects160. For example, the openings110aand110bare formed using photolithography.

Continuing, the second mask layer109is selectively removed using the resist mask113; and the openings110aand110beach expand downward. In other words, openings formed in the second mask layer109have the same configurations as the configurations of the openings110aand110b.

FIGS. 7A and 7Bare cross-sectional views after the second mask layer109is selectively removed.FIG. 7Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 7Bis a cross-sectional view along line E-E shown inFIG. 6B. As shown inFIG. 7A, the first mask layer107is exposed at the bottom surfaces of the openings110aand110b.

As shown inFIGS. 8A and 8B, the first mask layer107is selectively removed using the second mask layer109.FIG. 8Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 8Bis a cross-sectional view along line E-E shown inFIG. 6B.

For example, the first mask layer107can be removed by RIE. Thereby, the openings110aand110bexpand further downward; and portions160gof the first interconnects160are exposed respectively in the openings110aand110b. Also, as shown inFIG. 8B, the resist mask113that is on the second mask layer109also is removed by RIE. Other portions160hof the first interconnects160are covered with the first mask layer107and the second mask layer109.

As shown inFIGS. 9A and 9B, the portions160gof the first interconnects160are removed, which are exposed respectively in the openings110aand110b.FIG. 9Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 9Bis a cross-sectional view along line E-E shown inFIG. 6B.

For example, the portions160gof the first interconnects160are removed using RIE. The second insulating layers105on the portions160gand the second mask layer109that remain on the portions160hof the first interconnects160(referring toFIG. 9B) also are removed simultaneously. As shown inFIG. 9A, there are cases where the inter-layer insulating layer40also is etched in the openings110aand110b; and recesses40aare formed in the top surface of the inter-layer insulating layer40. In other words, it is difficult to selectively remove the first interconnects160without removing the inter-layer insulating layer40.

On the other hand, as shown inFIG. 9B, portions160hof the first interconnects160and the inter-layer insulating layer40are not removed at the region covered with the first mask layer107. The first mask layer107is resistant to the etching condition of the portions160gand protects the portions160hof the first interconnects160. In such a case as well, it is difficult to select the conditions under which the first interconnects160are removed without removing the first mask layer107.

Accordingly, a material is selected for the first mask layer107, which has a slower etching rate than an etching rate of the first interconnects160for the prescribed etching conditions. The first mask layer107is, for example, a carbon layer that includes carbon and a matrix material. For example, the first mask layer107includes carbon having a high concentration and is conductive. Also, it is desirable for the thickness in the Z-direction of the first mask layer107to be not less than twice the thickness in the Z-direction of the metal layer101that is formed into the first interconnects160.

As shown inFIGS. 10A and 10B, the entire portions160gof the first interconnects160exposed in the openings110aand110bare removed; and the portions160hof the first interconnects160are formed into the second interconnects (the bit lines60).FIG. 10Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 10Bis a cross-sectional view along line E-E shown inFIG. 6B.

As shown inFIG. 10A, the portions160gof the first interconnects160are removed, which are exposed in the openings110aand110b. The recesses40aare made in the top surface of the inter-layer insulating layer40exposed at the bottom of the openings110aand110b. For example, the recesses40aare formed so as not to reach the interconnects (not-shown) provided under the recesses40a. In other words, the inter-layer insulating layer40has a thickness such that the bottoms of the recesses40ado not reach the lower interconnects.

As shown inFIG. 10B, the portions160hof the first interconnects160covered with the first mask layer107are not etched, and formed into the bit line60. For example, the inner surfaces of the recesses40aare positioned at a level lower than the top surfaces40band40cof the inter-layer insulating layer40directly under the adjacent bit lines60aand60b, and also lower than a top surface40dbetween the top surfaces40band40c.

As shown inFIGS. 11A and 11B, the first mask layer107is removed; and the bit lines60are completed.FIG. 11Ais a cross-sectional view along line F-F shown inFIG. 11B.FIG. 11Bis a plan view showing the upper surface of the inter-layer insulating layer40. For example, the first mask layer107is selectively removed by ashing using reactive oxygen.

As shown inFIG. 11A, the multiple bit lines60are formed on the inter-layer insulating layer40. The top surface40dof the inter-layer insulating layer40exposed between the adjacent bit lines60is not etched while removing the portions160gof the first interconnect160. Also, the top surface40dis not etched in the process of removing the first mask layer107.

As shown inFIG. 11B, the first interconnects160are separated into the adjacent bit lines60aand60band the end portions160eby the loop cutting in the openings110aand110b. The multiple bit lines60are formed between the opening110aand the opening110b. The bit lines60each have two ends60e. Also, the bit lines60are formed on the end surfaces of the drain contacts65exposed at the top surface of the inter-layer insulating layer40. Thereby, the multiple bit lines60are electrically connected respectively to the semiconductor layers10.

A method for manufacturing the bit lines60according to a modification of the embodiment will now be described with reference toFIGS. 12A to 15B.FIGS. 12A to 15Bare schematic views showing the manufacturing processes continuing fromFIG. 7B. Hereinbelow,FIGS. 12A to 15Aare cross-sectional views; andFIG. 15Bis a plan view showing the upper surface of the insulating layer40.

FIG. 12Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 12Bis a cross-sectional view along line E-E shown inFIG. 6B. As shown inFIG. 12A, the first mask layer107is selectively removed such that a part of the first mask layer107remains between the portions160gof the first interconnects160; and, for example, upper ends160fof the first interconnects160are exposed. Alternatively, the first mask layer107may be removed so that a top surface107aof the first mask107is positioned to be higher than the upper ends160fof the first interconnects160and to expose the upper ends of the second insulating layers105on the portions160g. In other words, this differs from the embodiment recited above in that parts of the first mask layer107remain at the bottoms of the openings110aand110b. As shown inFIG. 12B, portions160hof the first interconnects160are covered with the first mask layer107and the second mask layer109.

As shown inFIGS. 13A and 13B, the second insulating layers105and portions160gof the first interconnects160are removed in the openings110aand110b.FIG. 13Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 13Bis a cross-sectional view along line E-E shown inFIG. 6B.

The portions160gof the first interconnects160are removed using, for example, RIE. As shown inFIG. 13A, the inter-layer insulating layer40is not etched because the parts of the first mask layer107remains between the adjacent portions160gof the first interconnects160. Also, as shown inFIG. 13B, although the second mask layer109also is removed, portions160hof the first interconnects160that are covered with the first mask layer107are not etched.

As shown inFIGS. 14A and 14B, the entire portions160gof the first interconnects160exposed in the openings110aand110bare removed; and the bit lines60are formed at the region covered with the first mask layer107.FIG. 10Ais a cross-sectional view along line D-D shown inFIG. 6B; andFIG. 10Bis a cross-sectional view along line E-E shown inFIG. 6B.

As shown inFIG. 14A, the entire portions160gof the first interconnects160exposed in the openings110aand110bare removed. The portions160gof the first interconnects are over-etched in order to be completely removed; and thus, recesses40fare formed in the top surface of the inter-layer insulating layer40. The recesses40fare made directly under the portions160gof the first interconnects160removed by the etching. AlthoughFIG. 14Ashows the parts of the first mask layer107remaining on the inter-layer insulating layer40, the parts of the first mask layer107may not remain on the bottoms of the openings110aand110bafter the entire portions160gof the first interconnects160are removed.

As shown inFIG. 14B, the portion160hof the first interconnects160that are covered with the first mask layer107are formed into the bit lines60without being etched. For example, the inner surfaces of the recesses40fare positioned at a level lower than a top surface40gof the inter-layer insulating layer40directly under the bit lines60. As shown inFIGS. 15A and 15B, the first mask layer107is removed; and the bit lines60are completed.FIG. 15Ais a cross-sectional view along line G-G shown inFIG. 15B.FIG. 15Bis a plan view showing the upper surface of the inter-layer insulating layer40. For example, the first mask layer107is selectively removed by ashing using reactive oxygen.

As shown inFIG. 15A, the multiple bit lines60are formed on the inter-layer insulating layer40. For example, the top surface40dof the inter-layer insulating layer40exposed between the adjacent bit lines60is covered with the first mask layer107and therefore is not etched. Also, the top surface40dis not etched in the process of removing the first mask layer107as well.

As shown inFIG. 15B, the first interconnects160are separated into the adjacent bit lines60aand60band the end portions160eby the loop cutting in the openings110aand110b. The multiple bit lines60are formed between the opening110aand the opening110b. The bit lines60each have two ends60e. Also, the bit lines60are formed on the end surfaces of the drain contacts65exposed at the front surface of the inter-layer insulating layer40. Thereby, the multiple bit lines60are electrically connected respectively to the semiconductor layers10.

In the example, the parts of the first mask layer107remains in the bottom of the openings110aand110b; and the upper ends160fof the first interconnects160are exposed. Thereby, in the process of the loop cutting, wherein the portions160gof the first interconnects160are removed, the recesses40fformed in the top surface of the inter-layer insulating layer40may have the depth not reaching the interconnects under the openings110aand110b.