Laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates

In some embodiments, laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates are presented. In this regard, a substrate in introduced having a dielectric layer wherein material has been removed from a surface and the cavity has been plated with conductive material resulting in a feature width of less than about 10 micrometers. Other embodiments are also disclosed and claimed.

FIELD OF THE INVENTION

Embodiments of the present invention generally relate to the field of integrated circuit packages, and, more particularly to a laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates.

BACKGROUND OF THE INVENTION

The demand for enhanced performance and body size reduction of integrated circuit components continues to increase design and fabrication complexity due to the higher bandwidth requirements needed to enable higher clock frequencies. The substrates designed for these components will need to be manufactured with even smaller feature sizes to enable optimization of bandwidth.

DETAILED DESCRIPTION

FIG. 1is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. In accordance with the illustrated example embodiment, package substrate100includes one or more of dielectric layers102and106, core layer104, cavities108and110, and surface112.

Dielectric layers102and106represent material such as epoxy resin that has been added to core layer104as part of a build-up process. Although not shown, conductive traces may be routed within and through-holes may be routed through dielectric layers102and106.

Core layer104represents a substrate core that may be made of a metal such as copper. Core layer104may be laminated with dielectric material as part of a substrate build-up and may have insulated traces routed through it.

Cavities108and110represent areas where dielectric material has been removed from layer102below surface112. As part of a process of fabricating a high density interconnect flip chip substrate, for example as described in reference toFIG. 4, cavities108and110may have been created by a hybrid process involving laser ablation and imprinting technology. Cavity108is intended to represent a cavity with a line/space geometry of equal to or less than about 10 micrometers that was created through laser ablation. Cavity110is intended to represent a cavity with a line/space geometry of greater than about 10 micrometers that was created through imprinting technology.

FIG. 2is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As shown, package substrate200includes conductive plating layer202which has plated cavities108and110and surface112. Conductive plating layer202may be a layer of copper.

FIG. 3is a graphical illustration of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. As part of a planarization process, conductive plating layer202over surface112has been removed, leaving cavities108and110filled with conductive material.

In one embodiment, package substrate300is coupled on surface112with an integrated circuit die such as a flip chip silicon die. In another embodiment, surface112is laminated with another dielectric layer as part of a continued build-up process.

FIG. 4is a flow chart of an example method for fabricating a high density interconnect flip chip substrate, in accordance with one example embodiment of the invention. It will be readily apparent to those of ordinary skill in the art that although the following operations may be described as a sequential process, many of the operations may in fact be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged or steps may be repeated without departing from the spirit of embodiments of the invention.

According to but one example implementation, the method ofFIG. 4begins with lamination (402) of dielectric material (for example layer102) on a core layer (for example layer104).

Next, feature formation (404) takes place in dielectric layer102. In one embodiment, imprinting technology is utilized to displace dielectric material, effectively removing from the surface (112) and creating features where the required feature width is greater than about 10 micrometers. Non-imprinted areas may be masked off (appearing as blank areas) on the micro-tool. In one embodiment, nickel plated micro-tools are used to stamp surface112to generate patterns and structures in dielectric layer102. In one embodiment, subsequent to an imprint performed, a release coating is applied by spray coating. In one embodiment, imprinting is done at a temperature of not more than about 170 C. and a pressure of not more than about 2 atm.

In some embodiments, laser ablation is then utilized to pattern dielectric layer102where the required feature width is less than about 10 micrometers, for example in the necking regions of the substrate. In one embodiment, a high fluence eximer laser operating at a wavelength of about 248 nm is utilized.

Next, any residue left behind in the feature formation would be removed (406). In one embodiment, plasma etching with tetrafluoromethane or carbon tetrafluoride is used to remove residual dielectric material from cavities108and110.

Lastly, surface112and cavities108and110plated and planarized (408). In one embodiment, a damascene-style process flow would be followed where the features would be plated with copper and a chemical mechanical planarization process would be followed to remove the overplated copper. In one embodiment, planarization includes a high removal rate copper slurry with removal rates of about 15 um/min. Additional steps may be needed to complete the substrate and to couple the substrate with an integrated circuit die.

FIG. 5is a block diagram of an example electronic appliance suitable for implementing a high density interconnect flip chip substrate, in accordance with one example embodiment of the invention. Electronic appliance500is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, desktops, cell phones, wireless communication subscriber units, wireless communication telephony infrastructure elements, personal digital assistants, set-top boxes, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance500may include one or more of processor(s)502, memory controller504, system memory506, input/output controller508, network controller510, and input/output device(s)512coupled as shown inFIG. 5. Processor(s)502, or other integrated circuit components of electronic appliance500, may be housed in a package including a substrate described previously as an embodiment of the present invention.

Processor(s)502may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s)502are Intel® compatible processors. Processor(s)502may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system.

Memory controller504may represent any type of chipset or control logic that interfaces system memory508with the other components of electronic appliance500. In one embodiment, the connection between processor(s)502and memory controller504may be referred to as a front-side bus. In another embodiment, memory controller504may be referred to as a north bridge.

System memory506may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s)502. Typically, though the invention is not limited in this respect, system memory506will consist of dynamic random access memory (DRAM). In one embodiment, system memory506may consist of Rambus DRAM (RDRAM). In another embodiment, system memory506may consist of double data rate synchronous DRAM (DDRSDRAM).

Input/output (I/O) controller508may represent any type of chipset or control logic that interfaces I/O device(s)512with the other components of electronic appliance500. In one embodiment, I/O controller508may be referred to as a south bridge. In another embodiment, I/O controller508may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003.

Network controller510may represent any type of device that allows electronic appliance500to communicate with other electronic appliances or devices. In one embodiment, network controller510may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller510may be an Ethernet network interface card.

Input/output (I/O) device(s)512may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance500.

Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.