Methods to embed magnetic material as first layer on coreless substrates and corresponding structures

Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

TECHNICAL FIELD

Embodiments of the present disclosure relate electronics packaging, and more particularly, to electronic packaging with embedded magnetic layers.

BACKGROUND

Improvement in power delivery is needed in packaging architectures in order to meet increasingly demanding electrical requirements. Furthermore, the improvement in power delivery needs to be implemented without increasing the form factor (e.g., the Z-height) of packages. One way to obtain the desired improvements in power delivery is by utilizing magnetic materials on coreless substrates.

However, substrate manufacturing process used today for integrating magnetic material into the package lead to interactions with wet chemistries such as desmear, electroless plating, flash etch, soft etch, surface finishes, and the like. In particular, processing environments interact negatively with the magnetic fillers (e.g., Fe fillers). For example, the processing environment may interact with the magnetic materials and result in corrosion. Additionally, the magnetic fillers may leach into the chemistry bath and reduce the bath life and chemistry performance.

In some current processing flows that integrate magnetic materials into the package, the magnetic material is formed last to avoid some of the above mentioned issues. However, with a magnetic materials last approach, solder resist lamination needs to be done after dummy core detach. This is problematic because substrate suppliers need a dedicated tool and capital expenditure investment to enable solder resist lamination after dummy core detach. Also, tool purchase and installation would bring schedule risk to new products.

EMBODIMENTS OF THE PRESENT DISCLOSURE

As noted above, the inclusion of magnetic materials in the manufacture of organic packages is currently problematic due to the leaching of magnetic materials (e.g., iron, alloys containing iron, and other ferromagnetic particles or elements) into processing baths and corrosion. Accordingly, it is presently not feasible to integrate components, such as inductors, that benefit from the use of magnetic materials into organic substrates.

However, embodiments described herein provide processing methods that allow for the integration of magnetic materials with currently available processing techniques. Particularly, embodiments include embedding magnetic materials so that the magnetic materials are not exposed to processing environments where the leaching of magnetic materials is detrimental. For example, embodiments include embedding the magnetic materials so that the magnetic materials are not exposed to processing environments that have chemistries that may be negatively altered by leached magnetic materials, such as electroless baths, desmear baths, subtractive etching baths and the like. Since the magnetic material is isolated from such environments, there is no need to redesign the chemistries of processing baths or provide dedicated processing baths to handle the magnetic materials.

Furthermore, isolating the magnetic material allows for subsequent changes to the magnetic material to be made without needing to adjust the chemistries of processing environments. This allows for quicker design times and reduces the cost of development. Additionally, embodiments allow for reduced capital expenditures because the solder resist layer may be formed prior to dummy core removal or after the dummy core removal.

Referring now toFIG. 1, a cross-sectional illustration of an electronic package100is shown, in accordance with an embodiment. In an embodiment, the package100may include a plurality of dielectric layers and conductive layers. In an embodiment, the package100may be a coreless package. In an embodiment, the electronic package100may include a first layer130. The first layer130may comprise a dielectric layer. In a particular embodiment, the first layer130may be a photoimageable dielectric (PID). In order to provide improved functionality of integrated passive devices, the first layer130may have a thickness T that is minimized. In an embodiment, the thickness T may be 10 μm or less. In some embodiments, the thickness T may be 5 μm or less.

In an embodiment, the first layer130may directly support a first conductive layer111. The first conductive layer111may include conductive traces such as copper traces. In an embodiment, the first conductive layer111may also include traces123used for passive devices, as will be described below. In an embodiment, a second conductive layer112may be formed over the first conductive layer111. The second conductive layer112may include a plurality of conductive pillars, such as copper pillars. The conductive layer112may electrically couple the first conductive layer111to other conductive layers in the package100.

In an embodiment, the first layer130may also support a second layer125. In an embodiment, the second layer125may comprise a magnetic material. For example, the second layer125may comprise a dielectric material with magnetic filler particles, such as iron filler particles. In an embodiment, the magnetic material may be a cured liquid with magnetic filler particles or a laminated film with magnetic filler particles.

As noted above, the presence of the magnetic materials in the second layer125is problematic for currently available processing environments used in electronic packaging. Accordingly, the first conductive layer111and the second conductive layer112may be formed with lithography processes prior to second layer125being formed over the first layer130. As such, the patterning and deposition processes needed to form the first conductive layer111and the second conductive layer112are implemented without the presence of the magnetic material in the second layer125. Furthermore, since the first conductive layer111and the second conductive layer112are formed with photolithography processes, sidewalls of the first conductive layer111and the second conductive layer112may be substantially vertical. As used herein, substantially vertical may refer to a surface that is within +/−5° from being orthogonal to an underlying surface.

In an embodiment, a third layer140may be formed over a surface of the second layer125. The third layer140may comprise a dielectric material. In an embodiment, the third layer is in direct contact with the second layer125and portions of the second conductive layer112. The third layer140may be formed over the second layer125with a process that does not expose the second layer125to a bath. For example, the third layer140may be laminated over the second layer125. The third layer140may be considered a barrier layer since it protects the magnetic material of the second layer125from subsequent processing operations.

In an embodiment, a third conductive layer113may be formed through the third layer140. The third conductive layer113may include vias formed through the third layer140. In an embodiment, the vias may be formed with a lithography process or with laser drilling. It is to be appreciated that the plating and/or desmear used to form the third conductive layer113do not contact the magnetic second layer125since the third layer140protects the magnetic second layer125from the processing environments used to form the third conductor layer113.

Additional embodiments may include a fourth layer150formed over the third layer140. In an embodiment, the fourth layer150may comprise a dielectric material. A fourth conductive layer114and a fifth conductive layer115may be formed in the fourth layer150. Embodiments may include a fourth conductive layer114that includes a plurality of traces and pads, and a fifth conductive layer115that includes vias. Since the magnetic second layer125is protected by the third layer140, the magnetic material is not exposed to the processing environments used to form the fourth and fifth conductive layers114and115.

In an embodiment, a sixth conductive layer116may be formed over the fourth layer150. A solder resist layer160may be formed over the fourth layer150and the sixth conductive layer116. In an embodiment, openings121may be formed into the solder resist layer160to expose the sixth layer116. As is known in the art, surface treatment and/or protection layers119may be formed over surfaces the sixth conductive layer116exposed by the openings121. While the solder resist layer160is shown as being formed over the fourth layer150, it is to be appreciated that the electronic package100may include any number of dielectric layers and conductive layers between the magnetic second layer125and the solder resist layer160.

In an embodiment, the conductive layers and the magnetic layers may be configured to form passive elements. For example, electronic package100may include an inductor120. In an embodiment, the inductor120may include an inductor trace123that is surrounded by a magnetic material. The inductor trace123may be formed as part of the first conductive layer111. The magnetic material may surrounding the inductor trace123may include the second layer125and a magnetic block126. In an embodiment, the second layer125may be in direct contact with inductor trace123. For example, the second layer125may be in direct contact with sidewalls and a first surface121of the inductor trace123. In an embodiment, the magnetic block126may be separated from the second surface122of the inductor trace123by the first layer130. In an embodiment, the inductor120may be a transmission line inductor, a spiral inductor or a solenoid inductor.

Referring now toFIG. 2, a cross-sectional illustration of an electronic package200is shown, in accordance with an embodiment. The electronic package200is substantially similar to the electronic package100described above, with the exception that the solder resist layer is formed after a dummy core detach. As illustrated, a second solder resist layer260is formed over the first layer230. In an embodiment, the magnetic block226is formed in an opening in the solder resist layer260. Additionally, a conductive layer208is formed through first layer230. The conductive layer208may include a treatment and/or protection layer219.

Referring now toFIG. 3, a cross-sectional illustration of an electronic package300is shown, in accordance with another embodiment. Electronic package300includes a first barrier layer345and a second barrier layer340surrounding the magnetic layer325. The inclusion of a first barrier layer345allows for the first layer130/230described in the previous embodiments to be omitted. In an embodiment, the first barrier layer345may comprise a dielectric material. The first barrier layer345may be formed along the surfaces of the first conductive layer311and the second conductive layer312. Accordingly, the first barrier layer345separates the magnetic layer325from the first and second conductive layers311and312. In an embodiment, the second barrier layer340is formed over the top surface of the magnetic layer325. Combined, the first barrier layer345and the second barrier layer340enclose the magnetic layer325. As such, the magnetic layer325is protected from processing environments that may negatively interact with the magnetic materials of the magnetic layer325.

Referring now toFIGS. 4A-4Mcross-sectional illustration of a process flow for forming an electronic package with a magnetic layer is shown, in accordance with an embodiment. Referring now toFIG. 4A, a cross-sectional illustration of a dummy core405is shown, in accordance with an embodiment. In an embodiment, the dummy core405may include first and second films406and407over both surfaces, as is known in the art.

Referring now toFIG. 4B, a cross-sectional illustration of after a first layer430is formed over the films407is shown, in accordance with an embodiment. In an embodiment, the first layer430comprises a dielectric material. In some embodiments, the first layer is a PID. Embodiments include forming the first layer with any suitable process, such as laminating or the like. In an embodiment, the thickness T of the first layer is minimized in order to optimize the performance of subsequently formed passive devices. For example, the thickness T may be 10 μm or less. In some embodiments, the thickness T may be 5 μm or less.

As illustrated inFIG. 4B, the first layer430is formed over both surfaces of the dummy core405. It is to be appreciated that embodiments include forming similar layers over both surfaces of the dummy core. However, only the layers formed over the top surface of the dummy core will be described herein for clarity and simplicity.

Referring now toFIG. 4C, a cross-sectional illustration after the first layer430is patterned is shown, in accordance with an embodiment. In an embodiment, the first layer430may be patterned to form openings431that expose a portion of the film407. In an embodiment, the first layer may be patterned with a lithography process.

Referring now toFIG. 4D, a cross-sectional illustration after an underlying conductive layer408is formed in the opening is shown, in accordance with an embodiment. In an embodiment, the underlying conductive layer408may be formed with an electrolytic plating process. In an embodiment, one or more additional layers409, such as a protective layer may also be formed over the underlying layer408. The combined thickness of the underlying layer408and the additional layers409may be substantially similar to the thickness T of the first layer430.

Referring now toFIG. 4E, a cross-sectional illustration after a first conductive layer411and a second conductive layer412is formed is shown, in accordance with an embodiment. In an embodiment, the first and second conductive layers411and412may be formed with a lithography process. The first conductive layer411may include conductive traces and pads. In an embodiment, the first conductive layer411may also include conductive features423used for passive devices, such as an inductor. In an embodiment, the second conductive layer412may be formed over the first conductive layer, and may include conductive pillars. In an embodiment, sidewalls of the first and second conductive layer411and412may be substantially vertical.

Referring now toFIG. 4F, a cross-sectional illustration after a second layer425is formed is shown, in accordance with an embodiment. In an embodiment, the second layer425may comprise a magnetic material. The second layer425may be laminated or the second layer425may be a cured liquid. In an embodiment, the second layer may be planarized in order to have a top surface that is substantially coplanar with a top surface of the second conductive layer412. Embodiments include a second layer425that is conformal to the surfaces of the first conductive layer411and the second conductive layer412and that is in direct contact with portions of the first conductive layer411and the second conductive layer412. In an embodiment, the second layer425may be formed over and in direct contact with a first surface421of the passive device trace423and sidewalls of the passive device trace423.

Referring now toFIG. 4G, a cross-sectional illustration after a third layer440is formed is shown, in accordance with an embodiment. In an embodiment, the third layer440may comprise a dielectric material. Some embodiments may include a third layer440that is a PID. In an embodiment, the third layer440may be formed with a lamination process or any other suitable deposition process. The third layer440may be formed over and in direct contact with the magnetic second layer425. As such, after the formation of the third layer440, the magnetic second layer425is completely embedded and protected from subsequent processing environments. Particularly, embodiments include a magnetic second layer425that is in direct contact with the first layer430, the third layer440, and surfaces of the first and second conductive layers411and412.

In an embodiment, a third conductive layer413may be formed through the third layer440. For example, the third conductive layer413may comprise a plurality of vias. The via openings may be formed with any suitable process, such as laser drilling or photolithography. In embodiments where laser drilling is used, a desmear process may also be needed. However, since the magnetic second layer425is protected by the third layer440, there is no contamination issue, as described above. Similarly, the third conductive layer413may be plated (e.g., with an electroless or electrolytic plating process) without contamination issues.

In an embodiment, a fourth conductive layer414may be formed over a surface of the third layer440. The fourth conductive layer414may be formed with any suitable processes, such as electroless or electrolytic plating, photolithography processes, or the like. The fourth conductive layer414may include conductive traces and pads, such as pads formed over the third conductive layer413.

Referring now toFIG. 4H, a cross-sectional illustration after a fourth layer450is formed is shown, in accordance with an embodiment. In an embodiment, the fourth layer450may comprise a dielectric material. In an embodiment, the fourth layer450may be a different material than the third layer440. In some embodiments, the fourth layer450may be the same material as the third layer440. Embodiments include forming a fifth conductive layer415in the fourth layer450. The fifth conductive layer415may include conductive vias. For example, the fifth conductive layer and the fourth layer450may be formed with typical semi-additive processes (SAP), additive processes, or any other suitable process. In an embodiment, a sixth conductive layer416may be formed over the top surface of the fourth layer450. The sixth conductive layer416may include conductive pads and traces. The sixth conductive layer may be formed with any suitable process, such as an additive process, a SAP process, or the like. It is to be appreciated that since the magnetic second layer425is protected by the third layer440, there is no contamination issue during the processes used to form the fourth layer450or any of the conductive layers.

Referring now toFIG. 4I, a cross-sectional illustration of after a solder resist layer460is formed is shown, in accordance with an embodiment. Embodiments include forming the solder resist layer460over the fourth layer450and the sixth conductive layer416. However, it is to be appreciated that any number of layers of dielectric layers and conductive layers may be formed between the magnetic second layer425and the solder resist layer460. In an embodiment, the solder resist layer460may be formed with any suitable process. For example, the solder resist layer460may be formed with a lamination process.

Referring now toFIG. 4J, a cross-sectional illustration after openings421are formed through the solder resist layer is shown, in accordance with an embodiment. In an embodiment, the solder resist openings421may be formed with any suitable process, such as laser drilling, or the like. In an embodiment, a plasma cleaning may be implemented after the solder resist openings421are formed. Additionally, a surface finish419may be applied to the exposed surfaces of the sixth conductive layer416.

Referring now toFIG. 4K, a cross-sectional illustration after the dummy core405is removed is shown, in accordance with an embodiment. In an embodiment, the dummy core405may be detached with any suitable detaching process. As illustrated, the detach process may result in the film407remaining on the underside of the package. InFIG. 4Ka single package is shown. However, it is to be appreciated that the dummy core detach results in both the top-side package and the bottom-side package being released. From here on in the Figures, only one of the detached packages is illustrated for clarity.

Referring now toFIG. 4L, a cross-sectional illustration after the film407and the underlying conductive layer408are removed is shown, in accordance with an embodiment. In an embodiment, the film407and the underlying layer may be removed with a wet etching process. The conductive layers (e.g., the first conductive layer411) may be protected from the wet etch by protective layer409, which functions as an etch stop layer. In an embodiment that includes protective layer409, the protective layer may then be removed with an etching process that selectively removes the protective layer409without significantly etching away the first conductive layer411.

Referring now toFIG. 4M, a cross-sectional illustration after a magnetic block426is formed is shown, in accordance with an embodiment. In an embodiment, the magnetic block426may be formed with a printing process. As such, there is no need for etching a magnetic material to form the magnetic block426. In an embodiment, the magnetic block426may be a portion of a passive device420integrated into the package. In an embodiment, the passive device420may be an inductor. In the illustrated embodiment, the inductor420may include a conductive traces423that is surrounded by magnetic material from the second layer425and the magnetic block426. In an embodiment, the inductor may be a transmission line inductor, a spiral inductor, or a solenoid inductor.

Referring now toFIGS. 5A-5F, a series of cross-sectional illustrations of a process for forming an electronic package with an integrated magnetic material is shown, in accordance with an embodiment. Referring now toFIG. 5A, a cross-sectional illustration of an electronic package being fabricated, is shown in accordance with an embodiment. The package inFIG. 5Ais substantially similar to the package illustrated inFIG. 4H, and the processing operations used to get to this point in the process flow will not be repeated here. In an embodiment,FIG. 5Amay differ fromFIG. 4Hwith respect to the underlying layer408. For example, inFIG. 5Athere is no protection layer409between the underlying layer408and the first layer511.

Referring now toFIG. 5B, a cross-sectional illustration after the dummy core505is removed is shown, in accordance with an embodiment. In an embodiment, the dummy core505may be detached with any suitable detaching process. As illustrated, the detach process may result in the film507remaining on the underside of the package. InFIG. 5Ba single package is shown. However, it is to be appreciated that the dummy core detach results in both the top-side package and the bottom-side package being released. From here on in the Figures, only one of the detached packages is illustrated for clarity.

Referring now toFIG. 5C, a cross-sectional illustration after the film507is removed is shown, in accordance with an embodiment. In an embodiment, the film507and the underlying layer may be removed with a wet etching process.

Referring now toFIG. 5D, a cross-sectional illustration after a solder resist layer560is formed over a top surface and a bottom surface of the package is shown, in accordance with an embodiment. Embodiments include forming a first solder resist layer560over the fourth layer550and the sixth conductive layer516, and forming a second solder resist layer560over the first layer530and the underlying layer508. However, it is to be appreciated that any number of layers of dielectric layers and conductive layers may be formed between the magnetic second layer525and the solder resist layer560. In an embodiment, the solder resist layers560may be formed with any suitable process. For example, the solder resist layer560may be formed with a lamination process.

Referring now toFIG. 5E, a cross-sectional illustration after openings521are formed through the solder resist layers560is shown, in accordance with an embodiment. In an embodiment, the solder resist openings521may be formed with any suitable process, such as laser drilling, or the like. The solder resist openings521may be formed through the solder layers560to expose portions of conductive layers (e.g., the sixth conductive layer516and the underlying layer508). In an additional embodiment, an opening521may also be formed through solder resist layer560to expose a portion of the first layer530. For example, an opening521may be formed to expose a portion of the first layer530proximate to the passive device trace523.

Referring now toFIG. 5F, a cross-sectional illustration after a magnetic block526is formed is shown, in accordance with an embodiment. In an embodiment, the magnetic block526may be formed with a printing process. As such, there is no need for etching a magnetic material to form the magnetic block526. In an embodiment, the magnetic block526may be a portion of a passive device520integrated into the package. In an embodiment, the passive device520may be an inductor. In the illustrated embodiment, the inductor520may include a conductive trace523that is surrounded by magnetic material from the second layer525and the magnetic block526. In an embodiment a surface finish519may be applied to the exposed surfaces of the sixth conductive layer516and the underlying layer508. In an embodiment, the inductor may be a transmission line inductor, a spiral inductor, or a solenoid inductor.

Referring now toFIGS. 6A-6I, cross-sectional illustrations of a process flow for forming an electronic package with an embedded magnetic layer is shown, in accordance with an embodiment. Referring now toFIG. 6A, a cross-sectional illustration of a dummy core605after first and second conductive layers611and612are formed is shown, in accordance with an embodiment. In an embodiment, the dummy core605may include film layers606and607. The first conductive layer611may then be formed over the films607. In an embodiment the first conductive layer611may include conductive traces and pads. For example, the first conductive layer611may include a conductive trace623for use in a passive component. The second conductive layer612may be formed over the first conductive layer. The second conductive layer612may include conductive pillars. The first and second conductive layers611and612may be formed with a lithography process. As such, sidewalls of the first and second conductive layers611and612may be substantially vertical.

Referring now toFIG. 6B, a cross-sectional illustration after a first barrier layer645and a magnetic layer625are formed over the first and second layer611and612is shown, in accordance with an embodiment. In an embodiment, the first barrier layer645may be a conformal layer over the conductive layers. For example, the first barrier layer645may be formed in direct contact with sidewalls and planar surfaces of the first conductive layer611and the second conductive layer612.

After the first barrier layer645is formed, a magnetic layer625may be formed over the first barrier layer645. In an embodiment, the magnetic layer625may comprise a dielectric material with magnetic filler particles. In an embodiment, the magnetic layer625may be laminated over the first barrier layer645or it may be deposited as a liquid and cured. In an additional embodiment, the first barrier layer645may be laminated over a surface of the magnetic layer625prior to them being deposited onto the package. In such embodiments, the combined stack of the first barrier layer645and the magnetic layer625may be laminated over the conductive layers with a single process. In an embodiment, the magnetic layer625may be deposited to have a thickness above a top surface of the second conductive layer612, and then be planarized with a top surface of the second conductive layer612.

Referring now toFIG. 6C, a cross-sectional illustration after a second barrier layer640is formed is shown, in accordance with an embodiment. In an embodiment, the second barrier layer640may comprise a dielectric material. Some embodiments may include a second barrier layer640that is a PID. In an embodiment, the second barrier layer640may be formed with a lamination process or any other suitable deposition process. The second barrier layer640may be formed over and in direct contact with the magnetic layer625. As such, after the formation of the second barrier layer640, the magnetic layer625is completely embedded and protected from subsequent processing environments. Particularly, embodiments include a magnetic second layer625that is in direct contact with the first barrier layer645and the second barrier layer640.

In an embodiment, a third conductive layer613may be formed through the second barrier layer640. For example, the third conductive layer613may comprise a plurality of vias. The via openings may be formed with any suitable process, such as laser drilling or photolithography. In embodiments where laser drilling is used, a desmear process may also be needed. However, since the magnetic layer645is protected by the second barrier layer640, there is no contamination issue, as described above. Similarly, the third conductive layer613may be plated (e.g., with an electroless or electrolytic plating process) without contamination issues.

In an embodiment, a fourth conductive layer614may be formed over a surface of the second barrier layer640. The fourth conductive layer614may be formed with any suitable processes, such as electroless or electrolytic plating, photolithography processes, or the like. The fourth conductive layer614may include conductive traces and pads, such as pads formed over the third conductive layer613.

Referring now toFIG. 6D, a cross-sectional illustration after a buildup layer650is formed is shown, in accordance with an embodiment. In an embodiment, the buildup layer650may comprise a dielectric material. In an embodiment, the buildup layer650may be a different material than the barrier layer640. In some embodiments, the buildup layer650may be the same material as the second barrier layer640. Embodiments include forming a fifth conductive layer615in the buildup layer650. The fifth conductive layer615may include conductive vias. For example, the fifth conductive layer615and the buildup layer650may be formed with typical semi-additive processes (SAP), additive processes, or any other suitable process. In an embodiment, a sixth conductive layer616may be formed over the top surface of the buildup layer650. The sixth conductive layer616may include conductive pads and traces. The sixth conductive layer may be formed with any suitable process, such as an additive process, a SAP process, or the like. It is to be appreciated that since the magnetic layer625is protected by the barrier layer640, there is no contamination issue during the processes used to form the buildup layer650or any of the conductive layers.

Referring now toFIG. 6E, a cross-sectional illustration after the dummy core605is removed is shown, in accordance with an embodiment. In an embodiment, the dummy core605may be detached with any suitable detaching process. As illustrated, the detach process may result in the film607remaining on the underside of the package. InFIG. 6Ea single package is shown. However, it is to be appreciated that the dummy core detach results in both the top-side package and the bottom-side package being released. From here on in the Figures, only one of the detached packages is illustrated for clarity.

Referring now toFIG. 6F, a cross-sectional illustration after the film607is removed is shown, in accordance with an embodiment. In an embodiment, the film607may be removed with a wet etching process. As shown, the removal of the film607results in the exposure of the first conductive layer611and portions of the first barrier layer645. The first barrier layer645protects the magnetic layer625from the processing environments and prevents contamination of etching baths.

Referring now toFIG. 6G, a cross-sectional illustration after a solder resist layer660is formed over a top surface and a bottom surface of the package is shown, in accordance with an embodiment. Embodiments include forming a first solder resist layer660over the buildup layer650and the sixth conductive layer616, and forming a second solder resist layer660over the first conductive layer611and the first barrier layer645. However, it is to be appreciated that any number of layers of dielectric layers and conductive layers may be formed between the magnetic layer625and the solder resist layer660. In an embodiment, the solder resist layers660may be formed with any suitable process. For example, the solder resist layer660may be formed with a lamination process.

Referring now toFIG. 6H, a cross-sectional illustration after openings621are formed through the solder resist layers660is shown, in accordance with an embodiment. In an embodiment, the solder resist openings621may be formed with any suitable process, such as laser drilling, or the like. The solder resist openings621may be formed through the solder layers660to expose portions of conductive layers (e.g., the sixth conductive layer616and the first conductive layer611). In an additional embodiment, an opening621may also be formed through solder resist layer660to expose the passive device trace623and a portion of the first barrier layer645immediately adjacent to the passive device trace623.

Referring now toFIG. 6I, a cross-sectional illustration after magnetic block626is formed is shown, in accordance with an embodiment. In an embodiment, the magnetic block626may be formed with a printing process. As such, there is no need for etching a magnetic material to form the magnetic block626. In an embodiment, the magnetic block626may be a portion of a passive device620integrated into the package. In an embodiment, the passive device620may be an inductor. In the illustrated embodiment, the inductor620may include a conductive trace623that is surrounded by magnetic material from the magnetic layer625and the magnetic block626. In an embodiment a surface finish619may be applied to the exposed surfaces of the sixth conductive layer616the first conductive layer611, passive device trace623. In an embodiment, the inductor620may be a transmission line inductor, a spiral inductor, or a solenoid inductor.

Referring now toFIG. 7, a cross-sectional illustration of a packaged system790is shown, in accordance with an embodiment. In an embodiment, the packaged system790may include a die740electrically coupled to a package substrate770with solder bumps743. In additional embodiments, the die740may be electrically coupled to the package substrate770with any suitable interconnect architecture, such as wire bonding or the like. The package substrate770may be electrically coupled to a board, such as a printed circuit board (PCB) with solder bumps773or any other suitable interconnect architecture, such as wire bonding or the like.

In an embodiment, an inductor720similar to embodiments described above may be integrated into the package substrate770or the board780, or the package substrate770and the board780. Embodiments include any number of inductors720formed into the package substrate770and the board780. For example, a plurality of inductors720may be integrated into the circuitry of the package substrate770or the board780, or the package substrate770and the board780for power management, filtering, or any other desired use.

FIG. 8illustrates a computing device800in accordance with one implementation of the invention. The computing device800houses a board802. The board802may include a number of components, including but not limited to a processor804and at least one communication chip806. The processor804is physically and electrically coupled to the board802. In some implementations the at least one communication chip806is also physically and electrically coupled to the board802. In further implementations, the communication chip806is part of the processor804.

The processor804of the computing device800includes an integrated circuit die packaged within the processor804. In some implementations of the invention, the integrated circuit die of the processor may be communicatively coupled to an organic electronic package that includes an inductor surrounded by magnetic material, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip806also includes an integrated circuit die packaged within the communication chip806. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be communicatively coupled to an organic electronic package that includes an inductor surrounded by magnetic material, in accordance with embodiments described herein.

Example 1 includes an electronic package, comprising: a first layer, wherein the first layer comprises a dielectric material; a second layer over the first layer, wherein the second layer comprises a magnetic material; a third layer over the second layer, wherein the third layer comprises a dielectric material, and wherein the third layer entirely covers a first surface of the second layer; and a first conductive layer and a second conductive layer embedded within the second layer, wherein sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

Example 2 includes the electronic package of Example 1, wherein the first layer is a photoimageable dielectric (PID).

Example 3 includes the electronic package of Example 1 or Example 2, wherein an opening through the first layer exposes a surface of the first conductive layer.

Example 4 includes the electronic package of Examples 1-3, wherein the second conductive layer comprises a vertical pillar.

Example 5 includes the electronic package of Example 1-4, further comprising: a magnetic block formed on a surface of the first layer opposite from the second layer.

Example 6 includes the electronic package of Example 1-5, wherein the first conductive layer comprises a conductive trace between the magnetic block and the second layer.

Example 7 includes the electronic package of Example 1-6, further comprising: an inductor, wherein the inductor comprises portions of the first conductive layer, the second layer, and the magnetic block, and wherein the inductor is a transmission line inductor, a spiral inductor, or a solenoid inductor.

Example 8 includes the electronic package of Example 1-7, further comprising: a fourth layer over the third layer, wherein the fourth layer is a dielectric material.

Example 9 includes the electronic package of Example 1-8, further comprising: a third conductive layer through the third layer; a fourth conductive layer over the third layer; a fifth conductive layer in the fourth layer; and a sixth conductive layer over the fourth layer.

Example 10 includes the electronic package of Example 1-9, further comprising a first solder resist layer over the fourth layer, wherein openings are formed into the solder resist layer to expose portions of the fifth conductive layer.

Example 11 includes the electronic package of Example 1-10, further comprising: a second solder resist layer over a surface of the first layer opposite the second layer.

Example 12 includes the electronic package of Example 1-11, further comprising: a conductive layer through the first layer, wherein the second solder resist comprises an opening to expose a portion of the conductive layer.

Example 13 includes the electronic package of Example 1-12, wherein the electronic package is a coreless package.

Example 14 includes an electronic package, comprising: a first layer, wherein the first layer comprises a magnetic material; a first conductive layer and a second conductive layer embedded within the first layer; a first barrier layer along a bottom surface of the first layer and along sidewall surfaces of the first layer, wherein the first barrier layer separates the first layer from the first conductive layer and the second conductive layer; and a second barrier layer over a top surface of the first layer.

Example 15 includes the electronic package of Example 14, wherein sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

Example 16 includes the electronic package of Example 14 or Example 15, wherein a thickness of the first barrier layer is less than a thickness of the second barrier layer.

Example 17 includes the electronic package of Example 14-16, further comprising: a third conductive layer through the second barrier layer; a fourth conductive layer over the second barrier layer; a buildup layer over the second barrier layer, wherein the buildup layer comprises a dielectric material; a fifth conductive layer through the buildup layer; and a sixth conductive layer over the buildup layer.

Example 18 includes the electronic package of Example 14-17, further comprising: a first solder resist layer over the buildup layer; and a second solder resist layer contacting a portion of the first barrier layer.

Example 19 includes the electronic package of Example 14-18, further comprising: a magnetic block formed on through an opening in the second solder resist layer; and an inductor comprising portions of the first conductive layer, the first layer, and the magnetic block.

Example 20 includes the electronic package of Example 14-19, wherein the electronic package is a coreless package.

Example 21 includes a method of forming an electronic package, comprising: forming a first conductive layer over a dummy core; forming a second conductive layer over the first conductive layer with a lithographic process; forming a first barrier layer over exposed surfaces of the first conductive layer, the second conductive layer, and the dummy core; forming a first layer over the first barrier layer, wherein the first layer comprises a magnetic material, and wherein a top surface of the first layer is substantially coplanar with a top surface of the second conductive layer; and forming a second barrier layer over the first layer and the second conductive layer, wherein the first barrier layer and the second barrier layer entirely surround portions of the first layer.

Example 22 includes the method of claim21, wherein the first layer and the first barrier layer are laminated together prior to being disposed over exposed surfaces of the first conductive layer, the second conductive layer, and the dummy core.

Example 23 includes the method of Example 21 or Example 22, wherein a portion of the first layer forms a portion of an inductor in the electronic package.

Example 24 includes an electronic package, comprising: a coreless package substrate, wherein the coreless package substrate includes a magnetic layer, wherein portions of the magnetic layer are entirely surrounded by a first barrier layer and second barrier layer; and a die affixed to the coreless package.

Example 25 includes the electronic package of Example 24, further comprising: an inductor on or embedded in the coreless package substrate, wherein at least a portion of the inductor includes the portions of the magnetic layer that is entirely surrounded by the first barrier layer and the second barrier layer.