Interleaved input signal path for multiplexed input

System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner. In another embodiment, the command path includes a plurality of command latches that latch commands from the input signals in an interleaved manner and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner.

TECHNICAL FIELD

Embodiments of the invention relate generally to an input signal path for multiplexed signal lines, and more specifically, to an input signal path having separate command and address paths.

BACKGROUND OF THE INVENTION

As known, conventional NAND flash memory devices typically multiplex input/output (I/O) lines for receiving command, address, and data signals. Some commands, such as a program (i.e., write) command, require all three different types of information to be provided to the memory device. That is, in order to program memory cells with new data, a write command is issued, then the address of the memory cells that will be programmed is provided, and finally, data to be programmed is provided. A confirmation command is typically issued after the data is provided to the memory device indicating the end of the command. All of this information is provided to the memory device using the same I/O lines.

Control signals are used to differentiate the types of signals when latching the different information into the memory device. For example, typical control signals CLE and ALE are brought to a HIGH logic level to indicate to the memory device that the signals that will be latched in response to the next rising edge of a write enable signal (WE#) are either a command or an address, respectively. Thus, when the CLE signal is HIGH (and the ALE signal is LOW), the signals latched from the I/O lines in response to a rising edge of the WE# signal represent a command. In contrast, when the ALE signal is HIGH (and the CLE signal is LOW), the signals latched from the I/O lines in response to a rising edge of the WE# signal represent an address. When both the CLE and ALE signals are LOW, the signals latched from the I/O lines in response to a rising edge of the WE# signal represent data.

FIG. 1illustrates a conventional input signal path100for receiving and internally routing commands and addresses that are latched by a data latch108from signals applied to a DQ pad and buffer104. The DQ pad and buffer104represents the I/O signal lines to which external command, address, and data signals are applied to the memory. The signals are latched by the data latch108in response to the WE# signal, and commands and addresses are provided to a command decoder112and column address latches122-127, respectively, which are all coupled to an output of the data latch108. Conventional clock logic118generates various internal clock signals and pulses in response to the CLE, ALE and WE# signals to clock the address latches122-127and clock a command state machine116to generate internal control signals for executing the command in response to receiving the internal command signals from the command decoder112. Gating logic120,130,140,150,160are used to couple Clk_add—1st-Clk_add—5th signals to respective address latches122-127when an active enable signal is output by the command state machine116. The enable signal is active for commands that require latching of addresses, for example, read and program commands.

As will be explained in more detail below, the input signal path100is shown to receive an address having five parts over five WE# clock cycles, each part including up to 8 bits of the total address. As shown, the address latch122is clocked by the Clk_add—1st signal to latch bits0-7(eight bits) of a first part of the address, the address latch123is clocked by the Clk_add—2nd signal to latch bits0-3(four bits) of a second part of the address, the address latches124,125are clocked by the Clk_add—3rd signal to latch bits0-5(six bits) and bits6-7(two bits), respectively, of the third part of the address, the address latch126is clocked by the Clk_add—4th signal to latch bits0-7(eight bits) of the fourth part of the address, and the address latch127is clocked by the Clk_add—5th signal to latch bits0-1(two bits) of the fifth part of the address.

FIG. 2is a timing diagram of various signals of the input signal path100during a page read operation. At time T1 the CLE signal transitions HIGH to indicate to the memory that the signals provided to the DQ pad and buffer104(represented inFIG. 2as Padq signals) at the next rising edge of the WE# signal represent a command. The command signals are provided to the DQ pad and buffer104shortly after the CLE signal goes HIGH and the WE# signal transitions HIGH at time T2 to clock the data latch108to latch the signals at the DQ pad and buffer104. As shown inFIG. 2, the command provided to the memory is a page read command00H. After a response and propagation delay of the data latch108, the latched00H command is output by the data latch108(represented inFIG. 2as the Dqin signals) to the command decoder112at time TA. The command decoder112decodes the00H command and generates internal command signals (not shown) to be provided to the command state machine116. The command state machine116receives the internal command signals and begins generating internal control signals in response to a ltcmd pulse at times TB-TC. The ltcmd signal is generated in response to the previous clock cycle of the WE# signal and the HIGH CLE signal.

During the time the data latch108is latching the00H command, the command decoder112is generating the internal command signals, and the command state machine116begins generating internal control signals at time TB, the CLE signal provided to the memory is transitioned LOW at time T3 and the ALE signal is transitioned HIGH at time T4 to indicate that the signals provided to the memory on DQ pad and buffer104at the next rising edge of the WE# signal represent addresses. As shown inFIG. 2, the address provided to the memory is the first address A1of five parts of addresses (i.e., A1-A5). The rising edge of the WE# signal at time T5 clocks the data latch108and shortly thereafter at time TD the latched address is output at time TD. The Clk_add—1st pulse is HIGH at times TE-TF to clock the address latch122to latch bits0-7of the A1address.

Before the next rising edge of the WE# signal at time T6 (ALE continues to be HIGH), the signals provided to the DQ pad and buffer104are changed to the second address A2of the five part address. The A2address is latched by the data latch108in response to the rising edge of the WE# signal at time T6 . The signals provided to the DQ pad and buffer104are latched, and after a response and propagation delay, the A2address is output by the data latch108at time TG. The Clk_add—2nd pulse at times TH-TI clocks the address latch123to latch bits0-3of the A2address.

The third through fifth addresses A3-A5are latched in a similar manner by the rising edges of the WE# signal at times T7-T9, with the rising edge of the WE# signal clocking the data latch108to latch the A3address at time T7 (with the A3address available at time TJ to be latched by address latches124,125in response to the Clk_add—3rd pulse at times TK-TL), the rising edge of the WE# signal clocking the data latch108to latch the A4address at time T8 (with the A4address available at time TM to be latched by address latch126in response to the Clk_add—4th pulse at times TN-TO), and the rising edge of the WE# signal clocking the data latch108to latch the A5address at time T9(with the A5address available at time TP to be latched by address latch127in response to the Clk_add—5th pulse at times TQ-TR). At time T10, the ALE signal is transitioned low indicating that no more addresses will be provided to the memory.

At time T11, the CLE signal is transitioned HIGH to indicate that another command will be provided to the memory over the DQ pad and buffer104. A confirmation command (i.e.,30H) is issued to the memory to indicate the end of the current command. At the next rising edge of the WE# signal at time T12, the30H command is latched by the data latch108and the CLE signal is transitioned LOW at time T13 to end provision of the current command. With the30H command latched at T12, the output of the data latch108provides the30H command at time TS to the command decoder112. The command decoder112decodes the30H command and generates internal command signals. In response to the ltcmd pulse at times TT-TU, the command state machine116inputs the internal command signals and generates corresponding internal control signals. A status command (70H) is also issued to the memory by transitioning the CLE signal HIGH at time T14 and providing a70H command prior to the next rising edge of the WE# signal. The data latch108is clocked by the rising edge of the WE# signal at time T15 to latch the70H command. Soon after latching, the output of the data latch108provides the70H command to the command decoder112at time TV. Internal command signals are generated and are provided to the command state machine116, which inputs the internal command signals in response to the ltcmd pulse at times TW-TX.

In programming data to the memory, the time for the program operation to complete can be divided into three different time ranges: (1) command and address writing time, (2) data loading time, and (3) programming time. Using an example of a write cycle time tWC of 35 ns (i.e., the period of the WE# signal), the three time ranges can typically be about 245 ns (i.e., 7×35 ns) for command and address writing time, 150 us for the programming time, and assuming that data for a full page is being loaded (further assuming a page is 2 kbytes and a byte-wide I/O lines), 71.7 us (i.e., 35 ns×2 kbytes) for the data loading time. As illustrated by the present example, the command and address writing time is nearly negligible, but the data loading time can be almost one-third of the total time for the program operation to complete.

In an effort to decrease the overall time for a program operation to complete, which is considered desirable, manufacturers are allows the use of shorter tWC to reduce the data loading time. A small decrease in tWC may have a relatively large impact where considerable data, such as data for an entire page, is being loaded. However, as the allowable tWC is decreased, internal timing margins of the memory may be decreased as well, raising potential issues with proper operation. This can be illustrated with reference to the timing diagram ofFIG. 2. Although the timing diagram ofFIG. 2is directed to a page read command, decreasing tWC affects the internal timing margins of both read and program operations.

As previously discussed, the Dqin signal represents the output of the data latch108, to which the command decoder112/command state machine116and address latches122-127are coupled. As known, the command decoder112/command state machine116and the address latches122-127need to receive and latch the respective data before the output of the data latch108changes in response to latching of signals at the next rising edge of the WE#. As shown inFIG. 2, the output of the data latch108generally transitions after a time of tWC. As previously described, pulses of the ltcmd signal are used to clock the command state machine116and pulses of the Clk_add—1st-Clk_add—5th signals are used to clock the address latches122-127. The pulses of the ltcmd and Clk_add—1st-Clk_add—5th signals are generated in response to the previous rising edge of the WE# signal. For example, pulses202,214, and216of the ltcmd signal are generated in response to the rising edges of the WE# signal at time T2, T13, and T15, respectively, to latch the commands00H,30H, and70H from Dqin. Pulses204-212of the Clk_add—1st-Clk_add—5th signals are generated in response to the rising edges of the WE# signal at times T5-T9, respectively, to latch addresses A1-A5from Dqin.

For command and addresses to be accurately latched from Dqin, the pulses must occur at a time when the Dqin signals are stable. As known, the timing of pulses (i.e., when the pulses occur) and pulse width can vary slightly due to changes in temperature and supply voltage. To accommodate variations in timing and pulse width, the pulses occur after a minimum internal set-up time after a transition of the Dqin signals. The pulse width should be sufficient to clock a latch circuit to latch the signals, but leave a minimum internal hold time before a next transition of the Dqin signals. With reference toFIG. 2, and for the pulse202clocking the command state machine116, the set-up time is between TA-TB, the pulse width between TB-TC, and the hold time between TC-TD. As for the pulse204clocking the address latch122, the set-up time is between TD-TE, the pulse width between TE-TF, and the hold time between TF-TG. The set-up, pulse width, and hold times for the pulses204-216are generally the same as for the pulses202and204.

As a shorter tWC is used (resulting in a shorter period of WE#) to reduce data load time, as previously discussed, the set-up time, hold time, pulse width or all three will also be reduced, thus, reducing the timing margin for accurately latching the command, address, and data signals. As a result, a lower limit to tWC exists due to the variations in the timing and pulse width of the latch pulses. In order for tWC to be further reduced, there is a need for a input signal path that provides timing margin for latching input signals provided to a memory while allowing the use of a shorter tWC.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 3illustrates an input signal path300according to an embodiment of the present invention. The input signal path300includes components that were previously described with reference to the input signal path100ofFIG. 1. In contrast to the input signal path100, however, the input signal path300includes separate signal paths for latching commands and addresses. Each signal path includes a plurality of data latches that are operated in an interleaved fashion to provide greater internal timing margin, as will be explained in more detail below. The signal path for commands includes an even command signal path, represented by a data latch304and command decoder308, and further includes an odd command signal path, which is represented by a data latch312and command decoder314. The data latches304and312are clocked by clock signals clk1and clk2, that are generated by a clock logic318in response to the WE# signal and a HIGH CLE signal. Internal command signals generated by the command decoders308,314are provided to a command state machine316that is clocked by command latch signals ltcmd_e and ltcmd_o, which are used to clock-in the internal signals from the even command signal path and the odd command signal path, respectively.

The signal path for addresses includes even and odd data latches320and324that are clocked by clock signals clk3and clk4. The clk3and clk4signals are generated by the clock logic318in response to the WE# signal and a HIGH ALE signal. The data latches320,324output the latched address signals to an appropriate address latch122-127. As with the input signal path100(FIG. 1), each of the address latches122-127is coupled to receive particular bits of the address signals and are clocked by a respective clock signal to latch the correct address information provided to the memory over five WE# clock cycles. Namely, the address latch122latches bits0-7from the A1signals in response to the Clk_add—1st signal, the address latch123latches bits0-3from the A2signals in response to the Clk_add—2nd signal, the address latch124latches bits0-5and the address latch125latches bits6and7from the A3signals in response to the Clk_add—3rd signal, the address latch126latches bits0-7from the A4signals in response to the Clk_add—4th signal, and the address latch127latches bits0and1from the A5signals in response to the Clk_add—5th signal. In contrast to the input signal path100, the address latches122-127of the input signal path300are coupled to receive the address bits from one of the two data latches320,324, instead of having all the address latches122-127coupled to the single data latch108.

Operation of the input signal path300will be described with reference to the timing diagram ofFIG. 4. The timing diagram ofFIG. 4illustrates similar signals to the timing diagram ofFIG. 2, but further includes alternative and additional signals during operation of the input signal path300. For example, the output for the four data latches304,312,320,324(corresponding to Dqin_cmd_e, Dqin_cmd_o, Dqin_addr_e, and Dqin_addr_o) are illustrated inFIG. 4, whereas only Dqin is shown inFIG. 2.FIG. 4also illustrates clk1-clk4signals used to clock the data latches304,312,320,324, and instead of one command latch signal ltcmd, two command latch signals ltcmd_e and ltcmd_o are used to clock the command state machine316. The clock and latch signals are generated by the clock logic318which is conventional in design and operation. It will be appreciated that such clock logic can be designed by those ordinarily skilled in the art based on an understanding obtained by the description provided herein.

Turning toFIG. 4, at time T1 the CLE is transitioned HIGH to indicate to the memory that the signals provided to the Dq pad and buffer104(represented inFIG. 4as signals Padq) at the next rising edge of the WE# signal represent a command. The signals are provided to the DQ pad and buffer104shortly after the CLE signal goes HIGH and the WE# signal transitions HIGH at time T2 to receive the signals at the DQ pad and buffer104. As shown inFIG. 4, the command provided to the memory is a page read command00H. As previously discussed, the clock logic318generates clk1-clk4signals to clock the data latches304,312,320, and324. As shown inFIG. 4, the clk1and clk2signals alternate in response to the WE# signal and a HIGH CLE signal to alternately clock the data latch304of the even command signal path and the data latch312of the odd command signal path. Assuming that the even command signal path is the next one to latch the input signals, the clk1signal transitions HIGH at time T2 in response to the HIGH CLE signal and the WE# signal to clock the data latch304and latch the00H command applied to the DQ pad and buffer104. After a response and propagation delay of the data latch304, the latched00H command is output by the data latch304(represented inFIG. 4as the Dqin_cmd_e signals) to the command decoder308at time TA. The command decoder308decodes the00H command and generates internal command signals (not shown) to be provided to the command state machine316. The command state machine receives the internal command signals and begins generating internal control signals in response to a ltcmd_e pulse at times TB-TC. The ltcmd_e signal is generated in response to the previous clock cycle of the WE# signal and the HIGH CLE signal.

During the time the data latch304is latching the00H command, the command decoder308is generating the internal command signals, and the command state machine316begins generating internal control signals at time TB, the CLE signal provided to the memory is transitioned LOW at time T3 and the ALE signal is transitioned HIGH at time T4 to indicate that the signals provided to the memory on DQ pad and buffer104at the next rising edge of the WE# signal represent addresses. As shown inFIG. 4, the address provided to the memory is the first address A1of five parts of addresses (i.e., A1-A5). The clk3and clk4signals clock the data latches320,324, respectively, to alternately latch signals at the DQ pad and buffer104. Assuming that data latch320is the next latch to be clocked, the clk3signal has a rising edge at time T5 that corresponds to the rising edge of the WE# signal. The clk3signal clocks the data latch320and shortly thereafter at time TD the latched address is output (represented inFIG. 4as Dqin_addr_e signals). The Clk_add—1st pulse is HIGH at times TE-TF to clock the address latch122to latch bits0-7of the A1address. The timing of the Clk_add—1st pulse-Clk_add—4th pulse and the operation of the address latches122-127are as previously described with respect to the input signal path100ofFIG. 1.

Before the next rising edge of the WE# signal at time T6 (ALE continues to be HIGH), the signals provided to the DQ pad and buffer104are changed to the second address A2of the five parts of addresses. As previously discussed, generation of the clk3and clk4signals in response to the WE# signal is alternated to interleave latching of signals by the data latches320,324. The A1address was latched in response to the clk3signal. As a result, the A2address is latched by the data latch324in response to the clk4signal, which has a rising edge at time T6 corresponding to the rising edge of the WE# signal. After a response and propagation delay, the A2address is output by the data latch324(represented inFIG. 4by Dqin_addr_o). The Clk_add—2nd pulse at times TH-TI clocks the address latch123to latch bits0-3of the A2address.

The third through fifth addresses A3-A5are latched in a similar manner by the rising edges of the WE# signal at times T7-T9, with the clk3signal clocking the data latch320to latch the A3address at time T7 (with the A3address available at time TJ to be latched by address latches124,125in response to the Clk_add—3rd pulse at times TK-TL), the clk4signal clocking the data latch324to latch the A4address at time T8(with the A4address available at time TM to be latched by address latch126in response to the Clk_add—4th pulse at times TN-TO), and the clk3signal clocking the data latch320to latch the A5address at time T9(with the A5address available at time TP to be latched by address latch127in response to the Clk_add—5th pulse at times TQ-TR). As illustrated by the present example, the A1-A5addresses are latched by interleaving operation of the data latches320and324through alternating clk3and clk4signals in response to the WE# signal. At time T10, the ALE signal is transitioned LOW indicating that no more addresses will be provided to the memory.

At time T11, the CLE signal is transitioned HIGH to indicate that another command will be provided to the memory over the DQ pad and buffer104. As previously described, a confirmation command (i.e.,30H) is issued to the memory. At the next rising edge of the WE# signal at time T12, the30H command is latched by the data latch312in response to the clk2signal. As previously described, the previous command (00H) is latched by the data latch304in response to the clk1signal. Generation of the clk1and clk2signals in response to the WE# signal is alternated to interleave latching of commands. The CLE signal is transitioned low at time T13 to end provision of the current command. With the30H command latched at T12, the output of the data latch312(represented inFIG. 4as signals Dqin_cmd_o) provides the30H command at TS to the command decoder314. The command decoder314decodes the30H command and generates internal command signals. In response to the ltcmd_o pulse at times TT-TU, the command state machine316inputs the internal command signals and generates internal control signals in response.

A status command is also issued to the memory by transitioning the CLE signal HIGH at time T14 and providing a70H command prior to the next rising edge of the WE# signal. Since the data latch312of the odd command signal path latched the previously issued30H confirmation command, the data latch304of the even command signal path is clocked by the clk1signal at time T15 to latch the70H command. Soon after latching, the output of the data latch304provides the70H command to the command decoder308. Internal command signals are generated at time TV and are provided to the command state machine316, which inputs the internal command signals in response to the ltcmd_e pulse at times TW-TX.

Separating the input signal path into separate command and address signal paths and having even and odd signal paths that are operated in an interleaved manner, increase internal timing margin for latching commands and addresses. For example, with respect to the A1and A2addresses that are latched by the data latches320and324, respectively, the time over which the A1address can be latched is between times TD-TJ and the time over which the A2address can be latched is between times TG-TM. The internal set-up time (between TD-TE) and internal hold time (between TF-TJ) for the Clk_add—1st pulse at times TE-TF can be much longer since the A1address is available for a longer time compared to the conventional input signal path100. In the conventional input signal path100, the internal set-up time, internal hold time, and the Clk_add—1st pulse was limited to approximately one clock cycle of the WE# signal. In contrast, in the input signal path300the internal set-up time, internal hold-time, and the Clk_add—1st pulse is spread over approximately two clock cycles of the WE# signal because the latching of addresses is interleaved between the two data latches320,324. As a result, the next address either of the data latches320,324latches is occurs at every other rising edge of the WE# signal (due to alternating clk3and clk4signals, respectively) and not every rising edge of the WE# signal.

The same benefit previously described for the address input path is provided for commands latched by the data latches304and312. For example, the30H command and the70H command latched by the data latches312and304and decoded by the command decoders314, and308, all respectively, allow for an internal set-up time, internal hold time, and a pulse width to be spread over approximately two clock cycles of the WE# signal rather than being limited to one WE# clock cycle, as in the case of the input signal path100ofFIG. 1. As with the address input path of the input signal path300, each data latch304,312of the even and odd command signal paths can maintain the command at its output for a longer time since the soonest a subsequent command is latched by either data latch304,312occurs two WE# clock cycles later in response to the clk1, clk2signals, respectively.

The previous embodiment of the input signal path300has been described as including a command signal path having dual-interleaved signal paths and an address signal path having dual-interleaved signal paths. However, in alternative embodiments, the command signal path can have greater or fewer signal paths and the address signal path can have greater or fewer signal paths. For example, an alternative embodiment of the invention includes an address signal path having three-interleaved signal paths, each having a data latch for latching addresses provided to the memory, and further includes a separate data signal path having only one signal path with one data latch for latching commands. The present invention includes various embodiments having separate command and address signal paths, each of which can have different numbers of interleaved signal paths. Consequently, the previously discussed input signal path300ofFIG. 3is provided by way of example, and not intended to limit the present invention to the particular embodiment.

FIG. 5is a simplified block diagram of a portion of a flash memory500that includes an input signal path according to an embodiment of the present invention. As shown inFIG. 5, the memory500has been simplified to focus on features of the memory that are helpful in understanding the present invention. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. The memory500includes a memory array502having a plurality of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge for the non-volatile storage of data. Each of the cells can be electrically programmed on an individual basis by charging the floating gate. The rows of memory array502are arranged in blocks, where a memory block is some discrete portion of the memory array502. The memory cells generally can be erased in blocks. Data, however, may be stored in the memory array502in finer increments than a memory block. Row decoder and column decoder circuits530,534decode memory addresses to access the corresponding memory locations in the memory array502. Data register540and optional cache register542temporarily store data read from, or to be written to the memory array502.

Command, address and data signals are provided to an I/O control514on device bus516, which is multiplexed for receiving the various signals. The I/O control514includes data latches304,312,320, and324(FIG. 3). Which of the various signals are being received is determined by control signals518provided to a control logic528. In response to control signals518indicating that command signals are being provided on the device bus516to the I/O control514, the command signals are received by the I/O control514and provided to the control logic528via internal command bus522. The control logic528includes the command decoders308,314and the command state machine316. As previously discussed, commands are decoded and corresponding internal control signals are generated by the control logic528to perform the requested commands. In response to the control signals518indicating that address signals are being provided on the device bus516to the I/O control514, the address signals are received and the corresponding addresses are latched in an address register, which includes gating logic120,130,140,150,160and address latches122-127. A status register526is used to latch status information provided to it over an internal status bus527from the control logic528. The status information is generated by the control logic528in response to receiving a command requesting the status of an operation. Clock logic318is included in the control logic528, and as previously described, generates the appropriate clock signals to clock the data latches304,312,320,324, the command state machine316, and the address latches122-127.

The control logic528is coupled to a transistor532to provide a ready/busy signal R/B# that can be used for indicating the completion of various memory operations. The signal is typically HIGH, and transitions to LOW after a command is written to the device. When the current memory operation is completed, the R/B# signal transitions back to HIGH.

In operation, the memory array502can be accessed by providing a combination of control, command, and address signals. For example, to perform a read operation, a first combination of control signals518is provided to the control logic528to indicate that command signals are applied to the device bus516. The control logic528generates internal control signals for the I/O control514to receive the command signals and for the corresponding command to be latched in the command register528. The control logic528decodes the read command and begins to generate internal control signals for accessing the memory array502.

A second combination of control signals518is provided to the control logic528to indicate that address signals are applied to the device bus516. The control logic generates internal control signals for the I/O control514to receive the address signals and for the corresponding addresses to be latched in the address register512. The addresses are provided to a row decoder circuit530and a column decoder circuit534via an internal address bus524for decoding the addresses and accessing the memory locations corresponding to the latched addresses.

A page of memory cells having the memory locations to be accessed is read from the memory array502and stored in a data register540. The data from the page of memory is transferred to a secondary (and optional) cache register542before being provided to the I/O control514on an internal data bus544. The cache register can be used to temporarily store the page of data in order to free the data register540to store another page of data for a subsequent access operation of the memory array502. The page of data is transferred to the I/O control514from the cache register542. Based on the addresses, the appropriate data from the page of data is output on the device bus516.

A write operation occurs in a similar manner except that following the second combination of control signals a third combination of control signals are provided to the control logic528indicating that data to be written to the memory locations corresponding to the addresses is being provided on the device bus516. The data received by the I/O control514is provided on the internal data bus544to the cache register542for writing to the memory array502.

The flash memory500can be used in various electronic systems. For example, it may be used in a processor-based system, such as a processor-based system600shown inFIG. 6. In one embodiment, the processor-based system is an embedded system having an embedded memory such as the flash memory500. In another embodiment, the processor-based system600is a computer system including flash memory devices that include flash memory500.

The processor-based system600includes a processor602for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor602includes a processor bus604that normally includes an address bus, a control bus, and a data bus. The processor602is also typically coupled to cache memory626, for temporarily storing data, and further coupled to a memory620through a memory controller630. The memory620includes flash memory such as memory500. The memory controller630normally includes a control bus636and an address bus638that are coupled to the memory620. A data bus640is coupled from the memory620to the processor bus604either directly (as shown), through the memory controller630, or by some other means.

In embodiments where the processor-based system600represents a computer system, the system600further includes input devices614, such as a keyboard or a mouse, that are coupled to the processor602to allow a user to interface with the processor-based system600. Typically, the processor-based system600also includes one or more output devices616coupled to the processor602, such output devices typically being a printer or a video terminal. One or more data storage devices618are also typically coupled to the processor602to allow the processor602to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices618include hard disks, flash drives, compact and digital video disk read-only memories (CD- and DVD-ROMs).