Method for manufacturing semiconductor device

An alignment mark section on a semiconductor substrate has two grooves which are filled with silicon oxide. The surface of the portion of the semiconductor substrate sandwiched by these grooves is lower than other portions of the semiconductor substrate to produce a step having a predetermined depth in the alignment mark section.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a device formation section (or region) and an alignment mark section on a semiconductor substrate.

2. Background Art

In recent years, semiconductor devices have become smaller and smaller as their integration density has increased and each semiconductor region of the devices has been miniaturized. The transistor characteristics of a miniaturized semiconductor device is significantly affected by the alignment between the active regions and the gate electrodes, as described in detail below.

Each gate electrode (of a semiconductor device) is formed on a predetermined area of an active region. Therefore, when the gate electrode material is patterned, it is necessary to carry out the process of aligning the gate electrode material with the active regions.

One method for such alignment is to detect the alignment marks under the gate electrode material by passing light through the material. However, general-purpose memories such as DRAMs (Dynamic Random Access Memories), SRAM (Static Random Access Memories), and flash memories use polycide or polymetal as their gate electrode material, which makes it difficult to detect the alignment marks since these materials have a high light reflectance level.

To overcome the above problem, a step (or a height difference) is formed in the alignment mark section to facilitate the alignment, as described in Japanese Laid-Open Patent Publication No. 11-87488 (1999).

Description will be made of a conventional method for manufacturing a semiconductor device with referenceFIGS. 28to37. It should be noted that in these figures, like numerals will be used to denote like components.

First of all, a silicon oxide film62and a silicon nitride film63are sequentially formed on a semiconductor substrate61, as shown inFIGS. 28Ato28C. Then, active region patterns are formed on the semiconductor substrate61by use of a photolithographic technique. Specifically, first a resist pattern64is formed on the silicon nitride film63. It should be noted thatFIG. 28A,28B, and28C show the portions of the resist pattern (64) in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

Then, the silicon nitride film63is etched using the resist patterns64as a mask, forming a silicon nitride film pattern65as a hard mask. After removing the resist pattern64, which is no longer necessary, the semiconductor substrate61is etched using the silicon nitride film pattern65. Then, a silicon oxide film67is formed on the inside walls of grooves66by the thermal oxidation method, producing the structures shown inFIGS. 29Ato29C.

Then, a silicon oxide film68is formed on the silicon nitride film pattern65such that it fills the grooves66, and polished by the CMP (Chemical Mechanical Polishing) method, producing the structures shown inFIGS. 30Ato30C. In these figures, the top surface68aof the silicon oxide film68and the top surface65aof the silicon nitride film pattern65are in the same plane.

After wet-etching the silicon oxide film68by use of hydrofluoric acid, the silicon nitride film pattern65is removed since it is no longer necessary. This produces the structures shown inFIGS. 31Ato31C. These figures show a step(s)69having a height of h′ formed at the boundary between the silicon oxide film68and the silicon oxide film62.

Then, channel doping is applied to the semiconductor substrate61to set the well for each transistor and the transistor threshold value. Specifically, impurities of a first or second conductive type are ion-implanted in desired areas using resist patterns formed by a photolithographic technique as masks.

For example, as shown inFIGS. 32Ato32C, a resist pattern70is formed on all sections except for the NMOS region of the peripheral circuit section (shown in FIG.32C). Then, impurity ions are implanted in the NMOS region using the resist pattern70as a mask. After removing the resist pattern70, which is no longer necessary, a resist pattern71is formed on all sections except for the PMOS region of the peripheral circuit section (shown in FIG.33C), as shown inFIGS. 33Ato33C. Then, impurity ions are implanted in the PMOS region using the resist pattern71as a mask. After that, the resist pattern71is removed since it is no longer necessary. Then, as shown inFIGS. 34Ato34C, a resist pattern72is formed on all sections other than the memory cell section (shown in FIG.34B). After implanting impurity ions in the memory cell section using the resist pattern72as a mask, the resist pattern72is removed since it is no longer necessary.

After the above ion implantation, a resist pattern73is formed on all sections other than the alignment mark section, as shown inFIGS. 35Ato35C. Then, the silicon oxide films62,67, and68are removed through wet-etching using the resist pattern73as a mask. After that, the resist pattern73, which is no longer necessary, is removed, producing the structures shown inFIGS. 36Ato36C.

Furthermore, after removing the silicon oxide film62by wet-etching, a gate insulation film material74, a gate electrode material75, a hard mask material76, and a resist film77are laminated in that order, producing the structures shown inFIGS. 37Ato37C.

InFIGS. 37B and 37C, the surface of the silicon oxide film68buried in the grooves in the memory cell section and the peripheral circuit section and the surface of the gate insulation film material74formed on the semiconductor substrate61together form a substantially flat surface even though there exist some small steps at the boundary between them. Therefore, the surfaces of the gate electrode material75and the hard mask material76formed on the above substantially flat surface are also substantially flat.

On the other hand, as shown inFIG. 37A, since the silicon oxide film68is not formed on the groove in the alignment mark section, the gate insulation film material74, the gate electrode material75, and the hard mask material76are formed along the groove, forming a concave portion. That is, formation of such a big step (concave portion) in the alignment mark portion facilitates detection of the alignment marks. Therefore, the resist film77can be patterned at a desired position, allowing the gate electrodes to be formed at desired positions.

The above conventional method, however, requires the process shown inFIGS. 35 and 36to form a step in the alignment mark section. That is, after implanting ions in the peripheral circuit section and the memory cell section, a resist pattern having an opening over the alignment mark section must be formed, and then the silicon oxide films in the alignment mark section must be removed using the resist pattern as a mask. As a result, the total number of processes required greatly increases, leading to the problem of a reduction in the throughput, cost, yield, etc.

SUMMARY OF THE INVENTION

The present invention has been devised in view of the above problems. It is, therefore, an object of the present invention to provide a semiconductor device and a manufacturing method therefor capable of providing a reduced number of manufacturing processes required without reducing the alignment accuracy when the gate electrodes are formed.

According to one aspect of the present invention, in a method for manufacturing a semiconductor device, a first insulation film is formed on a semiconductor substrate of a first conductive type. A hard mask is formed on the first insulation film. The first insulation film and the semiconductor substrate are etched using the hard mask so as to form grooves having a predetermined depth in an alignment mark section and a device formation section of the semiconductor substrate. A second insulation film is buried into the grooves. The hard mask is removed. A resist pattern is formed on predetermined areas of the first and the insulation films. Impurities are ion-implanted in the semiconductor substrate using the resist pattern as a mask, the impurities being of at least one of first and second conductive types. The portion of the first insulation film exposed at (an opening of) the resist pattern, and the portion of the second insulation film corresponding to a film thickness of the first insulation film (and exposed at the opening of the resist pattern) are removed. The resist pattern is removed. A gate insulation film is formed on the semiconductor substrate. A gate electrode is formed on the gate insulation film. The resist pattern also has an opening over the alignment mark section. The series of steps from the resist pattern forming step to the resist pattern removing step are repeated to form a concave portion having a predetermined depth in the alignment mark section.

According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a first insulation film is formed on a semiconductor substrate of a first conductive type. A hard mask is formed on the first insulation film. The first insulation film and the semiconductor substrate are etched using the hard mask so as to form a groove in a device formation section of the semiconductor substrate and to form a first groove and a second groove in an alignment mark section of the semiconductor substrate, the groove and the first and second grooves having substantially a same predetermined depth. A second insulation film is buried into all the grooves formed in the device formation section and the alignment mark section. The hard mask is removed. A first resist pattern having openings is formed over the alignment mark section and a predetermined area of the device formation section. Impurities are ion-implanted in the semiconductor substrate using the first resist pattern as a mask, the impurities being of at least one of first and second conductive types. The portion of the first insulation film exposed at the first resist pattern is removed so as to expose the semiconductor substrate. The first resist pattern is removed. A second resist pattern which covers the area (the predetermined area) of the device formation section at which the semiconductor substrate is exposed is formed, the second resist pattern having openings over another predetermined area of the device formation section and an area sandwiched by the first and second grooves in the alignment mark section. Impurities are ion-implanted in the semiconductor substrate using the second resist pattern as a mask, the impurities being of at least one of the first and second conductive types. The portion of the semiconductor substrate exposed at the second resist pattern is electively etched to form a concave portion having a predetermined depth in the alignment mark section. The second resist pattern is removed. A gate insulation film is formed on the semiconductor substrate. A gate electrode is formed on the gate insulation film.

According to other aspect of the present invention, in a method for manufacturing a semiconductor device, a first insulation film is formed on a semiconductor substrate of a first conductive type. A hard mask is formed on the first insulation film. The first insulation film and the semiconductor substrate are etched using the hard mask so as to form grooves having a predetermined depth in an alignment mark section and a device formation section of the semiconductor substrate. A second insulation film is buried into the grooves. The hard mask is removed. A first resist pattern having openings is formed over the alignment mark section and a predetermined area of the device formation section. Impurities are ion-implanted in the semiconductor substrate using the first resist pattern as a mask, the impurities being of at least one of first and second conductive types. The portion of the first insulation film exposed at the first resist pattern is removed so as to expose the semiconductor substrate. The first resist pattern is removed. A second resist pattern which covers the area (the predetermined area) of the device formation section at which the semiconductor substrate is exposed is formed, the second resist pattern having openings over the alignment mark section and another predetermined area of the device formation section. Impurities are ion-implanted in the semiconductor substrate using the second resist pattern as a mask, the impurities being of at least one of the first and second conductive types. The portion of the semiconductor substrate exposed at the second resist pattern is selectively etched to form a convex portion having a predetermined height in the alignment mark section. The second resist pattern is removed. A gate insulation film is formed on the semiconductor substrate. A gate electrode is formed on the gate insulation film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

Description will be made of a method for manufacturing a semiconductor device according to a first embodiment of the present invention with reference toFIGS. 1to11. It should be noted that in these figures, like numerals will be used to denote like components.

As shown inFIGS. 1Ato1C, first a silicon oxide film2is formed on a semiconductor substrate1of a first conductive type as a first insulation film. Then, a silicon nitride film3is formed on the silicon oxide film2. The silicon nitride film3is used to form a hard mask.

A silicon substrate may be used as the semiconductor substrate1. Further, the silicon oxide film2may be formed by the thermal oxidation method such that it has a film thickness of approximately 20 nm. Still further, the silicon nitride film3may be formed by the CVD (Chemical Vapor Deposition) method such that it has a film thickness of approximately 100 nm.

Then, active region patterns are formed on the semiconductor substrate1by use of a photolithographic technique. Specifically, first a resist pattern4is formed on the silicon nitride film3.FIGS. 1A,1B, and1C show the portions of the resist pattern (4) in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. It should be noted that the memory cell section and the peripheral circuit section are hereinafter collectively referred to as the device formation section.

FIG. 2is a plan view of the alignment mark section. In the figure, a rectangular pattern5indicates the alignment mark. That is,FIG. 1Ais a cross-sectional view of the alignment mark section inFIG. 2taken along line A-A′, and the rectangular pattern5inFIG. 2corresponds to a groove6in FIG.1A.

Then, the silicon nitride film3is etched using the resist pattern4as a mask. After that, the resist pattern4is removed, producing the structures shown inFIGS. 3Ato3C. A silicon nitride film pattern7in these figures is used as a hard mask in the next process. It should be noted thatFIGS. 3A,3B, and3C show the portions of the silicon nitride film pattern7in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

Then, the silicon-oxide film2and the semiconductor substrate1are etched using the silicon nitride film pattern7as a mask, forming grooves8as shown inFIG. 4Ato4C. At that time, the etch depth may be set to approximately 300 nm, considering the withstand voltage for the separation. After that, a silicon oxide film9is formed on the inside walls of the grooves8by the thermal oxidation method, etc. The film thickness of the silicon oxide film9may be set to approximately 25 nm. It should be noted thatFIGS. 4A,4B, and4C show the grooves8in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

Then, a silicon oxide film10is formed on the silicon nitride film pattern7as a second insulation film such that it fills the grooves8. The silicon oxide film10may be formed by the CVD method, the SOG (Spin on Glass) method, etc. The silicon oxide film10is then polished by the CMP (Chemical Mechanical Polishing) method, producing the structures shown inFIGS. 5Ato5C. It should be noted thatFIGS. 5A,5B, and5C show the portions of the silicon oxide film (10) in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. In these figures, the top surface10aof the silicon oxide film10and the top surface7aof the silicon nitride film pattern7are in substantially the same plane.

Then, the silicon oxide film10is wet-etched by use of hydrofluoric acid, etc. At that time, the silicon oxide film10is preferably selectively etched until the height of its top surface10afrom the bottom surface of the silicon nitride film pattern7is reduced to a predetermined value. For example, the etching of the silicon oxide film10is stopped when the distance from the bottom surface of the silicon nitride film pattern7to the top surface10aof the silicon oxide film10is reduced to approximately between 10 nm and 20 nm. After that, the silicon nitride film pattern7, which is no longer necessary, is removed through wet-etching by use of phosphoric acid, producing the structures shown inFIGS. 6Ato6C. It should be noted thatFIGS. 6A,6B, and6C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. These figures show a step11having a height of h1formed at the boundary between the silicon oxide film10and the silicon oxide film2. It should be noted that if the step11is formed by adjusting the film thickness of the silicon nitride film pattern7, the above wet-etching process of the silicon oxide film10is not required.

Then, channel doping is applied to the semiconductor substrate1to set the well for each transistor and the transistor threshold value. Specifically, impurities of at least one of first and second conductive types are ion-implanted in desired areas using resist patterns formed by a photolithographic technique as masks.

According to the present embodiment, it is arranged that no resist pattern is formed also on the alignment mark section in the above process.

For example, description will be made of the process of implanting ions in the NMOS region of the peripheral circuit section with reference toFIGS. 7Ato7C. In this case, to implant ions in the NMOS region, a resist pattern12is not formed on the region, as shown in FIG.7C. On the other hand, as shown inFIG. 7B, the resist pattern12is formed on the memory cell section since ions should not be implanted in this section. As for the alignment mark section, as shown inFIG. 7A, the present embodiment does not form the resist pattern12on it even though ions need not be implanted therein.

Specifically, the resist pattern may be formed as follows. When a positive type resist is used, a mask is prepared which has a conventional mask pattern and furthermore an opening for letting light pass through to the alignment mark section. Then, the resist film is irradiated with light through the mask and developed, making it possible to form a resist pattern having openings over both the target implantation area and the alignment mark section.

Then, impurity ions are implanted in the NMOS region using the resist pattern12as a mask, as shown in FIG.7C. At that time, the impurity ions are also implanted in the alignment mark section, as shown in FIG.7A. However, no problem arises since they do not affect the transistor characteristics.

After implanting the ions, the portions of the silicon oxide films2,9, and10exposed at the openings of the resist pattern12are wet-etched by use of hydrofluoric acid, etc. before the resist pattern12is removed. Specifically, the etching is stopped when the exposed portion of the silicon oxide film2has been removed, as shown inFIGS. 8Ato8C. After that, the resist pattern12is removed since it is no longer necessary, producing the structures shown inFIGS. 9Ato9C. It should be noted thatFIGS. 9A,9B, and9C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. These figures (FIGS. 9A and 9C) show that the portion of the silicon oxide film2not covered with the resist pattern12has been removed, along with the portions of the silicon oxide films9and10corresponding to the film thickness of the silicon oxide film2.

Likewise, when ions are implanted in the PMOS region of the peripheral circuit section or in the memory cell section, a resist pattern is formed on the alignment mark section as well as the target implantation area.

After implanting the ions, the portions of the silicon oxide films2,9, and10exposed at the openings of the resist pattern are wet-etched before the resist pattern is removed. Specifically, the etching is stopped when the exposed portion of the silicon oxide film2(formed on the semiconductor substrate1) has been removed. At that time, the portions of the silicon oxide films9and10corresponding to the film thickness of the silicon oxide film2are also removed. Thus, a number of etching operations corresponding to the number of ion implantation operations (that is, the number of transistors) are performed on the alignment mark section.

According to the present embodiment, also in each target implantation area, the silicon oxide film2and the portions of the silicon oxide films9and10corresponding to the film thickness of the silicon oxide film2are removed at the same time (for example, see FIG.9C). However, even after the portion of the silicon oxide film10corresponding to the film thickness, of the silicon oxide film2has been removed, the surface of the silicon oxide film10is still higher than that of the semiconductor substrate1by h1since there exists the step11having a height of h1formed at the boundary between the surfaces of the silicon oxide film2and the silicon oxide film10, as shown in FIG.6. When the silicon oxide film10is removed by etching in a postprocess, this arrangement prevents the grooves8from being processed such that they have an inverse tapered shape in cross-section, thereby preventing deterioration of the electrical characteristics of the transistors.

It should be noted that the height of the step provided at the boundary between the surfaces of the silicon oxide film10and the semiconductor substrate1need not necessarily be equal to that of the step at the boundary between the surfaces of the silicon oxide film10and the silicon oxide film2(h1). That is, the same effect can be obtained if the surface of the silicon oxide film10has a height equal to or more than that of the surface of the semiconductor substrate1.

Repeating ion implantation and wet-etching as described above gradually etches the silicon oxide films9and10buried in the groove8in the alignment mark section. As a result, a concave portion17having a predetermined depth is produced in the alignment mark section.FIGS. 10A,10B, and10C illustrate this process, respectively showing the alignment mark section, the memory cell section, and the peripheral circuit section.

It should be noted that the entire silicon oxide films9and10in the alignment mark section may not necessarily be etched, as with the case shown in FIG.10A. However, if the depth of the concave portion17(that is, the height of the step at the boundary between the surface of the silicon oxide film9or10and that of the semiconductor substrate1) is 50 nm or more, the alignment mark can be adequately detected. It should be noted that the number of transistors generally formed in the above process is large enough to form a concave portion17having a depth of 50 nm or more.

Therefore, the present embodiment can eliminate the conventional process of forming a mask for etching only the alignment mark section by a photolithographic technique, making it possible to reduce the cost and the number of processes for manufacturing the semiconductor device.

After implanting ions in all predetermined areas and then removing the silicon oxide films in the alignment mark section, a gate insulation film material13, a gate electrode material14, a hard mask material15, and a resist film16are laminated in that order, producing the structures shown inFIGS. 11Ato11C. It should be noted thatFIGS. 11A,11B, and11C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. After patterning the resist film16by use of a photolithographic technique, the hard mask material15is etched using the patterned resist film16as a mask, forming a hard mask. After that, the gate electrode material14and the gate insulation film material13are etched using the hard mask, forming the gate insulation films and the gate electrodes.

It should be noted that after forming the hard mask material15, an antireflective film may be formed thereon. When the resist film formed on the antireflective film is patterned, the antireflective film absorbs the exposure light which has passed through the resist film, functioning to eliminate the reflection of the exposure light at the interface between the resist film and the antireflective film. A film mainly made of an organic substance and formed by the spin coat method, etc. may be used as the antireflective film.

As can be seen fromFIG. 11A, the width L of the concave portion17formed in the alignment mark section must satisfy formula (1) below.
L>(film thickness of gate insulation film material+film thickness of gate electrode material+film thickness of hard mask material)×2  (1)

According to the present embodiment described above, each resist pattern used for ion implantation is provided with openings over the alignment mark section as well as a target implantation area. With this arrangement, after the implantation, the silicon oxide films exposed at the openings of the resist pattern are removed before removing the resist pattern. This process is repeated, thereby gradually removing the (entire) silicon oxide films in the alignment mark section. As a result, a step having a height of 50 nm or more can be eventually formed. Thus, it is possible to eliminate the photolithographic process for etching only the alignment mark section and thereby reduce the cost and the number of processes for manufacturing the semiconductor device.

Second Embodiment

Description will be made of a method for manufacturing a semiconductor device according to a second embodiment of the present invention with reference toFIGS. 12to21. It should be noted that in these figures, like numerals will be used to denote like components.

First of all, as in the first embodiment, a silicon oxide film22is formed on a semiconductor substrate21of a first conductive type as a first insulation film. Then, a silicon nitride film23is formed on the silicon oxide film22. The silicon nitride film23is used to form a hard mask. A silicon substrate may be used as the semiconductor substrate21.

Then, active region patterns are formed on the semiconductor substrate21by use of a photolithographic technique. Specifically, first a resist pattern24is formed on the silicon nitride film23, producing the structures shown inFIGS. 12Ato12C. It should be noted thatFIGS. 12A,12B, and12C show the portions of the resist pattern (24) in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

FIG. 13is a plan view of the alignment mark section. As shown in the figure, the alignment mark of the present embodiment is made up of two rectangular patterns: a first rectangular pattern25and a second rectangular pattern26formed inside the first rectangular pattern25.FIG. 12Ais a cross-sectional view of the alignment mark section inFIG. 13taken along line B-B′. The first rectangular pattern25and the second rectangular pattern26correspond to grooves28and27inFIG. 12A, respectively.

Then, the silicon nitride film23is etched using the resist pattern24as a mask, forming a hard mask (not shown). Then, the silicon oxide film22and the semiconductor substrate21are etched using the hard mask, forming a plurality of grooves having substantially the same depth in the device formation section and the alignment mark section. According to the present embodiment, first and second grooves corresponding to the grooves27and28shown inFIG. 12Aare formed in the alignment mark section.

Then, a silicon oxide film29is formed on the inside walls of all formed grooves by the thermal oxidation method, etc. After that, as in the first embodiment, a silicon oxide film30is formed as a second insulation film such that it fills the above grooves. Then, the hard mask is removed, producing the structures shown inFIGS. 14Ato14C. It should be noted thatFIGS. 14A,14B, and14C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. These figures show a step31having a height of h2formed at the boundary between the silicon oxide film30and the silicon oxide film22. The step31may be formed in the same manner as in the first embodiment. For example, after burying the silicon oxide film30into the grooves, the silicon oxide film30may be selectively etched until the height of its top surface from the bottom surface of the hard mask is reduced to a predetermined value (between 10 nm and 20 nm). After that, the hard mask may be removed since it is no longer necessary.

Then, channel doping is applied to the semiconductor substrate21to set the well for each transistor and the transistor threshold value. Specifically, impurities of at least one of first and second conductive types are ion-implanted in desired areas using resist patterns formed by a photolithographic technique as masks. At that time, it is arranged that no resist pattern is formed also on the alignment mark section, as in the first embodiment.

For example, description will be made of the process of implanting ions in the NMOS region of the peripheral circuit section with reference toFIGS. 15Ato15C. In this case; to implant ions in the NMOS region, a resist pattern32(a first resist pattern) is not formed on the region, as shown in FIG.15C. On the other hand, as shown inFIG. 15B, the resist pattern.32is formed on the memory cell section since ions should not be implanted in this section. As for the alignment mark section, as shown inFIG. 15A, the present embodiment does not form the resist pattern32on it even through ions need not be implanted therein.

Then, impurity ions are implanted using the resist pattern.32as a mask. At that time, the impurity ions are also implanted in the alignment mark section. However, no problem arises since they do not affect the transistor characteristics.

After implanting the ions, the portions of the silicon oxide films22,30, and29exposed at the openings of the resist pattern32are wet-etched before the resist pattern32is removed. The wet-etching may be achieved by use of phosphoric acid, etc. After that, the resist pattern32, which is no longer necessary, is removed, producing the structures shown inFIGS. 16Ato16C. It should be noted thatFIGS. 16A,16B, and16C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

The above wet-etching is stopped when the exposed portion of the silicon oxide film22(formed on the semiconductor substrate21) has been removed, exposing the surfaces of the semiconductor substrate21in the alignment mark section and the NMOS region of the peripheral circuit section. At that time, the portions of the silicon oxide films29and30corresponding to the film thickness of the silicon oxide film22are also removed, along with the exposed portion of the silicon oxide film22. In the above process, a step31having a height of h2is formed at the boundary between the surface of the silicon oxide film22and that of the silicon oxide film30, as shown in FIG.14. Therefore, even after the portion of the silicon oxide film30corresponding to the film thickness of the silicon oxide film22has been removed, the surface of the silicon oxide film30is still higher than that of the semiconductor substrate21by h2. When the silicon oxide film30is removed by etching in a postprocess, this arrangement prevents the grooves formed by removing the oxide films from being processed such that they have an inverse tapered shape in cross-section, thereby preventing deterioration of the electrical characteristics of the transistors.

It should be noted that the height of the step provided at the boundary between the surfaces of the silicon oxide film30and the semiconductor substrate21need not necessarily be equal to that of the step at the boundary between the surfaces of the silicon oxide film30and the silicon oxide film22(h2). That is, the same effect can be obtained if the surface of the silicon oxide film30has a height equal to or more than that of the surface of the semiconductor substrate21.

Then, as shown inFIGS. 7Ato7C, ions are implanted in the PMOS region of the peripheral circuit section using a resist pattern33as a second resist pattern. In this case, it is arranged that the resist pattern33is not formed on the area of the alignment mark section sandwiched by first and second grooves39and40(shown in FIG.17A), as well as on the target implantation area (the PMOS region shown in FIG.17C). It should be noted that the resist pattern33is formed on the NMOS region in which the semiconductor substrate21has been exposed. That is, the resist pattern33covers the NMOS region (in which the semiconductor substrate21has been exposed) and has openings over the PMOS region and the area sandwiched by the first and second grooves39and40in the alignment mark section.

FIG. 18is a plan-view of the alignment mark section, andFIG. 17Ais a cross-sectional view of the alignment mark section inFIG. 18taken along line C-C′. As shown inFIG. 18, the resist pattern33is not formed on the area sandwiched by the first rectangular pattern25and the second rectangular pattern26. The first rectangular pattern25corresponds to the second groove40inFIG. 17A, while the second rectangular pattern26corresponds to the first groove39in FIG.17A.

After implanting ions in the PMOS region using the resist pattern33as a mask, as shown inFIG. 17C, the portion of the semiconductor substrate21exposed in the alignment mark section (shown inFIG. 17A) is wet-etched before the resist pattern33is removed. It should be noted that since the NMOS region is covered with the resist pattern33, the semiconductor substrate21in the NMOS region is not etched. The etching is achieved by use of a chemical solution capable of selectively etching the semiconductor substrate21. For example, if a silicon substrate is used as the semiconductor substrate21, aqueous ammonia may be used. By using such a solution, only the semiconductor substrate21exposed in the alignment mark section can be etched without etching the silicon oxide films22,29, and30exposed in the PMOS region, producing the structures shownFIGS. 19Ato19C. It should be noted thatFIGS. 19A,19B, and19C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

As a result, a concave portion (a step) having a predetermined depth is formed in the alignment mark section, as shown in FIG.19A. The depth h3of the concave portion is preferably set to a value large enough to detect the alignment mark, namely 50 nm or more.

When a silicon substrate is used as the semiconductor substrate21and aqueous ammonia is used for the etching, the bottom surface34of the groove formed in the alignment mark section has an arc-like shape in cross-section (downwardly concave around the center), as shown in FIG.19A. On the other hand, the silicon substrate may be dry-etched. In this case, a gas having a high selectivity ratio against the silicon oxide films may be used to produce a substantially flat bottom surface34, making it possible to further enhance the alignment accuracy.

After completing etching of the semiconductor substrate21in the alignment mark section, the resist pattern33is removed since it is no longer necessary. Then, a gate insulation film material35, a gate electrode material36, a hard mask material37, and a resist film38are laminated in that order, producing the structures shown inFIGS. 20Ato20C. It should be noted thatFIGS. 20A,20B, and20C show the alignment mark section, the memory cell section, and the peripheral circuit-section, respectively. After patterning the resist film38by use of a photolithographic technique, the hard mask material37is etched using the patterned resist film38as a mask, forming a hard mask. After that, the gate electrode material36and the gate insulation film material35are etched using the hard mask, forming the gate insulation films and the gate electrodes.

It should be noted that after forming the hard mask material37, an antireflective film may be formed thereon. When the resist film formed on the antireflective film is patterned, the antireflective film absorbs the exposure light which has passed through the resist film, functioning to eliminate the reflection of the exposure light at the interface between the resist film and the antireflective film. A film mainly made of an organic substance and formed by the spin coat method, etc. may be used as the antireflective film.

FIG. 21is a cross-sectional view of an alignment mark section in which the gate insulation film material35, the gate electrode material36, the hard mask material37, and the resist film38are laminated in that order after dry-etching the silicon substrate so as to form a flat bottom surface34as shown in FIG.19A. As shown inFIG. 21, the surface21aof the semiconductor substrate in the area sandwiched by the first and second grooves39and40is lower than the surface21bof the semiconductor substrate in other areas, forming a step t1having a predetermined depth in the alignment mark section.

According to the present embodiment, after forming the first rectangular pattern and the second rectangular pattern in the alignment mark section, ions are implanted in an implantation area and the alignment mark section. After that, the silicon oxide films in the implantation area and the alignment mark section are removed, exposing the semiconductor substrate therein. Then, when the next ion implantation is carried out, only the portion of the semiconductor substrate sandwiched by the above rectangular patterns is exposed. After the ion implantation, the exposed portion of the semiconductor substrate is etched, forming a concave portion having a predetermined depth in the alignment mark section. Therefore, it is possible to eliminate the photolithographic process for etching only the alignment mark section and thereby reduce the cost and the number of processes for manufacturing the semiconductor device. It should be noted that after forming the concave portion in the alignment mark section, ions can be implanted in other predetermined areas of the device formation section in the conventional manner. That is, each resist pattern used as a mask for implantation only need to have an opening over the target implantation area, and no opening is required over the alignment mark section.

Third Embodiment

The alignment mark section of a third embodiment of the present invention employs the same patterns as those shown inFIG. 2described in connection with the first embodiment.

Description will be made of a method for manufacturing a semiconductor device according to the present embodiment with reference toFIGS. 22to27. It should be noted that in these figures, like numerals will be used to denote like components.

First of all, a first insulation film and a hard mask are sequentially formed on a semiconductor substrate of a first conductive type. Then, the first insulation film and the semiconductor substrate are etched using the hard mask, forming grooves having a predetermined depth in the alignment mark section and the device formation section of the semiconductor substrate. After burying a second insulation film into the grooves, the hard mask is removed. For example, as shown inFIGS. 22Ato22C, active region patterns are formed on a semiconductor substrate41of a first conductive type according to the processes shown inFIGS. 1to6described with connection with the first embodiment. It should be noted thatFIGS. 22A,22B, and22C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. In these figures, reference numeral42denotes a silicon-oxide film used as a first insulation film, and44denotes another silicon oxide film used as a second insulation film. Further, reference numeral43denotes a silicon oxide film formed on the inside walls of the grooves in the alignment mark section and the device formation section. It should be noted that a silicon substrate may be used as the semiconductor substrate41.

Then, channel doping is applied to the semiconductor substrate41. Specifically, impurities of at least one of first and second conductive types are ion-implanted in desired areas using resist patterns formed by a photolithographic technique as masks. At that time, it is arranged that no resist pattern is formed also on the alignment mark section, as in the first embodiment.

For example, when ions are implanted in the NMOS region of the peripheral circuit section, a resist pattern45(a first resist pattern) is not formed on this region in order to implant ions in the region, as shown in FIG.23C. On the other hand, as shown inFIG. 23B, the resist pattern45is formed on the memory cell section since ions should not be implanted in this section. As for the alignment mark section, as shown inFIG. 23A, the present embodiment does not form the resist pattern45on it even though ions need not be implanted therein. Then, impurity ions are implanted in the NMOS region using the resist pattern45as a mask. At that time, the impurity ions are also implanted in the alignment mark section. However, no problem arises since they do not affect the transistor characteristics.

After completing the implantation of ions, the portions of silicon oxide films42,43, and44exposed at the resist pattern45are wet-etched. The wet-etching may be achieved by use of hydrofluoric acid, etc. After that, the resist pattern45is removed since it is no longer necessary, producing the structures shown inFIGS. 24Ato24C. It should be noted thatFIGS. 24A,24B, and24C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.

The above wet-etching is stopped when the exposed portion of the silicon oxide film42(formed on the semiconductor substrate41) has been removed, exposing the surfaces of the semiconductor substrate41in the alignment mark section and the NMOS region of the peripheral circuit section. At that time, the portions of the silicon oxide films43and44corresponding to the film thickness of the silicon oxide film42are also removed, along with the silicon oxide film42. In the above process, a step may be formed at the boundary between the surface of the silicon oxide film44and that of the silicon oxide film42beforehand. With this, even after the silicon oxide film42has been removed, the surface of the silicon oxide film44can be set higher than that of the semiconductor substrate41. When the silicon oxide film44is removed by etching in a postprocess, this arrangement prevents the grooves formed by removing the silicon oxide films from being processed such that they have an inverse tapered shape in cross-section, thereby preventing deterioration of the electrical characteristics of the transistors. It should be noted that the above step may be formed in the same manner as in the first embodiment. For example, after burying the silicon oxide film44into the grooves, the silicon oxide film44may be selectively etched until the height of its top surface from the bottom surface of the hard mask is reduced to a predetermined value (between 10 nm and 20 nm). After that, the hard mask may be removed since it is no longer necessary.

It should be noted that the height of the step provided at the boundary between the surfaces of the silicon oxide film44and the semiconductor substrate41need not necessarily be equal to that of the step at the boundary between the surfaces of the silicon oxide film44and the silicon oxide film42. That is, the same effect can be obtained if the surface of the silicon oxide film44has a height equal to or more than that of the surface of the semiconductor substrate41.

Then, as shown inFIGS. 25Ato25C, ions are implanted in the PMOS region of the peripheral circuit section using a resist pattern46as a second resist pattern. In this case, it is arranged that the resist pattern46is not formed on the alignment mark section, as well as on the target implantation area. It should be noted that the resist pattern46is formed on the NMOS region in which the semiconductor substrate41has been exposed. That is, the resist pattern46covers the NMOS region (in which the semiconductor substrate41has been exposed) and has openings over the PMOS region and the alignment mark section. For example, when a positive type resist is used, a mask is prepared which has a conventional mask pattern and furthermore an opening for letting light pass through to the alignment mark section. Then, the resist film is irradiated with light through the mask and developed, making it possible to form a resist pattern having openings over the target implantation area and the alignment mark section.

After implanting ions in the PMOS region using the resist pattern46as a mask, as shown inFIG. 25C, the portion of the semiconductor substrate41exposed in the alignment mark section (shown inFIG. 25A) is wet-etched before the resist pattern46is removed. It should be noted, that since the NMOS region is covered with the resist pattern46, the semiconductor substrate41in the NMOS region is not etched. The etching is achieved by use of a chemical solution capable of selectively etching the semiconductor substrate41. For example, if a silicon substrate is used as the semiconductor substrate41, aqueous ammonia may be used. By using such a solution, only the portion of the semiconductor substrate41exposed in the alignment mark section can be etched without etching the silicon oxide films42,43, and44exposed in the PMOS region. It should be noted that if a silicon substrate is used as the semiconductor substrate41, it may be dry-etched by use of a gas having a high selectivity ratio against the silicon oxide films.

Thus, the semiconductor substrate41can be etched to form a convex portion (a step) having a predetermined height in the alignment mark section, as shown in FIG.26. The height h4of the convex portion (the depth of the step) is preferably set to 50 nm or more, which is large enough to detect the alignment mark. It should be noted that inFIG. 26, the convex portion corresponds to the groove formed in the alignment mark section, and the surface of the semiconductor substrate41surrounding the convex portion is lower than that of the semiconductor substrate41in the device formation section (seeFIGS. 27Ato27C).

After completing etching of the semiconductor substrate41in the alignment mark-section, the resist pattern46is removed since it is no longer necessary. Then, a gate insulation film material47, a gate electrode material48, a hard mask material49, and a resist film50are laminated in that order, producing the structures shown inFIGS. 27Ato27C. It should be noted thatFIGS. 27A,27B, and27C show the alignment mark section, the memory cell section, and the peripheral circuit section, respectively. After patterning the resist film50by use of a photolithographic technique, the hard mask material49is etched using the patterned resist film50as a mask, forming a hard-mask. After that, the gate electrode material48and the gate insulation film material47are etched using the hard mask, forming the gate insulation films and the gate electrodes.

It should be noted that after forming the hard mask material49, an antireflective film may be formed thereon. When the resist film formed on the antireflective film is patterned, the antireflective film absorbs the exposure light which has passed through the resist film, functioning to eliminate the reflection of the exposure light at the interface between the resist film and the antireflective film. A film mainly made of an organic substance and formed by the spin coat method, etc. may be used as the antireflective film.

According to the present embodiment, after implanting ions in an implantation area and the alignment mark section, the silicon oxide films in the implantation area and the alignment mark section are removed, exposing the semiconductor substrate therein. Then, when the next ion implantation is carried out, only the portion of the semiconductor substrate in the alignment mark section is exposed. After the ion implantation, the exposed portion of the semiconductor substrate is etched, forming a convex portion having a predetermined height in the alignment mark section. Thus, it is possible to eliminate the need for the mask and photolithographic process for etching only the alignment mark section and thereby reduce the cost and the number of processes. It should be noted that after forming the convex portion in the alignment mark section, ions can be implanted in other predetermined areas of the device formation section in the conventional manner. That is, each resist pattern used as a mask for implantation only need to have an opening over the target implantation area, and no opening is required over the alignment mark section.

The features and advantages of the present invention may be summarized as follows.

According to one aspect of the present invention described above, each resist pattern used for ion implantation is provided with openings over the alignment mark section as well as a target implantation area. With this arrangement, after the implantation, the insulation films exposed at the openings of the resist pattern are removed before removing the resist pattern. This process is repeated, thereby gradually removing the (entire) insulation films in the alignment mark section. As a result, a step having a predetermined depth can be eventually formed. Thus, it is possible to eliminate the photolithographic process for etching only the alignment mark section and thereby reduce the cost and the number of processes.

According to another aspect of the present invention, after forming first and second grooves in the alignment mark section, ions are implanted in an ion implantation area and the alignment mark section. After that, the insulation films in the implantation area and the alignment mark section are removed, exposing the semiconductor substrate therein. Then, when the next ion implantation is carried out, only the portion of the semiconductor substrate sandwiched by the first and second grooves is exposed. After the ion implantation, the exposed portion of the semiconductor substrate is selectively etched, forming a step having a predetermined depth in the alignment mark section. Thus, it is possible to eliminate the photolithographic process for etching only the alignment mark section and thereby reduce the cost and the number of processes.

According to still another aspect of the present invention, after implanting ions in an implantation area and the alignment mark section, the insulation films in the implantation area and the alignment mark section are removed. Then, when the next ion implantation is carried out, only the portion of the semiconductor substrate in the alignment mark section is exposed. After the ion implantation, the exposed portion of the semiconductor substrate is etched, forming a step having a predetermined height in the alignment mark section. Thus, it is possible to eliminate the photolithographic process for etching only the alignment mark section and thereby reduce the cost and the number of processes.

The entire disclosure of a Japanese Patent Application No. 2003-382917, filed Nov. 12, 2003 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.