Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory

The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed on both sides of the first gate. The semiconductor layer is disposed on the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit. The second unit includes a second gate and a third and a fourth charge trapping layer respectively disposed on both sides of the second gate. The doped region is disposed at both sides of the semiconductor layer and serves as a common source/drain region of both the first and the second unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method and an operating method thereof. More particularly, the present invention relates to a non-volatile memory and a manufacturing method and an operating method thereof.

2. Description of Related Art

Data can be written into and read or erased from an electrically erasable programmable read-only memory (EEPROM) repeatedly and the data stored in the EEPROM won't be lost even after the power is cut off. Thus, EEPRM among non-volatile memories has been broadly applied to personal computers and electronic equipments.

Typically, the floating gate and control gate of an EEPROM are fabricated with doped polysilicon, and the insulation layers between gates and the substrate and between gate and gate are silicon oxide layers.

However, a plurality of polysilicon layers and a plurality of silicon oxide layers are to be formed in the foregoing EEPROM. Thus, a plurality of mask processes has to be performed during the fabricating process, which not only prolongs the fabricating process but also increases the fabricating cost. Moreover, a memory cell in the EEPROM can only store a 1-bit data and the double-gate design also takes a lot of space, which are very disadvantageous to device integration.

Memories with nitride charge trapping layers have been provided later on. According to the memory cell structure, charges are trapped in a silicon nitride dielectric layer for storing data. Even though the memory with nitride charge trapping layer can store 2-bit data in a single memory cell, the 2 data bits may affect each other and which reduces the reliability of the memory. Moreover, it cannot provide good charge endurance. Hence, a non-volatile memory having high integration and high reliability is required.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a non-volatile memory which allows multi-bit data to be stored in a single memory cell.

According to another aspect of the present invention, a manufacturing method of a non-volatile memory is provided, wherein the non-volatile memory which can store multi-bit data in a single memory cell is manufactured through several self alignments.

According to yet another aspect of the present invention, an operating method of a non-volatile memory is provided for operating multi-bits in a single memory cell.

The present invention provides a non-volatile memory which includes a memory cell disposed on a substrate. The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed at two sides of the first gate. The semiconductor layer is disposed on the substrate and covers the first unit, and the lateral dimension of the semiconductor layer is greater than the lateral dimension of the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit with the semiconductor layer as the symmetry axis. The second unit includes a second gate disposed on the semiconductor layer, a third charge trapping layer, and a fourth charge trapping layer, wherein the third and the fourth charge trapping layer are respectively disposed at two sides of the second gate. The doped region is disposed in both sides of the semiconductor layer and is used for a common source/drain region of both the first and the second unit.

According to the non-volatile memory in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer includes nanocrystal, tantalum oxide, strontium titanate, or hafnium oxide.

According to the non-volatile memory in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer includes silicon nitride.

According to the non-volatile memory in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer includes silicon oxide/silicon nitride/silicon oxide (ONO) composite material.

According to the non-volatile memory in an embodiment of the present invention, the first unit is disposed in the substrate, and a passivation layer is disposed between the first unit and the substrate.

According to the non-volatile memory in an embodiment of the present invention, a dielectric layer is disposed on the substrate, and the first unit is disposed in the dielectric layer.

According to an embodiment of the present invention, the non-volatile memory further includes a plurality of memory cells arranged as a column/row array on the substrate.

According to the non-volatile memory in an embodiment of the present invention, the memory cells in the same column are disposed adjacently in mirror symmetry.

According to the non-volatile memory in an embodiment of the present invention, any two adjacent memory cells disposed in mirror symmetry share a doped region.

According to an embodiment of the present invention, the non-volatile memory further includes a plurality of bottom word lines, a plurality of top word lines, and a plurality of bit lines. The bottom word lines are arranged in parallel in the direction of columns and connect the first gates of the memory cells in the same columns; the top word lines are arranged in parallel in the direction of columns and connect the second gates of the memory cells in the same columns; and the bit lines are arranged in parallel in the direction of rows and connect the doped regions of the memory cells in the same rows.

According to an embodiment of the present invention, the non-volatile memory further includes a tunneling dielectric layer respectively disposed between the first unit and the semiconductor layer, and between the second unit and the semiconductor layer.

According to an embodiment of the present invention, the tunneling dielectric layer includes a multi-layer structure.

According to an embodiment of the present invention, the multi-layer structure is a composite material of a bottom layer of silicon oxide/a middle layer of silicon nitride/a top layer of silicon oxide (ONO).

According to an embodiment of the present invention, the thickness of the bottom layer of silicon oxide in the composite material is less than 2 nm, such as between about 0.5˜2 nm, or less than 1.5 nm.

According to an embodiment of the present invention, the thickness of the middle layer of silicon nitride in the composite material is less than 2 nm, such as between about 1˜2 nm.

According to an embodiment of the present invention, the thickness of the top layer of silicon oxide in the composite material is less than 2 nm, such as between about 1.5˜2 nm.

The present invention provides a manufacturing method of a non-volatile memory. According to the method, a substrate is provided first. An insulation layer and a bottom conductive layer are sequentially formed on the substrate. A first dielectric layer having a first opening for exposing the bottom conductive layer is then formed on the substrate. Next, a first unit is formed in the first opening. The first unit includes a first and a second charge trapping layer respectively formed on two sidewalls of the first opening, and a first gate filled in the first opening and electrically connected to the bottom conductive layer. After that, a second dielectric layer having a second opening for exposing the first unit is formed on the substrate. Thereafter, a third dielectric layer is formed in the second opening to cover the first unit. A semiconductor layer is further formed in the second opening to cover the first unit, and the lateral dimension of the semiconductor layer is greater than that of the first unit. Next, a second unit is formed on the semiconductor layer. The second unit includes a second gate formed on the semiconductor layer, and a third and a fourth charge trapping layer respectively formed at both sides of the second gates. A doped region is then formed in both sides of the semiconductor layer.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the substrate has a recess, and the insulation layer and the bottom conductive layer are sequentially formed in the recess to fill up the recess.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the method for forming the first unit may include following steps. First, a charge trapping material layer is formed in the opening. Portion of the charge trapping material layer is then removed to form the first and the second charge trapping layer on two sidewalls of the opening and to expose portion of the bottom conductive layer. Next, the first gate is filled in the opening and is connected to the bottom conductive layer.

According to an embodiment of the present invention, the manufacturing method of a non-volatile memory further includes a step of forming a dielectric layer on the inner walls of the first and the second charge trapping layer before the step of forming the first gate.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the method for forming the second unit may include following steps. First, the second gate is formed on the substrate. A charge trapping material layer is then formed on the substrate. Next, portion of the charge trapping material layer is removed to respectively form the third and the fourth charge trapping layer at both sides of the second gate.

According to an embodiment of the present invention, the manufacturing method of a non-volatile memory further includes a step of forming a tunneling dielectric layer on the semiconductor layer before the step of forming the second gate.

According to an embodiment of the present invention, the manufacturing method of a non-volatile memory further includes a step of forming a dielectric layer at both sides of the second gate before the step of forming the third and the fourth charge trapping layer.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the formation method of the semiconductor layer includes epitaxial lateral overgrowth.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the method for sequentially forming the insulation layer and the bottom conductive layer in the recess to fill up the recess may include following steps. First, an insulation material layer and a conductor material layer are formed in sequence on the substrate. Next, portion of the insulation material layer and portion of the conductor material layer are removed through chemical mechanical polishing with the substrate as the stop layer.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer includes nanocrystal, tantalum oxide, strontium titanate, or hafnium oxide.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer includes silicon nitride.

According to the manufacturing method of a non-volatile memory in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer includes silicon oxide/silicon nitride/silicon oxide (ONO) composite material.

According to an embodiment of the present invention, the manufacturing method of a non-volatile memory further includes a step of forming a top conductive layer on the second unit, wherein the top conductive layer is electrically connected to the second gate.

The present invention further provides an operating method of a non-volatile memory which is suitable for a memory cell disposed on a substrate. The memory cell includes: a first unit having a first gate, a first charge trapping layer, and a second charge trapping layer, wherein the first and the second charge trapping layer are disposed at both sides of the first gate; a semiconductor layer covering the first unit; a second unit disposed on the semiconductor layer and being in mirror symmetry to the first unit with the semiconductor layer as the symmetry axis, wherein the second unit includes a second gate disposed on the semiconductor layer and a third and a fourth charge trapping layer disposed at both sides of the second gate; and a source region and a drain region respectively disposed in the semiconductor layer at both sides of the second unit and used as the common source region and common drain region of the first and the second unit. According to the operating method, while performing a program operation to the non-volatile memory, a first voltage is supplied to the first gate, a second voltage is supplied to the source region, a third voltage is supplied to the drain region, a fourth voltage is supplied to the second gate, and charges are injected into the first charge trapping layer, wherein the first voltage is higher than the second voltage, and the second voltage is higher than the third and the fourth voltage.

According to the operating method of a non-volatile memory in an embodiment of the present invention, the mechanism of performing the program operation includes channel hot electron injection.

According to the operating method of a non-volatile memory in an embodiment of the present invention, the first voltage is between 5V and 10V, the second voltage is between 3V and 6V, and the third and the fourth voltage are both 0V.

According to an embodiment of the present invention, the operating method of a non-volatile memory further includes while performing an erase operation to the non-volatile memory, supplying a fifth voltage to the first gate, supplying a sixth voltage to the source region, supplying a seventh voltage to the drain region, supplying an eighth voltage to the second gate, and erasing the charges in the first charge trapping layer, wherein the fifth voltage is lower than the sixth, the seventh and the eighth voltages, and the sixth voltage is higher than the seventh and the eighth voltages.

According to the operating method of a non-volatile memory in an embodiment of the present invention, the mechanism of performing the erase operation includes band-to-band hot hole (BTBHH) injection.

According to the operating method of a non-volatile memory in an embodiment of the present invention, the fifth is negative voltage and the sixth voltage is positive voltage. According to the operating method of a non-volatile memory in an embodiment of the present invention, the fifth voltage is between −5V and −10V, the sixth voltage is between +3V and +6V, and the seventh and the eighth voltage are both 0V.

According to an embodiment of the present invention, the operating method of a non-volatile memory further includes while performing a read operation to the non-volatile memory, supplying a ninth voltage to the first gate, supplying a tenth voltage to the source region, supplying an eleventh voltage to the drain region, supplying a twelfth voltage to the second gate, and reading the storage state of the first charge trapping layer, wherein the ninth voltage is higher than the eleventh voltage, and the eleventh voltage is higher than the tenth and the twelfth voltage.

According to the operating method of a non-volatile memory in an embodiment of the present invention, the mechanism of performing the read operation includes reverse reading.

According to the operating method of a non-volatile memory in an embodiment of the present invention, the ninth voltage is between 3V and 5V, the eleventh voltage is between 1V and 2V, and the tenth and twelfth voltage are both 0V.

According to an embodiment of the present invention, the operating method of a non-volatile memory further includes: while performing a program operation to the non-volatile memory, supplying the first voltage to the first gate structure, supplying the third voltage to the source region, supplying the second voltage to the drain region, supplying the fourth voltage to the second gate, and injecting charges into the second charge trapping layer through channel hot electron injection; while performing an erase operation to the non-volatile memory, supplying a fifth voltage to the first gate, supplying a seventh voltage to the source region, supplying a sixth voltage to the drain region, supplying an eighth voltage to the second gate, and erasing the charges in the second charge trapping layer through BTBHH injection; and while performing a read operation to the non-volatile memory, supplying a ninth voltage to the first gate, supplying an eleventh voltage to the source region, supplying a tenth voltage to the drain region, supplying a twelfth voltage to the second gate, and reading the storage state of the second charge trapping layer through reverse reading.

According to an embodiment of the present invention, the operating method of a non-volatile memory further includes: while performing a program operation to the non-volatile memory, supplying the fourth voltage to the first gate, supplying the second voltage to the source region, supplying the third voltage to the drain region, supplying the first voltage to the second gate, and injecting charges into the third charge trapping layer through channel hot electron injection; while performing an erase operation to the non-volatile memory, supplying an eighth voltage to the first gate, a sixth voltage to the source region, a seventh voltage to the drain, a fifth voltage to the second gate, and erasing the charges in the third charge trapping layer through BTBHH injection; and while performing a read operation to the non-volatile memory, supplying a twelfth voltage to the first gate, supplying a tenth voltage to the source region, supplying an eleventh voltage to the drain region, supplying a ninth voltage to the second gate, and reading the storage state of the third charge trapping layer through reverse reading.

According to an embodiment of the present invention, the operating method of a non-volatile memory further includes: while performing a program operation to the non-volatile memory, supplying the fourth voltage to the first gate, supplying the third voltage to the source region, supplying the second voltage to the drain region, supplying the first voltage to the second gate, and injecting electrons into the fourth charge trapping layer through channel hot electron injection, so as to store a fourth bit into the memory cell; while performing an erase operation to the non-volatile memory, supplying an eighth voltage to the first gate, supplying a seventh voltage to the source region, supplying a sixth voltage to the drain region, supplying a fifth voltage to the second gate, and erasing the electrons in the fourth charge trapping layer through BTBHH injection; and while performing a read operation to the non-volatile memory, supplying a twelfth voltage to the first gate, supplying an eleventh voltage to the source region, supplying a tenth voltage to the drain region, supplying a ninth voltage to the second gate, and reading the storage state of the fourth charge trapping layer through reverse reading.

The present invention further provides a circuit system, comprising a non-volatile memory and a circuit. The non-volatile memory comprises a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The memory cells are arranged as a column/row array, each memory cell comprises a first unit, a semiconductor layer, a second unit, and a doped region. The first unit comprises a first gate, and a first charge trapping layer and a second charge trapping layer respectively disposed at both sides of the first gate. The semiconductor layer is disposed on the substrate and covering the first unit, and the lateral dimension of the semiconductor layer is greater than the lateral dimension of the first unit. The second unit is disposed on the semiconductor layer, the second unit being in mirror symmetry to the first unit with the semiconductor layer as a symmetry axis, and the second unit comprises a second gate disposed on the semiconductor layer; and a third charge trapping layer and a fourth charge trapping layer, respectively disposed at both sides of the second gate. The doped region is disposed in both sides of the semiconductor layer and serving as a common source/drain region of both the first unit and the second unit. The plurality of words comprises a plurality of bottom word lines, arranged in parallel in a direction of the columns, for connecting the first gates of the memory cells in the same columns, and a plurality of top word lines, arranged in parallel in the direction of the columns, for connecting the second gates of the memory cells in the same columns. The plurality of bit lines are arranged in parallel in a direction of the columns, for connecting the doped regions of the memory cells in the same columns. The circuit is coupled to the non-volatile memory, comprising a column decoder coupled to the bit lines, a row decoder coupled to the word lines, and a data-in structure coupled to the column decoder, wherein a datum is stored in the non-volatile memory through the data-in structure.

According to the circuit system in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer comprises nanocrystal, tantalum oxide, strontium titanate, or hafnium oxide.

According to the circuit system in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer comprises silicon nitride.

According to the circuit system in an embodiment of the present invention, the material of the first, the second, the third, and the fourth charge trapping layer comprises silicon oxide/silicon nitride/silicon oxide (ONO) composite material.

According to the circuit system in an embodiment of the present invention, the semiconductor layer is formed through epitaxial lateral overgrowth.

According to the circuit system in an embodiment of the present invention, the memory cells in the same column are disposed adjacently in mirror symmetry.

According to the circuit system in an embodiment of the present invention, two adjacent memory cells disposed in mirror symmetry share the doped region.

According to the present invention, charge trapping layers are formed at both sides of gates through self-alignment, and a doped region in the semiconductor layer is used as a common source/drain region of two units, thus, a highly integrated memory cell is manufactured and multi-bit data can be stored in a single memory cell.

Moreover, since the charge trapping layers in such a memory cell are respectively disposed at two sides of the gates, the various bits can be easily programmed, erased, and read by supplying appropriate voltages to the source region, drain region, first gate, and second gate, and there won't be interference between the various bits, accordingly, the reliability of the memory cell and the electrical performance of a memory are both improved.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

FIG. 1Ais a cross-sectional view of a non-volatile memory according to an embodiment of the present invention.FIG. 1Bis a cross-sectional view of a non-volatile memory according to another embodiment of the present invention.FIG. 2is a top view of a non-volatile memory according to an embodiment of the present invention.

Referring toFIG. 1AandFIG. 1B, a single memory cell MC is used for describing the non-volatile memory in the present invention. The memory cell MC is disposed on a substrate100and is composed of a semiconductor layer140, a first unit120, a second unit160, and a doped region165.

Referring toFIG. 1A, the substrate100may be a silicon substrate. The first unit120includes a first gate130, and a first charge trapping layer122aand a second charge trapping layer122bdisposed at both sides of the first gate130. The material of the first gate130may be doped polysilicon, and the material of the first charge trapping layer122aand the second charge trapping layer122bmay be silicon nitride or composite material such as silicon oxide/silicon nitride, or silicon oxide/silicon nitride, silicon oxide/silicon nitride, silicon oxide (ONO, OSO). Certainly, the material of the first charge trapping layer122aand the second charge trapping layer122bis not limited to silicon nitride, which may also be any other material which can trap charges, such as nanocrystal, tantalum oxide, strontium titanate, or hafnium oxide.

A dielectric layer125is further disposed between the first gate130and the first charge trapping layer122a, the second charge trapping layer122b. The material of the dielectric layer125may be silicon oxide.

The first unit120may be disposed in the substrate100, and a passivation layer117may be disposed between the first gate130of the first unit120and the substrate100to separate the first gate130and the substrate100. In an embodiment of the present invention, a passivation layer119may also be disposed between the first charge trapping layer122a, the second charge trapping layer122band the substrate100for preventing charges captured in the charge trapping layers from entering the substrate100. The material of the passivation layer117and the passivation layer119may be silicon oxide.

Referring toFIG. 1B, in another embodiment of the present invention, the first unit120may also be disposed in the dielectric layer115on the substrate100. The material of the dielectric layer115may be silicon oxide.

Referring toFIG. 1AandFIG. 1Bthe semiconductor layer140covering the first unit120is disposed on the substrate100, and the lateral dimension thereof is greater than that of the first unit120. The semiconductor layer140may be formed through epitaxial lateral overgrowth. A tunneling dielectric layer135is further disposed between the first unit120and the semiconductor layer140, i.e. disposed between the semiconductor layer140and the first gate130. The tunneling dielectric layer135may be a single layer or a multi-layer structure, such as silicon oxide or composite material like silicon oxide/silicon nitride, silicon oxide/silicon nitride, silicon oxide (ONO, OSO). The thickness of the bottom layer of silicon oxide in the composite material is less than 2 nm. In one embodiment, it may be between about 0.5˜2 nm, and in another embodiment, it may be less then 1.5 nm. The thickness of the middle layer of silicon nitride, silicon oxide in the composite material is less than 2 nm, and in one embodiment, it may be about 1˜2 nm. The thickness of the top layer of silicon oxide in the composite material is less than 2 nm, and, in one embodiment, it may be about 1.5˜2 nm.

The second unit160is disposed on the semiconductor layer140and is in mirror symmetry to the first unit120with the semiconductor layer140as a symmetry axis. The second unit160includes a second gate145disposed on the semiconductor layer140, and a third charge trapping layer155aand a fourth charge trapping layer155bdisposed at both sides of the second gate145.

The material of the second gate145may be a conductive material such as doped polysilicon or metal silicide. The material of the third charge trapping layer155aand the fourth charge trapping layer155bmay be silicon nitride, composite material such as silicon oxide/silicon nitride, silicon oxide/silicon nitride/silicon oxide (ONO), or any other material which can trap charges, such as nanocrystal, SiON, tantalum oxide, strontium titanate, or hafnium oxide.

Referring toFIG. 1B, in another embodiment of the present invention, the semiconductor layer140may be disposed in the dielectric layer132for separating the semiconductor layer140of adjacent memory cell MC. A dielectric layer163may be disposed at both sides of the second units160to facilitate the formation of the word lines later. The material of the dielectric layer132and the dielectric layer163may be silicon oxide or similar dielectric material.

Referring toFIG. 1A, a tunneling dielectric layer143is disposed between the bottom of the third charge trapping layer155a, the second gate145, and the fourth charge trapping layer155bof the second unit160and the semiconductor layer140. The tunneling dielectric layer143may be a single layer or a multi-layer structure, such as silicon oxide or composite material like silicon oxide/silicon nitride, silicon oxide/silicon nitride, silicon oxide (ONO, OSO). The thickness of the bottom layer of silicon oxide in the composite material is less than 2 nm. In one embodiment, it may be between about 0.5˜2 nm, and in another embodiment, it may be less then 1.5 nm. The thickness of the middle layer of silicon nitride, silicon oxide in the composite material is less than 2 nm, and in one embodiment, it may be about 1˜2 nm. The thickness of the top layer of silicon oxide in the composite material is less than 2 nm, and in one embodiment, it may be about 1.5˜2 nm. A dielectric layer153may be disposed between two sidewalls of the second gate145and the third charge trapping layer155aand fourth charge trapping layer155b, and the material of the dielectric layer153may be silicon oxide.

Referring toFIG. 1B, in another embodiment, the tunneling dielectric layer143may be disposed between the second gate145and the semiconductor layer140. The dielectric layer153may be disposed between the sidewalls and the bottoms of the third charge trapping layer155aand the forth charge trapping layer155band the second gate145, the semiconductor layer140. During the operation process of the memory, the charges can tunnel through the dielectric layer153(particularly the bottom parts of the charge trapping layers155aand155b) and the tunneling dielectric layer143.

The doped region165is disposed in both sides of the semiconductor layer140, that is, in the semiconductor layer140at both sides of the second unit160and the first unit120as a common source/drain region of the first unit120and the second unit160. In an embodiment of the present invention, the substrate100may be a P-type substrate, and the doped region165may be an N-type doped region which is heavily doped with phosphor or arsenic.

The first charge trapping layer122a, second charge trapping layer122b, third charge trapping layer155a, and fourth charge trapping layer155bcan respectively store data. In other words, multi-bit data can be stored in a single memory cell MC.

Referring toFIG. 2, a plurality of memory cells MC may be arranged as a column/row array on the substrate100. Those memory cells MC in the same column (in direction X) are disposed adjacently in mirror symmetry. Any adjacent two memory cells MC may share the same doped region165.

The memory cell array further includes bottom word lines BWL1, BWL2, BWL3, top word lines, TWL1, TWL2, TWL3, and bit lines BL1, BL2, BL3.

The bottom word lines BWL1, BWL2, and BWL3connect the first gates130of the memory cells MC in the same column (in direction X); the top word lines TWL1, TWL2, and TWL3connect the second gates145of the memory cells MC in the same column (in direction X); and the bit lines BL1, BL2, and BL3may be connect the doped regions165of the memory cells MC in the same row (in direction Y) through a plug175.

Referring toFIG. 1B, in an embodiment of the present invention, the bottom word lines110may be disposed between the substrate100and the first unit120and are electrically connected to the first gates130. An insulation layer is further disposed between the bottom word lines110and the substrate100to separate the bottom word lines110and the substrate100. The top word lines170are disposed on the second unit160and are electrically connected to the second gates145. The material of the bottom word line110and the top word line170may be a conductive material such as doped polysilicon, aluminum, aluminum alloy, or metal silicide.

In a non-volatile memory in the present embodiment, a single memory cell has plural charge trapping layers, so that the memory cell can store multi-bit data. In other words, the memory cell in the present invention can store more data in per unit area and which is very advantageous in device integration.

In addition, the charge trapping layers are disposed at both sides of the gates, thus, charges in the charge trapping layers will not interfere with each other, accordingly, both the reliability and electrical performance of the memory are improved.

The present invention further provides a manufacturing method of a non-volatile memory.FIG. 3A-1andFIGS. 3B˜3Gare cross-sectional views illustrating a manufacturing flow of the non-volatile memory inFIG. 2cut along line I-I′.FIG. 3A-2is a cross-sectional view illustrating a manufacturing flow of the non-volatile memory inFIG. 2cut along line II-II′.

Referring toFIG. 3A-1andFIG. 3A-2, according to the manufacturing method in the present embodiment, a substrate200is first provided, wherein the substrate200may be a silicon substrate and a recess203has been formed in the substrate200. The formation method of the recess203may be as following: first, forming a patterned photoresist layer (not shown) on the substrate200; removing portion of the substrate200; and then removing the patterned photoresist layer.

Next, an insulation layer205and a bottom conductive layer210are formed sequentially to cover the substrate200and fill up the recess203. After that, a planarization process is performed through chemical mechanical polishing to remove the bottom conductive layer210and the insulation layer205on the substrate200.

Next, referring toFIG. 3B, a dielectric layer215is formed on the bottom conductive layer210. The material of the dielectric layer215may be silicon oxide, and the formation method thereof may be chemical vapor deposition (CVD). After that, an opening217is formed in the dielectric layer215to expose the bottom conductive layer210. The opening217may be formed through photolithography and etching processes.

Thereafter, a charge trapping material layer221and a dielectric material layer223are sequentially formed on the substrate200. The material of the charge trapping material layer221may be any material which can trap charges, such as silicon nitride, nanocrystal, SiON, composite material such as silicon oxide/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO), tantalum oxide, strontium titanate, or hafnium oxide, and the formation method of the charge trapping material layer221may be CVD. The material of the dielectric material layer223may be silicon oxide, and the formation method thereof may be CVD.

Next, referring toFIG. 3C, portion of the dielectric material layer223and portion of the charge trapping material layer221are removed, so as to form the charge trapping layers222a,222b, and the dielectric layer225on two sidewalls of the opening217and expose the bottom conductive layer210. The method for removing portion of the dielectric material layer223and portion of the charge trapping material layer221may be dry etching or wet etching. After that, the gate230connected to the bottom conductive layer210is filled into the opening217. The method for forming the gate230may be forming an integral conductive layer (not shown) on the substrate200, and the material of the conductive layer may be doped polysilicon. The conductive layer on the dielectric layer215is then removed through a planarization process such as chemical mechanical polishing. The gate230and the charge trapping layers222a,222bform the first unit220of the memory cell.

Thereafter, referring toFIG. 3D, another dielectric layer232is formed on the substrate200. The material of the dielectric layer232may be silicon oxide, and the formation method thereof may be CVD. After that, another opening234is formed in the dielectric layer232to expose the first unit220. The formation method of the opening234may be a photolithography etching process. The lateral dimension of the opening234may be greater than that of the first unit220to expose the dielectric layer215.

Thereafter, a tunneling dielectric layer235is formed in the opening234. The tunneling dielectric layer235may be a single layer or a multi-layer structure, such as silicon oxide, or composite material like silicon oxide/silicon nitride, silicon oxide/silicon nitride, silicon oxide (ONO, OSO), and the formation method thereof may be CVD. The tunneling dielectric layer235formed through CVD has excellent film quality. However, the tunneling dielectric layer235may also be formed by leaving portion of the dielectric layer232while forming the opening234.

Next, the semiconductor layer240is filled in the opening234. The material of the semiconductor layer240may be silicon, and the formation method thereof may be epitaxial lateral overgrowth.

Next, referring toFIG. 3E, a dielectric layer243and a gate245are formed on the substrate200. The formation method of the dielectric layer243and the gate245may be sequentially forming a dielectric material layer (not shown) and a gate material layer (not shown) on the substrate200and then patterning the foregoing material layers through a photolithography etching process. The dielectric material layer may be a single layer or a multi-layer structure, such as silicon oxide, or composite material like silicon oxide/silicon nitride, silicon oxide/silicon nitride, silicon oxide (ONO, OSO), and the formation method thereof may be CVD. The material of the gate material layer may be doped polysilicon, and the formation method thereof may be performing an ion implantation process to an undoped polysilicon layer formed through CVD, or may also be CVD through in-situ dopant implantation.

After that, referring toFIG. 3F, an integral dielectric material layer247and an integral charge trapping material layer249are sequentially formed on the substrate200. The dielectric material layer247may be a single layer or a multi-layer structure, such as silicon oxide, or composite material like silicon oxide/silicon nitride, silicon oxide/silicon nitride, silicon oxide (ONO, OSO), and the formation method thereof may be CVD. The material of the charge trapping material layer249may be nanocrystal, silicon nitride, SiON, tantalum oxide, SrTiO3, or HfO2, and the formation method thereof may be CVD.

Thereafter, referring toFIG. 3G, portion of the charge trapping material layer249and portion of the dielectric material layer247are removed and only the portions on the sidewalls of the gate245are remained, so as to form the charge trapping layers255a,255band the dielectric layer253. The gate245and the charge trapping layers255a,255bform the second unit260of the memory cell. The dielectric layer253(particularly the bottom parts of the charge trapping layers255aand255b) and the dielectric layer243may be used as the tunneling dielectric layers of the second unit260, and during operation of memory cell, charges tunnel into and out of the charge trapping layers255aand255bthrough these dielectric layers.

Next, a doped region265is formed in both sides of the semiconductor layer240. The doped region265may be formed by performing a dopant implantation process with N-type dopant such as phosphor ion or arsenic ion. The doped region265is disposed in the semiconductor layer at both sides of the second unit260and the first units220and can be used as the common source/drain region of the second unit260and the first unit220.

A dielectric layer263and a top conductive layer270are then formed on the substrate200. The top conductive layer270is connected to the gate245and used as a top word line of the memory. The bottom conductive layer210at the bottom of the memory connected to the gate230is used as a bottom word line of the memory. The subsequent processes for forming the plug, the bit lines, and for completing the memory are familiar to those skilled in the art, therefore which will not be described herein.

According to the manufacturing method of a non-volatile memory in the present embodiment, through self-alignment and disposition of spacers, the charge trapping layers222aand222bare formed at both sides of the gate230, and the charge trapping layers255aand255bare formed at both sides of the gate230. The multi-bit structure of a single memory cell reduces the space taken by a memory in the layout of a chip; accordingly, device integration is greatly improved.

An operating method of a non-volatile memory in the present invention will be described below.FIGS. 4A˜4Cillustrate the operation of a first bit in a single memory cell of a non-volatile memory according to an embodiment of the present invention.FIGS. 5A˜5Cillustrate the operation of a second bit in a single memory cell of a non-volatile memory according to an embodiment of the present invention.FIGS. 6A˜6Cillustrate the operation of a third bit in a single memory cell of a non-volatile memory according to an embodiment of the present invention.FIGS. 7A˜7Cillustrate the operation of a fourth bit in a single memory cell of a non-volatile memory according to an embodiment of the present invention.FIG. 8is a simplified circuit diagram of a non-volatile memory according to an embodiment of the present invention.

In the present embodiment, the structure of the memory cell is the same as that inFIG. 2, and to describe the operating method of the memory cell in the present embodiment more clearly, the memory cells illustrated inFIGS. 4A˜4C,FIGS. 5A˜5C,FIGS. 6A˜6C, andFIGS. 7A˜7Care composed of the first unit, second unit, semiconductor layer, and doped region inFIG. 2. The reference numerals used here are the same as those used inFIG. 2, and the structure of the memory cell will not be described herein. It should be noted that the doped region165inFIG. 2is denoted respectively as a source region165aand a drain region165bin the present embodiment.

Referring toFIG. 4A, while performing a program operation to the memory cell, a voltage Vcg1is supplied to the gate130, a voltage Vs is supplied to the source region165a, a voltage Vd is supplied to the drain region165b, and a voltage Vcg2is supplied to the gate145, wherein the voltage Vcg1is higher than the voltage Vs, and the voltage Vs is higher than the voltage Vd and voltage Vcg2. Electrons are injected into the charge trapping layer122athrough channel hot electron injection, so as to store a first bit B1into the memory cell. In an embodiment of the present invention, the voltage Vcg1may be between 5V and 10V, preferably 8V; the voltage Vs may be between 3V and 6V, preferably 4V; and the voltage Vd and the voltage Vcg2may be both 0V.

Referring toFIG. 4B, while performing an erase operation to the memory cell, the voltage Vcg1is supplied to the gate130, the voltage Vs is supplied to the source region165a, the voltage Vd is supplied to the drain region165b, and the voltage Vcg2is supplied to the gate145, wherein the voltage Vcg1is lower than the voltage Vs, Vd and Vcg2, and the voltage Vs is higher than the voltage Vd and voltage Vcg2. Holes are injected into the charge trapping layer122athrough band-to-band hot hole (BTBHH) injection, so as to erase the first bit B1previously stored in the memory cell. In an embodiment of the present invention, the voltage Vcg1may be between −5V and −10V, preferably −8V; the voltage Vs may be between +3V and +6V, preferably +4V; and the voltage Vd and the voltage Vcg2may be both 0V.

Referring toFIG. 4C, while performing a read operation to the memory cell, the voltage Vcg1is supplied to the gate130, a voltage Vs is supplied to the source region165a, the voltage Vd is supplied to the drain region165b, and the voltage Vcg2is supplied to the gate145, wherein the voltage Vcg1is higher than the voltage Vd, and the voltage Vd is higher than the voltage Vs and voltage Vcg2. The storage state of the first bit B1in the charge trapping layer122ais read through reverse reading. In an embodiment of the present invention, the voltage Vcg1may be between 3V and 5V, preferably 3V; the voltage Vd may be between 1V and 2V, preferably 1.6V; and the voltage Vs and the voltage Vcg2may be both 0V.

According to the non-volatile memory in the present invention, a single memory cell has four charge trapping layers for respectively storing data, andFIGS. 4A˜4Crespectively illustrate the methods of program, erase, and read to the first bit B1in the charge trapping layer122a. The second bit B2in the charge trapping layer122b, the third bit B3in the charge trapping layer155a, and the fourth bit B4in the charge trapping layer155bhave similar operation mechanisms at those of the first bit B1and which will be further described below.

Referring toFIGS. 5A˜5C, the only difference of the methods for programming, erasing, and reading the second bit B2in the charge trapping layer122bfrom the methods for programming, erasing, and reading the first bit B1in the charge trapping layer122ais that the voltages supplied to the source region165aand the drain region165bare exchanged so that electrons or holes are injected into the charge trapping layer122binstead to program, erase, and read the second bit B2.

Referring toFIGS. 6A˜6C, the difference between the operating methods of the third bit B3in the charge trapping layer155aand the operating methods of the first bit B1is that the voltages supplied to the gate145and the gate130are exchanged so that electrons or holes are injected into the charge trapping layer115ato program, erase, and read the third bit B3.

Referring toFIGS. 7A˜7C, the difference between the operating methods of the fourth bit B4in the charge trapping layer155band the operating methods of the first bit B1is that the voltages supplied to the gate145and the gate130are exchanged, and the voltage Vs supplied to the source region165aand the voltage Vd supplied to the drain region165bare exchanged, so that electrons or holes are injected into the charge trapping layer115ato program, erase, and read the fourth bit B4.

In foregoing embodiments, the operating methods of a single memory cell are described; however, such memory cells may also be arranged as a column/row array to form a memory.FIG. 1is a top view of such a memory, andFIG. 8is a simplified circuit diagram of this memory.

Referring toFIG. 8, taking the first bit B1of the memory cell MC as an example, while performing a program operation, the voltage Vcg1is supplied to the bottom word line BWL1, the voltage Vs is supplied to the bit line BL1, the voltage Vd is supplied to the bit line BL2, and the voltage Vcg2is supplied to the top word line TWL1, wherein the voltage Vcg1is higher than the voltage Vs, and the voltage Vs is higher than the voltage Vd and the voltage Vcg2, and a first bit B1is stored into the memory cell MC through channel hot electron injection. In an embodiment of the present invention, the voltage Vcg1may be between 5V and 10V, preferably 8V; the voltage Vs may be between 3V and 6V, preferably 4V; and the voltage Vd and the voltage Vcg2may be both 0V.

While performing an erase operation, the voltage Vcg1is supplied to the bottom word line BWL1, the voltage Vs is supplied to the bit line BL1, the voltage Vd is supplied to the bit line BL2, and the voltage Vcg2is supplied to the top word line TWL1, wherein the voltage Vcg1is lower than the voltage Vs, Vd, and Vcg2, and the voltage Vs is higher than the voltage Vd and the voltage Vcg2. The first bit B1previously stored in the memory cell MC is erased through BTBHH. In an embodiment of the present invention, the voltage Vcg1may be between −5V and −10V, preferably −8V; the voltage Vs may be between +3V and +6V, preferably +4V; and the voltage Vd and the voltage Vcg2may be both 0V.

While performing a read operation, the voltage Vcg1is supplied to the bottom word line BWL1, the voltage Vs is supplied to the bit line BL1, the voltage Vd is supplied to the bit line BL2, and the voltage Vcg2is supplied to the top word line TWL1, wherein the voltage Vcg1is higher than the voltage Vd, and the voltage Vd is higher than the voltage Vs and the voltage Vcg2. The storage state of the first bit B1of the memory cell MC is read through reverse reading. In an embodiment of the present invention, the voltage Vcg1may be between 3V and 5V, preferably 3V; the voltage Vd may be between 1V and 2V, preferably 1.6V; and the voltage Vs and the voltage Vcg2may be both 0V.

The operating methods to the second, third, and fourth bits of the memory cell MC can be derived from foregoing description of the operating methods to the second, third, and fourth bits of a single memory cell by those skilled in the art, therefore which will not be described herein.

According to the operating method of a non-volatile memory in the present invention, appropriate biases are respectively supplied to the gate130, the gate145, the source region165a, and the drain region165b, so that the memory can be operated by simply controlling the actions of charges. Moreover, since charge trapping layers are disposed at both sides of the gates, the operations to various bits will not interfere with each other, accordingly, the reliability and electrical performance of the memory can be both improved.

FIG. 9is a simplified circuit block diagram of an integrated circuit applying an embodiment of the present invention. The circuit990includes a nonvolatile memory (memory cell array)900implemented using memory cells which have multi-bits per cell, on a semiconductor substrate. A row decoder910is coupled to a plurality of word lines905, and arranged along rows in the memory cell array900. A column decoder920is coupled to a plurality of bit lines915arranged along columns in the memory cell array900for reading and programming data from the multi-bit memory cells in the array900. Addresses are supplied on bus960to column decoder920and row decoder910. Sense amplifiers and data-in structures in block930are coupled to the column decoder920via data bus925. Data is supplied via the data-in line933from input/output ports on the circuit990or from other data sources internal or external to the circuit990, to the data-in structures in block930. In the illustrated embodiment, other circuitry is included in the circuit990, such as a general purpose processor or special purpose application circuitry, or a combination of modules supported by the multi-bit memory cell array. Data is supplied via the data-out line935from the sense amplifiers in block930to input/output ports on the circuit990, or to other data destinations internal or external to the circuit990.

A controller implemented in this example using programming, erasing & reading bias arrangement state machine950controls the application of bias arrangement supply voltages940, such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.