Low power non-volatile SRAM memory systems

Memory structures are provided, where a fast SRAM in an mNVSRAM block may serve as the buffer for a large block NVM memory to increase the data exchange rate between computing units or processor cores and the large NVM memory. The mNVSRAM blocks may also provide a fast boot function, where a boot code may be stored in the NVM parts of the mNVSRAM block, and due to the high bandwidth communication between fast SRAM part and the associated NVM memories, the boot code may be transferred into the fast SRAM in one or a few clock cycles enabling fast boot up function. Similarly, code stored in the NVM parts of an mNVSRAM block may be transferred into fast SRAM rapidly at wake-up time enabling fast wake up and voiding a need to wake up any other memory part, which may also result in energy savings for the computing system.

BACKGROUND

Despite developments in integrated circuitry and processing technologies, computers are still considered slow at boot-up or wake-up times. At bot-up or wake-up time, a computer needs to retrieve data from memory and execute essential programs. However, non-volatile memory (NVM) systems may be slow to write or read data. Thus, a computer's power-up or wake-up speed depends on its data retrieval capability/memory system. If a computer cannot wake up rapidly enough, users may not prefer to allow it to be placed in sleep mode wasting energy.

SUMMARY

Briefly stated, technologies are generally described herein for multi-bit (multi-page) non-volatile static random access memory (NVSRAM) systems, which may enable computing devices to enhance their boot-up and/or wake-up speeds.

In some memory structures according to embodiments, a fast SRAM in an mNVSRAM block may serve as the buffer for a large block NVM memory to increase the data exchange rate between computing units or processor cores and the large NVM memory. The mNVSRAM blocks may also provide a fast boot function, where a boot code may be stored in the NVM parts of the mNVSRAM block, and due to the high bandwidth communication between fast SRAM part and the associated NVM memories, the boot code may be transferred into the fast SRAM in one or a few clock cycles enabling fast boot up function. Similarly, code stored in the NVM pans of an mNVSRAM block may be transferred into fast SRAM rapidly at wake-up time enabling fast wake up and voiding a need to wake up any other memory part, which may also result in energy savings for the computing system.

all arranged according to at least some embodiments presented herein.

DETAILED DESCRIPTION

This disclosure is generally drawn, inter alia, to technologies for multi-bit (multi-page) non-volatile static random access memory (NVSRAM) systems, which may enable computing devices to enhance their boot-up and/or wake-up speeds. In some examples, memory structures are provided, where a fast SRAM in an mNVSRAM block may serve as the buffer for a large block NVM memory to increase the data exchange rate between computing units or processor cores and the large NVM memory. The mNVSRAM blocks may also provide a fast boot function, where a boot code may be stored in the NVM parts of the mNVSRAM block, and due to the high bandwidth communication between fast SRAM part and the associated NVM memories, the boot code may be transferred into the fast SRAM in one or a few clock cycles enabling fast boot up function. When a computing system wakes up from a deep sleep mode, the code stored in the NVM parts of an mNVSRAM block may be transferred into the fast SRAM rapidly enabling fast wake up and voiding a need to wake up any other memory part, which may also result in energy savings for the computing system. The mNVSRAM block may be also used as a local memory to store the frequently used code. Then, the total system power may be reduced because the local memory does not need to charge a large array loading to fetch the data. In some cases, the SRAM part of the mNVSRAM block may be shared as one part of the entire computing system SRAM. The SRAM part of an mNVSRAM block may also be connected directly to a CPU and/or a large block NVM memory to be used directly by CPU.

As used herein, NVM memory may include, but is not limited to, a floating gate memory, a SONOS memory, a RRAM (resistive RAM), phase change memories, or magnetic base memories, such as MRAM, and STTRAM, or a Ferroelectric based RAM, or Ferroelectric capacitor based memory.

FIG. 1Ais a schematic circuit diagram illustrating an example NVSRAM cell formed by a combination of an SRAM cell with multiple NVM cells, arranged according to at least some embodiments presented herein.

Diagram100A shows a cell structure for an NVSRAM cell with an SRAM cell (fast SRAM) characterized by the word line SWL0and two bitlines BL106, BL#108coupled to multiple NVM cells110forming the rows. The NVM cells (e.g., floating gate) may be connected to the latch nodes Q/QB102,104of the SRAM cell.

FIG. 1Bis a schematics diagram of an array structure formed by the example NVSRAM cells ofFIG. 1A, arranged according to at least some embodiments presented herein.

Diagram100B shows three example NVSRAM cells112,114,116combined to form a memory array. Any number of cells may be combined to form multi-cell arrays. The fast SRAM cells share the same word line SWL0, while NVM cells of a same row share respective word lines such as nvWL0, nvWL1, etc. All NVSRAM cells may be coupled to SL110as shown in the diagram.

FIG. 2Ais a schematic circuit diagram illustrating another example NVSRAM cell formed by a combination of an SRAM cell with multiple NVM cells, arranged according to at least some embodiments presented herein.

Diagram200A shows a cell structure for an NVSRAM cell with an SRAM cell (fast SRAM) characterized by the word line SWL0and two bitlines BL206, BL#208coupled to multiple NVM cells210forming the rows. The NVM cells may be connected to the latch nodes Q/QB202,204of the SRAM cell. Each NVM cell includes a selective transistor to form the NVM cell with an NVM device.

FIG. 2Bis a schematics diagram of an array structure formed by the example NVSRAM cells ofFIG. 2A, arranged according to at least some embodiments presented herein.

Diagram200B shows three example NVSRAM cells212,214,216combined to form a memory array. Any number of cells may be combined to form multi-cell arrays. The fast SRAM cells share the same word line SWL0, while NVM cells of a same row share respective word lines such as nvWL0, nvWL1, etc. All NVSRAM cells may be coupled to SL210as shown in the diagram.

FIG. 3Ais a schematic circuit diagram illustrating a further example NVSRAM cell formed by a combination of an SRAM cell with multiple resistive NVM cells, arranged according to at least some embodiments presented herein.

Diagram300A shows a cell structure for an NVSRAM cell with an SRAM cell (fast SRAM) characterized by the word line SWL0and two bitlines BL306, BL#308coupled to multiple NVM cells310forming the rows. The NVM cells may be connected to the latch nodes Q/QB302,304of the SRAM cell. Each NVM cell includes an adjustable resistor and a transistor to form the NVM cell (resistive NVM device).

FIG. 3Bis a schematics diagram of an array structure formed by the example NVSRAM cells ofFIG. 3A, arranged according to at least some embodiments presented herein.

Diagram300B shows three example NVSRAM cells312,314,316combined to form a memory array. Any number of cells may be combined to form multi-cell arrays. The fast SRAM cells share the same word line SWL0, while NVM cells of a same row share respective word lines such as nvWL0, nvWL1, etc. All NVSRAM cells may be coupled to SL310as shown in the diagram.

FIG. 4Ais a schematic circuit diagram illustrating an example multi-bit SRAM cell formed by a combination of a fast SRAM cell with multiple capacitor based memory cells, arranged according to at least some embodiments presented herein.

Diagram400A shows a cell structure for an NVSRAM cell with an SRAM cell (fast SRAM) characterized by the word line SWL0and two bitlines BL406, BL#408coupled to multiple NVM cells410forming the rows. The NVM cells may be connected to the latch nodes Q/QB402,404of the SRAM cell. Each NVM cell includes an adjustable capacitor and a transistor to form the NVM cell (capacitive NVM device).

FIG. 4Bis a schematics diagram of an array structure formed by the example multi-bit SRAM cells ofFIG. 4A, arranged according to at least some embodiments presented herein.

Diagram400B shows three example NVSRAM cells412,414,416combined to form a memory array. Any number of cells may be combined to form multi-cell arrays. The fast SRAM cells share the same word line SWL0, while NVM cells of a same row share respective word lines such as nvWL0, nvWL1, etc. All NVSRAM cells may be coupled to SL410as shown in the diagram.

FIG. 5Ais a schematic circuit diagram illustrating an example multi-bit NVSRAM cell formed by a combination of a fast SRAM cell with multiple resistive NVM cells, arranged according to at least some embodiments presented herein.

Diagram500A shows a cell structure for an NVSRAM cell, where multiple rows of resistive NVM devices506,508are coupled through the latch nodes Q/Q′504/502. The bitlines connect the NVM cell rows, whereas the word lines are coupled to the gates of the NVM cell transistors. Each NVM cell includes an adjustable resistor and a transistor to form the NVM cell (resistive NVM device).

FIG. 5Bis a schematics diagram of an array structure formed by the example multi-bit NVSRAM cells ofFIG. 5A, arranged according to at least some embodiments presented herein.

Diagram500B shows two example NVSRAM cells512and514combined to form a memory array. Any number of cells may be combined to form multi-cell arrays. Word line SWL0couples to the gates of the transistors in the first row of devices, while NVM cells of a same row share respective word lines such as nvWL0, nvWL1, etc.

FIG. 6illustrates an example mNVSRAM block, arranged according to at least some embodiments presented herein.

Based on the cell structures described inFIG. 1Athrough SA, but not limited to these cell structures, mNVSRAM (multi-bit NVSRAM or multi-page NVSRAM) block/array devices may be formed. Typically, the SRAM cell and NVM cells are integrated at bit level. The stored data of one bit SRAM cell may be stored (written) to any one bit of its associated n-bit NVRAM cells, and the data stored in any one bit of the n-bit NVSRAM cells may be read by and/or loaded into its associated one bit SRAM. The one bit SRAM cell may serve as the interface for its associated n-bit NVRAM cells when data is exchanged with other devices (outside the mNVSRAM block).

In the example block of diagram600, the mNVSRAM block602may contain an A bit SRAM604, and an A×n bit NVM memory606. On some practical implementations, two NVRAM cells may be needed to form one bit NVM memory, but embodiments are not limited to this configuration. The bandwidth for this memory is A bit wide, which means A bit data stored on NVM may be transferred to/from SRAM in 1 or a few clock cycles.

FIG. 7illustrates an example memory architecture employing mNVSRAM, arranged according to at least some embodiments presented herein.

In the example memory structure702of diagram700using mNVSRAM for a computing system, the mNVSRAM block may serve a few functions: (1) The fast SRAM704in the mNVSRAM block may serve as the buffer for large block NVM memory710, which is typically relatively slow, and this arrangement may significantly increase the data exchange rate between CPU708(or other computing units/core) and the large NVM memory710; (2) The mNVSRAM block may provide a fast boot function. Boot code for the system may be stored in the NVM parts in the mNVSRAM block, and due to the high bandwidth communication between SRAM704and its associated NVM memories (706), the boot code stored in the NVM706in mNVSRAM block may be transferred into SRAM704in 1 or a few clock cycles enabling fast boot up function; (3) Deep sleep and fast wake up function. During deep sleep mode, all memory parts may be turned off. When the system wakes up, the code stored in the NVM706in mNVSRAM block may be transferred into SRAM704in 1 or a few clock cycles enabling fast wake up voiding a need to wake up any other memory part, which may also result in energy savings for the computing system; (4) The mNVSRAM block may be also used as a local memory to store the frequently used code. Then, the total system power may be reduced because the local memory does not need to charge a large array loading to fetch the data. In some cases, the SRAM704of the mNVSRAM block may be shared as one part of the system SRAM. The SRAM704in mNVSRAM block may also be connected directly to CPU708and/or the large block NVM memory710to be used directly by CPU708.

FIG. 8illustrates the use of an mNVSRAM block in a sensor hub application, arranged according to at least some embodiments presented herein.

Diagram800shows an example memory structure using an mNVSRAM block804for a sensor hub application. The driver and library for each sensor808may be stored into the NVM part806of the mNVSRAM block804, so they can be quickly loaded into SRAM802of the mNVSRAM block804to be executed quickly without using main memory to save energy and provide quick action. Each page of the mNVSRAM block804may store the driver and library for one sensor or multiple sensors. In some examples, the boot code may be stored into the mNVSRAM block804to achieve a fast boot up/wake up speed. The SRAM802of the mNVSRAM block804may be shut off in the sleep mode to reduce the standby power. In other cases, the large NVM memory block may be turned off to save power.

FIG. 9illustrates a multi-mode mNVSRAM block with a different NVRAM configuration, arranged according to at least some embodiments presented herein.

As shown in diagram900, each of the n NVM blocks/pages of the mNVSRAM (multi-bit NVSRAM or multi-page NVSRAM) block/array902may be configured or programmed or fabricated into different modes to serve different purposes. For example, NVM page/block906may be configured to high endurance mode to store data which needs to be written/erased frequently, while NVM page/block908may be configured to long retention mode used to store code which needs long retention time.

For example, in Ferroelectric RAM (FRAM), especially HfO2 based FRAM, the endurance and retention time can be modulated by program pulse (some RRAMs may also have this effect). So, by adjusting the program pulse, some NVM pages/blocks in the mNVSRAM may be configured to high endurance mode, and other NVM pages/blocks may be configured to long retention mode. Normally, there exists a trade-off between the endurance and retention. However, using the structure and schemes according to embodiments, a more balanced hybrid memory may be achieved.

Various types of transistors may be used in embodiments. The disclosure may use, for purposes of illustration, metal-oxide semiconductor field effect transistors (MOSFET). A MOSFET may have a source terminal (e.g., a first terminal), a drain terminal (e.g., a second terminal), and a control terminal. When an appropriate level of bias signal is applied to the control terminal, the transistor may be activated (e.g., biased into active operation) wherein conduction between the source terminal and the drain terminal may be facilitated. Depending on the type of transistor (e.g., N-type or P-type), an appropriate level of bias signal may be applied, or previously applied bias signal may be removed, to cause the transistor to be deactivated wherein conduction between the source and the drain may be abated. A MOSFET “terminal” may also be termed a “port.”

An NVM cell in the multi-bit or multi-page NVSRAM according to embodiments is not limited to floating gate memories, but may also be a SONOS cell, a RRAM (resistive RAM), phase change memories, or magnetic base memories, such as MRAM, and STTRAM, or a Ferroelectric based RAM, a Ferroelectric capacitor based memory, or comparable NVM cells.

Some embodiments are directed to example processes to operate low power memory systems. The operations of any process described herein are not necessarily presented in any particular order and that performance of some or all of the operations in an alternative order(s) is possible and is contemplated. The operations have been presented in the demonstrated order for ease of description and illustration. Operations may be added, combined, modified, omitted, and/or performed simultaneously, in a different order, etc., without departing from the scope of the present disclosure.

The illustrated process can be ended at any time and need not be performed in its entirety. Some or all operations of the processes, and/or substantially equivalent operations, can be performed by execution by one or more processors of computer-readable instructions included on a computer storage media, such as described herein, including a tangible non-transitory computer-readable storage medium. The term “computer-readable instructions,” and variants thereof, as used in the description and claims, is used expansively herein to include routines, applications, application modules, program modules, programs, components, data structures, algorithms, or the like. Computer-readable instructions can be implemented on various system configurations, including single-processor or multiprocessor systems, minicomputers, mainframe computers, personal computers, hand-held computing devices, microprocessor-based, programmable consumer electronics, combinations thereof, or the like.

FIG. 10is a block diagram illustrating an example computing device1000that is arranged for implementing and/or operating low power memory systems as discussed herein, in accordance with at least some embodiments described herein. In a very basic configuration1002, computing device1000typically includes one or more processors1004and system memory1006. A memory bus1008can be used for communicating between the processor1004and the system memory1006.

Depending on the desired configuration, processor1004can be of any type including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor1004can include one more levels of caching, such as cache memory1012, a processor core1014, and registers1016. The processor core1014can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. A memory controller1018can also be used with the processor1004, or in some implementations the memory controller1010can be an internal part of the processor1004.

Depending on the desired configuration, the system memory1006can be of any type including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof. System memory1006typically includes an operating system1020, one or more applications1022, and program data1024.

Computing device1000can have additional features or functionality, and additional interfaces to facilitate communications between the basic configuration1002and any required devices and interfaces. For example, a bus/interface controller1040can be used to facilitate communications between the basic configuration1002and one or more data storage devices1032via a storage interface bus1034. The data storage devices1032can be removable storage devices1036, non-removable storage devices1038, or a combination thereof. Examples of removable storage and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard-disk drives (HDDs), optical disk drives such as compact disk (CD) drives or digital versatile disk (DVD) drives, solid state drives (SSDs), and tape drives to name a few. Example computer storage media can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.

System memory1006, removable storage1036and non-removable storage1038are all examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device1000. Any such computer storage media can be part of device1000. Thus, any of the computer storage media may be implemented using the SRAM based memory structures as discussed herein.

Computing device1000can also include an interface bus1040for facilitating communication from various interface devices (e.g., output interfaces, peripheral interfaces, and communication interfaces) to the basic configuration1002via the bus/interface controller1030. Example output devices1042include a graphics processing unit1048and an audio processing unit1050, which can be configured to communicate to various external devices such as a display or speakers via one or more A/V ports1052. Example peripheral interfaces1044include a serial interface controller1054or a parallel interface controller1056, which can be configured to communicate with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device, etc.) or other peripheral devices (e.g., printer, scanner, etc.) via one or more I/O ports1058. An example communication device1046includes a network controller1060, which can be arranged to facilitate communications with one or more other computing devices1062over a network communication via one or more communication ports1064. The communication connection is one example of a communication media. Communication media may typically be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery media. A “modulated data signal” can be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, communication media can include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared (IR) and other wireless media. The term computer readable media as used herein can include both storage media and communication media.

It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations.

However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations).

Further, the use of the terms “first,” “second,” “third,” “fourth,” and the like is to distinguish between repeated instances of a component or a step in a process and does not impose a serial or temporal limitations unless specifically stated to require such serial or temporal order.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments are possible. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.