Asymmetric circuitry

Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.

BACKGROUND

Technical Field

This disclosure relates generally to computer processing and more specifically to asymmetric circuits.

Description of the Related Art

Software registers are used in various contexts to store values for relatively long periods of time, including: handling different use cases, working around bugs, storing parameters for processing large amounts of data, etc. In digital signal processing, coefficients are often stored in software registers and can be used to fine tune filter behavior. Similar parameters are also used in wireless communications and other applications.

Often, parameters or coefficients stored in registers do not change (or are not allowed to change) for a known period of time (e.g., a frame of video data). Thus, the register values may remain fixed over many computations. For example, a register may store a coefficient to be used for millions of samples before the coefficient changes.

SUMMARY

Techniques are disclosed relating to asymmetric circuits.

In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values.

In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption in contexts in which an input to the asymmetric circuit is constant over a time interval.

In some embodiments, a multiplier circuit is configured to encode an input using high-order encoding such as radix-8 or higher encoding, for example. In some embodiments, the circuitry is configured such that the encoding lowers the toggle activity of the circuit, which may reduce dynamic power consumption. In some embodiments, another active input to the multiplier is not encoded at all, which may reduce the critical path for this active input.

In some embodiments, an exclusive-or circuit is configured to drive a smaller number of transistors with an active input than the number of transistors driven by a programmable constant input. This may reduce the critical path and reduce dynamic power consumption. In some embodiments, one or more transistors driven by the programmable constant input are low-leakage transistors.

In some embodiments, a multiplexer is configured to encode a select signal. In one embodiment, the encoding is one-hot encoding. This may reduce overall power consumption by the multiplexer and may reduce a critical path for inputs to the multiplexer.

Further, as used herein, the terms “first,” “second,” “third,” etc. do not necessarily imply an ordering (e.g., temporal) between elements. For example, a reference to a “first” number of clock edges and a “second” number of clock edges may refer to any two different numbers of clock edges. In short, references such as “first,” “second,” etc. are used as labels for ease of reference in the description and the appended claims.

DETAILED DESCRIPTION

This disclosure initially describes, with reference toFIGS. 1-2, an overview of an asymmetric circuit and an exemplary device. Exemplary embodiments of asymmetric circuits described in further detail with reference toFIGS. 3-8. In some embodiments, the techniques disclosed herein may increase performance and reduce power consumption in circuits when a circuit input is maintained as a constant over a time interval.

Referring now toFIG. 1, a block diagram illustrating one embodiment of a circuit100is shown. In the illustrated embodiment, circuit100includes asymmetric circuit110and storage element120. In various embodiments, asymmetric circuit110may be configured asymmetrically with respect to its inputs in order to increase the speed and/or reduce the power consumption of circuit100.

Storage element120, in the illustrated embodiment, is configured to maintain programmable constant value150over a given time interval. Said another way, circuit100is configured to ensure that programmable constant value150does not change over the given time interval. Storage element120may be a software register, for example, and may be configured such that software cannot change the value stored during the given time interval. For example, storage element120may be configured to never change while asymmetric circuit110is operating, only changing when asymmetric circuit110is not currently operating. The time interval may correspond to a frame of video data in some embodiments, e.g., when storage element120is configured to store a filter coefficient. Thus, the term “constant” as used herein does not imply that a value never changes, but simply that the value does not change relative to some time period, fixed number of operations, fixed amount of data, etc. Also, programmable constant150is different than a constant or hardwired input, e.g., because it can change. Active input130, in various embodiments, may take on multiple values during operations using a single value of programmable constant value150. Based on the knowledge that programmable constant value will not change often, relative to active input130, asymmetric circuit110may be improved relative to symmetric circuitry configured to perform the same operation.

Asymmetric circuit110, in the illustrated embodiment, is configured to receive programmable constant value150and active input130, perform an operation based on the inputs, and generate output140. Asymmetric circuit110may be configured to perform various operations such as arithmetic operations, logical operations, instruction processing operations, etc. In particular exemplary embodiments discussed below, asymmetric circuit110is a multiplier, a multiplexer (MUX), or an exclusive-or (XOR) circuit. However, these embodiments are exemplary only and are not intended to limit the functionality of asymmetric circuit110.

As used herein, the term “asymmetric circuit” refers to circuitry that is at least one of “leakage power asymmetric” and “critical path asymmetric” as those terms are defined below. Generally, these types of asymmetry are defined with reference to different ones of a plurality of inputs to a circuit. In this discussion, two inputs A and B may be used for exemplary purposes, but asymmetric circuitry may be implemented with any number of inputs.

A circuit is “critical path asymmetric” if it is configured such that the critical path between a first input and an output of the circuit is at least one and a half times greater in time than the critical path between a second input and the output. A critical path corresponds to the minimum time between a change in an input a circuit and a point in time at which the output of the circuit is valid based on the input. Critical path asymmetry may or may not be related to leakage power asymmetry. For example, critical path asymmetry may be caused by circuit design (e.g., input B may drive a path that includes more components than any path driven by input A, resulting in a longer critical path even when the components have the same leakage characteristics). Some types of circuits may be critical path asymmetric by their nature, but the critical path asymmetry of such circuits may be increased or changed (e.g., such that another input has a longest critical path for the circuit) by encoding one of the inputs, thereby increasing the critical path for that input and often allowing decreased critical paths for other inputs.

A circuit is “leakage power asymmetric” if it includes a first portion with a first set of one or more inputs that uses circuit elements (e.g., transistors, etc.) with lower leakage power consumption than circuit elements of a second portion of the circuit with a second set of one or more inputs. For example, input A may be used to drive high-speed transistors with high leakage power while input B may be used to drive lower-speed transistors with lower leakage power. Note that some portions of leakage power asymmetric circuitry may be driven by both input A and input B, so long as other portions are driven by only input A or input B and have different leakage power characteristics. For various transistor circuitry, a circuit is considered to be leakage power asymmetric if transistors driven by a first input have a nominal threshold voltage that is at least 30% higher than the threshold voltage of transistors driven by a second input.

“Leakage power” is power that is consumed simply because a circuit is on. This is in contrast to dynamic power, which is consumed (for digital circuitry) when changing logic states. Leakage power in metal-oxide semiconductor (MOS) transistors may include reverse biased diode leakage (related to parasitic diodes formed between diffusion region and substrate), gate induced drain leakage (current flowing between drain and substrate), gate-oxide tunneling, subthreshold leakage (related to the weak inversion effect, drain-induced barrier lowering, and direct punch-through of electrons between drain and source), etc. Lowering the threshold voltage of transistors generally increases all of these effects (typically exponentially) and thus increases leakage power, but may increase computation speed. In contrast, transistors with a high threshold voltage may reduce computation speed but can greatly reduce leakage power. Various transistors described herein are MOS transistors, but similar techniques may be implemented using various field effect transistors as well as other transistors technologies such as bipolar junction transistors, for example.

A circuit may also be described as “area asymmetric.” Area symmetric circuits may or may not be leakage power asymmetric or critical path asymmetric. A circuit is “area asymmetric” if a given input drives at least one and a half times the amount of circuitry as another input. For example, input A may drive 20 transistors while input B may drive only 10 transistors. Some circuits may be naturally area asymmetric, e.g., based on their function. However, designing functionally symmetric circuits (such as NAND gates or XOR gates, for example) to be area asymmetric may reduce power consumption in some embodiments. Circuitry that is area asymmetric may have low dynamic power consumption when the area of circuitry driven by a dynamic/active input is small reducing the amount of toggle activity. Speaking generally, reducing circuitry driven by an active input reduces toggle activity and dynamic power consumption.

Referring now toFIG. 2, a block diagram illustrating an exemplary embodiment of a device200is shown. In some embodiments, elements of device200may be included within a system on a chip. In some embodiments, device200may be included in a mobile device, which may be battery-powered. Therefore, power consumption by device200may be an important design consideration. In the illustrated embodiment, device200includes fabric210, compute complex220, input/output (I/O) bridge250, cache/memory controller245, graphics unit260, display unit265, and data processing unit270.

Fabric210may include various interconnects, buses, MUX's, controllers, etc., and may be configured to facilitate communication between various elements of device200. In some embodiments, portions of fabric210may be configured to implement various different communication protocols. In other embodiments, fabric210may implement a single communication protocol and elements coupled to fabric210may convert from the single communication protocol to other communication protocols internally.

In the illustrated embodiment, compute complex220includes bus interface unit (BIU)225, cache230, and cores235and240. In various embodiments, compute complex220may include various numbers of cores and/or caches. For example, compute complex220may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache230is a set associative L2 cache. In some embodiments, cores235and/or240may include internal instruction and/or data caches. In some embodiments, a coherency unit (not shown) in fabric210, cache230, or elsewhere in device200may be configured to maintain coherency between various caches of device200. BIU225may be configured to manage communication between compute complex220and other elements of device200. Processor cores such as cores235and240may be configured to execute instructions of a particular instruction set architecture (ISA) which may include operating system instructions and user application instructions.

Cache/memory controller245may be configured to manage transfer of data between fabric210and one or more caches and/or memories. For example, cache/memory controller245may be coupled to an L3 cache, which may in turn be coupled to a system memory. In other embodiments, cache/memory controller245may be directly coupled to a memory. In some embodiments, cache/memory controller245may include one or more internal caches.

As used herein, the term “coupled to” may indicate one or more connections between elements, and a coupling may include intervening elements. For example, inFIG. 2, graphics unit260may be described as “coupled to” a memory through fabric210and cache/memory controller245. In contrast, in the illustrated embodiment ofFIG. 2, graphics unit260is “directly coupled” to fabric210because there are no intervening elements.

Graphics unit260may be configured as described above with reference toFIGS. 1B, 2, and 3. Graphics unit260may include one or more processors and/or one or more graphics processing units (GPU's). Graphics unit260may receive graphics-oriented instructions, such OPENGL® or DIRECTED® instructions, for example. Graphics unit260may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit260may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display. Graphics unit260may include transform, lighting, triangle, and/or rendering engines in one or more graphics processing pipelines. Graphics unit260may output pixel information for display images. In some embodiments, graphics unit260may include a programmable shader core configured to perform both vertex and pixel processing.

Data processing unit270may be configured to process various types of data, e.g., in conjunction with other elements of device200. For example, data processing unit270may be configured to perform generic image processing, video processing, or communications data processing. Data processing unit270, in some embodiments may include asymmetric circuitry. This circuitry may be used for processing images, frames of video, frames of communications data, and/or various other data blocks.

Display unit265may be configured to read data from a frame buffer and provide a stream of pixel values for display. Display unit265may be configured as a display pipeline in some embodiments. Additionally, display unit265may be configured to blend multiple frames to produce an output frame. Further, display unit265may include one or more interfaces (e.g., MIPI® or embedded display port (eDP)) for coupling to a user display (e.g., a touchscreen or an external display).

Peripheral unit255, in some embodiments, may be coupled to various internal or external peripherals such as one or more cameras, for example. In some embodiments, peripheral unit255may include an image signal processor which may be configured to perform various operations on image and/or video data. In some embodiments, the image signal processor includes asymmetrical circuitry as described herein. In other embodiments, asymmetrical circuitry may be included in various elements of device200including, for example, graphics unit260, display unit265, and/or various additional elements that are not shown inFIG. 2.

Referring now toFIG. 3A, a block diagram illustrating one embodiment of a multiplier300is shown. In the illustrated embodiment, multiplier300includes partial product selection305, adder array310, radix encoder320, and booth encoder325.

Booth encoder325, in the illustrated embodiment, is configured to encode multiplicand340and provide the result to partial product selection305.

Radix encoder320, in the illustrated embodiment, is configured to encode multiplier330using radix encoding (e.g., radix-4, which may involve multiplying multiplier330by 0, 1, 2, and 3) and provide the resulting partial products to partial product selection305.

Partial product selection305, in the illustrated embodiment, is configured to select from among the partial products based on the input from booth encoder325and provide the selected partial products to adder array310.

Adder array310, in the illustrated embodiment, is configured to add the selected partial products to produce multiplication result345.

Multiplier300, in the illustrated embodiment, may be designed to be substantially symmetric. For example, a critical path from multiplier330to result345may be similar in length to a critical path from multiplicand340to result345. Further, the types of transistors driven by multiplier330and multiplicand340may be the same or may have similar leakage power characteristics. Thus, multiplier300may not be an asymmetric circuit.

Referring now toFIG. 3B, a block diagram illustrating one embodiment of an asymmetric multiplier350is shown. In the illustrated embodiment, multiplier350includes partial product selection355, adder array360, and high-order radix encoder370.

High-order radix encoder370, in the illustrated embodiment, is configured to encode programmable constant value380using radix-8, radix-16, or some other high-order radix encoding. High-order radix encoding may be time consuming in comparison to radix-4, for example, because some partial products (such as multiplication by 5 and 7) take more time to generate. However, because programmable constant value380is guaranteed to be constant for a given time interval, high-order radix encoding may be efficient overall, because the resulting partial products may be used for many multiplication operations (e.g., for multiple values of active input390). Active input390, in the illustrated embodiment, is not encoded, but is provided directly to partial product selection355.

Partial product selection355, in the illustrated embodiment, is configured to select from partial products generated by high-order radix encoder370based on active input390(which is not encoded in the illustrated embodiment) and pass the selected partial products to adder array360.

Adder array360, in the illustrated embodiment, is configured to add the selected partial products to produce multiplication result395. In comparison to adder array310of multiplier300, adder array360may include significantly less circuitry because the number of partial products may be smaller as a result of the high-order encoding. This may significantly reduce dynamic power consumption by adder array360in comparison to adder array310, for example.

Further, in some embodiments, multiplier350is critical path asymmetric because the critical path for active input390is significantly shorter than the critical path for programmable constant value380. For example, the critical path for a multiplier with radix-8 encoding may include circuitry for only N/3 additions while the critical path for a multiplier with radix-4 encoding may include circuitry from N/2 additions (where N is the number of bits in the multiplier and multiplicand). Further, in some embodiments, the circuitry in high-order radix encoder370includes using low-leakage circuitry (e.g., transistors with a high threshold voltage) relative to circuitry in partial product selection355, so multiplier350may be leakage power asymmetric. In the illustrated embodiments, the radix encoding does not affect dynamic power consumption or the critical path of multiplier350.

In various embodiments, multiplier350may achieve increased performance and/or lower power consumption overall in comparison with multiplier300. These advantages may be the result of one or more of: lower-leakage circuitry used in encoding, a shorter critical path for the active input, and reduced circuitry in the adder array.

In other embodiments, various types of encoding may be performed in place of and/or in addition to radix encoding. The particular types of encoding ofFIGS. 3A-3Bare included for exemplary purposes and are not intended to be limiting.

Referring now toFIGS. 4A-4B, diagrams illustrating embodiments of a MUX410and an XOR circuit420are shown. These elements may be implemented using asymmetric circuitry as described in further detail below with reference toFIGS. 6A-6B and 7B.

MUX410, in the illustrated embodiment, is a four-to-one MUX configured to select one of inputs A-D based on select bits S0and S1. In other embodiments, MUXs of various sizes (e.g., having various numbers of select bits) may be implemented using similar techniques. In the embodiments ofFIGS. 6A-6B, MUX410is implemented using asymmetric circuitry for a select signal that is a programmable constant.

XOR circuit420, in the illustrated embodiment, is configured to generate an output based on inputs A and B. XOR circuit420is configured to generate a true output (e.g., a high voltage or a ‘1’) when an odd number of inputs to XOR circuit420are true. In the illustrated embodiment, XOR circuit420is a two-input circuit, but in other embodiments, XOR circuits having larger numbers of inputs may be implemented using similar techniques. In the embodiment ofFIG. 7B, XOR420is implemented using asymmetric circuitry for one input that is a programmable constant.

Referring now toFIGS. 5A-5B, diagrams illustrating exemplary embodiments of MUXs510and520are shown. Both MUXs are four-to-one MUXs with four inputs A-D and two select bits S0and S1. In the illustrated embodiment, MUX510is pass transistor implementation while MUX520is a CMOS implementation. Each implementation includes twelve transistors that are controlled by the select signal (which also drives two inverters, not shown). In the illustrated embodiment, !S0represents the inverse of S0and !S1represents in the inverse of S1. If the select signal is constant or programmable constant, MUXs510and520may be improved as shown inFIGS. 6A-6B.

Referring now toFIGS. 6A-6B, diagrams illustrating exemplary embodiments of asymmetric MUX circuits610and620are shown. As inFIG. 5, both MUXs are four-to-one MUXs with four inputs A-D and two select bits S0and S1. In the illustrated embodiment, MUX610is pass transistor implementation while MUX620is a CMOS implementation. In the illustrated embodiment, the select bits are one-hot encoded using circuitry that is not shown (e.g., AND gates) to generate select signals SA-SD. In the embodiments ofFIG. 6, inputs A, B, C, and D each travel through one less transistor before reaching the output, relative to the embodiments ofFIG. 5. This may result in lower delay and dynamic power consumption relative to the embodiments ofFIG. 5. For example, relative to the circuits ofFIG. 5, the circuits in the illustrated embodiments ofFIG. 6may have a critical path that is ⅔ of the length and consume ⅔ the amount of dynamic power.

In some embodiments, because the transistors driven by the select signals SA-SDwill not be switching often, a high threshold voltage can be used for those transistors, further reducing power consumption. In these embodiments, MUX620is leakage power asymmetric. In some embodiments, low-leakage circuitry is also used in encoding select signals SA-SD. Because of the encoding, MUXs610and620are typically critical path asymmetric. This may increase performance in various embodiments by reducing the critical path of the inputs A-D, because the critical path of the select signal is relatively unimportant if the select signal is programmable constant.

The exemplary circuit layouts and transistor types shown inFIGS. 6A-6Bare not intended to be limiting; other asymmetrical layouts and transistor topologies are contemplated.

Referring now toFIG. 7A, a diagram illustrating one embodiment of an XOR circuit710is shown. In the illustrated embodiment, each input (A or B) drives four transistors directly, typically resulting in the same power and delay with respect to each input. XOR circuit710may be naturally symmetrical in the illustrated embodiment.

Referring now toFIG. 7B, a diagram illustrating one embodiment of an asymmetrical XOR circuit750is shown. In this embodiment, the input B is programmable constant. In this embodiment, the input B is coupled to drive six transistors (including four gate terminals) while the active input A is coupled to drive four transistors (including only two gate terminals). XOR circuit750may not be the smallest achievable XOR circuit in terms of number of transistors, but it is highly asymmetric. This may result in a shorter critical path for the active input A, which may in turn result in increased performance relative to the embodiment ofFIG. 7A. This may also reduce active power consumption. In some embodiments, transistors M1, M2, and M7may have a high threshold voltage relative to the remaining transistors in order to reduce leakage power. This may result in reduced power consumption relative to the embodiment ofFIG. 7A.

The exemplary circuit layout and transistor types shown inFIG. 7Bare not intended to be limiting; other asymmetrical layouts and transistor topologies are contemplated. In other embodiments, other types of asymmetric circuits are contemplated in addition to and/or in place of the exemplary multiplier, MUX, and XOR circuits discussed herein.

Referring now toFIG. 8, a flow diagram illustrating one exemplary embodiment of a method800using asymmetric circuitry is shown. The method shown inFIG. 8may be used in conjunction with any of the computer systems, devices, elements, or components disclosed herein, among other devices. In various embodiments, some of the method elements shown may be performed concurrently, in a different order than shown, or may be omitted. Additional method elements may also be performed as desired. Flow begins at block810.

At block810, a first input value is provided (e.g., by storage element120) to a first portion of a circuit. In the illustrated embodiment, the first input value does not change during the time interval. The time interval may corresponding to processing performed for a frame of video data or wireless communication data, for example. Flow proceeds to block820.

At block820, respective ones of a set of second input values are provided to a second portion of the circuit. In the illustrated embodiment, the first and second portions of the circuit are asymmetric. In some embodiments, the first and second portions are both leakage power asymmetric and critical path asymmetric. In some embodiments, the first input value may be held constant while performing operations using a large number of second input values. Flow proceeds to block830.

At block830, multiple output values are generated (e.g., by multiplier350, MUX610, MUX620, or XOR circuit750in some embodiments) during the time interval, based on the first input value and the respective ones of the set of second input values. Flow ends at block830.