A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

The present invention is directed generally to data communication. More particularly, the present invention relates to methods and arrangements for data transfer using a two-phase handshaking protocol.

Ongoing demands for more-complex circuits have led to significant achievements that have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as a set of functionally-defined modules that process data and then transfer the processed data to other modules for further processing. This communication between functionally-defined modules can pass small or large amounts of data between modules within the same integrated circuit or between more remotely-located communication circuit arrangements and systems. Regardless of the configuration, the communication typically requires closely controlled interfaces to insure that data integrity is maintained and that integrated circuit designs are sensitive to practicable limitations in terms of implementation space and available operating power.

With the increased complexity of circuits, there has been a commensurate demand for increasing the speed at which data is passed between the modules. Many of these high-speed communication applications can be implemented using parallel data interconnect transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such “parallel bussing” is a well-accepted approach for achieving data transfers at high data rates.

A typical system might include a number of modules that interface to and communicate over a parallel data bus, for example, in the form of an internal bus on an integrated circuit, a cable, and/or other interconnect. A transmitting module transmits data over the bus synchronously with a clock on the transmitting module. In this manner, the transitions on the parallel signal lines leave the transmitting module in a synchronous relationship to each other and to a clock on the transmitting module. At a remote end of the parallel data interconnect, a receiving module receives the data on a parallel data bus. In such systems, the received signals should have a specific phase relationship with a clock on the receiving module in order to provide proper data recovery.

Many integrated circuits include more than one clock domain; therefore a data-transmitting module might be operating in one clock domain at a first clock frequency, while a data-receiving module is operating in another clock domain at a different second clock frequency. Multiple clock domains may also occur for a data-transmitting module and a data receiving operating at the same clock frequency, but having an unknown phase relationship. The interface between clock domains is a clock domain boundary, or a clock domain crossing where information crosses the boundary.

Where transmitting and receiving modules reside in different clock domains, synchronization is required to maintain the integrity of data transferred across the clock domain boundary. A handshaking protocol or intermediate buffers may be used to implement the required synchronization at the clock domain crossing. Synchronization buffers are conventionally used for point-to-point communication between two clock domains, such as illustrated in U.S. Pat. No. 6,154,803, “Method and Arrangement for Passing Data between a Reference Chip and an External Bus”. A handshaking protocol can be used for synchronization of a parallel bus between more than two clock domains corresponding to multiple modules interfacing with the parallel bus. However, the conventional handshaking protocol in such an environment is a four-phase handshake protocol that limits the possible data transfer rate.

Implementing integrated circuits using a plurality of clock domains is desirable for a variety of reasons, for example, the device control and status network (DCS network) from Philips Semiconductors permits a controller to communicate with multiple peripherals, with each peripheral potentially having a separate clock source. Accordingly, improving data communication over parallel busses between clock domains permit more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to serving the demands for high-speed circuits. Various aspects of the present invention address the above-mentioned deficiencies and also provide for communication methods and arrangements that are useful for other applications as well.

Various aspects of the present invention are directed to data transfer in a manner that addresses and overcomes the above-mentioned issues. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Another embodiment of the present invention discloses a method for the transferring a first data value associated with a read operation. The read operation is produced and identifies one of a plurality of target modules. The first data value is produced by the identified target module. A respective second data value is generated by each of the target modules, with the second data value modified for the identified target module by an exclusive-or operation between the first data value and a previous second data value, and with the second data value remaining unmodified for the target modules besides the identified target module. A respective first validation value is also generated by each of the target modules, with the first validation value modified for the identified target module, and the first validation value remaining unmodified for the target modules besides the identified target module. An exclusive or operation generates a second validation value from the first validation values. The availability of the first data value is determined from a modification of the second validation value. An exclusive-or operation generates a third data value from the second data values. The first data value is determined by an exclusive-or operation between the third data value and a previous third data value.

The present invention is believed to be generally applicable to methods and arrangements for transferring data between modules. The invention has been found to be particularly advantageous for transferring data between modules that reside in different clock domains. Examples of such applications include, among others, system on-chip using a controller in one clock domain that communicates with multiple integrated peripherals that can each potentially reside in a distinct clock domain, and high-speed communication between integrated circuits that can be situated on one or more printed circuit boards. While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.

According to one example embodiment of the present invention, a data communication arrangement has multiple targets that each provide an acknowledgment signal and a data bus. Each target uses a transition of the respective acknowledgment signal to indicate the availability of data on the respective data bus. An exclusive-or function of all the acknowledgment signals generates a global acknowledgment signal, and a transition on one of the acknowledgment signals for a target propagates to an associated transition on the global acknowledgment signal. Each target encodes data on the data bus with a parallel exclusive-or between the data from the target and the previous encoded data. A parallel exclusive-or function of all the data buses generates a global data bus. A controller determines the availability of data on the global data bus by observing a transition in the global acknowledgment signal. The controller decodes the data from the global data bus by a parallel exclusive-or between the current and previous value of the global data bus. The controller indicates acceptance of the data, and possibly provides a subsequent access request, by toggling a request signal corresponding to the target.

Various embodiments of the invention permit data transfer in a manner similar to a parallel bus interface between a controller module and multiple target modules, while permitting efficient data transfer using a two-phase transfer protocol. The two-phase transfer protocol eliminates two recovery phases, which do not transfer data, from the prior four-phase transfer protocol. Data transfer occurs efficiently because after a data transfer using the two-phase protocol another transfer can immediately occur by repeating the two phases of the two-phase protocol instead of the recovery phases of the prior four-phase protocol. Elimination of the recovery phases can also reduce the power required for a data transfer because signal switching is eliminated that is associated with returning the data bus to a default value, as is typically implemented during the recovery phase in the prior four-phase transfer protocol. The two alternating phases of the two-phase protocol are a request phase, which may acknowledge acceptance of the result for a prior request, and an acknowledgment phase. The controller module and each of the target modules can reside in separate clock domains.

Referring toFIG. 1, a block diagram is shown for an example data communication arrangement100between a controller module102and a plurality of target modules104, according to the present invention. The controller module102can request data from any one of the target modules104. Typically, the controller module102does not simultaneously overlap multiple requests to the target modules104.

Upon a target module104obtaining data to send to the controller module102, such as the data to satisfy a read request from the controller module102, the target module104sends the data to the controller module102via a corresponding data bus on a line106. In one embodiment, the data sent by a target module104to the controller module102via a corresponding data bus on a line106can be encoded as is later described in detail. Together with sending the data via a corresponding data bus on a line106, a target module104modifies the current value of a corresponding acknowledge signal on a line108to indicate that valid data is available. The modification of an acknowledge signal on a line108by a target module104can be a toggling of the value of the acknowledge signal on the line108. Thus, either a low to high or a high-to-low transition of an acknowledge signal on a line108can indicate that data is available from the corresponding target module104on the corresponding data bus on a line106.

A target module104does not modify the value of the corresponding acknowledge signal on a line108unless the target module104is indicating that data is available. A target module104does not modify the value of the corresponding data bus on a line106unless the target module104is sending data to the controller module102.

An exclusive-or function110generates the exclusive-or of all the acknowledge signals on lines108to produce the global acknowledge signal on line111. The exclusive- or function110has the property that a transition on any one of the acknowledge signals on a line108is propagated to a transition on the global acknowledge signal on line111. Thus, the bus controller102can determine from a transition of the global acknowledge signal on line111that a target104is indicating that data is available on a corresponding data bus on a line106.

A parallel exclusive-or function112generates the global data bus on line114from all the data busses on lines106. Typically, the data busses on lines106and the global data bus on line114have identical bit widths of one or more signals. The parallel exclusive-or function112generates each bit of the global data bus on line114from an exclusive-or of a corresponding bit from the data busses on lines106, for example, the least significant bit of the global data bus on line114is generated from an exclusive-or of the least significant bit from each of the data busses on lines106.

The parallel exclusive-or function112has the property that any modification of a data bus on a line106is propagated to a modification of the global data bus on line114. While the data sent by a target module104is not generally transferred unmodified from a target module104to the controller module102, the modification observed on the global data bus114by the controller module102may be used to determine the data value sent by the target module104on a data bus on a line106as is later discussed in detail.

While the data communication arrangement100is typically used for binary logic systems, it will be appreciated that the data communication arrangement100can be used for other logic systems, such as ternary logic systems.

It should be understood that the elements described inFIG. 1are for description only, to aid in the understanding of the present invention. As is known in the art, elements described as hardware may equivalently be implemented in software. Reference to specific electronic circuitry is also only to aid in the understanding of the present invention, and any circuit to perform essentially the same function is to be considered an equivalent circuit.

Referring toFIG. 2, a block diagram is shown of an example data communication arrangement illustrating distributed exclusive-or trees, according to the present invention. A controller module102communicates data with multiple target modules104. XOR gates202,204,206, and208form an XOR tree and collectively correspond to exclusive-or function110ofFIG. 1. XOR gates210,212,214, and216form an XOR tree and collectively correspond to exclusive-or function112ofFIG. 1. The XOR tree formed by XOR gates202,204,206, and208generates the global acknowledge signal on line111from the acknowledge signals on lines108of the target modules104. The XOR tree formed by XOR gates210,212,214, and216generates the global data bus on line114from the data buses on lines106of the target modules104.

An XOR tree, such as the XOR tree formed by XOR gates202,204,206, and208, can have a number of arrangements as long as the overall function of the tree produces an output, such as the global acknowledge signal on line111, that is the exclusive-or of the inputs, such as the acknowledge signals on lines108. The individual bits of the global data bus on line114can each have a XOR tree with a distinct arrangement.

Each XOR tree can have a distributed arrangement selected to reduce the wiring required to implement the XOR tree. For example, the placement of modules102and104inFIG. 2can roughly correspond to the physical placement of the modules102and104on an integrated circuit, and a first level of clustering of the modules102and104based on adjacent physical locations can be used to produce a first level of an XOR tree, such as is shown for a first level of XOR gates204,206, and208. Physical clustering of modules can be used at each level of an XOR tree. The wiring required can be significantly reduced, especially when there are a large number of target modules104. A distributed XOR tree also can eliminate long signal lines on an integrated circuit or other system, thereby eliminating excessive propagation delays that can be associated with long signal lines.

Referring toFIG. 3, a block diagram is shown of an example target module104, according to the present invention. A target module104includes a target interface302used to interface target logic304of the target module104with the controller module (not shown).

The controller module can provide an access request to the target module104on the access bus on line306. The request signal on line308can be used to indicate that a valid access request is on the access bus on line306, and can also be used to indicate that a result from the target module104for the previous access request was accepted by the controller module. A no-operation (NOP) access request can be used to indicate acceptance of the result for the previous access request without indicating an additional access request that requires processing by the target module104. A modification, such as a toggling, of the request signal on line308can be used to indicate availability of an access request on the access bus on line306, and can also be used to indicate acceptance by the controller module of the result for the previous access request.

The target module104and the controller module can operate in different clock domains, such that synchronization is required for communication between the target module104and the controller module. A first register310may sample the request signal on line308based on the local clock of the target module104. Since the respective clocks of the controller module and the target module104may not be synchronized, the first register310can sample the request signal on line308during a transition of the request signal on line308. Thus, signal312can have an undefined meta-stable value immediately after the sampling by the first register310. Generally, any meta stability of signal312is resolved by first register310before being sampled by the second register314, and thus registers310and314synchronize the request signal on line308with the local clock of the target module104. Typically, the second register (or flip flop)314is used only if the target module and controller module are in different clock domains; in an alternative embodiment, where the target is in the same domain as the controller, this second register314is bypassed.

Because the controller module provides the transition of the request signal on line308together with the corresponding access request on the access bus on line306, a transition on the synchronized request signal on line316is not recognized by target logic304unless the access bus on line306has had a stable value for at least one clock cycle of the local clock of the target module104. Thus, register318samples and provides a stable value on line320whenever the synchronized request signal on line316has a transition. When the synchronized request signal on line316does not have a transition an access request on line320may have a meta stable value and this potentially meta-stable value should be ignored by the target logic304.

An access request provided on the access bus on line306can be a read access to a memory or other location, such as an I/O location, associated with the target104. After obtaining the data associated with the read access, the target logic304may provide the data on line322and assert the update signal on line324for a single clock cycle of the target104clock. The inverter326, multiplexer328, and register330transform the pulse for the update signal on line324into an acknowledge transition on line108that is propagated to the controller module via an XOR tree, such as exclusive-or function110ofFIG. 1. The XOR gate332, multiplexer334and register336encode the data associated with the read access on line322. The encoded data has a transition on a bit of the data bus on line106for a corresponding bit of the data on line322having a value of one, and the encoded data does not have a transition on a bit of the data bus on line106for the corresponding bit of the data on line322having a value of zero.

It will be appreciated that a bit of the encoded data on line106can instead have a transition for the data on line322having a value of zero and not have a transition for the data on line322having a value of one. In another embodiment, the XOR gate332and multiplexer334are omitted and the data on line322is not encoded by being sent directly to register336.

In one embodiment, each write access is posted at target104and is not acknowledged by target104. In another embodiment, some or all write accesses are acknowledged by the target logic304asserting the update signal on line324for a single cycle while providing a default data value on line322. The acknowledge of some or all write accesses can be used for flow control or ordering purposes. The request signal on line308can indicate the acceptance of read data by the controller module for a prior read access or the acceptance of the completion of a write by the controller module for a prior write access.

Referring toFIG. 4, a block diagram is shown of an example controller module102, according to the present invention. The controller module102includes a controller interface402used to interface controller logic404of the controller module102with the target modules (not shown).

The controller module102can have an access bus on line306that is coupled to all of the target modules. The controller module102can have a separate request signal on lines406,308, and408for each of the target modules. The respective request signal on lines406,308, and408is can be used to indicate the availability of an access request on the access bus on line306that is designated for the corresponding target module, and can be used to indicate the acceptance of the results of a prior access request from the corresponding target module. In another embodiment, there is only one request signal on line308, and the access bus on line306includes information identifying the target module, such as an address with the address space partitioned between the target modules, or a tag specifying the target module.

The exclusive-or function110performs the exclusive-or of all the acknowledge signals108from the target modules to produce the global acknowledge signal on line111. The controller module102has registers410and412to synchronize the global acknowledge signal on line111with the local clock of the controller module102. As with the illustration ofFIG. 3, the second register412is used only if the target module and controller module are in different clock domains; in an alternative embodiment, where the target is in the same domain as the controller, this second register412is bypassed.

Multiplexer414, register416, and XOR gate418produce an asserted value on line420after an acknowledge transition occurs on global acknowledge signal on line111due to an acknowledge transition on a line108from one of the target modules. The controller logic404, on observing an asserted value on line420, can subsequently sample decoded data on line422. The target module transfers the encoded data on line106together with the transition of the acknowledge signal on line108. Thus, the decoded data on line422has a stable value because the global data bus on line114has been stable for at least one local clock cycle of the controller module102whenever an asserted value is observed on line420by the controller logic404.

Changes of the value of a data bus106from a target module are propagated to corresponding changes in the value of the global data bus114by exclusive-or function112, and then captured by register424. Multiplexer426, register428, and XOR gate430decode a change in the value of the global data bus114into decoded data on line422that corresponds to the data that was encoded by the target module. After sampling the decoded data on line422, the controller logic404can assert the sample signal on line432for a single cycle of the local clock of controller module102.

The pulse of the sample signal on line432causes register416to be updated via multiplexer414with the current level of the global acknowledge signal on line111, such that XOR gate418de-asserts the value on line420until a subsequent transition of the global acknowledge signal on line111. The pulse of the sample signal on line432causes register428to be updated with the current value of register424reflecting the current value of the global data bus on line114. The updating of register428enables XOR gate430to convert subsequent transitions within the encoded value of the global data bus on line114into a decoded value on line422. During decoding, a bit with a transition is converted into a value of one, and a bit lacking of a transition is converted into a value of zero.

In another embodiment, the target modules do not encode data on the data bus on line106, and the controller module102maintains, for each target module, a register storing a copy of the current data value driven by the target module. Transitions observed on the global data bus on line114are used to update the value of the register corresponding to the particular target module. A bit with a transition observed on the global data bus on line114causes the corresponding bit in the register corresponding to the particular target module to be complemented. A bit without a transition observed on the global data bus on line114causes the corresponding bit in the register corresponding to the particular target module to remain unmodified.

Referring toFIG. 5, a flow diagram is shown of an example process500for data communication between a controller module and a plurality of target modules, according to the present invention. At step502, a controller module produces an access, such as a read access or a write access, which identifies a particular target module. The target module may be identified, for example, by an access address included in the access that corresponds to a particular target module via an address map, a tag included in the access that identifies a particular target module, or by asserting an individual strobe signal, such as a request signal, corresponding to a particular target module. For a read access the process500proceeds from decision504to step506, and for a write access the process500proceeds from decision504to step520.

At step506, the identified target obtains the data to satisfy the read access from a location associated with the read access. The data is encoded, at step508, by the identified target module with a parallel exclusive-or between the data and the previously encoded data for the identified target module. Target modules other than the identified target module do not modify their respective encoded data. At step510, an acknowledge signal for the identified target module is toggled to indicate the availability of the encoded data for the read access, while acknowledge signals for target modules other than the identified target module remain unmodified.

A global acknowledge signal is generated by an exclusive-or of the acknowledge signals from each of the target modules, at step512. At step514, the availability of the encoded data for the read access is determined from a toggling of the global acknowledge signal. A global data bus is generated by a parallel exclusive-or of a data bus from each of the target modules, at step516. At step518, the read data is decoded from the current and previous values of the global data bus by a parallel exclusive or between the current and previous values of the global data bus.

For a certain write access, a completion can be generated for the write access by the identified target module. At step520, the completion of the write access is indicated by toggling the acknowledge signal for the identified target module, while acknowledge signals for target modules other than the identified target module remain unmodified. A global acknowledge signal is generated by an exclusive-or of the acknowledge signals from each of the target modules, at step522. At step524, the completion of the write access is determined from a toggling of the global acknowledge signal.

It will be appreciated that these data communication arrangements and approaches are not limited to synchronous (clocked) designs, but are also applicable to fully asynchronous implementations as well. Such application is apparent when considering one or more of the above illustrated embodiments, for example, with use of fully asynchronous communication protocol in which no clocks are included on either the controller module or the target module. Such protocols are illustrated and described in AMULET3: A 100 MIPS Asynchronous Embedded Processor, Furber, S. B.; Edwards, D. A.; Garside, J. D.; Computer Design, 2000 International Conference on Sep. 17-20, 2000, pp. 329-334; and A Fully Asynchronous Digital Signal Processor Using Self-timed Circuits, Jacobs, G. M.; Brodersen, R. W., IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, December 1990, pp 1526-1537 incorporated herein by reference (also attached hereto as Appendix A and Appendix B).

Accordingly, various embodiments have been described by way of the figures and/or discussion as example implementations of the present invention involving data communication between a controller module and multiple target modules. The present invention should not be considered limited to these particular example implementations. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable fall within the scope of the present invention. For example, multi-chip or single-chip arrangements can be implemented using similarly constructed interfaces for communication between the chip-set arrangements. Such variations may be considered as part of the claimed invention, as fairly set forth in the appended claims.