Electronic component

An electronic component of the present disclosure includes a first insulating layer that includes impurities, a thin film resistor formed on the first insulating layer, and a barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities. The first insulating layer includes a first surface and a concave portion that is hollowed with respect to the first surface, and the barrier layer may include a first part embedded in the concave portion and a second part formed along the first surface of the first insulating layer from an upper area of the first part.

TECHNICAL FIELD

This disclosure relates to an electronic component.

BACKGROUND ART

Patent Literature 1 discloses an electric component that includes a first-layer metal wiring pattern formed on a first interlayer insulating film, a second interlayer insulating film with which the first-layer metal wiring pattern is covered, a CrSi thin film resistor formed on the second interlayer insulating film, and a first electroconductive plug that electrically connects the CrSi thin film resistor and the first-layer metal wiring pattern together.

CITATION LIST

Patent Literature

Patent Literature 1: Japanese Patent Application Publication No. 2005-235995

SUMMARY OF INVENTION

Solution to Problem

An electronic component according to a preferred embodiment of the present disclosure includes a first insulating layer that includes impurities, a thin film resistor formed on the first insulating layer, and a barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities.

An electronic component producing method according to a preferred embodiment of the present disclosure includes a step of forming a lower wiring layer by sputtering by use of an inert gas, a first step of forming a first insulating layer so as to cover the lower wiring layer, a second step of forming a barrier layer, which obstructs transmission of compositions of the inert gas included in the first insulating layer, on the first insulating layer, and a third step of forming a thin film resistor on the barrier layer so as to allow at least one part of the thin film resistor to overlap the barrier layer.

DESCRIPTION OF EMBODIMENTS

Preferred Embodiments of Present Disclosure

First Preferred Embodiment

FIG.1is a schematic plan view showing an electronic component1according to a first preferred embodiment of the present disclosure, and is a plan view showing a form in which a barrier layer17according to a first configuration example is incorporated.

The electronic component1is a semiconductor device including various functional devices that are made of conductor materials or semiconductor materials or that are formed by use of properties, etc., of semiconductor materials. The electronic component1includes a semiconductor layer2that is an example of a support substrate.

The semiconductor layer2is formed in a rectangular parallelepiped shape. The semiconductor layer2includes a first principal surface3on one side, a second principal surface4on the other side, and side surfaces5A,5B,5C, and5D that connect the first principal surface3and the second principal surface4together. The first principal surface3is a device forming surface. The first principal surface3and the second principal surface4are each formed in a quadrangular shape (in this embodiment, square shape) in a plan view seen from their normal directions (hereinafter, referred to simply as a “plan view”).

The semiconductor layer2may be a Si semiconductor layer including Si (silicon). The Si semiconductor layer may have a laminated structure including a Si semiconductor substrate and a Si epitaxial layer. The Si semiconductor layer may have a single layer structure consisting of a Si semiconductor substrate.

The semiconductor layer2may be a SiC semiconductor layer including SiC (silicon carbide). The SiC semiconductor layer may have a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer. The SiC semiconductor layer may have a single layer structure consisting of a SiC semiconductor substrate.

The semiconductor layer2may be a compound semiconductor layer including compound semiconductive materials. The compound semiconductor layer may have a laminated structure including a compound semiconductor substrate and a compound semiconductor epitaxial layer. The compound semiconductor layer may have a single layer structure consisting of a compound semiconductor substrate.

The compound semiconductive material may be a group III-V compound semiconductor material. The semiconductor layer2may include at least one among AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide) each of which is an example of the group III-V compound semiconductor material.

The semiconductor layer2includes a device region6and an outside region7. The device region6is a region in which a functional device is formed. The device region6is set at a distance from the side surfaces5A to5D of the semiconductor layer2toward an inward region. In this embodiment, the device region6is formed in the shape of the letter L in a plan view. The planar shape of the device region6is arbitrary, and is not limited to the planar shape shown inFIG.1.

The functional device is formed by use of the first principal surface3and/or a surface layer portion of the first principal surface3. The functional device may include at least one among a passive device, a semiconductor rectifier device, and a semiconductor switching device. The passive device may include a semiconductor passive device.

The passive device (semiconductor passive device) may include at least one among a resistor, a capacitor, and a coil. The semiconductor rectifier device may include at least one among a pn junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode.

The semiconductor switching device may include at least one among BJT (Bipolar Junction Transistor), MISFET (Metal Insulator Field Effect Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field Effect Transistor).

The functional device may include a circuit network in which at least two among a passive device (semiconductor passive device), a semiconductor rectifier device, and a semiconductor switching device are combined together. The circuit network may form a part or all of an integrated circuit. The integrated circuit may include SSI (Small Scale Integration), LSI (Large Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), or ULSI (Ultra-Very Large Scale Integration).

The outside region7is a region outside the device region6. The outside region7does not include a functional device. In this embodiment, the outside region7is demarcated in a region between the side surfaces5A to5D and the device region6. In this embodiment, the outside region7is formed in a quadrangular shape in a plan view. The disposition and the planar shape of the outside region7are arbitrary, and are not limited to those shown inFIG.1. The outside region7may be formed at a central portion of the first principal surface3in a plan view.

The electronic component1includes a resistance circuit10. A plurality of (two or more) resistance circuits10may be formed although an example in which one resistance circuit10is formed is described in this embodiment. The resistance circuit10is electrically connected to a functional device.

The resistance circuit10is formed in the outside region7. This makes it possible to suppress an electrical influence exerted by the resistance circuit10on the device region6, and makes it possible to suppress an electrical influence exerted by the device region6on the resistance circuit10.

As an example, the resistance circuit10is disposed in the outside region7, thus making it possible to suppress parasitic capacitance between the device region6and the resistance circuit10. In other words, it is possible to reduce noise by raising the Q value of an electronic circuit.

A structure of the resistance circuit10will be hereinafter described in detail.FIG.2is a cross-sectional view along line II-II shown inFIG.1.FIG.2is a cross-sectional view along line II-II shown inFIG.1.FIG.3is an enlarged view of region III shown inFIG.2.FIG.4is an enlarged view of region IV shown inFIG.2.

Referring toFIG.2toFIG.4, the electronic component1includes an insulating laminated structure12formed on the first principal surface3of the semiconductor layer2in the device region6and in the outside region7. The insulating laminated structure12has a laminated structure in which a plurality of (in this embodiment, four) insulating layer s are laminated.

In this embodiment, the insulating laminated structure12includes a first insulating layer13, a second insulating layer14, a third insulating layer15, a barrier layer17, and a fourth insulating layer16that are laminated in that order from the first principal surface3side of the semiconductor layer2.

The number of insulating layers laminated in the insulating laminated structure12is arbitrary, and is not limited to the number of the laminated layers shown inFIG.2. Therefore, the insulating laminated structure12may include insulating layers whose number is less than five, or may include insulating layers whose number is six or more.

The first to fourth insulating layers13to16and the barrier layer17each have a principal surface. The principal surfaces of the first to fourth insulating layers13to16and the principal surface of the barrier layer17are each formed so as to be flat. The principal surfaces of the first to fourth insulating layers13to16and the principal surface of the barrier layer17each extend in parallel with the first principal surface3of the semiconductor layer2. The principal surfaces of the first to fourth insulating layers13to16and the principal surface of the barrier layer17may be each a ground surface. In other words, the principal surfaces of the first to fourth insulating layers13to16and the principal surface of the barrier layer17may each have grinding marks.

The first to fourth insulating layers13to16and the barrier layer17may each have a laminated structure including a silicon oxide film and a silicon nitride film. In this case, the silicon nitride film may be formed on the silicon oxide film, and the silicon oxide film may be formed on the silicon nitride film.

The first to fourth insulating layers13to16and the barrier layer17may each have a single layer structure including a silicon oxide film or a silicon nitride film. Preferably, the first to fourth insulating layers13to16and the barrier layer17are made of the same kind of insulating material. In this embodiment, the first to fourth insulating layers13to16and the barrier layer17each have a single layer structure consisting of a silicon oxide film.

The third insulating layer15includes a silicon oxide film formed by, for example, HDP-CDV (High Density Plasma Chemical Vapor Deposition). The third insulating layer15may include an impurity. The impurity is an inert gas composition that is used in sputter etching of, for example, a metal thin film or a silicon oxide film, etc. The impurity is, for example, Ar, etc.

The barrier layer17includes a silicon oxide film (TEOS film) formed by, for example, P-CDV (Plasma Chemical Vapor Deposition). The barrier layer17obstructs the transmission of an impurity included in the third insulating layer15. From the viewpoint of being made of an insulating material, the barrier layer17may be referred to as an “insulating barrier layer,” or may be referred to simply as a “fifth insulating layer” in distinction from the first to fourth insulating layers13to16. Additionally, the barrier layer17may be referred to as a thin film resistor support layer, a thin film resistor support insulating layer, or the like because the barrier layer17is a layer that supports a thin film resistor35as described later.

The thicknesses TI of the first to fourth insulating layers13to16and the thickness TI of the barrier layer17may be each not less than 100 nm and not more than 3500 nm. The thickness TI may be not less than 100 nm and not more than 500 nm, not less than 500 nm and not more than 1000 nm, not less than 1000 nm and not more than 1500 nm, not less than 1500 nm and not more than 2000 nm, not less than 2000 nm and not more than 2500 nm, not less than 2500 nm and not more than 3000 nm, or not less than 3000 nm and not more than 3500 nm. Preferably, the thickness TI is not less than 100 nm and not more than 1500 nm. The thicknesses TI of the first to fourth insulating layers13to16and the thickness TI of the barrier layer17may be equal to each other or may differ from each other.

The insulating laminated structure12includes a plurality of wirings formed in the first to fourth insulating layers13to16and in the barrier layer17. As a result, a multilayer wiring structure is formed. More specifically, the insulating laminated structure12includes a wiring circuit forming layer21and a resistance circuit forming layer22.

The wiring circuit forming layer21includes the first insulating layer13and the second insulating layer14. Additionally, the wiring circuit forming layer21includes a wiring circuit formed in the first insulating layer13and in the second insulating layer14. The wiring circuit of the wiring circuit forming layer21is routed from the device region6to the outside region7. A detailed structure of the wiring circuit forming layer21is described later.

The resistance circuit forming layer22is formed on the wiring circuit forming layer21. The resistance circuit forming layer22includes the third insulating layer15and the fourth insulating layer16. Additionally, the resistance circuit forming layer22includes the resistance circuit10formed in the third insulating layer15and in the fourth insulating layer16. The resistance circuit10is electrically connected to the device region6(functional device) through the wiring circuit of the wiring circuit forming layer21.

For example, the resistance circuit10includes a thin film resistor35, a first via electrode23and a second via electrode24, a first lower wiring layer41and a second lower wiring layer42, a first long via electrode83and a second long via electrode84, and a first upper wiring layer61and a second upper wiring layer62as shown inFIG.1andFIG.2. These will be hereinafter described in detail.

Referring toFIG.1toFIG.3, the resistance circuit10includes the first via electrode23and the second via electrode24. The first via electrode23is embedded in the third insulating layer15and in the barrier layer17, and is exposed from the principal surface of the barrier layer17. The second via electrode24is embedded in the third insulating layer15and in the barrier layer17at a distance from the first via electrode23, and is exposed from the principal surface of the barrier layer17.

In this embodiment, the first via electrode23is formed in a circular shape in a plan view. The planar shape of the first via electrode23is arbitrary. The first via electrode23may be formed in a polygonal shape, such as a triangular shape, a quadrangular shape, or a hexagonal shape, or may be formed in an elliptical shape in a plan view.

The first via electrode23includes a first end portion23aon one side and a second end portion23bon the other side with respect to the normal direction of the principal surface of the barrier layer17. The first end portion23ais exposed from the principal surface of the barrier layer17. The second end portion23bis placed inside the third insulating layer15. The first via electrode23is formed in a tapered shape in which its width becomes smaller from the first end portion23atoward the second end portion23bin a cross-sectional view.

In this embodiment, the first end portion23aincludes a first projecting portion23cthat projects from the principal surface of the barrier layer17toward the fourth insulating layer16. The first projecting portion23cis formed by the principal surface and the side surface of the first via electrode23.

The first via electrode23has a laminated structure including a main body layer25and a barrier layer26. The main body layer25is embedded in the third insulating layer15and in the barrier layer17. The main body layer25may include tungsten (W) or copper (Cu). In this embodiment, the main body layer25has a single layer structure consisting of a tungsten layer27.

The barrier layer26is interposed between the third insulating layer15and the main body layer25. In this embodiment, the barrier layer26has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer26includes a Ti layer28and a TiN layer29formed in that order from the third insulating layer15. The Ti layer28is in contact with the third insulating layer15. The TiN layer29is in contact with the main body layer25. The barrier layer26may have a single layer structure consisting of the Ti layer28or the TiN layer29.

In this embodiment, the second via electrode24is formed in a circular shape in a plan view. The planar shape of the second via electrode24is arbitrary. The second via electrode24may be formed in a polygonal shape, such as a triangular shape, a quadrangular shape, or a hexagonal shape, or may be formed in an elliptical shape in a plan view.

The second via electrode24includes a first end portion24aon one side and a second end portion24bon the other side with respect to the normal direction of the principal surface of the barrier layer17. The first end portion24ais exposed from the principal surface of the barrier layer17. The second end portion24bis placed inside the third insulating layer15. The second via electrode24is formed in a tapered shape in which its width becomes smaller from the first end portion24atoward the second end portion24bin a cross-sectional view.

In this embodiment, the first end portion24aincludes a second projecting portion24cthat projects from the principal surface of the barrier layer17toward the fourth insulating layer16. The second projecting portion24cis formed by the principal surface and the side surface of the second via electrode24.

The second via electrode24has a laminated structure including a main body layer30and a barrier layer31. The main body layer30is embedded in the third insulating layer15and in the barrier layer17. The main body layer30may include tungsten (W) or copper (Cu). In this embodiment, the main body layer30has a single layer structure consisting of a tungsten layer32.

The barrier layer31is interposed between the third insulating layer15and the main body layer30. In this embodiment, the barrier layer31has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer31includes a Ti layer33and a TiN layer34formed in that order from the third insulating layer15. The Ti layer33is in contact with the third insulating layer15. The TiN layer34is in contact with the main body layer30. The barrier layer31may have a single layer structure consisting of the Ti layer33or the TiN layer34.

Referring toFIG.2toFIG.4, the resistance circuit10includes a thin film resistor35formed inside the insulating laminated structure12. The thin film resistor35is formed at the resistance circuit forming layer22. In other words, the thin film resistor35is formed on the first principal surface3. More specifically, the thin film resistor35is formed at a distance from the first principal surface3in the lamination direction of the insulating laminated structure12.

The thin film resistor35is formed in the outside region7. This makes it possible to suppress an electrical influence exerted by the thin film resistor35on the device region6, and makes it possible to suppress an electrical influence exerted by the device region6on the thin film resistor35. As an example, it is possible to suppress parasitic capacitance between the device region6and the thin film resistor35. In other words, it is possible to reduce noise by raising the Q value of an electronic circuit.

More specifically, the thin film resistor35is interposed in a region between the barrier layer17and the fourth insulating layer16. The thin film resistor35is formed in a film shape on the principal surface of the barrier layer17. The thin film resistor35occupies the principal surface of the barrier layer17. A film-shaped or layer-shaped wiring excluding the thin film resistor35is not formed on the principal surface of the barrier layer17in the device region6and in the outside region7.

Referring toFIG.2, the barrier layer17overlaps the entirety of the thin film resistor35. In this case, the barrier layer17may cover the entirety of the third insulating layer15. The barrier layer17is merely required to be interposed in at least one part of a region between the thin film resistor35and the third insulating layer15. Therefore, the barrier layer17may be configured to overlap only a part of the thin film resistor35. The barrier layer17obstructs the transmission of impurities, and therefore the thin film resistor35becomes insusceptible to impurities by interposing the barrier layer17between the thin film resistor35and the third insulating layer15.

FIG.5is a plan view showing the thin film resistor35.FIG.6is a cross-sectional view along line VI-VI shown inFIG.5. Referring toFIG.5andFIG.6, the thin film resistor35is formed so as to straddle the first via electrode23and the second via electrode24. Hence, the thin film resistor35is electrically connected to the first via electrode23and to the second via electrode24. In this embodiment, the thin film resistor35is formed in a quadrangular shape (in more detail, a rectangular shape) in a plan view. The planar shape of the thin film resistor35is arbitrary, and is not limited to the quadrangular shape.

The thin film resistor35includes a first end portion35aon one side, a second end portion35bon the other side, and a connection portion35cthat connects the first and second end portions35aand35btogether. The first end portion35acovers the first via electrode23. More specifically, the first end portion35acovers the first end portion23a(first projecting portion23c) of the first via electrode23. The first end portion35ais formed in a film shape along the principal surface and the side surface of the first via electrode23.

The second end portion35bcovers the second via electrode24. More specifically, the second end portion35bcovers the first end portion24a(second projecting portion24c) of the second via electrode24. The second end portion35bis formed in a film shape along the principal surface and the side surface of the second via electrode24.

The connection portion35cextends in a belt shape in a region between the first end portion35aand the second end portion35b. In this embodiment, the connection portion35cextends in a belt shape along a straight line that connects the first end portion35aand the second end portion35btogether. In this embodiment, the first end portion35a, the second end portion35b, and the connection portion35care each formed with a uniform width.

The thin film resistor35includes chromium silicide. In this embodiment, the thin film resistor35includes crystallized chromium silicide. The thin film resistor35is a so-called metal silicide thin film resistor. With the thin film resistor35that is a metal silicide thin film resistor, it is possible to appropriately realize film thinning and plane-area reduction unlike conductive polysilicon, etc.

This makes it possible to appropriately interpose the thin film resistor35in a region between the barrier layer17and the fourth insulating layer16while securing flatness. Additionally, it is possible to appropriately reduce the plane area of the thin film resistor35, and therefore it is possible to relax a design rule. This makes it possible to appropriately dispose the thin film resistor35in the outside region7. Therefore, it is possible to appropriately suppress an electrical impact between the thin film resistor35and the device region6.

The thin film resistor35may include at least one among CrSi, CrSi2, CrSiN, and CrSiO as an example of chromium silicide. CrSiN is also chromium nitride. CrSiO is also chromium oxide. In this embodiment, the thin film resistor35is made of CrSi.

The thin film resistor35has a thickness TR of 1 μm or less. Preferably, the thickness TR is equal to or less than 500 nm. More preferably, the thickness TR is not less than 0.1 nm and not more than 100 nm. The thickness TR may be not less than 0.1 nm and not more than 5 nm, not less than 5 nm and not more than 10 nm, not less than 10 nm and not more than 20 nm, not less than 20 nm and not more than 40 nm, not less than 40 nm and not more than 60 nm, not less than 60 nm and not more than 80 nm, or not less than 80 nm and not more than 100 nm. Most preferably, the thickness TR is not less than 1 nm and not more than 5 nm.

A sheet resistance value RT of the thin film resistor35may be not less than 100Ω/□ and not more than 50000Ω/□. The sheet resistance value RT may be not less than 100Ω/□ and not more than 5000Ω/□, not less than 5000Ω/□ and not more than 10000Ω/□, not less than 10000Ω/□ and not more than 15000Ω/□, not less than 15000Ω/□ and not more than 20000Ω/□, not less than 20000Ω/□ and not more than 25000Ω/□, not less than 25000Ω/□ and not more than 30000Ω/□, not less than 30000Ω/□ and not more than 35000Ω/□, not less than 35000Ω/□ and not more than 40000Ω/□, not less than 40000Ω/□ and not more than 45000Ω/□, or not less than 45000Ω/□ and not more than 50000 Ω/□.

The chromium content with respect to the overall weight of the thin film resistor35may be not less than 5% by weight and not more than 50% by weight. The Cr content may be not less than 5% by weight and not more than 10% by weight, not less than 10% by weight and not more than 20% by weight, not less than 20% by weight and not more than 30% by weight, not less than 30% by weight and not more than 40% by weight, or not less than 40% by weight and not more than 50% by weight.

Referring toFIG.5, the thin film resistor35includes a trimming mark38. The trimming mark38is shown by dot hatching inFIG.5andFIG.6.

The trimming mark38is a region in which a part of the thin film resistor35(chromium silicide) has been eliminated. More specifically, the trimming mark38is a laser processing mark in which a part of the thin film resistor35(chromium silicide) has been eliminated by a laser irradiation method.

In this embodiment, the trimming mark38is formed at the connection portion35cof the thin film resistor35. The trimming mark38may be formed at either one or both of the first end portion35aand the second end portion35b.

The trimming mark38extends in a direction intersecting a direction in which the thin film resistor35extends. In this embodiment, the trimming mark38extends in a direction perpendicular to the direction in which the thin film resistor35extends. The trimming mark38may extend in the direction in which the thin film resistor35extends.

Referring again toFIG.2toFIG.4, the resistance circuit10includes a protective layer40covering the thin film resistor35. The protective layer40is interposed in a region between the barrier layer17and the fourth insulating layer16, and covers the thin film resistor35. More specifically, the protective layer40is formed in a film shape along a surface of the thin film resistor35. The protective layer40additionally covers the trimming mark38.

The protective layer40has a planar shape matching the planar shape of the thin film resistor35. The protective layer40may have a side surface continuous with a side surface of the thin film resistor35. The side surface of the protective layer40may be formed so as to be flush with the side surface of the thin film resistor35.

The protective layer40may have a laminated structure including a silicon oxide layer and a silicon nitride layer. In this case, the silicon nitride layer may be formed on the silicon oxide layer, or the silicon oxide layer may be formed on the silicon nitride layer. The protective layer40may have a single layer structure consisting of a silicon oxide layer or a silicon nitride layer. In this embodiment, the protective layer40has a single layer structure consisting of a silicon oxide layer.

The thickness of the protective layer40may be not less than 1 nm and not more than 5 μm. The thickness of the protective layer40may be not less than 1 nm and not more than 10 nm, not less than 10 nm and not more than 50 nm, not less than 50 nm and not more than 100 nm, not less than 100 nm and not more than 200 nm, not less than 200 nm and not more than 400 nm, not less than 400 nm and not more than 600 nm, not less than 600 nm and not more than 800 nm, or not less than 800 nm and not more than 1 μm.

The thickness of the protective layer40may be not less than 1 μm and not more than 1.5 μm, not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, not less than 2.5 μm and not more than 3 μm, not less than 3 μm and not more than 3.5 μm, not less than 3.5 μm and not more than 4 μm, not less than 4 μm and not more than 4.5 μm, or not less than 4.5 μm and not more than 5 μm.

Preferably, the thickness of the protective layer40is equal to or more than the thickness TR of the thin film resistor35. With the protective layer40having a thickness equal to or more than the thickness TR of the thin film resistor35, it is possible to appropriately bury a bulge formed at the thin film resistor35.

The resistance circuit10includes the first lower wiring layer41and the second lower wiring layer42. The first lower wiring layer41is formed inside the third insulating layer15. More specifically, the first lower wiring layer41is formed on the wiring circuit forming layer21(second insulating layer14), and is covered with the third insulating layer15. The first lower wiring layer41is electrically connected to the thin film resistor35through the first via electrode23.

The second lower wiring layer42is formed inside the third insulating layer15. More specifically, the second lower wiring layer42is formed on the wiring circuit forming layer21(second insulating layer14), and is covered with the third insulating layer15. The second lower wiring layer42is formed at a distance from the first lower wiring layer41. The second lower wiring layer42is electrically connected to the thin film resistor35through the second via electrode24.

Hence, the thin film resistor35is connected in series with the first lower wiring layer41and with the second lower wiring layer42. The thin film resistor35is formed on a line that connects the first lower wiring layer41and the second lower wiring layer42together in a plan view. In this embodiment, the thin film resistor35linearly extends in a region between the first lower wiring layer41and the second lower wiring layer42in a plan view.

The first lower wiring layer41and the second lower wiring layer42each have a first thickness TL1. The first thickness TL1may be not less than 100 nm and not more than 3000 nm. The first thickness TL1of each of the first and second lower wiring layers41and42may be not less than 100 nm and not more than 500 nm, not less than 500 nm and not more than 1000 nm, not less than 1000 nm and not more than 1500 nm, not less than 1500 nm and not more than 2000 nm, not less than 2000 nm and not more than 2500 nm, or not less than 2500 nm and not more than 3000 nm.

Preferably, the first thickness TL1is not less than 100 nm and not more than 1500 nm. The first thickness TL1of the first lower wiring layer41and the first thickness TL1of the second lower wiring layer42may differ from each other. Preferably, the first thickness TL1of the first lower wiring layer41and the first thickness TL1of the second lower wiring layer42is equal to each other.

Referring toFIG.1andFIG.3, the first lower wiring layer41includes a first end portion41aon one side, a second end portion41bon the other side, and a connection portion41cthat connects the first end portion41aand the second end portion41btogether. The first end portion41aoverlaps the first end portion35aof the thin film resistor35in a plan view. The first end portion41ais electrically connected to the first end portion35aof the thin film resistor35through the first via electrode23.

The second end portion41bis placed in a region outside the thin film resistor35in a plan view. In this embodiment, the second end portion41bis placed in the outside region7. The connection portion41cextends in a belt shape in a region between the first end portion41aand the second end portion41bin a plan view. In this embodiment, the connection portion41cextends in a belt shape along a straight line that connects the first end portion41aand the second end portion41btogether.

In this embodiment, the first lower wiring layer41has a laminated structure in which a plurality of electrode layers are laminated. The first lower wiring layer41includes a first barrier layer43, a main body layer44, and a second barrier layer45that are laminated in that order from the top of the wiring circuit forming layer21(second insulating layer14).

In this embodiment, the first barrier layer43has a laminated structure including a Ti layer46and a TiN layer47that are laminated in that order from the top of the wiring circuit forming layer21(second insulating layer14). The first barrier layer43may have a single layer structure consisting of the Ti layer46or the TiN layer47.

The main body layer44has a resistance value less than the resistance value of the first barrier layer43and the resistance value of the second barrier layer45. The main body layer44has a thickness exceeding the thickness of the first barrier layer43and the thickness of the second barrier layer45. The main body layer44may include at least one among Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer44has a single layer structure consisting of an AlCu alloy layer48.

In this embodiment, the second barrier layer45has a laminated structure including a Ti layer49and a TiN layer50that are laminated in that order from the top of the main body layer44. The second barrier layer45may have a single layer structure consisting of the Ti layer49or the TiN layer50.

Referring toFIG.4, the second lower wiring layer42includes a first end portion42aon one side, a second end portion42bon the other side, and a connection portion42cthat connects the first end portion42aand the second end portion42btogether. The first end portion42aoverlaps the second end portion35bof the thin film resistor35in a plan view. The first end portion42ais electrically connected to the second end portion35bof the thin film resistor35through the second via electrode24.

The second end portion42bis placed in a region outside the thin film resistor35in a plan view. In this embodiment, the second end portion42bis placed in the outside region7. The connection portion42cextends in a belt shape in a region between the first end portion42aand the second end portion42bin a plan view. In this embodiment, the connection portion42cextends in a belt shape along a straight line that connects the first end portion42aand the second end portion42btogether.

In this embodiment, the second lower wiring layer42has a laminated structure in which a plurality of electrode layers are laminated. The second lower wiring layer42includes a first barrier layer53, a main body layer54, and a second barrier layer55that are laminated in that order from the top of the wiring circuit forming layer21(second insulating layer14).

In this embodiment, the first barrier layer53has a laminated structure including a Ti layer56and a TiN layer57that are laminated in that order from the top of the wiring circuit forming layer21(second insulating layer14). The first barrier layer53may have a single layer structure consisting of the Ti layer56or the TiN layer57.

The main body layer54has a resistance value less than the resistance value of the first barrier layer53and the resistance value of the second barrier layer55. The main body layer54has a thickness exceeding the thickness of the first barrier layer53and the thickness of the second barrier layer55. The main body layer54may include at least one among Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer54has a single layer structure consisting of an AlCu alloy layer58.

In this embodiment, the second barrier layer55has a laminated structure including a Ti layer59and a TiN layer60that are laminated in that order from the top of the main body layer54. The second barrier layer55may have a single layer structure consisting of the Ti layer59or the TiN layer60.

Referring toFIG.2toFIG.4, the third insulating layer15has a stepped surface on which the shape of the first lower wiring layer41and the shape of the second lower wiring layer42are reflected. In other words, the third insulating layer15has a first surface15aserving as a principal surface and a concave portion15bthat is hollowed from the first surface15ain a region15cbetween the first lower wiring layer41and the second lower wiring layer42. The barrier layer17may have a first part17aembedded in the concave portion15band a second part17bformed along the first surface15aof the third insulating layer15from an upper area of the first part17a. In other words, the barrier layer17is thicker than surroundings in the region15cbetween the first lower wiring layer41and the second lower wiring layer42.

The concave portion15bhas a bottom surface15dand an inclined surface15ethat connects the bottom surface15dand the first surface15atogether. The bottom surface15dis formed at a position higher than an upper surface of the first lower wiring layer41and than an upper surface of the second lower wiring layer42. Referring toFIG.3, the concave portion15bmay partially overlap the first end portion41aof the first lower wiring layer41. Additionally, referring toFIG.4, the concave portion15bmay partially overlap the first end portion42aof the second lower wiring layer42.

The resistance circuit10includes the first upper wiring layer61and the second upper wiring layer62. The first upper wiring layer61is formed on the fourth insulating layer16. The first upper wiring layer61forms one of the uppermost wiring layers of the insulating laminated structure12. The first upper wiring layer61is electrically connected to the first lower wiring layer41.

The second upper wiring layer62is formed on the fourth insulating layer16at a distance from the first upper wiring layer61. The second upper wiring layer62forms one of the uppermost wiring layers of the insulating laminated structure12. The second upper wiring layer62is electrically connected to the second lower wiring layer42.

Hence, the thin film resistor35is electrically connected to the first upper wiring layer61through the first lower wiring layer41. Additionally, the thin film resistor35is electrically connected to the second upper wiring layer62through the second lower wiring layer42. The thin film resistor35is connected in series with the first upper wiring layer61and with the second upper wiring layer62through the first lower wiring layer41and through the second lower wiring layer42.

Referring toFIG.1, the first upper wiring layer61is formed at a distance from the thin film resistor35in a plan view. The first upper wiring layer61does not overlap the thin film resistor35in a plan view. The entirety of the thin film resistor35is exposed from the first upper wiring layer61in a plan view.

The second upper wiring layer62is formed at a distance from the thin film resistor35in a plan view. The second upper wiring layer62does not overlap the thin film resistor35in a plan view. The entirety of the thin film resistor35is exposed from the second upper wiring layer62in a plan view.

In other words, the thin film resistor35is formed in a region between the first upper wiring layer61and the second upper wiring layer62in a plan view. Hence, it is possible to suppress parasitic capacitance in a region between the thin film resistor35and the first upper wiring layer61. Additionally, it is possible to suppress parasitic capacitance in a region between the thin film resistor35and the second upper wiring layer62.

In this embodiment, the thin film resistor35is formed at a distance from the first upper wiring layer61and from the second upper wiring layer62in a plan view. Hence, it is possible to appropriately suppress parasitic capacitance in the region between the thin film resistor35and the first upper wiring layer61.

The first upper wiring layer61and the second upper wiring layer62each have a second thickness TL2. The second thickness TL2is equal to or more than a first thickness TL1(TL1≤TL2). More specifically, the second thickness TL2exceeds the first thickness TL1(TL1<TL2).

The second thickness TL2may be not less than 100 nm and not more than 15000 nm. The second thickness TL2may be not less than 100 nm and not more than 1500 nm, not less than 1500 nm and not more than 3000 nm, not less than 3000 nm and not more than 4500 nm, not less than 4500 nm and not more than 6000 nm, not less than 6000 nm and not more than 7500 nm, not less than 7500 nm and not more than 9000 nm, not less than 9000 nm and not more than 10500 nm, not less than 10500 nm and not more than 12000 nm, not less than 12000 nm and not more than 13500 nm, or not less than 13500 nm and not more than 15000 nm.

The second thickness TL2of the first upper wiring layer61and the second thickness TL2of the second upper wiring layer62may differ from each other. Preferably, the second thickness TL2of the first upper wiring layer61and the second thickness TL2of the second upper wiring layer62are equal to each other.

Referring toFIG.1andFIG.3, the first upper wiring layer61includes a first end portion61aon one side, a second end portion61bon the other side, and a connection portion61cthat connects the first end portion61aand the second end portion61btogether. The first end portion61ais placed in a region in which the first end portion61aoverlaps the first end portion41aof the first lower wiring layer41in a plan view.

The second end portion61bis placed in a region outside the thin film resistor35in a plan view. In this embodiment, the second end portion61bis placed in the device region6in a plan view. The second end portion61bmay be placed in the outside region7. The connection portion61cextends in a belt shape in a region between the first end portion61aand the second end portion61bin a plan view. In this embodiment, the connection portion61cextends in a belt shape along a straight line that connects the first end portion61aand the second end portion61btogether.

In this embodiment, the first upper wiring layer61has a laminated structure in which a plurality of electrode layers are laminated. The first upper wiring layer61includes a first barrier layer63, a main body layer64, and a second barrier layer65that are laminated in that order from the top of the resistance circuit forming layer22(fourth insulating layer16).

In this embodiment, the first barrier layer63has a laminated structure including a Ti layer66and a TiN layer67that are laminated in that order from the top of the resistance circuit forming layer22(fourth insulating layer16). The first barrier layer63may have a single layer structure consisting of the Ti layer66or the TiN layer67.

The main body layer64has a resistance value less than the resistance value of the first barrier layer63and the resistance value of the second barrier layer65. The main body layer64has a thickness exceeding the thickness of the first barrier layer63and the thickness of the second barrier layer65. The main body layer64may include at least one among Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer64has a single layer structure consisting of an AlCu alloy layer68.

In this embodiment, the second barrier layer65has a laminated structure including a Ti layer69and a TiN layer70that are laminated in that order from the top of the main body layer64. The second barrier layer65may have a single layer structure consisting of the Ti layer69or the TiN layer70.

Referring toFIG.1andFIG.4, the second upper wiring layer62includes a first end portion62aon one side, a second end portion62bon the other side, and a connection portion62cthat connects the first end portion62aand the second end portion62btogether. The first end portion62ais placed in a region in which the first end portion62aoverlaps the second end portion42bof the second lower wiring layer42in a plan view.

The second end portion62bis placed in a region outside the thin film resistor35in a plan view. In this embodiment, the second end portion62bis placed in the device region6in a plan view. The second end portion62bmay be placed in the outside region7in a plan view. The connection portion62cextends in a belt shape in a region between the first end portion62aand the second end portion62bin a plan view. In this embodiment, the connection portion62cextends in a belt shape along a straight line that connects the first end portion62aand the second end portion62btogether.

On the other hand, in this embodiment, the second upper wiring layer62has a laminated structure in which a plurality of electrode layers are laminated. The second upper wiring layer62includes a first barrier layer73, a main body layer74, and a second barrier layer75that are laminated in that order from the top of the resistance circuit forming layer22(fourth insulating layer16).

In this embodiment, the first barrier layer73has a laminated structure including a Ti layer76and a TiN layer77that are laminated in that order from the top of the resistance circuit forming layer22(fourth insulating layer16). The first barrier layer73may have a single layer structure consisting of the Ti layer76or the TiN layer77.

The main body layer74has a resistance value less than the resistance value of the first barrier layer73and the resistance value of the second barrier layer75. The main body layer74has a thickness exceeding the thickness of the first barrier layer73and the thickness of the second barrier layer75. The main body layer74may include at least one among Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer74has a single layer structure consisting of an AlCu alloy layer78.

In this embodiment, the second barrier layer75has a laminated structure including a Ti layer79and a TiN layer80that are laminated in that order from the top of the main body layer74. The second barrier layer75may have a single layer structure consisting of the Ti layer79or the TiN layer80.

Referring toFIG.1toFIG.4, the resistance circuit10includes a first long via electrode83and a second long via electrode84. The first long via electrode83is electrically connected to the first lower wiring layer41and to the first upper wiring layer61. The second long via electrode84is electrically connected to the second lower wiring layer42and to the second upper wiring layer62.

Hence, the thin film resistor35is electrically connected to the first upper wiring layer61through the first via electrode23, the first lower wiring layer41, and the first long via electrode83. Alternatively, the thin film resistor35is electrically connected to the second upper wiring layer62through the second via electrode24, the second lower wiring layer42, and the second long via electrode84.

The first long via electrode83is formed beside the thin film resistor35. In this embodiment, the first long via electrode83is placed on a straight line that connects the first via electrode23and the second via electrode24together.

The second long via electrode84is formed beside the thin film resistor35at a distance from the first long via electrode83. In this embodiment, the second long via electrode84faces the first long via electrode83with the thin film resistor35between the second long via electrode84and the first long via electrode83. The second long via electrode84is placed on the straight line that connects the first via electrode23and the second via electrode24together.

Hence, the thin film resistor35is placed on a straight line that connects the first long via electrode83and the second long via electrode84together. The thin film resistor35is placed on the straight line that connects the first via electrode23, the second via electrode24, the first long via electrode83, and the second long via electrode84together. In this embodiment, the thin film resistor35extends along the straight line that connects the first long via electrode83and the second long via electrode84together.

In this embodiment, the first long via electrode83is formed in a circular shape in a plan view. The planar shape of the first long via electrode83is arbitrary. The first long via electrode83may be formed in a polygonal shape, such as a triangular shape, a quadrangular shape, or a hexagonal shape, or may be formed in an elliptical shape in a plan view.

The first long via electrode83crosses the thin film resistor35in the normal direction of the principal surface of the third insulating layer15in a lateral view. The first long via electrode83passes through the third insulating layer15, the barrier layer17, and the fourth insulating layer16, and is embedded in these layers, i.e., is embedded in the third insulating layer15, the barrier layer17, and the fourth insulating layer16. The first long via electrode83is exposed from the principal surface of the fourth insulating layer16.

The first long via electrode83includes a first end portion83aon one side and a second end portion83bon the other side with respect to the normal direction of the principal surface of the third insulating layer15. The first end portion83ais exposed from the principal surface of the fourth insulating layer16. The first end portion83ais electrically connected to the first end portion61aof the first upper wiring layer61.

The second end portion83bis placed inside the third insulating layer15. The second end portion83bis electrically connected to the second end portion41bof the first lower wiring layer41. The first long via electrode83is formed in a tapered shape in which its width becomes smaller from the first end portion83atoward the second end portion83bin a cross-sectional view.

The first long via electrode83has a lower part83cplaced on the third insulating layer15side with respect to the thin film resistor35and an upper part83dplaced on the fourth insulating layer16side with respect to the thin film resistor35. The length of the upper part83dis equal to or more than the length of the lower part83cwith respect to the normal direction of the principal surface of the third insulating layer15. More specifically, the length of the upper part83dexceeds the length of the lower part83c.

The first long via electrode83has a laminated structure including a main body layer85and a barrier layer86. The main body layer85is embedded in the third insulating layer15and in the fourth insulating layer16. The main body layer85may include tungsten (W) or copper (Cu). In this embodiment, the first long via electrode83has a single layer structure consisting of a tungsten layer87.

The barrier layer86is interposed between the main body layer85and the third insulating layer15and between the main body layer85and the fourth insulating layer16. In this embodiment, the barrier layer86has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer86includes a Ti layer88and a TiN layer89that are formed in that order from the third insulating layer15.

The Ti layer88is in contact with the third insulating layer15and with the fourth insulating layer16. The TiN layer89is in contact with the main body layer85. The barrier layer86may have a single layer structure consisting of the Ti layer88or the TiN layer89.

In this embodiment, the second long via electrode84is formed in a circular shape in a plan view. The planar shape of the second long via electrode84is arbitrary. The second long via electrode84may be formed in a polygonal shape, such as a triangular shape, a quadrangular shape, or a hexagonal shape, or may be formed in an elliptical shape in a plan view.

On the other hand, the second long via electrode84crosses the thin film resistor35in the normal direction of the principal surface of the third insulating layer15in a lateral view. The second long via electrode84passes through the third insulating layer15, the barrier layer17, and the fourth insulating layer16, and is embedded in these layers, i.e., is embedded in the third insulating layer15, the barrier layer17, and the fourth insulating layer16. The second long via electrode84is exposed from the principal surface of the fourth insulating layer16.

The second long via electrode84includes a first end portion84aon one side and a second end portion84bon the other side with respect to the normal direction of the principal surface of the third insulating layer15. The first end portion84ais exposed from the principal surface of the fourth insulating layer16. The first end portion84ais electrically connected to the first end portion62aof the second upper wiring layer62.

The second end portion84bis placed inside the third insulating layer15. The second end portion84bis electrically connected to the second end portion42bof the second lower wiring layer42. The second long via electrode84is formed in a tapered shape in which its width becomes smaller from the first end portion84atoward the second end portion84bin a cross-sectional view.

The second long via electrode84has a lower part84cplaced on the third insulating layer15side with respect to the thin film resistor35and an upper part84dplaced on the fourth insulating layer16side with respect to the thin film resistor35. The length of the upper part84dis equal to or more than the length of the lower part84cwith respect to the normal direction of the principal surface of the third insulating layer15. More specifically, the length of the upper part84dexceeds the length of the lower part84c.

The second long via electrode84has a laminated structure including a main body layer90and a barrier layer91. The main body layer90is embedded in the third insulating layer15and in the fourth insulating layer16. The main body layer90may include tungsten (W) or copper (Cu). In this embodiment, the second long via electrode84has a single layer structure consisting of a tungsten layer92.

The barrier layer91is interposed between the main body layer90and the third insulating layer15and between the main body layer90and the fourth insulating layer16. In this embodiment, the barrier layer91has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer91includes a Ti layer93and a TiN layer94that are formed in that order from the third insulating layer15.

The Ti layer93is in contact with the third insulating layer15and with the fourth insulating layer16. The TiN layer94is in contact with the main body layer90. The barrier layer91may have a single layer structure consisting of the Ti layer93or the TiN layer94.

Referring toFIG.2, the wiring circuit forming layer21includes a wiring95that electrically connects a functional device and the thin film resistor35together. The wiring95is selectively formed inside the first insulating layer13and inside the second insulating layer14, and is routed from the device region6to the outside region7.

More specifically, the wiring95includes a single or a plurality of connection wiring layers96that is or are electrically connected to the functional device in the device region6. The single or the plurality of connection wiring layers96is or are formed either on the first insulating layer13or on the second insulating layer14, or alternatively, both on the first insulating layer13and on the second insulating layer14. InFIG.2, an example is shown in which two connection wiring layers96are formed on the first insulating layer13.

The single or the plurality of connection wiring layers96is or are selectively routed from the device region6to the outside region7. The connection wiring layer96has the same laminated structure as the first lower wiring layer41(second lower wiring layer42) and as the first upper wiring layer61(second upper wiring layer62). A detailed description of the connection wiring layer96is omitted.

The wiring95includes a single or a plurality of connection via electrodes97. The single or the plurality of connection via electrodes97connect(s) the single or the plurality of connection wiring layers96to an arbitrary first lower wiring layer41(second lower wiring layer42) or to an arbitrary first upper wiring layer61(second upper wiring layer62).

The single or the plurality of connection via electrodes97is or are formed either on the first insulating layer13or on the second insulating layer14, or alternatively, both on the first insulating layer13and on the second insulating layer14. InFIG.2, an example is shown in which a single connection wiring layer96is connected to the first lower wiring layer41by means of two connection via electrodes97.

The connection via electrode97has the same laminated structure as the first via electrode23(second via electrode24) and as the first long via electrode83(second long via electrode84). A detailed description of the connection via electrode97is omitted.

The second end portion61bof the first upper wiring layer61may be connected to an arbitrary connection wiring layer96through the connection via electrode97. The second end portion62bof the second upper wiring layer62may be connected to an arbitrary connection wiring layer96through the connection via electrode97.

Referring toFIG.2, an uppermost insulating layer101is formed on the insulating laminated structure12. The uppermost insulating layer101covers the first upper wiring layer61and the second upper wiring layer62. The uppermost insulating layer101covers a connection portion between the first upper wiring layer61and the first long via electrode83in a plan view. The uppermost insulating layer101covers a connection portion between the second upper wiring layer62and the second long via electrode84in a plan view.

A first pad opening102and a second pad opening103are formed in the uppermost insulating layer101in the outside region7. The first pad opening102exposes a region of a part of the first upper wiring layer61so as to serve as a first pad region104. More specifically, the first pad opening102exposes a region other than the connection portion between the first upper wiring layer61and the first long via electrode83in the first upper wiring layer61so as to serve as the first pad region104.

The second pad opening103exposes a region of a part of the second upper wiring layer62so as to serve as a second pad region105. More specifically, the second pad opening103exposes a region other than the connection portion between the second upper wiring layer62and the second long via electrode84in the second upper wiring layer62so as to serve as the second pad region105.

In this embodiment, the uppermost insulating layer101has a laminated structure including a passivation layer106and a resin layer107. For clarity, the resin layer107is shown by hatching inFIG.1.

The passivation layer106may have a laminated structure including a silicon oxide layer and a silicon nitride layer. In this case, the silicon nitride layer may be formed on the silicon oxide layer, or the silicon oxide layer may be formed on the silicon nitride layer.

The passivation layer106may have a single layer structure consisting of a silicon oxide layer or a silicon nitride layer. Preferably, the passivation layer106is made of an insulating material differing from that of the insulating laminated structure12. In this embodiment, the passivation layer106has a single layer structure consisting of a silicon nitride layer.

The resin layer107may include a photosensitive resin. The photosensitive resin may be a positive type or a negative type. The resin layer107may include at least one among polyimide, polyamide, and polybenzoxazole. Preferably, the resin layer107is made of polyamide or polybenzoxazole.

The first via electrode23, the first lower wiring layer41, the first long via electrode83, and the first upper wiring layer61form a first wiring that is connected to the thin film resistor35. An end (first via electrode23) of the first wiring is connected to the thin film resistor35inside the insulating laminated structure12, and the other end (first upper wiring layer61) of the first wiring serves as an external terminal exposed outwardly.

The second via electrode24, the second lower wiring layer42, the second long via electrode84, and the second upper wiring layer62form a second wiring that is connected to the thin film resistor35. An end (second via electrode24) of the second wiring is connected to the thin film resistor35inside the insulating laminated structure12, and the other end (second upper wiring layer62) of the second wiring serves as an external terminal exposed outwardly. A high voltage may be applied to the first wiring, and a low voltage may be applied to the second wiring. A low voltage may be applied to the first wiring, and a high voltage may be applied to the second wiring.

As described above, the electronic component1includes the third insulating layer15(first insulating layer) including impurities, the thin film resistor35formed on the third insulating layer15, and the barrier layer17that is interposed in at least a part of a region between the thin film resistor35and the third insulating layer15and that obstructs the transmission of the impurities.

With this electronic component1, the barrier layer17obstructs the transmission of impurities included in the third insulating layer15, and therefore it is possible to suppress the movement of the impurities from the third insulating layer15to the thin film resistor35. As a result, the surface resistance of the thin film resistor35becomes insusceptible to the impurities, and therefore it is possible to reduce the in-plane variation of its surface resistance.

The barrier layer17overlaps the entirety of the thin film resistor35. Hence, impurities are prevented from being moved from the third insulating layer15to the thin film resistor35over the entirety of the thin film resistor35, and therefore it is possible to more considerably reduce the in-plane variation of the surface resistance of the thin film resistor35.

The impurities include Ar. This makes it possible to form the third insulating layer15by using Ar as an inert gas, and makes it possible to form the thin film resistor35whose in-plane variation of the surface resistance has been reduced on the third insulating layer15.

FIG.7AtoFIG.7Uare cross-sectional views shown to describe an example of a method of producing the electronic component1ofFIG.1.FIG.7AtoFIG.7Uare cross-sectional views of a part, which corresponds toFIG.2, of the electronic component1.

Referring toFIG.10A, the semiconductor layer2is prepared. The semiconductor layer2includes the device region6and the outside region7. Next, the wiring circuit forming layer21of the insulating laminated structure12is formed on the first principal surface3of the semiconductor layer2. The wiring circuit forming layer21includes the first insulating layer13, the second insulating layer14, the single or plurality of connection wiring layers96, and the single or plurality of connection via electrodes97. A description of forming step of the wiring circuit forming layer21is omitted.

Next, referring toFIG.7B, a first base wiring layer111that serves as a base of the first lower wiring layer41and as a base of the second lower wiring layer42is formed on the wiring circuit forming layer21. The forming step of the first base wiring layer111includes a step of forming a first barrier layer112, a main body layer113, and a second barrier layer114in that order from the top of the wiring circuit forming layer21.

The forming step of the first barrier layer112includes a step of forming a Ti layer and a TiN layer in that order from the top of the wiring circuit forming layer21. The Ti layer and the TiN layer may be each formed by a sputtering method. The forming step of the main body layer113includes a step of forming an AlCu alloy layer on the first barrier layer112. The AlCu alloy layer may be formed by the sputtering method.

The forming step of the second barrier layer114includes a step of forming a Ti layer and a TiN layer in that order from the top of the main body layer113. The Ti layer and the TiN layer may be each formed by the sputtering method.

Next, referring toFIG.7C, a mask115having a predetermined pattern is formed on the first base wiring layer111. The mask115has an opening116that covers a region in which the first lower wiring layer41and the second lower wiring layer42in the first base wiring layer111are to be formed and that exposes regions other than the region in which the first lower wiring layer41and the second lower wiring layer42are to be formed.

Next, unnecessary portions of the first base wiring layer111are removed by an etching method through the mask115. Hence, the first base wiring layer111is divided into the first lower wiring layer41and the second lower wiring layer42. The mask115is removed afterward.

Next, referring toFIG.7D, the third insulating layer15covering the first and second lower wiring layers41and42is formed on the wiring circuit forming layer21. The third insulating layer15is formed by HDP-CDV (High Density Plasma Chemical Vapor Deposition). As a result, a stepped surface on which the shape of the first lower wiring layer41and the shape of the second lower wiring layer42are reflected is formed at the third insulating layer15. In other words, the first surface15aserving as a principal surface and the concave portion15bhollowed from the first surface15ain the region15cbetween the first lower wiring layer41and the second lower wiring layer42are formed at the third insulating layer15.

Next, referring toFIG.7E, the barrier layer17is formed on the third insulating layer15. In other words, a silicon oxide film (TEOS film) serving as the barrier layer17is formed by P-CDV (Plasma Chemical Vapor Deposition). The barrier layer17is formed so as to flatten its upper surface. As a result, the thickness of the barrier layer17becomes larger than surroundings in the region15cbetween the first lower wiring layer41and the second lower wiring layer42.

Next, referring toFIG.7F, a first via hole117that exposes the first lower wiring layer41and a second via hole118that exposes the second lower wiring layer42are formed in the third insulating layer15and the barrier layer17. In this step, a mask119having a predetermined pattern is first formed on the third insulating layer15. The mask119has a plurality of openings120that expose a region in which the first via hole117and the second via hole118are to be formed in the barrier layer17.

Next, unnecessary portions of the third insulating layer15and unnecessary portions of the barrier layer17are removed by the etching method through the mask119. Hence, the first via hole117and the second via hole118are formed in the third insulating layer15and the barrier layer17. The mask119is removed afterward.

Next, referring toFIG.7G, a base electrode layer121that serves as a base of the first via electrode23and as a base of the second via electrode24is formed on the barrier layer17. The forming step of the base electrode layer121includes a step of forming a barrier layer122and a main body layer123in that order from the top of the barrier layer17.

The forming step of the barrier layer122includes a step of forming a Ti layer and a TiN layer in that order from the top of the barrier layer17. The Ti layer and the TiN layer may be each formed by the sputtering method. The forming step of the main body layer123includes a step of forming a tungsten layer on the barrier layer122. The tungsten layer may be formed by a CVD method.

Next, referring toFIG.7H, the removing step of the base electrode layer121is performed. The base electrode layer121is removed until the barrier layer17is exposed. The removing step of the base electrode layer121may include a step of removing the base electrode layer121by grinding.

In this embodiment, the grinding step of the base electrode layer121is performed by a CMP (Chemical Mechanical Polishing) method that uses a polishing agent (abrasive grains). The grinding step of the base electrode layer121may include a step of flattening the principal surface of the barrier layer17. Hence, the first via electrode23is formed inside the first via hole117. Additionally, the second via electrode24is formed inside the second via hole118.

Thereafter, referring toFIG.7I, the polishing agent (abrasive grains) that has adhered to the principal surface of the barrier layer17is removed by washing while using a chemical liquid. A part of the barrier layer17is removed together with the polishing agent (abrasive grains) by means of the chemical liquid in this step. Hence, a part of the first via electrode23is formed as the first projecting portion23cthat projects from the barrier layer17. Additionally, a part of the second via electrode24is formed as the second projecting portion24cthat projects from the barrier layer17.

Next, referring toFIG.7J, a base resistance layer124that serves as a base of the thin film resistor35is formed on the principal surface of the barrier layer17. The base resistance layer124includes chromium silicide. The base resistance layer124may include at least one among CrSi, CrSi2, CrSiN, and CrSiO as an example of the chromium silicide. In this embodiment, the base resistance layer124is made of CrSi. The base resistance layer124may be formed by the sputtering method.

Next, a base protective layer125that serves as a base of the protective layer40is formed on the base resistance layer124. The base protective layer125includes silicon oxide. The base protective layer125may be formed by the CVD method.

Next, the base resistance layer124(CrSi) is crystallized. The crystallization step of the base resistance layer124includes a step of performing annealing treatment at temperature and time at which the base resistance layer124(CrSi) is crystallized. The base resistance layer124may be heated during a period of time of not less than 60 minutes and not more than 120 minutes at a temperature of not less than 400° and not more than 600°. The crystallization step of the base resistance layer124may be performed prior to the forming step of the protective layer40after the forming step of the base resistance layer124.

Next, referring toFIG.7K, a mask126having a predetermined pattern is formed on the base protective layer125. The mask126has an opening127that covers a region in which the protective layer40is to be formed in the base protective layer125and that exposes regions other than the region in which the protective layer40is to be formed. Next, unnecessary portions of the base protective layer125are removed by the etching method through the mask126. Hence, the protective layer40is formed.

Next, unnecessary portions of the base resistance layer124are removed by an etching method in which the mask126and the protective layer40are each used as a mask. Hence, the thin film resistor35is formed. The mask126is removed afterward. The mask126may be removed prior to the forming step of the thin film resistor35after the forming step of the protective layer40.

Next, referring toFIG.7L, the fourth insulating layer16covering the protective layer40and the thin film resistor35is formed on the barrier layer17. The fourth insulating layer16may be formed by the CVD method.

Next, referring toFIG.7M, a first via hole128that exposes the first lower wiring layer41and a second via hole129that exposes the second lower wiring layer42are formed in the third insulating layer15, the barrier layer17, and the fourth insulating layer16.

In this step, a mask130having a predetermined pattern is first formed on the fourth insulating layer16. The mask130has a plurality of openings131that expose a region in which the first via hole128and the second via hole129are to be formed in the fourth insulating layer16.

Next, unnecessary portions of the third insulating layer15, unnecessary portions of the barrier layer17, and unnecessary portions of the fourth insulating layer16are removed by the etching method through the mask130. Hence, the first via hole128and the second via hole129are formed in the third insulating layer15, the barrier layer17, and the fourth insulating layer16. The mask130is removed afterward.

Next, referring toFIG.7N, a base electrode layer132that serves as a base of the first long via electrode83and as a base of the second long via electrode84is formed on the fourth insulating layer16. The forming step of the base electrode layer132includes a step of forming a barrier layer133and a main body layer134in that order from the top of the fourth insulating layer16.

The forming step of the barrier layer133includes a step of forming a Ti layer and a TiN layer in that order from the top of the fourth insulating layer16. The Ti layer and the TiN layer may be each formed by the sputtering method. The forming step of the main body layer134includes a step of forming a tungsten layer on the barrier layer133. The tungsten layer may be formed by the CVD method.

Next, referring toFIG.7O, the removing step of the base electrode layer132is performed. The base electrode layer132is removed until the fourth insulating layer16is exposed. The removing step of the base electrode layer132may include a step of removing the base electrode layer132by grinding.

In this embodiment, the grinding step of the base electrode layer132is performed by the CMP method using a polishing agent (abrasive grains). The grinding step of the base electrode layer132may include a step of flattening the principal surface of the fourth insulating layer16. Hence, the first long via electrode83and the second long via electrode84are formed in the first via hole128and the second via hole129, respectively.

The polishing agent (abrasive grains) that has adhered to the principal surface of the fourth insulating layer16may be removed by washing while using a chemical liquid after the grinding step of the base electrode layer132. A part of the fourth insulating layer16may be removed together with the polishing agent (abrasive grains) by means of a chemical liquid. In this case, a part of the first long via electrode83may be formed as a projecting portion that projects from the fourth insulating layer16. Additionally, a part of the second long via electrode84may be formed as a projecting portion that projects from the fourth insulating layer16.

Next, referring toFIG.7P, a second base wiring layer135that serves as a base of the first upper wiring layer61and as a base of the second upper wiring layer62is formed on the fourth insulating layer16. The forming step of the second base wiring layer135includes a step of forming a first barrier layer136, a main body layer137, and a second barrier layer138in that order from the top of the fourth insulating layer16.

The forming step of the first barrier layer136includes a step of forming a Ti layer and a TiN layer in that order from the top of the fourth insulating layer16. The Ti layer and the TiN layer may be each formed by the sputtering method. The forming step of the main body layer137includes a step of forming an AlCu alloy layer on the first barrier layer136. The AlCu alloy layer may be formed by the sputtering method.

The forming step of the second barrier layer138includes a step of forming a Ti layer and a TiN layer in that order from the top of the main body layer137. The Ti layer and the TiN layer may be each formed by the sputtering method.

Next, referring toFIG.7Q, a mask139having a predetermined pattern is formed on the second base wiring layer135. The mask139has an opening140that covers a region in which the first upper wiring layer61and the second upper wiring layer62in the second base wiring layer135are to be formed in the outside region7and that exposes regions other than the region in which the first upper wiring layer61and the second upper wiring layer62are to be formed.

Next, unnecessary portions of the second base wiring layer135are removed by the etching method through the mask139. Hence, the second base wiring layer135is divided into the first upper wiring layer61and the second upper wiring layer62. Additionally, hence, the insulating laminated structure12including the wiring circuit forming layer21and the resistance circuit forming layer22is formed on the first principal surface3of the semiconductor layer2. The mask139is removed afterward.

Next, referring toFIG.7R, the passivation layer106is formed on the insulating laminated structure12. The passivation layer106includes silicon nitride. The passivation layer106may be formed by the CVD method.

Next, referring toFIG.7S, the trimming mark38is formed in a predetermined region of the thin film resistor35(seeFIG.5). In this step, the trimming mark38is formed at the thin film resistor35by removing (trimming) a part of the thin film resistor35by means of a laser radiation method. Hence, the resistance value of the thin film resistor35is adjusted so as to be a desired value.

Next, referring toFIG.7T, a photosensitive resin that becomes the resin layer107is applied onto the passivation layer106. The photosensitive resin may include at least one among polyimide, polyamide, and polybenzoxazole. Preferably, the photosensitive resin is made of polyimide or polybenzoxazole. Next, the photosensitive resin is selectively exposed to light, and is then developed. Hence, the resin layer107having a plurality of openings141that serve as a base of the first pad opening102and as a base of the second pad opening103is formed.

Next, referring toFIG.7U, unnecessary portions of the passivation layer106are removed by the etching method through the resin layer107. Hence, the first pad opening102and the second pad opening103that expose the first upper wiring layer61and the second upper wiring layer62, respectively, are formed. The electronic component1is produced through a process including these steps.

Second Preferred Embodiment

FIG.8is a cross-sectional view, which corresponds toFIG.2, showing an electronic component150according to a second preferred embodiment of the present disclosure. The same reference sign is hereinafter given to a constituent corresponding to each constituent described with respect to the electronic component1according to the first preferred embodiment, and a description of this constituent is omitted.

The electronic component150according to the second preferred embodiment has a configuration in which the barrier layer17overlaps only one part of the thin film resistor35. The barrier layer17overlaps a central region of the thin film resistor35, whereas the barrier layer17does not overlap end regions of the thin film resistor35. The barrier layer17is formed on the bottom surface15dof the third insulating layer15, and yet is not formed on the first surface15aof the third insulating layer15. More specifically, the barrier layer17may have only its part embedded in the concave portion15bof the third insulating layer15, and the first surface15aof the third insulating layer15is exposed from the barrier layer17. Hence, a part of the thin film resistor35is in contact with the first surface15aof the third insulating layer15.

The fourth insulating layer16is in contact with the first surface15aof the third insulating layer15. Therefore, the first via electrode23and the second via electrode24are embedded in the third insulating layer15. Additionally, the first long via electrode83and the second long via electrode84are embedded in the third insulating layer15and the fourth insulating layer16.

Likewise, with the thus formed electronic component150, the barrier layer17obstructs the transmission of impurities included in the third insulating layer15, and therefore the surface resistance of the thin film resistor35becomes insusceptible to the impurities. As a result, it is possible to reduce the in-plane variation of the surface resistance of the thin film resistor35.

Next, samples in which the present disclosure has been carried out will be described. The present disclosure is not limited to the following samples.FIG.9is a cross-sectional view, which corresponds toFIG.2, showing an electronic component160according to Sample3.FIG.10is a graph showing in-plane variations of surface resistance Rs in the thin film resistor35.

A reference example is the electronic component160that does not have the barrier layer17and in which the fourth insulating layer16is laminated on the third insulating layer15. Sample1corresponds to the electronic component1according to the first preferred embodiment shown inFIG.2. Sample2corresponds to the electronic component150according to the second preferred embodiment shown inFIG.8.

As shown inFIG.10, it was ascertained that the in-plane variation of the surface resistance Rs exceeds 100% in the reference example, whereas the in-plane variation of the surface resistance Rs is suppressed to 20% or less in Sample2, and is suppressed to 10% or less in Sample1.

Third Preferred Embodiment

FIG.11is a schematic plan view showing an electronic component151according to a third preferred embodiment of the present disclosure, and is a plan view showing a form in which the thin film resistor35according to a first configuration example is incorporated therein.

The electronic component1includes the single resistance circuit10(thin film resistor35) formed in the outside region7. On the other hand, referring toFIG.11, the electronic component151includes a plurality of (two or more: in this embodiment, four) resistance circuits10(thin film resistors35) formed in the outside region7. The number of resistance circuits10(thin film resistors35) is arbitrary, and may be set so as to be five or more in accordance with the form of the functional device.

The resistance circuits10(thin film resistors35) are each electrically connected to the device region6(functional device) through the wiring circuit forming layer21. Each of the resistance circuits10(thin film resistors35) may be electrically connected to the device region6independently of each other. At least two among the resistance circuits10(thin film resistors35) may be connected in parallel or in series with each other.

As described above, the electronic component151is likewise enabled to fulfill the same effect as the effect described with respect to the electronic component1.

The electronic component1according to the first preferred embodiment, the electronic component150according to the second preferred embodiment, and the electronic component151according to the third preferred embodiment may have an electric structure shown inFIG.12.FIG.12is a circuit diagram showing an electric structure according to the first configuration example of the electronic component1according to the first preferred embodiment and of the electronic component151according to the second preferred embodiment.

Referring toFIG.12, the electronic components1and151include an operational amplifier circuit201. The operational amplifier circuit201includes a positive supply terminal202, a negative supply terminal203, a non-inverted positive supply terminal204, an inverted positive supply terminal205, an output terminal206, transistors TrA1to TrA14(semiconductor switching devices), and resistors RA1to RA4(passive devices).

A power supply voltage VDD is input to the positive supply terminal202. A reference voltage VSS is input to the negative supply terminal203. The reference voltage VSS may be a ground voltage. A non-inverted voltage VIN+ is input to the non-inverted positive supply terminal204. An inverted voltage VIN− is input to the inverted positive supply terminal205. The operational amplifier circuit201amplifies a difference voltage between the non-inverted voltage VIN+ and the inverted voltage VIN−, and outputs it from the output terminal206. In short, the operational amplifier circuit201is a differential operational amplifier circuit.

The transistors TrA1to TrA14are each formed in the device region6in the semiconductor layer2. In other words, the functional device formed in the device region6includes a circuit network formed by the transistors TrA1to TrA14. The transistors TrA1to TrA3and TrA7to TrA10each consist of a p type MISFET. The transistors TrA4to TrA6and TrA11to TrA14each consist of an n type MISFET.

On the other hand, the resistors RA1to RA4are formed in the outside region7in the semiconductor layer2. At least one or all of the resistors RA1to RA4are formed by the thin film resistor35. The resistors RA1to RA4form current-value setting resistance, and determine a current amplification factor. The resistors RA1to RA4are selectively connected to a circuit network formed by the transistors TrA1to TrA14through the wiring circuit forming layer21(connection wiring layer96and connection via electrode97).

A bias voltage Vb1is input to a gate of the transistor TrA1. A drain of the transistor TrA1is connected to the positive supply terminal202. A source of the transistor TrA1is connected to a source of the transistor TrA2and to a source of the transistor TrA3. A gate of the transistor TrA2is connected to the non-inverted positive supply terminal204. A gate of the transistor TrA3is connected to the inverted positive supply terminal205.

A bias voltage Vb2is input to a gate of the transistor TrA4. A drain of the transistor TrA4is connected to a source of the transistor TrA5and to a source of the transistor TrA6.

A source of the transistor TrA4is connected to the negative supply terminal203. A gate of the transistor TrA5is connected to the non-inverted positive supply terminal204. A gate of the transistor TrA6is connected to the inverted positive supply terminal205.

A gate of the transistor TrA7is connected to a gate of the transistor TrA8. A bias voltage Vb3is input to the gate of the transistor TrA7and to the gate of the transistor TrA8. A source of the transistor TrA7is connected to the positive supply terminal202through the resistor RA1.

A drain of the transistor TrA7is connected to a source of the transistor TrA9. A source of the transistor TrA8is connected to the positive supply terminal202through the resistor RA2. A drain of the transistor TrA8is connected to a source of the transistor TrA10.

A gate of the transistor TrA9is connected to a gate of the transistor TrA10. A bias voltage Vb4is input to the gate of the transistor TrA9and to the gate of the transistor TrA10.

A drain of the transistor TrA9is connected to a drain of the transistor TrA11. A drain of the transistor TrA10is connected to a drain of the transistor TrA12.

A drain of the transistor TrA6is connected to a connection portion between the drain of the transistor TrA7and the source of the transistor TrA9. A drain of the transistor TrA5is connected to a connection portion between the drain of the transistor TrA8and the source of the transistor TrA10.

A gate of the transistor TrA11is connected to a gate of the transistor TrA12. A bias voltage Vb5is input to the gate of the transistor TrA11and to the gate of the transistor TrA12.

A source of the transistor TrA11is connected to a drain of the transistor TrA13. A source of the transistor TrA12is connected to a drain of the transistor TrA14.

A gate of the transistor TrA13is connected to a gate of the transistor TrA14. The gate of the transistor TrA13and the gate of the transistor TrA14are connected to the drain of the transistor TrA11.

A source of the transistor TrA13is connected to the negative supply terminal203through the resistor RA3. A source of the transistor TrA14is connected to the negative supply terminal203through the resistor RA4.

An example in which the operational amplifier circuit201includes the transistors TrA1to TrA6has been described in this embodiment. However, the operational amplifier circuit201that does not include the transistors TrA1to TrA3may be employed, or the operational amplifier circuit201that does not include the transistors TrA4to TrA6may be employed.

The electronic component1according to the first preferred embodiment, the electronic component150according to the second preferred embodiment, and the electronic component151according to the third preferred embodiment may have an electric structure shown inFIG.13.FIG.13is a circuit diagram showing an electric structure according to a second configuration example of the electronic component1according to the first preferred embodiment, of the electronic component150according to the second preferred embodiment, and of the electronic component151according to the third preferred embodiment.

Referring toFIG.13, the electronic components1and151include a current amplification type constant current regulator211. The constant current regulator211includes a positive supply terminal212, a negative supply terminal213, an output terminal214, transistors TrB1to TrB12(semiconductor switching devices), resistors RB1to RB3(passive devices), and a capacitor C (passive device).

A power supply voltage VDD is input to the positive supply terminal212. A reference voltage VSS is input to the negative supply terminal213. The reference voltage VSS may be a ground voltage. The constant current regulator211outputs a constant current according to a potential difference between the power supply voltage VDD and the reference voltage VSS from the output terminal214.

The transistors TrB1to TrB12, the resistors RB1and RB3, and the capacitor C are each formed in the device region6in the semiconductor layer2. In other words, the functional device formed in the device region6includes a circuit network formed by the transistors TrB1to TrB12, the resistors RB1and RB3, and the capacitor C.

The transistors TrB1to TrB4and TrB7each consist of an n type MISFET. The transistor TrB5and TrB6each consist of an npn type BJT. The transistors TrB8to TrB12each consist of a p type MISFET. The resistors RB1and RB3may be each made of polysilicon resistance.

The resistor RB2is formed in the outside region7in the semiconductor layer2. The resistor RB2is formed by the thin film resistor35. The resistor RB2forms current-value setting resistance, and determines a current amplification factor. The resistor RB2is selectively connected to a circuit network formed by the transistors TrB1to TrB12, the resistors RB1and RB3, and the capacitor C through the wiring circuit forming layer21(connection wiring layer96and connection via electrode97).

A gate of the transistor TrB1is connected to a gate of the transistor TrB2. The gate of the transistor TrB1and the gate of the transistor TrB2are connected to a drain of the transistor TrB1.

The drain of the transistor TrB1is connected to the positive supply terminal212through the resistor RB1. A source of the transistor TrB1is connected to the negative supply terminal213. A source of the transistor TrB2is connected to the source of the transistor TrB1.

A gate of the transistor TrB3is connected to a gate of the transistor TrB4. The gate of the transistor TrB3and the gate of the transistor TrB4are connected to a drain of the transistor TrB3.

A source of the transistor TrB3is connected to the negative supply terminal213. A drain of the transistor TrB2is connected to the gate of the transistor TrB1and to the gate of the transistor TrB2. A source of the transistor TrB4is connected to the negative supply terminal213.

A base of the transistor TrB5is connected to a base of the transistor TrB6. The base of the transistor TrB5and the base of the transistor TrB6are connected to a collector of the transistor TrB5. An emitter of the transistor TrB5is connected to the negative supply terminal213through the resistor RB2. An emitter of the transistor TrB6is connected to the negative supply terminal213.

A gate of the transistor TrB7is connected to a collector of the transistor TrB6. A drain of the transistor TrB7is connected to the drain of the transistor TrB2. A source of the transistor TrB7is connected to the negative supply terminal213.

The resistor RB3forms an RC series circuit215with the capacitor C. The RC series circuit215is connected to an area between the gate of the transistor TrB7and the negative supply terminal213.

Gates of the transistors TrB8to TrB12are connected to each other. The gates of the transistor TrB8to TrB12are each connected to the gate of the transistor TrB7. Drains of the transistors TrB8to TrB12are each connected to the positive supply terminal212.

A source of the transistor TrB8is connected to the drain of the transistor TrB3. A source of the transistor TrB9is connected to the collector of the transistor TrB5. A source of the transistor TrB10is connected to the collector of the transistor TrB6.

A source of the transistor TrB11is connected to the gates of the transistors TrB8, TrB9, TrB10, and TrB12, and is connected to the drain of the transistor TrB7. A source of the transistor TrB12is connected to the output terminal214.

Besides, various design changes can be made within the range of items listed in the claims.

The following features can be extracted from the present disclosure besides the invention described in the claims.

An electronic component including:a first insulating layer that includes impurities,a thin film resistor formed on the first insulating layer, anda barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities.

According to this configuration, the barrier layer obstructs transmission of impurities included in the first insulating layer, and therefore it is possible to suppress the movement of the impurities from the first insulating layer to the thin film resistor. As a result, the surface resistance of the thin film resistor becomes insusceptible to the impurities, and therefore it is possible to reduce the in-plane variation of the surface resistance.

The electronic component according to Appendix 1, where the barrier layer overlaps entirety of the thin film resistor.

According to this configuration, the impurities are prevented from being moved from the first insulating layer to the thin film resistor over the entirety of the thin film resistor, and therefore it is possible to more considerably reduce the in-plane variation of the surface resistance of the thin film resistor.

The electronic component according to Appendix 1 or Appendix 2, where the first insulating layer includes a first surface and a concave portion that is hollowed with respect to the first surface, andthe barrier layer is embedded in the concave portion.
[Appendix 4]

The electronic component according to Appendix 3, where the barrier layer includes a first part embedded in the concave portion and a second part formed along the first surface of the first insulating layer from an upper area of the first part.

The electronic component according to Appendix 3 or Appendix 4, where the concave portion has a bottom surface and an inclined surface that connects the bottom surface and the first surface together.

The electronic component according to any one of Appendix 1 to Appendix 5, where the impurities include Ar.

According to this configuration, it is possible to form the first insulating layer by using Ar as an inert gas, and it is possible to form the thin film resistor whose in-plane variation of the surface resistance has been reduced on the first insulating layer.

The electronic component according to any one of Appendix 1 to Appendix 6, further including:a second insulating layer that is formed on the first insulating layer and that covers the thin film resistor,a first via electrode that is embedded in the first insulating layer and that is in contact with a first end portion of the thin film resistor, anda second via electrode that is embedded in the first insulating layer and that is in contact with a second end portion on a side opposite to the first end portion in the thin film resistor.
[Appendix 8]

The electronic component according to Appendix 7, further including:a first lower wiring layer that is formed in a region on a side of the first insulating layer with respect to the thin film resistor and that is electrically connected to the first via electrode, anda second lower wiring layer that is formed in a region on a side of the first insulating layer with respect to the thin film resistor and that is electrically connected to the second via electrode.
[Appendix 9]

The electronic component according to Appendix 8, where the thin film resistor is connected in series with the first lower wiring layer and with the second lower wiring layer.

The electronic component according to Appendix 8 or Appendix 9, further including:a first upper wiring layer that is formed on the second insulating layer and that is electrically connected to the first lower wiring layer, anda second upper wiring layer that is formed on the second insulating layer and that is electrically connected to the second lower wiring layer.
[Appendix 11]

The electronic component according to Appendix 10, where the thin film resistor is connected in series with the first upper wiring layer and with the second upper wiring layer.

The electronic component according to Appendix 10 or Appendix 11, where the first upper wiring layer is away from the thin film resistor in a plan view, and

the second upper wiring layer is away from the thin film resistor in a plan view.

The electronic component according to any one of Appendix 10 to Appendix 12, where the first upper wiring layer forms an uppermost wiring layer, andthe second upper wiring layer forms an uppermost wiring layer.
[Appendix 14]

The electronic component according to any one of Appendix 10 to Appendix 13, where the first upper wiring layer has a thickness equal to or more than a thickness of the first lower wiring layer.

The electronic component according to any one of Appendix 10 to Appendix 14, where the second upper wiring layer has a thickness equal to or more than a thickness of the second lower wiring layer.

The electronic component according to any one of Appendix 10 to Appendix 15, further including:a first long via electrode that is allowed to pass though and is embedded in the first insulating layer and the second insulating layer and that is electrically connected to the first lower wiring layer and to the first upper wiring layer, anda second long via electrode that is allowed to pass though and is embedded in the first insulating layer and the second insulating layer and that is electrically connected to the second lower wiring layer and to the second upper wiring layer.
[Appendix 17]

The electronic component according to Appendix 16, where the thin film resistor is placed on a straight line that connects the first long via electrode and the second long via electrode together in a plan view.

The electronic component according to Appendix 16 or Appendix 17, where the first long via electrode has a first lower part placed on a side of the first lower wiring layer with respect to the thin film resistor and a first upper part that is placed on a side of the first upper wiring layer with respect to the thin film resistor and that has a length equal to or more than a length of the first lower part.

The electronic component according to any one of Appendix 16 to Appendix 18, where the second long via electrode has a second lower part placed on a side of the second lower wiring layer with respect to the thin film resistor and a second upper part that is placed on a side of the second upper wiring layer with respect to the thin film resistor and that has a length equal to or more than a length of the second lower part.

The electronic component according to any one of Appendix 16 to Appendix 19, further including an insulating layer that covers the first upper wiring layer and the second upper wiring layer and that has a first pad opening by which the first upper wiring layer is exposed and a second pad opening by which the second upper wiring layer is exposed.

The electronic component according to Appendix 20, where the insulating layer covers a connection portion between the first upper wiring layer and the first long via electrode in a plan view.

The electronic component according to Appendix 20 or Appendix 21, where the insulating layer covers a connection portion between the second upper wiring layer and the second long via electrode in a plan view.

The electronic component according to any one of Appendix 7 to Appendix 22, where the first via electrode has a first projecting portion that projects toward the second insulating layer with respect to a principal surface of the first insulating layer, andthe thin film resistor covers the first projecting portion of the first via electrode.
[Appendix 24]

The electronic component according to any one of Appendix 7 to Appendix 23, where the second via electrode has a second projecting portion that projects toward the second insulating layer with respect to the principal surface of the first insulating layer, andthe thin film resistor covers the second projecting portion of the second via electrode.
[Appendix 25]

The electronic component according to any one of Appendix 1 to Appendix 24, further including a semiconductor layer having a principal surface, wherethe first insulating layer is formed on the principal surface of the semiconductor layer.
[Appendix 26]

The electronic component according to Appendix 25, where the semiconductor layer includes a device region in which a functional device has been formed and an outside region outside the device region, andthe thin film resistor is formed in the outside region in a plan view.
[Appendix 27]

The electronic component according to any one of Appendix 1 to Appendix 26, where the thin film resistor is made of a metal thin film including at least one among CrSi, TaN, and TiN.

A method of producing an electronic component, the method including:a step of forming a lower wiring layer by sputtering by use of an inert gas;a first step of forming a first insulating layer so as to cover the lower wiring layer;a second step of forming a barrier layer on the first insulating layer, the barrier layer obstructing transmission of compositions of the inert gas included in the first insulating layer; anda third step of forming a thin film resistor on the barrier layer so as to allow at least one part of the thin film resistor to overlap the barrier layer.

According to this method, when the lower wiring layer is formed by sputtering, an impurity included in the inert gas remains in the lower wiring layer as an impurity, and this impurity comes to be included in the first insulating layer formed in the first step. However, the barrier layer formed in the second step obstructs the transmission of the impurity, and therefore it is possible to suppress the movement of the impurity to the thin film resistor formed in the third step. As a result, the surface resistance of the thin film resistor becomes insusceptible to the impurity, and therefore it is possible to reduce the in-plane variation of the surface resistance.

The method of producing an electronic component according to Appendix 28, where the lower wiring layer includes a first lower wiring layer and a second lower wiring layer formed with a predetermined region between the second lower wiring layer and the first lower wiring layer, andthe first insulating layer is formed so as to have a concave portion on the predetermined region in the first step,the barrier layer is formed so as to be embedded in the concave portion in the second step, andthe thin film resistor is formed on the barrier layer embedded in the concave portion in the third step.
[Appendix 30]

The method of producing an electronic component according to Appendix 28 or Appendix 29, where the first step includes a step of forming the first insulating layer by HDP-CDV (High Density Plasma Chemical Vapor Deposition), andthe second step includes a step of forming the barrier layer by P-CDV (Plasma Chemical Vapor Deposition) while using a TEOS gas.

This application corresponds to Japanese Patent Application No. 2020-036117 filed in the Japan Patent Office on Mar. 3, 2020, the entire disclosure of which is incorporated herein by reference.

Reference Signs List1electronic component2semiconductor layer3first principal surface6device region7outside region17barrier layer17afirst part17bsecond part15third insulating layer15afirst surface15bconcave portion15cregion15dbottom surface15einclined surface16fourth insulating layer23first via electrode23cfirst projecting portion of first via electrode24second via electrode24csecond projecting portion of second via electrode35thin film resistor35afirst end portion35bsecond end portion41first lower wiring layer42second lower wiring layer61first upper wiring layer62second upper wiring layer83first long via electrode83clower part of first long via electrode83dupper part of first long via electrode84second long via electrode84clower part of second long via electrode84dupper part of second long via electrode101uppermost insulating layer102first pad opening103second pad opening150electronic component151electronic componentTL1first wiring thicknessTL2second wiring thickness