Non-volatile memory device with independent channel regions adjacent different sides of a common control gate

Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.

PRIORITY STATEMENT

This application claims the benefit of Korean Patent Application No. 10-2006-0118558, filed on Nov. 28, 2006, in the Korean Intellectual Property Office, the entire contents of which is incorporated herein by reference.

BACKGROUND

Example embodiments relate to a semiconductor device, and more particularly, to a non-volatile memory device including a storage node layer for storing charges and a method of fabricating the same.

2. Description of the Related Art

FIG. 1is a plan view of a conventional non-volatile memory device. Referring toFIG. 1, the non-volatile memory device includes buried bit line regions55and control gate electrodes70which extend across the buried bit line regions55. Dopant may be doped in a semiconductor substrate50to define the buried bit line regions55. Since an isolation layer in a cell region is not required in a non-volatile memory device as shown inFIG. 1, the non-volatile memory device may have a relatively small size.

However, the buried bit line regions55in conventional non-volatile memory devices generally have higher resistances than metal lines. Thus, the resistances of the buried bit line regions55are relatively high in an array structure in which the buried bit line regions55have long lengths. Therefore, the buried bit line regions55arranged beside the control gate electrodes70are connected to metal lines through contact structures60. However, the contact structures60increase the size of the non-volatile memory device and thus, reduce the integration of the conventional non-volatile memory device as shown inFIG. 1.

Further, if distances between the buried bit line regions55are shortened, the integration of the non-volatile memory device may be increased. However, in this case, the reliability of the conventional non-volatile memory device is significantly decreased due to a short channel effect.

SUMMARY

Example embodiments provide a non-volatile memory device that may be highly integrated and reliable, and a method of fabricating the non-volatile memory device.

An example embodiment provides a non-volatile memory device. The non-volatile memory device may include a first control gate electrode recessed into a semiconductor substrate; a gate insulating layer interposed between the semiconductor substrate and the control gate electrode; a storage node layer interposed between the gate insulating layer and the control gate electrode; a blocking insulating layer interposed between the storage node layer and the control gate electrode; a plurality of first dopant doping regions disposed along a first side of the first control gate electrode; and a plurality of second dopant doping regions disposed along a second side of the first control gate electrode opposite to the first side. According to an example embodiment the second dopant doping regions alternate with the first dopant doping regions. Stated differently, each of the second dopant doping regions are arranged in a region on the second side of the control gate electrode that is adjacent to at least one of the first dopant doping regions.

According to an example embodiment, the non-volatile memory device may further include a plurality of first bit line electrodes and a plurality of second bit line electrodes. Each of the plurality of first bit line electrodes may include at least one first plug portion recessed into one of the first dopant doping regions. Each of the plurality of second bit line electrodes may include at least one second plug portions recessed into one of the second dopant doping regions.

According to an example embodiment, the non-volatile memory device may further include a buried insulating layer interposed between a bottom of the control gate electrode and the semiconductor substrate. The thickness of the buried insulating layer is greater than the thickness of the gate insulating layer.

According to an example embodiment, the non-volatile memory device may also include a second control gate electrode formed on the control gate electrode to be recessed into the semiconductor substrate; the second control gate electrode being insulated from the first control gate electrode.

Another example embodiment provides a non-volatile memory device. The non-volatile memory device may include a plurality of control gate electrodes recessed into a semiconductor substrate; a gate insulating layer interposed between the semiconductor substrate and the control gate electrodes; a storage node layer interposed between the gate insulating layer and the control gate electrodes; a blocking insulating layer interposed between the storage node layer and the control gate electrodes; a plurality of first dopant doping regions disposed along first sides of the control gate electrodes and defined in the semiconductor substrate; and a plurality of second dopant doping regions alternating with the first dopant doping regions along second sides of the control gate electrodes opposite to the first sides and defined in the semiconductor substrate.

Still another example embodiment provides a method of fabricating a non-volatile memory device. The method may include forming a first trench in a semiconductor substrate; forming a gate insulating layer in the first trench; forming a storage node layer covering the gate insulating layer; forming a blocking insulating layer covering the storage node layer; forming a control gate electrode on the blocking insulating layer to fill at least a portion of the first trench; forming a plurality of first dopant doping regions along a first side of the control gate electrode; and forming a plurality of second dopant doping regions in the semiconductor substrate along a second side of the control gate electrode opposite to the first side, each of the plurality of second dopant doping regions being formed in a region on the second side that is adjacent to at least one of the plurality of first dopant doping regions along the first side.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments, and one skilled in the art will appreciate that example embodiments may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

Example embodiments described below with respect to the drawings are provided so that this disclosure will be thorough, complete and fully convey the concept of the example embodiments to those skilled in the art. In the drawings, like numbers refer to like elements throughout. Further, the thicknesses of layers and regions are exaggerated for clarity in the drawings. Still further, in the example embodiments described below, a non-volatile memory device may be a flash memory device.

FIG. 2is a perspective view of an example embodiment of a non-volatile memory device,FIG. 3is a cross-sectional view of the non-volatile memory device taken along a line III-III′ ofFIG. 2, andFIG. 4is a plan view of the non-volatile memory device taken along a line IV-IV′ ofFIG. 3.

Referring toFIGS. 2 through 4, a gate electrode140may be recessed in a semiconductor substrate105. A gate insulating layer120may be interposed between the semiconductor substrate105and the control gate electrode140. A storage node layer125is interposed between the gate insulating layer120and the control gate electrode140. A blocking insulating layer130may be interposed between the storage node layer125and the control gate electrode140. First dopant doping regions153may be disposed along a first side of the control gate electrode140, and second dopant doping regions157may be disposed along a second side of the control gate electrode140.

In the example embodiment of the non-volatile memory device shown inFIGS. 2 through 4, the control gate electrode140may be used as a part of a word line. Thus, the control gate electrode140may be controlled to store data in the storage node layer125or erase data from the storage node layer125. Two adjacent first dopant doping regions153and the control gate electrode140may form a memory transistor or a unit cell. Also, two adjacent second dopant doping regions157and the control gate electrode140may form a memory transistor or a unit cell. Thus, the first dopant doping regions153may be sequentially called source regions or drain regions, and the second dopant doping regions157may be sequentially called source regions or drain regions.

First channel regions154may be arranged along the first side of the control gate electrode140and may be located and/or defined between every two adjacent first dopant doping regions153in the semiconductor substrate105. Similarly, second channel regions158may be arranged along the second side of the control gate electrode140and may be located and/or defined between every two adjacent second dopant doping regions157. In other words, the first and second channel regions154and158may be located and/or defined along the first and second sides of the control gate electrode140, respectively. The first and second channel regions154and158are regions in which channels are to be formed when a memory transistor is activated.

For example,FIGS. 1 through 3may illustrate a cell region of a non-volatile memory device. An isolation layer may not be interposed between unit cells in the cell region of the non-volatile memory device. However, an isolation layer may be formed in a peripheral region outside the cell region. Because the isolation layer may be omitted in the cell region as described above, integration of an example embodiment of the non-volatile memory device may be improved as compared to conventional non-volatile memory devices.

According to an example embodiment, the semiconductor substrate105may be a bulk semiconductor wafer, e.g., a silicon wafer, a germanium wafer, or a silicon-germanium wafer. As illustrated inFIGS. 1 and 2, the control gate electrode140is recessed into the semiconductor substrate105and thus may be referred to as a recess type or trench type control gate electrode. However, as indicated above, the example embodiment illustrated inFIGS. 1 and 2, or any of the other example embodiments, do not limit the scope of this disclosure.

The control gate electrode140may be recessed from a surface of the semiconductor substrate105into an interior of the semiconductor substrate105to a desired and/or predetermined depth according to an example embodiment. However, according to another example embodiment, the control gate electrode140may include a portion protruding from the surface of the semiconductor substrate105or may be buried in the semiconductor substrate105. The first and second sides of the control gate electrode140may refer to the longitudinal sides of the control gate electrode140based on the plan view of the non-volatile memory device taken along the line IV-IV′ ofFIG. 3.

The control gate electrode140may be insulated from the semiconductor substrate105. For example, the control gate electrode140may be insulated from the semiconductor substrate105by the gate insulating layer120. A buried insulating layer135may be selectively further interposed between a bottom of the control gate electrode140and the semiconductor substrate105. In more detail, the buried insulating layer135may be formed on the blocking insulating layer130. The buried insulating layer135may be thicker than the gate insulating layer120, and thus a channel may not be formed in a portion of the semiconductor substrate105underneath the control gate electrode140. The buried insulating layer135may include an oxide layer, for example.

The gate insulating layer120may allow tunneling of charges, and thus may include, for example, an oxide layer, a nitride layer, and/or a high dielectric constant layer. The blocking insulating layer130may inhibit movement of charges between the storage node layer125and the control gate electrode140, and thus may include, for example, an oxide layer, a nitride layer, and/or a high dielectric constant layer. According to an example embodiment, the high dielectric constant layer may be defined as an insulating layer having a greater dielectric constant than the oxide layer and the nitride layer.

The storage node layer125may store charges and include, for example, a silicon nitride layer, metal or silicon dots, and/or metal or silicon nano-crystals. In particular, the storage node layer125may locally trap charges.

According to an example embodiment, the gate insulating layer120, the storage node layer125, and the blocking insulating layer130may be interposed between the first and second sides of the control gate electrode140and the semiconductor substrate105and may extend onto the semiconductor substrate105. However, portions of the gate insulating layer120, the storage node layer125, and the blocking insulating layer130extending onto the semiconductor substrate105may be omitted according to another example embodiment. Further, each of the gate insulating layer120, the storage node layer125, and the blocking insulating layer130may be divided into two portions by the control gate electrode140.

A mask insulating layer110may be interposed between the gate insulating layer120and an upper surface of the semiconductor substrate105according to an example embodiment. However, according to another embodiment, the mask insulating layer110may be replaced with another appropriate insulating layer or may be omitted.

Dopant may be doped into the semiconductor substrate105to form the first and second dopant doping regions153and157according to an example embodiment. For example, if the semiconductor substrate105is doped with p-type dopant, the first and second dopant doping regions153and157may be doped with n-type dopant. Alternatively, if the semiconductor substrate105is doped with n-type dopant, the first and second dopant doping regions153and157may be doped with p-type dopant. The first and second dopant doping regions153and157may extend from the surface of the semiconductor substrate105to desired and/or predetermined depths. The first dopant doping regions153may be adjacent to the first side of the control gate electrode140, and the second dopant doping regions157may be adjacent to the second side of the control gate electrode140.

The first dopant doping regions153may alternate with the second dopant doping regions157. As such, one of the second dopant doping regions157may be disposed between two adjacent first dopant doping regions153. Stated differently, each of the second dopant doping regions157may be arranged in a region on the second side of the control gate electrode140that is adjacent to at least one of the plurality of first dopant doping regions153. Further restated, each of the second dopant doping regions157may be arranged on the second side of the control gate electrode140and across from a region on the first side of the control gate electrode140that is interposed between two adjacent first dopant doping regions153. Further, the first and second dopant doping regions153and157may be disposed at the same distance, and thus, each of the second dopant doping regions157may be disposed between two first dopant doping regions153.

The first dopant doping regions153may alternate with the second dopant doping regions157near opposite sides of the control gate electrode140. The first dopant doping regions153may alternate with the second dopant doping regions157in the direction in which the control gate electrode140extends. Thus, integration of the non-volatile memory device according to an example embodiment may be double that of the conventional non-volatile memory device illustrated inFIG. 1. Furthermore, a short channel effect can be improved. In other words, in the non-volatile memory device according to an example embodiment, may include two unit cells the amount of space occupied by a single unit cell of the conventional non-volatile memory device illustrated inFIG. 1. Since the first dopant doping regions153alternate with the second dopant doping regions157according to an example embodiment, widths of the first channel regions154between the first dopant doping regions153and the second channel regions158between the second dopant doping regions157may be kept relatively wide. The improvement of the short channel effect significantly contributes to improving the reliability of an example embodiment of a non-volatile memory device as compared to conventional non-volatile memory devices.

The first dopant doping regions153may be connected to a plurality of first bit line electrodes172, and the second dopant doping regions157may be connected to a plurality of second bit line electrodes177according to an example embodiment. For example, the first bit line electrodes172may include first plug portions160and first line portions170, and the second bit line electrodes177may include second plug portions165and second line portions175.

The first plug portions160may be recessed into the first dopant doping regions153, and the second plug portions165may be recessed into the second dopant doping regions157. The first line portions170may be connected to the first plug portions160, and the second line portions175may be connected to the second plug portions165. Further, the first and second line portions170and175may extend across the control gate electrode140. Depths of the first and second plug portions160and165may be modified within a range of being defined in the first and second dopant doping regions153and157.

According to an example embodiment, the first and second plug portions160and165may include, for example, polysilicon, metal, and/or metal silicide; and the first and second line portions170and175may include, for example, polysilicon, metal, and/or metal silicide. In this case, the first and second bit line electrodes172and177may have very low electrical resistances compared to conventional buried bit line regions. An interlayer insulating layer145may be interposed between the semiconductor substrate105and the first and second bit line electrodes172and177according to an example embodiment.

In the non-volatile memory device according to an example embodiment, two adjacent first bit line electrodes172or two adjacent second bit line electrodes177may be selected to address a unit cell. For example, charges of the first or second channel regions154or158may be injected into the storage node layer125using a hot carrier injection method to perform a program operation. The storage node layer125may be used as a local charge trap layer. Thus, unit cells may change a direction of a current flowing in the first channel regions154or a direction of a current flowing in the second channel regions157to process 2-bit data.

It is obvious that reading and erasing operations may be easily performed according to a method known by those of ordinary skill in the art and thus, these reading and erasing operations will not be further discussed in this disclosure for the sake of brevity.

FIG. 5is a perspective view of a non-volatile memory device according to another example embodiment. The non-volatile memory device illustrated inFIG. 5is the same as the non-volatile memory device illustrated inFIGS. 1 through 3except that a control gate electrode in the non-volatile memory device ofFIG. 5has a two-layer structure. Thus, descriptions of elements common to the example embodiment illustrated inFIGS. 1 through 3and the example embodiment illustrated inFIG. 5are not repeated for the sake of brevity.

Referring toFIG. 5, lower and upper control gate electrodes140aand140bare recessed into a semiconductor substrate105to be sequentially stacked. A lower buried insulating layer135amay be interposed between a bottom of the lower control gate electrode140aand the semiconductor substrate105, and an upper buried insulating layer135bmay be interposed between the lower and upper control gate electrodes140aand140b.

In the example embodiment of the non-volatile memory device illustrated inFIG. 5, charges may be locally stored in a storage node layer125adjacent to first and second sides of the lower and upper control gate electrodes140aand140b. Thus, integration of the non-volatile memory device illustrated in FIG. may be double that of the non-volatile memory device illustrated inFIGS. 1 through 3.

FIG. 6is a plan view of a non-volatile memory device according to yet another example embodiment. This example embodiment of the non-volatile memory device may have a structure in which a plurality of non-volatile memory devices as illustrated inFIGS. 1 through 3are arrayed and thus, the number of control gate electrodes is increased. It should be understood by one skilled in the art that the non-volatile memory device ofFIG. 6has a structure in which a plurality of non-volatile memory devices as illustrated inFIG. 3are repeatedly arrayed. Thus, descriptions of similar elements in the previously described example embodiments are not repeated for the sake of brevity.

Referring toFIG. 6, a plurality of control gate electrodes140are disposed at desired and/or predetermined distances from one another. The control gate electrodes140are recessed in a semiconductor substrate105. First dopant doping regions153are located and/or defined in the semiconductor substrate105along first sides of the control gate electrodes140, and second dopant doping regions157are located and/or defined in the semiconductor substrate105along second sides of the control gate electrodes140.

For example, the first dopant doping regions153may be disposed in a plurality of rows along the first sides of the control gate electrodes140, and the second dopant doping regions157may be disposed in a plurality of rows along the second sides of the control gate electrodes140. The first dopant doping regions153alternate with the second dopant doping regions157near opposite sides of the control gate electrodes140in the direction in which the control gate electrodes140extend.

First bit line electrodes172, including first line portions170and first plug portions160, may connect the first dopant doping regions153disposed in the same column. In other words, the first line portions170may extend across the control gate electrodes140to connect the first plug portions160disposed in the same column. Similarly, second bit line electrodes177, including second line portions175and second plug portions165, may connect the second dopant doping regions157disposed in the same column. In other words, the second line portions175may extend across the control gate electrodes140to connect the second plug portions165disposed in the same column.

The example embodiment of the non-volatile memory device illustrated inFIG. 6may be referred to as a NOR structure or an AND structure. In other words, two of the first bit line electrodes172or two of the second bit line electrodes177may be selected, and one of the control gate electrodes140may be selected to operate a unit cell. In the NOR structure, the first and second bit line electrodes172and177disposed in odd-numbered or even-numbered rows may be grounded.

FIGS. 7 through 13are perspective views illustrating an example embodiment of a method of fabricating a non-volatile memory device. Referring toFIG. 7, a mask insulating layer110is formed on a semiconductor substrate105. The mask insulating layer110may include a nitride layer, for example. The mask insulating layer110may be used as an etching protecting layer to etch an exposed portion of the semiconductor substrate105so as to form a first trench115.

Referring toFIG. 8, a gate insulating layer120is formed on the exposed portion of the semiconductor substrate105in the first trench115. The gate insulating layer120may be formed using a thermal oxidation method or a chemical vapor deposition (CVD) method, for example. The gate insulating layer120may extend onto the mask insulating layer110according to an example embodiment.

A storage node layer125is formed on the gate insulating layer120. The thickness of the storage node layer125may be controlled so that the storage node layer125does not completely fill the first trench115. A blocking insulating layer130is formed on the storage node layer125. The storage node layer125and the blocking insulating layer130may be formed using a CVD method, for example.

A buried insulating layer135is formed on the blocking insulating layer130to fill the first trench115according to an example embodiment. The buried insulating layer135may be formed to a desired and/or predetermined thickness using a CVD method, for example. The buried insulating layer135may then be planarized. The buried insulating layer135may have etching selectivity with respect to the blocking insulating layer130. For example, if the blocking insulating layer130includes a nitride layer or a high dielectric constant layer, the buried insulating layer135may include an oxide layer.

Referring toFIG. 9, the buried insulating layer135is selectively etched to define the buried insulating layer135in a lower part of the first trench115. The buried insulating layer135may be dry or wet etched. The buried insulating layer135may be thicker than the gate insulating layer120so that a channel is not formed in a portion of the semiconductor substrate105underneath a bottom of the first trench115according to an example embodiment.

Referring toFIG. 10, a control gate electrode140is formed on the buried insulating layer135to fill at least a portion of the first trench115. For example, a conductive layer may be formed to fill the first trench115and then planarized or etched to a desired and/or appropriate height so as to form the control gate electrode140.

As illustrated inFIG. 10, an interlayer insulating layer145is formed on the control gate electrode140. The interlayer insulating layer145may extend outside the first trench115to cover the blocking insulating layer130. The interlayer insulating layer145may include an oxide layer and/or a nitride layer, for example. The interlayer insulating layer145may be formed using a CVD method.

Referring toFIG. 11, a plurality of second trenches150are formed in the semiconductor substrate105along a first side of the control gate electrode140, and a plurality of third trenches155are formed in the semiconductor substrate105along a second side of the control gate electrode140. The third trenches155alternate with the second trenches150in the direction in which the control gate electrode140extends. The second and third trenches150and155may be formed at the same time or in a random sequence according to an example embodiment.

For example, the interlayer insulating layer145, the blocking insulating layer130, the storage node layer125, the gate insulating layer120, and the semiconductor substrate105may be sequentially etched to form the second and third trenches150and155.

First dopant doping regions (refer to reference numeral153ofFIG. 4) are formed in portions of a surface of the semiconductor substrate105exposed by the second trenches150, and second dopant doping regions (refer to reference numeral157ofFIG. 4) are formed in portions of the surface of the semiconductor substrate105exposed by the third trenches155. For example, dopants may be doped into the exposed surface of the semiconductor substrate105to a desired and/or predetermined depth to define the first and second dopant regions in the semiconductor substrate105. The dopants may be doped using an ion implantation method, for example. The first and second dopant doping regions may be formed at the same time or in a random sequence.

Referring toFIG. 12, a plurality of first plug portions160are formed to at least partially fill the second trenches150, and a plurality of second plug portions165are formed to at least partially fill the third trenches155. The first plug portions160may be recessed into the first dopant doping regions, and the second plug portions165may be recessed into the second dopant doping regions. For example, a conductive layer may be formed to fill the second and third trenches150and155and then planarized to form the first and second plug portions160and165.

Referring toFIG. 13, a plurality of first line portions170are formed to be respectively connected to the first plug portions160and extend across the control gate electrode140. A plurality of second line portions175are formed to be respectively connected to the second plug portions165and extend across the control gate electrode140. First bit line electrodes172include the first plug portions160and the first line portions170, and second bit line electrodes177include the second plug portions165and the second line portions175.

According to another example embodiment, the first and second dopant doping regions153and157may be formed before the second and third trenches150and155illustrated inFIG. 11are formed. In this case, the second and third trenches150and155may be formed to be defined in the first and second dopant doping regions.

According to still another example embodiment, the mask insulating layer110illustrated inFIG. 7may be removed after the first trench115is formed. In this case, the gate insulating layer120illustrated inFIG. 8may be formed in the first trench115and an upper surface of the semiconductor substrate105.

According to another example embodiment, the process of forming the control gate electrode140may be repeated to form control gate electrodes (refer to reference numerals140aand140bofFIG. 5) having a multiple layer structure. For example, the process of forming the control gate electrode140may be repeated to form control gate electrodes having a two-layer structure as illustrated inFIG. 5. The control gate electrodes of the two-layer structure include a lower control gate electrode and an upper control gate electrode. In this case, an upper buried insulating layer135bmay be further formed on the lower control gate electrode before the upper control gate electrode is formed.

According to another example embodiment, the method described with reference toFIGS. 7 through 13may be applied to the non-volatile memory device ofFIG. 6.

As described above, in a non-volatile memory device and a method of fabricating the non-volatile memory device according to example embodiments, first dopant doping regions can alternate with second dopant doping regions beside opposite sides of a control gate electrode. Thus, integration of the non-volatile memory device according to example embodiment may be at least about twice that of a conventional non-volatile memory device.

Also, widths of first and second channel regions can be kept large. Thus, a short channel effect of example embodiments of a non-volatile memory device can be improved as compared with a conventional non-volatile memory device. As a result, reliability of the non-volatile memory device according to example embodiments can be improved as compared with a conventional non-volatile memory device.

Furthermore, example embodiments of a non-volatile memory device may include bit line electrodes having lower resistances than bit line electrodes of a conventional non-volatile memory device.

While example embodiments have been particularly shown in the drawings and described above, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of this disclosure.