ESD protection device

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

CROSS REFERENCE TO RELATED APPLICATION(S)

The present application claims priority to International Patent Application No. PCT/IB2015/002294, entitled “ESD PROTECTION DEVICE,” filed on Oct. 2, 2015, the entirety of which is herein incorporated by reference.

FIELD OF USE

The present disclosure relates generally to semiconductor devices, and more specifically, to semiconductor devices providing protection from electrostatic discharge (ESD).

BACKGROUND

Integrated circuits (ICs) and electronic assemblies, and the devices therein, are at risk of damage due to electrostatic discharge (ESD) events. This is well known in the art. It is therefore commonplace to provide an ESD protection clamp (voltage limiting device) across the terminals of such devices, IC's and electronic circuits or assemblies. As used herein, the term integrated circuit and the abbreviation IC are intended to refer to any type of circuit or electronic assembly whether formed in a monolithic substrate or as individual elements or a combination thereof.

DETAILED DESCRIPTION

In a first aspect, an ESD protection device coupled between a first terminal and a second terminal of an integrated circuit is proposed. The ESD protection device comprises a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by a ring region which is an undoped or lightly doped ring-shaped region and which is surrounded by the outer region. The ESD protection device further comprises a semiconductor region over the buried layer; a first well of the first conductivity type in the semiconductor region, extending from a surface of the semiconductor region to a main region of the outer region of the buried layer; a first transistor in the semiconductor region having an emitter coupled to the first terminal; and a second transistor in the semiconductor region having an emitter coupled to the second terminal. The first well forms a collector of the first transistor and a collector of the second transistor. The buried layer is located below at least one of the first transistor and the second transistor. A high holding voltage Vh is achieved by a suitable choice of the width of the ring region.

A second aspect concerns a method for forming an ESD protection device coupled between a first terminal and a second terminal of an integrated circuit. The method comprises forming a ring-shaped masking layer over a first region of a first semiconductor layer, wherein the ring-shaped masking layer masks a ring region located in the first region of the first semiconductor layer. A dopant of a first conductivity type is implanted into the first semiconductor layer using the ring-shaped masking layer. The implanting results in a heavily doped inner region and a heavily doped outer region in the first semiconductor layer, wherein the ring region surrounds the inner region and the outer region surrounds the ring region. A second semiconductor layer is formed over the first semiconductor layer and the inner region and the outer region. A first well of the first conductivity type is formed in the second semiconductor layer, extending from a surface of the second semiconductor layer to a main region of the outer region. A first transistor in the second semiconductor layer is formed over the first semiconductor layer, the first transistor having an emitter coupled to the first terminal. A second transistor is formed in the second semiconductor layer over the first semiconductor layer. The second transistor has an emitter coupled to the second terminal. The first well forms a collector of the first transistor and a collector of the second transistor. A high holding voltage Vh is achieved by a suitable choice of the width of the ring-shaped masking layer.

ESD protection clamps are circuit elements used to protect integrated circuit (IC) devices from voltage and current spikes that may be associated with an electrostatic discharge. To protect an IC device, an ESD clamp is connected between an input or output terminal of the device and a ground or common terminal. During normal operation, the ESD clamp does not conduct. But when subjected to an excessive voltage, the ESD clamp becomes conductive, conducting current to ground and limiting voltage to a desired safe level, thereby protecting the IC to which the ESD clamp is connected.

Generally, ESD clamps can be connected across any terminals of an IC that constitutes the electronic device to be protected. Accordingly, any reference herein to a particular input or output terminal of an IC is intended to include any and all other terminals of electronic circuits, not merely those used for input or output signals. With respect to structures or elements used for ESD protection, the terms device, clamp and transistor are used interchangeably.

FIG. 1is a graph showing a transmission line pulse (TLP) current (I) versus voltage (V) for a typical electrostatic discharge (ESD) protection device. In operation, as the voltage applied to the terminals is increased, very little current flows through the ESD protection device until the triggering voltage Vt1at point31is reached. The value Vt1refers to forward triggering voltage. Upon reaching the triggering voltage, the ESD protection device turns on and the voltage drops to the holding voltage Vh at point32, in which the current flow through the device is Ih. The difference between the triggering voltage and the holding voltage is referred to as the snapback voltage, denoted Vsb. Depending upon the internal impedance of the voltage source, current and voltage may further increase to point33at current It2and voltage Vt2, beyond which destructive failure may occur leading to further current increase accompanied by voltage decrease. Generally, It2indicates the current capability of the ESD protection device before the device is thermally damaged.

A similar explanation applies to the reverse direction in a bi-polarity or bi-directional ESD protection device in which very little current flows through the ESD protection device until a reverse triggering voltage Vt1Ris reached. At this point, the ESD protection device turns on and the voltage drops to a reverse holding voltage VhR. The reverse snapback voltage, VsbR, is the difference between the reverse triggering voltage and the reverse holding voltage. As will be described in more detail below, the forward behavior and reverse behavior of a bi-directional ESD protection device may not be symmetrical. Accordingly, the ESD protection device may be optimized for either a forward or reverse ESD event.

In high-voltage or high-power ESD clamp implementations (e.g., those used in the automotive industry) ESD clamps having a higher snapback voltage (Vsb) generally provide improved latch-up immunity. Typically, the snapback voltage and holding voltage of an ESD protection device is a constant voltage which is defined by the process technology used in manufacturing the ESD protection device. However, in some applications, this holding voltage value is not sufficient. For example, in one application, an electrical disturbance from the battery, such as for a reverse double battery event, may be on the order of 28 V. In this situation, the holding voltage needs to remain above 28 V in order for the ESD device to remain within allowable limits. Therefore, in one embodiment, a buried N type layer, as will be described below, is used to control or adjust the holding voltage by controlling the internal resistance of the ESD protection device.

FIG. 2is a cross-sectional view of an ESD protection device100implemented in a semiconductor substrate at an initial stage in processing in accordance with an embodiment of the invention. ESD protection device100is a dual polarity (bi-directional) ESD clamp device for use in protecting electronic devices and circuits. As will be described below, the ESD protection device will include two mirrored and interconnected transistors124and126(seeFIG. 7) and may be incorporated into an ESD protection clamp.

Illustrated inFIG. 2is a substrate102on which ESD protection device100is formed. Substrate102is a semiconductor substrate and is provided with a buried oxide layer (BOX)104. Depending upon the implementation, substrate102may be either of N-type or P-type. Substrate102includes a region12in which a first of the two mirrored interconnected transistors, transistor124, will be formed and a region14in which a second of the two mirrored interconnected transistors, transistor126, will be formed. Buried oxide layer104provides electrical isolation to devices formed over substrate102.

As used herein, the term “semiconductor” is intended to include any semiconductor whether single crystal, poly-crystalline or amorphous and to include type IV semiconductors, non-type IV semiconductors, compound semiconductors as well as organic and inorganic semiconductors. Further, the terms “substrate” and “semiconductor substrate” are intended to include single crystal structures, polycrystalline structures, amorphous structures, thin film structures, layered structures as, for example and not intended to be limiting, semiconductor-on-insulator (SOI) structures, and combinations thereof. For convenience of explanation and not intended to be limiting, semiconductor devices and methods of fabrication are described herein for silicon semiconductors but persons of skill in the art will understand that other semiconductor materials may also be used. Additionally, various device types and/or doped semiconductor regions may be identified as being of N type or P type for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either N or P type and the second type then is either P or N type.

Still referring toFIG. 2, a semiconductor layer105is formed over BOX layer104. In one embodiment, semiconductor layer105is epitaxially deposited over BOX layer104and may be either N-type or P-type doped. In one embodiment, semiconductor layer105has a thickness in a range of 1 micrometer (μm) to 4 μm. As will be described below, an N-type buried layer (NBL) will be formed in semiconductor layer105using an appropriate masking layer and implantation. Adjacent regions12and14of substrate102may also be referred to as a first region and a second region, respectively, of semiconductor layer105.

FIG. 3illustrates ESD protection device100at a subsequent stage in processing in accordance with one embodiment. A ring-shaped masking layer16is formed over semiconductor layer105and includes openings17,18,19. In one embodiment, ring-shaped masking layer16is formed by forming a photoresist layer over semiconductor layer105and then patterning the photoresist layer to form openings17-19. Ring-shaped masking layer16covers a ring-shaped region of semiconductor layer105in the first region12and has openings17and19over semiconductor layer105in the first region12and an opening18over semiconductor layer105in the second region14. An implant30is then injected or diffused into semiconductor layer105via the openings17-19to form doped regions within semiconductor layer105as defined by openings17-19. Implant30enters semiconductor layer105in those regions exposed by the photoresist material and is blocked from entering semiconductor layer105in those regions covered by photoresist material.

In one embodiment, implant30is performed using an N-type dopant such as antimony, phosphorus, or suitable combinations thereof. In one embodiment, implant30has a concentration of 2×1015cm−2.

FIG. 4illustrates ESD protection device100at a subsequent stage in processing, after removal of ring-shaped masking layer16. Implant30into semiconductor layer105results in highly doped regions147-149which are aligned to the openings in ring-shaped masking layer16, such as openings17-19. After implant30, dopants may laterally diffuse from the highly doped regions by about, e.g., 0.5 um to 1 um laterally, resulting in a laterally diffused region150around the highly doped regions. Laterally diffused region150has a lower dopant concentration than the highly doped regions. For example, the highly doped regions may have a dopant concentration of about 1×1016cm−3to about 1×1019cm−3, while laterally diffused region150has a dopant concentration of about 5×1015cm−3to about 1×1018cm−3

Doped regions147-149and laterally diffused region150form an N-type buried layer (NBL)108. Due to ring-shaped masking layer16, NBL108is formed throughout in region14but only partly in region12. In region12, semiconductor layer105includes a ring-shaped undoped region110(ring region) resulting from ring-shaped masking layer16. Therefore, NBL108may be described as having an opening in region12in which an undoped portion of semiconductor layer105is in direct contact with BOX layer104. In region14, NBL108provides a continuous doped layer. As will be discussed below, the undoped region in semiconductor layer105allows for NBL108to have an increased electrical resistance.

In alternate embodiments, a P-type buried layer, similar to NBL108, may be formed in which implant30is performed using a P-type dopant and ring-shaped masking layer16.

FIG. 5illustrates a top down view of a portion of ESD protection device100ofFIG. 4in accordance with various embodiments. Openings17-19of ring-shaped masking layer16, which define the highly doped regions147-148, include an inner opening17and outer openings18and19. Outer openings18and19are mutually connected and constitute a single outer opening18,19separate from and surrounding the inner opening17. For example, as can be understood fromFIG. 5, inner opening17may be rectangular.

The ring-shaped masking layer16results in a highly doped region147,148,149which includes an outer region148,149and an inner region147. Outer region148,149includes a main region148located in region14and an edge region149located in region12. Inner region147is located as an isolated island within outer region148,149. Inner region147is surrounded by ring region110which separates inner region147from outer region148,149. Ring region110is a ring-shaped, undoped region of semiconductor layer105. In the example, ring region110is the only undoped region of semiconductor layer105. Inner region147, outer region148,149, and ring region110are located in a plane parallel to a major surface103of NBL108. Note that major surface103of NBL108is parallel to a major surface of ESD protection device100(and also corresponds to a major surface of semiconductor layer105in which NBL108is formed) and is parallel to the plane of projection ofFIG. 5. Therefore, the major axes of inner region147, the major axis of the outer region148,149, and any diameter of the ring region110are parallel to major surface103of NBL108. Laterally diffused region150is located at the borders of highly doped regions147-149in a plane parallel to major surface103.

Undoped ring region110has a width WR, which may be either constant or variable to some extent along the inner or outer circumference of ring region110. In a good approximation, the width WRcan be regarded as constant. In another embodiment, the width WRdenotes an average width of the ring region110, e.g., when the local width is averaged along the inner or outer circumference of the ring region110. The inner circumference of ring region110is the outer circumference of inner region147. The outer circumference of ring region110is the inner circumference of outer region148,149. For example, 0.5≦μm WR≦3.0 μm.

The ring-shaped masking layer16has a width WM, determining the resulting width WRof the ring region110. In one embodiment, the width WMof ring-shaped masking layer16is sufficiently large to prevent the lateral diffusion between adjacent highly doped regions to overlap, so as to provide the ring region110within NBL108. In one such embodiment, the width WMof ring-shaped masking layer16is at least 0.5 μm. In another embodiment, the width WMis quite small (e.g., less than 0.5 μm) and, as a consequence, the lateral diffusion between adjacent highly doped regions meets or overlaps, resulting in a lightly doped ring region consisting of laterally diffused region150. Laterally diffused region150may be referred to as lightly doped ring region150in this case.

FIG. 6illustrates ESD protection device100at a subsequent stage in processing. After formation of the doped regions in semiconductor layer105to form NBL108, a semiconductor layer111is formed over semiconductor layer105and NBL108. In one embodiment, semiconductor layer111is formed by epitaxial deposition of silicon and may be either N-type or P-type doped. An example doping concentration range of region111is about 1×1015cm−3to about 8×1015cm−3. As such, layer111may be relatively lightly doped. The thickness of layer111may, for example, be in the range of 3 μm to about 9 μm.

As shown inFIG. 6, NBL108is not continuous through ESD protection device100. Instead, NBL108, once formed, defines the ring region110. That is, ring region110is located within an opening of NBL108in region12. As such, NBL108does not form a continuous layer of N-type material formed across the surface of BOX layer104. NBL108is continuous in region14but not in region12. The combination of semiconductor layer111and the portions of semiconductor layer105which do not include NBL108(such as the portion of semiconductor layer105in ring region110) may be referred to as a semiconductor region112(seeFIG. 7). As such, region112is formed over NBL108and BOX layer104. By ring region110, region112comes into contact with BOX layer104.

As mentioned above, the gap between inner region147and outer region148,149can be small enough to allow the NBL lateral diffusions to meet in the middle to form a lighter doping NBL extension, e.g., in the form of a laterally diffused region150which will be ring-shaped. Laterally diffused region150may replace ring region110without qualitatively changing the operating characteristics of ESD protection device100.

FIG. 7illustrates ESD protection device100at a subsequent stage in processing in which transistor124of ESD protection device100is formed in region12and transistor126of protection device100is formed in region14. After formation of semiconductor layer111which results in region112, a number of deep N-well regions114are formed in region112. N well regions114may be doped with arsenic, phosphorus, antimony, or suitable combinations thereof. The peak doping density for N-well regions114may be in a range of about 1×1017cm−3to about 1×1019cm−3although other doping densities may also be used N-well regions114are formed to be in contact (and, therefore, in electrical communication with) NBL108. Note that N-well regions114are in contact (and in electrically communication with) highly doped regions of NBL108, such as regions149,147, and148. In one embodiment, N-well regions114are formed such that the entire bottom of each deep N-well region contacts a highly doped region of NBL108and thus does not contact laterally diffused region150.

After formation of N-well regions114, a number of shallow trench isolation (STI) structures120are formed over a surface of device100. The depth of STI structures120is usually in the range of about 0.05 μm to about 1 μm, more conveniently about 0.2 μm to about 0.5 μm, although thicker or thinner STI structures may also be used.

To fully isolate devices formed over substrate102, deep trench isolation (DTI) regions106may be formed to provide electrically insulating walls around the devices. DTI regions106include dielectric materials that provide lateral electrical isolation to the device. Deep trench isolation regions may be provided extending from the surface of ESD device100to BOX104. For example, DTI regions106extend through NBL108to BOX104.

P-well regions118are formed within region112. P-well regions118may be doped with boron or other suitable dopants. The peak doping density for P-well regions118is in the range of about 1×1016cm−3to about 1×1019cm−3. The depth of P-well regions118may be in the range of 0.3 μm from the surface of device100, to any location above or in contact with NBL108, but other depth may also be used.

A number of silicide block regions123can be formed over the surface of device100to prevent reaction with a silicide forming conductor (that may be deposited over the device at a later time). In one embodiment, the silicide block regions123include a first layer of silicon oxide overlaying the surface, followed by a second layer of silicon nitride overlapping the first layer. While in another embodiment, the silicide block regions123may be omitted. In some cases, the silicide block regions123are replaced using shallow trench isolation (STI).

N+ doped contact regions122are formed in P-well regions118. N+ contact regions122include relatively shallow, but highly doped N-type regions and may include phosphorus, arsenic, or suitable combinations thereof as dopants. The peak doping density for N+ contact regions122can be in the range of about 5×1019cm−3to about 1×1021cm−3. The depth of N+ contact regions122can range from about 0.05 μm to about 0.3 μm. Other dopants, density and depths, though, may also be used.

P+ doped contact regions121are formed in P-well regions118to make electrical contact with P-well regions118. P+ contact regions121include relatively shallow, but highly doped P regions and may include boron as a dopant. The peak doping density for P+ contact regions121is in the range of about 5×1019cm−3to about 1×1021cm−3. The depth of P+ contact regions120can range from about 0.05 μm to about 0.3 μm. But other dopants, density and depths may also be used.

In the configuration shown inFIG. 7, the structure forms two NPN bipolar junction transistors124and126, in which transistor124is formed in region12and transistor126in region14. To illustrate the location and electrical interconnection of transistors124and126within the device,FIG. 7includes a dashed schematic overlay showing the approximate location of a number of transistor structures within device100. In the overlay, transistor124is represented by transistor Q1and transistor126is represented by transistor Q2. InFIG. 7, transistors Q1, Q2, Q3(described below), and their interconnections are only included for reference and do not form any portion of the structure of device100. InFIG. 7, N+ doped regions122serve as the emitters of transistors124and126. P-well regions118serve as the bases of transistors124and126. The N-well region128(and connected NBL region108) serves as the shared collector of transistors124and126. The base and emitter terminals (130and132, respectively) of transistor124are tied together to form cathode terminal138for ESD protection device100. The base and emitter terminals (134and136, respectively) of transistor126are tied together to form anode140terminal for ESD protection device100. In this configuration, a parasitic PNP transistor structure is formed in device100at the approximate location of transistor Q3inFIG. 7. N-well region128and the adjoining NBL region108serve as the base of the transistor structure Q3, and P-well regions118serve as the emitter and collector of transistor structure Q3. N-well region128also serves as a collector of transistor124and as a collector of transistor126. In the present device, the main region148of outer region148,149of NBL108formed under transistor126enables the operation of the parasitic PNP transistor structure Q3.

During a forward ESD event, when a positive voltage is applied to terminal140with respect to terminal138, transistor126acts as a forward-biased diode, and transistor124's base-collector junction is reverse biased. When a sufficiently large voltage is applied to terminal140with respect to terminal138, intermediate portion142of region112becomes depleted of free carriers. As the applied voltage increases to Vt1, avalanche breakdown occurs across the base-collector spacing in portion142of region112. Thus, the (forward) triggering voltage Vt1at which avalanche breakdown occurs in transistor124can depend upon the base-collector spacing between P-well118and N-well128within transistor124; the larger the spacing, the higher Vt1and, conversely, the smaller the spacing, the smaller Vt1. As the applied voltage increases above Vt1, the avalanche breakdown generates carriers turning on NPN transistor124(Q1). NPN transistor124(Q1) then couples with PNP transistor structure Q3so that the base of transistor124(Q1) also serves as and connects to the collector of transistor structure Q3, and the collector of transistor124(Q1) serves as and connects to the base of transistor structure Q3. The coupling between transistor124and transistor structure Q3forms a parasitic silicon controlled rectifier (SCR). The parasitic SCR effects provide strong current capability for the device after the device snaps back and begins conducting.

Conversely, during a reverse ESD event, when a negative voltage is applied to terminal140with respect to terminal138, transistor124acts as a forward-biased diode and transistor126's base-collector junction is reverse biased. This example is illustrated by the overlay schematic inFIG. 8illustrating a forward-biased diode D1in place of transistor Q1. When a positive voltage with sufficiently large amplitude is applied to terminal138with respect to terminal140, intermediate portion144of region112becomes depleted of free carriers. As the applied voltage increases to Vt1R, avalanche breakdown occurs across the base-collector spacing in portion144of region112. Thus, the reverse triggering voltage Vt1Rat which avalanche breakdown occurs in transistor126can depend upon the base-collector spacing between P-well118and N-well128within transistor126; the larger the spacing, the higher Vt1Rand, conversely, the smaller the spacing, the smaller Vt1R. As the applied voltage increases above Vt1R, the avalanche breakdown generates carriers to turn on NPN transistor126(Q2). NPN transistor126(Q2) then couples with PNP transistor structure Q3in a way that the base of transistor126(Q2) also serves as and connects to the collector of transistor structure Q3, and the collector of transistor126(Q2) serves as and connects to the base of Q3. The coupling between transistor126and transistor structure Q3also forms a parasitic SCR. The parasitic SCR effects provide strong reverse current capability for the device after the device snaps back and start conducting.

The forward and reverse triggering voltages Vt1and Vt1Rmay be substantially the same or different depending on whether the base-collector spacings in portions142and144are substantially the same or different.

In the arrangement shown inFIG. 7, transistor124controls the forward triggering of ESD protection device100during a forward ESD event. The parasitic SCR formed by transistor124and transistor structure Q3controls the forward holding voltage of ESD protection device100after the applied voltage exceeds Vt1for the device (and so the device begins to snapback and conduct current). Transistor126controls the reverse triggering of ESD protection device100during a reverse ESD event. The parasitic SCR formed by transistor126and transistor structure Q3controls the reverse holding voltage of ESD protection device100after the applied voltage exceeds Vt1Rfor the device (and the device begins to snapback and conduct current).

In a conventional dual-polarity ESD protection device having a full, uniformly implanted NBL, a substantial amount of current flows through the NBL that is located under each transistor. However, in ESD device100as illustrated inFIGS. 7 and 8, NBL108is either not present between inner region147and outer region148,149(resulting in ring region110and laterally diffused region150) or present between inner region147and outer region148,149but only with a relatively low doping concentration (resulting in laterally diffused region150but not necessarily in ring region110). As a result, after the device is triggered, relatively little current flows through NBL108for transistor124. This behavior increases the forward holding voltage, Vh, of the device, improving its performance for a forward ESD event. Forward and reverse operations can be symmetrical.

FIG. 9schematically shows an example of an embodiment of an ESD protection device200produced on the basis of the device fromFIG. 6. ESD protection device200is generally similar to ESD protection device100fromFIG. 7. Only differences over ESD protection100will be described in the following.

ESD protection device200includes a first P+ trigger contact region125at the top surface of ESD protection device200and in direct contact with P-well region118in region12and with intermediate portion142of semiconductor region112. Intermediate portion142of semiconductor region112extends through to the top surface of device200, i.e. to the surface on which silicide block regions123are disposed. At the top surface of device200, intermediate portion142of semiconductor region112has a width Sp. Intermediate portion142of semiconductor region112thus isolates first P+ trigger region125, which is in direct contact with P-well region118and intermediate portion142, from STI structure120. The width Sp of intermediate portion142of semiconductor region112can be approximately equal to the width WRof ring region110(seeFIGS. 5 and 6). This can result in a high holding voltage Vh. For example, the width Sp can be in the range of 0.8*WRto 1.2*WR(i.e. Sp=WR±20%).

ESD protection device200further includes a second P+ trigger region125at the top surface of ESD protection device200and in direct contact with P-well region118in region14and with intermediate portion144of semiconductor region112. Intermediate portion144of semiconductor region112extends through to the top surface of device200, i.e. to the surface on which silicide block regions123are disposed. At the top surface of device200, intermediate portion144of semiconductor region112has a width Spr. Intermediate portion144of semiconductor region112thus isolates second P+ trigger region125, which is in direct contact with P-well region118and intermediate portion144, from STI structure120. The width Spr of intermediate portion144of semiconductor region112can be approximately equal to the width WRof ring region110(seeFIGS. 5 and 6), as this can result in a high holding voltage Vh. For example, the width Spr can be in the range of 0.8*WRto 1.2*WR(i.e. Spr=WR±20%).

First and second P+ trigger regions125(located in regions12and14, respectively) can be relatively shallow but highly doped P regions and may include boron as a dopant. The peak doping density for P+ trigger regions125is in the range of about 5×1019cm−3to about 1×1021cm−3. The depth of P+ trigger regions125can range from about 0.05 μm to about 0.3 μm. But other dopants, density and depths may also be used.

FIG. 10schematically shows ESD protection device200during operation with a schematic overlay representing the flow of the holding current, of amplitude Ih, during a forward ESD event. In region14, the holding current passes mainly through anode140, P+ contact region121, P-well118, and portion148of outer region148,149of NBL108. From portion148of outer region148,149, a first part of the holding current continues through ring region110of semiconductor region112, inner region147of NBL108, semiconductor region112, P-well region118(in region12), N+ contact region122, and cathode138while a second part of the holding current continues through semiconductor region112, P-well region118(in region12), N+ contact region122, and cathode138without passing through inner region147. The width WRof ring region110can be chosen such that the first part Ih1of the holding current (which flows through the ring region110) has an amplitude Ih1in the range of 0.3*Ih to 0.7*Ih and that the second part Ih2of the holding current (which bypasses the ring region110) has an amplitude Ih2in the range of 0.3*Ih to 0.7*Ih (wherein it is understood that the sum of Ih1and Ih2does not exceed Ih). The applicant has carried out studies which suggest that choosing the ring width WRsuch that the first part Ih1and the second part Ih2of the holding current are approximately equal (e.g., 0.5<Ih1/Ih2<2) can result in a large holding voltage.

FIG. 11shows a diagram with current-vs-voltage graphs A (“Full NBL”), B (“No NBL”), and C (“NBL with Gap”) for three different ESD protection devices, along with a table indicating the holding voltage Vh, the triggering voltage Vt1, and the current capability It2determined from the graphs. Graph A refers to a first ESD protection device similar to ESD protection device200but including an NBL layer which is continuous through regions12and14. Graph B refers to a second ESD protection device similar to ESD protection device200but not having an NBL layer in device12(inner region147is absent in ESD protection device of graph B). Graph C refers to an ESD protection device like ESD protection device200described above. As seen, ESD protection200has a holding voltage Vh of 51.6 V. This is significantly higher than the holding voltages Vh=36.0 V and Vh=45.1 V of the first and second ESD protection devices, respectively.

Since ESD protection device100can be constructed using silicon-on-insulator fabrication process, the ESD protection device may be isolated by buried oxide layer (BOX) and deep trench isolation (DTI), as described above. This configuration allows the device to be stacked. This capability minimizes device footprint when a number of the ESD protection devices are stacked over one another. The stacking of the ESD protection devices allows for the formation of a single ESD protection clamp that includes a number of ESD protection devices and that can provide an increased Vh.

When stacked within an ESD protection clamp, two or more ESD protections devices are formed next to one another in a single substrate. The ESD protection devices are then connected in series (i.e., stacked) with the cathode of one ESD protection device being electrically connected to the anode of the next ESD device. The anode of the first ESD protection device in the stack provides a positive input or anode terminal for the ESD protection clamp. Similarly, the cathode of the last ESD protection device in the stack provides a negative input or cathode terminal for the ESD protection clamp. The positive and negative input terminals of the ESD protection clamp can then be connected to an IC device to provide protection thereto.

FIGS. 12A and 12B, for example, are cross-sectional views of an ESD protection clamp that includes two stacked ESD protection devices. InFIG. 12Atwo ESD protection devices100and100′ are connected in series, though other devices or clamps could include more than two series-connected ESD protection devices. In the arrangement shown inFIG. 12A, device100′ is the first ESD protection device in the stacked device and device100is the second ESD protection device.

Each of devices100and100′ inFIG. 12Ais configured in accordance with the example device100shown inFIG. 8 or 9. However, the DTI regions106of each device have been duplicated inFIG. 12A.FIG. 12Aalso shows the substrate310and BOX layer308over which each ESD protection device is formed.

Each of the devices100and100′ are electrically isolated by DTI regions106(DTI regions106surround device100and DTI regions106′ surround device100) from N type or P type region (formed by epitaxial deposition)306and in some embodiment P well region304. STI structure302is provided for additional isolation.

To interconnect the devices, cathode138′ of device100′ is connected to anode140of device100, thereby connecting devices100and100′ in series. The anode140′ of device100′ is connected to a first terminal (e.g., a positive terminal at Vpos) of IC device300. The cathode138of the stacked ESD protection device100is connected to a second terminal (e.g., a negative terminal at Vneg) of IC device300. In this configuration, the stacked ESD protection devices100and100′ operate as an ESD protection clamp to provide protection to IC device300.

FIG. 12Bis a cross-sectional view showing two stacked ESD protection devices100and100′, where the devices are isolated from one another using an alternative trench structure. InFIG. 12B, devices100and100′ ofFIG. 12Aare separated by a single DTI trench region312that provides electrical isolation between the two devices100and100′. In this arrangement, device100′ is the first ESD protection device in the stacked arrangement and device100is the second ESD protection device.

Again, the cathode138′ of device100′ is connected to the anode140of device100, connecting devices100and100′ in series. The anode140′ of device100′ is connected to a first terminal of IC device300, where IC device300is to be protected by the stacked ESD protection device. The cathode138of the stacked ESD protection device100is connected to a second terminal of IC device300.

Using the configuration shown inFIGS. 12A and 12Bany number of ESD protection devices can be combined, in series, to form an ESD protection clamp. The anode of the first ESD protection device in the stack and the cathode of the last ESD protection device in the stack can then be connected to an IC device to provide protection thereto.

When two or more ESD protection devices are stacked as shown inFIG. 12AorFIG. 12B, the holding voltage Vh of the entire stacked device is equal to the sum of the holding voltages of each of individual ESD protection devices100. As such, to provide a protection device that targets a holding voltage of 30 V, a stack that includes two or more ESD protection devices connected in series can be used. For example, the holding voltage of each individual ESD protection device may be approximately 15 V. In the example described above regarding the reverse double battery event of about 28 V, a holding voltage of 30 V remains within the allowable limit. The doping profile of NBL108can therefore be used to control the holding voltage of ESD protection devices, and ESD protection devices can be stacked in series as needed to provide the desired final holding voltage.

Therefore, by now it can be appreciated how the doping profile of a buried layer below one or both transistors of a bi-directional ESD protection device can be used to control the holding voltage of the ESD protection device. For example, a ring-shaped masking layer can be used for an implant into a semiconductor layer to form a buried layer having a heavily doped inner region and a heavily doped outer region, the inner region being surrounded by an undoped or lightly doped ring region. The ring region separates the inner region from the outer region. The electrical resistance between the inner region and the outer region can be controlled by the width WRof the ring region. The greater the width of the ring region, the larger the electrical resistance between the heavily doped inner region and the heavily doped outer region. In this manner, holding voltages of the ESD protection device can be controlled. A lightly doped ring region can result from lateral diffusion of the implant into the ring-shaped region that was covered by the ring-shaped masking layer. A lightly doped ring region can have generally the same effect as a strictly undoped ring region.

The preceding detailed description is exemplary in nature and is not intended to limit the invention or the application and uses of the same. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose.

Although the present disclosure describes specific examples, embodiments, and the like, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. For example, although the exemplary methods, devices, and systems described herein are in conjunction with a configuration for the aforementioned device, the skilled artisan will readily recognize that the exemplary methods, devices, and systems may be used in other methods, devices, and systems and may be configured to correspond to such other exemplary methods, devices, and systems as needed. Further, while at least one embodiment has been presented in the foregoing detailed description, many variations exist. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all of the claims.