Zero to one hundred and eight-degree active phase shifter for microwave frequencies

A zero to one hundred and eight-degree active phase shifter for microwave frequencies contains a differential input amplifier having an inverting output (.beta.V) and a non-inverting output (.alpha.V) and a first (T.sub.11, T.sub.12) and a second (T.sub.13, T.sub.14) output stage of the push-pull type realized with MES-transistors and each comprising an inverting input and a non-inverting input. The inverting output (.beta.V) of the input amplifier controls the inverting input (T.sub.12) of the first output stage and the non-inverting input (T.sub.13) of the second output stage. The non-inverting output (.alpha.V) of the input amplifier controls the non-inverting input (T.sub.11) of the first output stage and the inverting input (T.sub.14) of the second output stage.

BACKGROUND OF THE INVENTION 
The invention relates to a 0.degree.-180.degree. active phase shifter for 
microwave frequencies. 
A known phase shifter of this type embodies a differential shape comprising 
two field effect transistors whose sources are coupled together and which 
are charged by an impedance Z whose value is adjusted to obtain equality 
in the magnitude of the signals present at the drains of the transistors, 
and to obtain the desired value of the phase, i.e. 180.degree.. 
Such an adjustment can only be realized in a relatively small frequency 
band and, moreover, it occupies a considerable part of the surface of the 
substrate when it is integrated. 
SUMMARY OF THE INVENTION 
The invention has for its object to provide an active phase shifter 
embodying active elements but requiring a much less considerable part of 
the substrate surface, and which is also capable of functioning in a large 
frequency band and has inter alia a good common mode rejection. 
To this end a 0.degree.-180.degree. active phase shifter for microwave 
frequencies according to the invention is characterized in that it 
comprises a differential input amplifier receiving an input signal and 
having an inverting output and a non-inverting output, and a first and a 
second output stage of the push-pull type realized with MESFET 
transistors, each stage comprising an inverting input and a non-inverting 
input, said inverting output controlling the inverting input of the first 
output stage and the non-inverting input of the second output stage and 
said non-inverting output controlling the non-inverting input of the first 
output stage and the inverting input of the second output stage, the 
outputs of the two output stages constituting the outputs of the phase 
shifter. 
In a preferred embodiment the differential input amplifier is a MESFET 
amplifier having an active charge whose outputs control the respective 
inputs of the first and the second output stage and in that it comprises 
diodes arranged in series with the outputs of the said MESFET amplifier, 
whilst at least a certain number of the inputs of the first and the second 
output stage are connected to the said outputs of the MESFET amplifier via 
at least one of said diodes so as to compensate for level shifts.

DETAILED DESCRIPTION OF THE INVENTION 
FIG. 1a shows a prior art 0.degree.-180.degree. phase shifter having two 
source coupled MESFET transistors T.sub.1 and T.sub.2 so as to form a 
differential stage, an impedance Z being arranged between the sources and 
a power supply terminal. The drains of the transistors are connected to a 
common mode terminal via a resistor R. A simplified form of this circuit 
is shown in FIG. 1b. In this circuit the transistor T.sub.1 is equivalent 
to a capacitor C.sub.1 receiving the input voltage e at one of its 
terminals and supplying the voltage VgS.sub.1 at its terminals, and it is 
equivalent to a controlled current source having a current gm VgS.sub.1 
arraged in series with the resistor R of the drain of the transistor 
T.sub.1 and connected to the other terminal of the capacitor C.sub.1. The 
transistor T.sub.2 is equivalent to a capacitor C.sub.2 arranged in 
parallel with the charge Z and supplying the voltage VgS.sub.2 at its 
terminals, and it is equivalent to a controlled current source having a 
current gmVgS.sub.2 arranged in series between the resistor R of the drain 
of the transistor T.sub.2 and the parallel network Z, C.sub.2. 
Consequently: 
EQU VgShd 2=VgS.sub.1 -3 
EQU gmV.sub.GS2 +gmV.sub.GS1 +jC.omega.V.sub.GS1 +((1/Z)+JC.sub.2 .omega.) 
V.sub.GS2 =O 
EQU V'=-R gm VgS.sub.2 
EQU V=-R gm VgS.sub.1 
The solution of the set of equations gives the values of V' and V: 
##EQU1## 
The equality of the modules (identical gains at the two branches) and the 
180.degree. phase shift can be obtained by adjusting the impedance Z. Such 
an adjustment can only be carried out for a limited frequency band the 
presence of passive elements involves a detrimental loss of space. 
According to FIG. 2a a phase shifter according to the invention comprises a 
differential amplifier receiving an input signal Ve and producing a signal 
Va at its non-inverting output and a signal Vb at its inverting output. 
Consequently: 
##EQU2## 
in which Gd denotes the gain of the differential amplifier and Gc denotes 
its common mode gain. 
The output signals V.sub.1 and V.sub.2 of the phase shifter are produced by 
two push-pull amplifiers provided with MESFET transistors, the first 
amplifier comprising the transistors T.sub.11 and T.sub.12 receiving the 
signals .alpha.V and .beta.V, respectively, at their gates, and the second 
amplifier comprising transistors T.sub.13 and T.sub.14 receiving the 
signals .beta.V and .alpha.V, respectively, at their gates. The drain of 
transistor T.sub.11 is connected to a power supply terminal, its source is 
connected to the drain of transistor T.sub.12 and the source of transistor 
T.sub.12 is connected to the common mode terminal. The drain of transistor 
T.sub.13 is connected to the said power supply terminal, its source is 
connected to the drain of transistor T.sub.14 and the source of transistor 
T.sub.14 is connected to the common mode terminal. If the push-pull 
amplifiers are considered as being ideal, we have: V.sub.1 32 
(.alpha.-.beta.) V=GdV.sub.1 and V.sub.2 =(.beta.-.alpha.) V=-GdV.sub.1, 
which corresponds exactly to the value of the module and the phase and to 
a total rejection of the common mode. In practice, the amplifiers 
introduce faults and the importance of the use of MESFET push-pull stages 
in the relevant case will now be explained. 
A simplified equivalent circuit diagram of a push-pull stage constituted by 
the transistors T.sub.11 and T.sub.12 is shown in FIG. 2b. For the 
transistor T.sub.11 receiving the signal .alpha.V the diagram shows a 
parallel capacitor having a value Cgd receiving the voltage .alpha.V at 
its terminals, a series capacitor having the value Cgs one terminal of 
which is connected to the ungrounded terminal of the parallel capacitor 
Cgd and the other terminal of which is connected to a terminal of a 
controlled current source having current gmV'gs.sub.2 connected via the 
common mode terminal, in which V'gs.sub.2 denotes the voltage at the 
terminals of the capacitor Cgs. A conductance having a value gd is 
connected parallel to the above-mentioned current source. For the 
transistor T.sub.12 receiving the signal .beta.V the circuit diagram shows 
a parallel capacitor having a value Cgs receiving the voltage .beta.V (by 
definition equal to V'gs.sub.1) at its terminals, a series capacitor 
having a value Cgd one terminal of which is connected to the ungrounded 
terminal of the parallel capacitor Cgs and the other terminal of which is 
connected to a terminal of a controlled current source having a current gm 
V'gs.sub.1 connected via the common mode terminal. Finally a conductance 
of the value gd is connected parallel to the above-mentioned current 
source. 
The output voltage V.sub.1 is the voltage which is present at the common 
terminal of the series capacitors and the conductances of the value gd. 
We have: 
V'gs.sub.1 =.beta.V 
V'gs.sub.2 =.alpha.V-V.sub.1 -gmV'gs.sub.1 +gmV'gs.sub.2 
-gV+(.beta.V-V.sub.1) j.omega.Cgd+(.alpha.V-V.sub.1) 
j.omega.Cgs=O 
with g=2gd. 
Thus, 
##EQU3## 
with gm+g+j.omega.(Cgs+Cgd)=G 
For obtaining the value of V.sub.2 it is sufficient to invert .alpha. and 
.beta. in the preceding formula. 
Thus, 
##EQU4## 
By replacing .alpha. and .beta. by their value: 
##EQU5## 
we have: 
##EQU6## 
that is to say: 
##EQU7## 
A reduction in the common mode gain is obtained because of a 
multiplicative factor k which is less than 1: 
##EQU8## 
As far as the phase shift if concerned, its value is exact from f=O and it 
progressively degrades at high frequencies. It can be shown that the 
improvement can be expressed in the equivalent form of the factor K: 
##EQU9## 
Thus an improvement is obtained relating to the phase up to the cut-off 
frequency of the transistor. 
In FIG. 3 the phase shifter comprises an differential input stage having 
two MESFET transistors whose sources are coupled and connected to a 
current source constituted by a transistor T.sub.28, whose gate and source 
are connected to the negative power supply terminal U.sub.3 (for example, 
-4 V) and whose drain is connected to the sources of the transistors 
T.sub.21 and T.sub.23. The input voltage Ve is applied to the gate of 
transistor T.sub.21 via a decoupling network comprising a series capacitor 
C.sub.4 and a parallel resistor R.sub.2 between the gate of transistor 
T.sub.21 and the common mode terminal. The gate of transistor T.sub.23 is 
directly coupled to the common mode terminal. 
In order to obtain a dynamic gain while preserving a continuous gain of the 
order of one, the drains of the transistors T.sub.21 and T.sub.23 are 
associated with an active charge constituted by MESFET transistors 
T.sub.22 and T.sub.24 whose sources are connected to the drain of the 
corresponding transistor and which comprise a capacitor C.sub.3 of low 
value (of the order of a picofarad) connected between their source and 
their gate. The gate of each transistor T.sub.22 and T.sub.24 is connected 
to a power supply terminal U.sub.1 (of, for example, +1.5 V) via a 
resistor R.sub.1 and their drain is connected to a power supply terminal 
U.sub.2 (for example, +4V). 
Transistors T.sub.25 and T.sub.26 arranged as followers whose drain is 
directly connected to the supply source U.sub.2 receive the drain voltages 
of the transistors T.sub.21 and T.sub.23, respectively, at their gate. The 
sources of transistors T.sub.25 and T.sub.26 are each connected to a group 
of several series-arranged diodes D, in this example 4, so as to realize a 
level adaptation for the push-pull output stages. Transistors T.sub.27 and 
T.sub.29 arranged as a current source in a manner analogous to transistor 
T.sub.28 have their drain connected to the cathode of the last diode of 
each group so as to define the current flowing through the diodes and thus 
the voltage drop in these diodes. 
The source of the transistors T.sub.25 and T.sub.26 is connected to the 
gate of the transistors T.sub.13 and T.sub.11, respectively, with a 
voltage drop in one diode, and to the gate of the transistors T.sub.12 and 
T.sub.14, respectively, with a voltage drop in the total number of diodes, 
namely 4, which permits of correctly polarizing the output stages. In this 
configuration U.sub.1 =1.5 V, U.sub.2 =6 V and U.sub.3 =-4 V. 
FIGS. 4a and 4b show a preferred embodiment of the invention in which the 
value of the phase difference between the outputs of the phase shifter can 
vary between 0.degree. and 180.degree.. 
In FIG. 4a a phase shift circuit (.phi..sub.1, .phi..sub.2) comprises two 
parallel branches receiving the input signal. The first parallel branch 
comprises an amplifier A.sub.5 whose output is charged by two identical 
series-arranged resistors R.sub.5 and R'.sub.5, R'.sub.5 having a terminal 
connected to the common mode terminal. The common terminal of the 
resistors R.sub.5 and R'.sub.5 constitutes the output of the first branch. 
The second parallel branch comprises an inverter amplifier A.sub.6 whose 
output is charged by a variable resistor R.sub.6 whose value is controlled 
by a voltge V'e and a capacitor C.sub.6 having a terminal connected to the 
common mode terminal. The common terminal of the resistor R.sub.6 and the 
capacitor C.sub.6 constitutes the output of the second branch. 
The outputs of the two branches are combined by a summation circuit 40 
whose output provides a signal S. 
With R.sub.5 =R'.sub.5 and the two amplifiers A.sub.5 and A.sub.6 having 
the same gain A we have: 
##EQU10## 
The phase shift for a given frequency depends on the time constant 
.tau.=R.sub.6 C.sub.6. 
We have: 
##EQU11## 
Thus, a phase difference .DELTA..phi. can be written which varies between 
0.degree. and 180.degree. in accordance with the value of .tau., thus of 
R.sub.6. 
FIG. 4b shows a particularly advantageous embodiment of the phase shifter 
in which the phase difference may be controlled between 0.degree. and 
180.degree. and which embodies a MESFET differential input stage having an 
active charge and an output stage for each amplifier comprising the MESFET 
transistors arranged in a push-pull configuration which permits of 
optimising the residual common mode voltage. 
An improvement relating to the phase up to the cut-off frequency of the 
transistor is thus obtained. 
Similar elements in FIG. 4b have the same reference numerals as in FIG. 3. 
The resistors R.sub.5 and R'.sub.5 are arranged in series between the 
output of the push-pull stage T.sub.11, T.sub.12 and the common mode 
terminal with the possible interpositioning of a decoupling capacitor 
C.sub.5 having a low value. The variable resistor R.sub.6 is the 
drain-source resistor of a MESFET transistor T.sub.36 whose drain is 
connected to the output of the push-pull stage T.sub.13, T.sub.14 and 
whose source is connected to the ungrounded terminal of the capacitor 
C.sub.6. The gate of transistor T.sub.36 receives a voltage V'.sub.e. 
Finally, the summation circuit 40 is constituted by two MESFET transistors 
T.sub.31 and T.sub.32 whose drains are connected to the power supply 
source U.sub.2, whose sources are interconnected and connected to a 
transistor T.sub.33 arranged as a current source in a manner analogous to 
transistor T.sub.28. The source of transistor T.sub.36 is connected to the 
gate of transistor T.sub.32 and the common terminal of the resistors 
R.sub.5 and R'.sub.5 is connected to the gate of transistor T.sub.31 which 
produces the sum of their voltages at the sources of the transistors 
T.sub.31 and T.sub.32 (signal S). To vary the phase difference between 
0.degree. and 180.degree., the voltage V'e must be varied up to the 
pinch-off voltage of the channel of the transistor T.sub.36.