Switch driver with a low-cost cross-conduction-preventing circuit

A driver for a power transistor switch comprising a FET complementary output stage which is driven by another FET complementary pre-driver stage which is further driven by an input-buffer and level-shifter stage. The pre-driver stage includes a current-limiting and cross-delaying circuit which is inserted in between drains terminals of a complementary FET pair. The current-limiting and cross-delaying circuit limits shoot-current at the pre-driver stage; and in conjunction with the FET pair and the input-buffer and level-shifter stage, it is adapted to delay turning on one complementary output FET until after the other complementary output FET is turned off, thereby preventing cross conduction at the output stage.

TECHNICAL FIELD

The present invention relates in general to a driver circuit for driving a power transistor switch. And more particularly, the present invention relates to a switch driver circuit with a complementary output in which cross conduction is prevented or minimized by use of a current-limiting and cross-delaying circuit.

BACKGROUND ART

A switch driver, also frequently referred to as a gate driver, is a circuit that can accept a typically low-current, logic-voltage-level external input signal, and then level-shift and amplify the input signal to produce a higher-current and usually wider voltage-level output, which is coupled to drive the gate of a power transistor (such as a power metal-oxide-semiconductor-field-effect-transistor (MOSFET), or an insulated-gate-bipolar-transistor (IGBT)), thereby switching ON/OFF the power transistor at high speeds. Because of intrinsic parasitic capacitances, a power transistor is considered a capacitive load for a switch driver, which essentially charges or discharges the power transistor during switching transitions. A switch driver can also be used to drive other types of equivalent capacitive loads, such as digital bus lines.

It is very common for a switch driver to comprise a complementary or totem-pole output that is based on a p-channel field-effect-transistor (FET) at the top and an n-channel FET on the bottom with drain terminals of the 2 FETs being coupled to form a common output node.FIG. 1illustrates a typical prior-art switch driver100comprising: a p-channel FET101including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply VDRIVE; an n-channel FET102including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a ground potential relative to the VDRIVE, and wherein the drain terminal is coupled to the drain terminal of the FET101thereby forming a complementary output node which is operable to be coupled to drive an external power transistor switch130(via an optional gate resistor (not shown), if it is necessary to reduce ringing introduced by parasitic lead inductance); a pre-driver circuit110, powered by the VDRIVE, and operable to be coupled to drive the gate terminals of the FETs101and102by switching one FET on while switching the other FET off during a switching transition; an input-buffer and level-shifter circuit120, being powered by both a logic-voltage-level power supply VLOGICand the VDRIVE, to buffer and level-shift an external input signal at node150from VLOGIClevel to VDRIVElevel, and coupled to drive the pre-driver circuit110. If during a switching transition, both the FETs101and102are partially or completely turned on simultaneously by the pre-driver circuit110, cross conduction occurs, and a relatively large momentary shoot-through current runs through the FETs101and102, resulting in low driving efficiency and potentially overheating the prior-art switch driver100. Therefore, the prior-art switch driver100usually contains complicated circuits to minimize or hopefully eliminate cross conduction in the complementary output when the prior-art switch driver100operates within a specified junction temperature range.

There are switch driver designs that can minimize or prevent cross conduction at complementary outputs by complicated logic circuits and/or timing circuits. U.S. Pat. No. 6,538,479 (Bellomo et al.) discloses a switch driver circuit, which includes an adaptive anti-cross-conduction mechanism based on two power-on detectors, each of which is coupled to a respective complementary-output FET; when a power-on detector detects that a corresponding FET is still on, the switch driver circuit prohibits the other FET from being turned on.

SUMMARY OF INVENTION

Technical Problem

All known prior-art cross-conduction-preventing mechanisms implemented in switch drivers are considerably complicated in design, and significantly costly to produce, either in discrete modules or in integrated circuits (ICs). Usually, each of the complementary-output FETs needs to be separately driven by a plurality of stages of pre-drivers. And a complicated timing circuit and/or a complicated logic circuit (based on comparator(s), or sensors/detectors, and so forth) are required to implement a reliable cross-conduction-preventing feature. Subsequently, it is relatively expensive to produce a high-performing switch driver, and it is even more challenging to integrate a single or a plurality of high-performing switch drivers together with other major circuit functions on the same IC.

Solution to Problem

In one embodiment of the invention, a driver for a power transistor switch comprises: a first p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply VDRIVE; a first n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a ground potential relative to the VDRIVE, and wherein the drain terminal is coupled to the drain terminal of the first p-channel FET thereby forming a complementary output node which is operable to be coupled to drive the power transistor switch; a second p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first p-channel FET; a second n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first n-channel FET; a current-limiting and cross-delaying circuit including a first node and a second node, further comprising at least one resistor, and wherein the first node is coupled to the drain terminal of the second p-channel FET, and wherein the second node is coupled to the drain terminal of the second n-channel FET, to reduce current flowing from the first node to the second node thereby limiting shoot-through current when both the second p-channel FET and the second n-channel FET are momentarily turned on during a switching transition, and delaying turning on the first p-channel FET when the first n-channel FET is being turned off, and delaying turning on the first n-channel FET when the first p-channel FET is being turned off; and an input-buffer and level-shifter circuit, being powered by both a logic-voltage-level power supply VLOGICand the VDRIVE, to buffer and level-shift an external input signal from VLOGIClevel to VDRIVElevel, and coupled to drive the gate terminals of the second p-channel FET and the second n-channel FET, and in conjunction with the current-limiting and cross-delaying circuit, to turn off the first p-channel FET before turning on the first n-channel FET thereby preventing cross conduction, and to turn off the first n-channel FET before turning on the first p-channel FET thereby preventing cross conduction. The at least one resistor may alternatively be constructed utilizing the drain-to-source turn-on resistance of a FET. In other embodiments of the invention, in addition to the at least one resistor, the current-limiting and cross-delaying circuit may comprise any combination of the following: a single resistor or a plurality of resistors; a single diode or a plurality of diodes; and a single transistor or a plurality of transistors.

In one embodiment, the input-buffer and level-shifter circuit further comprises: a third p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to the VDRIVE, and wherein the drain terminal is coupled to the gate terminal of the second p-channel FET, and wherein the gate terminal is coupled to the second node of the current-limiting and cross-delaying circuit; a third n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the drain terminal is coupled to the drain terminal of the third p-channel FET, and wherein the source terminal is coupled to the ground potential; an input buffer, being powered by the VLOGIC, and including an input terminal coupled to the external input signal, and including an output terminal coupled to the gate terminal of the third n-channel FET; an inverter, being powered by the VLOGIC, and including an input terminal coupled to the output terminal of the input buffer, and including an output terminal coupled to the gate terminal of the second n-channel FET.

In another embodiment of the invention, a driver for a power transistor switch comprises: a first p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply VDRIVE; a first n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a ground potential relative to the VDRIVE, and wherein the drain terminal is coupled to the drain terminal of the first p-channel FET thereby forming a complementary output node which is operable to be coupled to drive the power transistor switch; a second p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first p-channel FET; a second n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first n-channel FET; a current-limiting and cross-delaying circuit including a first node and a second node, further comprising at least one resistor, and wherein the first node is coupled to the drain terminal of the second p-channel FET, and wherein the second node is coupled to the drain terminal of the second n-channel FET, to reduce current flowing from the first node to the second node thereby limiting shoot-through current when both the second p-channel FET and the second n-channel FET are momentarily turned on during a switching transition, and delaying turning on the first p-channel FET when the first n-channel FET is being turned off, and delaying turning on the first n-channel FET when the first p-channel FET is being turned off; and an input-buffer circuit, being powered by the VDRIVE, to buffer and amplify an external input signal, and coupled to drive the gate terminals of the second p-channel FET and the second n-channel FET, and in conjunction with the current-limiting and cross-delaying circuit, to turn off the first p-channel FET before turning on the first n-channel FET thereby preventing cross conduction, and to turn off the first n-channel FET before turning on the first p-channel FET thereby preventing cross conduction.

Advantageous Effects of Invention

It is an advantageous effect of the invention to achieve a switch driver with a low-cost cross-conduction-preventing circuit; wherein a p-channel FET and an n-channel FET essentially forms a complementary pre-driver circuit with a current-limiting and cross-delaying circuit inserted in between their drain terminals, so that cross conduction of the complementary output can be prevented at low cost without compromising the performance of the switch driver; and the current-limiting and cross-delaying circuit can comprise a passive element as simple as a single resistor.

Another advantageous effect of the invention is a simple implementation of an input-buffer and level-shifter circuit in conjunction with the current-limiting and cross-delaying circuit, thereby further reducing the cost to build the switch driver without compromising the performance of the switch driver.

Still another advantageous effect of the invention is the feasibility of utilizing FETs only (no bipolar-junction-transistors (BJTs)) to implement the switch driver thereby achieving essentially zero quiescent power consumption.

Other advantages and benefits of the invention will become readily apparent upon further review of the following drawings.

MODES FOR CARRYING OUT THE INVENTION

In one embodiment of the invention, as illustrated inFIG. 2, a driver200for a power transistor switch230comprises: a first p-channel FET201including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply VDRIVE; a first n-channel FET202including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a ground potential relative to the VDRIVE, and wherein the drain terminal is coupled to the drain terminal of the first p-channel FET201thereby forming a complementary output node242which is operable to be coupled to drive the power transistor switch230(via an optional gate resistor (not shown), if it is necessary to reduce ringing introduced by parasitic lead inductance); a second p-channel FET203including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first p-channel FET201; a second n-channel FET204including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first n-channel FET202; a current-limiting and cross-delaying circuit210including a first node240and a second node241, further comprising at least one resistor, and wherein the first node240is coupled to the drain terminal of the second p-channel FET203, and wherein the second node241is coupled to the drain terminal of the second n-channel FET204, to reduce current flowing from the first node240to the second node241thereby limiting shoot-through current when both the second p-channel FET203and the second n-channel FET204are momentarily turned on during a switching transition, and delaying turning on the first p-channel FET201when the first n-channel FET202is being turned off, and delaying turning on the first n-channel FET202when the first p-channel FET201is being turned off; and an input-buffer and level-shifter circuit220, being powered by both a logic-voltage-level power supply VLOGICand the VDRIVE, to buffer and level-shift an external input signal at node250from VLOGIClevel to VDRIVElevel, with nodes252and254to be coupled to respectively drive the gate terminals of the second p-channel FET203and the second n-channel FET204, and in conjunction with the current-limiting and cross-delaying circuit210, to turn off the first p-channel FET201before turning on the first n-channel FET202thereby preventing cross conduction, and to turn off the first n-channel FET202before turning on the first p-channel FET201thereby preventing cross conduction.

After the second n-channel FET204is turned on, the first n-channel FET202is turned off; then the second p-channel FET203is turned off leaving its drain terminal floating; then the first node240of the current-limiting and cross-delaying circuit210starts to pull down the gate voltage of the first p-channel FET201toward ground potential until the first p-channel FET201is turned on, thereby sourcing VDRIVEto the complementary output node242. Likewise, after the second p-channel FET203is turned on, the first p-channel FET201is turned off; then the second n-channel FET204is turned off leaving its drain terminal floating; then the second node241of the current-limiting and cross-delaying circuit210starts to pull up the gate voltage of the first n-channel FET202toward VDRIVEuntil the first n-channel FET202is turned on, thereby sinking the complementary output node242to ground potential.

In one embodiment, both the VDRIVEand the VLOGICare respectively coupled to bypass capacitors (not shown) to work with peak switching currents. VLOGICmay be provided externally or be generated from VDRIVEvia a voltage regulator or a Zener diode (not shown). The second p-channel FET203and the second n-channel FET204essentially form a complementary pre-driver with the current-limiting and cross-delaying circuit210inserted in between their drain terminals; and they are preferably designed to be respectively smaller than the first p-channel FET201and the first n-channel FET202, and subsequently have respectively larger drain-to-source turn-on resistances. The gate-to-source voltage ratings of the first p-channel FET201and the second n-channel FET202should be higher than VDRIVE; and subsequently, the maximum VDRIVEis limited by these gate-to-source voltage ratings. The larger the resistance of the resistor of the current-limiting and cross-delaying circuit210, the more delay the current-limiting and cross-delaying circuit210can cause for turning on the first p-channel FET201or the first n-channel FET202. In various embodiments, instead of driving a single power transistor switch, the driver200drives a plurality of power transistor switches simultaneously (not shown), or drives some other equivalent capacitive load (e.g., a digital bus line, or an equivalent load).

FIG. 3illustrates a basic embodiment of the current-limiting and cross-delaying circuit210comprising: a resistor211A, including two terminals respectively coupled to the first node240and the second node241of the current-limiting and cross-delaying circuit210. This embodiment is one of the most basic, simplest, and still highly efficient implementations of the current-limiting and cross-delaying circuit210. The resistor211A essentially forms a resistive-capacitive (RC) delay circuit with either the gate capacitance of the first p-channel FET201or the gate capacitance of the first n-channel FET202.

During a switching transition, when both the second p-channel FET203and the second n-channel FET204are momentarily turned on, and after discharging the input capacitances of the first p-channel FET201and the first n-channel FET202as much as possible, the drain-to-source turn-on resistance of the second p-channel FET203, and the drain-to-source turn-on resistance of the second n-channel FET204, and the resistor211A essentially form a virtual voltage divider across the VDRIVEand the ground potential. In one embodiment, this virtual voltage divider is designed to maintain the following mathematical relationships in order to prevent cross conduction at the complementary output: the source-to-drain voltage drop of the second p-channel FET203is preferably smaller than the absolute value of the gate threshold voltage of the first p-channel FET201; and the drain-to-source voltage drop of the second n-channel FET204is preferably adapted to be smaller than the gate threshold voltage of the first n-channel FET202. These are illustrated respectively by the following equations (1) and (2):

Because the drain-to-source turn-on resistance of a FET tends to exhibit a positive temperature coefficient (i.e., the higher the junction temperature, the higher the drain-to-source turn-on resistance), and because both VSD_203and VDS_204are proportional to VDRIVE, to partially compensate for changes of VSD_103and VDS_104with respect to changes of junction temperature or VDRIVE, in one embodiment of the invention, the resistor211A possesses both a positive temperature coefficient and a positive voltage coefficient (i.e., the higher the voltage drop across the resistor211A, the higher the resistance of the resistor211A). As an example, an n-well resistor is one type of resistor that exhibits both a positive temperature coefficient and a positive voltage coefficient.

There are many possible design embodiments of a functioning input-buffer and level-shifter circuit220. In addition to the embodiment of the current-limiting and cross-delaying circuit210,FIG. 3also illustrates an embodiment of the input-buffer and level-shifter circuit220comprising: a third p-channel FET224A including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to the VDRIVE, and wherein the drain terminal is coupled to the gate terminal of the second p-channel FET203(thereby forming the node252), and wherein the gate terminal is coupled to the second node241of the current-limiting and cross-delaying circuit210; a third n-channel FET223A including a gate terminal, a source terminal, and a drain terminal, wherein the drain terminal is coupled to the drain terminal of the third p-channel FET224A, and wherein the source terminal is coupled to the ground potential; an input buffer221A, being either inverting or non-inverting (FIG. 3illustrates an inverting buffer even though a non-inverting buffer would also be feasible in another embodiment), and being powered by the VLOGIC, and including an input terminal coupled to the external input signal at node250, and including an output terminal251coupled to the gate terminal of the third n-channel FET223A; an inverter222A, being powered by the VLOGIC, and including an input terminal253coupled to the output terminal251of the input buffer221A, and including an output terminal coupled to the gate terminal of the second n-channel FET204(thereby forming the node254).

When both the third p-channel FET224A and the third n-channel FET223A are turned on, the drain-to-source turn-on resistances of both FETs essentially form another virtual voltage divider across the VDRIVEand the ground potential, and in one embodiment, these FETs are adapted to be in an appropriate ratio to enable reliably turning ON/OFF the second p-channel FET203within the entire operating VDRIVErange. In one embodiment, the combined drain-to-source resistances of both FETs are adapted to be sufficiently large to limit current flowing from the VDRIVEto the ground potential.

To assist in understandingFIG. 3,FIG. 11illustrates a 0-to-1 switching process1100starting in step1102. In step1104, the external input signal at node250transitions from logic 0 to logic 1. In step1106, the output251of the buffer221A transitions from logic 1 to logic 0. In step1108, the output (at node254) of the inverter222A transitions from logic 0 to logic 1; while approximately concurrent to step1108, in step1110, the drain voltage (at node252) of the third n-channel FET223A transitions from ground potential to floating. In step1112, the drain voltage of the second n-channel FET204transitions from VDRIVEtoward ground potential while turning off the first n-channel FET202and turning on the third p-channel FET224A which starts to charge the gate voltage of the second p-channel FET203toward VDRIVE; while approximately concurrent to step1112, in step1114, the first p-channel FET201stays off because the second p-channel FET203has not been turned off. In step1116, the third p-channel FET224A turns off the second p-channel FET203whose drain voltage becomes floating; while approximately concurrent to step1116, in step1118, the drain terminal of second n-channel FET204starts to pulls down the gate voltage of the first p-channel FET201toward ground potential via the resistor211A. In step1120, the first p-channel FET201is turned on thereby sourcing VDRIVEto the complementary output node242. And the 0-to-1 switching process1100ends in step1122.

To further assist in understandingFIG. 3,FIG. 12illustrates a 1-to-0 switching process1200starting in step1202. In step1204, the external input signal at node250transitions from logic 1 to logic 0. In step1206, the output251of the buffer221A transitions from logic 0 to logic 1. In step1208, the output (at node254) of the inverter222A transitions from logic 1 to logic 0; while approximately concurrent to step1208, in step1210, the drain voltage (at node252) of the third n-channel FET223A transitions from VDRIVEto active low thereby turning on the second p-channel FET203. In step1212, the first n-channel FET202stays off because the second n-channel FET204has not been turned off; while approximately concurrent to step1212, in step1214, the drain voltage of the second p-channel FET203transitions from ground potential to active high while turning off both the first p-channel FET201and the third p-channel FET224A. In step1216, the output254of inverter222A turns off the second n-channel FET204whose drain voltage becomes floating; while approximately concurrent to step1216, in step1218, the second p-channel FET203starts to pull up the gate voltage of the first n-channel FET202toward VDRIVEvia the resistor211A. In step1220, the first n-channel FET202is turned on thereby sinking the complementary output node242to ground potential. And the 1-to-0 switching process1200ends in step1222.

Since when the external input signal at node250transitions from logic 0 to logic 1, the complementary output node242transitions from ground potential to VDRIVE, the driver illustrated inFIG. 3is constructed in a non-inverting configuration. In contrast, if the buffer221A is constructed as a non-inverting buffer in another embodiment, the driver200is constructed in an inverting configuration instead.

The resistor211A can be fabricated in any one of many feasible ways including utilizing the drain-to-source turn-on resistance of a FET. In addition to the resistor211A, the current-limiting and cross-delaying circuit210may optionally comprise any combination of the following: a single resistor or a plurality of resistors; a single diode or a plurality of diodes; and a single transistor or a plurality of transistors. These are explained in the following sections.

FIG. 4, essentially identical toFIG. 3except that the fabrication of a resistor differs, illustrates another embodiment of the current-limiting and cross-delaying circuit210comprising: a p-channel FET211B, including a gate terminal coupled to the ground potential, and including a source terminal and a drain terminal respectively coupled to the first node240and the second node241of the current-limiting and cross-delaying circuit210. The second node241of the current-limiting and cross-delaying circuit210is still coupled to the gate terminal of the third p-channel FET224A in the input-buffer and level-shifter circuit220. When the source voltage of the FET211B exceeds the corresponding gate threshold voltage, the FET211B is turned on and the drain-to-source turn-on resistance becomes an effective replacement for the resistor211A inFIG. 3. The advantages of this embodiment over the embodiment illustrated inFIG. 3include easier fabrication of a FET versus fabrication of a resistor on an IC, and a positive temperature coefficient of the drain-to-source turn-on resistance of the FET211B. The disadvantages of this embodiment over the embodiment illustrated inFIG. 3include not being able to pull down the gate voltage of the first p-channel FET201to ground potential because of the limitation of the gate threshold voltage of the FET211B, and a negative voltage coefficient of the drain-to-source turn-on resistance of the FET211B.

As an alternative to the embodiment illustrated inFIG. 4,FIG. 5, essentially identical toFIG. 3except that the fabrication of a resistor differs, illustrates another embodiment of the current-limiting and cross-delaying circuit210comprising: an n-channel FET211C, including a gate terminal coupled to the VDRIVE, and including a drain terminal and a source terminal respectively coupled to the first node240and the second node241of the current-limiting and cross-delaying circuit210. The second node241of the current-limiting and cross-delaying circuit210is still coupled to the gate terminal of the third p-channel FET224A in the input-buffer and level-shifter circuit220. When the source voltage of the FET211C drops below VDRIVEby an amount equal to the corresponding gate threshold voltage, the FET211C is turned on and the drain-to-source turn-on resistance becomes an effective replacement for the resistor211A inFIG. 3. The advantages of this embodiment over the embodiment illustrated inFIG. 3include easier fabrication of a FET versus fabrication of a resistor on an IC, and a positive temperature coefficient of the drain-to-source turn-on resistance of the FET211C. The disadvantages of this embodiment over the embodiment illustrated inFIG. 3include not being able to pull up the gate voltage of the first n-channel FET202to VDRIVEbecause of the limitation of the gate threshold voltage of the FET211C, and a negative voltage coefficient of the drain-to-source turn-on resistance of the FET211C.

FIG. 6is essentially identical toFIG. 3except that it illustrates still another embodiment of the current-limiting and cross-delaying circuit210comprising: an upper resistor2110, including a first terminal coupled to the first node240of the current-limiting and cross-delaying circuit210, and including a second terminal coupled to the gate terminal of the third p-channel FET224A in the input-buffer and level-shifter circuit220; a lower resistor2120, including a first terminal coupled to the second terminal of the upper resistor2110, and including a second terminal coupled to the second node241of the current-limiting and cross-delaying circuit210. Assuming the combined resistance of the upper resistor2110and the lower resistor2120is equal to the resistance of the resistor211A inFIG. 3, the advantages of this embodiment over the embodiment illustrated inFIG. 3include faster turning off of the third p-channel FET224A, and faster turning off of the first n-channel FET202. The disadvantages of this embodiment over the embodiment illustrated inFIG. 3include slower turning on of the third p-channel FET224A, and the extra cost to fabricate one more resistor.

FIG. 7is essentially identical toFIG. 3except that it illustrates still another embodiment of the current-limiting and cross-delaying circuit210comprising: an upper resistor211E, including a first terminal coupled to the first node240of the current-limiting and cross-delaying circuit210, and including a second terminal coupled to the gate terminal of the third p-channel FET224A in the input-buffer and level-shifter circuit220; a lower diode212E, including an anode coupled to the second terminal of the upper resistor211E, and including a cathode coupled to the second node241of the current-limiting and cross-delaying circuit210. The advantages of this embodiment over the embodiment illustrated inFIG. 3include faster turning off of the third p-channel FET224A, and faster turning off of the first n-channel FET202. The disadvantages of this embodiment over the embodiment illustrated inFIG. 3include slower turning on of the third p-channel FET224A, and the extra cost to fabricate a diode.

FIG. 8is essentially identical toFIG. 3except that it illustrates still another embodiment of the current-limiting and cross-delaying circuit210comprising: an upper diode211F, including an anode coupled to the first node240of the current-limiting and cross-delaying circuit210; a lower resistor212F, including a first terminal coupled to a cathode of the upper diode211F, and including a second terminal coupled to the gate terminal of the third p-channel FET224A and to the second node241of the current-limiting and cross-delaying circuit210. Assuming that the resistance of the lower resistor212F is equal to the resistance of the resistor211A inFIG. 3, the advantages of this embodiment over the embodiment illustrated inFIG. 3include longer delay to turn on the first p-channel FET201or the first n-channel FET202, and better current-limiting when both the second p-channel FET203and the second n-channel FET204are momentarily turned on during a switching transition. The disadvantages of this embodiment over the embodiment illustrated inFIG. 3include longer switching propagation delays, and the extra cost to fabricate a diode.

FIG. 9is essentially identical toFIG. 3except that it illustrates still another embodiment of the current-limiting and cross-delaying circuit210comprising: a resistor211G, including a first terminal and a second terminal respectively coupled to the first node240and the second node241of the current-limiting and cross-delaying circuit210; another resistor212G, including a second terminal coupled to the second terminal of the resistor211G; and a switch213G, including a first terminal coupled to the first terminal of the resistor211G, and including a second terminal coupled to a first terminal of the resistor212G, and including a control terminal244via which the switch213G is operable to be turned on by the driver200when VDRIVEdrops below a pre-determined voltage threshold, thereby paralleling both the resistors211G and212G to reduce the overall resistance across the first node240and the second node241of the current-limiting and cross-delaying circuit210. The advantages of this embodiment over the embodiment illustrated inFIG. 3include shorter propagation delays when VDRIVEdrops below the pre-determined voltage threshold. The disadvantages of this embodiment over the embodiment illustrated inFIG. 3include the extra cost and the extra complexity to fabricate one more resistor and a switch plus related voltage reference and control logic.

If VDRIVEis equal to VLOGIC, level-shifting is unnecessary. This may happen when VDRIVEis also at logic voltage level, or when the external input signal has been level-shifted to VDRIVElevel in a pre-switch-driver circuit, or in any other possible scenario. Therefore, in another embodiment of the invention, as illustrated inFIG. 10, a driver300for a power transistor switch330comprises: a first p-channel FET301including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply VDRIVE; a first n-channel FET302including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal coupled to a ground potential relative to the VDRIVE, and wherein the drain terminal is coupled to the drain terminal of the first p-channel FET301thereby forming a complementary output node342which is operable to be coupled to drive the power transistor switch330(in one embodiment via a gate resistor (not shown) if it is necessary to reduce ringing introduced by parasitic lead inductance); a second p-channel FET303including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first p-channel FET301; a second n-channel FET304including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first n-channel FET302; a current-limiting and cross-delaying circuit310including a first node340and a second node341, further comprising at least one resistor, and wherein the first node340is coupled to the drain terminal of the second p-channel FET303, and wherein the second node341is coupled to the drain terminal of the second n-channel FET304, to reduce current flowing from the first node340to the second node341thereby limiting shoot-through current when both the second p-channel FET303and the second n-channel FET304are momentarily turned on during a switch transition, and delaying turning on the first p-channel FET301when the first n-channel FET302is being turned off, and delaying turning on the first n-channel FET302when the first p-channel FET301is being turned off; and an input-buffer circuit320, being powered by the VDRIVE, to buffer and amplify an external input signal at node350, and to be coupled via nodes352and354to drive the gate terminals of the second p-channel FET303and the second n-channel FET304, and in a conjunction with the current-limiting and cross-delaying circuit310, to turn off the first p-channel FET301before turning on the first n-channel FET302thereby preventing cross conduction, and to turn off the first n-channel FET302before turning on the first p-channel FET301thereby preventing cross conduction.

In one embodiment of the current-limiting and cross-delaying circuit310, at least one resistor includes two terminals which are respectively coupled to the first node340and the second node341of the current-limiting and cross-delaying circuit310. The at least one resistor can be fabricated in any one of many feasible ways including being fabricated as an n-well resistor. As an alternative, the at least one resistor may be fabricated as a p-channel FET including: a source terminal, being coupled to the drain terminal of the second p-channel FET303; and a drain terminal, being coupled to the drain terminal of the second n-channel FET304; and a gate terminal, being coupled to the ground potential. The at least one resistor may also be fabricated as an n-channel FET including: a drain terminal, being coupled to the drain terminal of the second p-channel FET303; and a source terminal, being coupled to the drain terminal of the second n-channel FET304; and a gate terminal, being coupled to the VDRIVE.

In addition to the at least one resistor, the current-limiting and cross-delaying circuit310may optionally comprise any combination of the following: a single resistor or a plurality of resistors; a single diode or a plurality of diodes; and a single transistor or a plurality of transistors.

In one embodiment of the invention, instead of driving a single power transistor switch, the driver300can drive a plurality of power transistor switches simultaneously (not shown), or drive some other equivalent capacitive loads (e.g., a digital bus line or an equivalent).

FIG. 13illustrates a method1300to fabricate a driver for a power transistor switch, in accordance with one embodiment of the invention. The method begins in operation1302. Operation1304is next and includes fabricating a first p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to an output-drive power supply VDRIVE. Operation1306is next and includes fabricating a first n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to a ground potential relative to the VDRIVE, and wherein the drain terminal is coupled to the drain terminal of the first p-channel FET thereby forming a complementary output node which is operable to be coupled to drive the power transistor switch. Operation1308is next and includes fabricating a second p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first p-channel FET. Operation1310is next and includes fabricating a second n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal and the drain terminal are respectively coupled to the source terminal and the gate terminal of the first n-channel FET. Operation1312is next and includes constructing a current-limiting and cross-delaying circuit including a first node and a second node, further comprising at least one resistor, and wherein the first node is coupled to the drain terminal of the second p-channel FET, and wherein the second node is coupled to the drain terminal of the second n-channel FET, to reduce current flowing from the first node to the second node thereby limiting shoot-through current when both the second p-channel FET and the second n-channel FET are momentarily turned on during a switching transition, and delaying turning on the first p-channel FET when the first n-channel FET is being turned off, and delaying turning on the first n-channel FET when the first p-channel FET is being turned off. Operation1314is next and includes constructing an input-buffer and level-shifter circuit, being powered by both a logic-voltage-level power supply VLOGICand the VDRIVE, to buffer and level-shift an external input signal from VLOGIClevel to VDRIVElevel, and coupled to the gate terminals of the second p-channel FET and the second n-channel FET, and in conjunction with the current-limiting and cross-delaying circuit, to turn off the first p-channel FET before turning on the first n-channel FET thereby preventing cross conduction, and to turn off the first n-channel FET before turning on the first p-channel FET thereby preventing cross conduction. The method ends in operation1316.

One method to construct the current-limiting and cross-delaying circuit includes fabricating at least one resistor to include two terminals which are respectively coupled to the first node and the second node of the current-limiting and cross-delaying circuit. One method is to fabricate the at least one resistor as turn-on drain-to-source resistance of a p-channel FET or an n-channel FET, or as an n-well resistor. One method to construct the current-limiting and cross-delaying circuit is, in addition to the at least one resistor, to comprise any combination of the following: a single resistor or a plurality of resistors; a single diode or a plurality of diodes; and a single transistor or a plurality of transistors.

One method to construct the input-buffer and level-shifter circuit comprises: fabricating a third p-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to the VDRIVE, and wherein the drain terminal is coupled to the gate terminal of the second p-channel FET, and wherein the gate terminal is coupled to the second node of the current-limiting and cross-delaying circuit; fabricating a third n-channel FET including a gate terminal, a source terminal, and a drain terminal, wherein the drain terminal is coupled to the drain terminal of the third p-channel FET, and wherein the source terminal is coupled to the ground potential; constructing an input buffer, being powered by the VLOGIC, and including an input terminal coupled to the external input signal, and including an output terminal coupled to the gate terminal of the third n-channel FET; constructing an inverter, being powered by the VLOGIC, and including an input terminal coupled to the output terminal of the input buffer, and including an output terminal coupled to the gate terminal of the second n-channel FET.

INDUSTRIAL APPLICABILITY

In view of the foregoing, the industrial applicability of the present invention is broad and can provide a low-cost and high-performing switch driver with a cross-conduction-preventing circuit. And because of its simplicity and ease of fabrication, a single switch driver or a plurality of such switch drivers can be integrated with other functions on a same IC. Applications of such a switch driver include switch-mode power supplies (SMPS), synchronous rectifier circuits, motor controls, digital bus line drivers, and so forth.

While the foregoing invention shows a number of illustrative and descriptive embodiments of the invention, it will be apparent to any person with ordinary skills in the area of technology related to the invention that various changes, modifications, substitutions and combinations can be made herein without departing from the scope or the spirit of the invention as defined by the following claims.