Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump

A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.

FIELD OF THE INVENTION

The present invention relates generally to electronic circuits and semiconductor devices and, more specifically, to a semiconductor device and method of forming a power MOSFET with an interconnect structure and silicide layer formed over closely spaced transistors and further including a low profile bump.

BACKGROUND OF THE INVENTION

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, operate with a lower voltage, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

Power MOSFETs are one example of semiconductor devices commonly used in electronic circuits, such as communication systems and power supplies. Power MOSFETs are particularly useful when used as electric switches to enable and disable the conduction of relatively large currents. The on/off state of the power MOSFET is controlled by applying and removing a triggering signal at the gate electrode. When turned on, the electric current in the MOSFET flows between the drain and source. When turned off, the electric current is blocked by the MOSFET.

The miniaturization of power MOSFETs produces devices that include small MOSFET cells or transistors that are distributed across an entire surface of a semiconductor die. MOSFET cells include source and drain regions that are formed at the scale of electrical interconnects, such as bumps formed over source and drain pads, or terminals, for subsequent electrical interconnect. Accordingly, multiple source and drain regions are often located under a single source or drain pad. The use of strictly vertical interconnects within a power MOSFET with closely spaced transistors does not provide for connecting both source and drain regions of a transistor located under a single source pad or drain pad to connect with corresponding horizontally offset source pads and drain pads. Accordingly, an interconnect structure that accounts for horizontal offset is needed to connect source and drain regions located under a single source or drain pad to horizontally offset source and drain pads.

Furthermore, power MOSFETs, like other semiconductor devices, include interconnect structures for electrically connecting the semiconductor device to substrates, circuit boards, and other semiconductor devices. One common technique of interconnecting a semiconductor die with a printed circuit board (PCB) or other device involves the use of solder bumps.FIG. 1ashows a conventional UBM solder bump structure10. Solder bump structure10includes a semiconductor die11including a semiconductor wafer of base silicon12over which an active area14is formed. Active area14includes analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die11and electrically interconnected according to the electrical design and function of the semiconductor die. An electrically conductive layer16is formed over active area14of semiconductor die11, and operates as a contact pad. An insulation or passivation layer18is formed over semiconductor die11and conductive layer16. A portion of insulation layer18is removed by an etching process to form opening20in the insulation layer that exposes a portion of conductive layer16. In one embodiment, opening20has a width of 270 micrometers (μm). An electrically conductive or UBM layer22is formed over, and conformally applied to, conductive layer16, within opening20, and over a portion of insulation layer18. In one embodiment, conductive layer22includes an adhesion layer, barrier layer, and wetting layer comprising aluminum (Al), nickel vanadium (NiV), and copper (Cu), respectively. An insulation or passivation layer24such as benzocyclobutene (BCB) is formed over conductive layer22and insulation layer18. An opening26in insulation layer24is formed over and exposes a portion of UBM22. In one embodiment, opening26has a width of 280 μm. A conductive bump28is disposed over conductive layers16and22, and within openings20and26to complete conventional UBM solder bump structure10. In one embodiment, conductive bump28includes a preformed solder sphere with a predetermined diameter30of 350 μm that is mounted to conductive layer22in a ball drop process.

FIG. 1bshows semiconductor die11with the conventional UBM solder bump structure10fromFIG. 1apackaged as part of an over molded system in package (SiP)32. Semiconductor die11is mounted to substrate or multilayered PCB34which further includes conductive contacts36. Underfill38is deposited around bumps28and between substrate34and active area14of semiconductor die11to improve a connection between semiconductor die11and substrate34. Bumps28undergo multiple reflows to improve electrical and mechanical connections. The multiple reflows of bumps28include reflowing bumps28for connecting the bumps to semiconductor die11, reflowing bumps28while connected to semiconductor die11to connect semiconductor die11and bumps28to substrate34, reflowing bumps28when mounting SiP32to an additional substrate or multilayered PCB, and reflowing bumps28for the mounting of additional components to, or rework of, the additional substrate or multi-layered PCB. However, reflowing bumps28in some instances leads to solder bridging and electrical shorting among bumps28, thereby causing failure of semiconductor die11. Solder bridging and electrical shorting among bumps28is more likely to occur when the bumps have a fine pitch. Underfill material38is optimized to prevent voiding of the underfill between bumps28and to help prevent solder bridging and electrical shorting by keeping bump material localized during reflow. However, controlling placement of underfill material38is difficult and may result in the placement of the underfill with a non-uniform thickness. A non-uniform thickness of underfill material38is common and includes, for example, a configuration in which only a portion of a gap between semiconductor die11and substrate34on a first side of the semiconductor die is filled while an entirety of the gap on a second side of the semiconductor die is filled. Unevenly distributed underfill38causes an imbalance of stresses on semiconductor die11which can lead to cracking and failure of the semiconductor die. Furthermore, encapsulant or mold compound40is placed over and around semiconductor die11. The combination of encapsulant40and unevenly distributed underfill38further causes an imbalance of stresses on semiconductor die11, which further leads to cracking and failure of the die. Accordingly, the conventional assembly of SiP32with underfill38is prone to defects that decrease the yield and reliability of the SiP assemblies.

SUMMARY OF THE INVENTION

A need exists to provide a power MOSFET with a low profile bump and an interconnect structure formed over closely spaced transistors. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device, comprising providing a substrate, forming a source region on a first surface of the substrate, forming a drain region on the first surface of the substrate adjacent to the source region, depositing a silicide layer over the source region and drain region, forming a first interconnect layer over the silicide layer, forming a second interconnect layer over the first interconnect layer, and forming a UBM over and electrically connected to the second interconnect layer. The first interconnect layer includes a first runner connected to the source region and a second runner connected to the drain region. The second interconnect layer includes a third runner connected to the first runner and a fourth runner connected to the second runner. The method further includes the steps of disposing a mask over the substrate with an opening in the mask aligned over the UBM, depositing a conductive bump material within the opening, removing the mask, and reflowing the conductive bump material to form a bump.

In another embodiment, the present invention is a method of making a semiconductor device, comprising providing a substrate including a source region and an adjacent drain region, depositing a silicide layer over the source and drain regions, and forming a first interconnect layer over the silicide layer. The first interconnect layer includes a first runner connected to the source region and a second runner connected to the drain region. The method further includes the steps of forming a UBM over and electrically connected to the first interconnect layer, disposing a mask over the substrate with an opening in the mask aligned over the UBM, depositing a conductive bump material within the opening, removing the mask, and reflowing the conductive bump material to form a bump.

In another embodiment, the present invention is a method of making a semiconductor device, comprising providing a substrate, forming a transistor with a silicide layer on the substrate, forming a first interconnect layer over and connected to the transistor, forming a UBM over and connected to the first interconnect layer, disposing a mask over the substrate with an opening in the mask aligned over the UBM, and depositing a conductive bump material within the opening to form a bump.

In another embodiment, the present invention is a semiconductor device, comprising a substrate including a source region and an adjacent drain region. A silicide layer is disposed over the source and drain regions. A first interconnect layer is formed over the silicide layer. The first interconnect layer includes a first runner connected to the source region and second runner connected to the drain region. A UBM is formed over and electrically connected to the first interconnect layer. A bump is electrically connected to the UBM. The bump has a volume of conductive bump material determined by a volume of a mask opening.

DETAILED DESCRIPTION OF THE DRAWINGS

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 2illustrates electronic device50having a chip carrier substrate or PCB52with a plurality of semiconductor packages mounted on its surface. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 2for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 3a-3cshow exemplary semiconductor packages.FIG. 3aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as Al, Cu, tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and bond wires82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74or bond wires82.

FIG. 3billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Bond wires94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and bond wires94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 3c, semiconductor die58is mounted face down to intermediate carrier106with a flipchip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flipchip style first level packaging without intermediate carrier106.

FIGS. 4a-4tillustrate, in relation toFIGS. 2 and 3a-3c, steps in a process of forming a power MOSFET with an interconnect structure and a silicide layer formed over closely spaced transistors, and further including a low profile bump.FIG. 4ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support.

FIG. 4bshows a cross-sectional view of a portion of a substrate or semiconductor wafer120made of base substrate material122for the formation of a MOSFET cell124. Semiconductor wafer120includes a top surface130and bottom surface132that is opposite top surface130.

The MOSFET cell124can be an n-channel device (N-MOS) or a p-channel device (P-MOS), where “p” denotes a positive carrier type (hole) and “n” denotes a negative carrier type (electron). Although the present embodiment of MOSFET cell124is described in terms of a N-MOS device formed on a p-type substrate120, the opposite type semiconductor material can be used to form a P-MOS device. For example, an n-type substrate can be initially doped with n-type semiconductor material, such as phosphorus, antimony, or arsenic impurities, to form an n-well region. The present embodiment including p-type substrate120may further be deposited on top of a p-minus-type substrate.

InFIG. 4d, a polysilicon layer138is formed over insulating layer134. InFIG. 4e, photoresist layer140is formed over polysilicon layer138. A portion of photoresist layer140is removed by an etching process to form openings142in the photoresist layer and to expose a portion of polysilicon layer138. The remaining portion of photoresist layer140not removed in the etching process corresponds to a gate pattern, within MOSFET cell124.

InFIG. 4f, the portion of polysilicon layer138located within a footprint of openings142and outside photoresist layer140is removed by an etching process. A remaining portion of polysilicon layer138serves as a gate for later formed transistors within MOSFET cell124.

InFIG. 4g, a remainder of photoresist layer140is removed after the etching of polysilicon layer138.FIG. 4gfurther shows substrate120is doped with n-type semiconductor material, such as arsenic, to form lightly doped drain (LDD) regions144and146. The n-type dopant is deposited by ion implantation. The dosages of dopant introduced by the ion implantation can vary such that LDD regions144and146include n-minus LDDs and n-type regions.

InFIG. 4h, insulation layer150is formed around polysilicon layer138over insulation layer134. Insulation layer150also extends over a portion of LDD regions144and146. Insulation layer150contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. Insulation layer150is formed using PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of insulation layer134over LDD regions144and146is removed by an etching process using polysilicon layer138and insulation layer150as the mask. The remaining portion of insulation layer134extends beyond polysilicon layer138over LDD regions144and146and below insulation layer150. Insulation layer150also operates as a sidewall spacer to mask subsequent drain and source ion implantation. The placement of insulation layer150reduces an area of insulation layer134exposed by openings142, thereby forming openings152with an area less than the area of openings142.

InFIG. 4i, the portion of LDD regions144and146outside the mask formed by polysilicon layer138and insulation layer150(i.e., within openings152) is heavily doped to form source region160and drain region170. WhileFIG. 4ishows a single source region160and single drain region170, MOSFET cell124includes a plurality of source and drain regions160and170as shown in subsequent FIGs. Source regions160and drain regions170extend into wafer120farther than previously formed LDDs144and146, respectively. Accordingly, an area of LDD regions144and146is reduced by the formation of source regions160and drain regions170, such that LDD regions144and146occupy a reduced area located below insulation layer150and do not occupy the area within openings152. In one embodiment, the varying dosages of implantation used to form LDD regions144and146result in n-minus-type LDDs144and n-type regions146.

FIG. 4ifurther shows source region160is comprised of regions162,164, and166. Regions162,164, and166can be doped according to various configurations. In a first configuration, region162is doped as an n-plus-type region, region164is doped as a p-plus-type region, and region166is doped as an n-type region. In a second configuration, region164is doped as a p-plus-type region and regions162and166are doped as n-plus-type regions adjacent to either side of p-plus-type region164. Additionally, regions162and164of source region160can include LDDs144. On the other hand, LDDs144may be entirely absent from source region160. Drain region170, also formed inFIG. 4i, is doped as an n-plus-type region. Drain region170is disposed between n-type regions146.

InFIG. 4j, a silicide layer174is formed as a thin layer over source region160, over drain region170, and within openings152in passivation layer134. Silicide layer174includes WSi2, TiSi2, MoSi2, TaSi2, or other suitable silicides and is formed by using PVD, CVD, co-evaporation, sputtering, or other suitable process. When silicide layer174is formed by PVD, silicide layer174is self-aligned by depositing a refractory metal over semiconductor wafer120and heating the semiconductor wafer and refractory metal such that the silicide layer is formed where the refractory metal contacts the semiconductor wafer. Excess refractory metal that has not reacted to form a portion of the silicide layer is removed. Silicide layer174is formed on a top surface of source region160and on a top surface of drain region170. In one embodiment, silicide layer174has a thickness in the range of 100-3,000 angstroms. Silicide layer174serves as a metal conductor across the top surface of source and drain regions160and170. The presence of silicide layer174reduces overall cost of MOSFET cell124and serves as a metallization path that enhances current conduction by forming part of a low resistance electrical path from a later formed bump to source and drain regions160and170, respectively.

InFIG. 4k, an insulation layer or interlayer dielectric (ILD)180is formed over semiconductor wafer120, including over polysilicon layer138, insulation layer150, and silicide layer174. ILD180contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. ILD180is formed using PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of ILD180is removed by an etching process to form vias182. Vias182extend from a top surface of ILD180, through the ILD, and to silicide layer174to provide subsequent electrical connection to source region160, and drain region170. An electrical connection is also made with the gate electrode for MOSFET cell124at polysilicon layer138, which can include a connection with via182. Conductive material184is formed in vias182and over the exposed portions of silicide layer174to form conductive vias. Conductive material184includes tungsten (W), and may also include Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), polysilicon, or other suitable electrically conductive material, and is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.

FIG. 4lshows a top plan view of MOSFET cell124fromFIG. 4k. Source region160and drain region170of MOSFET cell124are formed in substrate120as interleaved stripes extending across substrate120. Source region160and drain region170are alternately spaced at intervals of a fixed distance, and are separated by polysilicon gate138.

Conductive material184is deposited in vias182to form conductive vias186over source region160and conductive vias188over drain region170. Conductive vias186and188provide electrical connection from source and drain regions160and170, respectively, to a first interconnect layer194.

The first interconnect layer194is formed over ILD180, over conductive pillars186and188, and over source and drain regions160and170. The first interconnect layer194includes source runners or conductive layers196and drain runners or conductive layers198. Source runners196and drain runners198can be one or more layers, and can be Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. Source runners196and drain runners198are patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process. Although source runners196and drain runners198shown inFIG. 4lare rectangular and of substantially equal widths, the runners can be of any shape. For instance, source runners196and drain runners198may be of unequal widths and runners may have varying narrow and wider portions and rounded corners. In one embodiment, first source and drain runners196and198include dimensions that are short and wide relative to conventional devices. Source runners196and drain runners198are interleaved and alternately spaced at intervals of a fixed distance, and are oriented substantially parallel with respect to each other. Source runners196and drain runners198are oriented substantially perpendicular or orthogonal with respect to source regions160and drain regions170. Alternatively, other non-perpendicular orientations (e.g., angled or parallel) may be used. The repeating interleaved or alternating intervals at which source runners196and drain runners198are oriented produce a unit structure distributed over the surface of semiconductor wafer120.

The source and drain runners196and198are electrically connected to source and drain regions160and170, respectively, through conductive vias186and188, respectively.FIG. 4lshows two vias186are used to form the electrical connection between source region160and source runner196at a location where the source region and source runner overlap. Similarly,FIG. 4lfurther shows two vias188are used to form the electrical connection between drain region170and source runner198at a location where the drain region and drain runner overlap. Alternatively, one conductive via, or more than two conductive vias can be used to connect source and drain regions160and170to source and drain runners196and198, respectively.

FIG. 4m, continuing fromFIG. 4k, shows a cross sectional view of MOSFET cell124and source runner196. Source runner196, fromFIG. 4l, is formed over and electrically connected to conductive via186.

InFIG. 4n, an insulation layer or ILD200is formed over first interconnect layer194and ILD180. ILD200contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. ILD200is formed using PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of ILD200is removed by an etching process to form vias202. Vias202extend from a top surface of ILD200, through the ILD, to first interconnect layer194. Conductive material204is formed in vias202and over the exposed portions of first interconnect layer194to form conductive vias. Conductive material204includes W, and may also include Al, Cu, Sn, Ni, Au, Ag, Ti, polysilicon, or other suitable electrically conductive material, and is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.

FIG. 4oshows a top plan view of the partially formed semiconductor device fromFIG. 4n. Conductive material204formed in vias202results in conductive vias206formed over source runners196and conductive vias208formed over drain runners198. Conductive vias206and208provide electrical connection from source and drain runners196and198, respectively, to a second interconnect layer214.

The second interconnect layer214is formed over ILD200, over conductive pillars206and208, and over first interconnect layer194. The second interconnect layer214includes source runners or conductive layers216and drain runners or conductive layers218. Source runners216and drain runners218can be one or more layers, and can be Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. Source runners216and drain runners218are patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process. Although source runners216and drain runners218shown inFIG. 4oare of substantially equal widths and rectangular, the runners can be of any shape. For instance, source runners216and drain runners218may be of unequal widths and runners may have varying narrow and wider portions and rounded corners. In one embodiment, second source and drain runners216, and218include dimensions that are short and wide relative to conventional devices. Source runners216and drain runners218are interleaved and alternately spaced at intervals of a fixed distance, and are oriented substantially parallel with respect to each other. Source runners216and drain runners218are oriented substantially perpendicular or orthogonal with respect to source runners196and drain runners198. Alternatively, other non-perpendicular orientations (e.g., angled or parallel) may be used. The repeating interleaved or alternating intervals at which source runners216and drain runners218are oriented produce a unit structure distributed over source runners196and drain runners198, as well as over the surface of semiconductor wafer120.

Source and drain runners216and218are electrically connected to source and drain runners196and198, respectively, through conductive vias206and208, respectively.FIG. 4oshows two vias206are used to form the electrical connection between source runner196and source runner216at a location where source runners196and216overlap. Similarly,FIG. 4ofurther shows two vias208are used to form the electrical connection between drain runners198and218at a location where the drain runners overlap. Alternatively, one conductive via, or more than two conductive vias can be used to connect source and drain regions160and170to source and drain runners196and198, respectively.

FIG. 4p, continuing fromFIG. 4n, shows a cross sectional view of MOSFET cell124and source runner216and drain runners218. Source runner216, fromFIG. 4o, is formed over and electrically connected to conductive vias206.

InFIG. 4q, an insulation layer or ILD220is formed over second interconnect layer214and ILD200. ILD220contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. ILD220is formed using PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of ILD220is removed by an etching process to form vias222. Vias222extend from a top surface of ILD220, through the ILD, to second interconnect layer214. Conductive material224is formed in vias222and over the exposed portions of second interconnect layer214to form conductive vias. Conductive material224includes W, and may also include aluminum Al, Cu, Sn, Ni, Au, Ag, Ti, polysilicon, or other suitable electrically conductive material using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.

FIG. 4rshows a top plan view of the partially formed semiconductor device fromFIG. 4q. Conductive material224formed in vias222results in conductive vias226formed over source runners216. Conductive vias226provide electrical connection from source runners216to a third interconnect level234. Source pad236is formed at the third interconnect level234over ILD220, over conductive pillars226, and over second interconnect layer214. Source pad236can be one or more layers of Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. Source pad236is patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process.

Source pad236is configured to be connected to a later formed source bump which provides electrical connection between source region160and devices external to MOSFET cell124. Similarly, conductive material224formed in vias222and over drain runners218provide electrical connection from drain runners218to a drain pad. The drain pad is configured to be connected to a later formed drain bump which provides electrical connection from drain region170to devices external to MOSFET cell124.

FIG. 4s, continuing fromFIG. 4q, shows a cross sectional view of MOSFET cell124and source pad236. Source pad236, fromFIG. 4r, is formed over and electrically connected to conductive vias226. An electrically conductive bump material is deposited over source pad236to form source bump or interconnect240, as is described in additional detail inFIGS. 6a-6i. Source bump240provides electrical connection from source region160to devices external to MOSFET cell124. Source bumps240represent one type of interconnect structure that can be formed over source pad236. Source bump or interconnect240can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

FIG. 4tshows an isometric three dimensional view of MOSFET cell124. The first interconnect layer194, second interconnect layer214, and conductive vias provide electrical interconnection from source and drain regions160and170to source and drain pads at the third interconnect level234. Thus, the problem of connecting small closely aligned transistors formed across an entire surface of a semiconductor die with both source and drain connections located under a single source pad or drain pad is solved. Rather than using strictly vertical interconnects which would connect transistor source and drain regions to a single source or drain pad, conductive runners are configured to connect transistor source regions and drain regions under a single pad to multiple corresponding pads. Thus, transistor drain regions are connected to drain pads, and transistor source regions are connected to source pads. Specifically, source region160is electrically connected to source bump240by source pad236, conductive vias186, source runner196, conductive via206, source runner216, and conductive vias226. Similarly, drain region170is electrically connected to a drain pad by conductive vias188, drain runner198, conductive vias208, drain runner218, and additional conductive vias extending from drain runner218to the drain pad.

Silicide layer174is formed over source region160and drain region170. Silicide layer174is formed on the top surfaces of source region160and drain region170. Silicide layer174serves as a metal conductor across the top surface of source and drain regions160and170to reduce overall cost of MOSFET cell124and serve as a metallization path to enhance current conduction as part of a low resistance electrical path from source and drain regions160and170, respectively, to later formed bumps.

FIG. 5ashows an isometric three dimensional view of a power MOSFET258including a plurality of MOSFET cells, such as MOSFET cells124fromFIG. 4t. Power MOSFET258contains hundreds or thousands of MOSFET cells124. InFIG. 5a, detail of MOSFET cells such as the detail of MOSFET cell124shown inFIG. 4t, including source region160, drain region170, and polysilicon gate138, as well as first interconnect layer194, second interconnect layer214, and conductive vias including conductive vias186,188,206,208, and226are not explicitly shown, but are included within power MOSFET258below source bumps240, drain bumps246, and gate bump250.FIG. 5afurther shows source bumps240formed over source pads236, drain bumps246formed over drain pads244, and a gate bump250formed over gate pad248. In the embodiment shown inFIG. 5a, source pads236and drain pads244are arranged in a checkerboard configuration across a top surface of power MOSFET258. Electrical connections for the plurality of MOSFET cells124are routed through the plurality of source pads236, drain pads244, and gate pads248. Power MOSFET258contains arrays of interconnected MOSFET cells that cover most of the die or package area within each power MOSFET258. Each power MOSFET258operates as a single monolithic switching device capable of handling many amperes of electrical current.

FIG. 5bshows an alternate isometric three dimensional view of power MOSFET259similar to power MOSFET258shown inFIG. 5a. Source pads237and a drain pad245shaped as “stripes” are interleaved and alternately spaced at intervals of a fixed distance, and are oriented substantially parallel with respect to each other. Gate pad249is formed over a top surface of power MOSFET259in-line with a shortened source pad237or a shortened drain pad245according to the configuration and design of the power MOSFET.FIG. 5bfurther shows source bumps241formed over source pads237, drain bumps247formed over drain pads245, and a gate bump251formed over gate pad249.

FIG. 5cshows a top plan view of semiconductor wafer120fromFIG. 4afurther including a plurality of power MOSFETs258. Power MOSFETs258are formed on base substrate material122and are separated by saw streets260as described above.

FIG. 6ashows a cross-sectional view of a portion of semiconductor wafer120, including portions of multiple MOSFET cells124belonging to separate power MOSFETs258separated by saw street260. Both a source contact pad236and a drain contact pad244are shown at the third interconnect level234over MOSFET cells124. Detail of MOSFET cells124shown inFIG. 4t, including source region160, drain region170, and polysilicon gate138, as well as first interconnect layer194, second interconnect layer214, and conductive vias including conductive vias186,188,206,208, and226are not explicitly shown, but are included below source pad236and drain pad244. Before a source bump is formed over source pad236, and before a drain bump is formed over source pad244, a number of intervening layers are formed over the source and drain pads. Specifically, an insulation or passivation layer270is conformally applied to the semiconductor device at the third interconnect level234over a top surface of MOSFET cells124, source contact pad236, drain contact pad244, and saw streets260. A bottom surface of insulation layer270is conformally applied to and follows a contour of a bottom surface of the third interconnect level, source contact pad236, and drain contact pad244. A top surface of insulation layer270is substantially planar such that the insulation layer has a first thickness over semiconductor wafer120outside a footprint of source pad236and drain pad244, and a second thickness over semiconductor wafer120within a footprint of source pad236and drain pad244. The first thickness is greater than the second thickness. The insulation layer270can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, zircon (ZrO2), Al2O3, polyimide, BCB, PBO, or other material having suitable electrical insulating properties. The insulation layer270is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering with curing, or thermal oxidation. A portion of insulation layer270is removed by an etching process to create openings272in insulation layer270which expose a portion of source pad236and drain pad244. Openings272extend from a top surface of insulation layer270to a bottom surface of the insulation layer. In one embodiment, opening272has a width of 270 μm, analogous to the width of opening20fromFIG. 1a. Another portion of source pad236and drain pad244remains covered by insulation layer270.

InFIG. 6b, an electrically conductive layer278is formed over and conformally applied to source pad236and drain pad244and over a portion of insulation layer270by using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. In one embodiment, wafer120is immersed into an electroless nickel plating solution and nickel is plated on source pad236and drain pad244to a thickness of 3 μm. Alternatively, conductive layer278can be one or more layers of Al, Cu, Sn, Au, Ag, or other suitable electrically conductive material. Conductive layer278extends across a top portion of, and follows the contours of, the top surface of insulation layer270, along a side wall of insulation layer270at a periphery of opening272, and across the top surface of source pad236and drain pad244within opening272. Conductive layer278includes an area280that is within a footprint of opening272and over source pad236and drain pad244. Area280is substantially flat and is smaller than an entire area of source pad236and drain pad244, respectively. Conductive layer278operates as a first UBM layer for a later formed bump.

InFIG. 6c, an electrically conductive layer284is formed over and conformally applied to conductive layer278using a deposition process such as electroless plating or a patterning and metal deposition process such as printing, PVD, CVD, sputtering, and electrolytic plating. In one embodiment, wafer120is immersed into an electroless gold plating solution and a layer of gold with a thickness of approximately 100 angstroms is plated on the exposed metal regions of conductive layer278with an electroless plating process. In another embodiment, the layer of gold is plated with a thickness of 10-300 angstroms. Alternatively, conductive layer284can be one or more layers of Al, Cu, Sn, Ni, Ag, or other suitable electrically conductive material. Conductive layer284follows the contours of conductive layer278across the surfaces of conductive layer278exposed from insulation layer270, source pad236, and drain pad244. Conductive layer284extends across sidewalls of conductive layer278from insulation layer270to, and across, a top surface of insulation layer270and into and across area280of conductive layer278. A top surface of conductive layer284includes an area286that is substantially flat, formed over source pad236and drain pad244, and is both smaller than, and included within a footprint of, area280. Conductive layer284acts as a second UBM layer that serves as an adhesion layer to aid in the later attachment of a conductive bump to conductive layer278, source pad236, and drain pad244. While the use of conductive layers278and284is a low cost method of forming a UBM, other methods may also be used to form a UBM over source pad236and drain pad244to aid in the later attachment of a conductive bump.

InFIG. 6d, a stencil or masking layer288with openings290is disposed over wafer120such that openings290align with and expose central portions of areas286. Stencil288includes a rigid body with a solid surface and is made of metal or other suitable material. Stencil288is disposed over an entirety of wafer120and includes openings290which are formed by a laser or cutting tool at desired locations to align with UBM sites configured to receive later formed bumps. Openings290are aligned over a central portion of areas286such that a portion of stencil288is disposed over a peripheral portion of conductive layers278and284to separate openings290from passivation layer270. By separating openings290and passivation layer270, later formed conductive material is prevented from spreading or flowing under passivation layer270. Openings290have a height and width formed to contain a predetermined volume of a later deposited conductive paste according to the design and function of the semiconductor package. Accordingly, the volume of later deposited conductive material on area286is determined by a thickness of the stencil and a cross sectional area or aperture size of openings290. In one embodiment, openings290have a circular cross sectional area configured to form conductive bumps with a cylindrical shape including a short height and a circular cross section. In another embodiment, openings290have a width less than 270 μm which is less than the width of opening272in insulation layer270.

InFIG. 6e, an electrically conductive bump material294is deposited within openings290and over a central portion of area286. Conductive bump material294can be Al, Sn, Ni, Au, Ag, Pb, bismuth (Bi), Cu, indium (In), solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. Conductive bump material294is deposited by stenciling the bump material onto conductive layer284within openings290. Stenciling is accomplished by using an object such as a squeegee to force quantities of bump material294into openings290as the object moves across a top surface of stencil288. Stenciling is also accomplished by spraying, painting, or brushing conductive bump material294into openings290within stencil288. Alternatively, conductive bump material294can be injected into openings290. By stenciling conductive bump material294onto wafer120and over MOSFET cells124, rather than stenciling conductive paste onto a circuit board, a correct location for conductive bump material294is provided such that the bump material for forming conductive bumps over a semiconductor die can be deposited for the entire semiconductor wafer120in a single step. Furthermore, a volume of conductive bump material294deposited on conductive layer284is controlled by a thickness of stencil288and a cross sectional area or aperture size of opening290, thereby controlling a final size of the later formed conductive bump.

InFIG. 6f, stencil288is removed from over wafer120leaving a volume of conductive bump material294on a central portion of area286and over conductive layers278,284, source pad236, and drain pad244. The resulting volume of solder material that remains over conductive layers278,284, source pad236, and drain pad244will be less than a volume of conductive material from a preformed solder ball used in a ball drop process that has a predetermined diameter corresponding to a width of source pad236and drain pad244.

InFIG. 6g, the conductive bump material294is reflowed by heating the material above its melting point to form a short conductive bump298. In some applications, bump298is reflowed multiple times to improve electrical and mechanical connections including contact with conductive layers278and284. Subsequent reflows of bumps298further include: reflowing bumps298while connected to MOSFET cell124in order to connect MOSFET cell124and bumps298to a later provided substrate, reflowing bumps298when mounting MOSFET cell124to an additional later provided substrate or multilayered PCB, and reflowing bumps298for the mounting of additional components to, or rework of, the additional later provided substrate or multi-layered PCB. When reflowing conductive paste294, the conductive paste travels outward from the central portion of area286and contacts a sidewall of conductive layer284at a periphery of the conductive layer and contacts a portion of insulation layer270adjacent to the periphery of conductive layer284. The spreading of conductive paste294from a first width substantially equal to a width of opening290to a second width substantially equal to a width of conductive layer284results in short conductive bump298. Bump298has a rounded profile with a width that is greater than a width of conductive paste294and a height that is less than a height of the conductive paste deposited in opening290. In one embodiment, conductive bumps298have a width 300 of approximately 300 μm, a spacing between bumps of approximately 200 μm, and a pitch of approximately 500 μm. However, the pitch of openings290and the corresponding pitch of bumps298can be made much smaller. Additionally, bumps298have a height302of approximately 70 μm. The resulting short bump298has a wider contact area over source pad236and drain pad244than a contact area of a preformed spherical solder ball of substantially equal height. Similarly, short bump298has a height, e.g., 70 μm, which is substantially smaller than a preformed spherical ball with a similar width, e.g., 300 μm. Accordingly, the configuration of bumps298provides improved flow of electrical current with respect to preformed spherical solder balls of substantially similar height.

FIG. 6hshows a plan or top view of short bumps298formed over source pad236and drain pad244, insulation layer270, conductive layer278, and conductive layer284. As noted above, in one embodiment source pad236, drain pad244, conductive layer278, and conductive layer284have circular cross sections such that reflowed bumps298include a cylindrical shape having a short height and a circular cross section.

InFIG. 6i, semiconductor wafer120is singulated through saw streets260with saw or laser cutting tool306to form individual power MOSFETs258with a plurality of short bumps298.

FIG. 7ashows another embodiment of the present invention, similar to the embodiment shown inFIGS. 4a-4t.FIG. 7ashows an isometric three dimensional view of MOSFET cell310. MOSFET cell310includes source regions314and drain regions316similar to source regions160and drain regions170shown inFIG. 4t. However, source regions314and drain regions316are shown configured in a “checkerboard” pattern across MOSFET cell310rather than as “stripes” as shown inFIG. 4t.

The first interconnect layer322is formed over MOSFET cell310, over conductive vias320, and over drain regions316. First interconnect layer322includes a conductive plane324, that further includes openings or cutouts328and connections330. Conductive plane324is one or more layers of Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. Conductive plane324is patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process. Conductive plane324electrically connects to source regions314through conductive vias320, and operates as a source connection layer. Openings328in conductive plane324are formed by removal of a portion of the conductive plane. By removing a portion of conductive plane324in a periphery of connection300, connection300is electrically isolated with respect to the conductive plane324, and is configured for subsequent vertical electrical connections to pass from above first interconnect layer322to below the first interconnect layer without contacting conductive plane324.

The second interconnect layer338is formed over MOSFET cell310, over source regions314and drain regions316, over conductive vias320,334, and336, and over connections330. Second interconnect layer338includes a conductive plane340, the conductive plane further includes openings342and connections344. Conductive plane340is one or more layers of Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. Conductive plane340is patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process. Conductive plane340electrically connects to drain regions316through conductive vias334, connections330, conductive vias336, and operates as a drain connection layer. Openings342in conductive plane340are formed by removal a portion of the conductive plane. By removing a portion of conductive plane340in a periphery of connection344, connection344is electrically isolated with respect to conductive plane340, and is configured for subsequent vertical electrical connections to pass from above second interconnect layer340to below the second interconnect layer without contacting conductive plane340.

The third interconnect layer, similar to source pad236shown as a third interconnect layer inFIGS. 4rand4s, is formed over MOSFET cell310, over source regions314and drain regions316, over conductive vias320,334,336, and346, over connections330and344, and over first and second interconnect layers322and338. The third interconnect layer includes a source pad that is one or more layers of Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. The source pad is patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process. The source pad is configured to be connected to a later formed source bump which provides electrical connection between drain region316and devices external to MOSFET cell310.

An electrically conductive bump material is deposited over the source pad to form a source bump or interconnect, as described above inFIGS. 6a-6i. The drain bump provides electrical connection from drain region316to devices external to MOSFET cell310. The source bump represents one type of interconnect structure that can be formed over the source pad. The source bump or interconnect can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

FIG. 7cshows a top plan view of conductive plane340with openings342to electrically connect source regions314to conductive vias320, conductive plane324, conductive via346, and connections344.

FIG. 8shows another embodiment of the present invention, similar to the embodiments shown inFIGS. 4a-4t, andFIGS. 7a-7c.FIG. 8shows a top plan view of an interconnect layer350, similar to interconnect layers disposed at interconnect levels194,214, and234inFIGS. 4l-4t, and interconnect layers322and338inFIGS. 7a-7c. Each interconnect layer350includes source runners or conductive layers354and drain runners or conductive layers356. Source runners354and drain runners356can be one or more layers, and can be Cu, Sn, Ni, NiV, Au, Ag, Al or other suitable conductive material. Source runners354and drain runners356are patterned and deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable metal deposition process. Source runners354and drain runners356are cross-shape (+) and establish electrical connections with adjacent source regions, drain regions, or adjacent interconnect layers. Source runners354and drain runners356may be of shapes other than a cross-shape (+), such as an L-shape (L) and a T-shape (T).

Source runners354and drain runners356are arranged in a repeating pattern having a constant pitch, or distance between center points of adjacent runners. Similarly, additional structures connected to source runners354and drain runners356, such as conductive vias and source bumps, or other interconnect layers, are also arranged in a repeating pattern having a constant pitch between center points. The repeating interleaved or alternating intervals at which source runners354and drain runners356are oriented produce a unit structure distributed over the surface of a semiconductor wafer over which the source and drain runners are formed.

Each interconnect layer350can be used as a first, second, third, or other interconnect level. More than two or three interconnect layers may be used, and intermediate interconnect layers can be formed between first and second interconnect layers, or between second and third interconnect layers. Additional intermediate interconnect layers assist in the routing of electrical signals and decrease the pitch of source and drain bumps or interconnects. As a first interconnect level, interconnect level350is electrically connected to conductive vias and to source and drain regions. Source runners354and drain runners356electrically connect any desired number of chip-side conductive elements. In one embodiment, the cross shaped runners are electrically connected to conductive vias that contact a group of five source or drain regions. One via is located at a center of the cross shaped runner where the two orthogonal portions of the cross overlap, and four vias are located at the four distal ends of the cross shaped runners. Source runners354and drain runners356electrically connect to source regions and drain regions, respectively. Alternatively, source runners354and drain runners356need not connect source and drain regions of an integrated device, but in another embodiment can electrically connect to various discrete components. As a second interconnect level, interconnect level350is formed over source and drain regions, over conductive pillars, and over first interconnect layer. As a second interconnect level, interconnect level350can also be disposed under conductive vias, under a third interconnect level, and under a later formed bump which provides electrical connection to devices external the MOSFET cell. As a third interconnect level, interconnect level350is configured to be connected to later formed source and drain bumps or interconnects, as shown for example inFIGS. 6a-6i, which provide electrical connection between the second interconnect layer and devices external the MOSFET cell. In one embodiment, source and drain bumps fromFIGS. 6a-6iare attached at the center of the cross-shape (+) source runners354and drain runners356. Source and drain bumps or interconnects also include bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

FIG. 9shows another embodiment of the present invention, similar to the embodiment shown inFIGS. 4a-4t,FIGS. 7a-7c, andFIG. 8.FIG. 9shows an isometric three dimensional view of MOSFET cell360. MOSFET cell360includes source region372and drain region374similar to source region160and drain region170shown, e.g., inFIG. 4t. A polysilicon layer364, similar to polysilicon layer138fromFIG. 4d, is formed over semiconductor wafer362. A portion of polysilicon layer364is removed by an etching process and a remaining portion of polysilicon layer364, shown inFIG. 9, serves as a gate for transistors within MOSFET cell360. An insulation layer366, similar to insulation layer150fromFIG. 4h, is formed around polysilicon layer364and extends over a portion of source region372and drain region374. A silicide layer368, similar to a silicide layer174inFIG. 4j, is formed as a thin layer over source region372and drain region374.

First interconnect layer382is formed over MOSFET cell360, over conductive vias378and380, and over source region372and drain region374. First interconnect layer382includes source runners or conductive layers384, and drain runners or conductive layers386, similar to source runners196and drain runners198fromFIG. 4land similar to source runners216and drain runners218fromFIG. 4o. Source runners384are formed over, and electrically connected to, source region372with conductive vias378. Drain runners386are formed over, and electrically connected to, drain region374with conductive vias380. Source runners384are also electrically connected to conductive vias formed over source runners384, similar to conductive vias226shown inFIG. 4r. Drain runners386are also electrically connected to conductive vias390, formed over drain runners386and electrically connected to a second interconnect layer394.

The second interconnect layer394, similar to source pad236shown as a third interconnect layer inFIGS. 4rand4s, is formed over MOSFET cell360. The second interconnect layer394is also formed over source region372and drain region374, over conductive vias378,380, and390, and over the first interconnect layer382including source runners384and drain runners386.FIG. 9shows second interconnect layer394formed as drain pad396that is connected to drain bump398to provide electrical connection between drain region374and devices external to MOSFET cell360. Drain bump398is formed over drain pad396as described above inFIGS. 6a-6i. The drain bump provides electrical connection from drain region374to devices external to MOSFET cell360. The drain bump represents one type of interconnect structure that can be formed over drain pad396. The source bump or interconnect398also includes bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

FIG. 10ashows singulated power MOSFET cell400, similar to power MOSFET258fromFIGS. 5aand6i, or power MOSFET259fromFIG. 5b, with short conductive bumps401being mounted to a substrate or multilayered PCB402with bumps401oriented toward the substrate. Substrate402provides general structural support and electrical interconnect for power MOSFET400when the power MOSFET is mounted to the substrate. Substrate402further includes conductive contacts404.

InFIG. 10b, power MOSFET400is mounted to substrate402. No underfill material is deposited around bumps401or between substrate402and power MOSFET400. Bumps401undergo multiple reflows to improve electrical and mechanical connections. The multiple reflows of bumps401include reflowing bumps401for connecting the bumps to power MOSFET400, reflowing bumps401while connected to power MOSFET400to connect power MOSFET400and bumps401to substrate402, reflowing bumps401when mounting substrate402to an additional substrate or multilayered PCB, and reflowing bumps401for the mounting of additional components to, or rework of, the additional substrate or multi-layered PCB. Significantly, a risk of bumps401bridging and electrically shorting, even without an underfill material, is reduced due to the reduced height of bumps401with respect to traditional spherical bumps like bumps28shown inFIG. 1b. The reduced volume of bump material present in bumps401tends to stay in place over UBM layers during reflow without spreading to contact other bumps and causing electrical shorting. Therefore, the need for underfill material is reduced and the difficulty of underfill material causing semiconductor die cracking and failure is mitigated.

Encapsulant408is formed over substrate402, and over and around power MOSFET400using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. Encapsulant408can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant408is non-conductive, provides physical support, and environmentally protects power MOSFET400from external elements and contaminants. A portion of encapsulant408extends at least partially between power MOSFET400and substrate402, especially near a perimeter of power MOSFET400. Encapsulant408can also extend completely under power MOSFET400to completely fill the void between power MOSFET400and substrate402. A risk of power MOSFET400shifting due to placement of encapsulant408is reduced due to the reduced height and low profile of bumps401. Additionally, the problem of mechanical, thermal, and chemical stresses caused by non-uniform underfill material is not present with a uniformly deposited encapsulant. The configuration of package410, including power MOSFET400mounted to substrate402with short conductive bump401, creates a shorter electrical path between the transistors of power MOSFET400and substrate402than with traditional spherical bumps. The shorter electrical path results in lower resistance and less inductance, especially with high frequency applications. The shorter electrical path also results in increased thermal performance of power MOSFET400due to the reduced standoff height between the power MOSFET and substrate402that allows heat from the power MOSFET to be transferred to the substrate more readily. Therefore, the configuration of package410, including the attachment of power MOSFET to a substrate with short conductive bumps without underfill molding, reduces the problem of solder bridging and shorting among bumps while maintaining robust electrical connections thereby increasing yield and reliability.