Printed circuit board and method for manufacturing same

A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. national stage application of International Patent Application No. PCT/KR2011/010058, filed Dec. 23, 2011, which claims priority to Korean Application Nos. 10-2010-0134543, filed Dec. 24, 2010, and 10-2011-0052487, filed May 31, 2011, the disclosures of each of which are incorporated herein by reference in their entirety.

BACKGROUND

The present invention relatives to a printed circuit board and a method for manufacturing the same.

The printed circuit board (PCB) refers to print the circuit pattern on an electrical insulating substrate using a conductive materials such as copper, particularly means a board just before mounting electronic components.

That is, in order to densely mount various types of electronic elements on a flat panel, the printed circuit board means a circuit board for confirming a mounting location of each part, printing and fixing the circuit pattern connected to the part on the flat panel

A demand for a high performance, a compact, a cost-competitive and a period for payment in an electronics industry increases according to a development of the electronics industry. In response to these trends, a printed circuit board companies achieves a thin and densification of the printed circuit board using semi additive process (SAP).

FIG. 1a. to1eare a cross-section showing a bump manufacturing process in a typical printed circuit board.

First, a first metal layer2is formed on insulation board (an insulating plates1as shown inFIG. 1a.

In addition, the first metal layer2may be made of copper, nickel or an ally thereof.

If the first metal layer2is formed, a first mask pattern is formed on the first metal layer2.

And then, the pad4is formed by electroplating the first metal layer3using first metal layer2as seed layer, centering on the first mask pattern

Then, a pad4is formed by electrolytic plating a first metal layer as a seed layer around the formed first mask pattern3.

When the pad4is formed, an unnecessary part2, for example the first metal layer2and a first mask pattern3is removed through a peeling and etching process.

Then, a solder resist5exposing the formed pad4is formed on the insulating substrate1formed with the pad4.

Then, the second metal layer6is formed on the doped solder resist5as shown inFIG. 1cand a second mask pattern7is formed on the formed second metal layer6.

In this case, a surface treatment of the solder resist5is performed to ensure adhesion force between the sold resist5and the second metal layer6.

After this, as shown inFIG. 1d, a bump8is formed on the pad4and then the unnecessary parts, for example the second metal layer6and the second mask pattern7are removed through the peeling and etching process as shown inFIG. 1e.

According to the prior art, a diameter of the bump8is formed larger than opening section of the solid resist5.

However, as described above, when the bump is formed, an interval between neighboring bumps becomes narrow, so that it is highly likely that a bad connection will occur

BRIEF SUMMARY

The present embodiment is to provide a printed circuit board and a method for manufacturing the same capable of minimizing an interference between adjacent bumps.

The embodiment is to provide a printed circuit board and a method for manufacturing the same having a novel bump shape.

A technical problem for being resolved by the present invention is not limited to the above-mentioned problem and those having the art will be clearly understand that there are other problems that are not mentioned above through the following description.

A printed circuit board according to a embodiment of then present invention includes an insulating layer; a pad formed on the insulating layer and exposed through an opening section of a solder resist; a bump formed on the pad and filling the opening section of the solder resist and having an narrow width than the opening section of the solder resist.

In addition, the bump fills the opening section of the solder resist and protrudes from a surface of the solder resist in a predetermined height.

In addition, the printed circuit board further includes a bump connection section formed between the pad and the bump to electrically connect the pad and the bump section.

Furthermore, the bump is formed narrower than the width of an upper surface of the bump connection section.

Moreover, the bump has a narrow width than an upper surface of the pad and the bump is formed such that a width of the upper surface thereof and a lower surface opposite the upper surface is equal.

In addition, the bump of the printed circuit board has a square pillar in shape.

Moreover, the bump of the printed circuit board is made of alloy containing copper.

Meanwhile, a method for manufacturing a print circuit board according to a embodiment of the present invention includes forming a pad on an insulating substrate; applying a solder resist having an opening section exposing the formed pad on the insulating substrate; forming a mask having a window for opening of the opening section of the solder resist on the solder resist; and forming a bump for filling a portion of the opening of the solder resist and the window by performing a plating.

In addition, in a manufacturing method of the printed circuit board, the pad is formed by etching or plating process.

Moreover, the manufacturing method of the printed circuit board further includes forming a bump connecting section electrically connecting the pad and the bump by performing the plating.

In addition, the method further comprises forming a bump connecting section for electrically connecting of the pad and the bump by performing the plating.

In addition, forming the mask on the solder resist comprises forming the mask having the window of narrow width than opening section of the solder resist.

In addition, the forming the bump comprises forming the bump having a narrow width than the upper surface of the formed pad.

Moreover, forming the bump comprises forming the bump such that the width of the upper surface and a lower surface opposite the upper surface is equal.

In addition, the bump is a cylinder pillar, a square pillar and a polygonal pillar in shape.

Moreover, a manufacturing method of the printed circuit board further includes forming solder for filling the window on the formed bump.

In addition, the method further comprises forming solder for filling the window on the formed bump.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A printed circuit board according to an embodiment of the present invention will be described with reference toFIGS. 2 to 14.

FIG. 2is a cross-section of the printed circuit board according to an embodiment of the present invention.

The invention provides to an economic and reliable circuit board to use a seed layer to form a circuit pattern on an insulating layer and to use the same seed layer as the seed layer used at the time of the formation of the circuit pattern to form a bump on the circuit pattern.

Referring toFIG. 2, the printed circuit board100according to an embodiment of the present invention includes an insulating plate110, a pad120connected to a circuit pattern (not shown) formed on the insulating plate110, a solder resist130covering the pad120and the circuit pattern; a plating seed layer140formed in an inner wall of the solder resist130, a bump connection section150formed in the pad120to fill the opening section135of the solder resist130, a bump160formed on the bump connection section and a solder formed on the bump.

The insulting plate110may a support plate of the printed circuit board100formed with single circuit pattern, but can mean insulating layer formed with a circuit pattern (not shown) of the printed circuit board having a plurality of a stack structures.

When the insulating plate100means one insulating layer of a plurality of stack layer structures, a plurality of circuit patterns (not shown) are successively formed at an upper portion or a lower portion of the insulating plate110.

The insulating plate100may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, organic-inorganic composite material substrate or glass fibers impregnated substrate and if the insulating plate includes a polymer resin, this may contains epoxy insulating resin, otherwise may contain polyimid resin.

The plurality of pads120capable of connecting to a plurality of circuit patterns is formed on the insulating plate110. The pad120is a bump mounted on the printed circuit board100and means a pad120attached with the solder170.

The pad120is made of a conductive material and may be made of alloy containing copper if a copper thin layer formed on the insulating plate110is pattered to form the circuit pattern,

In addition, the pad120may be formed by selectively removing the plating layer formed on the insulating plate110by a non-electrolytic plating.

The circuit pattern is covered on the insulating plate110and the solder resist130is formed.

The solder resist130serves to protect the surface of the insulating plate110and has an opening portion135for opening an upper surface of the pad120to be exposed.

The plating seed layer140is formed at a side surface of the formed solder resist130.

The plating seed layer140is formed at a side surface of the opening section135of the solder resist130to be exposed.

The plating seed layer140is a seed for forming the bump connection section formed on the plating seed layer150and may an alloy having a high adhesion to copper as copper or nickel if bump connection150is made of copper.

In addition, the plating seed layer140may be on the solder resist130formed by chemical copper plating.

The opening section135of the solder resist130is filled on the plating seed layer140and the bump connection150is formed.

The bump connection150is formed to be protruded from the upper surface of the solder resist130and may be formed at the same height as the upper surface of the solder resist130.

The bump connection150may be formed by the electrolytic copper plating using seed layer140as seed.

The bump connection150may be formed by performing electro clad plating using the seed layer140as a seed.

The bump connection150may be formed by performing the electrolytic copper plating the seed layer140as a seed.

The bump160is formed on the bump connection150.

The bump160is formed to protrude from the upper surface of the solder resist130.

In this case, the bump160is formed in at least any one of shape of cylinder pillars, a square pillars and motile pillars, which a width of the upper surface and the lower surface opposite the upper surface is the same.

That is, the bump160has a shape of the square pillar130and is formed to protrude from the upper surface of the solder resist to easily perform a formation of solder170.

In this case, the bump160is formed at an inner side of the opening section135of the solder resist130and is formed to have a narrow width than the opening section135of the solder resist130.

That is, as shown inFIG. 1, when the width of the opening section135of the solder resist130is A, the bump is formed to have a narrow width B than the width A.

According to the prior art, the bump is formed such that an area protruding from the solder resist130is expanded to have a larger width than the opening section135.

In this case, when the bump is formed as described above, the solder formed on the bump is formed to have the width greater than the opening section, so that an interval between adjacent solders become narrow, thereby causing the bad connection due to a contact between the solders.

Therefore, in the present invention, the width of the bump160is formed narrow than the width solder resist130and the solder170is formed at the same width as the width of the solder resist, thereby maximizing the interval between adjacent solders.

The solder170is formed on the bump160. The solder170has a round shape by a surface tension by reflowing and melting to contact with the element.

The solder170includes more than binary metal and the binary metal is alloy containing Sn, specifically, an alloy containing Sn—Cu.

The printed circuit board100forms a narrow width of the bump160than that of the opening section of the solder resist.

In the printed circuit board100according to a embodiment of the present invention, the width of the bump160is formed narrower than that of the opening section135included in the solder resist180, so that the adjacent solder between the interval is maximized, thereby preventing a bad connection caused by the contact between the adjacent solders.

FIGS. 3 to 13is a cross-section showing a method for manufacturing the printed circuit board100according to an embodiment of the present invention.

In this case, the metal layer115may be formed by the non-electrolyte plating of the metal including copper on the insulating plate110.

The insulating plate100may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, organic-inorganic composite material substrate or glass fibers impregnated substrate and if the insulating plate includes a polymer resin, this may contains epoxy insulating resin, otherwise may contain polyimid resin.

In addition, the metal115may use copper clad laminate (CCL) unlike the method for forming the metal layer on the insulating plate110by the non-electrolyte plating.

Moreover, if the metal layer115is formed by the non-electrolyte plating, the plating may be performed smoothly by providing the top of surface roughness of an insulating plate110.

Subsequently, as shown inFIG. 4, a conductive layer115forming on the insulating plate110is selectively removed to form the circuit pattern (not shown) or the pad120.

In this case, the conductive layer115forming in the insulating plate may be formed at upper surface of the insulating plate110and an lower portion of the insulating plate110and therefore the circuit pattern (not shown) and the pad120may also formed at the lower surface.

Thus, the circuit pattern and pad120is formed in at least one side of the insulating plate110and the solder resist130to fill the formed circuit pattern to the insulating plate110is coated as shown inFIG. 5.

In this case, the solder resist130is formed to include the opening section135exposing the pad120and the opening section135is formed to have a narrow width than the pad120, so that the edge area of the pad120is protected by the solder resist130.

Subsequently, the plating seed layer140covering the upper surface and the side surface of the forming solder resist is formed as shown inFIG. 6.

The plating seed layer140may be formed by an electroless plating scheme.

The non-electrolyte plating method performs a degreasing process, soft-corrosion process, pre-catalytic process, a catalytic process, a activation process, an electroless plating process and an oxidation preventing process in the orders.

In addition, the plating seed layer140may be formed by using a plasma rather than a metal particles.

In this case, a des-smear process to remove a smear of the surface of the solder resist is additionally performed prior to plating the plating seed layer140.

The des-smear process provides the surface roughness to the surface of solder resist130to provide a high plating strength of the plating seeding layer140.

In addition, the plating seed layer140is formed at the upper surface of the pad120in addition to the upper surface and the side surface of the solder resist130.

Next, the mask180having the window for opening a portion of the solder resist opening section185is formed as shown inFIG. 7.

More preferably, the mask180has a window185opening the area formed with a bump connection150, bump160and a solder70.

The mask180preferably uses a heat-resistant dry film.

In this case, the window185formed on the mask has a narrow width than the opening section135included in the solder resist130.

On the other hand, the window185of the mask180is formed in the opening section135formed in the solder resist to open only a portion of the opening135.

Next, the bump connection150is formed on the pad120as shown inFIG. 8.

That is, the alloy containing the conductive material, preferably copper is made by an electrolytic plating the plating seed layer140as the seed layer to form the bump connection150in which a portion of the window185of the mask180.

In this case, the window185of the mask180has a narrow width than the opening section135, so that the width of the bump connection150is formed to have the narrow width than the solder resist130.

Next, as shown inFIG. 9, the bump160is formed on the formed bump connection150.

That is, the electrolyte plating is performed on the ally containing the conductive material preferably copper.

In this case the bump160is formed to have the narrow width than the width of the opening section135included in the solder resist130.

That is, since the bump160is formed by filling the window185having a narrow width than the width of the opening section135, it is formed as a narrow width than the width of the opening section135.

In addition, the bump160is determined in shape thereof depending on the pattern of the window185formed in the mask180.

In this case, the pattern of the window185has a square pillar shape.

Next, the solder170is formed on the bump160as known inFIG. 10.

The solder170may be formed to fill the entire window185of the mask180.

In addition, the solder170reflows and melted to have the round shape by the surface tension to contact with the components.

The solder170includes more than binary metal and the binary metal is alloy containing Sn, specifically, an alloy containing Sn—Cu.

Next, the mask180formed on the plating seed layer140is removed, that is, the mask180is peeled to expose the bump160and solder170as shown inFIG. 11.

Subsequently, as shown inFIG. 12, the formed plating metal seed layer140is etched and removed.

More preferably, the plating seed layer formed in the surface of the solder resist130is selectively etched, so that the upper surface of the solder resist130is exposed.

FIG. 13is a plan view of the print circuit board according to the prior art andFIG. 14is a plan view of the printed circuit board100according to the present invention.

Referring toFIG. 13, in the printed circuit board1, the opening section is formed at the solder resist5and the bump8covering the entire opening section is formed.

On the other hand, in the printed circuit board1, the width b in the bump8is formed to be greater than the width of the opening section in the solder resist5.

As a result the printed circuit board1has an interval of c and the bump8is formed in succession.

However, referring toFIG. 14, in the printed circuit board100, the opening135is formed in the solder resist and the bump160covering a portion of the opening section135toward the side of the opening135.

In the other hand, in the printed circuit board1, the width b in the bump160is formed to be narrow than the width A of the opening in the solder resist130.

Therefore, the printed circuit board100has an interval of C and the bump160is continuously formed.

At this time, in the printed circuit board100according to the present invention, A is great than B, in the printed circuit board1according to the prior art, a is narrow than b, so that the printed circuit board100has the internal C greater than c having the printed circuit board1and the bump160is continuously formed.

FIG. 15. is a plane view of the printed circuit board according to another embodiment of the present invention.

On the other hand, referring toFIG. 15, the print circuit board100according to the present invention has a protective layer formed with opening section and the bump160covering only a portion of the opening section135is formed toward an inner side of the opening section.

FIGS. 16 and 17shows a reliability evaluation of a printed circuit according to the embodiment of the present invention.

Referring toFIG. 16, a structure of Case 3 shows the overall height reliability based on a simulation evaluation result according to the bump structure. When chip and the bond are bonded by the bump structure160, a street applied to a die will be reduced.

In addition, referring toFIG. 17, the case 3 structure has the best life cycle based on bump crack analysis result.