Semiconductor package with a cavity in a die pad for reducing voids in the solder

A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.

BACKGROUND

Technical Field

The present disclosure is directed to semiconductor devices and more particularly, semiconductor packages.

Description of the Related Art

Quad-flat no-leads (“QFN”) semiconductor packages are known. Such packages physically and electrically connect integrated circuits to substrates, such as printed circuit boards. During operation, the integrated circuit produces heat, which is dissipated to avoid damage to the package. In known QFN packages, the heat produced by the integrated circuit is dissipated from the integrated circuit through the die pad to which the integrated circuit is coupled, and into the substrate or a thermal pad on the substrate. In attaching the integrated circuit to the die pad of the package, solder material is commonly used because of its high thermal conductivity. However, solder material has volatile components, such as flux, that create bubbles of gas that are trapped during solidification of the solder when coupling the integrated circuit to the die pad. Such bubbles of gas are referred to as solder voids. The voids can cause a displacement of electrical and thermal paths and a local concentration of power and heat, which reduce the efficiency of heat transfer and thus reduce the reliability and applicability of QFN packages. Larger packages with higher heat dissipation requirements are utilized in certain industries, such as in the automotive industry. However, solder voids are even more likely to form in these larger packages due to the increase in the amount of solder used to couple the integrated circuit to the die pad.

BRIEF SUMMARY

The present disclosure is directed to a semiconductor package or device including a die pad and leads. The package includes a semiconductor die coupled to the die pad, typically with a die attach material, such as solder, to aid in the transfer of heat. Wires are coupled between the semiconductor die and the leads to establish an electrical connection between the die and the leads. The semiconductor die, the die pad, and the leads are encapsulated in a plastic material to produce a package, with the plastic material protecting the electrical components. The die pad and the leads are exposed on a surface of the package to enable an electrical connection to be formed with the die and an exterior device.

In at least one embodiment, a cavity or aperture is formed through the die pad to expose a portion of the die attach material. Additional material, such as solder, is back filled into the aperture in two distinct steps. In a first step, the original die attach material is reheated, which allows any voids that formed during coupling of the semiconductor die to the die pad to be released. In the second step, a solder layer is formed on the die attach material to fill the aperture. In one example, the solder in the aperture is coplanar with the surface of the package, such that the package has exposed solder on the surface of the package in the place of the portion of the die pad that was removed when forming the aperture.

In one example, the material coupling the die to the die pad is the same as the material of the solder layer. In other examples, the material used for the die attach is different from the material used for the solder layer in the aperture. Using different solder for the solder layer and the die attach material may be advantageous to help establish a strong physical and electrical connection with an external device that the package is coupled to. Put another way, the external device that receives the package may have pre-formed solder on a surface facing the package. The solder used for the solder layer (e.g. the solder exposed on the surface of the package) can be the same as the pre-formed solder on the external device, thus ensuring that a strong physical and electrical connection is established between the various layers of solder.

The present disclosure further includes methods of forming such semiconductor packages, including coupling a semiconductor die to the die pad with the die attach material, coupling wires between the semiconductor die and the leads and encapsulating the resulting combination in a plastic material to form a package. Then, a cavity or aperture is formed through the die pad and the first reheating step discussed above is performed to release the voids in the solder. Then, the solder layer is formed in the aperture to fill the voids and the aperture. The solder layer can be the same material as the die attach material or a different material. In one example, the method includes forming vent holes in the die pad during the forming of the die pad, such that voids in the die attach material can escape through the vent holes when the semiconductor die is coupled to the die pad with the die attach material, which eliminates the first reheating step described above.

Known solutions to reduce solder voids include vacuum treatment while solder is a molten state and optimization of the solder reflow temperature profile to increase the likelihood that trapped gas can escape at vent areas. However, such solutions are inadequate for several reasons. For example, these solutions have a low success rate in that voids are often still present in the solder even after using one of these solutions. Further, such solutions are costly because they involve special equipment and experimental trials to optimize, which increases the cost of the resulting package without experience significant benefits.

DETAILED DESCRIPTION

The present disclosure is generally directed to semiconductor packages having a cavity or aperture in a die pad of the package with solder or other material in the cavity coplanar with a surface of the die pad. The cavity allows for solder voids in the solder to escape during solder reflows, thus reducing the presence of solder voids and increasing thermal performance of the package.

FIG. 1illustrates a known semiconductor package20. The package20includes a die pad22and a plurality of leads24. A semiconductor die26is coupled to the die pad22with a die attach material28, which may be solder. Because the die pad22is typically a solid block of metal, the material28is only exposed to the ambient environment at sides30of the material28.FIG. 1illustrates the package20significantly enlarged for clarity. In actuality, a typical package20is on the order of a few millimeters in width, length, and thickness. As such, the area of die attach material28exposed at sides30is often significantly less than 1 mm. Thus, the vent area for the material28is insufficient and gas or air voids32form in the die attach material28as it solidifies. These voids32are randomly dispersed and differ in size and orientation throughout the material.

When electricity is provided to the package20, the voids32cause a displacement of electrical and thermal paths and a local concentration of power and heat around the voids32. This concentration of power and heat causes issues for the package20over the life cycle of the package20, which typically includes hundreds, if not thousands, or more, of power cycles. Such issues can include delamination of the die attach material28from one of the die26and the die pad22, or delamination of the die26from the die pad22, which can both lead to package failure if contaminants, such as water or dirt are allowed to enter the separated package20. Other issues include shorting, overheating, or melting of the electrical components of the package20. These problems are only exacerbated in larger packages, as the die attach material28in the middle of the package is even further from the vents at the sides30, thus increasing the likelihood of formation of voids32.

FIGS. 2 and 3illustrate an embodiment of a semiconductor package100according to the present disclosure, which includes a first surface102and a second surface104opposite the first surface102. Specifically,FIG. 2illustrates a plan view of the second surface104of the package100andFIG. 3illustrates a cross-sectional view of the package100along the line A-A inFIG. 2. The package100includes a lead frame comprising a die pad106spaced from a plurality of leads108. In one embodiment, the die pad106is a die pad area. The die pad106includes a first surface110and a second surface112opposite the first surface110. Similarly, the plurality of leads108include a first surface114and a second surface116opposite the first surface114. In one embodiment, the surfaces110,112of the die pad106are coplanar with the surfaces114,116of the leads108. As such, a first surface of the lead frame includes the first surface110of the die pad106as well as the first surface114of the leads108and a second surface of the lead frame includes the second surface112of the die pad106and the second surface116of the leads108.

In one embodiment, the second surface of the lead frame is coplanar with the second surface104of the package100. The die pad106further includes a cavity or aperture118extending through the die pad106from the first surface110to the second surface112of the die pad106. The cavity118defines sidewalls120of the die pad106, which extend around a periphery of the die pad106, as shown inFIG. 2. In other words, the cavity118is preferably centrally disposed with respect to the die pad106to define a plurality of sidewalls120, which may also be referred to as a single sidewall including a plurality of walls, extending from the first surface110to the second surface112of the die pad106.

A die attach material122is in the cavity118of the die pad. The die attach material122couples a semiconductor die124to the die pad106, and more specifically, to the sidewall120of the die pad106. As will be described further, the die attach material122includes a first layer of material122A, which may be a die attach material, such as solder, for example, which couples the die124to the die pad106. Preferably, the first layer of material122A extends between the sidewalls120of the die pad106. Then, a second layer of material1226is formed on the first layer122A to fill the cavity118. In one embodiment, the layers of material122A,122B are the same and as such, in the composite product a boundary line between the layers may not be distinguishable. Here, a boundary between the layers122A,122B is denoted by a dashed line for clarity. In other embodiments where the layers122A,122B are different, a more clear boundary would appear in a cross-sectional view. The die attach material122has a first surface126and a second surface128.

In one embodiment, the first surface126of the die attach material122is in the cavity118of the die pad106on the die124(e.g. between the first and second surfaces110,112of the die pad106) and the second surface128of the die attach material122is coplanar with the second surface104of the package100. As such, inFIG. 2, the die attach material122is exposed on the second surface104of the package104to the ambient environment. In other embodiments, the die attach material122is not coplanar with the second surface104of the package100, but rather, the die attach material122extends beyond the second surface104of the package100or the die attach material122has a thickness such that the die attach material122does not completely fill the cavity118. Further, it is to be appreciated that while the layers of material122A,122B are illustrated inFIG. 3as having the same thickness, that a thickness of each layer122A,122B can be selected. For example, the thickness of layer122A may be more or less than the thickness of layer122B.

As shown inFIG. 3, the package100further includes a plurality of wires130coupled between the die124and the plurality of leads108. In one embodiment, the plurality of wires130are any type of metal wire and are bonded between the leads108and the die124with solder. In other embodiments, one or more of the wires130are formed from a conductive paste (e.g. an adhesive with entrained metal particles) and sintered or solidified in place. In such embodiments, a sacrificial layer may be used under the uncured conductive paste to establish a connection path between the leads108and the die124, wherein the sacrificial layer evaporates as the wires130are cured. An encapsulant132is formed over the leads108, the wires130, the die124, and the die pad106. The encapsulant132may be a polymer, a plastic, a thermoplastic, a resin, any combination thereof, or the like.

In one embodiment, the package100is square, such that a length134of each side136of the package100is equal or substantially equal. Further, the die pad106and the cavity118are preferably square as well, as shown inFIG. 2. The die pad106includes a perimeter or outermost edge138, which may also be referred to as a first edge, and an inner edge140, which may also be referred to as a second edge. In one embodiment, a length or dimension142of each side of the die pad106along the perimeter edge138is greater than a length or dimension144of each side of the inner edge140. As such, an area of the die pad106defined by the perimeter edge138is greater than an area of the cavity118as defined by the inner edge140. However, other embodiments of the present disclosure include other package and die pad shapes, including square or circular, for example, as well as die pads with edges of different size relative to the cavity or aperture.

FIGS. 4 and 5illustrate an alternative embodiment of a semiconductor package200. Certain aspects of the package200are identical to the package100and as such, redundant disclosure has been omitted in the interest of brevity and to avoid obscuring features of the embodiments.

The package200includes a first surface201and a second surface203opposite the first surface201and a die pad202defined by sidewalls204of the die pad202.FIG. 4illustrates the second surface203of the package200andFIG. 5is a cross-sectional view of the package200through line B-B inFIG. 4. The die pad202includes a first surface206and a second surface208opposite the first surface206and an aperture210extending through the die pad202from the first surface206to the second surface208of the die pad202. A die attach material212is formed in the aperture210. The die attach material212can include a plurality of layers212A,212B, and212C. Specifically, the first layer212A is in the aperture210and on the die214. The first layer212A is formed with a first solder reflow to couple the die214to the die pad202before formation of the aperture210. Then, the aperture210is formed, and a second solder reflow process is performed to release solder voids in the first layer212A. The aperture210can be formed with a single mask and a wet or dry etch, or with multiple etching steps. In other embodiments, the aperture210is formed by laser or mechanical cutting, for example.

Because the aperture210extends across most, or all of, the die pad202, there is significantly more vent area for the solder voids compared to known packages. In the second solder reflow, additional solder can be added as the second solder layer212B. Dashed line228represents the interface between the first and second layers212A,212B. Because the release of the voids in the first layer212A may create an uneven surface facing the second layer212B, dashed line228includes several curved portions to represent cavities at a surface of the first layer212A that may remain after the solder voids are vented. Finally, the third layer212C is formed on the second layer212B and preferably coplanar with the second surface203of the package. As shown inFIG. 5, the third layer212C has a larger area than the first and second layers212A,212B. The layers212A,212B,212C are added sequentially, as above, which allows for gas in the solder to vent before the next layer is added. As such, each layer in the package200will have significantly less solder voids (e.g., 80% less, 90% less or more in various embodiments) compared to known packages. Moreover, embodiments of the present disclosure include more than two layers of die attach material212in the aperture210, such as three, four, five, or more layers, which can be selected according to the application of the package200.

InFIG. 5, an area of an opening the aperture210and thus the third layer of material212C is at least equal to an area of the die pad202. In other words, the aperture210and the third layer of material212C have a first area defined by a first dimension216and a second dimension218and the die pad202includes a second area defined by an outer edge of the sidewalls204of the die pad202. The first area is preferably equal or substantially equal to the second area. In one embodiment, the first area is greater than the second area. In the illustrated embodiment, a portion of the third layer of material212C is under the sidewalls204of the die pad202and is coplanar with an outer surface of the sidewalls204of the die pad202.

The second surface203of the package200includes the second layer212B of material212exposed to the ambient environment. In one embodiment, the die pad202is not visible on the second surface203of the package200regardless of viewing orientation, as inFIG. 4. The package200further includes the die214having sidewalls220extending between a first surface222and a second surface224of the die214. The die pad202that receives the die214has a greater area than an area of the die214between the sidewalls220. As such, there is a gap or space224between sidewalls220of the die and sidewalls204of the die pad202. In one embodiment, molding compound226fills the gap or space224in the package200. However, when coupling the die214to the die pad202, the gap224provides clearance to prevent damage to the die214by contacting the die214with the sidewalls204of the die pad202. In other words, the gap224prevents chipping or cracking of the die214when attaching or coupling the die214to the die pad202with the die attach material212.

FIG. 6illustrates an alternative exemplary embodiment of a package300. The package300may be identical in several respects to the package100described with reference toFIGS. 1 and 2and as such, redundant description has been omitted. The package300includes a lead frame302including a die pad304and a plurality of leads306. A hole308extends through the die pad304. The package300includes a semiconductor device310, such as a semiconductor die, received in the hole308. Put another way, the semiconductor device310includes a first surface312opposite a second surface314and the die pad304includes a first surface316opposite a second surface318. The second surface314of the semiconductor device310is positioned in the hole308between the first and second surface316,318of the die pad304, which may also be referred to as a first and second surface of the lead frame302. A first material320is in the hole308on the second surface314of the semiconductor device310. The first material320has a first surface322and a second surface324, wherein the first surface322of the first material320is between the first and second surfaces316,318of the die pad304on the semiconductor device310.

A second material326is on the first material320. In the illustrated embodiment, the second material326is below the first material320. More specifically, the second material326includes a first surface328and a second surface330, wherein the first surface328of the second material326is on the second surface324of the first material320and the second surface330of the second material326is coplanar with a surface of the package300, as described herein. In one embodiment, the first and second materials320,326are the same solder, in which case, the materials320,326may generally be referred to as a single material, or a single material with two layers320,326, wherein the second surface330of the combined material is coplanar with a surface of the package300. In other embodiments, the materials320,326are different. For example, the first material320may be a first type of solder and the second material326may be a second, different type of solder with different thermal, electrical, and bonding characteristics than the first type of solder.

FIGS. 7A-Fillustrate an embodiment of a method for forming a semiconductor package400of the type described herein. WhileFIGS. 7A-Fillustrate the formation of one package, it is to be appreciated that the method can be performed to form hundreds of packages at the same time, wherein the last step is singulation of the composite structure containing numerous packages into singular packages through mechanical or laser cutting, or different types of etching, for example.FIG. 7Aillustrates a lead frame402, which includes a die pad404spaced from a plurality of leads406. The lead frame402may be formed from a solid sheet of material by wet or dry etching, mechanical cutting, or laser cutting for example. The die pad404includes a first surface408opposite a second surface410and a cavity412extending into the die pad404from the first surface408. As with the lead frame402, the cavity412may be formed by etching, among other processes.

InFIG. 7B, a semiconductor die414is coupled to the die pad404and more specifically, to the first surface408of the die pad404in the cavity412of the die pad404. The die414is coupled to the die pad404with a die attach material416, which may be solder, for example. The die attach material416is between the first surface408of the die pad404and the die414. As described above, an area of an opening of the cavity412is greater than an area of the die414and as such, there is a gap or space between edges of the die414and the die pad404to prevent damage to the die414during coupling. Once the die414is attached, a plurality of wires418are coupled between the die414and the leads406to establish an electrical connection between the same. As shown inFIG. 7B, the die414is received in the cavity412, or in other words, a first surface405of the die414is positioned above a first surface408of the die pad404and the lead frame402generally while a second surface407of the die414is between the first and second surfaces408,410of the die pad404and the lead frame202.

InFIG. 7C, an encapsulant420is formed over the die414, the wires418, the die pad404, and the leads406to form the package400having a first surface401opposite a second surface403. Formation of the encapsulant420can be accomplished by any number of conventional methods.

The method continues inFIG. 7Dby removing a portion of the die pad404. More specifically, an aperture422is formed through the die pad404from the second surface410to the first surface408of the die pad408to expose at least a portion of, or an entire surface of, the die attach material416. In one embodiment, the aperture422is formed to correspond to a location of the die414, while in other embodiments, the aperture422is offset from the die414. Further, in one embodiment, the aperture422has an area greater than an area of the die414, while in other embodiments, the area of the aperture422is equal to or less than the area of the die414. InFIG. 7Dan area of the aperture422is less than an area of the die pad404, while in other embodiments, the area of the aperture422is greater than or equal to the area of the die pad404on a surface of the package.

Further, it is to be appreciated that because the aperture422is preferably formed by etching, that the aperture422can be formed to selected depths relative to the die pad404. For example, in one embodiment, the aperture422is formed to remove only a portion of the die pad404, while in other embodiments, etching can be selectively performed to remove a portion of the die attach material416as well. Removing a portion of the die attach material416may be advantageous to remove any voids in the die attach material416proximate the die pad404(e.g. at a surface of the die attach material416facing the die pad404).

Then, inFIG. 7E, the package400is flipped and a solder reflow is performed to release any voids in the die attach material416. In one embodiment, the solder reflow includes reheating the die attach material416until it is at least partially molten liquid, at which point, the voids can escape through the aperture422, which is a considerably larger vent area than at sides of the package400, as described with reference toFIG. 1. Preferably, the solder reflow includes heating the die attach material416until all or substantially all of the die attach material416is in a molten, liquid state. There is a much higher likelihood of the voids escaping the package400as compared to known packages because a vent area of the die attach material416and the aperture422(e.g. an area corresponding to the exposed portion of the die attach material416via the aperture422) is two, three, four, five, six, seven, eight, nine, ten, or more times greater than a vent area at sides of the package inFIG. 1.

Thus, as the die attach material416is reheated, the gas in the voids tends to move to a surface424of the die attach material416that is at a top of the package400according to known principles of density. In other words, because the ambient environment surrounding the exposed die attach material416is less dense than the heated gas in the voids via the first solder reflow, the gas will naturally navigate towards the surface424of the die attach material416to be released. In an alternative embodiment, the first solder reflow includes adding a thin layer of solder (relative to the die attach material416) on the die attach material416to fill any surface cavities that remain after the gas voids are released through the surface424.

Then, inFIG. 7F, a material426is formed in the aperture422on the die attach material416. As described herein, the material426, which may also be a layer of material, has a first surface428opposite a second surface430, wherein the first surface428is on the die attach material416in the aperture422between the first and second surfaces408,410of the die pad404and the second surface430is coplanar or flush with the second surface403of the package400to facilitate coupling the package400to an external device, such as a substrate.

As such, the method includes multiple solder reflows, in conjunction with increased vent area at the aperture422in the die pad404to release the solder voids and back fill solder such that the package400can be coupled to an external device. Specifically, a first solder reflow is performed inFIG. 7Bto couple the die414to the die pad404with the die attach material416, which may be solder. Then, after forming the aperture422, a second solder reflow is performed to release the voids in the die attach material416through the expanded vent area enabled by the aperture422. The second reflow may or may not include adding additional solder. Finally, a third solder reflow fills the aperture422with material426such that the material426is coplanar with the second surface403of the package400. Because the aperture422is open to the ambient environment, any trapped gas in the material426will be vented without additional solder reflows. In other words, the aperture422provides a sufficient vent area to reduce or prevent formation of solder voids in the material426added during the third solder reflow. In one embodiment, forming the material426includes the material426being the same solder material as the die attach material416. As such, the combination of the die attach material416and the material426is a single, contiguous layer of solder with different portions corresponding to the different solder reflows. In other embodiments, these materials are different.

FIG. 8illustrates an alternative embodiment of a method for forming a package, such as package400described with reference toFIGS. 7A-F. Specifically, the method includes forming a plurality of vent holes508in a die pad502, wherein each vent hole508extends through the die pad502from a second surface506to a first surface504of the die pad402. Preferably, the vent holes508are formed before coupling a die512to the die pad502. In other words,FIG. 8illustrates an alternative method to that described inFIG. 7A, as the vent holes508are formed in the die pad502, which may be part of a lead frame, before the die512is coupled to the die pad502. The vent holes508increase a vent area to allow gas trapped in the die attach material to escape. While the vent holes508are exaggerated in size inFIG. 8for ease of recognition, it is to be appreciated that the vent holes508are, in actuality, small enough that a die attach material510, which may be solder, for example, will not escape through the vent holes508.

Further, while only four vent holes508are shown inFIG. 8, it is to be appreciated that the plurality of vent holes508can include tens, if not hundreds of vent holes508across the die pad502. The vent holes508may be formed by wet or dry etching or by laser cutting, for example. After formation of the vent holes508, the method described with reference toFIGS. 7A-Fproceeds according to the same procedure, except that the solder reflow described with reference toFIG. 7Eto release the gas voids may not be necessary. In other words, because the gas in the die attach material510in this embodiment can escape through the vent holes508during solidification of the die attach material510, the solder reflow to release the same inFIG. 7Emay not be needed. Then, the vent holes508can be removed by etching or cutting to form the aperture422, as described herein. Because the vent holes508can be pre-formed in the die pad502before coupling the die414to the die pad404, the embodiment ofFIG. 8results in a more efficient method than that described with reference toFIGS. 7A-Fbecause the method ofFIG. 8involves one less solder reflow step (e.g. two total instead of three total).

In one embodiment, the vent holes508are formed before coupling the die512to the die pad502, as above. In other embodiments, the vent holes508are formed instead of the aperture422described with reference toFIG. 7D. In other words, an alternative embodiment of a method proceeds as described untilFIG. 7D, at which point, the vent holes508are formed in the die pad502instead of the aperture422. In this embodiment, the solder reflow described inFIG. 7Eis performed, wherein the trapped gas is allowed to escape through the vent holes508instead of through the aperture422. Then, inFIG. 7F, the material426is added to fill the vent holes508during a solder reflow step, such that the resulting package includes alternating sections of die pad502and material426in the vent holes508.

FIG. 9is yet a further alternative embodiment of a method for forming a package600, which may be similar to package400, except as otherwise described. The method proceeds as described with reference toFIGS. 7A-F, except that in this embodiment, the package600includes a first material608on a semiconductor die606in an aperture604in a die pad602and a second material610on the first material608. In this embodiment, the first material608and the second material610are different. For example, the first material608may be a solder including tin and lead and the second material608may be a lead-free solder, such as a solder including tin, silver, and copper. In other embodiments, the first material608is the lead-free solder and the second material610is the tin and lead solder. In yet further embodiments, the first material608is a lead-free solder with a first combination of tin, silver, and copper and the second material610is a lead-free solder with a second, different combination of tin, silver, and copper. As such, embodiments of the present disclosure are not limited by the type of solder used for the first material608and the second material610, but rather, the materials can be selected according to application of the package600.

FIG. 10illustrates the package600coupled to a substrate612, which may be a printed circuit board (PCB), for example. The package600includes an encapsulant614formed over and surrounding the die606, the die pad602, a plurality of leads616, and a plurality of wires618coupled between the die606and the leads616. The encapsulant614includes a first surface620opposite as second surface622. In one embodiment, the first surface620and the second surface622of the encapsulant are a first and second surface, respectively, of the package600.

The substrate612includes a first surface624opposite a second surface626with a material628formed on the first surface624of the substrate612. In one embodiment, the material628is pre-formed on the first surface624and is comprised of solder. For example, the material628may be a tin and lead solder, or a lead-free solder, such as a solder containing tin, silver, and copper, alone or in any combination. As shown inFIG. 10, a location of each portion of the material628on the substrate612corresponds to a location of the leads616and the die pad602of the package600. As such, the substrate612is configured to receive the package600. Preferably, the material628is of the same type as the second material610of the package600. As such, when the package600is coupled to the substrate612, the material628and the second material610of the package, which is exposed, are soldered together. The material628is also soldered to the leads616and the die pad602. Because the materials610,628are preferably of the same composition, the resulting combination forms a strong physical connection, which improves reliability of the coupling between the package600and the substrate612. The first material608of the package600is preferably a different material, such as a tin and lead solder, that is compatible with the second material610and the material628on the substrate612as well as with the semiconductor material comprising the die606. Moreover, the material628can be selected to be a material compatible with the leads616and the die pad602, which are preferably formed of a metal, such as copper or a copper alloy, among other examples.

Once the package600is coupled to the substrate, the package600is spaced from the first surface624of the substrate612in areas where the material628is not present. In other words, there is an air gap630between the second surface622of the encapsulant614(and the package600) and the first surface624of the substrate612. In one embodiment, the second surface622of the encapsulant614faces the substrate612and the first surface624of the substrate612faces the package600and the encapsulant614. As such, the air gap630is between a surface of the encapsulant612facing the substrate612and a surface of the substrate612facing the encapsulant612. In one embodiment, the air gap630acts as an additional heat dissipation region, as heat transferred from the package600to the material628is dissipated in the air gap630. In other words, the air gap630provides for air flow around the material628and the package600, which naturally cools the package600and the substrate612via convection.

As such, embodiments of the present disclosure provide for semiconductor packages with a semiconductor die coupled to a die pad with a first material. The die pad includes a cavity or aperture extending through the die pad. Then, a solder reflow process is performed to remove solder voids in the first material that form during solidification of the first material when coupling the die to the die pad. A second material is then formed or deposited in the cavity on the first material. Preferably, the second material is coplanar with a surface of the package. The first and second materials may be the same or different types of solder, for example. As such, the packages described herein include solder on a surface of a package that is exposed to an ambient environment, wherein the solder does not include, or has a substantially reduced amount of, voids or trapped gas relative to known packages. The reduction in voids of trapped gas reduces the concentration of heat and power and enables more efficient heat transfer from the package to a substrate to which the package is coupled.

The relative terms “approximately” and “substantially,” when used to describe a value, amount, quantity, or dimension, generally refer to a value, amount, quantity, or dimension that is within plus or minus 5% of the stated value, amount, quantity, or dimension, unless the context clearly dictates otherwise. It is to be further understood that any specific dimensions of components or features provided herein are for illustrative purposes only with reference to the exemplary embodiments described herein, and as such, it is expressly contemplated in the present disclosure to include dimensions that are more or less than the dimensions stated, unless the context clearly dictates otherwise.