Selective deposition and nitridization of bottom electrode metal for MRAM applications

A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

BACKGROUND

Technical Field

The present invention relates generally to semiconductor devices, and more specifically, to the selective deposition and nitridization of a bottom electrode metal for at least magnetic random access memory (MRAM) applications.

Description of the Related Art

Integrated circuits are typically fabricated with multiple levels of patterned metallization lines, electrically separated from one another by interlayer dielectrics containing vias at selected locations to provide electrical connections between levels of the patterned metallization lines. As these integrated circuits are scaled to smaller dimensions in a continual effort to provide increased density and performance (e.g., by increasing device speed and providing greater circuit functionality within a given area chip), the interconnect linewidth dimension becomes increasingly narrow, which in turn renders them more susceptible to effects such as electromigration.

SUMMARY

In accordance with an embodiment, a method is provided for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches, selectively depositing an electrode over the top surface of the exposed metal, and nitridizing the electrode to form a barrier between chip components and the metal.

In accordance with an embodiment, a method is provided for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches, selectively recessing the exposed metal of one or more of the trenches, selectively depositing an electrode within the recessed portion of the exposed metal, and nitridizing the electrode to form a barrier between chip components and the metal.

In accordance with another embodiment, a semiconductor device is provided. The semiconductor device includes an insulating layer formed over a semiconductor substrate, trenches configured to receive a metal, the trenches formed by etching the insulating layer, one or more sacrificial layers selectively etched to expose a top surface of the metal of one or more of the trenches, and an electrode selectively deposited over the top surface of the exposed metal, the electrode nitridized to form a barrier between chip components and the metal.

DETAILED DESCRIPTION

In one or more embodiments, a method is provided for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches, selectively depositing an electrode over the top surface of the exposed metal, and nitridizing the electrode to form a barrier between chip components and the metal.

In one or more embodiments, a method is provided for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches, selectively recessing the exposed metal of one or more of the trenches, selectively depositing an electrode within the recessed portion of the exposed metal, and nitridizing the electrode to form a barrier between chip components and the metal.

In one or more embodiments, a semiconductor device is provided. The semiconductor device includes an insulating layer formed over a semiconductor substrate, trenches configured to receive a metal, the trenches formed by etching the insulating layer, one or more sacrificial layers selectively etched to expose a top surface of the metal of one or more of the trenches, and an electrode selectively deposited over the top surface of the exposed metal, the electrode nitridized to form a barrier between chip components and the metal.

In one or more embodiments, the blocking boundary can be created directly underneath the via/trench, whereas in other embodiments the blocking boundary can be created in an area or region surrounding the via/trench.

In one or more embodiments, a blocking boundary is only placed where needed (i.e., not under all the vias). As a result, the via resistance can be very low for critical circuits where a blocking boundary is not necessary. The blocking boundary does not impact trench resistance or capacitance since the blocking boundary is limited to select vias.

In one or more embodiments, a structure and method are introduced to integrate a self-aligned metal bottom electrode and nitridize it to form a barrier in specific regions of the chip, while leaving other logic regions largely unchanged. Such a structure and method is achieved by blocking out non-MTJ (magnetic tunnel junction) regions of the chip and leaving a sacrificial dielectric cap to protect areas designed to remain unmodified. Additionally, selective deposition of a metal on top of the bottom contact (no additional critical mask or Cu recess required) and nitridation of a selective metal to form effective barrier is achieved.

In one or more embodiments, selective deposition of a metal that is not a barrier by itself is followed by a nitridization process to impart barrier properties. The selective deposition would be electroless (wet) for certain metal (e.g., tantalum) or would be a selective chemical vapor deposition (CVD) (dry) for certain metals (e.g., cobalt).

As used herein, “semiconductor device” refers to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor determines the conductivity type of the semiconductor.

A “gate structure” means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields.

As used herein, the term “drain” means a doped region in the semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain.

As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel.

The term “direct contact” or “directly on” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

The terms “overlying”, “atop”, “positioned on” or “positioned atop” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure can be present between the first element and the second element.

The term “electrically connected” means either directly electrically connected, or indirectly electrically connected, such that intervening elements are present; in an indirect electrical connection, the intervening elements can include inductors and/or transformers.

The term “crystalline material” means any material that is single-crystalline, multi-crystalline, or polycrystalline.

The term “non-crystalline material” means any material that is not crystalline; including any material that is amorphous, nano-crystalline, or micro-crystalline.

The term “intrinsic material” means a semiconductor material which is substantially free of doping atoms, or in which the concentration of dopant atoms is less than 1015atoms/cm3.

As used herein, the terms “insulating” and “dielectric” denote a material having a room temperature conductivity of less than about 10−10(Ω-m)−1.

As used herein, the term “silicide” is an alloy of a metal and silicon.

As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium.

As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.

The terms, chip, integrated circuit, monolithic device, semiconductor device, and microelectronic device, are often used interchangeably in this field. The present invention is applicable to all the above as they are generally understood in the field.

The terms metal line, interconnect line, trace, wire, conductor, signal path and signaling medium are all related. The related terms listed above, are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnect or simply metal. Metal lines, generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling or interconnecting electrical circuitry. Conductors other than metal are available in microelectronic devices. Materials such as doped polysilicon, doped single-crystal silicon (often referred to simply as diffusion, regardless of whether such doping is achieved by thermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo), and refractory metal silicides are examples of other conductors.

The terms contact and via, both refer to structures for electrical connection of conductors from different interconnect levels. These terms are sometimes used in the art to describe both an opening in an insulator in which the structure will be completed, and the completed structure itself. For purposes of this invention, contact and via refer to the completed structure.

As used herein, an “anisotropic etch process” denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is greater than in the direction parallel to the surface to be etched. The anisotropic etch can include reactive-ion etching (RIE).

Reactive ion etching (RIE) is a form of plasma etching in which during etching the surface to be etched is placed on the RF powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used include ion beam etching, plasma etching or laser ablation.

The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, stripping, implanting, doping, stressing, layering, and/or removal of the material or photoresist as required in forming a described structure.

As used herein, “depositing” can include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

The terms “gas” and “gases” are used interchangeably, unless otherwise noted, and refer to one or more precursors, reactants, catalysts, carrier, purge, cleaning, combinations thereof, as well as any other fluid introduced into the chamber body.

As used herein, a surface is “substantially planar” if the surface is intended to be planar and the non-planarity of the surface is limited by imperfections inherent in the processing steps that are employed to form the surface.

As used herein, a “mounting structure” is any structure to which a semiconductor chip can be mounted by making electrical connections thereto. A mounting structure can be a packaging substrate, an interposer structure, or another semiconductor chip.

The semiconductor devices described herein can be any type of device. Exemplary types of semiconductor devices include planar field effect transistors (FETs), fin-type field effect transistors (FinFETs), nanowire/nanosheet devices, vertical field effect transistors (VFETs), or other devices.

FIG. 1is a cross-sectional view of a semiconductor structure including copper (Cu) received within recessed regions of an insulator deposited over a semiconductor substrate, in accordance with an embodiment of the present invention.

A semiconductor structure5includes a semiconductor substrate10. An insulator layer12is deposited over the substrate10. The insulating layer12is etched to form trenches thereon. A tantalum nitride (TaN) liner14or in the alternative a tantalum (Ta) liner14is deposited over or around the trenches. In one example embodiment, the conductive fill material14can be deposited, for example, by electroplating, electroless plating, chemical vapor deposition (CVD), atomic layer deposition (ALD) and/or physical vapor deposition (PVD).

The trenches are then configured to receive a conducting material. The conducting material can be a metal, such as copper (Cu)16. A top surface15of the copper regions16can be exposed. In the exemplary embodiment, two Cu regions16are illustrated for the sake of clarity. One skilled in the art may contemplate a plurality of Cu regions16defined within the insulator layer12. Additionally, a top surface11of the insulating layer12is exposed between the Cu regions16.

In one or more embodiments, the substrate10can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate10can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate10can be essentially (i.e., except for contaminants) a single element (e.g., silicon), primarily (i.e., with doping) of a single element, for example, silicon (Si) or germanium (Ge), or the substrate10can include a compound, for example, Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate10can also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI). The substrate10can also have other layers forming the substrate10including high-k oxides and/or nitrides. In one or more embodiments, the substrate10can be a silicon wafer. In an embodiment, the substrate10is a single crystal silicon wafer.

FIG. 2is a cross-sectional view of the semiconductor structure ofFIG. 1where sacrificial layers are deposited over the Cu regions, in accordance with an embodiment of the present invention.

In various embodiments, a first sacrificial layer18, a second sacrificial layer20, and an oxide22are deposited over the Cu regions16, as well as the exposed portions of the insulator12. Additionally, a photoresist24is used in the lithography, which defines the location desired to form the blocking boundary. Photoresist24is deposited over one of the Cu regions16. The first sacrificial layer18can be, e.g., silicon nitride (SiN) or a dielectric cap. The second sacrificial layer20can be, e.g., SiN or a metal nitride.

In some embodiments, depositing the SiN layer18comprises exposing the metal nitride film to a first deposition gas and a second deposition gas, either simultaneously (e.g., CVD) or sequentially (e.g., ALD). The first deposition gas can comprise any suitable silicon-containing precursor and the second deposition gas can comprise any suitable reactive gas capable of reacting with the first deposition gas. In some embodiments, the first deposition gas comprises disilane and a second deposition gas comprises ammonia and exposing the plasma treated metal nitride film to the deposition gases forms a metal-SiN film.

As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example, in one embodiment, a selective etch can include an etch chemistry that removes a first material selectively to a second material by a ratio of 10:1 or greater, e.g., 100:1 or greater, or 1000:1 or greater.

In various embodiments, the materials and layers can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, for example plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions can be epitaxial processes, and the deposited material can be crystalline. In various embodiments, formation of a layer can be by one or more deposition processes, where, for example, a conformal layer can be formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill can be formed by a second process (e.g., CVD, electrodeposition, PVD, etc.).

FIG. 3is a cross-sectional view of the semiconductor device ofFIG. 2where a portion of the sacrificial layers are removed by, e.g., reactive-ion etching (RIE) to expose a top surface of one or more of the Cu regions, in accordance with an embodiment of the present invention.

In various embodiments, the photoresist24and the oxide layer22are selectively etched. Additionally, the first and second sacrificial layers18,20not positioned under the photoresist24are etched to expose the top surface15of the Cu region16(right-hand side), as well as the top surface11of the insulating layer12. In contrast, the first and second sacrificial layers18,20positioned under the photoresist24remain intact on the other Cu region16(left-hand side).

The etching can include a dry etching process such as, for example, reactive ion etching, plasma etching, ion etching or laser ablation. The etching can further include a wet chemical etching process in which one or more chemical etchants are used to remove portions of the blanket layers that are not protected by the patterned photoresist. The patterned photoresist can be removed utilizing an ashing process. In one example embodiment, RIE is performed.

Concerning removal of the oxide, plasma processes commonly use nitrogen gas (N2) for dilution, nitrous oxide (N2O) as an oxygen carrying gas, and silane (SiH4) as a silicon carrying gas. In the plasma phase these compounds are dissociated into their respective ionic components and the more mobile electrons are accelerated by high frequency RF at high power coupled to the reaction chamber to strike the plasma. There is a small negative voltage between the positive ions in the plasma and the wafer that rests on a grounded heater block. This potential difference will accelerate the ions towards the wafer surface where the ions form a layer of silicon dioxide (SiO2).

High and low frequency RF power is commonly used in oxide reactors to enhance the LPCVD process. High frequency RF power is used to strike the plasma by accelerating the electrons, whereas low frequency RF power is used to enhance the densification of the layer to be formed as it keeps heavier ions mobile for an extended time.

FIG. 4is a cross-sectional view of the semiconductor device ofFIG. 3where a bottom metal electrode is deposited, in accordance with an embodiment of the present invention.

In various embodiments, a conducting material26is deposited over the exposed Cu region16. Also, the second sacrificial layer20is stripped to reveal only the first sacrificial material18. The conducting material26can be a metal. The metal can be a bottom metal electrode. The bottom metal electrode26can be, e.g., tantalum (Ta), cobalt (Co), ruthenium (Ru), manganese (Mn), tungsten (W), and molybdenum (Mo). However, if electroless deposition takes place, then the metal could also be, e.g., chromium (Cr), nickel (Ni), CoWP (cobalt tungsten phosphorus), and NiWP (nickel tungsten phosphorus). Thus, the bottom metal electrode26is deposited over the exposed Cu region16(right-hand side) and the first sacrificial material18remains over the other Cu region16(left-hand side).

Among the various metal liners for copper (Cu) interconnect technology, tantalum-based (Ta) materials are one of the most widely used because they provide high thermal and mechanical stability and diffusion barrier properties, and good adhesion, all of which result in good reliability. Sputtered tantalum (Ta) and reactive sputtered tantalum nitride (TaN) have been demonstrated to be good diffusion barriers between copper and a silicon substrate due to their high conductivity, high thermal stability, and resistance to diffusion of foreign atoms.

Ion-induced atomic layer deposition (iALD) is one process for depositing TaN. iALD is an example of a plasma-assisted deposition process. Another plasma-assisted deposition process is plasma-enhanced chemical vapor deposition (PECVD). iALD processes can produce TaN layers having a higher density (e.g., about 13 to 14 g/cm3) compared to the density of TaN layers produced with other methods. For example, thermal atomic layer deposition (ALD) commonly produces TaN layers with a density of about 8 to 9 g/cm3. iALD TaN layers also can have a higher conductivity and lower resistivity than thermal ALD TaN layers. iALD processes can have other advantages, including providing very conformal layers, a precise control of the thickness of these layers, the ability to vary the layer composition, and the ability to engineer the surface of the layer to improve the adhesion of a subsequent layer.

FIG. 5is a cross-sectional view of the semiconductor device ofFIG. 4where the bottom metal electrode is nitridized, in accordance with an embodiment of the present invention.

In various embodiments, the top surface of the bottom metal electrode26is nitridized, as shown by the arrows “A.” As such, a metal-nitride cap28is formed over the remaining bottom metal electrode26′.

FIG. 6is a cross-sectional view of the semiconductor device ofFIG. 5where the remaining sacrificial layer is stripped and chemical-mechanical planarization (CMP) is performed, in accordance with an embodiment of the present invention.

In various embodiments, the remaining sacrificial layer18is stripped to expose a top surface15of the Cu region16. Thus, one Cu region16(right-hand side) is shown with a metal-nitride cap28formed thereon and another Cu region16(left-hand side) is shown with its top surface exposed. The metal-nitride cap28can be referred to as a conductive cap or a blocking boundary. The Cu regions16have a thickness greater than the thickness of the blocking boundary28.

FIG. 7is a cross-sectional view of the semiconductor device ofFIG. 6where a blocking boundary is created over the nitridized Cu region and vias/trenches are formed that are aligned with the blocking boundary, in accordance with an embodiment of the present invention.

In various embodiments, a dielectric cap layer30is formed over the Cu regions16. The dielectric cap30hermetically seals the metal below from moisture and/or oxygen. The dielectric cap30also acts as a Cu diffusion barrier, thus preventing Cu from escaping into the ILD above an insulator32.

The insulator32is deposited over the dielectric cap30. A plurality of vias and trenches are subsequently formed that extend through the insulator32. A via33has a proximal end31P and a distal end31D. The distal end31D of the via33extends to the top surface15of the Cu region16.

A trench34has a proximal end35P and a distal end35D. The distal end35D of the trench34extends to a top surface of the magnetic tunnel junction (MTJ)36. The MTJ36is formed over the blocking boundary28. Additionally, several other trenches34can be formed within the insulator32such that they extend a certain length therewith. The via33extends into the dielectric cap30.

The via33is self-aligned with the Cu region16(left-hand side) and the trench34is optionally self-aligned with the blocking boundary28and with the Cu region16(right-hand side). Stated differently, a longitudinal axis (not shown) extends through the center point of the trench34, the blocking boundary28, and the Cu region16. Additionally, a first dielectric cap40and a second dielectric cap42can be formed over the via33and the trenches34.

The dielectric caps40,42can be deposited, planarized, and etched back. The dielectric caps40,42can be, e.g., a nitride film. In an embodiment, the dielectric caps40,42can be an oxide, for example, silicon oxide (SiO), a nitride, for example, a silicon nitride (SiN), or an oxynitride, for example, silicon oxynitride (SiON).

The planarization process can be provided by chemical mechanical planarization (CMP). Other planarization process can include grinding and polishing.

In one or more embodiments, the dielectric caps40,42can have a thickness in the range of about 3 nm to about 30 nm.

The dielectric caps40,42can be deposited, planarized, and etched back so that the dielectric caps40,42extend across all the proximal ends of the vias33and trenches34. The final structure is designated as structure7.

FIG. 8is a cross-sectional view of the semiconductor device ofFIG. 3where the exposed Cu region is recessed, in accordance with another embodiment of the present invention.

In various embodiments, after selective etching is performed, as shown inFIG. 3, the Cu region16is recessed. The recessed Cu region16′ can be accomplished by, e.g., wet etching. The Cu region16′ can be recessed by a distance “X.” The Cu region16can be recessed by, for example, by forming copper oxide and removing with a DHF (dilute hydrofluoric acid) solution.

FIG. 9is a cross-sectional view of the semiconductor device ofFIG. 8where the recessed Cu region is filled with a metal to create a bottom metal electrode, in accordance with an embodiment of the present invention.

In various embodiments, a conducting material56is deposited within the recess of the Cu region16′. The conducting material56can be a metal. The metal can be a bottom metal electrode. The bottom metal electrode56can be, e.g., tantalum (Ta), cobalt (Co), ruthenium (Ru), manganese (Mn), tungsten (W), and molybdenum (Mo). However, if electroless deposition takes place, then the metal56could also be, e.g., chromium (Cr), nickel (Ni), CoWP (cobalt tungsten phosphorus), and NiWP (nickel tungsten phosphorus).

FIG. 10is a cross-sectional view of the semiconductor device ofFIG. 9where the bottom metal electrode is nitridized, in accordance with an embodiment of the present invention.

In various embodiments, the top surface of the bottom metal electrode56is nitridized, as shown by the arrows “A.” As such, a metal-nitride cap58is formed over the remaining bottom metal electrode56′.

FIG. 11is a cross-sectional view of the semiconductor device ofFIG. 10where the remaining sacrificial layer is stripped and chemical-mechanical planarization (CMP) is performed, in accordance with an embodiment of the present invention.

In various embodiments, the remaining sacrificial layer18is stripped to expose a top surface15of the Cu region16. Thus, one Cu region16′ is shown with a metal-nitride cap58formed thereon and another Cu region16is shown with its top surface15exposed. The metal-nitride cap58can be referred to as a conductive cap or a blocking boundary. The Cu regions16,16′ have a thickness greater than the thickness of the blocking boundary58. The blocking boundary58can have a greater thickness than the blocking boundary26′ ofFIGS. 5-7.

FIG. 12is a cross-sectional view of the semiconductor device ofFIG. 11where a blocking boundary is created over the recessed and nitridized Cu region and vias/trenches are formed that are aligned with the blocking boundary, in accordance with an embodiment of the present invention.

In various embodiments, a dielectric cap layer30is formed over the Cu regions16,16′. The dielectric cap30hermetically seals the metal below from moisture and/or oxygen. The dielectric cap30also acts as a Cu diffusion barrier, thus preventing Cu from escaping into the ILD above an insulator32.

The insulator32is deposited over the dielectric cap30. A plurality of vias and trenches are subsequently formed that extend through the insulator32. A via33has a proximal end31P and a distal end31D. The distal end31D of the via33extends to the top surface15of the Cu region16.

A trench34has a proximal end35P and a distal end35D. The distal end35D of the trench34extends to a top surface of the magnetic tunnel junction (MTJ)36′. The MTJ36′ is formed over the blocking boundary58. Additionally, several other trenches34can be formed within the insulator32such that they extend a certain length therewith. The via33extends into the dielectric cap30.

The via33is self-aligned with the Cu region16and the trench34is self-aligned with the blocking boundary58and with the Cu region16′. Stated differently, a longitudinal axis (not shown) extends through the center point of the trench34, the blocking boundary58, and the Cu region16′. Additionally, a first dielectric cap40and a second dielectric cap42can be formed over the via33and the trenches34.

The dielectric caps40,42can be deposited, planarized, and etched back. The dielectric caps40,42can be, e.g., a nitride film. In an embodiment, the dielectric caps40,42can be an oxide, for example, silicon oxide (SiO), a nitride, for example, a silicon nitride (SiN), or an oxynitride, for example, silicon oxynitride (SiON).

The planarization process can be provided by chemical mechanical planarization (CMP). Other planarization process can include grinding and polishing.

In one or more embodiments, the dielectric caps40,42can have a thickness in the range of about 3 nm to about 30 nm.

The dielectric caps40,42can be deposited, planarized, and etched back so that the dielectric caps40,42extend across all the proximal ends of the vias33and trenches34. The final structure is designated as structure9.

Regarding the metal deposition in structure7(FIG. 7) and structure9(FIG. 12), the selective deposition can be cyclic with nitridization steps in between pure metal depositions to give a metal nitride. Nitridation allows the metal to form an effective barrier between the Cu regions and the MTJ stacks.

FIG. 13is a cross-sectional view of a semiconductor device where a thick blocking mask and a thick bottom metal electrode are deposited, in accordance with another embodiment of the present invention.

In various embodiments, a thicker sacrificial layer74can be used as a blocking mask over one of the Cu regions16. Additionally, a thicker bottom metal electrode76can be used over another of the Cu regions16.

FIG. 14is a cross-sectional view of the semiconductor device ofFIG. 13where the bottom metal electrode is nitridized, in accordance with another embodiment of the present invention.

In various embodiments, the top surface of the bottom metal electrode76is nitridized, as shown by the arrows “A.” As such, a metal-nitride cap78is formed over the remaining bottom metal electrode76′.

FIG. 15is a cross-sectional view of the semiconductor device ofFIG. 14where the selective dielectric deposition takes place to fill regions adjacent the nitridized bottom metal electrode, in accordance with another embodiment of the present invention.

In various embodiments, further dielectric12′ can be selectively deposited adjacent the metal-nitride cap78such that the dielectric12′ extends to a top surface of the metal-nitride cap78, as well as to a top surface of the sacrificial layer74. The dielectric12′ can be deposited, planarized, and etched back to be coplanar with the top surfaces of the metal-nitride cap78and the sacrificial layer74. The planarization process can be provided by chemical mechanical planarization (CMP). Other planarization process can include grinding and polishing.

FIG. 16is a cross-sectional view of the semiconductor device ofFIG. 15where a blocking boundary is created over the nitridized Cu region and vias/trenches are formed that are aligned with the blocking boundary, in accordance with another embodiment of the present invention.

In various embodiments, an insulator32is further deposited over the metal-nitride cap78and the sacrificial layer74. A plurality of vias and trenches are subsequently formed that extend through the insulator32. For example, a via33extends to the top surface15of the Cu region16(left-hand side).

A trench34has a proximal end35P and a distal end35D. The distal end35D of the trench34extends to a top surface of the magnetic tunnel junction (MTJ)36. The MTJ36is formed over the blocking boundary78. Additionally, several other trenches34can be formed within the insulator32such that they extend a certain length therewith. The via33extends up to a top surface of the Cu region16(left-hand side).

The via33is self-aligned with the Cu region16and the trench34is self-aligned with the blocking boundary78and with the Cu region16(right-hand side). Stated differently, a longitudinal axis (not shown) extends through the center point of the trench34, the blocking boundary78, and the Cu region16. Additionally, a first dielectric cap40and a second dielectric cap42can be formed over the via33and the trenches34, as described above in detail. The dielectric caps40,42can be deposited, planarized, and etched back. The final structure is designated as structure80.

FIG. 17is a block/flow diagram of an exemplary method for forming a semiconductor device, in accordance with an embodiment of the present invention.

At block102, an insulating layer is deposited over a semiconductor substrate.

At block104, the insulating layer is etched to form trenches for receiving a metal.

At block106, one or more sacrificial layers are deposited.

At block108, portions of the one or more sacrificial layers are etched to expose a top surface of the metal of one or more of the trenches.

At block110, an electrode is selectively deposited over the top surface of the exposed metal.

At block112, the electrode is nitridized to form a barrier between chip components and the metal.

In summary, a method is presented to enable a self-aligned metal bottom electrode for magnetic tunnel junctions (MTJs) by using a block mask to separate out processing between MTJ and non-MTJ regions, by selective metal deposition on exposed copper (Cu), and by nitridization of selective metal cap to form a proper barrier. The advantages of the exemplary embodiments of the present invention include (i) reduction in the cost of masks required for MTJ integration (no bottom electrode critical dimension (CD) mask required), (ii) selective deposition allows self-alignment to avoid concerns over overlay tolerances at that step, and (iii) nitridization allows for effective barrier formation, and adjustments without requiring new physical vapor deposition (PVD) targets.

The exemplary embodiments of the present invention avoid these aforementioned issues by allowing for the creation of localized or selective self-aligned metal caps or blocking boundaries atop of interconnects. Thus, the exemplary embodiments of the present invention apply the metal cap only in certain regions of interest on the chip. The metal caps prevent copper (Cu) diffusion. The metal caps or blocking boundaries are created at the via interfaces (i.e., between the top surface of the Cu region and the distal end of the via). In various embodiments, the blocking boundary can be placed directly underneath the via where the circuit requires a blocking boundary.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps/blocks can be varied within the scope of the present invention.