Systems and methods for off track error recovery

Various embodiments of the present invention provide systems and methods for recovering data from a storage medium. As an example, a data recovery circuit is disclosed that includes: a controller circuit, a data processing circuit, a selector circuit, and a combining circuit. The controller circuit is operable to position a sensor over a track of the storage medium at a first distance from the center of the track to yield a first data set, and to position the sensor over the track of the storage medium at a second distance from the center of the track to yield a second data set. The data processing circuit is operable to process a processing data set, and the selector circuit is operable to select between the first data set and a combined data set as the processing data set. The combining circuit is operable to combine the first data set with at least the second data set to yield the combined data set.

BACKGROUND OF THE INVENTION

The present inventions are related to systems and methods for data retrieval, and more particularly to systems and methods for retrieving data from a track based storage medium.

Various circuits have been developed that provide for accessing data from a storage medium. As an example, a disk drive system typically includes a head that is positioned in relation to data on a storage medium to allow for sensing the information maintained on the storage medium. Where the head is not positioned correctly, the information on the storage medium may not be readable, and an error message is generated. Such a failure to properly recover data from the storage medium is undesirable.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for recovering data from a storage medium.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for data retrieval, and more particularly to systems and methods for retrieving data from a track based storage medium.

Various embodiments of the present invention provide data recovery circuits that include: a controller circuit, a data processing circuit, a selector circuit, and a combining circuit. The controller circuit is operable to position a sensor over a track of the storage medium at a first distance from the center of the track to yield a first data set, and to position the sensor over the track of the storage medium at a second distance from the center of the track to yield a second data set. The data processing circuit is operable to process a processing data set, and the selector circuit is operable to select between the first data set and a combined data set as the processing data set. The combining circuit operable to combine the first data set with at least the second data set to yield the combined data set.

In some instances of the aforementioned embodiments, the combining circuit is an averaging circuit operable to average the first data set with at least the second data set to yield the combined data set. In some cases, the averaging circuit includes: a coefficient table, an accumulation memory, a first multiplier circuit, a second multiplier circuit, and a summation circuit. The coefficient table is operable to provide a first coefficient and a second coefficient each corresponding to a number of data sets included in the combined data set. The accumulation memory is operable to store the combined data set. The first multiplier circuit is operable to multiply the first data set by the first coefficient to yield a first weighted data set, and the second multiplier circuit is operable to multiply a prior instance of the combined data set by the second coefficient to yield a second weighted data set. The summation circuit is operable to sum the first weighted data set with the second weighted data set to yield the combined data set. In one or more particular cases, the first coefficient is one and the second coefficient is zero when the first data set is an initial data set, and when the first data set is greater than the seventh consecutive data set the first coefficient and the second coefficient are the same as for a previously combined data set.

In various instances of the aforementioned embodiments, the circuit further includes an analog to digital converter circuit operable to receive a signal derived from the head and to provide a corresponding series of digital samples; and an equalizer circuit operable to equalize the series of digital samples to yield the first data set and the second data set. In some instances of the aforementioned embodiments, the data processing circuit includes a data detection circuit and a data decoding circuit. In one or more instances of the aforementioned embodiments, the circuit further includes a head location controller circuit operable to position the sensor relative to the storage medium. In some such instances, the first distance from the center of the track is controlled by the head location controller based upon an input from the controller circuit, and the first distance from the center of the track is between a maximum positive offset and a negative maximum offset. In some cases, the input from the controller circuit is generated at least in part on a programmable offset value and a programmable step value.

Other embodiments of the present invention provide methods for data recovery. The methods include: providing a storage medium having data stored along a track; receiving a first data set corresponding to information sensed from the track using a sensor disposed over the track at a first offset distance from the center of the track; receiving a second data set corresponding to information sensed from the track using the sensor disposed over the track at a second offset distance from the center of the track; combining the first data set with at least the second data set to yield a combined data set; and processing the combined data set.

In some cases, processing the combined data set includes performing a data detection and a data decoding on the data set. In various instances of the aforementioned embodiments, the method further includes: positioning the sensor over the track at the first offset distance from the center of the track; and positioning the sensor over the track at the second offset distance from the center of the track. In some instances of the aforementioned embodiments, the first offset distance from the center of the track is a maximum offset, and the maximum offset is programmable. In various instances of the aforementioned embodiments, the method further includes calculating the second offset from the center of the track. In such instances, calculating the second offset from the center of the track is done by adding a step value to a previous offset position to yield the second offset from the center of the track. In some instances, combining the first data set with at least the second data set to yield the combined data set includes averaging the first data set with at least the second data set such that the combined data set is an average data set.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for data retrieval, and more particularly to systems and methods for retrieving data from a track based storage medium.

Turning toFIG. 1, three track read scenarios100,101,102are depicted that occur in state of the art data recovery. Scenario100shows a head105(i.e., a sensing device or sensor) flying over a track195in a direction103. The dashed center line represents the alignment of head105relative to track195. In scenario100, head105is well centered over track195. Such a centered disposition of head105relative to track195yields a sensed signal output120with an amplitude135.

Scenario101shows a head110flying over a track195in a direction113. The dashed center line represents the alignment of head110relative to a track196. In scenario101, head110is offset from track196by a positive delta distance114. Such an offset orientation of head110relative to track196yields a sensed signal output125with an amplitude140. Of note, amplitude140is less than amplitude135. Such a reduction in amplitude can result in an inability to recover the data sensed from track196.

Scenario102shows a head115flying over a track197in a direction123. The dashed center line represents the alignment of head115relative to a track197. In scenario102, head115is offset from track197by a negative delta distance124. Such an offset orientation of head115relative to track197yields a sensed signal output130with an amplitude145. Of note, amplitude145is less than amplitude135. Such a reduction in amplitude can result in an inability to recover the data sensed from track197.

Turning toFIG. 2, a storage system200including a read channel circuit210with an off track data recovery circuit is shown in accordance with various embodiments of the present invention. Storage system200may be, for example, a hard disk drive. Storage system200also includes a preamplifier270, an interface controller220, a hard disk controller266, a motor controller268, a spindle motor272, a disk platter278, and a read/write head276. Interface controller220controls addressing and timing of data to/from disk platter278. The data on disk platter278consists of groups of magnetic signals that may be detected by read/write head assembly276when the assembly is properly positioned over disk platter278. In one embodiment, disk platter278includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly276is accurately positioned by motor controller268over a desired data track on disk platter278. Motor controller268both positions read/write head assembly276in relation to disk platter278and drives spindle motor272by moving read/write head assembly to the proper data track on disk platter278under the direction of hard disk controller266. Spindle motor272spins disk platter278at a determined spin rate (RPMs). Once read/write head assembly278is positioned adjacent the proper data track, magnetic signals representing data on disk platter278are sensed by read/write head assembly276as disk platter278is rotated by spindle motor272. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter278. This minute analog signal is transferred from read/write head assembly276to read channel circuit210via preamplifier270. Preamplifier270is operable to amplify the minute analog signals accessed from disk platter278. In turn, read channel circuit210decodes and digitizes the received analog signal to recreate the information originally written to disk platter278. This data is provided as read data203to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data201being provided to read channel circuit210. This data is then encoded and written to disk platter278.

In some cases, read channel circuit210is unable to recover the originally written data. In such cases, it may be tested whether the inability to recover the data is due to an improper positioning of read/write head assembly276relative to the track on disk platter278from which data is being read. Such an improper positioning results in an unacceptable lateral distance between read/write head assembly276and the center of the track being read. In such cases, the off track data recovery circuit included in read channel circuit210attempts to recover the data. The off track data recovery circuit may be implemented similar to that discussed in relation toFIG. 3below, and/or may operate consistent with the method discussed in relation toFIG. 4below.

It should be noted that storage system200may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system200may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.

Turning toFIG. 3, an off track data recovery circuit300is shown in accordance with some embodiments of the present invention. Off track data recovery circuit300includes a controller circuit305operable to provide control signals307to a head location controller circuit310. In turn, head location controller circuit310provides a location control311to a head312. In response to location control311, head312is positioned relative to a track on a storage medium315. Controller circuit305is operable to adjust the location of head312relative to a given track from a maximum offset (e.g., a maximum positive offset) from one direction from the center of the track as indicated by a maximum offset input303by discrete step amounts indicated by a programmable step value302to the maximum offset (e.g., a maximum negative offset) from the opposite direction from the center of the track. In some cases, both maximum offset input303and programmable step value302are programmable. In other cases, one or both of the aforementioned are fixed values.

At each step that controller circuit305moves head312relative to the center of the track being read, data is sensed from storage medium315and provided as an analog output316to an analog front end circuit320. Analog front end circuit320includes various circuitry used to prepare analog output316for analog to digital conversion by analog to digital converter circuit325. In some embodiments of the present invention, analog front end circuit320includes a preamplifier circuit (not shown) that amplifies analog output316, and a continuous time filter (not shown) that filters the amplified output. In particular, analog front end circuit320provides a processed output321to analog to digital converter circuit325where it is converted to a series of digital samples326.

Digital samples326are provided to an equalizer circuit330that performs an equalization to yield an equalized data set331to a multiplexer circuit332. In some embodiments of the present invention equalizer circuit330is a digital finite impulse response filter as are known in the art. Multiplexer circuit332provides either equalized data set331or an averaged data set351as a processing data set333. Controller circuit305provides a selector output306that controls which of the multiplexer inputs are provided as processing data set333.

Processing data set333is provided to a data processing circuit335where it is processed in an attempt to recover the data originally written to storage medium312. The recovered data is provided as data output337, and a convergence indicator output336is provided to controller circuit305. Data processing circuit335may be any circuit known in the art that is capable of decoding information in an attempt to recover an original data set. In one particular embodiment, data processing circuit includes a maximum a posteriori detector circuit and a low density parity check circuit as are known in the art. Other embodiments of the present invention include a data processing circuit that includes a Viterbi algorithm data detector circuit and a low density parity check circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data processing circuits that may be used in relation to different embodiments of the present invention.

Off track data recovery circuit300includes a read averaging circuit370(shown in dashed lines) that is operable to average each of the data sets that are re-read each time controller circuit305causes an offset from the center of the track being read. Read averaging circuit370includes a counter circuit340that increments each time the track is successfully re-read under direction of a count output308. In some embodiments, a data set is considered successfully re-read where the synchronization information included as part of the data set was properly identified. Counter circuit340is also reset once either the data from the particular track has been recovered as indicated by convergence indicator output336or once all of the steps between the positive maximum offset and the negative maximum offset from the center of the track have been processed. Counter circuit340provides a count output341to an average coefficient table345. Count output341corresponds to the number of data sets that have been accumulated in an accumulation memory350.

Based on count output341, average coefficient table345provides a new data averaging coefficient347and an accumulated data averaging coefficient346. These averaging coefficients are used to weight the newly received data relative to the already accumulated data to yield an average value. For example, where the count value is zero, new data averaging coefficient347is one and accumulated data averaging coefficient346is zero. In this case, equalized data set331(the newly received data set) is multiplied by one by a multiplier circuit347and provided as a weighted output356to a summation circuit360. Averaged data set351from accumulation memory350is multiplied by zero by a multiplier circuit365and provided as a weighted output366to summation circuit360. In turn, summation circuit360adds weighted output356to weighted output366to yield an average output347that is stored to accumulation memory350. Of note, when count output341is zero (i.e., equalized data set331corresponds to the first re-read of the track), average output361is equalized data set331.

As another example, when count output341is one new data averaging coefficient347is 0.5 and accumulated data averaging coefficient346is 0.5. In this case, equalized data set331is multiplied by 0.5 by multiplier circuit347and provided as weighted output356to summation circuit360; and averaged data set351is multiplied by 0.5 by multiplier circuit365and provided as weighted output366to summation circuit360. In turn, summation circuit360adds weighted output356to weighted output366to yield an average output347that is stored to accumulation memory350. Of note, in this case (i.e., equalized data set331corresponds to the second re-read of the track), average output361is the average of equalized data set331and averaged data set351.

As yet another example, when count output341is two new data averaging coefficient347is 0.33 and accumulated data averaging coefficient346is 0.67. In this case, equalized data set331is multiplied by 0.33 by multiplier circuit347and provided as weighted output356to summation circuit360; and averaged data set351is multiplied by 0.67 by multiplier circuit365and provided as weighted output366to summation circuit360. In turn, summation circuit360adds weighted output356to weighted output366to yield an average output347that is stored to accumulation memory350. Of note, in this case (i.e., equalized data set331corresponds to the third re-read of the track), average output361is the weighted average of equalized data set331and averaged data set351.

Controller circuit305asserts selector output306such that averaged data set351is provided as processing data set333by multiplexer circuit332. As such, averaged data set351is processed by data processing circuit335to see if the averaged data set converges. Of note, when count output341is equal to zero, selector output306is asserted such that equalized data set331is provided as processing data set333. When count output341is greater than zero, selector output306is asserted such that averaged data set351is provided as processing data set333.

This process of averaging and performing data processing continues until either the data sets corresponding to each of the steps between the positive maximum offset and the negative maximum offset from the center of the track have been processed, or until a data convergence is indicated by convergence indicator output336. The following pseudocode describes the operation of read averaging circuit370:

In some cases to limit circuit complexity, any count output341that is greater than eight uses the same values for new data averaging coefficient347and accumulated data averaging coefficient346. Thus, even where the number of steps between the negative maximum offset and the positive maximum offset is greater than eight, the maximum number of eight will be used in the averaging process. The following pseudocode describes the operation of read averaging circuit370where the coefficients based on the count value are limited:

Turning toFIG. 4, a flow diagram400depicts a process in accordance with some embodiments of the present invention for off track data recovery. Following flow diagram400, a data set is received (block405). The data set is received by positioning a head over a storage medium in relation to a track. The data set is passed to an analog front end circuit where analog front end processing is performed (block410). Such analog processing may be any processing known in the art for amplifying and/or filtering an analog signal. The processed data is provided to an analog to digital converter circuit where an analog to digital conversion is performed (block415). Such an analog to digital conversion yields a series of digital samples corresponding to the input received from the analog front end processing. An equalization process is performed on the series of digital samples to yield an equalized data set (block420). In some cases, the equalization process is performed by a digital finite impulse response filter circuit. Data processing is then performed on the equalized data set in an attempt to recover data originally written to the storage medium (block425). Such data processing may be performed using any data processing approaches and/or circuitry known in the art. For example, the data processing circuit includes a maximum a posteriori detector circuit and a low density parity check circuit as are known in the art. Other embodiments of the present invention include a data processing circuit that includes a Viterbi algorithm data detector circuit and a low density parity check circuit as are known in the art. Based upon the disclosure provide herein, one of ordinary skill in the art will recognize a variety of circuitry and/or data processing methods that may be used in relation to different embodiments of the present invention.

It is determined whether a retry is desired (block430). A retry is desired, for example, where the initial reading of the data set failed to converge. Such convergence occurs when the error correction codes and/or parity checking done by the data processing indicates an acceptable conclusion to the processing. Where a retry is not desired (e.g., the data set converged) (block430), the recovered data set is provided as an output (block435).

Alternatively, where a retry is desired (block430), the head used to sense the data from the storage medium is moved to a positive maximum offset from the center of the track from which the data was originally read (block440). With the head in this positive maximum offset orientation, the data set is re-read from the track (block445). This re-read process includes moving or flying the head over the track with the defined offset from what is expected to be the center of the track associated with the data set being read. The received data set is passed to an analog front end circuit where analog front end processing is performed (block450). Again, such analog processing may be any processing known in the art for amplifying and/or filtering an analog signal. The processed data is provided to an analog to digital converter circuit where an analog to digital conversion is performed (block455). Again, such an analog to digital conversion yields a series of digital samples corresponding to the input received from the analog front end processing. An equalization process is performed on the series of digital samples to yield an equalized data set (block460).

The recently received data set is averaged with previously re-read data sets (block465). In the case where the data set is the first re-read data set, the average is simply the currently received data set. The resulting averaged data set is stored to a buffer (block470). Data processing is performed on the averaged output (block475). Again, such data processing may be performed using any data processing approaches and/or circuitry known in the art. Where the data processing converges (block480), the output resulting from the data processing is provided (block485).

Otherwise, where the data processing failed to converge (block480) it is determined whether the track offset has been decremented to the maximum negative offset (block490). Where the track offset has not been decremented to the maximum negative offset (block490), the track offset is decremented by a step value, and the head is re-positioned over the track in accordance with the new track offset (block496). In some embodiments of the present invention, the step value and the maximum track offset value are programmable. With the head in this orientation, the processes of blocks445,450,455,460,465,470,475,480,485,490,495,496are repeated. Alternatively, where the track offset has been decremented to the maximum negative offset (block490) a failure to recover indication is provided (block495).