Conversion of digital signals into spiking analog signals

A digital signal may be converted into a spiking analog signal. A different constant current may be applied to each of a plurality of switch circuits. Each bit of the digital signal may be applied to a corresponding one of the plurality of switch circuits. Each switch circuit may apply the corresponding constant current to a common output when the corresponding bit has a predetermined value. Each switch circuit may not apply the corresponding constant current to the common output when the corresponding bit does not have the predetermined value. A common current may be applied at the common output to a spiking neuron circuit.

FIELD

The present invention relates generally to the technical field of electronic circuits. More particularly, the present invention relates to the conversion of digital signals into analog signals.

BACKGROUND

As is known in the art, digital-to-analog converters (DACs) have been used in a wide variety of applications to convert an N-bit digital signal into a corresponding analog signal. Artificial neural networks (ANNs) that use spiking analog signals for communication between individual neuron circuits, are known for their low power consumption and their low circuit complexity compared to artificial neural networks using digital logic for implementing the network components.

Digital images, i.e., one or more still image or sequences of images, such as a video streams, often are digitally encoded as red-green-blue (RGB) images. Each RGB image consists of a large number of pixels, and each pixel data consists of, e.g., 8 bits of data for the color red, representing 256 red values, 8 bits of data for the color green, representing 256 green values, and 8 bits of data for blue, representing 256 blue values, for a total of 24 bits per image pixel.

Digital processing typically uses variations of convolutional neural networks that consist of a plurality of network layers. The individual network layers have different functions, and therefore, result in different circuitry, connectivity, and topology. For example, a convolutional network without storage elements, i.e., a network that evaluates only the current input signals with disregard to any previous input signals, consists of sampling layers, convolutional layers, and one or more output layers. One well-known example is the feedforward convolutional network style named “LeNet” and its various slightly different implementations by main author Yann LeCun and other research groups.

SUMMARY

Disclosed herein is a method of converting a digital signal into a spiking analog signal. A different constant current is applied to each of a plurality of switch circuits. Each bit of the digital signal is applied to a corresponding one of the plurality of switch circuits. Each switch circuit applies the corresponding constant current to a common output when the corresponding bit has a predetermined value and does not apply the corresponding constant current to the common output when the corresponding bit does not have the predetermined value. A common current at the common output is applied to a spiking neuron circuit.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

Referring toFIG. 1there is shown a DAC circuit12having a number of digital inputs10and at least one analog output, and a spiking neuron circuit16, having an analog signal input and an analog output18. The output of the converter12and the input of the neuron16may be connected through wire14.

In more detail, the number of digital inputs10may be any integer number that is equal to or higher than one. The DAC12may interpret the digital signal applied to the N inputs as an N-bit signal value and generate an analog current, which is proportional to the N-bit input signal, at the output of converter12.

Wire14may provide a current to the input of spiking neuron16. Once a sufficient amount of current flows through14into16, the neuron16may generate a waveform at its output18that resembles a spiking waveform.

FIG. 2is an example diagram showing how multiple instances of the invention ofFIG. 1may be connected to a multi-layer neural network26. Each of the four spiking neuron circuits24may act as an input layer neuron of the network and may be connected to one or more spiking neurons28and30of the intermediate network layer. It is known in the art that the connections34and36between the network layers may implement weighting functions, also referred to as weights, assigning unique weights for each connection between the outputs of spiking neurons24and neurons28and30.

The outputs of neurons28and30may be connected to an output layer neuron32of network26through the weighted connections36. The output of spiking neuron32may be connected to an analog-to-digital converter circuit38that provides a digital signal40at its output for consumption of connected digital logic.

Referring now to the circuit shown inFIG. 3, which is a component of the DAC block12ofFIG. 1, a current source42may provide a constant current on wire44to the two conducting path through the switches46and48, which are controlled by a single digital input value “Bit” from10and its inverted value “Bit bar.” If switch46is on, the entire current from source42may flow through resistor50to the common ground connection of the circuit. If switch48is activated, the current from source42may flow through resistor52into node54instead.

FIG. 4represents a multitude of circuits as shown inFIG. 3to implement an N-bit DAC with N being an integer number of 1 or higher. The outputs of switches46that are controlled by inverted input signals, may be connected over resistances50to the common ground node of the circuit. The outputs of switches48, inFIG. 3node54and shown here inFIG. 4, which are controlled by the non-inverted input signals, such as “Bit0” and “Bit N−1” may be connected through net14and fed to the output pin of DAC logic.

It is known to those skilled in the art that resistors50and52may alternatively be implemented as a multitude of transistors by biasing the transistor gates such that the transistors act as devices with a constant resistance.

FIG. 4also illustrates a current mirror circuit used as the common current source for each branch of the DAC. A very small constant current in the nano-ampere to micro-ampere range may be drawn from the current source74and may flow through transistors56and58. It is known to those skilled in the art that two major parameters of field effect transistors (FETs), such as56and58, may be the dimensions of the conducting channel. The dimensions may be defined by the width “W” of the channel and length “L” of the channel. As is further known to those skilled in the art, the usual way of describing the channel dimensions may be by defining the ratio of the width to the length of the channel as “W/L”. An increase in the width may reduce the channel resistance, while an increase in the length of the channel may increase the channel resistance.

The pair of transistors56and58may build a current mirror circuit with transistors60and62. In an example implementation in a 65 nm CMOS technology, the ratio of transistor width to length for node56and58may be W/L=1, e.g., W=60 nm and L=60 nm. It is known to those skilled in the art that if the transistor width-to-length ratios of60and62are chosen to be the same as those of56and58(W/L=1), the resulting current through node44may be the same as the current through current source74.

Transistors56and58also represent a current mirror with transistors70and72. If, as an example, “N” is chosen to be 2, a 2-bit digital-to-analog converter may be implemented. In that case, the width-to-length ratio of transistors70and72may be chosen to be W/L=2, so that the current flowing through transistors70,72, switch48of bit1, and resistor52to node14is twice the amount of the current flowing through transistors60,62, switch48of bit0and resistor52. It is known to those skilled in the art that this D/A circuitry may be extended to more than two input bits by adding bit slices with transistor ratios of W/L=4, W/L=8, and so on, until the desired number of digital input bits is achieved. As an example, using 8-bit digital input data, the width-to-length ratios of transistors70and72may be W/L=128. It is also known to those skilled in the art that any transistor with a width W that is p times larger than the smallest width used in the design, may be replaced by p transistors, each having a width of W/p.

It is understood for someone skilled in the art that independent of the values that are applied to the N-bit inputs, the total current drawn from current source74may be constant.

The transistors56,58,60,62,70, and72may be implemented as p-channel metal-oxide-semiconductor field-effect transistors (P-MOSFET or PMOS) transistors. The switches46and48may be implemented as p-channel (PMOS) or n-channel MOSFET (NMOS) or bipolar transistors. In the preferred implementation, all transistors inFIG. 4may be implemented as PMOS transistors. Also in the preferred implementation, the resistive elements50and52, may be implemented using PMOS transistors.

The constant current drawn from current source may enable an accurate high-speed adjustment of the output current through node14and therefore accurate and high-speed analog signaling from the DAC12to the spiking neuron circuit16ofFIG. 1. The drawing of constant amount of current through the entirety of all resistive elements50and52ofFIG. 4, independent of the N-bit digital input data, may allow for a smooth and continuous current flow through node14when one or more of the N inputs change their values.

FIG. 5represents the circuit implementation of the current source74inFIG. 4. It is known to those skilled in the art that the combination of NMOS transistors78,80,82, and84may implement a current mirror, such that the constant current through resistor76is “mirrored” in the output current on node86. In one example implementation, where VDD may be set to 1.8V, the resistor76may have a value of 270MΩ, and the W/L ratios of transistors are set to 2/1 (e.g., W=240 nm and L=120 nm), the resulting constant current of the current source, when used as in74inFIG. 4, may be approximately 5 nA.

Referring now toFIG. 6, the spiking neuron circuit block ofFIG. 1, may include an input14, a voltage source88, capacitor90, a switch92, a resistive element94connected to one connector of the switch and connected to the ground terminal, a differential amplifier circuit96, a feedback loop net98that controls switch92, and the output terminal and net100.

In one implementation, the resistive element94may be implemented as an n-channel MOSFET transistor (NMOS).

It is known to those skilled in the art that the differential amplifier96may output a positive voltage on net100when the input voltage on node14exceeds the voltage generated by voltage source88.

A current entering the circuit at node14may charge the capacitor90until a certain voltage is reached on node14that surpasses the threshold voltage, defined by voltage source88, needed for the amplifying circuit96to change its output value from approximately zero to a voltage close to or identical to the operating voltage of the circuit inFIG. 6. Once the output voltage, and therefore the voltage on node100, reaches a threshold voltage, switch92, which is connected to node100through net98, may become conducting and discharges capacitor76through resistor94towards ground.

It is understood for someone skilled in the art that the process of charging the capacitor90by means of a constant current delivered to neuron input14may follow a certain time constant. Also known to those skilled in the art is that the resulting waveform on output node100may resemble that of a spike. The frequency of spikes emitted from the neuron circuit may be proportional to the current entering the circuit on node14.

It is understood for someone skilled in the art that the power consumption of the circuit shown inFIG. 6, including the amplifying circuit96, may be close to zero at all times in which the input signal on node14is zero. The circuit shown inFIG. 6may only consume a measurable amount of power when the input signal on node14causes the capacitor90to charge to the point that the voltage over capacitor90causes the amplifying circuit96to output a waveform, thus, causing feedback net98and switch92to trigger, resulting in a spiking waveform on output100.

FIG. 7is an example detailed circuit implementation of the circuit inFIG. 6. In this figure, the differential amplifier circuit96ofFIG. 6may be replaced by a comparator circuit, consisting of transistors104,106,108, and110, and resistive element112, as well as a pair of inverter circuits114and116. As is known in the art, the pair of inverters114and116may be used for signal shaping of the spiking signal on output node100as well as for driving high loads at output100.

It is known to someone skilled in the art that the capacitor102may provide positive feedback from the output node100to the input node14of the differential amplifier, causing the voltage on node14to increase faster than it would solely through the input current entering the circuit through node14. Once the voltage on net98surpasses a certain value determined by the resistance of94and the transistor properties of92, the capacitor90may quickly discharge to ground, the output voltage100may return to about zero and the circuit may be ready to charge capacitor90again and create another spike at the output100.

In one example implementation in a 65 nm CMOS technology, the operating voltage VDD may be 1.8V, the capacitances of90and102may be 5 fF, the width-to-lengths ratios of PMOS transistors104and108may be 2/1, the width-to-length ratios of NMOS transistors106and110may be 1/1, the width-to-length ratio of NMOS transistor92may be ½, the resistance of94may be 1MEGΩ, the resistance of112may be 470KΩ, the voltage88may be 0.7V, and the inverter circuits114and116may be implemented as standard CMOS inverters.

The arrangements described herein may enable an accurate conversion of an N-bit digital signal into a spiking analog signal of a given and mostly constant amplitude; further, this conversion may be performed using a minimal amount of power, and even further, the conversion of the digital input signals into analog spiking signals may be possible over a wide range of frequencies. In one example implementation, as shown inFIG. 1, with N=5 input bits, an input signal frequency of 5.0 MHz and activity ratios for bit0of 100%, bit1of 50%, bit2of 25%, bit3of 12.5%, and bit4of 6.25%, the D/A converter circuit and the spiking neuron circuit may draw a combined 68 μA at VDD=1.8V, resulting in a total power consumption of 122.4 μW.

In another embodiment of the invention, a current mirror circuit may be used that is composed of NMOS transistors instead of the PMOS transistors56,58,60,62,64, and66.