Integrated planar-trench gate power MOSFET

Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.

FIELD OF THE INVENTION

Aspects of the present disclosure generally relate to transistors and more particularly to Vertical Double-Diffused metal oxide semiconductor (VDMOS) field effect transistors and Trench Gate metal oxide semiconductor field effect transistors (MOSFETs).

BACKGROUND OF THE INVENTION

The consumer market demands ever-smaller devices. Additionally, computing power and performance increases with an increase in the number of transistors that can fit on a single wafer. Cooling and power usage decreases with a reduction of on-resistance (Rdson) by reducing transistor pitch.

Currently for high voltage applications, there exists a limitation on the pitch of planar transistors. As the distance between body regions sharing a gate decreases the lateral depletion rate of the charge carriers in the JFET region between the two body regions increases. This leads to an increase in the Resistance from drain to source (RDS). A solution to this is to increase the doping concentration of the JFET region but there are limits to the resulting size decrease.

It is within this context that aspects of the present disclosure arise.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

The disclosure herein refers silicon doped with ions of a first conductivity type or a second conductivity. The ions of the first conductivity type may be opposite ions of a second conductivity type. For example, ions of the first conductivity type may be n-type, which create charge carriers when doped into silicon. Ions of the first conductivity type include phosphorus, antimony, bismuth, lithium and arsenic. Ions of the second conductivity may be p-type, which create holes for charge carriers when doped into silicon and in this way are referred to as being the opposite of n-type. P-type type ions include boron, aluminum, gallium and indium. While the above description referred to n-type as the first conductivity type and p-type as the second conductivity the disclosure is not so limited, p-type may be the first conductivity and n-type may be second the conductivity type.

In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. For convenience, use of + or − after a designation of conductivity or net impurity carrier type (p or n) refers generally to a relative degree of concentration of designated type of net impurity carriers within a semiconductor material. In general terms, an n+ material has a higher n type net dopant (e.g., electron) concentration than an n material, and an n material has a higher carrier concentration than an n− material. Similarly, a p+ material has a higher p type net dopant (e.g., hole) concentration than a p material, and a p material has a higher concentration than a p− material. It is noted that what is relevant is the net concentration of the carriers, not necessarily dopants. For example, a material may be heavily doped with n-type dopants but still have a relatively low net carrier concentration if the material is also sufficiently counter-doped with p-type dopants. As used herein, a concentration of dopants less than about 1016/cm3may be regarded as “lightly doped” and a concentration of dopants greater than about 1017/cm3may be regarded as “heavily doped”.

Introduction

According to aspects of the present disclosure, the pitch of transistor devices may be improved by creating an integrated planar-trench gate having a contiguous gate portion and trench portion. The integrated planar-trench gate allows for smaller planar gate sizes and reduces RDS. Prior devices have implemented a combination of a planar gate and a trench gate separated by an insulating layer and electrically coupled via wires. These prior devices were made with a large deep trench and it was therefore impossible to form an integrated gate-trench that was contiguous between the gate portion and the trench portion having a flat planar gate. Filing the larger trenches of prior devices with insulating layers and conductive layers resulted in gates that were not sufficiently flat. An intermediate insulating layer between the planar gate and the trench gate was used to create a flat gate. Creating an opening through the insulating layer between the planar gate and the trench gate to electrically couple the two gates was impractical because of difficulties in alignment of the trench gate and planar gate. As such, the planar gate and the trench gate were electrically connected using wire leads instead of direct contact between the conductive layers of the two gates. The deep trench and indirect connection of the two gates in prior devices increased the complexity of prior devices and made shrinking the size of the prior devices difficult.

In solution to this a transistor device and method of making thereof has been devised, the transistor device comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type opposite the first conductivity type is formed in the epitaxial layer and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. The device includes an integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a trench gate portion formed in a trench in the epitaxial layer. In some implementations, the device may further include a localized JFET implant region, heavily doped with first conductivity type formed around the bottom and sides of the trench gate portion. A region of the epitaxial layer lightly doped with the first conductivity type may separate the localized JFET implant and the body region. In some implementations, the trench gate portion may be formed in the body region of the epitaxial layer.

In some other implementations, the depth of a bottom of the trench gate portion in the substrate may be less than a lowest doped depth of the body region. In other implementations, the trench-gate portion may be insulated from the epitaxial layer by a thick insulating layer at a bottom of the gate trench that is thicker than an insulating layer on at least one side of the gate trench. In yet other implementations, the epitaxial layer may further include alternating body region columns doped with the second conductivity type and columns of epitaxial layer lightly doped with the first conductivity type that form a so-called superjunction structure. The sidewalls of a trench of the gate trench portion of the device may intersect with a bottom of the trench of the gate trench portion at an angle that is greater than 90 degrees in some implementations. The gate trench portion of the transistor device may have a trench depth of between 0.3 and 0.8 micrometers. The device may have a width of the insulating layer at the bottom a trench of the gate trench portion may be 1.5 to 2 times as thick as insulating layer on a side of the trench in some implementations of the present disclosure.

Device

FIG.1depicts a side cut away view of the integrated planar-trench gate transistor device according to aspects of the present disclosure. As shown, the integrated planar-trench gate transistor device includes a substrate101heavily doped with ions of a first conductivity type. An epitaxial layer102may be formed on top of the substrate101. By way of example, and not by way of limitation, the epitaxial layer102may be grown on a surface of the substrate101using epitaxial growth or otherwise deposited on the surface of the substrate. A trench103is formed in the epitaxial layer102. In some implementations, a region around the sides and bottom of the trench103may be heavily doped with ions of the first conductivity type, forming a localized JFET implant region108. A dielectric layer106is formed on the surface of the substrate to electrically insulate the planar gate portion107of the integrated planar-trench gate from the epitaxial layer102. The dielectric layer106also lines sidewalls and bottom of the trench103creating the insulating layer for the sidewalls105and bottom104of the trench portion of the integrated planar-trench gate. In some implementations, the insulating layer on the bottom104of the trench103may be 1.5 to 2 times as thick as the insulating layer on the sides103of the trench referred herein as the thick bottom insulator. The insulating layers may be comprised of dielectric materials such as silicon oxide. The planar gate portion107may be formed by patterning a conductive layer formed on a surface of the insulating layer106. Part of the conductive layer fills portions of the trench103that are not occupied by the dielectric layer106and is insulated from the epitaxial layer102by portions of the insulating layer on the sidewalls105and bottom104of the trench. The conductive layer creates the integrated planar-trench gate that is contiguous between the planar portion107of the gate and the trench portion112of the gate. The conductive layer may be comprised of polycrystalline silicon or other conductive material such as Titanium Nitride (TiN) or Tungsten. A gate contact113is coupled to the conductive layer107. Due to the contiguous nature of planar gate portion107and trench gate portion112of the gate, the trench portion112does not have a separate gate contact. The trench portion112is instead maintained at gate potential levels by virtue of being contiguous with the planar gate portion107of the gate. One or more body regions109may be formed in the epitaxial layer102. Source regions110may be formed in the body109of the epitaxial layer102. A source contact111couples the source region to the source and may also include a body short contact. A drain metal114may be formed on the bottom of the substrate101. A drain contact115may be coupled to the drain metal114.

During operation, a gate potential at the gate contact113allows current to be conducted through the transistor device. For example and without limitation in an N type MOSFET configuration, current applied to the drain contact115is conducted through the drain metal114and through the substrate101, and epitaxial layer102. Charge carriers from the epitaxial layer102combine with oppositely-charged holes in the body region109allowing current to be conducted to the source region110and the source contact111.

FIG.2shows a side cut away view of an alternative implementation of the integrated planar-trench gate transistor device according to aspects of the present disclosure. In the implementation shown inFIG.2, the body region209touches a localized junction field-effect transistor (JFET) implant region208. Additionally the source region210is located closer to the gate trench203than in implementations without intersecting body regions and an integrated planar-trench gate. As shown, the two body regions209are arranged so close to the trench203that the regions intersect underneath the trench203. The planar portion207of the integrated planar-trench gate is shorter than in implementations that do not include intersecting body regions underneath the trench. The integrated planar-trench gate and localized JFET implant208allows for a decrease in the pitch of transistor device as the width of the planar portion207of the integrated planar-trench gate may be reduced without significantly influencing the RDSof the device.

FIG.3depicts shows a side cut away view of super junction transistor device having the integrated planar-trench gate according to aspects of the present disclosure. As shown, the body regions309of the device include columns320doped with ions of the second conductivity type that terminate near the substrate101. The epitaxial layer302forms columns doped with ions of the first conductivity type. Thus, the combination of doped body columns320and regions of the epitaxial layer doped with ions of the first conductivity302creates alternating columns doped with first conductivity type and second conductivity type in the epitaxial layer respectively for a super junction device.

Method of Making

FIGS.4A-4Jshow a side cut away view of the method of making the integrated planar-trench gate transistor device according to aspects of the present disclosure.FIG.4Ashows a substrate401that is heavily doped with ions of the first conductivity type and an epitaxial layer402that is more lightly doped according to aspects of the present disclosure. The substrate401may be doped at an ion concentration of between 1×1019and 1×1020cm−3. The substrate may be composed of, for example and without limitation, silicon, silicon carbide, gallium nitride or gallium arsenide. An epitaxial layer402may be formed on a surface of the substrate401. The epitaxial layer402may be grown on the top surface of the epitaxial layer401by such processes as vapor phase epitaxy. The epitaxial layer402may be lightly doped with ions of the first conductivity type during or after formation. The epitaxial layer402may be doped at an ion concentration of between 1×1017and 6×1017cm−3.

FIG.4Bdepicts a side cut away view of formation of the trench403in the epitaxial layer402for the integrated planar-trench gate transistor device according to aspects of the present disclosure. Initially a hard mask comprised of a silicon oxide layer407, Silicon nitride layer406, silicon oxide layer405stack may be deposited on the surface of the epitaxial layer402. The oxide layer,407,405and nitride layer406may be formed with by chemical vapor deposition techniques (CVD) to form SiO2and Silicon Nitride or by a thermal oxidation process to form SiO2. A mask pattern404is formed on a surface of the hard mask. The mask pattern404may be created using photolithography techniques or applied by a mechanical masking process. The mask pattern404includes a trench gap408. An etching process such as plasma dry etch or a wet etching using phosphoric acid or other such selecting etchant is applied to the mask pattern and hard mask. The hard mask is etched away at the trench gap408exposing the epitaxial layer402in the trench gap. The epitaxial layer402may then be etched to a desired depth through the trench gap408by plasma etching techniques such as deep reactive ion etching (DRIE). The depth of the trench403created may be between 0.3 micrometers (μm) and 0.8 μm into the epitaxial layer. Alternatively, the depth of the trench may be selected based on the desired device characteristics. The general effect on trench depth is that as the spacing between two P-type body regions decreases the depth of the trench increases. The sides of the trench403may be formed with an angle such that a side of the trench intersects with the bottom of the trench at greater than 90 degrees with respect to the surface of the epitaxial layer402. For example and without limitation the angle created by a side of the trench and the surface of the epitaxial layer402at the bottom of the trench may be between 101 and 105 degrees.

FIG.4Cdepicts a side cut away view of formation of the localized JFET implant region409according to aspects of the present disclosure. As shown a localized JFET implant region409may be formed in the epitaxial layer402around the bottom and sides of the trench403. In some implementations, a localized JFET implant region409may be formed by ion implantation410through the pattern mask and hard mask. The localized JFET implant region411may be heavily doped with ions of the first conductivity type. The localized JFET implant region may be doped at an ion concentration that is 2 to 3 times that of the epitaxial layer. The localized JFET implant region may reduce the depletion charge carriers and therefore aid in reducing the RDSof the device.

FIG.4Dshows a cut away view of formation of a thick bottom insulating layer411at the bottom of the trench403according to aspects of the present disclosure. The thick bottom insulating layer411may be formed by deposition techniques such as high density plasma (HDP) deposition or chemical vapor deposition techniques (CVD). The thick bottom insulating layer may be comprised of silicon oxide or nitride or ONO (SiO2/nitride/SiO2) film. A plasma dry etch or wet etch is then applied to the side walls of the trench403to remove any excess insulating layer deposited on the sides of the trench. The thick bottom insulating layer is initially formed with a thickness of between 1500 and 2500 angstroms (Å). In some embodiments the final thickness of thick bottom insulating layer is 1.5 to 2 times the thickness of the insulating layer of the sidewall of the trench, this final thickness is achieved after insulating layer has been formed on the sides and bottom of the trench as seen inFIG.4E.

FIG.4Eshows a cut away side view of formation of a gate insulating layer having a planar portion412and a trench portion413according to aspects of the present disclosure. As shown an insulating layer is deposited over the surface of the epitaxial layer402. The planar portion412of the insulating layer on the surface of the epitaxial layer402will form part of the planar portion of the integrated planar-trench gate. Insulating layer material is also deposited on the bottom and sidewalls413of the trench403. In implementations, having the thick bottom insulating layer the insulating material is deposited on top of the previously deposited insulating material creating the final thickness of the thick bottom insulating layer411. The insulating layer may be comprised of a silicon oxide. The planar portion412of the insulating layer and the trench portion413on the bottom of the trench403may be about the same thickness, e.g., between 800 and 1000 angstroms thick.

As depicted inFIG.4F, the conductive layer includes a planar portion415on the planar portion412of the insulating layer and a trench portion416. The conductive layer may be deposited on a surface of the insulating layer. The trench portion416of the conductive layer fills portions of the trench413not occupied by portions of the insulating layer including the thick bottom insulator (optional)411and the insulating layer on the side of the trench413. The planar portion415of the conductive layer covers the planar portion412of the insulating layer. The techniques described herein create an extremely flat surface of the conductive layer over both the planar portion and the trench portion of the insulating layer without formation of an intermediate insulating layer between the planar and trench portions.

FIG.4Gdepicts a cut away side view of formation of an integrated planar-trench gate after patterning the conductive layer to form a planar-trench gate having a contiguous planar gate portion415and trench gate portion416according to aspects of the present disclosure. The conductive layer415is masked and etched away leaving the final dimensions of the planar-trench gate. After the mask is removed, the planar gate portion415may then act as a mask for a subsequent etching of the planar portion412of the insulating layer. Preferably, the process that etches the conductive layer is selective to the material of the conductive layer, i.e., etches the material of the insulating layer at a much lower rate than the conductive layer material. Conversely, the process that etches the insulating layer is selective to the material of the insulating layer, i.e., etches the conductive layer at a much lower rate than the insulating layer.

FIG.4Hshows a cut away side view of formation of body regions417for a transistor device having an integrated planar-trench gate according to aspects of the present disclosure. A mask419may be formed on the surface of the epitaxial layer with gaps in the location for the body region417. The mask may be a photo resist mask applied to the surface of the epitaxial layer. Ion implantation418may be used to dope the epitaxial layer402with ions of the second conductivity type (e.g. if the first conductivity type is n-type then the second conductivity type is p-type). After forming the body region417, the mask419may be removed by plasma ashing and washing with a removal solution or any other known mask removal technique for example and without limitation planarization or polishing.

In some implementations, the body regions may be formed before formation of the trench and the integrated planar trench gate. In these implementations, the trench may be formed in body region of the epitaxial layer. The localized JFET implant region may then be formed in the body region via counter ion doping. This implementation of the method may be used to produce the device seen inFIG.2. In yet other implementations, doped columns may be formed under the body region. These doped columns form a super-junction device such as the one shown inFIG.3.

FIG.4Idepicts a cut away side view of formation of source regions for a transistor device having an integrated planar-trench gate according to aspects of the present disclosure. A source mask420may be formed on the surface of the epitaxial layer with gaps at the locations for the source region422. One or more source regions422may be formed in the body region417of the epitaxial layer402via implantation of ions421through openings in the source mask420. The source region(s)422may be doped with ions of the first conductivity type at a concentration greater than the epitaxial layer. After formation of the source region(s)422, the source mask420may be removed by plasma ashing and washing with a removal solution of any other known mask removal technique for example and without limitation planarization or polishing.

FIG.4Jshows a cut away side view of formation of other structures on the integrated planar-trench gate transistor device according to aspects of the present disclosure. An isolation layer424is formed on the surface of the epitaxial layer402after formation of the source region(s)422. The Isolation layer may be for example and without limitation, a silicon oxide deposited on the surface of the epitaxial layer. The Isolation layer may also cover423the integrated gate trench completing the insulation layer for gate. A source contact mask is applied to the isolation layer424over the source region(s)422and body region(s)417of the epitaxial layer. The isolation layer is etched away and a source contact metal426is deposited on the surface of the epitaxial layer402over the source region422and body region417. A gate contact mask is applied to the gate insulation426the gate contact is etched away and a gate contact metal425is deposited on the conductive layer415of the gate. Etching for the gate contact and source contact may be performed by using plasma dry etching, after the etch the gate contact mask and source contact mask may be removed by plasma ashing and washing with a suitable mask removal solution or any other known mask removal technique such as without limitation planarization or polishing. A drain conductive layer427may be formed on the backside of the substrate401. The drain conductive layer427may be for example and without limitation, a metal deposited on the back of the substrate401.