Method for forming planarized interconnect level using selective deposition and ion implantation

On the surface of a semiconductor structure containing portions to be selectively connected to an interconnection pattern, a thin conductive, uniform base layer, which promotes the growth of an interconnect conductor, is desposited. To define the interconnect structure, a thick layer of insulation material is selectively formed on the surface of the base layer with openings in the insulation layer exposing portions of the base layer that are to be connected to the interconnect layer. Next, on the portions of the base layer that are exposed by the openings in the insulation layer, a layer of interconnect metal, such as tungsten or gold, that effectively blocks the implantation of the ions through it, is selectively deposited to fill the openings in the insulation layer upon and even with the top surface of the insulation layer, so that the insulation layer and deposited metal are effectively planarized. The base layer which underlies the planarized insulator/interconnect metal layer is selectively converted to an insulator in those regions beneath the insulator but not beneath the interconnect metal by bombarding the entire structure with suitable conversion causing (e.g. oxygen or nitrogen) ions.

FIELD OF THE INVENTION 
The present invention relates in general to integrated circuits and is 
particularly directed to a methodology for forming a planarized 
metal/insulation interconnection arrangement by employing selective metal 
deposition and ion implantation. 
BACKGROUND OF THE INVENTION 
The continued growth and expansion of microminiaturized circuit 
architectures has involved an increase in complexity and packaging density 
of both the functional circuit elements contained within a semiconductor 
substrate and interconnection arrangements (metal/insulation structures) 
that overlie the surface of the substrate and which serve to interconnect 
components in the substrate to each other and to external electrical 
coupling terminals. Typically, the interconnection layers comprise 
multiple layers of signal coupling tracks that pass over and/or are 
interconnected to each other and/or to components in the underlying 
substrate, effectively creating a three-dimensional tiered or layered 
arrangements of conductors separated by insulator layers. 
Because of the complexity of the integrated circuit layout in the 
semiconductor material of the chip and the resulting often tortuous 
interconnection pattern required, the potential for discontinuities in the 
interconnection pattern is a significant problem that must be minimized 
for achieving sought after yield and performance. In essence, what is 
desired is that each level of interconnect be effectively planar, namely 
without "steps", whereat corners and field gradients in a conductor layer 
give rise to contact/conductor separation (open circuits), punch through, 
etc. 
One approach for achieving a planarized interconnect structure involves the 
use of a planarization overlay that is deposited over an uneven 
metal/insulator structure. The overlay is made of a material which, for a 
prescribed etchant, is etched at approximately the same rate as the 
highest (thickest) of the layers to be planarized. In its deposited 
configuration, the planarization overlay has a substantially flat upper 
surface. As a result, as the etchant attacks the overlay and the higher 
(thicker) material, the surface of the overall structure follows the 
flattened surface contour of the overlay, to thereby obtain a "planarized" 
structure. A drawback to this procedure is the fact that the overlay layer 
adds additional material to the structure, which is not functionally 
necessary for its operation, and requires additional processing steps. 
SUMMARY OF THE INVENTION 
In accordance with the present invention there is provided a new and 
improved methodology for forming a planarized interconnect structure that 
does not require the use of additional layer structure (e.g. the 
flattening layer discussed above) and thereby provides a more efficient 
processing scheme, while, at the same time, providing the sought-after 
packaging density and interconnect isolation for achieving operational 
performance of the overall architecture. 
Pursuant to the present invention, on the surface of a semiconductor 
structure, such as a substrate containing functional elements to be 
selectively connected to an interconnection pattern or on the surface of a 
multi-level structure including substrate and one or more levels of 
interconnect thereover, a thin conductive, uniform (constant thickness) 
base layer, which promotes the growth of an interconnect conductor, is 
deposited. For a single level structure, such a base layer may comprise 
doped polycrystalline silicon which overlies contact areas of a silicon 
substrate, functional circuit element regions in which are to be 
conductively connected to the interconnect structure. To define the 
interconnect structure, a thick layer of insulation material (e.g. silicon 
nitride, silicon oxide, etc.) is formed on the surface of the base layer 
with openings in the insulation layer subsequently formed exposing 
portions of the base layer that are to be connected to the interconnect 
layer and thereby join the interconnect layer to underlying circuit 
element regions. 
Next, on the portions of the base layer that are exposed by the openings in 
the insulation layer, a layer of interconnect metal, such as tungsten or 
gold, that effectively blocks the implantation of ions through it, is 
selectively deposited to fill the openings in the insulation layer and be 
even with the top surface of the insulation layer, whereby the insulation 
layer and deposited metal are effectively planarized. 
The base layer which underlies the planarized insulator/interconnect metal 
layer is selectively converted to an insulator at those regions thereof 
beneath the insulator, but not beneath the interconnect metal, by 
bombarding the entire structure with suitable insulation 
conversion-causing (e.g. oxygen or nitrogen) ions. Because of its ion 
implantation masking properties relative to those of the insulator, the 
interconnect metal effectively blocks the insulation conversion-causing 
ions and prevents the ions from reaching the underlying base layer. In 
those regions of the base layer not covered by the interconnect metal, 
however, the base layer is converted to an insulator, so that that portion 
of the structure underlying the ion implanted base layer is effectively 
insulated from the interconnect metal by a planar insulator layer formed 
of a dual layer structure of a thin ion-converted base layer and the 
overlying thick insulator (oxide) layer.

DETAILED DESCRIPTION 
Referring now to FIGS. 1-5 there are shown diagrammatic cross-sectional 
illustrations of a portion of an integrated circuit architecture to which 
the planarization interconnect methodology of the present invention is 
applied. In the embodiment described, the underlying semiconductor 
structure upon which the planarized interconnect arrangement is formed is 
shown as a substrate containing one or more functional element regions. It 
should be understood however, that the invention is applicable to any 
level of semiconductor architecture, including multi-level configurations. 
Moreover, while the present description relates to the formation of a 
single planarized level, it is to be appreciated that the interconnect 
planarization methodology of the invention is applicable to multiple 
levels of a semiconductor structure. FIG. 1 shows a planar silicon 
substrate 11 having a substantially planar surface 12 in which are formed 
respective active element regions 13 and 14. The details of the substrate 
and the functional circuit element regions disposed therein are not 
necessary for an understanding of the present invention and, accordingly, 
will not be detailed here. Rather, the description to follow will focus 
upon the interconnect scheme through which various regions in the 
substrate are interconnected to one another and to external connector 
terminals by the medium of the selectively formed and planarized 
interconnect structure. 
In accordance with the present invention, an initial thin conductive base 
layer, such as aluminum or doped polysilicon, is formed on the surface 12 
of the substrate 11. This thin layer is shown in FIG. 1 as a polysilicon 
layer 15 doped with an impurity such as arsenic, phosphorus or boron and 
having an impurity concentration on the order of 10.sup.19 -10.sup.20 
cm.sup.-3 and a thickness on the order of 500 .ANG.. Where aluminum is 
used as the base layer, its thickness may be on the order of 5000 .ANG.. 
What is important is that the properties of the base layer are such that 
they promote the growth of a metallization layer to be selectively formed, 
as will be described below. 
Next, as shown in FIG. 2, a relatively thick (on the order of 5000 .ANG.) 
insulation layer 21, such as silicon oxide, is formed atop the doped 
polysilicon base layer 15. The thickness of the insulator layer 21 is 
chosen in accordance with the desired thickness of the ultimate 
interconnected pattern as well as the implant dosage of ions to be 
introduced into the base layer 15. For purposes of the present example, 
wherein doped polysilicon having a thickness on the order of 500 .ANG. is 
formed as the base layer, insulator layer 21 may comprise a layer of 
silicon oxide or silicon nitride having a thickness in the range given 
above. A metallization mask photoresist layer is formed atop the insulator 
layer 21 and openings 23 and 24 are then etched in the insulator layer to 
expose portions of the doped polysilicon layer therebeneath. 
Next, as shown in FIG. 3, an interconnect metallization layer, such as 
tungsten or gold, is formed in the openings 23 and 24 of the insulator 
layer 21. Where tungsten is formed, it may be formed by the selective 
deposition of tungsten such as by the reduction of tunsten hexafluoride 
(WF.sub.6) in a reduced pressure atmosphere. Where gold is formed in the 
openings 23 and 24, it may be formed by a standard gold electroplate or 
electroless process. In either event, the metallization layer is formed 
until it reaches the top surface 25 of the dielectric insulator layer 21. 
This effectively results in an overall planarized interconnect 
metal/insulator layer formed atop the doped polysilicon layer 15, as shown 
in FIG. 3. At this point in the process, each of the interconnect 
metallization layers 33 and 34 are effectively connected to each other and 
to all of the regions in the substrate beneath the polysilicon layer by 
virtue of their common conductive path through the doped polysilicon base 
layer 15. 
In accordance with the present invention, selected portions of the 
underlying polysilicon layer are converted into insulator material by 
implanting ions, such as oxygen or nitrogen ions, through the 
metallization/insulator structure lying atop of the doped polysilicon, 
whereby those portions of the polysilicon base layer 15 beneath the 
insulator 21 are converted into silicon dioxide or silicon nitride, and 
thereby form an effectively continuous insulator layer extending from the 
upper top surface 12 of the semiconductor substrate 11 to the top surface 
25 of the insualtor layer 21. (For a detailed description of the 
implantation of oxygen, nitrogen ions into semiconductive material to 
convert the material to an insulator, attention may be directed to the 
following U.S. patent literation: U.S. Pat. Nos. 3,622,382 and 3,666,548 
to Brack et al; U.S. Pat. No. 3,897,274 to Stehlin et al; U.S. Pat. No. 
4,084,986 to Aoki et al; U.S. Pat. No. 4,105,805 to Glendinning et al; 
U.S. Pat. No. 4,406,051 to Iizuka; and U.S. Pat. No. 4,479,297 To Mizutani 
et al.) 
The ion implantation insulation conversion is effectively shown in FIGS. 4 
and 5 wherein an ion implant beam 41 is directed through the dual 
metallization/ insulator structure lying atop the doped polysilicon layer 
15. Because of the differential ion implantation blockage characteristics 
of the metallization layer 33, 34 and the dielectric layer 21, the peak 
depth of the ion implanation doping profile effectively lies in the middle 
of the doped polysilicon base layer 15 in those portions of layers 15 
beneath the dielectric layer 21, as shown by the broken lines R.sub.PD in 
FIG. 4, and also occurs at a very shallow level R.sub.PM in the 
metallization layers 33 and 34. In effect, the metallization layers 33 and 
34 block the oxygen, nitrogen ions and prevent them from entering the 
polysilicon base layer directly beneath the metallization layers 33 and 
34. On the other hand, because the dielectric layer 21 does not 
effectively impede the introduction of the nitrogen, oxygen ions into the 
polysilicon layer 15 therebeneath, the doped polysilicon becomes 
effectively amorphous. Next, the structure is exposed to a low temperature 
reaction bake or heat treatment, so that those portions of the doped 
polysilicon base layer that had been rendered amorphous by the 
introduction of the ion implanted nitrogen, oxygen ions become 
SiO.sub.x(x.ltoreq.2), where oxygen is doped, and become Si.sub.3 
N.sub.y(y.ltoreq.4) where nitrogen is doped. 
For the materials and range of thicknesses of the metallization layer, 
polysilicon layer, and dielectric layer thereon described above, nitrogen 
and/or oxygen ions may be implanted at an energy on the order of 360 KeV 
with a dose on the order of 10.sup.18 ions/cm.sup.2. Where aluminum is 
employed as the base layer 15, having a thickness on the order of 500 
.ANG., to provide R.sub.PM at a distance of 3700 .ANG. from the top 
surface of the aluminum, the implant energy of the nitrogen/oxygen ions 
must be on the order of 360 KeV. 
As will be appreciated from the foregoing description of the methodology of 
the present invention, by taking advantage of the fact that 
oxygen/nitrogen ions can be employed to convert a layer of conductive 
material (e.g. doped polysilicon, aluminum) into an insulator, and using 
the differential implantation inhibiting properties of an interconnect 
metal such as tungsten or gold as compared with that of a dielectric 
layer, a very simplified planarization technique for forming a planarized 
metal/insulator interconnect layer can be achieved. 
While I have shown and described an embodiment in accordance with the 
present invention, it is understood that the same is not limited thereto 
but is susceptible of numerous changes and modifications as known to a 
person skilled in the art, and I therefore do not wish to be limited to 
the details shown and described herein but intend to cover all such 
changes and modifications as are obvious to one of ordinary skill in the 
art.