Memory device with a charge transfer device

Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense a state of the memory cell, a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, one or more of the plurality of sense components may sense the charge with one of a variety of sensing schemes. Based on the charge being transferred using the charge transfer device and each sense component sensing the charge, a logic state associated with the memory cell may be determined. The number of sensed states may be correlated to the number of sense amplifiers. The ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than one.

BACKGROUND

The following relates generally to a system that includes at least one memory device and more specifically to sensing techniques using a charge transfer device.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices most often store one of two states, often denoted by a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read, or sense, at least one stored state in the memory device. To store information, a component of the device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Some memory cells may be configured to store multiple states. Determining correlations between components associated with sensing and writing a memory cell may be desirable to more accurately and expeditiously determine the number of components that may be used based on characteristics of the memory cell or the number of states that may be stored based on the number of components that may be associated with the memory cell, generally.

DETAILED DESCRIPTION

A memory cell capable of storing three or more states (e.g., a multi-level memory cell) may be read (e.g., sensed) using a charge transfer device. As such, a single multi-level memory cell may be configured to store more than one bit of digital data. To sense a multi-level memory cell, a charge transfer device may be used to improve the window in which the memory cell is sensed. For example, the charge transfer device may augment differences between charges stored on a memory cell to more-accurately sense the particular logic state stored on the memory cell. Thus, based on the particular logic state stored to the memory cell, the charge transfer device may couple a digit line associated with the memory cell to one or more sense components during a read operation.

Techniques are provided for sensing a memory cell configured to store multiple states (e.g., three or more states) using a number of sense components or a number of reference voltages. A ratio between the number of logic states read by the sense components and the number of sense components of a memory device may be determined. In such examples, the ratio of the number of states read by the plurality of sense components and the number of sense components may be greater than one. Different configurations of memory devices may have different ratios of sense components to states of a memory cell or different ratios of reference voltages to states of a memory cell. For example, two sense components may be used to detect a state stored in a memory cell configured to store three states. In other examples, three sense components may be used to detect a state stored in a memory cell configured to store four states. In other examples, a single fixed reference voltage may be used to detect a state stored in a memory cell that is configured to store three states or four states. Determining the logic state of the memory cell may be based on the sense operations conducted by each of the three sense components using the reference voltages.

Features of the disclosure are initially described in the context of a memory system. Features of the disclosure are described in the context of a memory die, a memory circuit, and timing diagrams that support sensing techniques using a charge transfer device in accordance with aspects of the present disclosure. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to sensing techniques using a charge transfer device.

FIG. 1illustrates an example of a system100that utilizes one or more memory devices in accordance with aspects disclosed herein. The system100may include an external memory controller105, a memory device110, and a plurality of channels115coupling the external memory controller105with the memory device110. The system100may include one or more memory devices, but for ease of description the one or more memory devices may be described as a single memory device110.

The system100may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. The system100may be an example of a portable electronic device. The system100may be an example of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, or the like. The memory device110may be component of the system configured to store data for one or more other components of the system100. In some examples, the system100is configured for bi-directional wireless communication with other systems or devices using a base station or access point. In some examples, the system100is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

At least portions of the system100may be examples of a host device. Such a host device may be an example of a device that uses memory to execute processes such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, some other stationary or portable electronic device, or the like. In some cases, the host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller105. In some cases, the external memory controller105may be referred to as a host or host device.

In some cases, a memory device110may be an independent device or component that is configured to be in communication with other components of the system100and provide physical memory addresses/space to potentially be used or referenced by the system100. In some examples, a memory device110may be configurable to work with at least one or a plurality of different types of systems100. Signaling between the components of the system100and the memory device110may be operable to support modulation schemes to modulate the signals, different pin designs for communicating the signals, distinct packaging of the system100and the memory device110, clock signaling and synchronization between the system100and the memory device110, timing conventions, and/or other factors.

The memory device110may be configured to store data for the components of the system100. In some cases, the memory device110may act as a slave-type device to the system100(e.g., responding to and executing commands provided by the system100through the external memory controller105). Such commands may include an access command for an access operation, such as a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands. The memory device110may include two or more memory dice160(e.g., memory chips), which may be referred to, for example, memory die160-a, memory die160-b, and so forth, to memory die160-N, to support a desired or specified capacity for data storage. The memory device110including two or more memory dice may be referred to as a multi-die memory or package (also referred to as multi-chip memory or package).

The system100may further include a processor120, a basic input/output system (BIOS) component125, one or more peripheral components130, and an input/output (I/O) controller135. The components of system100may be in electronic communication with one another using a bus140.

The processor120may be configured to control at least portions of the system100. The processor120may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, the processor120may be an example of a central processing unit (CPU), a graphics processing unit (GPU), or a system on a chip (SoC), among other examples.

The BIOS component125may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system100. The BIOS component125may also manage data flow between the processor120and the various components of the system100, e.g., the peripheral components130, the I/O controller135, etc. The BIOS component125may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

The peripheral component(s)130may be any input device or output device, or an interface for such devices, that may be integrated into or with the system100. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots. The peripheral component(s)130may be other components understood by those skilled in the art as peripherals.

The I/O controller135may manage data communication between the processor120and the peripheral component(s)130, input devices145, or output devices150. The I/O controller135may manage peripherals that are not integrated into or with the system100. In some cases, the I/O controller135may represent a physical connection or port to external peripheral components.

The input145may represent a device or signal external to the system100that provides information, signals, or data to the system100or its components. This may include a user interface or interface with or between other devices. In some cases, the input145may be a peripheral that interfaces with system100via one or more peripheral components130or may be managed by the I/O controller135.

The output150may represent a device or signal external to the system100configured to receive an output from the system100or any of its components. Examples of the output150may include a display, audio speakers, a printing device, or another processor on printed circuit board, and so forth. In some cases, the output150may be a peripheral that interfaces with the system100via one or more peripheral components130or may be managed by the I/O controller135.

The components of system100may be made up of general-purpose or special purpose circuitry designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, in any combination thereof, configured to carry out the functions described herein. In some examples, memory device110may be coupled with multiple sense components. Each memory cell, for example, may be coupled with the sense components via a digit line coupled with a charge transfer device, for example, a transistor. The gate of the charge transfer device may be coupled with a compensation device, which for example, also may be another transistor, and a capacitor configured to compensate for the threshold voltage associated with the charge transfer device. In some examples, the charge transfer device may be configured to transfer a charge between the digit line and the sense component based on a memory cell being discharged onto the digit line. Subsequently, each sense component may sense a respective charge using a fixed reference voltage, multiple reference voltages, at a same time, at different times, or a combination thereof.

The memory device110may include a device memory controller155and one or more memory dice160. Each memory die160may include a local memory controller165(e.g., local memory controller165-a, local memory controller165-b, and/or local memory controller165-N) and a memory array170(e.g., memory array170-a, memory array170-b, and/or memory array170-N). A memory array170may be a collection (e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data. Features of memory arrays170and/or memory cells are described in more detail with reference to at leastFIG. 2. As described above, the memory device110may be coupled with multiple sense components. For example, each memory cell (e.g., of a respective memory array and within a memory die) may be coupled with the sense components via the digit line and the charge transfer device (e.g., a transistor). In some examples, the gate of each charge transfer device may be coupled with a compensation device (e.g., another transistor) and a capacitor configured to compensate for the threshold voltage associated with the charge transfer device.

The memory device110may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die160. A 3D memory device may include two or more memory dice160(e.g., memory die160-a, memory die160-b, and/or any number of memory dice160-N). In a 3D memory device, a plurality of memory dice160-N may be stacked on top of one another. In some cases, memory dice160-N in a 3D memory device may be referred to as decks, levels, layers, or dies. A 3D memory device may include any quantity of stacked memory dice160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high, and so forth). This may increase the number of memory cells that may be positioned on a substrate as compared with a single 2D memory device, which in turn may reduce production costs or increase the performance of the memory array, or both. In some 3D memory device, different decks may share at least one common access line such that some decks may share at least one of a word line, a digit line, and/or a plate line.

The device memory controller155may include circuits or components configured to control operation of the memory device110. As such, the device memory controller155may include the hardware, firmware, and software that enables the memory device110to perform commands and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device110. The device memory controller155may be configured to communicate with the external memory controller105, the one or more memory dice160, or the processor120. In some cases, the memory device110may receive data and/or commands from the external memory controller105. For example, the memory device110may receive a write command indicating that the memory device110is to store certain data on behalf of a component of the system100(e.g., the processor120) or a read command indicating that the memory device110is to provide certain data stored in a memory die160to a component of the system100, for example, the processor120.

In some cases, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160. Examples of the components included in the device memory controller155and/or the local memory controllers165may include receivers for demodulating signals received from the external memory controller105, decoders for modulating and transmitting signals to the external memory controller105, logic, decoders, amplifiers, filters, or the like. In some examples, the device memory controller155may be configured to control the operations of a memory array as it relates to a read operation using a charge transfer device. For example each memory cell of memory array170-amay be coupled with a node of at least a first sense component and a second sense component via a respective digit line. In some examples, the digit line may be coupled with a charge transfer device configured to transfer a charge between the digit line and the node based on a memory cell being discharged onto the digit line. In further examples, the states stored by each memory cell may be correlated to a number of sense amplifiers or reference voltages as described herein.

In some examples, the memory cell may be sensed by the local memory controller165transferring, using a charge transfer device, a charge between the digit line and the node. In some examples, the first sense component may sense a signal on the node at a first time based at least in part on transferring the charge between the digit line and the node. Additionally or alternatively, the second sense component may sense the signal on the node at a second time different than the first time based at least in part on transferring the charge between the digit line and the node. The local memory controller165may determine a logic state of the memory cell based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component. In some examples, each of the sense components may sense the respective signal using a fixed reference voltage or by using a different reference voltage. In further examples, a correlation may exist between the number of states of the memory cell and the number of sense amplifiers or reference voltages used by the memory device to read the memory cell.

In other examples, the memory cell may be sensed by the local memory controller165transferring a charge between the digit line and the node. The first sense component may sense a signal on the node at a time using a first reference value based at least in part on transferring the charge between the digit line and the node. Additionally or alternatively, the second sense component may sense the signal on the node at the time using a second reference value based at least in part on transferring the charge between the digit line and the node. The local memory controller165may then determine a logic state of the multi-level memory cell based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component. In some examples, each of the sense components may sense the respective signal using a fixed reference voltage or by using a different reference voltage. Additionally or alternatively, in the examples described above, the local memory controller165may implement at least a third sense component to determine the logic state of the memory cell.

The local memory controller165(e.g., local to a memory die160) may be configured to control operations of the memory die160. Also, the local memory controller165may be configured to communicate (e.g., receive and transmit data and/or commands) with the device memory controller155. The local memory controller165may support the device memory controller155to control operation of the memory device110as described herein. In some cases, the memory device110does not include the device memory controller155, and the local memory controller165or the external memory controller105may perform the various functions described herein. As such, the local memory controller165may be configured to communicate with the device memory controller155, with other local memory controllers165, or directly with the external memory controller105or the processor120.

The external memory controller105may be configured to enable communication of information, data, and/or commands between components of the system100(e.g., the processor120) and the memory device110. The external memory controller105may act as a liaison between the components of the system100and the memory device110so that the components of the system100may not need to know the operation details of the memory device. The components of the system100may present requests to the external memory controller105for example, read commands or write commands, that the external memory controller105satisfies. The external memory controller105may convert or translate communications exchanged between the components of the system100and the memory device110. In some cases, the external memory controller105may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller105may include a common data clock that generates a common (source) data clock signal.

In some cases, the external memory controller105or other component of the system100, or its functions described herein, may be implemented by the processor120. For example, the external memory controller105may be hardware, firmware, or software, or some combination thereof implemented by the processor120or other component of the system100. While the external memory controller105is depicted as being external to the memory device110, in some cases, the external memory controller105, or its functions described herein, may be implemented by a memory device110. For example, the external memory controller105may be hardware, firmware, or software, or some combination thereof implemented by the device memory controller155or one or more local memory controllers165. In some cases, the external memory controller105may be distributed across the processor120and the memory device110such that portions of the external memory controller105are implemented by the processor120and other portions are implemented by a device memory controller155or a local memory controller165. Likewise, in some cases, one or more functions ascribed herein to the device memory controller155or local memory controller165may in some cases be performed by the external memory controller105(either separate from or as included in the processor120).

The components of the system100may exchange information with the memory device110using a plurality of channels115. In some examples, the channels115may enable communications between the external memory controller105and the memory device110. Each channel115may include one or more signal paths or transmission mediums (e.g., conductors) between terminals associated with the components of system100. For example, a channel115may include a first terminal including one or more pins or pads at external memory controller105and one or more pins or pads at the memory device110. A pin may be an example of a conductive input or output point of a device of the system100, and a pin may be configured to act as part of a channel. In some cases, a pin or pad of a terminal may be part of to a signal path of the channel115. Additional signal paths may be coupled with a terminal of a channel for routing signals within a component of the system100. For example, the memory device110may include signal paths (e.g., signal paths internal to the memory device110or its components, such as internal to a memory die160) that route a signal from a terminal of a channel115to the various components of the memory device110(e.g., a device memory controller155, memory dice160, local memory controllers165, memory arrays170).

Channels115(and associated signal paths and terminals) may be dedicated to communicating specific types of information. In some cases, a channel115may be an aggregated channel and thus may include multiple individual channels. For example, a data channel190may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and so forth.

In some cases, the channels115may include one or more command and address (CA) channels186. The CA channels186may be configured to communicate commands between the external memory controller105and the memory device110including control information associated with the commands (e.g., address information). For example, the CA channel186may include a read command with an address of the desired data. In some cases, the CA channels186may be registered on a rising clock signal edge and/or a falling clock signal edge. In some cases, a CA channel186may include eight or nine signal paths.

In some cases, the channels115may include one or more clock signal (CK) channels188. The CK channels188may be configured to communicate one or more common clock signals between the external memory controller105and the memory device110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller105and the memory device110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal paths of the CK channels188may be configured accordingly. In some cases, the clock signal may be single ended. In some cases, the clock signal may be a 1.5 GHz signal. A CK channel188may include any number of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations for the memory device110, or other system-wide operations for the memory device110. The clock signal CK may therefore may be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, or the like).

In some cases, the channels115may include one or more data (DQ) channels190. The data channels190may be configured to communicate data and/or control information between the external memory controller105and the memory device110. For example, the data channels190may communicate information (e.g., bi-directional) to be written to the memory device110or information read from the memory device110. The data channels190may communicate signals that may be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

In some cases, the channels115may include one or more other channels192that may be dedicated to other purposes. These other channels192may include any number of signal paths.

In some cases, the other channels192may include one or more write clock signal (WCK) channels. While the ‘W’ in WCK may nominally stand for “write,” a write clock signal WCK (e.g., a WCK_t signal and a WCK_c signal) may provide a timing reference for access operations generally for the memory device110(e.g., a timing reference for both read and write operations). Accordingly, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channels may be configured to communicate a common data clock signal between the external memory controller105and the memory device110. The data clock signal may be configured to coordinate an access operation (e.g., a write operation or read operation) of the external memory controller105and the memory device110. In some cases, the write clock signal may be a differential output (e.g., a WCK_t signal and a WCK_c signal) and the signal paths of the WCK channels may be configured accordingly. A WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, or the like).

In some cases, the other channels192may include one or more error detection code (EDC) channels. The EDC channels may be configured to communicate error detection signals, such as checksums, to improve system reliability. An EDC channel may include any number of signal paths.

The channels115may couple the external memory controller105with the memory device110using a variety of different architectures. Examples of the various architectures may include a bus, a point-to-point connection, a crossbar, a high-density interposer such as a silicon interposer, or channels formed in an organic substrate or some combination thereof. For example, in some cases, the signal paths may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

Signals communicated over the channels115may be modulated using a variety of different modulation schemes. In some cases, a binary-symbol (or binary-level) modulation scheme may be used to modulate signals communicated between the external memory controller105and the memory device110. A binary-symbol modulation scheme may be an example of a M-ary modulation scheme where M is equal to two. Each symbol of a binary-symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary-symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) having two symbols (e.g., PAM2), and/or others.

In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller105and the memory device110. A multi-symbol modulation scheme may be an example of a M-ary modulation scheme where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logic 00, a logic 01, a logic 10, or a logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and/or others. A multi-symbol signal or a PAM4 signal may be a signal that is modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols. As indicated herein and described with reference toFIGS. 3 through 5, the sensing scheme described may be performed with respect to multi-level memory cells. Moreover, the number of sensed states may be correlated to the number of sense amplifiers. In one example, the ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than 1.

FIG. 2illustrates an example of a memory die200in accordance with various examples of the present disclosure. The memory die200may be an example of the memory dice160described with reference toFIG. 1. In some cases, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that are programmable to store different logic states. Each memory cell205may be programmable to store two or more states. For example, the memory cell205may be configured to store one bit of digital logic at a time (e.g., a logic 0 and a logic 1). In some cases, a single memory cell205(e.g., a multi-level memory cell) may be configured to store more than one bit of digit logic at a time (e.g., a logic 00, logic 01, logic 10, or a logic 11).

A memory cell205may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In some examples, the digit line may be coupled with a charge transfer device configured to transfer charge between the digit line and the node of the sense component during a read operation. The charge transfer device may be implemented in order to improve sensing capabilities of memory cell205(e.g., of a multi-level memory cell configured to store three or more logic states). In some examples, the charge transfer device may be coupled with a node of at least a first sense component and a second sense component. A charge representable of the programmable states may be transferred to the node—via the charge transfer device—and may be sensed by at least one of the first sense component or the second sense component. The charge may represent, for example, one of four logic states stored to the memory cell205(e.g., logic “00”, logic “01”, logic “10”, or logic “11”). In some examples, if memory cell205is configured to store four logic states, three sense components may be implemented.

Operations such as reading and writing may be performed on memory cells205by activating or selecting access lines such as a word line210and/or a digit line215. In some cases, digit lines215may also be referred to as bit lines. References to access lines, word lines and digit lines, or their analogues, are interchangeable without loss of understanding or operation. Activating or selecting a word line210or a digit line215may include applying a voltage to the respective line.

The memory die200may include the access lines (e.g., the word lines210and the digit lines215) arranged in a grid-like pattern. Memory cells205may be positioned at intersections of the word lines210and the digit lines215. By biasing a word line210and a digit line215(e.g., applying a voltage to the word line210or the digit line215), a single memory cell205may be accessed at their intersection.

Accessing the memory cells205may be controlled through a row decoder220, a column decoder225. For example, a row decoder220may receive a row address from the local memory controller260and activate a word line210based on the received row address. A column decoder225may receive a column address from the local memory controller260and may activate a digit line215based on the received column address. For example, the memory die200may include multiple word lines210, labeled WL_1through WL_M, and multiple digit lines215, labeled DL_1through DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line210and a digit line215, e.g., WL_1and DL_3, the memory cell205at their intersection may be accessed. The intersection of a word line210and a digit line215, in either a two-dimensional or three-dimensional configuration, may be referred to as an address of a memory cell205.

The memory cell205may include a logic storage component, such as capacitor230and a switching component235. The capacitor230may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of the capacitor230may be coupled with the switching component235and a second node of the capacitor230may be coupled with a voltage source240. In some cases, the voltage source240is the cell plate reference voltage, such as Vpl. In some cases, the voltage source240may be an example of a plate line coupled with a plate line driver. The switching component235may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components. In some examples, memory cell205may be referred to as a multi-level memory cell. Stated another way, memory cell205may be configured to store three or more states (e.g., three or more logic states).

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component235. The capacitor230may be in electronic communication with the digit line215using the switching component235. For example, the capacitor230may be isolated from digit line215when the switching component235is deactivated, and the capacitor230may be coupled with digit line215when the switching component235is activated. In some cases, the switching component235is a transistor and its operation may be controlled by applying a voltage to the transistor gate, where the voltage differential between the transistor gate and transistor source may be greater or less than a threshold voltage of the transistor. In some cases, the switching component235may be a p-type transistor or an n-type transistor. The word line210may be in electronic communication with the gate of the switching component235and may activate/deactivate the switching component235based on a voltage being applied to word line210.

A word line210may be a conductive line in electronic communication with a memory cell205that is used to perform access operations on the memory cell205. In some architectures, the word line210may be in electronic communication with a gate of a switching component235of a memory cell205and may be configured to control the switching component235of the memory cell. In some architectures, the word line210may be in electronic communication with a node of the capacitor of the memory cell205and the memory cell205may not include a switching component.

A digit line215may be a conductive line that connects the memory cell205with a sense component245. In some architectures, the memory cell205may be selectively coupled with the digit line215during portions of an access operation. For example, the word line210and the switching component235of the memory cell205may be configured to couple and/or isolate the capacitor230of the memory cell205and the digit line215. In some architectures, the memory cell205may be in electronic communication (e.g., constant) with the digit line215.

As described above, the digit line215may be coupled with a charge transfer device (e.g., a transistor), which may be coupled with multiple sense components. In some examples, the digit line215may be configured to receive a charge from (e.g., to be biased by) memory cell205. Stated another way, memory cell205may be discharged onto digit line215, which may bias the digit line to a particular voltage. The voltage of the digit line may thus be representative of or related to a logic state stored to memory cell205. For example, if memory cell205were to store a logic “0” and be discharged onto digit line215, the digit line may be biased to a different voltage than if memory cell205were to store a logic “1” and be discharged onto digit line215. In some examples, the charge transfer device may transfer the voltage discharged onto the digit line215to each of the sense components, which may determine a logic state of the memory cell205.

The sense component245may be configured to detect a state (e.g., a charge) stored on the capacitor230of the memory cell205and determine a logic state of the memory cell205based on the stored state. The charge stored by a memory cell205may be extremely small, in some cases. As such, the sense component245may include one or more sense amplifiers to amplify the signal output by the memory cell205. The sense amplifiers may detect small changes in the charge of a digit line215during a read operation and may produce signals corresponding to a logic state 0 or a logic state 1 based on the detected charge.

During a read operation, the capacitor230of memory cell205may output a signal (e.g., discharge a charge) to its corresponding digit line215. The signal may cause a voltage of the digit line215to change. The sense component245may be configured to compare the signal received from the memory cell205across the digit line215to a reference signal250(e.g., reference voltage). The sense component245may determine the stored state of the memory cell205based on the comparison. For example, in binary-signaling, if digit line215has a higher voltage than the reference signal250, the sense component245may determine that the stored state of memory cell205is a logic 1 and, if the digit line215has a lower voltage than the reference signal250, the sense component245may determine that the stored state of the memory cell205is a logic 0. The sense component245may include various transistors or amplifiers to detect and amplify a difference in the signals. The detected logic state of memory cell205may be output through column decoder225as output255. In some cases, the sense component245may be part of another component (e.g., a column decoder225, row decoder220). In some cases, the sense component245may be in electronic communication with the row decoder220or the column decoder225. In some examples, multiple sense components may be coupled with memory cell205, and each memory cell may be configured to sense a voltage of a node coupled thereto.

As described above, memory cell205may be discharged onto digit line215and, in some examples, the charge transfer device may transfer the resulting charge to the node. Accordingly, the node may discharge at a rate that is related to an amount of charge that was transferred. The sense components may sense the voltage of the node, described below with reference toFIGS. 3 through 5, in order to determine the logic state of the memory cell. For example, each sense component may be configured to sense a voltage (e.g., a signal) on the node using a fixed reference voltage, different reference voltages, at a same time, at different times, or a combination thereof. In some examples, a number of sense components implemented may be related to a number of logic states the memory cell205is configured to store. For example, if memory cell205is configured to store three logic states, two sense components may be implemented. In some examples, a charge transfer device may improve a quality of the signal (e.g., of the charge) transferred to the node coupled with the sense components. For example, the signal transferred to the sense components may be amplified such that the difference between a reference voltage and the signal is more profound, resulting in an improved sensing operation. Stated another way, this may result in the sense components more-accurately sensing the logic state of the memory cell205. In some examples, the sense component245may operate with greater accuracy particularly as it relates to multi-level memory cells.

The local memory controller260may control the operation of memory cells205through the various components (e.g., row decoder220, column decoder225, and sense component245). The local memory controller260may be an example of the local memory controller165described with reference toFIG. 1. In some cases, one or more of the row decoder220, column decoder225, and sense component245may be co-located with the local memory controller260. The local memory controller260may be configured to receive commands and/or data from an external memory controller105(or a device memory controller155described with reference toFIG. 1), translate the commands and/or data into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to the external memory controller105(or the device memory controller155) in response to performing the one or more operations. The local memory controller260may generate row and column address signals to activate the target word line210and the target digit line215. The local memory controller260may also generate and control various voltages or currents used during the operation of the memory die200. In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die200.

As described above with reference toFIG. 1, the local memory controller260may cause a charge to be transferred between the digit line215and a node coupled with a first sense component and a second sense component. In some examples, the first sense component may sense a signal on the node at a first time based at least in part on transferring the charge between the digit line215and the node. Additionally or alternatively, the second sense component may sense the signal on the node at a second time different than the first time based at least in part on transferring the charge between the digit line215and the node. The local memory controller260may then determine a logic state of the memory cell based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component. In some examples, each of the sense components may sense the respective signal using a fixed reference voltage or by using a different reference voltage.

In other examples, the memory cell205may be sensed by the local memory controller260causing a charge to be transferred between the digit line215and the node. The first sense component may sense a signal on the node at a time using a first reference value based at least in part on transferring the charge between the digit line215and the node.

Additionally or alternatively, the second sense component may sense the signal on the node at the time using a second reference value based at least in part on transferring the charge between the digit line215and the node. The local memory controller260may then determine a logic state of the multi-level memory cell based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component. In some examples, each of the sense components may sense the respective signal using a fixed reference voltage or by using a different reference voltage. Additionally or alternatively, in the examples described above, the local memory controller260may implement at least a third sense component to determine the logic state of the memory cell205.

In some cases, the local memory controller260may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells205of the memory die200. During a write operation, a memory cell205of the memory die200may be programmed to store a desired logic state. In some cases, a plurality of memory cells205may be programmed during a single write operation. The local memory controller260may identify a target memory cell205on which to perform the write operation. The local memory controller260may identify a target word line210and a target digit line215in electronic communication with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215), to access the target memory cell205. The local memory controller260may apply a specific signal (e.g., voltage) to the digit line215during the write operation to store a specific state (e.g., charge) in the capacitor230of the memory cell205, the specific state (e.g., charge) may be indicative of a desired logic state.

In some cases, the local memory controller260may be configured to perform a read operation (e.g., a sense operation) on one or more memory cells205of the memory die200. During a read operation, the logic state stored in a memory cell205of the memory die200may be determined. In some cases, a plurality of memory cells205may be sensed during a single read operation. The local memory controller260may identify a target memory cell205on which to perform the read operation. The local memory controller260may identify a target word line210and a target digit line215in electronic communication with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215), to access the target memory cell205. The target memory cell205may transfer a signal to the sense component245in response to biasing the access lines. The sense component245may amplify the signal. The local memory controller260may activate the sense component245(e.g., latch the sense component) and thereby compare the signal received from the memory cell205to the reference signal250.

Based on that comparison, the sense component245may determine a logic state that is stored on the memory cell205. The local memory controller260may communicate the logic state stored on the memory cell205to the external memory controller105(or the device memory controller155) as part of the read operation.

In some memory architectures, accessing the memory cell205may degrade or destroy the logic state stored in a memory cell205. For example, a read operation performed in DRAM architectures may partially or completely discharge the capacitor of the target memory cell. The local memory controller260may perform a re-write operation or a refresh operation to return the memory cell to its original logic state. The local memory controller260may re-write the logic state to the target memory cell after a read operation. In some cases, the re-write operation may be considered part of the read operation. Additionally, activating a single access line, such as a word line210, may disturb the state stored in some memory cells in electronic communication with that access line. Thus, a re-write operation or refresh operation may be performed on one or more memory cells that may not have been accessed.

FIG. 3illustrates an example circuit300that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. In some examples, circuit300may include one or more components described above with reference toFIGS. 1 and 2. For example, circuit300may include a memory cell305, which may be an example of memory cell205as described with reference toFIG. 2; a digit line310, which may be an example of digit line215as described with reference toFIG. 2; and a first sense component340and a second sense component340-a, which each may be examples of sense component245as described with reference toFIG. 2. Circuit300may include an isolation device315, a charge transfer device320, a compensation device325, a capacitor330, a voltage source335, a transistor345, a transistor345-a, a first reference line350carrying a reference voltage, and a second reference line355carrying a reference voltage. In some examples, the circuit300may include a write logic block360, a node365, a node370, a voltage source (e.g., a CT precharge voltage)375, and a voltage source (e.g., DVC2)380. In some examples, the voltage source380, DVC2, may be Vcc/2. In some examples, the memory cell305may include a transistor (e.g., a switching component)385, a capacitor390, and a voltage source395. In some examples, the charge transfer device320, the compensation device325, the isolation device315, may all be referred to as transistors, and the transistor345and transistor345-amay each be referred to as a switching device, for clarifying and explanatory purposes only.

In some examples, memory cell305may be indirectly coupled with node365, which may be coupled with first sense component340and second sense component340-a. For example, memory cell305may be coupled with digit line310, which may be coupled with isolation device315. Additionally or alternatively, isolation device315may be coupled with charge transfer device320, which may be coupled with node365. In some examples, as described above, memory cell305may be discharged onto digit line310. Thus, in some examples, the resulting voltage of the digit line310(e.g., a resulting charge on digit line310) may be transferred to node365by way of isolation device315and charge transfer device320. The transfer may occur, in part, based on whether isolation device315is active (or inactive) and a voltage applied to the gate of charge transfer device320.

The charge transfer device320may be coupled with isolation device315, compensation device325, capacitor330, and node365. The charge transfer device320may be, in some examples, a transistor. Accordingly, a gate of the charge transfer device320may be coupled with the compensation device325and the capacitor330, a source of the charge transfer device320may be coupled with isolation device315(e.g., which is coupled with memory cell305), and a drain of the charge transfer device320may be coupled with node365. The charge transfer device320may be configured to transfer a charge (e.g., a charge received at its source) based on a voltage of the digit line310being less than a voltage of the gate of the charge transfer device320. Stated another way, a voltage may be applied to the gate of charge transfer device320to activate the charge transfer device320based on a voltage applied to the source of the charge transfer device320. With the charge transfer device320being activated, the device may transfer a charge to the node365to be sensed by first sense component340and/or second sense component340-a.

A read operation performed by the circuit300may be divided into different phases. A precharge phase may be used to precharge the node365(e.g., CT precharge voltage) and/or the digit line (e.g., DVC2) to their respective precharge voltages. A compensation phase may be used to set a gate voltage for the gate of the charge transfer device320. A cell dump phase may be used to dump the state (e.g., the charge) of the memory cell305onto the digit line310. In some examples, the compensation phase and the cell dump phase may be performed serially. In some examples, the compensation phase and the cell dump phase may be performed, at least in part, concurrently. After the compensation phase, the compensation device325may be deactivated thereby causing the gate of the charge transfer device320to float. After the compensation device325is deactivated, the node365may be precharged a second time before a sense phase of the read operation begins. With the gate voltage of the charge transfer device320set and the memory cell305having dumped its charge onto the digit line310, the sense phase may begin. To begin the sense phase, the isolation device315may be activated, thereby coupling the digit line310with the charge transfer device320. The charge transfer device320may transfer a charge between the digit line310and the node365based on the state of the memory cell305and/or the gate voltage applied to the gate of the charge transfer device320. The sense components340and340-amay be configured to sense a signal on the node365after the charge is transferred. The state of the memory cell305may be determined based on the signal sensed at the node365.

The read operation relies on the charge transfer device320to transfer varying amounts of charge between digit line and the node365based on the state stored on the memory cell305. In order to transfer a charge to or from the node365, a gate of the charge transfer device320may be biased to a first voltage. The first voltage may be equivalent to or may be based in part on a voltage of the digit line310and the threshold voltage of the charge transfer device320. In some cases, the first voltage may be equal to the precharge voltage of the digit line310and a threshold voltage of the charge transfer device320. In some examples, the gate of the charge transfer device320may be biased to a first voltage based on a voltage being applied to node365from voltage source375. A memory device may include multiple charge transfer devices (e.g., for multiple digit lines). Because each charge transfer device may have a unique threshold voltage, having at least one compensation device325for each charge transfer device may allow for the gate voltage applied to the charge transfer device320to account for the unique threshold voltage. Using this, a memory device may increase the uniformity of the read operation across the memory device even though threshold voltages may vary. In some cases, capacitor330may be configured to maintain the gate of the charge transfer device320at a fixed voltage (e.g., at a first voltage).

In order to conduct a sensing operation on memory cell305, a gate of the charge transfer device320may be biased to a first voltage. The first voltage may be equivalent to or may be based in part on a precharge voltage of the digit line310plus the threshold voltage of the charge transfer device320. The first voltage applied to the gate of the charge transfer device320may result in the charge transfer device320being activated based on a state stored on the memory cell305. In some examples, the gate of the charge transfer device320may be biased to a first voltage based on a precharge voltage being applied to node365. In some examples, the memory cell305may be discharged onto the digit line310after the first voltage is applied to the gate of the charge transfer device320.

The compensation device325may be configured to apply a voltage to the gate of the charge transfer device320that compensates for a threshold voltage of the charge transfer device320. As part of biasing the gate of the charge transfer device320to the first voltage, the voltage applied to node365may be removed and the isolation device315activated. In such cases, node365may be coupled with a precharged digit line310. The voltage on the node365may relax to a voltage that is the precharge value of the digit line310plus the threshold voltage of the charge transfer device320. After the first voltage is set, the compensation device325may be deactivated and the gate of the charge transfer device320may be caused to float. Capacitor330may be implemented in order to maintain the gate of the charge transfer device320at a fixed voltage (e.g., at a first voltage).

In some examples, the memory cell305may be discharged onto the digit line310. Accordingly, by discharging the memory cell305, the digit line310may be biased to a voltage (e.g., to a second voltage), which may be based on a logic state stored to the memory cell305. For example, the digit line310may be biased to a different voltage if the memory cell305were to store a logic “1” state, then if the memory cell305were to store a logic “0” state.

The charge transfer device320may transfer the charge on the digit line310to the node365under certain conditions. Due to the charge transfer device320being activated (e.g., due to the first voltage applied to the gate), the charge from the memory cell305may be transferred to the sense component340if the second voltage is less than the first voltage. Because the charge across the digit line310and the resulting voltage applied to the gate of the charge transfer device320may be associated with a logic state of the memory cell305, the charge transfer device320may activate to varying degrees based on a particular logic state being stored to the memory cell305. In some cases, the degree to which the charge transfer device320is activated is based on the gate voltage applied to the charge transfer device320and the voltage applied to the source of the charge transfer device320(e.g., voltage on the digit line that is based on the logic state stored in the memory cell305).

In a first example of the read operation, the compensation phase and the cell dump phase are performed serially. Stated differently, the cell dump phase may not begin until the compensation phase is complete. To begin the compensation phase, a gate voltage may be applied to the gate of the charge transfer device320. The value of the gate voltage applied to the charge transfer device320may affect the amount of charge transferred during the read operation. In some cases, the gate voltage may be set to be around the precharge voltage of the digit line310plus the threshold voltage of the charge transfer device320. To bias the gate of the charge transfer device320to the first voltage (e.g., the gate voltage), the node365may be biased to a precharge voltage (e.g., CT precharge voltage). During this time, the compensation device325may be activated such that the gate of the charge transfer device320is also biased to the precharge voltage. The digit line310may also be precharged to its precharge voltage (e.g., DVC2). After the node365and the digit line310are precharged, the node365may be isolated from the voltage source375by deactivating the transistor377.

In addition, the isolation device315may be activated such that the node365and the digit line310are coupled through the charge transfer device320and the isolation device315. Upon coupling the node365and the digit line310, the node365may begin to discharge. Eventually, the voltage on the node365(and the gate of the charge transfer device320) may discharge to the first voltage value that is approximately the precharge voltage of the digit line310(e.g., DVC2) plus the threshold voltage (e.g., Vth) of the charge transfer device320(e.g., DVC2+Vth). After the gate voltage of the charge transfer device320is set, the compensation device325may be deactivated, causing the gate of the charge transfer device320to float. In addition, the isolation device315may be deactivated thereby isolating the digit line310from the charge transfer device320before the cell dump phase of the read operation begins. The read operation may move onto other phases of the operation, including dumping the value stored in the memory cell305onto the digit line310, transferring the charge between the digit line310and the node365, and sensing the signal on the node365.

During the cell dump phase, the transistor385may be activated thereby coupling the capacitor390of the memory cell305to the digit line310. The memory cell305may then discharge its stored charge onto the digit line310thereby biasing the digit line310to a second voltage different than the precharge voltage. Before this occurs, the digit line310may be isolated from the voltage source395used to precharge the digit line by deactivating the transistor385.

During the cell dump phase, the node365may be precharged to a second precharge voltage (e.g., sense precharge voltage). In some cases, the second precharge voltage is different than the first precharge voltage. In some cases, the second precharge voltage is the same as the first precharge voltage. The second precharge voltage may be set at a level such that charge may be transferred between the node365and the digit line310during the sensing phase.

After the cell dump phase is complete, the sensing phase may begin by activating the isolation device315. The digit line310, biased to a second voltage, may be coupled with the node365, biased to the second precharge voltage, by the charge transfer device320. Based on the value of the first voltage applied to the gate of the charge transfer device320and the second voltage on the digit line310, the charge transfer may transfer a varying amount of charge between the node365and the digit line310. For example, if second voltage is much less than the first voltage, a large amount of charge may be transferred, or if the second voltage is slightly less than the first voltage, a smaller amount of charge may be transferred. The sense components340and340-amay detect a signal (e.g., a charge) on the node365after the charge is transferred. A logic state stored to the memory cell305may be determined based on the signals sensed by the sense components340and340-a. Additional details about the sense phase are described with reference toFIGS. 4 and 5.

In a second example of the read operation, the compensation phase and the cell dump phase are performed at least partially concurrently. To clarify, the cell dump phase may begin before the compensation phase is complete. This is accomplished by using a different voltage source (e.g., voltage source335) other than digit line310to apply the first voltage to the gate of the charge transfer device320. In some cases, the gate voltage of the charge transfer device320may also be set at a value that is different than precharge voltage of the digit line310plus the threshold voltage of the charge transfer device320.

Additionally or alternatively, the circuit300may include voltage source335, which may be coupled with node370(e.g., via a transistor337). In some examples, node370may be referred to as a node of the charge transfer device320, and the voltage source335may be configured to apply a voltage to node370so that the compensation phase of the read operation may occur concurrently with the cell dump phase of the read operation. Said another way, the gate voltage of the charge transfer device320may be set using the voltage source335rather than the digit line310(biased to a precharge voltage, DVC2), thereby allowing another operation to occur on the digit line310while the gate of the charge transfer device320is being set. To bias the gate of the charge transfer device320using the voltage source335, the node365may be biased to a precharge voltage. During this time, the compensation device325may be activated such that the gate of the charge transfer device320is also precharged to the precharge voltage. After the node365is biased to the precharge voltage, the voltage source335may be coupled to the node370using the transistor337. The voltage may be applied when isolation device315is deactivated (e.g., is in an “off” position). The precharge voltage may cease being applied to the node365and the node365may discharge to a level that is the value of the voltage source335plus the voltage threshold of the charge transfer device320. The value of the voltage source335may set to be the precharge voltage of the digit line310(e.g., DVC2) or a value around the precharge voltage of the digit line (e.g., DVC2±φ). The gate of the charge transfer device320may be biased to a first voltage at least partially concurrent with the memory cell305being discharged onto the digit line310. After setting the gate voltage of the gate of the charge transfer device320, the voltage source335may be isolated from the node370and/or the compensation device325may be deactivated.

After biasing the gate of the charge transfer device320(e.g., to a first voltage) using the voltage source335, a cell dump phase may occur. During the cell dump phase, the transistor385may be activated thereby coupling the capacitor390of the memory cell305to the digit line310. The memory cell305may then discharge its stored charge onto the digit line310thereby biasing the digit line310to a second voltage different than the precharge voltage. Before this occurs, the digit line310may be isolated from the voltage source380used to precharge the digit line by deactivating the transistor387.

After the compensation phase but before the sensing phase, the node365may be precharged to a second precharge voltage (e.g., sense precharge voltage). In some cases, the second precharge voltage is different than the first precharge voltage. In some cases, the second precharge voltage is the same as the first precharge voltage. The second precharge voltage is set at a level such that charge may be transferred between the node365and the digit line310during the sensing phase.

After the cell dump phase is complete, the sensing phase may begin by activating the isolation device315. The digit line310, biased to a second voltage, may be coupled with the node365, biased to the second precharge voltage, by the charge transfer device320. Based on the value of the first voltage applied to the gate of the charge transfer device320and the second voltage on the digit line310, the charge transfer may transfer a varying amount of charge between the node365and the digit line310. For example, if second voltage is much less than the first voltage, a large amount of charge may be transferred, or if the second voltage is slightly less than the first voltage, a smaller amount of charge may be transferred. The sense components340and340-amay detect a signal (e.g., a charge) on the node365after the charge is transferred. A logic state stored on the memory cell305may be determined based on the signals sensed by the sense components340and340-a. Additional details about the sense phase are described with reference toFIGS. 4 and 5.

During the sensing phase, the node365may begin to discharge based on the voltage on the digit line310. The node365may discharge at different rates depending on the voltage on the digit line310. In some cases, the voltage on the digit line310means that the charge transfer device320does not transfer any charge or transfers very little charge (e.g., when the voltage on the digit line310is greater than the voltage on the gate of the charge transfer device320) For example, if the memory cell305discharged a logic “0” value onto the digit line310, the node365may discharge more quickly than, for example, if the memory cell305discharged a logic “1” value onto the digit line310. Thus, by sensing the voltage value of the node365(e.g., by first sense component340and second sense component340-a), a logic state of the memory cell305may be determined.

In some examples, first sense component340and second sense component340-amay sense the signal at node365using a fixed reference value at different times (e.g., at a first time and at a second time). Stated another way, the first sense component340may be provided with a same reference voltage (e.g., reference voltage415described with reference toFIG. 4) as the second sense component340-a. A transistor345may be activated such that first sense component340may receive the signal of the node365. The first sense component340may conduct a sense operation by comparing the signal of the node365to reference voltage. This sense operation may occur at a first time.

In some examples, the transistor345may then be deactivated such that the signal of the node365may not be received by the first sense component340. To conduct the sense operation, the transistor345-amay be activated (e.g., turned to an “on” position) such that the second sense component340-amay receive the signal of the node365. The second sense component340-amay then conduct a sense operation by comparing the signal of the node365to a reference voltage. In some examples, the transistor345-amay then be deactivated (e.g., turned to an “off” position). This sense operation may occur, for example, at a second time different than (e.g., after) the first time. The resulting values of sensing the signal of the node365using the first sense component340and the second sense component340-amay be used to determine the logic state of the memory cell305. For example, if memory cell305was configured to store three logic states, the resulting logic state may be a logic “0”, a logic “mid”, or a logic “1” value. A logic “mid” may be, in some examples, either a logic “01” or a logic “10” value. In some examples, using a fixed reference voltage may reduce the noise associated with changing the reference voltage during the sensing period. The noise may be reduced, for example, because a reference voltage of the second sense component340-awould not need to be updated and/or applied to the second sense component340-aafter a first sense operation.

In some examples, the first sense component340and the second sense component340-amay sense the signal of node365using different fixed reference values at a same time (e.g., reference voltage415and reference voltage420described with reference toFIG. 4). Stated another way, the first sense component340may be provided with a first reference voltage (e.g., reference voltage415) and the second sense component340-amay be provided with a second reference voltage (e.g., a different reference voltage420). In some examples the reference voltages may be offset (e.g., by a predetermined voltage value). Further, circuit300may include, a first reference line350and a second reference line355. The first reference line350may be coupled to the first sense component340and configured to carry a first reference voltage to at least the first sense component340. The second reference line355may be coupled to the second sense component340-aand configured to carry a second reference voltage to the second sense component340-aor, in some cases, the first reference voltage to the second sense component340-a. In some examples, the first reference voltage provided by the first reference line350and the second reference voltage provided by the second reference line355may be fixed voltages. Additionally, the first reference voltage provided to both the first reference line350and the second reference line355may be a fixed voltage. In other examples, the first and second reference voltages may be any combination of fixed and variable voltages.

A transistor345and a transistor345-amay each be activated such that the first sense component340and the second sense component340-amay receive a signal (e.g., a charge) of the node365at a same time. The first sense component340and the second sense component340-amay conduct a sense operation simultaneously by comparing the signal of the node365to a first reference voltage and a second reference voltage different than the first reference voltage. The resulting values of sensing the signal on the node365at the first sense component340and the second sense component340-amay be used to determine the logic state of the memory cell305. For example, if memory cell305was configured to store three logic states, the resulting logic state may be a logic “00”, a logic “mid”, or a logic “11” value. A logic “mid” may be, in some examples, either a logic “01” or a logic “10” value.

In some cases, it may be more difficult to detect some states that other states. For example, using the sense component340to detect a 0 and the sense component340-ato detect a 1 (e.g., a logic state 01) may be harder to sense than the logic state 10 (for example, when the sense component340detects a 1 and the sense component340-adetects a 0). In some examples, a simultaneous sense operation (e.g., sensing the signal of node365via the first sense component340and the second sense component340-asimultaneously) may improve the timing of a read operation. Additionally or alternatively, in the examples described above, a sensing operation may occur using the first sense component340and the second sense component340-aby using any combinations of a fixed reference voltage, different reference voltages, a fixed timing operation, and different timing operations. Moreover, the number of sensed states may be correlated to the number of sense amplifiers. In one example, the ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than 1. More specifically, in this example, the ratio of the number of states read by the sense components and the number of sense components may be 3:2.

In some examples, first reference line350and second reference line355may provide a first fixed reference voltage and a second fixed reference voltage, respectively. In this example, the number of states read by the first sense component and the second sense component may be correlated to the number of reference voltages. Continuing this example, the ratio of the number of states read by the first sense component and the second sense component to the number of reference voltages may be greater than 1. Further, the ratio of the number of states read by the first sense component and the second sense component to the number of reference voltages may be 3:2. In some examples, the first reference line350and the second reference line355may provide the same reference voltage to their respective sense components. In such examples, the ratio of the number of states read by the first sense component and the second sense component to the number of reference voltages may be 3:1.

In other examples, the memory cell305may be configured to store four logic states (e.g., “00”, “01”, “10”, or “11”). Using the same techniques as described above, the logic state of the memory cell305may be determined. In some examples, to determine a logic state of a memory cell configured to store four logic states, a third sense component (not shown) may be implemented. For example, a third sense component may be coupled with node365using an additional transistor (not shown) configured to isolate the third sense component from the first sense component340and the second sense component340-aat different times during the sensing operation. Furthermore, the number of sensed states may be correlated to the number of sense amplifiers. In one example, the ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than 1. More specifically, in this example, the ratio of the number of states read by the sense components and the number of sense components may be 4:3.

In some examples, first reference line350, second reference line355and a third reference line, may provide a first fixed reference voltage, a second fixed reference voltage, and a third fixed reference voltage, respectively. In this example, the number of states read by the first sense component, the second sense component, and the third sense component may be correlated to the number of reference voltages. Continuing this example, the ratio of the number of states read by the first, second, and third sense components to the number of reference voltages may be greater than 1. Further, the ratio of the number of states read by the first, second, and third sense components to the number of reference voltages may be 4:3. In some examples, the first reference lines may provide the same reference voltage to each of their respective sense components. In such examples, the ratio of the number of states read by the first, second, and third sense components to the number of reference voltages may be 4:1. Accordingly, in some examples, the first sense component340, the second sense component340-a, and the third sense component may sense the voltage of node365using a fixed reference value at different times (e.g., at a first time, at a second time, and at a third time). Stated another way, the first sense component340may be provided with a same reference voltage as second sense component340-a, and the third sense component. The second sense component340-aand the third sense component may be isolated from the first sense component340by activating transistor345, such that first sense component340may receive a signal of the node365. The first sense component340may conduct a sense operation by comparing the signal of the node365to the reference voltage. This sense operation may occur at a first time.

In some examples, the transistor345may be deactivated such that the signal of node365may not be received by the first sense component340or the third sense component. The second sense component340-amay conduct a sense operation by first activating transistor345-aand comparing the signal of the node365to the reference voltage. This sense operation may occur, for example, at a second time different than (e.g., after) the first time. The transistor345may remain deactivated such that the signal of node365may not be received by the first sense component340and the second sense component340-a. The third sense component may then conduct a sense operation by comparing the signal of the node365to an additional (e.g., a fixed) reference voltage. This sense operation may occur, for example, at a third time different than (e.g., after) the first time and the second time. In some examples, the transistor345and the transistor345-amay each be deactivated during the third sense operation.

The resulting values of sensing the signal of the node365at the first sense component340, the second sense component340-a, and the third sense component may be used to determine the logic state of the memory cell305. For example, if memory cell305was configured to store four logic states, the resulting logic state of the memory cell305may be a logic “00”, a logic “01”, a logic “10”, or a logic “11” value.

In yet another example, the first sense component340, the second sense component340-a, and the third sense component may sense the signal of node365using different fixed reference values at a same time. Stated another way, the first sense component340may be provided with a first reference voltage (e.g., provided by reference line350), the second sense component340-amay be provided with a second reference voltage (e.g., provided by reference line355), and the third sense component may be provided with a third reference voltage (e.g., different than the first reference voltage and the second reference voltage). In some examples the reference voltages may be offset (e.g., by a predetermined voltage value).

To determine the logic state of the memory cell305, at least the transistor345and the transistor345-amay be activated such that first sense component340, the second sense component340-a, and the third sense component may receive a signal (e.g., a charge) of the node365at a same time. The first sense component340, the second sense component340-a, and the third sense component may conduct a sense operation simultaneously by comparing the signal of the node365to a first reference voltage, a second reference voltage, and third reference voltage (e.g., associated with the third sense component) respectively. The resulting values of sensing the signal of the node365at the first sense component340, the second sense component340-a, and the third sense component may be used to determine the logic state of the memory cell305. For example, if memory cell305was configured to store four logic states, the resulting logic state may be a logic “00”, a logic “01”, a logic “10”, or a logic “11” value. Additionally or alternatively, in the examples described above, a sensing operation may occur using first sense component340, second sense component340-a, and third sense component by using any combinations of a fixed reference voltage, different reference voltages, a fixed timing operation, and different timing operations.

In some examples, each of the sense components (e.g., first sense component340, second sense component340-a, and/or a third sense component) may be coupled with write logic block360. In some examples, the write logic block360may be configured to write a logic value to the memory cell based on a sense operation. As described above, a sense operation may be conducted on a memory cell configured to store either three logic states or four logic states, using any combination of a fixed reference voltage, different reference voltages, a fixed timing operation, and different timing operations. Thus, the determined logic value of memory cell305, using any of the aforementioned methods, may be written back to memory cell305using write logic block360.

FIG. 4illustrates an example timing diagram400that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The timing diagram400may illustrate an operation of the circuit300as described with reference toFIG. 3. Thus, timing diagram400may illustrate the operation of one or more components described above with reference toFIGS. 1, 2, and 3. For example, timing diagram400may illustrate the voltage of a node (e.g., node365as described with reference toFIG. 3) as applied to a first sense component (e.g., sense component340as described with reference toFIG. 3) and a second sense component (e.g., sense component340-aas described with reference toFIG. 3). The voltage405may represent a voltage of the node based on the state stored on the memory cell. Timing diagram400may also illustrate a reference voltage465and a reference voltage460. In some examples, a circuit may apply a single fixed reference voltage (e.g., reference voltage465) to multiple sense components to determine the logic state stored on the memory cell. In some examples, a circuit may apply multiple fixed reference voltages (e.g., reference voltage465and reference voltage460) to different sense components to determine logic state stored on the memory cell. In such examples, the second reference voltage460may be used in read operations where both sense amplifiers activate at the same time. In some examples, the voltages410,415, and420(e.g., high, mid, and low) may be different possibilities of signals on the node based on the different states that can be stored on the memory cell.

A node (e.g., node365as described with reference toFIG. 3) coupled with a charge transfer device (e.g., charge transfer device320as described with reference toFIG. 3) may be precharged to a first voltage. For example, the node may be precharged by a voltage source coupled with the node and a compensation device. In some examples, the node may be precharged to 1.5V. After precharging the node, a compensation operation may occur, and the node may begin to discharge. Subsequently, a memory cell (e.g., memory cell305as described with reference toFIG. 3) may be discharged onto a digit line (e.g., digit line310as described with reference toFIG. 3). Accordingly, the digit line voltage may be biased to a second voltage based on the logic state stored to the memory cell.

At435, a precharge voltage may be applied to the node coupled with the charge transfer device (e.g., re-applying the first precharge voltage to the node), and may be applied to the node coupled with the first sense component and the second sense component via the charge transfer device. Thus, during435, the voltage of the node may be maintained at a constant (e.g., a fixed) voltage value.

At440, the node coupled with the first sense component and the second sense component may be coupled with the digit line. This may signal the beginning of a sense phase of the read operation. To accomplish this, in some cases, the isolation device (e.g., isolation device315described with reference toFIG. 3) may be activated. The node may begin to discharge based on the voltage on the digit line (e.g., based on the state stored on the memory cell). In some examples, the rate at which the node discharges may be based on the state stored on the memory cell. Additionally or alternatively, if the charge transfer device transfers a charge between the digit line and the node, the node may discharge at a second (e.g., a faster) rate. Thus, the voltage of the node may correspond to a particular logic state of the memory cell based on transferring the charge between the digit line and the node (e.g., voltages410,415, and420at high, mid, and low levels, respectively, may each correspond to a different logic state of the memory cell).

At445, a first sense operation may occur at a first time. For example, the first sense component (e.g., the sense component340described with reference toFIG. 3) may sense a signal on the node (e.g., the sense component may be fired). During the first sense operation, the voltage of the node may be compared with reference voltage465by the first sense component. Because the rate at which the node discharges may be based on based on a logic state of the memory cell, comparing the voltage405with the reference voltage465may indicate a logic state of the memory cell. For example, the first sense amplifier may be configured to distinguish between a first logic state and two other logic states by comparing the signal on the node to a reference signal positioned between the first logic state and the second logic state. Hence, an additional sense amp may be used to distinguish between the second logic state and the third logic state.

At450, a duration may pass between a first sense operation and a second sense operation. For example, at430, the transistor coupled with the first sense component and the second sense component may be deactivated (e.g., transistor345and transistor345-aas described with reference toFIG. 3). This may isolate the first sense component from the second sense component, such that the voltage of the node may be sensed by the second sense component during a second sense operation. In addition, during this duration, the signal on the node may discharge and/or continue to discharge.

At455, a second sense operation may occur at a second time after the first time. During the second sense operation, the voltage of the node may be sensed by the sense component and compared with reference voltage465. Because the rate at which the node discharges may be based on the state stored on the memory cell, comparing the voltage405with the reference voltage465may indicate a logic state of the memory cell. Additionally or alternatively, by using a charge transfer device, the sensing window425and the sensing window430may be improved, thus resulting in a more accurate sensing operation, among other benefits.

In some examples, a logic sate of the memory cell may be determined based on both the first sense operation and the second sense operation. For example, the first sense component may compare voltage405with the reference voltage465. Based on a difference between the voltages, the first sense component may determine a “1” or a “0” value. Subsequently, the second sense component may compare voltage405with the reference voltage465and, based on the difference between the voltages, may determine a “1” or a “0” value. Accordingly, based on the sense operations, the logic state of the memory cell may be determined to be a logic “00”, “01”, or “11” value.

The number of sensed states may be correlated to the number of sense amplifiers. In one example, the ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than 1. More specifically, in this example, the ratio of the number of states read by the sense components and the number of sense components may be 3:2. In some examples, first reference line350and second reference line355may provide a first fixed reference voltage and a second fixed reference voltage, respectively.

In this example, the number of states read by the first sense component and the second sense component may be correlated to the number of reference voltages. Continuing this example, the ratio of the number of states read by the first sense component and the second sense component to the number of reference voltages may be greater than 1. Further, the ratio of the number of states read by the first sense component and the second sense component to the number of reference voltages may be 3:2. Moreover, the ratio of the number of states read by the first sense component and the second sense component to the number of reference voltages may be 3:1.

In some examples, a first sense operation and second sense operation may occur at a same time (e.g., at a first time). For example, the first sense component and the second sense component (e.g., the sense component340described with reference toFIG. 3) may each sense a signal on the node. During the sense operation, the voltage of the node may be transferred to the first sense component and the second sense component and be compared with reference voltage465and reference voltage460, respectively. Stated another way, during a sense operation where the first sense component and the second sense component operate concurrently, voltage405may be compared with the reference voltage465by the first sense component and voltage405may be compared with the reference voltage460by the second sense component (or vice-versa).

Because the rate at which the node discharges may be based on whether the charge transfer device transfers a charge from the digit line, and whether the charge transfer device transfers a charge from the digit line may be based on a logic state of the memory cell, comparing the voltage405with the reference voltage465and the reference voltage460, respectively, may indicate a logic state of the memory cell. For example, the first sense amplifier may be configured to distinguish between a first logic state and two other logic states, and the second sense amplifier may be used to distinguish between the second logic state and the third logic state by comparing the signal on the node to a reference signal positioned between the second logic state and the third logic state.

FIG. 5illustrates an example timing diagram500that supports sensing techniques using a charge transfer device in accordance with aspects of the present disclosure. In some examples, timing diagram500may illustrate a portion of read operation for a memory cell that stores four states. The timing diagram500may illustrate an operation of circuit similar to the circuit300described with reference toFIG. 3, except that a third sense component may be coupled with the node365. Thus, timing diagram500may illustrate the operation of one or more components described above with reference toFIGS. 1, 2, and 3. For example, timing diagram500may illustrate the voltage of a node (e.g., node365as described with reference toFIG. 3) as applied to a first sense component (e.g., sense component340as described with reference toFIG. 3), a second sense component (e.g., sense component340-aas described with reference toFIG. 3), and a third sense component. In some examples, the voltages505,510,515, and520may be different possibilities of signals on the node based on the different states that are stored on the memory cell. The voltages505,510,515, and520may represent a high-level, a high-mid-level, a low-mid-level, and a low level, respectively, and may each correspond to a different logic state stored by the memory cell. Timing diagram500may also include reference voltage525, reference voltage575, and reference voltage580. Reference voltage575and reference voltage580may be used in examples where a first sense component, second sense component, and third sense component fire at a same time.

As described above, a node (e.g., node365as described with reference toFIG. 3) coupled with the charge transfer device (e.g., charge transfer device320as described with reference toFIG. 3) may be precharged to a first voltage. For example, the node may be precharged by a voltage source coupled with the node and a compensation device. In some examples, the node may be precharged to 1.5V. After precharging the node, a compensation operation may occur, and the node may begin to discharge. Subsequently, a memory cell (e.g., memory cell305as described with reference toFIG. 3) may be discharged onto a digit line (e.g., digit line310as described with reference toFIG. 3). Accordingly, the digit line voltage may be biased to a second voltage based on the logic state stored to the memory cell.

At545, the node coupled with the first sense component, the second sense component, and the third sense component may be coupled with the digit line. In some examples, this may signal the beginning of a sense phase of the read operation. To accomplish this the isolation device (e.g., isolation device315described with reference toFIG. 3) may be activated. The node may begin to discharge based on the voltage on the digit line (e.g., based on the state stored on the memory cell). In some examples, the rate at which the node discharges may be based on the state stored on the memory cell Additionally or alternatively, if the charge transfer device transfers a charge from the digit line to the node, the node may discharge at a second (e.g., a faster) rate. Thus the voltage of the node may correspond to a particular logic state of the memory cell.

At550, a first sense operation may occur at a first time. For example, the first sense component (e.g., the sense component340described with reference toFIG. 3) may sense a signal on the node. During the first sense operation, the voltage of the node may be transferred to the sense component and compared with reference voltage525. Stated another way, during a first sense operation, the signal on the node may be compared with the reference voltage525by the first sense component. Because the rate at which the node discharges may be based on whether the charge transfer device transfers a charge from the digit line, and whether the charge transfer device transfers a charge from the digit line may be based on a logic state of the memory cell, comparing the signal on the node with the reference voltage525may indicate a logic state of the memory cell. For example, the first sense amplifier may be configured to distinguish between a first logic state and three other logic states.

At555, a duration may pass between a first sense operation and a second sense operation. For example, at555, the at least one transistor coupled with the first sense component, the second sense component, and the third sense component may be deactivated. This may isolate the first sense component and the third sense component from the second sense component, such that the voltage of the node may be sensed by the second sense component during a second sense operation. In addition, during this duration, the signal on the node may continue to discharge.

At560, a second sense operation may occur at a second time. For example, the second sense component (e.g., the sense component340-adescribed with reference toFIG. 3) may sense a signal on the node. During the second sense operation, the voltage of the node may be compared with reference voltage525by the second sense component. Because the rate at which the node discharges may be based on whether the charge transfer device transfers a charge from the digit line, and whether the charge transfer device transfers a charge from the digit line may be based on a logic state of the memory cell, comparing the signal on the node with the reference voltage525may indicate a logic state of the memory cell. For example, the second sense amplifier may be configured to distinguish between a second logic state and a third logic state.

At565, a duration may pass between a second sense operation and a third sense operation. For example, at565, the at least one transistor coupled with the first sense component, the second sense component, and/or the third sense component may be deactivated. This may isolate the first sense component and the second sense component from the third sense component, such that the voltage of the node may be sensed by the third sense component during a third sense operation. In addition, during this duration, the signal on the node may continue to discharge.

At570, a third sense operation may occur at a third time. For example, the third sense component may sense a signal on the node. During the third sense operation, the voltage of the node may be compared with reference voltage525by the third sense component. Because the rate at which the node discharges may be based on whether the charge transfer device transfers a charge from the digit line, and whether the charge transfer device transfers a charge from the digit line may be based on a logic state of the memory cell, comparing the signal on the node with the reference voltage525may indicate a logic state of the memory cell. For example, the third sense amplifier may be configured to distinguish between a third logic state and a fourth logic state. Additionally or alternatively, by implementing a charge transfer device, the sensing window530, the sensing window535, and the sensing window540may be improved, thus resulting in a more accurate sensing operation.

In some examples, a logic sate of the memory cell may be determined based on each of the first sense operation, the second sense operation, and the third sense operation. For example, the first sense component may compare the signal on the node with the reference voltage525. Based on a difference between the voltages, the first sense component may determine a “1” or a “0” value. Subsequently, the second sense component may compare the signal on the node with the reference voltage525and, based on the difference between the voltages, may determine a “1” or a “0” value. Additionally or alternatively, the third sense component may compare the signal on the node with the reference voltage525and, based on the difference between the voltages, may determine a “00”, “01”, “10”, or “11” value based on both the first sense operation and the second sense operation. Thus, based on each of the sense operations, the logic state of the memory cell may be determined to be a logic “00”, “01”, “10”, or “11” value.

Additionally, the number of sensed states may be correlated to the number of sense amplifiers. In one example, the ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than 1. More specifically, in this example, the ratio of the number of states read by the sense components and the number of sense components may be 4:3. In some examples, first reference line350, second reference line355and a third reference line coupled to the third sense component, may provide a first fixed reference voltage, a second fixed reference voltage, and a third fixed reference voltage, respectively.

In this example, the number of states read by the first sense component, the second sense component, and the third sense component may be correlated to the number of reference voltages. Continuing this example, the ratio of the number of states read by the first, second, and third sense components to the number of reference voltages may be greater than 1. Further, the ratio of the number of states read by the first, second, and third sense components to the number of reference voltages may be 4:3. Moreover, the ratio of the number of states read by the first, second, and third sense components to the number of reference voltages may be 4:1.

In some examples, a first sense operation, a second sense operation, and a third sense operation may occur at a same time (e.g., at a first time). For example, the first sense component, the second sense component, and the third sense component may each sense a signal on the node. During the sense operation, the signal of the node may be compared with reference voltage525, reference voltage575, and reference voltage580, respectively, at the same time. Stated another way, during a sense operation where the first sense component, the second sense component, and the third sense component fire concurrently, the signal on the node may be compared with the reference voltage525by the first sense component, the signal on the node may be compared with the reference voltage580by the second sense component, and the signal on the node may be compared with the reference voltage575by the third sense component.

Because the rate at which the node discharges may be based on whether the charge transfer device transfers a charge from the digit line, and whether the charge transfer device transfers a charge from the digit line may be based on a logic state of the memory cell, comparing the signal on the node with the reference voltage525, the reference voltage575, and the reference voltage580, respectively, may indicate a logic state of the memory cell. For example, the first sense amplifier may be configured to distinguish between a first logic state and three other logic states, the second sense amplifier may be used to distinguish between the second logic state and the third logic state, and the third sense amplifier may be used to distinguish between the third logic state and the fourth logic state.

FIG. 6shows a block diagram600of a memory component605that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The memory component605may be an example of aspects of a memory controller (e.g., external memory controller105, device memory controller155, local memory controller165, or a combination thereof as described with reference toFIG. 1). The memory component605may include transfer component610, sense component615, determination component620, gate component625, comparative component630, bias component635, discharge component640, isolation component645, and store component650. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

Transfer component610may transfer, using a charge transfer transistor, a charge between a digit line and a node coupled with a first sense component and a second sense component based at least in part on a first voltage on the digit line being less than a second voltage on a gate of the charge transfer transistor. In some examples, transfer component610may transfer, using a charge transfer transistor, a charge between a digit line and a node of a first sense component and a second sense component during a read operation, wherein the charge is transferred based at least in part on a first voltage on the digit line being less than a second voltage on a gate of the charge transfer transistor. The charge transfer transistor may be referred to as such for purposes of clarity and function and not of limitation. The charge transfer transistor may be any type of transistor that performs the appropriate functions as described herein.

Sense component615may sense, by the set of sense components, a signal on the node at a first time based at least in part on transferring the charge between the digit line and the node. In some examples, sense component615may sense, by the second sense component, the signal on the node at a second time different than the first time based at least in part on transferring the charge between the digit line and the node. In some examples, sense component615may sense the signal by the first sense component and may compare the signal on the node to a fixed reference value at the first time. Further, the sense component615may sense the signal at the second sense component and may compare the signal on the node to the fixed reference value at the second time. In some examples, a set of sense components may sense a state of a memory cell that is configured to store three or more states, in which a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one.

In some examples, sense component615may sense, by a third sense component coupled with the digit line using the charge transfer transistor, the signal on the node at the time using a third reference value based at least in part on transferring the charge between the digit line and the node, wherein determining the logic state of the multi-level memory cell is based at least in part on sensing the signal at the third sense component. In some examples, a set of sense components, including a first sense component, a second sense component, and a third sense component, may sense a state of a memory cell that is configured to store three or more states, in which a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one.

In some examples, sense component615may sense, using a third sense component coupled with the digit line using the charge transfer transistor, the signal on the node at a third time different than the second time based at least in part on transferring the charge between the digit line and the node, in which determining the logic state of the multi-level memory cell is based at least in part on sensing the signal using the third sense component. In some examples, sense component615may sense, by the first sense component, a signal on the node at a time using a first reference value based at least in part on transferring the charge between the digit line and the node. In some examples, sense component615may sense, by the second sense component, the signal on the node at the time using a second reference value based at least in part on transferring the charge between the digit line and the node.

Determination component620may determine a logic state of a multi-level memory cell based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component. Determination component620may be a configuration of multiple elements and may include any of the following elements in any combination thereof, a first sense component coupled to the digit line and the node, a second sense component coupled to the digit line and the node, a first reference line coupled to the first sense component and configured to transmit a first reference voltage to at least the first sense component, a second reference line coupled to the second sense component and configured to transmit a second reference voltage to the second sense component, and a charge transfer device which may be a transistor. In some examples, determination component620may determine a logic state of a multi-level memory cell coupled with the digit line based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component. In some examples, determination component620may determine the second voltage on the gate of the charge transfer transistor. In some examples, the determination component620may determine the state of the memory cell based on the ratio being greater than one. The multi-level memory cell may be referred to as a memory cell and the terms may be used interchangeably herein.

Gate component625may bias the gate of the transistor to the second voltage before transferring the charge between the digit line and the node. In some examples, gate component625may bias the digit line to the first voltage based at least in part on discharging the multi-level memory cell onto the digit line. In some examples, gate component625may bias the gate of the transistor to the second voltage based at least in part on applying the third voltage. In some examples, gate component625may bias the digit line to the first voltage based at least in part on discharging the multi-level memory cell onto the digit line. In some examples, gate component625may bias the gate of the transistor to the second voltage before transferring the charge between the digit line and the node.

Comparative component630may compare the charge transferred to the node to a fixed reference value at a first time, in which the transistor is configured to transfer the charge between the digit line and the node of the first and second sense components and also compares the charge transferred to the node to the fixed reference value at a second time different than the first time.

Bias component635may bias the gate of the transistor to the second voltage before transferring the charge between the digit line and the node.

Discharge component640may discharge the multi-level memory cell onto the digit line based at least in part on biasing the gate of the transistor. In some examples, discharge component640may discharge the node onto the gate of the transistor while the transistor is coupled with the digit line. In some examples, discharge component640may discharge the multi-level memory cell to the digit line concurrent with biasing the gate of the transistor.

In some examples, discharge component640may discharge the multi-level memory cell onto the digit line based at least in part on applying the second voltage to the gate of the transistor, wherein the digit line is biased to the first voltage based at least in part on discharging the multi-level memory cell onto the digit line. In some examples, discharge component640may discharge the multi-level memory cell to the digit line concurrent with biasing the gate of the transistor, wherein the digit line is biased to the first voltage based at least in part on discharging the multi-level memory cell onto the digit line.

Isolation component645may isolate the digit line from the transistor after biasing the gate of the transistor to the second voltage. In some examples, isolation component645may isolate the digit line from the transistor after biasing the gate of the transistor to the second voltage.

Store component650may write the determined logic state to the multi-level memory cell after the read operation.

FIG. 7shows a flowchart illustrating a method700that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The operations of method700may be implemented by a memory device with a charge transfer device and/or its components as described herein. For example, the operations of method700may be performed by a controller (e.g., external memory controller105, device memory controller155, local memory controller165, local memory controller260, or a combination thereof) as described with reference toFIGS. 1 through 3. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, a memory device may perform aspects of the functions described below using special-purpose hardware.

At705, the controller may transfer, using a transistor, a charge between a digit line and a node coupled with a set of sense components during a read operation, where the charge is transferred based on a first voltage on the digit line being less than a second voltage on a gate of the transistor. In some examples, aspects of the operations of705may be performed by a transfer component as described with reference toFIG. 6.

At710, the controller may sense, by the set of sense components based on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, where a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one. In some examples, aspects of the operations of710may be performed by a sensing component as described with reference toFIG. 6.

At715, the controller may determine the state of the memory cell based on the ratio being greater than one. In some examples, aspects of the operations of715may be performed by a determining component as described with reference toFIG. 6.

FIG. 8shows a flowchart illustrating a method800that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The operations of method800may be implemented by a controller or its components as described herein. For example, the operations of method800may be performed by a controller (e.g., external memory controller105, device memory controller155, local memory controller165, local memory controller260, or a combination thereof) as described with reference toFIGS. 1, 2, and 3. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, a memory device may perform aspects of the functions described below using special-purpose hardware.

At805, the controller may transfer, using a transistor, a charge between a digit line and a node coupled with a set of sense components during a read operation, where the charge is transferred based on a first voltage on the digit line being less than a second voltage on a gate of the transistor. In some examples, aspects of the operations of805may be performed by a transfer component as described with reference toFIG. 6.

At810, the controller may sense, by the set of sense components based on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, where a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one, where the set of sense components includes a first sense component and a second sense component that are each coupled with the node. In some examples, aspects of the operations of810may be performed by a sensing component as described with reference toFIG. 6.

At815, the controller may determine the state of the memory cell based on the ratio being greater than one, where the ratio of the number of states read by the set of sense components to the number of the set of sense components is 3:2. In some examples, aspects of the operations of815may be performed by a determination component as described with reference toFIG. 6.

FIG. 9shows a flowchart illustrating a method900that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The operations of method900may be implemented by a controller or its components as described herein. For example, the operations of method900may be performed by a controller (e.g., external memory controller105, device memory controller155, local memory controller165, local memory controller260, or a combination thereof) as described with reference to at leastFIGS. 1, 2, and 3. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, a memory device may perform aspects of the functions described below using special-purpose hardware.

At905, the controller may transfer, using a transistor, a charge between a digit line and a node coupled with a set of sense components during a read operation, where the charge is transferred based on a first voltage on the digit line being less than a second voltage on a gate of the transistor. In some examples, aspects of the operations of905may be performed by a transfer component as described with reference toFIG. 6.

At910, the controller may sense, by the set of sense components based on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, where a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one, where the set of sense components includes a first sense component and a second sense component that are each coupled with the node. In some examples, aspects of the operations of910may be performed by a sense component as described with reference toFIG. 6.

At915, the controller may sense a signal at the first sense component by comparing the charge transferred to the node to a fixed reference value at a first time, where the transistor is configured to transfer the charge between the digit line and the node of the first sense component and the second sense component during the read operation, and. In some examples, aspects of the operations of915may be performed by a comparative component as described with reference toFIG. 6.

At920, the controller may compare the charge transferred to the node to the fixed reference value at a second time different than the first time. In some examples, aspects of the operations of920may be performed by a comparative component as described with reference toFIG. 6.

At925, the controller may determine the state of the memory cell based on the ratio being greater than one, where the ratio of the number of states read by the set of sense components to the number of the set of sense components is 3:2. In some examples, aspects of the operations of925may be performed by a determination component as described with reference toFIG. 6.

FIG. 10shows a flowchart illustrating a method1000that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The operations of method1000may be implemented by a memory device or its components as described herein. For example, the operations of method1000may be performed by a controller (e.g., external memory controller105, device memory controller155, local memory controller165, local memory controller260, or a combination thereof) as described with reference toFIGS. 1, 2, and 3. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, a memory device may perform aspects of the functions described below using special-purpose hardware.

At1005, the controller may bias the gate of the transistor to the second voltage before transferring the charge between the digit line and the node. In some examples, aspects of the operations of1005may be performed by a bias component as described with reference toFIG. 6.

At1010, the controller may discharge the memory cell onto the digit line based on biasing the gate of the transistor to the second voltage, where the digit line is biased to the first voltage based on discharging the memory cell onto the digit line. In some examples, aspects of the operations of1010may be performed by a discharge component as described with reference toFIG. 6.

At1015, the controller may transfer, using a transistor, a charge between a digit line and a node coupled with a set of sense components during a read operation, where the charge is transferred based on a first voltage on the digit line being less than a second voltage on a gate of the transistor. In some examples, aspects of the operations of1015may be performed by a transfer component as described with reference toFIG. 6.

At1020, the controller may sense, by the set of sense components based on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, where a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one. In some examples, aspects of the operations of1020may be performed by a sense component as described with reference toFIG. 6.

At1025, the controller may determine the state of the memory cell based on the ratio being greater than one. In some examples, aspects of the operations of1025may be performed by a determination component as described with reference toFIG. 6.

At1030, the controller may isolate the set of sense components from the digit line based on sensing the state of the memory cell. In some examples, aspects of the operations of1030may be performed by an isolation component as described with reference toFIG. 6.

At1035, the controller may store a high-level state in the memory cell based on isolating the set of sense amplifiers from the digit line. In some examples, aspects of the operations of1035may be performed by a store component as described with reference toFIG. 6.

FIG. 11shows a flowchart illustrating a method1100that supports a memory device with a charge transfer device in accordance with aspects of the present disclosure. The operations of method1100may be implemented by a memory device or its components as described herein. For example, the operations of method1100may be performed by a controller (e.g., external memory controller105, device memory controller155, local memory controller165, local memory controller260, or a combination thereof) as described with reference toFIGS. 1, 2, and 3. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described below. Additionally or alternatively, a memory device may perform aspects of the functions described below using special-purpose hardware.

At1105, the controller may transfer, using a transistor, a charge between a digit line and a node coupled with a set of sense components during a read operation, where the charge is transferred based on a first voltage on the digit line being less than a second voltage on a gate of the transistor. In some examples, aspects of the operations of1105may be performed by a transfer component as described with reference toFIG. 6.

At1110, the controller may sense, by the set of sense components based on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, where a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one, where the set of sense components includes a first sense component and a second sense component that are each coupled with the node. In some examples, aspects of the operations of1110may be performed by a sense component as described with reference toFIG. 6.

At1115, the controller may sense, using a third sense component coupled with the digit line using the transistor, the charge transferred to the node at a third time different than a second time based on sensing the charge transferred to the node at the second time, where determining the state of the memory cell includes, sensing the charge at the third sense component. In some examples, aspects of the operations of1115may be performed by a sense component as described with reference toFIG. 6.

At1120, the controller may determine the state of the memory cell based on the ratio being greater than one. In some examples, aspects of the operations of1120may be performed by a determination component as described with reference toFIG. 6.

At1125, the controller may determine the state of the memory cell based on a ratio being four states read by the set of sense components to three sense components. In some examples, aspects of the operations of1125may be performed by a determination component as described with reference toFIG. 6.

An apparatus is described. The apparatus may include a memory cell coupled with a digit line and configured to store three or more states, a set of sense components coupled with a node and configured to read a number of states of the memory cell, a transistor coupled with the node and the digit line and configured to transfer charge between the digit line and the node, and wherein a ratio of the number of states read by the set of sense components and a number of the set of sense components is greater than one. The plurality of sense components may include a first sense component coupled with the node and configured to sense a signal caused by transferring the charge between the digit line and the node, and a second sense component coupled with the node and configured to sense the signal caused by transferring the charge between the digit line and the node.

A method is described. In some examples, the method may include transferring, using a transistor, a charge between a digit line and a node coupled with a plurality of sense components during a read operation, wherein the charge is transferred based at least in part on a first voltage on the digit line being less than a second voltage on a gate of the transistor, sensing, by the plurality of sense components based at least in part on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, wherein a ratio of the number of states read by the plurality of sense components and a number of the plurality of sense components is greater than one, determining the state of the memory cell based at least in part on the ratio being greater than one. The plurality of sense components comprises a first sense component and a second sense component that are each coupled with the node, further wherein the ratio of the number of states read by the plurality of sense components to the number of the plurality of sense components is 3:2.

In some examples, the method may include sensing a signal at the first sense component by comparing the charge transferred to the node to a fixed reference value at a first time, wherein the transistor is configured to transfer the charge between the digit line and the node of the first sense component and the second sense component during the read operation and sensing the signal at the second sense component may include comparing the charge transferred to the node to the fixed reference value at a second time different than the first time.

In some examples, the method may include sensing, using a third sense component coupled with the digit line using the transistor, the charge transferred to the node at a third time different than a second time based at least in part on sensing the charge transferred to the node at the second time, where determining the state of the memory cell comprises, sensing the charge at the third sense component. Additionally, the method may include determining the state of the memory cell based at least in part on a ratio being four states read by the plurality of sense components to the three sense components. Additionally, the method may include determining the state of the memory cell based at least in part on a ratio of the states read by the plurality of sense components to the sense components is 4:3.

In some examples, the method may include biasing the gate of the transistor to the second voltage before transferring the charge between the digit line and the node, and discharging the memory cell onto the digit line based at least in part on biasing the gate of the transistor to the second voltage, wherein the digit line is biased to the first voltage based at least in part on discharging the memory cell onto the digit line. Further to this example, the method may include isolating the plurality of sense components from the digit line based at least in part on sensing the state of the memory cell, and storing a high-level state in the memory cell based at least in part on isolating the plurality of sense amplifiers from the digit line.

An apparatus is described. In some examples, the apparatus may support means for transferring, using a transistor, a charge between a digit line and a node coupled with a plurality of sense components during a read operation, wherein the charge is transferred based at least in part on a first voltage on the digit line being less than a second voltage on a gate of the transistor, means for sensing, by the plurality of sense components based at least in part on transferring the charge between the digit line and the node, a state of a memory cell that is configured to store three or more states, wherein a ratio of the number of states read by the plurality of sense components and a number of the plurality of sense components is greater than one, and means for determining the state of the memory cell based at least in part on the ratio being greater than one. The plurality of sense components comprises a first sense component and a second sense component that are each coupled with the node, further wherein the ratio of the number of states read by the plurality of sense components to the number of the plurality of sense components is 3:2.

In some examples, the apparatus may support means for sensing a signal at the first sense component by comparing the charge transferred to the node to a fixed reference value at a first time, wherein the transistor is configured to transfer the charge between the digit line and the node of the first sense component and the second sense component during the read operation and means for sensing the signal at the second sense component may include comparing the charge transferred to the node to the fixed reference value at a second time different than the first time.

In some examples, the apparatus may support means for sensing, using a third sense component coupled with the digit line using the transistor, the charge transferred to the node at a third time different than a second time based at least in part on sensing the charge transferred to the node at the second time, where determining the state of the memory cell comprises, sensing the charge at the third sense component. Additionally, the apparatus may support means for determining the states of the memory cell based at least in part on a ratio being four states read by the plurality of sense components to the three sense components.

In some examples, the apparatus may support means for biasing the gate of the transistor to the second voltage before transferring the charge between the digit line and the node, and means for discharging the memory cell onto the digit line based at least in part on biasing the gate of the transistor to the second voltage, wherein the digit line is biased to the first voltage based at least in part on discharging the memory cell onto the digit line. Further to this example, the apparatus may support means for isolating the plurality of sense components from the digit line based at least in part on sensing the state of the memory cell, and means for storing a high-level state in the memory cell based at least in part on isolating the plurality of sense amplifiers from the digit line.

An apparatus is described. The apparatus may include a memory cell coupled with a digit line and configured to store three or more states, a plurality of sense components coupled with a node, a transistor coupled with the node and the digit line, and a controller coupled with the memory cell. The controller may be operable to transfer, by the transistor, a charge between the digit line and the node, sense, by the plurality of sense components, a state of the memory cell based at least in part on transferring the charge between the digit line and the node, wherein a ratio of a number of states read by the plurality of sense components to a number of the plurality of sense components comprises a ratio of 3:2, and determine the state of the memory cell based at least in part on the ratio being 3:2. The controller may also be operable to couple, the plurality of sense components with the node, wherein the plurality of sense components comprises a first sense component, a second sense component, and a third sense component, wherein the plurality of sense components is configured to sense a signal caused by transferring the charge between the digit line and the node, and determine the state of the memory cell based at least in part on a ratio being four states read by plurality of sense components to three sense components.

In some examples, the apparatus may include a first reference line coupled with at least the first sense component and configured to transmit a first reference voltage to the first sense component and a second reference line coupled with the second sense component and configured to transmit a second reference voltage to the second sense component, wherein the second reference voltage is different than the first reference voltage. The plurality of sense components may include a first sense component coupled with the node and configured to sense a signal caused by transferring the charge between the digit line and the node, a second sense component coupled with the node and configured to sense the signal caused by transferring the charge between the digit line and the node, and a third sense component coupled with the node and configured to sense the signal caused by transferring the charge between the digit line and the node and the number of states read by the plurality of sense components is based at least on a ratio of four states to three sense components.

In some examples, the apparatus may include a second transistor coupled with a gate of the transistor and the node of the plurality of sense components, the second transistor configured to apply a first voltage to the gate of the transistor that compensates for a threshold voltage associated with the transistor, and a third transistor coupled with the node of the plurality of sense components and configured to isolate the plurality of sense components during at least a portion of a read operation. The apparatus may further include a write-back component coupled with at least the plurality of sense components and configured to write a value to the memory cell based at least in part on the plurality of sense components sensing the charge.

As used herein, the term “virtual ground” refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly coupled with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. “Virtual grounding” or “virtually grounded” means connected to approximately 0V.

The term “layer” used herein refers to a stratum or sheet of a geometrical structure. each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers may include different elements, components, and/or materials. In some cases, one layer may be composed of two or more sublayers. In some of the appended figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration. Those skilled in the art will, however, recognize that the layers are three-dimensional in nature.

As used herein, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough to achieve the advantages of the characteristic.