Address generating circuit and address generating method

An address generating circuit according to an embodiment includes a register that maintains a partition address set by a CPU, a comparator that determines whether a designated address designated by the CPU designates the interleaved area or the non-interleaved area, a selection signal generating unit that generates the selection signal based on a least significant bit of the designated address in a case of the interleaved area and generates the selection signal based on a high-order bit other than the least significant bit of the designated address in a case of the non-interleaved area, and a physical address generating unit that generates the physical address acquired by excluding the least significant bit from the designated address in a case of the interleaved area and generates the physical address acquired by excluding the high-order bit from the designated address in a case of the non-interleaved area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-284134, filed on Dec. 27, 2012; the entire contents of which are incorporated herein by reference.

FIELD

The present embodiment, generally, relates to an address generating circuit and an address generating method.

BACKGROUND

In flash memories, it is necessary to erase data in units of blocks before data is written, and it takes a long time to erase data with respect to an operating clock of the system. As a method for shortening the data erasure time, there are a method of simultaneously erasing data of a plurality of storage device banks and a method of hiding a erasure time by overlapping data erasures of a plurality of storage device banks in an interleaved mode. As the number of storage device banks for overlapping increases, a higher speed can be implemented. Also for reading a memory, by interleaving a plurality of storage device banks, the access time overlaps each other, whereby the processing can be performed at a higher speed.

DETAILED DESCRIPTION

An address generating circuit according to an embodiment of the present invention provides a bank selection signal representing a selection of a first bank or a second bank and a physical address for a non-volatile storage unit that includes the first bank and the second bank, alternately stores data of consecutive addresses in the first bank and the second bank in units of words in an interleaved area, and consecutively stores the data in the first bank or the second bank in a non-interleaved area up to a unit of a sector larger than a unit of the word. The address generating circuit according to the embodiment includes a register that maintains a partition address set by a CPU, a comparator that determines whether a designated address designates the interleaved area or the non-interleaved area based on the designated address designated by the CPU and the partition address, a bank selection signal generating unit that generates the bank selection signal based on a least significant bit of the designated address in a case where the comparator determines the interleaved area and generates the bank selection signal based on a high-order bit other than the least significant bit of the designated address in a case where the comparator determines the non-interleaved area, and a physical address generating unit that generates the physical address acquired by excluding the least significant bit from the designated address in a case where the comparator determines the interleaved area and generates the physical address acquired by excluding the high-order bit from the designated address in a case where the comparator determines the non-interleaved area.

Hereinafter, an address generating circuit and an address generating method according to an embodiment will be described with reference to the accompanying drawings. However, the present invention is not limited to this embodiment.

EMBODIMENT

In a system having an on-chip flash memory such as a SIM (Subscriber Identity Module) card, there is restriction on the chip size, and it is difficult for a large number of memories to be included on-chip. In addition, a case where data of a plurality of storage device banks is simultaneously erased, or a case where the number of data erasures is large incurs a problem of decreasing the life of the flash memory and a problem of increasing power consumption in a system used for a cellular phone requiring low power consumption. The number of erasures of a flash memory is not unlimited.

A time is required for a data erasure, and accordingly, as there are more storage device banks of which data can be simultaneously erased, the effect of interleaving increases. In a system in which data of a plurality of storage device banks may not be simultaneously erased, data needs to be erased in a serial manner for each bank in the interleaved mode, whereby the erasure time increases by that much, and the number of erasures increases. In a non-interleaved access mode, a data erasure may be performed for only one bank that is used. However, on the other hand, a read access can be made at a higher speed in the interleaved mode.

As data to be written into the flash memory, there are data for which a high-speed access is necessary and data that is frequently rewritten, which have different characteristics of data. However, by employing any one of the memory access modes, it is difficult to have compatibility with both characteristics.

In a memory system physically configured by a plurality of banks, there is a method for increasing the speed of a memory access by configuring a plurality of banks as an interleaved memory. In a flash memory, data needs to be erased in units of blocks before data is written, and accordingly, a very long time is required for a data erasure with respect to an operating clock of the system, whereby the power consumption increases during the data erasure. In a system having a flash memory such as an SIM card on-chip, a large number of flash memories may not be physically included, and erasing data of a plurality of flash memories has a problem from the viewpoint of low power consumption.

In a semiconductor system having a flash memory such as an SIM card on-chip, the address generating circuit according to this embodiment provides a partition function of the flash memory. From this, the interleaved mode emphasizing the access speed of the flash memory and the non-interleaved mode emphasizing the data erasure time are realized in a same system, and a semiconductor device having a function for setting the division of an interleaved access area and a non-interleaved access area to be programmable can be provided.

As illustrated inFIG. 1, a flash memory that is physically configured by two banks (bank0and bank1) is divided into an interleaved area1and a non-interleaved area2. The address at which the division is performed is a partition address3, and the division function is the partition function.

The flash memory is divided into blocks called sectors or pages, and the erasure of data is performed in units of sectors or pages. In a system in which accesses may not be made to both banks, the interleaved area1and the non-interleaved area2, as illustrated inFIG. 2, have mutually-different sizes of sectors or pages that are units of data erasing and data reading. Since the size of the sector or the page of the interleaved area1is twice as much as that of the non-interleaved area2, the data erasure time in the interleaved area is twice as much as that in the non-interleaved area.

For example, a read access or a write access to the flash memory may be performed only in units of a word (four bytes). The address input to the flash memory is a word address. Even word addresses of the interleaved area1are mapped into the bank0, and odd word addresses are mapped into the bank1. When consecutive word addresses are alternately accessed, the bank0and the bank1are alternately accessed in units of words. On the other hand, the non-interleaved area2is mapped into the banks0and1for each sector (4 K bytes). Addresses within a same sector are mapped into a same bank. The setting of the partition address3is set in units of 8 K bytes that form the unit of data erasing and data reading in the interleaved area1illustrated inFIG. 2.

FIG. 3illustrates an address generating circuit100generating a physical address that is input to a flash memory for implementing data storage as illustrated inFIG. 1in a system having the flash memory such as an SIM card on-chip. When the flash memory has a total of 1 M bytes, each one of the banks0and1is 512 K bytes, and a 17 bit address of a physical address is necessary in the case of an access to a word. HADDR[19:2]110is an access address that is output by a CPU10. This HADDR[19:2]110depends on the bus status and is transmitted to selectors41and42through a holding circuit5that holds address data when the bus is busy. A bank selection signal BANKSELECT101that is output from the selector41is a signal representing the selection of a specific bank. FADDR102that is output from the selector42is a physical address input to the flash memory (banks0and1).

In this embodiment, for example, a user determines a value desired as a partition address3such that data requiring a high-speed access is arranged in the interleaved area1, and data that is frequently rewritten is arranged in the non-interleaved area2. More specifically, for example, a value of a partition address3that is set by the user in advance is written into an OS (operating system) recorded in a ROM60or the flash memory (banks0and1), and the CPU10can write or read the value of the partition address3into or from a register20.

The register20sets the partition address3to a comparator30. For the selection of the interleaved area1or the non-interleaved area2, an access address (designated address) supplied from the CPU10and the partition address3maintained in the register20are compared by the comparator30. Then, for example, in a case where the access address is lower than the partition address3, an access to the interleaved area1is determined, and otherwise, an access to the non-interleaved area2is determined.

When it is determined that the access address corresponds to the interleaved area1or the non-interleaved area2, a physical address FADDR102and a bank selection signal BANKSELECT101can be determined. More specifically, the selectors41and42operate as below.

In a case where the access address is determined to correspond to the interleaved area1by the comparator30, the selector41notifies the banks0and1of NVADDR[0]106that is a least significant bit of the access address as the bank selection signal BANKSELECT101. On the other hand, in a case where the access address is determined to correspond to the non-interleaved area2, the selector41notifies the banks0and1of NVADDR[10]107that is the value of the 10-th bit that is a bit having order higher than that of the access address as the bank selection signal BANKSELECT101. The reason for using the value of the 10-th bit of the access address is that this bit is a bit representing conversion for every 4 K bytes that correspond to a data amount of the sector unit in the non-interleaved area2. Accordingly, in a case where the non-interleaved area2is determined, the digit of the access address of which the banks0and1are notified as the bank selection signal BANKSELECT101depends on the amount of data in the unit of a sector that is consecutively written in the non-interleaved area2and is not necessarily limited to the 10-th bit.

In a case where the access address is determined to correspond to the interleaved area1by the comparator30, the selector42notifies the banks0and1of NVADDR[17:1]104acquired by extracting NVADDR[0]106, which is used as the bank selection signal BANKSELECT101, from the access address as the physical address FADDR102. On the other hand, in a case where the access address is determined to correspond to the non-interleaved area2, the selector42notifies the banks0and1of {NVADDR[17:11], NVADDR[9:0]}105acquired by extracting NVADDR[10]107, which is used as the bank selection signal BANKSELECT101, from the access address as the physical address FADDR102.

FIG. 4is a block diagram that illustrates the functional configuration of the address generating circuit100illustrated inFIG. 3. While a register20and a comparator30included in the address generating circuit100are the same as those illustrated inFIG. 3, a bank selection signal generating unit51is a functional block that is implemented by the holding circuit5and the selector41illustrated inFIG. 3, and a physical address generating unit52is a functional block that is implemented by the holding circuit5and the selector42illustrated inFIG. 3.

In a system having a flash memory such as an SIM card on-chip, in order for the CPU10to actually perform data reading and data writing for the banks0and1by designating an access address, in addition to the address generating circuit100illustrated inFIG. 4, a read line300(bus) and a write line200(bus) as illustrated inFIG. 5are arranged in the banks0and1, and data that is actually to be read or written is transmitted using the read line and the write line.

According to this embodiment, depending on the purpose of a user using the system, the division sizes of the interleaved area and the non-interleaved area can be set to be programmable. Data having a low rewriting frequency such as a command code is arranged in the interleaved area, whereby a high-speed read access thereto can be made. On the other hand, data having a high rewriting frequency is written into the non-interleaved area, whereby the data erasure time can decrease. Accordingly, by properly using the interleaved area and the non-interleaved area in accordance with the characteristics of data to be written, the processing time can be shortened.