Semiconductor device and method of fabricating the same

Provided are semiconductor devices and methods of fabricating the same. The device may include lower interconnection lines, upper interconnection lines crossing the lower interconnection lines, selection elements disposed at intersections, respectively, of the lower and upper interconnection lines, and memory elements interposed between the selection elements and the upper interconnection lines, respectively. Each of the selection elements may be realized using a semiconductor pattern having a first sidewall, in which a first lower width is smaller than a first upper width, and a second sidewall, in which a second lower width is greater than a second upper width, the first and second sidewalls crossing each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2011-0073542, filed on Jul. 25, 2011, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The general present general inventive concepts relate to a semiconductor device, and more particularly, to a semiconductor device with a high integration density and a method of fabricating the same.

2. Description of the Related Art

Higher integration of semiconductor memory devices is required to satisfy the increasing demands of the electronic industry. A Down-scaling is an important and effective way for achieving the higher integration of semiconductor memory devices and reducing the fabricating cost.

Hole-type etching processes have been used to form holes in interlayer dielectrics of the semiconductor device, which are used by components as contact points. However, this may lead to several problems, such as a decrease in process margin and/or an increasing difficulty in optimizing all components (e.g., various driving circuits and/or memory cells) constituting the semiconductor device.

SUMMARY

At least one exemplary embodiment provides a method of fabricating a semiconductor device having an increased integration density and an improved operation property.

According to example embodiments of the present general inventive concepts, a semiconductor device may include lower interconnection lines, upper interconnection lines crossing the lower interconnection lines, selection elements disposed at intersections, respectively, of the lower and upper interconnection lines, and memory elements interposed between the selection elements and the upper interconnection lines, respectively. Each of the selection elements may be realized using a semiconductor pattern having a first sidewall, in which a first lower width is smaller than a first upper width, and a second sidewall, in which a second lower width is greater than a second upper width, the first and second sidewalls crossing each other.

According to other example embodiments of the present general inventive concepts, a method of fabricating a semiconductor device may include forming mold patterns on a semiconductor substrate, the mold patterns extending along a direction to define first trenches exposing the semiconductor substrate, forming semiconductor layers to fill the first trenches, and forming second trenches crossing the mold patterns and the semiconductor layers to form semiconductor patterns two-dimensionally arranged on the semiconductor substrate.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference will now be made in detail to exemplary embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The exemplary embodiments are described below in order to explain the present general inventive concept while referring to the figures.

Hereinafter, a phase changeable random access memory (PRAM) device will be described as an example of semiconductor devices according to example embodiments of the present general inventive concept, but example embodiments of the present general inventive concept may not be limited thereto. For example, the present general inventive concept may be used to realize other variable resistance memory devices, such as a resistive memory device (RRAM), a magnetic RAM (MRAM), and a ferroelectric RAM (FRAM). Furthermore, the present general inventive concept may be used to realize a dynamic RAM (DRAM), a static RAM (SRAM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a FLASH memory device.

FIG. 1is a block diagram of a semiconductor device according to example embodiments of the present general inventive concept.

Referring toFIG. 1, a semiconductor device may include a memory cell array1and peripheral circuits controlling the memory cell array1.

The memory cell array1may include a plurality of memory blocks BLK0-BLKn, and each of the memory blocks BLK0-BLKn may include a plurality of memory cells storing data, a plurality of word lines and bit lines.

The peripheral circuits may include a row decoder2, a data input/output circuit3, and a column decoder4. The row decoder2may be configured to be able to select one of the memory blocks BLK0-BLKn of the memory cell array1and/or to be able to select one word line of the selected memory block, based on a given address information. The data input/output circuit3may be configured to store data in the memory cells or read out data from the memory cells. The column decoder4may be configured to select at least one of the bit lines in the selected memory block and serve as a path for transmitting data between the data input/output circuit3and an external device (for example, a memory controller). In some exemplary embodiments, the peripheral circuits may further include a logic circuit and a voltage generator.

FIG. 2is a schematic circuit diagram of a memory cell array of a semiconductor device according to example embodiments of the present general inventive concept.

Referring toFIG. 2, a memory cell array may include a plurality of word lines WL1-WLm, a plurality of bit lines BL1-BLn, and a plurality of memory cells MC. The memory cells MC may be disposed at intersections between the word lines WL1-WLm and the bit lines BL1-BLn, respectively.

In some exemplary embodiments, each of the memory cells MC may include a memory element Rp and a selection element D. The memory element Rp may be interposed between one of the bit lines BL1-BLn and the selection element D, and the selection element D may be interposed between the memory element Rp and one of the word lines WL1-WLm.

In some exemplary embodiments, the memory element Rp may be a variable resistance element whose resistance can be varied in two or more levels by an electric pulse applied thereto. For example, the memory element Rp may include a phase changeable material whose crystal structure can be controlled by an amount of electric current. The phase changeable material may be at least one of chalcogenides including at least one of antimony (Sb), tellurium (Te), or selenium (Se). For example, the memory element Rp may be at least one of GaSb, InSb, InSe, Sb2Te3, GeTe, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe, AgInSbTe, (GeSn)SbTe, GeSb(SeTe), or Te81Ge15Sb2S2.

The phase changeable material may be a material whose crystalline structure or electric resistance can be reversibly transferred to a high resistive amorphous state and a low resistive crystallized state by controlling Joule's heat generated therein. For example, a state or phase of the phase changeable material can be reversibly changed by controlling temperature and cooling time thereof, and this phase changing mechanism can be used to write data to the memory element Rp.

In other exemplary embodiments, the memory element Rp may include at least one of perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials.

The selection element D may control an electric current between the memory element Rp and one of the word lines WL1-WLm, depending on a voltage of the corresponding word line WL1-WLm.

In some exemplary embodiments, the selection element D may be configured to form a PN junction diode or a PIN junction diode. For instance, an anode of the diode may be connected to the memory element Rp and a cathode of the diode may be connected to one of the word lines WL1-WLm. In this case, if a voltage difference between the anode and cathode is higher than a threshold voltage of the diode, the diode will be in the “on” state and an electric current can be supplied to the memory element Rp.

In other exemplary embodiments, the selection element D may be a metal-oxide-semiconductor (MOS) transistor. For example, the selection element D may be a NMOS transistor whose gate electrode is connected to one of the word lines WL1-WLm. In other words, voltages applied to the word lines WL1-WLm can be used to control an electric current flowing through the memory element Rp.

In still other exemplary embodiments, the selection element D may be a PNP or NPN bipolar transistor (BJT).

FIGS. 3 through 10are perspective views illustrating a method of fabricating a semiconductor device according to example embodiments of the present general inventive concepts, andFIG. 11is a perspective view illustrating a method of fabricating a semiconductor device according to modified exemplary embodiments of the inventive concept.

Referring toFIG. 3, a semiconductor substrate100may be prepared to include a plurality of cell array regions10and a contact region20interposed between the cell array regions10.

The semiconductor substrate100may extend along a lengthwise direction that defines a length of the semiconductor device and a widthwise direction that defines a width of the semiconductor device. Further, the semiconductor substrate100may be formed of a single-crystalline semiconductor material. For example, the semiconductor substrate100may be one of a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxially grown substrate.

Device isolation patterns110may be formed to define active regions in the semiconductor substrate100. In some exemplary embodiments, the device isolation patterns110and the active regions may have a linear shape extending along a direction of y-axis.

The formation of the device isolation patterns110may include patterning the semiconductor substrate100to form device isolation trenches delimiting the active regions, and filling the device isolation trenches with an insulating material. The formation of the device isolation trenches may include forming a device isolation mask (not shown) delimiting the active regions on the semiconductor substrate100and then anisotropically etching the semiconductor substrate100using the device isolation mask as an etch mask.

The device isolation patterns110may be formed of at least one of silicon oxide or low-k dielectrics (for example, having a lower dielectric constant than silicon oxide). In addition, the formation of the device isolation patterns110may further include a liner structure (not shown) covering inner walls of the device isolation trenches. The liner structure may include a thermal oxide layer, which may be formed by thermally oxidizing the inner walls of the device isolation trenches, and a nitride liner conformally covering the structure provided with thermal oxide layer.

In some exemplary embodiments, before or after the formation of the device isolation patterns110, lower interconnection lines105serving as the word lines WL1-WLm ofFIG. 2may be formed in the active regions of the semiconductor substrate100. The lower interconnection lines105may have a linear shape extending along the direction of the y-axis. The lower interconnection lines105may be formed between the device isolation patterns110.

The lower interconnection lines105may be doped regions formed by doping the semiconductor substrate100with impurities. In some exemplary embodiments, the lower interconnection lines105may be formed to have a conductivity type different from a conductivity type of the semiconductor substrate100. For example, when the semiconductor substrate100is a p-type, the lower interconnection lines105may be formed by injecting n-type impurities of high concentration into the semiconductor substrate100. Alternatively, the lower interconnection lines105may be formed of a metallic material.

Referring toFIG. 4, mold patterns120may be formed on the semiconductor substrate100to define first trenches301.

The formation of the mold patterns120may include sequentially stacking an etch stop layer121and a first insulating layer123on the semiconductor substrate100, forming a first mask pattern (not shown) having a line-and-space shape on the first insulating layer123, and then, anisotropically etching the first insulating layer123and the etch stop layer121using the first mask pattern as an etch mask to expose a top surface of the semiconductor substrate100.

The etch stop layer121may be formed of oxide, nitride and/or oxynitride. The first insulating layer123may be formed of at least one selected from the group consisting of borosilicate glass (BSG), phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), high density plasma (HDP) materials. Alternatively, the first insulating layer123may be formed of at least one of low-k dielectrics having a lower dielectric constant than silicon oxide. The etch stop layer121may be formed to have a thickness ranging from several tens to several hundreds of angstroms, and the first insulating layer123may be formed to have a thickness ranging from several hundred to several thousand of angstroms.

The mold patterns120may be formed on the device isolation patterns110to have a linear shape extending along the direction of the y-axis. The first trenches301may be formed to expose the top surface of the semiconductor substrate100. In some exemplary embodiments, the first trenches301may expose surfaces of the lower interconnection lines105. As a result of the anisotropic etching process, the first trenches301may have a bottom width smaller than a top width. In addition, the maximum width of the first trenches301may be smaller than a minimum feature size. Hereinafter, the minimum feature size refers to a minimum pattern width that can be printed by a photolithography system.

The first trenches301may be performed to completely remove the etch stop layer121from the top surface of the semiconductor substrate100, for example, in an over-etching manner. In this case, a surface of the semiconductor substrate100exposed by the first trenches301may be damaged. The surface damage of the semiconductor substrate100may lead to crystal defects of semiconductor layers130(ofFIG. 5), which will be formed by a selective epitaxial growth process. However, according to example embodiments of the present general inventive concept, a cleaning process may be performed after the formation of the first trenches301to cure the surface of the semiconductor substrate100exposed by the first trenches301. The cleaning process may be performed using a basic cleaning solution containing ammonia water, hydrogen peroxide water, and water.

Referring toFIG. 5, semiconductor layers130may be formed to fill the first trenches301. As a result, the semiconductor layers130may have a linear shape.

In some exemplary embodiments, the semiconductor layers130may be formed by a selective epitaxial growth (SEG) process, in which the semiconductor substrate100exposed by the mold patterns120are used as a seed layer. As a result, the semiconductor layers130may have a single-crystalline structure substantially, like the semiconductor substrate100.

In other exemplary embodiments, the semiconductor layers130may be formed using a solid phase epitaxial process. For example, the formation of the semiconductor layers130may include depositing an amorphous or polycrystalline semiconductor layer to fill the first trenches301, and then, crystallizing the amorphous or polycrystalline semiconductor layer.

In still other exemplary embodiments, the semiconductor layers130may be formed using a laser-induced epitaxial growth process. For example, the formation of the semiconductor layers130may include crystallizing an amorphous semiconductor layer provided in the first trenches301using a laser beam such as an excimer laser.

The semiconductor layers130may be grown over top surfaces of the mold patterns120. In this case, the semiconductor layers130may be planarized to have flat top surfaces, after the growth of the semiconductor layers130.

The semiconductor layers130may be in direct contact with the semiconductor substrate100or the lower interconnection lines105, in the first trenches301. Each of the semiconductor layers130may have a linear shape extending parallel to the mold patterns120. Each of the semiconductor layers130may have sidewalls in contact with inner walls of the first trenches301and have a lower portion narrower than an upper portion. In addition, the maximum width of the semiconductor layer130may be smaller than the minimum feature size.

The semiconductor layers130may be formed of a material containing silicon (Si) and/or germanium (Ge). The semiconductor layers130may be formed to have one of single-crystalline, amorphous, and polycrystalline structures. In some exemplary embodiments, there may be interfacial surfaces having a discontinuous crystal structure between the semiconductor substrate100and the semiconductor layers130.

Referring toFIG. 6, a partial view of the semiconductor substrate100is illustrated. Second trenches302may be formed to cross the mold patterns120and the semiconductor layers130. For example, the second trenches302may extend along the direction of the x-axis.

The formation of the second trenches302may include forming a second mask pattern (not shown) having a line-and-space shape to cross the mold patterns120and the semiconductor layers130, and then, anisotropically etching the mold patterns120and the semiconductor layers130using the second mask pattern as an etch mask.

In some exemplary embodiments, the second trenches302may be formed to expose the top surface of the semiconductor substrate100. For example, the second trenches302may be formed to expose portions of the lower interconnection lines105and/or portions of the etch stop layer121.

As a result of the anisotropic etching process, the second trenches302may have a bottom width smaller than a top width. In addition, portions of the semiconductor substrate100exposed by the second trench302may be recessed to have a vertical level lower than other portions of the semiconductor substrate100covered with the semiconductor pattern135.

As a result of the formation of the second trenches302, the semiconductor layers130may be cut to form semiconductor patterns135two-dimensionally arranged on the semiconductor substrate100.

Similarly, the first insulating layers123may be cut to form first insulating patterns125two-dimensionally arranged on the semiconductor substrate100. Each of the first insulating patterns125may be interposed between the corresponding one of pairs of the semiconductor patterns135adjacent to each other in the direction of the x-axis. The first insulating patterns125have an inverse shape with respect to the shape of the semiconductor patterns135. More specifically, the semiconductor patterns135include an upper portion and a lower portion that is smaller than the upper portion. The insulating patterns125have an upper portion and a lower portion that is greater than the upper portion. Accordingly, the insulating patterns125are inversely shaped with respect to the semiconductor patterns135.

The semiconductor patterns135may have first sidewall surfaces135adelimited by the first trenches301and second sidewall surfaces135bdelimited by the second trenches302. For each of the semiconductor patterns135, if a first lower width W1and a first upper width W2are measured in a vertical section parallel to the direction of the x-axis as shown inFIG. 12, the first lower width W1may be smaller than the first upper width W2. Furthermore, for each of the semiconductor patterns135, if a second lower width L1and a second upper width L2are measured in a vertical section parallel to the direction of the y-axis, the second upper width L2may be smaller than the second lower width L1. In the direction of the y-axis, the maximum width of the semiconductor pattern135may be smaller than the minimum feature size.

The semiconductor pattern135may have substantially a irregular quadrilateral polyhedron shape, because it is cut by the first and second trenches301and302crossing each other.

According to a modified exemplary embodiment depicted inFIG. 11, the formation of the second trenches302may include anisotropically and partially etching the mold patterns120and the semiconductor layers130. For example, the second trenches302may be formed to remain portions of the mold patterns120and portions of the semiconductor layers130thereunder. As a result, upper portions of the semiconductor patterns135may be two-dimensionally arranged on the semiconductor substrate100and lower portions of the semiconductor patterns135may be connected with each other via connecting portions133. Here, the connecting portions133may be or include portions of the semiconductor patterns135remaining under the second trenches302.

Referring toFIGS. 6 and 11, second trenches302may be formed to define pad semiconductor patterns137, which may be provided on the contact region20. For example, the pad semiconductor patterns137may be delimited by a pair of the second trenches302that are provided between the cell array regions10and the contact region20. In the direction of the y-axis, a width of the pad semiconductor pattern137may be greater than that of the semiconductor pattern135. In the direction of the x-axis, a wide of the pad semiconductor pattern137may be substantially equivalent to that of the semiconductor pattern135. An x-axis directional width of the pad semiconductor pattern137may be smaller in an upper portion than in a lower portion, and a y-axis directional width of the pad semiconductor pattern137may be smaller in the lower portion than in the upper portion.

According to an example depicted inFIG. 13, the semiconductor layers130may be removed from the contact region20, during forming the second trenches302. As a result, the semiconductor patterns135may be two-dimensionally arranged on the cell array regions10, and top surfaces of the lower interconnection lines105and the device isolation patterns110may be exposed in the contact region20.

Referring toFIG. 7, second insulating patterns140may be formed to fill the second trenches302. Each of the second insulating patterns140may extend along the direction of the x-axis and cover the second sidewalls135bof the semiconductor patterns135.

The formation of the second insulating patterns140may include filling the second trenches302with an insulating material and planarizing the insulating material to expose top surfaces of the first insulating patterns125and the semiconductor patterns135.

The second insulating patterns140may be formed of at least one silicon oxide material, such as borosilicate glass (BSG), phosphosilicate glass (PSG), boro-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), or high density plasma (HDP) oxides. Alternatively, the second insulating patterns140may be formed of at least one of low-k dielectrics having a lower dielectric constant than silicon oxide.

Next, an upper doped region135pand a lower doped region135nmay be formed in each of the semiconductor patterns135.

The lower and upper doped regions135nand135pmay have different conductivity types from each other. For example, the upper doped regions135pmay be formed by injecting p-type impurities into upper portions of the semiconductor patterns135, and the lower doped regions135nmay be formed by injecting n-type impurities into lower portions of the semiconductor patterns135. The p-type impurities include, but are not limited to, boron, and the n-type impurities include, but are not limited to, phosphorus. In addition, the lower and upper doped regions135nand135pmay be formed to be in contact with each other, and in some exemplary embodiments, a p-type impurity concentration of the upper doped region135pmay be higher than an n-type impurity concentration of the lower doped region135n.

The lower and upper doped regions135nand135p, formed in each of the semiconductor patterns135, may form a PN junction diode capable of serving as a rectifying element. The semiconductor patterns135may also form a PIN junction diode, which includes a doped intrinsic semiconductor region between a p-type semiconductor and an n-type semiconductor region.

During the formation of the upper and lower doped regions135pand135n, upper and lower pad doped pad regions137pand137nmay be formed in each of the pad semiconductor patterns137. In at least one exemplary embodiment, the upper doped pad region137pmay be positively doped to form a p-type semiconductor pad region, and the lower doped pad region137nmay be negatively doped to form a n-type semiconductor pad region. It can be appreciated, however, that the pad semiconductor patterns137are not limited to the doping arrangements of the pad regions137p,137ndescribed above.

Referring toFIG. 8, lower electrodes150may be formed on the semiconductor patterns135, respectively.

The formation of the lower electrodes150may include forming a first interlayer dielectric145on the semiconductor patterns135, pattering the first interlayer dielectric145to form openings, each of which exposes a top surface of the corresponding one of the semiconductor patterns135, and then, forming lower electrodes150in the openings.

The first interlayer dielectric145may be formed of at least one of boro-phosphosilicate glass (BPSG), high density plasma (HDP) oxides, tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), or silazene-based materials (such as, Tonen Silazene (TOSZ)). The first interlayer dielectric145may be formed using a deposition technique providing a good step coverage property, such as a chemical vapor deposition (CVD) or an atomic layer deposition (ALD). After the formation of the first interlayer dielectric145, a planarization process, such as a chemical-mechanical polishing (CMP) or etch-back process, may be performed to make a top surface of the first interlayer dielectric145as flat as possible.

In some exemplary embodiments, the lower electrodes150may be formed in the openings, each of which is formed through the first interlayer dielectric145. In an inner wall of the opening, a spacer (not shown) may be formed to reduce a top area of the lower electrode150.

Alternatively, an ohmic layer141may be formed on the top surfaces of the semiconductor patterns135before forming the lower electrodes150(for example, before forming the first interlayer dielectric145.

The ohmic layer141may be formed by reacting the top surfaces of the semiconductor patterns135with a metallic material. In this case, the ohmic layer141may be formed of a metal silicide layer (e.g., of cobalt silicide, titanium silicide, nickel silicide or tungsten silicide).

Referring toFIG. 9, memory elements160and upper interconnection lines170may be formed on the lower electrodes150.

For instance, a second interlayer dielectric165may be formed on the first interlayer dielectric145provided with the lower electrodes150. The second interlayer dielectric165may be formed to have openings exposing the top surfaces of the lower electrodes150and crossing the lower interconnection lines105or the first trenches301. Memory elements160may be formed in the openings of the second interlayer dielectric165, respectively. For instance, each of the memory elements160may be formed to have a linear shape crossing the lower interconnection lines105. Alternatively, each of the memory elements may be formed parallel to the lower interconnection lines105. In other exemplary embodiments, the memory elements160may be two-dimensionally arranged on the semiconductor substrate100. For instance, each of the memory elements160may be disposed on the corresponding one of the semiconductor patterns135.

In some exemplary embodiments, the memory elements160may include at least one of variable resistance materials, whose resistance can be selectively changed using an electric current flowing therethrough. For example, the memory elements160may include at least one of phase changeable materials, whose crystallographic structure can be reversibly switched between a high-resistance amorphous state and a low-resistance crystalline state, using the Joule-heating effect. The phase changeable materials may be chalcogenide materials that contain at least one of antimony (Sb), tellurium (Te), or selenium (Se).

For example, the phase changeable materials may be at least one of chalcogenides (such as Ge—Sb—Te, As—Sb—Te, As—Ge—Sb—Te, Sn—Sb—Te, Ag—In—Sb—Te, In—Sb—Te, 5A group element-Sb—Te, 6A group element-Sb—Te, 5A group element-Sb—Se, 6A group element-Sb—Se, Ge—Sb, In—Sb, Ga—Sb, or Ge—Sb—Te doped with C, N, B, Bi, Si, P, Al, Dy or Ti). The phase changeable materials may be formed using PVD or CVD. In the case in which the memory elements160include a phase changeable material, a capping electrode layer (not shown) may be formed on the phase changeable material, before patterning the phase changeable material to form the memory elements160.

In other exemplary embodiments, the memory elements160may include a layered structure whose electric resistance can be changed using a spin-polarized current or a spin torque transfer mechanism. For example, the memory elements160may be configured to have a magneto-resistance property and include at least one ferromagnetic material and/or at least one antiferromagnetic material. In still other exemplary embodiments, the memory elements160may include at least one of perovskite compounds or transition metal oxides.

The upper interconnection lines170may be formed on the memory elements160to cross the lower interconnection lines105(for example, parallel to the direction of the x-axis). In some exemplary embodiments, the upper interconnection lines170may be formed to be substantially parallel to the memory elements160.

Referring toFIG. 10, strapping interconnection lines190may be formed on the upper interconnection lines170.

The strapping interconnection lines190may be formed by stacking a metal conductive layer on the third interlayer dielectric175and then patterning the metal conductive layer. The strapping interconnection lines190may extend along the direction of the y-axis and be substantially parallel to the lower interconnection lines105. The strapping interconnection lines190may be electrically connected to the lower interconnection lines105via the contact plugs180.

In some exemplary embodiments, the formation of the contact plugs180may include forming contact holes to penetrate the first to third interlayer dielectrics145,165and175, and then depositing a metallic layer in the contact holes. The contact holes may be inserted into the pad semiconductor pattern137. For example, the contact holes may be formed using an anisotropic etching process to expose the lower pad doped regions137nthrough the upper pad doped region137p. As a result, the contact plugs180may be electrically connected to the lower pad doped regions137n. In some exemplary embodiments, before the formation of the contact plugs180, an insulating layer185may be formed to surround an outer sidewall of the contact plug180. Due to the presence of the insulating layer185, it is possible to prevent the contact plugs180from being electrically connected to the upper pad doped region137p. Since the pad semiconductor patterns137are formed on the semiconductor substrate100, an aspect ratio of the contact plug180can be reduced, for example, compared with the case depicted inFIG. 13.

The strapping interconnection lines190and the contact plugs180may be formed of metallic materials. For example, the strapping interconnection lines190and the contact plugs180may include at least one of conductive metal nitrides, metals, and conductive carbon compounds. In some exemplary embodiments, the strapping interconnection lines190and the contact plugs180may include at least one selected from the group consisting of TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, W, Mo, Ta, TiSi, TaSi, TiON, TiAlON, WON, TaON, and conductive carbon compounds.

As shown inFIG. 13, in the case in which the pad semiconductor pattern137is not provided in the contact region20, the contact plugs180may be in direct contact with the top surface of the lower interconnection line105.

FIG. 12is an enlarged perspective view of a semiconductor device according to example exemplary embodiments of the present general inventive concepts, andFIG. 13is an enlarged perspective view of a semiconductor device according to modified exemplary embodiments of the present general inventive concepts. Hereinafter, the semiconductor device fabricated by the afore-described method will be described with reference toFIGS. 10,12and13.

Referring toFIGS. 10 and 12, the semiconductor device may include the semiconductor substrate100, the lower interconnection lines105on the semiconductor substrate100, the upper interconnection lines170crossing the lower interconnection lines105, the selection elements disposed at intersections, respectively, of the lower and upper interconnection lines105and170, and the memory elements160interposed between the selection elements and the upper interconnection lines170. The selection elements may be two-dimensionally arranged on the semiconductor substrate100to control a flow of electric current passing through the memory elements160.

The lower interconnection lines105may be shaped like a line extending along the direction of the y-axis. In some exemplary embodiments, the lower interconnection lines105may be doped regions formed by doping the semiconductor substrate100with impurities. The lower interconnection lines105may have a conductivity type different from a conductivity type of the semiconductor substrate100.

The selection elements may include the semiconductor patterns135fabricated by the afore-described method. Each of the semiconductor patterns135may include the upper and lower doped regions135pand135nthat may have conductivity types different from each other. For example, the upper doped region135pmay be positively doped to form a p-type semiconductor region, and the lower doped region135nmay be negatively doped to form a n-type semiconductor region. Further, the lower doped region135nmay have a conductivity type that is the same as the conductivity type of the lower interconnection lines105, and the upper doped region135pmay have a conductivity type different from the conductivity type of the lower doped region135n. As a result, each of the semiconductor patterns135may include a PN junction consisting of the upper and lower doped regions135pand135n. Alternatively, an intrinsic region may be interposed between the upper and lower doped regions135pand135n, thereby forming a PIN junction diode in the semiconductor pattern135.

Along the direction of the z-axis, the lower doped region135nand the lower interconnection line105may be interposed between the upper doped region135pand the semiconductor substrate100. In some aspects, it can be said that the semiconductor substrate100, the upper and lower doped regions135pand135n, and the lower interconnection line105form a PNP or NPN bipolar transistor.

According to the afore-described fabricating method, the semiconductor patterns135may be cut by the first and the second trenches301and302. In other words, the semiconductor patterns135may be spaced apart from each other in both of the directions of the x- and y-axes or be two-dimensionally arranged on the semiconductor substrate100.

Referring toFIG. 12, each of the semiconductor patterns135may have the first sidewall surfaces135adelimited by the first trenches301to face each other and the second sidewall surfaces135bdelimited by the second trenches302to face each other. Each of the semiconductor patterns135may have top or bottom surfaces with a substantially rectangular shape.

For each of the semiconductor patterns135, if a first lower width W1and a first upper width W2are measured in a vertical section parallel to the direction of x-axis or are given by as distances between the first sidewall surfaces135a, the first lower width W1may be smaller than the first upper width W2.

Furthermore, for each of the semiconductor patterns135, if a second lower width L1and a second upper width L2are measured in a vertical section parallel to the direction of y-axis or are given by distances between the second sidewall surfaces135b, the second upper width L2may be smaller than the second lower width L1.

In other exemplary embodiments, as shown inFIG. 11, the connecting portions133may be formed on the lower interconnection lines105to be substantially parallel to the lower interconnection lines105and connect the lower portions of the semiconductor patterns135with each other. A top surface of the connecting portion133may be closer to the semiconductor substrate100than an interfacial boundary between the upper and lower doped regions135pand135nor an interface whose net concentration of impurity is zero.

Referring again toFIG. 10, the first insulating patterns125may be interposed between the semiconductor patterns135, respectively, which are adjacent to each other in the direction of x-axis. The second insulating patterns140may be interposed between the semiconductor patterns135adjacent to each other in the direction of y-axis, and moreover, the second insulating patterns140may extend between the first insulating patterns125adjacent to each other in the direction of y-axis. In other words, the semiconductor patterns135may be surrounded by the first and second insulating patterns125and140. In some exemplary embodiments, the top surfaces of the semiconductor patterns135may be coplanar with those of the first and second insulating patterns125and140.

The lower electrodes150, the memory elements160, and the upper interconnection lines170may be disposed on the semiconductor patterns135.

In some exemplary embodiments, each of the memory elements160may be substantially parallel to the upper interconnection lines170and be connected to a plurality of the lower electrodes150. Alternatively, the memory elements160may be two-dimensionally arranged. In other words, each of the memory elements160may be disposed on the corresponding one of the semiconductor patterns135. As described above, the memory elements160may be formed of a variable resistance material whose resistance can be selectively changed using an electric current flowing therethrough. For example, the memory element160may include at least one of phase changeable materials whose crystallographic structure can be reversibly switched between a high-resistance amorphous state and a low-resistance crystalline state. Alternatively, the memory element160may include at least one of perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, antiferromagnetic materials and/or ferroelectric material.

Each of the lower electrodes150may be disposed between the corresponding one of the semiconductor patterns135and the corresponding one of the memory elements160. A horizontal area of the lower electrode150may be smaller than that of the semiconductor pattern135or the memory element160.

In some exemplary embodiments, the lower electrodes150may be shaped like a pillar. However, a shape of the lower electrode150may be variously modified in such a way that the lower electrode150can have a reduced area in a horizontal section. For example, a vertical section of the lower electrode150may be shaped like a letter “U”, a letter “L”, a hollow cylinder, a ring, or a cup.

The ohmic layer141may be interposed between the lower electrodes150and the semiconductor patterns135to reduce a contact resistance therebetween. For example, the ohmic layer141may be formed of a metal silicide layer (e.g., of titanium silicide, cobalt silicide, tantalum silicide, nickel silicide or tungsten silicide).

The upper interconnection lines170may be disposed on the memory elements160to cross the lower interconnection lines105and be electrically connected to the memory elements160.

In some exemplary embodiments, the semiconductor substrate100may include the contact region20interposed between the cell array regions10. The strapping interconnection lines190may be disposed to cross the upper interconnection lines170and the contact region20. The strapping interconnection lines190may be electrically connected to the lower interconnection lines105via the contact plugs180provided in the contact region20.

The strapping interconnection lines190may be substantially parallel to the lower interconnection lines105. The strapping interconnection lines190and the contact plugs180may be formed of metallic materials, and this suppresses a signal delay, which may be caused by a relatively high electric resistance of the lower interconnection line,105, from occurring. According to example embodiments of the present general inventive concepts, each of the cell array regions10includes a plurality of memory cells that are arranged along the direction of the y-axis and are connected to the corresponding one of the lower interconnection lines105. The lower interconnection lines105are connected to the strapping interconnection lines190via the contact plugs180in the contact region20interposed between the cell array regions10. In other words, the lower interconnection lines105may be electrically connected to the strapping interconnection lines190in the middle of the lower interconnection lines105. This enables suppression of a signal delay in word lines.

In the example depicted inFIG. 10, the pad semiconductor patterns137may be formed on the contact region20of the semiconductor substrate100. The contact plugs180may penetrate upper portions of the pad semiconductor patterns137to be connected to the lower doped region137n.

In the example depicted inFIG. 13, the pad semiconductor pattern137may not be formed in the contact region20. In this case, the contact plugs180may be directly connected to the lower interconnection lines105in the contact region20.

FIGS. 14 through 18are perspective views illustrating a method of fabricating a semiconductor device according to other example embodiments of the present general inventive concepts. For concise description, a previously described element may be identified by an identical reference number without repeating an overlapping description thereof.

Referring toFIG. 14, the mold patterns120and semiconductor layers131extending along the direction of the y-axis may be formed on the semiconductor substrate100, as described with reference toFIGS. 3 through 5.

The mold patterns120may be formed by patterning the etch stop layer121and the first insulating layer123sequentially stacked on the semiconductor substrate100. The semiconductor layers131may be an epitaxial layer grown using the semiconductor substrate100exposed by the mold patterns120as a seed layer.

According to at least one exemplary embodiment, top surfaces of the semiconductor layers131may be etched to form recess regions303exposing upper inner walls of the first trenches301. The recess regions303may be shaped like a line or bar extending along the direction of the y-axis. The recess regions303may be formed by etching the semiconductor layers131using an etching method having an etch selectivity with respect to the mold patterns120.

Referring toFIG. 15, a lower electrode layer151may be formed in the recess regions303. The formation of the lower electrode layer151may include depositing a conductive layer to cover conformally inner walls of the recess regions303, and then planarizing the conductive layer to expose the top surfaces of the mold patterns120.

The lower electrode layer151may be formed using a deposition process, such as an atomic layer deposition (ALD), a metal organic chemical vapor deposition (MO-CVD), a thermal CVD, a biased CVD, a plasma CVD, and an ECR CVD. In addition, the lower electrode layer151may have a thickness ranging from about 0.1 nm to about 30 nm.

After the deposition of the conductive layer, a capping insulating layer153may be formed on the conductive layer to fill the recess region303. The capping insulating layer153may be etched during the planarization of the conductive layer to expose the top surfaces of the mold patterns120. The capping insulating layer153may be formed of at least one selected from the group consisting of, for example, SiO2, SiN, PE-SiN, SiON, C, ALD-AlN, GeN, Al2O3, MgO, SiO2, CaO, Y2O3, TiO2, Cr2O3, FeO, CoO, ZrO and CuO2.

Before the formation of the lower electrode layer151, the ohmic layer141may be formed on the top surfaces of the semiconductor layers131exposed by the recess region303. The ohmic layer141may be formed by reacting the top surfaces of the semiconductor layers131with a metallic material. In this case, the ohmic layer141may be formed of a metal silicide layer (e.g., of cobalt silicide, titanium silicide, nickel silicide or tungsten silicide).

Referring toFIG. 16, upper trenches304may be formed to recess partially a top surface of the lower electrode layer151. The upper trench304may be formed to be substantially parallel to the first trench301.

As a result of the formation of the upper trenches304, the lower electrode layer151may have a linear shape extending along the direction of the y-axis. The lower electrode layer151may include a bottom portion on the semiconductor layer131and sidewall portions extending upward from the bottom portion along the sidewall of the first insulating layer123. Here, as a result of the formation of the upper trenches304, the sidewall portions of the lower electrode layer151may be different from each other in terms of vertical length. The x-axis directional maximum width of the lower electrode layer151may be substantially equivalent to an upper width of the semiconductor layer131.

The upper trench304may be filled with an insulating gap-filling layer155, and then the insulating gap-filling layer155may be planarized to expose a top surface of the lower electrode layer151. In some modified exemplary embodiments, the upper trench304may be filled with a first interlayer dielectric145(seeFIGS. 8-10,18, and22) to be subsequently formed, without the insulating gap-filling layer155.

Referring toFIG. 17, the second trenches302may be formed to cross the mold patterns120and the semiconductor layers131, as described with reference toFIG. 6. According to at least one exemplary embodiment, the formation of the second trenches302may include patterning the lower electrode layers151and the insulating gap-filling layer155to form lower electrodes152, and then, patterning the mold patterns120and the semiconductor layers131to form the semiconductor patterns135.

For example, the formation of the second trenches302may include forming a second mask pattern (not shown) having a line-and-space shape on the lower electrode layers151to cross the mold patterns120and the semiconductor layers131, and then anisotropically etching the lower electrode layers151and the semiconductor layers131using the second mask pattern as an etch mask.

The second trenches302may be formed to extend along the direction of the y-axis. In addition, the second trenches302may be formed to expose the top surface of the semiconductor substrate100. For example, the second trenches302may expose surfaces of the lower interconnection lines105formed by doping the semiconductor substrate100with impurities. Furthermore, the second trenches302may expose the etch stop layer121disposed below the first insulating layer123. As the result of the anisotropic etching, a width of the second trench302may be smaller in a lower portion than in an upper portion. The second trench302may have a bottom surface that is recessed below the top surface of the semiconductor substrate100.

As the result of the formation of the second trenches302, the semiconductor patterns135may be two-dimensionally arranged on the semiconductor substrate100, and the lower electrodes152may be disposed on the semiconductor patterns135, respectively, as shown inFIG. 17. In addition, the ohmic patterns142may be interposed between the semiconductor patterns135and the lower electrodes152, respectively, and the capping insulating patterns154may be formed on the lower electrodes152, respectively. During the formation of the second trenches302, the insulating gap-filling layer155in the recess region may be patterned to form gap-fill insulating patterns157. According to at least one exemplary embodiment, similar to the semiconductor patterns135, first sidewalls of the lower electrode152may be delimited by the first trenches301, and second sidewalls of the lower electrode152may be delimited by the second trenches302.

The lower electrode152may have a linear top surface. An x-axis directional width of the lower electrode152may be substantially equivalent to that of an upper portion of the semiconductor pattern135, and a y-axis directional width of the lower electrode152may be substantially equivalent to that of the upper portion of the semiconductor pattern135.

Thereafter, the second trenches302may be filled with the second insulating patterns140. In other words, the second insulating patterns140may extend along the direction of the x-axis and cover the second sidewalls135b(seeFIGS. 6 and 12) of the semiconductor patterns135and the lower electrodes152.

In at least one exemplary embodiment, the formation of the second insulating patterns140may include filling the second trenches302with an insulating material, and then, planarizing the insulating material to expose top surfaces of the gap-fill insulating pattern157and the lower electrode152. The second insulating patterns140may be in direct contact with the sidewalls of the lower electrode152and the capping insulating pattern154exposed by the second trenches302.

Referring toFIG. 18, the first interlayer dielectric145may be formed on the lower electrodes152. The first interlayer dielectric145may be formed to define the openings crossing the lower interconnection lines105or the first trenches301and exposing top surfaces of the lower electrodes152. The memory elements160may be formed in the openings of the first interlayer dielectric145. Accordingly, each of the memory elements160may be shaped like a line crossing the lower interconnection lines105.

The upper interconnection lines170may be formed on the memory elements160to cross the lower interconnection lines105or be parallel to the direction of the x-axis. In at least one exemplary embodiment, the upper interconnection lines170may be substantially parallel to the memory elements160.

FIGS. 19 through 22are perspective views illustrating a method of fabricating a semiconductor device according to modifications of other example embodiments of the present general inventive concept. These modifications may differ from at least one exemplary embodiment described with reference toFIGS. 14 through 18, in terms of the method of forming the capping insulating layer153.

Referring toFIG. 19, the top surfaces of the semiconductor layers131may be recessed to form the recess regions303, as described with reference toFIG. 14. Next, the lower electrode layer151and the capping insulating layer153may be sequentially and conformally deposited on the structure including the recess regions303.

Here, a total deposition thickness of the lower electrode layer151and the capping insulating layer153may be smaller than half the width of the upper trench304(seeFIGS. 16 and 20). In other words, the recess region303may have a portion that is not occupied by the lower electrode layer151and the capping insulating layer153.

Referring toFIG. 20, the upper trenches304may be formed to recess partially the lower electrode layer151. In at least one exemplary embodiment, the formation of the upper trenches304may include sequentially and partially etching the capping insulating layer153and the lower electrode layer151in an anisotropic etching manner. The upper trenches304may be formed to be substantially parallel to the first trench301. Due to the presence of the upper trenches304, the lower electrode layers151and the capping insulating layers153may have line shapes extending along the direction of the y-axis, and top surfaces of the first insulating layers123may be partially covered with the lower electrode layers151and the capping insulating layers153.

Referring toFIG. 21, the insulating gap-filling layers155may be formed to fill the upper trenches304(seeFIG. 20) and the recess regions303(seeFIG. 19). In at least one exemplary embodiment, the insulating gap-filling layer155may cover the top surface of the capping insulating layer153. Thereafter, the insulating gap-filling layer155may be planarized to expose the top surfaces of the first insulating layers123. During this process, the capping insulating layer153and the lower electrode layer151may be also planarized and localized in the recess region303. As a result, a top surface of the lower electrode layer151may be shaped like a line extending along the direction of the y-axis. Along the direction of the z-axis, the lower electrode layer151may include a bottom portion on the semiconductor layer131and sidewall portions extending upward from the bottom portion along the sidewall of the first insulating layer123. In at least one exemplary embodiment, the x-axis directional maximum width of the lower electrode layer151may be substantially equivalent to an x-axis directional upper width of the semiconductor layer131. The capping insulating layer153may be formed in the recess region303to cover conformally the top surface of the lower electrode layer151.

Referring toFIG. 22, the second trenches302may be formed to cross the mold patterns120and the semiconductor layers131. As a result, the semiconductor patterns135may be two-dimensionally arranged on the semiconductor substrate100, and the lower electrodes152may be formed on the semiconductor patterns135, respectively. In addition, the ohmic patterns142may be interposed between the semiconductor patterns135and the lower electrodes152, respectively, and the capping insulating patterns154may be formed on the lower electrodes152, respectively. During the formation of the second trenches302, the insulating gap-filling layer155in the recess region may be patterned to form gap-fill insulating patterns157.

Thereafter, the first interlayer dielectric145may be formed to define the openings crossing the lower interconnection lines105or the first trenches301and exposing top surfaces of the lower electrodes152, as previously described with reference toFIG. 18. The memory elements160may be formed in the openings of the first interlayer dielectric145, and the upper interconnection lines170may be formed on the memory elements160.

Hereinafter, the semiconductor device fabricated by the afore-described method will be described with reference toFIG. 22. For concise description, a previously described element may be identified by an identical reference number without repeating an overlapping description thereof.

Referring toFIG. 22, the semiconductor device may include the semiconductor substrate100, the lower interconnection lines105on the semiconductor substrate100, the upper interconnection lines170crossing the lower interconnection lines105, the selection elements disposed at intersections, respectively, of the lower and upper interconnection lines105and170, and the memory elements160interposed between the selection elements and the upper interconnection lines170.

The selection elements may include the semiconductor patterns135formed by the forming method described with reference toFIGS. 14 through 18. Each of the semiconductor patterns135may include the upper and lower doped regions135pand135n(seeFIGS. 7-10,12, and13), and the lower electrodes152may be formed between the semiconductor patterns135and the memory elements160, respectively. The semiconductor patterns135may be cut by the first and the second trenches301and302, such that they may be spaced apart from each other in both of the directions of the x- and y-axes or be two-dimensionally arranged on the semiconductor substrate100. Here, each of the semiconductor patterns135may have the first sidewalls135a(seeFIGS. 6 and 12) delimited by the first trenches301to face each other and the second sidewalls135a(seeFIGS. 6 and 12) delimited by the second trenches302to face each other. Each of the semiconductor patterns135may have a substantially irregular quadrilateral shape in a planar sectional view.

Referring to the exemplary embodiment illustrated inFIG. 12, for each of the semiconductor patterns135, if a first lower width W1and a first upper width W2are measured in a vertical section parallel to the direction of the x-axis or are given as distances between the first sidewalls135a, the first lower width W1may be smaller than the first upper width W2. Furthermore, for each of the semiconductor patterns135, if a second lower width L1and a second upper width L2are measured in a vertical section parallel to the direction of the y-axis or are given as distances between the second sidewalls135b, the second upper width L2may be smaller than the second lower width L1.

Referring toFIG. 22, in at least one exemplary embodiment, the lower electrodes152may have first and second sidewalls delimited by the first and second trenches301and302, respectively.

In a vertical sectional view, each of the lower electrodes152may include the bottom portion on the semiconductor pattern135and the sidewall portions extending upward from the bottom portion along the sidewall of the first insulating pattern125. Here, the sidewall portions of the lower electrodes152may be different from each other in terms of vertical length. The top surface of the lower electrode152in contact with the memory element160may have a linear shape, in a plan view. For example, a longitudinal direction of the top surface of the lower electrode152may be substantially parallel to one of the lower interconnection line105and the upper interconnection line170. In at least one exemplary embodiment, the longitudinal length of the lower electrode152may be substantially equivalent to the second upper width L2of the second sidewall135bof the semiconductor pattern135(seeFIG. 12).

Furthermore, the capping insulating layers153may be disposed on the lower electrodes152, respectively. Each of the capping insulating layers153may cover the bottom and sidewall portions of the lower electrode152, as shown inFIGS. 18 and 22, and be in direct contact with the sidewalls of the second insulating pattern140.

FIG. 23is a block diagram of an electronic device1000including a semiconductor device according to example embodiments of the present general inventive concept.

The electronic device1000according to example embodiments of the present general present general inventive concept may be used in various applications and/or devices including, but not limited to, an application chipset, a camera image sensor, a camera image signal processor (ISP), a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, and a wired and/or wireless electronic device.

Referring toFIG. 23, the electronic device1000may include a semiconductor memory device1300, a central processing unit (CPU)1500, a user interface1600, and a power supply device1700, which are connected to a system bus1450. The semiconductor memory device1300may include a semiconductor device1100, which may be one of the semiconductor devices described previously with reference toFIGS. 1 through 22, and a memory controller1200.

Data processed by the CPU1500and/or input from the user interface1600may be stored in the semiconductor device1100, and the memory controller1200may be configured to control such data exchange among the CPU1500, the user interface1600, and the semiconductor device1100. The semiconductor memory device1100may constitute a solid state drive (SSD), and in this case, an operating speed of the electronic device1000may become very fast.

A semiconductor pattern is used to realize a selection element. According to the afore-described exemplary embodiments of the present general present general inventive concept, the semiconductor pattern may be formed by patterning a semiconductor layer of linear shape. This may reduce a variation in width of the semiconductor pattern, even in the case in which integration density of the semiconductor device is very high. As a result, it is possible to fabricate semiconductor devices having an increased integration density and an improved operation property (e.g., reliability).