Display device and method of manufacturing display device

A display device includes a display area, a frame area around the display area, and a contact area between the display area and the frame area. In the display area is there provided a light-emitting element layer including an anode, a functional layer, a cathode, and a pixel bank covering an edge of the anode. The cathode is electrically connected to a metal film in the contact area. An insular TEG pattern is provided in the contact area.

TECHNICAL FIELD

The present disclosure relates to display devices and methods of manufacturing display devices.

BACKGROUND ART

The display area of a display device includes a stack of patterned functional layers formed by vapor deposition. Patent Literature 1 describes a TEG (test element group) pattern provided between panel formation areas on the substrate, except in the effective area, to manage a vapor deposition process (film-forming process) for the functional layers. Patent Literature 1 further describes that the condition of each vapor-deposited layer is managed through the measurement of, for example, the thickness or location of the TEG pattern thus formed.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

The invention described in Patent Literature 1, however, only provides the TEG pattern away from the display area in the effective area (panel), therefore falling short of accurately managing the condition of the vapor-deposited functional layer. The invention described in Patent Literature 1 hence have difficulty detecting local defects in the effective area.

The present disclosure, in an aspect thereof, has been made to address these problems and has an object to provide a display device in which the condition of a vapor-deposited functional layer is precisely evaluated and a method of manufacturing such a display device.

Solution to Problem

To address the problems, the present disclosure, in an aspect thereof, is directed to a display device having a display area and a frame area around the display area, the display area including a stack body including: a TFT layer; a light-emitting element layer including an anode, a functional layer, a cathode, and a pixel bank covering from an opening therein to an edge of the anode; and a sealing layer, the sealing layer including at least one organic film, there being provided a partition wall in the frame area, the partition wall being configured to delineate an edge of the organic film, the display device further having, between the display area and the partition wall, a contact area in which the cathode is electrically connected to a metal film made of a same material and in a same layer as the anode, and there being provided an insular TEG pattern in the contact area, the insular TEG pattern being made of a same material as the functional layer.

Advantageous Effects of Disclosure

The present disclosure, in an aspect thereof, provides a TEG pattern in a contact area adjacent to the display area and evaluates the condition of a vapor-deposited functional layer in the display area on the basis of this TEG pattern, thereby evaluating the condition of the vapor-deposited functional layer with improved precision.

DESCRIPTION OF EMBODIMENTS

The following will describe in detail an embodiment in accordance with the present disclosure. Portion (a) ofFIG.1is a schematic plan view of a structure of a display device, and (b) ofFIG.1is a cross-sectional view of a display area. As shown inFIG.1, a display device2has a display area (active area) A1and a frame area (non-display area) F1around the display area A1. In the display area A1are there provided a plurality of subpixels SP and a plurality of wires or lines (e.g., scan signal lines, data signal lines, light-emission control lines, and EL power supply lines; none of them shown). In the frame area F1, there are provided, for example, various driver circuitry and a terminal section (neither shown). The display area A1may be notched. A portion of the frame area F1(e.g., the terminal section) may be bent backwards.

The display device2includes a barrier layer3, a TET layer4, a light-emitting element layer5, a sealing layer6, and a functional film29stacked in this sequence on a base member12. The base member12may be a glass substrate or a flexible resin substrate (e.g., polyimide substrate). The barrier layer3prevents foreign material such as water, oxygen, and mobile ions from reaching the TFT layer4and the light-emitting element layer5. The barrier layer3is composed of, for example, a film of silicon oxide or silicon nitride formed by CVD or a stack of these films.

The TFT layer4includes a semiconductor layer15, an inorganic insulation film16, a first metal layer (including gate electrodes GE and gate lines GH), an inorganic insulation film18, a second metal layer (including capacitor electrodes CE), an inorganic insulation film20, a third metal layer (including source lines SH), and a planarization film21stacked in this sequence. The gate lines GH include, for example, the scan signal lines and the light-emission control lines. The source lines SH include, for example, the data signal lines and the EL power supply lines.

The semiconductor layer15may be composed of a low-temperature polysilicon (LTPS) or an oxide semiconductor (e.g., In—Ga—Zn—O-based semiconductor). Each metal layer is a monolayer or multilayer metal film containing at least one of, for example, aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper. The inorganic insulation films16,18, and20may be made of, for example, a film of silicon oxide or silicon nitride formed by CVD or a stack of these films. The planarization film21(interlayer insulation film) may be made of an organic material, such as polyimide or acrylic resin, that can be applied by printing or coating technology and that exhibits a planarization effect.

In the TFT layer4, transistors TR are formed so as to include the semiconductor layer15and the gate electrodes GE. Capacitors Cp are formed between the gate lines GH and the capacitor electrodes CE.FIG.1shows the transistor TR as having a bottom-gate structure. The transistor TR may alternatively be have, for example, a top-gate structure.

The light-emitting element layer5includes anodes22, pixel banks (edge covers)23covering the edges of the anodes22, an EL (electrolurninescence) layer24, and cathodes25stacked in this sequence. Each pixel bank23has an opening (second opening)23ain which the anode22is exposed.

Each subpixel SP includes a self-luminous light-emitting element ES (e.g., an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED)) including the anode22, the functional layer24, and the cathode25. The light-emitting element ES is driven by various wires or lines (e.g., a scan signal line, a data signal line, a light-emission control line, and an EL power supply line) and a pixel circuit (including the transistor TR and the capacitor Cp) formed in the TFT layer4, to adjust current between the anode22and the cathode25in accordance with a data signal (gray level signal).

The functional layer24(alternatively referred to as the active layer or the EL layer) includes, for example, a hole injection layer, a hole transport layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked in this sequence. The light-emitting layer is formed by, for example, vapor deposition or inkjet printing technology so as to overlap the openings23ain the pixel banks23that delineate light-emitting regions. One or more of the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be omitted.

A FMM (fine metal mask) is used in forming the light-emitting layer for OLEDs by vapor deposition. A FMM is a sheet of, for example, an invar material with numerous through holes. An organic material that has passed through a through hole forms an insular light-emitting layer (corresponding to one light-emitting element ES).

An insular QLED light-emitting layer (corresponding to one light-emitting element ES) can be formed, for example, by inkjet printing with a solvent containing diffused quantum dots or by patterning by photolithography the quantum dot layer obtained by applying the solvent using a coater.

The anode22includes a stack of, for example, ITO (indium in oxide) and either Ag (silver) or a Ag-containing alloy, so that the anode22is light-reflective. The cathode25may be formed of a transparent conductive material such as a Mg—Ag alloy (super thin film), ITO, or IZO (indium zinc oxide).

Each pixel bank23is arranged in such a manner as to separate adjacent pixels pix. The pixel bank23is insulating and made of, for example, an organic material, such as polyimide or acrylic resin, that can be applied by printing or coating technology. The pixel bank23is provided so as to cover an edge of the anode22. The pixel bank23serves as an edge cover that prevents short-circuiting between an edge of the anode22and the cathode25even if the functional layer24hhas a thin edge. The pixel bank23serves also as a pixel separation film to prevent current leaks between those pixels pix that are adjacent to each other.

When the light-emitting element ES is an OLED, holes and electrons recombine in the light-emitting layer due to a current between the anode22and the cathode25, to produce excitors that transition to the ground state to emit light. Since the cathode25is transparent, and the anode22is light-reflective, the light emitted by the functional layer24travels upwards, thereby achieving “top emission.”

When the light-emitting element ES is a QLED, holes and electrons recombine in the light-emitting layer due to a current between the anode22and the cathode25, to produce excitors that transition from the conduction hand to the valence band of the quantum dot to emit light (fluorescence).

The light-emitting element layer5may include light-emitting elements other than the OLED and QLED, such as inorganic light-emitting diodes.

The sealing layer6is transparent and includes an inorganic sealing film26covering the cathode25, an organic buffer film (organic film)27overlying the inorganic sealing film26, and an inorganic sealing film28overlying the organic buffer film27. The sealing layer6, covering the light-emitting element layer5, prevents foreign material such as water, oxygen, and mobile ions from reaching the light-emitting element layer5.

The inorganic sealing films26and28are transparent insulation films and may each include, for example, a film of silicon oxide or silicon nitride formed by CVD or a stack of these films. The organic buffer film27is a transparent organic film that exhibits a planarization effect. The organic buffer film27may be made of an organic material, such as acrylic resin, that can be applied by printing or coating technology. The organic buffer film27may be formed by inkjet printing.

The functional film29has, for example, at least one of a protection function, an optical compensation function, and a touch sensor function.

The display device2may be flexible, in which case the aforementioned layers are formed on a mother substrate, the mother substrate is thereafter detached, and a film or like body is attached as a support. Then, individual flexible display panels (organic EL display panels) are obtained by cutting out EL display panels from the film carrying stack bodies7thereon. The individual EL display panels are fitted with drivers and other circuitry to complete the manufacture of OLED display devices.

A description will be given next of a structure of the light-emitting element layer5with reference toFIG.2.FIG.2is a schematic diagram of a structure of the light-emitting element layer5. The light-emitting element layer5includes the anode22, the pixel bank23, the functional layer24, and the cathode25.

The anode22feeds holes to the functional layer24. As shown inFIG2, the functional layer24includes, for example, a hole injection layer41, a hole transport layer42, a light-emitting layer43, a hole blocking layer44, an electron transport layer45, and an electron injection layer46stacked by vapor deposition in this sequence when viewed from the anode22. These layers constitute the functional layer24. The cathode25is formed so as to cover the functional layer24.

Referring toFIG.3, the hole transport layer42and the light-emitting layer43are provided in an insular manner for each pixel pix by vapor deposition using a vapor deposition mask.FIG.3is an enlarged diagram of a part of the display area of the display device in accordance with an embodiment. The layers other than the hole transport layer42and the light-emitting layer43, that is, the hole injection layer41, the hole blocking layer44, the electron transport layer45, the electron injection layer46, and the cathode25are provided as common layers across the pixels pix. One or more of the hole injection layer41, the hole blocking layer44, the electron transport layer45, and the electron injection layer46may be omitted. Those layers that are vapor-deposited for each pixel pix using a vapor deposition mask, like the hole transport layer42and the light-emitting layer43, will be referred to as vapor deposition layers.

The light-emitting layer43and the hole transport layer42are provided for each color of the light emitted by the pixel pix in the pixel pix. For instance, when the pixel pix is a red pixel Rpix that emits red light, a green pixel Gpix that emits green light, or a blue pixel Bpix that emits blue light, the red pixel Rpix includes a red light-emitting layer43R and a red hole transport layer42R, the green pixel Gpix includes a green light-emitting layer43G and a green hole transport layer42G, and the blue pixel Bpix includes a blue light-emitting layer43B and a blue hole transport layer42B, respectively.

The hole injection layer41contains a hole injecting material to improve the efficiency of hole injection to the light-emitting layer43. The hole transport layer42contains a hole transporting material to improve the efficiency of hole transport from the anode22via the hole injection layer41to the light-emitting layer43. The red hole transport layer42R improves the efficiency of hole transport to the red light-emitting layer43R. The green hole transport layer42G improves the efficiency of hole transport to the green light-emitting layer43G. The blue hole transport layer42B improves the efficiency of hole transport to the blue light-emitting layer43B.

The hole blocking layer44contains a hole transport-obstructing material to obstruct hole transport, via the light-emitting layer43to the electron transport layer45. The electron injection layer46contains an electron injecting material to improve the efficiency of electron injection to the light-emitting layer43. The electron transport layer45contains an electron transporting material to improve the efficiency of electron transport to the light-emitting layer43.

The holes injected from the anode22to the light-emitting layer43and the electrons injected from the cathode25to the light-emitting layer43recombine in the light-emitting layer43, to produce excitors that fall from the excited state to the ground state to emit light. By this mechanism, the red light-emitting layer43R emits red light, the green light-emitting layer43G emits green light, and the blue light-emitting layer43B emits blue light.

The red hole transport layer42R, the red light-emitting layer43R, the green hole transport layer42G, the green light-emitting layer43G, the blue hole transport layer42B, and the blue light-emitting layer43B are formed sequentially in the pixel pix by vapor deposition using an individual vapor deposition mask. Any layer that is formed for each pixel pix (in other words, in the opening23ain the pixel bank23), including the hole transport layer42and the light-emitting layer43, may be formed using a vapor deposition mask.

FIG.3shows, as an example, a PenTile layout of the red pixels Rpix each including the red hole transport layer42R and the red light-emitting layer43R, the green pixels Gpix each including the green hole transport layer42G and the green light-emitting layer43G, and the blue pixels Bpix each including the blue hole transport layer42B and the blue light-emitting layer43B. The pixels are not necessarily arranged in a PenTile layout and may be arranged in, for example, a stripe layout or another layout.

The hole transport layer42and the light-emitting layer43have the same shape as the opening23ain the pixel bank23in which the light-emitting layer43and the hole transport layer42are formed. In the example shown inFIG.3, the red pixels Rpix and the blue pixels Bpix have the same resolution (have the same pixel-to-pixel pitch). In contrast, the green pixels Gpix have a higher resolution than the red pixels Rpix and the blue pixels Bpix (have a smaller pixel-to-pixel pitch). There are some cases like this, where only those pixels pix for a particular one of the colors of emitted light need to have a higher resolution.

The pixels pix do not necessarily emit red, green, and blue light and may emit light of other colors. The pixels pix do not necessarily emit three colors of light and may emit two, four, or more colors of light.

The display device2includes TEG patterns to manage the vapor deposition process in which the functional layer24such as the hole transport layer42or the light-emitting layer43is formed for each pixel pix by vapor deposition using a vapor deposition mask. The management is done, for example, through the observation of vapor deposition film displacements and layer separation precision. A description is now given of TEG patterns50in the display device2with reference toFIGS.4to7.FIG.4is a diagram of a display panel on the substrate.FIG.5is a schematic diagram of a structure of the display area and the frame area.FIG.6is a schematic cross-sectional view of the structure of the display area and the frame area.FIG.7is an enlarged diagram of a contact area shown inFIG.6.

FIG.4illustrates display panels PA before being cut out of a film or substrate carrying the stack body7thereon. Known display device includes TEG patterns for each display panel PA outside the display panel PA. Accordingly, the TEG patterns for checking the separation precision for the functional layer24are located away from the display area A1containing pixels formed by the functional layer24. The TEG patterns are also few in number for each display panel PA. In addition, the areas outside the display panel PA are flat patterned areas, and it is therefore not possible to check for adverse effects of the shadow created by the height of the pixel bank23in the display area A1. It is hence impossible to precisely evaluate the causes for, and solutions (offset) to, color mixing that may occur in the display area A1.

In the display device2in accordance with an embodiment, the TEG patterns50are provided in a contact area C1around the display area A1as shown inFIG.5. This location of the TEG patterns50enables accurate observation of vapor deposition film displacements and layer separation precision near the display area A1, thereby achieving more precise vapor deposition management. The manufactured display device2hence exhibits no undesirable color mixing and related defects.

Furthermore, the display device2allows for the provision of many TEG patterns50in the contact area C1, which stretches along all the four sides of the display area A1, so long as the contact resistance of the contact area C1(the resistance between the cathodes25and the electrode wiring formed near the TFTs on the substrate is tolerated. The display device2therefore allows for more effective detection of, for example, local vapor deposition film displacements and shadows.

FIG.5is a schematic top view of the display device2, with parts of the layers on the functional layer24being removed to illustrate the TEG pattern50. Referring toFIG.5, the frame area F1resides around the display area A1of the display device2. The contact area C1resides between the display area A1and the frame area F1, and the cathodes25are electrically connected in the contact area C1.

The pixel pix is provided for each color of emitted light in the display area A1.FIG.5shows, as an example, the display area A1where the red pixels Rpix that emit red light, the green pixels Gpix that emit, green light, and the blue pixels Bpix that, emit blue light are separated by the pixel banks23.

The frame area F1includes provided therein a first bank (partition wall)57, a second bank58, and a sealing area59where the inorganic sealing films26and28in the sealing layer6are directly joined. The sealing layer6resides across the display area A1, the contact area C1, and the frame area F1on the cathodes25formed after the vapor deposition process. The first bank57serves also as a spacer that delineates an edge of the organic film in the sealing layer6(i.e., the organic buffer film27inFIG.1).

The contact area C1resides between the display area A1and the second bank58in the frame area F1. Specifically, as shown inFIG.7, there is provided a metal film63in the contact area C1. The metal film63is made of the same material and in the same layer as the anode22. There is also provided a conductive film68in the contact area C1. The conductive film68is made of the same material and in the same layer as the source line SH. In the contact area C1, the cathode25is electrically connected to the metal film63and also to the conductive film68via the metal film63. The conductive film68is electrically connected to a low-voltage power supply (ELVSS).

The hole transport layer42and the light-emitting layer43, which are both the functional layers24, are vapor deposited in the opening23ain the pixel bank23for each pixel pix in the display area A1. Since the anode22is exposed in the opening23ain the pixel bank23, the functional layer24is vapor-deposited on the anode22. When the TEG pattern50is formed by vapor depositing the same material on the metal film63in the contact area C1as the functional layer24, the functional layer24and the TEG pattern50are formed by vapor deposition not only closely, but also under similar vapor deposition conditions. The particular structure enables accurate observation of vapor deposition film displacements and layer separation precision in the functional layer24, thereby achieving more precise vapor deposition management.

In example shown inFIG.5, the TEG patterns for the hole transport layer42and the light-emitting layer43are provided for each color of red, green, and blue. In other words, as shown in the contact area C1, particularly inFIG.7, the TEG patterns residing between an out-of-pixel spacer (out-of-pixel partition wall)56overlapping the cathode25and the out-of-pixel spacer56not overlapping the cathode25are formed in an insular manner on the metal film63separately for each vapor deposition layer and for each color of the pixels. The TEG patterns hence enable vapor deposition management for each layer and each pixel without being affected by the overlapping of the functional layer24and the pixel-to-pixel overlapping of layers.

The metal film63on a TFT substrate30has openings (first openings)63ain the present embodiment, as shown inFIG.6. A vapor deposition film67that has TEG patterns is provided over the openings63a, to form the insular TEG patterns50on the metal film63. In other words, the TEG patterns50are formed such that the TEG patterns50at least partially overlap the openings63ain the metal film63when viewed from the above with respect to the direction in which the constituent layers of the stack body7are stacked. This particular structure enables vapor deposition management for the functional layer(s)24through mere evaluation of the vapor deposition of the TEG patterns50with reference to the openings63ain the metal film63, without having to observe vapor deposition in the pixels pix in the display area A1.FIG.6shows an in-pixel spacer64in contact with the vapor deposition mask60in the display area A1and the out-of-pixel. spacer56in contact with the vapor deposition mask60in the frame area F1. The “out-of-pixel spacer”56is a spacer in the frame area F1, and the in-pixel spacer64is a spacer in the display area A1.

Referring toFIG.5, the opening63ain the metal film63is provided for each layer and for each color of the pixels. In other words, there are provided an opening51R for a red hole transport layer, an opening52R for a red light-emitting layer, an opening51G for a green hole transport layer, an opening52G for a green light-emitting layer, an opening51B for a blue hole transport layer, and an opening52B for a blue light-emitting layer.

The TEG patterns50are formed so as to overlap these openings respectively. In other words, the TEG pattern50includes a vapor deposition film53R made of the same material as the red hole transport layer, a vapor deposition film54R made of the same material as the red light-emitting layer, a vapor deposition film53G made of the same material as the green hole transport layer, a vapor deposition film54G made of the same material as the green light-emitting layer, a vapor deposition film53B made of the same material as the blue hole transport layer, and a vapor deposition film54B made of the same material as the blue light-emitting layer.

The hole transport layer42and the light-emitting layer43are stacked in in the pixel pix and may overlap in adjacent pixels. Overlapping of many films makes it difficult to observe the condition of individual films by evaluating vapor deposition film displacements in the pixels pix through fluorescence (PL) under UV radiation. Since the TEG patterns50are provided in an insular manner in the contact area C1separately for each layer and for each color of the pixels, the display device2enables vapor deposition management for each layer and each pixel through observation of the condition of the vapor deposition film under UV radiation on the TEG patterns50, without being affected by the overlapping of the functional layer24and the pixel-to-pixel overlapping of layers. In addition, since the TEG pattern50resides on the metal film63, it becomes easier to detect vapor deposition film displacements when, for example, the metal film63is made of highly reflective silver. In the opening63ain the metal film63, those parts that do not overlap the TEG pattern50emit more light.

The functional layer24is vapor-deposited for each pixel pix by a process using the vapor deposition mask60shown inFIG.6. The vapor deposition mask60has openings61for the openings23ain the pixel banks23and openings62for the openings63ain the metal film63. The use of the vapor deposition mask60in vapor deposition enables the formation of the functional layer24for each pixel pix in the display area A1and the simultaneous formation of the vapor deposition film67having the TEG patterns of the same material as the functional layer24on the metal film63in the contact area C1. If the TEG patterns50are provided in the contact area C1all along the four sides of the display area A1, the vapor deposition mask60need to be have the openings62on all the corresponding four sides thereof. This particular structure enables well-balanced stretching of the sheet-like vapor deposition mask60.

After the vapor deposition process using the vapor deposition mask60, the TEG patterns50are illuminated with UV radiation to evaluate the condition of the vapor deposition film67to investigate, for example, causes for undesirable color mixing. The locations and size of the openings61in the vapor deposition mask60for the openings23ain the pixel banks23may be adjusted in view of results of the evaluation to re-design the vapor deposition mask60, change the stretching conditions of the vapor deposition mask60, and/or change vapor deposition conditions.

The contact area C1may include the out-of-pixel spacers56as shown inFIGS.5and6. The out-of-pixel spacers56are formed so as to surround the display area A1like a frame. The openings63ain the metal film63are provided between two adjacent out-of-pixel spacers56. The out-of-pixel spacers56are made of the same material and in the same layer as the pixel banks23.

Variation Example 1

The insular vapor deposition film for the TEG patterns50may entirely overlap the opening63ain the metal film63when viewed from the above with respect to the direction in which the constituent layers of the stack body7are stacked. In other words, the opening63ain the metal film63may be larger than the insular vapor deposition film67for the TEG patterns50. This particular structure facilitates the observation of the amount of displacement of the vapor deposition film67for the TEG patterns50relative to the opening63ain the metal film63.

The opening63ain the metal film63may have substantially the same shape as the opening23ain the pixel bank23similarly to, for example, the opening51R corresponding to the red hole transport layer and the opening52R corresponding to the red light-emitting layer shown inFIG.5. This particular structure enables more reliable observation of the condition of the vapor deposition of, for example, the pixels pix.

The opening63ain the metal film63may be cross-shaped like opening55shown inFIG.5. This particular structure enables more reliable observation of displacements of the vapor deposition film67.

Variation Example 2

The opening63ain the metal film63may entirely overlap the insular vapor deposition film67for the TEG patterns50when viewed from the above with respect to the direction in which the constituent layers of the stack body7are stacked. In other words, the opening63ain the metal film63may be smaller than the insular vapor deposition film67for the TEG patterns50. This particular structure facilitates the observation of whether or not the vapor deposition film67for the TEG patterns50is displaced relative to the opening63ain the metal film63.

The opening63ain the metal film63may have substantially the same shape as the opening23ain the pixel bank23and may be cross-shaped in the present variation example, similarly to Variation Example 1.

A description is now given of another embodiment of the present disclosure with reference toFIG.8.FIG.8is a schematic cross-sectional view of a structure of the display area A1and the frame area F1. As shown inFIG.8, the present embodiment differs from Embodiment 1 in that the metal film63has no opening63aand also that there is provided an out-of-pixel bank70on the metal film63. The description of the present embodiment therefore will focus on the differences from Embodiment 1 and may skip mentioning similarities.

The out-of-pixel bank70, similarly to the pixel banks23, has openings (third openings)70ain the contact area C1, particularly between the out-of-pixel spacer56overlapping the cathode25and the out-of-pixel spacer56not overlapping the cathode25. The insular TEG patterns50are formed by forming the vapor deposition film67for TEG patterns in the openings70ain the out-of-pixel bank70. In other words, the TEG patterns50are formed so as to at least partially overlap the openings70ain the out-of-pixel bank70when viewed from the above with respect to the direction in which the constituent layers of the stack body7are stacked. This particular structure enables vapor deposition management for the functional layer(s)24through mere evaluation of the vapor deposition of the TEG patterns50with reference to the openings70ain the out-of-pixel bank70, without having to observe vapor deposition in the pixels pix in the display area A1. The out-of-pixel bank70is made of the same material and in the same layer as the pixel banks23. The opening70ain the out-of-pixel bank70emits more or less the same amount of light under UV radiation in the portion thereof overlapping the TEG pattern50and in the portion thereof not overlapping the TEG pattern50.

Similarly to Embodiment 1, the opening70ain the out-of-pixel bank70is provided for each layer and for each color of the pixels in the present embodiment. In other words, the opening51R for a red hole transport layer, the opening52R for a red light-emitting layer, the opening51G for a green hole transport layer, the opening52G for a green light-emitting layer, the opening51B for a blue hole transport layer, and the opening52B for a blue light-emitting layer, all shown inFIG.5, are the openings70ain the out-of-pixel bank70. The TEG patterns50are provided so as to respectively overlap these openings.

In the present embodiment, the vapor deposition mask60has openings61for the openings23ain the pixel banks23and openings62for the openings70ain the out-of-pixel bank70. The use of the vapor deposition mask60in vapor deposition enables the formation of the functional layer24for each pixel pix in the display area A1and the simultaneous formation of the vapor deposition film67having the TEG patterns of the same material as the functional layer24in the contact area C1.

The out-of-pixel bank70preferably has a height above the metal film63that is lower than the height of the out-of-pixel spacer56above the metal film63. This particular structure allows for such vapor deposition that no vapor deposition film covers the top of the out-of-pixel spacer56. The structure hence prevents vapor deposited films from coming into contact with the vapor deposition mask60in later steps, thereby reducing contamination of the vapor deposition mask60and production of foreign objects. The out-of-pixel bank70can be made of the same material and in the same layer as the out-of-pixel spacer56. If the out-of-pixel bank70and the out-of-pixel spacer56are simultaneously formed by, for example, photolithography using a halftone mask, the structure also advantageously facilitates the manufacture.

Variation Example 3

The insular vapor deposition film for the TEG patterns50may entirely overlap the opening70ain the out-of-pixel bank70when viewed from the above with respect to the direction in which the constituent layers of the stack body7are stacked. In other words, the opening70ain the out-of-pixel bank70may be larger than the insular vapor deposition film67for the TEG patterns50. This particular structure facilitates the observation of the amount of displacement of the vapor deposition film67for the TEG patterns50relative to the opening70ain the out-of-pixel bank70.

The opening70ain the out-of-pixel bank70may have substantially the same shape as the opening23ain the pixel bank23similarly to, for example, the opening51R corresponding to the red hole transport layer and the opening52R corresponding to the red light-emitting layer shown inFIG.5. This particular structure enables more reliable observation of the condition of the vapor deposition of, for example, the pixels pix.

The opening70ain the out-of-pixel bank70may be cross-shaped like opening55shown inFIG.5. This particular structure enables more reliable observation of displacements of the vapor deposition film.

Variation Example 4

The opening70ain the out-of-pixel bank70may entirely overlap the insular vapor deposition film67for the TEG patterns50when viewed from the above with respect to the direction in which the constituent layers of the stack body7are stacked. In other words, the opening70ain the out-of-pixel bank70may be smaller than the vapor deposition film67for the TEG patterns50, This particular structure facilitates the observation of whether or not the vapor deposition film67for the TEG patterns50is displaced relative to the opening70ain the out-of-pixel bank70.

The opening70ain the out-of-pixel bank70may have substantially the same shape as the opening23ain the pixel bank23and may be cross-shaped in the present variation example, similarly to Variation Example 3.

Method of Manufacturing Display Device

A method of manufacturing a display device in accordance with an embodiment of the present disclosure is a method of manufacturing a display device having a display area and a frame area around the display area, the display area including a stack body including: a TFT layer; a light-emitting element layer including an anode, a functional layer, a cathode, and a pixel bank covering from an opening therein to an edge of the anode; and a sealing layer, the method including: forming a partition wall in the frame area, the partition wall being configured to delineate an edge of an organic film in the sealing layer; forming, between the display area and the partition wall, a contact area in which the cathode is electrically connected to a metal film made of the same material and in the same layer as the anode; and forming, in the contact area, an insular TEG pattern of the same material as the functional layer.

In other words, an embodiment of the method of manufacturing a display device in accordance with the present disclosure is a method of manufacturing the aforementioned display device in accordance with an embodiment of the present disclosure. Therefore, an embodiment of the method of manufacturing a display device in accordance with the present disclosure follows the description of the aforementioned display device in accordance with an embodiment of the present disclosure.

General Description

The present disclosure, in aspect 1 thereof, is directed to a display device (display device2) having a display area A1and a frame area F1around the display area, the display area A1including a stack body7including: a TFT layer4; a light-emitting element layer5including an anode22, a functional layer24, a cathode25, and a pixel bank23covering from an opening therein to an edge of the anode; and a sealing layer6, the sealing layer including at least one organic film27, there being provided a partition wall (first bank57) in the frame area, the partition wall being configured to delineate an edge of the organic film, the display device further having, between the display area and the partition wall, a contact area C1in which the cathode is electrically connected to a metal film63made of a same material and in a same layer as the anode, and there being provided an insular TEG pattern50in the contact area, the insular TEG pattern50being made of a same material as the functional layer.

This structure includes a TEG pattern in the contact area residing around the display area. The structure therefore enables accurate observation of, for example, vapor deposition film displacements and layer separation precision near the display area, thereby achieving more precise vapor deposition management.

In aspect 2 of the present disclosure, the display device of aspect 1 may be configured such that the metal film has a first opening (opening63a) at least partially overlapped by the TEG pattern when viewed from above with respect to a stacking direction for the stack body. This structure enables vapor deposition management for the functional layer through mere evaluation of the vapor deposition of the TEG pattern with reference to the first opening, without having to observe vapor deposition in a pixel pix in the display area.

In aspect 3 of the present disclosure, the display device of aspect 2 may be configured such that the TEG pattern entirely overlaps the first opening when viewed from above with respect to the stacking direction for the stack body. This structure facilitates the observation of the amount of displacement of the vapor deposition film for the TEG pattern relative to the first opening.

In aspect 4 of the present disclosure, the display device of aspect 3 may be configured such that the first opening is cross-shaped. This structure enables more reliable observation of displacements of the vapor deposition film.

In aspect 5 of the present disclosure, the display device of aspect 3 may be configured such that the first opening is substantially identical in shape to a second opening (opening23a) in the pixel bank. This structure enables more reliable observation of the condition of the vapor deposition of, for example, a pixel pix.

In aspect 6 of the present disclosure, the display device of aspect 2 may be configured such that the first opening is entirely overlapped by the TEG pattern when viewed from above with respect to the stacking direction for the stack body. This structure facilitates the observation of whether or not the vapor deposition film for the TEG pattern is displaced relative to the first opening.

In aspect 7 of the present disclosure, the display device of aspect 6 may be configured such that the first opening is cross-shaped. This structure enables more reliable observation of displacements of the vapor deposition film.

In aspect 8 of the present disclosure, the display device of aspect 6 may be configured such that the first opening is substantially identical in shape to a second opening in the pixel bank. This structure more reliable observation of the condition of the vapor deposition of, for example, a pixel pix.

In aspect 9 of the present disclosure, the display device of any one of aspects 2 to 8 may be configured such that the contact area further including, on the metal film, an out-of-pixel partition wall (out-of-pixel spacer56) overlapping the cathode and an out-of-pixel partition wall (out-of-pixel spacer56) not overlapping the cathode, wherein the TEG pattern resides between the out-of-pixel partition wall overlapping the cathode and the out-of-pixel partition wall not overlapping the cathode. This structure enables vapor deposition management for the functional layer through mere evaluation of the vapor deposition of the TEG pattern residing between the out-of-pixel partition wall overlapping the cathode and the out-of-pixel partition wall not overlapping the cathode, without having to observe vapor deposition in a pixel pix in the display area.

In aspect 10 of the present disclosure, the display device of aspect 1 may be configured such that there being further provided an out-of-pixel bank70on the metal film, the out-of-pixel bank having a third opening (opening70a), wherein the TEG pattern at least partially overlaps the third opening when viewed from above with respect to a stacking direction for the stack body. This structure enables vapor deposition management for the functional layer through mere evaluation of the vapor deposition of the TEG pattern with reference to the third opening, without having to observe vapor deposition in a pixel pix in the display area.

In aspect 11 of the present disclosure, the display device of aspect 10 may be configured such that the TEG pattern entirely overlaps the third opening when viewed from above with respect to the stacking direction for the stack body. This structure facilitates the observation of the amount of displacement of the vapor deposition film for the TEG pattern relative to the third opening.

In aspect 12 of the present disclosure, the display device of aspect 11 may be configured such that the third opening is cross-shaped. This structure enables more reliable observation of displacements of the vapor deposition film.

In aspect 13 of the present disclosure, the display device of aspect 11 may be configured such that the third opening is substantially identical in shape to a second opening in the pixel bank. This structure enables more reliable observation of the condition of the vapor deposition of, for example, a pixel pix.

In aspect 14 of the present disclosure, the display device of aspect 10 may be configured such that the third opening is entirely overlapped by the TEG pattern when viewed from above with respect to the stacking direction for the stack body. This structure facilitates the observation of whether or not the vapor deposition film for the TEG pattern is displaced relative to the third opening.

In aspect 15 of the present disclosure, the display device of aspect 14 may be configured such that the third opening is cross-shaped. This structure enables more reliable observation of displacements of the vapor deposition film.

In aspect 16 of the present disclosure, the display device of aspect 14 may be configured such that the third opening is substantially identical in shape to a second opening in the pixel bank. This structure enables more reliable observation of the condition of the vapor deposition of, for example, a pixel pix.

In aspect 17 of the present disclosureinvention, the display device of any one of aspects 10 to 16 may be configured such that the contact area further including at least one out-of-pixel partition wall on the metal film, wherein the out-of-pixel bank has a lower height above the metal film than do the at least one out-of-pixel partition wall above the metal film.

This structure allows for such vapor deposition that no vapor deposition film covers the top of the out-of-pixel spacer. The structure hence prevents vapor deposited films from coming into contact with the vapor deposition mask60in later steps, thereby reducing contamination of the vapor deposition mask and production of foreign objects.

In aspect 18 of the present disclosure, the display device of aspect 17 may be configured such that the at least one out-of-pixel partition wall including an out-of-pixel partition wall overlapping the cathode and an out-of-pixel partition wall not overlapping the cathode, the TEG pattern resides between the out-of-pixel partition wall overlapping the cathode and the out-of-pixel partition wall not overlapping the cathode. This structure enables vapor deposition management for the functional layer through mere evaluation of the vapor deposition of the TEG pattern residing between the out-of-pixel partition wall overlapping the cathode and the out-of-pixel partition wall not overlapping the cathode, without having to observe vapor deposition in a pixel pix in the display area.

In aspect 19 of the present disclosure, the display device of aspect 17 or 18 may be configured such that the out-of-pixel bank is made of a same material and in a same layer as the at least one out-of-pixel partition wall. This structure facilitates the formation of the out-of-pixel bank and the out-of-pixel partition wall.

In aspect 20 of the present disclosure, the display device of any one of aspects 10 to 19 may be configured such that the pixel bank is made of a same material and in a same layer as the out-of-pixel bank. This structure facilitates the formation of the pixel bank and the out-of-pixel bank.

In aspect 21 of the present disclosure, the display device of any one of aspects 1 to 20 may be configured such that the functional layer includes a light-emitting layer. This structure enables precise evaluation of the condition of the vapor deposition of the light-emitting layer.

In aspect 22 of the present disclosure, the display device of any one of aspects 1 to 21 may be configured such that the functional layer includes a hole transport layer. This structure enables precise evaluation of the condition of the vapor deposition of the hole transport layer.

The present disclosure, in aspect 23 thereof, is directed to a method of manufacturing a display device having a display area and a frame area around the display area, the display area including a stack body including: a TFT layer; a light-emitting element layer including an anode, a functional layer, a cathode, and a pixel bank having an opening in which the anode resides; and a sealing layer, the method including: forming a partition wall configured to delineate an edge of an organic film in the sealing layer in the frame area; forming, between the display area and the partition wall, a contact area in which the cathode is electrically connected to a metal film made of a same material and in a same layer as the anode; and forming, in the contact area, an insular TEG pattern of a same material as the functional layer.

This structure achieves similar advantage to those achieved by the display device of aspect 1 in accordance with the present disclosure.

The present disclosure is not limited to the description of the embodiments above and may be altered within the scope of the claims. Embodiments based on a proper combination of technical means disclosed in different embodiments are encompassed in the technical scope of the present disclosure. Furthermore, new technological features can be created by combining different technical means disclosed in the embodiments.