Semiconductor device and method for manufacturing the same

In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses 10a are formed beforehand at both end portions respectively of the wedge tool lest both end portions in the width direction of the Al ribbon bonded to the pad should contact the pressure bonding surface of the wedge tool.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2009-96165 filed on Apr. 10, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a manufacturing technique for the same. Particularly, the present invention is concerned with a semiconductor device wherein a bonding pad of a semiconductor chip and a lead frame are coupled together using a metallic ribbon, as well as a technique effectively applicable to the manufacture thereof.

A semiconductor chip having formed thereon power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) each used for example as a power control switch or a charge/discharge protecting circuit switch in a portable information device, is sealed in a small-sized surface mount package such as a flat lead package or a SOP-8.

A back surface of the above semiconductor chip configures a drain of the power MOSFETs and is bonded onto a die pad portion of a lead frame through a conductive adhesive such as Ag paste. In a top layer of a main surface of the semiconductor chip there is formed a source pad coupled to sources of the power MOSFETs and a gate pad coupled to gate electrodes of the same transistor. The source pad is formed at a wider area than the gate pad in order to decrease ON resistance of the power MOSFETs.

Plural leads which configure external coupling terminals are exposed to the exterior of molding resin which seals the semiconductor chip. These leads comprise source, drain and gate leads. The drain leads are integral with the die pad portion and are electrically coupled to the back surface of the semiconductor chip (drain of the power MOSFETs) mounted on the die pad portion.

Recently, in the surface mount package of the above structure, the technique of coupling a source pad and source leads with use of a flexible metallic ribbon has been adopted practically in order to decrease ON resistance of the power MOSFETs.

The metallic ribbon is formed for example by Al (aluminum) foil or Cu (copper) foil having a thickness of several hundred μm or so and the width thereof is generally 1 mm or so though it differs depending on the source pad width. For coupling the metallic ribbon to the source pad or source leads there is used a wedge bonding method which utilizes ultrasonic vibration.

The metallic ribbon is advantageous in that the ribbon width is much larger than the diameter of Au (gold) wire and that therefore even with a single metallic ribbon it is possible to ensure a sufficient coupling area for the source pad and ON resistance of the power MOSFETs can be greatly reduced as compared with the case where both source pad and source leads are coupled together using plural Au wires. Besides, there also is an effect that the cost of the package material can be reduced because the ribbon is formed by Al which is cheaper than Au.

Patent Document 1 discloses an improved technique of a wedge tool used for coupling the above metallic ribbon. In a lower surface of the wedge tool described in Patent Document 1 there are formed plural grooves or notches in parallel with the extending direction of the metallic ribbon. Therefore, when the wedge tool is brought into pressure contact with the metallic ribbon disposed on a semiconductor chip, only a part of the tool lower surface comes into contact with the metallic ribbon. Consequently, the propagation of excessive ultrasonic vibration energy from the wedge tool to the surface of the semiconductor chip can be prevented and hence the occurrence of damage such as a crack or a fissure in the semiconductor chip is decreased.

In Patent Document 2 is disclosed a wedge tool for ribbon bonding wherein plural projections and plural grooves each formed between adjacent such projections are formed on a pressure bonding surface.

In Patent Document 3 is disclosed a wedge tool for ribbon bonding wherein plural projections are formed on a pressure bonding surface. In each of the plural projections, two side faces opposed to each other are inclined relative to the pressure bonding surface, while other two side faces adjacent to the two side faces are nearly perpendicular to the pressure bonding surface.

In Patent Document 4 is disclosed a technique wherein projections are formed by knurling on a pressure bonding surface of a wedge tool for ribbon bonding, then the projections are pushed onto a metallic ribbon in ultrasonic bonding to apply a pushing load and ultrasonic vibration to the metallic ribbon, thereby forming ultrasonically bonded portions corresponding to a required energizing capacity dispersedly in an overlapped surface area between a heat spreader and the metallic ribbon.

In Patent Document 5 is disclosed a technique wherein one or plural loops are formed in a metallic ribbon when bonding the ribbon to a pad.

PRIOR ART DOCUMENTS

Patent Document 1

Patent Document 2

Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-529303

Patent Document 3

Patent Document 4

Patent Document 5

SUMMARY OF THE INVENTION

For bonding a metallic ribbon to a source pad on a semiconductor chip having powder MOSFETs formed thereon, first a front end portion of the metallic ribbon is positioned above the source pad on the semiconductor chip, the bottom (a pressure bonding surface) of a wedge tool is brought into pressure contact with the metallic ribbon and ultrasonic vibration is applied to the ribbon. As a result, the metallic ribbon is crushed at the region where it is in contact with the bottom of the wedge tool, and is bonded to the surface of the source pad.

However, if an attempt is made to increase the number of semiconductor devices obtained from a semiconductor wafer for the purpose of cost reduction, external dimensions of a semiconductor chip become smaller and so does the area of a source pad. To carry out bonding while forming a stable loop for the source pad thus reduced in area, it is necessary to reduce the thickness of the metallic ribbon.

However, if the thickness of the metallic ribbon is reduced, the metallic ribbon becomes easier to break when bonded to the source pad surface, because the thickness of its portion crushed by the wedge tool becomes extremely small.

For preventing such breaking of the metallic ribbon it is necessary to make some improvement for the wedge tool. However, in any of Patent Documents 1 to 5 there is found no description about a technique for bonding a metallic ribbon stably to such a fine pad.

It is an object of the present invention to provide a technique which, in the manufacture of a semiconductor device including the step of bonding a metallic ribbon to a pad on a semiconductor chip, can prevent breaking of the metallic ribbon while ensuring a required bonding strength even in the case where the metallic ribbon becomes thin as a result of reduction in size of the semiconductor chip.

The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.

The following is a brief description of typical inventions out of the inventions disclosed in the present application.

In one aspect of the present invention there is provided a semiconductor device comprising a semiconductor chip, a first conductor disposed near the semiconductor chip, and a metallic ribbon for coupling a pad formed over a main surface of the semiconductor chip and the first conductor electrically with each other, wherein the metallic ribbon coupled to the pad of the semiconductor chip is thicker at its both end portions in its width direction than its portion located inside the both end portions.

In another aspect of the present invention there is provided a method for manufacturing a semiconductor device, comprising the step of bonding a metallic ribbon to a pad formed over a main surface of a semiconductor chip, wherein a wedge tool is used in the bonding step and it is formed with recesses at both end portions respectively of a pressure bonding surface thereof opposed to both end portions in the width direction of the metallic ribbon.

The following is a brief description of an effect obtained by the above typical inventions.

Even when the thickness of the metallic ribbon becomes smaller with reduction in size of the semiconductor chip, it is possible to prevent breaking of the metallic ribbon while ensuring a required bonding strength.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below in detail with reference to the drawings. In all of the drawings for illustrating the embodiments, the same members are identified by the same reference numerals in principle and repeated explanations thereof will be omitted.

In the following embodiments, explanations of the same or similar portions will not be repeated in principle except when such explanations are specially needed. In the drawings for illustrating the following embodiments, even a plan view may be hatched to make the illustrated configuration easier to understand.

In the following embodiments, by the term “Al ribbon” is meant a band-like wiring material configured by a conductive material containing Al as a principal component. Usually, Al ribbon is installed in a spooled state onto a bonding device. Al ribbon is extremely thin, so is characteristic in that when coupling it to a lead frame or to a pad on a semiconductor chip, its length and loop shape can be set arbitrarily.

First Embodiment

The semiconductor device of this embodiment is applied to a flat lead package (hereinafter referred to as FLP) which is a kind of a surface mount package.FIG. 1(a) is a plan view showing an upper surface of the FLP,FIG. 1(b) is a side view on a short side,FIG. 2is a plan view showing a back surface (component side),FIG. 3is a plan view showing an internal structure, andFIG. 4is a sectional view taken along line A-A inFIG. 3.

The FLP is a small-sized surface mount package wherein a semiconductor chip1mounted on a die pad portion3D of a lead frame is sealed with molding resin2. Its external dimensions are long side=6.1 mm, short side=5.3 mm, and thickness=0.8 mm.

Eight leads3(#1 to #8) which configure external coupling terminals of the FLP are exposed to short sides of the molding resin2, the molding resin2being an epoxy resin impregnated with silicon filler. Of these leads, shown inFIGS. 1 and 2, No. 1 lead (#1) to No. 3 lead (#3) are source leads, No. 4 lead (#4) is a gate lead, and No. 5 lead (#5) to No. 8 lead (#8) are drain leads. Back surfaces of the eight leads3and a back surface of the die pad3D are exposed to the exterior on a back surface of the molding resin2for the dissipation of heat generated in the semiconductor chip1and for the improvement of the package heat dissipating property. A three-layer plating as a laminate of Ni (nickel) film, Pd (palladium) film and Au (gold) film is applied surfaces of the die pad portion3D and the eight leads3.

Of the eight leads3, the three source leads (#1 to #3) are coupled with one another in the interior of the molding resin2. That is, the three source leads (#1 to #3) are coupled together electrically. The source leads positioned in the interior of the molding resin2will hereinafter be referred to as the source post3S. Likewise, in the gate lead (#5), the portion positioned in the interior of the molding resin2will hereinafter be referred to as the gate post3G. On the other hand, the four drain leads (#5 to #8) are formed integrally with the die pad portion3D in the interior of the molding resin2.

The semiconductor chip1is mounted on the die pad portion D through a conductive adhesive4such as, for example, Ag paste or solder. The semiconductor chip1is formed by a single crystal silicon and on a main surface thereof are formed plural power MOSFETs (power elements) each used for example as a power control switch or a charge/discharge protecting circuit switch in a portable information device. A back surface of the semiconductor chip1configures a drain common to those power MOSFETs and is coupled to the drain leads (#5 to #8) electrically through the die pad portion3D.

On the main surface of the semiconductor chip1are formed one gate pad5coupled electrically to gate electrodes of the power MOSFETs and two source pads6coupled electrically to sources of the power MOSFETs. The gate pad5is coupled electrically to the gate post3G through an Au wire7. On the other hand, each of the two source pads6is formed at a wider area than the gate pad5to decrease ON resistance of the power MOSFETs and is coupled electrically to the source post3S through an Al ribbon8which has a wider area than the Au wire7.

FIG. 5is a sectional view of a principal portion, showing trench gate type n-channel power MOSFETs.

An n−type single crystal silicon layer31is formed on a main surface of an n+type single crystal silicon substrate30and a p type semiconductor region32is formed in an upper portion of the n−type single crystal silicon layer31, further, n+type semiconductor regions33are formed on a surface of the p type semiconductor region32. The n+type single crystal silicon substrate30and the n−type single crystal silicon layer31are semiconductor regions which configure a drain of the power MOSFETs and the n+type semiconductor regions33are semiconductor regions which configure sources of the power MOSFETs. The p type semiconductor region32is a semiconductor region wherein channels of the power MOSFETs are formed.

In part of the p type semiconductor region32are formed trenches34whose bottoms reach the n−type single crystal silicon layer (drain)31. In the interior of each trench34are formed a gate insulating film35and a gate electrode36. The gate insulating film35is formed by a silicon oxide film, while the gate electrode36is formed by an n type polycrystalline silicon film. An upper end portion of each gate electrode36projects upwards above the trench34and side wall spacers37each formed by a silicon oxide film are formed on both sides of the upper end portion of the gate electrode. On top of the gate electrode36are formed a silicon nitride film38and a silicon oxide film39.

A source electrode41and a gate lead electrode42are formed over the silicon oxide film39. The source electrode41and the gate lead electrode42are each formed by a conductive film comprising a barrier metal film43and an Al alloy film44deposited thereon, the barrier metal film43being a laminated film of both Ti film and TiN film. The source electrode41is coupled electrically to the sources (n+type semiconductor regions33) of the power MOSFETs through coupling holes45formed in the silicon nitride film38and the silicon oxide film39. The gate lead electrode42is coupled electrically to the gate electrodes36of the power MOSFETs through coupling holes formed in the silicon nitride film38and the silicon oxide film39in a region (not shown).

A surface protecting film46formed by a laminated film of both silicon oxide film and silicon nitride film is formed over the source electrode41and the gate lead electrode42. A part of the surface protecting film46which covers the top of the source electrode41is removed, allowing the source electrode41to be exposed to the surface of the semiconductor chip1. Likewise, a part of the surface protecting film46which covers the top of the gate lead electrode42is removed, allowing the gate lead electrode42to be exposed to the surface of the semiconductor chip1. The exposed region of the source electrode41exposed to the surface of the semiconductor chip1configures the source pad6and the exposed region of the gate lead electrode42exposed to the surface of the semiconductor chip1configures the gate pad5. Though not shown inFIG. 5, the Al ribbon8is bonded to surfaces of the source pads6and the Au wire7is bonded to a surface of the gate pad5.

FIG. 6is a plan view showing a layout of gate lead electrodes42, gate pad5and source pads6.

A planar shape of the semiconductor chip1is a rectangular shape having a long side length of 1.6 mm and a short side length of 1.0 mm. A planar shape of each of the two source pads6(6a,6b) is a rectangular shape having a long side length of 1.02 mm and a short side length of 0.225 mm. Further, a planar shape of the gate pad5is a square shape with a one-side length of 0.12 mm.

The gate lead electrodes42are disposed at both outer periphery portion and central portion respectively of the main surface of the semiconductor chip1. The gate pad5is disposed at one end of the gate lead electrode42disposed centrally of the semiconductor chip1. In the case where the gate lead electrodes42and the gate pad5are thus disposed on the main surface of the semiconductor chip1, one end of the gate electrode36in each of the power MOSFETs extends rectilinearly toward the nearby gate lead electrode42and is coupled to the gate lead electrode42electrically, as shown inFIG. 7(a perspective view showing a layout of gate electrodes36in the region indicated by the symbol B inFIG. 6). Thus, the gate electrodes36can be made shortest in length throughout the whole of the semiconductor chip1. Consequently, gate resistance (Rg) is reduced to half or less and the switching characteristic of the power MOSFETs is improved, in comparison with for example a layout wherein one source pad6is disposed centrally of the semiconductor chip1and the gate pad5is disposed at the peripheral portion.

On the other hand, when a gate lead electrode42is disposed centrally of the semiconductor chip1, source electrodes41each configured by a conductive film in the same layer as the gate lead electrode42are formed on both sides of the gate lead electrode42. Therefore, source pads6are also disposed on both sides respectively of the gate lead electrodes42.

Thus, in the FLP of this embodiment, in order to improve the switching characteristic of the power MOSFETs, a gate lead electrode42is disposed centrally of the semiconductor chip1to minimize the length of each gate electrode36coupled to the gate electrode42, thereby decreasing the gate resistance (Rg). Consequently, two source pads6are disposed on both sides respectively of the gate lead electrode42. Accordingly, one end of the Al ribbon8which couples the source post3S and the semiconductor chip1electrically with each other is bonded to surfaces of the two source pads6.

The following description is now provided about a problem encountered in case of bonding the Al ribbon8to the two source pads6on the semiconductor chip1with use of a wedge tool in a conventional ribbon bonding device.

For bonding the Al ribbon8to the two source pads6, first, as shown inFIG. 8, a front end portion of the Al ribbon is positioned on a first source pad6on the semiconductor chip1, then a pressure bonding surface of a wedge tool20is brought into pressure contact with the Al ribbon8and ultrasonic vibration with energy of several W or so is applied to the Al ribbon. As a result, the Al ribbon8is crushed in its area which is in contact with the pressure bonding surface of the wedge tool20, and is bonded to a surface of the first source pad6. Next, the wedge tool20is moved onto a second source pad6, then, as shown inFIG. 9, the pressure bonding surface of the wedge tool20is brought into pressure contact with the Al ribbon8and ultrasonic vibration with energy of several W is applied to the ribbon. As a result, the Al ribbon is crushed in its area which is in contact with a bottom of the wedge tool20, and is bonded to a surface of the second source pad6.

As noted above, the gate lead electrode42coupled to the gate pad5is disposed between the two source pads6. Therefore, when bonding the Al ribbon8to the two source pads6with use of the wedge tool20, as shown inFIG. 9, the Al ribbon8between the two source pads6is looped to avoid bonding damage to the gate lead electrode42. At this time, if the height of the loop is made low, then at the time of sealing the semiconductor chip1with molding resin2, the molding resin2cannot get into the gap between the surface of the semiconductor chip1and the Al ribbon8, with consequent fear of formation of a void. In many cases, water stays in such a void and undergoes volume expansion under solder reflow at the time of mounting the semiconductor device onto a wiring substrate, thus causing an inconvenience such as package cracking for example. To avoid the occurrence of such an inconvenience it is necessary to adjust the loop height so that the molding resin2can get into the gap between the semiconductor chip1and the Al ribbon8.

However, in the FLP of this embodiment, the external dimensions of the semiconductor chip1are very small and hence the spacing between the two source pads6is very narrow. Therefore, for forming a loop in the Al ribbon which straddles the two source pads6, it is necessary that the thickness of the Al ribbon be as small as 0.1 mm or less, preferably 0.05 mm or less.

However, if the Al ribbon8is made so thin, then when the Al ribbon8is bonded to the surface of a source pad6, the thickness of the portion crushed by the wedge tool20becomes extremely small, with the result that cracks are developed at both axial ends (the portions indicated by arrows inFIG. 9) of the Al ribbon8, which cracks may advance inwards from the both ends, leading to breakage of the Al ribbon8.

Moreover, if a loop is formed between the two source pads6which are spaced narrow from each other, the rise of the loop becomes very steep, so that a strong bending stress is imposed on the Al ribbon8at the loop rising area. Therefore, in case of bonding the extremely thin Al ribbon8to the two source pads6which are disposed in close proximity to each other, the Al ribbon is apt to break particularly on the first source pad6.

In this embodiment, in view of the above-mentioned problem, bonding of the Al ribbon8is performed using the following wedge tool.

FIG. 10(a) is a plan view of the wedge tool used in this embodiment, as seen from below,FIG. 10(b) is a plan view showing a pressure bonding surface of the wedge tool,FIG. 11(a) is a perspective view showing a front end portion of the wedge tool, andFIG. 11(b) is a side view thereof. InFIG. 11(b) there also is shown a sectional structure of the Al ribbon with which the wedge tool is in pressure contact.

The wedge tool used in this embodiment is configured by metal such as stainless steel (SUS304) and its pressure bonding surface has a rectangular plane shape. The length of each long side of the pressure contact surface is larger than the width of the Al ribbon8and smaller (by say 0.89 mm to 0.9 mm or so) than each long side of each source pad6. The length of each short side of the pressure contact surface is smaller (by say 0.09 mm or so) than each short side of each source pad6.

The wedge tool10used in this embodiment has recesses10a(first recesses) at both longitudinal ends of the pressure contact surface. On the other hand, three convex portions10care formed centrally of the pressure contact surface in a sandwiching relation to two shallow recesses10b(second recesses). A difference in height, La, between each convex portion10cand each recess10ashown inFIG. 11(b) is set so as to be larger than the thickness of the Al ribbon8. For example, if the thickness of the Al ribbon8is 0.05 mm, the difference in height between each convex portion10cand each recess10ais about 0.06 mm. Therefore, when the pressure bonding surface of the wedge tool10is brought into pressure contact with the Al ribbon8, both end portions of the pressure contact surface do not come into contact with the Al ribbon8.

That is, as shown inFIG. 11(b), the recesses10aformed at both end portions of the pressure bonding surface of the wedge tool10are regions opposed to both end portions (thick film portions8a) in the width direction of the Al ribbon8. It follows that when the pressure bonding surface of the wedge tool10comes into pressure contact with the Al ribbon8, both end portions (thick film portions8a) in the width direction of the Al ribbon8do not contact the wedge tool10.

The two shallow recesses10bformed centrally of the pressure bonding surface of the wedge tool10are for relieving stress applied to the central part (thin film portions8c) of the Al ribbon8to the environs (thick film portions8a,8b). The depth of each of the shallow grooves10b, i.e., a difference in height, Lb, between each convex portion10cand each recess10bshown inFIG. 11(b), is smaller than the difference in height La between each convex portion10cand each recess10a, (La>Lb). That is, the thick film portions8band the thin film portions8cof the Al ribbon correspond to the shallow recesses10band the convex portions10crespectively of the wedge tool10and the thickness of the Al ribbon8is such that thick film portion8a>thick film portion8b>thin film portion8c.

The shallow recesses10bformed in the pressure bonding surface are not essential. For example, as shown inFIG. 12, a convex portion10cmay be formed throughout the whole of the central part. Alternatively, as shown inFIG. 13, a single shallow recess10bmay be formed at a central position. In both cases, by forming the recesses10aat both end portions of the pressure bonding surface, there is no fear of cracks being developed in both end portions (thick film portions8a) of the Al ribbon8. Thus, it is possible to prevent a crack from advancing inwards of the Al ribbon8and causing breakage of the ribbon.

FIG. 14is a side view showing a front end portion and the vicinity thereof of the wedge tool10as loaded to a ribbon bonding device. As shown in the same figure, a ribbon guide11for sending out the Al ribbon8to the pressure bonding surface of the wedge tool10is attached to one side face of the wedge tool10. Likewise, a cutter12for cutting the Al ribbon10after completion of bonding is attached to the other side face of the wedge tool10.

Next, a description will be given below about a method for manufacturing the FLP, including a bonding step of the Al ribbon8with use of the wedge tool10described above.FIG. 15is an entire flow chart showing a manufacturing process for the FLP.

For manufacturing the FLP of this embodiment, first, as shown inFIGS. 16 and 17, a semiconductor chip1is mounted onto a die pad portion3D of a lead frame LF with use of a conductive adhesive4such as, for example, Ag paste or solder (Die Bonding).

Next, as shown inFIGS. 18 and 19, the front end portion of the Al ribbon delivered from the ribbon guide11is positioned on the first source pad6of the semiconductor chip1, then the pressure bonding surface of the wedge tool10is brought into pressure contact with the Al ribbon8and ultraviolet vibration with energy of several W or so is applied to the ribbon. As a result, the Al ribbon8is crushed at its area in contact with the convex portions10cformed on the pressure bonding surface of the wedge tool10and is bonded to the surface of the first source pad6. As noted above, since recesses10aare formed in both end portions of the pressure bonding surface of the wedge tool10, both end portions in the width direction of the Al ribbon8bonded to the source pad6are not in contact with the pressure bonding surface of the wedge tool10. Therefore, cracks are not developed in both end portions of the Al ribbon8and hence it is possible to prevent cracks from advancing inwards of the Al ribbon8and causing breakage of the ribbon.

Next, the Al ribbon located between two source pads6is looped while moving the wedge tool10onto the second source pad6, then, as shown inFIGS. 20 and 21, the pressure bonding surface of the wedge tool10is brought into pressure contact with the Al ribbon8and ultraviolet vibration with energy of several W or so is applied to the ribbon. As a result, the Al ribbon8is crushed at its area in contact with the convex portions10cformed on the pressure bonding surface of the wedge tool10and is bonded to the surface of the second source pad6. Also at this time, both end portions in the width direction of the Al ribbon8bonded to the second source pad6are out of contact with the pressure bonding surface of the wedge tool10. Thus, also in the bonding of the second source pad6, cracks are not developed in both end portions of the Al ribbon8and hence it is possible to prevent cracks from advancing inwards of the Al ribbon8and causing breakage of the ribbon.

As noted earlier, if the Al ribbon8is looped at its position between the two source pads6, the rise of the loop becomes very steep, so that a strong bending stress is imposed on the Al ribbon8at the loop rising area. As a result of this strong bending stress imposed on the Al ribbon8, there may occur breakage of the ribbon. According to an effective measure for relaxing this bending stress, as shown inFIG. 22, with respect to each of the recesses10bformed in the pressure bonding surface of the wedge tool10, the radius of curvature (R1) of its corner positioned close to the source post3S (close to the loop) is made larger than the radius of curvature (R2) of its corner positioned on the front end side of the Al ribbon8, (R1>R2). By so doing, with respect to each of the thick film portions8bof the Al ribbon8, the radius of curvature of its corner positioned close to the source post3(close to the loop) becomes larger than the radius of curvature of its corner positioned on the opposite side (the front end side of the Al ribbon8), so that the bending stress imposed on the Al ribbon8is dispersed. On the other hand, by making small the radius of curvature (R2) of the corner positioned on the front end side of the Al ribbon8, it is possible to ensure a required area of bonding between the Al ribbon8and each source pad6.

Next, as shown inFIG. 23, the wedge tool10is moved onto the source post3S of the lead frame LF, then its pressure bonding surface is brought into pressure contact with the Al ribbon8, and the Al ribbon8is bonded to the surface of the source post3S in the same manner as above. Subsequently, as shown inFIG. 24, the Al ribbon8is cut with the cutter12, whereby the ribbon bonding step of coupling the source post3S with the two source pads6electrically by the Al ribbon8is completed.

In this way the above ribbon bonding step is repeated to couple the source pads6and the source post3S electrically with each other by the Al ribbon8with respect to all the semiconductor chips1mounted on the ribbon frame LF, as shown inFIG. 25. Thereafter, as shown inFIG. 26, the gate pads5and the gate posts3G of all the semiconductor chips1mounted on the lead frame LF are coupled together electrically by means of a known ball bonding device and using Au wires7.

The bonding step using the Al ribbon8and the bonding step using the Au wire7may be done in reverse order from the above. That is, bonding of the Al ribbon8may be done after bonding of the Au wire7. However, since the width and thickness of the Al ribbon8are each larger than the diameter of the Au wire7, the vibration energy exerted on the semiconductor chip1when bonding the Al ribbon8is larger than that exerted on the semiconductor chip1when bonding the Au wire7. Therefore, if bonding of the Al ribbon8is performed after bonding of the Au wire7, the bonding strength between the Au wire and the gate pad5decreases due to the vibration energy applied to the chip when bonding the Al ribbon8. As the case may be, there is a fear of disengagement of the Au wire7from the gate pad5. There also is a fear that the wedge tool10used in bonding the Al ribbon8may come into contact with the Au wire7, damaging or cutting the wire. Accordingly, it is preferable that the bonding of Au wire7be done after the bonding of Al ribbon8.

Next, the semiconductor chips1, Al ribbons8, Au wires7, portions of leads3and portions of the die pads3D are sealed with molding resin2, then product names, etc. are printed on the surface of the molding resin2by a laser marking method, thereafter, unnecessary lead frame LF portions exposed to the exterior of the molding resin2are cut and resin burrs are removed, and finally a testing step of determining whether the products thus obtained are good or not is carried out. In this way the FLP of this embodiment shown inFIGS. 1 to 4is completed.

Thus, in this embodiment, the recesses10aare formed in both end portions of the pressure bonding surface of the wedge tool10lest both end portions in the width direction of the Al ribbon8should contact the pressure bonding surface of the wedge tool10. Therefore, even when the extremely thin Al ribbon8is bonded to the two source pads6disposed close to each other, it is possible to prevent breakage of the Al ribbon8while ensuring a required coupling strength between the Al ribbon8and the source pads6.

Moreover, since the radius of curvature (R1) of a corner portion at the pressure bonding surface of the wedge tool10is made large, the bending stress imposed on the Al ribbon8due to a steep rise of a ribbon loop can be suppressed and hence it is possible to prevent breakage of the Al ribbon8in a more positive manner.

Further, since both end portions of the pressure bonding surface of the wedge tool10do not come into contact with the Al ribbon8, even when using the wedge tool10repeatedly, deterioration of the pressure bonding surface caused by the deposition of Al powder produced from the Al ribbon8is suppressed and hence it is possible to prolong the service life of the wedge tool10.

Second Embodiment

According to an FLP of this second embodiment, as shown inFIG. 27, the source pads6of the semiconductor chip1and the source post3S may be coupled together using plural Al ribbons8. In the illustrated example, the source pads6and the source post3are coupled together using two Al ribbons8. The number of Al ribbons8for coupling the source pads6and the source post3S may be three or more.

In the FLP, the size of the semiconductor chip1differs depending on product type or generation and so does the size of each source pad6. However, if plural types of Al ribbons8different in width are to be provided according to sizes of source pads6, management of the Al ribbons8becomes complicated. On the other hand, as in this embodiment, if one type of Al ribbon8of a relatively narrow width is provided and the number of such Al ribbons to be used is changed according to the size of the source pad6used, management of the Al ribbon is not complicated.

Also in case of manufacturing the FLP of this embodiment there can be obtained the same effect as in the previous first embodiment by using the above wedge tool10in the Al ribbon8bonding step.

Third Embodiment

Generally, in the manufacturing process for a resin-sealed type semiconductor device including FLP there is used a lead frame LF having plural die pad portions3D as inFIG. 16.

When the source pads6of plural semiconductor chips1mounted on such a lead frame LF are to be coupled with source posts3S through Al ribbons8, the bonding time can be shortened by combining plural wedge tools10and coupling Al ribbons8simultaneously to the source pads6on plural semiconductor chips1, as shown inFIG. 28.

Also in this case, the same effect as in the first embodiment can be obtained by using the combined wedge tool10.

Although the present invention has been described above by way of embodiments, it goes without saying that the present invention is not limited to the above embodiments and that various changes may be made within the scope not departing from the gist of the invention.

Although in the above embodiments there was used Al ribbon as a conductive material for coupling between the source pads and the source post, there also may be used ribbons made of other materials small in electric resistance such as, for example, Au or Cu alloy. Moreover, as the gate post—gate pad coupling conductive material there also may be used a wire made of any other material than Au, e.g., Al wire or Cu wire.

Although in the above embodiments a semiconductor chip is mounted on the die pad portion with use of Ag paste, there also may be used any other material for mounting as pellet than Ag paste, e.g., solder paste or solder ribbon. Further, the chip mounting portion of the die pad portion3D may be plated with solder. In case of performing soldering by solder ribbon or solder plating, it is possible to ensure required solder wettability by also using an activating agent such as flux for example. In case of coupling a semiconductor chip with solder, both wettability of solder and couplability with solder can be ensured by metalizing a soldering surface (back surface of the chip) with Ni/Au for example.

Although in the above embodiments FLP was shown as an example of a resin package for sealing the semiconductor chip formed with power MOSFETs, the present invention is applicable also to a SOP-8 for example.

FIG. 29is a plan view showing an upper surface of a SOP-8. The SOP-8, like FLP, is also a kind of a small-sized surface mount package and the pin layout of eight leads23exposed to the exterior of the molding resin22is also the same as in FLP, but each of the leads23is formed in a gull wing shape.FIG. 30is a plan view showing an internal structure of a SOP-8 wherein the semiconductor chip1used in the first embodiment is sealed with molding resin22. Also in this case, by using the wedge tool described in the previous embodiments at the time of coupling the source pads6and a source post23S with use of the Al ribbon8, it is possible to prevent breakage of the Al ribbon8while ensuring the bonding strength of the ribbon.

Although in the above embodiments a description has been given about the case where the Al ribbon is bonded to the semiconductor chip having two (plural) source pads, the present application is applicable also to the case where the Al ribbon8is bonded to a semiconductor chip1having one source pad6, as shown inFIG. 31. That is, as the semiconductor chip size becomes extremely small, the source pad—source post spacing also becomes narrow and a loop of the Al ribbon formed between the source pad and the source post becomes steep. Therefore, for preventing breakage of the Al ribbon while ensuring the bonding strength of the ribbon, the use of the wedge tool described in the above embodiments is effective.

Further, although in the above embodiments the Al ribbon is bonded to the source pads of the semiconductor chip formed with power MOSFETs, semiconductor chips formed with other elements than power MOSFETS are also employable if only they have a pad capable of being bonded with the Al ribbon. For example, in the case of a semiconductor chip formed with insulated gate bipolar transistors (IGBTs), the present invention can be applied thereto also in case of bonding the Al ribbon to an emitter pad because the emitter pad is formed at a wider area than a gate pad in order to decrease ON resistance of the IGBTs.

The present invention is applicable to a semiconductor device wherein a bonding pad of a semiconductor chip and a lead frame are coupled together using a metallic ribbon.