Static random access memories including a silicon-on-insulator substrate

Static random access memories (SRAMs) include a semiconductor substrate having a buried insulator in a predetermined portion of the semiconductor substrate and a silicon-on-insulator (SOI) region including a semiconductor layer on the buried insulator. A flip-flop circuit is in the SOI region and a pass transistor connected to the flip-flop circuit is on a bulk region of the semiconductor substrate. The bulk region of the semiconductor substrate is a separate region from the SOI region. The flip-flop circuit may include at least two CMOS inverters and the pass transistor may be a plurality of pass transistors.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 2003-68995, filed on Oct. 4, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

The present invention relates to integrated circuit devices, and more particularly, to integrated circuit memory devices.

Static random access memories (SRAMs) are typically high speed memory devices, with relatively low power consumption, which generally do not need to refresh data. SRAMs may be effectively employed in mobile equipment, such as cellular phones. Generally, SRAM memory cells include two inverters that form a flip-flop circuit to which two pass transistors are coupled. Conventional SRAM cells may be classified into load SRAM and CMOS SRAM. In load SRAM, pull down transistors and a load coupled to the pull down transistors are generally included in inverters, which, in turn, form a flip-flop circuit. A resistor or a thin film transistor may be used as the load. In CMOS SRAM, pull up transistors and pull down transistors, that is, CMOS transistors including PMOS and NMOS transistors, are generally included in inverters, which, in turn, form a flip-flop circuit. The CMOS structure, in which SRAM cells are configured using a CMOS process, may be useful because CMOS SRAM devices generally have superior electrical characteristics in comparison to load SRAM.

Problems may arise when configuring SRAM cells using a CMOS process. For example, it may be difficult to scale down the size of SRAM cells. When configuring SRAM cells in a CMOS process, six transistors may be integrated into a single SRAM cell, and NMOS and PMOS transistors coexist in the single SRAM cell. Therefore, a relatively large space may be required for the SRAM cell.

In addition, a complicated well structure may be needed for separating the NMOS transistors from the PMOS transistors, which may increase the size of the SRAM cell. For example, an N-well for a PMOS transistor would typically be formed within a P-well for an NMOS transistor. The N-well may be formed in a bulk substrate and surround at least the PMOS transistor, which may create a large gap between the NMOS and PMOS transistors. In this regard, there have been numerous studies and attempts to come up with ways to limit an increase in the overall size of SRAM cells caused by such a complicated well structure when configuring SRAM cells for a CMOS process.

Another possible problem is latch-up, which is a problem related to the coexistence of NMOS and PMOS transistors in an SRAM cell configured in a CMOS process. Furthermore, as a gate is scaled down, a soft error rate (SER), which indicates reliability, an important characteristic of SRAMs, may increase.

SUMMARY OF THE INVENTION

Embodiments of the present invention include SRAMs in a semiconductor substrate having a buried insulator in a predetermined portion of the semiconductor substrate and a silicon-on-insulator (SOI) region including a semiconductor layer on the buried insulator. A flip-flop circuit is provided in the SOI region and a pass transistor connected to the flip-flop circuit is provided on a bulk region of the semiconductor substrate. The bulk region of the semiconductor substrate is a separate region from the SOI region.

In some embodiments of the present invention, the flip-flop circuit includes at least two CMOS inverters and the pass transistor is a plurality of pass transistors. The semiconductor substrate may be a P type semiconductor substrate and the buried insulator may be a thermal oxide layer with a thickness of about 500 angstroms (Å) to about 4000 Å. The semiconductor layer may have a maximum thickness of about 2000 Å.

In other embodiments of the present invention, an active region is defined in a portion of the semiconductor layer including one of the CMOS inverters and extends to the bulk region of the semiconductor substrate including one of the pass transistors such that an output terminal of the one of the CMOS inverters shares a same active region with source/drain terminals of the one of the pass transistors.

In further embodiments of the present invention, a first isolation layer is provided on the buried insulator in the semiconductor layer and separates devices in the SOI region. A second isolation layer is provided at a boundary between the SOI region and the bulk region. The second isolation layer is configured to allow the active region to extend to the bulk region and extends deeper than the buried insulator. The first isolation layer may be a chemical vapor deposition oxide layer and/or a chemical vapor deposition nitride layer. The second isolation layer may have a maximum thickness of approximately 3000 Å and may be a shallow trench isolation layer. The SRAM may further include a well contact node electrically connected to the semiconductor substrate in the bulk region below one of the pass transistors that controls a potential of a channel region of the one of the pass transistors to reduce a floating body effect in the SOI region.

In other embodiments of the present invention, an SRAM includes a semiconductor substrate having a buried insulator in a predetermined portion of the semiconductor substrate and a silicon-on-insulator (SOI) region including a semiconductor layer on the buried insulator. A flip-flop circuit is provided in the SOI region and a plurality of pass transistors are connected to the flip-flop circuit and provided on a bulk region of the semiconductor substrate, the bulk region of the semiconductor substrate being a separate region from the SOI region. A first isolation layer defines an active region. The active region includes a main part crossing the SOI region, a first branch protruding from the main part and a second branch protruding from the main part in a direction opposite to the first branch and from a different position of the main part from where the first branch protrudes. A second isolation layer forms a boundary between the SOI region and the bulk region, the second isolation layer being configured to allow the active region to extend to the bulk region. The flip-flop circuit includes a first CMOS inverter including an NMOS transistor and a PMOS transistor and a second CMOS inverter configured as a mirror image of the first CMOS inverter and including an NMOS transistor and a PMOS transistor, the second CMOS inverter being in the main part and the second branch of the active region. The pass transistors each include N+-type source/drain regions on the active region and connected to the flip-flop circuit and a gate that crosses the active region between the N+-type source/drain regions. At least one of the NMOS transistors includes N+-type source/drain regions in the main part of the active region and a gate crossing the active region between the N+-type source/drain regions of the at least one of the NMOS transistors and extending across the active region between P+-type source/drain regions in the first or second branch of the active region adjacent to the N+-type source/drain regions of the at least one of the NMOS transistors. The PMOS transistor of at least one of the CMOS inverters includes the P+-type source/drain regions in the first or second branch of the active region adjacent to the first N+-type source/drain regions of the at least one of the NMOS transistors and the first gate of the at least one of the NMOS transistors.

In further embodiments of the present invention, the second isolation layer is deeper than the first isolation layer and the buried insulator. The second isolation layer may be configured to allow both ends of the active region to extend to the bulk region in opposite directions from each other. One of the N+-type source/drain regions of the NMOS transistors may directly contact one of the P+-type source/drain regions. A different one of the N+-type source/drain regions of the NMOS transistors and a different one of the P+-type source/drain regions may be separated by the first isolation layer. One of the N+-type source/drain regions of the NMOS transistors may directly contact one of the N+-type source/drain regions of the pass transistors. A well contact node may be electrically connected to the semiconductor substrate of the bulk region below at least one of the pass transistors that controls a potential of a channel region of the at least one of the pass transistors to reduce a floating body effect in the SOI region.

In other embodiments of the present invention, an SRAM includes a semiconductor substrate having a buried insulator in a predetermined portion of the semiconductor substrate and an SOI region including a semiconductor layer on the buried insulator. A flip-flop circuit including two CMOS inverters is provided in an SOI region and two pass transistors are connected to the flip-flop circuit and provided on a bulk region of the semiconductor substrate. A first isolation layer defines a first active region and a second active region. The first active region includes a main part crossing the SOI region, a first branch that protrudes from the main part, and a second branch that protrudes from the main part in the same direction as the first branch and from a different region of the main part from where the first branch protrudes. The second active region is a mirror image of the first active region. A second isolation layer that allows the first and second active regions to extend to the bulk region is provided at the boundary between the SOI region and the bulk region.

The flip-flop circuit includes a first CMOS inverter including an NMOS transistor and a PMOS transistor in the first active region, and a second CMOS inverter configured as a mirror image of the first CMOS inverter and including an NMOS transistor and a PMOS transistor in the second active region. The two pass transistors each include first N+-type source/drain regions formed on an active region extending from either the first or second active region and connected to the flip-flop circuit and a gate that crosses the first or second active region between the N+-type source/drain regions-of the respective pass transistors. The SOI region is a portion of the semiconductor substrate on which the semiconductor layer is formed, and the bulk region is a portion of the semiconductor substrate excluding the SOI region. One of the NMOS transistors includes N+-type source/drain regions in the first branch of the first active region and a gate crossing the first branch between the first N+-type source/drain regions and extending across the second branch between P+-type source/drain regions and one of the PMOS transistors includes the P+-type source/drain regions formed in the second branch of the first active region and the gate of on of the pass transistors.

In some embodiments, the second isolation layer is deeper than the first isolation layer and the buried insulator and the second isolation layer is configured to allow both of the active regions to extend to the bulk region in opposite directions. One of the N+-type source/drain regions may directly contact one of the second P+-type source/drain regions. Another one of the N+-type source/drain regions and another one of the P+-type source/drain regions may be separated by the first isolation layer, and the first active region and the second active region may be separated by the first isolation layer. One of the N+-type source/drain regions of at least one of the NMOS transistors may directly contact one of the N+-type source/drain regions of at least one of the pass transistors. A well contact node may be electrically connected to the semiconductor substrate of the bulk region below one of the pass transistors that controls a potential of a channel region of the one of the pass transistors to reduce a floating body effect in the SOI region.

In further embodiments of the present invention, an SRAM includes an integrated circuit substrate having a buried insulator in a portion of the integrated circuit substrate and a silicon-on-insulator (SOI) region including a semiconductor layer on the buried insulator and a bulk region of the integrated circuit substrate separate from the SOI region. A flip-flop circuit is provided in the SOI region. The flip-flop circuit includes a first and second CMOS inverter. A first pass transistor in the bulk region is electrically coupled to the first CMOS inverter and a second pass transistor in the bulk region is electrically coupled to the second CMOS inverter.

In other embodiments of the present invention, the SOI region includes an active region having a main part and a first and second branch part extending at different points therefrom. The first CMOS inverter may include a first and a second N+-type source/drain region in the main part and a third N+-type source/drain region in the first branch part and a gate crossing the main part between the first and second N+-type source/drain regions and crossing the first branch between the first and third N+-type source/drain regions. The first N+-type source/drain region may also be a source/drain region of the first pass transistor. The second CMOS inverter may include a fourth and a fifth N+-type source/drain region in the main part and a sixth N+-type source/drain region in the second branch part and a gate crossing the main part between the fourth and fifth N+-type source/drain regions and crossing the second branch between the fourth and sixth N+-type source/drain regions. The fourth N+-type source/drain region may also be a source/drain region of the second pass transistor. In further embodiments of the present invention, the active region includes a first and second active region with an isolation layer therebetween. The first CMOS inverter is in the first active region and the second CMOS inverter is in the second active region in such embodiments. The first and second part may extend from the main part in a same direction or in opposite directions.

DETAILED DESCRIPTION OF THE INVENTION

According to some embodiments of the present invention, a storage node in a static random access memory (SRAM) cell includes a full CMOS transistor. The CMOS transistors may be formed in a silicon-on-insulator (SOI) region and pass transistors for reading and writing data may be formed in a bulk region. In other words, for some embodiments of the present invention, a flip-flop circuit used as a storage node includes two inverters formed as CMOS transistors in the SOI region while the pass transistors, which are NMOS transistors, are formed in the bulk region. To form the SRAM cell, a partial SOI substrate may be prepared. The partial SOI substrate may include an SOI region and a region without an SOI structure, that is, a bulk region.

The SOI region may include an integrated circuit (semiconductor) substrate, a buried insulator and a semiconductor layer. For other embodiments of the present invention, the bulk region may include a conventional semiconductor substrate. The buried-insulator may cover bottom parts of the CMOS transistors formed in the SOI region. In other words, the CMOS transistors, i.e., the PMOS and NMOS transistors, may be floated on the buried insulator (or bottom insulator).

The PMOS and NMOS transistors may be formed on the same active region. The pass transistors in such embodiments may be formed on an extended portion of the active region that extends into the bulk region. Therefore, the active region may extend from the SOI region to the bulk region. An output terminal of a CMOS inverter may be common on the same active region as that of source/drain regions of the pass transistors.

Although the pass transistors may be formed only in the bulk region, the active region of the bulk region and that of the SOI region may be connected with each other. Thus, a floating body effect generally accompanying the use of the SOI structure may be reduced and/or effectively eliminated. In other words, the potential of the semiconductor substrate or a well under the pass transistors formed in the bulk region may be maintained stable by a certain well bias, thereby reducing or effectively eliminating the floating body effect. To control the well bias under the pass transistors, a well contact node may be formed. The well contact node may be electrically connected to the well under the pass transistors. In particular embodiments of the present invention, a path may be provided in the semiconductor substrate or the well to allow electric charges accumulated under the pass transistors as a result of the floating body effect to be driven out.

Some embodiments of the present invention utilize a novel layout of an SRAM cell that includes the SOI region and the bulk region, which may effectively reduce the size of the SRAM cell. In particular embodiments of the present invention, a novel layout of the active region is utilized that may further reduce the size of the SRAM cell.

Embodiments of the present invention will now be further described with reference toFIGS. 1-4.FIG. 1is a circuit diagram illustrating an SRAM according to some embodiments of the present invention.FIG. 2is a plan view of a layout of the SRAM ofFIG. 1according to some embodiments of the present invention.FIG. 3is a cross-sectional view taken along the line A-A′ ofFIG. 2illustrating an SRAM according to some embodiments of the present invention.FIG. 4is a cross-sectional view taken along the line B-B′ ofFIG. 2illustrating an SRAM according to some embodiments of the present invention.

Referring first toFIG.1, the illustrated embodiments of an SRAM include a storage node (within a schematically illustrated region110), which is a flip-flop circuit including two CMOS inverters. The SRAM also includes pass transistors PS1and PS2for reading and writing data. The two CMOS inverters include two pull down transistors PD1and PD2and two pull up transistors PU1and PU2. The CMOS inverters are formed in the SOI region110. The pass transistors PS1and PS2are connected to a word line and to a bit line formed on a bulk region of a semiconductor substrate (i.e., outside the SOI region110).

Embodiments of an SRAM as illustrated inFIG. 1will now be further described with reference to the layout shown inFIG. 2and the cross-sectional views illustrated inFIGS. 3 and 4. For the embodiments ofFIGS. 2,3, and4, a partial SOI substrate including the SOI region110and a bulk region150is prepared in which an SRAM cell will be formed. The SOI region110includes a buried insulator230in a predetermined portion of a semiconductor substrate100and a semiconductor layer120formed on the buried insulator230. The bulk region150is shown as formed of a remaining portion of the semiconductor substrate100other than the partially configured SOI region110.

Here, the semiconductor layer120may be a monocrystalline silicon layer and may be disposed on the buried insulator230. Thus, the semiconductor layer120may float on the buried insulator230, which serves as a buried floating layer. The semiconductor layer120may be formed, for example, to a thickness no greater than about 2000 angstroms (Å). The buried insulator230may be formed in various ways to manufacture the SOI substrate, and, in some embodiments, is approximately 500 Å to 4000 Å thick. The buried insulator230may include a thermal oxide layer or an oxide or nitride layer formed by chemical vapor deposition (CVD).

Referring now toFIG. 2, to form an SRAM cell having six transistors, an active region130is defined in the substrate100. The illustrated active region130includes a main part131, which crosses the SOI region110, a first branch135which protrudes from the main part131, and a second branch137which protrudes, in an opposite direction to that of the first branch135, from a different region of the main part131from where the first branch135protrudes. The active region130may also extend beyond the SOI region110to the bulk region150. In other words, the active region130may not only include the SOI region110but may also extend to the bulk region150.

The active region130in the SOI region110is defined by a first isolation layer250formed on the buried insulator230and the semiconductor Substrate100. A second isolation layer210may be formed at the boundary between the SOI region110and the bulk region150and defines the SOI region110. The second isolation layer210may surround the SOI region110and allow the active region130to extend to the bulk region150.

The first isolation layer250may be formed by a local oxidation of silicon (LOCOS) separation process and/or a shallow trench isolation (STI) process. The first isolation layer250may be a chemical vapor deposition (CVD) oxide or nitride layer. The second isolation layer210may also be formed by one of the LOCOS and/or STI processes. The second isolation layer210may be formed by the STI process in a trench with a maximum depth of approximately 3000 Å.

The first isolation layer250and the second isolation layer210may be formed in the same process because the buried insulator230is disposed beneath the first isolation layer250. The second isolation layer210may be a CVD oxide layer and/or a CVD nitride layer. The first isolation layer250may also be a CVD oxide layer and/or a CVD nitride layer. The second isolation layer210may be deeper than the buried insulator230so that the second isolation layer210facilitates forming of an isolation layer in a peripheral circuit region that operates the SRAM cell.

An isolation layer in the peripheral circuit region may be formed deeply because a deep isolation layer is generally beneficial to a PMOS transistor formed in the peripheral region of the semiconductor substrate100. When forming the SRAM, an isolation layer in the peripheral circuit region and the second isolation layer210may be formed simultaneously.

The second isolation layer210may also enhance operating characteristics of the pass transistors PS1and PS2because the second isolation layer210isolates the pass transistors PS1and PS2from the pull up and pull down transistors PU1and PD1and/or PU2and PD2of the CMOS inverter. In some embodiments of the present invention using a CMOS process, CMOS transistors330and350, collectively310, are formed in the SOI region110and a pass transistor370, which is an NMOS transistor, is formed in the bulk region150on the active region130defined by the first isolation layer250.

Referring now to the embodiments ofFIG. 3, the semiconductor substrate100may be formed of a P-type semiconductor and N-type impurities ion-implanted into the main part131of the active region130of the semiconductor layer120, thereby forming first N+-type source/drain regions141. Additional N+-type source/drain regions145of the pass transistors370may also be formed by the ion-implantation of N-type impurities into the semiconductor substrate100. As a P type substrate may be used as the semiconductor substrate100, there may be no need to form a P well. However, a P well may be additionally formed under the pass transistors370if desired.

P+-type source/drain regions143may be formed by the ion-implantation of P-type impurities into the first branch135of the active region130adjacent to the first source/drain regions141. Here, an additional well forming process may not be required as all of the first source/drain regions141and the second source/drain regions143are formed in the semiconductor layer120on the buried insulator230in the SOI region110. In particular, an additional N well for the PMOS transistor330may be unnecessary.

It may be desired to ion-implant P type impurities into a portion of the semiconductor layer120occupied by the PMOS transistor330to secure a stable channel between the second N+-type source/drain regions143. However, it is not necessary to form a well like a conventional N well that extends over a large portion of the semiconductor substrate100.

It may be possible to secure a channel for the PMOS transistor330by ion-implanting of N+-type impurities for the first source/drain regions141to the PMOS transistor region330at the same time. Additionally, increased security of the channel may be provided using an ion-implanting process for adjusting a threshold voltage VT. Therefore, it may not be necessary to form a well, such as an N well, that extends over a large portion of the semiconductor substrate100and is formed when configuring CMOS transistors, as in a conventional bulk semiconductor substrate.

As a result, the size of the SRAM cell may be significantly smaller than a conventional SRAM in some embodiments of the present invention because the area taken up by an N well may be smaller. For example, a reduction of approximately fifteen percent may be achieved in particular embodiments of the present invention.

The source/drain regions may be formed in the second branch137and a portion of the main part131adjacent to the second branch137as well as in the first branch135and a portion of the main part131adjacent to the first branch135of the active region130such that the active region and the source/drain regions have a mirrored structure.

As shown in the embodiments ofFIG. 3, gates410and450, including a gate dielectric layer240and a spacer260, are formed on the source/drain regions141,143, and145. The CMOS transistors310and the pass transistor370include the gates410and450, the gate dielectric layer240, the spacer260and the source/drain regions141,143, and145. To be more specific, referring to the embodiments ofFIGS. 2 and 3, the first gate410crosses the active region130of the main part131between the first source/drain regions141and extends to cross the active region130of the first branch135between the second source/drain regions143. That is, the first gate410in the illustrated embodiments is not straight. Similarly, another gate, being a mirror image of the first gate410, is formed on the second branch137. Meanwhile, the second gate450is formed on the active region130between the third source/drain regions145.

The NMOS transistor350includes the first source/drain regions141and the first gate410, and the PMOS transistor330includes the second source/drain regions143and the first gate410. The CMOS transistor310includes the NMOS transistor350and the PMOS transistor330. A first CMOS inverter includes the CMOS transistor. A second CMOS inverter includes an NMOS transistor and a PMOS transistor formed on the main part131and the second branch137of the active region130. Referring toFIG. 2, a flip-flop circuit includes the first CMOS inverter and the second CMOS inverter.

In the bulk region150of the illustrated embodiments ofFIGS. 2 and 3, the pass transistor370includes the third source/drain regions145and the second gate450and is connected to each of the first and second CMOS inverters. Referring to the embodiments ofFIGS. 2 and 3, any one of the first source/drain regions141of the NMOS transistor350may directly contact any one of the second source/drain regions143of the PMOS transistor330. Further, any one of the first and the second source/drain regions141and143may directly contact any one of the third source/drain regions145.

One of an output terminal530and a storage node of the CMOS inverter310may be formed between the first source/drain regions141and the second source/drain regions143such that the one of the output terminal530and the storage node of the CMOS inverter310is electrically connected to both the first source/drain regions141and the second source/drain regions143. As the active region130extends into the bulk region150, a source/drain terminal510of the pass transistor370, that is, a bit line terminal, may be formed on the active region131and may be in electrical contact with the output terminal530. This configuration is in accordance with the circuit diagram ofFIG. 1.

Referring again to the embodiments ofFIG. 2, the NMOS transistor350and the PMOS transistor330are separated by the second isolation layer250. In other words, the second isolation layer250separates the first source/drain regions141from the second source/drain regions143. Referring to the circuit diagram of theFIG. 1and the cross-section ofFIG. 2, the SRAM includes a Vcc terminal540and a Vss terminal550, and a word line terminal including a first gate terminal560and a second gate terminal520. The Vss terminal550can be connected to the circuit with a single contact. When the positions of the transistors are changed, for example, when the PMOS transistor330and the NMOS transistor350are switched, the Vss terminal550becomes the Vcc terminal540and is connected to the circuit with a single contact. Hence, it may be easier to form the interconnected wiring required to form the circuit ofFIG. 1.

A variety of advantages may be obtained when the CMOS inverters including the PMOS and NMOS transistors330and350are formed on the SOI region110for some embodiments of the present invention. First, it may be unnecessary to have a well region that separates the NMOS transistor350from the PMOS transistor330because the two inverters for storing data are configured in a flip-flop circuit in the SOI region110. Thus, compared to an SRAM with inverters formed in the bulk region150, a fifteen percent reduction in the size of the SRAM cell may be achieved. In addition, excellent SER and a reduction or even prevention of latch-up may be provided in some embodiments as the CMOS transistor310, including the NMOS transistor350and the PMOS transistor330, is formed in the SOI region110. In particular, as the NMOS transistor350, which has relatively high carrier mobility, is formed in the SOI region110, the operating speed of the SRAM may be significantly increased.

Moreover, since the pass transistor370is formed in the bulk region150, a stable well potential may be achieved by applying a well bias in some embodiments of the present invention. Thus, a floating body effect, which may be a problem in conventional SOI devices, may be reduce or even effectively be prevented. In other words, a well contact node may be formed by using a well or the semiconductor substrate100under a channel of the pass transistor370as a path. Then, the potential of the channel region may be controlled externally by applying a voltage to the well contact node.

Referring now to the embodiments ofFIG. 4, the NMOS transistor350in the SOI region110and the pass transistor370in the bulk region150are both formed in the active region130. The P type semiconductor substrate100, or a well, exists below the pass transistor370. The potential of the well or a channel may be stable when the well contact node570is electrically connected to the well or the semiconductor substrate100. In other words, the potential of the well or the channel may be stabilized by applying a well bias. Specifically, electric charges accumulated and floating on the buried insulator230as a result of the floating body effect may be driven out of the SRAM via the well contact node. Therefore, despite the general characteristics of an SOI device, it may be possible to reduce or effectively eliminate the floating body effect.

In addition, since the partial SOI substrate including the bulk region150is used, an additional circuit, for example, an anti-static circuit, may be formed in the bulk region150in order to improve the reliability of the SRAM cell. It is generally difficult to form such an anti-static circuit in the SOI region110whereas an anti-static circuit can generally easily be formed in the bulk region150. Therefore, the reliability of the SRAM may be improved when the partial SOI substrate having the bulk region150is used.

Referring toFIG. 2, the SRAM may include the active region130but may also include a divided active region, which may allow further reduction of the size of the SRAM cell.

Further embodiments of the present invention will now be described with reference toFIG. 5.FIG. 5is a plan view of the layout of an SRAM cell according to some other embodiments of the present invention. As shown in the embodiments ofFIG. 5, an SRAM includes two active regions630and640that mirror one another. The division of the active region may enable a further reduction in the size of the SRAM cell from that of an SRAM cell having the layout ofFIG. 2. A detailed description of elements of the embodiments of the present invention inFIG. 5that are identical to elements of the embodiments described with reference toFIG. 2will not be further provided as they have been fully described above. As described with reference to the embodiments ofFIG. 2throughFIG. 4, an SRAM according to the embodiments ofFIG. 5may include a SOI substrate having an SOI region110and a bulk region150. The SRAM further includes a first isolation layer250, a second isolation layer210, and a buried insulator230.

The SRAM shown in the embodiments ofFIG. 5includes a first active region630and a second active region640. The first active region630includes a first main part631, which crosses the SOI region110on a semiconductor layer120, a first branch633, which protrudes from the first main part631, and a second branch635, which protrudes from the first main part631in the same direction as the first branch633from a different region of the first main part631from where the first branch633protrudes. The second active region640is a mirror image of the first active region630. The first branch633and the second branch635protrude in the same direction and are separated by the second isolation layer250.

The second active region640includes a second main part641separated from the first main part631by the second isolation layer250that parallels the first main part631, a third branch643, which protrudes from the second main part641in a direction opposite to the direction in which the first branch633protrudes from the first main part631, and a fourth branch645, which protrudes from the second main part641in the same direction as the third branch643but from a different position on the second main part641from where the third branch643protrudes.

As described with reference toFIG. 3, first N+-type source/drain regions are formed in the first branch633of the first active region630and the second P+-type source/drain regions are formed in the second branch635of the first active region630. Moreover, a first gate410, which crosses the first branch633between the first source/drain regions, extends across the second branch635between the second source/drain regions.

An NMOS transistor350includes the first source/drain regions and the first gate410, and a PMOS transistor330includes the second source/drain regions and the first gate410. As described with reference toFIG. 4, a first CMOS inverter310includes the NMOS transistor350and the PMOS transistor330. Similarly, in the second active region640, there is a second CMOS inverter laid out as a mirror image of the first CMOS inverter310. The second CMOS inverter includes an NMOS transistor and a PMOS transistor and forms a flip-flop circuit together with the first CMOS inverter310.

As described with reference toFIG. 3, the first isolation layer250is formed at the boundary between the SOI region110and the bulk region150. The first isolation layer250allows each of the first and the second active regions630and640to extend to the bulk region150.

Third N+-type source/drain regions are formed in the active regions630and640and are connected to the flip-flop circuit. Further, a second gate450crosses the active regions630and640between the third source/drain regions. The third N+-type source/drain regions and the second gate450constitute two pass transistors370. As the active regions630and640extend to the bulk region150in opposite directions, the pass transistors370are also formed in opposite directions.

Various of the above described embodiments of the present invention may provide an SRAM cell having improved characteristics. In particular, the SRAM cell according to the embodiments illustrated inFIG. 5may be even smaller than an SRAM cell according the embodiments of the present invention illustrated inFIG. 2.

As described above, embodiments of the present invention provide an SRAM including six transistors that may have improved characteristics. These characteristics may include integration density, performance (for example, static noise margin (SNM)) and/or reliability (for example, SER).