Semiconductor chip package and printed circuit board

A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2007-0094916 filed with the Korean Intellectual Property Office on Sep. 18, 2007, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor chip package and a printed circuit board having an embedded semiconductor chip package.

2. Description of the Related Art

In current electronic products, especially portable electronic devices, etc., the variety of consumer demands is continuously increasing. In particular, the demands for multi-functionality, compact sizes, light weight, high speeds, low costs, increased portability, real time access to the wireless Internet, and sophisticated designs are goading developers, designers, and manufacturers alike to provide superior products. Increased competition in providing such products have led to more frequent releases of newer models, exacerbating the burden on those involved. The demands related to mobile products, such as cell phones, PDA's, digital cameras, and laptops, in particular, are greater than ever, one result of which is that the electronic parts for these products are being modularized and integrated, to implement multi-functionality, compact sizes, light weight, and low costs, etc.

In the case of embedding a passive component in a semiconductor chip, there is a limit to the types of material that can be used when considering compatibility with semiconductor processes. Embedding the passive component may also increase chip size or increase cost, and thus impose a limit on applicability. Another method is to embed the passive component in a semiconductor chip package. Methods of forming a capacitor directly inside the package include methods that provide thick film types and methods that provide thin film types.

In the case of a thick film capacitor, a composite material may be used that includes a dielectric filler dispersed in the epoxy resin used for the insulation. Although this may provide superb workability, the dielectric constant may be low, to be about 30, making it difficult to implement a high-capacitance capacitor. On the other hand, a thin film capacitor may provide a high capacitance density, but there is a higher likelihood of electrical leakage caused by defects in the surface of the surface of the copper foil used for the lower electrode.

In order to form a passive component in a semiconductor chip package with greater reliability, a technique has also been conceived of forming a capacitor on the rewiring layer of a semiconductor package. In this case, however, the capacitor may be formed in-between the rewiring lines, so that there is a limit to the size of the capacitor. The material used for the capacitor may also be limited to those that are compatible with the rewiring process, and the degree of freedom may be very low in planning for the processes, with regards, for example, process temperatures and patterning methods, etc.

SUMMARY

An aspect of the invention is to provide semiconductor chip package and a printed circuit board having an embedded semiconductor chip package, in which a capacitor is arranged in an area separated from the rewiring layer of the semiconductor, so that the semiconductor chip may be utilized effectively.

One aspect of the invention provides a semiconductor chip package that includes a semiconductor chip, on one side of which at least one chip pad is formed, and a capacitor formed on the other side of the semiconductor chip.

The capacitor can include an upper electrode formed on the other side of the semiconductor chip, a dielectric layer formed on the upper electrode, and a lower electrode formed on the dielectric layer.

The lower electrode may be electrically connected with a lower pad formed on the other side of the semiconductor chip, while the upper electrode may be electrically connected with an upper pad formed on the other side of the semiconductor chip.

On the one side of the semiconductor chip, a rewiring layer may be stacked that includes a rewiring line electrically connected with the chip pad.

Another aspect of the invention provides a printed circuit board, in which a semiconductor chip is embedded, and in which at least one circuit pattern layer and at least one insulation layer are alternately stacked. In this printed circuit board, a chip pad formed on one side of the semiconductor chip may be electrically connected with a first circuit pattern of the circuit pattern layer, and a capacitor formed on the other side of the semiconductor chip may be electrically connected with a second circuit pattern of the circuit pattern layer.

The capacitor can include an upper electrode formed on the other side of the semiconductor chip, a dielectric layer formed on the upper electrode, and a lower electrode formed on the dielectric layer.

The lower electrode can be electrically connected with a lower pad formed on the other side of the semiconductor chip, and the upper electrode can be electrically connected with an upper pad formed on the other side of the semiconductor chip.

The chip pad and the first circuit pattern may be connected by way of an interposed rewiring layer that includes a rewiring line.

DETAILED DESCRIPTION

The semiconductor chip package and a printed circuit board having an embedded semiconductor chip package according to certain embodiments of the invention will be described below in more detail with reference to the accompanying drawings. Those elements that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number, and redundant explanations are omitted.

FIG. 1ais a bottom view of a semiconductor chip package according to an embodiment of the invention, andFIG. 1bis a cross sectional view of a semiconductor chip package according to an embodiment of the invention. InFIGS. 1aand1b, there are illustrated a semiconductor chip package10, a semiconductor chip11, a semiconductor substrate111, chip pads112, a protective film113, a capacitor12, a lower electrode121, a dielectric layer122, an upper electrode123, a lower pad131, and an upper pad132.

FIG. 1bis a cross sectional view across portion A inFIG. 1a, and as illustrated inFIG. 1b, a semiconductor chip package10can include a semiconductor chip11and a capacitor12formed on the semiconductor chip11.

The semiconductor chip11can be composed mainly of a semiconductor substrate111, in which an integrated circuit may be embedded; chip pads112, which may be positioned on one side of the semiconductor substrate111and electrically connected with the integrated circuit; and a protective film113, which may be stacked on the semiconductor substrate111such that the chip pads112are exposed.

The capacitor12can be formed on the other side of the semiconductor chip11. The capacitor12can be formed by deposition as a thin film. A lower electrode121of the capacitor12can be formed on the other side of the semiconductor chip11, while a dielectric layer122can be formed on the lower electrode121. Also, an upper electrode123can be formed on the dielectric layer122. The lower electrode121and the upper electrode123can be electrically connected respectively to the lower pad131and the upper pad132formed on the other side of the semiconductor chip11.

The materials that can be used for the lower electrode121, upper electrode123, and dielectric layer122of the capacitor12are commonly known to those skilled in the art, and thus will not be described here in detail.

In this embodiment, the capacitor12can be formed on the other side of the semiconductor chip11, where the chip pads112are not formed, so that the space on the semiconductor chip11may be utilized efficiently and the capacitor12may be formed in various sizes.

FIG. 2is a cross sectional view of a semiconductor chip package according to another embodiment of the invention. InFIG. 2, there are illustrated a semiconductor chip package20, a semiconductor chip21, a semiconductor substrate211, a chip pad212, a protective film213, a capacitor22, a lower electrode221, a dielectric layer222, an upper electrode223, a lower pad231, an upper pad232, a rewiring layer24, a rewiring line241, and insulation layers242.

The example shown inFIG. 2differs from that ofFIG. 1bin that a rewiring layer24may be formed over one side of the semiconductor chip21. The following descriptions will focus mainly on such differences, and the descriptions for other elements will not be repeated.

A chip pad212formed on one side of the semiconductor chip21can have an extremely small diameter, of about 10 to 20 μm. Since a chip pad212of this size may cause difficulties in control during the process for manufacturing the printed circuit board, there may be problems in directly connecting the chip pad212to the printed circuit board. Thus, the rewiring layer24can be formed, using a rewiring process to increase the size of the pad for connecting to the exterior.

The rewiring layer24can be composed mainly of insulation layers242and a rewiring line241placed between the insulation layers242. The rewiring line241can be electrically connected to the chip pad212of the semiconductor chip21, with a portion of the rewiring line241exposed to the exterior. The portion of the rewiring line241exposed to the exterior may have a larger surface area than that of the chip pad212, making it easier to connect to an external component.

FIG. 3is a cross sectional view of a semiconductor chip package according to yet another embodiment of the invention. InFIG. 3, there are illustrated a semiconductor chip package30, a semiconductor chip31, a capacitor32, chip pads33, circuit pattern layers35, insulation layers36, a first circuit pattern351, a second circuit pattern352, and a printed circuit board300.

The structure of a printed circuit board300according to this embodiment can include insulation layers36and circuit pattern layers35stacked in alternation and can include an embedded semiconductor chip package30. A core layer37may also be included in the middle of the printed circuit board300.

The chip pads33can be formed on one side of the semiconductor chip package30, where the chip pads33can be electrically connected with a first circuit pattern351. The chip pads33may also be connected to the first circuit pattern351by vias.

Also, the capacitor32can be formed on the other side of the semiconductor chip31. The capacitor32can be electrically connected with a second circuit pattern352.

The connections between the chip pads33and the first circuit pattern351and between the capacitor32and the second circuit pattern352in this embodiment can be implemented, after embedding the semiconductor chip package30in the printed circuit board300, by forming vias.

When embedding a semiconductor chip package30in the printed circuit board300that includes a capacitor32formed beforehand on the other side of the semiconductor chip31as in the present embodiment, the capacitance of the capacitor32can be precisely controlled, because the capacitor32can be formed beforehand. Thus, with the capacitor-embedded printed circuit board300structured as above, the capacitor can be manufactured, during the manufacturing process for the printed circuit board, with a higher level of reliability in terms of capacitance compared to the conventional printed circuit board formed with a thin film capacitor.

In particular, since there may be no chip pads33formed on the other side of the semiconductor chip31, a larger area may be obtained, and since the other side of the semiconductor chip31may be very flat, the capacitor32may readily be formed by thin film deposition.

As set forth above, by forming a capacitor as a thin film in a semiconductor chip on a surface other than the surface on which the chip pads are formed, the semiconductor chip may be utilized more efficiently. Also, by using a separate process to form the capacitor as a thin film in the semiconductor chip, a more reliable capacitor may be formed compared to having the capacitor formed during the manufacturing process of the printed circuit board.

Furthermore, when this semiconductor chip package, which includes a capacitor formed on the semiconductor chip, is embedded in the printed circuit board, substantially the same effects can be obtained as the case in which the capacitor is embedded in the printed circuit board.

While the spirit of the invention has been described in detail with reference to particular embodiments, the embodiments are for illustrative purposes only and do not limit the invention. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the invention.