Gate drivers and auto-zero comparators

Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

FIELD OF THE DISCLOSURE

This disclosure relates generally to circuits and, more particularly, to gate drivers and auto-zero comparators.

BACKGROUND

High-voltage and/or high-current applications require power electronic devices capable of efficient and effective operation at various operating conditions. In such applications, power modules deliver power using power devices such as, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), etc. A driver may be used to control a power device used as a power delivering device to support delivering power to a load.

In an Enhancement mode (E-mode) gallium nitride (GaN) process, there are limited options for Depletion mode (D-mode) devices, for example P-type devices, that can be deployed for limiting an achievable single stage gain. In some instances, the lack of P-type devices may limit an input common mode range of a comparator. In such instances, absolute parameters of GaN transistors (e.g., VGS,TH, gm, etc.) may show relatively large variation. Such variation can lead to relatively large mismatch between GaN transistors, which can result in relatively large offset voltages of comparator circuits.

DETAILED DESCRIPTION

The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used herein, connection references (e.g., attached, coupled, connected, and joined) are to be construed in light of the specification and, when pertinent, the surrounding claim language. Construction of connection references in the present application shall be consistent with the claim language and the context of the specification, which describes the purpose for which various elements are connected or coupled. As such, connection references do not necessarily infer that two elements are directly connected or directly coupled and in fixed relation to each other.

Consistent with the present disclosure, the term “configured to” purports to describe the structural and functional characteristics of one or more tangible non-transitory components. For example, a device that is “configured to” perform a function can be understood to mean that the device has a particular configuration that is designed or dedicated for performing a certain function. Within this understanding, a device is “configured to” perform a certain function if such a device includes tangible non-transitory components that can be enabled, activated, or powered to perform that certain function. While the term “configured to” may encompass the notion of being configurable, this term should not be limited to such a narrow definition. Thus, when used for describing a device, the term “configured to” does not require the described device to be configurable at any given point of time.

Similarly, while operations are depicted in the drawings in an example particular order, this should not be understood as requiring that such operations be performed in the example particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results unless such order is recited in one or more claims. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments.

For improved switching performance, a gate driver of a power converter circuit is preferred to be placed as close as possible to a power switch (e.g., a power switch transistor) to minimize and/or otherwise reduce the parasitic gate-loop inductance. Enhancement mode (E-mode) gallium nitride (GaN) transistors (e.g., enhancement mode GaN transistors) can be such switches or power switches. In some instances, a GaN switch can be manufactured using a lateral power process, which offers monolithic integration of driver and power transistor on one die. Such monolithic integration may also provide a close placement between the gate driver and the GaN switch.

However, the monolithic integration process may lack P-type devices for use in an E-mode GaN implementation. The lack of P-type devices generates difficulty when implementing a rail-to-rail (e.g., from a ground rail (GND) or ground terminal to a supply voltage rail (VDD) or supply voltage terminal) gate driver with transistor pull-up for efficient switching and safe turn-off of the GaN switch. In some instances, additional difficulty arises when implementing the rail-to-rail gate driver without an auxiliary voltage rail or terminal that is greater than VDD.

In some instances, a comparator is associated with a gate driver, such as a rail-to-rail gate driver. For example, a comparator can be used as a peak current comparator in a control loop of a direct current (DC) to DC converter, as a zero comparator in an active diode, as a voltage comparator in an undervoltage lockout (UVLO) circuit, an over-voltage protection (OVP) circuit, etc. However, in E-mode GaN implementations or processes, efficient D-mode devices or P-type devices are not as prevalent. Thereby, the achievable single stage gain is limited. In some instances, the lack of efficient P-type devices may limit the input common mode range that can be supported by the comparator. In some instances, absolute parameters of GaN transistors (e.g., threshold voltage VGS,TH, trans conductance gm, etc.) may show relatively large variation. Such variation can lead to relatively large mismatch between GaN transistors, which can result in relatively large offset voltages of comparator circuits.

Examples described herein include gate driver circuits, comparators (e.g., auto-zero comparators), and related methods. In some described gate driver circuits, an enable signal is generated with a self-timed bootstrap circuit that can generate a voltage greater than VDDto pull the gate of an E-mode GaN transistor up to VDD. In some described gate driver circuits, the pull-up path and pull-down path associated with the E-mode GaN transistor can be controlled (e.g., turned on, turned off, etc.) to minimize and/or otherwise reduce DC cross current to provide driving levels of 0 Volts (V) and VDDto effectuate safe and reliable control of the E-mode GaN transistor. Advantageously, example gate driver circuits described herein can control a power transistor, such as an E-mode GaN transistor, without an additional voltage rail or terminal.

Examples described herein include a general auto-zero loop, which can be implemented around a differential input stage of a comparator to reduce the input referred offset of the comparator. In some described examples, the comparator and/or associated auto-zero loop can be implemented with GaN process using discrete components, such as capacitors, resistors, and E-mode N-type devices. Advantageously, in some described examples, the comparator and/or associated auto-zero loop can support rail-to-rail input common mode and can reduce offset caused by immature matching of E-mode N-type GaN devices (e.g., N-type enhancement mode GaN transistors).

FIG. 1is a schematic illustration of an example power delivery system100including an example input stage102, an example output stage104, and an example GaN die106. The output stage104may also be known as a load stage. The power delivery system100is an offline buck converter in a low-side configuration. The input stage102and the output stage104can be a first voltage domain (e.g., 300 V domain, 400 V domain, etc.) and the GaN die106can be a second voltage domain (e.g., a 5 V domain, a 6 V domain, etc.). In the example ofFIG. 1, the input stage102is coupled to the output stage104, and the output stage104is coupled to the GaN die106. The GaN die106of the example ofFIG. 1includes an example gate driver108and an example comparator110.

In the illustrated example ofFIG. 1, the input stage102and the output stage104are in and/or otherwise form a first integrated circuit and the GaN die106is a second integrated circuit. Alternatively, one or more of the input stage102, the output stage104, and/or the GaN die106can be included in the same integrated circuit. In the example ofFIG. 1, the input stage102and the output stage104are a first die and the GaN die106is a second die. Alternatively, one or more of the input stage102, the output stage104, and/or the GaN die106may be in the same die.

In the illustrated example ofFIG. 1, the input stage102includes an alternating current (AC) voltage source112having an AC voltage VLINEcoupled to a diode bridge114in a configuration to convert VLINEto a DC voltage VDC. The diode bridge114is a passive diode full-bridge rectifier. VLINEcan have an example AC voltage of 110 Vrms, 230 Vrms, etc. Alternatively, the AC voltage source112may be a DC voltage source having a voltage in an example range of 85 V to 400 V. InFIG. 1, the diode bridge114is coupled to an electromagnetic interference (EMI) pi-filter including a first capacitor (CEMI)116, a first inductor (LEMI)118, and a second capacitor (CBULK)120. For example, CEMI116, LEMI118, and CBULK120can be coupled to the diode bridge114in a configuration to reduce EMI in the power delivery system100.

In the illustrated example ofFIG. 1, the output stage104includes a diode (DFW)122coupled to a third capacitor (COUT)124, a second inductor (LOUT)126, and a load128. COUT124is an output buffer capacitor, LOUT126is a shielded conductor, and DFW122is a freewheeling diode. DFW122, COUT124, and LOUT126form a freewheeling loop to generate an output voltage (VOUT) across the load128. COUT124is a capacitor that can filter an inductor current (IL) (e.g., the triangular waveform shaped inductor current) to generate a constant DC current (e.g., a DC current with a relatively low ripple) that can be delivered to the load128. The load128is a light-emitting diode (LED), such as a bulb replacement LED lamp. Alternatively, the load128may be any other type of electrical or power consuming device, such as, for example, an Internet-of-Things (IoT) device, a wall power adapter (e.g., an AC-DC wall charger adapter) for a computing device (e.g., a laptop, a smartphone, a tablet, a television, etc.). In some examples, the load128can be a component included in and/or otherwise associated with an electric vehicle (EV) or a hybrid-electric vehicle (HEV). For example, the load128can be an electronic control unit (ECU), one or more batteries (e.g., Lithium-ion batteries), a motor (e.g., an electric motor), a traction inverter, etc., and/or a combination thereof.

In the illustrated example ofFIG. 1, the GaN die106includes a high-voltage supply regulator130, an electro-static discharge (ESD) active clamp132, a fourth capacitor (CHV)134, an inverter136, a first latch138, a max off timer140, a logic gate142, a second latch144, a blanking circuit146, and a switch (QS)148. Further depicted in the example ofFIG. 1is a fifth capacitor (CAUX)150coupled to the ESD active clamp132, the high-voltage supply regulator130, and an example reference voltage terminal (e.g., a ground terminal)152. VDDis present at a fourth example node162. CAUX150is used to buffer the supply voltage for the GaN die106. Further depicted in the example ofFIG. 1is a resistor (RSHUNT) (e.g., a shunt resistor)154coupled to the gate driver108, the blanking circuit146, QS148, and the reference terminal152. RSHUNT154is coupled to the GaN die106in a configuration to perform ground-referred current sensing.

In the illustrated example ofFIG. 1, the ESD active clamp132is coupled to the high-voltage supply regulator130in a configuration to provide ESD protection to the high-voltage supply regulator130, and/or, more generally, the GaN die106. In the example ofFIG. 1, the high-voltage supply regulator130has an input terminal coupled to a supple voltage terminal (VDD), a first output terminal (PWR_GD), and a second output terminal (UVLO). InFIG. 1, PWR_GD is a power good output coupled to a set input of the first latch138. For example, the high-voltage supply regulator130can assert PWR_GD in response to VDDbeing greater than a power good threshold and can de-assert PWR_GD in response to VDDbeing less than the power good threshold. In such examples, the high-voltage supply regulator130can set the first latch138in response to VDDbeing greater than the power good threshold causing the first latch138to deliver a logic low signal (e.g., a voltage representative of a circuit logic ‘0’) from an output terminal of the first latch138to an inverted enable input of the second latch144. The inverted enable input of the second latch144can invert the logic low signal to a logic high signal (e.g., a voltage representative of a circuit logic ‘1’) to enable the second latch144.

In the illustrated example ofFIG. 1, UVLO is an undervoltage lockout output terminal coupled to a reset input terminal of the first latch138. For example, the high-voltage supply regulator130can assert UVLO in response to VDDbeing less than a UVLO detection voltage threshold and can de-assert UVLO in response to VDDbeing greater than the UVLO detection voltage threshold. In such examples, the high-voltage supply regulator130can reset the first latch138in response to VDDbeing less than the UVLO detection voltage threshold causing the first latch138to deliver a logic high signal from the output terminal of the first latch138to the inverted enable input terminal of the second latch144. The inverted enable input terminal of the second latch144can invert the logic high signal to a logic low signal to disable the second latch144.

In the illustrated example ofFIG. 1, the input terminal of the high-voltage supply regulator130is coupled to CHV134and a first current terminal (e.g., a drain, a drain terminal, a power transistor current terminal, etc.) of QS148. A switch voltage (VSW) is present at a first example node156. In the example ofFIG. 1, the high-voltage supply regulator130, CHV134, and the first current terminal of QS148are coupled to DFW122, LOUT126, and/or, more generally, the output stage104.

In the illustrated example ofFIG. 1, CHV134is coupled to an input terminal of the inverter136(e.g., an inverter input, an inverter input terminal, etc.). InFIG. 1, the inverter136is a Schmitt inverter (e.g., a Schmitt trigger). Alternatively, any other inverter136may be used. InFIG. 1, an output terminal of the inverter136(e.g., an inverter output, an inverter output terminal, etc.) is coupled to a first input of the logic gate142. InFIG. 1, the logic gate142is an OR logic gate. Alternatively, any other logic gate and/or combination of logic gates may be used. InFIG. 1, the max off timer140ofFIG. 1is a timer. InFIG. 1, an output terminal of the max off timer140is coupled to a second input terminal of the logic gate142. InFIG. 1, an input terminal of the max off timer140is coupled to an output terminal of the gate driver108and a gate (e.g., a gate terminal, a power transistor gate terminal, etc.) of QS148. A gate voltage (VGATE) is present at a third example node160.

In the illustrated example ofFIG. 1, an output terminal of the logic gate142is coupled to a set input of the second latch144and an output terminal of the comparator110is coupled to a reset input of the second latch144. In the example ofFIG. 1, an output terminal of the second latch144is coupled to a first input of the gate driver108. A second input (e.g., a feedback input) of the gate driver108is coupled to a second current terminal (e.g., a source, a source terminal, etc.) of QS148, an input (e.g., an input terminal) of the blanking circuit146, and RSHUNT154. A shunt voltage (VSHUNT) is present at a second example node158. InFIG. 1, a first input (designated with a ‘+’ symbol) of the comparator110(e.g., a first comparator input) is coupled to an output terminal of the blanking circuit146. The voltage at the first input of the comparator110is represented by VSIG. InFIG. 1, a second input (designated with a ‘−’ symbol) of the comparator110(e.g., a second comparator input) is coupled to a reference voltage (VREF).

In example operating conditions, the GaN die106magnetizes and/or otherwise energizes LOUT126in response to turning on and/or otherwise enabling QS148. In response to turning on QS148, ILassociated with LOUT126increases and causes energy to be stored in LOUT126. In example operating conditions, the inductor current is measured by the GaN die106based on VSHUNTat the second node158. In example operating conditions, the comparator110can assert a logic high signal in response to determining that VSHUNTis greater than VREF. For example, after a blanking time has elapsed as determined by the blanking circuit146, the comparator110can receive VSHUNTto execute a comparison of VSHUNTto VREF. In response to the comparator110determining that the inductor current has reached and/or otherwise satisfied a current threshold (e.g., a desired peak current), the comparator110can assert a logic high signal to reset the second latch144. In response to the second latch144being reset, the second latch144delivers a logic low signal to the gate driver108and, thus, causing the gate driver108to turn off QS148.

In example operating conditions, in response to turning off QS148, the inductor current takes a path (e.g., the freewheeling path) across DFW122, which causes an output current (IOUT) to increase and the inductor current to decrease. The output current can cause a voltage to be stored by COUT124, which can cause power to be delivered to the load128. In example operating conditions, the GaN die106can determine when the inductor current reaches approximately zero. For example, VSWat the first node156can be stored by CHV134and, when the inductor current reaches and/or otherwise substantially approaches zero, the inverter136can invert a logic low signal to a logic high signal to invoke the logic gate142to assert a logic high signal to the set input of the second latch144. In response to the second latch144receiving the logic high signal at the set input, the second latch144can instruct and/or otherwise invoke the gate driver108to turn on QS148. In response to turning on QS148, the inductor current begins to increase.

Advantageously, the comparator110improves the power delivery system100of the example ofFIG. 1by having a reduced input referred offset and an extended DC input common mode range to full rail-to-rail (e.g., from the reference terminal152to VDD) as described herein. Advantageously, the gate driver108improves the power delivery system100of the example ofFIG. 1by pulling VGATEup to VDDand by minimizing and/or otherwise reducing the DC cross current to provide driving levels of 0 (e.g., a voltage of the reference terminal152) and VDDto effectuate safe and reliable turn-on and turn-off operations of QS148as described herein.

FIG. 2is a schematic illustration of a fourth example gate driver circuit200including QS148and the shunt resistor154ofFIG. 1. The fourth gate driver circuit200includes an example gate driver (e.g., a gate driver circuit)202coupled to QS148ofFIG. 1in a configuration to either turn on or turn off QS148. The gate driver202can be an example implementation of the gate driver108ofFIG. 1. The gate driver202is a rail-to-rail (RR) gate driver because the gate driver202can provide a driving level of either an example supply voltage terminal (VDD)204or an example reference voltage terminal (GND)206for QS148.

InFIG. 2, the gate driver202includes an example latch208, a first example pre-driver (e.g., pre-driver circuit)210, a second example pre-driver212, a first example switch (Q1)214, and second example switches (Q2.1, Q2.2)216,218. The first pre-driver210and the second pre-driver212are rail-to-rail pre-drivers (e.g., rail-to-rail pre-driver circuits). The latch208, the first-pre-driver210, and the second pre-driver212are configured in a cross-coupled arrangement to effectuate non-overlap operation. The first switch214and the second switches216,218are N-type E-mode GaN high electron mobility transistors (HEMTs). InFIG. 2, the first pre-driver210and the second pre-driver212are rail-to-rail pre-drivers. In the example ofFIG. 2, a respective drain (e.g., a current terminal, a drain terminal, etc.) of Q2.1216and Q2.2218are coupled to VDD204. In the example ofFIG. 2, a respective source (e.g., a current terminal, a source terminal, etc.) of Q2.1216and Q2.2218are coupled to a drain of Q1214and the gate of QS148. InFIG. 2, a source of Q1214is coupled to the reference voltage terminal206.

InFIG. 2, Q1214, Q2.1216, and Q2.2218represent an example output stage (e.g., a gate driver output stage)220. In the example ofFIG. 2, Q1214is coupled to and driven by the first pre-driver210. In the example ofFIG. 2, Q2.1216and Q2.2218are coupled to and driven by the second pre-driver212. In example operating conditions, Q2.1216is driven with VDD204for a relatively quick leading edge of a turn-on signal of QS148. In example operating conditions, Q2.2218is driven with a bootstrapped signal greater than VDD204to pull the gate of QS148up to VDD204.

In the illustrated example ofFIG. 2, the first pre-driver210has a first input (INP2), a second input (INN_BD), a first output (OUTP2) (e.g., an enable output), and a second output (OUTN2). InFIG. 2, the second pre-driver212has a first input (INP1), a second input (INN_BD), a first output (OUTP1), a second output (OUTN1), and a third output (OUTP_BST) (e.g., an enable output). Additionally or alternatively, the first pre-driver210may have a third output (OUTP_BST). InFIG. 2, INP1is coupled to a first output (Q) of the latch208and INP2is coupled to a second output (Q) of the latch208.

InFIG. 2, a first example control signal (TURNON)222is coupled to a set input (S) of the latch208. The first control signal222can be received from the output of the logic gate142ofFIG. 1. For example, the first control signal222can be asserted in response to an output from the max off timer140ofFIG. 1being asserted or the falling edge detection of CHV134ofFIG. 1and/or the inverter136ofFIG. 1. A second example control signal (TURNOFF)224is coupled to a reset input (R) of the latch208. The second control signal224can be received from the comparator110ofFIG. 1. For example, the second control signal224can be asserted in response to the comparator110detecting a peak current. InFIG. 2, the latch208is a set-reset (SR) latch. Alternatively, the latch208may be any other type of latch. In some examples, the latch208is an example implementation of the second latch144ofFIG. 1. In some examples, the latch208is coupled to the second latch144ofFIG. 1.

In the illustrated example ofFIG. 2, INN_BD of the first pre-driver210is coupled to OUTN1of the second pre-driver212. InFIG. 2, INN_BD of the second pre-driver212is coupled to OUTN2of the first pre-driver210. In the example ofFIG. 2, OUTP2of the first pre-driver210is coupled to a gate of Q1214. InFIG. 2, OUTP1of the second pre-driver212is coupled to a gate of Q2.1216. InFIG. 2, OUTP_BST of the second pre-driver212is coupled to a gate of Q2.2218.

In example operating conditions, the first control signal222is asserted to set the latch208and cause the latch208to assert a logic high signal to INP1of the second pre-driver212. In response to Q being asserted,Qis pulled down to a logic low signal to invoke the first pre-driver210to pull (e.g., actively pull) a second example enable signal (EN_B)230to ground (e.g., to the reference voltage terminal206) to turn off Q1214. In response to INP1receiving the asserted signal, the second pre-driver212asserts a first example enable signal (EN)226to turn on Q2.1216for a relatively quick leading-edge of the turn signal to enable QS148. In response to INP1receiving the asserted signal, the second pre-driver212asserts an example enable bootstrap signal (EN_BST)228to turn on Q2.2218to pull a gate voltage (VGATE) at the gate of QS148all the way up to VDD204.

In example operating conditions, the first control signal222is de-asserted and the second control signal224is asserted to reset the latch208. In response to asserting the second control signal224and causingQto be asserted high, Q is de-asserted and invokes the second pre-driver212to pull (e.g., actively pull) EN226and EN_BST228to ground (e.g., to the reference voltage terminal206) to turn off Q2.1216and Q2.2218. In response to resetting the latch208, the latch208asserts a logic high signal to INP2of the first pre-driver210. In response to INP2receiving the logic high signal, the first pre-driver210asserts EN_B230to turn on Q1214and, thus, pull down VGATEat the gate of QS148all the way down to GND.

Advantageously, the gate driver202ofFIG. 2can generate at least one of EN226or EN_BST228with a self-timed bootstrap circuit included in the second pre-driver212. For example, the second pre-driver212can generate EN_BST228to have a voltage greater than VDD204to pull the gate of QS148up to VDD204. Advantageously, the gate driver202ofFIG. 2can adjust the pull-up path and the pull-down path to turn on and off to minimize and/or otherwise reduce DC cross current. Advantageously, by adjusting the pull-up path and the pull-down path, the gate driver202can provide GND from the reference voltage terminal206and VDD204as the driving levels for safe turn-on and turn-off of QS148and, thus, effectuate a full rail-to-rail gate driver. Advantageously, the second pre-driver212, and/or, more generally, the gate driver202, can effectuate the full rail-to-rail gate driver without any additional voltage rails or terminals.

FIG. 3is an example timing diagram300associated with the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2. The timing diagram300ofFIG. 3includes example waveforms302,304,306,308,310,312,314,316associated with the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2including a first example waveform302, a second example waveform304, a third example waveform306, a fourth example waveform308, a fifth example waveform310, a sixth example waveform312, a seventh example waveform314, and an eighth example waveform316.

In the illustrated example ofFIG. 3, the first waveform302can correspond to the first control signal222ofFIG. 2. For example, the first waveform302can be representative of the first control signal222coupled to the set input of the latch208ofFIG. 2. In the example ofFIG. 3, the second waveform304can correspond to the second control signal224ofFIG. 2. For example, the second waveform304can be representative of the second control signal224coupled to the reset input of the latch208. InFIG. 3, the third waveform306can correspond to a first signal from the first output (Q) of the latch208that can be delivered to INP1of the second pre-driver212ofFIG. 2.

In the illustrated example ofFIG. 3, the fourth waveform308can correspond to a second signal from the second output (Q) of the latch208that can be delivered to INP2of the first pre-driver210ofFIG. 2. In the example ofFIG. 3, the fifth waveform310can correspond to the first enable signal (EN)226ofFIG. 2. For example, the fifth waveform310can be representative of a signal to control (e.g., to turn on, to turn off, etc.) Q2.1216ofFIG. 2.

In the illustrated example ofFIG. 3, the sixth waveform312can correspond to the enable bootstrap signal (EN_BST)228ofFIG. 2. For example, the sixth waveform312can be representative of a signal to control (e.g., to turn on, to turn off, etc.) Q2.2218ofFIG. 2. In the example ofFIG. 3, the seventh waveform314can correspond to the second enable signal (EN_B)230ofFIG. 2. For example, the seventh waveform314can be representative of a signal to control (e.g., to turn on, to turn off, etc.) Q1214ofFIG. 2. In the example ofFIG. 3, the eighth waveform316can correspond to a gate voltage (VGATE) of QS148ofFIGS. 1 and/or 2.

In the timing diagram300ofFIG. 3, at a first example time (T1)318, the first waveform302is asserted from a first logic level (e.g., a first voltage level) of approximately 0 V to a second logic level (e.g., a second voltage level) of a supply voltage terminal (VDD) (e.g., VDD204ofFIG. 2). At the first time318, the third waveform306is asserted from a logic low level to a logic high level. At the first time318, the fourth waveform308is de-asserted from a logic high level to a logic low level. At the first time318, the seventh waveform314is de-asserted from a first logic high level of VDD to a logic low level of approximately 0 V. For example, at the first time318, the first control signal222can set the latch208to invoke the latch208to assert a logic high signal to INP1of the second pre-driver212and deliver a logic low signal to INP2of the first pre-driver210. In such examples, in response to receiving the logic low signal at INP2, the first pre-driver210de-asserts EN_B230to turn off Q1214.

In the timing diagram300ofFIG. 3, at a second example time (T2)320, the first waveform302is de-asserted, the fifth waveform310is asserted to the first logic level of VDD, the sixth waveform312is asserted to a second logic level based on a sum of VDDand VTH(e.g., a threshold voltage (VGS,TH) associated with Q2.2218ofFIG. 2) and/or otherwise a voltage level greater than VDD. At the second time320, the eighth waveform316begins to increase. For example, in response a logic high signal asserted to INP1, the second pre-driver212asserts EN226to turn on Q2.1216and asserts EN_BST228to turn on Q2.2218. In response to turning on Q2.1216and Q2.2218, the gate voltage (VGATE) at the gate of the switch218increases to turn on QS148. The gate voltage increases from approximately 0 V at the first time318to a voltage based on a difference between VDDand VTH(e.g., a threshold voltage VGS,THassociated with Q2.1216ofFIG. 2) and/or otherwise a voltage level less than VDD at a time shortly after the second time320. The gate voltage increases from the difference between VDDand VTHto VDDat a third example time (T3)322.

In the timing diagram300ofFIG. 3, at a fourth example time (T4)324, the second waveform304is asserted, the third waveform306is de-asserted, the fourth waveform308is asserted, the fifth waveform310is de-asserted, and the sixth waveform312is de-asserted. For example, the second control signal224can be asserted to reset the latch208ofFIG. 2to invoke and/or otherwise cause the latch208to de-assert the first output of the latch208(e.g., the first latch output) to INP1and assert the second output of the latch208to INP2. In response to receiving the de-asserted first output at INP1, the second pre-driver212de-asserts EN226and EN_BST228ofFIG. 2to turn off Q2.1216and Q2.2218.

In the timing diagram300ofFIG. 3, at a fifth example time (T5)326, the second waveform304is de-asserted, the seventh waveform314is asserted, and the eighth waveform316begins to decrease to approximately 0 V. For example, the first pre-driver210can assert EN_B230to turn on Q1214ofFIG. 2to discharge the gate voltage of the switch218to the reference voltage terminal206ofFIG. 2. Advantageously, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2implement a rail-to-rail gate driver by controlling QS148with driving levels that extend a full voltage range from 0 V to VDD as demonstrated by the eighth waveform316of the timing diagram300ofFIG. 3.

FIG. 4is a schematic illustration of a third example pre-driver (e.g., a third pre-driver circuit)400. In the example ofFIG. 4, the third pre-driver400can be an example implementation of the first pre-driver210and/or the second pre-driver212ofFIG. 2. The third pre-driver400has a first input (INP)402, a second input (INN_BD)404, a first output (OUTP)406, a second output (OUTN)408, and a third output (OUTP_BST)410. InFIG. 4, INP402can correspond to INP1of the second pre-driver212and/or INP2of the first pre-driver210. InFIG. 4, the INN_BD404can correspond to INN_BD of the first pre-driver210and/or the second pre-driver212. InFIG. 4, OUTP406can correspond to OUTP1of the first pre-driver210and/or OUTP2of the second pre-driver212. InFIG. 4, OUTN408can correspond to OUTN2of the first pre-driver210and/or OUTN1of the second pre-driver212. InFIG. 4, OUTP_BST410can correspond to OUTP_BST of the second pre-driver212.

The third pre-driver400includes a third example switch (Q3)412, a fourth example switch (Q4)414, a fifth example switch (Q5)416, a sixth example switch (Q6)418, a seventh example switch (Q7)420, an eighth example switch (Q8)422, and a ninth example switch (Q9)424. In the example ofFIG. 4, Q3412, Q4414, Q5416, Q6418, Q7420, Q8422, and Q9424are N-type E-mode GaN HEMTs.

The third pre-driver400includes a first example logic gate426, a second example logic gate428, and a third example logic gate430. In the example ofFIG. 4, the first logic gate426is a NAND gate (e.g., a NAND logic gate). Alternatively, the NAND gate may be replaced with any other combination of logic gates. In the example ofFIG. 4, the second logic gate428and the third logic gate430are inverters, or inverter logic gates. Alternatively, one or both inverters depicted in the example ofFIG. 4may be replaced with any other combination of logic gates. The third pre-driver400includes an example diode (D)432, a first example capacitor (C1)434, and a second example capacitor (C2)436.

The first logic gate426has a first input (e.g., a first NAND input) coupled to INP402and a second input (e.g., a second NAND input) coupled to INN_BD404. The first logic gate426and the second logic gate428are coupled to an example supply voltage terminal (VDD)438and an example reference voltage terminal440. VDDat the supply voltage terminal438can correspond to VDD204ofFIG. 2and/or the reference voltage terminal440can correspond to the reference voltage terminal206ofFIG. 2.

The supply voltage terminal438is coupled to an anode of the diode432, a power input of the second logic gate428, a drain of Q4414, a drain of Q5416, and a drain of Q9424. A cathode of the diode432is coupled to a first plate of C1434and a gate of Q5416. An output terminal (e.g., an inverted output, an inverted output terminal, etc.) of the first logic gate426(e.g., a NAND output, a NAND logic gate output, etc.) is coupled to a second plate of C1434, an input terminal of the second logic gate428, a gate of Q3412, an input terminal of the third logic gate430, a gate of Q6418, a gate of Q8422, and OUTN408. An output terminal of the second logic gate428is coupled to a gate of Q4414. A source of Q5416is coupled to a first plate of C2436, a power input of the third logic gate430, and a drain of Q7420. A source of Q4414is coupled to a drain of Q3412and a second plate of C2436. A source of Q7420is coupled to a drain of Q6418, a gate of Q9424, and OUTP_BST410. A source of Q9424is coupled to OUTP406and a drain of Q8412.

In example operating conditions, C2436is pre-charged to VDDof the supply voltage terminal438. In response to INP402and INN_BD404going high and/or otherwise being asserted, the first logic gate426de-asserts an output of the first logic gate426. In response to the first logic gate426de-asserting the output, OUTN408is de-asserted. The second logic gate428inverts the de-asserted output to an asserted output and/or otherwise output a logic high signal. In response to the second logic gate428outputting a logic high signal, the gate of Q4414is pulled up to VDDof the supply voltage terminal438. In response to the gate of Q4414being pulled up to VDDof the supply voltage terminal438, the source of Q4414and, thus, the second plate of C2436has a voltage based on a difference between VDD438and a threshold voltage of Q4414(VGS,TH,Q4). The first plate of C2436thereby has a voltage of the second plate potential of C2436plus the pre-charged VDDof the supply voltage terminal438. Accordingly, the first plate of C2436can have a voltage of 2*VDD−VGS,TH,Q4.

In example operating conditions, the gate of Q7420is pulled up to the voltage of 2*VDD−VGS,TH,Q4. The source of Q7420, which is coupled to OUTP_BST410, thereby has a voltage of 2*VDD−VGS,TH,Q4−VGS,TH,Q7, which is equivalent to a difference between 2*VDDand 2*VGS,TH(2*VDD−2*VGS,TH). In example operating conditions, the voltage of OUTP_BST410can cause Q2.2218ofFIG. 2to turn on. In example operating conditions, VGS,THis less than one-third of VDDto generate a boundary condition based on the following relationships:
OUTP_BST=(2*VDD)−(2*VTH)=(2*VDD)−(2/3*VDD)=4/3*VDD=VDD+VTH

FIG. 5is a schematic illustration of a fourth example pre-driver (e.g., a fourth pre-driver circuit)500. The fourth pre-driver500can be an example implementation of the first pre-driver210and/or the second pre-driver212ofFIG. 2. The fourth pre-driver500has the first input (INP)402, the second input (INN_BD)404, the first output (OUTP)406, the second output (OUTN)408, and the third output (OUTP_BST)410ofFIG. 4. The fourth pre-driver500includes Q3412, Q4414, Q5416, Q6418, Q7420, Q8422, Q9424, C1434, C2436, and the supply voltage terminal438ofFIG. 4.

The fourth pre-driver500includes a tenth example switch (Q10)502, an eleventh example switch (Q11)504, a twelfth example switch (Q12)506, a thirteenth example switch (Q13)508, a fourteenth example switch (Q14)510, a first example resistor (R1)512, a second example resistor (R2)514, and a third example resistor (R3)516. The tenth switch502, the eleventh switch504, the twelfth switch506, the thirteenth switch508, and the fourteenth switch510are N-type E-mode GaN transistors.

Q10502, Q11504, and R1512can be coupled together in an arrangement to form an example implementation of a NAND logic gate518. For example, Q10502, Q11504, and R1512can be an implementation of the first logic gate426ofFIG. 4. Q13508and R2514can be coupled together in an arrangement to form an example implementation of a first inverter logic gate520. For example, Q13508and R2514can be an implementation of the second logic gate428ofFIG. 4. Q14510and R3516can be coupled together in an arrangement to form an example implementation of a second inverter logic gate522. For example, Q14510and R3516can be an implementation of the third logic gate430ofFIG. 4.

In example operating conditions, Q12506is turned on causing VC1to be approximately a difference between VDDof the supply voltage terminal438and a threshold voltage VGS,THof Q12506. In example operating conditions, in response to INP402being asserted, INN_BD404being asserted, or neither INP402or INN_BD404being asserted, a logic high signal is asserted at the second plate of C1434and respective gates of Q13508, Q3412, Q14410, Q6418, and Q8422to turn on the respective switches. In response to turning on Q13508, VC1becomes a difference between two times VDDof the supply voltage terminal438and the threshold voltage of Q12506(e.g., VC1=2*VDD−VTH). In example operating conditions, in response to INP402and INN_BD404being asserted, a logic low signal is delivered to the second plate of C1434and the respective gates of Q13508, Q3412, Q14510, Q6418, and Q8422to turn off the respective switches.

In example operating conditions, C1434is used to bootstrap Q5416to charge C2436to VDDof the supply voltage terminal438in response to turning on Q3412and Q5416. In response to charging C2436to have a voltage of VDDof the supply voltage terminal, Q7420is turned on to assert a logic high signal at OUTP_BST410, where the logic high signal can correspond to a sum of VDDof the supply voltage terminal and a threshold voltage of Q7420. In response to turning on Q7420, Q9424is turned on to assert a logic high signal at OUTP406, where the logic high signal can correspond to VDDof the supply voltage terminal438. To turn off the fourth pre-driver500, Q6418and Q8422are turned on to de-assert the logic high signals at OUTP406and OUTP_BST410.

FIG. 6depicts graphs600,602of example waveforms604,606,608,610,612associated with the first pre-driver210ofFIG. 2, the second pre-driver212ofFIG. 2, the third pre-driver400ofFIG. 4and/or the fourth pre-driver500ofFIG. 5. The waveforms604,606,608,610,612include a first example waveform604, a second example waveform606, a third example waveform608, a fourth example waveform610, and a fifth example waveform612.

The graphs600,602depict example operating conditions during startup or initialization of the first pre-driver210ofFIG. 2, the second pre-driver212ofFIG. 2, the third pre-driver400ofFIG. 4and/or the fourth pre-driver500ofFIG. 5. The first waveform604can correspond to a voltage at INP1and/or INP2ofFIG. 2, INP402ofFIGS. 4-5, etc. The second waveform606can correspond to a voltage at OUTP ofFIG. 2, OUTP406ofFIGS. 4-5, etc. The third waveform608can correspond to VDD204ofFIG. 2, VDDof the supply voltage terminal438ofFIGS. 4-5, etc. The fourth waveform610can correspond to VC1ofFIGS. 4-5. The fifth waveform612can correspond to VC2ofFIGS. 4-5.

During startup, the third waveform608begins to increase at a first example time (t1)614, the fourth waveform610begins to increase at a second example time (t2)616, and the fifth waveform612begins to increase at a third example time (t3)618.

The third waveform608increases from the first time614to a first voltage (e.g., a voltage in a range of 0 V to 6 V) at a fourth example time (t4)620. The fourth waveform610increases from the second time616to a second voltage (e.g., a voltage in a range of 0 V to 4 V) at the fourth time620. The fifth waveform612increases from the third time618to a third voltage (e.g., a voltage in a range of 0 V to 2 V) at the fourth time620.

FIG. 7is an example timing diagram700associated with the first pre-driver210ofFIG. 2, the second pre-driver212ofFIG. 2, the third pre-driver400ofFIG. 4, and/or the fourth pre-driver500ofFIG. 5. The timing diagram700includes example waveforms702,704,706,708,710,712,714,716including a first example waveform702, a second example waveform704, a third example waveform706, a fourth example waveform708, a fifth example waveform710, a sixth example waveform712, and a seventh example waveform714, and an eighth example waveform716.

Further depicted in the timing diagram700ofFIG. 7are a first example voltage level718based on a sum of VDDand VTH, a second example voltage level720being VDD, and a third example voltage level722being 0 V. Also depicted in the timing diagram700are a fourth example voltage level724based on a difference between 2*VDDand VTH, and a fifth example voltage level726based on a difference between VDDand VTH.

The first waveform702can correspond to VDD204ofFIG. 2and/or VDDof the supply voltage terminal438ofFIGS. 4-5. The second waveform704can correspond to a voltage of INP ofFIG. 2and/or INP402ofFIGS. 4-5. The third waveform706can correspond to a voltage of INN_BD ofFIG. 2and/or INN_BD ofFIGS. 4-5. The fourth waveform708can correspond to a voltage of OUTN ofFIG. 2and/or OUTN408ofFIGS. 4-5. The fifth waveform710can correspond to a voltage of OUTP ofFIG. 2and/or OUTP406ofFIGS. 4-5. The sixth waveform712can correspond to a voltage of OUTP ofFIG. 2and/or OUTP_BST410ofFIGS. 4-5. The seventh waveform714can correspond to a voltage of VC2ofFIGS. 4-5. The eighth waveform716can correspond to a voltage of VC1ofFIGS. 4-5.

At a first example time (t1)728, INP is asserted, INN_BD is de-asserted, and OUTN is asserted (e.g., the first logic gate426ofFIG. 4asserts a logic high signal to OUTN408). At the first time728, VC2is at the second voltage level720, which is VDD, and VC1is at the fourth voltage level724. For example, at the first time728, VC2inFIG. 4is VDDbecause Q3412is turned on and pulls the bottom plate of C2436to ground potential. In such examples, at the first time728, VC1is at a voltage potential based on a difference between 2*VDD and a voltage drop (VD,TH) across D432. In some such examples, the gate of Q5416is connected to this voltage potential and, thus, C2436is charged to VDD. In some such examples, at the first time728, C1434can turn on Q5416to cause VC2to be at VDD.

At a second example time (t2)730, INP and INN_BD are asserted, which causes OUTN to be de-asserted (e.g., the first logic gate426outputs a logic low signal to OUTN408). At the second time730, VC2increases from the second voltage level720to the fourth voltage level724and VC1decreases from the fourth voltage level724to the fifth voltage level726. For example, at the second time730, C1434can charge to a voltage of VDD−VD,TH. In response to OUTN being de-asserted, a logic gate428asserts a logic high signal to the gate of Q4414. The second plate of C2436is pushed to a voltage based on a difference between VDD of the supply voltage terminal438and VTH,Q4of transistor Q4414. This causes VC2to increase to a voltage based on a difference between 2*VDDand a threshold voltage (VTH,Q4) of transistor Q4414.

At the second time730, OUTP and OUTP_BST begin to increase. At a third example time (t3)732, OUTP and OUTP_BST is at VDD(e.g., increased from 0 V). For example, at the second time730, the logic low signal of OUTN is inverted to a logic high signal by the third logic gate430ofFIGS. 4-5to turn on Q7420, which causes the fourth voltage level724(e.g., 2*VDD−VTH) to be output at OUTP_BST at the third time732. In such examples, at the second time730, in response to turning on Q7420, Q9424is turned on to output the second voltage level720(e.g., VDD) at OUTP at the third time732.

FIG. 8depicts a graph800of example waveforms802,804,806associated with turning on the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2. The waveforms802,804,806include a first example waveform802, a second example waveform804, and a third example waveform806. The first waveform802can correspond to VDD204ofFIG. 2and/or VDDof the supply voltage terminal438ofFIGS. 4-5. The second waveform804can correspond to VGATEofFIGS. 1 and 2. The third waveform806can correspond to the first control signal222ofFIG. 2.

Advantageously, the pre-drivers210,212,400,500ofFIGS. 2, 4, and/or5, and/or, more generally, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2, in response to asserting the first control signal222, can turn on QS148ofFIGS. 1 and 2by increasing VGATEfrom a first voltage (e.g., a voltage below 0 V) to a second voltage (e.g., a voltage of approximately 6 V) to implement a full rail-to-rail driver with a high-driving voltage level of approximately VDD.

FIG. 9depicts a graph900of example waveforms902,904,906associated with turning off the gate driver of108ofFIG. 1and/or the gate driver202ofFIG. 2. The waveforms902,904,906include a first example waveform902, a second example waveform904, and a third example waveform906. The first waveform902can correspond to VDD204ofFIG. 2and/or VDDof the supply voltage terminal438ofFIGS. 4-5. The second waveform904can correspond to VGATEofFIGS. 1 and 2. The third waveform906can correspond to the second control signal224ofFIG. 2.

Advantageously, the pre-drivers210,212,400,500ofFIGS. 2, 4, and/or5, and/or, more generally, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2, in response to asserting the second control signal224, can turn off QS148ofFIGS. 1 and 2by decreasing VGATEfrom a first voltage (e.g., a voltage of approximately 6 V) to a second voltage (e.g., a voltage below 0 V) to implement a full rail-to-rail driver with a low-driving voltage level of approximately 0 V.

Advantageously, the pre-drivers210,212,400,500ofFIGS. 2, 4, and/or5, and/or, more generally, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2, can implement a rail-to-rail gate driver without an additional voltage rail or terminal, an additional charge pump circuit, etc. Advantageously, the pre-drivers210,212,400,500ofFIGS. 2, 4, and/or5, and/or, more generally, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2, can dynamically generate a bootstrapped voltage (e.g., a voltage at the gate of Q2.2218ofFIG. 2).

Advantageously, the pre-drivers210,212,400,500ofFIGS. 2, 4, and/or5, and/or, more generally, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2, can implement a rail-to-rail gate driver using one bootstrap stage (e.g., Q2.2218). Advantageously, the pre-drivers210,212,400,500ofFIGS. 2, 4, and/or5, and/or, more generally, the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2, can implement a rail-to-rail gate driver by splitting a single pull-up transistor into at least two transistors (e.g., Q2.1216and Q2.2218) as depicted in the example ofFIG. 2.

Advantageously, by splitting the single pull-up transistor into at least two transistors, the fourth gate driver circuit200ofFIG. 2can effectuate improved switching behavior (e.g., more efficient switching behavior) because the bootstrapped signal (e.g., EN_BST228ofFIG. 2) does not need to drive the full output stage, but, instead, in some examples, can drive a portion of the full output stage. For example, the second pre-driver212ofFIG. 2can assert EN_BST228to drive a portion of VGATEofFIG. 2.

A flowchart representative of an example process that may be carried out while utilizing example hardware logic, example machine readable instructions (e.g., hardware readable instructions), example hardware implemented state machines, and/or any combination thereof for implementing the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2is shown inFIG. 10. The example machine readable instructions may be one or more executable programs or portion(s) of an executable program for execution by programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)). The program may be embodied in software stored on a non-transitory computer readable storage medium such as a non-volatile memory, volatile memory, etc., but the entire program and/or parts thereof could alternatively be executed by any other device (e.g., programmable device) and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowchart illustrated inFIG. 10, many other methods of implementing the example gate driver108ofFIG. 1and/or the example gate driver202ofFIG. 2may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware.

FIG. 10is a flowchart representative of an example process1000that may be carried out while utilizing machine readable instructions that can be executed and/or hardware configured to implement the gate driver108ofFIG. 1and/or the gate driver202ofFIG. 2to control a power transistor, such as QS148ofFIG. 1. The example process1000ofFIG. 10begins at block1002, at which the gate driver108and/or the gate driver202generates control signal(s) to turn on a first pre-driver circuit to turn off a power transistor. For example, an assertion of the second control signal224can be generated to reset the latch208ofFIG. 2. In such examples, the latch208can de-assert a first signal at INP1of the second pre-driver212and assert a second signal at INP2of the first pre-driver210. In response to asserting the second signal at INP2, the first pre-driver210asserts EN_B230to turn on Q1214ofFIG. 2. In response to turning on Q1214, QS148turns off.

At block1004, the gate driver108and/or the gate driver202output a signal to a cross-coupled second pre-driver circuit. For example, the first pre-driver circuit210can output an assertion of OUTN2and transmit the assertion of OUTN2to INN_BD of the second pre-driver212.

At block1006, the gate driver108and/or the gate driver202generate a first voltage greater than a voltage of a supply voltage terminal (VDD) to bootstrap a transistor in the second pre-driver circuit. For example, the first logic gate426ofFIG. 4can assert a logic high signal in response to INP402being de-asserted and INN_BD404being asserted (e.g., OUTN2from the first pre-driver circuit210being asserted and transmitted to INN_BD404of the second pre-driver212). In such examples, the first logic gate426can assert the logic high signal to cause VC1ofFIG. 4to become 2*VDD−VTH(e.g., the fourth voltage level724ofFIG. 7), which is greater than VDD of the supply voltage terminal438, to bootstrap the gate of Q5416ofFIG. 4and, thus, turn on Q5416. In some such examples, the first logic gate426can assert the logic high signal to turn on Q3412to charge C2436to VDD of the supply voltage terminal438when Q5416is on.

At block1008, the gate driver108and/or the gate driver202turn on the bootstrapped transistor to generate a second voltage. For example, C1434can be used to turn on Q5416to charge C2436to VDDof the supply voltage terminal438in response to Q5416and Q3412being turned on.

At block1010, the gate driver108and/or the gate driver202generate control signal(s) to turn off the first pre-driver circuit and turn on the second pre-driver circuit. For example, an assertion of the first control signal222can be generated to set the latch208. In such examples, the latch208can assert the first signal at INP1of the second pre-driver212and de-assert the second signal at INP2of the first pre-driver210.

At block1012, the gate driver108and/or the gate driver202output a bootstrap signal having a voltage greater than VDD to turn on a first high-side transistor to turn on the power transistor. For example, in response to asserting the first signal at INP1, the second pre-driver212asserts EN_BST228to turn on a first high-side transistor, such as Q2.2218ofFIG. 2. The gate of Q2.2218is driven with a bootstrapped signal greater than VDD204to pull the gate of QS148up to VDD204. For example, the first logic gate426can de-assert a logic signal to invoke the second logic gate428to turn on Q4414and invoke the third logic gate430to turn on Q7420. In response to turning on Q7420, a voltage of VDD+VTHis transferred to OUTP_BST410.

At block1014, the gate driver108and/or the gate driver202output an enable signal to turn on a second high-side transistor to turn on the power transistor. For example, in response to asserting the first signal at INP1, the second pre-driver212asserts EN226to turn on a second high-side transistor, such as Q2.1216ofFIG. 2. The gate of Q2.1216is driven with VDD204for a quick leading edge of the turn on of QS148. For example, the first logic gate426can de-assert a logic signal to invoke the second logic gate428to turn on Q4414and invoke the third logic gate430to turn on Q7420. In response to turning on Q7420, a voltage of VDD is transferred to OUTP406.

At block1016, the gate driver108and/or the gate driver202determine whether to continue controlling the power transistor. If, at block1016, the gate driver108and/or the gate driver202determine to continue controlling the power transistor, control returns to block1002to generate control signal(s) to turn on the first pre-driver circuit to turn off the power transistor, otherwise the example process1000ofFIG. 10concludes.

FIG. 11is a schematic illustration of a differential amplifier1100that can be an input stage of a comparator circuit. The differential amplifier1100includes N-type E-mode GaN transistors Q1, Q2, QC1, QC2, QC3, QC4, QC5, QC6, and resistors R1and R2arranged in a configuration to amplify a difference between an input voltage (INP) and a reference voltage (INN). The differential amplifier1100can generate an amplified output signal (OUTP−OUTN) based on the difference. For example, the amplified output signal can be 10*(INP−INN), 20*(INP−INN), etc.

As Q1and Q2are N-type E-mode GaN transistors, a respective one of Q1and Q2are turned on with a voltage greater than a threshold voltage (VGS,TH) of the respective one of Q1and Q2. Accordingly, the differential amplifier1100may have a reduced voltage range that can be used for INN and INP because lower voltages for INN and INP may not be high enough to turn on a respective one of Q1and Q2. The accuracy of the differential amplifier1100is based on matching Q1and Q2. However, if Q1and Q2are based on the semiconductor wafer, then even if Q1and Q2have the same size, Q1and Q2may be mismatched and, thus, can cause the differential amplifier1100to have a relatively large offset voltage.

FIG. 12is a schematic illustration of an example comparator circuit1200. The comparator circuit1200is an auto-zero comparator circuit. The comparator circuit1200includes an example comparator1202, a first example capacitor (C1)1204, a second example capacitor (C2)1206, a first example switch1208, a second example switch1210, a third example switch1212, and fourth example switch1214. The comparator1202can be an example implementation of the comparator110ofFIG. 1. The first switch1208and the second switch1210are N-type E-mode GaN transistors. The third switch1212and the fourth switch1214are example bootstrapped switch circuits represented by a switch. An example implementation of the third switch1212and/or the fourth switch1214is described below in connection withFIG. 15. Alternatively, the third switch1212and/or the fourth switch1214may be N-type E-mode GaN transistors.

InFIG. 12, a first signal (e.g., a voltage) (VSIG) is coupled to a first example terminal1216of the comparator circuit1200. VSIGcan be representative of a voltage that is desired to be compared to a reference. For example, VSIGcan correspond to VSIGofFIG. 1. A second signal (e.g., a voltage) (VREF) is coupled to a second example terminal1218of the comparator circuit1200. VREFcan be representative of a reference voltage. For example, VREFcan correspond to VREFinFIG. 1, which is at the second input of the comparator110ofFIG. 1. The first switch1208is coupled to the first terminal1216. The second switch1210and C21206are coupled to the second terminal1218.

C11204is coupled to the first switch1508, the second switch1210, the third switch1212, and a first input (designated with a ‘+’ symbol) of the comparator1202. C21206is coupled to the second switch1210, the fourth switch1214, and a second input (designated with a ‘−’ symbol) of the comparator1202. C11204is coupled to the first input of the comparator1202and the third switch1212at a first example node1226. C21206is coupled to the second input of the comparator1202and the fourth switch1214at a second example node1228.

The third switch1212is coupled to a first differential output (DIFF_N) of the comparator1202. The fourth switch1214is coupled to a second differential output (DIFF_P) of the comparator1202. The comparator1202has an example output terminal (OUT) (e.g., a comparator output terminal)1224. For example, the output terminal1224ofFIG. 12can correspond to the output of the comparator110ofFIG. 1, which is coupled to the reset input of the second latch144. In such examples, the output terminal1224ofFIG. 12can be coupled to the reset input of the second latch144.

The first switch1208is controlled by a first example control signal (φAZ_B)1220. The second switch1210, the third switch1212, and the fourth switch1214are controlled by a second example control signal (φAZ)1222. The first control signal1220is an enable signal that can be asserted while a main power transistor, such as QS148ofFIG. 1, is turned on. For example, the first control signal1220can be asserted in response to turning on QS148and can be de-asserted in response to turning off QS148. Accordingly, the comparator1202can be active, enabled, etc., and/or otherwise executing a voltage comparison (e.g., comparing VSIGto VREF) in response to QS148being active and, thus, causing the first control signal1220to be asserted.

The second control signal1222can be asserted to invoke an auto-zero (AZ) operation of the comparator circuit1200. The second control signal1222is an inverted enable signal provided by a pull-down path of a gate driver. For example, the second control signal1222can be asserted in response to turning off QS148and can be de-asserted in response to turning on QS148. Accordingly, the comparator1202can be instructed to execute an auto-zero operation instead of a voltage comparison (e.g., comparing VSIGto VREF) in response to QS148being disabled and, thus, causing the first control signal1220to be asserted.

Advantageously, a general auto-zero loop is implemented around the differential stages (DIFF_N and DIFF_P) of the comparator circuit1200to reduce the input referred offset of the comparator circuit1200. Advantageously, C11204and C21206are coupled to the comparator1202in an arrangement to extend the DC input common mode range to full rail-to-rail (e.g., from a ground terminal (GND) to a supply voltage terminal (VDD)).

In example operating conditions, the comparator circuit1200can be instructed and/or otherwise invoked to execute a comparison operation. For example, the first control signal1220can be asserted to close the first switch1208and the second control signal1222can be de-asserted to open the second through fourth switches1210,1212,1214. In such examples, VSIGis stored on C11204and VREFis stored on C21206. The comparator1202can compare VSIGto VREF. In response to VSIGbeing greater than VREF, the comparator1202asserts a logic high signal (e.g., 3.3 V, 5 V, etc.), at the output terminal1224, otherwise the comparator1202generates a logic low signal (e.g., 0 V, 0.5 V, etc.) at the output terminal1224.

In example operating conditions, the comparator circuit1200can be instructed and/or otherwise invoked to execute an auto-zero operation. For example, the first control signal1220can be de-asserted and the second control signal1222can be asserted. In such examples, the differential stages (DIFF_N and DIFF_P) are placed into a unity gain configuration by coupling the differential outputs to the corresponding inputs of the comparator1202.

In response to invoking the auto-zero operation, a first voltage of DIFF_N becomes the same voltage at the first input of the comparator1202, which can be stored on a first plate of C11204. For example, the first voltage can be a first drain voltage associated with a first transistor (e.g., Q4ofFIG. 13). A second voltage of DIFF_P can be the same voltage at the second input of the comparator1202, which can be stored on a first plate of C21206. For example, the second voltage can be a second drain voltage associated with a second transistor (e.g., Q3ofFIG. 13). By closing the second switch1210, VREFis transferred to second plates of C11204and C21206. Accordingly, an offset voltage associated with the transistors, such as Q11312, Q21314, Q31344, and Q41346ofFIG. 13, can be sampled on C11204and C21206. For example, if the first drain voltage associated with DIFF_N is higher than the second drain voltage associated with DIFF_P, then the voltage sampled on C11204is greater than the voltage sampled on C21206.

In example operating conditions, in response to asserting the first control signal1220and de-asserting the second control signal1222, VSIGor VREFcan be level shifted based on the previously sampled offset voltage. For example, if a first input transistor associated with VSIGhad a greater drain voltage than a drain voltage of a second input transistor associated with VREF, then the sampled voltage stored on C21206is greater than the sampled voltage stored on C11204. In such examples, VREFcan be level shifted higher by an amount of the sampled voltage to eliminate and/or otherwise reduce an effect of the offset voltage of the input transistors on a subsequent comparison by the comparator1202.

FIG. 13is a schematic illustration of an example comparator1300. The comparator1300of the example ofFIG. 13is a comparator circuit that can be an example implementation of the comparator110ofFIG. 1and/or the comparator1202ofFIG. 12. The comparator1300includes a first example differential stage1302, a second example differential stage1304, an example cross-coupled latch1306, and an example output stage1308. The first differential stage1302is a first differential amplifier (e.g., a first differential amplifier circuit) and the second differential stage1304is a second differential amplifier (e.g., a second differential amplifier circuit). For example, the first differential amplifier stage1302and/or the second differential amplifier stage1304may implement the differential amplifier1100ofFIG. 11.

The first differential stage1302includes an example input stage1310, which includes a first example transistor (Q1)1312and a second example transistor (Q2)1314. Q11312and Q21314are input transistors (e.g., input stage transistors). The input stage1310obtains signals (e.g., voltages) to compare, such as VSIGcoupled to Q21314and VREF(a reference voltage) coupled to Q11312.

The first differential stage1302includes a first example resistor (R1)1316, a second example resistor (R2)1318, a first example common mode transistor (QC1)1320, a second example common mode transistor (QC2)1322, a third example common mode transistor (QC3)1324, a fourth example common mode transistor (QC4)1326, a fifth example common mode transistor (QC5)1328, and a sixth example common mode transistor (QC6)1330. For example, QC1-QC61320,1322,1324,1326,1328,1330are common mode transistors. In an example, Q11312, Q21314, QC11320, QC21322, QC31324, QC41326, QC51328, and QC61330are N-type E-mode GaN transistors.

R11316, R21318, a drain (e.g., a current terminal, a drain terminal, etc.) of QC11320, and a drain of QC41326are coupled to a supply voltage terminal (VDD)1332. A source of QC11320is coupled to a drain of QC21322, to a gate of QC21322, and to a gate (e.g., a gate terminal) of QC31324. A source (e.g., a current terminal, a source terminal, etc.) of QC41326is coupled to a drain of QC51328, to a gate of QC51328, and to a gate of QC61330. A source of Q11312of coupled to a source of Q21314, to a drain of QC31324, and to a drain of QC61330. Sources of QC21322, QC31324, QC51328, and QC61330are coupled to a reference terminal (e.g., a ground terminal)1334. The first differential stage1302is coupled to the second differential stage1304via a first example node1336and a second example node1338.

The second differential stage1304includes a third example resistor (R3)1340, a fourth example resistor (R4)1342, a third example transistor (Q3)1344, a fourth example transistor (Q4)1346, a seventh example common mode transistor (QC7)1348, and an eighth example common mode transistor (QC8)1350. In an example, Q31344, Q41346, QC71348, and QC81350are N-type E-mode GaN transistors.

QC1through QC81320,1322,1324,1326,1328,1330,1348,1350are used in common mode feedback loops. For example, QC1-QC61320,1322,1324,1326,1328,1330are coupled in an arrangement to establish a common mode loop (e.g., a common mode feedback loop) to adjust current flowing through Q11312and Q21314in order to set a proper common mode voltage at the drains of Q11312and Q21314to achieve a desired common mode. QC71348and QC81350are coupled in an arrangement to establish a common mode loop to set the currents through Q31344and Q41346to have the proper common mode voltage at the drains of Q31344and Q41346.

R31340and R41342are coupled to VDD1332. A drain of Q31344is coupled to R31340. A drain of Q41346is coupled to R41342. A source of Q31344is coupled to a source of Q41346, to a drain of QC71348, and to a drain of QC81350. Sources of QC71348and QC81350are coupled to the reference terminal1334. The first node1336is coupled to a gate of Q41346to deliver and/or otherwise transfer the signal PRE_P from the first differential stage1302to the second differential stage1304. The second node1338is coupled to a gate of Q31344to deliver and/or otherwise transfer the signal PRE_N from the first differential stage1302to the second differential stage1304.

The second differential stage1304is coupled to the cross-coupled latch1306. The gate of QC81350is coupled to the gates of Q71356and Q81358. The gate of QC71348is coupled to the gates of Q91360and Q101362, the drain of Q101362, and the drain of Q81358.

The cross-coupled latch1306includes a seventh example transistor (Q7)1356, an eighth example transistor (Q8)1358, a ninth example transistor (Q9)1360, and a tenth example transistor (Q10)1362. In an example, Q71356, Q81358, Q91360, and Q101362are N-type E-mode GaN transistors. A drain of Q71356is coupled to a source of Q51352, to a gate of Q71356, to a gate of Q81358, and to a drain of Q91360. A drain of Q81358is coupled to a source of Q61354, to a drain of Q101362, to a gate of Q101362, to a gate of Q91360, and to a gate of QC71348. A gate of Q91360is coupled to the gate of Q101362. Sources of Q71356, Q81358, Q91360, and Q101362are coupled to the reference terminal1334.

The second differential stage1304is coupled to a fifth example transistor (Q5)1352and a sixth example transistor (Q6)1354. In some examples, the second differential stage1304includes Q51352and Q61354. For example, Q51352, Q61354, Q71356, Q101362, QC71348, and QC81350are coupled together in an arrangement to form a common mode feedback loop for the second differential stage1304. In such examples, Q51352can operate similarly to QC11320, Q61354can operate similarly to QC41326, Q71356can operate similarly to QC21322, Q101362can operate similarly to QC51328, QC71348can operate similarly to QC31324, and QC81350can operate similarly to QC61330. R31340and the drain of Q31344are coupled to a gate of Q51352. R41342and the drain of Q41346are coupled to a gate of Q61354. Drains of Q51352and Q61354are coupled to VDD1332. In an example, Q51352and Q61354are N-type E-mode GaN transistors. The output stage1308includes a fifth example resistor (R5)1364, a sixth example resistor (R6)1366, an eleventh example transistor (Q11)1368, and a twelfth example transistor (Q12)1370. Q111368and Q121370are N-type E-mode GaN transistors. R51364and R61366are coupled to VDD1332. A drain of Q111368is coupled to R51364and a gate of Q121370. A drain of Q121370is coupled to R61366and an example output terminal (OUT)1372. For example, the output terminal1372ofFIG. 13can correspond to the output terminal1224ofFIG. 12.

The comparator1300includes the first differential stage1302to increase a gain of a voltage difference between VSIGand VREFat the input stage1310. The first differential stage1302generates first example amplified signals PRE_P and PRE_N. For example, in response to VSIGbeing greater than VREF, Q21314is turned on harder (e.g., conducts more current) than Q11312, which causes PRE_N to decrease (and PRE_P to increase). In response to PRE_N decreasing, Q41346turns on harder than Q31344, which causes DIFF_P to increase (and DIFF_N to decrease). In other examples, in response to VSIGbeing less than VREF, PRE_P decreases in voltage and turns on Q31344harder than Q41346to cause DIFF_N to increase in voltage.

The comparator1300includes the second differential stage1304to increase the gain of the auto-zero loop, such as the auto-zero loop depicted inFIG. 12. For example, the second differential stage1304can increase the gain of the voltage difference between VSIGand VREFgenerated by the first differential stage1302. Q51352and Q61354act and/or otherwise operate as source followers to feed the signal from the second differential stage1304to the cross-coupled latch1306for improved gain and to add a hysteresis. The gate-to-source voltage (VGS) of Q71356and Q101362is used as bias voltage for the current source devices QC81350and QC71348, respectively. Depending on the differential input signal, either QC71348or QC81350can deliver the bias current for the second differential stage1304.

Q51352and Q61354are source followers. For example, the voltage at the source of Q51352follow the voltage at the gate of Q51352shifted by the threshold voltage of Q51352. In other examples, the voltage at the source of Q61354follow the voltage at the gate of Q61354shifted by the threshold voltage of Q61354. In example operating conditions, in response to VSIGbeing greater than VREFand causing Q41346to turn on harder than Q31344, DIFF_P increases in voltage to increase the voltage at the gate of Q51352and, thus, increase the voltage at the source of Q51352.

In example operating conditions, QC71356, Q91360, and Q101362are turned off because they have their gates connected together and their sources are connected to the reference terminal1334. In such example operating conditions, VGSof QC71356, Q91360, and Q101362can be 1.5 V, which is less than a VGS,THof approximately 2 V for respective ones of QC71356, Q91360, and Q101362.

In example operating conditions, QC81350, Q71356, Q81358, and Q111368are turned on because they have their gates connected together and their sources are connected to the reference terminal1334. In such example operating conditions, VGSof QC81350, Q71356, Q81358, and Q111368can be 2.5 V, which is greater than a VGS,THof approximately 2 V for respective ones of QC71356, Q91360, and Q101362. In response to Q111368being turned on, the gate of Q121370is pulled to the reference terminal1334and, thereby, causing Q121370to turn off. In response to turning off Q121370, the voltage at the output terminal1372goes high. In such example operating conditions, in response to QC71348being turned off and QC81350being turned on, only QC81350delivers the bias current for the second differential stage1304.

FIG. 14depicts graphs including example waveforms1402,1404,1406,1408,1410,1412,1414,1416associated with the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13. The waveforms1402,1404,1406,1408,1410,1412,1414,1416include a first example waveform1402, a second example waveform1404, a third example waveform1406, a fourth example waveform1408, a fifth example waveform1410, a sixth example waveform1412, a seventh example waveform1414, and an eighth example waveform1416. Further depicted is an example voltage level (VGS,TH,Q7, VGS,TH,Q11)1418corresponding to a threshold voltage of Q71356and Q111368ofFIG. 13.

The first waveform1402is a waveform of a reference voltage that can correspond to VREFofFIGS. 1, 12, 13, and/or14. The second waveform1404is a waveform of a signal voltage that can correspond to VSIGofFIGS. 1, 12, 13, and/or14. The third waveform1406is a waveform of a voltage that can correspond to PRE_N ofFIG. 13. The fourth waveform1408is a waveform of a voltage that can correspond to PRE_P ofFIG. 13. The fifth waveform1410is a waveform of a voltage that can correspond to DIFF_N ofFIGS. 12 and/or 13. The sixth example waveform1412is a waveform of a voltage that can correspond to DIFF_P ofFIGS. 12 and/or 13. The seventh example waveform1414is a waveform of a gate-to-source voltage that can correspond to the gate-to-source voltages (VGS,TH,Q7, VGS,TH,Q11) of Q71356and Q111368ofFIG. 13. The eighth example waveform1416is a waveform of a comparator output voltage that can correspond to an output of the comparator110ofFIG. 1, a voltage at the output terminal1224ofFIG. 12, and/or a voltage at the output terminal1372ofFIG. 13.

At a first example time (t1)1420, VSIGis less than VREF, which causes PRE_N to be greater than PRE_P and DIFF_N to be greater than DIFF_P. For example, in response to VSIGbeing less than VREF, Q11312ofFIG. 13is turned on harder than Q21314, which causes PRE_N to increase in voltage and PRE_P to decrease in voltage. In such examples, in response to PRE_N being greater than PRE_P, Q31344is turned on harder than Q41346, which causes DIFF_N to be greater than DIFF_P. At the first time1420, VGS,Q7and VGS,Q11are less than the threshold voltage1418, which causes Q71356and Q111368ofFIG. 13to turn off. When Q111368is turned off, the gate of Q121370is pulled up to VDD1332by R51364, which causes Q121370to turn on and pull down the output signal at the output terminal1372of the comparator1300to a logic low level (e.g., 0 V).

At a second example time (t2)1422, VSIGis approximately equal to VREF. After a relatively short time after the second time1422, VSIGis greater than VREF, which causes PRE_P to be greater than PRE_N and DIFF_P to be greater than DIFF_N. For example, in response to VSIGbeing greater than VREF, Q21314ofFIG. 13is turned on harder than Q11312, which causes PRE_P to increase in voltage and PRE_N to decrease in voltage. In such examples, in response to PRE_P being greater than PRE_N, Q41346is turned on harder than Q31344, which causes DIFF_P to be greater than DIFF_N. After the second time1422, VGS,Q7and VGS,Q11are greater than the threshold voltage1418, which causes Q71356and Q111368ofFIG. 13to turn on. When Q111368is turned on, Q111368pulls down the gate of Q121370to turn off Q121370. Thereby, the output signal at the output terminal1372of the comparator1300is pulled up to VDD1332by R61366to a logic high level.

FIG. 15is a schematic illustration of an example bootstrapped switch circuit1500. The bootstrapped switch circuit1500ofFIG. 15is an example implementation of the third switch1212and/or the fourth switch1214ofFIG. 12. Advantageously, the bootstrapped switch circuit1500is operable to put the comparator circuit1200ofFIG. 12in a unity-gain configuration for auto-zeroing without P-type devices (e.g., P-type transistors). Advantageously, the bootstrapped switch circuit1500can provide well-matched switch resistance for the feedback paths depicted inFIG. 12(e.g., a feedback path from DIFF_N to the third switch1212to C11204ofFIG. 12).

The bootstrapped switch circuit1500includes a first example transistor (Q1)1502, a second example transistor (Q2)1504, a third example transistor (Q3)1506, a fourth example transistor (Q4)1508, a fifth example transistor (Q5)1510, a sixth example transistor (Q6)1512, a seventh example transistor (Q7)1514, an eighth example transistor (QINV)1516, a ninth example transistor (QSW)1518, a first example capacitor (C1)1520, a second example capacitor (C2)1522, a third example capacitor (C3)1524, an example resistor (RINV)1526, a first example logic gate1528, a second example logic gate1530, an example input voltage terminal1532and an example output voltage terminal1534. Further depicted inFIG. 15is an example supply voltage terminal (VDD)1536and an example reference voltage terminal (e.g., a ground terminal)1538. Q11502, Q21504, Q31506, Q41508, Q51510, Q61512, Q71514, QINV1516, and QSW1518are N-type E-mode GaN transistors. The first logic gate1528and the second logic gate1530are inverters (e.g., inverter logic gates).

The bootstrapped switch circuit1500includes an example charge pump1540and an example bootstrapping circuit1542. The charge pump1540is a cross-coupled charge pump. The charge pump1540includes Q11502, Q21504, C11520, C21522, the first logic gate1528and the second logic gate1530. The bootstrapping circuit1542includes Q31506, Q41508, Q51510, Q61512, Q71514, QINV1516, QSW1518, C31524, and the resistor1526.

In some examples where the third switch1212ofFIG. 12is implemented by the bootstrapped switch circuit1500, the input voltage terminal1532is coupled to the DIFF_N output of the comparator1202. In such examples, the output voltage terminal1534can be coupled to the first node1226ofFIG. 12. In some such examples, QSW1518can correspond to the third switch1212.

In some examples where the fourth switch1214ofFIG. 12is implemented by the bootstrapped switch circuit1500, the input voltage terminal1532is coupled to the DIFF_P output of the comparator1202. In such examples, the output voltage terminal1534can be coupled to the second node1228ofFIG. 12. In some such examples, QSW1518can correspond to the fourth switch1214.

Drains of Q11502, Q21504, and Q31506are coupled to VDD1536. A source of Q11502is coupled to C11520, a gate of Q21504and a gate of Q31506. A source of Q21504is coupled to a gate of Q11502, C21522, and the resistor1526. A source of Q31506is coupled to C31524and a drain of Q51510. A drain of QINV1516is coupled to the resistor1526and a gate of Q51510. A source of Q51510is coupled to a drain of Q61512and respective gates of Q71514and QSW1518. A drain of Q41508is coupled to C31524and a drain of Q71514. A source of Q71514and a drain of QSW1518is coupled to the input voltage terminal1532. A drain of QSW1518is coupled to the output voltage terminal1534.

An input terminal of the first logic gate1528is coupled to a first signal input that is configured to obtain a first control signal, which in the example ofFIG. 15, is the second control signal1222ofFIG. 12. An output terminal of the first logic gate1528is coupled to C11520, an input terminal of the second logic gate1530, and respective gates of Q41508, QINV1516, and Q61512. An output terminal of the second logic gate1530is coupled to C21522. The first logic gate1528is configured to invert the first control signal to a second control signal (φA).

In example operating conditions, such as when the comparator1202ofFIG. 12is in normal operation and/or otherwise executing a comparison operation of VSIGand VREF, VDD1536is stored on C31524. In example operating conditions, such as when the comparator1202ofFIG. 12is in auto-zero operation and/or otherwise executing an auto-zero operation, an input voltage (VIN) at the input voltage terminal1532is coupled to a second plate of C31524and the drain of Q41508. In response to coupling the input voltage terminal1532to the second plate of C31524, a voltage sum of VDDand VINis delivered and/or otherwise guided to QSW1518to provide a constant gate-to-source voltage of VDDindependent of VIN. In example operating conditions, the charge pump1540provides and/or otherwise delivers a voltage of 2*VDD1536to the gate of Q31506to charge C31524to VDD1536and to apply the voltage sum (i.e., VDD+VIN) to the gate of QSW1518via Q51510. Advantageously, the bootstrapping circuit1542includes QSW1518coupled in an arrangement that is suitable for input voltages in a range of 0 to VDD1536.

FIG. 16depicts graphs including example waveforms1602,1604,1606,1608,1610,1612associated with the third switch1212ofFIG. 12, the fourth switch1214ofFIG. 12, and/or the bootstrapped switch circuit1500ofFIG. 15during initialization or startup. The waveforms1602,1604,1606,1608,1610,1612include a first example waveform1602, a second example waveform1604, a third example waveform1606, a fourth example waveform1608, a fifth example waveform1610, and a sixth example waveform1612.

The first waveform1602is a waveform of a supply voltage terminal, such as VDD1536ofFIG. 15. For example, VDDinFIG. 16can have a range of 0 V to 6 V. The second waveform1604is a waveform of a voltage of a control signal, such as the second control signal ofFIG. 15. The third waveform1606is a waveform of a voltage of a control signal, such as the first control signal1220ofFIGS. 12 and/or 15. The fourth waveform1608is a waveform of a voltage, such as VC1ofFIG. 15. The fifth waveform1610is a waveform of a voltage, such as VC2ofFIG. 15. The sixth waveform1612is a waveform of a voltage, such as VC3ofFIG. 15.

FIG. 17is an example timing diagram1700associated with the third switch1212ofFIG. 12, the fourth switch1214ofFIG. 12, and/or the bootstrapped switch circuit1500ofFIG. 15. The timing diagram1700includes example waveforms1702,1704,1706,1708,1710,1712,1714,1716,1718including a first example waveform1702, a second example waveform1704, a third example waveform1706, a fourth example waveform1708, a fifth example waveform1710, a sixth example waveform1712, a seventh example waveform1714, an eighth example waveform1716, and a ninth example waveform1718.

The first waveform1702is a waveform of a supply voltage terminal, such as VDD1536ofFIG. 15. For example, the first waveform1702ofFIG. 17can correspond to the first waveform1602ofFIG. 16. The second waveform1704is a waveform of a voltage of a control signal, such as the second control signal ofFIG. 15. For example, the second waveform1704ofFIG. 17can correspond to the second waveform1604ofFIG. 16. The third waveform1706is a waveform of a voltage of a control signal, such as the first control signal1220ofFIGS. 12 and/or 15. For example, the third waveform1706ofFIG. 17can correspond to the third waveform1606ofFIG. 16. The fourth waveform1708is a waveform of a voltage, such as VC1ofFIG. 15.

The fourth waveform1708ofFIG. 17can correspond to the fourth waveform1608ofFIG. 16. The fifth waveform1710is a waveform of a voltage, such as VC2ofFIG. 15. For example, the fifth waveform1710ofFIG. 17can correspond to the fifth waveform1610ofFIG. 16. The sixth waveform1712is a waveform of a voltage, such as VC3ofFIG. 15. For example, the sixth waveform1712ofFIG. 17can correspond to the sixth waveform1612ofFIG. 16. The seventh waveform1714is a waveform of an input voltage, such as VINofFIG. 15. The eighth waveform1716is a waveform of an output voltage, such as VOUTofFIG. 15. The ninth waveform1718is a waveform of a gate voltage of a transistor (VG,SW), such as a voltage at the gate of QSW1518ofFIG. 15.

In the timing diagram1700ofFIG. 17, at a first example time (t1)1720, φAZtransitions from a logic low to a logic high, which causes φAto transition from a logic high to a logic low. For example, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13can execute an auto-zero operation by coupling the differential outputs (DIFF_N and DIFF_P) of the comparator110,1202,1300to the inputs of the comparator110,1202,1300at the first time1720. In response to φAtransitioning to a logic low, VC1ofFIG. 15decreases from 2*VDD1536to VDD1536. In response to φAtransitioning to a logic low, the second logic gate1530inverts the logic low to a logic high, which causes VC2to increase from VDD1536to 2*VDD1536. In response to φAtransitioning to a logic low, Q41508ofFIG. 15is turned off, which causes VC3to increase. In response to φAtransitioning to a logic low, an inverter implemented by QINV1516and RINV1526ofFIG. 15inverts the logic low to a logic high to turn on Q51510, which causes the gate voltage of QSW1518(VG,SW) to increase. In response to VG,SWincreasing, QSW1518ofFIG. 15turns on to transfer VINfrom the input voltage terminal1532as VOUTat the output voltage terminal1534to execute the auto-zero operation.

In the timing diagram1700ofFIG. 17, at a second example time (t2)1722, φAZtransitions from a logic high to a logic low, which causes φAto transition from a logic low to a logic high. For example, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13can execute a comparison of VSIGand VREFat the second time1722. At the second time1722, when φAZis low, C31524ofFIG. 15is recharged to VDD1536in response to turning on Q31506and Q41508ofFIG. 15. In response to φAtransitioning to a logic high, VC1ofFIG. 15increases from VDD1536to 2*VDD1536. In response to φAtransitioning to a logic high, the second logic gate1530inverts the logic high to a logic low, which causes VC2to decrease from 2*VDD1536to VDD1536. In response to φAtransitioning to a logic high, Q41508ofFIG. 15is turned on, which causes VC3to decrease. In response to φAtransitioning to a logic high, the inverter implemented by QINV1516and RINV1526ofFIG. 15inverts the logic high to a logic low to turn off Q51510, which causes the gate voltage of QSW1518(VG,SW) to decease. In response to VG,SWdecreasing, QSW1518ofFIG. 15turns off and, thus, enabling the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13to compare VSIGto VREFwith reduced and/or otherwise eliminated offset voltage.

FIG. 18depicts graphs1810,1820of example measurements1800associated with the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13. The graphs1810,1820include a first example graph1810and a second example graph1820. The first graph1810includes a first example waveform1812and a second example waveform1814. The first waveform1812is a waveform of a reference voltage, such as VREFofFIGS. 1, 12, 13, and/or14. The second waveform1814is a waveform of a signal voltage, such as VSHUNTofFIG. 1. The second graph1820includes a third example waveform1822, which is a waveform of a gate driver output, which can correspond to an output of the gate driver108ofFIG. 1, such as VGATEofFIG. 1.

The measurements1800characterize the propagation delay associated with the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13by relatively quickly stepping up VSHUNTby approximately 700 millivolts (mV) to 1.1 V, which is below the threshold voltage of the input transistors (e.g., Q11312and Q21314ofFIG. 13) of the comparator110,1202,1300. As depicted by the measurements1800ofFIG. 18, approximately 100 nanoseconds (ns) after VSHUNTcrosses VREF, the output signal VGATEis pulled low. Subtracting the propagation delay of the gate driver (e.g., the gate driver108), this results in an example propagation delay of the comparator110,1202,1300of approximately 50 ns, which affirms the input level shifting functionality of the auto-zeroing input capacitors (e.g., C11204and C21206ofFIG. 12) of the comparator110,1202,1300. Advantageously, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13have reliable switching at an example input common mode of 0.5 V<<VTH, with the depicted propagation delays. A value of the propagation delay is dependent on temperature and/or otherwise correlates with a temperature coefficient of approximately 8000 parts-per-million per Kelvin of the on-resistance of the transistors and resistors in GaN technology.

FIG. 19depicts graphs1910,1920of an example measurement1900associated with the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13. The graphs1910,1920include a first example graph1910and a second example graph1920. The first graph1910includes a first example waveform1912and a second example waveform1914. The first waveform1912is a waveform of a reference voltage, such as VREFofFIGS. 1, 12, 13, and/or14. The second waveform1914is a waveform of a signal voltage, such as VSHUNTofFIG. 1. The second graph1920includes a third example waveform1922, which is a waveform of a gate driver output. The gate driver output can correspond to an output of the gate driver108ofFIG. 1, such as VGATEofFIG. 1.

The offset reducing effect is depicted in the first graph1910. For example, when the relatively slowly rising input voltage VSHUNTis approximately 18 mV higher than VREF, the output signal VGATEis pulled low. Advantageously, the auto-zero loop depicted inFIG. 12can reduce the input referred offset of the comparator110,1202,1300from an example typical value of 200 mV to less than 10%. Advantageously, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13demonstrates reliable switching at an example residual offset of 20 mV as depicted in the example graphs1910,1920ofFIG. 19.

Advantageously, by being implemented in E-mode GaN, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13is/are improvement(s) over conventional comparators. Advantageously, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13is/are improvement(s) because the auto-zero loop ofFIG. 12is implemented around the differential input stages of the comparator to reduce the input referred offset. Advantageously, the different configuration(s), coupling(s), etc., of the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13is/are improvement(s) by being implemented using resistors and N-type devices, and not using any P-type devices.

Advantageously, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13is/are improvement(s) by not requiring additional biasing. Further, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13is/are improvement(s) because the input common mode is not limited to a voltage greater than VTH. Advantageously, the comparator110ofFIG. 1, the comparator1202ofFIG. 12, and/or the comparator1300ofFIG. 13is/are improvement(s) by having a rail-to-rail logic output

Advantageously, by being implemented using resistors and E-mode GaN devices, the bootstrapped switch circuit1500ofFIG. 15is an improvement over conventional bootstrapped switch circuits. Advantageously, the configuration(s), the coupling(s), etc., of the bootstrapped switch circuit1500ofFIG. 15is an improvement by not needing P-type devices. For example, the bootstrapped switch circuit1500ofFIG. 15is an improvement by being configured in such an arrangement to put the input stages of the comparator110,1202,1300in unity-gain configuration for auto-zeroing without P-type devices. Further, by effectuating the pull down of the gate of the switch transistor being implemented with only one transistor Q61512in the bootstrapped switch circuit1500ofFIG. 15, the bootstrapped switch circuit1500ofFIG. 15is an improvement because series connection of multiple transistors may not be required.

A flowchart representative of an example process that may be carried out while utilizing example hardware logic, example machine readable instructions (e.g., hardware readable instructions), example hardware implemented state machines, and/or any combination thereof for implementing the gate driver108ofFIG. 1, the gate driver202ofFIG. 2, the comparator110ofFIG. 1, the comparator circuit1200ofFIG. 12, and/or the comparator circuit1300ofFIG. 13is shown inFIG. 20. The example machine readable instructions may be one or more executable programs or portion(s) of an executable program for execution by programmable processor(s), programmable controller(s), GPU(s), DSP(s), ASIC(s), PLD(s), and/or FPLD(s). The program may be embodied in software stored on a non-transitory computer readable storage medium such as a non-volatile memory, volatile memory, etc., but the entire program and/or parts thereof could alternatively be executed by any other device (e.g., programmable device) and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowchart illustrated inFIG. 20, many other methods of implementing the gate driver108ofFIG. 1, the gate driver202ofFIG. 2, the comparator110ofFIG. 1, the comparator circuit1200ofFIG. 12, and/or the comparator circuit1300ofFIG. 13may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware.

FIG. 20is a flowchart representative of an example process2000that may be carried out while utilizing machine readable instructions that can be executed and/or hardware configured to implement the gate driver108ofFIG. 1, the gate driver202ofFIG. 2, the comparator110ofFIG. 1, the comparator circuit1200ofFIG. 12, and/or the comparator circuit1300ofFIG. 13to control a power transistor, such as QS148ofFIG. 1. The example process2000ofFIG. 20begins at block2002, at which the gate driver108and/or the gate driver202turn on a power transistor, such as QS148ofFIG. 1, to generate a signal voltage, such as VSHUNTofFIG. 1.

At block2004, the comparator110,1200,1300compares the signal voltage to a reference voltage at input transistors in a first differential stage to generate first amplified signals. For example, the input transistors Q11312, Q21314of the first differential stage1302of the comparator1300ofFIG. 13can compare VSIGto VREFto generate PRE_P and PRE_N.

At block2006, the comparator110,1200,1300generates second amplified signals in a second differential stage. For example, input transistors of the second differential stage1304, Q31344and Q41346, of the comparator1300ofFIG. 13can compare PRE_N and PRE_P to generate DIFF_P and DIFF_N.

At block2008, the comparator110,1200,1300invokes a cross-coupled latch to generate a voltage based on the second amplified signals. For example, the second differential stage1304can invoke the cross-coupled latch1306of the comparator1300ofFIG. 13to generate VGS,10.

At block2010, the comparator110,1200,1300generates a comparator output based on the generated voltage. For example, the output stage1308of the comparator1300ofFIG. 13can generate an output signal at the output terminal1372, which can correspond to a logic low signal, a logic high signal, etc., based on VGS,10.

At block2012, the comparator110,1200,1300determines whether the output signal is indicative of drain current of the power transistor satisfying a threshold. For example, in response to VGS,10being greater than VTHof Q101362, the comparator output at the output terminal1372can be VDD1332. In such examples, VDD1332at the output terminal1372can be representative of VSHUNT, which is generated based on the drain current of QS148ofFIG. 1, being greater than VREF.

If, at block2012, the comparator110,1200,1300determines that the output signal is not indicative of drain current of the power transistor satisfying a threshold, control returns to block2004to compare the signal voltage to the reference voltage at the input transistors in the first differential stage to generate the first amplified signals. If, at block2012, the comparator110,1200,1300determines that the output signal is indicative of drain current of the power transistor satisfying a threshold, then, at block2014, the gate driver108and/or the gate driver202turn off the power transistor to execute an auto-zero operation to reduce comparator offset. For example, in response to the gate driver108turning off QS148, the first control signal1220ofFIG. 12can be de-asserted and the second control signal1222ofFIG. 12can be asserted to configure the differential stages of the comparator circuit1200in unity-gain configuration.

At block2016, the comparator110,1200,1300determines whether to continue controlling the power transistor. If, at block2016, the gate driver108and/or the gate driver202determine to continue controlling the power transistor, control returns to block2002to turn on the power transistor to generate a signal voltage, otherwise the example process2000ofFIG. 20concludes.

From the foregoing, it will be appreciated that example gate driver circuits, auto-zero comparators, and related methods have been disclosed that improve operation of power delivery systems and other types of electrical systems. The example gate driver circuits and related methods disclosed herein do not need an additional voltage terminal greater than VDD to effectuate gate driver operations. The example gate driver circuits and related methods use fewer bootstrap stages and use additional pull-up transistors, which lead to improved efficiency of switching behavior, as the bootstrapped signal drives a portion of an output stage associated with a power transistor rather than the full output stage.

The example auto-zero comparators and related methods disclosed herein are implemented in GaN using resistors, capacitors, and N-type enhancement mode devices, with no depletion mode devices used. The example auto-zero comparators and related methods disclosed herein support rail-to-rail DC input common mode and, in some examples, up to capacitor breakdown voltage. The example auto-zero comparators and related methods disclosed herein reduce offset caused by immature matching.

Example methods, apparatus, systems, and articles of manufacture for gate driver circuits and/or auto-zero comparators are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes an integrated circuit comprising a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

Example 2 includes the integrated circuit of example 1, wherein the transistor is a power transistor, the gate terminal is a power transistor gate terminal, the current terminal is a power transistor current terminal, and the GaN gate driver includes a first transistor comprising a first gate terminal and a first current terminal, a second transistor comprising a second gate terminal, a second current terminal, and a third current terminal, a third transistor comprising a third gate terminal, a fourth current terminal, and a fifth current terminal, a first rail-to-rail driver comprising a first input, a second input, a first output, a first enable output, and a second enable output, the first enable output coupled to the second gate terminal, the second enable output coupled to the third gate terminal, a second rail-to-rail driver comprising a third input, a fourth input, a second output, and a third enable output, the first input coupled to the first output, the second output coupled to the second input, the third enable output coupled to the first gate terminal, and a latch comprising a first latch output and a second latch output, the first latch output coupled to the first input, the second latch output coupled to the fourth input.

Example 3 includes the integrated circuit of example 1, wherein the transistor is a power transistor, the gate terminal is a power transistor gate terminal, the current terminal is a power transistor current terminal, and the GaN gate driver includes a NAND logic gate comprising a NAND output, a first inverter comprising a first inverter input and a first inverter output, the first inverter input coupled to the NAND output, a first transistor comprising a first gate terminal and a first current terminal, the first gate terminal coupled to the first inverter output, a second transistor comprising a second gate terminal and a second current terminal, the second gate terminal coupled to the NAND output, the second current terminal coupled to the first current terminal, a third transistor comprising a third gate terminal and a third current terminal, the third gate terminal coupled to the NAND output, a second inverter comprising a second inverter input and a second inverter output, a fourth transistor comprising a fourth gate terminal and a fourth current terminal, the fourth gate terminal coupled to the second inverter output, the fourth current terminal coupled to the third current terminal, a fifth transistor comprising a fifth gate terminal and a fifth current terminal, the fifth gate terminal coupled to third current terminal and the fourth current terminal, a sixth transistor comprising a sixth gate terminal and a sixth current terminal, the sixth gate terminal coupled to the NAND output, the sixth current terminal coupled to the fifth current terminal, and a seventh transistor comprising a seventh current terminal coupled to the fourth transistor.

Example 4 includes the integrated circuit of example 3, wherein the first through seventh transistors are N-type enhancement mode GaN transistors.

Example 5 includes the integrated circuit of example 1, wherein the transistor is a power transistor, and the enhancement mode GaN comparator has a first comparator input, a second comparator input, a comparator output, a first differential output, a second differential output, a first bootstrapped switch circuit coupled to the first differential output, and a second bootstrapped switch circuit coupled to the second differential output.

Example 6 includes the integrated circuit of example 5, wherein the transistor is a power transistor, and at least one of the first bootstrapped switch circuit or the second bootstrapped switch circuit includes a charge pump including a first transistor, a second transistor coupled to the first transistor, a first capacitor coupled to the first transistor and the second transistor, a second capacitor coupled to the first capacitor, the first transistor, and the second transistor, a first inverter coupled to the first capacitor, and a second inverter coupled to the first inverter, the first capacitor, and the second capacitor, and a bootstrapping circuit coupled to the charge pump.

Example 7 includes the integrated circuit of example 5, wherein the transistor is a power transistor, and at least one of the first bootstrapped switch circuit or the second bootstrapped switch circuit includes a charge pump, and a bootstrapping circuit coupled to the charge pump, the bootstrapping circuit including a first transistor coupled to the charge pump, a first capacitor coupled to the first transistor, a second transistor coupled to the charge pump and the first capacitor, a resistor coupled to the charge pump, a third transistor coupled to the resistor and the second transistor, a fourth transistor coupled to the third transistor and the resistor, a fifth transistor coupled to the fourth transistor, the second transistor, and the charge pump, a sixth transistor coupled to the fourth transistor and the fifth transistor, and a seventh transistor coupled to the fourth transistor, the fifth transistor, the sixth transistor, and at least one of the first comparator input or the second comparator input.

Example 8 includes the integrated circuit of example 1, wherein the transistor is a power transistor, and the enhancement mode GaN comparator includes one or more differential stages, a cross-coupled latch, and an output stage, a first differential stage of the one or more differential stages including a first resistor and a second resistor, a first transistor coupled to the first resistor, a second transistor coupled to the second resistor and the first transistor, a first common mode loop including a first set of common mode transistors coupled to the first resistor and the first transistor, and a second common mode loop including a second set of common mode transistors coupled to the second resistor and the second transistor.

Example 9 includes the integrated circuit of example 1, wherein the transistor is a power transistor, and the enhancement mode GaN comparator includes a first differential stage, a second differential stage, a cross-coupled latch, and an output stage, the second differential stage including a first resistor and a second resistor, a first transistor coupled to the first resistor and the first differential stage, a second transistor coupled to the second resistor and the second differential stage, a third transistor coupled to the first transistor, the second transistor, and the cross-coupled latch, and a fourth transistor coupled to the first transistor, the second transistor, the third transistor, and the cross-coupled latch.

Example 10 includes the integrated circuit of example 1, wherein the transistor is a power transistor, and the enhancement mode GaN comparator includes one or more differential stages, a cross-coupled latch, and an output stage, the cross-coupled latch including a first transistor coupled to a first differential stage of the one or more differential stages, a second transistor coupled to the first transistor, a third transistor coupled to the first transistor and the second transistor, and a fourth transistor coupled to the third transistor, the first differential stage, and the output stage.

Example 11 includes a gate driver comprising a first switch comprising a first gate terminal and a first current terminal, a second switch comprising a second gate terminal, a second current terminal, and a third current terminal, a third switch comprising a third gate terminal, a fourth current terminal, and a fifth current terminal, at least one of the first switch, the second switch, or the third switch is an enhancement mode gallium nitride (GaN) transistor, a first pre-driver circuit comprising a first input, a second input, a first output, a first enable output, and a second enable output, the first enable output coupled to the second gate terminal, the second enable output coupled to the third gate terminal, and a second pre-driver circuit comprising a third input, a fourth input, a second output, and a third enable output, the first input coupled to the first output, the second output coupled to the second input, the third enable output coupled to the first gate terminal.

Example 12 includes the gate driver of example 11, wherein at least one of the first pre-driver circuit or the second pre-driver circuit includes a NAND logic gate comprising a NAND output, a first inverter comprising a first inverter input and a first inverter output, the first inverter input coupled to the NAND output, a first transistor comprising a first gate terminal and a first current terminal, the first gate terminal coupled to the first inverter output, a second transistor comprising a second gate terminal and a second current terminal, the second gate terminal coupled to the NAND output, the second current terminal coupled to the first current terminal, and a third transistor comprising a third gate terminal and a third current terminal, the third gate terminal coupled to the NAND output, at least one of the first transistor, the second transistor, or the third transistor is an enhancement mode GaN transistor.

Example 13 includes the gate driver of example 12, wherein the at least one of the first pre-driver circuit or the second pre-driver circuit includes a second inverter comprising a second inverter input and a second inverter output, a fourth transistor comprising a fourth gate terminal and a fourth current terminal, the fourth gate terminal coupled to the second inverter output, the fourth current terminal coupled to the third current terminal, a fifth transistor comprising a fifth gate terminal and a fifth current terminal, the fifth gate terminal coupled to third current terminal and the fourth current terminal, a sixth transistor comprising a sixth gate terminal and a sixth current terminal, the sixth gate terminal coupled to the NAND output, the sixth current terminal coupled to the fifth current terminal, and a seventh transistor comprising a seventh current terminal coupled to the fourth transistor.

Example 14 includes the gate driver of example 13, wherein the first through seventh transistors are N-type enhancement mode GaN transistors.

Example 15 includes a comparator circuit comprising a comparator comprising a first comparator input, a second comparator input, a first differential output, a second differential output, and a comparator output, a first capacitor coupled to the first comparator input, a second capacitor coupled to the second comparator input, a first bootstrapped switch circuit coupled to the first differential output, the first capacitor, and the first comparator input, a second bootstrapped switch circuit coupled to the second differential output, the second capacitor, and the second comparator input, a first enhancement mode gallium nitride (GaN) transistor coupled to the first capacitor, and a second enhancement mode GaN transistor coupled to the first enhancement mode GaN transistor, the first capacitor, and the second capacitor.

Example 16 includes the comparator circuit of example 15, wherein at least one of the first bootstrapped switch circuit or the second bootstrapped switch circuit includes a charge pump including a first transistor, a second transistor coupled to the first transistor, at least one of the first transistor or the second transistor is an enhancement mode GaN transistor, a third capacitor coupled to the first transistor and the second transistor, a fourth capacitor coupled to the third capacitor, the first transistor, and the second transistor, a first inverter coupled to the third capacitor, and a second inverter coupled to the first inverter, the third capacitor, and the fourth capacitor, and a bootstrapping circuit coupled to the charge pump.

Example 17 includes the comparator circuit of example 15, wherein at least one of the first bootstrapped switch circuit or the second bootstrapped switch circuit includes a charge pump, and a bootstrapping circuit coupled to the charge pump, the bootstrapping circuit including a first transistor coupled to the charge pump, a third capacitor coupled to the first transistor, a second transistor coupled to the charge pump and the third capacitor, a resistor coupled to the charge pump, a third transistor coupled to the resistor and the second transistor, a fourth transistor coupled to the third transistor and the resistor, a fifth transistor coupled to the fourth transistor, the second transistor, and the charge pump, a sixth transistor coupled to the fourth transistor and the fifth transistor, and a seventh transistor coupled to the fourth transistor, the fifth transistor, the sixth transistor, and at least one of the first comparator input or the second comparator input, the first through seventh transistors are enhancement mode GaN transistors.

Example 18 includes the comparator circuit of example 15, wherein the comparator includes a differential amplifier including one or more differential stages, a cross-coupled latch, and an output stage, a first differential stage of the one or more differential stages including a first resistor and a second resistor, a first transistor coupled to the first resistor, a second transistor coupled to the second resistor and the first transistor, a first common mode loop including a first set of common mode transistors coupled to the first resistor and the first transistor, and a second common mode loop including a second set of common mode transistors coupled to the second resistor and the second transistor, at least one of the first transistor, the second transistor, one or more of the first set of the common mode transistors, or one or more of the second set of the common mode transistors is an enhancement mode GaN transistor.

Example 19 includes the comparator circuit of example 15, wherein the comparator includes a differential amplifier including one or more differential stages, a cross-coupled latch, and an output stage, a first differential stage of the one or more differential stages including a first resistor and a second resistor, a first transistor coupled to the first resistor, a second transistor coupled to the second resistor, a third transistor coupled to the first transistor, the second transistor, and the cross-coupled latch, and a fourth transistor coupled to the first transistor, the second transistor, the third transistor, and the cross-coupled latch, at least one of the first transistor, the second transistor, the third transistor, or the fourth transistor is an enhancement mode GaN transistor.

Example 20 includes the comparator circuit of example 15, wherein the comparator includes a differential amplifier including one or more differential stages, a cross-coupled latch, and an output stage, the cross-coupled latch including a first transistor coupled to the differential amplifier, a second transistor coupled to the first transistor, a third transistor coupled to the first transistor and the second transistor, and a fourth transistor coupled to the third transistor, the differential amplifier, and the output stage, at least one of the first transistor, the second transistor, the third transistor, or the fourth transistor is an enhancement mode GaN transistor.