HYBRID INTEGRATION OF BACK-END-OF-LINE LAYERS FOR DISAGGREGATED TECHNOLOGIES

Integrated circuit (IC) dies, microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, an IC die may include a substrate, a front-end-of-line (FEOL) layer over the substrate, where the FEOL layer includes a plurality of transistors, a first back-end-of-line (BEOL) layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects.

BACKGROUND

A front-end-of-line (FEOL) layer of an integrated circuit (IC) die generally refers to a layer in which active or passive circuitry based on highly crystalline semiconductor materials are formed, e.g., front-end transistors of logic devices. A back-end-of-line (BEOL) layer of such a die refers to a layer above the FEOL layer, in which either further active or passive circuitry (e.g., back-end transistors) and/or conductive pathways for providing connectivity for the active or passive circuitry are formed. A die typically includes multiple BEOL layers where conductive pathways such as conductive traces and/or conductive vias are included. In general, FEOL and BEOL refer to different layers, or different fabrication processes used to manufacture different portions of IC devices in context of complementary metal oxide semiconductor (CMOS) processes (e.g., logic devices in the FEOL layer, peripheral circuitry and/or interconnects in the BEOL layer). A far BEOL (FBEOL) layer of an IC die is a layer above the one or more BEOL layers, the FBEOL layer typically including a top metal layer, a passivation layer, and conductive contacts for coupling the die to other components such as a package substrate, an interposer, a circuit board, or another die.

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor dies. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a die, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each IC die and each IC package that includes one or more dies becomes increasingly significant. In particular, heterogenous/disaggregated packaging architectures aim to optimize performance by disaggregating single monolithic die into multiple dies (also referred to as “chiplets” or “tiles”) such as compute, graphics, system-on-chip (SoC), etc. These different dies could be manufactured by different foundries and/or according to different manufacturing technologies for better performance, optimized yield, cost, or accelerated ramp, and later assembled into a single package. However, dies manufactured by different foundries and/or according to different manufacturing technologies may differ in, e.g., metallurgy, topography, and passivation surfaces, which, in turn, result in different assembly design rules (DRs). Attaching such dies onto a single package substrate, interposer, or a mold complex presents significant challenges due to bumping and assembly DR differences, bonding yield, passivation mismatch, chip-to-package interactions, etc. These challenges are generally present for all disaggregated technologies, and if FBEOL processes for two dies are radically different, the challenges are exacerbated even further.

DETAILED DESCRIPTION

Hybrid integration of BEOL layers for disaggregated technologies and associated IC dies, microelectronic assemblies, and related devices and methods, are disclosed herein. In particular, such hybrid integration is applicable to scenarios where an IC die with an FEOL layer and one or more BEOL layers, including FBEOL layers, manufactured by one foundry, is processed further by another foundry to add additional BEOL layers to make the die compatible with dies manufactured by that foundry or further foundries. In some embodiments, a resulting IC die may include an FEOL layer that includes a plurality of transistors, a first BEOL layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects. Various ones of the embodiments disclosed herein may help achieve reliable inclusion, in a single package, of multiple IC dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches. The microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).

For convenience, the phrase “FIG.18” may be used to refer to the collection of drawings ofFIGS.18A-18J. To not clutter the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be labeled with a reference sign. The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and may not reflect real-life process limitations which may cause various features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC dies manufactured using hybrid integration of BEOL layers for disaggregated technologies as described herein.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. When used to describe a location of an element, the phrase “between X and Y” represents a region that is spatially between element X and element Y. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an insulating material” may include one or more insulating materials, while a “metal” may include one or more metals.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous, as are a “die” and an “IC die.” As used herein, the term “insulating” means “electrically insulating,” unless otherwise specified. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, if used, the terms “oxide,” “carbide,” “nitride,” “sulfide,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, sulfur, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. In another example, as used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art.

FIG.1is a side, cross-sectional view of a microelectronic assembly100, in accordance with various embodiments. A number of elements are illustrated inFIG.1as included in the microelectronic assembly100, but a number of these elements may not be present in a microelectronic assembly100. For example, in various embodiments, the heat spreader131, the thermal interface material129, the mold material127, the die114-3, the die114-4, the second-level interconnects137, and/or the circuit board133may not be included. Further,FIG.1illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies100disclosed herein. Examples of such elements include the heat spreader131, the thermal interface material129, the mold material127, the second-level interconnects137, and/or the circuit board133. Many of the elements of the microelectronic assembly100ofFIG.1are included in other ones of the accompanying figures; the discussion of these elements is not repeated when discussing these figures, and any of these elements may take any of the forms disclosed herein. In some embodiments, individual ones of the microelectronic assemblies100disclosed herein may serve as a system-in-package (SiP) in which multiple dies114having different functionality are included. In such embodiments, the microelectronic assembly100may be referred to as an SiP. Any of the dies114may be fabricated using hybrid integration of BEOL layers for disaggregated technologies as described herein.

The microelectronic assembly100may include a package substrate102coupled to a die114-1by die-to-package substrate (DTPS) interconnects150-1. In particular, the top surface of the package substrate102may include a set of conductive contacts146, and the bottom surface of the die114-1may include a set of conductive contacts122; the conductive contacts122at the bottom surface of the die114-1may be electrically and mechanically coupled to the conductive contacts146at the top surface of the package substrate102by the DTPS interconnects150-1. In the embodiment ofFIG.1, the top surface of the package substrate102includes a recess108in which the die114-1is at least partially disposed; the conductive contacts146to which the die114-1is coupled are located at the bottom of the recess108. In other embodiments, the die114-1may not be disposed in a recess (e.g., as discussed below with reference toFIGS.9-11). Any of the conductive contacts disclosed herein (e.g., the conductive contacts122,124,146,140, and/or135) may include bond pads, posts, or any other suitable conductive contact, for example.

The package substrate102may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate102may be a dielectric material, such as an organic dielectric material, a fire retardant grade4material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate102is formed using standard printed circuit board (PCB) processes, the package substrate102may include FR-4, and the conductive pathways in the package substrate102may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate102may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable.

In some embodiments, one or more of the conductive pathways in the package substrate102may extend between a conductive contact146at the top surface of the package substrate102and a conductive contact140at the bottom surface of the package substrate102. In some embodiments, one or more of the conductive pathways in the package substrate102may extend between a conductive contact146at the bottom of the recess108and a conductive contact140at the bottom surface of the package substrate102. In some embodiments, one or more of the conductive pathways in the package substrate102may extend between different conductive contacts146at the top surface of the package substrate102(e.g., between a conductive contact146at the bottom of the recess108and a different conductive contact146at the top surface of the package substrate102). In some embodiments, one or more of the conductive pathways in the package substrate102may extend between different conductive contacts140at the bottom surface of the package substrate102.

The dies114disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die114may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die114may include a semiconductor material, such as silicon, germanium, or a Ill-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die114may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die114in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die114). Example structures that may be included in the dies114disclosed herein are discussed below with reference toFIG.20. The conductive pathways in the dies114may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable.

In some embodiments, the die114-1may include conductive pathways to route power, ground, and/or signals to/from some of the other dies114included in the microelectronic assembly100. For example, the die114-1may include through-substrate vias (TSVs, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide) or other conductive pathways through which power, ground, and/or signals may be transmitted between the package substrate102and one or more dies114“on top” of the die114-1(e.g., in the embodiment ofFIG.1, the die114-2and/or the die114-3). In some embodiments, the die114-1may include conductive pathways to route power, ground, and/or signals between different ones of the dies114“on top” of the die114-1(e.g., in the embodiment ofFIG.1, the die114-2and the die114-3). In some embodiments, the die114-1may be the source and/or destination of signals communicated between the die114-1and other dies114included in the microelectronic assembly100.

In some embodiments, the die114-1may not route power and/or ground to the die114-2; instead, the die114-2may couple directly to power and/or ground lines in the package substrate102. By allowing the die114-2to couple directly to power and/or ground lines in the package substrate102, such power and/or ground lines need not be routed through the die114-1, allowing the die114-1to be made smaller or to include more active circuitry or signal pathways.

In some embodiments, the die114-1may only include conductive pathways, and may not contain active or passive circuitry. In other embodiments, the die114-1may include active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others). In some embodiments, the die114-1may include one or more device layers including transistors (e.g., as discussed below with reference toFIG.20. When the die114-1includes active circuitry, power and/or ground signals may be routed through the package substrate102and to the die114-1through the conductive contacts122on the bottom surface of the die114-1.

AlthoughFIG.1illustrates a specific number and arrangement of conductive pathways in the package of102and/or one or more of the dies114, these are simply illustrative, and any suitable number and arrangement may be used. The conductive pathways disclosed herein (e.g., conductive traces and/or conductive vias) may be formed of any appropriate conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, for example.

In some embodiments, the package substrate102may be a lower density medium and the die114-1may be a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive lines and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process).

The microelectronic assembly100ofFIG.1may also include a die114-2. The die114-2may be electrically and mechanically coupled to the package substrate102by DTPS interconnects150-2, and may be electrically and mechanically coupled to the die114-1by die-to-die (DTD) interconnects130-1. In particular, the top surface of the package substrate102may include a set of conductive contacts146, and the bottom surface of the die114-2may include a set of conductive contacts122; the conductive contacts122at the bottom surface of the die114-1may be electrically and mechanically coupled to the conductive contacts146at the top surface of the package substrate102by the DTPS interconnects150-2. Further, the top surface of the die114-1may include a set of conductive contacts124, and the bottom surface of the die114-2may include a set of conductive contacts124; the conductive contacts124at the bottom surface of the die114-2may be electrically and mechanically coupled to some of the conductive contacts124at the top surface of the die114-1by the DTD interconnects130-1.FIG.2is a bottom view of the die114-2of the microelectronic assembly100ofFIG.1, showing the “coarser” conductive contacts122and the “finer” conductive contacts124. The die114-2of the microelectronic assembly100may thus be a single-sided die (in the sense that the die114-2only has conductive contacts122/124on a single surface), and may be a mixed-pitch die (in the sense that the die114-2has sets of conductive contacts122/124with different pitch). AlthoughFIG.2illustrates the conductive contacts122and the conductive contacts124as each being arranged in a rectangular array, this need not be the case, and the conductive contacts122and124may be arranged in any suitable pattern (e.g., triangular, hexagonal, rectangular, different arrangements between the conductive contacts122and124, etc.). A die114that has DTPS interconnects150and DTD interconnects130at the same surface may be referred to as a mixed-pitch die114; more generally, a die114that has interconnects130of different pitches at a same surface may be referred to as a mixed-pitch die114.

The die114-2may extend over the die114-1by an overlap distance191. In some embodiments, the overlap distance191may be between 0.5 millimeters and 5 millimeters (e.g., between 0.75 millimeters and 2 millimeters, or approximately 1 millimeter).

The microelectronic assembly100ofFIG.1may also include a die114-3. The die114-3may be electrically and mechanically coupled to the die114-1by DTD interconnects130-2. In particular, the bottom surface of the die114-3may include a set of conductive contacts124that are electrically and mechanically coupled to some of the conductive contacts124at the top surface of the die114-1by the DTD interconnects130-2. In the embodiment ofFIG.1, the die114-3may be a single-sided, single-pitch die; in other embodiments, the die114-3may be a double-sided (or “multi-level,” or “omni-directional”) die, and additional components may be disposed on the top surface of the die114-3.

As discussed above, in the embodiment ofFIG.1, the die114-1may provide high density interconnect routing in a localized area of the microelectronic assembly100. In some embodiments, the presence of the die114-1may support direct chip attach of fine-pitch semiconductor dies (e.g., the dies114-2and114-3) that cannot be attached entirely directly to the package substrate102. In particular, as discussed above, the die114-1may support trace widths and spacings that are not achievable in the package substrate102. The proliferation of wearable and mobile electronics, as well as Internet of Things (IoT) applications, are driving reductions in the size of electronic systems, but limitations of the PCB manufacturing process and the mechanical consequences of thermal expansion during use have meant that chips having fine interconnect pitch cannot be directly mounted to a PCB. Various embodiments of the microelectronic assemblies100disclosed herein may be capable of supporting chips with high density interconnects and chips with low-density interconnects without sacrificing performance or manufacturability.

The microelectronic assembly100ofFIG.1may also include a die114-4. The die114-4may be electrically and mechanically coupled to the package substrate102by DTPS interconnects150-3. In particular, the bottom surface of the die114-4may include a set of conductive contacts122that are electrically and mechanically coupled to some of the conductive contacts146at the top surface of the package substrate102by the DTPS interconnects150-3. In the embodiment ofFIG.1, the die114-4may be a single-sided, single-pitch die; in other embodiments, the die114-4may be a double-sided die, and additional components may be disposed on the top surface of the die114-4. Additional passive components, such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top surface or the bottom surface of the package substrate102, or embedded in the package substrate102.

The microelectronic assembly100ofFIG.1may also include a circuit board133. The package substrate102may be coupled to the circuit board133by second-level interconnects137at the bottom surface of the package substrate102. In particular, the package substrate102may include conductive contacts140at its bottom surface, and the circuit board133may include conductive contacts135at its top surface; the second-level interconnects137may electrically and mechanically couple the conductive contacts135and the conductive contacts140. The second-level interconnects137illustrated inFIG.1are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects137may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The circuit board133may be a motherboard, for example, and may have other components attached to it (not shown). The circuit board133may include conductive pathways and other conductive contacts (not shown) for routing power, ground, and signals through the circuit board133, as known in the art. In some embodiments, the second-level interconnects137may not couple the package substrate102to a circuit board133, but may instead couple the package substrate102to another IC package, an interposer, or any other suitable component.

The microelectronic assembly100ofFIG.1may also include a mold material127. The mold material127may extend around one or more of the dies114on the package substrate102. In some embodiments, the mold material127may extend above one or more of the dies114on the package substrate102. In some embodiments, the mold material127may extend between one or more of the dies114and the package substrate102around the associated DTPS interconnects150; in such embodiments, the mold material127may serve as an underfill material. In some embodiments, the mold material127may extend between different ones of the dies114around the associated DTD interconnects130; in such embodiments, the mold material127may serve as an underfill material. The mold material127may include multiple different mold materials (e.g., an underfill material, and a different overmold material). The mold material127may be an insulating material, such as an appropriate epoxy material. In some embodiments, the mold material127may include an underfill material that is an epoxy flux that assists with soldering the dies114-1/114-2to the package substrate102when forming the DTPS interconnects150-1and150-2, and then polymerizes and encapsulates the DTPS interconnects150-1and150-2. The mold material127may be selected to have a coefficient of thermal expansion (CTE) that may mitigate or minimize the stress between the dies114and the package substrate102arising from uneven thermal expansion in the microelectronic assembly100. In some embodiments, the CTE of the mold material127may have a value that is intermediate to the CTE of the package substrate102(e.g., the CTE of the dielectric material of the package substrate102) and a CTE of the dies114.

The microelectronic assembly100ofFIG.1may also include a thermal interface material (TIM)129. The TIM129may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM129may be a thermal interface material paste or a thermally conductive epoxy (which may be a fluid when applied and may harden upon curing, as known in the art). The TIM129may provide a path for heat generated by the dies114to readily flow to the heat spreader131, where it may be spread and/or dissipated. Some embodiments of the microelectronic assembly100ofFIG.1may include a sputtered back side metallization (not shown) across the mold material127and the dies114; the TIM129(e.g., a solder TIM) may be disposed on this back side metallization.

The microelectronic assembly100ofFIG.1may also include a heat spreader131. The heat spreader131may be used to move heat away from the dies114(e.g., so that the heat may be more readily dissipated by a heat sink or other thermal management device). The heat spreader131may include any suitable thermally conductive material (e.g., metal, appropriate ceramics, etc.), and may include any suitable features (e.g., fins). In some embodiments, the heat spreader131may be an integrated heat spreader.

The DTPS interconnects150disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects150may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the DTPS interconnects150). DTPS interconnects150that include solder may include any appropriate solder material, such as lead/tin, tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, tin/nickel/copper, tin/bismuth/copper, tin/indium/copper, tin/zinc/indium/bismuth, or other alloys. In some embodiments, a set of DTPS interconnects150may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In some embodiments, an anisotropic conductive material may include microscopic conductive particles embedded in a binder or a thermoset adhesive film (e.g., a thermoset biphenyl-type epoxy resin, or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and/or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper that is in turn coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is uncompressed, there may be no conductive pathway from one side of the material to the other. However, when the anisotropic conductive material is adequately compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the region of compression may contact each other so as to form a conductive pathway from one side of the film to the other in the region of compression.

The DTD interconnects130disclosed herein may take any suitable form. The DTD interconnects130may have a finer pitch than the DTPS interconnects150in a microelectronic assembly. In some embodiments, the dies114on either side of a set of DTD interconnects130may be unpackaged dies, and/or the DTD interconnects130may include small conductive bumps or pillars (e.g., copper bumps or pillars) attached to the conductive contacts124by solder. The DTD interconnects130may have too fine a pitch to couple to the package substrate102directly (e.g., to fine to serve as DTPS interconnects150). In some embodiments, a set of DTD interconnects130may include solder. DTD interconnects130that include solder may include any appropriate solder material, such as any of the materials discussed above. In some embodiments, a set of DTD interconnects130may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects130may be used as data transfer lanes, while the DTPS interconnects150may be used for power and ground lines, among others.

In some embodiments, some or all of the DTD interconnects130in a microelectronic assembly100may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the conductive contacts124on either side of the DTD interconnect130may be bonded together (e.g., under elevated pressure and/or temperature) without the use of intervening solder or an anisotropic conductive material. In some embodiments, a thin cap of solder may be used in a metal-to-metal interconnect to accommodate planarity, and this solder may become an intermetallic compound during processing. In some metal-to-metal interconnects that utilize hybrid bonding, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, or an organic layer) may be present between the metals bonded together (e.g., between copper pads or posts that provide the associated conductive contacts124). In some embodiments, one side of a DTD interconnect130may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in a dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxides are conductive (e.g., silver). In some embodiments, a metal-to-metal interconnect may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be capable of reliably conducting a higher current than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be constrained to mitigate mechanical failure.

In some embodiments, some or all of the DTD interconnects130in a microelectronic assembly100may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the DTPS interconnects150. For example, when the DTD interconnects130in a microelectronic assembly100are formed before the DTPS interconnects150are formed (e.g., as discussed below with reference toFIGS.17A-17F), solder-based DTD interconnects130may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the DTPS interconnects150may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium.

In the microelectronic assemblies100disclosed herein, some or all of the DTPS interconnects150may have a larger pitch than some or all of the DTD interconnects130. DTD interconnects130may have a smaller pitch than DTPS interconnects150due to the greater similarity of materials in the different dies114on either side of a set of DTD interconnects130than between the die114and the package substrate102on either side of a set of DTPS interconnects150. In particular, the differences in the material composition of a die114and a package substrate102may result in differential expansion and contraction of the die114and the package substrate102due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTPS interconnects150may be formed larger and farther apart than DTD interconnects130, which may experience less thermal stress due to the greater material similarity of the pair of dies114on either side of the DTD interconnects. In some embodiments, the DTPS interconnects150disclosed herein may have a pitch between 80 microns and 300 microns, while the DTD interconnects130disclosed herein may have a pitch between 7 microns and 100 microns.

The elements of the microelectronic assembly100may have any suitable dimensions. Only a subset of the accompanying figures are labeled with reference numerals representing dimensions, but this is simply for clarity of illustration, and any of the microelectronic assemblies100disclosed herein may have components having the dimensions discussed herein. For example, in some embodiments, the thickness164of the package substrate102may be between 0.1 millimeters and 1.4 millimeters (e.g., between 0.1 millimeters and 0.35 millimeters, between 0.25 millimeters and 0.8 millimeters, or approximately 1 millimeter). In some embodiments, the recess108may have a depth175between 10 microns and 200 microns (e.g., between 10 microns and 30 microns, between 30 microns and 100 microns, between 60 microns and 80 microns, or approximately 75 microns). In some embodiments, the depth175may be equal to a certain number of layers of the dielectric material in the package substrate102. For example, the depth175may be approximately equal to between one and five layers of the dielectric material in the package substrate102(e.g., two or three layers of the dielectric material). In some embodiments, the depth175may be equal to the thickness of a solder resist material (not shown) on the top surface of the package substrate102.

In some embodiments, the distance179between the bottom surface of the die114-1and the proximate top surface of the package substrate102(at the bottom of the recess108) may be less than the distance177between the bottom surface of the die114-2and the proximate top surface of the package substrate102. In some embodiments, the distance179may be approximately the same as the distance177. In some embodiments, the distance177between the bottom surface of the die114-2and the proximate top surface of the package substrate102may be greater than the distance193between the bottom surface of the die114-2and the proximate top surface of the die114-1. In other embodiments, the distance177may be less than or equal to the distance193.

In some embodiments, the top surface of the die114-1may extend higher than the top surface of the package substrate102, as illustrated inFIG.1. In other embodiments, the top surface of the die114-1may be substantially coplanar with the top surface of the package substrate102, or may be recessed below the top surface of the package substrate102.FIG.3illustrates an example of the former embodiment. Although various ones of the figures illustrate microelectronic assemblies100having a single recess108in the package substrate102, the thickness of102may include multiple recesses108(e.g., having the same or different dimensions, and each having a die114disposed therein), or no recesses108. Examples of the former embodiments are discussed below with reference toFIGS.7-8, and examples of the latter embodiments are discussed below with reference toFIGS.9-11. In some embodiments, a recess108may be located at the bottom surface of the package substrate102(e.g., proximate to the conductive contacts140), instead of or in addition to a recess108at the top surface of the package substrate102.

In the embodiment ofFIG.1, a single die114-2is illustrated as “spanning” the package substrate102and the die114-1. In some embodiments of the microelectronic assemblies100disclosed herein, multiple dies114may span the package substrate102and another die114. For example,FIG.4illustrates an embodiment in which two dies114-2each have conductive contacts122and conductive contacts124disposed at the bottom surfaces; the conductive contacts122of the dies114-2are coupled to conductive contacts146at the top surface of the package substrate102via DTPS interconnects150-2, and the conductive contacts124of the dies114-2are coupled to conductive contacts124at the top surface of the die114via DTD interconnects130. In some embodiments, power and/or ground signals may be provided directly to the dies114of the microelectronic assembly100ofFIG.4through the package substrate102, and the die114-1may, among other things, route signals between the dies114-2.

In some embodiments, the die114-1may be arranged as a bridge between multiple other dies114, and may also have additional dies114disposed thereon. For example,FIG.5illustrates an embodiment in which two dies114-2each have conductive contacts122and conductive contacts124disposed at the bottom surfaces; the conductive contacts122of the dies114-2are coupled to conductive contacts146at the top surface of the package substrate102via DTPS interconnects150-2, and the conductive contacts124of the dies114-2are coupled to conductive contacts124at the top surface of the die114via DTD interconnects130(e.g., as discussed above with reference toFIG.4). Additionally, a die114-3(or multiple dies114-3, not shown) is coupled to the die114-1by conductive contacts124on proximate surfaces of these dies114and intervening DTD interconnects130-2(e.g., as discussed above with reference toFIG.1).

As noted above, any suitable number of the dies114in a microelectronic assembly100may be double-sided dies114. For example,FIG.6illustrates a microelectronic assembly100sharing a number of elements withFIG.1, but including a double-sided die114-6. The die114-6includes conductive contacts122and124at its bottom surface; the conductive contacts122at the bottom surface of the die114-6are coupled to conductive contacts146at the top surface of the package substrate102via DTPS interconnects150-2, and the conductive contacts124at the bottom surface of the die114-6are coupled to conductive contacts124at the top surface of the die114-1via DTD interconnects130-1. The die114-6also includes conductive contacts124at its top surface; these conductive contacts124are coupled to conductive contacts124at the bottom surface of a die114-7by DTD interconnects130-3.

As noted above, a package substrate102may include one or more recesses108in which dies114are at least partially disposed. For example,FIG.7illustrates a microelectronic assembly100including a package substrate102having two recesses: a recess108-1and a recess108-2. In the embodiment ofFIG.7, the recess108-1is nested in the recess108-2, but in other embodiments, multiple recesses108need not be nested. InFIG.7, the die114-1is at least partially disposed in the recess108-1, and the dies114-6and114-3are at least partially disposed in the recess108-2. In the embodiment ofFIG.7, like the embodiment ofFIG.6, the die114-6includes conductive contacts122and124at its bottom surface; the conductive contacts122at the bottom surface of the die114-6are coupled to conductive contacts146at the top surface of the package substrate102via DTPS interconnects150-2, and the conductive contacts124at the bottom surface of the die114-6are coupled to conductive contacts124at the top surface of the die114-1via DTD interconnects130-1.

The die114-6also includes conductive contacts124at its top surface; these conductive contacts124are coupled to conductive contacts124at the bottom surface of a die114-7by DTD interconnects130-3. Further, the microelectronic assembly100ofFIG.7includes a die114-8that spans the package substrate102and the die114-6. In particular, the die114-8includes conductive contacts122and124at its bottom surface; the conductive contacts122at the bottom surface of the die114-8are coupled to conductive contacts146at the top surface of the package substrate102via DTPS interconnects150-3, and the conductive contacts124at the bottom surface of the die114-8are coupled to conductive contacts124at the top surface of the die114-6via DTD interconnects130-4.

In various ones of the microelectronic assemblies100disclosed herein, a single die114may bridge to other dies114from “below” (e.g., as discussed above with reference toFIGS.4and5) or from “above.” For example,FIG.8illustrates a microelectronic assembly100similar to the microelectronic assembly100ofFIG.7, but including two double-sided dies114-9and114-10, as well as an additional die114-11. The die114-9includes conductive contacts122and124at its bottom surface; the conductive contacts122at the bottom surface of the die114-9are coupled to conductive contacts146at the top surface of the package substrate102via DTPS interconnects150-3, and the conductive contacts124at the bottom surface of the die114-9are coupled to conductive contacts124at the top surface of the die114-6via DTD interconnects130-4. The die114-6includes conductive contacts124at its top surface; these conductive contacts124are coupled to conductive contacts124at the bottom surface of a die114-10by DTD interconnects130-3. Further, the die114-11includes conductive contacts124at its bottom surface; some of these conductive contacts124are coupled to conductive contacts124at the top surface of the die114-9by DTD interconnects130-6, and some of these conductive contacts124are coupled to conductive contacts124at the top surface of the die114-10by DTD interconnects130-5. The die114-11may thus bridge the dies114-9and114-10.

As noted above, in some embodiments, the package substrate102may not include any recesses108. For example,FIG.9illustrates an embodiment having dies114and a package substrate102mutually interconnected in the manner discussed above with reference toFIG.1, but in which the die114-1is not disposed in a recess in the package substrate102. Instead, the dies114are disposed above a planar portion of the top surface of the package substrate102. Any suitable ones of the embodiments disclosed herein that include recesses108may have counterpart embodiments that do not include a recess108. For example,FIG.10illustrates a microelectronic assembly100having dies114and a package substrate102mutually interconnected in the manner discussed above with reference toFIG.4, but in which the die114-1is not disposed in a recess in the package substrate102.

Any of the arrangements of dies114illustrated in any of the accompanying figures may be part of a repeating pattern in a microelectronic assembly100. For example,FIG.11illustrates a portion of a microelectronic assembly100in which an arrangement like the one ofFIG.10is repeated, with multiple dies114-1and multiple dies114-2. The dies114-1may bridge the adjacent dies114-2. More generally, the microelectronic assemblies100disclosed herein may include any suitable arrangement of dies114.FIGS.12-16are top views of example arrangements of multiple dies114in various microelectronic assemblies100, in accordance with various embodiments. The package substrate102is omitted fromFIGS.12-16; some or all of the dies114in these arrangements may be at least partially disposed in a recess108in a package substrate102or may not be disposed in a recess of a package substrate102. In the arrangements ofFIGS.12-16, the different dies114may include any suitable circuitry. For example, in some embodiments, the die114A may be an active or passive die, and the dies114B may include input/output circuitry, high bandwidth memory, and/or enhanced dynamic random-access memory.

FIG.12illustrates an arrangement in which a die114A is disposed below multiple different dies114B. The die114A may be connected to a package substrate102(not shown) in any of the manners disclosed herein with reference to the die114-1, while the dies114B may span the package substrate102and the die114A (e.g., in any of the manners disclosed herein with reference to the die114-2).FIG.12also illustrates a die114C disposed on the die114A (e.g., in the manner disclosed herein with reference to the die114-3). InFIG.12, the dies114B “overlap” the edges and/or the corners of the die114A, while the die114C is wholly above the die114A. Placing dies114B at least partially over the corners of the die114A may reduce routing congestion in the die114A and may improve utilization of the die114A (e.g., in case the number of input/outputs needed between the die114A and the dies114B is not large enough to require the full edge of the die114A). In some embodiments, the die114A may be disposed in a recess108in a package substrate102. In some embodiments, the die114A may be disposed in a recess108in a package substrate102, and the dies114B may be disposed in one or more recesses108in the package substrate102. In some embodiments, none of the dies114A or114B may be disposed in recesses108.

FIG.13illustrates an arrangement in which a die114A is disposed below multiple different dies114B. The die114A may be connected to a package substrate102(not shown) in any of the manners disclosed herein with reference to the die114-1, while the dies114B may span the package substrate102and the die114A (e.g., in any of the manners disclosed herein with reference to the die114-2).FIG.13also illustrates dies114C disposed on the die114A (e.g., in the manner disclosed herein with reference to the die114-3). InFIG.13, the dies114B “overlap” the edges of the die114A, while the dies114C are wholly above the die114A. In some embodiments, the die114A may be disposed in a recess108in a package substrate102. In some embodiments, the die114A may be disposed in a recess108in a package substrate102, and the dies114B may be disposed in one or more recesses108in the package substrate102. In some embodiments, none of the dies114A or114B may be disposed in recesses108. In the embodiment ofFIG.13, the dies114B and114C may be arranged in a portion of a rectangular array. In some embodiments, two dies114A may take the place of the single die114A illustrated inFIG.13, and one or more dies114C may “bridge” the two dies114A (e.g., in the manner discussed below with reference toFIG.15).

FIG.14illustrates an arrangement in which a die114A is disposed below multiple different dies114B. The die114A may be connected to a package substrate102(not shown) in any of the manners disclosed herein with reference to the die114-1, while the dies114B may span the package substrate102and the die114A (e.g., in any of the manners disclosed herein with reference to the die114-2). InFIG.14, the dies114B “overlap” the edges and/or the corners of the die114A. In some embodiments, the die114A may be disposed in a recess108in a package substrate102. In some embodiments, the die114A may be disposed in a recess108in a package substrate102, and the dies114B may be disposed in one or more recesses108in the package substrate102. In some embodiments, none of the dies114A or114B may be disposed in recesses108. In the embodiment ofFIG.14, the dies114B may be arranged in a portion of a rectangular array.

FIG.15illustrates an arrangement in which multiple dies114A are disposed below multiple different dies114B such that each die114A bridges two or more horizontally or vertically adjacent dies114B. The dies114A may be connected to a package substrate102(not shown) in any of the manners disclosed herein with reference to the die114-1, while the dies114B may span the package substrate102and the die114A (e.g., in any of the manners disclosed herein with reference to the die114-2). InFIG.12, the dies114B “overlap” the edges of the adjacent dies114A. In some embodiments, the dies114A may be disposed in one or more recesses108in a package substrate102. In some embodiments, the dies114A may be disposed in one or more recesses108in a package substrate102, and the dies114B may be disposed in one or more recesses108in the package substrate102. In some embodiments, none of the dies114A or114B may be disposed in recesses108. InFIG.15, the dies114A and the dies114B may be arranged in rectangular arrays.

FIG.16illustrates an arrangement in which multiple dies114A are disposed below multiple different dies114B such that each die114A bridges the four diagonally adjacent dies114B. The dies114A may be connected to a package substrate102(not shown) in any of the manners disclosed herein with reference to the die114-1, while the dies114B may span the package substrate102and the die114A (e.g., in any of the manners disclosed herein with reference to the die114-2). InFIG.12, the dies114B “overlap” the corners of the adjacent dies114A. In some embodiments, the dies114A may be disposed in one or more recesses108in a package substrate102. In some embodiments, the dies114A may be disposed in one or more recesses108in a package substrate102, and the dies114B may be disposed in one or more recesses108in the package substrate102. In some embodiments, none of the dies114A or114B may be disposed in recesses108. InFIG.16, the dies114A and the dies114B may be arranged in rectangular arrays.

In some deployment scenarios, different ones of the dies114may be manufactured by different foundries and/or according to different manufacturing technologies for better performance, optimized yield, cost, or accelerated ramp, and later assembled into a single microelectronic assembly100according to any embodiments described above. In such scenarios, any one of the dies114may be fabricated using hybrid integration of BEOL layers for disaggregated technologies according to a method200ofFIG.17.FIGS.18A-18Jillustrates cross-sectional side views of example IC dies after various processes of the method200ofFIG.17, in accordance with various embodiments. Some of the elements shown inFIGS.18A-18Jare referred in the present description with reference numerals illustrated in these drawings with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page ofFIGS.18A-18J. Although a certain number of a given element may be illustrated inFIGS.18A-18J(e.g., a certain number of conductive contacts or a certain number of conductive pathways), this is also simply for ease of illustration, and more, or less, than that number may be included in IC dies according to various embodiments of the present disclosure.

Although the operations of the manufacturing method illustrated inFIG.17are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, the operations may be performed in a different order to reflect the structure of a microelectronic assembly100in which an IC die fabricated using the method200will be included. In addition, the example manufacturing method illustrated inFIG.17may include other operations not specifically shown in the drawings, such as various cleaning operations as known in the art. For example, in some embodiments, the die surface that is being processed may be cleaned prior to, after, or during any of the processes of the manufacturing method illustrated inFIG.17, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using, e.g., a chemical solution (such as peroxide), and/or ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)).

Turning to the method200, at202, a die may be received. A die302, depicted inFIG.18A, illustrates an example of a die that may be received at202. As shown inFIG.18A, the die302may include a base332and an FEOL layer334over the base, the FEOL layer including active or passive circuitry336(e.g., transistors, diodes, resistors, inductors, and capacitors, among others), electrically isolated from one another by an insulating material338. The base332may be a die substrate, e.g., a die substrate1602described with reference toFIG.20. The FEOL layer334may include one or more device layers disposed on the die substrate, e.g., one of more device layers1604described with reference toFIG.20.

The die302may further include a first BEOL layer340-1over the FEOL layer334and a second BEOL layer340-2over the first BEOL layer340-2(together, the first and second BEOL layers340-1and340-2, as well as additional BEOL layers340-3,340-4, etc., shown in subsequent drawings, may be referred to as “BEOL layers340”). The first BEOL layer340-1may include a plurality of first conductive pathways342-1in a first insulating material344-1, while the second BEOL layer340-2may include a plurality of second conductive pathways342-2in a first insulating material344-2(together, the first and second conductive pathways342-1and342-2, as well as additional conductive pathways342-3,342-4, etc., shown in subsequent drawings, may be referred to as “conductive pathways342,” while the first and second insulating materials344-1and344-2, as well as additional insulating materials344-3,344-4, etc., shown in subsequent drawings, may be referred to as “insulating materials344”). Any of the conductive pathways342may include conductive traces and/or conductive vias, e.g., such as lines1628aand/or vias1628bdescribed with reference toFIG.20. It should be noted that the first BEOL layer340-1is not necessarily the very first BEOL layer340-1above the FEOL layer334, but that the terminology “first” merely represents a BEOL layer that is closer to the base332than the top BEOL layer of the die302received at202, where the top BEOL layer is the “second” BEOL layer340-2. To that end,FIG.18Afurther illustrates that the die302may include a further layer346between the FEOL layer334and the first BEOL layer340-1, where the further layer346may include one or more additional BEOL layers. The BEOL layers340and the further layer346may be implemented similar to interconnect layers disposed on the device layer, e.g., as interconnect layers1606-1610disposed on the one or more device layers1604as described with reference toFIG.20.

The top BEOL layer of the die302received at202, i.e., the second BEOL layer340-2, may include various conductive features protruding from the top surface of the second insulating material344-2. One example of such conductive features, shown inFIG.18A, are conductive contacts348. Typically, the die302would be received at202with a passivation layer350provided over all conductive features of the top surface of the die302, where the passivation layer350may include materials such as silicon oxide, silicon nitride, or silicon oxynitride.FIG.18Afurther illustrates that, in some embodiments, conductive features protruding from the top surface of the second insulating material344-2may also include conductive traces352, in which case the passivation layer350would be provided over the top of the conductive traces352as well.

The die302may be an example of a portion of any of the dies114of the microelectronic assembly100, where the conductive pathways342may take form of any of the conductive pathways to route power, ground, and/or signals to various components of the die302(e.g., to the active or passive circuitry336), to/from other dies, and/or to/from other components of the microelectronic assembly100(e.g., to/from the package substrate102) as described above. For example, the conductive pathways342may include TSVs, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide, or other conductive pathways through which power, ground, and/or signals may be transmitted in/through the die302. The conductive pathways342may be formed of any appropriate conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, for example. In some embodiments, the conductive pathways342in different BEOL layers340may be formed of different conductive materials; e.g., in some embodiments, the first conductive pathways342-1may be formed of copper, while the second conductive pathways342-2may be formed of aluminum. Similarly, the insulating materials344in different BEOL layers340may be same or different insulating materials, and may include any of the insulating materials typically used as interlayer dielectric (ILD) materials, such as low-k and ultra low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).

The conductive contacts348may be implemented similar to any of the conductive contacts of the microelectronic assembly100, described above, such as the conductive contacts122,124, etc. For example, in some embodiments, the conductive contacts348may be implemented as conductive pads or sockets. AlthoughFIG.18Aillustrates each of the conductive contacts348being coupled to one of the conductive pathways342, this need not be the case for all embodiments of the die302. In some embodiments, one or more of the conductive contacts348may be so-called “dummy conductive contacts” or “no-connect conductive contacts” because they are not electrically connected to any of the conductive pathways342and, hence, are electrically isolated from all components of the die302. Such dummy conductive contacts may sometimes be implemented in the die302in order to ensure that certain pad density rules are met.

Once the die302received at202is cleaned, the method200may proceed with204, in which an insulating material is deposited over the top surface of the die302. A die304, depicted inFIG.18B, illustrates an example of the die302with an insulating material354deposited on top. The insulating material354may be deposited at204using any suitable deposition techniques such as atomic level deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The insulating material354may include any of the insulating materials typically used as ILD materials, e.g., a silicon oxide. In general, the insulating material354may be substantially the same material as the insulating material344-2or the insulating material344-1, e.g., all of these could include silicon oxide. However, because it is deposited at a different place compared to where the insulating materials344-1and344-2were deposited (e.g., at a different foundry or a different other manufacturer), it may be difficult to match the exact material composition and material characteristics even if the same namesake material is used. Therefore, one characteristic feature indicative of the method200may be that the insulating material354has different density, porosity, compressive vs. tensile stress, or other material characteristics compared to the insulating materials344-1and344-2. For example, in some embodiments, the density of the insulating material354may differ by at least about 2% (e.g., by at least about 5%) from the density of the insulating material344-2. In some embodiments, any one of the porosity, compressive stress, or tensile stress of the insulating material354may differ by at least about 2% (e.g., by at least about 5%) from the corresponding characteristic of the insulating material344-2.

At206, the insulating material is deposited at204may be planarized. A die306, depicted inFIG.18C, illustrates an example of the die304for which the insulating material354deposited at204has been planarized. The planarization performed at206may include any suitable process for removing overburden or excess of the insulating material354. In some embodiments, planarization may be carried out at206using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface of the insulating material354.FIG.18Cillustrates an embodiment where, as a result of the planarization of the process206, some of the insulating material354remains on the top of (i.e., covering) all of the features of the die302, e.g., on top of the conductive contacts348and, if present, on top of the conductive traces352.

At208, a passivation layer may be deposited over the planarized insulating material. A die308, depicted inFIG.18D, illustrates an example of the die306with a passivation layer356deposited over the planar surface of the insulating material354. The passivation layer356may be deposited at208using any suitable deposition techniques such as ALD, CVD, PVD, etc., and may include any of the materials described with reference to the passivation layer350. However, because the passivation layer356is deposited at a different place compared to where the passivation layer350was deposited (e.g., at a different foundry or a different other manufacturer), it may be difficult to match the exact material composition and material characteristics even if the same namesake material is used. Therefore, another characteristic feature indicative of the method200may be that the passivation layer356may be different from the passivation layer350in one or more of stochiometry, density, porosity, compressive stress, or tensile stress, e.g., at least about 2% different or at least about 5% different. The flat, passivated surface of the die308, produced at the end of208, may then serve as a fundamental building block in performing further processing of the die. From here on, further processing may include one or more of formation of additional BEOL layers, integration of other active or passive circuitry (e.g., capacitors) over the top surface of the die308, and formation of new top conductive contacts, as needed for a particular deployment scenario. Formation of a flat, passivated surface even though the die may be originally received with a surface with conductive features protruding from it (e.g., as is the case for the die302) may be particularly advantageous for foundries or manufacturers that have fabrication processes designed to start with a die with a flat surface.

After the flat surface is formed at the end of208, the second BEOL layer340-2may be seen as including a first sub-layer341-1and a second sub-layer341-2. The first sub-layer341-1is a portion of the second BEOL layer340-2that includes second conductive pathways342-2surrounded by the second insulating material344-3, while the second sub-layer341-2is a portion of the second BEOL layer340-2that includes conductive features that were protruding from the surface of the die302(e.g., the conductive contacts348and conductive traces352) surrounded by the insulating material354.

From208, the method200may proceed with210, which includes forming one or more openings in the passivation layer356and the insulating material354to selectively expose (i.e., expose as needed) conductive features of the top surface of the die that was received at202. A die310, depicted inFIG.18E, illustrates an example of the die308for which a first opening358-1and a second opening358-2(together, referred to as “openings358”) are formed to expose the conductive contacts348. Although not specifically shown in the present drawings, in other embodiments,210may include forming openings to expose any of the conductive traces352and/or exposing only some but not all of the conductive contacts348. Exposing the conductive features of the die received at202includes at least removing portions of the passivation layer356and the passivation layer350; if any of the insulating material354remains over the top of the conductive features after the insulating material354is planarized at206, then forming the openings358at210further includes removing portions of the insulating material354that was remaining over the top of the conductive features. In various embodiments, any suitable etching techniques may be used at210, possibly in combination with patterning, to form the openings358. Some examples of etching techniques that may be used at210include, but are not limited to, any suitable anisotropic etch techniques such as a dry etch, e.g., radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In some embodiments, the etch performed in the process210may include an anisotropic etch using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. In some embodiments, during the etch of the process210, the die may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface. Some examples of patterning techniques that may be used at210include, but are not limited to, lithographic patterning or electron-beam patterning, possibly in combination with suitable masks.

The openings358formed at210may then be used to provide electrical connectivity between selective conductive features of the top surface of the die that was received at202(i.e., conductive features that were exposed by the openings358at210) and additional components that may be provided over the top surface of the die310. To that end, from210, the method200may proceed with any one or more of processes212,214, and216.

At212, one or more additional BEOL layers may be formed over the top surface of the die resulting from the process210. A die312, depicted inFIG.18F, illustrates an example of the die310over which a third BEOL layer342-3was formed at212. The third BEOL layer342-3may include a plurality of third conductive pathways (e.g., conductive traces and/or conductive vias)342-3in a third insulating material344-3, where at least some of the third conductive pathways342-3extend into the openings358formed at210, to electrically connect to some conductive features of the top surface of the die that was received at202, e.g., to route power, ground, and/or signals to/from these conductive features. For example,FIG.18Fillustrates that at least some of the third conductive pathways342-3may electrically connect (e.g., be in contact with) exposed portions of the conductive contacts348. A passivation layer360may be provided over the top of the third BEOL layer342-3. Any suitable deposition and patterning techniques as known in the art for forming BEOL layers may be used at212to provide one or more additional BEOL layers over the top surface of the die resulting from the process210.

At214, other active or passive circuitry (e.g., capacitors) may be integrated over the top surface of the die. A die314, depicted inFIG.18G, illustrates an example of the die312over which a fourth BEOL layer342-4was formed at214, the fourth BEOL layer342-4containing a structure362representing, e.g., capacitors (e.g., metal-insulator-metal (MIM) capacitors) as an example of active or passive circuitry that may be integrated. The fourth BEOL layer342-4may include a plurality of fourth conductive pathways (e.g., conductive traces and/or conductive vias)342-4in a fourth insulating material344-4. At least some of the fourth conductive pathways342-4may extend through the passivation layer360to electrically connect to some of the third conductive pathways342-3to route power, ground, and/or signals to/from the third conductive pathways342-3. At least some of the fourth conductive pathways342-4may electrically connect to the structure362to route power, ground, and/or signals to/from the structure362. A passivation layer364may be provided over the top of the fourth BEOL layer342-4. Any suitable deposition and patterning techniques (e.g., any of those described above) for forming BEOL layers with active or passive circuitry may be used at214to integrate such circuitry over the top surface of the die resulting from the process210or the process212. For example, in various embodiments, active or passive circuitry of the structure362may be fabricated using any suitable technique, e.g., Damascene, dual Damascene, semi-additive processing (SAP), or subtractive fabrication. Furthermore, the process214may include applying any suitable etching techniques (e.g., any of those described above) to form openings to expose underlying conductive structures to which the structures provided in the process214are to be electrically connected to. For example, the process214may include forming openings through the passivation layer360so that the fourth conductive pathways342-4and/or conductive portions of the structure362(e.g., capacitor electrodes) may be electrically connected to the third conductive pathways342-3. Integrating the structure362containing additional active or passive circuitry may advantageously allow adding new functionality to the die302that was received from a given foundry or manufacturer or it may allow enhancing existing functionality. For example, adding capacitors in the form of the structure362to the back end of the die314may address the challenge of native MIM capacitance insufficiency that may exist for the die302.

Although not specifically shown in the present drawings, in some embodiments, the method200may proceed to214directly from210. In such embodiments, the fourth BEOL layer340-4with the structure362would be formed directly over the openings358formed at210and at least some of the fourth conductive pathways342-4would extend into the openings358to electrically connect to some conductive features of the top surface of the die that was received at202, e.g., to route power, ground, and/or signals to/from these conductive features. However, it may be advantageous to include at least one intermediate BEOL layer (e.g., the third BEOL layer340-3) between the fourth BEOL layer340-4with the structure362and the second sub-layer341-2of the second BEOL layer340-2. For example, in some implementations, it may be advantageous in terms of decreasing the congestion of conductive pathways to/from the conductive features of the top surface of the die that was received at202and the active or passive circuitry (e.g., the structure364) provided at214, which may advantageously reduce power noise effects in the die.

At216, new top conductive contacts may be formed over the top surface of the die. A die316, depicted inFIG.18H, illustrates an example of the die314over which a fifth BEOL layer342-5is formed at216, the fifth BEOL layer342-5containing a plurality of fifth conductive pathways (e.g., conductive traces and/or conductive vias)342-5in a fifth insulating material344-5. A passivation layer366may be provided over the top of the fifth BEOL layer342-5. As shown inFIG.18H, the die316further includes new top conductive contacts368that may protrude from the surface of the fifth BEOL layer342-5and may be electrically connected, through openings in the passivation layer366, to some of the over the fifth conductive pathways342-5and, therefore, to the conductive pathways342in lower BEOL layers340, to route power, ground, and/or signals to components connected thereto. Any suitable deposition and patterning techniques (e.g., any of those described above) for forming new top conductive contacts may be used at216to integrate such conductive contacts over the top surface of the die resulting from any of the processes210,212, or214. For example, the process216may include applying any suitable etching techniques (e.g., any of those described above) to form openings to expose underlying conductive structures to which the new top conductive contacts368provided in the process216are to be electrically connected to. For example, the process216may include forming openings through the passivation layer364and the passivation layer366so that the new top conductive contacts368may be electrically connected to conductive pathways342in the underlying BEOL layers340.

A die318, depicted inFIG.18I, illustrates an example of the die310with the new top conductive contacts368as described with reference toFIG.18Hformed by directly connecting to the conductive features, e.g., the conductive contacts348, exposed by the openings358formed at210. Thus, the die318is one example illustration of the method200proceeding from210directly to216, without performing212or214(the possibility of which is illustrated inFIG.2with an arrow directly from210to216). Another example of proceeding from210directly to216without performing212or214is shown with a die320ofFIG.18J.FIG.18Jillustrates an embodiment where the planarization performed at206is such that the insulating material354is flush with the upper surface of the conductive features, e.g., the conductive contacts348. The passivation layer deposited at208has a non-zero thickness and, therefore, there will still be an opening formed through it at210, in order to expose the conductive contacts348so that an electrical connection may be made between the new top conductive contacts368and the original conductive contacts348. Thus, characteristic of the use of the method200may be that the width of the openings formed at210(a dimension shown inFIG.18Jas a width372) may be smaller than the width of the new top conductive contacts368(a dimension shown inFIG.18Jas a width374). Forming the new conductive contacts368over the top surface of the die302that was received from a given foundry or manufacturer may advantageously allow addressing the challenge of unifying the metal and passivation materials used by different foundries or manufacturers, so that different dies may be included within a single microelectronic assembly100in a manner that is less costly and complex.

In general, the insulating materials344of the BEOL layers340starting with the third BEOL layer340-3may include any of the insulating materials described for the BEOL layers340-1and340-2; the passivation layers360,364,366may include any of the materials described for the passivation layers350and354; and the conductive pathways342of the BEOL layers340starting with the third BEOL layer340-3may include any of the conductive materials described for the BEOL layers340-1and340-2. However, the dies312,314,316,318, and320will also exhibit several additional features that are characteristic of the use of the method200.

One such feature is that, similar to the insulating material254, the insulating materials344of the BEOL layers340starting with the third BEOL layer340-3may have different (e.g., at least about 2% different or at least about 5% different) stochiometry, density, porosity, compressive vs. tensile stress, or other material characteristics compared to the insulating materials344-1and344-2even though the same namesake insulating materials may be used.

Another characteristic feature is that, similar to the passivation layer356, the passivation layers360,364,366may have different (e.g., at least about 2% different or at least about 5% different) stochiometry, density, porosity, compressive vs. tensile stress, or other material characteristics compared to the passivation layer350even though the same namesake insulating materials may be used.

Yet another characteristic feature is that, similar to the conductive pathways342-1, the conductive pathways342of the BEOL layers340starting with the third BEOL layer340-3be formed of a different metal than the conductive pathways342-2. Thus, in some implementations of the method200, a resulting die may include a BEOL layer340with conductive pathways342of one metal be sandwiched between BEOL layers340with conductive pathways342of another metal. For example, in some embodiments, the first conductive pathways342-1and the third conductive pathways342-3may be formed of copper, while the second conductive pathways342-2may be formed of aluminum. In this context, additional active or passive circuitry such as the one represented by the structure362would normally be implemented below (i.e., closer to the base332than) the layer of conductive pathways formed of aluminum, but in the die314or the die316it would be above (i.e., further away from the base332than) the layer of conductive pathways formed of aluminum.

Furthermore, an inset380, shown inFIG.18F, illustrates that a given conductive pathway, e.g., a metal trace, may include a conductive fill material382and a liner384. What would be characteristic of the use of the method200is that, in some embodiments, a material composition of the liner384of either the first conductive pathways342-1or the second conductive pathways342-2is different from a material composition of the liner384of the third conductive pathways342-3. For example, the liner384of either the first conductive pathways342-1or the second conductive pathways342-2may be a liner having one or more of tantalum, tantalum nitride, titanium nitride, and tungsten carbide, while the liner384of the third conductive pathways342-3may be a liner having one or more of tantalum, tantalum nitride, and cobalt. In any of these liners384, any of the materials may be included in the amount of between about 5% and 50%, indicating that these materials are included by intentional alloying of materials, in contrast to potential unintentionally doping or impurities being included, which would be less than about 0.1% for any of these metals. In other embodiments, other materials and combinations of materials may be used, all being within the scope of the present disclosure. In further embodiments, thicknesses of these liners may be different. For example, in some embodiments, a thickness of the liner384of either the first conductive pathways342-1or the second conductive pathways342-2is different from a thickness of the liner384of the third conductive pathways342-3, e.g., at least about 5% different, at least about 10% different, or at least 5-50% different. For example, in some embodiments, the liner384of either the first conductive pathways342-1or the second conductive pathways342-2may have a thickness between about 1 and 6 nanometers, including all values and ranges therein, while the liner384of the third conductive pathways342-3may have a thickness between about 4 and 10 nanometers, including all values and ranges therein. In other embodiments, the liner384of the third conductive pathways342-3may have a thickness between about 1 and 6 nanometers, including all values and ranges therein, while the liner384of either the first conductive pathways342-1or the second conductive pathways342-2may have a thickness between about 4 and 10 nanometers, including all values and ranges therein. It should be noted that, even though the inset380and some other cross-sectional side views of some of the conductive pathways342are shown as tapering down the closer they get to the base332, which may be indicative of Damascene fabrication used to form those conductive pathways, in various embodiments, any of the conductive pathways342described herein may be fabricated using any suitable technique, e.g., Damascene, dual Damascene, SAP, or subtractive fabrication.

Still another characteristic feature of the use of the method200is that the old conductive contacts, i.e., the conductive contacts348that were present on the die302received at202, may be buried below the surface of the dies312,314,316,318, and320, covered by the additional materials provided at212,214, and216. A related feature is that the conductive contacts348that were present on the die302received at202may be directly electrically connected to conductive pathways both below and above the second sub-layer341-2of the second BEOL layer340-2. This is drastically different form conventional dies, where conductive contacts are electrically connected to conductive pathways on one side, but to interconnects such as DTD or DTPS interconnects on the other.

The IC dies fabricated using hybrid integration of BEOL layers for disaggregated technologies as disclosed herein, and the microelectronic assemblies100with such dies as disclosed herein may be included in any suitable electronic component.FIGS.19-22illustrate various examples of apparatuses that may include, or be included in, any of the dies fabricated using hybrid integration of BEOL layers for disaggregated technologies disclosed herein or any of the microelectronic assemblies100disclosed herein.

FIG.19is a top view of a wafer1500and dies1502that may include any of the dies fabricated using hybrid integration of BEOL layers for disaggregated technologies disclosed herein (e.g., any suitable ones of the dies114) and that may be included in any of the microelectronic assemblies100disclosed herein. The wafer1500may be composed of semiconductor material and may include one or more dies1502having IC structures formed on a surface of the wafer1500. Each of the dies1502may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer1500may undergo a singulation process in which the dies1502are separated from one another to provide discrete “chips” of the semiconductor product. The die1502may be any of the dies114disclosed herein. The die1502may include one or more transistors (e.g., some of the transistors1640ofFIG.20, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other IC components. In some embodiments, the wafer1500or the die1502may include a memory device (e.g., a random-access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1502. For example, a memory array formed by multiple memory devices may be formed on a same die1502as a processing device (e.g., the processing device1802ofFIG.22) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. Various ones of the dies fabricated using hybrid integration of BEOL layers for disaggregated technologies as disclosed herein may be processed as a part of the wafer1500that includes others of the dies114, and the wafer1500is subsequently singulated.

FIG.20is a cross-sectional side view of an IC device1600that may be included in any of the dies fabricated using hybrid integration of BEOL layers for disaggregated technologies disclosed herein (e.g., any suitable ones of the dies114) and/or in any of the microelectronic assemblies100with such dies. One or more of the IC devices1600may be included in one or more dies1502(FIG.19). The IC device1600may be formed on a die substrate1602(e.g., the wafer1500ofFIG.19) and may be included in a die (e.g., the die1502ofFIG.19). The die substrate1602may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate1602may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate1602may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, Ill-V, or IV may also be used to form the die substrate1602. Although a few examples of materials from which the die substrate1602may be formed are described here, any material that may serve as a foundation for an IC device1600may be used. The die substrate1602may be part of a singulated die (e.g., the dies1502ofFIG.19) or a wafer (e.g., the wafer1500ofFIG.19).

The IC device1600may include one or more device layers1604disposed on the die substrate1602. The device layer1604may include features of one or more transistors1640(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate1602. The device layer1604may include, for example, one or more source and/or drain (S/D) regions1620, a gate1622to control current flow in the transistors1640between the S/D regions1620, and one or more S/D contacts1624to route electrical signals to/from the S/D regions1620. The transistors1640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1640are not limited to the type and configuration depicted inFIG.20and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

The S/D regions1620may be formed within the die substrate1602adjacent to the gate1622of each transistor1640. The S/D regions1620may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate1602to form the S/D regions1620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate1602may follow the ion-implantation process. In the latter process, the die substrate1602may first be etched to form recesses at the locations of the S/D regions1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1620. In some implementations, the S/D regions1620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1620may be formed using one or more alternate semiconductor materials such as germanium or a group Ill-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors1640) of the device layer1604through one or more interconnect layers disposed on the device layer1604(illustrated inFIG.20as interconnect layers1606-1610). For example, electrically conductive features of the device layer1604(e.g., the gate1622and the S/D contacts1624) may be electrically coupled with the interconnect structures1628of the interconnect layers1606-1610. The one or more interconnect layers1606-1610may form a metallization stack (also referred to as an “ILD stack”)1619of the IC device1600.

The interconnect structures1628may be arranged within the interconnect layers1606-1610to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures1628depicted inFIG.20. Although a particular number of interconnect layers1606-1610is depicted inFIG.20, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1628may include lines1628aand/or vias1628bfilled with an electrically conductive material such as a metal. The lines1628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate1602upon which the device layer1604is formed. For example, the lines1628amay route electrical signals in a direction in and out of the page from the perspective ofFIG.20. The vias1628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate1602upon which the device layer1604is formed. In some embodiments, the vias1628bmay electrically couple lines1628aof different interconnect layers1606-1610together.

The interconnect layers1606-1610may include a dielectric material1626disposed between the interconnect structures1628, as shown inFIG.20. In some embodiments, the dielectric material1626disposed between the interconnect structures1628in different ones of the interconnect layers1606-1610may have different compositions; in other embodiments, the composition of the dielectric material1626between different interconnect layers1606-1610may be the same.

A first interconnect layer1606(referred to as Metal 1 or “M1”) may be formed directly on the device layer1604. In some embodiments, the first interconnect layer1606may include lines1628aand/or vias1628b, as shown. The lines1628aof the first interconnect layer1606may be coupled with contacts (e.g., the S/D contacts1624) of the device layer1604.

A second interconnect layer1608(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer1606. In some embodiments, the second interconnect layer1608may include vias1628bto couple the lines1628aof the second interconnect layer1608with the lines1628aof the first interconnect layer1606. Although the lines1628aand the vias1628bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer1608) for the sake of clarity, the lines1628aand the vias1628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual Damascene process) in some embodiments.

A third interconnect layer1610(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1608according to similar techniques and configurations described in connection with the second interconnect layer1608or the first interconnect layer1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack1619in the IC device1600(i.e., farther away from the device layer1604) may be thicker.

The IC device1600may include a solder resist material1634(e.g., polyimide or similar material) and one or more conductive contacts1636formed on the interconnect layers1606-1610. InFIG.20, the conductive contacts1636are illustrated as taking the form of bond pads. The conductive contacts1636may be electrically coupled with the interconnect structures1628and configured to route the electrical signals of the transistor(s)1640to other external devices. For example, solder bonds may be formed on the one or more conductive contacts1636to mechanically and/or electrically couple a chip including the IC device1600with another component (e.g., a circuit board). The IC device1600may include additional or alternate structures to route the electrical signals from the interconnect layers1606-1610; for example, the conductive contacts1636may include other analogous features (e.g., posts) that route the electrical signals to external components. The conductive contacts1636may serve as the conductive contacts122or124, as appropriate.

In some embodiments in which the IC device1600is a double-sided die (e.g., like the die114-1), the IC device1600may include another metallization stack (not shown) on the opposite side of the device layer(s)1604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers1606-1610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)1604and additional conductive contacts (not shown) on the opposite side of the IC device1600from the conductive contacts1636. These additional conductive contacts may serve as the conductive contacts122or124, as appropriate.

In other embodiments in which the IC device1600is a double-sided die (e.g., like the die114-1), the IC device1600may include one or more TSVs through the die substrate1602; these TSVs may make contact with the device layer(s)1604, and may provide conductive pathways between the device layer(s)1604and additional conductive contacts (not shown) on the opposite side of the IC device1600from the conductive contacts1636. These additional conductive contacts may serve as the conductive contacts122or124, as appropriate.

FIG.21is a cross-sectional side view of an IC device assembly1700that may include any of the dies fabricated using hybrid integration of BEOL layers for disaggregated technologies disclosed herein (e.g., any suitable ones of the dies114) and/or any of the microelectronic assemblies100disclosed herein. In some embodiments, the IC device assembly1700may be a microelectronic assembly100where at least one of the dies114is a die fabricated using hybrid integration of BEOL layers for disaggregated technologies disclosed herein. The IC device assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC device assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742. Any of the IC packages discussed below with reference to the IC device assembly1700may take the form of any suitable ones of the embodiments of the microelectronic assemblies100disclosed herein.

In some embodiments, the circuit board1702may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board1702. In other embodiments, the circuit board1702may be a non-PCB substrate. In some embodiments the circuit board1702may be, for example, the circuit board133.

The IC device assembly1700illustrated inFIG.21includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702, and may include solder balls (as shown inFIG.21), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to an interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG.21, multiple IC packages may be coupled to the interposer1704; indeed, additional interposers may be coupled to the interposer1704. The interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, a die (the die1502ofFIG.19), an IC device (e.g., the IC device1600ofFIG.20), or any other suitable component. Generally, the interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer1704may couple the IC package1720(e.g., a die) to a set of ball grid array (BGA) conductive contacts of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG.21, the IC package1720and the circuit board1702are attached to opposing sides of the interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the interposer1704. In some embodiments, three or more components may be interconnected by way of the interposer1704.

The IC device assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC device assembly1700illustrated inFIG.21includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art.

FIG.22is a block diagram of an example electrical device1800that may include any of the dies fabricated using hybrid integration of BEOL layers for disaggregated technologies disclosed herein (e.g., any suitable ones of the dies114) and/or one or more of the microelectronic assemblies100disclosed herein. For example, any suitable ones of the components of the electrical device1800may include one or more of the IC device assemblies1700, IC devices1600, or dies1502disclosed herein, and may be arranged in any of the microelectronic assemblies100disclosed herein. A number of components are illustrated inFIG.22as included in the electrical device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

Additionally, in various embodiments, the electrical device1800may not include one or more of the components illustrated inFIG.22, but the electrical device1800may include interface circuitry for coupling to the one or more components. For example, the electrical device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the electrical device1800may not include an audio input device1824or an audio output device1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled.

The electrical device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1800to an energy source separate from the electrical device1800(e.g., AC line power).

The electrical device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the electrical device1800, as known in the art.

The electrical device1800may include an other output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

Example 1 provides an IC die that includes: a base; a FEOL layer over the base, the FEOL layer including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others); a first BEOL layer including first conductive pathways (e.g., conductive traces and/or conductive vias); a second BEOL layer including second conductive pathways; and a third BEOL layer including third conductive pathways, where the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second conductive pathways is different from an electrically conductive fill material of the first conductive pathways and from an electrically conductive fill material of the third conductive pathways.

Example 2 provides the IC die according to example 1, where the electrically conductive fill material of the second conductive pathways includes aluminum, and where at least one of the electrically conductive fill material of the first conductive pathways or the electrically conductive fill material of the third conductive pathways includes copper.

Example 3 provides the IC die according to any one of examples 1-2, where the second BEOL layer includes a first sub-layer and a second sub-layer, the first sub-layer is between the FEOL layer and the second sub-layer and includes a first subset of the second conductive pathways separated from one another by a first insulator material, the second sub-layer is between the first sub-layer and the third BEOL layer and includes a second subset of the second conductive pathways separated from one another by a second insulator material, and the second insulator material and the first insulator material have different material compositions.

Example 4 provides the IC die according to example 3, where a portion of the second insulator material is above the second subset of the second conductive pathways, and at least one of the third conductive pathways extends through the portion of the second insulator material that is above the second subset of the second conductive pathways and contacts at least one of the second subset of the second conductive pathways.

Example 5 provides the IC die according to example 4, further including an intermediate layer over the second subset of second conductive pathways, where the at least one of the third conductive pathways extends through the intermediate layer.

Example 6 provides the IC die according to example 5, the intermediate layer is between the second subset of the second conductive pathways and the portion of the second insulator material that is above the second subset of the second conductive pathways.

Example 7 provides the IC die according to any one of examples 5-6, where the intermediate layer is further at an interface between the first insulator material and the second insulator material.

Example 8 provides the IC die according to any one of examples 5-7, where the third conductive pathways are separated from one another by a third insulator material, the intermediate layer is a first intermediate layer, and the IC die further includes a second intermediate layer at an interface between the second insulator material and the third insulator material.

Example 9 provides the IC die according to example 8, where the at least one of the third conductive pathways extends through the second intermediate layer.

Example 10 provides the IC die according to any one of examples 1-9, further including one or more capacitors in the third BEOL layer.

Example 11 provides the IC die according to any one of examples 1-10, where at least some of the first conductive pathways include a liner and an electrically conductive fill material, at least some of the third conductive pathways include a liner and an electrically conductive fill material, and a material composition of the liner of the first conductive pathways is different from a material composition of the liner of the third conductive pathways.

Example 12 provides the IC die according to example 11, where a thickness of the liner of the first conductive pathways is different from a thickness of the liner of the third conductive pathways, e.g., at least about 5% different, at least about 10% different, or at least 5-50% different.

Example 13 provides the IC die according to examples 11 or 12, where a material composition of the electrically conductive fill material of the first conductive pathways is different from a material composition of the electrically conductive fill material of the third conductive pathways. For example, the electrically conductive fill material of the first conductive pathways may include copper (Cu), while the electrically conductive fill material of the third conductive pathways may include tungsten (W), aluminum (Al), ruthenium (Ru), cobalt (Co), or AlCu (e.g., in proportions of between 1:1 to 1:100).

Example 14 provides the IC die according to any one of examples 1-13, where the second BEOL layer further includes a conductive pad.

Example 15 provides the IC die according to example 14, where the conductive pad has a first face and a second face, the first face is closer to the base than the second face, one of the second conductive pathways is electrically connected to the first face of the conductive pad, and one of the third conductive pathways is electrically connected to the second face of the conductive pad.

Example 16 provides an IC die that includes a device layer, including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others); a first metallization layer over the device layer, the first metallization layer including a first insulator material having a first face and a second face opposite the first face, and further including first conductive pathways (e.g., conductive traces and/or conductive vias) in the first insulator material, where the first face is closer to the device layer than the second face; a layer including conductive contacts at the second face of the metallization layer; and a second metallization layer including second conductive pathways (e.g., conductive traces and/or conductive vias), where the layer is between the first metallization layer and the second metallization layer.

Example 17 provides the IC die according to example 16, where the conductive contacts include conductive pads.

Example 18 provides the IC die according to examples 16 or 17, where at least one of the conductive contacts is electrically connected to one of the first conductive pathways on one side of the at least one of the conductive contacts and is electrically connected to one of the second conductive pathways on another side of the at least one of the conductive contacts.

Example 19 provides the IC die according to any one of examples 16-18, where at least one of the conductive contacts is electrically connected to one of the first conductive pathways on one side of the at least one of the conductive contacts and is not electrically connected to any further pathways above the second face of the first metallization layer.

Example 20 provides an IC die that includes a device layer, including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others); a first metallization layer over the device layer, the first metallization layer including a first insulator material and first conductive pathways (e.g., conductive traces and/or conductive vias) in the first insulator material; a second metallization layer over the device layer, the second metallization layer including a second insulator material and second conductive pathways (e.g., conductive traces and/or conductive vias) in the second insulator material; and conductive contacts buried in a layer of a third insulator material between the first metallization layer and the second metallization layer.

Example 21 provides the IC die according to example 20, where at least one of the conductive contacts is electrically connected to one of the first conductive pathways on one side of the at least one of the conductive contacts and is electrically connected to one of the second conductive pathways on another side of the at least one of the conductive contacts.

Example 22 provides an IC package that includes an IC die including an IC die according to any one of examples 1-21; and a further IC component, coupled to the IC die.

Example 23 provides the IC package according to example 22, where the further IC component includes a package substrate.

Example 24 provides the IC package according to example 22, where the further IC component includes an interposer.

Example 25 provides the IC package according to example 22, where the further IC component includes a further IC die.

Example 26 provides a computing device that includes a carrier substrate and an IC die coupled to the carrier substrate, where the IC die is an IC die according to any one of examples 1-21, or the IC die is included in the IC package according to any one of examples 22-25.

Example 27 provides the computing device according to example 26, where the computing device is a wearable or handheld computing device.

Example 28 provides the computing device according to examples 26 or 27, where the computing device further includes one or more communication chips.

Example 29 provides the computing device according to any one of examples 26-28, where the computing device further includes an antenna.

Example 30 provides the computing device according to any one of examples 26-29, where the carrier substrate is a motherboard.

Example 31 provides the IC die according to any one of examples 1-21, where the IC die includes or is a part of a central processing unit.

Example 32 provides the IC die according to any one of examples 1-31, where the IC die includes or is a part of a memory device.

Example 33 provides the IC die according to any one of examples 1-32, where the IC die includes or is a part of a logic circuit.

Example 34 provides the IC die according to any one of examples 1-33, where the IC die includes or is a part of input/output circuitry.

Example 35 provides the IC die according to any one of examples 1-34, where the IC die includes or is a part of a field programmable gate array transceiver.

Example 36 provides the IC die according to any one of examples 1-35, where the IC die includes or is a part of a field programmable gate array logic.

Example 37 provides the IC die according to any one of examples 1-36, where the IC die includes or is a part of a power delivery circuitry.

Example 38 provides the IC die according to any one of examples 1-37, where the IC die includes or is a part of a Ill-V amplifier.

Example 39 provides the IC die according to any one of examples 1-38, where the IC die includes or is a part of Peripheral Component Interconnect Express circuitry or Double Data Rate transfer circuitry.