INTEGRATED CIRCUIT CAPABLE OF PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING OPERATION BASED ON WORKLOAD AND OPERATING METHOD THEREOF

Provided are an integrated circuit capable of classifying a workload of a core based on monitored data and performing a dynamic voltage and frequency scaling (DVFS) operation based on the classified workload, and an operating method of the integrated circuit. The integrated circuit includes at least one core, a shared buffer which receives a request from the at least one core, access an external memory according to the request, and receive a response from the external memory, a monitor which monitors the shared buffer to obtain a buffer capacity of the shared buffer and a response waiting time, and a DVFS controller configured to classify a workload of the at least one core.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0101594, filed on Aug. 12, 2022, and Korean Patent Application No. 10-2022-0170043, filed on Dec. 7, 2022, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety.

BACKGROUND

The inventive concepts relate to integrated circuits, and more particularly, to integrated circuits capable of classifying the workload of a core based on monitored data and performing a dynamic voltage and frequency scaling (DVFS) operation based on the classified workload, and operating methods of the integrated circuits.

As computing systems such as mobile devices are becoming more compact, power management has emerged as an important issue. In particular, in the case of portable devices such as mobile devices, which use batteries with limited energy, power is reduced in order to reduce power consumption, but voltage has to be increased to improve the performance thereof. Thus, the need for efficient power management according to workload characteristics such as memory characteristics of a bus or a dynamic random access memory (DRAM) is increasing.

SUMMARY

The inventive concepts provide integrated circuits, operating methods of the integrated circuits, and computing systems, wherein the integrated circuits are capable of classifying a workload by considering not only a state of a central processing unit (CPU), or the like, but also the characteristics of a bus or a dynamic random access memory (DRAM), and a dynamic voltage and frequency scaling (DVFS) operation may be effectively performed by differently determining a scaling factor based on the classified workload. For example, power management of an application processor of a mobile device can be done by controlling a voltage through a DVFS operation in which a frequency and a voltage of a processing device are controlled according to a workload of a processing device embedded in the application processor.

According to some aspects of the inventive concepts, there is provided an integrated circuit including at least one core configured to process an instruction according to a voltage-frequency level, a shared buffer which receives a request from the at least one core, access an external memory according to the request, and receive a response from the external memory, a monitor configured to monitor the shared buffer to obtain a buffer capacity of the shared buffer and a response waiting time for the response received from the external memory, and a DVFS controller configured to receive, from the monitor, the buffer capacity and the response waiting time, classify a workload of the at least one core based on the buffer capacity and the response waiting time, and determine a scaling factor for the voltage-frequency level based on the classified workload.

According to some aspects of the inventive concepts, there is provided an operating method of an integrated circuit, the operating method including monitoring a shared buffer and obtaining a buffer capacity of the shared buffer and a response waiting time for a response received from an external memory, classifying a workload of a core based on the buffer capacity and the response waiting time, and determining a scaling factor for a voltage-frequency level of the core based on the classified workload of the core.

According to some aspects of the inventive concepts, there is provided a computing system including a processor, at least one memory, a bus connecting the processor to the at least one memory, a DVFS controller configured to classify a workload of at least one core based on a buffer capacity of a shared buffer and a response waiting time for a response received from the bus, determine a scaling factor based on the classified workload, and generate a voltage control signal and a clock control signal based on the determined scaling factor, a power management unit configured to adjust an amplitude of a power supply voltage provided to the at least one core in response to the voltage control signal, and a clock management unit configured to adjust a frequency of a clock signal provided to the at least one core, in response to the clock control signal, the processor including the at least one core configured to process an instruction according to the amplitude of the power supply voltage and a frequency of the clock signal, the shared buffer configured to receive a request from the at least one core, access the bus according to the request, and receive a response from the bus, and a monitor configured to monitor the shared buffer to obtain the buffer capacity and the response waiting time.

DETAILED DESCRIPTION

FIG.1is a block diagram illustrating an integrated circuit according to some example embodiments.

Referring toFIG.1, an integrated circuit10may include a processor100, a dynamic voltage and frequency scaling (DVFS) controller200, a clock management unit (CMU)300, a power management unit (PMU)400, a bus500, and a memory600. In some example embodiments, the processor100, the DVFS controller200, the clock management unit300, the power management unit400, the bus500, and the memory600may be included in a single chip, that is, a system-on-chip (SoC), and the integrated circuit10may be referred to as an application processor (AP). However, in some example embodiments, the processor100, the DVFS controller200, the clock management unit300, the power management unit400, the bus500, and the memory600may be included in a plurality of chips.

The integrated circuit10may be included in a stationary computing system such as a desktop PC, a server, and the like, and may be included in a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, an internet of everything (IoE) device, and/or an e-book.

The processor100may include at least one core110, a shared buffer120, and a monitor130. In some example embodiments, the processor100may execute a program composed of instructions. A program may include a plurality of subprograms, and a subprogram may be referred to as a subroutine, a routine, a procedure, a function, or the like.

The core110may process instructions independently. Hereinafter, a central processing unit (CPU) core will be mainly described as the core110, but it is noted the example embodiments are not limited thereto. For example, the core110may include a CPU core, a graphics processing unit (GPU) core, a neural processing unit (NPU) core, or an image signal processor (ISP) core. As a plurality of cores110may be included in the processor100, the processor100may be referred to as a multi-core processor. In some example embodiments, the core110may process an instruction according to a clock signal clk and a power supply voltage vdd, and the performance of the core110may depend on the clock signal clk and the power supply voltage vdd. Some example embodiments of the above will be described later with reference toFIGS.6A and6B.

The shared buffer120may include a buffer shared by the plurality of cores110in a multi-core processor. For example, the processor100may include a CPU, the plurality of cores110may include an L2 cache, and the shared buffer120may include an L3 cache. The shared buffer120may store data not included in the core110and may transmit/receive data to or from the core110. In some example embodiments, data for the core110to process a command may not exist inside the core110, and data may be requested Req from the shared buffer120. The shared buffer120may receive a request Req from the core110, and when data corresponding to the request Req exists in the shared buffer120, the corresponding data may be transmitted to the core110. When the data corresponding to the request Req does not exist in the shared buffer120(for example, when a cache miss has occurred), an external memory may be accessed Acc, and a response Res from the external memory may be received to obtain data corresponding to the request Req. For example, the shared buffer120may access Acc the memory600through the bus500and receive a response Res from the memory600through the bus500. The shared buffer120may include a plurality of blocks121, and some example embodiments regarding this will be described later with reference toFIG.2.

The monitor130may monitor the shared buffer120and obtain a buffer capacity of the shared buffer120and a response waiting time for a response received from the external memory. In some example embodiments, the buffer capacity of the shared buffer120may represent a filled state of the capacity of the plurality of blocks121, and the response waiting time for a response received from the external memory may be a period of time taken by the shared buffer120to receive a response Res from the memory600after accessing Acc the memory600through the bus500. Some example embodiments of this will be described later with reference toFIGS.3A and3B.

In some example embodiments, the monitor130may monitor the core110, and obtain, from the shared buffer120, a period of time taken by the core110to receive data corresponding to the request Req. For example, the core110may include a CPU core and may include the L2 cache. The shared buffer120may include the L3 cache. Data for a CPU core to process an instruction may not be in the L2 cache, and may be requested Req from the L3 cache. The L3 cache may receive a request Req from the L2 cache, and if data corresponding to the request Req exists in the L3 cache, the corresponding data may be transmitted to the L2 cache. When data corresponding to the request Req does not exist in the L3 cache, the L3 cache may access Acc an external memory, receive a response Res from the external memory, and obtain data corresponding to the request Req. The L3 cache may transmit data obtained from the external memory to the L2 cache. The monitor130may monitor the L2 cache, request Req data from the L3 cache, and obtain a period of time taken until data corresponding to the request Req is received from the L3 cache.

The DVFS controller200may receive a buffer capacity of the shared buffer120from the monitor130and a response waiting time for a response received from an external memory, and classify a workload of the core110based on the buffer capacity and the response waiting time. In some example embodiments, the DVFS controller200may classify the workload of the core110as a first workload or a second workload, and the first workload may include more requests for accessing an external memory than the second workload. For example, the first workload may be a memory intensive workload, and the memory intensive workload may refer to a situation in which congestion occurs in the bus500or the memory600when a cache miss occurs during an operation of the processor100. Congestion may refer to a condition, for example, in which a number of packets/signals (for example, commands) is greater than a number of packets/signals the processor100may receive and process, and other conditions as may be understood by one skilled in the art, for example related to physical, virtual, or other limits of the processor100, bus5900, the memory600and/or other components. The second workload may be a computing workload, and the computing workload is related to instruction processing of the core110, and may refer to a situation in which a cache miss does not occur during an operation of the processor100.

In some example embodiments, the DVFS controller200may classify the workload of the core110as the first workload when the buffer capacity and the response waiting time are equal to or greater than a threshold value. If the buffer capacity or the response waiting time is less than the threshold value, the DVFS controller200may classify the workload of the core110as the second workload. Some example embodiments of this will be described later with reference toFIGS.2to4.

In some example embodiments, the DVFS controller200may receive, for example, from the monitor130, a period of time taken by the core110to receive the data corresponding to the request Req from the shared buffer120, and classify, based on the received period of time, the workload of the core110as the first workload or the second workload. The first workload may include more requests for accessing an external memory than the second workload. For example, the core110may be a CPU core and may include the L2 cache. The shared buffer120may be the L3 cache. When there is free space in the L3 cache capacity, the L3 cache may receive a request Req from the L2 cache, and respond to the request Req by receiving an access Acc to an external memory and obtain data corresponding to the response Res from the external memory. The period of time taken for the L2 cache to receive the data corresponding to the request Req from the L3 cache may be shorter than a threshold time, and the DVFS controller200may classify the workload of the core110as the second workload. When there is no free space in the L3 cache capacity (for example, when the capacity of the L3 cache is filled with data other than the data corresponding to the request Req), the L3 cache may not receive the request Req from the L2 cache, and may receive the request Req after performing an operation on the filled data. Then, data corresponding to the request Req may be obtained by accessing Acc the external memory and receiving a response Res from the external memory. The period of time taken for the L2 cache to receive the data corresponding to the request Req from the L3 cache may be longer than a threshold time, and the DVFS controller200may classify the workload of the core110as the first workload.

The DVFS controller200may determine a scaling factor for a voltage-frequency level based on the classified workload of the core110. In some example embodiments, the scaling factor may be determined such that the voltage-frequency level decreases according to the workload of the classified core110. For example, the DVFS controller200may classify the workload of the core110as a first workload or a second workload, and the first workload may include more requests for accessing an external memory than the second workload. The required performance of the core110having the first workload may be lower than that of the core110having the second workload. The performance of the core110may be dependent on the voltage-frequency level, and when the workload of the core110is classified as the first workload, the DVFS controller200may determine a scaling factor such that the voltage-frequency level decreases. Some example embodiments of this will be described later with reference toFIGS.6A and6B.

The DVFS controller200may generate a control signal based on the determined scaling factor. In some example embodiments, the DVFS controller200may generate a clock control signal C_clk for adjusting a frequency of the core110and transmit the clock control signal C_clk to the clock management unit300. In some example embodiments, the DVFS controller200may generate a voltage control signal C_vdd for adjusting the power supply voltage vdd of the core110, and transmit the voltage control signal C_vdd to the power management unit400.

As the DVFS controller200classifies the workload of the core110based on the buffer capacity and the response waiting time obtained by the monitor130monitoring the shared buffer120, the DVFS controller200may determine a scaling factor for a voltage-frequency level, differently according to the characteristics of the bus500or the memory600. Accordingly, power consumption may be reduced, for example, more efficiently or easily, compared when the workload is not classified, and overhead may be reduced because additional calculation is not required compared to when the workload is classified using software. Although the DVFS controller200is described as being located outside the processor100, the DVFS controller200may also be located inside the processor100. Alternatively, or additionally, as described above, the use of the scaling factor for a voltage-frequency level may have a positive effect on the circuit10, such as improved processing distribution and allocation, improved power usage, improved wear-and-tear on the device, etc.

The clock management unit300may generate a clock signal clk and adjust a frequency of the clock signal clk based on the clock control signal C_clk. For example, the clock management unit300may include an oscillator generating a clock signal clk based on the clock control signal C_clk. The clock management unit300may also be referred to as a clock generator or a clock generation circuit.

The power management unit400may generate the power supply voltage vdd and adjust an amplitude of the power supply voltage vdd based on the voltage control signal C_vdd. For example, the power management unit400may include a switching regulator that generates the power supply voltage vdd from a voltage provided from an external power source, based on the voltage control signal C_vdd. The power management unit400may also be referred to as a power management integrated circuit (PMIC).

The bus500may include a system bus to which a protocol having a certain standard bus standard is applied, and may include various Intellectual Property (IPs) connected to the system bus. As a standard specification of a system bus, an Advanced Microcontroller Bus Architecture (AMBA) protocol by Advanced RISC Machine (ARM) may be applied. Bus types of the AMBA protocol may include an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI), AXI4, and AXI Coherency Extensions (ACE). In addition, other types of protocols such as SONICs Inc.'s uNetwork, IBM's CoreConnect, and OCP-IP's Open Core Protocol may be applied. Although the bus500is described as being included inside the integrated circuit10, the bus500may be located outside the integrated circuit10.

The memory600may correspond to various types of semiconductor memory devices, and may include, according to some example embodiments, a dynamic random access memory (DRAM) such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and the like. Further, the memory600may be any one of a flash memory, a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), and a ferroelectric RAM (FeRAM). While the memory600is described as being included in the integrated circuit10, the memory600may be located outside the integrated circuit10and may be referred to as an external memory in this case.

The integrated circuit10may include components other than those illustrated inFIG.1. For example, the integrated circuit10may further include various types of functional blocks such as an input/output (IO) interface block, a universal serial bus (USB) host block, and a USB slave block.

FIG.2is a block diagram for describing a shared buffer and data monitored by a monitor, according to some example embodiments.

Referring toFIGS.1and2, the shared buffer120ofFIG.2may be the same as the shared buffer120ofFIG.1and may include a plurality of blocks121. Descriptions overlapping with those ofFIG.1will be omitted. In some example embodiments, at least one block121may constitute one set, and the shared buffer120may include a plurality of sets. A total capacity of the shared buffer120may be determined based on the plurality of sets. For example, a size of the block121may be B bytes (B is an integer greater than or equal to 0), one set may include N or more (N is an integer greater than or equal to 1) blocks121, and the shared buffer120may include M sets (M is an integer greater than or equal to 1). The total capacity of the shared buffer120may be determined as B*N*M bytes.

In some example embodiments, when a filled degree of the total capacity of the shared buffer120is greater than or equal to a threshold value, the DVFS controller200may classify the workload of the core110as a first workload. For example, when 70% or more of the total capacity of B*N*M bytes of the shared buffer120is filled, the DVFS controller200may classify the workload of the core110as the first workload.

In some example embodiments, each of the cores110may transmit a request Req only to a certain block among the plurality of blocks121. For example, the request Req may include data designating a location of a certain block among the plurality of blocks121.

In some example embodiments, the memory600may be classified into a plurality of regions (not shown), and each block121may access Acc only a certain region among the plurality of regions of the memory600. For example, the request Req received by the shared buffer120from the core110may include an address, and the address may include data designating a location of a certain region of the memory600.

FIGS.3A and3Bare graphs for describing a buffer capacity and a response standby time, according to some example embodiments.

Referring toFIGS.1and3A, the graph ofFIG.3Amay represent a capacity of the block121over time. In some example embodiments, when a number of blocks121in which the capacity of each block121is filled is greater than or equal to a threshold number, the buffer capacity of the shared buffer120may be labelled as full. For example, when the number of blocks121having a capacity filled to 70% (for example, a first threshold Th1) or more among the plurality of blocks121is 50% (for example, a threshold number of blocks) or more of the total number of blocks121, the buffer capacity of the shared buffer120may be in a full state. Sections in which the buffer capacity is full may be section C1and section C2.

Referring further toFIG.3B, the graph ofFIG.3Bmay represent a response waiting time for a response received by the shared buffer120from an external memory. In some example embodiments, the response waiting time for a response received from the external memory may include a period of time taken by the shared buffer120to receive a response Res from the memory600after accessing Acc the memory600via the bus500(hereinafter referred to as a response waiting time). When the shared buffer120accesses Acc the memory600through the bus500, a signal may transition from a first level (for example, logic low) to a second level (for example, logic high). When the shared buffer120receives a response Res from the memory600through the bus500, the signal may transition from the second level to the first level. A period of time taken from a transition of the signal from the first level to the second level to the transition from the second level to the first level (for example, time a1, time a2, time a3, or time b1) may be a response waiting time.

In some example embodiments, when the buffer capacity of the shared buffer120indicates a full state, and the response waiting time is longer than a threshold time Th2, the DVFS controller200may classify a workload of the core110as a first workload among the first workload and a second workload. The first workload may include more requests for accessing an external memory than the second workload. For example, a state in which the buffer capacity of the shared buffer120is full may be the section C1and the section C2. The time a1, the time a2, and the time a3may correspond to a period of time in which the response waiting time is longer than the threshold time Th2. At a point in time T1, the buffer capacity of the shared buffer120may indicate a full state, and the response waiting time may be longer than the threshold time Th2. At a point in time T2, the response waiting time is longer than the threshold time Th2, but the buffer capacity of the shared buffer120may not be in a full state. Accordingly, congestion may occur in the bus500or the memory600in a section from the point in time T1to the point in time T2, and the DVFS controller200may classify the workload of the core110as the first workload.

In some example embodiments, the monitor130may monitor the shared buffer120and obtain an identifier (source ID). The identifier (source ID) may refer to an address of the core110that transmits the request Req to the shared buffer120, and the DVFS controller200may receive the identifier (source ID) from the monitor130. In the section from the point in time T1to the point in time T2, the DVFS controller200may identify a certain core among the plurality of cores110according to an identifier (source ID), and classify a workload of the identified core as a first workload.

FIG.4is a block diagram illustrating some example embodiments of an integrated circuit according to some example embodiments.

Referring toFIGS.1and4, an integrated circuit10amay include the processor100, the DVFS controller200and a temperature sensor800. In some example embodiments, the processor100and the DVFS controller200ofFIG.4may be the same as the processor100and the DVFS controller200ofFIG.1, respectively. Descriptions overlapping with those ofFIG.1will be omitted.

The temperature sensor800may sense a temperature of the processor100and provide temperature information according to a sensing result, to the DVFS controller200. The temperature sensor800may include a thermistor and a memory (not shown) capable of storing temperature information. In some example embodiments, the temperature sensor800may sense the temperature of the cores110. Temperature information according to a sensing result may be provided to the DVFS controller200and stored in a memory.

Referring further toFIGS.3A and3B, in some example embodiments, when the buffer capacity of the shared buffer120is not full, or the response waiting time is less than the threshold time Th2, the DVFS controller200may classify the workload of the core110as the second workload among the first workload and the second workload, based on the temperature information. The first workload may include more requests for accessing an external memory than the second workload. For example, the buffer capacity may not be full in sections other than the section C1and the section C2. In the section C1, the buffer capacity is full, but the response waiting time (for example, time b1) may not exceed the threshold time Th2. In a section C3, the buffer capacity is full, but the response waiting time may not exceed the threshold time Th2. Accordingly, in the section before the point in time T1or after the point in time T2, the buffer capacity of the shared buffer120may not be full or the response waiting time may be less than the threshold time Th2. In the section before the point in time T1or after the point in time T2, when temperature information sensed by the temperature sensor800is equal to or greater than a threshold temperature, for example, may be a situation where the core110operates excessively to process an instruction, or a situation where no cache miss occurs during the operation of the processor100. Accordingly, the DVFS controller200may classify the workload of the core110as the second workload.

In some example embodiments, the monitor130may monitor the shared buffer120and obtain an identifier (source ID). The identifier (source ID) may refer to an address of the core110that transmits the request Req to the shared buffer120, and the DVFS controller200may receive the identifier (source ID) from the monitor130. In the section before the point in time T1or after the point in time T2, the DVFS controller200may identify a certain core among the plurality of cores110according to an identifier (source ID), and classify the workload of the identified core as the second workload.

FIG.5is a block diagram illustrating some example embodiments of an integrated circuit according to some example embodiments.

Referring toFIGS.1and5, an integrated circuit10bmay include a DVFS controller200a, the clock management unit300, the power management unit400, and a memory700. In some example embodiments, the clock management unit300and the power management unit400ofFIG.5may be the same as the clock management unit300and the power management unit400ofFIG.1, respectively. Descriptions overlapping with those ofFIG.1will be omitted.

The DVFS controller200amay include a workload classification logic210, a DVFS governor module220, a clock management unit driver230, and a power management unit driver240. The workload classification logic210may receive, from the monitor130, an address of the core110that transmits a request Req from the monitor130to the shared buffer120(hereinafter referred to as an identifier), the buffer capacity of the shared buffer120, and a response waiting time for a response received from an external memory. The workload classification logic210may identify a certain core among the plurality of cores110according to the identifier and classify a workload of the certain core based on the buffer capacity and the response waiting time. Classified workload data of the certain core may be transmitted to the DVFS governor module220. For example, the workload classification logic210may classify the workload of the core110as a first workload or a second workload based on the buffer capacity and the response waiting time, and the first workload may include more requests for accessing an external memory than the second workload. The workload classification logic210may classify the workload of a certain core as the first workload when the buffer capacity is full and the response waiting time is longer than the threshold time, and transmit, to the DVFS governor module220, data indicating that the certain core is classified as the first workload.

The DVFS governor module220may determine a scaling factor for a voltage-frequency level based on the classified workload data of a certain core. In some example embodiments, when the DVFS governor module220receives data indicating that a certain core is classified as the first workload, the DVFS governor module220may obtain, from the memory700, a DVFS table710including a power supply voltage vdd and a frequency of a clock signal clk, which correspond to the first workload. The DVFS governor module220may determine a scaling factor for the voltage-frequency level based on the power supply voltage vdd and the clock signal clk corresponding to the first workload.

As described above, there may be an effect of improving power consumption of the circuit10bby determining a scaling factor for the voltage-frequency level, for example, during a lower needs or slower period, and/or an effect of improving processing capability by determining a scaling factor for the voltage-frequency level, for example, during a higher needs or intensive period.

Hereinafter, a module may refer to hardware capable of performing functions and operations according to each name, or may refer to computer program code capable of performing specific functions and operations. However, the inventive concepts are not limited thereto and may refer to an electronic recording medium, for example, a processor, in which a computer program code capable of performing specific functions and operations is loaded. That is, a module may refer to a functional and/or structural combination of software for carrying out the inventive concepts.

The clock management unit driver230may generate a clock control signal C_clk based on a scaling factor determined by the DVFS governor module220and provide the clock control signal C_clk to the clock management unit300.

The power management unit driver240may generate a power supply voltage control signal C_vdd based on the scaling factor determined by the DVFS governor module220and provide the power supply voltage control signal C_vdd to the power management unit400.

The memory700may include the DVFS table710. In some example embodiments, the DVFS table710may include a power supply voltage vdd and a frequency of a clock signal clk corresponding to each workload. The DVFS table710may include values that are hard-coded in the memory700or soft-coded and modifiable values. Modification of the DVFS table710may be performed by the DVFS governor module220. Although one DVFS table710is illustrated inFIG.5, a plurality of DVFS tables710may also be included. For example, a plurality of DVFS tables710may be created according to a buffer capacity, a response waiting time, and a workload.

FIGS.6A and6Bare, respectively, a graph and a table for describing a DVFS controller capable of determining a scaling factor, according to some example embodiments.

Referring toFIGS.1and6A, the graph ofFIG.6Amay indicate a relationship between performance and power consumption of the core110. Power consumption P may satisfy Mathematical Expression 1 below.

V may refer to a power supply voltage, and f may refer to a frequency of the core110. The power consumption P may be proportional to the square of a power supply voltage V and may be proportional to a frequency f of the core110, and thus, the higher the power supply voltage V or the frequency f of the core110, the greater the power consumption P may be. The performance of the core110may be dependent on a voltage-frequency level. For example, as the amplitude of the power supply voltage V increases and the frequency f of the core110increases, the core110may operate faster, thus improving the performance of the core110. Accordingly, the power consumption P and the performance of the core110may have a proportional relationship to each other.

Referring further toFIGS.5and6B, the workload classification logic210may classify the workload of the core110as a first workload or a second workload, and the DVFS governor module220may determine a scaling factor for a voltage-frequency level, based on the classified workload of the core110. The table ofFIG.6Bmay be the DVFS table710ofFIG.5. In some example embodiments, when the DVFS governor module220receives data w1indicating that the workload of the core110is classified as the first workload, the DVFS governor module220may obtain, from the memory700, the DVFS table710including a power supply voltage v1and a frequency f1of a clock signal. The DVFS governor module220may determine a scaling factor for the voltage-frequency level based on the power supply voltage v1and the frequency f1of the clock signal. For example, the first workload may be a memory intensive workload, and the memory intensive workload may indicate a situation in which congestion occurs in the bus500or the memory600when a cache miss occurs during operation of the processor100. When congestion occurs in the bus500or the memory600, the congestion may be resolved by adjusting a number of requests Req by lowering the performance of the core110, and since the performance of the core110is proportional to power consumption, power consumption may be reduced. Accordingly, the DVFS governor module220may determine a scaling factor such that the voltage-frequency level decreases, based on the power supply voltage v1and the frequency f1of the clock signal.

In some example embodiments, referring further toFIG.4, when the temperature information detected by the temperature sensor800is equal to or greater than the threshold temperature, the DVFS governor module220may receive data w2indicating that the workload of the core110is classified as the second work load, and obtain, from the memory700, the DVFS table710including a power supply voltage v2and a frequency f2of a clock signal. For example, the second workload may be a computing workload, and the computing workload is related to instruction processing of the core110, and may refer to a situation in which a cache miss does not occur during an operation of the processor100. In a situation where a cache miss does not occur, the number of requests Req may not be adjusted by lowering the performance of the core110, unlike for a workload classified as the first workload. However, when a temperature of the core110is equal to or higher than the threshold temperature, increasing the performance of the core110may cause a malfunction due to heat generation of the core110, and this may lower the temperature of the core110. Accordingly, the DVFS governor module220may determine a scaling factor such that the voltage-frequency level decreases, based on the power supply voltage v2and the frequency f2of the clock signal.

The DVFS table710may include a power supply voltage and a frequency of a clock signal according to data other than the illustrated data (w1or w2). For example, when the temperature information detected by the temperature sensor800is less than the threshold temperature, the DVFS governor module220may receive data (not shown) indicating that the workload of the core110is classified as the second workload, and obtain, from the memory700, the DVFS table710including a power supply voltage (not shown) and a clock signal frequency (not shown). The second workload may include a computing workload, and the core110may require high performance to process instructions. As the temperature of the core110is less than the threshold temperature, the increase in the performance of the core110may not cause a malfunction due to heat generation. Accordingly, the DVFS governor module220may determine a scaling factor such that the voltage-frequency level increases, based on the power supply voltage (not shown) and the frequency (not shown) of the clock signal.

As the power consumption P and the performance of the core110may be in a proportional relationship to each other, the DVFS governor module220may differently determine a scaling factor according to a workload of the core110, and improve or efficiently manage power consumption and the performance of the core110.

FIG.7is a block diagram illustrating some example embodiments of an integrated circuit according to some example embodiments.

Referring toFIGS.1and7, an integrated circuit10cmay include at least one processor100and a DVFS controller200b. In some example embodiments, the processor100ofFIG.7may be identical to the processor100ofFIG.1. Descriptions overlapping with those ofFIG.1will be omitted.

The DVFS controller200bmay include at least one processor280, a memory250, an artificial intelligence (AI) accelerator260, and a hardware accelerator270. The at least one processor280may execute instructions. For example, the at least one processor280may execute an operating system by executing instructions stored in the memory250, and execute applications executed on the operating system. In some example embodiments, by executing instructions, the at least one processor280may direct a task to the AI accelerator260and/or the hardware accelerator270, and may obtain, from the AI accelerator260and/or the hardware accelerator270, a result of performing the task. In some example embodiments, the at least one processor280may be an application specific instruction set processor (ASIP) customized for a specific purpose and may support a dedicated instruction set.

The memory250may have any structure for storing data. For example, the memory250may include a volatile memory device such as DRAM and static random access memory (SRAM), or a non-volatile memory device such as flash memory and/or resistive random access memory (RRAM).

The AI accelerator260may refer to hardware designed for AI applications. In some example embodiments, the AI accelerator260may include a Neural Processing Unit (NPU) for implementing a neuromorphic structure, and may generate output data by processing input data provided by the at least one processor280and/or the hardware accelerator270, and provide the output data to the at least one processor280and/or the hardware accelerator270. In some example embodiments, the AI accelerator260may be programmable and may be programmed by the at least one processor280and/or the hardware accelerator270.

The hardware accelerator270may refer to hardware designed to perform a specific task at high speed. High speed may refer to performing the specific task in less time/cycles than a non-designed (e.g., generic) hardware performing the specific task. For example, the hardware accelerator270may be designed to perform data conversion such as demodulation, modulation, encoding, and decoding at high speed. The hardware accelerator270may be programmable and may be programmed by the at least one processor280and/or the hardware accelerator270.

In some example embodiments, the AI accelerator260may execute an artificial neural network model. For example, with further reference toFIG.1, the memory250may store training data. The training data may include a buffer capacity and a response waiting time obtained by monitoring the shared buffer120, by the monitor130, and include a scaling factor determined by the DVFS controller200based on the buffer capacity and the response waiting time. The AI accelerator260may execute an artificial neural network model, and the processor280may train the artificial neural network model by using the training data. After the training of the artificial neural network model is completed, the processor280may receive the buffer capacity and the response waiting time from the monitor130. When the received buffer capacity and response waiting time correspond to the buffer capacity and the response waiting time stored in the memory250, a scaling factor corresponding to the buffer capacity and the response waiting time may be determined using the trained artificial neural network model. After the artificial neural network model is trained, the DVFS controller200may determine a scaling factor without classifying the workload of the core110and generate a clock control signal and a voltage control signal, for example, more quickly than without the classification.

In some example embodiments, the training data may include an address, and the processor280may use the training data including the address, to train an artificial neural network model. For example, a request Req received by the shared buffer120from the core110may include an address, and the address may include data designating a location of a certain region a of the memory600. After training of the artificial neural network model is completed, the processor280may receive an address from the monitor130, and determine a scaling factor corresponding to the address. The training data may further include other data than the data described above.

FIG.8is a flowchart of an operating method of an integrated circuit, according to some example embodiments. As illustrated inFIG.8, an operating method900of an integrated circuit may include a plurality of operations S110to S150.

Referring toFIGS.1and8, in operation S110, the shared buffer120is monitored, and the buffer capacity of the shared buffer120and the response wait time for the response received by the shared buffer120from the external memory may be obtained. In some example embodiments, the buffer capacity of the shared buffer120may represent a filled state of the capacity of the plurality of blocks121, and a response waiting time for a response received from an external memory may be a period of time taken by the shared buffer120to receive a response Res from the memory600after accessing Acc the memory600through the bus500.

In operation S130, the workload of the core110may be classified based on the buffer capacity and the response waiting time. In some example embodiments, when the buffer capacity and the response waiting time are equal to or greater than a threshold values, the DVFS controller200may classify the workload of the core110as the first workload. If the buffer capacity or the response waiting time is less than the threshold value, the DVFS controller200may classify the workload of the core110as the second workload. In some example embodiments, a temperature of the core110may be used in classifying the workload of the core110.

In operation S150, a scaling factor for a voltage-frequency level of the core110may be determined based on the classified workload of the core110. In some example embodiments, when the workload of the core110is classified as the first workload, the scaling factor may be determined such that a voltage-frequency level decreases. When the workload of the core110is classified as the second workload, the scaling factor may be determined such that a voltage-frequency level increases. In some example embodiments, a temperature of the core110may be used in determining the scaling factor for a voltage-frequency level of the core110.

FIG.9is a flowchart of some example embodiments of an operating method of an integrated circuit, according to some example embodiments. Operation S130ofFIG.8may include some example embodiments of the operating method of the integrated circuit ofFIG.9. Some example embodiments of the operating method of the integrated circuit (S130) may include a plurality of operations S131to S135.

Referring toFIGS.1and9, some example embodiments of the operating method of an integrated circuit (S130) may indicate that the DVFS controller200operates in one of three modes. In operation S131, it may be determined whether the buffer capacity is full and whether the response waiting time is longer than the threshold time Th2. When the buffer capacity is full and the response waiting time is longer than the threshold time Th2, the DVFS controller200may operate in a memory intensive workload mode in operation S132. For example, in the memory intensive workload mode, the DVFS controller200may classify the workload of the core110as a memory intensive workload and determine a scaling factor such that the voltage-frequency level decreases.

When the buffer capacity is not full and/or the response waiting time is shorter than the threshold time Th2, the DVFS controller200may receive, from the temperature sensor ofFIG.4, temperature information T of the core110. When the temperature information T of the core110is higher than a threshold temperature th3, the DVFS controller200may operate in a computing workload mode in operation S134. For example, in the computing workload mode, the DVFS controller200may classify the workload of the core110as a computing workload and determine a scaling factor such that the voltage-frequency level decreases. When the temperature information T of the core110is not higher than the threshold temperature th3, the DVFS controller200may operate in a normal workload mode in operation S135. For example, in the normal workload mode, the DVFS controller200may classify the workload of the core110as a normal workload, and may determine a scaling factor such that the voltage-frequency level increases.

Since the operation mode of the DVFS controller200is changed according to the buffer capacity and the response waiting time, and the scaling factor is determined differently according to the operation mode, power consumption may be adjusted as needed. For example, a scaling factor determined by the DVFS controller200when operating in the memory intensive workload mode, may be a scaling factor that further reduces the voltage-frequency level than a scaling factor determined by the DVFS controller200when operating in the computing workload mode.

FIG.10is a flowchart of some example embodiments of an operating method of an integrated circuit, according to some example embodiments. As illustrated inFIG.10, some example embodiments1000of an operating method of an integrated circuit may include a plurality of operations S210to S250.

Referring toFIGS.7and10, in operation S210, the memory250may store training data. In some example embodiments, the memory250may receive and store training data from the monitor130. The training data may include a buffer capacity and a response waiting time obtained by monitoring the shared buffer120by the monitor130, and include a scaling factor determined by the DVFS controller200based on the buffer capacity and the response waiting time.

In operation S230, an artificial neural network model may be trained using the training data. In some example embodiments, the AI accelerator260may execute an artificial neural network model, and the processor280may train the artificial neural network model by using the training data.

After training is completed in operation S250, the processor280may determine a scaling factor corresponding to the buffer capacity and the response waiting time received from the monitor. In some example embodiments, the processor280may receive the buffer capacity and the response waiting time from the monitor130. When the received buffer capacity and response waiting time correspond to the buffer capacity and the response waiting time stored in the memory250, a scaling factor corresponding to the buffer capacity and the response waiting time may be determined using the trained artificial neural network model. After the artificial neural network model is trained, the DVFS controller200may determine a scaling factor without classifying the workload of the core110, and generate a clock control signal and a voltage control signal, for example, more quickly than without the classification.

FIG.11is a block diagram illustrating a system according to some example embodiments.

Referring toFIG.11, a system30may be implemented as a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), and/or a handheld device such as a handheld game console, or an e-book.

The system30may include a SoC3100and a memory device3200. The SoC3100may include a central processing unit (CPU)3110, a graphics processing unit (GPU)3120, a neural processing unit (NPU)3130, an image signal processor (ISP)3140, a memory interface (MIF)3150, a CMU3160, and a PMU3170. The CPU3110, the GPU3120, the NPU3130, the ISP3140, and the MIF3150may be some example embodiments of the integrated circuit10described above with reference toFIGS.1to10. Accordingly, the CPU3110, the GPU3120, the NPU3130, the ISP3140, and the MIF3150may each include the monitor130and the DVFS controller200, and the DVFS controller200may perform a DVFS operation based on the buffer capacity and the response waiting time monitored by the monitor130.

The CPU3110may process or execute commands and/or data stored in the memory device3200in response to a clock signal generated by the CMU3160.

The GPU3120may acquire image data stored in the memory device3200in response to a clock signal generated by the CMU3160. The GPU3120may generate data for an image output through a display device (not shown), from image data provided from the MIF3150, or encode the image data.

The NPU3130may refer to any device that runs a machine learning model. The NPU3130may include a hardware block designed to run a machine learning model. The machine learning model may include a model based on an artificial neural network, a decision tree, a support vector machine, regression analysis, Bayesian network, genetic algorithm, and/or the like. Non-limiting examples of the artificial neural network may include a convolution neural network (CNN), a region with convolution neural network (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), a stacking-based deep neural network (S-DNN), a state-space dynamic neural network (S-SDNN), a deconvolution network, a deep belief network (DBN), a restricted Boltzmann machine (RBM), a fully convolutional network, a long short-term memory (LSTM) network, and a classification network.

The ISP3140may perform a signal processing operation on raw data received from an image sensor (not shown) located outside the SoC3100and generate digital data having improved image quality.

The MIF3150may provide an interface to the memory device3200located outside the SoC3100. The memory device3200may include DRAM, PRAM, ReRAM, or flash memory.

The CMU3160may generate a clock signal and provide the clock signal to components of the SoC3100. The CMU3160may include a clock generator such as a Phase Locked Loop (PLL), a Delayed Locked Loop (DLL), and/or a crystal oscillator. The PMU3170may convert external power to internal power and supply power to the components of the SoC3100from the internal power.

FIG.12is a block diagram illustrating a communication device including an application processor, according to some example embodiments.

Referring toFIG.12, a communication device40may include an application processor4010, a memory device4020, a display4030, an input device4040, and a radio transceiver4050. The application processor4010may be some example embodiments of the integrated circuit10described above with reference toFIGS.1to11.

The radio transceiver4050may transmit or receive a radio signal through an antenna4060. For example, the radio transceiver4050may change a wireless signal received through the antenna4060into a signal that may be processed by the application processor4010.

Accordingly, the application processor4010may process a signal output from the radio transceiver4050and transmit the processed signal to the display4030. In addition, the radio transceiver3250may change a signal output from the application processor4010, into a wireless signal, and output the wireless signal to an external device through the antenna4060.

The input device4040may include a device capable of inputting a control signal for controlling the operation of the application processor4010or data to be processed by the application processor4010, and may be implemented as a pointing device such as a touch pad or a computer mouse, or a keypad or a keyboard.

Here, the application processor4010may further include the monitor130and the DVFS controller200according to some example embodiments, and the DVFS controller200may perform a DVFS operation based on the buffer capacity and the response waiting time monitored by the monitor130.

Although not illustrated inFIG.12, the communication device40may further include a clock management unit providing clock signals to various components and a power management unit providing a power supply voltage.

By using the integrated circuit10according to the inventive concepts as described above, a workload of a core may be classified, and a scaling factor for a voltage-frequency level may be determined based on the classified workload, and thus, power consumption may be improved or efficiently controlled as needed.

As described herein, any electronic devices and/or portions thereof according to any of the example embodiments may include, may be included in, and/or may be implemented by one or more instances of processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or any combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an Electronic Control Unit (ECU), an Image Signal Processor (ISP), and the like. In some example embodiments, the processing circuitry may include a non-transitory computer readable storage device (e.g., a memory), for example a DRAM device, storing a program of instructions, and a processor (e.g., CPU) configured to execute the program of instructions to implement the functionality and/or methods performed by some or all of any devices, systems, modules, units, controllers, circuits, architectures, and/or portions thereof according to any of the example embodiments, and/or any portions thereof.