Fast debugging tool for CRC insertion in MPEG-2 video decoder

A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

BACKGROUND

I. Field of the Invention

The present invention relates to the field of video signal processing, and more particularly to a video decoder debugging system and method thereof.

II. Background of the Invention

Digital video has become common in the field of consumer electronics, due in large part to the emergence of digital video standards such as MPEG-1, MPEG-2 and MPEG-4. The challenging of a video decoder technology is to design a decoder that can precisely decode the bitstream data and send to the display engine for viewing.

If an error happened during the decoding process, the video decoder will not be able to deliver a correct picture frame to the display. A debugger must find the error data path and fix the error in a short time in order to meet users' need.

InFIG. 1, a schematic diagram illustrates a conventional video decoder functional blocks that decode multimedia bitstream data.

As shown, the conventional video decoder system100includes a header parser101, a bitstream buffer102, a variable length decoder (VLD)103, an inverse discrete Cosine transform (IDCT)104, a motion compensation (MC)105, an address translation and arbiter106, a reconstruction107and a video decoder controller (VDEC)108. The VDEC controller108issues control signals to regulate the operation of the above-mentioned functional blocks. The address translation and arbiter106connects to a traffic controller120and the traffic controller120further connects to a storage device130, e.g., double data rate dynamic random access memory (DDR). The address translation and arbiter106also connects to the bitstream buffer102and the motion compensation105. The bitstream buffer102connects to the header parser101and the variable length decoder (VLD)103. The header parser101connects to the variable length decoder (VLD)103and the address translation and arbiter106. The variable length decoder (VLD)103connects to the inverse discrete Cosine transform (IDCT)104and the motion compensation105. The inverse discrete Cosine transform (IDCT)104and the motion compensation105connect to the reconstruction107. The reconstruction107connects to the address translation and arbiter106.

An encoded bitstream data is fetched from the DDR130via the traffic controller120by the address translation and arbiter106and put into the bitstream buffer102. The encoded bitstream data is then sent to the header parser101for parsing system information and such system information is sent back to DDR130via the address translation and arbiter106for the use of CPU or VDEC controller108. The bitstream buffer102sends the bitstream data to VLD103for parsing data information with reference to the information provided by header parser101. VLD103sends the motion vector to TDCT104and MC105. The TDCT104will generate a spatial domain difference. MC105will fetch a reference frame from the DDR130with reference to the motion vector provided by VLD103. Both the output of IDCT104and MC105will be sent to reconstruction107and have a decoded frame. The traffic controller120further connects to a reduced instruction set computer (RISC)140for additional data computing, an audio decoder150for audio signal decoding and a display engine160for displaying the decoded video bitstream data.

However, it is difficult to locate the error data path during the decoding process because: (1) The debugger needs to dump the decoded frame buffer, which is a huge size of data, from the external DRAM to compare with the golden data, and (2) the debugger needs to rely on the logic analyzer to trace all the possible signals which cost a lot of time and equipments.

Therefore, there is a need for an alternative video decoder structure featuring a debugging functional block design that can improve the above-mentioned drawbacks.

SUMMARY OF THE INVENTION

Systems, methods, and apparatuses for an improved video decoder debugging tool are disclosed. In order to overcome the disadvantages of the conventional system and method, the present invention provides an improved video decoder debugging tool that inserts a cyclic redundancy check (CRC) logic in a MPEG-2 video decoder. Such improvement features a new structure of functional blocks capable of quickly identifying data path errors. In one aspect, a video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes: (1) a plurality of functional blocks, wherein each said plurality of functional blocks has an output signal to be used as an input signal for a next stage functional block; (2) a multiplexer that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and (3) a check logic that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

In another aspect, a video decoder debugging system is disclosed. The video decoder debugging system includes: (1) a plurality of functional blocks, wherein each said plurality of functional blocks couples to a next stage functional block with a data path; (2) a multiplexer that receives a plurality of data extracted from said data path of each said plurality of functional blocks; (3) a check logic operably coupled to an output signal of said multiplexer and calculates said output signal of said multiplexer; and (4) a controller that stores a result that compares a golden data against a calculation result of said check logic.

In still another aspect, a method of debugging a video decoder system is disclosed. The method comprises the following steps: (1) a plurality of input signals is provided to a multiplexer; (2) a first control signal is issued from a controller to said multiplexer; (3) one of said plurality of input signals is allowed to pass through said multiplexer; (4) a check logic calculates said input signal and further generates a calculation result; (5) a golden data is compared to said calculation result and said check logic further generate a comparison result; and (6) the comparison result is stored to said controller.

Some advantages of the present invention are: (1) prompt identification of errors without the need to dump all external data from external DRAM; (2) insertion of a check logic such as cyclic redundancy check (CRC) logic provides a fast debugging tool for the MPEG-2 video decoder; and (3) recognition of the data path problems made easier by adding some mode selection codes in the decoder, which can help the debugger to locate errors without using a logic analyzer. These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.”

DETAILED DESCRIPTION

While the invention is described here in terms of embodiments, the invention is not intended to be limited to just those embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the appended claims. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. As is obvious to one of ordinary skilled in the art, the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so that the essence of the invention will not be obscured.

One embodiment of the present invention discloses a video decoder capable of generating a check data in response to a data selection code for debugging. The present invention features a new functional blocks structure capable of effectively identifying data path errors. The proposed video decoder debugging functional blocks comprise a multiplexer and a cycling redundancy check logic.

Embodiment

InFIG. 2, a schematic diagram that illustrates a video decoder featuring debugging functional blocks with debugging capability in accordance with one embodiment of the present invention is shown.

According toFIG. 2, the proposed video decoder system200includes: (1) a plurality of functional blocks, wherein each said plurality of functional blocks has an output signal to be used as an input signal for a next stage functional block; (2) a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and (3) a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

The proposed video decoder system200further comprises a header parser201, a bitstream buffer202, a variable length decoder (VLD)203, an inverse discrete Cosine transform (IDCT)204, a motion compensation (MC)205, an address translation and arbiter206, a reconstruction207, a video decoder controller (VDEC)208, a multiplexer209and a check logic210, e.g., cycling redundancy check (CRC) logic. The VDEC controller208issues control signals to regulate the operation of the above-mentioned functional blocks. The address translation and arbiter206connects to a traffic controller220and the traffic controller220further connects to a storage device230, e.g., double data rate dynamic random access memory (DDR). The address translation and arbiter206further connects to the bitstream buffer202and the motion compensation205. The bitstream buffer202connects to the header parser201and the variable length decoder (VLD)203. The header parser201connects to the variable length decoder (VLD)203and the address translation and arbiter206. The variable length decoder (VLD)203connects to the inverse discrete Cosine transform (IDCT)204and the motion compensation205. The inverse discrete Cosine transform (IDCT)204and the motion compensation205connect to the reconstruction207. The reconstruction207connects to the address translation and arbiter206.

There are four data paths which will exchange data with external DRAM. They are header raw data (HD), bitstream buffer (BU), motion compensation (MC) and reconstruction (RC). These four data paths are also coupled to the multiplexer209. The VDEC controller208issues a RC Combine Mode signal to the reconstruction207and a data selection signal to the multiplexer209. The output of the multiplexer209is coupled to the check logic210.

An encoded bitstream data is fetched from the DDR230via the traffic controller220by the address translation and arbiter206and put into the bitstream buffer202. The encoded bitstream data is then sent to the header parser201for parsing system information and such system information is sent back to DDR230via the address translation and arbiter206for the use of CPU or VDEC controller208. The bitstream buffer202sends the bitstream data to VLD203for parsing data information with reference to the information provided by header parser201. VLD203sends the motion vector to IDCT204and MC205. The IDCT204will generate a spatial domain difference. MC205will fetch a reference frame from the DDR230with reference to the motion vector provided by VLD203. Both the output of IDCT204and MC205will be sent to and processed through reconstruction207to obtain a decoded frame.

To ensure the correctness of the decoded frame, the VDEC controller208can select which path is calculated by the check logic210by issuing a data selection signal to the multiplexer209with a corresponding code, e.g., 00 (RC), 01 (MC), 10 (BU) and 11 (HD). For the reconstruction path (RC), the RC combine mode signal is used to split the IDCT204and MC205data with a corresponding code, e.g., 00 (IDCT+MC), 01 (IDCT only), 10 (MC only), 11 (picture coding type). At picture coding type, if the data is I/D encoding, the data will go through IDCT204. If the data is P/B encoding, the data will go through MC205. The calculation result of the check logic210of the selected path is stored within the controller208. The CPU will compare the calculation result with a corresponding reference data and generate a comparison result. If the comparison result is matched, the decoded frame is correct. If the comparison result is not matched, the decoded frame is incorrect. The multiplexer209can select data outputted from each of the functional blocks in a sequential manner for computation by the check logic210, such that the debugger can look at each specific data path and accurately locate the problem. The check logic is a cyclic redundancy check (CRC) logic comprising a hash function such as a polynomial 1+x2+x15x16.

The advantages of the embodiment of the present invention which have been described in the above paragraphs are as follows: (1) prompt identification of errors without the need to dump all external data from external DRAM; (2) insertion of a check logic such as cycling redundancy check (CRC) logic provides a fast debugging tool for MPEG-2 video decoder; (3) recognition of the data path problem made easier by adding some mode selection codes in the decoder which can help the debugger to locate errors without using a logic analyzer.

Although the embodiment of the invention is illustrated by a video decoder, it is not intended to limit thereto. Other types of decoder system can be implemented.

While the invention has been described with reference to one illustrative embodiment, the description is not intended to be construed in a limiting sense. The appended claims will cover any modifications or embodiments as may fall within the scope of the present invention.