Method for forming interlevel dielectric layer in semiconductor device using electron beams

A method for stabilizing an interlevel dielectric layer formed by a chemical vapor deposition (CVD) process, using electron beams. A CVD oxide layer is formed on a semiconductor substrate. The CVD oxide layer is radiated with electron beams at a temperature of between approximately room temperature and approximately 500.degree. C. for a predetermined time, using an electron beam radiator, to densify the layer.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a method for manufacturing a semiconductor 
device, and more particularly, to a method for stabilizing an interlevel 
dielectric layer. 
2. Description of the Related Art 
In general, as semiconductor devices become more integrated, the steps on 
such semiconductor substrates become larger. The steps cause diffused 
reflection during a photolithography process, and thus a desired pattern 
may not be obtained. An interlevel dielectric layer having a high degree 
of planarization is therefore desirable. 
Also, the planarization of the interlevel dielectric layer improves step 
coverage of a conductive layer to be formed thereon and allows the use of 
a wider range of thicknesses and line widths of underlying conductive 
layers. 
A phospho-silicate glass (PSG) layer, a boro-phospho-silicate glass (BPSG) 
layer and an undoped silicate glass (USG) layer, which are formed by a CVD 
process, are typically used for the interlevel dielectric layer. Since 
these layers are porous in comparison with a thermal oxide film, 
humidification can occur in these layers during subsequent processes. When 
these humidified layers are used for the interlevel dielectric layer, hot 
carriers are degraded by --OH groups in the interlevel dielectric layer, 
thereby deteriorating the reliability of the semiconductor device. Also, 
the dielectric constant of an interlevel dielectric layer increases 
proportional to humidity, which causes delayed signal transmission or 
noise. 
Also, a chemical mechanical polishing (CMP) process, which is widely used 
as a global planarization method, may be adapted to planarize an 
interlevel dielectric layer. Humidification after the CMP process may 
increase if the interlevel dielectric layer is not hard enough. In 
addition, defects such as scratches can occur during the CMP process. 
Conventionally, an interlevel dielectric layer is first formed, and then 
cured with high temperature treatment of 800.degree. C. or more to prevent 
humidification of the interlevel dielectric layer. A semiconductor memory 
device with a storage capacity of 256 Mb or more employs a dielectric 
material having a high dielectric constant such as TaO or BST. When a 
dielectric material layer having a high dielectric constant is formed on a 
semiconductor substrate, the semiconductor substrate can not tolerate the 
high temperature heat treatment. 
Accordingly, a need exists for a method to prevent humidification in a low 
temperature process. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a method for forming an 
interlevel dielectric layer in a semiconductor device in which a 
low-humidity interlevel dielectric layer is formed by a low temperature 
process. 
To accomplish the above object, a CVD oxide layer is formed on a 
semiconductor substrate. The CVD oxide layer is densified by radiating it 
with electron beams at a temperature of between approximately room 
temperature and approximately 500.degree. C. for a predetermined time. 
Before forming the CVD oxide layer, a conductive layer pattern may be 
formed on an insulating layer over a semiconductor substrate. And the step 
of forming a first capping layer covering the conductive layer pattern can 
be further included. Here, the CVD oxide layer is formed on this resultant 
structure. 
After radiating the CVD oxider layer with electron beams, the CVD oxide 
layer may be planarized. The planarized CVD oxide layer is radiated with 
electron beams at a temperature of between approximately room temperature 
and approximately 500.degree. C. for a predetermined time, using an 
electron beam radiator. 
After radiating the planarized CVD oxide layer, a second capping layer may 
be formed on the planarized layer. The second capping layer may also be 
radiated with electron beams at a temperature of between approximately 
room temperature and approximately 500.degree. C. for a predetermined 
time. 
Also, according to another method embodiment for forming an interlevel 
dielectric layer, a CVD oxide layer is formed on a semiconductor 
substrate. The CVD oxide layer is planarized through a CMP process. The 
planarized CVD oxide layer is densified by being radiated with electron 
beams at a temperature of between approximately room temperature and 
approximately 500.degree. C. for a predetermined time. 
According to still embodiment of the invention, a capping layer composed of 
an oxide layer is formed on the planarized oxide layer by a CVD process. 
The capping layer is radiated with electron beams at a temperature of 
between approximately room temperature and approximately 500.degree. C. 
for a predetermined time to density the layer. 
According to the present invention, moisture absorbed into an interlevel 
dielectric oxide layer during a CVD process can be effectively removed, 
and the possibility of humidification in the interlevel dielectric layer 
during subsequent processes may be effectively prevented by using a low 
temperature process.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
According to the present invention, the electron beams radiate an 
interlevel dielectric layer formed by a chemical vapor deposition (CVD) 
process under predetermined conditions at a relatively low temperature to 
density the interlevel dielectric layer. By that process, moisture 
absorbed into the interlevel dielectric layer is greatly reduced, and the 
humidification of the interlevel dielectric layer can be prevented in 
subsequent processes. 
In FIG. 1, plot (a) is absorptive when a BPSG layer is not radiated with 
electron beams after deposition, and plot (b) is not absorptive the BPSG 
layer is radiated with electron beams to density it. As shown in FIG. 1, a 
spectroscopic peak is shown at around 3000.about.3700 cm.sup.-1 in plot 
(a). Such a peak, however, is not shown in plot (b) thus indicating that 
the moisture present in the BPSG film after deposition is substantially 
removed by electron beam radiation. Furthermore, it has been found that 
moisture absorption is greatly reduced in the radiated BPSG film during 
subsequent processes. 
FIG. 2 is a graph showing dielectric constants before and after electron 
beams radiate the layers formed by a CVD process. In the graph, PSG 
indicates a PSG layer; BPSG indicates a BPSG layer; P-SiN indicates a SiN 
layer formed by plasma-enhanced CVD (PECVD) method; LP-SiN indicates a SiN 
layer formed by low-pressure CVD (LPCVD); USG indicates an USG layer; and 
TEOS indicates a tetra-ethyl-ortho-silicate (TEOS) layer. Also, PSG.sub.-- 
E, BPSG.sub.-- E, P-SiN.sub.-- E, LP-SiN.sub.-- E, USG.sub.-- E and 
TEOS.sub.-- E indicate a PSG layer, a BPSG layer, a P-SiN layer, a LP-SiN 
layer, a USG layer and a TEOS layer, all of which is radiated with 
electron beams. As shown in FIG. 2, the dielectric constants of each 
interlevel dielectric layer formed by the CVD process after the 
irradiation of electron beams becomes lower than the dielectric constants 
before the irradiation of electron beams. 
In FIG. 3, the wet etch rates of a thermal oxide film and a high 
temperature oxidation film are shown for comparison with the wet etch 
rates of the interlevel dielectric layers formed according to the present 
invention. As shown in FIG. 3, the etch rates of radiated interlevel 
dielectric layers after a CVD process is similar to the etch rates of 
interlevel dielectric layers annealed at 750.degree. C. or more. 
As described above, when electron beams radiate the interlevel dielectric 
layer including an oxide layer formed by the CVD process to densify the 
layer, the wet etch rate of the interlevel dielectric layer is at a 
conventional level, and simultaneously the dielectric constant is reduced. 
Also, moisture in the interlevel dielectric layer is effectively removed. 
Furthermore, the interlevel dielectric layers are prevented from being 
humidified in subsequent processes. 
A low-humidity interlevel dielectric layer can be obtained according to the 
following low temperature process. 
Referring to FIG. 4, a conductive layer pattern 14 is formed on a 
dielectric layer 12 over a semiconductor substrate. A first capping layer 
16 is formed on the conductive layer pattern 14. It is preferable that the 
first capping layer 16 is formed of a SiO.sub.2 layer, a SiON layer or a 
SiN layer. The first capping layer 16 may be formed on sidewalls and an 
upper surface of the conductive layer pattern 14, or only the upper 
surface of the conductive layer pattern 14. 
Then, a CVD oxide layer 20 is formed on the entire surface of the resultant 
structure. The CVD oxide layer 20 is formed of a layer selected from the 
group consisting of USG, BPSG, PSG, a borosilicate glass (BSG), a 
fluorine-doped silicate glass (FSG), SiN and SiON, formed by an 
atmospheric-pressure CVD (APCVD), a plasma-enhanced CVD (PECVD) or a 
low-pressure CVD (LPCVD) process. 
Subsequently, electron beams 30 are radiated to the semiconductor substrate 
10 at a temperature of between approximately room temperature and 
approximately 500.degree. C. in a predetermined time for reaching a 
desired exposure dose, using an electron beam radiator, to density the CVD 
oxide layer 20. At this time, the electron beams are radiated, by applying 
a current of 5.about.25 mA, a voltage of 1,000.about.30,000 V to the 
electron beam radiator, and at an exposure dose of 2,000.about.10,000 
.mu.C/cm.sup.2. The predetermined time can be varied according to the 
applied current or exposure dose for radiation of electron beams. If a 
current of 20 mA is applied at an exposure dose of 5,000 .mu.C/cm.sup.2, 
the predetermined time is about 300 seconds. The lower the current applied 
at a constant exposure dose, the more time for exposure is required. 
Incomplete bonds and moisture are removed from the CVD oxide layer 20 by 
the electron beams. Here, since the electrons in the beam do not have 
sufficient energy to etch the CVD oxide layer 20, the thickness of the CVD 
oxide layer 20 is not changed by the electron beam radiation, and the CVD 
oxide layer 20 is more stabilized. 
Referring to FIG. 5, the CVD oxide layer 20 is planarized by a CMP process 
to form a planarized interlevel dielectric layer 20A. 
Referring to FIG. 6, electron beams 40 radiate the resultant structure 
where the interlevel dielectric layer 20A is formed in order to remove the 
moisture absorbed into the interlevel dielectric layer 20A during a CMP 
process by the same manner as shown in FIG. 4. At the same time, the 
interlevel dielectric layer 20A is prevented from being humidified during 
subsequent processes. The process of radiating electron beams 40 may be 
omitted if necessary. 
Referring to FIG. 7, a second capping layer 22 is formed on the interlevel 
dielectric layer 20A. The second capping layer 22 is formed for 
stabilizing and densifying the interlevel dielectric layer 20A, and for 
preventing the interlevel dielectric layer 20A from being humidified in 
subsequent processes, and the second capping layer 22 may be omitted if 
necessary. The second capping layer 22 may be a CVD oxide layer formed of 
USG, BPSG, PSG, BSG, FSG, SiN or SiON by APCVD, PECVD or LPCVD process. 
Referring to FIG. 8, electron beams 50 radiate the second capping layer 22, 
by the same manner as shown in FIG. 4. 
When the CVD oxide layer 20 is planarized by a CMP process to form the 
interlevel dielectric layer 20A, and then electron beams 40 radiate the 
interlevel dielectric layer 20A, the radiation of electron beams 30 of 
FIG. 4 can be omitted. 
Also, a semiconductor substrate can be annealed at 400.about.600.degree. C. 
for approximately 30 min before or after forming the interlevel dielectric 
layer 20A. 
As described above, electron beams radiate the interlevel CVD oxide layer 
to densify the layer. Accordingly, moisture of the interlevel CVD oxide 
layer can be effectively removed, and a humidification of the interlevel 
CVD oxide layer, which may occur during the subsequent processes, can be 
effectively prevented. 
It should be understood that the invention is not limited to the 
illustrated embodiment and that many changes and modifications can be made 
within the scope of the invention by a person skilled in the art.