Electrical circuit arrangement for a display device

Disclosed is a method for addressing a display pixel and an electrical circuit arrangement for the display device. In some embodiments, the electrical circuit arrangement includes an input terminal for receiving a first signal; a first memory element for storing information about the first signal; a driver element coupled to the first memory element for outputting a second signal via an output terminal in accordance with the information about the first signal; and a calibration circuit coupled between the driver element and the input terminal for matching a potential difference between the driver element and the input terminal during a calibration phase prior to receiving the first signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 U.S.C. §371 of International Application No. PCT/IB2005/050769 filed on Mar. 2, 2005, and published in the English language as International Publication No. WO 2005/091269, which claims priority to European Application No. 04101031.5, filed on Mar. 12, 2004, incorporated herein by reference.

FIELD OF INVENTION

The invention relates to an electrical circuit arrangement for a display device comprising an input terminal for receiving a first signal, a first memory element, and a driver element for outputting a second signal in accordance with said first signal via an output terminal.

US 2001/0052606 discloses a display device comprising a matrix of pixels at crossings of row and column electrodes. The pixels each comprise a current mirror circuit to cope with transistor uniformity issues resulting from differences between drive transistors with respect to the charge carrier mobility and threshold voltage.

The currents in these types of display devices are very small, and the voltages required to drive pixels differ widely for pixels to be driven subsequently. This results in the disadvantage of long programming times for the display pixels, which are required to charge any parasitic capacitances with the very small currents. As these long programming times are not always available, the light emitted from the display pixels may not accurately reflect the current signal applied to the display pixel.

It is an object of the invention to provide an electrical circuit arrangement for a display device that has relatively short programming times.

This object is achieved by providing an electrical circuit arrangement for a display device, wherein said arrangement comprises an input terminal for receiving a first signal; a first memory element for storing information about the first signal; a driver element coupled to the first memory element for outputting a second signal via an output terminal in accordance with the information about the first signal; and a calibration circuit coupled between the driver element and the input terminal for matching a potential difference between the driver element and the input terminal during a calibration phase prior to receiving the first signal. By introducing this matching, there is no voltage change required at the input terminal during a subsequent programming phase if during this subsequent programming phase the second signal has to be programmed to the same value as during the previous programming phase. Usually, deviations between subsequent values of the second signal are small, so only small voltage changes are required of the input terminal. As these voltage changes are small, the required time to charge or discharge any parasitic capacitances, associated with the input terminal, is relatively short.

In a prior art arrangement, the potential of the input terminal prior to the programming phase may be quite different from the potential required during the programming, which results in a considerable time required to charge the parasitic capacitances during the programming phase. If in this case the charging is not completed before the end of the programming phase, the first memory element is not programmed correctly. In subsequent programming phases the same quite different potentials are present, which means that again the charging is not completed before the end of the programming phase. The electrical arrangement according to the invention allows recursive action, wherein the second signal approaches the first signal with even more accuracy if several identical first signals are received subsequently.

In an embodiment, the calibration circuit comprises a calibration switch for coupling the input terminal to a calibration voltage. By coupling the input terminal to the calibration voltage during the calibration phase, the voltage at the input terminal reaches in a relatively very short time the value of the calibration voltage. So, during the calibration phase the calibration circuit matches the difference between this calibration voltage and the potential of the driver element. The switch may be a common calibration switch for all calibration circuits coupled to the input terminal. The calibration switch may be controlled by a display controller.

In an embodiment the calibration circuit further comprises a calibration transistor coupled with its main terminals between the input terminal and the driver element, and a second memory element coupled to a gate of the calibration transistor. In this embodiment the calibration transistor carries during the calibration phase through its main terminals a current corresponding to the first signal of the previous programming phase. The second memory element is set during this calibration phase to such a value, that the gate of the transistor receives a voltage, which results in the desired current, so corresponding to the previous first signal, through the main terminals while the voltage difference between its main terminals matches the voltage difference between the input terminal and the driver element. As a result, if after the calibration phase during a subsequent programming phase the first signal is applied in the form of a current to the calibration circuit, no potential changes of the input terminal are required, if the first signal is the same as the previous first signal.

The calibration circuit may further comprise a switch coupled between one of the main terminals and the gate of the calibration transistor. This switch may be closed during the calibration phase to couple the potential of the driver element to the second memory element.

A further switch may be coupled between the driver element and the output terminal in order to block an output current, forming the second signal as provided by the driver element, from flowing to the output terminal during the calibration and programming phase.

Another switch may be coupled between the driver element and the calibration circuit. This switch may be closed during the calibration and the programming phase to couple the output current to the calibration transistor.

In a preferred embodiment of the invention the first memory element is arranged in a current mirror circuit. Current mirror circuits facilitate in replication of an input signal to an identical output signal.

The driver element may be a drive transistor having a gate connected to said first memory element, and a main terminal coupled to the calibration circuit, the gate further being coupled via a switch to the main terminal of the drive transistor. This is a simple, cost effective solution.

The first memory element may comprise a capacitor.

The invention further relates to a column driver comprising an electrical circuit arrangement as described above. This element of a display device typically receives a first signal that is to be quickly and accurately converted to a second signal.

The invention further relates to a display device comprising a plurality of display pixels comprising an electrical circuit arrangement as described above.

Another aspect of the invention provides a product comprising the display device according to the invention and signal processing circuitry. The product may be a handheld device such as a mobile phone, a Personal Digital Assistant (PDA) or a portable computer as well as a device such as a monitor for a Personal Computer, a television set, or a display on e.g. a dashboard of a car.

The invention finally relates to a method for addressing a display pixel. Further dependent claims define advantageous embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION

FIG. 1shows a product1comprising an active matrix display device6and signal processing circuitry SP. The display device6comprises an active matrix display panel2having a plurality of display pixels3arranged in a matrix of rows4and columns5. The display panel2is an active matrix display comprising display pixels3containing polymer light emitting diodes (PLEDs) or small molecule light emitting diodes (SMOLEDs). The display panel2may be a high resolution display panel as the available programming times in such display panels are very small.

The product1may be a television receiver, in which case the signal processing circuitry SP may include circuitry for receiving a television signal and converting the television signal into a format for driving a data input10of the display device6. Alternatively, the product1may be a handheld device such as a mobile phone or PDA, a portable computer or a monitor for a personal computer or any other product with a display device. In these cases the signal processing circuitry SP may include data processing circuitry and circuitry for processing of images to be displayed into a format suitable for driving the data input10.

FIG. 2shows a schematical illustration of an active matrix display device6, comprising e.g. a PLED display panel2of product1as shown inFIG. 1. The display device6comprises a display controller7, including a row selection circuit8and a column driver9including driver parts9A for driving the respective columns5(seeFIG. 1) of display pixels3. A data signal, comprising information or data such as for (video) images to be presented on the display panel2, is received via a data input10by the display controller7. The data may be written as driver programming currents Idatvia line13, the column driver9and data lines11to the appropriate display pixels3for each column5. The selection of the rows4(seeFIG. 1) of display pixels3is performed by the row selection circuit8via selection lines12, controlled by the display controller7. Synchronization between selection of the rows4of display pixels3and writing of the data to the display pixels3is performed by the display controller7.

FIG. 3shows an electrical circuit arrangement for a current programmable display pixel3wherein a first signal is applied as a current Iprogvia the column electrode11.

A driving transistor T2is used in both programming the display pixel3and in driving an emissive element14, such as a PLED element, via terminal15. The application of the programming current over the column electrode11is indicated by a current source Iprog, representing the driver part9A. During the programming period a transistor T4connects a capacitor C with a current carrying electrode of the driving transistor T2while the emissive element14is isolated from the driving transistor T2by a transistor T3. During this programming phase the data input programming current is forced through T2while the capacitor C is charged or discharged depending on the previously programmed value to reach the associated gate-source voltage VGS for T2. Now, by opening T1and T4and by closing T3, the drain current of the driving transistor T2is fed as a second signal to the emissive element14. The memory function of the capacitor C assures that the current is a copy of the programming current signal received over line11.

The current I through the driving transistor T2is equal to Iprogwhich is proportional to μ(V−Vt)2, wherein μ is the mobility of the charge carriers, Vt the threshold voltage of the driving transistor T2and V the gate-source voltage of the driving transistor T2. It is assumed here that the current I from the driving transistor T2is indeed identical to the programming current Iprog, which is a reasonable approximation for a display pixel3with a current mirror circuit. The programming voltage Vprogrepresenting the voltage that results from the application of the programming current Iprogtherefore yields:
Vprog=Vcc−Vt−√(Iprog/μ)
wherein Vccis the voltage supplied to the power line. The current mirror circuit of the display pixel3shown inFIG. 3has the advantageous feature that at low frequencies, despite differences in mobility μ and threshold voltages Vt of the driving transistors between the various display pixels3, the current Ilightthrough the emissive element, being equal to the current I through the driving transistor T2, is an almost exact copy of the received programming current. This current Ilightwill hereinafter also be called the second signal. Each driver part9A may apply the same circuit arrangement as described above for the display pixels. In this case (seeFIG. 2) the column driver9receives data in the form of the driver programming currents Idat(corresponding to the first signal) via line13. Each of the driver parts9A may be programmed sequentially by its corresponding part of the driver programming currents Idat. After the sequential programming of the driver parts9A, each of the driver parts9A may simultaneously provide its programming current Iprogto the data line11coupled to it. So, in case the electrical circuit arrangement is applied to a driver part9A, the programming current Iprog, being the resulting output of the arrangement, corresponds to the second signal as mentioned in the description of the current programmable display pixel3.

The programming currents Iprogare typically low, i.e. in the order of nanoamperes in the dark region to microamperes at full brightness of the emissive element14. The line capacitance of the column electrode11may be in the order of 100 pF. Thus for a difference in the programming voltage Vprogof 1 Volt between the upper and lower display pixel3, a programming current of 10 nanoamperes results in a period of 10 milliseconds to bring the column electrode11to the required voltage Vprog. Such long stabilization times limit operation of the display panel2at high frequencies, requiring relatively short programming times. For a high resolution display panel2the capacitance of the column electrode11increases, yielding worse performance. Further the trend to use higher resolutions and the use of highly efficient organic LED material results in a decrease of the programming currents for each display pixel3.

FIG. 5is a schematic illustration of the basic idea of the invention. An electrical circuit arrangement A for a display pixel3or a driver part9A as used in a display device6as shown inFIG. 2comprises an input terminal11,13respectively, for receiving as first signal the current Iprogor Idatand an output terminal15or11, respectively, for outputting as the second signal the current Ilightor Iprogfor a display pixel3or a driver part9A, respectively. The arrangement A further contains a first memory element M1coupled to a driver D for outputting the second signal Ilightor Iprogin accordance with the first signal Iprogor Idat, and a second memory element M2connected to a calibration circuit S for matching a potential difference between the driver D and the input terminal11,13by storing data in the second memory element M2related to said first signal Iprogor Idat.

In operation the first signal Iprogor Idatis received at the input terminal11,13and stored in the first memory element M1during a programming phase. A second signal Ilightor Iprogis generated from the driver element D in accordance with the first signal Iprogor Idatduring an output phase. Next, the data relating to the first signal Iprogor Idatare stored in the second memory element M2during a calibration phase. The data relating to the first signal may be transferred via the calibration circuit to the second memory M2or may be transferred via a direct coupling of the first memory M1and the second memory M2(not shown). The data stored in the second memory M2are used to preset the calibration circuit. This preset involves the setting of a voltage across the calibration circuit which matches the difference between the potential of the input terminal11,13and the driver D. This setting is done during the calibration phase to such a value, that it carries the current corresponding to the previously received first signal. As a result, when the further first signal does not differ from the previous one, there is no change of the potential of the input terminal11,13, required and as a consequence, there is for example, no delay in the programming phase caused by the charging of the line capacitance by the programming current Iprog.

So, if subsequently a further first signal is received at the input terminal11,13a potential of said input terminal11,13only changes if the further first signal differs from the previously received first signal or the data stored in M2are not yet in accordance with the data relating to the first signal although the further first signal is identical to the original or previous first signal.

Optionally the calibration phase may be skipped if the further first signal does not differ from the previously received first signal. When using this method, only a difference in potential of the input terminal11,13that may arise from two differing subsequent first signal Iprogor Idatneeds to be effected. Such a change of the potential can be effected much quicker as a result of which the second signal, i.e. Ilightor Iprogrespectively, can be a more accurate copy of the first signal Iprogor Idat. Further, the method allows recursive action, wherein the second signal Ilightor Iprogapproaches the first signal Iprogor Idatwith even more accuracy if several identical first signals are received at the input terminal11,13. Indeed for subsequent frames presented on a display panel2, the information to be displayed by a display pixel3of the display panel2is often substantially the same.

FIGS. 6A-6Cshow an application of the basic arrangement A displayed inFIG. 5for a display pixel3. It should however be appreciated that the invention is by no means limited to this specific application.

InFIG. 6Athe display pixel3is shown in the output phase. The voltage over the capacitor C may cause T2to drive the current emissive element14via the second terminal15with a second signal Ilightas a result of a previously received first signal Iprogof which data are stored at the capacitor C. It should be appreciated that the invention does not require that light is emitted from the emissive element14. T2corresponds to the driver element D and the capacitor C corresponds to the first memory element M1ofFIG. 5.

InFIG. 6Bthe calibration phase is shown. The data relating to the previous first signal Iprogare transferred to the capacitor Ccalby closing switches S1and S5prior to reception of a first signal Iprogat the column electrode11. The capacitor Ccalcorresponds to the second memory element M2inFIG. 5. This calibration phase may be triggered by the display controller7actuating switches S1and S5. S3is open. Switch S4is open such that the display pixel3is not programmed by charging or discharging the capacitor C. In this calibration phase the switch Scalis closed applying a calibration voltage Vcalof e.g. 0 Volts to the column electrode11. At the same time the current of T2is forced through a calibration transistor Tcaland a calibration capacitor Ccalis programmed to continue this current through Tcal, while the column line11is kept at the potential of the calibration voltage of e.g. 0 Volts. The gate voltage of the calibration transistor Tcalis connected to the capacitor Ccalsuch that while the calibration voltage is present on the column electrode11, a current substantially equal to the previously received first signal IprogofFIG. 6A, is flowing through Tcalas during this calibration phase switch S3is open, and the driver current is forced to flow through Tcaland not in the emissive element. The transistor Tcalwith the switches S5and Scalcorrespond to the calibration circuit inFIG. 5.

FIG. 6Cillustrates the programming phase wherein the display pixel3is programmed by charging the capacitor C to the adequate voltage. Accordingly, S5is opened, switch S4is closed and switch S3remains opened. Further the switch Scalis opened to allow the first programming current signal into the display pixel3. The capacitor Ccalensures maintenance of the input state on the column electrode11after opening of the switch Scal. As S5is opened the gate voltage of the calibration transistor Tcalwill remain constant at the value previously calibrated. As a result of the current setting of Tcal, the drain current of Tcalequals the programming current of the previously applied first signal. The actual programming current will now flow through Tcal, S1and T2such that the voltage over the capacitor C increases or decreases to a value where the current through the driving transistor T2is equal to the programming current Iprog.

If the display pixel3should not emit light for a particular percentage of the frame time when it is not addressed, i.e. a reduced duty cycle applies, the switch S3should be open for this percentage of the frame time.

The calibration phase described above may be executed row-wise for each column5. However, it is advantageous to execute the calibration phase for more than one row4of display pixels3at the time or even for the whole display panel2at once. The latter option requires the charge on Ccalto be sufficiently stable, i.e. no or negligible leakage, over the relevant period of time, i.e. the time during which the calibration voltage Vcalshould be maintained for the display pixel3. The initiation of the calibration phase for one or more rows4can be controlled by the display controller7.

A result of the calibration phase displayed inFIG. 6Bis that the display pixels3can be quickly and accurately current programmed as a result of the calibration with the previously applied current signal. Further, if substantially the same current signals are received as subsequent first signals for a particular display pixel3at the input terminal11, the remaining error in the current output to the emissive element14will reduce as a result of the recursive action provided by the presence of the first and second memory elements C and Ccal. Also for changing pictures, the light output required for a considerable amount of display pixels3remains the same.

A disadvantage of the active matrix display device6according to the invention is the increase in the area accommodated by circuitry for each display pixel3which is detrimental for the aperture of the display pixel. However, for top emission display panels2, wherein the light of the emissive element14is emitted away from the display pixel circuitry, this is not an issue.

The invention can be applied in active current-addressed matrix displays as described above and allows poor initial matching of the driver transistors T2between the display pixels3. Also field emission display drivers can advantageously use the invention.