Method for testing a memory device and memory device for carrying out the method

A memory device for data storage has a memory module with at least one memory bank in which data are stored and from which the stored data are read out, and a logic unit for controlling a writing and a reading of data to and from the at least one memory bank. Furthermore, a test module for testing the functionality of the memory module is provided. The test module is arranged in a manner separated from the memory module in a separate circuit unit, and is connected to the memory module via a communication device for the exchange of communication signals

Method for testing a memory device and memory device for carrying out the method

FIELD OF THE INVENTION

The present invention generally relates to memory devices having memory modules with high packing density. The present invention particularly relates to a method and a device for testing the memory modules contained in the memory device.

The present invention specifically relates to a memory device for data storage having a memory module, having at least one memory bank in which data to be stored are stored and from which the stored data are read out, and a logic unit for controlling a writing and a reading of data to and from the memory bank, and a test module for testing the functionality of the memory module.

In this case, the test module has a comparison compression device for outputting a defective determination signal if the memory module has at least one malfunction, whereas a defect-free determination signal is output when the memory module is operating correctly.

BACKGROUND

FIG. 4shows a conventional memory device100, which in this example has arranged four memory banks101a,101b,101cand101d.The individual memory banks101a–101dare connected to a comparison and compression circuit V arranged in an evaluation circuit region A. The comparison and data compression circuit V serves for testing the functionality of the individual memory banks101a–101dof the memory module100. It should be pointed out that the circuit arrangement illustrated inFIG. 4is a detail from an arbitrary semiconductor memory chip with memory array and data path. It is disadvantageous that in the conventional memory module100only ever one memory bank101a,101b,101c,or101dat a time can transmit results onto a data bus D.

As shown below with reference toFIG. 5, the data bus comprises four data lines103a–103din this example of a conventional memory module. In a conventional manner, the memory banks101a–101din each case comprise secondary sense amplifiers102a–102d.All data lines are connected to the comparison and data compression circuit in order to be able to perform a data comparison and a data compression.

FIG. 5shows the memory module100illustrated schematically inFIG. 4in greater detail.FIG. 5shows only two memory banks101a,101bwith the corresponding secondary sense amplifiers102a–102d.It should be pointed out that only four sense amplifiers102a–102dare shown by way of example here, whereas in principle a large number of secondary sense amplifiers102a–102nis provided in a memory bank101a–101n,where the number n may be greater than 100.

The requirement for increasingly higher storage densities gives rise to the problem that a chip area, i.e. a space requirement for the memory module, has to be reduced. In the case of the conventional memory modules illustrated inFIGS. 4 and 5, it is thus inexpedient that the comparison and data compression circuit identified by a reference symbol V is arranged in the evaluation circuit region A (dashed region inFIG. 4). The comparison and data compression circuit V serves for testing the individual memory banks101a–101nof the memory module, it being disadvantageous that only one memory bank101a–101din each case can be tested at a specific time. It is disadvantageous that a simultaneous testing of the memory banks101a–101ncontained in the memory module100is not made possible, in such a way that the test time is increased (four-fold in the example shown inFIG. 4in order to test all four memory banks).

This inexpediently leads to the disadvantage that the test costs are increased as a result of a lengthening of the test time when testing the conventional memory module100for functionality. An increase in parallelism when testing the memory module100could be provided by increasing the number of internal data lines103a–103d.However, increasing data lines in this way inexpediently leads to the disadvantage that they cause a considerable space requirement, as a result of which the chip area is disadvantageously enlarged.

SUMMARY

Therefore, it is an object of the present invention to provide a memory device for data storage in the case of which the memory module present in the memory device can be tested in a simple and efficient manner. In particular, it is necessary to reduce test costs.

This object is achieved by embodiments of the invention.

An important concept of the invention consists in providing a circuit unit by means of which the memory module is tested in a manner separated from the memory module. The customary arrangement of a test module within the memory device for testing the memory module present in the memory device has the disadvantage of a low degree of parallelism and a large space requirement. Another aspect of the invention consists in providing only connection units for connection of a test module in an evaluation circuit region of the memory module, said test module forming a separate circuit unit. The communication between the memory module to be tested and the test module that provides the test of the memory module is effected via a suitably designed communication device. The communication device advantageously comprises a needle card for making the electrical contact between the memory module and the test module.

Furthermore, it is expedient to design the communication device in such a way that communication signals can be exchanged via radio, i.e. in wire-free fashion. In a further aspect of the invention, the communication signals are exchanged optically between the test module and the memory module. In accordance with a general aspect, the memory device for data storage according to the invention essentially has:a) a memory module having at least one memory bank in which data to be stored are stored and from which the stored data are read out, and a logic unit for controlling a writing and a reading of data to and from the at least one memory bank; andb) a test module for testing the functionality of the memory module, the test module having a comparison compression device for outputting a defective determination signal if the memory module has at least one malfunction, and for outputting a defect-free determination signal if the memory module is operating correctly. The test module is arranged in a manner separated from the memory module in a separate circuit unit, and is connected to the memory module via a communication device for the exchange of communication signals.

Furthermore, the method according to the invention for storing data to be stored essentially has the following steps of:a) storing the data to be stored in a memory module, having at least one memory bank in which the data to be stored are stored and from which the stored data are read out, and a logic unit for controlling a writing and a reading of data to and from the memory bank; andb) testing the functionality of the memory module by means of a test module, a comparison compression device outputting a defective determination signal if the memory module has at least one malfunction, and a defect-free determination signal if the memory module is operating correctly, in a manner dependent on the serviceability of the memory module.

In accordance with this aspect of the method according to the invention, communication signals are exchanged between the test module and the memory module via a communication device, the test module being arranged in a manner separated from the memory module in a separate circuit unit.

In accordance with one preferred development of the present invention, the communication device via which the test module can be connected to the memory module is electrically connected by test module connection units to memory module connection units. Preferably, the communication device is designed as a needle card contact-making unit which electrically connects test module connection units to memory module connection units.

In accordance with a further preferred development of the present invention, the communication device via which the test module is connected to the memory module is provided as an RF or radio link. Such a radio link has the advantage that the communication signals can be transmitted in wire-free fashion, as a result of which it is possible to save or completely eliminate connecting lines between the memory module and the test module. Consequently, the test module is expediently totally separate from the memory module. Furthermore, it is expedient that a test module can test more than one memory module for functionality.

In accordance with yet another preferred development of the present invention, the communication device via which the test module is connected to the memory module is provided as an optical link. In particular when an optical access is provided between the test module and the memory module, it is advantageous to exchange optical communication signals between the two modules since these enable a greater data rate and data density in comparison with the abovementioned radio link.

In accordance with yet another preferred development of the present invention, a result communication signal is provided as a 1-bit wide defect-free/defective determination signal which indicates the functionality of the memory module.

In accordance with a further preferred development of the present invention, input communication signals are derived from secondary sense amplifiers arranged in the at least one memory bank of the memory module and are fed to the test system200.

On account of the input communication signals, in the test system a result communication signal is preferably processed in the test system. Furthermore, it is possible for the result communication signal to be output from the test system, fed back into the memory module and processed there.

Such separate provision of the test module as a circuit unit arranged in a manner separated from the memory module enables the memory module to be tested with a high degree of parallelism. Furthermore, the space requirement of chip area on the memory module is reduced and the test costs are lowered.

Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the description below.

DETAILED DESCRIPTION

In the figures, identical reference symbols designate identical or functionally identical components or steps.

FIG. 1schematically shows a memory module100′, which may have a large number of memory banks101a,101b,. . .101i, . . .101n. A chip area of the memory module between the individual memory banks101a–101nis identified by a hatched region A inFIG. 1. This hatched region is provided as an evaluation circuit region in which circuit units (for example logic units) for controlling writing and reading of data to and from the at least one memory bank may be arranged.

FIG. 2illustrates an exemplary memory module100having four memory banks101a,101b,101cand101d,this region being encompassed by a broken line. It is assumed hereafter that the memory module comprises these four memory banks101a–101d.It should be pointed out that the method according to the invention and the memory device with test module provided can also be applied to memory modules having a larger number of memory banks.

FIG. 2shows a detail from the memory module100illustrated inFIG. 1, the two memory banks101a–101bbeing illustrated in greater detail. The memory banks101a,101bin each case have secondary sense amplifiers102a–102dvia which data can be read out from the memory banks or written to the memory banks.

It should be pointed out that although only four secondary sense amplifiers102a–102dare illustrated inFIG. 2, in principle a larger number of secondary sense amplifiers102a–102nmay be provided, specific memory banks comprising a number of n≧100 secondary sense amplifiers102a–102n.In the present example, four secondary sense amplifiers102a–102dare provided per memory bank101a,101b.A data bus for supplying the secondary sense amplifiers with corresponding data thus comprises four data lines103a,103b,103cand103d.The data lines of the data bus are connected on the one hand to the corresponding amplifier of the secondary sense amplifiers102a–102dof the memory banks101a,101band on the other hand to a logic unit106. The logic unit serves only for controlling a writing or a reading of data to or from the at least one memory bank101a–101d.

It should be pointed out that a comparison and data compression circuit as in the conventional memory module described above with reference toFIGS. 4 and 5need not be provided here.

In this way, it is possible to save chip area. In order to test the memory module for its functionality, as illustrated inFIG. 2, memory module connection units105a–105dare provided in a contact-making region104. A communication with the (here by way of example 4) secondary sense amplifiers102a–102dis possible via the memory module connection units105a–105d.Furthermore, a connection to the four data lines103a–103dmay be provided. Although this is not shown inFIG. 2it is furthermore possible to address the remaining (in this example two) memory banks101c,101d(not shown) via corresponding memory module connection units.

FIG. 3shows the memory device for data storage according to the invention, in the case of which the memory module100and a test module200are arranged on separate chips (circuit units). The memory module100corresponds to the memory module described with reference toFIG. 2. A description of this memory module100is omitted here in order to avoid an overlap in the description.

The test module200has test module input connection units205a–205d.It should be pointed out that when a larger number of secondary sense amplifiers102a–102dare provided in the memory module100, it is also possible to provide a correspondingly increased number of test module connection units205a–205n(illustrated by the dots inFIG. 3). It shall be assumed here that the test module200for testing the memory module100to be tested has four test module input connection units205a–205d.

When the functionality of the memory module100is tested by means of the test module200, in the test module desired data are compared with actual data read out from the at least one memory bank101a–101n,whereupon a corresponding test result is provided,b1) a comparison compression device (201) outputting a defective determination signal if the memory module (100) has at least one malfunction, and a defect-free determination signal if the memory module (100) is operating correctly, in a manner dependent on the test result.

Furthermore, the test module200has a comparison compression device, in which a data comparison (actual data with desired data for testing the memory module to be tested) and also a data compression are effected. It should be pointed out that the circuit units for carrying out such a comparison and data compression operation, in the conventional memory device (FIG. 4andFIG. 5), are disadvantageously situated on the memory module100and thereby cause a considerable space requirement.

In accordance with a principal aspect of the present invention, the circuit units shown in the test module200are now arranged separately from the memory module100in such a way that a chip area in the case of operation of the memory module100for data storage is reduced. It should be pointed out that the test module200may have a plurality of comparison compression devices201in order to be able to read out all input communication signals206a–206nread out from the secondary sense amplifiers102a–102nof the memory module100.

The output signals of the comparison compression devices are combined in a combination unit202. The output signals are preferably provided as defect-free determination signals if the corresponding tested memory bank101a–101nis sound. If all tested memory banks101a–101nof the memory module100are defect-free, then the ANDing provided in the combination unit202produces a result communication signal indicating a functionality of the tested memory module100.

The test module200furthermore has a test module output connection unit203, via which the result communication signal either can be tapped off and processed further in a further circuit unit, or can be fed back via a communication device204to the logic unit106of the memory module100in order to be processed further there.

The communication device204is provided for connecting the memory module connection units105a–105dto the test module input connection units205a–205d,on the one hand, and the test module output connection unit203of the test module200to the logic unit106of the memory module100, on the other hand.

In this case, the communication device204may be provided as a wire-based communication device such as a needle card unit, for example, or as a wire-free communication device. A wire-free communication device comprises for example an RF or radio link or an optical link. Consequently, it is possible to address and to test a plurality of different memory modules100with one test module200.

The memory device according to the invention saves test costs and increases parallelism when testing the memory module to be tested. A large number of test module input connection units205a–205dmay advantageously be provided for the test module200. Furthermore, it is advantageous that comprehensive circuits can be provided for a data compression to be carried out in the test module200, which circuits advantageously do not cause a space requirement on the memory module as a result of the invention's separation of test module200and memory module100. The test signals which are fed to the memory module100via the test module200can be fed in directly upstream of the secondary sense amplifiers102a–102n,in which case the signals to be read out can be tapped off directly downstream of the secondary sense amplifiers102a–102n.As a result, it is possible in principle to simultaneously address all secondary sense amplifiers102a–102nof a memory bank101a–101n,thereby increasing parallelism when testing the memory module100to be tested.

After a testing and a data compression in the test module200, the result of the data compression may be fed back to the memory module100. Furthermore, it is possible for the test result to be evaluated directly in the test module200(not shown inFIG. 3). The same applies correspondingly to the write signals, as a result of which the memory module can be tested with great parallelism.

In order to carry out the method according to the invention for storing data to be stored in a memory module100, the memory module100being able to be tested by the test module200, it is necessary, in comparison with the conventional circuit arrangement, merely to provide corresponding memory module connection units105a–105din place of the comparison and data compression circuit.

The description above with reference toFIG. 3stated that a result communication signal207is fed to the memory module100via a test module output connection unit203of the test module200in a manner dependent on a test result. Such a signal supplies a determination of whether the tested memory module100is defective or defect-free. Such a “pass-fail” signal can be returned to the memory module100in order to be processed further there, or can be processed further directly in the test module200. During such testing, a data path of the memory module100is not tested or is only partially tested.

In order also to test the data path of the memory module100, a bit combination that arises during testing can be driven back via the data path of the memory module100. In this case, in the event of a positive comparison result, i.e. in the event of a defect-free determination signal (“pass” signal), the bit combination originally read out is written back to the memory module. By contrast, in the event of a negative comparison result, i.e. in the event of a defective determination signal (“fail” signal), a correspondingly inverted bit combination is written back to the memory module100. The table below gives examples, represented in a hexadecimal code, of such bit combinations for the case of a defect-free determination signal (comparison results=“pass” signal) and a defective determination signal (comparison results=“fail” signal).

The feedback of a result communication signal illustrated in accordance with the above table affords the advantage that the data path of the memory module100to be tested can also be concomitantly tested.

With regard to the conventional memory device for data storage as illustrated inFIGS. 4 and 5, reference is made to the introduction to the description.

Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways.

Moreover, the invention is not restricted to the application possibilities mentioned.

List of Reference Symbols

In the figures, identical reference symbols designate identical or functionally identical components or steps.