Reduced leakage memory cells

Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

TECHNICAL FIELD

The information disclosed herein relates generally to embodiments of semiconductor devices, including memory cells.

BACKGROUND

The semiconductor device industry has a market-driven need to reduce the size of devices used, for example, in dynamic random access memories (DRAMs) that are found in computers and mobile communications systems. Currently, the industry relies on the ability to reduce or scale the dimensions of its basic devices to increase device density. This includes scaling the channel length of the metal oxide semiconductor field effect transistor (MOSFET). Increased channel scaling of the MOSFET can lower the channel resistance. Consequently, channel leakage currents may increase. This relationship has made the present MOSFET channel design less useful for providing increasingly smaller memory cells, and thus, there is a need to find other mechanisms to generate reduced cell geometry.

DETAILED DESCRIPTION

One approach to increasing the on-chip storage capacity of a semiconductor is to increase the number of capacitor cells per unit area, which generally means reducing the overall size of the capacitor. However, reducing capacitor size may result in a lower capacitance per cell. If the lower cell capacitance means more capacitive elements are needed to maintain or improve upon a performance characteristic, such as the ability to maintain a storage charge over time, then any gain in capacitor density may be offset. The double-sided capacitor provides one useful device structure for increasing capacitance without a commensurate increase in area. A double-sided capacitor may be scaled smaller, for example, by increasing the dielectric constant of the insulator material separating the capacitor plates.

A double-sided capacitor used for a DRAM memory cell is typically coupled to an access transistor located in close proximity. For performance reasons and to maximize cell density, the access transistor and the double-sided capacitor may be formed in a stacked capacitor-transistor arrangement. A continued reduction in the size of the double-sided capacitor for such an arrangement then, may involve further reduction (or scaling) in the access transistor. In the case of a MOSFET, scaling smaller typically means reducing the channel length as well as channel width, which may lead to lower drain-source resistance (rds). Lower rds, may allow higher off-state leakage currents to flow between the drain and source. A lower rdsmay result from an increase in the channel conduction due to a short channel effect such as drain induced barrier lowering (DIBL). Near the channel inversion threshold, a potential barrier may be formed between the source and the channel blocking drain current flow. The application of a drain voltage may decrease the potential barrier height between the source and channel, increasing the drain current at near and below threshold. The drain current may therefore be due to the drain voltage as well as the gate voltage, effectively reducing rdsat near or below the inversion threshold. A higher gate leakage current may also occur at shorter channel lengths due to the higher gate electric fields. Many embodiments of the invention may operate to reduce the leakage currents as the channel length is reduced.

The bulk (or native) band gap energy of a semiconductor material is the energy separation between the conduction and valance bands having a three dimensional continuum of energy states. A semiconductor material with a three dimensional continuum of energy states does not, generally, exhibit substantial quantum size effects such as discrete energy levels, spin-orbit splitting of heavy and light hole bands and changes in band gap separation. Quantum size effects may be introduced by altering a crystal's dimensions. A change in the physical dimensions of a single crystal semiconductor material does not generally change the bulk band gap energy of the material, if all three crystal dimensions are sufficiently large. Conversely, reducing the size of a semiconductor material may cause the band gap energy of the material to increase or shift to higher energy, if at least one of the three crystal dimensions is made sufficiently small. For example, a rod shaped from semiconductor material may cause the energy band gap of the material to increase above its bulk band gap energy state as the diameter or the length of the rod is reduced. The change in the energy band gap of a rod-shaped material caused by its small dimensions may be exploited. A rod with a diameter on the order of a nanometer may be termed a “nanorod”.

In many embodiments, vertical transistor channels are formed using one or more semiconductor nanorods oriented substantially perpendicular to a surface of a substrate. In some cases, the channels comprise a nanorod shape. In some cases, the channel region is formed using multiple nanorods. And in some cases, a nanorod includes the channel region.

Nanorods offer alternatives to the designers of MOSFET-based devices since the geometry can be used to alter the electronic properties of the MOSFET channel using quantum size effects. As the diameter of the nanorod channel is reduced, a shift in the density of states, from a three-dimensional continuum of states to a two-dimensional density of states in the channel region may occur. Consequently, the electron and hole effective mass may be reduced and the band gap energy of the semiconductor material may increase in the channel. The lower effective masses of the charge carriers may provide improved carrier transport properties such as higher carrier mobilities. A MOSFET channel with a higher band gap energy may provide a low leakage current between source and drain regions, a lower gate-channel leakage current and a faster switching speed.

A common MOSFET channel material is single crystal silicon. Silicon is a material where the electronic band gap increases as the physical size of the crystal decreases. For a MOSFET with a silicon vertical electron channel shaped as a nanorod, or a silicon vertical electron channel formed with multiple nanorods, reducing the diameter of the nanorod, for example from 13 nm to 7 nm, increases the band gap energy at room temperature from its bulk (or native) band gap energy of 1.12 eV to 3.5 eV. Additional energy band gap separation may be possible by decreasing the nanorod diameter ever further. Lowering the surface state density of the channel along the side of the nanorod using a dielectric or a semiconductor with a band gap energy exceeding the higher energy of the nanorod, may also increase the band gap separation. Increasing the band gap separation may reduce DIBL and other short channel effects, including band-to-band tunneling induced off-state leakage.

FIG. 1Ais a cross-section illustrating nanorod formation according to various embodiments of the invention. In many embodiments, substrate101A comprises a silicon substrate, but substrate materials other than silicon, such as silicon germanium, may be used. In some embodiments, substrate101A may comprise a wafer, such as a silicon wafer. In various embodiments, substrate101A may comprise a silicon on sapphire or a silicon on insulator. The substrate101A may also comprise an isoelectronic material such as isoelectronic silicon. Various embodiments include the substrate101A with (001), (011) and (111) oriented crystal surfaces. In some embodiments, the substrate101A may be cut and/or polished off-axis with an angle ranging from 0.5° to 15° relative to the on-axis cut surface normal (shown as Y).

The impurity and/or electrical carrier concentration in layer102A may be adjusted to obtain the desired layer conductivity. For example, layer102A may be a doped to provide an n-type conductivity. In some embodiments, the layer102A may have p-type conductivity. In various embodiments, the layer102A may be a substantially unintentionally doped (or undoped) layer. In various embodiments, the layer102A may be of the same conductivity type as the substrate101A. In some embodiments, the layer102A has substantially the same electrical impurity concentration as the substrate101A. In various embodiments, layer102A is formed from the substrate101A. In some embodiments, layer102A may comprise a portion of the substrate101A. In various embodiments, layer102A may comprise an epitaxially grown or deposited film. In some embodiments, the impurity concentration and conductivity type of the layer102A may be adjusted using ion implantation to achieve the desired electrical concentration.

The layer103A may be formed on layer102A and, in some embodiments, may be formed from layer102A. The layer103A may be formed using an epitaxial process or a deposition process. Layer103A and layer102A may be of the same or of a different conductivity type. In various embodiments, layer103A is a substantially unintentionally doped layer. In some embodiments, layer103A is a doped layer having an impurity concentration of less than 1×1017cm−3. Examples of n-type impurities include P, As, and Sb. Examples of p-type impurities include B, Ga and In. In some embodiments, layer103A may have an electrically active concentration of less than 1×1017cm−3. In various embodiments, the impurity and/or electrically active concentration is graded in a direction substantially perpendicular to the surface normal. In various embodiments, the impurity and/or electrically active concentration is graded in a direction substantially parallel to the surface normal. In some embodiments, the impurity concentration and conductivity type of layer103A may be adjusted using ion implantation to provide a particular electrical concentration. In some embodiments, layer103A has substantially the same conductivity type as the substrate101A. In various embodiments, layer103A is formed from the substrate101A. In some embodiments, layer103A may form a portion of the substrate101A. In various embodiments, layers103A,102A and substrate101A may be formed from a single wafer such as a silicon wafer.

As shown inFIG. 1A, layer105A may be formed on the surface of the layer103A as a mask layer. Layer105A may be formed in the shape of a line, square, circle or other geometry as desired. Layer105A may be formed of any number of patternable materials such a photoresist, a metal, or a dielectric adaptable to various lithography processes. Spacers104A may be formed adjacent to layer105A using a suitable etch resistant material. In some embodiments, layer104A may comprise, without limitation, a semiconductor material such as SiGe, SiC and SiGeC, a dielectric such as silicon nitride, an oxynitride and SiO2, a polymer such as a photoresist, a block polymer such as diblock copolymer blends of polystyrene and polymethylmethacrylate, a metal such as W, MO, Ta and Al, or some combination of one or more layers of semiconductors, polymers, block polymers, dielectrics and metals. In various embodiments, the spacers104A may be formed as a self-assembled layer in a shape of an annular ring. In some embodiments, the spacers may be formed as a self-assembled layer with an island-like profile. In various embodiment, the spacers104A may be formed as a self-assembled layer forming a circular shaped hole. In some embodiment, the spacers104A may be formed by a self-assembled layer process without the layer105A.

FIG. 1Bis a cross-section illustrating nanorod formation according to various embodiments of the invention. Here, the layer105A ofFIG. 1Ais shown removed, leaving spacers104B substantially unchanged on layer103B. At this point, layers102B and/or103B may be further processed as desired using for example, diffusion, implantation, and anneal processes to adjust the electrical and mechanical properties of the respective layers between the spacers104B. In some embodiments,102B and/or103B may be further processed to adjust the electrical and mechanical properties of a portion of the respective layers directly under the spacers104B using the spacers as a mask. In various embodiments, the electrical properties of the layer102B may be adjusted to provide a conductive region adjacent to the spacers104B. In various embodiments, the electrical properties of the layer102B may be adjusted to form one or more shared doped regions extending, at least in part, laterally under the spacers104B. In some embodiments, the electrical properties of the layer102B may be adjusted to form a region contacting a doped region.

FIG. 1Cis a cross-section illustrating nanorod formation according to various embodiments of the invention. Here, layer103C and a portion of layer102C are shown removed between the spacers104C forming a vertical nanorod structure110C. The material between the spacers104C may be removed using an etch process, such as a wet chemical etch, a gas etch such as a plasma etch, and other suitable processes. In various embodiments, the depth of the etch may be less than 1 μm. Layer103C of the vertical nanorod structure110C forms the channel region and layer102C forms a shared doped drain/source region of a transistor. In some embodiments, the channel portion of the vertical structure may be less than 0.5 μm.

The nanorods110C may be formed as a pillars or columns and may have a lateral cross-section shaped substantially in the form of a disk presenting a vertical rod-like structure as illustrated inFIG. 1D.

FIG. 1Dillustrates nanorods110D formed according to various embodiments of the invention. The diameter of the layer103D below the spacers104C may range from about 0.5 nm to about 15 nm. In some embodiments, a diameter of the103D layer below the spacers104D may range from about 1 nm to about 10 nm. In general, the diameter may be chosen according to the desired energy band shift. In various embodiments, the layer103D between the spacers102D may be partially removed. In some embodiments, layers102D,103D and a portion of substrate material101D may be removed between the spacers104D such that there is no shared doped region using layer102D without further processing (not shown).

In some embodiments, layers102D and103D are formed from the substrate material101D. For example, layer102D and103D may be a portion of the substrate material101D that is a semiconductor wafer. In various embodiments, substrate101D is a single crystal silicon wafer. In some embodiments, layers102D,103D and101D comprise silicon layers. In various embodiments, layer102D and103D may comprise SiGe layers. In some embodiments, layer102D may be a SiGe layer and103D may comprise a silicon layer. In various embodiments, layer102D may comprise a silicon layer and103D a SiGe layer. In some embodiments, layer102D and/or layer103D may comprise a SiC layer or a SiGeC layer.

FIG. 2Ais cross-section illustrating a MOS transistor according to various embodiments of the invention. Here, the vertical nanorod210A is first formed, then a gate dielectric206A is formed in contact with the channel region203A of the vertical nanorods. Insulator207A may be formed between the nanorods over layer202A. An optional field insulator may be further formed between the nanorods (not shown). The gate dielectric206A may be formed along the sides of the nanorods210A surrounding or enclosing the channel region. In some embodiments, the insulator207A and the gate dielectric206A are formed of the same dielectric material. In various embodiments, the insulator207A and the gate dielectric206A may be different materials. Examples of gate dielectric materials include, without limitation, SiO2, SiN, and nitrides and oxynitrides formed with Si, Mo, W, Ta, Hf, and Al. In some embodiments the gate dielectric may comprise a composite multi-layer dielectric. The thickness of the gate dielectric206A may range from about 2 nm to about 20 nm, depending on the gate dielectric material and related properties such as a dielectric constant. In some embodiments, the insulator207A and the gate dielectric206A may be formed with the same thickness or with different thicknesses.

FIG. 2Bis cross-section illustrating a MOS transistor according to various embodiments of the invention. Here, two access transistors200B are shown separated by an isolation region212B formed on the substrate201B. The isolation region212B may be a shallow trench isolation region formed in the shared drain/source region202B to electrically isolate the access transistors200B. Isolation region212B may be an etched region filled with a dielectric material such as vapor deposited SiO2. In some embodiments, the isolation region212B may be formed in a portion of the substrate201B. The access transistors include the vertical nanorods210B with a drain/source region211B at one end of the nanorod in contact with channel region203B, and a shared drain/source region202B at the second end in contact with the channel region. In some embodiments, an isolation region may used to electrically isolate a plurality of vertical nanorods configured in parallel to form a vertical channel transistor. In some embodiments, the length of the vertical channel region203B may be less than 250 nm. In various embodiments, the length of the vertical channel region203B may be between about 20 nm and about 150 nm.

The gate conductor208B may be formed over the gate dielectric206B that surrounds the nanorods in the channel region203B. The gate region may be formed as a shared conductive gate region by filling-in the area between the nanorods210B with a suitable conductive material. In some embodiments, the gate region may be formed such that there is no shared gate region. Examples of conductive gate region materials include, but are not limited to, polysilicon, metals such as Al, W, Mo and Ta, binaries such as TiN and TaN, metal silicides such as WSix, NiSi, CoSixand TiSix, a dacecamine, and combinations of layers of conductive material. Field insulator209B may be formed overlaying gate conductor208B and may comprise any suitable insulator, including, without limitation, SiO2, SiN, and oxynitride-based dielectrics containing Si, Al, W, Ta, Ti, and Mo.

Drain/source region211B and shared source/drain region202B may be configured to be in electrical contact using the vertical channel region203B of the nanorods such that no current flows across the channel region with zero gate bias voltage applied to gate conductor208B. Drain/source region211B may be formed by epitaxial growth, ion implantation, and deposition processes. In some embodiments, the drain/source region211B may be formed as a shared region. In various embodiments, drain/source region211B may comprise silicon, doped polysilicon, SiC, SiGe or SiGeC. A substantially planar surface may be obtained for the field dielectric209B and drain source region211B using a chemical mechanical process as are known to those of ordinary skill in the art. In various embodiments, a conductive region overlaying insulator209B and the drain/source region211B may be formed to couple the nanorods210B (not shown).

FIG. 3is a surface view of a MOS transistor according to various embodiments of the invention. Here, the access transistor300is shown with nine nanorods310and an isolation region312, but may include more or less nanorods. The vertical channel region203B ofFIG. 2Bcoupled to the drain/source region302form a composite of parallel channels, which may be electrically coupled to a capacitor at311(not shown). In some embodiments, the isolation region312may be used electrically isolate a plurality of vertical channel regions. In various embodiments, the isolation region312may be used to electrically isolate the vertical channel regions of an access transistor300from the vertical channel regions of an adjacent access transistor300. In some embodiments, the isolation region312may be used to isolate a capacitor coupled to the access transistor300from adjacent capacitor cells (not shown). As show by way of example inFIG. 3, but not by limitation, a shared annular gate arrangement of nine nanorods310may be formed with a center-to-center spacing of 24 nm using vertical nanorod channels (not shown) having about a 10 nm diameter, a gate dielectric306with about a 2 nm radial thickness and gate conductor308with about a 5 nm radial thickness. Various embodiments include a gate dielectric thicknesses ranging from about 2 nm to about 20 nm, channel region diameters ranging from about 0.5 nm to about 15 nm, and conductive gate region thicknesses ranging from about 3 nm to about 10 nm. The number of parallel coupled nanorods and/or channels formed as part of the access transistor, or other such transistor, may affect desired performance characteristics. In general, the number of vertical channels per surface area may be determined and adjusted according to specified design rules for a particular manufacturing process.

FIG. 4is a cross-section illustrating a memory cell according to various embodiments of the invention. Here, a DRAM cell430includes an access transistor400and double-sided capacitor425, but any type of capacitor may be configured to be supported by and/or coupled to the access transistor. The double-sided capacitor stores electrical charge received from an input circuit (not shown) such that the charge establishes an electric field across the insulator422between capacitor plates421and423. More information regarding fabrication of storage cell capacitors can be found in U.S. Pat. No. 6,030,847 entitled Method for Forming a Storage Capacitor Compatible with High Dielectric Constant Material, and U.S. patent application Ser. No. 10/788,977 entitled Semiconductor Fabrication Using a Collar, both incorporated by reference herein in their entirety.

In various embodiments, and as shown inFIG. 4, the n-type drain/source region411of the access transistor400are in contact the nanorod channels403and capacitor plate421. The electric charge supporting the electric field between capacitor plates421and423may place each drain/source region411in contact with capacitor plate421at substantially equal potential. In this case, charge may not flow though the vertical channel region403of any nanorod410in the absence of a bias potential on gate conductor408. In some embodiments, the gate conductor408shared a conductor coupling the gate region of one or more nanorods. Thus, the gate conductor408may comprise multiple discrete gate electrodes coupled using a conductor. The vertical channel403of the nanorods410may be sufficiently small in diameter so that the electronic band gap energy of the material in the channel region403is greater than in the non-channel regions, such as in the unetched portion of the n-type drain/source region402and the substrate layer401. In various embodiments, the substrate401, the n-type shared drain/source region402, the channel region403and/or the n-type drain/source region411are formed from a material with the same lattice constant. In some embodiments, the substrate401, the shared drain/source region402, the channel region403and/or the drain/source region411are formed of silicon. In various embodiments, the drain/source region411is made sufficiently large to eliminate quantum size effects, such as a higher energy band gap shift. In some embodiments, the drains/source region411may be shared drains/source region. In various embodiments, a portion of the shared drain/source region402is made sufficiently large to eliminate quantum size effects in that portion. In some embodiments, the shared drain/source region402is coupled to the ground plane413using via holes (not shown). In various embodiments, the shared source drain region402may be used as a ground plane or a similar conductive region. In some embodiments, the substrate is coupled to the ground plane413. In various embodiments, the substrate forms at least a part of a conductive plane such as a ground plane. In some embodiments, an electrical isolation region (not shown) may be formed in the substrate between the nanorods410. In various embodiments, the substrate may comprise an electrically non-conductive material such as a silicon wafer with a low carrier concentration. In some embodiments, the ground plane413may comprise a series of ground planes. In various embodiments, the ground plane413is formed as a plurality of conductors coupled to one or more conductors, electrodes, circuit element, voltages and the like.

Charge placed on the capacitor425by a voltage signal transmitted by conductor from an input/output circuit (not shown), for example, may be stored during the access transistor's off-state since no further current path is provided. For the memory cell illustrated inFIG. 4, the charge may be used to establish an electric field in the vertical direction between the capacitor plate421and the conductive ground plane413. A portion of the electric field may have a vertical potential gradient across the channel region403of the nanorods410of the access transistor400between the source/drain regions402,411. In the absence of voltage applied to the gate conductor408, substantially no current flows between drain/source regions402,411(off-state).

Application of a voltage to the gate conductor408may establish an electric field across gate dielectric406with field components perpendicular to the channel403. A gate voltage in cooperation with the gate dielectric layer406may further generate a charge inversion layer (not shown) extending inward from the gate dielectric along the channel403between drain/source regions402,411. The charge inversion layer may electrically couple the drain/source regions402,411to form a current path there between. In some embodiments, the nanorods may have a circular cross-section and the electric field includes a radial potential gradient. The formation of a current path between the capacitor plate421in contact with the drain/source region411and the shared drain/source region402and/or substrate401and/or conductive ground plane413, may allow the capacitor425to discharge through the channel region, removing the capacitor's charge and the respective voltage and electric field.

In the transistor off-state, the energy band discontinuity (or energy band offset) between the capacitor plate421and the channel region403may be larger with the nanorods410than for a transistor channel formed from the same material with a bulk band gap energy (e.g. without nanorods). This increased energy band offset may provide an increased electron barrier for blocking electrons thereby reducing the amount of charge escaping the capacitor plate421though the channel region403. The increased energy band gap difference between the source/drain region402and the channel region403may reduce DIBL by improving the sub-threshold ideality factor and sub-threshold voltage swing. Consequently, a reduction in the amount of charge leaking from the capacitor425over time may occur through the access transistor400. As a result, the DRAM cell430may retain charge for longer times.

FIG. 5is block diagram of a memory device500according to various embodiments of the invention. The memory device500may include an array of memory cells502, an address decoder504, row access circuitry506, column access circuitry508, control circuitry510, and an input/output (I/O) circuit512. The memory cells502may comprise one or more capacitor cells operatively coupled to the row access circuit506and the column access circuit. The memory device500may be operably coupled to an external processor514, or memory controller (not shown) to provide access to the memory content. The memory device500is shown to receive control signals from the processor514, such as WE*, RAS* and CAS* signals. The memory device500may store data which is accessed via I/O lines. It will be appreciated by those of ordinary skill in the art that additional circuitry and control signals can be provided, and that the memory device ofFIG. 5has been simplified to help focus on, and not obscure, various embodiments of the invention. Any of the memory cells, transistors, and associated circuitry may include an integrated circuit structure and/or elements in accordance with various embodiments of the invention. For example, the array of memory cells502may be fabricated according to embodiments of the invention, so as to include one or more nanorods, as shown inFIG. 1D.

It should be understood that the above description of a memory device500is intended to provide a general understanding of possible memory structures, and is not a complete description of all the elements and features of a specific type of memory, such as DRAM. Further, many embodiments of the invention are equally applicable to any size and type of memory circuit and are not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (static random access memory) and flash memories. Additionally, the DRAM could comprise a synchronous DRAM, commonly referred to as SGRAM (synchronous graphics random access memory), SDRAM (synchronous DRAM), SDRAM II, and DDR SDRAM (double data rate SDRAM), as well as Synchlink™ or Rambus™ DRAMs and other technologies.

FIG. 6illustrates a semiconductor wafer600according to various embodiments of the invention. As shown, a semiconductor die610may be produced from a wafer600. The semiconductor die610may be individually patterned on a substrate layer or wafer600that contains circuitry, or integrated circuit devices, to perform a specific function. The semiconductor wafer600may contain a repeated pattern of such semiconductor dies610containing the same functionality. The semiconductor die610may be packaged in a protective casing (not shown) with leads extending therefrom (not shown), providing access to the circuitry of the die for unilateral or bilateral communication and control. The semiconductor die610may include an integrated circuit structure or element in accordance with various embodiments of the invention, including one or more nanorods, as shown inFIG. 1D.

FIG. 7illustrates a circuit module700according to various embodiment of the invention. As shown inFIG. 7, two or more semiconductor dice610may be combined, with or without a protective casing, into a circuit module700to enhance or extend the functionality of an individual semiconductor die610. The circuit module700may comprise a combination of semiconductor dice610representing a variety of functions, or a combination of semiconductor dies610containing the same functionality. One or more semiconductor dice610of circuit module700may contain at least one integrated circuit structure or element in accordance with embodiments of the invention, including one or more nanorods, as shown inFIG. 1D.

Some examples of a circuit module include memory modules, device drivers, power modules, communication modems, processor modules and application-specific modules, and may include multilayer, multichip modules. The circuit module700may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, a personal digital assistant, a network server such as a file server or an application server, an automobile, an industrial control system, an aircraft and others. The circuit module700may have a variety of leads710extending therefrom and coupled to the semiconductor dice610providing unilateral or bilateral communication and control.

FIG. 8illustrates a circuit module as a memory module800, according to various embodiment of the invention. A memory module800may include multiple memory devices810contained on a support815(the number generally depending upon the desired bus width and the desire for parity checking). The memory module800may accept a command signal from an external controller (not shown) on a command link820and provide for data input and data output on data links830. The command link820and data links830may be connected to leads840extending from the support815. The leads840are shown for conceptual purposes and are not limited to the positions shown inFIG. 8. At least one of the memory devices810may contain an integrated circuit structure or element in accordance with embodiments of the invention, including one or more nanorods, as shown inFIG. 1D.

FIG. 9illustrates a block diagram of an electronic system900according to various embodiment of the invention.FIG. 9shows an electronic system900containing one or more circuit modules700. The electronic system900may include a user interface910that provides a user of the electronic system900with some form of control or observation of the results generated by the electronic system900. Some examples of a user interface910include a keyboard, a pointing device, a monitor or printer of a personal computer; a tuning dial, a display or speakers of a radio; an ignition switch, gauges or gas pedal of an automobile; and a card reader, keypad, display or currency dispenser of an automated teller machine, as well as other human-machine interfaces.

The user interface910may further include access ports provided to electronic system900. Access ports are used to connect an electronic system900to the more tangible user interface components previously provided by way of example. One or more of the circuit modules700may comprise a processor providing some form of manipulation, control or direction of inputs from or outputs to the user interface710, or of other information either preprogrammed into, or otherwise provided to, the electronic system900. As will be apparent from the lists of examples previously given, the electronic system900may be associated with certain mechanical components (not shown) in addition to the circuit modules700and the user interface910. It should be understood that the one or more circuit modules700in the electronic system900can be replaced by a single integrated circuit. Furthermore, the electronic system900may be a subcomponent of a larger electronic system. It should also be understood by those of ordinary skill in the art, after reading this disclosure that at least one of the memory modules700may contain an integrated circuit structure or element in accordance with embodiments of the invention, including one or more nanorods, as shown inFIG. 1D.

FIG. 10illustrates a block diagram of an electronic system as a memory system1000according to various embodiment of the invention. A memory system1000may contain one or more memory modules800and a memory controller1010. The memory modules800may each contain one or more memory devices810. At least one of memory devices810may contain an integrated circuit structure or element in accordance with embodiments of the invention, including one or more nanorods, as shown inFIG. 1D.

The memory controller1010may provide and control a bidirectional interface between the memory system1000and an external system bus1020. In some embodiments, the memory controller1010may also contain one or more nanorods, as shown inFIG. 1D. The memory system1400may accept a command signal from the external system bus1020and relay it to the one or more memory modules800on a command link830. The memory system1000may provide data input and data output between the one or more memory modules800and the external system bus1020on data links1040.

FIG. 11illustrates a block diagram of an electronic system as a computer system1100according to various embodiment of the invention. A computer system1100may contain a processor1110and a memory system1000housed in a computer unit1105. The computer system1100also serves as an example of an electronic system containing another electronic system, i.e., memory system1000, as a subcomponent. The computer system1100optionally contains user interface components, such as a keyboard1120, a pointing device1130, a monitor1140, a printer1150and a bulk storage device1160. Other components associated with the computer system1100, such as modems, device driver cards, additional storage devices, etc. may also be included. The processor1110and the memory system1000of the computer system1100can be incorporated on a single integrated circuit. Such single package processing units may operate to reduce the communication time between the processor and the memory circuit. The processor1110and the memory system1000may contain one or more nanorods, as shown inFIG. 1D. In some embodiments, the printer1150or the bulk storage device1160may contain an integrated circuit structure or element in accordance with embodiments of the invention, including one or more nanorods, as shown inFIG. 1D.

The above Detailed Description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments. These embodiments, which are also referred to herein as “examples,” are described in enough detail to enable those skilled in the art to practice the invention. The embodiments may be combined, other embodiments may be utilized, or structural, logical and electrical changes may be made without departing from the scope of the present invention. The Detailed Description is, therefore, not to be taken in a limiting sense, and the scope of the various embodiments is defined only by the appended claims and their equivalents.

The Abstract is provided to comply with 37 C.F.R. §1.72(b), which requires that it allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.