Dual molded stack TSV package

Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.

BACKGROUND

Field

Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to packages including an embedded die with through silicon vias.

Background Information

The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. Additionally, while the form factor (e.g. thickness) and footprint (e.g. area) for semiconductor die packaging is decreasing, the number of input/output (I/O) pads is increasing.

SUMMARY

Embodiments describe semiconductor die packages including a first level die with through silicon vias (TSVs). For example, the first level die may be an active die such as a logic die or system on chip (SOC) die, and the first level die may be embedded in the package between two redistribution layers (RDLs). In accordance with embodiments, the packages may be system in package (SiP) structures. In one embodiment, a package includes a first RDL including a top side and a back side. A second level die is mounted on the top side of the first RDL. The back side of the first RDL is on a front surface of a first level die, and the front surface of the first level die includes a first plurality of first landing pads electrically connected to active devices in the first level die and a second plurality of second landing pads electrically connected a plurality of TSVs in the first level die. The package additionally includes a second RDL including a top side and a back side, with the top side of the second RDL on a back surface of the first level die. In accordance with embodiments, the first level die may include active devices and be less than 50 μm thick.

The first level die may additionally include one or more interconnect layers between the active devices and the front surface of the first level die. A first level molding compound can encapsulate the first level die between the first RDL and the second RDL, and a second level molding compound can encapsulate the second level die on the first RDL. In an embodiment, the second level molding compound also encapsulates a non-silicon compound mounted on the first RDL. A plurality of conductive pillars may be formed on the first RDL and extend through the second level molding compound. For example, this may provide an electrical connection to bond a second package to for a package on package (PoP) structure. A plurality of conductive bumps can be placed on the back side of the second RDL, for example, for bonding the package or PoP. In an embodiment, each TSV has a maximum width of 10 μm or less. In an embodiment, the first RDL is directly on the front surface of the first level die, the second RDL is directly on the back surface of the first level die, and the first RDL and the second RDL each have a maximum thickness of less than 30 μm.

In one embodiment, a package includes a first RDL including a top side and a back side. A second level die is mounted on the top side of the first RDL. The back side of the first RDL is on a front surface of a first level die, the first level die comprises active devices and a plurality of TSVs, and the first level die is less than 50 μm thick. The package additionally includes a second RDL including a top side and a back side, with the top side of the second RDL directly on a back surface of the first level die.

In accordance with embodiments, a thinned first level active die with TSVs embedded between RDLs may be used to achieve smaller package dimensions with a high I/O count. In an embodiment, each TSV has a maximum width of 10 μm or less. Each TSV may also have an aspect ratio of less than 10:1 of first level die thickness : TSV maximum width. At these sizes a TSV keep out zone may be reduced to less than 5 μm. At these dimensions the first level die may have a TSV density of at least 2,500 per mm2. Additionally, the first RDL and the second RDL may each have a maximum thickness of less than 30 μm.

In an embodiment, a method of forming a package includes encapsulating a first level die on a carrier substrate with a first level molding compound, removing the carrier substrate, forming a first RDL on the first level die and the first level molding compound, mounting a second level die on the first RDL, encapsulating the second level die on the first RDL with a second level molding compound, reducing a thickness of the first level die and the first level molding compound, and forming a second RDL on the first level molding compound and on TSVs of the first level die. In an embodiment, the TSVs are exposed when reducing the thickness of the first level die and the first level molding compound. In an embodiment, the TSV are formed through the first level die after reducing the thickness of the first level die and the first level molding compound, and prior to forming the second RDL. In an embodiment, the first RDL may be formed directly on a first plurality of first landing pads electrically connected to active devices in the first level die, and formed directly on a second plurality of second landing pads electrically connected to the TSVs.

DETAILED DESCRIPTION

Embodiments describe semiconductor packages including a first level die with through silicon vias (TSVs). Specifically, the first level die may be a thinned active die with TSVs embedded in the package. In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

In one aspect, embodiments describe a package design involving a dual molded wafer process flow with an embedded first level die (e.g. active die) including TSVs. The process flow is such that the embedded first level die with TSVs can be thinned down to extremely thin levels (e.g. less than 50 μm, or more specifically less than 20 μm, or 5 μm), which is much thinner than a traditional interposer, for example, with a thickness of at least 150 μm. At the reduced thickness, short and direct routing paths (e.g. with a vertical height less than 100 μm) can be designed from the package bottom surface contacts (e.g. landing pads or conductive bumps) to a second level die in the package. As a result, signal and power routing penalties commonly associated with a traditional stacked die (e.g. with a vertical routing height greater than 100 μm from a package bottom surface contacts to a second level die) is not prohibitive. Embodiments may be used for a variety of die integration schemes, including system on chip (SOC) die splitting (e.g. splitting an SOC into stacked die), die partitioning (e.g. functionally partitioning an SOC die), MEM/AP (memory-application processor) die stacking, VR (voltage regulation) integration, passives integration, and other heterogeneous combinations of technologies in a relatively thin form factor.

In one aspect, embodiments describe an embedded TSV first level die configuration that may have a comparatively low keep out zone (KOZ). It has been observed that TSVs, such as copper TSVs through a silicon die, can create stress in the surrounding die area. As a result, active devices are arranged outside of a lateral KOZ around a TSV to mitigate TSV-induced stress on the active devices, such as affecting carrier mobility in the active devices. In accordance with embodiments, the reduced thickness of the embedded active first level die can allow the formation of TSVs with a substantially less width (or diameter) compared to common TSVs such as those in a traditional interposer. In some embodiments, aspect ratios of at most 10:1 first level die thickness:TSV maximum width are well within processing parameters. For example, TSVs having a maximum width (or diameter) of 10 μm, or much less are possible. An exemplary list of TSV dimensions and aspect ratios is provided in Table 1 for illustrative purposes.

A reduced TSV height may allow for reduced TSV maximum width (or diameter), as well as increased TSV density and a smaller KOZ. In some embodiments, a TSV density of 50×50 per mm2(e.g. 2,500 per mm2) is possible, which may be greater than that achievable with traditional interposers at approximately 10×10 per mm2(or 1,000 per mm2). In some embodiments, a KOZ of less than approximately 5 μm is possible. In an embodiment, a TSV through the active first level die is within 5 μm of an active device (e.g. transistor) in the active first level die. In one aspect, this may allow for a greater degree of freedom in location of the active devices, as well as location and density of the TSVs to provide a shorter and more direct routing from a bottom landing pad or conductive bump (e.g. solder bump or stud bump) of the package to the stacked second level die or a top package in a package on package (PoP) structure. In accordance with embodiments the stacked second level die or top package can have relatively straight routing to the bottom landing pad or conductive bump of the (bottom) package, where the power plane is, for example on a circuit board.

In one embodiment, a package includes a first RDL including a top side and a back side. A second level die is mounted on the top side of the first RDL. The back side of the first RDL is on a front surface of a first level die, and the front surface of the first level die includes a first plurality of first landing pads electrically connected to active devices in the first level die and a second plurality of second landing pads electrically connected a plurality of TSVs in the first level die. The package additionally includes a second RDL including a top side and a back side, with the top side of the second RDL on a back surface of the first level die. In accordance with embodiments, the first level die may include active devices and be less than 50 μm thick.

In one embodiment, a package includes a first RDL including a top side and a back side. A second level die is mounted on the top side of the first RDL. The back side of the first RDL is on a front surface of a first level die, the first level die comprises active devices and a plurality of TSVs, and the first level die is less than 50 μm thick. The package additionally includes a second RDL including a top side and a back side, with the top side of the second RDL directly on a back surface of the first level die.

FIG. 1is a flow chart illustrating a method of forming a package in accordance with an embodiment. In interest of clarity, the following description ofFIG. 1is made with regard to reference features found inFIGS. 2-13. At operation a1010a first level die110is encapsulated on a carrier substrate102with a first level molding compound130, followed by removal of the carrier substrate102at operation1020. One or more through mold vias (TMVs)164and/or non-silicon component(s)400may optionally be encapsulated on the carrier substrate with the first level molding compound at operation1010. A first RDL140is then formed on the first level die110and the first level molding compound130, and optionally the TMVs164and non-silicon component(s)400at operation1030. Conductive pillars190may then be optionally formed on the first RDL140. A second level die150, and optionally one or more non-silicon components300, are then mounted on the first RDL140at operation1040. At operation1040the second level die150is encapsulated on the first RDL140with a second level molding compound160. A thickness of the first level die110and the first level molding compound130is then reduced at operation1060, for example, using chemical mechanical polishing (CMP). A second RDL170may then be formed on the first level molding compound130and on a TSV120of the first level die110at operation1070. In some embodiments, the first level die110is an active die including pre-formed blind vias119at operation1010, and the reduction in thickness at operation1060exposes the blind vias119to form TSVs120. In another embodiment, the TSVs120may be formed in the first level die110after reducing the thickness of the first level die110at operation1060. Various additional structural features and variations of the process and structure are described with regard toFIGS. 2-13.

Referring now toFIG. 2a schematic cross-sectional side view is provided of a first level die110including blind vias119in accordance with an embodiment. In accordance with embodiments, the first level die110may be an active die such as a logic die or SOC die including an active component(s) such as, but not limited to, a microprocessor, memory, RF transceiver, and mixed-signal component. In the particular embodiment illustrated, an active device121(e.g. transistor) of an active component is shown by way of example. As shown, the active devices121may be formed on a substrate117such as a silicon substrate or silicon on insulator (SOI) substrate. In an embodiment, the active devices121are formed in a top epitaxial silicon layer116, formed over a base silicon substrate114. In an embodiment, the KOZ is less than 5 μm, and a blind via119is formed within 5 μm (laterally) of an active device121. One or more interconnect layers118may be formed for routing purposes to connect the active devices121and blind vias119to landing pads128(including both128A,128B on the front surface112) of the first level die110. The interconnect layers118may include one or more metal layers126and/or dielectric layers124. In the embodiment illustrated, the blind vias119(which will become TSVs120) are interspersed between the active devices121in the first level die110.

The landing pads128may be exposed in a variety of ways.FIG. 3is a close up cross-sectional side view of a first level die110with polymer defined landing pads128in accordance with an embodiment. As shown, a passivation layer122(e.g. polyimide) is formed over a top metal layer126. The landing pad128is defined by an opening in the passivation layer122exposing the underlying top metal layer126.FIG. 4is a close up cross-sectional side view of a first level die110with under bump metallurgy (UBM) defined landing pads128in accordance with an embodiment. As shown, a passivation layer122(e.g. polyimide) is formed over a top metal layer126. An opening is formed in the top metal layer126, and a UBM pad is formed over the opening and in contact with the top metal layer126. In this configuration, the UBM pad corresponds to the landing pad128.

Referring toFIGS. 2-4, the metal layer(s)126may provide lateral interconnect paths, with vias127providing vertical connections. In accordance with embodiments, the front surface112of the first level die110includes landing pads128B connected to blind vias119, and landing pads128A connected to the active devices121of the first level die110. In the embodiment illustrated, the blind vias119are formed in the active layer (e.g. interconnect layer118) of the active devices121. The blind vias119may extend completely through the active layer (e.g. interconnect layer118) and optionally into the base substrate114. The depth of the blind vias119may be at least the depth of the final TSVs120to be formed. In an embodiment, the blind vias119may be formed in an SOI substrate, with the top silicon SOI layer corresponding to epitaxial layer116inFIG. 2. In an embodiment, the blind vias119may optionally extend at least partially through the interconnect layer(s)118. For example, blind vias119may extend through the interconnect layer118to landing pads128A, or to a metal layer126in an embodiment. In an embodiment, blind vias119may not contact a landing pad (e.g.128A,128B) on the front surface112and instead connect with an active device121through one or more metal layers126and vias127in the interconnect layer118. In this manner, the TSVs120to be formed can connect directly to the active devices121within the first level die110without routing through the first RDL140, yet to be formed.

Referring now toFIG. 5, one or more first level die110are mounted on a carrier substrate102such as a glass panel, silicon wafer, metal panel, etc. The carrier substrate102may include an adhesive (e.g. polymer) or tape layer104for mounting the first level die110. As shown, the first level die110are mounted onto the carrier substrate102face down, such that the front surface112including the landing pads128(128A,128B) is face down. In an embodiment, one or more non-silicon components400(seeFIG. 13) are optionally mounted onto the carrier substrate102with the one or more first level die110. In an embodiment, through mold vias (TMVs)164are optionally formed on the carrier substrate. The material of optional TMVs164can include, but is not limited to, a metallic material such as copper, titanium, nickel gold, and combinations or alloys thereof. TMVs164may be formed using a suitable processing technique, and may be formed of a variety of suitable materials (e.g. copper) and layers. In an embodiment, TMVs164are formed by a plating technique, such as electroplating using a patterned photoresist to define the TMV dimensions, followed by removal of the patterned photoresist layer. In an embodiment, the optional TMVs164are formed prior to mounting of the first level die110.

The plurality of first level die110and optional TMVs164and/or non-silicon component(s)400are then encapsulated in a first level molding compound130on the carrier substrate102. For example, the first level molding compound130may include a thermosetting cross-linked resin (e.g. epoxy), though other materials may be used as known in electronic packaging. Encapsulation may be accomplished using a suitable technique such as, but not limited to, transfer molding, compression molding, and lamination. In the embodiment illustrated, the first level molding compound130covers the back surfaces115of the first level die110, and optional TMVs164and/or non-silicon component(s)400in order to provide structural support, e.g. as a reconstituted wafer, during subsequent processing.

Referring now toFIG. 6a first redistribution layer (RDL)140is formed on the first level molding compound130and the exposed surfaces of the landing pads128A,128, and optionally exposed surfaces of the TMVs164and/or non-silicon component(s)400, when present. As shown, the first RDL140includes a top side143and a back side141formed directly on the front surface112of the first level die110. The first RDL140may include a single redistribution line142or multiple redistribution lines142and dielectric layers144. The first RDL140may be formed by a layer-by-layer process, and may be formed using thin film technology. In an embodiment, the first RDL140has a total thickness of less than 50 μm, or more specifically less than 30 μm, such as approximately 20 μm. In an embodiment, first RDL140includes embedded redistribution lines142(embedded traces). For example, the redistribution lines142may be created by first forming a seed layer, followed by forming a metal (e.g. copper) pattern. Alternatively, redistribution lines142may be formed by deposition (e.g. sputtering) and etching. The material of redistribution lines142can include, but is not limited to, a metallic material such as copper, titanium, nickel, gold, and combinations or alloys thereof. The metal pattern of the redistribution lines142is then embedded in a dielectric layer144, which is optionally patterned. The dielectric layer(s)144may be any suitable material such as an oxide, or polymer (e.g. polyimide).

In the embodiment illustrated, redistribution lines142are formed directly on the landing pads128A,128B. More specifically, contact pads145of the redistribution lines142of the first RDL140are formed directly on the landing pads128A,128B of first level die110, and optionally directly on the TMVs164and/or directly one the non-silicon component(s)400.

Following the formation of the first RDL140a plurality of conductive pillars190may optionally be formed on the first RDL140as illustrated inFIG. 7. Conductive pillars190may be formed similarly, and of the same materials as described above with regard to the optional TMVs164.

Referring toFIG. 7one or more second level die150, and optionally non-silicon component(s)300(seeFIGS. 12-13, e.g. transducer, passive device such as inductor, capacitor, filter), are mounted (e.g. surface mounted with solder joints) on the top side143of the first RDL140. In the embodiment illustrated, second level die150is front facing toward the first RDL140and is attached to landing pads or under bump metallurgy (UBM) pads148of the first RDL140with conductive bumps, such as stud bumps, solder bumps, or stud bumps152with solder tips154. Following mounting of the second level die150to the first RDL140, an underfill material156may optionally be applied to between the second level die150and first RDL140. In an embodiment, the back side of the second level die150does not include any conductive contacts (e.g. stud bumps, solder bumps, etc.).

In an embodiment, the second level die150may be an SOC die, for example in a die splitting configuration in which first level die110and second level die150slit SOC components. In an embodiment, second level die150is a memory die, such as dynamic random-access memory (DRAM). In an embodiment, second level die150is a voltage regulator die. In such a configuration, the second level (voltage regulator) die150controls voltage to the first level (SOC) die110. In accordance with embodiments, the relatively small thickness of the RDLs (140and170to be formed) and first level die110allows for signal/power routing to the second level die150which is much shorter than for a typical stack package. Accordingly, this allows for the location of a second level (voltage regulator) die150on top of a first level (SOC) die110in one embodiment.

The second level die150, and optional conductive pillars190and/or optional non-silicon components300are then encapsulated in a second level molding compound160on the first RDL140. The second level molding compound160may be formed similarly as, and from the same material as the first level molding compound130. Following encapsulation with the second level molding compound, the structure may optionally be processed with a grinding operation, etching operation, or patterned and etched to expose the top surface151of the second level die, and optional conductive pillars190. In an embodiment, the top surface161of the second level molding compound160, and the top surface151of the second level die150, and optional top surface191of the conductive pillars190are coplanar after a grinding or etching operation.

Following the formation of the second level molding compound160, and optional reduction in thickness, the second level molding compound160may be used as the carrier, e.g. reconstituted wafer, for reducing a thickness of the first level molding compound130, first level die110, and optional TMVs164and optional non-silicon component(s)300.FIG. 8Ais a cross-sectional side view illustration of a thinned first level molding compound130and thinned first level die110with exposed TSVs120in accordance with an embodiment. In accordance with some embodiments, thinning is achieved with a grinding operation (e.g. CMP) to expose the blind vias119, resulting in a back surface115of the first level die110including exposed surfaces123of TSVs120. In an embodiment, the first level die110is thinned to less than 50 μm thick, or more specifically less than 20 μm.

In an embodiment, rather than forming TSVs120by thinning the first level die110to expose the blind vias119, the structure illustrated inFIG. 8Amay be achieved by forming TSVs120after thinning using suitable processing techniques such as etching and plating to form the TSVs120. Referring now toFIG. 8Bin an embodiment, TSVs120formed after thinning can extend through the first level die110and into the first RDL140in accordance with an embodiment. For example, the TSVs120may extend to a redistribution line (e.g. metal layer)142within the first RDL140, or to the landing pads or under bump metallurgy (UBM) pads148of the first RDL140for direct connection to the second level die148or optional conductive pillars190. In an embodiment, TSVs120extending through the first RDL140may have a maximum width greater than 10 μm.

Referring now toFIG. 9, a second RDL170is then formed on (e.g. directly on) the exposed top side131of the second level molding compound130, the exposed surfaces123of TSVs120on the back surface115of the first level die110, and optionally the exposed surfaces165of the TMVs164and optionally the exposed surfaces of the non-silicon component(s)300. As shown, the second RDL170includes back side171and a top side173formed directly on the back surface115of the first level die110. The second RDL170may include a single redistribution line172or multiple redistribution lines172and dielectric layers174. The second RDL170may be formed by a layer-by-layer process, and may be formed using thin film technology. In an embodiment, the second RDL170has a total thickness of less than 50 μm, or more specifically less than 30 μm, such as approximately 20 μm. In an embodiment, second RDL170includes embedded redistribution lines172(embedded traces). For example, the redistribution lines172may be created by first forming a seed layer, followed by forming a metal (e.g. copper) pattern. Alternatively, redistribution lines172may be formed by deposition (e.g. sputtering) and etching. The material of redistribution lines172can include, but is not limited to, a metallic material such as copper, titanium, nickel, gold, and combinations or alloys thereof. The metal pattern of the redistribution lines172is then embedded in a dielectric layer174, which is optionally patterned. The dielectric layer(s)174may be any suitable material such as an oxide, or polymer (e.g. polyimide).

In the embodiment illustrated, redistribution lines172are formed directly on the exposed surfaces123of the TSVs120, and optionally the exposed surfaces165of the TMVs164and/or non-silicon component(s)300. In the embodiment illustrated, contact pads175of the redistribution lines172of the second RDL170are formed directly on the exposed surfaces123of the TSVs120, and optionally the exposed surfaces165of the TMVs164. Following the formation of the second RDL170a plurality of conductive bumps180(e.g. solder bumps, or stud bumps) may be formed on landing pads (e.g. UBM pads)178on the back side171of the second RDL170.

FIG. 10is a cross-sectional side view illustration of a package100variation including a thinned first level die110in accordance with an embodiment. Similar to the package100illustrated inFIG. 9, the thinned first level die110is embedded within the package between the first RDL140and second RDL170. WhileFIG. 9illustrates multiple first level die110, and optional TMVs164, the embodiment illustrated inFIG. 10includes a single, larger first level die110. This may allow for the inclusion of more components within a single first level die110(e.g. logic or SOC die), while retaining short and direct routing from landing pads178of the second RDL170, through the second RDL170, through TSVs120of the first level die110, through the first RDL140, and to the second level die150.

FIG. 11is a cross-sectional side view illustration of a package on package (PoP) variation with conductive pillars190in accordance with an embodiment. The lower package100illustrated inFIG. 11is similar to that illustrated inFIG. 10, with the addition of the optional conductive pillars190extending through the second level molding compound160. The conductive pillars190may be formed as described with regard toFIG. 7. As shown, a top package200is bonded to the lower package100to form a PoP structure. For example, a top package200including a die250is bonded to the exposed surfaces191of conductive pillars190with conductive bumps280(e.g. solder bumps, or stud bumps).

FIG. 12is a cross-sectional side view illustration of a package100variation with heterogeneous integration of a die150and non-silicon component300within the second level molding compound160in accordance with an embodiment. The package100illustrated inFIG. 12is similar to package100illustrated inFIG. 10with the addition of the non-silicon component300mounted on the first RDL140and encapsulated within the second level molding compound160similarly as described with regard toFIG. 7.

FIG. 13is a cross-sectional side view illustration of a package100variation with heterogeneous integration of die110,150and non-silicon components400,300within the first and second level molding compounds130,160in accordance with an embodiment. Package100illustrated inFIG. 13is similar to package100illustrated inFIG. 12with the addition of a non-silicon component400(e.g. transducer, passive device such as inductor, capacitor, filter) embedded in the first level molding compound130between the first RDL140and second RDL170. For example, non-silicon component400may have been mounted on the carrier substrate102similarly as the first level die110illustrated inFIG. 5, followed by encapsulation within the first level molding compound130, and formation of the first RDL140as illustrated inFIG. 6. Additionally, the second RDL170may be formed on the non-silicon component400similarly as described with regard toFIG. 9after the thinning operation described with regard toFIGS. 8A-8B.

While the package100variations described and illustrated inFIGS. 9-13have been described and illustrated separately, many of the structural features and processing sequences may be combined in a single embodiment. In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming package including a thinned first level die with TSVs. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.