A self-biased high-speed receiver is described. The receiver is powered by one power supply with the core operation voltage and one power supply with the IO operation voltage. The receiver is self-biased to provide a stable bias voltage. A reference voltage and an IO signal are applied on the receiver so that the difference is amplified. Thick oxide transistors are used to increase the operation voltage of the transistors. Native thick oxide transistors are used so that the receiver can work with low command mode input.

FIELD OF INVENTION

This invention relates generally to the MOS integrated circuits and more particularly to a high-speed IO signal receiver that can be used in deep submicron technology.

BACKGROUND

An IO signal can be received by a receiver that detects the IO signal and amplifies it. The IO signal is then input to a core circuit for further processing. Since the IO signal is not generated by the core circuit, its amplitude is not limited by the core circuit's power supply voltage (also known as the core operation voltage or Vdd). The amplitude of the IO signal may be as high as the IO circuit's power supply voltage (also known as the IO operation voltage or Vddio). Therefore, the core circuit that directly takes input from an IO signal receiver must be able to handle an IO signal with amplitude of Vddio.

In a traditional circuit that employs micron technology or earlier technologies, the operation voltage of the core circuit was in a range of about 2.5V to 3.3V, similar to the IO operation voltage of 3.3V to 5.0V, so that amplified IO signal can be directly input to a core circuit since their operation voltages are in same range. However, with the integrated circuit size continuing to shrink, the core operation voltage is lowered. For example, a circuit made with sub micron technology (0.5 to 0.8 micron) has an operation voltage of about 2.5V to about 3.3V. When the deep sub micron technology is employed, the size of a circuit is further reduced to about 0.25, 0.18 or even 0.13 micron, and the operation voltage drops to around 1 volt. It is expected that the core operation voltage will continue to fall with the integrated circuit size continuing to shrink.

While the core circuit operation voltage falls, the IO circuit voltage often stays at a higher voltage. Problems can arise when a high IO signal with the amplitude Vddiois input to a core circuit. The core circuit can be damaged or degraded if it is only designed to handle a voltage no higher than its operation voltage Vdd. Traditionally, a differential amplifier can be used as the IO signal receiver due to the compatibility of Vddioand Vdd.

FIG. 1, which was taken from U.S. Pat. No. 4,958,133, illustrates a circuit schematic view of a conventional IO receiver. A reference voltage is applied at node A and an IO signal voltage is applied at node B. The IO signal is amplified and output to node OUT. It is to be noted that the power supply at node C is the same as the power supplies at nodes D and E. This circuit works fine in the micron technology. However, in deep micron technology, since the power voltage at node C is around 1V, while the input IO signal at node B is 2.5V to 3.3V, the circuit does not function correctly. The input IO signals are clamped by transistors1band2bwhen the input signal is higher than Vdd. Transistors1band2band surrounding transistors may be damaged or degraded by voltages higher than they are designed to handle.

A solution to this problem is to use a device called level-down converter. This device takes an input signal with the amplitude of the IO operation voltage (Vddio) and converts to a relatively low signal with the amplitude of the core operation voltage (Vdd).FIG. 2is a schematic view of how a traditional circuit50works. The signal Vinis an IO signal input. Vrefis a reference voltage used to decide whether the input signal is a “1” or “0”, and is normally a fixed voltage. The receiver circuit52is used to receive the input IO signal Vinand amplify it. After amplification, the amplitude of the IO signal is Vddio. A level-down converter54is used to reduce its amplitude to Vddbefore the signal is sent to a core circuit56. Level-down converter54is normally a stand-alone device.

This solution has an intermediate stage at which the IO signal is amplified to a high level of Vddio. This not only increases power consumption but also degrades the circuit response to high-speed IO signals. The response degradation was observed when the signal speed reaches several hundred mega hertz. Two factors may have contributed to the degradation. Firstly, charging a device to a higher voltage and discharging it requires more time, but the high-speed signals have only a short time to change state, so that the signals may be distorted. Secondly, an IO signal is a noise source. When a signal changes state, electromagnetic noise that interferes with other parts of the circuit are generated. A higher voltage will generate a higher amount of noise. For example, a 3.3V signal generates much higher noise than a 1.2V signal.

SUMMARY OF THE INVENTION

In one aspect, the present invention provides a new circuit that solves problems of the prior art. In the preferred embodiments, the circuit combines a stand-alone, level-down converter into the receiver circuit without degrading the lifetime or reliability of the circuit. At the same time, the circuit will have improved response to high-speed IO signals. The present invention addresses these requirements.

The preferred embodiment of the present invention is devised to provide an integrated solution of a high-speed IO signal receiver. A circuit with dual power supplies is described. The circuit has a self-biased circuit to provide a stable bias voltage. A reference voltage is provided to decide the state of an IO signal. Thick oxide transistors are used together with thin oxide transistors to match different operation voltages. The output signal has an amplitude of the core operation voltage. The integration of the signal receiver with the level-down converter minimizes the number of devices working under the high IO operation voltage and increases the work range of the receiver to a higher speed.

A variation of the high-speed signal receiver takes advantage of the very low threshold voltages of native transistors. The using of native thick oxide transistors extends the working range of the receiver to low command mode input signals.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A preferred embodiment of a self-biased high-speed receiver is described. A variation of the present invention will then be discussed.

FIG. 3illustrates a block diagram of a first embodiment of the present invention. Compared toFIG. 2, it is noted that the IO signal detector53and the level-down converter54are integrated into one circuit60and the intermediate IO signal with amplitude of Vddiois removed. The output of the circuit60is provided to a core circuit56compatible signal with the amplitude of Vdd.

FIG. 4illustrates a circuit schematic diagram of the preferred embodiment circuit1. The reference voltage Vddat node32is a power supply of the core circuit56. Its voltage is determined by the technology used to make the core circuit. In deep micron technology, Vddat node32is typically around 1.0V to 1.5V. The supply voltage Vddioat node30is equal to the IO power supply, preferably 1.8 V to 3.3V. Other values can be used as long as they are higher than the IO signal amplitude and higher than Vddat node32. The signal Vinat node57is the input IO signal and the signal Vrefat node53is a comparison reference voltage. An input signal Vinthat is higher than Vrefis considered to be a high signal, or “1”. Conversely, an input signal Vinthat is lower than Vrefis considered to be a low signal, or “0”. The signal Vinhas a range between the negative power supply (or the ground) and Vddio. Voutis the output of the receiver and is between the negative power supply (or the ground) at node33and Vdd.

The sub circuit made of transistors2,4,6,8,10and12has two major functions. Firstly, it provides bias current to the circuit. Secondly, it provides the first stage amplified the input signal. Transistors6and8are pMOS transistors arranged as a first differential pair having their sources coupled to each other, and transistors10and12are nMOS transistors arranged as a second differential pair of transistors having their sources coupled to each other. The two differential pairs are complementary to each other in that they comprise transistors having complimentary carrier types. This circuit has a push-and-pull effect to the nodes that are coupled to the complimentary pairs so that desired result can be maximized. The gates of transistors6and10are coupled to the reference voltage Vrefat node53, and the gates of transistors8and12are coupled to the input Vinat node57.

Transistor2is a pMOS transistor with its source coupled to Vddioat node30. Its drain is coupled to the sources of transistors6and8. Transistor2provides a bias current to transistors6and8. Transistors6and8act as a splitter of the relatively stable bias current. The splitting of the bias current contributes to the differential amplification. If one of the transistors6and8receives more current, the other one receives less. Transistor4is an nMOS transistor, its source is coupled to the negative power supply or the ground. Its drain is coupled to the sources of transistors10and12. Transistor4provides a sink for the current coming from transistors10and12. Transistors10and12act as the current combiner for transistor4. Since the drain-source current of transistor4is relatively stable, if one of the transistors10or12inject more current into transistor4, the other one injects less, so that the current combiner also contributes to the differential amplification. Transistor pairs2and4,6and10, and8and12are complementary.

The sub circuit made of transistors14,16and18mainly provides a stable bias voltage with the help of transistors2,4,6,8,10and12. pMOS transistor14and nMOS transistor18are also a complementary pair. The drain current of transistor14is sourced to transistors16and10. The source of transistor18is coupled to the negative power supply or the ground, and its drain is coupled to the drain of transistor16. Transistor18's gate and drain are connected together so that it is biased in its saturation region as long as its gate-source voltage Vgsis more positive than its threshold voltage Vth. Transistor18's gate at node36is also connected to the gates of transistors16,14,4,2,22,20and24, and therefore, provides a bias voltage Vbiasto them. The bias circuit generates a negative feedback. As such, if the voltage Vbiasgoes up for any reason (such as process, temperature, power supply etc.), Vgsof transistor18becomes higher and transistor18conducts more. Therefore, the drain-source voltage Vdsof transistor18becomes lower. Since transistor18's drain is coupled to its gate, the gate voltage, or Vbiasbecomes lower, therefore the shift of Vbiasis corrected by the circuit itself. The negative feedback is also provided by transistors16and14. When Vbiasat node36goes up, the gate voltages of transistors16and14go up, and the source-drain voltages Vsgof transistors14and16become smaller, so that transistors14and16conduct less. This takes down the drain voltage of transistor16, therefore lowers Vbiasat node36. More important, self-bias is implemented through the six transistors in the middle of the circuit, namely,2,4,6,8,10and12. For example, if Vbiasat node36goes up, the gate voltage of transistors2and4goes up, causing transistor2to conduct less, transistor4to conduct more, transistor6to conduct less, and transistor10to conduct more, so that the voltage at nodes38and40goes down. This takes down Vbiasat node36. The negative feedback keeps the bias voltage stable and insensitive to the variations in processing, supply voltage, and temperature. Since the gates of transistors16,14and18are coupled to bias voltage Vbias, the gates of transistors6and8are coupled to Vref, and both Vbiasand Vrefare stable. All nodes on the left side of transistors2and4have stable voltages and the current in each device is also stable.

Under a stable bias current, the sub circuit made of transistors20,22and24can output the amplified signal. pMOS transistor20and nMOS transistor24are one complementary pair. The drain current of transistor20is sourced to transistors22and12. The drain of nMOS transistor12is coupled to the output Voutat node34instead of its gate and its source is coupled to a negative power supply or the ground.

The circuit1has a good common mode rejection. This is because transistors on the left and right side of transistors2and4are symmetrical pairs. The characteristics of transistor pairs14and20,16and22,18and24,10and12, and6and8are made to substantially match each other by design. When Vinand Vrefincrease or decrease together, the output voltage Voutis not affected. In other words, the voltages of Vrefand Vindo not affect Vout, only their difference does. The common mode rejection can be explained as such. Since the gates of transistors14,16,18,22, and24are all coupled to the same voltage Vbias, if Vrefand Vinare at the same voltage, the nodes on the left side and the corresponding nodes on the right side should be at the same voltages because circuit1is symmetrical. Therefore, the drain voltage of transistor24, which is Voutat node34, should equal the drain voltage of transistor18, which is also Vbiasat node36. Considering Vbiasis stable, Voutwill not change even if Vrefand Vinchange as long as Vinequals Vref.

The differential input of Vrefand Vinis amplified. Since the gates of transistors24,22, and20are coupled to bias voltage, their gate voltages are stable, so that the states of these transistors are controlled by Vin. The amplification of the IO signal Vinis conducted through two paths. The first path is through transistor12. When Vinbecomes lower, transistor12conducts less, so that voltage at the source of transistor22is higher. Since transistor22is a pass gate, or source follower, the drain voltage of transistor22is higher, and Voutat node34is higher. The second path is through transistor8, if Vinat node57is lower, transistor8conducts more and its source voltage goes up, therefore Voutat node34is higher. From the above analysis, it is found that both transistors8and12help to amplify the signal Vin. They work together to make the receiver gain higher.

Vrefvalue is normally set to the middle of Vin's fluctuation range, for example, Vref=Vss+(Vddio−Vss)/2, where Vssis the negative supply voltage reference at node33. Depending on the nature of the signal Vin, Vrefmay be set in a wide range. It is desirable that Vrefis set in optimal range between Vth10and (Vddio-Vth6), where Vth10is the threshold voltage of the transistor10and Vth6is the threshold voltage of the transistor6. If Vinand Vrefare lower than Vth10, transistors10and12are cut off, only transistors6and8conduct and amplify the signals. Likewise, if Vinand Vrefare higher than (Vddio-Vth6), transistors6and8cut off, only transistors10and12conduct and amplify the signals. An advantage of this circuit is that when Vddiois coupled to 3.3V, by adjusting Vref, different IO signals may be received without the need of changing Vddio. This greatly simplifies the design of a circuit in which the present invention is to be used. For example, with Vddioequaling 3.3V, setting Vrefto 1.65V makes the circuit work with the IO signal of 0V to 3.3V, and setting Vrefto 0.75V makes the circuit work with the IO signal of 0V to 1.5V.

Since Vinis an IO signal coming from an external source, its amplitude is not controlled by circuit1. As previously stated, the highest voltage Vincan reach is Vddio, which may be as high as 3.3V or more. In order for the voltage not to be clamped, the source of transistor2is coupled to Vddioinstead of Vdd. However, the operation voltage of devices in a deep micron circuit is around 1.0 volt, devices may degrade or be damaged if operated at higher voltages. When the difference of the core operation voltage and the IO operation voltage gets bigger, the possibility that devices are damaged is also higher. Therefore, all transistors using Vddioas a power supply, namely transistors2,4,6,8,10and12, need to have the operation voltage of Vddio. The present embodiment uses thick oxide transistors to achieve higher operation voltages. The thick oxide transistors have thicker gate oxide than the thin oxide transistors and have higher operation voltage, higher threshold voltage and lower speed. The thick oxide transistors used by the present invention preferably have the operation voltage of 2.5V to 3.3V, more preferably 3.3V, as 3.3V is compatible with any IO signal 3.3V or lower.

Since transistors18,24,16,22,14and20use Vddas the power supply, they may be made of thin oxide devices. The thin oxide transistors have lower operation voltage, higher speed and lower power consumption. The concept of thin and thick is relative. The actual thickness of the transistor gate oxide depends on the material used and the process. For example, a thin oxide transistor thickness of 17 Å to 20 Å has an operation voltage of 1.0V to 1.5V. To promote the operation voltage to about 2.5V to 3.3V, the thickness of the transistor gate oxide needs to be increased to about 45 Å to 60 Å. The making of thick oxide transistors is known in the arts of the design of chip I/O buffers and it is not in the scope of the present invention so that the details are not discussed. The separation of transistors into thick oxide transistors and thin oxide transistors has created a circuit that minimized the number of transistors that operate at the IO operation voltage.

FIG. 5illustrates a circuit schematic view of a variation of the preferred embodiment. The preferred embodiment described inFIG. 4works best when Vinand Vrefare in the optimal range. The typical threshold voltage of a thin oxide transistor is about 0.7V, so that Vinand Vrefhave an optimal work range of about 0.9V to about 1.8V. If Vinand Vrefare out of the circuit's optimal range, the amplification of the circuit is low since only part of the circuit amplifies. Also, the thick oxide transistors have higher threshold voltages than the thin oxide transistors, with a typical threshold voltage of about 0.25V to about 0.35V, so that the receiver's optimal range is further limited by using thick oxide transistors. This presents a problem for low command mode input signals. A low command mode input voltage Vincan typically be as low as about 0.7V. To receive and amplify this low Vinsignal effectively, the Vrefneeds to be set as low as about 0. To increase the gain of the nMOS differential input transistor pair10and12, a modification is made as illustrated inFIG. 5. In this embodiment, the thick oxide transistors10and12are replaced with transistors210and212that are native thick oxide transistors. Native transistors sit in wafer substrate type or in wells of the same type as the substrate. They have very low threshold voltages. It is desired that the threshold voltage be below about 0V. The making of native transistors is well known in the art.

With a low voltage threshold, transistors210and212still have gain of differential input pair. This gain can be explained from the small signal device analysis. When these transistors are turned on and operate in the saturation region, their transconductances gmcontribute to the gain. If the transistor's gate-to-source voltage Vgsis higher than its threshold voltage Vth, and its drain-to-source voltage Vdsis equal to or higher than its gate-to-source voltage Vgs, this transistor is operating in the saturation region. In this region, assuming the signal is small, the MOS transconductance gmis d(Ids)/d(Vgs), where d indicates delta, or changes. In the small signal analysis, output voltage Voutcan be expressed as (gmVin)*Ro, where Rois the small signal out impedance. The big signal gmmay be distorted or degraded due to some non-linear effect. For large signal operation, the device still has enough transconductance gmif the operation region is in the saturation region.

Compared to the prior art, the present invention has several advantages. Firstly, the receiver can meet all reliability requirements in any operation mode. In the normal operation, the self-bias technique makes the circuit free from the fluctuation caused by processing, supply voltage, and temperature, etc. In the power-down mode, some transistors may be added to shut off all circuit paths and isolate the transients that may destroy or degrade the devices. The mixed Vddioand Vddscheme of the present invention has insured that the node voltages of the thin oxide transistors are less than Vddand the node voltages of the thick oxide devices are less than Vddio, therefore the lifetime and reliability of the devices are not compromised.

Secondly, the level-down function is combined into the receiver. Therefore, the total power consumption is reduced by removing the stand-alone, level-down converter. By minimizing the number of transistors working under high voltage, the receiver can work to high-speed IO interface up to about 800 MHz.

Thirdly, the circuit is operational even for low command mode inputs. The extension of the operation range is due to the using of native transistors (zero threshold voltage) in the circuit.