Array substrate and display panel

An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is the 371 application of PCT Application No. PCT/CN2020/113807, filed on Sep. 7, 2020, the entire contents of both of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to display technology, and more particularly, to an array substrate and a display panel.

BACKGROUND

With the application and popularization of the concept of full-screen in small and medium-sized display products, large-sized display products (e.g. TVs) are pursuing extremely fashion appearance. The TV market has moved to a “bezel-less” era and full-screen has become a new developing direction of the TV market. However, at present, large-sized full-screen display products have picture quality problem such as Mura (uneven brightness).

It should be noted that information in the background technology are provided only for acquiring better understanding of the background of the disclosure and therefore may include information that is not exist technology already known to those of ordinary skill in the art.

SUMMARY

It is an objective of the present disclosure to provide an array substrate and a display panel that is capable of reducing the picture quality problem such as Mura existing in the products and improve product quality.

A first aspect of the present disclosure provides an array substrate, wherein the array substrate includes:

a base substrate;

a plurality of pixel electrodes, arranged in a form of array on the base substrate in a row direction and a column direction, wherein each of the pixel electrodes has a plurality of first electrode strips disposed at intervals in the row direction;

a plurality of common electrodes, disposed on a same layer as the pixel electrodes, wherein each of the common electrodes has a plurality of second electrode strips disposed at intervals in the row direction, and the second electrode strips and the first electrode strips are alternatively arranged in the row direction;

a plurality of rows of first scan lines, formed between the base substrate and the pixel electrodes, wherein each row of the first scan lines is located between two adjacent rows of the pixel electrodes;

a plurality of columns of second scan lines, formed between the base substrate and the pixel electrodes, wherein each column of the second scan lines is located between two adjacent columns of the pixel electrodes and is electrically connected to the corresponding first scan line through a via hole structure, and the second scan line has a scan signal input terminal; and

a plurality of columns of data lines, formed between the base substrate and the pixel electrodes, wherein each of the data lines has a data signal input terminal, and two sides of the data line in the row direction are located within both sides of one of the pixel electrodes in the row direction.

In an exemplary embodiment of the present disclosure, distances from the two sides of the data line in the row direction to a center of the pixel electrode in the row direction are equal to each other.

In an exemplary embodiment of the present disclosure, the two sides of the data line in the row direction are located on within both sides of one of the second electrode strips in the row direction.

In an exemplary embodiment of the present disclosure, the data lines and the second scan lines are provided on a same layer.

In an exemplary embodiment of the present disclosure, a number of the common electrodes is less than a number of the pixel electrodes in each row.

In an exemplary embodiment of the present disclosure, both sides of the second scan line in the row direction are located within two sides of one of the second electrode strips in the row direction.

In an exemplary embodiment of the present disclosure, the array substrate further includes:

a plurality of rows of first common signal lines, wherein the first common signal lines and the first scan lines are disposed on a same layer, and each of the first common signal lines is located between two adjacent rows of the pixel electrodes,

wherein one row of the first common signal lines and one row of the first scan lines are disposed between every two adjacent rows of the pixel electrodes, and each of the first common signal line is electrically connected to the corresponding common electrode through a via hole structure.

In an exemplary embodiment of the present disclosure, the array substrate further includes:

one or more columns of second common signal lines, wherein the second common signal lines and the second scan lines are disposed on a same layer, each column of the second common signal lines is located between two adjacent columns of the pixel electrodes and is electrically connected to each row of the first common signal lines through a via hole structure, and both sides of the second common signal line in the row direction are located within both sides of one of the second electrode strips in the row direction,

wherein the second common signal line has a common signal input terminal.

In an exemplary embodiment of the present disclosure, a column of the second scan lines is provided between two adjacent columns of the pixel electrodes of one portion of the pixel electrodes, and a column of the second common signal lines is provided between two adjacent columns of the pixel electrodes of another portion of the pixel electrodes.

In an exemplary embodiment of the present disclosure, the array substrate further includes first metal lines and second metal lines disposed on a same layer as the first scan lines, wherein the first metal lines and the second metal lines are disconnected from the first scan lines, respectively,

wherein orthographic projections of the first metal line and the second metal line on the base substrate are located within an orthographic projection of one of the second electrode strips on the base substrate, and are located on both sides of the corresponding second scan line in the row direction respectively, or located on both sides of the corresponding second common signal line in the row direction respectively.

In an exemplary embodiment of the present disclosure, the second electrode strip of the common electrode corresponding to the data line, the second scan line or the second common signal line has a size in the row direction larger than that of the other second electrode strips in the row direction.

In an exemplary embodiment of the present disclosure, the scan signal input terminal of the second scan line, the common signal input terminal of the second common signal line and the data signal input terminal of the data line are located on a same side of the base substrate.

In an exemplary embodiment of the present disclosure, each row of the first scan lines is electrically connected to two or more columns of the second scan lines.

In an exemplary embodiment of the present disclosure, the array substrate further includes: a plurality of drive transistors, arranged in a form of array on the base substrate in the row direction and the column direction, wherein each of the drive transistors corresponds to one of the pixel electrodes,

wherein the drive transistor includes a gate electrode disposed on a same layer as the first scan line, an active layer located on a side of the gate electrode distal to the base substrate, and a source-drain electrode disposed on a same layer as the data line,

a gate insulating layer is formed between the gate electrode and the active layer, wherein the gate insulating layer covers the gate electrode and the first scan line, a passivation layer is formed between the source-drain electrode and the pixel electrode, and the passivation layer covers the source-drain electrode, the data line and the second scan line, and

the first scan line is electrically connected to the gate electrode, the data line is electrically connected to a source electrode in the source-drain electrode, and the pixel electrode is electrically connected to a drain electrode in the source-drain electrode via a via hole structure penetrating the passivation layer.

In an exemplary embodiment of the present disclosure, the array substrate further includes: an organic insulating layer, formed between the passivation layer and the pixel electrode, wherein the pixel electrode is electrically connected to the drain electrode via a via hole structure penetrating the organic insulating layer and the passivation layer.

In an exemplary embodiment of the present disclosure, the array substrate further includes: a color filter layer, formed between the passivation layer and the organic insulating layer, wherein the pixel electrode is electrically connected to the drain electrode via a via hole structure penetrating the organic insulating layer, the color filter layer and the passivation layer.

In an exemplary embodiment of the present disclosure, the first electrode strips and the second electrode strips are in a bending shape, and the first electrode strips and the second electrode strips are bent with a bending angle of 150° to 170°.

A second aspect of the present disclosure provides a display panel including the array substrate as described in any of the above.

The technical solutions provided by the present disclosure may realize the following beneficial effects:

In the array substrate and the display panel provided by the present disclosure, the pixel electrodes and the common electrodes are disposed on the same layer and interposed to each other. Such design can reduce the capacitance generated between the pixel electrodes and the common electrodes, thereby increasing the charging rate and the aperture ratio of the pixels. Furthermore, the data line is disposed on the inner side of one pixel electrode and the second scan line is disposed between two adjacent columns of pixel electrodes. Such design can increase the distance between the second scan line and the data line, thereby reducing signal crosstalk between the second scan line and the data line such that the Mura phenomenon of the screen can be reduced and the display effect can be improved.

Reference signs inFIGS.1and2:

Reference signs inFIGS.3to17:

DETAILED DESCRIPTION

To make the objects, technical solutions and advantages of the present disclosure more clear and easy to be understood, embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Note that the embodiments may be implemented in a number of different forms. A person of ordinary skill in the art could readily appreciate the fact that the manners and contents may be transformed into a variety of forms without departing from the purpose and scope of the present disclosure. Accordingly, the present disclosure should not be construed to be limited only to the contents contained in the following embodiments. If there is no conflict, the embodiments and the features in the embodiments of the present disclosure may be arbitrarily combined with each other.

In the accompanying drawings, sizes of the respective constituent elements, and thickness or region of layers are sometimes represented in an exaggerated way for the sake of clarity. Thus, one manner of the present disclosure is not necessarily limited to that size, and the shape and size of the components in the accompanying drawings do not reflect true proportions. In addition, the accompanying drawings schematically illustrate ideal examples, but one manner of the present disclosure is not limited to the shape or value shown in the accompanying drawings.

The ordinal words such as “first”, “second”, “third” are set herein to avoid confusion of constituent elements and are not restrictive of the quantity.

In this specification, for the sake of convenience, words indicating the orientation or position relationship such as “middle region”, “regions on both sides”, “on”, “inner” and “outer” are used to illustrate the position relationships of the constituent elements with reference to the accompanying drawings, only to facilitate the description of this specification and simplify the description, instead of indicating or implying that the device or element must have a specific orientation, or must be constructed and operated in a specific orientation, therefore it is not to be construed as a limitation of the present disclosure. The position relationships of the constituent elements vary appropriately depending on the orientation of the described constituent elements. Therefore, the words and phrases are not limited to those described in the specification and may be appropriately replaced according to circumstances.

In this specification, terms such as “mounting”, “connection” and “connecting” should be understood in a broad sense unless otherwise expressly specified and provided. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate member, or a connection within two components. A person of ordinary skill in the art could understand the specific meanings of the above-described terms in the present disclosure in specific cases.

In the present disclosure, unless otherwise specified, the phrase “disposed on the same layer” is used to mean that two layers, parts, components, elements or portions may be formed by the same patterning process and that the two layers, parts, components, elements or portions are generally formed of the same material.

In the present disclosure, unless otherwise specified, the expression of “patterning process” generally includes coating, exposure, development, etching of photoresist, and stripping of the photoresist, etc. The expression of “single patterning process” refers to a process of forming patterned layers, parts, components, etc., using a single mask.

In order to realize full-screen design, an embodiment of the present disclosure provides an array substrate which is applicable to a liquid crystal display panel. As shown inFIG.1, the array substrate may include horizontal scan lines10extending in a row direction X, vertical scan lines11extending in a column direction Y, and data lines12extending in the column direction Y; the vertical scan lines11are electrically connected to the horizontal scan lines10through via hole structures13respectively, and scan signal input terminals of the vertical scan lines11and data signal input terminals of the data lines12may be located on the same side of the array substrate, for example, a binding side of the array substrate, so that the other three non-display sides than the binding side in the array substrate may be made very narrow because there are no input ends of the scan lines and input ends of the data lines12, thus the screen-to-body ratio can be increased, that is, the area of a display region will be increased, to realize full-screen.

It should be noted that structures located in regions divided by the horizontal scan lines10and the data lines12inFIG.1may be subpixels14. As shown inFIGS.1and2, the vertical scan line11and the data line12are provided between two adjacent columns of subpixels14, which makes the signal crosstalk between the vertical scan line11and the data line12serious.

In addition, as shown inFIG.2, the subpixel14may include a pixel electrode140and a common electrode141. The pixel electrode140may be a slit electrode having slits140aand the common electrode may be a plate electrode without any slit. The common electrode141is located on a side of the pixel electrode140close to the a base substrate15; and such design makes the overlapping area between the pixel electrode140and the common electrode141larger, leading to large capacitance between the pixel electrode140and the common electrode141, so that the charging rate and the aperture ratio of pixels will be greatly affected, resulting in poor display effect. It should be noted that the electric field between the common electrode141and the pixel electrode140is an electric field for driving liquid crystal.

Based on the foregoing, an embodiment of the present disclosure further provides an array substrate which is applicable to a liquid crystal display panel. As shown inFIG.3, the array substrate2may be divided into a display region A and a non-display region B disposed around the display region A. The non-display region B of the array substrate2may be provided with a sealing region B1surrounding the display region A, a source electrostatic discharge region B2located close to the display region A in the sealing region B1, and a fan-out region B3located on the side of the sealing region B1distal to the display region A. The source electrostatic discharge region B2and the fan-out region B3are located in the non-display region B on the same side of the display region A (i.e., the binding region).

As shown inFIGS.4to7, the array substrate2may include a base substrate20and pixel electrodes21, common electrodes22, first scan lines23a, second scan lines23b, data lines24, drive transistors25, first common signal lines26aand second common signal lines26bprovided on the base substrate20. The pixel electrodes21, the common electrodes22, the first scan lines23a, the second scan lines23b, the data lines24, the drive transistors25, the first common signal lines26aand the second common signal lines26bare all provided in the display region A of the base substrate20.

The array substrate2of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

As shown inFIGS.5to7, the base substrate20may be a single-layer structure. For example, the base substrate20may be a glass substrate, but it is not limited thereto, and it may be a substrate made of other materials as well. Furthermore, the base substrate20may be a multi-layer structure as well, as the case may be.

As shown inFIG.4, a plurality of pixel electrodes21may be provided, and the plurality of pixel electrodes21may be arranged in the form of array in the row direction X and the column direction Y. Each of the pixel electrodes21may have a plurality of first electrode strips210disposed at intervals in the row direction X, and each of the pixel electrodes21may further have a first conductive connection portion211located on the same side of the respective first electrode strips210and connected to the respective first electrode strips210. In other words, the pixel electrodes21, as a whole, may be “comb-shaped”.

As shown inFIGS.4and8, the first electrode strips210may be bent with a bending angle α1of 150° to 170°. Specifically, the first electrode strips210may include two parts, and an included angle α1between the two parts is 150° to 160°, for example, 150°, 156°, 162°, 166°, 170°, etc. In other words, included angles α2, α3between the extension directions of the two parts and the column direction Y may be 5° to 15°, respectively, for example, 5°, 7°, 9°, 12°, 15°, etc.

As shown inFIG.4, a plurality of drive transistors25may be provided, and the plurality of drive transistors25are arranged in the form of array in the row direction X and the column direction Y. Each of the drive transistors25may correspond to a pixel electrode21. Specifically, the drive transistors25may include a gate electrode250, an active layer251and a source-drain electrode, respectively. The source-drain electrode may include a source electrode252and a drain electrode253which are electrically connected to the two ends of the active layer251, respectively. The drain electrode253is electrically connected to a corresponding pixel electrode21. For example, the gate electrode250, the source electrode252and the drain electrode253may be made of metal materials such as aluminum, molybdenum, etc.

As shown inFIG.7, the drive transistor25may be of a bottom-gate type. That is, the active layer251is located on the side of the gate electrode250distal to the base substrate20. It should be understood that a gate insulating layer may be formed between the gate electrode250and the active layer251in order to insulate the active layer251from the gate electrode250. That is to say, in the process of fabricating the array substrate2, the gate electrode250may be formed on the base substrate20firstly; thereafter, a gate insulating layer27acovering the gate electrode250is formed; then, the active layer251directly facing the gate electrode250is formed on the gate insulating layer27a. It should be noted that the gate insulating layer27ais provided as an entire layer on the base substrate20. That is to say, the gate insulating layer27amay not only cover the gate electrode250but also cover other metal structures provided on the same layer as the gate electrode250. It should be understood that the gate insulating layer27amay be an inorganic insulating layer.

In addition, the drive transistor25is formed on the side of the pixel electrode21close to the base substrate20. That is to say, in the process of fabricating the array substrate2, the drive transistor25may be formed on the base substrate20firstly; thereafter, the pixel electrode21is formed. It should be noted that a passivation layer27bmay be formed after the source-drain electrode of the drive transistor25is formed on the base substrate20and before the pixel electrode21is formed. As shown inFIG.7, the passivation layer27bcovers the source-drain electrode, and the pixel electrode21may be electrically connected to the drain electrode253through a via hole structure P penetrating the passivation layer27b.

The passivation layer27bis provided as an entire layer on the base substrate20. In other words, the passivation layer27bmay cover not only the source-drain electrode but also other metal structures provided on the same layer as the source-drain electrode. It should be understood that the passivation layer27bmay be an inorganic insulating layer.

As shown inFIGS.10,12and14, an organic insulating layer27cmay further be formed between the passivation layer27band the pixel electrodes21. That is to say, in the process of manufacturing the array substrate2, the passivation layer27bmay be formed on the base substrate20firstly; thereafter, the organic insulating layer27cmay be formed on the passivation layer27b; then the pixel electrode21is formed on the organic insulating layer27c, wherein the pixel electrode21may be electrically connected to the drain electrode253via the via hole structure P penetrating the organic insulating layer27cand the passivation layer27b.

In the embodiments of the present disclosure, by providing the organic insulating layer27c, planarization is realized for subsequent coating of the material of the pixel electrode21and as the same time, the distance between the pixel electrode21and the layer where the source-drain electrode is located may be increased, thus avoiding interference with the pixel electrode21by other signal lines on the layer at which the source-drain electrode is located.

It should be noted that the array substrate2of the embodiments of the present disclosure may not be provided with the organic insulating layer27c.

As shown inFIGS.11,13and15, a color filter layer27dmay further be formed between the passivation layer27band the organic insulating layer27c. That is to say, in the process of fabricating the array substrate2, the passivation layer27bmay be formed on the base substrate20firstly; thereafter, the color filter layer27dmay be formed on the passivation layer27b; then the organic insulating layer27cmay be formed on the color filter layer27d, wherein the pixel electrode21may be electrically connected to the drain electrode253via the via hole structure P penetrating the organic insulating layer27c, the color filter layer27dand the passivation layer27b. For example, the color filter layer27dmay include a plurality of color resistance blocks such as a red color resistance block, a green color resistance block, a blue color resistance block, etc. and the color resistance blocks may be provided in one-to-one correspondence with the pixel electrodes21.

It should be noted that the array substrate2of the embodiments of the present disclosure may not be provided with the color filter layer27d.

Wherein the drive transistor of the embodiments of the present disclosure is not limited to of a bottom gate type, it may be of a top gate type as well, as the case may be.

As shown inFIG.4, a plurality of common electrodes22may be provided, and the common electrodes22may be provided on the same layer as the pixel electrodes21, wherein each of the common electrodes22may have a plurality of second electrode strips220disposed at intervals in the row direction X, and each of the common electrodes22may further have a second conductive connection portion221located on the same side of the respective second electrode strips220and connected to the respective second electrode strips220. That is to say, the common electrodes22, as a whole, may be “comb-shaped”, wherein the second electrode strips220of the common electrode22and the first electrode strips210of the pixel electrode21are alternatively arranged in the row direction X. In other words, the common electrodes22and the pixel electrodes21located in the same row are interposed with each other, the design of which can reduce the capacitance generated between the pixel electrode21and the common electrode22, thereby increasing the charging rate and the aperture ratio of the pixels.

It should be understood that there should be a gap between, the first electrode strips210and the first conductive connection portion211of the pixel electrode21, and the second electrode strips220and the second conductive connection portion221of the common electrode22, to avoid an electrically-conductive state between the pixel electrode21and the common electrode22.

As shown inFIGS.4and9, the second electrode strip220may be bent with a bending angle β1of 150° to 170°. Specifically, the second electrode strip220may include two parts, and an included angle β1between the two parts is 150° to 160°, for example, 150°, 156°, 162°, 166°, 170°, etc. In other words, included angles β2, β3between the extension directions of the two parts and the column direction Y are 5° to 15°, respectively, for example, 5°, 7°, 9°, 12°, 15°, etc.

It should be noted that the second electrode strips220may be substantially parallel to the first electrode strips210. That is to say, the bending angle β1of the second electrode strip220may be the same as the bending angle α1of the first electrode strip210.

Based on the foregoing, by providing the first electrode strips210of the pixel electrode21and the second electrode strips220of the common electrode22in a bent shape, color shift can be reduced and the display effect can be improved.

As shown inFIG.4, the number of the common electrodes22may be smaller than the number of the pixel electrodes21in each row. That is to say, one common electrode22may be interposed with a plurality of pixel electrodes21in each row. For example, in each row, a plurality of pixel electrodes21may be provided, one common electrode22may be provided, and the one common electrode22is interposed with all of the pixel electrodes21in each row. However, it is not limited thereto, and in each row, a plurality of common electrodes22may be provided as well, and the common electrodes22may be interposed with the pixel electrodes21in one-to-one correspondence, or one-to more correspondence, depending on the case.

It should be noted that the aforementioned common electrodes22and pixel electrodes21may be transparent electrodes, and the common electrodes22may be made of metal materials such as silver nanowire, or made of semiconductor oxide such as Indium Tin Oxide (ITO).

As shown inFIG.4, the first common signal lines26amay be provided in a plurality of rows. The first common signal lines26amay be formed between the base substrate20and the common electrode22. As previously mentioned, the common electrodes22and the pixel electrodes21are provided on the same layer. That is to say, in the process of fabricating the array substrate2, the first common signal lines26amay be formed on the base substrate20firstly, then the pixel electrodes21and the common electrodes22are formed, wherein each of the first common signal lines26amay be located between two adjacent rows of the pixel electrodes21and is electrically connected to one corresponding row of the common electrodes22.

For example, as shown inFIG.4, the first common signal line26amay be provided on the same layer as the gate electrode250of the drive transistor25. In this case, the first common signal line26ais electrically connected to the common electrode22through a via hole structure Q. It should be noted that the via hole structure Q mentioned here may penetrate at least the passivation layer27band the gate insulating layer27a. When the array substrate2includes the aforementioned organic insulating layer27cand the color filter layer27d, the via hole structure Q penetrates the organic insulating layer27cand the color filter layer27din addition to the passivation layer27band the gate insulating layer27a.

As shown inFIG.4, one or more columns of second common signal lines26bmay be provided. The second common signal lines26bmay be formed between the base substrate20and the common electrodes22. As previously mentioned, the common electrodes22and the pixel electrodes21are disposed on the same layer. That is, in the process of fabricating the array substrate2, the second common signal lines26bmay be formed on the base substrate20firstly and then the pixel electrodes21and the common electrodes22may be formed, wherein each of the second common signal lines26bmay be located between two adjacent columns of the pixel electrodes21, and both sides of the second common signal line26bin the row direction X may be located within both sides of a second electrode strip220of a common electrode22in the row direction X. The second electrode stripe220may function to shield signals, that is, it can shield common signals on the second common signal line26band prevent the common signals from affecting the electric field formed between the pixel electrode21and the common electrode22.

By way of example, a shape of a portion of the second common signal line26bcorresponding to the first electrode strip210may match the shape of the first electrode strip210. That is, when the first electrode strip210is in a bending shape, the portion of the second common signal line26bcorresponding to the first electrode strip210may be in a bending shape as well and may be substantially parallel to the first electrode strip210.

The size of the second common signal line26bin the row direction X is d1, as shown inFIG.4, the size of the second electrode strip220located above the second common signal line26bin the row direction X is d2, wherein a ratio of d1to d2is greater than 0.5 and less than 1, for example, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc. However, it is not limited thereto, and the ratio of d1to d2may be less than 0.5 as well, as the case may be.

It should be noted that the second electrode strip220located above the second common signal line26bmentioned in the embodiments of the present disclosure refers to the second electrode strip220whose orthographic projection obtained on the base substrate20overlaps the orthographic projection of the second common signal line26b.

The second common signal line26bmay be electrically connected to the first common signal line26ain the respective rows. The second common signal line26bmay have a common signal input terminal. That is to say, the common signal may be transferred to the common electrodes22via the second common signal line26band the first common signal lines26ain turn. For example, the second common signal line26band the source-drain electrode of the drive transistor25may be provided on the same layer. In this case, as shown inFIG.4, the second common signal line26bmay be electrically connected to the first common signal lines26ain the respective rows through via hole structures M. It should be noted that the via hole structure M mentioned herein may penetrate the gate insulating layer27a.

In the embodiments of the present disclosure, by providing the first common signal lines26aand the second common signal lines26b, it is realized to transmit the common signals to the common electrodes22of the entire array substrate2, and at the same time, the number of common signal terminals will be greatly reduced, thereby reducing the number of leads and the cost.

It should be understood that in the embodiments of the present disclosure, only the first common signal line26amay be provided, or only the second common signal line26bmay be provided, as the case may be.

As shown inFIG.4, a plurality of rows of the first scan lines23amay be provided. The first scan lines23amay be formed between the base substrate20and the pixel electrodes21. That is, in the process of fabricating the array substrate2, the first scan lines23amay be formed on the base substrate20firstly and then the pixel electrodes21may be formed, wherein the first scan lines23amay be located between two adjacent rows of the pixel electrodes21.

For instance, the first scan line23aand the first common signal line26amay be provided on the same layer. Since the first common signal line26aand the gate electrode250of the drive transistor25may be provided on the same layer as previously mentioned, the first scan line23aand the gate electrode250of the drive transistor25are provided on the same layer as well. It should be understood that there is a gap between the first scan line23aand the first common signal line26a. In other words, the first scan line23ais not electrically connected to the first common signal line26a, but the first scan line23ais electrically connected to the gate electrode250of the drive transistor25.

A row of the first common signal lines26aand a row of the first scan lines23amay be provided between two adjacent rows of the pixel electrodes21, wherein the first scan line23ais electrically connected to the gate electrodes250of the drive transistors25corresponding to one row of the pixel electrodes21, while the first common signal line26ais electrically connected to the common electrode22corresponding to the other row of the pixel electrodes21through the via hole structure Q.

As shown inFIG.4, a plurality of columns of second scan lines23bmay be provided. The second scan lines23bmay be formed between the base substrate20and the pixel electrodes21. That is to say, in the process of fabricating the array substrate2, the second scan lines23bmay be formed on the base substrate20firstly and then the pixel electrodes21may be formed, wherein the second scan line23bmay be located between two adjacent columns of the pixel electrodes21. For example, the shape of a portion of the second scan line23bcorresponding to the first electrode strip210may match the shape of the first electrode strip210. That is, when the first electrode strip210is in a bending shape, the portion of the second scan line23bcorresponding to the first electrode strip210may be in a bending shape as well and may be substantially parallel to the first electrode strip210.

It should be noted that, since the first scan line23ais located between two adjacent rows of the pixel electrodes21and the second scan line23bis located between two adjacent columns of the pixel electrodes21, in order to avoid unnecessary electrical connection between the second scan line23band other first scan lines23a, the second scan line23band the first scan line23amay be provided on different layers, and an insulating layer may be provided between the second scan line23band the first scan line23a, wherein the second scan line23bhas a scan signal input terminal, in order to enable a scan signal received by the second scan line23bto be transmitted to a particular first scan line23a, as shown inFIG.4, a via hole structure N corresponding to the first scan line23amay be provided in the insulating layer, and the second scan line23bmay be electrically connected to the first scan line23athrough the via hole structure N. Based on this structure, the scan signal may be transmitted to the gate electrode250of the corresponding drive transistor25through the second scan line23b, the via hole structure N and the first scan line23ain turn, to control on/off of the drive transistor25.

For example, the second scan line23band the second common signal line26bmay be provided on the same layer, and since the second common signal line26band the source-drain electrode of the drive transistor25may be disposed on the same layer as previously mentioned, the second scan line23band the source-drain electrode of the drive transistor25may be disposed on the same layer as well. It should be noted that, as previously mentioned that the second scan line23bis electrically connected to the first scan line23athrough the via hole structure N, the via hole structure N mentioned here may penetrate the passivation layer27b.

In order to ensure display uniformity, the number of signal lines between the respective two adjacent columns of the pixel electrodes21in the array substrate2may be the same, so that in the embodiments of the present disclosure, as shown inFIG.4, a column of the second scan lines23bmay be provided between two adjacent columns of the pixel electrodes of one portion of the pixel electrodes, and a column of the second common signal lines26bmay be provided between two adjacent columns of the pixel electrodes21of another portion of the pixel electrodes.

It should be noted that, as mentioned earlier, one common electrode22may be interposed with a plurality of pixel electrodes21in each row. That is to say, a second electrode strip220of the common electrode22is disposed between the adjacent first electrode strips210of the pixel electrode as well. Specifically, as shown inFIGS.6,12and13, both sides of the second scan line23bin the row direction X may be located within both sides of a second electrode strip220in the row direction X. The second electrode stripe220may function to shield signals, that is, it can shield scan signals on the second scan line23b, and prevent the scan signals from affecting the electric field formed between the pixel electrode21and the common electrode22.

The size of the second scan line23bin the row direction X is d3, as shown inFIG.6, the size of the second electrode strip220located above the second scan line23bin the row direction X is d4. The ratio of d3to d4is greater than 0.5 and less than 1, for example, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc., but it is not limited thereto, and the ratio of d3to d4may be less than 0.5 as well, depending on the case.

It should be noted that the second electrode strip220located above the second scan line23bmentioned in the embodiments of the present disclosure refers to the second electrode strip220whose orthographic projection obtained on the base substrate20overlaps the orthographic projection of the second scan line23b.

In the embodiments of the present disclosure, as shown inFIG.16, each row of the first scan lines23amay be electrically connected to two or more columns of the second scan lines23b. That is to say, each row may be driven by two sets of scan signals or more scan signals, so that the scan signals may be enhanced to improve the display effect, and furthermore, such design may be used for splicing display products.

It should be noted that, each row of the first scan line23ais not limited to being electrically connected to two or more columns of the second scan lines23b, and it may be electrically connected to only one column of the second scan lines23b, as the case may be.

As shown inFIG.4, a plurality of columns of data lines24may be provided. The data lines24are formed between the base substrate20and the pixel electrodes21. That is to say, in the process of fabricating the array substrate2, the data lines24may be formed on the base substrate20firstly and then the pixel electrodes21may be formed, wherein the data lines24have data signal input terminals and the data lines24may be electrically connected to the source electrodes252of the drive transistors25respectively. That is to say, data signals may be transmitted to the source electrodes252through the data lines24.

For example, the data lines24and the second scan lines23bmay be provided on the same layer. Since the second scan line23band the source-drain electrode of the drive transistor25may be provided on the same layer as previously mentioned, the data line24and the source-drain electrode of the drive transistor25may be provided on the same layer as well.

As mentioned earlier, the second scan line23bis provided between two adjacent columns of pixel electrodes21, and in order to reduce signal crosstalk between the second scan line23band the data line24, in the embodiments of the present disclosure, as shown inFIGS.4,5,10and11, two sides of the data line24in the row direction X may be located within both sides of a pixel electrode21in the row direction X. Compared to the solution in which both the data line24and the second scan line23bare disposed between the same two adjacent columns of pixel electrodes21, such design increases the distance between the second scan line23band the data line24, thereby reducing the signal crosstalk between the second scan line23band the data line24, such that the Mura phenomenon of the screen may be reduced and the display effect may be improved.

Optionally, the distances from the two sides of the data line24in the row direction X to the center of the pixel electrode21in the row direction X are equal to each other. In other words, the data line24may be provided with respect to the center of the pixel electrode21in the row direction X, to balance the signal crosstalk on both sides of the data line24, thus ensuring uniformity of the screen.

As shown inFIGS.4,5,10and11, as mentioned above, the both sides of the data line24in the row direction X may further be located within the both sides of second electrode strips220in the row direction X. The second electrode stripe220can play the role of shielding, that is, it can shield data signals on the data line24and prevents the data signals from affecting the electric field formed between the pixel electrode21and the common electrode22.

For example, the shape of a portion of the data line24corresponding to the second electrode strip220may match the shape of the second electrode strip220. That is, when the second electrode strip220is in a bending shape, the portion of the data line24corresponding to the second electrode strip220may be in a bending shape as well and may be substantially parallel to the second electrode strip220.

The size of the data line24in the row direction X is d5, as shown inFIG.5, the size of the second electrode strip220located above the data line24in the row direction X is d6, wherein the ratio of d5to d6is greater than 0.5 and less than 1, for example, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc. However, it is not limited thereto, and the ratio of d5to d6may be less than 0.5 as well, depending on the case.

It should be noted that the second electrode strip220located above the data line24mentioned in the embodiments of the present disclosure refers to the second electrode strip220whose orthographic projection obtained on the base substrate20overlaps the orthographic projection of the data line24.

As shown inFIGS.4,6,12and13, the array substrate2of the embodiments of the present disclosure may further include first metal lines28aand second metal lines28b. The first metal lines28aand the second metal lines28bmay be provided on the same layer as the first scan lines23a, and the first metal lines28aand the second metal lines28bare disconnected from the first scan lines23arespectively, i.e., not electrically connected to the first scan lines23a.

Orthographic projections of the first metal line28aand the second metal line28bon the base substrate20may be located within an orthographic projection of a second electrode strip220on the base substrate20. As shown inFIGS.6,12and13, the first metal line28aand the second metal line28bmay be located on the two sides of the second scan line23bin the row direction X, respectively. The first metal line28aand the second metal line28bcan function to shield signals, that is, it can shield the scan signals of the second scan line23b, so as to prevent the scan signals from affecting the electric field formed between the pixel electrode21and the common electrode22. In addition, the first metal line28aand the second metal line28bmay further function to shield light.

As shown inFIG.4, when the array substrate2of the present disclosure has the aforementioned second common signal line26b, the second common signal line26bmay be provided with the first metal line28aand the second metal line28bon both sides thereof in the row direction X as well. Such design can shield the common signals, so as to prevent the common signals from affecting the electric field formed between the pixel electrode21and the common electrode22, and at the same time, can ensure the uniformity of the screen.

In addition, the data line24may be provided with the first metal line28aand the second metal line28bon both sides thereof in the row direction X as well. Such design may shield data signals, so as to prevent the data signals from affecting the electric field formed between the pixel electrode21and the common electrode22. However, it is not limited thereto, and the data line24may not be provided with any one of the first metal wire28aand the second metal wire28bon both sides thereof in the row direction X.

For example, the shape of the first metal line28aand the second metal line28bmay match the shape of the second electrode strip220, that is, when the second electrode strip220is in a bending shape, the first metal line28aand the second metal line28bmay be in a bending shape as well and may be substantially parallel to the second electrode strip220.

It should be noted that, as shown inFIG.4, the second electrode strips220of the common electrode22corresponding to the data line24, the second scan line23bor the second common signal line26bmay have a size in the row direction X larger than that of other second electrode strips220in the row direction X, so as to more effectively shield the data signals, the scan signals or the common signals, to prevent the data signals, the scan signals or the common signals from affecting the electric field formed between the pixel electrode21and the common electrode22.

The size of the second electrode strips220of the common electrode22corresponding to the data line24, the second scan line23bor the second common signal line26bin the row direction X is d7, and the size of other second electrode strips220in the row direction X is d8, wherein the ratio of d8to d7is 0.1 to 0.5, for example, 0.1, 0.2, 0.3, 0.4, 0.5, etc. However, it is not limited thereto, and the ratio of d8to d7may be greater than 0.5 and less than 1 as well, as the case may be. In the embodiments of the present disclosure, the scan signal input terminals of the second scan lines23b, the common signal input terminals of the second common signal lines26band the data signal input terminals of the data lines24mentioned above may be located on the same side of the base substrate20. For example, the base substrate20has a first side and a second side provided opposite to each other in the column direction Y. The scan signal input terminals of the second scan lines23b, the common signal input terminals of the second common signal lines26band the data signal input terminals of the data lines24are all close to the first side or the second side, such that other sides of the base substrate20can be provided with none of the scan signal input terminals of the second scan lines23b, the common signal input terminals of the second common signal lines26band the data signal input terminals of the data lines24, therefore, the said other sides of the base substrate20can be made very narrow, thus the percentage of a display region A can be increased, so as to realize a full-screen display.

It should be noted that, as shown inFIG.3, the region B4where a gate drive circuit for providing the scan signals to the second scan line23bis located, may be located in the non-display region B, specifically, located between the source electrostatic discharge region B2and the fan-out region B3, and located on the inner side of the sealing region B1. However it is not limited thereto, the gate drive circuit for providing the scan signals to the second scan line23bmay not be provided on the base substrate20and it may be electrically connected to the second scan line23bon the base substrate20by a flexible circuit board.

Furthermore, it should be further noted that the via hole structures P, Q, M and N mentioned in the present disclosure may be structures of holes with conductive materials filled therein.

An embodiment of the present disclosure further provides a display panel including the array substrate2as described in any of the above-described embodiments. It should be understood that the display panel may be a liquid crystal panel. Therefore, as shown inFIG.17, the display panel may further include an opposite substrate3provided opposite to the array substrate2, and liquid crystal molecules (not shown inFIG.17) disposed between the opposite substrate3and the array substrate2.

When the array substrate2has the aforementioned color filter layer27d, the opposite substrate3may not need to be provided with the color filter layer27d. At this time, the opposite substrate3may include a transparent substrate30and a black matrix layer31provided on the side of the transparent substrate30facing the array substrate2. The black matrix layer31is configured to shield opaque structures in the array substrate2, for example, the drive transistors25, the first scan lines23a, the second scan lines23b, the data lines24, the first common signal lines26a, the second common signal lines26b, the first metal lines28aand the second metal lines28b, etc.

It should be understood that, if the array substrate2does not have the color filter layer27das previously mentioned, the color filter layer27dmay be provided in the opposite substrate3.

An embodiment of the present disclosure further provides an electronic device including a display panel as described above.

In the embodiment of the present disclosure, the specific type of the electronic equipment is not particularly limited, as long as it is the type of electronic device that is commonly used in the field, for example, LCD TVs, mobile phones, computers, watches and so on, and a person skilled in the art may correspondingly choose the electronic device according to the concrete purpose thereof, which will not be elaborated here.

It should be noted that the electronic device further includes other necessary parts and components in addition to the display panel. Taking a display as an example, it may specifically include housing, a circuit board, a power cord, etc., for example. Those of ordinary skill in the art could make a supplementary accordingly based on to the specific use requirements of the electronic device, which will not be elaborated here.