Small signal amplifier with large signal output boost stage

A small signal amplifier with a large signal output boost stage are connected between first and second supply rails. The small signal amplifier receives first and second input signals and provides an output signal at an output node which drives a load. Under small signal conditions, the output signal varies approximately linearly with the difference voltage. However, under large signal conditions, a rail-to-rail large signal output boost stage connected to the output node is arranged to drive the output node close to the first or second supply rail as needed to provide the current demanded by the load. The large signal output boost stage is off in small signal conditions, but comes on rapidly and transfers maximum charge to the load under large signal conditions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of amplifiers, and particularly to amplifier circuits capable of providing large load currents on demand.

2. Description of the Related Art

In some applications, an amplifier may be called upon to deliver a charge to a load. For example, a typical LCD display is made up of pixels, with each pixel's optical transmission controlled by a voltage stored on a pixel capacitance. When numerous stored voltages are to be changed simultaneously, a large amount of charge must be driven into the panel to image the changes. An amplifier providing this charge may be configured to provide a desired small signal response. However, the desired small signal response may cause the output to be overdriven when large amounts of charge are called for, and thus unable to deliver the currents demanded by the load.

SUMMARY OF THE INVENTION

An amplifier circuit comprising a small signal amplifier with a large signal output boost stage is presented which addresses the problems noted above, in that it provides a desired small signal response, as well as large currents that may be demanded by the load.

The present amplifier circuit includes a small signal amplifier and a large signal output boost stage connected between first and second power supply rails. The small signal amplifier receives first and second input signals at respective input nodes and provides an output signal at an output node to which a load is connected. When the difference voltage between the input signals is less than a predetermined threshold (i.e., small signal), the output signal varies approximately linearly with the difference voltage. However, when the difference voltage is greater than the predetermined threshold (i.e., large signal), a rail-to-rail large signal output boost stage connected to the output node is arranged to drive the output node close to the first or second supply rail as needed to provide the current demanded by the load. The large signal output boost stage is off in small signal conditions, simplifying its biasing and allowing low power operation when only small signals are present. But the output stage comes on rapidly and transfers maximum charge to the load under large signal conditions. In this way, the present amplifier circuit supplies load currents that would otherwise overload the small signal amplifier.

Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is an amplifier circuit capable of providing an accurate small signal response, and of supplying large currents when a large signal response is called for by the load being driven. This is accomplished by combining a small signal amplifier with a large signal output boost stage.

An exemplary embodiment of the present amplifier circuit is shown inFIG. 1. The amplifier circuit includes a small signal amplifier comprising a first stage10and an output stage12which drives an output node14, and a large signal output boost stage16which is also connected to drive output node14. The amplifier circuit is connected between first and second power rails, labeled inFIG. 1as VIN and GND, though both rails could be at non-zero potentials.

The small signal amplifier is suitably configured as a current feedback amplifier. Here, first stage10comprises first and second transistors (Q1, Q2) of opposite polarity; Q1and Q2are shown as bipolar transistors inFIG. 1, though FETs could also be used. Q1and Q2have their bases coupled to a first input node INP which serves as the small signal amplifier's non-inverting input, and are biased to operate as emitter followers: Q1and Q2shift the level of an input signal up and down, respectively; the level-shifted results appear at nodes18and20, respectively. Opposite polarity transistors Q3and Q4are driven by nodes18and20, respectively, and serve to shift the input signal level back down (Q3) and up (Q4) to a node22, which serves as the small signal amplifier's inverting input INM.

First stage10is preferably arranged such that Q1-Q4are operated at about equal currents. A current source24provides a bias current I1; after flowing through Q1, most of I1is mirrored to Q2and the base of Q4via a current mirror26. Q1-Q4are sized such that their respective base-emitter voltages are approximately equal when conducting equal currents. As a result, the current through Q3and Q4should approximate the square root of the product of the Q1and Q2currents, which is about the same as I1.

Currents in Q3and Q4are mirrored by current mirrors28and30, respectively, such that their difference appears at a node32. Node32is very lightly loaded, so that a small difference in the Q1and Q2currents results in large signal swings at node32, limited by the compliance and output impedance of mirrors28and30.

Input node INM presents a low input impedance. As a result, if a signal presented at INM differs from zero, a net current will flow into INM and be delivered to node32by current mirrors28and30. This current not only drives output stage12, but also charges a frequency compensating capacitor C1which is preferably connected between nodes22and32.

The signal at node32drives the small signal amplifier's output stage12, which provides an output signal (OUT) to output node14. The small signal amplifier is at equilibrium when OUT=INP=INM. When arranged as shown, the signal at node32responds very rapidly to a non-zero difference voltage between INM and INP. Since INM is the inverting input, the small signal amplifier will drive OUT in opposition to the difference to try and restore equilibrium.

Output stage12is preferably configured as a totem pole output; one possible arrangement is shown inFIG. 1. A transistor MP1is connected to act as a level shifter and follower for signals at node32, providing the level shifted signal at a node34to which a bias current Ibiasis provided; Ibiasis generated, for example, with a current mirror driven by a current applied to a BIAS node. A diode-connected FET MP2is connected between node34and the base of a transistor Q5, which has its collector-emitter circuit connected between VIN and OUT. Ibiasdrives Q5by way of MP2, causing Q5to pull up on OUT. However, as the output rises, the voltage at node34also rises, and diverts some of Ibiasinto MP1when OUT approaches the voltage at node32. This diverted current causes MP1to pull up the gate of a FET MN1connected between OUT and GND by way of a resistance R1, turning MN1on. MN1's drain current is directed to the load driven by OUT by R1. The resulting voltage developed across R1pulls down the emitter of a transistor Q6, which is diode-connected to the base of Q5. Further increases in the MN1current steal away the bias current driving the base of Q5, and so restrict the positive swing of the output.

Thus, for a given voltage at node32, Ibiasdrives the base of Q5by way of MP2, and Q5acts as a follower to drive the load. As OUT approaches the voltage at node32, bias current is diverted through MP1, turning on MN1and thereby reducing the drive to Q5so as to hold the output voltage at a level fixed by the node32voltage. This local loop results in relatively low open loop output impedance, and has large bandwidth.

When node32is driven low, OUT will follow, and since it is driven low by MN1, it can approach the lower power rail GND. The Q6, R1arrangement limits the shoot through current in Q5and MN1under no load, and allows a low impedance pseudo-class A operation over a range of outputs near the lower power rail. MP2and the base-emitter voltage of Q5limit the positive output swing.

The small signal amplifier may be lightly loaded in some modes of operation, and a desire to keep the operating bias and shoot through current low results in output stage12having a relatively low current limit, with the negative drive limited by R1. However, in some applications, the load being driven by the small signal amplifier may occasionally demand large currents that exceed the capabilities of output stage12.

One such application is that of providing a “Vcom” voltage to an LCD panel comprising multiple pixels. The load (40) presented by such a panel is modeled as shown inFIG. 1. Typically, each pixel's optical transmission is controlled by a voltage stored on a pixel capacitance connected between a drive voltage and a voltage “Vcom”, here provided as the output of the present amplifier circuit; a desired Vcom voltage is applied at INP. In the greatly simplified schematic of load40shown inFIG. 1, the DRV node represents the effect of charging a large number of pixels of one row in the same direction. Doing so acts like a positive or negative step of voltage on DRV. A feedback voltage (FB) is taken which indicates the net charge put into the panel by one row of pixels. For example, if the majority of pixel capacitances in one row are driven positive during a refresh operation, the FB node will be driven positive. This positive pulse is coupled to inverting input INM, resulting in a negative swing at OUT. This output drives the panel negative, resulting in a large negative charge being swept into the distributed network of the panel. As the charge equilibrates, the overdrive at the FB node will be reduced and the amplifier circuit output will move towards the Vcom voltage applied at INP.

For some signal patterns in the LCD panel, a large amount of charge must be driven into the panel to image the changes in the pixel driving charge. Since the negative excursion of the small signal amplifier is limited to the difference between the Vcom input voltage and the supply rail, the small signal amplifier will be unable to respond linearly. When these large overdrives are present, the output voltage would ideally swing to its maximum as quickly as possible, and when the overdrive settles out the amplifier should recover to linear operation and restore normal operating voltage to the panel.

The present amplifier circuit accomplishes this non-linear response by means of large signal output boost stage16, which comprises additional output drivers that switch on when large currents are demanded by the load being driven. One possible implementation of such a stage (16) is shown inFIG. 1. A FET MP3is connected between VIN and OUT and driven by Q3's collector voltage, and a FET MN2is connected between OUT and GND and driven by Q4's collector voltage. Thus, MP3and MN2directly drive OUT, bypassing totem pole output stage12.

To ensure accurate small signal performance, large signal output boost stage16is preferably arranged to come on only during large signal conditions. One way in which this can be achieved is by making FETs MP3and MN2DMOS devices, with the FETs making up current mirror28(MP4, MP5) and30(MN3, MN4) being regular MOS devices. The threshold voltages of the DMOS devices are larger than those of the regular MOS devices; as such, little or no current flows in MP3or MN2under normal equilibrium conditions. However, if INM is driven positive, for example, causing Q4to deliver a much larger current, the voltage across MN3will rise and turn on MN2. Since MN2is much larger than MN3, once activated it can supply much more current than MN4, such that the MN2current directly drives OUT very close to the negative rail while supplying the large currents demanded by the load. Similarly, if INM is driven low, the Q3current is increased. Here, the increasing voltage across MP4turns on MP3to directly drive the output close to the positive rail.

A disadvantage of the large signal output boost stage16implementation shown inFIG. 1is that, in order to drive DMOS FETs MP3or MN2to conduct large currents, it is necessary to develop a voltage across mirrors28or30that is several volts higher than the DMOS FETs' threshold voltages. This requires an amount of current from Q3or Q4that may be unacceptably high. Moreover, variability in manufacture between the MOS and DMOS thresholds means that the actual current level needed for a given output can be quite variable.

This disadvantage is eliminated with the preferred large signal output boost stage implementation shown inFIG. 2. Here, saturating current mirrors are placed in series with mirrors28and30, to reduce and give better control over the current level required to trigger the large signal response. FETs MP6and MP7are inserted in series between VIN and FETs MP4and MP5, respectively, and FETs MN5and MN6are inserted in series between GND and FETs MN3and MN4, respectively.

MP6and MP7are biased and sized such that, under small signal conditions, they operate in the triode region and act as degeneration for MP4and MP5. However, if the small signal amplifier's operating equilibrium is disturbed by INM being pulled low, for example, a much larger current will flow from Q3. As this current rises, MP6will be pulled out of triode operation and into current saturation. This causes the gate of MP3to be pulled low. This causes DMOS FET MP3to turn on, making it capable of delivering a large current to the load while it drives the load voltage close to VIN. A protection circuit, preferably a zener diode D1, protects mirror28as well as the gate of MP3from excess voltage.

As MP6leaves the triode region and enters current saturation, the impedance at the gate of MP4will rise, causing the amplifier circuit to enter a high “gain” condition. However, since this happens during an input overload condition, the actual loop gain will be low, particularly once MP3is in triode operation, so that frequency stability should not be a problem.

As the demand for a large load current becomes satisfied, the feedback to INM should rebalance the input, allowing the MP4voltage to return to its initial voltage and thereby turn off MP3, and the amplifier circuit will resume small signal operation.

Similarly, MN5and MN6are biased and sized such that they operate in the triode region and act as degeneration for MN3and MN4under small signal conditions. If INM is overdriven in the positive direction, Q4will deliver a large current to MN5by way of MN3. This will cause MN5to go into current saturation, allowing the gate node of MN3, MN4, and MN2to swing positive. In small signal operation, this gate line is at or below the threshold voltage of MN2, so that MN2is off. In the positive overload state, however, DMOS FET MN2is turned on and is capable of delivering a large current to the load while it drives the load voltage close to GND. This maximizes the charge delivered to the load during positive overload events. Assuming that the charge delivered can restore the load's feedback voltage, the overload on INM will clear, the gate voltage of MN2will drop, and the amplifier circuit will resume small signal operation. A zener diode D2protects mirror30as well as the gate of MN2from excess voltage.

An exemplary bias current arrangement is also shown inFIG. 2. A bias current source50provides a current I2, which pulls down on the gate of a PMOS FET MP8. This causes MP8to pull down on the gate of a FET MP9, turning it on such that its current flowing in MP10rises to match bias current I2. This is an equilibrium point, with the gate voltage of MP8stabilized so as to bias MP9to match I2. This also stabilizes the gate voltage of other PMOS devices referred to VIN, such as diode-connected FET MP11, so that they deliver an image of the I2current; this mirroring arrangement might also be used to generate bias current I1from current source24, if not separately provided for. The MP11current is used to set the operating point of a multiple output mirror52(which includes FETs MN7and MN8) on the bottom power rail. The MP9gate voltage also drives MP12to deliver Ibias, which is cascoded with MP13to stabilize the current over the output voltage swing as well as shielding MP12from excess voltage.

When so arranged, the saturation level for MP6and MP7depends on their relative sizes with respect to MP9, and the saturation level for MN5and MN6depends on their relative sizes with respect to MN7.

Note that the biasing scheme shown is merely exemplary; there are myriad ways in which the necessary bias currents could be generated.

The dual saturating mirrors (MP6/MP7, MN5/MN6) placed in series with mirrors28and30as shown inFIG. 2might alternatively be implemented with single transistors, as shown inFIG. 3. The schematic ofFIG. 3is identical to that ofFIG. 2, except that MP6/MP7are replaced with a FET MP14, and MN5/MN6are replaced with a FET MN9. Operation is as before: if INM is overdriven in the positive direction, MN9goes into current saturation, allowing the gate node of MN3, MN4, and MN2to swing positive such that MN2is turned on. If INM is overdriven in the negative direction, MP14goes into current saturation, allowing the gate node of MP4, MP5and MP3to swing negative such that MP3is turned on.

As shown inFIGS. 2 and 3, each supply rail preferably comprises at least two branches, with the supply rail branches powering the small signal amplifier being different from the branches powering the large signal output boost stage.

Note that the implementations shown inFIGS. 1-3are merely exemplary; the present invention could be realized using many different circuit configurations. It is only essential that an amplifier circuit in accordance with the present invention include a small signal amplifier which provides an output signal which varies approximately linearly with the difference voltage between its input signals when the difference voltage is less than a predetermined threshold—i.e., under small signal conditions, and a large signal output boost stage connected to the output node which is arranged to drive the output close to one of the amplifier circuit's supply rails when the difference voltage is greater than the predetermined threshold—i.e., under large signal conditions, thereby enabling large currents that may be demanded by the load to be supplied.