Semiconductor device having strained channel layer and method of manufacturing the same

Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0062538, filed on May 4, 2015, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety.

BACKGROUND

1. Technical Field

Example embodiments of the present inventive concepts relate to semiconductor devices having a strained channel layer and methods of manufacturing the same.

2. Description of the Related Art

As the degree of integration of semiconductor devices has increased, the sizes of the semiconductor devices have decreased. In order to overcome limitations of device characteristics in the semiconductor devices having smaller sizes, efforts have been made to develop semiconductor devices including fin field effect transistors (FinFET) having a three-dimensional channel. In addition, in order to implement a high-performance field effect transistor, efforts have been made to develop semiconductor devices having a strained channel layer to increase the mobility of electrons or electron holes thereof.

SUMMARY

Aspects of the present inventive concepts may provide semiconductor devices having improved mobility characteristics and a method of manufacturing the same.

According to example embodiments of the present inventive concepts, semiconductor devices may include a substrate, a plurality of active fins on the substrate, the active fins including a buffer layer on the substrate and a channel layer on the buffer layer, and the channel layer having a first lattice constant higher than a second lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, a plurality of sidewall spacers on both sidewalls of the gate structure, a plurality of source/drain structures on both sides of the channel layer, and a plurality of capping layers contacting lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

The plurality of capping layers may be disposed between the sidewall spacers and the channel layer. A sidewall of respective ones of the plurality of capping layers may contact respective ones of the plurality of source/drain structures.

The plurality of capping layers may extend along the gate structure while covering the channel layer.

The plurality of capping layers may include a material preventing oxygen from being diffused into the channel layer.

The material preventing oxygen from being diffused into the channel layer may include SiN and/or SiCN.

The channel layer may be formed of a silicon-germanium compound.

The channel layer may include a plurality of regions having different germanium contents.

The channel layer may include a central portion having a first germanium content and a surface portion having a second germanium content higher than the first germanium content.

The buffer layer may be formed of a silicon-germanium compound having a first germanium content lower than a second germanium content in the channel layer.

Respective ones of the plurality of source/drain structures may include a protruding portion projecting under the plurality of sidewall spacers.

Respective ones of the plurality of capping layer may be disposed between a lower surface of respective ones of the plurality of sidewall spacers and the protruding portion of respective ones of the plurality of source/drain structures.

According to example embodiments of the present inventive concepts, semiconductor devices may include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first lattice constant higher than a second lattice constant of the buffer layer, an isolation layer disposed between the active fins, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, source/drain structures on both sides of the channel layer, and capping layers contacting lower surfaces of the sidewall spacers and having a first width substantially the same as a second width of the lower surfaces of the sidewall spacers.

The capping layers may be disposed between the sidewall spacers and the channel layer, and between the sidewall spacers and the isolation layer.

The source/drain structures may be in contact with the channel layer at both sides of the gate structure.

The source/drain structures may be formed of silicon-germanium compound and may have a first germanium content higher than a second germanium content in the channel layer.

The gate structure may include a gate insulation layer including a high-k material and a gate electrode including a metal material.

According to example embodiments of the present inventive concepts, semiconductor devices may include a substrate including a first region and a second region, first active fins disposed in the first region and including a first channel layer, second active fins disposed in the second region and may include a second channel layer having a second lattice constant lower than a first lattice constant of the first channel layer, a first gate structure covering the first channel layer and intersecting the first active fins, a second gate structure covering the second channel layer and intersecting the second active fins, first sidewall spacers disposed on both sidewalls of the first gate structure, second sidewall spacers on both sidewalls of the second gate structure, and a capping layer contacting lower surfaces of the first sidewall spacers and having a first width substantially the same as a second width of the lower surfaces of the first sidewall spacers.

The first channel layer may be formed of a silicon-germanium compound. The second channel layer may be formed of silicon. The second sidewall spacers may directly contact with the second channel layer.

The semiconductor device may further include a first buffer layer disposed below the first channel layer and a second buffer layer disposed below the second channel layer.

The first channel layer may be formed of a material having the first lattice constant higher than a third lattice constant of the first buffer layer, and the second channel layer may be formed of a material having the second lattice constant lower than a fourth lattice constant of the second buffer layer.

According to example embodiments of the present inventive concepts, methods of manufacturing semiconductor devices may include preparing a substrate having a first region and a second region, forming first active fins disposed in the first region and including a first channel layer, forming second active fins disposed in the second region and including a second channel layer having a second lattice constant lower than a first lattice constant of the first channel layer, forming a capping layer surrounding the first channel layer, forming a sacrificial oxidation layer on the second channel layer by heat-treating the substrate in an oxidation atmosphere, forming a first sacrificial gate disposed on the capping layer and intersecting the first active fins and a second sacrificial gate disposed on the sacrificial oxidation layer and intersecting the second active fins, forming first sidewall spacers disposed on both sidewalls of the first sacrificial gate and second sidewall spacers disposed on both sidewalls of the second sacrificial gate, forming first source/drain structures on a first fin recess formed by etching a portion of the capping layer and a portion of the first channel layer along side surfaces of the first sidewall spacers, and forming a first gate structure in a first gate recess formed by removing the first sacrificial gate and a portion of the capping layer.

The capping layer may be disposed to contact lower surfaces of the first sidewall spacers, and formed to have a first width substantially the same as a second width of the lower surfaces of the first sidewall spacers.

The capping layer may be formed between the first channel layer and the first sidewall spacers.

The first channel layer may be formed of a silicon-germanium compound, and the second channel layer may be formed of silicon.

The methods of manufacturing semiconductor devices may further include forming second source/drain structures in a second fin recess formed by etching a portion of the second channel layer along side surfaces of the second sidewall spacers, and forming a second gate structure in a second gate recess formed by removing the second sacrificial gate and a portion of the sacrificial oxidation layer.

DETAILED DESCRIPTION

Example embodiments of the present inventive concepts will now be described in detail with reference to the accompanying drawings.

Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the present disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

Meanwhile, when an embodiment can be implemented differently, functions or operations described in a particular block may occur in a different way from a flow described in the flowchart. For example, two consecutive blocks may be performed simultaneously, or the blocks may be performed in reverse according to related functions or operations.

FIG. 1is a plan view illustrating a semiconductor device according to example embodiments of the present inventive concepts.FIG. 2is a perspective view illustrating a semiconductor device according to example embodiments of the present inventive concepts.FIG. 3is a cross-sectional view illustrating cross sections of a semiconductor device according to example embodiments of the present inventive concepts, taken along lines X-X′ and Y-Y′ ofFIG. 1.

Referring toFIG. 1, a semiconductor device10according to example embodiments of the present inventive concepts may include a substrate11, active fins F, a gate structure50intersecting the active fins F, and source/drain structures30. The semiconductor device10may be provided as a P-type fin field effect transistor (FinFET).

Referring toFIGS. 2 and 3, the semiconductor device10according to example embodiments of the present inventive concepts may include a lower buffer layer13bformed on the substrate11, the active fins F formed on the lower buffer layer13b, an isolation layer17formed between the active fins F, and the gate structure50formed to intersect the active fins F on the active fins F. The semiconductor device10may further include sidewall spacers24formed on both sidewalls of the gate structure50, the source/drain structures30formed on both sides of the gate structure50, and an inter-layer insulation layer40formed on the source/drain structures30and the isolation layer17. The semiconductor device10may further include a capping layer20formed between the sidewall spacers24and a channel layer15. The capping layer20may extend along the gate structure50while covering the channel layer15. The capping layer20may be also formed between the sidewall spacers24and the isolation layer17. The capping layer20may be disposed to contact lower surfaces of the sidewall spacers24, and have a width substantially the same as a width of the lower surfaces of the sidewall spacers24.

The active fins F may protrude from the lower buffer layer13band extend in a first direction (e.g. a y-direction). The gate structure50may extend in a second direction (e.g. an x-direction) intersecting the first direction. The first direction and the second direction may be substantially perpendicular to each other. The gate structure50may be formed to cover an upper portion of the active fins F, for example, the channel layer15.

The active fins F may include an upper buffer layer13aand the channel layer15. The lower buffer layer13bdisposed below the upper buffer layer13amay be commonly connected to lower portions of the active fins F.

A lattice constant of the lower buffer layer13bmay be higher than a lattice constant of the substrate11. A lattice constant of the upper buffer layer13amay be equal to the lattice constant of the lower buffer layer13b. According to some embodiments of the present inventive concepts, the lattice constant of the upper buffer layer13amay be higher than the lattice constant of the lower buffer layer13b. The lattice constant of the channel layer15may be higher than the lattice constant of the upper buffer layer13a. Thus, the upper buffer layer13amay cause a compressive strain in the channel layer15disposed on the upper buffer layer13a. As a result, hole mobility in the channel layer15may be increased.

The substrate11may be provided as a semiconductor substrate. The substrate11may be provided as a silicon substrate or a silicon-on-insulator (SOI) substrate.

The upper buffer layer13aand the lower buffer layer13bmay be formed of a silicon-germanium compound. According to example embodiments of the present inventive concepts, the upper buffer layer13amay be formed of a material having the same composition as a composition of a material forming the lower buffer layer13b. On the other hand, a germanium content in the upper buffer layer13amay be higher than a germanium content in the lower buffer layer13b. The germanium content may gradually increase as a distance increases from a lower surface of the lower buffer layer13bto an upper surface of the upper buffer layer13a.

The channel layer15may be formed of a silicon-germanium compound. A germanium content in the channel layer15may be higher than the germanium content in the upper buffer layer13a. According to example embodiments of the present inventive concepts, the channel layer15may include a central portion and a surface portion, with the surface portion having a germanium content higher than a germanium content in the central portion. The germanium content may gradually increase as a distance increases from the central portion to the surface portion of the channel layer15.

An oxidation rate of a silicon-germanium compound may increase as the germanium content therein increases. Thus, an oxidation rate of the channel layer15having a relatively higher germanium content may be faster than an oxidation rate of the upper buffer layer13a. Due to the oxidation, a surface of the channel layer15may be lost and/or damaged. In a case in which such a phenomenon gets worse, a compressive strain in the channel layer15may be relieved, and thus, the hole mobility may be decreased. Thus, according to example embodiments of the present inventive concepts, the damage to the channel layer15may be reduced, and the deterioration of device characteristics may be reduced or prevented, by disposing the capping layer20, formed of a material able to prevent oxygen from being diffused, on the channel layer15so that the channel layer15is not oxidized in a subsequent process.

The capping layer20may be disposed to cover the channel layer15. The capping layer20may be formed of the material able to prevent oxygen from being diffused into the channel layer15. The capping layer20may include any one of SiN, SiCN, and combinations thereof. The capping layer20on the channel layer15may be partially removed in a subsequent process, to remain between the sidewall spacers24and the channel layer15, as illustrated inFIG. 2andFIG. 3. The capping layer20may also remain between the sidewall spacers24and the isolation layer17. The capping layer20may be disposed to contact the lower surfaces of the sidewall spacers24, and have the width substantially the same as the width of the lower surfaces of the sidewall spacers24.

The isolation layer17may be formed between the active fins F. The isolation layer17may be formed to cover a lower portion of the active fins F and expose the channel layer15of the active fins F. According to example embodiments of the present inventive concepts, the isolation layer17may be formed such that an upper surface of the isolation layer17may be at substantially the same height as a height of an upper surface of the upper buffer layer13a. In some example embodiments of the present inventive concepts, the isolation layer17may be formed such that the upper surface of the isolation layer17may be at a height different from the height of the upper surface of the upper buffer layer13a.

The source/drain structures30may be disposed on both sides of the channel layer15. The source/drain structures30may be formed in a recess from which the channel layer15has been removed, along the side surfaces of the sidewall spacers24. A lower surface of the recess may be at substantially the same height as the height of the upper surface of the upper buffer layer13a. In some embodiments of the present inventive concepts, the source/drain structures30may be formed in a recess from which the channel layer15and a portion of the upper buffer layer13ahave been removed. According to example embodiments of the present inventive concepts, the source/drain structures30may be formed in a recess from which a portion of the channel layer15has been removed. The source/drains30may be provided as elevated source/drain structures such that an upper surface of the source/drain structures30may be at a height higher than a height of an upper surface of the channel layer15. The source/drain structures30may be formed of a silicon-germanium compound, and may have a germanium content higher than a germanium content in the channel layer15.

The gate structure50may be disposed on the active fins F while intersecting the active fins F. The gate structure50may include a gate insulation layer51, a lower gate electrode53, and an upper gate electrode55. The gate insulation layer51may contain, for example, a silicon oxide, a silicon nitride, and/or a high-K material. The high-K material may contain, for example, HfO2, ZrO2Al2O3, and/or Ta2O5. The lower gate electrode53may include, for example, a metal nitride such as TiN, TaN, TiAlN, and/or WN. The upper gate electrode55may include, for example, a metal material such as Ti, Ta, Al, Mo, and/or W.

FIG. 4is a cross-sectional view illustrating cross sections of a semiconductor device according to example embodiments of the present inventive concepts.

In detail,FIG. 4is the cross-sectional view illustrating cross sections of a semiconductor device including source/drain structures30′ having a structure different from a structure of the source/drain structures30of the semiconductor device10described with reference toFIG. 2andFIG. 3.FIG. 3is a cross-sectional view illustrating cross sections of the semiconductor device10ofFIG. 1taken along lines X-X′ and Y-Y′. Descriptions provided above will be omitted, and elements not described above will be described below.

Referring toFIG. 4, the source/drain structures30′ disposed on both sides of a channel layer IS may have a structure including a protruding portion projecting downwardly from sidewall spacers24. Sidewalls of the channel layer15are illustrated as being inclined, but are not limited thereto. Thus, a capping layer20may be disposed between a lower surface of the sidewall spacers24and the protruding portion of the source/drain structures30′. The capping layer20may be disposed to contact the lower surfaces of the sidewall spacers24, and have a width substantially the same as a width of the lower surfaces of the sidewall spacers24.

FIG. 5is a plan view illustrating a semiconductor device according to example embodiments of the present inventive concepts.FIG. 6is a perspective view illustrating a semiconductor device according to example embodiments of the present inventive concepts.FIG. 7Ais a cross-sectional view illustrating cross sections of the semiconductor device ofFIG. 5taken along lines A-A′ and B-B′.FIG. 7Bis a cross-sectional view illustrating cross-sections of the semiconductor device ofFIG. 5taken along lines C-C′ and D-D′.

Referring toFIG. 5, a semiconductor device100may include a substrate101having a first region I and a second region II, a first transistor100A formed in the first region I, and a second transistor100B formed in the second region II. The first region I may be provided as an N-well region doped with an N-type impurity, and the second region II may be provided as a P-well region doped with a P-type impurity. The first transistor100A may be provided as a P-type field effect transistor, and the second transistor100B may be provided as an N-type field effect transistor. The first transistor100A and the second transistor100B may be provided as fin field effect transistors (FinFET).

The first transistor100A may include first active fins F1, a first gate structure150intersecting the first active fins F1, and first source/drain structures130disposed on both sides of the first gate structure150. The second transistor100B may include second active fins F2, a second gate structure250intersecting the second active fins F2, and second source/drain structures232disposed on both sides of the second gate structure250.

Referring toFIGS. 6, 7A, and 7B, the first transistor100A formed in the first region I of the semiconductor device100according to example embodiments of the present inventive concepts may include a first lower buffer layer103bformed on the substrate101, the first active fins F1formed on the first lower buffer layer103b, and the first gate structure150formed on the first active fins F1. The first transistor100A may further include first sidewall spacers124formed on both sidewalls of the first gate structure150and first source/drain structures130formed on both sides of the first gate structure150. The first transistor100A may further include a first inter-layer insulation layer140formed on the first source/drain structures130and a first isolation layer110. The first transistor100A may further include a capping layer115formed between the first sidewall spacers124and a first channel layer105. The capping layer115may be also formed between the first sidewall spacers124and the first isolation layer110.

The first active fins F1may protrude from the first lower buffer layer103band extend in a first direction (e.g. a y-direction). The first gate structure150may extend in a second direction (e.g. an x-direction) intersecting the first direction. The first gate structure150may be formed to cover upper portions of the first active fins F1.

The first active fins F1may include a first upper buffer layer103aand the first channel layer105. The first lower buffer layer103bdisposed below the first upper buffer layer103amay be commonly connected to lower portions of the first active fins F1.

A lattice constant of the first lower buffer layer103bmay be higher than a lattice constant of the substrate101. A lattice constant of the first upper buffer layer103amay be equal to the lattice constant of the first lower buffer layer103b. In some embodiments of the present inventive concepts, the lattice constant of the first upper buffer layer103amay be higher than the lattice constant of the first lower buffer layer103b. A lattice constant of the first channel layer105may be higher than the lattice constant of the first upper buffer layer103a. Thus, the first upper buffer layer103amay cause a compressive strain in the first channel layer105disposed on the upper buffer layer103a. As a result, hole mobility in the first channel layer105may be increased.

The substrate101may be provided as a semiconductor substrate. The substrate101may be provided as a silicon substrate or a silicon-on-insulator (SOI) substrate.

The first upper buffer layer103aand the first lower buffer layer103bmay be formed of a silicon-germanium compound. According to example embodiments of the present inventive concepts, the first upper buffer layer103amay be formed of a material having the same composition as a composition of a material forming the first lower buffer layer103b. In some embodiments of the present inventive concepts, a germanium content in the first upper buffer layer103amay be higher than a germanium content in the first lower buffer layer103b. The germanium content may gradually increase as a distance increases from a lower surface of the first lower buffer layer103bto an upper surface of the first upper buffer layer103a.

The first channel layer105may be formed of a silicon-germanium compound. A germanium content in the first channel layer105may be higher than the germanium content in the first upper buffer layer103a. The first channel layer105may include a central portion and a surface portion having a germanium content higher than a germanium content in the central portion. According to example embodiments of the present inventive concepts, the germanium content may gradually increase as a distance increases from the central portion to the surface portion of the first channel layer105.

An oxidation rate of a silicon-germanium compound may increase as the germanium content therein increases. Thus, an oxidation rate of the first channel layer105having a relatively higher germanium content may be faster than an oxidation rate of the first upper buffer layer103a. Due to the oxidation, a surface of the first channel layer105may be lost and/or damaged. In a case in which such a phenomenon gets worse, a compressive strain in the first channel layer105may be relieved, and thus, the electron hole mobility may be decreased. Thus, according to example embodiments of the present inventive concepts, the damage to the first channel layer105may be reduced, and the deterioration of device characteristics may be prevented or reduced, by disposing the capping layer115, formed of a material able to prevent the first channel layer105from being oxidized in a subsequent process, on the first channel layer105. The capping layer115may include any one of SiN, SiCN, and combinations thereof.

The capping layer115on the first channel layer105may be partially removed in a subsequent process, to remain between the first sidewall spacers124and the first channel layer105, as illustrated inFIG. 6andFIG. 7A. The capping layer115may also remain between the first sidewall spacers124and the first isolation layer110. The capping layer115may extend along the first gate structure150while intersecting the first channel layer105.

The first isolation layer110may be formed between the first active fins F1. The first isolation layer110may be formed such that upper portions of the first active fins F1are protruded over an upper surface of the first isolation layer110. According to example embodiments of the present inventive concepts, the first isolation layer110may be formed such that an upper surface of first isolation layer110may be at substantially the same height as a height of an upper surface of the first upper buffer layer103a. In some embodiments of the present inventive concepts, the first isolation layer110may be formed such that the upper surface of the first isolation layer110may be at a height different from the height of the upper surface of the first upper buffer layer103a.

The first source/drain structures130may be disposed on both sides of the first channel layer105. The first source/drain structures130may be formed in a first fin recess from which the first channel layer105has been removed, along the side surfaces of the first sidewall spacers124. A lower surface of the first fin recess may be at substantially the same height as the height of the upper surface of the first upper buffer layer103a. In some embodiments of the present inventive concepts, the first source/drain structures130may be formed in a first fin recess from which the first channel layer105and a portion of the first upper buffer layer103ahave been removed. According to example embodiments of the present inventive concepts, the first source/drain structures130may be formed in a first fin recess from which a portion of the first channel layer105has been removed. The first source/drains130may be provided as elevated source/drain structures such that an upper surface of the first source/drain structures130may be at a height higher than a height of an upper surface of the first channel layer105. The first source/drain structures130may be formed of a silicon-germanium compound, and have a germanium content higher than a germanium content in the first channel layer105. The first source/drain structures130may be doped with a P-type impurity.

The first gate structure150may be disposed on the first active fins F1while intersecting the first active fins F1. The first gate structure150may include a first gate insulation layer151, a first lower gate electrode153, and a first upper gate electrode155. The first gate insulation layer151may contain a silicon oxide, a silicon nitride, or a high-K material. The high-K material may contain, for example, HfO2, ZrO2Al2O3, and/or Ta2O5. The first lower gate electrode153may include, for example, a metal nitride such as TiN, TaN, TiAlN, and/or WN. The first upper gate electrode155may include, for example, a metal material such as Ti, Ta, Al, Mo, and/or W.

Referring toFIGS. 6, 7A, and 7Bagain, a second transistor100B formed in a second region II of the semiconductor device100may include a second lower buffer layer203bformed on the substrate101, second active fins F2formed on the second lower buffer layer203b, and a second gate structure250formed on the second active fins F2. The second transistor100B may further include second sidewall spacers224formed on both sidewalls of the second gate structure250, and second source/drain structures232formed on both sides of the second gate structure250. The second transistor100B may further include a second inter-layer insulation layer240formed on the second source/drain structures232and a second isolation layer210.

The second active fins F2may protrude from the second lower buffer layer203band extend in a first direction (e.g. a y-direction). The second gate structure250may extend in a second direction (e.g. an x-direction) intersecting the first direction. The second gate structure250may be formed to cover upper portions of the second active fins F2.

The second active fins F2may include an upper buffer layer203aand a second channel layer208. The second lower buffer layer203bdisposed below the second upper buffer layer203amay be commonly connected to lower portions of the second active fins F2.

A lattice constant of the second lower buffer layer203bmay be higher than a lattice constant of the substrate101. A lattice constant of the second upper buffer layer203amay be equal to the lattice constant of the second lower buffer layer203b. In some embodiments of the present inventive concepts, the lattice constant of the second upper buffer layer203amay be lower than the lattice constant of the second lower buffer layer203b. A lattice constant of the second channel layer208may be lower than the lattice constant of the second upper buffer layer203a. Thus, the second upper buffer layer203amay cause a tensile strain in the second channel layer208disposed on the second upper buffer layer203a. As a result, electron mobility in the second channel layer208may be increased.

The substrate101may be provided as a semiconductor substrate. The substrate101may be provided as a silicon substrate or a silicon-on-insulator (SOI) substrate.

The second upper buffer layer203aand the second lower buffer layer203bmay be formed of a silicon-germanium compound. According to example embodiments of the present inventive concepts, the second upper buffer layer203amay be formed of a material having substantially the same composition as a composition of a material forming the second lower buffer layer203b. On the other hand, a germanium content in the second upper buffer layer203amay be lower than a germanium content in the second lower buffer layer203b. The germanium content may gradually decrease as a distance increases from a lower surface of the second lower buffer layer203bto an upper surface of the second upper buffer layer203a. The second upper buffer layer203aand the second lower buffer layer203bmay be formed of a silicon-germanium compound having substantially the same composition as a composition of a silicon-germanium compound forming the first upper buffer layer103aand the first lower buffer layer103b.

The second channel layer208may be formed of silicon or a silicon-germanium compound having a germanium content lower than a germanium content in the second upper buffer layer203a.

The second isolation layer210may be formed between the second active fins F2. The second isolation layer210may be formed such that upper portions of the second active fins F2are protruded over an upper surface of the first isolation layer210. According to example embodiments of the present inventive concepts, the second isolation layer210may be formed such that an upper surface of the second isolation layer210may be at substantially the same height as a height of an upper surface of the second upper buffer layer203a. In some embodiments of the present inventive concepts, the upper surface of the second isolation layer210may be at a height different from the height of the upper surface of the second upper buffer layer203a.

The second source/drain structures232may be disposed on both sides of the second channel layer208. The second source/drain structures232may be formed in a second fin recess from which the second channel layer208has been removed, along side surfaces of the second sidewall spacers224. A lower surface of the second fin recess may be formed to be at substantially the same height as the height of the upper surface of the second upper buffer layer203a. In some embodiments of the present inventive concepts, the second source/drain structures232may be formed in a second fin recess from which the second channel layer208and a portion of the second upper buffer layer203ahave been removed. According to example embodiments of the present inventive concepts, the second source/drain structures232may be formed in a second fin recess from which a portion of the second channel layer208has been removed. The second source/drains232may be provided as elevated source/drain structures such that an upper surface of the second source/drain structures232may be at a height higher than a height of an upper surface of the second channel layer208. The second source/drain structures232may be formed of silicon. The second source/drain structures232may be doped with an N-type impurity.

The second gate structure250may be disposed on the second active fins F2while intersecting the second active fins F2. The second gate structure250may include a second gate insulation layer251, a second lower gate electrode253, and a second upper gate electrode255. The second gate insulation layer251may contain a silicon oxide, a silicon nitride, or a high-K material. The high-K material may contain, for example, HfO2, ZrO2Al2O3, and/or Ta2O5. The second lower gate electrode253may include, for example, a metal nitride such as TiN, TaN, TiAlN, and/or WN. The second upper gate electrode255may include, for example, a metal material such as Ti, Ta, Al, Mo, and/or W.

FIGS. 8 through 16Bare cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments of the present inventive concepts. The first region I and second region II described with respect toFIGS. 8 through 16Bare as illustrated inFIG. 5.

Referring toFIG. 8, a first buffer layer103and a second buffer layer203may be formed on a substrate101including a first region I and a second region II. Subsequently, a first channel layer105may be formed on the first buffer layer103, and a second channel layer208may be formed on the second buffer layer203.

The substrate may be provided as, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate. The first buffer layer103formed in the first region I and the second buffer layer203formed in the second region II may be formed of a material having a lattice constant higher than a lattice constant of a material forming the substrate101. The first buffer layer103and the second buffer layer203may be formed of, for example, a silicon-germanium compound. The first buffer layer103and the second buffer layer203may be respectively formed of silicon-germanium compounds having equal compositions. The first buffer layer103may be doped with an N-type impurity, and the second buffer layer203may be doped with a P-type impurity.

The first buffer layer103and the second buffer layer203may be formed using an epitaxial growth process. The epitaxial growth process may be provided as a chemical vapor deposition (CVD) process or a molecular-beam epitaxy (MBE) process.

Subsequently, the first channel layer105may be formed on the first buffer layer103, and the second channel layer208may be formed on the second buffer layer203. The first channel layer105may be formed of a material having a lattice constant higher than a lattice constant of a material forming the first buffer layer103, and the second channel layer208may be formed of a material having a lattice constant lower than a lattice constant of a material forming the second buffer layer203. For example, the first channel layer105may be formed of a silicon-germanium compound having a germanium content higher than a germanium content in the first buffer layer103, and the second channel layer208may be formed of silicon or a silicon-germanium compound having a germanium content lower than a germanium content in the second buffer layer203. The first channel layer105may be doped with an N-type impurity, and the second channel layer208may be doped with a P-type impurity.

The first channel layer105and the second channel layer208may be formed using an epitaxial growth process. The epitaxial growth process may be provided as a chemical vapor deposition (CVD) process or a molecular-beam epitaxy (MBE) process. The first channel layer105and the second channel layer208may be formed respectively using separate epitaxial growth processes.

Referring toFIGS. 9A and 9B, first active fins F1and second active fins F2may be formed on the substrate101including the first region I and the second region II.

First, the first active fins F1may be formed by anisotropically etching the first channel layer105and a portion of the first buffer layer103using a mask pattern in the first region I. The second active fins F2may be formed by anisotropically etching the second channel layer208and a portion of the second buffer layer203using a mask pattern in the second region II. After the anisotropic etching process is completed, the first buffer layer103may be divided into a first upper buffer layer103aand a first lower buffer layer103b, and the second buffer layer203may be divided into a second upper buffer layer203aand a second lower buffer layer203b. The first upper buffer layer103aand the first channel layer105may form the first active fins F1. The second upper buffer layer203aand the second channel layer208may form the second active fins F2. According to example embodiments of the present inventive concepts, the first buffer layer103and the second buffer layer203may be anisotropically etched entirely such that the first lower buffer layer103band the second lower buffer layer203bmay not remain. The first active fins F1and the second active fins F2are illustrated as having shapes having constant widths, but the widths thereof may become narrower as a distance increases from a lower portion to an upper portion thereof in example embodiments of the present inventive concepts.

Subsequently, a trench between the first active fins F1and a trench between the second active fins F2may be filled with an insulation material, and then a flattening process may be conducted. The insulation material filling the trench may be partially removed, such that a first isolation layer110exposing an upper portion of the first active fins F1and a second isolation layer210exposing an upper portion of the second active fins F2may be formed. Heights of upper portions of the first isolation layer110and the second isolation layer210are illustrated so that the first channel layer105and the second channel layer208are entirely exposed, but are not limited thereto. The process in which the insulation material is removed may include a process in which the mask pattern is removed.

Referring toFIGS. 10A and 10B, a capping layer115conformally covering the first channel layer105and the second channel layer208may be formed in the first region I and the second region II. Subsequently, a protection pattern117covering the capping layer115may be formed in the first region I.

The capping layer115may be formed of a material able to prevent oxygen from being diffused. For example, the capping layer115may be formed of any one of SiN, SiCN, and combinations thereof. The protection pattern117may be formed of a material having an etching selectivity with respect to the capping layer115. For example, the protection pattern117may be formed of a silicon oxide.

The capping layer115may be formed using, for example, an atomic layer deposition (ALD) process.

Referring toFIGS. 11A and 11B, a sacrificial oxidation layer218may be formed on the second channel layer208in the second region II.

First, a process in which the capping layer115on the second channel layer208in the second region is removed may be conducted. Subsequently, the substrate101may be heat-treated in an oxidation atmosphere, in order to form the sacrificial oxidation layer218on the second channel layer208. In the heat-treatment process, a surface of the second channel layer208may be oxidized, such that the sacrificial oxidation layer218may be formed. For example, when the second channel layer208is formed of silicon, the sacrificial oxidation layer218may be formed of a silicon oxide. The heat-treatment process may be provided, for example, as a radical oxidation process or a thermal oxidation process. In the heat-treatment process, the first channel layer105in the first region may not be oxidized because the first channel layer105may be covered by the capping layer115. However, a surface of the capping layer115may be partially oxidized. For example, when the capping layer115is formed of SiN, a SiON layer may be formed on the surface of the capping layer115.

Referring toFIGS. 12A and 12B, a first sacrificial gate120and a second sacrificial gate220may be formed in the first region I and the second region II.

First, a sacrificial gate material may be deposited on the capping layer115in the first region I and on the sacrificial oxidation layer218in the second region II. Subsequently, a first gate mask pattern122may be formed on the sacrificial gate material in the first region I, and a second gate mask pattern222may be formed on the sacrificial gate material in the second region II. Next, the first sacrificial gate120and the second sacrificial gate220may be formed by anisotropically etching the sacrificial gate material using the first gate mask pattern122and the second gate mask pattern222. Subsequently, the sacrificial oxidation layer218may be partially removed from the second region II by conducting a cleaning process in which a by-product of the etching may be removed. In detail, a portion of the sacrificial oxidation layer218not disposed below the second sacrificial gate220may be removed.

The first sacrificial gate120and the second sacrificial gate220may be formed in positions corresponding to a first gate structure150and a second gate structure250(seeFIG. 7A), and removed in a subsequent process. The first sacrificial gate120and the second sacrificial gate220may include, for example, polysilicon.

Referring toFIGS. 13A and 13B, first sidewall spacers124and second sidewall spacers224may be formed respectively in the first region I and the second region II.

First, spacer insulation films having constant thicknesses may be formed to cover the first sacrificial gate120and the second sacrificial gate220. Then, the first sidewall spacers124may be formed on both sidewalls of the first sacrificial gate120, and the second sidewall spacers224may be formed on both sidewalls of the second sacrificial gate220, by conducting an anisotropic etching process. The first sidewall spacers124may be formed on the capping layer115, and the second sidewall spacers224may be formed on the second channel layer208. The first and second sidewall spacers124and224may be formed, for example, of a silicon oxide, a silicon nitride, or combinations thereof.

Referring toFIGS. 14A and 14B, first source/drain structures130and second source/drain structures232may be formed respectively in the first region I and the second region II, and a first inter-layer insulation layer140and a second inter-layer insulation layer240may be formed respectively in the first region I and the second region II.

First fin recesses may be formed on both sides of the first channel layer105by etching a portion of the capping layer115and a portion of the first channel layer105along sidewalls of the first sidewall spacers124, using the first gate mask pattern122and the first sidewall spacers124as an etching mask. An epitaxial layer may be grown in the first fin recesses by conducting a selective epitaxial growth (SEG) process, to form the first source/drain structures130. The first source/drain structures130may be provided as elevated source/drain structures, of which an upper surface may be at a height higher than a height of an upper surface of the first channel layer105. The first source/drain structures130may be formed of, for example, a silicon-germanium compound, and doped with a P-type impurity. The first source/drain structures130may be doped with the P-type impurity in-situ in the selective epitaxial growth process. In example embodiments of the present inventive concepts, the first fin recesses are illustrated as being formed at substantially the same position as a position of an upper surface of the first upper buffer layer103a, but the present inventive concepts are not limited thereto.

Second fin recesses may be formed on both sides of the second channel layer208by etching a portion of the second channel layer208along sidewalls of the second sidewall spacers224, using the second gate mask pattern222and the second sidewall spacers224as an etching mask. An epitaxial layer may be grown in the second fin recesses by conducting a selective epitaxial growth (SEG) process, to form the second source/drain structures232. The second source/drain structures232may be provided as elevated source/drain structures, of which an upper surface may be at a height higher than a height of an upper surface of the second channel layer208. The second source/drain structures232may be formed of, for example, silicon, and doped with an N-type impurity. The second source/drain structures232may be doped with the N-type impurity in situ in the selective epitaxial growth process. In example embodiments of the present inventive concepts, the second fin recesses are illustrated as being formed at substantially the same position as a position of an upper surface of the second upper buffer layer203a, but the present inventive concepts are not limited thereto.

Subsequently, insulation materials covering the first and second sidewall spacers124and224and the first and second source/drain structures130and232may be formed, and then a flattening process may be conducted so that upper surfaces of the first and second gate mask patterns122and222are exposed, to form the first and second inter-layer insulation layers140and240.

Referring toFIGS. 15A and 15B, a first gate recess RS1and a second gate recess RS2may be formed by removing the first and second sacrificial gates120and220.

In detail, the first gate mask pattern122and the first sacrificial gate120may be selectively removed from the first region I, and then the capping layer115disposed below the first sacrificial gate120may be partially removed, to form the first gate recess RS1exposing a portion of the first channel layer105and a portion of the isolation layer110. Here, the capping layer115may be disposed to contact lower surfaces of the first sidewall spacers124, and formed to have substantially the same width as a width of a lower surface of the first sidewall spacers124.

The second gate mask pattern222and the second sacrificial gate220may be selectively removed from the second region II, and then the sacrificial oxidation layer218disposed below the second sacrificial gate220may be removed, to form the second gate recess RS2exposing a portion of the second channel layer208and a portion of the isolation layer210.

Processes of removing the first and second gate mask patterns122and222, the first and second sacrificial gates120and220, the capping layer115, and the sacrificial oxidation layer218may be conducted using at least one of a dry etching process and a wet etching process.

Referring toFIG. 16AandFIG. 16B, the first gate structure150and the second gate structure250may be formed respectively in the first gate recess RS1and the second gate recess RS2.

A first gate insulation layer151may be formed substantially conformally along a sidewall and a lower surface of the first gate recess RS1. A first lower gate electrode153and a first upper gate electrode155may be sequentially formed on the first gate insulation layer151.

A second gate insulation layer251may be formed substantially conformally along a sidewall and a lower surface of the second gate recess RS2. A second lower gate electrode253and a second upper gate electrode255may be sequentially formed on the second gate insulation layer251.

The first and second gate insulation layers151and251may include a silicon oxide, a silicon nitride, or a high-K material. The first and second lower gate electrodes153and253may include, for example, a metal nitride, and the first and second upper gate electrodes155and255may include, for example, a metal material.

Subsequently, the semiconductor device illustrated inFIG. 6may be manufactured by conducting a planarization process so that upper surfaces of the first and second inter-layer insulation layers140and240are exposed.

FIGS. 17A and 17Bare cross-sectional views illustrating a semiconductor device according to example embodiments of the present inventive concepts.

In detail, the semiconductor device ofFIGS. 17A and 17Bis different from the semiconductor device100described above with reference toFIGS. 6, 7A, and 7B, in that the semiconductor device ofFIGS. 17A and 17Bhas source/drain structures130′ and232′ having structures different from structures of the source/drain structures of the semiconductor device100. Descriptions provided above will be omitted, and elements which are different from those described above will be described below.

Referring toFIGS. 17A and 17B, the first source/drain structures130′ disposed on both sides of a first channel layer115may have a structure including a protruding portion projecting downwardly from a first sidewall spacer124. A sidewall of the first channel layer105is illustrated as being inclined, but is not limited thereto. Thus, a capping layer115may be disposed between a lower surface of the first sidewall spacers124and the protruding portion of the first source/drain structures130′. In addition, the second source/drain structures232′ disposed on both sides of a second channel layer208may have a structure including a protruding portion projecting downwardly from a second sidewall spacer224. A sidewall of the second channel layer208is illustrated as being inclined, but is not limited thereto.

FIG. 18is a circuit diagram of an inverter including a semiconductor device according to example embodiments of the present inventive concepts. In detail, the semiconductor device illustrated inFIG. 18may be a complementary metal-oxide-semiconductor (CMOS) inverter.

Referring toFIG. 18, the CMOS inverter may be configured of a P-type metal-oxide-semiconductor (PMOS) field effect transistor TP1and an N-type metal-oxide-semiconductor (NMOS) field effect transistor TN1. The PMOS field effect transistor TP1and the NMOS field effect transistor TN1may be connected in series between a power supply voltage line Vdd and a ground voltage line Vss. Input signals IN may be commonly input to gates of the PMOS field effect transistor TP1and the NMOS field effect transistor TN1. In addition, output signals OUT may be commonly output from drains of the PMOS field effect transistor TP1and the NMOS field effect transistor TN1. The CMOS inverter may output the output signal OUT by inverting the input signal IN. In detail, when a “high” logic value is input as the input signal IN of the inverter, a “low” logic value may be output as the output signal OUT, and when a “low” logic value is input as the input signal of the inverter, a “high” logic value may be output as the output signal OUT. The aforementioned transistors may be configured of the semiconductor device according to various example embodiments of the present inventive concepts described above.

FIG. 19is a circuit diagram of a NAND gate cell including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG. 19, the NAND gate cell may be configured to receive two input signals M and N and output a signal Q performing a NAND operation. The NAND gate cell may be configured of a PMOS transistor TP1transmitting a “high” logic value to an output terminal Q when the input signal M has a “low” logic value, NMOS transistors TN1and TN2turned on and transmitting “low” logic value to the output terminal Q when both the input signals M and N have “high” logic values, and a PMOS transistor TP2transmitting a “high” logic value to the output terminal Q when the input signal N has a “low” logic value.

When both the input signals M and N have “high” logic values, the PMOS transistors TP1and TP2are turned off, and the NMOS transistors TN1and TN2are turned on, such that a “low” logic value may be output to the output terminal Q.

When both the input signals M and N have “low” logic values, the PMOS transistors TP1and TP2are turned on, and the NMOS transistors TN1and TN2are turned off, such that a “high” logic value is output to the output terminal Q.

The aforementioned transistors may be configured of the semiconductor device according to various example embodiments of the present inventive concepts described above.

FIG. 20is a circuit diagram of an SRAM cell including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG. 20, the SRAM cell may be configured of a first pull-down transistor TN1, a second pull-down transistor TN2, a first pull-up transistor TP1, a second pull-up transistor TP2, a first pass transistor TN3, and a second pass transistor TN4. Here, sources of the first and second pull-down transistors TN1and TN2may be connected to a ground voltage line Vss, and sources of the first and second pull-up transistors TP1and TP2may be connected to a power supply voltage line Vdd.

In addition, the first pull-down transistor TN1configured of an NMOS field effect transistor and the first pull-up transistor TP1configured of a PMOS field effect transistor may be connected in series to configure a first inverter. Further, the second pull-down transistor TN2configured of an NMOS field effect transistor and the second pull-up transistor TP2configured of a PMOS field effect transistor may be connected in series to configure a second inverter. An output terminal of the first inverter may be connected to a source of the first pass transistor TN3, and an output terminal of the second inverter may be connected to a source of the second pass transistor TN4. In addition, an input terminal of the first inverter may be connected to the output terminal of the second inverter, and an input terminal of the second inverter may be connected to the output terminal of the first inverter. As a result, the first inverter and the second inverter may form a latch circuit. A drain of the first pass transistor TN3may be connected to a first bit line BL, and the second pass transistor TN4may be connected to a second bit line/BL. Gates of the first and second pass transistors TN3and TN4may be connected to a word line WL. The aforementioned transistors may be configured of the semiconductor device according to various example embodiments of the present inventive concepts described above.

FIG. 21is a block diagram illustrating a storage device including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG. 21, a storage device1000according to example embodiments of the present inventive concepts may include a controller1010communicating with a HOST, and memories1020-1,1020-2, and1020-3storing data.

The HOST communicating with the controller1010may be provided as various types of electronic devices such as smartphones, digital cameras, desktop computers, laptop computers, media players, and the like. The controller1010may receive request for writing data or reading data from the HOST, and generate a command CMD to store data in the memories1020-1,1020-2, and1020-3or retrieve data from the memories1020-1,1020-2, and1020-3. The controller1010or the memories1020-1,1020-2, and1020-3may include the semiconductor device according to the various example embodiments of the present inventive concepts described above.

As illustrated inFIG. 21, one or more memories1020-1,1020-2, and1020-3may be connected to the controller1010in parallel in the storage device1000. The storage device1000with relatively high capacity such as solid state drive (SSD) may be implemented by connecting a plurality of the memories1020-1,1020-2, and1020-3to the controller1010in parallel.

FIG. 22is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG. 22, an electronic device2000according to example embodiments of the present inventive concepts may include a communications unit2010, an input unit2020, an output unit2030, a memory2040, and a processor2050.

The communications unit2010may include a wired/wireless communications module and may include a wireless internet module, a short-range communications module, a global positioning system (GPS) module, a mobile communications module, and the like. The wired/wireless communications module included in the communications unit2010may be connected to an external communications network based on various communications standards so as to transmit and receive data.

The input unit2020may be provided to allow a user to control operations of the electronic device2000, and may include a mechanical switch, a touch screen, a voice recognition module, and the like. In addition, examples of the input unit2020may include a trackball mouse, a laser pointer mouse, or a finger mouse, and may further include various sensor modules allowing the user to input data.

Information processed by the electronic device2000may be output in a form of audio or video by the output unit2030, and the memory2040may store a program for processing and controlling operations of the processor2050, or may store data. The processor2050may store or retrieve data by transmitting command to the memory2040according to required operation.

The memory2040may be installed in the electronic device2000or communicate with the processor2050through a separate interface. When the memory2040communicates with the processor2050through a separate interface, the processor2050may store data in the memory2040or retrieve data therefrom through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB, and the like.

The processor2050may control operations of respective units included in the electronic device2000. The processor2050may perform controlling and processing related to audio calls, video calls, data communications, and the like, or controlling and processing for playing and managing a multimedia. In addition, the processor2050may process an input transmitted from the user through the input unit2020and output a corresponding result thereof through the output unit2030. The processor2050may store data required to control operations of the electronic device2000in the memory2040or retrieve the data from the memory2040. At least one of the processor2050and the memory2040may include a semiconductor device according to the various example embodiments of the present inventive concepts.

FIG. 23is a view schematically illustrating a system including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG. 23, a system3000may include a controller3100, an input/output device3200, a memory3300, and an interface3400. The system3000may be provided as a mobile system or a system transmitting or receiving information. The mobile system may be provided, for example, as a portable digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

The controller3100may execute a program and control the system3000. The controller3100may be provided as, for example, a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto.

The input/output device3200may be used in inputting or outputting data of the system3000. The system3000may be connected to an external device such as a personal computer or a network using the input/output device3200, and exchange data with the connected external device. The input/output device3200may be provided as, for example, a keypad, a keyboard, or a display.

The memory3300may store a code for an operation of the controller3100and/or data, and/or store data processed by the controller3100.

The interface3400may serve as a passage for data transmission between the system3000and an external device. The controller3100, the input/output device3200, the memory3300, and/or the interface3400may communicate with each other through a bus3500.

At least one of the controller3100and the memory3300may include a semiconductor device according to the various example embodiments of the present inventive concepts.

As set forth above, according to example embodiments of the present inventive concepts, semiconductor devices may have an improved mobility characteristic due to the formation of a capping layer able to prevent oxidation of a channel layer including germanium.