Dynamic Controller Buffer Management and Configuration

A method and apparatus for dynamic controller buffer management is disclosed. According to certain embodiments, responsive to commands received from a host, a controller may adjust one or more partitions of a controller buffer memory to adjust the size of different types of buffer memory. In some embodiments, preset buffer memory configurations may be applied to the buffer memory to adjust buffer memory allocation based on the current workload. By way of example, when sequential reads are detected, a TRAM buffer size may be increased to provide additional RLA buffers, at the expense of XRAM and/or L2P buffer size. Where operations involving SLC memory is detected, allocation of buffer memory parity buffers of XRAM may be decreased, to provide additional buffer space to L2P.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to a controller for a data storage device, and more particularly to managing buffer memory in the controller.

Background of the Invention

One aspect of optimizing performance of a data storage device (DSD) is providing fast buffer memory in a controller of the storage device. According to certain embodiments, this buffer memory may be an SRAM, or in some cases, a DRAM, and other memory types are useful for this purpose. Conventionally, this buffer memory may include a number of static partitions that are used during operations. A transactional random access memory (TRAM) partitions contains buffers that are used for host write operations and relocations, as well as read-look ahead (RLA) buffers that are used for optimization of sequential read operations. A buffer for holding parity accumulated from different pages for each open block on the DSD is referred to herein as XRAM. Parity in this context is used to recover data in the event of read errors and defects in one or more storage cells of a non-volatile (NVM) memory device of the DSD, such as a NAND. A logical to physical (L2P) cache is a third type of buffer of the buffer memory that stores portions of a L2P table, for use in DSD operations.

Conventionally, controller buffer partitions are kept at static sizes.

Accordingly, what is needed are systems and methods to improve usage of the controller memory buffer.

SUMMARY OF THE DISCLOSURE

The present disclosure generally relates to a method and apparatus for dynamic controller buffer management. According to certain embodiments, responsive to commands received from a host, a controller may adjust one or more partitions of a controller buffer memory to adjust the size of different types of buffer memory. In some embodiments, preset buffer memory configurations are applied to the buffer memory to adjust buffer memory allocation based on the current workload. By way of example, when sequential reads are detected, a TRAM buffer size may be increased to provide additional RLA buffers, at the expense of XRAM and/or L2P buffer size. Where operations involving SLC memory is detected, allocation of buffer memory parity buffers of XRAM may be decreased, to provide additional buffer space to L2P.

In one embodiment, a data storage device is disclosed that includes a non-volatile memory (NVM) device, and a controller coupled to the NVM device. The controller includes a buffer memory device comprising a first buffer partition consisting of one of a transactional RAM (TRAM) buffer, a logical to physical (L2P) buffer, or a parity RAM (XRAM) buffer, the first buffer partition being of a first buffer size, and a second buffer partition consisting of one of a transactional RAM (TRAM) buffer, a logical to physical (L2P) buffer, or a parity RAM (XRAM) buffer that is different from the first buffer partition, the of a second buffer partition being of a second buffer size, and a processor coupled to the buffer memory device. The processor is configured to identify a workload characteristic of a workload of the data storage device, modify the first buffer size based on the workload characteristic, and modify the second buffer size based on the modification of the first buffer size.

In another embodiment, a controller for a data storage device is disclosed that includes a buffer memory device consisting of a first buffer partition comprising one of a transactional RAM (TRAM) buffer, a logical to physical (L2P) buffer, or a parity RAM (XRAM) buffer, the first buffer partition being of a first buffer size, and a second buffer partition consisting of one of a transactional RAM (TRAM) buffer, a logical to physical (L2P) buffer, or a parity RAM (XRAM) buffer that is different from the first buffer partition, the of a second buffer partition being of a second buffer size, the first buffer size and second buffer size allocated based on a first workload, and a buffer management module (BMG) coupled to the buffer memory, configured to adjust the first buffer size and second buffer size based on a workload of the data storage device.

In another embodiment, a data storage device is disclosed that includes one or more non-volatile memory (NVM) means, and a controller means comprising computer-readable instructions. The computer-readable instructions cause the controller means to identify a workload characteristic of a workload of the data storage device, and remove a first data type from a first buffer partition of a buffer memory means based on the workload characteristic. The computer-readable instructions further cause the controller means to modify the first buffer size, and modify a second buffer size of a second buffer partition of the buffer memory means, based on the modification of the first buffer size.

DETAILED DESCRIPTION

The present disclosure generally relates to methods and systems for dynamic controller buffer management. According to certain embodiments, responsive to commands received from a host, a controller may adjust one or more partitions of a controller buffer memory to adjust the size of different types of buffer memory. In some embodiments, preset buffer memory configurations may be applied to the buffer memory to adjust buffer memory allocation based on the current workload. By way of example, when sequential reads are detected, a TRAM buffer size may be increased to provide additional RLA buffers, at the expense of XRAM and/or L2P buffer size. Where operations involving SLC memory is detected, allocation of buffer memory parity buffers of XRAM may be decreased, to provide additional buffer space to L2P.

Example System

FIG.1is a schematic block diagram illustrating a storage system100in which a host device104is in communication with a data storage device (DSD)106, according to certain embodiments. For instance, the host device104may utilize a non-volatile memory (NVM)110included in DSD106to store and retrieve data. The host device104comprises a host DRAM138. In some examples, the storage system100may include a plurality of storage devices, such as the DSD106, which may operate as a storage array. For instance, the storage system100may include a plurality of DSD106configured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for the host device104.

The DSD106includes a controller108, NVM110, a power supply111, volatile memory112, the interface114, and a write buffer116. In some examples, the DSD106may include additional components not shown inFIG.1for the sake of clarity. For example, the DSD106may include a printed circuit board (PCB) to which components of the DSD106are mechanically attached and which includes electrically conductive traces that electrically interconnect components of the DSD106or the like. In some examples, the physical dimensions and connector configurations of the DSD106may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5″ data storage device (e.g., an HDD or SSD), 2.5″ data storage device, 1.8″ data storage device, peripheral component interconnect (PCI), PCI-extended (PCI-X), PCI Express (PCIe) (e.g., PCIe ×1, ×4, ×8, ×16, PCIe Mini Card, MiniPCI, etc.). In some examples, the DSD106may be directly coupled (e.g., directly soldered or plugged into a connector) to a motherboard of the host device104, or may be located remotely from the host device104and accessed via a network or bus (e.g., PCIe) via interface114.

Interface114may include one or both of a data bus for exchanging data with the host device104and a control bus for exchanging commands with the host device104. Interface114may operate in accordance with any suitable protocol. For example, the interface114may operate in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. Interface114(e.g., the data bus, the control bus, or both) is electrically connected to the controller108, providing an electrical connection between the host device104and the controller108, allowing data to be exchanged between the host device104and the controller108. In some examples, the electrical connection of interface114may also permit the DSD106to receive power from the host device104. For example, as illustrated inFIG.1, the power supply111may receive power from the host device104via interface114.

The NVM110may include a plurality of memory devices or memory units. NVM110may be configured to store and/or retrieve data. For instance, a memory unit of NVM110may receive data and a message from controller108that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controller108that instructs the memory unit to retrieve data. In some examples, each of the memory units may be referred to as a die. In some examples, the NVM110may include a plurality of dies (i.e., a plurality of memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

In some examples, each memory unit may include any type of non-volatile memory devices, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory devices.

The NVM110may comprise a plurality of flash memory devices or memory units. NVM Flash memory devices may include NAND or NOR-based flash memory devices and may store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks, which may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller108may write data to and from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level.

The power supply111may provide power to one or more components of the DSD106. When operating in a standard mode, the power supply111may provide power to one or more components using power provided by an external device, such as the host device104. For instance, the power supply111may provide power to the one or more components using power received from the host device104via interface114. In some examples, the power supply111may include one or more power storage components configured to provide power to the one or more components when operating in an idle or shutdown mode, such as where power ceases to be received from the external device, or is received at a lower rate. In this way, the power supply111may function as an onboard backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, super-capacitors, batteries, and the like. In some examples, the amount of power that may be stored by the one or more power storage components may be a function of the cost and/or the size (e.g., area/volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and/or the size of the one or more power storage components also increases.

The volatile memory112may be used by controller108to store information such as command queues, error correction code (ECC) data, and other data that may be utilized by the controller108during operation of the DSD106. Volatile memory112may include one or more volatile memory devices. In some examples, controller108may use volatile memory112as a cache. For instance, controller108may store cached information in volatile memory112until the cached information is written to the NVM110. As illustrated inFIG.1, volatile memory112may consume power received from the power supply111. Examples of volatile memory112include, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)).

Controller108may manage one or more operations of the DSD106. For instance, controller108may manage the reading of data from and/or the writing of data to the NVM110. In some embodiments, when the DSD106receives a write command from the host device104, the controller108may initiate a data storage command to store data to the NVM110and monitor the progress of the data storage command. Controller108may determine at least one operational characteristic of the storage system100and store at least one operational characteristic in the NVM110. In some embodiments, when the DSD106receives a write command from the host device104, the controller108temporarily stores the data associated with the write command in the internal memory or write buffer116before sending the data to the NVM110. Controller108includes a buffer memory150that includes a transactional RAM buffer (TRAM)154, a parity RAM buffer (XRAM)158, and a logical to physical cache (L2P)162. TRAM154are holding buffers used for host write operations and relocation operations. According to certain embodiments, buffer memory150, and accordingly its components, may be implemented with a RAM, SRAM, DRAM, SDRAM or other physical memory architecture. Although shown as three components, according to certain embodiments buffer memory150is a contiguous physical memory space that may be allocated, or adjusted, as described herein. According to certain embodiments, buffer memory150may include more than three buffers, and up to any number of buffers, as indicated by nRAM164. By way of example and not limitation, additional buffers may include one or more management tables such as a grown bad block list, management tables associated with a host memory buffer (HMB) such as host DRAM138, management tables for circuit bonded array (CBA) operations, as well as additional TRAM, XRAM, and/or L2P buffers.

According to certain embodiments, TRAM154is managed in buffers sized in 4 KB increments; other embodiments may use different sizes. When host device104seeks to write data from host DRAM138the data may first be written to TRAM154before being written to the NVM110. Regarding relocation, when data is to be relocated, such as for garbage collection operations, data is copied from a block of the NVM110to TRAM154, and then to another block in the NVM110. TRAM154may further be utilized for read-look-ahead (RLA) operations. When the controller detects that the current workload from the host device104is in a sequential read mode, TRAM154may serve as a read look ahead buffer for reading sequential blocks from the NVM in order to improve RLA operations. According to certain embodiments, a controller may detect that the current workload is a sequential read by analyzing a threshold number of received commands that are determined to be reads on the NVM110from sequential locations, e,g., sequential logic addresses (LBAs).

XRAM158is configured to hold parity data accumulated for different pages of each open block of the NVM110. The parity data is used to recover data, for example, that has been modified as a result of a NAND defect in the NVM110. XRAM158is typically limited in size, and it is common that parity data may be swapped into/out of the NVM110by firmware.

L2P162is a buffer space for storing parts of a logical to physical table, mapping logical location references to physical locations on the NVM110.

As described herein, the relative sizes of the TRAM154, XRAM158, and L2P162, and in some embodiments, additional buffers such as up to nRAM164, may be changed depending on the workload of the DSD106as detected by the controller108. Buffer management module (BMG)166of the controller108detects the workload and state of the DSD106. Based on the detected workload and/or state of the DSD106, the BMG166maps one of a plurality of buffer memory profiles170to the buffer memory150, modifying the relative sizes of the TRAM154, XRAM158, and L2P162buffers, and in some embodiments, additional buffers through nRAM164. This provides additional buffer space to the appropriate buffer (e.g., TRAM154, XRAM158, L2P162, nRAM164) to increase operational efficiency of the DSD106for the then-current workload. Each buffer memory profile170in this context contains a different size allocation for the TRAM154, XRAM158, and L2P162, and in some embodiment additional buffers through nRAM164, that may be assigned to the buffer memory150based on a detected workload of the DSD106.

Example Process

FIG.2depicts an example process200for dynamic controller buffer management and configuration, according to certain embodiments. At block204, the BMG166identifies the current workload of the DSD106. According to certain embodiments, the workload is identified based on a workload characteristic of the workload, such as a command, or sequence of commands, received from the host device104. Based on the identified workload, at block208the BMG166determines an allocation of the buffer memory150for each of the TRAM154, XRAM158, and L2P162, and in some embodiment one or more additional buffers such as nRAM164, to best accommodate the detected workload. According to certain embodiments, determining the allocation may be done via a lookup table, indexed by workloads, with a buffer memory profile170correlating to each indexed workload. By way of example, where commands from the host104are directed to sequential read operations where logical block addresses are continuous, a profile may be chosen to accelerate RLA. According to certain embodiments, the BMG166may modify the buffer memory based on a state of the controller108, such as, for example, if the controller108applies garbage collection to one or more of the non-volatile memory devices110, or where host data operations are directed to SLC memory (rather than TLC memory) of the non-volatile memory devices110.

Based on the identified workload, the BMG166configures the buffer memory profile170to the buffer memory150, adjusting the relative sizes of two or more of the TRAM154, XRAM158, and L2P162, and in some embodiments one or more additional buffers such as nRAM164. At block212, based on the chosen buffer memory profile170the effective size of a first buffer of the buffer memory150is reduced. The reduced buffer may be any one of the TRAM154, XRAM158, or L2P162, or in some embodiments one or more additional buffers such as nRAM164.FIGS.3A,3B, and3Cdepict remapping of buffer memory150. Each of the first buffer304, third buffer308, and second buffer312represent one of the TRAM154, XRAM158, and L2P162, as each may be adjusted accordingly based on the desired buffer memory profile170, which as discussed above, is selected based on the workload of the DSD106. Although only one buffer is mentioned as being reduced, two buffers may be reduced so as to enable increase in buffer size at block216. At block216, the size of a second buffer is increase, at least in part at the expense of the first buffer reduced at block212. The second buffer that is increased is at least one of the buffers that was not reduced at block212. Although it is mentioned that one buffer increases, it is understood that in embodiments where one buffer is reduced (e.g., first buffer), the remaining buffers may both be increased, depending on the buffer memory profile170selected by the BMG.

FIGS.3A,3B, and3Cdepict examples of changing buffer sizes, according to certain embodiments. InFIG.3A, a first buffer304is shown to be reduced in size to a first buffer316while a second buffer312increases in size to second buffer320, and third buffer308remains the same. InFIG.3B, first buffer304reduces in size to first buffer316, second buffer312increases in size to second buffer320, and third buffer308reduces in size to third buffer324.FIG.3Cdepicts buffer304reducing in size to first buffer316, second buffer312increases in size to second buffer320, and third buffer308also increases in size to third buffer328. Each buffer, and concomitant increased/reduced size buffer, are one of the TRAM154, XRAM158, and L2P162, depending on the buffer memory profile selected by the BMG166; the depicted left-to-right ordering is arbitrary, intended only to show relative sizes, and changes in relative size that is dependent on the buffer memory profile170selected.

FIG.4depicts a process diagram400showing an example implementation of dynamic controller buffer management and configuration, according to certain embodiments. At block404, the BMG166identifies that the DSD106is in, or will be in, an SLC operation mode. At block408, the BMG166selects a buffer memory profile170for the SLC operation mode.

At block412, the BMG166modifies the buffer memory150allocation among the TRAM154, XRAM158, and L2P162in accordance with the selected buffer memory profile170. The selected buffer memory profile170causes the evacuation of TLC parity buffers from the XRAM buffer158to the NVM110, or host DRAM138. This reduces the effective XRAM158size. At block416, the BMG166causes the additional memory freed up in block412to be allocated to improve SLC write performance, increasing the effective size of the L2P162.

FIG.5depicts a process diagram500showing an example implementation of dynamic controller buffer management and configuration, according to certain embodiments. At block504, the BMG166identifies that the DSD106is in, or will be in, a read-look-ahead (RLA) mode. At block508, the BMG166selects a buffer memory profile170for the RLA mode.

At block512, the BMG166modifies the buffer memory150allocation among the TRAM154, XRAM158, and L2P162in accordance with the selected buffer memory profile170. The selected buffer memory profile170causes reduction of L2P162buffers of the buffer memory150, effectively decreasing the effective size of the L2P162.

At block516, the selected memory profile170causes the additional memory freed up in block512to be allocated to improve RLA performance, increasing the effective size of the TRAM154.

FIG.6depicts a process diagram600showing an example implementation of dynamic controller buffer management and configuration, according to certain embodiments. At block604, the BMG166identifies that the DSD106is in, or will be in, a sequential read operation without ongoing garbage collection (GC), in a drive state that allows RLA mode. At block608, the BMG166selects a buffer memory profile170for the RLA mode without ongoing GC.

At block612, the BMG166modifies the buffer memory150buffer allocation among the TRAM154, XRAM158, and L2P162in accordance with the selected buffer memory profile170. The selected buffer memory profile170causes reduction of TRAM154size for writes and/or GC, allocating more TRAM154size for RLA. At block616, selected buffer memory profile170causes reduction in the XRAM158buffer used for TLC parity, causing these buffers to be allocated for RLA, increasing the effective TRAM154size.

FIG.7depicts a process diagram700showing an example implementation of dynamic controller buffer management and configuration, according to certain embodiments. At block704, the BMG166identifies that the DSD106is in, or will be in, a background operations (BKOPS) mode, such as host-writes or NVM data relocation. At block708, the BMG166selects a buffer memory profile170for the BKOPS mode.

At block712, the BMG166causes the buffer memory150to modify buffer allocation among the TRAM154, XRAM158, and L2P162according to the selected buffer memory profile170. The selected buffer memory profile170causes allocation of more buffer space of buffer memory150for parities, increasing the effective XRAM158size. At block716, the selected buffer memory profile170further causes reduction of TRAM154space used for host-write operations and relocations, decreasing the effective TRAM154size.

FIG.8depicts a method800for dynamic controller buffer management and configuration, according to certain embodiments. At block804, the BMG166identifies a workload characteristic of a workload of the DSD106. According to certain embodiments, the workload characteristic is mapped to a buffer memory profile. According to certain embodiments, the buffer memory profile defines the first buffer size, the second buffer size, and the third buffer size. According to certain embodiments, the first buffer size, second buffer size, and third buffer size is based on the buffer memory profile.

At block808, the first buffer size is modified based on the workload characteristic. According to certain embodiments, the processor is further configured to identify a second workload characteristic and map the second workload characteristic to a second buffer memory profile, and adjusting the first buffer size, second buffer size, and third buffer size is based on the second buffer memory profile.

At block812, the second buffer size is modified based on the first buffer size.

By providing the DSD106with the BMG166and buffer memory150as disclosed herein, operations of the DSD106are dynamically provided with additional buffer memory150to improve speed and efficiency of operations.

According to certain embodiments, a data storage device is disclosed comprising a non-volatile memory (NVM) device, and a controller coupled to the NVM device. The controller comprises a buffer memory device comprising a first buffer partition comprising one of a transactional RAM (TRAM) buffer, a logical to physical (L2P) buffer, or a parity RAM (XRAM) buffer, the first buffer partition being of a first buffer size, and a second buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer that is different from the first buffer partition, the of a second buffer partition being of a second buffer size, and a processor coupled to the buffer memory device. The processor is configured to identify a workload characteristic of a workload of the data storage device, modify the first buffer size based on the workload characteristic, and modify the second buffer size based on the modification of the first buffer size. The data storage device, wherein the buffer memory further comprises a third buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer, that is different than the first buffer partition and second buffer partition, the third buffer partition being of a third buffer size, and wherein the processor is further configured to modify the third buffer size based on the workload characteristic and the modification of the first buffer size and the second buffer size. The data storage device wherein the workload characteristic is mapped to a buffer memory profile. The data storage device, wherein the buffer memory profile defines the first buffer size, the second buffer size and the third buffer size. The data storage device wherein modifying the first buffer size, the second buffer size, and the third buffer size is based on the buffer memory profile. The data storage device, wherein the processor is further configured to identify a second workload characteristic and map the second workload characteristic to a second buffer memory profile. The data storage device, further comprising adjusting two of the first buffer size, the second buffer size, and the third buffer size based on the second buffer memory profile.

According to certain embodiments, a controller for a data storage device is disclosed, comprising a buffer memory device comprising a first buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer, the first buffer partition being of a first buffer size, and a second buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer that is different from the first buffer partition, the of a second buffer partition being of a second buffer size, the first buffer size and second buffer size allocated based on a first workload, and a buffer management module (BMG) coupled to the buffer memory, configured to adjust the first buffer size and second buffer size based on a second workload of the data storage device. The controller, wherein the BMG being configured to adjust comprises identifying a workload characteristic of the second workload, modifying the first buffer size, and modifying the second buffer size based on the modification of the first buffer size. The controller, wherein the identified workload characteristic of the second workload is mapped to a buffer memory profile. The controller, wherein the buffer memory profile defines the first buffer size and the second buffer size. The controller, wherein the first buffer size and second buffer size is modified based on the buffer memory profile. The controller, wherein the BMG adjusts the first buffer size and second buffer size based on a third workload that is mapped to a second buffer memory profile. The controller, wherein the buffer memory further comprises a third buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer, that is different than the first buffer partition and second buffer partition, the third buffer partition being of a third buffer size, and wherein the BMG adjusts the third buffer size based on the second workload. The controller, wherein the first buffer partition comprises a TRAM buffer, the second buffer partition comprises an XRAM buffer, and the third buffer partition comprises an L2P buffer.

According to certain embodiments, a data storage device is disclosed, comprising one or more non-volatile memory (NVM) means, and a controller comprising computer-readable instructions. The computer-readable instructions cause the controller to identify a workload characteristic of a workload of the data storage device, remove a first data type from a first buffer partition of a buffer memory means based on the workload characteristic, modify a first buffer size, and modify a second buffer size of a second buffer partition of the buffer memory means, based on the modification of the first buffer size. The data storage device, wherein the workload characteristic is mapped to a buffer memory profile. The data storage device, wherein the buffer memory profile defines the first buffer size and the second buffer size. The data storage device, wherein modifying the first buffer size and second buffer size is based on the buffer memory profile. The data storage device, wherein the computer-readable instructions further cause the controller to identify a second workload characteristic of a second workload, mapping the second workload characteristic to a second buffer memory profile, and modifying the first buffer size and second buffer size based on the second buffer memory profile.