Semiconductor devices and methods of manufacturing the same

A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of priority to Korean Patent Application No. 10-2020-0045923 filed on Apr. 16, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to semiconductor devices. As the demand for high performance, high speed, and multi-functionality in semiconductor devices has increased, the degree of integration of semiconductor devices has increased. With the trend for high-density semiconductor devices, transistors in semiconductor devices are increasingly scaled down and there is ongoing research into methods of forming transistors having reduced sizes. In order to address limitations of operating characteristics caused by a decrease in sizes of planar metal oxide semiconductor FETs (MOSFETs), various efforts have been made to develop semiconductor devices including FinFETs with a channel having a 3-dimensional structure.

SUMMARY

Example embodiments provide a semiconductor device having improved electrical characteristics and a method of manufacturing the same.

According to an example embodiment, a semiconductor device includes a substrate having first to third regions, a first transistor on the first region and including a first gate dielectric layer, a first gate electrode layer on the first gate dielectric layer, and first source/drain regions on the substrate on opposite sides, adjacent to the first gate electrode layer, a second transistor on the second region and including a second gate dielectric layer, a second gate electrode layer on the second gate dielectric layer, and second source/drain regions on the substrate on opposite sides, adjacent to the second gate electrode layer, and a third transistor on the third regions and including a third gate dielectric layer, a third gate electrode layer on the third gate dielectric layer, and third source/drain regions on the substrate on opposite sides, adjacent to the third gate electrode layer. Each of the first and second gate electrode layers includes a first conductive layer, a first upper conductive layer on the first conductive layer, and a first internal conductive layer on the first upper conductive layer. The third gate electrode layer includes a second conductive layer, a second upper conductive layer on the second conductive layer, and a second internal conductive layer on the second upper conductive layer. The first and second conductive layers each include first and second layers, the first conductive layer further includes third and fourth layers, the first and second conductive layers include TiN, at least one of the first to fourth layers includes TiON, and the first to third transistors are MOSFETs having the same channel conductivity type.

According to an example embodiment, a semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region and including a first conductive layer, including a first plurality of layers, and the first gate electrode layer including a first upper conductive layer on the first conductive layer, and a second gate electrode layer on the second region and including a second conductive layer, including a second plurality of layers, and the second gate electrode layer including a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes TiON, a first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are MOSFETs having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

According to an example embodiment, a semiconductor device includes a substrate having first to third regions, a first gate structure on the first region and including a first gate dielectric layer, a first conductive layer on the first gate dielectric layer, and a first upper conductive layer on the first conductive layer, a second gate structure on the second region and including a second gate dielectric layer, a second conductive layer on the second gate dielectric layer, and a second upper conductive layer on the second conductive layer, and a third gate structure on the third region and including a third gate dielectric layer, a third conductive layer on the third gate dielectric layer, and a third upper conductive layer on the third conductive layer. Each of the first to third conductive layers includes one or a plurality of first layers including TiN, and the first and second conductive layers further include one or a plurality of second layers including TiON.

According to an example embodiment, a method of manufacturing a semiconductor device includes forming active fins, sacrificial gate structures, and source/drain regions in first to sixth regions of a substrate, removing the sacrificial gate structure to form openings, forming a gate dielectric layer in the openings, forming a first layer in the first to sixth regions, removing the first layer in the third to sixth regions, forming a second layer in the first to sixth regions, removing the second layer in the fourth to sixth regions, forming a third layer in the first to sixth regions, removing the third layer in the fifth and sixth regions, and forming a fourth layer in the first to sixth regions. Among the first to fourth layers, one or a plurality of layers is formed of TiON formed by oxidizing TiN, and others of the first to fourth layers are formed of TiN. A threshold voltage of a transistor, including the TiON, is smaller than a threshold voltage of a transistor, not including the TiON.

DETAILED DESCRIPTION

FIG.1is a plan view of a plurality of transistors of a semiconductor device according to example embodiments.FIG.2Aillustrates cross-sectional views of the semiconductor device inFIG.1, taken along lines I-I′, IV-IV′, V-V′, and VI-VI′, respectively.FIG.2Billustrates cross-sectional views of the semiconductor device inFIG.1, taken along lines A-A′, B-B′, C-C′, D-D′, E-E′, and F-F′, respectively.

Referring toFIGS.1to2B, a semiconductor device100may include a substrate101having first to sixth regions R1, R2, R3, R4, R5, and R6, and active fins105a,105b,105c,105d,105e, and105f, source/drain regions150a,150b,150c,150d,150e, and150f, interface layers112, gate dielectric layers114a,114b,114c,114d,114e, and114f, gate spacer layers116, and first to sixth gate electrode layers GE1, GE2, GE3, GE4, GE5, and GE6. The semiconductor device100may further include an isolation region107, a gate capping layer160, an interlayer insulating layer170, and a contact structure180. The gate dielectric layers114ato114f, the gate spacer layers116, the first to sixth gate electrode layers GE1to GE6, and the gate capping layer160may be collectively referred to as a gate structure.

The semiconductor device100may include FinFET elements, transistors in which active fins105ato105fhave a fin structure. The FinFET elements may include first to sixth transistors10,20,30,40,50, and60. For example, the first to third transistors10,20, and30may be p-type MOS field effect transistors (MOSFETs), and the fourth to sixth transistors40,50, and60may be n-type MOSFETs. The first to sixth transistors10,20,30,40,50, and60may be driven by different threshold voltages and may constitute the same circuit or different circuits in the semiconductor device100.

The first transistor10may include a first active fin105a, a first gate dielectric layer114a, first source/drain regions150a, and a first gate electrode layer GE1. The second transistor20may include a second active fin105b, a second gate dielectric layer114b, second source/drain regions150b, and a second gate electrode layer GE2. The third transistor30may include a third active fin105c, a third gate dielectric layer114c, third source/drain regions150c, and a third gate electrode layer GE3. The fourth transistor40may include a fourth active fin105d, a fourth gate dielectric layer114d, fourth source/drain regions150d, and a fourth gate electrode layer GE4. The fifth transistor50may include a fifth active fin105e, a fifth gate dielectric layer114e, fifth source/drain regions150e, and a fifth gate electrode layer GE5. The sixth transistor60may include a sixth active fin105f, a sixth gate dielectric layer114f, sixth source/drain regions150f, and a sixth gate electrode layer GE6.

The substrate101may have first to sixth regions R1to R6different from each other. The first to sixth regions R1-R6may be regions in which first to sixth transistors10,20,30,40,50, and60are disposed, respectively. The first to sixth regions R1to R6may be disposed to be spaced apart from each other or to be adjacent to each other in the semiconductor device100.

The substrate101may have an upper surface extending in an X direction and a Y direction. The substrate101may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate101may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like.

The isolation regions107may define the active fins105ato105fin the substrate101, as illustrated inFIG.2B. The isolation regions107may be formed by, for example, a shallow trench isolation (STI) process. According to example embodiments, the isolation regions107may include regions extending deeper downwardly of the substrate101between adjacent active fins105ato105f. The isolation regions107may include an insulating material. Each of the isolation regions107may include, for example, an oxide, a nitride, or a combination thereof.

The active fins105ato105fare defined by the isolation regions107in the substrate101and may be disposed to extend in one direction, for example, the X direction. The active fins105ato105fmay have a shape of a line or bar protruding from the substrate101between the isolation regions107. InFIG.1, the active fins105ato105fare illustrated as being disposed one by one in the first to sixth regions R1to R6, respectively. However, the arrangement and the number of the active fins105ato105fare not limited thereto. For example, two or three or more active fins105ato105fmay be disposed in each of the first to sixth regions R1to R6.

Among the active fins105ato105f, certain active fins may be recessed on opposite sides of the first to sixth gate electrode layers GE1to GE6. Source/drain regions150ato150fmay be disposed on the recessed active fins105ato105f. Accordingly, the active fins105ato105fmay have a relatively great height below the first to sixth gate electrode layers GE1to GE6. In example embodiments, the active fins105ato105fmay include impurities. For example, the first to third active fins105a,105b, and105cmay include n-type impurities, and the fourth to sixth active fins105d,105e, and105fmay include p-type impurities.

The interface layers112may be disposed between the active fins105ato105fand the gate dielectric layers114ato114E The interface layers112may include a dielectric material, for example, a silicon oxide, a silicon oxynitride, or combinations thereof.

The gate dielectric layers114ato114fmay be disposed between the active fins105ato105fand the first to sixth gate electrode layers GE1to GE6. The gate dielectric layers114ato114fmay be disposed on (e.g., to cover) lower surfaces and opposite side surfaces of the first to sixth gate electrode layers GE1to GE6.

The gate dielectric layers114ato114fmay include an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a higher dielectric constant than silicon oxide (Sift). The high-k dielectric materials include, for example, an aluminum oxide (Al2O3), a tantalum oxide (Ta2O3), a titanium oxide (TiO2), an yttrium oxide (Y2O3), a zirconium oxide (ZrO2), a zirconium silicon oxide (ZrSixOy), a hafnium oxide (LaHfxOy), a hafnium silicon oxide (HfSixOy), a lanthanum oxide (La2O3), a lanthanum aluminum oxide (LaAlxOy), a lanthanum hafnium oxide (LaHfxOy), a hafnium aluminum oxide (HfAlxOy), a praseodymium oxide (Pr2O3), or combinations thereof. The gate dielectric layers114ato114fmay include a common (i.e., the same) material, and the second, fourth, and sixth gate dielectric layers114b,114d, and114fmay further include an element serving to increase or decrease a threshold voltage of a transistor, more than the first, third, and fifth gate dielectric layers114a,114c, and114e. For example, the second, fourth, and sixth gate dielectric layers114b,114d, and114fmay further include a rare earth element, such as lanthanum (La), gadolinium (Gd), ruthenium (Ru), yttrium (Y), or scandium (Sc), that may be absent from (or present at a smaller concentration in) the first, third, and fifth gate dielectric layers114a,114c, and114e. Such elements may form, for example, an electric dipole to change a threshold voltage of a transistor.

The gate spacer layers116may be disposed on opposite side surfaces of the first to sixth gate electrode layers GE1to GE6. The gate spacer layers116may insulate the source/drain regions150ato150fand the first to sixth gate electrode layers GE1to GE6. According to example embodiments, the gate spacer layers116may have a multilayer structure. The gate spacer layers116may include an oxide, a nitride, or an oxynitride.

The first to sixth gate electrode layers GE1to GE6may be disposed to extend in one direction, for example, in the y direction while intersecting the active fins105ato105fabove the active fins105ato105f. Channel regions of the first to sixth transistors10,20,30,40,50, and60may be formed in the active fins105ato105fintersecting the first to sixth gate electrode layers GE1to GE6.

In the first to sixth regions R1to R6, the first to sixth gate electrode layers GE1to GE6may have substantially the same length or similar lengths in a channel direction, for example, the X direction. In the first to sixth regions R1to R6, the first to sixth gate electrode layers GE1to GE6may have substantially the same height or similar heights in a vertical direction, for example, a Z direction. The length and/or the height of the first to sixth gate electrode layers GE1to GE6are not limited to those illustrated in the drawings, and may vary according to example embodiments. For example, at least one of the first to sixth gate electrode layers GE1to GE6may have a relatively greater length in the X direction than the other gate electrode layers.

Each of the first gate electrode layer GE1and the second gate electrode layer GE2may include a first conductive layer120aincluding first to fourth layers121,122,123, and124, a first upper conductive layer130aon the first conductive layer120a, and a first internal conductive layer135aon the first upper conductive layer130a.

The third gate electrode layer GE3may include a second conductive layer120bincluding second to fourth layers122,123, and124, a second upper conductive layer130bon the second conductive layer120b, and a second internal conductive layer135bon the second upper conductive layer130b.

The fourth gate electrode layer GE4may include a third conductive layer120cincluding third and fourth layers123and124, a third upper conductive layer130con the third conductive layer120c, and a third internal conductive layer135con the third upper conductive layer130c.

Each of the fifth gate electrode layer GE5and the sixth gate electrode layer GE6may include a fourth layer124, a fourth upper conductive layer130don the fourth layer124, and a fourth internal conductive layer135don the fourth upper conductive layer130d.

A relative thickness of each of the layers, constituting the first to sixth gate electrode layers GE1to GE6, is not limited to that illustrated in the drawings, and may vary according to example embodiments. The number of the layers, constituting the first to sixth gate electrode layers GE1to GE6, is also not limited to that illustrated in the drawing, and may vary according to example embodiments. For example, the first gate electrode layer GE1may include a first conductive layer120aincluding a first plurality of layers, and the second gate electrode layer GE2may include a second conductive layer120bincluding a second plurality of layers. The first plurality of layers and the second plurality of layers may have either equal or different numbers of layers.

In each of the first and second gate electrode layers GE1and GE2, the first to fourth layers121,122,123, and124of the first conductive layer120ahave substantially the same thickness. In the first transistor10, the first to fourth layers121,122,123, and124may be conformally disposed on the first gate dielectric layer114aand may be sequentially stacked. In the second transistor20, the first to fourth layers121,122,123, and124may be conformally disposed on the second gate dielectric layer114band may be sequentially stacked. Each of the first to fourth layers121,122,123, and124may have a U shape or a U-like shape. The first to fourth layers121,122,123, and124may incompletely fill a space defined by the first and second gate dielectric layers114aand114band the gate capping layer160. Each of the first to fourth layers121,122,123, and124may have a thickness within a range of about 1 nanometer (nm) to about 2 nm. Boundaries between the first to fourth layers121,122,123, and124may be apparent or may not apparent.

Each of the first to fourth layers121,122,123, and124may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), tungsten (W), tungsten carbonitride (WCN), or combinations thereof. At least one of the first to fourth layers121,122,123, or124may include TiON.

As an example, the first layer121may include TiON, and each of the second to fourth layers122,123, and124may include TiN.

As another example, each of the first and second layers121and122may include TiON, and each of the third and fourth layers123and124may include TiN.

As another example, each of the first to third layers121,122, and123may include TiON, and the fourth layer124may include TiN.

As another example, the second layer122may include TiON, and each of the first, third and fourth layers121,123,124may include TiN.

A combination of a layer including TiON and a layer including TiN, among the first to fourth layers121,122,123, and124, may vary according to example embodiments. In the gate electrode layer, a threshold voltage of a transistor may be changed by a combination of materials forming the first to fourth layers121,122,123, and124.

In one embodiment in which the first conductive layer120aincludes TiN, at least one of the first to fourth layers121,122,123, and124may have a higher concentration of oxygen elements than other adjacent layers. Alternatively, at least one of the first to fourth layers121,122,123, or124may have a smaller concentration of oxygen than other adjacent layers. The first layer121may be disposed in a lowest portion of the first conductive layer120a.

In the third gate electrode layer GE3of the third transistor30, the second to fourth layers122,123, and124of the second conductive layer120bmay be conformally disposed on the third gate dielectric layer114cand may be sequentially stacked. The descriptions of the first conductive layer120aexcept the description of the first layer121, may be equally applied to the second to fourth layers122,123, and124of the second conductive layer120b.

In the fourth gate electrode layer GE4of the fourth transistor40, the third and fourth layers123and124of the third conductive layer120cmay be conformally disposed on the fourth gate dielectric layer114dand may be sequentially stacked. The descriptions of the first conductive layer120aexcept the descriptions of the first and second layers121and122, may be equally applied to the third and fourth layers123and124of the third conductive layer120c.

Each of the fifth and sixth gate electrode layers GE5and GE6of the fifth and sixth transistors50and60may include a fourth conductive layer. The fourth conductive layer may include a fourth layer124. The fourth layer124may be conformally disposed on the fifth gate dielectric layer114ein the fifth transistor50. The fourth layer124may be conformally disposed on the sixth gate dielectric layer114fin the sixth transistor60. The descriptions of the first conductive layer120aexcept the descriptions of the first to third layers121,122, and123, may be equally applied to the fourth layer124.

In an example embodiment, a thickness of the first conductive layer120amay be greater than a thickness of the second conductive layer120b. The thickness of the first conductive layer120amay be greater than a thickness of the third conductive layer120c. The thickness of the first conductive layer120amay be greater than a thickness of the fourth conductive layer including the fourth layer124. The thickness of the second conductive layer120bmay be greater than the thickness of the third conductive layer120c. The thickness of the second conductive layer120bmay be greater than the thickness of the fourth conductive layer including the fourth layer124. The thickness of the third conductive layer120cmay be greater than the thickness of the fourth conductive layer including the fourth layer124.

Each of the first and second gate electrode layers GE1and GE2of the first and second transistors10and20may include a first upper conductive layer130a. The first upper conductive layer130amay be conformally disposed on the first conductive layer120ain the first and second transistors10and20. The first upper conductive layer130ahas a U shape or a U-like shape, and may incompletely fill a space defined by the first conductive layer120aand the gate capping layer160. The first upper conductive layer130amay have a first width W1in the X direction. The first width W1may refer to a distance between external (i.e., exterior) sidewall surfaces of the first upper conductive layer130ain the X direction. The first upper conductive layer130amay be formed to have a first thickness T1, a substantially constant thickness. In an example embodiment, the first thickness T1may range from about 4 nm to about 6 nm. The first thickness T1may be described as a “width.”

The first upper conductive layer130amay include an alloy including aluminum (Al), a conductive metal carbide including Al, a conductive metal nitride including Al, or combinations thereof and may include titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or combinations thereof. The first upper conductive layer130amay have a work function smaller than a work function of the first conductive layer120a, but the present disclosure is not limited thereto.

The first internal conductive layer135amay be disposed in each of the first and second gate electrode layers GE1and GE2of the first and second transistors10and20. The first internal conductive layer135amay have a non-U shape, such as a pillar (e.g., rectangular) shape or a pillar-like shape, and may fill a space defined by the first upper conductive layer130aand the gate capping layer160. The first internal conductive layer135amay have a second thickness T2between internal (i.e., interior) sidewall surfaces of the first upper metal layer130ain the X direction. The second thickness T2may be described as “width.” The second thickness T2may be substantially the same as or greater than the first thickness T1. However, relative sizes of the second thickness T2and the first thickness T1may vary according to a line width of the gate structure and/or a thickness of each of the layers constituting the gate structure.

The first internal conductive layer135amay include a material different from a material of the first upper conductive layer130a. The first internal conductive layer135amay include, for example, TiN, TaN, W, WCN, or combinations thereof. However, the first internal conductive layer135ais not necessarily formed of a metal material and may be formed of a semiconductor material such as polysilicon according to example embodiments.

The second upper conductive layer130bmay be disposed in the third gate electrode layer GE3of the third transistor30. The second upper conductive layer130bmay be conformally disposed on the second conductive layer120bin the third transistor30. The above description of the first upper conductive layer130amay be equally applied to the second upper conductive layer130b. However, the second upper conductive layer130bmay have a second width W2greater than the first width W1of the first upper conductive layer130ain the X direction. The second upper conductive layer130bmay have substantially the same thickness as the first thickness T1of the first upper conductive layer130a.

The second internal conductive layer135bmay be disposed in the third gate electrode layer GE3of the third transistor30. The second internal conductive layer135bmay have a pillar shape or a pillar-like shape, and may fill a space defined by the second upper conductive layer130band the gate capping layer160. The above description of the first internal conductive layer135amay be equally applied to the second internal conductive layer135b. However, the second internal conductive layer135bmay have a third thickness T3greater than the second thickness T2of the first internal conductive layer135abetween the second upper metal layers130bin the X direction. The third thickness T3may be described as “width.”

The third upper conductive layer130cmay be disposed in the fourth gate electrode layer GE4of the fourth transistor40. The third upper conductive layer130cmay be conformally disposed on the third conductive layer120cin the fourth transistor40. The above description of the first upper conductive layer130amay be equally applied to the third upper conductive layer130c. However, the third upper conductive layer130cmay have a third width W3, greater than the first width W1, of the first upper conductive layer130ain the X direction. The third width W3may be greater than the second width W2.

The third internal conductive layer135cmay be disposed in the fourth gate electrode layer GE4of the fourth transistor40. The third internal conductive layer135cmay have a pillar shape or a pillar-like shape, and may fill a space defined by the third upper conductive layer130cand the gate capping layer160. The above description of the first internal conductive layer135amay be equally applied to the third internal conductive layer135c. However, the third internal conductive layer135chas a fourth thickness T4greater than the second thickness T2of the first internal conductive layer135abetween the third upper metal layers130cin the X direction. The fourth thickness T4may be greater than the third thickness T3. The fourth thickness T4may be described as “width.”

The fourth upper conductive layer130dmay be disposed in each of the fifth and sixth gate electrode layers GE5and GE6of the fifth and sixth transistors50and60. The fourth upper conductive layer130dmay be conformally disposed on the fourth layer124in the fifth and sixth transistors50and60. The above description of the first upper conductive layer130amay be equally applied to the fourth upper conductive layer130d. However, the fourth upper conductive layer130dmay have a fourth width W4larger than the first width W1of the first upper conductive layer130ain the X direction. The fourth width W4may be greater than the second width W2and the third width W3.

The fourth internal conductive layer135dmay be disposed in each of the fifth and sixth gate electrode layers GE5and GE6of the fifth and sixth transistors50and60. The fourth internal conductive layer135dmay have a pillar shape or a pillar-like shape, and may fill a space defined by the fourth upper conductive layer130dand the gate capping layer160. The above description of the first internal conductive layer135amay be equally applied to the fourth internal conductive layer135d. However, the fourth internal conductive layer135dmay have a fifth thickness T5greater than the second thickness T2of the first internal conductive layer130abetween the fourth upper metal layers130din the X direction. The fifth thickness T5may be greater than the third thickness T3and the fourth thickness T4. The fifth thickness T5may be described as “width.”

The first to third transistors10,20, and30may be MOSFETs having the same channel conductivity type but may have different threshold voltages. For example, the first to third transistors10,20, and30may be p-channel MOSFETs. The first transistor10may have a smaller threshold voltage than the second transistor20. Also, the second transistor20may have a smaller threshold voltage than the third transistor30.

The fourth to sixth transistors40,50, and60may be MOSFETs having the same channel conductivity type but may have different threshold voltages. For example, the fourth to sixth transistors40,50, and60may be n-channel MOSFETs. The fourth transistor40may have a higher threshold voltage than the fifth transistor50. Also, the fifth transistor50may have a higher threshold voltage than the sixth transistor60.

In the present disclosure, the magnitude of the threshold voltage may be compared as an absolute value. A difference between threshold voltages of the first and second transistors10and20may be caused by a difference between the first gate dielectric layer114aand the second gate dielectric layer114b. Since at least one of the first to fourth layers121,122,123, and124includes TiON, the first gate electrode GE1of each of the first and second transistors10and20may have a relatively smaller threshold voltage than when at least one of the first to fourth layers121,122,123, or124does not include TiON. When a layer including TiON is present in the gate electrode, a transistor having a threshold voltage, decreased by about 10 millivolts (mV) to about 60 mV as compared to the case in which the layer including TiON is not present in the gate electrode, may be provided.

According to an example embodiment, the first to third transistors10,20,30may be MOSFETs having the same conductivity type, for example, as p-channel MOSFETs, the first layer121of each of first and second transistors10and20may include TiON, the second to fourth layers122,123, and124of the first and second transistors10and20may include TiN, and the second to fourth layers122,123, and124of the third transistor30may include TiN. In this case, a threshold voltage of the first transistor10may be smaller than a threshold voltage of the second transistor20, and the threshold voltage of the second transistor20may be smaller than a threshold voltage of the third transistor30.

According to an example embodiment, the first to third transistors10,20, and30may be MOSFETs having the same conductivity type, for example, p-channel MSOFETs, the first and second layers121and122of the first and second transistors10and20and the second layer122of the third transistor30may include TiON, and the third and fourth layers123and124of the first to third transistors10,20, and30may include TiN. In this case, a threshold voltage of the first transistor10may be smaller than a threshold voltage of the second transistor20, and the threshold voltage of the second transistor20may be smaller than a threshold voltage of the third transistor30.

According to an example embodiment, the first to third transistors10,20, and30may be MOSFETs having the same conductivity type, for example, p-channel MSOFETs, the first to third layers121,122, and123of the first and second transistors10and20and the third layer123of the third transistor30include TiON, and the fourth layer124of the first to third transistors10,20, and30may include TiN. In this case, a threshold voltage of the first transistor10may be smaller than a threshold voltage of the second transistor20, and the threshold voltage of the second transistor20may be smaller than a threshold voltage of the third transistor30.

According to an example embodiment, each of the first to third conductive layers120a,120b, and120cmay include one or more layers including TiN. The first and second conductive layers120aand120bmay include one or more layers including TiON. A thickness of the first conductive layer120aand a thickness of the second conductive layer120bmay be less than a thickness of the third conductive layer120c. In the first conductive layer120a, a single layer or a plurality of layers including TiON may be disposed in a lowermost portion, but the present disclosure is not limited thereto.

In example embodiments, the semiconductor device100may not include at least one of the third to sixth transistors30,40,50, or60. For example, the semiconductor device100may include only the first and second transistors10and20, or may include only the first and third transistors10and30. As described above, types of transistors included in the semiconductor device100may be variously selected according to threshold voltage ranges required in the semiconductor device100.

The source/drain regions150ato150fmay be disposed on the active fins105ato105f, respectively, on opposite sides adjacent to the first to sixth gate electrode layers GE1to GE6. The source/drain regions150ato150fmay be provided as source regions or drain regions of the first to sixth transistors10,20,30,40,50, and60. According to example embodiments, the source/drain regions150ato150fmay be connected to or merged with two or more active fins105ato105fto form a single source/drain region150ato150f.

The source/drain regions150ato150fmay be a semiconductor layer including silicon (Si), and may include an epitaxial layer. The source/drain regions150ato150fmay include impurities. For example, the source/drain regions150ato150fmay include p-type doped silicon-germanium (SiGe). In example embodiments, the source/drain regions150ato150fmay include a plurality of regions including elements having different concentrations and/or doping elements.

The gate capping layer160may be disposed on the first to sixth gate electrode layers GE1TO GE6and the gate spacer layers116. The gate capping layer160may be disposed to recess certain upper portions of the first to sixth gate electrode layers GE1to GE6and the gate spacer layers116. A lower surface of the gate capping layer160may have a downwardly convex shape, so that upper surfaces of the first to sixth gate electrode layers GE1to GE6may also be curved. A maximum width of the gate capping layer160may be greater than a width of each of the first to sixth gate electrodes GE1to GE6in the X direction. In example embodiments, the gate capping layer160may be omitted, and the first to sixth gate electrode layers GE1to GE6may upwardly extend longer.

The interlayer insulating layer170may be disposed on (e.g., to cover) the isolation regions107, the source/drain regions150ato150f, and the gate capping layer160. The interlayer insulating layer170may include, for example, at least one of an oxide, a nitride, or an oxynitride, and may include a low-k dielectric material.

The contact structure180may extend through the interlayer insulating layer170to connect (e.g., electrically and/or physically connect) to the source/drain regions150ato150fand may apply an electrical signal to the source/drain regions150ato150f. The contact structure180may have an inclined side surface in which a width of a lower portion is reduced to be narrower than a width of the upper portion according to an aspect ratio, but the present disclosure is not limited thereto. The contact structure180may be disposed to be in contact with upper surfaces of the source/drain regions150ato150fwithout recessing the source/drain regions150ato150f.

The contact structure180may include a conductive layer, a metal-semiconductor compound layer between the conductive layer and the source/drain regions150ato150f, and a contact barrier metal layer surrounding the conductive layer. The conductive layer may include W, Co, Ti, alloys thereof, or combinations thereof. The metal-semiconductor compound layer may be a silicide layer, and may include, for example, CoSi, NiSi, or TiSi. The contact barrier metal layer may include TiN, TaN, WN, or combinations thereof.

FIGS.3A and3Bare cross-sectional views of a semiconductor device according to example embodiments.

Referring toFIGS.3A and3B, a semiconductor device200may include a substrate101having first to sixth regions R1, R2, R3, R4, R5, and R6, active fins105a,105b,105c,105d,105e, and105f, channel structures140ato140f, each including a plurality of channel layers141,142, and143, source/drain regions150a,150b,150c,150d,150e, and150f, interface layers112, gate dielectric layers114a,114b,114c,114d,114e, and114f, gate spacer layers116, and first to sixth gate electrode layers GE1, GE2, GE3, GE4, GE5, and GE6. The semiconductor device100may further include an isolation region107, internal spacer layers148, a gate capping layer160, an interlayer insulating layer170, and a contact structure180. Hereinafter, a description will be given of only a structure different from the semiconductor device100inFIGS.2A and2B.

In the semiconductor device200, the active fins105ato105fhave a fin structure, and the first to sixth gate electrode layers GE1to GE6may be disposed between the active fins105ato105fand channel structures140ato140f, between a plurality of channel layers141,142, and143of the channel structures140ato140f, and above the channel structures140ato140f. Therefore, the semiconductor device200may include a multi-bridge channel FET (MBCFET™) formed by the channel structures140ato140f, the source/drain regions150ato150f, and the first to sixth gate electrode layers GE1to GE6.

The MBCFET™ elements may include first to sixth transistors11,21,31,41,51, and61. For example, the first to third transistors11,21, and31may be p-type MOS field effect transistors (MOSFETs), and the fourth to sixth transistors41,51, and61may be n-type MOSFETs. The first to sixth transistors11to61may be driven by different threshold voltages, and may constitute the same circuit or different circuits in the semiconductor device200.

The channel structures140ato140fmay include first to third channel layers141,142, and143, a plurality of channel layers spaced apart from each other on the active fins105ato105fin a direction, perpendicular to upper surfaces of the active fins105ato105f, for example, a Z direction. The first to third channel layers141,142, and143may be spaced apart from the upper surfaces of the active fins105ato105fwhile being connected to the source/drain regions150ato150f. The first to third channel layers141,142, and143may be formed of a semiconductor material, and may include at least one of, for example, silicon (Si), silicon-germanium (SiGe), or germanium (Ge). The first to third channel layers141,142, and143may be formed of, for example, the same material as the substrate101. The number and shape of the channel layers141,142, and143, constituting one channel structure140ato140f, may vary according to example embodiments.

The internal spacer layers148may be disposed parallel to the first to sixth gate electrode layers GE1to GE6between the channel structures140ato140f. The internal spacer layers148may be disposed on, for example, opposite sides adjacent to the first to sixth gate electrode layers GE1to GE6in the X direction, above a lower surface of each of the first to third channel layers141,142, and143. The internal spacer layers148may have external sidewall surfaces, substantially coplanar with external sidewall surfaces of the first to third channel layers141,142, and143. The shape of the internal spacer layers148is not limited to that illustrated in the drawings, and a side surface facing the first to sixth gate electrode layers GE1to GE6may be convexly rounded inwardly of the first to sixth gate electrodes GE1to GE6. The internal spacer layers148may be formed of an oxide, a nitride, or an oxynitride and, in particular, may include a low-k dielectric material.

The interface layers112, the gate dielectric layers114ato114f, and the first to sixth gate electrode layers GE1to GE6may be disposed above the third channel layer143, and may be disposed between the active fins105ato105fand the first channel layer141, between the first channel layer141and the second channel layer142, and between the second channel layer142and the third channel layer143. The first to sixth gate electrode layers GE1to GE6may extend in one direction and be disposed to intersect the active fins105ato105f. The interface layers112may be disposed on (e.g., to cover) upper and lower surfaces of the channel layers141,142, and143between the source/drain regions150ato150f. Between the source/drain regions150ato150f, the gate dielectric layers114ato114fmay be disposed on (e.g., to cover) internal side surfaces of the internal spacer layers148and upper and lower surfaces of the interface layers112and to surround the first to fourth layers121,122,123, and124.

Between the first source/drain regions150aand between the second source/drain regions150b, the first to fourth layers121,122,123, and124may be disposed to surround the first upper conductive layer130aand the first upper conductive layer130amay be disposed to surround the first internal conductive layer135a. Between the third source/drain regions150c, the second to fourth layers122,123, and124may be disposed to surround the second upper conductive layer130band the second upper conductive layer130bmay be disposed to surround the second internal conductive layer135b. Between the fourth source/drain regions150d, the third and fourth layers123and124may be disposed to surround the third upper conductive layer130cand the third upper conductive layer130cmay be disposed to surround the third internal conductive layer135c. Between the fifth source/drain regions150eand between the sixth source/drain regions150f, the fourth layer124may be disposed to surround the fourth upper conductive layer130dand the fourth upper conductive layer130dmay be disposed to surround the fourth internal conductive layer135d.

FIG.4is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments.FIGS.5A to5Dare flowcharts illustrating a method of manufacturing a semiconductor device according to example embodiments.FIGS.6A to60are process flow diagrams illustrating a method of manufacturing a semiconductor device according to example embodiments.FIGS.6A to60illustrate an example embodiment of a method of manufacturing the semiconductor device inFIGS.2A and2B.FIGS.7A to7Fare partially enlarged cross-sectional views of portions of a semiconductor device, illustrating a method of manufacturing the semiconductor device according to example embodiments.

Referring toFIGS.4and6A, the substrate101having first to sixth regions R1to R6may be patterned to form active fins105ato105f, a sacrificial gate structure190, and the source/drain regions150ato150f(S10). In addition, in operation S10, gate spacer layers116and interlayer insulating layer170may be formed.

The first to third regions R1, R2, and R3may be PMOS transistor regions, and the fourth to sixth regions R4, R5, and R6may be NMOS transistor regions. The substrate101may include conductive regions, for example, well structures doped with impurities. The active fins105ato105fmay be defined by forming isolation regions107(seeFIG.2B), and may have a shape protruding from the substrate101. The active fins105ato105fmay include impurity regions.

The sacrificial gate structure190is disposed in a region, in which the interface layers112, gate dielectric layers114ato114f, and first to sixth gate electrode layers GE1to GE6are disposed as illustrated inFIG.2A, through a subsequent process. The sacrificial gate structure190may include a sacrificial gate insulating layer192, a sacrificial gate electrode layer195, and a sacrificial gate capping layer196. The sacrificial gate insulating layer192and the sacrificial gate capping layer196may be insulating layers and the sacrificial gate electrode layer195may be a conductive layer, but the present disclosure is not limited thereto. For example, the sacrificial gate insulating layer192may include a silicon oxide, the sacrificial gate electrode layer195may include polysilicon, and the sacrificial gate capping layer196may include at least one of a silicon oxide, a silicon nitride, or a silicon oxynitride.

The gate spacer layers116may be formed on both (e.g., opposite) sidewalls of the sacrificial gate structure190. The gate spacer layers116may be formed of an insulating material, and include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

The source/drain regions150ato150fmay be formed on the recessed active fins105ato105fafter removing a portion of the active fins105ato105fon opposite sides adjacent to the gate spacer layers116. The source/drain regions150ato150fmay be formed using, for example, a selective epitaxial growth (SEG) process. The source/drain regions150ato150fmay include a semiconductor material doped with impurities, for example, Si, SiGe, or SiC. In particular, the first to third source/drain regions150a,150b, and150cmay include p-type impurities, and the fourth to sixth source/drain regions150d,150e, and150fmay include n-type impurities. Impurities may be doped in-situ during the formation of source/drain regions150ato150f, or may be implanted separately after growth.

The interlayer insulating layer170may be formed by performing a planarization process to expose an upper surface of the sacrificial gate structure190after depositing an insulating material to cover the sacrificial gate structure190and the source/drain regions150ato150f. The interlayer insulating layer170may include, for example, at least one of an oxide, a nitride, or an oxynitride, and may include a low-k dielectric material.

Referring toFIGS.4and6B, the sacrificial gate structure190may be removed to form a first opening OP (S20).

The sacrificial gate structure190may be selectively removed with respect to the isolation region107and the active fins105ato105f, such that a first opening OP may be formed to expose the isolation region107, the active fins105ato105f, and the gate spacer layer116. The process of removing the sacrificial gate structure190may employ at least one of a dry etching process or a wet etching process.

Referring toFIGS.4and6C, the interface layer112and the gate dielectric layers114ato114fmay be formed in the first opening OP (S30). The first layer121may be formed in the first to sixth regions R1to R6(S40).

The interface layer112and the gate dielectric layers114ato114fmay be formed to have substantially the same thickness in the first to sixth regions R1to R6. The interface layer112may be formed on upper surfaces of the active fins105ato105fexposed to a lower surface/level of the first opening OP. According to example embodiments, the interface layer112may be formed by oxidizing a portion of each of the active fins105ato105f.

The gate dielectric layers114ato114fmay be formed substantially conformally along a sidewall and a bottom surface of the first opening OP. The process of forming the first, third, and fifth gate dielectric layers114a,114c, and114eand the process of forming the second, fourth, and sixth gate dielectric layers114b,114d, and114fmay be performed independently of each other. The gate dielectric layers114ato114fmay be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The second gate dielectric layer114bmay be formed to further include elements that are not included in the first gate dielectric layer114a. For example, the first and second gate dielectric layers114aand114bmay include a hafnium oxide (HfO2), and the second gate dielectric layer114bmay further include a lanthanum hafnium oxide (LaHfxOy).

The first layer121may be a layer constituting a portion of the first conductive layer120athrough a subsequent process. The first layer121may be conformally formed on the gate dielectric layers114ato114f. The first layer121may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first layer121may include TiN, TaN, TiON, TiSiN, W, WCN, or combinations thereof. The first layer121may be formed of the same material as the second to fourth layers122,123, and124that are formed in a subsequent process.

Referring toFIGS.4,5A,6D, and7A, a first oxidation treatment process1may be performed on the first to sixth regions R1to R6(S45).

The first oxidation treatment process1may be performed using a source gas containing O2, O3, or H2O. The first oxidation treatment process1may be an oxygen plasma treatment process. The first layer121may be oxidized by the first oxidation treatment process1. In one embodiment in which the first layer121includes TiN, oxygen may be diffused into the first layer121from a surface of the first layer121by the first oxidation treatment process1, as illustrated inFIG.7A, such that TiN of the first layer121may be oxidized to be turned into TiON. The first oxidation treatment process1may be omitted according to example embodiments.

Referring toFIGS.4and6E, the first layer121may be removed in the third to sixth regions R3, R4, R5, and R6(S50).

The first layer121may be removed only in the third to sixth regions R3, R4, R5, and R6after an additional mask layer is performed on the first and second regions R1and R2. Thus, the first layer121may remain in the first and second regions R1and R2.

Referring toFIGS.4and6F, the second layer122may be formed in the first to sixth regions R1to R6(S60).

The second layer122may be a layer constituting a portion of the first and second conductive layers120aand120bthrough a subsequent process. The second layer122may be conformally formed on the first layer121in the first and second regions R1and R2, and may be conformally formed on the third to sixth gate dielectric layers114c,114d,114e, and114fin the third to sixth regions R3, R4, R5, and R6.

Referring toFIGS.4,5B,6G, and7B, a second oxidation treatment process2may be performed on the first to sixth regions R1to R6(S65).

The second oxidation treatment process2may be performed using a source gas containing O2, O3, or H2O. The second oxidation treatment process2may be an oxygen plasma treatment process. The second layer122may be oxidized by the second oxidation treatment process2. In one embodiment in which the second layer122includes TiN, oxygen may be diffused into the second layer122from a surface of the second layer122by the second oxidation treatment process2, as illustrated inFIG.7B, such that TiN of the second layer122may be turned into TiON. The second oxidation treatment process2may be omitted according to example embodiments.

In an example embodiment, a depth at which oxygen is diffused in the first and second layers121and122by the second oxidation treatment process2may be changed. For example, as illustrated inFIG.7E, oxygen may be diffused from a surface of the second layer122by the second oxidation treatment process2to turn TiN of the first and second layers121and122into TiON. In this case, the first oxidation treatment process1may be omitted.

The first and second oxidation treatment processes1and2may be performed to turn TiN of each of the first and second layers121and122into TiON. However, a diffusion depth of oxygen may be adjusted during the second oxidation treatment process2without performing the first oxidation treatment process1to turn TiN of each of the first and second layers121and122into TiON.

Referring toFIGS.4and6H, the second layer122may be removed in the fourth to sixth regions R4, R5, and R6(S70).

The second layer122may be removed only in the fourth to sixth regions R4, R5, and R6after an additional mask layer is formed on the first to third regions R1, R2, and R3. Thus, the second layer122may remain in the first to third regions R1, R2, and R3.

Referring toFIGS.4and61, the third layer123may be formed in the first to sixth regions R1to R6(S80).

The third layer123may be a layer constituting a portion of the first to third conductive layers120a,120b, and120cthrough a subsequent process. The third layer123may be conformally formed on the second layer122in the first to third regions R1, R2and R3, and may be conformally formed on the fourth to sixth gate dielectric layers114d,114e, and114fin the fourth to sixth regions R4, R5and R6.

Referring toFIGS.4,5C,6J, and7C, a third oxidation treatment process3may be performed on the first to sixth regions R1to R6(S85).

The third oxidation treatment process3may be performed using a source gas containing O2, O3, or H2O. The third oxidation treatment process3may be an oxygen plasma treatment process. The third layer123may be oxidized by the third oxidation treatment process3. In one embodiment in which the third layer123includes TiN, oxygen is diffused into the third layer123from a surface of the third layer123by the third oxidation treatment process3, as illustrated inFIG.7C, such that TiN of the third layer123may be turned into TiON. The third oxidation treatment process3may be omitted according to example embodiments.

In an example embodiment, a depth at which oxygen is diffused in the first to third layers121,122, and123by the third oxidation treatment process3may be changed. For example, as illustrated inFIG.7F, oxygen may be diffused from a surface of the third layer123by the third oxidation treatment process3to turn TiN of the second and third layers122and123into TiON. In this case, the second oxidation treatment process2may be omitted.

The second and third oxidation treatment processes2and3may be performed to turn TiN of each of the second and third layers122and123into TiON. However, a diffusion depth of oxygen may be adjusted during the third oxidation treatment process3without performing the second oxidation treatment process2to turn TiN of each of the second and third layers122and123into TiON.

Referring toFIGS.4and6K, the third layer123may be removed in the fifth and sixth regions R5and R6(S90).

The third layer123is removed only in the fifth and sixth regions R5and R6after an additional mask layer is formed on the first to fourth regions R1, R2, R3, and R4. Thus, the third layer123may remain in the first to fourth regions R1, R2, R3, and R4.

Referring toFIGS.4and6L, the fourth layer124may be formed in the first to sixth regions R1to R6(S100).

The fourth layer124may be a layer constituting a portion of the first to third conductive layers120a,120b, and120cthrough a subsequent process. The fourth layer124may be conformally formed on the third layer123in the first to fourth regions R1, R2, R3, and R4, and may be conformally formed on the fifth and sixth gate dielectric layers114eand114fin the fifth and sixth regions R5and R6.

Referring toFIGS.4,5D,6M, and7D, a fourth oxidation treatment process4may be performed on the first to sixth regions R1to R6(S105).

The fourth oxidation treatment process4may be performed using a source gas containing O2, O3, or H2O. The fourth oxidation treatment process4may be an oxygen plasma treatment process. The fourth layer124may be oxidized by the fourth oxidation treatment process4. In one embodiment in which the fourth layer124includes TiN, oxygen may be diffused into the fourth layer124from a surface of the fourth layer124by the fourth oxidation treatment process4, as illustrated inFIG.7D, such that TiN of the fourth layer124may be turned into TiON. The fourth oxidation treatment process4may be omitted according to example embodiments.

Referring toFIGS.4,6N, and60, upper conductive layers130a,130b,130c, and130dand internal conductive layers135a,135b,135c, and135dmay be formed in the first to sixth regions R1to R6(S110). The gate capping layer160may be formed on the first to sixth gate electrode layers GE1to GE6(S120).

The upper conductive layers130a,130b,130c, and130dand the internal conductive layers135a,135b,135c, and135dmay be formed in the first opening OP in the first to sixth regions R1to R6.

After the upper conductive layers130a,130b,130c, and130dand the internal conductive layers135a,135b,135c, and135dare formed, a portion of the first to fourth layers121,122,123, and124, the upper conductive layers130a,130b,130c, and130d, and the internal conductive layers135a,135b,135c, and135dmay be removed on the interlayer insulating layer170. The removal process may employ a planarization process such as a chemical mechanical polishing (CMP) process.

An upper portion of the gate spacer layers116, first to fourth layers121,122,123, and124, upper conductive layers130a,130b,130c, and130d, and internal conductive layers135a,135b,135c, and135dmay be removed, and the gate capping layer160may be formed in the removed portion. Thus, the first to sixth gate electrode layers GE1to GE6may be finally formed in the first to sixth regions R1to R6, and the first to sixth transistors10,20,30,40,50, and60may be formed.

Referring again toFIG.2A, contact structures180may be formed to be connected to the source/drain regions150ato150fby extending through the interlayer insulating layer170. As a result, the semiconductor device100ofFIGS.1to2Bmay be manufactured.

FIGS.8A to8Dare process flow diagrams illustrating a method of manufacturing a semiconductor device according to example embodiments.FIGS.8A to8Dillustrate an example embodiment of a method of manufacturing the semiconductor device ofFIGS.3A and3B.

Referring toFIG.8A, sacrificial layers119and channel layers141,142, and143may be alternately stacked on a substrate101having first to sixth regions R1to R6. The substrate101, the sacrificial layers119, and the channel layers141,142, and143may be patterned to form active fins105ato105f. A sacrificial gate structure190and gate spacer layers116may be formed across the active fins105ato105f. Processes of forming the active fins105ato105f, isolation regions107, gate spacer layers116, and sacrificial gate structure190are the same as or similar to those described with reference toFIGS.4and6A, and thus, descriptions thereof will be omitted.

The sacrificial layers119may be replaced with first to sixth gate electrode layers GE1to GE6in a subsequent process, as illustrated inFIGS.3A and3B. The sacrificial layers119may be formed of a material having an etching selectivity with respect to the channel layers141,142, and143. The sacrificial layers119and the channel layers141,142, and143include, for example, a semiconductor material including at least one of silicon (Si), silicon-germanium (SiGe), or germanium (Ge) and may include different materials. In addition, the sacrificial layers119and the channel layers141,142, and143may or may not include impurities. For example, the sacrificial layers119may include silicon-germanium (SiGe), and the channel layers141,142, and143may include silicon (Si).

The sacrificial layers119and the channel layers141,142, and143may be formed by performing an epitaxial growth process using the substrate101as a seed. The number of the channel layers141,142, and143, alternately stacked with the sacrificial layers119, may vary according to example embodiments.

Referring toFIG.8B, exposed portions of the sacrificial layers119and the channel layers141,142, and143are removed on opposite sides adjacent to the sacrificial gate structure190to form a recessed region RC. Thus, the channel structures140ato140fmay be formed. A portion of the exposed sacrificial layers119may be removed from side surface thereof. Internal spacer layers148may be formed in a region in which a portion of the sacrificial layers119is removed.

Exposed portions of sacrificial layers119and channel layers141,142, and143may be removed using the sacrificial gate structure190and the gate spacer layers116as masks. Accordingly, the channel layers141,142, and143have a defined length in an X direction and constitute channel structures140ato140f.

The sacrificial layers119may be selectively etched with respect to the channel structures140ato140fby, for example, a wet etching process to be removed to a certain depth from side surfaces thereof in the X direction. Due to the etching of the side surfaces, the sacrificial layers119may have inwardly concave side surfaces.

The internal spacer layers148may be formed by filling an insulating material in a region, in which the sacrificial layers119are removed, and removing the insulating material deposited on external sides of the channel structures140ato140f.

Referring toFIG.8C, on opposite sides adjacent to the sacrificial gate structures190, source/drain regions150ato150fmay be formed on the active fins105ato105fand an interlayer insulating layer170is formed. Then, the sacrificial gate structures190may be removed to form a second opening OPa. Processes of forming the source/drain regions150ato150fand the interlayer insulating layer170are the same as or similar to those described with reference toFIGS.4and6A, and thus, descriptions thereof will be omitted. However, upper surfaces of the source/drain regions150ato150fmay be disposed to be higher than an upper surface of the third channel layer143.

The sacrificial gate structure190may be selectively removed with respect to the isolation region107, the active fins105ato105f, and the channel structures140ato140fdisposed therebelow. Thus, the isolation region107, the active fins105ato105f, the gate spacer layers116, and the internal spacer layers148may be exposed.

Referring toFIG.8D, a first layer121may be formed in the first to sixth regions R1to R6.

The first layer121may be conformally formed on the gate dielectric layers114ato114fin the first to sixth regions R1to R6. Unlike what is illustrated inFIG.6C, the first layer121may also be conformally formed on gate dielectric layers114ato114f, disposed between the channel structures140ato140fand the active fins105ato105f, between the source/drain regions150ato150f.

Next, the same processes as described with reference toFIGS.6D to7Fmay be performed in the same manner to manufacture the semiconductor device ofFIGS.3A and3B. For example, a first oxidation treatment process1may be performed on the first to sixth regions R1to R6to turn TiN of the first layer121into TiON and the first layer121may be removed in the third to sixth regions R3, R4, R5, and R6. Among the first to fourth oxidation treatment processes1,2,3, and4, certain processes may be omitted according to example embodiments.

As described above, gate electrode layers of transistors may have various structures to provide various threshold voltages. Accordingly, a semiconductor device having improved electrical characteristics and a method of manufacturing the same may be provided.