CMOS input circuit

A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from MOS transistors. Circuitry provides output currents of optimal waveforms from the digital-to-analog converters for driving stages subsequent to such converters. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz). The circuits facilitate the production of the signals at such high frequencies by employing the distributed capacitances in a first transistor to expedite the response of a second transistor to binary input signals introduced to the first transistor. A servo system is also provided for controlling the magnitude of a biasing voltage introduced to the second transistor and for maintaining substantially constant the currents flowing at all times through one or the other of the first and second transistors.

FIG. 1 illustrates circuitry for receiving binary input signals and for 
producing an output current representative of the binary input signals. 
The circuitry of FIG. 1 is particularly adapted to be used in a 
digital-to-analog converter. The circuitry shown in FIG. 1 includes an 
input line 100 for receiving the binary input signals. The input line 100 
is connected to the gate of a transistor 102 such as a MOS transistor of 
the p-type. The drain of the transistor 102 is connected through a line 
103 to a reference potential such as ground. The source of the transistor 
102 is common with the source of a transistor 104 and with the drain of a 
transistor 106. The transistors 104 and 106 may be MOS transistors of the 
p-type. 
The source of the transistor 106 receives an energizing potential such as 
approximately 5 volts. The gate of the transistor 106 receives a 
substantially constant bias voltage through a circuit which is shown in 
FIG. 3 and which will be described in detail subsequently. The gate of the 
transistor 104 receives a suitable biasing voltage such as a voltage of 
approximately 1.2 volts on a line 108. The output from the circuitry shown 
in FIG. 1 is produced on a line 110 which is connected to the drain of the 
transistor 104. 
Distributed capacitances 112 (shown in broken lines in FIG. 1) exist 
between the gate and the source of the transistor 102 and distributed 
capacitances 114 (shown in broken lines in FIG. 1) exist between the gate 
and the drain of the transistor. These distributed capacitances are 
charged during the time that the transistor 102 is nonconductive and they 
become discharged when the transistor 102 becomes conductive. 
In output circuitry of the prior art, the discharge of a distributed 
capacitance corresponding to the capacitance 112 occurs through a circuit 
including the source and gate of a transistor and the discharge of a 
distributed capacitor corresponding to the capacitance 114 occurs through 
a circuit including the gate and drain of the transistor. However, in the 
prior art, such a transistor is an n-type rather than being the p-type 
shown for the transistor 102 in FIG. 1. As a result of the charge and 
discharge of such distributed capacitances, a current signal on the line 
110 in FIG. 1 is produced in the n-type of transistor in the prior art 
with characteristics such as indicated at 116 in FIG. 2. This signal has a 
blip 118 which is produced upon a change from a non-conductive state to a 
conductive state in the operation of the n-type of transistor of the prior 
art. Similarly, the n-type of transistor corresponding in the prior art to 
the transistor 102 (p-type in this invention) produces a slow edge 119 
when the state of the transistor changes from a conductive to a 
non-conductive state. This results from the fact that the drain of the 
transistor in the prior art (corresponding to the transistor 106) must 
swing over a larger voltage range than this invention requires. The 
parasitic capacitances corresponding to the capacitances 112 and 114 and 
the large voltage swings interfere with the operation of the output 
circuitry in the prior art and they slow the response of such circuitry. 
A signal 122 in FIG. 2 may be introduced to the line 100 (FIG. 1). This 
causes the transistor 102 to become conductive. The production of a 
conductive state in the transistor 102 is also facilitated because it is 
in series with the transistor 106. The current through the transistor 106, 
and therefore through the transistor 102, has a predetermined value 
because of the fixed bias introduced to the base of the transistor 106 
through the circuitry shown in FIG. 3. When the transistor 102 becomes 
conductive, the charges in its parasitic capacitances 112 and 114 
facilitate the flow of current through the transistor 102. The distributed 
capacitances 112 and 114 accordingly aid the switching of the output 
transistor 104 from the conductive state to the non-conductive state, thus 
increasing the switching speed of the transistor 104. Furthermore, the 
voltage swing at the drain of the transistor 106 is reduced and this 
further increases the speed of switching the transistor 104. This results 
in the current wave forms 124 (FIG. 2) in the line 110 in FIG. 1. 
At the end of the signal on the line 100, the transistor 102 becomes 
non-conductive and the transistor 104 becomes conductive because of the 
bias voltage on the gate of the transistor 104. The resultant flow of 
current through the transistors 106 and 104 produces a rise in voltage on 
the drain of the transistor 106 and on the source of the transistor 104. 
Since this rise in voltage is from a value of approximately +1 volts which 
is produced on the sources of the transistors 102 and 104 when the 
transistor 102 is conductive, the rise in voltage on the drain of the 
transistor 104 is quite fast. This results in part from the fact that the 
voltage of approximately +1 volts on the source of the transistor 104 is 
quite close to the voltage of approximately +1.2 volts on the gate of the 
transistor. This is particularly true since the corresponding voltage on 
the source of the n-type of transistor in the prior art to the transistor 
corresponding 102 (p-type in this invention) is approximately 0 volts. The 
production of a positive voltage on the source of the transistor 104 is 
facilitated by the charging of the distributed capacitances 112 and 114 
when the transistor 102 becomes non-conductive. 
As a result of the discharge of the distributed capacitances 112 and 114 
through the transistor 102 in the circuitry shown in FIG. 1 when the 
transistor 102 becomes conductive, the slope of the signal produced if the 
distributed capacitors 112 and 114 did not discharge through the 
transistor 102. This may be seen from a comparison of the leading edge of 
the signal 124 (FIG. 2) produced on the line 110 by the circuitry shown in 
FIG. 1 in comparison to the leading edge of a signal 126 produced on the 
same line by the circuitry of the prior art. Furthermore, as will be seen 
from the signal 124, no blips are produced in the leading and trailing 
edges of the signal. 
The trailing edge of the output signal 124 produced by the circuitry shown 
in FIG. 1 is also sharper than the signal 126 produced by the circuitry of 
the prior art. This results from the reduced time, in comparison to the 
prior art, for the voltage on the drain of the transistor 104 to reach the 
proper value when the transistor 104 changes from a non-conductive state 
to a conductive state in the circuitry of this invention. 
As will be seen from the above discussion, the circuitry shown in FIG. 1 
and described above has certain advantages over the prior art. It provides 
on the output line 110 the signal 124 at a frequency in excess of 
eighty-five megahertz (85 mhz). It also provides the signal 124 with 
relatively sharp characteristics. This is in contrast to the prior art 
since the prior art provides the output signal 126 at a maximum frequency 
of approximately twenty-five megahertz (25 mhz) and with characteristics 
not nearly as sharp as those of the signal 124. 
FIG. 3 illustrates circuitry for regulating the biasing voltages introduced 
to the gates of the transistors 104 and 106. The circuitry shown in FIG. 3 
is disposed on an integrated circuitry chip. The circuitry shown in FIG. 3 
includes a pad 150 outside of the chip 60 for providing a reference 
voltage such as approximately 1.2 volts and a pad 152 outside of the chip 
60 for providing a reference voltage such as approximately -1.2 volts. A 
resistance 154 is disposed electrically between the pad 150 and a 
reference potential such as ground. 
Input terminals of an operational amplifier 156 are respectively connected 
to the pads 150 and 152. The output from the operational amplifier 156 is 
introduced to the gate of a transistor 158 such as a MOS transistor of the 
p-type. The source of the transistor 158 receives an energizing voltage 
such as approximately +5 volts. The drain of the transistor 158 and a 
source of a transistor 160 are common. Connections are respectively made 
from the gate and the drain of the transistor 160 to the pads 152 and 150. 
The transistor 160 may be a MOS transistor of the p-type. 
The output of the operational amplifier 156 is introduced to the gates of 
transistors 106a, 106b, etc. corresponding to the transistor 106 in FIG. 
1. Similarly, connections are made from the pad 152 to the gates of 
transistors 104a, 104b, etc. corresponding to the transistor 104 in FIG. 
1. Transistors 102a, 102b, etc. (corresponding to the transistor 102 in 
FIG. 10) are respectively connected to the transistors 104a and 106a and 
to the transistors 104b and 104b in a manner shown in FIG. 1. Lines 110a, 
110b, etc. are connected to the line 110 also shown in FIG. 1. Lines 103a, 
103b, etc. correspond to the line 103 in FIG. 1. 
A substantially constant current flows through a circuit including the pad 
150, the resistance 154 and the reference potential such as ground. This 
current is balanced in the operational amplifier 156 by the current 
produced in the amplifier as the result of the introduction of the voltage 
from the pad 152 to the amplifier. The current in the operational 
amplifier biases the transistor 158 to a state of conductivity so that 
current flows through the transistors 158 and 160 to the pad 150 to 
correct for any imbalances between the current flowing through the 
operational amplifier 156 and the current flowing through the resistance 
154. In this way, the bias introduced from the operational amplifier 156 
to the gate of the transistor 158 is substantially constant. 
The transistors 158 and 160 correspond respectively to the transistors 
106a, 106b, etc., and the transistors 104a, 104b, etc. As a result, the 
same current flows through the transistors 106a and 104a and through the 
transistors 106b and 104b as flows through the transistors 158 and 160. As 
a result, each of the circuits 106a and 104a, 106b and 104b, etc., 
provides a substantially constant current to the output line 110 in FIGS. 
1 and 3 when a signal is introduced to the gate of the associated one of 
the transistors 102a, 102b, etc., to make these transistors conductive. 
The magnitude of the cumulative current on the output line 110 indicates 
the analog value corresponding to the value of digital signals introduced 
to the gates of the transistors 102a, 102b, etc. in FIG. 3. The analog 
indication represented by the current on the line 110 is monotonic and 
provides minimal integral and differential non-linearities. 
Although this invention has been disclosed and illustrated with reference 
to particular embodiments, the principles involved are susceptible for use 
in numerous other embodiments which will be apparent to persons skilled in 
the art. The invention is, therefore, to be limited only as indicated by 
the scope of the appended claims.