Power device and fabricating method thereof

In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.

TECHNICAL FIELD

The concept relates to a power device, and more particularly, to a power device which uses a semiconductor substrate as a field stop layer and forms a drift region therein by growing an epitaxial layer of the semiconductor substrate, and a fabricating method thereof.

BACKGROUND

Recently, an Insulated Gate Bipolar Transistor (IGBT) has received attention as a power semiconductor device having both a high-speed switching characteristic of a high-power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a high-power characteristic of a Bipolar Junction Transistor (BJT). Among various types of IGBT structures, an IGBT of a Field Stop (FS) type may be understood as an IGBT of a soft punch-through type or a shallow punch-through type. Such an FS-IGBT may be understood as a combination of Non-Punch-Through (NPT) IGBT technology and PT IGBT technology, and accordingly, understood to have such a low saturation collector-emitter voltage Vice (sat), an easy parallel operation, and ruggedness as in the technologies.

SUMMARY

The inventive concept provides a power device, which has a Field Stop (FS) layer based on a semiconductor substrate between a collector region and a drift region in an FS-IGBT structure, wherein the thickness of the FS layer and the impurity density of the collector region are easy to adjust and the FS layer has an improved function, and a fabricating method thereof.

According to an aspect of the inventive concept, there is provided a power device including: a first-conductive-type semiconductor substrate; a FS layer which is formed on the semiconductor substrate through a first-conductive-type ion implant and has a section having a higher density than the semiconductor substrate; a drift region which is formed on the FS layer by growing a first-conductive-type epitaxial layer and has a lower density than the semiconductor substrate; a second-conductive-type base region formed on the drift region; a first-conductive-type emitter region formed on the surface of the second-conductive-type base region; a gate electrode formed by interposing a gate insulation layer on the drift region, the second-conductive-type base region, and the first-conductive-type emitter region; and a second-conductive-type collector region formed below the semiconductor substrate.

The FS layer may have a maximum impurity density at a first section with an impurity density increasing from the semiconductor substrate to the first section and decreasing from the first section to the drift region.

The FS layer may include at least two layers formed with different impurities or different doping energies. A layer adjacent to the semiconductor substrate among the at least two layers may have a higher impurity density than the other layers.

Each of the semiconductor substrate and the drift layer may have a constant density profile along a depth direction, the semiconductor substrate may have a higher density than the drift layer, and the FS layer may cancel a density difference between the semiconductor substrate and the drift layer and have a higher density than the semiconductor substrate.

According to another aspect of the inventive concept, there is provided a method of fabricating a power device, the method including: preparing a first-conductive-type semiconductor substrate; forming a second FS layer by implanting first-conductive-type impurity ions on the upper surface of the first-conductive-type semiconductor substrate; forming a drift region by growing a first-conductive-type epitaxial layer, which has a lower density than the first-conductive-type semiconductor substrate, on the second FS layer; forming a second-conductive-type base region on a predetermined section of the surface of the drift region; forming a first-conductive-type emitter region on a predetermined section of the surface of the second-conductive-type base region; forming a gate electrode by interposing a gate insulation layer on the drift region, the second-conductive-type base region, and the first-conductive-type emitter region; forming an emitter electrode on the second-conductive-type base region and the first-conductive-type emitter region; forming a first FS layer by grinding the lower surface of the first-conductive-type semiconductor substrate; and forming a second-conductive-type collector region below the first FS layer.

The forming the second FS layer may include diffusing the impurity ions by a heat treatment after implanting the impurity ions.

Each of the second-conductive-type base region and the first-conductive-type emitter region may be formed by selectively implanting corresponding ions in a predetermined part and diffusing the implanted ions by a heat treatment, and the second-conductive-type collector region may be formed by implanting corresponding ions in the lower surface of the ground semiconductor substrate and diffusing the implanted ions by a heat treatment.

According to another aspect of the inventive concept, there is provided a power device including: a first FS layer which is formed based on a first-conductive-type semiconductor substrate and has a constant impurity density along a depth direction; a second FS layer which is formed on the first FS layer through a first-conductive-type ion implant, has a variable impurity density along a depth direction, and has a higher peak area than the impurity density of the first FS layer; and a drift region formed on the second FS layer by growing a first-conductive-type epitaxial layer.

DETAILED DESCRIPTION

Exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings. In the description below, when it is described that a certain component is above another component, the certain component may be directly above another component, or a third component may be interposed therebetween. In the drawings, the thicknesses or sizes of components are exaggerated for convenience and clarity of description, and parts irrelevant to the description are omitted. Like reference numerals in the drawings denote like elements. The terminology used herein is for the purpose of describing the inventive concept only and is not intended to be limiting of the meaning or the scope of the inventive concept as defined by the appended claims.

FIGS. 1A and 1Bare cross-sectional views of power devices1000and1000aaccording to embodiments of the inventive concept.

Referring toFIG. 1A, the power device1000may include a Field Stop (FS) layer110, an implant FS layer120, a drift region130, a base region140, an emitter region150, and a collector region160.

The FS layer110may be formed based on a semiconductor substrate. For example, the FS layer110may be formed using an N0semiconductor substrate doped with an N-type impurity. In this case, the semiconductor substrate may be doped with an N-type impurity having enough density to form the FS layer110in a Field Stop-Insulated Gate Bipolar Transistor (FS-IGBT), i.e., enough density to prevent a depletion region from expanding to the collector region160of a P-type, which is formed on a surface of the semiconductor substrate opposite to a surface on which the drift region130is formed. The impurity density of the N0semiconductor substrate for forming the FS layer110may be, for example, about 1E14 cm−3to about 1E16 cm−3.

As such, the FS layer110based on the N0semiconductor substrate may have an almost constant density profile along a depth direction. That is, the FS layer110may completely have a uniform impurity density. This will be checked fromFIG. 2A or 2B.

Alternatively, the FS layer110may not use an initial semiconductor substrate as it is, and instead, a portion remaining after forming the implant FS layer120on the upper surface of the semiconductor substrate, grinding the lower surface of the semiconductor substrate, and forming the collector region160in a portion on the lower surface of the semiconductor substrate may be the FS layer110, as will be more clearly understood from the description of power device fabrication with respect toFIGS. 4 to 11.

In general, the semiconductor substrate forming the FS layer110may be produced by a Czochralski (CZ) method favorable in the production of large-diameter wafers. Since semiconductor substrates produced by the CZ method are more economical than substrates produced by a Float Zone (FZ) method, a semiconductor substrate produced by the CZ method may contribute to implementation of an economical power device.

The implant FS layer120may be formed on the FS layer110by implanting N-type impurity ions into the upper surface of the semiconductor substrate. In detail, the implant FS layer120may be formed by implanting N-type impurity ions into the upper surface of the N0semiconductor substrate and diffusing the impurity ions by a heat treatment. An impurity density of the implant FS layer120may gradually increase from the impurity density of the FS layer110to a maximum impurity density and then gradually decrease from the maximum impurity density to an impurity density of the drift region130on the implant FS layer120. For example, the maximum impurity density of the implant FS layer120may be about 1E15 cm−3to about 1E17 cm−3. Of course, the maximum impurity density of the implant FS layer120is not limited thereto. A density profile of the implant FS layer120may be checked fromFIGS. 2A and 2B.

The presence of the implant FS layer120may cause the thickness of the FS layer110to be decreased. That is, conventionally, when an FS layer is implemented only with an N0semiconductor substrate, since a collector region is formed in a portion on the lower surface of the N0semiconductor substrate in an opposite direction of the FS layer, an increase in density of the FS layer is limited, and accordingly, the FS layer is formed to be considerably thick to function as a normal FS layer. However, in the power device1000according to the current embodiment, since the implant FS layer120is separately formed, an increase in density and thickness of the FS layer110may not be required. Accordingly, the thickness of the FS layer110may be sufficiently decreased, resulting in a total thickness of the implant FS layer120and the FS layer110, which is smaller than the prior thickness of an FS layer. For example, while a conventional FS layer with a thickness equal to or greater than 10 μm is formed when no implant FS layer exists, in the power device1000, the total thickness of the implant FS layer120and the FS layer110may be equal to or less than 10 μm by forming the FS layer110with a thickness of several μm and the implant FS layer120with a thickness of several μm.

The implant FS layer120may function as a barrier for preventing holes in the P-type collector region160from passing therethrough to the drift region130.

The drift region130may be formed by growing an N-type epitaxial layer on the implant FS layer120. The drift region130may be formed with a lower density than that of the FS layer110. In detail, the drift region130may be formed by growing an N-type epitaxial layer with a density suitable for a breakdown voltage of an N-type power device on the implant FS layer120. For example, the drift region130may have a low impurity density that is equal to or less than 1E14 cm−3. The drift region130may have a variable thickness depending on a breakdown voltage required by the FS-IGBT. For example, when a breakdown voltage of about 600 V is required, the drift region130may formed with a thickness of about 60 μm.

The drift region130may have variable density of a doped impurity in epitaxial growth. Accordingly, the drift region130may have a constant or variable impurity density profile along a depth (or thickness) direction. That is, a density profile of an impurity in the drift region130may be changed by adjusting a type of impurity ions, implant energy, and a diffusion time in the drift region130. In the power device1000, a density profile of the drift region130may be constant along a depth direction. The density profile of the drift region130may be checked fromFIGS. 2A and 2B.

The base region140and the emitter region150may be formed in the upper surface of the drift region130. In more detail, the base region140may be formed by selectively implanting P-type impurity ions into the upper surface of the drift region130and diffusing the P-type impurity ions by a heat treatment. The base region140may be a high-density P-type (P+) impurity region. The base region140may form a P-N junction region together with the drift region130. The base region140may include a first base region P++(not shown) formed in an upper portion of the base region140and a second base region P−(not shown) formed below the first base region P++according to densities thereof. For example, the a first base region P++may have impurity density of about 1E19/cm3and a second base region P−(not shown) may have impurity density of about 1E17/cm3.

The emitter region150may be formed by selectively implanting N-type impurity ions into a predetermined region on the upper surface of the base region140and diffusing the N-type impurity ions by a heat treatment. The emitter region150may be a high-density N-type (N1) impurity region. For example, the emitter region150may have impurity density of about 1E18/cm3to about 1E20/cm3.

An emitter electrode200may be formed on the base region140and the emitter region150. A gate electrode300may be formed on the drift region130, the base region140, and the emitter region150with a gate insulation layer310therebetween. The gate electrode300may set a channel in a portion of the base region140, which is between the drift region130and the emitter region150, by applying a voltage thereto.

Although not shown, an insulation layer and/or a passivation layer covering the emitter electrode200and the gate electrode300may be formed.

The collector region160may be formed below the FS layer110. That is, the collector region160may be formed by grinding the lower surface of the semiconductor substrate, implanting P-type implant ions into the lower surface of the semiconductor substrate, and diffusing the P-type implant ions by a heat treatment. The collector region160may be formed to be very thin. For example, the collector region160may be formed with a thickness equal to or less than 1 μm. The collector region160may be a high-density P-type (P+) impurity region.

A collector electrode400may be formed below the collector region160.

Although an N-type power device has been described as an example, a P-type power device may also be implemented by changing conductive types of impurities in corresponding regions.

In the power device1000, the implant FS layer120may be formed by implanting impurity ions, thereby sophisticatedly and easily controlling an impurity density of the implant FS layer120. In addition, due to the sophisticated impurity density control, a thickness or a density profile of the implant FS layer120may be variously adjusted. Accordingly, the power device1000may considerably have improved electrical characteristics, e.g., an on-off switching waveform, thereby implementing a high-speed switching characteristic.

By forming the implant FS layer120separately from the FS layer110based on the semiconductor substrate, the impurity density of the collector region160formed below the FS layer110may be easily adjusted. In addition, since the FS layer110is formed by grinding the lower surface of the semiconductor substrate, a process of injecting high-energy ions for the FS layer110and an accompanying annealing diffusion process are unnecessary.

Referring toFIG. 1B, the power device1000aaccording to the current embodiment may be similar to the power device1000, except for an implant FS layer120a. That is, in the power device1000a, the implant FS layer120amay be formed by at least two layers, e.g., a lower implant FS layer122and an upper implant FS layer124. The implant FS layer120amay be formed by the at least two layers, namely, the lower and upper implant FS layers122and124, having different impurities and different doping energies. In addition, the thickness and impurity density of each of the at least two layers namely, the lower and upper implant FS layers122and124, forming the implant FS layer120amay vary depending on required characteristics of the power device1000a.

In the implant FS layer120aformed by a plurality of layers, an impurity density of a layer adjacent to the FS layer110may be higher than that of another layer. For example, an impurity density of the lower implant FS layer122may be generally higher than that of the upper implant FS layer124. In addition, among the layers forming the implant FS layer120a, an impurity density of a layer adjacent to the drift layer130may be lower than that of the FS layer110. For example, an impurity density of the upper implant FS layer124may be lower than that of the FS layer110. However, the impurity density of the implant FS layer120aformed by a plurality of layers is not limited thereto.

Although the implant FS layer120ais formed by two layers in the current embodiment, the implant FS layer120amay be formed by more than two layers. By forming the implant FS layer120aby several layers with various densities, a function as a field stop layer may increase. In addition, the thickness of the FS layer110based on the semiconductor substrate may be thin, thereby contributing to a decrease in a total size of the power device1000a.

FIGS. 2A and 2Bare graphs showing density profiles of the power devices1000and1000aofFIGS. 1A and 1B, respectively.

FIG. 2Ais a graph showing a density profile of the power device1000ofFIG. 1Aalong a depth direction, wherein an x-axis indicates depth, and a y-axis indicates impurity density. A depth of the x-axis indicates a depth from the upper surface of the drift region130to the collector region160, and the base region140and the emitter region150formed in the drift region130are excluded.

Referring toFIG. 2A, the drift region130(N-drift) grown by an N-type epitaxial layer has a constant impurity density along a depth direction. Of course, as described above, the drift region130may be formed so that the impurity density varies along a depth direction.

An impurity density of the implant FS layer120(Im-FS) gradually increases from a point contacting with the drift region130to a maximum impurity density point A and then gradually decreases to an impurity density of the FS layer110(N0-Sub). The implant FS layer120has a function to prevent a depletion region from expanding together with the FS layer110as described above. In addition, since a high-density portion may be formed in the implant FS layer120by an ion implant performed separately from that of the FS layer110, the high-density portion may be efficient to prevent a depletion region from expanding, thereby contributing to a minimum thickness of the FS layer110below the implant FS layer120.

The FS layer110based on the semiconductor substrate has a constant impurity density along a depth direction and has a rapidly decreasing impurity density in a portion contacting with the collector region160(Col). An impurity density of the collector region160rapidly increases from a portion contacting with the FS layer110so that the collector region160is a high-density P-type (P+) impurity region.

FIG. 2Bis a graph showing a density profile of the power device1000aofFIG. 1Balong a depth direction, wherein an x-axis indicates depth, and a y-axis indicates impurity density. A depth of the x-axis is as described above.

Referring toFIG. 2B, the drift region130(N-drift) has a constant impurity density along a depth direction as shown inFIG. 2A. Of course, the impurity density of the drift region130may vary along the depth direction.

The implant FS layer120a(Im-FS) may be classified into two layers based on a long-short-long line at the center thereof. The upper implant FS layer124(Up) on the left side contacts with the drift region130and has a gradually increasing impurity density from the impurity density of the drift region130. The lower implant FS layer122(Down) on the right side has a gradually increasing impurity density to a maximum impurity density point B and has a gradually decreasing impurity density to the impurity density of the FS layer110. As such, by forming the implant FS layer120aincluding two layers, the implant FS layer120amay efficiently perform the depletion field expansion prevention function together with the FS layer110(N0-Sub). The number of layers included in the implant FS layer120aand a density profile of the implant FS layer120amay be determined by generally considering required characteristics of the power device1000aand cost and time taken to form the implant FS layer120a.

The FS layer110based on the semiconductor substrate and the collector region160(Col) formed below the FS layer110are as described with reference toFIG. 2A.

FIG. 3is a graph showing density profiles according to impurity ions when an implant FS layer is formed with different impurity ions.

Referring toFIG. 3, the graph shows density profiles of the implant FS layer according to two-types of impurity ions. For example, A denotes a graph of a case where the implant FS layer is formed using arsenic (As) as impurity ions, and B denotes a graph of a case where the implant FS layer is formed using phosphorus (P) as impurity ions. In general, the phosphorus (P) may be favorable to form a wide implant FS layer since the phosphorus (P) is quickly diffused by a heat treatment, and the arsenic (As) may be favorable to form a narrow implant FS layer since the arsenic (As) is slowly diffused by a heat treatment.

When an implant FS layer is formed, which impurity ions are used may be determined depending on required characteristics and a size of a power device. For example, when a thin implant FS layer is formed to maintain a relatively high impurity density, impurity ions that hardly diffuse may be used.

FIGS. 4 to 11are cross-sectional views showing a method of fabricating the power device1000ofFIG. 1A, according to an embodiment of the inventive concept.

Referring toFIG. 4, a first-conductive-type semiconductor substrate100, e.g., an N0semiconductor substrate doped with N-type impurity ions, is prepared. The N0semiconductor substrate100may be doped with an impurity having density required to form an FS layer in an FS-IGBT, i.e., N-type impurity ions having enough density to prevent a depletion region from expanding to a P-type collector region formed on a lower surface of the substrate. For example, The N0semiconductor substrate100having an impurity density of about 1E14 cm−3to about 1E16 cm−3is prepared. An impurity density profile in the semiconductor substrate100may be constant along the depth (or thickness) direction as shown inFIG. 2A or 6B.

The semiconductor substrate100may be produced by the CZ method favorable in the production of large-diameter wafers. Of course, a substrate produced by the FZ method is not excluded.

Referring toFIG. 5, an implant FS layer120is formed by implanting N-type impurity ions into the upper region of the semiconductor substrate100a. When the implant FS layer120is formed, after implanting the N-type impurity ions, a diffusion process by a heat treatment may be performed. In some cases, the diffusion process may be omitted. An impurity density of the implant FS layer120may vary along a depth direction and have a density of about 1E15 cm−3to about 1E17 cm−3. The implant FS layer120may be formed to be thin with a thickness of several μm. In some cases, the implant FS layer120may be formed with a thickness of tens μm.

The implant FS layer120may be formed by a plurality of layers as shown inFIG. 1B. In this case, impurity ions and/or impurity densities of the plurality of layers forming the implant FS layer120may be different from each other. In addition, the plurality of layers forming the implant FS layer120may be formed with different impurity ions and/or different doping energy and may be formed to have the same or a different thickness.

Referring toFIG. 6A, a drift region130ais formed on the implant FS layer120by growing an epitaxial layer of a conductive type identical to a first conductive type, i.e., an N type. The drift region130amay have a lower impurity density than a semiconductor substrate100a. The drift region130amay be formed by growing an N-type epitaxial layer having density suitable for a breakdown voltage of an N-type power device, e.g., an FS-IGBT. The thickness of the drift region130amay vary depending on a required breakdown voltage of the FS-IGBT. For example, when a breakdown voltage of about 600 V is required, the drift region130amay be formed with a thickness of about 60 μm.

When the drift region130ais epitaxially grown, a density of a doped impurity may be adjusted. Accordingly, the drift region130amay have a constant or variable impurity density profile along the depth (thickness) direction. That is, the impurity density profile of the drift region130amay vary depending on the desire of a designer. In the power device1000, the impurity density profile of the drift region130amay be constant along a depth direction as shown inFIG. 6B.

Referring toFIG. 6B, a graph shows a brief impurity density from the semiconductor substrate100ato the drift region130aafter the drift region130ais formed. The semiconductor substrate100aand the drift region130amaintain a constant impurity density along a depth direction. Of course, as described above, the impurity density of the drift region130amay vary in some cases.

The impurity density of the implant FS layer120gradually increases from the impurity density of the semiconductor substrate100ato a maximum ion density point C and then gradually decreases to the impurity density of the drift region130a. The implant FS layer120may offset a density difference between the drift region130aand the semiconductor substrate100aand form a high-density ion barrier. Accordingly, the implant FS layer120may prevent diffusion of a depletion region and prevent holes from passing therethrough from a collector region.

Referring toFIG. 7, a base region140of a P-type is formed by selectively implanting impurity ions of a second conductive type other than the first conductive type, e.g., the P type, into a predetermined region of the upper surface of the drift region130aand diffusing the implanted P-type impurity ions. The base region140may be a high-density P-type (P1) impurity region and may form a P-N junction region together with the drift region130a.

An emitter region150of an N-type is formed by selectively implanting the first-conductive-type, i.e., the N-type, impurity ions into a predetermined region of the upper surface of the base region140and diffusing the implanted N-type impurity ions. The emitter region150may be a high-density N-type (N+) impurity region. The diffusion processes described above may be performed together in a heat treatment process performed after implanting the impurity ions.

Referring toFIG. 8, after the emitter region150is formed, an emitter electrode200contacting with the base region140and the emitter region150is formed. In addition, a gate insulation layer310is formed on the surface region of the drift region130and a portion of the upper surfaces of the base region140and the emitter region150, and a gate electrode300is formed on the gate insulation layer310. The gate electrode300may set a channel in a portion of the base region140, which is between the drift region130and the emitter region150, by applying a voltage thereto.

Although not shown, an insulation layer and/or a passivation layer covering the emitter electrode200and the gate electrode300may be further formed after the emitter electrode200and the gate electrode300are formed.

The above-described process may be performed as in a Double-Diffused Metal-Oxide Semiconductor (DMOS) fabricating process or a trench gate-type MOSFET process.

Referring toFIG. 9, the semiconductor substrate100ais formed as an actual FS layer110a. That is, although an FS layer in a power device, e.g., an FS-IGBT structure, is actually formed with a less thickness than a drift region, the current semiconductor substrate100ais very thick. Thus, the lower surface of the semiconductor substrate100ais ground to reduce its thickness.

Since a collector region160will be formed below the FS layer110a, the remaining thickness of the semiconductor substrate100ais set by taking the thickness of the collector region into account. For example, when the thickness of the drift region130is set to about 110 μm, the remaining thickness of the semiconductor substrate100afor the FS layer110amay be considered to be about 5 μm to about 15 μm. In this case, the thickness of the collector region160may be considered to be very thin, e.g., about 0.3 μm to about 1 μm. Of course, the remaining thickness of the semiconductor substrate100aand the thickness of the collector region160are not limited thereto.

The actual FS layer110ais formed by grinding the lower surface of the semiconductor substrate100ain consideration with the remaining thickness thereof. As such, since the FS layer110ais formed by grinding the lower surface of the semiconductor substrate100a, a high-energy ion injection process and an accompanying annealing diffusion process for the FS layer110amay be excluded. In addition, since the implant FS layer120has already been formed on the upper surface of the semiconductor substrate100aby an ion implant, the FS layer110abased on the semiconductor substrate100amay be formed to be sufficiently thin.

In addition, since the semiconductor substrate100amaintains a sufficient thickness before the grinding process, the semiconductor substrate100amay functions as a supporting substrate in a process for forming the base region140, the emitter region150, the emitter electrode300, and the insulation layer. Thus, the limitation which may occur when a thin substrate is used, e.g., a substrate roll phenomenon, and a heat process limit for solving the roll phenomenon may be excluded.

Referring toFIG. 10, a collector region160is formed below the lower surface of an FS layer110by implanting impurity ions of the second conductive type opposite to the first conductive type, e.g., a P type, into the surface of the ground FS layer110aand annealing and diffusing the implanted P-type impurity ions. In this case, an impurity density of the collector region160may be determined depending on a device switching-off characteristic. The collector region160may be a high-density P-type (P+) impurity region, and may be formed with a thin thickness equal to or less than 1 μm as described above.

In the power device1000according to the current embodiment, the implant FS layer120is formed separately from the FS layer110based on a semiconductor substrate. Accordingly, the impurity density of the collector region160formed below the lower surface of the FS layer110based on a semiconductor substrate may be freely adjusted in some levels. That is, the conventional confliction between a requirement that the FS layer110should be formed with high density to improve a function of the FS layer110and a requirement that the FS layer110should be formed with low density to form the collector region160therein may be excluded by separately forming the implant FS layer120on the FS layer110in the power device1000according to the current embodiment.

Referring toFIG. 11, by forming a collector electrode400below the lower surface of the collector region160, the power device1000as shown inFIG. 1A, e.g., an FS-IGBT, is formed.

FIG. 12is a cross-sectional view of a power device1000baccording to an embodiment of the inventive concept. Since the power device1000bofFIG. 12has the same configuration as that ofFIG. 1Aexcept for the base region140, the emitter region150, a gate electrode300aand a gate insulation layer310a, the descriptions made with respect toFIG. 1Aare repeated in brief or omitted for convenience of description. The base region140may include a first base region P++(not shown) formed in an upper portion of the base region140and a second base region P−(not shown) formed below the first base region P++according to densities thereof. For example, the a first base region P++may have impurity density of about 1E19/cm3and a second base region P−(not shown) may have impurity density of about 1E17/cm3.

That is, the power device1000bmay have a trench-gate structure in which a insulation layer310ais formed on a trench (T) which is formed down to a predetermined depth into the drift region from the upper surface of the drift region130and a first sidewall of the trench (T) is adjacent to the first side of first-conductive-type emitter region and the second-conductive-type base region. As shown inFIG. 12, the base region140and the emitter region150may be disposed at a first sidewall of the trench (T). In addition, although not shown, a second side of the other base region and the emitter region are also adjacent to a second sidewall of the trench (T) according to a symmetrical structure. Although the gate insulation layer310ais formed to cover the upper surface of the emitter region150inFIG. 12, the gate insulation layer310amay not be formed on the upper surface of the emitter region150according to circumstances.

Referring toFIG. 12, a gate electrode300adisposed on the gate insulation layer310a. An upper end portion of the gate electrode300amay have the same plane as an upper end portion of the drift region130as shown inFIG. 12, or may be formed to further protrude by a predetermined length on a plane from the upper end portion of the drift region130although not shown.

In addition, although the implant FS layer120is shown as a single layer inFIG. 12, the implant FS layer120may be formed by at least two layers having different densities as shown inFIG. 1B.

In one general aspect, a power device can include a first-conductive-type semiconductor substrate, and a Field Stop (FS) layer of a first-conductive-type disposed on the semiconductor substrate. The FS layer has a section having an impurity density higher than an impurity density of the semiconductor substrate. The power device can include a drift region of a first-conductive-type epitaxial layer disposed on the FS layer and having an impurity density lower than the impurity density of the semiconductor substrate. The power device can include a second-conductive-type base region disposed in an upper portion of the drift region, and a first-conductive-type emitter region disposed in an upper portion of the second-conductive-type base region. The power device can include a gate electrode on a gate insulation layer where the gate insulation layer is over the drift region, the second-conductive-type base region, and the first-conductive-type emitter region. The power device can include a second-conductive-type collector region disposed below the semiconductor substrate.

In some implementations, the FS layer has a maximum impurity density at a first section, and an impurity density of the FS layer increases from the semiconductor substrate to the first section and decreases from the first section to the drift region. In some implementations, the impurity density rapidly decreases at a portion of the FS layer, and the portion of the FS layer contacts the drift region.

In some implementations, the FS layer includes at least two layers with different impurities. In some implementations, at least two layers includes a first layer adjacent to the semiconductor substrate, and the first layer has an impurity density higher than an impurity density of a second layer from the at least two layers. In some implementations, the at least two layers includes a layer adjacent to the drift region, and the layer has an impurity density lower than the impurity density of the semiconductor substrate.

In some implementations, each of the semiconductor substrate and the drift region has a constant impurity density profile along a depth direction, and the semiconductor substrate has the impurity density higher than the impurity density of the drift region. In some implementations, the FS layer cancels a density difference between the semiconductor substrate and the drift region and has a portion with an impurity density higher than the impurity density of the semiconductor substrate.

In some implementations, the semiconductor substrate has an impurity density of about 1E14 cm−3to about 1E16 cm−3, and the FS layer includes a portion having an impurity density of about 1E15 cm−3to about 1E17 cm−3. In some implementations, the power device can include an emitter electrode electrically connected to the first-conductive-type emitter region, and a collector electrode electrically connected to the second-conductive-type collector region. In some implementations, the semiconductor substrate includes a Czochralski (CZ) single-crystal.

In another general aspect, a method of fabricating a power device can include preparing a first-conductive-type semiconductor substrate, and forming a second Field Stop (FS) layer by implanting first-conductive-type impurity ions in an upper surface of the first-conductive-type semiconductor substrate. The method can include forming a drift region by growing a first-conductive-type epitaxial layer, which has an impurity density lower than an impurity density of the first-conductive-type semiconductor substrate, on the second FS layer. The method can include forming a second-conductive-type base region in a section of the surface of the drift region, and forming a first-conductive-type emitter region in a section of the surface of the second-conductive-type base region. The method can include forming a gate insulation layer over the drift region, the second-conductive-type base region, and the first-conductive-type emitter region. The method can include forming a gate electrode on the gate insulation layer, and forming an emitter electrode on the second-conductive-type base region and on the first-conductive-type emitter region. The method can also include forming a first FS layer by grinding a lower surface of the first-conductive-type semiconductor substrate, and forming a second-conductive-type collector region below the first FS layer.

In some implementations, a sum of a thickness of the second FS layer and a thickness of the first FS layer is less than the thickness of the first FS layer when the second FS layer is not formed. In some implementations, the forming the second FS layer includes diffusing the first-conductive-type impurity ions by a heat treatment after implanting the first-conductive-type impurity ions.

In some implementations, the second FS layer includes at least two layers formed with different impurities or different doping energies. In some implementations, the at least two layers includes a first layer adjacent to the first FS layer, the first layer has an impurity density higher than an impurity density of a second layer from the at least two layers.

In some implementations, each of the first FS layer and the drift layer has a constant impurity density profile along a depth direction, and the first FS layer has an impurity density higher than an impurity density of the drift layer. The second FS layer includes a region having an impurity density higher than an impurity density of the first FS layer, and the impurity density of the second FS layer increases and then decreases to cancel a density difference between the first FS layer and the drift layer.

In some implementations, the first FS layer has an impurity density of about 1E14 cm−3to about 1E16 cm−3, and the second FS layer includes a portion having an impurity density of about 1E15 cm−3to about 1E17 cm−3. In some implementations, each of the second-conductive-type base region and the first-conductive-type emitter region is formed by selectively implanting corresponding ions in a predetermined part and diffusing the implanted ions by a heat treatment, and the second-conductive-type collector region is formed by implanting corresponding ions into the lower surface of the ground semiconductor substrate and diffusing the implanted ions by a heat treatment.

In another general aspect, a power device can include a first Field Stop (FS) layer based on a first-conductive-type semiconductor substrate and having an impurity density that is constant along a depth direction. The power device can include a second FS layer of a first-conductive-type which is disposed on the first FS layer, has an impurity density that is variable along the depth direction, and has a peak impurity density area higher than the impurity density of the first FS layer. The power device can also include a drift region of a first-conductive-type epitaxial layer disposed on the second FS layer. In some implementations, the drift region has a constant impurity density along the depth direction and has an impurity density less than the impurity density of the first FS layer.

In yet another general aspect, a power device can include a first conductive semiconductor substrate, and a Field Stop (FS) layer which is disposed on the first conductive semiconductor substrate, has a first conductive type, and has a section having a higher density than the first conductive semiconductor substrate. The power device can include a drift region which is disposed on the FS layer, is formed as a first-conductive-type epitaxial layer and has a lower density than the first FS layer. The power device can include a second-conductive-type base region disposed in an upper portion of the drift region, and a first-conductive-type emitter region disposed in a surface portion of the second-conductive-type base region. The power device can include a gate electrode on a gate insulation layer, where the gate insulation layer is disposed on the surface of a trench which is formed down to a predetermined depth into the drift region. The power device can include a second-conductive-type collector region disposed below the FS layer.

In some implementations, a first sidewall of the trench which is adjacent to the first side of the first-conductive-type emitter region and the second-conductive-type base region. In some implementations, the FS layer has a maximum impurity density at a first section, an impurity density of the FS layer increases from the first conductive semiconductor substrate to the first section and decreases from the first section to the drift region. In some implementations, the FS layer comprises at least two layers having different densities.

In some implementations, each of the first conductive semiconductor substrate and the drift region (or layer) has a constant impurity density profile along a depth direction, and the first conductive semiconductor substrate has the impurity density higher than the impurity density of the drift region, and the FS layer cancels a density difference between the first conductive semiconductor substrate and the drift region and has a portion with an impurity density higher than the impurity density of the first conductive semiconductor substrate.