Non-volatile memory device

A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2011-0060117 filed on Jun. 21, 2011 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a non-volatile memory device and a method of manufacturing thereof, and more particularly, to an air gap isolation structure to minimize cell-to-cell interference and method of manufacturing the gap isolation structure in the non-volatile memory device.

DESCRIPTION OF THE RELATED ART

With integration density increasing, cell-to-cell distance decreases, a charge trap non-volatile memory suffers from memory cell errors arising from cell-to-cell interference. For example, when some data are programmed in a memory cell of the charge trap non-volatile memory device, an adjacent memory cell neighboring the memory cell is also programmed into the same data by the interference between neighboring memory cells. Accordingly, a charge trap non-volatile memory is desired to have a device isolation structure to suppress the cell-to-cell interference.

SUMMARY

Exemplary embodiments of the present inventive concept provide a non-volatile memory device in which cell-to-cell interference is minimized.

In an embodiment of the inventive concept, a non-volatile memory device comprises a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.

In a further embodiment, the tunnel insulation layer is conformally formed on the active region and the trench. The trap insulation layer is positioned on the tunnel insulation layer formed on active region and is not connected to other insulation layers adjacent to the trap insulation layer. The one of the insulation layer extending is the blocking insulation layer positioned on the trap insulation layer. The top of the air gap is defined by the trap insulation layer and the blocking insulation layer.

Alternatively, the trap insulation layer is positioned on tunnel insulation layer formed on the active region, and the one of the insulation layer extending is the trap insulation layer. The top of the air gap is defined by the trap insulation layer and the bottom is defined by a portion of the tunnel insulation layer that is formed on the device isolation pattern.

Alternatively, the tunnel insulation layer is positioned on the active region, and the one of the insulation layer extending is the tunnel insulation layer. The top of the air gap is defined by the trap insulation layer and the bottom is defined by a top surface of the device isolation pattern.

Lastly, the tunnel insulation layer is positioned on the active region and is not connected to other tunnel insulation layers adjacent to the tunnel insulation layer. The one of the insulation layer extending is the trap insulation layer positioned on the tunnel insulation layer. The top of the air gap is defined by the tunnel insulation layer and the trap insulation layer and the bottom is defined by a top surface of the device isolation pattern.

In another further embodiment, the one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap. Width of the trench decreases with increasing depth and a corner angle between an upper surface of the active region and a sidewall of the trench is over 90°. The trap insulation layer includes any one material selected from the group consisting of silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide and compositions thereof. The tunnel insulation layer includes one of a silicon oxide layer and a silicon oxynitride layer.

In an another embodiment of the inventive concept, a method of manufacturing a non-volatile memory device comprise a step forming a trench on a substrate and an active region defined by the trench, a step of forming a device isolation pattern positioned at a lower portion of the trench, a step of forming a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking dielectric layer that are sequentially stacked on the active region, a step of forming one of the insulation layers extending from the active region toward the device isolation region to enclose top of an air gap, bottom of the air gap being defined by a layer other than that of the top, and a step of forming a control gate electrode positioned on the cell structure.

In a further embodiment, the step of forming one of the insulation layers extending is carried out with the substrate tilted at a first tilt angle, and then at a second tilt angle.

In a still another embodiment of the inventive concept, a non-volatile memory device comprises a substrate, a first active region in the substrate, a second active region in the substrate, a memory cell layer formed on the first and second active regions having a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the first and second active regions, and a trench including a device pattern isolation at a lower portion of the trench that is positioned between the first and second active regions in the substrate and includes an air gap, the air gap having top defined by at least one of the insulation layers and bottom defined by a layer other than that of the top of the air gap.

In a further embodiment, the air gap has the top defined by the trap insulation layer and the blocking insulation layer, the bottom defined by a portion of the tunnel insulation layer that is formed on the device isolation pattern and side defined by a portion of the tunnel insulation layer that is formed on sidewalls of the trench.

Alternatively, the air gap has the top defined by the trap insulation layer, the bottom defined by a portion of the tunnel insulation layer that is formed on the device isolation pattern and side defined by a portion of the tunnel insulation layer that is formed on sidewalls of the trench.

Alternatively, the air gap has the top defined by the tunnel insulation layer, the bottom defined by a top surface of the device isolation pattern and side defined by sidewalls of the trench.

Lastly, the air gap has the top defined by the tunnel insulation layer and the trap insulation layer, the bottom defined by a top surface of the device isolation pattern, and side defined by sidewalls of the trench.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

FIG. 1is a perspective view of a charge trap non-volatile memory device according to a first embodiment of the present inventive concept.FIG. 2is a cross-section view of the charge trap non-volatile memory device along with the line A-A′ ofFIG. 1according to the first embodiment of the inventive concept.

Referring toFIGS. 1 and 2, the charge trap non-volatile memory device may include an active region200, an isolation region300, memory cell layers110,112and114. The active region200and the isolation region300may be formed in a substrate100. The active region200may be positioned between two neighboring isolation regions300. The isolation region300may include a device isolation trench106and an air gap116. The device isolation trench106may extend in a first direction I and a plurality of the trenches106arrange in a second direction II perpendicular to the first direction I. A sidewall of the trench106may be straight or linear from a top to bottom of the trench in such a configuration that width of the trench106may gradually decrease with increasing depth. The trench106may have a rounded end at the bottom of the trench. Since the width of the trench106may gradually decrease with increasing depth, a corner angle C between an upper surface of the active region200and a sidewall of the trench106may be larger than 90°.

The air gap116may have a first side and a bottom defined by a tunnel insulation layer110on the trench and a top defined by a trap insulation layer112and a blocking insulation layer114. The air gap116may be filled with air, which is known as having the lowest dielectric constant except vacuum. As a result, the air gap116of the isolation region300may reduce parasitic capacitance between neighboring active regions200due to the low dielectric constant.

The isolation region300may also include a device isolation pattern108a. The device isolation pattern108amay be positioned at a lower portion of the trench106and an upper surface of the device isolation pattern108amay be lower than the upper surface of the substrate100of the active region200. As a result, the isolation region300may include the air gap116and the device isolation pattern108aand a lateral portion of the air gap116may be conformal to the straight sidewall of the trench106, especially to the sidewall of the upper portion of the trench106. That is, the lateral portion of the air gap116may also be straight or linear. The air gap116and device isolation pattern118amay run along the device isolation trench106between the neighboring active regions200. The air gap116positioned between the active regions200at upper portion of the isolation region300may sufficiently reduce the parasitic capacitance between the neighboring active regions200, and the device isolation pattern positioned at lower portion of the isolation region300may electrically isolate two neighboring active regions200.

The memory cell layers110,112and114may include a tunnel insulation layer110, a trap insulation layer112and a blocking insulation layer114. The memory cell layer110,112and114on the active region200may function as a memory storage cell of a non-volatile memory. The tunnel insulation layer110may be conformally formed on the active region200of the substrate100, sidewalls of the device isolation trench106and the device isolation pattern108a. The tunnel insulation110does not fill the device isolation trench106. The tunnel insulation layer110may be an insulation layer having a low dielectric constant such as silicon oxide, silicon oxynitride, and doped polysilicon.

The thickness of the tunnel insulation layer110may also affect the parasitic capacitance of the insulation region300because the thickness may determine width of the air gap defined by sidewalls of the tunnel insulation layer110inside the device isolation trench106. The larger width of the air gap may lead to the less parasitic capacitance of the isolation region300.

For example, the trench106has a width below about 50 nm, and more particularly, below about 20 nm. When the width of the trench106may be less than about 20 nm, the air gap116may have a width of about a few nanometers.

The trap insulation layer112may be positioned on a part of the tunnel insulation layer110, including an active trap insulation layer112aand a field trap insulation layer112b. The field trap insulation layer112bmay have a portion having thickness larger than that of the active trap insulation layer112a. The active trap insulation layer112amay be positioned on a top surface of the tunnel insulation layer110that may be formed on the active region200. The field trap insulation layer112bmay be positioned at the corner of the tunnel insulation layer110and may not be positioned on the remaining portion of the tunnel insulation layer110that may be formed on the sidewalls of the device isolation trench106. Two neighboring trap insulation layer112may do not meet each other. The field trap insulation layers112bof the two neighboring trap insulation layer112may do not meet one another. The shortest distance between the two neighboring field trap insulation layers112bmay be smaller than a distance between facing sidewalls of the tunnel insulation layer110at an upper portion of the trench106. The amount of charges trapped in the trap insulation layer112may determine one of data states of a memory cell: a data-on state and a programmed state.

The trap insulation layer112may be a layer having a high dielectric constant such as silicon nitride, silicon oxynitride, hafnium silicon oxide, aluminum oxide and hafnium oxide. The dielectric constant of the trap insulating layer112may be higher than that of the tunnel insulation layer.

A blocking insulation layer114may be positioned on the trap insulation layer112that may be disconnected to each other, enclosing the gap between the neighboring two trap insulation layers to form the air gap that may be filled with air and enclosed by the tunnel insulation layer110, the second trap insulation layer112band the blocking dielectric layer114. Air is known as having the lowest dielectric constant except vacuum, so the air gap116of the isolation region300may reduce interference between neighboring active regions200due to its low dielectric constant.

The blocking insulation layer114may be a layer of metal oxide having a high dielectric constant. Examples of the metal oxide may include hafnium oxide, titanium oxide, tantalum oxide, aluminum oxide, and zirconium oxide. These may be used alone or in combinations thereof.

A control gate electrode118may be positioned on the blocking layer114having a sufficiently planarized surface. The control gate electrode118may be a line extending in the second direction II and may include high conductive materials. Example of the conductive materials may include a doped polysilicon, a metal, a metal nitride, and a metal silicide. These materials may be used alone or in combinations thereof.

Hereinafter, a method of manufacturing the non-volatile memory devices ofFIG. 1will be described in detail.

FIGS. 3 to 11Bare cross-sectional views illustrating a method of manufacturing the non-volatile memory device ofFIG. 1.

FIG. 3shows a step of forming a hard mask pattern104necessary to form a device isolation trench on the substrate100according to the first embodiment of the present inventive concept. A buffer oxide layer and a hard mask layer may be sequentially formed on the semiconductor substrate100including single crystalline silicon. The buffer oxide layer may be formed by a thermal oxidation process against the substrate100and the hard mask layer may be formed by deposition of polysilicon on the buffer oxide layer.

The buffer oxide layer and the hard mask layer may be sequentially patterned to thereby form a buffer oxide pattern102and a hard mask pattern104that may be extended in the first direction I. The hard mask pattern104may function in the subsequent process as a mask pattern for forming a device isolation trench on the substrate100.

FIG. 4shows a step of forming a trench106using the mask pattern104according to the first embodiment of the present inventive concept. The substrate100may be partially removed by an anisotropic etching process using the hard mask pattern as an etching mask, to thereby form the trench106on the substrate100. The trench106functions as a device isolation region300of the substrate100. A part of the substrate100covered with the hared mask pattern104may not be removed by the same etching process and may be defined by the two neighboring trenches106. The part of the substrate100may function as an active region of the substrate100. Under the anisotropic etching process, width of the device isolation trench106may gradually decrease with increasing depth. The device isolation trench106may also have a rounded end at the bottom of the device isolation trench106. Thus the sidewall of the device isolation trench106may have a certain slope with respect to an upper surface of the substrate100and may be straight from a top to a bottom of the trench without any curved portions.

For example, the trench106may be formed to have a width below about 50 nm, and more particularly, below about 20 nm.

A sidewall oxide layer (not shown) may be formed on the sidewall of the trench106by a thermal oxidation process.

FIG. 5andFIG. 6show a step of form an isolation pattern108ain the trench106according to the first embodiment of the present inventive concept. InFIG. 5, an insulation layer having good gap-fill characteristics (not shown) may be formed on the substrate100to a sufficient thickness to fill up the trench106and a gap between the hard mask patterns104. For example, the insulation layer is a TOSZ oxide layer deposited using a spin-on coating process. Then, the insulation layer may be planarized until a top surface of the hard mask pattern104may be exposed, to thereby form a preliminary device isolation pattern108on the substrate100.

InFIG. 6, the device isolation pattern108amay be recessed to a predetermined depth of the trench106. The hard mask pattern104may be removed first. Then the buffer oxide pattern102and the preliminary device isolation pattern108may be subject to an etching process. The preliminary device isolation pattern108may be recessed until the buffer oxide pattern102may be removed on the substrate100. The remaining portion of the preliminary isolation pattern108may be the device isolation pattern108a. The height of the device isolation pattern108ameasured from the bottom of the trench106may determine a height of the air gap between the neighboring active regions of the substrate100. That is, the lower the height of the device isolation pattern108a, the higher the height of the air gap between the active regions.

The resulting structure ofFIG. 6may include the device isolation pattern108aat the lower portion of the trench106, and may expose an upper sidewall of the trench106and an upper surface of the substrate. The upper portion of the trench106corresponding to the recessed portion of the preliminary device isolation pattern108may be formed into the air gap116in subsequent processes, and thus lateral portions of the air gap116may be conformal to the straight sidewall of the upper portion of the trench106.

FIG. 7shows a step of forming a tunnel insulation layer110according to the first embodiment of the present inventive concept. The tunnel insulation layer110may be conformally formed on the upper surface of the active region200of the substrate100, on the upper sidewall of the trench106and on the device isolation pattern108a, forming an open space116abetween the facing sidewalls of the tunnel insulation layer100. As the thickness of the tunnel insulation layer110increases, the width of the open space116adecreases. The tunnel insulation layer110may be an insulation layer having a low dielectric constant such as silicon oxide, silicon oxynitride, and doped polysilicon. The dielectric constant of the tunnel insulation layer110may be larger than that of air, but smaller than that of the trap insulation layer.

FIG. 8,FIG. 9AandFIG. 9Bshow a step of forming a trap insulation layer112according to the embodiment 1 of the present inventive concept.FIG. 8shows a resulting structure having the trap insulation layer112and an empty space116bfrom performing a deposition method explained below usingFIGS. 9A and 9B. The trap insulation layer112may be a layer having a high dielectric constant such as silicon nitride, silicon oxynitride, hafnium silicon oxide, aluminum oxide and hafnium oxide. The dielectric constant of the trap insulating layer112may be higher than that of the tunnel insulation layer.

InFIGS. 9A and 9B, the trap insulation layer112ofFIG. 8may be formed by two consecutive deposition steps using a jet deposition process, both by rotating and by tilting a substrate at a predetermined tilt angle according to the first embodiment of the present inventive step. The characteristics of the jet deposition process may be a high degree of directionality of reaction gases to a substrate. The better the directionality, the more collimated the reaction gases, resulting in a deposition layer having poor step coverage and poor conformality.

In a first step ofFIG. 9A, the jet deposition process may be carried out while a substrate may be rotated at a first direction, for example, clockwise. The substrate may also be tilted rightward at a first tilt angle θ1, resulting in the highest deposition rate at a left portion L. This difference of the deposition rate may result in a varying thickness of the first trap insulation layer111athat decrease from a left portion L to a right portion R of the substrate100. Particularly, the first trap insulation layer111amay have the largest thickness around the corner of the left portion L. Due to the high directionality and tilting the substrate, few reaction gases for depositing the first trap insulation layer111amay hit the lower portion of the trench106. The reaction gases, if any, may not form a layer at the lower portion of the trench106.

After a formation of the first trap insulation layer111a, the second step ofFIG. 9Bmay be carried out under a different arrangement of the substrate. For example, the substrate100may be rotated at a second direction of counterclockwise. The substrate100may also be tilted leftward at a second tilt angle θ2, resulting in the highest deposition rate at a right portion R. Particularly, the second trap insulation layer111bhas the largest thickness around the corner of the right portion R. Due to the high directionality and tilting the substrate, few reaction gases for depositing the second trap insulation layer111bhit the lower portion of the trench106. The reaction gases, if any, do not form a layer at the lower portion of the trench106. The thickness distribution of the first and second trap insulation layers111aand111bmay be controlled to form a uniform thickness distribution of the combined first and second trap insulation layers111aand111bon a top surface of the tunnel insulation layer110. The first and second trap insulation layers111aand111bmay merely be formed at the corner portions L and R of the trench106and the top surface of the tunnel insulation layer other than the lower portion of the trench106. As a result, the combined first and second trap insulation layers111aand111bmay be disconnected at every device isolation region300of the substrate100.

Due to the tilting of the substrate100, the deposition source gases, even though they have a high degree of directionality to the substrate100, may not be deposited on the tunnel insulation layer110that may be formed at the lower portion of the trench106, resulting in the empty space116b.

FIG. 10,FIG. 11AandFIG. 11Bshow a step of forming a blocking insulation layer114according to the first embodiment of the present inventive concept.FIG. 10shows a resulting structure having the blocking insulation layer114and an air gap116from performing a deposition method explained below usingFIGS. 11A and 11B. The blocking insulation layer114may be a layer of metal oxide having a high dielectric constant. Examples of the metal oxide include hafnium oxide, titanium oxide, tantalum oxide, aluminum oxide, and zirconium oxide. These may be used alone or in combinations thereof.

InFIGS. 11A and 11B, the blocking insulation layer112ofFIG. 10may be formed using a deposition method used in forming the trap insulation layer112explained above. The deposition method includes two consecutive deposition steps using a jet deposition process, both by rotating and by tilting a substrate at a predetermined tilt angle according to the first embodiment of the present inventive step. The characteristics of the jet deposition process may be a high degree of directionality of reaction gases to a substrate. The better the directionality, the more collimated the reaction gases, resulting in a deposition layer having poor step coverage and poor conformality.

In a first step ofFIG. 9A, the jet deposition process may be carried out when a substrate may be rotated at a first direction of clockwise. The substrate may also be tilted rightward at a third tilt angle θ3, resulting in the highest deposition rate at a left portion L. This difference of the deposition rate results in a thickness distribution of the first blocking insulation layer113athat decrease from a left portion L to a right portion R of the substrate100. Particularly, the first blocking insulation layer113ahas the largest thickness around the corner of the left portion L. Due to the high directionality and tilting the substrate, few reaction gases for depositing the first blocking insulation layer113ahit the lower portion of the round corner of the trap insulation layer112and the tunnel insulation layer110that may be form on the lower portion of the trench106. The reaction gases, if any, do not form a deposition layer on the lower portion of the round corner of the trap insulation layer112and the tunnel insulation layer110that may be formed on the lower portion of the trench106.

After a formation of the first blocking insulation layer111a, the second step ofFIG. 11Bmay be carried out under a different arrangement of the substrate100. For example, the substrate100may be rotated at a second direction of counterclockwise. The substrate100may be also tilted leftward at a second tilt angle θ4, resulting in the highest deposition rate at a right portion R. Particularly, the second blocking insulation layer113bhas the largest thickness around the corner of the right portion R. Due to the high directionality and tilting the substrate, few reaction gases for depositing the second blocking insulation layer113bhit the lower portion of the trench106. The reaction gases, if any, do not form a layer at the lower portion of the trench106. The thickness distribution of the first and second blocking insulation layers113aand113bmay be controlled to form a uniform thickness distribution of the combined first and second trap insulation layers114on a top surface of the trap insulation layer112. The first and second trap insulation layers111aand111bmay merely be formed at the corner portions L and R and the top surface of the trap insulation layer112other than the tunnel insulation layer110that may be form on the lower portion of the trench106. As a result, the blocking insulation layer114of combined first and second blocking insulation layers113aand113bmay forms continuous layer with a recess114a.

The recess114amay be formed at a region corresponding to the gap between neighboring two trap insulation layers112. The recess114amay result from the gap between the two neighboring trap insulation layers112.

Due to the tilting of the substrate100, the deposition source gases, even though they have a high degree of directionality to the substrate100, may not be deposited on the tunnel insulation layer110that may be formed at the lower portion of the trench106. The corners L and R of the trap insulation layer114may have the highest deposition rate on the first and second trap insulation layers113aand113b, resulting in enclosing the gap between two neighboring trap insulation layers112. This enclosure may block deposition gases from arriving on the tunnel insulation layer110in the trench106, resulting in the air gap116.

Referring againFIGS. 1 and 2, a control gate layer (not illustrated) may be formed on the blocking dielectric layer114and a second mask pattern (not illustrated) may be formed on the control gate layer. The second mask pattern extends in the second direction II.

The control gate layer may be partially removed from the blocking dielectric layer114by an etching process using the second mask pattern as an etching mask, thereby forming the control gate electrode118on the blocking dielectric layer114. The control gate electrode118may include a doped polysilicon, a metal, a metal nitride, and a metal silicide. These may be used alone or in combinations thereof. In the present example embodiment, the control gate electrode118a multi-layered electrode, in which a tungsten layer may be stacked on a tungsten nitride layer.

Accordingly, the non-conformal deposition for the trap insulation layer and the blocking dielectric layer may facilitate the formation of the air gap in the trench of the device isolation region of the substrate.

FIG. 12is a cross-sectional view illustrating a charge trap non-volatile memory device according to a second example embodiment of the present inventive concept.

The charge trap non-volatile memory device of the second embodiment may have the same structure as that of the first embodiment, except for the shape of the trap insulation layer and the air gap. Thus, the tunnel insulation layer, the trap insulation layer and the blocking dielectric layer of the second embodiment may have the same materials as those in the first embodiment.

Referring toFIG. 12, the substrate100may be prepared and a device isolation region300and an active region200may be defined on the substrate100. The device isolation trench106may be prepared in the device isolation region300of the substrate100and width of the trench106may decrease with increasing depth of the trench106. The trench106may have a straight sidewall from a top to a bottom thereof and a width of the trench106may decrease with increasing depth. Thus, a corner angle between an upper surface of the active region200and the straight sidewall of the upper portion of the trench106may be larger than about 90°.

The device isolation pattern108amay be positioned at a lower portion of the trench106in such a configuration that an upper surface of the device isolation pattern108amay be lower than the upper surface of the substrate100in the active region200. The tunnel insulation layer110may be positioned on the upper surface of the active region200of the substrate100, on the upper sidewall of the trench106and on the device isolation pattern108a. That is, the tunnel insulation layer110may be conformal to the trench106on the substrate100and may not be filled up with the tunnel insulation layer110.

The trap insulation layer300of the second embodiment may be continuously arranged over the isolation region300, resulting in enclosing an air gap132between the trap insulation layer300and the tunnel insulation layer110. The air gap116may have a first side and a bottom defined by a tunnel insulation layer110on the trench and a top defined by the trap insulation layer300. The air gap132may be filled with air, which is known as having the lowest dielectric constant except vacuum. As a result, the air gap132of the isolation region300may reduce parasitic capacitance between neighboring active regions200due to the low dielectric constant.

The trap insulation layer300may have a recess300a, resulting in non-uniform thickness arising from the air gap132. The recess300aforms at a region corresponding to the center of the air gap132.

A blocking dielectric layer134may be arranged on the trap insulation layer300and may make contact with a whole surface of the trap insulation layer300. The blocking dielectric layer134may be conformal to a shape of an upper surface of the trap insulation layer300.

Hereinafter, a method of manufacturing the non-volatile memory device illustrated inFIG. 12will be described in detail with reference toFIGS. 13 to 14.

The device isolation pattern108aand the tunnel insulation layer110may be formed on the substrate100including the device isolation trench106through the same process steps as described with reference toFIGS. 3 to 7, thereby forming the structure on the substrate100as illustrated inFIG. 7.

FIG. 13shows a step of forming a trap insulation layer300on the tunnel insulation layer110by the two-consecutive deposition method using a jet deposition process. Unlike the first embodiment where the trap insulation layer112forms only on the tunnel insulation layer110on the active region200, the trap insulation layer300of the second embodiment may be formed over the insulation region200, resulting in forming the air gap132.

Like explained with reference toFIGS. 9A and 9B, the jet deposition process may form a first trap insulation layer111aand the second trap insulation layer111bon the tunnel insulation layer110of the active region200. InFIGS. 9A and 9B, the left portion L may be connected to the right portion R adjacent to the left portion L by controlling the tilt angles θ1, θ2, θ3and θ4. This merged structure of the trap insulation layer300from the first and second insulation layers111aand111bmay result in the air gap132and a recess300aat a region corresponding to the center of the air gap132.

FIG. 14show a step of form a blocking dielectric layer134on the trap insulation layer300and may be sufficiently conformal to a surface profile of the trap insulation layer300.

Thereafter, as illustrated inFIG. 12, a control gate layer may be formed on the blocking dielectric layer134and may be patterned into a control gate electrode136.

FIG. 15is a cross-sectional view illustrating a charge trap non-volatile memory device according to a third embodiment of the present inventive concept.

The charge trap non-volatile memory device of the third embodiment may have the same structure as that of the first embodiment, except for the shape of the tunnel insulation layer, the trap insulation layer and the air gap. Thus, the tunnel insulation layer, the trap insulation layer and the blocking dielectric layer of the third embodiment may have the same materials as those of the first embodiment.

Referring toFIG. 15, the substrate100may be prepared and a device isolation region300and an active region200may be defined on the substrate100. The device isolation trench106may be prepared in the device isolation region300of the substrate100and width of the trench106may decrease with increasing depth of the trench106. The trench106may have a straight sidewall from a top to a bottom thereof and a width of the trench106may decrease with increasing depth. Thus, a corner angle between an upper surface of the active region200and the straight sidewall of the upper portion of the trench106may be larger than about 90°.

The device isolation pattern108amay be positioned at a lower portion of the trench106in such a configuration that an upper surface of the device isolation pattern108amay be lower than the upper surface of the substrate100in the active region.

The tunnel insulation layer140may be formed over the insulation region200, resulting in forming the air gap142. In the first and second embodiments, the tunnel insulation layer110may be conformally formed on the substrate100,

A trap insulation layer144may be arranged on the tunnel insulation layer140and make contact with a whole surface of the tunnel insulation layer140. The trap insulation layer144may be conformal to a shape of an upper surface of the tunnel insulation layer140.

A blocking dielectric layer146may be arranged on the trap insulation layer144and may make contact with a whole surface of the trap insulation layer144. The blocking dielectric layer146may be conformal to a shape of an upper surface of the trap insulation layer144.

A control gate electrode148may be arranged on the blocking dielectric layer146. Since an upper surface of the blocking dielectric layer146may be sufficiently flat, a lower surface of the control gate electrode148may also be sufficiently flat. For example, the control gate electrode148may be shaped into a line extending in the second direction II perpendicular to the active region extending in the first direction I.

Hereinafter, a method of manufacturing the non-volatile memory device illustrated inFIG. 15will be described in detail with reference toFIGS. 16 to 17.

FIGS. 16 and 17are cross-sectional views illustrating a method of manufacturing the non-volatile memory device ofFIG. 15.

The device isolation pattern108amay be formed on the substrate100including the device isolation trench106through the same process steps as described with reference toFIGS. 3 to 6, thereby forming the structure on the substrate100as illustrated inFIG. 6.

FIG. 16shows a step of forming a tunnel insulation layer140using a two-consecutive deposition method using a jet deposition process. Unlike the first embodiment where the tunnel insulation layer110may conformally be deposited on the substrate100, the tunnel insulation layer140of the third embodiment may be deposited over the insulation region200, resulting in forming the air gap142.

The tunnel insulation layer140may be deposited by a two-consecutive deposition process using a jet deposition process similar to that used in the second embodiment. The same mechanism explained with reference toFIG. 13applies. The tunnel insulation layer140may only be deposited on the active region due to the high degree of directionality of reaction gases and the tilting of the substrate. The tunnel insulation layer140may partly be deposited on the active regions connects to one another when the tunnel insulation layer140on the active regions extends toward the insulation regions300. This merged structure of the insulation layer140may result in the air gap132and a recess140aat a region corresponding to the center of the air gap142.

FIG. 17may show a step of depositing a trap insulation layer144and a blocking insulation layer according to the third embodiment of the present inventive concept. The trap insulation layer144may be formed on the tunnel insulation layer140and may be sufficiently conformal to a surface profile of the tunnel insulation layer140. The blocking dielectric layer146may be formed on the trap insulation layer144and may be sufficiently conformal to a surface profile of the trap insulation layer144.

Thereafter, as illustrated inFIG. 15, a control gate layer may be formed on the blocking dielectric layer146and may be patterned into a control gate electrode148.

FIG. 18is a cross-sectional view illustrating a charge trap non-volatile memory device according to a fourth example embodiment of the present inventive concept.

The charge trap non-volatile memory device of the fourth embodiment may have the same structure as that of the third embodiment, except for the shape of the tunnel insulation layer and the trap insulation layer.

Referring toFIG. 18, the substrate100may be prepared and a device isolation region300and an active region area200may be defined on the substrate100. The device isolation trench106may be prepared in the device isolation region300of the substrate100and width of the trench106may decrease with increasing depth of the trench106.

The device isolation pattern108amay be positioned at a lower portion of the trench106in such a configuration that an upper surface of the device isolation pattern108amay be lower than the upper surface of the substrate100in the active region.

A tunnel insulation layer150may be positioned on the upper surface of the active region of the substrate100and on the upper sidewall of the trench106. The tunnel insulation layer150at the active region200may have a thickness different from that of the tunnel insulation layer150at the device isolation region300. The tunnel insulation layer150may be disconnected to one another at the device isolation region300of the substrate100and may extend in the first direction I in parallel with the active region200of the substrate100.

A trap insulation layer152may be continuously arranged on the tunnel insulation layer150, resulting in an air gap154and a recess152a. The air gap154may have a first side defined by sidewalls of the device isolation trench106, a bottom defined by a top surface of the device isolation pattern108a, and a top defined by the trap insulation layer300and a bottom portion of the tunnel insulation layer150. The air gap132may be filled with air, which is known as having the lowest dielectric constant except vacuum. As a result, the air gap132of the isolation region300may reduce parasitic capacitance between neighboring active regions200due to the low dielectric constant.

The trap insulation layer152may have a recess152a, resulting in non-uniform thickness arising from the air gap154. The recess152amay be formed at a region corresponding to the center of the air gap154. A blocking dielectric layer156may be arranged on the trap insulation layer152that may be conformal to a surface profile of the trap insulation layer152.

A control gate electrode158may be arranged on the blocking dielectric layer156. Since an upper surface of the blocking dielectric layer156may be sufficiently flat, a lower surface of the control gate electrode158may also be sufficiently flat. For example, the control gate electrode158may be shaped into a line extending in the second direction II perpendicular to the active region extending in the first direction I.

Hereinafter, a method of manufacturing the non-volatile memory device illustrated inFIG. 18will be described in detail with reference toFIGS. 19 to 20.

FIGS. 19 and 20are cross-sectional views illustrating a method of manufacturing the non-volatile memory device ofFIG. 18.

The device isolation pattern108amay be formed on the substrate100including the device isolation trench106through the same process steps as described with reference toFIGS. 3 to 6, thereby forming the structure on the substrate100as illustrated inFIG. 6.

FIG. 19shows a step of forming a tunnel insulation layer150using a two-consecutive deposition method using a jet deposition process. Due to the directionality of the jet deposition process and tilting the substrate at a predetermined tilt angle, the tunnel insulation layer150may be formed on the upper surface of the active region200and on the upper sidewall of the trench106. Thus, the tunnel insulation layer150may be disconnected to one another at the device isolation region300of the substrate100.

FIG. 20shows a step of forming a trap insulation layer152using a two-consecutive deposition method using a jet deposition process. Like explained with reference toFIGS. 9A and 9B, the jet deposition process may form a first trap insulation layer111aand the second trap insulation layer111bon the tunnel insulation layer110of the active region200. InFIGS. 9A and 9B, the left portion L may be connected to the right portion R adjacent to the left portion L by controlling the tilt angles θ1, θ2, θ3and θ4. This merged structure of the trap insulation layer152ofFIG. 20from the first and second insulation layers111aand111bmay result in the air gap154and a recess152aat a region corresponding to the center of the air gap154.

A blocking dielectric layer156may be formed on the trap insulation layer154and may be sufficiently conformal to a surface profile of the trap insulation layer154.

Thereafter, as illustrated inFIG. 18, a control gate layer may be formed on the blocking dielectric layer156and may be patterned into the control gate electrode158.

The above-described non-volatile memory devices may be installed to various electronic systems.

FIG. 21is a block diagram illustrating a memory system according to an embodiment of the present inventive concept. The memory system200may include a memory controller210and a non-volatile memory device220electrically connected to the memory controller210.

The memory controller210may control the operation of the non-volatile memory device220. For example, the memory controller210may include a static random access memory (SRAM) device211, a central process unit (CPU)212, a host interface213, an error correction block (ECB)214and a memory interface215.

The DRAM device211may function as an operational memory device for the CPU212. The host interface213may include a protocol for communicating data with a host center that may be positioned outside the memory system200and electrically connected to the memory system200. The ECB214may detect errors from the data read from the non-volatile memory device220and may correct the detected errors. The memory interface215may communicate data with the non-volatile memory device220. Various operations of the memory controller210may be performed by the CPU212. Although not illustrated inFIG. 21, a read-only memory (ROM) device may be further provided to the memory system200. For example, the ROM device may include a set of code data for encryption and decryption when communicating data between the exterior host center and the memory system200.

The non-volatile memory device220may include a single memory chip and a multi-chip package having a plurality of the memory chips. The memory chip may include any one of the above-described example embodiments of the non-volatile memory devices of the present invention, and thus any detailed descriptions on the memory chip will be omitted. Particularly, when a plurality of flash memory devices may be provided with the non-volatile memory device220, the memory system200may be used as a storage system such as a solid state disk (SSD). In such a case, the memory controller210may communicate data with exterior host center via various protocol interfaces such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI and IDE. In addition, the memory controller210for the SSD may further include a random operator for random arithmetic calculations.

FIG. 22is a schematic block diagram illustrating a computing system including the memory system ofFIG. 21according to an embodiment of the present inventive concept. The computing system300may include a memory system310, a microprocessor320electrically connected to a system bus360, a random access memory (RAM) unit330, a user interface340and a MODEM350such as a baseband chipset. The memory system310may have the same structure as the memory system200ofFIG. 21. The computing system300may be provided as a mobile system and a battery may be further installed to the mobile computing system. In addition, the mobile computing system may further include an application chipset, a camera image processor (CIS) and a mobile DRAM.

The memory system310may include a single memory chip and a multi-chip package having a plurality of the memory chips. The memory chip may include any one of the above-described example embodiments of the non-volatile memory devices of the present invention.

According to the embodiments of the present inventive concept, signal interference between neighboring memory cells may be minimized in the non-volatile memory device, thereby minimizing operational failures of the memory device due to the interference. In addition, this interference immunity may increase integration density of a non-volatile memory.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Those skilled in the art will readily appreciate that many modifications and alternative forms are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications and alternative forms are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.