CHARGER

A charger includes: a rectifier including input terminals, a cathode terminal and an anode terminal, wherein the input terminals are configured for connection to an AC power supply; a DC/DC converter including a first terminal, a second terminal and output terminals, the first terminal being configured to be connected to the cathode terminal of the rectifier, the second terminal being configured to be connected to the anode terminal of the rectifier, wherein the output terminals are configured for connection to a battery; and a power pulsation absorbing circuit including a first to third diodes, an inductor, a capacitor, a first switch and a second switch, wherein the DC/DC converter, the first and second switch are controlled to obtain a constant sum of a power outputted from the AC power supply and a power outputted from the capacitor during increasing a voltage outputted from the AC power supply.

BACKGROUND OF THE INVENTION

Technical Field

The present invention relates to a charger.

Background Art

Various isolated single phase AC/DC converters have been considered as chargers for electric vehicles. Generally, a circuit arrangement is utilized as a charger for an electric vehicle, wherein the circuit arrangement includes a diode rectifier with a power factor correction (PFC) circuit, a high capacitance capacitor for a DC link, and high frequency isolated DC/DC converter. The high capacity capacitor for a DC link is required to have a capacitance which enables power pulsation due to a single-phase AC power supply to be absorbed. With the above-mentioned circuit arrangement, it is difficult to reduce a size of the capacitor.

As a compact charger which enables power pulsation to be absorbed, Non-Patent Document 1 discloses a charging circuit including a Dual-Active-Bridge (DAB) converter with an active buffer added, and control of such a charging circuit, the active buffer being intended for power pulsation absorption.

CITATION LIST

Non-Patent Document 1; Shohei Komeda, Yoshiya Ohnuma, “A Dual Active Bridge AC-DC Converter with an Active Energy Buffer”, Material of the Technical Committee on Semiconductor Power Converter, 2021, SPC-21-003, pp. 13-18

SUMMARY OF THE INVENTION

However, the control according to Non-Patent Document 1 is applicable to voltage decrease operation, but may not be applicable to voltage increase operation.

An objective of the present invention is to provide a compact charger which enables pulsation of power to be absorbed.

In order to achieve the objective, a charger according to the present invention includes a rectifier including two input terminals, a cathode terminal and an anode terminal, wherein the two input terminals are configured for connection to an AC power supply; a DC/DC converter including a first terminal, a second terminal and two output terminals, the first terminal being configured to be connected to the cathode terminal of the rectifier via a first line, the second terminal being configured to be connected to the anode terminal of the rectifier via a second line, wherein the output terminals are configured for connection to a battery; a power pulsation absorbing circuit including a first diode, a second diode, a third diode, an inductor, a capacitor, a first switch and a second switch; and a controller configured to control switching of a switch of the DC/DC converter and switching of the first switch and the second switch; wherein the first diode is connected between the inductor of the power pulsation absorbing circuit and one of the two input terminals of the rectifier, and the second diode is connected between the inductor and another of the two input terminals of the rectifier, wherein the capacitor and the first switch are connected in series between the first line and the second line with the capacitor being arranged closer to the second line than the first switch, wherein the third diode is connected between the inductor of the power pulsation absorbing circuit and a line which connects the capacitor to the first switch, wherein the second switch is connected between the second line and a line which connects the inductor of the power pulsation absorbing circuit to the third diode, wherein the controller is configured to control the switch of the DC/DC converter, the first switch and the second switch to obtain a constant sum of a power outputted from the AC power supply and a power outputted from the capacitor during increasing a voltage outputted from the AC power supply.

The present invention enables a compact charger to be provided which can absorb pulsation of power.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG.1shows a charger100according to an embodiment of the present invention. The charger100includes a rectifier110, a DC/DC converter120, a power pulsation absorbing circuit130, and a controller140. The charger100converts the single-phase AC voltage vSinputted from the single-phase AC power supply200to a DC voltage Vdc, and outputs it to a battery300.

The rectifier110includes a cathode terminal111and an anode terminal112connected to DC/DC converter120, and two input terminals113for connection to the AC power supply200. For example, the rectifier110is configured as a bridge diode rectifier formed by four diodes, receives an AC current applied between the two input terminals113connected to the AC power supply, converts the current into a DC current and outputs it from the cathode terminal111, as shown inFIG.1. As shown inFIG.1, the rectifier110may be configured to be connected to the AC power supply200via a filter F, wherein the filter F includes an inductor Lac and a capacitor Cac.

For example, the DC/DC converter120is configured as a DAB (Dual Active Bridge) converter. The DC/DC converter120includes a first terminal121, a second terminal122, a third terminal123and a fourth terminal124, the first terminal121being connected to the cathode terminal111of the rectifier110, the second terminal122being connected to the anode terminal112of the rectifier110, wherein the third and fourth terminals123and124are configured for connection to a positive electrode and a negative electrode of the battery300, respectively. The DC/DC converter120includes a transformer Tr as well as four switches on an input side (primary side), i.e., a first switch S21, a second switch S22, a third switch S23and a fourth switch S24, and four switches on an output side (secondary side), i.e., a fifth switch S25, a sixth switch S26, a seventh switch S27and an eighth switch S28, wherein the transformer Tr is arranged between the four switches on the input side and the four switches on the output side. For example, each of the eight switches S21˜S28is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, the N-channel power MOSFET may include a snubber capacitor, as shown inFIG.1.

The DC/DC converter120includes an inductor L on the primary side of the transformer Tr. This inductor L is, for example, a leakage inductor of the transformer Tr.

Further, a DC capacitor Cdc is connected between the third terminal123and the fourth terminal124of DC/DC converter120. An inductor Ldc may be connected between the third terminal123of the DC/DC converter120and the positive electrode of the battery300.

The power pulsation absorbing circuit130includes a first diode D31, a second diode D32, a third diode D33, an inductor Lb, a buffer capacitor Cbuf, a first switch S31, and a second switch S32.

The first diode D31of power pulsation absorbing circuit130is connected between the inductor Lb of the power pulsation absorbing circuit130and one of the two input terminal113of the rectifier110. The second diode D32of power pulsation absorbing circuit130is connected between the inductor Lb of the power pulsation absorbing circuit130and the other of the two input terminal113of the rectifier110. In this case, each of the first diode D31and second diode D32of the power pulsation absorbing circuit130is connected between the inductor Lb of the power pulsation absorbing circuit130and the input terminals113of the rectifier110so that these diodes have a forward direction extending from the input terminals113of the rectifier110to the inductor Lb. Therefore, even when the AC power supply200is connected to the input terminals113of the rectifier110, a DC current is applied to the inductor Lb of power pulsation absorbing circuit130.

The buffer capacitor Cbuf of the power pulsation absorbing circuit130and the first switch S31are connected in series between a first line LH and a second line LL, wherein the first line LH connects the cathode terminal111of the rectifier110to the first terminal121of the DC/DC converter120, and the second line LL connects the anode terminal112of the rectifier110to the second terminal122of the DC/DC converter120. The buffer capacitor Cbuf is arranged closer to the second line LL, and the first switch31is arranged closer to the first line LH. The first switch S31is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, a source and a drain of the N-channel power MOSFET may be preferably connected to the first line LH and the buffer capacitor, respectively.

The third diode D33of the power pulsation absorbing circuit130is connected between line connecting the buffer capacitor Cbuf of the power pulsation absorbing circuit130to the first switch S31on the one hand and the inductor Lb of the power pulsation absorbing circuit130on the other hand so that the third diode D33has a forward direction along a direction extending from the inductor Lb to this line.

The second switch S32of the power pulsation absorbing circuit130is connected between the second line LL and a line connecting the inductor Lb of the power pulsation absorbing circuit130to the third diode D33. The second switch S32is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, a drain of the N-channel power MOSFET may be preferably connected to the line connecting the inductor Lb of the power pulsation absorbing circuit130to the third diode D33, wherein a source of the N-channel power MOSFET may be preferably connected to the second line LL.

The controller140controls switching of the switches S21to S28of the DC/DC converter120as well as switching of the switches S31and S32of the power pulsation absorbing circuit130.

Since the power pulsation absorbing circuit130includes a first diode D31, a second diode D32, a third diode D33, an inductor Lb, a buffer capacitor Cbuf, a first switch S31, and a second switch S32, the power pulsation absorbing circuit130may serve as a power factor correction (PFC) circuit. Therefore, according to the present embodiment, control is possible which provides the following sinusoidal voltage vSand sinusoidal current is to the charger100from the AC power supply200:

iS(t)=√{square root over (2)}ISsin ωStwherein VSindicates an effective value of the power supply voltage and ISindicates an effective value of the power supply current.

In this case, an instantaneous power pSoutputted from the AC power supply200is formed by a sum of an average power P (=VSIS) and a pulsation component prip(t) (=−VSIScos 2ωSt) as shown below, wherein the instantaneous power pSpulsates around the average power P (dashed line inFIG.2) with an angular frequency which is twice as high as an angular frequency ω of the AC, as shown with a solid line inFIG.2.

For the above-mentioned reasons, the controller140controls switching of the switches S21to S28of the DC/DC converter120as well as switching of the switches S31and S32of the power pulsation absorbing circuit130to absorb power pulsation due to the AC power supply in the power pulsation absorbing circuit130so that a constant power is inputted to the DC/DC converter120.

In this case, the charger100according to the present embodiment is provided such that different controls are applied for the instantaneous power from the AC power supply200being higher than the average power (pS>P) and for the instantaneous power being lower than the average power (pS<P).

In the case of the instantaneous power pSfrom the AC power supply being higher than the average power P (pS>P), switching of the eight switches S21to S28of the DC/DC converter120and the two switches S31and S32of the power pulsation absorbing circuit130are controlled to charge the pulsation component pripof the instantaneous power pSfrom the AC power supply200to the buffer capacitor Cbuf via the inductor Lb of the power pulsation absorbing circuit130, whereby only the average power P of the power outputted from the AC power supply may be provided to the DC/DC converter120. This means that according to the present embodiment, the buffer capacitor Cbuf is charged in a phase in which a higher instantaneous power pSthan the average power P is outputted from the AC power supply (charging phase), wherein a negative instantaneous power pCis outputted from the buffer capacitor Cbuf, as shown with a dashed dotted line inFIG.2.

On the other hand, in the case of the instantaneous power pSfrom the AC power supply200being lower than the average power P (pS<P), switching of the eight switches S21to S28of the DC/DC converter120and the first switch S31of the power pulsation absorbing circuit130are controlled while maintaining the second switch S32of the power pulsation absorbing circuit130in an off-state to actively discharge the buffer capacitor Cbuf via the first switch S31. This compensates the pulsation component prip, i.e., a difference between the instantaneous power pSand the average power P outputted from the AC power supply200to input the average power P to the DC/DC converter120. This means that according to the present embodiment, the buffer capacitor Cbuf is discharged in a phase in which a lower instantaneous power pSthan the average power P is outputted from the AC power supply (discharging phase), wherein a positive instantaneous power pCis outputted from the buffer capacitor Cbuf, as shown with a dashed dotted line inFIG.2.

In other words, according to the present embodiment, the controller140controls switching of the switches S21to S28of the DC/DC converter120, the switches S31and S32of the power pulsation absorbing circuit130to obtain a constant sum of the instantaneous power pSoutputted from the AC power supply200and the instantaneous power pCoutputted from the buffer capacitor Cbuf.

In this manner, the present embodiment is provided such that the buffer capacitor Cbuf is actively discharged during the discharging phase. Consequently, the present embodiment enables an amount of power accumulated in the buffer capacitor Cbuf (i.e., capacitance of the buffer capacitor Cbuf) to be limited, whereby the buffer capacitor Cbuf can be reduced in size.

Further, according to the present embodiment, the second switch S32is activated only during the charging phase. Consequently, the present embodiment enables an amount of power accumulated in the inductor Lb (i.e., inductance of the inductor Lb) to be limited, whereby the inductor Lb can be reduced in size.

Further, according to the present embodiment, a power without pulsation is inputted to the DC/DC converter120. Consequently, the present embodiment enables the transformer Tr of the DC/DC converter120and/or the DC capacitor Cdc to be reduced in size.

In this manner, the present embodiment enables passive elements to be reduced in size, for example capacitors and inductors. Consequently, the present embodiment enables a compact charger to be provided which can absorb pulsation of power.

Switching Modes and Operation Waveform

The controller140controls switching of the switches S21to S28of the DC/DC converter120and the first switch S31of the power pulsation absorbing circuit130according to seven modes to obtain an operation waveform iLof the inductor L of the DC/DC converter120which is approximable by a rectangular waveform.FIG.3shows respective states of each of switches in the seven modes. The seven modes a mode (mode 5) in which the switches S21to S28of the DC/DC converter120and the first switch S31of the power pulsation absorbing circuit130are all switched off.

FIG.4shows an operation waveform iLof an inductor L of a DC/DC converter120according to the present embodiment and a corresponding equivalent rectangular waveform iL′. This operation waveform iLis obtained by switching the seven modes as shown inFIG.3to mode 1, mode 2, mode 3, mode 4, mode 5, mode 4, mode 6, mode 7, mode 1 and mode 5 in this order. In this case, a current iLis obtained in each of the seven modes as follows (see Non-Patent Document 1)

iL(t)={vC+VdcL⁢(t-tc⁢1)+iL(tc⁢1)(Mode⁢1)vC+VdcL⁢(t-tc⁢2)+iL⁢(tc⁢2)(Mode⁢2)vrec+VdcL⁢(t-tc⁢3)+iL⁢(tc⁢3)(Mode⁢3)-vC+VdcL⁢(t-tc⁢4)+iL(tc⁢4)(Mode⁢4)0(Mode⁢5)-vrec+VdcL⁢(t-tc⁢6)+iL(tc⁢6)(Mode⁢6)-vC+VdcL⁢(t-tc⁢7)+iL⁢(tc⁢7)(Mode⁢7)wherein tcn(n=1 to 7) indicates a time at which switching to mode n is performed.

According to the present embodiment, in order to discharge the buffer capacitor Cbuf more actively when the first switch S31of the power pulsation absorbing circuit130is in an on-state, the controller140controls a voltage vCapplied to the buffer capacitor Cbuf such that the voltage vCis always higher than an instantaneous voltage vrecoutputted from the rectifier110. Therefore, according to the present embodiment, the voltage vCapplied to the buffer capacitor Cbuf has a value which is different from the instantaneous voltage vrecof the rectifier110, and modes 2 and 3 have different gradients of the operation waveform iL. Similarly, modes 6 and 7 have different gradients of the operation waveform iL. In this manner, the present embodiment enables operation waveforms to be generated which are asymmetrical with respect to iL=0 in positive and negative waveforms, as shown inFIG.4.

For the operation waveform iLas shown inFIG.4, it is possible to approximate it by an equivalent rectangular waveform iL′ if t0to t10are set such that |t0−t1|=|t5−t6|, |t1−t2|=|t7−t8|, |t2−t3|=|t6−t7|, |t3−t4|=|t8−t9|, and if tS1and tS2are set between t3and t4and between t8and t9respectively such that |t0−t1|=|tS1−t4|=|tS2−t9|.

If phases from t0to t1, from tS1to t4, from t5to t6, and from tS2to t9of the equivalent rectangular waveform iL′ are defined as reactive current phases Tq, phases from t1to t2and from t7to t8are defined as buffer capacitor discharge current phases TC, phases from t2to t3and from t6to t1are defined as power supply current phases Trec, phases from t3to tS1and from t8to tS2are defined as current balance phases Tb, and phases from t4to t5and from t9to t10are defined as zero current phases T0, a duty cycle for each of the phases within a switching period TSWis as follows:

{Dq=2⁢TqTSW=2⁢IL′⁢L(vC+Vdc)⁢TSW-Db2DC=2⁢TCTSW=iCIL′+Db=(vr⁢e⁢c-Vdc)⁢ir⁢e⁢c+(vC+Vdc)⁢iC2⁢Vdc⁢IL′Drec=2⁢Tr⁢e⁢cTSW=ir⁢e⁢cIL′Db=2⁢TbTSW=(vr⁢e⁢c-Vdc)⁢ir⁢e⁢c+(vC+Vdc)⁢iC2⁢Vdc⁢IL′D0=2⁢T0TSW=1-(2⁢Dq+DC+Dr⁢e⁢c+Db)(1)The duty cycle of each of the phases can be obtained by giving irec, iC, vCand VdcIL′ as set values. The obtained duty cycles of phases may be used to determine a control rule for the operation waveform iLinFIG.4. Among these set values, set values irec* and iC* for irecand iCare switched as follows for the discharging phase and charging phase, wherein the power pulsation absorbing circuit130is operated to function as a PFC circuit and as a circuit for absorbing power pulsation:

Switching Control during Voltage Increase Operation

In order to operate the charger100by performing the above-described control, all the duty cycles in the above formulas (1) should be positive. During voltage decrease operation (i.e., VS≥Vdc), all the duty cycles in the formulas (1) are positive. However, during voltage increase operation (i.e., VS<Vdc), the duty cycle Dbin the current balance phase Tband the duty cycle DCin the buffer capacitor discharge current phase TCmay be negative, as shown inFIG.5. In the example as shown inFIG.5, both of the duty cycle Dbin the current balance phase Tband the duty cycle DCin the buffer capacitor discharge current phase TCare positive at a phase ωSt of 0 degree of the AC power supply voltage vS. However, at the phase ωSt of approximately 15 degrees of the AC power supply voltage vS, the duty cycle Dbin the current balance phase Tbis negative, and at the phase ωSt of approximately 45 degrees of the AC power supply voltage vS, the duty cycle DCin the buffer capacitor discharge current phase TCis negative. When the duty cycle Dbin the current balance phase Tbis negative, the following is obtained according to the formula (1)

(vrec−Vdc)irec+(vC−Vdc)iC<0  (2)And when the duty cycle DCin the buffer capacitor discharge current phase TCis negative, the following is obtained according to the formula (1):

Therefore, according to the present embodiment, a different switching control is applied in the case of the duty cycle Dbin the current balance phase Tbbeing negative (i.e., the above formula (2) is fulfilled), and in the case of the duty cycle DCin the buffer capacitor discharge current phase TCbeing negative (i.e., the above formula (3) is fulfilled), a further different switching control is applied. Hereinafter, the control in the case of both formulas (2) and (3) being not fulfilled, i.e., the control as described above, shall be referred to as “voltage decrease sequence”, the control in the case where formula (2) is fulfilled and formula (3) is not fulfilled shall be referred to as “voltage increase sequence I”, and the control in the case of both formulas (2) and (3) being fulfilled shall be referred to as “voltage increase sequence II”.

Voltage Increase Sequence I

In the operation waveform iLas shown inFIG.4, iL(t1)≤iL(t3). However, when the duty cycle Dbin the current balance phase Tbis negative (i.e., the above formula (2) is fulfilled), this results in iL(t1)≥iL(t3) in the operation waveform iL, as shown inFIG.6. Therefore, according to the present embodiment, in the case where formula (2) is fulfilled and formula (3) is not fulfilled, t0to t10are set such that |t0−t1|=|t5−t6|, |t1−t2|=|t7−t8|, |t2−t3|=|t6−t7|, |t3−t4|=|t8−t9|, and tS1and tS2are set between t0and t1and between t5and t6respectively such that |t0−tS1|=|t3−t4|=|t5−tS2|, and the operation waveform iLis then approximated by the following equivalent rectangular waveform iL′:

If phases from t0 to tS1, from t3to t4, from t5to tS2, and from t8to t9of the equivalent rectangular waveform iL′ are defined as reactive current phases Tq, phases from t1to t2and from t7to t8are defined as buffer capacitor discharge current phases TC, phases from t2to t3and from t6to t7are defined as power supply current phases Trec, phases from tS1to t1and from tS2to t6are defined as current balance phases Tb, and phases from t4to t5and from t10to t10are defined as zero current phases T0, a duty cycle for each of the phases within a switching period TSWis as follows:

{Dq=2⁢IL′⁢L(vC+Vdc)⁢TSW-Db2DC=iCIL′-Db=(vr⁢e⁢c-Vdc)⁢ir⁢e⁢c+(vC+Vdc)⁢iC2⁢Vdc⁢IL′Drec=ir⁢e⁢cIL′Db=-(vr⁢e⁢c-Vdc)⁢ir⁢e⁢c+(vC+Vdc)⁢iC2⁢Vdc⁢IL′D0=1-(2⁢Dq+DC+Dr⁢e⁢c+Db)(4)Similarly, in the voltage increase sequence I, the duty cycle of each of the phases can be obtained by giving irec, iC, vCand VdcIL′ as set values. The obtained duty cycles of phases may be used to determine a control rule for the operation waveform iLinFIG.6.

Voltage Increase Sequence II

Further, according to the present embodiment, in the case of both formulas (2) and (3) being fulfilled, switching of the switches S21to S28of the DC/DC converter120and the first switch S31of the power pulsation absorbing circuit130is controlled according to nine modes as shown inFIG.7which include two modes in addition to the seven modes as shown inFIG.3. Such control results in an operation waveform iLas shown inFIG.8. The operation waveform iLas shown inFIG.8is obtained by switching the nine modes as shown inFIG.7to mode 1, mode 8, mode 2, mode 3, mode 4, mode 5, mode 4, mode 9, mode 6, mode 7, mode 1 and mode 5 in this order.

Then, for the operation waveform iLas shown inFIG.8, it is possible to approximate it by an equivalent rectangular waveform iL′ if t0to t12are set such that |t0−t1|=|t6−t7|=, |t1−t2|=|t7−t8|=, |t2−t3|=|t9−t10|=, |t3−t4|=|t8−t9|=, |t4−t5|=|t10−t11| and |t5−t6|=|t11−t12|.

If phases from t0to t1,from t4to t5,from t6to t7,and from t10to t11of the equivalent rectangular waveform iL′ are defined as reactive current phases Tq, phases from t2to t3and from t9to t10are defined as buffer capacitor discharge current phases TC, phases from t3to t4and from t8to t9are defined as power supply current phases Trec, phases from t1to t2and from t7to t8are defined as current balance phases Tb, and phases from t5to t6and from t11to t12are defined as zero current phases T0, a duty cycle for each of the phases within a switching period TSWis as follows:

Operation of the Charger100

FIG.9shows duty cycles in the case of operating the charger100by using three controls, i.e., the voltage decrease sequence, voltage increase sequence I and voltage increase sequence II. As shown inFIG.9, it is possible to operate the charger100also during the voltage increase operation by changing the switching control into voltage decrease sequence, voltage increase sequence I, voltage increase sequence II, voltage decrease sequence, voltage increase sequence II and voltage increase sequence I in this order.

Control of Switching Frequency fSW

The zero current phase T0is mode 5, wherein in this phase, all the switches S21to S28of DC/DC converter120are switched off. However, the switches are practically switched off at times which are offset, wherein this offset causes residual current and thus resonance between the inductor L of the DC/DC converter120and parasitic capacitances of the switches S21to S28. Therefore, switching after the zero current phase T0(switching in a changing process from mode 5 to mode 4, switching in a changing process from mode 5 to mode 1) will becomes hard switching, which results in switching loss.

Therefore, a method has been proposed in which switching frequencies fSWof switching of the switches S21to S28of the DC/DC converter120and/or of the switch S31of the power pulsation absorbing circuit130are changed within one period of the AC voltage vSinputted from the AC power supply200so that no zero current phase T0exists, whereby oscillation of a current iLand a voltage VLof the inductor L is removed and hard switching is avoided after the zero current phase T0to control the charger100more efficiently (Shohei Komeda, Shunsuke Takuma and Yoshiya Ohnuma “A Variable Frequency Control Method for a Dual-Active-Bridge AC-DC Converter with an Active Energy Buffer”, lecture papers collection of 2021 IEE-Japan Industry Applications Society Conference, Vol. 1, No. 30, pp. 13-18 (2021)).

Similarly in the present embodiment, for example, the controller140may control values of switching frequencies fSWof switching of the switches S21to S28of the DC/DC converter120and/or of the switch S31of the power pulsation absorbing circuit130so that no zero current phase T0exists. By solving the above equations (1), (4) and (5) with D0=0, the switching frequency fSWwith which no zero current phase T0exists is obtained as follows.

fS⁢W=vC+Vdc4⁢IL′⁢L⁢(1-Dr⁢e⁢c-DC)(6)fSW=vC+Vdc4⁢IL′⁢L⁢(1-Dr⁢e⁢c-DC⁢vC-vrecvC+Vdc⁢Db)(7)Equation (6) as above corresponds to switching frequencies fSWfor the voltage decrease sequence and voltage increase sequence I, while equation (7) as above corresponds to a switching frequency fSWfor the voltage increase sequence II.

Set Value for Peak Value IL′ of the Equivalent Rectangular Wave iL′

In the above-mentioned document (see Shohei Komeda, Shunsuke Takuma and Yoshiya Ohnuma “A Variable Frequency Control Method for a Dual-Active-Bridge AC-DC Converter with an Active Energy Buffer”, lecture papers collection of 2021 IEE-Japan Industry Applications Society Conference, Vol. 1, No. 30, pp. 13-18 (2021)), a method has been also proposed in which a set value for a peak value IL′ of the equivalent rectangular wave iL′ in a voltage decrease sequence according to the prior art is optimized to operate the charger100more efficiently. In this method, the set value of the peak value IL′ of the equivalent rectangular waveform iL′ is controlled to obtain a predetermined value fminof the switching frequency fSW(equation (6) as mentioned above) at a phase ωSt of 45 degrees of AC power supply voltage vSso that the charger100is operated more efficiently.

However, during the voltage increase operation, at the phase ωSt of 45 degrees of AC power supply voltage vS, the charger100may be not operated with the voltage decrease sequence according to the prior art, but with the voltage increase sequence II, as shown inFIG.9. In this case, it is not possible to use the method proposed in the above document directly. Therefore, in such a case, for example the set value of the peak value IL′ of the equivalent rectangular waveform iL′ is preferably controlled at the phase ωSt of 45 degrees of AC power supply voltage vSto obtain a predetermined value fminof the switching frequency fSWin the voltage increase sequence II (equation (7) as mentioned above). In this case, the set value IL′* of the peak value IL′ of the equivalent rectangular waveform iL′ is as follows:

The above formula (8) is effective in the case where the switching frequency fSWin the voltage increase sequence II (equation (7) as mentioned above) is minimum at the phase ωSt of 45 degrees of AC power supply voltage vS. When a maximum value of the voltage vCapplied to the buffer capacitor Cbuf is set to a sufficiently high value, the switching frequency fSWin the voltage increase sequence II (equation (7) as mentioned above) is minimum at the phase ωSt of 45 degrees of AC power supply voltage vS. On the other hand, when the maximum value of the voltage vCapplied to the buffer capacitor Cbuf is reduced, the switching frequency fSWin the voltage increase sequence II (equation (7) as mentioned above) may be minimum at a phase ωSt AC power supply voltage vSwhich is different from 45 degrees. In such a case, a set value of the peak value IL′ of the equivalent rectangular waveform may be preferably determined with which a minimum value of the switching frequency fSWin the voltage increase sequence II (equation (7) as mentioned above) is adjusted to the predetermined value fmin.

The present invention has been described above by means of the preferable embodiment thereof. Although the invention has been described herein by presenting a specific example, various modifications and changes may be made to such an example without departing from the spirit and scope of the invention as set forth in the claims.

REFERENCE SIGNS LIST