Temperature compensation circuit and semiconductor integrated circuit using the same

The disclosure provides a temperature compensation circuit that generates a temperature-compensated current and an integrated semiconductor circuit using the temperature compensation circuit. The temperature compensation circuit includes: a first PTAT current source which has a first emitter area ratio and generates a first current, the first current having a first temperature coefficient proportional to the absolute temperature; a second PTAT current source which has a second emitter area ratio and generates a second current, the second current having a second temperature coefficient proportional to the absolute temperature; an adjustment circuit which adjusts the current generated by the first PTAT current source; and a differential circuit which outputs the difference between the current adjusted by the adjustment circuit and the current generated by the second PTAT current source.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Japan application serial no. 2021-149138, filed on Sep. 14, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The present disclosure relates to a temperature compensation circuit that generates temperature-compensated current, particularly a temperature compensation circuit with two proportional-to-absolute-temperature (PTAT) current sources.

Description of Related Art

A temperature-compensated voltage corresponding to the operating temperature is generally generated in a semiconductor device, such as a memory or a logic circuit. The temperature-compensated voltage ensures the reliability of the circuit by keeping the circuit operating. When data is read, if the read current flow decreases due to temperature changes in the memory circuit, then the read tolerance would decrease, preventing data from being read accurately. For example, Patent Document 1 (Japanese Patent Laid-Open No. 2021-82094) discloses a voltage generating circuit that compares a reference voltage VREF and a temperature-dependent voltage VPTAT, and selects one of the reference voltage VREF and the temperature-dependent voltage VPTAT based on the comparison result to generate a highly reliable voltage.

Temperature coefficient (Tco) of a constant current circuit or a constant current source is often a problem in the analog circuit design. For example, as an oscillator includes a delay circuit to determine the period (cycle) of oscillation, a constant current circuit is sometimes adapted as the delay circuit to avoid voltage dependence of the delay time due to fluctuations in the power supply voltage, but the temperature coefficient of the constant current circuit varies in the delay time with respect to the temperature, affecting the period of the oscillator by the temperature.

SUMMARY

The temperature compensation circuit of the disclosure includes: a first circuit employing transistors with a first emitter area ratio or diodes with a number ratio equivalent to the first emitter area ratio to generate a first current having a first temperature coefficient proportional to the absolute temperature; a second circuit employing transistors with a second emitter area ratio or diodes with a number ratio equivalent to the second emitter area ratio to generate a second current having a second temperature coefficient proportional to the absolute temperature; and a differential circuit configured to output a differential current of the first current and the second current.

The semiconductor integrated circuit of the disclosure includes: the temperature compensation circuit described above; and a voltage generation circuit configured to generate a voltage based on the differential current output by the temperature compensation circuit.

According to the disclosure, a high-precision, temperature-compensated current is obtained by generating a difference of currents having different temperature coefficients proportional to the absolute temperature.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the disclosure are described in detail with reference to the drawings. The temperature compensation circuit of the disclosure may be used in semiconductor integrated circuits, such as a voltage generation circuit for generating a reference voltage, an oscillation circuit, and other logic circuits.

FIG.1is a diagram showing the configuration of a general PTAT current source. The PTAT current source10includes a current mirror circuit20that supplies a current I1and a current I2to a first current path and a second current path, an NPN bipolar transistor Q1connected to the first current path, and an NPN bipolar transistor Q2connected to the second current path, and a resistor R connected between the transistor Q2and the ground (GND). The output current I1is made equal to the current I2to control the current mirror circuit20. In addition, the emitter area ratio of the diode-connected transistor Q1to the transistor Q2is 1:n (n is the emitter area ratio), and the current density of the transistor Q1is n times that of the transistor Q2.

FIG.2is a graph showing the relationship between the current I1(=I2) flowing in the PTAT current source shown inFIG.1and the temperature. The vertical axis represents the current (uA), and the horizontal axis represents the temperature. In addition, the graph shows the relationship between the current and the temperature when the emitter area ratio n is 1:2, 1:4, and 1:8. The current I1has a positive temperature coefficient with respect to the absolute temperature, and the magnitude of the current is substantially proportional to the emitter area ratio n. However, when the emitter area ratio is different, the temperature coefficient is also slightly different, such that the ratios are approximate and not exactly proportional. Table 1 shows the relationship between the emitter area ratio and the temperature coefficient in the temperature range of −45° C. to 52.5° C. of the graph inFIG.2. As the emitter area ratio increases, the temperature coefficient decreases.

In this embodiment, two PTAT current sources are adapted to generate a temperature-compensated current by the difference of the two currents. As described above, when the emitter area ratio is different, the temperature coefficients of the two are also slightly different, but with the difference between the two currents, it is possible to find that the current hardly changes with respect to temperature. In an embodiment, the magnitude of the current of one or both of the two PTAT current sources can be adjusted proportionally, such that the temperature coefficient of the differential current is close to zero, so as to generate a high-precision, temperature-compensated current.

Next, the temperature compensation circuit of the present embodiment is described in detail.FIG.3is a diagram showing a configuration of a temperature compensation circuit according to an embodiment of the disclosure. The temperature compensation circuit100of this embodiment includes a first PTAT current source110, a second PTAT current source120, an adjustment circuit130, and a differential circuit140. The first PTAT current source110generates a current IAwith a temperature coefficient proportional to the absolute temperature. The second PTAT current source120generates a current IBwith a temperature coefficient proportional to the absolute temperature. The adjustment circuit130adjusts the magnitude of the current IAgenerated by the first PTAT current source110to be K times to generate the adjusted current KIA. The differential circuit140outputs the difference between the adjusted current KIAand the current IBgenerated by the second PTAT current source120.

The first PTAT current source110includes a first current path and a second current path between the supply voltage VDD and the GND. A PMOS transistor P1and an NPN bipolar transistor Q1are connected in series on the first current path. The PMOS transistor P2, the NPN bipolar transistor Q2, and the resistor RAare connected in series on the second current path. The transistor P1and the transistor P2form a current mirror with a mirror ratio of 1 (m=1), and function as a current source for flowing a current IAto each of the first current path and the second current path. In the bipolar transistor Q1and the bipolar transistor Q2, the respective bases are commonly connected to the first current path, performing a diode connection, and the emitter area ratio n of the bipolar transistor Q1and the bipolar transistor Q2is, for example, 1:2. The resistor RAis not particularly defined and is composed of, for example, a resistor having a positive temperature characteristic or a resistor made of a semiconductor material having a negative temperature characteristic.

Similar to the first PTAT current source110, the second PTAT current source120includes a first current path and a second current path between the supply voltage VDD and the supply voltage GND. A PMOS transistor P3and an NPN bipolar transistor Q3are connected in series on the first current path. The PMOS transistor P4, the NPN bipolar transistor Q4, and the resistor RBare connected in series on the second current path. The transistor P3and the transistor P4form a current mirror with a mirror ratio of 1 (m=1), and function as a current source for flowing a current IBto the first current path and the second current path. In the bipolar transistor Q3and the bipolar transistor Q4, the respective bases are commonly connected to the first current path, performing a diode connection, and the emitter area ratio n of the transistor Q3and the transistor Q4is, for example, 1:4. The resistor RBis configured to have the same resistance value as resistor RA(RB=RA).

The adjustment circuit130adjusts the magnitude of the current IAgenerated by the first PTAT current source110. In this example, the adjustment circuit130includes a PMOS transistor P5that forms a current mirror with the PMOS transistor P1and the PMOS transistor P2to adjust a mirror ratio K (m=K; K is a value greater than 1) of the transistor P5. The adjustment scheme of the mirror ratio K is not particularly defined. The adjustment circuit130includes, for example, logic for adjusting the mirror ratio K based on a trim code (TRC) supplied externally or a trim code TRC stored in advance in a storage unit, such as a memory. For example, as shown inFIG.4A, the adjustment circuit130includes a plurality of transistors P51to P5nin which n number of transistors P5are connected in parallel, and switches SW1to SWn are connected in series to these transistors. The witches SW1to SWn are selectively turned on and off according to the trim code TRC. As a result, the sum of the drain currents of the transistors conducted becomes the adjusted current KIA. As such, a mirror current K×IAthat is K times the current IAis generated at the drain of the transistor P5.

The differential circuit140includes a first current path and a second current path between the supply voltage VDD and the supply voltage GND. The first current path includes an NMOS transistor N1connected in series with the transistor P5of the adjustment circuit130. The current KIAfrom the transistor P5is supplied to the first current path. The second current path includes: a PMOS transistor P6that forms a current mirror with the transistor P3and the transistor P4of the second PTAT current source and has a mirror ratio of 1 (m=1); and an NMOS transistor N2connected in series to the PMOS transistor P6. The current IBfrom the transistor P6is supplied to the second current path. In the transistor N1and the transistor N2, the respective gates are commonly connected to the first current path to form a current mirror circuit. As such, the differential current Idiff (IB−KIA) of the current IBand the current KIAis output externally from a connection node Q of the transistor P6and the transistor N2.

The current IAis approximately IB/2 according to the emitter area ratio of the NPN bipolar transistor, but the temperature coefficient (Tco) of the current IAis larger than the temperature coefficient (Tco) of the current IB. If the mirror ratio K of the adjustment circuit130is selected in a way that the temperature gradient of the current KIAwith respect to the absolute temperature is approximately the same as that of the current IB, the temperature dependence of the differential current Idiff may be brought close to zero.

FIG.5is a graph showing the relationship between the differential current Idiff and the temperature when the mirror ratio K is changed in the actual temperature compensation circuit100. When the mirror ratio K is reduced, the influence of the current IBis relatively increased. Therefore, the output current Idiff increases in a positive direction as the temperature increases. When the mirror ratio K is increased, the influence of the current KIAis relatively increased. Therefore, the output current Idiff advances in the direction of decreasing current as the temperature increases. Therefore, as long as the mirror ratio K is selected in the middle between the range that changes in the positive direction and the range that changes in the negative direction (e.g., the range denoted by S inFIG.5), the temperature change of the output current Idiff may be close to zero.

As such, according to the temperature compensation circuit of the present embodiment, it is possible to obtain a temperature-compensated constant current with higher accuracy than conventional ones by utilizing the difference in the temperature coefficients of the two PTAT current sources.

In the embodiment described, the NPN bipolar transistor Q1, the NPN bipolar transistor Q2, the NPN bipolar transistor Q3, and the NPN bipolar transistor Q4are used in the first PTAT current source110and the second PTAT current source120, but these transistors may also be replaced with diode-connected PNP bipolar transistors. Furthermore, NPN bipolar transistors may also be replaced with diodes. In this case, the emitter area ratio is equivalent to the number ratio of diodes connected in parallel.

In the embodiment, the emitter area ratio of the first PTAT current source110is 1:2, and the emitter area ratio of the second PTAT current source120is 1:4. However, these emitter area ratios are but an example, and there may be other emitter area ratios adoptable. For example, the emitter area ratio of the first PTAT current source110may 1:4, and the emitter area ratio of the second PTAT current source120may 1:8.

An example of adjusting the current IAgenerated by the first PTAT current source110is shown in the embodiment described, but the current IBgenerated by the second PTAT current source120may also be adjusted. In this case, the adjustment circuit130adjusts the mirror ratio of the transistor P6that forms the current mirror with the transistor P3and the transistor P4to be m=K′, and provides the adjusted current K′IBto the second current path of the differential circuit140. In addition, the adjustment circuit130may also adjust both the current IAand the current IB, and provide the adjusted current KIAand the current K′IBto the first current path and the second current path of the differential circuit140.

An example of supplying the current IBwith the transistor P6to the second current path of the differential circuit140is shown in the embodiment described, but the transistor P6is not necessarily required. For example, the current IBgenerated from the transistor P4of the second PTAT current source120may be directly supplied to the differential circuit140. In addition, the configuration of the differential circuit140is but an example. Other current differential circuits may also be adopted.

A modification of the adjustment circuit of the temperature compensation circuit of the present embodiment is described hereinafter with reference toFIG.6. In the embodiment, the adjustment circuit130includes a PMOS transistor P5constituting a current mirror. In this example, the first PTAT current source110shown inFIG.6includes an adjustment circuit130A. Except for the configuration mentioned above, the rest of the configuration is the same as that inFIG.3.

In the first PTAT current source110, the mirror ratio of the transistor P2constituting the current mirror circuit is adjusted to K (m=K). The adjustment circuit130A adjusts the mirror ratio K of the transistor P2according to the trim code TRC (e.g., the adjustment scheme as shown inFIG.4A), and provides the adjusted mirror current KIAto the differential circuit140. By removing the transistor P5that constitutes the current mirror, the configuration of the temperature compensation circuit100A is simplified, thereby saving more space.

In addition, in the case of adjusting the current IBof the second PTAT current source120, the mirror ratio of the transistor P4that constitutes the current mirror circuit may also be adjusted to K′ in the second PTAT current source120using the same scheme as above, and the adjusted mirror current K′IBmay be then provided to the second current path of the differential circuit140.

Another modification of the adjustment circuit of the temperature compensation circuit of the present embodiment is described hereinafter with reference toFIG.7. In the temperature compensation circuit100B of this modification, an adjustment circuit130B adjusts the magnitudes of the current IAand the current IBthat are proportional to the absolute temperature by changing the resistance value of the resistor RAof the first PTAT current source110and/or the resistance value of the resistor RBof the second PTAT current source120.

As the resistor RAand the resistor RBare variable resistors, the adjustment circuit130B may change the resistance values of the resistor RAand the resistor RBaccording to the trim code TRC. However, the adjustment scheme of the resistor may be chosen as needed. For example, as shown inFIG.4B, the adjustment circuit130B is connected to a switch SW1, a switch SW2, . . . , and a switch SWn at multiple terminal positions of the resistor RA, and the resistance value is changed by selectively turning on the switches SW1to SWn according to the trim code TRC to short-circuit part of the resistor RA.

In this example, the adjustment circuit130B adjusts the resistor RAor the resistor RB. However, if it is necessary to make the temperature change of the differential current Idiff close to zero, the adjustment circuit130B may also adjust the mirror ratio K simultaneously with the adjustment of the resistor RAand the resistor RBas shown inFIG.3orFIG.6.

A modification of the PTAT current source of the temperature compensation circuit of the present embodiment is described hereinafter with reference toFIG.8. The first PTAT current source110and the second PTAT current source120control the current IAand the current IBusing the current mirror circuit of the PMOS transistor, which may be replaced by an operational amplifier current mirror. The first PTAT current source110A and the second PTAT current source120A include a PMOS transistor P10, a PMOS transistor P11(having the same configuration as the transistor P10), and an operational amplifier112. The PMOS transistor P10and the PMOS transistor P11are connected to the supply voltage VDD. The operational amplifier112is connected to a node Node1to the non-inverting input terminal (+) and a node Node2to the inverting input terminal (−), and the output terminals are commonly connected to the gates of a transistor P10and a transistor P11. The operational amplifier112controls the gate voltages of the transistor P10and the transistor P11to equal the voltage of the node Node1and the voltage of the node Node2, such that equal current IAand current IBflow through the first current path and the second current path. Compared to the previous embodiment, equal current IA/current IBwith high precision is generated on the first current path and the second current path by using the operational amplifier112.

Although the embodiments of the disclosure has been described in detail, the disclosure is not limited to these embodiments, and various modifications and changes can be made within the scope of the disclosure described in the claims.