Display apparatus with multiple power modes and electronic system including the same

A display apparatus includes a display panel and a timing controller. The timing controller generates first output image data based on input image data and sets a driving frequency of the display panel as a first frequency in a first operation mode. The timing controller converts the input image data into second output image data and sets the driving frequency of the display panel as a second frequency lower than the first frequency in a second operation mode. The display panel displays a first image based on the first frequency and the first output image data in the first operation mode. The first image is represented by X grayscales. The display panel displays a second image based on the second frequency and the second output image data in the second operation mode. The second image is represented by Y grayscales, where Y is less than X.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2015-0076387, filed on May 29, 2015 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

Exemplary embodiments relate generally to display systems, and more particularly to display apparatuses that are used as one of input/output (I/O) devices and electronic systems including the display apparatuses.

DESCRIPTION OF THE RELATED ART

A liquid crystal display apparatus is a type of flat panel display (FPD), which is widely used in recent years. The FPD may include, but are not limited to, a liquid crystal display (LCD), a plasma display panel (PDP) and an organic light emitting display (OLED), for example.

The display apparatuses can be used in various electronic systems, such as a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), etc. As more capabilities and features are added to mobile devices their power consumption increases limiting performance.

SUMMARY

At least one exemplary embodiment of the present disclosure provides an electronic system including a display apparatus.

According to exemplary embodiments, a display apparatus includes a display panel and a timing controller. The timing controller generates first output image data based on input image data and sets a driving frequency of the display panel as a first frequency in a first operation mode. The timing controller converts the input image data into second output image data and sets the driving frequency of the display panel as a second frequency lower than the first frequency in a second operation mode. The display panel displays a first image based on the first frequency and the first output image data in the first operation mode. The first image is represented by X grayscales, where X is a natural number equal to or greater than two. The display panel displays a second image based on the second frequency and the second output image data in the second operation mode. The second image is represented by Y grayscales, where Y is a natural number less than X.

In an example embodiment, the display panel may display the second output image data based on a frame masking driving (FMD) scheme where every second frame of the input image data is blocked from the display.

In an example embodiment, the display apparatus may further include a data driver. The data driver may generate a plurality of data voltages based on one of the first output image data and the second output image data and to apply the plurality of data voltages to the display panel.

In an example embodiment, the display apparatus may further include a gate driver. The gate driver may generate a plurality of gate signals based on one of the first output image data and the second output image data and to apply the plurality of gate signals to the display panel.

In an example embodiment, the timing controller may include an image compensator, an image divider, an image analyzer, a grayscale selector and an image converter. The image compensator may generate the first output image data based on the input image data in the first operation mode. The image divider may generate a plurality of partial image data by dividing the input image data in the second operation mode. Each frame of the input image data is divided into a plurality of partial image data. The image analyzer may generate a plurality of grayscale histograms based on each partial image data of the plurality of partial image data. The grayscale selector may determine a plurality of representative grayscales for each partial image data of the plurality of partial image data based on the grayscale histograms for each partial image data and a plurality of reference grayscales. The image converter may generate the second output image data based on the plurality of partial image data and the plurality of representative grayscales.

A flicker level of the display panel may be lower than a reference flicker level when the display panel displays an image represented by the plurality of reference grayscales. The plurality of representative grayscales may be included in the plurality of reference grayscales.

In an example embodiment, the plurality of partial images may include a first partial image. The image divider may generate first partial image data corresponding to the first partial image. The image analyzer may generate a first grayscale histogram based on the first partial image data. The grayscale selector may determine first representative grayscales based on the first grayscale histogram and the plurality of reference grayscales. The image converter may generate a first part of the second output image data based on the first partial image data and the first representative grayscales.

In an example embodiment, the grayscale selector may select Z grayscales as the representative grayscales for each partial image data of the plurality of partial image data, where Z is a natural number equal to or less than Y. The Z grayscales may indicate majority grayscales among the plurality of reference grayscales in the grayscale histogram for each partial image data of the plurality of partial image data. The image converter may convert each of a plurality of grayscales for each partial image data of the plurality of partial image data into a respective one of the representative grayscales for each partial image data of the plurality of partial image data.

In an example embodiment, the plurality of partial images may include a second partial image. The image divider may generate second partial image data corresponding to the second partial image. The image analyzer may generate a second grayscale histogram based on the second partial image data. The grayscale selector may determine second representative grayscales based on the second grayscale histogram and the plurality of reference grayscales. The image converter may generate a second part of the second output image data based on the second partial image data and the second representative grayscales. Some of the second representative grayscales may be included in the first representative grayscales, and others of the second representative grayscales may be not included in the first representative grayscales.

In an example embodiment, the timing controller may further include a storage device. The storage may store the plurality of reference grayscales.

In an example embodiment, the timing controller may further include a reference grayscale setting unit. The reference grayscale setting unit may determine the plurality of reference grayscales based on flicker levels obtained from an external flicker measurement device.

In an example embodiment, the timing controller may further include a driving frequency setting unit. The driving frequency setting unit may set the driving frequency of the display panel as the first frequency in the first operation mode and may set the driving frequency of the display panel as the second frequency in the second operation mode.

The timing controller may receive a mode selection signal that selectively enables the first operation mode or the second operation mode.

According to exemplary embodiments, an electronic system includes a display apparatus and a processor. The display apparatus includes a display panel and a timing controller. The processor controls an operation of the display apparatus. The timing controller generates first output image data based on input image data and sets a driving frequency of the display panel as a first frequency in a first operation mode. The timing controller converts the input image data into second output image data and sets the driving frequency of the display panel as a second frequency lower than the first frequency in a second operation mode. The display panel displays a first image based on the first frequency and the first output image data in the first operation mode. The first image is represented by X grayscales, where X is a natural number equal to or greater than two. The display panel displays a second image based on the second frequency and the second output image data in the second operation mode. The second image is represented by Y grayscales, where Y is a natural number less than X.

In an example embodiment, the display panel may display the second output image data based on a frame masking driving (FMD) scheme where every second frame of the input image data is blocked from the display.

In an example embodiment, the display apparatus may further include a data driver. The data driver may generate a plurality of data voltages based on one of the first output image data and the second output image data to apply the plurality of data voltages to the display panel.

In an example embodiment, the display apparatus may further include a gate driver. The gate driver may generate a plurality of gate signals based on one of the first output image data and the second output image data and to apply the plurality of gate signals to the display panel.

In an example embodiment, the timing controller may include an image compensator, an image divider, an image analyzer, a grayscale selector and an image converter. The image compensator may generate the first output image data based on the input image data in the first operation mode. The image divider may generate a plurality of partial image data by dividing the input image data in the second operation mode. Each frame of the input image data is divided into a plurality of partial image data. The image analyzer may generate a plurality of grayscale histograms based on each partial image data of the plurality of partial image data. The grayscale selector may determine a plurality of representative grayscales for each partial image data of the plurality of partial image data based on the grayscale histograms for each partial image data and a plurality of reference grayscales. The image converter may generate the second output image data based on the plurality of partial image data and the plurality of representative grayscales.

In an example embodiment, the plurality of partial images may include a first partial image. The image divider may generate first partial image data corresponding to the first partial image. The image analyzer may generate a first grayscale histogram based on the first partial image data. The grayscale selector may determine first representative grayscales based on the first grayscale histogram and the plurality of reference grayscales. The image converter may generate a first part of the second output image data based on the first partial image data and the first representative grayscales. The grayscale selector may select Z grayscales as the first representative grayscales, where Z is a natural number equal to or less than Y. The Z grayscales may indicate majority grayscales among the plurality of reference grayscales in the first grayscale histogram. The image converter may convert each of a plurality of grayscales for the first partial image data into a respective one of the first representative grayscales.

The processor may generate a mode selection signal that selectively enables the first operation mode or the second operation mode to apply the mode selection signal to the timing controller.

According to an exemplary embodiment for operating a timing controller including receiving an input image data, a mode selection signal and selecting one of a first and a second operation mode based on the mode selection signal. A first operation mode includes, generating a first output image data based on the input image data in the first operation mode, wherein the first output image data may be image data that is substantially the same as the input image data. A second operation mode includes generating a partial image data by dividing input image data, generating grayscale histograms based on partial image data, determining representative grayscales based on grayscale histograms and reference grayscales and generating second output image data based on partial image data and representative grayscales. Generating a frequency signal indicating the driving frequency of the display panel based on the mode selection signal. Receiving an input control signal and generating a first control signal for a gate driver and a second control signal for a data driver based on the input control signal.

In an exemplary embodiment wherein the second operation mode further includes blocking, based on a frame masking driving (FMD) scheme, every second frame of the input image data and setting the driving frequency of the display panel to be a reciprocal of a period of two successive image frames.

In an exemplary embodiment wherein the second operation mode further includes blocking, based on a frame masking driving (FMD) scheme, every second and third frame of the input image data and setting the driving frequency of the display panel to be a reciprocal of a period of three successive image frames.

In an exemplary embodiment wherein the second operation mode further includes dividing each frame of the input image data into a plurality of partial image date; and the each frame may be divided into I-by-J partial images, where I and J are natural numbers.

DETAILED DESCRIPTION

Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application.

FIG. 1is a block diagram illustrating a display apparatus according to exemplary embodiments.

Referring toFIG. 1, a display apparatus10includes a display panel100, a timing controller200, a gate driver300and a data driver400.

The display panel100is connected to a plurality of gate lines GL and a plurality of data lines DL. The display panel100displays an image represented by a plurality of grayscales based on first output image data DAT1or second output image data DAT2. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2crossing (e.g., substantially perpendicular to) the first direction D1.

The display panel100may include a plurality of pixels that are arranged in a matrix form. Each pixel may be electrically connected to a respective one of the gate lines GL and a respective one of the data lines DL.

Each pixel may include a switching element, a liquid crystal capacitor and a storage capacitor. The liquid crystal capacitor and the storage capacitor may be electrically connected to the switching element. For example, the switching element may be a thin film transistor. The liquid crystal capacitor may include a first electrode connected to a pixel electrode and a second electrode connected to a common electrode. A data voltage may be applied to the first electrode of the liquid crystal capacitor. A common voltage may be applied to the second electrode of the liquid crystal capacitor. The storage capacitor may include a first electrode connected to the pixel electrode and a second electrode connected to a storage electrode. The data voltage may be applied to the first electrode of the storage capacitor. A storage voltage may be applied to the second electrode of the storage capacitor. The storage voltage may be substantially equal to the common voltage.

Each pixel may have a rectangular shape. For example, each pixel may have a relatively short side in the first direction D1and a relatively long side in the second direction D2. The relatively short side of each pixel may be substantially parallel to the gate lines GL. The relatively long side of each pixel may be substantially parallel to the data lines DL.

The timing controller200controls an operation of the display panel100and controls operations of the gate driver300and the data driver400. The timing controller200receives input image data IDAT, an input control signal ICONT and a mode selection signal MS from an external device (e.g., a host). The input image data IDAT may include a plurality of input pixel data for the plurality of pixels. Each input pixel data may include red grayscale data R, green grayscale data G and blue grayscale data B for a respective one of the plurality of pixels. The input control signal ICONT may include a master clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc. The mode selection signal MS may selectively enable a first operation mode or a second operation mode.

The timing controller200generates the first or second output image data DAT1or DAT2, a first control signal CONT1and a second control signal CONT2based on the input image data IDAT, the input control signal ICONT and the mode selection signal MS.

For example, the timing controller200may generate the first or second output image data DAT1or DAT2based on the input image data IDAT. The timing controller200may generate the first control signal CONT1based on the input control signal ICONT and the mode selection signal MS. The first control signal CONT1may be provided to the gate driver300. A driving timing of the gate driver300may be controlled based on the first control signal CONT1. The first control signal CONT1may include a vertical start signal, a gate clock signal, etc. The timing controller200may generate the second control signal CONT2based on the input control signal ICONT and the mode selection signal MS. The second control signal CONT2may be provided to the data driver400. A driving timing of the data driver400may be controlled based on the second control signal CONT2. The second control signal CONT2may include a horizontal start signal, a data clock signal, a data load signal, a polarity control signal, etc.

The gate driver300receives the first control signal CONT1from the timing controller200. The gate driver300generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1. The gate driver300may sequentially apply the plurality of gate signals to the gate lines GL.

The data driver400receives the second control signal CONT2and the output image data DAT1or DAT2from the timing controller200. The data driver400generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2and the output image data DAT1or DAT2(e.g., digital image data). The data driver400may apply the plurality of data voltages to the data lines DL.

In some exemplary embodiments, the data driver400may include a shift register, a latch, a signal processor and a buffer. The shift register may output a latch pulse to the latch. The latch may temporarily store the output image data, and may output the output image data to the signal processor. The signal processor may generate the analog data voltages based on the digital output image data and may output the analog data voltages to the buffer. The buffer may output the analog data voltages to the data lines DL.

In some exemplary embodiments, the gate driver300and/or the data driver400may be disposed, e.g., directly mounted, on the display panel100, or may be connected to the display panel100in a tape carrier package (TCP) type. Alternatively, the gate driver300and/or the data driver400may be integrated on the display panel100.

The display apparatus10according to exemplary embodiments may operate one of the first operation mode and the second operation mode based on the mode selection signal MS. In the first operation mode, the timing controller200generates the first output image data DAT1based on the input image data IDAT and sets a driving frequency of the display panel100as a first frequency. The display panel100displays a first image based on the first frequency and the first output image data DAT1in the first operation mode. The first image is represented by X grayscales, where X is a natural number equal to or greater than two. In the second operation mode, the timing controller200converts the input image data IDAT into the second output image data DAT2and sets the driving frequency of the display panel100as a second frequency lower than the first frequency. The display panel100displays a second image based on the second frequency and the second output image data DAT2in the second operation mode. The second image is represented by Y grayscales, where Y is a natural number less than X.

The first operation mode may be referred to as a normal operation mode or a high frequency mode. The second operation mode may be referred to as a low power mode or a low frequency mode. The first image may be a high quality image that is displayed based on a relatively high driving frequency and is represented by a relatively large number of grayscales. The second image may be a low quality image that is displayed based on a relatively low driving frequency and is represented by a relatively small number of grayscales. The display apparatus10according to exemplary embodiments may display the low quality image based on the relatively low driving frequency in the low power mode, and thus may have a relatively low power consumption.

FIGS. 2A, 2B and 2Care diagrams for describing an operation of the display apparatus according to exemplary embodiments.

Referring toFIGS. 1 and 2A, in the first operation mode, all of a plurality of image frames F11, F12, F13, F14, F15and F16(e.g., image frames for displaying the first image) may be displayed on the display panel100. The driving frequency of the display panel100may be a reciprocal of a period T1of a single image frame (e.g., the frame F11). For example, the period T1of the single image frame may be about 16.66 ms, and the driving frequency of the display panel100(e.g., the first frequency) may be set as about 60 Hz in the first operation mode.

Referring toFIGS. 1, 2B and 2C, in the second operation mode, the display apparatus10may operate based on a frame masking driving (FMD) scheme where a display of at least one image frame is blocked. In the FMD scheme, some of the image frames (e.g., image frames for displaying the second image) may be displayed on the display panel100, and a display of others of the image frames may be blocked.

In some exemplary embodiments, as illustrated inFIG. 2B, frames F21, F23and F25may be displayed on the display panel100, and a display of frames F22, F24and F26may be blocked. In other words, an output of one image frame (e.g., the frame F22) of two successive image frames (e.g., the frames F21and F22) may be blocked. The driving frequency of the display panel100may be a reciprocal of a period T2of two successive image frames (e.g., the frames F21and F22). For example, the period T2of the two successive image frames may be about 33.33 ms, and the driving frequency of the display panel100(e.g., the second frequency) may be set as about 30 Hz in the second operation mode.

In some exemplary embodiments, as illustrated inFIG. 2C, frames F31and F34may be displayed on the display panel100, and a display of frames F32, F33, F35and F36may be blocked. In other words, an output of two image frames (e.g., the frames F32and F33) of three successive image frames (e.g., the frames F31, F32and F33) may be blocked. The driving frequency of the display panel100may be a reciprocal of a period T3of three successive image frames (e.g., the frames F31, F32and F33). For example, the period T3of three successive image frames may be about 50 ms, and the driving frequency of the display panel100(e.g., the second frequency) may be set as about 20 Hz in the second operation mode.

In some exemplary embodiments, at least one image frame for displaying the second image may be blocked in the FMD scheme by blocking an output of the data driver400. For example, in the case ofFIG. 2B, the data driver400may output the plurality of data voltages for the frames F21, F23and F25and may block an output of the plurality of data voltages for the frames F22, F24and F26. In the example ofFIG. 2C, the data driver400may output the plurality of data voltages for the frames F31and F34and may block an output of the plurality of data voltages for the frames F32, F33, F35and F36.

In some exemplary embodiments, at least one image frame for displaying the second image may be blocked in the FMD scheme by blocking an output of the gate driver300. For example, in the case ofFIG. 2B, the gate driver300may output the plurality of gate signals for the frames F21, F23and F25and may block an output of the plurality of gate signals for the frames F22, F24and F26. In the example ofFIG. 2C, the gate driver300may output the plurality of gate signals for the frames F31and F34and may block an output of the plurality of gate signals for the frames F32, F33, F35and F36.

Alternatively, at least one image frame for displaying the second image may be blocked in the FMD scheme by blocking one or both of the output of the data driver400and the output of the gate driver300.

Although not illustrated inFIGS. 2B and 2C, in the second operation mode, the display apparatus10may operate based on one of various low frequency driving schemes. For example, inFIG. 2B, the frame F21may be consecutively displayed on the display panel100during the whole period T2in the second operation mode. InFIG. 2C, the frame F31may be consecutively displayed on the display panel100during the whole period T3in the second operation mode.

FIG. 3is a block diagram illustrating a timing controller included in the display apparatus according to exemplary embodiments.

Referring toFIGS. 1 and 3, a timing controller200may include an image compensator210, an image divider220, an image analyzer230, a storage device240, a grayscale selector250, an image converter260, a driving frequency setting unit270and a control signal generator280.

The image compensator210may receive the mode selection signal MS and the input image data IDAT. The image compensator210may generate the first output image data DAT1based on the input image data IDAT in the first operation mode. The first output image data DAT1may be image data that is substantially the same as the input image data IDAT or compensated image data that is generated by compensating the input image data IDAT. For example, the image compensator210may selectively perform image quality compensation, a spot compensation, an adaptive color correction (ACC), and/or a dynamic capacitance compensation (DCC) for the input image data IDAT to generate the first output image data DAT1.

The image divider220may receive the mode selection signal MS and the input image data IDAT. The image divider220may generate a plurality of partial image data PDAT by dividing the input image data IDAT in the second operation mode. Each of the plurality of partial image data PDAT may correspond to a respective one of a plurality of partial images partitioned from the first image. The number of the partial images and the number of the partial image data PDAT may be changed.

The image analyzer230may generate a plurality of grayscale histograms HIS based on the plurality of partial image data PDAT. The grayscale histogram may indicate a relationship between a plurality of grayscales and the number of pixels corresponding to the plurality of grayscales. For example, each of the partial image data PDAT may include a plurality of pixel data. Each of the grayscale histograms HIS may indicate, for example, the number of the pixel data corresponding to two hundred fifty six grayscales, which range from about 0 grayscale to about 255 grayscale.

The storage240may store a plurality of reference grayscales GREF. For example, the storage240may include, for example, at least one nonvolatile memory such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), etc.

The plurality of reference grayscales GREF may be flicker free grayscales that allow the display panel100to operate in the low frequency mode without flicker. The plurality of reference grayscales GREF will be described in detail with reference toFIG. 7.

The grayscale selector250may select a plurality of representative grayscales GREP based on the plurality of grayscale histograms HIS and the plurality of reference grayscales GREF. As will be described with reference toFIG. 8, the plurality of representative grayscales GREP may be included in the plurality of reference grayscales GREF.

The image converter260may generate the second output image data DAT2based on the plurality of partial image data PDAT and the plurality of representative grayscales GREP. The image converter260may convert each of the plurality of partial image data PDAT and may combine the plurality of converted partial image data to generate the second output image data DAT2.

The driving frequency setting unit270may generate a frequency signal FS indicating the driving frequency of the display panel100based on the mode selection signal MS. The driving frequency setting unit270may set the driving frequency of the display panel100as the first frequency in the first operation mode and may set the driving frequency of the display panel100as the second frequency in the second operation mode. For example, as described with reference toFIGS. 2A, 2B and 2C, the first frequency may be set to about 60 Hz, and the second frequency may be set to about 30 Hz, 20 Hz, etc.

The control signal generator280may receive the input control signal ICONT. The control signal generator280may generate the first control signal CONT1for the gate driver300and the second control signal CONT2for the data driver400based on the input control signal ICONT and the driving frequency of the display panel100(e.g., the frequency signal FS). The control signal generator280may output the first control signal CONTI to the gate driver300and may output the second control signal CONT2to the data driver400.

As described above, in the second operation mode, the image divider220may be enabled, and the image analyzer230, the storage240, the grayscale selector250and the image converter260may be also enabled. In the first operation mode, the image divider220, the image analyzer230, the storage240, the grayscale selector250and the image converter260may be disabled. The image compensator210may be enabled in the first operation mode and may be disabled in the second operation mode.

In an exemplary embodiment, inFIG. 3, the image quality compensation, the spot compensation, the ACC, and/or the DCC for the input image data IDAT or the second output image data DAT2may be selectively performed in the second operation mode. In other words, the image compensator210may be enabled in both the first operation mode and the second operation mode.

FIG. 4is a flow chart illustrating an operation of the timing controller ofFIG. 3.FIGS. 5, 6A, 6B, 6C, 6D, 7 and 8are diagrams for describing the operation of the timing controller ofFIG. 3.FIG. 5is a plan view illustrating an example of dividing an image.FIGS. 6A, 6B, 6C and 6Dare graphs illustrating an example of the grayscale histograms HIS.FIG. 7is a graph illustrating an example of the reference grayscales GREF.FIG. 8is a table illustrating an example of the representative grayscales GREP.FIG. 9is a flow chart illustrating an example of step S400inFIG. 4.

Hereinafter, an operation of the timing controller200that generates the second output image data DAT2in the second operation mode will be described in detail.

Referring toFIGS. 3, 4, 5, 6A, 6B, 6C, 6D, 7, 8 and 9, the image divider220may generate the plurality of partial image data PDAT by dividing the input image data IDAT in the second operation mode (step S100). For example, as illustrated inFIG. 5, an image IMG1corresponding to the input image data IDAT (or corresponding to the first output image data DAT1) may be divided into first, second, third and fourth partial images PI1, PI2, PI3and PI4. In other words, the image IMG1(e.g., the first image) may include the first through fourth partial images PI1˜PI4, and the image divider220may generate first, second, third and fourth partial image data corresponding to the first through fourth partial images PI1˜PI4.

AlthoughFIG. 5illustrates the example in which the image IMG1is divided into two-by-two partial images, the first image may be divided into I-by-J partial images, where I and J are natural numbers.

In an exemplary embodiment, the image IMG1may be divided into six partial images. The image IMG1may be divided by the image divider220into three segments along a horizontal direction and two segments along a vertical line. In other words, the image IMG1(e.g., the first image) may include the first through sixth partial images PI1˜PI6, and the image divider220may generate first, second, third, fourth, fifth and sixth partial image data corresponding to the first through sixth partial images PI1˜PI6.

The image analyzer230may generate the plurality of grayscale histograms HIS based on the plurality of partial image data PDAT in the second operation mode (step S200). For example, the image analyzer230may generate a first grayscale histogram illustrated inFIG. 6Abased on the first partial image data. The image analyzer230may generate a second grayscale histogram illustrated inFIG. 6Bbased on the second partial image data. The image analyzer230may generate a third grayscale histogram illustrated inFIG. 6Cbased on the third partial image data. The image analyzer230may generate a fourth grayscale histogram illustrated inFIG. 6Dbased on the fourth partial image data.

AlthoughFIGS. 6A, 6B, 6C and 6Dillustrate the example in which the partial images PI1˜PI4in the image IMG1ofFIG. 5are represented by two hundred fifty six grayscales, which range from about 0 grayscale to about 255 grayscale, the partial images may be represented by M grayscales, where M is a natural number.

The plurality of reference grayscales GREF may be determined based on a characteristic of the display panel100inFIG. 1. For example, in a manufacturing process, test images having various grayscales may be displayed on the display panel100, and flicker levels of the display panel100may be measured based on the test images. Thus, as illustrated inFIG. 7, a relationship between a plurality of grayscales and a plurality of flicker levels corresponding to the plurality of grayscales may be obtained. Based on the graph ofFIG. 7, a minimum grayscale (e.g., about 0 grayscale) and flicker free grayscales may be selected as the plurality of reference grayscales GREF. The flicker free grayscales may allow the display panel100to have a flicker level lower than a reference flicker level RFLK (e.g., about 1.0) and may be grayscales between GREFA and GREFB in the graph ofFIG. 7(e.g., about 32 grayscale through about 162 grayscale). In other words, the flicker level of the display panel100may be lower than the reference flicker level RFLK when the display panel100displays an image only represented by the plurality of reference grayscales GREF.

AlthoughFIG. 7illustrates the example in which the reference flicker level RFLK is about 1.0 and the plurality of reference grayscales GREF include about 0 grayscale and about 32 grayscale through about 162 grayscale, the reference flicker level and the plurality of reference grayscales may be not limited thereto.

The grayscale selector250may determine the plurality of representative grayscales GREP based on the plurality of grayscale histograms HIS and the plurality of reference grayscales GREF in the second operation mode (step S300). For example, the grayscale selector250may determine first representative grayscales for the first partial image data based on the first grayscale histogram ofFIG. 6Aand the reference grayscales GREF obtained from the graph ofFIG. 7. The grayscale selector250may determine second representative grayscales for the second partial image data based on the second grayscale histogram ofFIG. 6Band the reference grayscales GREF. The grayscale selector250may determine third representative grayscales for the third partial image data based on the third grayscale histogram ofFIG. 6Cand the reference grayscales GREF. The grayscale selector250may determine fourth representative grayscales for the fourth partial image data based on the fourth grayscale histogram ofFIG. 6Dand the reference grayscales GREF.

In some exemplary embodiments, the grayscale selector250may select Z grayscales as the first representative grayscales, where Z is a natural number equal to or less than Y. The Z grayscales may indicate majority grayscales among the plurality of reference grayscales GREF in the first grayscale histogram. For example, the first grayscale histogram ofFIG. 6Amay include a large number of about 0 grayscale, about 32 grayscale, about 43 grayscale, about 81 grayscale, about 89 grayscale, about 130 grayscale, about 139 grayscale and about 162 grayscale among the reference grayscales GREF (e.g., about 0 grayscale and about 32 grayscale through about 162 grayscale). Thus, as illustrated inFIG. 8, about 0 grayscale, about 32 grayscale, about 43 grayscale, about 81 grayscale, about 89 grayscale, about 130 grayscale, about 139 grayscale and about 162 grayscale, which are the majority grayscales in the first grayscale histogram ofFIG. 6A, may be selected as the first representative grayscales. The first representative grayscales may be included in the plurality of reference grayscales GREF. In other words, the first representative grayscales may be a subset of the reference grayscales GREF.

Similarly, about 0 grayscale, about 32 grayscale, about 43 grayscale, about 77 grayscale, about 81 grayscale, about 89 grayscale, about 130 grayscale and about 162 grayscale, which are majority grayscales among the plurality of reference grayscales GREF in the second grayscale histogram ofFIG. 6B, and may be selected as the second representative grayscales. About 0 grayscale, about 32 grayscale, about 43 grayscale, about 83 grayscale, about 112 grayscale, about 128 grayscale, about 151 grayscale and about 162 grayscale, which are majority grayscales among the plurality of reference grayscales GREF in the third grayscale histogram ofFIG. 6C, and may be selected as the third representative grayscales. About 0 grayscale, about 32 grayscale, about 43 grayscale, about 83 grayscale, about 90 grayscale, about 112 grayscale, about 141 grayscale and about 162 grayscale, which are majority grayscales among the plurality of reference grayscales GREF in the fourth grayscale histogram ofFIG. 6D, and may be selected as the fourth representative grayscales.

The plurality of representative grayscales GREP may be substantially the same each other or may be different from each other depending on grayscale distributions of the partial images PI1˜PI4. For example, some (e.g., about 0 grayscale, about 32 grayscale, about 43 grayscale, about 81 grayscale, about 89 grayscale, about 130 grayscale and about 162 grayscale) of the second representative grayscales may be included in the first representative grayscales, and others (e.g., about 77 grayscale) of the second representative grayscales may be not included in the first representative grayscales.

AlthoughFIG. 8illustrates the example in which eight representative grayscales are selected for one partial image, the number of selected representative grayscales may be not limited thereto.

The image converter260may generate the second output image data DAT2based on the plurality of partial image data PDAT and the plurality of representative grayscales GREP in the second operation mode (step S400). For example, the image converter260may generate a first part of the second output image data DAT2based on the first partial image data and the first representative grayscales illustrated inFIG. 8. The image converter260may generate a second part of the second output image data DAT2based on the second partial image data and the second representative grayscales illustrated inFIG. 8. The image converter260may generate a third part of the second output image data DAT2based on the third partial image data and the third representative grayscales illustrated inFIG. 8. The image converter260may generate a fourth part of the second output image data DAT2based on the fourth partial image data and the fourth representative grayscales illustrated inFIG. 8. The image converter260may combine the first through fourth parts of the second output image data DAT2to generate the second output image data DAT2.

In some exemplary embodiments, the image converter260may convert each of a plurality of grayscales for the first partial image data into a respective one of the first representative grayscales. For example, the image converter260may perform a grayscale conversion for the first partial image data and may perform a dithering operation to minimize a quantization error, which is caused by the grayscale conversion, between an input grayscale (e.g., an original grayscale) and an output grayscale (e.g., a converted grayscale).

The grayscale conversion and the dithering operation will be described in detail with reference toFIG. 9.

InFIG. 9, the image converter260may compare an original N-th grayscale GN with the first representative grayscales, where N is a natural number (step S410). The original N-th grayscale GN may be an original grayscale for N-th pixel data among a plurality of pixel data included in the first partial image data.

When the original N-th grayscale GN is substantially equal to one of the first representative grayscales (step S410: YES), the image converter260may set a converted N-th grayscale GN′ for the N-th pixel data as the original N-th grayscale GN (step S420).

When the original N-th grayscale GN is different from all of the first representative grayscales (step S410: NO), the image converter260may set the converted N-th grayscale GN′ for the N-th pixel data as one of the first representative grayscales, which is closest to the original N-th grayscale GN, based on threshold grayscales THL (step S430).

In some exemplary embodiments, the threshold grayscales THL may include middle grayscales, each of which is between two representative grayscales. For example, as illustrated inFIG. 8, when the first representative grayscales include about 0 grayscale, about 32 grayscale, about 43 grayscale, about 81 grayscale, about 89 grayscale, about 130 grayscale, about 139 grayscale and about 162 grayscale, the threshold grayscales THL for the first representative grayscales may include about 16 grayscale, about 37.5 grayscale, about 62 grayscale, about 85 grayscale, about 109.5 grayscale, about 134.5 grayscale and about 150.5 grayscale.

The image converter260may perform an error calculation by subtracting the original N-th grayscale GN from the converted N-th grayscale GN′ to generate an error grayscale Err for the N-th pixel data (step S440). For example, when the converted N-th grayscale GN′ is about 32 grayscale and when the original N-th grayscale GN is about 20 grayscale, the error grayscale Err may be about 10 grayscale.

The image converter260may perform an error diffusion based on the error grayscale Err (step S450). For example, the error grayscale Err may be spread to neighboring pixels that are adjacent to a pixel operating based on the N-th pixel data.

In some exemplary embodiments, the steps S440and S450may be performed based one of a Floyd-Steinberg dithering algorithm, a Jarvis, Judice and Ninke dithering algorithm, a Stucki dithering algorithm and a Atkinson dithering algorithm. The Floyd-Steinberg dithering algorithm, Jarvis, Judice and Ninke dithering algorithm, Stucki dithering algorithm and Atkinson dithering algorithm are widely known to those skilled in the art, and thus will be not described in detail.

When the grayscale conversion and the dithering operation for each of the pixel data of the plurality of pixel data included in the first partial image data are not completed (step S460: NO), the number N increases (step S470), and the steps S410, S420, S430, S440, S450and S460may be repeated for each of the plurality of pixel data included in the first partial image data other than first through N-th pixel data. The steps may be repeated until the grayscale conversion and the dithering operation for each of the pixel data of the plurality of pixel data included in the first partial image data are completed.

When the grayscale conversion and the dithering operation for each of the pixel data of the plurality of pixel data included in the first partial image data are completed (step S460: YES), the data conversion for the first partial image data may be terminated, and the image converter260may generate the first part of the second output image data DAT2corresponding to the first partial image data.

Similarly, the image converter260may convert each of a plurality of grayscales for the second partial image data into a respective one of the second representative grayscales. The image converter260may convert each of a plurality of grayscales for the third partial image data into a respective one of the third representative grayscales. The image converter260may convert each of a plurality of grayscales for the fourth partial image data into a respective one of the fourth representative grayscales.

FIG. 10is a block diagram illustrating a timing controller included in the display apparatus according to exemplary embodiments.FIG. 11is a block diagram illustrating a flicker measurement device to measure flicker levels of the display apparatus according to exemplary embodiments.

The display apparatus10ofFIG. 11according to exemplary embodiments may display the low quality image based on the relatively low driving frequency and the second output image data DAT2in the second operation mode, and thus may have a relatively low power consumption.

Referring toFIGS. 1, 10 and 11, a timing controller200amay include an image compensator210, an image divider220, an image analyzer230, a reference grayscale setting unit245, a grayscale selector250, an image converter260, a driving frequency setting unit270and a control signal generator280.

The timing controller200aofFIG. 10may be substantially the same as the timing controller200ofFIG. 3, except that the storage240inFIG. 3is replaced with the reference grayscale setting unit245inFIG. 10. The image compensator210, the image divider220, the image analyzer230, the grayscale selector250, the image converter260, the driving frequency setting unit270and the control signal generator280inFIG. 10may be substantially the same as the image compensator210, the image divider220, the image analyzer230, the grayscale selector250, the image converter260, the driving frequency setting unit270and the control signal generator280inFIG. 3, respectively.

The reference grayscale setting unit245may determine the plurality of reference grayscales GREF based on a plurality of flicker levels FV obtained from an external flicker measurement device30. For example, a relationship between a plurality of grayscales and a plurality of flicker levels corresponding to the plurality of grayscales may be obtained in real time by displaying test images having various grayscales on the display panel100and by measuring flicker levels of the display panel100based on the test images. The plurality of reference grayscales GREF may be determined based on the relationship (e.g., the graph ofFIG. 7) and a reference flicker level (e.g., RFLK inFIG. 7).

In some exemplary embodiments, the display apparatus10may be temporarily connected to the flicker measurement device30and may receive the plurality of flicker levels FV from the flicker measurement device30. For example, the display apparatus10may communicate with the flicker measurement device30using a protocol between communication interfaces, based on, for example, an Inter-Integrated Circuit (I2C) interface. When the determination of the reference grayscales GREF is completed, the flicker measurement device30may be separated from the display apparatus10.

Although not illustrated inFIG. 10, the plurality of reference grayscales GREF may be provided with the input image data IDAT. For example, the reference grayscales GREF may be inserted into a header of the input image data IDAT.

FIG. 12is a block diagram illustrating an electronic system according to exemplary embodiments.FIG. 13is a diagram illustrating an example in which the electronic system ofFIG. 12is implemented as a portable electronic device.

Referring toFIG. 12, an electronic system1000includes a processor1010, a connectivity unit1020, a memory device1030, a display apparatus1040, a user interface1050and a power supply1060. In some exemplary embodiments, the electronic system1000may be any portable electronic device, such as a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistants (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation system, etc.

The processor1010may execute applications, such as an internet browser, a game application, a video player application, etc. For example, the processor1010may be a central processing unit (CPU), an application processor (AP), etc.

In some exemplary embodiments, the processor1010may include a single processor core or a plurality of processor cores. For example, the processor1010may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. In some exemplary embodiments, the processor1010may further include a cache memory located inside or outside the processor1010.

The connectivity unit1020may perform wired or wireless communication with an external device. For example, the connectivity unit1020may perform a USB communication, an Ethernet communication, a near field communication (NFC), a radio frequency identification (RFID) communication, a mobile telecommunication, a memory card communication, wireless internet, wireless fidelity (Wi-Fi), global positioning system (GPS), Bluetooth (BT), global system for mobile communication (GSM), general packet radio system (GPRS), wideband code division multiple access (WCDMA), high speed uplink/downlink packet access (HSxPA), etc. The connectivity unit1020may include a baseband chipset.

The memory device1030may store an instruction/data processed by the processor1010, may serve as a working memory, or may store a boot image for booting the electronic system1000. For example, the memory device1030may include at least one volatile memory, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), etc., and/or at least one nonvolatile memory, such as an EPROM, an EEPROM, a flash memory, a PRAM, a RRAM, a MRAM, a FRAM, a NFGM, a PoRAM, etc.

In some exemplary embodiments, the processor1010may generate the mode selection signal MS that selectively enables the first operation mode or the second operation mode to apply the mode selection signal MS to the timing controller200. In some exemplary embodiments, to additionally reduce the power consumption after the second operation mode is enabled, a part of the processor cores in the processor1010may not operate, luminance of the display apparatus1040may be reduced, and/or the number of applications (e.g., softwares or programs) executed by the processor1010may be reduced.

The selection of the mode indicated by the mode selection signal MS may be automatic or manual. For example, a processor of the device may automatically change the mode selection signal MS based on a remaining charge contained is the device's battery, a current uptime of the device and/or a projected remaining operating time based on the remaining charge contained is the device's battery. The selection of the mode selection signal MS may be performed by a user of the device or based on a schedule set by the user of the device.

The user interface1050may include at least one input device, such as a keypad, a touch screen, a keyboard, a mouse, a microphone, etc., and at least one output device, such as a speaker, etc. The power supply1060may supply power to the electronic system1000. In some exemplary embodiments, the electronic system1000may further include a camera image processor (CIS) storage device, such as a memory card, a solid state drive (SSD), a CD-ROM, etc.

According to exemplary embodiments, the electronic system1000and/or components of the electronic system1000may be packaged in various forms, such as a package on package (PoP), a ball grid arrays (BGA), a chip scale packages (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline IC (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi chip package (MCP), a wafer-level fabricated package (WFP), or a wafer-level processed stack package (WSP).

Although the exemplary embodiments are described based on the examples of specific frequencies, specific grayscales and the specific number of partial images, the exemplary embodiments will be employed to an example in which the display panel operates based on any driving frequency, any grayscales are set as the representative grayscales, and/or an image displayed on the display panel is divided into any number of the partial images.

The above described embodiments may be used in a display apparatus and/or a system including the display apparatus, such as a mobile phone, a smart phone, a PDA, a PMP, a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation device, a personal computer (PC), a server computer, a workstation, a tablet computer, a laptop computer, a smart card, a printer, etc.