Capacitance phase interpolation circuit and method thereof, and multi-phase generator applying the same

A capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed. The first capacitance phase interpolation unit includes a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling, and the first capacitance phase interpolation unit receives a plurality of reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, wherein a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained via the first capacitance phase interpolation unit and the second capacitance phase interpolation unit by performing phase interpolation on all the reference clock signals.

CROSS-REFERENCE OF RELATED APPLICATION

This application claims the benefit of Taiwan application Serial No. 103120318, filed Jun. 12, 2014, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The disclosure relates in general to a capacitance phase interpolation circuit and a method thereof, and a multi-phase generator using the same.

BACKGROUND

Phase interpolation technology has been widely used in electronic devices, such as clock generator, testing machine and so on, for interpolating a plurality of output clock signals having different phases from a plurality of reference clock signals.

Normally, phase interpolation technology is used in a high-frequency operating environment, and thus factors, such as high-frequency noise interference, frequency offset and phase error, are taken into consideration. Of these factors, the phase error is normally caused by process variation.

Therefore, the present disclosure discloses a capacitance phase interpolation circuit and a method thereof capable of overcoming above factors to obtain required output clock signals.

SUMMARY

The disclosure is directed to a capacitance phase interpolation circuit, a method thereof, and a multi-phase generator using the same, wherein each of the output clock signals is obtained by performing phase interpolation on all the reference clock signals.

According to one embodiment, a capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed. The first capacitance phase interpolation unit includes a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling, and the first capacitance phase interpolation unit receives a plurality of reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, wherein a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained via the first capacitance phase interpolation unit and the second capacitance phase interpolation unit by performing phase interpolation on all the reference clock signals.

According to another embodiment, a capacitance phase interpolation method is disclosed. A plurality of reference clock signals are received by a first capacitance phase interpolation unit including a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling. Interpolation is performed by the first capacitance phase interpolation unit and a second capacitance phase interpolation unit, wherein the second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained by performing phase interpolation on all the reference clock signals.

According to an alternative embodiment, a multi-phase generator including a phase-locked loop, an interpolation circuit and a phase selector is disclosed. The phase-locked loop generates a first multi-phase output signal from a reference signal. The interpolation circuit is coupled to the phase-locked loop for obtaining a second multi-phase output signal by interpolating the first multi-phase output signal outputted from the phase-locked loop. The phase selector is coupled to the interpolation circuit for selecting at least a phase from the second multi-phase output signal.

DETAILED DESCRIPTION

Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. The common technology or theory in the field of the disclosure is not described in details if it does not involve the features of the disclosure. Further, shapes, sizes and ratios of the objects are exemplary for one skilled person in the art to understand the disclosure, not to limit the disclosure.

Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure.

Referring toFIG. 1A, a circuit diagram of a capacitance phase interpolation circuit according to an embodiment of the present disclosure is shown. As indicated inFIG. 1A, the capacitance phase interpolation circuit100according to the embodiment of the present disclosure includes a first capacitance phase interpolation unit110and a buffer unit120. The first capacitance phase interpolation unit110includes a plurality of capacitors110a˜110i(also referred as a first capacitance group), wherein each of the capacitors110a˜110ihas equivalent capacitance. The buffer unit120includes a plurality of phase inverters120a˜120f, wherein each of the phase inverters120a˜120fbasically has equivalent circuit structure.

The capacitor110ahas two ends: one is coupled to a first reference clock CLK0, and the other is coupled to the capacitor110i.

The capacitor110bhas two ends: one is coupled to the first reference clock CLK0, and the other is coupled to the phase inverter120aof the buffer unit120.

The capacitor110chas two ends: one is coupled to the first reference clock CLK0, and the other is coupled to the phase inverter120bof the buffer unit120.

The capacitor110dhas two ends: one is coupled to a second reference clock CLK1, and the other is coupled to the phase inverter120bof the buffer unit120. Or, the capacitors110cand110dare serially coupled between the first reference clock signal CLK0and the second reference clock signal CLK1of the reference clock signals, wherein the capacitors110cand110dtogether are coupled to the phase inverter120b.

The capacitor110ehas two ends: one is coupled to the second reference clock CLK1, and the other is coupled to the phase inverter120cof the buffer unit120.

The capacitor110fhas two ends: one is coupled to the second reference clock CLK1, and the other is coupled to the phase inverter120dof the buffer unit120.

The capacitor110ghas two ends: one is coupled to a third reference clock CLK2, and the other is coupled to the phase inverter120dof the buffer unit120.

The capacitor110hhas two ends: one is coupled to the third reference clock CLK2, and the other is coupled to the phase inverter120eof the buffer unit120.

The capacitor110ihas two ends: one is coupled to the third reference clock CLK2, and the other is coupled to the phase inverter120fof the buffer unit120.

The phase inverter120ais coupled to the capacitor110bfor inverting the first reference clock CLK0to a first output clock signal P0.

The phase inverter120bis coupled to the capacitors110cand110d. Since the second ends of the capacitors110cand110dare coupled to a node N1, the signal at the node N1is an interpolation result of the first reference clock CLK0and the second reference clock CLK1. Therefore, the phase inverter120binverts the signal at the node N1to a second output clock signal P1.

The phase inverter120cis coupled to the capacitor110efor inverting the second reference clock CLK1to a third output clock signal P2.

The phase inverter120dis coupled to the capacitors110fand110g. Since the second ends of capacitors110fand110gare coupled to a node N2, the signal at the node N2is an interpolation result of the second reference clock CLK1and the third reference clock CLK2. Therefore, the phase inverter120dinverts the signal at the node N2to a fourth output clock signal P3.

The phase inverter120eis coupled to the capacitor110hfor inverting the third reference clock CLK2to a fifth output clock signal P4.

The phase inverter120fis coupled to the capacitors110iand110a. Since the second ends of capacitors110iand110aare coupled to a node N3, the signal at the node N3is an interpolation result of the third reference clock CLK2and the first reference clock CLK0. Therefore, the phase inverter120finverts the signal at the node N3to a sixth output clock signals P5.

Signals at the nodes N1, N2and N3are referred as intermediate signals; and signals between capacitors and their associated phase inverters are also referred as intermediate signals.

As indicated inFIG. 1A, the capacitance phase interpolation circuit100obtains six output clock signals by performing phase interpolation on three reference clock signals, wherein three output clock signals among the six output clock signals are inverse signals of the three reference clock signals, and the other three output clock signals are inverse signals of three intermediate signals obtained by performing phase interpolation on every two of the three reference clock signals.

As indicated inFIG. 1A, each signal path for generating output clock signal includes one single phase inverter. However, anyone who is skilled in the technology field of the present disclosure shall understand that the signal path may include two or more than two phase inverters (that is, one or more than one phase inverters is serially coupled to the phase inverter120a, and such design is still within the spirit of the present disclosure.

In addition, the one or more than one phase inverter of each signal path for generating output clock signal may be used for adjusting the level of the output clock signal, and such design is still within the spirit of the present disclosure.

Besides, the capacitors110a˜110iof the first capacitance phase interpolation unit110may be regarded as ring coupling because the first capacitor110ais coupled to the last capacitor110i. That is, the capacitors are either directly coupled or indirectly coupled. Moreover, among the capacitors110a˜110i, the capacitors110a,110c,110d,110f,110gand110iare serially coupled to each other.

FIG. 1Bis a detailed circuit diagram of the phase inverter120a. As indicated inFIG. 1B, the phase inverter120aincludes a capacitor C1, a resistor R1, and transistors T1and T2. The capacitor C1is coupled between an input end and a node N4. The capacitor C1, the resistor R1, the transistor T1and T2are coupled to the node N4. The resistor R1is coupled between the node N4and an output node. The transistor T1is coupled to the node N4, a voltage supply (not illustrated) and the output node. The transistor T2is coupled to the node N4, a ground end and the output node. Descriptions of the operations of the elements of the phase inverter120aare omitted here.

Referring toFIG. 2, a circuit diagram of a capacitance phase interpolation circuit according to another embodiment of the present disclosure is shown. As indicated inFIG. 2, the capacitance phase interpolation circuit200includes a first capacitance phase interpolation unit210, a buffer unit220and a second capacitance phase interpolation unit230. The first capacitance phase interpolation unit210includes a plurality of capacitors210a˜210i. The buffer unit220includes a plurality of phase inverters220a˜220f. The second capacitance phase interpolation unit230includes a plurality of capacitors230a˜230f(also referred as a second capacitance group), wherein each of the capacitors230a˜230fhas equivalent capacitance, and the capacitors230a˜230fare serially coupled. The structures and operations of the first capacitance phase interpolation unit210and the buffer unit220are identical or similar to that illustrated inFIG. 1A, and specific descriptions are omitted here.

The structures and operations of the second capacitance phase interpolation unit230are disclosed below. The capacitor230ahas two ends respectively coupled to nodes N21and N22. The capacitors210b,230aand230ftogether with the phase inverter220aare coupled to the node N21. The capacitors210c,210d,230aand230btogether with the phase inverter220bare coupled to the node N22.

The capacitor230bhas two ends respectively coupled to nodes N22and N23. The capacitors210e,230band230ctogether with the phase inverter220care coupled to the node N23.

The capacitor230chas two ends respectively coupled to nodes N23and N24. The capacitors210f,210g,230c, and230dtogether with the phase inverter220dare coupled to the node N24.

The capacitor230dhas two ends respectively are coupled to node N24and N25. The capacitors210h,230d, and230etogether with the phase inverter220eare coupled to the node N25.

The capacitor230ehas two ends respectively coupled to node N25and N26. The capacitors210i,210a,230e, and230ftogether with the phase inverter220fare coupled to the node N26.

The capacitor230fhas two ends respectively coupled to node N26and N21.

The coupling relationship between the capacitors230a˜230fis referred as “ring” coupling. That is, anyone of the capacitors230a˜230fmay be coupled to anyone of the capacitors230a˜230f. For example, the capacitor230amay be coupled to the capacitor230dvia the capacitors230band230c.

Details of interpolation are disclosed below. In the embodiment illustrated inFIG. 2, the coupling relationship between the capacitors230a˜230fof the second capacitance phase interpolation unit230is ring coupling. During interpolation, each output clock signal is obtained by performing phase interpolation on each reference clock signal (that is, each input signal) and all the other output clock signals. Or, each output clock signal is obtained by performing phase interpolation on all the reference clock signals. Let the first output clock signal P0be taken for example. The phase inverter220ainverts the signal at the node N21to obtain the first output clock signal P0. As for the node N21, the first reference clock CLK0may be coupled to the node N21via the capacitor210b; the second reference clock CLK1may be coupled to the node N21via the capacitors210dand230a; and the third reference clock CLK2may be coupled to the node N21via the capacitors210i,210aand210b. Moreover, the second output clock signal P1(that is, the signal at the node N22) may be coupled to the node N21via the capacitor230a; the third output clock signal P2(that is, the signal at the node N23) may be coupled to the node N21via the capacitors230aand230b; the fourth output clock signal P3(that is, the signal at the node N24) may be coupled to the node N21via the capacitors230a,230band230c(or, via the capacitors230d,230eand230f); the fifth output clock signal P4(that is, the signal at the node N25) may be coupled to the node N21via the capacitors230eand230f; and the sixth output clock signals P5(that is, the signal at the node N26) may be coupled to the node N21via the capacitor230f.

Or, in the present embodiment of the disclosure, a plurality of capacitors are used for generating a plurality of the intermediate signals (for example, the signals at the nodes N21, N23and N25ofFIG. 2). Then, the capacitors are further used for generating output clock signals from the intermediate signals.

InFIG. 1AandFIG. 2, six output clock signals are obtained by performing interpolation on three reference clock signals. Based on the above description, anyone who is skilled in the technology field of the disclosure will understand that in other possible embodiments, n output clock signals may be obtained by performing interpolation on m reference clock signals, wherein m and n are positive integers which are set as n=2m under normal circumstances.

In addition, the levels of the output clock signals are determined according to the operating voltages of the buffer units120and220. Therefore, the levels of the output clock signals may be adjusted by adjusting the operating voltages of the buffer unit120and220. That is, the circuit structures as illustrated inFIG. 1AandFIG. 2according to the embodiment of the present disclosure may also be used as level shifters.

Besides, a multi-phase generator is disclosed in other embodiment of the present disclosure. As indicated inFIG. 3, the multi-phase generator300includes a phase-locked loop (PLL)310, an interpolation circuit (IP)320, a phase selector (PS)330, a multiplexer (MUX)340and a divide-by-4 circuit350.

The phase-locked loop310may provide a multi-phase output signal. Exemplarily but not restrictively, the phase-locked loop310may provide an 8-phase output signal, and the phase-locked loop310is operated under a high-frequency operating environment of 160 picoseconds. The phase difference between the phases of the 8-phase output signal of the phase-locked loop310is 20 ps.

The phase-locked loop310includes a divide-by-2 circuit311, a phase and frequency detector (PFD)312, a charge pump (CP)313, a low-pass filter (LF)314, a voltage controlled oscillator (VCO)315and a divide-by-64 circuit316.

The divide-by-2 circuit311divides the reference signal (for example, 200 MHz) by 2. The phase and frequency detector312detects the phase and frequency of the output signal of the divide-by-2 circuit311and that of the output signal of the divide-by-64 circuit316. The charge pump313outputs a control signal according to the detection result obtained by the phase and frequency detector312. The control signal, after filtered by the low-pass filter314, controls the output signal of the voltage controlled oscillator315. The output signal of the voltage controlled oscillator315is outputted to the phase selector320and the divide-by-64 circuit316. The structure and operation of the phase-locked loop310are not subjected to specific restrictions here.

The interpolation circuit320may be realized by the capacitance phase interpolation circuit of either of two embodiments above disclosed. The interpolation circuit320may perform interpolation on the 8-phase output signal outputted from the phase-locked loop310to obtain a 16-phase output signal, wherein the phase difference between the phases of the 16-phase output signal is 10 ps.

The phase selector340selects a required phase from the 16-phase output signal of the interpolation circuit320. The phase selected by the phase selector340is down-converted to an output signal OUT (for example, 1.6 GHz) by the divide-by-4 circuit350for the convenience of subsequent digital signal processing.

The multiplexer330outputs, for example, a 16-bit control signal according to the control signal CTL (such as 4 bits) to control the selection of the phase selector340.

According to above embodiments of the present disclosure, the multi-phase generator including the capacitance phase interpolation circuit is capable of generating the required multi-phase output signal, and such design is still within the spirit of the present disclosure.

A capacitance phase interpolation method is disclosed in other embodiments of the present disclosure. Firstly, a plurality of reference clock signals are received by a first capacitance phase interpolation unit including a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling. Interpolation is performed by the first capacitance phase interpolation unit and a second capacitance phase interpolation unit. Each of the output clock signals is obtained by performing phase interpolation on all the reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group. A plurality of capacitors in the second capacitance group are in a ring coupling.

Besides, since the capacitor may filter noises, the capacitance phase interpolation circuit of the embodiments of the present disclosure is capable of eliminating noises and reducing interference.

As disclosed in above embodiments of the present disclosure, since the capacitors are in a ring coupling, each output clock signal is obtained by performing phase interpolation on all the reference clock signals, thus the phase interpolation is little affected by process variation and has higher phase precision, and may thus be used in multi-phase generation circuit requiring high precision.

For example, according to the related art, the output clock signal P1may be obtained by performing phase interpolation just on the reference clock signals CLK0and CLK1. If process variation occurs to the capacitor210c, the output clock signals P1obtained thereby may have offset. According to the embodiments of the present disclosure, each output clock signal is obtained by performing phase interpolation on all the reference clock signals. Even if the variation occurs to the capacitor210c, each reference clock signal still may participate in the generation of the output clock signal P1via the ring coupling of capacitors. Therefore, the impact of process variation is lessened, and the offset of the output clock signal P1is reduced.

Besides, each of the capacitors230a˜230fof the second capacitance phase interpolation unit230is coupled between two relevant output points (for example, the capacitor230ais coupled between output points P0and P1), therefore the obtained output clock signal is related to the reference clocks no matter the output clock signal is obtained through interpolation or not. For example, even though generation of the output clock signal P0is not through interpolation while the output clock signal P1is an interpolation result of the first reference clock CLK0and the second reference clock CLK1, the output clock signal P0is still related to the reference clocks. This is the called self-calibration, which avoids the output signal are unsynchronized in high-frequency operation and reduces the phase offset caused by high-frequency effect. The phase offset will affect the precision of phase output.