Memory device with control circuitry for generating a reset signal in read and write modes of operation

A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

BACKGROUND

A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store a data bit. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.

In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into an active phase and a precharge phase, with the active phase being used to read or write one or more memory cells of the array and the precharge phase being used to precharge the bitlines to a precharge voltage in preparation for the next cycle. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.

For a given read or write operation, the corresponding memory cycle is more particularly referred to as a read cycle or a write cycle, respectively. In certain types of memory devices, such as static random access memories (SRAMs), the read and write cycle times are not equal. The read access time is typically longer than the write access time, while the write precharge time is longer than the read precharge time.

As is well known to those skilled in the art, read and write self-time tracking arrangements may be used in order to establish appropriate signal timing for respective read and write operations. Such self-time tracking functionality is often designed to control the read and write signal timing over expected process, voltage and temperature (PVT) variations. This is particularly important for high-speed operations having read and write cycle frequencies in the gigahertz (GHz) range.

A conventional self-time tracking arrangement of this type utilizes a dummy row of memory cells and a dummy column of memory cells, associated with a dummy wordline and a dummy bitline, respectively, with those memory cells being configured in substantially the same manner as the actual memory cells of the memory array. A dummy wordline driver generates a dummy wordline signal for application to the dummy wordline with substantially the same timing as an actual wordline signal applied to an actual wordline of the memory array. The dummy wordline and dummy bitline are also known as a self-time wordline (STWL) and a self-time bitline (STBL), respectively.

In order to permit independent control of the read and write cycle times, self-time tracking circuitry may be separated into two paths, one for read and another for write. This approach is also called dual mode self-time (DMST).

Conventional approaches to reading data from a memory cell include the use of differential sense amplifiers. In a typical conventional arrangement, sense amplifiers are associated with respective columns of the memory array. For each read memory cycle, the sense amplifier is turned on in order to sense data on a corresponding bitline, and then turned off once the sensed data is latched at the sense amplifier output. The sense amplifier is turned on and off responsive to respective logic states of a sense amplifier enable signal. The turning on and turning off of the sense amplifier is also referred to as enabling and disabling the sense amplifier. The use of differential sense amplifiers generally provides faster sensing with lower dynamic power consumption than single-ended sensing arrangements.

However, controlling the timing of the transitions in the sense amplifier enable signal can be problematic, particularly for high-speed read operations. For example, in conventional arrangements, the sense amplifier enable signal may be provided by a sense latch, with the sense latch being set and reset in order to turn on and turn off the sense amplifiers. More particularly, the sense latch may be reset responsive to a pulse of a sense off signal that corresponds to a delayed and inverted version of the sense amplifier enable signal, as returned to the sense latch from a final one of the sense amplifiers. It can be very difficult to accurately control the delay of the sense off signal, particularly over PVT variations. As a result, read memory cycle time is increased, thereby degrading memory access time performance.

SUMMARY

Embodiments of the invention provide, by way of example, memory devices in which read and write reset signals are generated in an accurate and efficient manner. For example, a given such arrangement can allow better control of read and write timing over PVT variations, thereby facilitating high-speed read and write operations.

In one embodiment, a memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

Other embodiments of the invention include but are not limited to methods, integrated circuits and processing devices.

A memory device in accordance with embodiments of the invention may be implemented, for example, as a stand-alone memory device, such as a packaged integrated circuit, or as an embedded memory in a microprocessor or other processing device.

DETAILED DESCRIPTION

Embodiments of the invention will be illustrated herein in conjunction with exemplary semiconductor memory devices having memory arrays and associated control circuitry configured to generate reset signals for read and write modes of operation. It should be understood, however, that embodiments of the invention are more generally applicable to any semiconductor memory device in which improvements in read and write performance are desired, and may be implemented using circuitry other than that specifically shown and described in conjunction with the illustrative embodiments.

FIG. 1shows a block diagram of a memory device100in accordance with an illustrative embodiment of the invention. The memory device100comprises a memory array102. The memory array102comprises a plurality of memory cells105each configured to store a single bit of data. Such memory cells are also referred to herein as “bitcells.” Each cell105is coupled to a corresponding row or wordline115and column or bitline120. The memory array therefore includes a memory cell at each point where a wordline intersects with a bitline. The memory cells of the memory array are illustratively arranged in N columns and M rows. The values selected for N and M in a given implementation will generally depend upon on the data storage requirements of the application in which the memory device is utilized. In some embodiments, one of N and M may have value 1, resulting in an array comprising a single column of memory cells or a single row of memory cells.

Particular ones of the memory cells105of the memory array102can be activated for writing data thereto or reading data therefrom by application of appropriate row and column addresses to respective row decoder125and column decoder130. Other elements of the memory device100include input/output (I/O) circuitry135, an input data buffer140and an output data buffer145. The I/O circuitry135in the present embodiment is assumed by way of example to comprise a plurality of sense amplifiers, such as differential sense amplifiers coupled to respective columns of the memory array102. The operation of these and other memory device elements, such as row decoder125, column decoder130, and buffers140and145, is well understood in the art and will not be described in detail herein.

Although memory array102is identified inFIG. 1as comprising the cells105and their associated wordlines and bitlines115and120, the term “memory array” as used herein is intended to be more broadly construed, and may encompass one or more associated elements such as the row and column decoders125and130, the I/O circuitry135, or the input and output data buffers140and145, or portions thereof.

Also, the wordlines115and bitlines120, although shown as respective single lines inFIG. 1, may each comprise a corresponding pair of differential lines. By way of example, differential bitlines herein may be denoted as BL and BLB. Also, separate read and write wordlines or bitlines may be used, and a given such read or write wordline or bitline may comprise a corresponding pair of differential lines.

The memory device100in one or more of the illustrative embodiments may be assumed to comprise a static random access memory (SRAM) device. However, as indicated previously, the disclosed control circuitry with reset signal generation functionality can be adapted in a straightforward manner for use with other types of memory devices, including, for example, dynamic random access memory (DRAM), electrically erasable programmable ROM (EEPROM), magnetic RAM (MRAM), ferroelectric RAM (FRAM), phase-change RAM (PC-RAM), etc. Also, other types of memory cell configurations may be used. For example, the memory cells105in the memory array102could be multi-level cells each configured to store more than one bit of data. Embodiments of the invention are therefore not limited in terms of the particular storage or access mechanism utilized in the memory device.

The present embodiment of memory device100is configured to avoid one or more of the drawbacks of conventional practice through the use of control circuitry150that is configured to generate reset signals for read and write operations in a manner that provides better control of read and write timing in the memory array102over PVT variations, thereby facilitating high-speed read and write operations.

By way of example, in a read mode of operation a reset signal may be asserted responsive to sensing of a signal transition on a dummy bitline by a dummy sense amplifier and in a write mode of operation the reset signal may be asserted responsive to a signal transition on a dummy wordline return. Assertions of the read signal may comprise respective signal pulses, with the reset signal in the read mode of operation being asserted earlier in time than the reset signal in the write mode of operation. This causes an internal clock signal and one or more additional global signals of the memory array102, such as actual wordline signals, to have shorter pulse widths in the read mode of operation than these signals have in the write mode of operation.

The control circuitry150may comprise signal generation circuitry configured to generate at least one internal clock signal for the memory device100at least in part as a function of the reset signal.

As will be described in greater detail below, in one or more of the illustrative embodiments, the memory device100exhibits shorter read and write memory cycles and lower power consumption, as well as improved overall operating performance, relative to conventional devices.

The memory device100as illustrated inFIG. 1may include other elements in addition to or in place of those specifically shown, including one or more elements of a type commonly found in a conventional implementation of such a memory device. These and other conventional elements, being well understood by those skilled in the art, are not described in detail herein. It should also be understood that the particular arrangement of elements shown inFIG. 1is presented by way of illustrative example only. Those skilled in the art will recognize that a wide variety of other memory device configurations may be used in implementing embodiments of the invention.

Referring now toFIG. 2A, a portion200of theFIG. 1memory device100is shown. In this embodiment, the memory array102includes N pairs of read bitlines120, with one such pair associated with each column of the memory array, and each pair comprising a read bitline BL and its complement BLB. As mentioned previously, the memory array comprises memory cells105arranged in M rows and N columns, from an initial memory cell105-1,1of the first column to a final memory cell105-M,N of the last column.

The control circuitry150in this embodiment comprises a dummy signal multiplexer (DMux)202and an internal clock generator203. The dummy signal multiplexer generates a reset signal that is applied to the internal clock generator203. The internal clock generator203in the present embodiment utilizes the reset signal and an external clock signal CK to generate an internal clock signal CKINT that is used to control timing of read and write operations in the memory device100. The internal clock generator203is further assumed to generate one or more additional clock signals that are utilized by the memory device100, including in the present embodiment a predecoder clock PredecCK, which may be generated using the internal clock signal CKINT.

In the present embodiment, it is assumed that the internal clock signal CKINT has a rising edge that is triggered by a rising edge of the external clock CK, and a falling edge that is triggered by a rising edge of the reset signal, as will be described below in conjunction with the timing diagrams ofFIGS. 5A,5B and5C. Accordingly, the internal clock signal CKINT has a pulse width that is controlled at least in part by the reset signal. Other global signals used in the memory array102, including actual wordline signals WL and the PredecCK signal, are gated by the CKINT signal, and therefore also have pulse widths that are indirectly controlled by the reset signal.

The multiplexer202and internal clock generator203may be viewed individually or collectively as examples of what is more generally referred to herein as “signal generation circuitry.” Of course, other types of signal generation circuitry may be used in this and other embodiments.

The multiplexer202is coupled to a dummy bitline (DBL) and a dummy wordline (DWL), and operates at least in part responsive to an applied control signal, illustratively a read control signal denoted RD. In the present embodiment, the control signal RD has a first logic level for a read mode of operation of the memory device100and a second logic level for a write mode of operation of the memory device100. Thus, for example, the RD signal may be assumed to have a logic “0” level for the read mode of operation and a logic “1” level for the write mode of operation. In other embodiments, different types of control signaling may be used, possibly involving separate read and write control signals. Accordingly, a read control signal may have a first logic level indicative of a read operation being performed and a second logic level indicative of a read operation not being performed, and a separate write control signal may have a first logic level indicative of a write operation being performed and a second logic level indicative of a write operation not being performed. Also, a given memory device may have multiple read modes and multiple write modes, with the control signaling being adjusted to accommodate these multiple modes.

The I/O circuitry135comprises a plurality of output sense amplifiers (SAs)204-1through204-N that are configured to sense stored data associated with respective columns of the memory array102in conjunction with read operations directed to the array. Each of the output sense amplifiers204is configured to sense data associated with a corresponding one of the read bitline pairs. Thus, for example, output sense amplifier204-1is coupled to the read bitline BL1and its complement BLB1of the first read bitline pair120. Similarly, output sense amplifier204-N is coupled to the read bitline BLN and its complement BLBN of the final read bitline pair120. The output sense amplifiers204are therefore implemented as differential sense amplifiers in the present embodiment, although use of differential sense amplifiers should not be viewed as a requirement of embodiments of the invention.

Each of the sense amplifiers204has a corresponding enable input coupled to the dummy wordline DWL, with the enable input illustratively receiving what is referred to herein as a sense amplifier control signal, or more specifically a sense amplifier enable signal, over the dummy wordline DWL. The DWL signal carried by the dummy wordline DWL in the present embodiment is assumed to transition from a logic “0” level to a logic “1” level in order to enable the sense amplifiers204, and to transition from its logic “1” level to its logic “0” level in order to disable the sense amplifiers204, although other types and configurations of sense amplifier control signals may be used in other embodiments.

For example, other embodiments of the present invention may implement separate sense amplifier control signals for respective ones of the sense amplifiers204, in the manner described in U.S. patent application Ser. No. 13/561,673, filed Jul. 30, 2012 and entitled “Memory Device with Separately Controlled Sense Amplifiers,” which is commonly assigned herewith and incorporated by reference herein.

The dummy row and column circuitry160in this embodiment more particularly comprises a dummy row205which includes a plurality of dummy memory cells206-1through206-N, each also denoted as a DROW cell. Each of the dummy memory cells206in the dummy row205is coupled to the dummy wordline DWL. The dummy wordline DWL is further characterized in this embodiment as having a “near” portion in proximity to the first dummy memory cell206-1of the dummy row205, and a “far” portion in proximity to the last dummy memory cell206-N of the dummy row205.

The circuit portion200illustrated inFIG. 2also includes inverters208,210and212, one or more of which may be viewed as comprising part of the control circuitry150. Inverter208is coupled between the far end of the dummy wordline DWL and a dummy wordline return DWL_RET. The dummy wordline return DWL_RET in the present embodiment returns an inverted version of the DWL signal from inverter208at the far end of the dummy wordline DWL back to the multiplexer202. The dummy wordline return DWL_RET is assumed to be implemented as a metal line.

An output of inverter210drives the near end of the dummy wordline DWL, and is configured in the present embodiment to have a driving capability that is substantially the same as that of wordline drivers used to drive respective actual wordlines115of the memory array102.

Inverter212serves in the present embodiment as a dummy sense amplifier, although other types of dummy sense amplifiers may be used in other embodiments. The inverter212has an input coupled to the dummy bitline DBL and an output that provides a dummy sense amplifier detection (DSAD) signal to the multiplexer202.

Each of the dummy memory cells206of the dummy row205is assumed for purposes of the present embodiment to be associated with a corresponding localized dummy row bitline that is not explicitly shown in the figure.

The dummy row and column circuitry160in this embodiment further comprises a dummy column215which includes a plurality of dummy memory cells216. The dummy memory cells216more particularly comprise single or multiple blocks of dummy discharge cells216-1, also denoted DDC, and dummy load cells216-1through216-M, each also denoted as a DLOAD cell. Each of the dummy memory cells216in the dummy column215is coupled to the dummy bitline DBL.

The dummy discharge cell216-1receives the predecoder clock signal PredecCK, which is derived by gating a predecoded address signal with the internal clock signal CKINT. The predecoder clock signal line is assumed to be loaded by a predecoder that is not explicitly shown in the figure, and is also triggered by the internal clock signal CKINT.

The clock signal CKINT is used to generate an actual wordline signal that is not explicitly shown inFIG. 2Abut triggers dummy discharge cell216-1to discharge dummy bitline DBL. The discharge of DBL is detected in the dummy sense amplifier212and utilized to generate the DSAD signal applied to multiplexer202as well as the DWL signal that is sent via inverter210to the dummy memory cells206of dummy row205. The dummy memory cells206, each of which is a replica of an actual memory cell105, are arranged along the DWL signal line so as to ensure that the DWL signal experiences substantially the same horizontal RC loading conditions as an actual wordline signal.

FIG. 2Billustrates one possible embodiment of multiplexer202. In this embodiment, the multiplexer202has a first input coupled to the output of the inverter212and receiving the DSAD signal therefrom, a second input coupled to the dummy wordline return DWL_RET and receiving a DWL_RET signal therefrom that corresponds to the inverted DWL signal provided by inverter208. The multiplexer202has a reset output providing the reset signal as a function of a selected one of the first and second inputs. The multiplexer202further includes a control input that receives the control signal RD, which as indicated above is assumed to be at a logic “0” level for the read mode of operation and is at a logic “1” level for the write mode of operation.

The control signal RD is applied to an input of inverter214in the multiplexer202, in order to generate the complementary signal RDB. The multiplexer202also includes a first tristate inverter216-1coupled between the first input and the reset output, and a second tristate inverter216-2coupled between the second input and the reset output. The first tristate inverter216-1has active high and active low control inputs driven by RDB and RD, respectively, and the second tristate inverter216-2also has active high and active low control inputs, but driven in an opposite manner by RD and RDB, respectively.

The first and second tristate inverters216-1and216-2receive at their respective inputs the DSAD and DWL_RET signals referred to above. In the read mode of operation, the multiplexer202connects the first input to the reset output via the first tristate inverter216-1and disconnects the second input from the reset output via the second tristate inverter216-2, such that the DSAD signal is provided to the reset output. In the write mode of operation, the multiplexer202connects the second input to the reset output via the second tristate inverter216-2and disconnects the first input from the reset output via the first tristate inverter216-1, such that the DWL_RET signal is provided to the reset output.

The multiplexer202in the present embodiment is configured such that assertion of the reset signal will vary depending upon whether a read operation or a write operation is being executed. More particularly, in the read mode of operation the reset signal is asserted responsive to sensing of a signal transition on the dummy bitline DBL by the dummy sense amplifier212as reflected in the DSAD signal, and in the write mode of operation the reset signal is asserted responsive to a signal transition on the dummy wordline return DWL_RET. The reset signal in the read mode of operation therefore has a pulse width that is independent of any delays associated with RC loading on the dummy wordline DWL, and is typically asserted earlier in time than a corresponding reset signal in the write mode of operation, resulting in a shorter pulse width for the CKINT signal and other associated global signals, as will be illustrated in the timing diagrams ofFIG. 5.

As noted above, the internal clock signal CKINT is generated in internal clock generator203using the reset signal provided by the multiplexer202. More particularly, the pulse width of CKINT is determined by the reset signal in the present embodiment, as will be illustrated in the timing diagrams ofFIG. 5. Other global signals such as actual wordline signals WL are gated by CKINT, and so the reset signal indirectly controls the pulse widths of these other global signals as well.

Accordingly, in the read mode of operation, the reset signal is asserted earlier in time, such that WL and other global signals that are controlled at least in part by the reset signal can be returned to their respective low-power or “golden” states sooner than would otherwise be possible, thereby reducing dynamic power consumption in the memory device. Moreover, in the write mode of operation, the reset signal is asserted later in time, thereby increasing the pulse width of the internal clock CKINT, and ensuring that WL and other global signals will have a sufficient write window to successfully complete the writing of data to all of their corresponding memory cells105.

It is to be appreciated that numerous other types and arrangements of multiplexing circuitry may be used to generate the reset signal in control signal150.

Also, the particular configuration of the dummy row205may be altered in other embodiments. For example,FIG. 3shows a circuitry portion300which is generally similar to the circuitry portion200ofFIG. 2but with the DROW cells of dummy row205replaced by respective field effect transistors, and more particularly N-type metal-oxide-semiconductor (NMOS) devices D1through DN, in a dummy row305.

Each such NMOS device D1through DN has its gate coupled to the dummy wordline DWL and to the enable input of a corresponding one of the sense amplifiers204, and its drain and source coupled to a lower supply voltage, illustratively implemented as VSS in the figure.

The NMOS devices D1through DN in this embodiment are each sized to provide a load on the dummy wordline DWL that approximates a load provided on an actual wordline WL by one or more of the memory cells105of the memory array102. Thus, for example, if column multiplexing is used in the memory device102, the NMOS devices D1through DN would each be sized to mimic the collective load associated with multiple memory cells from the respective multiplexed columns.

Another embodiment illustrated inFIG. 4comprises circuitry portion400which is generally similar to the circuitry portion200ofFIG. 2but with the dummy row eliminated altogether. Instead, in this embodiment, as shown more particularly inFIG. 4A, sense amplifiers404-1through404-N have their respective enable inputs coupled to the dummy wordline DWL and are configured to provide a load on the dummy wordline DWL that approximates a load provided on an actual wordline WL by one or more of the memory cells105of the memory array102. As shown inFIG. 4B, an input inverter412-1associated with the enable input of a given one of the sense amplifiers404has its input coupled to the dummy wordline DWL and is sized to provide the load on the dummy wordline DWL that approximates the load provided on the actual wordline WL by the one or more memory cells of the memory array. The input inverter412-1is arranged in series with a second inverter412-2, the output of which represents the SAEN signal to be applied to the enable input of the given sense amplifier. Again, if column multiplexing is used in the memory device102, the input inverters of the respective sense amplifiers404would each be sized to mimic the collective load associated with multiple memory cells from the respective multiplexed columns.

FIGS. 5A and 5Bare timing diagrams illustrating the relationships between various signals in the embodiments ofFIGS. 2,3and4for respective exemplary read and write operations in the memory device100. More particularly, these two timing diagrams show control signal RD, external clock signal CK, internal clock signal CKINT, signals on actual wordline WL and dummy bitline DBL, and the DSAD and reset signals. TheFIG. 5Btiming diagram additionally shows the signals on the dummy wordline DWL and the dummy wordline return DWL_RET, which are not shown in the timing diagram ofFIG. 5A.

With reference to theFIG. 5Atiming diagram, the control signal RD goes low for the read mode, and a rising edge of external clock CK triggers a rising edge of internal clock CKINT. The multiplexer202generates the reset signal from the DSAD signal, which transitions responsive to discharge of the dummy bitline DBL. The rising edge of the reset signal triggers the falling edge of CKINT as indicated, which in turn triggers the falling edge of the actual wordline signal WL.

With reference to theFIG. 5Btiming diagram, the control signal RD goes high for the write mode, and a rising edge of external clock CK again triggers a rising edge of internal clock CKINT. The multiplexer202generates the reset signal from the DWL_RET signal, which transitions after the signal delay associated with the RC loading of the dummy wordline DWL. The rising edge of the reset signal triggers the falling edge of CKINT as indicated, which in turn triggers the falling edge of the actual wordline signal WL.

The timing diagram ofFIG. 5Cshows substantially the same signals of theFIG. 5AandFIG. 5Btiming diagrams, less the control signal RD, and superimposes the two reset signals, as well as two instances of each of the CKINT, WL, DBL and DSAD signals, as generated for the respective read and write modes of operation. It can be seen that the reset signal in the read mode of operation is asserted earlier in time than the reset signal in the write mode of operation. This causes the internal clock signal CKINT and the additional global signal WL to have shorter pulse widths in the read mode of operation than these signals have in the write mode of operation.

In this embodiment, the time difference between assertion of the reset signal in the read mode of operation and assertion of the reset signal in the write mode of operation is given approximately by the additional signal delay associated with RC loading of the dummy wordline DWL, as reflected in the delayed transition of the DWL_RET signal relative to the DWL signal. Accordingly, in deep submicron process technologies, where horizontal RC delay begins to dominate over gate delays at fast process corners, the disclosed techniques serve to increase self-time pulse widths in proportion to horizontal RC delay, thereby ensuring that a sufficient write window is provided for all memory cells105of the memory array102.

It should be noted that generation of a reset signal in a read mode of operation or a write mode of operation as described herein is intended to be broadly construed, so as to encompass, for example, arrangements in which a reset signal is initially asserted while a control signal such as RD is at the logic level associated with a particular mode but the reset signal remains asserted beyond a subsequent transition in the control signal. Accordingly, a reset signal in a read or write mode may be initially asserted in that mode but may have a pulse width that extends beyond a transition to another mode. The disclosed techniques can be adapted in a straightforward manner for use with a wide variety of different reset signals, mode control signals and memory operating modes.

The illustrative embodiments described above provide improved generation of a reset signal in read and write modes of operation of a memory device, allowing global signal pulse widths to be substantially decreased in read mode while also ensuring that these pulse widths are sufficiently wide in write mode to accommodate wordline signal delays attributable to RC loading effects. Arrangements of this type can significantly reduce memory cycle times and dynamic power consumption, thereby improving the overall operating performance of the memory device100.

It is to be appreciated that the particular control circuitry configurations illustrated inFIGS. 2 through 4are presented by way of illustrative example only, and other embodiments may use other types and arrangements of control circuitry. The term “control circuitry” as used herein is therefore intended to be broadly construed, and should not be viewed as being limited to the particular arrangements shown and described in conjunction with the illustrative embodiments.

For example, in one or more of these other embodiments, the conductivity types of at least a subset of the NMOS transistors of the control circuitry may be reversed, and other suitable modifications may be made to the circuitry and associated signaling levels, as would be appreciated by one skilled in the art. Also, other types of sense amplifiers and other memory device components may be used in implementing other embodiments. The term “sense amplifier” as used herein is therefore intended to be broadly construed so as to encompass a wide variety of different arrangements of sensing circuitry.

Embodiments of the invention are particularly well suited for use in high-speed SRAMs and DRAMs, as well as other types of memories that demand high read speeds, such as content-addressable memories (CAMs) and processor register files.

A given memory device configured in accordance with an embodiment of the invention may be implemented as a stand-alone memory device, for example, as a packaged integrated circuit memory device suitable for incorporation into a higher-level circuit board or other system. Other types of implementations are possible, such as an embedded memory device, where the memory may be, for example, embedded into a processor or other type of integrated circuit device which comprises additional circuitry coupled to the memory device. More particularly, a memory device as described herein may comprise, for example, an embedded memory implemented within a microprocessor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other type of processor or integrated circuit device.

FIG. 6shows an embodiment of a processing device600which incorporates the memory device100ofFIG. 1. In this embodiment, the memory device100is coupled to a processor602. The processing device further includes interface circuitry604coupled to the processor602. The processing device600may comprise, for example, a computer, a server or a portable communication device such as a mobile telephone. The interface circuitry604may comprise one or more transceivers for allowing the device600to communicate over a network.

Alternatively, processing device600may comprise a microprocessor, DSP or ASIC, with processor602corresponding to a central processing unit (CPU) and memory device100providing at least a portion of an embedded memory of the microprocessor, DSP or ASIC.FIG. 7shows an example of an arrangement of this type, with processor integrated circuit700incorporating the memory device ofFIG. 1as an embedded memory100′. The embedded memory100′ in this embodiment is coupled to a CPU702. The embedded memory may comprise, for example, a high-speed register file. Numerous alternative embedded memory embodiments are possible.

As indicated above, embodiments of the invention may be implemented in the form of integrated circuits. In fabricating such integrated circuits, identical die are typically formed in a repeated pattern on a surface of a semiconductor wafer. Each die includes a memory device with a memory array, sense amplifiers and control circuitry as described herein, and may include other structures or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered embodiments of this invention.

Again, it should be emphasized that the above-described embodiments of the invention are intended to be illustrative only. For example, other embodiments can use different types and arrangements of memory arrays, memory cell circuitry, sense amplifiers, control circuitry, multiplexing circuitry, signal generation circuitry, transistor conductivity types, reset signals, control signals, modes of operation, and other elements, signals and operating parameters for implementing the described functionality. Also, the various assumptions made in conjunction with describing the illustrative embodiments need not apply in other embodiments. These and numerous other alternative embodiments within the scope of the following claims will be apparent to those skilled in the art.