Technique for improving the quality of digital signals in a multi-level signaling system

A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method comprises encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting the sets of P symbols.

FIELD OF THE INVENTION

The present invention relates generally to multi-level signaling and, more particularly, to a technique for improving the quality of digital signals in a multi-level signaling system.

BACKGROUND OF THE INVENTION

High-speed serial link channels delivering an effective data rate above 5 Gb/s in a backplane environment are subject to significant signal distortion due to inter-symbol interference (ISI). Transmitters and receivers need to compensate most of the signal distortion using very low complexity schemes in order to obtain a target bit error rate (BER) of less than or equal to 10−17at Gb/s rates and under severe power and complexity restrictions. This constrained space presents significant challenges to well-known signal processing and coding techniques, and sub-optimal but efficient alternatives are sometimes needed to fulfill the task.

Attenuation caused by conductor and dielectric losses causes dispersion ISI. Another important ISI component is reflections, which are essentially multipath components of a signal and originate from impedance discontinuities such as those caused by connectors of line cards at both transmit and receive ends. In addition to ISI distortion, cross-talk effects from far and near end adjacent channels is becoming increasingly significant.

To counteract channel attenuation at high bit rates, 4-level pulse amplitude modulation (4-PAM) signaling is often used instead of conventional 2-level pulse amplitude modulation (2-PAM) signaling. That is, in a 2-PAM signaling system, each conductor in the system may carry signals at one of two signal levels (i.e., at either a logic zero level or a logic one level). Thus, in a 2-PAM signaling system, each conductor in the system can only transmit one bit of data at a time. However, in a 4-PAM signaling system, each conductor in the system may carry signals at four different signal levels (i.e., four different symbols). Thus, in a 4-PAM signaling system, each conductor in the system can transmit two bits of data simultaneously at half of the symbol rate for an equivalent bandwidth.

In a 4-PAM signaling system that uses current-based output drivers, the four different signal levels are represented by different current values. For example, the four different current levels may be identified as0i,1i,2i, and3i. Similarly, in a 4-PAM transmission system that uses voltage-based output drivers, the four different signal levels are represented by different voltage values. For example, the four different voltage levels may be identified as 0v, 1v, 2v, and 3v. Both of these types of output drivers are typically connected in a transmission line environment that presents an effective resistance or impedance to the output driver. This transmission line impedance causes the output voltage to change if the output current from the current driver changes, and causes the output current to change if the output voltage from the voltage driver changes.

A 4-PAM signaling system may be used in systems having either differential pairs of signals or single-ended signals referenced to ground. In a 4-PAM signaling system utilizing many single-ended output drivers, it is desirable to maintain the total signal current required to transmit a byte of data (or code word) at a relatively constant current level in comparison to other bytes of data (or code words). If the signal current fluctuates greatly from one byte to the next, current changes flow through power supply connections and cause noise. These current changes occur when using either voltage drivers or current drivers. The noise on the power supply increases in systems that have high data transmission rates and fast edge rate transmitters. This noise on the power supply degrades the voltage margins of the signals.

Understandably, while advantageous in channels with dominant attenuation, 4-PAM signaling systems are more sensitive to reflections and cross-talk than 2-PAM signaling systems due to the reduction in signal margin as a result of carrying more information per symbol. Thus, in cases where high loss and reflections are combined, the advantages of 4-PAM signaling over 2-PAM signaling may be lost.

In order to preserve the advantages of 4-PAM signaling over 2-PAM signaling it would be desirable to eliminate full-swing transitions (FST) between sequential 4-PAM symbols. This could enhance system performance in terms of: 1.) voltage margins (Vm), by reducing peak distortion (PD) via the elimination of one or more worst case sequences; and 2.) timing margins (Tm), especially at outer eyes where FST close eyes the most.

It would also be desirable to secure a minimum density of desirable symbol transitions useful for clock recovery. These clock data recovery (CDR) transitions could prevent continuous phase drifting from an optimum sampling point at the center of an eye in plesiochronous systems with frequency offsets between received data and a local receive clock.

In view of the foregoing, it would be desirable to provide a technique for improving the quality of digital signals in a multi-level signaling system which overcomes the above-described inadequacies and shortcomings in an efficient and cost effective manner.

SUMMARY OF THE INVENTION

According to the present invention, a technique for improving the quality of digital signals in a multi-level signaling system is provided. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method comprises encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting the sets of P symbols.

In accordance with other aspects of this particular exemplary embodiment of the present invention, each set of P symbols may beneficially be formed with Q bits, wherein Q is greater than N. For example, N may equal 8 and Q may equal 10. Alternatively, N may equal 6 and Q may equal 8. Alternatively still, N may equal 16 and Q may equal 20.

In accordance with further aspects of this particular exemplary embodiment of the present invention digital signals may beneficially be transmitted at four signal levels on a single transmission medium. Accordingly, each symbol may then represent two bits. Also, the single transmission medium comprise a number of different configurations such as, for example, a single electrical conductor, a differential pair of electrical conductors, or an optical fiber.

In accordance with still further aspects of this particular exemplary embodiment of the present invention, each set of P symbols may beneficially include at least one transition that is substantially geometrically centered, which is particularly beneficial for clock recovery. Depending upon signal level assignments, only a most significant symbol bit or a least significant symbol bit may beneficially change during such transitions between successive symbol transmissions occurring between adjacent signal levels.

In accordance with additional aspects of this particular exemplary embodiment of the present invention, the method may further beneficially comprise receiving the transmitted sets of P symbols, and then decoding the digital values of N bits from the transmitted sets of P symbols.

In accordance with still additional aspects of this particular exemplary embodiment of the present invention, a first symbol of each set of P symbols may beneficially be selected to ensure that undesirable transitions do not occur between neighboring sets of P symbols. Also, a last symbol of each set of P symbols may beneficially be selected to ensure that undesirable transitions do not occur between neighboring sets of P symbols.

In accordance with still other aspects of this particular exemplary embodiment of the present invention, the corresponding sets of P symbols may beneficially include a first symbol and a second symbol and the digital values may beneficially be encoded by detecting an undesirable transition between the first and second symbols, and then modifying at least one of the first and second symbols to eliminate the undesirable transition. If such is the case, the undesirable transition may corresponds to a full-swing transition between the first and second symbol, wherein the first and second symbols are adjacent symbols within the corresponding sets of P symbols. Also, modifying at least one of the first and second symbols may beneficially comprise inverting an odd number of bits in a first set of P symbols that includes the first and second symbols. Alternatively, when selectively inverting at least one of the first and second symbols does not eliminate the undesirable transition, modifying at least one of the first and second symbols may beneficially comprise encoding at least one of the first and second symbols using a predetermined exception encoding scheme, and then including in the corresponding sets of P symbols an indication that the at least one of the first and second symbols has been encoded using the exception encoding scheme. Alternatively still, when selectively inverting at least one of the first and second symbols eliminates the undesirable transition, modifying at least one of the first and second symbols may beneficially comprise inverting at least one of the first and second symbols, and then including in the corresponding sets of P symbols an indication that the at least one of the first and second symbols has been inverted. If such is the case, a determination as to whether selectively inverting at least one of the first and second symbols eliminates the undesirable transition may beneficially be performed using a lookup table. Also, inverting a symbol may further beneficially comprise performing a bit-wise inversion of all bits within the symbol.

In accordance with yet other aspects of this particular exemplary embodiment of the present invention, the corresponding sets of P symbols may beneficially include a first set of P symbols and the digital values may beneficially be encoded by detecting a lack of a clock recovery transition within the first set of P symbols, and then modifying at least one symbol within the first set of P symbols to induce a clock recovery transition within the first set of P symbols. If such is the case, modifying may further beneficially comprise performing a bit-wise inversion of the at least one symbol of the first set of P symbols. Alternatively, modifying may further beneficially comprise performing a bit-wise inversion of only one symbol of the first set of P symbols.

In accordance with even further aspects of this particular exemplary embodiment of the present invention, the digital values may beneficially be encoded such that a selected symbol in each set of P symbols is limited to a subset of possible symbol choices. If such is the case, the selected symbol may beneficially be a first symbol or a last symbol of the set of P symbols. Also, the subset of possible symbol choices beneficially does not include either a highest signal level or a lowest signal level of the more than two signal levels. Then, the method may further beneficially comprise receiving the transmitted sets of P symbols, decoding the digital values represented by the sets of N bits from the transmitted sets of P symbols, and detecting at least a portion of the selected symbols in the sets of P symbols. If such is the case, detecting at least a portion of the selected symbols may beneficially comprise using the selected symbols to produce framing information corresponding to the sets of P symbols.

In another particular exemplary embodiment, the technique may be realized as at least one signal embodied in at least one carrier wave for transmitting a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the above-described method.

In still another particular exemplary embodiment, the technique may be realized as at least one processor readable carrier for storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the above-described method.

In yet another particular exemplary embodiment, the technique may be realized as an apparatus for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The apparatus comprises an encoder for encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The apparatus also comprises a transmitter for transmitting the sets of P symbols. The apparatus may further comprise a receiver for receiving the transmitted sets of P symbols, and a decoder for decoding the digital values of N bits from the transmitted sets of P symbols. The apparatus may still further comprise additional features similar to those recited above with respect to the above-described method.

The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENT(S)

Referring toFIG. 1A, there is shown a complete transition diagram for a 4-PAM signaling system. This diagram shows all of the possibilities of how a signal at a given signal level may transition to another signal level between adjacent symbols. There are 16 distinct transitions between symbols, including no transition at all.

Referring toFIG. 1B, there is shown a reduced transition diagram for a 4-PAM signaling system wherein full-swing transitions (FST) have been eliminated. There are now 14 distinct transitions between symbols.

The signal level designations shown inFIGS. 1A and 1Bare such that a two-bit binary value is assigned to each signal level (e.g., a Gray code assignment). Each sequential symbol carries this two-bit binary value in a 4-PAM signaling system. It should be noted, however, that the present invention is not limited to signal level designations having Gray code assignments.

Referring toFIG. 2A, there is shown a first group of symbol transitions which are desirable for use in clock recovery in a 4-PAM signaling system. These symbol transitions are desirable because the crossing point of each of the waveforms is geometrically centered between symbols. Each of these symbol transitions has a property where only the most significant bit (MSB) or the least significant bit (LSB) changes from one symbol to the next. This holds true for at least the numeric assignment given to each signal level used in this detailed description. The large MSB symbol transitions are eliminated via full-swing elimination (FSE) coding. Among the remaining six symbol transitions, the small MSB symbol transitions are the most desirable since there is no need to estimate an offset for samplers. Providing an adequate quantity of transitions suitable for clock recovery is a secondary objective of the coding techniques described herein.

Referring toFIG. 2B, there is shown a second group of symbol transitions which are not desirable for use in clock recovery in a 4-PAM signaling system. The four symbol transitions having no value change cannot be used for clock recovery at all. The remaining four symbol transitions are not desirable because the crossing point of each of the waveforms is offset to either side of the geometric center between symbols. Clock recovery using these symbol transitions would pull the optimal sampling point away from the geometric center, potentially in a data dependent manner.

Referring toFIG. 3, there is shown a 4-PAM signaling system100comprising an encoder102, a serializing 4-PAM transmitter104, a deserializing 4-PAM receiver106, and a decoder108. The serializing 4-PAM transmitter104and the deserializing 4-PAM receiver106are interconnected by a pair of signal carrying conductors110.

The encoder102receives parallel input data DIN, and then encodes the received parallel input data DINso as to provide parallel code words to the serializing 4-PAM transmitter104that are organized as MSB code words (M) and LSB code words (L). The MSB code words (M) and the LSB code words (L) together include multiple consecutive symbols. The parallel input data DINis received as a word having x+1 bits. The MSB code words (M) and the LSB code words (L) each have y+1 bits. The encoder102may be implemented with traditional binary logic.

The serializing 4-PAM transmitter104receives the MSB code words (M) and the LSB code words (L) in parallel form from the encoder102. The serializing 4-PAM transmitter104comprises a differential transmitter112for differentially serially transmitting the received multiple consecutive symbols in the MSB code words (M) and the LSB code words (L) over the pair of signal carrying conductors110to the deserializing 4-PAM receiver106.

The deserializing 4-PAM receiver106comprises a differential receiver114for differentially serially receiving the multiple consecutive symbols in the MSB code words (M) and the LSB code words (L) over the pair of signal carrying conductors110from the serializing 4-PAM transmitter104. The differential receiver114then transmits the MSB code words (M) and the LSB code words (L) in parallel form to the decoder108.

The decoder108is the inverse of the encoder102. That is, the decoder108receives the MSB code words (M) and the LSB code words (L) in parallel form from the deserializing 4-PAM receiver106, and then decodes the received MSB code words (M) and the received LSB code words (L) so as to provide parallel output data DOUT. The parallel output data DOUTis provided as a word having x+1 bits. The decoder108may be implemented with traditional binary logic.

At this point it should be noted that, whileFIG. 3shows the serializing 4-PAM transmitter104as having the differential transmitter112and the deserializing 4-PAM receiver106as having the differential receiver114, the present invention is not limited in this regard. That is, the MSB code words (M) and the LSB code words (L) may be transmitted from the serializing 4-PAM transmitter104to the deserializing 4-PAM receiver106in a single-ended manner requiring only a single-ended transmitter and a single-ended receiver. Thus, the serializing 4-PAM transmitter104and the deserializing 4-PAM receiver106may alternatively be interconnected by a single signal carrying conductor instead of the pair of signal carrying conductors110. Alternatively still, in an optical based system, the serializing 4-PAM transmitter104and the deserializing 4-PAM receiver106may be interconnected by an optical fiber capable carrying signals at multiple optical signal levels.

The many embodiments described herein are directed primarily toward the encoder102and the decoder108. These two components work in conjunction with the serializing 4-PAM transmitter104and the deserializing 4-PAM receiver106to provide desirable signal transmission characteristics and/or improve the signal to noise ratio for a given data rate.

One particular exemplary embodiment utilizes a 3-symbol to 4-symbol encoder and a 4-symbol to 3-symbol decoder (i.e., a 3S4S codec implementation). The 3S4S codec implementation utilizes a 3S4S transition-limiting code, which may be used as a basis for more complex codec implementations. The 3S4S transition-limiting code provides a modified 4-PAM sequence which does not have any full-swing transitions. The efficiency of the 3S4S transition-limiting code is 75%. Also, the 3S4S transition-limiting code provides desirable transitions for clock recovery, yielding at least one transition which may be used for clock recovery assuming that the clock recovery system utilizes all of the desirable small MSB symbol transitions discussed above with respect to FIG.2A.

Referring toFIG. 4, there is shown a portion of the 4-PAM signaling system100ofFIG. 3comprising a 3S4S encoder102A, the serializing 4-PAM transmitter104, and the pair of signal carrying conductors110. The 3S4S encoder102A shown inFIG. 4is for implementing a 3S4S transition-limiting code.

Similar toFIG. 3, the 3S4S encoder102A shown inFIG. 4receives parallel input data DIN<5:0>, and then encodes the received parallel input data DIN<5:0> so as to provide parallel code words to the serializing 4-PAM transmitter104that are organized as MSB code words (M<3:0>) and LSB code words (L<3:0>). The MSB code words (M<3:0>) and the LSB code words (L<3:0>) together include multiple consecutive symbols. The parallel input data DIN<5:0> is received as 6-bit word. The MSB code words (M<3:0>) and the LSB code words (L<3:0>) each have 4 bits.

For purposes of showing the dataflow through the 3S4S encoder102A, bit pairs of the input words are assigned letters and an order within the input word. For example, the DIN<5:0> bus is assigned an ‘abc’ bit-pair triplet. Lower case letters are used to designate input data. The M<3:0> bus and the L<3:0> bus together represent output data. The M<3:0> bus represents the MSB's of four consecutive 4-PAM symbols, while the L<3:0> bus represents the LSB's of four consecutive 4-PAM symbols. The symbol representation of the output data is ‘ABCD’, where ‘A’ is the first symbol serially transmitted and ‘D’ is the last symbol serially transmitted. For implementation mapping, the concatenation of {M<0>, L<0>} represents the ‘A’ symbol and the concatenation of {M<3>, L<3>} represents the ‘D’ symbol.

The ‘ABCD’ symbol group is produced by first examining the ‘abc’ input symbol group. If an illegal symbol transition combination is present, then corrective action may be required. The corrective action requires inverting the bits of the ‘b’ symbol. Examples of these illegal combinations are when values 0,2 or 2,0 are present on either or both of the ‘ab’ or ‘bc’ symbol pairs. By inverting the bits (both the MSB and the LSB) of the ‘b’ symbol, the illegal input combination where ‘ab’=0,2 is changed to ‘ab’=0,1, which is legal. One may also choose a method of inverting only the LSB to correct the illegal combinations, but this is not as desirable because this does not provide for clock recovery sequences.

Some input combinations, unaltered, will not support clock recovery transitions when output. These distinct patterns need to be detected and corrected. The method for correcting these patterns is, again, to invert both the MSB and LSB of the ‘b’ symbol.

The ‘D’ output symbol is used as an opcode to indicate whether or not the ‘b’ bits were inverted. For this example, ‘D’ is always odd, represented with values 1 or 3. This is important because the ‘A’ symbol of a subsequent code word will never contain an illegal transition sequence from generated ‘D’ to generated ‘A’ when ‘D’ is odd. Illegal transition sequences from generated ‘C’ to generated ‘D’ are also prevented when ‘D’ is odd.

Referring toFIG. 5, there is shown a 3S4S conversion table. The 3S4S conversion table ofFIG. 5shows that some input combinations provide support for desirable clock recovery (CDR stands for clock data recovery inFIG. 5) symbol pairs. For example, those symbol pairs which contain 13, 31, 01, 10, 32, and 23 provide support for desirable clock recovery symbol pairs. Other input combinations are undesirable for clock recovery and require correction.

Referring toFIG. 6, there is shown a functional diagram of the 3S4S encoder102A shown in FIG.4. Detection functions120and122examine the values of the input symbols to detect whether the symbol pairs are either 2,0 or 0,2. Detection functions124and126cover the eight cases in the table ofFIG. 5which need special attention. In the embodiment illustrated, such special attention cases are encoded using an exception encoding scheme. Detection functions124and126and the associated exception encoding scheme may be implemented using a lookup table or similar circuitry. By using a lookup table for a small portion of the encoding function (e.g., exception cases) while employing a primary encoding scheme that can utilize relatively simple circuitry (e.g., symbol inversion), the circuitry required to perform the encoding function can be implemented in a limited amount of die area. As such, full-swing transitions can be avoided and CDR ensured without undue overhead.

The outputs of all of the detection functions120-126are provided to a logical NOR function128. The output of the logical NOR function128is provided to a selectable bus inversion function130, which generates the ‘B’ output by selectively inverting the ‘b’ bus when the ‘D’ MSB is equal to 0. Inverting the ‘b’ bus causes the values of the bits being transmitted on the bus to be inverted. For example, a symbol representing binary ‘11’ would be altered to a symbol representing binary ‘00’. The output of the logical NOR function128is also used to construct the ‘D’ symbol, as shown. The ‘a’ and ‘c’ inputs are passed directly to the ‘A’ and ‘C’ outputs unchanged.

Referring toFIG. 7, there is shown a functional diagram of a 3S4S decoder108A for use with the 3S4S encoder102A shown inFIGS. 4 and 6. As shown inFIG. 7, the 3S4S decoder108A is quite simple. That is, a selectable bus inversion function140generates the ‘b’ output by selectively inverting the ‘B’ bus when the ‘D’ MSB is equal to 0. Otherwise, ‘B’ passes unchanged to the ‘b’ output when the ‘D’ MSB is equal to 1. Both ‘A’ and ‘C’ pass unchanged to the outputs ‘a’ and ‘c’. The input ‘D’ is discarded.

The 3S4S transition-limiting code as defined above with reference toFIGS. 4-7may be used as a basis for an 8S10S transition-limiting code. Such an 8S10S transition-limiting code may extend the benefits obtained with the 3S4S transition-limiting code, particularly those associated with the correction of 2,0 and 0,2 symbol pairs by symbol inversion and the retention of desirable clock recovery transitions. An 8S10S transition-limiting code also provides a common interface data width (16 bits/20 bits), which increases bandwidth efficiency to 80%. Further, an 8S10S transition-limiting code provides facilities for unique codes for framing and control characters, as discussed in detail below.

Assume an 8S10S transition-limiting code for encoding an input word ‘abcdefgh’ to an output word ‘ABCDEFGHIJ’, wherein the ‘IJ’ symbol pair represents an instruction. That is, the 8S10S transition-limiting code may be formed by first examining the existing properties of the input word ‘abcdefgh’, and then appending the 2-symbol opcode ‘IJ’ for transmission along with the modified word ‘ABCDEFGH’ to form the 10-symbol output word ‘ABCDEFGHIJ’. The 2-symbol opcode ‘IJ’ represents an ‘a’, ‘c’, ‘e’, and ‘g’ symbol inversion (i.e., inversion code or invCode). The ‘a’ symbol inversion also depends upon the value of a previously converted ‘J’ symbol. The 2-symbol opcode ‘IJ’ is assigned values, excluding 0,2 and 2,0 symbol pairs, such that all output codes provide desirable clock recovery transition sequences. This may come through the opcode itself or through corrective actions specified by the opcode.

Thus, the 2-symbol opcode ‘IJ’ represents information that is necessary to perform a basic code translation method (i.e., an M0 translation method). However, since the 0,2 and 2,0 symbol pairs are excluded, there are only 14 combinations of the 2-symbol opcode ‘IJ’ that may be used, and so not all of the invCode values may be directly represented. Accordingly, since the 2-symbol opcode ‘IJ’ is not large enough to fully enumerate all of the invcode values necessary for the M0 translation method, additional methods are necessary to identify the remaining invCode values. These additional methods include a first additional code translation method (i.e., the M1 translation method) and a second additional code translation method (i.e., the M2 translation method). A complete 8S10S encoder chooses symbol codes from a combination of the M0 translation method, the M1 translation method, and the M2 translation method based upon multiplexer selections derived from a predefined ‘IJ’ Table.

Referring toFIG. 8, there is shown an 8S10S encoder150in accordance with an embodiment of the present invention. The 8S10S encoder150comprises an invCode detector152, ‘IJ’ Table logic154, M0 translation method logic156, M1 translation method logic158, M2 translation method logic160, an ‘ABC’ symbol triplet multiplexer162, a ‘DE’ symbol pair multiplexer164, an ‘F’ symbol multiplexer166, a ‘GH’ symbol pair multiplexer168, and an ‘IJ’ symbol pair multiplexer170.

The invCode detector152first examines the input word ‘abcdefgh’ along with the ‘J’ symbol of the previously encoded output word ‘ABCDEFGHIJ’ (“J′” represents the ‘J’ symbol of the previously encoded output word ‘ABCDEFGHIJ’). If any illegal combination of symbols within symbol triplets J′ab, bcd, def, and fgh is encountered, a corresponding bit in the invCode is set to represent the position of the repair necessary. Illegal combinations detected include 20×, 02×, ×02, and ×20, while the repair mechanism involves symbol inversion by changing the middle symbol of a triplet from 0 to 3 or from 2 to 1. This change is made by the M0 translation method logic156.

Referring toFIG. 8A, there is shown a more detailed functional block diagram of the M0 translation method logic156shown in FIG.8. As shown inFIG. 8A, the M0 translation method logic156comprises a plurality of selectable bus inversion functions172. Each of the plurality of selectable bus inversion functions172operates by translating or mapping its respective input symbol to its inverse value when the respective input bit of the invcode is set to 1. For example, when the respective input bit of the invCode is set to 1, input symbol 00 translates or maps to output symbol 11, input symbol 01 translates or maps to output symbol 10, input symbol 10 translates or maps to output symbol 01, and input symbol 11 translates or maps to output symbol 00.

Difficulty arises when the sixteen invCode combinations need to be represented in an available space of fourteen symbol combinations because two of the symbol combinations are illegal (i.e., symbol combinations of 0,2 and 2,0 of the 2-symbol opcode ‘IJ’ are illegal). Also, the ‘IJ’ Table logic154must be carefully designed so that illegal symbol pairings are not introduced by concatenating the 2-symbol opcode ‘IJ’ to the repaired message word. Thus, the ‘IJ’ Table logic154directly encodes the most frequently occurring invCode combinations in order to cover a majority of input words.

Referring toFIG. 9A, all sixteen invCode combinations are shown, along with the number of input words requiring repair for each invCode. As shown inFIG. 9A, the nine most frequently occurring invcode combinations include 0000, 0001, 0010, 0100, 1000, 0011, 0110, 0101, and 1100.

Referring toFIG. 9B, there is shown an ‘IJ’ Table for the ‘IJ’ Table logic154ofFIG. 8in accordance with an embodiment of the present invention. The ‘IJ’ Table logic154operates in accordance with the ‘IJ’ Table shown inFIG. 9Bto generate ‘IJ’ symbols for the nine most frequently occurring invcode combinations, thereby insuring that 61650 of the available 65536 input words are encoded through direct representation of these nine most frequently occurring invcode combinations. Since the symbol combinations of 0,2 and 2,0 are illegal, the remaining seven invcode combinations (i.e., 1001, 1010, 0111, 1110, 1101, 1011, and 1111) need to be represented using the M1 translation method logic158and the M2 translation method logic160.

The M1 translation method logic158generates ‘FGHIJ’ symbols for possible inclusion into output word ‘ABCDEFGHIJ’. The M2 translation method logic160generates ‘DEFIJ’ symbols for possible inclusion into output word ‘ABCDEFGHIJ’. The ‘IJ’ Table logic154also uses the ‘IJ’ Table shown inFIG. 9Bto generate multiplexer selection signals selM1and selM2for determining which symbols are included in output word ‘ABCDEFGHIJ’.

Referring toFIGS. 10A and 10B, there is shown an M1 Table for the M1 translation method logic158. That is, the inputs to the M1 translation method logic158are the input symbols ‘fgh’ and the calculated invcode. The M1 translation method logic158produces the M1 version of output symbols ‘FGH’ and the 2-symbol opcode ‘IJ’. The M1 Table ofFIGS. 10A and 10Bshows the input-to-output mappings of the M1 translation method logic158. These input-to-output mappings are selected to minimize the size of the M1 Table.

Referring toFIGS. 11A and 11B, there is shown an M2 Table for the M2 translation method logic160. That is, the inputs to the M2 translation method logic160are the input symbols ‘def’, the calculated invCode, and the input symbol ‘h’. The M2 translation method logic160produces the M2 version of output symbols ‘DEF’ and the 2-symbol opcode ‘IJ’. The input symbol ‘h’ is used to select between two opcode values which identify that the M2 Table has been used. This ensures that an output 2-symbol opcode ‘IJ’ following an output symbol ‘H’ will not produce an illegal output symbol combination. The M2 Table ofFIGS. 11A and 11Bshows the input-to-output mappings of the M2 translation method logic160. These input-to-output mappings are selected to minimize the size of the M2 Table.

Referring toFIG. 12, there is shown an 8S10S decoder180in accordance with an embodiment of the present invention. The 8S10S decoder180comprises ‘IJ’ Table logic182, M1 translation method logic184, M2 translation method logic186, an invCode multiplexer188, a symbol inversion function190, a ‘de’ symbol pair multiplexer192, an ‘f’ symbol multiplexer194, and a ‘gh’ symbol pair multiplexer196.

The ‘IJ’ Table logic182generates multiplexer selection signals selM1and selM2for controlling the invCode multiplexer188, the ‘de’ symbol pair multiplexer192, the ‘f’ symbol multiplexer194, and the ‘gh’ symbol pair multiplexer196. The ‘IJ’ Table logic182also generates an ‘IJ’ version of the invCode signal for input to the invCode multiplexer188. The ‘IJ’ Table logic182operates in accordance with an ‘IJ’ Table.

Referring toFIG. 13, there is shown an ‘IJ’ Table for the ‘IJ’ Table logic182ofFIG. 12in accordance with an embodiment of the present invention. The ‘IJ’ Table ofFIG. 13shows the mapping from the coded input symbol pair ‘IJ’ to the three output signals (i.e., selm1, selm2, and the ‘IJ’ version of the invCode). When either selM1or selM2is asserted, the ‘IJ’ version of the invcode will not be used. In order to reduce logic complexity, a common value is used in order to provide common logic terms. This is done for the illegal input combinations as well. If one wanted to detect illegal input conditions in the coded input symbol pair ‘IJ’, then an additional output signal from the ‘IJ’ Table could be used which would report an error if the illegal entries were encountered.

The M1 translation method logic184generates an M1 version of the ‘fgh’ symbols for possible inclusion into output word ‘abcdefgh’. The M1 translation method logic184also generates an M1 version of the invCode for input to the invCode multiplexer188. When multiplexer selection signal selM1is asserted, both the M1 version of the invCode and the M1 version of the ‘fgh’ symbols are used to generate the output word ‘abcdefgh’. The M1 translation method logic184ofFIG. 12operates according to the same M1 Table (i.e., the M1 Table shown inFIGS. 10A and 10B) as the M1 translation method logic158of FIG.8.

The M2 translation method logic186generates an M2 version of the ‘def’ symbols for possible inclusion into output word ‘abcdefgh’. The M2 translation method logic186also generates an M2 version of the invcode for input to the invCode multiplexer188. When multiplexer selection signal selM2is asserted, both the M2 version of the invCode and the M2 version of the ‘def’ symbols are used to generate the output word ‘abcdefgh’. The M2 translation method logic186ofFIG. 12operates according to the same M2 Table (i.e., the M2 Table shown inFIGS. 11A and 11B) as the M2 translation method logic160of FIG.8.

The invCode multiplexer188determines which invCode is provided to the symbol inversion function190based upon the states of multiplexer selection signals selM2and selM2. The symbol inversion function190generates inverted output symbols A′, C′, E′, and G′ that are either directly (i.e., A′ and C′) or possibly (i.e., E′ and G′) used to generate the output word ‘abcdefgh’. Based upon the states of multiplexer selection signals selM2and selM2, the ‘de’ symbol pair multiplexer192, the ‘f’ symbol multiplexer194, and the ‘gh’ symbol pair multiplexer196provide ‘de’, ‘f’, and ‘gh’ symbols, respectively, for the output word ‘abcdefgh’.

Referring toFIG. 12A, there is shown a more detailed functional block diagram of the symbol inversion function190shown in FIG.12. As shown inFIG. 12A, the symbol inversion function190comprises a plurality of selectable bus inversion functions198. Each of the plurality of selectable bus inversion functions198operates by translating or mapping its respective input symbol to its inverse value when the respective input bit of the invCode is set to 1. For example, when the respective input bit of the invCode is set to 1, input symbol 00 translates or maps to output symbol 11, input symbol 01 translates or maps to output symbol 10, input symbol 10 translates or maps to output symbol 01, and input symbol 11 translates or maps to output symbol 00.

In an alternative embodiment, the present invention may be realized as a 4S5S transition-limiting code. Referring toFIG. 14, there is shown a 4S5S encoder200for providing such a 4S5S transition-limiting code. The 4S5S encoder200comprises an 8-bit to 10-bit encoder202, look-up table logic204, and a multiplexer206. The 4S5S encoder200receives 8-bit data words and provides 10-bit code words. Both the 8-bit to 10-bit encoder202and the look-up table logic204receive 8-bit data words and provide 10-bit code words. The look-up table logic204also provides a multiplexer selection signal to the multiplexer206. The multiplexer206determines which 10-bit code word is provided as the output 10-bit code word from the 4S5S encoder200based upon the state of the multiplexer selection signal.

The 4S5S encoder200may support several different types of 4S5S encoding in accordance with the present invention. A first type, herein referred to as 4S5S edge stuffing (ES) encoding, utilizes an n-to-n+1-to-n+2 bit domain design technique. In this technique, all 8-bit data words are first converted into 9-bit blocks having even parity by appending one parity bit to the 8-bit data word. It should be noted that the 9-bit blocks may instead have odd parity in accordance with an alternative embodiment of the present invention.

There are 350 total available 10-bit code words which qualify for full-swing elimination (FSE). By appending an even parity bit there are 100 code words which pre-qualify for FSE. Among these 100 code words, 92 code words secure at least one small MSB or LSB transition per a five symbol block. The remaining non-qualified code words either allow full-swing transitions (FST), or there is no useful symbol transition per a five symbol block. In these cases, the violating 9-bit code words are mapped to 10-bit code words by converting the code words to odd parity by flipping an odd number of bits and simultaneously performing FSE. This mapping covers 226 cases.

Direct mapping is applied to the remaining group of 30 data words for which the encoding function does not produce full-swing elimination (FSE) or good clock data recovery (CDR) transitions. There are a total of 114 spare FSE-compliant code words. Out of these 114 code words, 30 code words may be selected for encoding the 30 data words by direct mapping using the look-up table logic204. Out of these 114 spare FSE-compliant code words, there are 98 code words which have at least one small MSB and/or LSB transition. Out of these 98 code words, 30 code words may alternatively be selected for encoding the 30 data words by direct mapping using the look-up table logic204. Out of these 98 code words, there are 56 code words which have at least one small MSB transition. Out of these 56 code words, 30 code words may also alternatively be selected for encoding the 30 data words by direct mapping using the look-up table logic204. Out of these 56 code words, there are 36 code words with DC balance in the [7 9] range where the total sum's range is [0 15]. Out of these 36 code words, 30 code words may still alternatively be selected for encoding the 30 data words by direct mapping using the look-up table logic204.

Referring toFIG. 15, there is shown a logical flow chart for the 8-bit to 10-bit encoder202in the 4S5S encoder200ofFIG. 14for supporting 4S5S edge stuffing (ES) encoding in accordance with an embodiment of the present invention.

Referring toFIG. 16, there is shown a look-up table for the look-up table logic204in the 4S5S encoder200ofFIG. 14for supporting 4S5S edge stuffing (ES) encoding in accordance with an embodiment of the present invention. The look-up table ofFIG. 16may be formed by choosing any 30 of the 98 FSE-compliant code words which have small MSB and/or LSB transitions. It should be noted that the pairings shown in the look-up table ofFIG. 16may be rearranged to optimize and minimize the look-up table logic204.

A second type of 4S5S encoding, herein referred to as 4S5S center stuffing (CS) encoding, differs from 4S5S edge stuffing (ES) encoding in the location of the stuffing bits. That is, unlike 4S5S edge stuffing (ES) encoding, wherein bits are stuffed at the end of a code word, in 4S5S center stuffing (CS) encoding, bits are stuffed in the center of a code word.

Referring toFIG. 17, there is shown a logical flow chart for the 8-bit to 10-bit encoder202in the 4S5S encoder200ofFIG. 14for supporting 4S5S center stuffing (CS) encoding in accordance with an embodiment of the present invention. As shown inFIG. 17, in 4S5S center stuffing (CS) encoding, each bit in the 8-bit uncoded data word (b1, b2, b3, b4, b5, b6, b7, b8) is assigned to a corresponding bit in the 10-bit code word (C1, C2, C3, C4, C5, C6, C7, C8, C9, C10). The two bits that are used for stuffing are C5and C6. Bit C2is always set to 1 so that there are no FSE violations from the previous code word. Bit C5assumes the value of bit b2. Bit C6is set to 0, and the 10-bit code word is progressively checked for FSE and CDR violations. In case of any FSE or CDR violations, bit C6is set to 1, and bits C8and C10are inverted. This process results in 16 cases of FSE and CDR violations, which are encoded by direct mapping using the look-up table logic204.

Referring toFIG. 18, there is shown a look-up table for the look-up table logic204in the 4S5S encoder200ofFIG. 14for supporting 4S5S center stuffing (CS) encoding in accordance with an embodiment of the present invention. It should be noted that the pairings shown in the look-up table ofFIG. 18may be rearranged to optimize and minimize the look-up table logic204.

Referring toFIG. 19, there is shown a 4S5S decoder210for use with the 4S5S encoder200of FIG.14. The 4S5S decoder210comprises an 10-bit to 8-bit decoder212, look-up table logic214, and a multiplexer216. The 4S5S decoder210receives 10-bit code words and provides 8-bit data words. Both the 10-bit to 8-bit decoder212and the look-up table logic214receive 10-bit code words and provide 8-bit data words. The look-up table logic214also provides a multiplexer selection signal to the multiplexer216. The multiplexer216determines which 8-bit data word is provided as the output 8-bit data word from the 4S5S decoder210based upon the state of the multiplexer selection signal.

Referring toFIG. 20, there is shown a logical flow chart for the 10-bit to 8-bit decoder212in the 4S5S decoder210ofFIG. 19for supporting 4S5S edge stuffing (ES) decoding in accordance with an embodiment of the present invention. The look-up table logic214may use the same look-up table for 4S5S edge stuffing (ES) decoding as is used for 4S5S edge stuffing (ES) encoding (e.g., the look-up table shown in FIG.16), but with reverse mapping.

The 4S5S edge stuffing (ES) decoding operation is simply the reverse of the 4S5S edge stuffing (ES) encoding operation. That is, after checking the look-up table logic214for the 30 code words that are encoded by direct mapping using the look-up table logic204, based on the combination of the 9-bit block parity and code word bits C8and C10, the bit-flipping operations are reversed, and code word bits C9and C10are dropped to form the initial 8-bit data word.

Referring toFIG. 21, there is shown a logical flow chart for the 10-bit to 8-bit decoder212in the 4S5S decoder210ofFIG. 19for supporting 4S5S center stuffing (CS) decoding in accordance with an embodiment of the present invention. The look-up table logic214may use the same look-up table for 4S5S center stuffing (CS) decoding as is used for 4S5S center stuffing (CS) encoding (e.g., the look-up table shown in FIG.18), but with reverse mapping.

The 4S5S center stuffing (CS) decoding operation is described as follows. The look-up table logic214is used to first check for the 16 code words that are encoded by direct mapping using the look-up table logic204. Next, data word bit b2is assigned to code word bit C5, and if C6is equal to 1, code word bits C8and C10are inverted. Then, code word bits C5and C6are dropped to form the initial 8-bit data word.

All of the above-described encoding techniques support complete FSE between all output symbol pairs both within and between concatenated code words. For the 8S10S transition-limiting code, all code words except one have at least one CDR transition per a ten symbol block. The two 4S5S transition-limiting codes guarantee at least one transition per a five symbol block. The 8S10S transition-limiting code performs state-dependent encoding requiring a ‘look-behind’ type of operation for the encoder and creating critical path requirements, while the two 4S5S transition-limiting codes are state-independent. In addition, all of the above-described encoding techniques allow the definition of unique control characters without bypassing their primary encoding functions. For example, in the parity-based 4S5S edge stuffing (ES) transition-limiting code, the 10-bit code word 0100000000 is an FSE and CDR compliant code word, unique with respect to all possible concatenations of the assigned code words, so that it can be used for synchronization/framing purposes. Other such 10-bit code words for use for synchronization/framing purposes include 0000000001, 0000000100, 0000000110, 0000001110, 1010100100, 1010101011, 1010101100, 1010101110, and 1110101010.

At this point it should be noted that the two 4S5S transition-limiting codes have a unique property wherein the two outer 4-PAM signal levels are periodically unused. That is, assuming T is the symbol period, every 5T the two outer 4-PAM signal levels (highest and lowest) are not used (i.e., there are no transitions starting from or ending with these two outer 4-PAM signal levels). The periodic non-use of these two outer 4-PAM signal levels allows for their alternative use in framing codewords (i.e., identifying the boundary of a codeword).

At this point it should be noted that improving the quality of transmitted digital signals in accordance with the present invention as described above may involve the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, as described above, specific electronic components may be employed in an encoder, decoder, or other similar or related circuitry for implementing the functions associated with improving the quality of transmitted digital signals in accordance with the present invention as described above. Alternatively, one or more processors operating in accordance with stored instructions may implement the functions associated improving the quality of transmitted digital signals in accordance with the present invention as described above. If such is the case, it is within the scope of the present invention that such instructions may be stored on one or more processor readable carriers (e.g., a magnetic disk), or transmitted to one or more processors via one or more signals.

In summary, to increase robustness of multi-level signaling to reflections and cross-talk, the present invention provides a family of transition-limiting codes that eliminate undesirable transitions, which can include, for example, full-swing transitions and transitions that are not helpful in CDR. Such elimination can be accomplished by modification of one or both of two symbols between which the undesirable transition occurs. Such modification may utilize symbol inversion, inversion of an odd number of bits in a symbol set, lookup tables, or other techniques where some modifications may require special attention. In special attention cases, an exception encoding scheme is utilized to modify symbols that cannot be adequately modified based on a primary modification technique (e.g., symbol inversion).

The transition-limiting codes have very low hardware complexity, which is essential in high-speed serial-link systems. In addition to increasing voltage margins via the elimination of worst case sequences and the reduction of peak distortion, these transition-limiting codes increase timing margins by full-swing elimination, which is another critical aspect of multi-level signaling. Furthermore, these transition-limiting codes guarantee a sufficient number of transitions for clock recovery.

The present invention is not to be limited in scope by the specific embodiments described herein. Indeed, various modifications of the present invention, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such modifications are intended to fall within the scope of the following appended claims. Further, although the present invention has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present invention can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breath and spirit of the present invention as disclosed herein.