FLEXIBLE SRAM PRE-CHARGE SYSTEMS AND METHODS

Embodiments of the present disclosure include techniques for pre-charging an SRAM. A pre-charge signal may be used to apply a pre-charge voltage to bit lines in an SRAM memory bank. Features and advantages of the present disclosure include receiving a pre-charge signal in an SRAM and storing the pre-charge signal. The pre-charge signal may be received and stored on a cycle where the SRAM is performing a memory access. The stored pre-charge signal may be applied on a later cycle. In some embodiments, an SRAM is partitioned into multiple sub-banks, and multiple pre-charge signals are received and stored for different sub-banks. Stored pre-charge signals may be applied to the different sub-banks independently, for example.

BACKGROUND

The present disclosure relates generally to computing, and in particular, to flexible static random access memory (SRAM) pre-charge systems and methods.

SRAM memories typically pre-charge their bit lines to a high-voltage state before a read or write access can take place. When an SRAM's bit lines are in a pre-charged state, the SRAM will typically exhibit more leakage power than in the non-pre-charged state. In addition, multiple large drivers within an SRAM, such as word line drivers, contribute a large amount of the overall SRAM leakage power. To improve power consumption in designs using SRAMs, it is desirable to minimize the time SRAMs are in the high leakage state.

DETAILED DESCRIPTION

Described herein are techniques for pre-charging an SRAM. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of some embodiments. Various embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below and may further include modifications and equivalents of the features and concepts described herein.

Features and advantages of the present disclosure include a mechanism to use an dynamic explicit pre-charge scheme on an SRAM while allowing the system to initiate a pre-charge request to the SRAM while a previous access is in progress on a current within the SRAM. This leads to a reduction in leakage power without adding additional latency to the SRAM access. The techniques described herein may be used with or without grouping SRAMs into “banks” to achieve parallelism as described below.

In some embodiments, an SRAM includes circuitry to (1) pipeline the pre-charge/SRAM access cycles and (2) determine whether to put the SRAM in the low leakage state after a current access or to keep the SRAM in pre-charge state ready for the next access. A pre-charge request can be provided to the SRAM one or more cycles before an SRAM access. However, during an SRAM access, a new pre-charge request for the next access can be provided to the SRAM (e.g., a pipelined pre-charge feature). In some embodiments, the SRAM may further determine whether to keep a header/footer voltage on and pre-charge the bit lines after the current access, or to turn off the header/footer voltage and not to pre-charge the bit lines after the current access in order to put the SRAM in a low leakage state. These techniques provide a flexible solution since the SRAM can dynamically either always keep the pre-charge input asserted or explicitly pre-charge on demand, but without the additional performance penalty to pre-charge.

Additionally, in some embodiments, the SRAM allows for dynamic pre-charging of select memory sub-banks of an SRAM for more granular pre-charging. Further, a pre-charge-reset input (e.g., pre-charge-reset-all) may be provided in the SRAM, which clears the pre-charged SRAM bit lines for all sub-banks, and in some embodiments, the pipelined pre-charge requests inside the SRAM, for example.

FIG.1illustrates an SRAM101according to an embodiment. SRAM101includes an SRAM memory bank111and an SRAM access control circuit110. SRAM memory bank111is configured to store bits of data120(e.g., using latch configured CMOS transistors) and comprises a plurality of bit lines121(e.g., typically 2 bit lines—BL and BL*). SRAM access control circuit110is configured with digital logic circuits for performing operations on SRAM memory bank111, such as reading and writing data to and from an array of bit cells in the memory bank111. Advantageously, SRAM access control circuit110is coupled to the plurality of bit lines121of the SRAM memory bank111to pre-charge the plurality of bit lines121to access the stored bits of data120. SRAM access control circuit110receives and stores a pre-charge signal112. The pre-charge control signal112may be stored to pre-charge bit lines for a subsequent cycle when the SRAM access control circuit110is accessing stored bits of data120in the SRAM memory bank111on a current cycle.

Accordingly, an SRAM circuit may include pre-charge request inputs (Pre-chg IN”) that receive the pre-charge signal. The pre-charge signal may be a digital signal, and in various embodiments may comprise one bit or a plurality of bits, for example. Using the pre-charge signal, the SRAM may assert a pre-charge request when an SRAM access (e.g., read or write) is already in progress, for example.

For instance, SRAM access control circuit110may receive and store a pre-charge signal112to implement any of the following scenarios. When the SRAM access control circuit is not accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal may cause the plurality of bit lines to pre-charge. Similarly, when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal may be stored in the SRAM access control circuit to automatically pre-charge the plurality of bit lines when the current memory access is completed. Alternatively, when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit does not pre-charge the bit lines when the current memory access is completed. Further, when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit may further turn off one or more head switches providing power to a plurality of word lines when the current memory access is completed. An example of a head switch is illustrated further below.

FIG.2illustrates a method of pre-charging an SRAM according to an embodiment. At201, bits of data are stored in an SRAM memory bank comprising a plurality of bit lines. At202, a pre-charge signal for a subsequent cycle is received and stored by an SRAM access control circuit when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle. At203, the bit lines are pre-charged by the SRAM access control circuit based on the pre-charge signal to access the stored bits of data of the SRAM memory bank.

FIG.3illustrates SRAM pre-charging according to another embodiment. During cycle 0301upstream logic302in a system may cause the generation of a pre-charge signal at303. The upstream logic may correspond to an impending memory read or write, for example. The pre-charge signal304is coupled to SRAM309indicating a pre-charge is to occur on a subsequent cycle. SRAM309may be in the process of performing another read or write at the same time the pre-charge signal is received. SRAM309may store the pre-charge signal for use on a later cycle, for example. During cycle 1305information for performing an operation may be provided to the SRAM, such as address, a write command (for writes), read/write control signals, and a memory enable signal, for example. During cycle 2, the memory access operation is carried out on a current cycle (cycle 2) using the pre-charge signal received on a previous cycle.

FIG.4illustrates SRAM circuitry according to an embodiment. This example diagram illustrates SRAM access control circuit401, a word line driver section490and a column491of a memory bank including a pair of bit lines (BL/BL*)450-451and corresponding bit cells460a-x. In this example, a pre-charge signal comprises a 4-bit digital signal (“pre-charge<3:0>”) for pre-charging 4 corresponding sub-banks of a 4-partition memory, which is illustrated below. It is to be understood that other memory partitions may be used in other embodiments. Pre-charge bits may be stored in flip flops (e.g., set-reset flip flops)430-433, for example, and coupled to pre-charge outputs (“pre-charge out*,” active low) that are coupled to particular bit lines.

This example illustrates 2 bit lines450-451coupled to a plurality of bit cells460a-x. A bit cell460acomprises cross coupled inverters410-411coupled to bit lines450-451through NMOS transistors412-413, which are controlled by word line inputs, wL0-x, for example. Inverters each may include 2 transistors. Accordingly, the bit cell inFIG.4is an example of a 6 transistor (6T) bit cell. In this example, a pre-charge output of SRAM access control circuit401is coupled to gates of PMOS transistors420-421, which are coupled between the bit lines450-451and a power supply voltage, Vdd. When pre-charge out*499is high (inactive), PMOS transistors420-422are off and the bit lines are floating. However, during a pre-charge, pre-charge out* is low (active) and PMOS transistors420-422are turned on, connecting the bit lines450-451together and to Vdd, thus pre-charging the bit lines before the word line inputs are applied (at which point the pre-charge is turned off).

FIG.4further shows another aspect of the present disclosure. An SRAM may comprise a word line driver section490comprising inverter configured transistors for each word line (e.g.,403/404and405/406), which are coupled to Vdd through a head switch transistor402. Advantageously, when an access is not going to occur, the head switch may be turned off to further reduce leakage and power consumption. Accordingly, the same pre-charge signal used to control pre-charge may be used to control the head switch to further improve performance of the memory circuit.

In the example inFIG.4, the SRAM access control circuit401further comprises a pre-charge-reset input. Pre-charge reset may be used to clear the pre-charge on plurality of bit lines. In some embodiments, the pre-charge-reset input may further clear pre-charge signals stored in the SRAM access control circuit (e.g., in the FFs). In some embodiments, the pre-charge-reset input further turns off one or more head switches providing power to a plurality of word lines (e.g., deactivating “header_en”).

FIG.5illustrates an SRAM layout according to an embodiment. In various embodiments, SRAM memory banks may be partitioned into multiple sub-banks.FIG.5illustrates a partition comprising four (4) sub-banks510,511,512, and513. A local data input/output bus (LDIO) runs between sub-banks510and511and a LDIO bus runs between sub-banks512and513. Accordingly, the banks are shown as510a-b,511a-b,512a-b, and513a-b(on either side of each LDIO). SRAM access control circuitry may be configured at550, for example. Word line drivers and head switches may be configured in the layout as shown at520and521, for example. In this example the control circuitry may comprise a 4 bit digital pre-charge signal and 4 pre-charge output signals to activate bit lines in different sub-banks510-513, for example. In some embodiments, multiple pre-charge voltages may be applied independently within sub-banks.

FIG.6illustrates an SRAM timing diagram. The following example uses a 6 transistor (6T) bit cell illustrated above. 6T SRAM memories may use column-muxing, such as 4-to-1 or 8-to-1. Typically, only one set of bit lines (such as 1 of 4, or 1 of 8) are being used during a memory operation for a given I/O column of the memory. The other unused sets of bit lines with corresponding word lines asserted would have either true or complement side (BL, BL*) of the bit lines discharged by the bit cells, but the values for those bit lines may not be used (e.g., known as a “dummy read”). Before an SRAM memory access, bit lines are pre-charged before a word line is asserted. During an SRAM idle/ready state, all word lines are de-asserted and the bit lines may be pre-charged so they are ready for the next memory operation. However, bit lines may also be floating in the idle state to save leakage, as long as the bit lines are pre-charged before the next memory access. During a memory access, the word line is asserted, and the bit lines are driven to logic 0 or logic 1 states. For read or dummy read, either the true or complement bit lines are being driven to logic “0” by the memory bit cells. The other bit lines start with pre-charged logic “1” state, and are then held at logic “1” state initially by the bit line capacitance, and later held by bit cells at “weak 1” state, since bit cells drive only “weak 1” through NMOS access transistors. For write operation, the bit lines are driven to logic 0 or logic 1 state by the write drivers coupled to the bit lines (not shown).

Referring toFIG.6, precharge_set_bank<x> input stays asserted. At idle, bit lines are pre-charged (precharge_set_bank<x> asserted causes int_pch_en_rslat_bank<x> to be asserted). When the SRAM is being accessed (e.g., a word line turns on), bit line pre-charge is turned off and bit lines are being driven to logic 0/1. After access, bit lines are pre-charged, since int_pch_en_rslat_bank<x> is asserted.

FIG.7illustrates another SRAM timing diagram. In this example, pre-charge occurs at least one cycle before memory access. For example, pre-charge may occur at 2, 3, or 1 cycles before the memory access cycles, or more generally, the precharge may occur N cycles before the mem_en cycle, where N is any integer greater than or equal to 1. Once a precharge_set_bank is asserted with the rising edge of the clock (clk), the corresponding bit lines are pre-charged. At the clk rising edge, with mem_en asserted int_pch_en_rslat_bank<x> get reseted to logic 0 because precharge_set_bank<x> are not asserted at those cycles. When the SRAM is being accessed (e.g., when the word line turns on), the bit lines are being driven to logic 0/1. After access, int_pch_en_rslat_bank<x> is de-asserted and the bit lines are floating.

FIG.8illustrates yet another SRAM timing diagram. This example illustrates pre-charging for two consecutive memory accesses. The 3 time periods801,802, and803illustrate how the inputs (clk, mem_en, addr<11:10>, and precharge_set_bank<x>) affect the outputs of the internal flip-flops (int_pch_en_rslat_bank<x>), which may be Reset/Set flip-flops, for example. In this particular example, each memory access takes two cycles. So while a memory access is happening, there are three ways to assert a “precharge_set_bank” input. At the clock rising edge with mem_en asserted, if the precharge_set_bank<x> is also asserted, then the corresponding int_pch_en_rslat_bank<x> stays asserted (801and803); otherwise, the corresponding int_pch_en_rslat_bank<x> will be deasserted (802; deasserted in between two clock cycles with mem_en asserted).

Advantageously, in this illustrative example, the timing of the pre-charge signal, here “precharge_set_bank<3>”, controls the timing that the pre-charge voltage is applied to bit lines in the bank, which illustrates the flexibility of the techniques presented herein. During the time period labeled801, clk rising edge occurs with addr A1 asserted and precharge_set_bank<3> stays asserted for two clock cycles. Therefore, the bit line voltage, int_pch_en_rslat_bank<3>, stays asserted until clk rising with addr B1 is asserted. Accordingly, the first clock cycle of precharge_set_bank<3> is associated with access A1, while the second clock cycle of precharge_set_bank<3> is associated with access B1. Time period801is an example of how the second clock cycle of precharge_set_bank<3>, associated with access B1, occurs simultaneously with the mem_en for in-progress access A1.

During the time period labeled802, clk rising edge with addr A2 asserted, since precharge_set_bank<3> is not asserted, therefore, int_pch_en_rslat_bank<3> is de-asserted when word line (A2) is asserted. However, during clk rising edge with precharge_set_bank<3> asserted (in between addr A2 and B2), int_pch_en_rslat_bank<3> gets asserted, and the bit lines are pre-charged to get ready for B2 memory access. Accordingly, the first clock cycle of precharge_set_bank<3> is associated with access A2, while the second clock cycle of precharge_set_bank<3> is associated with access B2. Time period802is an example of how the second clock cycle of precharge_set_bank<3>, associated with access B2, occurs simultaneously with the SRAM bit cell access for in-progress access A2.

During the time period labeled803, precharge_set_bank<3> input is asserted for 3 clock cycles. However, int_pch_en_rslat_bank<3> has the same behavior. Time period803illustrates a combination of801and802. The first clock cycle of precharge_set_bank<3> is associated with access A3, while the second and third clock cycles of precharge_set_bank<3> are associated with access B3. Time period803further illustrates the pipelining of801and802(B3's precharge is asserted during A3's mem_en cycle and A3's sram bitcell access cycle), but also illustrates how the present techniques may keep the precharge input active for multiple cycles for a given request (B3 in this case), if needed.

Further Examples

Each of the following non-limiting features in the following examples may stand on its own or may be combined in various permutations or combinations with one or more of the other features in the examples below. In various embodiments, the present disclosure may be implemented as a processor or method.

Embodiments of the present disclosure include a static random access memory (SRAM) circuit comprising: an SRAM memory bank configured to store bits of data, the SRAM memory bank comprising a plurality of bit lines; and an SRAM access control circuit coupled to the plurality of bit lines of the SRAM memory bank, the SRAM access control circuit configured to pre-charge the plurality of bit lines to access the stored bits of data, wherein the SRAM access control circuit receives and stores a pre-charge signal for a subsequent cycle when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle.

In another embodiment, the present disclosure includes a method of pre-charging an SRAM circuit comprising: storing bits of data in an SRAM memory bank, the SRAM memory bank comprising a plurality of bit lines; receiving and storing, by an SRAM access control circuit, a pre-charge signal for a subsequent cycle when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle; and pre-charging, by the SRAM access control circuit, the plurality of bit lines based on the pre-charge signal to access the stored bits of data of the SRAM memory bank.

In one embodiment, when the SRAM access control circuit is not accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal causes the plurality of bit lines to pre-charge.

In one embodiment, when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal is stored in the SRAM access control circuit to automatically pre-charge the plurality of bit lines when the current memory access is completed.

In one embodiment, when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit does not pre-charge the bit lines when the current memory access is completed.

In one embodiment, when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit further turns off one or more head switches providing power to a plurality of word lines when the current memory access is completed.

In one embodiment, the pre-charge signal comprises one or more bits.

In one embodiment, the SRAM memory bank comprises a plurality of memory sub-banks and the pre-charge signal comprises a corresponding number of bits to independently pre-charge the plurality of memory sub-banks.

In one embodiment, the number of bits is equal to a number of the plurality of memory sub-banks.

In one embodiment, the SRAM access control circuit comprises a plurality of pre-charge signal inputs equal to a number of the plurality of memory sub-banks.

In one embodiment, the SRAM access control circuit comprises a plurality of flip flops for storing the plurality of pre-charge signal inputs equal to the number of the plurality of memory sub-banks.

In one embodiment, the SRAM access control circuit comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines.

In one embodiment, the pre-charge-reset input further clears pre-charge signals stored in the SRAM access control circuit.

In one embodiment, the pre-charge-reset input further turns off one or more head switches providing power to a plurality of word lines.