Clocked all-spin logic circuit

Described is a latch comprising: a first all-spin logic (ASL) device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a clock signal; and a third ASL device coupled to the second ASL device, wherein the first and third ASL devices have respective magnets coupled to a power supply terminal. Described is a flip-flop which comprises: a first ASL device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a first clock signal; a third ASL device coupled to the second ASL device, the third ASL device controllable by a second clock signal, the second clock signal being out of phase relative to the first clock signal; and a fourth ASL device coupled to the third ASL device, wherein the first and fourth ASL devices have respective magnets coupled to a power supply terminal.

CLAIM OF PRIORITY

This application claims the benefit of priority of International Patent Application No. PCT/US2013/059279 filed Sep. 11, 2013, titled “CLOCKEDALL-SPINLOGICCIRCUIT,” which is incorporated by reference in its entirety.

BACKGROUND

To seek a way to continue integrated circuit scaling and make computation more energy efficient, spintronic devices can be used. In spintronic devices, electron spins carry and store the information. One feature of such devices is their non-volatility (i.e., the computational state is preserved even when power to the circuit is turned off). This feature opens a path to normally-off, instantly-on logic chips which consume much less static power and thus are very desirable for mobile systems. Another feature of spintronic devices is that a collective state of particles (rather than individual electrons) experiences switching. Thus, spintronic devices have a much lower limit of switching energy per bit. The supply voltage of a spintronic device may not be related to leakage current and can be reduced to tens of milli-volts. This leads to lower active power.

One example of spintronic devices is all-spin logic (ASL) device. However, while the ASL device operates at low supply voltage (e.g., 10 mV) it has static bias current at its input and output non-magnets. This increases the energy per operation.

DETAILED DESCRIPTION

The embodiments describe ASL devices used to realize synchronous logic latch and flip-flop sequential stage element functions. Clocking of the ASL devices reduces the static current joule heating energy consumption and combines the state element and the logic function. The embodiments also describe clocked ASL devices, different from synchronous ASL circuits. In one embodiment, for a clocked ASL device, every ferromagnet (FM) is coupled to one clock signal in the system. In one embodiment, constant supply voltage may not be used for clocked ASL devices.

FIG. 1illustrates a simple ASL (All-Spin-Logic) device100. The ASL device100includes ferromagnets (FM)101aand101bwith respective terminals. In this example, the respective terminals are coupled to power supply (Vdd). FM101aand FM101bextend in the x-direction (also called first direction). In ASL, each FM (e.g.101a) has the output (“right”) side (e.g., its interface with the channel portion102b) and the input (“left”) side (e.g., its interface with the channel portion102a), separated by spacer104a. Similar structure exists for other ferromagnets (e.g.101b). Spacers104aand104bare made from insulating material. Conducting non-magnetic (NM) metal channels102connect the output side of the previous stage FM and the input side of the next stage FM. Coupled to the right side of each spacer are other NM103aand NM103bwhich are coupled to ground (Vss). In one embodiment, tunneling barrier on the input side can be removed which is easier to fabricate and has a smaller resistance in the spin injection path.

ASL devices operate by spin-polarized currents flowing through a non-magnetic metal channel from the output side of a driving FM, and resulting in spin transfer torque (STT) exerted on the input side of a driven FM. The magnitude and direction of torques determine the final state of magnetization in the driven FMs.

The majority of magnetic moments of electrons in an FM (101aand/or101b) points in the direction of magnetization. The x, y, and z unit vectors inFIG. 1show the positive directions for each axis. The FM dimensions are selected such that its easy and hard axes are x-axis and z-axis, respectively. The magnetization of every FM has two stable states—in either the positive (+x) and negative (−x) direction. When its magnetization points in +x direction, it is treated as logic 1; and when it points in −x direction, it is treated as logic 0. Furthermore, inFIG. 1the non-magnetic metal wires102are channels, and103a/103bare ground leads. Spacers104a/104bprevent currents flowing from one channel (e.g., first portion102a) to the next (i.e., second portion102b). Vdd and Vss are the power supply voltage and the ground voltage, respectively.

The non-reciprocity (i.e., input/output distinction) in ASL devices, for logic implementation, is enabled by placing the ground lead (e.g.,103a) closer to one of the FMs (e.g.,101a). Similarly, FM101bis closer to the ground lead103b. For the portion of the channel102b, the driving FM is101aand the driven FM is101b. Even though the areas of the input and output sides may be designed to be identical, the ground lead (e.g.,103b) is close to the output side of every FM (e.g.,101b). Therefore, the resistance from Vdd to Vss is smaller on the output side (i.e., path through101a,102b, and103b) than on the input side (i.e., path through101b,102b, and103b), and the current is larger at the output side. Thus, the spin-polarized density is larger on the output side than that on the input side. That creates a net spin-polarized current from the output side of the driving FM101ato the input side of the driven FM101b. By these means multiple ASL devices can be cascaded input-to-output, without additional converting stages (i.e., concatenability).

In addition, FMs101aand101bhave two stable, low energy states (e.g., magnetization in +x and −x directions), and spin dissipation causes magnetization to evolve toward the stable states. Therefore, the output of each stage starts in one of these stable states. In other words, the spin signal does not degrade from stage to stage and can be regenerated from relatively small spin-polarized currents if they are above the threshold value determined by the FM energy barrier (i.e., amplification). These properties make ASL devices suitable for logic implementations.

For positive supply voltages, electrons traverse from Vss to Vdd. FMs101a/101bextract electrons from channel102with magnetic moments polarized in the same direction as their magnetization. This leaves the accumulation of spins with opposite magnetic moments in channel102under FMs101a/101b. Due to channel102resistance and the position of the ground lead (103a), the charge current in the output side is much higher than that in the input side. Thus, the accumulated density of spins is higher on the output side. Electrons diffuse from output to the input side and exert STT on the driven FM. If STT is over a certain threshold value, the driven FM magnetization switches to the direction opposite to the driving FM magnetization. Hence, ASL device100shown inFIG. 1operates as an inverter for positive supply voltages. Similarly, for negative supply voltages the device operates as a buffer, and the magnetization of the driven FM follows (“copies”) that of the driving FM.

FIG. 2illustrates an ASL inverter/buffer200. It is pointed out that those elements ofFIG. 2having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. ASL inverter/buffer200is similar to ASL100except for the second ground terminal103bis removed. FM101bis the NOT of FM101afor a positive Vdd (i.e., for positive Vdd, an inverter is formed) and the COPY of FM101afor a negative Vdd (i.e., for negative Vdd, a buffer is formed).

The term “scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology. The term “scaling” generally also refers to downsizing layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slow down) of a signal frequency relative to another parameter, for example, power supply level. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value.

For purposes of the embodiments, the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors also include Tri-Gate and FinFet transistors, Gate All Around Cylindrical Transistors or other devices implementing transistor functionality like carbon nano tubes or spintronic devices. Source and drain terminals may be identical terminals and are interchangeably used herein. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors—BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term “MN” indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term “MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

FIG. 3is a static 3-input ASL logic300, according to one embodiment. It is pointed out that those elements ofFIG. 3having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In this embodiment, the three inputs are formed by FMs301a,301d, and301c. In this embodiment, the three ASL devices are coupled together via a common channel302. In one embodiment, the first ASL device comprises FM301a, spacer304a, and ground terminal303a, where spacer304aprovides a barrier in channel302. In one embodiment, the second ASL device comprises FM301band spacer304b, where spacer304bprovides a barrier in channel302. In one embodiment, the third ASL device comprises FM301d, spacer304d, and ground terminal303d, where spacer304dprovides a barrier in channel302. In one embodiment, output is revived by channel under FM301bwhich has an associated spacer304b.

In the following embodiments, different identifiers are used in different figures but they are previously discussed. For example, FM101ainFIG. 1is same as FM303ainFIG. 3. Likewise, spacer104aofFIG. 1is same as spacer304aofFIG. 3.

ASL logic300forms a majority gate (MG) based ASL device. ASL devices operate based on analog operations (i.e., summation of spin currents at the driven FM), but with the threshold barrier in the driven FM, resolve and regenerate the outputs in digital form (i.e., either of two stable states via magnetization of the driven FM). In one embodiment, MGs with odd number of inputs can be efficiently built.

In one embodiment, the driving FMs (i.e.,301a,301c, and301d) are equivalent. In one embodiment, ground leads (i.e.,303a,303c, and303d) have equal dimensions. In one embodiment, each channel302that connects the corresponding driving FM to the driven FM has the same dimensions as well.

Truth table for ASL MG gate300is given by Table 1. In this embodiment, the majority gates with unequal input channel lengths still function properly, but the tolerable difference in length for its correct functioning may depend on the spin diffusion length (i.e., material dependent).

NAND/AND and NOR/OR gates can be built from 3-input MG300by fixing the magnetization of one driving FM in either positive or negative x-direction, according to one embodiment. When it is fixed in +x direction, 3-input MG300operates as a NOR gate for a positive Vdd and as an OR gate for a negative Vdd. In one embodiment, when magnetization of one driving FM is fixed in −x direction, 3-input MG300operates as a NAND gate for a positive Vdd and as an AND gate for a negative Vdd. The summary for NAND/AND and NOR/OR designs is illustrated in Table 1 where FMin1(i.e.,301a) is regarded as the control while FMin2(i.e.,301c) and FMin3(i.e.,301d) are regarded as logical inputs of the NAND/AND/NOR/OR functions. In one embodiment, by permutation, any of the inputs of the majority gate can serve as the control.

FIG. 4is a static ASL full-adder400, according to one embodiment. It is pointed out that those elements ofFIG. 4having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In one embodiment, static ASL full-adder400comprises five ASL devices with respective ground terminals. In this embodiment, the three inputs (i.e., A, B, and Cin) are formed by FMs401a,401d, and401c, where Cin refers to carry-in input. In this embodiment, the five ASL devices are coupled together via a common channel402. In one embodiment, the first ASL device comprises FM401a, spacer404a, and ground terminal403a, where spacer404aprovides a barrier in channel402. In one embodiment, the second ASL device comprises FM401b, spacer404b, and ground terminal403b, where spacer404bprovides a barrier in channel402. In one embodiment, the third ASL device comprises FM401d, spacer404d, and ground terminal403d, where spacer404dprovides a barrier in channel402. In one embodiment, the fourth ASL device comprises FM401b, spacer404b, and ground terminal403b. In one embodiment, the fifth ASL device comprises FM401e(i.e. Comp. S) and spacer404e.

In one embodiment, ASL400is a one-bit full adder which adds two one-bit inputs (A and B) with an incoming carry Cin, and produces a sum (S) and an outgoing carry Cout as outputs. In one embodiment, Cout becomes logic 1 when at least two of three inputs to a full adder are logic 1. In one embodiment, 3-input MG with the inputs (A, B and Cin) can produce the complementary Cout (i.e., Comp. Cout) for a positive Vdd.

Table 2 demonstrates that the complementary S can be obtained by the 5-input majority gate400with the inputs (A, B, Cin, and two complementary Cout's) for a positive Vdd. In one embodiment, the strength of the complementary Cout can be set to two times the strength of the other inputs (A, B and Cin) by adjusting the length and width of the channel between complementary Cout and S relative to the other channels as quantified by injected spin polarized current.

In one embodiment, one-bit full adder400is reduced to two cascaded 3-input majority gates (MG). In one embodiment, the loopback structure does not impact the input-output isolation in the magnets. In one embodiment, the magnet which serves as an input in channel402is determined by which one of the magnet is the closest to the ground electrode (or lead). In one embodiment, the loopback of the signal of complementary to its input part does not alter the dynamics of the magnet, since it injects spin polarization in the same direction as its own magnetization.

In one embodiment, when input A is set to logic 0, complementary S corresponds to the output of an XNOR (exclusive NOR) gate with the inputs (B and Cin). In one embodiment, when input A is set to logic 1, complementary S corresponds to the output of an XOR (exclusive-OR) gate again with the inputs (B and Cin). In one embodiment, any other random gates can be constructed from the ASL gates proposed in this section. In one embodiment, terminals to FM401a-eare coupled to clock signals instead of constant power supply Vdd.

FIGS. 5A-Cillustrate an ASL latch and its operating stages, according to one embodiment. It is pointed out that those elements ofFIGS. 5A-Chaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Latches are level-sensitive devices. Latches are opaque (i.e., blocking the signal transmission between two consecutive gate stages) when the clock signal is low; and transparent (i.e., transmitting the signal from the previous stage to the next) when the clock signal is high.FIG. 5Aillustrates an ASL latch500, according to one embodiment.FIG. 5Billustrates ASL latch520when clock signal to ASL latch500is at Vss level.FIG. 5Cillustrates ASL latch530when clock signal to ASL latch500is at Vdd level.

In one embodiment, ASL latch500comprises at least three ASL devices with three inputs. In this embodiment, the three inputs are formed by input sides of ferromagnets A501a, L501b, and B501c. In this embodiment, the three ASL devices are coupled together via a common channel502. In one embodiment, the first ASL device comprises FM501a, spacer504a, and ground terminal503a, where spacer504aprovides a barrier in channel502. In one embodiment, the second ASL device comprises FM501b, spacer504b, and ground terminal503b, where spacer504bprovides a barrier in channel502. In one embodiment, the third ASL device comprises FM501c, spacer504c, and ground terminal503c, where spacer504cprovides a barrier in channel502.

In this embodiment, Vclk is the clock signal that periodically changes between Vdd and Vss (e.g., 10 mV and 0V). In one embodiment, A is the last FM501ain the previous stage and B is the first FM501bin the next stage. In one embodiment, when Vclk is low as shown by latch520, FM501bin the middle (i.e., L) does not allow current flowing towards B, and in the meantime it samples the value of A. In one embodiment, when Vclk turns high as shown by latch530, latch530becomes transparent, allowing the data flow from A to B (i.e., from the previous stage to the next stage).

In the embodiments, the clock signals (e.g., Vclk) are generated by a clock buffer (or a clock synthesis circuit). In one embodiment, the clock buffer (not shown) is controllable by a clock gating control signal which is generated by a clock control circuit (not shown). In one embodiment, the clock control circuit can dynamically apply positive, negative, or floating clock signal with controllable phase for the clock buffer to provide to the ferromagnet(s). In one embodiment, the clock control circuit comprises spin-logic devices and/or CMOS devices.

In the embodiments, the power supplies for the FMs are independently controllable. For example, in one embodiment, a control circuit is provided which generates a signal to cause a power supply select circuit to provide a positive, negative, or floating power supply to the FM. In one embodiment, the power supply select circuit comprises spin-logic devices and/or CMOS devices. In one embodiment, the control circuit comprises spin-logic devices and/or CMOS devices. In one embodiment, the clock signals and the power supplies for each of the FMs are provided by a circuit which can be independently controlled or dynamically controlled to provide positive power supply, negative power supply, floating signal, positive clock signal, or negative clock signal to the FMs. In one embodiment, the circuit comprises spin-logic devices and/or CMOS devices.

FIGS. 6A-Cillustrate positive edge-triggered ASL flip-flops and their operating stages, according to one embodiment. It is pointed out that those elements ofFIGS. 6A-Chaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

DFFs (Data flip-flop) are edge-triggered sequencing elements. They transmit the sampled data at the rising or falling edge of the clock signal. A master-slave DFF can be implemented via two back-to-back latches.FIG. 6Aillustrates an ASL DFF600, according to one embodiment.FIG. 6Billustrates ASL DFF620where D1is transparent ad D2is opaque.FIG. 6Cillustrates ASL DFF630where D is opaque and D2is transparent.

In one embodiment, ASL DFF600comprises at least four ASL devices with four inputs. In this embodiment, the four inputs are formed by input sized of ferromagnets A601a, D1601b(which received Vclk1), D2601c(which receives Vclk2), and B601d, where Vclk1and Vclk2which are clock signals with different phases relative to one another. For example, Vclk2is an inverted version of Vclk1. In this embodiment, the four ASL devices are coupled together via a common channel602. In one embodiment, the first ASL device comprises FM601a, spacer604a, and ground terminal603a, where spacer604aprovides a barrier in channel602. In one embodiment, the second ASL device comprises FM601b, spacer604b, and ground terminal603b, where spacer604bprovides a barrier in channel602. In one embodiment, the third ASL device comprises FM601c, spacer604c, and ground terminal603c, where spacer604cprovides a barrier in channel602. In one embodiment, the fourth ASL device comprises FM601d, spacer604d, and ground terminal603d, where spacer604dprovides a barrier in channel602.

In one embodiment, while the master latch is transmitting, the slave latch is not and vice versa. Let's assume at time t=0 the master latch is transmitting and the slave latch is not. Therefore, the master latch starts sampling the previous stage at time t=0. When the master latch turns off and the slave latch starts transmitting, the slave latch gets the last sampled data from the master latch and transmits it to the next stage.

In one embodiment, a master-slave ASL DFF is implemented using two ASL latches coupled in series, where Vclk1(clock signal) is the inverted Vclk2(clock signal), A is the last FM in the previous stage, B is the first FM in the next stage, and D1and D2are the master and slave ASL latches, respectively. DFF shown inFIGS. 6A-Cis a positive edge-triggered DFF because it transmits the sampled data from the previous stage to the next at the rising edge of Vclk.

For example, for the ASL positive edge-triggered DFF with Vclk1and Vclk2of 4 ns period and 50% duty cycle until 2 ns D1is opaque and D2is transparent. Between 2 ns and 4 ns D1transmits the value of A to D2while D2is opaque. After 4 ns D2becomes transparent and transmits the last sampled A to B. In one embodiment, a negative edge-triggered DFF is obtained by interchanging Vclk1and Vclk2.

In one embodiment, the clocking circuitry for sequential ASL elements is built using CMOS logic to generate clocks toggling between Vss and +/−Vdd that is as low as a few or tens of mVs. In one embodiment, CMOS logic (not shown) is used to generate clock phases. In one embodiment, the CMOS logic is powered with high voltage supplies (e.g., 1V). In one embodiment, the voltage swing is lowered to a suitable level for ASL using power-efficient voltage regulator techniques (e.g., switched-capacitor DC-to-DC converter).

FIGS. 7A-Billustrate a pipe-line synchronous ASL logic using positive power supply and clock waveforms, according to one embodiment. It is pointed out that those elements ofFIGS. 7A-Bhaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Synchronous logic operates based on a clock signal. In one embodiment, static ASL gates (i.e., combinational ASL circuits) are coupled with sequential ASL elements to form synchronous ASL circuits. In one embodiment, a sequential ASL element is placed after every combinational ASL circuit that consists of a number of static ASL gates.FIG. 7Ais a pipe-line architecture700with two pipes (i.e., pipe1701and pipe2702) coupled in series, according to one embodiment.

In one embodiment, each pipe-line stage (e.g.,701and702) contains one master ASL latch701c/702c, one slave ASL latch701a/702aand one combinational ASL circuit701b/702b(i.e., cascaded static ASL gates). In one embodiment, the components in the same pipe-line stage are connected to the same supply voltage while the corresponding clocks transition between that supply voltage and Vss. In one embodiment, ASL slave latch701areceives signal A is a controlled by Vclk1. In one embodiment, output of ASL slave latch701ais received by static ASL gates701bwhich operates using positive Vdd. In one embodiment, output C of combinational circuits701bis received by ASL master latch701cwhich operates using Vclk2.FIG. 7Billustrates a plot720with waveforms Vclk1721and Vclk2722. Here, x-axis is time and y-axis is voltage.

In one embodiment, synchronous ASL circuits comprise inverting and non-inverting ASL gates together in a single system when sequencing is provided by ASL DFFs (data flip-flops). In such an embodiment, since the master and slave latches in an ASL DFF are not simultaneously transparent, each combinational stage is isolated from every other combinational stage. In one embodiment, each combinational stage can be connected to either positive or negative supply voltage regardless of the other stages. In one embodiment, the clock signals connected to the master latches toggle between Vss and the supply voltage connected to the previous stage; and the clock signals connected to the slave latches toggle between Vss and the supply voltage connected to the next stage. In addition, the clock signals to the master and slave latches are in opposite phases such that both latches could not turn on during the same phase of the clock.

FIGS. 8A-Billustrate a pipe-line synchronous ASL logic using positive and negative power supplies and clock waveforms, according to one embodiment. It is pointed out that those elements ofFIGS. 8A-Bhaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

FIG. 8Ais a pipe-line architecture800with two pipes (i.e., pipe1801and pipe2802) coupled in series, according to one embodiment. Compared to embodiment ofFIG. 7A, the embodiment ofFIG. 8Auses positive Vdd for pipe1combinational logic701band negative Vdd for pipe2combinational logic702b. In this embodiment, ASL slave latch702aoperates with clock Vclk3and ASL master latch702cwith clock Vclk4, where Vclk3and Vclk4are negative clock signals and out of phase relative to one another. For example, Vclk4is an inverted Vclk3as shown inFIG. 8B.FIG. 8Billustrates a plot820with waveforms Vclk3822and Vclk4821. Here, x-axis is time and y-axis is voltage. In this embodiment, negative supply voltages enable a non-inverting combinational logic stage

FIGS. 9A-Billustrate a pipe-line clocked ASL logic and associated clock waveforms, according to one embodiment. It is pointed out that those elements ofFIGS. 9A-Bhaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In one embodiment, in synchronous ASL circuits (as shown with reference toFIGS. 7A-BandFIGS. 8A-B) only sequential elements are connected to the clock signals, and the other elements are connected to a constant power supply. In clocked ASL devices ofFIGS. 9A-Bevery FM is connected to one clock signal in the system. In one embodiment, no constant supply voltage is used in clocked ASL devices.

FIG. 9Ais a pipe-line architecture900which illustrates a clocked ASL based pipe-line stages901and902concatenated together, according to one embodiment. In this embodiment, combination ASL circuits (i.e., static ASL gates) of pipe1901are coupled to Vclk2. In one embodiment, combination ASL circuits (i.e., static ASL gates) of pipe2902are coupled to Vclk2or Vclk4. In one embodiment, when combination ASL circuits (i.e., static ASL gates) of pipe2902are coupled to Vclk4then slave latch702aof pipe2is coupled to Vclk3and master latch702cof pipe2is coupled to Vclk4. In one embodiment, when combination ASL circuits (i.e., static ASL gates) of pipe2902are coupled to Vclk2then slave latch702aof pipe2is coupled to Vclk1and master latch702cof pipe2is coupled to Vclk2.

In one embodiment, a clocked ASL system can have four different clock signals such that they are based on two pairs of 2-phase clocks. For example, Vclk1, Vlk2, Vclk3, Vclk4, where Vclk2is out of phase relative to Vclk1, and where Vclk3is a negative clock signal and out of phase relative to Vclk4which is also a negative clock signal. In such an embodiment, one pair of the 2-phase clocks toggles between Vss and a positive supply voltage (e.g., Vclk1and Vclk2) while the other pair toggles between Vss and a negative supply voltage (e.g., Vclk3and Vclk4). In one embodiment, the FMs in the same stage can be connected to any one of these four clock signals such that the FMs in adjacent stages are connected to the clock signals that are in the opposite clock phase.

In one embodiment, all FMs in the same stage are connected to the same clock signal. For example, FMs combination circuits701bof pipe1901are connected to Vclk2.FIG. 9Bis a pipe-line architecture920which illustrates two pipes (pipe1921and pipe2922) concatenated with one another. In one embodiment, since all stages are isolated from each other (i.e., two consecutive stages never simultaneously transmit the data), the clocks between stages are distributed in a similar way. For example, combinational circuit (i.e., static ASL gates)701bof921operates on Vclk1to process input A and to generate output E. In this example, combinational circuit (i.e., static ASL gates)702bof922operates on Vclk2which is out of phase relative to Vclk1. In one embodiment, when combinational circuit (i.e., static ASL gates)701bof921operates on Vclk3, combinational circuit (i.e., static ASL gates)702bof922operates on Vclk4.

FIGS. 10A-Bare exemplary embodiments of multi-gate clocked ASL device, according to one embodiment. It is pointed out that those elements ofFIGS. 10A-Bhaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In multi-gate clocked ASL device1000ofFIG. 10A, more than one FM is cascade is clocked by the same clock signal, according to one embodiment. In one embodiment, the multi-gate clocked ASL device1000comprises ten FMs with ten inputs. In one embodiment, first ASL device comprises FM1001a, channel1002, spacer1004a, and ground terminal1003a. In one embodiment, second ASL device comprises FM1001c, channel1002, spacer1004c, and ground terminal1003c. In one embodiment, third ASL device comprises FM1001d, channel1002, spacer1004d, and ground terminal1003d. In this embodiment, FM1001a, FM1001c, and FM1001dare controlled by Vclk1.

In one embodiment, fourth ASL device comprises FM1001b, channel1002, spacer1004b, and ground terminal1003b. In one embodiment, fifth ASL device comprises FM1001e, channel1002, spacer1004e, and ground terminal1003e. In one embodiment, sixth ASL device comprises FM1001f, channel1002, spacer1004f, and ground terminal1003f. In one embodiment, seventh ASL device comprises FM1001g, channel1002, spacer1004g, and ground terminal1003g. In one embodiment, eighth ASL device comprises FM1001h, channel1002, spacer1004h, and ground terminal1003h. In this embodiment, FM1001e, FM1001f, FM1001g, FM1001hare controlled by Vclk1.

In one embodiment, ninth FM comprises FM1001i, channel1002, spacer1004i, ground terminal1003i. In one embodiment, tenth FM comprises FM1001j, channel1002, spacer1004j, ground terminal1003j. In this embodiment, FM1001iand1001jof ninth and tenth ASL devices are controlled by Vclk2. In one embodiment, all FMs in the same stage are connected to the same clock signal. Since all stages are isolated from each other (i.e., two consecutive stages never simultaneously transmit the data), we can distribute the clocks between stages.

In multi-gate clocked ASL device1020ofFIG. 10B, more than one FM is cascade is clocked by the same clock signal, according to one embodiment. In this embodiment, every FM in a consecutive logic stage is cocked by an alternating clock phase. For example, first stage (i.e., first, second and third ASL devices) is controlled by Vclk1, second stage (i.e., fourth, sixth, and seventh ASL devices) is controlled by Vclk2, third stage (i.e., ninth ASL device) is controlled by Vclk3, and fourth stage (i.e., tenth ASL device) is controlled by Vclk4. In this embodiment, FMs of fifth and eighth ASL devices are controlled by Vclk1.

FIG. 11is a 3-input multi-gate ASL logic1100driving an ASL inverter using clocked ASL devices, according to one embodiment. It is pointed out that those elements ofFIG. 11having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In this embodiment, multi-gate ASL logic1100comprises three stages—stage1, stage2, and stage3. In one embodiment, stage1comprises first, second, and third ASL devices. In one embodiment, stage1is controlled by Vclk1. In one embodiment, first ASL device comprises FM1101a, channel1102, ground terminal1103a, spacer1104a, where FM1101ais controlled by Vclk1. In one embodiment, second ASL device comprises FM1101c, channel1102, ground terminal1103c, spacer1104c, where FM1101cis controlled by Vclk1. In one embodiment, third ASL device comprises FM1101d, channel1102, ground terminal1103d, spacer1104d, where FM1101dis controlled by Vclk1.

In one embodiment, second stage comprises fourth ASL device. In one embodiment, fourth ASL device is controlled by Vclk2. In this embodiment, second stage is coupled to first stage. In one embodiment, fourth ASL device comprises FM1101b, channel1102, ground terminal1103b, spacer1104b, where FM1101bis controlled by Vclk2. In one embodiment, third stage comprises fifth ASL device. In one embodiment, fifth ASL device is controlled by Vclk1. In this embodiment, third stage is coupled to second stage. In one embodiment, fifth ASL device comprises FM1101e, channel1102, and spacer1104e, where FM1101eis controlled by Vclk1.

In this embodiment, 3-input MG (multi-gate)1100is driving an inverter. For example, for Vclk1and Vclk2of 4 ns period and 50% duty cycle, until 2 ns only the FM1101bin stage2transmits the signal, so the inverter is in evaluation mode and writes its result into FM1101ein stage3. In one embodiment, between 2 ns and 4 ns FMs1101a,1101c,1101din stages1and3transmit the signal and FM1101bin stage2does not. When 3-input MG1100is in evaluation mode, the result is stored into FM1101bin stage2. After 4 ns again FM1101bin stage2turns on, thereby switching inverter1100on, while the other FMs are off. In the last 2 ns all FMs are on except for the one in stage2.

FIG. 12is a smart device or a computer system or an SoC (system-on-chip) with synchronous and clocked ASL devices, according to one embodiment of the disclosure.FIG. 12is a smart device or a computer system or an SoC (system-on-chip) with the bandgap reference architecture, according to one embodiment of the disclosure. It is pointed out that those elements ofFIG. 12having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

FIG. 12illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In one embodiment, computing device1600represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device1600.

In one embodiment, computing device1600includes a first processor1610with synchronous and/or clocked ASL devices described with reference to embodiments. Other blocks of the computing device1600may also include apparatus with synchronous and/or clocked ASL devices described with reference to embodiments. The various embodiments of the present disclosure may also comprise a network interface within1670such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant or a wearable device.

In one embodiment, processor1610(and/or processor1690) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. Processor1690may be optional. While the embodiment shows two processors, a single or more than two processors may be used. The processing operations performed by processor1610include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device1600to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device1600includes audio subsystem1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device1600, or connected to the computing device1600. In one embodiment, a user interacts with the computing device1600by providing audio commands that are received and processed by processor1610.

Display subsystem1630represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device1600. Display subsystem1630includes display interface1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface1632includes logic separate from processor1610to perform at least some processing related to the display. In one embodiment, display subsystem1630includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller1640represents hardware devices and software components related to interaction with a user. I/O controller1640is operable to manage hardware that is part of audio subsystem1620and/or display subsystem1630. Additionally, I/O controller1640illustrates a connection point for additional devices that connect to computing device1600through which a user might interact with the system. For example, devices that can be attached to the computing device1600might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller1640can interact with audio subsystem1620and/or display subsystem1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem1630includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller1640. There can also be additional buttons or switches on the computing device1600to provide I/O functions managed by I/O controller1640.

Connectivity1670can include multiple different types of connectivity. To generalize, the computing device1600is illustrated with cellular connectivity1672and wireless connectivity1674. Cellular connectivity1672refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)1674refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections1680include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device1600could both be a peripheral device (“to”1682) to other computing devices, as well as have peripheral devices (“from”1684) connected to it. The computing device1600commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device1600. Additionally, a docking connector can allow computing device1600to connect to certain peripherals that allow the computing device1600to control content output, for example, to audiovisual or other systems.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

For example, in one embodiment, an apparatus is provided which comprises: a first ferromagnet; a second ferromagnet coupled to the first ferromagnet, the second ferromagnet controllable by a clock signal; and a third ferromagnet coupled to the second ferromagnet, wherein the first and third ferromagnets have respective magnets coupled to a power supply terminal.

In one embodiment, each of the first, second, and third ferromagents form a first, second, and third all-spin logic (ASL) devices respectively, each of which includes: a magnet with a first terminal, the magnet extending in a first direction; a non-magnet with a second terminal, the non-magnet extending in a second direction different from the first direction; and a non-conductor coupled to the magnet, the non-conductor extending in the second direction to isolate a first portion of a non-magnet interconnect from a second portion of the non-magnet interconnect, the second portion coupled to the magnet and the non-magnet, the non-magnet interconnect extending in the first direction.

In one embodiment, the first terminal is coupled to a power supply terminal for the first ASL device. In one embodiment, the first terminal is coupled to the clock signal for the second ASL device. In one embodiment, the first terminal is coupled to a power supply terminal for the third ASL device. In one embodiment, the second terminal is coupled to ground. In one embodiment, the first terminal for each of the ASL devices is independently controllable to be coupled to a positive power supply, a negative power supply, a floating node, a positive clock signal, or a negative clock signal. In one embodiment, the apparatus further comprises a clock gating control circuit to provide a control signal for independently controlling coupling of the first terminal to a positive power supply, a negative power supply, a floating node, a positive clock signal, or a negative clock signal. In one embodiment, the power supply terminal is coupled to at least one of: a positive power supply; a negative power supply; or a floating node.

In another example, an apparatus is provided which comprises: a first ferromagnet; a second ferromagnet coupled to the first ferromagnet, the second ferromagnet controllable by a first clock signal; a third ferromagnet coupled to the second ferromagnet, the third ferromagnet controllable by a second clock signal, the second clock signal being out of phase relative to the first clock signal; and a fourth ferromagnet coupled to the third ferromagnet, wherein the first and fourth ferromagnets have respective magnets coupled to a power supply terminal.

In one embodiment, each of the first, second, third, and fourth ferromagnet form a first, second, third, and fourth all-spin logic (ASL) devices respectively, each of which include: a magnet with a first terminal, the magnet extending in a first direction; a non-magnet with a second terminal, the non-magnet extending in a second direction different from the first direction; and a non-conductor coupled to the magnet, the non-conductor extending in the second direction to isolate a first portion of a non-magnet interconnect from a second portion of the non-magnet interconnect, the second portion coupled to the magnet and the non-magnet, the non-magnet interconnect extending in the first direction.

In one embodiment, the first terminal is coupled to a power supply terminal for the first ASL device. In one embodiment, the first terminal is coupled to the first clock signal for the second ASL device. In one embodiment, the first terminal is coupled to the second clock signal for the third ASL device. In one embodiment, the first terminal is coupled to a power supply terminal for the fourth ASL device. In one embodiment, the second terminal is coupled to ground. In one embodiment, the first terminal for each of the ASL devices is independently controllable to be coupled to a positive power supply, a negative power supply, a floating node, a positive clock signal, or a negative clock signal. In one embodiment, the apparatus further comprises a clock gating control circuit to provide a control signal for independently controlling coupling of the first terminal to a positive power supply, a negative power supply, a floating node, a positive clock signal, or a negative clock signal. In one embodiment, the power supply terminal is coupled to at least one of: a positive power supply; a negative power supply; or a floating node.

In one embodiment, a pipe-line apparatus with all-spin logic (ASL) devices, the pipe-line apparatus comprising: a first pipe-line stage including: a first sequential unit including ASL devices, with one of the ASL devices having a magnet coupled to a first clock signal; a combinational logic including one or more ASL devices, the combinational logic coupled to the first sequential unit, the combinational logic having one or more magnets coupled to a power supply; and a second sequential unit including ASL devices, with one of the ASL devices having a magnet coupled to a second clock signal, the second sequential unit coupled to the combinational logic. In one embodiment, the pipe-line apparatus further comprises clock buffers to generate first and second clock signals, wherein the second clock signal being out of phase relative to the first clock signal. In one embodiment, the first and second sequential units are one of ASL based latches or ASL based flip-flops. In one embodiment, the pipe-line apparatus further comprises: a second pipe-line stage coupled to the first pipe-line stage.

In one embodiment, wherein the second pipe-line stage comprises: a first sequential unit including ASL devices, with one of the ASL devices having a magnet coupled to a third clock signal; a combinational logic including one or more ASL devices, the combinational logic coupled to the first sequential unit, the combinational logic having one or more magnets coupled to a power supply; and a second sequential unit including ASL devices, with one of the ASL devices having a magnet coupled to a third clock signal, the second sequential unit coupled to the combinational logic. In one embodiment, the power supply to the second pipe-line stage is a negative power supply.

In one embodiment, the pipe-line apparatus further comprises clock buffers to provide the third and fourth clock signals, wherein the third and fourth clock signals to oscillate between a voltage level of the negative power supply and ground. In one embodiment, wherein the power supply to the second pipe-line stage is a positive power supply. In one embodiment, the pipe-line apparatus further comprises clock buffers to provide the third and fourth clock signals, wherein the third and fourth clock signals to oscillate between a voltage level of the positive power supply and ground, wherein the third clock signal has a phase substantially phase aligned to the first clock signal, and wherein the fourth clock signal has a phase substantially aligned to the second clock signal.

In another example, a computer system is provided which comprises: a memory; a processor coupled to the memory, the processor having a latch according to the latch apparatus of the embodiments; and a wireless interface for allowing the processor to communicate with another device.

In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having a flip-flop according to flip-flop apparatus of the embodiments; and a wireless interface for allowing the processor to communicate with another device.

In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having a pipe-line apparatus according to the pipe-line apparatus of the embodiments; and a wireless interface for allowing the processor to communicate with another device.