Phase shifter and wireless communication apparatus

A phase shifter includes a first capacitor connected to a first line to which a first input signal is input, a second capacitor connected to a second line to which a second input signal having a first phase difference with respect to the first input signal is input, and a combining circuit that is connected to the first line and the second line and that outputs a combined signal having a phase determined depending on a first capacitance ratio between the first capacitor and the second capacitor.

BACKGROUND

1. Technical Field

The present disclosure relates to a phase shifter and a wireless communication apparatus.

2. Description of the Related Art

In the field of wireless communication, a beamforming technique is known. In this technique, a phase of a signal transmitted or received via each of a plurality of antennas is adjusted individually for each antenna such that a beam is formed in a desired direction.

As one of methods of achieving a beamforming receiver using a fine Complementary Metal-Oxide-Semiconductor (CMOS) process, it is known to use a phase shifter configured based on a discrete-time analog circuit.

For example, a phase shifter using a discrete-time analog circuit is disclosed in Michiel Soer, Eric Klumperink, Bram Nauta, Frank van Vliet “A 1.5-to-5.0 GHz input-matched+2 dBm P1 dB all-passive switched-capacitor beamforming receiver front-end in 65 nm CMOS”, ISSCC Dig. Tech. Papers, pp. 174-175, February 2012. In this technique, a continuous-time analog signal is converted to a discrete-time analog signal using switches, and the gain of the discrete-time analog signal is adjusted thereby controlling the phase of the discrete-time analog signal.

SUMMARY

However, in this phase shifter described above, a large number of switches for converting a continuous-time analog signal to a discrete-time analog signal are provided in a path of the continuous-time analog signal, and thus it is difficult to achieve a high-speed operation, which makes it difficult to deal with a wideband signal.

One non-limiting and exemplary embodiment provides a phase shifter and a wireless communication apparatus capable of operating at a high speed to deal with a wideband signal.

In one general aspect, the techniques disclosed here feature a phase shifter including a first capacitor connected to a first line to which a first input signal is input, a second capacitor connected to a second line to which a second input signal having a first phase difference with respect to the first input signal is input, and, a combining circuit that is connected to the first line and the second line and that outputs a combined signal having a phase determined depending on a first capacitance ratio between the first capacitor and the second capacitor.

The phase shifter and the wireless communication apparatus based on the techniques disclosed here are capable of operating at a high speed to handle a wideband signal.

General or specific embodiments may be implemented as a system, an apparatus, a method, an integrated circuit, a computer program, or a storage medium or any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a storage medium.

DETAILED DESCRIPTION

Embodiments of the present disclosure are described in detail below with reference to drawings. Note that the embodiments described below are merely examples, and the present disclosure is not limited to these examples.

First Embodiment

Configurations of Transmission Apparatus and Reception Apparatus

FIG. 1Ais a diagram illustrating an example of a configuration of a transmission apparatus1according to a first embodiment of the present disclosure.FIG. 1Bis a diagram illustrating an example of a configuration of a reception apparatus2according to the first embodiment of the present disclosure. Note that in the following description, expressions such as “ . . . er”, “ . . . or” or the like used to indicate constituent elements of the transmission apparatus1or the reception apparatus2may be replaced by other expressions such as “ . . . circuitry”, . . . device”, . . . unit”, . . . module”, or the like.

The transmission apparatus1shown inFIG. 1Aincludes, for example, a digital transmission processing unit10, a D/A (Digital to Analog) converter11, NTanalog transmission processing units12(analog transmission processing units12-1to12-NT), a reference frequency oscillator13, and an LO (Local Oscillator) frequency oscillator14, where NTis an integer greater than or equal to 1.

The analog transmission processing units12-1to12-NThave the same configuration, and thus the analog transmission processing unit12-1is taken as an example in the following description. The analog transmission processing unit12-1includes, for example, a phase shifter15, a transmission mixer (MIX)16, a power amplifier (PA)17, and an antenna18.

The digital transmission processing unit10performs a predetermined digital transmission process including, for example, a coding process and a modulation process on transmission data thereby generating a baseband digital transmission signal, and the digital transmission processing unit10outputs the resultant baseband digital transmission signal to the D/A converter11.

The D/A converter11converts the baseband digital transmission signal to a baseband analog transmission signal. The D/A converter11outputs the baseband analog transmission signal to the analog transmission processing units12-1to12-NT.

The reference frequency oscillator13generates a reference frequency signal fREF_LO1used in generating a local oscillation signal fLO1and outputs it to the LO frequency oscillator14.

The LO frequency oscillator14generates the local oscillation signal fLO1based on the reference frequency signal fREF_LO1and outputs the resultant local oscillation signal fLO1to the transmission mixer16.

The phase shifter15controls the phase of the baseband analog transmission signal. For example, the phase shifter15controls the phase of the baseband analog transmission signal to a phase corresponding to the direction of a beam formed by the transmission apparatus1. The phase shifter15outputs the phase-controlled baseband analog transmission signal to the transmission mixer16. The magnitude of the phase controlled by the phase shifter15is specified, for example, by a not-illustrated control unit.

Note that an example of a configuration and an example of an operation of the phase shifter15will be described later.

The transmission mixer16up-converts the phase-controlled baseband analog transmission signal based on the local oscillation signal fLO1to an RF frequency (radio frequency), and outputs a resultant analog transmission signal up-converted to the RF frequency to the power amplifier17.

The power amplifier17amplifies power of the analog transmission signal up-converted to the RF frequency and outputs the resultant analog transmission signal to the antenna18.

The antenna18radiates the power-amplified analog transmission signal.

The phase shifter15provided in each of the analog transmission processing units12-1to12-NTcontrols the phase of the baseband analog transmission signal such that signals (beams) are controlled so as to be transmitted in desired directions from the antennas18of the respective analog transmission processing units12-1to12-NT.

The reception apparatus2shown inFIG. 1Bincludes, for example, NRanalog reception processing units20(analog reception processing units20-1to20-NR), an A/D (Analog to Digital) converter21, a digital reception processing unit22, a reference frequency oscillator23, and an LO frequency oscillator24where NRis an integer greater than or equal to 1.

The analog reception processing units20-1to20-NRhave the same configuration, and thus the analog reception processing unit20-1is taken as an example in the following description. The analog reception processing unit20-1includes, for example, an antenna25, a low noise amplifier (LNA)26, a reception mixer (MIX)27, and a phase shifter28.

The antenna25receives an analog reception signal with an RF frequency from a not-illustrated transmission apparatus and outputs the received analog reception signal to the low noise amplifier26.

The low noise amplifier26amplifies the received RF-frequency analog reception signal, and outputs the resultant received analog reception signal to the reception mixer27.

The reference frequency oscillator23generates a reference frequency signal fREF_LO2used in generating a local oscillation signal fLO2, and outputs the generated reference frequency signal fREF_LO2to the LO frequency oscillator24.

The LO frequency oscillator24generates the local oscillation signal fLO2based on the reference frequency signal fREF_LO2, and outputs the generated local oscillation signal fLO2to the reception mixer27.

The reception mixer27converts the frequency of the RF-frequency analog reception signal to a baseband analog reception signal based on the local oscillation signal fLO2, and outputs the resultant baseband analog reception signal to the phase shifter28.

The phase shifter28controls the phase of the baseband analog reception signal. For example, the phase shifter28controls the phase of the baseband analog reception signal to a phase corresponding to the direction of the beam formed by the reception apparatus2. The phase shifter28outputs the phase-controlled baseband analog reception signal to the A/D converter21. The phase controlled by the phase shifter28is specified, for example, by a not-illustrated control unit.

That is, the signal input to the A/D converter21is a signal obtained by combining the baseband analog reception signals with the phases controlled by the phase shifters28of the respective analog reception processing units20-1to20-NR. The A/D converter21converts the combined baseband analog reception signal to a baseband digital reception signal, and outputs the resultant baseband digital reception signal to the digital reception processing unit22. Note that in the example shown inFIG. 1B, the baseband analog reception signals with phases controlled by the phase shifters28of the respective analog reception processing units20-1to20-NRare combined together by the single A/D converter21. Alternatively, for example, a plurality of A/D converters21may be provided such that the baseband analog reception signals with phases controlled by the phase shifters28of the respective analog reception processing units20-1to20-NRare individually converted into baseband digital reception signals by the respective A/D converters21. The baseband digital reception signals obtained as a result of being converted by the plurality of A/D converters21may be combined.

The digital reception processing unit22performs a predetermined digital reception process including, for example, a demodulation process and a decoding process and/or the like on the baseband digital reception signal thereby generating reception data and outputs the resultant reception data.

Note that the transmission apparatus1shown inFIG. 1Aand the reception apparatus2shown inFIG. 1Beach have a direct conversion configuration. In the transmission apparatus1or the reception apparatus2according to the first embodiment, one or more mixers may be added, and a process at an intermediate frequency (IF) may be performed.

In a case where the transmission apparatus1shown inFIG. 1Aand the reception apparatus2shown inFIG. 1Bare included in one communication apparatus, the reference frequency signal fREF_LO1and the reference frequency signal fREF_LO2may be shared by the transmission signal processing and the reception signal processing. The reference frequency oscillator13and the reference frequency oscillator23may be shared by the transmission apparatus1and the reception apparatus2, while the LO frequency oscillator14and the LO frequency oscillator24may be shared by the transmission apparatus1and the reception apparatus2.

In the example shown inFIG. 1A, the phase shifter15is disposed between the D/A converter11and the transmission mixer16. However, the present disclosure is not limited to this example. The phase shifter15may be disposed between the transmission mixer16and the power amplifier17, or between the LO frequency oscillator14and the transmission mixer16.

In a case where the phase shifter15is disposed between the transmission mixer16and the power amplifier17, the phase shifter15controls the phase of the analog transmission signal having been subjected to the up-conversion to the RF frequency.

In a case where the phase shifter15is disposed between the LO frequency oscillator14and the transmission mixer16, the phase shifter15controls the phase of the local oscillation signal fLO1. By controlling the phase of the local oscillation signal fLO1, the phase of the analog transmission signal which is up-converted by the transmission mixer16based on the local oscillation signal fLO1is indirectly controlled.

In the example of the reception apparatus2shown inFIG. 1B, the phase shifter28is disposed between the reception mixer27and the A/D converter21. However, the present disclosure is not limited to this example. The phase shifter28may be disposed between the low noise amplifier26and the reception mixer27, or between the LO frequency oscillator24and the reception mixer27.

In a case where the phase shifter28is disposed between the low noise amplifier26and the reception mixer27, the phase shifter28controls the phase of the RF-frequency analog reception signal.

In a case where the phase shifter28is disposed between the LO frequency oscillator24and the reception mixer27, the phase shifter28controls the phase of the local oscillation signal fLO2. By controlling the phase of the local oscillation signal fLO2, the phase of the analog reception signal which is down-converted by the reception mixer27based on the local oscillation signal fLO2is indirectly controlled.

Note that a gain control function (a variable gain amplifier) may be added to the phase shifter15and/or the phase shifter28, or a function of a filter and/or a function of an equalizer may be added to the phase shifter15and/or the phase shifter28. For example, the configuration of the phase shifter15and/or the phase shifter28may be changed to add at least one of functions including the gain control function, the filter function, and the equalizer function. Alternatively, to add the gain control function, a variable gain amplifier may be added. To add the filter function, a filter may be added. To add the equalizer function, an equalizer may be added.

Configuration and Operation of Phase Shifter100

Next, referring toFIG. 2, an example of a configuration of the phase shifter100according to the first embodiment is described below. The phase shifter100described below corresponds to the phase shifter15shown inFIG. 1Aand/or the phase shifter28shown inFIG. 1B.

FIG. 2is a diagram illustrating an example of a configuration of the phase shifter100according to the first embodiment. The phase shifter100shown inFIG. 2includes, for example, a TA (Transconductance Amplifier, voltage-to-current conversion circuit)110-1, a TA110-2, a capacitor120-1, a capacitor120-2, and a combining circuit130.

The input terminal TIN_Iand the input terminal TIN_Qof the phase shifter100are respectively input with the baseband analog signal VIN_Iand the analog signal VIN_Q. The phase shifter100outputs, from an output terminal TOUT, an output signal VOUTobtained as a result of changing the phase of the analog signal VIN_I.

The analog signal VIN_Iand the analog signal VIN_Qrespectively correspond, for example, to an in-phase component (hereinafter, also referred to as an I-component) and a quadrature component (hereinafter also referred to as a Q-component), which are obtained as a result of being converted by a not-illustrated IQ mixer (IQ generation circuit). The phase difference between the analog signal VIN_Iand the analog signal VIN_Qis, for example, 90°. The analog signal VIN_Iand the analog signal VIN_Qinput to the phase shifter100may also be referred to, respectively, as an input signal VIN_Iand an input signal VIN_Q.

In the example described above, a combination of the I-component and the Q-component output by the IQ mixer is used as an input signal. For example, the IQ mixer may be configured to output a four-phase signal including an I-component, a Q-component, an IB-component (a component opposite in phase to the I-component), and a QB-component (a component opposite in phase to the Q-component). In this case, one of four combinations, I and Q, I and QB, IB and Q, and IB and QB may be used as an input signal. Note that the phase difference between two signals input to the phase shifter100is n×π/2 (n is an integer greater than or equal to 1).

Note that a system that includes the TA110-1and the capacitor120-1shown inFIG. 2and that operates in response to an input signal VIN_Imay be called an I-circuit. On the other hand, a system that includes the TA110-2and the capacitor120-2shown inFIG. 2and that operates in response to an input signal VIN_Qmay be called a Q-circuit.

The TA110-1is a voltage-to-current conversion circuit in the I-circuit, and converts the input signal VIN_Ito a current (gm×VIN_I) where gmis a value of the transconductance of the TA110-1.

One of electrodes of the capacitor120-1is connected to the output of the TA110-1, and the other one of the electrodes is connected to GND (that is, grounded). The capacitor120-1has a capacitance value of C1.

The TA110-2is a voltage-to-current conversion circuit in the Q-circuit, and converts the input signal VIN_Qto a current (gm×VIN_Q) where gmis a value of the transconductance of the TA110-2.

One of electrodes of the capacitor120-2is connected to the output of the TA110-2, and the other one of the electrodes is connected to GND (that is, grounded). The capacitor120-2has a capacitance value of C2.

At least one of the capacitor120-1and the capacitor120-2may be is a variable capacitor capable of adjusting the capacitance value.

The combining circuit130calculates the sum or the difference between the electric potentials at the terminals, opposite to the terminals connected to GND, of the respective capacitors120-1and120-2, and outputs the result as the output signal VOUTfrom the output terminal TOUT. The output signal VOUTmay also be referred to as an output voltage signal.

An example of an operation of the phase shifter100is described below. In a case where VIN_I=sin ωt and VIN_Q=cos ωt are input to the phase shifter100, the output signal VOUTis represented by equation (1) where ω is the angular frequency of the input signal and is represented as ω=2πfinusing the frequency finof the input signal.

The magnitude α of the difference in phase between the output signal VOUTand the input signal VIN_I=sin ωt is represented by equation (2).

Equation (2) indicates that the phase of the output signal VOUTis determined by a capacitance ratio. Hereinafter, the magnitude α of the difference in phase between the output signal VOUTand the input signal VIN_Iwill also be referred to as a phase control amount.

In the first embodiment, the phase is controlled according to a theory described below. Note that this theory is employed also in other embodiments.

In a case where the I-circuit in the phase shifter100gives an amplitude A to the input signal VINI=sin ωt, and the Q-circuit gives an amplitude B to the input signal VIN_Q=cos ωt, the output voltage signal VOUTis given by equation (3).
VOUT=Asin ωt+Bcos ωt=√{square root over (A2+B2)} sin(ωt+α)  (3)

In equation (3), A and B each take a real or complex number. Note that A may be represented by a transfer function of the I-circuit, and B may be represented by a transfer function of the Q-circuit.

The phase control amount α is represented by equation (4).

Next, a phase control characteristic of the phase shifter100is described below.FIG. 3is a diagram illustrating an example of a result of simulation of an output waveform output from the phase shifter100according to the first embodiment. InFIG. 3, a horizontal axis represents time, and a vertical axis represents an output voltage. The result of the simulation shown inFIG. 3is for a case where the input signal frequency fin=1 [GHz], the input signal power Pin=−30 [dBm], gm=20 [mS], C1=50 [fF], and C2=50 [fF] or 500 [fF].FIG. 3shows two results obtained for two respective values 50 [fF] and 500 [fF] for C2thereby changing the capacitance ratio between C1and C2.

FIG. 3indicates that the phase of the output signal changes depending on the capacitance ratio. As can be seen fromFIG. 3, it is possible to adjust the phase of the output signal output from the phase shifter100by changing the capacitance ratio of C1to C2.

Furthermore,FIG. 3indicates that the amplitude changes depending on the capacitance ratio. That is,FIG. 3indicates that if the phase of the output signal is changed, then a corresponding change in amplitude of the output signal occurs.

Note that it is assumed that the output from the phase shifter100is connected to an amplifier (for example, a power amplifier17shown inFIG. 1A). By adjusting the amplitude of the signal by the amplifier connected to the output of the phase shifter100, the amplitude of the output signal may be corrected so as to cancel out the change that occurs in response to a change in the phase of the output signal. A variable gain amplifier may be used as the amplifier. Alternatively, the amplifier may be a digital amplifier configured to adjust the output level such that when the amplitude of the output signal is greater than a certain threshold value, the output signal is controlled at a fixed output level.

As described above, in the configuration according to the first embodiment, the phase shifter100includes the two voltage-to-current conversion circuits (110-1and110-2), the two capacitors (120-1and120-2), and the combining circuit130. In the configuration shown inFIG. 2, it is possible to control the phase by controlling the capacitance values, C1and C2, of two capacitors.

The phase shifter100according to the first embodiment has a simple configuration including no switch disposed in series in a signal path, which makes it possible to operate at a high speed to handle a wideband signal.

Furthermore, it is possible to achieve a small variation in capacitance ratio even in the CMOS configuration which is sensitive to a process variation, and/or variations of power supply voltage and temperature. Therefore, by using the phase shifter100according to the first embodiment in which the phase is controlled by the capacitance ratio, it is possible to achieve a phase control with a small deviation from a design value even when the phase shifter100is produced using the CMOS process. Thus, it is possible to reduce or simplify a calibration circuit that adjusts the variation from the design value, which makes it possible to reduce the size and/or consumption power of a wireless communication apparatus.

Second Embodiment

In a second embodiment described below, there is disclosed a continuous time (CT)/discrete time (DT) hybrid type phase shifter obtained by adding a charge sharing circuit to the phase shifter100according to the first embodiment described above. According to the second embodiment, the phase shifter also has the capability of controlling the phase using a control signal input to the charge sharing circuit in addition to the capability of controlling the phase by controlling the capacitance ratio.

Configurations of Transmission Apparatus and Reception Apparatus

FIG. 4Ais a diagram illustrating an example of a configuration of a transmission apparatus3according to the second embodiment of the present disclosure.FIG. 4Bis a diagram illustrating an example of a configuration of a reception apparatus4according to the second embodiment of the present disclosure. Note that in the following description, expressions such as “ . . . er”, “ . . . or” or the like used to indicate constituent elements of the transmission apparatus3or the reception apparatus4may be replaced by other expressions such as “ . . . circuitry”, . . . device”, . . . unit”, . . . module”, or the like.

The transmission apparatus3shown inFIG. 4Aincludes, for example, a digital transmission processing unit10, a D/A converter11, NTanalog transmission processing units32(analog transmission processing units32-1to32-NT), a reference frequency oscillator33, and an LO frequency oscillator14, where NTis an integer greater than or equal to 1.

The analog transmission processing units32-1to32-NThave the same configuration, and thus the analog transmission processing unit32-1is taken as an example in the following description. The analog transmission processing unit32-1includes a phase shifter35, a transmission mixer16, a power amplifier17, and an antenna18.

The digital transmission processing unit10performs a predetermined digital transmission process including, for example, a coding process and a modulation process on transmission data thereby generating a baseband digital transmission signal, and the digital transmission processing unit10outputs the resultant baseband digital transmission signal to the D/A converter11.

The D/A converter11converts the baseband digital transmission signal to a baseband analog transmission signal. The D/A converter11outputs the baseband analog transmission signal to the analog transmission processing units32-1to32-NT.

The reference frequency oscillator33generates a reference frequency signal fREF1used by the phase shifter35, and outputs the resultant reference frequency signal fREF1to the phase shifter35. The reference frequency oscillator33generates a reference frequency signal fREF_LO1used in generating a local oscillation signal fLO1and outputs it to the LO frequency oscillator14. The frequency of the reference frequency signal fREF1output to the phase shifter35and the frequency of the reference frequency signal fREF_LO1output to the LO frequency oscillator14may be or may not be equal to each other.

The LO frequency oscillator14generates the local oscillation signal fLO1based on the reference frequency signal fREF_LO1, and outputs the resultant local oscillation signal fLO1to the transmission mixer16.

The phase shifter35controls the phase of the baseband analog transmission signal using the reference frequency signal fREF1. For example, the phase shifter35controls the phase of the baseband analog transmission signal to a phase corresponding to the direction of a beam formed by the transmission apparatus3. The phase shifter35outputs the phase-controlled baseband analog transmission signal to the transmission mixer16. The phase controlled by the phase shifter35is specified, for example, by a not-illustrated control unit.

Note that a configuration and an operation of the phase shifter35will be described later.

The transmission mixer16up-converts the phase-controlled baseband analog transmission signal to an RF frequency based on the local oscillation signal fLO1, and outputs, to the power amplifier17, the resultant analog transmission signal up-converted to the RF frequency.

The power amplifier17amplifies power of the analog transmission signal up-converted to the RF frequency, and outputs the resultant analog transmission signal to the antenna18.

The antenna18radiates the power-amplified analog transmission signal.

The phase shifter35provided in each of the analog transmission processing units32-1to32-NTcontrols the phase of the baseband analog transmission signal such that signals (beams) are controlled so as to be transmitted in desired directions from the antennas18of the respective analog transmission processing units32-1to32-NT.

The reception apparatus4shown inFIG. 4Bincludes, for example, NRanalog reception processing units40(analog reception processing units40-1to40-NR), an A/D converter21, a digital reception processing unit22, a reference frequency oscillator43, and an LO frequency oscillator24, where NRis an integer greater than or equal to 1.

The analog reception processing units40-1to40-NRhave the same configuration, and thus the analog reception processing unit40-1is taken as an example in the following description. The analog reception processing unit40-1includes, for example, an antenna25, a low noise amplifier26, a reception mixer27, and a phase shifter48.

The antenna25receives an analog reception signal with an RF frequency from a not-illustrated transmission apparatus, and outputs the received analog reception signal to the low noise amplifier26.

The low noise amplifier26amplifies the received RF-frequency analog reception signal, and outputs the received analog reception signal to the reception mixer27.

The reference frequency oscillator43generates a reference frequency signal fREF2used by the phase shifter48, and outputs the resultant reference frequency signal fREF2to the phase shifter48. The reference frequency oscillator43generates a reference frequency signal fREF_LO2used in generating a local oscillation signal fLO2, and outputs the generated reference frequency signal fREF_LO2to the LO frequency oscillator24. The frequency of the reference frequency signal fREF2output to the phase shifter48and the frequency of the reference frequency signal fREF_LO2output to the LO frequency oscillator24may be or may not be equal to each other.

The LO frequency oscillator24generates the local oscillation signal fLO2based on the reference frequency signal fREF_LO2, and outputs the generated local oscillation signal fLO2to the reception mixer27.

The reception mixer27converts the RF-frequency analog reception signal to a baseband analog reception signal by performing a frequency conversion based on the local oscillation signal fLO2, and outputs the resultant baseband analog reception signal to the phase shifter48.

The phase shifter48controls the phase of the baseband analog transmission signal using the reference frequency signal fREF2. For example, the phase shifter48controls the phase of the baseband analog reception signal to a phase corresponding to the direction of the beam formed by the reception apparatus4. The phase shifter48outputs the phase-controlled baseband analog reception signal to the A/D converter21. The phase controlled by the phase shifter48is specified, for example, by a not-illustrated control unit.

The A/D converter21combines the baseband analog reception signals that have been subjected to the phase control performed by the phase shifters48of the respective analog reception processing units40-1to40-NR. The A/D converter21converts the combined baseband analog reception signal to a baseband digital reception signal, and outputs the resultant baseband digital reception signal to the digital reception processing unit22.

The digital reception processing unit22performs a predetermined digital reception process including, for example, a demodulation process and a decoding process and/or the like on the baseband digital reception signal thereby generating reception data, and outputs the resultant reception data.

The transmission apparatus3shown inFIG. 4Aand the reception apparatus4shown inFIG. 4Beach have a direct conversion configuration. In the transmission apparatus3or the reception apparatus4according to the second embodiment, one or more mixers may be added and a process at an intermediate frequency (IF) may be performed.

In a case where the transmission apparatus3shown inFIG. 4Aand the reception apparatus4shown inFIG. 4Bare included in one communication apparatus, two or more of the reference frequency signal fREF_LO1, the reference frequency signal fREF_LO2, the reference frequency signal fREF1, and the reference frequency signal fREF2may be shared by both the transmission signal processing and the reception signal processing. That is, the reference frequency oscillator33and the reference frequency oscillator43may be shared by the transmission apparatus3and the reception apparatus4, and/or the LO frequency oscillator14and the LO frequency oscillator24may be shared by the transmission apparatus3and the reception apparatus4.

In the example of the transmission apparatus3shown inFIG. 4A, the phase shifter35is disposed between the D/A converter11and the transmission mixer16. However, the present disclosure is not limited to this example. The phase shifter35may be disposed between the transmission mixer16and the power amplifier17, or between the LO frequency oscillator14and the transmission mixer16.

In a case where the phase shifter35is disposed between the transmission mixer16and the power amplifier17, the phase shifter35controls the phase of the analog transmission signal having been subjected to the up-conversion to the RF frequency.

In a case where the phase shifter35is disposed between the LO frequency oscillator14and the transmission mixer16, the phase shifter35controls the phase of the local oscillation signal fLO1. By controlling the phase of the local oscillation signal fLO1, the phase of the analog transmission signal which is up-converted by the transmission mixer16based on the local oscillation signal fLO1is indirectly controlled.

In the example of the reception apparatus4shown inFIG. 4B, the phase shifter48is disposed between the reception mixer27and the A/D converter21. However, the present disclosure is not limited to this example. The phase shifter48may be disposed between the low noise amplifier26and the reception mixer27, or between the LO frequency oscillator24and the reception mixer27.

In a case where the phase shifter48is disposed between the low noise amplifier26and the reception mixer27, the phase shifter48controls the phase of the RF-frequency analog reception signal.

In a case where the phase shifter48is disposed between the LO frequency oscillator24and the reception mixer27, the phase shifter48controls the phase of the local oscillation signal fLO2. By controlling the phase of the local oscillation signal fLO2, the phase of the analog reception signal which is down-converted by the reception mixer27based on the local oscillation signal fLO2is indirectly controlled.

The phase shifter35and/or the phase shifter48may be a variable gain amplifier having a gain control function, or a function of a filter and/or a function of an equalizer may be added to the phase shifter35and/or the phase shifter48. For example, the configuration of the phase shifter35and/or the phase shifter48may be changed to add at least one of functions including the gain control function, the filter function, and the equalizer function. Alternatively, to add the gain control function, a variable gain amplifier may be added. To add the filter function, a filter may be added. To add the equalizer function, an equalizer may be added.

Configuration and Operation of Phase Shifter200

Next, referring toFIG. 5, an example of a configuration of the phase shifter200according to the second embodiment is described below. The phase shifter200described below corresponds to the phase shifter35shown inFIG. 4Aand/or the phase shifter48shown inFIG. 4B.

FIG. 5is a diagram illustrating an example of a configuration of the phase shifter200according to the second embodiment. The phase shifter200shown inFIG. 5includes, for example, a TA210-1, a TA210-2, a capacitor220-1, a capacitor220-2, a charge sharing circuit230-1, a charge sharing circuit230-2, a combining circuit240, a clock generator250-1, and a clock generator250-2.

The TA210-1, the TA210-2, the capacitor220-1, the capacitor220-2, and the combining circuit240shown inFIG. 5are respectively similar to the TA110-1, the TA110-2, the capacitor120-1, the capacitor120-2, and the combining circuit130shown inFIG. 2. The capacitance value of the capacitor220-1and the capacitance value of the capacitor220-2are respectively CH1and CH2.

The clock generator250-1generates a control signal CK1-1and a control signal CK2-1using the reference frequency signal fREF1output from the reference frequency oscillator33(seeFIG. 4A) or the reference frequency signal fREF2output from the reference frequency oscillator43(seeFIG. 4B), and the clock generator250-1outputs them to the charge sharing circuit230-1.

The clock generator250-2generates a control signal CK1-2and a control signal CK2-2using the reference frequency signal fREF1output from the reference frequency oscillator33(seeFIG. 4A) or the reference frequency signal fREF2output from the reference frequency oscillator43(seeFIG. 4B), and the clock generator250-2outputs them to the charge sharing circuit230-2.

One of electrodes of the charge sharing circuit230-1is connected to the output of the TA210-1, and the other one of the electrodes is connected to GND (that is, grounded). The charge sharing circuit230-1is input with the control signal CK1-1and the control signal CK2-1generated by the clock generator250-1. Note that one of the control signal CK1-1and the control signal CK2-1may be input to the charge sharing circuit230-1.

One of electrodes of the charge sharing circuit230-2is connected to the output of the TA210-2, and the other one of the electrodes is connected to GND (that is, grounded). The charge sharing circuit230-2is input with the control signal CK1-2and the control signal CK2-2generated by the clock generator250-2. Note that one of the control signal CK1-2and the control signal CK2-2may be input to the charge sharing circuit230-2.

Note that a system that includes the TA210-1, the capacitor220-1, and the charge sharing circuit230-1shown inFIG. 5and that operates to handle an input signal VIN_Imay be called an I-circuit. On the other hand, a system that includes the TA210-2, the capacitor220-2, and the charge sharing circuit230-2shown inFIG. 5and that operates to handle an input signal VIN_Qmay be called a Q-circuit.

Note that the charge sharing circuit230-1and the charge sharing circuit230-2may be generically referred to as a charge sharing circuit230. The clock generator250-1and the clock generator250-2may be generically referred to as a clock generator250. The control signal CK1-1and the control signal CK1-2may be generically referred to as a control signal CK1. The control signal CK2-1and the control signal CK2-2may be generically referred to as a control signal CK2.

Next, an example of the charge sharing circuit230and examples of the control signal CK1and the control signal CK2output from the clock generator250are described below.

FIG. 6Ais a diagram illustrating the charge sharing circuit230according to the second embodiment. The charge sharing circuit230shown inFIG. 6Aincludes, for example, a connection terminal A and a connection terminal B. The charge sharing circuit230is input with the control signal CK1and the control signal CK2generated by the clock generator250. Note that the control signal each may be called a clock. InFIG. 6A, by way of example, the control signal CK1and the control signal CK2are input to the charge sharing circuit230. However, one of the control signal CK1and the control signal CK2may be input to the charge sharing circuit230.

FIG. 6Bis a diagram illustrating an example of a control signal input to the charge sharing circuit230illustrated by way of example inFIG. 6A. InFIG. 6B, a horizontal axis represents time and a vertical axis represents an amplitude. The duty ratio (=pulse width Ts/repetition period TCKof control signal) is 1/2 for both the control signal CK1and the control signal CK2. The control signal CK2is a signal with a phase different by 180° with respect to the phase of the control signal CK1. The clock frequency fCK(fCK=1/TCK) of each of the control signal CK1and the control signal CK2may be or may not be equal to the frequency of the reference frequency signal (fREF).

In the following description, a time period in which the control signal CK1is at a “high” level shown inFIG. 6Bmay be referred to as a high level period of the control signal CK1, and a time period in which the control signal CK1is at a “low” level shown inFIG. 6Bmay be referred to as a low level period of the control signal CK1. Similarly, a time period in which the control signal CK2is at a “high” level and a time period in which the control signal CK2is at a “low” level may be respectively referred to as a high level period and a low level period of the control signal CK2.

First Example of Charge Sharing Circuit230

FIG. 7Ais a diagram illustrating a first example of the charge sharing circuit230according to the second embodiment. The charge sharing circuit230ashown inFIG. 7Aincludes, for example, a capacitor231a, a switch232-1, and a switch232-2.

A capacitor231ais a variable capacitor capable of adjusting its capacitance value. The capacitance value of the capacitor231ais denoted as CR.

The switch232-1is disposed between an electrode A and one of electrodes of the capacitor231a. The switch232-2is disposed between an electrode B and the other one of electrodes of the capacitor231a.

The turning-on and the turning-off of the switch232-1and the switch232-2are controlled by the control signal CK1. For example, the switch232-1and the switch232-2are in an on-state when the control signal CK1is in the high level period, while the switch232-1and the switch232-2are in an off-state when the control signal CK1is in any period other than the high level period.

Also in the following description, switches are in the on-state when the control signal is in the high level period, while switches are in the off-state when the control signal is in any period other than the high level period.

For example, when the control signal CK1is in the high level period, the switch232-1connects the terminal A to the one of terminals of the capacitor231a. The switch232-2connects the terminal B to the other one of the terminals of the capacitor231awhen the control signal CK1is in the high level period. When the control signal CK1is in any period other than the high level period, the switch232-1and the switch232-2are in the off-state and thus the connections are opened.

In the charge sharing circuit230a, when the control signal CK1is in the high level period, the capacitor231ais connected to the terminal A and the terminal B, while when the control signal CK1is in the low level period, the connections of the capacitor231aare opened.

Next, an example of an operation of the phase shifter200shown inFIG. 5is described below for a case where the charge sharing circuit230ashown inFIG. 7Ais used as the charge sharing circuit230-1and the charge sharing circuit230-2inFIG. 5.

Note that in a case where the charge sharing circuit230ais used as the charge sharing circuit230-1, the capacitor231amay be called a capacitor231a-1, while in a case where the charge sharing circuit230ais used as the charge sharing circuit230-2, the capacitor231amay be called a capacitor231a-2.

When the control signal CK1is in the high level period, a charge output from the TA210-1is accumulated in both the capacitor220-1and the capacitor231a-1. When the control signal CK1is in the low level period, a charge output from the TA210-1is accumulated in the capacitor220-1.

Similarly, when the control signal CK1is in the high level period, a charge output from the TA210-2is accumulated in both the capacitor220-2and the capacitor231a-2, while when the control signal CK1is in the low level period, a charge output from the TA210-2is accumulated in the capacitor220-2.

Second Example of Charge Sharing Circuit230

FIG. 7Bis a diagram illustrating a second example of the charge sharing circuit230according to the second embodiment. The charge sharing circuit230bshown inFIG. 7Bincludes, for example, a capacitor231b, and switches232-1to232-4.

The capacitor231bis a variable capacitor capable of adjusting its capacitance value. The capacitance value of the capacitor231bis denoted as CR.

The switch232-1is disposed between an electrode A and one of electrodes of the capacitor231b. The switch232-2is disposed between an electrode B and the other one of the electrodes of the capacitor231b. The switch232-3and the switch232-4are disposed between one of the electrodes of the capacitor231band the other one of the electrodes.

The turning-on and the turning-off of the switch232-1and the232-2are controlled by the control signal CK1. The turning-on and the turning-off of the switches232-3and232-4are controlled by the control signal CK2.

For example, when the control signal CK1is in the high level period, the switch232-1connects the terminal A to the one of terminals of the capacitor231, while the switch232-2connects the terminal B to the other one of the terminals of the capacitor231bwhen the control signal CK1is in the high level period. When the control signal CK1is in any period other than the high level period, the switch232-1and the switch232-2are in the off-state and thus the connections are opened.

For example, when the control signal CK2is in the high level period, the switch232-3and the switch232-4connect one of terminals of the capacitor231bto the other one of the terminals. When the control signal CK2is in any period other than the high level period, the switch232-3and the switch232-4are in the off-state and thus the connections are opened.

In the case of a configuration in which one of electrodes of the capacitor231bis connected to the other one of electrodes when the control signal CK2is in the high level period, for example, one of the switch232-3and the switch232-4may be removed.

As shown inFIG. 6B, the control signal CK1and the control signal CK2are different in phase from each other by 180°. Therefore, when the control signal CK1is in the high level period, the control signal CK2is in the low level period, while when the control signal CK1is in the low level period, the control signal CK2is in the high level period.

In the charge sharing circuit230b, when the control signal CK1is in the high level period, the capacitor231bis connected to the terminal A and the terminal B, while when the control signal CK1is in the low level period, one of terminals of the capacitor231bis connected to the other one of the terminals. The connecting one of the electrodes of the capacitor231bto the other one of the electrodes causes the two terminals of the capacitor231bto be equal in potential to each other, and thus the charge stored in the capacitor231bis discharged.

Next, an example of an operation of the phase shifter200shown inFIG. 5is described below for a case where the charge sharing circuit230bshown inFIG. 7Bis used as the charge sharing circuit230-1and the charge sharing circuit230-2shown inFIG. 5.

Note that in a case where the charge sharing circuit230bis used as the charge sharing circuit230-1, the capacitor231bmay be called a capacitor231b-1, while in a case where the charge sharing circuit230bis used as the charge sharing circuit230-2, the capacitor231bmay be called a capacitor231b-2.

When the control signal CK1is in the high level period, a charge output from the TA210-1is accumulated in both the capacitor220-1and the capacitor231b-1. When the control signal CK1is in the low level period, a charge output from the TA210-1is accumulated in the capacitor220-1. When the control signal CK1is in the low level period (the control signal CK2is in the high level period), the charge stored in the capacitor231b-1is discharged.

Similarly, when the control signal CK1is in the high level period, a charge output from the TA210-2is accumulated in both the capacitor220-2and the capacitor231b-2, while when the control signal CK1is in the low level period, a charge output from the TA210-2is accumulated in the capacitor220-2. When the control signal CK1is in the low level period (the control signal CK2is in the high level period), the charge accumulated in the capacitor231b-2is discharged.

The configuration shown inFIG. 7Aand the configuration shown inFIG. 7Bare different from each other in terms of complexity and the degree of gain control range, which provides a freedom of selection of the configuration. In the charge sharing circuit230ashown inFIG. 7A, when the control signal CK1is in the low level period, a charge is retained in the capacitor231a. In the charge sharing circuit230bshown inFIG. 7B, when the control signal CK1is in the low level period, the control signal CK2is in the high level period, and thus the charge in the capacitor231bis discharged.

In a case where the charge sharing circuit230ashown inFIG. 7Ais used as the charge sharing circuit230-1inFIG. 5, a transfer function of an I-circuit including the TA210-1, the capacitor220-1, and the charge sharing circuit230-1shown inFIG. 5is given by equation (5).

In equation (5), CHdenotes a capacitance value (CH1) of the capacitor220-1, and CRdenotes a capacitance value of the capacitor231a-1for a case where the charge sharing circuit230ais used as the charge sharing circuit230-1. The pulse width TSis determined by the clock frequency of the control signals CK1-1and CK2-1. D1is given by equation (6).
D1=1−K0z−1−K1z−2(6)

K0in equation (6) is given by equation (7).

K1in equation (5) and equation (6) is given by equation (8).

Similarly, a transfer function of a Q-circuit including the TA210-2, the capacitor220-2, and the charge sharing circuit230-2shown inFIG. 5is given by equation (5). In the transfer function of the Q-circuit, CHin equation (5) is given by a capacitance value CH2of the capacitor220-2, and CRis given by a capacitance value of the capacitor231a-2for a case where the charge sharing circuit230ais employed as the charge sharing circuit230-2.

The clock frequency of the control signal CK1-1input to the charge sharing circuit230-1and the clock frequency of the control signal CK2-1input to the charge sharing circuit230-2may be or may not be equal to each other. The duty ratio of the control signal CK1-1input to the charge sharing circuit230-1and the duty ratio of the control signal CK2-1input to the charge sharing circuit230-2may be or may not be equal to each other.

Equation (5) indicates that the gain of the circuit represented by the transfer function is determined by the clock frequency and the capacitance ratio, which means that it is possible to control the phase of the phase shifter200shown inFIG. 5by using at least one of the clock frequency and the capacitance ratio.

It also can be seen that in a case where the charge sharing circuit230bshown inFIG. 7Bis employed as the charge sharing circuit230-1and the charge sharing circuit230-2shown inFIG. 5, the gains of the I-circuit and the Q-circuit are determined by the clock frequency and the capacitance ratio. Thus, it is possible to control the phase of the phase shifter200shown inFIG. 5by using at least one of the clock frequency and the capacitance ratio.

Method of Controlling Phase

In a case where the charge sharing circuit230ashown inFIG. 7Ais used in the phase shifter200, and also in a case where the charge sharing circuit230bshown inFIG. 7Bis used in the phase shifter200, it is possible to give a difference (a gain difference) between the gain of the I-circuit and the gain of the Q-circuit by executing at least one of control methods (2-1) to (2-3) described by way of example below thereby controlling the phase of the output signal output from the combining circuit240.

Control Method (2-1)

Adjust the capacitance value of the capacitor220-1and the capacitance value of the capacitor220-2.

Control Method (2-2)

Adjust the capacitance ratio between the capacitor220-1and the capacitor231-1of the charge sharing circuit230-1, and the capacitance ratio between the capacitor220-2and the capacitor231-2of the charge sharing circuit230-2.

Control Method (2-3)

Adjust the clock frequency of control signals input to the charge sharing circuit230-1and the charge sharing circuit230-2.

It is possible to control the phase of the output signal using at least one of the control methods (2-1) to (2-3) described above.

Next, a phase control characteristic of the phase shifter200is described.

FIG. 8is a diagram illustrating an example of a result of simulation of an output waveform output from the phase shifter200according to the second embodiment. InFIG. 8, a horizontal axis represents time and a vertical axis represents an output voltage.

The result of the simulation shown inFIG. 8is for a case where the input signal frequency fin=0.1 [GHz], the input signal power Pin=−30 [dBm], gm=20 [mS], CR=100 [fF], CH1=50 [fF], and CH2=50 [fF] or 500 [fF].FIG. 8shows two results obtained for two respective values of CH2, 50 [fF] and 500 [fF], while maintaining CH1at a fixed value of 50 [fF] thereby changing the capacitance ratio between CH1and CH2.

FIG. 8indicates that the phase of the output signal changes depending on the capacitance ratio. As can be seen fromFIG. 8, the phase shifter200is capable of adjusting the phase of the output signal by changing the capacitance ratio of CH1to CH2.

Furthermore,FIG. 8indicates that the amplitude changes depending on the capacitance ratio. That is,FIG. 8indicates that if the phase of the output signal is adjusted, then a corresponding change in amplitude of the output signal occurs.

Note that it is assumed that the output from the phase shifter200is connected to an amplifier (for example, the power amplifier17shown inFIG. 4A). By adjusting the amplitude of the signal by the amplifier connected to the output of the phase shifter200, the amplitude of the output signal may be corrected so as to cancel out the change that occurs in response to a change in the phase of the output signal. A variable gain amplifier may be used as the amplifier. Alternatively, the amplifier may be a digital amplifier configured to adjust the output level such that when the amplitude of the output signal is greater than a certain threshold value, the output signal is controlled at a fixed output level.

In the second embodiment, the configuration is explained for the phase shifter200including the two voltage-to-current conversion circuits (210-1and210-2), the two capacitors (220-1and220-2), the two charge sharing circuits (230-1and230-2), the combining circuit240and the clock generator250. In the configuration shown inFIG. 5, it is possible to control the phase by controlling the capacitance ratio and/or a parameter (for example, the clock frequency) associated with the control signal.

The phase shifter200according to the second embodiment has a simple configuration in which there are only a small number of switches and there is no switch disposed in series in a signal path, which makes it possible to operate at a high speed to handle a wideband signal.

Furthermore, it is possible to achieve a small variation in capacitance ratio even in the CMOS configuration which is sensitive to a process variation, and/or variations of power supply voltage and temperature. Therefore, by using the phase shifter200according to the second embodiment in which the phase is controlled by the clock frequency or the capacitance ratio, it is possible to achieve a phase control with a small deviation from a design value when the phase shifter200is produced using the CMOS process. Thus, it is possible to reduce or simplify a calibration circuit that adjusts the variation from the design value, which makes it possible to reduce the size and/or consumption power of a wireless communication apparatus.

In the second embodiment, by way of example, a variable capacitor is employed as the capacitor231aof the charge sharing circuit230aand also as the capacitor231bof the charge sharing circuit230b. However, the present disclosure is not limited to this example. For example, in a case where the charge sharing circuit230ais used as the charge sharing circuit230-1and the charge sharing circuit230-2shown inFIG. 5, the capacitor231aof one of the charge sharing circuit230-1and the charge sharing circuit230-2may be a variable capacitor, and the capacitor231aof the other one may be a capacitor with a fixed capacitance value. In this case, the capacitance ratio may be adjusted by adjusting the capacitance value of the variable capacitor.

Third Embodiment

In a third embodiment described below, an equalizer function is added to the phase shifter200according to the second embodiment thereby achieving a phase shifter having a wide frequency characteristic.

The transmission apparatus and the reception apparatus according to the third embodiment are similar, in configuration, to the transmission apparatus3shown inFIG. 4Aand the reception apparatus4shown inFIG. 4B, and thus a further description thereof is omitted. The phase shifter according to the fourth embodiment corresponds to, for example, the phase shifter35shown inFIG. 4Aor the phase shifter48shown inFIG. 4B. Note that in the following description, expressions such as “ . . . er”, “ . . . or” or the like used to indicate constituent elements of the transmission apparatus3or the reception apparatus4may be replaced by other expressions such as “ . . . circuitry”, . . . device”, . . . unit”, . . . module”, or the like.

Configuration and Operation of Phase Shifter300

FIG. 9is a diagram illustrating an example of a configuration of a phase shifter300according to the third embodiment. The phase shifter300shown inFIG. 9includes, for example, a TA310-1, a TA310-2, a capacitor320-1, a capacitor320-2, a charge sharing circuit330-1, a charge sharing circuit330-2, a combining circuit340, a clock generator350-1, and a clock generator350-2.

The TA310-1, the TA310-2, the capacitor320-1, the capacitor320-2, and the combining circuit340shown inFIG. 9are respectively similar to the TA110-1, the TA110-2, the capacitor120-1, the capacitor120-2, and the combining circuit130shown inFIG. 2. The capacitance value of the capacitor320-1and the capacitance value of the capacitor320-2are respectively CH1and CH2.

The clock generator350-1generates control signals S1-1, S2-1, S3-1, and S4-1using a reference frequency signal fREF1output from a reference frequency oscillator33(refer toFIG. 4A) or a reference frequency signal fREF2output from a reference frequency oscillator43(refer toFIG. 4B), and outputs them to the charge sharing circuit330-1. The clock frequency of the control signals S1-1, S2-1, S3-1, and S4-1is, for example, fCK1.

The clock generator350-2generates control signals S1-2, S2-2, S3-2, and S4-2using a reference frequency signal fREF1output from a reference frequency oscillator33(refer toFIG. 4A) or a reference frequency signal fREF2output from a reference frequency oscillator43(refer toFIG. 4B), and outputs them to the charge sharing circuit330-2. The clock frequency of the control signals S1-2, S2-2, S3-2, and S4-2is, for example, fCK2.

One of electrodes of the charge sharing circuit330-1is connected to the output of the TA310-1, and the other one of electrodes is connected to GND (that is, grounded). The charge sharing circuit330-1is input with a control signal generated by the clock generator350-1.

One of electrodes of the charge sharing circuit330-2is connected to the output of the TA310-2, and the other one of the electrodes is connected to GND (that is, grounded). The charge sharing circuit330-2is input with a control signal generated by the clock generator350-2.

Note that a system that includes the TA310-1, the capacitor320-1, and the charge sharing circuit330-1shown inFIG. 9and that operates to handle an input signal VIN_Imay be called an I-circuit, while a system that includes the TA310-2, the capacitor320-2, and the charge sharing circuit330-2shown inFIG. 9and that operates to handle an input signal VIN_Qmay be called a Q-circuit.

Note that the charge sharing circuit330-1and the charge sharing circuit330-2may be generically referred to as a charge sharing circuit330. The clock generator350-1and the clock generator350-2may be generically referred to as a clock generator350. The control signal S1-1and the control signal S1-2may be generically referred to as a control signal S1. The other control signals may be generically referred in a similar manner.

Next, an example of the charge sharing circuit330and examples of the control signals S1, S2, S3, and S4output from the clock generator350are described below.

FIG. 10Ais a diagram illustrating the charge sharing circuit330according to the third embodiment. The charge sharing circuit330shown inFIG. 10Aincludes, for example, a connection terminal A and a connection terminal B. The charge sharing circuit330is input with the control signals S1to S4generated by the clock generator350. Note that the control signals each may also be called a clock.

FIG. 10Bis a diagram illustrating an example of each of control signals input to the charge sharing circuit330illustrated by way of example inFIG. 10A. InFIG. 10B, a horizontal axis represents time and a vertical axis represents an amplitude. The duty ratio of each of the control signals S1to S4is 1/4. The control signal S2is a signal with a phase different by 90° with respect to the phase of the control signal S1. The control signal S3is a signal with a phase different by 180° with respect to the phase of the control signal S1. The control signal S4is a signal with a phase different by 270° with respect to the phase of the control signal S1. The clock frequency fCK(fCK=1/TCK) of each of the control signals S1to S2may be or may not be equal to the frequency of the reference frequency signal (fREF).

In the following description, a time period in which the control signal S1is at a “high” level shown inFIG. 10Bmay be referred to as a high level period of the control signal S1, while a time period in which the control signal S1is at a “low” level shown inFIG. 10Bmay be referred to as a low level period of the control signal S1. High and low level periods may be defined in a similar manner also for the control signals S2to S4.

Example of Charge Sharing Circuit330

FIG. 11is a diagram illustrating an example of the charge sharing circuit330according to the third embodiment of the present disclosure. The charge sharing circuit330shown inFIG. 11includes, for example, switches332-1to332-8, a capacitor331-1, and a capacitor331-2.

The capacitor331-1includes a terminal X1and a terminal Y1. The capacitor331-2includes a terminal X2and a terminal Y2. The capacitance value of the capacitor331-1and the capacitance value of the capacitor331-2are CR. Note that the capacitance value of the capacitor331-1may be different from the capacitance value of the capacitor331-2. At least one of the capacitor331-1and the capacitor331-2may be a variable capacitor.

The switch332-1is disposed between the terminal X1and the terminal A. The switch332-2is disposed between the terminal Y1and the terminal B. The switch332-1and the switch332-2are controlled by the control signal S1.

The switch332-3is disposed between the terminal X2and the terminal A. The switch332-4is disposed between the terminal Y2and the terminal B. The switch332-3and the332-4are controlled by the control signal S2.

The switch332-5is disposed between the terminal X1and the terminal B. The switch332-6is disposed between the terminal Y1and the terminal A. The switch332-5and the332-6are controlled by the control signal S3.

The switch332-7is disposed between the terminal X2and the terminal B. The switch332-8is disposed between the terminal Y2and the terminal A. The switch332-7and the332-8are controlled by the control signal S4.

In the charge sharing circuit330shown inFIG. 11, the switches332-1to332-8turn on and off according to the control signals S1to S4shown inFIG. 10Bsuch that four operations described below are performed in each period (1TCK), and the four operations are repeated at intervals of the period TCK.

First operation: When the control signal S1is in the high level period, the terminal X1of the capacitor331-1is connected to the terminal A, and the terminal Y1is connected to the terminal B (hereinafter, this situation is referred to as a positive-phase connection of the capacitor331-1). Note that when the control signal S1is in the high level period, the control signals S2to S4are in the low level period, and thus the terminals of the capacitor331-2are opened and a charge accumulated in the capacitor331-2during a fourth operation (described later) is retained therein.

Second operation: When the control signal S2is in the high level period, the terminal X2of the capacitor331-2is connected to the terminal A, and the terminal Y2is connected to the terminal B (hereinafter, this situation is referred to as a positive-phase connection of the capacitor331-2). Note that when the control signal S2is in the high level period, the control signals S1, S3, and S4are in the low level period, and thus the terminals of the capacitor331-1are opened and a charge accumulated in the capacitor331-1during the first operation is retained therein.

Third operation: When the control signal S3is in the high level period, the terminal Y1of the capacitor331-1is connected to the terminal A, and the terminal X1is connected to the terminal B (hereinafter, this situation is referred to as a negative-phase connection of the capacitor331-1). Note that when the control signal S3is in the high level period, the control signals S1, S2, and S4are in the low level period, and thus the terminals of the capacitor331-2are opened, and a charge accumulated in the capacitor331-2during the second operation is retained therein.

Fourth operation: When the control signal S4is in the high level period, the terminal Y2of the capacitor331-2is connected to the terminal A, and the terminal X2is connected to the terminal B (hereinafter, this situation is referred to as a negative-phase connection of the capacitor331-2). Note that when the control signal S4is in the high level period, the control signals S1to S3are in the low level period, and thus the terminals of the capacitor331-1are opened and a charge accumulated in the capacitor331-1during the third operation is retained therein.

The four operations, that is, the first operation in which the capacitor331-1is connected in the positive-phase connection and the charge charge-shared during the negative-phase connection state in the capacitor331-2is retained, the second operation in which the capacitor331-2is connected in the positive-phase connection and the charge charge-shared during the positive-phase connection state in the capacitor331-1is retained, the third operation in which the capacitor331-1is connected in the positive-phase connection and the charge charge-shared during the positive-phase connection state in the capacitor331-2is retained, and the fourth operation in which the capacitor331-2is connected in the negative-phase connection and the charge charge-shared during the negative-phase connection state in the capacitor331-1is retained, are performed repeatedly such that one operation is performed in one Ts period and a next operation is performed in a next Ts period.

The capacitor331-1and the capacitor331-2each operate such that a charge is charge-shared during a positive-phase connection (negative-phase connection) period and the polarity of this retained charge is inverted when a negative-phase connection (positive-phase connection) is made.

That is, in the first to fourth operations described above, the charge sharing circuit330connects the capacitor331-1such that the polarity of the charge retained in the capacitor331-1is inverted while the connection of the capacitor331-2is opened and the charge is retained in the capacitor331-2(in the first and third operations), and then the capacitor331-2is connected such that the polarity of the charge retained in the capacitor331-2is inverted while the connection of the capacitor331-1is opened and the charge is retained in the capacitor331-1(in the second and fourth operations). The above four operations are performed repeatedly such that one operation is performed in one Ts period and a next operation is performed in a next Ts period.

Next, an example of an operation of the phase shifter300shown inFIG. 9is described below for a case where the charge sharing circuit330shown inFIG. 11is used as the charge sharing circuit330-1and the charge sharing circuit330-2inFIG. 9.

In the I-circuit (which includes the TA310-1, the capacitor320-1, and the charge sharing circuit330-1) shown inFIG. 9, the capacitor320-1and the charge sharing circuit330-1perform the charge sharing repeatedly every Ts period thereby generating a sample value. The capacitor320-1and the charge sharing circuit330-1share three types of charges as described below.

(a) A charge obtained as a result of conversion from the input voltage signal VIN_Ito a current performed by the TA310-1. (b) A charge captured one sampling period before and retained in the capacitor320-1. (c) A charge captured two sampling periods before and retained in the charge sharing circuit330-1.

Note that in the three types of sharing, the charge sharing circuit330performs charge sharing by inverting the polarity of the charge captured two sampling periods before and retained currently.

The transfer function of the I-circuit (which includes the TA310-1, the capacitor320-1, and the charge sharing circuit330-1) is given by equation (9).

CHin equation (9) denotes a capacitance value (CH1) of the capacitor320-1, and CRdenotes the capacitance values of the capacitor331-1and the capacitor331-2in the charge sharing circuit330-1. Note that the pulse width Ts is determined by the clock frequency of the control signals. D is given by equation (10).
D=1−K0z−1+K1z−2(10)

K0in equation (10) is given by equation (11).

K1in equation (9) and equation (10) is given by equation (12).

The DC gain of the I-circuit is determined by the transfer function shown in equation (9) as described in equation (13).

In equation (13), fS=1/TS. For example, when the duty ratio is 1/4, fS=4 fCK.

Similarly, a transfer function of a Q-circuit including the TA310-2, the capacitor320-2, and the charge sharing circuit330-2shown inFIG. 9is given by equation (9), and the DC gain of the Q-circuit is given by equation (13). In the case of the transfer function of the Q-circuit, CHin equations (9) to (13) is the capacitance value CH2of the capacitor320-2, and CRis the capacitance value of the capacitor331-1and the capacitor331-2in the charge sharing circuit330-2.

Method of Controlling Phase

In the phase shifter300in which the charge sharing circuit330shown inFIG. 11is used, it is possible to give a gain difference between the gain of the I-circuit and the gain of the Q-circuit by performing control according to at least one of control methods (3-1) to (3-3) described by way of example below, thereby controlling the phase of the signal output from the combining circuit340.

Control Method (3-1)

Control Method (3-2)

Adjust the ratio of the capacitance value CH1of the capacitor320-1to the capacitance value CRof the capacitor331in the charge sharing circuit330-1and the ratio of the capacitance value CH2of the capacitor320-2to the capacitance value CRof the capacitor331in the charge sharing circuit330-2.

Control Method (3-3)

Adjust the clock frequency of the control signals input to the charge sharing circuit330-1and the charge sharing circuit330-2.

It is possible to control the phase of the output signal by at least one of the control methods (3-1) to (3-3) described above.

For example, in a case where the phase of the output signal is controlled using the control method (3-1) and/or the control method (3-2), a relationship between capacitance values and the phase of the output signal is represented by equation (14).

In equation (14), CH1is the capacitance value of the capacitor320-1, CR1is the capacitance value of the capacitor331-1and the capacitor331-2included in the charge sharing circuit330-1, CH2is the capacitance value of the capacitor320-2, and CR2is the capacitance value of the capacitor331-1and the capacitor331-2included in the charge sharing circuit330-2. K0_Iis obtained as a result of substituting CH1and CR1respectively into CHand CRin equation (11). K1_Iis obtained as a result of substituting CH1and CR1respectively into CHand CRin equation (12). K0_Qis obtained as a result of substituting CH2and CR2respectively into CHand CRin equation (11). K1_Qis obtained as a result of substituting CH2and CR2respectively into CHand CRin equation (12). Equation (14) is obtained from equation (13) when the clock frequency of control signals generated by the clock generator350-1is set to the clock frequency of control signals generated by the clock generator350-2.

For example, in a case where the phase of the output signal is controlled using the control method (3-3), the clock frequency of the control signals and the phase control amount α of the output signal has a relationship represented by equation (15).

In equation (15), fCK1is the clock frequency of control signals generated by the clock generator350-1, and fCK2is the clock frequency of control signals generated by the clock generator350-2. Equation (15) is obtained from equation (13), for example, when capacitance values or capacitance ratio are set such that equation (14) has a value of 1.

Next, a phase control characteristic of the phase shifter300is described.

FIG. 12Ais a diagram illustrating a first example of a result of simulation of an output waveform output from the phase shifter300according to the third embodiment.FIG. 12Bis a diagram illustrating a second example of a result of simulation of an output waveform output from the phase shifter300according to the third embodiment. In each ofFIG. 12AandFIG. 12B, a horizontal axis represents time and a vertical axis represents an output voltage.

The result of the simulation shown inFIG. 12Ais for a case where the input signal frequency fin=1 [GHz], the input signal power Pin=−30 [dBm], gm=20 [mS], CR=100 [fF], CH1=50 [fF], fCK=fCK1=fCK2=2 [GHz], and CH2=50 [fF] or 500 [fF].FIG. 12Ashows two results obtained for two respective values of CH2, 50 [fF] and 500 [fF], while maintaining CH1at a fixed value of 50 [fF] thereby changing the capacitance ratio between CH1and CH2.

FIG. 12Aindicates that the phase of the output signal changes depending on the capacitance ratio. As can be seen fromFIG. 12A, the phase shifter300is capable of adjusting the phase of the output signal by changing the capacitance ratio of CH1to CH2.

The result of the simulation shown inFIG. 12Bis for a case where the input signal frequency fin=1 [GHz], the input signal power Pin=−30 [dBm], gm=20 [mS], CR=100 [fF], CH1=CH2=50 [fF], fCK1=2 [GHz], and fCK2=2 [GHz] or fCK2=4 [GHz].FIG. 12Bshows two results obtained for two respective values of fCK2, 2 [GHz] and 4 [GHz], while maintaining fCK1at a fixed value of 2 [GHz] thereby changing the clock frequency ratio between fCK1and fCK2.

FIG. 12Bindicates that the phase of the output signal changes depending on the clock frequency ratio. As can be seen fromFIG. 12B, the phase shifter300is capable of adjusting the phase of the output signal by changing the clock frequency.

Furthermore,FIG. 12Aindicates that the amplitude changes depending on the capacitance ratio. Furthermore,FIG. 12Bindicates that the amplitude changes depending on the clock frequency ratio. That is,FIGS. 12A and 12Bindicate that when the phase of the output signal is adjusted, a corresponding change in amplitude of the output signal occurs.

In the configuration described above, it is assumed that an amplifier (for example, the power amplifier17shown inFIG. 4A) is connected to the output of the phase shifter300. By adjusting the amplitude by the amplifier connected to the output of the phase shifter300, the amplitude of the output signal that changes in response to an adjustment of the phase of the output signal may be corrected. A variable gain amplifier may be used as the amplifier. Alternatively, the amplifier may be a digital amplifier configured to adjust the output level such that when the amplitude of the output signal is greater than a certain threshold value, the output signal is controlled at a fixed output level.

As described above, in the configuration according to the third embodiment, the phase shifter300includes the two voltage-to-current conversion circuits (310-1and310-2), the two capacitors (320-1and320-2), the two charge sharing circuits (330-1and330-2), the combining circuit340, and the clock generator350. In the configuration shown inFIG. 9, it is possible to control the phase by controlling the capacitance ratio and/or a parameter (for example, the clock frequency) associated with the control signal.

The phase shifter300according to the third embodiment has a simple configuration in which there are only a small number of switches and there is no switch disposed in series in a signal path, which makes it possible to operate at a high speed to handle a wideband signal.

Furthermore, it is possible to achieve a small variation in capacitance ratio even in the CMOS configuration which is sensitive to a process variation, and/or variations of power supply voltage and temperature. Therefore, by using the phase shifter300according to the third embodiment in which the phase is controlled by the capacitance ratio, it is possible to achieve a phase control with a small deviation from a design value when the phase shifter300is produced using the CMOS process. Thus, it is possible to reduce or simplify a calibration circuit that adjust the variation from the design value, which makes it possible to reduce the size and/or consumption power of a wireless communication apparatus.

In the phase shifter300according to the third embodiment, the provision of the equalizer function makes it possible to correct the frequency characteristic. In this configuration, it is not necessary to separately provide an additional equalizer for adjusting the frequency characteristic, which allows a reduction in the apparatus size.

Fourth Embodiment

In the phase shifter300according to the third embodiment described above, the charge sharing circuit330-1is provided in a path via which the input signal VIN_Iis input, and the charge sharing circuit330-2is provided in a path via which the input signal VIN_Qis input. In a fourth embodiment described below, the configuration of the phase shifter300according to the third embodiment is modified such that a charge sharing circuit is provided between the path via which the input signal VIN_Iis input and the path via which the input signal VIN_Qis input. Note that the configuration according to the present fourth embodiment is a configuration obtained as a result of simplifying the configuration according to the third embodiment.

The transmission apparatus and the reception apparatus according to the fourth embodiment are similar, in configuration, to the transmission apparatus3shown inFIG. 4Aand the reception apparatus4shown inFIG. 4B, and thus a duplicated description of the configurations thereof is omitted. The phase shifter according to the fourth embodiment corresponds to, for example, the phase shifter35shown inFIG. 4Aor the phase shifter48shown inFIG. 4B. Note that in the following description, expressions such as “ . . . er”, “ . . . or” or the like used to indicate constituent elements of the transmission apparatus3or the reception apparatus4may be replaced by other expressions such as “ . . . circuitry”, . . . device”, . . . unit”, . . . module”, or the like.

Configuration and Operation of Phase Shifter400

FIG. 13is a diagram illustrating an example of a configuration of a phase shifter400according to the fourth embodiment. The phase shifter400shown inFIG. 13includes, for example, a TA410-1, a TA410-2, a capacitor420-1, a capacitor420-2, a charge sharing circuit430, a combining circuit440, and a clock generator450.

The TA410-1, the TA410-2, the capacitor420-1, the capacitor420-2, and the combining circuit440shown inFIG. 13are respectively similar to the TA110-1, the TA110-2, the capacitor120-1, the capacitor120-2, and the combining circuit130shown inFIG. 2. The capacitance value of the capacitor420-1and the capacitance value of the capacitor420-2are respectively CH1and CH2.

The clock generator450generates control signals S1, S2, S3, and S4using a reference frequency signal fREF1output from a reference frequency oscillator33(refer toFIG. 4A) or a reference frequency signal fREF2output from a reference frequency oscillator43(refer toFIG. 4B), and outputs them to the charge sharing circuit430. The clock frequency of the control signals S1, S2, S3, and S4is, for example, fCK.

One of electrodes of the charge sharing circuit430is connected to the output of the TA410-1, and the other one of electrodes is connected to the output of the TA410-2. The charge sharing circuit430is input with control signals generated by the clock generator450.

Note that a system that includes a TA410-1and a capacitor420-1shown inFIG. 13and that operates in response to an input signal VIN_Imay be called an I-circuit, and a system that includes a TA410-2and a capacitor420-2shown inFIG. 13and that operates in response to an input signal VIN_Qmay be called a Q-circuit. Note that in the fourth embodiment, the charge sharing circuit430is shared by both the I-circuit and the Q-circuit.

Next, an example of the charge sharing circuit430and examples of the control signals S1, S2, S3, and S4output from the clock generator350are described below.

The configuration of the charge sharing circuit430may be similar to, for example, the configuration of the charge sharing circuit330shown inFIG. 10AorFIG. 11. The charge sharing circuit430is input with the control signals S1to S4generated by the clock generator450. Note that the control signals each may also be called a clock. The control signals may have waveforms similar to, for example, those shown inFIG. 10B.

Note that in the following description, a time period in which the control signal S1is at a “high” level shown inFIG. 10Bmay be referred to as a high level period of the control signal S1, and a time period in which the control signal S1is at a “low” level shown inFIG. 10Bmay be referred to as a low level period of the control signal S1. High and low level periods may be defined in a similar manner also for the control signals S2to S4.

Next, an example of an operation of the phase shifter400shown inFIG. 13is described below for a case where the charge sharing circuit330shown inFIG. 11is used as the charge sharing circuit430inFIG. 13. More specifically, the operation of the phase shifter400is described below, by way of example, for a case where the terminal A shown inFIG. 11is connected to the capacitor420-1, and the terminal B is connected to the capacitor420-2.

The phase shifter400operates in a period in which the control signal S1is at the high level, in a period in which the control signal S2is at the high level, in a period in which the control signal S3is at the high level, and in a period in which the control signal S4is at the high level, and the operations in these periods are performed repeatedly such that one operation is performed in a period and a next operation is performed in a next period. The operation in each period is performed as follows.

In the period in which the control signal S1is at the high level, the terminal X1of the capacitor331-1(CR) is connected to the capacitor420-1(CH1), and the terminal Y1of the capacitor331-1(CR) is connected to the capacitor420-2(CH2).

In the period in which the control signal S2is at the high level, the terminal X2of the capacitor331-2(CR) is connected to the capacitor420-1(CH1), and the terminal Y2of the capacitor331-2(CR) is connected to the capacitor420-2(CH2).

In the period in which the control signal S3is at the high level, the terminal Y1of the capacitor331-1(CR) is connected to the capacitor420-1(CH1), and the terminal X1of the capacitor331-1(CR) is connected to the capacitor420-2(CH2). In the period in which the control signal S3is at the high level, the capacitor331-1is connected between the capacitor420-1and the capacitor420-2such that the connection direction thereof is opposite to the direction in the period in which the control signal S1is at the high level.

In the period in which the control signal S4is at the high level, the terminal Y2of the capacitor331-2(CR) is connected to the capacitor420-1(CH1), and the terminal X2of the capacitor331-2(CR) is connected to the capacitor420-2(CH2). In the period in which the control signal S4is at the high level, the capacitor331-2is connected between the capacitor420-1and the capacitor420-2such that the connection direction is opposite to the direction in the period in which the control signal S2is at the high level.

It is possible to control the phase of the output signal by combining, via the capacitor331-1and the capacitor331-2, the I-signal input from the TA410-1and the Q-signal with a 90°-shifted phase input from the TA410-2.

Method of Controlling Phase

In the phase shifter400shown inFIG. 13, in a case where the charge sharing circuit330shown inFIG. 11is used as the charge sharing circuit430, it is possible to give a gain difference between the gain of the I-circuit and the gain of the Q-circuit by performing control according to a control method described by way of example below thereby controlling the phase of the signal output from the combining circuit440.

Control Method

Adjust the ratio of the capacitance value CH1of the capacitor420-1to the capacitance value CRof the capacitor331(seeFIG. 11) in the charge sharing circuit430, and the ratio of the capacitance value CH2of the capacitor420-2to the capacitance value CRof the capacitor331(seeFIG. 11) in the charge sharing circuit430.

Next, a phase control characteristic of the phase shifter300is described.

FIG. 14Ais a diagram illustrating a first example of a result of simulation of an output waveform output from the phase shifter400according to the fourth embodiment.FIG. 14Bis a diagram illustrating an example of a result of simulation of an output waveform for a case where a lowpass filter is connected to the phase shifter400according to the fourth embodiment. In each ofFIG. 14AandFIG. 14B, a horizontal axis represents time and a vertical axis represents an output voltage.

The result of the simulation shown inFIG. 14Ais for a case where the input signal frequency fin=1 [GHz], the input signal power Pin=−30 [dBm], gm=20 [mS], CR=100 [fF], CH1=50 [fF], fCK=2 [GHz], and CH2=50 [fF] or 500 [fF].FIG. 14Ashows results obtained for two respective values 50 [fF] and 500 [fF] for CH2, while maintaining CH1at a fixed value of 50 [fF] thereby changing the capacitance ratio between CH1and CH2.

FIG. 14Aindicates that the phase of the output signal changes depending on the capacitance ratio. As can be seen fromFIG. 14A, it is possible to adjust the phase of the output signal from the phase shifter400by changing the capacitance ratio of CH1to CH2.

FIG. 14Bis a diagram illustrating an example of a result of simulation of an output waveform for a case where a lowpass filter is connected to the phase shifter400. In this configuration in which the lowpass filter is connected to the phase shifter400, a low frequency component of the output waveform (see, for example,FIG. 14A) output from the phase shifter400is output from the lowpass filter, but a high frequency component of the output waveform output from the phase shifter400is suppressed. For example, abrupt changes in amplitude (such as sharp peaks) occur in the output waveform inFIG. 14A, but abrupt changes are suppressed and smooth output waveform is obtained inFIG. 14B.

In the configuration described here, it is assumed that an amplifier (for example, the power amplifier17shown inFIG. 4A) is connected to the output of the phase shifter400. By adjusting the amplitude of the signal by the amplifier connected to the output of the phase shifter400, the amplitude of the output signal may be corrected so as to cancel out the change that occurs in response to a change in the phase of the output signal. A variable gain amplifier may be used as the amplifier. Alternatively, the amplifier may be a digital amplifier configured to adjust the output level such that when the amplitude of the output signal is greater than a certain threshold value, the output signal is controlled at a fixed output level.

As described above, in the configuration according to the third embodiment, the phase shifter400includes the two voltage-to-current conversion circuits (410-1and410-2), the two capacitors (420-1and420-2), one charge sharing circuit (430), the combining circuit440, and the clock generator450. In the configuration shown inFIG. 13, it is possible to control the phase by controlling the capacitance ratio.

The phase shifter400according to the fourth embodiment has a simple configuration in which there are only a small number of switches and there is no switch disposed in series in a signal path, which makes it possible to operate at a high speed to handle a wideband signal.

Note that capacitors used in each embodiment described above may be capacitors having fixed capacitance values or may be variable capacitors whose capacitance values are variable.

The present disclosure can be realized by software, hardware, or software in cooperation with hardware.

Each functional block used in the description of each embodiment described above can be partly or entirely realized by an LSI such as an integrated circuit, and each process described in each embodiment may be controlled partly or entirely by a single LSI or a combination of LSIs. The LSI may be individually formed by chips, or the LSI may include only one chip on which a part or all of the functional blocks are formed. The LSI may include a data input and a data output. The LSI here may be referred to as an IC, a system LSI, a super LSI, or an ultra LSI depending on a difference in the degree of integration.

The technique of implementing an integrated circuit is not limited to the LSI and may be realized by using a dedicated circuit, a general-purpose processor, or a special-purpose processor. The integrated circuit may also be realized using an FPGA (Field Programmable Gate Array) that can be programmed after the manufacture of the LSI or a reconfigurable processor that is allowed to be reconfigured in terms of the connection or the setting of circuit cells in the inside of the LSI. The present disclosure can be realized as digital processing or analogue processing.

When a new integrated circuit technique other than LSI techniques are realized in the future by an advance in semiconductor technology or related technology, the functional blocks may be realized using such a new technique. A possible example of a new technique is biotechnology.

The present disclosure may be implemented in a wide variety of apparatuses, devices, and systems (generically referred to as a communication apparatus) having a communication function. Non-limiting examples of communication apparatuses include a telephone (a portable telephone, a smartphone, etc.), a tablet computer, a personal computer (PC) (a laptop computer, a desktop computer, a notebook computer, etc.), a camera (a digital camera, a still camera, a video camera, etc.), a digital player (a digital audio/video player, etc.), a wearable device (a wearable camera, a smart watch, a tracking device, etc.), a tame console, a digital book reader, a telehealth/telemedicine device, a vehicle/transportation (a car, an air plane, a ship, etc.) having a communication capability, and various combinations of apparatuses described above.

The communication apparatuses are not limited to those of potable or mobile types, but the communication apparatuses may also include a wide variety of unportable or firmly-installed apparatuses, devices, and systems, such as a smart home device (a home electric appliance, lighting equipment, a smart meter, a measuring instrument, a control panel, etc.), a vending machine, and other many things located on an IoT (Internet of Things).

The communication may include data communication using a cellular system, a wireless LAN system, a satellite communication system and/or the like, and data communication using an arbitrary combination thereof.

The communication apparatuses include a device such as a controller, a sensor, or the like connected or coupled to a communication device capable of executing a communication function according to the present disclosure. A specific example may be a controller or a sensor configured to generate a control signal, a data signal, or the like for use by a communication device that executes a communication function of a communication apparatus.

Furthermore, the communication apparatuses may also include an infrastructure facility such as a base station, an access point, etc., and other many apparatuses, devices, and systems that communicate with or control the above-described non-limiting apparatuses.

The present disclosure may also be implemented as a control method executed by a wireless communication apparatus or a control apparatus. The present disclosure may also be implemented as a program for executing the control method on a computer. The present disclosure may be represented by storing the program in a storage medium such that the program may be readable by a computer. That is, the present disclosure may be implemented in any of forms including an apparatus, a method, a program, and a storage medium.

Various embodiments have been described above with reference to drawings. However, the present disclosure are not limited to these embodiments. It should be understood by those skilled in the art that various modifications or alterations may occur within the scope of the present disclosure. Note that such modifications or alterations also fall within the scope of the present disclosure. Furthermore, various combinations of constituent elements of the embodiments may occur without departing from the scope of the present disclosure.

SUMMARY OF THE PRESENT DISCLOSURE

In an aspect, the present disclosure provides a phase shifter including a first capacitor connected to a first line to which a first input signal is input, a second capacitor connected to a second line to which a second input signal having a first phase difference with respect to the first input signal is input, and a combining circuit that is connected to the first line and the second line and that outputs a combined signal having a phase determined depending on a first capacitance ratio between the first capacitor and the second capacitor.

In the phase shifter according to the present disclosure, the first phase difference may be equal to n×π/2 where n is an integer greater than or equal to 1.

The phase shifter according to the present disclosure may further include a third capacitor that is connected to the first line and disconnected from the first line repeatedly in a first period, and a fourth capacitor that is connected to the second line and disconnected from the second line repeatedly in a second period, wherein the combined signal may have a phase determined depending on the first capacitance ratio, a second capacitance ratio between the third capacitor and the fourth capacitor, the first period, and the second period.

In the phase shifter according to the present disclosure, the third capacitor may be connected to the first line in a one-half period of the first period and disconnected from the first line in the other one-half period of the first period, and the fourth capacitor may be connected to the second line in a one-half period of the second period and disconnected from the second line in the other one-half period of the second period.

In the phase shifter according to the present disclosure, when the third capacitor is in a period in which the third capacitor is disconnected from the first line, the third capacitor may retain a charge accumulated in a period in which the third capacitor is connected to the first line, and when the fourth capacitor is in a period in which the fourth capacitor is disconnected from the second line, the fourth capacitor may retain a charge accumulated in a period in which the fourth capacitor is connected to the second line.

In the phase shifter according to the present disclosure, when the third capacitor is in a period in which the third capacitor is disconnected from the first line, the third capacitor may discharge a charge accumulated in a period in which the third capacitor is connected to the first line, and when the fourth capacitor is in a period in which the fourth capacitor is disconnected from the second line, the fourth capacitor may discharge a charge accumulated in a period in which the fourth capacitor is connected to the second line.

The phase shifter according to the present disclosure may further include a fifth capacitor having two terminals one of which is connected to the first line in a third period and the other one of which is connected to the first line in a period shifted from the third period by one-half of the third period, a sixth capacitor having two terminals one of which is connected to the first line in a period shifted from the third period by one-fourth of the third period and the other one of which is connected to the first line in a period shifted from the third period by three-fourth of the third period, a seventh capacitor having two terminals one of which is connected to the second line in a fourth period and the other one of which is connected to the fourth line in a period shifted from the fourth period by one-half of the fourth period, and an eighth capacitor having two terminals one of which is connected to the second line in a period shifted from the fourth period by one-fourth of the fourth period and the other one of which is connected to the second line in a period shifted from the fourth period by three-fourth of the fourth period, wherein the combined signal may have a phase determined depending on the first capacitance ratio, a third capacitance ratio determined from values of the fifth to eighth capacitors, the third period, and the fourth period.

In the phase shifter according to the present disclosure, the one of the two terminals of the fifth capacitor may be connected to the first line in a one-fourth period of the third period, and the one of the two terminals of the seventh capacitor may be connected to the second line in a one-fourth period of the fourth period.

The phase shifter according to the present disclosure may further include a ninth capacitor having a first terminal and a second terminal that are connected such that in a fifth period, the first terminal is connected to the first line and the second terminal is connected to the second line, while in a period shifted from the fifth period by one-half of the fifth period, the second terminal is connected to the first line and the first terminal is connected to the second line, and a tenth capacitor having a third terminal and a fourth terminal that are connected such that in a period shifted from the fifth period by one-fourth of the fifth period, the third terminal is connected to the first line and the fourth terminal is connected to the second line, while in a period shifted from the fifth period by a three-fourth of the fifth period, the fourth terminal is connected to the first line and the third terminal is connected to the second line, wherein the combined signal may have a phase determined depending on the first capacitance ratio, a fourth capacitance ratio determined from values of the ninth and tenth capacitors.

In an aspect, the present disclosure provides a wireless communication apparatus including a plurality of phase shifters according to the present disclosure, wherein a beam having a controlled directivity may be formed by controlling the combined signal of each of the plurality of phase shifters.

A phase shifter according to an aspect of the present disclosure is useful in a high frequency signal processing circuit and a baseband signal processing circuit in a wireless communication apparatus, and is useful in a phase control process.