Multi-channel package and electronic system including the same

A multi-channel package has at least four channels and includes a package substrate having a first surface and a second surface, semiconductor chips mounted on the first surface of the package substrate, and external connection terminals disposed on the second surface of the package substrate and electrically connected to the semiconductor chips by the at least four channels. Each channel is dedicated to one or a group of the chips. An electronic system includes a main board, at least one such multi-channel package mounted on the main board, and a controller package that is mounted on the main board, has 4n channels (wherein n≧2) and controls the at least one multi-channel package.

PRIORITY STATEMENT

This application claims the benefit of Korean Patent Application No. 10-2011-0072570, filed on Jul. 21, 2011, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The inventive concept relates to semiconductor packages. More particularly, the inventive concept relates to multi-channel packages and to electronic device including a multi-channel package.

Although semiconductor devices are being scaled down to meet such demands as the demand for smaller and smaller electronic products, the semiconductor devices must still be able to process very large amounts of data. Accordingly, i.e., to meet such demands, semiconductor chips of today's electronic products need to be highly integrated and incorporated into a single package. Moreover, in addition to the need for highly integrated semiconductor chips, there is a demand for chips that offer better performance and greater reliability. Similarly, there is an ever increasing demand for electronic systems that operate at higher speeds.

SUMMARY

According to an aspect of the inventive concept, there is provided a multi-channel package having at least four channels and comprising a package substrate having a first surface and a second surface, 4n semiconductor chips mounted to the package substrate on the first surface thereof, wherein n is a positive integer, and a plurality of external connection terminals on the second surface of the package substrate. Each of the channels constitutes a discrete path in the package associated with and along which signals are transmitted to/from a respective one or group of the semiconductor chips in the package. Also, each of the channels is discrete and independent from the other channels in the package such that each of the chips can transmit/receive signals to/from the external connection terminals via only one of the channels amongst the at least four channels.

According to an aspect of the inventive concept, there is provided an electronic system comprising a main board including wiring, at least one multi-channel package having at least four channels and mounted to the main board, and a controller package mounted on the main board. The controller package has 4n channels wherein n is an integer equal to or greater than 2. Each multi-channel package comprises at least four semiconductor chips, and external connection terminals by which the package is electrically connected to the main board. Also, each of the channels of the multi-channel package constitutes a discrete path in the package associated with and along which signals are transmitted to/from a respective one or a group of the semiconductor chips in the package, and each of the channels is discrete and independent from the other channels in the package. Therefore, each of the chips can transmit/receive signals to/from the external connection terminals via only one of the channels. Respective ones of the channels of the controller package are connected by the wiring of the main board to respective ones of the channels of the at least one multi-channel package.

According to another aspect of the inventive concept there is provided an electronic device comprising a main board including a wiring pattern of discrete wires, at least one multi-channel package having at least four channels mounted to the main board, and a controller package mounted on the main board. Each multi-channel package includes a package substrate having a first surface and a second surface, 4n semiconductor chips mounted to the package substrate on the first surface thereof, wherein n is a positive integer, and a plurality of external connection terminals on the second surface of the package substrate and by which the multi-channel package is electrically connected to the wiring of the main board. The controller package has a number of channels equal to the total number of channels of the multi-channel package or packages mounted to the main board, and the channels of the controller package are connected to the channels of the at least one multi-channel package, respectively, by the wires of the wiring pattern of the main board, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments and examples of embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the sizes and relative sizes and shapes of elements and layers shown in section may be exaggerated for clarity. In particular, the cross-sectional illustrations of the semiconductor packages are schematic. Also, like numerals are used to designate like elements throughout the drawings.

Furthermore, the terminology used herein for the purpose of describing particular examples or embodiments of the inventive concept is to be taken in context. For example, the term “connected” generally will refer to an electrical connection in the context of this are. Furthermore, the terms “comprises” or “comprising” when used in this specification specifies the presence of stated features but does not preclude the presence or additional features.

It will also be understood that when a component is referred to as being merely “connected to” another component, the components may be directly connected to one another or another component(s) may be connected therebetween.

Furthermore, the terms first, second, third, etc., are used herein to designate particular elements such as chips. However, these elements are not limited by these terms. Rather, these terms are only used to distinguish one element from another.

An embodiment of a multi-channel package100according to the inventive concept will now be described in more detail with reference toFIG. 1andFIG. 2.

The multi-channel package100includes a package substrate110, a plurality of semiconductor chips120a,120b,120c, and120dmounted to the package substrate110, a plurality of external connection terminals130a,130b,130c, and130d, and encapsulant150encapsulating the semiconductor chips120a,120b,120c, and120d.

The package substrate110may be any of various types of substrates such as a printed circuit board, a flexible substrate, or a tape substrate. In any case, the package substrate110has a substrate body including a first surface114and a second surface116, and a plurality of bonding pads112a,112b,112c, and112dlocated on the first surface114of the substrate body of the package substrate110. The semiconductor chips120a,120b,120c, and120dare disposed on the first surface114of the package substrate110and are electrically connected to the bonding pads112a,112b,112c, and112d.

In this example, the bonding pads112a,112b,112c, and112dare arranged along two edges only of the package substrate110, but the inventive concept is not limited to such an arrangement of the bonding pads112a,112b,112c, and112d. Furthermore, in this example, the bonding pads112a,112b,112c, and112dare divided into at least four groups each associated with one of at least four channels, respectively. For example, the bonding pads112a,112b,112c, and112dconsist of a first bonding pad group BG1of first bonding pads112aassociated with a first channel, a second bonding pad group BG2of second bonding pads112bassociated with a second channel, a third bonding pad group BG3of third bonding pads112cassociated with a third channel, and a fourth bonding pad group BG4of fourth bonding pads112dassociated with a fourth channel. Here, a channel refers to an independent or discrete path such as a bus along which commands or data (signals) are transmitted to/from corresponding semiconductor chips.

Also, in the example illustrated inFIG. 2, the first bonding pads112aand the second bonding pads112bare arranged in respective series (rows) along one peripheral edge of the first surface114of the package substrate110(left edge in the figure), and the third bonding pads112cand the fourth bonding pads112dare arranged in respective series (rows) along the opposite peripheral edge of the first surface114of the package substrate110(right edge in the figure). However, the inventive concept is not limited to these serial arrangements of the bonding pads. For example, the first and second bonding pads112aand112bmay be alternately disposed in a series (row) along one edge of the first surface114of the package substrate110, and the third and fourth bonding pads112cand112dmay be alternately disposed in a series (row) along another of the edges of the first surface114of the package substrate110.

The package substrate110may also include a plurality of bump pads115at the second surface116thereof. In this case, the external connection terminals130a,130b,130c, and130dare coupled to the bump pads115.

The external connection terminals130a,130b,130c, and130dmay be bumps or solder balls. Also, the external connection terminals130a,130b,130c, and130dmay be arrayed along the second surface116of the package substrate110. Accordingly, the multi-channel package100may be a ball grid array (BGA) type of package.

Furthermore, the external connection terminals130a,130b,130c, and130dare divided into at least four groups corresponding to the channels, respectively. For example, the external connection terminals130a,130b,130c, and130dinclude a first external connection terminal group SG1of first external connection terminals130a, a second external connection terminal group SG2of second external connection terminals130b, a third external connection terminal group SG3of third external connection terminals130c, and a fourth external connection terminal group SG4of fourth external connection terminals130d. The first external connection terminal group SG1is electrically connected to the first bonding pad group BG1via the bump pads115and internal wiring/vias (not shown) of the package substrate110, i.e., conductive paths extending within and through the substrate body of the package substrate10. Likewise, the second external connection terminal group SG2and the second bonding pad group BG2, the third external connection terminal group SG3and the third bonding pad group BG3, and the fourth external connection terminal group SG4and the fourth bonding pad group BG4are also respectively electrically connected via the bump pads115and internal wiring/vias.

Each channel is dedicated to one or a group of the semiconductor chips. Therefore, the semiconductor chips120a,120b,120c, and120dcorrespond to at least four channels and may be divided into groups associated with the channels, respectively. For example, the semiconductor chips120a,120b,120c, and120dmay include a first chip group CG1of first semiconductor chips120ato which a first channel is dedicated, a second chip group CG2of second semiconductor chips120bto which a second channel is dedicated, a third chip group CG3of third semiconductor chips120cto which a third channel is dedicated, and a fourth chip group CG4of fourth semiconductor chips120dto which a fourth channel is dedicated. In the illustrated embodiment, each chip group has only two semiconductor chips. However, the inventive concept is not limited to a package in which only two respective semiconductor chips are associated with each of at least four channels. For example, at least three semiconductor chips or only one semiconductor chip may be associated with each channel. Also, the relative locations of the semiconductor chips or groups CG1, CG2, CG3, CG4of the chips may be different than what is illustrated inFIG. 2. For example, the first and third semiconductor chips in a direction away from the package substrate110may constitute the first chip group CG1, and the second and fourth semiconductor chips in a direction away from the package substrate110may constitute the second chip group CG2.

Furthermore, the semiconductor chips120a,120b,120c, and120dmay be memory chips or logic chips. This includes the case in which some of the semiconductor chips120a,120b,120c, and120dare memory chips and the rest are logic chips. In the case in which any of the semiconductor chips120a,120b,120c, and120dis a memory chip, the memory chip may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a phase-change random access memory (PRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FeRAM), or a magnetoresistive random access memory (MRAM). In the example of the present embodiment, the semiconductor chips120a,120b,120c, and120dare all flash memory chips. Thus, memories of each group, i.e., flash memories of each group in this example, share a respective (single) channel. Accordingly, each group of flash memories that is connected to one of the channels may operate independently from the flash memories of each group that is connected to another of the channels.

The first through fourth semiconductor chips120a,120b,120c, and120dhave first through fourth chip pads122a,122b,122c, and122ddisposed along the periphery of upper surfaces of the chip bodies thereof, respectively. That is, first chip pads122aare disposed on the body of each first semiconductor chip120a, second chip pads122bare disposed on the body of each second semiconductor chip120b, third chip pads122care disposed on the body of each third semiconductor chip120c, and fourth chip pads122dare disposed on the body of each fourth semiconductor chip120d. The first through fourth chip pads122a,122b,122c, and122dmay allow signals to be input and/or output to internal circuits of the first through fourth semiconductor chips120a,120b,120c, and120d.

In this example, the first through fourth chips groups CG1, CG2, CG3, CG4form a cascading type of offset stack structure. The first through fourth chip pads122a,122b,122c, and122dare exposed due to this offset arrangement. Also, in this example, the (horizontal) direction in which the chips of the first and second chip groups CG1and CG2are offset in the stack from each other is opposite to the (horizontal) direction in which the chips of the third and fourth chip groups CG3and CG4are offset from each other in the stack. Furthermore, given that the amounts of horizontal offset between adjacent ones of the chips may be equal throughout the stack, an arrangement may be realized in which a fourth semiconductor chip120dis vertically juxtaposed in precise alignment with a second semiconductor chip120b.

The multi-channel chip package100of this embodiment also includes first through fourth connectors140a,140b,140c,140dby which the chip(s) associated with the channels, respectively, are electrically connected to the bonding pad groups BG1, BG2, BG3, BG4, respectively, via the first through fourth chip pads122a,122b,122c,122d, respectively. Using the first connectors140aof the illustrated embodiment as an example, the first semiconductor chips120aof the first chip group CG1are electrically connected to the first bonding pads112aof the first bonding pad group BG1via the first chip pads122aand the first connectors140a. Also, in this example, the first through fourth connectors140a,140b,140c, and140dare metal wires.

The encapsulant150is disposed on the package substrate110and covers the first through fourth semiconductor chips120a,120b,120c, and120d. More specifically, the encapsulant150encapsulates the first through fourth semiconductor chips120a,120b,120c, and120dto protect the same from external physical impacts and/or chemicals. To this end, the encapsulant150may be an epoxy molding compound (EMC).

According to the multi-channel package as described above, signals can be separately input or output to/from each of the first through fourth chips. That is, signals may be separated into four channels to be input or output to/from semiconductor chips, respectively. Accordingly, if a defect occurs in a chip or chip group, just that chip or chip group may be treated as a defect and not the entire multi-channel package. In addition, the multi-channel package can operate at a remarkably high speed because signals can be separately transmitted to the first through fourth chips. This advantages is more pronounced when the inventive concept is embodied as a BGA package, compared to a lead frame package, because BGA packages have a relatively large number of terminals through which signals are transmitted.

Hereinafter, representative reference numerals may be used for like elements for conciseness and ease of description. For instance, any of the first through fourth semiconductor chips120a,120b,120c, and120dmay be simply referred to as a semiconductor chip120, any of the first through fourth bonding pads112a,112b,112c, and112dmay be referred to as a bonding pad112, any of the first through fourth external connection terminals130a,130b,130c, and130dmay be referred to as an external connection terminal130, any of the first through fourth chip pads122a,122b,122c, and122dmay be referred to as a chip pad122, and any of the first through fourth connectors140a,140b,140c,140dmay be referred to as a connector140.

Another embodiment of a multi-channel package100aaccording to the inventive concept will now be described with reference toFIG. 3.

The multi-channel package100ais similar to the multi-channel package100of the embodiment ofFIGS. 1 and 2, but differs in regard to its wiring connection. That is, in the multi-channel package100a, connectors140extend from the chip pads122of only one of the semiconductor chips120constituting a chip group CG. The chip pads of the other semiconductor chip(s)120of that chip group CG are directly connected to the chip pads of the semiconductor chip120adjacent thereto in the stack by separate individual wires. In the embodiment ofFIG. 3, using the first semiconductor chip group CG1as an example, a chip pad122of a lower semiconductor chip120aof the first semiconductor chip group CG1is directly connected to a first bonding pad112avia a first connector140, and a chip pad122of an upper semiconductor chip120ais directly connected to the chip pad122of the lower semiconductor chip120aof the first semiconductor chip group CG1via a separate wire so as to be connected to the first bonding pad112avia those two wires.

The above-described connection structure minimizes the lengths of the connectors140and simplifies the arrangement of the multi-channel package. Furthermore, a phenomena known as wire sweeping is less likely to occur because the loop height of the connector140is minimal.

Another embodiment of a multi-channel package100baccording to the inventive concept will now be described with reference toFIG. 4. Those aspects/features of this embodiment which are similar to those of the embodiment ofFIG. 1will be not be described in detail for the sake of brevity.

Referring toFIG. 4, the semiconductor chips120of the multi-channel package100bare arranged to alternately protrude on opposite sides of the stack. That is, the semiconductor chips120of the multi-channel package100bform a zigzag type of stack structure. For example, the first semiconductor chips120amay be the first and third chips disposed on the substrate110, the second semiconductor chips120bmay be the fifth and seventh chips disposed on the substrate110, the third semiconductor chips120cmay be the second and fourth chips disposed on the substrate110, and the fourth semiconductor chips120dmay be the sixth and eighth chips disposed on the substrate110. In this case, the first and second semiconductor chips120aand120bmay be vertically aligned, the third and fourth semiconductor chips120cand120dmay be vertically aligned, and the aligned first and second semiconductor chips120aand120bmay be (horizontally) offset from the aligned third and fourth semiconductor chips120cand120d. All of the chip pads122are exposed due to the offset arrangement such that the chip pads122can be readily connected to corresponding bonding pads112via connectors140, respectively.

Another embodiment of a multi-channel package100caccording to the inventive concept will now be described with reference toFIG. 5.

The multi-channel package100cincludes an adhesive layer or an underfill125interposed between adjacent ones of the semiconductor chips120in the stack. In this embodiment, the semiconductor chips120are vertically aligned and may be of the same size such that the peripheral surfaces of each chip are aligned with the peripheral surfaces of each of the other chips.

The underfill125provides space between adjacent semiconductor chips. Thus, the chip pads122of the semiconductor chips120may be respectively connected to corresponding bonding pads112via connectors140. The connections between the semiconductor chips120and the bonding pads112may be configured similarly to those illustrated inFIG. 1.

In another example of this embodiment, the first through fourth semiconductor chips120a,120b,120c, and120dare offset in the manner described with reference to the embodiment ofFIG. 4. This provides greater distances between adjacent connectors140, thereby reducing the likelihood that wire sweeping will occur.

Another embodiment of a multi-channel package100daccording to the inventive concept will now be described with reference toFIGS. 6 and 7. Most notably, the multi-channel package100dis different from the multi-channel packages of the above-described embodiments in terms of the stacked structure formed by the semiconductor chips120, the configuration of the connections formed by the connectors140, and the positions of the bonding pads112. Otherwise, the features/aspects of this embodiment are similar to those of the embodiment ofFIG. 1and will not be described in detail.

In the multi-channel package100daccording to the inventive concept, the bonding pads112are disposed along the four sides of the package substrate110. For example, as illustrated inFIG. 7, the first bonding pads112aare disposed along a left side of the package substrate110; the second bonding pads112bare disposed along a front side of the package substrate110; the third bonding pads112care disposed along a right side of the package substrate110; and the fourth bonding pads112dare disposed along a back side of the package substrate110.

Meanwhile, four pairs of semiconductor chips120are (horizontally) offset in the stack in left, right, front, and back directions, respectively. Also, the chips120of each pair are (horizontally) offset from each other in a respective one of the left, right, front, and back directions. For example, two first semiconductor chips120aare stacked with the upper chip offset from the lower chip in a right direction, two third semiconductor chips120care stacked with the upper chip offset from the lower chip in a left direction, two second semiconductor chips120bare stacked with the upper chip offset from the lower chip in the front direction, and two fourth semiconductor chips120dare stacked with the upper chip offset from the lower chip in the back direction.

Accordingly, the chip pads122of the semiconductor chips120are exposed at the right, left, front and back sides of the stack. More specifically, chip pads122aof the first semiconductor chips120aare provided at the left sides of the first semiconductor chips120aand are exposed at a left side of the stack; chip pads122bof the second semiconductor chips120bare provided at the front sides of the second semiconductor chips120band are exposed at the front side of the stack; third chip pads122cof the third semiconductor chips120care provided at the right sides of the third semiconductor chips120cand are exposed at the right side of the stack; and fourth chip pads122dof the fourth semiconductor chips120dare provided at the back sides of the fourth semiconductor chips120dand are exposed at the back side of the stack. Therefore, the chip pads122may be readily connected to corresponding bonding pads112via connectors140in a manner similar to that shown in and described with reference toFIG. 1or, as illustrated, in a manner similar to that shown in and described with reference toFIG. 3.

Another embodiment of a multi-channel package100eaccording to the inventive concept will now be described with reference toFIGS. 8 and 9. As in the detailed description of the previous embodiments, features/aspects of this embodiment which are shown in the figures and are similar to those described above will not be described again in further detail.

Referring toFIGS. 8 and 9, in the multi-channel package100c, semiconductor chips120are stacked by using adhesive layers or underfill125therebetween. Also, the connectors that connect the chip pads122and the bonding pads112are silicon vias (TSVs)160a,160b,160c, and160d.

More specifically, as best shown inFIG. 9, in this example, the bonding pads112are disposed along four edge sides of the package substrate110. Furthermore, chip pads122aof the first semiconductor chips120aare provided along left sides of the first semiconductor chips120a, chip pads122bof the second semiconductor chips120bare provided along front sides of the second semiconductor chips120b, chip pads122cof the third semiconductor chips120care provided along right sides of the third semiconductor chips120c, and chip pads122dof the fourth semiconductor chips120dare provided along back sides of the fourth semiconductor chips120d. Still further, the TSVs160a,160b,160c, and160dhave different lengths. In this respect, first TSVs160apass through only two chips, namely, the first semiconductor chips120a, to connect the first chip pads122aof the first semiconductor chip120ato the first bonding pads112a. Second TSVs160b(only two of which are shown inFIG. 8) pass through only four chips, namely, semiconductor chips120aand120b, to connect the second chip pads122bof the second semiconductor chips120bto the second bonding pads112b. Third TSVs160cpass through only six chips, namely, semiconductor chips120a,120band120c, to connect the third chip pads122cof the third semiconductor chips120cto the third bonding pads112c. And fourth TSVs160d(only two of which are also shown inFIG. 8) pass through all eight chips, namely, semiconductor chips120a,120b,120cand120d, to connect the fourth chip pads122dof the fourth semiconductor chips120dto the fourth bonding pads112d.

In another example of this embodiment, all of the TSVs160a,160b,160c, and160dpass through each of the semiconductor chips120like the fourth TSVs160d. In this case, the TSVs160a,160b,160c, and160dmay be formed at once after all of the semiconductor chips120have been stacked. Accordingly, the packaging process is relatively simple so that time and costs are saved.

In some instances, dummy pads may be provided on the semiconductor chips120, and the TSVs160are formed to extend through the dummy pads. Dummy pads refer to conductive pads that are not electrically connected to circuits of the semiconductor chips120. For example, dummy pads may be provided on the left sides of the second through fourth semiconductor chips120b,120c, and120dso that the first TSVs160apass through the first chip pads122aof the first semiconductor chips120aand the dummy pads of the second through fourth semiconductor chips120b,120c, and120d. In this case, the dummy pads may be used to align the semiconductor chips120while the semiconductor chips120are being stacked.

Another embodiment of a multi-channel package100faccording to the inventive concept will be described with reference toFIG. 10. In this embodiment, as was mentioned above, only one semiconductor chip120is associated with each at least four channels. Furthermore, each chip may be (horizontally) offset relative to the chip on which it is directly disposed.

Yet another embodiment of a multi-channel package100gaccording to the inventive concept will be described with reference toFIG. 11.

The multi-channel package100gof this embodiment has more than four channels. In this embodiment, the multi-channel package100ghas eight chips or chip groups, eight bonding pad groups, and eight external connection terminal groups. More specifically, in the illustrated example of this embodiment, each of eight semiconductor chips120athrough120his associated with a respective channel.

Furthermore, the chips120are stacked and the bonding pads112are disposed on package substrate110in a manner similar to that shown in and described with reference toFIGS. 6 and 7. However, in this case, two rows bonding pads112are provided along each of four sides of the package substrate110, and the chip pads122of each of the eight semiconductor chips120are connected to the bonding pads112of a respective one of the rows thereof via connectors140.

Another embodiment of a multi-channel package100haccording to the inventive concept will be described with reference toFIGS. 12 and 13.

The multi-channel package100hincludes at least one embedded control chip200mounted on the first surface114of package substrate110. For example, a respective embedded control chip200may be provided for each channel, or for every two channels, or for every four channels. In the example of the current embodiment, four channels are provided, and one embedded control chip200is provided for the four channels.

The embedded control chip(s)200controls the semiconductor chips120. For example, the embedded control chip200may perform error correction code (ECC) and flash translation layer (FTL) processing to increase the performance and reliability of memories constituted by the chips120. Here, FTL processing may include logical/physical address translation, wear leveling, garbage collection, bad block management or control.

In addition, the embedded control chip200allows the multi-channel package100hto be used in an external memory card.

Also, in the example of this embodiment, the package substrate110has control chip bonding pads112edisposed on first surface114of the substrate body thereof, and the embedded control chip200has control chip pads210electrically connected to the control chip bonding pads112evia connectors, that is, control chip bonding wires220. The control chip bonding pads112emay be electrically connected to the bonding pads112of the package substrate110via internal wings of the package substrate110. Accordingly, the first through fourth semiconductor chips120a,120b,120c, and120dmay be electrically connected to the embedded control chip200. Also, the embedded control chip200may be electrically connected to external connection terminals130via the control chip bonding pads112e.

Still further, the external connection terminals130disposed on the second surface116of package substrate110do not have to be arranged in groups associated with the first through fourth chip groups CG1, CG2, CG3, and CG4, respectively, in this embodiment. Rather, the first through fourth chip groups CG1, CG2, CG3, and CG4may still be respectively connected to first through fourth bonding groups BG1, BG2, BG3, and BG4of the package substrate110via the embedded control chip(s). Accordingly, the connections to the first through fourth chip groups CG1, CG2, CG3, and CG4via the embedded control chip(s)200may be controlled to cut off a chip group(s) that is/are defective.

A memory card7000according to the inventive concept will be described with reference toFIG. 14. The memory card7000may be a memory stick card, a smart media card (SM), a secure digital (SD), a mini secure digital card (mini SD), or a multi media card (MMC).

The memory card7000includes a controller7100, and a memory7200operatively connected to the controller7100to be controlled by the controller7100. For example, when the controller7100issues a command, the memory7200may transmit data. The memory7200may include a memory array (not shown) or a memory array bank (not shown). The controller7100and/or the memory7200include(s) a multi-channel package of any of the types described above with reference toFIGS. 1 through 13.

An electronic system8000according to the inventive concept will now be described with reference toFIG. 15. The electronic system8000may be employed by a mobile system such as a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile pone, a digital music player such as an MP3 player, or a memory card. The electronic system8000may also be used in a navigation device, a portable multimedia player (PMP), or a solid state drive (SSD), or in household appliances.

The electronic system8000of this embodiment includes a controller8100, an input/output device8200, a memory8300, and an interface8400. The electronic system8000may also include a bus8500via which the controller8100, the input/output device8200, the memory8300, and the interface8400communicate with one another.

The controller8100executes programs and controls the electronic system8000. The controller8100is, for example, a microprocessor, a digital signal processor, a microcontroller, or the like. The input/output device8200is configured to input or output data to or from the electronic system8000. In this respect, the input/output device8200may be a keypad, a keyboard, or a display. The electronic system8000may be connected by the input/output device8200to an external apparatus such as a personal computer or a network so as to exchange data with the external apparatus.

The memory8300may store code and/or data for operating the controller8100and/or store the data processed by using the controller8100. The controller8100and the memory8300may include a multi-channel package of any of the types described with reference toFIGS. 1 through 13.

The interface8400provides a data transmission path between the electronic system8000and another external device or devices.

In addition, the operational speed of the electronic system8000is relatively high because the multi-channel package according to the inventive concept includes four channels. This will be described in more detail below with reference toFIGS. 16 through 22.

An electronic system according to the inventive concept and embodied as an SSD1000will now be described with reference toFIGS. 16 and 17.

The SSD1000includes at least one multi-channel package100according to the inventive concept, an SSD controller3000, a DRAM400, and a main board500. Furthermore, the SSD1000may include an interface520for communicating with an external device. The interface520may be formed at one side of the main board500.

The multi-channel package(s)100is/are mounted on the main board500via external connection terminals (130) with reference to the previous figures. The connection terminals may be bumps or solder balls in a ball grid array (BGA). However, the multi-channel package100may be embodied in other ways concerning the manner in which it is mounted to the main board500. For example, the multi-channel package100may be realized in the form of a pin grid array (PGA) package, a tape carrier package (TCP), a chip-on-board (COB) structure, a quad flat non-leaded (QFN) structure, or a quad flat package (QFP).

In the embodiment illustrated inFIGS. 16 and 17, two multi-channel packages PKG1and PKG2are provided. That is, if the SSD controller300supports eight or more channels, two or more multi-channel packages100may be provided.

In any case, each channel of the multi-channel package100includes a signal terminal. The signal terminals may be external connection terminals. InFIG. 17, I/O0-7denote eight input/output terminals, and data, address, and command signals are input or output via the input/output terminals I/O0-7. On the other hand, CE0-8are terminals through which control signals, e.g., nRE (read enable), CLE (command latch enable), ALE (address latch enable), nWP (write enable), nWP (write protect), R/B 1 (read/busy out), R/B 2, nCE 1 (chip enable), or nCE 2, are transmitted. In addition to the I/O terminals and the CE terminals, each channel may include a Vcc terminal through which power is supplied and a Vss terminal through which a ground voltage is applied. Also, each channel may further include a not connected (N.C.) dummy terminal which is not connected to any circuit.

As briefly alluded to above, the SSD controller300may include eight channels as illustrated inFIG. 17, and which are respectively connected to respective channels of the multi-channel packages PKG1and PKG2to control semiconductor chips of the multi-channel packages PKG1and PKG2. However, the inventive concept may be applied to an SSD whose SSD controller300includes fewer or greater than eight channels. For example, the SSD controller300may include sixteen channels, and in this case, four multi-channel packages each including four channels may be provided or two multi-channel packages each including eight channels may be provided.

The SSD controller300may include a program via which a signal may be transmitted or received to/from an external device according to any serial advanced technology attachment (SATA) standard, parallel advanced technology attachment (PATA) standard, or small computer system interface (SCSI) standard. The SATA standards referenced may include not only the so-called SATA-1 standard but also the SATA-2, SATA-3, and e-SATA (external SATA) standards. The PATA standards referenced include all kinds of integrated drive electronics (IDE) standards such as IDE standards, and enhanced-IDE (E-IDE) standards.

In addition, the SSD controller300may perform EEC or FTL processing. The SSD controller300may also be embodied as a package mounted on the main board500. In this respect, the SSD controller300may be realized in a package form like that of the multi-channel package100, i.e., may be realized as a BGA package, a PGA package, a TCP structure, a COB structure, a QFN structure, or a QFP.

The DRAM400is an auxiliary memory device and may function as a buffer in terms of the exchanging of data between the SSD controller300and the multi-channel package100. The DRAM400may also be embodied as a package mounted to the main board500and so, may be in the form of a BGA package, a PGA package, a TCP structure, a COB structure, a QFN structure, or a QFP, etc.

The main board500may be a printed circuit board, a flexible printed circuit board, a tape substrate, or the like. The main board500may include a core (not shown) having upper and lower surfaces and a resin layer (not shown) formed on each of the upper and lower surfaces of the core. Also, the printed circuit board may have a multi-layered structure in which a signal layer, a ground layer, and a power layer, that form wiring patterns, are interposed between the outermost resin layers. An additional wiring pattern may be formed on one or both of the outermost resin layers. InFIG. 16the minute patterns shown on the main board500illustrate may such a wiring pattern. Alternatively, these markings may denote various passive electronic components.

As illustrated inFIG. 17, channels of the SSD controller300are respectively connected to corresponding channels of the multi-channel package100, and thus data input to and output from the semiconductor chips of the multi-channel package100may be controlled in parallel. Also, as described above, in this example of an electronic system, each multi-channel package100includes four channels, and two multi-channel packages providing eight channels are mounted on the main board500.

If the memory packages of the SSD of this example were to have only one or two channels, four or eight memory packages would have to be mounted to the SSD controller. In such a case, the wiring between the memory package and the SSD controller would have to be relatively long and thus, would offer an impediment with regard to the high speed operation of the SSD. For example, if four two channel memory packages were arranged in a row, and the memory packages were of the same size as those of the multi-channel packages PKG1and PKG2of the current embodiment, the wires leading to the third and fourth two channel memory packages from the SSD controller, especially the wires leading to the fourth two channel memory package located away from the SSD controller300, would hinder a high speed operation of the SSD.

In addition to facilitating a high speed operation of the SSD, the memory packages according to the inventive concept can help realize smaller products without compromising their integration density.

Another example of an SSD1000aaccording to the inventive concept will be described with reference toFIGS. 18 and 19. However, those features/aspects of the SSD1000awhich are similar to those of the embodiment ofFIGS. 16 and 17will not be described in complete detail hereinafter, for the sake of brevity.

Referring toFIGS. 18 and 19, the SSD device1000ais similar to the SSD device1000ofFIGS. 16 and 17but further includes a memory controller package PKG3600. The memory controller package PKG3600is a component in which embedded controller chips200of the type described above with reference toFIG. 12are packaged independently from the multi-channel package(s)100, and which is mounted on the main board500. The memory controller package PKG3600of this example is disposed between a multi-channel package100and the SSD controller300.

Furthermore, the chip input capacitance Cin in the SSD device1000ais minimal. Chip input capacitance Cin refers to capacitance that is present when a controller operates a memory package, and is equal to the sum of the capacitance of the package substrate and capacitances of the chips of the package. Thus, the chip input capacitance Cin is higher the greater the number of chips in the package. However, in the SSD device1000aaccording to the inventive concept, the SSD controller300access just up to the memory controller package600, and thus the chip input capacitance Cin is established by the memory controller package600. Accordingly, even though the memory package(s) may each have a fairly large number of semiconductor chips (at least four), the chip input capacitance Cin may be minimized to some extent. The minimized wiring lengths and the low chip input capacitance Cin allow the SSD device1000ato operate at a relatively high speed and to offer high performance.

Still another example of an SSD1000baccording to the inventive concept will be described with reference toFIG. 20.

The SSD1000bis similar to the SSD1000ofFIG. 16but differs from the SSD1000with regard to the structure of each multi-channel package. Specifically, the SSD1000bincludes a multi-channel package(s)100hof the type described with reference toFIG. 12in which the embedded controller chip200is packaged (e.g., encapsulated) along with the memories.

Another example of an SSD1000caccording to the inventive concept will be described with reference toFIG. 21.

The SSD1000chas a multi-channel package100gincluding eight channels as distinguished from the other examples of the SSDs according to the inventive concept. The multi-channel package100gmay be of the type described with reference toFIG. 11. However, the structure of the multi-channel package100gis not limited to having the configuration of the multi-channel package100fofFIG. 11. Furthermore, more than one multi-channel package100gmay be provided. For example, if the SSD controller300includes sixteen channels, the SSD device1000cmay include two multi-channel packages100g.

The lengths of the wiring are minimal in this example, however, because the SSD100cincludes only one multi-channel package100gcompared to a corresponding SSD in which four memory packages are provided in alignment Accordingly, the SSD1000ccan operate at a relatively high speed.

Still another example of an SSD1000daccording to the inventive concept will be described with reference toFIG. 22.

The SSD1000dincludes a multi-channel package100ghaving eight channels, like the SSD1000cofFIG. 21, and a memory controller package600as like the SSD1000aofFIG. 18. Thus, this SSD1000dhas the advantages described with reference toFIGS. 18,19and21.

In the examples of SSDs ofFIGS. 18 and 22described above, the memory controller package600is shown and described as having only two chips such that each chip takes charge of (controls the transmission of signals/data through) four channels. However, these SSDs according to the inventive concept may instead have a memory controller package of a type illustrated inFIGS. 23A through 23D.

Referring toFIG. 23A, for example, the memory controller package600amay include one semiconductor chip that takes charge of eight channels. Alternatively, as illustrated inFIG. 23B, the memory controller package600bmay have two semiconductor chips each of which takes charge of four respective channels. Furthermore, as illustrated inFIG. 23C, the memory controller package600cmay include four semiconductor chips each of which takes charge of two respective channels. As illustrated inFIG. 23D, the memory controller package600cmay include eight semiconductor chips each of which takes charge of one respective channel.

Finally, embodiments of the inventive concept and examples thereof have been described above in detail. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments were described so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Thus, the true spirit and scope of the inventive concept is not limited by the embodiment and examples described above but by the following claims.