Organic light emitting diode display

An organic light emitting diode display is disclosed that includes a shield layer on a substrate; a semiconductor layer on the shield layer; a gate insulating layer on the semiconductor layer; a first gate electrode on the gate insulating layer; a first interlayer dielectric layer on the first gate electrode; a second gate electrode and a connection electrode on the first interlayer dielectric layer, the connection electrode electrically connected to the shield layer and passing through the semiconductor layer; a second interlayer dielectric layer on the second gate electrode and the connection electrode; a source electrode and a drain electrode on the second interlayer dielectric layer, the drain electrode electrically connected to the semiconductor layer and the source electrode electrically connected to the connection electrode; an insulating layer on the drain electrode and the source electrode; and a first electrode on the insulating layer and electrically connected to the source electrode.

This application claims the priority benefit of Korean Patent Application No. 10-2015-0123247 filed on Aug. 31, 2015, which is incorporated herein by reference for all purposes as if fully set forth herein.

BACKGROUND

Field of the Invention

The present disclosure relates to an organic light emitting diode (OLED) display and a method of manufacturing the same, and more particularly, to a high-resolution OLED display.

Discussion of the Related Art

Various flat panel displays (FPDs) have been recently developed, replacing cathode ray tubes (CRTs) that are heavy and large in size. Examples of flat panel displays include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an organic light emitting diode (OLED) display.

An OLED display is a self-emission display device configured to emit light by exciting an organic compound. The OLED display typically does not require a backlight unit, which is used in an LCD device, and thus, can be implemented with thin profile and lightweight by a simplified manufacturing process. The OLED display can be also manufactured at a low temperature and has many advantages such as fast response time of 1 ms or less, low power consumption, wide viewing angle and high contrast.

The OLED display typically includes a light emitting layer of an organic material between a first electrode serving as an anode and a second electrode serving as a cathode. The OLED display forms hole-electron pairs, excitons, by combining the holes received from the first electrode and the electrons received from the second electrode inside the light emitting layer and emits light according to an energy generated when the excitons return to a ground or lower energy level.

As the display technology is advancing, user demands continue to increase. In particular, the pixel size may need to be gradually decreased so as to meet the demand for a high-resolution display device. However, because the OLED display according to the related art has many contact holes in its pixel structure, it may be difficult to decrease the pixel size and increase the resolution of the OLED display.

SUMMARY

Accordingly, embodiments relate to an organic light emitting diode display comprising a shield layer on a substrate; a semiconductor layer on the shield layer; a gate insulating layer on the semiconductor layer; a first gate electrode on the gate insulating layer; a first interlayer dielectric layer on the first gate electrode; a second gate electrode and a connection electrode on the first interlayer dielectric layer, the connection electrode electrically connected to the shield layer and passing through the semiconductor layer; a second interlayer dielectric layer on the second gate electrode and the connection electrode; a source electrode and a drain electrode on the second interlayer dielectric layer, the drain electrode electrically connected to the semiconductor layer and the source electrode electrically connected to the connection electrode; an insulating layer on the drain electrode and the source electrode; and a first electrode on the insulating layer and electrically connected to the source electrode.

The connection electrode is connected to the shield layer through a first contact hole passing through the first interlayer dielectric layer, the gate insulating layer, the semiconductor layer, and the buffer layer.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. It will be paid attention that detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the invention.

A display device according to an embodiment of the invention is a plastic display device, in which a display element is formed on a flexible plastic substrate. Examples of the plastic display device include an organic light emitting diode (OLED) display, a liquid crystal display (LCD), and an electrophoresis display. Embodiments of the present invention are described using a plastic OLED display by way of example, but the present invention is not limited thereto.

An OLED display includes a light emitting layer of an organic material between a first electrode serving as an anode and a second electrode serving as a cathode. The OLED display is a self-emission display device configured to form hole-electron pairs, excitons, by combining the holes received from the first electrode and the electrons received from the second electrode inside the light emitting layer and emit light according to an energy generated when the excitons return to a ground or lower energy level. The OLED display according to an embodiment of the invention may use a glass substrate as well as a plastic substrate.

FIG. 1is a schematic block diagram of an organic light emitting diode (OLED) display.FIG. 2illustrates a first example of a circuit configuration of a subpixel.FIG. 3illustrates a second example of a circuit configuration of a subpixel.

Referring toFIG. 1, an OLED display according to an embodiment of the invention includes an image processing unit10, a timing controller20, a data driver30, a gate driver40, and a display panel50.

The image processing unit10outputs a data signal DATA and a data enable signal DE supplied from the outside. The image processing unit10may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE. For the sake of brevity and ease of reading, these signals are not shown. The image processing unit10is formed on a system circuit board in an integrated circuit (IC) form.

The timing controller20receives the data signal DATA and driving signals including the data enable signal DE or the vertical sync signal, the horizontal sync signal, the clock signal, etc. from the image processing unit10. The timing controller20outputs a gate timing control signal GDC for controlling operation timing of the gate driver40and a data timing control signal DDC for controlling operation timing of the data driver30based on the driving signals. The timing controller20is formed on a control circuit board in an IC form.

The data driver30samples and latches the data signal DATA received from the timing controller20in response to the data timing control signal DDC supplied from the timing controller20and converts the sampled and latched data signal DATA using gamma reference voltages. The data driver30outputs the converted data signal DATA to data lines DL1to DLn. The data driver30is formed on a data circuit substrate in an IC form.

The gate driver40outputs a gate signal while shifting a level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller20. The gate driver40outputs the gate signal to gate lines GL1to GLm. The gate driver40is formed on a gate circuit board in an IC form or is formed on the display panel50in a gate-in panel (GIP) manner

The display panel50displays an image in response to the data signal DATA and the gate signal respectively received from the data driver30and the gate driver40. The display panel50includes subpixels SP for displaying an image

Referring toFIG. 2, each subpixel includes a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode (OLED). The OLED operates to emit light based on a driving current generated by the driving transistor DR.

The switching transistor SW performs a switching operation so that a data signal supplied through a first data line DL1is stored in a capacitor as a data voltage in response to a gate signal supplied through a first gate line GL1. The driving transistor DR enables a driving current to flow between a high potential power line VDD and a low potential power line GND based on the data voltage stored in the capacitor. The compensation circuit CC is a circuit for compensating for a threshold voltage of the driving transistor DR. A capacitor connected to the switching transistor SW or the driving transistor DR may be mounted inside the compensation circuit CC.

The compensation circuit CC includes one or more thin film transistors (TFTs) and a capacitor. Configuration of the compensation circuit CC may be variously changed depending on a compensation method. A detailed description thereof may be briefly made or may be entirely omitted.

As shown inFIG. 3, the subpixel including the compensation circuit CC may further include a signal line and a power line for driving a compensation TFT and supplying a predetermined signal or electric power. The added signal line may be defined as a 1-2 gate line GL1bfor driving the compensation TFT included in the subpixel. InFIG. 3, “GL1a” is a 1-1 gate line for driving the switching transistor SW. The added power line may be defined as an initialization power line INIT for initializing a predetermined node of the subpixel at a predetermined voltage. However, this is merely an example, and the embodiment of the invention is not limited thereto.

FIGS. 2 and 3illustrate that one subpixel includes the compensation circuit CC by way of example. However, the compensation circuit CC may be omitted when an object (for example, the data driver30) to be compensated is positioned outside the subpixel. The subpixel has a configuration of 2T(Transistor)1C(Capacitor) in which the switching transistor SW, the driving transistor DR, the capacitor, and the OLED are provided. However, when the compensation circuit CC is added to the subpixel, the subpixel may have various configurations such as 3T1C, 4T2C, 5T2C, 6T2C, 7T2C, and the like.

Also,FIGS. 2 and 3illustrate that the compensation circuit CC is positioned between the switching transistor SW and the driving transistor DR by way of an example. However, the compensation circuit CC may be further positioned between the driving transistor DR and the OLED. The position and the structure of the compensation circuit CC are not limited to the ones illustrated inFIGS. 2 and 3.

Hereinafter, various subpixel structures, in which the above-described driving transistor DR and the above-described organic light emitting diode are connected, will be described.

First Embodiment

FIG. 4is a plan view illustrating a part of an OLED display according to a first embodiment of the invention.FIG. 5is a cross-sectional view taken along line I-I′ ofFIG. 4.

Referring toFIG. 4, a driving transistor DR and a first electrode160are connected to each other on a substrate110. The driving transistor DR includes a semiconductor layer120on a shield layer114, a first gate electrode130corresponding to the semiconductor layer120, a second gate electrode135separated from the first gate electrode130at a location corresponding to the first gate electrode130, and a drain electrode140and a source electrode145respectively connected to both sides of the semiconductor layer120.

The drain electrode140of the driving transistor DR is connected to the semiconductor layer120through a second contact hole CH2, and the source electrode145of the driving transistor DR is connected to the semiconductor layer120through a third contact hole CH3. Further, the source electrode145is connected to a connection electrode132through a fourth contact hole CH4, and the connection electrode132is connected to the shield layer114through a first contact hole CH1. Hence, the source electrode145is electrically connected to the shield layer114. The source electrode145of the driving transistor DR is connected to the first electrode160through a fifth contact hole CHS. The first electrode160is exposed by an opening OP of a bank layer (not shown).

More specifically, referring toFIG. 5, in the OLED display100according to the first embodiment of the invention, a first buffer layer112is positioned on the substrate110. The first buffer layer112serves to protect a thin film transistor (TFT) formed in a subsequent process from impurities, for example, alkali ions discharged from the substrate110. The shield layer114is positioned on the first buffer layer112. The shield layer114serves to reduce or prevent reduction in a panel driving current which may be generated by using a substrate formed of polyimide. A second buffer layer116is positioned on the shield layer114. The second buffer layer116serves to protect a TFT formed in a subsequent process from impurities, for example, alkali ions discharged from the shield layer114.

The semiconductor layer120is positioned on the second buffer layer116. The semiconductor layer120may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. The polycrystalline silicon has a high mobility (for example, 100 cm2/Vs or more), low energy power consumption, and excellent reliability, and thus may be applied to a gate driver and/or a multiplexer (MUX) for use in a driving element or applied to a driving TFT of each pixel of the OLED display100. Because the oxide semiconductor has a low off-current, the oxide semiconductor is suitable for a switching TFT which has a short on-time and a long off-time. Further, because the oxide semiconductor increases a voltage hold time of the pixel due to the low off-current, the oxide semiconductor is suitable for a display device with a slow driving and/or low power consumption. The semiconductor layer120includes a drain region123and a source region124each including p-type or n-type impurities and a channel121between the drain region123and the source region124. The semiconductor layer120further includes a lightly doped region122between the drain region123and the source region124adjacent to the channel121.

A gate insulating layer GI is positioned on the semiconductor layer120. The first gate electrode130is positioned on the gate insulating layer GI in a predetermined portion of the semiconductor layer120, namely, at a location corresponding to the channel121when impurities are injected. The first gate electrode130serves as a gate electrode of the driving transistor DR. The connection electrode132is positioned on one side of the first gate electrode130. The connection electrode132is connected to the shield layer114through the first contact hole CH1passing through the gate insulating layer GI and the second buffer layer116. The connection electrode132is positioned on the same layer as the first gate electrode130.

A first interlayer dielectric layer ILD1is positioned on the first gate electrode130to insulate the first gate electrode130. The second gate electrode135is positioned on the first interlayer dielectric layer ILD1. The second gate electrode135is a capacitor electrode forming a capacitor together with the first gate electrode130and does not operate as a gate electrode of the driving transistor DR. A second interlayer dielectric layer ILD2is positioned on the second gate electrode135to insulate the second gate electrode135. The second and third contact holes CH2and CH3are positioned in a portion of each of the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulating layer GI to expose a portion of the semiconductor layer120. More specifically, the second contact hole CH2exposes the drain region123of the semiconductor layer120, and the third contact hole CH3exposes the source region124of the semiconductor layer120. The fourth contact hole CH4is positioned in a portion of each of the second interlayer dielectric layer ILD2and the first interlayer dielectric layer ILD1to expose the connection electrode132.

The drain electrode140and the source electrode145are positioned on the second interlayer dielectric layer ILD2. The drain electrode140is connected to the semiconductor layer120through the second contact hole CH2exposing the drain region123of the semiconductor layer120. The source electrode145is connected to the semiconductor layer120through the third contact hole CH3exposing the source region124of the semiconductor layer120. Further, the source electrode145is connected to the connection electrode132through the fourth contact hole CH4, which is formed by penetrating the second interlayer dielectric layer ILD2and the first interlayer dielectric layer ILD1and exposes the connection electrode132. Thus, the driving transistor DR including the semiconductor layer120, the first gate electrode130, the drain electrode140, and the source electrode145is formed.

A passivation layer PAS is positioned on the substrate110including the driving transistor DR. A planarization layer PLN is positioned on the passivation layer PAS to planarize the parts underlying the planarization layer PLN. The fifth contact hole CH5is positioned in a portion of each of the passivation layer PAS and the planarization layer PLN to expose the source electrode145. The first electrode160is positioned on the planarization layer PLN. The first electrode160serves as a pixel electrode and is connected to the source electrode145of the driving transistor DR through the fifth contact hole CH5. A bank layer BNK is positioned on the substrate110including the first electrode160to define the pixel. The bank layer BNK includes the opening OP exposing the first electrode160. A light emitting layer170contacting the first electrode160is positioned in the opening OP of the bank layer BNK, and a second electrode180is positioned on the light emitting layer170.

The OLED display100according to the first embodiment of the invention includes the first contact hole CH1and the fourth contact hole CH4so as to connect the shield layer114to the source electrode145of the driving transistor DR.

A method for manufacturing the OLED display according to the first embodiment of the invention will now be described.FIGS. 6A to 6Lare cross-sectional views sequentially illustrating a method for manufacturing the OLED display according to the first embodiment of the invention.

Referring toFIG. 6A, a substrate110is prepared. The substrate110is made of glass, plastic, or metal, etc. In the embodiment of the invention, the substrate110may be made of plastic, and more particularly, may be a polyimide substrate. Thus, the substrate110according to the embodiment of the invention may be flexible.

A first buffer layer112is formed on the substrate110. The first buffer layer112may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof. The first buffer layer112may be formed using a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, and the like. Subsequently, an opaque material is stacked on the first buffer layer112and is patterned using a first mask to form a shield layer114. The shield layer114may be formed of a conductive material, a semiconductor such as silicon, a metal, and the like.

Next, referring toFIG. 6B, a second buffer layer116is formed on the substrate110, on which the shield layer114is formed. The second buffer layer116may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof through the CVD method, the PECVD method, and the like. Subsequently, a silicon semiconductor or an oxide semiconductor is stacked on the second buffer layer116and is patterned using a second mask to form a semiconductor layer120.

Next, referring toFIG. 6C, a gate insulating layer GI is formed on the substrate110including the semiconductor layer120. The gate insulating layer GI may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof through the CVD method, the PECVD method, and the like. Subsequently, the second buffer layer116and the gate insulating layer GI are etched using a third mask to form a first contact hole CH1exposing the shield layer114.

Next, referring toFIG. 6D, a metal material is stacked on the substrate110, in which the first contact hole CH1is formed, and is patterned using a fourth mask to form a first gate electrode130and a connection electrode132. The first gate electrode130and the connection electrode132are formed of one selected from the group including molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. Further, each of the first gate electrode130and the connection electrode132may be a multilayer formed of one selected from the group including molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. For example, each of the first gate electrode130and the connection electrode132may be formed as a double-layer of Mo/Al—Nd or Mo/Al. The connection electrode132is connected to the shield layer114through the first contact hole CH1.

Subsequently, n-type impurities are lightly doped on a front surface of the substrate110to dope the semiconductor layer120. In this instance, a remaining portion of the semiconductor layer120except the semiconductor layer120underlying the first gate electrode130is doped using the first gate electrode130on the semiconductor layer120as a mask.

Next, referring toFIG. 6E, n-type impurities are heavily doped on the front surface of the substrate110to dope the semiconductor layer120. In this instance, a channel121, a lightly doped region122, a drain region123, and a source region124are formed at the semiconductor layer120by masking and doping a predetermined region of the semiconductor layer120using a fifth mask.

Next, referring toFIG. 6F, a first interlayer dielectric layer ILD1is formed on the substrate110, on which the first gate electrode130and the connection electrode132are formed. The first interlayer dielectric layer ILD1may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof through the CVD method, the PECVD method, and the like. Subsequently, a metal material is stacked on the substrate110and patterned using a sixth mask to form a second gate electrode135. The second gate electrode135is formed to overlap the first gate electrode130and may form a capacitance together with the first gate electrode130.

Next, referring toFIG. 6G, a second interlayer dielectric layer ILD2is formed on the substrate110, on which the second gate electrode135is formed. The second interlayer dielectric layer ILD2may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof through the CVD method, the PECVD method, and the like. Subsequently, a photoresist is applied to the second interlayer dielectric layer ILD2, and the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulating layer GI are etched using a seventh mask. A second contact hole CH2exposing the drain region123of the semiconductor layer120and a third contact hole CH3exposing the source region124of the semiconductor layer120are formed by etching the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulating layer GI. Further, the second interlayer dielectric layer ILD2and the first interlayer dielectric layer ILD1are etched to form a fourth contact hole CH4exposing the connection electrode132.

Next, referring toFIG. 6H, a metal material is stacked on the substrate110, on which the second interlayer dielectric layer ILD2is formed, and is patterned using an eighth mask to form a drain electrode140and a source electrode145. The drain electrode140and the source electrode145may be formed as a single layer or a multilayer. When the drain electrode140and the source electrode145are formed as a single layer, the drain electrode140and the source electrode145may be formed of one selected from the group including molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. When the drain electrode140and the source electrode145are formed as a multilayer, the drain electrode140and the source electrode145may be formed as a double-layer of Mo/Al—Nd or a triple-layer of Ti/Al/Ti, Mo/Al/Mo or Mo/Al—Nd/Mo.

The drain electrode140is connected to the drain region123of the semiconductor layer120through the second contact hole CH2, and the source electrode145is connected to the source region124of the semiconductor layer120through the third contact hole CH3. Further, the source electrode145is connected to the connection electrode132through the fourth contact hole CH4. Thus, a driving transistor DR including the semiconductor layer120, the first gate electrode130, the drain electrode140, and the source electrode145is formed.

Next, referring toFIG. 6I, a passivation layer PAS is formed on the substrate110including the driving transistor DR. The passivation layer PAS may be formed as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof through the CVD method, the PECVD method, and the like. Subsequently, a fifth contact hole CH5exposing the source electrode145is formed by etching the passivation layer PAS using a ninth mask.

Next, referring toFIG. 6J, a planarization layer PLN is formed on the substrate110, in which the fifth contact hole CH5is formed. The planarization layer PLN may be a planarization layer for reducing a height difference of an underlying structure. The planarization layer PLN may be formed of an organic material, such as polyimide, benzocyclobutene-based resin, and acrylate. The planarization layer PLN may be formed through a spin-on glass (SOG) method in which an organic material in a liquid state is coated and then cured. Subsequently, the fifth contact hole CH5of the passivation layer PAS extends by etching the planarization layer PLN using a tenth mask.

Next, referring toFIG. 6K, a transparent conductive layer is stacked on the planarization layer PLN and is patterned using an eleventh mask to form a first electrode160. The first electrode160is an anode and may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). When the first electrode160is a reflective electrode, the first electrode160further includes a reflective layer. The reflective layer may be formed of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), Pd (palladium) or a combination thereof. Preferably, the reflective layer may be formed of Ag/Pd/Cu (APC) alloy. Thus, the first electrode160is filled in the fifth contact hole CH5and may be connected to the source electrode145of the driving transistor DR.

Next, referring toFIG. 6L, a bank layer BNK and a spacer SP are formed on the substrate110including the first electrode160. The bank layer BNK is a pixel definition layer that exposes a portion of the first electrode160and defines a pixel, and the spacer SP serves to reduce or prevent a mask from contacting the substrate when a light emitting layer is formed in a subsequent process. The bank layer BNK and the spacer SP may be formed of an organic material, such as polyimide, benzocyclobutene-based resin, and acrylate. An opening OP exposing the first electrode160is formed in the bank layer BNK using a halftone mask, a twelfth mask, and the spacer SP is patterned. An organic light emitting layer170is formed on the first electrode160exposed by the opening OP of the bank layer BNK. The organic light emitting layer170is a layer in which electrons and holes combine and emit light. A hole injection layer or a hole transport layer may be positioned between the organic light emitting layer170and the first electrode160, and an electron injection layer or an electron transport layer may be positioned on the organic light emitting layer170.

Subsequently, a second electrode180is formed on the substrate110on which the organic light emitting layer170is formed. The second electrode180is a cathode electrode formed on a front surface of the substrate110. The second electrode180may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or a combination thereof, each having a low work function. When the second electrode180is a transmissive electrode, the second electrode180is beneficially thin enough to transmit light. When the second electrode180is a reflective electrode, the second electrode180is beneficially thick enough to reflect light. Thus, the OLED display according to the first embodiment of the invention is manufactured using a total of twelve masks.

The OLED display according to the first embodiment of the invention connects the shield layer114to the source electrode145of the driving transistor DR and applies a source voltage to the shield layer114. When the source voltage is applied to the shield layer114, a difference in horizontal energy field (E-field) between the source region124and the channel121of the semiconductor layer120can be reduced. Thus, hot carriers, in which electrons enter into an interface of the semiconductor layer120or the gate insulating layer GI, can be reduced or prevented, and thus, reduction in electron mobility and/or on-current of the driving transistor DR can be reduced or prevented. Further, when the driving transistor DR is turned off, its off-current can also be reduced.

The OLED display according to the first embodiment of the invention forms four contact holes in a connection structure of the source electrode, the shield layer, and the first electrode. A second embodiment of the invention describes a method of manufacturing an OLED display having reduced number of contact holes for achieving a high resolution.

Second Embodiment

FIG. 7is a plan view illustrating a part of an OLED display according to a second embodiment of the invention.FIG. 8is a cross-sectional view taken along line II-II′ ofFIG. 7. Structures and components identical or equivalent to those described in the first embodiment are designated with the same reference numerals, and a further description may be briefly made or may be entirely omitted in the second embodiment for brevity.

Referring toFIG. 7, a driving transistor DR and a first electrode160are connected to each other on a substrate110. The driving transistor DR includes a semiconductor layer120on a shield layer114, a first gate electrode130corresponding to the semiconductor layer120, a second gate electrode135separated from the first gate electrode130at a location corresponding to the first gate electrode130, and a drain electrode140and a source electrode145respectively connected to both sides of the semiconductor layer120.

A connection electrode132is connected to the shield layer114and the semiconductor layer120through a first contact hole CHE The source electrode145of the driving transistor DR is connected to the connection electrode132through a third contact hole CH3and thus is electrically connected to the semiconductor layer120. The drain electrode140of the driving transistor DR is connected to the semiconductor layer120through a second contact hole CH2. Further, the source electrode145is connected to the connection electrode132and is electrically connected to the shield layer114. The source electrode145of the driving transistor DR is connected to the first electrode160through a fourth contact hole CH4. The first electrode160is exposed by an opening OP of a bank layer (not shown).

More specifically, referring toFIG. 8, in the OLED display100according to the second embodiment of the invention, a first buffer layer112is positioned on the substrate110, and the shield layer114is positioned on the first buffer layer112. The shield layer114serves to prevent reduction in a panel driving current which may be generated by using a substrate formed of polyimide. A second buffer layer116is positioned on the shield layer114, and the semiconductor layer120is positioned on the second buffer layer116. The semiconductor layer120includes a drain region123and a source region124, each including p-type or n-type impurities and a channel121between the drain region123and the source region124. The semiconductor layer120further includes a lightly doped region122between the drain region123and the source region124adjacent to the channel121.

A gate insulating layer GI is positioned on the semiconductor layer120. The first gate electrode130is positioned on the gate insulating layer GI in a predetermined region of the semiconductor layer120, namely, at a location corresponding to the channel121when impurities are injected. The first gate electrode130serves as a gate electrode of the driving transistor DR. A first interlayer dielectric layer ILD1is positioned on the first gate electrode130to insulate the first gate electrode130. The second gate electrode135and the connection electrode132are positioned on the first interlayer dielectric layer ILD1. The second gate electrode135is a capacitor electrode forming a capacitor together with the first gate electrode130and does not operate as a gate electrode of the driving transistor DR. The connection electrode132is connected to the shield layer114through the first contact hole CH1passing through the first interlayer dielectric layer ILD1, the gate insulating layer GI, the semiconductor layer120, and the second buffer layer116. Further, the connection electrode132is connected to the semiconductor layer120through the first contact hole CH1. The first contact hole CH1has a structure passing through the source region124of the semiconductor layer120. Hence, when the first contact hole CH1is filled with the connection electrode132, the connection electrode132contacts a side of the semiconductor layer120and can be electrically connected to the semiconductor layer120. Thus, the connection electrode132can be electrically connected to the semiconductor layer120and the shield layer114through the first contact hole CH1at once.

A second interlayer dielectric layer ILD2is positioned on the second gate electrode135and the connection electrode132to insulate the second gate electrode135. The second and third contact holes CH2and CH3are positioned in a portion of each of the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulating layer GI to expose a portion of the semiconductor layer120. More specifically, the second contact hole CH2exposes the drain region123of the semiconductor layer120, and the third contact hole CH3exposes the connection electrode132.

The drain electrode140and the source electrode145are positioned on the second interlayer dielectric layer ILD2. The drain electrode140is connected to the semiconductor layer120through the second contact hole CH2exposing the drain region123of the semiconductor layer120, and the source electrode145is connected to the semiconductor layer120through the third contact hole CH3exposing the connection electrode132. Thus, the driving transistor DR including the semiconductor layer120, the first gate electrode130, the drain electrode140, and the source electrode145is formed.

A passivation layer PAS is positioned on the substrate110including the driving transistor DR. A planarization layer PLN is positioned on the passivation layer PAS to planarize the parts underlying the planarization layer PLN. The fourth contact hole CH4is positioned in a portion of each of the passivation layer PAS and the planarization layer PLN to expose the source electrode145. The first electrode160is positioned on the planarization layer PLN. The first electrode160serves as a pixel electrode and is connected to the source electrode145of the driving transistor DR through the fourth contact hole CH4. A bank layer BNK is positioned on the substrate110including the first electrode160to define the pixel. The bank layer BNK includes the opening OP exposing the first electrode160. A light emitting layer170contacting the first electrode160is positioned in the opening OP of the bank layer BNK, and a second electrode180is positioned on the light emitting layer170.

The OLED display according to the second embodiment of the invention includes the first contact hole CH1that passes through the source region124of the semiconductor layer120and exposes the shield layer114, thereby connecting the connection electrode132to the semiconductor layer120and the shield layer114through the first contact hole CH1at once. Thus, the OLED display according to the second embodiment of the invention can reduce a total of two contact holes respectively connected to the semiconductor layer120and the shield layer114to one.

A method for manufacturing the OLED display according to the second embodiment of the invention will now described. Duplicative description will be omitted for brevity.

FIGS. 9A to 9Lare cross-sectional views sequentially illustrating a method for manufacturing the OLED display according to the second embodiment of the invention.FIG. 10is a cross-sectional view illustrating a first contact hole of an OLED display according to an embodiment of the invention.FIG. 11illustrates an image of a first contact hole shown inFIG. 10taken using a scanning electron microscope (SEM).

Referring toFIG. 9A, a first buffer layer112is formed on a substrate110. An opaque material is stacked on the first buffer layer112and is patterned using a first mask to form a shield layer114.

Next, referring toFIG. 9B, a second buffer layer116is formed on the substrate110, on which the shield layer114is formed. A silicon semiconductor or an oxide semiconductor is stacked on the second buffer layer116and is patterned using a second mask to form a semiconductor layer120.

Next, referring toFIG. 9C, a gate insulating layer GI is formed on the substrate110including the semiconductor layer120. A metal material is stacked on the gate insulating layer GI and is patterned using a third mask to form a first gate electrode130. Subsequently, n-type impurities are lightly doped on a front surface of the substrate110to dope the semiconductor layer120. In this instance, a remaining portion of the semiconductor layer120except the semiconductor layer120underlying the first gate electrode130is doped using the first gate electrode130on the semiconductor layer120as a mask.

Next, referring toFIG. 9D, n-type impurities are heavily doped on the front surface of the substrate110to dope the semiconductor layer120. In this instance, a channel121, a lightly doped region122, a drain region123, and a source region124are formed at the semiconductor layer120by masking and doping a predetermined region of the semiconductor layer120using a fourth mask.

Next, referring toFIG. 9E, a first interlayer dielectric layer ILD1is formed on the substrate110, on which the first gate electrode130is formed. The first interlayer dielectric layer ILD1, the second buffer layer116, and the gate insulating layer GI are etched using a fifth mask to form a first contact hole CH1exposing the shield layer114. The first contact hole CH1is formed to pass through the source region124of the semiconductor layer120and expose the shield layer114. Thus, the semiconductor layer120is exposed to an inner circumference surface of the first contact hole CH1.

Next, referring toFIG. 9F, a metal material is stacked on the substrate110, in which the first contact hole CH1is formed, and is patterned using a sixth mask to form a second gate electrode135and a connection electrode132. The second gate electrode135is formed to overlap the first gate electrode130and may form a capacitance together with the first gate electrode130. The connection electrode132is filled in the first contact hole CH1and is simultaneously connected to the shield layer114and the source region124of the semiconductor layer120. Thus, the connection electrode132can be simultaneously connected to the shield layer114and the semiconductor layer120through the first contact hole CH1. Hence, the number of contact holes for connecting the connection electrode132to both the shield layer114and the semiconductor layer120can be reduced from two to one.

Next, referring toFIG. 9G, a second interlayer dielectric layer ILD2is formed on the substrate110, on which the second gate electrode135and the connection electrode132are formed. A photoresist is applied to the second interlayer dielectric layer ILD2, and the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulating layer GI are etched using a seventh mask. A second contact hole CH2exposing the drain region123of the semiconductor layer120is formed by etching the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulating layer GI. Further, the second interlayer dielectric layer ILD2is etched to form a third contact hole CH3exposing the connection electrode132.

Next, referring toFIG. 9H, a metal material is stacked on the substrate110, on which the second interlayer dielectric layer ILD2is formed, and is patterned using an eighth mask to form a drain electrode140and a source electrode145. The drain electrode140is connected to the drain region123of the semiconductor layer120through the second contact hole CH2, and the source electrode145is connected to the connection electrode132through the third contact hole CH3. Further, the source electrode145is electrically connected to the semiconductor layer120through the connection electrode132connected to the source region124of the semiconductor layer120. Thus, a driving transistor DR including the semiconductor layer120, the first gate electrode130, the drain electrode140, and the source electrode145is formed.

Next, referring toFIG. 9I, a passivation layer PAS is formed on the substrate110including the driving transistor DR. A fourth contact hole CH4exposing the source electrode145is formed by etching the passivation layer PAS using a ninth mask.

Next, referring toFIG. 9J, a planarization layer PLN is formed on the substrate110, in which the fourth contact hole CH4is formed. The fourth contact hole CH4of the passivation layer PAS extends by etching the planarization layer PLN using a tenth mask.

Next, referring toFIG. 9K, a transparent conductive layer is stacked on the planarization layer PLN and is patterned using an eleventh mask to form a first electrode160. The first electrode160is filled in the fourth contact hole CH4and may be connected to the source electrode145of the driving transistor DR.

Next, referring toFIG. 9L, a bank layer BNK and a spacer SP are formed on the substrate110including the first electrode160. The bank layer BNK is a pixel definition layer that exposes a portion of the first electrode160and defines a pixel, and the spacer SP serves to reduce or prevent a mask from contacting the substrate when a light emitting layer is formed in a subsequent process. The bank layer BNK and the spacer SP may be formed of an organic material, such as polyimide, benzocyclobutene-based resin, and acrylate. An opening OP exposing the first electrode160is formed in the bank layer BNK using a halftone mask, a twelfth mask, and the spacer SP is patterned. Subsequently, an organic light emitting layer170is formed on the first electrode160exposed by the opening OP of the bank layer BNK. A second electrode180is formed on the substrate110, on which the organic light emitting layer170is formed. Thus, the OLED display according to the second embodiment of the invention is manufactured using a total of twelve masks.

Referring toFIG. 10, a first contact hole CH1passes through a first interlayer dielectric layer ILD1, a gate insulating layer GI, a semiconductor layer120, and a second buffer layer116and exposes a shield layer114. The side of the semiconductor layer120is exposed to an inner circumference surface of the first contact hole CH1. A connection electrode132is formed in the first contact hole CH1and is connected to the shield layer114while being filled in the first contact hole CH1. In this instance, because the first contact hole CH1is filled with the connection electrode132, the connection electrode132contacts a side of the semiconductor layer120exposed to the inner circumference surface of the first contact hole CH1. Thus, the connection electrode132is connected to both the semiconductor layer120and the shield layer114.

As shown inFIG. 11, the connection electrode132is formed along the first contact hole CH1and contacts both the semiconductor layer120exposed to the inner circumference surface of the first contact hole CH1and the shield layer114.

The OLED display according to the second embodiment of the invention includes the first contact hole CH1that passes through the source region124of the semiconductor layer120and exposes the shield layer114, thereby connecting the connection electrode132to the semiconductor layer120and the shield layer114through the first contact hole CH1at once. Thus, the OLED display according to the second embodiment of the invention can reduce a total of two contact holes respectively connected to the semiconductor layer120and the shield layer114to one. As a result, the second embodiment of the invention can reduce the number of contact holes formed inside the pixel, and can reduce the pixel size by reducing the number of contact holes and thus achieve a high resolution.