Selective recessing to form a fully aligned via

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

BACKGROUND

The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer (i.e., M layers) in a selective recess region.

In contemporary semiconductor device fabrication processes, a large number of semiconductor devices and conductive interconnect layers are fabricated in and on a single wafer. The conductive interconnect layers serve as a network of pathways that transport signals throughout an integrated circuit (IC), thereby connecting circuit components of the IC into a functioning whole and to the outside world. Interconnect layers are themselves interconnected by a network of holes (or vias) formed through the wafer. As IC feature sizes continue to decrease, the aspect ratio (i.e., the ratio of height/depth to width) of features such as vias generally increases. Fabricating intricate structures of conductive interconnect layers and vias within an increasingly smaller wafer footprint is one of the most process-intensive and cost-sensitive portions of semiconductor IC fabrication.

SUMMARY

According to an embodiment of the present invention, a method of fabricating a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region is provided. The method can include forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

According to another embodiment, a structure having a via fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer is provided. The structure can include a plurality of metal lines formed in a first dielectric layer; first portions of the plurality of metal lines recessed in a recess region such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; and a non-recess region including second portions of the plurality of metal lines that are outside the recess region.

According to another embodiment, a method of fabricating a semiconductor device having a via fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region is provided. The method can include forming a plurality of metal lines in a first dielectric layer; recessing in a recess region a first portion of a first metal line such that a top surface of the first portion of the first metal line is below a top surface of the first dielectric layer, the first metal line adjacent to a first side of a second metal line; and recessing in a recess region a first portion of a third metal line such that a top surface of the first portion of the third metal line is below a top surface of the first dielectric layer, the third metal line adjacent to a second side of the second metal line, wherein the first side and the second side are opposite sides of the second metal line; wherein a non-recess region includes second portions of the first metal line and the second metal line that are outside the recess region.

DETAILED DESCRIPTION

By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a via according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

Fundamental to the above-described fabrication processes is semiconductor lithography, i.e., the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.

Turning now to a more detailed description of technologies relevant to the present invention, the fabrication of very large scale integrated (VLSI) or ultra large scale integrated (VLSI) circuits requires an interconnect structure including metallic wiring that connects individual devices in a semiconductor chip to one another. Typically, the wiring interconnect network consists of two types of features that serve as electrical conductors, namely line features that traverse a distance across the chip, along with via features that connect lines in different levels. Typically, the conducting metal lines and vias are comprised of aluminum or copper and are electrically insulated by interlayer dielectrics (ILD). In the interconnect structure, laminations of via interlayer films are referred to herein as “V” layers, and interconnect interlayer films are referred to herein as “M” layers.

To improve performance, the semiconductor industry has repeatedly shrunk the transistor gate length and the chip size. As a consequence the interconnect structure that forms the metallic circuitry has also shrunk. As IC feature sizes continue to decrease, the aspect ratio, (i.e., the ratio of height/depth to width) of features such as vias generally increases. Fabricating intricate structures of conductive interconnect layers and vias within an increasingly smaller wafer footprint is one of the most process-intensive and cost-sensitive portions of semiconductor IC fabrication.

To improve the manufacturability of lithography fabrication operations, advanced masks that incorporate phase-shifting and optical proximity correction have been employed. In addition, as the size scale of these interconnects decrease, overlay error between features in the interconnect structure can lead to reliability issues. Overlay errors result from misalignment during the lithography process as the mask invariably becomes misaligned with the underlying structure. Although overlay errors can be mitigated by reworking the lithography operations, some level of overlay error is unavoidable.

Two failure modes for interconnects that can result from the overlay errors of lithographic patterns are electro-migration (EM) and time dependent dielectric breakdown (TDDB). EM failure results when a void forms in the conducting metal feature through metal diffusion leading to a short (or very high resistance) in the circuitry. The mechanism of EM is highly dependent upon the current density and the cross section of the metal features. If the wiring is constructed such that the intersection between a via and a line is too small, smaller voids formed by EM can lead to failure, which shortens the EM lifetime.

TDDB is a failure mode whereby the insulating materials (or layers) no longer serve as adequate electrical insulators resulting in unintended conductance between two adjacent metal features. This phenomenon is highly dependent upon the electrical field between the metal features because regions with higher electrical fields are more susceptible to TDDB failure. Consequently, it is a design goal to control the spacing between conducting metal features to maintain electrical fields to tolerable levels.

To combat via misalignment and the device failures associated therewith, it would be desirable if one could form a fully aligned via, which is a vertical metal line interconnect that is fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer. Some solutions to achieve a fully aligned via require either a global recess or a selective dielectric, i.e., a build-up approach, or a combination of both methods. These approaches are associated with a plurality of processing and lithography problems, including, for example, a negative impact on typical back end of line (BEOL) structures. Recess approaches to achieve a fully aligned via structure can create undesirably high incoming aspect ratios (ARs) having a narrow pitch, which can result in a non-ideal metal fill or ultra low-k dielectric (ULK) line flop over. Creating these high aspect ratios during reactive ion etching (RIE) presents its own challenges, such as hard mask selectivity. The required hard mask thickness increases as the AR increases. For ARs greater than about 3.0, the required hard mask thickness becomes relatively large and the selective removal of the hard mask becomes increasingly difficult. Recess solutions can also have critical dimension dependence that negatively affects wide lines. Further, cap/ULK selectivity during the required dielectric etches is also challenging, due to the need to aggressively scale cap thickness due to RC time constant concerns. Moreover, while build-up approaches can achieve a fully aligned via, these approaches do so at the hard mask and are therefore subject to the overlay tolerance of lithography employed.

One or more embodiments of the present invention provide methods of fabricating a semiconductor device having a via fully aligned to both a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region. Because the via alignment in the first direction is not done at the hard mask, the described method is free of any overlay dependency from upstream patterning associated therewith. The described method employs a selective recess process that mitigates via size variation through containment by selective materials. Methods for fabricating a fully aligned via in a selective recess region and the resulting structures therefrom in accordance with embodiments of the present invention are described in detail below by referring to the accompanying drawings inFIGS. 1-23.

FIG. 1illustrates a top-down view of a structure100having a plurality of metal lines formed in a first dielectric layer104during an intermediate operation of a method of fabricating a semiconductor device that will have a fully aligned via1000(shown inFIG. 10) formed in a selective recess region106according to one or more embodiments. The selective recess region106overlaps a portion (e.g.,101A,101B,101C) of metal lines102A,102B, and102C of the plurality of metal lines. The remaining metal lines of the plurality of metal lines lie outside the selective recess region106. A via landing site108delineates a region within the selective recess region106where the via1000will be deposited during a damascene metallization operation, which will be described in greater detail later in this detailed description. The metal lines102A,102B, and102C are parallel to each other in a first direction110. For ease of illustration and description, only some of the plurality of metal lines are depicted (e.g., metal lines102A,102B,102C, and two additional lines on either side thereof). However, it is understood that three or more metal lines can be utilized. Each of the metal lines102A,102B, or102C includes a first portion101A,101B, or101C that is within the selective recess region106, as well as a second portion103A,103B, or103C of the metals lines102A,102B, or102C that is outside the selective recess region106. The areas of the structure100that are outside the selective recess region106are, collectively, a non-recess region.

FIG. 2illustrates a cross-sectional view of the selective recess region106(shown inFIG. 1) of the structure100along the line A-A ofFIG. 1during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments. The metal lines102A,102B, and102C are shown deposited in the first dielectric layer104formed on a substrate200.FIG. 2illustrates the portions101A,101B, and101C of the three metal lines102A,102B, and102C that are within the selective recess region106.

A variety of methods can be used to form the intermediate structure100illustrated inFIGS. 1 and 2. The metal lines102A,102B, and102C can be fabricated using any technique, such as, for example, a single or dual damascene technique. In one or more embodiments, the metal lines102A,102B, and102C are deposited in a dielectric layer by patterning the dielectric layer with open trenches where the conductor should be. The trenches in the dielectric are formed using, for example, a reactive ion etching (RIE) technique. RIE is a type of dry etching which uses chemically reactive plasma to remove a material, such as a masked pattern of semiconductor material, by exposing the material to a bombardment of ions that dislodge portions of the material from the exposed surface. The plasma is generated under low pressure (vacuum) by an electromagnetic field. Once the underlying oxide layer is patterned with open trenches a thick coating of copper that significantly overfills the trenches is deposited on the oxide layer, and chemical-mechanical planarization (CMP) is used to remove the portion of the copper (known as overburden) that extends above the top of the oxide layer. The remaining copper within the trenches of the oxide layer is not removed and becomes the patterned metal lines102A,102B, and102C. In one or more embodiments, the metal lines102A,102B, and102C can be any conductive material such as, for example, copper (Cu), aluminum (Al), or tungsten (W).

In one or more embodiments, the metal lines102A,102B, and102C can be copper (Cu) and can include a barrier metal liner (not shown). The barrier metal liner prevents the copper from diffusing into, or doping, the surrounding materials, which can degrade their properties. Silicon, for example, forms deep-level traps when doped with copper. An ideal barrier metal liner must limit copper diffusivity sufficiently to chemically isolate the copper conductor from the surrounding materials and should have a high electrical conductivity, for example, tantalum nitride and tantalum (TaN/Ta), titanium, titanium nitride, cobalt, ruthenium, and manganese. It should be noted that the barrier metal liner is not required if the interlayer dielectrics insulating the metal lines102A,102B, and102C are not susceptible to copper diffusion.

The first dielectric layer104is formed over substrate200and can include any dielectric material such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. The first dielectric layer104can be formed using, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition, atomic layer deposition, flowable CVD, spin-on dielectrics, or physical vapor deposition. The first dielectric layer104can have a thickness ranging from about 25 nm to about 200 nm. The substrate200can be of any suitable substrate material such as, for example, monocrystalline Si, SiGe, SiC, or semiconductor-on-insulator (SOI).

FIG. 3is a cross-sectional view after forming a sacrificial nitride layer300on the first dielectric layer104and forming a low temperature oxide layer302on the sacrificial nitride layer300. The sacrificial nitride layer300can be any suitable material such as silicon nitride. The sacrificial nitride layer300is removable during a wet etching process. For example, silicon nitride can be removed using a buffered hydrofluoric acid (BHF) etch. The low temperature oxide layer302can be formed using a variety of known methods such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The sacrificial nitride layer300and low temperature oxide layer302serve as a hard mask over the first dielectric layer104and the metal lines102A,102B, and102C.

FIG. 4is a cross-sectional view after depositing a tri-layer mask pattern400on the low temperature oxide layer302. The tri-layer mask pattern400includes a photoresist layer402selectively patterned with an opening404having a width W such that the photoresist layer402is on top of the second portions103A,103B, and103C of the metals lines102A,102B, and102C (i.e., those portions of the metal lines that are beyond or outside the selective recess region106as depicted inFIG. 1) and the remaining metal lines of the plurality of metal lines that lie outside the selective recess region106, but not on top of the first portions101A,101B, and101C of the metals lines102A,102B, and102C (i.e., the portions of the metal lines that are under the opening404and inside the selective recess region106). The photoresist layer402allows for the recessing selectivity of the first portions101A,101B, and101C of the metal lines102A,102B, and102C.

The tri-layer mask pattern includes an anti-reflective coating layer406and an organic underlayer408, the anti-reflective coating layer406located in between the photoresist layer402and the organic underlayer408. The organic underlayer408is located directly on top of the low temperature oxide layer302. The tri-layer mask pattern can be made of any suitable materials and can be formed using any suitable methodology. In one embodiment, a silicon-based anti-reflective spin-on hard mask (Si-SOH) is deposited using a spin-on coating process. The Si-SOH is a tri-layer hard mask including a photoresist formed on an organic anti-reflective coating, such as a silicon-containing anti-reflective coating (SiARC), which is formed on an organic planarization underlayer (OPL). In another embodiment, the tri-layer mask can be formed using chemical vapor deposition (CVD) process. In still another embodiment, a tri-layer mask is not used. Instead, a bilayer resist (BLR) process (not illustrated) is used to pattern the opening404.

FIG. 5is a cross-sectional view after opening the tri-layer mask pattern400and removing the sacrificial nitride layer300and the low temperature oxide layer302on top of the portions101A,101B, and101C of the three metal lines102A,102B, and102C to expose surfaces500A,500B, and500C of the portions101A,101B, and101C of the metal lines102A,102B, and102C. In one embodiment, strong oxygen plasma is used to strip the lithographic stacks including the sacrificial nitride layer300and the low temperature oxide layer302.

FIG. 6is a cross-sectional view after forming recessed openings604A,604B, and604C by recessing portions101A,101B, and101C of the three metal lines102A,102B, and102C within the selective recess region106below a top surface602of the first dielectric layer104. The recessed openings604A,604B and604C can be formed using any etching technique, such as, for example, reactive ion etching (RIE) and/or wet etching. In one embodiment, the recessing can be performed in a manner where the bulk of the metal lines can be removed in a separate operation from a metal barrier liner.

FIG. 7is an expanded cross-sectional view along the line A-A ofFIG. 1which includes metal lines700A and700B which are located outside of the selective recess region106, as depicted inFIG. 1, after stripping the remaining low temperature oxide layer302and sacrificial nitride layer300hard mask over the plurality of metal lines to completely expose the top surface602of the first dielectric layer104and the top surface700of the metal lines which were not recessed.

FIG. 8is a cross-sectional view after depositing a cap800on the first dielectric layer104and in the recessed openings604A,604B, and604C. The cap can be semi-conformally formed using any suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. In some embodiments the cap is a silicon nitride, silicon carbonitride (SiNCH), or metal oxide.

In one embodiment, conventional plasma enhanced chemical vapor deposition (PECVD) in combination with cyclic deposition—plasma treatment is used for forming the semi-conformal cap. Low radio frequency (RF) plasma power is used to deposit ultra-thin (˜2 nm) SiN film using silane and ammonia as precursors. Post deposition plasma treatment is performed to densify the film. Plasma nitridation is performed to improve the density of the SiN layers. This process can be repeated until the desired cap thickness is achieved.

Back End of Line (BEOL) capacitance is primarily governed by two components: the interlayer dielectric (ILD) and the dielectric barrier films. Lowering the dielectric constant of the barrier film can be preferred for capacitance reduction over the uses of lower k dielectrics, due to mechanical considerations, integration challenges and reliability requirements. Thinning the cap layer can be desirable because the caps often have higher dielectric constants than the neighboring dielectric, especially when using ULK dielectric. Thin caps are less selective than thick caps, however, and a tradeoff between selectivity and capacitance must be made. The first generation of dielectric cap that was integrated successfully with copper metallization was SiN (k˜7). In some applications SiNCH (k˜5.3) can be preferable to SiN due to its lower dielectric constant.

FIG. 9is a cross-sectional view after forming a second dielectric layer900on the cap800. In some embodiments, the first dielectric layer104and the second dielectric layer900are the same dielectric material. The second dielectric layer900can be formed using a variety of suitable methods, such as flowable chemical vapor disposition (CVD) or spin-on-dielectric processes.

FIG. 10is a cross-sectional view of the structure100having a metal line interconnect (via)1000fully aligned to both a first direction110(shown inFIG. 1) and a second direction1001in the selective recess region106. Metal lines102A,102B,102C are deposited in a first dielectric layer104. The metal lines are parallel to each other in the first direction110and define a first interconnect level1002. The portions101A,101B, and101C of the three metal lines102A,102B, and102C within the selective recess region106are recessed below a top surface602of the first dielectric layer104.

A trench1006, which defines a second interconnect level1004, and the via1000can be formed using a typical BEOL single or dual damascene metallization operation (Vx/Mx+1process). Any suitable self-aligned vertical interconnect access (SAV) scheme for forming a self-aligned via (SAV) damascene structure can be used to form a via self-aligned in the direction perpendicular to the second direction1001(i.e., the direction along the trench1006). In some embodiments, the first interconnect level1002is orthogonal to the second interconnect level1004, such that the direction perpendicular to the second direction1001is the first direction110. In one or more embodiments, a pattern trench first scheme is used wherein at least one trench1006is formed along the second direction1001on the second dielectric layer900prior to the via1000metallization operation, such that the trench1006allows the via1000to self-align perpendicularly to the second direction1001.

The cap800on the first dielectric layer104ensures that the via1000will self-align perpendicularly to the first direction110(i.e., to align in the second direction1001). During the via1000metallization operation, a via RIE removes a portion of the cap800to expose the portion101B of metal line102B. In some embodiments, the via RIE partially erodes sidewalls1008A and1008B of the cap800. Self-containment, however, leading to a reduced via1000size, is maintained even if the sidewalls1008A and1008B are partially eroded. For example, if the via1000contacts the cap800while being deposited into the via landing site108the via1000will not pass through the cap800but will instead conform to the shape of the cap800. As such, the cap800serves as a barrier between the via1000and the neighboring metal lines that forces the via to self-align in the second direction1001, preventing a short from forming during the metallization operation. In this manner, the incoming via aspect ratio is reduced at the expense of reducing the metal height in and around the via landing site108, resulting in an improved metal fill and a reduction in the risk of a ULK line flop over.

FIG. 11illustrates a top-down view of another structure1100having a plurality of metal lines formed in a first dielectric layer1104during an intermediate operation of a method of fabricating a semiconductor device that will have a fully aligned via1500(shown inFIG. 15) formed in a via landing site1108according to one or more embodiments. Selective recess regions1106A and1106B overlap a portion (e.g.,1101A and1101B) of metal lines1102A and1102C of the plurality of metal lines. The remaining metal lines of the plurality of metal lines lie outside the selective recess regions1106A and1106B. Via landing site1108delineates a region between the selective recess regions1106A and1106B where the via1500will be deposited during a damascene metallization operation, which will be described in greater detail later in this detailed description. The metal lines1102A,1102B, and1102C are parallel to each other in a first direction1110. For ease of illustration and description, only some of the plurality of metal lines are depicted (e.g., metal lines1102A,1102B,1102C, and two additional lines on either side thereof). However, it is understood that three or more metal lines can be utilized. Each of the metal lines1102A and1102C includes a first portion1101A and1101B that is within the selective recess regions1106A and1106B, respectfully, as well as a second portion1103A and1103B of the metals lines1102A and1102C that is outside the selective recess regions1106A and1106B.

FIG. 12illustrates a cross-sectional view of the structure1100along the line A-A ofFIG. 11during an intermediate operation of a method of fabricating a semiconductor device having a fully aligned via. The first dielectric layer1104can be formed on a substrate1202. This view illustrates the portions1101A and1101B of the metal lines1102A and1102C that are within the selective recess regions1106A and1106B.

The structure1100includes a substrate1202below the first dielectric layer1104and a sacrificial nitride layer1204, a low temperature oxide layer1206, and a tri-layer mask1216including a photoresist layer1212, an anti-reflected coating layer1210and an organic underlayer1208formed on the first dielectric layer1104, in a like configuration and formed in a like manner as in the structure100depicted inFIG. 4. In this embodiment, however, the photoresist layer1212is selectively patterned with two openings1214A and1214B having widths W1and W2, respectfully, such that the photoresist is not on top of the portions1101A and1101B of the metal lines1102A and1102C (i.e., within the selective recess regions1106A and1106B as depicted inFIG. 11).

FIG. 13is a cross-sectional view of the structure1100after opening the tri-layer mask pattern1216(as depicted inFIG. 12) and removing the sacrificial nitride layer1204and the low temperature oxide layer1206on top of the portions1101A and1101B of the metal lines1102A and1102C (i.e., within the selective recess regions1106A and1106B as depicted inFIG. 11) in a like manner as in the structure100depicted inFIG. 5. In one embodiment, strong oxygen plasma is used to strip the lithographic stacks including the sacrificial nitride layer300and the low temperature oxide layer302. The portions1101A and1101B of the metal lines1102A and1102C are adjacent to, and on opposite sides of, a metal line1304which is not recessed. Recessed openings1300and1302are formed by recessing portions1101A and1101B of the metal lines1102A and1102C (as depicted inFIG. 11) within the selective recess regions1106A and1106B below a top surface1304of the first dielectric layer1104. The recessed openings1300and1302can be formed using any etching technique, such as, for example, reactive ion etching (RIE) and/or wet etching. In one embodiment, the recessing can be performed in a manner where the bulk of the metal lines can be removed in a separate operation from a metal barrier liner.

FIG. 14is an expanded cross-sectional view along the line A-A ofFIG. 11which includes metal lines1401A,1401B and1401C which are located outside of the selective recess regions1106A and1106B, as is depicted inFIG. 11, after stripping the remaining low temperature oxide layer1206and sacrificial nitride layer1204hard mask in a like manner as in the structure100depicted inFIG. 7. A cap1400is formed on the first dielectric layer1104and in the first recess1300and in the second recess1302, in a like manner as in the structure100depicted inFIG. 8. The cap can be conformally formed using any suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. In some embodiments the cap is a silicon nitride, silicon carbonitride (SiNCH), or metal nitride.

A second dielectric layer1402is formed on the cap1400, in a like manner as is depicted inFIG. 9. In some embodiments, the first dielectric layer1104and the second dielectric layer1402are the same dielectric material. The second dielectric layer1402can be formed using any suitable method, such as flowable chemical vapor disposition (CVD) or spin-on-dielectric processes.

FIG. 15is a cross-sectional view of the structure1100having a metal line interconnect (via)1500fully aligned to both a first direction1110(shown inFIG. 11) and a second direction1501in the selective recess regions1106A and1106B. Metal lines1102A,1102B and1102C are deposited in a first dielectric layer1104. The metal lines are parallel to each other in the first direction1110and define a first interconnect level1502. The portions1101A and1101B of the metal lines1102A and1102B within the selective recess regions1106A and1106B, respectfully, are recessed below the top surface1304of the first dielectric layer1104.

A trench1508, which defines a second interconnect level1504, and the via1500can be formed using a typical BEOL single or dual damascene metallization operation (Vx/Mx+1process). Any suitable self-aligned vertical interconnect access (SAV) scheme for forming a self-aligned via (SAV) damascene structure can be used to form a via self-aligned in the direction perpendicular to the second direction1501(i.e., the direction along the trench1508). In some embodiments, the first interconnect level1502is orthogonal to the second interconnect level1504, such that the direction perpendicular to the second direction1501is the first direction1110. In one or more embodiments, a pattern trench first scheme is used wherein at least one trench1508is formed along the second direction1501on the second dielectric layer1402prior to the via1500metallization operation, such that the trench1508allows the via1500to self-align perpendicularly to the second direction1501.

The cap1400on the first dielectric layer1104guides the via1500to self-align perpendicularly to the first direction1110(i.e., the second direction1501). For example, if the via1500contacts the cap1400while being deposited into the via landing site1108(shown inFIG. 11) the via1500will conform to the shape of the cap1400and will not pass through. As such, the cap1400serves as a barrier between the via1500and the neighboring metal lines which forces the via to self-align in the second direction1501, preventing a short from forming during the metallization process.

In this embodiment, only the neighboring metal lines1101A and1101B, adjacent to the via landing site1108, are recessed. As a result, a full via approach aspect ratio is maintained at the via landing site1108without a corresponding spacing reduction between the first interconnect level and the second interconnect level. A full via approach aspect ratio relaxes the cap/ULK selectivity requirement to achieve a desired capacitance because the via is landing on a taller site, which results in a higher capacitance. This method requires a more precise lithography than that required by the process employed to form the structure100as depicted inFIG. 10and as described herein. In some embodiments this method (i.e., wherein only the neighboring metal lines are recessed) is reserved for portions of the overall lithography having a critical capacitance requirement.

FIG. 16illustrates a top-down view of another structure1600having metal lines1602A,1602B, and1602C parallel to each other in a first direction1610, in a first dielectric layer1604during an intermediate operation of a method of fabricating a semiconductor device having a fully aligned via1900(shown inFIG. 19) according to one or more embodiments. A via landing site1606, between selective recess regions1608A and1608B, delineates a region wherein the via1900will be deposited during a damascene metallization operation. Selective recess regions1608A and1608B overlap a portion (e.g.,1601A and1601B) of metal lines1602A and1602C of the plurality of metal lines. The remaining metal lines of the plurality of metal lines lie outside the selective recess regions1608A and1608B. Via landing site1606delineates a region between the selective recess regions1608A and1608B where the via1900will be deposited during a damascene metallization operation, which will be described in greater detail later in this detailed description. The metal lines1602A,1602B, and1602C are parallel to each other in a first direction1610. For ease of illustration and description, only some of the plurality of metal lines are depicted (e.g., metal lines1602A,1602B,1602C, and two additional lines on either side thereof). However, it is understood that three or more metal lines can be utilized. Each of the metal lines1602A and1602C includes a first portion1601A and1601B that is within the selective recess regions1608A and1608B, respectfully, as well as a second portion1603A and1603B that is outside the selective recess regions1106A and1106B.

FIG. 17is a cross-sectional view along the line A-A ofFIG. 16. The structure1600includes recessed portions1601A and1601B of metal lines1602A and1602C (shown inFIG. 16) recessed below a top surface1702of the first dielectric layer1604. The region above each of the recessed lines1601A and1601B defines a first recess1704and a second recess1706, respectively. The metal lines1602A and1602C are adjacent to, and on opposite sides of, a metal line1602B which is not recessed. The recessed portions1601A and1601B of metal lines1602A and1602C and the associated first recess1704and second recess1706can be formed using any etching technique, such as, for example, reactive ion etching (RIE) and/or wet etching.

The first dielectric layer1604is formed on a substrate1710. A cap1712is formed on the first dielectric layer1604and in the first recess1704and in the second recess1706, in a like manner as in the structure100depicted inFIG. 8. The cap can be conformally formed using any suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. In some embodiments the cap is a silicon nitride, silicon carbonitride (SiNCH), or metal nitride.

FIG. 18is a cross-sectional view of the structure1600after depositing an etch-resistant dielectric1800into the first recess1704and the second recess1706until the recesses are completely filled. The etch-resistant dielectric1800forms a barrier between the two recessed portions1601A and1601B of metal lines1602A and1602C and the via1900(shown inFIG. 19) deposited in a later metallization process. The etch-resistant dielectric1800can be any dielectric with a high etch-resistance such as, but not limited to, a nitride or silicon nitride. The etch-resistant dielectric1800can also be a high-k dielectric having a dielectric constant greater than 4.0, 7.0, or 10.0. High-k dielectric materials include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material can further include dopants such as, for example, lanthanum and aluminum.

The etch-resistant dielectric1800can be formed by any suitable deposition process, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes.

FIG. 19is a cross-sectional view of the structure1600having a metal line interconnect (via)1900fully aligned to both a first direction1610and a second direction1910in the selective recess regions1608A and1608B. The structure1600is substantially similar to the structure1100depicted inFIG. 15and is formed in a like manner, except that the structure1600includes the etch-resistant dielectric1800which completely fills both the first recess1704and the second recess1706. A second dielectric layer1902is formed on the cap1712, in a like manner as is depicted inFIG. 9. In some embodiments, the second dielectric layer1902has a lower etch resistance than the etch-resistant dielectric1800. In still other embodiments the second dielectric layer1902has a lower dielectric constant than the first dielectric layer1604. Moreover, as these embodiments advantageously fill both the first recess1704and the second recess1706with the etch-resistant dielectric1800, the likelihood of a non-ideal dielectric fill causing a void in either recess is reduced.

A trench1904, which defines a second interconnect level1906, and the via1900can be formed using a typical BEOL single or dual damascene metallization operation (Vx/Mx+1process). Any suitable self-aligned vertical interconnect access (SAV) scheme for forming a self-aligned via (SAV) damascene structure can be used to form a via self-aligned in the direction perpendicular to the second direction1910(i.e., the direction along the trench1904). In some embodiments, a first interconnect level1912is orthogonal to the second interconnect level1906, such that the direction perpendicular to the second direction1910is the first direction1610(shown inFIG. 16). In one or more embodiments, a pattern trench first scheme is used wherein at least one trench1904is formed along the second direction1910on the second dielectric layer1902prior to the via1900metallization operation, such that the trench1904allows the via1900to self-align perpendicularly to the second direction1910.

The cap1712on the first dielectric layer1604and the etch-resistant dielectric1800guide the via1900to self-align perpendicularly to the first direction1610. The via1900cannot pass through either the cap1712or the etch-resistant dielectric1800while being deposited into the via landing site1606(shown inFIG. 16). As such, the cap1712and the etch-resistant dielectric1800serve as a barrier between the via1900and the neighboring metal lines which forces the via to self-align in the second direction1910, preventing a short from forming during the metallization process.

In some embodiments, the combination of the cap1712and the etch-resistant dielectric1800allows for a via upsize or for a via which at least partially overlays the etch-resistant dielectric1800without causing a short during the metallization process. Vias tend to naturally shift from 1 to 10 nm, with a shift of 5 nm fairly common during the metallization process. The via overlay1908, whether due to a via upsize or to a natural shift in the via position, can be prevented from shorting the first interconnect level1912by the etch-resistant dielectric1800.

FIG. 20illustrates yet another embodiment of the present invention. The structure2000of this embodiment is formed in a like manner as the structure1600as depicted inFIG. 17, except that in this embodiment a porous silicon carbonitride ((p)SiNCH)2018is formed on the cap2016. Porous SiNCH advantageously serves as its own copper diffusion layer, obviating the need for any barrier metal liner, which saves space during the metallization operation.

The structure2000includes two recessed metal lines2002A and2002B recessed below a top surface2004of a first dielectric layer2006. The region above each of the recessed lines2002A and2002B defines a first recess2008and a second recess2010, respectively. The metal lines2002A and2002B are adjacent to, and on opposite sides of, a metal line2012, which is not recessed. The first dielectric layer2006is formed on a substrate2014. A cap2016is conformally formed on the first dielectric layer2006and in the first recess2008and in the second recess2010, in a like manner as in the structure100depicted inFIG. 8. The cap can be conformally formed using any suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. In some embodiments the cap is a silicon nitride, silicon carbonitride (SiNCH), or metal nitride.

In some embodiments the cap2016prevents a via (not depicted) deposited during the following metallization operation from passing through a void2020within either the first recess2008or the second recess2010. PECVD low-k films with poor gap filling capabilities, such as, for example, porous SiNCH, are often avoided in gap-filling applications. As this embodiment advantageously confines the porous SiNCH to recessed regions where the via will not land, porous SiNCH can be used in place of some other dielectric having good gap-filling properties, but which requires a barrier metal liner. In some embodiments, the porous SiNCH can be replaced with other low-k films having poor gap filling capabilities.

FIG. 21illustrates yet another embodiment of the present invention. The structure2100of this embodiment is substantially similar to, and formed in a like manner as, the structure1600as depicted inFIG. 16, except that in this embodiment a line end2102exists which separates a first metal line2104and a second metal line2106along a first direction2112. Line end adjacent shapes can be complicated, requiring asymmetric lines or space reduced process windows. In this embodiment a plurality of line selective recess windows2108A,2108B, and2108C define areas for selectively recessing metal lines to control a via (not depicted) deposited in a via landing site2110during a metallization operation from causing a short in accordance with any previous embodiment taught by this invention.

FIG. 22illustrates a selective copper-liner wet recess (TaN/Co/Cu) in accordance with one or more embodiments of the present invention. The structure2200demonstrates a wet recess process having a good selectivity to ULK.

FIG. 23illustrates a selective copper-liner wet recess elemental map (TaN/Co/Cu) of a portion ofFIG. 22in accordance with one or more embodiments of the present invention. The structure2300demonstrates a wet recess process having a good selectivity to ULK.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.