Interconnect structures, design structure and method of manufacture

An interconnect structure is provided that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing. The metal interconnect is formed in a dielectric material. A metal cap is selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

FIELD OF THE INVENTION

The present invention relates to integrated circuits (ICs), a design structure and a method of manufacturing the IC and, more particularly, to a cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC.

BACKGROUND

Electromigration is the transport of material caused by the gradual movement of ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect of electromigration is an important consideration to take into account in applications where high direct current densities are used, such as in microelectronics and related structures. In fact, electromigration is known to decrease the reliability of integrated circuits (ICs) and hence lead to a malfunction of the circuit. In the worst case, for example, electromigration leads to the eventual loss of one or more connections and intermittent failure of the entire circuit.

The effect of electromigration becomes an increasing concern as the size of the IC decreases. That is, as the structure size in ICs decreases, the practical significance of this effect increases. Thus, with increasing miniaturization the probability of failure due to electromigration increases in VLSI and ULSI circuits because both the power density and the current density increase.

Back-end-of-line (BEOL) interconnects, consisting of metal wires and inter-level vias, carry high direct current (DC) in advanced integrated circuit (IC) chip technology. In particular, as IC chip technology advances, the current density required in these metal wires/vias increases with the ever-decreasing dimensions in IC chip technology. Also, self-heating by high current devices raises the temperature of nearby interconnects under circuit operation and makes use of high current carrying BEOL interconnects extremely challenging. For example, a device that uses high current and self-heats (e.g., a resistor, a bipolar transistor, etc.) may heat up an interconnect wire that couples to the device. The high current leads to electro-migration (EM) degradation of the interconnect (via and/or line), causing shorts or opens.

As a result, the current-carrying capability (or the Idclimit specified in the design manuals) is significantly reduced to avoid electro-migration degradation in interconnects. As an example, a direct current limit in a copper interconnect may be reduced by a factor of more than three resulting from a temperature rise of about 15° C. from, for example, 85° C. to 100° C., and by almost a factor of 20 at a 125° C. interconnect temperature. As a result, high direct current at elevated temperatures is almost impossible with conventional interconnect structures.

There are various methods aimed at addressing this reliability issue in metal wires/vias. Known methods, though, result in EM induced voids occurring in any section of the segment, which will cause the wire to eventually open as the void grows in size. Other methods use liners to enclose vias. However, such structures and methods do not provide any means to protect EM damage in metal wires, nor do such structures address the EM damage at the via/wire interface.

SUMMARY

In a first aspect of the invention, a structure comprises a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap comprising RuX, where X is at least one of Boron and Phosphorous.

In another aspect of the invention, a method of fabricating an interconnect structure comprises forming an interconnect in an insulation material. The method further comprises selectively depositing a metal cap material on the interconnect. The metal cap material comprises RuX, where X is at least one of Boron and Phosphorous.

In yet a still further aspect of the invention, a design structure is embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect, the metal cap comprising RuX, where X is at least one of Boron and Phosphorous.

DETAILED DESCRIPTION

The present invention relates to integrated circuits (ICs), a design structure and a method of manufacturing the IC and, more particularly, to a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. In implementation, the present invention provides a metal cap design to overcome EM induced damage, which includes a metal cap layer that is selective to the metal interconnect. The metal cap layer serves as an EM blocking layer.

FIG. 1shows a beginning structure in accordance with the invention. The beginning structure includes a sacrificial dielectric layer12deposited on a dielectric layer10. The sacrificial dielectric layer12may be, for example, SiO2. The sacrificial dielectric layer12may be deposited in any conventional manner such as, for example, a spin on process or chemical vapor deposition (CVD) process. The low k dielectric layer10may be SiCOH, as one non-limiting example. The low k dielectric layer10may be either porous or dense, and may be applied by a spin on process or CVD process.

InFIG. 2, trenches14are processed in the low k dielectric layer10and the sacrificial dielectric layer12. The trenches14may be formed using any conventional lithography and etching process. For example, a mask (not shown) may be applied over the sacrificial dielectric layer12and exposed to light to form openings. A reactive ion etching (RIE) may then be performed to form the trenches14.

FIG. 3shows post metallization and chemical mechanical polishing (CMP) processes. More specifically, inFIG. 3a liner16is deposited in the trenches. The liner16may be a barrier layer of TiN, TaN, WN, RuTa(N) or RuN, for example. The deposition process may be a conventional deposition process such as, for example, CVD, physical vapor deposition (PVD) or atomic layer deposition (ALD). In embodiments, the liner16can have a thickness of about 20 Å to 200 Å. An interconnect18such as, for example, Cu or Cu(Al) is deposited over the liner18. The structure is then planarized using, for example, CMP processes.

InFIG. 4, a metal cap20is selectively deposited on the interconnect18. More specifically, the metal cap20is selective to metal, e.g., the interconnect18, such that the metal cap20is not deposited on the low k dielectric layer10. In embodiments, the metal cap20is Ru(P), Ru(B) or Ru(P,B). It should be understood by those of skill in the art that the use of Ru alone is not a good oxygen diffusion barrier. As such, the copper surface of the interconnect18may oxidize which has a negative impact on EM resistance. However, it has been found that using Ru(P), Ru(B) or Ru(P,B) is a superior oxygen diffusion barrier which does not allow the interconnect surface to oxidize. Accordingly, the metal cap of Ru(P), Ru(B) or Ru(P,B) will prevent EM issues.

FIGS. 5a-5dshow different variants of Ru(P), Ru(B) or Ru(P,B) as contemplated by the invention. For example, as shown inFIG. 5a, in aspects of the invention, the metal cap comprises a bottom layer of Ru and an upper layer of Ru(P), Ru(B) or Ru(P,B). In embodiments, the Ru layer and the layer of Ru(P), Ru(B) or Ru(P,B) are each about 20 Å or less and can range from about 10 Å to 20 Å. In further embodiments, the percent concentration of (P), (B) or (P)(B) ranges from about 2% to 30%.

FIG. 5bshows a further aspect of the invention, where the metal cap is a layer of Ru(P), Ru(B) or Ru(P,B), with the (P), (B) or (P)(B) component gradually increasing in percentage concentration as it is deposited on the interconnect18. For example, in implementation, the (P), (B) or (P)(B) can be introduced during the deposition process by increasing the gas flow of (P), (B) or (P)(B) such that the bottom portion of the metal cap is, for example, 0% of (P), (B) or (P)(B) and the upper portion is, for example, about 30% of (P), (B) or (P)(B), with a gradual increase therebetween. The concentration of (P), (B) or (P)(B) can be increased or decreased by adjusting the gas flow.

FIG. 5cshows a further aspect of the invention, where the metal cap is a single layer of Ru(P), Ru(B) or Ru(P,B), with the (P), (B) or (P)(B) component having a substantially constant percentage concentration throughout the entire metal cap. For example, in implementation, the percentage concentration of (P), (B) or (P)(B) can range from about 2% to 30%, in relation to the entire structure.

FIG. 5dshows a further aspect of the invention, where the metal cap is a layered structure. For example, in one aspect, the layers may alternate between (i) Ru and Ru(P), (ii) Ru and Ru(B), (iii) Ru and Ru(P,B). In embodiments, the percentage concentration of (P), (B) or (P)(B) can range from about 0% to 30%, in relation to the entire layered structure. The thickness of the metal cap can be about 30 Å to 50 Å, with each layer ranging from about less than 10 Å and preferably about 1 Å to 2 Å.

FIG. 6shows a final structure and respective processing steps in accordance with an aspect of the invention. As shown inFIG. 6, a dielectric cap22is deposited on the structure ofFIG. 4. The dielectric cap22can be, for example, Si3N4, SiC, SiC(N, H) etc. The dielectric cap22can be deposited via a CVD deposition technique.

Design Structure

FIG. 7shows a block diagram of an exemplary design flow900used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow900includes processes and mechanisms for processing design structures to generate logically or otherwise functionally equivalent representations of the embodiments of the invention shown inFIGS. 4 and 6. The design structures processed and/or generated by design flow900may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems.

Design process910may include hardware and software modules for processing a variety of input data structure types including netlist980. Such data structure types may reside, for example, within library elements930and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications940, characterization data950, verification data960, design rules970, and test data files985which may include input test patterns, output test results, and other testing information. Design process910may further include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

Design process910employs and incorporates well-known logic and physical design tools such as HDL compilers and simulation model build tools to process design structure920together with some or all of the depicted supporting data structures to generate a second design structure990. Similar to design structure920, design structure990preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown inFIGS. 4 and 6. In one embodiment, design structure990may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown inFIGS. 4 and 6.

Design structure990may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure990may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data processed by semiconductor manufacturing tools to fabricate embodiments of the invention as shown inFIGS. 4 and 6. Design structure990may then proceed to a stage995where, for example, design structure990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.