Method for forming trenches on a surface of a semiconductor substrate

A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to a method for forming trenches on a surface of a semiconductor substrate. Furthermore, the invention also relates to a method for forming floating-gate electrodes on a semiconductor substrate and to a corresponding integrated circuit.

2. Related Art

The fabrication of a semiconductor device often comprises the formation of a relatively high number of oriented trenches within a relatively small area. For example, to fabricate an integrated semiconductor circuit with a relative high density of transistors, it is necessary to etch a plurality of parallel insulation trenches into the surface of the semiconductor substrate with a relative small distance between two adjacent trenches.

SUMMARY

A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches.

Additionally, a method for forming floating-gate electrodes on a semiconductor substrate is described. The method may include: depositing a layer of dielectric material on a surface of the semiconductor substrate; depositing a layer of material for floating-gate electrodes on the layer of dielectric material; etching a first plurality of trenches; filling the first plurality of trenches at least partially with an insulating material to form insulation trenches; etching a second plurality of trenches to shape a first side wall of a plurality of floating-gate electrodes, the first side wall running parallel to the longitudinal direction of the insulation trenches; covering the first side wall at least partially with a first layer; and etching a third plurality of trenches to shape a second side wall of the plurality of floating-gate electrodes, so that each floating-gate electrode of the plurality of floating-gate electrodes comprises one first side wall and one second side wall opposing the first side wall.

Furthermore, an integrated circuit is described. The integrated circuit may comprise: a layer of dielectric material covering a surface of a semiconductor substrate at least partially; a plurality of insulation trenches formed within the surface of the semiconductor substrate; and a plurality of floating-gate electrodes, each floating-gate electrode of the plurality of floating-gate electrodes having a first side wall running parallel to the longitudinal direction of the insulation trenches and a second side wall opposing the first side wall, wherein the first side wall is covered at least partially by a first layer and the second side wall is covered at least partially by a second layer, such that an interface is formed between the first layer and the second layer.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration one or more specific implementations in which the invention may be practiced. It is to be understood that other implementations may be utilized and structural changes may be made without departing form the scope of this invention.

FIG. 1is a flowchart showing an example of an implementation of a method for forming trenches on a surface of a semiconductor substrate.

As an example, the method may include a number of steps, e.g. etching a first plurality of trenches into a surface of a semiconductor substrate in step100and filling the first plurality of trenches with at least one material in step102. For instance, a reactive ion etch (“RIE”) process may be performed to etch the first plurality of trenches. The first plurality of trenches may be filled with an insulating material to provide insulation trenches. However, the technology is not restricted to an insulating material filled into the first plurality of trenches.

The method may also include etching a second plurality of trenches into every second trench of the first plurality of trenches in step104. After the etching of the second plurality of trenches, two adjacent trenches of the second plurality of trenches may embrace one trench of the first plurality of trenches in which no trench of the second plurality is etched. The trenches of the second plurality of trenches may be less deep than the trenches of the first plurality of trenches.

As an example, an isotropic etch process may be performed to etch the second plurality of trenches. The second plurality of trenches etched by performing the isotropic etch process may be wider than the trenches of the first plurality of trenches.

FIG. 2is a flowchart showing another approach of an implementation of a method for forming trenches on a surface of a semiconductor substrate.

The method may include the steps of etching a first plurality of trenches into a surface of a semiconductor substrate (step200) and filling the first plurality of trenches with at least one material (step202). In step204, a second plurality of trenches may be etched into every second trench of the first plurality of trenches. For instance, a RIE process may be performed to etch the second plurality of trenches. However, the present technology is not restricted to the RIE process for etching the second plurality of trenches. It is also possible to perform an isotropic etch process to etch the second plurality of trenches.

The second plurality of trenches may be filled with at least one material (step206). The material filled into the second plurality of trenches may differ from the material filled into the first plurality of trenches. For instance, a first layer of a first coupling-dielectric material may be formed to cover the side walls and the bottoms of the second plurality of trenches. Furthermore, the first layer of the first coupling-dielectric material may be covered at least partially by a first layer of material for control-gate electrodes.

Moreover, the method may also include etching a third plurality of trenches into every second trench of the first plurality of trenches in step208. After step208, two adjacent trenches of the third plurality of trenches may embrace one trench of the second plurality of trenches.

The trenches of the third plurality of trenches may be etched wider than the trenches of the second plurality of trenches. However, it is possible to form trenches for the third plurality of trenches that have the same breadth than the trenches of the second plurality of trenches.

For instance, an isotropic etch process may be performed to etch the third plurality of trenches. The trenches of the third plurality of trenches may be etched as deep as the trenches of the second plurality of trenches.

In a not shown step, the third plurality of trenches may be filled at least partially with a material. For instance, the third plurality of trenches may be filled with a second layer of a second coupling-dielectric material and a second layer of material for the control-gate electrodes. The second coupling dielectric material may differ from the first coupling-dielectric material. However, it is also possible to cover the side walls and the bottoms of the third plurality of trenches at least partially with the first coupling-dielectric material.

FIG. 3is a flowchart showing an example of an implementation of a method for forming floating-gate electrodes on a semiconductor substrate.

The method may include a step300of depositing a layer of dielectric material on a surface of the semiconductor substrate. On the layer of dielectric material, a layer of material for floating-gate electrodes may be deposited to provide the material for floating-gate electrodes later to be formed (step302). The layer of material for floating-gate electrodes may include polysilicon.

In step304, a first plurality of trenches may be etched. The first plurality of trenches may be filled at least partially with an insulating material to form insulation trenches.

A second plurality of trenches may be etched to shape a first side wall of a plurality of floating-gate electrodes (step306). The first side wall may be arranged parallel to the longitudinal direction of the insulation trenches. Each trench of the second plurality of trenches may be etched into every second trench of the first plurality of trenches.

In another process step308, the first side wall may be covered at least partially with a first layer. The first layer may include a first coupling-dielectric material. Furthermore, a first layer of material for the control-gate electrodes may be formed on the first layer to fill the second plurality of trenches. However, the present technology is not restricted to these materials.

A third plurality of trenches may be etched to shape a second side wall of the plurality of floating-gate electrodes (step310). The second side wall may be arranged in an opposite direction with regard to the first side wall. Each trench of the third plurality of trenches may be etched such that two adjacent trenches of the second plurality of trenches embrace one trench of the third plurality of trenches.

In a not shown process step, the second side wall may be covered at least partially with a second layer such that an interface is formed between the first layer and the second layer. For instance, the second layer may comprise a second coupling-dielectric material. The second coupling-dielectric material may differ from the first coupling-dielectric material. Furthermore, the second layer may be covered at least partially with a second layer of material for the control-gate electrodes. However, the present technology is not restricted to the given examples.

FIGS. 4A to 4Ishow cross-sectional views of a semiconductor device to describe another approach of an implementation of a method for forming floating-gate electrodes.

InFIG. 4A, a cross-sectional view of a semiconductor substrate400is shown. As an example, the material of the semiconductor substrate400may be silicon.

An insulation layer402is formed on a surface404of semiconductor substrate400. The insulation layer402may have a layer thickness of about 5-15 nm. As an example, the insulation layer402may be a silicon oxide layer formed by utilizing a thermal oxidation process. However, it is appreciated by those skilled in the art that there are various other insulating materials that may also be used to form the insulation layer402.

A floating-gate layer406is formed on the surface408of the insulation layer402. In this example, the floating-gate layer406may include polysilicon. The floating-gate layer406may have a higher layer thickness than the insulation layer402. As an example, the thickness of the floating-gate layer406may be about 20-120 nm.

A nitride layer410is formed to cover a surface412of floating-gate layer406at least partially. A mask414is placed on a surface416of nitride layer410. As an example, the mask414may be a carbon hard mask. A lithographic process may be performed to structure the mask414. The structured mask414may include a plurality of mask openings418that expose the nitride layer410according to a pattern of trenches that are to be formed in the semiconductor substrate400. The result is shown inFIG. 4A.

InFIG. 4B, a cross-sectional view of semiconductor substrate400is shown after the formation of a first plurality of trenches420. For instance, a reactive ion etch (“RIE”) process is performed to etch the first plurality of trenches420into semiconductor substrate400.

Each trench420may extend through nitride layer410, floating-gate layer406, insulation layer402and into semiconductor substrate400. For example, the depth of the trenches420may be 250 nm. The trenches420may have a first breadth b1.

The not exposed areas under mask414may be chosen large enough to ensure a sufficient stiffness of the interspaces between the trenches420. Thus, the interspaces between two adjacent trenches420may be structurally strong enough to resist bending or breaking.

After the etching of the first plurality of trenches420, the mask414may be removed. In this example, the trenches420become STI-trenches. Therefore, the trenches420are filled with an insulating material422. For instance, the insulating material422may be silicon oxide. However, instead of silicon oxide numerous other types of insulating materials may be filled into the trenches420. A chemical mechanical polishing (CMP) process may be performed to remove the insulating material422from the surface416of nitride layer410.

The insulating material422filled into the trenches420further increases the stiffness of the newly formed structures on the surface404of the semiconductor substrate400.

FIG. 4Cshows a cross-sectional view of semiconductor substrate400after the formation of a second plurality of trenches424. The trenches424are etched into every second trench of the first plurality of trenches. Two adjacent trenches of the second plurality of trenches424may embrace one trench428of the first plurality of trenches, which is still filled completely with the insulating material422.

The trenches424may be etched by an isotropic etch process. The trenches424may not be etched as deep as the trenches428. This reduces the surface of the remaining STI-fills426to a level above the surface408of the insulation layer402. However, due to the isotropic etch process, the breadth b2of the trenches424is larger than the breadth b1of the trenches428.

The walls of the trenches424define first side walls432of the floating-gate electrodes later to be formed. The first side walls432are arranged parallel to the longitudinal direction of the trenches filled with the insulating material422and426. The etching of the second plurality of trenches424is performed to shape the first side walls432.

A first coupling-dielectric material layer430is formed on the surface416of nitride layer410. The first coupling-dielectric material layer430also covers the walls and the bottoms of the trenches424. As an example, the first coupling-dielectric material layer430may be deposited by a low pressure chemical vapor deposition (“LPCVD”) process. The first coupling-dielectric material layer430may include silicon oxide. However, instead of silicon oxide, the coupling-dielectric material layer430may include another dielectric material.

The first coupling-dielectric material layer430is covered with a first layer of material for the control-gate electrodes436. The layer thickness of the first layer of material for the control-gate electrodes436is large enough to fill the remaining space of the trenches424. The result is shown inFIG. 4D.

FIG. 4Eshows a cross-sectional view of semiconductor substrate400after a CMP-process performed to the remove protruding parts of the first coupling-dielectric material layer430and the first layer of material for the control-gate electrodes436. The CMP-process is performed until the nitride layer410is exposed again.

Another (not shown) mask is deposited on the semiconductor substrate400. In a following lithographic process, those areas of the mask are exposed that cover the remaining trenches428still filled completely with the insulating material422.

Then, using the mask, a third plurality of trenches438is etched into the remaining trenches428. The trenches438may be etched by an isotropic etch process. This isotropic etch process may be performed until the surface of the remaining STI-fills440has the same height as the STI-fills426. The trenches438are located such that two adjacent trenches438are arranged on both sides of a trench424. The breadth of the trenches438may be equal to the value b2. Then, the mask and the nitride layer410are removed from the surface of the semiconductor substrate400. The result is shown inFIG. 4F.

The third plurality of trenches438is etched to shape a second side wall446of a plurality of floating-gate electrodes (“FG”)442formed of the former floating-gate layer406. The second side walls446of the floating-gate electrodes are defined by the walls of the trenches438. Each floating-gate electrode442has one first side wall432and one second side wall446opposing the first side wall432.

The floating-gate electrodes442have an upper breadth b3which may be about 10 nm. The lower breadth b4of the floating-gate electrodes442may be in the range between 30 nm to 100 nm. This inverse T-shape of the floating-gate electrodes442reduces the interaction between two floating-gate electrodes442arranged next to each other in a direction perpendicular to the cross-section of theFIGS. 4A to 4I. The interaction between a floating-gate electrode442and its associated (in a following process step to be formed) control-gate electrode is not limited by the inverse T-shape of the floating-gate electrodes442.

Due to the lower value of the upper breadth b3, the upper parts of the floating-gate electrodes442might start to bend or even break in a situation where both pluralities of trenches424and438are formed simultaneously. However, this risk may be avoided when the floating-gate electrodes442are produced by the method explained above. The floating-gate electrodes442produced by this method are formed in several process steps. First, the first side wall432of the floating gate electrodes442is shaped. The first side wall432is covered with the layers430and436before the second side wall446is shaped. Thus, the floating-gate electrodes442are in contact with at least one other layer in each process step. This contact of the floating-gate electrodes442with at least one other layer may provide sufficient stability to the floating-gate electrodes442.

A second coupling-dielectric material layer444(such as, for example, silicon oxide) is filled into the trenches438to cover the walls and the bottoms of the trenches438. The second coupling-dielectric material layer444is covered with a second layer of material for the control-gate electrodes450.

The result is shown inFIG. 4G. The second coupling-dielectric material layer444covering the second side walls446has an interface448with the first coupling-dielectric material layer430covering the first side walls432. Even though both layers430and444may include the same coupling-dielectric material, there is still the interface448provided between the two layers430and444.

InFIG. 4H, a cross-sectional view of the semiconductor substrate400after a CMP-process is shown. The CMP-process is performed to remove protruding parts of the second coupling-dielectric material layer444and the second layer of material for the control-gate electrodes450.

The size of the interface448between the first coupling-dielectric material layer430and the second coupling-dielectric material layer444may be reduced by the CMP-process. However, the interface448in the upper part of the floating-gate electrodes442is there after the CMP-process.

FIG. 4Ishows a cross-sectional view of the semiconductor substrate400having a first top layer452deposited on the semiconductor substrate400. The first top layer452may include polysilicon or another appropriate material.

The first top layer452is deposited to form together with the layers436and450control-gate electrodes CG. Therefore, the first top layer452is in contact with contact regions458of layer430and contact regions460of layer444. The contact regions458and460are arranged in the upper part of the layers430and444. The first top layer452also covers the interfaces448between the two layers430and444.

The contact regions458and460may have a different shape. For example, the contact regions458may have a curvature with a first average radius of curvature and the contact regions460may have a curvature with a second average radius of curvature. The first average radius of curvature may be smaller than the second average radius of curvature.

A second top layer454and a third top layer356are deposited on the first top layer452. As an example, the second top layer454and the third top layer356may comprise tungsten nitride and tungsten. In this case, the second top layer454is a barrier to prevent the tungsten of the third top layer356from diffusing into the first top layer452of polysilicon.

However, this technology is not limited to the materials tungsten nitride and tungsten for the top layers454and356to form a wordline WL connected to the plurality of control-gate electrodes CG.

FIGS. 5A to 5Gshow cross-sectional views of a semiconductor device to describe another approach of an implementation of a method for forming floating-gate electrodes.

InFIG. 5A, a cross-sectional view of a semiconductor substrate500is shown. In accordance with the process steps described above with regard toFIG. 4A, an insulation layer502, a floating-gate layer504and a nitride layer506are formed on the semiconductor substrate500. A first plurality of trenches508is etched into the semiconductor substrate500with the layers502to506. For instance, a RIE process is performed to etch the first plurality of trenches508with a first breadth b1.

Each trench508is filled with an insulating material510. Thus, STI-trenches are provided within the semiconductor substrate500. A CMP-process may be performed to remove the insulating material510protruding out of the trenches503.

A second plurality of trenches512is etched into every second trench of the first plurality of trenches508. Thus, two adjacent trenches of the second plurality of trenches512may embrace one trench508of the first plurality of trenches, which is still filled completely with the insulating material510.

The trenches512may have the same breadth b1as the trenches508. However, the surface of the remaining STI-fills514is reduced by the second plurality of trenches512. For instance, a RIE process may be performed to etch the second plurality of trenches512.

The trenches512are etched to shape first side walls516of the floating-gate electrodes later to be formed. The first side walls516are arranged parallel to the longitudinal direction of the trenches filled with the insulating material510and514.

The first side walls516are covered by a first coupling-dielectric material layer518and a first layer of material for the control-gate electrodes520. The layers518and520may be deposited by a LPCVD process. For instance, the first coupling-dielectric material layer518may include silicon oxide. However, the present technology is not restricted to this material. The result is shown inFIG. 5B.

FIG. 5Cshows a cross-sectional view of semiconductor substrate500after a CMP-process is performed to remove protruding parts of the layers518and520. The CMP-process is performed until the nitride layer506is exposed again.

FIG. 5Dshows a cross-sectional view of semiconductor substrate500after an etching of a third plurality of trenches522to shape a second side wall524of the floating-gate electrodes526. The third plurality of trenches522is etched into the remaining trenches of the first plurality of trenches. After the etching of the third plurality of trenches522, two trenches522may embrace one trench512of the second plurality of trenches512.

The third plurality of trenches522may be etched by an isotropic etch process. This isotropic etch process may be performed until the surface of the remaining STI-fills528has the same height as the STI-fills514. The breadth b2of the trenches522may be larger that the breadth b1of the trenches508and512.

During the etching of the third plurality of trenches522, floating-gate electrodes FG526are formed of the former floating-gate layer504. Each floating-gate electrode526has one first side wall516and one second side wall524. The first side wall516may have a different shape than the second side wall524. For instance, the first side wall may have a first curvature with a first radius of curvature and the second side wall may have a second curvature with a second radius of curvature, wherein the second radius of curvature has a different value than the first radius of curvature. In the example shown inFIG. 5D, the first side wall516is almost flat while the second side wall524has a curvature.

The floating-gate electrodes526may have a L-shape. Each floating-gate electrode526may have an upper breadth b3which is smaller than its lower breadth b4. The upper breadth b3may be about 10 nm. The lower breadth b4of the floating-gate electrodes526may be in the range between 30 nm to 100 nm.

The L-shape of the floating-gate electrodes526may reduce the interaction between two floating-gate electrodes526arranged next to each other in a direction perpendicular to the cross-section of theFIGS. 5A to 5G. The interaction between a floating-gate electrode526and its associated (in a following process step to be formed) control-gate electrode is not limited by the inverse L-shape of the floating-gate electrodes526.

The second side walls524are covered with a second coupling-dielectric material layer530and a second layer of material for the control-gate electrodes532. Thus, an interface534is formed between the first coupling-dielectric material layer518and the second coupling-dielectric material layer530. The result is shown inFIG. 5E.

The second coupling-dielectric material layer530may have a different layer thickness than the first coupling-dielectric material layer518. Furthermore, the layer thickness of the second layer of material for the control-gate electrodes532may be different from the layer thickness of the first layer of material for the control-gate electrodes520.

The layers530and532may also include different materials than the layers518and520. For instance, the second coupling-dielectric material layer530may include a high-k material.

Layers formed of a high-k material may be sensitive to electrical field intensity. However, the increased breadth b2of the third plurality of trenches522makes it possible to form a layer530of a high-k material within the trenches522, wherein the layer530has an increased layer thickness compared with the first coupling-dielectric material layer518.

The layer530of a high-k material may provide a good capacitive coupling between each floating-gate electrode526and its associated control-gate electrodes (later to be formed). The layers518and520may be formed to provide an electrical shielding between two adjacent floating-gate electrodes526.

InFIG. 5F, a cross-sectional view of the semiconductor substrate500after a CMP-process is shown. During the CMP-process, the protruding parts of the layers530and532are removed.

In accordance with the process steps described with regard toFIG. 4I, a first top layer536, a second top layer538and a third top layer540are deposited on the layers518,520,530and532.

The first top layer536also covers the interfaces534and the contact regions542and544of the layers520and532. As described above, the contact regions542and544may have a different shape. For instance, the contact regions542of layer520may almost be flat while the contact regions544of layer532may have a curvature.