Receiving circuit

Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2011-286245, filed on Dec. 27, 2011, the entire contents of which are incorporated herein by reference.

FIELD

The present invention relates to a receiving circuit.

BACKGROUND

Performances of components composing computers and other information processing equipment have made great advancement, as seen in memory, processor and switching LSI (large-scale integrated circuit). In view of improving system performances, it is necessary to improve not only performances of the individual components, but also signal transmission rate between these components or elements (increase in transmission capacity and reduction in transmission delay). For example, improvement in performances of computer (server) needs improvement in the signal transmission rate between a memory, such as SRAM (static random access memory) or DRAM (dynamic random access memory), and a processor, and signal transmission rate between servers. Besides the servers, with the progress in performances of information processing equipment including those for backbone system of communication, there has been a growing need of increasing data rate in signal transmission inside and outside the equipment.

In recent years, in addition to a demand on increase in the data rate, there has been a further demand of implementing such higher data rate at a low power consumption. In order to respond to the requirements of higher data rate and lower power consumption, not a few integrated circuits have encountered need for increasing the data rate of an input/output circuit (I/O) from several gigabits/second to several tens gigabits/second. For advanced equipment, it is also necessary to integrate a large number of I/O ports compatible to such large data rate into a single integrated circuit. High speed I/O needs a large number of analog circuits including equalizer, timing generator and so forth. From the viewpoints of readiness in design and integration of a large number of I/Os, it is preferable to replace these analog circuits with digital circuits.

There has been known a data decoding circuit which includes an analog-digital converter converting input analog signals expressing a data stream into digital signals in synchronization with a clock signal, to thereby generate a digital code stream obtained by sampling with intervals shorter than data intervals of the data stream; a phase detector calculating a position of cross point at which a line segment obtained by interpolating the digital data stream crosses the horizontal line expressing the level of predetermined code value, lying approximately at the center of a possible range of values of digital codes; a phase estimation unit determining an estimated position of the center point of the data stream based on the position of the cross point; and a data decision unit extracting a stream of decided data value from the digital data stream, based on the position of the cross point and the estimated position of the center point of the data stream (see Patent Document 1).

SUMMARY

According to the present invention, there is provided a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase of the one unit interval, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase. The data selection circuit selects the two input data based on the center phase calculated by the arithmetic unit. The correction circuit corrects the two input data based on a correction value corresponded to the past data level output by the data decision circuit.

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIG. 1is a drawing illustrating an exemplary configuration of a receiving circuit of a first embodiment. The receiving circuit is typically used for signal transmission between LSI chips, signal transmission between a plurality of circuit blocks in a package, and signal transmission between the packages, and is featured by high-speed transmission. The receiving circuit receives binary data through a transmission line from a transmitting circuit.

The receiving circuit has a clock data recovery (CDR) circuit, and decodes output data Do based on input data Di. An decision feedback equalizer (DFE)111has a correction circuit105, a phase detection circuit106, a data decision circuit107, and a correction value generating circuit108.

The equalizer101is a feed-forward equalizer (FFE), and removes distortion in waveform of input data, which is ascribable to the transmission line, by equalizing the binary input data Di corresponding to transmission characteristics of the transmission line. The sampler102samples data output by the equalizer101, in synchronization with a clock signal which is asynchronous to a clock signal of the transmitting circuit.

FIG. 2Ais a drawing illustrating a change in the binary input data Di. One unit interval (1 UI) means a duration of one bit data, and the one unit interval of the individual bit data is almost constant. Boundary phase Pb is a phase which appears at the boundary of the adjacent unit intervals, at which the level of input data Di may change. Center phase Pc means a phase at the center of one unit interval (1 UI), and has a phase difference of 0.5 unit intervals away from the boundary phase Pb. The input data Di is a NRZ (non-return-to-zero) binary data, at a transmission rate of 2.5 Gbits/sec, for example.

The sampler102illustrated inFIG. 1typically samples two sample data per one unit interval (double over sampling). The analog-digital converter103converts the analog data sampled by the sampler102into digital data. For example, the analog-digital converter103is a 4-bit, analog-digital converter, performing digital conversion at a sampling rate of 5 gigasamples per second.

The data selection circuit104receives center phase Pc from an adder110, and selects two input data located while placing in between the center phase Pc of one unit interval of digital data resulted from conversion by the analog-digital converter103. The correction circuit105is typically an adder, which receives a correction value from the correction value generating circuit108, and corrects the input data by adding the input data selected by the data selection circuit104and the correction value.

The phase detection circuit106detects a phase at which the level of input data changes as a boundary phase Pb in the one unit interval, based on the input data corrected by the correction circuit105. A loop filter109is a low-pass filter, smoothens the boundary phase Pb, and outputs the smoothened boundary phase. The adder110adds 0.5 unit intervals to the output signal of the loop filter109, and outputs the sum as the center phase Pc of the one unit interval. If the sum is larger than one unit interval, the adder110outputs a value obtained by subtracting 1 from the sum. The loop filter109may be provided alternatively on the downstream side of the adder110. It suffices that the arithmetic unit, configured by the loop filter109and the adder110, outputs the center phase Pc after smoothened by the loop filter109.

The data decision circuit107decides the level of either one of the two input data selected by the selection circuit104and corrected by the correction circuit105, based on the center phase Pc and the boundary phase Pb, and outputs the determined level as the output data Do. For example, if the level of data exceeds 0, the data is determined to have a level of “+1”, whereas if the level of data is smaller than 0, the data is determined to have a level of “−1”.

The data selection circuit104implements the selection based on the center phase Pc resulted from addition by the adder110. The correction value generating circuit108generates a correction value corresponded to the past data level output by the data decision circuit107. For example, the correction value generating circuit108has a correction value table, and outputs correction value “+d” if the past data is “−1”, whereas outputs correction value “−d” if the past data is “+1”. The past data may be one bit, or may be 2 bit or more. The correction circuit105adds the input data selected by the data selection circuit104and the correction value generated by the correction value generating circuit108, and outputs the sum to the phase detection circuit106.

The correction value generating circuit108generates the correction value corresponding to the past output data Do of the data decision circuit107. For example, the correction value is generated using the past output data Do which amounts one bit if the decision feedback equalizer111has a single-tap configuration, or using the past output data which amounts two bits if the decision feedback equalizer111has a two-tap configuration, and necessarily using 2mcorrection values for a m-tap configuration. The correction value may preliminarily be determined, or may be optimized by adaptive control.

FIG. 2Bis a drawing explaining a method of detecting the boundary phase Pb by the phase detection circuit106illustrated inFIG. 1. The input data Di typically has a binary level of “+1” or “−1”. The phase detection circuit106typically enters adjacent two input data a and b. The input data a has a phase of 0 unit intervals and has a level below 0. The input data b has a phase of 0.5 unit intervals and has a level above 0. The phase detection circuit106detects a phase at which change from the input data a to the input data b crosses the level 0, as the boundary phase Pb. More specifically, the phase detection circuit106calculates Pb=0.5×a/(a−b) based on linear interpolation, to thereby find the boundary phase Pb [UI].

FIG. 2Bshowed an exemplary case where the boundary phase Pb resides in the range of unit interval from 0 to 0.5. For the case where the boundary phase Pb is not found in the range of unit interval from 0 to 0.5, the boundary phase Pb in the range of unit interval from 0.5 to 1 is detected.

FIGS. 3A and 3Bare drawings explaining a method of determining data implemented by the data decision circuit107illustrated inFIG. 1. As seen inFIG. 2A, since the level of data may change at around the boundary phase Pb, it is not preferable to decode the data at around the boundary phase Pb. In contrast, the level of data is relatively stable at the center phase Pc, so that it is preferable for the data decision circuit107to decode the data based on the data at around the center phase Pc.

InFIG. 3A, the two input data located while placing the center phase Pc in between are the input data b and c, with the boundary phase Pb fallen between the input data b and c. In this case, if the center phase Pc is smaller than the boundary phase Pb, the data decision circuit107determines the input data b on the binary basis, and outputs data “+1” or “−1” as decoded data. In contrast, if the center phase Pc is larger than the boundary phase Pb, data decision circuit107determines the input data c on the binary basis, and outputs data “+1” or “−1” as the decoded data.

InFIG. 3B, the two input data located while placing the center phase Pc in between are the input data a and b, with the boundary phase Pb fallen between the input data b and c. In this case, since the input data a and b are determined to have the same level, so that the data decision circuit107determines either input data a or b on the binary basis, and outputs data “+1” or “−1” as the decoded data.

The data decision circuit107may alternatively implement a precise data decision as described below. If the center phase Pc is smaller than the boundary phase Pb as illustrated inFIG. 3B, the data decision circuit107determines the input data a on the binary basis, and outputs data “+1” or “−1” as the decoded data. In contrast, if the center phase Pc is larger than the boundary phase Pb, the data decision circuit107determines the input data b on the binary basis, and outputs data “+1” or “−1” as the decoded data.

FIG. 4is a drawing explaining a method of correction implemented by the correction circuit105illustrated inFIG. 1. The input data a, b and c are sampled from input data403. The correction circuit105adds the same correction value to the input data b and c located while placing in between the center phase Pc in the current one unit interval402, based on the data of the previous one unit interval401(past data), to thereby remove intersymbol interference, and outputs corrected data404. The correction values added to the input data b and c are same.

FIG. 5is another drawing explaining a method of correction implemented by the correction circuit105illustrated inFIG. 1. The correction circuit105adds correction value “−d” respectively to uncorrected input data b1and c1, and outputs the corrected input data b2and c2. For the case where the center phase Pc (boundary phase Pb) is determined by linear interpolation by the phase detection circuit106, under the double oversampling by the sampler102, the linear interpolation will be accurate when the impulse response is given as a square wave with a width of one unit interval. If the linear interpolation is accurate, addition of the same correction value “−d” to the input data b1and c1at both ends of the interval, is equivalent to addition of the correction value to the data at the center phase Pc.

FIG. 6is a drawing explaining another method of phase detection implemented by the phase detection circuit106illustrated inFIG. 1. The input data a has the phase of 0 unit intervals. The input data b has the phase of ½ (=0.5) unit intervals. The level of the input data a has a positive value, and the level of the input data b has a negative value, for example. The linear interpolation is now given between the input data a and the input data b.

Now a represents the level of the input data a, and b represents the level of the input data b. The level at level 0 [UI] is a, the level at 1/16 [UI] is (7a+b)/8, the level at 2/16 [UI] is (3a+b)/4, the level at 3/16 [UI] is (5a+3b)/8, the level at 4/16 [UI] is (a+b)/2, the level at 5/16 [UI] is (3a+5b)/8, the level at 6/16 [UI] is (a+3b)/4, the level at 7/16 [UI] is (a+7b)/8, and the level at 8/16 [UI] is b.

If a and (7a+b)/8 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “000” which indicates that the boundary phase Pb falls in the range from 0 to 1/16 [UI].

If (7a+b)/8 and (3a+b)/4 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “001” which indicates that the boundary phase Pb falls in the range from 1/16 to 2/16 [UI].

If (3a+b)/4 and (5a+3b)/8 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “010” which indicates that the boundary phase Pb falls in the range from 2/16 to 3/16 [UI].

If (5a+3b)/8 and (a+b)/2 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “011” which indicates that the boundary phase Pb falls in the range from 3/16 to 4/16 [UI].

If (a+b)/2 and (3a+5b)/8 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “100” which indicates that the boundary phase Pb falls in the range from 4/16 to 5/16 [UI].

If (3a+5b)/8 and (a+3b)/4 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “101” which indicates that the boundary phase Pb falls in the range from 5/16 to 6/16 [UI].

If (a+3b)/4 and (a+7b)/8 have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “110” which indicates that the boundary phase Pb falls in the range from 6/16 to 7/16 [UI].

If (a+7b)/8 and b have different signs, the phase detection circuit106outputs, as the boundary phase Pb, a phase code “111” which indicates that the boundary phase Pb falls in the range from 7/16 to 8/16 [UI].

Note that, for the case where the boundary phase Pb falls in the range from 0.5 to 1 [UI], the boundary phase Pb may be detected by linear interpolation over the range from 0.5 to 1 [UI], similarly as described in the above.

FIG. 7is a drawing illustrating an exemplary configuration for implementing the phase detection circuit106illustrated inFIG. 6. A multiplier701doubles a, and outputs 2a. An adder702adds a and b, and outputs a+b. A multiplier703doubles b, and outputs 2b. A multiplier704doubles 2a, and outputs 4a. An adder705adds 2a and a+b, and outputs 3a+b. A multiplier706doubles a+b, and outputs 2a+2b. An adder707adds a+b and 2b, and outputs a+3b. A multiplier708doubles 2b, and outputs 4b. An adder709adds 4a and 3a+b, and outputs 7a+b. An adder710adds 3a+b and 2a+2b, and outputs 5a+3b. An adder711adds 2a+2b and a+3b, and outputs 3a+5b. An adder712adds a+3b and 4b, and outputs a+7b. A detector713outputs the boundary phases Pb having codes of “000” to “111” according to the method illustrated inFIG. 6, based on the signs of a, 7a+b, 5a+3b, 3a+5b, a+7b and b. The multipliers701,703,704,706,708can perform the two-fold multiplication by bit shifting. The detector713can detects difference or equality of the signs by exclusive OR operation of sign bits.

FIG. 8is a drawing illustrating an exemplary configuration of a loop filter109illustrated inFIG. 1. The loop filter109is a quadratic low pass filter having two integrators. A subtractor801subtracts average boundary phase Pa from the boundary phase Pb, and outputs the difference. An adder802adds the output value of the subtractor801and an output value of a delayer803, and outputs the sum. The delayer803delays the output value of the adder802by one sample data, and outputs the result. A multiplier804multiplies the output value of the delayer803and a coefficient kf, and outputs the product. An adder805multiplies the output value of the multiplier804and an output value of a delayer806, and outputs the product. The delayer806delays the output value of the adder805by one sample data, and outputs the result. The multiplier807multiplies the output value of the delayer806and a coefficient kp, and outputs the average phase Pa to the subtractor801and the adder110(FIG. 1). Add-subtract operation of the boundary phase Pb is performed using mod 2m, while assuming the one [UI] with integers from 0 to 2m−1. In other words, the add-subtract operation gives a value of phase subtracted by one [UI], if the value exceeds one [UI].

In order to solve the problem of circuit scale and power consumption of the receiving circuit using the analog-digital converter103as illustrated inFIG. 1, it is effective to reduce the number of bits required for the analog-digital converter103by modifying the methods of equalizing and data decision. For example, a flash analog-digital converter used for high-speed, analog-digital converter can exponentially reduce the power consumption and occupied space, by reducing the necessary number of bits (halved if reduced by one bit).

One effective method of modifying the method of equalization is to locate the analog equalizer101on the upstream side of the analog-digital converter103, and locate the decision feedback equalizer111on the downstream side of the analog-digital converter103. The configuration having the analog equalizer101located on the upstream side of the analog-digital converter103is advantageous in that the number of bits required by the analog-digital converter103may be reduced, since quantization noise of analog-digital converter103will not be amplified by the equalizer101. By locating the decision feedback equalizer111on the downstream side of the analog equalizer101, the decision feedback equalizer111can decode the signal level without amplifying the noise component contained therein, so that the band required for the analog equalizer101may be narrowed, and thereby the number of bits required for the analog-digital converter103may further be reduced.

This embodiment is configured to make the correction circuit105add the correction value to the sample data selected by the data selection circuit104, without using a circuit explicitly determining a signal value at the center phase Pc, so that an effect of using the decision feedback equalizer, which determines a signal value at the center phase Pc, may be obtained only with a less amount of hardware. By incorporating the decision feedback equalizer111, performance of equalization may be improved, and thereby performance of the receiving circuit may be improved.

FIG. 9is a drawing illustrating results of simulation of the receiving circuit. The receiving circuit uses the sampler102to sample the input data according to an asynchronous clock signal. The abscissa represents jitter frequency, and the ordinate represents jitter amplitude. A characteristic curve903represents characteristic of the receiving circuit illustrated inFIG. 1. A characteristic curve902represents characteristics of a receiving circuit having no decision feedback equalizer111. A characteristic curve901represents characteristics of the receiving circuit using the decision feedback equalizer111for determining a signal value at the center phase Pc. It is understood that this embodiment represented by the characteristic curve903shows larger jitter resistance at high frequencies as compared with the receiving circuit represented by the characteristic curve902, and shows characteristics comparable to those of the receiving circuit represented by the characteristic curve901, according to which a signal value at the center phase Pc is determined using the decision feedback equalizer.

FIG. 10is a drawing illustrating other results of simulation of the receiving circuit. The abscissa represents jitter frequency, and the ordinate represents jitter amplitude. A characteristic curve1003represents characteristics of the receiving circuit illustrated inFIG. 1. A characteristic curve1002represents characteristics of an interpolation-type CDR circuit which performs correction using a correction value corresponded to the center phase Pc. A characteristic curve1001represents characteristics of a tracking-type CDR circuit which performs synchronization control of sampling clock frequency. It is understood that this embodiment represented by the characteristic curve1003may implement performances comparable to those represented by the characteristic curves1001and1002, only with a more simple circuit configuration.

According to this embodiment, by providing the decision feedback equalizer111, the equalization characteristics may be improved, and the number of bits required for the analog-digital converter103may be reduced. Also by virtue of needlessness of the circuit for determining a signal value at the center phase Pc, the hardware amount and power consumption of the receiving circuit may be reduced.

Second Embodiment

FIG. 11is a drawing illustrating an exemplary configuration of a receiving circuit of a second embodiment. Aspects different from those in the first embodiment will be explained below. Correction units105aand105bcorrespond to the correction circuit105illustrated inFIG. 1. The correction unit105ais an adder, which adds correction value “+d” to the input data selected by the data selection circuit104, and outputs the corrected input data. The correction unit105bis an adder, which adds correction value “−d” to the input data selected by the data selection circuit104, and outputs the corrected input data.

Phase detectors106ato106ccorrespond to the phase detection circuit106illustrated inFIG. 1. The phase detector106adetects a phase at which the level of the input data changes as the boundary phase Pb, based on the input data corrected by the correction unit105a. The phase detector106bdetects a phase at which the level of the input data changes as the boundary phase Pb, based on the input data corrected by the correction unit105b. A first phase detector106cdetects a phase at which the level of the input data changes as the boundary phase Pb, based on the input data converted by the analog-digital converter103, and outputs the boundary phase Pb to the loop filter109. The loop filter109smoothens the boundary phase Pb detected by the first phase detector106c, and outputs the smoothened boundary phase Pd. The adder110adds 0.5 [UI] to the boundary phase output by the loop filter109, and outputs the center phase Pc.

Data decision units107aand107bcorrespond to the data decision circuit107illustrated inFIG. 1. The data decision unit107adetermines the level of either one of the two input data corrected by the correction unit105a, based on the center phase Pc and the boundary phase Pb detected by the phase detector106a. Data decision unit107bdetermines the level of either one of the two input data corrected by the correction unit105b, based on the center phase Pc and the boundary phase Pb detected by the phase detector106b.

An equalizer selection circuit1101selects the level of either one of data output by the data decision units107aand107b, based on the past data level stored in a storage unit1102, and outputs data Do. The storage unit1102stores the past data composed of one bit or a plurality of bits output by the equalizer selection circuit1101. The past data composed of one bit may be stored in the storage unit1102, by providing two sets of correction units105a,105b, phase detectors106a,106band data decision units107a,107b, as illustrated inFIG. 11.

The past data composed of two or more bits may be stored in the storage unit1102, by providing three or more sets of correction units105a,105band so forth, phase detectors106a,106band so forth, and data decision units107a,107band so forth. In this case, the plurality of correction units105a,105band so forth correspond to the correction circuit105illustrated inFIG. 1, and correct the input data selected by the selection circuit104, based on a plurality of correction values. The plurality of phase detectors106a,106band so forth correspond to the phase detection circuit106illustrated inFIG. 1, and detect phases at which the levels of input data change as the boundary phases Pb, based on the input data corrected by the plurality of correction units105a,105band so forth. The plurality of data decision units107a,107band so forth correspond to the data decision circuit107illustrated inFIG. 1, determine the levels of either ones of the two input data respectively corrected by the plurality of correction units105a,105band so forth, based on the center phase Pc and the plurality of boundary phases Pb detected by the plurality of phase detectors106a,106band so forth, and output the levels. The equalizer selection circuit1101selects the level of either one of the levels output by the plurality of data decision units107a,107band so forth, corresponding to the past data level stored in the storage unit1102.

This embodiment is configured to preliminarily create data by adding the correction values corresponded to all possible cases, and to detect phase and to determine data for all data, rather than feeding back the correction value generated based on the past data and by adding it to the input data.FIG. 11exemplifies the equalizer of a single-tap configuration, so that 21=2 correction values (+d and −d) are generated and added to the input data. Upon completion of output of decision values corresponded to all corrected data, an output of the path, through which an appropriate correction value has been added corresponding to the past data, is selected as a correct decision value, and is output. In the full-rate design in which the decision is made at a frequency same as the data rate, the output is selected by the selection circuit which selects one of the two input data based on the past data.

FIG. 12Ais a drawing illustrating an exemplary configuration of a part of the receiving circuit of this embodiment. A demultiplexor1201is provided between the analog-digital converter103and the selection circuit104. The demultiplexor1201is an 1:16 demultiplexor, and converts a serial data output by the analog-digital converter103into 16-bit-wide parallel digital data, at a clock frequency of 312.5 MHz for example.

FIG. 12Bis a drawing illustrating an exemplary configuration of the equalizer selection circuit1101illustrated inFIG. 11. The equalizer selection circuit1101has a selector1202, a flipflop1203and a selector1204, and can process data of m-tap equalizer in an L-bit parallel manner. If the operating frequency of the data decision units107a,107bequals to 1/L of the data rate frequency, the data decision units107a,107band so forth output L parallel bit data. L selectors1202make selection from the decision values added with 2mdifferent correction values corresponding to m past data series. Since the past data series for controlling the selector1202employ the decision values which precede the currently focused bit, so that it is necessary to ensure “propagation of decision value” such that a decision value at a certain bit is always used for selection of the equalizer at the next bit.

Third Embodiment

FIG. 13is a drawing illustrating an exemplary configuration of a receiving circuit of a third embodiment. Aspects of this embodiment different from those in the second embodiment will be explained below. In this embodiment (FIG. 13), a phase selection circuit1301is provided in place of the first phase detector106cin the second embodiment (FIG. 11). The phase selection circuit1301selects either one of the boundary phases Pd detected by the phase detectors106a,106b, and outputs the selected one, based on the past data level stored in the storage unit1102. The loop filter109smoothens the boundary phase Pb output by the phase selection circuit1301, and outputs the smoothened boundary phase. The adder110adds 0.5 [UI] to the boundary phase output by the loop filter109, and outputs the sum as the center phase Pc.

The phase selection circuit1301selects the boundary phase based on the past data stored in the storage unit1102, similarly to the equalizer selection circuit1101. In this way, the boundary phase Pb detected based on appropriately corrected data may be output to the loop filter109, and this is advantageous enough to improve output accuracy of the loop filter109.

Fourth Embodiment

FIG. 14is a drawing illustrating an exemplary configuration of a receiving circuit of a fourth embodiment. Aspects of this embodiment different from those in the second embodiment will be explained below. This embodiment (FIG. 14) is understood as an exemplary case where the first phase detector106cwas omitted from the second embodiment (FIG. 11). The loop filter109smoothens the boundary phase Pb detected by the phase detector106a, and outputs the smoothened boundary phase. The adder110adds 0.5 [UI] to the boundary phase output by the loop filter109, and outputs the sum as the center phase Pc.

The loop filter109may alternatively be configured so as to receive the boundary phase Pb detected by the phase detector106b, not by the phase detector106a. It suffices that the loop filter109smoothens the boundary phase Pb detected by either one of the phase detectors106a,106b.

While the boundary phase Pb biased to a certain degree is input to the loop filter109in this embodiment, it has experimentally been proven that, by averaging the boundary phase Pb using the loop filter109, the average boundary phase may be obtained almost without bias. The reason why the average value is not biased is that change in the input data from −1 to +1, and change from +1 to −1 occurs with almost equal probability, so that the same past data cause phase shifting by an equal value and different signs for the individual cases. In short, averaging can yield the average phase without bias. This embodiment is advantageous over the second embodiment, in that the number of phase detectors to be employed may be reduced, and thereby the amount of hardware may be reduced.

Fifth Embodiment

FIG. 15is a drawing illustrating an exemplary configuration of a receiving circuit of a fifth embodiment. Aspects of this embodiment different from those in the second embodiment will be explained. This embodiment (FIG. 15) is understood as an exemplary case where an equalizer1501is provided in place of the equalizer101in the second embodiment (FIG. 11), and where an enable control circuit1503and a least mean square (LMS) adaptive control circuit1502are additionally provided. The enable control circuit1503outputs an enable signal to the LMS adaptive control circuit1502, based on the center phase Pc. The LMS adaptive control circuit1502calculates a tap coefficient and the correction value d of the equalizer1501, when the enable signal is activated, and outputs the tap coefficient to the equalizer1501.

FIG. 16is drawing explaining a method of detecting phase by the phase detectors106ato106cillustrated inFIG. 15. Assuming now that the level of input data a changes with a predetermined slope SL to the level of input data b, the phase detectors106ato106crespectively detects the boundary phase Pb at which the level of input data changes. If the absolute value |a| of a is not larger than the absolute value |b| of b, the boundary phase Pb is given as Pb=|a|/SL. In contrast, if the absolute value |a| of a is larger than the absolute value |b| of b, the boundary phase Pb is given as Pb=0.5 [UI]−|b|/SL. The equalizer1501illustrated inFIG. 15is controlled so as to allow the input data to change with the predetermined slope SL. The equalizer1501equalizes the input data Di so as to allow the level of input data to change with the predetermined slope SL. A method of controlling of the equalizer1501will be described later.

FIG. 17is a drawing illustrating changes in the input data controlled by the equalizer1501illustrated inFIG. 15. The input data is controlled so as to give a diamond-like waveform according to which the input data changes with the predetermined slope SL. The enable control circuit1503illustrated inFIG. 15inactivates the enable signal in a 0.2 [UI] area containing the boundary phase Pb at which the input data changes, whereas it activates the enable signal in the other area1701. Since the area1701shows no decay in the data change waveform, so that the LMS adaptive control circuit1502performs adaptive control only in the area1701.

FIG. 18is a drawing illustrating an exemplary configuration of the equalizer1501illustrated inFIG. 15. The multiplier1801multiplies the input data Di and the tap coefficient c0, and outputs the product. A subtractor1802subtracts an output value of a multiplier1804from the output value of the multiplier1801, and outputs data EQo to the sampler102illustrated inFIG. 15. A decision circuit1803decides a binary code of the data EQo, and outputs “+1” or “−1”. The multiplier1804multiplies the output value of the decision circuit1803and a tap coefficient c1, and outputs the product to the subtractor1802.

FIG. 19is a drawing illustrating an exemplary configuration of the LMS adaptive control circuit1502illustrated inFIG. 15. Enable signal CTL is an output signal of the enable control circuit1503illustrated inFIG. 15. Expected value DE is an output data of the decision circuit1803illustrated inFIG. 18, and has a value of “+1” or “−1”. Sign SI is a sign of input data Di.

A multiplier1902multiplies the expected value DE and the enable signal CTL, and outputs the product. A subtractor1903subtracts the data EQo from the output value of the multiplier1902, and outputs an error. A multiplier1904multiplies the error output by the subtractor1903and the input data Di, and outputs the product. A multiplier1909multiplies the error output by the subtractor1903and the sign SI, and output the product. A multiplier1905multiplies the output value of the multiplier1904and a coefficient μc0, and outputs the product. A multiplier1910multiplies the output value of the multiplier1909and a coefficient μc1, and outputs the product.

A logic circuit1901outputs 1 to multipliers1906and1911if the enable signal CTL is not 0, whereas outputs 0 to the multipliers1906and1911if the enable signal CTL is 0. The multiplier1906multiplies the output values of the multipliers1905and logic circuit1901, and outputs the product. The multiplier1911multiplies the output values of the multiplier1910and the output value of the logic circuit1901, and outputs the product. An adder1907adds the output value of the multiplier1906and an output value of a flipflop1908, and outputs the tap coefficient c0to the equalizer illustrated inFIG. 18. An adder1912adds the output value of the multiplier1911and an output value of a flipflop1913, and outputs the tap coefficient c1to the equalizer illustrated inFIG. 18. The equalizer illustrated inFIG. 18has the tap coefficients c0and c1set thereon. The flipflop1908stores the tap coefficient c0output by the adder1907. The flipflop1913stores the tap coefficient c1output by the adder1912.

This embodiment is different from the second embodiment in the configuration of the phase detectors106a,106b, and in that the LMS adaptive control circuit1502is additionally provided. The phase detectors106aand106bcalculate the boundary phase Pb based on the predetermined slope SL, as illustrated inFIG. 16. If the slope SL of the data waveform during change is constant, the sample value itself represents the phase, and thereby the phase detectors106aand106bmay be simplified to a considerable degree.

Note that this method requires constancy of the slope SL during the data change, and this is controlled by the LMS adaptive control circuit1502. The LMS adaptive control circuit1502uses an LMS algorism to adjust the tap coefficients c0and c1so as to minimize the difference between the data EQo and the desired expected value DE.

The enable control circuit1503determines whether the control by the LMS adaptive control circuit1502will be implemented or not. This is for the purpose of preventing the accuracy of adaptive control from degrading depending on the range of phase. For example, the adaptive control may be stabilized by implementing it not in the 0.2 [UI] area which contains the boundary phase Pb, but in the other area1701.

FIG. 20is a drawing illustrating results of simulation of the receiving circuit of the fifth embodiment. The abscissa represents jitter frequency, and the ordinate represents jitter amplitude. A characteristic curve2001represents characteristics of the receiving circuit illustrated inFIG. 15. A characteristic curve2002represents characteristics of a receiving circuit using a general phase detector and an LMS algorism. It is understood that this embodiment represented by the characteristic curve2001can achieve characteristics comparable to those of the configuration represented by the characteristic curve2002, even if the phase detectors106aand106bwere simplified.

As described in the above, according to the first to fifth embodiments, the decision feedback equalizer111may be implemented with a smaller amount of hardware. As a consequence, performance of equalization may be improved, and thereby larger channel loss may be compensated with a smaller number of bits of the analog-digital converter103. In addition, since the correction value generating circuit108generates a predetermined correction value irrespective of phase, so that the amount of hardware may be reduced. Reduction in the amount of hardware of the analog-digital converter103and the digital circuit yields an effect of reducing occupied space and power consumption of the receiving circuit. In short, the first to fifth embodiments enable highly accurate decoding of data only with a less amount of hardware, and implement space saving and power saving.

The present invention enables highly accurate decoding of data only with a less amount of hardware, and implement space saving and power saving.