ESD power clamp with stable power start up function

An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.

BACKGROUND

1. Field of the Disclosure

The present disclosure generally relates to the field of integrated circuits having an internal circuitry and a protection circuit to minimize the risk of damage due to electrostatic discharge (ESD) events.

2. Description of the Related Art

In modern integrated circuits usually a very large number of individual circuit elements, such as field effect transistors, capacitors, resistors and the like are formed on a small substrate area to provide the required functionality of the circuitry. Typically, a number of contact pads are provided, which, in turn, are electrically connected to respective terminals, also referred to as pins, to allow the circuitry to communicate with the environment to provide the required input/output (I/O) capabilities. As feature sizes of the circuit elements are steadily shrinking to increase packing density and enhance performance of the integrated circuit, the ability for withstanding an externally applied over-voltage to any of the pins of the integrated circuit decreases significantly. One reason for this resides in the fact that decreasing feature sizes of field effect transistors, which is a dominant design component of complex circuitry based on CMOS technology, i.e., reducing the channel length of the field effect transistor, typically also requires scaling down the thickness of the insulation layer separating the gate electrode from the channel region in order to maintain controllability of a channel that forms at the gate insulation layer upon application of an appropriate control voltage to the gate electrode. Any over-voltage supplied to the thin gate insulation layer, however, will lead to defects in the gate insulation layer, resulting in reduced reliability, or to destruction, possibly resulting in a complete failure of the integrated circuit.

One major source of such over-voltages are so-called electrostatic discharge (ESD) events, wherein an object carrying charges is brought into contact with one or more of the pins of the integrated circuit. For example, a person can develop very high static voltage from a few hundred to several thousand volts, merely by moving across a carpet, so that an integrated circuit may be damaged when the person contacts the integrated circuit, for example, by removing the integrated circuit from the corresponding circuit board. A corresponding over-voltage caused by an ESD event may even occur during the manufacturing of the integrated circuit and may thus lead to a reduced product yield. Moreover, nowadays there is an increasing tendency to use replaceable integrated circuits in electronic systems so that only one or more integrated circuits have to be replaced instead of the whole circuit board in order to, for example, upgrade microprocessors and memory cards. Since the re-installation or replacement of integrated circuits is not necessarily carried out by a skilled person in an ESD-safe environment, the integrated circuits have to be provided with corresponding ESD protection. To this end, a number of protective circuits have been proposed that are typically arranged between a terminal of the integrated circuit and the internal circuit to provide a current path ensuring that the voltage applied to the internal circuit remains well below a specified critical limit. For example, in a typical ESD event caused by a charge carrying person, a voltage of several thousand volts is discharged in a time interval of about 100 ns (nanoseconds) or less, thereby creating a current of several amperes. Thus, the ESD protection circuit must allow a current flow of at least several amperes to ensure that the voltage across the ESD protection circuit does not exceed the critical limit.

A plurality of ESD protection circuits have been developed which basically attempt to provide appropriately designed current paths in order to discharge excess charge without damaging the sensitive circuit components of functional blocks in the integrated circuit. For example, a relatively straightforward approach is frequently used, in which each of the input/output terminals may be associated with a dedicated protection circuit, for instance in the form of diodes to enable a current flow between a respective pair of input/output terminals, across which an undesired high voltage may occur during an ESD event. Respective approaches may be referred to as pad-based ESD protection. Hence, in this case, a solid ESD current path has to be provided, which may provide the required current drive capability in both possible current flow directions. In CMOS technology, for this purpose, frequently NMOS transistor elements may be used with several configurations, such as gate grounded NMOS transistors, gate coupled NMOS transistors and the like. Typically, the NMOS transistor element may be operated during an ESD event by using the parasitic bipolar transistor, which, however, may, in sophisticated CMOS technologies, require significant efforts in obtaining sufficient current drive capabilities of the respective parasitic components. Therefore, the design of appropriate ESD protection circuits using the pad-based approach may be less flexible with respect to portability to different manufacturing technologies.

In another strategy, the excess charge created by an ESD event may be supplied to the supply voltage power rail and may then be shorted to the ground via an appropriately designed power clamp circuit, which may be provided in the form of an appropriately designed transistor element. Since the power clamp must not be enabled during normal operational conditions, for instance during power up and continuous operation, a trigger circuit may be required to appropriately activate the power clamp upon occurrence of an ESD event, while avoiding the activation of the power clamp in other cases. Although this approach, frequently referred to as rail-based ESD protection, may include more complex circuitry and may involve a high current path via a first ESD protection element connecting a respective input/output terminal with the VDDpower rail and subsequently connecting the power rail to the ground rail via the power clamp circuit, this technique is less dependent on technology-specific characteristics and may therefore provide a higher degree of flexibility during technology changes. For this reason, the rail-based ESD protection technique may be frequently employed in complex CMOS technology. However, although significant advantages with respect to design flexibility and independence of technological characteristics may be provided by the rail-based approach, in certain approaches, the high probability of creating erroneous trigger situations may occur, which will be explained in more detail with reference toFIGS. 1a-1c.

FIG. 1aschematically illustrates an integrated circuit100comprising a typical rail-based protection circuitry which may include a primary ESD protection circuit110, for instance, provided in the form of a high current diode structure, as previously explained. The primary ESD circuit110may thus be directly connected to an input/output pad103, which may be connected to an output stage104of a functional block105of the integrated circuit100, which has to be protected with respect to high voltage pulses, such as ESD events. Thus, the primary ESD circuit110may typically be designed so as to restrict a voltage at the input/output pad103to a tolerable value during certain ESD events. Furthermore, a secondary ESD circuit120may be connected to an input stage106of the internal circuit105and may be coupled to the input/output pad103via a resistive structure111. Hence, the secondary ESD circuit120may be essential in protecting the highly sensitive input stage106, which may comprise advanced transistor elements having extremely sophisticated gate dielectrics, as previously discussed. Furthermore, the integrated circuit100typically comprises a first power rail101, which may receive the supply voltage VDDduring normal operation of the device100. Similarly, a second power rail102is provided, i.e., a power rail for connecting the ground potential or “negative” supply voltage VSSto the circuit100. Additionally, the circuit100comprises a further ESD protection circuit130including a trigger circuit140and a power clamp circuit150. For example, the power clamp circuit150may be provided in the form of a high current N-channel field effect transistor having the required current drive capability for accommodating the high current flow created during an ESD event. The trigger circuit140comprises a trigger stage160, which may comprise a resistor161and a capacitor162, which may commonly define an RC time constant. Furthermore, the trigger circuit140comprises a first inverter stage170, a second inverter stage180and a third inverter stage190, connected in series between the trigger stage160and a control input151of the power clamp transistor150.

During normal operation, the supply voltage may be applied across the first and second power rails101and102, thereby resulting in the supply voltage occurring at the input node of the first inverter stage170after the settling time of the RC trigger stage160. That is, if the RC time constant of the trigger stage160is significantly less than the rise time of the supply voltage upon powering up the circuit100, the voltage at the input of the inverter stage170may rise substantially in the same manner as the slowly rising supply voltage at the power rail101. Due to the chain of the inverter stages170,180,190, the output of the last inverter stage190, and thus the control gate151of the power clamp transistor150, may remain in a low state, thereby avoiding a shorting of the power rails101,102.

FIG. 1bschematically illustrates the circuit100during the occurrence of an ESD event. It may be assumed that a high voltage signal, such as a contact with a human body and the like, may result in the creation of excess charge at the input/output pad103. As previously indicated, a respective ESD pulse may have significantly shorter rise times in the order of approximately some tens of nanoseconds, which may be comparable to the RC time constant of the trigger stage160. Thus, during the occurrence of the ESD event, the primary and secondary ESD circuits110,120may become conductive and may connect the pad103to the power rail101, thereby creating an increase of voltage across the power rails101and102. Due to the relatively short rise time that may be comparable to the RC time constant of the trigger stage160, the voltage at the input of the inverter stage170may remain at a relatively low level, while the “supply voltage” may rise in a fast manner according to the rise time of the ESD pulse. Consequently, the output of the first inverter stage170may turn into a high state, that is, it may follow the rising voltage VDD, thereby also resulting in a high state at the control gate151of the power clamp transistor150, which may therefore be turned on, thereby providing a conductive path between the power rails101and102for discharging the excess charge transferred to the input/output pad103. Hence, the voltage at the input/output103may be maintained at a non-critical value, while also maintaining the voltage drop across the power rails101,102at a non-critical value. Thus, upon appropriately dimensioning the RC time constant of the trigger stage160, an appropriate trigger behavior of the ESD protection circuit130may be accomplished, in which it may be distinguished between a normal power up situation and the occurrence of a fast pulse, as is typically the case in ESD situations. However, in complex CMOS designs, resistors may typically be provided in the form of field effect transistors so as to save valuable semiconductor area in the chip. In this case, the trigger behavior of the circuit160may differ from the operational behavior described above for the following reasons.

FIG. 1cschematically illustrates the trigger circuit160in the conventional arrangement as described above on the left-hand side and the corresponding arrangement of the trigger circuit160in accordance with a design in which the resistor161is replaced by a P-channel transistor163. Furthermore, as illustrated, the capacitor162may be provided in the form of the parasitic capacitance, i.e., the gate/drain and the gate/source capacitance of a field effect transistor164. For this purpose, the transistor163is typically designed so as to exhibit a corresponding resistance to obtain, in combination with the parasitic capacitance of the transistor164, the required RC time constant. However, due to the fact that the transistor163may become conductive only after exceeding the threshold voltage, which may be dependent on the overall design of the transistor163, the actual RC time constant may be significantly higher at an initial phase upon applying voltage to the power rail101. Hence, in this situation, the RC time constant of the trigger stage160as shown on the right-hand side may become comparable to the rise time of a power up situation, since the transistor163may not be conductive at all when the input voltage is below the threshold voltage, which may finally result in an incorrect triggering of the power clamp transistor150. Thus, during power up events of the device100, a significant current may be drawn by the power clamp transistor150, which may significantly reduce overall performance of the device100in view of settling time and overall power consumption, while also requiring an increase current drive capability of a power source for supplying the circuit100.

SUMMARY OF THE DISCLOSURE

The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects disclosed herein. This summary is not an exhaustive overview, and it is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

Generally, the subject matter disclosed herein relates to techniques and electronic circuits in which area-efficient CMOS designs may be used in providing an efficient rail-based ESD protection circuit, that is, resistors may be replaced by field effect transistors, while, nevertheless, providing an improved trigger behavior of the ESD circuit during power up situations. To this end, the inverter stages used in the trigger circuit may be appropriately modified compared to conventional strategies to provide a different response to a fast rising “supply voltage” and a slowly rising normal supply voltage during an initial phase of an ESD situation or a power up, when an “RC” component comprised of field effect transistors may exhibit a moderately high RC time constant. In some illustrative aspects disclosed herein, this imbalance in the response of the inverter stages to the rising supply voltage may be efficiently “amplified” by providing a positive feedback from the second inverter stage to the first inverter stage, thereby reliably “clamping” the respective output nodes of these inverters to obtain the desired trigger behavior. Hence, erroneous trigger events during a power up situation may be avoided or at least substantially reduced.

One illustrative integrated circuit disclosed herein comprises a first power rail and a second power rail. Furthermore, a power clamp is connected between the first and second power rails and a trigger circuit is connected to the power clamp and the first and second power rails. The trigger circuit comprises an RC element formed on the basis of field effect transistors. The trigger circuit further comprises a first inverter stage connected to the RC element, a second inverter stage and a third inverter stage, which are connected in series to a control input of the power clamp. Furthermore, the trigger circuit comprises a feedback connection from an output of the second inverter stage to the first inverter stage.

One illustrative ESD protection circuit disclosed herein comprises a trigger node formed by a P-channel transistor and an N-channel transistor and a first inverter stage, a second inverter stage and a third inverter stage connected in series, wherein an input of the first inverter stage is connected to the trigger node. The ESD protection circuit further comprises an N-channel power clamp transistor having a drain/source path connected between a first power rail and a second power rail and having a gate terminal connected to an output of the third inverter stage. Additionally, the ESD protection circuit comprises a feedback P-channel transistor connected to the first and second inverter stages to provide a positive feedback signal.

One illustrative integrated circuit disclosed herein comprises a protection circuit configured to connect a first power rail with a second power rail. The protection circuit comprises a plurality of P-channel transistors and N-channel transistors connected to form a trigger circuit including a trigger stage, a first inverter stage, a second inverter stage and a third inverter stage. An output of the first inverter stage has a shorter rise time compared to a rise time of an output of the second inverter stage for high voltage signal applied to the first and second power rails that has a rise time of approximately 100 nanoseconds and less. Furthermore, the output of the first inverter stage has a longer rise time than a rise time of the output of the second inverter stage for a voltage signal applied to the first power rail that has a rise time of approximately 200 nanoseconds or more. Finally, the integrated circuit comprises an N-channel power clamp transistor connected to the trigger circuit.

DETAILED DESCRIPTION

Generally, the circuits and techniques disclosed herein provide an enhanced trigger behavior of ESD protection circuits, which may be designed in accordance with space-efficient design approaches, in which resistive structures are represented by field effect transistors. Since the RC time constant of an RC network comprised of field effect transistors may, at least at an initial phase of the normal power up situation, still be significantly high, thereby conventionally resulting in an erroneous triggering of the power clamp stage, the techniques disclosed herein provide an appropriate response of the trigger circuit such that, for moderately long rise times of the signal at VDD, an “imbalance” between the first output node and the second output node of the inverter stages may be introduced and, in some illustrative aspects, “amplified” so as to substantially avoid the turning on of the power clamp stage. For this purpose, the design and the hardware configuration of the inverter stages may be appropriately adapted, while additionally a positive feedback loop may be established, so as to stabilize the desired imbalance in responding to voltage signals at the power rail VDDof different rise times and thus of different slew rates. Consequently, advanced design approaches for complex circuits on the basis of CMOS technology may be realized with enhanced performance due to the avoidance or at least significant reduction of miss-trigger events during a power up situation, while nevertheless providing the desired ESD protection behavior.

FIG. 2aschematically illustrates a circuit diagram of an integrated circuit200, which may comprise an “internal” circuit205the components of which, such as input stages206and output stages204, may have to be protected with respect to high current/high voltage events, such as ESD situations, in which undesired excess charge may be applied to an input/output pad203. For example, a primary ESD circuit210may be directly connected to the input/output pad203, for instance in the form of diode structures having a high current drive capability. Similarly, a secondary ESD circuit220may be connected to the input stage206, which in turn may be connected to the pad203via a resistor221. Furthermore, the circuit200may comprise an ESD protection circuit230, which may include a trigger circuit240and an output power clamp stage250connected to the trigger circuit240. For example, as previously explained, the power clamp stage250may be provided in the form of an N-channel transistor comprising a drain/source path252for connecting a first power rail201, i.e., a power rail corresponding to the VDDline, with a second power rail202, i.e., a power rail corresponding to ground or VSSpotential. The drain/source path252may be controlled by a control input or gate terminal251. Consequently, a voltage at the control terminal251above a threshold voltage of the power clamp stage250may result in a reduced resistivity of the drain/source path252.

The trigger circuit240may comprise a trigger stage260representing an RC component comprised of a P-channel transistor263and an N-channel transistor264connected such that a trigger node265may be defined. Hence, the transistor263may act as a resistor when a voltage difference between a source terminal263S and a gate terminal263G is approximately at or above the threshold voltage of the transistor263. The threshold voltage represents the voltage at which a source/drain path of the transistor263forms a conductive channel, the resistance value of which may be substantially constant for moderately low voltages VDD. Thus, below the threshold value of the transistor263, the trigger stage260may have a high RC constant, substantially defined by leakage currents of the transistor263and the capacitance of the transistor264, as previously explained.

The trigger circuit240may further comprise a first inverter stage270, a second inverter stage280and a third inverter stage290, which are connected in series. That is, an output of the first inverter stage270may be connected to an input of the second inverter stage280, thereby defining a first node N1. Similarly, an output of the second inverter stage280may be connected to an input of the third inverter stage290, thereby defining a second node N2. Moreover, an output of the inverter stage290may be connected to the control terminal251. As previously explained, the inverters270,280and290may be formed on the basis of a circuit design using P-channel transistors and N-channel transistors, without providing space-consuming resistive structures so as to obtain a space-efficient overall circuit design for the circuit200. Furthermore, the inverter stages270,280and290may be designed such that, upon providing a voltage signal at the first power rail201having a rise time of approximately 100 nanoseconds and less, as may usually be the case during ESD events, the rise time T1rof the node N1may be inherently less compared to a rise time T2rof node N2. For example, design-specific characteristics may be used, for instance, by appropriately selecting the pull-up and/or pull-down strength of the individual inverter stages270,280,290, the threshold voltages of respective transistor elements comprised therein and the like, in order to obtain the desired behavior for voltages at VDDhaving a high slew rate.

Consequently, the operational behavior of the inverter stages270,280,290may be defined by design-specific characteristics and may, therefore, be appropriately implemented to the actual manufacturing process and may also result in an appropriate behavior during simulation and verification of the circuit200. Furthermore, the inverter stages270,280,290may further be designed such that, for a voltage signal at the power rail201having a moderately “long” rise time of approximately 200 nanoseconds and more, the rise time T1rat node N1may be longer compared to the rise time T2rat node N2, so that, in this situation, node N2may charge up faster compared to node N1.

FIG. 2bschematically illustrates a time diagram, which qualitatively illustrates the situation for a fast rising signal at VDD, as may typically occur during ESD events. In this case, a signal at the first power rail201may rise within a time interval of approximately 100 nanoseconds and significantly less, as indicated by curve A. Therefore, the trigger stage260may respond to the voltage VDDby charging the “capacitor”264when the respective threshold voltage Vtof the transistor263is exceeded, as indicated by curve B. For convenience, the threshold voltage Vtis illustrated as a relatively high value. On the other hand, the rising voltage VDDmay result, according to the operational behavior as described with reference toFIG. 2a, in an increase of the voltages of the nodes N1and N2, for instance via the respective P-channel transistors of the inverter stages270,280. For example, curve C representing the voltage at node N2may, for instance, rise with a reduced slope compared to a voltage at the node N1, represented by curve D, which, for instance, may be accomplished by appropriately adjusting the current drive capabilities of the respective inverter stages. It should be appreciated that also respective threshold voltages of the transistors may be appropriately adjusted to obtain the desired behavior. Consequently, the slightly higher voltage at node N1may maintain the voltage at N2at a low level, thereby resulting in a high level at the last inverter stage290, which may result in turning on the power clamp250, thereby providing a discharge path through the drain/source path252. Hence, in this case, the desired ESD behavior may be obtained.

FIG. 2cschematically illustrates the situation for a slowly rising voltage at the power rail201, which is qualitatively illustrated by curve A, wherein it may be assumed that, after a time interval of approximately 200 nanoseconds and significantly more, the voltage VDDmay have settled. Thus, compared to the situation as shown inFIG. 2b, the voltage VDDrepresented by curve A may be considered as a signal having a moderately low slew rate. The trigger stage260may have a very high RC time constant until VDDhas reached the threshold voltage of the corresponding transistor261, as previously indicated. In this situation, however, due to appropriate configuration of the inverter stages270,280,290, as previously described, the voltage at the node N2, indicated by curve C, may rise faster, for instance by providing transistors of a reduced threshold voltage in the inverter stage280compared to the stage270, so that charging of node N2may start earlier compared to node N1, even though the inverter stage270may have a higher current drive capability, as previously explained. Consequently, node N2may drive inverter stage290so as to maintain its output and thus the control terminal251at a low level, thereby avoiding the turning on of the drain/source path252. Consequently, during the initial phase of the voltage rise at the power rail201, a miss triggering of the power output clamp250may be avoided.

FIG. 2dschematically illustrates the ESD protection circuit230according to further illustrative embodiments, in which the initially created imbalance between the different charging behavior at the nodes N1and N2during a normal power-up situation, as shown inFIG. 2c, may be stabilized. For this purpose, a positive feedback loop274may be provided between the inverter stage280, that is, the output node N2, and the inverter stage270, so as to maintain the node N1at a low level during the time interval after the initial power-on event until the trigger circuit260may exhibit the desired behavior so as to force the output node N1to a low level. For this purpose, the inverter stage270may be considered as comprising a P-channel transistor271and an N-channel transistor272, wherein the resistance of the P-channel transistor271may be assumed to be a controllable “resistor,” at least a portion of which may also be controlled by the voltage of N2, which is fed back via the loop274. For example, as illustrated a “variable resistor”273may be provided in the current path between the power rail201and the output node N1, thereby enabling a slowing down of the charging up of the node N1, when the “resistor273” has a higher resistance. In this sense, a positive feedback may be considered as a mechanism in which the loop274may provide an increased “resistance” of the “resistor”273, when a voltage at N2increases, while a decreasing voltage at N2may result in a reduced resistance value of the “resistor”273. Hence, when increasing the voltage at node N2, the resistance of the “resistor”273may also increase, thereby further reducing the charging up of the node N1. Finally, N1will settle at VSS, thereby clamping N2to the rising voltage VDD. Hence, a stable behavior of the output nodes N1and N2may be accomplished until finally the trigger voltage at the node265holds the node N1at low level, as in the conventional trigger circuit, such as the trigger circuit130having a resistor in the trigger stage160, as previously described.

FIG. 2eschematically illustrates the ESD protection circuit230according to further illustrative embodiments. As illustrated, in the first inverter stage270, the positive feedback is accomplished by a P-channel transistor273that is connected with its source/drain path273S between the output node N1and a source/drain path271S of the P-channel transistor271. Furthermore, a gate273G is connected to the output node N2of the second inverter stage280. Thus, the desired positive feedback behavior may be accomplished, as previously explained. Furthermore, the inverter stage280may comprise a P-channel transistor281and an N-channel transistor282, wherein a first field effect transistor, that is, a P-channel transistor231, may be connected with its source/drain path231S between the power rail201and a transistor281, while the gate231G may be connected to the control input251. Furthermore, a second P-channel transistor232may be connected with its source/drain path232S to the output node N2of the second stage280, while a gate232G may be connected to the control input251.

Thus, during an ESD event or any other fast rising voltage at the power rail201, the ESD protection circuit230may respond as follows. Initially, all node voltages in the circuit may be zero. Upon application of the fast rising voltage at the power rail201, node N1may be charged faster compared to node N2, as previously explained, thereby creating a rising voltage, which causes the voltage at node N2to decrease via the N-channel transistor282. In this case, the control voltage for the feedback transistor273may also be pulled down, thereby further reducing the overall resistance in the current path that charges node N1so that finally N1will settle at the voltage currently occurring at the power rail201, while node N2may be clamped to the voltage at power rail202, that is, VSS. Consequently, the power clamp transistor250may be reliably turned on as desired.

During normal power-up mode, N2may charge up to a slightly higher voltage compared to node N1via the transistors231and281and also via the transistor232, as previously explained. Again, the positive feedback provided by the transistor273may result in a stabilization, since the increasing voltage at N2may further slow down the charging of node N1, thereby resulting in settling of N1at VSS, while N2may settle at VDD, thereby reliably maintaining the power clamp transistor250in its off state, as desired.

Consequently, an enhanced performance of the circuit200during standard power-on situations may be accomplished, although resistive structures may be realized by field effect transistors.

It should be appreciated that the circuit200may be manufactured on the basis of well-established techniques so that a predictable and reliable operational behavior may be obtained, as previously explained. For example, the respective circuit elements, i.e., the P-channel transistors and N-channel transistors, of the circuit200may be formed on the basis of well-established manufacturing techniques adapted to the technology standard under consideration. Thus, after designing and verifying the circuit200and, in particular, the ESD protection circuit230, enhanced operational behavior may be obtained while, nevertheless, providing a space-efficient configuration.