Pixel current detection circuit and method, and display device

The present disclosure provides a pixel current detection circuit, a pixel current detection method, and a display device. The pixel current detection circuit includes: a pixel current conversion circuit which obtains a first pixel current, a second pixel current and a third pixel current according to an input pixel current to be detected, wherein a ratio of the first pixel current to the second pixel current and a ratio of the second pixel current to the third pixel current are predetermined values; and a current detection circuit which is connected to the pixel current conversion circuit, converts the first pixel current into a first detection voltage, the second pixel current into a second detection voltage, and the third pixel current into a third detection voltage, and determines the pixel current according to the first detection voltage, the second detection voltage and the third detection voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. national phase of PCT Application No. PCT/CN2019/097857 filed on Jul. 26, 2019, which claims priority to Chinese Patent Application No. 201810845464.0 filed on Jul. 27, 2018, which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, and in particular to a pixel current detection circuit, a pixel current detection method, and a display device.

BACKGROUND

In the design of an Active-Matrix Organic Light Emitting Diode (AMOLED) display panel, due to the instability of the device, an external compensation circuit is typically provided to compensate for the threshold voltage shift and change in mobility of the device. When the pixel current is detected in the external compensation circuit, an integration circuit composed of a differential operational amplifier is required. The external compensation technology detects the electrical characteristics of a driving transistor, corrects the data voltage based on the detection result, and compensates for the differences in the electrical characteristics of the driving transistor.

In the related art, in order to detect the electrical characteristics of the driving transistor, a current detection circuit is installed in a source driver. The pixel current flowing through the driving transistor when the light emitting element emits light is detected directly by the current detection circuit, and the pixel current is accumulated for a specified amount of time by an integrator connected to an external compensation line and is converted to a detection voltage. The detection voltage is sampled by using an Analog-to-Digital Converter (ADC) to obtain a digital sensing value. The ADC is a device that converts analog signals into digital signals. The input voltage range of the ADC is fixed. When the pixel current is too large, the ADC cannot detect it (for example, in a case that the maximum input voltage that the ADC can read is 5V, when the input terminal of the ADC receives a detection voltage higher than 5V, the digital voltage output by the ADC still corresponds to 5V, which means that the ADC cannot sample an excessive detection voltage). When the pixel current is too small, the voltage detected by the ADC will be inaccurate.

SUMMARY

The present disclosure provides a pixel current detection circuit which is applied to a pixel circuit and configured to detect a pixel current in the pixel circuit. The pixel current detection circuit includes:

a pixel current conversion circuit which obtains a first pixel current, a second pixel current and a third pixel current according to an input pixel current to be detected, wherein a ratio of the first pixel current to the second pixel current and a ratio of the second pixel current to the third pixel current are predetermined values; and

a current detection circuit connected to the pixel current conversion circuit, the current detection circuit converts the first pixel current into a first detection voltage, converts the second pixel current into a second detection voltage, and converts the third pixel current into a third detection voltage, and determines the pixel current according to the first detection voltage, the second detection voltage and the third detection voltage.

Optionally, the first pixel current is less than the pixel current, the third pixel current is greater than the pixel current;

the current detection circuit is configured to convert the first pixel current into a first detection voltage, and convert the third pixel current into a third detection voltage.

Optionally, the current detection circuit includes a first conversion sub-circuit, a second conversion sub-circuit, a third conversion sub-circuit, and a detection sub-circuit;

the first conversion sub-circuit is connected to the pixel current conversion circuit to receive the first pixel current, and converts the first pixel current into the first detection voltage;

the second conversion sub-circuit is connected to the pixel current conversion circuit to receive the second pixel current, and converts the second pixel current into the second detection voltage;

the third conversion sub-circuit is connected to the pixel current conversion circuit to receive the third pixel current, and converts the third pixel current into the third detection voltage;

the detection sub-circuit is connected with the first, second and third conversion sub-circuits, and is configured to determine the pixel current according to the first, second and third detection voltages.

Optionally, the detection sub-circuit further includes an analog-to-digital converter, a comparator, and a pixel current acquisition circuit;

the analog-to-digital converter is configured to sample the first detection voltage in a first sampling period of a sampling stage and convert the first detection voltage into a first digital voltage, to sample the second detection voltage in a second sampling period of the sampling stage and convert the second detection voltage into a second digital voltage, and to sample the third detection voltage in a third sampling period of the sampling stage and convert the third detection voltage into a third digital voltage;

the comparator is configured to compare the second digital voltage with a predetermined maximum digital voltage and with a predetermined minimum digital voltage, and to output the first digital voltage when the second digital voltage is higher than the predetermined maximum digital voltage, to output the third digital voltage when the second digital voltage is lower than the predetermined minimum digital voltage, and to output the second digital voltage when the second digital voltage is higher than or equal to the predetermined minimum digital voltage and lower than or equal to the predetermined maximum digital voltage;

the pixel current acquisition circuit is configured to calculate the pixel current according to an output result of the comparator.

Optionally, the pixel current conversion circuit includes a first pixel current output terminal for outputting the first pixel current;

the first conversion sub-circuit includes a first differential operational amplifier, a first storage capacitor, a second storage capacitor, a first switch, a second switch, and a third switch; the detection sub-circuit further includes a first initialization circuit;

an inverting input terminal of the first differential operational amplifier is connected to the first pixel current output terminal, a non-inverting input terminal of the first differential operational amplifier is connected to a reference voltage input terminal; the reference voltage input terminal is used to input a reference voltage;

the first switch and the first storage capacitor are connected in parallel between the inverting input terminal of the first differential operational amplifier and an output terminal of the first differential operational amplifier;

the output terminal of the first differential operational amplifier is connected to a first terminal of the second switch, a second terminal of the second switch is connected to a first terminal of the third switch, a second terminal of the third switch is connected to the analog-to-digital converter;

a first terminal of the second storage capacitor is connected to the second terminal of the second switch, a second terminal of the second storage capacitor is connected to a first voltage input terminal;

the first initialization circuit is configured to provide the reference voltage to the inverting input terminal of the first differential operational amplifier and/or the output terminal of the first differential operational amplifier in an initial stage;

the first switch is configured to turn on or turn off a connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier;

the second switch is configured to turn on or turn off a connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor;

the third switch is configured to turn on or turn off a connection between the first terminal of the second storage capacitor and the analog-to-digital converter.

Optionally, the first switch is configured to turn on, in the initial stage, the connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier, and to turn off, in an integration stage and the sampling stage, the connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier;

the second switch is configured to turn on, in the initial stage and the integration stage, the connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor, and to turn off, in the sampling stage, the connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor;

the third switch is configured to turn off, in the initial stage, the integration stage and the sampling stage except for the first sampling period, the connection between the first terminal of the second storage capacitor and the analog-to-digital converter, and to turn on the connection between the first terminal of the second storage capacitor and the analog-to-digital converter in the first sampling period.

Optionally, the pixel current conversion circuit includes a second pixel current output terminal for outputting the second pixel current;

the second conversion sub-circuit includes a second differential operational amplifier, a third storage capacitor, a fourth storage capacitor, a fourth switch, a fifth switch, and a sixth switch; the detection sub-circuit further includes a second initialization circuit;

an inverting input terminal of the second differential operational amplifier is connected to the second pixel current output terminal, a non-inverting input terminal of the second differential operational amplifier is connected to a reference voltage input terminal; the reference voltage input terminal is used to input a reference voltage;

the fourth switch and the third storage capacitor are connected in parallel between the inverting input terminal of the second differential operational amplifier and an output terminal of the second differential operational amplifier;

the output terminal of the second differential operational amplifier is connected to a first terminal of the fifth switch, a second terminal of the fifth switch is connected to a first terminal of the sixth switch, a second terminal of the sixth switch is connected to the analog-to-digital converter;

a first terminal of the fourth storage capacitor is connected to the second terminal of the fifth switch, a second terminal of the fourth storage capacitor is connected to a first voltage input terminal;

the second initialization circuit is configured to provide the reference voltage to the inverting input terminal of the second differential operational amplifier and/or the output terminal of the second differential operational amplifier in the initial stage;

the fourth switch is configured to turn on or turn off a connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier;

the fifth switch is configured to turn on or turn off a connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor;

the sixth switch is configured to turn on or turn off a connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter.

Optionally, the fourth switch is configured to turn on, in the initial stage, the connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier, and to turn off, in an integration stage and the sampling stage, the connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier;

the fifth switch is configured to turn on, in the initial stage and the integration stage, the connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor, and to turn off, in the sampling stage, the connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor;

the sixth switch is configured to turn off, in the initial stage, the integration stage and the sampling stage except for the second sampling period, the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter, and to turn on, in the second sampling period, the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter.

Optionally, the pixel current conversion circuit includes a third pixel current output terminal for outputting the third pixel current;

the third conversion sub-circuit includes a third differential operational amplifier, a fifth storage capacitor, a sixth storage capacitor, a seventh switch, an eighth switch, and a ninth switch; the detection sub-circuit further includes a third initialization circuit;

an inverting input terminal of the third differential operational amplifier is connected to the third pixel current output terminal, a non-inverting input terminal of the third differential operational amplifier is connected to a reference voltage input terminal; the reference voltage input terminal is used to input a reference voltage;

the seventh switch and the fifth storage capacitor are connected in parallel between the inverting input terminal of the third differential operational amplifier and an output terminal of the third differential operational amplifier;

the output terminal of the third differential operational amplifier is connected to a first terminal of the eighth switch, a second terminal of the eighth switch is connected to a first terminal of the ninth switch, a second terminal of the ninth switch is connected to the analog-to-digital converter;

a first terminal of the sixth storage capacitor is connected to the second terminal of the eighth switch, a second terminal of the sixth storage capacitor is connected to a first voltage input terminal;

the third initialization circuit is configured to provide the reference voltage to the inverting input terminal of the third differential operational amplifier and/or the output terminal of the third differential operational amplifier in the initial stage;

the seventh switch is configured to turn on or turn off a connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier;

the eighth switch is configured to turn on or turn off a connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor;

the ninth switch is configured to turn on or turn off a connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter.

Optionally, the seventh switch is configured to turn on, in the initial stage, the connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier, and to turn off, in an integration stage and the sampling stage, the connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier;

the eighth switch is configured to turn on, in the initial stage and the integration stage, the connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor, and to turn off, in the sampling stage, the connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor;

the ninth switch is configured to turn off, in the initial stage, the integration stage and the sampling stage except for the third sampling period, the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter, and to turn on the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter in the third sampling period.

Optionally, the pixel current conversion circuit includes:

an input transistor having a gate and a first electrode connected to the pixel current, and a second electrode connected to a second voltage input terminal;

a first power-supply transistor having a gate and a first electrode connected to a third voltage input terminal;

a first output transistor having a gate connected to the gate of the input transistor, a first electrode connected to a second electrode of the first power-supply transistor, and a second electrode for outputting the first pixel current;

a second power-supply transistor having a gate and a first electrode connected to the third voltage input terminal;

a second output transistor having a gate connected to the gate of the input transistor, a first electrode connected to a second electrode of the second power-supply transistor, and a second electrode for outputting the second pixel current;

a third power-supply transistor having a gate and a first electrode connected to the third voltage input terminal;

a third output transistor having a gate connected to the gate of the input transistor, a first electrode connected to a second electrode of the third power-supply transistor, and a second electrode for outputting the third pixel current;

a ratio of a width-to-length ratio of the first output transistor to a width-to-length ratio of the input transistor is less than 1, and a ratio of a width-to-length ratio of the third output transistor to the width-to-length ratio of the input transistor is greater than 1.

Optionally, a ratio of a width-to-length ratio of the second output transistor to the width-to-length ratio of the input transistor is in a range greater than or equal to 0.99 and less than or equal to 1.01; the ratio of the width-to-length ratio of the first output transistor to the width-to-length ratio of the input transistor is greater than 0 and less than 0.6, and the ratio of the width-to-length ratio of the third output transistor to the width-to-length ratio of the input transistor is greater than 1.5.

The present disclosure further provides a pixel current detection method applied to the above pixel current detection circuit. The pixel current detection method includes:

a current conversion step of converting the pixel current by the pixel current conversion circuit to obtain a first pixel current, a second pixel current and a third pixel current; and

a current detection step of converting, by the current detection circuit, the first pixel current into a first detection voltage, the second pixel current into a second detection voltage, and the third pixel current into a third detection voltage, and determining the pixel current according to the first detection voltage, the second detection voltage and the third detection voltage.

Optionally, the first pixel current is less than the second pixel current, the third pixel current is greater than the second pixel current;

the current detection circuit includes a first conversion sub-circuit, a second conversion sub-circuit, a third conversion sub-circuit, and a detection sub-circuit; the current detection step includes:

receiving the first pixel current and converting the first pixel current into the first detection voltage by the first conversion sub-circuit;

receiving the second pixel current and converting the second pixel current into the second detection voltage by the second conversion sub-circuit;

receiving the third pixel current and converting the third pixel current into the third detection voltage by the third conversion sub-circuit;

determining the pixel current according to the first, second and third detection voltages by the detection sub-circuit.

Optionally, the detection sub-circuit includes an analog-to-digital converter, a comparator, and a pixel current acquisition circuit; the step of determining the pixel current according to the first, second and third detection voltages by the detection sub-circuit includes:

sampling the first detection voltage in a first sampling period of a sampling stage and converting the first detection voltage into a first digital voltage by the analog-to-digital converter, sampling the second detection voltage in a second sampling period of the sampling stage and converting the second detection voltage into a second digital voltage by the analog-to-digital converter, and sampling the third detection voltage in a third sampling period of the sampling stage and converting the third detection voltage into a third digital voltage by the analog-to-digital converter;

comparing the second digital voltage with a predetermined maximum digital voltage and with a predetermined minimum digital voltage by the comparator, and outputting the first digital voltage when the second digital voltage is higher than the predetermined maximum digital voltage, outputting the third digital voltage when the second digital voltage is lower than the predetermined minimum digital voltage, and outputting the second digital voltage when the second digital voltage is higher than or equal to the predetermined minimum digital voltage and lower than or equal to the predetermined maximum digital voltage;

calculating the pixel current according to an output result of the comparator by the pixel current acquisition circuit.

Optionally, the first conversion sub-circuit includes a first differential operational amplifier, a first storage capacitor, a second storage capacitor, a first switch, a second switch, and a third switch; the detection sub-circuit further includes a first initialization circuit; a detection time includes an initial stage, an integration stage and a sampling stage arranged in sequence; the sampling stage includes a first sampling period; the step of converting the first pixel current into the first detection voltage by the current detection circuit includes:

in the initial stage, turning on a connection between an inverting input terminal of the first differential operational amplifier and an output terminal of the first differential operational amplifier by the first switch, turning on a connection between the output terminal of the first differential operational amplifier and a first terminal of the second storage capacitor by the second switch; turning off a connection between the first terminal of the second storage capacitor and the analog-to-digital converter by the third switch; and providing a reference voltage to the inverting input terminal of the first differential operational amplifier and/or the output terminal of the first differential operational amplifier by the first initialization circuit;

in the integration stage, turning off the connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier by the first switch, turning on the connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor by the second switch, turning off the connection between the first terminal of the second storage capacitor and the analog-to-digital converter by the third switch, and charging the first storage capacitor with the first pixel current;

in the sampling stage, turning off the connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier by the first switch, and turning off the connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor by the second switch; wherein

in the first sampling period, the third switch turns on the connection between the first terminal of the second storage capacitor and the analog-to-digital converter, the analog-to-digital converter samples a voltage at the first terminal of the second storage capacitor, which is the first detection voltage; and

in the sampling stage except for the first sampling period, the third switch turns off the connection between the first terminal of the second storage capacitor and the analog-to-digital converter.

Optionally, the second conversion sub-circuit includes a second differential operational amplifier, a third storage capacitor, a fourth storage capacitor, a fourth switch, a fifth switch, and a sixth switch; the detection sub-circuit further includes a second initialization circuit; a detection time includes an initial stage, an integration stage and a sampling stage arranged in sequence; the sampling stage further includes a second sampling period;

the step of converting the second pixel current into the second detection voltage by the current detection circuit includes:

in the initial stage, turning on a connection between an inverting input terminal of the second differential operational amplifier and an output terminal of the second differential operational amplifier by the fourth switch, turning on a connection between the output terminal of the second differential operational amplifier and a first terminal of the fourth storage capacitor by the fifth switch; turning off a connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter by the sixth switch; and providing a reference voltage to the inverting input terminal of the second differential operational amplifier and/or the output terminal of the second differential operational amplifier by the second initialization circuit;

in the integration stage, turning off the connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier by the fourth switch, turning on the connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor by the fifth switch, turning off the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter by the sixth switch, and charging the third storage capacitor with the second pixel current;

in the sampling stage, turning off the connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier by the fourth switch, and turning off the connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor by the fifth switch; wherein

in the second sampling period, the sixth switch turns on the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter, the analog-to-digital converter samples a voltage at the first terminal of the fourth storage capacitor, which is the second detection voltage; and

in the sampling stage except for the second sampling period, the sixth switch turns off the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter.

Optionally, the third conversion sub-circuit includes a third differential operational amplifier, a fifth storage capacitor, a sixth storage capacitor, a seventh switch, an eighth switch, and a ninth switch; the detection sub-circuit further includes a third initialization circuit; a detection time includes an initial stage, an integration stage and a sampling stage arranged in sequence; the sampling stage further includes a third sampling period;

the step of converting the third pixel current into the third detection voltage by the current detection circuit includes:

in the initial stage, turning on a connection between an inverting input terminal of the third differential operational amplifier and an output terminal of the third differential operational amplifier by the seventh switch, turning on a connection between the output terminal of the third differential operational amplifier and a first terminal of the sixth storage capacitor by the eighth switch; turning off a connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter by the ninth switch; and providing a reference voltage to the inverting input terminal of the third differential operational amplifier and/or the output terminal of the third differential operational amplifier by the third initialization circuit;

in the integration stage, turning off the connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier by the seventh switch, turning on the connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor by the eighth switch, turning off the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter by the ninth switch, and charging the fifth storage capacitor with the third pixel current;

in the sampling stage, turning off the connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier by the seventh switch, and turning off the connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor by the eighth switch; wherein

in the third sampling period, the ninth switch turns on the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter, the analog-to-digital converter samples a voltage at the first terminal of the sixth storage capacitor, which is the third detection voltage;

in the sampling stage except for the third sampling period, the ninth switch turns off the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter.

The present disclosure further provides a display device including the above pixel current detection circuit; the display device further includes a pixel circuit;

the pixel current detection circuit is configured to detect a pixel current in the pixel circuit.

Optionally, the pixel circuit includes a data writing circuit, an energy storage circuit, a driving circuit, a light emitting element, and a current output control circuit;

a control terminal of the data writing circuit is connected to a first scanning line, a first terminal of the data writing circuit is connected to a data line, a second terminal of the data writing circuit is connected to a control terminal of the driving circuit, and the data writing circuit is configured to turn on or turn off a connection between the data line and the control terminal of the driving circuit under control of the first scanning line;

the energy storage circuit is connected to the control terminal of the driving circuit to control a potential of the control terminal of the driving circuit;

a first terminal of the driving circuit is connected to a power supply voltage terminal, a second terminal of the driving circuit is connected to the light emitting element, and the driving circuit is configured to drive the light emitting element to emit light under control of the control terminal thereof,

a control terminal of the current output control circuit is connected to a second scanning line, a first terminal of the current output control circuit is connected to the second terminal of the driving circuit, a second terminal of the current output control circuit is connected to an external compensation line;

the pixel current conversion circuit in the pixel current detection circuit is connected to the external compensation line, and configured to detect the pixel current output from the external compensation line.

DETAILED DESCRIPTION

The transistors adopted in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of a transistor except the gate, one of the two electrodes is referred to as a first electrode, and the other is referred to as a second electrode. In practice, the first electrode may be a drain, and the second electrode may be a source; alternatively, the first electrode may be a source, and the second electrode may be a drain.

The pixel current detection circuit according to an embodiment of the present disclosure is applied to a pixel circuit and is configured to detect the pixel current in the pixel circuit. The pixel current detection circuit includes:

a pixel current conversion circuit which obtains a first pixel current, a second pixel current and a third pixel current according to an input pixel current to be detected, wherein a ratio of the first pixel current to the second pixel current and a ratio of the second pixel current to the third pixel current are predetermined values; and

a current detection circuit which is connected to the pixel current conversion circuit, converts the first pixel current into a first detection voltage, the second pixel current into a second detection voltage, and the third pixel current into a third detection voltage, and determines the pixel current according to the first detection voltage, the second detection voltage and the third detection voltage.

The pixel current detection circuit according to the present disclosure uses the pixel current conversion circuit to convert the pixel current to obtain the first pixel current, the second pixel current and the third pixel current, the current detection circuit obtains the pixel current according to the first detection voltage obtained by converting the first pixel current, the second detection voltage obtained by converting the second pixel current, and the third detection voltage obtained by converting the third pixel current, so that the problem of inaccurate detection results due to the limited detection range of the current detection circuit can be avoided, and the pixel current can be detected accurately, thereby enabling better external compensation.

In practice, the first pixel current is lower than the pixel current to be detected, and the third pixel current is higher than the pixel current to be detected;

the current detection circuit is configured to convert the first pixel current into a first detection voltage, to convert the third pixel current into a third detection voltage.

The pixel current detection circuit according to an embodiment of the present disclosure is applied to a pixel circuit and is configured to detect the pixel current Ip in the pixel circuit. As shown inFIG. 1, the pixel current detection circuit includes:

a pixel current conversion circuit11which is configured to convert the pixel current Ip to obtain a first pixel current I1, a second pixel current I2, and a third pixel current I3; the first pixel current I1is lower than the pixel current Ip, a ratio of the second pixel current I2to the pixel current Ip is within a predetermined ratio range, and the third pixel current I3is higher than the pixel current Ip; and

a current detection circuit I2which is connected to the pixel current conversion circuit I1, and is configured to convert the first pixel current I1into a first detection voltage, the second pixel current I2into a second detection voltage, and the third pixel current I3into a third detection voltage, and obtains the pixel current according to at least one of the first detection voltage, the second detection voltage and the third detection voltage.

The pixel current detection circuit according to the embodiment of the present disclosure uses the pixel current conversion circuit to convert the pixel current Ip to obtain the first pixel current I1, the second pixel current I2and the third pixel current I3; the first pixel current I1is lower than the pixel current Ip, the ratio of the second pixel current I2to the pixel current Ip is within a predetermined ratio range, and the third pixel current I3is higher than the pixel current Ip; the current detection circuit I2obtains the pixel current according to at least one of the first detection voltage obtained by converting the first pixel current I1, the second detection voltage obtained by converting the second pixel current I2, and the third detection voltage obtained by converting the third pixel current I3, so that the problem of inaccurate detection results due to the limited detection range of the current detection circuit can be avoided, and the pixel current can be detected accurately, thereby enabling better external compensation.

Optionally, when the pixel current Ip is too large, the current detection circuit I2obtains the pixel current according to the first detection voltage converted from the current I1; when the pixel current Ip is too small, the current detection circuit I2obtains the pixel current according to the third detection voltage converted from the current I3, so that the pixel current detection result can be accurate.

In some embodiments, the second pixel current I2is equal to the pixel current Ip.

In an embodiment of the present disclosure, the ratio of the second pixel current I2to the pixel current Ip is within a predetermined ratio range. The predetermined ratio range may be greater than or equal to 0.99 and less than or equal to 1.01, so that the current I2and the current Ip are equal or approximately equal.

In practice, the ratio of the first pixel current to the pixel current may be greater than 0 and less than 0.6, and the ratio of the third pixel current to the pixel current may be greater than 1.5.

Optionally, the pixel current conversion circuit I1includes a first pixel current output terminal, a second pixel current output terminal, and a third pixel current output terminal. The first pixel current output terminal is configured to output the first pixel current I1, the second pixel current output terminal is configured to output the second pixel current I2, and the third pixel current output terminal is configured to output the third pixel current3.

Optionally, as shown inFIG. 2, the current detection circuit I2may include a first conversion sub-circuit21, a second conversion sub-circuit22, a third conversion sub-circuit23, and a detection sub-circuit20;

the first conversion sub-circuit21is configured to receive the first pixel current I1, and converts the first pixel current I1into the corresponding first detection voltage VD1;

the second conversion sub-circuit22is configured to receive the second pixel current I2, and converts the second pixel current I2into the corresponding second detection voltage VD2;

the third conversion sub-circuit23is configured to receive the third pixel current I3, and converts the third pixel current I3into the corresponding third detection voltage VD3;

the detection sub-circuit20is connected to the first, second and third conversion sub-circuits21,22and23, and is configured to obtain the pixel current according to at least one of the first, second and third detection voltages VD1, VD2, and VD3.

In practice, the current detection circuit I2includes a first conversion sub-circuit21, a second conversion sub-circuit22, a third conversion sub-circuit23, and a detection sub-circuit20, converts the currents I1, I2, and I3by the first, second and third conversion sub-circuits21,22and23, respectively, so as to obtain the voltages VD1, VD2, and VD3, and obtains the pixel current by the detection sub-circuit20according to at least one of the voltages VD1, VD2, and VD3.

Optionally, as shown inFIG. 3, on the basis of the embodiment shown inFIG. 2, the detection sub-circuit20may include an analog-to-digital converter ADC, a comparator31, and a pixel current acquisition circuit32;

the analog-to-digital converter ADC is configured to sample the first detection voltage VD1in a first sampling period included in a sampling stage and convert the first detection voltage VD1into a first digital voltage Vdig1, to sample the second detection voltage VD2in a second sampling period included in the sampling stage and convert the second detection voltage VD2into a second digital voltage Vdig2, and to sample the third detection voltage VD3in a third sampling period included in the sampling stage and convert the third detection voltage VD3into a third digital voltage Vdig3;

the comparator31is configured to compare the second digital voltage Vdig2with a predetermined maximum digital voltage Vmax, and compare the second digital voltage Vdig2with a predetermined minimum digital voltage Vmin. When the second digital voltage Vdig2obtained by comparing is higher than the predetermined maximum digital voltage Vmax, the comparator31transfer the first digital voltage Vdig1to the pixel current acquisition circuit32; when the second digital voltage Vdig2obtained by comparing is lower than the predetermined minimum digital voltage Vmin, the comparator31transfer the third digital voltage Vdig3to the pixel current acquisition circuit32; when the second digital voltage Vdig2obtained by comparing is higher than or equal to the predetermined minimum digital voltage Vmin and lower than or equal to the predetermined maximum digital voltage Vmax, the comparator31transfer the second digital voltage Vdig2to the pixel current acquisition circuit32.

The pixel current acquisition circuit32is configured to calculate the pixel current according to the output result of the comparator, i.e., the first, second, or third data voltages Vdig1, Vdig2or Vdig.3.

When the second detection voltage VD2is higher than a predetermined maximum input voltage of the analog-to-digital converter ADC, the second digital voltage Vdig2is higher than the predetermined maximum digital voltage Vmax, and thus the pixel current acquisition circuit32obtains the pixel current according to the first digital voltage Vdig1. When the second detection voltage VD2is lower than a predetermined minimum input voltage of the analog-to-digital converter ADC, the second digital voltage Vdig2is lower than the predetermined minimum digital voltage Vmin, and thus the pixel current acquisition circuit32obtains the pixel current according to the third digital voltage Vdig3. When the second detection voltage VD2is higher than or equal to the predetermined minimum input voltage and lower than or equal to the predetermined maximum input voltage, the second digital voltage Vdig2is higher than or equal to the predetermined minimum digital voltage Vmin and lower than or equal to the predetermined maximum digital voltage Vmax, and thus the pixel current acquisition circuit32obtains the pixel current according to the second digital voltage Vdig2.

Optionally, the pixel current acquisition circuit32may be a processor having a computing function and an analog-to-digital conversion function, and they each may be implemented by a circuit or by using software, hardware (circuit), firmware, or any combination thereof, which is not limited in this embodiment. In practice, the predetermined maximum digital voltage Vmax and the predetermined minimum digital voltage Vmin may be selected according to actual situations; for example, when the input voltage range of the analog-to-digital converter ADC is 0V-5V, Vmax may be set to a digital voltage corresponding to 4.8V (that is, Vmax is equal to the digital voltage output by the ADC when the input terminal of the ADC receives a voltage of 4.8V). The voltage Vmin is set to a digital voltage corresponding to 0.5V (that is, Vmax is equal to the digital voltage output by the ADC when the input terminal of the ADC receives a voltage of 0.5V), but not limited to this.

In practice, the predetermined maximum digital voltage Vmax may be a digital voltage corresponding to an analog voltage slightly smaller than an upper limit of the input voltage range of the digital-to-analog converter ADC.

Optionally, as shown inFIG. 4, the first conversion sub-circuit may include a first differential operational amplifier Amp1, a first storage capacitor C1, a second storage capacitor C2, a first switch41, a second switch42, and a third switch43; the detection sub-circuit further includes a first initialization circuit (not shown inFIG. 4);

an inverting input terminal of the first differential operational amplifier Amp1is connected to the first pixel current output terminal (not shown inFIG. 4) included in the pixel current conversion circuit, a non-inverting input terminal of the first differential operational amplifier Amp1is connected to a reference voltage input terminal; the reference voltage input terminal is used to input a reference voltage Vref;

the first switch41and the first storage capacitor C1are connected in parallel between the inverting input terminal of the first differential operational amplifier Amp1and an output terminal of the first differential operational amplifier Amp1;

the output terminal of the first differential operational amplifier Amp1is connected to a first terminal of the second switch42, a second terminal of the second switch42is connected to a first terminal of the third switch43, a second terminal of the third switch43is connected to the analog-to-digital converter (not shown inFIG. 4) included in the detection sub-circuit;

a first terminal of the second storage capacitor C2is connected to the second terminal of the second switch42, a second terminal of the second storage capacitor C2is connected to a first voltage input terminal; the first voltage input terminal is used to input a first voltage V1;

the first initialization circuit (not shown inFIG. 4) is configured to provide the reference voltage Vref to the inverting input terminal of the first differential operational amplifier Amp1and/or the output terminal of the first differential operational amplifier Amp1in an initial stage;

the first switch41is configured to turn on or turn off a connection between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1;

the second switch42is configured to turn on or turn off a connection between the output terminal of the first differential operational amplifier Amp1and the first terminal of the second storage capacitor C2;

the third switch43is configured to turn on or turn off a connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4).

In practice, the first switch41is configured to turn on, in the initial stage, the connection between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1, and to turn off, in an integration stage and the sampling stage, the connection between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1;

the second switch42is configured to turn on, in the initial stage and the integration stage, the connection between the output terminal of the first differential operational amplifier Amp1and the first terminal of the second storage capacitor C2, and to turn off, in the sampling stage, the connection between the output terminal of the first differential operational amplifier Amp1and the first terminal of the second storage capacitor C2;

the third switch43is configured to turn off, in the initial stage, the integration stage and a period included in the sampling stage except for the first sampling period, the connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4), and to turn on, in the first sampling period, the connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4).

In practice, the first switch41may include a first switch element, the second switch42may include a second switch element, and the third switch43may include a third switch element.

In the embodiment shown inFIG. 4, the first voltage input terminal may be a ground terminal or a low voltage input terminal, but is not limited thereto.

As shown inFIG. 5, when the embodiment of the first conversion sub-circuit of the present disclosure shown inFIG. 4is in operation, a detection time TD includes an initial stage Tinit, an integration stage Tsen, and a sampling stage Tsam arranged in sequence; the sampling stage Tsam includes a first sampling period Ts1;

in the initial stage Tinit, S1is at a high level, S2is at a high level, and S3is at a low level. The first switch41turns on the connection between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp, the second switch42turns on the connection between the output terminal of the first differential operational amplifier Amp1and the first terminal of the second storage capacitor C2; the third switch43turns off the connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4); the first initialization circuit (not shown inFIG. 4)) provides the reference voltage Vref to the inverting input terminal of the first differential operational amplifier Amp1and/or an output terminal of the first differential operational amplifier Amp1, so that the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1are connected to Vref, thereby eliminating the influence of previous data on the detection result;

in the integration stage Tsen, S is at a low level, S2is at a high level, and S3is at a low level. The first switch41turns off the connection between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1, and the second switch42turns on the connection between the output terminal of the first differential operational amplifier Amp1and the first terminal of the second storage capacitor C2, the third switch43turns off the connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4), charging the first storage capacitor C1by the first pixel current I1;

in the sampling stage Tsam, S1and S2are at a low level, and the first switch41turns off the connection between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1, the second switch42turns off the connection between the output terminal of the first differential operational amplifier Amp1and the first terminal of the second storage capacitor C2;

during the first sampling period Ts1, S3is at a high level, the third switch43turns on the connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4). The analog-to-digital converter samples the voltage at the first terminal of the second storage capacitor C2, which is the first detection voltage VD1;

in a period included in the sampling stage Tsam except for the first sampling period Ts1, S3is at a low level, and the third switch43turns off the connection between the first terminal of the second storage capacitor C2and the analog-to-digital converter (not shown inFIG. 4).

InFIG. 5, the reference sign S represents a first control signal for controlling the first switch41to be turned on or off, the reference sign S2represents a second control signal for controlling the second switch42to be turned on or off, and the reference sign S3represents a third control signal for controlling the third switch43to be turned on or off. In the embodiment shown inFIG. 4, when S1is at a high level, the first switch41is turned on, and when S1is at a low level, the first switch41is turned off; when S2is at a high level, the second switch42is turned on, and when S2is at a low level, the second switch42is turned off; when S3is at a high level, the third switch43is turned on, and when S3is at a low level, the third switch43is turned off.

Optionally, as shown inFIG. 6, the second conversion sub-circuit may include a second differential operational amplifier Amp2, a third storage capacitor C3, a fourth storage capacitor C4, a fourth switch44, a fifth switch45, and a sixth switch46; the detection sub-circuit further includes a second initialization circuit (not shown inFIG. 6);

the inverting input terminal of the second differential operational amplifier Amp2is connected to a second pixel current output terminal (not shown inFIG. 6) included in the pixel current conversion circuit (that is, the inverting input terminal of Amp2receives the second pixel current I2), the non-inverting input terminal of the second differential operational amplifier Amp2is connected to a reference voltage input terminal; the reference voltage input terminal is used to input a reference voltage Vref;

the fourth switch44and the third storage capacitor C3are connected in parallel between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2;

the output terminal of the second differential operational amplifier Amp2is connected to a first terminal of the fifth switch45, and a second terminal of the fifth switch45is connected to a first terminal of the sixth switch46, a second terminal of the sixth switch46is connected to the analog-to-digital converter (not shown inFIG. 6);

a first terminal of the fourth storage capacitor C4is connected to a second terminal of the fifth switch45, and a second terminal of the fourth storage capacitor C4is connected to a first voltage input terminal; the first voltage input terminal is used to input the first voltage V1;

the second initialization circuit (not shown inFIG. 6) is configured to provide the reference voltage to the inverting input terminal of the second differential operational amplifier and/or the output terminal of the second differential operational amplifier in an initial stage;

the fourth switch44is configured to turn on or turn off a connection between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2;

the fifth switch45is configured to turn on or turn off a connection between the output terminal of the second differential operational amplifier Amp2and the first terminal of the fourth storage capacitor C4;

the sixth switch46is configured to turn on or turn off a connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter (not shown inFIG. 6).

In the embodiment shown inFIG. 6, the first voltage input terminal may be a ground terminal or a low voltage input terminal, but is not limited thereto.

In practice, the fourth switch44may include a fourth switch element, the fifth switch45may include a fifth switch element, and the sixth switch46may include a sixth switch element.

In practice, the fourth switch44is configured to turn on, in the initial stage, the connection between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2, and to turn off, in the integration stage and the sampling stage, the connection between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2;

the fifth switch45is configured to turn on, in the initial stage and the integration stage, the connection between the output terminal of the second differential operational amplifier Amp2and the first terminal of the fourth storage capacitor C4, and to turn off, in the sampling stage, the connection between the output terminal of the second differential operational amplifier Amp2and the first terminal of the fourth storage capacitor C4;

the sixth switch46is configured to turn off, in the initial stage, the integration stage and a period included in the sampling stage except for the second sampling period, the connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter (not shown inFIG. 6), and to turn on, in the second sampling period, the connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter.

When the second conversion sub-circuit22of the present disclosure shown inFIG. 6is in operation, a detection time includes an initial stage, an integration stage, and a sampling stage arranged in sequence; the sampling stage further includes a second sampling period;

in the initial stage, the fourth switch44turns on the connection between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2, the fifth switch45turns on the connection between the output terminal of the second differential operational amplifier Amp2and the first terminal of the fourth storage capacitor C4; the sixth switch46turns off the connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter (not shown inFIG. 6); the second initialization circuit (not shown inFIG. 6) provides the reference voltage Vref to the inverting input terminal of the second differential operational amplifier Amp2and/or the output terminal of the second differential operational amplifier Amp2, so that the inverting input terminal of Amp2and the output terminal of Amp2are connected to Vref, thereby eliminating the influence of the previous data on the detection result;

in the integration stage, the fourth switch44turns off the connection between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2, the fifth switch45turns on the connection between the output terminal of the second differential operational amplifier Amp2and the first terminal of the fourth storage capacitor C4, and the sixth switch46turns off the connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter (not shown inFIG. 6), charging the third storage capacitor C3by the second pixel current I2;

in the sampling stage, the fourth switch44turns off the connection between the inverting input terminal of the second differential operational amplifier Amp2and the output terminal of the second differential operational amplifier Amp2, the fifth switch45turns off the connection between the output terminal of the second differential operational amplifier Amp2and the first terminal of the fourth storage capacitor C4;

in the second sampling period, the sixth switch46turns on the connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter (not shown inFIG. 6), and the analog-to-digital converter samples a voltage at the first terminal of the fourth storage capacitor C4, which is the second detection voltage VD2;

in a period included in the sampling stage except for the second sampling period, the sixth switch46turns off the connection between the first terminal of the fourth storage capacitor C4and the analog-to-digital converter (not shown inFIG. 6).

Optionally, as shown inFIG. 7, the third conversion sub-circuit may include a third differential operational amplifier Amp3, a fifth storage capacitor C5, a sixth storage capacitor C6, a seventh switch47, an eighth switch48, and a ninth switch49; the detection sub-circuit further includes a third initialization circuit (not shown inFIG. 7);

an inverting input terminal of the third differential operational amplifier Amp3is connected to a third pixel current output terminal (not shown inFIG. 7) included in the pixel current conversion circuit (that is, the inverting input terminal of Amp3receives the third pixel current I3), a non-inverting input terminal of the third differential operational amplifier Amp3is connected to a reference voltage input terminal; the reference voltage input terminal is used to input a reference voltage Vref;

the seventh switch47and the fifth storage capacitor C5connected in parallel with each other are connected between the inverting input terminal of the third differential operational amplifier Amp3and an output terminal of the third differential operational amplifier Amp3;

the output terminal of the third differential operational amplifier Amp3is connected to a first terminal of the eighth switch48, a second terminal of the eighth switch48is connected to a first terminal of the ninth switch49, a second terminal of the ninth switch49is connected to the analog-to-digital converter (not shown inFIG. 7);

a first terminal of the sixth storage capacitor C6is connected to the second terminal of the eighth switch48, a second terminal of the sixth storage capacitor C6is connected to a first voltage input terminal; the first voltage input terminal is used to input the first voltage V1;

the third initialization circuit (not shown inFIG. 7) is configured to provide the reference voltage Vref to the inverting input terminal of the third differential operational amplifier Amp3and/or the output terminal of the third differential operational amplifier in an initial stage Amp3;

the seventh switch47is configured to turn on or turn off a connection between the inverting input terminal of the third differential operational amplifier Amp3and the output terminal of the third differential operational amplifier Amp3;

the eighth switch48is configured to turn on or turn off a connection between the output terminal of the third differential operational amplifier Amp3and the first terminal of the sixth storage capacitor C6;

the ninth switch49is configured to turn on or turn off a connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter (not shown inFIG. 7).

In practice, the seventh switch47is configured to turn on, in the initial stage, the connection between the inverting input terminal of the third differential operational amplifier Amp3and the output terminal of the third differential operational amplifier Amp3, and to turn off, in an integration stage and the sampling stage, the connection between the inverting input terminal of the third differential operational amplifier Amp3and the output terminal of the third differential operational amplifier Amp3;

the eighth switch48is configured to turn on, in the initial stage and the integration stage, the connection between the output terminal of the third differential operational amplifier Amp3and the first terminal of the sixth storage capacitor C6, and to turn off the connection between the output terminal of the third differential operational amplifier Amp3and the first terminal of the sixth storage capacitor C6in the sampling stage;

the ninth switch49is configured to turn off, in the initial stage, the integration stage and a period included in the sampling stage except for the third sampling period, the connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter (not shown inFIG. 7), and to turn on the connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter in the third sampling period.

In the embodiment shown inFIG. 7, the first voltage input terminal may be a ground terminal or a low voltage input terminal, but is not limited thereto.

In practice, the seventh switch47may include a seventh switch element, the eighth switch48may include an eighth switch element, and the ninth switch49may include a ninth switch element.

When the third conversion sub-circuit23of the present disclosure shown inFIG. 7is in operation, a detection time includes an initial stage, an integration stage, and a sampling stage arranged in sequence; the sampling stage further includes a third sampling period;

in the initial stage, the seventh switch47turns on the connection between the inverting input terminal of the third differential operational amplifier Amp3and the output terminal of the third differential operational amplifier Amp3, the eighth switch48turns on the connection between the output terminal of the third differential operational amplifier Amp3and the first terminal of the sixth storage capacitor C6; the ninth switch49turns off the connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter (not shown inFIG. 7); the third initialization circuit (not shown inFIG. 7) provides the reference voltage Vref to the inverting input terminal of the third differential operational amplifier Amp3and/or the output terminal of the third differential operational amplifier Amp3, so that the inverting input terminal of Amp3and the output terminal of Amp3are connected to Vref, thereby eliminating the influence of the previous data on the detection result;

in the integration stage, the seventh switch47turns off the connection between the inverting input terminal of the third differential operational amplifier Amp3and the output terminal of the third differential operational amplifier Amp3, the eighth switch48turns on the connection between the output terminal of the third differential operational amplifier Amp3and the first terminal of the sixth storage capacitor C6, and the ninth switch49turns off the connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter (not shown inFIG. 7), charging the fifth storage capacitor C5with the third pixel current I3;

in the sampling stage, the seventh switch47turns off the connection between the inverting input terminal of the third differential operational amplifier Amp3and the output terminal of the third differential operational amplifier Amp3, and the eighth switch48turns off the connection between the output terminal of the third differential operational amplifier Amp3and the first terminal of the sixth storage capacitor C6;

in the third sampling period, the ninth switch49turns on the connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter (not shown inFIG. 7), and the analog-to-digital converter samples a voltage at the first terminal of the sixth storage capacitor C6, which is the third detection voltage VD3;

in a period included in the sampling stage except for the third sampling period, the ninth switch49turns off the connection between the first terminal of the sixth storage capacitor C6and the analog-to-digital converter (not shown inFIG. 7).

Optionally, the pixel current conversion circuit may include:

an input transistor having a gate and a first electrode connected to the pixel current, and a second electrode connected to a second voltage input terminal;

a first power-supply transistor having a gate and a first electrode connected to a third voltage input terminal;

a first output transistor having a gate connected to the gate of the input transistor, a first electrode connected to a second electrode of the first power-supply transistor, and a second electrode for outputting the first pixel current;

a second power-supply transistor having a gate and a first electrode both connected to the third voltage input terminal;

a second output transistor having a gate connected to the gate of the input transistor, a first electrode connected to a second electrode of the second power-supply transistor, and a second electrode for outputting the second pixel current;

a third power-supply transistor having a gate and a first electrode both connected to the third voltage input terminal;

a third output transistor having a gate connected to the gate of the input transistor, a first electrode connected to a second electrode of the third power-supply transistor, and a second electrode for outputting the third pixel current;

a ratio of a width-to-length ratio of the first output transistor to a width-to-length ratio of the input transistor is less than 1, and a ratio of a width-to-length ratio of the third output transistor to the width-to-length ratio of the input transistor is greater than 1.

In practice, the second voltage input terminal may be a ground terminal or a low voltage input terminal, but is not limited thereto.

In practice, the third voltage input terminal may be a high voltage input terminal, but is not limited thereto.

Optionally, the ratio of the width-to-length ratio of the first output transistor to the width-to-length ratio of the input transistor may be greater than 0 and less than 0.6, and the ratio of the width-to-length ratio of the third output transistor to the width-to-length ratio of the input transistor may be greater than 1.5.

As shown inFIG. 8, an embodiment of the pixel current conversion circuit includes:

an input transistor M1having a gate and a drain connected to the pixel current Ip, and a source connected to a ground terminal GND;

a first power-supply transistor M6having a gate and a drain connected to a high voltage input terminal; the high voltage input terminal is used to input a high voltage VDD;

a first output transistor M7having a gate connected to the gate of the input transistor M1, a drain connected to a source of the first power-supply transistor M6, and a source for outputting the first pixel current I1;

a second power-supply transistor M4having a gate and a drain connected to the high voltage VDD;

a second output transistor M5having a gate connected to the gate of the input transistor M1, a drain connected to a source of the second power-supply transistor M4, and a source for outputting the second pixel current I2;

a third power-supply transistor M2having a gate and a drain connected to the high voltage VDD;

a third output transistor M3having a gate connected to the gate of the input transistor M1, a drain connected to a source of the third power-supply transistor M2, and a source for outputting the third pixel current3.

In the embodiment of the pixel current conversion circuit shown inFIG. 8, all the transistors are N-type transistors, but not limited thereto.

In the embodiment shown inFIG. 8, I1is equal to Ip/2, I2is equal to Ip, I3is equal to 2Ip, the width-length ratio of M7is half of the width-length ratio of M1, the width-length ratio of M5is equal to that of M1, and the width-to-length ratio of M3is twice of M1.

The pixel current detection circuit according to the present disclosure will described below with reference to an embodiment.

An embodiment of the pixel current detection circuit according to the present disclosure is applied to a pixel circuit to detect a pixel current Ip in the pixel circuit. As shown inFIG. 9, the embodiment of the pixel current detection circuit according to the present disclosure including a pixel current conversion circuit I1and a current detection circuit;

the pixel current conversion circuit I1includes:

an input transistor M1having a gate and a drain connected to the pixel current Ip, and a source connected to a ground terminal GND;

a first power-supply transistor M6having a gate and a drain both connected to a high voltage input terminal; the high voltage input terminal is used to input a high voltage VDD;

a first output transistor M7having a gate connected to the gate of the input transistor M1, a drain connected to a source of the first power-supply transistor M6, and a source for outputting the first pixel current I1;

a second power-supply transistor M4having a gate and a drain connected to the high voltage VDD;

a second output transistor M5having a gate connected to the gate of the input transistor M1, a drain connected to a source of the second power-supply transistor M4, and a source for outputting the second pixel current I2;

a third power-supply transistor M2having a gate and a drain connected to the high voltage VDD;

a third output transistor M3having a gate connected to the gate of the input transistor M1, a drain connected to a source of the third power-supply transistor M2, and a source for outputting the third pixel current I3;

The source of the first output transistor M7is the first pixel current output terminal of the pixel current conversion circuit I1, the source of the second output transistor M5is the second pixel current output terminal of the pixel current conversion circuit I1, the source of the third output transistor current M3is the third pixel current output terminal of the pixel current conversion circuit I1;

The current detection circuit includes the first conversion sub-circuit21, the second conversion sub-circuit22, the third conversion sub-circuit23, and a detection sub-circuit;

The detection sub-circuit includes an analog-to-digital converter ADC, a comparator (not shown inFIG. 9) and a pixel current acquisition circuit (not shown inFIG. 9);

the first conversion sub-circuit21includes a first differential operational amplifier Amp1, a first storage capacitor C1, a second storage capacitor C2, a first switch element SW1, a second switch element SW2, and a third switch element SW3; the detector sub-circuit further includes a first initialization circuit (not shown inFIG. 9);

an inverting input terminal of the first differential operational amplifier Amp1is connected to a source of the first output transistor M7, and a non-inverting input terminal of the first differential operational amplifier Amp1receives a reference voltage Vref;

the first switch element SW1and the first storage capacitor C1are connected in parallel between the inverting input terminal of the first differential operational amplifier Amp1and the output terminal of the first differential operational amplifier Amp1;

the output terminal of the first differential operational amplifier Amp1is connected to a first terminal of the second switch element SW2, and a second terminal of the second switch element SW2is connected to a first terminal of the third switch element SW3, and a second terminal of the third switch element SW3is connected to an input terminal of the analog-to-digital converter ADC;

a first terminal of the second storage capacitor C2is connected to the second terminal of the second switch element SW2, and a second terminal of the second storage capacitor C2is connected to a ground terminal GND;

the first initialization circuit (not shown inFIG. 9) is configured to provide the reference voltage Vref to the output terminal of the first differential operational amplifier Amp1in an initial stage;

the second conversion sub-circuit22includes a second differential operational amplifier Amp2, a third storage capacitor C3, a fourth storage capacitor C4, a fourth switch element SW4, a fifth switch element SW5, and a sixth switch element SW6; the detector sub-circuit further includes a second initialization circuit (not shown inFIG. 9);

an inverting input terminal of the second differential operational amplifier Amp2is connected to a source of the second output transistor M5, and a non-inverting input terminal of the second differential operational amplifier Amp2receives the reference voltage Vref;

the fourth switch element SW4and the third storage capacitor C3connected in parallel with each other are connected between the inverting input terminal of the second differential operational amplifier Amp2and an output terminal of the second differential operational amplifier Amp2;

the output terminal of the second differential operational amplifier Amp2is connected to a first terminal of the fifth switch element SW5, and a second terminal of the fifth switch element SW5is connected to a first terminal of the sixth switch element SW6, and a second terminal of the sixth switch element SW6is connected to the input terminal of the analog-to-digital converter ADC;

a first terminal of the fourth storage capacitor C4is connected to the second terminal of the fifth switch element SW5, and a second terminal of the fourth storage capacitor C4is connected to the ground terminal GND;

the second initialization circuit (not shown inFIG. 9) is configured to provide the reference voltage Vref to the output terminal of the second differential operational amplifier Amp2in the initial stage;

the third conversion sub-circuit includes a third differential operational amplifier Amp3, a fifth storage capacitor C5, a sixth storage capacitor C6, a seventh switch element SW7, an eighth switch element SW8, and a ninth switch element SW9; the detection sub-circuit further includes a third initialization circuit (not shown inFIG. 9);

an inverting input terminal of the third differential operational amplifier Amp3is connected to the source of the third output transistor M3, and a non-inverting input terminal of the third differential operational amplifier Amp3receives the reference voltage Vref;

the seventh switch element SW7and the fifth storage capacitor C5are connected in parallel between the inverting input terminal of the third differential operational amplifier Amp3and an output terminal of the third differential operational amplifier Amp3;

the output terminal of the third differential operational amplifier Amp3is connected to a first terminal of the eighth switch element SW8, a second terminal of the eighth switch element SW8is connected to a first terminal of the ninth switch element SW9, and a second terminal of the ninth switch element SW9is connected to the input terminal of the analog-to-digital converter ADC;

a first terminal of the sixth storage capacitor C6is connected to the second terminal of the eighth switch element SW8, and a second terminal of the sixth storage capacitor C6is connected to the ground terminal GND;

the third initialization circuit (not shown inFIG. 9) is configured to provide the reference voltage Vref to the output terminal of the third differential operational amplifier Amp3in the initial stage;

In the embodiment shown inFIG. 9, I1is equal to Ip/2, I2is equal to Ip, I3is equal to 2Ip, the width-length ratio of M7is half of the width-length ratio of M1, the width-length ratio of M5is equal to that of M1, and the width-to-length ratio of M3is twice of M1.

In the embodiment shown inFIG. 9, the reference voltage Vref is a ground voltage, that is, the non-inverting input terminal of Amp1, the non-inverting input terminal of Amp2, and the non-inverting input terminal of Amp3are all grounded. According to the virtual-short characteristic of the operational amplifier (i.e., it is equivalent to a short circuit between the non-inverting input terminal of the operational amplifier and the inverting input terminal of the operational amplifier, and the voltage at the non-inverting input terminal of the operational amplifier is equal to the voltage at the inverting input terminal of the operational amplifier), the source of M3, the source of M5and the source of M7are all grounded. Since the source of M1is connected to the ground terminal GND, and the gates of M1, M3, M5, and M7are connected to each other, a current mirror is formed by M1, M3, M5, and M7. It should be noted that the sources of M1, M3, M5, and M7may also be not grounded, as long as their potentials are equal.

In the embodiment shown inFIG. 9, M1, M3, M5, and M7form a current mirror. The ratio of I3flowing through M3to Ip flowing through M1is the ratio of the width-length ratio of M3to the width-length ratio of M1. The ratio of I2flowing through M5to Ip flowing through M1is the ratio of the width-length ratio of M5to the width-length ratio of M1. The ratio of I1flowing through M7to Ip flowing through M1is the ratio of the width-length ratio of M7to the width-length ratio of M1.

InFIG. 9, the point A1is a node connected with the inverting input terminal of Amp1, the point B1is a node connected with the output terminal of Amp1, the point A2is a node connected with the inverting input terminal of Amp2, the point B2is a node connected with the output terminal of Amp2, the point A3is a node connected with the inverting input terminal of Amp3, and the point B3is a node connected with the output terminal of Amp3.

Moreover, in the embodiment shown inFIG. 9, Ip is taken from an external compensation line SL, and the gate and drain of the input transistor M1are both connected to the external compensation line SL;

The pixel circuit Pix, to which the pixel current detection circuit according to the present disclosure shown inFIG. 9is applied, includes a data writing transistor T1, a display storage capacitor Cst, a driving transistor T3, and a compensation output transistor T2. A gate of T1is connected to a first scanning line G1, a gate of T2is connected to a second scanning line G2, a drain of T1is connected to a data line DATA, a source of T1is connected to a gate of T3, a first terminal of Cst is connected to the gate of T3, a second terminal of Cst is connected to a source of T3, a drain of T3receives a positive power supply voltage ELVDD, the source of T3is connected to a anode of an organic light emitting diode OLED, a cathode of OLED receives a negative power supply voltage ELVSS, a source of T2is connected to the anode of OLED, and a drain of T2is connected to the external compensation line SL.

In the embodiment shown inFIG. 9, all the transistors are N-type transistors, but not limited thereto.

FIG. 10is an operation timing diagram of the pixel current detection circuit shown inFIG. 9.

InFIG. 10, the reference sign S1represents a first control signal for controlling the first switch element SW to be turned on or off, the reference sign S2represents a second control signal to control the second switch element SW2to be turned on or off, and the reference sign S3represents a third control signal for controlling the third switch element SW3to be turned on or off; the reference sign S4represents a fourth control signal for controlling the fourth switch element SW4to be turned on or off, the reference sign S5represents a fifth control signal for controlling the fifth switch element SW5to be turned on or off, the reference sign S6represents a sixth control signal for controlling the sixth switch element SW6to be turned on or off; the reference sign S7represents a seventh control signal for controlling the seventh switch element SW7to be turned on or off, the reference sign S8represents an eighth control signal for controlling the eighth switch element SW8to be turned on or off, and the reference sign S9represents a ninth control signal for controlling the ninth switch element SW9to be turned on or off. In the embodiment shown inFIG. 9, when S is at a high level, SW1is turned on, and when S1is at a low level, SW1is turned off; when S2is at a high level, SW2is turned on, and when S2is at a low level, SW2is turned off; when S3is at a high level, SW3is turned on, and when S3is at a low level, SW3is turned off; when S4is at a high level, SW4is turned on, and when S4is at a low level, SW4is turned off; when S5is at a high level, SW5is turned on, and when S5is at a low level, SW5is turned off; when S6is at a high level, SW6is turned on, and when S6is at a low level, SW6is turned off; when S7is at a high level, SW7is turned on, and when S7is at a low level, SW7is turned off; when S8is at a high level, SW8is turned on, and when S8is at a low level, SW8is turned off; when S9is at a high level, SW9is turned on, and when S9is at a low level, SW9is turned off.

As shown inFIG. 10, when the embodiment of the pixel current detection circuit according to the present disclosure shown inFIG. 9is in operation, a detection time TD includes an initial stage Tinit, an integration stage Tsen, and a sampling stage Tsam arranged in sequence;

In the initial stage Tinit, both G1and G2output a high level, both T1and T2are turned on, a reset potential (the reset potential can be zero potential, but not limited to this) is written to DATA and SL, then DATA is controlled to output a data voltage Vdata, and the reference voltage Vref is written to SL. At this time, the first initialization circuit (not shown inFIG. 9) provides the reference voltage Vref to the output terminal of Amp1, the second initialization circuit (not shown inFIG. 9)) provide Vref to the output terminal of Amp2, and the third initialization circuit (not shown inFIG. 9) provides Vref to the output terminal of Amp3; S, S2, S4, S5, S7, and S8are at a high level, S3, S6, and S9are at a low level, SW1, SW4, SW7, SW2, SW5, and SW8are turned on, and SW3, SW6, and SW9are turned off. At this time, the inverting input terminal of Amp1is connected to the output terminal of Amp1, and Amp1operates as a circuitry-gain buffer; the inverting input terminal of Amp2is connected to the output terminal of Amp2, and Amp2operates as a circuitry-gain buffer; the inverting input terminal of Amp3is connected to the output terminal of Amp3, and Amp3operates as a circuitry-gain buffer;

In the integration stage Tsen, S, S4, and S7are at a low level, S2, S5, and S8are at a high level, S3, S6, and S9are at a low level, SW1, SW4, and SW7are turned off, and SW2, SW5, and SW8are kept on, SW3, SW6, and SW9are turned off, G1and G2output high levels, and T1and T2are turned on. The pixel current Ip (at this time, Vdata is written to DATA and Vref is written to SL, so the gate-source voltage of T3is equal to (Vdata-Vref). Since Vdata and Vref are constant within a detection time TD, Ip is constant during the detection time TD) is written to the drain of M1, and the current mirror including M1, M3, M5, and M7works. The source of M7outputs Ip/2 to the inverting input terminal of Amp1, the source of M5outputs Ip to the inverting input terminal of Amp2, and the source of M3outputs 2Ip to the inverting input terminal of Amp3. The inverting input terminal of Amp1is connected to the output terminal of Amp1via C1. Amp1operates as a current integrator and integrates Ip/2. Because a duration ΔT of the integration stage Tsen is constant (ΔT is also the integration time), the amount of accumulated current is constant. The potential at the point A1is kept at Vref due to the virtual-short characteristic of Amp1, so the potential at the point B1is increased due to the increasing potential difference between the two terminals of C1, and the resulted voltage at B1is the first detection voltage VD1. Furthermore, since SW2is turned on, the potential at the first terminal of C2is VD1. The inverting input terminal of Amp2is connected to the output terminal of Amp2via C2. Amp2operates as a current integrator and integrates Ip. Because the duration ΔT of the integration stage Tsen is constant (ΔT is also the integration time), the amount of accumulated current is constant. The potential at the point A2is kept at Vref due to the virtual-short characteristic of Amp2, so the potential at the point B2is increased due to the increasing potential difference between the two terminals of C2, and the resulted voltage at B2is the second detection voltage VD2. Furthermore, since SW5is turned on, the potential at the first terminal of C4is VD2. The inverting input terminal of Amp3is connected to the output terminal of Amp3via C3. Amp3operates as a current integrator and integrates 2Ip. Because the duration ΔT of the integration stage Tsen is constant (ΔT is also the integration time), the amount of accumulated current is constant. The potential at the point A3is kept at Vref due to the virtual-short characteristic of Amp1, so the potential at the point B3is increased due to the increasing potential difference between the two terminals of C3, and the resulted voltage at B3is the third detection voltage VD3. Furthermore, since SW8is turned on, the potential at the first terminal of C6is VD3;

in the first sampling period Ts1included in Tsam, SW3is turned on, SW6and SW9are turned off, VD1stored in C2is provided to the ADC via the SW3that is turned on, and the ADC converts VD1to the corresponding first digital voltage Vdig1;

in the second sampling period Ts2included in Tsam, SW6is turned on, SW3and SW9are turned off, VD2stored in C4is provided to the ADC via the SW5that is turned on, and the ADC converts VD2to the corresponding second digital voltage Vdig2;

in the third sampling period Ts3included in Tsam, SW9is turned on, SW3and SW6are turned off, VD3stored in C6is provided to the ADC via the SW8that is turned on, and the ADC converts VD3to the corresponding third digital voltage Vdig3;

The comparator (not shown inFIG. 9) determines whether Vdig2is too large or too small. When the comparator determines that Vdig2is too large, it transfers Vdig1to the pixel current acquisition circuit (not shown inFIG. 9), and the pixel current acquisition circuit calculates the pixel current according to Vdig1. When the comparator determines that Vdig2is too small, it transfers Vdig3to the pixel current acquisition circuit (not shown inFIG. 9), and the pixel current acquisition circuit calculates the pixel current according to Vdig3. When the comparator determines that the second detection voltage is within the detection range of the ADC according to Vdig2, it transfers the Vdig2to the pixel current acquisition circuit (not shown inFIG. 9), and the pixel current acquisition circuit calculates the pixel current according to Vdig2. After the pixel current is calculated, a compensation to the threshold voltage and mobility of the driving transistor T3can be performed according to the pixel current.

In practice, the comparator and the pixel current acquisition circuit may be provided in a timing controller.

When the embodiment of the pixel current detection circuit according to the present disclosure shown inFIG. 9is in operation,

the pixel current obtained according to VD1is equal to 2×C1×(Vref−VD1)/ΔT;ΔT;

the pixel current obtained according to VD2is equal to C1×(Vref−VD2)/ΔT;

the pixel current obtained according to VD3is equal to C1×(Vref−VD3)/2ΔT;

When the embodiment of the pixel current detection circuit according to the present disclosure shown inFIG. 9is in operation, if VD2exceeds the detection range of the ADC (that is, when VD2is higher than the maximum detection voltage of the ADC), Vdig1corresponding to VD1is read out, which can solve the problem that Ip is too large so that the data read by the ADC exceeds the detection range of the ADC; if VD2is too small, Vdig3corresponding to VD3is read out, which can solve the problem that the ADC cannot read small data accurately.

In order to improve the detection accuracy and detection range of an OLED (organic light emitting diode) display panel, according to the embodiments of the present disclosure, firstly the pixel current Ip is converted into ½Ip, Ip, 2Ip by current mirror circuits, and these currents are then input into respective integrating circuits for current integration. The comparator may output a suitable digital voltage to the pixel current acquisition circuit according to the value of Vdig2output by the ADC, and the pixel current acquisition circuit may detect the pixel current according to the digital voltage.

An embodiment of the present disclosure further provides a pixel current detection method for the above pixel current detection circuit. The pixel current detection method includes:

a current conversion step of converting the pixel current by the pixel current conversion circuit to obtain a first pixel current, a second pixel current and a third pixel current; and

a current detection step of converting, by the current detection circuit, the first pixel current into a first detection voltage, the second pixel current into a second detection voltage, and the third pixel current into a third detection voltage, and determining the pixel current according to the first detection voltage, the second detection voltage and the third detection voltage.

The pixel current detection method according to the present disclosure uses the pixel current conversion circuit to convert the pixel current to obtain the first pixel current, the second pixel current and the third pixel current, the current detection circuit obtains the pixel current according to the first detection voltage obtained by converting the first pixel current, the second detection voltage obtained by converting the second pixel current, and the third detection voltage obtained by converting the third pixel current, so that the problem of inaccurate detection results due to the limited detection range of the current detection circuit can be avoided, and the pixel current can be detected accurately, thereby enabling better external compensation.

Optionally, the first pixel current is less than the pixel current to be detected, and the third pixel current is greater than the pixel current to be detected.

The pixel current detection method according to an embodiment of the present disclosure is applied to a pixel circuit, so as to detect the pixel current in the pixel circuit by using the above pixel current detection circuit. As shown inFIG. 11, the pixel current detection method includes:

a current conversion step Step1: converting the pixel current by the pixel current conversion circuit to obtain a first pixel current, a second pixel current and a third pixel current; the first pixel current is less than the pixel current, a ratio between the second pixel current to the pixel current is within a predetermined ratio range, and the third pixel current is greater than the pixel current;

a current detection step Step2: converting, by the current detection circuit, the first pixel current into a first detection voltage, the second pixel current into a second detection voltage, and the third pixel current into a third detection voltage, and determining, by the current detection circuit, the pixel current according to at least one of the first detection voltage, the second detection voltage and the third detection voltage.

The pixel current detection method according to the embodiment of the present disclosure uses the pixel current conversion circuit to convert the pixel current to obtain the first pixel current, the second pixel current and the third pixel current, the first pixel current is less than the pixel current, a ratio between the second pixel current to the pixel current is within a predetermined ratio range, and the third pixel current is greater than the pixel current, the current detection circuit obtains the pixel current according to at least one of the first detection voltage obtained by converting the first pixel current, the second detection voltage obtained by converting the second pixel current, and the third detection voltage obtained by converting the third pixel current, so that the problem of inaccurate detection results due to the limited detection range of the current detection circuit can be avoided, and the pixel current can be detected accurately, thereby enabling better external compensation.

Optionally, the current detection circuit may include a first conversion sub-circuit, a second conversion sub-circuit, a third conversion sub-circuit, and a detection sub-circuit; the current detection step may include:

receiving the first pixel current and converting the first pixel current into the first detection voltage correspondingly by the first conversion sub-circuit;

receiving the second pixel current and converting the second pixel current into the second detection voltage correspondingly by the second conversion sub-circuit;

receiving the third pixel current and converting the third pixel current into the third detection voltage correspondingly by the third conversion sub-circuit;

obtaining the pixel current according to at least one of the first, second and third detection voltages by the detection sub-circuit.

In practice, the detection sub-circuit includes an analog-to-digital converter, a comparator, and a pixel current acquisition circuit; the step of determining the pixel current according to at least one of the first, second and third detection voltages by the detection sub-circuit includes:

sampling the first detection voltage in a first sampling period included in a sampling stage and convert the first detection voltage into a first digital voltage by the analog-to-digital converter, sampling the second detection voltage in a second sampling period included in the sampling stage and convert the second detection voltage into a second digital voltage by the analog-to-digital converter, and sampling the third detection voltage in a third sampling period included in the sampling stage and convert the third detection voltage into a third digital voltage by the analog-to-digital converter;

comparing the second digital voltage with a predetermined maximum digital voltage and with a predetermined minimum digital voltage by the comparator; when the comparator determines that the second digital voltage is higher than the predetermined maximum digital voltage by comparing, the comparator transfer the first digital voltage to the pixel current acquisition circuit; when the comparator determines that the second digital voltage is lower than the predetermined minimum digital voltage, the comparator transfer the third digital voltage to the pixel current acquisition circuit; when the comparator determines that the second digital voltage is higher than or equal to the predetermined minimum digital voltage and lower than or equal to the predetermined maximum digital voltage, the comparator transfer the second digital voltage to the pixel current acquisition circuit;

calculating the pixel current according to an output result of the comparator by the pixel current acquisition circuit.

Optionally, the first conversion sub-circuit may include a first differential operational amplifier, a first storage capacitor, a second storage capacitor, a first switch, a second switch, and a third switch; the detection sub-circuit further includes a first initialization circuit; a detection time includes an initial stage, an integration stage and a sampling stage arranged in sequence; the sampling stage includes a first sampling period; the step of converting the first pixel current into the first detection voltage by the current detection circuit includes:

in the initial stage, turning on a connection between an inverting input terminal of the first differential operational amplifier and an output terminal of the first differential operational amplifier by the first switch, turning on a connection between the output terminal of the first differential operational amplifier and a first terminal of the second storage capacitor by the second switch; turning off a connection between the first terminal of the second storage capacitor and the analog-to-digital converter by the third switch; and providing a reference voltage to the inverting input terminal of the first differential operational amplifier and/or the output terminal of the first differential operational amplifier by the first initialization circuit;

in the integration stage, turning off the connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier by the first switch, turning on the connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor by the second switch, turning off the connection between the first terminal of the second storage capacitor and the analog-to-digital converter by the third switch, and charging the first storage capacitor with the first pixel current;

in the sampling stage, turning off the connection between the inverting input terminal of the first differential operational amplifier and the output terminal of the first differential operational amplifier by the first switch, and turning off the connection between the output terminal of the first differential operational amplifier and the first terminal of the second storage capacitor by the second switch; wherein

in the first sampling period, the third switch turns on the connection between the first terminal of the second storage capacitor and the analog-to-digital converter, the analog-to-digital converter samples a voltage at the first terminal of the second storage capacitor, which is the first detection voltage;

in a period included in the sampling stage except for the first sampling period, the third switch turns off the connection between the first terminal of the second storage capacitor and the analog-to-digital converter.

Optionally, the second conversion sub-circuit may include a second differential operational amplifier, a third storage capacitor, a fourth storage capacitor, a fourth switch, a fifth switch, and a sixth switch; the detection sub-circuit further includes a second initialization circuit; a detection time includes an initial stage, an integration stage and a sampling stage arranged in sequence; the sampling stage further includes a second sampling period;

the step of converting the second pixel current into the second detection voltage by the current detection circuit includes:

in the initial stage, turning on a connection between an inverting input terminal of the second differential operational amplifier and an output terminal of the second differential operational amplifier by the fourth switch, turning on a connection between the output terminal of the second differential operational amplifier and a first terminal of the fourth storage capacitor by the fifth switch; turning off a connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter by the sixth switch; and providing a reference voltage to the inverting input terminal of the second differential operational amplifier and/or the output terminal of the second differential operational amplifier by the second initialization circuit;

in the integration stage, turning off the connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier by the fourth switch, turning on the connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor by the fifth switch, turning off the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter by the sixth switch, and charging the third storage capacitor with the second pixel current;

in the sampling stage, turning off the connection between the inverting input terminal of the second differential operational amplifier and the output terminal of the second differential operational amplifier by the fourth switch, and turning off the connection between the output terminal of the second differential operational amplifier and the first terminal of the fourth storage capacitor by the fifth switch; wherein

in the second sampling period, the sixth switch turns on the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter, the analog-to-digital converter samples a voltage at the first terminal of the fourth storage capacitor, which is the second detection voltage;

in a period included in the sampling stage except for the second sampling period, the sixth switch turns off the connection between the first terminal of the fourth storage capacitor and the analog-to-digital converter.

Optionally, the third conversion sub-circuit may include a third differential operational amplifier, a fifth storage capacitor, a sixth storage capacitor, a seventh switch, an eighth switch, and a ninth switch; the detection sub-circuit further includes a third initialization circuit; a detection time includes an initial stage, an integration stage and a sampling stage arranged in sequence; the sampling stage further includes a third sampling period;

the step of converting the third pixel current into the third detection voltage by the current detection circuit comprises:

in the initial stage, turning on a connection between an inverting input terminal of the third differential operational amplifier and an output terminal of the third differential operational amplifier by the seventh switch, turning on a connection between the output terminal of the third differential operational amplifier and a first terminal of the sixth storage capacitor by the eighth switch; turning off a connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter by the ninth switch; and providing a reference voltage to the inverting input terminal of the third differential operational amplifier and/or the output terminal of the third differential operational amplifier by the third initialization circuit;

in the integration stage, turning off the connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier by the seventh switch, turning on the connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor by the eighth switch, turning off the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter by the ninth switch, and charging the fifth storage capacitor with the third pixel current;

in the sampling stage, turning off the connection between the inverting input terminal of the third differential operational amplifier and the output terminal of the third differential operational amplifier by the seventh switch, and turning off the connection between the output terminal of the third differential operational amplifier and the first terminal of the sixth storage capacitor by the eighth switch; wherein

in the third sampling period, the ninth switch turns on the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter, the analog-to-digital converter samples a voltage at the first terminal of the sixth storage capacitor, which is the third detection voltage;

in a period included in the sampling stage except for the third sampling period, the ninth switch turns off the connection between the first terminal of the sixth storage capacitor and the analog-to-digital converter.

A display device according to an embodiment of the present disclosure includes the above pixel current detection circuit; the display device further includes a pixel circuit;

the pixel current detection circuit is configured to detect a pixel current in the pixel circuit.

Optionally, as shown inFIG. 12, the pixel circuit may include a data writing circuit81, an energy storage circuit82, a driving circuit83, a light emitting element EL, and a current output control circuit84;

a control terminal of the data writing circuit81is connected to a first scanning line G1, a first terminal of the data writing circuit81is connected to a data line DATA, a second terminal of the data writing circuit81is connected to a control terminal of the driving circuit83, and the data writing circuit81is configured to turn on or turn off a connection between the data line DATA and the control terminal of the driving circuit83under control of the first scanning line G1;

the energy storage circuit82is connected to the control terminal of the driving circuit83to control a potential of the control terminal of the driving circuit83;

a first terminal of the driving circuit83is connected to a power supply voltage terminal, a second terminal of the driving circuit83is connected to the light emitting element EL, and the driving circuit83is configured to drive the light emitting element EL to emit light under control of the control terminal thereof, the power supply voltage terminal is used to output a positive power supply voltage ELVDD;

a control terminal of the current output control circuit84is connected to a second scanning line G2, a first terminal of the current output control circuit84is connected to the second terminal of the driving circuit83, a second terminal of the current output control circuit84is connected to an external compensation line SL;

the pixel current conversion circuit (not shown inFIG. 12) in the pixel current detection circuit120is connected to the external compensation line SL, and configured to detect the pixel current output from the external compensation line SL.

Optionally, the light emitting element EL may be an organic light emitting diode OLED. The anode of the OLED is connected to the second terminal of the driving circuit83. The cathode of the OLED may receive a negative power supply voltage. The energy storage circuit82may include a display storage capacitor. The data writing circuit may include a data writing transistor, the driving circuit83may include a driving transistor, and the current output control circuit may include a current output control transistor.

The display device provided in the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

The above are the preferred embodiments of the present disclosure. It should be noted that, for those of ordinary skill in the art, without departing from the principles described in the present disclosure, many improvements and retouches can be made, and should also be regarded as the scope of protection of this disclosure.