Control method for a memory device

A control method for a memory device uses an inverting data to label that a data stored in a memory block is in an inverting state or a non-inverting state. According to the inverting data, the number of bits whose data states is changed is lower than a half of total bits in the memory block in writing operation. Therefore, an energy consumption of the memory device can reduce. The control method of the present invention also can utilize the inverting data to label a memory block with a defective bit and to select a spare block to repair the memory block with a defective bit.

This application claims priority of Application No. 109132028 filed in Taiwan on 17 Sep. 2020 under 35 U.S.C. § 119; the entire contents of all of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a control method for a memory device, particularly to a control method which can save power, repair defective bits and prolong a lifetime of a memory device.

Description of the Prior Art

In conventional random access memories, such as the magnetoresistive random access memory (MRAM), the resistive random access memory (RRAM), the ferroelectric random access memory (FRAM), a writing operation requires large current to change data states of bits, wherein the data states can be changed from “0” to “1” or from “1” to “0”. Therefore, the more the bits whose states are changed, the more the energy that is consumed in writing operations. Besides, if the states of data are varied too frequently, the durability and reliability of bits will be decreased, and the service life of RANI will be shortened.

In the conventional technology, defective bits of RANI are repaired in the manufacture process. When defective bits occur during the RAM use, the defective bits will be repaired with an error-correcting code (ECC). However, the ECC technology requires support from other components, such the mainboard or CPU. The conventional RAM is unlikely to repair defective bits by itself.

SUMMARY OF THE INVENTION

One objective of the present invention is to provide a control method for a memory device, which can save power, repair defective bits and prolong a lifetime of a memory device.

In one embodiment, the control method for a memory device comprises the steps of: providing an inverting data to label a first data of a memory block as in an inverting state or in a non-inverting state, wherein the inverting data has at least two bits; while a second data is written into the memory block, writing the second data or a third data into the memory block according to said first data and said inverting data, wherein the third data is obtained via inverting the second data; while a defective bit is detected in the memory block, changing at least one of the at least two bits to be in a data state of non-0 and non-1; selecting one from a plurality of spare blocks to replace the memory block, wherein the inverting data labels the selected spare block.

The present invention uses an inverting data to label the data stored in a memory block as in an inverting state or a non-inverting state, whereby while data is written into the memory block, the bits whose data state are changed are not more than a half number of the total bits in the memory block, wherefore energy consumption is decreased. Besides, the present invention uses the inverting data to label the memory block having a defective bit and select a spare block for repairing the memory block having a defective bit.

DETAILED DESCRIPTION OF THE INVENTION

Refer toFIG. 1andFIG. 2.FIG. 1schematically shows a memory device10according to the present invention.FIG. 2schematically shows an embodiment of the memory array12inFIG. 1. The memory device10comprises a memory array12, two inverting circuits14and16, and two buffers18and20. The memory array12may be divided into two parts; the first part includes a plurality of memory blocks N1-Nn and a plurality of label blocks K1-Kn; the second part includes a plurality of spare blocks R1-R5and a plurality of label blocks KR1-KR5. Each memory block has in (a first number) bits122, wherein the first number in is a positive integer. Thus, each first data stored in each memory block has in bits. Each spare block has in bits124. Each label block has 2 bits126. The label blocks K1-Kn and the label blocks KR1-KRn are used to store inverting data WIB. The inverting data WIB stored in the label blocks K1-Kn are used to label an inverting state or a non-inverting state of the memory blocks N1-Nn. The inverting data WIB stored in the label blocks KR1-KR5are used to label an inverting state or a non-inverting state of the spare blocks R1-R5. In the embodiment shown inFIG. 2, the memory blocks N1-Nn, the label blocks K1-Kn, the spare blocks R1-R5and the label blocks KR1-KR5are all in the same memory array12. In other embodiments, the memory blocks N1-Nn, the label blocks K1-Kn, the spare blocks R1-R5and the label blocks KR1-KR5may be respectively disposed in different memory arrays.

FIG. 3shows a flowchart of the reading and writing operations of the memory device10according to the present invention. In a step S10, while the memory device10receives a read/write instruction, a first data which is read from one of the memory blocks N1-Nn will be stored into two buffers18and20. Herein, the operation of reading a first data from the memory block N1is used as an exemplification. In a step S12, the memory device10determines whether to perform a writing operation. In a step S14, while the memory device10determines to perform a reading operation, the inverting circuit14detects the inverting data WIB in the label block K1to determine the first data is in an inverting state or a non-inverting state. In this embodiment, while the inverting data WIB is “00” or “11”, it indicates that the first data is in the non-inverting state. While the inverting data WIB is “01” or “10”, it indicates that the first data is in the inverting state. The present invention is not limited to this, for example, the first data is in the inverting state while the inverse data WIB is “00” or “11”, and the first data is a non-inverting state while the inverting data WIB is “01” or “10”. In a step S16, while the inverting circuit14determines that the first data is in the non-inverting state, the inverting circuit14directly uses the first data in the buffer18as the read data DR and outputs the read data DR to an external circuit outside the memory device10. If the inverting circuit14determines that the first data is in the inverting state in the step S14, the process proceeds to a step S18. In the step S18, the inverting circuit14inverts the first data to generate a fourth data as the read data DR and outputs the read data DR to an external circuit outside the memory device10. For example, if the first data is “1001”, the fourth data is “0110”.

If the memory device10determines to perform a writing operation in the step S12, the memory device10will execute a step S20. In the step S20, the inverting circuit16detects the inverting data WIB of the label block K1to determine the first data is in an inverting state or a non-inverting state. If the first data is in a non-inverting state, the inverting circuit16stores a second data, which is to be written, in the buffer20. Next, the process proceeds to a step S22. In the step S22, the memory device10compares the first data in the buffer18with the second data in the buffer20. The comparation process includes finding out the bits at the same positions but in different states in the first data and the second data, and counts the number of these bits to generate a second number WB. Next, the process proceeds to a step S24. In the step S24, determine whether the second number WB is greater than a half of the first number in. If the second number WB is smaller than m/2, the process proceeds to a step S26. In the step S26, the memory device10directly writes the second data into the memory block N1, and maintains the inverting data WIB, which is corresponding to the memory block N1, in the non-inverting state. If the second number WB is greater than m/2, the process proceeds to a step S28. In the step S28, the inverting circuit16inverts the second data to generate a third data. Next, the process proceeds to a step S30. In the step S30, the memory device10writes the third data into the memory block N1, and the inverting data WIB, which is corresponding to the memory block N1, will be labeled as in inverting state.

Herein, a practical embodiment is offered to explain the steps S22-S30. Suppose that the first data is “10010001”. As the first data has 8 bits, the first number in is 8. Suppose that the second data in the step S22is “10010010”. After the comparison process, it can know that only the data states of last two bits of the first data “10010001” and the second data “10010010” are different. Therefore, in the step S24, the memory device10determines that the second number WB is 2 and smaller than a half of the first number in. Next, the process proceeds to the step S26. In the step S26, the second data “10010010” is written into the memory block N1. As only the data states of the last two bits of the first data “10010001” and the second data “10010010” are different, only the data states of the last two bits122in the memory block N1need changing in writing. Suppose that the second data in the step S22is “10001110”. After the comparison process, it can know that the data states of the last five bits of the first data “10010001” and the second data “10001110” are different. Therefore, in the step S24, the memory device10determines that the second number WB is 5 and greater than a half of the first number in. If the second data is written into the memory block N1in such a case, there are five bits need to change data states. It will result in a high energy consumption. In order to decrease energy consumption, the memory device10executes the step S28to invert the second data and generate the third data “01110001”. Next, the process proceeds to the step S30. In the step S30, the memory device10writes the third data “01110001” into the memory block N1and simultaneously the inverting data WIB of label block K1will be labeled as in inverting state. As only the data states of the first three bits of the first data “10010001” and the third data “01110001” are different, only the first three bits122in the memory block N1need changing the data states in writing. Therefore, the present invention can achieve the target of saving power.

If the first data is in an inverting state in the step S20, the memory device10will execute a step S32. In the step S32, the inverting circuit16inverts the second data to generate the third data and stores the third data into the buffer20. Next, the process proceeds to a step S34. In the step S34, the memory device10compares the first data in the buffer18with the third data in the buffer20. After the comparison process, the memory device10can know that the bits whose positions are identical but whose data states are different in the first data and the third data. The memory device10counts the number of these bits to obtain the second number WB. Next, the process proceeds to a step S36. In the step S36, the memory device10determines whether the second number WB is greater than a half of the first number in. If the second number WB is smaller than m/2, the process proceeds to a step S38. In the step S38, the memory device10writes the third data into the memory block N1, and maintains the inverting data WIB, which is corresponding to the memory block N1, in the inverting state. If the second number WB is greater than m/2, the process proceeds to a step S40. In the step S40, the memory device10writes the second data into the memory block N1, and simultaneously changes the inverting data WIB to be in a non-inverting state.

Herein, practical embodiment is offered to explain the steps S32-S40. Suppose that the first data is “01101110”. As the first data has 8 bits, the first number in is 8. As the first data is labelled as in an inverting state in the step S32, the inverting circuit16inverts the second data “01110001” to be a third data “10001110” and stores the third data in the buffer20. The memory device10compares the first data “01101110” and the third data “10001110” so as to know that the data states of the first three bits are different. Thus, the memory device determines that the second number WB is 3 and smaller than a half of the first number in. Next, the process proceeds to the step S38. In the step S38, the memory device10writes the third data “10001110” into the memory block N1and maintains the inverting data WB of the label block K1unchanged. As only the data states of the first three bits are different in the first data “01101110” and the third data “10001110”, only the first three bits122of the memory block N1need changing in writing. In another embodiment, suppose that the second data is “01101001”, and a third data “10010110” is generated in the step S32. Next, in the step34and the step S36, the memory device10knows that the data states of the first five bits are different in the first data “01101110” and the third data “10010110” and determines that the second number WB is greater than a half of the first number in. In order to decrease energy consumption, the memory device10executes the step S40. In the step S40, the memory device10writes the second data into the memory block N1and changes the inverting data of the label block K1to be in the non-inverting state. As only the date states of the last three bits are different for the first data “01101110” in the memory block N1and the second data “01101001”, only the data states of the last three bits122of the memory block N1need changing in writing. Therefore, the present invention can achieve the target of saving power.

Herein, the label block K1inFIG. 2is used as an exemplification. The inverting data WIB of the label block K1has two bits, wherein “00” and “11” may be used to express a non-inverting state; “01” and “10” may be used to express an inverting state. If the data states of the bits126are changed too frequently, the durability and reliability of the bits126will be lowered, and a lifetime of the label block K1will be shortened. In order to decrease the frequency of changing the states of the bits126, the inverting data WIB may be changed in an order. For example, the inverting data WIB is changed in an order: “00” to “01”; “01” to “11”; “11” to “10”; “10” to “00”. In other words, the inverting data WIB is changed cyclically in a sequence: “00”, “01”, “11”, and “10”. Thus, only one bit126is changed each time in the label block K1, and the data state of the same bit126would not be changed twice successively. Then, the frequency of changing the states of the bits126is decreased, and the lifetime of the label block K1is increased. The present invention does not limit the number of the bits of the inverting data WIB. For example, the inverting data WIB may have three bits. In such a case, “000”, “011” and “110” may be used to express a non-inverting state; “001”, “111” and “100” may be used to express an inverting state. The inverting data WIB may be changed in a sequence: “000”, “001”, “011”, “111”, “110” and “100”. In another embodiment, “000”, “011” and “110” may be used to express an inverting state of the inverting data WIB; “001”, “111” and “100” may be used to express a non-inverting state of the inverting data WIB.

A third state X, which is non-0 and non-1, can be written into the bits126of the label blocks K1-K12inFIG. 2. Based on the feature, the memory device10of the present invention can instantly repair defective bits. While a bit122in the memory block N1becomes a defective bit because of overuse or other factors, at least one bit126of the label block K1can be changed to have a data state X to indicate that the memory block N1has a defective bit. The memory device10of the present invention can select one of the spare blocks R1-R5to replace the memory block N1according to the inverting data WIB.FIG. 4shows the relationship between the inverting data WIB and the spare blocks R1-R5. While the memory device10detects that the inverting data WIB of the memory block N1is “X0”, the memory device10will select the spare block R1to replace the memory block N1. While the memory device10detects that the inverting data WIB of the memory block N1is “X1”, the memory device10will select the spare block R2to replace the memory block N1. While the memory device10detects that the inverting data WIB of the memory block N1is “0X”, the memory device10will select the spare block R3to replace the memory block N1. While the memory device10detects that the inverting data WIB of the memory block N1is “1X”, the memory device10will select the spare block R4to replace the memory block N1. While the memory device10detects that the inverting data WIB of the memory block N1is “XX”, the memory device10will select the spare block R5to replace the memory block N1. The embodiment inFIG. 2uses five spare blocks R1-R5. However, the present invention is not limited by this embodiment. The present invention may increase or decrease the number of the spare blocks according to requirement. The number of the bits of the inverting data WIB may vary with the number of the spare blocks.

In the embodiment shown inFIG. 2, a plurality of bits122forms an n×m array. The arrangement direction of the spare blocks R1-R5can depend on the relationship of n and in to achieve a better repair efficiency. Refer toFIG. 5. While n>m (e.g. n=16 and m=8), the spare blocks R1-R5can be arranged along the Y direction to achieve a better repair efficiency, as shown by the solid lines. In details, while the n×m array ofFIG. 5has a defective bit, the spare blocks R1-R5arranged along the Y direction only need to use 8 bits124to replace the memory block having the defective bit. It means that 8 bits124are used to repair a defective bit in such a case. If the spare blocks R1-R5are arranged along the X direction (as shown by the dotted lines), 16 bits are used to replace the memory block having the defective bit. It means that 16 bits are used to repair a defective bit. Therefore, while n>m, arranging the spare blocks R1-R5along the Y direction will acquire a better repair efficiency. While n<m (e.g. n=8 and m=16), arranging the spare blocks R1-R5along the X direction will acquire a better repair efficiency, as shown inFIG. 6.

The embodiments have been described above to demonstrate the present invention to enable the persons skilled in the art to understand, make, and use the present invention. However, these embodiments are only to exemplify the present invention but not to limit the scope of the present invention. Any modification or variation according to the spirit, principle, and/or characteristic of the present invention is to be also included by the scope of the present invention, which is based on the claims stated below and the equivalents thereof.