Digital timing recovery in hard disk drive read channel for preamble reduction

A method of reading data from a rotating magnetic storage medium, having at least one read head, includes storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, determining a zero-phase start phase angle from a preamble of the digitized data samples, feeding forward the zero-phase start phase angle to an interpolator, selecting an interpolation filter based on the fed-forward zero-phase start phase angle, releasing the respective digitized data from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting, and interpolating samples of the digitized data released from the respective timing buffer.

FIELD OF USE

This disclosure relates to digital timing recovery for use in the read channel of a hard disk drive. More particularly, this disclosure relates to increasing the area available for user data on a hard disk drive by reducing the latency of digital timing recovery, thereby reducing the amount of disk area devoted to preamble data.

BACKGROUND

In magnetic recording, as one example, reading and writing are performed by one or more heads that move relative to the surface of a storage medium. Many magnetic disk drives, for example, include a plurality of individual disks, or “platters,” which may be two-sided—i.e., each platter can store data on each of its two sides. Therefore, such a disk drive would have at least two heads for each platter. Indeed, for each platter, there is normally at least one write head and at least one separate read head, so that such a disk drive normally has at least four heads per platter.

In a common configuration, all of the heads in a given disk drive are mounted on arms attached to a common actuator that controls the radial position of the heads (an angular, tangential or circumferential component of motion is provided by the rotation of the platters relative to the heads). This is true whether there is one or many platters, and one or multiple heads per platter.

When writing user data to a hard disk drive, a preamble followed by user data is written first. When reading the data, a clock has to be recovered from the data that is read, and the preamble must be long enough for clock recovery to occur while the preamble is being read. However, the longer the preamble, the more disk space is occupied by preamble data, leaving less space for user data.

SUMMARY

In accordance with implementations of the subject matter of this disclosure, a method of reading data from a rotating magnetic storage medium having at least one read head includes storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, determining a zero-phase start phase angle from a preamble of the digitized data samples, feeding forward the zero-phase start phase angle to an interpolator, selecting an interpolation filter based on the fed-forward zero-phase start phase angle, releasing the respective digitized data from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting, and interpolating samples of the digitized data released from the respective timing buffer.

A first implementation of such a method may further include, where analog signals from each read head of the at least one read head are digitized at a clock rate that is oversampled relative to a bit rate of the data, phase-rotating the digitized data prior to the determining, to account for the oversampled clock, where the releasing occurs after a duration sufficient for completion of the phase-rotating, the determining, the feeding forward and the selecting.

A second implementation of such a method may further include, when the at least one read head comprises more than one read head, delaying signals from at least one of the at least one read head to align the signals before the storing.

A third implementation of such a method may further include equalizing the interpolated samples, detecting data bits from the interpolated samples, detecting timing error between the interpolated samples and the data bits, and deriving a bit rate from the timing error, where selecting the interpolation filter is based also on the bit rate.

Where analog signals from each read head of the at least one read head are digitized at a clock rate that is oversampled relative to a bit rate of the data, a first aspect of that third implementation may further include, prior to equalization, storing the interpolated samples in a FIFO buffer based on the oversampled clock, and reading the interpolated samples from the FIFO buffer at the bit rate.

In a fourth implementation of such a method, determining a zero-phase start phase angle from the preamble of the digitized data may include performing a Discrete Fourier Transform operation on the preamble of the digitized data, deriving cosine values and sine values from the Discrete Fourier Transform operation, and performing a CORDIC operation on the cosine values and the sine values to derive the zero-phase start phase angle.

According to a first aspect of that fourth implementation, performing the CORDIC operation may include performing a number of CORDIC rotations determined by a desired precision.

According to a second aspect of that fourth implementation, deriving the cosine values and the sine values from the Discrete Fourier Transform operation may include applying cosine coefficients from the Discrete Fourier Transform to each of the digitized data samples and accumulating the cosine values, and applying sine coefficients from the Discrete Fourier Transform to each of the digitized data samples and accumulating the sine values.

In a first instance of that second aspect, accumulating the cosine values and accumulating the sine values vary according to a tone of the preamble.

A third aspect of that fourth implementation may further include converting the zero-phase start phase angle to a phase jump.

In a first instance of that third aspect, converting the zero-phase start phase angle to a phase jump may include looking up a phase jump value in a look-up table.

A second instance of that third aspect may further include correcting the phase jump to account for the oversampling.

In a first variation of that second instance, correcting the phase jump to account for the oversampling may include correcting an integer portion of the zero-phase start phase angle in an angle domain, and correcting a fractional portion of the zero-phase start phase angle in a phase domain.

In accordance with implementations of the subject matter of this disclosure, a storage device includes a rotating storage medium on which data is written, at least one read head, a respective timing buffer configured to store respective digitized data samples from each respective read head of the at least one read head, zero-phase start circuitry configured to determine a zero-phase start phase angle from a preamble of the digitized data samples, and interpolator circuitry, output of the zero-phase start circuitry being fed forward to the interpolator circuitry, the interpolator circuitry including an interpolation filter configured to be selected based on the fed-forward zero-phase start phase angle. The respective digitized data is released from the respective timing buffer after a duration sufficient for completion of operation of the zero-phase start circuitry and the interpolator circuitry, and the interpolator circuitry is configured to interpolate samples of the digitized data released from the respective timing buffer.

A first implementation of such a storage device may further include a respective analog-to-digital converter configured to digitize analog signals from a respective read head of the at least one read head, each respective analog-to-digital converter clocked by a clock that is oversampled relative to a bit rate of the data, and phase-rotation circuitry configured to phase-rotate the digitized data prior to input to the zero-phase start circuitry, to account for the oversampled clock, where the duration may further be sufficient to account for completion of the phase-rotating.

In a second implementation of such a storage device, the at least one read head may include more than one read head, and the storage device may further include delay circuitry configured to delay signals from at least one of the at least one read head to align the signals before storage in the respective timing buffers.

A third implementation of such a storage device may further include equalization circuitry configured to filter the interpolated samples, a data detector configured to detect data bits from the interpolated samples, error-detecting circuitry configured to detect timing error between the interpolated samples and the data bits, and a timing loop configured to derive a bit rate from the timing error, where the interpolator circuitry is configured to select an interpolation filter based on the bit rate.

A first aspect of that third implementation may further include a respective analog-to-digital converter configured to digitize analog signals from a respective read head of the at least one read head, each respective analog-to-digital converter clocked by a clock that is oversampled relative to a bit rate of the data, and a FIFO buffer configured to store the interpolated samples based on the oversampled clock, and to output the interpolated samples at the bit rate.

In a fourth implementation of such a storage device, the zero-phase start circuitry may include Discrete Fourier Transform circuitry configured to operate on the preamble of the digitized data, cosine accumulator circuitry configured to derive cosine values from output of the Discrete Fourier Transform circuitry, sine accumulator circuitry configured to derive sine values from output of the Discrete Fourier Transform circuitry, and CORDIC circuitry configured to operate on the cosine values and the sine values to derive the zero-phase start phase angle.

According to a first aspect of that fourth implementation, the CORDIC circuitry may be configured to perform a number of CORDIC rotations determined by a desired precision.

According to a second aspect of that fourth implementation, the cosine accumulator circuitry and the sine accumulator circuitry may vary according to a tone of the preamble.

A third aspect of that fourth implementation may further include circuitry configured to convert the zero-phase start phase angle to a phase jump.

In a first instance of that third aspect, the circuitry configured to convert the zero-phase start phase angle to a phase jump may include a look-up table.

A second instance of that third aspect may further include circuitry configured to correct the phase jump to account for the oversampling.

In a first variation of that second instance, the circuitry configured to correct the phase jump to account for the oversampling may be configured to correct an integer portion of the zero-phase start phase angle in an angle domain, and to correct a fractional portion of the zero-phase start phase angle in a phase domain.

In accordance with implementations of the subject matter of this disclosure a storage device includes rotating storage means on which data is written, at least one read head means, respective timing buffer means configured to store respective digitized data samples from each respective read head means of the at least one read head means, zero-phase start means configured to determine a zero-phase start phase angle from a preamble of the digitized data samples, and interpolator means, output of the zero-phase start circuitry means being fed forward to the interpolator means, the interpolator means including interpolation filter means configured to be selected based on the fed-forward zero-phase start phase angle. The respective digitized data is released from the respective timing buffer means after a duration sufficient for completion of operation of the zero-phase start means and the interpolator means, and the interpolator means is configured to interpolate samples of the digitized data released from the respective timing buffer means.

A first implementation of such a storage device may further include a respective analog-to-digital converter means configured to digitize analog signals from a respective read head means of the at least one read head means, each respective analog-to-digital converter means clocked by clock means that is oversampled relative to a bit rate of the data, and phase-rotation means configured to phase-rotate the digitized data prior to input to the zero-phase start means, to account for the oversampled clock, where the duration further be sufficient to account for completion of the phase-rotating.

In a second implementation of such a storage device, the at least one read head means may include more than one read head means, and the storage device may further include delay means configured to delay signals from at least one of the at least one read head means to align the signals before storage in the respective timing buffer means.

A third implementation of such a storage device may further include equalization means configured to filter the interpolated samples, data detector means configured to detect data bits from the interpolated samples, error-detecting means configured to detect timing error between the interpolated samples and the data bits, and timing loop means configured to derive a bit rate from the timing error, where the interpolator means is configured to select an interpolation filter based on the bit rate.

A first aspect of that third implementation may further include respective analog-to-digital converter means configured to digitize analog signals from a respective read head means of the at least one read head means, each respective analog-to-digital converter means clocked by a clock that is oversampled relative to a bit rate of the data, and FIFO buffer means configured to store the interpolated samples based on the oversampled clock, and to output the interpolated samples at the bit rate.

In a fourth implementation of such a storage device, the zero-phase start means may include Discrete Fourier Transform means configured to operate on the preamble of the digitized data, cosine accumulator means configured to derive cosine values from output of the Discrete Fourier Transform means, sine accumulator means configured to derive sine values from output of the Discrete Fourier Transform means, and CORDIC means configured to operate on the cosine values and the sine values to derive the zero-phase start phase angle.

According to a first aspect of that fourth implementation, the CORDIC means may be configured to perform a number of CORDIC rotations determined by a desired precision.

According to a second aspect of that fourth implementation, the cosine accumulator means and the sine accumulator means may vary according to a tone of the preamble.

A third aspect of that fourth implementation may further include means configured to convert the zero-phase start phase angle to a phase jump.

In a first instance of that third aspect, the means configured to convert the zero-phase start phase angle to a phase jump may include look-up table means.

A second instance of that third aspect may further include means configured to correct the phase jump to account for the oversampling.

In a first variation of that second instance, the means configured to correct the phase jump to account for the oversampling may be configured to correct an integer portion of the zero-phase start phase angle in an angle domain, and to correct a fractional portion of the zero-phase start phase angle in a phase domain.

DETAILED DESCRIPTION

FIGS.1and2show an example of a disk drive100with which the subject matter of the present disclosure may be used. In this particular example, disk drive100has three platters101,102,103, although any number of platters may be included in a disk drive with which the subject matter of the present disclosure may be used. As shown, each platter101,102,103has, on each of its upper and lower surfaces111,112, a coating110made from a material in which data can be stored, e.g., magnetically. The present disclosure also is relevant to a disk drive in which one or more platters includes coating110on only one of its surfaces, but such a disk drive would store less data in the same volume than a disk drive with two-sided platters. The platters101-103are mounted on a rotatable spindle104. Spindle motor105rotates spindle104to rotate platters101-103in the direction of arrow A (FIG.2). Although spindle motor105is shown connected directly to spindle104, in some cases spindle motor105may be located off-axis of spindle104and would be connected to spindle104through belts or gears (not shown).

Read/write head assembly120includes an actuator121that bears arms122-125, one of which is disposed adjacent to each surface111,112of a platter101,102,103that has a memory storage coating110. In this example, with heads on both surfaces of each of arms123,124, that amounts to four arms122-125, but in the single-sided platter example discussed above, there would be only three arms. In other examples, the number of arms would increase or decrease along with the number of platters.

Each arm122-125bears, at or near its end furthest from actuator121, and on both its upper and lower surfaces in the case of arms123,124, a plurality of read heads/sensors and write heads. In this case, two sensors131,132are shown, and may represent, respectively, read and write sensors, although it in some applications each arm123,124may bear more than one read head/sensor and more than one write head (not shown). In the configuration shown inFIGS.1and2, arms122-125are aligned along a radius of platters101-103, bringing heads131,132as close as they can get to spindle104. It should be noted thatFIGS.1and2are schematic only and not to scale. Normally, the spindle diameter would be larger relative to the disk diameter. Moreover, arms122-125normally cannot point directly at the center of the disk.

Each of read heads131,132is connected to a read channel301of a hard drive controller300(there is a corresponding write channel302) (FIG.3). Hard drive controller300also includes a processor310and memory311, as well as a connection312to a host processor (not shown).

As noted above, when writing user data to a hard disk drive, a preamble followed by user data is written first. When reading the data, a clock has to be recovered from the data that is read, and the preamble must be long enough for clock recovery to occur while the preamble is being read. However, the longer the preamble, the more disk space is occupied by preamble data, leaving less space for user data. Therefore, if clock or timing recovery is too slow, a longer preamble is required, reducing the disk space available for user data and lowering the storage efficiency of the disk drive. It would be desirable to shorten the preamble to increase the disk space available for user data.

The signal from a disk drive read head originates as an analog signal, which is digitized for further processing. An analog-to-digital converter (ADC) for digitizing the data is necessarily clocked. In typical analog timing recovery techniques, information is fed back from the digital domain to an analog clock source—e.g., a phase-locked loop (PLL)—that clocks the ADC. The feedback loop typically introduces substantial latency based on, e.g., the latency of zero-phase start circuitry, which adjusts the sampling phase, as well as the latency of timing accumulator circuitry. If the disk drive uses two heads, as in two-dimensional magnetic recording (TDMR) implementations, additional latency is introduced by any buffering needed to account for the distance between read heads.

However, in accordance with implementations of the subject matter of this disclosure, a digital timing recovery technique is provided which eliminates the effects of latency of zero-phase start operations and associated timing accumulation operations. In implementations of this technique, the analog timing is completely separated from the digital timing. The ADC in the analog domain, which digitizes the read-head signals, is clocked by a free-running clock (which may be provided, e.g., by a PLL). There is no feedback to that clock from the digital domain. However, in order to assure that the ADC conversion is not undersampled, the analog clock is deliberately oversampled so that is it certain to be no slower than the target clock to be recovered in the digital domain. Any effects of the oversampling are removed later in the digital timing recovery processing.

Unlike analog timing recovery, where portions of the clock recovery processing must be completed during the time it takes to read the preamble signal from the storage medium, which necessitates lengthening the preamble to account for that clock recovery processing time, and thereby increase the storage capacity occupied by the preamble, in digital timing recovery, the signal read from the storage medium can simply be held in a buffer until those portions of the clock recovery processing are complete. Therefore, the preamble length is decoupled from the clock recovery processing time, and the preamble needs to be only as long as is necessary to support clock recovery processing as described below. While that does not reduce the time necessary for the processing (except for the differences between analog and digital processing), it reduces the amount of storage medium space needed for the preamble, improving storage medium efficiency.

The digitized data from the read head or heads is buffered while zero-phase start operations are performed to determine a starting phase and magnitude which are fed forward (instead of being fed back as in analog timing recovery) to interpolation operations to recover the clock. If two or more heads are used, a delay or delays are used to align the respective signals from the different heads before buffering. The aligned signals are then buffered and also processed through phase rotation to remove the effects of oversampling (as discussed above), because zero-phase start operation will not function correctly on the oversampled signals. Effectively, the phase rotation is equivalent to downsampling the signals back to their original sampling rate.

The zero-phase start operation begins with a Discrete Fourier Transform (DFT) operation on the preamble data, to derive sine and cosine coefficients, which are accumulated to provide inputs to a CORDIC operation that determines the ZPS phase angle, which is converted into a sampling time adjustment, as described below. The preamble may be a 2T, 3T or 4T tone, requiring different CORDIC resolution. The number of CORDIC iterations may be selected for the highest required resolution. For example, ten iterations may provide the required resolution for the 4T case, without imposing a significant burden on the 2T or 3T case, even though fewer iterations may be sufficient in those cases. Once the ZPS angle has been determined, it may be converted to a ZPS time jump (i.e., sampling time adjustment) using, e.g., a single look-up table whose values may be multiplied by 2, 3 or 4, respectively, for a 2T, 3T or 4T preamble. A further correction may be implied taking into account the oversampling factor. Further adjustments or corrections may be applied by the user—in either the oversampled domain or the downsampled domain or both—to account for, e.g., constant errors due to media defects.

Implementations of the subject matter of this disclosure may be better understood by reference toFIGS.4-20.

The nature of the problem to be solved may be appreciated fromFIG.4, which is a representation of a data packet400to be read from a hard disk drive. In addition to the actual user data payload401, data packet400includes a sync mark411to aid in locating packet400, and a preamble421from which zero-phase start circuitry may determine the starting phase. As seen inFIG.5, before the ZPS operation500, ADC samples501occur at seemingly random times during the clock cycle. ZPS operation500runs the initial bits of the preamble through a Discrete Fourier Transform (DFT) operation, to derive a phase adjustment after which ADC samples510are regularly distributed relative to the clock. The preamble needs to be only long enough to provide sufficient data for the DFT operation to derive the phase adjustment.

In a typical two-head read channel circuit600configured for analog timing recovery, shown inFIG.6, signal602from leading read head601is processed through analog front end AFE-1 (603) and then is digitized at analog-to-digital converter ADC-1 (604). Signal612from trailing read head611is processed through analog front end AFE-2 (613) and then is digitized at analog-to-digital converter ADC-2 (614). Digitized leading-head signal605is delayed at606so that digitized trailing-head signal617can catch up and the two signals607,617are aligned.

Aligned signals607,617are equalized in finite impulse response filters FIR-1 (608) and FIR-2 (618) and the equalized signals609,619are combined at620. The combined signal621passes through a Viterbi detector622to derive user data401. The output623of Viterbi detector622is compared at624to signal621to yield a timing error signal626detected by timing error detector625. Timing error signal626passes through timing loop627and is combined in timing accumulator628with the phase correction determined by ZPS circuitry629from signals607,617. The output of timing accumulator628is a phase correction signal630that adjusts the phase of phase-locked loop (PLL) circuit631which controls the sampling timing of ADC-1 (604) and ADC-2 (614).

In such a typical analog timing recovery architecture, preamble421must be long enough to allow operations in ZPS circuitry629and timing accumulator628, as well as the phase jump at PLL631, to occur, as well as to account for head-to-head distance delay606. As discussed above, lengthening the preamble421to account for these delays increases the amount of storage medium capacity devoted to the preamble, thereby reducing the amount of storage medium capacity available for user data401.

As shown inFIG.7, in accordance with implementations of the subject matter of this disclosure, feedback from ZPS circuitry629is eliminated from two-head read channel circuit700configured for digital timing recovery. Instead of being fed back, the output of ZPS circuitry629is fed forward, to interpolation circuitry710that adjusts the clock phase as described below. There is no feedback from the digital clock domain701to the analog clock domain702. Accordingly, to ensure that the analog sampling clock730, which is not adjusted based on feedback, that clocks ADCs604,614is not too slow, PLL711, which has a free-running reference clock input712, is overclocked by oversampling factor (OSF)713. The digital clock domain701is thus divided into an oversampled clock subdomain751upstream of interpolation circuitry710, and a bit-rate clock subdomain761downstream of interpolation circuitry710.

ZPS circuitry629will not operate correctly on an oversampled clock. Therefore, digital timing recovery circuitry700includes a rotation filter714, upstream of ZPS circuitry629, to filter out the effect of OSF713. Like analog timing recovery circuitry600, digital timing recovery circuitry700includes delay606in the path from leading read-head601to align the signals from leading read-head601to the signals from trailing read-head611. However, because digital timing recovery circuitry700is digital, the aligned delayed signals607,617need not be processed in real time. Instead, aligned delayed signals607,617can be buffered as long as necessary in separate buffers—DTR Buffer-1 (715) and DTR Buffer-2 (716)—for the signals from leading read-head601and the signals from trailing read-head611, respectively, until rotation operations in rotation filter714, and ZPS operations in ZPS circuitry629can be completed and the ZPS output717can be processed through timing accumulator718.

Interpolation circuitry710may include separate interpolation filters—Interpolation Filter-1 (719) and Interpolation Filter-2 (720)—for the signals from leading read-head601and the signals from trailing read-head611, respectively, as well as an interpolation bank721which may select from among predetermined sets of coefficients for interpolation filters719,720based on ZPS output717as processed through timing accumulator718.

Interpolated data signals722,723from interpolation filters719,720are clocked into first-in-first-out (FIFO) circuit724based on oversampled clock730but are clocked out of FIFO circuit724based on bit-rate clock725. FIFO output signals726,727are equalized in finite impulse response filters FIR-1 (608) and FIR-2 (618) and the equalized signals609,619are combined at620. The combined signal621passes through a Viterbi detector622to derive user data401. The output623of Viterbi detector622is compared at624to signal621to yield a timing error signal626detected by timing error detector625. Timing error signal626passes through timing loop627and is combined in timing accumulator718with the phase correction717determined by ZPS circuitry629, providing selection signal728for interpolation bank721to select from among predetermined sets of coefficients for interpolation filters719,720as discussed above.

Selection signal728may represent a phase shift of the oversampled signal relative to the desired phase, determined as follows:if (PHASE_SHIFT<0)NEXT_PHASE_SHIFT=PHASE_SHIFT+1.0elseNEXT_PHASE_SHIFT=PHASE_SHIFT−(OSF+phase_error)if (NEXT_PHASE_SHIFT<0)SKIP_CLOCK=1elseSKIP_CLOCK=0
That is, if the current phase shift (i.e., the phase of an interpolated sample relative to the desired phase) is negative, then the phase shift is increased by one clock period to make the phase shift positive. Otherwise, if the current phase shift is positive, the phase shift is decreased by the sum of the OSF and the measured phase error. And if the phase shift as so adjusted is still negative, then the phase skips forward one period.

Although digital timing recovery circuitry700is shown as accommodating two heads, digital timing recovery circuitry in accordance with implementations of this disclosure may work with only one head, or with three (or more) heads. In a one-head implementation, one of DTR Buffer-1 (715) and DTR Buffer-2 (716) and one of Interpolation Filter-1 (719) and Interpolation Filter-2 (720) may be omitted, or forced to zero, and rotation filter714and ZPS circuitry629may operate with a single input. Additional circuitry may be provided if there are additional heads.

As noted above, implementations of this disclosure are intended to minimize the length of the preamble to maximize the amount of space available for user data. Accordingly, using techniques in accordance with implementations of this disclosure may not speed up performance of the various calculations required (phase rotation, zero-phase start, etc.). Rather, because the digital data from the read head or heads may be held in the DTR buffer or buffers as long as is necessary for those calculations to be performed (which in some cases may actually increase the overall time required), the size of the preamble, and therefore the storage space for the preamble, is determined simply by the length of the Discrete Fourier Transform of the preamble tone, which may be a 2T tone, a 3T tone or a 4T tone.

Although many implementations of ZPS circuitry629are possible, one implementation of ZPS circuitry629in accordance with this disclosure may operate using CORDIC (COordinate Rotation DIgital Computer) techniques to determine the starting phase angle (and the starting magnitude, which may optionally be fed forward for automatic gain control). One implementation of a CORDIC arrangement800for determining the ZPS angle is shown inFIG.8. The output801of phase rotator714is multiplied at802and812by cosine coefficients and sine coefficients, respectively, from the Discrete Fourier Transform of the preamble tone. Details of the coefficients are discussed below. The products803,813are accumulated in respective cosine and sine accumulators804,814, yielding x and y coordinates representing the ZPS angle on a unit circle. CORDIC computation circuitry805uses well-known CORDIC techniques, in which the (x,y) vector is rotated toward the x-axis in angular steps of tan−1(2−n), where n=0, 1, 2, . . . . If any particular nth rotation overshoots the x-axis, the next rotation is in the opposite direction, until the vector is so close to the axis to be considered to have reached the x-axis, as discussed below. The signed sum of angular steps (where clockwise rotation is added and counterclockwise rotation is subtracted) is used as the ZPS phase angle, and may be converted to a phase jump in units of T.

The DFT coefficients to be applied at802,812depend on whether the preamble is a 2T preamble, a 3T preamble or a 4T preamble.

For a 2T preamble, the cosine values of cos (2πn/4) and the sine values of sin (2πn/4) represent four positions around a unit circle at 0°, 90°, 180° and 270°. For the cosine values, those four positions correspond to coefficients n=[1,0,−1,0]. For the sine values, those four positions correspond to coefficients n=[0,−1,0,1].

For a 3T preamble, the cosine values of cos (2πn/6) and the sine values of sin (2πn/6) represent six positions around a unit circle at 0°, 60°, 120°, 180°, 240° and 300°. For the cosine values, those six positions correspond to coefficients n=[1,1/2,−1/2,−1,−1/2,1/2]=[2,1,−1,−2,−1,1]×1/2. For the sine values, those six positions correspond to coefficients n=[0,−√{square root over (3)}/2,−√{square root over (3)}/2,0,√{square root over (3)}/2,√{square root over (3)}/2]=[0,−1,−1,0,1,1]×√{square root over (3)}/2.

For a 4T preamble, the cosine values of cos (2πn/8) and the sine values of sin (2πn/8) represent eight positions around a unit circle at 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315°. For the cosine values, those eight positions correspond to coefficients n=[1,1/√{square root over (2)},0,−1/√{square root over (2)},−1,−1/√{square root over (2)},0,1/√{square root over (2)}]= [1,0,0,0,−1,0,0,0,]+ [0,1,0,−1,0,−1,0,1]×1/√{square root over (2)}. For the sine values, those eight positions correspond to coefficients n=[1,−1/√{square root over (2)},−1,−1/√{square root over (2)},0,1/√{square root over (2)},1,1/√{square root over (2)}]= [0,0,−1,0,0,0,1,0]+ [0,−1,0,−1,0,1,0,1]×1/√{square root over (2)}.

FIG.9shows an implementation900of cosine and sine DFT coefficient generation for the 2T preamble case. For a 2T preamble, the cosine and sine accumulators804,814are identical. The DFT coefficients, operating at802on the phase rotator output801provides a cosine or sine value901that is divided at902by the ZPS length, ZPS: (i.e., the number of samples at the output of the rotation filter714which are accumulated by the DFT, which is the number of preamble samples over which ZPS is computed), which could be as high as 48 as shown in following table:

The quotient is added at903to the previously accumulated values from previous coefficients.

FIG.10shows implementations1000,1010of cosine DFT coefficient generator804and sine DFT coefficient generator814for the 3T preamble case. For a 3T preamble, the cosine and sine DFT coefficient computations are different. As seen, 3T cosine DFT coefficient generator1000is essentially the same as cosine DFT coefficient generator900. In sine DFT coefficient generator1010, the input901is multiplied at1001by √{square root over (3)}/2 to reflect the coefficient values described above, and then is divided at1002by the ZPS length ZPSL, as discussed above. The quotient is added at1003to the previously accumulated values from previous coefficients.

For a 4T preamble, as in the case of a 2T preamble, the cosine DFT coefficient generator804and the sine DFT coefficient generator814are the same, having the structure1100(FIG.11). As described above, the coefficients in the 4T case are the sum of a first term equal to 0, +1 or −1, and a second term equal the product of (a) 0, +1 or −1, and (b) 1/√{square root over (2)}. Therefore, DFT coefficient generator1100has first input1101and a second input1102. Input1102is multiplied at1103by 1/√{square root over (2)}, and that product is added at1104to first input1101. That sum is divided at1105by the ZPS length, ZPSL, as described above. The quotient is added at1106to the previously accumulated values from previous coefficients.

As discussed above, the accumulated coefficients may be used in CORDIC circuitry805to determine a phase angle that allows the interpolation circuitry710to adjust the phase of the read head signals607,617. As illustrated inFIG.12, CORDIC rotates input vector (x0, y0)1201, in each of i iterations by an angle θi=tan−1(2−(i−1)). The sign of yi−1determines the direction of rotation for ithiteration—if yi−1is positive (the rotated vector is above the x-axis), then the next rotation direction is clockwise and θiis positive; if yi−1is negative (the rotated vector is below the x-axis), then the next rotation direction is counterclockwise and θiis negative.

In the illustration inFIG.12, after the first iteration1202with rotation θ1=tan−1(2−0)=45° or π/4 radians (with θ1being positive and added in an accumulator), y1is positive (the rotated vector is above the x-axis), so the next angle1203—i.e., θ2=tan−1(2−1)=26.57°, or 0.4636 radians—will be positive (added in the accumulator), and the next rotation direction will be clockwise. After that second iteration, y2is negative (the rotated vector is now below the x-axis), so the next angle1204—i.e., θ3=tan−1(2−2)=14.04°, or 0.2445 radians—will be negative (subtracted in the accumulator), and the next rotation direction will be counterclockwise.

After sufficient number, n, of iterations, yn≈0. The magnitude xnof the rotated vector will remain approximately equal to √(x2+y2). The angle θ=tan−1(y0/x0) can be derived as

ZPS for a 2T, 3T, or 4T preamble requires a resolution of (π/2)/128, (π/3)/128, or (π/4)/128 radians, respectively. Therefore the best resolution is (π/4)/128=0.006135923 radians. Dividing by 2 to take the effects of rounding into account means a resolution of 0.006135923/2=0.00306796157 radians is required. At the nthiteration, CORDIC has a resolution of θn=tan−1(2−(n−1)). The smallest n for which θn<0.00306796157 radians is n=10 (because tan−1(2−9)=0.001953125, but tan−1(2−8)=0.00390625). Therefore, ten CORDIC iterations are required to achieve the desired resolution in such an implementation. The first rotation (i=1) of 45° is trivial, and so circuitry is needed only for nine iterations.

To rotate each vector

[xi-1yi-1]
by the angle θi=tan−1(2−(−1)) in the ithiteration, one can use a rotation matrix Ri:

Ri=11+tan2(θi)[1tan⁡(θi)-tan⁡(θi)1]
such that

The gain

Ki=11+tan2(θi)
may be ignored at each individual iteration and applied at the end as

K1n=∏1nKi=∏i=1n11+tan2(θi)
This allows the use of an alternative rotation matrix Rt:

This can be implemented by circuit1300ofFIG.13. It is determined at1301whether or not yi−1is negative, to yield control signal1302, which causes multiplexer1303to select, as di−1, +1 if yi−1>0, or −1 if yi−1<0. If yi−1=0, the CORDIC computation ends after the ithiteration. yi(1304) is determined by adding or subtracting (depending on the value of di−1) (xi−1)×(−2−(i−1)) to or from yi−1(1305) at1306, and xi(1307) is determined by adding or subtracting (depending on the value of di−1) (yi−1)×(2−(i−1)) to or from xi−1(1308) at1309.

In implementations of the subject matter of this disclosure, the CORDIC angle may be converted to a phase jump. As seen inFIG.14, for a 2T preamble, 360° (2π radians) of rotation around unit circle1400corresponds to 4T of phase. As seen by comparison ofFIGS.14and15, a forward (counterclockwise) rotation angle1401corresponds to a positive phase jump1501, while a backward (clockwise) rotation angle1402corresponds to a negative phase jump1502.

As seen inFIG.16, for a 3T preamble, 360° (2π radians) of rotation around unit circle1600corresponds to 6T of phase. As seen by comparison ofFIGS.16and17, a forward (counterclockwise) rotation angle1601corresponds to a positive phase jump1701, while a backward (clockwise) rotation angle1602corresponds to a negative phase jump1702.

As seen inFIG.18, for a 4T preamble, 360° (2π radians) of rotation around unit circle1800corresponds to 8T of phase. As seen by comparison ofFIGS.18and19, a forward (counterclockwise) rotation angle1801corresponds to a positive phase jump1901, while a backward (clockwise) rotation angle1802corresponds to a negative phase jump1902.

The required resolution of ZPS circuitry629is equal to T divided by the number of increments in interpolation circuitry710. For an interpolation filter with, e.g., 128 increments, the required resolution is T/128. For a 2T preamble, with four 90° steps around the unit circle1400, the required resolution would be 90/128 degrees= (π/2)/128 radians. For a 3T preamble, with six 60° steps around the unit circle1600, the required resolution would be 60/128 degrees=(π/3)/128 radians. For a 4T preamble, with eight 45° steps around the unit circle1800, the required resolution would be 45/128 degrees=(π/4)/128 radians. As set forth above, the smallest resolution required, accounting for rounding, would be ((π/4)/128)/2 radians=0.00306796157 radians.

The ZPS phase output can be stored in a look-up table in terms of fractions of T. For 128 increments, each increment of phase would be equal to π/p radians where pT is the preamble pattern; thus p∈{2, 3, 4}. Measured in radians, the ZPS angle would be:

Thus, the ZPS phase jump determination can be implemented as a look-up table with nine entries (as noted above, ten CORDIC steps are needed but the first step is trivial). Only one look-up table is needed for all of the 2T, 3T and 4T cases. The LUTivalue in the look-up table may be multiplied by p (i.e., by 2, 3 or 4) depending on the preamble tone value. One such look-up table (LUT)2000is shown inFIG.20. In LUT 2000, four extra bits of resolution are added so that the resolution is T/(128×4)=T/512.

The interpolation filter runs in the oversampled clock domain751. Therefore, once the ZPS angle is determined from the CORDIC operation (whether implemented as a look-up table or not), the ZPS angle must be adjusted by the oversampling factor OSF. If, for example:
θread=(1+OSF/128)·θwrite
then
ZPS_JUMP=(1+OSF/128)·fractional portion of ZPS_Angle
This correction is applied only to any fractional ZPS angle after subtracting all integer multiples of 360° from the ZPS angle.

One implementation2100for application of this correction is seen inFIG.21. After CORDIC circuitry805, the angle is converted to a phase jump in the time domain in ZPS Jump Computation circuitry2101. The integer part2111of the phase jump and the final fractional portion2121of the phase jump are combined at2102.

A method2200according to implementations of the subject matter of this disclosure is diagrammed inFIG.22. Method2200begins at2201, where, to read data from a rotating magnetic storage medium having at least one read head, where analog signals from each read head of the at least one read head are digitized by a respective analog-to-digital converter clocked by a clock that is oversampled relative to a bit rate of the data, respective digitized data samples from each respective read head of the at least one read head are stored in a respective timing buffer. At2202, a zero-phase start phase angle is determined from a preamble of the digitized data samples. At2203, the zero-phase start phase angle is fed forward to an interpolator. At2204, an interpolation filter is selected based on the fed-forward zero-phase start phase angle. At2205, the respective digitized data is released from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting. At2206, samples of the digitized data released from the respective timing buffer are interpolated. Method2200then ends.

Thus it is seen that a digital timing recovery technique for use in the read channel of a hard disk drive, to increasing the area available for user data on a hard disk drive by reducing the latency of digital timing recovery, thereby reducing the amount of disk area devoted to preamble data, has been provided.

As used herein and in the claims which follow, the construction “one of A and B” shall mean “A or B.”

It is noted that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.