Oscillator control apparatus

An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal, a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal, an adder which adds the count and the phase difference and outputs the added value as first phase information, a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information, and a filter for smoothing a difference between the phase control signal and the second phase information, to output the oscillator adjusting signal.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims benefit of priority from the Japanese Patent Application No. 2009-40668, filed on Feb. 24, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to an oscillator control apparatus.

An All Digital Phase Locked Loop (ADPLL) circuit, in which all of control signals in a phase locked loop (PLL) are digitized, has been recently used in a radio communication apparatus such as radio LAN equipment (see, for example, Japanese Patent Application Laid-open No. 2009-21954). In the ADPLL circuit, an analog circuit is replaced with a digital circuit, and therefore, the advance of processes can save a space and electric power.

The ADPLL circuit includes a digital loop filter, a digitally-controlled oscillator (DCO), a counter, and a time-to-digital converter (TDC). The counter is adapted to count outputs from the DCO and to output a count in response to a reference signal synchronized with the output from the DCO. The TDC takes a phase difference of 1 cycle or less of the output from the DCO in synchronism with the reference signal. A comparison result (i.e., a difference) between a value obtained by adding the count and the phase difference and a phase control signal is applied to the digital loop filter. An oscillation frequency of the DCO is controlled based on the output from the digital loop filter.

The output from the DCO is asynchronous to the reference signal. In other words, in the ADPLL circuit, outputs from the two circuits (i.e., the counter and the TDC) operative by an asynchronous clock are added. As a consequence, a value read by the counter is shifted, thereby raising a possibility of instable operation of the PLL.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided an oscillator control apparatus comprising:

a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal;

a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal;

a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal;

an adder which adds the count and the phase difference and outputs the added value as first phase information;

a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information; and

a filter for smoothing a difference between the phase control signal and the second phase information, to output the oscillator adjusting signal.

DESCRIPTION OF THE EMBODIMENTS

A description will be given below according to an embodiment of the present invention with reference to the attached drawings.

FIG. 1is a diagram schematically illustrating the configuration of an oscillator control apparatus according to an embodiment of the present invention. The oscillator control apparatus is provided with a digitally-controlled oscillator (hereinafter abbreviated as a DCO)100, a flip-flop110, a counter120, a Time-to-Digital Converter (TDC)130, an adder140, an accumulator150, a corrector160, a subtractor170, a digital filter180, and a multiplier190, thus constituting an ADPLL (All Digital Phase Locked Loop).

The DCO100is an oscillator whose oscillation frequency can be discretely controlled in response to an outside control signal (Oscillator Tuning Word (OTW)). The DCO100is achieved by controlling a plurality of varactor capacities in binary.

The flip-flop110holds a value of a reference signal Fref and outputs the signal in response to an output signal (i.e., an oscillation signal) CKV from the DCO100as a clock input. In other words, the flip-flop110outputs the reference signal Fref synchronized with the output signal CKV from the DCO100.

The counter120includes an accumulator121which receives the output signal CKV from the DCO100as a clock. The counter120receives the output signal from the flip-flop110as a clock, and then, outputs a value from the accumulator121as a count CNTV in synchronism with the clock. In other words, the counter120is a circuit to be operated in synchronism with the output signal CKV from the DCO100.

When, for example, the frequency of the output signal CKV from the DCO100is 2400 MHz and the frequency of the reference signal Fref is 40 MHz, the count CNTV output from the counter120is a value incremented by 60.

The TDC130is a time measuring device capable of digitally representing a phase difference d between the output signal CKV from the DCO100and the reference signal Fref with an accuracy minuter than 1 cycle of the output signal CKV from the DCO100. The TDC130is a circuit to be operated in synchronism with the reference signal Fref. In other word, the TDC130is operated by a clock asynchronous to the counter120.

FIG. 2exemplifies the configuration of the TDC130. The TDC130includes reverse circuits (i.e., inverters)200-1to200-n(n is an integer of 2 or more), flip-flops210-1to210-n, and an edge detector220. The reverse circuits200-1to200-nare connected in series to each other, for sequentially outputting the output signal CKV from the DCO100with a delay. A delay time in each of the reverse circuits200-1to200-nis, for example, several tens ps.

The flip-flops210-1to210-nhold output signals from the reverse circuits200-1to200-naccording to a rising-up or rising-down edge of the reference signal Fref, respectively, and then, output them.

The edge detector220detects the phase difference d between the output signal CKV from the DCO100and the reference signal Fref (with an accuracy minuter than 1 cycle of the signal CKV) out of the outputs from the flip-flops210-1to210-nat a transition timing of the reference signal Fref, and then, outputs it to the adder140as a digital value. Moreover, the edge detector outputs a length dCKV of 1 cycle of the output signal CKV from the DCO100to the corrector160.

The adder140adds the count CNTV output from the counter120and the phase difference d output from the TDC130, and then, outputs the added value (i.e., first phase information) to the corrector160.

The accumulator150integrates a value obtained by standardizing a frequency control signal Fc with the reference signal Fref, and then, outputs the integrated value to the corrector160and the subtractor170as a phase control signal Acc1.

The corrector160corrects the first phase information CNTV+d of the oscillation signal CKV from the DCO100based on the phase control signal Acc1, the output signal from the adder140(i.e., the first phase information CNTV+d), and the cycle dCKV of the output signal CKV from the DCO100, and then, outputs second phase information Acc2to the subtractor170.

The corrector160corrects the phase information in a normal state, that is, in a state in which the oscillation frequency in the DCO100is stable. A controller10controls whether or not the corrector160corrects the phase information. The controller10allows the corrector160to correct the first phase information after a lapse of a predetermined time (e.g., about 200 μs by Bluetooth®) after the oscillator control apparatus starts to be operated. Until the lapse of a predetermined time, the corrector160does not correct the first phase information CNTV+d but outputs it to the subtractor170.

Hereinafter, description will be given on a method for correcting the phase information by the corrector160. The corrector160determines whether or not a difference (dCKV-d) between the cycle dCKV of the output signal CKV from the DCO100and the phase difference d between the output signal CKV from the DCO100and the reference signal Fref (with the accuracy minuter than 1 cycle of the signal CKV) is smaller than a predetermined value A.

The difference dCKV-d being smaller than the predetermined value A signifies that the reference signal Fref rises up near the rising-up of the oscillation signal CKV, as illustrated inFIG. 3. In this case, the reference signal Fref rises up somewhat earlier than the oscillation signal CKV. An arbitrary value may be set as the predetermined value A from the outside. For example, when the delay time of each of the reverse circuits200-1to200-nin the TDC130is 1/10 of the cycle dCKV and the TDC130can detect the phase difference with an accuracy of 1/10 of 1 cycle of the oscillation signal CKV, A=0.2

When the difference dCKV-d is smaller than the predetermined value A, the corrector160determines whether or not a difference |Acc1−(CNTV+d)| between the phase control signal Acc1and the phase information CNTV+d is greater than |Acc1−(CNTV−1+d)|. This is to determine whether or not the output CNTV from the counter120is shifted since the counter120and the TDC130are operated by the asynchronous clock.

For example, inFIG. 3, the phase difference d output from the TDC130should be added to a value N output from the counter120(i.e., the accumulator121). However, when the reference signal Fref rises up near the rising-up of the oscillation signal CKV, the output CNTV from the counter120is shifted, thereby raising a possibility that the phase difference d and the value N+1 are added.

In view of the above, when |Acc1−(CNTV+d)| is greater than |Acc1−(CNTV−1+d)|, it is determined that the output CNTV from the counter120is shifted. When |Acc1−(CNTV+d)| is greater than |Acc1−(CNTV−1+d)|, the corrector160subtracts 1 from the phase information CNTV+d output from the adder140, and then, outputs it to the subtractor170as the corrected phase information Acc2.

In contrast, the corrector160outputs the phase information CNTV+d as it is to the subtractor170as the phase information Acc2when |Acc1−(CNTV+d)| is |Acc1−(CNTV−1+d)| or smaller.

In addition, the corrector160determines whether or not the phase difference d is smaller than the predetermined value A. The phase difference d being smaller than the predetermined value A signifies that the reference signal Fref rises up near the rising-up of the oscillation signal CKV, as illustrated inFIG. 4. In this case, the reference signal Fref rises up somewhat later than the oscillation signal CKV.

When the phase difference d is smaller than the predetermined value A, the corrector160determines whether or not the difference |Acc1−(CNTV+d)| between the phase control signal Acc1and the phase information CNTV+d is greater than |Acc1−(CNTV+1+d)|. This is to determine whether or not the output CNTV from the counter120is shifted since the counter120and the TDC130are operated by the asynchronous clock.

For example, inFIG. 4, the phase difference d output from the TDC130should be added to a value N+1 output from the counter120(i.e., the accumulator121). However, when the reference signal Fref rises up near the rising-up of the oscillation signal CKV, the output CNTV from the counter120is shifted, thereby raising a possibility that the phase difference d and the value N are added.

In view of the above, when |Acc1−(CNTV+d)| is greater than |Acc1−(CNTV+1+d)|, it is determined that the output CNTV from the counter120is shifted. When |Acc1−(CNTV+d)| is greater than |Acc1−(CNTV+1+d)|, the corrector160adds 1 to the phase information CNTV+d output from the adder140, and then, outputs it to the subtractor170as the corrected the phase information Acc2.

In contrast, the corrector160outputs the phase information CNTV+d as it is to the subtractor170as the phase information Acc2when |Acc1−(CNTV+d)| is |Acc1−(CNTV+1+d)| or smaller.

In other cases, that is, when the difference dCKV-d is the predetermined A or greater and the phase difference d is the predetermined A or greater, the corrector160outputs the phase information CNTV+d as it is to the subtractor170as the phase information Acc2.

The above-described operation of the corrector160will be described below with reference to a flowchart illustrated inFIG. 5.

It is determined whether or not the difference between the cycle dCKV and the phase difference d is smaller than the predetermined value A. If the difference is smaller than the predetermined value A, the control routine proceeds to step S503. In contrast, if the difference is the predetermined value A or greater, the control routine proceeds to step S502.

It is determined whether or not the phase difference d is smaller than the predetermined value A. If the phase difference d is smaller than the predetermined value A, the control routine proceeds to step S504. In contrast, if the phase difference d is the predetermined value A or greater, the control routine proceeds to step S505.

It is determined whether or not the difference |Acc1−(CNTV+d)| between the phase control signal Acc1and the phase information CNTV+d is greater than |Acc1−(CNTV−1+d)|. If |Acc1−(CNTV+d)| is greater than |Acc1−(CNTV−1+d)|, the control routine proceeds to step S506.

In contrast, if |Acc1−(CNTV+d)| is |Acc1−(CNTV−1+d)| or smaller, the control routine proceeds to step S505.

It is determined whether or not the difference |Acc1−(CNTV+d)| between the phase control signal Acc1and the phase information CNTV+d is greater than |Acc1−(CNTV+1+d)|.

If |Acc1−(CNTV+d)| is greater than |Acc1−(CNTV+1+d)|, the control routine proceeds to step S507. In contrast, if |Acc1−(CNTV+d)| is |Acc1−(CNTV+1+d)| or smaller, the control routine proceeds to step S505.

The phase information CNTV+d output from the adder140is output as it is to the subtractor170as the phase information Acc2.

The value obtained by subtracting 1 from the phase information CNTV+d output from the adder140is output to the subtractor170as the phase information Acc2.

The value obtained by adding 1 to the phase information CNTV+d output from the adder140is output to the subtractor170as the phase information Acc2.

Otherwise, the operation of the corrector160may be described as illustrated inFIG. 6.

As illustrated inFIG. 1, the subtractor170calculates a difference between the phase control signal Acc1and the phase information Acc2output from the corrector160, and then, outputs the difference to the digital filter180.

The digital filter180acts as a low-pass filter, to smooth the received difference.

The multiplier190multiplies the output from the digital filter180by a coefficient K, and then, outputs the signal OTW. A frequency gain with respect to a control value in the DCO100is corrected by multiplying the coefficient K.

When the oscillation frequency in the DCO100becomes greater (or smaller) than a value set by the frequency control signal Fc, the digital filter180and the multiplier190output the signal OTW to control to decrease (or increase) the oscillation frequency based on the difference calculated in the subtractor170. In this manner, the oscillation frequency in the DCO100is controlled to become constant.

Even if the count CNTV added to the phase difference d is shifted by the asynchronous operation of the counter120and the TDC130, the corrector160can correct the shift, thereby preventing any erroneous operation so as to enhance the stability of the PLL operation.

In this manner, the oscillator control apparatus according to the present embodiment can achieve the stable PLL operation.

In the above-described embodiment, when the transition (i.e., rising-up) time of the output from the flip-flop110becomes long, the count output from the counter120may be markedly shifted. In this case, the corrector160outputs the phase control signal Acc1as the phase information Acc2. In other words, the output CNTV+d from the adder140is not considered. As a consequence, the PLL operation can be prevented from becoming instable. Incidentally, the operation of the corrector160in this case may be described as illustrated inFIG. 7. A threshold B is, for example, 2.

Alternatively, as illustrated inFIG. 8, an input to the accumulator150and an output from the digital filter180may be multiplied by a value obtained by standardizing modulation data Fmod by the reference signal Fref. With this configuration, modulation can be controlled with high accuracy in modulating a wide bandwidth.

The oscillator control apparatus in the embodiment may be applied to the ADPLL having a frequency as low as about 100 kHz as the frequency of the reference signal Fref, the ADPLL taking much time to restore once an erroneous operation occurs.

Or, the oscillator control apparatus in the embodiment may be applied to radio LAN equipment, a mobile telephone, a broadcast wave receiver, or the like.