Buried MIM capacitor structure with landing pads

A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.

BACKGROUND

The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a thermally stable buried metal-insulator-metal (MIM) capacitor with landing pads that is formed on a bulk semiconductor substrate.

A capacitor is a passive two-terminal electrical component that stores electrical energy in an electric field. A capacitor is a component designed to add capacitance to a circuit. Capacitors are widely used in electronic circuits for blocking direct current while allowing alternating current to pass.

Metal-insulator-metal (MIM) capacitors are one type of capacitor design that is valuable in many applications. For example, MIM capacitors can be used in radio frequency (RF) circuits, in various configurations in analog integrated circuits (ICs), and for decoupling capacitance in high power microprocessor units (MPUs). MIM capacitors are useful in dynamic access random memory (DRAM) cells. As such, there is a need for providing MIM capacitors that are thermally stable and which can have a tailored capacitance.

Furthermore, and in conventional MIM capacitors, the metal layers of the capacitor are very thin and hard to contact. Hence, there is also a need for providing MIM capacitors in which larger bulk areas are provided for contacting.

SUMMARY

A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.

In one aspect of the present application, a semiconductor structure containing a thermally stable MIM capacitor with landing pads is provided. In one embodiment, the semiconductor structure may include a first oxide layer located on a semiconductor substrate. A metal-insulator-metal (MIM) capacitor is located on the first oxide layer. The MIM capacitor includes a first refractory metal or metal alloy layer, a dielectric material layer, and a second refractory metal or metal alloy layer. A second oxide layer is located above the MIM capacitor. A semiconductor material device layer is located on the second oxide layer. In accordance with the present application, the first oxide layer includes a first landing pad embedded therein, and the second oxide layer includes a second landing pad embedded therein. The landing pads are composed of a refractory metal or metal alloy.

In another aspect of the present application, a method of forming a semiconductor structure containing a thermally stable MIM capacitor with landing pads is provided. In one embodiment, the method may include providing a first structure that includes a first oxide layer located on a surface of a first semiconductor substrate, the first oxide layer having an opening located therein, and a first refractory metal or metal alloy layer located above the first oxide layer and filling the opening. A second structure is also provided that includes a second semiconductor substrate, a second oxide layer is located on the second semiconductor substrate and having an opening located therein, and a second refractory metal or metal alloy layer above the second oxide layer and filling the opening. In the present application, a dielectric material layer is present on at least one of the first refractory metal or metal alloy layer and the second refractory metal or metal alloy layer. Next, the first and second structures are bonded together such that the second semiconductor substrate has a physically exposed surface. A portion of the second semiconductor substrate is then removed. Next, first and second trench isolation structures are formed extending from a topmost surface of a remaining portion of the second semiconductor substrate and contacting a surface of the first semiconductor substrate.

In another embodiment, the method may include providing a first structure that includes a first oxide layer located on a surface of a first semiconductor substrate, the first oxide layer having an opening located therein, a first refractory metal or metal alloy layer is located above the first oxide layer and filling the opening, and a first dielectric material layer is located on the first refractory metal or metal alloy layer. A second refractory metal or metal alloy layer is then formed on the first dielectric material layer. A second oxide layer is formed above the second refractory metal or metal alloy layer, wherein the second oxide layer has a refractory metal or metal alloy structure embedded therein. A second structure is provided than includes a second semiconductor substrate. The first and second structures are bonded together. Next, a portion of the second semiconductor substrate is removed. Next, first and second trench isolation structures are formed extending from a topmost surface of a remaining portion of the second semiconductor substrate and contacting a surface of the first semiconductor substrate.

DETAILED DESCRIPTION

Referring first toFIG. 1, there is illustrated an exemplary semiconductor structure that can be employed in accordance with an embodiment of the present application. The exemplary semiconductor structure ofFIG. 1includes a first oxide layer12located on a surface of a first semiconductor substrate10.

The semiconductor substrate10that can be employed in the present application is a bulk semiconductor substrate. By “bulk” it is meant that the semiconductor substrate10is entirely composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that may provide the semiconductor substrate10include silicon (Si), germanium (Ge), silicon germanium alloys (SiGe), III-V compound semiconductors or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements. In one example, the semiconductor substrate10may be entirely composed of silicon. In some embodiments, the semiconductor substrate10may include a multilayered semiconductor material stack including at least two different semiconductor materials, as defined above. In one example, the multilayered semiconductor material stack may comprise, in any order, a stack of Si and a silicon germanium alloy.

The semiconductor material that provides the semiconductor substrate10may be a single crystalline semiconductor material. The semiconductor material that provides the semiconductor substrate10may have any of the well known crystal orientations. For example, the crystal orientation of the semiconductor substrate10may be {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used in the present application.

The first oxide layer12is a dielectric material such as, for example, a semiconductor oxide. In one embodiment, the semiconductor oxide may include silicon dioxide. In one embodiment, the first oxide layer12may be formed utilizing a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). In other embodiments, the first oxide layer12may be formed using a spin-on oxide process which also has self-leveling properties. In yet other embodiments, the first oxide layer12may be formed by a thermal oxidation process. The first oxide layer12can have a thickness from 50 nm to 1000 nm. Other thicknesses that are above or below the aforementioned thickness range may also be employed as the thickness of the first oxide layer12.

Referring now toFIG. 2, there is illustrated the exemplary semiconductor structure ofFIG. 1after forming an opening14in the first oxide layer12. As is shown, the opening14is formed partially in, but not completely through, the first oxide layer12. The opening14can be formed by lithography and etching. Lithography includes forming a photoresist material on a material to be patterned, exposing the photoresist material to a pattern of irradiation and then developing the exposed photoresist material. Etching may include a dry etching process such as, for example, reactive ion etching, or a wet chemical etching process. The opening14provides a region/area in which a landing pad will be subsequently formed.

Referring now toFIG. 3, there is illustrated the exemplary semiconductor structure ofFIG. 2after forming a first metal-containing liner16on the first oxide layer12and within the opening14. The first metal-containing liner16is a continuous layer that is present on physically exposed surfaces of the first oxide layer12. The first metal-containing liner16serves as a reaction and diffusion barrier. The first metal-containing liner16may be composed of Ru, RuTi, RuTa, RuNb, RuW, Ta, TaTi, TW, TaNb, TaMo, Ta/TiN, TaNbN, TaWN, TaMoN, Ti, TiN, TiTaN, W or WN. The first metal-containing liner16can be formed by a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition or plating. The first metal-containing liner16may have a thickness from 0.5 nm to 20 nm. Other thickness are contemplated and can be employed in the present application as long as the first metal-containing liner16does not entirely fill the opening14.

Referring now toFIG. 4, there is illustrated the exemplary semiconductor structure ofFIG. 3after forming a first refractory metal or metal alloy layer18on the first metal-containing liner16. As is shown, the first refractory metal or metal alloy layer18completely fills in the opening14that is formed in the first oxide layer12.

The first refractory metal or metal alloy layer18is composed of a metal or metal alloy that is extraordinarily resistant to heat. That is, the metal or metal alloy that provides the first refractory metal or metal alloy layer18has a melting point above 2000° C. Examples of metals or metal alloys that provide the first refractory metal or metal alloy layer18include niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re) or alloys thereof.

The first refractory metal or metal alloy layer18may be formed utilizing a deposition process such as, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or plating. In some embodiments, a chemical removal process such as, for example, chemical mechanical polishing may follow the deposition of the metal or metal alloy that provides the first refractory metal or metal alloy layer18. The first refractory metal or metal alloy layer18may have a thickness from 20 nm to 100 nm. Other thicknesses are contemplated and can be employed in the present application.

Referring now toFIG. 5, there is illustrated the exemplary semiconductor structure ofFIG. 4after forming a first dielectric material layer20on the first refractory metal or metal alloy layer18. The first dielectric material layer20is a continuous layer that covers an entirety of the underlying first refractory metal or metal alloy layer18. In some embodiments, the first dielectric material layer20may be omitted.

The first dielectric material layer20that is employed in the present disclosure includes any dielectric material having electrically insulating properties and a dielectric constant that is equal to, or greater than, silicon dioxide. Dielectric materials having dielectric constants greater than silicon dioxide, which can also be used as first dielectric material layer20, may be referred to as high k dielectric materials. In one embodiment, the first dielectric material layer20that can be employed in the present disclosure is a high k dielectric material having a dielectric constant of 8.0 or greater. In another embodiment, the first dielectric material layer20that can be employed in the present disclosure is a high k dielectric material having a dielectric constant of 10.0 or greater.

Exemplary dielectric materials that can be employed as first dielectric material layer20include, but are not limited to, silicon dioxide, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. Multilayered stacks of these dielectric materials can also be employed as the first dielectric material layer20.

The first dielectric material layer20can be formed by a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). In one embodiment of the present application, the first dielectric material layer20can have a thickness in a range from 1 nm to 10 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the first dielectric material layer20.

Referring nowFIG. 6, there is illustrated another exemplary semiconductor structure will be subsequently bonded to the exemplary semiconductor structure shown inFIG. 5. The another exemplary semiconductor structure ofFIG. 6includes a second semiconductor substrate100having a hydrogen implant region101located therein, a second oxide layer102located on the second semiconductor substrate100, the second oxide layer102having an opening therein, a second metal-containing liner106on the second oxide layer102and within the opening, a second refractory metal or metal alloy layer108on the second metal-containing liner108and a second dielectric material layer110located on the second metal-containing liner108. In some embodiments of the present application, the second dielectric material layer110may be omitted. It is noted that at least one of the exemplary structures for bonding includes a dielectric material layer. In some embodiments, the hydrogen implant region101is optional.

The second semiconductor substrate100is a bulk semiconductor material as defined above. The second semiconductor substrate100may include one of the semiconductor materials mentioned above for the first semiconductor substrate. In one embodiment, the semiconductor material that provides the second semiconductor substrate100is composed of a same semiconductor material as that which provides the first semiconductor substrate10. In another embodiment, the semiconductor material that provides the second semiconductor substrate100is composed of a different semiconductor material than that which provides the first semiconductor substrate10.

The hydrogen implant region101is formed into the second semiconductor substrate100by implanting hydrogen ions into the second semiconductor substrate100. The hydrogen ion implantation is typically performed after forming the second oxide layer102, but prior to forming the second metal-containing liner108. The hydrogen implant region101has a peak ion concentration that is located at a depth from 200 nm to 2000 nm below the upper surface of the second semiconductor substrate100. The implant conditions can vary depending upon the thickness of the second semiconductor substrate100. Typical implantation conditions used in forming the hydrogen implant region101are as follows: ion energy from 60 KeV to 250 KeV and a hydrogen ion dose from about 2E16 atoms/cm2to 5E16 atoms/cm2.

The second oxide layer102includes one of the dielectric oxide materials mentioned above for the first oxide layer12. The second oxide layer102may be composed of a same, or a different, dielectric oxide material as the first oxide layer20. The second oxide layer102may be formed utilizing one of the techniques mentioned above in forming the first oxide layer12. The second oxide layer102may have a thickness within the thickness range mentioned above for the first oxide layer12. The opening that is provided in the second oxide layer102can be formed by lithography and etching, as defined above.

The second metal-containing liner106includes one of the metals or metal alloys mentioned above for the first metal-containing liner16. The second metal-containing liner106may be composed of a same, or a different, metal or metal alloy as the first metal-containing liner16. The second metal-containing liner106may be formed utilizing one of the techniques mentioned above in forming the first metal-containing liner16. The second metal-containing liner106may have a thickness within the thickness range mentioned above for the first metal-containing liner16.

The second refractory metal or metal alloy layer108includes one of the refractory metals or metal alloys mentioned above for the first refractory metal or metal alloy layer18. The second refractory metal or metal alloy layer108may be composed of a same, or a different, refractory metal or metal alloy as the first refractory metal or metal alloy layer18. The second refractory metal or metal alloy layer108may be formed utilizing one of the techniques mentioned above in forming the first refractory metal or metal alloy layer18. The second refractory metal or metal alloy layer108may have a thickness within the thickness range mentioned above for the first refractory metal or metal alloy layer18.

The second dielectric material layer110includes one of the dielectric materials mentioned above for the first dielectric material layer20. The second dielectric material layer110may be composed of a same, or a different, dielectric material as the first dielectric material layer20. The second dielectric material layer110may be formed utilizing one of the techniques mentioned above in forming the first dielectric material layer20. The second dielectric material layer110may have a thickness within the thickness range mentioned above for the first refractory metal or metal alloy layer20.

Referring now toFIG. 7, there is illustrated the exemplary semiconductor structures ofFIGS. 5-6after bonding the two exemplary structures together. The bonding of the two exemplary structures together includes flipping one of the exemplary structures 180°, bringing the two exemplary structures into intimate contact with each other, and performing a bonding anneal. An external pressure can be applied during and/or after the contact step.

The flipping of one of the two exemplary structures and the bringing them into intimate contact can be performed by hand or by mechanical means. In one embodiment and as shown, bonding occurs between the first and second dielectric material layers20,110. In another embodiment, bonding occurs between the dielectric material layer of one of the exemplary structures and the refractory metal or metal alloy layer of another of the exemplary structures.

In some embodiments, the intimate contacting may provide an initial bond between the two exemplary structures that is provided by a dielectric/dielectric interface or a dielectric/refractory metal or metal alloy interface. The intimate contacting may be performed at a temperature from 15° C. to 40° C. In some embodiments, bond strength can be enhanced by plasma activation of the oxide surfaces before bonding.

The bonding anneal is performed at a temperature that is relatively low so as to prevent hydrogen induced crack propagation in the hydrogen implant region101from occurring prior to bond strengthen which is achieved during the bonding anneal. In one embodiment, the bonding anneal is performed at a temperature from 200° C. to 350° C. The bonding anneal may be performed for a time period from 2 hours to 24 hours The bonding annealing can be performed in an inert ambient including helium, nitrogen, argon, neon and/or krypton. Alternatively, a forming gas which includes a mixture of nitrogen and hydrogen can be employed. The bonding anneal may be performed at a single targeted temperature utilizing a single ramp up rate, or various ramp and soak cycles using various ramp rates and soak times can be employed.

Referring now toFIG. 8, there is illustrated the exemplary bonded semiconductor structure ofFIG. 7during the removal of an upper portion100B of the second semiconductor substrate100that includes the hydrogen implant region101. The remaining portion of the second semiconductor substrate100may be referred to a semiconductor material device layer100A. The semiconductor material device layer100A may have a thickness from 5 nm to 100 nm. In embodiments in which no hydrogen implant region101is present in the second semiconductor substrate100, a material removal process such as, for example, chemical mechanical polishing and/or grinding may be employed. A wet etch process is another example of a material removal process that can be used in the present application to remove an upper portion100B of the second semiconductor substrate100.

The removal of the upper portion100B of the second semiconductor substrate100is performed utilizing a splitting anneal that is performed at a higher temperature than the bonding anneal described above so as to allow a hydrogen induced Oswald ripen effect to occur, i.e., to form a crack in the second semiconductor substrate100at the plane of the hydrogen implant region101. That is, this splitting anneal is performed at a temperature that forms a crack at the hydrogen implant region101which is capable of separating, i.e., splitting, a portion of the second semiconductor substrate100from the bonded structures. A razor blade or other like means can be used to aid in the separation process.

In one embodiment, the splitting anneal is performed at a temperature from 475° C. to 550° C. In some embodiments, the splitting anneal may be performed for a time period from 4 hours to 6 hours. This splitting anneal can be performed in one of the above mentioned ambients and various heating regimes including different ramp up rates, soak cycles and cool down rates can be employed.

Referring now toFIG. 9, there is illustrated the exemplary bonded semiconductor structure ofFIG. 10after complete removal of the upper portion100B of the second semiconductor substrate100that includes the hydrogen implant region101. One or more semiconductor devices such as, for example, transistors may be processed on or within the semiconductor material device layer100A. InFIG. 9, element P1denotes a first landing pad, while element P2denotes a second landing pad. The landing pads, P1, P2, are composed of the refractory metal or metal alloy that is located within each opening that was formed into the oxide layers. The first and second dielectric layers20,110may collectively be referred to herein as a capacitor insulator material layer21.

Referring now toFIG. 10, there is illustrated the exemplary bonded semiconductor structure ofFIG. 9after forming, in any order, contact structures and trench isolation structures50L,50R;50L may be referred to as a first trench isolation structure, and50R may be referred to as a second trench isolation structure. Each contact structures may include a diffusion barrier liner52L,52R and a contact metal or metal alloy structure54L,54R. Each of the contact structures contacts a surface of one of the landing pads, P1, P2. Elements52L,54L define a first contact structure, while elements52R,54R define a second contact structure. The first and second contact structures may be devoid of the diffusion barrier liner.

The contact structures can be formed by providing a contacting opening that extends from a topmost surface of the semiconductor material device layer100A to a surface of one of the underlying landing pads, P1, P2. The contact openings can be formed by lithography and etching. A diffusion barrier layer can then be optionally formed into each of the contact openings. The diffusion barrier layer may be composed of any diffusion barrier material such as, for example, Ti, TiN, Ta or Ta/TaN. A sputter etch may be employed to remove the diffusion barrier layer from the surface of the landing pads, P1, P2. A contact metal or metal alloy such as, for example, copper, aluminum, cobalt, tungsten or a copper-aluminum alloy is then formed into each contact opening. A planarization process may follow so as to provide diffusion barrier liners52L,52R and contact metal or metal alloy structures54L,54R in their respective contact openings.

Trench isolation structures50L,50R can be formed by lithography and etching to provide isolation trenches in the structure. The isolation trenches can be filled with a trench dielectric material such as, for example, silicon dioxide. A densification process and/or a planarization process may follow the trench fill process.

Collectively, the first refractory metal or metal alloy layer18, the capacitor insulator material layer21, and the second refractory metal or metal alloy layer108that is provided between neighboring trench isolation structures50L,50R provide a buried MIM capacitor of the present application with landing pads P1, P2. The capacitance of the buried MIM capacitor can adjusted by varying the distance between the neighboring trench isolation structures50L,50R.

FIG. 10illustrates an exemplary semiconductor structure of the present application. The exemplary semiconductor structure includes a first oxide layer12located on a semiconductor substrate10. A metal-insulator-metal (MIM) capacitor (18/21/108) is located on the first oxide layer12. The MIM capacitor (18/21/108) comprises a first refractory metal or metal alloy layer18, a dielectric material layer21, and a second refractory metal or metal alloy layer108. A second oxide layer102is located on the MIM capacitor (18/21/108). A semiconductor material device layer100A is located on the second oxide layer102. In accordance with the present application the first oxide layer12includes a first landing pad, P1, embedded therein, and the second oxide layer102includes a second landing pad, P2, embedded therein.

The first and second landing pads, P1, P2are composed of a refractory metal or metal alloy. In this embodiment, the first landing pad, P1, is composed of a same refractory metal or metal alloy as the first refractory metal or metal alloy layer18, while the second landing pad, P2, is composed of a same refractory metal or metal alloy as the second refractory metal or metal alloy layer108. In this embodiment, the first landing pad, P1, is in direct physical contact with the first refractory metal or metal alloy layer18, and the second landing pad is in direct physical contact with the second refractory metal or metal alloy layer108.

Referring now toFIG. 11, there is illustrated the exemplary semiconductor structure ofFIG. 4after forming a first dielectric material layer20on the first refractory metal or metal alloy layer18, and a second refractory metal or metal alloy layer108on the first dielectric material layer20in accordance with another embodiment of the present application.

The first dielectric material layer20of this embodiment includes one of the dielectric materials mentioned previous for the first dielectric material layer20. The first dielectric material layer20of this embodiment can be formed utilizing one of the techniques mentioned above in forming the first dielectric material layer20. The first dielectric material layer20has a thickness that is generally thicker than in the embodiment illustrated previously. Notably, the first dielectric material layer20of this embodiment can have the combined thickness of the first and second dielectric material layers20,110of the previous embodiment of the present application.

The second refractory metal or metal alloy layer108of this embodiment is the same as that in the previous embodiment of the present application except that the second refractory metal or metal alloy layer108is formed directly upon the first dielectric material layer20utilizing one of the deposition processes previous mentioned above for forming the first refractory metal or metal alloy layer18.

Referring now toFIG. 12, there is illustrated the exemplary semiconductor structure ofFIG. 11after forming a second metal-containing liner106on the second refractory metal or metal alloy layer108. The second metal-containing liner106of this embodiment is the same as that in the previous embodiment of the present application except that the second metal-containing liner106is formed directly upon the second refractory metal or metal alloy layer108utilizing one of the deposition processes previous mentioned above for forming the first metal-containing liner16.

Referring now toFIG. 13, there is illustrated the exemplary semiconductor structure ofFIG. 12after forming an oxide layer102L on the second metal-containing liner106. The oxide layer102L of this embodiment is the same as the second oxide layer102of the previous embodiment of the present application except that the oxide layer102L is formed directly upon the second metal-containing liner106utilizing one of the deposition processes previous mentioned above for forming the first oxide layer12.

Referring now toFIG. 14, there is illustrated the exemplary semiconductor structure ofFIG. 13after forming an opening (not shown) in the oxide layer102L, and forming metal-containing spacers107and a refractory metal or metal alloy structure112in the opening. The opening can be formed by lithography and etching, as defined above. Next, a metal-containing layer is formed into the opening and a spacer etch can be used to remove a portion of the metal-containing layer along the bottom of the opening to provide the metal-containing spacers107. The metal-containing layer and thus the metal-containing spacers107include a same metal or metal alloy as the second metal-containing liner106mentioned above.

Next, a refractory metal or metal alloy layer is formed into the opening and thereafter a planarization process can be employed to provide the refractory metal or metal alloy structure112. The refractory metal or metal alloy that provides the refractory metal or metal alloy structure112is composed of one of the refractory metals or metal alloys mentioned above for the first refractory metal or metal alloy layer18. The refractory metal or metal alloy that provides the refractory metal or metal alloy structure112may be composed of a refractory metal or metal alloy that is the same or different from the refractory metal or metal alloy that provides either the first or second refractory metal or metal alloy layers18,108. The refractory metal or metal alloy layer may be formed by utilizing one of the deposition processed mentioned above for forming the first refractory metal or metal alloy layer18.

Referring now toFIG. 15, there is illustrated the exemplary semiconductor structure ofFIG. 14after forming additional oxide on the oxide layer102L. The additional oxide layer is typically the same oxide as the oxide layer102L. Collectively, the additional oxide layer and the oxide layer102L may be referred to as the second oxide layer102. The additional oxide layer is formed atop the metal-containing spacers107and the refractory metal or metal alloy structure112that was previously formed into the opening provided in the oxide layer102L. The additional oxide layer can be formed utilizing one of the techniques mentioned above in forming the first oxide layer12.

Referring now toFIG. 16, there is illustrated the exemplary semiconductor structure ofFIG. 15after bonding a second semiconductor substrate100containing a hydrogen implant region101to the additional oxide, i.e., to a topmost surface of the second oxide layer102. In some embodiments, the second semiconductor substrate100may include an oxide layer114thereon such that an oxide-to-oxide bonding interface is formed. In another embodiment, oxide layer114may be omitted and a semiconductor-to-oxide bonding interface may be formed. In some embodiments, no hydrogen implant region101is present in the second semiconductor substrate100.

The second semiconductor substrate100includes materials and can be formed as described above in the previous embodiment of the present application. Hydrogen implant region101can be formed as described above. Bonding may be performed utilizing the bonding process mentioned above, i.e., flipping one of the structures 180°, bringing the two structures into intimate contact with each other and then performing a bonding anneal.

The exemplary structure shown inFIG. 16may then be subjected to the splitting anneal mentioned above (or any other material removal process) to remove an upper portion of the second semiconductor substrate100, and thereafter trench isolation structures and contact structures as defined above can be formed. The contact structures will contact surfaces of the landing pads P1, P2.

After performing these steps another exemplary semiconductor structure is provided that includes a first oxide layer12located on a semiconductor substrate10. A metal-insulator-metal (MIM) capacitor (18/20/108) is located on the first oxide layer12. The MIM capacitor (18/20/108) comprises a first refractory metal or metal alloy layer18, a dielectric material layer20, and a second refractory metal or metal alloy layer108. A second oxide layer102is located on the MIM capacitor (18/20/108). A semiconductor material device layer (i.e., remaining portion of100) is located on the second oxide layer102. In accordance with the present application the first oxide layer12includes a first landing pad, P1, embedded therein, and the second oxide layer102includes a second landing pad, P2, embedded therein.

The first and second landing pads P1, P2are composed of a refractory metal or metal alloy. In this embodiment, the first landing pad, P1, is composed of a same refractory metal or metal alloy as the first refractory metal or metal alloy layer18, while the second landing pad, P2, is composed of a refractory metal or metal alloy that may or may not be the same as the second refractory metal or metal alloy layer108. In this embodiment, the first landing pad, P1, is in direct physical contact with the first refractory metal or metal alloy layer18, and the second landing pad spaced apart from the second refractory metal or metal alloy layer108.

Referring now toFIG. 17, there is illustrated the exemplary semiconductor structure ofFIG. 3after forming a first refractory metal or metal alloy layer18in accordance with another embodiment of the present application. In this embodiment, a larger area MIM capacitor is provided composed to the MIM capacitors formed in the previously embodiments of the present application.

The first refractory metal or metal alloy layer18of this embodiment of the present application is the same as the previous embodiments except that the thickness of the first refractory metal or metal alloy layer18of this embodiment is much greater than in the other embodiments of the present application. In one example, the first refractory metal or metal alloy layer18of this embodiment may have a thickness from 2 nm to 10 nm.

Referring now toFIG. 18, there is illustrated the exemplary semiconductor structure ofFIG. 17after patterning the first refractory metal or metal alloy layer18to provide a patterned first refractory metal or metal alloy layer18P having a topography. The patterning of the first refractory metal or metal alloy layer18may be performed utilizing lithography and etching, a sidewall-image transfer process or a directed self-assembly process. In some embodiments, the patterned first refractory metal or metal alloy layer18P contains a plurality of vertical pillars or fins that extend upwards from a base portion of the patterned first refractory metal or metal alloy layer18P. A gap may be present between the vertical pillars (i.e., fins) as shown inFIG. 18.

Referring now toFIG. 19, there is illustrated the exemplary semiconductor structure ofFIG. 18after forming a first dielectric material layer20on the patterned first refractory metal or metal alloy layer18P. The first dielectric material layer20includes dielectric materials and thicknesses as mentioned above in the first embodiment of the present application, see, for example,FIG. 5and related text.

Referring now toFIG. 20, there is illustrated the exemplary semiconductor structure ofFIG. 19after forming a second refractory metal or metal alloy layer108on the first dielectric material layer20. The second refractory metal or metal alloy layer108of this embodiment is the same as that in the first embodiment of the present application except that the second refractory metal or metal alloy layer108is formed directly upon the first dielectric material layer20utilizing one of the deposition processes previous mentioned above for forming the first refractory metal or metal alloy layer18. In some embodiments, a planarization process may follow the deposition of the refractory metal or metal alloy that provides the second refractory metal or metal alloy layer108.

Referring now toFIG. 21, there is illustrated the exemplary semiconductor structure ofFIG. 20after forming a second metal-containing liner106on the second refractory metal or metal alloy layer108. The second metal-containing liner106of this embodiment is the same as that in the first embodiment of the present application except that the second metal-containing liner106is formed directly upon the second refractory metal or metal alloy layer108utilizing one of the deposition processes previous mentioned above for forming the first metal-containing liner16.

Referring now toFIG. 22, there is illustrated the exemplary semiconductor structure ofFIG. 21after forming an oxide layer102L. The oxide layer102L of this embodiment is the same as the second oxide layer102of the first embodiment of the present application except that the oxide layer102L is formed directly upon the second metal-containing liner106utilizing one of the deposition processes previous mentioned above for forming the first oxide layer12.

Referring now toFIG. 23, there is illustrated the exemplary semiconductor structure ofFIG. 22after forming an opening (not shown) in the oxide layer102L, forming metal-containing spacers107and a refractory metal or metal alloy structure112in the opening, forming additional oxide, and bonding a second semiconductor substrate100containing a hydrogen implant region101to the additional oxide. The opening can be formed by lithography and etching, as defined above. Next, a metal-containing layer is formed into the opening and a spacer etch can be used to remove a portion of the metal-containing layer along the bottom of the opening to provide the metal-containing spacers107. The metal-containing layer and thus the metal-containing spacers107include a same metal or metal alloy as the second metal-containing liner106mentioned above.

Next, a refractory metal or metal alloy layer is formed into the opening and thereafter a planarization process can be employed to provide the refractory metal or metal alloy structure112. The refractory metal or metal alloy that provides the refractory metal or metal alloy structure112is composed of one of the refractory metals or metal alloys mentioned above for the first refractory metal or metal alloy layer18. The refractory metal or metal alloy that provides the refractory metal or metal alloy structure112may be composed of a refractory metal or metal alloy that is the same or different from the refractory metal or metal alloy that provides either the first or second refractory metal or metal alloy layers18,108. The refractory metal or metal alloy layer may be formed by utilizing one of the deposition processed mentioned above for forming the first refractory metal or metal alloy layer18.

Next, the additional oxide layer is formed on oxide layer102and atop the metal-containing spacers107and the refractory metal or metal alloy structure112. The additional oxide layer is typically the same oxide as the oxide layer102L. Collectively, the additional oxide layer and the oxide layer102L may be referred to as the second oxide layer102. The additional oxide layer is formed atop the metal-containing spacers107and the refractory metal or metal alloy structure112that was previously formed into the opening provided in the oxide layer102L. The additional oxide layer can be formed utilizing one of the techniques mentioned above in forming the first oxide layer12.

A second semiconductor substrate100containing a hydrogen implant region101is then provided and bonded to the additional oxide, i.e., to a topmost surface of the second oxide layer102. In some embodiments, the second semiconductor substrate100may include an oxide layer114thereon such that an oxide-to-oxide bonding interface is formed. In another embodiment, oxide layer114may be omitted and a semiconductor-to-oxide bonding interface may be formed. In some embodiments, the hydrogen implant region101is omitted from the second semiconductor substrate100.

The second semiconductor substrate100containing a hydrogen implant region101includes materials and can be formed as described above in the previous embodiment of the present application. Bonding may be performed utilizing the bonding process mentioned above, i.e., flipping one of the structures 180°, bringing the two structures into intimate contact with each other and then performing a bonding anneal.

The exemplary structure shown inFIG. 23may then be subjected to the splitting anneal mentioned above (or any other material removal process) to remove an upper portion of the second semiconductor substrate100, and thereafter trench isolation structures and contact structures as defined above can be formed. The contact structures will contact surfaces of the landing pads P1, P2.

After performing these steps another exemplary semiconductor structure is provided that includes a first oxide layer12located on a semiconductor substrate10. A metal-insulator-metal (MIM) capacitor (18/20/108) is located on the first oxide layer12. The MIM capacitor (18/21/108) comprises a first refractory metal or metal alloy layer18, a dielectric material layer20, and a second refractory metal or metal alloy layer108. A second oxide layer102is located on the MIM capacitor (18/20/108). A semiconductor material device layer (i.e., remaining portion of100) is located on the second oxide layer102. In accordance with the present application the first oxide layer12includes a first landing pad, P1, embedded therein, and the second oxide layer102includes a second landing pad, P2, embedded therein.

The first and second landing pads P1, P2are composed of a refractory metal or metal alloy. In this embodiment, the first landing pad, P1, is composed of a same refractory metal or metal alloy as the first refractory metal or metal alloy layer18, while the second landing pad, P2, is composed of a refractory metal or metal alloy that may or may not be the same as the second refractory metal or metal alloy layer108. In this embodiment, the first landing pad, P1, is in direct physical contact with the first refractory metal or metal alloy layer18, and the second landing pad P2is spaced apart from the second refractory metal or metal alloy layer108.