Configurable cell for customizable logic array device

This invention discloses a cell forming part of a customizable logic array device, the cell including at least first (34) and second multiplexers, each having a select input and an output, at least two inverters (42, 52), each having an input and an output, and electrical connections (26, 54), selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the at least two inverters. A customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers is also disclosed. The invention additionally discloses a cell forming part of a customizable logic array device, the cell including a pair of identical logic portion located on opposite sides of a driver portion. The driver portion includes at least two drivers, each having an input and an output. The pair of identical logic portions including at least one multiplexer (12) having a select input and an output, at least one inverter (18) having an input and an output and at least one NAND gate (30) having two inputs and an output. Preferably the cell also includes electrical connections, selectably connecting each output of each element of the cell to any other input or output of any other element of the same cell, preferably at the same metal layer.

FIELD OF THE INVENTION

The present invention relates to application-specific integrated circuits generally and more particularly to the structure of the principal building blocks of gate arrays in multi-metal semiconductor devices.

Application specific integrated circuits (ASICs) are microelectronic devices that are designed and configured to carry out sets of instructions for specific applications. Application specific integrated circuits are preferable over general-purpose of-the-shelf devices when speed, performance or device compactness is desired, or when the specific functionality cannot be obtained by available devices. Generally, the logic portion of an ASIC device is implemented by either standard cell or gate array technology. In the gate array technology an array of cells comprising simply interconnected transistors is provided by tiling and repeating the same cell over and over again. Sometimes a gate array block may be found within a standard cell device or a full custom device. In gate array technology, the metal interconnections are customized for each application. The customization of the metal interconnection layers determines the functionality of the cells and enables the desired application.

For purpose of simplicity, cost savings and short delivery time it is desirable to minimize the number of metal interconnect layers that need to be modified to implement a given functionality. For that purpose, the repetitive cells that build the array must be designed and constructed so they can provide simple as well as complex functionality with minimal overall modifications of the device.

U.S. Pat. Nos. 5,684,412, 5,751,165 and 5,861,641 describe logic cells comprising a cascade of multiplexers that are useful for a gate array that can be programmed by modifying only one or two layers of a multi-layer interconnect structure of the device. The function of each of these cells is input selectable. However, those logic cell structures have the drawback that when it is desirous to implement two simple functions such as two inverters in parallel, two separate unit logic cells have to be employed. This reduces the area utilization of the device, reduces its performance and increases its cost.

SUMMARY OF THE INVENTION

The present invention seeks to provide an improved customizable logic array device and cell therefor.

There is thus provided in accordance with a preferred embodiment of the present invention a cell forming part of a customizable logic array device, the cell including at least first and second multiplexers, each having a select input and an output, at least two inverters, each having an input and an output, and electrical connections, selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the input of one of the at least two inverters.

Further in accordance with a preferred embodiment of the present invention the at least first and second multiplexers include at least three multiplexers and the at least two inverters include at least three inverters.

Still further in accordance with a preferred embodiment of the present invention the multiplexers are implemented in at least one metal layer and said electrical connections include vias connecting said at least one metal layer to another metal layer other than said at least one metal layer.

Preferably the another metal layer is a top metal layer.

Alternatively, the another metal layer is an intermediate metal layer.

Moreover in accordance with a preferred embodiment of the present invention the another metal layer is a metal layer lying immediately above the at least one metal layer.

Additionally in accordance with a preferred embodiment of the present invention the cell being further characterized in that it has a programmable logic function. Preferably the programmable logic function is programmable by selection of at least one input to the at least first and second multiplexer and by selectable connection of the electrical connections.

Additionally, the selectable connection is effected by metal deposition, patterned and etch. Alternatively, the selectable connection is effected by application of laser energy to the electrical connections for eliminating portions thereof.

Still further in accordance with a preferred embodiment of the invention the selectable connection may be effected by application of electrical energy to the electrical connections.

Additionally in accordance with a preferred embodiment of the present invention the selectable connection is effected by metal deposition and etching.

Further in accordance with a preferred embodiment of the present invention the cell includes at least three inverters each having generally identical driving power.

Still further in accordance with a preferred embodiment of the present invention at least two of the at least three inverters each have generally identical driving power and a third of the at least three inverters has a driving power different from the driving power of the at least two of the at least three inverters.

Furthermore in accordance with a preferred embodiment of the present invention at least two of the at least three inverters each have generally identical driving power and a third of the at least three inverters has a driving power which is at least double the driving power of each of the at least two of the at least three inverters.

Furthermore in accordance with a preferred embodiment of the present invention the cell includes no more than three multiplexers, no more than five inverters and only a single NAND gate.

There is also provided in accordance with yet another preferred embodiment of the present invention a cell forming part of a customizable logic array device, the cell including at least first and second multiplexers, at least two inverters, and electrical connections, selectably connecting the at least first and second multiplexers and the at least two inverters such that the multiplexers operate either in parallel or in series.

Further in accordance with a preferred embodiment of the present invention the multiplexers are implemented in at least one metal layer and the electrical connections include vias connecting the at least one metal layer to another metal layer other than the at least one metal layer.

Preferably the another metal layer is a top metal layer.

Alternatively, the another metal layer is an intermediate metal layer.

Moreover in accordance with a preferred embodiment of the present invention the another metal layer is a metal layer lying immediately above the at least one metal layer.

There is also provided in accordance with another preferred embodiment of the present invention a customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers, each having a select input and an output, at least two inverters, each having an input and an output, and electrical connections, selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the input of one of the at least two inverters.

Further in accordance with a preferred embodiment of the present invention the at least first and second multiplexers include at least three multiplexers and the at least two inverters include at least three inverters.

There is further provided in accordance with yet another preferred embodiment of the present invention a customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers, at least two inverters, and electrical connections, selectably connecting the at least first and second multiplexers and the at least two inverters such that the multiplexers operate either in parallel or in series.

There is additionally provided in accordance with a preferred embodiment of the present invention a cell forming part of a customizable logic array device, the cell including a pair of identical logic portions located on opposite sides of a driver portion.

Preferably, the driver portion includes at least two drivers, each having an input and an output. In accordance with a preferred embodiment of the present invention, the pair of identical logic portions each comprises:

at least one multiplexer having a select input and an output;

at least one inverter having an input and an output; and

at least one NAND gate having two inputs and an output.

Preferably, the cell also includes electrical connections, selectably connecting an output of the at least one multiplexer to any of an input of the at least one inverter, an input of the at least one NAND gate, an input of at least one of the at least two drivers and an input of another one of the at least one multiplexer.

Additionally or alternatively, the cell also includes electrical connections, selectably connecting an output of the at least one NAND gate to any of an input of the at least one inverter, an input of the at least one multiplexer and an input of at least one of the at least two drivers.

Additionally or alternatively, the cell also includes electrical connections, selectably connecting an output of the at least one inverter to any of an input of the at least one NAND gate, an input of at least one of the at least two drivers and an input of one of the at least one multiplexer.

There is additionally provided in accordance with a preferred embodiment of the present invention a cell forming part of a customizable logic array device, the cell including a pair of identical logic portions located on opposite sides of a driver portion and electrical connections interconnecting the pair of identical logic portions and the driver portion at the same metal layer.

Preferably, the metal layer is a top metal layer of a microelectronic device. In accordance with a preferred embodiment of the present invention, the electrical connections comprise metal bridges located at the top metal layer. Preferably, the metal bridges connect terminals which are connected to metal segments at the bottom of the microelectronic device that form inputs and outputs.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference is now made toFIG. 1, which illustrates a single unit logic cell1constructed and operative in accordance with a preferred embodiment of the present invention. The unit logic cell comprises multiple circuit elements, generally similar to those illustrated in U.S. Pat. No. 5,684,412, but with a major distinction that the various elements are not fixedly connected to each other. Rather, the connections between the elements can be reconfigured, as will be described below.

The unit logic cell comprises a first multiplexer12, having first and second inputs13and14, a select input15and an output16, a second multiplexer22having first and second inputs23and24and a select input25, a NAND gate30having inputs31and32, and a third multiplexer34having first and second inputs35and36and a select input37. The output16of multiplexer12is fed to an inverter18, and the output36of the NAND gate30is connected to the second input36of the multiplexer34.

The output19of inverter18can be selectably connected to the first input35of the third multiplexer34. The output26of multiplexer22can be selectably connected to either the select input37of multiplexer34or to the input54of a second inverter52. The output38of multiplexer34can be selectably connected to the input44of a third inverter42, to the input54of the second inverter52, or to both. The inverters18,42and52are inverting drivers, also referred below simply as “inverters”. Their connection to the respective multiplexers forms inverting multiplexers with drive strengths as outlined below.

Simplicity is a particular feature of the cell of FIG.1. Preferably the cell ofFIG. 1includes no more than three multiplexers and no more than three inverters. Preferably, only a single NAND gate is provided.

Reference is now made toFIG. 2A, which shows one configuration of the cell of FIG.1. It is seen that when output19of the first inverter18is connected to input35of the third multiplexer34, the output26of the second multiplexer22is connected to select input37of the third multiplexer34, and output38of the third multiplexer34is connected to input44of the third inverter42, the structure of the resulting cell, shown within dotted lines designated by reference numeral70, becomes practically the same as that of the cell described in the prior art (U.S. Pat. No. 5,684,412). In this configuration, the inverter52shown within dotted lines72is not operative in the cell.

Reference is now made toFIG. 2B, which illustrates an alternative configuration of the cell of FIG.1. In contrast to the configuration shown inFIG. 2A, in the configuration ofFIG. 2B, output26of multiplexer22is connected to input54of inverter52, and no connection is provided between output19of inverter18and input35of multiplexer34. The resulting logic cell thus defines two inverting multiplexers which are shown within dotted lines respectively designated by reference numerals74and76. The circuit elements shown within dotted lines designated by reference numeral78are not operative in this cell configuration. The two inverting multiplexers can operate in parallel, with inputs13and14of multiplexer12being equivalent to inputs23and24of multiplexer22, and select input15of multiplexer12being equivalent to select input25of multiplexer22and output19of inverter18being equivalent to output56of inverter52.

Each of these inverting multiplexers can be further programmed through its inputs to perform a simple, different, input-selectable logic function. For example, when the first input13is set to 0 (e.g. connected to Vss), a signal A is connected to input14and a signal B is connected to the select input15, the inverting multiplexer within dotted lines74performs the logic function NAND. The same is true for the inverting multiplexer within dotted lines76. When the first input13is connected to a signal A, input14is set to 1 (e.g. connected to Vdd) and a signal B is connected to the select input15, the inverting multiplexer within dotted lines74performs the logic function NOR. The same is true for the inverting multiplexer within dotted lines76.

When the first input13is set to 0 (e.g. connected to Vss), the second input14is set to 1 (e.g. connected to Vdd) and a signal B is connected to the select input15the inverting multiplexer within dotted lines74performs as an inverter. The same is true for the inverting multiplexer within dotted lines76.

The configurability of the interconnects of the various element of the cell ofFIG. 1provides the following useful properties:

a) In the prior art cells, when two simple logic functions need to be implemented in parallel, such as two multiplexers, a NOR and a NAND, an inverter and a NOR, or an inverter and a NAND, in each case the design requires two separate logic cell sites. With the configurable logic cell ofFIG. 1, one can break up the logic cell to operate two separate logic functions in parallel within the same logic cell. This property allows higher area utilization of the device, which leads to reduction in cost and increase in device density.

b) The selectable connectivity of output38of multiplexer34to the inverters42and52allows connecting one or two inverters in parallel. This is useful for matching the desired drive strength to the external load for achieving optimal rise time of the load line. For low external load, only one inverter may be connected so as to minimize the internal load that limits the rise time, and for high external load, the two inverters may be connected to output38and operated in parallel, to achieve maximum driving power.

Preferably the transistor sizes of the multiplexer12should be identical to the transistor sizes of multiplexer22, and the transistor sizes of inverter52should be identical to those of inverter18. Thus, when output26is connected to input54, the elements shown within dotted lines74and76are identical, with output19matching output56with same rise time and drive strength. This is important for use with automatic design tools that need to utilize these structures for design implementation, and should be able to select the one or the other inverting multiplexer interchangeably for implementing a given logic function with given characteristics. In contrast, inverter42may be selected to be different from the other two inverters. Preferably inverter42may have double the transistor size of inverter52. This may enable a total driving strength of 1×, 2× or 3× of that of the inverter52alone to be attained, when connecting the output38to input54only, to input44only or to input44and54in parallel, respectively.

As can be seen fromFIG. 1, additional combinations of the elements are possible beyond those shown inFIGS. 2A and 2B. For example, as a variation of the arrangement ofFIG. 2A, output46may be connected to input54, thus achieving a further level of signal inversion. In this arrangement inverters42and52operate in series.

In another embodiment which may be considered as a variation of the arrangement ofFIG. 2B, external signals may be supplied to input35and select input37, in which case the cell may be broken into three parallel elements, e.g. by connecting output38to input44within dotted lines78of FIG.2B.

Referring now toFIGS. 3,4A,4B, &5it is appreciated that the connections between the elements of the logic cell for configuring the cell to perform one or more independent logic functions can be realized in several ways. Generally the implementation of the elements of the logic cell shown inFIG. 1is performed in the bottom layers of the microelectronic device (generally at the semiconductor level, the gate level and at the first metal layer). It may, however, be desirable to implement the connections that select the configuration of the cell in the top metal layer. This involves minimum cost and effort when bug fixes or device iterations are required, as only one photolithographic mask must be re-made and only one metal layer must be re-processed.

In one preferred embodiment the connections identified inFIGS. 2A and 2Bby reference numerals81,82,83and91may take the form of metal bridges between terminals located at the top metal layer. These terminals may be connected to metal segments at the bottom of the device that form the inputs and outputs shown schematically in FIG.1.

The connections between the top layer terminals and the bottom metal inputs and outputs may be realized by standard microfabrication techniques known in the art, such as stacked vias or a cascade of vias extending through the dielectric layers of the multi-layer device and being connected by metal connecting segments in the various metal layers (not shown).

FIG. 3shows a section of the top metal layer, which constitutes one preferable interconnection arrangement for configuring the logic cell of FIG.1. The interconnection arrangement also carries input and output signals to and from the cells, and may be used for programming the functionality of the logic cells.FIG. 3shows a top metal layer101having segments102that operate as removable links or as connectable links. Vias103are also shown. The vias connect the top metal layer101to underlying metal layers (not shown) and also connect to the logic cell inputs and outputs. Specifically, all the inputs and outputs identified by reference numerals inFIG. 1are connected to corresponding terminals in the top metal layer, which are identified inFIG. 3by corresponding reference numerals incremented by 100. In addition, reference numerals106and108inFIG. 3indicate terminals connected by vias to the Vss potential (logic 0) and Vdd potential (logic 1), respectively.

FIG. 4Ashows an implementation of the connectivity in the top metal for implementing the cell configured in FIG.2A. InFIG. 4A, a connection is defined between terminals119and135, between terminals126and137and between terminals138and144, while the connection between terminals126and154is broken.

FIG. 4Bshows the implementation of the connectivity in the top metal for implementing the cell configured in FIG.2B. InFIG. 4B, a connection is defined between terminals126and154, while the connections between terminals119and135and between terminals154and138are broken.

It is appreciated that in bothFIGS. 4A and 4B, many other connections between various terminals are also broken.

FIG. 4Bfurther illustrates the implementation of two parallel logic NAND functions in the two sub-cells within dotted lines74and76that are defined by the above connections. InFIG. 4B, a connection is defined between the Vss terminals106and terminals113and123, which terminals are connected in turn to the first inputs13and23of multiplexers12and22, as shown schematically in FIG.2B.

Signals A1, B1, and A2, B2are supplied along vias, connected to signal lines in the underlying interconnect layer (not shown), to the multiplexers12and22of the sub-cells within dotted lines74and76respectively of FIG.2B. Thus it may be appreciated that signal A1is supplied through terminal114to input14of multiplexer12, signal B1is supplied through terminal115to input15of multiplexer12, signal A2is supplied through terminal124to input24of multiplexer22and signal B2is supplied through terminal125to input25of multiplexer22.

FIG. 4Balso shows a vertical metal track103that is not used for cell configuration or for carrying an input or output signal for this specific cell implementation. This track can be used as a bypass for routing signals between other cells (not shown) located on both sides of the terminal area of the cell shown in FIG.4B.

The placement of the various terminals need not be limited to the layout shown in FIG.3. Rather, other placements with different nearest neighbors can be used. Yet, any effective placement should reflect key design considerations. Among the design considerations included in the design shown inFIG. 3are the placement of Vdd and Vss terminals in proximity to the terminals that are connected to the inputs of the first and second multiplexers12and22and a terminal that is connected to an input of the NAND gate30, so as to implement desired input-selectable logic functions. Outputs and inputs of the logic cell for connecting to adjacent logic cells and to a routing grid should be easily accessible. In the design shown inFIG. 3the terminals are divided into two branches that connect to four vertical metal tracks, for easy access. In particular, terminals146and156that are connected to the logic cell outputs46and56respectively, are preferably placed at the top of the terminal structure and on two separate branches, to allow maximum flexibility and minimum interference in connecting the output signals to the interconnect grid (not shown). Extra vias connected to underlying signal lines are preferably placed within the cell terminal area, for easy connection between adjacent cells without utilizing too many metal routing tracks, in order to avoid signal traffic congestion in the configuring metal layer shown inFIGS. 3,4A &4B.

Furthermore, terminal156is preferably placed in proximity to terminal131, to provide feedback from output56of the logic cell ofFIG. 1to the input31of the NAND gate30of the same cell, enabling efficient implementation of a sequential flip-flop. While some terminals (such as terminals106,108,126and156) are duplicated for easy access, this duplication should be minimized so as to minimize area consumption and unnecessary interference with underlying routing tracks (not shown). Connections between duplicated terminals are performed in the underlying metal layers of the device.

The segments102that form the contacts between the terminals may be applied in various ways. In one preferred embodiment these segments may be removable links. In this case, the links are pre-deposited, connecting all terminals together as shown in FIG.3. In the configuration step the links are broken, e.g. by pulsed laser radiation, or by patterning the top metal and etching away all the undesirable links.

In another preferred embodiment, the top metal may be a blanket metal that connects all the vias101together. In this embodiment the blanket metal may be patterned by standard micro-lithography using a mask with the desired connection pattern. After patterning and etching preferably only the connections between the desired vias and between the vias and other signal lines are left in the top metal layer.

In yet another embodiment the segments102may be “make-link” segments. In this embodiment, shown inFIG. 5, the metal is produced and patterned without any of the segments102in place. Instead, “make-link” sites104are disposed in all locations where it may be desired to form links. In the configuration step the links are made selectively by either one of the linking technologies known in the art e.g. by local metal deposition, by laser induced linking, or by electric field induced linking.

In yet another preferred embodiment, the vias101themselves may be configurable. In this embodiment, in the configuration step, both the upper via layer and the top metal layer are patterned and etched by standard lithographic techniques. This embodiment requires two application specific lithographic masks for configuration (e.g. a via mask and a top-metal layer mask). Considering simplicity, speed of configuration and cost of configuration, configuring the upper via and any additional layer besides the top metal is inferior to top-metal-only configuration as in the previously described embodiments.

However, when other layers besides the top metal layer participate in the configuration step, enhanced device density may be achieved, since only the necessary vias are deposited and additional metal signal lines can now be provided in the area that was otherwise occupied by unnecessary or unused via terminals.

In yet another preferred embodiment, the configurable metal layer need not be the top metal layer. Rather, one of the intermediate metal layers of the multi-metal layer device may be chosen for configuring the cells. The advantage of using an intermediate metal layer for configuration is that the configuring layer can be accessed from both metal layers above it and below it, allowing a higher level of flexibility and connectivity in the routing process. In this case the terminals shown inFIGS. 3 & 5will still be connected to vias, but these vias may lead to either a metal layer above the configuring layer or to a metal layer underneath it. When the configuration step is carried out by using standard photolithography followed by metal etching, the ability to configure the device by modifying the layout of only a single metal layer provides significant savings in photolithographic mask costs.

In particular, the configuring layer may be the lowest metal layer of the device, lying just over the metal layer used to implement the circuit elements of the logic cell. This has the added advantage of minimizing the length of stacked vias that may be necessary in order to connect the cell inputs and outputs to its terminals in the configuring layer. This helps to reduce resistivity, improve device speed and reliability and minimize interference with the metal interconnection grid.

In gate array structures the logic cells and the overlying metal structure are tiled and repeated over a large area, a portion of such area shown schematically in FIG.6. However, the repetitive structure of the logic cells may cover only a portion of the total device. Other elements such as I/O cells, memory cells, inverters, analogue structures, busses and other special designs for implementing interfaces with other components and implementing intellectual property blocks may co-exist with the tiled logic array structure.

Reference is now made toFIG. 7, which illustrates a logic cell201constructed and operative in accordance with a preferred embodiment of the present invention. The unit logic cell comprises multiple circuit elements, generally similar to those illustrated in U.S. Pat. No. 5,684,412, but with a major distinction that the various elements are not fixedly connected to each other. Rather, the connections between the elements can be reconfigured, as will be described below. As distinct from the single unit logic cell1ofFIG. 1described hereinabove, the logic cell201ofFIG. 7is preferably constructed of a pair of identical logic portions203and205which are preferably located on opposite sides of a driver portion207, which preferably includes a first driver209having an input241and an output242and second driver211having an input243and an output244.

Logic portion203preferably comprises a first multiplexer212, having first and second inputs213and214, a select input215and an output216, while identical logic portion205preferably comprises a second multiplexer222having first and second inputs223and224, a select input225and an output226.

Logic portion203also preferably comprises a first NAND gate230having inputs231and232and an output233, while identical logic portion205preferably comprises a second NAND gate234, having inputs235and236and an output237.

Logic portion203also preferably comprises a first inverter238having an input245and an output246, while identical logic portion205preferably comprises a second inverter239, having an input247and an output248.

It is a particular feature of the invention exemplified inFIG. 7that each input and each output of each element therein may be connected to any other input or output of any other element of the same or a different cell, preferably at the same metal layer.

Reference is now made toFIG. 8A, which shows one flip-flop configuration of the cell of FIG.7. It is seen that input213of multiplexer212is designated as a data input D. The select inputs215and225of respective multiplexers212and222are interconnected and designated as clock inputs CP. Inputs232and235of respective NAND gates230and234are interconnected and designated as clear inputs CLN.

The output216of multiplexer212is connected to input231of NAND gate230. The output246of inverter238is connected to input214of multiplexer212. The output233of NAND gate230is connected to the input245of inverter238and to input223of multiplexer222. The output226of multiplexer222is connected to the input247of inverter239. The output248of inverter239is connected to input236of NAND gate234.

The output237of NAND gate234is connected to input224of multiplexer222and defines the output OUT of the data flip flop defined by the structure of FIG.8A.

Reference is now made toFIG. 8B, which shows another flip-flop configuration of the cell ofFIG. 7, characterized in that it employs a driver having higher current capacity than that employed in the embodiment of FIG.8A. It is seen that as in the embodiment ofFIG. 8A, input213of multiplexer212is designated as a data input D. The select inputs215and225of respective multiplexers212and222are interconnected and designated as clock inputs CP. Inputs232and235of respective NAND gates230and234are interconnected and designated as clear inputs CLN.

As distinct from the embodiment ofFIG. 8A, here output237of NAND gate234, connected to input224of multiplexer222, is also connected to the input243of driver211, whose output244defines the output OUT of the data flip flop defined by the structure of FIG.8B.

Reference is now made toFIG. 8C, which shows yet other flip-flop configuration of the cell ofFIG. 7characterized in that it employs a driver having even higher current capacity than that employed in the embodiment of FIG.8B. It is seen that as in the embodiment ofFIGS. 8A and 8B, input213of multiplexer212is designated as a data input D. The select inputs215and225of respective multiplexers212and222are interconnected and designated as clock inputs CP. Inputs232and235of respective NAND gates230and234are interconnected and designated as clear inputs CLN.

The output216of multiplexer212is connected to input231or NAND gate230. The output246of inverter238is connected to input214of multiplexer212. The output233of NAND gate230is connected to the input245of inverter238and to input223of multiplexer222. The output226of multiplexer222is connected to the input247of inverter239. The output248of inverter239is connected to input236of NAND gate234.

As distinct from the embodiment ofFIG. 8B, here output237of NAND gate234, connected to input224of multiplexer222, is also connected to the inputs241and243of respective drivers209and211, whose respective outputs242and244are connected to each other and together define the output OUT of the data flip flop defined by the structure of FIG.8C.

Reference is now made toFIG. 9A, which shows one XOR—XOR configuration of the cell ofFIG. 7, wherein logic portions203and205each define a XOR circuit It is seen that the input213of multiplexer212and the input245of inverter238are interconnected and designated as a data input A1. The select input215of multiplexer212is designated as a data input B1. The output246of inverter238is connected to input214of multiplexer212. The output216of multiplexer212defines the output OUT1of a first XOR circuit defined by the structure of FIG.9A.

Input224of multiplexer222and the input247of inverter239are interconnected and designated as a data input A2. The select input225of multiplexer222is designated as a data input B2. The output248of inverter239is connected to input223of multiplexer222. The output226of multiplexer222defines the output OUT2of another XOR circuit defined by the structure of FIG.9A.

Reference is now made toFIG. 9B, which shows a XNOR-XOR configuration of the cell ofFIG. 7, wherein logic elements203and205respectively define a XNOR circuit and an XOR circuit and characterized in that the XNOR circuit employs a driver having higher current capacity than that employed in the embodiment of FIG.9A. It is seen that as in the embodiment ofFIG. 9A, the input213of multiplexer212and the input245of inverter238are interconnected and designated as a data input A1. The select input215of multiplexer212is designated as data input B1. The output246of inverter238is connected to input214of multiplexer212.

As distinct from the embodiment ofFIG. 9A, here output216of multiplexer212is connected to the input241of driver209, whose output242defines the output OUT1of a XNOR circuit defined by the structure of FIG.9B.

It is also seen that as in the embodiment ofFIG. 9A, input224of multiplexer222and the input247of inverter239are interconnected and designated as a data input A2. The select input225of multiplexer222is designated as a data input B2. The output248of inverter239is connected to input223of multiplexer222. Output226of multiplexer222defines the output OUT2of a XOR circuit defined by the structure of FIG.9B.

Reference is now made toFIG. 9C, which shows a XNOR—XNOR configuration of the cell ofFIG. 7in which logic elements203and205are both XNOR circuits and also characterized in that the XNOR circuit defined by element203employs a driver having higher current capacity than that employed in the embodiment of FIG.9B. It is seen that as in embodiment ofFIG. 9B, input213of multiplexer212and the input245of inverter238are interconnected and designated as a data input A1. The select input215of multiplexer212is designated as a data input B1. The output246of inverter238is connected to input214of multiplexer212. Output216of multiplexer212is connected to the input241of driver209, whose output242defines the output OUT1of a first XNOR circuit defined by the structure of FIG.9C.

Input224of multiplexer222and input247of inverter239are interconnected and designated as a data input A2. The select input225of multiplexer222is designated as a data input B2. The output248of inverter239is connected to input223of multiplexer222.

As distinct from the embodiment ofFIG. 9B, here output226of multiplexer222is connected to the input243of driver211, whose output244defines the output OUT2of a second XNOR circuit defined by the structure of FIG.9C.

Reference is now made toFIG. 9D, which shows another XNOR-XOR configuration of the cell ofFIG. 7wherein logic element203is a XNOR circuit and logic element205is a XOR circuit and characterized in that the XNOR circuit employs a driver having even higher current capacity than that employed in the embodiment of FIG.9B. It is seen that as in the embodiment ofFIG. 9B, input213of multiplexer212and input245of inverter238are interconnected and designated as a data input A1. The select input215of multiplexer212is designated as a data input B1. The output246of inverter238is connected to input214of multiplexer212.

As distinct from the embodiment ofFIG. 9B, here output216of multiplexer212is connected to the inputs241and243of respective drivers209and211, whose outputs242and244are connected to each other and together define an output OUT1of a XNOR circuit defined by output OUT2of a XOR circuit defined by the structure of FIG.9D.

It is also seen that as in embodiment ofFIG. 9B, input224of multiplexer222and input247of inverter239are interconnected and designated as a data input A2. The select input225of multiplexer222is designated as a data input B2. The output248of inverter239is connected to the input223of multiplexer222. Output226of multiplexer222defines an output OUT2of a XOR circuit defined by the structure of FIG.9D.

Reference is now made toFIGS. 10,11A-11C and12A-12D, which show a preferred interconnection structure useful in the configuration and customization of the cell structure of FIG.7. It is appreciated that the connections between the elements of a logic cell for configuring the cell to perform one or more independent logic functions can be realized in several ways. Generally the implementation of the elements of the logic cell shown inFIG. 7is performed in the bottom layers of the microelectronic device (generally at the semiconductor level, the gate level and at the first metal layer). It may, however, be desirable to implement the connections that select the configuration of the cell in the top metal layer. This involves minimum cost and effort when bug fixes or device iterations are required, as only one photolithographic mask must be re-made and only one metal layer must be re-processed.

In one preferred embodiment the connections shown inFIGS. 8A-8Cand9A-9D may take the form of metal bridges between terminals located at the top metal layer. These terminals may be connected to metal segments at the bottom of the device that form the inputs and outputs shown schematically in FIG.7.

The connections between the top layer terminals and the bottom metal inputs and outputs may be realized by standard microfabrication techniques known in the art, such as stacked vias or a cascade of vias extending through the dielectric layers of the multi-layer device and being connected by metal connecting segments in the various metal layers (not shown).

FIG. 10shows a section of the top metal layer, which constitutes one preferable interconnection arrangement for configuring the logic cell of FIG.10. The interconnection arrangement also carries input and output signals to and from the cell, and may be used for programming the functionality of the logic cell.FIG. 7shows a top metal layer301having segments302that operate as removable links or as connectable links. Vias304are also shown. The vias connect the top metal layer301to underlying metal layers (not shown) and also connected to logic cell inputs/outputs370,372,374,376,378,380,382and384. Specifically, all the inputs and outputs identified by reference numerals inFIG. 7preferably are connected to corresponding terminals in the top metal layer, which are identified inFIG. 10by corresponding reference numerals incremented by 100. In addition, reference numerals354and356inFIG. 10indicate terminals connected by vias to the Vss potential (logic 0) and Vdd potential (logic 1), respectively.

Reference is now made toFIG. 11Awhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.8A. InFIG. 11A, a connection401is defined between a terminal314and a terminal346; a connection403is defined between a terminal331and a terminal316; a connection405is defined between a terminal323and a terminal333; a connection407is defined between a terminal348and a terminal336; a connection409is defined between a terminal326and a terminal347; a connection411is defined between a terminal337and a terminal324and a connection413is defined between another terminal333and a terminal345.

Connections are defined between a logic input370and a terminal315; between a logic input378and a terminal313; between a logic input380and a terminal332; between a terminal337and a logic output382; between a logic input384and a terminal335and between a logic input376and a terminal325.

Reference is now made toFIG. 11Bwhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.8B. InFIG. 11B, similarly toFIG. 11A, a connection401is defined between a terminal314and a terminal346; a connection403is defined between a terminal331and a terminal316; a connection405is defined between a terminal323and a terminal333; a connection407is defined between a terminal348and a terminal336; a connection409is defined between a terminal326and a terminal347; a connection411is defined between a terminal337and a terminal324and a connection413is defined between another terminal333and a terminal345. Connections are defined between a logic input370and a terminal315; between a logic input378and a terminal313; between a logic input380and a terminal332; between a logic input384and a terminal335and between a logic input376and a terminal325.

In contrast to that shown inFIG. 11A, the connection between a terminal337and a logic output382is replaced by a connection415between a terminal337and a terminal343and by a connection between a terminal344and a logic output382.

Reference is now made toFIG. 11Cwhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.8C. InFIG. 11C, similarly toFIG. 11B, a connection401is defined between a terminal314and a terminal346; a connection403is defined between a terminal331and a terminal316; a connection405is defined between a terminal323and a terminal333; a connection407is defined between a terminal348and a terminal336; a connection409is defined between a terminal326and a terminal347; a connection411is defined between a terminal337and a terminal324and a connection413is defined between another terminal333and a terminal345. Connections are defined between a logic input370and a terminable315; between a logic input378and a terminal313; between a logic input380and a terminal332; between a logic input384and a terminal335and between a logic input376and a terminal325. A connection415is defined between a terminal337and a terminal343and a connection is defined between a terminal344and a logic output382.

In contrast to that shown inFIG. 11B, an additional connection417is defined between a terminal342and another terminal344and an additional connection419is defined between another terminal341and a terminal343.

Reference is now made toFIG. 12Awhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.9A. InFIG. 12A, a connection501is defined between a terminal314and a terminal346; a connection503is defined between a terminal345and a terminal333; a connection505is defined between a terminal313and a terminal333; a connection507is defined between a terminal343and a terminal356; a connection509is defined between a terminal356and a terminal341; a connection511is defined between a terminal348and a terminal323; a connection513is defined between a terminal347and a terminal337and a connection515is defined between terminal337and a terminal345.

Connections are defined between a logic input370and a teal315; between a logic input378and a terminal313; between a terminal316and a logic output380and; between a terminal326and a logic output382; between a logic input384and a terminal324and between a logic input376and a terminal325.

Reference is now made toFIG. 12Bwhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.9B. InFIG. 12B, similarly toFIG. 12A, a connection501is defined between a terminal314and a terminal346; a connection503is defined between a terminal345and a terminal333; a connection505is defined between a terminal313and a terminal333; a connection507is defined between a terminal343and a terminal356; a connection511is defined between a terminal348and a terminal323; a connection513is defined between a terminal347and a terminal337and a connection515is defined between terminal337and a terminal345.

Connections are defined between a logic input370and a terminal315; between a logic input378and a terminal313; between a terminal326and a logic output382; between a logic input384and a terminal324and between a logic input376and a terminal325.

In contrast to that shown inFIG. 12A, the connection509between a terminal356and a terminal341is eliminated and the connection between terminal316and logic output380is replaced by a connection517between a terminal316and a terminal341and by a connection between a terminal342and a logic output380.

Reference is now made toFIG. 12Cwhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.9C. InFIG. 12C, similarly toFIG. 12B, a connection501is defined between a terminal314and a terminal346; a connection503is defined between a terminal345and a terminal333; a connection505is defined between a terminal313and a terminal333; a connection511is defined between a terminal348and a terminal323; a connection513is defined between a terminal347and a terminal337and a connection515is defined between terminal337and a terminal345. Connections are defined between a logic input370and a terminal315; between a logic input378and a terminal313; between a logic input384and a terminal324and between a logic input376and a terminal325. A connection517is defined between a terminal316and a terminal341and a connection is defined between a terminal342and a logic output380.

In contrast to that shown inFIG. 12B, connection507between terminal343and terminal356is eliminated and the connection between terminal326and logic output382is replaced by a connection519between terminal326and a terminal343and by a connection between a terminal344and logic output382.

Reference is now made toFIG. 12Dwhich is a simplified illustration of a preferred customization of the structure ofFIG. 10for implementing the cell configuration of FIG.9D. InFIG. 12D, similarly toFIG. 12B, a connection501is defined between a terminal314and a terminal346; a connection503is defined between a terminal345and a terminal333; a connection505is defined between a terminal313and a terminal333; a connection511is defined between a terminal348and a terminal323; a connection513is defined between a terminal347and a terminal337and a connection515is defined between terminal337and a terminal345. Connections are defined between a logic input370and a terminal315; between a logic input378and a terminal313; between a terminal326and a logic output382; between a logic input384and a terminal324and between a logic input376and a terminal325. A connection517is defined between a terminal316and a terminal341and a connection is defined between a terminal342and a logic output380.

In contrast to that shown inFIG. 12B, connection507between terminal343and terminal356is replaced by a connection521between terminal343and another terminal341and by a connection523between another terminal342and a terminal344.

Reference is now made toFIG. 13which illustrates in a simplified schematic form, a plurality of logic cells201arranged together in an array.

Reference is now made toFIG. 14, which corresponds to FIG.13and shows the layouts301of a plurality of logic cells201arranged together in an array.

In gate array structures the logic cells and the overlying metal structure are tiled and repeated over a large area, a portion of such area shown schematically in FIG.6. However, the repetitive structure of the logic cells may cover only a portion of the total device. Other elements such as I/O cells, memory cells, inverters, analogue structures, busses and other special designs for implementing interfaces with other components and implementing intellectual property blocks may co-exist with the tiled logic array structure.

It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. The present invention includes combinations and subcombinations of the embodiments described hereinabove as well as modifications and variations thereof which would occur to a person of skill in the art upon reading the foregoing description and which are not in the prior art.