Method for testing nonlinearity error of high speed digital-to-analog converter

A novel method applies the down-conversion sampling technology to test a high-speed digital-to-analog conversion. In the method, a digital-to-analog conversion output signal of a high-speed digital-to-analog converter and a low-frequency sinusoidal carrier wave signal input to a comparator to obtain a low-speed pulse signal. Therefore, the variation of the pulse width of the low-speed pulse signal can be measured by a common logic analyzer to assess the nonlinearity error of the high-speed digital-to-analog converter.

FIELD OF THE INVENTION

The present invention relates to a method for testing a digital-to analog converter, particularly to a method for testing the nonlinearity error of a high-speed digital-to-analog converter.

BACKGROUND OF THE INVENTION

The high-speed digital-to-analog (D/A) converter has been extensively applied to consumer electronics and communication technology. Refer toFIG. 1. In the conventional test method for the D/A converter (DAC)1, a precision analog signal measurement circuit3containing a sample-hold circuit4is arranged in the output2of the D/A converter1. The performance, especially the accuracy and stability, of the sample-hold circuit4directly influences the correctness of the measurement results. However, the design for a high-speed or high-resolution hold-sample circuit is hard to realize.

The tested signals are usually converted into special test eigenvalues to facilitate analysis. The test eigenvalues are converted into the frequency or the duty ratio of pulse signals, whereby the digital counting signals can be used to measure analog signals. However, the abovementioned technology needs a high-speed circuit to match the high-speed DAC, which greatly increases the difficulty of design.

SUMMARY OF THE INVENTION

The primary objective of the present invention is to develop a novel DAC test architecture according to the down-conversion sampling technology, whereby the analog signals of a digital-to-analog converter (DAC) is converted into a series of low-speed pulse stream, and whereby the nonlinearity error of DAC is worked out from the width of the pulse signals.

To achieve the abovementioned objective, the method of the present invention comprises steps: obtaining a digital-to-analog conversion output signal from a high-speed DAC; providing a low-frequency carrier wave signal; providing a comparator, and inputting the digital-to-analog conversion output signal and the low-frequency carrier wave signal into the comparator to obtain a low-speed pulse signal; using a logic analyzer to measure the variation of the pulse width of the low-speed pulse signal; working out the nonlinearity error of the high-speed DAC from the variation of the pulse width.

Thus, the present invention does not adopt a high-speed circuit but uses a common logic analyzer to assess the nonlinearity error of a high-speed DAC. Therefore, the present invention can promote the capability of ATE (Automatic Test Equipment) in testing a high-speed DAC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments are described in detail in cooperation with the drawings to demonstrate the technical contents of the present invention.

Refer toFIG. 2andFIG. 3for the sampling theorem of the present invention. Suppose that f(ωt) is the waveform output by a digital-to-analog converter (DAC)10and that the waveform has a period of T. Three sampling points p1, p2and p3, which are originally sampled from a single cycle, are respectively arranged in three different cycles. Respectively define the time difference and voltage difference of a first sampling point and a second sampling point to be ΔWiand ΔVi. Thus, ΔWi=Wi−T. The nonlinearity error of the tested circuit f(ωt)/dt can express the signal difference of the sampling points as the pulse width signal, i.e. the variation of the pulse width ΔWi.

Refer toFIG. 3for the sampling circuit according to the present invention. InFIG. 3, f(ωt) is the digital-to-analog conversion output signal of the DAC10. The digital-to-analog conversion output signal passes through a low-pass filter11, and the low-pass filter11filters out the high-frequency noise of the digital-to-analog conversion output signal. A carrier wave generator30generates a carrier wave signal f(ω′t)31having a frequency slightly lower that of f(ωt). The two signals of f(ωt) and f(ω′t) are sent to a comparator20for comparison, and the comparator20outputs a pulse signal s(t) to a register40, and the register40outputs a low-speed pulse signal w(t). The low-speed pulse signal w(t) reflects the nonlinearity error of the output of the DAC10. Therefore, the present invention needn't measure a high-speed analog signal with a high-speed or high-resolution measurement circuit but can measure the low-speed pulse signal w(t) with a logic analyzer (not shown in the drawings).

As Wicorresponds to the difference of two sampling points, the offset error of the comparator20is neutralized naturally. The method of the present invention works in a low-speed sampling mode, and only a sampling point is taken in each cycle. Thus, the circuit operates in a very low working frequency. Therefore, the required circuit is easy to realize. Further, the final test eigenvalues are the pulse widths of digital signals, which are less likely to distort when transmitted to the outside of the chip. Besides, the oscilloscope of the existing ATE has superior time-domain sampling capability to achieve high precision in measuring the pulse width of signals. Considering the influence of noise on the pulse width during modulation, the duration of the test is prolonged to repeat the same sampling activities in the same positions and obtain an average of the pulse widths. Thus is reduced the influence of noise.

Refer toFIGS. 4A-4CandFIG. 5. In the present invention, a triangular wave or a sinusoidal wave may be used as the low-frequency carrier wave signal31. In the case of a triangular wave, the relationship of the period Tcof the low-frequency carrier signal31and the period Tdaof the tested signal12(i.e. the digital-to-analog conversion output signal) is Tc=Tda+ΔT, wherein ΔT is the difference of the period Tcof the low-frequency carrier signal31and the period Tdaof the tested signal12. The relationship between the slopes of the low-frequency carrier signal31and tested signal12is expressed by

Suppose the tested circuit (the DAC10) is an n-bit element having (2n−1) quantization partitions and has N pieces of test eigenvalues W, respectively sampled from (N+1) signal cycles. In advance should be determined the cycle difference ΔT of the tested signal12and the carrier wave signal31and the relationship of the bit number n of the tested circuit and the period Tdaof the tested signal12before determining the frequency of the carrier wave signal31used in modulation. Suppose that N sampling points is needed. Thus, (N+0.5) cycles are needed in obtaining the eigenvalues Wi, wherein i=1, 2, 3, . . . , N.

Thus, the working frequency of the low-frequency carrier wave signal31should be obtained. Refer toFIG. 6. In this case, the total sampling time is denoted by ΣT, and ΣT has to meet the following equations:

Refer toFIG. 7AandFIG. 7Bfor the relationship of the test eigenvalues and the nonlinearity error of the tested circuit. Suppose that the tested circuit has a nonlinearity error in a specified quantization partition and that the nonlinearity error results in a slope variation Δw in a segment of the tested signal, as shown inFIG. 7A.FIG. 7Bis a partially enlarged view ofFIG. 7A. The error-induced slope variation has the following relationships:

From the abovementioned equation, it is known that Wjrepresents the pulse width modulation signal. Thereby, the nonlinearity error can be deduced from the pulse width, which is the result of the comparison of the low-frequency carrier wave signal31and the tested signal12.

Refer toFIG. 8, wherein a sinusoidal wave is used as a low-frequency carrier wave signal32. In the practical test environment, a precision and adjustable triangular wave generator is harder to realize. A sinusoidal signal can be generated much more easily than a triangular wave. However, the modulation does not resorted to an instinctive linear manner when a sinusoidal wave is used as the low-frequency carrier wave signal32. Thus, it is necessary to find out the relationship between the tested signal12and the modulated test eigenvalues.

Firstly, the low-frequency carrier wave signal32can be imagined to be a combination of piecewise linear slopes because the sampling points amount to a considerable number. In other words, the signal difference between two adjacent sampling points is very small. The voltage signals of two adjacent sampling points are supposed to have a linear relationship. However, the sampling points in different intervals have different linear relationships. Besides, the peak or trough of a sinusoidal signal is unsuitable to be the low-frequency carrier wave signal32because the slope variation thereof is too great. Therefore, the sinusoidal signal Vcshould be slightly greater than the tested signal Vdalest the sampling points in the overlap regions of the two signals appear in the nearby of the peak or trough.

Therefore, the equation is rearranged into

Refer toFIG. 9. The abovementioned mc[i] can be further expressed by

Refer toFIG. 10andFIG. 11. Then, express the test eigenvalue Wiin a similar form, and deduce the period difference ΔT of the tested signal12and the low-frequency carrier wave signal32to determine the frequency of the carrier wave signal used in modulation.

As the sampling points amount to a considerable number, i.e. the difference between two adjacent sampling points is very small, the voltage signals of two adjacent sampling points are supposed to have a linear relationship. However, the sampling points in different intervals have different linear relationships. Thus, Equation (1) is slightly modified as follows:

Refer toFIG. 12AandFIG. 12B. Similarly, Equation (2) is also slightly modified. Suppose that a nonlinearity error exists in a quantization partition of the tested circuit and causes a slope variation Δw in a small segment. The slope variation Δw is modified as follows:

The present invention works out the relationship of the pulse width modulation and the nonlinearity error of the signal output by the DAC10. In order to decrease the assessment error, the sampling points are increased instinctively. Such a measure can be easily realized via increasing the working frequency of the low-frequency carrier wave signal32. Suppose that there is an 8-bit DAC having 255 quantization levels, and that 1020 points are sampled therefrom. Thus, each quantization level is sampled four times averagely, and the original 255 quantization levels will be worked out from the 1020 sampling points.

Refer toFIG. 3,FIG. 13AandFIG. 13B. Suppose that the DAC10is an ideal converter, and that each quantization level has the same number of sampling points. In such a case, the slope mfcan be obtained from the slope average miof each two adjacent points, wherein i=1, . . . , 4. Unfortunately, the quantization levels of the DAC10are non-ideal in fact, and the sampling points are not all identical, as shown inFIG. 13B. It can be found inFIG. 13Bthat there is a slope inflection m4between the third and fourth sampling points. Therefore, in the calculation of mf1and mf2, m4should be taken into the average. Thus, the differential nonlinearity error (DNL) can be worked out from the following equations:

However, another case should be also taken in consideration. When m5>m4>m3, it means that the third sampling point is very close to the inflection point. In other words, slope m3is much smaller than slope m4. Thus, the average of m3and m4is almost equal to m4. Therefore, m4should not be taken into the calculation of mf1. Then, the equations should be modified as follows:

To demonstrate the DNL assessment, suppose that there are N sampling points. Refer toFIG. 14for the distribution of the slope between every two adjacent sampling points. Firstly, the position where the slope has the maximum value is found out to function as the beginning of each code. Then, calculate the slope average corresponding to the maximum value of the slopes.

When m5j>m3j>m4j, it is known from the preceding discussion that

For an n-bit DAC and N sampling points, the DLN assessment will be normalized as follows:

In the first situation, when (mk+1>mk+1−2>mmk+1−1),

In another situation, when (mk+1>mmk+1−1>mmk+1−2)

The integral nonlinearity error (INL) can be obtained via summing DNL and expressed by

Via the preceding equation, INL can be easily worked out from DNL. However, INL also incorporates the systematic errors of DNL.

In order to solve the problem, the source of the systematic errors should be found out, whereby the systematic errors can be separated from the real INL. The pulse width modulation itself has systematic errors because a sinusoidal carrier wave is regarded as the combination of piecewise linear slopes in assessing DNL. In fact, a sinusoidal carrier wave is not a combination of piecewise linear slopes but a combination of continuous curves. Thus, minor errors systematically exist between the real DNL and the assessed DNL. The systematic error appears and varies periodically with the frequency of the output of DAC. Thus, INL can be assessed via the following equations:

INLestimation⁡[i]=∑k=1i⁢⁢DNLestimation=∑k=1i⁢⁢[DNLreal⁡[k]+ɛ⁡(ω⁢⁢k)],
wherein ε(ωk) represents the systematic error of INL, and

From the viewpoint of signal, the INL signal can be regarded as the integral of DNLs, including the systematic errors of DNLs. The period of the signal output by DAC is very great. Because the frequency of the systematic error is much smaller than that of the DNL signal, the systematic error can be removed via a mere high-pass filter (HPF) to improve the accuracy of INL assessment. Thus, the equation for INL is slightly modified into

In conclusion, the present invention proposes a testing method to assess the non-ideal effect of a high-speed DAC. The method of the present invention applies the down-conversion sampling technology to realize a PWM (Pulse Width Modulation) signal, whereby the nonlinearity error of the tested circuit is converted into the variation of pulse width. Thus, the method of the present invention does not need a high-speed or high-definition device to capture analog signals.