Package structure with separated street between chips

A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.

BACKGROUND

Technical Field

The present disclosure relates to package technology. More particularly, the present disclosure relates to a package structure.

Description of Related Art

With development of technology, integrated circuits (ICs) have been applied to various fields, and various packaging methods also have been developed.

In some related arts, one or more individual chips are packaged into one package structure. For example, one or more chips belong to different wafers and are attached on a flexible print circuit board such that they are packaged into one package structure. Since these chips belong to the different wafers, two adjacent chips in the package structure are separated by a longer distance (for example, 6 mm to 10 mm) based on the packaging rule. In this situation, the size of the package structure is larger.

SUMMARY

Some aspects of the present disclosure are to provide a package structure. The package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.

DETAILED DESCRIPTION

The embodiments in the following descriptions are described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the disclosure covered by the present disclosure. The structure and operation are not intended to limit the execution order. Any structure regrouped by elements, which has an equal effect, is covered by the scope of the present disclosure. In addition, the drawings are merely for illustration and are not illustrated according original sizes. For ease of understanding, the same or similar components in the following descriptions will be described with the same symbols.

Reference is made toFIG. 1.FIG. 1is a schematic diagram illustrating an electrical system100according to some embodiments of the present disclosure. In some embodiments, the electrical system100is a display device and is configured for displaying an image.

The implementation of the electrical system100above is merely for illustration, and the present disclosure is not limited thereto. Various implementations of the electrical system100are within the contemplated scopes of the present disclosure. For example, the electrical system100may be an electrical system with other functions.

As illustrated inFIG. 1, the electrical system100includes a driver integrated circuit (IC)120, a power IC140, a timing controller160, and a display panel180. The diver IC120is attached on a flexible print circuit board190.

The power IC140is coupled to the diver IC120and configured to provide power to the diver IC120. In some embodiments, the power IC140includes a plurality of power sources to provide different power voltages to the diver IC120, in order to power on the diver IC120.

The timing controller160is coupled to the diver IC120and configured to control the diver IC120. In some embodiments, the timing controller160includes a plurality of signal sources to provide different control signals or display data to the diver IC120, in order to control the diver IC120.

The diver IC120is coupled to the display panel180and configured to drive the display panel180. In some embodiments, the driver IC120includes a plurality of driver chips to provide different driving signals or display data to the display panel180, in order to drive the display panel180to display the image. For example, the driver IC120may be a source driver, a gate driver, or a combination thereof.

In the present disclosure, “connected” or “coupled” may refer to “electrically connected” or “electrically coupled.” “Connected” or “coupled” may also refer to operations or actions between two or more elements.

In some embodiments, the electrical system100further includes a plurality of power lines L1, a plurality of signal lines L2, a plurality of pass lines L3, and a plurality of chip lines L4. The power lines L1, the signal lines L2, the pass lines L3, and the chip lines L4may be made by conductive segments.

As illustrated inFIG. 1, the power lines L1are coupled between the power IC140and the diver IC120. These power lines L1are configured to transmit power signals PS from the power source(s) in the power IC140to the diver IC120. Thus, the diver IC120can be powered on according to the received power signals PS.

The signal lines L2are coupled between the timing controller160and the diver IC120. The signal lines L2are configured to transmit differential signals DS from the signal source(s) in the timing controller160to the diver IC120. As described above, the differential signals DS may be the control signals or the display data. Thus, the diver IC120can be controlled to operate according to the received differential signals DS.

The pass lines L3are arranged on the flexible print circuit board190and are coupled between the display panel180and other circuits. The pass lines L3are configured to transmit pass line signals LS between the display panel180and these circuits without passing through the diver IC120. The pass line signals LS may be other signals.

The chip lines L4are coupled between the diver IC120and the display panel180. The chip lines L4are configured to transmit chip signals CS from the diver IC120to the display panel180. As described above, the chip signals CS may be the driving signals or the display data. Thus, the display panel180can be driven to display the image according to the received chip signals CS.

It is noted that the quantities of the power lines L1, the signal lines L2, the pass lines L3, and the chip lines L4inFIG. 1are merely for illustration, and the present disclosure is not limited thereto. Various quantities of the power lines L1, the signal lines L2, the pass lines L3, and the chip lines L4are within the contemplated scopes of the present disclosure.

Reference is made toFIG. 2.FIG. 2is a schematic diagram illustrating an IC on the flexible print circuit190board according to some embodiments of the present disclosure. As illustrated inFIG. 2, the IC on the flexible print circuit190is a driver IC120A, and the driver IC120A may be an example of the driver IC120inFIG. 1.

In some embodiments, the driver IC120A includes multiple chips that belong to a common wafer. As illustrated inFIG. 2, the driver IC120A includes a first chip1201and a second chip1202, and the first chip1201and the second chip1202belong to the common wafer.

It is noted that the quantity of the chips in the driver IC120A is merely for illustration, and the present disclosure is not limited thereto. Various quantities of the chips are within the contemplated scopes of the present disclosure.

The first chip1201is coupled to a plurality of first power lines L1aand a pair of first signal lines L2a. The first power lines L1aare disposed at two sides of the pair of first signal lines L2a. To be more specific, the pair of first signal lines L2aare disposed at the center of the first chip1201, some of the first power lines L1aare disposed at the right side of the pair of first signal lines L2a, and other are disposed at the left side of the pair of first signal lines L2a. Similarly, the second chip1202is coupled to a plurality of second power lines L1band a pair of second signal lines L2b. The second power lines L1bare disposed at two sides of the pair of second signal lines L2b. To be more specific, the pair of second signal lines L2bare disposed at the center of the second chip1202, some of the second power lines L1bare disposed at the right side of the pair of first signal lines L2b, and other are disposed at the left side of the pair of first signal lines L2b. Effectively, some of the first power lines L1aand some of the second power lines L1bare disposed in a space between the pair of first signal lines L2aand the pair of second signal lines L2b.

In addition, a plurality of pass lines L3aand L3bare disposed at two sides of the first chip1201and the second chip1202. To be more specific, the pass lines L3aare at the left side of the first chip1201and the pass lines L3bare disposed at the right side of the second chip1202. Explained in another way, the first chip1201, the second chip1202, the first power lines L1a, the second power lines L1b, the pair of first signal lines L2a, and the pair of second signal lines L2bare disposed in a space between the pass lines L3aand the pass lines L3b. The pass lines L3aand L3bare configured to transmit the pass line signals LS inFIG. 1without passing through the first chip1201and the second chip1202.

In some embodiments, the first chip1201and the second chip1202perform the same function. For example, both of the first chip1201and the second chip1202are source drivers and they are used to drive a display panel that has a larger size. In these embodiments, the channel number of the diver IC120A can be increased (for example, doubled).

In some other embodiments, the first chip1201and the second chip1202perform different functions. In these other embodiments, the diver IC120A can perform multiple functions and can be applied to more fields.

As described above, the first chip1201and the second chip1202belong to the common wafer. In other words, the first chip1201and the second chip1202belong to the same wafer. As illustrated inFIG. 2, the first chip1201and the second chip1202can be packaged into one package structure, and a separated street SS1is between the first chip1201and the second chip1202. In some embodiments, the separated street SS1is also referred as a scribing line. In general, when chips are designed on a wafer, the wafer will be divided into a plurality of regions by the scribing lines and the chips are arranged on the regions respectively. Then, a cutter is used to cut the regions along the scribing lines in order to form individual chips.

As illustrated inFIG. 2, the separated street SS1can be used for separating the first chip1201and the second chip1202, and the separated street SS1is disposed between one of the first power lines L1aand one of the second power lines L1B. To be more specific, the separated street SS1is disposed between the rightmost first power lines L1acoupled to the first chip1201and the leftmost second power lines L1bcoupled to the second chip1202.

However, in the present disclosure, the separated street SS1is not cut, and the first chip1201and the second chip1202are packaged into one package structure. For example, the first chip1201and the second chip1202can be packaged into a Chip-on-Film (CoF) package. Thus, the separated street SS1is a scribing line inside the package or a scribing line inside the driver IC120A.

In some embodiments, the separated street SS1is a blank area or an invalid circuit area. Explained in another way, with the configuration of the separated street SS1, the first chip1201is dependent from the second chip1202, or the first chip1201is electrically disconnected to the second chip1202. In this situation, the first chip1201would not affect operations of the second chip1202, and the second chip1202would not affect operations of the first chip1201.

In some related arts, one or more individual chips are packaged into one package structure. For example, one or more chips belong to different wafers and are attached on a flexible print circuit board such that they are packaged into one package structure. Since these chips belong to the different wafers, two adjacent chips in the package structure are separated by a longer distance (for example, 6 mm to 10 mm) based on the packaging rule. In this situation, the size of the package structure is larger.

Compared to these related arts, in the present disclosure, the separated street SS1between the first chip1201and the second chip1202that belong to the common wafer is not cut, and the first chip1201and the second chip1202are packaged into one package. Therefore, the size of the package can be reduced since the first chip1201and the second chip1202that belong to the common wafer are separated by a shorter distance. In some embodiments, a width of the separated street SS1is less than aforementioned 6 mm. In other words, the first chip1201and the second chip1202are separated by less than 6 mm. For example, the width of the separated street SS1can be substantially in a range of 70 μm to 90 μm. In addition, with this configuration, the design of the power plane and the design of circuits can be easier, and the driver IC120A can share masks with products with a single IC.

Reference is made toFIG. 3.FIG. 3is a schematic diagram illustrating an IC on the flexible print circuit board190according to some embodiments of the present disclosure. As illustrated inFIG. 3, the IC on the flexible print circuit190is a driver IC120B, and the driver IC120B may be an example of the driver IC120inFIG. 1.

Similar to the driver IC120A inFIG. 2, the driver IC120B inFIG. 3includes multiple chips that belong to a common wafer. As illustrated inFIG. 3, the driver IC120B includes a first chip1203and a second chip1204, and the first chip1203and the second chip1204belong to the common wafer.

It is noted that the quantity of the chips in the driver IC120B is merely for illustration, and the present disclosure is not limited thereto. Various quantities of the chips are within the contemplated scopes of the present disclosure.

The first chip1203is coupled to a plurality of first power lines L1cand a pair of first signal lines L2c. The pair of first signal lines L2care disposed at the edge of the first chip1203, and the first power lines L1care disposed at a side (for example, the left side) of the first signal line L2c. The second chip1204is coupled to a plurality of second power lines L1dand a pair of second signal lines L2d. The pair of second signal lines L2dare disposed at the edge of the second chip1204, and the second power lines L1dare disposed at a side (for example, the right side) of the second signal lines L2d. The pair of first signals line L2care adjacent to the pair of second signal lines L2d, and the pair of first signals line L2cand the pair of second signal lines L2dare disposed in a space between the first power lines L1cand the second power lines L1d.

In addition, a plurality of pass lines L3cand L3dare disposed at two sides of the first chip1203and the second chip1204. The configuration and operations of the pass lines L3cand L3dinFIG. 3are similar to the pass lines L3aand L3binFIG. 2, so they are not described herein again.

Similarly, the first chip1203and the second chip1204can perform the same function or perform different functions. Thus, the channel number of the diver IC120B can be increased (for example, doubled) or the diver IC120B can perform multiple functions.

As described above, the first chip1203and the second chip1204belong to the common wafer. In other words, the first chip1203and the second chip1204belong to the same wafer. As illustrated inFIG. 3, the first chip1203and the second chip1204are packaged into one package structure, and a separated street SS2is between the first chip1203and the second chip1204.

As illustrated inFIG. 3, the separated street SS2can be used for separating the first chip1203and the second chip1204, and the separated street SS2is disposed between one of the pair of the first signal lines L2cand one of the pair of the second signal lines L2d.

In the present disclosure, the separated street SS2is not cut, and the first chip1203and the second chip1204are packaged into one package structure. For example, the first chip1203and the second chip1204can be packaged into a Chip-on-Film (CoF) package. Thus, the separated street SS2is a scribing line inside the package or a scribing line inside the driver IC120B.

The functions of the separated street SS2inFIG. 3are similar to those of the separated street SS1inFIG. 2, so they are not described herein again.

Based on the descriptions above, in the present disclosure, the separated street between the first chip and the second chip that belong to the common wafer is not cut, and the first chip and the second chip are packaged into one package structure. Therefore, the size of the package can be reduced since the first chip and the second chip that belong to the common wafer are separated by a shorter distance.

Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, in some embodiments, the functional blocks will preferably be implemented through circuits (either dedicated circuits, or general purpose circuits, which operate under the control of one or more processors and coded instructions), which will typically comprise transistors or other circuit elements that are configured in such a way as to control the operation of the circuity in accordance with the functions and operations described herein. As will be further appreciated, the specific structure or interconnections of the circuit elements will typically be determined by a compiler, such as a register transfer language (RTL) compiler. RTL compilers operate upon scripts that closely resemble assembly language code, to compile the script into a form that is used for the layout or fabrication of the ultimate circuitry.