Thermal control of memory modules using proximity information

An information handling system includes a processor having access to a system memory. The system is operable to detect a thermal alert and identify an associated portion of system memory. The system may then modify memory allocation information used by an operating system to allocate system memory. When the thermal alert indicates a rising memory module temperature that exceeds a specified threshold, the modification of the memory allocation information causes the memory to appear to be more “distant” from the system processor(s) and thereby allocated less preferentially than other memory. If the temperature continues to rise beyond a higher threshold, a second modification of the memory allocation information is performed to simulate a “hot eject” of the memory module. As the memory module cools, the memory allocation information can be restored to simulate a hot add of the memory module and to restore the proximity of the memory module.

TECHNICAL FIELD

The present invention is related to the field of computer systems and, more particularly, thermal control in computer systems.

BACKGROUND OF THE INVENTION

One type of information handling system is a server, which is a processor-based network device that manages network resources. As examples, a file server is dedicated to storing files, a print server manages one or more printers, a network server manages network traffic, and a database server processes database queries. A Web server services Internet World Wide Web pages.

A server may be implemented as a “stand alone” or monolithic servers in which a single chassis contains a single set of processing resources and an associated set of I/O resources. A multiprocessor monolithic server may, for example, include two or more processors that share access to a common system memory and a common set of peripheral devices including persistent storage resources, network interface resources, graphical display resources, and so forth. In other implementations, some of the I/O resources available to the server are provided as external components. Persistent storage, for example, may be provided to a monolithic server as an external box.

In more recent years, servers have been implemented as “blade servers.” Blade servers are so named because they employ server blades, which are thin, modular electronic circuit boards containing one or more microprocessors, memory, and other server hardware and firmware. Blade servers, which are sometimes referred to as a high-density servers, typically include a space saving, rack-based chassis that accepts multiple server blades. Blade servers are often used in clusters of servers dedicated to a single task. For example, a blade server may function as a web server by servicing web-based requests addressed to one or more universal resource locators (URLs). In this implementation, the blade server may route individual requests to different server blades within the blade server based on factors including the current loading of individual blades and the locality of information required to respond to a request, all in a manner that is transparent to the user.

Power management and power conservation is an increasingly important consideration in the design and implementation of all information handling systems in general and server system especially. Power consumption is not only costly, but it also generates heat that must be dissipated to maintain performance parameters as well as the electrical and mechanical integrity of the server. Traditional thermal management efforts have tended to focus on techniques for performance “throttling” by, for example, slowing the speed of the system clock, reducing the number of instructions processed per unit of time interval, reducing the operating voltages, and so forth. While traditional thermal management techniques have utility, they tend to have a negative performance impact that is generally undesirable.

SUMMARY OF THE INVENTION

Therefore a opportunity exists for an information handling system operable to provide thermal management over at least some of its resources without a substantial performance impact. The present disclosure describes a system and method for thermal management of system memory resources by manipulating information used by the operating system in allocating memory to executing threads.

In one aspect, an information handling system as described includes at least one processor having access to a system memory. The system is operable to detect a thermal alert and identify a portion of system memory associated with the thermal alert. The system responds to the thermal alert by modifying memory allocation information used by an operating system to allocate system memory. When the thermal alert indicates a rising memory module temperature that exceeds a specified threshold, the modification of the memory allocation information causes the memory to appear to be more “distant” from the system processor(s). Distant memory is allocated less preferentially than “near” memory thereby resulting in the distant memory being used less than other memory. The reduced usage gives the distant memory an opportunity to recover thermally. If the temperature of the memory module continues to rise beyond a higher threshold, a second modification of the memory allocation information is performed that simulates a “hot eject” of the memory module. Hot ejecting a memory module eliminates that portion of system memory as memory that can be allocated by the operating system, thereby again giving the memory the opportunity to recover thermally.

Detecting the thermal alert may include detecting a signal issued by a thermal sensor located in proximity to a memory module where the identified portion of system memory corresponds to a portion of system memory contained in or otherwise implemented in the memory module. Modifying memory allocation information may include modifying memory affinity information, such as memory affinity information defined by the ACPI specification, to alter the perceived proximity of the identified portion of system memory.

The modification of memory affinity information may be combined with conventional performance throttling techniques in a tiered approach where, for example, performance throttling is attempted if the memory module temperature rises above a first threshold, perceived proximity is increased if the temperature rises above a higher threshold, and the hot eject is simulated if the temperature rises above a still higher threshold.

In another aspect, a disclosed method of implementing thermal control in an information handling system includes detecting a thermal alert indicative of a temperature of a memory module exceeding a specified threshold, identifying a portion of system memory address space associated with the memory module, and modifying memory allocation information associated with the identified portion of system memory address space. Modifying memory allocation information may include modifying memory allocation information used by an operating system to identify memory for allocating to a requesting thread. Modifying memory allocation information includes may also include increasing a perceived proximity between a processor of the information handling system and the identified portion of system memory address space.

In yet another aspect, a disclosed computer program product includes computer executable instructions, stored on a computer readable medium, for thermal control of a memory module, including instructions for detecting a thermal alert associated with the memory module, instructions for identifying a portion of system memory address space associated with the identified memory module; and instructions for modifying memory allocation information associated with the identified portion of system memory address space to reduce an operating system preference for allocating the identified portion of system memory address space.

The present disclosure includes a number of important technical advantages. One technical advantage is the ability to respond to increasing memory module temperatures with corrective action that does not have a direct impact on performance.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the invention and its advantages are best understood by reference to the drawings wherein like numbers refer to like and corresponding parts.

Preferred embodiments and their advantages are best understood by reference toFIG. 1throughFIG. 5, wherein like numbers are used to indicate like and corresponding parts. For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.

In one aspect, a system and method suitable for modifying or otherwise maintaining processor/memory affinity information in an information handling system as corrective action in response to a thermal warning or alert. Specifically, a system and method may include detecting a thermal warning or alert originating from or otherwise associated with a memory module, such as a dual in-line memory module (DIMM), that represents a distinct portion of system memory. The system and method may address the thermal warning or alert by modifying information, referred to herein generically as memory allocation information, that affects the manner in which an operating system allocates system memory. By modifying the allocation information, appropriately, the system and method make the “hot” memory appear undesirable to the operating system as an allocation target. Unless system memory resources are saturated, the operating system will respond to the modified allocation information by allocating system memory to other portions of system memory. As a result, the hot memory will be less utilized and the hot memory will, hopefully, begin to cool due to lack of activity.

In the preferred embodiment, the system and method the memory allocation information used to implement thermal control is memory affinity information of which the operating system is already aware. Although memory affinity information is typically designed for use in distributed memory systems where there are substantial differences in memory access times depending upon the processor requesting memory access and the memory to which the request is directed. In one embodiment of the present application, however, the memory affinity information is useful for thermal control even in a symmetrical architecture (i.e., an architecture in which memory access time is largely independent of the requesting processor and the memory access module.

Turning now toFIG. 1, selected elements of an embodiment of an information handling system100suitable for implementing a thermal control technique based on memory allocation is depicted. The depicted implementation is exemplary of a server class information handling system although the described thermal control methods are fully applicable to desktop, laptop, and hand held information handling systems. In server class implementations, the information system may be implemented as a monolithic or blade type server. Throughout this disclosure hyphenated reference numerals refer to instances of an element that is represented generically or collectively by the reference numeral without hyphenation. Thus, elements10-1and10-2, as examples, refer to first and second instances of an element10, which may be referred to generically or collectively as element(s)10.

In the depicted implementation, information handling system100includes one or more processors102-1through102-n (generically or collectively referred to herein as processor(s)102). Processors102are connected to a shared system bus106. Information handling system100as depicted includes a chip set110that includes a north bridge108and a south bridge120. North bridge chip108is operable as a memory controller that provides an interface between system bus106and a memory bus system memory104. In addition, the depicted embodiment of north bridge108is shown as providing an advanced graphics port (AGP) interconnect111that interfaces to a graphics controller112or other form of video controller.

South bridge120connects to north bridge108and provides peripheral busses including, in the depicted implementation, a PCI (Peripheral Components Interface) bus113, a USB (Universal Serial Bus)114and, an ISA (Industry Standard Architecture) or other form of legacy peripheral bus115. In the depicted embodiment, a network interface card or adapter (NIC)116and a disk controller117are connected to PCI bus113while a non volatile memory (NVM)118containing a BIOS119is connected to ISA bus118. NVM118may be implemented as a flash memory, a PROM (Programmable Read Only Memory), or other suitable form of non volatile, but preferably programmable storage.

Although the depicted implementation of information handling system100describes a specific architecture and set of components, other implementations are equally applicable. For example, although north and south bridge108and120are illustrated and described as being distinct elements, they may be integrated into a single piece of silicon or integrated within a single integrated circuit package. Similarly, although the depicted embodiment implements a memory controller in north bridge108, other embodiments may incorporate the memory controller function directly into processors102-1through102-N. In these embodiments, the AGP bus provided by north bridge108may be provided by south bridge120or the AGP bus may be replaced by another bus, an express PCI bus, for example, that is provided by South Bridge120.

FIG. 11depicts a non-uniform memory architecture (NUMA) embodiment of an information handling system1100. Information handling system1100is suitable for implementing thermal control methods described herein. NUMA information handling system1100includes nodes1101-1through1101-4interconnected via a NUMA interconnection1110. Each node1101includes processing and I/O resources represented by reference numeral1102and a local system memory1104. Local system memories1104, as suggested by their names, are portions of the information handling system memory that are local to or “close to” the processing and I/O resources of the node. Thus, for example, local system memory1104-1is local to processing/I/O resources1102-1, and so forth. All portions of system memory not local to a node are referred to as remote portions of system memory. For example, local system memories1104-2,1104-3, and1104-4are remote portions of system memory relative to first node1101-1. In a NUMA system such as NUMA information handling system1100, memory latency access time is a function of system memory address whereas, in a conventional uni-processor or symmetrical multiprocessor system, memory access time is substantially independent of system memory address. In NUMA system1100the access time for remote portions of system memory is significantly different (i.e., greater) than the access time for local system memory.

NUMA system1100as implemented inFIG. 11includes four nodes and two tiers of access times. The first tier access time is the access time associated with all local accesses to system memory. A local access is an access by a processing or I/O resource of a node to a portion of system memory that resides in the local system memory of that node. The second tier represents all accesses to remote memory. In this implementation, all remote accesses have a substantially uniform latency. In more complex implementations, a number of nodes may be substantially greater than four and the number of access time tiers may exceed two. For example, a system may employ an architecture in which two or more NUMA interconnect segments must be traversed to access a particular portion of system memory. The latency associated with accesses that must traverse multiple interconnect segments, sometimes referred to as “hops,” will be greater than the latency associated with a single hop.

Regardless of the complexity of a particular NUMA implementation, NUMA system1100preferably includes memory affinity information (MAI)125stored in a portion of the system memory. AlthoughFIG. 11depicts MAI125stored in local system memory1104-1, MAI125may be stored in any one or more of nodes1101. MAI125, as described in greater detail below, conveys information indicative of the memory architecture of the system. MAI125may include, for example, information indicating which system memory addresses are located on which nodes1101, and the relative “distances” between any pair of nodes. In this context, the “distance” between a pair of nodes may refer to the number of NUMA interconnect hops between the two nodes. In such embodiments, the MAI125may facilitate NUMA implementations by providing an operating system with information it can use to allocate memory accesses efficiently, e.g., by allocating processing threads to execute on a node where most of the system memory accesses executed by the thread are local accesses. In the context of thermal control techniques as described herein, thermal control techniques may leverage the presence of MAI125and extend the function of the MAI to encompass more than the physical architecture of the system. In any event,FIG. 1andFIG. 11depict different implementations of information handling systems suitable for employing thermal control techniques as described herein.

In one embodiment, BIOS119includes code that, among other things, generates memory allocation information125that is shown as being stored in system memory104, preferably in a portion of system memory125that is reserved for BIOS access. In one embodiment, memory allocation information125includes processor/affinity information, which may include, a static resource affinity table (SRAT)200and/or a system locality information table(SLIT)300as described in greater detail below with respect toFIG. 2andFIG. 3.

As used throughout this specification, memory allocation information refers to information used to control or otherwise affect that manner in which a processor allocates memory while affinity information refers to information indicating a proximity relationship between portions of system memory and processors of the system. Affinity information is generally used in multi-node server systems in which memory access is non-uniform. See, e.g., U.S. patent application of V. Nijhawan et al., entitled Modifying Node Descriptors to Reflect Memory Migration in an Information Handling System with Non-Uniform Memory Access, application Ser. No. 11/372,569 filed Mar. 10, 2006 (referred to hereinafter as the “Nijhawan application”). As disclosed herein, however, affinity information may be used to bias the operating system against allocating selected portions of system memory for purposes, including thermal recovery, that are unrelated to processor/memory proximity.

Some embodiments of memory allocation information125include processor/memory affinity information that is formatted in compliance with the Advanced Configuration and Power Interface (ACPI) standard. ACPI is an open specification that establishes industry standard interfaces for operating system directed configuration and power management on laptops, desktops, and servers. ACPI is fully described in theAdvanced Configuration and Power Interface Specificationrevision 3.0a (the ACPI specification) from the Advanced Configuration and Power Interface work group (www.ACPI.info). The ACPI specification and all previous revisions thereof is incorporated in its entirety by reference herein. Moreover, as subsequent ACPI Specifications are developed, those specifications are applicable herein as well.

ACPI includes, among other things, a specification of the manner in which memory affinity information is formatted. ACPI defines formats for two data structures that provide processor/memory affinity information. These data structures include a Static Resource Affinity Table (SRAT) and a System Locality Information Table (SLIT).

FIG. 2depicts a conceptual representation of an SRAT200, which includes a memory affinity data structure201. Memory affinity data structure201includes a plurality of entries202-1,202-2, etc. (generically or collectively referred to herein as entry/entries202). Each entry202includes values for various fields defined by the ACPI specification. More specifically, each entry202in memory affinity data structure201includes a value for a proximity domain field204and memory address range information206. In the case of a multi-node server, for example, the proximity domain field204contains a value that indicates the node on which the memory address range indicated by the memory address range information206is located. In the implementation depicted inFIG. 2, memory address range information206includes a base address low field208, a base address high field210, a low length field212, and a high length field214. Each of the fields208through214is a 4-byte field. The base address low field208and the base high field210together define a 64-bit base address for the relevant memory address range. The length fields212and214define a 64-bit memory address offset value that, when added to the base address, indicates the high end of the memory address range. Other implementations may define a memory address range differently (e.g., by indicating a base address and a high address explicitly) Memory affinity data structure201as shown inFIG. 2also includes a 4-byte field220that includes 32 bits of information suitable for describing characteristics of the corresponding memory address range. These characteristics include, but are not limited to, whether the corresponding memory address range is hot pluggable.

Referring now toFIG. 3, a conceptual representation of one embodiment of a SLIT300is depicted. In the depicted embodiment, SLIT300includes a matrix301having a plurality of rows302and an equal number of columns304. Each row302and each column304correspond to an object of $ server100. Under ACPI, the objects represented in SLIT matrix301include processors, memory controllers, and host bridges. Thus, the first row302may correspond to a particular processor in $ server100. The first column304would necessarily correspond to the same processor. The values in SLIT matrix301represent the relative $ distance between the locality object corresponding to the row and the locality object corresponding to the column. Data points along the diagonal of SLIT300represent the distance between a locality object and itself. The ACPI specification arbitrarily assigns a value of 10 to these diagonal entries in SLIT matrix301. The value 10 is sometimes referred to as the SMP distance. The values in all other entries of SLIT300represent the $ distance relative to the SMP distance. Thus, a value of 30 in SLIT300indicates that the $ distance between the corresponding pair of locality objects is approximately 3 times the SMP distance. The locality object information provided by SLIT300may be used by operating system software to facilitate efficient allocation of threads to processing resources.

Some embodiments of using memory allocation information to provide thermal control for system resources are implemented in whole or in part with a set of computer executable instructions (software) stored on a computer readable medium such as the system memory or a hard disk. When executed by a suitable processor, the instructions cause the computer to perform a thermal control function illustrated generically inFIG. 4and in additional detail according to one embodiment, inFIG. 6-9.

Turning now toFIG. 4, selected elements of an embodiment of a method400for providing thermal control for an element or resource of information handling system100are illustrated. In the illustrated embodiment, the element or resource to which thermal control is provided is system memory104. System memory104is likely implemented with two or more modular components frequently referred to as memory modules. Information handling system100may include a plurality of memory module components. These components may be implemented, for example, as Dual Inline Memory Modules (DIMMs) containing any suitable form of system memory including, as examples, double data rate (DDR) memory, double data rate 2 (DDR2) memory, and fully buffered DIMM (FBD) memory.

As depicted inFIG. 4, method400includes monitoring (block402) an information handling system for an interrupt, signal, or other form of information indicative of a thermal alert or warning associated with the system memory. Referring briefly toFIG. 5, an implementation of system memory104emphasizes the use of a plurality of memory modules130-1through130-N. Memory modules130as depicted inFIG. 5may represent DIMMs or another form of memory module suitable for use in a microprocessor-based information handling system. Each memory modules130as shown includes, in addition to its RAM (random access memory) devices (not shown explicitly), a thermal sensor132. Thus, for example, memory module130-1includes a corresponding thermal sensor132-1, memory module130-N includes a corresponding memory module132-N, and so forth. Although the thermal sensors132are indicated inFIG. 5as being “on” a memory module, specific implementations may also include the thermal sensors in close proximity, but not physically on, the corresponding memory module. Moreover, althoughFIG. 5illustrates a one-to-one correspondence between memory modules130and thermal sensors132, other embodiments may use fewer thermal sensors, e.g., a thermal sensor132associated with two or more adjacent memory modules130.

Returning now toFIG. 4, memory alert monitoring402may include information handling system100detecting a thermal alert associated with one or more memory modules130. In response to detecting the thermal alert in block402, the depicted embodiment of method400includes determining (block404) if one or more forms of performance throttling have been pursued. In this embodiment, performance throttling is a first option for responding to a thermal alert. In other embodiments, however, performance throttling may be designated as a secondary procedure that is not pursued memory allocation information125is modified as described herein.

In the depicted embodiment of method400, performance throttling406is pursued as a first technique for responding to thermal alert. Performance throttling406as represented inFIG. 4encompasses various performance throttling techniques known by those skilled in the field. Such techniques would include, frequency throttling, voltage scaling, and various forms of throttling processor performance by reducing the number of instructions processed per unit time.

If method400determines in block404that performance throttling has already been implemented in the information handling system, method400attempts to address the thermal alert by causing an operating system to reduce it preference for or usage of a portion of system memory that corresponds to a portion of system memory that is associated with the thermal alert. Accordingly, method400includes determining which portion of system memory is associated with an alert.

In the depicted embodiment of method400, determining which portion of system memory104is associated with an alert includes identifying (block406) a memory module130that is associated with the thermal sensor132that issued the alert. Memory modules130represent distinct portions of system memory104that are readily associated with thermal alerts triggered by thermal sensors132. In embodiments having a one-to-one correspondence between memory modules130and thermal sensors132, identifying the memory modules130associated with a thermal alert includes determining which thermal sensor132caused an alert and determining which memory module(s)130are associated with the determined thermal sensor132. Identifying the thermal sensor that issued an alert may be achieved by providing the identity of the thermal sensor as part of the thermal alert. If, for example, the thermal alert is an interrupt, the thermal alert preferably includes information identifying the thermal sensor132and the interrupt handler triggered by the alert may include identifying the memory module132associated with the identified thermal sensor.

After determining a memory module130or other portion of system memory104associated with a thermal alert, method400includes determining (block407) the portion of system memory corresponding to the identified memory module by identifying the range of system memory addresses associated with the identified memory module(s)130. Information handling system100preferably includes a table or mapping containing information regarding the range of system memory addresses corresponding to each memory module130. From this information, method400can associate a system memory address range associated with a thermal alert.

Method400as depicted includes modifying (block408) the perceived proximity of the range of system memory addresses identified in block407. By modifying the perceived proximity of a range of system memory addresses, method400provides a form of corrective action following a thermal alert associated with one or more memory modules130. Specifically, if the thermal alert indicates an over-temperature condition, the corrective action represented by block408includes increasing the perceived proximity of a system memory address range. The system memory address range for which perceived proximity is increased preferably corresponds precisely with the system memory addresses associated with the memory module130associated with the thermal alert.

In some cases, however, it is possible that the granularity and/or boundaries of system memory address ranges that may be modified using affinity information does not correspond precisely to the system memory address ranges corresponding to the physical memory modules130. In such cases, the modification of perceived proximity information in block408includes identifying the best fit between a range of system memory address space corresponding to a memory module130associated with a thermal alert and a range of system memory address space alterable through affinity information.

As indicated in the preceding paragraphs, thermal alerts may indicate an over temperature condition when a thermal sensor132senses a temperature exceeding some specified threshold. Thermal alerts may also indicate an under temperature condition, presumably occurring when a thermal sensor132that previously sensed an over temperature condition subsequently senses a reduced temperature that is below a specified threshold. To avoid excessive “thrashing” of the proximity information and the routines that adjust the information, preferred embodiments of information handling system100implement a buffer or hysteresis condition between a threshold in a rising temperature environment and a threshold in a decreased temperature (thermal recovery) environment. Moreover, some embodiments of method400implement two or more thresholds in each “direction,” namely, a two or more thresholds in a temperature increasing direction and two or more corresponding recover thresholds.

Referring toFIG. 6, a line graph600is depicted to emphasize a specification implementation of corrective action taken in response to thermal alerts according to one embodiment of information handling system100. As depicted inFIG. 6, line graph600includes seven specified temperature thresholds, identified as T0through T6. These thresholds include three pairs of thresholds for various stages of corrective action and an ultimate threshold associated with a shut down situation.

More specifically, as depicted inFIG. 6, the temperature thresholds T0and T1are associated with a first level of corrective action, T2and T3are associated with a second level of corrective action, and T4and T5are associated with a third level of corrective action. The levels of corrective action may include implementing performance throttling, modifying perceived proximity, and simulating a hot eject of a memory module. The ordering of these levels of corrective action are an implementation detail that may vary from implementation to implementation. Generally, it is preferable to perform hot eject simulation only after modifying perceived proximity information, but the performance throttling may be positioned anywhere in the ordering of corrective action.

The embodiment depicted inFIG. 6uses performance throttling as a first level of corrective action, proximity modification as a second level, and hot eject simulation as the third level. In this embodiment, T1represents a threshold for implementing the first level of corrective action—performance throttling—and T0represents a threshold for removing performance throttles. If a thermal sensor132senses a temperature exceeding threshold T1, one or more forms of performance throttling are initiated by information handling system100. As indicated previously, performance throttling may include any of various types of performance throttling, but, generally, performance throttling refers to techniques that attempt to reducing thermal overload by reducing the speed or amount of processing activity.

Following initiation of the first level of corrective action, the temperature sensed by one or more thermal sensors may continue to rise, remain static, or drop. If the temperature continues to rise to a temperature equal to or exceeding the temperature corresponding to threshold T3, a second level of corrective action—e.g., proximity modification—is initiated.

Proximity modification according to an embodiment of the information handling system that includes SLIT information as described above may include modifying the SLIT information to increase the perceived proximity of a particular portion of system memory. If, for example, a single temperature sensor132senses a temperature in excess of the T3threshold, information handling system100may increase the SLIT table value of the corresponding portion of system memory relative to all other portions of the system address range for all processors so that the “hot” portion of system memory address space is allocated less preferentially than all other portions. In this manner, a hot section of system memory will hopefully remain unallocated to any thread or process and thereby remain in a low power consumption state e.g., a standby or refresh-only state. Although a portion of system memory may be de-prioritized using memory affinity information as described, the portion of system memory is still, nevertheless, available for memory allocation. If the system memory is in very high demand, the operating system may be forced to allocate even those portions of system memory that appear to be distant. Presumably, however, the distant portions of system memory are among the last to be allocated and among the first to be de-allocated.

If the hot portion of memory remains in the unallocated state for a sufficient duration, it may cool sufficiently to a permit the temperature sensor to sense a temperature of less than the temperature indicated by threshold T2. A thermal alert may then be issued to indicate that the previous over-temperature condition has been resolved, at which point the proximity information may be restored or otherwise modified to bring the affected portion of system memory back to its original state, i.e., its original level of perceived proximity.

Following the second level of corrective action, the temperature of the hot portion of system memory could, once again, rise, remain static, or drop. If the temperature rises to temperature exceeding the temperature associated with threshold T5, a third level of corrective action is take. In one embodiment, the third level of corrective action may include simulating a hot eject of the memory module associated with the over temperature condition.

Commercially distributed operating systems, including ACPI-compliant operating systems, typically support hot adding and hot removing of memory modules. In information handling systems executing on such operating systems, as third level of corrective action might include configuring the system as if the memory module associated with the hot portion of system memory has been hot removed. Representing a memory module as having been hot ejected entirely prevents the operating system from allocating any activity to the module. Thus, this third level of corrective action is analogous to the second level, but makes the system memory portion entirely unavailable for allocation and, preferably, places the portion of system memory into a low power or no power state thereby accelerating the thermal recovery process.

If, in response to the third level of corrective action, the temperature cools below the temperature corresponding to threshold T4, the portion of system memory that was simulated as being hot removed is restored to a state of available memory. Restoring the portion of system memory in this case might include simulating the portion of system memory as being hot added under ACPI and the operating system.

Finally, as depicted inFIG. 6, if the third level of corrective action fails to stem the rising temperature associated with a memory module, a shut down temperature threshold T6is provided. If a temperature sensor senses a temperature exceeding T6, the system preferably aborts all processing and begins an immediate power shut down to preserve system integrity. The shut down may include or omit routines to preserve data that is open or active at the time of a T6thermal alert.

Turning now to the flow diagrams ofFIGS. 7,8,9, and10, specific embodiments of routines to implement some of the thermal alert handling techniques described above are presented. InFIG. 7, a method700exemplary of a thermal alert handling procedure invoked in response to a thermal sensor132sensing a temperature exceeding temperature threshold T2as depicted inFIG. 6. In the embodiment as depicted inFIG. 7, method700includes identifying (block702) a hot memory module. A memory range associated with the hot memory module is then determined by reference to a memory allocation table or descriptor and the memory range associated with the hot memory module is “marked” (block704) as being distant from the processor(s) in information handling system100. In embodiments, where affinity information is used to indicate the distance of the hot memory to the CPU, the operating system is notified to reload (block706) the affinity information, which may include SRAT information, SLIT information, or both. Additional details of the manner in which information handling system can dynamically modify and reload ACPI compliant affinity information including SRAT and SLIT information is described in the Nijhawan application referenced above.

FIG. 8depicts an embodiment of a method800for responding to a thermal alert issued when a temperature sensor sense a temperature drop below the temperature threshold T1as depicted inFIG. 6after having previously risen above temperature threshold T2and thereby triggering the corrective action depicted inFIG. 7. Method800as depicted includes identifying (block802) the memory module that cooled down and restoring (block804) modifying the affinity information associated with the memory module. Preferably, the affinity information is modified by restoring the information to its original state (i.e., the state of the information that existed before method700described above was invoked) or otherwise reducing the perceived distance of the identified memory module. After restoring or otherwise modifying the affinity information, the operating system is requested or notified to reload (block706) the affinity information.

Method900as depicted inFIG. 9is exercised in response to a thermal sensor detecting a temperature in excess of the temperature corresponding to threshold T5. Method900includes determining (block902) the hot memory module and simulating (block904) a hot remove or hot eject for the hot memory module and, in some embodiments, other memory modules in the same set of memory modules before restoring execution to the operating system.FIG. 10depicts a method1000invoked in response to a temperature sensor dropping below the threshold indicated by temperature threshold T4. Method1000as depicted includes determining (block1002) the memory module that has cooled down and simulating (block1004) a hot add of the memory module such as by issuing an ACPI hot add command for the memory module before returning execution to the operating system.

Although the disclosed embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made to the embodiments without departing from their spirit and scope