Recovery from cache and NVS out of sync

For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general computing systems, and more particularly to systems for increased cache and data management efficiency in computing storage environments.

2. Description of the Related Art

In today's society, computer systems are commonplace. Computer systems may be found in the workplace, at home, or at school. Computer systems may include data storage systems, or disk storage systems, to process and store data. Contemporary computer storage systems are known to destage, and subsequently, demote storage tracks from cache to long-term storage devices so that there is sufficient room in the cache for data to be written. Computer systems also may include Non Volatile Storage (NVS) systems to retain data in the event of power loss or equipment failure.

SUMMARY OF THE INVENTION

As one of ordinary skill in the art will appreciate, it is necessary for computing environments having cache memory structures and NVS systems to synchronize function in order to maintain the correct data flow and ensure data integrity. When Cache/NVS get out of sync with certain data segments, modified sectors, or NVS control blocks used for tracks, for example, various problems and panics occur while trying to recover, pin, or discard the NVS track.

For example, if Cache believes an NVS segment has been freed, Cache may reallocate the segment for another track. Since NVS is still using the segment to hold modified data for the first track, the data in NVS for the first will be overlaid by the second track. Since data is typically destaged from Cache to disk (and the data in NVS then discarded), the double use of NVS segments may not always be immediately detected. However, if a failover were to occur (due to a hardware, power or other resource failure, for example), data loss would result, since the data in NVS is corrupt. A need exists for a mechanism to ensure recovery (including retention of critical data structures) in the event that the NVS and Cache become out of sync.

Accordingly, and in view of the foregoing, various embodiments for cache/data management in a computing storage environment by a processor device, are provided. In one embodiment, by way of example only, a method for cache/data management in a computing storage environment by a processor device is provided. Incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.

Other system and computer program product embodiments are provided and supply related advantages.

DETAILED DESCRIPTION OF THE DRAWINGS

As mentioned previously, as one of ordinary skill in the art will appreciate, it is necessary for computing environments having cache memory structures and NVS systems to synchronize function in order to maintain the correct data flow and ensure data integrity. When Cache/NVS get out of sync with certain data segments, modified sectors, or NVS control blocks used for tracks, for example, various problems and panics occur while trying to recover, pin, or discard the NVS track.

For example, if Cache believes an NVS segment has been freed, Cache may reallocate the segment for another track. Since NVS is still using the segment to hold modified data for the first track, the data in NVS for the first will be overlaid by the second track. Since data is typically destaged from Cache to disk (and the data in NVS then discarded), the double use of NVS segments may not always be immediately detected. However, if a failover were to occur (due to a hardware, power or other resource failure, for example), data loss would result, since the data in NVS is corrupt. A need exists for a mechanism to ensure recovery (including retention of critical data structures) in the event that the NVS and Cache become out of sync.

The mechanisms of the illustrated embodiments serve to provide information to various storage components (such as the aforementioned Cache) that data segments are still in use, such that in the event that NVS and other hardware components are out of sync, those hardware components are made aware of the data segments in use so as to ensure data integrity. As previously mentioned, in one of the exemplary embodiments, incoming data segments into the NVS may be validated against a bitmap to determine if the incoming data segments are currently in use. If so, they are designated to the Cache as such. In this manner, the NVS effectively detects corruption before it is allowed to occur. In all cases, the out of sync data segments may be pinned and reported as data loss to prevent data integrity issues.

Turning toFIG. 1, a block diagram of one embodiment of a system100for data management incorporating various aspects of the present invention is illustrated. At least in the illustrated embodiment, system100comprises a memory102coupled to a cache104and a processor110via a bus108(e.g., a wired and/or wireless bus).

Memory102may be any type of memory device known in the art or developed in the future. Examples of memory102include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the various embodiments of memory102, storage tracks are capable of being stored in memory102. Furthermore, each of the storage tracks can be staged or destaged from/to memory102from cache104when data is written to the storage tracks.

Cache104, in one embodiment, comprises a write cache partitioned into one or more ranks106, where each rank106includes one or more storage tracks. Cache104may be any cache known in the art or developed in the future.

During operation, the storage tracks in each rank106are destaged to memory102in a foreground destaging process after the storage tracks have been written to. That is, the foreground destage process destages storage tracks from the rank(s)106to memory102while a host (not shown) is actively writing to various storage tracks in the ranks106of cache104. Ideally, a particular storage track is not being destaged when one or more hosts desire to write to the particular storage track, which is known as a destage conflict.

In various embodiments, processor110comprises or has access to a NVS management module112, which comprises computer-readable code that, when executed by processor110, causes processor110to perform data management operations in accordance with the present invention. In the various embodiments, processor110is configured for validating incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment against a bitmap to determine if the incoming data segments are currently in use, and designating those of the incoming data segments determined to be currently in use to the computing storage environment to protect data integrity.

In various other embodiments, processor110is configured for configuring the bitmap.

In various other embodiments, processor110is configured for performing the validating by an NVS Network Adapter (NA) associated with the NVS device.

In various other embodiments, processor110is configured for performing the validating by comparing an incoming Non Volatile Storage Control Block (NVSCB) against the bitmap.

In various other embodiments, processor110is configured for, pursuant to designating those of the incoming data segments, performing at least one of pinning and reporting the designated incoming data segments as data loss.

In various other embodiments, processor110is configured for, at one of an Initial Memory Load (IML) and a Warmstart, clearing and rebuilding the bitmap.

FIG. 2is a block diagram200illustrating an exemplary hardware structure of a data storage system in which aspects of the present invention may be implemented. Host computers210,220,225, are shown, each acting as a central processing unit for performing data processing as part of a data storage system200. The cluster hosts/nodes (physical or virtual devices),210,220, and225may be one or more new physical devices or logical devices to accomplish the purposes of the present invention in the data storage system200. A Network (e.g., storage fabric) connection260may be a fibre channel fabric, a fibre channel point-to-point link, a fibre channel over ethernet fabric or point to point link, a FICON or ESCON I/O interface. The hosts,210,220, and225may be local or distributed among one or more locations and may be equipped with any type of fabric (or fabric channel) (not shown inFIG. 2) or network adapter260to the storage controller240, such as Fibre channel, FICON, ESCON, Ethernet, fiber optic, wireless, or coaxial adapters. Data storage system200is accordingly equipped with a suitable fabric (not shown inFIG. 2) or network adapter260to communicate. Data storage system200is depicted inFIG. 2comprising storage controllers240and cluster hosts210,220, and225. The cluster hosts210,220, and225may include cluster nodes.

To facilitate a clearer understanding of the methods described herein, storage controller240is shown inFIG. 2as a single processing unit, including a microprocessor242, system memory243and nonvolatile storage (“NVS”)216, which will be described in more detail below. It is noted that in some embodiments, storage controller240is comprised of multiple processing units, each with their own processor complex and system memory, and interconnected by a dedicated network within data storage system200. Moreover, given the use of the storage fabric network connection260, additional architectural configurations may be employed by using the storage fabric260to connect multiple storage controllers240together with one or more cluster hosts210,220, and225connected to each storage controller240.

In some embodiments, the system memory243of storage controller240includes operation software250and stores program instructions and data which the microprocessor242may access for executing functions and method steps associated with executing the steps and methods of the present invention. As shown inFIG. 2, system memory243may also include or be in communication with a cache245, also referred to herein as a “cache memory”, for buffering “write data” and “read data”, which respectively refer to write/read requests and their associated data. In one embodiment, cache245is allocated in a device external to system memory243, yet remains accessible by microprocessor242and may serve to provide additional security against data loss, in addition to carrying out the operations as described herein.

In some embodiments, cache245may be implemented with a volatile memory and non-volatile memory and coupled to microprocessor242via a local bus (not shown inFIG. 2) for enhanced performance of data storage system200. The NVS216included in data storage controller is accessible by microprocessor242and serves to provide additional support for operations and execution as described in other figures. The NVS216, may also be referred to as a “persistent” cache, or “cache memory” and is implemented with nonvolatile memory that may or may not utilize external power to retain data stored therein. The NVS may be stored in and with the cache245for any purposes suited to accomplish the objectives of the present invention. In some embodiments, a backup power source (not shown inFIG. 2), such as a battery, supplies NVS216with sufficient power to retain the data stored therein in case of power loss to data storage system200. In certain embodiments, the capacity of NVS216is less than or equal to the total capacity of cache245.

The NVS216may include a NVS management module112. The NVS management module112may work in conjunction with each and every component of the storage controller240, the hosts210,220,225, and other storage controllers240and hosts210,220, and225that may be remotely connected via the storage fabric260. NVS management module112may be structurally one complete module or may be associated and/or included with other individual modules. NVS management module112may also be located in the other components of the storage controller240.

NVS management module112includes a bitmap217, whose functionality will be further described in detail, following. For purposes of the instant discussion, however, bitmap217serves as a validation tool, in which existing data segments in NVS are compared against incoming data segments to determine which, if any, of the incoming data segments are currently in use.

The storage controller240includes a control switch241for controlling a protocol to control data transfer to or from the host computers210,220,225, a microprocessor242for controlling all the storage controller240, a nonvolatile control memory243for storing a microprogram (operation software)250for controlling the operation of storage controller240, cache245for temporarily storing (buffering) data, and buffers244for assisting the cache245to read and write data, and the NVS management module112, in which information may be set. The multiple buffers244may be implemented to assist with the methods and steps as described herein.

Turning now toFIG. 3, a flow chart diagram, illustrating an exemplary method300for data management in which aspects of the present invention are incorporated, is depicted. Method300begins (step302). Incoming data segments (e.g., tracks) into NVS storage are validated against a bitmap to determine if the incoming data segments are in use (step304). Those of the incoming data segments that are identified as such are designated to components in the computing environment (step306). The method300then ends (step306).

FIG. 4, following, is an additional flow chart diagram depicting an exemplary method400of operation of various storage components in accordance with the present invention. Method400begins (step402) with the configuration of a bitmap in the NVS network adapter (NA) code to designate segments in use (step404). In one exemplary embodiment, this bitmap is implemented as a structure per 16 MB Logical Memory Block (LMB) in the computing storage environment.

Again, in one exemplary embodiment, during an Initial Memory Load (IML) and Warmstart operation, the bitmap is cleared and rebuilt with the modified Non Volatile Storage Control Blocks (NVSCBs). For each NVSCB, the bit corresponding to each used segment is tuned on.

When a track NVSCB Buffer arrives in NVS, the NA code validates that the new segments are not currently in use in the bitmap (step406). If any segment is currently in use (step408), then the NA code has detected corruption before it is allowed to occur (e.g., the Non Volatile component believes that a segment is FREE while a NA component knows it is IN-USE). Once the segment is identified, the segment is pinned (step410), and the segment is reported as potential data loss (step412). The method400then continues (returning to step406).

In one exemplary embodiment, if an out-of-sync scenario is identified, once the Commit or Abort for the Track NVSCB Buffer is complete, the NA code will panic to drive a warmstart to get the NA and NVS back in sync for the used segments.

NA and NV can get out of sync if NA is told Commit (e.g., keep the segments) and Cache/NV is told Abort (e.g., free the segments). When NA Discards a track, the bits in the bitmap for each discarded segment are verified to be on, then turned off. When NA Commits a track, the bits in the bitmap for each kept segment are verified to be off, then turned on.

InFIG. 5, following, a table500of exemplary rules to be employed during a Warmstart NVSCB Recovery operation is depicted. In a first situation, if NVS has a track, and Cache does not have a CDCB for the track, then the track is Pinned Non-Retryable. In a second situation, if NVS has a track and Cache has a CDCB for the track, but the track is not NVS modified, then the track is restored from NVS to Cache.

In a third situation, if the NVS segments kept for a track are different from the Primary Segment Control Block (PSCB) segments for a track, and the PSCBs are not in use by another track, then the PSCBs are force allocated to match NVS, and the track is restored from NVS to Cache. In a fourth situation, if the NVS segments kept for a track are different from the PSCB segments for the track and the PSCB segments are in use by another track, the track is made Pinned Non-Retryable.

Any combination of one or more computer-readable medium(s) may be utilized. The computer-readable medium may be a computer-readable signal medium or a physical computer-readable storage medium. A physical computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, crystal, polymer, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Examples of a physical computer-readable storage medium include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, RAM, ROM, an EPROM, a Flash memory, an optical fiber, a CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain, or store a program or data for use by or in connection with an instruction execution system, apparatus, or device.

Computer code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the foregoing. Computer code for carrying out operations for aspects of the present invention may be written in any static language, such as the “C” programming language or other similar programming language. The computer code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, or communication system, including, but not limited to, a local area network (LAN) or a wide area network (WAN), Converged Network, or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

While one or more embodiments of the present invention have been illustrated in detail, one of ordinary skill in the art will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.