I2C device including bus switches and programmable address

An I2C device is disclosed that includes a main I2C section, bus switches, switch logic, and address logic as part of the I2C device. The I2C device is coupled to an I2C bus for communicating with other I2C devices and an I2C bus controller that is also on the I2C bus. The switch logic controls a current position of the switches. The I2C device is coupled to the I2C bus utilizing the switches. The switches control whether the main I2C section, the address logic, the switch logic, or a combination of the main I2C section, address logic, and switch logic is currently coupled to I2C bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the I2C device. The I2C device will respond to the address that is stored in its address logic.

CROSS-REFERENCE TO RELATED APPLICATIONS

The subject matter of the present invention is related to copending U.S. application Ser. No. 09/779,364, entitled I2C SELF BUS SWITCHING DEVICE, filed on Feb. 8, 2001; Ser. No. 09/779,368, entitled METHOD FOR ISOLATING AN I2C BUS FAULT USING SELF BUS SWITCHING DEVICE, filed on Feb. 8, 2001; and Ser. No. 09/773,185, entitled DYNAMICALLY ALLOCATING I2C ADDRESSES USING SELF BUS SWITCHING DEVICE, filed on Jan. 31, 2001, all of which being assigned to the same assignee and all of which incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to computer bus architecture. More specifically, the present invention relates to Inter Integrated Circuit (I2C) buses.

2. Description of Related Art

Many similarities exist between seemingly unrelated designs in consumer, industrial and telecommunication electronics. Examples of similarities include intelligent control, general-purpose circuits (i.e. LCD drivers, I/O ports, RAM) and application-oriented circuits. The Philips Inter Integrated Circuit (I2C) bus is a bi-directional two-wire serial bus designed to exploit these similarities.

Devices on the I2C bus are accessed by individual addresses, 00-FF (even addresses for Writes, odd addresses for reads). The I2C architecture can be used for a variety of functions. One example is Vital Product Data (VPD). Each component in the system contains a small Electrically Erasable Programmable Read Only Memory (EEPROM) (typically 256 bytes) which contains the VPD information such as serial numbers, part numbers, and engineering change revision level.

I2C busses can connect a number of devices simultaneously to the same pair of bus wires. Normally, the device addresses on the I2C bus are predefined by hardwiring on the circuit boards. A limitation of the I2C bus is that it will only allow a single device to respond to each even address between 00 and FF. All addresses are even because only the high-order seven bits of the address byte are used for the address. Bit0is used to indicate whether the operation is to be a read or a write. Therefore, there are a limited number of addresses that can be assigned to a device.

Many I2C devices have their high-order four address bits predefined. The remaining three address bits are assigned with the use of strapping pins on the device. For example, most I2C accessible EEPROMs have three strapping pins which limit their addresses to the even addresses between A0–AF. This permits eight unique addresses for a given chip of that type. Thus, only eight of these devices may be connected to a single bus and still each have a unique address.

In addition to address conflicts, a problem results when one of the devices malfunctions and pulls a bus signal (clock or data) low. The bus will not operate, and it is very difficult to determine which of the numerous devices connected to the I2C bus is responsible. A similar problem occurs when one of the bus conductors becomes shorted to a low impedance source, such as, for example, ground.

Therefore, a need exists for an I2C device that includes bus switches and that may be addressed using a reprogrammable device address.

SUMMARY OF THE INVENTION

An I2C device is disclosed that includes a main I2C section, bus switches, switch logic, and address logic as part of the I2C device. The I2C device is coupled to an I2C bus for communicating with other I2C devices and to an I2C bus controller that is also coupled to the I2C bus. The switch logic controls a current position of the switches. The I2C device is coupled to the I2C bus utilizing the switches. The switches control whether the main I2C section, the address logic, the switch logic, or a combination of the main I2C section, address logic, and switch logic is currently coupled to I2C bus. The address logic is used to receive and store the address of the I2C device. Thus, the device address can be redefined or reprogrammed. The I2C device will respond to the address that is stored in its address logic. Thus, the I2C device's address is the address that is stored in its address logic.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference now to the figures and in particular with reference toFIG. 1, a pictorial representation of a data processing system in which the present invention may be implemented is depicted in accordance with a preferred embodiment of the present invention. A computer100is depicted which includes a system unit110, a video display terminal102, a keyboard104, storage devices108, which may include floppy drives and other types of permanent and removable storage media, and mouse106. Additional input devices may be included with personal computer100, such as, for example, a joystick, touchpad, touch screen, trackball, microphone, and the like. Computer100can be implemented using any suitable computer, such as an IBM RS/6000 computer or IntelliStation computer, which are products of International Business Machines Corporation, located in Armonk, N.Y. Although the depicted representation shows a computer, other embodiments of the present invention may be implemented in other types of data processing systems, such as a network computer. Computer100also preferably includes a graphical user interface that may be implemented by means of systems software residing in computer readable media in operation within computer100.

With reference now toFIG. 2, a block diagram of a data processing system is shown in which the present invention may be implemented. Data processing system200is an example of a computer, such as computer100inFIG. 1, in which code or instructions implementing the processes of the present invention may be located. Data processing system200employs an I2C bus architecture. The I2C bus248is a bi-directional serial bus requiring only two wires: a serial data line (SDA) and a serial clock line (SCL). Although serial buses do not have the throughput capability of parallel buses, serial buses require less wiring and fewer Integrated Circuit (IC) connector pins. Each device (processor202, electronically erasable and programmable read only memory (EEPROM)240, temperature sensor242, and any other I2C device244) connected to I2C bus248is software addressable by a unique address. The devices can operate as either transmitters or receivers. All I2C bus compatible devices have an on-chip interface which allows the devices to communicate directly with each other via the I2C bus248. A simple master/slave relationship exists at all times. A master is a device which initiates a data transfer and the clock signals to permit the transfer, and any device addressed at the time of transfer is considered a slave. The I2C bus is a multimaster bus, meaning more than one device capable of controlling the bus can be connected to it. However, the present implementation is operated in a single-master mode.

Processor202and main memory204are connected to PCI local bus206through PCI bridge208. PCI bridge208also may include an integrated memory controller and cache memory for processor202. Additional connections to PCI local bus206may be made through direct component interconnection or through add-in boards. In the depicted example, local area network (LAN) adapter210, small computer system interface SCSI host bus adapter212, and expansion bus interface214are connected to local bus206by direct component connection. In contrast, audio adapter216, graphics adapter218, and audio/video adapter219are connected to local bus206by add-in boards inserted into expansion slots. Expansion bus interface214provides a connection for a keyboard and mouse adapter220, modem222, and additional memory224. SCSI host bus adapter212provides a connection for hard disk drive226, tape drive228, and CD-ROM drive230.

An operating system runs on processor202and is used to coordinate and provide control of various components within data processing system200inFIG. 2. The operating system may be a commercially available operating system such as Windows 2000, which is available from Microsoft Corporation. An object oriented programming system such as Java may run in conjunction with the operating system and provides calls to the operating system from Java programs or applications executing on data processing system200. “Java” is a trademark of Sun Microsystems, Inc. Instructions for the operating system, the object-oriented programming system, and applications or programs are located on storage devices, such as hard disk drive226, and may be loaded into main memory204for execution by processor202.

For example, data processing system200, if optionally configured as a network computer, may not include SCSI host bus adapter212, hard disk drive226, tape drive228, and CD-ROM230, as noted by dotted line232inFIG. 2denoting optional inclusion. In that case, the computer, to be properly called a client computer, must include some type of network communication interface, such as LAN adapter210, modem222, or the like. As another example, data processing system200may be a stand-alone system configured to be bootable without relying on some type of network communication interface, whether or not data processing system200comprises some type of network communication interface. As a further example, data processing system200may be a personal digital assistant (PDA), which is configured with ROM and/or flash ROM to provide non-volatile memory for storing operating system files and/or user-generated data.

The depicted example inFIG. 2and above-described examples are not meant to imply architectural limitations. For example, data processing system200also may be a notebook computer or hand held computer in addition to taking the form of a PDA. Data processing system200also may be a kiosk or a Web appliance.

The processes of the present invention are performed by processor202using computer implemented instructions, which may be located in a memory such as, for example, main memory204, memory224, or in one or more peripheral devices226–230.

FIG. 3depicts a schematic diagram of an integrated circuit chip that includes an I2C device that has address logic and bus switches in accordance with the present invention. I2C device300includes a main I2C section302, address logic304, switch logic306, IN switch pair308, and OUT switch pair310. I2C main section302is an I2C device such as known in the prior art that adheres to the I2C standard.

In the prior art, one or more I2C devices, such as main section302, are coupled together using an I2C bus to communicate with each other. According to the present invention, switch pairs308and310, address logic304and switch logic306are added to main section302to create a new I2C device300. Thus, one or more I2C devices300may be coupled together using an I2C bus to communicate with each other.

An IN switch pair308and an OUT switch pair310are also included which are controlled by switch logic306in order to control which portions of I2C device300are coupled to the I2C bus as well as whether or not I2C device300communicates on the I2C bus at all. In addition, by selecting particular switch positions, I2C device300can control whether or not devices coupled to the I2C bus downstream from I2C device300can communicate on the I2C bus.

I2C devices that receive a signal on the I2C bus after a particular I2C device has received the signal are considered to be “downstream” from the particular I2C device.

Since an I2C bus is comprised of two signal lines, Clock and Data, the IN and OUT switches are each comprised of a pair of rotary switches. Each one of the IN and OUT switches is a double pole rotary switch. One of the poles in the IN pair is for the Clock signal and the other is for the Data signal. The same is true of the OUT switch.

For simplicity, the drawings and corresponding description indicate that the two signals combined as the “I2C bus communication bus”, “I2C bus signals”, or “I2C signals” and the double pole rotary switches will simply be referred to herein as “switch” or “switches”.

Each switch may, independently of the position of the other switch, be in one of four different positions, position0,1,2, or3. Thus, IN switch308may be in either position0,1,2, or3while OUT switch310may be in either position0,1,2, or3.

Switch positions are controlled by switch logic306. Thus, switch logic306receives a command and then causes one or both switches308,310to change their position.

A reset signal312may be received by main section302and address logic304. When reset signal312is received, switch logic306causes both IN switch308and OUT switch310to move to position3if they are not in position3already.

I2C device300is included within an integrated circuit320. Various parts of I2C device300are accessible utilizing one of the pins322–336of integrated circuit320. For example, reset signal312may be received utilizing pin322. The I2C communication bus is input to I2C device300utilizing pins336and334for the Clock and Data signals and is output from I2C device300utilizing pins332and330. In this manner, multiple devices, such as I2C device300, may be coupled serially together by coupling an output of the I2C bus for one I2C device to an input for the bus for another I2C device.

Address logic304is used by an I2C device300to receive and store the address of I2C device300. I2C device300will respond to the address that is stored in its address logic. The address stored in address logic304is programmable. Thus, I2C device300may receive a new address and then store that address in its address logic306. I2C device300will then respond to this new address. In this manner, the address of I2C device300is reprogrammable to a new address received via the I2C bus.

A typical I2C address is a seven-bit address. The lower-order three bits are typically hardwired using pins. The present invention may be used to override, and thus reprogram, any or all of these seven bits. Thus, any or all of the three lower-order hardwired address pins can be overridden by storing a new address in the address logic that changes just the lower-order bits. As another example, only the higher-order four address bits could be overridden using the present invention, thus preserving the hardwired bits.

For example,FIG. 4illustrates multiple I2C devices coupled together utilizing an I2C bus in accordance with the present invention. The I2C bus is a communications bus that is used by the various I2C devices300a–dto communicate with each other. A bus driver400controls an I2C bus. The I2C bus is a serial bus. Therefore, each device300a–dreceives an incoming I2C bus signal, and then outputs an outgoing I2C bus signal which is then received by another device300as an incoming I2C bus signal.

The I2C bus signal is first received, via I2C bus segment402, as an input to device300a. I2C bus segment404is used to output an I2C bus signal from device300ato be received as an input by device300b. Device300boutputs an I2C bus signal via I2C bus segment406which is then received as an input by device300c. Device300cthen outputs an I2C bus signal via I2C bus segment408which is received as an input by device300d.

A reset signal410is output from bus driver400and received by each device300a–d.

Referring again toFIG. 3, the following discussion of switch positions applies to the switches of any of the devices300a–d. Each IN switch receives an incoming I2C bus signal. If an output I2C bus signal is provided by a device300, that signal is output through an OUT switch.

When both IN308and OUT310switches are in position3, the I2C bus signal received at IN switch308will pass through device300and be made available as an output from switch310on pin330to any device downstream that is connected to this device. The I2C bus signal is received by main section302, address logic304, and switch logic306. When the switches are in position3, main section302is active and available. The address of device300may be programmed, and the switches may be controlled by switch logic306.

When both IN308and OUT310switches are in position2, the I2C bus signal received at IN switch308will pass through device300and be made available as an output from switch310on pin330to any device downstream that is connected to this device. The I2C bus signal is received by address logic304and switch logic306. Main section302is disconnected from the bus and will not receive the bus signal. When the switches are in position2, main section302is inactive and unavailable. However, address logic304and switch logic306are both active and available. Therefore, the address of device300may be programmed, and the switches may be controlled by switch logic306when the switches are both in position2.

When both IN308and OUT310switches are in position1, the I2C bus signal received at IN switch308will pass through device300and be made available as an output from switch310on pin330to any device downstream that is connected to this device. The I2C bus signal is not received by main section302, address logic304, or switch logic306. Main section302, address logic304, and switch logic306are all disconnected from the bus and will not receive the bus signal. Therefore, when the switches are in position1, the address of device300may not be programmed, and the switches cannot be controlled by switch logic306. When the switches are in position1, device300is logically removed from the I2C bus. In addition, most of the device's300ability to create a bus fault is removed for diagnostic purposes.

When OUT switch310is in position0, all downstream devices are removed from the bus. Thus, the I2C bus signal received at IN switch308will not be made available as an output from switch310to any device downstream that is connected to this device. If the IN switch is in position3, the I2C bus received at IN switch308will be received by main section302, address logic304, and switch logic306. If the IN switch is in position2, the I2C bus received at IN switch308will be received by address logic304and switch logic306. However, if the OUT switch310is in position0, regardless of the position of IN switch308, the bus signal will not be sent to any device downstream that is coupled to the output of device300.

When IN switch308is in position0, all downstream devices are removed from the bus. In addition, device300is removed from the bus and will not receive the I2C bus signal. Thus, the I2C bus signal received at IN switch308will not be received by main section302, address logic304, or switch logic306. In addition, the bus signal will not be sent to any device downstream that is coupled to the output of device300.

Referring again toFIG. 4, as an example, suppose both IN and OUT switches of device300aare in position3, the bus signal received on segment402will be output on segment404and received at device's300bIN switch.

Now suppose both switches of device300bare in position3, the bus signal will be received by the main section, address logic, and switch logic of device300b, and then output on segment406.

If both switches of device300bare in position2, the bus signal will be received by only the address logic and switch logic, and not the main section, of device300b. The bus signal will also be output on segment406.

If both switches of device300bare in position1, the bus signal will not be received by main section, address logic, or switch logic of device300b. The bus signal will, however, pass from the IN switch to the OUT switch of device300band be output on segment406.

If the IN switch of device300bis in position0, the main section, address logic, and switch logic of device300bwill not receive the bus signal. In addition, the bus signal will not be output on segment406. Therefore, devices300cand300dwill not receive the bus signal and are, therefore, logically removed from the bus.

If the OUT switch of device300bis in position0and the IN switch is in position3, the main section, address logic, and switch logic of device300will receive the signal, but the signal will not be output on segment406. Therefore, devices300cand300dwill not receive the bus signal and are, therefore, logically removed from the bus.

If the OUT switch of device300bis in position0and the IN switch is in position2, the address logic and switch logic of device300will receive the signal, but the signal will not be output on segment406. Therefore, devices300cand300dwill not receive the bus signal and are, therefore, logically removed from the bus.

FIG. 5depicts a high level flow chart which illustrates programming bus switches that are included within an I2C device in accordance with the present invention. The process starts as depicted by block500and thereafter passes to block502which illustrates a determination of whether or not an instruction has been received by an I2C device300to exclude the I2C device including all of its elements, including its main section, address logic, and switch logic, from the I2C bus, while still passing I2C bus traffic to downstream I2C devices. If a determination is made that an instruction has been received to exclude the I2C device including all of its elements from the I2C bus while still passing I2C bus traffic, the process passes to block503which depicts setting both switches of the I2C device300to position1. Thus, all of the elements including in this I2C device, including its main section, address logic, and switch logic will be removed from the I2C bus. The I2C bus traffic will continue to pass through this I2C device and be received by I2C devices downstream. The process then terminates as illustrated by block512.

Referring again to block502, if a determination is made that an instruction to exclude the I2C device including all of its elements from the I2C bus while still passing I2C bus traffic to downstream devices has not been received, the process passes to block504. Block504depicts a determination of whether or not an instruction has been received by an I2C device300to exclude just the I2C device's main section from the I2C bus while permitting bus traffic to still be received by the address logic and switch logic and be passed to downstream I2C devices. If a determination is made that an instruction has been received to exclude just the main section from the I2C bus while bus traffic is passed to downstream I2C devices, the process passes to block505which illustrates setting the positions of both switches of this I2C device to position2. The process then terminates as depicted by block512.

Referring again to block504, if a determination is made that an instruction has not been received to exclude just the I2C device's main section from the I2C bus while bus traffic is passed to downstream I2C devices, the process passes to block506. Block506depicts a determination of whether or not an instruction has been received by an I2C device300to remove all I2C devices that are downstream from this I2C device while this I2C device including all of its elements remain on the bus receiving bus traffic. If a determination is made that an instruction has been received by an I2C device300to remove all I2C devices that are downstream from this I2C device while this I2C device including all of its elements remain on the bus receiving bus traffic, the process passes to block507which illustrates setting the OUT switch for this I2C device to position0. The process then terminates as depicted by block512.

Referring again to block506, if a determination is made that an instruction has not been received by an I2C device300to remove all I2C devices that are downstream from this I2C device while this I2C device including all of its elements remain on the bus receiving bus traffic, the process passes to block508. Block508illustrates a determination of whether or not an instruction has been received by an I2C device to remove all I2C devices that are downstream from this I2C device as well as this I2C device. If a determination is made that an instruction has been received by an I2C device to remove all I2C devices that are downstream from this I2C device as well as this I2C device, the process passes to block509which depicts setting the IN switch for this I2C device to position0. The process then terminates as illustrated by block512.

Referring again to block508, if a determination is made that an instruction has not been received by an I2C device to remove all I2C devices that are downstream from this I2C device as well as this I2C device, the process passes to block510. Block510illustrates a determination of whether or not an instruction has been received to reset one or more I2C devices. If a determination is made that an instruction has been received to reset one or more I2C devices, the process passes to block511which depicts setting both switches for any I2C device that is to be reset to position3. Any I2C device that has both switches in position3will be fully functional, capable of receiving bus traffic by its main section, address logic, and switch logic, and will pass I2C bus traffic to the next I2C device downstream from this I2C device. The process then terminates as depicted by block512.

Referring again to block510, if a determination is made that an instruction has not been received to reset one or more I2C devices, the process then terminates as depicted by block512.

FIG. 6illustrates a high level flow chart which depicts reprogramming addresses of one or more I2C devices in accordance with the present invention. The process starts as depicted by block600and thereafter passes to block602which illustrates sending a reset signal to all I2C devices. This reset signal will cause the switches in all I2C devices to be set to position3making all I2C devices fully functional. Next, block604depicts a determination of whether or not any of the I2C devices have duplicate addresses. If a determination is made that none of the I2C devices have duplicate addresses, the process passes to block616.

Referring again to block616, if a determination is made that at least two of the I2C devices have duplicate addresses, the process passes to block606which illustrates sending a command to the I2C devices that have duplicate addresses to set their OUT switches to position0. Thus, such a command is broadcast on the I2C bus to the duplicate address.

Each device300monitors the I2C bus and will respond to its own address. When an address conflict occurs, i.e. when two or more devices have the same address, all of those devices having this address will respond to the address. Thus, if a command to set OUT switches to position0is broadcast to the duplicate address, all of the I2C devices having the duplicate address will respond to the command by setting their OUT switches to position0.

Next, block608depicts sending a command to the duplicate address to change its address to a specified new address. Because all I2C devices having the duplicate address have removed downstream devices from the I2C bus when their OUT switch was set to position0, only the first I2C device on the bus from the bus driver that has the duplicate address will receive this command to change its address. This I2C device that is first on the serial bus from the bus driver will change its address to the new address. However, the remaining I2C devices on the bus having the duplicate address will continue to have what was originally the duplicate address. Block610, then, illustrates sending a command to this new address to set the switches in the I2C device to position3to make the device fully functional and permit downstream I2C devices to receive bus traffic.

Now, the second device having the previously duplicate address is reconnected to the bus. If it is the only device still having that address, nothing more needs to be done as it is no longer an address shared by another device.

Thereafter, block612depicts a determination of whether or not any more of the I2C devices have duplicate addresses. If a determination is made that one or more of the I2C devices still have duplicate addresses, the process passes back to block608. This process loop continues until only one device has the original duplicate address which is then a unique address. Once a set of duplicate addresses is dealt with in the manner described above, the process then passes back to block602.

Referring again to block604, if none of the devices have duplicate addresses, the process passes to block616which depicts a determination of whether or not any addresses for other I2C devices should be changed. If a determination is made that no other addresses need to be changed, the process terminates as illustrated by block624.

Referring again to block616, if a determination is made that the address for another I2C device needs to be changed, the process passes to block620which depicts sending a command to this I2C device to change its address to a new address. The process then terminates as depicted by block624.

The device depicted herein is given merely by way of example and is not intended as an architectural limitation to the present invention. Other embodiments of a device including switches may include different numbers of pins and include other components not shown.