Nanosheet single gate (SG) and extra gate (EG) field effect transistor (FET) co-integration

A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

BACKGROUND

Technical Field

The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices including channel regions integrated within nano-sheets.

Description of the Related Art

With the continuing trend towards miniaturization of integrated circuits (ICs), there is a need for transistors to have higher drive currents with increasingly smaller dimensions. The use of non-planar semiconductor devices such as, for example, nanowire and nano-sheet transistors may be the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices.

SUMMARY

In one aspect, a method of forming an electrical device is provided that produces one stack of nanosheets having a channel region contacted by a single gate structure; and a second stack of nanosheets having a channel region contacted by a multi-gate structure (hereafter referred to as extra gate structure). In one embodiment, the method includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness, wherein the second thickness is less than the first thickness; and forming a dielectric layer on the first and second stack of nanosheets, wherein the dielectric layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and the work function metal layer is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

In another embodiment, a method of forming an electrical device is provided that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness, wherein the second thickness is less than the first thickness. The method may continue with forming a dielectric layer on the first and second stack of nanosheets, wherein the dielectric layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The dielectric layer may be removed from the first stack of nanosheets to open the space between the nanosheets in the first stack, wherein the dielectric layer remains conformally present on the nanosheets in the second stack. A work function metal layer is formed on the first and second stack of nanosheets. The work function metal layer is present filling an entirety of the space between the nanosheets in the first stack. The work function metal layer is conformally present about an entirety of the nanosheets in the second stack, wherein a space remain between stacked nanosheets in the second stack.

In another embodiment, the method of forming the electrical device includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness, wherein the second thickness is less than the first thickness; and forming a metal nitride layer on the first and second stack of nanosheets. In some embodiments, the metal nitride layer fills a space between the nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The metal nitride layer can be removed from the second stack of nanosheets. An oxide layer is formed on the second stack of nanosheets, and the metal nitride layer is removed from the first stack of nanosheets. A work function metal layer may be formed on the first and second stack of nanosheets, wherein the work function metal layer is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

In another aspect, a semiconductor device is provided. In one embodiment, the semiconductor device comprises a first stack of nanosheets on a first portion of a substrate, and a second stack of nanosheets on a second portion of the substrate. The nanosheets in the first stack have a greater thickness than the nanosheets in the second stack. Therefore, the space separating adjacently stacked nanosheets in the second stack is greater than the space separating the adjacently stacked nanosheets in the first stack. A first gate structure is present on the first stack of nanosheets. The first gate structures is a singular gate structure including a first high-k dielectric that is conformally present on the nanosheets in the first stack; a dielectric layer filling the space between the adjacently stacked nanosheets; and a first work function metal layer on exterior sidewalls of the first stack and the dielectric layer filling the space between the adjacently staked nanosheets in the first stack. A second gate structure is present on the second stack of nanosheets. The second gate structure is a multi-gate (also referred to as extra-gate) structure including a second high-k dielectric that is conformally present on the nanosheets in the second stack; a dielectric layer filling the space between the adjacently stacked nanosheets; and a second work function metal layer on exterior sidewalls of the second stack and the dielectric layer filling the space between the adjacently staked nanosheets in the second stack.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. For purposes of the description hereinafter, the terms “upper”, “over”, “overlying”, “lower”, “under”, “underlying”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The term “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

In one aspect, embodiments of the present disclosure describes nanosheet transistors and methods of forming nanosheet transistors. Nanosheet (nanowire) MOSFET is a candidate for future CMOS technology. Nanosheet MOSFETs can provide better gate electrostatic control and larger effective device width per footprint (multiple nanosheets in one stack). In some embodiments, it can be desirable to have both thin and thick oxide transistors using nanosheet technology simultaneously in the same device, e.g., on the same supporting substrate simultaneously. Further details regarding the method and structures of the present disclosure are now described with reference toFIGS. 1-17

FIG. 1is a top down view of a plurality of nanosheets10a,10b, in which a first set of the nanosheets10ais used to for providing high voltage single gate (SG) nanosheet semiconductor devices having a thick oxide layer within the gate structure, and a second set of the nanosheets10bis used for providing extra gate (EG) nanosheet semiconductor devices having a thin oxide layer within the gate structure.

FIG. 2is a side cross-sectional view of the stacks of nanosheets10a,10bdepicted inFIG. 1. The cross-section depicted inFIG. 2is through the channel region portions of the nanosheets10a,10b. The cross-section depicted inFIG. 2is following removal of a sacrificial gate structure as part of a replacement gate process flow, which may also be referred to as a gate last process flow.

The stacks of nanosheets10a,10bare depicted being present on a supporting substrate1. In some embodiments, each stack of nanosheets10a,10bincludes at least two semiconductor materials5a,5b,5c,5dthat are present overlying the substrate1. The substrate1may be composed of a supporting material1, such as a semiconductor material, e.g., silicon, or dielectric material, such as silicon oxide or silicon nitride.

The stack of nanosheets10a,10beach include at least two semiconductor materials5a,5b,5c,5dis typically composed of two alternating materials. For example, the first semiconductor material5a,5bthat is present on the substrate1may be composed of a silicon and germanium containing semiconductor material, such as silicon germanium (SiGe), whereas the second semiconductor material5c,5dthat is present on the first semiconductor material5a,5bmay be composed of a germanium free silicon containing semiconductor material, such as silicon (Si). It is noted that this is only one example of semiconductor materials that may be used for the at least two semiconductor materials5a,5b,5c,5d. Any semiconductor material composition may be used for each of the at least two semiconductor materials5a,5b,5c,5dso long as at least one of the compositions selected allow for selective etching between at least two of them. Any type IV semiconductor composition combination and/or III-V semiconductor composition combination is suitable for use with the present disclosure. For example, the compositions selected for the at least two semiconductor materials include Si, SiGe, SiGeC, SiC, single crystal Si, polysilicon, i.e., polySi, epitaxial silicon, i.e., epi-Si, amorphous Si, i.e., a:Si, germanium, gallium arsenide, gallium nitride, cadmium telluride and zinc sellenide.

AlthoughFIG. 2only depicts two semiconductor material layers5a,5b,5c,5din each stack10a,10b, it is noted that the present disclosure is not limited to only this example. Any number of semiconductor material layers5a,5b,5c,5dmay be present in each stack10.

The stack10a,10bof the at least two semiconductor materials5a,5b,5c,5dmay be formed using a deposition process, such as chemical vapor deposition (CVD). The thickness of each of the at least two semiconductor material layers5a,5b,5c,5dmay range from 1 nm to 30 nm. In another embodiment, the thickness of each of the at least two semiconductor material layers5a,5b,5c,5dmay range from 5 nm to 20 nm.

Following deposition, the semiconductor material layers5a,5b,5c,5dmay be patterned to provide the geometry of the stack. In some embodiments, the semiconductor material layers5a,5b,5c,5dmay be patterned using deposition, photolithography and subtractive etch processing. In one example, the stack10a,10bmay have a height H1ranging from 5 nm to 200 nm, and a width ranging from 5 nm to 60 nm.

In the following description, the semiconductor material layers identified by reference numbers5aand5bmay also be referred to as “nanosheets”, and the semiconductor material layers identified by reference numbers5cand5dmay be referred to as “sacrificial nanosheets”.

Isolation regions2may be composed of a dielectric material, e.g., silicon oxide. The isolation regions2may be formed using a deposition process, such as chemical vapor deposition (CVD).

Still referring toFIG. 2, as noted above, the cross-section that is depicted in through the channel following removal of the replacement gate structure, i.e., sacrificial gate structure, of a replacement gate process. By “replacement” it is meant that the structure is present during processing of the semiconductor device, but is removed from the semiconductor device prior to the device being completed. As used herein, the term “replacement gate structure” denotes a sacrificial structure that dictates the geometry and location of the later formed functioning gate structure. The “functional gate structure” operates to switch the semiconductor device from an “on” to “off” state, and vice versa.

In one embodiment, the sacrificial material that provides the replacement gate structure may be composed of any material that can be etched selectively to the at least one of the material layers of the stacks10a,10bof the at least two semiconductor materials5a,5b,5c,5d, i.e, the stacks10a,10bof the nanosheets5a,5b, and the sacrificial nanosheets5c,5d. In one embodiment, the replacement gate structure may be composed of a silicon-including material, such as polysilicon. In another embodiment, the replacement gate structure may be composed of a dielectric material, such as an oxide, nitride or oxynitride material, or amorphous carbon. The replacement gate structure may be formed using deposition (e.g., chemical vapor deposition) photolithography and etch processes (e.g., reactive ion etching). A spacer can be formed on the sidewall of the replacement gate structure.

In some embodiments, before removing the replacement gate structure, source and drain regions are formed for each set of stacks10a,10b, in which the source and drain regions are positioned on opposing sides of the replacement gate structure. In some embodiments, the portions of the stacks10a,10bthat extend beyond the spacer may be etched prior to forming the source and drain regions. As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel region, in which carriers are flowing out of the transistor through the drain. The term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel region.

The source and drain regions may be composed of epitaxial semiconductor material that is doped to an n-type or p-type dopant. The term “epitaxial semiconductor material” denotes a semiconductor material that has been formed using an epitaxial deposition or growth process. “Epitaxial growth and/or deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has substantially the same crystalline characteristics as the semiconductor material of the deposition surface. In some embodiments, when the chemical reactants are controlled and the system parameters set correctly, the depositing atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystal surface will take on a {100} orientation.

In some embodiments, the epitaxial semiconductor material that provides the source and drain regions may be composed of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C), or the epitaxial semiconductor material that provides the source and drain regions may be composed of a type III-V compound semiconductor, such as gallium arsenide (GaAs).

In some embodiments, after forming the source and drain regions, the replacement gate structure may be removed. In some embodiments, removing the replacement gate structure may begin with forming an interlevel dielectric layer overlying at least the source and drain regions, and planarizing the interlevel dielectric layer to expose an upper surface of the replacement gate structure. The replacement gate structure may be removed using a wet or dry etch process. In one embodiment, the replacement gate structure may be removed by at least one of an anisotropic etch process, such as reactive ion etch (RIE), or an isotropic etch process, such as a wet chemical etch. Removing the replacement gate structure provides a gate opening to the channel region portions of the stacks of nanosheets10a,10b.

FIG. 3depicting removing a sacrificial nanosheet5c,5dfrom both stacks10a,10bof nanosheets5a,5bin the single gate (SG) region15and extra gate (EG) region20of the substrate1. In some embodiments, the sacrificial nanosheets5c,5dof the stack10a,10bare removed selectively to at least a remaining material composition that provides suspended channel structures, i.e., the nanosheets5a,5b. For example, in one embodiment when the semiconductor material of the nanosheets5a,5bis composed of silicon germanium (SiGe) and the sacrificial nanosheets5c,5dare composed of silicon, the sacrificial nanosheets5bmay be removed selectively to the semiconductor material of the nanosheets5a,5bwith an etch process, such as a wet chemical etch.

In this example, following removal of one of the sacrificial nanosheets5c,5dof the stacks10a,10b, a suspended channel structure is provided by the nanosheets5a,5bthat remain. By “suspended channel” it is meant that at least one semiconductor material layer, e.g., nanosheets5a,5b, is present overlying the substrate1, wherein the sidewalls of the suspended channel are supported, e.g., anchored, in the spacer that was previously formed on the sidewall of the replacement gate structure. As noted, the suspended channels are provided by nanosheets5a,5b. The term “nanosheet” denotes a substantially two dimensional structure with thickness in a scale ranging from 1 to 100 nm. The width and length dimensions of the nanosheet may be greater than the width dimensions.

FIG. 3also depicts forming a bock mask30over the nanosheets5ain the single gate (SG) region15. The block mask30may comprise soft and/or hardmask materials and can be formed using deposition, photolithography and etching. In one embodiment, the block mask30is a hardmask composed of an organic planarization layer (OPL). The organic planarization layer (OPL) may be deposited on the structure depicted inFIG. 2. Following the formation of the OPL layer, an anti-reflection coating (ARC) or low temperature oxide (LTO) layer is deposited followed by a resist mask. The organic planarization layer (OPL) layer may be composed of an organic polymer that may include polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). The OPL layer should be baked at a temperature at or above the subsequent processing steps to ensure no out-gassing and contamination. In some embodiments, the organic planarization layer (OPL)16is deposited from solution, e.g., by spin on deposition, and is baked at high temperature.

In the embodiments that employ a low temperature oxide, the low temperature oxide, e.g., silicon oxide (SiO2), can be deposited by chemical vapor deposition (CVD) at temperatures of less than 400° C.

In the embodiments, that employ an anti-reflective coating, the anti-reflective coating (ARC) can be composed of silicon oxynitride (SiON) that is deposited using chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD) or low temperature chemical vapor deposition.

The resist mask may be patterned to protect the portion of the OPL, as well as the LTO and/or SiARC, that is present overlying the single gate (SG) region15. The exposed portion of the OPL layer, as well as the exposed portions of the LTO and/or SiARC layer, are then removed by an etch process. The resist mask may then be stripped. The remaining portion of the OPL layer provides the block mask30that is depicted inFIG. 3.

FIG. 4depicts thinning of the channel region portions of the suspended nanosheets5bin the extra gate (EG) region20of the substrate1.FIG. 4depicts that the nanosheets5athat are present in the single gate (SG) region15of the substrate1are protected by the block mask30, while the nanosheets5bthat are present in the extra gate (EG) region20of the substrate1are exposed. The exposed nanosheets5bmay be thinned by a process that includes controlling thinning of the silicon (Si) containing nanosheets5b, which can include ozone (O3) oxidation, SC1 chemistry oxidation and/or dry oxidation. In one embodiment, oxidation of the silicon containing surface of the exposed nanosheets5bincludes the application of ozone (O3) gas at room temperature, e.g., 20°-25° C., or at elevated temperature.

In another embodiment, the controlled thinning of the silicon containing nanosheets5bcan include the application of an SC-1 chemistry, which may be part of an RCA clean. For example, the first step of the RCA clean that includes ammonium hydroxide and hydrogen peroxide may be referred to as “SC-1” (standard clean #1). SC-1 includes of a mixture of ammonium hydroxide and hydrogen peroxide and deionized water. A typical concentration ratio for the mix is 1:1:5 NH4OH:H2O2:H2O, although ratios as low as 0.05:1:5 are suitable for cleaning the substrate5. SC-1 typically operates in a temperature ranging from 50° C. to 70° C. The second step of the RCA clean that includes the aqueous mixture of hydrochloric acid and an oxidizing agent may be may be referred to as “SC-2” (standard clean #2). SC-2 includes a mixture of hydrochloric acid, hydrogen peroxide, and deionized water. A typical concentration ratio for the mix is 1:1:5 HCl:H2O2:H2O. SC-2 is typically operated in the temperature range of 50−70° C.

In yet another example, the controlled oxidation may be provided by thermal oxidation, e.g., wet and/or dry thermal oxidation. Thermal oxidation of the exposed silicon containing nanosheets5bcan be performed at a temperature between 800° C. and 1200° C., resulting in so called High Temperature Oxide layer (HTO). In some embodiments, the thermal oxidation process may use either water vapor or molecular oxygen as the oxidant.

The aforementioned processes can form a thin oxide, e.g., silicon oxide (SiO2), on the exposed surfaces of the silicon containing nanosheets5b, which can have a thickness ranging from 1 nm to 5 nm in thickness. In some embodiments, the thickness of the oxide formed on the exposed surfaces of the silicon containing nanosheets5bcan range from 1 nm to 2 nm. The oxide is formed on all exposed surfaces of the silicon containing nanosheets5b. The thickness of the oxide formed on the exposed surfaces of the silicon containing nanosheets can be conformal.

In some embodiments, following the formation of the oxide surface, e.g., thermal oxide, on the exposed surfaces of the silicon containing nanosheets5b, an etch process may remove the oxide surface selectively to the non-oxidized portion of the silicon containing nanosheets5b. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example, in one embodiment, a selective etch may include an etch chemistry that removes a first material selectively to a second material by a ratio of 10:1 or greater, e.g., 1000:1. For example, the etch process may remove the exposed oxide surface, e.g., thermal oxide, on the exposed surfaces of the silicon containing nanosheets5bselectively to the non-oxidized portion of the silicon containing nanosheets5bthat is underlying the oxidized portion. The etch process may be a dry etch, or a wet etch. For example, reactive ion etch or plasma gas etching can remove the oxidized surfaces of the nanosheets5bthat are exposed. In some embodiments, removing the oxide reduces the dimensions of the nanosheets by 1 nm to 5 nm. For example, the nanosheet dimensions may be reduced by width and height (thickness) by 1 nm to 5 nm. In another embodiment, removing the oxide reduces the dimensions of the nanosheets by 1 nm to 2 nm.

FIG. 5depicts removing the block mask30from the structure depicted inFIG. 4.

In one embodiment, the method continues with the forming a gate structure on the channel region portions of the nanosheets5a,5bthat are depicted inFIG. 5. In some embodiments, forming the gate structure includes forming a high-k gate dielectric layer30directly on the channel region portions of the nanosheets5a,5b, as depicted inFIG. 6. The high-k gate dielectric layer30is conformally deposited to have a substantially equal thickness on each surface of the channel portion of the nanosheets5a,5bthat it is formed on.

Referring toFIG. 6, a high k material is a dielectric having a dielectric constant greater than silicon oxide at room temperature, e.g., 20° C. to 25° C. Exemplary high-k dielectrics suitable for the high-k gate dielectric layer30include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2ONy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.

Referring to theFIG. 6, the high-k gate dielectric layer30can be formed by chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

FIG. 6also depicts forming an extra gate (EG) oxide layer35on the high-k dielectric layer30. As depicted inFIG. 6, the extra gate (EG) oxide layer35is formed conformally around an entirety of the nanosheets5bin the extra gate (EG) region20of the substrate1, but does not pinch off the entirety of the space between the stacked nanosheets5b. More specifically, following the formation of the extra gate (EG) oxide layer35in the extra gate (EG) region20a space remains between the adjacently stacked nanosheets5b. As depicted inFIG. 6, the extra gate (EG) oxide layer35that is formed on the nanosheets5ain the single gate (SG) region15pinches off the space between adjacently stacked nanosheets5a. More specifically, following the formation of the extra gate (EG) oxide layer35in the single gate (SG) region15, the space between the adjacently stacked nanosheets5ais entirely filled.

The extra gate (EG) oxide layer35can be composed of silicon oxide, silicon oxynitride or other oxide containing dielectrics as used in the gate structure of semiconductor devices. The extra gate (EG) oxide layer35may be formed using any deposition process that provides that the extra gate (EG) oxide layer35that is formed on the nanosheets5ain the single gate (SG) region15pinches off the space between adjacently stacked nanosheets5a; and provides that the extra gate (EG) oxide layer35that is formed on the nanosheets5bin the extra gate (SG) region20does not pinch off the space between adjacently stacked nano sheets5b. More specifically, the extra gate (EG) oxide layer35that is formed on the nanosheets5bin the extra gate (SG) region20is conformally deposited on the high-k gate dielectric layer30. The extra gate (EG) oxide layer35can be formed by chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

FIG. 7illustrates one embodiment of forming a work function metal layer40aon the structure depicted inFIG. 6.

The work function metal40amay be selected to provide a p-type work function metal layer and an n-type work function metal layer. As used herein, a “p-type work function metal layer” is a metal layer that effectuates a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal layer ranges from 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. The term “p-type threshold voltage shift” as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device. A “valence band” is the highest range of electron energies where electrons are normally present at absolute zero. In one embodiment, the p-type work function metal layer may be composed of titanium and their nitrided/carbide. In one embodiment, the p-type work function metal layer is composed of titanium nitride (TiN). The p-type work function metal layer may also be composed of TiAlN, Ru, Pt, Mo, Co and alloys and combinations thereof.

As used herein, an “n-type work function metal layer” is a metal layer that effectuates an n-type threshold voltage shift. “N-type threshold voltage shift” as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device. The “conduction band” is the lowest lying electron energy band of the doped material that is not completely filled with electrons. In one embodiment, the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV. In one embodiment, the n-type work function metal layer is composed of at least one of TiAl, TiC, TaN, TaC, TiN, HfN, HfSi, or combinations thereof.

The material layers for the work function metal layer40amay be deposited using physical vapor deposition (PVD), plating or chemical vapor deposition (CVD).

Review ofFIG. 7illustrates that the extra gate (EG) oxide layer35that is formed on the nanosheets5ain the single gate (SG) region15pinches off the space between adjacently stacked nanosheets5a. This means that the work function metal layer40acan only be formed on the exterior surfaces of the stacks10ain the single gate (SG) region15, which provides only a single gate structure.FIG. 7also illustrates that the extra gate (EG) oxide layer35that is formed on the nanosheets5bin the double gate (SG) region25does not pinch off the space between adjacently stacked nanosheets5b, which provides that the work function metal layer40acan be deposited to encapsulate each of the nanosheets5bin a gate all around (GAA) structure. This provides that the double gate region25may include multiple gate structures.

FIGS. 11-17depict yet another embodiment of the present disclosure.

Although not depicted in the supplied figures, a gate electrode may then be formed on the work function metal layer40a. In various embodiments, the gate electrode is a metal, where the metal may be tungsten (W), tungsten nitride (WN) or combinations thereof. In one or more embodiments, the gate electrode is tungsten (W). In other embodiments, the gate electrode may be doped semiconductor material, such as n-type doped polysilicon. The gate electrode may be deposited by CVD, e.g., plasma enhanced chemical vapor deposition (PECVD). The material layers for the gate electrode40amay be deposited using physical vapor deposition, such as plating, electroplating, electroless deposition, sputtering and combinations thereof.

The gate electrode is optional and may be omitted.

The gate electrode, the metal work function layer40a, the extra gate oxide layer35and the high-k gate dielectric layer30provide a functional gate structure to each stack10a,10bof suspended nanosheets5a,5b. The functional gate structure operates to switch the semiconductor device from an “on” to “off” state, and vice versa.

FIGS. 8-10depict another embodiment of the present disclosure. The embodiment that is depicted inFIGS. 8-10beings with the structure previously described with reference toFIG. 6and provides for the formation of a nominal gate all around (GAA) device in the single gate region15, and an extra gate (EG) device in the extra gate (EG) region20.

FIG. 8depicts forming a block mask41over the extra gate region20depicted inFIG. 6, leaving the single gate region15exposed. The block mask41that is depicted inFIG. 8is similar to the block mask identified by reference number25inFIG. 3. Therefore, the description of the block mask identified by reference number25that is depicted inFIG. 3, as well as its method of formation, is suitable for describing at least one embodiment of the block mask identified by reference number41inFIG. 8. The block mask41that is depicted inFIG. 8protects the stacks10bof nanosheets5bhaving the extra gate (EG) oxide layer35and high-k dielectric layer30present thereon within the extra gate (EG) region20, while exposing the stacks10aof nanosheets5ahaving the extra gate (EG) oxide layer35that is present thereon within the single gate (SG) region715.

FIG. 9depicts removing the extra gate oxide layer35from the single gate region15. In some embodiments, the extra gate oxide layer35is removed by a selective etch. For example, the extra gate oxide layer35can be removed by an etch process that is selective to the high-k gate dielectric layer30. In some embodiments, the etch process may include reactive ion etching (RIE), plasma etching, wet chemical etching or a combination thereof. Following removal of the extra gate oxide layer35from the single gate region15, the block mask41that is present in the extra gate region20is removed, e.g., chemically stripped.

Removing the extra gate oxide layer35from the stacks10aof nanosheets5awithin the single gate region15removes the material that pinches off the space between adjacently stacked nanosheets5a. This reopens the space between the adjacently stacked nanosheets5ain the single gate region15. The exterior surfaces of the nanosheets5awithin the single gate region15are covered by the high-k gate dielectric layer30.

FIG. 10depicts forming a work functional metal40bon the structure depicted inFIG. 9. The work function metal40bis blanket deposited on the single gate region15and the extra gate region20. The portion of the work function metal layer40bthat is formed in the single gate region15is formed directly on the high-k dielectric layer30that is present on the exterior surfaces of the nanosheets5a, wherein the work function metal layer40bentirely surrounds the nanosheets5a. The work function metal layer40balso fills the space between the adjacently stacked nanosheets5ain the stack10aof nanosheets in the single gate region15. Therefore, the work function metal layer40bthat is present within the single gate region15of the embodiment that is depicted inFIG. 10pinches off the space between the adjacently stacked nanosheets5ain the stack10athat is present in the single gate region15. This provides that later deposited material layers, such as gate electrodes, can not be formed between adjacently stacked nanosheets5ain the stack10athat is present in the single gate region15.

The functional gate structures that are formed in the single gate region15provide nominal gate all around (GAA) devices in the single gate region15.

The portion of the work function metal layer40bthat is formed in the extra gate region20is deposited in a manner similar to the portion of the work function metal layer40athat is formed in the extra gate region20that is described with reference toFIG. 7. Therefore, the description of the work function metal layer40athat is depicted inFIG. 7, as well as its method of formation, is suitable for describing the work function metal layer40bthat is depicted inFIG. 10.

A gate electrode (not shown) may be optionally formed on the work function metal layer40bfor each stack10a,10bof nanosheets5a,5b.

The functional gate structures that are formed in the extra gate region20provide extra gate (EG) devices on the channel regions provided by the nanosheets5bin the extra gate region20.

Following the formation of the work function metal layer40b, a gate electrode can be formed for each functional gate structure. The gate electrode, the metal work function layer40b, the extra gate oxide layer35and the high-k gate dielectric layer30provide a functional gate structure to each stack10a,10bof suspended nanosheets5a,5b.

FIGS. 11-17depict another embodiment of the present disclosure that employs a metal nitride layer60to provide a single gate (SG) device and an extra gate (EG) device.FIG. 11depicts one embodiment of an initial structure in which a metal nitride layer60is blanket deposited on the structure depicted inFIG. 6without forming the extra gate oxide layer at this stage of the process flow.

The metal nitride layer60may be composed of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride or a combination thereof. The titanium nitride layer60may be deposited using chemical vapor deposition (CVD) and/or physical vapor deposition (PVD). For example, plasma enhanced chemical vapor deposition (PECVD) may be employed to form the metal nitride layer60. The metal nitride layer60may also be formed using a sputtering method. In further embodiments, the metal nitride layer60may be formed using electroplating and/or electroless plating.

Referring toFIG. 11, the metal nitride60is formed directly on the high-k dielectric layer30. As depicted inFIG. 11, the metal nitride60is formed conformally around an entirety of the nanosheets5bin the extra gate (EG) region20of the substrate1, but does not pinch off the entirety of the space between the stacked nanosheets5b. More specifically, following the formation of the metal nitride layer60in the extra gate (EG) region20, a space remains between the adjacently stacked nanosheets5b. As depicted inFIG. 11, the metal nitride layer60that is formed on the nanosheets5ain the single gate (SG) region15pinches off the space between adjacently stacked nanosheets5a. More specifically, following the formation of the metal nitride layer60in the single gate (SG) region15, the space between the adjacently stacked nanosheets5ais entirely filled.

FIG. 12depicts forming a block mask45over the stack of nanosheets5ain the single gate region15of the device structure depicted inFIG. 11. The block mask45that is depicted inFIG. 12is similar to the block mask identified by reference number25inFIG. 3. Therefore, the description of the block mask identified by reference number25that is depicted inFIG. 3, as well as its method of formation, is suitable for describing at least one embodiment of the block mask identified by reference number45inFIG. 12. The block mask45that is depicted inFIG. 12protects the stacks10aof nanosheets5ahaving the high-k dielectric layer30present thereon within the single gate (SG) region15, while exposing the stacks10bof nanosheets5bhaving the high-k dielectric layer30that is present thereon within the single gate (SG) region15.

FIG. 13depicts removing the metal nitride layer60from the extra gate region20. In some embodiments, the metal nitride layer60is removed by a selective etch. For example, the metal nitride layer60can be removed by an etch process that is selective to the high-k gate dielectric layer30. In some embodiments, the etch process may include reactive ion etching (RIE), plasma etching, wet chemical etching or a combination thereof. Following removal of the metal nitride layer60from the extra gate region20, the block mask45that is present in the single gate region15is removed, e.g., chemically stripped, as depicted inFIG. 14.

FIG. 14also depicts one embodiment of forming an extra gate oxide layer35. The extra gate oxide layer35is formed in both the single gate region15and the double gate region20. The extra gate oxide layer35that is depicted inFIG. 14is similar to the extra gate oxide layer35that is described with reference toFIG. 6. Therefore, the description of the extra gate oxide layer35that is provided forFIG. 6is suitable for describing at least one embodiment of the extra gate oxide layer35that is depicted inFIG. 14. The extra gate oxide layer35is formed around the entirety of the nanosheets5bwithin the extra gate region20, but is obstructed from being formed around the entirety of the nanosheets5awithin the single gate region15by the presence of the metal nitride layer60.

FIG. 15depicts forming a block mask46over the extra gate region20of the substrate leaving the portions of the extra gate layer35and the underlying metal nitride layer60that are present in the single gate region15exposed. The block mask46that is depicted inFIG. 15is similar to the block mask identified by reference number25inFIG. 3. Therefore, the description of the block mask identified by reference number25that is depicted inFIG. 3, as well as its method of formation, is suitable for describing at least one embodiment of the block mask identified by reference number46inFIG. 15.

FIG. 16depicts one embodiment of removing the portions of the extra gate oxide layer35and the underlying metal nitride layer60that are present in the single gate region15. In some embodiments, the extra gate oxide layer35and the metal nitride layer60is removed by a selective etch. For example, the metal nitride layer60can be removed by an etch process that is selective to the high-k gate dielectric layer30. In some embodiments, the etch process may include reactive ion etching (RIE), plasma etching, wet chemical etching or a combination thereof. Following removal of the extra metal nitride layer60from the single gate region15, the block mask46that is present in the extra gate region20is removed, e.g., chemically stripped.

Removing the metal nitride layer60from the stacks10aof nanosheets5awithin the single gate region15removes the material that pinches off the space between adjacently stacked nanosheets5a. This reopens the space between the adjacently stacked nanosheets5ain the single gate region15. The exterior surfaces of the nanosheets5awithin the single gate region15are covered by the high-k gate dielectric layer30.

FIG. 17depicts forming a work functional metal40con the structure depicted inFIG. 16. The work function metal40cis blanket deposited on the single gate region15and the extra gate region20. The portion of the work function metal layer40bthat is formed in the single gate region15is formed directly on the high-k dielectric layer30that is present on the exterior surfaces of the nanosheets5a, wherein the work function metal layer40centirely surrounds the nanosheets5a. The work function metal layer40calso fills the space between the adjacently stacked nanosheets5ain the stack10aof nanosheets in the single gate region15. Therefore, the work function metal layer40cthat is present within the single gate region15of the embodiment that is depicted inFIG. 17pinches off the space between the adjacently stacked nanosheets5ain the stack10athat is present in the single gate region15. This provides that later deposited material layers, such as gate electrodes, can not be formed between adjacently stacked nanosheets5ain the stack10athat is present in the single gate region15.

Following the formation of the work function metal layer40b, a gate electrode can be formed for each functional gate structure. The gate electrode, the metal work function layer40b, the extra gate oxide layer35and the high-k gate dielectric layer30provide a functional gate structure to each stack10a,10bof suspended nanosheets5a,5b.