Parallel processing in hardware accelerators communicably coupled with a processor

In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

TECHNICAL FIELD

The present disclosure relates to methods and systems for parallel processing in hardware accelerators that are communicably coupled with a processor.

BACKGROUND

In accordance with an example scenario, data-centric applications, such as, for example, data communication, image processing, complex mathematical and logical computations, has increased the amount of data processed by a processor in electronic devices. The performance of the processor is based on the instructions per second that the processor is able to perform. Such computationally intensive applications consume a relatively large amount of time and power of the processor, which affects other native operations performed by the processor. Although processing performance is enhanced by employing multi-core processors (for example, two or more processors working together jointly), it is noted that the performance gain of the multi-core processors decreases substantially. Alternatively, in order to increase the performance of such devices, the computationally intensive operations are performed by separate hardware accelerators that operate with the processor. However, effective utilization of the hardware accelerators by the processor in executing the computationally intensive applications is a challenge.

SUMMARY

In an embodiment, a device for parallel processing includes a processor, a plurality of hardware accelerator engines and a hardware scheduler. The processor is configured to schedule an execution of a plurality of instruction threads. Each instruction thread of the plurality of instruction threads includes a plurality of instructions. The plurality of instructions is associated with an execution sequence. The plurality of hardware accelerator engines is configured to perform the scheduled execution of the plurality of instruction threads. The hardware scheduler is communicatively coupled with the processor and the plurality of hardware accelerator engines. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine from among the plurality of hardware accelerator engines is configured to execute a corresponding instruction from among the plurality of instructions. The plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by the plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

In an embodiment, a method for parallel processing includes accessing an executable algorithm by a processor. The method further includes identifying a plurality of instruction threads in the executable algorithm by a processor, where each instruction thread of the plurality of instruction threads includes a plurality of instructions. In an embodiment, the plurality of instructions are associated with an execution sequence. The method also includes scheduling, with the processor, the plurality of instruction threads to be executed by a plurality of hardware accelerator engines. In an embodiment, each instruction thread of the plurality of instruction threads is scheduled is performed by the plurality of hardware accelerator engines in a sequential manner. In an embodiment, each instruction from among the plurality of instructions is executed by a corresponding hardware accelerator engine from among the plurality of hardware accelerator engines. The plurality of instructions threads are performed by the plurality of hardware accelerator engines in a parallel manner based on the execution sequence of the plurality of instructions and an availability status of each of the plurality of hardware accelerator engines.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present technology. It will be apparent, however, to one skilled in the art that the present technology can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form only in order to avoid obscuring the present technology.

Reference in this specification to ‘one embodiment’ or ‘an embodiment’ means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present technology. The appearance of the phrase ‘in one embodiment’ or ‘in an embodiment’ in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which are exhibited by some embodiments and not by others. Similarly, various requirements are described which are requirements for some embodiments but not for other embodiments.

Moreover, although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to said details are within the scope of the present technology. Similarly, although many of the features of the present technology are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the present technology is set forth without any loss of generality to, and without imposing limitations upon, the present technology.

Pursuant to an example scenario, a processor, for example a central processing unit (CPU), executes instructions by accessing data from a memory embodied in the processor or otherwise accessible to the processor. In a case, where the instructions involve intensive computations, for example, pixel matching between media frames or coding a sequence of frames in motion estimation for a lossless compression, the performance of the processor degrades. In such cases, the instructions that involve exhaustive computation, such as complex arithmetic operations on floating point data for pixel matching are executed by another processor, such as a hardware accelerator. The hardware accelerator is communicatively associated with the processor and is configured to perform specialized functions. Various embodiments of the present technology are capable of running independent sequences of algorithm in parallel in a plurality of hardware accelerators. Various embodiments of the present technology are herein disclosed in conjunction withFIGS. 1-6.

Referring toFIG. 1, a device100including a processor102and a data processing system104communicatively associated with the processor102is shown, according to an embodiment of the present technology. An example of the processor102is a microprocessor, a digital signal processor, a central processing unit or an application specific instruction set processor. The data processing system104is operable to perform computationally intensive tasks to aid the processor102. In various implementations, the data processing system104is configured to perform specialized functions. For instance, without loss of generality, the data processing system104is designed to execute the specialized functions that are computationally intensive such as Fast Fourier Transform (FFT), floating point arithmetic, motion estimation of objects between media frames, video compression, and the like. For example, in executing instructions associated with a binary search algorithm for block matching in video compression (for example, blocks having resolutions of 1024×768 pixels), the complexity in finding a matching block for a given block is log2(N), where N is the number of pixels. In some implementations, such computationally intensive tasks are allocated to the data processing system104by the processor102, and the processor102continues executing native instructions.

In an embodiment, the processor102is configured to receive a plurality of instructions associated with execution of an algorithm. In an embodiment, the processor102is configured to create a plurality of instruction threads from the plurality of instructions based on parallelism present in the algorithm. Herein, the parallelism in the algorithm refers to a plurality of independent sequences of instructions (also referred to as ‘the plurality of instruction threads’) that are executed in parallel. For example, the plurality of instruction threads are executed in parallel in the data processing system104.

In an example embodiment, the processor102is configured to schedule an execution of the plurality of instruction threads to be executed by the data processing system104. The data processing system104includes a hardware scheduler106and a plurality of hardware accelerator engines (108a-108n). In an example embodiment, the hardware scheduler106is communicatively with the processor102and the plurality of hardware accelerator engines (108a-108n). In an example embodiment, the hardware scheduler106is configured to control the scheduled execution of the plurality of instructions threads (that are scheduled by the processor102). The hardware scheduler106sequences the plurality of instructions in an instruction thread to be executed in the hardware accelerator engines (108a-108n) based on the scheduling of the processor102.

In an example embodiment, each hardware accelerator engine of the hardware accelerator engines (108a-108n) is configured to perform specific one or more instructions of an algorithm. For example, it is assumed that there are four instructions in a motion estimation algorithm between two or more frames, for example search for a predictor vector and determination of an associated Sum of Absolute Difference (SAD) (predicting matching set of pixels of one frame into another frame); a vector search and determination of an associated SAD (finding second level of matching pixels based on the predicted set of pixels); sub pixel search and determination of an associated SAD (determined a refined set of matching pixels) and a skip operation. In an example embodiment, each instruction from among the plurality of instructions is executed in at least one hardware accelerator engine of the hardware accelerator engines (108a-108n). In this example, a hardware accelerator engine108a(also referred to as a ‘predictor engine’) is operable to execute instructions related to searching for the predictor vector and determination of the associated SAD; a hardware accelerator engine108b(also referred to as a ‘vector engine’) is operable to execute instructions related to vector search and determination of the associated SAD. Similarly, a hardware accelerator engine108c(also referred to as a ‘sub pixel engine’) is operable to execute instructions related to sub pixel search and determination of the associated SAD and a hardware accelerator engine108d(also referred to as a ‘skip engine’) is operable to execute instructions related to skip operations.

In various embodiments of the present technology, a set of operations for the motion estimation is performed for a base frame and two frames (for example, between the base frame and a first frame and between the base frame and a second frame) in a parallel manner. For instance, the processor102receives instructions associated with the algorithm to run the motion estimation algorithm (for example, to determine motion vectors) associated with the base frame with each of the first frame and the second frame. The processor102creates a first instruction thread (L1) to determine a first motion vector between the base frame and the first frame and creates a second instruction thread (L2) to determine a second motion vector between the base frame and the second frame, where each of the instruction threads L1and L2includes four instructions, such as the predictor search, the vector search, the sub pixel search and the skip operation. It should be noted that the four instructions are herein provided in each of the L1and L2for merely example purposes, and instruction threads L1and L2include same or different number of instructions.

In an example embodiment, the instructions threads L1and L2are performed by the hardware accelerator engines (108a-108n) in a parallel manner, where each of the instruction threads L1or L2is performed individually in a sequential manner by the hardware accelerator engines (108a-108n). The execution of the instructions in an instruction thread, such as the instruction thread L1is based on an execution sequence. The execution sequence of the instruction thread L1is determined based on an algorithm dependency. For example, if the instruction thread L1executes instructions associated with determining the motion vector for the base frame associated with the first frame, the instruction thread L1includes instructions to perform the predictor search, the vector search and the sub pixel search. The instructions are executed in the sequential manner based on the algorithm dependency. For example, to execute the instruction associated with the sub pixel search requires an output of the execution of the instruction associated with the vector search. In this example, the instruction associated with the predictor search is executed followed by the execution of the instruction associated with the vector search and then the execution of the instruction associated with the sub pixel search. It should be noted that the hardware accelerator engines (108a-108n) do not perform the execution of the instruction associated with the vector search and the instruction associated with the sub pixel search of the instruction thread L1in parallel due to the execution sequence associated with the algorithm dependency. Similarly, the instructions of the instruction thread L2are performed in the sequential manner based on the algorithm dependency.

In an embodiment, the hardware accelerator engines (108a-108n) are shared by the plurality of instruction threads (such as L1and L2) and the availability status of a hardware acceleration engine (for example,108a,108bor108c) is determined based on the fact that whether the hardware acceleration engine is busy in executing corresponding instruction or not. In an embodiment, availability status of the hardware accelerator engine includes a free status and a busy status. In an embodiment, a status between a time instant (for example, a start time) at which a hardware accelerator engine starts execution of an instruction and a time instant (a completion time) at which the execution of the instruction is completed, the availability status of the hardware acceleration engine is the busy status, and otherwise the availability status is the free status. In an embodiment, the availability status also depends upon availability status of one or more of a buffer, an external memory, interfaces and input/output ports.

In an embodiment, the plurality of instruction threads are performed in a parallel manner by the hardware accelerator engines (108a-108n) based on the execution sequence of the plurality of instructions in each of the instruction thread and availability status of the hardware accelerator engines (108a-108n). For example, the instruction associated with the sub pixel search in the instruction thread L1is executed in parallel with the instruction associated with the vector search in the instruction thread L2. The instruction associated with the sub pixel search in the instruction thread L1is executed in the sub pixel engine and at the same time instant the instruction associated with the vector search in the instruction thread L2is executed in the vector engine based on their availability status.

In an embodiment, the processor102receives information associated with execution of each instruction of the plurality of instructions. For example, the processor102receives information associated with each of a time taken to fetch data for an instruction, a time needed by a hardware engine to execute the instruction, resources needed for execution of the instruction, execution sequence of instructions in the plurality of instruction threads and time required for accessing resources associated with the execution of that instruction. The processor102computes execution time associated with the execution of each instruction of the plurality of instructions based on the information received by the processor102. In an example embodiment, the processor102schedules the plurality of instruction threads in the hardware accelerator engines (108a-108n) based on the execution time, such that conflicts in the execution of the plurality of instruction threads in the plurality of hardware accelerator engines (108a-108n) are avoided.

In an embodiment, the device100also includes a data manager interface110and a buffer112. The data manager interface110is communicatively associated with the hardware accelerator engines (108a-108n) and is configured to receive output data from the hardware accelerator engines (108a-108n) after executing the instructions, and store the output data in the buffer112. In an example embodiment, the data manager interface110merges the output data associated with the plurality of instruction threads that were executed in parallel.

In some example embodiments, the data manager interface110sends timing information associated with execution of instructions of instruction threads to the processor102. For instance, as the availability status of a hardware accelerator engine changes from the busy status to the free status (which also signifies a completion of the execution of the corresponding instruction by the hardware accelerator engine), the processor102is notified of the free status of the hardware accelerator engine. In an example embodiment, the processor102utilizes the timing information associated with the execution of an instruction in an instruction thread to reschedule at least one instruction (for example, subsequent instructions in the instruction thread or the same instruction in other instruction threads). The rescheduling of the at least one instruction of the plurality of instruction threads by the processor102, reduces a total execution time of the plurality of instruction threads and thereby optimizing the scheduling/execution of the plurality of instruction threads. In some embodiments, the processor102is operable to provide the timing information to the hardware scheduler106, such that the hardware scheduler106controls execution of the rescheduled plurality of instructions.

In an example embodiment, the data manager interface110determines the availability status of the hardware accelerator engines (108a-108n) and the buffer112for executing the plurality of instruction threads. The buffer112is communicatively associated with the hardware scheduler106and the data manager interface110. In an example embodiment, the buffer112provides data to the hardware accelerator engines (108a-108n) for executing the plurality of instruction threads. The output data obtained after executing the plurality of instruction threads is stored in the buffer112.

FIG. 2illustrates a process200for execution of two instruction threads in parallel by a plurality of hardware accelerator engines. Without loss of generality, in an example, the process200relates to motion estimation between media frames. The process200is executed on a device, such as the device100. For the purposes of the description of the process200, references have been made to the device100as described with reference toFIG. 1. InFIG. 2, mthinstruction in nthinstruction thread is represented by ‘Tn-Sm’. For example, there are three instructions (S1, S2and S3) in each of the instruction threads (T1and T2), so accordingly, T1-S1denotes instruction S1of the instruction thread T1, and so on. In an embodiment, the processor102is configured to create the instruction threads T1and T2such that each of the instruction threads T1and T2include the instructions (S1, S2and S3). In an example embodiment, it should be noted that an instruction that is present in both of the instruction threads (T1and T2) is executed by a same hardware accelerator engine. For example, instruction S1of the instruction thread T1(shown as T1-S1) is scheduled to be executed in a first hardware accelerator engine, instruction S2of the instruction thread T1(shown as T1-S2) is scheduled to be executed in a second hardware accelerator engine and instruction S3of the instruction thread T1(shown as T1-S3) is scheduled to be executed in a third hardware accelerator engine. Similarly, instruction S1of the instruction thread T2(shown as T2-S1) is scheduled to be executed by the first hardware accelerator engine, instruction S2of the instruction thread T2(shown as T2-S2) is scheduled to be executed by the second hardware accelerator engine and instruction S3of the instruction thread T2(shown as T2-S3) is scheduled to be executed by the third hardware accelerator engine.

In an example, such as the motion estimation, the instruction S1is assumed to be associated with predictor search, the instruction S2is assumed to be associated with vector search and the instruction S3is assumed to be associated with sub pixel search. It should be noted that arrows222,224and226represent an execution sequence of the instructions (S1, S2and S3) of the instruction thread T1(shown as,210) and arrows242,244and246represent an execution sequence of the instructions (S1, S2and S3) of the instruction thread T2(shown as,230). For example, the instruction S2of the instruction thread T1is be initiated only after the instruction S1of the instruction thread T1is completed. The arrows252,254and256represent a resource dependency of the instruction thread T2, for example the availability status of the first hardware accelerator engine, the second hardware accelerator engine and the third hardware accelerator engine, for execution of operations associated with the instructions (S1, S2and S3) of the instruction thread T2.

In an example, the device100initiates the data processing system104to start (shown by block202) execution of the instruction threads T1and T2. In an example embodiment, the instruction threads T1and the T2are scheduled to be executed in parallel by the processor102. In the example of the motion estimation, the instruction thread T1includes instructions to determine a first motion vector between a base frame (Fb) and a first frame (F1), and the instruction thread T2includes instructions to determine a second motion vector between the base frame (Fb) and a second frame (F2, that is other than the first frame F1). In an example, a frame (for example, the base frame, the first frame F1and the second frame F2) includes a plurality of pixel blocks and determination of motion vector herein includes a plurality of search operations to determine matching pixel blocks in the frames F1and the F2corresponding to the pixel blocks in the base frame Fb. In an embodiment, arrows, such as the arrow252shows the resource dependency of the instruction (S1) in the instruction thread T2on the instruction (S1) of the instruction thread T1. For instance, the instruction T2-S1needs to be executed by the first hardware accelerator engine that is also required for the execution of the instruction T1-S1of the instruction thread T1. For example, the instruction T2-S1(the predictor vector search in the frame F2for the frame F1) in the instruction thread T2is executed by the first hardware accelerator engine after the first hardware accelerator completes the execution of the instruction T1-S1(predictor vector search in the frame R1for the frame F1) in the instruction thread T1.

In an example embodiment, the instruction thread T1includes the instructions S1, S2and S3for determining a first motion vector for pixel block P1of the base frame Fb in the first frame F1, and the instruction thread T2includes the instructions S1, S2and S3for determining a second motion vector for the pixel block P1of the base frame Fb in the second frame F2. At block212, the process200includes execution of the instruction T1-S1. The instruction T1-S1performs the predictor search for the pixel block P1of the base frame Fb in the first frame F1. The instruction T1-S1is executed in the first hardware accelerator engine. In an embodiment, output of T1-S1is needed for the execution of the instruction T1-S2. At block214, the process200includes execution of the instruction T1-S2for performing vector search operations based on the output of the predictor search associated with the instruction T1-S1. The instruction T1-S2is executed in the second hardware accelerator engine.

At block216, the process200includes execution of the instruction T1-S3for performing the sub pixel search to determine the first motion vector for the pixel block P1between the base frame Fb and the first frame F1based on an output associated with the executed instruction T1-S2by the second hardware accelerator engine. It should be noted that the instruction T1-S3is executed only after the execution of the instruction T1-S2is complete. The instruction T1-S3that performs the sub pixel search is executed in the third hardware accelerator engine.

At block232, the process200includes execution of the instruction T2-S1for performing the predictor search for the pixel block P1of the base frame Fb in the second frame F2. The instruction T2-S1is executed in the first hardware accelerator engine. At block234, the process200includes execution of the instruction T2-S2for performing the vector search operations based on the output of the predictor search (obtained by execution of the instruction T2-S1). The instruction T2-S2is executed in the second hardware accelerator engine. At block236, the process200includes execution of the instruction T2-S3for performing the sub pixel search operations to determine the second motion vector for the pixel block P1between the base frame Fb and the second frame F2. It should be noted that instruction T2-S3is executed only after the execution of the instruction T2-S2is complete. The instruction T2-S3that performs the sub pixel search is executed in the third hardware accelerator engine.

It should be noted that although the instruction threads T1and T2are independent, the instruction threads T1and T2share resources, such as the first hardware accelerator engine, the second hardware accelerator engine and the third hardware accelerator engine to execute the instructions S1, S2and S3, respectively. The instructions T1-S1and T2-S1perform the predictor search in the first hardware accelerator engine. It should be noted that the engines (the first hardware accelerator engine, the second hardware accelerator engine and the third hardware accelerator engine) execute their corresponding instructions of only one instruction thread T1or T2, at a given time instant. Accordingly, the instruction T2-S1is executed by the first hardware accelerator engine only after the execution of the instruction T1-S1. The hardware scheduler106initiates the instruction T2-S1only after execution of the instruction T1-S1. Further, it should be noted that the instruction threads T1and T2are performed in parallel manner, as the blocks214and232are performed simultaneously, and the blocks216and234are performed simultaneously. A timing diagram for the scheduling/execution of the instruction threads T1and T2is further explained with reference toFIG. 3.

FIG. 3illustrates a timing diagram300that shows parallel scheduling of two instruction threads T1and T2according to an embodiment. The timing diagram300ofFIG. 3is herein described for the process200as described in reference toFIG. 2. A processor, such as the processor102, receives information associated with execution time of each instruction of the plurality of instructions and the processor102schedules the plurality of instructions in the plurality of hardware accelerator engines (for example,108a-108n) based on the information. The processor102determines a number of time cycles for execution of each instruction of the instructions (S1, S2and S3) of the instruction threads T1and T2and schedules the instructions (S1, S2and S3) of the instruction threads T1and T2accordingly in the first hardware accelerator engine, second hardware accelerator engine and the third hardware accelerator engine, respectively.

In the example representation ofFIG. 3, at a time instance ‘t1’, the first hardware accelerator engine starts execution of the instruction T1-S1(shown by the block212) of the instruction thread T1as scheduled by the processor102. The processor102determines that the instruction T1-S1requires 4 cycles to execute the instruction T1-S1. As shown in the example representation ofFIG. 3, the first hardware accelerator engine takes 4 cycles to execute the instruction T1-S1. At time instance ‘t5’, the first hardware accelerator engine completes the execution of the instruction T1-S1. Although, the instruction T1-S2(shown by the block214) of the instruction thread T1is executed on the second hardware accelerator engine, it cannot be executed since the execution of the instruction T1-S2depends on output of execution of the instruction T1-S1(for example, due to algorithm dependency). Further, the execution of the instruction T2-S1(shown by the block232) does not depend on output of the execution of the instruction T1-S1, but T2-S1is also not executed in parallel with the instruction T1-S1as the instruction T2-S1is executed once the first hardware accelerator engine is free.

After the completion of the execution of the instruction T1-S1, at a time instance ‘t7’, the instruction T1-S2and the instruction T2-S1are initiated to be executed in the second hardware accelerator engine and the first hardware accelerator engine, respectively. It should be noted that the execution of the T1-S2and T2-S1also start at a time instance ‘t6’ in some implementations. In this example representation, it is assumed that the processor102allocates 3 cycles for the execution of the instruction T1-S2(shown by the block214) in the second hardware accelerator engine and 6 cycles for the execution of the instruction T2-S1(shown by the block232) in the first hardware accelerator engine. At time instance ‘t10’, the second hardware accelerator engine completes execution of the instruction T1-S2but the first hardware accelerator engine is still executing the instruction T2-S1. At time instance ‘t12’, the third hardware accelerator engine starts executing the instruction T1-S3(shown by the block216) as scheduled by the processor102. The instruction T1-S3uses output of the instruction T1-S2to execute the instruction T1-S3. As shown in theFIG. 3, the first hardware accelerator engine completes execution of the instruction T2-S1at a time instance ‘t13’ in 6 cycles as allocated by the processor102. In the example shown inFIG. 3, 5 cycles are allotted for the third hardware accelerator engine, 6 cycles for the first hardware accelerator engine and 4 cycles for the second hardware accelerator engine for the execution of the instructions T1-S3, T2-S1and T2-S2, respectively, based on the execution sequence of the instructions (S1, S2and S3) in the instruction threads T1and T2.

At a time instance ‘t15’, the second hardware accelerator engine starts execution of the instruction T2-S2(shown by the block234) in parallel with the execution of the instruction T1-S3by the third hardware accelerator engine. It should be noted that if there is a third instruction thread T3present in the algorithm, the first hardware accelerator engine is free to execute an instruction S1of the instruction thread T3(after completing the execution of the instruction T2-S1at time instance ‘t13’) in parallel with the instructions T1-S3and T2-S2. At a time instance ‘t17’, the third hardware accelerator engine completes execution of the instruction T1-S3, and becomes available to execute the instruction T2-S3. Although, the third hardware accelerator engine is available for execution of the instruction T2-S3(shown by the block236), the instruction T2-S3is not executed since the instruction T2-S3depends on output of the execution of the instruction T2-S2. Such dependency on output is referred to as the execution sequence of instructions in an instruction thread or algorithm dependency. At time instance ‘t19’, the second hardware accelerator engine completes execution of the instruction T2-S2and output of the instruction T2-S2is available for the execution of the instruction T2-S3.

After the completion of the execution of the instruction T2-S2, at time instance ‘t21’, the third hardware accelerator engine starts execution of the instruction T2-S3as scheduled by the processor102for the next 4 cycles. It should be noted that the other instructions (T1-S1, T1-S2, T1-S3, T2-S1and T2-S2) in the instruction threads T1and T2have completed execution and the first hardware accelerator engine and the second hardware accelerator engine remain idle during next 4 clock cycles. At time instance ‘t25’, the third hardware accelerator engine completes execution of the instruction T2-S3as scheduled by the processor102.

FIG. 4illustrates a timing diagram400that represents scheduling of two instruction threads T1and T2in parallel, according to one embodiment. The timing diagram400is herein described for the process200as described with reference toFIG. 2. If a hardware accelerator engine, such as the first hardware accelerator engine completes execution of an instruction (for example, T1-S1) earlier than number of cycles allotted by the processor102, the hardware accelerator engine remains idle for the remaining number of cycles allotted by the processor102. For example, if the instruction T1-S1(shown by block402) is executed in 2 cycles (for example, between time instances ‘t1-t3’) that is less than the 4 cycles (see,212) initially scheduled by the processor102. In such a scenario, the first hardware accelerator engine remains idle for 2 cycles (see,404). Although, the second hardware accelerator engine receives output of the instruction T1-S1from the first hardware accelerator engine, the second hardware accelerator engine starts execution of the instruction T1-S2at a time instance ‘t7’ as scheduled by the processor102. It should be noted that in the embodiment described with reference toFIG. 3, the first hardware accelerator engine waits until the next instruction scheduled by the processor102, is initiated for execution in the first hardware accelerator engine.

In an embodiment, if an instruction such as T1-S1is executed earlier than the scheduled cycles, the subsequent instructions are initiated without wasting one or more cycles that are freed up to enhance the performance of the device, such as the device100. In an embodiment, the processor102is configured to receive timing information associated with the execution of each instruction of an instruction thread, through the data manager interface110. For example, the processor receives timing information associated with executing the instruction S1of the instruction thread T1in the first hardware accelerator engine. In an embodiment, the processor102receives timing information from the hardware accelerator engines, such as the first hardware accelerator engine, second hardware accelerator engine and the third hardware accelerator engine, through the data manager interface110. The timing information includes a start time and a completion time associated with the execution of the instruction, such as the instruction T1-S1by the first hardware accelerator engine. For example, the processor102receives information when an instruction (for example, T1-S1) starts execution in the first hardware accelerator engine and the time instance at which the first hardware engine completes execution of the instruction T1-S1. The timing information helps the processor102in re-scheduling the remaining instructions of the instruction threads T1and T2if an instruction in the instruction thread completes execution earlier than the allocated number of cycles.

In an embodiment, the availability status of the engine, such as the first hardware engine includes a free status upon the completion event and includes a busy status between the start time and the completion time. For instance, the first hardware accelerator engine starts executing the instruction T1-S1at time instance ‘t1’, the first hardware accelerator engine sends information of the start time to the processor102. The first hardware accelerator engine remains in the busy status when the instruction T1-S1is being executed. In an example, if the instruction T1-S1(shown by the block402) completes execution in 2 cycles (as opposed to the 4 cycles allocated by the processor102for execution of the instruction T1-S1by the first hardware accelerator engine), the first hardware accelerator engine sends an information of the completion time to the processor102. The processor102determines that the first hardware accelerator engine is in the free status and is ready to execute the next instruction T2-S1of the instruction thread T2. An instruction, such as the predictor search in the motion estimation, completes in less number of cycles as initially scheduled by the processor102. For instance, it is assumed that the processor102allots ‘n’ number of cycles for the predictor search based on the probable maximum iterations to obtain the predictor vector for the frame that gives a minimal error. In a scenario, if the first hardware accelerator engine finds a suitable predictor vector (predictor vector that gives minimal error) in a second cycle (as opposed to scheduled ‘n’ cycles, where ‘n’ is a natural number greater than 2), the first hardware accelerator engine provides the predictor vector as output of the predictor search instruction. In an example embodiment, execution sequence of an algorithm having two independent threads T1and T2, each having instructions (S1, S2and S3), represented by the following sequence:Start T1-S1;Wait for T1-S1to complete;Start T1-S2and Start T2-S1;Wait for T1-S2to complete;Start T1-S3;Wait for T2-S1to complete;Start T2-S2;Wait for T2-S2to complete;Wait for T1-S3to complete;Start T2-S3.

The processor102schedules the instruction T1-S1in the first hardware accelerator engine, and the first hardware accelerator engine sends a start event to the processor102indicating that the first hardware accelerator engine is in the busy status executing the instruction T1-S1. The instructions T1-S2and T2-S1wait for the instruction T1-S1to be executed in the first hardware accelerator engine. The execution of the instruction T1-S2depends on the completion of the T1-S1(due to execution sequence as per the algorithm dependency) and the execution of the instruction T2-S1requires the first hardware acceleration engine to be in the free status after completing the execution of the T1-S1. As the first hardware accelerator engine completes the execution of the instruction T1-S1, the first hardware accelerator engine sends the completion event to the processor102indicating that the first hardware accelerator engine is in the free status to execute another instruction. In so much, as the timing information (completion event/time of the instruction T1-S1) is sent to the processor102and if the instruction T1-S1is executed earlier than the scheduled number of cycles, the processor102reschedules the next instructions T1-S2or T2-S1earlier than the initial scheduling of the instructions T1-S2or T2-S1, thereby saving one or more cycles that would have otherwise been wasted as per the one or more embodiments ofFIG. 3.

In an embodiment, the processor102reschedules the execution of other instructions (T1-S2, T2-S1, T1-S3, T2-S2and T2-S3) and optimizes the execution time associated with execution of the instructions (S1, S2and S3) in the instruction threads T1and T2. For example, the processor102schedules the instruction T1-S2to be executed in the second hardware accelerator engine and the instruction T2-S1in the first hardware accelerator engine, based on the reception of the completion event of the instruction T1-S1from the first hardware accelerator engine. In an embodiment, the processor102waits for the completion event from the second hardware accelerator engine that executes the instruction T1-S2. The processor102schedules the instruction T1-S3in the third hardware accelerator engine after it receives the completion event from the second hardware accelerator engine executing the instruction T1-S2. The processor102further determines whether the first hardware accelerator engine has completed the execution of the instruction T2-S1and schedules the instruction T2-S2in the second hardware accelerator engine according to the execution sequence. In some cases, although, the second hardware accelerator engine is in the free status to execute the instruction T2-S2after the execution of the instruction T1-S2, but still the instruction T2-S2waits for the completion of the execution of the instruction T2-S1as per the algorithm dependency.

In an example embodiment, the processor102is configured to wait until the reception of the completion event from the second hardware accelerator engine executing the instruction T2-S2and then determine whether the third hardware accelerator engine has completed the execution of the instruction T1-S3. The instruction T2-S3waits for the instruction T2-S2to be executed, since the instruction T2-S3is sequenced after the execution of the instruction T2-S2. The instruction T2-S3is executed by the third hardware accelerator engine, as the third hardware accelerator engine is in the free status upon completion of the execution of the instruction T1-S3by the third hardware accelerator engine. In an example embodiment, the processor102waits for the completion event of the instructions T1-S3and T2-S2and then initiates execution of the instruction T2-S3in the third hardware accelerator engine. The third hardware accelerator engine sends a completion event to the processor102after executing the instruction T2-S3.

In another example embodiment, the processor102is configured to further optimize the time (number of cycles) for execution of the instructions (S1, S2and S3) in the instruction threads T1and T2. An example algorithm of optimizing the number of cycles for execution of instructions is performed by executing the following pseudo-code:

In the above pseudo-code, if either of the second hardware accelerator engine executing the instruction T1-S2or the first hardware accelerator engine executing the instruction T2-S1complete the execution, a next instruction in the instruction threads (either T1or T2) is dynamically rescheduled for execution (which was otherwise executed as per the initial scheduling in one or more embodiments described with reference toFIG. 3). For example, if the second hardware accelerator engine completes execution of the instruction T1-S2, the processor102is configured to schedule the instruction T1-S3in the third hardware accelerator engine for execution. Alternatively, if the first hardware accelerator engine completes the execution of the instruction T2-S1, the processor102is configured to schedule the next instruction (T2-S2) in the execution sequence. In an example, if the instruction T1-S2is still being executed in the second hardware accelerator engine (if the status of the second hardware accelerator engine is the busy status), the processor102schedules the instruction T2-S2in another hardware accelerator engine (represented by T2-S′2) for the execution of the instruction T2-S2, such as a fourth hardware accelerator engine. The instructions T1-S2and T2-S′2are executed in parallel in their respective hardware accelerator engines. In this embodiment, the instruction T2-S3waits for the completion event from the third hardware accelerator engine executing T1-S3and the fourth hardware accelerator engine executing T2-S′2. After the reception of completion event from the third hardware accelerator engine and the fourth hardware accelerator engine, the instruction T2-S3is executed in the third hardware accelerator engine.

Although the above scheduling adopted by the processor reduces the number of cycles taken for the execution of the instructions (S1, S2and S3) in the instruction threads T1and T2, it is possible to further optimize the scheduling process by exploiting the parallel execution and using of loops to determine the timing information and schedule the instructions accordingly. It should be noted that the processor102is operable to schedule instructions of the multiple instruction threads in multiple hardware accelerator engines by maintaining the execution sequence of the instructions in the multiple instruction threads and following the availability status (that is, resource dependency) of the hardware accelerator engines (for example, first hardware accelerator engine).

FIG. 5is a block diagram of a device500used in a motion estimation application between two multimedia frames, such as video frames, according to an example embodiment. The device500includes a processor502communicatively associated with a motion estimation system504. The motion estimation system504is configured to perform specialised functions such as prediction of matching pixels, matching of pixels between frames, search operations, data macroblock ordering, transformation, sub sampling and other operations for the motion estimation and motion compensation. The processor502performs arithmetical and logical operations and transfers operations involving motion estimation to the motion estimation system504. For example, if a video signal is to be processed for the motion estimation, the processor502schedules and transfers instructions associated with the video signal processing to the motion estimation system504. Herein, the video signal includes any collection of multimedia frames where each frame shows a small change (for example, an object movement between frames) with respect to preceding or succeeding frame.

In an example embodiment, the motion estimation system504includes a hardware scheduler506, a data manager interface508, a predictor engine510, a vector engine512, a sub pixel engine514, a skip engine516and a buffer520. The hardware scheduler506is an example of the hardware scheduler106and the buffer520is an example of the buffer112described with reference toFIG. 1. The description of the hardware scheduler506and the buffer520is omitted for the sake of brevity.

In an embodiment, the predictor engine510is communicatively associated with the hardware scheduler506and is configured to execute prediction instructions. In an embodiment, the predictor engine510is operable to predict pixel blocks in a frame that are likely to be matching to pixels blocks in another frame. For example, there are two frames F1and F2, where each frame has a plurality of pixels (for example, 1920*1080 pixels). In an example, for the pixel block, for example a pixel block of 16*16 in the frame F1, a set of pixel blocks (each having a size of 16*16) are predicted in the frame F2, where a pixel block of the set of pixel blocks in the frame F2is likely to be matching to the pixel block in the frame F1. In an example representation, the frame F1includes the pixel blocks such as A1, A2. . . , An, where each of the Ai (‘i’ is a positive integer between 1 to n) has a fixed number of pixels; and the frame F2includes pixel blocks such as B1, B2, B3. . . , Bn, where each of the Bi (‘i’ is a positive integer between 1 to n) has the fixed number of pixels.

The predictor engine510is operable to predict a plurality of first level pixel blocks in the frame F2that are similar to a pixel block in the frame F1. For instance, the pixel block A5in the first frame F1represents a butterfly and the predictor engine is operable to predict a plurality of first level pixel blocks in the frame F2that are likely to be similar to the pixel block A5in the first frame F1. For example, the predictor engine510predicts that the butterfly appears at any one of the pixel blocks, such as B5, B8, B11, B3, B13, B15and B19of the second frame F2. For instance, it is predicted that the butterfly present in the pixel block A5of the first frame F1moved to one of the pixel blocks B5, B8, B11, B3, B13, B15and B19of the second frame F2. In an embodiment, the predictor engine510selects a first candidate pixel block among the plurality of first level pixel blocks (B5, B8, B11, B3, B13, B15and B19) based on comparison of pixel parameters of the pixel block A5of the first frame F1and pixel parameters of each of the pixel blocks B5, B8, B11, B3, B13, B15and B19of the second frame F2. For example, the pixel block (A5) in the first frame F1is compared with the pixel blocks B5, B8, B11, B3, B13, B15and B19of the second frame F2to determine the pixel block that is most similar to the pixel block A5. Examples of pixel parameters include, but are not limited to, color, texture and intensity. In an example, a difference between a pixel parameter of a pixel in the frame F1and a pixel parameter of a corresponding pixel in the frame F2is computed, and the difference in the pixel parameters is a metric of the similarity value between the two pixels. For example, if the difference is less, the two pixels are likely to be similar. In an embodiment, sum of absolute differences (SAD) in pixel parameters for the corresponding pairs of pixels between two pixel blocks is calculated to determine the similarity measure (or similarity value) between the two pixel blocks. In an example, the SAD is computed between the pixel block A5and the pixel blocks B5, B8, B11, B3, B13, B15and B19. In this example, it is assumed there is the least SAD (for example, having maximum similarity value) between the pixel block A5and the pixel block B8, and accordingly, the pixel B8is determined as the first candidate pixel block.

In an embodiment, the vector engine512is communicatively associated with the hardware scheduler506and is configured to execute vector search instructions. In an embodiment, the vector engine512is configured to determine a plurality of second level pixel blocks that are selected from the neighboring pixel blocks of the pixel block B8. For example, the vector engine512determines the second level pixel blocks B6, B7, B8, B9, and B10. In an embodiment, the vector engine512is configured to determine the pixel block from the pixel blocks B6, B7, B8, B9, and B10that has the maximum similarity value with the pixel block A5.

In an embodiment, the vector engine512is configured to select a second candidate pixel block from among the pixel blocks B6, B7, B8, B9, and B10that has the least SAD with the pixel block A5. In an embodiment, the second candidate pixel block is determined based on comparison of SADs between the pixel block A5and each of the pixel blocks B6, B7, B8, B9, and B10. For example, if the SAD between the pixel block A5and the pixel block B7is least, the vector engine512selects the second level pixel block B7as the second candidate pixel block.

In an embodiment, the sub pixel engine514is communicatively associated with the hardware scheduler506and is configured to execute sub pixel search instructions. In an embodiment, the sub pixel engine514is configured to interpolate plurality of pixels of the second candidate pixel block (the pixel block B7) and their neighboring pixels to determine a plurality of half pixels. The sub pixel engine514is operable to determine a plurality of third level pixel blocks including a combination of the one or more half pixels and one or more of the pixels of the pixel block B7. For example, a plurality of third level pixel blocks B71, B72, B73, B74, B75, B76, B77and B78are determined, where each of these pixel blocks have a same number of pixels as in the pixel block A5. In an embodiment, the sub pixel engine514determines a third candidate pixel block of the second frame F2from the plurality of third level pixel blocks that has pixel parameters similar to the pixel block A5of the first frame (based on the least SAD between the pixel block A5and each of the pixel blocks B71, B72, B73, B74, B75, B76, B77and B78). For example, if the sub pixel engine514determines that the third level pixel block B76has the least SAD with the pixel block A5, the pixel block B76is selected as the matching pixel block for the pixel block A5. It should be noted that the motion estimation algorithm includes further level of interpolations to refine the search process to determine the matching pixel block in the second frame F2for the pixel block A5of the first frame F1.

In an embodiment, a skip engine516is communicatively associated with the hardware scheduler506. The skip engine516is configured to use the neighboring motion vectors (motion vectors that are already determined for a neighboring pixel block) to predict the motion vector of the current pixel block of the frame, without performing search operation to determine a motion vector for a frame. For example, motion vectors of first frame F1and second frame F2are determined by executing instructions in the vector engine512and the sub pixel engine514as C1and C2, respectively. In an embodiment, the skip engine516predicts the motion vector for a third frame from the motion vectors C1and C2of the first frame F1and the second frame F2. It should be noted that the skip engine516is used to predict the motion vector for the third frame assuming a constant global motion between two frames for a moving object. The data manager interface508is configured to combine outputs of the predictor engine510, the vector engine512, the sub pixel engine514and the skip engine516after executing the instruction threads in parallel.

In an embodiment, the predictor engine510, the vector engine512, the sub pixel engine514and the skip engine516are configured to operate in parallel. An example of parallel execution of the instruction threads, where each instruction thread includes instructions associated with one or more of the engines510,512,514and516, is explained with reference to the following table 1.

In an example, a plurality of macro blocks (pixel blocks) are considered in each of the frames for the motion estimation between frames. The size of the pixel blocks vary depending on the application and processing techniques. For example, the size of the pixel block is 8×8, 16×16, 8×16 or 16×8. In an example provided in the Table 1, a motion estimation algorithm is executed for macro block MBn with respect to macro blocks in two directions L0and L1(for example, left or right directions, or up or down directions). The processor502is operable to create two parallel instruction threads for determining the motion vector for the macro block MBn in the two directions L0and L1. For example, in a first instruction thread, a first motion vector is determined for the macro block MBn with respect to another macro block in the direction L0; and in a second instruction thread, a second motion vector is determined for the macro block MBn with respect to another macro block in the direction L1. In the example provided in the Table 1, a motion estimation algorithm is also executed for a macro block MBn+1 with respect to macro blocks in two directions L0and L1. The processor502is operable to create two parallel instruction threads for determining the motion vector for the macro block MBn+1 in the directions L0and L1. For example, in a first instruction thread, a first motion vector is determined for the macro block MBn+1 with respect to another macro block in the direction L0; and in a second instruction thread, a second motion vector is determined for the macro block MBn+1 with respect to another macro block in the direction L1.

In the first T1cycles, the predictor engine510determines a first candidate pixel block for the MBn in L0direction. In the subsequent T2cycles, the predictor engine510and the vector engine512operate in parallel to determine a first candidate pixel block for the MBn in L1direction, a second candidate pixel block for the MBn in L0direction, respectively. As shown in the Table 1, during the T2cycles, the skip engine516is operable to execute the skip instruction to determine a skip motion vector associated with MBn in L0direction. As such, the skip instruction is typically executed independently and does not depend upon the execution of the instructions by the engines510,512,514. Accordingly, the skip engine516also executes the skip instruction in the first T1cycle.

At the subsequent T3cycle, the vector engine512and the sub pixel search engine514are configured to operate in parallel and determine a second candidate pixel block associated with the MBn in the L1direction and a third candidate pixel block associated with MBn in the L0direction, respectively, where the third candidate pixel block is determined as the matching pixel block for the macroclock MBn in the L0direction. During the T3cycle, the skip engine516is operable to execute the skip instruction to determine a skip motion vector associated with MBn in the L1direction. At the subsequent T4cycle, the sub pixel engine514determines a third candidate pixel block associated with MBn in the L1direction, where the third candidate pixel block is determined as the matching pixel block for the macroblock MBn in the L1direction.

At the subsequent T5cycle, the predictor engine510determines a first candidate pixel block for the MBn+1 in L0direction. At the subsequent T6cycle, the predictor engine510, the vector engine512and the skip engine516operate in parallel to determine a first candidate pixel block for the MBn+1 in L1direction, a second candidate pixel block for the MBn+1 in the L0direction and a skip motion vector associated with the MBn+1 in the L0direction, respectively. At the subsequent T7cycles, the vector engine512and the sub pixel search engine514are configured to operate in parallel and determine a second candidate pixel block associated MBn+1 in the L1direction and a third candidate pixel block associated with MBn+1 in the L0direction, respectively, where the third candidate pixel block is determined as the matching pixel block for the macroclock MBn+1 in the L0direction. During the T7cycle, the skip engine516is also configured to determine a skip motion vector associated with MBn+1 in the L1direction. At T8, the sub pixel engine514computes a third candidate pixel block associated with MBn+1 in the L1direction, where the third candidate pixel block is determined as the matching pixel block for the macroclock MBn+1 in the L1direction.

FIG. 6illustrates a flow diagram of an example method600, in accordance with an embodiment. In certain embodiments, operations of the method600are performed by a device, such as, for example, the device100as shown inFIG. 1and/or the device500shown and explained with reference toFIG. 5.

At block605, the method600includes accessing an executable algorithm by a processor such as the processor102. Without loss of generality, an example of the executable algorithm is a motion estimation algorithm between two or more media frames.

At block610, the method600includes identifying a plurality of instruction threads in the executable algorithm by the processor. For instance, in case of motion estimation for a frame with respect to the two frames in two directions with respect to the frame, two instruction threads are performed in parallel for determining the motion estimation in both directions. Each instruction thread includes a plurality of instructions that are the same instructions in each of the instruction thread. In an embodiment, the processor determines the instruction threads that are executed in parallel based on a set of operations performed by the instructions threads. For example, the processor receives instructions associated with executing search operations to determine a matching block for a pixel block of a first frame in a second frame and in a third frame. The pixel block of the first frame is compared with pixel blocks in the second frame and with the pixel blocks of the third frame to determine matching blocks. The processor102determines that search operations to compute matching blocks of the pixel block of the first frame in the second frame and in the third frame are independent and are executed in parallel. In an embodiment, the processor102creates two instruction threads, the first instruction thread includes instructions to determine the matching block for the pixel block of the first frame in the second frame and the second instruction thread includes instructions to determine the matching block for the pixel block of the first frame in the third frame. In an embodiment, the plurality of instructions are associated with an execution sequence. For example, to determine the matching block for the pixel block of the first frame in the second frame, the execution sequence includes executing a predictor search instruction, followed by a vector search instruction and then a sub pixel search instruction in the engines510,512and514, respectively.

At block615, the method600includes scheduling a plurality of instruction threads to be executed by a plurality of hardware accelerator engines. In an embodiment, the processor102is configured to schedule the plurality of instruction threads. For instance, the processor102computes execution time associated with executing each instruction in an instruction thread by a hardware accelerator engine and schedules the plurality of instruction threads based on the execution sequence and availability status of the hardware accelerator engines. In an embodiment, the plurality of instruction threads are scheduled such that each instruction thread from among the plurality of instruction threads is performed by a plurality of hardware accelerator engines in a sequential manner based on the execution sequence of the plurality of instructions. For example, to determine the matching block for the pixel block of the first frame in the second frame, the search operation including predictor search, vector search and sub pixel search are executed sequentially.

In an embodiment, each instruction from among the plurality of instructions is executed by a corresponding hardware accelerator engine from among the plurality of hardware accelerator engines. For example, vector search instructions to determine the matching block for the pixel block of the first frame in the second frame is executed in the vector engine, such as the vector engine512shown inFIG. 5. In an embodiment, the plurality of instructions threads are performed in a parallel manner based on the availability status of the plurality of hardware accelerator engines. For example, when a hardware accelerator engine executes vector search instructions to determine the matching block for the pixel block of the first frame in the second frame, another hardware accelerator engine is operable to execute predictor search instructions to determine the matching block for the pixel block of the first frame in the third frame. An example of the hardware accelerator engines include the predictor engine510, the vector engine512, the sub pixel engine514and the skip engine516that are shown and explained with reference toFIG. 5. The method600further includes merging outputs of the plurality of independent threads associated with the execution of the plurality of instructions.

Without in any way limiting the scope, interpretation, or application of the claims appearing below, effects of one or more of the example embodiments disclosed herein is to provide devices, systems and methods capable of parallel processing in hardware accelerator engines that are coupled with a processor. The scheduling technique exploits parallelism present in the hardware accelerator engines to execute instructions in parallel. The timing information associated with execution of each instruction provided to the processor, improves the performance of the device by scheduling the instructions efficiently. Furthermore, the device is flexible to adapt to different algorithms that system users define for their applications with little modifications to the instructions configured to be executed. It should be noted that reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages should be or are in any single embodiment. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present technology. Thus, discussions of the features and advantages, and similar language, throughout this specification but do not necessarily, refer to the same embodiment.

Various embodiments of the present disclosure, as discussed above, are practiced with steps and/or operations in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the technology has been described based upon these example embodiments, it is noted that certain modifications, variations, and alternative constructions are apparent and well within the spirit and scope of the technology.

Although various example embodiments of the present technology are described herein in a language specific to structural features and/or methodological acts, the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.