REDISTRIBUTION SUBSTRATE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING REDISTRIBUTION SUBSTRATE

A redistribution substrate includes first and second insulating layers; a wiring layer, and a metal layer. The wiring pattern includes a via portion penetrating the first insulating layer and a pad portion on the via portion, the pad portion extending onto an upper surface of the first insulating layer. The metal layer covers an upper surface of the wiring pattern. The second insulating layer is provided on the first insulating layer and covers the pad portion and the metal layer. The wiring pattern includes a first metal. The metal layer includes the first metal and a second metal. The metal layer includes a first portion vertically overlapping the pad portion, and a second portion surrounding the first portion, and a concentration of the first metal in the first portion of the metal layer is greater than a concentration of the first metal in the second portion of the metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0181749, filed on Dec. 22, 2022, and Korean Patent Application No. 10-2023-0019927, filed on Feb. 15, 2023, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure relates to a redistribution substrate and a semiconductor package, and more particularly, relates to a redistribution substrate including a wiring pattern and a semiconductor package including the same.

A semiconductor package is provided to implement an integrated circuit chip for use in electronic products. Typically, a semiconductor package includes a semiconductor chip that is mounted on a printed circuit board (PCB) and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of the electronic industry, various research has been conducted to improve reliability and to reduce a size of the semiconductor packages.

SUMMARY

It is an aspect to provide a redistribution substrate having improved structural stability, a semiconductor package including the same, and a method of fabricating the redistribution substrate.

It is another aspect to provide a redistribution substrate having improved reliability, a semiconductor package including the same, and a method of fabricating the redistribution substrate.

According to one or more example embodiments, there is provided a redistribution substrate comprising a first insulating layer; a wiring pattern including a via portion penetrating the first insulating layer and a pad portion on the via portion, the pad portion extending onto an upper surface of the first insulating layer; a metal layer covering an upper surface of the wiring pattern; and a second insulating layer on the first insulating layer, the second insulating layer covering the pad portion and the metal layer, wherein the wiring pattern includes a first metal, wherein the metal layer includes the first metal and a second metal, wherein the metal layer includes a first portion vertically overlapping the pad portion; and a second portion surrounding the first portion, and wherein a concentration of the first metal in the first portion of the metal layer is greater than a concentration of the first metal in the second portion of the metal layer.

According to one or more example embodiments, there is also provided a semiconductor package comprising a first redistribution substrate; a semiconductor chip mounted on the first redistribution substrate; and a molding layer on an upper surface of the first redistribution substrate and covering the semiconductor chip. The first redistribution substrate includes a first insulating layer; a wiring pattern including a via portion penetrating the first insulating layer and a pad portion on the via portion, the pad portion extending onto an upper surface of the first insulating layer; a metal layer covering an upper surface of the wiring pattern; and a second insulating layer on the first insulating layer, the second insulating layer covering the pad portion and the metal layer. A width of the metal layer is greater than a width of the pad portion, and a thickness of the metal layer is 300 Å to 1500 Å.

According to one or more example embodiments, there is also provided a method comprising forming a first insulating layer on a substrate, the first insulating layer having a first opening; forming a photoresist pattern on the first insulating layer, the photoresist pattern having a second opening on the first insulating layer that is connected to the first opening; forming a wiring pattern filling the first opening and the second opening, the wiring pattern including a first metal; forming a metal layer on the wiring pattern, the metal layer including a second metal; removing the photoresist pattern; and forming a second insulating layer on the first insulating layer, the second insulating layer covering the wiring pattern and the metal layer.

DETAILED DESCRIPTION

Hereinafter, a redistribution substrate, a semiconductor package including the same, and a fabricating method of the redistribution substrate according to various example embodiments will be described with reference to the drawings.

FIG.1is a cross-sectional view of a redistribution substrate according to some example embodiments.FIG.2Ais an enlarged view of region ‘A’ ofFIG.1.FIG.2Bis a plan view of a metal layer according to some example embodiments.

Referring toFIGS.1,2A, and2B, a redistribution substrate100may include a first protective layer101, a second protective layer103, insulating layers110, wiring patterns120, and metal layers130. The insulating layers110may include a first insulating layer111, a second insulating layer112, and a third insulating layer113. The number of insulating layers110is not limited to that shown inFIG.1, and in some example embodiments two or fewer or four or more insulating layers may be provided. The insulating layers110may include, for example, a photo-imageable dielectric (PID) material. The photo-imageable dielectric material may be a polymer. The photo-imageable dielectric material may include, for example, at least one of photosensitive polyimide, polybenzoxazole, phenol-based polymer, and benzocyclobutene-based polymer. InFIG.1, an interface between the insulating layers110is shown for convenience of description, but in some example embodiments, the interface between adjacent insulating layers110may not be distinguished. The metal layers130may include a first metal layer131and a second metal layer132. The wiring patterns120may include a first wiring pattern121and a second wiring pattern122.

The first protective layer101may be provided on a lower surface of the redistribution substrate100. The first protective layer101may include, for example, an insulating polymer.

A first redistribution pad102may be provided on the lower surface of the redistribution substrate100. The first redistribution pad102may be surrounded by the first protective layer101. In some example embodiments, the first protective layer101may completely cover side surfaces of the first redistribution pad102as illustrated inFIG.1. A lower surface of the first redistribution pad102may be exposed from a lower surface of the first protective layer101. In some example embodiments, the lower surface of the first redistribution pad102may be coplanar with the lower surface of the first protective layer101. An upper surface of the first redistribution pad102may be exposed from an upper surface of the first protective layer101. In some example embodiments, the upper surface of the first redistribution pad102may be coplanar with the upper surface of the first protective layer101. The first redistribution pad102may be provided in plural. The first redistribution pads102may include a conductive material. For example, the first redistribution pad102may include copper, aluminum, and/or nickel.

The first insulating layer111may be provided on the first protective layer101. The first insulating layer111may have a first opening OP1connecting an upper surface and a lower surface of the first insulating layer111. In some example embodiments, the first opening OP1may have a narrower width toward the lower surface of the first insulating layer111. The first opening OP1in the first insulating layer111may expose at least a portion of the upper surface of the first redistribution pad102.

The first wiring pattern121may be provided on the first insulating layer111. The first wiring pattern121may include a first via portion121aand a first pad portion121b. The first wiring pattern121may include a first metal. The first metal may include, for example, copper (Cu).

The first via portion121amay be provided in the first opening OP1. Accordingly, the first via portion121amay have a narrower width toward the lower surface of the first insulating layer111. The first via portion121amay be a wiring pattern for vertical wiring within the redistribution substrate100. The first via portion121amay electrically connect the first redistribution pad102and the first pad portion121b. The term ‘Electrical connection/coupling’ herein includes direct connection/coupling or indirect connection/coupling through another conductive component.

The first pad portion121bmay be provided on the first via portion121a. The first pad portion121bmay extend onto the upper surface of the first insulating layer111on the first via portion121a. The first pad portion121bmay electrically connect the first via portion121aand a via portion of another wiring pattern adjacent to the first via portion121a. The first pad portion121bmay be integrally connected to the first via portion121awithout an interface. A width of the first pad portion121bmay be greater than a width of the first via portion121a. In some example embodiments, the width of the first pad portion121bmay be greater than a maximum width of the first via portion121a. That is, the first wiring pattern121may have a T-shaped cross section.

Although not shown, the first wiring pattern121may further include a line portion horizontally connected to the first pad portion121b. The line portion may be a wiring pattern for connecting a plurality of first pad portions121b.

The first wiring pattern121may further include a seed pattern SP provided on a lower surface thereof. The seed pattern SP may cover a lower surface and a sidewall of the first via portion121aand a lower surface of the first pad portion121b, as illustrated inFIG.2A.

The first metal layer131may be provided on the first wiring pattern121. The first metal layer131may cover an entire upper surface of the first wiring pattern121. A lower surface of the first metal layer131may be in direct contact with the upper surface of the first wiring pattern121, that is, the upper surface of the first pad portion121b. A width of the first metal layer131may be greater than a width of the first pad portion121b. The first metal layer131may vertically overlap the entire first pad portion121b. Accordingly, the first metal layer131may be in contact with the entire upper surface of the first pad portion121b. When viewed in a plan view, the first pad portion121bmay be located inside the first metal layer131, as illustrated inFIG.2B. A thickness of the first metal layer131may be smaller than a thickness of the first pad portion121b. For example, the thickness of the first metal layer131may be 300 Å to 1500 Å. In some embodiments, the thickness of the first pad portion121bmay be greater than 1500 Å. A planar shape of the first metal layer131and the first wiring pattern121may be tetragonal, but example embodiments are not limited thereto, and in some example embodiments the planar shape of the first metal layer131may be circular or polygonal.

The first metal layer131may have a first portion R1vertically overlapping the first pad portion121band a second portion R2surrounding the first portion R1. The second portion R2may be a portion that does not vertically overlap the first pad portion121b.

The first metal layer131may include a first metal and a second metal. The first metal and the second metal may include different materials. A concentration of the first metal in the first metal layer131may be greater in the first portion R1than a concentration of the first metal the second portion R2. For example, the first portion R1may be a portion where the first metal and the second metal are mixed, and the second portion R2may be a portion where the second metal is present. In some example embodiments, the first portion R1may be a portion where the first metal and the second metal are mixed, and the second portion R2may be a portion where only the second metal is present. A concentration of the first metal in the first metal layer131may decrease as a distance from the lower surface of the first metal layer131increases. Here, the lower surface of the first metal layer131may correspond to an interface between the first metal layer131and the first pad portion121bor a surface of the first pad portion121bthat is in contact with the first metal layer131. A concentration of the first metal may decrease as a distance to the upper surface of the first metal layer131decreases and as a distance to the side surfaces of the first metal layer131decreases. For example, in a portion adjacent to the upper surface and a portion adjacent to the side surface of the first metal layer131, the second metal may be present but the first metal may not be present. For example, the second metal may include nickel (Ni).

The second insulating layer112may be provided on the first insulating layer111. The second insulating layer112may cover the first pad portion121band the first metal layer131on the first insulating layer111. For example, the second insulating layer112may cover a side surface of the first pad portion121band cover upper, side, and bottom surfaces of the first metal layer131. The second insulating layer112may have a second opening OP2that overlaps a portion of the upper surface of the first metal layer131to expose the portion of the upper surface of the first metal layer131.

The second wiring pattern122may be provided on the second insulating layer112. The second wiring pattern122may be connected to the first metal layer131. The second metal layer132may be provided on an upper surface of the second wiring pattern122. The second wiring pattern122and the second metal layer132may be substantially the same as or similar, respectively, to the first wiring pattern121and the first metal layer131described above, and thus repeated description thereof is omitted for conciseness. In some example embodiments, a portion of the second wiring pattern122may have a different size from a size of the first wiring pattern121, but a pad portion of the second wiring pattern122may have a larger width than a width of a via portion thereof, and the metal layer132may have a greater width than the width of the pad portion of the second wiring pattern122. In some example embodiments, the pad portion of the second wiring pattern122may have a larger width than a maximum width of the via portion thereof.

The third insulating layer113may be provided on the second insulating layer112. The third insulating layer113may cover the second wiring pattern122and the second metal layer132on an upper surface of the second insulating layer112.

The second protective layer103may be provided on the third insulating layer113. The second passivation layer103may cover a portion of an upper surface of the second metal layer132on the third insulating layer113. The second protective layer103may include, for example, an insulating polymer.

A second redistribution pad104may be provided on an upper surface of the redistribution substrate100. The second redistribution pad104may be surrounded by the second protective layer103. In some example embodiments, the second protective layer103may completely cover side surfaces of the second redistribution pad104as illustrated inFIG.1. A lower surface of the second redistribution pad104may be exposed on a lower surface of the second protective layer103. In some example embodiments, the lower surface of the second redistribution pad104may be coplanar with the lower surface of the second protective layer103. The second redistribution pad104may be connected to the second metal layer132. The upper surface of the second redistribution pad104may be exposed on an upper surface of the second passivation layer103. In some example embodiments, the upper surface of the second redistribution pad104may be coplanar with the upper surface of the second passivation layer103. The second redistribution pad104may be provided in plural. The second redistribution pads104may include a conductive material. The second redistribution pads104may include copper, aluminum and/or nickel.

The redistribution substrate100according to various embodiments may include the wiring patterns120in the insulating layers110and the metal layer130covering the upper surfaces of the wiring patterns120. The metal layer130may be provided on the upper surface of the wiring pattern120and have the wider width than the width of the pad portion of the wiring pattern120. The metal layer130may prevent cracks from being generated at an interface between the side surface of the pad portion and the insulating layers110covering the pad portion during heat treatment and increase reliability in a fabricating process of the redistribution substrate100.

FIG.3is a cross-sectional view illustrating a semiconductor package according to some example embodiments. The same reference numerals may be provided for the same elements and configurations, and description overlapping with the description of the same elements described above will be omitted for conciseness.

Referring toFIG.3, a semiconductor package10may include a lower package11and an upper package12. The lower package11may include the first redistribution substrate100, external connection terminals140, a first semiconductor chip200, a second redistribution substrate300, a first molding layer400, and a through electrode500.

The first redistribution substrate100may be substantially the same as or similar to the redistribution substrate100described with reference toFIG.1. The external connection terminals140may be provided on a lower surface of the first redistribution substrate100. The external connection terminals140may be provided on the first redistribution pads102. The external connection terminals140may include solder balls or solder bumps. The external connection terminals140may include, for example, tin, bismuth, lead, silver, or an alloy thereof.

The first semiconductor chip200may be provided on the first redistribution substrate100. The first semiconductor chip200may be, for example, a logic chip or a buffer chip. The logic chip may include an ASIC chip or an application processor (AP) chip. In some example embodiments, the logic chip may include a central processing unit (CPU) or a graphics processing unit (GPU). The ASIC chip may include an application specific integrated circuit (ASIC). In some example embodiments, the first semiconductor chip200may be a memory chip.

The first semiconductor chip200may include first chip pads210provided on a lower surface of the first semiconductor chip200. The first chip pads210may be electrically connected to an integrated circuit formed in the first semiconductor chip200. The first chip pads210may be exposed on the lower surface of the first semiconductor chip200. The first chip pads210may include a conductive material. For example, the first chip pads210may include copper, aluminum, and/or nickel.

A first chip passivation layer220may be provided on the lower surface of the first semiconductor chip200. The first chip passivation layer220may surround the first chip pads210. The first chip passivation layer220may expose lower surfaces of the first chip pads210. The lower surface of the first chip passivation layer220and the lower surfaces of the first chip pads210may be coplanar with each other. The first chip passivation layer220may include an insulating material such as silicon oxide, silicon nitride, or silicon carbonitride.

The first semiconductor chip200may be flip-chip bonded on the first redistribution substrate100. The second redistribution pads104may include inner second redistribution pads104aand outer second redistribution pads104b. In detail, first chip connection terminals250may be provided between the inner second redistribution pads104aand the first chip pads210. The first chip connection terminals250may be connected to the inner second redistribution pads104aand the first chip pads210. Accordingly, the first semiconductor chip200may be electrically connected to the first redistribution substrate100. The first chip connection terminals250may include solder balls or solder bumps. The first chip connection terminals250may include, for example, tin, bismuth, lead, silver, or an alloy thereof.

The through electrode500may be provided on the first redistribution substrate100. The through electrode500may be provided on the outer second redistribution pad104b. The through electrode500may be electrically connected to the first redistribution substrate100through the outer second redistribution pad104b. The through electrode500may be provided in plural. The through electrodes500may be horizontally spaced apart from the first semiconductor chip200. The through electrodes500may surround the first semiconductor chip200. When viewed in a plan view, the through electrodes500may be disposed between a side surface of the first redistribution substrate100and a side surface of the first semiconductor chip200. The through electrodes500may include a conductive material. The through electrodes500may include, for example, copper or tungsten.

The first molding layer400may be provided on the first redistribution substrate100. The first molding layer400may cover the first semiconductor chip200and the through electrodes500on an upper surface of the first redistribution substrate100. The first molding layer400may surround the first chip connection terminals250between the first redistribution substrate100and the first semiconductor chip200. The through electrodes500may vertically penetrate the first molding layer400and be connected to the second redistribution pads104. An upper surface of the first molding layer400may be coplanar with upper surfaces of the through electrodes500. The first molding layer400may include an insulating polymer such as an epoxy-based molding compound (EMC).

The second redistribution substrate300may be provided on the first molding layer400. An insulating layer310, a wiring pattern320, a metal layer330, a third protective layer304, and a third redistribution pad303of the second redistribution substrate300may be substantially the same as or similar to the insulating layer110, the wiring pattern120, the metal layer130, the second protective layer103, and the second redistribution pad104of the first redistribution substrate100, respectively, and thus a detailed description thereof is omitted for conciseness. For example, the metal layer330may be provided on a pad portion of the wiring pattern320within the insulating layer310, and the metal layer330may have a wider width than a width of the pad portion. The metal layer330may vertically overlap the entire wiring pattern320. The wiring pattern320may include a first metal. The metal layer330may include the first metal and a second metal different from the first metal. The metal layer330may include a first portion that vertically overlaps the pad portion and a second portion that does not vertically overlap the pad portion. The first portion may have a higher concentration of the first metal than a concentration of the first metal in the second portion. A concentration of the first metal in the metal layer330may decrease as a distance from a lower surface of the metal layer330increases. The lower surface of the metal layer330may be an interface between the metal layer330and the wiring pattern320or the lower surface of the metal layer330may be a surface where the metal layer330and the wiring pattern320are in contact. A concentration of the first metal may decrease as a distance from an upper surface of the metal layer330decreases, or as a distance from side surfaces of the metal layer330decreases. For example, the first metal may include copper (Cu), and the second metal may include nickel (Ni).

A lowermost wiring pattern320may be exposed on a lower surface of the second redistribution substrate300. For example, a via portion of the lowermost wiring pattern320may pass through a lowermost insulating layer310and be connected to the through electrode500. Accordingly, the first redistribution substrate100and the second redistribution substrate300may be electrically connected by the through electrode500.

The upper package12may be provided on the second redistribution substrate300. The upper package12may include an upper substrate550, second chip connection terminals520, a second semiconductor chip600, and a second molding layer700.

The upper substrate550may be provided on the second redistribution substrate300. The upper substrate550may be a printed circuit board. In some example embodiments, the upper substrate550may be a redistribution substrate. The upper substrate550may include a first substrate pad501on an upper surface of the upper substrate550and a second substrate pad502on a lower surface of the upper substrate550. The first substrate pad501may be exposed onto the upper surface of the upper substrate550. The second substrate pad502may be exposed onto the lower surface of the upper substrate550. Although not shown, the upper substrate550may include wirings electrically connecting the first substrate pad501and the second substrate pad502.

Substrate connection terminals510may be provided between the upper substrate550and the second redistribution substrate300. The substrate connection terminals510may be connected to the second substrate pad502and the third redistribution pad303. The substrate connection terminals510may electrically connect the upper package12and the lower package11.

The second semiconductor chip600may be provided on the upper substrate550. The second semiconductor chip600may have second chip pads610provided on a lower surface of the second semiconductor chip600. The second chip pads610may be electrically connected to an integrated circuit formed in the second semiconductor chip600. The second chip pads610may include a conductive material. For example, the second chip pads610may include copper, aluminum, and/or nickel.

A second chip passivation layer620may be provided on the lower surface of the second semiconductor chip600. The second chip passivation layer620may surround the second chip pads610. The second chip passivation layer620may expose lower surfaces of the second chip pads610. A lower surface of the second chip passivation layer620and the lower surface of the second chip pads610may be coplanar with each other. The second chip passivation layer620may include an insulating material such as silicon oxide, silicon nitride, or silicon carbonitride.

The second semiconductor chip600may be mounted on the upper substrate550. For example, the second semiconductor chip600may be flip-chip bonded on the upper substrate550. The second chip connection terminals520may be provided between the second semiconductor chip600and the upper substrate550. The second chip connection terminals520may be disposed between the second chip pads610and the first substrate pad501. The second chip connection terminals520may be connected to the second chip pads610and the first substrate pad501. Accordingly, the second semiconductor chip600may be electrically connected to the lower package11through the upper substrate550. The second chip connection terminals520may include solder balls or solder bumps. The second chip connection terminals520may include, for example, tin, bismuth, lead, silver, or an alloy thereof. In some example embodiments, the second semiconductor chip600may be wire-bonded on the upper substrate550.

The second molding layer700may be provided on the upper substrate550. The second molding layer700may cover the second semiconductor chip600on an upper surface of the upper substrate550. The second molding layer700may surround the second chip connection terminals520between the upper substrate550and the second semiconductor chip600. In some example embodiments, an underfill may be provided between the upper substrate550and the second semiconductor chip600. The second molding layer700may include an insulating polymer such as an epoxy-based molding compound (EMC).

FIG.4is a cross-sectional view of a semiconductor package according to some example embodiments. The same reference numerals may be provided for the same elements and configurations, and description overlapping with the description of the same elements described above will be omitted for conciseness.

Referring toFIG.4, a semiconductor package30may include a package substrate540, a package connection terminal560, a redistribution substrate1100, chip stacks CS, a semiconductor device710, and a molding layer410.

The package substrate540may be a printed circuit board including wiring patterns printed on upper and lower surfaces. In some example embodiments, the package substrate540may be the same as or similar to the redistribution substrate100described with reference toFIG.1, and thus a repeated detailed description thereof is omitted for conciseness. First upper substrate pads580may be disposed on the upper surface of the package substrate540. The first upper substrate pads580may be exposed onto the upper surface of the package substrate540. First lower substrate pads570may be disposed on the lower surface of the package substrate540. The first lower substrate pads570may be exposed onto the lower surface of the package substrate540. Although not shown, the first upper substrate pads580and the first lower substrate pads570may be electrically connected through wirings in the package substrate540. The first upper substrate pads580and the first lower substrate pads570may include a conductive material. For example, the first upper substrate pads580and the first lower substrate pads570may include copper, aluminum, and/or nickel.

The package connection terminals560may be disposed on the lower surface of the package substrate540. The package connection terminals560may be disposed on the first lower substrate pads570. The package connection terminals560may include solder balls or solder bumps. The package connection terminals560may be one of tin, silver, copper, nickel, bismuth, indium, antimony, or cerium, or an alloy thereof.

The redistribution substrate1100may be provided on the package substrate540. The redistribution substrate1100may be substantially the same as or similar to the redistribution substrate100described with reference toFIG.1, and thus a repeated detailed description thereof is omitted for conciseness. External connection terminals140may be provided between the redistribution pad102and the first upper substrate pads580to electrically connect the package substrate540and the redistribution substrate1100.

A first underfill590may be provided between the package substrate540and the redistribution substrate1100. The first underfill590may surround the external connection terminals140and fill between the external connection terminals140.

The chip stacks CS may be provided on the redistribution substrate1100. Each of the chip stacks CS may include a base semiconductor chip810, lower semiconductor chips820, and upper semiconductor chips850. The lower semiconductor chips820and the upper semiconductor chip850may be sequentially stacked on the base semiconductor chip810. A width of the base semiconductor chip810may be greater than a width of the upper semiconductor chip850and a width of each of the lower semiconductor chips820. A width of the upper semiconductor chip850and a width of each of the lower semiconductor chips820may be substantially the same. The same thickness, size, level, and width of certain components may mean equality within an error range that is capable of occurring in a process. The base semiconductor chip810may include a logic chip, a controller chip, or a buffer chip. The upper semiconductor chip850and the lower semiconductor chips820may include different types of semiconductor chips from the base semiconductor chip810. The upper semiconductor chip850and the lower semiconductor chips820may include memory chips.

The base semiconductor chip810may include first upper chip pads811, first lower chip pads812, and first through electrodes813.

The first lower chip pads812may be provided on a lower surface of the base semiconductor chip810. The first lower chip pads812may be electrically connected to a circuit layer of the base semiconductor chip810. The first upper chip pads811may be provided on an upper surface of the base semiconductor chip810. The first upper chip pads811may be surrounded by a protective layer on the upper surface of the base semiconductor chip810. The first upper chip pads811and the first lower chip pads812may include a conductive material such as copper, aluminum, and/or nickel.

The first through electrodes813may be provided in the base semiconductor chip810. The first through electrodes813may vertically penetrate the base semiconductor chip810. The first through electrodes813may be connected to corresponding first upper chip pads811and first lower chip pads812, respectively. The first through electrodes813may include copper, titanium, tungsten, and/or combinations thereof.

The lower semiconductor chips820may be vertically stacked on the base semiconductor chip810. Hereinafter, configurations of the lower semiconductor chips820will be described based on one lower semiconductor chip820.

The lower semiconductor chip820may include second upper chip pads821, second lower chip pads822, and second through electrodes823.

The second lower chip pads822may be provided on a lower surface of the lower semiconductor chip820. The second lower chip pads822may be electrically connected to a circuit layer of the lower semiconductor chip820. The second upper chip pads821may be provided on an upper surface of the lower semiconductor chip820. The second upper chip pads821may be surrounded by a protective layer on the upper surface of the lower semiconductor chip820. The second upper chip pads821and the second lower chip pads822may include a conductive material such as copper, aluminum, and/or nickel.

The second through electrodes823may be provided in the lower semiconductor chip820. The second through electrodes823may vertically penetrate the lower semiconductor chip820. The second through electrodes823may be connected to corresponding second upper chip pads821and second lower chip pads822, respectively. The second through electrodes823may include copper, titanium, tungsten, and/or combinations thereof.

The upper semiconductor chip850may be disposed on the lower semiconductor chips820. Third lower chip pads825may be provided on a lower surface of the upper semiconductor chip850. The third lower chip pads825may be electrically connected to a circuit layer of the upper semiconductor chip850.

Connection bumps831may be provided between two adjacent semiconductor chips of the base semiconductor chip810, the lower semiconductor chips820, and the upper semiconductor chip850. The connection bumps831may be disposed between corresponding first upper chip pads811, second upper chip pads821, second lower chip pads822, and third lower chip pads825, respectively. The connection bumps831may electrically connect the base semiconductor chip810, the lower semiconductor chips820, and the upper semiconductor chip850.

The non-conductive layers824may fill between adjacent two semiconductor chips of the base semiconductor chip810, the lower semiconductor chips820, and the upper semiconductor chip850. The non-conductive layers824may surround the connection bumps831between the base semiconductor chip810, the lower semiconductor chips820, and the upper semiconductor chip850. The non-conductive layers824may protrude from the side surfaces of the upper semiconductor chip850and the lower semiconductor chips820. The non-conductive layers824may include non-conductive film (NCF) or non-conductive paste (NCP). In some example embodiments, the non-conductive layers824may include an insulating polymer.

The chip stacks CS may be horizontally spaced apart from each other. The chip stacks CS may be mounted on the redistribution substrate1100. Stack connection terminals830may be provided between the chip stacks CS and the redistribution substrate1100. The stack connection terminals830may be disposed to correspond to each of the second redistribution pad104of the redistribution substrate1100and the first lower chip pads812of the base semiconductor chip810. The chip stacks CS may be electrically connected to the package substrate540through the redistribution substrate1100. The stack connection terminals830may include solder balls or solder bumps. The stack connection terminals830may include tin, silver, copper, nickel, bismuth, indium, antimony, cerium, and/or combinations thereof.

A second underfill650may be provided between the base semiconductor chip810and the redistribution substrate1100. The second underfill650may surround the stack connection terminals830between the base semiconductor chip810and the redistribution substrate1100and may fill between the stack connection terminals830.

The semiconductor device710may be provided between the chip stacks CS on the redistribution substrate1100. The semiconductor device710may be a semiconductor chip. The semiconductor device710may include third chip pads720provided on its lower surface. The third chip pads720may be electrically connected to a circuit layer of the semiconductor device710. Third chip connection terminals750may be provided between the third chip pads720and the second redistribution pad104of the redistribution substrate1100. The semiconductor device710may be mounted on the redistribution substrate1100through the third chip connection terminals750.

The molding layer410may be provided on the redistribution substrate1100. The molding layer410may surround the semiconductor device710and the chip stacks CS on an upper surface of the redistribution substrate1100. The molding layer410may expose upper surfaces of the semiconductor device710and the chip stacks CS. In some example embodiments, the molding layer410may bury the semiconductor device710and the chip stacks CS. The molding layer410may include an insulating polymer such as an epoxy-based molding compound.

FIGS.5to12are cross-sectional views illustrating a method of fabricating a redistribution substrate according to some example embodiments.

Referring toFIG.5, a first protective layer101may be formed on a carrier substrate1000. Although not shown, an adhesive layer for adhering the first protective layer101to the carrier substrate1000may be formed. A first redistribution pad102may be formed in the first passivation layer101. The first redistribution pad102may be exposed through upper and lower surfaces of the first protective layer101.

A first insulating layer111may be formed on the upper surface of the first protective layer101. The first insulating layer111may be formed by coating an insulating material on the first protective layer101. The insulating material may include a photo-imageable dielectric (PID) material. The photo-imageable dielectric material may be a polymer. The photo-imageable dielectric material may include, for example, at least one of photosensitive polyimide, polybenzoxazole, phenol-based polymer, and benzocyclobutene-based polymer.

The first insulating layer111may be patterned to form a first opening OP1. The first opening OP1may be formed by performing exposure and development processes on the first insulating layer111. For example, the first opening OP1may be formed by forming a mask on the first insulating layer111and then etching using the mask. The formation of the first insulating layer111may further include a curing process of the insulating material.

The first opening OP1may connect upper and lower surfaces of the first insulating layer111. The first opening OP1may have a narrower width toward the lower surface of the first insulating layer111. The first opening OP1may expose at least a portion of the upper surface of the first redistribution pad102.

Referring toFIG.6, a seed layer SL may be formed on the first insulating layer111. The seed layer SL may be formed by plating or depositing a conductive material on the first insulating layer111. The seed layer SL may conformally cover an upper surface of the first insulating layer111, an upper surface of the first redistribution pad102, and an inner wall of the first opening OP1. The seed layer SL may include a conductive material such as titanium.

A photoresist pattern PR may be formed on the seed layer SL. A third opening PO exposing at least a portion of an upper surface of the seed layer SL may be formed by patterning the photoresist pattern PR. The third opening PO may be formed on the first opening OP1. The third opening PO may be formed to have a larger width than a width of the first opening OP1. At least a portion of the third opening PO may vertically overlap the first opening OP1. For example, when viewed in a plan view, the first opening OP1may be located inside the third opening PO. The third opening PO may be connected to the first opening OP1.

Referring toFIG.7, a wiring pattern120may be formed in the third opening PO and the first opening OP1. The wiring pattern120may be formed through plating using the seed layer SL as an electrode. The wiring pattern120may cover the seed layer SL. The wiring pattern120formed in the first opening OP1may correspond to the via portion121a(inFIG.2). The wiring pattern120formed in the third opening PO may correspond to the pad portion121b(inFIG.2). The wiring pattern120may include a first metal. For example, the first metal may include copper.

Referring toFIG.8, a metal layer130may be formed on the wiring pattern120. The metal layer130may be formed on the wiring pattern120by plating a conductive material. The conductive material may be plated on an upper surface of the wiring pattern120and may extend onto an upper surface of the photoresist pattern PR. The metal layer130may be formed to have a width greater than a width of the wiring pattern120. The metal layer130may be formed to have a thickness of 300 Å to 1500 Å. The metal layer130may include a second metal different from the first metal. For example, the second metal may include nickel.

Referring toFIG.9, the photoresist pattern PR and a portion of the seed layer SL described above may be removed by an etching process. The other portion of the seed layer SL not removed by the etching process may form a seed pattern SP between the first insulating layer111and the wiring pattern120.

Referring toFIG.10, a second insulating layer112may be formed on the first insulating layer111. The second insulating layer112may be formed by applying an insulating material to cover the wiring pattern120and the metal layer130on the first insulating layer111.

The second insulating layer112may be patterned to form a second opening OP2. A method of forming the second opening OP2may be the same as the method of forming the first opening OP1ofFIG.5, and thus a repeated description thereof is omitted for conciseness. The formation of the second insulating layer112may further include a curing process of curing the insulating material.

The second opening OP2may become narrower as a distance from a lower surface of the second insulating layer112decreases. The second opening OP2may expose at least a portion of an upper surface of the metal layer130.

Referring toFIG.11, the processes described with reference toFIGS.6to10may be repeated on the second insulating layer112. Accordingly, a wiring pattern120, a metal layer130, and a third insulating layer113may be formed on the second insulating layer112.

Referring toFIG.12, a second protective layer103may be formed on the third insulating layer113. A second redistribution pad104may be formed in the second passivation layer103. The second redistribution pad104may be exposed onto an upper surface of the second passivation layer103. The second redistribution pad104may be connected to the metal layer130.

Referring back toFIGS.1and5, the carrier substrate1000may be removed thereby forming the redistribution substrate100illustrated inFIG.1. As illustrated inFIGS.5to12, although the method of fabricating the redistribution substrate in which three insulating layers are stacked is shown, example embodiments are not limited thereto. In some example embodiments, the redistribution substrate in which four or more insulating layers are stacked may be fabricated by repeatedly performing the processes ofFIGS.5to11.

In a process of fabricating the redistribution substrate in which the metal layer is not provided, the first metal constituting the wiring pattern may diffuse into the insulating layer on the wiring pattern, and at this time, by-products may be formed by a reaction between the material constituting the insulating layer and the first metal. The by-products remain in the openings of the insulating layer, and thus, voids may be formed in the redistribution substrate. Accordingly, structural stability of the redistribution substrate may be lowered.

By contrast, according to various example embodiments, the method of fabricating the redistribution substrate100may include forming a metal layer130covering the wiring pattern120in the insulating layer110. The metal layer130may include a second metal having a relatively lower diffusivity than a diffusivity of the first metal of the wiring pattern and a lower reactivity with the insulating layer110. Accordingly, by-products may not be formed between the metal layer130and the insulating layer110.

In addition, the metal layer130may function as a barrier layer preventing diffusion of the first metal of the wiring pattern120into the insulating layer110. When forming the insulating layer110, the first metal of the wiring pattern120may diffuse into the metal layer130due to heat accompanying the curing process, but the metal layer130may prevent diffusion of the first metal to the insulating layer110. For example, when a thickness of the metal layer is less than 300 Å, the first metal of the wiring pattern may pass through the metal layer and diffuse to the insulating layer, and thus the by-product described above may be formed. According to some example embodiments, the metal layer130may be formed to a thickness of 300 Å to 1500 Å such that the first metal may be diffused only in a portion adjacent to a lower surface of the metal layer130and may not be diffused to a portion adjacent to an upper and side surfaces of the metal layer130. Accordingly, the metal layer130may prevent formation of by-products due to diffusion of the first metal, and structural stability of the redistribution substrate100may be improved by the metal layer130.

FIGS.13to16are cross-sectional views illustrating a method of fabricating a semiconductor package according to some example embodiments.

Referring toFIG.13, the redistribution substrate100fabricated by the processes described above with respect toFIGS.5to12may be used to form a first redistribution substrate100in a semiconductor package fabricating process. Through electrodes500may be formed on the first redistribution substrate100. The through electrodes500may be formed on the outer second redistribution pad104b. Although not shown, after forming a sacrificial layer on the first redistribution substrate100, a through hole may be formed in the sacrificial layer to expose the outer second redistribution pad104b. The through electrodes500may be formed by performing an electroplating process to fill the through hole. The through electrodes500may extend from an upper surface of the second redistribution pad104bin a direction perpendicular to the first redistribution substrate100.

A first semiconductor chip200may be provided between the through electrodes500on the first redistribution substrate100. The first semiconductor chip200may be flip-chip bonded on the first redistribution substrate100. For example, after providing a first chip connection terminal250on a first chip pad210of the first semiconductor chip200, the first semiconductor chip200may be disposed on the first redistribution substrate100to arrange the inner second redistribution pads104aand the first chip connection terminal250. Thereafter, the first semiconductor chip200may be mounted on the first redistribution substrate100by performing a reflow process on the first chip connection terminal250.

Referring toFIG.14, a first molding layer400may be formed on the first redistribution substrate100. The first molding layer400may cover the first semiconductor chip200and the through electrodes500.

Referring toFIG.15, an upper portion of the molding layer400may be removed through a grinding process. In some example embodiments, upper portions of the through electrodes500and the molding layer400may be removed together. Through the grinding process, an upper surface of the molding layer400and a upper surface of the through electrodes500may be coplanar with each other. Unlike what is shown, the upper surface of the first semiconductor chip200may be exposed through the grinding process. The grinding process may be performed by, for example, a chemical mechanical polishing process (CMP).

A second redistribution substrate300may be formed on the upper surface of the molding layer400. A fourth insulating layer311may be formed on the molding layer400. An opening of the fourth insulating layer311may expose upper surfaces of the through electrodes500. Thereafter, the process described with reference toFIGS.6to12may be performed on the fourth insulating layer311to form the second redistribution substrate300. Accordingly, a lower package11may be fabricated.

Referring toFIG.16, an upper package12may be provided on the lower package11. A second semiconductor chip600may be flip-chip bonded on an upper substrate550. For example, after providing a second chip connection terminal520on a second chip pad610of a second semiconductor chip600, the second semiconductor chip600may be disposed on an upper substrate550to align a first substrate pad501of the upper substrate550to a second chip connection terminal520. Thereafter, a reflow process may be performed on the second chip connection terminal520to mount the second semiconductor chip600on the upper substrate550.

A second molding layer700may be formed on the upper substrate550. The second molding layer700may cover the second semiconductor chip600on an upper surface of the upper substrate550. Accordingly, the upper package12may be fabricated.

The upper package12may be mounted on the lower package11. After the upper package12provides the substrate connection terminal510on the second substrate pad502of the upper substrate550, the substrate connection terminal510may be disposed on the lower package11to be aligned with the third redistribution pad303of the second redistribution substrate300. Thereafter, the upper package12may be mounted on the lower package11by performing a reflow process on the substrate connection terminal510.

Referring back toFIGS.3and5, the carrier substrate1000may be removed from the first redistribution substrate100. At this time, lower surfaces of the first redistribution pads102may be exposed. External connection terminals140may be provided on the lower surfaces of the first redistribution pads102. Accordingly, the semiconductor package10may be fabricated.

In the redistribution substrate according to some example embodiments, the metal layer covering the upper surface of the wiring pattern may be provided in the insulating layer. The metal layer may be provided to have the width wider than the width of the wiring pattern to prevent cracks from being formed between the wiring pattern and the insulating layer. In addition, the metal layer may prevent the by-products caused by the insulating layer and the wiring pattern. Accordingly, the structural stability and reliability of the redistribution substrate and the semiconductor package including the same may be improved.

While various example embodiments are described above, a person skilled in the art may understand that many modifications and variations may be made without departing from the spirit and scope of the present disclosure defined in the following claims. Accordingly, the various example embodiments should be considered in all respects as illustrative and not restrictive, with the spirit and scope of the present disclosure being indicated by the appended claims.