EEPROM cell having a floating-gate transistor within a cell well and a process for fabricating the memory cell

An EEPROM memory device includes a substrate of a first conductivity type having a cell well region of a second conductivity type therein. A floating-gate transistor of the first conductivity type resides in the cell well region and includes a first region separated from a second region by a channel region. A write transistor of the second conductivity type resides in the substrate and includes a first region separated from a second region by a channel region. The second region partially extends into the cell well region and forms a p-n junction with the second region of the floating-gate transistor. The process for fabricating the EEPROM device includes forming the cell well region in the substrate by creating a retrograde doping profile. In operation, the EEPROM device transfers electrons between the cell well region and the floating-gate electrode during both programming and erasing operations.

TECHNICAL FIELD

The present invention relates, generally, to non-volatile memory devices and to methods of fabrication and, more particularly, to EEPROM cells and to methods for their fabrication.

BACKGROUND

The trend in semiconductor fabrication technology is toward the construction of smaller and smaller devices. As the feature size of individual components within a semiconductor device is reduced, the packing density of the devices can be increased. Accordingly, in addition to fabricating devices having reduced feature sizes, cell architecture plays an important role in achieving high packing densities. Electrically-erasable-read-only-memory (EEPROM) devices are particularly difficult to fabricate at high packing density because of the relatively large capacitive coupling necessary to program and erase the device. Further, EEPROM cells require high voltage and low voltage transistors for their operation. These factors lead to relatively large cell size and accompanying smaller storage capability as compared to volatile memory devices, such as dynamic-random-access-memory (DRAM) and static-random-access-memory (SRAM) devices, and the like.

EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs devices can have a two-transistor design or a three-transistor design. A three-transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a floating-gate (or sense) transistor. In a two-transistor device, the functions of the read and write transistor are combined into a single transistor. Although the read and write functions can be combined into a single transistor to produce an EEPROM cell having only two transistors, a relatively large surface area must still be provided to accommodate the capacitive coupling necessary to program and erase the memory cell.

To program an EEPROM cell, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively low voltage Vppis applied to the drain (bit line contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on, allowing the voltage applied to the bit line to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell. In a typical EEPROM cell, the electron path from the floating-gate electrode to the source of the write transistor can involve traversal of a relatively high resistance path in view of the relative positioning of the write transistor and the floating-gate transistor.

To erase an EEPROM cell, a voltage Vccis applied to the gate of the write transistor, a ground potential is applied to the bit line, and a high voltage Vpp+ is applied to the control-gate electrode. Under this bias condition, the high voltage applied to the control-gate electrode is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode. The transfer of electrons during the erase cycle typically takes place through a tunnel oxide layer underlying the floating-gate electrode.

The efficient transfer of electrons to and from the floating-gate electrode is essential to high performance operation of an EEPROM cell. Notably, both two-transistor and three-transistor EEPROM cells depend on rapid transfer of charge between the floating-gate electrode and underlying substrate regions. Accordingly, the operational efficiency of various types of EEPROM cells can benefit from enhancements in the charge transfer structures within the memory cell.

SUMMARY

The present invention is for an EEPROM cell having a floating-gate transistor that is positioned within a cell well region of the substrate. The cell well is specially fabricated to have conductivity opposite that of the substrate in order to accommodate a floating-gate transistor having the same conductivity as the substrate. Further, the cell well region has a doping concentration that is optimized to maximize charge transfer between the cell well region and the floating-gate electrode of the floating-gate transistor.

In one embodiment of the invention, an EEPROM device is provided that includes a substrate of a first conductivity type having a cell well region of a second conductivity type. A floating-gate transistor of the first conductivity type includes a first region, a second region, and a channel region intermediate to the first and second regions all residing in the cell well region. A write transistor of the second conductivity type includes a first region and a channel region residing in the substrate. A second region of the write transistor partially extends into the cell well region and forms a p-n junction with the second region of the floating-gate transistor.

In another embodiment of the invention, an EEPROM device includes a first memory cell and a second memory cell. The first and second memory cells include a floating-gate transistor residing in a cell well region and a write transistor residing in the substrate. A first word line electrically couples the write transistor of the first memory cell and a second word line electrically couples the write transistor of the second memory cell. A floating-gate region is capacitively coupled to the floating-gate electrode of the floating-gate transistors in the first and second memory cells. A bit line is electrically coupled to the write transistors of the first and second memory cells. A first sense line is electrically coupled to the first memory cell and a second sense line is electrically coupled to the second memory cell.

In yet another embodiment of the invention, a process is provided for fabricating an EEPROM device. The process includes providing a substrate of a first conductivity type and forming a cell well region of a second conductivity type in the substrate. A doping process is carried out to create a retrograde doping profile in the cell well region. A floating-gate transistor is formed having a first electrode region in the cell well region. A write transistor is formed having a first electrode region in the substrate and a second electrode region partially extending into the cell well region. The second electrode region of the write transistor forms a p-n junction with the first electrode region of the floating-gate transistor.

DETAILED DESCRIPTION

FIG. 1illustrates a schematic circuit diagram of a two-transistor memory cell10arranged in accordance with one embodiment of the invention. The two-transistor memory cell includes a write transistor12and floating-gate transistor14. A word line16is electrically coupled to the gate electrode of write transistor12. A control-gate region18is capacitively coupled to the gate electrode of floating-gate transistor14. A bit line20is electrically coupled to an electrode region of write transistor12and a sense line22is electrically coupled to an electrode region of floating-gate transistor14. In accordance with the invention, the electrode regions and the channel region of floating-gate electrode14are formed in a cell well region24.

FIG. 2illustrates, in cross-section, memory cell10and a portion of an adjacent memory cell11. Cell well region24resides in a semiconductor substrate26. The active regions of memory cells10and11are electrically isolated from each other by an isolation region28. Floating-gate transistor14includes a gate electrode30overlying a channel region32. A first electrode region34and a second electrode region36reside in cell well24and are separated by channel region32. Write transistor12includes a gate electrode38overlying a channel region40and separated therefrom by a gate dielectric layer41. A first electrode region42resides in substrate26and is separated from a second electrode region44by channel region40. Second electrode region44extends into cell well24and forms a p-n junction46with second electrode region36.

First electrode region42is connected to bit line20by a metal interconnect48. Sense line22makes electrical contact to first electrode region42through a metal interconnect50. Metal interconnects48and50are preferably formed by fabricating contact openings in an interlevel dielectric layer51that overlies semiconductor substrate26. The openings are filled with an electrically conductive metal such as aluminum, an aluminum alloy, a refractory metal, a refractory metal silicide, and the like. As depicted inFIG. 2, interlevel dielectric layer51is planarized to form a planar surface upon which additional metal interconnects can be formed.

In a preferred embodiment, substrate26is a p-type substrate, cell well24is an n-type region, floating-gate transistor14is a p-type transistor, and write transistor12is an n-type transistor. Those skilled in the art will realize, however, that the conductivity of all substrate regions and transistors can be reversed without affecting the operability of the invention.

In accordance with the invention, additional structures are also fabricated to improve the performance of memory cells10and11. A floating-gate protection layer52overlies floating-gate electrode30and a dielectric liner54overlies the active and isolation regions of semiconductor substrate26and the gate electrodes of the floating-gate and write transistors.

In addition to floating-gate protection layer52and dielectric liner54, sidewall spacers56are formed adjacent to the edges of floating-gate electrode30and write transistor gate electrode38. Further, source/drain extension regions58are formed in substrate26beneath the edges of gate electrodes30and38. Additional performance improvement is also obtained by forming refractory metal silicide regions at locations where electrical interconnects are made to gate electrodes and electrode regions in semiconductor substrate26. In a preferred embodiment, the refractory metal silicide regions are formed by a salicide process, in which a refractory metal silicide is selectively formed by a chemical-vapor-deposition (CVD) process. In a preferred embodiment of the invention, gate electrodes30and38are polycrystalline and silicon layers formed by CVD and isotropic etching processes. In addition to polycrystalline silicon, other materials commonly used for the fabrication of semiconductor devices, such as refractory metals, refractory metal silicides, and the like, can also be used to form gate electrodes30and38.

Floating-gate electrode30is separated from cell well24by a tunnel dielectric layer60. In operation of memory cell10, voltages are applied to memory cell10that cause electrons to tunnel through tunneled dielectric layer60. In accordance with the invention, both programming and erasing of floating-gate electrode30take place by the transfer of electrons to and from floating-gate electrode30through cell well24.

In accordance with the invention, electron transfer from cell well24is optimized by creating a retrograde doping profile in cell well24. The retrograde doping profile can be created by several different processes known to those skilled in the art. For example, where cell well24is formed by ion implantation, an ion implantation energy can be selected to place the peak doping concentration at a distance into substrate26away from the substrate surface. Where cell well24is an n-type region, phosphorus ions at an implant dose of about 1E14 ions/cm2to about 1E15 ions/cm2are implanted into substrate26at an implantation energy of about 30 keV to about 80 keV. The implant process places the peak phosphorus doping concentration in substrate26at a depth of about 0.2 microns to about 0.4 microns from the substrate surface. Further, multiple implant steps can be carried out to precisely adjust the doping concentration at various depths in cell well24. Those skilled in the art will appreciate that other n-type dopants, such as arsenic and the like, can be used and that the implant parameters will be adjusted accordingly.

One embodiment of a two-transistor memory array arranged in accordance with the invention is illustrated in FIG.3. The portion of the memory array illustrated inFIG. 3is serviced by word lines16and16′, bit lines20and20′, sense lines22and22′ and control-gate regions18and18′. The elements denoted herein as18′,20′, and so forth, identify features associated with the unselected cells of the memory array.

Bit line20is electrically coupled to the write transistors of memory cell10and adjacent memory cell11. Sense line22is electrically coupled memory cell10and sense line22′ is electrically coupled to adjacent memory cell11. Control-gate region18is capacitively coupled to the floating gate transistors of both memory cell10and adjacent memory cell11.

Operations are carried out on the various memory cells within the array by selecting rows and columns within the array. As shown in Table 1, programming operations take place where programming voltages are applied to the word line and the bit line of a particular cell. Correspondingly, read operations take place where a read voltage is applied to both the word line and the bit line of a particular cell. For example, referring toFIG. 3, where programming voltage is applied to word line16and to bit line20, data will be stored in memory cell10, but not in memory cell11or in any of the remaining cells illustrated in FIG.3.

Voltages applied to the terminals of memory cell10for erase, program and read operations are illustrated below in Table 1.

In Table 1 and inFIG. 3, word line16is designated “WL” and control-gate region18is designated “ACG.” Further, sense line22is designated “PT” and bit line20is designated as “PTG.” Table 1 shows operating voltages for both a selected cell (designed as selected row and selected column) and an adjacent cell (designed unselected row and unselected column). Programming voltage Vpp+ is preferably about 12 volts and bit line voltage Vppis preferably about 10 volts to about 11 volts. Read voltage Vccis preferably about 1.8 volts to about 3.6 volts. The voltage designated Vacgis a bias voltage applied to the control-gate region that can range from about 0 volts to about Vcc. The term “HZ” designates that the terminal voltage is allowed to float during programming of the memory cell. In the unselected memory cell, Vunseldesignates a bias voltage applied to the word line and bit line to avoid unintentional programming of an unselected memory cell.

As shown in Table 1, to program memory cell10, programming voltage is applied to word line16and to bit line20. Since the programming voltage applied to word line16turns write transistor12on, the voltage applied to bit line20is transferred across channel region40to second electrode region44and into cell well24. The high positive voltage impressed on cell well24causes electrons to flow from floating-gate electrode30across tunnel dielectric layer60to cell well24.

To erase memory cell10, high voltage Vpp+ is applied to control-gate region18, which is capacitively coupled to floating-gate electrode30. Cell well24is maintained at ground potential, which results in the flow of electrons from cell well24across tunnel dielectric layer60to floating-gate electrode30.

To read data stored in memory cell10, read voltage Vccis applied to word line16and a small voltage Vacgis applied to control-gate region16. The read voltage is also applied to bit line20. Under these conditions, if a negative charge is stored on floating-gate electrode30, floating-gate transistor14will be on and the read voltage Vccwill be detected at sense line22.

A three-transistor memory cell64arranged in accordance with the invention is illustrated in FIG.4. Memory cell64is formed in a semiconductor substrate85and includes a write transistor66and a floating-gate transistor68. Write transistor66is coupled to a word line70and to a bit line72. Floating-gate transistor68is capacitively coupled to a control-gate region74. In memory cell64, floating-gate transistor68is a complementary-metal-oxide silicon (CMOS) transistor that includes a p-type MOS (PMOS) transistor76and an n-type MOS (NMOS) transistor78. The floating-gate electrode of floating-gate transistor68controls both PMOS transistor76and NMOS transistor78. A sense line80is electrically coupled to NMOS transistor78. In the embodiment illustrated inFIG. 4, PMOS transistor76resides in a cell well82. An output node84(V0) is electrically coupled to both PMOS transistor76and NMOS transistor78.

A cross-sectional view of memory cell64is illustrated in FIG.5. PMOS transistor76includes a floating-gate electrode86overlying a channel region88and separated therefrom by a gate dielectric layer89. A first electrode region90and a second electrode region92are formed in cell well82and separated by channel region88and by lightly doped source/drain regions91. NMOS transistor78includes a floating-gate electrode94overlying a channel region96and separated therefrom by a gate dielectric layer97. NMOS transistor78also includes a first electrode region98and a second electrode region100separated from first electrode region98by channel region96and by lightly doped source/drain regions99.

Write transistor66includes a gate electrode102overlying a channel region104and separated therefrom by a gate dielectric layer105. A first electrode region106is separated from a second electrode region108by channel region104and by lightly doped source/drain regions107. Second electrode region108partially extends into cell well82and forms a p-n junction110with second electrode region92of PMOS transistor76.

Bit line contact72is electrically coupled to first electrode region106of write transistor66by an interconnect112formed in an ILD layer113. Correspondingly, first electrode region98of NMOS transistor78is electrically connected to sense line80by an interconnect114formed in ILD layer113. Output node84is electrically connected to both first electrode region90and second electrode region100by an interconnect116and by a connection lead118. Connection lead118electrically contacts first electrode region90and second electrode region100and overlies an isolation region120.

In similarity with the two-transistor memory cell embodiment, memory cell64includes additional features to enhance the operational performance of the memory cell. For example, a floating-gate protection layer122overlies floating-gate electrodes86and94. Further, a dielectric liner124overlies the surface of semiconductor substrate85and gate electrodes86,94and102. Also, sidewall spacers123are also formed as described above in connection with the two-transistor embodiment.

An alternative embodiment of a three-transistor memory cell is illustrated in the cross-sectional view of FIG.6. In the alternative embodiment, output node before is coupled to PMOS transistor76and NMOS transistor78by separate interconnects128and130. The fabrication of separate interconnects128and130to construct output node84involves an overall simplified fabrication procedure compared to the common interconnects structure illustrated in FIG.5. In particular, by fabricating separate interconnect structures128and130to electrically couple the PMOS and NMOS transistors to an output node84, it is unnecessary to fabricate a connection lead, such as connection lead118. While offering a simplified fabrication process, the embodiment illustrated inFIG. 6results in a slightly larger cell area than the embodiment illustrated in FIG.5. All remaining features of the embodiment illustrated inFIG. 6are identical to those illustrated in FIG.5.

FIG. 7illustrates a schematic diagram of a memory array containing memory cell64integrated with additional memory cells, such as memory cell56. Control-gate region74services numerous memory cells adjacently positioned to one another in the array, such as memory cells64and65.

Word line70is coupled to memory cell65and word line70′ is coupled to adjacent memory cell65. Similarly, sense line80is coupled to memory cell65and sense line80′ is coupled to adjacent memory cell65.

Table 2 illustrates the operational conditions for memory cell64.

The notation set forth in Table 2 has the same meaning and voltage values as that appearing in Table 1 described above. The operational voltages are shown for both selected cells and unselected cells. In similarity with the two-transistor embodiment, voltages Vunselare impressed on the word lines and bit lines coupled to the unselected cells to avoid unintentional programming of these cells while carrying out operations on a selected cell.

The programming of cell64is carried out by applying a high voltage Vpp+ to word line70and applying a programming voltage Vppto bit line72. Further, cell64is erased by applying a high voltage Vpp+ to control-gate region74and a low voltage Vccto word line70. In similarity to the two-transistor embodiment, programming and erasing are carried out by transferring electrons to and from floating-gate electrode86and cell well82. Electron transfer takes place across a tunnel dielectric layer124underlying floating-gate electrode86. In contrast to the two-transistor embodiment, erasing also occurs by transfer of electrons from floating-gate electrode94to channel region96across a gate dielectric layer126. By coupling voltage Vpp+ to floating-gate electrodes86and94through control-gate region74, electrons are transferred onto the floating-gate electrode from two separate substrate regions. Accordingly, the cell erasing operation can be carried out efficiently and at high speed.

Thus, it is apparent that there has been described, in accordance with the invention, an EEPROM cell having a floating-gate transistor within a cell well and a process for fabricating the memory cell that fully provides the advantages set forth above. Those skilled in the art will recognize that numerous modifications and variations can be made without departing from the spirit and scope of the invention. For example, the memory cell can be integrated into numerous semiconductor devices, such as micro processor devices, micro controller devices, programmable logic devices, and the like. Accordingly, all such variations and modifications are intended to be included within the scope of the appended claims and equivalents thereof.