Damascene structure having a reduced permittivity and manufacturing method thereof

A semiconductor device includes a damascene structure and an air gap embedded in the damascene dielectric layer. A method of manufacturing a semiconductor device includes depositing a metal barrier in advance as an etch stop, forming a copper damascene interconnect structure, forming an air gap, and depositing a photosensitive passivation material on the air gap.

This application claims the benefit of priority from prior People's Republic of China Patent Application No. 200510003374.X, filed Dec. 31, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to semiconductor manufacturing. More specifically, this invention relates to a damascene structure having a reduced permittivity and a manufacturing method thereof.

2. Description of the Related Art

Recent developments in semiconductor process technology have led to a decrease in device dimension and an increase in signal speed. With smaller and faster devices, conductive interconnect structures in devices play an increasingly significant role in device performance. A major area of concern is the resistance and capacitance (RC) delay associated with the interconnect structures of devices. As device dimensions become smaller, the RC delay causes greater signal propagation delay and has a larger effect on overall operating speed. Moreover, the RC delay also contributes to power dissipation.

Various efforts have been made to minimize the RC delay effect of interconnections. For example, one way to minimize the RC delay is by reducing the resistance of the interconnect structures. Aluminum interconnects had been widely used in semiconductor devices for decades. With the reduction in chip size, however, aluminum interconnects have been largely replaced by copper, which has a lower resistance than aluminum, in order to the RC delay. As a result, copper processing technology, e.g., copper Back End Of line (BEOL) processing, has been extensively developed. Copper BEOL processing involves damascene interconnection processes, in which trenches are formed in a layer of dielectric material, and copper is used to fill the trenches to form the interconnection. However, there is still a need to further reduce the RC delay of the interconnection, and improve the signal speed.

SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a semiconductor device comprising an etch barrier layer, a dielectric layer over the etch barrier layer, a conductive metal interconnect formed in a first region of the semiconductor device and through the dielectric layer and etch barrier layer, a metal barrier layer formed in a second region of the semiconductor device different from the first region and over the etch barrier layer, an air gap formed in the second region and extending though the dielectric layer and to the metal barrier layer, an upper photosensitive passivation material formed at least over a top portion of the air gap, and a lower photosensitive passivation material formed at a bottom portion of the air gap on the metal barrier layer.

Also in accordance with the present invention, there is provided a method of manufacturing a semiconductor device comprising forming an etch barrier layer, forming a dielectric layer on the etch barrier layer, forming a metal barrier layer over the etch barrier layer in a first region, forming a metal interconnection through the dielectric layer and the etch barrier in a second region different from the first region, forming a metal passivation layer on an uppermost portion of the metal interconnection, applying and patterning a first photosensitive material on the metal passivation layer, etching the metal passivation layer using the patterned photosensitive material to expose the uppermost portion of the metal interconnection, removing the patterned first photosensitive material, applying and patterning a second photosensitive material on the metal passivation layer and the exposed uppermost portion of the metal interconnection, etching the first region to form an air gap extending to the metal barrier layer, the first region being substantially free of metal Interconnections, removing the pattered second photosensitive material, applying a photosensitive passivation material on the air gap, etching the photosensitive passivation material to expose the uppermost portion of the metal Interconnection, and baking the semiconductor device.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Damascene structures include conductive metal interconnects formed within a dielectric material. The RC delay of a damascene structure can be reduced in two ways: by reducing the resistance of the conductive metal interconnects (e.g., by using copper instead of aluminum), and by reducing the capacitance of the dielectric material. The following equation describes line-to-line capacitance:

C=2⁢(Cl+Cv)=2⁢k⁢⁢ɛ0⁢LTW⁡(1W2+1T2)(Equation⁢⁢1)
wherein k is peminittivily, W is the width of each metal line; T is the depth of the metal lines; L is the length of the metal lines; ∈ois vacuum permittivity; Ciis longitudinal capacitance; and Cvis transverse capacitance. As Equation 1 shows, the line-to-line capacitance is directly proportional to permittivity. That is, with a lower permittivity, a smaller line-to-line capacitance can be obtained.

Next, the following equation describes line-to-line RC delay:

RCdelay=2⁢⁢ρ⁢⁢k⁢⁢ɛ0⁢L2⁡(1W2+1T2)(Equation⁢⁢2)
wherein k is permittivity; p is the metal resistivity; W is the width of each metal line; T is the depth of the metal lines; L is the length of the metal lines; ∈ois vacuum permittivity. Again, the line-to-line RC delay is, directly proportional to permittivity. Thus, a lower permittivity, or a lower dielectric constant, will lead to a smaller capacitance, and a reduction in line-to-line RC delay.

Generally, materials having a dielectric constant of about 4 or less are regarded as materials with a low permittivity. One example such a material is silicon dioxide, which has a permittivity of 3.9. Permittivity of vacuum is defined as 1. Permittivity of air is known to be about 1.00054 at room temperature, Thus, the present inventors have considered forming one or more air gaps in a semiconductor device having a damascene structure, in order to reduce the permittivity, and consequently reduce the undesirable RC delay effect on the device.

FIG. 1illustrates a structure consistent with an embodiment of the invention. A semiconductor device100is shone. Semiconductor device100includes alternating layers of a damascene dielectric layer102and an etch barrier layer104. Semiconductor device100may include one or more layers of each of damascene dielectric layer102and etch barrier layer104. Each damascene dielectric layer102preferably has a thickness of between 200 nm and 10,000 nm. Each etch barrier layer104preferably has a thickness of between 10 nm and 200 nm. Various materials may be used in damascene dielectric layers102and etch barrier is104. For example SiO2or FSG (fluorosllicate glass) may be used to form damascene dielectric layers102Etch barrier layers104may be formed from SiN, SiC, or SiON.

A copper interconnect106is formed within a region108embedded within alternating layers of damascene dielectric layer102and etch barrier layer104. A metal passivation layer110is disposed on an uppermost portion of copper interconnect106and damascene dielectric layer102. Metal passivation layer110preferably has a thickness of between 100 nm and 10,000 nm. A variety of materials may be used to form metal passivation layer110, such as SiO2, SiN, SiC, or SiON.

At least one region112in semiconductor device100is predetermined and reserved for subsequently forming an air gap. Copper interconnect108permittivity is formed within region108and not formed within region112. Exemplary values for the size of region112, in which an air gap is to be formed, may be selected from the following group: 2×2 square microns, 3×3 square microns, 4×4 square microns, 5×5 square microns, 3×2 square microns, 4×2 square microns, 5×2 square microns, 4×3 square microns, 5×3 square microns, 5×4 square microns,

In addition, a metal barrier layer114is embedded in region112reserved for forming an air gap. Metal layer114serves as an etch stop during formation of the air gap and may be formed on one of the etch barriers layers104in the present example, metal barrier layer114is formed on the lowest one of the illustrated etch barrier layers104. A typical thickness of metal barrier layer114ranges from 200 nm to 10,000 nm. A number of metal or metal alloys can be used form metal layer114, such as copper, TaN, or Ta.

Next, inFIG. 2, a form photosensitive material200is applied onto metal passivation layer110. First photosensitive material200may comprise an organic solvent, anti-reflective material, cross-linking resin, and micro metal ions. Examples of suitable micro metal ions include Fe, Cu, Na, or K. Various organic solvents may be used. For example, ketone, aether, or paraffin organic solvent may be used as an organic solvent. First photosensitive material200may have a molecular weight of between 5000 and 50,000. In addition, a molar weight ratio of the organic solvent to cross-linking resin may be 1:X, wherein X preferably ranges from 5 to 100. The thickness of first photosensitive material200may vary depending on the manufacturing process, and may be between 100 nm and 850 nm.

One exemplary method of applying first photosensitive material200on metal passivation layer110is described. First photosensitive material200may be applied by means of coating. For example, 1.5 ml to 5 ml of first photosensitive material200may be applied by spin coating onto the entire surface of the wafer that includes device100being fabricated, thus coating the surface of metal passivation110. Thereafter, semiconductor device100includes first photosensitive material200may be soft-baked. A temperature for soft-baking generally ranges from 60° C. to 250° C. For example, first photosensitive material200may be soft-baked at 60° C. 80° C. or 120° C. Soft-baking time generally ranges from 10 seconds to 120 seconds. For example, soft-baking may be performed for an arbitrary duration of 60 seconds, 80 seconds, 100 seconds, or 120 seconds.

First photosensitive material200may then be patterned using lithographic methods in order to form a pattern202. Metal passivation layer110may then be etched using pattern202to expose a top surface of copper interconnect106. The remaining portions of first photosensitive material200may be stripped, and semiconductor device100is cleaned.

Referring toFIG. 3, a second photosensitive material300is disposed on metal passivation layer110. Second photosensitive material300may comprise an organic solvent, anti-reflective material, cross-linking resin, and micro metal ions. As in the case of first photosensitive material200, various organic solvents may be used. For example, ketone, aether, or paraffin organic solvent may be used as an organic solvent. Second photosensitive material300may have a molecular weight of between 5000 and 50,000. In addition, a molar weight ratio of the organic solvent to cross-linking resin may be 1:X, wherein X preferably ranges from 20 to 1000. The thickness of second photosensitive material300may be varied depending on the manufacturing process, and may be between 1000 nm and 5000 nm.

One exemplary method of applying second photosensitive material300on metal passivation layer110is described. Second photosensitive material300may be applied by means of coating. For example, 5 ml to 15 ml of second photosensitive material300may be applied by spin coating onto the entire surface of the wafer that includes device100being fabricated, thus coating the top surface of metal passivation layer110and copper interconnect106. Thereafter, semiconductor device100including second photosensitive material300may be soft-baking. As In the case of first photosensitive material200, the temperature for soft-baking generally ranges from 60° C. to 250° C. For example, second photosensitive material300may be soft-baking at 60° C., 80° C. or 120° C. soft-baking time generally ranges from 10 seconds to 120 seconds. For example, soft-baking may be performed for an arbitrary duration of 60 seconds, 80 seconds, 100 seconds, or 120 seconds.

Second photosensitive material300may be partially removed within region112in which copper interconnect106is not formed, using lithographic methods. Metal passivation layer110, damascene dielectric layer102and etch barrier layer104are subsequently etched to form an air gap302. The etching process may be repeated, if necessary, to remove all of damascene dielectric layers102and etch barrier layers104within region112to form air gap302. The etching process stops at metal barrier layer114. Air gap302is thus formed in region112of semiconductor100. The size of air gap302may typically have, in cross section, a length between 2 μm to 5 μm and a width of between 2 μm to 5 μm, and a depth of 500 μm to 100,000 μm. After forming air gap302, the remaining portions of second photosensitive material300may be, and semiconductor device100is cleaned.

InFIG. 4, a photosensitive passivation material400is deposited on semiconductor device100. Photosensitive passivation material completes the formation of air gap302by covering the top and-bottom air gap302. Photosensitive passivation material400may serve to, protect air gap302by preventing ultraviolet radiation and cosmic particles from penetrating into air gap302. In addition, photosensitive passivation material400may protect semiconductor device100by absorbing mechanical stresses applied to the device.

Photosensitive passivation material400may comprise an organic solvent, photosensitive cross-linking polyimide resin, and micro metal ions. Various organic solvents may be used. For example, ketone, aether, or paraffin organic solvent may be used as an organic solvent Photosensitive passivation material400may have a molecular weight of between 50,000 and 500,000. Photosensitive passivation material400preferably has a permittivity of 1.0 and 4.0. In addition, a molar weight ratio of the organic solvent to photosensitive cross-linking polyimide resin may be 1:X wherein X preferably ranges from 5 to 10,000.

Photosensitive passivation material400may be deposited by repeating the steps of coating a layer of material and baking it. For example, the steps of coating a layer of material and baking it may be repeated between one and ten times. Here, one exemplary method of disposing photosensitive passivation material400is described. First, photosensitive passivation material400may be applied in a first coating. For example, 1.5 ml to 2 ml of photosensitive passivation material400may be applied by spin coating over the entire surface of the wafer that includes device100being fabricated. As a result, photosensitive passivation material400may cover the top surface of metal passivation layer110and copper interconnect106, over air gap302, and even into air gap302, reaching the bottom of air gap302. Device100containing the first coating of photosensitive passivation material400is baked at a temperature of one of 60° C. , 80° C. , or 120° C. , for example, for a duration of 60 seconds, 80 seconds, 100 seconds, or 120 seconds.

Next, photosensitive passivation material400may be applied in a second coating. The second coat of photosensitive passivation material400may be applied by spin coating between 2 ml and 3 ml of material400over the entire wafer surface, and covering the first coating of photosensitive passivation material400. Due to its chemical viscosity and surface stress, the second coating of photosensitive passivation material400will likely not reach the bottom of air gap302and may cause the size of the top opening of air gap302to decrease or, in some cases, even completely close that opening. Device100containing the second coating of photosensitive passivation material400is baked at a temperature of 120° C. , 140° C. 160° C. , 180° C. , or 200° C. , for example, for a duration of 60 seconds, 80 seconds, 100 seconds, or 120 seconds.

Following the second coating, photosensitive passivation material400may be applied in a third coating. The third coating of photosensitive passivation material400may be applied by spin coating 2 ml, 3 ml 4 ml, or 5 ml of material400over the entire wafer surface, and covering the first and second coating of photosensitive passivation material400. Due to its chemical viscosity and surface stress, the third coating of photosensitive passivation material400can close the top opening of air gap302, and thus seal air gap302. Device100containing the third coating of photosensitive passivation material400is baked at a temperature of 90° C. , 100° C. , 120° C. , or 140° C. , for example, a duration of 60 second, 80 second, 100 seconds, or 120 seconds. The number Of coatings, baking times, and the amount of photosensitive passivation material400in each application may vary depending on the size, position, and depth of air gap302.

By the above described method of applying photosensitive passivation material400, a portion of photosensitive passivation material400disposed in region112is deposited at the bottom of air gap302, and another portion is deposited above air gap302, thereby closing air gap302. For example, a lower layer of photosensitive passivation material400of a thickness of between 100 nm and 10,000 nm may be deposited at the bottom of air gap302, and an upper layer of photosensitive passivation material400of a thickness of between 2000 nm and 100,000 nm may be deposited on top of air gap302.

Subsequently, photosensitive passivation material400may be partially removed using lithographic methods to expose the top surface of copper interconnect106. After exposing the top surface of copper interconnect106, the device100may be baked at a temperature of 90° C. , 100° C. , 120° C. , or 140° C. , for example, for a duration of 60 seconds, 80 seconds, 100 seconds, or 120 seconds.

FIG. 5shows a top view of a mask plate500containing an exemplary metal interconnect layout. Metal interconnect layout shows defined regions502, each corresponding to region112on semiconductor device100, reserved for forming air gaps. As illustrated inFIG. 5, reserved regions502are distributed symmetrically on mask plate500. By forming air gaps symmetrically throughout semiconductor device100, one may be able to manufacture a semiconductor device containing air gaps that is stable and able to evenly distribute mechanical and thermal stresses.

Thus, by forming air gaps in a device, one can effectively lower the permittivity in the dielectric layer of the Interconnect structure, and thus reduce the RC delay effect of the interconnect structure on the device performance.

While embodiments of the invention have been described In which an air gap is formed in a semiconductor device containing copper interconnect structures, the invention is not so limited. The benefits of the invention can also be realized by practice in semiconductor devices having interconnect structures formed of one or more conductive metals other than or in addition to copper.

Other embodiments of the invention will be apart to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.