A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

TECHNICAL FIELD

The present disclosure relates to the manufacture of semiconductor devices, such as integrated circuits (ICs). The present disclosure is particularly applicable to forming defect-free relaxed silicon germanium (SiGe) fins for field effect transistors (FETs), particularly for the 7 nanometer (nm) technology node and beyond.

BACKGROUND

Standard techniques to either deliver a fully relaxed or a defect free fin-type FET (FinFET) device include a strain relaxed buffer (SRB) or a fin condensation (e.g., oxide snowplow). However, these standard techniques cannot both yield a fully relaxed film and a defect free substrate. For example, a fully strained epitaxial SiGe growth can be made completely defect-free as deposited. However, when epitaxial (epi) growth parameters or post-deposition processing is introduced to relax the film, defects are incorporated that can result in performance degradation.

A need therefore exists for a methodology enabling preservation of the defect-free nature of the initial fully strained epitaxial growth of SiGe, while relaxing the SiGe and the resulting device.

SUMMARY

An aspect of the present disclosure is a method for forming defect-free relaxed SiGe fins by breaking the crystal lattice by a tilted implant and anneal.

Another aspect of the present disclosure is a method for forming defect-free relaxed SiGe fins by breaking the crystal lattice by selective oxidation.

Another aspect of the present disclosure is a device including defect-free relaxed SiGe fins formed by breaking the crystal lattice by a tilted implant and anneal.

Another aspect of the present disclosure is a device including defect-free relaxed SiGe fins formed by breaking the crystal lattice by selective oxidation.

According to the present disclosure, some technical effects may be achieved in part by a method including: forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming shallow trench isolation (STI) regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting a dopant into the Si substrate below the SiGe fins; and annealing.

Aspects of the present disclosure include methods for forming the SiGe fins by recessing the Si substrate; epitaxially growing a SiGe layer in the recess; and etching the SiGe layer. Another aspect includes a method for forming the SiGe and Si fins by blanket depositing a SiGe layer over the first and second portions of the Si substrate; recessing the SiGe layer over the second portion of the Si substrate; epitaxially growing Si in the recess; implanting germanium (Ge) in the SiGe layer in the first portion of the Si substrate; and etching the Si and SiGe layers. Further aspects include recessing the STI regions below a bottom surface of the SiGe layer in both the first and second portions of the Si substrate; and implanting the dopant in the Si substrate below the SiGe fins and the Si fins. Other aspects include recessing the STI regions 30 to 100 nanometers (nm). Additional aspects include forming the cladding layer of nitride, oxynitride, low-k dielectric material, or silicon oxycarbide (SiOC). Another aspect includes implanting the dopant into the substrate below the SiGe fins by a tilted implantation at an angle of 1 to 25°. Other aspects include annealing by rapid thermal anneal (RTA).

A further aspect includes a method including forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; and oxidizing a bottom portion of the SiGe fins through the STI regions until the STI regions at opposite sides of each SiGe fin are joined beneath the SiGe fin.

Aspects of the present disclosure include forming the SiGe fins by recessing the Si substrate; epitaxially growing a SiGe layer in the recess; and etching the SiGe layer. Another aspect includes forming the SiGe and Si fins by: blanket depositing a SiGe layer over the first and second portions of the Si substrate; recessing the SiGe layer over the second portion of the Si substrate; epitaxially growing Si in the recess; implanting Ge in the SiGe layer in the first portion of the Si substrate; and etching the Si and SiGe layers. Further aspects include oxidizing the SiGe layer under the Si fins. Other aspects include forming the cladding layer of nitride, oxynitride, low-k dielectric material, or SiOC. Additional aspects include oxidizing by RTA. Other aspects include oxidizing at a temperature of 1050° C. to 1150° C. for 10 seconds to 100 seconds.

Another aspect of the present disclosure is a device including: fully strained defect-free SiGe fins, each having a top portion and a bottom portion, on a first portion of a Si substrate; Si fins, each having a top portion and a bottom portion, on a second portion of the Si substrate; STI regions between adjacent SiGe fins and Si fins, the STI regions being below a bottom surface of the SiGe fins and below the top portion of the Si fins; a cladding layer over top and side surfaces of the top portions of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; and a dopant implanted into the Si substrate below the SiGe fins.

Aspects of the device include the SiGe fins including a first SiGe material over a second SiGe material, the first SiGe material having a higher concentration of Ge than the second SiGe material; the Si fins including a Si material over the second SiGe material; and the dopant being implanted in the Si substrate under the second SiGe material of the Si fins and under the SiGe fins. Other aspects include the cladding layer including nitride, oxynitride, low-k dielectric material, or SiOC.

A further aspect of the present disclosure is a device including: fully strained defect-free SiGe fins on a first portion of a Si substrate; Si fins on a second portion of the Si substrate; STI regions between adjacent SiGe fins and Si fins; and a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate, wherein a bottom portion of the SiGe fins is oxidized.

Aspects of the device include the SiGe fins including a first SiGe material over a second SiGe material, the first SiGe material having a higher concentration of Ge than the second SiGe material; the Si fins including a Si material over the second SiGe material; and a bottom portion of the second SiGe material of both the SiGe fins and the Si fins is oxidized.

DETAILED DESCRIPTION

The present disclosure addresses and solves the current problem of strain or defects attendant upon forming FinFET device with SRBs or fin condensation. In accordance with embodiments of the present disclosure, a fully strained, defect-free SiGe is grown patterned. Then, using a protective cladding on the SiGe fins a tilted implant and anneal or a selective oxidation through the STI is performed to break the crystal lattice. In the case of a tilted implant and anneal the connection to the substrate is retained, whereas in case of selective oxidation the SiGe fins effectively become silicon-on-insulator (SOI).

Methodology in accordance with embodiments of the present disclosure includes forming fully strained defect-free SiGe fins on a first portion of a Si substrate. Then, Si fins are formed on a second portion of the Si substrate. Next, STI regions are formed between adjacent SiGe fins and Si fins. Subsequently, a cladding layer is formed over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate. Then, the STI regions are recessed on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins. Next, dopants are implanted into the Si substrate below the SiGe fins followed by an anneal.

Adverting to,FIGS. 1A through 1Eformation of defect-free relaxed SiGe fins by a tilted implant and anneal is illustrated, in accordance with an exemplary embodiment.FIG. 1Arepresents a Si substrate101. The substrate may alternatively be SOI. Adverting toFIG. 1B, a hardmask103is formed over part of the Si substrate101. Then, a recess105is formed in the rest of the Si substrate101to a depth of 10 nm to 100 nm, for example by etching. As illustrated inFIG. 1C, a SiGe layer107is epitaxially grown in the recess105. If necessary, chemical mechanical polishing (CMP) is performed to planarize the SiGe. The SiGe is fully strained and defect-free. InFIG. 1D, the SiGe layer107is etched to form SiGe fins109, which continue to be fully strained and defect-free. In addition, the hardmask102is removed, and the underlying Si substrate101is etched to form Si fins111. The SiGe fins109and Si fins111may, for example, have a pitch of 10 nm to 40 nm and a width of 2 nm to 15 nm. Subsequently, STI regions113are formed between adjacent SiGe fins109and Si fins111. The STI region is formed to a width of 10 nm to 35 nm and a depth of 30 nm to 100 nm. Next, a cladding layer115is formed to a thickness of 5 nm to 10 nm over top and side surfaces of the SiGe fins109and Si fins111and over the STI regions around the Si fins111. The cladding layer is formed of nitride, oxynitride, low-k dielectric material, or silicon oxycarbide (SiOC). Adverting toFIG. 1E, the STI regions113around the SiGe fins109are recessed 10 nm to 20 nm from the top of the STI to reveal a bottom portion of the SiGe fins109. Thereafter, dopants117are implanted into the Si substrate101below the SiGe fins109(i.e., regions119) by a tilted implantation at an angle of 1 to 25°. The dopants may be Si, C, Ge, which may be implanted at a dose of 1e14 to 1e16 and with an energy of 1 to 3 keV. Next, the Si substrate is annealed by RTA at a temperature of 900° C. to 1150° C. for 5 seconds to 300 seconds.

FIG. 2illustrates the method for forming defect-free relaxed SiGe fins by selective oxidation, in accordance with an exemplary embodiment. The embodiment illustrated inFIG. 2begins the same as the first embodiment throughFIG. 1D. Specifically, a fully strained defect-free SiGe layer107is epitaxially grown in a recess105formed in one portion of a Si substrate101. Then, the SiGe layer107is etched to form SiGe fins109. The remaining part of the Si substrate101is etched to form Si fins111. STI regions113are formed between adjacent SiGe fins109and Si fins111. A cladding layer115is formed over top and side surfaces of the SiGe fins109and Si fins111and over the STI regions113around the Si fins111. Then, as illustrated inFIG. 2, the bottom portion of each SiGe fin109is oxidized through the STI regions113until the STI regions113are joined beneath the SiGe fins109.

FIGS. 3A through 3Eillustrate an alternative to the process ofFIGS. 1A through 1Efor forming of defect-free relaxed SiGe fins and Si fins by a tilted implant and anneal, in accordance with another exemplary embodiment. Adverting toFIG. 3A, a SiGe layer303having 20 to 30% Ge is blanket deposited over the Si substrate301. As illustrated inFIG. 3B, the SiGe layer303is recessed to a depth of 10 to 40 nm over a portion of the Si substrate301. A hardmask305is formed over the rest of the substrate, and Si307is epitaxially grown in the recess. InFIG. 3C, the hardmask305is removed, and a new hardmask311is formed over the Si307. Then, Ge is implanted in an upper portion of the SiGe layer303, forming SiGe layer309with a Ge concentration of 40 to 60%. Next, inFIG. 3D, the hardmask311is removed, and the Si307and underlying SiGe layer303are etched to form Si fins each having a Si top portion313and bottom portion315. Correspondingly, the SiGe layer309and the underlying SiGe layer303are etched to form SiGe fins each having top portions317with a high Ge concentration and bottom portions319with a low Ge concentration. The Si fins and the SiGe fins may, for example, have a pitch of 10 nm to 40 nm and a width of 2 nm to 15 nm. Subsequently, STI regions321are formed between adjacent Si fins and SiGe fins. The STI regions321are formed to a width of 10 nm to 35 nm and a depth of 30 nm to 100 nm. A cladding layer323is formed to a thickness of 5 nm to 10 nm over top and side surfaces of the Si fins and SiGe fins. Adverting toFIG. 3E, the STI regions321are recessed to below a bottom surface of the SiGe layer, e.g. 10 to 20 nm. Dopants325are then implanted in the Si substrate301below the SiGe fins and the Si fins (i.e., regions327and329). As inFIG. 1E, the dopants are implanted at an angle of 1 to 25°. The dopants may be Si, Ge, C, which may be implanted at a dose of 1e14 to 1e16 and with an energy of 1 to 3 keV. Then the substrate is annealed by RTA at a temperature of 900° C. to 1150° C. and a pressure of 10 torr to 750 torr for 5 seconds to 300 seconds.

FIG. 4illustrates an alternative to the process ofFIG. 2for forming defect-free relaxed SiGe fins and Si fins by selective oxidation, in accordance with another exemplary embodiment. The process begins the same as the embodiment illustrated inFIGS. 3A through 3Ebut only throughFIG. 3D. Specifically, a SiGe layer303having a Ge concentration of 20 to 30% is blanket deposited over the Si substrate301. The SiGe layer303is recessed to a depth of 10 to 40 over a portion of the Si substrate301. Si307is epitaxially grown in the recess. Ge is implanted in the SiGe layer303on the first portion of the Si substrate301, forming a SiGe layer309with a Ge concentration of 40 to 60%. Then, the Si307and underlying SiGe layer303are etched to form Si fins each having Si top portions313and SiGe bottom portions315. Correspondingly, the SiGe layer309and the underlying SiGe layer303are etched to form SiGe fins each having high concentration Ge top portions317and low concentration Ge bottom portions319. Subsequently, STI regions321are formed between adjacent Si fins and SiGe fins. Then, a cladding layer323is formed to a thickness of 5 nm to 10 nm over top and side surfaces of the Si fins and SiGe fins. Next, the bottom portion of the Si fins and SiGe fins are oxidized through the STI regions321adjacent to the Si fins and SiGe fins until the STI regions are joined beneath the Si fins and SiGe fins.

The embodiments of the present disclosure can achieve several technical effects, such as a fully relaxed and defect free FinFET devices. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated finFET semiconductor devices, particularly for the 7 nm technology node and beyond.