High-performance programmable logic architecture

A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511). Furthermore, the plurality of second logic blocks (505) include a plurality of third logic blocks (525) which may be programmably coupled using a third programmable interconnect network (535). A signal from a third logic block (525) may be programmably coupled to the other logic blocks, the diagnostic block interface (415), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

BACKGROUND OF THE INVENTION

The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.

Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known Classic®, MAX® 5000, MAX® 7000, FLEX® 8000, and FLEX® 10K products made by Altera Corp.

PLDs are generally known in which many LABs are provided in a two dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR.

Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as “chips”), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks.

While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of more complex logic modules and additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.

Furthermore, general purpose programmable logic devices are not generally especially designed for special applications such as emulation and ASIC prototyping. While these general purpose programmable logic devices may have served adequately in the initial development of these applications, it has become increasingly clear that for these applications, general purpose devices have some significant drawbacks. Many general purpose programmable logic devices typically emphasize speed and density above other goals. In order to be cost effective for most applications, a general purpose programmable logic architecture attempts to provide routing resources sufficient to give a good chance of fitting a design, and allowing the utilization of most of the available logic gates in the integrated circuit. However, with a general purpose programmable logic architecture, there is always a possibility that a given design or partition may not be implementable even through the gate count is within the rated capacity of the chip.

General purpose programmable logic devices have also typically not supported easy user-probing of internal state information inside the integrated circuit. In a general purpose PLD, any net which is of interest must be brought out to a pin explicitly in the design netlist. This augmentation of the netlist to provide for state observability and controllability often forces a significantly different set of placement decisions on the fitting and routing software. In these cases, the act of setting up to observe a signal may significantly alter the detailed timing of that or other signals. In short, an attempt to observe the event alters the event.

In an application such as an emulation system, there may be very many (e.g., possibly tens of thousands) programmable logic chips. A large design netlist will be partitioned over the collection of chips. If any (one or more) particular design partition does not fit into the assigned programmable logic chip, then the whole system will not be properly implemented. Consequently, it is vital that each and every partition fit and route individually. It is also important that incremental changes to the netlist should result in proportional impacts on the partitioning, fitting and routing. Furthermore, when used for emulation, the programmable logic device should have highly predictable routability, capacity, and timing characteristics.

Furthermore, when partitioning large designs into a number of programmable logic chips, it is desirable that the timing of the original netlist be preserved, which may not be the case if the programmable logic architecture does not provide features to allow this. When partitioning designs into a number of chips, signal path delays may be expanded, but not necessarily uniformly. These differences in signal path delays may introduce timing problems including skews, setup, and hold time violations which are not inherent in the design netlist. Furthermore, timing problems which are present in the design netlist will be hidden by the mapping into multiple programmable logic devices. Existing programmable logic architectures generally do not include adequate means for detecting these types of introduced timing problems and effective means for removing these problems.

As can be seen, an improved programmable logic device architecture is needed, especially programmable logic elements and interconnect networks which improve the organization of logic modules for particular applications including emulation and prototyping.

BRIEF SUMMARY OF THE INVENTION

The present invention is a programmable logic device architecture. The architecture provides flexibility and a great deal of design routability. Many features of the architecture of the present invention are especially well-suited for use in emulation and rapid prototyping applications.

This programmable logic architecture includes a logic block L2and a diagnostic block interface. Logic block L2includes a plurality of logic blocks L1and an X2 programmable interconnect network. The X2 programmable interconnect network programmably couples signals between the plurality of logic blocks L1. Also, the X2 programmable interconnect network programmably couples signals between the logic block L2and the diagnostic block interface and a plurality of programmable I/O pins of the integrated circuit. Each of the plurality of logic blocks L1includes a plurality of logic blocks L0and an X1 programmable interconnect. The X1 programmable interconnect network is used to programmably couple the logic blocks L0, and to programmably couple logic blocks L0to the X2 programmable interconnect block. Each of the logic blocks L0includes a plurality of LE logic elements and an X0 programmable interconnect network. In some embodiments of the present invention, logic blocks L0may further include a secondary or auxiliary logic block. The X0 programmable interconnect network programmably couples signals between LEs, and the X1 interconnect network.

Using the architecture of the present invention, signals from the various logic blocks may be programmably coupled to other logic blocks, and to logic blocks at different levels. The architecture may also include a diagnostic block interface, which interfaces with logic block L2, for performing functions such as JTAG functions, configuring logic block L2, initializing logic block L2, interfacing with off-chip diagnostic and test devices and equipment, and other similar functions. Logic block L2interfaces with the other components of the integrated circuit such as the diagnostic block interface using the X2 programmable interconnect network.

In the present invention, the internal circuitry of the various logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications. For example, the present architecture provides, among other features: predictable logic, routing, and pin-out capacity; predictable and easily modified timing characteristics; and user-available diagnostic capabilities, including state observability. The present architecture may be used for debugging intensive applications where the probability of placement and routing success per chip is more of a concern than the operating speed path of the completed system.

In an embodiment, the invention is an integrated circuit including a number of first programmable interconnect blocks. The integrated circuit also has a number of blocks, each including a number of second programmable interconnect blocks, where every pair of the second programmable interconnect blocks is programmably connected to two or fewer of the first programmably interconnect blocks in common.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows a block diagram of a digital system within which the present invention may be embodied. The system may be provided on a single board, on multiple boards, or even within multiple enclosures.FIG. 1illustrates a system101in which a programmable logic device121may be utilized. Programmable logic devices (sometimes referred to as a PALS, PLAs, FPLAs, PLDs, EPLDs, EEPLDs, LCAs, or FPGAs), are well known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices allow a user to electrically program standard, off the shelf logic elements to meet a user's specific needs. See, for example, U.S. Pat. No. 4,617,479, incorporated herein by reference for all purposes. Such devices are currently represented by, for example, Altera's MAX® series of PLDs and FLEX® series of PLDs. The former are described in, for example, U.S. Pat. Nos. 5,241,224 and 4,871,930, and the Altera Data Book, March 1995, all incorporated by reference. The latter are described in, for example, U.S. Pat. Nos. 5,258,668, 5,260,610, 5,260,611 and 5,436,575, and the Altera Data Book, March 1995, all incorporated by reference for all purposes. Logic devices and their operation are well known to those of skill in the art.

In the particular embodiment ofFIG. 1, a processing unit101is coupled to a memory105and an I/O111and incorporates a programmable logic device (PLD)121. PLD121may be specially coupled to memory105through connection131and to I/O111through connection135. The system may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems may be designed for a wide variety of applications such as, merely by way of example, telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, and others.

Processing unit101may direct data to an appropriate system component for processing or storage, execute a program stored in memory105or input using I/O111, or other similar function. Processing unit101may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, programmable logic device programmed for use as a controller, or other processing unit. Furthermore, in many embodiments, there is often no need for a CPU. For example, instead of a CPU, one or more PLDs121may control the logical operations of the system. In some embodiments, processing unit101may even be a computer system. Memory105may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage retrieval means, or any combination of these storage retrieval means. PLD121may serve many different purposes within the system in FIG.1. PLD121may be a logical building block of processing unit101, supporting its internal and external operations. PLD121is programmed to implement the logical functions necessary to carry on its particular role in system operation.

FIG. 2is a simplified block diagram of the overall internal architecture and organization of a programmable logic device. Many details of PLD architecture, organization, and circuit design are not necessary for an understanding of the present invention and such details are not shown in FIG.2. FIG.2and the following description are representative of a programmable logic device architecture pioneered by Altera Corporation. An understanding of this programmable logic architecture may be useful for a better understanding and appreciation of the present invention.

FIG. 2shows a six-by-six two-dimensional array of thirty-six logic array blocks (LABs)200. LAB200is a physically grouped set of logical resources that is configured or programmed to perform logical functions. The internal architecture of a LAB will be described in more detail below in connection with FIG.3. PLDs may contain any arbitrary number of LABs, more or less than the PLD121shown in FIG.2. Some PLDs may even contain a single LAB. However, generally in the future, as technology advances and improves, programmable logic devices with even greater numbers of logic array blocks will undoubtedly be created.

Furthermore, LABs200need not be organized in a square or rectangular matrix. While a rectangular or square array is generally an efficient layout structure, any arrangement of LABs inside the PLD may be conceived. For example, the array may be organized in a five-by-seven or a twenty-by-seventy matrix of LABs. Furthermore, in some circumstances, some number of LABs may be replaced by different programmable structures.

LAB200has inputs and outputs (not shown) which may or may not be programmably connected to a global interconnect structure, comprising an array of global horizontal interconnects (GHs)210and global vertical interconnects (GVs)220. Although shown as single lines inFIG. 2, each GH210and GV220line represents a plurality of signal conductors. The inputs and outputs of LAB200are programmably connectable to an adjacent GH210and an adjacent GV220. Utilizing GH210and GV220interconnects, multiple LABs200may be connected and combined to implement larger, more complex logic functions than can be realized using a single LAB200.

In one embodiment, GH210and GV220conductors may or may not be programmably connectable at intersections225of these conductors. Also, in some embodiments, intersection225may have programmable drivers for selecting the signal from a conductor in one direction and buffer the signal and drive it onto one of the alternate conductors in the same or different direction. Moreover, GH210and GV220conductors may make multiple connections to other GH210and GV220conductors. Various GH210and GV220conductors may be programmably connected together to create a signal path from a LAB200at one location on PLD121to another LAB200at another location on PLD121. Furthermore, an output signal from one LAB200can be directed into the inputs of one or more LABs200. Also, using the global interconnect, signals from a LAB200can be fed back into the same LAB200. In other embodiments or the present invention, only selected GH210conductors are programmably connectable to a selection of GV220conductors. Furthermore, in still further embodiments, GH210and GV220conductors may be specifically used for passing signal in a specific direction, such as input or output, but not both.

The global interconnect may contain long and segmented conductors. Long conductors run the entire length or width of PLD121. In particular, long conductors may programmably couple LABs along a length or width of PLD121. Segmented conductors are for shorter length interconnections. For example, segmented conductors may include double lines for interconnections between two LABs200. Other segmented conductors include, among other, triple lines, quadruple lines, quintuple lines, sextuple lines, and other similar interconnection resources. Furthermore, at intersections225, segmented conductors may be programmably coupled (or programmably uncoupled) to other long or segmented conductors, in the same or different direction. Intersection225may sometimes be referred to as a “switch box.” As an example, a double line may be programmably coupled to other double, long, or segmented lines, in the same or different direction, at intersections225.

The PLD architecture inFIG. 2further shows at the peripheries of the chip, input-output drivers230. Input-output drivers230are for interfacing the PLD to external, off-chip circuitry.FIG. 2shows thirty-two input-output drivers230; however, a PLD may contain any number of input-output drivers, more or less than the number depicted. Each input-output driver230is configurable for use as an input driver, output driver, or bidirectional driver.

Like LABs200, input-output drivers230are programmably connectable to adjacent GH210and GV220conductors. Using GH210and GV220conductors, input-output drivers230are programmably connectable to any LAB200. Input-output drivers230facilitate the transfer of data between LABs200and external, off-chip circuitry. For example, off-chip logic signals from other chips may be coupled through input-output drivers230to drive one or more LABs200. Based on these off-chip inputs and the logical functions programmed into LABs200, LABs200will generate output signals that are coupled through the global interconnect to input-output drivers230for interfacing with off-chip circuitry.

FIG. 3Ashows a simplified block diagram of LAB200of FIG.2. LAB200is comprised of a varying number of logic elements (LEs)300, sometimes referred to as “logic cells,” and a local (or internal) interconnect structure310. LAB200has eight LEs300, but LAB200may have any number of LEs, more or less than eight. In a further embodiment of the present invention, LAB200has two “banks” of eight LEs for a total of sixteen LEs, where each bank has common inputs, but separate outputs and control signals. In a specific embodiment of the present invention, LAB200has thirty-six LEs300. In some embodiments, LAB200includes carry chains.

A general overview of a LAB200is presented here, sufficient to provide a basic understanding of LAB200. LE300is the smallest logical building block of a PLD. Signals external to the LAB, such as from GHs210and GVs220, are programmably connected to LE300through local interconnect structure310, although LE300may be implemented in many architectures other than those shown inFIGS. 1-3. In one embodiment, LE300of the present invention incorporates a function generator that is configurable to provide a logical function of a number of variables, such a four-variable Boolean operation. As well as combinatorial functions, LE300also provides support for sequential and registered functions using, for example, D flip-flops.

In an embodiment, LE300provides combinatorial and registered outputs that are connectable to the GHs210and GVs220, outside LAB200. Furthermore, the outputs from LE300may be internally fed back into local interconnect structure310; through local interconnect structure310, an output from one LE300may be programmably connected to the inputs of other LEs300, without using the global interconnect structure's GHs210and GVs220. Local interconnect structure310allows short-distance interconnection of LEs, without utilizing the limited global resources, GHs210and GVs220. Through local interconnect structure310and local feedback, LEs300are programmably connectable to form larger, more complex logical functions than can be realized using a single LE300. Furthermore, because of its reduced size and shorter length, local interconnect structure310has reduced parasitics compared to the global interconnection structure. Consequently, local interconnect structure310generally allows signals to propagate faster than through the global interconnect structure.

FIG. 3Bshows LAB200and LEs300interfacing with a secondary or auxiliary logic block350. Secondary logic block350provides additional functionality for LAB200and LEs300. Secondary logic block350contains specialized logical functionality such as a memory, an arithmetic accelerator, a wide multiplexer, or a other similar logic components, and combinations of these. Data is passed to and from LEs300of LAB200and secondary logic block350. For example, signals and data may be passed to secondary logic block350, processed by secondary logic block350, and then the results returned to LAB200and LEs300. PLD121may contain multiple secondary logic blocks350, all of which need not provide the same logic function. For example, one secondary logic block350may be an arithmetic accelerator while another is a memory.

As shown in the embodiment ofFIG. 3B, multiple LEs300within LAB200may be programmably coupled to one secondary logic block350. In further embodiments, there many be any number of LEs300or LABs200programmably coupled to secondary logic block350. For example, there may be one secondary logic block350for one LE300or one secondary logic block350shared by a plurality of LABs200. Also, only a portion of the LEs300of LAB200may be programmable coupled to one secondary logic block350, while the others are coupled to another.

FIG. 4shows a block diagram of a programmable logic architecture of the present invention. This programmable logic architecture may be used as a complete PLD integrated circuit or features of this architecture may be incorporated within the PLD architecture shown in FIG.2. Furthermore, this architecture may be embedded or used, within or in conjunction with, other integrated circuits such as memories, ASICs, and computing and information processors. This architecture features flexibility and richness of routing.

The programmable logic device architecture comprises a pad ring405, a diagnostic interface415, and a logic block L2425. Pad ring405includes a number of pad blocks435. Pad blocks435may be similar to input-output drivers230described above. Each pad block435is programmably configurable for use as an input driver, output driver, or bidirectional driver. An input driver buffers a signal received on an external pin and drives this signal onto one of the conductors inside the integrated circuit; then, this signal may be coupled to the desired internal circuits and LABs200. An output driver buffers a signal received on an internal conductor to drive the signal out onto the external pin of the device. This makes the signal available to the “outside world.”

An output driver may have additional characteristics. Among these are “tristate,” “open drain,” and “open source” features. A tristateable output driver may be enabled and disabled by a control signal. When enabled, a tristate output driver drives a data signal onto the external pin with a low impedance. When disabled, this output buffer does not drive the data signal out to the external pin, but the output buffer assumes a high-impedance state. In the high-impedance state, the tristate output driver has no effect on the signal level of the external pin. A tristateable output buffer may be used for a bidirectional input-output bus. An open-drain output driver behaves as follows: When the input data is a logic high, the output buffer assumes a high impedance state. When the input data input is a logic low, the output buffer drives out a logic low at low impedance. An open-source output driver behaves similarly: When the input data is a logic high, the buffer drives the external pin to a logic high at low impedance. When the input data is a logic low, the buffer assumes a high-impedance state.

An external pin may be coupled to both an input buffer and an output buffer. This type of pin is sometimes referred to as an input-output (or I/O) pin. In other embodiments of the present invention, a PLD may have dedicated input drivers and dedicated output driver, as well as special “fast” input drivers and the like. Moreover, pad block435may include a bonding pad, input-output registers, and control and data selectors (or multiplexers). Pad blocks435may be programmably coupled to diagnostic block interface415or logic block L2425, or both. Pad ring405may also contain pad blocks445specifically associated with and coupled to diagnostic interface block415. For example, diagnostic interface block415may be directly coupled (via line450) to pad blocks445. This may similarly be the case for the pad ring and logic block L2425.

In a specific embodiment of pad ring405, there are approximately 512 pad blocks435. Pad blocks435may be bidirectional-type circuits, as discussed earlier. Moreover, pad blocks435may interface via a bonding pad, a wire, and a lead frame to an external pin of an integrated circuit package.

Diagnostic interface block415may perform JTAG functions, configure the programmable elements in the device, handle logic state initialization and read back, reports error conditions, and provide special functions for manufacturing test enhancement, as well as other types of functions. JTAG functions include those specified in IEEE Standard 1149.1 (1149.1a), which is described in IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated by reference herein for all purposes.

FIG. 5shows a more detailed block diagram of logic block L2425. Logic block L2425contains programmable logic blocks, elements, and interconnect for performing logical functions. Logic block L2425includes a plurality of logic blocks L1505, an X2 programmable interconnect network510, and interconnect515for programmably coupling X2 programmable interconnect network510to pad ring405and logic blocks L1505. Interconnect515between pad ring405, X2 programmable interconnect network511, and logic blocks L1505consists of conductors with two end pins and may not have fan-in or fan-out. These may be referred to as “two-point wires.” X2 interconnect network511may be formed using programmable interconnect, crossbars, multiplexers, and the like, and combinations of these. In a specific embodiment, X2 interconnect network511is implemented using partial crossbars or crossbars.

FIG. 6shows a block diagram of a typical crossbar circuit605. Typically, a crossbar circuit605is a programmable interconnect resource used to programmably couple signals and programmable elements to other components of the integrated circuit. A more detailed description of a specific embodiment of a crossbar structure is provided below in connection with FIG.10. Generally, crossbar circuit605has a plurality of pins610and pins615. As an example, a typical crossbar circuit may have forty-eight pins (a combination of pins610and pins615). Pins may be apportioned as pins610and pins615in any manner. For example, in a specific embodiment, there may be thirty-two pins610and sixteen pins615.

Each of pins610and615may be configured as an input pin or output pin. For example, a pin610may be programmably configured as an input pin and programmably coupled to one or more pins615, configured as output pins. Moreover, crossbar circuit605may also contain dedicated input pins and dedicated output pins. Crossbar circuit605may also provide buffered configurable directional connections from an input pin to one or more output pins. For example, a signal coupled to an input pin may be buffered to an output pin. Using a buffered path, data may be transferred in an input pin-to-output pin direction, but not necessarily in the reverse direction. Also, buffering allows signals to be driven onto longer conductors and with improved propagation speed. The direction may or may not be dynamically configured based upon the configuration of the pins. Moreover, some pins610and615may be associated with a particular buffer for transferring data in a specific direction.

In one embodiment of the present invention, the partial crossbar interconnect architecture is used. Some specific embodiments of this architecture are described in U.S. Pat. Nos. 5,036,473, 5,448,496, and 5,452,231, all incorporated herein by reference. In a partial crossbar interconnect architecture, the pins of each crossbar are connected to the same subset of pins of every logic block. For example, from a logic block L1, there would be four parallel connections to a particular X2 crossbar510. This would allow four signals from logic block L1to be coupled to that particular X2 crossbar510.

In the particular embodiment of the present invention shown inFIG. 5, there are eight logic blocks L1505and sixty-four X2 crossbars510, although an architecture of the present invention may be designed having various numbers of logic blocks and crossbars. Logic blocks L1505may be programmably coupled together using an X1 programmable interconnect network521. X1 interconnect network521is analogous to, and may be similar to, X2 programmable interconnect network511. In a specific embodiment, X1 interconnect network521may be implemented using partial crossbars or crossbars, and combinations of these, as well as many other interconnect resources. X1 interconnect network521may be used to programmably coupled signals between the logic blocks. For example, signals from one logic block L1505may be programmably coupled to other logic blocks L1505.

Logic blocks L1505are comprised of a plurality of logic blocks L0525. In the embodiment inFIG. 5, there are eight logic blocks L0525in a logic block L1505, although logic L1505may contain any number of logic blocks L0525. Logic blocks L0525may be analogous to LABs200. Logic blocks L0525may contain a plurality of LEs530, which may be programmably coupled using an X0 programmable interconnect network535. X0 programmable interconnect network535may be analogous to X1 programmable interconnect network520and local interconnect structure310. Logic block L0525will be described further below.

FIG. 7shows a more detailed block diagram of X2 interconnect network511and L1logic blocks505. X2 interconnect network511includes a plurality of X2 programmable interconnect blocks510. In a specific embodiment, X2 interconnect network511is a partial crossbar interconnect network. L1logic blocks505may be programmably coupled through the plurality of X2 programmable interconnect blocks510and interconnect515to pad blocks435(or other components of the integrated circuit). For example, the plurality of X2 programmable interconnect blocks510may be configured to programmably couple signals to and from L1logic blocks505to pad blocks435and diagnostic block interface415.

FIG. 7shows a particular embodiment of the present invention. As shown, there are sixty-four X2 programmable interconnect blocks510and eight logic blocks L1505. However, other embodiments of the present invention may include any number of these elements. X2 programmable interconnect block510has sixteen lines or pins515for coupling to pad blocks435and other components of the integrated circuit. Pins515may be referred to an “upper” pins. X2 programmable interconnect block510further comprises thirty-two “lower” pins516for coupling to eight logic blocks L1505. X2 programmable interconnect block510may programmably couple signals between any of the thirty-two “lower” pins516to any of the sixteen “upper” pins515, and vice versa. L1logic block505has 256 signal lines or pins725for input and output. These signal lines725are coupled “four-wires rich” to the X2 programmable interconnect block510. This means, for example, that each logic block L1505may be coupled by four wires to each X2 programmable interconnect block510. Accordingly, when there are sixty-four X2 programmable interconnect blocks510, there would be 256 (i.e., 64*4) signal lines725. A software routing program may specify and programmably configure signal lines725to interconnect L1logic blocks505to the lower pins516of X2 programmable interconnect block510as desired. And, from X2 programmable interconnect block510, the signals may be programmably routed to upper pins515as desired. X2 programmable interconnect block510may be configured to pass data from lower pins516to upper pins515, and vice versa.

An X2 programmable interconnect block510may programmably couple a signal on a lower pin516from a logic block L1505to upper pin515(also known as a “two-point wire”). This signal may also be driven to a plurality of upper pins515. This means that there may be no fan-out restrictions for lower pins516of X2 programmable interconnect block510. Pins516may drive out to many pins515and vice versa. The fan-in of upper pin515of X2 programmable interconnect block510may be one (when no logic is performed). With the architecture and routing structure of the present invention, signals may be programmably routed and coupled to, and between, the many logic blocks and logic elements. A signal from an upper pin515may be programmably coupled and routed through X2 programmable interconnect block510to an X1 programmable interconnect block520, within a logic block L1505. Specifically, pad block435may be programmably coupled through an upper pin515through X2 programmable interconnect block510and a lower pin516through signal lines725to X1 programmable interconnect block520.

FIG. 7shows a particular interconnection pattern between X2 programmable interconnect blocks510and X1 programmable interconnect blocks520of logic blocks L1505. The plurality of lower pins516is coupled in groups of four to each logic block L1505through signal lines725. Moreover, from lines725, signals may be programmably coupled to X1 programmable interconnect blocks520. For example, one X2 block510may be coupled via four lower pins516to each of eight logic blocks L1505. For a logic block L1505, each signal line725from a particular X2 block510may be coupled to a different X1 interconnect block520within the logic block L1505. For example, the four pins516from an X2 block510may be coupled to four different X1 blocks520within the same logic block L1505. Programmable interconnect blocks520may also be coupled to X2 programmable interconnect blocks510using other patterns, where the particular interconnection pattern chosen may provide various advantages. For example, a particular interconnect pattern may be appropriately suited for debugging applications. Other patterns may be more generalized and useful for providing flexible and predictable routability.

Further, the interconnection pattern of the X2 and X1 interconnect networks to the logic blocks and to the pad blocks435impacts the efficiency of the routing of nets and the probability of success when using routing software. An important concept in designing an interconnection pattern is to ensure that the routing is uniform and maximally dispersed. “Maximally dispersed” means that for a given pair of “lower-level” interconnection blocks, they will couple directly to as many “higher-level” interconnection blocks as possible. For example, for a pair of X1 interconnection blocks520in different logic blocks L1505, they should be coupled directly to as many X2 programmable interconnect blocks510as possible. If this is true for every pair of X1 programmable interconnect blocks520in the integrated circuit then the interconnection pattern is maximally dispersed. Other patterns may also be used to improve the routing efficiency of the architecture.

FIG. 8shows a block diagram of the interface between X2 programmable interconnect network510and pad blocks435. A plurality of X2 partial crossbar interconnect network511pins are coupled to pad blocks435of the pad ring405. X2 partial crossbar interconnect network511and pad blocks435are interconnected according to the pattern shown. Please note that some of the interconnections between pad blocks435and X2 network blocks510are not shown in order to simplify the diagram. These interconnections would be similar to those already shown. In the pattern shown, a first data pin810of a pad block435is coupled to a first X2 block510. A second data pin810is coupled to an upper pin515of a second X2 block510, on an opposite side of the plurality of X2 blocks510. This pattern continues symmetrically until all data pins810are connected to a X2 interconnect block510. Other patterns may also be used, where the particular interconnection pattern chosen may provide various advantages as discussed earlier.

In the embodiment shown inFIG. 8, pad blocks435have data pins810for coupling to X2 programmable interconnect network blocks510. InFIG. 8, each pad block435has two data pins810for coupling to X2 programmable interconnect network blocks510. For example, in one embodiment, pad block435has a first data pin810for coupling to an X2 interconnect block510and a second data pin810for coupling to a different X2 interconnect block510. From the X2 network510, pad blocks435may be coupled to, for example, logic block L1505. As discussed earlier, pad block435may be configured as an input or output for driving and receiving signals to and from the logic blocks and logic elements of the integrated circuit. Then, these two lines provide paths for routing.

FIG. 9shows a block diagram of logic block L1505. Logic block L1505includes a plurality of logic blocks L0525and a plurality of X1 programmable interconnect blocks520. Logic blocks L0525may be programmably coupled through X1 programmable interconnect blocks520and lower pins925to X2 partial crossbar interconnect network511. A more detailed description of logic blocks L0525is provided below.

A logic block L1505has a plurality of “upper” lines725(also shown inFIG. 7) which are coupled to X2 interconnect blocks510. In one embodiment, there are four lines725from a logic block505coupled to each of sixty-four X2 programmable interconnect blocks510, for a total of 256 lines725. In the embodiment ofFIG. 9, logic block L1505includes eight logic blocks L0525and sixteen X1 programmable interconnect blocks520. Each logic block L0525is coupled to each X1 programmable interconnect block520using four lines925. This is analogous to the interconnection pattern described above between the X2 interconnect block510and logic blocks L1505in FIG.7.

X1 interconnect block520may be implemented using many different types of interconnect structures, such as programmable multiplexers, programmable AND, programmable NOR, global interconnect, and many others, including those which have been described above. In a preferred embodiment, X1 block520is implemented using a crossbar circuit. Then, for example, each pin may be configured as an input or an output. An input pin of an X1 crossbar520has no fanout restrictions and may drive as many output pins of the X1 crossbar520as desired. The fan-in of an X1 crossbar520output pin may be one in the case when no interconnect logic is performed. From an input pin, signals may be routed within the X2 crossbar520to any of the output pins.

Furthermore, to provide for the efficient routing of nets, the interconnection pattern for logic blocks L0525to X1 programmable interconnect blocks520within a logic block L1505should also be uniform and maximally dispersed, as described earlier.

FIG. 10shows a more detailed diagram of a specific programmable interconnect structure which may be used to implement X1 partial crossbar interconnect network521and X2 partial crossbar interconnect network511. More specifically,FIG. 10shows an embodiment of a crossbar structure for a programmable interconnect network. A plurality of lines1010intersect at programmable intersections (or crosspoints)1030with other lines in the plurality of lines1010. At programmable intersections1030, lines1010may be programmably coupled to another line1010, or other lines1010. Lines1010are coupled to programmable directional buffers1040. For example, signals in a lower portion1050of the programmable interconnect structure may be programmably coupled through programmable intersections1030to lines in an upper portion1060of the structure. Lower portion1050may be analogous to the lower pins of the X2 and X1 interconnect networks; and upper portion1060may be analogous to the upper pins of the X2 and X1 interconnect networks. Signals are input or output through programmable directional buffers1040.

Any connections1050and1060can be routed to any other of these connections at a crossbar, as one skilled in the art will readily perceive. Directional buffers1040have two possible states. If a connection1050or1060is an input to a crosspoint1030, then buffer1040is programmably configured to detect a signal incoming on connection1050or1060. Buffer1040buffers the incoming signal, providing faster, cleaner edges onto a crossbar via a line1010. In the case when connection1050or1060is an output of the crossbar, buffer1040is configured to detect a signal on line1010and to buffer the signal onto line1050or1060, providing faster, cleaner edges. As an example, in a specific embodiment of the present invention, X1 partial crossbar interconnect network521(seeFIG. 9) is implemented using the crossbar structure shown in FIG.10. Specifically, for each X1 interconnect block520in a logic block L1505, thirty-two lower-level connections1050(i.e., analogous to lines925) are coupled four wires rich to eight L0logic blocks. For each X1 interconnect block520in a logic block L1505, there are sixteen upper-level connections1060(i.e., analogous to lines725). Since there are eight X1 interconnect blocks520in a logic block L1505, a logic block L1505has 256 upper-level connections1060for coupling to the X2 interconnect block510(see FIG.7).

Moreover, in a specific embodiment, X2 partial crossbar interconnect network511(seeFIG. 7) is also similarly implemented using a crossbar structure as shown in FIG.10. Specifically, lower-level connections1050(i.e., analogous to lines725) couple to logic blocks L1505and upper-level connections1060(i.e., analogous to lines515) couple to pad blocks435.

FIG. 11shows a block diagram of a logic block L0525. Logic block L0525includes a plurality of LEs530(analogous to LEs300of FIG.3), X0 programmable interconnect network535, and optionally a secondary function block350(not shown). InFIG. 11, logic block L0535has thirty-six LEs530. In other embodiments, logic block L0535may have any number of LEs530. X0 programmable interconnect network535is a programmable interconnect for programmably coupling LEs530within a logic block L0535, somewhat similar to a local interconnect in a LAB. X0 network535may be implemented using many schemes including, among others, programmable AND-OR logic, programmable multiplexers, programmable crossbars, programmable interconnect such a global lines, and many others. X0 programmable interconnect network535is also used to programmably couple LEs530to X1 partial crossbar interconnect network521. Moreover, in an embodiment, logic block L0525has a secondary function block350. X0 programmable network535may be used to programmably couple LEs530to the secondary function block350.

As can be appreciated, the architecture of the present invention provides a great deal of flexibility in the routing and interconnection of the logical components. Within a logic block L0525, LEs350may be interconnected together using X0 interconnect network535. LEs350may be programmably coupled through X0 interconnect network535to X1 interconnect blocks520. From X1 interconnect blocks535, LEs350may be programmably coupled to LEs530in other logic blocks L0525, within the same logic block L1505. Also, from X1 interconnect blocks520, LEs530may also be programmably coupled to X2 interconnect blocks510; then, LEs530may be programmably coupled to LEs530in different logic blocks L1505. The programmable interconnect blocks, X1 and X2, provide richness in routability. In further embodiments of the present invention, additional “levels” of programmable interconnect blocks may be used for interconnecting even larger logic blocks, For example, an additional level of programmable interconnect blocks (similar to X1 and X2 interconnect blocks) may be used for interconnecting a plurality of logic blocks L2425, and a plurality of X2 interconnect blocks510. In a similar manner, the architecture of the present invention may be extended indefinitely.

The richness of routability allows LEs530to be easily interconnected. The many various interconnect paths allows LEs530to be interconnected using one or more paths, especially when the interconnect structure is heavily utilized. For example, the shortest interconnect path between two LEs530may already be used; however, these LEs530may still be interconnected using another path by passing signals through X1 and X2 interconnect blocks as needed. In fact, one such interconnection path may pass through many X1 and X2 interconnect blocks, possibly iterating back and forth many times between the X1 and X2 blocks. The flexibility of the present invention helps to ensure the routability of a logic function, regardless of the complexity. The present invention also has a regular, and uniform interconnect structure. Each of the levels of interconnect is similar to the other levels. For example, the interconnect structure for programmably coupling logic blocks L1505is similar to the structure used for logic blocks L0520. This feature allows more predictable routability of the components, thus enhancing the ease with which functions may be implemented, especially when using automated means (such as by the computer). However, in other embodiments of the present invention, the interconnect structure may be less uniform and regular depending on the application. For example, the present invention may include a plurality of secondary logic blocks350, each of which performs a different specialized function. Furthermore, some logic blocks in a particular logic block level, such as logic block L1505, may be substituted with a programmable logic device architecture as shown in FIG.2. In this fashion, the architecture of the present invention may be used to implement functions programmed into a plurality of programmable logic devices such as shown in FIG.2.

Software to program programmable logic is well known to those skilled in the art and is available in various embodiments from Altera Corporation and others producing FPGAs. The programmable logic architecture of the present invention may also be configured using software running on a programmed digital machine, such as a computer. In particular, to software rout the X1 and X2 programmable interconnect networks, the X1 and X2 programmable networks510may be treated as fully buffered output crossbars. The X1 and X2 programmable interconnect networks may be used for “ping-pong” routing, where a signal may be routed from one interconnect block through a plurality of interconnect blocks to its final destination. Furthermore, in certain cases, so many nets may need to be routed from adjacent pins programmably coupled through an X2 programmable interconnect block510to a logic block L1505that there are not enough pins and direct connections. In this case, in order to make the necessary connections, the router software may route the nets through unused pins of an X1 programmable interconnect block520and feed these back through another X2 programmable interconnect block510which has unused pins.

X1 programmable interconnect block520may be used to route signals between logic blocks L0525to other logic blocks L0525within a logic block L1505. A combination of routing from the X1 network to the X2 network and back to the X1 network may be used to route signals from one logic block L0to another logic block L0, when the logic blocks L0are in different logic blocks L1. X2 programmable interconnect block510may be used to route signals from logic blocks L0525to other logic blocks L0525in different logic blocks L1505.

This description of embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims.