MEMORY SUB-SYSTEM TRANSFER QUEUE RETENTION

A method includes issuing a program command to a logic unit (LUN) of a memory device, writing a plurality of commands to a transfer queue within the memory device, detecting a program failure for the LUN of the memory device, and maintaining a number of the plurality of commands in the transfer queue.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to memory sub-system transfer queue retention.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to memory sub-system transfer queue retention, in particular to memory sub-systems that include a memory sub-system transfer queue retention component. A memory sub-system can be a storage system, storage device, a memory module, or a combination of such. An example of a memory sub-system is a storage system such as a solid-state drive (SSD). Examples of storage devices and memory modules are described below in conjunction withFIG.1, et alibi. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory device can be a non-volatile memory device. One example of non-volatile memory devices is a negative-and (NAND) memory device (also known as flash technology). Other examples of non-volatile memory devices are described below in conjunction withFIG.1. A non-volatile memory device is a package of one or more dice. Each die can consist of one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. For some memory devices, blocks (also hereinafter referred to as “memory blocks”) are the smallest area than can be erased. Pages cannot be erased individually, and only whole blocks can be erased.

Each of the memory devices can include one or more arrays of memory cells. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. There are various types of cells, such as single level cells (SLCs), multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs). For example, a SLC can store one bit of information and has two logic states.

Some NAND memory devices employ a floating-gate architecture in which memory accesses are controlled based on a relative voltage change between the bit line and the word lines. Other examples of NAND memory devices can employ a replacement-gate architecture that can include the use of word line layouts that can allow for charges corresponding to data values to be trapped within memory cells based on properties of the materials used to construct the word lines.

During operation a memory sub-system may experience a program failure (e.g., following the issuance of a program command). Previously, upon such a program failure, all program commands for the failed LUN are flushed from the transfer queue and are rescheduled. All commands are rescheduled, except for program commands and erase commands for the failed block, and sense (e.g., read) commands on failed pages. However, this previous program failure response relies upon extensive data structures and/or firmware (e.g., to reschedule all of the commands for the failed LUN). For instance, in previous approaches, once a program failure was detected, as mentioned, all transfer queue commands are flushed (e.g., to a reissue component, such as a state machine for instance); after flushing all commands from the transfer queue a scheduler is blocked from the program failure block; then the reissue component reissues (e.g., replays) all flushed commands, after which the scheduler is released.

Aspects of the present disclosure address the above and other deficiencies by maintaining (e.g., retaining) a number of commands in a transfer queue subsequently to detecting a program failure for a LUN (e.g., following the issuance of a program command). Maintaining the number of commands in a transfer queue subsequent to detection of the program failure for the LUN can eliminate data structure complexities and/or eliminate previously utilized reissue/replay components previously utilized for a program failure. Because embodiments described herein allow for the number of commands to be maintained in the transfer queue subsequent to detection of the program failure, the maintained commands may be pushed to the LUN, rather than being reissued.

These and other benefits of the embodiments contemplated herein improve the functioning of a computing system (e.g., a memory sub-system and/or computing system) by reducing the additional components mentioned above and/or by reducing a quantity of reissued commands exhibited by current approaches by allowing for a reduction in power consumption of the computing system, reduction of data traffic involving the computing system, and/or reduction of adverse effects (e.g., read disturb, write disturb, write amplification, etc.) that result from memory accesses that involve, in particular, non-volatile memory devices.

The memory devices130,140can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device140) can be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

The memory sub-system110can include a transfer queue retention component113. Although not shown inFIG.1so as to not obfuscate the drawings, the transfer queue retention component113can include various circuitry to facilitate maintaining a number of commands to a transfer queue for a memory sub-system and/or components of the memory sub-system (e.g., subsequently to detecting a program failure for a LUN of the memory device). In some embodiments, the transfer queue retention component113can include special purpose circuitry in the form of an ASIC, FPGA, state machine, and/or other logic circuitry that can allow the transfer queue retention component113to orchestrate and/or perform operations to selectively perform transfer queue retention operations for the memory device130and/or the memory device140based on a precedingly occurring program failure for a LUN. As used herein, a component can be control circuitry (e.g., circuitry to control performance of the operations described in connection with the transfer queue retention component).

In some embodiments, the memory sub-system controller115includes at least a portion of the transfer queue retention component113. For example, the memory sub-system controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, the transfer queue retention component113is part of the host system110, an application, or an operating system.

In a non-limiting example, an apparatus (e.g., the computing system100and/or components thereof, such as the memory sub-system110, etc.) can include a memory sub-system transfer queue retention component113. The memory sub-system transfer queue retention component113can be resident on the memory sub-system110. As used herein, the term “resident on” refers to something that is physically located on a particular component, such as a circuit board, substrate, package, or similar assembly of physically directly coupled (e.g., soldered) hardware components of the apparatuses and/or systems described herein. For example, the memory sub-system transfer queue retention component113being “resident on” the memory sub-system110refers to a condition in which the hardware circuitry that comprises the memory sub-system transfer queue retention component113is physically located on the memory sub-system110. The term “resident on” can be used interchangeably with other terms such as “deployed on” or “located on,” herein.

The memory sub-system transfer queue retention component113can be configured to maintain a number of commands in a transfer queue subsequently to detecting a program failure for a LUN of the memory device. For example, the memory sub-system transfer queue retention component113can store, without overwriting, such commands in a set of physically addressable memory cells that are associated with the transfer queue. As described above, the memory components can be memory dice or memory packages that form at least a portion of the memory device130.

The memory sub-system transfer queue retention component113that can be further configured to recover programmable data from a computer component. The programmable data can correspond to one or more of a number of the plurality of commands maintained in the transfer queue subsequently to detecting a program failure for a LUN of the memory device. As an example, the programmable data can be single level cell (SLC) programmable data and the computer component can be a buffer. As another example, the programmable data can be quad level cell (QLC) programmable data and the computer component can be a cache.

FIG.2is a flow diagram231corresponding to memory sub-system transfer queue retention in accordance with some embodiments of the present disclosure. The flow231can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the flow231is performed by the memory sub-system transfer queue retention component113ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation232, a program command can be issued to a LUN of a memory device. One more embodiments provide that a computing component (e.g., a scheduler) can issue the program command to the LUN of the memory device. One more embodiments provide the computer component (e.g., a scheduler) can issue only one program command per each LUN of the memory device, such that only one program command per each LUN of the memory device is pending (e.g., unexecuted). As an example, as subsequent, single, program command may be issued to LUN of the memory device after completion (e.g., writing to the LUN) of a preceding program command.

At operation233, a plurality of commands (e.g., in association with the program command issued to the LUN of a memory device) can be written to a transfer queue of the memory device. Examples of the plurality of commands include sense (e.g., read) commands and erase commands, for instance. The plurality of commands can be directed to the LUN of the memory device for which the program command was issued.

At operation234, a program failure (e.g., a failure of the issued program command mentioned at operation232) for the LUN of the memory device can be detected. One or more embodiments provide that the program failure involves a number of SLC blocks and/or a number of QLC blocks. One or more embodiments provide that the program failure can be indicated by status indicator, such as a flag or a bit pattern.

At operation236, a number of the plurality of commands in the transfer queue can be maintained (e.g., subsequently to detecting the program failure for the LUN); this is in contrast to previous approaches where each command in a transfer queue is flushed (e.g., removed) from the transfer queue subsequent to a program failure for a LUN. As mentioned, this previous program failure response relies upon extensive data structures and/or firmware (e.g., to reschedule all of the commands for the failed LUN).

One or more embodiments provide that the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure, is based at least in part on a percentage of a total number of commands in the transfer queue. For instance, greater than 5% (e.g., from 10% to 50%), greater than 10% (e.g., from 15% to 65%), or greater than 15% (e.g., from 20% to 75%) of commands can be maintained in the transfer queue subsequent to a program failure, based on a percentage of a total number of commands in the transfer queue. One or more embodiments provide that 100% of commands can be maintained in the transfer queue subsequent to a program failure, based on a percentage of a total number of commands in the transfer queue. One or more embodiments provide that other percentages of commands can be maintained in the transfer queue subsequent to a program failure, based on a percentage of a total number of commands in the transfer queue.

One or more embodiments provide that the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure, is based at least in part on a type of command. For instance, each of the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure can be sense (e.g., read) commands. One or more embodiments provide that the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure can be erase commands. One or more embodiments provide that the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure can be sense commands and erase commands.

One or more embodiments provide that the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure, is based at least in part on a first in first out policy. For instance, each of the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure can be earlier written to the transfer queue, relative to commands that are not maintained in the transfer queue subsequent to the program failure.

One or more embodiments provide that the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure, is based at least in part on a size of data associated with the commands. For instance, each of the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure, can have a relatively smaller associated data size (e.g., data to be read), as compared to each commands that are not maintained in the transfer queue subsequent to the program failure. One or more embodiments provide that each of the number of the plurality of commands, maintained in the transfer queue subsequent to a program failure, can have a relatively larger associated data size (e.g., data to be read), as compared to each commands that are not maintained in the transfer queue subsequent to the program failure.

One or more embodiments provide that the number of the plurality of commands maintained in the transfer queue subsequent to a program failure can be pushed to (e.g., executed) the LUN with the program failure. For instance, a sense operation (e.g., read operation) may be performed (e.g., on a number of memory cells of the failed LUN) subsequently to receiving the indication of a program failure for the LUN.

One or more embodiments provide that data can be recovered a from a computer component (e.g., in association with one or more of the commands that is maintained in the transfer queue subsequent to the program failure). For instance, the data can be single level cell (SLC) data and the computer component can be a buffer. The data can be quad level cell (QLC) data and the computer component can be a cache. One or more embodiments provide that the SLC data can be programmed to the memory device. One or more embodiments provide that the QLC data can be programmed to the memory device.

Pushing the plurality of commands, maintained in the transfer queue subsequent to the program failure, to the LUN with the program failure can eliminate data structure complexities and/or eliminate previously utilized reissue/replay components previously utilized for a program failure. Because the number of commands are maintained in the transfer queue subsequently to detecting the program failure, the maintained commands may be pushed to the LUN, rather than being reissued by a previously utilized computing component.

FIG.3is a block diagram of a portion of a memory sub-system351in accordance with some embodiments of the present disclosure. The memory sub-system351may be utilized for causing performance (e.g., with controller352) of any one or more of the methodologies discussed herein. The memory sub-system351may correspond to the memory sub-system110ofFIG.1, for instance, or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the transfer queue retention component113ofFIG.1).

The memory sub-system351can include a transfer queue354, as shown inFIG.3. One or more embodiments provide that a plurality of commands (e.g., in association with a program command issued to a LUN (e.g., LUN353-1, LUN353-2, LUN353-4, or LUN353-4) can be written to the transfer queue354. Examples of the plurality of commands include sense (e.g., read) commands and erase commands, for instance. WhileFIG.3illustrates four LUNs, embodiments are not so limited. For instance, memory sub-system351may include less than four LUNs or more than four LUNs.

As mentioned, a program failure (e.g., a failure of an issued program command mentioned) for a LUN (e.g., LUN353-1, LUN353-2, LUN353-4, or LUN353-4) can be detected. Embodiments of the present disclosure provide that subsequently to detecting the program failure for the LUN, a number of the plurality of commands in the transfer queue354can be maintained (e.g., in contrast to be flushed (removed) from a transfer queue subsequent to a program failure for a LUN as in previous approaches).

One or more embodiments provide that the number of the plurality of commands maintained in the transfer queue354subsequent to a program failure can be pushed to (e.g., executed) the LUN (e.g., LUN353-1, LUN353-2, LUN353-4, or LUN353-4) with the program failure. For instance, a sense operation (e.g., read operation) may be performed (e.g., on a number of memory cells of the failed LUN) subsequently to receiving the indication of a program failure for the LUN.

FIG.4is a block diagram of a portion of a memory sub-system451in accordance with some embodiments of the present disclosure. The memory sub-system451may be utilized for causing performance (e.g., with a controller) of any one or more of the methodologies discussed herein. The memory sub-system451may correspond to the memory sub-system110ofFIG.1, for instance, or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the transfer queue retention component113ofFIG.1).

As shown inFIG.4, the memory sub-system451can include a number of computer components (e.g., computer component461, computer component462, computer component463). One or more embodiments provide that computer component461may be a scheduler. As mentioned, computer component461may issue commands (e.g., a program command) to a LUN (e.g., LUN353-1, LUN353-2, LUN353-4, or LUN353-4shown inFIG.3).

One or more embodiments provide that computer component462may be a buffer. As mentioned, one or more embodiments provide that data can be recovered a from a computer component (e.g., in association with one or more of the commands that is maintained in the transfer queue subsequent to the program failure). One or more embodiments provide that the data can be single level cell (SLC) data.

One or more embodiments provide that computer component463may be a cache. As mentioned, one or more embodiments provide that data can be recovered a from a computer component (e.g., in association with one or more of the commands that is maintained in the transfer queue subsequent to the program failure). One or more embodiments provide that the data can be quad level cell (QLC).