Semiconductor device

A semiconductor device 1 includes a semiconductor chip 10. Each of the semiconductor chips 10 includes a semiconductor substrate 12, a semiconductor layer 14 and an interconnect layer 16. The semiconductor substrate 12 has a specific resistance ρ1 (first specific resistance). A semiconductor layer 14 is provided on the semiconductor substrate 12. Such semiconductor layer 14 exhibits a specific resistance ρ2 (second specific resistance). The relationship of these specific resistances is: ρ2<ρ1. The interconnect layer 16 is provided on the semiconductor layer 14. An inductor 18 for transmitting and receiving signals with an external element outside the semiconductor chip 10 is provided in the interconnect layer 16.

This application is based on Japanese patent application No. 2006-148,187, the content of which is incorporated hereinto by reference.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

A plurality of semiconductor chip are deposited in a semiconductor device disclosed in Japanese Patent Laid-Open No. 2005-228,981. Each of the semiconductor chips is provided with an inductor for a communication. Each of the inductors are configured of an interconnect in an interconnect layer provided on the semiconductor substrate such as a silicon substrate and the like. The inductors are mutually inductively-coupled, which allows transmitting and receiving a signal between the chips.

The present inventor has recognized as follows. In the above-described semiconductor device, an eddy current is generated in the semiconductor substrate by a magnetic field of the inductors. Then, according to Lenz's law, a new magnetic field, which is oriented to neutralize the above-described magnetic field, is generated due to the eddy current, leading to a reduced strength of the magnetic field. The reduced strength of the magnetic field may cause a reduced available communication distance for transmitting and receiving a signal.

SUMMARY

According to one aspect of the present invention, there is provided a semiconductor device, comprising a semiconductor chip, which has: a semiconductor substrate having a first specific resistance; a semiconductor layer, provided on the semiconductor substrate and having a second specific resistance, which is lower than the first specific resistance; and an interconnect layer provided on the semiconductor layer, wherein an inductor for transmitting or receiving a signal between the semiconductor chip and an external element is provided in the interconnect layer of the semiconductor chip.

In such semiconductor device, a semiconductor substrate having larger specific resistance than the semiconductor layer is employed. This allows reducing an eddy current generated in the semiconductor substrate by a magnetic field of the inductor. Therefore, a magnetic field generated by eddy current and oriented to neutralize the above-described magnetic field is also reduced, thereby inhibiting a decrease in the strength of the magnetic field of the inductor.

According to the present invention, a semiconductor device, which is capable of reducing an eddy current generated in a semiconductor substrate by a magnetic field of an inductor, can be achieved.

DETAILED DESCRIPTION

Exemplary implementations of semiconductor devices according to the present invention will be described in reference to the annexed figures. In all figures, identical numeral is assigned to an element commonly appeared in the description of the present invention in reference to the figures, and the detailed description thereof will not be repeated.

First Embodiment

FIG. 1is a cross-sectional view, showing first embodiment of a semiconductor device according to the present invention. A semiconductor device1includes a semiconductor chip10. In the present embodiment, three semiconductor chips10are stacked. The semiconductor chips10are adhered with adhesive agents92.

Each of the semiconductor chips10includes a semiconductor substrate12, a semiconductor layer14and an interconnect layer16. The semiconductor substrate12is, for example, a silicon substrate. The semiconductor substrate12has a specific resistance ρ1(first specific resistance). A typical value of ρ1is, for example, 1,000 Ωcm. Preferably, the specific resistance may be presented as: ρ1≧200 Ωcm, and more preferably, ρ1≧500 Ωcm.

A semiconductor layer14is provided on the semiconductor substrate12. The semiconductor layer14is, for example, a silicon layer formed by an epitaxial growing process. Such semiconductor layer14exhibits a specific resistance ρ2(second specific resistance). The relationship of these specific resistances is: ρ2<ρ1. A typical value of ρ2is, for example, 10 Ωcm. Preferably, the specific resistance may be presented as: 5 Ωcm≧ρ2≧100 Ωcm.

The interconnect layer16is provided on the semiconductor layer14. An inductor18for transmitting and receiving signals with an external element outside the semiconductor chip10is provided in the interconnect layer16. An interconnect, which is not shown here, is provided in the interconnect layer16. The inductor18is configured of a portion of the interconnect, which is manufactured by forming such portion to a coil-shape. In addition to above, one of, or both of, an inductor for transmission and an inductor for reception may be provided in the interconnect layer16.

In the present embodiment, a plurality of semiconductor chips10are provided as described above. Those inductors18are provided in positions corresponding to the respective semiconductor chips10so as to provide inductive coupling therebetween. Specifically, the inductors18are provided in the positions, which provide overlaps of these inductors in plan view.

A signal processing circuit (not shown) for processing signals transmitted or received by the inductor18is formed in the semiconductor layer14. Further, an integrated circuit including the above-described signal processing circuit is formed in the semiconductor layer14.

Advantageous effects obtainable by employing the configuration of the present embodiment will be described. The semiconductor device1employs the semiconductor substrate12having larger specific resistance than that of the semiconductor layer14. This allows reducing an eddy current generated in the semiconductor substrate12by a magnetic field of the inductor18. Therefore, a magnetic field generated by eddy current and oriented to neutralize the above-described magnetic field is also reduced, thereby inhibiting a decrease in the strength of the magnetic field of the inductor18. Thus, a decrease in the available communication distance for transmitting and receiving a signal can be inhibited. Further, in case of transmitting and receiving signals for the same communication distance, the transmission and the reception can be achieved with lower electric power than the conventional device.

In particular, when the specific resistance is: ρ1≧200 Ωcm, considerable advantageous effect of inhibiting such eddy current can be obtained. Further, when the specific resistance is: ρ1≧500 Ωcm, further considerable level of such advantageous effect can be obtained.

The inductor18is composed of the interconnect in the interconnect layer16formed to be electric coil-shaped. This allows an easy provision of the inductor18in the semiconductor chip10.

The integrated circuit including the signal processing circuit is formed in the semiconductor layer14. Therefore, even if the thickness of the whole substrate (multiple-layered structure composed of the semiconductor substrate12and the semiconductor layer14in this case) is selected to be thicker than that of the semiconductor device disclosed in Japanese Patent Laid-Open No. 2005-228,981, a transmitting and receiving performances, which is equivalent to or better than the semiconductor device of the Japanese Patent Laid-Open No. 2005-228,981 can be obtained. Thus, sufficient mechanical strength of the semiconductor chip10can be ensured. Excessively smaller thickness of the substrate may lead to a bending of the substrate due to an influence of stress, thereby possibly deteriorating the characteristics of the semiconductor device such as transistors and the like.

In particular, when the specific resistance is: 5 Ωcm≦ρ2≦100 Ωcm, a manufacture of the above-described integrated circuit is facilitated. This is because the manufacture can be achieved by employing the existing device processes as they are without any modification.

When the semiconductor layer14is formed by an epitaxial growing process, or in other words, when the semiconductor layer14is an epitaxial layer, the semiconductor layer14having smaller specific resistance than the semiconductor substrate12can be easily formed.

The configuration also includes a plurality of semiconductor chips10provided therein so that the inductors18thereof provide inductive coupling therebetween. This allows a preferable transmission and reception of a signal between the semiconductor chips.

Second Embodiment

FIG. 2is a cross-sectional view, showing second embodiment of a semiconductor device according to the present invention. A semiconductor device2comprises a semiconductor chip10and a printed circuit board20. A configuration of the semiconductor chip10is equivalent to that described in reference toFIG. 1. In the present embodiment, two semiconductor chips10are stacked, and the semiconductor chip10in the bottom layer is attached to the printed circuit board20by a wire bonding. More specifically, the semiconductor chip10of the bottom layer is electrically coupled with the printed circuit board20by a wire94. A coupling between the semiconductor chips10and a coupling of the semiconductor chip10with the printed circuit board20are achieved by the adhesive agent92.

The interconnect22of the printed circuit board20is provided in a region that has no portion overlapping with the inductor18of the semiconductor chip10in plan view. More specifically, the interconnect22is disposed to escape the lower portion of the inductor18.

Such configuration allows preventing a generation of an eddy current in the interconnect22due to the magnetic field of the inductor18. A generation of an eddy current in the interconnect22causes a decrease in the strength of the magnetic field of the inductor, similarly as in the case that the eddy current is generated in the semiconductor substrate12. Other advantageous effects of semiconductor device2are similar to that of the semiconductor device1.

Third Embodiment

FIG. 3is a cross-sectional view, showing third embodiment of a semiconductor device according to the present invention. A semiconductor device3comprises a semiconductor chip10and a printed circuit board20. A configuration of the semiconductor chip10is equivalent to that described in reference toFIG. 1. Further, a configuration of the printed circuit board20is equivalent to that described in reference toFIG. 2. In the present embodiment, two semiconductor chips10are stacked, and the semiconductor chip10in the bottom layer is attached to the printed circuit board20by a flip chip bonding. More specifically, the semiconductor chip10of the bottom layer is coupled to the printed circuit board20by a bump30, in a situation that the interconnect layer16thereof is oriented toward the printed circuit board20. Specifically, an electroconductive pad42(first pad) and an electroconductive pad44(second pad) are formed in each of the semiconductor chip10and the printed circuit board20, and the bump30interposes between both pads42and44. Further, a spacing between the semiconductor chip10and the printed circuit board20is filed with an underfill resin96. A coupling between the semiconductor chips10is achieved by the adhesive agent92.

The bump30is provided in a region that has no portion overlapping with the inductor18in plan view. More specifically, the bump30is disposed to escape the lower portion of the inductor18. The bump30is formed of, for example, solder or gold. Further, the pads42and44are provided in regions that have no portion overlapping with the inductor18in plan view.

Such configuration allows preventing a generation of an eddy current in the bump30and/or the pads42and44due to the magnetic field of the inductor18. A generation of an eddy current in the bump30and/or the pads42and44causes a decrease in the strength of the magnetic field of the inductor, similarly as in the case that the eddy current is generated in the semiconductor substrate12. Other advantageous effects of semiconductor device3are similar to that of the semiconductor device2. Here, the present embodiment represents the exemplary implementation, in which all the interconnect22, the bump30and the pads42and44are disposed to escape the lower portion of the inductor18. Alternatively, only portions of these may be disposed to escape the lower portion of the inductor18.

It is not intended that the semiconductor devices according to the present invention is limited to the configurations illustrated in the above-described embodiments, and various modifications thereof are available. For example, the exemplary implementation employing a plurality of semiconductor chip10provided therein is illustrated in the above-described embodiment. Alternatively, only one semiconductor chip10may be provided. Further, the transmission and the reception of signals by the inductor18may not be limited to the case of the communication between the semiconductor chips10, and may be performed between the semiconductor chip10and other components.