Power semiconductor device

A semiconductor device may include: a semiconductor layer; and a trench gate. The semiconductor layer may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may include: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Japanese Patent Application No. 2018-070960 filed on Apr. 2, 2018, the contents of which are hereby incorporated by reference into the present application.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

DESCRIPTION OF RELATED ART

A semiconductor device is used in a power conversion device such as an inverter, and is used to control power supply to a load such as a motor. As described in International Publication No. WO 2016/067374, the load may be short-circuited due to various reasons. In such cases, the semiconductor device is exposed to stress of high voltage and large current. The stress of high voltage and large current when the load is short-circuited may bring forth a risk of thermal destruction of the semiconductor device.

BRIEF SUMMARY

Thus, a technique that reduces saturated current generated when a short circuit occurs to improve a short circuit tolerance is in demand. For example, the saturated current generated when a short circuit occurs can be reduced by increasing a channel resistance. However, such an increase in the channel resistance increases an on-resistance in a normal operation. As such, it is known that the saturated current generated when a short circuit occurs and the on-resistance in the normal operation are in a tradeoff relationship. A technique that improves such a tradeoff relationship is in demand.

In an embodiment disclosed herein, a semiconductor device may comprise a semiconductor layer; and a trench gate extending from a front surface of the semiconductor layer toward a back surface thereof. The semiconductor layer may comprise a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may comprise: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate. In the semiconductor device with such a configuration, the presence of the upper semiconductor region between the lower semiconductor region and the second semiconductor region enables suppression of an increase in an on-resistance in a normal operation as well as reduction in saturated current generated when a short circuit occurs.

DETAILED DESCRIPTION

FIG. 1shows a cross-sectional view of a primary portion corresponding to a half cell of a semiconductor device1. As shown inFIG. 1, the semiconductor device1is a semiconductor device of a type called n channel-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer10, a drain electrode22covering a back surface of the semiconductor layer10, a source electrode24covering a front surface of the semiconductor layer10, and a trench gate30provided in a front layer portion of the semiconductor layer10. The semiconductor layer10includes an n-type drain region12, an n-type drift region14, a p-type body region16, and an n-type source region18. A material of the semiconductor layer10is not particularly limited, and may be, for example, silicon. Instead of this, the material of the semiconductor layer10may be silicon carbide or a nitride semiconductor. Here, the drift region14is an example of a first semiconductor region disclosed herein, the body region16is an example of a second semiconductor region disclosed herein, and the source region18is an example of a third semiconductor region disclosed herein.

The drain region12is provided in a back layer portion of the semiconductor layer10, and contains n-type impurities at a high concentration. The drain region12is disposed at a position exposed at the back surface of the semiconductor layer10and is in ohmic contact with the drain electrode22.

The drift region14is provided on a front surface of the drain region12, disposed between the drain region12and the body region16, and is in contact with both the drain region12and the body region16. The drift region14includes a lower drift region14aand an upper drift region14b. The lower drift region14ais disposed closer to the drain region12than the upper drift region14b, is disposed between the drain region12and the upper drift region14b, and is in contact with both the drain region12and the upper drift region14b. The upper drift region14bis disposed closer to the body region16than the lower drift region14a, is disposed between the lower drift region14aand the body region16, and is in contact with both the lower drift region14aand the body region16. The upper drift region14bfaces a side surface30S of the trench gate30. More specifically, the upper drift region14bis provided to contact the side surface30S of the trench gate30. An n-type impurity concentration of the upper drift region14bis lower than an n-type impurity concentration of the lower drift region14a. Here, the lower drift region14ais an example of a lower semiconductor region disclosed herein, and the upper drift region14bis an example of an upper semiconductor region disclosed herein.

The body region16is provided on a front surface of the drift region14, is disposed between the drift region14and the source region18, and is in contact with both the drift region14and the source region18. The body region16is provided in the front layer portion of the semiconductor layer10, is disposed at a position exposed at the front surface of the semiconductor layer10, and is in ohmic contact with the source electrode24. The body region16faces the side surface30S of the trench gate30. More specifically, the body region16is provided to contact the side surface30S of the trench gate30.

The source region18is provided at a front surface of the body region16, is provided in the front layer portion of the semiconductor layer10, is separated from the drift region14by the body region16, and faces the side surface30S of the trench gate30. More specifically, the source region18is provided to contact the side surface30S of the trench gate30. The source region18is disposed at a position exposed at the front surface of the semiconductor layer10and is in ohmic contact with the source electrode24.

The trench gate30extends from the front surface of the semiconductor layer10toward the back surface thereof and includes a gate electrode32and a gate insulating film34. The gate electrode32has its side surface and bottom surface covered by the gate insulating film34.

Here, a depth D1of the body region16(a distance from the front surface of the semiconductor layer10to a lower surface of the body region16) is about 1 μm. A protruding depth D2of the trench gate30into the drift region14(a distance from an interface between the drift region14and the body region16to a bottom surface of the trench gate30) is about 0.7 μm. A thickness D3of the upper drift region14b(a distance from the interface between the drift region14and the body region16to a lower surface of the upper drift region14b) is about 0.5 μm. A protruding depth D4of the trench gate30into the lower drift region14a(a distance from an interface between the lower drift region14aand the upper drift region14bto the bottom surface of the trench gate30) is about 0.2 μm. Further, the n-type impurity concentration of the lower drift region14ais about 2×1016cm−3, the n-type impurity concentration of the upper drift region14bis about 1×1015cm−3, and a p-type impurity concentration of the body region16is about 5×1017cm−3. These physical property values are mere examples and may suitably be adjusted.

Next, an operation of the semiconductor device1during a normal operation will be described. When a voltage higher than that of the source electrode24is applied to the drain electrode22and a voltage higher than a threshold voltage is applied to the gate electrode32, the semiconductor device1is turned on. At this occasion, a channel (an inverted layer) is generated in a portion of the body region16adjacent to the side surface30S of the trench gate30, and an accumulation layer is generated in a portion of the upper drift region14badjacent to the side surface30S of the trench gate30. Electrons introduced from the source region18travel to the lower drift region14athrough the channel (the inverted layer) generated in the body region16and the accumulation layer generated in the upper drift region14b, by which the semiconductor device1is turned on. Since the upper drift region14bis disposed at a position facing the side surface30S of the trench gate30(in other words, the upper drift region14bis disposed at a shallower position than the bottom surface of the trench gate30), the accumulation layer is generated in the upper drift region14bwhen the semiconductor device1is turned on. Due to this, in the semiconductor device1, an increase in on-resistance is suppressed despite the presence of the upper drift region14bhaving the low impurity concentration. When the voltage applied to the gate electrode32becomes lower than the threshold voltage, the channel in the body region16vanishes and the semiconductor device1is thereby turned off.

Next, an operation of the semiconductor device1when a short circuit occurs will be described. When a load is short-circuited, a high voltage (such as 100 V) corresponding to a power source voltage is applied between the drain electrode22and the source electrode24. At this occasion, due to the presence of the upper drift region14bhaving the low impurity concentration, a depletion layer spreading from a pn junction between the upper drift region14band the body region16can spread beyond the upper drift region14bto cover the bottom surface of the trench gate30within an extremely short period of time. As above, when the short circuit occurs, a JFET effect is produced by the spread of the depletion layer and a channel resistance of the semiconductor device1thereby increases. Due to this, in the semiconductor device1, saturated current generated when the short circuit occurs is reduced.

As described above, since the upper drift region14bhaving the low impurity concentration is provided shallower than the trench gate30, the increase in the on-resistance is suppressed during the normal operation. Meanwhile, since the upper drift region14bhaving the low impurity concentration is present, the saturated current is reduced by the JFET effect when a short circuit occurs. As above, in the semiconductor device1, due to the upper drift region14bdisposed between the lower drift region14aand the body region16, the increase in the on-resistance can be suppressed in the normal operation and further the saturated current generated when a short circuit occurs can be reduced.

FIG. 2shows results of simulation on a characteristic of the semiconductor device1of the present embodiment and a comparative example in the normal operation. A gate voltage is 20 V. In the comparative example, the upper drift region14bis not provided (a region corresponding to the upper drift region14bof the present embodiment is set to have the same concentration as that of the lower drift region14a). As shown inFIG. 2, it was confirmed that the characteristic of the semiconductor device1in the normal operation was not different from that of the comparative example. That is, it can be understood that the increase in the on-resistance is suppressed even though the upper drift region14bhaving the low impurity concentration is provided.

FIG. 3shows results of simulation on the characteristic of the semiconductor device1of the present embodiment and the comparative example when a short circuit occurs. The gate voltage is 20 V. A configuration of a comparative example is same as that inFIG. 2. As shown inFIG. 3, it was confirmed that short-circuit current in the semiconductor device1was suppressed at 20 kA/cm2, whereas short-circuit current in the comparative example is 80 kA/cm2. As above, it was confirmed that the semiconductor device1can reduce the saturated current generated when a short circuit occurs while suppressing the increase in the on-resistance in the normal operation.

As above, due to the upper drift region14bdisposed between the lower drift region14aand the body region16, the semiconductor device1can reduce the saturated current generated when a short circuit occurs while suppressing the increase in the on-resistance in the normal operation. Further, in the semiconductor device1, a high accuracy is not required for a positional relationship between the trench gate30and the upper drift region14bin a planar direction of the semiconductor layer10. Due to this, the semiconductor device1has a feature that its manufacture is simple.

FIG. 4shows a cross-sectional view of a primary portion corresponding to a half cell of a semiconductor device2of a variant. The semiconductor device2is characteristic in that the drift region14further includes a side surface region14c. The side surface region14cis disposed between the side surface30S of the trench gate30and the upper drift region14b, and is in contact with both the side surface30S of the trench gate30and the upper drift region14b. An n-type impurity concentration of the side surface region14cis higher than the n-type impurity concentration of the upper drift region14b. Moreover, the n-type impurity concentration of the side surface region14cis lower than the n-type impurity concentration of the lower drift region14a. The impurity concentration of the side surface region14cis about 1×1016cm−3. This is merely an example, and the n-type impurity concentration of the side surface region14cmay suitably be adjusted. The side surface region14chas a width which encompasses a range of the accumulation layer generated at the position adjacent to the side surface30S of the trench gate30when the semiconductor device2is turned on. Here, the width of the side surface region14cis a width in a direction perpendicularly intersecting the side surface30S of the trench gate30. The width of the side surface region14cis 50 to 200 nm. This is merely an example, and the width of the side surface region14cmay suitably be adjusted.

In the semiconductor device2, the side surface region14cis provided to contact the side surface30S of the trench gate30. This side surface region14chas the higher n-type impurity concentration than the upper drift region14b. Due to this, an electric resistance in the accumulation layer can be reduced when the semiconductor device2is turned on. In the semiconductor device2, the increase in the on-resistance during the normal operation is further suppressed.

The above embodiment exemplified a MOSFET, however, the art described in the claims may be applied to other types of semiconductor devices provided with a trench gate, such as an IGBT (Insulated Gate Bipolar Transistor).

Specific examples of the present disclosure have been described in detail, however, these are mere exemplary indications and thus do not limit the scope of the claims. The art described in the claims include modifications and variations of the specific examples presented above. Technical features described in the description and the drawings may technically be useful alone or in various combinations, and are not limited to the combinations as originally claimed. Further, the art described in the description and the drawings may concurrently achieve a plurality of aims, and technical significance thereof resides in achieving any one of such aims.

Some of the features characteristic to the above-described embodiment will herein be listed. It should be noted that the respective technical elements are independent of one another, and are useful solely or in combinations. The combinations thereof are not limited to those described in the claims as originally filed.

In an embodiment disclosed herein, a semiconductor device may comprise a semiconductor layer; and a trench gate extending from a front surface of the semiconductor layer toward a back surface thereof. A material of the semiconductor layer is not particularly limited. The semiconductor layer may comprise a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may comprise a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.

In the semiconductor device of the above embodiment, the first semiconductor region may further comprise a side surface region disposed between the side surface of the trench gate and the upper semiconductor region and having a higher impurity concentration than the upper semiconductor region.

In the semiconductor device of the above embodiment, the impurity concentration of the side surface region may be lower than that of the lower semiconductor region.

In the semiconductor device of the above embodiment, a width of the side surface region in a direction perpendicularly intersecting the side surface of the trench gate may be in a range of 50 to 200 nm.