SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps.

TECHNICAL FIELD

The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof.

BACKGROUND

With the development of semiconductor technologies, there are a higher integration level of the semiconductor structure (such as the memory), a smaller spacing between devices in the semiconductor structure and a smaller spacing between adjacent conductive devices (such as bit lines (BLs)) in the semiconductor structure. A parasitic capacitance arising from adjacent conductive devices and the insulating material between the conductive devices is directly proportional to a dielectric constant of the insulating material, while inversely proportional to a spacing between the two conductive devices. While the spacing between the BLs is decreased, an increasingly larger parasitic capacitance is generated to cause a resistor capacitor (RC) delay of the semiconductor structure, to affect working efficiency of the semiconductor structure.

SUMMARY

According to a first aspect, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including:

providing a substrate, a plurality of spaced first trenches being formed in the substrate, and the first trenches extending along a first direction;

forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer;

removing the sacrificial layer with the etching holes to form air gaps; and

carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches, so as to form, in the substrate, BLs extending along the first direction, parts of side surfaces of the BLs being exposed in the air gaps.

According to a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, where a plurality of spaced BLs are formed in the substrate, the BLs extend along a first direction, first trenches are formed between adjacent two of the BLs, the BLs each are provided thereon with at least an active region, the active region includes a source region, a channel region and a drain region that are stacked sequentially, and one of the source region and the drain region is electrically connected to the BL; a protective layer in the first trenches, where air gaps are formed between the protective layer and bottoms of the first trenches, and parts of side surfaces of the BLs are exposed in the air gaps; a plurality of spaced first insulating layers on the protective layer, where the first insulating layers extend along a second direction, and the first insulating layers are located between adjacent two rows of the active regions in the second direction, and spaced apart from the active regions; gate structures between the first insulating layers and the active regions, where the gate structures extend along the second direction and surround the active regions, and the gate structures are opposite to at least parts of the channel regions; and a second insulating layer and a third insulating layer covering the gate structures.

DETAILED DESCRIPTION

An embodiment of the present disclosure provides a manufacturing method of a semiconductor structure. Air gaps are formed between BLs, and parts of side surfaces of the BLs are exposed in the air gaps. As the air has a dielectric constant of about 1, the dielectric constant of the structure between the BLs is reduced, thus reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

In order to make the objectives, features and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure are described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the disclosure without creative efforts shall fall within the protection scope of the present disclosure.

ReferringFIG.1, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps:

Step S101: Provide a substrate, a plurality of spaced first trenches being formed in the substrate, and the first trenches extending along a first direction.

FIG.2is a top view of a semiconductor structure according to an embodiment of the present disclosure. Referring toFIG.2, word lines (WLs)83and BLs52are formed in the semiconductor structure. The BLs52extend along the first direction, while the WLs83extend along the second direction. There is an included angle between the first direction and the second direction. For example, the first direction may be perpendicular to the second direction. Specifically, as shown inFIG.2, the BLs52extend along a vertical direction (Y direction), while the WLs83extend along a horizontal direction (X direction). Gate structures are formed in the WLs83. The WLs83or the BLs52may be straight lines, and may also be fold lines.

FIG.2shows sections at different positions. Specifically, the section A-A is parallel to the extension direction of the BLs52and located on the BLs52, and the section B-B is parallel to the extension direction of the BLs52and located between adjacent BLs52. The section C-C is parallel to the extension direction of the WLs83and located on the WLs83, and the section D-D is parallel to the extension direction of the WLs83and located between adjacent WLs83.

Referring toFIG.3toFIG.6, the substrate10may be a semiconductor substrate. The semiconductor substrate may include a silicon element. For example, the substrate may be a silicon substrate, a silicon-germanium substrate or a silicon on insulator (SOI) substrate. For convenience, detailed descriptions will be made by taking the silicon substrate as the substrate10for example in the embodiment of the present disclosure and the following embodiments.

Referring toFIGS.7-10, a plurality of first trenches11are formed in the substrate10. The first trenches11extend along the first direction and are spaced apart. Exemplarily, the substrate10is etched to form the first trenches11in the substrate10. Specifically, the first trenches11are formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) to increase the density of the first trenches11.

Step S102: Form a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer.

Referring toFIG.7toFIG.14, bottoms of the first trenches11are filled with the sacrificial layer20, and remaining parts of the first trenches11are filled with the first protective layer30. The sacrificial layer20and the first protective layer30are made of different materials. For example, the sacrificial layer20has a larger etch selectivity than the first protective layer30, which makes the first protective layer30less etched in subsequent removal of the sacrificial layer20. Exemplarily, the material of the first protective layer30may be silicon oxide, while the material of the sacrificial layer20may be silicon nitride.

Referring toFIG.15toFIG.19, the first protective layer30spaced by the first trenches11is provided with etching holes31. The etching holes31penetrate through the first protective layer30. The etching holes31expose the sacrificial layer20. Based on a plane parallel to the substrate10, sections of the etching holes31each may be of a circular shape, an elliptical shape, a square shape, a rectangular shape or other polygonal shapes. As shown inFIG.19, parts of walls of the etching holes31may further be sidewalls of the first trenches11. The etching holes31may be formed in edges of the first trenches11and away from regions for forming the WLs83. There may be one or more etching holes31in each first trench11. For example, two ends of the first trench11are respectively provided with one etching hole31.

In order to increase a surface area of the sacrificial layer20exposed in the etching holes31and remove the sacrificial layer subsequently, the etching holes31may extend to the sacrificial layer20, as shown inFIG.16. Exemplarily, bottoms of the etching holes31are located in the sacrificial layer20, or the etching holes31penetrate through the sacrificial layer20.

In a possible example, referring toFIG.7toFIG.18, the step of forming a sacrificial layer20in the first trenches11and a first protective layer30on the sacrificial layer20, the sacrificial layer20and the first protective layer30filling up the first trenches11, and the first protective layer30in the first trenches11being provided with etching holes31penetrating through the first protective layer30may include:

Step S1021: Deposit the sacrificial layer in the first trenches, the sacrificial layer filling the bottoms of the first trenches.

Referring toFIG.7toFIG.14, the sacrificial layer20is formed in the first trenches11by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). The thickness direction of the sacrificial layer20and the depth direction of the first trench11are the same and both are a direction perpendicular to the substrate10(Z direction shown inFIG.12).

Step S1022: Deposit the first protective layer on the sacrificial layer, the first protective layer leveling off the first trenches.

Referring toFIG.11toFIG.14, the first protective layer30is deposited on the sacrificial layer20and the substrate10. The first protective layer30fills the first trenches11and covers a top surface of the substrate10. As shown inFIG.11toFIG.14, the top surface of the substrate10refers to an upper surface of the substrate10. The first protective layer30on the top surface of the substrate10is removed to expose the substrate10. Exemplarily, the first protective layer30on the top surface of the substrate10is removed by chemical mechanical polishing (CMP). After the first protective layer30is removed, the top surface of the substrate10is exposed.

Step S1023: Etch the first protective layer at edges of the first trenches to form the etching holes.

As shown inFIG.15toFIG.18, in some possible examples, a mask plate is deposited on the substrate10and the first protective layer30. With the mask plate as a mask, the first protective layer30is removed by dry etching or wet etching to form the etching holes31shown inFIG.16. The mask plate is then removed.

Step S103: Remove the sacrificial layer with the etching holes to form air gaps.

Referring toFIG.20toFIG.23, the sacrificial layer20is removed with an etching gas or an etching solution in the etching holes31. After the sacrificial layer20in the first trenches is removed, air gaps21are formed in the first trenches. As shown inFIG.21, the air gap21is located under the etching hole31, and communicates with the etching hole31.

Step S104: Carry out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches, thereby forming, in the substrate, BLs extending along the first direction, parts of side surfaces of the BLs being exposed in the air gaps.

Referring toFIG.24toFIG.43, the BLs52are formed in the substrate10. The BLs52extend along the first direction. The BLs52are located between adjacent first trenches, and close to the bottoms of the first trenches. The BLs52are as wide as the substrate10between adjacent first trenches, such that parts of side surfaces of the BLs52are exposed in the air gaps21. As shown inFIG.40toFIG.43, lower parts of the side surfaces of the BLs52are exposed in the air gaps21, while upper parts of the side surfaces of the BLs52contact the first protective layer30.

The BLs52may be formed by the silicification reaction. A material of the BLs52includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide or nickel silicide, to reduce resistances of the BLs52. Exemplarily, as shown inFIG.24toFIG.43, the step of carrying out a silicification reaction on the substrate10between adjacent ones of the first trenches11and close to bottoms of the first trenches11, thereby forming, in the substrate10, BLs52extending along the first direction, parts of side surfaces of the BLs52being exposed in the air gaps21includes:

Step S1041: Etch the substrate and the first protective layer to form a plurality of spaced second trenches, the second trenches extending along a second direction and not communicating with the air gaps.

Referring toFIG.24toFIG.27, the substrate10and the first protective layer30are etched to form a plurality of second trenches12. The second trenches12are spaced apart and extend along the second direction. The second trenches12do not communicate with the air gaps21, namely bottoms of the second trenches12are located in the substrate10and the first protective layer30, without penetrating through the first protective layer30. Therefore, the remaining first protective layer30seals tops of the air gaps21, which prevents other materials from falling into the air gaps21in subsequent manufacture and reduces the parasitic capacitances through the air gaps21.

Step S1042: Form a second protective layer on sidewalls of the second trenches, the second protective layer in the second trenches enclosing third trenches.

Referring toFIG.24toFIG.31, a second protective layer50is formed on sidewalls of the second trenches12. The second protective layer50covers the sidewalls of the second trenches12. The second protective layer50in the second trenches12encloses third trenches51. The third trenches51exposes parts of the bottoms of the second trenches12. The first protective layer30and the second protective layer50may be made of a same material, such that the first protective layer30and the second protective layer50are formed into a whole.

In a possible embodiment, a second initial protective layer is deposited on the sidewalls and bottoms of the second trenches12, the substrate10and the first protective layer30, the second initial protective layer in the second trenches12enclosing the third trenches51. The second initial protective layer is etched along the third trenches51to remove the second initial protective layer on the bottoms of the second trenches12, the remaining second initial protective layer being formed into the second protective layer50.

In another possible embodiment, referring toFIG.32toFIG.35, a third protective layer40is further deposited on the substrate10and the first protective layer30, namely the third protective layer40covers the top surface of the substrate10. The third protective layer40, the second protective layer50and the first protective layer30may be made of a same material to form a whole.

Referring toFIG.32toFIG.39, a second initial protective layer is deposited on the sidewalls and bottoms of the second trenches12and on the third protective layer40. The second initial protective layer on the third protective layer40and the second initial protective layer on the bottoms of the second trenches12are removed to expose the bottoms of the second trenches12, the remaining second initial protective layer forming the second protective layer50.

It is to be understood that when the second initial protective layer is etched along the third trenches51by anisotropic etching to remove the second initial protective layer on the bottoms of the second trenches12, the second initial protective layer on the third protective layer40is etched inevitably. With the third protective layer40, only the substrate10in the second trenches12, rather than the top surface of the substrate10, is exposed to ensure forming positions of the BLs52.

As shown inFIG.36toFIG.37, a plurality of pillars are formed on an upper part of the substrate10. The second protective layer50covers outer peripheral surfaces of the pillars. The third protective layer40covers top surfaces of the pillars. The substrate10on bottoms of the third trenches51is exposed. For convenience, the case where the third protective layer40is formed on the substrate10is used as an example for detailed descriptions in the embodiment of the present disclosure and the following embodiments.

It is to be noted that the step of depositing a third protective layer40on the substrate10and the first protective layer30may be executed before the step of etching the substrate10and the first protective layer30to form a plurality of spaced second trenches12, the second trenches12extending along a second direction and not communicating with the air gaps21(Step S1041), namely the step is executed before Step S104. Specifically, the step may be executed after Step S1022, may also be executed after Step S1023, and may further be executed after Step S103.

Preferably, after the step of depositing the first protective layer30on the sacrificial layer20, the first protective layer30leveling off the first trenches11(Step S1023), the third protective layer40is deposited on the substrate10and the first protective layer30. The above arrangement facilitates the manufacture and reduces the manufacturing difficulty of the third protective layer40, and can further prevent the third protective layer40from falling into the etching holes31or the air gaps21to improve the performance of the semiconductor structure.

Correspondingly, the step of etching the substrate10and the first protective layer30to form a plurality of spaced second trenches12, the second trenches12extending along a second direction and not communicating with the air gaps21(Step S1041) includes: Etch the substrate10, the first protective layer30and the third protective layer40to form the plurality of spaced second trenches12, and remain the third protective layer40between adjacent ones of the second trenches12.

Step S1043: Deposit metal on bottoms of the third trenches, and carry out the silicification reaction by annealing to form the BLs.

Referring toFIG.40toFIG.43, the metal may be one of cobalt, titanium, tantalum, nickel and tungsten, and may also be refractory metal. The metal reacts with the substrate10to form metal silicide, and the substrate10between adjacent first trenches is silicided completely. The metal silicide is connected along the first direction to form the BLs52. Parts of top surfaces of the BLs52are exposed in the third trenches51, and parts of side surfaces of the BLs52are exposed in the air gaps21.

The annealing includes rapid thermal annealing (RTA). The annealing temperature is matched with the material of the metal and the material of the substrate10. For example, when the substrate10is made of silicon and the metal is the cobalt, the annealing temperature may be 400-800° C.

According to the manufacturing method of a semiconductor structure provided by the embodiment of the present disclosure, the sacrificial layer20is removed to form the air gaps21between the BLs52extending along the first direction, and parts of side surfaces of the BLs52are exposed in the air gaps21. As the air has a dielectric constant of about 1, the dielectric constant of the structure between the BLs52is reduced, thus reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

It is to be noted that, before the step of forming a second protective layer50on sidewalls of the second trenches12, the second protective layer50in the second trenches12enclosing third trenches51, the manufacturing method of a semiconductor structure further includes: Form active regions13in the substrate10away from the bottoms of the first trenches11, where the active regions13each include a source region, a drain region and a channel region; and the source region, the channel region and the drain region are arranged sequentially along a direction perpendicular to the bottoms of the first trenches11.

Before the BLs52are formed, a plurality of spaced active regions are formed in the substrate10. The active regions each include a source region, a drain region and a channel region. The channel region is located between the source region and the drain region. In the embodiment of the present disclosure, the source region, the channel region and the drain region are arranged vertically, namely arranged sequentially along the direction perpendicular to the bottoms of the first trenches11to form a vertical transistor. The source regions or the drain regions are close to the bottoms of the first trenches11. The source regions or the drain regions close to the bottoms of the first trenches11are electrically connected to the subsequently formed BLs52, namely the source regions or the drain regions are electrically connected to the BLs52. In this way, under the same area of the substrate10, the channel regions can be effectively lengthened by increasing heights of the active regions, thus reducing or preventing the short channel effect and improving the performance of the semiconductor structure.

In some possible embodiments of the present disclosure, after the step of etching the substrate10and the first protective layer30to form a plurality of spaced second trenches12, the second trenches12extending along a second direction and not communicating with the air gaps21(Step S1041), the first trenches11and the second trenches12isolate the substrate10into a plurality of spaced pillar structures. The pillar structures are doped to form the source regions and the drain regions in the pillar structures. The active regions are formed in the substrate10away from the bottoms of the first trenches11.

In other possible embodiments of the present disclosure, after the step of providing a substrate10, a plurality of spaced first trenches11being formed in the substrate10, and the first trenches11extending along a first direction (Step S101), the substrate10between adjacent first trenches11is doped to form the active regions, namely the active regions are of a strip shape, and extend along the first direction. After the second trenches12are formed, the second trenches12cut off the active regions to form a plurality of spaced pillar active regions.

It is to be noted that, referring toFIG.44toFIG.67, after the step of depositing metal on bottoms of the third trenches51, and carrying out the silicification reaction by annealing to form the BLs52, the manufacturing method of a semiconductor structure further includes:

Step a: Form first insulating layers in the third trenches, the first insulating layers filling the third trenches.

Referring toFIG.40toFIG.47, the first insulating layers61are formed in the third trenches51by deposition. The first insulating layers61extend along the second direction. The first insulating layers61fill up the third trenches51. For example, the first insulating layers61level off the third trenches51. As shown inFIG.40toFIG.47, the third protective layer40on the substrate10is removed to expose the substrate10. Surfaces of the first insulating layers61away from the air gaps21are flush with the substrate10, or top surfaces of the first insulating layers61are flush with the top surface of the substrate10. The first insulating layers61and the substrate10are formed into a regular surface to manufacture other structures conveniently.

The material of the first insulating layers61is different from that of the second protective layer50and that of the first protective layer30, so as to remove the second protective layer50or the first protective layer30individually. Exemplarily, the material of the first insulating layers61may be silicon nitride, and the material of the first protective layer30and/or the second protective layer50may be silicon oxide.

Step b: Remove, along a direction perpendicular to the substrate, the first protective layer and the second protective layer to a preset depth to form filling spaces, the filling spaces exposing side surfaces of the active regions.

Referring toFIG.48toFIG.59, a part of the first protective layer30and a part of the second protective layer50are removed by etching. The part of the first protective layer30and the part of the second protective layer50are removed along the direction perpendicular to the substrate10, to form recesses having a preset depth in the substrate10. The recesses each include a filling space72. The filling spaces72expose the side surfaces of the active regions. Specifically, the filling spaces72expose at least parts of the channel regions.

In some possible embodiments, as shown inFIG.48toFIG.59, the step of removing, along a direction perpendicular to the substrate10, the first protective layer30and the second protective layer50to a preset depth to form filling spaces72, the filling spaces72exposing side surfaces of the active regions13includes:

Etch the second protective layer50and the first protective layer30to an initial depth to form filling channels71. Referring toFIG.48toFIG.51, the first protective layer30and the second protective layer50are etched along the direction perpendicular to the substrate10to form filling channels71having an initial depth. The higher one of the source region and the drain region is opposite to the filling channel71. There are a plurality of filling channels71, the filling channels71are isolated by the first insulating layers61.

After the filling channels71are formed, a second insulating layer62is deposited in the filling channels71. The second insulating layer62fills up the filling channels71between the substrate10and the first insulating layers61. Referring toFIG.52toFIG.55, the second insulating layer62is deposited in the filling channels71, and the second insulating layer62fills up the filling channels71between the substrate10and the first insulating layers61. Specifically, the second insulating layer62is formed on sidewalls of the filling channels71. The second insulating layer62blocks off the filling channels71between the active regions and the first insulating layers61. After the second insulating layer62is formed, the filling channels71are isolated into a plurality of spaced openings.

After depositing the second insulating layer62, the remaining first protective layer30and the remaining second protective layer50are etched to a preset depth to form filling spaces72. Referring toFIG.56toFIG.59, the first protective layer30and the second protective layer50are etched continuously to the preset depth through the remaining filling channels71. A part of the remaining first protective layer30and a part of the remaining second protective layer50are removed to form the filling spaces72. The filling spaces72are located under the filling channels71and communicate with the filling channels71.

Step c: Form gate structures in the filling spaces, the gate structures extending along the second direction and surrounding the active regions.

Exemplarily, referring toFIG.60toFIG.67, the step of forming gate structures80in the filling spaces72, the gate structures80extending along the second direction and surrounding the active regions includes: Form oxide layers81on inner surfaces of the filling spaces72. Referring toFIG.56toFIG.63, the oxide layers81are deposited on the inner surfaces of the filling spaces72. The oxide layers81cover exposed outer peripheral surfaces of the active regions, parts of side surfaces of the first insulating layers61and a bottom surface of the second insulating layer62. The oxide layers81annularly provided on the outer peripheral surfaces of the active regions are formed into gate oxide layers of vertical transistors. The oxide layers81may be silicon oxide layers.

Then, conductive layers82are formed in the filling spaces72after the oxide layers81are formed. The conductive layers82are opposite to at least parts of the channel regions. Referring toFIG.60toFIG.63, the conductive layers82are deposited in the filling spaces72and etched back. The conductive layers82fill at least parts of filling spaces72. The oxide layers81and the conductive layers82are formed into the gate structures80. The gate structures80extend along the second direction and surround the active regions. The gate structures80are formed in the WLs83, namely the gate structures80are constituted as parts of the WLs83.

It is to be noted that, after the step of forming gate structures80in the filling spaces72, the gate structures80extending along the second direction and surrounding the active regions, the manufacturing method of a semiconductor structure further includes: Deposit a third insulating layer63on the gate structures80, the third insulating layer63covering the gate structures80and filling up the remaining filling channels71.

Referring toFIG.64toFIG.67, the third insulating layer63is deposited in the remaining filling channels71. The third insulating layer63fills up the filling channels71. By covering the gate structures80with the third insulating layer63, the gate structures80are insulated. The third insulating layer63, the second insulating layer62and the first insulating layers61may be made of a same material to form into a whole, thus implementing electrical isolation for the gate structures80. Referring toFIG.68andFIG.69, after the third insulating layer63is formed, contact nodes91and capacitors92are formed on the substrate10. The vertical transistors are electrically connected to the capacitors92through the contact nodes91.

Referring toFIG.2, andFIG.64toFIG.67, an embodiment of the present disclosure further provides a semiconductor structure, including a substrate10. The substrate10may be a silicon-containing substrate, such as a silicon substrate, a silicon-germanium substrate or an SOI substrate. A plurality of spaced BLs52are formed in the substrate10. The BLs52extend along a first direction. First trenches are formed between adjacent two of the BLs52, namely the first trenches also extend along the first direction. As shown inFIG.2, the first direction is the Y direction. A material of the BLs52includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide or nickel silicide, to reduce resistances of the BLs52.

The BLs52each are provided thereon with at least an active region13. The active region13includes a source region, a channel region and a drain region that are stacked sequentially, namely the source region, the channel region and the drain region are arranged vertically. One of the source region and the drain region is electrically connected to the BL52. For example, the source region is located on the channel region, the drain region is located under the channel region, and the drain region is electrically connected to the BL52.

A protective layer (including a first protective layer30and a second protective layer50) is provided in the first trenches. Air gaps21are formed between the protective layer and bottoms of the first trenches. Parts of side surfaces of the BLs52are exposed in the air gaps21. As shown inFIG.66, lower parts of the side surfaces of the BLs52are exposed in the air gaps21, while upper parts of the side surfaces of the BLs52contact the protective layer.

The protective layer is further filled between adjacent ones of the active regions. As shown inFIG.66, a top surface of the protective layer is higher than top surfaces of the BLs52. The top surface refers to a surface away from the bottom of the first trench. A plurality of spaced first insulating layers61are arranged on the protective layer. The first insulating layers61extend along a second direction (X direction inFIG.2). The active regions13in the second direction are formed into rows. The first insulating layers61are arranged between adjacent two rows of the active regions13, and spaced apart from the active regions13. The first insulating layers61isolate adjacent two rows of the active regions13, such that one row of the active regions13along the second direction is connected to one of gate structures80.

The gate structures80are provided between the first insulating layers61and the active regions13. The gate structures80extend along the second direction, and surround the active regions13. The gate structures80correspond to at least parts of the channel regions. The gate structures80each include an oxide layer and a conductive layer82. The oxide layer covers an outer surface of the conductive layer82. As shown inFIG.66, the oxide layer81covers a side surface, a bottom surface and a part of a top surface of the conductive layer82.

A second insulating layer62and a third insulating layer63further cover the gate structures80. As shown inFIG.66, the second insulating layer62is opposite to edge regions of the gate structures80, and the third insulating layer63is opposite to middle regions of the gate structures80. The second insulating layer62and the third insulating layer63are formed into a whole layer to cover the gate structures80. The first insulating layers61, the second insulating layer62and the third insulating layer63may be made of a same material such as silicon nitride, such that they are formed into a whole to implement electrical insulation on the gate structures80.

Referring toFIG.68andFIG.69, a contact node91is further provided on each of the active regions13. A capacitor92is provided on the contact node91. The capacitor92is electrically connected to the active region13through the contact node91. One of the source region and the drain region contacts the contact node91, for example, the source region contacts the contact node. The contact node91may be polycrystalline silicon. The capacitor92is configured to store data information.

According to the semiconductor structure provided by the embodiment of the present disclosure, the BLs52extend along the first direction, the first trenches11are formed between adjacent two of the BLs52, the protective layer is provided in the first trenches11, the air gaps21are formed between the protective layer and the bottoms of the first trenches11, and parts of the side surfaces of the BLs52are exposed in the air gaps21. As the air has a dielectric constant of about 1, the dielectric constant of the structure between the BLs52is reduced, thus reducing the parasitic capacitance92of the semiconductor structure and improving the working efficiency of the semiconductor structure.

The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other. In the descriptions of this specification, a description with reference to the term “one implementation”, “some implementations”, “an exemplary implementation”, “an example”, “a specific example”, “some examples”, or the like means that a specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure.

In this specification, the schematic expression of the above terms does not necessarily refer to the same embodiment or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more embodiments or examples. Finally, it should be noted that the foregoing embodiments are used only to explain the technical solutions of the present disclosure, but are not intended to limit the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions on some or all technical features therein. The modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.