Tight pitch vertical transistor EEPROM

A memory device including a first conductivity type vertically orientated semiconductor device in a first region of a substrate and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common floating gate structure in simultaneous electrical communication with a first fin structure of the first conductivity type vertically orientated semiconductor device and a second fin structure of the second conductivity type vertically orientated semiconductor device.

BACKGROUND

Technical Field

The present disclosure relates to vertical transistors and memory devices.

Description of the Related Art

Modern integrated circuits are made up of literally millions of active devices such as transistors and memory devices. The geometry of vertical transistors is attractive due to their potential density with increased scaling requirements. Further vertical transistors can allow for relaxed gate lengths to better control electrostatics. New memory structures are desired to integrate with vertical transistors.

SUMMARY

In one embodiment, the methods and structures that are described herein provide a common floating gate series n-type field effect transistor/p-type field effect transistor electrically erasable programmable read-only memory (EEPROM) that is integrated into a vertical transistor process flow. In one embodiment, a memory device is provided that includes a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. The memory device further includes a common floating gate structure in simultaneous electrical communication with a first fin structure of the first conductivity type vertically orientated semiconductor device and a second fin structure of the second conductivity type vertically orientated semiconductor device.

In another embodiment, the memory device includes a first conductivity type semiconductor device in a first region of a substrate and a second conductivity type semiconductor device in a second region of the substrate. A first source/drain region for each of the first and second conductivity type semiconductor devices is formed atop the substrate. A common floating gate structure is present in simultaneous electrical communication to a first vertically orientated channel region for the first conductivity type semiconductor device, and a second vertically orientated channel region for the second conductivity type semiconductor device. A commonly contacted second source/drain region is present on an end of the first and second vertically orientated channel regions that is opposite the first source/drain region for each of the first and second conductivity type semiconductor devices. A separate contact is in contact with each of the first source/drain regions.

In another aspect, a method is provided herein for forming a common floating gate series n-type field effect transistor/p-type field effect transistor electrically erasable programmable read-only memory (EEPROM) using a vertical transistor process flow. In one embodiment, the method may include forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate; and forming a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common floating gate structure is formed in simultaneous electrical communication with a first fin structure of the first conductivity type vertically orientated semiconductor device and a second fin structure of the second conductivity type vertically orientated semiconductor device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The terms “present on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

With increasing scaling for next generation semiconductor devices, vertical field effect transistors (vFETs) have become increasingly attractive. For example, vertical FET devices are attractive for 5 nm device architecture due to sub-30 nm fin pitch and since they are not constrained by the contact poly pitch (CPP) and gate width scaling. Vertical transistors are attractive candidates for 5 nm node and beyond due to their potential of better density scaling and allowing relaxed gate lengths to better control the electrostatics. Memory, such as electrically erasable programmable read-only memories (EEPROMs) are needed as memory cells for use in combination with vertical transistors simultaneously on the same semiconductor wafer.

The methods and structures described herein provide a common floating gate series n-type field effect transistor/p-type field effect transistor electrically erasable programmable read-only memory (EEPROM) that is integrated into a vertical transistor process flow. EEPROM (also written E2PROM) stands for electrically erasable programmable read-only memory, and is a non-volatile memory used in computers and other electronic devices to store relatively small amounts of data but allowing individual bytes to be erased and reprogrammed. EEPROMs are organized as arrays of floating-gate transistors. EEPROMs can be programmed and erased in-circuit, by applying programming signals. EEPROM typically allows bytes to be read, erased, and re-written individually. As used herein a “field effect transistor” is a transistor in which output current, i.e., source-drain current, is controlled by the voltage applied to the gate. A field effect transistor has three terminals, i.e., gate, source and drain. A “gate structure” means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical fields. As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain. As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel.

The field effect transistors of the present disclosure have a vertically orientated channel region that ca n be present within a fin structure. As used herein, a “fin structure” refers to a semiconductor material, which is employed as the body of a semiconductor device, in which the gate structure is positioned around the fin structure such that charge flows down the channel of the fin structure A finFET is a semiconductor device that positions the channel region of the semiconductor device in a fin structure. As used herein, the term “channel” is the region adjacent to the gate structure and between the source and drain of a semiconductor device that becomes conductive when the semiconductor device is turned on. The source and drain regions of the fin structure are the portions of the fin structure that are on opposing sides of the channel region of the fin structure. A “vertical” finFET semiconductor device has the drain, fin channel, and source device components arranged perpendicular to the plane of the substrate surface, which is referred to as a vertical stack. A vertically stacked finFET can have a longer gate length (i.e., height) and larger dielectric spacer than a horizontal (i.e., having the drain, fin channel, and source device components arranged parallel with the plane of the substrate surface) finFET having comparable contact gate pitch.

In some embodiments, unlike a traditional layout, the vertically orientated NFET and PFET are adjacent to each other, which allows for less complexity in the layout of the wiring for the input, output and power supply lines to the NFET and PFET devices. In some embodiments, because the gate are shared, the devices can be placed at less than the contacted-gate pitch. More specifically, because the gates are shared, the devices can be placed at non-contacted gate pitch.

As noted above, the devices described herein include a common floating gate series n-type field effect transistor/p-type field effect transistor electrically erasable programmable read-only memory (EEPROM). In one embodiment, the structure includes an assembly of a PFET and an NFET in a series connection. A first source/drain node of the PFET and a first source/drain node of the NFET are electrically connected to each other, thereby constituting a common node. A gate electrode of the PFET and a gate electrode of the NFET are electrically connected to each other and electrically floating, thereby constituting a common floating gate. The common floating gate is electrically floating, i.e., is configured to retain electrical charges therein with negligible or non-existent leakage current. Some embodiments of structures disclosed herein, are now described in more detail with reference toFIGS. 1A-1B.

Referring toFIGS. 1A and 1B, in some embodiments, the common floating gate series n-type field effect transistor/p-type field effect transistor electrically erasable programmable read-only memory (EEPROM)100includes a first conductivity type region90and a second conductivity type region95. The term “conductivity type” denotes whether the devices which the region have a p-type conductivity or an n-type conductivity. In some embodiments, the first conductivity type region90includes a vertically orientated fin type field effect transistor (VFET)50athat includes a source region and a drain region that is doped to an n-type conductivity, and is therefore referred to as being an n-type vertically orientated fin type field effect transistor (n-type VFET)50a. In some embodiments, the second conductivity type region95includes a vertically orientated fin type field effect transistor (VFET)50bthat includes a source region and a drain region that is doped to a p-type conductivity, and is therefore referred to as being an p-type vertically orientated fin type field effect transistor (p-type VFET)50b. It is noted the first and second conductivity types may be reversed, i.e., the first conductivity region90may be composed of p-type devices, and the second conductivity region95may be composed of n-type devices. For the purposes of simplicity, the first conductivity type region90is hereafter referred to as an n-type conductivity region90and the second conductivity region95is referred to as a p-type conductivity type region95.

Each of the n-type VFET and the p-type VFET may include a first source/drain region20a,20bthat may be composed of epitaxially formed semiconductor material, which can be present overlying a supporting semiconductor substrate10. In the example, depicted inFIGS. 1A and 1B, the first source/drain region20a,20bis a source region, but depending upon how the devices are configured to be biased, the first source/drain region20a,20bcan equally be a drain region. In some embodiments, the first source/drain region20a,20bis separated from the supporting semiconductor substrate10by a counter doped region15a,15b. The term “counter doped” means that the counter doped region15a,15bhas an opposite conductivity type as the first source/drain region20a,20b. For example, when the first source/drain region20athat is present in the n-type device region90has an n-type conductivity, the counter doped region15athat is present in the n-type device region90has a p-type conductivity; and when the first source/drain region20bthat is present in the p-type device region95has a p-type conductivity, the counter doped region15bmay have an n-type conductivity.

The first source/drain region20a,20b, the counter doped regions15a,15b, and the supporting substrate10may each be composed of a semiconductor material, such as a type IV or type III-V semiconductor. Examples of type IV semiconductors that are suitable for use as the base material for the first source/drain region20a,20b, the counter doped regions15a,15b, and the supporting substrate10may include silicon (Si), crystalline silicon (c-Si), monocrystalline silicon, germanium, silicon germanium (SiGe), silicon doped with carbon (Si:C), silicon germanium doped with carbon (SiGe:C) and a combination thereof, and similar semiconductors, e.g., semiconductor materials including at least one element from Group IVA (i.e., Group 14) of the Periodic Table of Elements. Examples of type III-V materials can include gallium arsenic (GaAs).

Although the supporting substrate10is depicted as a bulk substrate, in other embodiments, the supporting substrate10may be a semiconductor on insulator (SOI) substrate. As will be further described below the first source/drain region20a,20b, and the counter doped regions15a,15bmay be formed by ion implantation into the supporting substrate10or epitaxial growth atop the supporting substrate10.

Referring toFIGS. 1A and 1B, the n-type conductivity region90may be separated from the p-type conductivity region95by an isolation region24, such as a shallow trench isolation (STI) region. The isolation region24may be composed of a dielectric material, such as an oxide, e.g., silicon oxide, or a nitride, e.g., silicon nitride.

Each of the n-type VFET50aand the p-type VFET50bmay include a fin structure25a,25bfor the channel region of the device. Similar to the source/drain region20a,20b, and the counter doped regions15a,15b, each of the fin structures25a,25bmay be composed of a semiconductor material, e.g., a type IV semiconductor material, such as silicon or germanium, or a type III-V semiconductor material, such as gallium arsenic (GaAs). The fin structures25a,25bmay have a height ranging from 10 nm to 200 nm. In another embodiment, each of the fin structures25a,25bhas a first height ranging from 20 nm to 100 nm. In one example, each of the fin structures25a,25bhas a height ranging from 30 nm to 50 nm. Each of fin structures25a,25bmay have a width ranging from 5 nm to 20 nm. In another embodiment, each of the fin structures25a,25bhas a width ranging from 6 nm to 12 nm. In one example, each fin structure25a,25bhas a width that is equal to 8 nm. The pitch separating adjacent fin structures25a,25bmay range from 10 nm to 50 nm. In another embodiment, the pitch separating adjacent fin structures25a,25bmay range from 20 nm to 40 nm. In one example, the pitch is equal to 30 nm. The pitch selected for the adjacent fin structures25a,25bmay be less than the contacted gate pitch, i.e., the pitch may be equal to a minimum non-contacted gate pitch or less.

Referring toFIG. 1A, each of the fin structures25a,25bin the EEPROM device100may be in contact with a common gate structure30. The common gate structure30includes a gate dielectric31and a gate electrode32. The gate electrode32is a single structure of an electrically conductive material that is simultaneously in contact with a portion of the gate dielectric that is present on the fin structures25a,25bfor each of the n-type VFET50aand the p-type VFET50b.

FIGS. 1A and 1Billustrate that there is no direct contact to the common gate structure30. Therefore, the common gate structure30is floating. The gate dielectric31may be composed of any dielectric material, such as an oxide, nitride or oxynitride material. In some embodiments, the gate dielectric31is a high-k dielectric material. As used herein, “high-k” denotes a dielectric material featuring a dielectric constant (k) higher than the dielectric constant of SiO2at room temperature. For example, the gate dielectric layer31may be composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixtures thereof. Other examples of high-k dielectric materials for the gate dielectric22ainclude hafnium silicate, hafnium silicon oxynitride or combinations thereof. In one embodiment, the gate dielectric22ahas a thickness ranging from about 1.0 nm to about 6.0 nm.

The gate electrode32may be composed of a doped semiconductor that is electrically conductive, such as n-type doped polysilicon, or the gate electrode32may be composed of a metal, such as a p-type work function metal layer or an n-type work function metal layer. As used herein, a “p-type work function metal layer” is a metal layer that effectuates a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal layer ranges from 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. The term “p-type threshold voltage shift” as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device. A “valence band” is the highest range of electron energies where electrons are normally present at absolute zero. In one embodiment, the p-type work function metal layer may be composed of titanium and their nitrided/carbide. In one embodiment, the p-type work function metal layer is composed of titanium nitride (TiN). The p-type work function metal layer may also be composed of TiAlN, Ru, Pt, Mo, Co and alloys and combinations thereof. As used herein, an “n-type work function metal layer” is a metal layer that effectuates an n-type threshold voltage shift. “N-type threshold voltage shift” as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device. The “conduction band” is the lowest lying electron energy band of the doped material that is not completely filled with electrons. In one embodiment, the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV. In one embodiment, the n-type work function metal layer is composed of at least one of TiAl, TaN, TiN, HfN, HfSi, or combinations thereof.

Still referring toFIGS. 1A and 1B, the common gate structure30may be separated from the first source/drain region25a,25bby a first dielectric spacer40(which may be referred to as the bottom spacer) and the second source drain/region45a,45b(described below) may be separated from the common gate structure30by a second dielectric spacer51(which may be referred to as the top spacer). Each of the first and second dielectric spacer40,51may be composed of an oxide, such as silicon oxide, nitride, such as silicon nitride or a combination thereof.

The second source/drain region45a,45bis present on the opposite side of the fin structures25a,25bthat provide the channel regions for the n-type VFET50aand the p-type VFET50bthan the first source/drain regions25a,25b. The second source/drain regions45a,45btypically has the same conductivity type as the corresponding first source/drain regions25a,25b. For example, the second source/drain region45athat is present in the n-type region90is typically doped to an n-type conductivity, and the second source/drain region45bthat is present in the p-type region59is doped to a p-type conductivity. Similar to the first source/drain region25a,25b, the second source/drain regions45a,45bmay be composed of a semiconductor material, e.g., a type IV semiconductor materials, such as silicon (Si) or germanium (Ge), or a type III-V semiconductor material, such as gallium arsenide (GaAs). In some embodiments, the second source/drain regions45a,45bare formed using an epitaxial deposition process atop an exposed surface of the fin structures25a,25b. Although, the second source/drain regions45a,45bare depicted as drain regions inFIGS. 1A and 1B, the second source/drain regions45a,45bmay also be source regions depending upon how the device is biased.

Still referring toFIGS. 1A and 1B, the EEPROM100may also include a dielectric layer46encapsulating the device, wherein contacts34a,34b,35to the first source/drain region25a,25b, and the second source/drain regions45a,45bextend through the dielectric layer46. Referring toFIG. 1B, in some embodiments, a common electrical contact35is in direct contact with the second source/drain regions45a,45b. The common electrical contact35is the only contact to each of the second source/drain regions45a,45bof the n-type VFET50aand the p-type VFET50b, in which the common electrical contact35is indirect contact with both of the second source/drain regions45a,45bsimultaneously. In some embodiments, a first contact34ais in direct contact with the first source/drain region25aof the n-type VFET50a, and a second contact34bis in direct contact with the first source/drain region25bof the p-type VFET50b, in which the first and second contact34a,34bare separate from one another. There is not contact directly to the common gate structure30, i.e., the common gate structure30is a floating gate.

The floating gate, i.e., common gate structure30, to the n-type VFET50aand the p-type VFET50bof the EEPROM device100may be programmed by electron injection into the floating gate, i.e., common gate structure30, from the p-type VFET50b. In some embodiments, a negative floating body voltage can turn the p-type VFET50bto an ON mode, as opposed to an OFF mode. In some embodiments, erasure of the EEPROM device100is by hole injection into the floating gate, i.e., common gate structure30, from the n-type VFET50a. This operation is consistent with a floating gate complementary metal oxide (CMOS) device architecture. In some embodiments, to program the EEPROM device100, the voltage applied through the p-type contact34a(also referred to as VH) to the first source/drain region25b(in the embodiment depicted inFIGS. 1A and 1B, a source region) of the p-type VFET50bis equal to about 3 volts; the voltage applied to the n-type contact34b(also referred to as VL) to the first source/drain region25a(in the embodiment depicted inFIGS. 1A and 1B, a source region) of the n-type VFET device50ais equal to about 0 volts; and the common electrical contact35(also referred to as VC) to each of the second source/drain regions45a,45bof the n-type VFET50aand the p-type VFET50bis equal to about 0 volts.

In some embodiments, to program or hold a voltage in a circuit application, in which the common electrical contact35(also referred to as VC) is in direct electric communication with the circuit, a voltage is output between Vdd and ground to connect to a circuit node. Further, there is a voltage divider with the PFET and NFET resistance modules, i.e., modules to the p-type VFET50band the n-type VFET5a, by the charge in the floating gate, i.e., common gate structure30. Some embodiments of methods for forming the structures depicted inFIGS. 1A and 1Bare now described in greater detail with further reference toFIGS. 2-11.

FIG. 2depicts one embodiment of an initial material stack used in forming an EEPROM device100. In some embodiments, the initial material stack includes a supporting substrate10, a counter doped layer15a, and a material layer for provide a first source/drain region20a. The supporting substrate10has been described above with reference toFIGS. 1A and 1B. The counter doped layer15amay be formed on the upper surface of the supporting substrate10by ion implantation into the upper surface of the supporting substrate10or by epitaxial growth in combination with in situ doping or ion implantation. The counter doped layer15adepicted inFIG. 2is processed to provide the counter doped layer15awithin the n-type region90of the structure depicted inFIGS. 1A and 1B. Therefore, in this example, the counter doped layer15ais doped to a p-type conductivity. The counter doped layer15amay have a thickness ranging from 5 nm to 50 nm. The material layer for providing the first source/drain regions20amay also be formed using ion implantation or epitaxial growth in combination with ion implantation or in situ doping. The material layer for providing the first source/drain region20atypically provides the first source/drain region for the n-type VFET50awithin the n-type region90. Therefore, the first source/drain region20ais typically doped to an n-type conductivity. The thickness for the material layer for providing the first source/drain region20atypically has a thickness ranging from 10 nm to 100 nm.

FIG. 3depicts one embodiment the structure depicted inFIG. 2following processing to provide an n-type region90and a p-type region95. As noted above, the material layer for providing the first source/drain region20atypically provides the first source/drain region for the n-type VFET50awithin the n-type region90, and the counter doped layer15bprovides the counter doped layer for the n-type VFET50ain the n-type region90.

An isolation region24is formed to isolate the n-type region90from the p-type region95. The isolation region24is formed by etching a trench, e.g., by reactive ion etch, through the material layers for the first counter doped layer15a, and the material layer for the first source/drain region20afor the n-type VFET50ainto the supporting substrate10. The trench is then filled with a dielectric material, such as an oxide, e.g., silicon oxide (SiO2), or a nitride, such as silicon nitride. The deposition process may be a chemical vapor deposition process.

Following formation of the isolation region24, the portion of the structure that provides the n-type region90may be protected by forming an etch mask thereon, while the portions of the first counter doped layer15aand the material layer for the first source/drain region20afor the n-type VFET50athat are exposed by the etch mask are removed, e.g., via etch process. The etch mask may be a photoresist mask that is patterned using photolithography. The etch mask may also be provided by a hard mask, e.g., a mask composed of a dielectric material layer, such as silicon nitride. The etch process or removing the exposed portions of the first counter doped layer15a, and the material layer for the first source/drain region20afor the n-type VFET50athat are present in the p-type region95may be removed by an etch process, such as a selective etch process. For example, the etch process for removing the portions of the first counter doped layer15a, and the material layer for the first source/drain region20afor the n-type VFET50athat are present in the p-type region95may include an etch process that is selective to the supporting substrate10. In some embodiments, the etch process may be an anisotropic etch process, such as reactive ion etch.

Still referring toFIG. 2, the second counter doped layer15a, and the material layer for providing the first source/drain region20bof the p-type VFET50bmay be formed on the portion of the supporting substrate10that is present in the p-type region95. In one embodiment, the second counter doped layer15ais formed using epitaxial growth. The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown,” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline over layer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed.

The epitaxially formed second counter doped layer15a, and the material layer for providing the first source/drain region20bof the p-type VFET50bcan be a type IV semiconductor containing material layer. For example, the epitaxially formed in situ doped n-type semiconductor material15may be composed of silicon (Si), germanium (Ge), silicon germanium (SiGe) and other semiconductor materials. The epitaxial deposition process may employ the deposition chamber of a chemical vapor deposition type apparatus, such as a PECVD apparatus. A number of different sources may be used for the epitaxial deposition of the in situ doped n-type semiconductor material15. In some embodiments, the gas source for the deposition of an epitaxially formed in situ doped n-type semiconductor material15may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane and combinations thereof. In other examples, when the in situ doped n-type semiconductor material15includes germanium, a germanium gas source may be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. The temperature for epitaxial silicon germanium deposition typically ranges from 450° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.

The epitaxially formed second counter doped layer15a, and the material layer for providing the first source/drain region20bof the p-type VFET50bcan each be doped using ion implantation or may be doped in situ. By “in-situ” it is meant that the dopant that dictates the conductivity type of the second counter doped layer15a, and the material layer for providing the first source/drain region20bof the p-type VFET50bis introduced during the process step, e.g., epitaxial deposition, that forms the second counter doped layer15a, and the material layer for providing the first source/drain region20bof the p-type VFET50b.

As noted above, the second counter doped layer15ais typically doped to an n-type conductivity. The n-type gas dopant source may include arsine (AsH3), phosphine (PH3). The first source/drain region20bof the p-type VFET50bis typically doped to a p-type conductivity. A p-type dopant, such as borane and diborane gas, may be employed to in situ dope the first source/drain region20bof the p-type VFET50b.

The second counter doped layer15bmay have a thickness ranging from 5 nm to 50 nm. The thickness of the material layer for the first source/drain region20btypically ranges from 10 nm to 100 nm.

FIG. 4depicts one embodiment of forming a material stack for producing a sacrificial gate structure on the structure depicted inFIG. 3. In some embodiments, the material stack may include a first dielectric spacer layer that provides the first spacer40(also referred to as bottom spacer) of the n-type VFET50aandp-type VFET50b, a sacrificial gate structure layer60, a sacrificial spacer layer53and a cap dielectric layer52. Each of the aforementioned layers may be formed atop the structure depicted inFIG. 3using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), room temperature chemical vapor deposition (RTCVD), high density plasma chemical vapor deposition (HDPCVD) and combinations thereof.

The first dielectric spacer layer that provides the first spacer40may be composed of any dielectric material, and in some instances may be composed of silicon oxide or silicon nitride. In some embodiments, the first spacer40can be composed of a low-k material. As used herein, the term “low-k” denotes a dielectric material having a dielectric constant equal to the dielectric constant of silicon oxide (SiO2) or less. Examples of materials suitable for the low-k dielectric material include diamond like carbon (DLC), organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, carbon doped silicon nitride, porous silicon dioxide, porous carbon doped silicon dioxide, boron doped silicon nitride, spin-on organic polymeric dielectrics (e.g., SILK™), spin-on silicone based polymeric dielectric (e.g., hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinations thereof. The thickness of the first dielectric spacer layer may range from 5 nm to 20 nm.

The sacrificial gate structure layer60may be composed of any material that can be removed selectively to the first dielectric spacer layer. In some embodiments, the sacrificial gate structure layer60may be composed of a silicon containing material, such as amorphous silicon (α-Si). The sacrificial spacer layer51is similar to the first dielectric spacer layer. For example, the sacrificial spacer layer51may be composed of silicon oxide or silicon nitride. The cap dielectric layer52in some examples may be composed of an oxide, such as silicon oxide. The selection of the composition of the cap dielectric layer52and the sacrificial spacer layer51can be selected to provide that the cap dielectric layer52can be removed by an etch process that is selective to the sacrificial spacer layer51. The sacrificial spacer layer51protects the sacrificial gate structure layer60from being etched by the process steps that remove the cap dielectric layer53. The thickness of the cap dielectric layer53is selected to provide a portion of the fin structures for forming the upper source/drain region, i.e., second source/drain region45a,45b.

FIG. 5depicts forming fin structures25a,25bwithin the n-type region90and the p-type region95. The fin structures25a,25bprovide the channel regions for the devices in the CMOS arrangement of transistors in the EEPROM device100. In some embodiments, forming the fin structures25a,25bmay begin with forming fin structure openings through the material stack. The fin structure openings are formed using deposition, photolithography and etch processes. First, an etch mask is formed atop the material stack including the sacrificial gate layer60having openings exposing the portions of the material stack, in which the fin structure openings are formed. Specifically, a etch mask can be produced by applying a photoresist to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing conventional resist developer to produce the etch mask. Once the patterning of the photoresist is completed, the sections covered of the material stack covered by the etch mask are protected while the exposed regions are removed using an etching process that removes the unprotected regions. In some embodiments, the etch process may be an anisotropic etch that removes the exposed portions of the dielectric cap layer53, the sacrificial spacer layer52, as well as a portion of the first spacer layer40to expose a surface of the first source/drain region20a,20b. In some embodiments, the etch process for forming the fin structure openings may be selective to the material of the first source/drain region20a,20b. For example, the etch process for forming the fin structure openings can be a reactive ion etch process.

Still referring toFIG. 5, following the formation of the fin structure openings, a thermal oxidation process forms a dielectric surface61of the sidewall surface of the sacrificial gate layer60that are exposed within the fin structure openings. In the embodiments in which the sacrificial gate layer60is composed of a silicon containing material, the dielectric surface61may be composed of an oxide, such as silicon oxide.

In a following process step, the fin structures25a,25bare formed filling the fin structure openings using an epitaxial deposition process that employs the exposed surface of the first source/drain region20a,20bat the base of the fin structure openings as an epitaxial deposition growth surface. The epitaxial semiconductor material that provides the fin structures25a,25bdoes not form on dielectric surfaces, such as the dielectric cap layer53or the dielectric surface61of the sacrificial gate layer60. The epitaxial growth process for forming the fin structures25a,25bis similar to the epitaxial growth process that is described above for forming the first source/rain region20band the second counter doped layer15. Therefore, the above description for epitaxially forming the first source/rain region20band the second counter doped layer15is suitable for describing at least one method of the epitaxial deposition processes used to form the fin structures25a,25b.

The geometry and composition of the fin structures25a,25bthat are formed inFIG. 5have been described in greater detail with reference toFIGS. 1A and 1B. In some embodiments, the fin structure25ato the n-type VFET50athat is present within the n-type region90has the same composition as the p-type VFET50bin the p-type region95. In other embodiments, the fin structure25ato the n-type VFET50athat is present within the n-type region90has a different composition from the p-type VFET50bin the p-type region95. To provide that the fin structures25a,25bhave different epitaxial compositions, block masks may be employed. For example, a first block mask, e.g., photoresist mask, may be formed over the p-type region95protecting the fin structure opening present within that region, while a first epitaxial deposition process forms a fin structure25awithin the n-type region90. Thereafter, the first block mask may be removed, and a second block mask may be formed exposing the fin structure opening in the p-type region95while covering the fin structure25apreviously formed in the n-type region90. In this example, a second epitaxial deposition process may be used to form the fin structure25bin the p-type region95having a different composition than the fin structure25aformed by the first epitaxial deposition process in the n-type region90.

In some embodiments, the pitch P1separating adjacent fin structures25a,25bis selected to provide that the devices are positioned at less than the contacted gate pitch. In some embodiments, this is possible because the gate structure for the n-type VFET50aand the p-type VFET50bis a common structure30that is shared by both the n-type VFET50aand the p-type VFET50b. In some embodiments, the pitch P1separating the adjacent fin structures25a,25bmay range from 10 nm to 60 nm. In yet another embodiment, the pitch P1separating the adjacent fin structures25a,25bmay range from 25 nm to 40 nm.

FIG. 5further depicts recessing the epitaxially formed fin structures25a,25b, and forming a dielectric cap65on the recessed surfaces of the fin structures25a,25b. The fin structures25a,25bmay be recessed using an etch that is selective to the cap dielectric layer53. Etching the epitaxially formed fin structures25a,25bforms a recess in the upper portions of the fin structure openings. The recess is filled with a deposited dielectric material to provide the dielectric cap65. In some embodiments, the dielectric cap65may be composed of a nitride, such as silicon nitride, that is deposited using chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD).

FIG. 6depicts forming fin spacers66on portions of the fin structures25a,25bthat are subsequently processed to include an upper source/drain region, i.e., second source/drain region45a,45b. In some embodiments, forming the fin spacers66may begin with removing the cap dielectric layer52with an etch process, such as an etch process that is selective to the sacrificial spacer layer53. Removing the cap dielectric layer53exposes upper sidewalls of the fin structures25a,25b. The fin spacers66are formed on the exposed upper sidewalls of the fin structures25a,25busing a conformal deposition process, such as plasma enhanced chemical vapor deposition (PECVD), following by an anisotropic etchback process, such as reactive ion etch.

FIG. 7depicts one embodiment of removing a majority of the material stack that includes the sacrificial gate layer60. In some embodiments, an anisotropic etch, such as reactive ion etch (RIE), that is selective to the fin spacers66, the dielectric fin cap65and the first dielectric spacer40removes a majority of the sacrificial spacer layer53, and the sacrificial gate layer60. Due to the anisotropic nature of the etch process, a remaining portion of the sacrificial spacer layer53′ and a remaining portion of the sacrificial gate layer60is present underlying the fin spacers66.

FIG. 8depicts forming a gate dielectric31for a common gate structure30to each of the channel regions25a,25bfor each of the n-type VFET50aand the p-type VFET50b. In some embodiments, prior to forming the gate dielectric31, the remaining portion of the sacrificial spacer layer53′ and the remaining portion of the sacrificial gate layer60that is present underlying the fin spacers66may be removed using an isotropic selective etch, such as a plasma etch, gas etch or wet etch process. The etch process may also remove the dielectric surface61of the sidewall surface of the sacrificial gate layer60. The etch process may be selective to the fin structures25a,25b. Following the isotropic etch, the sidewalls of the fin structures25a,25bthat provide the channel regions of the n-type VFET50aand the p-type VFET50bmay be exposed.

In one embodiment, the gate dielectric31for the EEPROM memory device may have a thickness ranging from 2 nm to 50 nm. In another embodiment, the gate dielectric31for the EEPROM memory device may have a thickness ranging from 5 nm to 20 nm. In the embodiment that is depicted inFIG. 8, the material layer that provides the gate dielectric31is blanket deposited atop the entirety of the structure, and is therefore initially present on the exposed surfaces of the fin structures25a,25b, as well as the upper surfaces of the first dielectric spacer40, the fin spacers66, and the dielectric fin cap65.

In some embodiments the gate dielectric31may be composed of a high-k gate dielectric. As used herein, “high-k” denotes a dielectric material featuring a dielectric constant (k) higher than the dielectric constant of SiO2at room temperature. For example, the gate dielectric layer31may be composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixtures thereof. Other examples of high-k dielectric materials for the gate dielectric31include hafnium silicate, hafnium silicon oxynitride or combinations thereof. The gate dielectric31may be deposited using chemical vapor deposition methods, such as plasma enhanced chemical vapor deposition (PECVD). In other embodiments, the gate dielectric31may be deposited using atomic layer deposition (ALD).

FIG. 9depicts forming a gate conductor32for the common gate structure30on the gate dielectric31depicted inFIG. 8. The gate conductor32may be formed using deposition, patterning and etch processes. The gate conductor32may be formed directly on the gate dielectric31and may be composed of one or more electrically conductive materials, such as metals and electrically conductive semiconductors. For example, the gate conductor32may be composed of a work function metal that can be selected to provide a p-type work function metal layer and an n-type work function metal layer. In one embodiment, a p-type work function metal layer for the gate conductor32may be composed of titanium and their nitrided/carbide. In one embodiment, the p-type work function metal layer is composed of titanium nitride (TiN). The p-type work function metal layer may also be composed of TiAlN, Ru, Pt, Mo, Co and alloys and combinations thereof. In one embodiment, the n-type work function metal layer for the gate conductor31can be composed of at least one of TiAl, TaN, TiN, HfN, HfSi, or combinations thereof. In addition to the above described work function metals, the gate conductor32may be composed of a metal selected from tungsten (W), tungsten nitride (WN) or combinations thereof. In one or more embodiments, the gate conductor32is tungsten (W). In another embodiments, the gate conductor32may be doped semiconductor material, such as n-type doped polysilicon.

The material layer for the gate conductor32may be deposited by CVD, e.g., plasma enhanced chemical vapor deposition (PECVD). In other examples, the material layer for the gate conductor32may be deposited using physical vapor deposition, such as sputtering. In yet further examples, the material layer for the gate conductor32may be deposited using plating, electroplating, electroless deposition, and combinations thereof.

Following deposition of the material layer for the gate conductor32, an etch process, such as reactive ion etch (RIE), may recess the material layer to the appropriate height. The etch process for recessing the material layer for the gate conductor32may be selective to the gate dielectric31. In a following process step, an etch mask may be formed on the recessed material layer for the gate conductor32having a pattern selected to provide the geometry of the gate conductor32. The etch mask may be a photoresist mask. Following formation of the etch mask for defining the geometry of the gate conductor32, the material layer for the gate conductor32may be etched to remove the exposed portions. Following the etch process, the etch mask may be removed to provide the gate conductor32for the common gate structure30that is depicted inFIG. 9. In a following process step, the exposed portions of the gate dielectric31may be removed using an etch that is selective to the gate conductor32, or alternatively by an etch that is selective to the photoresist mask that is used to define the gate conductor32. The term “common” as used to describe the common gate structure30denotes that the common gate structure30is simultaneously in contact with both the fin structures25a,25bof the n-type VFET50aand the p-type VFET50b.

FIG. 10depicts forming an interlevel dielectric layer70on the structure depicted inFIG. 9. Prior to forming the interlevel dielectric layer70, a second dielectric spacer51(which may be referred to as the top spacer) is formed atop the gate conductor32. The second dielectric spacer51is similar to the first dielectric spacer40that is described above. Therefore, the description of the composition for the first dielectric spacer40is suitable for describing at least one embodiment of the composition for the second dielectric spacer51. The second dielectric spacer51may be formed using deposition, photolithography and etching processes, and the process sequence for forming the second dielectric spacer51may be integrated into the process sequence for patterning the gate conductor32of the common gate structure30.

Still referring toFIG. 10, an interlevel dielectric layer70may be formed over the structures in the n-type region90and the p-type region95of the substrate, and may be composed of any dielectric material, such as an oxide, nitride or oyxnitride material. For example, the interlevel dielectric layer70may be composed of any dielectric material used in microelectronic and nanoelectronic structures, which can include SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). The interlevel dielectric layer70may be deposited using chemical vapor deposition, deposition from solution, spin on deposition and combinations thereof. Following deposition, a planarization process may be applied to the upper surface of the interlevel dielectric layer70.

FIG. 11depicts one embodiment of epitaxially forming a second source/drain region45a,45bon the upper surface of the fin structures25a,25b. The second source/drain region45a,45bmay be formed using an epitaxial deposition process. The second source/drain region45athat is present in the n-type FET region90may be doped to an n-type conductivity; and the second source/drain region45bthat is present in the p-type region95may be doped to a p-type conductivity.

The process flow for forming the second source/drain regions45a,45bmay employ block masks to individually process the n-type FET region90and the p-type FET region95. The block masks may be photoresist masks, but in some embodiments, the block masks may be hard masks, e.g., hard masks composed of silicon nitride or silicon oxide. For example, a first block mask may be formed over the n-type FET region, and a selective etch process may be used to remove the dielectric fin cap65and the fin spacers66that are present on the second fin structure25b. The etch process for removing the exposed dielectric fin cap65and the fin spacers66may be a wet or dry etch, e.g., reactive ion etch, that can be selective to the second fin structure25b, as well as the interlevel dielectric layer70. Following removal of the dielectric fin cap65and the fin spacer66in the p-type FET region95, a second source/drain region45bmay be formed on the exposed end of the second fin structure25bin the p-type FET region95. The first block mask may then be removed from the n-type FET region90, and a second block mask may be formed over the p-type FET region95protecting the second source/drain region45bthat is present therein, while leaving the n-type FET region90exposed. A selective etch can then be used to remove the dielectric fin cap65and the fin spacer66from the n-type FET region90, while the p-type FET region95is protected by the second block mask. A second source/drain region45amay then be formed on the exposed fin structure25athat is present in the n-type FET region90. The second source drain region45amay be epitaxially formed on the exposed surface of the fin structure25a, and may be doped to an n-type conductivity. The second block mask may then be removed. It is noted that planarization steps, such as chemical mechanical planarization (CMP) may be applied to the upper surface of each of the second source/drain regions45a,45bafter they are formed.

Each of the second source/drain regions45a,45bmay be formed using a low temperature epitaxial growth processes. In some embodiments, because the gate structure is present, the top epitaxy needs to be done below 550° C. The second source/drain regions45a,45bare similar to the first source/drain regions20a,20bin base composition and dopant conductivity type. Therefore, the above description of the compositions for the first/source drain regions20a,20b, as well as their epitaxial growth process, are suitable for describing at least one embodiment of the composition and dopant type for the second source/drain regions45a,45b. For example, the second source/drain regions45a,45bmay be composed of type IV semiconductor material, such as silicon (Si), or a type III-V semiconductor material, such as gallium arsenide (GaAs). Further, the second source/drain regions45a,45bmay be in-situ doped to provide their conductivity type, doped using ion implantation, or doped using a combination of ion implantation and in situ doping. In the embodiments depicted inFIG. 11, the second source/drain regions45a,45bare drain regions, while the first source/drain regions are source regions, but the positioning of the source and drain regions may be reversed in other embodiments.

Referring toFIGS. 1A and 1B, following formation of the second source/drain regions45a,45b, via contacts34a,34b,35may be formed to each of the first source/drain regions20a,20band to the second source/drain regions45a,45b. There is no direct via contact to the common gate structure30. The common gate structure30is a floating gate. A single via contact35, i.e., a common via contact35, is formed in direct electrical contact to both the second source/drain region45ain the n-type region90and the second source/drain region45bin the p-type region95. The n-type vertically orientated field effect transistor50aand the p-type vertically orientated field effect transistor50bare connected in series. The common via contact35may also be referred to as a “VC” contact. The via contact34ato the first source/drain region20ain the n-type region90is separate from the via contact34bto the first source/drain region20bin the p-type region95. The via contacts34a,34bto the first source/drain regions20a,20bare also separate from the common via contact35to the second source/drain regions45a,45b. The via contact34ato the first source/drain region20aof the n-type vertically orientated field effect transistor50amay also be referred to as “VL”. The via contact34bto the second source/drain region20bof the p-type vertically orientated field effect transistor50bmay also be referred to as “VH”.

The via contacts34a,34b,35may be produce by forming a via opening through the interlevel dielectric layer70; and filling the via opening with an electrically conductive material. The via opening may be formed using photolithography and etch processes. For example, a photoresist mask may be formed exposing the portion of the dielectric material layers in which the via opening is to be formed, wherein following formation of the photoresist mask, the via opening may be etched into the interlevel dielectric using an etch process, such as reactive ion etch. The via opening may be filled with a doped semiconductor material, such as n-type doped polysilicon, or a metal, such as copper, aluminum, titanium, tungsten, platinum or combinations thereof, to form the via contacts34a,34b,35. The electrically conductive material may be deposited into the via opening using physical vapor deposition (PVD). Examples of PVD processes suitable for depositing the metal for the via contacts34a,34b,35include plating, electroplating, electroless plating, sputtering and combinations thereof.

Having described preferred embodiments of a structure and method for forming Tight Pitch Vertical Transistor Eeprom, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.