Accessible chip stack and process of manufacturing thereof

A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, relates to the processing of chips while arranged on a wafer prior to orienting the chips into stacks. Furthermore, the invention also pertains to the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

In essence, the basic concept of forming three-dimensional or stacked integrated circuits is well known in the semiconductor and related technology, in which the use and fabrication of multi-chip stacks are widely employed in enabling multiple and diverse technologies, and materials can be readily combined into a single system in order to provide functions which are incapable of being obtained by means of single technology and material combinations. Moreover, advantageous and versatile combinations of diverse integrated circuit structures or arrays and modules provided on chips which are assembled in multi-chip stacks can be readily obtained with the shortest leads or wires connecting the various chips, thereby resulting in a shortening of the wiring lengths while concurrently reducing the overall package area in forming the multi-chip stack. It is also possible to produce very large sized chips in the assembling of a plurality of smaller sized chips which are combined and bonded with each other, thereby increasing output of the electronic device employing the chip stacks. In some instances, the three-dimensional integrated chip structures, which are obtained through the formation of multi-chip stacks and the bonding of pluralities of smaller chips to each other in a three-dimensional stack-forming arrangement, can combine diverse technologies. This combination of technologies can enable the obtaining of advantages, such as particle-travel mapping or three-dimensional sensor. Consequently, chip stacks are often utilized in the form of so-called cubes, such as those manufactured by Irvine Sensors™ in which leads are extended outwardly from between bonded chips to a stack edge in order to afford accessibility thereto upon mounting of the chips, for example in a vertical chip array, on an underlying substrate. This, typically, requires special single chip processing on cube edges after effectuating cube stacking with fewer contact leads being accessible, and a necessity for implementing unusual packaging.

Smaller chips can be wire-bonded, while in a face-up orientation onto a larger chip. This hybrid combination, in turn, is then wirebonded to an outside carrier or C4 (controlled collapse chip connection) bonded onto special substrates, which are equipped with recesses in order to accept the so-called bump that normally is present in an attachment. Consequently, this basically-evident combination is limited to either one small or to a few very small-sized chips, which is or are bonded to a considerably larger chip, such that a significant proportion or percentage of the base wafer surface area remains available for connections of the latter to the electronic or semiconductor device package. This, in effect, forms a limitation which restricts the relative sizes and quantities of chips being formed or assembled into multi-chip stacks.

2. Discussion of the Prior Art

Although, various three-dimensional chip and wafer systems and assembling processes have been developed in the current-state-of-the-art, pertaining to this technology, these are still subject to various limitations and restrictions in comparison with the broader aspects attained by means of the present invention.

Suga, U.S. Pat. No. 6,465,892 B1 and Suga, U.S. Pat. No. 6,472,293 B2, which is a divisional of U.S. Pat. No. 6,465,892 B1, each relate to interconnect structure for stacked semiconductor devices and disclose a method of manufacture of the interconnect structures, wherein the basic concept in each of the patents resides in efforts of shortening the wiring length by superimposing semiconductor substrates and bonding these together by means of solid state bonding techniques. Although this provides for the stacking of chips, there is no formation of a multi-chip stack in a manufacturing process utilizing a flat wafer structure, whereby prior to forming and bonding the chips into stacks, all of the chips processing is precedingly performed.

Concerning Fung, et al., U.S. Pat. No. 6,355,501 B1, which relates to a three-dimensional chip stacking assembly, and which is commonly assigned to the assignee of the present application, this pertains to the forming of three-dimensional stacked SOI (silicon-on-insulator) structures. However, although this patent is directed to a method of stacking ultra thin chips with interconnections for maximizing the operational speed of an integrated circuit package, there is no disclosure of a process of fabrication and processing of all of the chips while mounted on a standard wafer prior to separation or slicing of the wafer into individual components prior to chip stacking.

SUMMARY OF THE INVENTION

Accordingly, in order to clearly and uniquely improve upon the prior art, as represented by the current technology, the present invention is directed to the provision of a process in which a manufacture is implemented in processing the chips while arrayed on flat planar wafers prior to separating and forming or bonding the chips superimposingly into multi-chip stacks.

In effect, the access to wiring for the integrated circuits or semiconductor devices is provided through upper chips towards chips positioned therebelow, so as to be adhesively bonded together and whereby usual planar wafer design, bonding, dicing and handling can be implemented, and in which the upper chips commence with SOI or the like technologies so as to be readily capable of being thinned, as necessary. This particular thinning process effectively affords that any through-vias in the chip can be of reasonable dimensions and are built or formed while the wafers are still intact and planer in surface configuration. This can facilitate an extremely high chip density being provided on the wafer surface, so as to thereby maximize the yield of processed chips and resultant increase in output upon forming of the multi-chip stacks through the superposition and bonding together of the chips.

Accordingly, it is an object of the present invention to provide a process for the manufacture of multi-chip stacks, which will afford the processing of the chips while arranged on a wafer substrate prior to the chips being aligned into multi-chip stacks.

Another object of the present invention resides in processing pluralities of chips while mounted on a wafer so as to enable access to wiring extending from upper chips to lower chips of a multi-chip stack formed from the chips in order to facilitate the utilization of a planar wafer design, bonding, wafer dicing and handling of the separated chips.

DETAILED DESCRIPTION OF THE INVENTION

Referring in specific detail to the drawings, as shown inFIG. 1, there is provided a first base semiconductor Chip10(identified as A), which is arranged on a substrate, such as a planar wafer12, and is provided with a plurality of metal levels14, of which only two are illustrated in this particular embodiment, although additional levels and layers may be readily provided for multiple-level technologies. Also provided in base semiconductor Chip10are, for example, active devices including Field Effect Transistor (FET) gate electrodes100and active SOI regions102.

This particular chip structure is in a wafer form, and includes interconnecting passages and vias16filled with electrically conductive material18, as may be required by a specific technology. The chip is mounted on a handle20constituting a handling layer below a Buried Oxide (“BOX”) and Shallow Trench Isolation (“STI”) layer22, and will remain permanently thereon. Hereby, the chip can be bulk, Si, SOI, SiGe, GaAs, or any suitable construction, as known in the technology.

As illustrated inFIG. 2of the drawings, there is provided a second Chip26, (identified as B), which may be constituted of an SOI, or any suitable material of that type from which a handle wafer28can be readily removed. At the opposite side from the handle wafer or layer28, the second Chip26is provided with a capping layer (or layers)30.

As in the preceding Chip A ofFIG. 1, any number of metal levels32may be utilized in Chip B, depending upon the types of technologies and connections required from the integrated circuit, although in this instance, only two metal levels32are illustrated by way of example. Also, as in the preceding Chip A, provided in base semiconductor Chip26are, for example, active devices including Field Effect Transistor (FET) gate electrodes104and active SOI regions106. The Chip26may be subjected to a near-final test in order to be able to identify a good die and then the wafer capped through capping layers or films30with dielectric, and printed and etched with a through-via34, which penetrates through capping layers or films30, and through Inter-Level Dielectrics (ILDs)19and BOX (buried oxide layers)22, stopping on or in the handle wafer or layer28. These through-vias34are not yet filled, and are subsequently employed in order to contact Chip A.

At possibly frequent times, if necessary, any electrical contact (not shown) to Chip B may be implemented from what inFIG. 2is the bottom thereof. Shapes36comprised of contact features penetrating completely through BOX and STI layers22to handle wafers28are employed, as shown in the drawingFIG. 2, to accomplish this particular manufacturing step. Thereafter, the Chip or Chips B's is or are diced and collected into dies which have been ascertained as being acceptable.

As illustrated in the assembling of chips10and26, i.e., chips A and B as inFIG. 3of the drawings, Chip B is inverted and an adhesive40is applied to the facing surfaces42,44of the wafer or Chip A and/or Chip B. The accepted Chip26(i.e., Chip B) is flipped over and aligned and bonded by means of the adhesive40to the previously tested and accepted wafer or Chip10(i.e., Chip A). The bonding adhesive may, for example, be constituted of a maleic anhydride polymer, which is activated by using a dendritic amine binder, and it is recommended that the bond between the chips formed through the adhesive be maintained as thin as possible so as not to result in any outgassing phenomenon or in any significant change in the volume of the stacked superimposed adhesively bonded chips10,26(i.e., Chips A and B). It is possible to attain a final thickness of 5 to 10 nm if the bonded surfaces are sufficiently flat and clean, thereby reducing the amount of adhesive required to a minimum thickness.

As illustrated inFIG. 4of the drawings, the wafer substrate comprising the handle layer28is removed from Chip26(i.e., Chip B), and in the event that handle layer28is constituted of silicon, it is possible to implement this removal process by means of KOH solution. Similarly, if the shape36contact features in Chip B are also constituted of silicon, then the employment of KOH will etch this material out, but this may not be necessary or essential unless they are to be refilled with the same material used to fill the through-via34. The removal of the handle wafer or layer28exposes the still unfilled through-via34, which has been formed in Chip26. Thereafter, etching may be implemented utilizing the still open through-via34as a mask in order to remove capping layers or films30and adhesive40, which are present below the through-via34and above the appropriate metal pads14; whereby the etching may stop on the metal pads14.

ConcerningFIG. 5of the drawings, the through-via or vias34are then filled, as are any through buried oxide layer (BOX) contacts to Chip26(Shapes36) in the event that they had been opened. Furthermore, it may be possible to implement this process by depositing and deep etching a thick liner material, and then plating thereover. A copper fill may be advantageous to provide for electrical conductivity; however, a copper fill may require the liner to be relatively thick, inasmuch as the copper will be penetrating the BOX layer of Chip26and thus render it susceptible to metal contamination. ALD processes can be employed for the purpose of depositing diverse materials that are utilized as a plug or seed. Any metal is then removed from the upper surfaces or top of the stack (chips10and26as superimposed). CMP may be employed to accomplish a cleanup of this upper surface if the upper surface is sufficiently flat. In order to maintain a general plurality or flatness of the upper surface dummy Chips B may be attached to bad Chip A sites, which have been ascertained. This cleanup step may preferably require the use of a dry etch.

FIG. 5of the drawings illustrates completed bonding of Chip A (Chip10) and Chip B (Chip26), with connections enabled to Chip A by filled through-vias34and to Chip B by filled contact shapes36.

Illustrated inFIG. 6andFIG. 7of the drawings is a design where direct contact from a top Chip C (referred to as Chip50) to base semiconductor Chip A is implemented without necessitating top-side connection of through-vias34to contact shapes36. In this embodiment, as depicted inFIG. 6, through-via34is configured so that it overlaps the wiring shape52of Chip50to which connection is required to base Chip10. Inasmuch as an etching of through-via34is blocked by wiring shape52, the via profile will be wider at its top than at its bottom.

Chip50is then inverted, and bonded to base Chip10, and the handle substrate is removed from Chip50and the bottom of through-via34is etched, as mentioned above. Then through-via34is lined and filled, and metal overburden removed, similarly as is implemented for the structure shown inFIG. 5of the drawings. The result of this process is illustrated inFIG. 7of the drawings. As the wider top portion of through-via34has now been moved to the bottom as a consequence of the inversion of Chip50prior to bonding, conformal filling of through-via34can result in fill void62.

The chip stacking process can be repeated by attaching additional chips to the top of a stack formed by chips10and26(A and B) fromFIG. 5, or a stack formed by chips50and26fromFIG. 7. Through-vias in these additional chips will need to intersect through-vias34or contact shapes36of each previous-level chip.

Bonding to the outside of the stacked chips may be implemented by connecting to the exposed filled vias on the top surface of the top chip of the stack and presently may only comprise small cross-sectional via ends. A further step would then be to plate a pad onto the surface, which would be a suitable material to which C4 or a wirebond could be connected. However, instead of plating or employing photolithography and etching to form a pad, it is possible to build chip containing only larger pads and through vias, and then to attach this pad-only chip to the top surface by using an approach similar to that described for two active-circuit chips.

In optional aspects of the invention, an adhesive to provide bonding of the chips10,26and/or50can be applied before the printing and/or etching of the through-via34on Chip26and then patterned with the through-via mask. This sequence in manufacture will assist in avoiding filling the via with adhesive, but represents a limit as to which resist and/or developers can be employed.

Furthermore, top chips (Chip26as illustrated) can be comprised of passive components, which upon occasion may be required for package compatibility, superconductors, large capacitors and so forth. Moreover, in the event of employing a polysilicon plug in through-BOX contact shapes36to Chip26, the polysilicon fill can be protected from the handle wafer removal etching by depositing a thin oxide film or coating into the as-etched shape36aperture prior to polysilicon deposition. Thereafter, only the thin oxide need be etched off to expose the polysilicon subsequent to removal of the handle layer28.

In order to provide for a satisfactory manufacture, the chips10,26and50(A, B and C) must be of adequately flat construction and the adhesive bonding material sufficiently thick to prevent the formation of any voids in the adhesive during bonding. Chips10and26(and50) alignment can be made very satisfactorily, at less than 25 nm, employing a modified lithographic exposure or setup. The location of Chip10is determined by looking at the front side thereof, and the same or different optics can be utilized to examine or map the front of Chip26. Appropriate precision mechanics, such as are employed for stepper stages, may be utilized to move Chip26into a proper location and then pressed down onto Chip10. (This also pertains to Chip50). Capping film30materials may be selected, for example, from candidate material, such as silicon nitrides, such that etching thereof to clear the bottom of the through-vias34after bonding does not thin the BOX and STI layer22of Chip26. Moreover, unless something else is required for final pads, all photolithographic processes may be implemented while all chips are still in wafer form, not on individual chips or chip stacks, so that very little special processing is required except the alignment of the Chip26to Chip10(or Chip50) and the application of the adhesive bonding material.

Finally, in order to enlarge the upper ends or tops of the through-vias34, it is possible to overplate the via metal in order to create bumps for improved contact to the metal layers without requiring any photolithography on the stack.

From the foregoing, it becomes readily apparent that the invention improves upon the manufacturing process of providing multi-chip stacks or wafers in a highly efficient and unique mode, providing for a simplified manufacturing sequence and allowing for a greater density of chips of diverse technologies to be positioned on a wafer and ready for stacked relationships forming three-dimensional integrated circuit structures.