Method of masking for periphery salicidation of active regions

An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

BACKGROUND AND SUMMARY OF THE INVENTION
 The present application relates to integrated circuit memory chips, and
 particularly to chips which include low-power SRAM cells.
 Sheet Resistance and Clock Speed
 The patterned thin-film layers which are used for conduction in integrated
 circuit devices will typically have a very significant distributed
 resistance and capacitance, which imposed a significant time constant on
 signals routed through such layers.
 The RC time constant of the gate can be reduced by making metal contact to
 the gate in more places. This effectively reduces the "R" term in the time
 constant. However, each such contact consumes some gate area. Moreover, in
 single-level-metal processes, the requirements of making source contacts
 severely constrain the possible geometries for gate contacts.
 Silicides and Conductive Nitrides
 One general technique for improving the conductivity of silicon and
 polysilicon layers is to clad them with a metal silicide and/or a
 conductive nitride (usually TiN). Many different metal silicides have been
 proposed for use; among the most common are titanium, cobalt, tantalum,
 tungsten, nickel, and molybdenum silicide.
 One particularly convenient way to provide suicides is to use a
 self-aligned process, in which a metal is deposited overall and heated to
 react it with exposed silicon. The unreacted metal can then be stripped
 off. Such process are known as "saliciding."
 Salicidation is not without costs and risks. With shallow source/drain
 depths, salicidation may lead to increased leakage. The potential problems
 are reviewed, for example, in S. Wolf, II SILICON PROCESSING FOR THE VLSI
 ERA at 142-152 (1990). Thus silicidation is often avoided in high-density
 low-power memories.
 Innovative Structures and Methods
 The disclosed inventions provide an integrated circuit memory fabrication
 process and structure, in which salicidation is performed on the periphery
 (and optionally on the ground lines) of a memory chip, but not on the
 transistors of the memory cells. This avoids leakage in the array, while
 preserving maximal speed in the peripheral logic.
 This is advantageously, but not necessarily, used in combination with the
 sidewall nitride process disclosed in the parent application, which
 provides a self-aligned zero-offset contact process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 The numerous innovative teachings of the present application will be
 described with particular reference to the presently preferred embodiment
 (by way of example, and not of limitation), in which:
 In the presently preferred embodiment, the claimed silicidation ideas are
 used in combination with the nitride and spacer innovations described in
 the parent application. However, it must be understood that the innovative
 silicidation ideas are not necessarily tied to this context.
 FIG. 1 shows a simple example of an integrated circuit structure. (As will
 be recognized by those skilled in the art, this is a simplified example of
 a device structure, which includes features in common with many
 high-density structures.) In this structure, a number of transistor
 locations 102 (i.e. locations where poly crosses over Active) occur along
 Section line A--A, and a first-poly-contact location 104 where contact is
 made to poly over field oxide occurs along section line B--B. (Note that
 these first-poly-contact locations are NOT related to the "first contacts"
 or direct contacts which were sometimes used, in the 1970s and 1980s, to
 form contacts directly from first poly to active.) These
 first-poly-contact locations are shown as mask outline FPCC in FIG. 7B.
 FIGS. 2A, 3A, 4A, etc. show sequential process steps at transistor gate
 sidewall locations 102 (along section A--A), and corresponding FIGS. 2B,
 3B, 4B, etc., show the same sequence of process steps at
 first-poly-contact location 104 (along section B--B).
 In FIG. 2B, note that an additional mask (the "FPC" mask) is used to remove
 the nitride etch stop in locations where a contact to poly will be
 required.
 After conventional beginnings (preparation of silicon wafer 200, formation
 of N-wells and P-wells, formation of field oxide 202 to e.g. 5000 .ANG.,
 sacrificial oxide grown and stripped, gate oxide 203 grown to e.g. 150
 .ANG., threshold voltage adjustment, etc. etc.), fabrication proceeds as
 follows:
 1. Polysilicon 210 is deposited, e.g. to a thickness of 1500 .ANG., and
 doped.
 2. Tungsten silicide (WSi.sub.x) 212 is deposited by chemical vapor
 deposition (CVD) to a thickness of e.g. 1500 .ANG.. (This polycide
 combination gives an eventual sheet resistance in the range of 4-5
 .OMEGA./.quadrature..)
 3. Si.sub.3 N.sub.4 layer 214 (or another suitable material, e.g.
 oxynitride, as discussed below) is deposited.
 4. The First-poly-contact pattern (the "FPC" mask) is used to etch an
 opening through the nitride layer 214 in locations where contacts to the
 clad first-poly layer 210/212 will be formed over field oxide 202.
 This results in the structure shown in FIGS. 2A and 2B.
 5. The poly-1 mask is now used to pattern the gate polycide layer.
 This results in the structure shown in FIGS. 3A and 3B.
 6. A re-oxidation step (e.g. 5-30 minutes at a temperature of
 800-900.degree. C. in an atmosphere of H.sub.2 O/N.sub.2 or O.sub.2
 /N.sub.2, in the presently preferred embodiment) is then performed to
 improve substrate protection. This grows an additional thickness of oxide
 216 (e.g. 500 .ANG.) on the exposed portions of the active area, as well
 as on exposed portions of the polysilicon 210 and silicide 212.
 This results in the structure shown in FIGS. 4A and 4B.
 7. A conventional LDD implant is then performed. Deep anti-punch-through
 implants may also be performed at this stage if desired.
 8. Si.sub.3 N.sub.4 is then deposited conformally (e.g. to a thickness of
 1500 .ANG., in the presently preferred embodiment) and etched
 anisotropically, using an SF.sub.6 +CF.sub.4 etch chemistry with endpoint
 detection, to produce sidewall spacers 220. Note that the height of the
 sidewall spacers 220 on the poly-1 sidewalls is greater than that of the
 gate polycide structure. Note that smaller spacers 220 also appear on the
 sidewalls of the FPC aperture, in addition to those on the poly-1
 sidewalls.
 This results in the structure shown in FIGS. 5A and 5B.
 9. Masked n+ and p+ implants are now performed to form source/drain
 diffusions. The doses and energies are preferably selected to form
 junction depths of e.g. 0.1 to 0.15 microns for the n+ diffusions, and
 15-0.2 microns for the p+ diffusions. In this sample embodiment, the doses
 and energies are such that the sheet resistance of the unclad diffusions
 would be about 60 .OMEGA./.quadrature. for n+ and 130 .OMEGA./.quadrature.
 for p+; but the clad diffusions have a sheet resistance of about 2.3
 .OMEGA./.quadrature. for n+ and about 2.0 .OMEGA./.quadrature. for p+. (Of
 course these specific parameters can readily be changed as desired.)
 Conventional annealing is preferably now performed for dopant activation.
 10. An oxide masking layer is now deposited overall. The thickness of this
 layer is not particularly critical, e.g. 100-1000 .ANG., or more
 specifically 300 .ANG. in the presently preferred embodiment.
 11. Resist is then patterned to expose the oxide mask layer over the
 periphery, and a plasma fluoro-etch is performed to remove this oxide mask
 layer from the periphery. The resist is then stripped.
 12. An RCA cleanup is then performed (preferably using the formulations
 known to those skilled in the art as SC1 and SC2, followed by HF).
 13. Titanium is then deposited overall, e.g. to a thickness of 400 .ANG.,
 and, in the presently preferred embodiment, TiN is then deposited thereon
 by CVD to a thickness of 300 .ANG..
 14. An RTA anneal is then performed (e.g. maintaining a peak temperature of
 about 730.degree. C. for about 20 sec). This forms titanium silicide 610
 over exposed silicon and polysilicon, and TiN over oxide. (Optionally, of
 course, a furnace anneal can be used instead of the RTA steps.)
 15. The TiN is then stripped in an NH.sub.4 OH/H.sub.2 O.sub.2 H.sub.2 O
 solution.
 16. A second RTA anneal is then performed (e.g. maintaining a peak
 temperature of about 850.degree. C. for about 20 sec). This lowers the
 sheet resistance of the titanium silicide.
 These steps form silicided active areas in the periphery, as illustrated in
 FIG. 6. Note that two different suicides are present in this device
 structure: one silicide 610 clads the active areas, and the other silicide
 212 is a part of the gate polycide structure. In the preferred embodiment,
 the first silicide 610 is a titanium silicide (optionally overlaid with
 TiN), and the second silicide is a tungsten silicide. Preferably the first
 silicide has a composition of approximately TiSi.sub.2, and the second
 silicide has a composition of approximately WSi.sub.2.
 Conventional processing now resumes. For example, an interlevel dielectric
 (e.g. BPSG over undoped silica glass) is now deposited, and is etched
 using an oxide etch chemistry which is selective to Si.sub.3 N.sub.4. In
 the presently preferred embodiment, this performed using a fluoro-etch
 with sacrificial silicon in the chamber. See Singer, "A New Technology for
 Oxide Contact and Via Etch", SEMICONDUCTOR INTERNATIONAL, August 1993,
 p.36, which is hereby incorporated by reference. Metal is now deposited,
 patterned, and etched to form a desired interconnect pattern. A wide
 variety of conventional metallization structures may be used, e.g. Al:1%
 Si:1% Cu, or a Ti/W/Al stack, or other known thin film recipes. Processing
 may then continue with conventional further steps, e.g. deposition of a
 further interlevel dielectric and a second metal layer (if desired),
 contact sinter (if needed), deposition and densification of a protective
 overcoat and removal thereof to expose contact pad locations. Processing
 may include additional conventional steps to complete fabrication, e.g.
 deposition and planarization of further interlevel dielectric, via
 patterning, second metal deposition and etch, protective overcoat
 deposition, etching contact pad apertures, etc. etc. See generally, e.g.,
 VLSI TECHNOLOGY (2.ed. Sze 1988); G. Anner, PLANAR PROCESSING PRIMER
 (1990); R. Castellano, SEMICONDUCTOR DEVICE PROCESSING (1991); W. Runyan &
 K. Bean, SEMICONDUCTOR INTEGRATED CIRCUIT PROCESSING TECHNOLOGY (1990
 ed.); S. Wolf, SILICON PROCESSING FOR THE VLSI ERA (1985, 1990); and the
 annual proceedings of the IEDM conferences for years 1979 to date; all of
 which are hereby incorporated by reference.
 FIGS. 7A-7C are overlaid views of key mask portions of an SRAM cell in
 which self-aligned salicide cladding is present on diffusions which are
 used for VSS routing, but is not present on the source/drain diffusions of
 the transistors of the memory cells. These Figures are all parts of a
 single drawing, and are drawn to a common scale, but are separated here
 for clarity.
 FIG. 7A shows the active pattern, i.e. the pattern of areas 701 where field
 oxide 703 is not present, and where transistors can consequently be
 formed. The sample layout shown is a 4T cell which includes two
 cross-coupled NMOS driver transistors 710A and 710B, and two NMOS pass
 transistors 720A and 720B. Note that the long horizontal active portion
 750 at the center of the cell is used for routing VSS (ground) through
 multiple cells, and will be silicided as shown in FIG. 7C. The channel
 locations of transistors 710A, 710B, 720A, and 720B are also generally
 indicated.
 FIG. 7B shows two additional masks, FPCC and poly-1. The polycide layer 702
 provides the gates of transistors 710A, 710B, 720A, and 720B. Portions at
 top and bottom (marked WL) provide word lines, and gate the pass
 transistors 720. An n+ implant will dope all of the active areas 701 n+.
 except where covered by the polysilicon layer 702 (and its sidewall
 spacers).
 FIG. 7C shows the pattern of the active portion 750 which is used for
 routing VSS (ground) through multiple cells.
 Additional structures, not shown, provide cross-connections between the
 driver transistors 710 and complete the SRAM cell. For example, an
 additional polysilicon layer provides the resistive loads and the
 connection to the positive power supply.
 FIG. 8 is a floor plan of a 4T SRAM chip, in which self-aligned salicide
 cladding is present on the peripheral transistors, but not on the
 transistors of the memory cells. This sample embodiment is a 16M chip
 which is organized as 4M.times.4, but of course other organizations can be
 used. This sample embodiment includes four subarrays 810 (illustrated with
 hatching) which are protected from the salicidation. Peripheral circuits,
 such as row decoders 830 and column-decode/sense-amplifier circuitry 820,
 provide data access to the memory cells.
 FIG. 9 is a floor plan of a DRAM chip, in which self-aligned salicide
 cladding is present on the peripheral transistors, but not on the pass
 transistors of the memory cells. This sample embodiment includes eight
 subarrays 910 (illustrated with hatching). Each subarray includes 2M 1T
 memory cells, and is protected from the salicidation. The peripheral
 circuits, such as row decoders, column-decoders, sense-amplifiers, input
 latches, and output buffers, are all conventional and not separately
 indicated.
 Modifications and Variations
 As will be recognized by those skilled in the art, the innovative concepts
 described in the present application can be modified and varied over a
 tremendous range of applications, and accordingly the scope of patented
 subject matter is not limited by any of the specific exemplary teachings
 given. For example, as will be obvious to those of ordinary skill in the
 art, other circuit elements can be added to, or substituted into, the
 specific circuit topologies shown.
 Of course, the specific etch chemistries, layer compositions, and layer
 thicknesses given are merely illustrative, and do not by any means delimit
 the scope of the claimed inventions.
 For example, many of the disclosed innovations are not limited to processes
 like those of FIGS. 1-5B, nor even to analogous processes, but can be used
 in a huge variety of integrated circuit processes.
 For another example, the sidewall spacers do not necessarily have to be
 silicon nitride, but in some alternative embodiments can be silicon
 dioxide or another dielectric.
 The invention can also be used with other deposited suicides instead of
 TaSi.sub.2, including for example, without limitation, silicides of
 tungsten, molybdenum, palladium, platinum, cobalt, nickel, chromium,
 hafnium, titanium or vanadium.
 The invention can also be used with other salicided silicides instead of
 TiSi.sub.2, including for example, without limitation, silicides of
 cobalt, nickel, or vanadium.
 Similarly, the nitride sidewall spacers of the presently preferred
 embodiment are not strictly necessary to the practice of the invention.
 While the inventions have been described with primary reference to a
 single-poly process, it will be readily recognized that these inventions
 are equally applicable to double-poly or triple-poly structures and
 processes.
 Similarly, it will be readily recognized that the described process steps
 can also be embedded into hybrid process flows, such as BiCMOS or
 smart-power processes.
 It should also be understood that the disclosed innovations can be applied
 to a wide variety of integrated circuits. However, the use of array-masked
 salicidation is most attractive in battery backed SRAMs (whether 4T, 6T,
 or with TFT loads).
 According to a disclosed class of innovative embodiments, there is
 provided: An integrated circuit memory, comprising: an array of memory
 cells; and peripheral circuits, include sense amplifiers and address
 decode logic, connected to provide data access to said cells from external
 pins; wherein at least some portions of said peripheral circuits include
 field-effect transistors having gates formed from a patterned conductive
 thin-film layer and having source/drain regions of a first conductivity
 type which are clad with a self-aligned metal silicide layer; and wherein
 at least some portions of said memory cells include field-effect
 transistors having gates formed from said conductive thin-film layer and
 having source/drain regions of said first conductivity type which are not
 clad with a self-aligned metal silicide layer.
 According to another disclosed class of innovative embodiments, there is
 provided: An integrated circuit memory, comprising: a array of memory
 cells, individual ones of said cells being connected to be powered by
 first and second supply voltages, and including a pair of field-effect
 driver transistors having source/drain regions thereof provided by
 diffusions in a substantially monocrystalline semiconductor material, said
 driver transistors being cross-coupled to pull a pair of complementary
 data nodes toward said first supply voltage; a pair of load elements
 connected to pull at least one of said data nodes toward said second
 supply voltage; and at least one pass transistor connected to selectably
 provide access to one of said data nodes; and peripheral circuits, include
 sense amplifiers and address decode logic, connected to provide data
 access to said cells from external pins; wherein at least some portions of
 said peripheral circuits include field-effect transistors having
 source/drain regions thereof provided by diffusions in said semiconductor
 material which are clad with a self-aligned metal silicide layer; and
 wherein said source/drain regions of said driver transistors are not clad
 with a self-aligned metal silicide layer.
 According to another disclosed class of innovative embodiments, there is
 provided: An integrated circuit memory, comprising: an array of memory
 cells, individual ones of said cells being connected to be powered by
 first and second supply voltages, and including a pair of field-effect
 driver transistors having source/drain regions thereof provided by
 diffusions in a substantially monocrystalline semiconductor material, said
 driver transistors being cross-coupled to pull a pair of complementary
 data nodes toward said first supply voltage; a pair of load elements
 connected to pull at least one of said data nodes toward said second
 supply voltage; and at least one pass transistor connected to selectably
 provide access to one of said data nodes; peripheral circuits, include
 sense amplifiers and address decode logic, connected to provide data
 access to said cells from external pins; wherein at least one said supply
 voltage is routed to said cells through diffusions which are clad with a
 self-aligned metal silicide layer; and wherein said source/drain regions
 of said driver transistors are not clad with a self-aligned metal silicide
 layer.
 According to another disclosed class of innovative embodiments, there is
 provided: An integrated circuit memory, comprising: an array of memory
 cells, individual ones of said cells including field-effect transistors
 having source/drain regions thereof provided by diffusions in a
 substantially monocrystalline semiconductor material, individual ones of
 said cells being connected to be powered by first and second supply
 voltages; and peripheral circuits, include sense amplifiers and address
 decode logic, connected to provide data access to said cells from external
 pins; wherein at least one said supply voltage is routed to said cells
 through diffusions which are clad with a self-aligned metal silicide
 layer.
 According to another disclosed class of innovative embodiments, there is
 provided: A fabrication method, comprising the steps of: a) providing a
 substrate having monocrystalline semiconductor material in active areas,
 at a first surface thereof, which are laterally separated by isolation
 regions; b) forming a patterned gate layer overlying and capacitively
 coupled to portions of ones of said active areas, in locations which
 define transistor portions of memory cells and also define transistor
 portions of peripheral logic; c) forming self-aligned dielectric spacers
 along the edges of said thin-film layer; and d) depositing and reacting a
 metal on at least some ones of said active areas, to form a metal silicide
 at the surfaces of said active areas; wherein a masking step is used in
 connection with said step d.), in locations such that said step (d.)
 ultimately provides said metal silicide in said transistor portions of
 said peripheral logic, but not in said transistor portions of said memory
 cells.