Jitter monitoring circuit

A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.

BACKGROUND

In electronic and/or telecommunication applications, jitter is a time deviation from a true periodicity of a presumably periodic signal. Among various causes of the jitter are electromagnetic interference (EMI) and crosstalk with other periodic or non-periodic signals. Such jitter is typically considered as a noise effect in a circuit, device or system. The jitter generally cause various issues for a respective circuit, device or system such as, for example, causing a display monitor to flicker, disadvantageously affecting an ability of a processor of a desktop or server to perform as originally intended operation, inducing clicks or other undesired effects in audio signals, loss of transmitted data between network devices, etc. Thus, there exists a need for a technique to accurately and quickly detect the presence of jitter in a circuit, device or system, and further determine the amount of such jitter (e.g., the range of the jitter).

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or one or more intervening elements may be present.

The present disclosure provides various embodiments of a jitter monitoring circuit that can detect a presence of jitter in a clock signal based on a noise window, and can further accurately determine the magnitude of the noise window. In some embodiments, the jitter monitoring circuit determines the presence of jitter by detecting whether a timing difference of respective transitioning edges of the clock signal and a reference clock signal exceeds the noise window. In response to detecting the presence of jitter, the clock signal and reference clock signal are respectively adjusted (e.g., delayed) by first and second delay circuits to cause the timing difference of the respective transitioning edges to be less than the noise window. Further, the jitter monitoring circuit includes a loop control circuit configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits. In some embodiments, based on a first oscillation frequency of the alternately formed first and second oscillation loops passing through the first delay circuit and a second oscillation frequency of the alternately formed first and second oscillation loops passing through the second delay circuit, the jitter monitoring circuit can accurately determine the noise window.

FIG. 1illustrates a schematic diagram of a jitter monitoring circuit100, in accordance with some embodiments. In some embodiments, the jitter monitoring circuit100is configured to detect a presence of jitter in a clock signal (e.g.,101) by determining whether the timing difference between respective transition edges of the clock signal and a reference clock signal (e.g.,103) exceeds a noise window, and further determine the magnitude of the noise window. Details of the jitter monitoring circuit100will be discussed as follows.

The clock signal101may be generated by a clock generation circuit, for example, a phase-locked-loop (PLL) circuit integrated in a bigger system circuit (e.g., a system-on-chip (SoC) circuit, an application-specific integrated circuit (ASIC), etc.). The reference clock signal103may be provided by an external crystal circuit, which is generally considered as a relatively reliable clock generation source, thus making the reference clock signal103a reliable reference. In some other embodiments, the reference clock103can be provided by either delaying the clock signal101by a pre-defined period of time or from another low-noise PLL, even off-chip instruments. The clock generation circuit, which provides the clock signal101, may be configured to provide one or more synchronous or asynchronous functionalities to the bigger system circuit. Thus, by coupling the disclosed jitter monitoring circuit100to such a bigger system circuit, the clock signal101may be accurately monitored in a real-time manner.

As shown in the illustrated embodiment ofFIG. 1, the jitter monitoring circuit100includes a loop control circuit104, a delay control circuit106, a jitter detector108, a first controllable buffer110, a first delay circuit112, a first switch114, one or more buffers116(which are herein referred to as “first buffer116”), a first inverter118, a first multiplexer120, a first frequency counter122, a second controllable buffer130, a second delay circuit132, a second switch134, one or more buffers136(which are herein referred to as “second buffer136”), a second inverter138, a second multiplexer140, a second frequency counter142, one or more registers144(which are herein referred to as “register144”), and a main control circuit146. Although not shown, in some embodiments, the main control circuit146is coupled to each of the other components of the jitter monitoring circuit100(e.g.,104,106,144, etc.) to control them, which will be discussed in further detail below.

Referring still toFIG. 1, the jitter detector108is configured to respectively receive the clock signal101through the first controllable buffer110and first delay circuit112and the reference clock signal103through the second controllable buffer130and second delay circuit132. As such, the jitter detector108may receive a delayed clock signal101′, which is delayed by the first delay circuit112, at its input108A, and a delayed reference clock signal103′, which is delayed by the second delay circuit132, at its input108B. Further, the jitter detector108is configured to compare respective transition edges between the delayed clock signal101′ and the delayed reference clock signal103′ so as to determine whether the clock signal101contains jitter that exceeds a noise window. If so, the jitter detector108may output a high logic state (hereinafter “logic 1”) to the register144. On the other hand, if no jitter is detected or the jitter in the clock signal101does not exceed the noise window, the jitter detector108may output a low logic state (hereinafter “logic 0”) to the register144. Thus, it is understood that over a certain period of time (after the jitter detector108compares a plurality of transition edges between the delayed clock signal101′ and the delayed reference clock signal103′), the jitter detector108may output a plurality of logic 1's, logic 0′, or combination thereof. In some embodiments, when the jitter detector108compares the delayed clock signal101′ with the delayed reference clock signal103′ to detect the above-mentioned jitter in the clock signal101, the jitter monitoring circuit100may be referred to as operating at a “Normal Monitoring Mode.” Details of the jitter detector108will be discussed in feather detail below with reference toFIGS. 2A, 2B, 3A, 3B, and 4.

In some embodiments, the main control circuit146is configured to read such logic states stored in the register144, and in response to reading one or more logic 1's, the main control circuit146may cause the delay control circuit106to control the first and second delay circuits112and132to respectively tune the timings of the clock signal101and reference clock signal103(i.e., delay) until the jitter detector108again outputs the logic 0 (i.e., the jitter contained in the clock signal does not exceed the noise window). In some embodiments, the first and second delay circuits112and132may be each implemented by a digitally controlled delay line (DCDL). In such embodiments, the delay control circuit106may “digitally” adjust how much delay the delay circuits112and132will apply on the clock signal101and reference clock signal103, respectively. For example, the delay control circuit106may select the delay code out of 0 to 63 for the second delay circuit132(hereinafter “second delay code”) as31. Generally, each delay code corresponds to a certain time amount of delay, and the larger the delay code is, the longer the delay is. On the other hand, the delay control circuit106may sweep the delay code from 0 to 63 for the first delay circuit112(hereinafter “first delay code”) to allow the output of jitter detector108to transition back to the logic 0.

Continuing with the above example, the main control circuit146may acknowledge that when the first delay codes range from 30 to 33 (while the second delay code is fixed as31), the jitter detector108can accordingly output plural logic 0's. As such, the jitter monitoring circuit100, or more specifically the main control circuit146, may determine that the noise window, actually used by the jitter detector108to selectively output either a logic 1 or 0, corresponds to a delay code window that is defined by the first delay code set at 29 (one delay code less than 30) and the second delay code set at 31, or the first delay code set at 34 (one delay code greater than 33) and the second delay code set at 31. Accordingly, the main control circuit146may cause the delay control circuit106to fix the first delay code at 29 and the second delay code at 31, for example, and cause the loop control circuit104to alternately form first and second oscillation loops passing through each of the first and second delay circuits112and132. In some embodiments, by forming such first and second oscillation loops for each of the first and second delay circuits112and132, the magnitude of the noise window actually used by the jitter detector108can be accurately determined, which will be discussed in further detail below. In some embodiments, when the loop control circuit104alternately forms the oscillation loops for each of the first and second delay circuits112and132, the jitter monitoring circuit100may be referred to as operating at a “Noise Window Calculation Mode.”

In some embodiments, when operating at the Noise Window Calculation Mode, the delay control circuit106may cause the first and second delay circuits112and132to respectively use the above-discussed first and second delay codes for the clock signal101and reference clock signal103, the loop control circuit104may deactivate the controllable buffers110and130to respectively decouple the clock signal101from the first delay circuit112and the reference clock signal103from the second delay circuit132thereby allowing plural oscillation loops passing through each of the first and second delay circuits112and132, and the main control circuit146may activate the first and second frequency counters122and142to count respective cycle numbers of oscillations passing through the first and second delay circuits112and132.

More specifically, after the first controllable buffer110is deactivated and the first delay circuit112uses the first delay code, a first oscillation loop151, passing through the first delay circuit112, the first switch114, the first buffer116, the first inverter118, and the first multiplexer120, can be formed by the first switch114to couple its terminal114A to terminal114B and by the first multiplexer120to select its input120A; and a second oscillation loop153, passing through the first delay circuit112, the first switch114, the second buffer136, the second inverter138, and the first multiplexer120, can be formed by the first switch114to couple its terminal114A to terminal114C and by the first multiplexer120to select its input120B. In some embodiments, the loop control circuit104causes the first switch114to couple its terminal114A to either terminal114B or114C, and causes the first multiplexer120to make the selection between inputs120A and120B. In other words, the first oscillation loop151and second oscillation loop153, passing through the first delay circuit112, are formed by the loop control circuit104. Further, in some embodiments, the loop control circuit104may alternately form the first oscillation loop151and second oscillation loop153to allow the first frequency counter122to count a total cycle number, N1, presented by the first and second oscillation loops151and153.

In some embodiments, the first frequency counter122counts the total cycle number N1of the first and second oscillation loops151and153by comparing the frequency presented at node “X” (hereinafter “frequency X”) with a reference frequency154, or a lowered reference frequency154(which will be discussed below), that is substantially less than the frequency X. As such, it is understood by persons of ordinary skill in the art that the corresponding period of the reference frequency154is substantially greater than the corresponding period of the frequency X. In some embodiments, the first frequency counter122may determine the total cycle number N1of the first and second oscillation loops151and153by counting how many corresponding periods of the frequency X are contained in one corresponding period of the reference frequency154.

Similarly, after the second controllable buffer130is deactivated and the second delay circuit132uses the second delay code, a first oscillation loop155, passing through the second delay circuit132, the second switch134, the second buffer136, the second inverter138, and the second multiplexer140, can be formed by the second switch134to couple its terminal134A to terminal134B and by the second multiplexer140to select its input140A; and a second oscillation loop157, passing through the second delay circuit132, the second switch134, the first buffer116, the first inverter118, and the second multiplexer140, can be formed by the second switch134to couple its terminal134A to terminal134C and by the second multiplexer140to select its input140B. In some embodiments, the loop control circuit104causes the second switch134to couple its terminal134A to either terminal134B or134C, and causes the second multiplexer140to make the selection between inputs140A and140B. In other words, the first oscillation loop155and second oscillation loop157, passing through the second delay circuit132, are formed by the loop control circuit104. Further, in some embodiments, the loop control circuit104may alternately form the first oscillation loop155and second oscillation loop157to allow the second frequency counter142to count a total cycle number, N2, presented by the first and second oscillation loops155and157.

In some embodiments, the second frequency counter122counts the total cycle number N2of the first and second oscillation loops155and157by comparing the frequency presented at node “Y” (hereinafter “frequency Y”) with the reference frequency155, or the lowered reference frequency155(which will be discussed below), that is substantially less than the frequency Y. As such, it is understood by persons of ordinary skill in the art that the corresponding period of the reference frequency155is substantially greater than the corresponding period of the frequency Y. In some embodiments, the second frequency counter142may determine the total cycle number N2of the first and second oscillation loops155and157by counting how many corresponding periods of the frequency Y are contained in one corresponding period of the reference frequency155.

By retrieving the cycle number N1of the alternately formed oscillation loops passing through the first delay circuit112and the cycle number N2of the alternately formed oscillation loops passing through the second delay circuit132, the noise window, actually used by the jitter detector108, can be accurately calculated, in accordance with some embodiments. This is because the actually used noise window is determined by a difference between the delay provided by the first delay circuit112and the delay provided by the second delay circuit132, and in some embodiments, such a difference between the delay provided by the first delay circuit112and the delay provided by the second delay circuit132can be accurately determined by the reference frequency155and a difference between the cycle numbers N1and N2, for example,

NReference⁢⁢Frequency⁢⁢155⁢(1N1-1N2)
where N is a predefined constant, which will be discussed as follows.

In some embodiments, the reference frequency155may be provided by an external crystal circuit, which is generally considered as a relatively reliable clock generation source, and further divided by a predefined constant. In some embodiments, the reference frequency155may be provided to be substantially less than the frequency X and frequency Y, and, moreover, the predefined constant N is selected to be a positive integer (e.g., 32) to further lower the reference frequency155as

Reference⁢⁢Frequency⁢⁢155N
(hereinafter “lowered reference frequency155”). Accordingly, the corresponding period of such a lowered reference frequency is

NReference⁢⁢Frequency⁢⁢155.
In some embodiments, the cycle number N1is determined by dividing the corresponding period of the lowered reference frequency155by the corresponding period of frequency X (i.e.,

N1=(NReference⁢⁢Frequency⁢⁢155)Corresponding⁢⁢Period⁢⁢of⁢⁢Frequency⁢⁢X),
and the cycle number N2is determined by dividing the corresponding period of the lowered reference frequency155by the corresponding period of frequency Y (i.e.,

N2=(NReference⁢⁢Frequency⁢⁢155)Corresponding⁢⁢Period⁢⁢of⁢⁢Frequency⁢⁢Y).
Since the cycle numbers N1and N2are provided by the frequency counters122and142, respectively, the corresponding periods of frequency X and frequency Y can be accordingly determined based on the above equations of N1and N2, in accordance with some embodiments. Further, since the actually used noise window used by the jitter detector108is determined by the difference between the delay provided by the first delay circuit112and the delay provided by the second delay circuit132, calculating a difference between the corresponding periods of frequency X and frequency Y (i.e.,

NReference⁢⁢Frequency⁢⁢155⁢(1N1-1N2))
can accurately determine the noise window used by the jitter detector108, which will be explained as follows.

In some embodiments, the corresponding period of the frequency X is determined by dividing a first weighted sum by N1, wherein the first weighted sum can be a sum of: the delay provided by the first delay circuit112(D112) times N1, the delay provided by the first switch114, the delays collectively provided by the first buffer116and first inverter118(D116+118) times the cycle number of the first oscillation loop151(which is (N1+1)/2 when N1is an odd integer, and is N1/2 when N1is an even integer), the delays collectively provided by the second buffer136and second inverter138(D136+138) times the cycle number of the second oscillation loop153(which is (N1−1)/2 when N1is an odd integer, and is N1/2 when N1is an even integer), and the delay provided by the first multiplexer120, wherein the delays respectively provided by the first switch114and first multiplexer120are substantially negligible when compared to the others. Thus, in accordance with some embodiments, the corresponding period of the frequency X may be expressed as,

Similarly, the corresponding period of the frequency Y over the N2cycle is determined by dividing a second weighted sum by N2, wherein the second weighted sum can be a sum of: the delay provided by the second delay circuit132(D132) times N2, the delay provided by the second switch134, the delays collectively provided by the second buffer136and second inverter138(D136+138) times the cycle number of the first oscillation loop155(which is (N2+1)/2 when N2is an odd integer, and is N2/2 when N2is an even integer), the delays collectively provided by the first buffer116and first inverter118(D116+118) times the cycle number of the second oscillation loop157(which is (N2−1)/2 when N2is an odd integer, and is N2/2 when N2is an even integer), and the delay provided by the second multiplexer140, wherein the delays respectively provided by the second switch134and second multiplexer140are substantially negligible when compared to the others. Thus, the corresponding period of the frequency Y may be expressed as,

1N2[⁢D132×N2+D136+138×(N2+12⁢⁢or⁢⁢N22)+D116+118×(N2-12⁢⁢or⁢⁢N22)],
in accordance with some embodiments.

In accordance with some embodiments of the present disclosure, after simplification, the corresponding periods of the frequency X and frequency Y have plural common terms, ½D116+118, and ½D136+138, which respectively account for delays provided by the components (116and118) and (136+138). By calculating the difference between the corresponding periods of the frequency X and frequency Y, such common terms can be canceled out and only the difference between the delay provided by the first delay circuit112(D112) and the delay provided by the second delay circuit132(D132) remains such that the noise window actually used by the jitter detector108can be accurately determined.

In an example, when the reference frequency155is provided as 200 MHz and the predefined constant is set at 32, the corresponding period of the lowered reference frequency is about 160 nanoseconds. After the oscillation loops151and153passing through the first delay circuit112and the oscillation loops155and157passing through the second delay circuit132are respectively formed, the first frequency counter122determines (counts) N1as 319±1 and the second frequency counter142determines (counts) N2as 316±1 such that the corresponding period of the frequency X can be calculated to range from 500 (i.e., 160/320) picoseconds to 503.1 (i.e., 160/318) picoseconds, and the corresponding period of the frequency Y can be calculated to range from 504.7 (i.e., 160/317) picoseconds to 507.9 (i.e., 160/315) picoseconds. As such, the actually used noise window can be determined to range from 1.6 (i.e., 504.7-503.1) picoseconds to 7.9 (i.e., 507.9-500) picoseconds.

In another example, when the reference frequency155is provided as 50 MHz and the predefined constant is set at 32, the corresponding period of the lowered reference frequency is about 640 nanoseconds. After the oscillation loops151and153passing through the first delay circuit112and the oscillation loops155and157passing through the second delay circuit132are respectively formed, the first frequency counter122determines (counts) N1as 1277±1 and the second frequency counter142determines (counts) N2as 1265±1 such that the corresponding period of the frequency X can be calculated to range from 500.8 (i.e., 640/1278) picoseconds to 501.6 (i.e., 640/1276) picoseconds, and the corresponding period of the frequency Y can be calculated to range from 505.5 (i.e., 640/1266) picoseconds to 506.3 (i.e., 640/1264) picoseconds. As such, the actually used noise window can be determined to range from 3.9 (i.e., 505.5−501.6) picoseconds to 5.5 (i.e., 506.3−500.8) picoseconds.

FIGS. 2A and 2Brespectively illustrate circuit diagrams of different embodiments of the jitter detector108, in accordance with some embodiments. More specifically, the illustrated embodiment shown inFIG. 2Ais a p-type jitter detector configured to compare respective “rising” edges of the clock signal101and the reference clock signal103, and the illustrated embodiment shown inFIG. 2Bis an n-type jitter detector configured to compare respective “falling” edges of the clock signal101and the reference clock signal103. For purposes of clarity, the p-type jitter detector inFIG. 2Ais herein referred to as “pJD200,” and the n-type jitter detector inFIG. 2Bis herein referred to as “nJD250.”

Referring first toFIG. 2A, the pJD circuit200includes a first delay circuit210, a second delay circuit212, a logic gate214, transistors216,218,220,222,224,226,228, and230, inverters232and234, a logic gate236, and a tuning circuit238. In some embodiments, the first and second delay circuits210and212may each include a plurality of serially coupled buffers, inverters, or the like (not shown). The first delay circuit210is configured to receive a clock signal201and provide a delayed clock signal, e.g.,201′, and the second delay circuit212is configured to receive a reference clock signal203and provide a delayed reference clock signal, e.g.,203′. In some embodiments, the clock signal201and reference clock signal203in the illustrated embodiment ofFIG. 2Amay correspond to the signals received at the inputs108A and108B of the jitter detector108, respectively (FIG. 1). That is, the clock signal201and reference clock signal203may be the delayed clock signal101′ and delayed reference clock signal103′ that have been respectively delayed by the first delay circuit112and second delay circuit132. In some embodiments, the logic gate214of the pJD circuit200may include a NAND logic gate that is configured to perform a NAND logic function on the clock signal201and the reference clock signal203so as to provide a control signal214′ based on a NAND'ed result of logic states of the clock signal201and the reference clock signal203.

In some embodiments, the transistors216,224,226,228, and230may be each implemented by an n-type metal-oxide-semiconductor (NMOS) field-effect-transistor (FET), and the transistors218,220, and222may be each implemented by a p-type metal-oxide-semiconductor (PMOS) field-effect-transistor (FET). However, it is noted that the transistors216to230may each be implemented as any of various types of transistors (e.g., a bipolar junction transistor (BJT), a high-electron mobility transistor (HEMT), etc.) while remaining within the scope of the present disclosure.

More specifically, the transistors216and218are commonly coupled to a first supply voltage207(e.g., Vdd) at respective drain and source, and gated by the control signal214′. The transistor220is coupled to the transistor216's source by its respective source, and gated by the delayed clock signal201′. Similarly, the transistor222is coupled to the transistor218's drain by its respective source, and gated by the delayed reference clock signal203′. And the transistor218's drain is coupled to the transistor216's source. The transistors224and226are coupled to a drain of the transistor220by their respective drains at a common node “A,” and to a second supply voltage209(e.g., Vss or ground) by their respective sources. In some embodiments, the transistor224is gated by the control signal214′. Similarly, the transistors228and230are coupled to a drain of the transistor222by their respective drains at a common node “B,” and to the second supply voltage209(e.g., Vss or ground) by their respective sources. In some embodiments, the transistor230is gated by the control signal214′.

More specifically, in some embodiments, the transistors226and228are cross-coupled to each other. That is, a gate of the transistor226is coupled to the drain of the transistor228and a gate of the transistor228is coupled to the drain of the transistor226so as to allow the transistors226and228to function as a latch circuit, which will be discussed in further detail below with respect toFIG. 3A.

In some embodiments, the inverters232and234are configured to receive signals present at nodes A and B (hereinafter “signal231” and “signal233”), respectively, as respective input signals, and provide respective logically inverted signals235and237. The signals235and237are received by the logic gate236, which may be implemented as an XOR logic gate in some embodiments. The logic gate236is configured to perform an XOR logic function on the signals235and237so as to provide the signal205whose logic state is determined based on an XOR'ed result of logic states of the signals235and237. In some embodiments, the signal205may be the output of the jitter detector108.

An exemplary circuit diagram of the tuning circuit238is illustrated inFIG. 4. In some embodiments, the tuning circuit238includes one or more capacitors402,404, and406coupled between the nodes A and B by respective switches408,410, and412. More specifically, the capacitor402includes two conductive plates402-1and402-2, wherein one conductive plate (e.g.,402-1) is coupled to the node B and the other conductive plate (e.g.,402-2) is coupled to the node A through the switch410; the capacitor404includes two conductive plates404-1and404-2, wherein one conductive plate (e.g.,404-1) is coupled to the node B and the other conductive plate (e.g.,404-2) is coupled to the node A through the switch408; and the capacitor406includes two conductive plates406-1and406-2, wherein one conductive plate (e.g.,406-1) is coupled to the node B and the other conductive plate (e.g.,406-2) is coupled to the node A through the switch412.

According to some embodiments, each of the switches408,410and412may be selectively turned on/off to tune a noise window, of the pJD circuit200. More specifically, when more switches are turned on, more capacitors are electrically coupled between the nodes A and B, which causes the noise window to become wider. Conversely, when less switches are turned on, less capacitors are electrically coupled between the nodes A and B, which causes the noise window to become narrower. Although only three capacitors402,404and406(and corresponding switches408,410and410) are shown in the illustrated embodiment ofFIG. 4, it is understood that any desired number of capacitors (and corresponding switches) may be included in the tuning circuit238.

As mentioned above, the noise window is used, by the jitter detector108(the pJD circuit200in the example ofFIG. 2A), to determine whether the jitter contained in the clock signal101exceeds the noise window. In some embodiments, although the noise window of the tuning circuit238can be designed before manufacturing, due to a variety of process variations on the components of the tuning circuit238, the noise window actually used by the jitter detector108may be deviated from the originally designed noise window. In this regard, the disclosed jitter monitoring circuit100can accurately determine the noise window actually used by the jitter detector108, as discussed above.

FIG. 3Aillustrates exemplary waveforms of signals201,203,214′,201′,203′,231,233, and205to operate the pJD circuit200ofFIG. 2A, in accordance with some embodiments. Each waveform of the signals201,203,214′,201′,203′,231,233, and205illustrated inFIG. 3Avaries between logic 1 and logic 0 over time. It is noted that the clock signal201and reference clock signal203may respectively correspond to the delayed clock signal101′ and delayed reference clock signal103′.

As mentioned above, jitter is a deviation from a true periodicity of a presumably periodic signal. In some embodiments, the reference clock signal203may be used as the “presumably periodic signal” that is used to examine the clock signal201and to determine whether a deviation of the clock signal201from the presumably periodic signal203exceeds a noise window. In some embodiments, when the clock signal201contains jitter (i.e., has a deviation) that exceeds the noise window (i.e., an intolerable amount of jitter) on its respective rising edge, the pJD circuit200may pull the signal205to logic 1, as mentioned above.FIG. 3Aillustrates a scenario where the clock waveform signal201contains jitter that exceeds a predetermined threshold, which is detected by the pJD circuit200, and the corresponding signals that are used or generated by the pJD circuit200(i.e., signals214′,201′,203′,231,233and205).

As shown inFIG. 3A, the clock signal201's rising edge201rdeviates from the reference clock signal203's rising edge203r. More specifically, the rising edge201roccurs “ΔT” ahead of the rising edge203r. Alternative stated, the rising edges201rand203rhave a timing difference ΔT from each other. As described above, the logic gate214performs the NAND logic function on the clock signal201and the reference clock signal203. As known in the art, only when both the signals201and203transition to logic 1, the logic gate214can output the control signal214′ as logic 0.

Prior to time “t0,” the control signal214′ is at logic 1, and at time t0, the control signal214′ remains at logic 1 because the logic states of the signals201and203are at logic 0. It is noted that the transistors216,218,224, and230are all gated by the signal214′. Accordingly, when the control signal214′ is at logic 1, the “NMOS” transistors216,224, and230are turned on, and the “PMOS” transistor218is turned off. In some embodiments, the transistor216may serve as a pre-charge circuit to pre-charge the transistors220and222, and more specifically, the sources of the transistors220and222, before the transistors220and222are turned off since, at time t0, the transistors220and222are turned on. The transistor218may serve as a current source after the control signal214's is pulled to logic 0, and the transistors224and230are configured to perform a reset function after the control signal214's is pulled back to logic 1, which will be discussed further below, respectively. Moreover, in some embodiments, a respective size of the transistor216may be selected to be substantially smaller than other transistors (e.g., the transistors220,222,224,226,228, and230) such that prior to time t0(e.g., before signal214′ transitions to logic 0) a stand-by current (also known as a “DC current”) may be minimized and respective logic states at nodes A and B may remain at logic 0. Thus, noise and/or false logic state(s), caused by the latch circuit formed by the transistors226and228, can be advantageously avoided.

Subsequently, at time “t1,” since both the clock signal201and the reference clock signal203have transitioned to logic 1, respectively, the (NAND) logic gate214transitions the control signal214′ to logic 0, which turns off the transistor216and turn on the transistor218such that the transistor216may stop pre-charging the transistors220and220and the transistor218may start charging the voltage levels at nodes A and B through the ON transistors220and222, respectively. It is noted that because of signal propagation delays caused by the logic gate214, the control signal214′ may not transition to logic 0 immediately after both signals201and203transition to logic 1. As mentioned above, the first and second delay circuits210and212respectively delay the clock signal201and the reference clock signal203. More specifically, in some embodiments, the first delay circuit210may delay the clock signal201by a delay “ΔT1” so as to provide the delayed signal201′ as shown; and the second delay circuit212may delay the clock signal203by a delay “ΔT2” so as to provide the delayed signal203′ as shown. In some embodiments, the delays ΔT1and ΔT2may be substantially similar to each other.

At time “t2,” because of the delays, rising edges of the delayed signals201′ and203′ have not been received by the “PMOS” transistors220and222, i.e., the delayed signals201′ and203′ are still at logic 0. Thus, the transistors220and222remain in the ON state. And the transistor216remains OFF and the transistor218remains ON because the control signal214′ has been pulled to logic 0 at time t1. The transistor218, which serves as the current source as mentioned above, is configured to keep charging voltage levels at nodes A and B. As such, the voltage levels at nodes A and B (i.e., the signals231and233) may be charged to logic 1 through the ON transistors220and222.

At time “t3,” the rising edge of the delayed signal201′ is received by the gate of the transistor220so that the transistor220is turned off. Accordingly, the voltage level at the node A (i.e., the signal231) starts being discharged through the transistor226at time t3. Similarly, at time “t4,” the rising edge of the delayed signal203′ is received by the gate of the transistor222so that the transistor222is turned off. Accordingly, the voltage level at the node B (i.e., the signal233) starts being discharged through the transistor228at time t4. In some embodiments, because of the substantially similar delays ΔT1and ΔT2, the timing difference “ΔT” between the rising edges201rand203ris reflected to the delayed signals201′ and203′ accordingly to turn off the transistors220and222at different times. The signals231and233may start being discharged at different times, i.e., the times t3and t4are different and the time t4is subsequent to the time t3. As such, the signal231may transition to logic 0 faster than the signal233. Moreover, as mentioned above, the transistors226and228function as a latch circuit. That is, once either one of the signals231and233transitions to a detectable logic state (e.g., a low enough voltage level), the logic states of the signals231and233may be latched to their current respective states. In a non-limiting example, when either one of the signals231and233transitions to a low enough voltage level, the logic state of the signal that transitions to the low enough voltage level may be latched to logic 0, and the logic state of the other signal may be complementarily latched to logic 1 (i.e., stops being discharged).

In the example ofFIG. 3A, since the signal231transitions to logic 0 (i.e., a low enough voltage level) at about time “t5” while the signal233is still being discharged, the logic states of the signals231and233may be latched to logic 0 and logic 1, respectively. That is, the signal231is latched to logic 0 and the signal233stops being discharged and latched to logic 1. In an example, in a scenario where the signals231and233start discharging at the same time (i.e., t3=t4) or at two substantially close times (i.e., t4is substantially close to t3), the logic states of the signals231and233become non-differentiable (i.e., both logic states of the signals231and233are at either logic 1 or logic 0), which causes the latch circuit formed by the transistors226and228to fail to latch a logic state within such a narrow timing difference between times t3and t4. Alternatively stated, when the timing difference between times t3and t4becomes smaller than the noise window, the latch circuit formed by the transistors226and228cannot latch signal231and signal233into inversed logic states (either logic 1 or logic 0).

On the other hand, as shown inFIG. 3A, when the timing difference between times t3and t4exceeds the noise window, the logic states of the signals231and233are differentiable because the logic state of the signal231transitions to logic 0 first. Accordingly, the latch circuit formed by the transistors226and228can latch the logic states of the signals231and233as logic 0 and logic 1, respectively. Subsequently, the signals231and233are logically inverted through the respective inverters232and234to become the signals235(now transitioning to logic 1) and237(now transitioning to logic 0).

At time “t6,” the logic gate236performs the XOR logic function on the logically inverted signals235and237. As known in the art, an XOR logic gate outputs a logic 1 when inputs of the XOR logic gate are in different logic states. Accordingly, the (XOR) logic gate236transitions the signal205to logic 1 at time t6. As mentioned above, when the signal205is pulled to logic 1, the pJD circuit200may thus determine that the deviation ΔT of the rising edge201r(of the clock signal201) from the rising edge203′ (of the reference clock signal203) exceeds the noise window, in accordance with some embodiments.

Subsequently, at time “t7,” since at least one of the clock signal201and the reference clock signal203transitioned to logic 0, the control signal214′ (NAND'ing at least one LOW from either the signal201or signal203) transitions to logic 1. Accordingly, the transistors224and230are turned on. As mentioned above, the transistors224and230, in some embodiments, may form a reset circuit. That is, when the transistors224and230are turned on, such a reset circuit is enabled, which starts to discharge the signals231and233. In some embodiments, the signal233may be pulled back to logic 0 slightly after time t7.

At time “t8,” the signals235and237both transition to logic 1 by logically inverting the signals231and233through the inverters232and234, respectively, so that the signal205is reset to logic 0 (XOR'ing two logic 1's of the signals235and237). It is noted that because of some signal propagation delays caused by the inverters232and234, respectively, the signal205may not transition to logic 0 immediately after the signals231and233are pulled back to logic 0. In some embodiments, after the signal205is reset to logic 0, following the operations described above, the pJD circuit200may be configured to be ready to monitor whether a subsequent rising edge (e.g.,201r′) of the clock signal201contains an intolerable amount of jitter when comparing to a rising edge (e.g.,203r′) of the reference clock signal203. The rising edge201r′ may be received by the first delay circuit210at a subsequent time (e.g., time “t9”), and the rising edge203r′ may be received by the second delay circuit212at another subsequent time (e.g., time “t10”).

Referring now toFIG. 2B, similar to the pJD circuit200, in some embodiments, the nJD circuit250includes a first delay circuit260, a second delay circuit262, a logic gate264, transistors266,268,270,272,274,276,278, and280, inverters282and284, a logic gate286, and a tuning circuit288. The tuning circuit288is substantially similar to the tuning circuit238, which is described above with respect toFIG. 2A. Also, the first and second delay circuits260and262may each include a plurality of serially coupled buffers, inverter, or the like (not shown). The first delay circuit260is configured to receive a clock signal251and provide a delayed clock signal, e.g.,251′, and the second delay circuit262is configured to receive the reference clock signal253and provide a delayed reference clock signal, e.g.,253′. In some embodiments, the clock signal251and reference clock signal253in the illustrated embodiment ofFIG. 2Bmay correspond to the signals received at inputs108A and108B of the jitter detector108, respectively (FIG. 1). That is, the clock signal251and reference clock signal253may be the delayed clock signal101′ and delayed reference clock signal103′, respectively, that have been respectively delayed by the first delay circuit112and second delay circuit132.

Different from the pJD circuit200, in some embodiments, the logic gate264of the nJD circuit250may include a NOR logic gate that is configured to perform a NOR logic function on the clock signal251and the reference clock signal253so as to provide a control signal264′ based on a NOR′ ed result of logic states of the clock signal251and the reference clock signal253. Further, the transistors268,270, and272may be each implemented by an NMOS FET, and the transistors266,274,276,278, and280may be each implemented by a PMOS FET. However, it is noted that the transistors266to280may be each implemented by any of various types of transistors (e.g., a bipolar junction transistor (BJT), a high-electron mobility transistor (HEMT), etc.) while remaining within the scope of the present disclosure.

In some embodiments, the transistors266and268are commonly coupled to a first supply voltage257(e.g., Vss or ground) at a respective drain and source, and gated by the control signal264′. The transistor270is coupled to the transistor266's source by its respective source, and gated by the delayed clock signal251′. The transistor272is coupled to the transistor268's drain by its respective source, and gated by the delayed reference clock signal253′. And the transistor268's source is coupled to the transistor266's drain. The transistors274and276are coupled to a drain of the transistor270by their respective drains at a common node “C,” and to a second supply voltage259(e.g., Vdd) by their respective sources. In some embodiments, the transistor274is gated by the control signal264′. Similarly, the transistors278and280are coupled to a drain of the transistor272by their respective drains at a common node “D,” and to the second supply voltage259(e.g., Vdd) by their respective sources. In some embodiments, the transistor280is gated by the control signal264′.

More specifically, in some embodiments, the transistors276and278are cross-coupled to each other. That is, a gate of the transistor276is coupled to the drain of the transistor728and a gate of the transistor278is coupled to the drain of the transistor276so as to allow the transistors276and278to function as a latch circuit that is substantially similar to the latch circuit formed by the transistors226and228of the pJD circuit200.

In some embodiments, the inverters282and284are configured to receive signals present at nodes C and D (hereinafter “signal281” and “signal283”), respectively, as respective input signals, and provide respective logically inverted signals285and287. The signals285and287are received by the logic gate286, which may be similarly implemented as an XOR logic gate in some embodiments. The logic gate286is configured to perform the XOR logic function on the signals285and287so as to provide the signal255whose logic state is determined based on an XOR'ed result of logic states of the signals285and287. In some embodiments, the signal255may be the output of the jitter detector108.

FIG. 3Billustrates exemplary waveforms of signals251,253,264′,251′,253′,281,283, and255to operate the nJD circuit250ofFIG. 2B, in accordance with some embodiments. Each waveform of the signals251,253,264′,251′,253′,281,283, and255illustrated inFIG. 3Bvaries between logic 1 and logic 0 over time. It is noted that the clock signal251and reference clock signal253may respectively correspond to the delayed clock signal101′ and delayed reference clock signal103′.

Similar to the operation of the pJD circuit200, in some embodiments, the reference clock signal253may be used as the “presumably periodic signal,” and the clock signal251may be used as a to-be examined signal to determine whether a deviation of the clock signal251from the presumably periodic signal253exceeds a noise window. When the clock signal251contains jitter (i.e., the deviation) that exceeds the noise window (i.e., an intolerable amount of jitter) on its respective falling edge, the nJD circuit250may pull the signal255to logic 1. Accordingly, in order to explain how the “intolerable” jitter on the falling edge of the clock signal251is detected by the nJD circuit250, inFIG. 3B, the waveform of signal251(received by the nJD circuit250) illustrates such a scenario and how the nJD circuit250responds by using signals264′,251′,253′,281, and283to pull the signal255to logic 1.

As shown inFIG. 3B, the clock signal251's falling edge251fis deviated from the reference clock signal253's falling edge253f. More specifically, the falling edge251foccurs “ΔT” ahead of the falling edge253f. Alternative stated, the rising edges251fand253fhave a timing difference ΔT from each other. As described above, the logic gate264performs the NOR logic function on the clock signal251and the reference clock signal253. As known in the art, only when both the signals251and253transition to logic 0, the logic gate264can output the control signal264′ as logic 1.

Prior to time “t0,” the control signal264′ is at logic 0, and at time t0, the control signal264′ remains at logic 0, because the logic states of the signals251and253are at logic 1. It is noted that the transistors266,268,274, and280are all gated by the signal264′. Accordingly, when the control signal264′ is at logic 0, the “NMOS” transistor268is turned off, and the “PMOS” transistors266,274, and280are turned on. In some embodiments, the transistor266may serve as a pre-discharge circuit to pre-discharge the transistors270and272, and more specifically, the sources of the transistors270and272, before the transistors270and272are turned off, since, at time t0, the transistors270and272are turned on. The transistor268may serve as a current sink after the control signal264's is pulled to logic 1, and the transistors274and280are configured to perform a reset function after the control signal264's is pulled back to logic 0, which will be discussed below, respectively. Moreover, in some embodiments, a respective size of the transistor266may be selected to be substantially smaller than other transistors (e.g., the transistors270,272,274,276,278, and280) such that prior to time t0(e.g., before signal264′ transitions to logic 1) a stand-by current (also known as a “DC current”) may be minimized and respective logic states at nodes C and D may remain at logic 1. Thus, noise and/or false logic state(s), caused by the latch circuit formed by the transistors276and278, can be advantageously avoided.

Subsequently, at time “t1,” since both the clock signal251and the reference clock signal253have transitioned to logic 0, respectively, the (NOR) logic gate264transitions the control signal264′ to logic 1, which turns off the transistor266and turn on the transistor268such that the transistor266may stop pre-discharging the transistors270and272and the transistor268may start discharging the voltage levels at nodes C and D through the ON transistors270and272, respectively. It is noted that because of a signal propagation delay caused by the logic gate264, the control signal264′ may not transition to logic 1 immediately after both signals251and253transition to logic 0. As mentioned above, the first and second delay circuits260and262respectively delay the clock signal251and the reference clock signal253. More specifically, in some embodiments, the first delay circuit260may delay the clock signal251by a delay “ΔT1” so as to provide the delayed signal251′ as shown; and the second delay circuit262may delay the clock signal253by a delay “ΔT2” so as to provide the delayed signal253′ as shown. In some embodiments, the delays ΔT1and ΔT2may be substantially similar to each other.

At time “t2,” because of the delays, falling edges of the delayed signals251′ and253′ have not been received by the “NMOS” transistors270and272, i.e., the delayed signals251′ and253′ are still at HIGH. Thus, the transistors270and272are remained ON. And the transistor266is remained OFF and the transistor268is remained ON because the control signal264′ has been pulled to HIGH at time t1. The transistor268, served as the current sink as mentioned above, is configured to keep discharging voltage levels at nodes C and D. As such, the voltage levels at nodes A and B (i.e., the signals281and283) may be discharged to LOW through the ON transistors520and522.

At time “t3,” the falling edge of the delayed signal251′ is received by the gate of the transistor270so that the transistor270is turned off. Accordingly, the voltage level at the node C (i.e., the signal281) starts being charged through the transistor276at time t3. Similarly, at time “t4,” the falling edge of the delayed signal253′ is received by the gate of the transistor272so that the transistor272is turned off. Accordingly, the voltage level at the node D (i.e., the signal283) starts being charged through the transistor278at time t4.

In some embodiments, because of the substantially similar delays ΔT1and ΔT2, the timing difference “ΔT” between the falling edges251fand253fis reflected to the delayed signals251′ and253′ accordingly to turn off the transistors270and272at different times. The signals281and283may start being charged at different times, i.e., the times t3and t4are different and the time t4is subsequent to the time t3. As such, the signal281may transition to logic 1 faster than the signal283. Moreover, as mentioned above, the transistors276and278function as a latch circuit. That is, once either one of the signals281and283transitions to a detectable logic state (e.g., a high enough voltage level), the logic states of the signals281and283may be latched as what they currently are. In a non-limiting example, when either one of the signals281and283transitions to a high enough voltage level, the logic state of the signal that transitions to the high enough voltage level may be latched to logic 1, and the logic state of the other signal may be complementarily latched to logic 0 (i.e., stops being charged).

In the example ofFIG. 3B, since the signal281transitions to logic 1 (i.e., a high enough voltage level) at about time “t5” while the signal283is still being charged, the logic states of the signals281and283may be latched to logic 1 and logic 0, respectively. That is, the signal281is latched to logic 1 and the signal583is stopped being charged and latched to logic 0.

In an example, when the signals281and283start being charged at the same time (i.e., t3=t4) or at two substantially close times (i.e., t4is substantially close to t3), the logic states of the signals281and283become non-differentiable (i.e., both logic states of the signals281and283are at either logic 1 or logic 0), which causes the latch circuit formed by the transistors276and278to fail to latch a logic state within such a narrow timing difference between times t3and t4. Alternatively stated, when the timing difference between times t3and t4becomes smaller than the noise window, the latch circuit formed by the transistors276and278cannot latch signal281and signal283into inversed logic states (either logic 1 or logic 0).

On the other hand, which is the case shown inFIG. 3B, when the timing difference between times t3and t4exceeds the noise window, the logic states of the signals281and283are differentiable because the logic state of the signal281transitions to logic 1 first. Accordingly, the latch circuit formed by the transistors276and278can latch the logic states of the signals281and283as logic 1 and logic 0, respectively. Subsequently, the signals281and283are logically inverted through the respective inverters282and284to become the signals285(now transitioning to logic 0) and287(now transitioning to logic 1).

At time “t6,” the logic gate286performs the XOR logic function on the logically inverted signals285and287. As described above, an XOR logic gate outputs a logic 1 when inputs of the XOR logic gate are in different logic states. Accordingly, the (XOR) logic gate286transitions the signal255to logic 1 at time t6, When the signal255is pulled to logic 1, the nJD circuit250may thus determine that the deviation ΔT of the falling edge251f(of the clock signal251) from the falling edge253f(of the reference clock signal253f) exceeds the noise window, in accordance with some embodiments.

Subsequently, at time “t7,” since at least one of the clock signal251and the reference clock signal253transitioned to logic 1, the control signal264′ (NOR'ing at least one logic 1 from either the signals251or signal253) transitions to logic 0. Accordingly, the transistors274and280are turned on. As mentioned above, the transistors274and280, in some embodiments, may form a reset circuit. That is, when the transistors274and280are turned on, such a rest circuit is enabled, which starts to charge the signals281and283. In some embodiments, the signal283may be pulled back to logic 1 slightly after time t7.

At time “t8,” the signals285and287both transition to logic 0 by logically inverting the signals281and283through the inverters282and284, respectively, so that the signal255is reset to logic 0 (XOR'ing two LOW's of the signals285and287). It is noted that because of some signal propagation delays caused by the inverters282and284, respectively, the signal255may not transition to logic 0 immediately after the signals281and283are pulled back to logic 1. In some embodiments, after the signal255is reset to logic 0, following the operations described above, the nJD circuit250may be configured to be ready to monitor whether a subsequent falling edge (e.g.,251f) of the clock signal251contains an intolerable amount of jitter when comparing to a falling edge (e.g.,253f) of the reference clock signal253. The falling edge251fmay be received by the first delay circuit260at a subsequent time (e.g., time “t9”), and the falling edge253fmay be received by the second delay circuit262at another subsequent time (e.g., time “t10”).

Referring again toFIG. 1, in addition to the above-discussed Normal Monitoring Mode and Noise Window Calculation Mode, the jitter monitoring circuit100may be operated in a Built-In-Self-Test (BIST) Mode, in accordance with some embodiments. Further, the BIST Mode may be further divided to two sub-modes, a first sub-mode of the BIST Mode (hereinafter “BIST Mode1”) and a second sub-mode of the BIST Mode (hereinafter “BIST Mode2”), which will be respectively discussed as follows.

When operating in the BIST Mode1, the main control circuit146may activate one and deactivate the other of the first and second controllable buffers110and130, such that one of the clock signals101and103can be received by the jitter detector108at one of its inputs (108A or108B) through the corresponding delay circuit (112or132) and the other input of the jitter detector108may receive a signal with either the frequency X or Y. As mentioned above, the frequency X, present at the node X, and the frequency Y, present at the node Y, respectively correspond to the alternately formed oscillation loops (151and153) and (155and157), which typically contain a large amount of noise (e.g., jitter). Thus, when the jitter detector108compares these two signals (one of the delayed clock signals101′ and103′, and one of the signals with the frequency X or Y), the main control circuit146may expect the outputs provided by the jitter detector108are all logic 1's or mostly logic 1's (e.g., above a predefined percentage). However, if not (i.e., the logic 1's output by jitter detector108are less than the predefined percentage), the main control circuit146may determine that at least one of the components of the jitter monitoring circuit100is malfunctioning such as, for example, the first delay circuit112, the second delay circuit132, etc.

When operating in the BIST Mode2, the main control circuit146may short the inputs108A and108B of the jitter detector108. As such, the jitter detector108may receive only one delayed clock signal, for example, either101′ or103′. Since the jitter detector108is now comparing a same (delayed) clock signal, the main control circuit146may expect the outputs provided by the jitter detector108are all logic 0's. However, if not, the main control circuit146may determine that the jitter detector108is malfunctioning.

FIG. 5illustrates a flow chart of an exemplary method500to operate the jitter monitoring circuit100ofFIG. 1, in accordance with some embodiments. In various embodiments, the operations of the method500are performed by the respective components illustrated inFIGS. 1-4. For purposes of discussion, the following embodiment of the method500will be described in conjunction withFIGS. 1-4. The illustrated embodiment of the method500is merely an example. Therefore, it should be understood that any of a variety of operations may be omitted, re-sequenced, and/or added while remaining within the scope of the present disclosure.

The method500starts with operation502in which a first clock signal and a second clock signal are received, in accordance with various embodiments. In the above example, the first and second clock signals may be received by the jitter monitoring circuit100as the to-be examined clock signal101and the reference clock signal103.

The method500proceeds to operation504in which the first clock signal and second clock signal are respectively delayed by a first delay circuit and a second delay circuit to align the first and second clock signals within a noise window, in accordance with various embodiments. Continuing with the above example, the first delay circuit112may use a first delay code to delay the clock signal101and the second delay circuit132may use a second delay code to delay the reference clock signal103in order to cause the jitter detector108to output plural logic 0's over time, i.e., the first and second clock signals101and103are aligned within a noise window used by the jitter detector108.

In some embodiments, the first and second delay codes used by the first and second delay circuits112and132, respectively, are provided by the delay control circuit106fixing one of the first and second delay codes at a first value and sweeping available values to be the other of the first and second delay codes. As such, during operation502, a delay code window may be determined by the delay control circuit106. Such a delay code window, which is defined by a range of the swept values that can still cause the jitter detector108to output logic 0, may be used to determine the noise window used by the jitter detector108, according to some embodiments of the present disclosure.

The method500proceeds to operation506in which a first oscillation loop and a second oscillation loop are alternately formed to pass through each of the first and second delay circuits so as to determine the noise window, in accordance with various embodiments. Using the same example, the delay control circuit106may still fix one of the first and second delay codes at the first value, but use one delay code greater than an upper boundary of the delay code window or one delay code less than a lower boundary of the delay code window as the other of the first and second delay codes. Subsequently, two oscillation loops are alternatively formed by the loop control circuit104to pass through each of the first and second delay circuits112and132, which allows the first and second frequency counters122and142to calculate the frequencies X and Y so as to calculate the noise window used by the jitter detector108, as discussed above.

In an embodiment, a circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.

In another embodiment, a circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to align the first and second clock signals within a noise window; a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits; a first frequency counter, coupled to the first delay circuit, and configured to count a number of cycles of the first and second oscillation loops passing through the first delay circuit using a reference frequency; and a second frequency counter, coupled to the second delay circuit, and configured to a number of cycles of the first and second oscillation loops passing through the second delay circuit using the reference frequency, wherein the noise window is determined based on the reference frequency and a difference between the number of cycles of the first and second oscillation loops passing through the first delay circuit and the number of cycles of the first and second oscillation loops passing through the second delay circuit.

In yet another embodiment, a method includes: receiving a first clock signal and a second clock signal; delaying the first and second clock signals by a first delay circuit and a second delay circuit, respectively, to align the first and second clock signals within a noise window; and alternately forming a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits to determine the noise window.