Power converter

In a power converter, a voltage command signal shifting part shifts a first duty command signal such that a first duty center value related to a voltage applied to a first set of windings is shifted downwards than an output center value of a possible duty range. The voltage command signal shifting part also shifts a second duty command signal such that a second duty center value related to a voltage applied to a second set of windings is shifted upwards than the output center value. First and second shift amounts of the first and second duty center values from the output center value are varied depending on amplitude. Accordingly, ripple current of a capacitor can be decreased, and a difference in heat loss between switching elements can be minimized.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and incorporates herein by reference Japanese patent application No. 2010-53149 filed on Mar. 10, 2010.

FIELD OF THE INVENTION

The present invention relates to a power converter for a multiphase rotating electric machine.

BACKGROUND OF THE INVENTION

Techniques for controlling current to drive a multiphase rotating electric machine by part of pulse width modulation (PWM) have been known in the related art. For example, if the multiphase rotating electric machine is a three-phase motor, a PWM reference signal of a triangular wave or the like is compared with a voltage reference signal related to voltages applied respectively to its three-phase windings and current flowing through the three-phase motor is controlled by switching on and off switching elements of an inverter.

If the inverter is connected to a capacitor, when no current flow into the inverter, the capacitor is charged as current flows from a power supply source into the capacitor. On the other hand, when current flows into the inverter, the capacitor is discharged as current flows from the capacitor into the inverter. In PWM control, the capacitor alternates between charging and discharging during one cycle of PWM, capacitor current is pulsed. Pulsation of current flowing through the capacitor is referred to as ripple current. When the capacitor current is pulsed, noises are generated or the capacitor generates heat. In addition, fluctuation of a voltage applied to the inverter may result in poor controllability of inverter current.

For the purpose of avoiding the above problems, JP 2001-197779A discloses a technique in which a phase difference is imposed on switching timings of switching elements between two sets of bridge circuits, based on pre-stored map data, so that a waveform of summed capacitor current approaches a smooth waveform in order to decrease ripple current. In addition, JP 2007-306705A discloses a technique in which, if two axes are connected in a PWM amplifier, a voltage command for one axis is biased to Vcc/4 (Vcc being a power source voltage) while a voltage command for the other is biased to −Vcc/4 in order to decrease ripple current.

However, the technique disclosed in JP 2001-197779A requires a delay circuit since the phase difference is imposed on the switching timings based on a modulation ratio and a power factor. In addition, this technique requires detection of current in a plurality of lines at short intervals, which may result in heavy operation load of a control circuit.

In the technique disclosed in JP 2007-306705A, for example if two inverter systems are present, a voltage command is biased to a ¼ upper part of a power source voltage for one of the two inverter systems. When the command voltage is biased upwards (higher), time for which a switching element at a higher potential is in the on-state is longer than time for which a switching element at a lower potential is in the on-state. On the other hand, for the other inverter system, the voltage command is biased to a ¼ lower part of the power source voltage. When the command voltage is biased downwards (lower), time for which a switching element at a lower potential is in the on-state is longer than time for which a switching element at a higher potential is in the on-state. If an integrated value of current flowing through the switching elements at the higher potential is significantly different from an integrated value of current flowing through the switching elements at the lower potential, it may result in a difference in heat loss between the switching elements at the higher potential and the switching elements at the lower potential. Such a difference in heat loss between the switching elements at the higher potential and the switching elements at the lower potential requires a marginal thermal design or an asymmetrical heat radiation design. In addition, this difference in heat loss may require additional elements in the switching elements at the higher potential and the switching elements at the lower potential, which may result in cost-up.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a power converter, which is capable of decreasing ripple current of a capacitor while suppressing a difference in heat loss between switching elements.

A power converter for a multiphase rotating electric machine includes two sets of windings. Each set is constituted by windings corresponding to each phase of the electric machine. The power converter includes tow inverter circuits, a capacitor and a control circuit. Each of the two inverter circuits has switching elements corresponding to each phase of the sets of windings. The capacitor is connected to the inverter circuits. The control circuit controls switching-on/off of the switching elements based on voltage command signals related to voltages applied to the sets of windings and a PWM reference signal. The control circuit further includes an amplitude calculating part and a shift amount calculating part. The amplitude calculating part calculates amplitudes of the voltage command signals. The shift amount calculating part calculates a first shift amount and a second shift amount. The first shift amount indicates a shift amount of a center value of a voltage command signal related to a voltage applied to one of the sets of windings from an output center value of a possible duty range to allow the center value of the voltage command signal to be shifted downwards than the output center value. The second shift amount indicates a shift amount of a center value of a voltage command signal related to a voltage applied to the other of the sets of windings from the output center value to allow the center value of the voltage command signal to be shifted upwards from the output center value. The first shift amount and the second shift amount are varied depending on the amplitudes calculated by the amplitude calculating part.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Power converter according to exemplary embodiments will be described with reference to the accompanying drawings. In the following embodiments, the same or similar elements are denoted by the same reference numerals throughout the drawings.

First Embodiment

As shown inFIG. 1, a power converter1is provided to drive and control a motor10, which is a multiphase rotating electric machine. For example, the power converter1is applied to an electric power steering system (EPS) for assisting in steering operation of a vehicle together with the motor10.

The motor10is a three-phase brushless motor and has a rotor and a stator (both not shown). The rotor, which is a disc-like member, has a surface to which permanent magnets are attached, and has magnetic poles. The stator accommodates and rotatably supports the rotor. The stator has projections projecting inwardly in a radial direction at predetermined angle intervals, with the projections wound with a U1 coil11, a V1 coil12, a W1 coil13, a U2 coil14, a V2 coil15and a W2 coil16. The U1 coil11, the V1 coil12and the W1 coil13constitute a first set of windings18. The U2 coil14, the V2 coil15and the W2 coil16constitute a second set of windings19. The first set of windings18and the second set of windings19thus provide two sets of windings. The motor10is provided with a position sensor69, which detects a rotation position of the rotor.

The power converter1includes a first inverter circuit20, a second inverter circuit30, a current detector circuit40, a capacitor50, a control circuit60, a battery70, etc. In the first embodiment, the first inverter circuit20and the second inverter circuit30provide two inverters.

The first inverter circuit20is a three-phase inverter and includes six bridged switching elements21to26for switching electrical connection of the U1 coil11, the V1 coil12and the W1 coil13in the first set of windings18. The switching elements21to26are field effect transistors, particularly, metal-oxide-semiconductor field effect transistors (MOSFETs). The switching elements21to26are simply referred to as FETs21-26.

Three FETs21to23have their respective drain electrodes connected to a positive pole of the battery70. Source electrodes of the FETs21to23are respectively connected to drain electrodes of FETs24to26. Source electrodes of the FETs24to26are connected to a negative pole of the battery70.

A node between the FET21and FET24in pair is connected to one end of the U1 coil11. A node between the FET22and FET25in pair is connected to one end of the V1 coil12. A node between the FET23and FET26in pair is connected to one end of the W1 coil13.

Like the first inverter circuit20, the second inverter circuit30is a three-phase inverter and includes six bridged switching elements31to36for switching electrical connection of the U2 coil14, the V2 coil15and the W2 coil16in the second set of windings19. Like the switching elements21to26, the switching elements31to36are FETs. The switching elements31to36are simply referred to as FETs31-36.

Three FETs31to33have their respective drain electrodes connected to the positive pole of the battery70. Source electrodes of the FETs31to33are respectively connected to drain electrodes of FETs34to36. Source electrodes of the FETs34to36are connected to the negative pole of the battery70.

A node between the FET31and FET34in pair is connected to one end of the U2 coil14. A node between the FET32and FET35in pair is connected to one end of the V2 coil15. A node between the FET33and FET36in pair is connected to one end of the W2 coil16.

The FETs21to23and the FETs31to33, which are switching elements at a higher potential side, are referred to as high-side FETs. The FETs24to26and the FETs34to36, which are switching elements at a lower potential side, are referred to as low-side FETs. As necessary, a phase and an inverter circuit corresponding to a state termed U1 high-side FET21will be described together.

The current detector circuit40includes a U1 current detector41, a V1 current detector42, a W1 current detector43, a U2 current detector44, a V2 current detector45and a W2 current detector46. The U1 current detector41is interposed between the node between the FET21and FET24and the U1 coil11and detects current flowing through the U1 coil11. The V1 current detector42is interposed between the node between the FET22and FET25and the V1 coil12and detects current flowing through the V1 coil12. The W1 current detector43is interposed between the node between the FET23and FET26and the W1 coil13and detects current flowing through the W1 coil13. The U2 current detector44is interposed between the node between the FET31and FET34and the U2 coil14and detects current flowing through the U2 coil14. The V2 current detector45is interposed between the node between the FET32and FET35and the V2 coil15and detects current flowing through the V2 coil15. The W2 current detector46is interposed between the node between the FET33and FET36and the W2 coil16and detects current flowing through the W2 coil16.

Each of the current detectors41to46is to detect a magnetic flux using a Hall element. A detected value of current detected by each of current detector41to46is analog-to-digital converted (AD value) and stored in a register constituting the control circuit60. AD values are simultaneously acquired by the register from the current detectors41to46. At the same time, a rotation position θ of the motor10detected by the position sensor69is acquired. InFIG. 1, control lines from the current detector circuit40and the position sensor69to the control circuit60are omitted for the purpose of simplicity and clarity.

The capacitor50is connected in parallel to the battery70, the first inverter circuit20and the second inverter circuit30and accumulates electric charges to assist in supply of electric power to the FETs21to26and31to36or suppresses noise components such as surge current and the like.

The control circuit60is configured to control the power converter1and includes a microcomputer67, registers (not shown), a driver circuit68and so on. Details of the control circuit60are shown inFIGS. 2 and 3. As shown inFIG. 2, the control circuit60includes a three-phase to two-phase converter (3/2 converter)62, a controller63, a two-phase to three-phase converter (2/3 converter)64, a duty calculator65, a triangular wave comparator66and so on.

A control process of the control circuit60will be described briefly with reference toFIGS. 2 and 3. In the following description, it is assumed that phase duties of a first duty command signal D11and a second duty command signal D12, which will be described later, are Du, Dv and Dw.

The three-phase to two-phase converter62reads AD values, which are detected by the current detectors41to43and stored in the registers, and calculates a current value Iu of the U1 coil11, a current value Iv of the V1 coil12and a current value Iw of the W1 coil13based on the read AD values. In addition, the three-phase to two-phase converter62calculates a d-axis current detected value Id and a q-axis current detected value Iq based on the calculated three-phase current values Iu, Iv and Iw and the rotation position θ of the motor10detected by the position sensor69.

The controller63performs a current feedback control operation to calculate a d-axis command voltage value Vd* and a q-axis command voltage value Vq* from a d-axis command current value Id* and a q-axis command current value Iq* and the d-axis current detected value Id and the q-axis current detected value Iq. More specifically, the controller63calculates a current deviation ΔId between the d-axis command current value Id* and the d-axis current detected value Id and a current deviation ΔIq between the q-axis command current value Iq* and the q-axis current detected value Iq and calculates the command voltages Vd* and Vq* to converge the current deviations ΔId and ΔIq to zero in order to follow the command current values Id* and Iq*.

The two-phase to three-phase converter64calculates three-phase command voltage values Vu*, Vv* and Vw* based on the command voltages Vd* and Vq* calculated by the controller63and the rotation position θ of the motor10.

In the duty calculator65, which is shown inFIG. 3, an amplitude calculator651calculates an amplitude of a command voltage and a shift amount calculator652calculates the amount of shift of the three-phase command voltage values based on the command voltage amplitude calculated by the amplitude calculator651. The duty calculator65calculates a U-phase duty Du, a V-phase duty Dv and a W-phase duty Dw based on the three-phase command voltage values Vu*, Vv* and Vw*, the shift amount calculated by the shift amount calculator652and a capacitor voltage Vc, and then stores the calculated phase duties Du, Dv and Dw into registers. In addition, for the calculation of the phase duties Du, Dv and Dw, after converting the three-phase command voltage values Vu*, Vv* and Vw* into duties, the shift amount may be calculated or a neutral point voltage operation by a modulation process, which will be described later, may be performed, or after performing a neutral point voltage operation, the three-phase command voltage values Vu*, Vv* and Vw* may be converted into duties.

The triangular wave comparator66outputs on/off signals of the FETs21to26and31to36by comparing the PWM reference signal, which is a carrier signal of a triangular wave, with the phase duty signals (phase duties) Du, Dv and Dw. In this embodiment, the process of the triangular wave comparator66is performed in an electrical circuit within the microcomputer67. This process may be performed by either software or hardware.

The amplitude calculator651corresponds to an amplitude calculating part and the shift amount calculator652corresponds to a shift amount calculating part. The three-phase command voltage values Vu*, Vv* and Vw* and phase duties Du, Dv and Dw calculated from three-phase command voltage values Vu*, Vv* and Vw* correspond to voltage command signals. In the following description, explanation about the conversion process of three-phase command voltage values Vu*, Vv* and Vw* into the phase duties Du, Dv and Dw will be omitted and the phase duties Du, Dv and Dw will be mainly described.

The first duty command signal D11to drive the first inverter circuit20includes three sinusoidal wave signals; a U-phase duty Du11regarding a voltage applied to the U1 coil11, a V-phase duty Dv11regarding a voltage applied to the V1 coil12and a W-phase duty Dw11regarding a voltage applied to the W1 coil13. The second duty command signal D12to drive the second inverter circuit30includes three sinusoidal wave signals; a U-phase duty Du12regarding a voltage applied to the U2 coil14, a V-phase duty Dv12regarding a voltage applied to the V2 coil15and a W-phase duty Dw12regarding a voltage applied to the W2 coil16(seeFIGS. 8A,8B andFIGS. 10A to 10C, etc.).

Subsequently, PWM control will be described with an example where no neutral point voltage operation is performed in the first inverter circuit20.

As shown inFIG. 4A, the PWM reference signal P is compared with the phase duties Du11, Dv11and Dw11to generate on/off signals of the FETs21to26. In this embodiment, the high-side FETs21to23are in the off-state and the corresponding low-side FETs24to26are in the on-state in an interval where the PWM reference signal P is above (higher than) the phase duties Du11, Dv11and Dw11. The high-side FETs21to23are in the on-state and the corresponding low-side FETs24to26are in the off-state in an interval where the PWM reference signal P is below (lower than) the phase duties Du11, Dv11and Dw11. That is, the high-side FETs21to23and low-side FETs24to26in pair have a reverse on/off relationship.

More specifically, for example in an interval K1, the PWM reference signal P is located below the U-phase duty Du11indicated by a solid line and is located above the V-phase duty Dv11indicated by a dashed line and the W-phase duty Dw11indicated by an alternate long and short dash line. Accordingly, for the U phase, the high-side FET21is in the on-state and the low-side FET24is in the off-state. For the V phase and the W phase, the high-side FETs22and23are in the off-state and the low-side FETs25and26are in the on-state.

A voltage vector pattern is a pattern indicating any three FETs, which are in the on-state, of six FETs21to26.FIG. 5shows voltage vector patterns V0to V7. Specifically the low-side FETs24to26are all turned on for the voltage vector V0. The high-side FETs21to23are all turned on for the voltage vector V7. Accordingly, the voltage vectors V0and V7are zero voltage vectors, for which no voltage is applied to the first set of windings18. On the other hand, the voltage vectors V1to V6are effective (valid) voltage vectors, for which a voltage is applied to the first set of windings18.

The first duty command signal D11for current flowing through the capacitor50while PWM control is being performed will be described by way of example with reference toFIGS. 6,7A and7B. The current detector circuit40, the second inverter circuit30and so on are excluded from the circuit diagrams shown inFIGS. 7A and 7Bfor simplicity.

As shown in (a) to (c) ofFIG. 6, when the PWM reference signal P is above the phase duties Du11, Dv11and Dw11, the corresponding high-side FETs (H-FETs)21to23are in the off-state and the corresponding low-side FETs24to26are in the on-state. When the PWM reference signal P is below the phase duties Du11, Dv11and DMA, the corresponding high-side FETs21to23are in the on-state and the corresponding low-side FETs24to26are in the off-state.

In a zero voltage vector where all of the high-side FETs21to23or all of the low-side FETs24to26are turned on, current flows from the battery70into the capacitor50, which is thus charged. For example, as shown inFIG. 7A, when the low-side FETs24to26are in the on-state, the current from the battery70does not flow into the first inverter circuit20and regenerative current Ir flows into the first set of windings18. In addition, the current from the battery70flows as charging current into the capacitor50, which is thus charged, as indicated by a symbol Ic.

In an effective voltage vector where one or two of the high-side FETs21to23are in the on-state, current flows into the first inverter circuit20from the capacitor50, which is thus discharged. For example, as shown inFIG. 76, when the high-side FET21and the low-side FETs25and26are in the on-state, the current from the battery70flows into the first inverter circuit20. In addition, as indicated by a symbol If, discharge current flows into the first inverter circuit20from the capacitor50which is then discharged.

Returning toFIG. 6where reference is made to a relationship between the PWM reference signal P, the first duty command signal D11and a charging state (C) and a discharging state (D) of the capacitor50, the capacitor50is charged in an interval where the PWM reference signal P is above or below the first duty command signals D11of all phases. On the other hand, the capacitor50is discharged in an interval where the PWM reference signal P is in the first duty command signal D11. In the example shown inFIG. 6, the capacitor50is charged when the PWM reference signal P lies in a valley side or a mountain side, and the capacitor50is discharged when the PWM reference signal P lies therebetween. Accordingly, as shown in (d) ofFIG. 6, the capacitor50alternates between charging (C) and discharging (D) in one cycle of PWM. This pulsates capacitor current, as shown in (e) ofFIG. 6.

In the first embodiment, ripple current of the capacitor50is decreased by shifting the first duty command signal D11regarding the voltage applied to the first set of windings18downwards (lower) from the center of possible duty range, which can be outputted, and shifting the second duty command signal D12regarding the voltage applied to the second set of windings19upwards (higher) from the center of possible duty range, depending on the amplitude of the voltage command signal. The first duty command signal D11corresponds to a lower-shifted voltage command signal and the second duty command signal D12corresponds to a higher-shifted voltage command signal.

Capacitor current provided when the duty command signals D11and D12are respectively shifted upwards and downwards from an output center value Rc(not shown inFIGS. 8A and 813, seeFIGS. 10A to 10C) of an possible duty range will be described with reference toFIGS. 8A and 8B.FIG. 8Ashows that the first duty command signal D11is shifted downwards andFIG. 8Bshows that the capacitor current obtained when the second duty command signal D12is shifted upwards.

As shown inFIG. 8A, when the first duty command signal D11is shifted downwards, charging time of the capacitor50at the mountain side of the PWM reference signal P is relatively long and discharging time of the capacitor50is biased to the valley side of the one PWM cycle. On the other hand, as shown inFIG. 8B, when the second duty command signal D12is shifted upwards, charging time of the capacitor50at the mountain side of the PWM reference signal P is relatively short and discharging time of the capacitor50is relatively biased to the center of the one PWM cycle. The charging time at the valley side of the PWM reference signal is relatively long.

That is, when the duty command signal is shifted downwards and upwards, a generation timing of the effective voltage vector is different from that of the zero voltage vector. Accordingly, if the PWM reference signal P has no phase difference, ripple current of the capacitor50can be decreased by shifting the first duty command signal D11downwards and shifting the second duty command signal D12upwards. In addition, when amplitudes of the duty command signals D11and D12are small, if the first duty command signal D11and the second duty command signal D12are shifted without being overlapped, the capacitor50is charged in one inverter circuit while being discharged in the other inverter circuit.

In addition, even when the duty command signals D11and D12are shifted upwards and downwards from the center of the possible duty range, if a line voltage is not changed, the voltages applied to the sets of windings18and19are not changed.

However, if the center values of the duty command signals D11and D12are deviated from the output center value Rc, time for which the high-side FETs are in the on-state is different from time for which the low-side FETs are in the on-state.

As shown inFIG. 9A, when the first duty command signal D11is shifted downwards, time for which the W1 low-side FET26is in the on-state is longer than time for which the W1 high-side FET23is in the on-state. This is equally applied to the U1 low-side FET24and U1 high-side FET21, and the V1 low-side FET25and V1 high-side FET22.

On the other hand, as shown inFIG. 98when the second duty command signal D12is shifted upwards, time for which the U2 high-side FET31is in the on-state is longer than time for which the U2 low-side FET34is in the on-state. This is equally applied to the V2 high-side FET32and V2 low-side FET35, and the W2 high-side FET33and W2 low-side FET36.

As the shift amount from the center of the possible duty range increases, a difference between the time for which the high-side FETs are in the on-state and the time for which the low-side FETs are in the on-state increases. Since an integrating current amount is changed if the time for which the high-side FETs are in the on-state is different from the time for which the paired low-side FETs are in the on-state, heat loss in the high-side FETs is different from heat loss in the low-side FETs.

In this embodiment, the ripple current of the capacitor50is decreased by shifting the first duty command signal D11downwards and shifting the second duty command signal D12upwards. In addition, a difference in heat loss between the FETs is suppressed to be small by varying the shift amounts of the first duty command signal D11and the second duty command signal D12depending on their amplitudes.

A voltage command signal is shifted as shown inFIGS. 10A,10B and10C.

In the first embodiment, the possible duty range is 0% to 100% of a power source voltage and the output center value Rcof the possible duty range is 50% of the power source voltage. In addition, a voltage of the battery70is 12 V, the possible duty range is 0V to 12V in terms of a voltage, and the output center value R, corresponds to 6V. In addition, a frequency of the PWM reference signal P is 20 kHz. A PWM reference signal related to driving of the first inverter circuit20and a PWM reference signal P related to driving of the second inverter circuit30are the same triangular wave signals or triangular wave signals having the same phase. In addition, the first duty command signal D11has the same amplitude as the second duty command signal D12.

As shown inFIG. 10A, if the amplitude of the first duty command signal D11is equal to or less than 25% of the possible duty range, that is, if the minimum value Dmin11of the first duty command signal D11when a first duty center value Dc11of the first duty command signal D11is shifted downwards such that the maximum value Dmax11of the first duty command signal D11corresponds to the output center value Rcis equal to or more than the lower limit Rminof the possible duty range, the first duty center value Dc11of the first duty command signal D11is shifted downwards from the output center value Rcsuch that the maximum value Dmax11corresponds to the output center value Rc.

On the other hand, if the amplitude of the second duty command signal D12is equal to or less than 25% of the possible duty range, that is, if the maximum value Dmax12of the second duty command signal D12when a second duty center value Dc12of the second duty command signal D12is shifted upwards such that the minimum value Dmin12of the second duty command signal D12corresponds to the output center value Rcis equal to or less than the upper limit Rmaxof the possible duty range, the second duty center value Dc12of the second duty command signal D12is shifted upwards from the output center value Rcsuch that the minimum value Dmin12corresponds to the output center value Rc.

As shown inFIG. 10B, if the amplitude of each of the first duty command signal D11and second duty command signal D12is 25% of the possible duty range, when the first duty center value Dc11is shifted downwards such that the maximum value Dmax11of the first duty command signal D11corresponds to the output center value K, the minimum value Dmin11of the first duty command signal D11corresponds to the lower limit Rminof the possible duty range. At this time, the first duty center value Dc11is shifted downwards by 25% of the possible duty range with respect to the output center value K. That is, the first duty center value Dc11at this point is Rc−25=25%.

In addition, when the second duty center value Dc12is shifted upwards such that the minimum value Dmin12of the second duty command signal D12corresponds to the output center value K, the maximum value Dmax12of the second duty command signal D12corresponds to the upper limit Rmaxof the possible duty range. At this time, the second duty center value Dc12is shifted upwards by 25% of the possible duty range with respect to the output center value Rc. That is, the second duty center value Dc12at this point is Rc+25=75%.

As shown inFIG. 10C, if the amplitude of the first duty command signal D11is more than 25% of the possible duty range, when the first duty center value Dc11is shifted downwards such that the maximum value Dmax11of the first duty command signal D11corresponds to the output center value K, the minimum value Dmin11of the first duty command signal D11is smaller than the lower limit Rminof the possible duty range. If the first duty command signal D11is beyond the possible duty range, an output voltage is distorted. Accordingly, if the amplitude of the first duty command signal D11is more than 25% of the possible duty range, that is, if the minimum value Dmin11of the first duty command signal D11when the center value Dc11of the first duty command signal D11is shifted such that the maximum value Dmax11of the first duty command signal D11corresponds to the output center value Rcis smaller than the lower limit Rminof the possible duty range, the first duty center value Dc11is shifted such that the minimum value Dmin11of the first duty command signal D11corresponds to the lower limit Rmin, of the possible duty range.

In addition, if the amplitude of the second duty command signal D12is more than 25% of the possible duty range, when the second duty center value Dc12is shifted upwards such that the minimum value Dmin12of the second duty command signal D12corresponds to the output center value Rc, the maximum value Dmax12of the second duty command signal D12is larger than the upper limit Rmaxof the possible duty range. If the second duty command signal D12is beyond the possible duty range, an output voltage is distorted. Accordingly, if the amplitude of the second duty command signal D12is more than 25% of the possible duty range, that is, if the maximum value Dmax12of the second duty command signal D12when the center value Dc12of the second duty command signal D12is shifted such that the minimum value Dmin12of the second duty command signal D12corresponds to the output center value Rcis larger than the upper limit Rmaxof the possible duty range, the second duty center value Dc12is shifted such that the maximum value Dmax12of the second duty command signal D12corresponds to the upper limit Rmaxof the possible duty range.

If the amplitude of the first duty command signal D11is equal to or less than 25% of the possible duty range, the first duty center value Dc11is shifted downwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the first duty command signal D11is more than 25% of the possible duty range, the first duty center value Dc11is shifted in a direction to be close to the output center value Rcfrom the first duty center value Dc11when the amplitude of the first duty command signal D11is 25% of the possible duty rage as the amplitude increases.

If the amplitude of the second duty command signal D12is equal to or less than 25% of the possible duty range, the second duty center value Dc12is shifted upwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the second duty command signal D12is more than 25% of the possible duty range, the second duty center value Dc12is shifted in a direction to be close to the output center value Rcfrom the second duty center value Dc12when the amplitude of the second duty command signal D12is 25% of the possible duty range as the amplitude increases.

That is, in the first embodiment, the shift amount (denoted by a symbol “M11” inFIGS. 10A to 10C) of the first duty center value Dc11and the shift amount (denoted by a symbol “M12” inFIGS. 10A to 10C) of the second duty center value Dc12can be varied depending on the amplitude of each of the duty command signals D11and D12. This configuration is particularly effective when the amplitude of each of the duty command signals D11and D12is equal to or smaller than 25% of the possible duty range.

Here, it is assumed that the amplitude of each of the duty command signals D11and012is 12.5% and a frequency of the PWM reference signal P is 20 kHz.

The first duty center value Dc11of the first duty command signal D11having the amplitude of 12.5% is shifted downwards from the output center value Rcby 12.5% such that the maximum value Dmax11corresponds to the output center value Rc. In addition, the second duty center value Dc12of the second duty command signal D12having the amplitude of 12.5% is shifted upwards from the output center value Rcby 12.5% such that the minimum value Dmin12corresponds to the output center value Rc.

Here, current flowing through the U1 coil11is shown inFIGS. 11A to 11Dand current flowing through the U2 coil14is shown inFIGS. 12A to 12D.

As shown inFIG. 11A, according to the PWM control based on the first duty command signal D11and the PWM reference signal P, current Iu1flowing through the U1 coil11may have substantially a sinusoidal wave. In addition, since a line voltage is not changed even when the first duty command signal D11is shifted from the output center value k, the current flowing through the U1 coil11corresponds substantially to U-phase current when a duty command signal is not shifted as illustrated in a first reference example shown inFIG. 26A.

Details of an area denoted by a symbol E1inFIG. 11Ais shown inFIGS. 11B to 11D. The sinusoidal U-phase current shown inFIG. 11Ais created from a continuous rectangular wave as shown inFIG. 11B. The rectangular wave shown inFIG. 116is a combination of current flowing through the U1 low-side FET (L-FET)24as shown inFIG. 11C, and current flowing through the U1 high-side FET (H-FET)21as shown inFIG. 11D.

In the first embodiment, since the first duty command signal D11is shifted downwards, in the first inverter circuit20, the low-side FETs24to26have longer electrical conduction times and larger integrated current values than those of the high-side FETs21to23. Specifically, for one cycle of electrical angle, an integrated current value of the U1 high-side FET21is 293.5 mA·sec and an integrated current value of the U1 low-side FET24is 484.7 mA·sec. In addition, an integrated current value of the V1 high-side FET22and an integrated current value of the W1 high-side FET23are about equal to the integrated current value of the U1 high-side FET21and an integrated current value of the V1 low-side FET25and an integrated current value of the W1 low-side FET26are about equal to the integrated current value of the U1 low-side FET24.

As shown inFIG. 12A, according to the PWM control based on the second duty command signal D12and the PWM reference signal P, current flowing through the U2 coil14have substantially a sinusoidal wave. In addition, since a line voltage is not changed even when the second duty command signal D12is shifted from the output center value Rc, the current flowing through the U2 coil14corresponds substantially to U-phase current when the duty command signal is not shifted as illustrated inFIG. 26A.

Details of an area denoted by a symbol E2inFIG. 12Ais shown inFIG. 126. Current flowing through the U2 low-side FET34is shown inFIG. 12C, and current flowing through the U2 high-side FET31is shown inFIG. 12D.

In the first embodiment, since the second duty command signal D12is shifted upwards, in the second inverter circuit30, the high-side FETs31to33have longer electrical conduction times and larger integrated current values than those of the low-side FETs34to36. Specifically, for one cycle of electrical angle, an integrated current value of the U2 high-side FET31is 485.2 mA·sec and an integrated current value of the U2 low-side FET34is 293.1 mA·sec. In addition, an integrated current value of the V2 high-side FET32and an integrated current value of the W2 high-side FET33are about equal to the integrated current value of the U2 high-side FET31and an integrated current value of the V2 low-side FET35and an integrated current value of the W2 low-side FET36are about equal to the integrated current value of the U2 low-side FET34.

Here, U-phase current in reference examples will be described with reference toFIGS. 26A to 26d,FIGS. 27A to 27dandFIGS. 28A to 28D.

A first reference example shown inFIG. 26Aindicates U-phase current when a first duty center value and a second duty center value are not shifted from an output center value. In the first reference example, since a first duty command signal is the same as a second duty command signal, the first inverter circuit20to be driven and controlled by the first duty command signal will be described.

According to PWM control based on the first duty command signal and the PWM reference signal, current flowing through the U1 coil11has a sinusoidal wave as shown inFIG. 26A. Details of an area denoted by a symbol E3inFIG. 26Ais shown inFIG. 26B. Current flowing through the U1 low-side FET24is shown inFIG. 26C, and current flowing through the U1 high-side FET21is shown inFIG. 26D.

In the first reference example, since the duty command signal is not shifted, as shown inFIGS. 26B to 26D, the high-side FETs21to23have substantially the same electrical conduction times and integrated current values as the low-side FETs24to26. Specifically, for one cycle of electrical angle, an integrated value of current flowing through the U1 high-side FET21and an integrated value of current flowing through the U1 low-side FET24is both 389.0 mA·sec. In this example, since the first duty center value is not shifted from the output center value, an integrated value of current flowing through the high-side FETs21to23is about equal to an integrated value of current flowing through the low-side FETs24to26. Heat loss in the high-side FETs21to23is not different from heat loss in the low-side FETs24to26. Likewise, since the second duty center value is not shifted from the output center value, an integrated value of current flowing through the high-side FETs31to33is about equal to an integrated value of current flowing through the low-side FETs34to36. Heat loss in the high-side FETs31to33is not different from heat loss in the low-side FETs34to36.

The first duty center value and the second duty center value are not shifted from the output center value R. Accordingly, generation timings of an effective voltage vector and a zero voltage vector in the first inverter circuit20coincide with those in the second inverter circuit30, which results in no decrease of ripple current of the capacitor50.

Next, a second reference example is shown inFIGS. 27A to 27DandFIGS. 28A to 28D.FIGS. 27A to 27Dshow U phase current of a case where the first duty command signal is shifted downwards from the output center value by 25% (−25% shift) of the possible duty range.FIGS. 28A to 28Dshow U phase current of a case where the second duty command signal D12is shifted upwards from the output center value by 25% (+25% shift) of the possible duty range.

In the second reference example, since the first duty command signal is shifted downwards from the output center value and the second duty command signal is shifted upwards from the output center value, generation timings of an effective voltage vector and a zero voltage vector in the first inverter circuit20are deviated from those in the second inverter circuit30, which results in decrease of ripple current of the capacitor.

As shown inFIGS. 27A and 28A, since a line voltage is not changed even when the duty command signal is shifted from the output center value, the current flowing through the U1 coil11and U2 coil14corresponds substantially to U-phase current when the duty command signal is not shifted as shown inFIG. 26A.

Details of an area denoted by a symbol E4inFIG. 27Ais shown inFIG. 27B. Current flowing through the U1 low-side FET24is shown inFIG. 27C, and current flowing through the U1 high-side FET21is shown inFIG. 27D.

In the second reference example, since the first duty command signal D11is shifted downwards by 25%, as shown inFIGS. 27B to 27D, electrical conduction time of the U1 low-side FET24is longer than that of the U1 high-side FET21and thus an integrated current value of the U1 low-side FET24is larger than that of the U1 high-side FET21. More specifically, for one cycle of electrical angle, an integrated value of current flowing through the U1 low-side FET24is 583.5 mA·sec and an integrated value of current flowing through the U1 high-side FET21is 194.9 mA·sec. In this example, since the shift amount of the first duty center value from the output center value is large, being −25%, an integrated value of current flowing through the U1 high-side FETs21to23is greatly different from an integrated value of current flowing through the U1 low-side FETs24to26. Accordingly, heat loss in the high-side FETs21to23is different from heat loss in the low-side FETs24to26.

Details of an area denoted by a symbol E5inFIG. 28Ais shown inFIG. 28B. Current flowing through the U2 low-side FET34is shown inFIG. 28C, and current flowing through the U2 high-side FET31is shown inFIG. 28D.

As shown inFIGS. 28B to 28D, electrical conduction time of the U2 high-side FET31is longer than that of the U2 low-side FET34and thus an integrated current value of the U2 high-side FET31is larger than that of the U2 low-side FET34. More specifically, for one cycle of electrical angle, an integrated value of current flowing through the U2 high-side FET31is 583.9 mA·sec and an integrated value of current flowing through the U2 low-side FET34is 194.9 mA·sec. In this example, since the shift amount of the second duty center value from the output center value is large, being +25%, an integrated value of current flowing through the high-side FETs31to33is greatly different from an integrated value of current flowing through the low-side FETs34to36. Accordingly, heat loss in the high-side FETs31to33is greatly different from heat loss in the low-side FETs34to36.

On the other hand, in the first embodiment, as shown inFIGS. 10A to 10D,FIGS. 11A to 11DandFIGS. 12A to 12D, the shift amounts of the duty command signals D11and D12are varied depending on their amplitudes. That is, when the amplitude of each of the duty command signals D11and D12is small, the shift amount is set to be small. Accordingly, ripple current of the capacitor50is decreased and a heat loss difference is suppressed to be small by suppressing a difference in integrated current value between the FETs21to26and between the FETs31to36to be small, as compared to the second reference example.

As described in detail above, on/off switching of the FETs21to26and the FETs31to36is controlled based on the duty command signals D11and D12regarding the voltages applied to the sets of windings18and19and the PWM reference signal P. The shift amount M11of the first duty center value Dc11from the output center value Rcis calculated such that the center value Dc11of the first duty command signal D11regarding the voltage applied to the first set of windings18lies in the lower part of the output center value Rcof the possible duty range. In addition, the shift amount M12of the second duty center value Dc12from the output center value Rcis calculated such that the center value Dc12of the second duty command signal D12regarding the voltage applied to the second set of windings19lies in the upper part of the output center value Rc. The first shift amount M11and the second shift amount M12vary in response to the amplitude.

In this embodiment, since the first duty command signal D11is shifted downwards and the second duty command signal D12is shifted upwards, charging and discharging timings of the capacitor50in the first inverter circuit20and charging and discharging timings of the capacitor50in the second inverter circuit30can be delayed to thereby decrease ripple current of the capacitor50. In addition, in the first embodiment, the ripple current of the capacitor50can be decreased without providing a phase difference to the PWM reference signal regarding driving of the two inverter circuits20and30. This results in reduction of a load of the control circuit60.

In addition, since the first shift amount M11and the second shift amount M12are varied depending on the amplitude, ripple current of the capacitor50is decreased and a heat loss difference is suppressed to be small by suppressing a difference in on/off time between the high-side FETs21to23and the low-side FETs24to26and between the high-side FETs31to33and the low-side FETs34to36to be small.

In the first embodiment, the first shift amount M11is calculated such that the maximum value Dmax11of the first duty command signal D11corresponds to the output center value Rc. In addition, the second shift amount M12is calculated such that the minimum value Dmin12of the second duty command signal D12corresponds to the output center value Rc. Smaller shift amounts M11and M12of the center values Dc11and Dc12of the duty command signals D11and D12from the output center value Rcprovide a smaller difference in on-time and off-time and a smaller difference in heat loss between the high-side FETs21to23and the low-side FETs24to26and between the high-side FETs31to33and the low-side FETs34to36. In the first embodiment, although the first duty command signal D11is shifted downwards and the second duty command signal D12is shifted upwards in order to decrease ripple current of the capacitor50, the shift amounts M11and M12of the duty command signals are determined depending on their amplitude such that the duty command signals D11and D12are collected on the output center value Rc. This allows a difference in on time between the high-side FETs21to23and the low-side FETs24to26and between the high-side FETs31to33and the low-side FETs34to36to be as small as possible. This results in a smaller heat loss difference.

If the minimum value Dmin11of the first duty command signal when the maximum value Dmax11of the first duty command signal D11is set to the output center value Rcis smaller than the lower limit Rminof the possible duty range, the first shift amount M11is calculated such that the minimum value Dmin11of the first duty command signal D11corresponds to the lower limit Rminof the possible duty range. In addition, if the maximum value Dmax12of the second duty command signal D12when the minimum value Dmm12of the second duty command signal D12is set to the output center value Rcis larger than the upper limit Rmaxof the possible duty range, the second shift amount M12is calculated such that the maximum value Dmax12of the second duty command signal D12corresponds to the upper limit Rmaxof the possible duty range. This can prevent an output voltage from being distorted.

In the first embodiment, the output center value Rcis set to 50%. Accordingly, a switching timing to switch on/off the FETs21to26and31to36in the inverter circuits20and30is uniform. This results in reduction of an operational load of the control circuit60. In addition, the first and second duty command signals D11and D12are sinusoidal wave signals to facilitate PWM control.

Second Embodiment

A second embodiment of the present invention is shown inFIGS. 13,14A,14B and15A to15C.

As shown inFIG. 13, the duty calculator65includes a modulator653in addition to the amplitude calculator651and the shift amount calculator652. The modulator653performs a modulation process to modulate a waveform of a reference sinusoidal wave. The modulator653corresponds to a modulation part.

In the second embodiment, an over-duty correction process shown inFIGS. 14A and 14Bis performed as the modulation process in the modulator653. In the over-duty correction process, for a reference sinusoidal wave shown inFIG. 14A, subtraction is made from all phases by an amount exceeding the reference maximum value Smaxand the reference minimum value Smin. This results in a waveform shown inFIG. 14Bafter over-duty correction. In addition, in the second embodiment, the amplitude of the reference sinusoidal wave before the correction is 1.154 (=2/√3) times as large as an amplitude of a duty command signal after the correction.

In addition, a value calculated by dividing a subtraction value calculated by subtracting the minimum value of the duty command signal after modulation from the maximum value thereof by 2 is referred to amplitude of duty command signal. In addition, a voltage command signal after modulation is simply referred to as a duty command signal. The following description will be given based on the duty command signal like the first embodiment. This is equally applied to the subsequent embodiments.

In the second embodiment, like the first embodiment, ripple current of the capacitor50is decreased by shifting a first duty command signal D21downwards and shifting a second duty command signal D22upwards. In addition, a difference in heat loss between FETs is suppressed to be smaller by varying the shift amounts of the first duty command signal D21and second duty command signal D22depending on their amplitudes.

Specifically, as shown inFIG. 15A, if the amplitude of the first duty command signal D21is equal to or less than 25% of the possible duty range, that is, if the minimum value Dmin21of the first duty command signal D21when a first duty center value Dc21is shifted such that the maximum value Dmax21of the first duty command signal D21corresponds to the output center value Rcis equal to or more than the lower limit Rminof the possible duty range, the first duty center value Dc21is shifted downwards such that the maximum value Dmax21of the first duty command signal D21corresponds to the output center value Rc. On the other hand, if the amplitude of the second duty command signal D22is equal to or less than 25% of the possible duty range, that is, if the maximum value Dmax22of the second duty command signal D22when a second duty center value Dc22is shifted such that the minimum value Dmin22of the second duty command signal D22corresponds to the output center value Rcis equal to or less than the upper limit Rmaxof the possible duty range, the second duty center value Dc22is shifted upwards such that the minimum value Dmin22of the second duty command signal D22corresponds to the output center value Rc.

As shown inFIG. 15B, if the amplitude of the first duty command signal D21is 25% of the possible duty range, when the first duty center value Dc21is shifted such that the maximum value Dmax21of the first duty command signal D21corresponds to the output center value Rc, the minimum value Dmin21of the first duty command signal D21corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D22is 25% of the possible duty range, when the second duty center value Dc22is shifted such that the minimum value Dmin22of the second duty command signal D22corresponds to the output center value Rc, the maximum value Dmax22of the second duty command signal D22corresponds to the upper limit Rmaxof the possible duty range.

As shown inFIG. 15C, if the amplitude of the first duty command signal D21is more than 25% of the possible duty range, that is, if the maximum value Dmax21of the first duty command signal D21when the first duty center value Dc21is shifted such that the maximum value Dmax21of the first duty command signal D21corresponds to the output center value Rcis less than the lower limit Rminof the possible duty range, the first duty center value Dc21is shifted such that the minimum value Dmin21of the first duty command signal D21corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D22is more than 25% of the possible duty range, that is, if the maximum value Dmax22of the second duty command signal D22when the second duty center value Dc22is shifted such that the minimum value Dmin22of the second duty command signal D22corresponds to the output center value Rcis more than the upper limit Rmaxof the possible duty range, the second duty center value Dc22is shifted such that the maximum value Dmax22of the second duty command signal D22corresponds to the upper limit Rmaxof the possible duty range.

That is, if the amplitude of the first duty command signal D21is equal to or less than 25% of the possible duty range, the first duty center value Dc21is shifted downwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the first duty command signal D21is more than 25% of the possible duty range, the first duty center value Dc21is shifted in a direction to be close to the output center value Rc.

In addition, if the amplitude of the second duty command signal D22is equal to or less than 25% of the possible duty range, the second duty center value Dc22is shifted upwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the second duty command signal D22is larger than 25% of the possible duty range, the second duty center value Dc22is shifted in a direction to be close to the output center value Rcas the amplitude increases.

That is, in this embodiment, the shift amount M21of the first duty center value Dc21from the output center value Rcand the shift amount M22of the second duty center value Dc22from the output center value Rccan be varied depending on the amplitude.

Accordingly, the second embodiment has the same advantages as the first embodiment. In addition, the over-duty correction process of subtraction from all phases by an amount exceeding the reference maximum value Smaxand the reference minimum value Sminis performed for a reference sinusoidal wave signal, being a sinusoidal wave signal before modulation. This results in improvement of voltage use efficiency.

Third Embodiment

A third embodiment of the present invention is shown inFIGS. 16A,16B and17A to17C.

In the third embodiment, like the second embodiment, the duty calculator65includes the modulator653, which performs a modulation process to modulate a waveform of a reference sinusoidal wave.

In the third embodiment, a maximum-minimum (max-min) duty equalization process shown inFIGS. 16A and 16Bis performed as the modulation process in the modulator653. In this process, a U-phase duty Du, a V-phase duty Dv and a W-phase duty Dw are calculated based on the following equations. In the following equations, Du′, Dv′ and Dw′ are U-phase, V-phase and W-phase duties before modulation, respectively. Dmaxand Dminare the maximum value and the minimum value of duty of each phase before modulation, respectively.
Du=Du′−(Dmax−Dmin)/2  (1)
Dv=DV′−(Dmax−Dmin)/2  (2)
Dw=Dw′−(Dmax−Dmin)/2  (3)

Waveforms of duty command signals after correction, which are calculated based on the above equations (1) to (3), are as shown inFIG. 16B.

In the third embodiment, like the first embodiment, ripple current of the capacitor50is decreased by shifting a first duty command signal D31downwards and shifting a second duty command signal D32upwards. In addition, a difference in heat loss between FETs is suppressed to be smaller by varying the shift amounts of the first duty command signal D31and second duty command signal D32depending on their amplitudes.

Specifically, as shown inFIG. 17A, if the amplitude of the first duty command signal D31is equal to or less than 25% of the possible duty range, that is, if the minimum value Dmin31of the first duty command signal D31when a first duty center value Dc31is shifted such that the maximum value Dmax31of the first duty command signal D31corresponds to the output center value Rcis equal to or more than the lower limit Rminof the possible duty range, the first duty center value Dc31is shifted downwards such that the maximum value Dmax31of the first duty command signal D31corresponds to the output center value Rc. On the other hand, if the amplitude of the second duty command signal D32is equal to or less than 25% of the possible duty range, that is, if the maximum value Dmax32of the second duty command signal D32when a second duty center value Dc32is shifted such that the minimum value Dmin32of the second duty command signal D32corresponds to the output center value Rcis equal to or less than the upper limit Rmaxof the possible duty range, the second duty center value Dc32is shifted upwards such that the minimum value Dmin32of the second duty command signal D32corresponds to the output center value Rc.

As shown inFIG. 17B, if the amplitude of the first duty command signal D31is 25% of the possible duty range, when the first duty center value Dc31is shifted such that the maximum value Dmax31of the first duty command signal D31corresponds to the output center value Rc, the minimum value Dmin31of the first duty command signal D31corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D32is 25% of the possible duty range, when the second duty center value Dc32is shifted such that the minimum value Dmin32of the second duty command signal D32corresponds to the output center value Rc, the maximum value Dmax32of the second duty command signal D32corresponds to the upper limit Rmaxof the possible duty range.

As shown inFIG. 17C, if the amplitude of the first duty command signal D31is more than 25% of the possible duty range, that is, if the minimum value Dmin31of the first duty command signal D31when the first duty center value Dc31is shifted such that the maximum value Dmax31of the first duty command signal D31corresponds to the output center value Rcis less than the lower limit Rminof the possible duty range, the first duty center value Dc31is shifted such that the minimum value Dmin31of the first duty command signal D31corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D32is more than 25% of the possible duty range, that is, if the maximum value Dmax32of the second duty command signal D32when the second duty center value Dc32is shifted such that the minimum value Dmin32of the second duty command signal D32corresponds to the output center value Rcis more than the upper limit Rmaxof the possible duty range, the second duty center value Dc32is shifted such that the maximum value Dmax32of the second duty command signal D32corresponds to the upper limit Rmaxof the possible duty range.

That is, if the amplitude of the first duty command signal D31is equal to or less than 25% of the possible duty range, the first duty center value Dc31is shifted downwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the first duty command signal D31is more than 25% of the possible duty range, the first duty center value Dc31is shifted in a direction to be close to the output center value R.

In addition, if the amplitude of the second duty command signal D32is equal to or less than 25% of the possible duty range, the second duty center value Dc32is shifted upwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the second duty command signal D32is more than 25% of the possible duty range, the second duty center value Dc32is shifted in a direction to be close to the output center value Rcas the amplitude increases.

That is, in the third embodiment, the shift amount M31of the first duty center value Dc31from the output center value Rcand the shift amount M32of the second duty center value Dc32from the output center value Rccan be varied depending on the amplitude.

Accordingly, the third embodiment has the same advantages as the first embodiment. In addition, the Max-min duty equalization process of calculating an average value between the largest duty and the smallest duty for the sinusoidal wave signal before modulation and subtracting the average value from all phases is performed. This results in improvement of voltage use efficiency.

Fourth Embodiment

A fourth embodiment of the present invention is shown inFIGS. 18A,18B and19A to19C.

In the fourth embodiment, like the second and third embodiments, the duty calculator65includes the modulator653which performs a modulation process to modulate a waveform of a reference sinusoidal wave.

In the fourth embodiment, a lower uniform two-phase modulation process shown inFIGS. 18A and 18Bis performed as the modulation process in the modulator653. In this process, for a reference sinusoidal wave shown inFIG. 18A, a difference between a duty of the smallest phase and the reference minimum value Sminis subtracted from all phases such that the duty of the smallest phase corresponds to the reference minimum value Smin. Waveforms after the lower uniform two-phase modulation are as shown inFIG. 18B.

In the fourth embodiment, like the first embodiment, ripple current of the capacitor50is decreased by shifting a first duty command signal D41downwards and shifting a second duty command signal D42upwards. In addition, a difference in heat loss between FETs is suppressed to be smaller by varying the shift amounts of the first duty command signal D41and second duty command signal D42depending on their amplitudes.

Specifically, as shown inFIG. 19A, if the amplitude of the first duty command signal D41is equal to or less than 25% of the possible duty range, that is, if the minimum value Dmin41of the first duty command signal D41when a first duty center value Dc41is shifted such that the maximum value Dmax41of the first duty command signal D41corresponds to the output center value Rcis equal to or more than the lower limit Rminof the possible duty range, the first duty center value Dc41is shifted downwards such that the maximum value Dmax41of the first duty command signal D41corresponds to the output center value Rc. On the other hand, if the amplitude of the second duty command signal D42is equal to or less than 25% of the possible duty range, that is, if the maximum value Dmax42of the second duty command signal D42when a second duty center value Dc42is shifted such that the minimum value Dmin42of the second duty command signal D42corresponds to the output center value Rcis equal to or less than the upper limit Rmaxof the possible duty range, the second duty center value Dc42is shifted upwards such that the minimum value Dmin42of the second duty command signal D42corresponds to the output center value K.

As shown inFIG. 19B, if the amplitude of the first duty command signal D41is 25% of the possible duty range, when the first duty center value Dc41is shifted such that the maximum value Dmax41of the first duty command signal D41corresponds to the output center value Rc, the minimum value Dmin41of the first duty command signal D41corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D42is 25% of the possible duty range, when the second duty center value Dc42is shifted such that the minimum value Dmin42of the second duty command signal D42corresponds to the output center value Rcthe maximum value Dmax42of the second duty command signal D42corresponds to the upper limit Rmaxof the possible duty range.

As shown inFIG. 19C, if the amplitude of the first duty command signal D41is more than 25% of the possible duty range, that is, if the minimum value Dmin41of the first duty command signal D41when the first duty center value Dc41is shifted such that the maximum value Dmax41of the first duty command signal D41corresponds to the output center value Rcis less than the lower limit Rminof the possible duty range, the first duty center value Dc41is shifted such that the minimum value Dmin41of the first duty command signal D41corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D42is more than 25% of the possible duty range, that is, if the maximum value Dmax42of the second duty command signal D42when the second duty center value Dc42is shifted such that the minimum value Dmin42of the second duty command signal D42corresponds to the output center value Rcis more than the upper limit Rmaxof the possible duty range, the second duty center value Dc42is shifted such that the maximum value Dmax42of the second duty command signal D42corresponds to the upper limit Rmaxof the possible duty range.

That is, if the amplitude of the first duty command signal D41is equal to or less than 25% of the possible duty range, the first duty center value Dc41is shifted downwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the first duty command signal D41is more than 25% of the possible duty range, the first duty center value Dc41is shifted in a direction to be close to the output center value Rc.

In addition, if the amplitude of the second duty command signal D42is equal to or less than 25% of the possible duty range, the second duty center value Dc42is shifted upwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the second duty command signal D42is more than 25% of the possible duty range, the second duty center value Dc42is shifted in a direction to be close to the output center value Rcas the amplitude increases.

That is, in the fourth embodiment, the shift amount M41of the first duty center value Dc41from the output center value Rcand the shift amount M42of the second duty center value Dc42from the output center value Rccan be varied depending on the amplitude.

Accordingly, the fourth embodiment has the same advantages as the first embodiment. In addition, the lower uniform two-phase modulation process of subtracting a difference between a duty of the smallest phase and the reference minimum value from all phases such that the smallest duty in a sinusoidal wave signal before modulation corresponds to the reference minimum value Sminis performed. This results in improvement of voltage use efficiency.

Fifth Embodiment

A fifth embodiment of the present invention is shown inFIGS. 20A,20B and21A to21C.

In the fifth embodiment, like the second to fourth embodiments, the duty calculator65includes the modulator653, which performs a modulation process to modulate a waveform of a reference sinusoidal wave.

In the fourth embodiment, an upper uniform two-phase modulation process shown inFIGS. 20A and 20Bis performed as the modulation process in the modulator653. In this process, for a reference sinusoidal wave shown inFIG. 20A, a difference between a duty of the largest phase and the reference maximum value Smaxis added to all phases such that the duty of the largest phase corresponds to the reference maximum value Smax. Waveforms after the upper uniform two-phase modulation are as shown inFIG. 20B.

In the fourth embodiment, like the first embodiment, ripple current of the capacitor50is decreased by shifting a first duty command signal D51downwards and shifting a second duty command signal D52upwards. In addition, a difference in heat loss between FETs is suppressed to be smaller by varying the shift amounts of the first duty command signal D51and second duty command signal D52depending on their amplitudes.

Specifically, as shown inFIG. 21A, if the amplitude of the first duty command signal D51is equal to or less than 25% of the possible duty range, that is, if the minimum value Dmin51of the first duty command signal D51when a first duty center value Dc51is shifted such that the maximum value Dmax51of the first duty command signal D51corresponds to the output center value Rcis equal to or more than the lower limit Rminof the possible duty range, the first duty center value Dc51is shifted downwards such that the maximum value Dmax51of the first duty command signal D51corresponds to the output center value R. On the other hand, if the amplitude of the second duty command signal D52is equal to or less than 25% of the possible duty range, that is, if the maximum value Dmax52of the second duty command signal D52when a second duty center value Dc52is shifted such that the minimum value Dmin52of the second duty command signal D52corresponds to the output center value Rcis equal to or less than the upper limit Rmaxof the possible duty range, the second duty center value Dc52is shifted upwards such that the minimum value Dmin52of the second duty command signal D52corresponds to the output center value Rc.

As shown inFIG. 21B, if the amplitude of the first duty command signal D51is 25% of the possible duty range, when the first duty center value Dc51is shifted such that the maximum value Dmax51of the first duty command signal D51corresponds to the output center value Rc, the minimum value Dmin51of the first duty command signal D51corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D52is 25% of the possible duty range, when the second duty center value Dc52is shifted such that the minimum value Dmin52of the second duty command signal D52corresponds to the output center value Rc, the maximum value Dmax52of the second duty command signal D52corresponds to the upper limit Rmaxof the possible duty range.

As shown inFIG. 21C, if the amplitude of the first duty command signal D51is more than 25% of the possible duty range, that is, if the minimum value Dmin51of the first duty command signal D51when the first duty center value Dc51is shifted such that the maximum value Dmax51of the first duty command signal D51corresponds to the output center value Rcis less than the lower limit Rminof the possible duty range, the first duty center value Dc51is shifted such that the minimum value Dmin51of the first duty command signal D51corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D52is more than 25% of the possible duty range, that is, if the maximum value Dmax52of the second duty command signal D52when the second duty center value Dc52is shifted such that the minimum value Dmin52of the second duty command signal D52corresponds to the output center value Rcis more than the upper limit Rmaxof the possible duty range, the second duty center value Dc52is shifted such that the maximum value Dmax52of the second duty command signal D52corresponds to the upper limit Rmaxof the possible duty range.

That is, if the amplitude of the first duty command signal D51is equal to or less than 25% of the possible duty range, the first duty center value Dc51is shifted downwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the first duty command signal D51is more than 25% of the possible duty range, the first duty center value Dc51is shifted in a direction to be close to the output center value Rc.

In addition, if the amplitude of the second duty command signal D52is equal to or less than 25% of the possible duty range, the second duty center value Dc52is shifted upwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the second duty command signal D52is more than 25% of the possible duty range, the second duty center value Dc52is shifted in a direction to be close to the output center value Rcas the amplitude increases.

That is, in the fifth embodiment, the shift amount M51of the first duty center value Dc51from the output center value Rcand the shift amount M52of the second duty center value Dc52from the output center value Rccan be varied depending on the amplitude.

Accordingly, this embodiment has the same advantages as the first embodiment. In addition, the upper uniform two-phase modulation process of adding a difference between a duty of the largest phase and the reference maximum value to all phases such that the largest duty in a sinusoidal wave signal before modulation corresponds to the reference maximum value Smaxis performed. This results in improvement of voltage use efficiency.

Sixth Embodiment

A sixth embodiment of the present invention is shown inFIGS. 22A to 22C.

In the sixth embodiment, like the second to fifth embodiments, the duty calculator65includes the modulator653which performs a modulation process to modulate a waveform of a reference sinusoidal wave.

In the sixth embodiment, as the modulation process in the modulator653, a lower uniform two-phase modulation process shown inFIGS. 18A and 18Bis performed for a command voltage to drive the first inverter circuit20and a upper uniform two-phase modulation process shown inFIGS. 20A and 20Bis performed for a command voltage to drive the second inverter circuit30.

In the sixth embodiment, like the first embodiment, ripple current of the capacitor50is decreased by shifting a first duty command signal D61downwards and shifting a second duty command signal D62upwards. In addition, a difference in heat loss between FETs is suppressed to be smaller by varying the shift amounts of the first duty command signal D61and second duty command signal D62depending on their amplitude.

Specifically, as shown inFIG. 22A, if the amplitude of the first duty command signal D61is equal to or less than 25% of the possible duty range, that is, if the minimum value Dmax61of the first duty command signal D61when a first duty center value Dc61is shifted such that the maximum value Dmax61of the first duty command signal D61corresponds to the output center value Rcis equal to or more than the lower limit Rminof the possible duty range, the first duty center value Dc61is shifted downwards such that the maximum value Dmax61of the first duty command signal D61corresponds to the output center value Rc. On the other hand, if the amplitude of the second duty command signal D62is equal to or less than 25% of the possible duty range, that is, if the maximum value Dmax62of the second duty command signal D62when a second duty center value Dc62is shifted such that the minimum value Dmax62of the second duty command signal D62corresponds to the output center value Rcis equal to or less than the upper limit Rmaxof the possible duty range, the second duty center value Dc62is shifted upwards such that the minimum value Dmin62of the second duty command signal D62corresponds to the output center value Rc.

As shown inFIG. 22B, if the amplitude of the first duty command signal D61is 25% of the possible duty range, when the first duty center value Dc61is shifted such that the maximum value Dmax61of the first duty command signal D61corresponds to the output center value the minimum value Dmin61of the first duty command signal D61corresponds to the lower limit Rminof the possible duty range. In addition, if the amplitude of the second duty command signal D62is 25% of the possible duty range, when the second duty center value Dc62is shifted such that the minimum value Dmin62of the second duty command signal D62corresponds to the output center value Rc, the maximum value Dmax62of the second duty command signal D62corresponds to the upper limit Rmaxof the possible duty range.

As shown inFIG. 22C, if the amplitude of the first duty command signal D61is more than 25% of the possible duty range, that is, if the minimum value Dmin61of the first duty command signal D61when the first duty center value Dc61is shifted such that the maximum value Dmax61of the first duty command signal D61corresponds to the output center value Rcis less than the lower limit Rminof the possible duty range, the first duty center value Dc61is shifted such that the minimum value Dmin61of the first duty command signal D61corresponds to the lower limit Rcof the possible duty range. In addition, if the amplitude of the second duty command signal D62is larger than 25% of the possible duty range, that is, if the maximum value Dmax62of the second duty command signal D62when the second duty center value Dc62is shifted such that the minimum value Dmin62of the second duty command signal D62corresponds to the output center value Rcis more than the upper limit Rmaxof the possible duty range, the second duty center value Dc62is shifted such that the maximum value Dmax62of the second duty command signal D62corresponds to the upper limit Rmaxof the possible duty range.

That is, if the amplitude of the first duty command signal D61is equal to or less than 25% of the possible duty range, the first duty center value Dc61is shifted downwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the first duty command signal D61is more than 25% of the possible duty range, the first duty center value Dc61is shifted in a direction to be close to the output center value Rc.

In addition, if the amplitude of the second duty command signal D62is equal to or less than 25% of the possible duty range, the second duty center value Dc62is shifted upwards to be distant from the output center value Rcas the amplitude increases. In addition, if the amplitude of the second duty command signal D62is more than 25% of the possible duty range, the second duty center value Dc62is shifted in a direction to be close to the output center value Rcas the amplitude increases.

That is, in the sixth embodiment, the shift amount M61of the first duty center value Dc61from the output center value and the shift amount M62of the second duty center value Dc62from the output center value Rccan be varied depending on the amplitude.

Accordingly, the sixth embodiment has the same advantages as the first embodiment. In addition, the lower uniform two-phase modulation process of subtracting a difference between a duty of the smallest phase and the reference minimum value Sminfrom all phases such that the duty of the smallest phase in a sinusoidal wave signal before modulation corresponds to the reference minimum value Sminis performed for the first duty command signal D61. In addition, the upper uniform two-phase modulation process of adding a difference between a duty of the largest phase and the reference maximum value Smaxto all phases such that the duty of the largest phase in a sinusoidal wave signal before modulation corresponds to the reference maximum value Smaxis performed for the second duty command signal D62. This results in improvement of voltage use efficiency.

The present invention is not limited to the above described embodiments but it is to be understood that various modifications may be made as follows without departing from the spirit and scope of the invention.

(a) Change of Shift Direction of Voltage Command Signal

While it has been illustrated in the foregoing embodiments that the first duty command signal related to the driving and control of the first inverter circuit is shifted downwards from the output center value and the second duty command signal related to the driving and control of the second inverter circuit is shifted upwards from the output center value, however, the shift direction of the voltage command signals may be inversed each other.

In addition, in a modification, the shift direction of the voltage command signal related to the driving and control of the first inverter circuit and the shift direction of the voltage command signal related to the driving and control of the second inverter circuit may be switched for each predetermined period of time.

InFIG. 23, a first duty command signal D71related to the driving and control of the first inverter circuit is indicated by a solid line and a second duty command signal D72related to the driving and control of the second inverter circuit is indicated by a dashed line. As shown inFIG. 23, during a period of time T1, the first inverter circuit is driven and controlled by the first duty command signal D71shifted downwards and the second inverter circuit is driven by the second duty command signal D72shifted upwards. During a period of time T2following the period of time T1, the first inverter circuit is driven and controlled by the first duty command signal D71shifted upwards and the second inverter circuit is driven and controlled by the second duty command signal D72shifted downwards. In addition, during a period of time T3following the period of time T2, like the period of time T1, the first inverter circuit is driven and controlled by the first duty command signal D71shifted downwards and the second inverter circuit is driven by the second duty command signal D72shifted upwards.

In this manner, two (first and second) periods of time are alternated at predetermined intervals. During the first period of time, the first inverter circuit is driven and controlled with the center value of the first duty command signal D71determined based on a first shift amount shifted downwards from the output center value Rc, and the second inverter circuit is driven and controlled with the center value of the second duty command signal D72determined based on a second shift amount shifted upwards from the output center value Rc. During the second period of time, the first inverter circuit is driven and controlled with the center value of the first duty command signal D71determined based on the second shift amount shifted upwards from the output center value Rc, and the second inverter circuit is driven and controlled with the center value of the second duty command signal D72determined based on the first shift amount shifted downwards from the output center value Rc. This refers to changing shift directions of the duty command signals related to driving the respective inverter circuits at predetermined intervals. This allows integrated current values to be equalized and a deviation in heat loss between switching elements to be minimized by minimizing a difference in on-time between switching elements. The periods of time T1and T3correspond to the first period of time and the period of time T2corresponds to the second period of time. In addition, the first inverter circuit corresponds to one inverter circuit and the second inverter circuit corresponds to the other inverter circuit. In addition, the first duty command signal D71corresponds to a first voltage command signal and the second duty command signal D72corresponds to a “second voltage command signal.

However, when the shift directions of the duty command signals are periodically changed as described above, noisy sound may be produced due to discontinuity of the duty command signals. For example, if the power converter is applied to an apparatus, such as an electric power steering system (EPS) or the like, a period of time during which the shift directions are changed to provide a frequency at which the sound is imperceptible may be set or a change cycle of the shift directions may be varied.

In addition, during the period of time for the change of the shift directions, based on an integrated current value of switching elements, the shift directions of the duty command signals may be changed if the integrated current value of switching elements exceeds a predetermined value. That is, the first inverter circuit is driven and controlled with the center value of the first duty command signal determined based on the first shift amount shifted downwards from the output center value Rcand the second inverter circuit is driven and controlled with the center value of the second duty command signal determined based on the second shift amount shifted upwards from the output center value Rc. In addition, if the integrated value of current flowing through some of the switching elements exceeds a predetermined value, the first inverter circuit is driven and controlled with the center value of the first duty command signal determined based on the second shift amount shifted upwards from the output center value Rcand the second inverter circuit is driven and controlled with the center value of the second duty command signal determined based on the first shift amount shifted downwards from the output center value Rc. This allows integrated current values to be equalized and a deviation in heat loss between switching elements to be minimized by minimizing a difference in on-time between switching elements. In addition, since a change frequency is not constant when the shift directions of the duty command signals are changed based on the integrated current value, noisy sound due to the change of the shift directions may be suppressed.

Such a change of the shift direction may be applied to any of the above described embodiments.

(b) Position of Current Detector Circuit

FIGS. 24A to 24Fillustrate locations of the current detector circuit. FIGS.24A to24F show just the first inverter circuit20and the first set of windings18corresponding to the first inverter circuit20without the second inverter circuit30and the second set of windings19corresponding to the second inverter circuit30.

As shown inFIG. 24A, the current detectors41to43may be provided at a ground side of the low-side FETs24to26. As shown inFIG. 24B, without the W1 current detector43, the U1 current detector41may be provided between the U low-side FET24and the ground and the V1 current detector42may be provided between the U low-side FET25and the ground. As in this example, even if one of n-phase current detectors is excluded, current for all phases may be detected from a difference with power source current. For example, current of phases for two of three phase current detectors may be detected, current of phases for three of four phase current detectors may be detected, current of phases for four of five phase current detectors may be detected, etc. In addition, any phase for the current detectors may be excluded.

As shown inFIG. 24C, the current detectors41to43may be provided at a power source side of the high-side FETs21to23. As shown inFIG. 240, the W1 current detector43may be excluded in the example ofFIG. 24C. The exclusion of one of n-phase current detectors is as illustrated inFIG. 24B.

As shown inFIG. 24E, the current detectors41to43may be provided between respective nodes between the high-side FETs21to23and the low-side FETs24to26and corresponding windings11to13. As shown inFIG. 24F, the W1 current detector43may be excluded in the example ofFIG. 24E. The exclusion of one of n-phase current detectors is as illustrated inFIG. 24B.

(c) Type of Current Detector Circuit

If a current detector circuit is provided at the locations shown inFIGS. 24E and 24F, a Hall element is preferably used as a current detector. If a current detector circuit is provided at the locations shown inFIGS. 24A to 24D, the Hall element may be replaced with a shunt resistor as a current detector.

If a shunt resistor is provided, as a current detector, at the location shown inFIG. 24Aor24B, for example for a mountain side of the PWM reference signal shown inFIGS. 4A and 4B, since current flowing through the current detectors41to43when all of the low-side FETs24to26are turned on (referred to as mountain side current) is equal to current flowing through the set of windings18, the mountain side current is detected as winding current. On the other hand, for a valley side of the PWM reference signal, current flowing through the current detectors41to43when all of the low-side FETs24to26are turned off (referred to as valley side current) is used for correction of the winding current based on variation of temperature of a shunt resistor or an amplification circuit.

That is, if a shunt resistor is used as the current detector, for the mountain and valley sides of the PWM reference signal, it is necessary to secure a period of time during which all of the low-side FETs24to26are turned on or a period of time during which all of the low-side FETs24to26are turned off. In addition, if current is detected by a shunt resistor, it is necessary to secure rigging convergence time (for example, 4.5 μsec), i.e., hold time for which no on/off switching of FETs is performed. Accordingly, for the current detector circuit, an possible duty range may be determined based on time taken to detect current.

In addition, if it is net necessary to correct winding current, only the upper limit of the possible duty range may be determined based on time taken to detect current in the current detector circuit.

In addition, if a shunt resistor is provided, as a current detector, at the location shown inFIG. 24Cor24D, for the valley side of the PWM reference signal, since the valley side current flowing through the current detectors41to43when all of the high-side FETs21to23are turned on is equal to the current flowing through the set of windings18, the valley side current is detected as the winding current. In this case, if it is not necessary to correct winding current, only the lower limit of the possible duty range may be determined based on time taken to detect current in the current detector circuit.

Accordingly, current flowing through the set of windings from the current detector circuit can be properly detected.

In addition, it is necessary that a bootstrap type gate driver circuit turns on all of the low-side FETs24to26for each predetermined cycle. This does not allow the upper limit of the possible duty range to be set to 100%. Accordingly, the upper limit of the possible duty range may be determined based on a configuration of a gate driver circuit.

(d) Other Modifications

While it has been illustrated in the foregoing embodiments that two lines of inverter circuits drive one motor10, as schematically shown inFIG. 25A, the two lines of inverter circuits may be configured to drive different motors, respectively, as schematically shown inFIG. 25B. For example, a first inverter circuit120may drive a first motor110while a second inverter circuit130may drive a second motor111.

Although it has been illustrated in the foregoing embodiments that all of the multiphase rotating electric machines are motors, they are not limited thereto but may be electric generators. Moreover, the multiphase rotating electric machines are not limited to EPSs but may be used for many different applications other than EPS including, for example, power windows and so on.