Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology

A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.

BACKGROUND

This disclosure relates generally to non-volatile memories (NVMs) and logic transistors, and more particularly, integrating NVMs with logic transistors that have high-k gate dielectrics and metal gates using a gate-last methodology.

2. Related Art

The integration of non-volatile memories (NVMs) with logic transistors has always been a challenge due to the different requirements for the NVM transistors, which store charge, and the logic transistors which are commonly intended for high speed operation. The need for storing charge has been addressed mostly with the use of floating gates but also with nanocrystals or nitride. In any of these cases, the need for this unique layer makes integration of the NVM transistors and the logic transistors difficult. The particular type of charge storage layer can also have a large effect on the options that are available in achieving the integration.

Accordingly there is a need to provide an integration that improves upon one or more of the issues raised above.

DETAILED DESCRIPTION

In one aspect, an integration of a non-volatile memory (NVM) cell in a NVM region of an integrated circuit and a logic transistor in a logic region of the integrated circuit includes forming the gate structure of the NVM cell in the NVM region, including the charge storage layer, while masking the logic region. The logic gate is formed while masking the NVM region with a hard mask that is subsequently used to form sidewall spacers in the NVM region. Source/drain implants are performed simultaneously in the NVM and logic regions. This is better understood by reference to the drawings and the following written description.

The semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. Oxide layer refers to a silicon oxide layer unless otherwise noted. Similarly, nitride layer refers to a silicon nitride layer unless otherwise noted.

Shown inFIG. 1is a semiconductor structure10of an integrated circuit having an NVM region11and a logic region13. Semiconductor structure10has a substrate12, an isolation region15separating logic region13from NVM region11, an isolation region17in NVM region11that, along with isolation region15, that defines borders of an active region in NVM region11, a P well14in substrate12in the NVM region extending from the surface of substrate12, a P well18in logic region13that extends from the surface of substrate12, an N region16below P well18for aiding in providing noise isolation for the logic transistors, an oxide layer20on the top surface of substrate12in NVM region11and logic region13. Oxide layer20is a thermal oxide that is grown, rather than deposited, for high quality. Over oxide layer20and isolation regions15and17is a polysilicon layer22that may be doped in situ or by implant. Nitride layer23(also referred to as an optical patterning layer or cap layer) is deposited on polysilicon layer22in NVM region11and logic region13. Alternatively, a layer of oxide (not shown) may be deposited over polysilicon layer22instead of nitride layer23. N wells are also formed in other portions of logic region13, which are not shown, for the forming P channel transistors.

Shown inFIG. 3is semiconductor structure10after forming a charge storage layer24having nanocrystals such as nanocrystal26. Nanocrystal layer is preferably formed by first growing a thermal oxide layer on the exposed top surface of substrate12and on the exposed surfaces of polysilicon layer22and cap layer23. This oxide grown on the top surface of substrate12is of particular importance because that is where charge will pass during program and erase. The nanocrystals are formed on the grown oxide and a deposited oxide is formed on and around the nanocrystals.

Shown inFIG. 4is semiconductor structure10after depositing a polysilicon layer28on charge storage layer24. This polysilicon layer is made conductive by doping which may be in situ or by implant.

Shown inFIG. 5is semiconductor structure10after an oxide layer29is formed on polysilicon layer28, a patterned photoresist layer is formed on oxide layer29, and a patterned etch of polysilicon layer28and oxide layer29is performed that results in NVM gate structures30and32. For NVM gate structure30, the portion of polysilicon layer22is the select gate and the portion of polysilicon layer28is the control gate in which a portion of the control gate is over a portion of the select gate and over a portion of the substrate adjacent to a side of the select gate facing NVM gate structure32. For NVM gate structure32, the portion of polysilicon layer22is the select gate and the portion of polysilicon layer28is the control gate in which a portion of the select gate is over a portion of the control gate and over a portion of the substrate adjacent to a side of the select gate facing NVM gate structure30. Charge storage layer24is between the select gate and control gate of NVM gate structure30and between the select gate and control gate of NVM gate structure32.

Shown inFIG. 6is semiconductor structure10after removing charge storage layer24from over substrate12and logic region13and leaving charge storage layer under the control gates and between the select gates and control gates.

Shown inFIG. 7is semiconductor structure10after depositing an oxide layer34, a nitride layer36on oxide layer34, and an oxide layer38on nitride layer36. Oxide layer34provides protection for the polysilicon from nitride layer36.

Shown inFIG. 8is semiconductor structure10after removing oxide layer34, nitride layer36, oxide layer38, polysilicon22and oxide20from logic region13. The remaining portion of oxide layer34, nitride layer36, and oxide layer38over NVM region functions as a hard mask.

Shown inFIG. 9is semiconductor structure10after forming a layer of high-k dielectric40on substrate12in logic region13and over the hard mask of oxide layer34, nitride layer36, and oxide layer38in NVM region11.

Barrier metal42is then deposited over high-k dielectric40for the P wells. Barrier metal42can function as a work function metal for P wells, such as P well18, and for providing a highly conductive gate conductor for both the N and P channel transistors. A polysilicon layer44is deposited over barrier metal42and a cap layer45(such as a nitride) is deposited over polysilicon layer44.

Cap layer45, polysilicon layer44, barrier metal42, and high-k dielectric40in logic region13are then selectively etched to leave a logic gate46in logic region13. The etch of metal42has the effect of metal making contact with NVM region11which can be a contaminant to charge storage layer24, especially when charge storage layer24has nanocrystals. The hard mask formed by oxide layer34and nitride layer36prevents the metal from contaminating NVM structures30and32. Oxide layer38in NVM region11is removed by a pre-clean prior to deposition of high-k dielectric40.

Shown inFIG. 10is semiconductor structure10after depositing a nitride layer48and an oxide layer50on nitride layer48. In NVM region11, nitride layer48is on nitride layer36. There is then an oxide-nitride-oxide layer of oxide layer34, nitride layers36and48, and oxide layer50in NVM region11. In logic region13, nitride layer48is on substrate12, although a thin native oxide layer may be between substrate12and nitride layer48, and on logic gate structure46. Oxide layer50is on nitride layer48. Oxide layers34and50and nitride layers36and48are conformal.

A patterned etch of oxide layer50is then performed to remove oxide layer50from NVM region11and leave oxide layer50in logic region13.

A selective etch of nitride layers36and48is performed using oxide layer50as a hard mask in logic region13. Nitride layers36and48are thus removed from NVM region11and nitride layer48is retained in logic region13. The use of oxide layer50as a hard mask allows for this selective etch of nitride layers36and48to be achieved without requiring a mask step using photoresist.

Shown inFIG. 11is semiconductor structure10after performing an anisotropic etch of oxide and a subsequent nitride etch that results in oxide layer34becoming sidewall spacers52,54,56, and58around NVM gate structures30,32in NVM region11. Oxide layer50becomes sidewall spacer60, and nitride layer48becoming a sidewall spacer62around logic control gate46. Sidewall spacer52is around a lower portion of NVM gate structure30adjacent to the select gate on one side and the control gate on the other side. Sidewall spacer54surrounds an upper portion of the NVM gate structure30adjacent to an upper portion of the control gate. Sidewall spacer56is around a lower portion of NVM gate structure32adjacent to the select gate on one side and the control gate on the other side. Sidewall spacer58surrounds an upper portion of the NVM gate structure32adjacent to an upper portion of the control gate. Sidewall spacer60is around logic gate structure46. The etch of nitride layer48removes nitride layer48from over substrate12and over the horizontal top surface of logic gate structure46. The result is a sidewall spacer62of nitride around logic gate structure46that may also be called a liner under sidewall spacer60.

Shown inFIG. 12is semiconductor structure10after receiving a source/drain implant that forms source/drain regions66,68and70in NVM region11and source/drain regions72and74in logic region13in substrate12. In particular source/drain region66is in well14nearly aligned to the select gate of NVM gate structure30, source/drain region68is in P well14nearly aligned to the control gates of NVM gate structures30and32, and source/drain region70is in P well14and nearly aligned to the select gate of NVM gate structure32. The implant forms the source/drain regions that, after processing is complete, define channel length. Source/drain regions72and74are nearly aligned to opposing sides of logic gate structure46. The presence of sidewall spacer62results in source/drain regions72and74are further from being aligned to the sides of logic gate structure46than source/drain regions66,68, and70are from being aligned to the select gates and control gates of NVM gate structures30and32. The source/drain regions shown are N type.

A second set of sidewall liners75,77,79,81,84of oxide and spacers76,78,80,82and86of nitride are then formed around sidewall spacers52,54,56,58, and62, respectively.

An implant that is further spaced from gate edges due to sidewall spacers76,78,80,82, and86is then performed that results in more heavily doped source/drain regions88,90,92,94, and96which are somewhat deeper and result in portions of source/drain regions66,68,70,72, and74, respectively, having higher doping concentrations thus having higher conductivity. This completes the steps for formation of the NVM cells and the logic transistor. These more heavily doped regions can then be silicided to make low resistance contacts100,102,104,106,108,110,112. The tops of polysilicon control gates28can also be silicided to make contacts111,113.

Shown inFIG. 13is semiconductor structure10after interlayer dielectric (ILD)114is conformally deposited in NVM region11and logic region13. ILD114is then planarized using chemical mechanical polishing (CMP) to a height that remains above the top of logic gate46and NVM cells30,32, for example by 200 Angstroms or more above the height of control gate28. ILD114is then etched to recess ILD to a height that remains above logic gate46but may be below the top of the control gate28and above the top of select gates22in NVM cells30,32. A layer of polysilicon is then conformally deposited over recessed ILD114in NVM region11and logic region13.

Shown inFIG. 14is semiconductor structure10after a polysilicon layer116and a portion of recessed ILD114are removed and planarized using CMP. A portion of the control gate for logic device46, and cap layer23, a portion of control gates28, and a portion of charge storage layer24over select gates22of NVM cells30,32, is removed. The use of polysilicon layer116over ILD114before the CMP helps prevent damage to the polysilicon in the control gates28of NVM cells30,32during the CMP planarization.

Shown inFIG. 15is semiconductor structure10after a hard mask is formed over NVM region11including a layer of nitride118and a layer of oxide120. Sacrificial polysilicon gate44is removed from logic structure46using a wet etch to form a gate opening122surrounded by first spacer60for logic structure46.

Shown inFIG. 16is semiconductor structure10after work function metal124is deposited around the sides and bottom of the gate opening122in logic structure46. A gate metal126is then deposited over the work function metal124to fill the gate opening122. Combinations of work function metal124and the barrier metal42(FIG. 11) sets the work function of N channel transistors and provides a highly conductive gate conductor in logic region13. An alternate combination of barrier metal and work function material can be used for P channel transistors.

After gate metal126is deposited in logic structure46, oxide layer120is removed by CMP over NVM region11and logic region13. Nitride layer118can be left in NVM region11or removed.

Shown inFIG. 17is semiconductor structure10after an additional layer of interlayer dielectric128is deposited over nitride layer118in NVM region11and in logic region13. Openings can be formed in dielectric128and filled with conductive material130to make contact with source/drain contacts100,104,108,110,112of NVM structures30,32and logic structure46.

Thus it is shown that metal gate transistors can be made in the presence of NVM cells, even if the NVM cells use nanocrystals, and further that the hard mask used during the metal etch can also subsequently be used in forming sidewall spacers used as an implant mask.

By now it should be appreciated that in some embodiments there has been provided a method of making a semiconductor structure (10) using a substrate (12), wherein the semiconductor structure comprises a logic device (46) in a logic region (13) and a non-volatile memory (NVM) device (30) in an NVM region (11). The method can comprise forming an NVM structure (30) in the NVM region, wherein the NVM structure comprises a control gate structure (28) and a select gate structure (22). A protective layer (34,36,38) is formed over the NVM structure. A gate dielectric layer (40) is formed over the substrate in the logic region, wherein the gate dielectric layer comprises a high-k dielectric. A sacrificial gate (44) is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed (114) around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure (124,126).

In another aspect, the forming the NVM structure can be further characterized by the select gate having a top surface and the control gate structure having an upper portion overlapping a portion of the top surface of the select gate.

In another aspect, wherein performing chemical mechanical polishing includes depositing a layer of polysilicon (116) over the top of the control gate and then removing the upper portion of the control gate that overlaps the portion of the top surface of the select gate.

In another aspect, the method can further comprise performing the source/drain implants (66,68,70,72,74,88,90,92,94,96) in the NVM region and the logic region prior to forming the first dielectric layer.

In another aspect, the method can further comprise forming a first sidewall spacer (60,62) around the sacrificial gate after forming the first sidewall spacer and before forming the first dielectric layer.

In another aspect, the replacing the sacrificial gate can comprise removing the sacrificial gate to leave an opening (122) over the gate dielectric layer; and forming a work function metal (124) in the opening.

In another aspect, the replacing the sacrificial gate further can comprise forming a metal gate (126) on the work function metal.

In another aspect, the forming the NVM structure can be further characterized by forming a capping layer (23) on the top surface of the select gate.

In another aspect, the forming the capping layer can be characterized by the capping layer comprising nitride.

In another aspect, the performing the chemical mechanical polishing can be further characterized as leaving at least a portion of the capping layer over the select gate structure.

In another aspect, the protective layer comprises a first oxide layer (34), a nitride layer (36) on the first oxide layer, and a second oxide layer (38) on the nitride layer.

In another aspect, the method can further comprise removing the second oxide layer and the nitride layer; and anisotropically etching the first oxide layer to form a sidewall spacer (52) around the select gate structure and the control gate structure.

In another aspect, the forming the NVM structure is further characterized by the control gate structure and the select gate structure comprising polysilicon.

In further embodiments, a method of making a semiconductor structure (10) using a substrate (12) is provide, wherein the semiconductor structure comprises a logic device (46) in a logic region (13) and a non-volatile memory (NVM) device (30) in an NVM region (11). The method can comprise forming an NVM structure (30) in the NVM region, wherein the NVM structure comprises a control gate structure (28) and a select gate structure (22) in which the control gate structure has an upper portion extending over a portion of a top surface of the select gate structure. A replacement gate structure (40,42,44,45) is formed in the logic region having a sacrificial gate (44). Chemical mechanical polishing is performed on the logic region and the NVM region which removes the upper portion of the control gate structure. The sacrificial gate is replaced with a metal gate structure (124,126).

In another aspect, the forming the replacement gate structure can comprise forming a gate dielectric (40) comprising a high-k dielectric.

In another aspect, the forming the replacement gate structure can be further characterized by the sacrificial gate comprising polysilicon; and further comprises forming a barrier layer (42) on the gate dielectric.

In another aspect, the replacing the sacrificial gate is further characterized by the metal gate structure comprising: a work function metal (124) on the barrier layer; and a metal gate (126) on the work function metal.

In another aspect, the method can further comprise forming a protection layer (34,36,38) over the NVM region after forming the NVM structure and before forming the replacement gate structure.

In another aspect, the method can further comprise forming a capping layer (23) over the select gate prior to forming the protection layer; and removing a portion of the capping layer during the performing the chemical mechanical polishing.

In still other embodiments, a method of making a semiconductor structure (10) using a substrate (12), wherein the semiconductor structure comprises a logic device (46) in a logic region (13) and a non-volatile memory (NVM) device (30) in an NVM region (11), can comprise forming an NVM structure (30) in the NVM region, wherein the NVM structure comprises a control gate structure (28) and a select gate structure (22) in which the control gate structure has an upper portion extending over a portion of a top surface of the select gate structure and the select gate structure has a nitride capping layer (23) on its top surface. A protection layer (34,36,38) is formed over the NVM region. A replacement gate structure (40,42,44,45) is formed in the logic region having a high-k dielectric (40), a barrier layer (42) on the high-k dielectric, and a sacrificial gate (44). Chemical mechanical polishing is performed on the logic region and the NVM region which removes the upper portion of the control gate structure and leaves a portion of the nitride capping layer on the top surface of the select gate structure. The sacrificial gate is replaced with a work function metal (124) on the barrier layer and a metal gate (126) on the barrier layer.