Non-volatile memory device having vertical structure and method of manufacturing the same

A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0120543, filed on Aug. 26, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The inventive concept relates to a non-volatile memory device having a vertical structure and a method of manufacturing the non-volatile memory device.

DISCUSSION OF RELATED ART

Volume miniaturization and high-capacity data processing are usually required for the modern electronic products. To fulfill these requirements, a non-volatile memory device having a vertical transistor structure instead of a conventional memory device having a horizontal transistor structure has been proposed. Recently, channel hole formation technology, which may ensure process simplification and reliability, has been adopted for the processes of manufacturing non-volatile memory devices having feature sizes highly miniaturized.

SUMMARY

The inventive concept provides a non-volatile memory device having a vertical structure, which may have simplified manufacturing processes and constant reliability, and a method of manufacturing the non-volatile memory device.

According to an aspect of the inventive concept, there is provided a non-volatile memory device having a vertical structure, the non-volatile memory device including: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer, and the first interlayer insulating layer, and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region of the gate dielectric layer which contacts the first gate electrode is greater than that in a region of the gate dielectric layer which contacts one of the second gate electrodes.

The gate dielectric layer contacts a top surface of the first interlayer insulating layer.

A separation distance between side walls of the gate dielectric layer in a region of the gate dielectric layer which contacts the first interlayer insulating layer is greater than that in a region of the gate dielectric layer which contacts one of the second interlayer insulating layers.

The gate dielectric layer includes: a tunneling insulating layer which contacts the channel region, a charge storage layer which contacts the tunneling insulating layer, and a first blocking insulating layer between the first gate electrode or the second gate electrodes and the charge storage layer.

The non-volatile memory device further includes a second blocking insulating layer which contacts the first blocking insulating layer in a region between two adjacent interlayer insulating layers from among the first interlayer insulating layer and the second interlayer insulating layers.

The gate dielectric layer has a bulb-type cross-section structure.

The first interlayer insulating layer is thinner than each of the second interlayer insulating layers.

The first interlayer insulating layer includes a middle temperature oxide (MTO) layer.

The first gate electrode is thicker than each of the second gate electrodes.

The channel region includes: a first channel layer formed on the gate dielectric layer, and a second channel layer formed on the first channel layer, wherein the second channel layer penetrates a bottom surface of the first channel layer, a bottom surface of the gate dielectric layer, and the first interlayer insulating layer, and is connected to the substrate.

According to another aspect of the inventive concept, there is provided a non-volatile memory device having a vertical structure, the non-volatile memory device including: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; a plurality of memory cell strings spaced apart from each other in a first direction parallel to a top surface of the substrate, wherein each of the memory cell strings penetrates the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and vertically extends on the substrate; and a common source line structure penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and extending in the first direction between memory cell strings that are adjacent to each other in a second direction perpendicular to the first direction from among the plurality of memory cell strings, wherein a width of each of the plurality of memory cell strings in the first direction in a region of the memory cell string which contacts the first gate electrode is greater than that in a region of the memory cell string which contacts one of the second gate electrodes.

The common source line structure includes: a common source line which penetrates the first interlayer insulating layer and is connected to the substrate; and a common source line spacer disposed on side walls of the common source line and positioned between the common source line and the first gate electrode or the second gate electrodes.

A bottom surface of the common source line spacer contacts a top surface of the first interlayer insulating layer.

A bottom surface of the common source line is located at a lower level than a bottom surface of the common source line spacer.

The substrate includes an impurity region in a recess of the top surface of the substrate, the common source line contacts the impurity region, and the common source line spacer is spaced apart from the impurity region.

The impurity region includes a first impurity region and a second impurity region, in which the second impurity region is located at the center and contacts the common source line, while the first impurity region surrounds the second impurity region, and the impurity concentration of the first impurity region is smaller than that of the second impurity region.

A width of each of the plurality of memory cell strings in a region of the memory cell string which contacts a top surface of the first interlayer insulating layer is greater than that in a region of the memory cell string which contacts one of the second interlayer insulating layers.

Each of the plurality of memory cell strings has a bulb-type cross-section structure.

Each of the plurality of memory cell strings includes: a filling insulating layer located at center of each of the plurality of memory cell strings; a channel region disposed on side walls and bottom of the filling insulating layer; and a gate dielectric layer disposed on side walls and some bottom portion of the channel region, in which the gate dielectric layer contacts a top surface of the first interlayer insulating layer, and the channel region penetrates the gate dielectric layer and the first interlayer insulating layer vertically on the substrate and is electrically connected to the substrate.

A ground selection transistor, a plurality of memory cell transistors, and a string selection transistor are disposed along side walls of the gate dielectric layer in a third direction which is perpendicular to the first and second directions.

According to yet another aspect of the inventive concept, there is provided a non-volatile memory device having a vertical structure, the non-volatile memory device including: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; and a plurality of memory cell strings spaced apart from each other in a first direction parallel to a top surface of the substrate, wherein each of the memory cell strings penetrates the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and vertically extends on the substrate, wherein a width of each of the plurality of memory cell strings in a region of the memory cell string which contacts a top surface of the first interlayer insulating layer is greater than that in a region of the memory cell string which contacts one of the second interlayer insulating layers.

Since the drawings inFIGS. 1-8are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity purpose.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the inventive concept will now be described in detail with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. In the drawings, the same elements are denoted by the same reference numerals and a repeated explanation thereof will not be given.

The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to one of ordinary skill in the art.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of”, when preceding a list of elements, modify the entire list of elements and do not just modify the individual elements of the list. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that, although the terms “first”, “second”, “third” etc. may be used herein to describe various members, regions, layers, portions, and/or elements, these members, regions, layers, portions, and/or elements should not be limited by these terms. These terms are only used to distinguish one member, region, layer, portion, or element from another member, region, layer, portion, or element. Thus, a first member, region, layer, portion, or element discussed below could be termed a second member, region, layer, portion, or element, or vice versa, without departing from the teachings of exemplary embodiments of the inventive concept. For example, a first element may be referred to as a second element, and likewise, a second element may be referred to as a first element without departing from the scope of the inventive concept.

All terms including technical and scientific terms used herein have meanings which can be generally understood by those of ordinary skill in the art, if the terms are not particularly defined. General terms defined by dictionaries should have meanings which can be contextually understood by any person skilled in the art and should not have ideally or excessively formal meanings, if the terms are not particularly defined herein by the exemplary embodiments of the inventive concept.

A specific process order in one embodiment may be changed in another embodiment. For example, two processes which are described as being continuously performed may be simultaneously performed or may be performed in a reverse order. As such, variations from the shapes of the illustrations caused from, for example, various manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing.

A non-volatile memory device according to one or more exemplary embodiments of the inventive concept may include a cell array region, a peripheral circuit region, a sense amplifier region, a decoding circuit region, and a connection region. In the cell array region, a plurality of memory cells, and bitlines and wordlines for electrical connection to the memory cells may be disposed. In the peripheral circuit region, circuits for driving the memory cells may be disposed, and in the sense amplifier region, circuits for reading information stored in the memory cells may be disposed. The connection region may be disposed between the cell array region and the decoding circuit region, and in the connection region, a wiring structure for electrically connecting the wordlines and the decoding circuit region may be disposed.

FIG. 1illustrates an equivalent circuit of a memory cell array10of a non-volatile memory device having a vertical structure, according to an exemplary embodiment of the inventive concept, and more particularly, illustrates an equivalent circuit diagram of a NAND flash memory device having a vertical structure including a vertical channel structure.

Referring toFIG. 1, the memory cell array10may include a plurality of memory cell strings11. Each of the memory cell strings11may have a vertical structure extending in a direction (z direction) perpendicular to a plane (x-y plane) that a top surface of a substrate forms. A memory cell block13may be formed by the memory cell strings11.

Each of the memory cell strings11may include a plurality of memory cells MC1to MCn, a string selection transistor SST, and a ground selection transistor GST. In each of the memory cell strings11, the ground selection transistor GST, the memory cells MC1to MCn, and the string selection transistor SST may be disposed in series in the vertical direction (z direction). In this regard, each of the memory cells MCI to MCn may be used to store data. A plurality of wordlines WL1to WLn may be coupled to the memory cells MC1to MCn, respectively, thereby controlling the memory cells MC1to MCn coupled thereto, respectively. The number of the memory cells MC1to MCn may be changed according to the change in capacity of a semiconductor memory device.

A plurality of bitlines BL1to BLm extending in the x direction may be connected to one side of each of the memory cell strings11arranged in first to m-th columns of the memory cell block13, for example, a drain of the string selection transistor SST. Also, a common source line CSL may be connected to the other side of each of the memory cell strings11, for example, a source of the ground selection transistor GST.

The wordlines WL1to WLn extending in the y direction may be commonly connected to gates of the memory cells MC1to MCn of the memory cell strings11arranged on the same layer. By driving the wordlines WL1to WLn, data may be programmed on, read from, or erased from the memory cells MC1to MCn.

In each of the memory cell strings11, the string selection transistor SST may be arranged between the bitlines BL1to BLm and the memory cells MC1to MCn. In the memory cell block13, each string selection transistor SST may control data transmission between the bitlines BL1to BLm and the memory cells MC1to MCn by using a string selection line SSL connected to a gate of each string selection transistor SST.

The ground selection transistor GST may be arranged between the memory cells MC1to MCn and the common source line CSL. In the memory cell block13, each ground selection transistor GST may control data transmission between the memory cells MC1to MCn and the common source line CSL by using a ground selection line GSL connected to a gate of each ground selection transistor GST.

FIG. 2Ais a perspective view of a non-volatile memory device100according to an exemplary embodiment of the inventive concept.FIG. 2Bis a cross-sectional view taken along line B2-B2ofFIG. 2A.

To illustrate a structure of a plurality of memory cell strings three-dimensionally, some elements illustrated inFIG. 2B, such as a bitline193and a bitline contact plug195, are omitted inFIG. 2A.

Referring toFIGS. 2A and 2B, the non-volatile memory device100may include the memory cell strings11, a plurality of gate electrodes150, a plurality of insulating layers160,181, and183, a common source line structure170, the bitline193, and the bitline contact plug195on a substrate101.

The substrate101may include, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like. A p-well may be further formed on the substrate101. The substrate101may have a main surface extending in both x and y directions (x-y plane).

The memory cell strings11, as illustrated inFIG. 2A, may be separate from each other in a zigzag form. That is, the memory cell strings11separate from each other in the y direction may be offset in the x direction. Also, although, in the present exemplary embodiment of the inventive concept, the memory cell strings11are offset for every two columns, arrangement of the memory cell strings11is not limited thereto, and the memory cell strings11may be arranged to have various structures. For example, the memory cell strings11may be disposed in one column in the y direction, or may be offset in the x direction for every three or more columns and disposed in a zigzag form. Further, a structure of the memory cell strings11is not limited to the zigzag form illustrated inFIG. 2A, and the memory cell strings11may be disposed in a matrix separate from each other side by side in the x direction and the y direction.

Each of the memory cell strings11may extend in a direction perpendicular to a top surface of the substrate101(in the z direction). Each of the memory cell strings11may include a channel region130, a gate dielectric layer140, a filling insulating layer175, and the ground selection transistor GST, a plurality of memory cell transistors MC1, MC2, MC3, and MC4, and the string selection transistor SST, which are disposed along side walls of the gate dielectric layer140. In some cases, each of the ground selection transistor GST and the string selection transistor SST may be two.

The channel region130having a pillar shape may extend in the z direction on the substrate101. As illustrated inFIG. 2A, the channel region130may be annular. However, a shape of the channel region130is not limited thereto, and the channel region130may have a cylinder or rectangular prism form.

The channel region130may be electrically connected to the substrate101at the bottom of the channel region130. For example, as illustrated inFIGS. 2A and 2B, the channel region130may include a contact portion132protruding from a lower surface of the channel region130, and thus may be connected to the substrate101via the contact portion132.

In an exemplary embodiment of the inventive concept, the channel region130may include a first channel layer130aand a second channel layer130b. The first channel layer130amay cover the gate dielectric layer140, and the second channel layer130bmay cover the first channel layer130a. The gate dielectric layer140may surround the side walls and bottom of the first channel layer130aas shown inFIGS. 2A and 2B.

In an exemplary embodiment of the inventive concept, the second channel layer130bmay include the contact portion132penetrating the first channel layer130a, the gate dielectric layer140and a first interlayer insulating layer161, and connected to the substrate101.

Each of the first channel layer130aand the second channel layer130bmay include, for example, a semiconductor material such as polysilicon or single crystalline silicon. The first channel layer130aand the second channel layer130bmay include, but are not limited to, the same material.

In an exemplary embodiment of the inventive concept, each of the first channel layer130aand the second channel layer130bmay include polysilicon doped with n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb) or p-type impurities such as aluminum (Al), boron (B), indium (In), or potassium (K). In an exemplary embodiment of the inventive concept, each of the first channel layer130aand the second channel layer130bmay include polysilicon not doped with impurities.

A conductive layer190may be formed on the channel region130, the gate dielectric layer140and the filling insulating layer175, and electrically connected to the channel region130. The conductive layer190may include, for example, doped polysilicon. The conductive layer190may act as a drain region of the string selection transistor SST.

The string selection transistors SST may be connected to the bitline193via the conductive layer190and the bitline contact plug195. Also, ground selection transistors GST may be electrically connected to an impurity region105.

The impurity region105may be formed in the main surface of the substrate101and may extend in the y direction. Although only one impurity region105is illustrated inFIGS. 2A and 2B, the impurity region105may be arranged for each gap between channel regions130next to each other in the x direction. In an exemplary embodiment of the inventive concept, the impurity region105may be a source region and may form PN junction with another region of the substrate101. The impurity region105may include a second impurity region105badjacent to the main surface of the substrate101and located at the center, and a first impurity region105asurrounding the second impurity region105b. In an exemplary embodiment of the inventive concept, the first impurity region105amay be a low impurity concentration region, and the second impurity region105bmay be a high impurity concentration region.

The common source line structure170may be formed on the impurity region105. The common source line structure170may penetrate the plurality of gate electrodes150and the plurality of insulating layers160, and extend in the y direction between memory cell strings11that are adjacent to each other in the x direction. In an exemplary embodiment of the inventive concept, the common source line structure170may include a common source line172and common source line spacers174.

Although the memory cell strings11adjacent to each other in the present exemplary embodiment of the inventive concept are symmetrical to the common source line structure170, arrangement of the memory cell strings11is not limited thereto. For example, the adjacent memory cell strings11may be asymmetrical with respect to the common source line structure170.

The common source line172may be formed on the impurity region105of the substrate101. For example, the common source line172may extend in the y direction on a portion of the impurity region105. In some cases, the common source line172may be formed on the entire impurity region105in the y direction.

In an exemplary embodiment of the inventive concept, the common source line172may include metal, for example, tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), etc. In an exemplary embodiment of the inventive concept, the common source line172may include a conductive material, for example, polysilicon doped with impurities or metal silicide such as nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, etc.

The common source line spacers174including an insulating material may be formed on both side walls of the common source line172. The common source line spacers174may be formed on side walls of the gate electrodes150, and may serve as a device isolation layer electrically insulating the gate electrodes150and the common source line172.

In an exemplary embodiment of the inventive concept, the common source line172may contact the impurity region105of the substrate101, and the common source line spacers174may be separate from the impurity region105of the substrate101. That is, the common source line172may penetrate the first interlayer insulating layer161and may be connected to the substrate101, and the common source line spacers174may contact a top surface of the first interlayer insulating layer161. Accordingly, a bottom surface172B of the common source line172may be located at a lower level than bottom surfaces174B of the common source line spacers174.

The gate electrodes151to156(150) may be separate from each other in the z direction along side surfaces of the channel region130, and each of the gate electrodes150may extend in the y direction.

Each of the gate electrodes150may serve as gates of the ground selection transistor GST, the memory cell transistors MC1, MC2, MC3, and MC4, and the string selection transistor SST. The gate electrodes150may be commonly connected to each of the memory cell strings11adjacent to the gate electrodes150. The gate electrode156of the string selection transistor SST may be connected to the string selection line SSL (refer toFIG. 1). The gate electrodes152,153,154, and155of the memory cell transistors MC1, MC2, MC3, and MC4may be connected to the wordlines WL1to WLn (refer toFIG. 1). The gate electrode151of the ground selection transistor GST may be connected to the ground selection line GSL (refer toFIG. 1). The first gate electrode151may be thicker than each of the other gate electrodes (second gate electrodes)152to156.

The gate electrodes150may include a metallic layer, for example, tungsten (W). The gate electrodes150may further include a diffusion barrier, and the diffusion barrier may include, for example, tungsten nitride (WN), tantalum nitride (TaN), and/or titanium nitride (TiN).

The gate dielectric layer140may be disposed between the channel region130and the gate electrodes150. In an exemplary embodiment of the inventive concept, the gate dielectric layer140may include, for example, one selected from an oxide-nitride-oxide (ONO) layer, an oxide-nitride-alumina (ONA) layer, and an oxide-nitride-oxide-alumina (ONOA) layer.

The gate dielectric layer140may include a tunneling insulating layer, a charge storage layer, and a blocking insulating layer, which are sequentially stacked on the channel region130in this stated order, and detailed descriptions thereof will be given later with reference toFIG. 3.

The interlayer insulating layers161to167(160) may be disposed between the gate electrodes150. In a similar manner to the gate electrodes150, the interlayer insulating layers160may be separate from each other in the z direction, and each of the interlayer insulating layers160may extend in the y direction. A side surface of each of the interlayer insulating layers160may contact the channel region130. In an exemplary embodiment of the inventive concept, the interlayer insulating layers160may include silicon oxide or silicon nitride.

The first interlayer insulating layer161, which is the lowermost layer of the interlayer insulating layers160, may be very thin. The first interlayer insulating layer161may be thinner than each of the second interlayer insulating layers162to167. The first interlayer insulating layer161may include a material which is the same as that of the second interlayer insulating layers162to167above the first interlayer insulating layer161, or may include a material which is different from that of the second interlayer insulating layers162to167.

In an exemplary embodiment of the inventive concept, the first interlayer insulating layer161may be a kind of buffer layer, may include a middle temperature oxide (MTO) layer, and may insulate the gate electrode151of the ground selection transistor GST from the substrate101.

Thickness of each of the interlayer insulating layers160may have various modifications of the one illustrated inFIGS. 2A and 2B, and the number of layers included in the interlayer insulating layers160may also be variously modified.

An upper insulating layer181may be formed on the second interlayer insulating layer167. A top surface of the upper insulating layer181may be located at substantially the same level as a top surface of the common source line172.

A common source line buried insulating layer183covering at least a region of the top surface of the common source line172may be formed on the upper insulating layer181. The common source line buried insulating layer183may be located between the common source line172extending in the y direction and the bitline193extending in the x direction above the common source line172, and may serve as a device isolation layer electrically isolating the common source line172and the bitline193.

In an exemplary embodiment of the inventive concept, the upper insulating layer181or the common source line buried insulating layer183may include a material which is the same as that of the interlayer insulating layers160or may include a material which is different from that of the interlayer insulating layers160.

The bitline193extending in the x direction and including line patterns may be formed on the common source line buried insulating layer183, and may be electrically connected to the conductive layer190via the bitline contact plug195penetrating the upper insulating layer181and the common source line buried insulating layer183.

Although it is illustrated inFIGS. 2A and 2Bthat the memory cell transistors MC1, MC2, MC3, and MC4are arranged as four, this is an example, and a larger or smaller number of memory cells may be arranged according to the capacity of the semiconductor memory device100.

In an exemplary embodiment of the inventive concept, the string selection transistor SST and the ground selection transistor GST may have structures which are different from those of the memory cell transistors MC1, MC2, MC3, and MC4.

The channel region130, the gate dielectric layer140, and/or the filling insulating layer175in each of the memory cell strings11in the present exemplary embodiment of the inventive concept may have bulb-type cross-section structures as illustrated inFIG. 2B. For example, a separation distance140W1between side walls of the gate dielectric layer140in the x direction in a portion (region G1ofFIG. 2B) adjacent to the gate electrode151of the ground selection transistor GST may be greater than a separation distance140W2between side walls of the gate dielectric layer140in the x direction in a portion (region G2ofFIG. 2B) adjacent to the other gate electrodes152,153,154,155, and156. That is, the width of each of the memory cell strings11in the x direction in a region which contacts the first gate electrode151may be greater than the width of each of the memory cell strings11in the x direction in a region which contacts the other gate electrodes152,153,154,155, and156. When the memory cell strings11are circular columns as shown inFIG. 2B, the separation distance between the side walls of the gate dielectric layer140or the width of each of the memory cell strings11may be equivalent to the diameter of the circle.

When each of the memory cell strings11has the structure as described above, a good etching process margin in an etching process (refer toFIG. 6G) for forming the contact portion132of the channel region130may be sufficiently obtained.

FIG. 3is an enlarged view of region A ofFIG. 2B. InFIG. 3, elements that are the same as those inFIGS. 1 to 2Bare designated by the same reference numerals, and a repeated description thereof is omitted for simplification.

InFIG. 3, the channel region130, which may be used as a channel of each of the memory cell strings11(refer toFIG. 2B), is illustrated. The filling insulating layer175may be disposed on a left side surface of the channel region130illustrated inFIG. 3, that is, on a left side wall of the second channel layer130b. The gate dielectric layer140may be disposed on a right side surface of the channel region130, that is, on a right side wall of the first channel layer130a.

The gate dielectric layer140may have a structure including a tunneling insulating layer142, a charge storage layer144, and a blocking insulating layer146, which are sequentially stacked on the right side wall of the first channel layer130ain this stated order. The first blocking insulating layer146may be between the charge storage layer144and the first gate electrode151or the second gate electrodes152to156.

The tunneling insulating layer142may allow charges to tunnel to the charge storage layer144through the process of Fowler-Nordheim (F-N) tunneling. The tunneling insulating layer142may be a single layer or complex layer including, for example, one or more selected from silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), hafnium oxide (HfOx), hafnium silicon oxide (HfSixOy), aluminum oxide (AlxOy), and zirconium oxide (ZrOx).

The charge storage layer144may be a charge trapping layer or a floating gate conductive layer. When the charge storage layer144is a floating gate conductive layer, the charge storage layer144may be formed by depositing polysilicon using chemical vapor deposition (CVD), for example, low pressure chemical vapor deposition (LPCVD) with Si2H6and PH3gases. When the charge storage layer144is a charge trapping layer, the charge storage layer144may include one or more selected from silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), hafnium oxide (HfOx), zirconium oxide (ZrOx), tantalum oxide (TaxOy), titanium oxide (TiOx), hafnium aluminum oxide (HfAlxOy), hafnium tantalum oxide (HfTaxOy), hafnium silicon oxide (HfSixOy), aluminum nitride (AlxNy), and aluminum gallium nitride (AlGaxNy).

In an exemplary embodiment of the inventive concept, the charge storage layer144may include quantum dots or nano crystals. In this regard, the quantum dots or the nano crystals may include a conductor such as particles of metal or semiconductor.

The blocking insulating layer146may include one or more selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a higher dielectric constant than that of an oxide layer.

In an exemplary embodiment of the inventive concept, the blocking insulating layer146may be a material having a dielectric constant higher than that of the tunneling insulating layer142. For example, the blocking insulating layer146may include at least one of aluminum oxide (AlxOy), tantalum oxide (TaxOy), titanium oxide (TiOx), yttrium oxide (YxOy), zirconium oxide (ZrOx), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfOx), hafnium silicon oxide (HfSixOy), lanthanum oxide (LaxOy), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (PrxOy).

The gate electrode152may be disposed on a right side surface of the gate dielectric layer140. Interlayer insulating layers162and163may be disposed, respectively, on and under the gate electrode152.

FIG. 4is a cross-sectional view of a non-volatile memory device200according to an exemplary embodiment of the inventive concept. InFIG. 4, elements that are the same as those inFIGS. 1 to 3are designated by the same reference numerals, and a repeated description thereof is omitted for simplification.

Referring toFIG. 4, the non-volatile memory device200may include a plurality of memory cell strings21, the gate electrodes150, the insulating layers160,181, and183, the common source line structure170, the bitline193, and the bitline contact plug195on the substrate101.

The non-volatile memory device200may have a structure substantially the same as or similar to the structure of the non-volatile memory device100described with reference toFIGS. 2A and 2B, except the structure of the memory cell strings21shown in the cross-sectional view. Hereinafter, structural differences of the memory cell strings21will be mainly described for simplification.

Each of the memory cell strings21may include a channel region230, a gate dielectric layer240, and a filling insulating layer275; and the ground selection transistor GST, the memory cell transistors MC1, MC2, MC3, and MC4, and the string selection transistor SST are disposed along side walls of the gate dielectric layer240.

The channel region230and/or the gate dielectric layer240in each of the memory cell strings21in a portion (region G3ofFIG. 4) of the ground selection transistor GST, that is adjacent to the gate electrode151, may have a structure in which a separation distance between lower side walls is greater than that between upper side walls. For example, a separation distance240W1between side walls of the gate dielectric layer240in the x direction in a portion adjacent to or contacting the first interlayer insulating layer161may be greater than a separation distance240W2between side walls of the gate dielectric layer240in the x direction in a portion adjacent to or contacting the second interlayer insulating layer162. Accordingly, a good etching process margin in an etching process (refer toFIG. 6G) for forming a contact portion232of the channel region230may be sufficiently obtained.

FIG. 5Ais a cross-sectional view of a non-volatile memory device300according to an exemplary embodiment of the inventive concept.FIG. 5Bis an enlarged view of region B ofFIG. 5A. InFIGS. 5A and 5B, elements that are the same as those inFIGS. 1 to 4are designated by the same reference numerals, and a repeated description thereof is omitted for simplification.

Referring toFIGS. 5A and 5B, the non-volatile memory device300may include a plurality of memory cell strings31including a first blocking insulating layer346, a second blocking insulating layer348, a plurality of gate electrodes350, the insulating layers160,181, and183, the common source line structure170, the bitline193, and the bitline contact plug195.

The non-volatile memory device300may have a structure substantially the same as or similar to the structure of the non-volatile memory device100described with reference toFIGS. 2A and 2B, except that the non-volatile memory device300further includes the second blocking insulating layer348. Hereinafter, the second blocking insulating layer348will be mainly described for simplification.

A gate dielectric layer340may have a structure including a tunneling insulating layer342, a charge storage layer344, and the first blocking insulating layer346, which are sequentially stacked on the right side wall of the first channel layer130ain this stated order. The tunneling insulating layer342, the charge storage layer344, and the first blocking insulating layer346may have structures substantially the same as or similar to the structures of the tunneling insulating layer142, the charge storage layer144, and the blocking insulating layer146, respectively, which have been described with reference toFIGS. 2A and 2B.

The second blocking insulating layer348may contact a side wall of the first blocking insulating layer346in each region between the interlayer insulating layers161to167(160). That is, the second blocking insulating layer348may cover lateral opening portions T1and T2(refer toFIG. 7B) defined between the interlayer insulating layers160. In an exemplary embodiment of the inventive concept, the second blocking insulating layer348may include a material which is the same as that of the first blocking insulating layer346, but is not limited thereto.

The lateral opening portions T1and T2after the second blocking insulating layer348is formed may be filled with the gate electrodes351to356(350). The gate electrodes350may have a structure substantially the same as or similar to the structure of the gate electrodes150described with reference toFIGS. 2A and 2B, except that the gate electrodes350contact the second blocking insulating layer348.

In the case where the second blocking insulating layer348contacting the side wall of the first blocking insulating layer346is additionally formed as in the present exemplary embodiment of the inventive concept, although a portion of the first blocking insulating layer346is damaged in a pullback etching process for forming the lateral opening portions T1and T2, which will be described later with reference toFIGS. 6M and 6N, the damaged portion may be repaired by the second blocking insulating layer348.

FIGS. 6A to 6Uare cross-sectional views illustrated according to a process sequence in order to describe a method of manufacturing a non-volatile memory device, according to an exemplary embodiment of the inventive concept. InFIGS. 6A to 6U, elements that are the same as those inFIGS. 1 to 5Bare designated by the same reference numerals, and a repeated description thereof is omitted for simplification.

Referring toFIG. 6A, the interlayer insulating layers161to167(160) and a plurality of sacrificial layers111and113to117(110) may be alternately stacked on the substrate101. As illustrated inFIG. 6A, the interlayer insulating layers160and the sacrificial layers110may be alternately stacked on the substrate101, with the first interlayer insulating layer161stacked first on the substrate101.

Second sacrificial layers113to117may include a material having etch selectivity with respect to the interlayer insulating layers160. For example, the second sacrificial layers113to117may include a material which may cause the second sacrificial layers113to117to be etched with a higher etch rate than that of the interlayer insulating layers160with respect to a predetermined etchant. That is, the second sacrificial layers113to117may include a material which may cause the second sacrificial layers113to117to be etched while minimizing etching of the interlayer insulating layers160with respect to the predetermined etchant. For example, the interlayer insulating layers160may include at least one of a silicon oxide layer and a silicon nitride layer; and the second sacrificial layers113to117may include one selected from a silicon layer, a silicon oxide layer, silicon carbide and a silicon nitride layer, which may be another material different from the material included in the interlayer insulating layers160and having etch selectivity with respect to the interlayer insulating layers160.

A first sacrificial layer111may include a material having etch selectivity with respect to the interlayer insulating layers160and not having etch selectivity with respect to the second sacrificial layers113to117above the first sacrificial layer111. For example, the first sacrificial layer111may include a material having a lower etch rate than that of the second sacrificial layers113to117with respect to a first etchant and having a higher etch rate than that of the interlayer insulating layers160with respect to a second etchant. For example, when the second sacrificial layers113to117are etched using the first etchant, etching of the first sacrificial layer111and the interlayer insulating layers160may be minimized, and when the first sacrificial layer111is etched using the second etchant, etching of the interlayer insulating layers160may be minimized. In an exemplary embodiment of the inventive concept, the first sacrificial layer111may include polysilicon.

In an exemplary embodiment of the inventive concept, not all thicknesses of the interlayer insulating layers160may be the same. The first interlayer insulating layer161, which is the lowermost layer of the interlayer insulating layers160, may be very thin. The first interlayer insulating layer161may include a material which is the same as that of the second interlayer insulating layers162to167above the first interlayer insulating layer161or may include a material which is different from that of the second interlayer insulating layers162to167. Even when the first interlayer insulating layer161includes a material which is different from that of the second interlayer insulating layers162to167, etch selectivity with respect to the sacrificial layers110may be the same as described above. The first interlayer insulating layer161may be a kind of buffer layer and may include an MTO layer.

Thicknesses of the interlayer insulating layers160and the sacrificial layers110may have various modifications of those illustrated inFIG. 6A. For example, although it is illustrated inFIG. 6Athat the first sacrificial layer111is thicker than each of the second sacrificial layers113to117, the first sacrificial layer111and each of the second sacrificial layers113to117may have substantially the same thickness. In addition, the number of layers included in the interlayer insulating layers160and the sacrificial layers110may be variously modified.

Referring toFIG. 6B, a first etching process of forming first middle opening portions Ta′ penetrating the second interlayer insulating layers162to167and the second sacrificial layers113to117which are alternately stacked, and exposing a portion of the first sacrificial layer111, may be performed.

The first etching process may be performed by forming a predetermined mask pattern for defining a position of the first middle opening portions Ta′ on the interlayer insulating layers160and the sacrificial layers110which are alternately stacked, and using an etchant which may etch the second interlayer insulating layers162to167and the second sacrificial layers113to117together by using the mask pattern as an etching mask.

The first etching process may be an anisotropic etching process. For example, the first etching process may be any one of physical etching such as sputter etching, chemical etching such as reactive radical etching, and physicochemical etching such as reactive ion etching (RIE), magnetically enhanced RIE (MERIE), transformer coupled plasma (TCP) etching, or inductively coupled plasma (ICP) etching.

In the first etching process, the first sacrificial layer111may serve as an etch stopper. Accordingly, as illustrated inFIG. 6B, a top surface of the first sacrificial layer111may be exposed.

In an exemplary embodiment of the inventive concept, an upper region of the first sacrificial layer111may be removed during the first etching process, and thus, the first sacrificial layer111after the first etching process being performed may have a recess111R1.

Referring toFIG. 6C, a second etching process of forming a first opening portion Ta by etching the first sacrificial layer111exposed via a first middle opening portion Ta′ may be performed.

First opening portions Ta may have a plan view structure having a shape of holes extending in the z direction. However, a structure of the first opening portions Ta is not limited to the holes. That is, the first opening portions Ta may have one or more forms according to the structure of a channel region to be formed. Also, the first opening portions Ta may be isolated regions spaced apart from each other in the x and y directions in a plan view.

The second etching process may be an isotropic etching process in which an etchant different from the etchant used to etch upper layers113to117and162to167is used. For example, the second etching process may be performed by using an etchant having a low etch rate with respect to the upper layers113to117and162to167and the first interlayer insulating layer161and having a high etch rate with respect to the first sacrificial layer111.

Through the second etching process, a top surface of the first interlayer insulating layer161may be exposed via the first opening portion Ta. In an exemplary embodiment of the inventive concept, an upper portion of the first interlayer insulating layer161may be removed by the second etching process.

As the second etching process is performed with isotropic etching, the first opening portion Ta may have a bulb-type cross-section structure, as illustrated inFIG. 6C. That is, a width Ta_W1of the first opening portion Ta measured in the x direction in a portion (region A1ofFIG. 6C) that is adjacent to the first sacrificial layer111may be greater than a width Ta_W2of the first opening portion Ta measured in the x direction in a portion (region A2ofFIG. 6C) that is adjacent to the second sacrificial layers113to117and the second interlayer insulating layers162to167.

In an exemplary embodiment of the inventive concept, the second etching process may be, but is not limited thereto, a wet etch process, a chemical dry etch (CDE) process, a dry gas phase etch (GPE) process, or the like. As such, during the second etching process, the first interlayer insulating layer161may remain and thus prevent the substrate101from being exposed by the first opening portion Ta, thereby lowering distribution of the first opening portions Ta. Further, as the second etching process is performed with isotropic etching, the first opening portion Ta may have a bulb-type cross-section structure, and accordingly, a good etching process margin in an etching process (refer toFIG. 6G) for forming the contact portion132of the channel region130, which is a subsequent process, may be sufficiently obtained.

Referring toFIG. 6D, the gate dielectric layer140uniformly covering interior walls and a bottom surface of each of the first opening portions Ta may be formed. As described above with reference toFIG. 3, the gate dielectric layer140may include the blocking insulating layer146(refer toFIG. 3), the charge storage layer144(refer toFIG. 3), and the tunneling insulating layer142(refer toFIG. 3). Accordingly, the blocking insulating layer146, the charge storage layer144, and the tunneling insulating layer142may be stacked in the first opening portions Ta in this stated order.

As described above, each of the first opening portions Ta exposes the top surface of the first interlayer insulating layer161, and accordingly, a bottom surface of the gate dielectric layer140may contact the top surface of the first interlayer insulating layer161.

In an exemplary embodiment of the inventive concept, each of the blocking insulating layer146, the charge storage layer144, and the tunneling insulating layer142may be formed by using, for example, a CVD process, a physical vapor deposition (PVD) process, a metal organic CVD (MOCVD) process, an atomic layer deposition (ALD) process, a metal organic ALD (MOALD) process, or the like, but is not limited thereto.

Referring toFIG. 6E, the first channel layer130amay be formed on the gate dielectric layer140. The first channel layer130amay include a semiconductor material such as polysilicon or single crystalline silicon. The semiconductor material may not be doped or may include p-type or n-type impurities. In an exemplary embodiment of the inventive concept, the first channel layer130amay be formed by using a process such as an ALD process or a CVD process.

Referring toFIG. 6F, a spacer layer135may be formed on the first channel layer130a.In an exemplary embodiment of the inventive concept, the spacer layer135may include, for example, a silicon oxide layer or a silicon nitride layer and may be formed by using ALD or CVD. The spacer layer135may be used as a mask for etching bottom surfaces of the first channel layer130aand the gate dielectric layer140, and may prevent the first channel layer130afrom being damaged in the etching process.

The spacer layer135in the present exemplary embodiment of the inventive concept covers the entire region of the first channel layer130a, but is not limited thereto. For example, the spacer layer135may cover only side walls of the first channel layer130a, which is different from that illustrated inFIG. 6F.

Referring toFIG. 6G, the spacer layer135may be used as an etching mask to perform anisotropic etching on both bottom surfaces of the first channel layer130aand the gate dielectric layer140, and on the first interlayer insulating layer161. A contact hole101H exposing the substrate101may be formed by the anisotropic etching process. As illustrated inFIG. 6G, in the anisotropic etching process, the substrate101may be overly etched and recessed to have a predetermined depth. As the substrate101is recessed as such, a contact region of the second channel layer130b(refer toFIG. 2B), which is to be filled in the recess by a subsequent process, and the substrate101may be larger, and thus, channel resistance may be smaller.

Referring toFIG. 6H, the spacer layer135remaining on side walls of the first channel layer130amay be removed. The spacer layer135may be removed, for example, through a wet cleaning process, or the like. The wet cleaning process may be performed by using, for example, a mixed solution of ammonia, peroxide and fluoride. Removing the spacer layer135may be performed by a separate process or by a cleaning process performed before forming the second channel layer130b, which will be described below.

Referring toFIG. 6I, the second channel layer130bmay be formed on the first channel layer130aexposed after the removal of the spacer layer135. The first and second channel layers130aand130bmay be defined as the channel region130. The second channel layer130bmay fill the contact hole101H, and accordingly, the channel region130may include the contact portion132. The channel region130may be electrically connected to the substrate101via the contact portion132. The second channel layer130bmay include a material which is the same as that of the first channel layer130a, and may include, for example, a semiconductor material such as polysilicon or single crystalline silicon.

Referring toFIG. 6J, the first opening portion Ta, which remains after the channel region130is formed, may be filled with the filling insulating layer175. Optionally, before the filling insulating layer175is formed, a hydrogen annealing operation in which the structure including the channel region130is heat-treated in a gas atmosphere including hydrogen or deuterium may be further performed. By performing the hydrogen annealing operation, many portions of crystal defects that exist in the channel region130may be repaired.

To remove unnecessary semiconductor materials and insulating materials which cover the uppermost second interlayer insulating layer167, a planarization process, for example, chemical mechanical polishing (CMP) or an etch-back process, may be performed until a top surface of the second interlayer insulating layer167is exposed.

When the etch-back process is performed, as illustrated inFIG. 6J, upper portions of the channel region130, the gate dielectric layer140, and the filling insulating layer175may be removed, and thus, a top surface of each of the channel region130, the gate dielectric layer140, and the filling insulating layer175may be located at a lower level than the top surface of the second interlayer insulating layer167. Thereafter, the conductive layer190covering the top surface of each of the channel region130, the gate dielectric layer140, and the filling insulating layer175may be formed. The conductive layer190may act as a drain region of the string selection transistor SST (refer toFIG. 2B). In an exemplary embodiment of the inventive concept, the conductive layer190may include polysilicon doped with n-type impurities, such as phosphorus (P), arsenic (As), or antimony (Sb).

As the filling insulating layer175and the conductive layer190are formed as described above, the memory cell strings11may be completed.

Referring toFIG. 6K, after the conductive layer190is formed, the upper insulating layer181covering top surfaces of the conductive layer190and the second interlayer insulating layer167may be formed. The upper insulating layer181may protect the conductive layer190from damage, contamination, or the like, which may be caused by subsequent processes for forming the common source line structure170.

Referring toFIG. 6L, anisotropic etching may be performed on the upper insulating layer181, the interlayer insulating layers160, and the second sacrificial layers113to117between the memory cell strings11to form a second opening portion Tb exposing the first sacrificial layer111. As in the first etching process described with reference toFIG. 6B, the first sacrificial layer111may serve as an etch stopper when the second opening portion Tb is formed.

In an exemplary embodiment of the inventive concept, an upper region of the first sacrificial layer111may be removed during a process of forming the second opening portion Tb, and thus, the first sacrificial layer111may have a recess111R2.

The second opening portion Tb may extend in the y direction. Although only one second opening portion Tb is illustrated inFIG. 6L, second opening portions Tb may respectively be formed between the memory cell strings11that are disposed adjacent to each other in the x direction.

Referring toFIG. 6M, the second sacrificial layers113to117(refer toFIG. 6L) exposed via the second opening portion Tb may be removed to form a plurality of first lateral opening portions T1defined between the interlayer insulating layers160. A process of removing the second sacrificial layers113to117may be performed, for example, through a pullback etching process.

Side surfaces of the gate dielectric layer140may be partially exposed via the first lateral opening portions T1.

The first lateral opening portions T1may be formed by horizontally etching the second sacrificial layers113to117with an etchant having etch selectivity with respect to the interlayer insulating layers160and the first sacrificial layer111. For example, when the second sacrificial layers113to117are silicon nitride layers, the first sacrificial layer111is a polysilicon layer, and the interlayer insulating layers160are silicon oxide layers, the etching process may be performed using an etchant including phosphoric acid. The etching process may be, for example, a wet etching process, a CDE process, a dry GPE process, or the like. Such an etching process may be an isotropic etching process.

Referring toFIG. 6N, the first sacrificial layer111(refer toFIG. 6M) exposed via the second opening portion Tb may be removed to form second lateral opening portions T2defined between the first interlayer insulating layer161and the second interlayer insulating layer162. A process of removing the first sacrificial layer111may be performed, for example, through a pullback etching process.

The second lateral opening portions T2may be formed by horizontally etching the first sacrificial layer111with an etchant having etch selectivity with respect to the interlayer insulating layers160. For example, when the first sacrificial layer111is a polysilicon layer, and the interlayer insulating layers160are silicon oxide layers, the etching process may be performed by using an etchant including halogen-containing reaction gas. The etching process may be, for example, a wet etching process, a CDE process, a dry GPE process, or the like. Such an etching process may be an isotropic etching process.

Although, in the present exemplary embodiment of the inventive concept, the first sacrificial layer111and the second sacrificial layers113to117are removed by separate etching processes, the first sacrificial layer111and the second sacrificial layers113to117may be removed simultaneously by a single etching process.

Even after the first sacrificial layer111and the second sacrificial layers113to117are removed, the substrate101may not be exposed by the lateral opening portions T1and T2as the first interlayer insulating layer161covers the top surface of the substrate101. As the substrate101is not exposed to a pullback etching process for removing the first sacrificial layer111and the second sacrificial layers113to117, the substrate101may be prevented from being damaged during the pullback etching process.

Referring toFIG. 6O, the second opening portion Tb and the lateral opening portions T1and T2may be filled with a conductive material. The conductive material may be metal, for example, tungsten. After the conductive material is filled therein, the conductive material may be removed from the second opening portion Tb so that the conductive material remains only in the lateral opening portions T1and T2. Accordingly, respective gate electrodes151to156(150) of the ground selection transistor GST, the memory cell transistors MC1, MC2, MC3, and MC4, and the string selection transistor SST may be formed, wherein the respective gate electrodes151to156(150) including the conductive material remain in the lateral opening portions T1and T2.

As all of the gate electrodes150include a metallic layer such as tungsten, resistance of the gate electrodes150may be remarkably smaller compared to when the gate electrodes150include polysilicon. Particularly, as the gate electrode151of the ground selection transistor GST includes a metallic layer, operating characteristics of the ground selection transistor GST may be improved.

In an exemplary embodiment of the inventive concept, a process of removing the conductive material in the second opening portion Tb may be an anisotropic etching process or an isotropic etching process. For example, the process of removing the conductive material in the second opening portion Tb may be a wet etching process in which an etchant having a relatively high selective etch ratio with respect to the conductive material and a relatively low selective etch ratio with respect to the interlayer insulating layers160is used. In this case, as the conductive material in the second opening portion Tb is preferentially exposed to the etchant, only the conductive material in the second opening portion Tb may be removed with the conductive material in the lateral opening portions T1and T2remained by adjusting time of the wet etching process or the like. However, unlike that illustrated inFIG. 6O, in addition to the removal of the conductive material from the second opening portion Tb during the wet etching process, a portion of the conductive material in the lateral opening portions T1and T2that is adjacent to the second opening portion Tb may also be removed.

Referring toFIG. 6P, impurities may be injected into the substrate101via the second opening portion Tb to form the first impurity region105a. In an exemplary embodiment of the inventive concept, the first impurity region105amay be a low-concentration impurity region.

Referring toFIG. 6Q, an insulating layer174xmay be formed on interior walls of the second opening portion Tb and a top surface of the upper insulating layer181. The insulating layer174xmay be formed by using, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

Referring toFIG. 6R, an anisotropic etching process may be performed on the insulating layer174x(refer toFIG. 6Q) to form the common source line spacer174. The first interlayer insulating layer161located in a third opening portion Tc defined by side walls of the common source line spacer174may be removed by the etching process, and thus, the first impurity region105ain the substrate101may be exposed.

Referring toFIG. 6S, impurities may be injected into the substrate101via the third opening portion Tc to form the second impurity region105b. In an exemplary embodiment of the inventive concept, the second impurity region105bmay be a high-concentration impurity region. The impurity region105including the first impurity region105aand the second impurity region105bmay serve as a source region.

Referring toFIG. 6T, a conductive layer, such as tungsten, tantalum, cobalt, tungsten silicide, tantalum silicide, cobalt silicide, etc., may be filled in the third opening portion Tc, and then, a planarization process may be performed on the conductive layer until the top surface of the upper insulating layer181is exposed to form the common source line172. The common source line172may be connected to the impurity region105of the substrate101. The common source line172and the common source line spacer174may constitute the common source line structure170.

Referring toFIG. 6U, the common source line buried insulating layer183covering the common source line structure170and the upper insulating layer181may be formed, and then, the bitline contact plug195penetrating the common source line buried insulating layer183and the upper insulating layer181and contacting the conductive layer190may be formed through a photolithography process and an etching process. Thereafter, the bitline193extending in the x direction on the common source line buried insulating layer183and connected to bitline contact plugs195may be formed.

FIGS. 7A to 7Dare cross-sectional views illustrated according to a process sequence in order to describe a method of manufacturing a non-volatile memory device, according to an exemplary embodiment of the inventive concept. InFIGS. 7A to 7D, elements that are the same as those inFIGS. 1 to 6Uare designated by the same reference numerals, and a repeated description thereof is omitted for simplification.

Referring toFIG. 7A, a structure including the first lateral opening portions T1and the second lateral opening portions T2defined between the interlayer insulating layers160may be prepared by processes substantially the same as or similar to those described with reference toFIGS. 6A to 6N.

The gate dielectric layer340may have a structure including the tunneling insulating layer342, the charge storage layer344, and the first blocking insulating layer346, which are sequentially stacked on a side wall of the first channel layer130ain this stated order, as described above with reference toFIG. 5B.

Referring toFIG. 7B, the second blocking insulating layer348conformally covering the second opening portion Tb, the first lateral opening portions T1, and the second lateral opening portions T2may be formed. Accordingly, the second blocking insulating layer348comes into contact with a side wall of the gate dielectric layer340, particularly, the first blocking insulating layer346(refer toFIG. 5B), that is exposed by the first lateral opening portions T1and the second lateral opening portions T2.

In the case where the second blocking insulating layer348contacting the side wall of the first blocking insulating layer346is additionally formed as such, although a portion of the first blocking insulating layer346is damaged in a pullback etching process for forming the lateral opening portions T1and T2described with reference toFIG. 7A, the damaged portion may be repaired by the second blocking insulating layer348.

The second blocking insulating layer348may include one or more selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a higher dielectric constant than that of an oxide layer.

The second blocking insulating layer348may include a material which is the same as that of the first blocking insulating layer346, but is not limited thereto.

Referring toFIG. 7C, in the lateral opening portions T1and T2after the second blocking insulating layer348is formed, the gate electrodes351to356(350) may be formed. For example, first, the lateral opening portions T1and T2after the second blocking insulating layer348is formed may be filled with a conductive material. The conductive material may be metal, for example, tungsten. After the conductive material is filled therein, the conductive material in the second opening portion Tb may be removed so that only the conductive material in the lateral opening portions T1and T2may remain, and thus, the gate electrodes350may be formed. In this regard, the second blocking insulating layer348in the second opening portion Tb may also be removed.

In an exemplary embodiment of the inventive concept, a process of removing the conductive material and the second blocking insulating layer348in the second opening portion Tb may be an anisotropic etching process or an isotropic etching process. For example, the process of removing the conductive material and the second blocking insulating layer348in the second opening portion Tb may be a wet etching process in which an etchant having a relatively high selective etch ratio with respect to the conductive material and the second blocking insulating layer348and having a relatively low selective etch ratio with respect to the interlayer insulating layers160is used. In this case, as the conductive material and the second blocking insulating layer348in the second opening portion Tb are preferentially exposed to the etchant, only the conductive material and the second blocking insulating layer348in the second opening portion Tb may be removed with the conductive material and the second blocking insulating layer348in the lateral opening portions T1and T2remained by adjusting time of the wet etching process or the like. However, unlike that illustrated inFIG. 7C, in addition to the removal of the conductive material and the second blocking insulating layer348from the second opening portion Tb during the wet etching process, portions of the conductive material and the second blocking insulating layer348in the lateral opening portions T1and T2that are adjacent to the second opening portion Tb may also be removed.

Referring toFIG. 7D, the impurity region105may be formed in the substrate101, and the upper insulating layer181, the common source line structure170, the common source line buried insulating layer183, the bitline contact plug195, and the bitline193may be formed to complete manufacturing of the non-volatile memory device300.

FIGS. 8A to 8Care cross-sectional views illustrated according to a process sequence in order to describe a method of manufacturing a non-volatile memory device, according to an exemplary embodiment of the inventive concept. InFIGS. 8A to 8C, elements that are the same as those inFIGS. 1 to 7Dare designated by the same reference numerals, and a repeated description thereof is omitted for simplification.

FIGS. 8A to 8Cillustrate a modified embodiment of processes described with reference toFIGS. 6E to 6G, and a description of processes before and after processes which will be described with reference toFIGS. 8A to 8Cwill be omitted.

Referring toFIG. 8A, the first interlayer insulating layer161, the second interlayer insulating layers162to167including the first opening portions Ta, and the sacrificial layers111to117(110) may be formed on the substrate101, and a gate dielectric layer440and a first channel layer430auniformly covering interior walls and a bottom surface of each of the first opening portions Ta may be sequentially formed. Respective formation processes of the interlayer insulating layers160, the sacrificial layers110, the gate dielectric layer440, and the first channel layer430amay be substantially the same as or similar to the processes described with reference toFIGS. 6A to 6E.

Referring toFIG. 8B, a contact hole401H exposing the substrate101is formed by etching the gate dielectric layer440and the first channel layer430aon bottom surfaces of the first opening portions Ta. The etching process may include performing anisotropic etching on the bottom surface of the first channel layer430a, and etching the gate dielectric layer440by using the first channel layer430aas an etching mask. The substrate101may be overly etched and recessed to have a predetermined depth.

Referring toFIG. 8C, a second channel layer430bmay be formed on the first channel layer430a. The first and second channel layers430aand430bmay be defined as a channel region430. The contact hole401H may be filled with the second channel layer430b, and accordingly, the channel region430may include a contact portion432. The channel region430may be electrically connected to the substrate101via the contact portion432. The second channel layer430bmay include a material which is the same as that of the first channel layer430a, and may include, for example, a semiconductor material such as polysilicon or single crystalline silicon.

In the present exemplary embodiment of the inventive concept, as the contact hole401H is formed by using the first channel layer430awithout using a spacer, the contact portion432may have a larger width. Accordingly, a contact region of the channel region430and the substrate101may be larger, and thus, channel resistance may be smaller.