Apparatus and method for a low-voltage supply low-power variable gain amplifier

A low-voltage supply low-power variable gain amplifier is shown that includes an input control circuit for receiving input signals, a variable gain amplifier (VGA) coupled to the input control circuit, and a circuit output terminal. A differential transconductor is interposed between the input control circuit and the VGA. The VGA amplification of the differential transconductor output is controlled by a gain control voltage signal. A differential amplifier is interposed between the input control circuit and the differential transconductor, where the differential amplifier receives and amplifies the input signal to produce an amplified input signal. An output filter is interposed between the VGA and the circuit output terminal.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This patent application is based upon provisional U.S. Patent Application No. 60/472,264 filed May 21, 2003.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a variable gain amplifier circuit.

2. Description of the Related Art

The Variable Gain Amplifier (VGA) is a critical baseband block of modern data communication transceivers. A VGA architecture was first proposed in the 1960s.

A representative example of a conventional VGA is shown inFIG. 1. The VGA10includes an input differential pair gain stage composed of transistors of24and34and resistors40and42. It is biased by transistor38. The amplification stage of the VGA of is comprised of two differential pairs. The first of these pairs consists of resistor26and transistors20and22. Resistor36and transistors30and32form the second pair. The VGA additionally includes resistors12and14to reduce the current flowing through the differential pairs of the amplification stage. In operation, a differential input signal is applied across the differential input pair by connecting the positive input to the base of transistor24and the negative input to the base of transistor34. Applying a differential signal across both differential pairs that comprise the amplification stage controls the variable gain of the VGA. The positive control signal is applied to the base of transistor22and transistor30. The negative control signal is applied to the base of transistor20and transistor32.

The conventional VGA architecture has been kept practically unchanged since its inception until today. It is compact and has both low noise and high input-to-output linearity. Its gain versus control voltage transfer function characteristics are linear when the gain is expressed in decibel units, which makes this VGA the preferred selection in high performance Automatic Gain Control (AGC) systems. It is the de-facto standard against which new VGA architectures are typically compared.

However, this architecture has some limitations and weaknesses. First, it has three stacked bipolar transistors and two resistors between the power supply and ground. Hence, it cannot be used with voltage supplies below ˜3 volts DC. Second, in order to obtain high linearity from input-to-output, the input differential pair stage transistors, transistors24and34as shown inFIG. 1, must be operating linearly. Thus, the current through the input differential pair stage transistors must be large. However, in order to minimize the noise of the circuit, only a small current should flow through the amplification stage containing transistors20,22,30, and32. These conflicting requirements have forced the addition of resistors12and14to the basic architecture in order to divert a significant part of the current away from the quad transistors20,22,30, and32. In other words, the addition of resistors12and14to the circuit introduces inefficiency because a significant amount of power is simply dissipated by resistors12and R814serving no useful purpose other than reducing the current through the actual elements that implement the VGA functionality (e.g. transistors20,22,30, and32and resistors26and36).

For many years these limitations were considered irrelevant. The requirement that the minimum voltage supply be greater than approximately 3 volts DC was almost a non-issue because existing voltage supplies were commonly in the range of 5 to 12 volts DC. Further, the increased power consumption was also negligible because most circuits were ultimately connected to a line supply of current: e.g. a 110/220 volts AC power supply.

However, with the development of portable, battery-operated wireless transceivers (particularly remote wireless sensor networks), limitations on voltage supplies and power consumption are increasingly important. Specifically, the voltage supply has to be as low as possible and the current consumption has to be kept to a minimum in order to prolong the useful lifetime of battery-operated transceivers from a few hours to months or even years.

Since some emerging applications require increased efficiency that cannot be obtained by simply optimizing the conventional VGA, there is a need for new VGA architectures that can meet the requirements of such emerging applications. Accordingly, it is advantageous to use a VGA that provides increased efficiency by consuming minimal current and functioning with a low voltage supply.

SUMMARY OF THE INVENTION

The present invention relates to an apparatus and method for variably amplifying a signal.

An embodiment of low-voltage supply low-power variable gain amplifier circuit, according to the present invention, includes a first amplifier having an input and an output and a transconductor having an input and an output. The circuit further includes a variable gain amplifier having an input coupled to the output of the transconductor, an output and a variable gain control input. The variable gain amplifier is configured such that a gain of the variable gain amplifier is controlled by a signal received at the variable gain control input. The circuit also includes an input control circuit having a first input for receiving a signal to be amplified, a second input electrically coupled to the output of the first amplifier, a first output coupled to the input of the first amplifier, a second output coupled to the input of the transconductor, and a gain control input. The input control circuit is configured to electrically couple the input and first output terminals of the input control circuit responsive to a first signal received at the gain control input corresponding to a high gain mode. The input control circuit is further configured to electrically couple the input and second output terminals of the input control circuit responsive to a second signal received at the gain control input corresponding to a low gain mode. In a further refinement of this embodiment, the input control circuit is further configured to generate a disabling signal at the first output of the input control circuit responsive to the second signal received at the gain control input corresponding to a low gain mode and the first amplifier is further configured to reduce its power supply current draw responsive to the disabling signal output by the input control circuit.

An embodiment of a method for selectively providing high gain amplification and low gain amplification to a received signal, according to the present invention, calls for providing an amplification stage for amplifying the received signal, providing a transconductance stage for transconducting the received signal, and providing a variable gain stage for amplifying the output of the transconductance stage under control of a variable gain control signal. The method also sets forth selectively engaging the amplification stage to amplify the received signal and output the amplified received signal to the transconductance stage responsive to a control signal corresponding to a high gain mode. The method further calls for selectively routing the received signal to the transconductance stage responsive to a control signal corresponding to a low gain mode. In a further refinement of this embodiment, the step of selectively routing the received signal to the transconductance stage responsive to a control signal corresponding to a low gain mode further includes disabling the amplifier stage in the low gain mode.

The features and advantages of the present invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Because of the inherent inefficiencies of the conventional VGA architecture, it is desirable to create an improved VGA that is capable of operating with a low-voltage supply and consumes power at a low rate.

FIG. 2is a functional block diagram illustrating an embodiment of a variable gain circuit, according to the present invention, that is generally applicable to low intermediate frequency (IF) receiver architectures. An input control circuit50is connected to both a differential amplifier stage60and a differential transconductor stage70and permits the variable gain circuit to be switched between a high-gain level and a low-gain level under control of a high-gain/low-gain control signal HG/LG*. As in the standard architecture, a differential input signal is applied to a set of input terminals labeled INP and INN. The input control circuit50receives a differential input signal at the input terminals labeled INP and INN. In addition, the HG/LG* control input signal is also received at the input labeled HG/LG inFIG. 2. The differential amplifier60has a differential input that is connected to the input control circuit50at an output pair labeled INP1and INN1. The input control circuit50also receives the output nodes N8and N9of differential amplifier60.

Under control of the HG/LG* control input signal, input control circuit50determines whether the signal received at input nodes INP and INN is directed through differential amplifier60before being input to differential transconductor70(high-gain mode) or whether the received signal is directed straight to differential transconductor70(low-gain mode).

The differential transconductor70is disposed between a variable gain amplifier (VGA) stage80and the input control circuit50. It has a differential input that is connected to the input control circuit50at an output pair labeled INP2and INN2. The differential transconductor70also has a differential output signal. This differential output signal is referred to as the pre-amplifier output (PAO) and the differential signals at the output terminals of transconductor70are PAOP and PAON. The VGA80is connected to the differential transconductor70. The VGA has a differential input, to which PAOP and PAON, the differential output signal from the differential transconductor70, are applied. The amplification provided by the VGA80is controlled by a differential control signal VCP and VCN, which is typically controlled by an AGC circuit that is not also controlling the differential signal applied to the input control circuit50. An output filter90is coupled with a differential output from VGA80. The voltage amplifier output from VGA80is differential signals VAOP and VAON. A set of input terminals on the output filter90are connected to the output terminals on the VGA80so that the inputs to the output filter90are VAOP and VAON.

The functional blocks illustrated inFIG. 2can be implemented in a variety of ways, as one of ordinary skill in the art would recognize. One exemplary embodiment of a transistor circuit implementation of the functional blocks ofFIG. 2is illustrated inFIG. 3. Input control circuit500ofFIG. 3shows one embodiment of the input control circuit50ofFIG. 2. One way to implement the differential amplifier60inFIG. 2is depicted in the differential amplifier circuit600ofFIG. 3. The differential transconductor70ofFIG. 2can be implemented as shown in the differential transconductor circuit700ofFIG. 3. Implementation of the VGA80ofFIG. 2can be accomplished by use of the VGA circuit800depicted inFIG. 3. Finally, the output filter90inFIG. 2may be realized as the output filter circuit900ofFIG. 3.

In the embodiment of an input control circuit500shown inFIG. 3, the input control circuit500is composed of four pairs of metal-oxide semiconductor (MOS) transistors. A first pair of MOS transistors, PMOS transistor510and NMOS transistor512, controls whether input terminal INP is electrically coupled to input INP1of differential amplifier60under control of low gain signal LG. Similarly, a second pair of MOS transistors, PMOS transistor514and NMOS transistor516, controls whether input terminal INN is electrically coupled to input INN1of differential amplifier60under control of low gain signal LG. When control signal LG is low, then INP and INN are electrically coupled to the inputs INP1and INN1, respectively, of differential amplifier600, which then provides preamplification of the signal received at INP and INN. Conversely, when control signal LG is high, e.g. low-gain mode, then INP and INN are electrically isolated from INP1and INN1and a low supply rail voltage VSSA is applied to INP1and INN1, which turns differential amplifier600off by halting the flow of current through transistors610and612. Transistor620provides the bias current for amplifier600under control of a bias voltage VBB.

Another pair of MOS transistors, PMOS transistors520and522, control whether input INP2of differential transconductor700is electrically coupled to input terminal INP or output node N9of amplifier600under the control of signal HG and LG. Similarly, PMOS transistors524and526, control whether input INN2of differential transconductor700is electrically coupled to input terminal INN or output node N8of amplifier600also under the control of signal HG and LG. When control signal HG is high and control signal LG is low, e.g. high gain mode, then output nodes N9and N8from amplifier600are electrically coupled to inputs INP2and INN2, respectively, of transconductor700. Conversely, when control signal HG is low and control signal LG is high, e.g. low gain mode, then output nodes N9and N8from amplifier600are electrically isolated from transconductor700and input terminals INP and INN are electrically coupled to the inputs INP2and INN2, respectively, of transconductor700.

Thus, in high gain mode, differential amplifier600is electrically inserted into the circuit between input terminals INP and INN and transconductor700to provide pre-amplification. In low gain mode, differential amplifier600is electrically removed from the circuit, and disabled such that no pre-amplification is performed, and the signal received at input terminals INP and INN is diverted directly to the inputs INP2and INN2of transconductor700.

To further describe the differential amplifier circuit600depicted inFIG. 3, a differential input pair of bipolar transistors610and612, are connected at their emitters to a biasing transistor620. The bases of both transistors610and612are connected to the input control circuit500. The collector of transistor610is connected to resistor602, which is also connected to high side supply rail VDDA to provide supply current. Similarly, the collector of612is connected to resistor604, which is also connected to high side supply rail VDDA. In addition, the collector of610is connected to node N8, which is one differential output of amplifier600, and the collector of612is connected to node N9, which is the other differential output of amplifier600. Differential outputs N8and N9are further connected to the input control circuit500.

FIG. 3also illustrates one implementation of a differential transconductor circuit700. The circuit700includes a pair of PMOS transistors710and712, whose gates are the inputs INP2and INN2, respectively, of transconductor700. The gates of both transistors710and712are connected to the input control circuit500. The sources of transistors710and712are connected to the drain of a biasing PMOS transistor720that is controlled by a PMOS biasing voltage VBP. The source of transistor720is connected to high side supply rail VDDA to provide supply current. Transconductor700further includes bipolar transistors722and724, which are separately coupled in series with transistors710and712, respectively. Transistor722is coupled in series with transistor710and is diode connected to form a current mirror that is one differential output PAOP of transconductor700. Transistor722is coupled to a base of transistor824of variable gain amplifier800. Likewise, transistor724is coupled in series with transistor712and is diode connected to form a current mirror that is the other differential output PAON of transconductor700. Transistor724is coupled to a base of transistor822of VGA800. Thus, transistors722and724output the transconducted signal by mirroring their current to transistors824and822, respectively, of VGA circuit800.

The embodiment of the VGA circuit800illustrated inFIG. 3includes the two bipolar transistors822and824that receive the differential output current signal from transconductor700. The VGA circuit800also includes two differential pairs of transistors: a first differential pair having bipolar transistors810and812and a second differential pair having bipolar transistors814and816. Transistor822is coupled in series with the first differential pair and transistor824is coupled is series with the second differential pair. The emitters of transistors810and812are connected to the collector of transistor822. The collector of transistor810is connected to high side supply rail VDDA whereas resistor802is connected between the collector of transistor812and VDDA, such that the collector of transistor812becomes one of the differential outputs VAON of VGA800. Thus, the differential output current from PAON of transconductor700is reflected through transistor822and into differential pair810and812for variable amplification and output to output filter900and output terminal ON.

Similarly, the emitters of transistors814and816are connected to the collector of transistor824. The collector of transistor816is connected to VDDA whereas resistor804is connected between the collector of transistor814and VDDA, such that the collector of transistor814becomes the other differential output VAOP of VGA800. Thus, the differential output current from PAOP of transconductor700is reflected through transistor824and into differential pair814and816for variable amplification and output to output filter900and output terminal OP. The variable amplification of VGA800is controlled by differential variable gain control signals VCP and VCN, which differentially drive the differential pairs. The signal VCP drives the base terminals of transistors812and814, while signal VCN drives the bases of transistors810and816.

Separate stages are used for the differential input signal (INP−INN) and the automatic gain control (AGC) control signal. This eliminates the need to stack three bipolar transistors and two resistors between the high side voltage supply rail VDDA and low side voltage supply rail VSSA. As a result, the 3-volt DC supply voltage limitation is eliminated. Furthermore, since the current through the transistor quad (810,812,814,816) in VGA800can be optimized independently from the current into the differential input pair (610and612) in the differential amplifier circuit600, there is no need to waste part of the current into resistors such as resistors12and14shown inFIG. 1.

In the embodiment of the input control circuit500shown inFIG. 3, MOS transistors are used as switches to control a differential input signal applied to sets of input terminals on the differential amplifier circuit600and on the differential transconductor circuit700. The differential input signal has a positive side INP and a negative side INN. PMOS transistor510and NMOS transistor512are connected in series between INP and VSSA. PMOS transistors520and522are connected in series between INP and N9on the collector of transistor612in the differential amplifier circuit600. PMOS transistor514and NMOS transistor516are connected in series between INN and VSSA. PMOS transistors524and526are connected in series between INN and N8on the collector of transistor610in the differential amplifier circuit600.

The switches are controlled by a signal that indicates whether the circuit should operate in high-gain or low-gain mode. The differential amplifier circuit600has an input INP1that is connected to the drains of transistors510and512. When the input control circuit500is operating in low-gain mode transistor510allows a signal INP1at the base of transistor610in the differential amplifier circuit600to equal the input signal INP. On the other hand, if the input control circuit500is operating in high-gain mode, transistor512will set INP1equal to VSSA. The differential transconductor circuit700has an input INP2at the gate of transistor710. When operating in low-gain mode, transistor520of the input control circuit500will set INP2to INP. However, when in the high-gain mode, the transistor522will set INP2equal to the voltage on N9of the differential amplifier circuit600. The differential amplifier circuit600has an input INN1that is connected to the drains of transistors514and516. When the input control circuit500is operating in low-gain mode, transistor516allows a signal INN1at the base of transistor612in the differential amplifier circuit600to equal VSSA. On the other hand, if the input control circuit500is operating in high-gain mode, transistor514will set INN1equal to the input signal INN.

The differential transconductor circuit700has an input INP2that is connected to the drains of transistors520and522. When the input control circuit500is operating in low-gain mode, transistor510passes the input signal INP directly to the input INP2at the gate of transistor710. When the input control circuit500is operating in high-gain mode, transistor522is on and connects INP2to N9on the differential amplifier600. The differential transconductor circuit700also has an input INN2that is connected to the drains of transistors524and526. When the input control circuit500is operating in low-gain mode, transistor524is on and INN2is equal to the input signal INN. On the other hand, when the input circuit500is operating in high-gain mode, transistor526links INN2to N8on the differential amplifier600.

Due to the input control circuit500, the VGA includes a dual-gain architecture. Weak input signals pass through both the differential amplifier circuit600and the differential transconductor circuit700. Strong input signals, however, are connected directly to the differential transconductor circuit700and bypass the differential amplifier circuit600. For weak input signals, the first two stages of the VGA800, which includes a bipolar differential amplifier circuit600and a metal-oxide semiconductor (MOS) differential transconductor700, are connected in series by setting the digital control voltages to the MOS transistor switches (510,512,520,522,514,516,514, and526) in the input control circuit500to HG=‘1’ and LG=‘0’. In this mode of operation, a high-gain (about 45 dB gain for the example shown later) and a low-noise (˜6 uVrms input referred noise, see example shown later) are obtained, which are the most important parameters for weak signals, and the linearity is fairly good (IIP3of about −20 dBm). On the other hand, for strong input signals, the bipolar differential amplifier circuit600is bypassed by setting the control voltages to the MOS switches (510,512,520,522,514,516,514, and526) in the input control circuit500to HG=‘0’ and LG=‘1’. The input is thus connected directly to the MOS differential transconductor circuit700. Although, the maximum attainable gain is smaller (˜20 dB), the linearity of the MOS differential transconductor circuit700is much better than the linearity of the bipolar differential pair (610and612) in the differential amplifier circuit600. This allows achieving a much higher IIP3(+9 dBm in the example shown later), which is what really matters when the input signal is strong. Since the input signal in this mode of operation is already strong, high gain is not needed.

MOS amplifiers suffer from higher DC offsets and 1/f noise. However, for a typical 1-MHz low-IF receiver architecture, a simple passive highpass filter following the VGA can reduce these problems.FIG. 3includes an embodiment of such a highpass filter900. Capacitors910and920form the filter in conjunction with resistors912,914,922and924. Placing the MOS differential transconductor amplifier700after the bipolar differential amplifier600assures also that the MOS DC offset will not be able to saturate the VGA stage800, since the DC offset is only amplified by the gain of the MOS amplifier720, e.g. ˜20 dB. Moreover, at the frequencies of interest in this embodiment, centered at the IF frequency (1 MHz, in our specific example), the MOS transistors are actually better than the bipolar transistors in terms of noise, since the MOS transistors have one less source of noise to worry about: i.e. they do not have a base resistance. In addition to suppressing the DC offsets and the low-frequency 1/f noise due mainly to the MOS differential transconductor700, the highpass filter900serves another useful task: the common mode output voltage of the core VGA800(without the highpass filter900) varies widely as a function of the differential control voltage v(vcp)−v(vcn) that controls the gain of the VGA800. This may pose a challenge for the circuit following the VGA800, usually an image-reject or lowpass filter, since its amplifiers would need to function properly for a wide range of input common mode voltages. The highpass filter900decouples the common mode output voltage of the core VGA800and sets a constant appropriate value
V_common_mode=0.5*[v(op)+v(on)]
for the next stage, determined by the relative values of the resistors912,914,922, and924inFIG. 3.

The MOS differential pair (transistors710and712) in the differential transconductor circuit700, as well as some of the MOS switches (510,520,522,514,524and528) in the input control circuit500, use native low-threshold p-channel MOS transistors. These transistors are usually available in present day complementary MOS (CMOS) and bipolar CMOS (BICMOS) processes. Native MOS transistors are not used in digital circuits since they typically lead to large leakage currents when the logic gates are supposedly “off”. However, their use in the VGA embodiment described here is safe and is preferable for low voltage supply operation.

Finally, in a wireless transceiver, it is desirable to be able to power the circuit down when it is not in use. The core of the VGA circuit800can be powered down by controlling the current source transistors620and720. The highpass filter900could lead to a small constant DC current unless the path from the power supply to ground through resistor pairs912and914and922and924is closed when the transceiver is powered down. This is the function accomplished by the digital control voltage PDB and the CMOS transistor switches916and926. In power down mode, PDB is set to PDB=‘0’, switching off the transistors916and926, so that no current flows from the supply voltage to ground through the resistors.

FIGS. 4–10illustrate the simulated performance of the embodiment ofFIG. 3. A prototype VGA was designed at the transistor level and simulated in the simulator program SPICE using an ELDO simulator. The technology used was 0.6 um BICMOS. A 2.2 volt DC power supply was used in the simulations and the resulting total current dissipation was 1.2 mA.

FIGS. 4 and 5show the SPICE simulation results for the DC gain of the VGA versus the differential control voltage v(vcp)−v(vcn).FIG. 4illustrates the High-Gain mode case and shows the input to output DC gain versus the differential control voltage of the VGA in high-gain-mode (HG=“1”, LG=“0”) of the circuit ofFIG. 3.FIG. 5illustrates the Low-Gain mode case and shows the input to output DC gain versus the differential control voltage of the VGA in low-gain-mode (HG=“0”, LG=“1”) of the circuit ofFIG. 3. In both cases a DC input signal of 100 uV was connected to the input of the VGA, the differential output voltage v(op)−v(on) was measured as a function of the automatic gain control (AGC) voltage and the gain of the VGA was calculated and plotted. As shown in the simulation results, for negative control voltages the gain in decibels (dB) is linearly dependent upon the control voltage. Such linear dependency is highly desirable for most automatic gain control applications.

FIGS. 6 and 7show the SPICE simulation results for the small signal AC gain versus frequency.FIG. 6corresponds to the High-Gain mode case whereasFIG. 7corresponds to the Low-Gain mode case.FIG. 6shows the AC gain versus frequency response of the circuit ofFIG. 3, where the control voltage is set to 0, e.g. V(VCP)−V(VCN)=0 in high gain mode (HG=“1”, LG=“0”). In both cases the control voltage that controls the gain of the VGA was set to Vc=0 Volts.FIG. 6shows that the small signal gain curve has a plateau centered at approximately 1 MHz, with the gain at the plateau being about 38 dB. This is consistent with the results for the DC gain versus the control voltage Vc, as shown inFIG. 4, that shows the DC gain is about 40 dB at Vc=0.

FIG. 6also shows that the gain is attenuated both at low and high frequencies. The attenuation of the gain at low frequencies (below 100 KHz) is the result of the highpass filter900in the last stage of the VGA. The attenuation of the gain at high frequencies (above 10 MHz) is the result of the effective lowpass filter action due to the combination of the resistors602and604with the input capacitance of the MOS transconductor amplifier circuit700, due mainly to the gate capacitance of transistors710and712. This bandpass characteristic of the VGA is an additional bonus of this architecture since we are primarily interested in amplifying only the desired signal. In a 1-MHz low-IF architecture receiver, the desired signal is centered at 1 MHz. The bandpass characteristics of the VGA help get rid of unwanted out-of-band interferers.

FIG. 7shows the AC gain versus frequency response of the circuit ofFIG. 3for the low-gain mode (HG=“0”, LG=“1”), where the control voltage is set to 0, e.g. V(VCP)−V(VCN)=0. The small signal gain curve has a plateau centered around 3 MHz. The gain at the plateau is about 10 dB, consistent with the results shown inFIG. 5for the DC gain versus control voltage at Vc=0 Volt. The low-frequency cutoff of the gain curve is again around 100 KHz due to the highpass filter900in the last stage of the VGA. However, the gain at high frequencies begins to fall at higher frequencies around 50 MHz. The reason is that in the low-gain mode the resistors602and604are disconnected from the input of the MOS amplifier700by the MOS transistor switches522and526that are “off”. However, the switches520and524that connect the inputs of the VGA, INP and INN, to the inputs of the MOS amplifier INP2and INN2, respectively, have themselves a small ‘on’ resistance of about 1 Kohm. This ‘on’ resistance, together with the input capacitance of the MOS amplifier700, creates a higher frequency pole around 50 MHz that gives rise to the slope of the gain versus frequency curve at high frequencies. If desired, resistors similar to600and604can be added in series to these switches to keep the bandwidth of the VGA the same, both in the high-gain and in the low-gain modes.

FIGS. 8A and 8Bgive the ELDO simulation results for the noise generated by the circuit elements versus frequency in the high-gain mode.FIG. 8illustrates the output noise and input referred noice of the VGA in Vrms/sqrrt(Hz), when the gain control voltage is set to 0 in high gain mode. The AGC control voltage was set to Vc=0 Volts (corresponding to a gain of ˜40 dB in the passband). The output noise is about 0.42 uVrms/sqrt(Hz) and the input referred noise is about 5.1 nVrms/sqrt(Hz). For a bandwidth BW of about 1.2 MHz around the center frequency of 1 MHz (corresponding to the signal bandwidth as well as the receiver bandwidth defined by the filters following the VGA), this corresponds to 0.42e-6*sqrt(1.2e+6)˜460 uVrms total output noise and, similarly, to 5.7 uVrms total input referred noise. For example, assuming a clean input signal to the VGA of 100 uVrms (noiseless signal) at 1 MHz, this corresponds to a Signal-to-Noise-Ratio, SNR of ˜25 dB.

FIGS. 9 and 10show the results of a two tone intermodulation simulation. In this case the input to the VGA is a two-tone signal with input tones at 3 MHz and 5 MHz, the intermodulation product at 1 MHz, and the amplitude of the input tones is 2 mV.FIG. 9illustrates the high gain mode andFIG. 10illustrates the low gain mode. The tones are centered at the adjacent and alternate adjacent channels. The channels in this application are separated from each other by 2 MHz.
Vin(t)=A*cosinus(3 MHz)+A*cosinus(5 MHz)

In an intermodulation test, the amplitude A of the interferer channels at 3 and 5 MHz is increased until the tone at 1 MHz, generated by the non-linearities in the VGA, emerges above the background of the frequency spectrum (calculated from the output waveform using a Fast Fourier Transform). In the high-gain mode,FIG. 9, A=2 mV and in the low-gain mode,FIG. 10, A=50 mV.

A simple calculation gives the following results for the IIP3:

Having illustrated and described the principles of the present invention in the context of the embodiments described above, it should be readily apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. For example, alternative implementations of the functional blocks ofFIG. 2may be suitable for use with the present invention.