MONOLITHIC THREE DIMENSIONAL (3D) RANDOM ACCESS MEMORY (RAM) ARRAY ARCHITECTURE WITH BITCELL AND LOGIC PARTITIONING

A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to memory cells for use with computing devices.

Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. The competition for space within the housing and other factors contribute to a continued miniaturization of components and power consumption within the circuitry.

Concurrent with the miniaturization pressures, there are pressures to reduce voltage levels within the mobile communication devices. Reduced voltage levels extend battery life and reduce heat generation within the mobile device. While there is pressure to reduce voltage levels, the presence of increasingly large memory blocks with a need for correspondingly larger voltage levels provides an opposing pressure. In many instances, these memory blocks are made from random access memory (RAM) and more particularly are made from static RAM (SRAM) having operating voltages on bit lines and word lines to perform row and column accesses for read and write commands to and from the memory bitcell. It is the length of the bit lines and word lines that negatively impacts the required voltage levels within the memory cell array. That is, in large arrays, the length of the bit line or word line may introduce enough capacitive or resistive qualities to diminish the voltage at distant bitcells to such a level that the desired low operating voltages are insufficient to operate the transistors at the distant bitcell.

SUMMARY OF THE DISCLOSURE

Embodiments disclosed in the detailed description include a monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. In an exemplary embodiment, the 3DIC is a monolithic 3DIC with monolithic intertier vias (MIV) coupling elements in different tiers. In an exemplary embodiment, the bitcell is arranged in a “butterfly” arrangement—so called because the bitcells are the ‘wings’ on either side of the control logic ‘thorax.’ Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit lines and word lines for each memory cell are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

In this regard in one embodiment, a 3D random access memory (RAM) is provided. The 3D RAM comprises a first 3DIC tier. The first 3DIC tier comprises a first RAM data bank disposed in the first 3DIC tier. The first 3DIC tier also comprises a second RAM data bank disposed in the first 3DIC tier. The first 3DIC tier also comprises a first RAM access logic comprising a first global block control logic disposed between the first RAM data bank disposed in the first 3DIC tier and the second RAM data bank disposed in the first 3DIC tier, the RAM access logic configured to control data access to the first RAM data bank disposed in the first 3DIC tier and the second RAM data bank disposed in the first 3DIC tier. The 3D RAM also comprises a second 3DIC tier. The second 3DIC tier comprises a first RAM data bank disposed in the second 3DIC tier. The second 3DIC tier also comprises a second RAM data bank disposed in the second 3DIC tier. The second 3DIC tier also comprises a second RAM access logic comprising a second global block control logic disposed between the first RAM data bank disposed in the second 3DIC tier and the second RAM data bank disposed in the second 3DIC tier, the second RAM access logic configured to control data access to the first RAM data bank disposed in the second 3DIC tier and the second RAM data bank disposed in the second 3DIC tier.

In another embodiment, a 3D RAM is disclosed. The 3D RAM comprises a first 3DIC tier. The first 3DIC tier comprises a first memory means disposed in the first 3DIC tier. The first 3DIC tier also comprises a second memory means disposed in the first 3DIC tier. The first 3DIC tier also comprises a first RAM access logic comprising a first global block control logic disposed between the first memory means disposed in the first 3DIC tier and the second memory means disposed in the first 3DIC tier, the RAM access logic configured to control data access to the first memory means disposed in the first 3DIC tier and the second memory means disposed in the first 3DIC tier. The 3D RAM also comprises a second 3DIC tier. The second 3DIC tier comprises a first memory means disposed in the second 3DIC tier. The second 3DIC tier also comprises a second memory means disposed in the second 3DIC tier. The second 3DIC tier also comprises a second RAM access logic comprising a second global block control logic disposed between the first memory means disposed in the second 3DIC tier and the second memory means disposed in the second 3DIC tier, the second RAM access logic configured to control data access to the first memory means disposed in the second 3DIC tier and the second memory means disposed in the second 3DIC tier.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

Embodiments disclosed in the detailed description include a monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. In an exemplary embodiment, the 3DIC is a monolithic 3DIC with monolithic intertier vias (MIV) coupling elements in different tiers. In an exemplary embodiment, the bitcell is arranged in a “butterfly” arrangement—so called because the bitcells are the ‘wings’ on either side of the control logic ‘thorax.’ Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit lines and word lines for each memory cell are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

Before addressing embodiments of the present disclosure, a brief overview of a conventional memory cell array is provided with reference toFIGS. 1-3. The discussion of embodiments of the present disclosure begins below with reference toFIG. 4.

In this regard,FIG. 1illustrates a memory cell10and in particular a six transistor (6T) static random access memory (RAM) (SRAM) bitcell. The memory cell10has a first inverter12and a second inverter14. A word line (WL)16couples to both inverters12,14. In particular, the word line16couples to the first inverter12through a gate of a first pass gate (PG) transistor18(PG1) and couples to the second inverter14through a gate of a second PG transistor20(PG2). A bit line (BL)22couples to a drain of the second PG transistor20. A bit line bar (BL)24couples to a source of the first PG transistor18.

With continued reference toFIG. 1, the first inverter12includes a first pull up (PU) transistor26(PU1) and a first pull down (PD) transistor28(PD1). The second inverter14includes a second PU transistor30(PU2) and a second PD transistor32(PD2). A voltage source (VDD)34couples to the first and second PU transistors26,30. The PD transistors28,32are coupled to ground36.

Memory cells10are well understood in the industry and are frequently assembled into an array of cells such memory cell array40illustrated inFIG. 2. In particular, memory cell array40is a three by four memory cell array although other arrays are also known (e.g., eight by one hundred twenty-eight, sixty-four by sixty-four, etc.). The bit line22and bit line bar24are coupled to the memory cells10through sense transistors42,44respectively. The voltage source34may likewise be coupled to the memory cells through transistors46. Likewise, the word lines16may be coupled to the memory cells10through the transistors42,44.

The memory cell array40is also well understood in the industry as are the control logic elements that are conventionally associated with such memory cell arrays. Such control logic elements are illustrated in association with memory cell array40inFIG. 3. In particular, the memory cell array40is coupled to a row decoder44by word lines16. The row decoder44may be coupled to row address buffers46. The memory cell40is further coupled to a column decoder48by bit lines22and bit lines bar24. The column decoder48may be coupled to column address buffers50. A databus52having a databus line and a databus bar line (databus) couples data input54to the bit lines22,24. The databus52may further couple to a sense amplifier56which provides a signal to an output58. A control logic60may control input buffers62and output buffer64.

As bit lines22, bit lines bar24, and word lines16get longer to reach the distant memory cells10within the memory cell array40(e.g., memory cell10A, in the lower left corner has relatively short lines16,22,24compared to memory cell10B in the upper right corner), the physical properties of the lines16,22,24introduce capacitive and resistive losses, which require the voltage applied to those lines to be elevated above the hypothetical minimum voltage required. Such elevated voltages decrease battery life, generate waste heat, and are otherwise considered undesirable.

One solution to shorten the length of the bit lines22, bit lines bar24, and word lines16is to arrange the memory cell arrays in a so-called “butterfly” configuration. That is, the memory cell arrays are positioned on either side of the control logic elements. Continuing the metaphor, the control logic becomes the “thorax” of the butterfly and the memory cell arrays are the “wings.” A simplified block diagram of an exemplary embodiment of a two dimensional (2D) butterfly RAM70is illustrated inFIG. 4. The butterfly RAM70has a core72having a row decoder74and word line driver76as well as a global block control (GBC) unit77. The GBC has all the processing logic to select the particular read/write multiplexers for the input and output of the memory. The core72may be adjacent to multiple memory cell arrays78,80,82,84. Each memory cell array78,80,82,84has a local data path (LDP)86,88,90,92respectively. The LDPs86,88,90,92may include any sense amplifiers (e.g., sense amplifier56) and any multiplexer (mux) as well as the actual drivers for controlling the memory cells. Each side of the core72may have a global data path (GDP)94,96, which includes the inputs and outputs for the butterfly RAM70. However, only one GDP94,96is needed per side.

By placing the LDPs86,88,90,92in this fashion, the length of the bit lines22, bit lines bar24, and word lines16(not illustrated inFIG. 4) are shortened. Shortening these lines22,24,16reduces the voltage levels needed to operate the RAM70compared to a conventional memory cell array40. Additionally, by having shorter lines, clock skew may be minimized

While the advantages of a 2D butterfly RAM70are impressive, the advent of 3DIC technology allows for even greater improvements in reducing line lengths, improving miniaturization by reducing the footprint of the memory, and customizing the memory device according to the needs of the circuit designer. The use of 3DIC technology allows the “wings” of the butterfly RAM70to be folded one atop the other such that the overall footprint is halved (or more) while maintaining the same memory storage capabilities. Additionally, different manufacturing techniques may be used between the different tiers of the 3DIC to allow for different flavors of memory to be provided on different tiers.

In this regard,FIG. 5illustrates a 3D butterfly RAM100having a first tier102and a second tier104. It should be appreciated that more tiers may be provided (not illustrated). The spacing between tiers102,104is exaggerated somewhat so as to show how the RAM data banks (also referred to as bit cell arrays)106,108,110,112extend to either side of the core114. Also illustrated are stylized representations of MIV116extending from the first tier102to the second tier104within the core114. While not illustrated, additional MIV may exist between the tiers102,104outside the core114. As with the 2D butterfly RAM70, the row decoder118, word line driver120and GBC122are positioned in the core114. Each RAM data bank106,108,110,112has a respective LDP124,126,128,130. Additionally, the GDP132,134are positioned in the second tier104, which is, as illustrated, on the bottom of the 3D butterfly RAM100. In an alternate embodiment, the GDP132,134may be in the first tier102and thus be on the top of the 3D butterfly RAM100.

In practice, by putting the access logic of the row decoder118and the word line driver120as well as the GBC122in the core114, along with the folded nature of the RAM data banks, shorter wire lengths are achieved for the word-lines16, bit lines22and bit lines bar24(not illustrated inFIG. 5). Shorter wire lengths increase memory read/write access times and saves dynamic power through reduced back-end-of-line capacitance. The folding of the RAM data banks can also result in smaller die areas resulting in increased density and smaller die and packaging costs. While described as generic RAM, both dynamic RAM (DRAM) and SRAM may benefit from the present disclosure.

The monolithic 3D RAM array architecture with bitcell and logic partitioning according to embodiments disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.

In this regard,FIG. 6illustrates an example of a processor-based system140that can employ the 3D butterfly RAM100illustrated inFIG. 5. In this example, the processor-based system140includes one or more central processing units (CPUs)142, each including one or more processors144. The CPU(s)142may be a master device. The CPU(s)142may have cache memory146which includes one or more 3D butterfly RAM100coupled to the processor(s)144for rapid access to temporarily stored data. The CPU(s)142is coupled to a system bus148and can intercouple master devices and slave devices included in the processor-based system140. As is well known, the CPU(s)142communicates with these other devices by exchanging address, control, and data information over the system bus148. For example, the CPU(s)142can communicate bus transaction requests to the memory system150that may include one or more 3D butterfly RAM100. Although not illustrated inFIG. 6, multiple system buses148could be provided, wherein each system bus148constitutes a different fabric.

Other master and slave devices can be connected to the system bus148. As illustrated inFIG. 6, these devices can include the memory system150, one or more input devices152, one or more output devices154, one or more network interface devices156, and one or more display controllers158, as examples. The input device(s)152can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s)154can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device(s)156can be any devices configured to allow exchange of data to and from a network160. The network160can be any type of network, including but not limited to a wired or wireless network, private or public network, a local area network (LAN), a wide local area network (WLAN), and the Internet. The network interface device(s)156can be configured to support any type of communication protocol desired.

The CPU(s)142may also be configured to access the display controller(s)158over the system bus148to control information sent to one or more displays162. The display controller(s)158sends information to the display(s)162to be displayed via one or more video processors164, which process the information to be displayed into a format suitable for the display(s)162. The display(s)162can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.