System aware transmitter adaptation for high speed serial interfaces

A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to system aware transmitter adaptation in a high speed serial interface.

BACKGROUND

As the speed of serial interfaces increases, variations in circuit design, component manufacture, environmental conditions, and other factors make it increasingly difficult to ensure highly reliable data transmission. In particular, transmitter and receiver equalization mechanisms to compensate for channel loss are calibrated on a best-effort basis, where settings that result in a “good enough” compensation solution are quickly obtained, in favor of iterative processes that might yield a more optimal solution, but which require an inordinate amount of time for such link training.

DETAILED DESCRIPTION OF DRAWINGS

Serial channel100includes a transmitter110, a transmission channel120, and a receiver130. Serial channel100represents one half of a bi-directional serial data link for communicating data from transmitter110located at a first component to receiver130located at a second component. The other half of the bi-directional serial data link is similar to serial channel100, but with a receiver in the first component, and a transmitter in the second component, for communicating data back from the second component to the first component. Here, the components can be understood to include elements within an information handling system, such as elements that are attached to one or more printed circuit board of the information handling system, where transmission channel120can represent one or more circuit traces on the printed circuit board, and can include one or more connectors. The components can also be understood to include devices of an information handling system, such as a hard drive, a storage array, and the like, that are separate from the printed circuit board of the information handling system, where transmission channel120can include one or more transmission cables. An example of serial channel100includes a PCI-Express (PCIe) channel that is in compliance with one or more PCIe specification, up to, and including the PCIe 4.0 Specification, a Serial ATA (SATA) channel that is in compliance with one or more SATA specification, up to, and including the SATA 3.2 Specification, a SAS channel that is in compliance with one or more SAS specification, up to and including the Serial Attached SCSI 4.0 Standard, or another high speed serial channel.

Serial channel100operates to provide back channel adaptation where transmitter110and receiver130communicate with each other to optimize and adjust various compensation values within the transmitter and the receiver to compensate for the insertion loss of transmission channel120. A determination is made as to whether or not a set of compensation values is satisfactory. In a particular embodiment, the determination is based upon the bit error rate (BER) associated with the set of values. In another embodiment, the determination is based upon the characteristics of the receiver eye pattern for the transmitted signals. It is possible for multiple different sets of compensation values to result in acceptable BER or receiver eye characteristics in serial channel100. Moreover, even on a particular information handling system, operating at different times, the back channel adaptation mechanism may operate to provide different sets of compensation values based upon minute variations in the operating condition of the information handling system. As such, serial channel100operates to adjust an output impedance of transmitter110and to repeatedly perform the back channel adaptation, recording the set of compensation values for each iteration of the back channel adaptation at each impedance setting, in order to determine a best impedance setting, as described below. Then serial channel100further operates to use the best impedance setting for subsequent iterations of the back channel adaptation.

Transmitter110includes a channel output module112and a channel management module114. Channel output module112includes an impedance setting and a tuning setting. The impedance setting operates to select a target impedance for the output of receiver130. For example, the impedance setting can operate to select a 25 ohm output impedance, a 40 ohm output impedance, a 50 ohm output impedance, a 75 ohm output impedance, or another output impedance selected to match an impedance of transmission channel120, as needed or desired. The tuning setting operates to select a fine tuning of the output impedance of transmitter110around the nominal impedance selected by the impedance setting. In a particular embodiment, the tuning setting provides a low impedance adjustment setting, a nominal setting, and a high impedance adjustment setting. For example, the low impedance adjustment setting can decrease the output impedance of channel output module112by a particular impedance value or percentage, and the high impedance adjustment setting can increase the output impedance of channel output module112by a particular impedance value or percentage. In another embodiment, the tuning setting provides more or less than three impedance adjustment settings, as needed or desired. Channel management module114will be described below.

Receiver130includes a continuous time linear equalization (CTLE) module134, an automatic gain control (AGC) module136, a decision feedback equalization (DFE) module138, a control logic module140, and a channel management module148. In operation, serial data is received from transmitter110, the received signal is provided to CTLE module134, and the CTLE module operates to provide compensation for inter-signal interference (ISI) in order to open the signal eye of the received signal. The amount of compensation is determined based upon an equalization setting. For example, receiver130can support21equalization settings which each prescribe a different amount of equalization, from 0 dB to 10 dB, in 0.5 dB steps. Other numbers of settings and amounts of equalization prescribed by the equalization setting can be utilized, as needed or desired

The equalized signal is provided from CTLE module134to AGC module136. AGC module136operates to provide linear gain to the signal received from CTLE module134to further open the signal eye of the received signal. The amount of gain is determined by a gain setting, and can support21gain settings which each prescribe a different amount of gain, for example, from 0 dB to 10 dB, in 0.5 dB steps. Other numbers of settings and amounts of gain prescribed by the gain setting can be utilized, as needed or desired.

The amplified signal is provided from AGC module136to DFE module138. DFE module138operates to provide feedback based compensation to the received signal. The amount of compensation is determined by enabling a number of circuit feedback taps. For example, DFE module138can support up to 16 taps that provide compensation based upon up to 16 previous data points. In a particular embodiment, DFE module138can be turned off, thereby reducing the power consumed by receiver130. In another embodiment, one or more tap of DFE module138can be turned on based upon the taps setting, while the rest of the taps are placed into a tri-state condition, that is, with power applied, but with the taps not providing feedback to the resultant DFE compensation. In yet another embodiment, one or more tap of DFE module138can be turned on based upon the taps setting, while the rest of the taps are turned off, thereby reducing the power consumed by receiver130. Other numbers of taps can be utilized, as needed or desired.

In operation, the impedance setting of channel output module112is set based upon a design target for transmission channel120. For example, if transmission channel120is designed as a 25 ohm transmission channel, then the impedance setting is set to the 25 ohm setting, and so forth. Control logic module140operates to direct transmitter110to set the tuning setting to the minimum offset setting, such as a minus one ohm setting. Control logic module140communicates with transmitter110via a communication channel established between channel management module114and channel management module148. In a particular embodiment, management module114and channel management module148represent a separate side-band communication channel for communicating adaptation instructions between transmitter110and receiver130. In another embodiment, management module114and channel management module148represent management traffic between transmitter110and receiver130that is communicated over transmission channel120and an additional transmission channel from receiver130to transmitter110.

With the tuning setting of channel output module112set to the minimum offset setting, control logic module140runs through the various combinations of settings for the equalization setting, the gain setting, and the taps setting, recording for each combination, an associated eye height or an associated BER, as needed or desired. Control logic module140directs transmitter110to select a next tuning setting of channel output module112and repeats the process of recording the associated eye height or BER for each of the various combinations of settings. Control logic module140continues the process of recording the associated eye height or BER for all tuning setting of channel output module112. Based upon the recorded eye heights or BERs, control logic module140determines a best tuning setting, and directs transmitter110to set the tuning setting to the best setting. Then, in subsequent iterations of back channel adaptations, transmitter110is set to provide the optimal performance for transmission channel120. A method for determining the best tuning setting is described below.

FIG. 3illustrates a graph of the exemplary results of various eye height measurements. Here, it is assumed for the sake of simplicity that CTLE module134has three equalization settings (0, 1, and 2), that AGC module136has three gain settings (0, 1, and 2), that DFE module138has three tap settings (0, 1, and 2), and that channel output module112has three settings (−1 ohm, nominal, and +1 ohm). Here, the equalization settings for receiver130are shown in the various combinations along the x-axis of the graph, where (x, y, z) represents a particular combination of settings. For example, the x-value can represent the equalization setting value, the y-value can represent the gain setting value, and the z-value can represent the taps setting value. The eye heights are marked for each tuning setting for channel output module112. Thus, a first line illustrates the eye heights for each combination of settings for the +1 ohm tuning setting, a second line illustrates the eye heights for each combination of settings for the nominal tuning setting, and a third line illustrates the eye heights for each combination of settings for the −1 ohm tuning setting.

The y-axis of the graph shows the recorded eye height in mili-volts (mV). The graph also illustrates a threshold value that represents a specified minimum eye height at 0.045 mV. In a particular embodiment, the best tuning setting is determined by the line that includes the highest eye height. Here, because the receiver setting of (2, 0, 2) produces a maximum eye height of around 0.0825 mV with the +1 ohm tuning setting, then the +1 ohm tuning setting is determined to be the best setting. In another embodiment, the setting that results in the lowest number of failing eye heights is determined to be the best tuning setting. Here, because the −1 ohm tuning setting only results in three failing setting combinations, the −1 ohm tuning setting is determined to be the best setting. In another embodiment, the best tuning setting is determined as the setting that produces the highest average eye height. In another embodiment, the best tuning setting is determined as the setting that results in a lowest standard deviation of the eye heights. In yet another embodiment, a combination of the above described criteria for determining the best tuning setting is employed, or another criteria is utilized, as needed or desired.

FIG. 4illustrates a method of determining an impedance tuning setting in a serial interface, starting at block402. An impedance for a transmitter is set in block404. For example, the impedance setting of channel output module112can be selected to match the design impedance of transmission channel120. A tuning setting for the transmitter is set to nominal in block406. For example, the tuning setting of channel output module112can be set to the nominal setting. The various combinations of compensation settings are selected in block408, and a measurement of the value at each combination is recorded in block410. For example, the 27 combinations of compensation settings as described inFIG. 3, above, can be selected, and a BER or an eye height can be measured and recorded. The skilled artisan will recognize that a method for selecting the combinations of compensation settings can include a nested loop where each combination of compensation settings is selected. The recorded values from block410are stored in a values database412.

A decision is made as to whether or not the selected tuning setting is the last tuning setting in decision block414. If not, the “NO” branch of decision block414is taken, the next tuning setting is selected in block416, and the method returns to block408where the various compensation setting combinations are selected. If the selected tuning setting is the last tuning setting, the “YES” branch of decision block414is taken and the recorded values for each tuning setting are evaluated to determine the best tuning setting in block418. For example, the best tuning setting can include one or more of the tuning setting that included the combination of compensation settings that provided the maximum eye height or the minimum BER, the tuning setting that included the fewest number of combinations of compensation settings that failed a particular criteria, the tuning setting that included the highest average eye height or the lowest average BER, or another criteria, as needed or desired. The recorded values are derived from values database412. The transmitter is set to the best tuning setting in block420and the method ends in block422.

Information handling system500can include devices or modules that embody one or more of the devices or modules described above, and operates to perform one or more of the methods described above. Information handling system500includes a processors502and504, a chipset510, a memory520, a graphics interface530, include a basic input and output system/extensible firmware interface (BIOS/EFI) module540, a disk controller550, a disk emulator560, an input/output (I/O) interface570, and a network interface580. Processor502is connected to chipset510via processor interface506, and processor504is connected to the chipset via processor interface508. Memory520is connected to chipset510via a memory bus522. Graphics interface530is connected to chipset510via a graphics interface532, and provides a video display output536to a video display534. In a particular embodiment, information handling system500includes separate memories that are dedicated to each of processors502and504via separate memory interfaces. An example of memory520includes random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/EFI module540, disk controller550, and I/O interface570are connected to chipset510via an I/O channel512. An example of I/O channel512includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. Chipset510can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/EFI module540includes BIOS/EFI code operable to detect resources within information handling system500, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module540includes code that operates to detect resources within information handling system500, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller550includes a disk interface552that connects the disc controller to a hard disk drive (HDD)554, to an optical disk drive (ODD)556, and to disk emulator560. An example of disk interface552includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator560permits a solid-state drive564to be connected to information handling system500via an external interface562. An example of external interface562includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive564can be disposed within information handling system500.

I/O interface570includes a peripheral interface572that connects the I/O interface to an add-on resource574, to a TPM576, and to network interface580. Peripheral interface572can be the same type of interface as I/O channel512, or can be a different type of interface. As such, I/O interface570extends the capacity of I/O channel512when peripheral interface572and the I/O channel are of the same type, and the I/O interface translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel572when they are of a different type. Add-on resource574can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource574can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system500, a device that is external to the information handling system, or a combination thereof.

Network interface580represents a NIC disposed within information handling system500, on a main circuit board of the information handling system, integrated onto another component such as chipset510, in another suitable location, or a combination thereof. Network interface device580includes network channels582and584that provide interfaces to devices that are external to information handling system500. In a particular embodiment, network channels582and584are of a different type than peripheral channel572and network interface580translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels582and584includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels582and584can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.