System and method for creating different field oxide profiles in a locos process

An efficient method is disclosed for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process). The method comprises (1) forming a first portion of the field oxide with a first field oxide profile (e.g., an abrupt bird's beak profile) during a field oxide oxidation process, and (2) forming a second portion of the field oxide with a second field oxide profile (e.g., a graded bird's beak profile) during the field oxide oxidation process. A graded bird's beak profile enables higher breakdown voltages. An abrupt bird's beak profile enables higher packing densities. The method gives an integrated circuit designer the flexibility to create an appropriate field oxide profile at a desired location.

CROSS-REFERENCE TO RELATED APPLICATION

The patent application is related to U.S. Patent Application Ser. No. 11/486,952 entitled “System and Method for Increasing Breakdown Voltage of LOCOS Isolated Devices” that is being filed concurrently with this patent application. This patent application and U.S. Patent Application Ser. No. 11/486,952 are both owned by the same assignee.

TECHNICAL FIELD OF THE INVENTION

The present invention is generally directed to semiconductor technology and, in particular, to a system and method for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process).

BACKGROUND OF THE INVENTION

In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits. Large scale integrated circuits comprise thousands of devices placed on a single integrated circuit chip. A standard process for electrically isolating the devices on an integrated circuit chip is the local oxidation of silicon process (LOCOS process).

The creation of a prior art LOCOS isolation structure is illustrated inFIG. 1and inFIG. 2. The structure100shown inFIG. 1comprises a silicon substrate100. A layer of pad oxide120made up of silicon dioxide (SiO2) is placed on the silicon substrate100. Then a layer130of silicon nitride (Si3N4) is placed on the layer pad oxide120. A mask and etch procedure is used to etch an aperture140through the silicon nitride layer130and through the pad oxide layer120down to the silicon substrate100. The application of the mask and etch procedure creates the structure100shown inFIG. 1.

Then the portions of the silicon substrate100that are exposed through aperture140are exposed to steam (H2, O2) at a relatively high temperature (e.g., one thousand degrees Celsius (1000° C.)). The oxygen in the steam oxidizes the silicon substrate100to form silicon dioxide (SiO2). The oxidation process causes the oxidized portion of the silicon substrate100increase in size.

The resulting structure200is shown inFIG. 2. The oxidized portion of the silicon substrate100is designated with reference numeral210. As shown inFIG. 2, the oxidized portion210of the silicon substrate100is sometimes referred to as a field oxide. The field oxide210forms an isolation structure or isolation barrier that electrically separates and isolates portions of the integrated circuit chip.

At the edges of the field oxide210(near the edges of the silicon nitride portions130) the thickness of the field oxide tapers off. The maximum thickness of the field oxide210(shown by double arrows inFIG. 2) gradually decreases near edges of the field oxide210and tapers down to the thickness of the pad oxide120.

The tapering profile of the edges of the field oxide210forms a portion of the field oxide210that is known as a “bird's beak.” The bird's beak portion of the field oxide210inFIG. 2is designated with reference numeral220.

If the bird's peak portion of the field oxide has a relatively graded slow tapering profile the resulting bird's beak profile will have the bird's peak profile300shown inFIG. 3. For convenience in description the bird's beak profile300will be referred to as a “graded” bird's beak.

If the bird's beak portion of the field oxide has a relatively short quick tapering profile the resulting bird's beak profile will have the bird's beak profile400shown inFIG. 4. For convenience in description the bird's beak profile400will be referred to as an “abrupt” bird's beak.

In prior art manufacturing processes a thick pad oxide and/or a thin silicon nitride layer will create a graded bird's beak300. Similarly, in prior art manufacturing processes a thin pad oxide and/or a thick silicon nitride layer will create an abrupt bird's beak400.

A significant advantage of the abrupt bird's beak is that the abrupt bird's beak takes up less lateral space than a graded bird's beak. This means that there is less space required to form the field oxide isolation structure. Therefore there is more space remaining in the integrated circuit chip for the integrated circuit devices (e.g., transistors). This concept is usually expressed by stating that the abrupt bird's beak provides a better packing density for the integrated circuit devices. A major drawback of the abrupt bird's beak is that the abrupt bird's beak has a lower breakdown voltage.

Conversely, a major advantage of the graded bird's beak is that it provides a higher breakdown voltage. But the graded bird's beak takes up more lateral space than an abrupt bird's beak. This means that the graded bird's beak has a correspondingly worse packing density in the integrated circuit chip for the integrated circuit devices (e.g., transistors).

In prior art manufacturing methods a single value of pad oxide thickness is used and a single value of silicon nitride thickness is used. This means that the designer of an integrated circuit is forced to make a tradeoff between the packing density and the breakdown voltage of the integrated circuit chip. If the packing density is optimized then the breakdown voltage is not optimized. Conversely, if the breakdown voltage is optimized then the packing density is not optimized.

There is a need in the art for an efficient method for manufacturing an integrated circuit that has two different field oxide profiles. In particular, there is a need in the art for a method that is capable of forming both a graded bird's beak profile and an abrupt bird's beak profile with the same field oxidation process.

The present invention provides an efficient method for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process). The method comprises (1) forming a first portion of the field oxide with a first field oxide profile (e.g., an abrupt bird's beak profile) during a field oxide oxidation process, and (2) forming a second portion of the field oxide with a second field oxide profile (e.g., a graded bird's beak profile) during the same field oxide oxidation process.

As will be described more fully below, an advantageous embodiment of the method of the invention uses a first value of a pad oxide thickness and a first value of a silicon nitride thickness to form a first portion of a field oxide having a first field oxide profile. The method simultaneously uses a second value of a pad oxide thickness and a second value of a silicon nitride thickness to form a second portion of the field oxide having a second field oxide profile.

It is an object of the present invention to provide a method for efficiently forming two different field oxide profiles during a field oxide oxidation process.

It is an object of the present invention to provide a manufacturing method for an integrated circuit that gives an integrated circuit designer the flexibility to create an appropriate type of field oxide profile in a desired location.

It is another object of the present invention to provide a manufacturing method for an integrated circuit that creates a graded bird's beak profile in an area where it is more important to have a higher breakdown voltage than a high packing density.

It is another object of the present invention to provide a manufacturing method for an integrated circuit that creates an abrupt bird's beak profile in an area where it is more important to have a higher packing density than a high breakdown voltage.

The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those persons who are skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Persons who are skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Persons who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

Definitions for certain words and phrases are provided throughout this patent document, those persons of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as future uses, of such defined words and phrases.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 5illustrates a first stage of a manufacturing method of the present invention for manufacturing different field oxide profiles in a local oxidation of silicon (LOCOS) process. The structure500shown inFIG. 5comprises a layer of silicon substrate510. A layer of pad oxide520made up of silicon dioxide (SiO2) is placed on the silicon substrate510. In one advantageous embodiment of the method of the present invention the thickness of the pad oxide520is approximately two hundred fifty Ångstroms (250 Å). An Ångstrom is 10−10meter.

Then a first layer530of silicon nitride (Si3N4) is placed on the layer pad oxide520. In one advantageous embodiment of the method of the present invention the thickness of the first layer of silicon nitride530is approximately one thousand Ångstroms (1000 Å).

A mask and etch procedure is used to etch the first layer of silicon nitride530away from the areas of the integrated circuit chip that will require a high breakdown voltage. The portions of the first layer of silicon nitride530over the areas of the integrated circuit chip that will require a high packing density are left in place. The resulting structure600is shown inFIG. 6.

In the next step of the method of the present invention an additional pad oxide layer710is grown over the exposed portions of the original pad oxide layer520. In one advantageous embodiment of the method of the present invention the additional pad oxide layer710increases the total thickness of the pad oxide layer over the areas of the integrated circuit chip that will require a high breakdown voltage to approximately six hundred thirty Ångstroms (630 Å). The resulting structure700is shown inFIG. 7.

In the advantageous embodiment of the method of the present invention shown inFIG. 7the thick pad oxide layer710(having a thickness of approximately 630 Å) is approximately three hundred eighty Ångstroms (380 Å) thicker than the thin pad oxide layer520(having a thickness of approximately 250 Å).

In the next step of the method of the present invention a second layer of silicon nitride810is deposited over the first layer of silicon nitride530and over the pad oxide layer720. In one advantageous embodiment of the method of the present invention the thickness of the second layer of silicon nitride810is approximately one thousand Ångstroms (1000 Å). The resulting structure800is shown inFIG. 8.

In the next step of the method of the present invention a mask and etch procedure is used pattern the second layer of silicon nitride810and the underlying first layer of silicon nitride530. On the portion of the integrated circuit chip that will require a high breakdown voltage the etch procedure stops on the underlying pad oxide layer720. On the portion of the integrated circuit chip that will require a high packing density the etch procedure stops of the underlying pad oxide520. The resulting structure900is shown inFIG. 9.

For convenience of description the portion of the second layer of silicon nitride810that remains on the portion of the integrated circuit that will require a high breakdown voltage is designated with reference numeral910. Similarly, the portion of the second layer of silicon nitride810that remains on the portion of the integrated circuit that will require a high packing density is designated with reference numeral920. As shown inFIG. 9, the lateral dimension (or width) of the silicon nitride portion910is greater than the lateral dimension (or width) of the silicon nitride portion920.

In the next step of the method of the present invention a field oxide is grown on the structure900by subjecting the structure900to steam (H2, O2) at a relatively high temperature (e.g., one thousand degrees Celsius (1000° C.)). The oxygen in the steam oxidizes the portions of the silicon substrate510that underlie the exposed portions of pad oxide layer720to form silicon dioxide (SiO2). The oxygen in the steam also oxidizes the portions of the silicon substrate510that underlie the exposed portions of pad oxide layer520to form silicon dioxide (SiO2).

The oxidation process causes the oxidized portions of the silicon substrate510increase in size. The resulting structure1000is shown inFIG. 10. The field oxide portions are designated with reference numeral1010.

During the oxidation process in the area with the thick pad oxide710and the single silicon nitride layer910the bird's beak profile of the field oxide1010will have a gradeder and more gradual profile. During the oxidation process in the area with the thin pad oxide520and the double nitride layers (i.e., silicon nitride layer920and silicon nitride layer530) the bird's beak profile of the field oxide1010will have a shorter and more abrupt profile.

In the next step of the method of the present invention the silicon nitride layers are removed. Specifically, the silicon nitride layer910is removed from the portion of the integrated circuit that will require a high breakdown voltage. The silicon nitride layer920and the silicon nitride layer530are removed from the portion of the integrated circuit that will require a high packing density. The resulting structure1100is shown inFIG. 11.

In the last step of the method of the present invention the pad oxide layers are removed. Specifically, the thick pad oxide layer710and the thin pad oxide layer520are stripped away. The resulting structure1200is shown inFIG. 12.

As shown inFIG. 12, the edge portions of the field oxide1010in the portions of the integrated circuit that will require a high breakdown voltage comprise a first graded bird's beak1210and a second graded bird's beak1220. The edge portions of the field oxide1010in the portions of the integrated circuit that will require a high packing density comprise a first abrupt bird's beak1230and a second abrupt bird's beak1240.

The first graded bird's beak1210and the second graded bird's beak1220have a higher breakdown voltage (which is more desirable) and a lower packing density (which is less desirable). The first abrupt bird's beak1230and the second abrupt bird's beak1240have a lower breakdown voltage (which is less desirable) and a higher packing density (which is more desirable).

The method of the present invention provides a novel and efficient method for forming two different field oxide profiles during a field oxide oxidation process. The method of the present invention gives an integrated circuit designer the flexibility to create an appropriate field oxide profile where desired. Specifically, the designer can create graded bird's beak profiles in those areas where it is more important to have a higher breakdown voltage than a high packing density. Similarly, the designer can create abrupt bird's beak profiles in those areas where it is more important to have a high packing density than a high breakdown voltage.

The method of the present invention creates integrated circuit chips that comprise (1) field oxide portions that facilitate the creation of integrated circuit devices that have a high packing density, and that comprise (2) field oxide portions that facilitate the creation of integrated circuit devices that have a high breakdown voltage.

The present invention has been described using basic LOCOS processing for both the thin and thick pad oxides and nitrides. It is understood that many presently existing modified LOCOS techniques could be applied to either or both of the oxide nitride stacks. Such modified LOCOS techniques include (but are not limited to) Poly Buffered LOCOS, recessed LOCOS, semi-recessed LOCOS, Poly Encapsulated LOCOS, and Side Wall Mask Isolation (SWAMI).

Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.