Display apparatus having data compensating circuit

In a data compensating circuit and a display apparatus having the same, a previous compressed data compressed from a previous frame data is previously stored in a memory, a decoder decompresses the previous compressed data from the memory to output a previous decompressed data, a coder-decoder compresses a present frame data into a present compressed data to store the present compressed data in the memory and decompresses the present compressed data to output a present decompressed data. A first processor outputs a difference value between the previous decompressed data and the present decompressed data, a second processor adds the present frame data and the difference value to generate a previous re-decompressed data. A compensator outputs a present compensation data based on the previous re-decompressed data and the present frame data. Thus, the size of the memory may be reduced while preventing damage of data.

CROSS-REFERENCE TO RELATED APPLICATION

This application relies for priorities upon Korean Patent Applications Nos. 2006-52607 filed on Jun. 12, 2006 and 2006-73457 filed on Aug. 3, 2006, the contents of which are herein incorporated by references in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display apparatus and, more particularly, to a display apparatus having a data compensating circuit capable of preventing damage of data.

2. Description of the Related Art

In general, a liquid crystal display (LCD) includes two display substrates and a liquid crystal layer interposed between the substrates. The LCD applies an electric field to the liquid crystal layer to control the transmittance of light passing through the liquid crystal layer by adjusting intensity of the electric field, thereby displaying desired images.

Recently, the LCD has been widely used as a display apparatus to display moving images for computers, television sets or the like. However, a conventional LCD is not suitable for displaying the moving images since the response speed of the liquid crystal is slow.

The slow response speed of the liquid crystal molecules is due to the time required to charge the liquid crystal capacitor to sufficient voltage to obtain the desired display brightness. Especially, when the voltage difference between a previous voltage charged into a liquid crystal capacitor and the target voltage is large, the liquid crystal capacitor is not charged to the target voltage during a 1H period when the switching element is turned on. This is so even if the target voltage is applied to the capacitor from the beginning of the 1H period.

To avoid this problem, a conventional LCD employs a dynamic capacitance compensation (DCC) method in order to speed-up the response speed of the liquid crystal. According to the DCC method, a compensation voltage is applied to pixels during a present frame based on the target voltage of the present frame and the previous voltage of the previous frame in order to speed-up the response speed of the liquid crystal.

However, additional frame memories are necessary in the conventional LCD employing the DCC method to store the previous voltage of the previous frame. As a result, the productivity of the LCD is degraded and the cost of manufacture increases due to the number and size of the frame memories.

SUMMARY OF THE INVENTION

The present invention provides a data compensating circuit capable of improving productivity thereof by reducing a memory size and preventing damage of data.

The present invention also provides a display apparatus having the above data compensating circuit.

In one aspect of the present invention, a data compensating circuit includes a memory, a decoder, a coder-decoder, a first processor, a second processor and a compensator. The memory stores data compressed from a previous frame and the decoder decompresses the previously compressed data that is read out from the memory during the present frame. The coder-decoder compresses present frame data and stores the present compressed data in the memory and decompresses the present compressed data to output decompressed data during the present frame.

The first processor outputs a first difference value indicating the difference between the previous decompressed data and the present decompressed data, and the second processor outputs a previous re-decompressed data based on the first difference value and the present frame data. The compensator compensates the present frame data based on the previous re-decompressed data and the present frame data to output a present compensation data.

In another aspect of the present invention, a data compensating circuit includes a first memory, a second memory, a coder, a comparator, a decoder, a compensator and a data selector.

In the first memory, (n−2)th compressed data from an (n−2)th frame data (where n represents the present frame) is previously stored and an (n−1)th compressed data from an (n−1)th frame data is previously stored in the second memory. The coder converts n-th frame data into n-th compressed data during the n-th frame, and the comparator compares the (n−2)th compressed data, the (n−1)th compressed data and the n-th compressed data with each other to output a selection signal.

The decoder decompresses the n-th compressed data, the (n−1)th compressed data and the (n−2)th compressed data into an n-th decompressed data, an (n−1)th decompressed data and an (n−2)th decompressed data, respectively. The compensator outputs a first compensation data based on the (n−1)th decompressed data and the (n−2)th decompressed data, and the data selector outputs either the n-th frame data or the first compensation data as output data in response to the selection signal.

In a further aspect of the present invention, a display apparatus includes a first memory, a second memory, a first decoder, a second decoder, a coder-decoder, a first processor, a second processor, a third processor, a fourth processor and a compensator. The first memory stores (n−2)th compressed data from an (n−2)th frame data during the (n−1)th frame, outputs the previously stored (n−2)th compressed data during the n-th frame, and stores (n−1)th compressed data from the (n−1)th frame data. The second memory stores the (n−1)th compressed data during the (n−1)th frame and outputs the previously stored (n−1)th compressed data during the n-th frame.

The first decoder decompresses the (n−2)th compressed data to output the (n−2)th decompressed data during the n-th frame, and the second decoder decompresses the (n−1)th compressed data to output the (n−1)th decompressed data during the n-th frame. The coder-decoder compresses the n-th frame data into the n-th compressed data to store the n-th compressed data in the second memory and decompresses the n-th compressed data into the n-th decompressed data during the n-th frame.

The first processor outputs a first difference value indicating a difference between the (n−2)th decompressed data and the n-th decompressed data, and the second processor outputs an (n−2)th re-decompressed data based on the first difference value and the n-th frame data. The third processor outputs a second difference value indicating a difference between the (n−1)th decompressed data and the n-th decompressed data, and the fourth processor generates an (n−1)th re-decompressed data based on the second difference value and the n-th frame data. The compensator compensates the (n−1)th re-decompressed data to output (n−1)th compensation data based on the (n−2)th re-decompressed data, the (n−1)th re-decompressed data and the n-th frame data.

In a further aspect of the present invention, a display apparatus includes a data compensating circuit, a data driving circuit, a gate driving circuit and a display part. The data compensating circuit receives n-th frame data to compensate the n-th frame data as the output data during the n-th frame. The data driving circuit converts the compensated data into a data voltage in response to a data control signal to output the data voltage. The gate driving circuit outputs a gate voltage in response to a gate control signal. The display part displays an image in response to the data voltage and the gate voltage.

The data compensating circuit includes a first memory, a second memory, a coder, a comparator, a decoder, a compensator and a data selector.

The (n−2)th compressed data compressed from the (n−2)th frame data is previously stored in the first memory and the (n−1)th compressed data compressed from the (n−1)th frame data is previously stored in the second memory. The coder converts the n-th frame data into the n-th compressed data during the n-th frame, and the comparator compares the (n−2)th compressed data, the (n−1)th compressed data and the n-th compressed data with each other to output a selection signal.

The decoder decompresses the n-th compressed data, the (n−1)th compressed data and the (n−2)th compressed data into the n-th decompressed data, the (n−1)th decompressed data and the (n−2)th decompressed data, respectively. The compensator outputs a first compensation data based on the n-th decompressed data, the (n−1)th decompressed data and the (n−2)th decompressed data, and the data selector outputs either the n-th frame data or the first compensation data as the output data in response to the selection signal.

According to the above, since the compressed data is stored in the memory, the size of the memory may be reduced. Also, in case of displaying a freeze-frame image, the present frame data that is neither compressed nor decompressed is output, thereby preventing damage of data.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a block diagram showing an exemplary embodiment of a data compensating circuit according to the present invention.

Referring toFIG. 1, a data compensating circuit100includes a memory110, a decoder120, a coder-decoder130, a first processor140, a second processor150and a compensator160.

In the memory110, data Fc(n−1) compressed from a previous frame F(n−1) is previously stored. In the present embodiment, if the previous frame data F(n−1) includes 24 bits, the previous compressed data Fc(n−1) includes 8 bits that are compressed into one-third of the previous frame data F(n−1). Thus, the memory110is smaller than 2m(m represents a number of bits of the previous frame data F(n−1)). That is, when the previous frame data F(n−1) includes 24 bits, the memory110has a size of 28. Likewise, compressed data having a data amount less than one frame amount is stored in the memory110, so that the size of the memory110may be reduced.

The decoder120reads out the previous compressed data Fc(n−1) that is previously stored in the memory110and decompresses the previous compressed data Fc(n−1) to output a previous decompressed data Fd(n−1) during a present frame. Particularly, the decoder120decompresses the previous compressed data Fc(n−1) of m/3 bits into the previous decompressed data Fd(n−1) of m bits.

The coder-decoder130receives present frame data F(n) and compresses the present frame data F(n) into present compressed data Fc(n) to store the present compressed data Fc(n) in the memory110during the present frame. The present frame data F(n) includes m bits and the present compressed data Fc(n) includes m/3 bits. The coder-decoder130decompresses the present compressed data Fc(n) to output a present decompressed data Fd(n) during the present frame.

The first processor140outputs a first difference value ΔFd(n) between the previous decompressed data Fd(n−1) and the present decompressed data Fd(n), and the second processor150generates a previous re-decompressed data Fd′(n−1) based on the first difference value ΔFd(n) and the present frame data F(n). Particularly, the second processor150adds the first difference value ΔFd(n) to the present frame data F(n) to generate the previous re-decompressed data Fd′(n−1). For a freeze-frame image, the present decompressed data Fd(n) is identical to the previous decompressed data Fd(n−1), so that the first difference value ΔFd(n) is equal to zero. Thus, the second processor150may output the previous re-decompressed data Fd′(n−1) that is identical to the present frame data F(n).

The compensator160compensates the present frame data F(n) based on the previous re-decompressed data Fd′(n−1) and the present frame data F(n) to output a present compensation data F′(n). Particularly, the compensator160outputs the present compensation data F′(n) that is identical to the present frame data F(n) when a second difference value between the previous re-decompressed data Fd′(n−1) and the present frame data F(n) is smaller than a predetermined first reference value. Thus, for a freeze-frame image, the first difference value ΔFd(n) is equal to zero, so that the previous re-decompressed data Fd′(n−1) is identical to the present frame data F(n).

During the present frame, the present frame data F(n) that is neither compressed nor decompressed is output. Thus, the present frame data F(n) that is not processed is used to display an image, thereby preventing damage of the freeze-frame image.

The compensator160outputs the present compensation data F′(n) which is increased by a predetermined compensated value over the present frame data F(n) when the second difference value is larger than the first reference value.

Hereinafter, the present compensation data that is overdriven (increased or decreased) by the compensator160will be described in detail with reference toFIGS. 2 and 3.

FIGS. 2 and 3are graphs showing brightness and voltage corresponding to the present compensation data compensated by the data compensating circuit shown inFIG. 1. InFIGS. 2 and 3, x axis represents time and y axis represent voltage and brightness. The voltage represents a voltage applied to the liquid crystal layer at every frame, and the brightness represents brightness of light that passes through the liquid crystal layer.

Referring toFIG. 2, the previous frame data corresponds to a first target voltage Vt1and the present frame data corresponds to a second target voltage Vt2that is higher than the first target voltage Vt1. When the voltage difference between the first target voltage Vt1and the second target voltage Vt2is larger than the predetermined reference value, the desired target brightness Lt may not be obtained within one frame even though the second target voltage Vt2is applied to the liquid crystal layer. In order to solve the problem, the compensator160(shown inFIG. 1) overdrives (increases) the second target voltage Vt2to a third target voltage Vt3that is higher than the second target voltage Vt2during the present frame n. Thus, the third target voltage Vt3is applied to the liquid crystal layer during the present frame n, so that the rising time of the voltage for the liquid layer may be reduced and the desired target brightness Lt may be obtained within one frame.

Referring toFIG. 3, the previous frame data corresponds to the first target voltage Vt1and the present frame data corresponds to the second target voltage Vt2that is lower than the first target voltage Vt1. When the voltage difference between the first target voltage Vt1and the second target voltage Vt2is larger than the predetermined reference value, the desired target brightness Lt may not be obtained within one frame even though the second target voltage Vt2is applied to the liquid crystal layer. In order to solve the problem, the compensator160(shown inFIG. 1) overdrives (decreases) the second target voltage Vt2to the third target voltage Vt3that is lower than the second target voltage Vt2during the present frame n. Thus, the third target voltage Vt3is applied to the liquid crystal layer during the present frame n, so that the falling time of the voltage for the liquid crystal layer may be reduced and desired target brightness Lt may be obtained within one frame.

As described above, the overdriven (increased or decreased) voltage is applied to the liquid crystal layer, thereby improving the response speed of the liquid crystal molecules of the liquid crystal layer.

FIG. 4is a block diagram showing another exemplary embodiment of a data compensating circuit according to the present invention andFIG. 5is an inner block diagram of the compensator shown inFIG. 4.

Referring toFIG. 4, a data compensating circuit200includes a first memory210, a second memory220, a first decoder230, a second decoder240, a coder-decoder250, a first processor260, a second processor270, a third processor280, a fourth processor290and a compensator295.

In the first memory210, (n−2)th compressed data Fc(n−2) from the (n−2)th frame data F(n−2) is previously stored, and the (n−1)th compressed data Fc(n−1) from an (n−1)th frame data F(n−1) is previously stored in the second memory220. The first memory210outputs the previously stored (n−2)th compressed data Fc(n−2) during an n-th frame and stores the (n−1)th compressed data Fc(n−1). The second memory220outputs the previously stored (n−1)th compressed data Fc(n−1) during the n-th frame. In the present embodiment, if each of the (n−2)th and (n−1)th frame data includes m bits, each of the (n−2)th and (n−1)th compressed data includes m/3 bits. Each of the first and second memories210and220is smaller than 2m. As an example of the present embodiment, each of the first and second memories210and220has a size of about 2m/3.

The first decoder230decompresses the (n−2)th compressed data Fc(n−2) to output (n−2)th decompressed data Fd(n−2) during the n-th frame, and the second decoder240decompresses the (n−1)th compressed data Fc(n−1) to output (n−1)th decompressed data Fd(n−1) during the n-th frame. In the present embodiment, the first and second decoders230and240decompress the (n−2)th and (n−1)th compressed data Fc(n−2) and Fc(n−1) of m/3 bits into (n−2)th and (n−1)th decompressed data Fd(n−2) and Fd(n−1) of m bits, respectively.

The coder-decoder250receives n-th frame data F(n) during the n-th frame and compresses the n-th frame data F(n) into the n-th compressed data Fc(n) to provide the n-th compressed data Fc(n) to the second memory220. The coder-decoder250decompresses the n-th compressed data Fc(n) to output n-th decompressed data Fd(n) during the n-th frame.

The first processor260outputs a first difference value ΔFd(n−2) between the (n−2)th decompressed data Fd(n−2) and the n-th decompressed data Fd(n), and the second processor270generates (n−2)th re-decompressed data Fd′(n−2) based on the first difference value ΔFd(n−2) and the n-th frame data F(n). The second processor270adds the first difference value ΔFd(n−2) to the n-th frame data F(n) to generate the (n−2)th re-decompressed data Fd′(n−2).

The third processor280outputs a second difference value ΔFd(n−1) between the (n−1)th decompressed data Fd(n−1) and the n-th decompressed data Fd(n), and the fourth processor290generates (n−1)th re-decompressed data Fd′(n−1) based on the second difference value ΔFd(n−1) and the n-th frame data F(n). The fourth processor290adds the second difference value ΔFd(n−1) to the n-th frame data F(n) to generate the (n−1)th re-decompressed data Fd′(n−1).

The compensator295compensates the (n−1)th re-decompressed data Fd′(n−1) based on the (n−2)th re-decompressed data Fd′(n−2), the (n−1)th re-decompressed data Fd′(n−1) and the n-th frame data F(n) to output (n−1)th compensation data F′(n−1).

As shown inFIG. 5, the compensator295includes a first compensator296and a second compensator297. The first compensator296generates (n−1)th compensation decompressed data Fd″(n−1) based on the (n−2)th re-decompressed data Fd′(n−2) and the (n−1)th re-decompressed data Fd″(n−1). The second compensator297generates the (n−1)th compensation data F′(n−1) based on the (n−1)th compensation decompressed data Fd″(n−1) and the n-th frame data F(n).

Particularly, the first compensator296outputs the (n−1)th compensation decompressed data Fd″(n−1) that is identical to the (n−2)th re-decompressed data Fd′(n−2) when a third difference value between the (n−2)th re-decompressed data Fd′(n−2) and the (n−1)th re-decompressed data Fd′(n−1) is smaller than a predetermined first reference value, and outputs the (n−1)th compensation decompressed data Fd″(n−1) that is overdriven from the (n−1)th re-decompressed data Fd′(n−1) when the third difference value is larger than the predetermined first reference value.

For a freeze-frame image, each of the first and second difference values ΔFd(n−2) and ΔFd(n−1) is equal to zero, so that each of the (n−2)th and (n−1)th re-decompressed data Fd′(n−2) and Fd′(n−1) is identical to the n-th frame data F(n). Also, the third difference value is equal to zero, the first compensator296outputs the (n−1)th compensation decompressed data Fd″(n−1) that is identical to the n-th frame data F(n).

Meanwhile, the second compensator297generates (n−1)th compensation data F′(n−1) that is larger by a second compensated value than the (n−1)th compensation decompressed data Fd″(n−1) when the (n−1)th compensation decompressed data Fd″(n−1) is smaller than a second reference value and the n-th frame data F(n) is larger than a third reference value. The second compensator297generates the (n−1)th compensation data F′(n−1) that is identical to the (n−1)th compensation decompressed data Fd″(n−1) when the (n−1)th compensation decompressed data Fd″(n−1) is larger than the second reference value or the n-th frame data F(n) is smaller than the third reference value.

For a freeze-frame image, the second compensator297generates the (n−1)th compensation data F′(n−1) that is identical to the (n−1)th compensation decompressed data Fd″(n−1). Since the (n−1)th compensation decompressed data Fd″(n−1) is identical to the n-th frame data F(n), the (n−1)th compensation data F′(n−1) is equal to the n-th frame data F(n).

Likewise, when displaying the freeze-frame image, each of the first and second compensators296and297output the n-th frame data F(n) that is neither compressed nor decompressed. Thus, the n-th frame data F(n) that is not processed is used to display an image, thereby preventing damage of the freeze-frame image.

FIG. 6is a block diagram showing another exemplary embodiment of a data compensating circuit according to the present invention andFIG. 7is an inner block diagram of a compensator shown inFIG. 6.

Referring toFIG. 6, a data compensating circuit900includes a first memory910, a second memory920, a coder930, a comparator940, a decoder950, a compensator960and a data selector970.

In the first memory910, (n−1)th compressed data Fc(n−1) compressed from the (n−1)th frame data F(n−1) is previously stored, and (n−2)th compressed data Fc(n−2) compressed from the (n−2)th frame data F(n−2) is previously stored in the second memory920. Each of the first and second memories910and920is smaller than 2m/i(m represents a number of bits of the (n−1)th and (n−2)th frame data F(n−1) and F(n−2) and i represents a value obtained by dividing m bits by a number of bits to be compressed).

In the present embodiment, in case that the (n−1)th frame data F(n−1) includes 24 bits, the (n−1)th compressed data Fc(n−1) includes 8 bits that is compressed into one third of the (n−1)th frame data F(n−1). Thus, each of the first and second memories910and920has a size of 28. Likewise, a compressed data having a data amount smaller than one frame amount is stored in each of the first and second memories910and920, so that the size of the first and second memories910and920may be reduced.

The coder930receives n-th frame data F(n) and compresses the n-th frame data F(n) into n-th compressed data Fc(n) during the n-th frame. Each of the (n−1)th and (n−2)th compressed data Fc(n−1) and Fc(n−2) previously stored in the first memory910and the second memory920, respectively, is read out during the n-th frame, and then each of the (n−1)th and (n−2)th compressed data Fc(n−1) and Fc(n−2) is stored in the first memory910and the second memory920, respectively.

The comparator940receives the n-th compressed data Fc(n), the (n−1)th compressed data Fc(n−1) and the (n−2)th compressed data Fc(n−2) from the coder930, the first memory910and the second memory920, respectively. The comparator940outputs a selection signal S1having a first state when the n-th compressed data Fc(n) is identical to the (n−1)th and (n−2)th compressed data Fc(n−1) and Fc(n−2). Also, the comparator940outputs the selection signal S1having a second state when the n-th compressed data Fc(n) is different from the (n−1)th compressed data Fc(n−1) and (n−2)th compressed data Fc(n−2) and the (n−1)th compressed data Fc(n−1) is identical to the (n−2)th compressed data Fc(n−2).

The decoder950includes a first decoder951, a second decoder952and a third decoder953. The first decoder951receives the n-th compressed data Fc(n) from the coder930and decompresses the n-th compressed data Fc(n) into an n-th decompressed data Fd(n) to output the n-th decompressed data Fd(n). The second decoder952receives the (n−1)th compressed data Fc(n−1) and decompresses the (n−1)th compressed data Fc(n−1) into (n−1)th decompressed data Fd(n−1) to output the (n−1)th decompressed data Fd(n−1). The third decoder953receives the (n−2)th compressed data Fc(n−2) and decompresses the (n−2)th compressed data into (n−2)th decompressed data Fd(n−2) to output the (n−2)th decompressed data Fd(n−2).

The compensator960receives the n-th, (n−1)th and (n−2)th decompressed data Fd(n), Fd(n−1) and Fd(n−2) from the first, second and third decoders951,952and953, respectively. The compensator960outputs first compensation data Fd″(n−1) based on the n-th, (n−1)th and (n−2)th decompressed data Fd(n), Fd(n−1) and Fd(n−2).

The data selector970receives the first compensation data Fd″(n−1), the n-th frame data F(n) and the selection signal S1from the comparator940to output data F′(n−1). Particularly, the data selector970outputs the n-th frame data F(n) as the output data F′(n−1) when the selection signal S1having the first state is input. The data selector970outputs the first compensation data Fd″(n−1) as the output data F′(n−1) when the selection signal S1having the second state is input.

As shown inFIG. 7, the compensator960includes a first compensator961and a second compensator962.

The first compensator961outputs second compensation data Fd′(n−1) based on the (n−1)th decompressed data Fd(n−1) and the (n−2)th decompressed data Fd(n−2). The second compensator962outputs the first compensation data Fd″(n−1) based on the second compensation data Fd′(n−1) and the n-th decompressed data Fd(n).

The first compensator961outputs the (n−1)th decompressed data Fd(n−1) when the difference between the (n−2)th decompressed data Fd(n−2) and the (n−1)th decompressed data Fd(n−1) is smaller than a predetermined reference value. First compensator961outputs the second compensation data Fd′(n−1) that is increased by a predetermined compensated value over the (n−1)th decompressed data Fd(n−1) when the difference value is larger than the reference value.

The second compensator962receives the second compensation data Fd′(n−1) and the n-th decompressed data Fd(n) to output first compensation data Fd″(n−1). As an example of the present embodiment, the first compensation data Fd″(n−1) has an intermediate value between the second compensation data Fd′(n−1) and the n-th decompressed data Fd(n).

According to another embodiment of the present invention, the data compensating circuit900further includes a look up table (LUT, not shown) having predetermined compensation data according to the values of the second compensation data Fd′(n−1) and the n-th decompressed data Fd(n). Thus, the second compensator962may output a compensation data based on the second compensation data Fd′(n−1) and the n-th decompressed data Fd(n) from the LUT as the first compensation data Fd″(n−1).

The data selector970outputs either the first compensation data Fd″(n−1) or the n-th frame data F(n) as the output data F′(n−1) according to the state of the selection signal S1.

Thus, for displaying a freeze-frame image, the data compensating circuit900outputs the n-th frame data F(n) that is not compressed, thereby preventing damage of data. Also, when the freeze-frame image is converted into a moving image, the data compensating circuit900outputs an intermediate value based on data from the freeze-frame image and data of the moving image, thereby preventing damage of the data at the conversion moment.

FIG. 8is a block diagram showing a liquid crystal display apparatus having the data compensating circuit shown inFIG. 1.

Referring toFIG. 8, a liquid crystal display apparatus1000includes a display part300displaying an image, a gate driving circuit400and a data driving circuit500driving the display part300, a gray-scale voltage generator800connected to the data driving circuit500and a timing controller600controlling the drive of the gate driving circuit400and the data driving circuit500.

A plurality of gate lines GL1˜GLn receiving a gate voltage and a plurality of data lines DL1˜DLm receiving a data voltage are arranged on the display part300. The gate lines GL1˜GLn and the data lines DL1˜DLm define a plurality of pixel areas in a matrix configuration and a pixel310is arranged in each pixel areas. The pixel310includes a thin film transistor311, a liquid crystal capacitor CLCand a storage capacitor CST.

As shown inFIG. 8, the thin film transistor311includes a gate electrode connected to a first gate line GL1, a source electrode connected to a first data line DL1and a drain electrode connected in parallel to the liquid crystal capacitor CLCand the storage capacitor CST.

In the present embodiment, the display part300includes a lower substrate, an upper substrate facing the lower substrate and a liquid crystal layer interposed between the lower substrate and the upper substrate.

The gate lines GL1˜GLn, the data lines DL1˜DLm, the thin film transistor311and pixel electrodes that serve as a first electrode of the liquid crystal capacitor CLCare formed onto the lower substrate. Thus, the thin film transistor311applies the data voltage to the pixel electrodes in response to the gate voltage.

A common electrode that serves as the second electrode of the liquid crystal capacitor CLCis formed onto the upper substrate, and a common voltage is applied to the common electrode. The liquid crystal layer interposed between the pixel electrode and the common electrode serves as the dielectric. Therefore, a voltage corresponding to the electric potential difference between the data voltage and the common voltage is charged into the liquid crystal capacitor CLC.

The gate driving circuit400is electrically connected to the gate lines GL1˜GLn arranged on the display part300to provide the gate voltage to the gate lines GL1˜GLn. The data driving circuit500is electrically connected to the data lines DL1˜DLm arranged on the display part300and selects a gray-scale voltage from the gray-scale voltage generator800to provide the gray-scale voltage to the data lines DL1˜DLm as the data voltage.

The timing controller600receives various control signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, a data enable signal DE, etc. The timing controller600outputs a gate control signal CONT1and a data control signal CONT2based on the various control signals.

The gate control signal CONT1is provided to the gate driving circuit400to control the drive of the gate driving circuit400. The gate control signal CONT1includes a vertical start signal starting the drive of the gate driving circuit400, a gate clock signal determining an output time of the gate voltage and an output enable signal determining an ON pulse width of the gate voltage.

The gate driving circuit400outputs the gate voltage as a gate-on voltage Von or a gate-off voltage Voff in response to the gate control signal CONT1from the timing controller600.

The data control signal CONT2is provided to the data driving circuit500as a signal to control the drive of the data driving circuit500. The data control signal CONT2includes a horizontal start signal that starts the driving of the data driving circuit500, a converting signal that converts the polarity of the data voltage, an output indication signal that determines an output time of the data voltage from the data driving circuit500.

The timing controller600is formed in a chip-shape, and the data compensating circuit100shown inFIG. 1is built in the timing controller600. Particularly, the compressed data is stored in the memory110(shown inFIG. 1), so that the size of the memory110may be reduced and the memory110may be built in the timing controller600.

The data compensating circuit100receives the present frame data F(n) from an external graphic controller (not shown) and compensates the present frame data F(n) into the present compensation data F′(n) during the present frame. The data driving circuit500receives the present compensation data F′(n) in response to the data control signal CONT1from the timing controller600and selects the gray-scale voltage corresponding to the present compensation data F′(n) among gray-scale voltages from the gray-scale voltage generator800. Then, the data driving circuit500converts the selected gray-scale voltage into the data voltage to output the data voltage.

Thus, the display part300displays the image in response to the data voltage and the gate voltage. Particularly, in case of the freeze-frame image, the present compensation data F′(n) is changed into the data voltage corresponding to the present frame data F(n) that is neither compressed nor decompressed, so that the display part300may display the image using the data that is not damaged.

According to the above, the frame data is compressed and stored in the memory, and the compressed frame data that is read out from the memory is provided to the compensator after decompressing the read out frame data. Thus, the size of the memory may be reduced and the memory may be built in the timing controller, thereby decreasing the cost of manufacture and increasing productivity. Further, in case of displaying the freeze-frame image, the present frame data that is neither compressed nor decompressed is used to display the image, thereby preventing damage of data.

The data driving circuit compares compressed data corresponding to three consecutive frames with each other and outputs the present frame data that is not compressed or outputs the intermediate value between the present frame data and the first compensation data according to the result of comparison. Thus, the display apparatus may improve the response speed and prevent damage of data due to the compression.