Voltage level shifter

A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

The application claims priority of Korean Patent Application No. 10-2015-0098303, filed on Jul. 10, 2015, which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the invention relate generally to semiconductor design technology, and more particularly to a voltage level shifter.

2. Description of the Related Art

Use of IoT (i.e., Internet of Things) and wearable electronic devices is expected to increase at a fast pace. One requirement for such devices is low power consumption. Various technologies, have been proposed for providing low power consumption including a technology generally referred to as NTV (Near Threshold Voltage) technology.

NTV technology may generally lower the power consumption of an electronic device by lowering the voltage level of one or more input signals to the device to more closely match the device's performance requirements. For example, NTV technology may lower the voltage level of an input signal to a value close to the threshold voltage level of a transistor, thereby minimizing power consumption. As illustrated inFIG. 1, the voltage level range of an input signal defined in the NTV technology may be defined as a voltage level range FRUGAL between a minimum level of a standard voltage VCORE and threshold voltage level of the transistor.

However, while NTV may lower power consumption, it may also cause operational malfunctioning of the electronic device because existing voltage level shifters used in integrated circuit devices are not capable of handling such voltage changes. For example, as the voltage of a signal inputted to a voltage level shifter is lowered, the performance of one or more transistors of the voltage level shifter may be degraded, thus also affecting the operation of the electronic device, voltage level shifter voltage level shifter voltage level shifter

SUMMARY

Various embodiments of the invention are directed to a voltage level shifter capable of stably shifting an input signal having a broad range of voltage levels from a low voltage level to a high voltage level, to an electronic device incorporating the voltage level shifter and a method of operation thereof. The voltage power shifter may be used with any suitable electronic device, however, it is particularly suited for integrated circuit electronic devices and especially IoT and wearable electronic devices requiring low power consumption. The voltage power shifter is particularly suitable for use in IC electronic devices incorporating power consumption lowering technologies such as NTV technology.

According to an embodiment of the invention, there is provided a voltage level shifter, the voltage level shifter including: a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.

According to another embodiment, a voltage level shifter is provided, the voltage level shifter including: a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node and a complementary output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node pair, to the second supply voltage based on the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the pull-down driving unit and the output node pair, and suitable for lowering voltage levels of the output node pair in stages based on the bias voltage to supply the lowered voltages to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.

DETAILED DESCRIPTION

Various embodiments of the invention will be described below in more detail with reference to the accompanying drawings. It should be understood, however, that the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the invention.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated to clearly illustrate features of the embodiments. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component, but also indirectly coupling another component through an intermediate component.

FIG. 2is a diagram illustrating a voltage level shifter according to an embodiment of the invention.

Referring toFIG. 2, the voltage level shifter may receive input signals INSIG and /INSIG which swing between a ground voltage VSS and a first supply voltage VDD and generate an output signal OUTSIG which swings between the ground voltage VSS and a second supply voltage VDDH higher than a first supply voltage VDD.

The voltage level shifter may include a pull-up driving unit220, a pull-down driving unit240, a bias generation unit260, and a bias operation unit280. The bias operation unit280may include a first bias operation unit282and a second bias operation unit284. The bias generation unit260may include a first bias generation unit264and a second bias generation unit266.

The pull-down driving unit240may pull-down drive output nodes (i.e., an output node pair) OUT_D and OUT_DB to the ground voltage VSS in response to the input signals INSIG and /INSIG. The output signal OUTSIG may be provided through the output node OUT_D.

The pull-up driving unit220may pull-up drive the output nodes OUT_D and OUT_DB to the second supply voltage VDDH according to the input signals INSIG and /INSIG.

The bias generation unit260may generate bias voltages BIAS1and BIAS2fixed to a voltage level higher than the first supply voltage VDD and lower than the second supply voltage VDDH.

The first bias generation unit264may generate the first bias voltage BIAS1fixed to a first level. The first level may be set within a voltage range higher than the first supply voltage VDD and lower than the second supply voltage VDDH.

The second bias generation unit266may generate the second bias voltage BIAS2fixed to a second level higher than the first supply voltage VDD and lower than the first level. For example, a level of the second bias voltage BIAS2may be fixed whenever the second bias voltage BIAS2is lower than the first bias voltage BIAS1.

The bias operation unit280may be coupled between the pull-down driving unit240and the output nodes OUT_D and OUT_DB. During a pull-down operation, the bias operation unit280may lower the level of the output nodes OUT_D and OUT_DB gradually or in stages in response to the bias voltages BIAS1and BIAS2and supply the lowered voltage level to the pull-down driving unit240.

The first bias operation unit282may lower the voltage level of the output nodes OUT_D and OUT_DB by the first level in response to the first bias voltage BIAS1, and supply the lowered voltage level to intermediate nodes MD_D and MD_DB, during a pull-down operation.

The second bias operation unit284may lower the voltage level of the intermediate nodes MD_D and MD_DB by the second level in response to the second bias voltage BIAS2, and supply the lowered voltage to nodes SV_D and SV_DB of the pull-down driving unit240, during a pull-down operation.

The first and second bias operation units282and284may be coupled in a cascade manner between the pull-down driving unit240and the output nodes OUT_D and OUT_DB.

The input signals INSIG and /INSIG may be inputted in a differential manner. For example, the voltage level shifter may be operated in a differential manner while two current paths are coupled to each other in a current mirror type. Thus, the voltage level shifter may further include an inverter INV which outputs the complementary input signal /INSIG and operates between the first supply voltage VDD and the ground voltage VSS. The complementary input signal /INSIG may be generated by inverting the input signal INSIG. The input signals INSIG and /INSIG generated in a differential manner through the inverter INV may be inputted to input nodes IS_D and IS_DB, through which the input signals INSIG and /INSIG may be inputted to the pull-down driving unit240, for determining whether to perform a pull-down operation. Furthermore, the bias operation unit280may be formed between the pull-down driving unit240and the pull-up driving unit220, and coupled in a cascade manner. Thus, although the input signals INSIG and /INSIG may not directly be applied to the pull-up driving unit220, the pull-up driving unit220may determine whether to perform a pull-up operation according to the voltage levels of the input signals INSIG and /INSIG.

Furthermore, when the output nodes OUT_D and OUT_DB, pull-up driven to the second supply voltage VDDH by the pull-up driving unit220, are pull-down driven to the first supply voltage VDD by the pull-down driving unit240, the bias operation unit280may not directly supply the output signal OUTSIG driven to the second supply voltage VDDH to the pull-down driving unit240, but may lower the nodes OUT_B and OUT_DB of the output signals OUTSIG in stages and supply the lowered voltage level to the pull-down driving unit240. This may be because a difference between the second supply voltage VDDH and the first supply voltage VDD is relatively large. For example, the second supply voltage VDDH may range from 3.3V to 1.8V, and the first supply voltage VDD may range from 1.1V to 0.6V. Thus, a maximum difference of 2.7V may occur. Therefore, since the operation in which the output nodes OUT_D and OUT_DB, pull-up driven to the second supply voltage VDDH, may be directly pull-down driven to the first supply voltage VDD by the pull-down driving unit240may not be normally performed, the bias operation unit280may be included between the pull-up driving unit220and the pull-down driving unit240.

For implementing the role of the bias operation unit280, first and second bias voltages BIAS1and BIAS2may be required. The first bias voltage BIAS1may be fixed to the first level set in a range that is higher than the first supply voltage VDD and lower than the second supply voltage VDDH, and the second bias voltage BIAS2may be fixed to the second level. The reason for this will be described below in more detail.

The pull-up driving unit220may include first and second PMOS transistors P1and P2coupled in a current mirror type. The first PMOS transistor P1may have a gate coupled to the complementary output node OUT_DB, a source coupled to the second supply voltage VDDH terminal, and a drain coupled to the output node OUT_D. The second PMOS transistor P2may have a gate coupled to the output node OUT_D, a source coupled to the second voltage VDDH terminal, and a drain coupled to the complementary output node OUT_DB.

The first bias operation unit282may include first and second NMOS transistors N1and N2. The first NMOS transistor N1may have a gate coupled to a node BIAS1_D where the first bias voltage BIAS1is applied, a drain coupled to the output node OUT_D, and a source coupled to the intermediate node MD_D. The second NMOS transistor N2may have a gate coupled to the node BIAS1_D, a drain coupled to the complementary output node OUT_DB, and a source coupled to the complementary intermediate node MD_DB.

The second bias operation unit284may include third and fourth NMOS transistors N3and N4. The third NMOS transistor N3may have a gate coupled to a node BIAS2_D where the second bias voltage BIAS2is applied, a drain coupled to the intermediate node MD_D, and a source coupled to the node SV_DB. The fourth NMOS transistor N4may have a gate coupled to the node BIAS2_D, a drain coupled to the complementary intermediate node MD_DB, and a source coupled to the node SV_D.

The pull-down driving unit240may include fifth and sixth NMOS transistors N5and N6. The fifth NMOS transistor N5may have a gate coupled to the input node IS_DB of the input signals INSIG and /INSIG, a drain coupled to the node SV_DB, and a source coupled to the ground voltage VSS terminal. The sixth NMOS transistor N6may have a gate coupled to the input node IS_D, a drain coupled to the node SV_D, and a source coupled to the ground voltage VSS terminal.

The gates of the first and second NMOS transistors N1and N2included in the first bias operation unit282may have a relatively large gate oxide thickness. On the other hand, the gates of the third and fourth NMOS transistors N3and N4included in the second bias operation unit284and the gates of the fifth and sixth NMOS transistors N5and N6included in the pull-down driving unit240may have a relatively smaller gate oxide thickness.

As the gates of the first and second NMOS transistors N1and N2have a relatively large thickness and the gates of the third to sixth NMOS transistors N3to N6have a relatively small thickness, the following differences may be observed.

First, the thinner NMOS transistors N<3:6> and the thicker NMOS transistors N<1:2> may have different threshold voltage levels. For example, while the thinner NMOS transistors N<3:6> have a threshold voltage level of 0.2V to 0.3V, the thicker NMOS transistors N<1:2> may have a threshold voltage level of 0.4V to 0.5V. That is, as the gate thickness increases the value of the threshold voltage level also increases.

Second, the thinner NMOS transistors N<3:6> and the thicker NMOS transistors N<1:2> may have different limit values for voltage differences among a gate-drain voltage Vgd, a gate-source voltage Vgs, and a drain-source voltage Vds which are set to guarantee reliability. For example, the thinner NMOS transistors N<3:6> may have a smaller limit value than the thicker NMOS transistors N<1:2> for voltage differences among the gate-drain voltage Vgd, the gate-source voltage Vgs, and the drain-source voltage Vds, which are set to guarantee reliability.

Hence, the characteristics each NMOS transistor may be changed by changing the gate thickness of the transistor.

The first and second NMOS transistors N<1:2> having a relatively large gate thickness may be included in the first bias operation unit282, and the third to sixth NMOS transistors N<0:6> having a relatively small thickness may be included in the second bias operation unit284and the pull-down driving unit240.

The fifth and sixth NMOS transistors N<5:6> included in the pull-down driving unit240may have a relatively small gate thickness for reasons which will become apparent from the following description.

The input signals INSIG and /INSIG may swing between the first supply voltage VDD and the ground voltage VSS. The first supply voltage VDD may need to satisfy the voltage level region defined in the NTV technology, that is, the voltage level region FRUGAL between the minimum level of the standard voltage VCORE and the threshold voltage level of the transistor inFIG. 1. For example, the first supply voltage VDD may have a voltage level region of 0.6V to 1.1V, and the voltage level region may be considered as a very low voltage level region.

In order for the pull-down driving unit240to normally operate when the input signals INSIG and /INSIG have a very low voltage level region, the threshold voltage level of the fifth and sixth NMOS transistors N<5:6> included in the pull-down driving unit240may need to be maintained at a relatively low level. For example, the pull-down driving unit240may include the first and sixth NMOS transistors N<5:6> having a threshold voltage level of 0.2 to 0.3V, to stably operate even when the input signals INSIG and /INSIG may have the lowest voltage level of 0.6V.

The reason why the first and second NMOS transistors N<1:2> having a relatively large gate thickness are included in the first bias operation unit282and the third to sixth NMOS transistors N<3:4> having a relatively small thickness are included in the second bias operation unit284will become apparent from the following description.

The first bias operation unit282and the second bias operation unit284may be pull-up driven by the pull-up driving unit220, lower the second supply voltage VDDH applied to the output nodes OUT_D and OUT_DB in stages, and supply the lowered second supply voltage VDDH to the pull-down driving unit240.

The first and second NMOS transistors N<1:2> included in the first bias operation unit282may directly receive the relatively high second supply voltage VDDH through the output nodes OUT_D and OUT_DB that are directly coupled to the drains thereof. Thus, the first and second NMOS transistors N<1:2> may have a relatively large gate thickness, to secure the reliability of the transistors while lowering the second supply voltage VDDH.

On the other hand, since the sources of the first and second NMOS transistors N<1:2> included in the first bias operation unit282and the drains of the third and fourth NMOS transistors N<3:4> included in the second bias operation unit284are coupled in a cascade manner around the intermediate nodes MD_D and MD_DB, a lower level than the second supply voltage VDDH may be applied to the intermediate nodes MD_D and MD_DB. Thus, the third and fourth NMOS transistors N<3:4> may have a relatively small gate thickness, for lowering the voltage level of the intermediate nodes MD_D and MD_DB while maintaining the minimum resistance value.

Although the first and second NMOS transistors N<1:2> included in the first bias operation unit282have a relatively large gate thickness and the third to fourth NMOS transistors N<3:4> included in the second bias operation unit284have a relatively small gate thickness, another condition may need to be satisfied, for lowering the second supply voltage VDDH applied to the output node OUT_D in stages. That is, when the first bias voltage BIAS1applied to the first bias operation unit282is fixed to the first level and the second bias voltage BIAS2applied to the second bias operation unit284is fixed to the second level, the second supply voltage VDDH applied to the output node OUT_D may be lowered in stages through the first and second bias operation units282and284, and then supplied to the pull-down driving unit240.

The first and second levels may be set according to the following four conditions.

The first condition is where the first bias voltage BIAS1fixed to the first level is applied to the gates of the first and second NMOS transistors N<1:2> included in the first bias operation unit.

The second condition is where the second bias voltage BIAS2fixed to the second level is applied to the gates of the third and fourth NMOS transistors N<3:4> Included in the second bias operation unit.

The third condition is where the first and second NMOS transistors N<1:2> are coupled in a cascade manner.

The fourth condition is where the first and second NMOS transistors N<1:2> have a relatively large gate thickness and the third and fourth NMOS transistors N<3:4> have a relatively less gate oxide thickness.

Due to the configuration based on the first condition of the above four conditions, the first level may need to be lower than the second supply voltage VDDH. This may be because a difference in gate-drain voltage Vgd between the first and second NMOS transistors N<1:2> may need to be set to a voltage level that may guarantee reliability. That is, the drains and sources of the first and second NMOS transistors N<1:2> may have a certain difference in response to the first bias voltage BIAS1, and the difference may be set to such a voltage level that may guarantee reliability.

Due to the configuration based on the third and fourth conditions, the first level may need to be fixed to a proper value in a range between the second supply voltage VDDH and the second level. Furthermore, due to the configuration based on the second condition, the second level may need to be lower than the first level. This may be because a difference in drain-source voltage Vds between the first and second NMOS transistors N<1:2> and a difference in gate-drain voltage Vgd between the third and fourth NMOS transistors N<3:4> need to be set to a voltage level that may guarantee the reliability of the transistor operation. That is, the drains and sources of the second and fourth NMOS transistors N<3:4> may have a certain difference in response to the second bias voltage BIAS2, and the difference may be set to a voltage level that may guarantee reliability.

Furthermore, when the above four conditions are satisfied, the first and second levels may be determined to minimize the resistance values of the first to fourth NMOS transistors N<1:4> which operate in response to the first and second bias voltages BIAS<1:2>.

For example, when the second supply voltage VDDH ranges from 1.8V to 3.3V, the first supply voltage VDD ranges from 0.6V to 1.1V, the threshold voltage level of the first and second NMOS transistors N<1:2> is 0.5V, and the threshold voltage level of the third and fourth NMOS transistor N<3:4> is 0.3V, the first level may be fixed to 1.98V, and the second level may be fixed to 1.21V.

Although a voltage of 1.8V to 3.3V is applied to the drains of the first and second NMOS transistors N<1:2>, that is, the output nodes OUT_D and OUT_DB, the drain-gate voltage Vdg of the first and second NMOS transistors N<1:2> may range from −0.18V to 1.32V, the drain-source voltage Vds may range from 0.32V to 1.82V, the gate-source voltage Vgs may be set to 0.5V, and the intermediate nodes MD_D and MD_DB may have a voltage of 1.48V at all times, because the first bias voltage BIAS1is 1.98V. Thus, while a voltage difference, which is enough to guarantee the reliability of the first and second NMOS transistors N<1:2> is provided, the voltage level applied to the intermediate nodes MD_D and MD_DB may have a stable state, regardless of whether the second supply voltage VDDH applied to the output nodes OUT_D and OUT_DB is significantly changed.

Furthermore, although a voltage of 1.48V is applied to the drains of the third and fourth NMOS transistors N<3:4>, that is, the Intermediate nodes MD_D and MD_DB, the drain-gate voltage Vdg of the third and fourth NMOS transistors N<3:4> may be set to 0.27V, the drain-source voltage Vds may be set to 0.57V, the gate-source voltage Vgs may be set to 0.3V, and the nodes SV_D and SV_DB may have a voltage of 0.91V at all times, because the second bias voltage BIAS2is 1.21V. Thus, a voltage difference, which is enough to guarantee the reliability of the third and fourth NMOS transistors N<3:4> may be provided.

Furthermore, since a voltage of 0.91V is applied to the drains of the fifth and sixth NMOS transistors N<5:6> included in the pull-down driving unit240, that is, the nodes SV_D and SV_DB, the drain-gate voltage Vdg of the fifth and sixth NMOS transistors N<5:6> may range from 0.31V to −0.19V, the drain-source voltage Vds may range from 0.61V to 0.11V, and the gate-source voltage Vgs may be set to 0.3V, even though the input signals INSIG and /INSIG applied to the gates have a voltage of 0.6V to 1.1V. Thus, the fifth and sixth NMOS transistors N<5:6> may be normally pull-down driven.

FIG. 3is a detailed circuit diagram of the bias generation unit260of the level shifter illustrated inFIG. 2.

Referring toFIG. 3, the bias generation unit260may further include an operation control unit262in addition to the first and second bias generation units264and266.

The operation control unit262may detect whether the first supply voltage VDD and the second supply voltage VDDH are turned on/off based on the preset initial level, and may control the operations of the first and second bias generation units264and266according to the detection result.

According to some embodiments, the operation control unit262may be required because a method for selectively turning on/off the first supply voltage VDD and the second supply voltage VDDH may be used. Also, the control method may be changed according to the type of a device to which the voltage level shifter is applied. For example, a part of the voltages may be turned off at the exact point of time when the modified power is initially supplied to the corresponding device.

In this way, when a specific voltage is turned off, the turning-off of the voltage may be detected to properly control the operation of the voltage level shifter. Hence, a malfunction of the voltage level shifter may be prevented while at the same preventing excess power consumption.

The operation control unit262may be used to control the operation of the voltage level shifter. An example operation control method for the operation control unit262is described in the following Table 1.

Referring to Table 1, when the first and second supply voltage levels VDD and VDDH become lower than the initial level and are detected as OFF, the operation control unit262may not perform a compulsory control operation on the first and second bias generation units264and266(i.e., no action required).

When the first supply voltage VDD becomes lower than the initial level and is detected as OFF and the second supply voltage VDDH becomes higher than the initial level and is detected as ON, the operation control unit262may control the first bias generation unit264to fix the first bias voltage BIAS1to the ground voltage VSS, but may not perform a compulsory control operation on the second bias generation unit266(i.e., no action required).

When the first supply voltage VDD becomes higher than the initial level and is detected as ON and the second supply voltage VDDH becomes lower than the initial level and is detected as OFF, the operation control unit262may not perform a compulsory control operation on the first bias generation unit264, but may control the second bias generation unit266to fix the second bias voltage BIAS2to the second level (i.e., normal operation).

When the first and second supply voltage levels VDD and VDDH become higher than the initial level and are detected as ON, the operation control unit262may control the first and second bias generation units264and266to fix the first and second bias voltages BIAS1and BIAS2to the first and second levels, respectively (i.e., normal operation).

According to an embodiment of the invention, when shifting an input signal having a low voltage level to a high voltage level, the voltage level shifter may lower the driving voltage having a high voltage level in stages, and may supply the lowered driving voltage to a transistor to which the input signal having a low voltage level is applied. Through this operation, the transistor may be stably operated even when receiving an input signal having a low voltage level, and thus the voltage level shifter may be stably operated.

For example, the positions and types of the logic gates and transistors used in the above-described embodiments may be set in different manners according to the polarities of Input signals.