Bonding pad on IC substrate and method for making the same

A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the fabrication of semiconductor devices and, more particularly, to a novel bonding pad structure on IC substrate and a manufacturing method thereof, which is particularly compatible with wire bonding, tape automated bonding (TAB), chip-on-film (COF) bonding or chip-on-glass (COG) bonding processes.

2. Description of the Prior Art

The reduction of the feature sizes of semiconductor devices using state-of-the-art semiconductor techniques have dramatically increased the device packing density of a single integrated circuit (IC) chip. However, as the device packing density increases, it is necessary to increase the number of electrical metal interconnect layers on the IC chip to effectively wire up the discrete devices on a substrate while reducing the chip size. For example, having two to six levels of metal interconnect layers in a single IC chip is a commonplace in this field.

After completing the multilevel interconnect structure, bonding pads are formed on the top surface of the interconnect structure to provide external electrical connections to the chip or die. A passivation layer is applied, such as silicon oxide, silicon nitride, silicon oxy-nitride or a combination thereof to protect the chip from moisture and contamination. After the passivation layer is formed, die containing a plurality of circuit patterns is connected to a package substrate. The package substrate may have a plurality of pins for connecting the circuitry to an external printed circuit board.

One method for forming electrical connections between the die and the package substrate is wire bonding. A corresponding set of contacts is located on the package substrate. A connecting wire is bonded to connect each bonding pad to a respective contact on the package substrate, using a method such as ultrasonic bonding. Following wire bonding, the package is encapsulated and sealed.

The reliability of the bonding process is particularly critical since the bonding process occurs so late in the production cycle. Die being packaged have typically already been tested and sorted. Any problems in the wire bonding process thus impact only good die. Secure, reliable bonding of the wire to the bonding pad requires that the bonding pad be formed of metals compatible with the bonding process. Aluminum and aluminum alloys are typically employed to achieve the most reliable bonds.

To prevent the shifting of bonding wires during the step of injecting the plastic material or the lengthening of the bonding wires, the bonding pads have been disposed on the peripheral of the chips. Therefore, longer conductive traces are needed to connect the device to the bonding pads. As the trend of chip advances toward higher speeds and higher capabilities, the number of I/O connections rapidly increases. However, the high inductance created in the connection of bonding pads and bonding wires obstructs the high-speed operation of the chips.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide a novel multi-layer bonding pad or bump structure directly bonded to a copper pad or layer of an IC substrate, which is particularly compatible with standard wire bonding, tape automated bonding (TAB), chip-on-film (COF) bonding, or chip-on-glass (COG) bonding processes.

According to the claimed invention, a bonding pad structure is disclosed. The bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

DETAILED DESCRIPTION

This invention pertains to the use of an embossing process to form a novel multi-layer bonding pad or bump structure directly bonded to a copper pad or aluminum layer of an IC substrate, which is particularly compatible with standard wire bonding, tape automated bonding (TAB), chip-on-film (COF) bonding, or chip-on-glass (COG) bonding processes.

Please refer toFIG. 1.FIG. 1is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with a first preferred embodiment of this invention. As shown inFIG. 1, an integrated circuit (IC) substrate10is provided. The IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit. The inlaid copper contact pad12may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.

A diffusion barrier (not shown) may be formed to encapsulate the inlaid copper contact pad12in order to prevent copper from diffusing into the IC substrate10. Suitable materials for the diffusion barrier may include, but not limited to, tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), niobium (Nb), aluminum silicate, titanium nitride (TiN) and TiSiN.

The insulating layer surrounding the inlaid copper contact pad12includes, but not limited to, low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHzcomposition.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. As can be seen inFIG. 1, the top surface of the inlaid copper contact pad12is approximately coplanar with the top surface of the IC substrate10. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14.

Typically, the opening16has a dimension of about 0.5-15 micrometers. In another case, the opening16may range between 15 and 300 micrometers.

An electrically conductive adhesion/barrier layer18is directly bonded to the inlaid copper contact pad12and extends to the top surface of the passivation layer14. As can be seen inFIG. 1, the electrically conductive adhesion/barrier layer18, which contours the top surface of the passivation layer14and sidewalls of the opening16, seals the opening16and prevents the inlaid copper contact pad12from contacting with the air. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

According to this preferred embodiment, the electrically conductive adhesion/barrier layer18comprises titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), titanium nitride (TiN), titanium tungsten (TiW), vanadium (V), chrome (Cr), copper (Cu), CrCu, tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or composite layer of the above-described materials. The metal suited for the electrically conductive adhesion/barrier layer18may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods.

A bonding metal layer20is disposed on the electrically conductive adhesion/barrier layer18. A gap or undercut15is formed between a bottom surface of the bonding metal layer20and the top surface of the passivation layer14. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals.

The metal suited for the bonding metal layer20may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods. Preferably, the bonding metal layer20is made of electroplating or electroless Au and is particularly suites for the wire bonding process, TAB process, COF process and COG process.

The total thickness h1, which is combination of the thickness of the bonding metal layer20and the thickness of the underlying electrically conductive adhesion/barrier layer18, may range between 2 and 30 micrometers, preferably 2-15 micrometers for wire bonding applications, and 8-30 micrometers for TAB, COF or COG applications.

Please refer toFIG. 2.FIG. 2is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like elements, layers or regions. As shown inFIG. 2, an IC substrate10is provided. Likewise, the IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit. The inlaid copper contact pad12may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional CMP process.

Typically, a diffusion barrier (not shown) is deposited on interior surface of the trench opening to encapsulate the inlaid copper contact pad12in order to prevent copper from diffusing into the IC substrate10. Suitable materials for the diffusion barrier may include, but not limited to, tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), niobium (Nb), aluminum silicate, titanium nitride (TiN) and TiSiN.

The insulating layer surrounding the inlaid copper contact pad12includes, but not limited to, low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHzcomposition.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. The top surface of the inlaid copper contact pad12is approximately coplanar with the top surface of the IC substrate10. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14.

Typically, the opening16has a dimension of about 0.5-15 micrometers. In another case, the diameter of the opening16may range between 15 and 300 micrometers.

An electrically conductive adhesion/barrier layer18is directly bonded to the inlaid copper contact pad12and extends to the top surface of the passivation layer14. The electrically conductive adhesion/barrier layer18, which contours the top surface of the passivation layer14and sidewalls of the opening16, seals the opening16and prevents the inlaid copper contact pad12from contacting with the air. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

An intermediate metal layer22is disposed on the electrically conductive adhesion/barrier layer18. According to this preferred embodiment, the intermediate metal layer22is made of nickel (>95% wt.). Preferably, the intermediate metal layer22has a thickness of about 0.1-10 micrometers.

A bonding metal layer20is disposed on the intermediate metal layer22. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals. Preferably, the bonding metal layer20is made of gold. In this case, nickel acts as a strong diffusion barrier and avoids the formation of eutectic inter-metal compounds. On the other hand, nickel also prevents the surface oxidation during gold plating.

The metal suited for the bonding metal layer20may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods. Preferably, the bonding metal layer20is made of electroplating or electroless Au and is particularly suites for the wire bonding process, TAB process, COF process and COG process.

Please refer toFIG. 3.FIG. 3is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like elements, layers or regions. As shown inFIG. 3, an IC substrate10is provided. Likewise, the IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit.

The insulating layer surrounding the inlaid copper contact pad12may include low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHzcomposition.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. The top surface of the inlaid copper contact pad12is approximately coplanar with the top surface of the IC substrate10. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14. The opening16has a dimension of about 0.5-300 micrometers.

An electrically conductive adhesion/barrier layer18is directly bonded to the inlaid copper contact pad12and extends to the top surface of the passivation layer14. The electrically conductive adhesion/barrier layer18, which contours the top surface of the passivation layer14and sidewalls of the opening16, seals the opening16and prevents the inlaid copper contact pad12from contacting with the air. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

A first intermediate metal layer32is disposed on the electrically conductive adhesion/barrier layer18. According to this preferred embodiment, the first intermediate metal layer32is made of copper (>95% wt.). The first intermediate metal layer32has a thickness of about 0.1-10 micrometers.

A second intermediate metal layer22is disposed on the first intermediate metal layer32. According to this preferred embodiment, the second intermediate metal layer22is made of nickel (>95% wt.). The second intermediate metal layer22has a thickness of about 0.1-10 micrometers.

A bonding metal layer20is disposed on the second intermediate metal layer22. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals. Preferably, the bonding metal layer20is made of gold. In this case, nickel layer22acts as a strong diffusion barrier. Nickel layer22also prevents the surface oxidation of the copper layer32.

The metal suited for the bonding metal layer20may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods. Preferably, the bonding metal layer20is made of electroplating or electroless Au and is particularly suites for the wire bonding process, TAB process, COF process and COG process. The thickness of the bonding metal layer20may range between 2 and 30 micrometers. According to this embodiment, the total thickness h2may range between 30 and 300 micrometers.

Please refer toFIG. 4.FIG. 4is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with another preferred embodiment of this invention. As shown inFIG. 4, an IC substrate10is provided. The IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit. The inlaid copper contact pad12may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.

A diffusion barrier (not shown) may be formed to encapsulate the inlaid copper contact pad12in order to prevent copper from diffusing into the IC substrate10. Suitable materials for the diffusion barrier may include, but are not limited to, tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), niobium (Nb), aluminum silicate, titanium nitride (TiN) & TiSiN The diffusion barrier can be under the inlaid copper contact pad12and at a sidewall of the inlaid copper contact pad12.

The insulating layer surrounding the inlaid copper contact pad12includes, but not limited to, low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHzcomposition.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. As can be seen inFIG. 1, the top surface of the inlaid copper contact pad12is approximately coplanar with the top surface of the IC substrate10. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14.

Typically, the opening16has a dimension of about 0.5-15 micrometers. In another case, the opening16may range between 15 and 300 micrometers.

A metal cap layer42is directly bonded to inlaid copper contact pad12and extends to the top surface of the passivation layer14. The metal cap layer42, which contours the top surface of the passivation layer14and sidewalls of the opening16, seals the opening16and prevents the inlaid copper contact pad12from contacting with the air.

According to this preferred embodiment, the metal cap layer42comprises aluminum (Al), gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals.

In another case, a barrier layer (not explicitly shown) may be interposed between the metal cap layer42and the inlaid copper contact pad12. The barrier layer may comprise titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), titanium nitride (TiN), titanium tungsten (TiW), vanadium (V), chrome (Cr), copper (Cu), CrCu, tantalum (Ta), tantalum nitride (TaN), or alloys thereof.

An electrically conductive adhesion/barrier layer18is directly bonded to the metal cap layer42. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

According to this preferred embodiment, the electrically conductive adhesion/barrier layer18comprises titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), titanium nitride (TiN), titanium tungsten (TiW), vanadium (V), chrome (Cr), copper (Cu), CrCu, tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or composite layer of the above-described materials. The metal suited for the electrically conductive adhesion/barrier layer18may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods.

A bonding metal layer20is disposed on the electrically conductive adhesion/barrier layer18. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals. Preferably, the bonding metal layer20is made of electroplating or electroless Au and is particularly suites for the wire bonding process, TAB process, COF process and COG process.

Please refer toFIG. 5.FIG. 5is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with another preferred embodiment of this invention. As shown inFIG. 5, an IC substrate10is provided. The IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit. The inlaid copper contact pad12may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14. Typically, the opening16has a dimension of about 0.5-15 micrometers. In another case, the diameter of the opening16may range between 15 and 300 micrometers.

A metal cap layer42is directly bonded to inlaid copper contact pad12and extends to the top surface of the passivation layer14. The metal cap layer42, which contours the top surface of the passivation layer14and sidewalls of the opening16, seals the opening16and prevents the inlaid copper contact pad12from contacting with the air.

According to this preferred embodiment, the metal cap layer42comprises aluminum (Al), gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals.

An electrically conductive adhesion/barrier layer18is directly bonded to the metal cap layer42. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

A first intermediate metal layer32is disposed on the electrically conductive adhesion/barrier layer18. According to this preferred embodiment, the first intermediate metal layer32is made of copper (>95% wt.). The first intermediate metal layer32has a thickness of about 0.1-10 micrometers.

A second intermediate metal layer22is disposed on the first intermediate metal layer32. According to this preferred embodiment, the second intermediate metal layer22is made of nickel (>95% wt.). The second intermediate metal layer22has a thickness of about 0.1-10 micrometers.

A bonding metal layer20is disposed on the second intermediate metal layer22. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals. The total thickness h3may range between 2 and 30 micrometers. In another case, the total thickness h3may range between 30 and 300 micrometers, and in such case, it becomes a bonding metal post structure landing on the contact pad12of the IC substrate10.

Please refer toFIG. 6.FIG. 6is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with another preferred embodiment of this invention. As shown inFIG. 6, an IC substrate10is provided. The IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit. A diffusion barrier (not shown) may be formed to encapsulate the inlaid copper contact pad12in order to prevent copper from diffusing into the IC substrate10. Suitable materials for the diffusion barrier may include, but not limited to, tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), niobium (Nb), aluminum silicate, titanium nitride (TiN) and TiSiN.

The insulating layer surrounding the inlaid copper contact pad12includes, but not limited to, low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHzcomposition.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. As can be seen inFIG. 6, the top surface of the inlaid copper contact pad12is approximately coplanar with the top surface of the IC substrate10. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14. Typically, the opening16has a dimension of about 0.5-15 micrometers.

A metal cap layer42is directly bonded to inlaid copper contact pad12and extends to the top surface of the passivation layer14. The metal cap layer42seals the opening16and prevents the inlaid copper contact pad12from contacting with the air. The difference between the bonding pad structure ofFIG. 4and the bonding pad structure ofFIG. 6is that a gap65is formed between a bottom surface of the rim portion44of the metal cap layer42and the top surface of the passivation layer14, such that the rim portion44of the metal cap layer42impends over the passivation layer14.

According to this preferred embodiment, the metal cap layer42comprises aluminum (Al), gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals.

In another case, a barrier layer (not explicitly shown) may be interposed between the metal cap layer42and the inlaid copper contact pad12. The barrier layer may comprise titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), titanium nitride (TiN), titanium tungsten (TiW), vanadium (V), chrome (Cr), copper (Cu), CrCu, tantalum (Ta), tantalum nitride (TaN), or alloys thereof.

An electrically conductive adhesion/barrier layer18is directly bonded to the metal cap layer42. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

According to this preferred embodiment, the electrically conductive adhesion/barrier layer18comprises titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), titanium nitride (TiN), titanium tungsten (TiW), vanadium (V), chrome (Cr), copper (Cu), CrCu, tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or composite layer of the above-described materials. The metal suited for the electrically conductive adhesion/barrier layer18may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods.

A bonding metal layer20is disposed on the electrically conductive adhesion/barrier layer18. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals. Preferably, the bonding metal layer20is made of electroplating or electroless Au and is particularly suites for the wire bonding process, TAB process, COF process and COG process.

Please refer toFIG. 7.FIG. 7is a schematic, cross-sectional diagram illustrating a gold bonding pad structure in accordance with another preferred embodiment of this invention. As shown inFIG. 7, an IC substrate10is provided. The IC substrate10comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

An inlaid copper contact pad12is formed at the top surface of the IC substrate10. In other embodiments, the inlaid copper contact pad12may be replaced with an aluminum layer. The inlaid copper contact pad12is part of the top metal layer of the multilevel interconnection of the IC substrate10and is electrically connected with the underlying integrated circuit. The inlaid copper contact pad12may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.

A passivation layer14covers the top surface of the IC substrate10including the inlaid copper contact pad12. The inlaid copper contact pad12is partially exposed by an opening16that is formed in the passivation layer14. Typically, the opening16has a dimension of about 0.5-15 micrometers. In another case, the diameter of the opening16may range between 15 and 300 micrometers.

A metal cap layer42is directly bonded to inlaid copper contact pad12and extends to the top surface of the passivation layer14. The metal cap layer42seals the opening16and prevents the inlaid copper contact pad12from contacting with the air. The difference between the bonding pad structure ofFIG. 5and the bonding pad structure ofFIG. 7is that a gap75is formed between a bottom surface of the rim portion44of the metal cap layer42and the top surface of the passivation layer14, such that the rim portion44of the metal cap layer42impends over the passivation layer14.

According to this preferred embodiment, the metal cap layer42comprises aluminum (Al), gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals.

An electrically conductive adhesion/barrier layer18is directly bonded to the metal cap layer42. Preferably, the electrically conductive adhesion/barrier layer18has a thickness ranging between 0.1 micrometer and 10 micrometers.

A first intermediate metal layer32is disposed on the electrically conductive adhesion/barrier layer18. According to this preferred embodiment, the first intermediate metal layer32is made of copper (>95% wt.). The first intermediate metal layer32has a thickness of about 0.1-10 micrometers.

A second intermediate metal layer22is disposed on the first intermediate metal layer32. According to this preferred embodiment, the second intermediate metal layer22is made of nickel (>95% wt.). The second intermediate metal layer22has a thickness of about 0.1-10 micrometers.

A bonding metal layer20is disposed on the second intermediate metal layer22. According to this preferred embodiment, suitable materials for the bonding metal layer20include gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), ruthenium (Ru), rhenium (Re), SnPb, SnAg, or alloys thereof, or composite layers of the above-described metals. The total thickness h3may range between 2 and 30 micrometers. In another case, the total thickness h3may range between 30 and 300 micrometers, and in such case, it becomes a bonding metal post structure landing on the contact pad12of the IC substrate10.

Please refer toFIG. 8.FIG. 8is a schematic, cross-sectional diagram illustrating exemplary gold and solder bonding structures on one chip in accordance with another preferred embodiment of this invention. As shown inFIG. 8, an IC substrate100is provided. The IC substrate100comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

Inlaid copper contact pads120a,120band120care formed at the top surface of the IC substrate100. These inlaid copper contact pads are part of the top metal layer of the multilevel interconnection of the IC substrate100and is respectively electrically connected with the underlying integrated circuit. The inlaid copper contact pads120a,120band120cmay be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.

A passivation layer140covers the top surface of the IC substrate100. The inlaid copper contact pads120a,120band120care exposed by openings160a,160band160crespectively, which are formed in the passivation layer140. Typically, the openings160,160band160chave a dimension of about 0.5-15 micrometers. In another case, the diameter of the openings160,160band160cmay range between 15 and 300 micrometers.

This preferred embodiment features the gold bonding structure300a, gold pad-on-redistribution layer structure300band solder bump structure300c, which are simultaneously fabricated on the IC substrate100. The gold bonding structure300a, gold pad-on-redistribution layer structure300band solder bump structure300care landed on the inlaid copper contact pads120a,120band120c, respectively.

The gold bonding structure300bcomprises an electrically conductive adhesion/barrier layer180athat is directly bonded to the inlaid copper contact pad120aand extends to the top surface of the passivation layer140. The electrically conductive adhesion/barrier layer180a, which contours the top surface of the passivation layer140and sidewalls of the opening160a, seals the opening160aand prevents the inlaid copper contact pad120afrom contacting with the air. Preferably, the electrically conductive adhesion/barrier layer180ahas a thickness ranging between 0.1 micrometer and 10 micrometers.

A first intermediate metal layer132ais disposed on the electrically conductive adhesion/barrier layer180a. According to this preferred embodiment, the first intermediate metal layer132ais made of copper (>95% wt.). The first intermediate metal layer132ahas a thickness of about 0.1-10 micrometers. A second intermediate metal layer122ais disposed on the first intermediate metal layer132a. According to this preferred embodiment, the second intermediate metal layer122ais made of nickel (>95% wt.). The second intermediate metal layer122ahas a thickness of about 0.1-10 micrometers. An electroless Au layer190ais disposed on the second intermediate metal layer122a. An Au bonding metal layer200ais disposed on the electroless Au layer190a.

The gold pad-on-redistribution layer structure300bcomprises an electrically conductive adhesion/barrier layer180bthat is directly bonded to the inlaid copper contact pad120band extends to the top surface of the passivation layer140. The electrically conductive adhesion/barrier layer180b, which contours the top surface of the passivation layer140and sidewalls of the opening160b, seals the opening160band prevents the inlaid copper contact pad120bfrom contacting with the air. Preferably, the electrically conductive adhesion/barrier layer180bhas a thickness ranging between 0.1 micrometer and 10 micrometers.

A first intermediate metal layer132bis disposed on the electrically conductive adhesion/barrier layer180b. The first intermediate metal layer132bis made of copper (>95% wt.). The first intermediate metal layer132bhas a thickness of about 0.1-10 micrometers. A second intermediate metal layer122bis disposed on the first intermediate metal layer132b. The second intermediate metal layer122bis made of nickel (>95% wt.). The second intermediate metal layer122bhas a thickness of about 0.1-10 micrometers. The electrically conductive adhesion/barrier layer180b, first intermediate metal layer132band second intermediate metal layer122bconstitute a redistribution trace layer280, which is an additional metal path for electrical interconnect on which the connections from the original contact pad120bis redistributed over the surface of the passivation layer140. An Au bonding metal layer200bis disposed on the other end of the redistribution trace layer280. Likewise, an electroless Au layer190ais interposed between the Au bonding metal layer200band the second intermediate metal layer122b.

The solder bump structure300ccomprises an electrically conductive adhesion/barrier layer180cthat is directly bonded to the inlaid copper contact pad120cand extends to the top surface of the passivation layer140. The electrically conductive adhesion/barrier layer180c, which contours the top surface of the passivation layer140and sidewalls of the opening160c, seals the opening160cand prevents the inlaid copper contact pad120cfrom contacting with the air. Preferably, the electrically conductive adhesion/barrier layer180chas a thickness ranging between 0.1 micrometer and 10 micrometers.

A first intermediate metal layer132cis disposed on the electrically conductive adhesion/barrier layer180c. According to this preferred embodiment, the first intermediate metal layer132cis made of copper (>95% wt.). The first intermediate metal layer132chas a thickness of about 0.1-10 micrometers. A second intermediate metal layer122cis disposed on the first intermediate metal layer132c. According to this preferred embodiment, the second intermediate metal layer122cis made of nickel (>95% wt.). The second intermediate metal layer122chas a thickness of about 0.1-10 micrometers. A solder bump or post250is disposed on the second intermediate metal layer122c.

The solder bump or post250may be jointed as chip, substrate, passive component such as capacitor or resist, or photodiode sensor, solar cell, etc. Preferably, the solder bump or post250comprises SnPb, SnAg, SnAgCu or Sn alloys. The solder bump or post250can be re-flowed as jointed.

Please refer toFIGS. 9-13.FIGS. 9-13are schematic, cross-sectional diagrams illustrating a method for fabricating the structure shown inFIG. 8. As shown inFIG. 9, an IC substrate100is provided. The IC substrate100comprises therein a plurality of circuit components such as, for example, transistors, memory and/or logic devices, dielectric layers and multilevel interconnection that communicates with the respective circuit components, which are not shown for the sake of simplicity.

Inlaid copper contact pads120a,120band120care formed at the top surface of the IC substrate100. These inlaid copper contact pads are part of the top metal layer of the multilevel interconnection of the IC substrate100and is respectively electrically connected with the underlying integrated circuit. The inlaid copper contact pads120a,120band120cmay be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.

A passivation layer140covers the top surface of the IC substrate100. The inlaid copper contact pads120a,120band120care exposed by openings160a,160band160crespectively, which are formed in the passivation layer140. Typically, the openings160,160band160chave a dimension of about 0.5-15 micrometers. In another case, the diameter of the openings160,160band160cmay range between 15 and 300 micrometers. The passivation layer140may comprise silicon oxide, silicon nitride, silicon oxy-nitride, and a combination thereof, for example, silicon oxide/silicon nitride (ON), silicon oxide/silicon nitride/silicon oxide (ONO), silicon oxy-nitride/silicon oxide/silicon nitride/silicon oxide, silicon oxide/silicon nitride/silicon oxy-nitride/silicon oxide, etc.

An electrically conductive adhesion/barrier layer180is blanket deposited over the IC substrate100. The electrically conductive adhesion/barrier layer180is directly bonded to the inlaid copper contact pads120a,120band120cand extends to the top surface of the passivation layer140. The electrically conductive adhesion/barrier layer180contours the top surface of the passivation layer140and sidewalls of the openings160a,160band160cand seals the openings160a,160band160c. Preferably, the electrically conductive adhesion/barrier layer180ahas a thickness ranging between 0.1 micrometer and 10 micrometers.

As shown inFIG. 10, a patterned photoresist layer400is formed on the electrically conductive adhesion/barrier layer180. The patterned photoresist layer400is formed by conventional lithography methods generally including the steps of photoresist coating, baking, exposure and development. The photoresist may be a dry film. The patterned photoresist layer400has an opening402a, opening402band opening402c. The opening402ais directly above the inlaid copper contact pad120a. The opening402bis directly above the inlaid copper contact pad120band defines a redistribution route. The opening402cis directly above the inlaid copper contact pad120c.

An electroplating process is carried out to plate copper layers132a,132band132cinto the openings402a,402band402c, respectively. The thickness of the copper layers132a,132band132cranges between 0.1 and 10 micrometers. In another case, the thickness of the copper layers132a,132band132cranges between 10 and 250 micrometers. Subsequently, another electroplating process is carried out to plate nickel layers122a,122band122cinto the openings402a,402band402c, respectively. As previously mentioned, the nickel layers122a,122band122cprevent surface oxidation of the underlying copper layer and it also acts as a strong barrier. The patterned photoresist layer400is then stripped off.

As shown inFIG. 11, another patterned photoresist layer500is formed on the IC substrate100. The patterned photoresist layer500has an opening502athat is directly above the inlaid copper contact pad120a, and an opening502bthat is not directly above the inlaid copper contact pad120b. The opening502aexposes a top surface of the nickel layer122a. The opening502bexposes a pre-selected redistribution region of the nickel layer122b. Electroless Au layers190aand190bare plated into the openings502aand502b, respectively. The electroless Au layers190aand190bare also optional. Thereafter, electroplating Au layers200aand200bare plated into the openings502aand502b, respectively. The patterned photoresist layer500is then removed.

As shown inFIG. 12, another patterned photoresist layer600is formed on the IC substrate100. The patterned photoresist layer600has an opening602cthat is directly above the inlaid copper contact pad120cand exposes a top surface of the nickel layer122c. A solder bump250is formed on the exposed nickel layer122cin the opening602c. The patterned photoresist layer600is then removed.

As shown inFIG. 13, after removing the patterned photoresist layer600, an etching process is performed to removed the exposed electrically conductive adhesion/barrier layer180, thereby forming electrically conductive adhesion/barrier layers180a,180band180c.