Method and system for checking frame-length in fibre channel frames

Method and system for checking frame-length in a Fiber Channel frames is provided. The method includes extracting a R_CTL value from a Fiber Channel frame; comparing the extracted R_CTL value of the Fiber Channel frame with R_CTL values stored in a Content Addressable Memory Table; determining a maximum frame-length and a minimum frame-length of the Fiber Channel frame for the extracted R_CTL value from the Content Addressable Memory Table; and marking the Fiber Channel frame so that it can be discarded if the frame-length is less than the minimum frame-length of the Fiber Channel frame or greater than the maximum frame-length of the Fiber Channel frame. The system includes a processor that accesses a CAM stored in memory; and a receive port that extracts and compares a R_CTL value of the Fiber Channel frame.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent application is related to the following US Patent Applications:

Ser. No. 10/894,627 filed on Jul. 20, 2004, entitled “Method and System for Programmable Data Dependent Network Routing”; and

Ser. No. 10/894,547, filed on Jul. 20, 2004, entitled “Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements”; the disclosure of the foregoing applications is incorporated herein by reference in their entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to Fibre Channel network systems, and more particularly, to checking frame-length in Fibre Channel frames.

2. Background of the Invention

Fibre Channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre Channel provides an input/output interface to meet the requirements of both channel and network users.

Fibre Channel supports three different topologies: point-to-point, arbitrated loop and Fibre Channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The Fibre Channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The Fibre Channel fabric topology allows several media types to be interconnected.

Fibre Channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or “F_port”.

A Fibre Channel switch is a multi-port device where each port manages a point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and routes it to another port.

Fibre Channel frames carry information between Fibre Channel Devices which include Host Bus Adapters, Switches and Disk Drives. The components of a Fibre Channel Frame include SOF, Frame Header, Payload, CRC and EOF. Typically, the minimum frame-length of a Fibre frame is 36 bytes and the maximum frame-length of a Fibre Channel frame is 2148 bytes.

Typically, a Fibre Channel device receives an incoming Fibre Channel frame when it detects a Start-Of-Frame (SOF) delimiter. The receive port detects an end of the Fibre Channel frame when it detects an End-Of-Frame (EOF) delimiter or if the maximum frame-length is reached. The receive port of the Fibre Channel device keeps a count of the frame-length of the Fibre Channel frame. The frame-length includes the summation of the length of SOF (4 bytes), Frame Header (24 bytes), Payload (0-2112 bytes), CRC (4 bytes) and EOF (4 bytes). The receive port then determines if the frame-length of the received Fibre Channel frame is within the minimum and maximum frame-length as specified in the Fibre Channel specification. If a violation of the frame-length occurs, then the frame is discarded and an error is reported to a processor.

With the addition of new routing features for example, Virtual Fabric and Inter-Fabric routing, the length of the Frame Header has changed. This addition caused the total frame-length of the Fibre Channel frame to be different than the current maximum and minimum frame-length. When a switch that was designed before these features were introduced receives a Fibre Channel frame, data is corrupted if the EOF is not detected due to the varying lengths of the frame. Furthermore, the current frame-length checking mechanism causes erroneous errors. Therefore, there is a need for a method and system for efficiently checking the frame-length of a Fibre Channel frame with varying frame lengths.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a method for checking frame-length in a Fibre Channel frames is provided. The method includes extracting a R_CTL value from a Fibre Channel frame; comparing the extracted R_CTL value of the Fibre Channel frame with R_CTL values stored in a Content Addressable Memory Table; determining a maximum frame-length and minimum frame-length of the Fibre Channel frame for the extracted R_CTL value from the Content Addressable Memory Table; and marking the Fibre Channel frame so that it can be discarded, if the frame-length is less than the minimum frame-length of the Fibre Channel frame or greater than the maximum frame-length of the Fibre Channel frame.

This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following definitions are provided for convenience as they are typically (but not exclusively) used in the Fibre Channel environment, implementing the various adaptive aspects of the present invention.

“CRC” (cyclic redundancy code): A 4 byte value used for checking the data integrity of a Fibre Channel frame.

“D_ID”: A 24-bit Fibre Channel header field that contains the destination address for a frame.

“Dword: A 4 byte Fibre Channel Data Word.

“EOF”: End-Of-Frame (EOF) delimiter that is the last Data Word of a Fibre Channel frame.

“EOFa”: A frame whose EOF is marked so that the frame is discarded by a destination port, N_Port or NL_Port.

“E_Port”: An expansion port that is used to connect Fibre Channel Switch elements in a Fabric.

“Fabric”: The structure or organization of a group of switches, target and host devices (NL_Port, N_ports etc.).

“F_Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports.

“Fibre Channel ANSI Standard” (“FC-FS-2”): The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others.

“Inter Fabric Header”: The Inter Fabric Routing Extended Header (IFR_Header) is used for routing Fibre Channel frames from one fabric to another. It provides the fabric identifier of the destination fabric, the fabric identifier of the source fabric and information to determine hop count.

“N_Port”: A direct fabric attached port, for example, a disk drive or a HBA.

“NL_Port”: A L_Port that can perform the function of a N_Port.

“R_CTL”: A 8 bit value containing routing information used to route Fibre Channel Frames.

“Switch”: A fabric element conforming to the Fibre Channel Switch standards.

“SOF”: Start_of_Frame (SOF) delimiter that is the first Data Word of a Fibre Channel frame.

“Virtual Fabric” (“VSAN”): As defined by FC-FS-2, Fibre Channel standard, incorporated herein by reference in its entirety, is a Fabric composed of partitions and N_ports having the properties of a single Fabric management domain and Generic Services; and independent from other Virtual Fabrics (e.g. an independent address space).

“Virtual Fabric Header” (VFT_Header): This is a header used for tagging Fibre Channel frames with a Virtual Fabric Identifier (VF_ID) of Virtual Fabric to which the frame belongs.

“Virtual Fabric Identifier” (“VF_ID”): A value that uniquely identifies a Virtual Fabric among plural Virtual Fabrics that shares a set of Switches and N_ports.

To facilitate an understanding of the preferred embodiment, the general architecture and operation of a Fibre channel System and a Fibre Channel switch element will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture.

Fibre Channel System

FIG. 1Ais a block diagram of a fibre channel system100implementing the methods and systems in accordance with the adaptive aspects of the present invention. System100includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device, e.g. server103, disk array105and storage device104. Fabric ports are located in fabric devices such as switch101and102. Arbitrated loop106may be operationally coupled to switch101using arbitrated loop ports (FL_Ports).

The devices ofFIG. 1Aare operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. between server103and storage104. A packet-switched path may be established using multiple links, e.g. an N-Port in server103may establish a path with disk array105through switch102.

Fibre Channel Switch Element

FIB.1B is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.FIG. 1Bprovides the general architecture of a 20-channel switch chassis using the 20port fabric element. Fabric element includes ASIC20with non-blocking Fibre Channel class2(connectionless, acknowledged) service and class3(connectionless, unacknowledged) service between any ports. It is noteworthy that ASIC20may also be designed for class1(connection-oriented) service, within the scope and operation of the present invention as described herein.

The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. AlthoughFIG. 1Bshows 20 ports, the present invention is not limited to any particular number of ports.

ASIC20has 20 ports numbered inFIG. 1Bas GL0through GL19. These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below.

For illustration purposes only, all GL ports are drawn on the same side of ASIC20inFIG. 1B. However, the ports may be located on both sides of ASIC20as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC.

Each port GL0-GL19is comprised of transmit and receive connections to switch crossbar50. Within each port, one connection is through receive buffer52, which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmit buffer54.

Switch crossbar50includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only, switch crossbar50is shown as a single crossbar. Switch crossbar50is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external to ASIC20.

In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/output processor (“IOP”). As seen inFIG. 1B, bi-directional connection to IOP66is routed through port67, which connects internally to a control bus60. Transmit buffer56, receives buffer58, control register62and Status register64connect to bus60. Transmit buffer56and receive buffer58connect the internal connectionless switch crossbar50to IOP66so that it can source or sink frames.

Control register62receives and holds control information from IOP66, so that IOP66can change characteristics or operating configuration of ASIC20by placing certain control words in register62. IOP66can read status of ASIC20by monitoring various codes that are placed in status register64by monitoring circuits (not shown).

FIG. 1Cshows a 20-channel switch chassis S2using ASIC20and IOP66. IOP66inFIG. 1Cis shown as a part of a switch chassis utilizing one or more of ASIC20. S2will also include other elements, for example, a power suplpy (not shown). The 20 GL_Ports correspond to channels C0-C19. Each GL_Port has a serial/deserializer (SERDES) designated as S0-S19. Ideally, the SERDES functions are implemented on ASIC20for efficiency, but may alternatively be external to each GL_Port. The SERDES converts parallel data into a serial data stream for transmission and converts received serial data into parallel data. The 8 bit to 10 bit encoding enables the SERDES to generate a clock signal from the received data stream.

Each GL_Port may have an optical-electric converter, designated as OE0-OE19connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C0-C19. It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters.

FIG. 1Dshows a block diagram of ASIC20with sixteen GL ports and four 10 G (Gigabyte) port control modules designated as XG0-XG3for four 10 G ports designated as XGP0-XGP3. ASIC20include a control port62A that is coupled to IOP66through a PCI connection66A. ASIC20Q also includes a Content Addressable Memory (CAM) Table80that maintains information regarding R_CTL, minimum Fibre Channel frame-length and maximum Fibre Channel frame-length.

CAM table80is stored in memory80A that is accessible to IOP66and other logic. CAM table80is a master copy for the switch element. As described below, each port can have its own CAM table with values that pertain to that particular port. Furthermore, plural ports can share a CAM Table that is located at one of the ports.

FIGS.1E-1/1E-2(jointly referred to asFIG. 1E) show yet another block diagram of ASIC20with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT)69(similar to58,FIG. 1B) with a receive buffer (RBUF)69A (similar to58,FIG. 1B) and a transmit port70with a transmit buffer (TBUF)70A (similar to56,FIG. 1B). GL and XG port control modules are coupled to physical media devices (“PMD”)76and75respectively.

Control port module62A includes control buffers62B and62D for transmit and receive sides, respectively. Module62A also includes a PCI interface module62C that allows interface with IOP66via a PCI bus66A.

XG_Port (for example74B) includes RPORT72with RBUF71similar to RPORT69and RBUF69A and a TBUF74B and TPORT74A similar to TBUF70A and TPORT70. Protocol module73interfaces with SERDES to handle protocol based functionality.

Incoming frames are received by RPORT69via SERDES68and then transmitted using TPORT70. Buffers69A and70A are used to stage frames in the receive and the transmit path.

FIG. 1Fshows a top-level block diagram of a receive port69that includes a frame length control module80B (or Control module80B) and a port level CAM table80C. CAM Table80C is described below with respect toFIG. 3B.

CAM Table80C can be loaded with different values for each port. It is noteworthy that each port may have its own table80C or table80C can be shared between plural ports. In contrast, CAM table80is the master copy and includes information regarding all the ports.

It is also noteworthy that receive port69includes various other components that are described in co-pending patent application Ser. No. 10/894,627, filed on Jul. 20, 200, the disclosure of which is incorporated herein by reference.

FIG. 1Gshows a top-level block diagram for Virtual Fabrics (VSANs), which use the extended headers, according to one aspect of the present invention.FIG. 1Gshows three Fabric switches,1,2and3. Each switch has 8-ports labeled0-7. It is noteworthy that the present invention is not limited to any particular number/type of ports.

FIG. 1Hshows an example of Inter-Fabric connections where an extended frame header is used and processed, according to one aspect of the present invention. Eight Fabric switch are shown (numbered1through8) to illustrate Inter-Fabric routing. Switch #1is coupled to Switch #2, while Switch #3is coupled to Switch #1and2. Fabric1includes Switch #1,2, and3.

Fabric2includes Switch4,5and6. Fabric3includes Switch5and Switch7, while Fabric4includes Switch6and Switch8. The extended headers are used to route frames between the plural Fabrics, for example, between Fabric1and Fabric4. It is noteworthy that the present invention is not limited to any particular number of Fabrics or switches.

Fibre Channel Frame

FIG. 2Ashows the components of a typical Fibre Channel Frame, according to one aspect of the present invention; andFIG. 2Bshows an example of a Fibre Channel frame with additional headers (228).

Receive port69detects a frame when a SOF220is received. SOF220is 4 bytes long and indicates the start of a frame. Receive port69starts counting frame-length when it detects a SOF220.

New routing features have added additional header words226to the frame header221. The additional frame header (32 bytes) is shown inFIG. 2Bas228. Examples of the new routing features include Virtual Fabric header and Inter-Fabric routing headers (shown as226).

Frame header228uses two R_CTL values. R_CTL value of 50hor 51h(shown as227,FIG. 2B) is used to identify a frame with an extended header, while R_CTL222is used to identify the type of frame. The total frame-length of a Fibre Channel frame depends on the frame header221or228, which in turn depends on R_CTL222or227values.

Payload or data field223follows the frame header221(or228,FIG. 2B). The length of the payload varies between a minimum of 0 bytes and a maximum of 2112 bytes. The maximum length of the payload has not changed for the new routing features. It is noteworthy that the adaptive aspects of the present invention are not limited to any particular payload size or R_CTL value.

CRC224, which is 4 bytes long, follows the payload223. This field is used to check the data integrity of the frame.

EOF225, which is 4 bytes long, follows the CRC224. EOF indicates the end of a frame. When an EOF225is detected, receive port69stops counting frame-length and stores the value for future comparison and/or frame processing.

Process Flow for Checking Frame-Length

FIG. 2Cshows a top-level flow chart for checking frame-length in a Fibre Channel frame, according to one aspect of the present invention. It is noteworthy that this process flow chart is applicable to any Fibre Channel device that needs to route frames and faces the same issues as a switch element. Although the examples herein are based on a switch element, the present invention is not limited to a switch element and other devices, for example, a host bus adapter, can also use these inventive features.

Turning in detail toFIG. 2C, in step S201, receive port69starts receiving a Fibre Channel frame when it detects a SOF. The receive port69starts counting frame-length of the received frame. The frame-length counter (not shown) is incremented by 4 bytes when the receive port69receives a data word. It is noteworthy that Fibre Channel data could be received in chunks of 4 bytes (Dword) on every clock. The frame length counter can count bits, bytes, Dwords or other values, and the adaptive aspects of the present invention are not limited to any particular type of counter.

In step S202, receive port69parses the frame and R_CTL value222(or227) is extracted from the frame header221.

In step S203, R_CTL value222(or227) is compared with the R_CTL values stored in a CAM Table80(or80C). CAM Table80, which maintains information regarding R_CTL and frame-length values, is described below with respect toFIG. 3A.

In step S204, a maximum frame-length and a minimum frame-length is determined from the fields corresponding to the matched R_CTL value. If none of the values match the R_CTL value then the default (or programmed) maximum frame-length (for example, 2148 bytes) and minimum frame-length (for example, 36 bytes) are used. The maximum frame-length and minimum frame-length values from the Frame length CAM are stored for future comparison.

In step S205, receive port69stops incrementing the received frame-length value when it detects an EOF or error condition.

In step S206, the received frame-length is compared with the stored maximum and minimum frame-length values to determine if the received Fibre Channel frame is a long or short frame. A Fibre Channel frame is a long frame if the received frame-length is greater than the maximum frame-length and a Fibre Channel frame is a short frame if the frame-length is less than the minimum frame-length.

It is noteworthy that the present invention is not limited to any particular format for the maximum and/or minimum frame length comparison. For example, frame length value when compared could be the actual frame length value or as an offset value.

If the Fibre Channel frame is determined to be a long or short frame in step S206, then in step S207, the Fibre Channel frame is marked for discarding. For example, the EOF value may be set to EOFa, which denotes that the frame should be discarded. When the frame is marked then it is discarded by a destination, for example, a host bus adapter or a storage device.

In another aspect of the present invention, the frame that is too long or short is discarded in step S207. In the alternative, a long frame is truncated to a maximum length and a short frame is padded to the minimum length and the EOF value is replaced by an EOFa (as stated above, this denotes EOF abort). Thereafter, the receive port69optionally notifies IOP66of the error and records the error statistics for the port.

In step S208, receive port69processes the received Fibre Channel frame if the frame is not a long or short frame in step S206.

Content Addressable Memory (CAM) Table

FIG. 3Ashows CAM Table80, which maintains information regarding R_CTL values. CAM Table80is maintained in Random Access Memory (RAM)80A, which is accessible by IOP66and receive port69. As stated above, CAM table80is a master table for the switch, while each port can have its own CAM Table (80C).

Each entry in CAM Table has a R_CTL value and the associated maximum frame-length and minimum frame-length. CAM Table80is comprised of a column300that includes the R_CTL value, a column301that has the corresponding maximum frame-length information and a column302that has the minimum frame-length information.

Firmware adds the entries in the CAM table80(and also for CAM80C,FIG. 1F) during the initialization of the switch. For example, for a typical Fibre Channel frame, entry corresponding to R_CTL values of 0×00 to 0×4F and 0X60 through 0XFF has a maximum frame-length value equal to 2148 bytes and a minimum frame-length value equal to 36 bytes. Similarly, for a Virtual Fabric frame, entry corresponding to R_CTL value equal to 0×50 has a maximum frame-length value equal to 2156 bytes and a minimum frame-length value equal to 44 bytes. Similarly, R_CTL values equal to 0×51 and 0×52 represent inter-fabric and encapsulated inter-fabric frames, respectively (i.e. frames with extended headers (seeFIG. 2B)).

It is noteworthy that R_CTL values can be stored in any format in Random Access Memory and the term “table” is not to be construed as a limitation.

In one aspect of the present invention, R_CTL values are used to determine the maximum and minimum frame-length values of the received Fibre Channel frame. These values allows a receive port to check for frame length without causing data corruption.

It is noteworthy that different values for the minimum frame-length and/or maximum frame-length are used for different R_CTL values. Also CAM Table80C provides default values for minimum frame-length and/or maximum frame-length if the extracted R_CTL values do not match stored R_CTL values.

It is also noteworthy that the present invention is not limited to any particular R_CTL, maximum/minimum frame length values. Switch element firmware operating under IOP66can program these values.

Frame Length Control Module

FIG. 3Bshows a detailed logic diagram for implementing port level CAM Table80C with entries 00 to entry N. CAM Table80C is located in each receive port69and is used by one port or shared between plural ports. The term “Table” as used herein is not limit to a table that simply stores values, but denotes a system/logic for achieving the adaptive aspects of the present invention.

It is noteworthy that although various bit values are shown inFIG. 3B, the adaptive aspects of the present invention are not limited to any particular bit value.

Incoming frames information (or fields) (R_CTL222/227) is compared by logic30E with entry30B. A valid/control bit30A is set for a valid control word entry. Logic30E generates a command/signal (output30E1) based on the comparison. Output30E1is sent to logic30F that generates a hit signal30F1.

Output30F1is sent to an encoder module30G, whose output30H is sent to MUX30K. Maximum frame-length30C and minimum frame-length30D are also sent to MUX30K. MUX30K selects maximum frame-length30J and a minimum frame-length30I depending on the input signal30H. The selected maximum frame-length30J and a minimum frame-length30I values are shown as the entries in column301and302respectively inFIG. 3A.

The present invention is not limited to CAM table80C as described above. A hashing table could also be used to implement the adaptive aspects of the present invention.

In one aspect of the present invention, frame length is checked efficiently and in real time. The foregoing process/system can accommodate the new standard Virtual Fabric and Inter-Fabric headers in previous Fibre Channel switch elements, without expensive upgrades.

Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.