STACKABLE CONTROLLERS FOR MULTIPHASE SWITCHING CONVERTERS AND POWER SUPPLY SYSTEM THEREOF

A power supply system has a first power circuit, a second power circuit, a first controller and a second controller. The first and second power circuits respectively have a first and second plurality of switching circuits coupled in parallel to provide an output voltage. The first controller provides a turn-on control signal at the first turn-on control pin based on a voltage feedback signal received by a first feedback pin, and provides a first plurality of switching control signals at the first plurality of switching control pins based on a turn-on control signal to successively turn ON a first plurality of switching circuits. The second controller provides a second plurality of switching control signals at a second plurality of switching control pins based on the turn-on control signal received by a second turn-on control pin to successively turn ON the second plurality of switching circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of CN application 202211551102.3, filed on Dec. 5, 2022, and incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to electronic circuits, and more particularly, relates to power supply systems, control circuits for voltage regulators and control methods thereof.

2. Description of Related Art

With the development of high performance CPU (Central Processing Unit), switching converters with lower output voltage and higher output current are needed, and requirements for better thermal performance and faster transient response are also increasing. Multiphase switching converters are widely used because of their superior performance. A multiphase switching converter has a plurality of switching circuits, each switching circuit being one phase, and output terminals of all the switching circuits are coupled together to provide an output voltage for a load.

A controller for a multiphase switching converter usually provides an individual switching control signal for each phase. However, if the number of the phases is larger than the number of switching control signals that the controller can provide, then it will be necessary to use one switching control signal to control two or more phases, which may cause new problems.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a stackable controllers for multiphase switching converters.

Embodiments of the present invention are directed to a power supply system, comprising a first power circuit, a second power circuit, a first controller, and a second controller. The first power circuit has a first plurality of switching circuits, and the second power circuit has a second plurality of switching circuits. Each of the first plurality of switching circuits and the second plurality of switching circuits are coupled in parallel to provide an output voltage. The first controller comprises a first feedback pin, a first turn-on control pin, and a first plurality of switching control pins. The first feedback pin is configured to receive a voltage feedback signal representative of the output voltage. The first controller is configured to provide a turn-on control signal at the first turn-on control pin based on the voltage feedback signal, and is configured to provide a first plurality of switching control signals at the first plurality of switching control pins based on the turn-on control signal to successively turn ON the first plurality of switching circuits. The second controller comprises a second turn-on control pin and a second plurality of switching control pins. The second turn-on control pin is coupled to the first turn-on control pin to receive the turn-on control signal provided by the first controller, and the second controller is configured to provide a second plurality of switching control signals at the second plurality of switching control pins based on the turn-on control signal to successively turn ON the second plurality of switching circuits.

Embodiments of the present invention are directed to a controller for a multiphase switching converter. The multiphase switching converter has a plurality of switching circuits coupled in parallel to provide an output voltage. The controller comprises a turn-on control pin, and a plurality of switching control pins. When the controller is configured as a master controller, the turn-on control pin is configured to provide a turn-on control signal based on the output voltage, and when the controller is configured as a slave controller, the turn-on control pin is configured to receive the turn-on control signal from another controller. The controller is configured to provide a plurality of switching control signals at the plurality of switching control pins to successively turn ON the plurality of switching circuits.

Embodiments of the present invention are directed to control method for a multiphase switching converter. The multiphase switching converter has a controller and a plurality of switching circuits coupled in parallel to provide an output voltage. The control method comprises providing or receiving a turn-on control signal at a turn-on control pin, and providing a plurality of switching control signals at a plurality of switching control pins to turn ON the plurality of switching circuits successively. Wherein when the controller is configured as a master controller, providing the turn-on control signal at the turn-on control pin, and when the controller is configured as a slave controller, receiving the turn-on control signal provided by the master controller at the turn-on control pin.

DETAILED DESCRIPTION OF THE INVENTION

FIG.1schematically illustrates a power supply system100in accordance with an embodiment of the present invention. The power supply system100receives an input voltage Vin, and provides an output voltage Vo and an output current Io. The power supply system100has multiphase switching converters1001,1002, and1003. The multiphase switching converter1001has a power circuit21and a controller10_1, the multiphase switching converter1002has a power circuit22and a controller10_2, and the multiphase switching converter1003has a power circuit23and a controller10_3. One with ordinary skill in the art should understand that the power supply system100may also comprise a different number of multiphase switching converters. The power circuits21-23receives the input voltage Vin, and converts the input voltage Vin to the output voltage Vo. Each of the power circuits21-23has a plurality of switching circuits coupled together in parallel to provide the output voltage Vo. In the example ofFIG.1, the power circuit21has switching circuits21_1-21_3providing currents I1_1-I1_3respectively, the power circuit22has switching circuits22_1-22_3providing currents I2_1-I2_3respectively, and the power circuit23has switching circuits23_1-23_3providing currents I3_1-I3_3respectively. In some embodiments, the switching circuits21_1-21_3,22_1-22_3, and23_1-23_3may comprise buck circuits, boost circuits or buck-boost circuits, etc. One with ordinary skill in the art should understand that each of the power circuits21-23may also have more or fewer than three switching circuits as shown inFIG.1. Although in the example ofFIG.1, each of the power circuits21-23has a same number of switching circuits, one with ordinary skill in the art should understand that, the number of switching circuits in each of the power circuits21-23may also be different.

In the example ofFIG.1, each controller10_i(i=1, 2, 3 in the embodiment ofFIG.1) has a feedback pin101, a turn-on control pin102, and a plurality of switching control pins103(e.g., control pins103_1,103_2, and103_3shown inFIG.1). The controllers10_1-10_3are stackable, i.e., the controllers10_1-10_3are coupled in parallel via the turn-on control pins102. In the example ofFIG.1, the controller10_1is configured as a master controller, the controllers10_2and10_3are configured as slave controllers.FIG.1is illustrated by employing two slave controllers as one example, and one with ordinary skill in the art should understand that the power supply system100may also have different numbers of slave controllers. The feedback pin101of the master controller10_1receives a voltage feedback signal Vfb representative of the output voltage Vo. The master controller10_1provides a turn-on control signal Set at its turn-on control pin102based on the voltage feedback signal Vfb, and provides a plurality of switching control signals PWM1(e.g., control signals PWM1_1, PWM1_2, and PWM1_3shown inFIG.1) based on the turn-on control signal Set. The switching control signals PWM1_1, PWM1_2, and PWM1_3are configured to turn ON the plurality of switching circuits21_1-21_3of the power circuit21successively. The turn-on control pins102of the slave controllers10_2and10_3are coupled to the turn-on control pin102of the master controller10_1to receive the turn-on control signal Set provided by the master controller10_1. The slave controller10_2provides a plurality of switching control signals PWM2(e.g., PWM2_1, PWM2_2, and PWM2_3shown inFIG.1) at the plurality of switching control pins103of the slave controller10_2based on the turn-on control signal Set provided by the master controller10_1, and the plurality of switching control signals PWM2_1, PWM2_2, and PWM2_3are configured to turn ON the plurality of switching circuits22_1-22_3successively. The slave controller10_3provides a plurality of switching control signals PWM3(e.g., PWM3_1, PWM3_2, and PWM3_3shown inFIG.1) at the plurality of switching control pins103of the slave controller10_3based on the turn-on control signal Set provided by the master controller10_1, and the plurality of switching control signals PWM3_1, PWM3_2, and PWM3_3are configured to turn ON the plurality of switching circuits23_1-23_3successively. In one embodiment, the feedback pins101of the slave controllers10_2and10_3are not configured to receive the voltage feedback signal Vfb. For example, the feedback pins101of the slave controllers10_2and10_3may be but not be limited to floating as shown inFIG.1.

In one embodiment, when the voltage feedback signal Vfb received by the master controller10_1is smaller than a voltage reference signal Vref, the master controller10_1turns ON the at least one switching circuits of the power circuit21, the slave controller10_2turns ON the at least one switching circuits of the power circuit22, and the slave controller10_3turns ON the at least one switching circuits of the power circuit23. The voltage reference signal Vref represents a desired value of the output voltage Vo.

Embodiments of the present invention provide a power supply system comprising a plurality of controllers coupled in parallel. The power supply system in accordance with the embodiments of the present invention expands the range of the output current, and drives each of the switching circuits by an individual switching control signal, which improves the reliability of the circuit.

In the example ofFIG.1, each controller10_ifurther comprises a communication pin104. The communication pins104of all the controllers10_1-10_3are coupled together through a communication bus201for data-transmit, thus data of the master controller10_1is synchronized to the slave controllers10_2-10_3. In one embodiment, the master controller10_1transmits data through the communication bus201comprises providing a total current data DIsum and a phase current data DIphase, or providing one of the total current data DIsum and the phase current data DIphase. The total current data DIsum indicates a total current (I1_1+I1_2+I1_3) flowing through the power circuit21, and the phase current data DIphase indicates a current flowing through each of the switching circuits21_1-21_3or a current flowing through at least one of the switching circuits21_1-21_3. In one example, the slave controller10_2transmits data through the communication bus201comprises receiving the total current data DIsum and the phase current data DIphase, or receiving one of the total current data DIsum and the phase current data DIphase, for regulating a total current (I2_1+I2_2+I2_3) flowing through the power circuit22, and thus achieving current balance between the power circuit21and the power circuit22. In one example, the slave controller10_3transmits data through the communication bus201comprises receiving the total current data DIsum and the phase current data DIphase, or receiving one of the total current data DIsum and the phase current data DIphase, for regulating a total current (I3_1+I3_2+I3_3) flowing through the power circuit23, and thus achieving current balance between the power circuit21and the power circuit23. The embodiments of the present invention can achieve current balance between different power circuits while expanding the range of the output current.

In one example, the master controller10_1transmits data through the communication bus201further comprises providing a preset ON time data DTON through the communication bus201, and the slave controllers10_2and10_3transmit data through the communication bus201further comprise receiving the preset ON time data DTON provided by the master controller10_1through the communication bus201. The preset ON time data DTON controls initial ON time periods of the plurality of switching circuits of the power circuits21-23equal to each other, thus initial output voltages and initial output currents of the power circuits21-23are synchronized. In one embodiment, the master controller10_1provides the preset ON time data DTON based on the input voltage Vin and the output voltage Vo (or the desired value of the output voltage Vo) to control the initial ON time period of each switching circuit of the power circuits21-23to vary with the input voltage Vin and the output voltage Vo (or the desired value of the output voltage Vo), and thus ensuring a switching frequency of each switching circuit of the power circuits21-23to remain substantially stable when the input voltage Vin or the output voltage Vo varies. In one example, data transmitted between the master controller10_1and the slave controllers10_2-10_3may further comprise but not be limited to a desired frequency data representative of a desired switching frequency, a protection data representative of a circuit protection status. For example, the circuit protection status may comprise but not be limited to over voltage, under voltage, over current, and over temperature, etc.

FIG.2schematically illustrates a power supply system200in accordance with an embodiment of the present invention. In the example ofFIG.2, each controller10_i(i=1, 2, 3 in the embodiment ofFIG.2) further comprises current sense pins105_1-105_3to receive current sense signals CSi_1-CSi_3. The current sense signals CSi_1-CSi_3represent currents Ii_1-Ii_3flowing through the switching circuits2i_1-2i_3respectively. As shown inFIG.2, the current sense pins105_1-105_3of the master controller10_1receive the current sense signals CS1_1-CS1_3respectively, the current sense pins105_1-105_3of the slave controller10_2receive the current sense signals CS2_1-CS2_3respectively, and the current sense pins105_1-105_3of the slave controller10_3receive the current sense signals CS3_1-CS3_3respectively. In the example ofFIG.2, each controller10_ifurther comprises a total current pin106. The total current pins106of all the controllers10_1-10_3are coupled together. The master controller10_1provides a total current sense signal Im1representative of a total current flowing through the switching circuits21_1-21_3based on the current sense signals CS1_1-CS1_3. The slave controller10_2provides a total current sense signal Im2representative of the total current flowing through the switching circuits22_1-22_3at its total current pin106based on the current sense signals CS2_1-CS2_3. The slave controller10_3provides a total current sense signal Im3representative of the total current flowing through the switching circuits23_1-23_3at its total current pin106based on the current sense signals CS3_1-CS3_3. In one embodiment, the master controller10_1provides a system current signal Imon representative of a total current flowing through all the power circuits21-23based on the total current sense signals Im1-Im3.

FIG.3schematically illustrates a power circuit2iin accordance with an embodiment of the present invention. In the example ofFIG.3, the switching circuits2i_1-2i_3employ buck topology. Each switching circuit2i_j comprises a switch Si_j, a switch SRi_j and an inductor Li_j (j=1, 2, 3 in the embodiment ofFIG.3) which are connected as shown inFIG.3. Each switching circuit2ij converts the input voltage Vin to the output voltage Vo and provides a current Ii_j under the switching action of the switches Si_j and SRi_j. The switches Si_j and SRi_j are turned ON and OFF complementarily under the control of the switching control signal PWMi_j. The current sense signal CSi_j represents the current Ii_j flowing through the switching circuit2i_j. For example, the current sense signal CSi_j may be provided by sensing a current flowing through the inductor Li_j, a current flowing through the switch Si_j, or a current flowing through the switch SRi_j.

FIG.4schematically illustrates a controller10_iin accordance with an embodiment of the present invention.FIG.4takes constant ON time control as one example, and one with ordinary skill in the art should understand that any other suitable control scheme may also be employed without detracting merits of the present invention. In the example ofFIG.4, the controller10_icomprises a current balance unit410, a comparison unit420, comparison unit420afrequency dividing unit430, and a switch signal generating unit440. One with ordinary skill in the art should understand that the detailed circuit of the controller10_iis not limited by the example ofFIG.4.

The current balance unit410provides bias signals Bias_1-Bias_3respectively based on differences between the current sense signals CSi_1-CSi_3and a current reference signal Iref (i.e., CSi_1-Iref, CSi_2-Iref, and CSi_3-Iref), and the bias signals Bias_1-Bias_3are configured to regulate ON time periods of the plurality of switching circuits2i_1-2i_3. The current balance unit410provides ON time thresholds Toni_1-Toni_3via regulating a preset ON time threshold TON, to regulate the ON time periods of the plurality of switching circuits2i_1-2i_3of the power circuit2i. For example, the ON time threshold Toni_1is provided based on a sum of the bias signal Bias_1and the preset ON time threshold TON (Bias_1+TON), the ON time threshold Toni_2is provided based on a sum of the bias signal Bias_2and the preset ON time threshold TON (Bias_2+TON), and the ON time threshold Toni_3is provided based on a sum of the bias signal Bias_3and the preset ON time threshold TON (Bias_3+TON). In one embodiment, the preset ON time threshold TON is generated based on the preset ON time data DTON. In the example ofFIG.4, the current balance unit410has subtractors411_1-411_3, proportional integrators412_1-412_3, and adders413_1-413_3. Each subtractor411_jhas a first input terminal, a second input terminal, and an output terminal. The first input terminal of each subtractor411_jreceives the current reference signal Iref, the second input terminal of each subtractor411_jreceives the corresponding current sense signal CSi_j, and the subtractor411_jprovides a current error signal Iej representative of a difference between the current reference signal Iref and the current sense signal CSi_j. Each proportional integrator412_jhas an input terminal and an output terminal. The input terminal of each proportional integrator412_jis coupled to the output terminal of the corresponding subtractor411_jto receive the current error signal Iej, and the proportional integrator412_jprovides the bias signal bias_j at its output terminal by performing proportion and integration of the current error signal Iej. Each adder414_jhas a first input terminal, a second input terminal, and an output terminal. The first input terminal of each adder414_jreceives the preset ON time threshold TON, the second input terminal is coupled to the output terminal of the corresponding proportional integrator412_jto receive the bias signal bias_j, and the adder414_jprovides the ON time threshold Toni j after regulation at its output terminal by adding the preset ON time threshold TON and the bias signal bias_j.

When the controller10_iis configured as the master controller, the feedback pin101receives the voltage feedback signal Vfb, the comparison unit420provides the turn-on control signal Set based on the voltage feedback signal Vfb and the voltage reference signal Vref. When the controller10_iis configured as the slave controller, the comparison unit420is disabled, e.g., the comparison unit420is disabled by a master-slave indication signal Ma, wherein the master-slave indication signal Ma is configured to indicate whether the controller10_iis the master controller or the slave controller. In one example, the master-slave indication signal Ma may be a programmable signal, e.g., the master-slave indication signal Ma may be set by a digit of a register, by a pin, or by any other suitable methods. In one embodiment, when the voltage feedback signal Vfb received by the master controller is smaller than the voltage reference signal Vref, the turn-on control signal Set is flipped (e.g., becomes logic high) to turn ON the at least one switching circuits of the power circuit21, the at least one switching circuits of the power circuit22, and the at least one switching circuits of the power circuit23. In one embodiment, when the controller10_iis configured as the master controller, the controller10_iprovides the turn-on control signal Set further based on a signal on the total current pin106. For example, the controller10_iprovides the system current signal Imon based on the signal on the total current pin106, and further provides the turn-on control signal Set based on the system current signal Imon. As shown inFIG.4, the master controller provides the turn-on control signal Set further based on a comparison result of the system current signal Imon and a max current threshold OCL, wherein the comparison result is provided by a comparison unit4201. When the controller10_iis configured as the slave controller, the comparison unit4201is disabled. In one embodiment, when the voltage feedback signal Vfb received by the master controller10_1is smaller than the voltage reference signal Vref and the system current signal Imon is smaller than the max current threshold OCL, the turn-on control signal Set is flipped (e.g., becomes logic high) to turn ON the at least one switching circuits of the power circuit21, the at least one switching circuits of the power circuit22, and the at least one switching circuits of the power circuit23.

The frequency dividing unit430receives the turn-on control signal Set provided by the master controller, and distributes pulses of the turn-on control signal Set to a plurality of frequency division signals Set1-Set3. The switch signal generating unit440is coupled to the frequency dividing unit430to receive the plurality of frequency division signals Set1-Set3, and is coupled to the current balance unit410to receive the plurality of ON time thresholds Toni_1-Toni_3. The switch signal generating unit440provides a plurality of switching control signals PWMi_1-PWMi_3based on the plurality of frequency division signals Set1-Set3and the plurality of ON time thresholds Toni_1-Toni_3to turn ON and OFF the plurality of switching circuits2i_1-2i_3of the power circuit2i. In one embodiment, the switch signal generating unit440turns ON the switching circuits2i_1-2i_3of the power circuit2icorrespondingly based on the frequency division signals Set1-Set3, and turns OFF the switching circuits2i_1-2i_3of the power circuit2icorrespondingly based on the ON time thresholds Toni_1-Toni_3. In the example ofFIG.4, the switch signal generating unit440comprises a plurality of RS flip-flops441-443. The RS flip-flop441has a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S of the RS flip-flop441receives the frequency division signal Set1, the reset terminal R of the RS flip-flop441receives the ON time threshold Toni_1, and the output terminal Q of the RS flip-flop441provides the switching control signal PWMi_1based on the frequency division signal Set1and the ON time threshold Toni_1to control the switching circuit2i_1. The RS flip-flop442has a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S of the RS flip-flop442receives the frequency division signal Set2, the reset terminal R of the RS flip-flop442receives the ON time threshold Toni_2, and the output terminal Q of the RS flip-flop442provides the switching control signal PWMi_2based on the frequency division signal Set2and the ON time threshold Toni_2to control the switching circuit2i_2. The RS flip-flop443has a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S of the RS flip-flop443receives the frequency division signal Set3, the reset terminal R of the RS flip-flop443receives the ON time threshold Toni_3, and the output terminal Q of the RS flip-flop443provides the switching control signal PWMi_3based on the frequency division signal Set3and the ON time threshold Toni_3to control the switching circuit2i_3.

In one embodiment, the controller10_ifurther comprises an interface unit450coupled to the communication pin104. When the controller10_iis configured as the master controller, the interface unit450converts a sum of the current sense signals CS1_1-CS1_3(CS1_1+CS1_2+CS1_3) to the total current data DIsum which represents the total current (I1_1+I1_2+I1_3) flowing through the power circuit21, and converts the current sense signals CS1_1-CS1_3or one of the current sense signals CS1_1-CS1_3to the phase current data DIphase which represents the current flowing through each of the switching circuits21_1-21_3or the current flowing through one of the switching circuits21_1-21_3. The interface unit450provides the total current data DIsum and the phase current data DIphase, or provides one of the total current data DIsum and the phase current data DIphase to the slave controllers. In one embodiment, when the controller10_iis configured as a slave controller, the interface unit450provides the current reference signal Iref based on the total current data DIsum or the phase current data DIphase. For example, the interface unit450provides the current reference signal Iref by performing digital to analog conversion on the total current data DIsum or the phase current data DIphase. In one embodiment, when the controller10_iis configured as the master controller, the interface unit450provides the current reference signal Iref based on the sum of the current sense signals CS1_1-CS1_3(CS1_1+CS1_2+CS1_3), the current sense signals CS1_1-CS1_3, or one of the current sense signals CS1_1-CS1_3. In one embodiment, when the controller10_iis configured as the master controller, the interface unit450further converts the preset ON time threshold TON to the preset ON time data DTON, and provides the preset ON time data DTON at the communication pin104. In one embodiment, when the controller10_iis configured as the slave controller, the interface unit450further receives the preset ON time data DTON provided by the master controller, and provides the preset ON time threshold TON based on the preset ON time data DTON.

In one embodiment, the controller10_ifurther comprises a total current processing unit460coupled to the total current pin106and the current sense pins105_1-105_3. The total current processing unit460provides the total current sense signal Imi representative of the total current flowing through the plurality of switching circuits2i_1-2i_3of the corresponding power circuit2ibased on the current sense signals CSi_1-CSi_3. For example, the total current sense signal Imi is equal to the sum of the current sense signals CS1_1-CS1_3(CS1_1+CS1_2+CS1_3). When the controller10_iis configured as the master controller, the total current processing unit460provides the system current signal Imon representative of the total current flowing through all the power circuits21-23. In one example, the system current signal Imon is equal to a sum of all the total current sense signals Im1-Im3(Im1+Im2+Im3). In the example ofFIG.4, the total current processing unit460comprises calculation units461-462and a switch34. The calculation unit461is coupled to the current sense pins105_1-105_3, and provides the total current sense signals Imi based on the sum of the current sense signals CS1_1-CS1_3(CS1_1+CS1_2+CS1_3). When the controller10_iis configured as the slave controller, the switch34is turned ON, and the slave controller provides the total current sense signals Imi at the total current pin106. When the controller10_iis configured as the master controller, the switch34is turned OFF, and the calculation unit462provides the system current signal Imon based on the sum of all the total current sense signals Im1-Im3(Im1+Im2+Im3).

FIG.5schematically shows a timing diagram of signals of the power supply system100in accordance with an embodiment of the present invention.FIG.5shows, from top to bottom, the voltage feedback signal Vfb, the turn-on control signal Set, the switching control signals PWM1_1-PWM1_3, the switching control signals PWM2_1-PWM2_3, and the switching control signals PWM3_1-PWM3_3. When the voltage feedback signal Vfb is smaller than the voltage reference signal Vref, the master controller10_1is configured to control the turn-on control signal Set flipped (e.g., becomes logic high). One with ordinary skill in the art should understand that pattern of the voltage reference signal Vref is not limited by the example ofFIG.5. For example, a ramp signal may also be added to the voltage reference signal Vref. The master controller10_1provides the switching control signals PWM1_1-PWM1_3based on the turn-on control signal Set to turn ON the plurality of switching circuits21_1-21_3successively, the slave controller10_2provides the switching control signals PWM2_1-PWM2_3based on the turn-on control signal Set to turn ON the plurality of switching circuits22_1-22_3successively, and the slave controller10_3provides the switching control signals PWM3_1-PWM3_3based on the turn-on control signal Set to turn ON the plurality of switching circuits23_1-23_3successively. A delay time period Tdl1represents a time period from the turn-on control signal Set becoming logic high to one of the switching control signals PWM1_1-PWM1_3becoming logic high. For example, the delay time period Tdl1may comprise an internal logic delay, or a computational delay, etc. A delay time period Tdl2represents a time period from when the turn-on control signal Set becomes logic high to one of the switching control signals PWM2_1-PWM2_3becoming logic high. A delay time period Tdl3represents a time period from when the turn-on control signal Set becomes logic high to one of the switching control signals PWM3_1-PWM3_3becoming logic high. For example, the delay time periods Tdl2-Tdl3may comprise internal logic delays, computational delays, or propagation delays caused by line transmission between the controllers, etc. One with ordinary skill in the art should understand that lengths of the delay time periods Tdl1-Tdl3are not limited by the example ofFIG.5.

FIG.6schematically illustrates a power supply system300in accordance with an embodiment of the present invention. The power circuits of the power supply system300(e.g., the power circuit21controlled by the switching control signals PWM1_1-PWM1_3, the power circuit22controlled by the switching control signals PWM2_1-PWM2_3, and the power circuit23controlled by the switching control signals PWM3_1-PWM3_3as shown inFIG.2) are omitted for illustration purpose. In one embodiment, each controller10_i(i=1, 2, 3 in the embodiment ofFIG.6) further comprises an alert pin107, and the alert pins107of all the controllers10_1-10_3are coupled together. When any controller10_iis in a fault condition, the controller10_iin the fault condition is configured to indicate the fault condition at its alert pin107, e.g., the alert pin107is set to be logic high or set to be logic low, and all power circuits21-23are turned off by the controllers10_1-10_3. In one embodiment, each controller10_ifurther comprises a communication pin109. In the example ofFIG.6, the communication pins109of all the controllers10_1-10_3are coupled to a communication pin601of a system controller60through a communication bus202to receive a system control command CMD from the system controller60. The system control command CMD controls circuit parameters of each power circuit2i, e.g., the output voltage Vo, the desired switching frequency, the initial ON time period, a max current limit of the power supply system200, a phase current protection limit, a temperature protection limit, and an under voltage protection limit, etc.

FIG.7schematically illustrates a power supply system400in accordance with an embodiment of the present invention. The power circuits of the power supply system400(e.g., the power circuit21controlled by the switching control signals PWM1_1-PWM1_3, the power circuit22controlled by the switching control signals PWM2_1-PWM2_3, and the power circuit23controlled by the switching control signals PWM3_1-PWM3_3as shown inFIG.2) are omitted for illustration purpose. In the example ofFIG.7, the communication pin109of the master controller10_1is coupled to a communication pin601of the system controller60through the communication bus202to receive the system control command CMD from the system controller60, and the master controller10_1controls the circuit parameters of the power circuit21based on the system control command CMD. The master controller10_1provides data to the slave controllers10_2-10_3through the communication bus201to control the circuit parameters of the power circuits22-23.

FIG.8illustrates a control method800for a multiphase switching converter in accordance with an embodiment of the present invention. The control method800comprises steps S11-S12. The multiphase switching converter has a controller and a plurality of switching circuits coupled together in parallel to provide an output voltage.

In step S11, providing or receiving a turn-on control signal via a turn-on control pin. When the controller is configured as a master controller, providing the turn-on control signal at the turn-on control pin, and when the controller is configured as a slave controller, receiving the turn-on control signal provided by the master controller at the turn-on control pin.

In step S12, providing a plurality of switching control signals at a plurality of switching control pins to turn ON the plurality of switching circuits successively.

In one embodiment, the control method for the multiphase switching converter further comprises coupling the controller to one or more other controllers through a first communication bus, and transmitting data between the controllers to synchronize information between the controllers, and coupling the controller to a system controller through a second communication bus, and receiving a system control command from the system controller to control circuit parameters of the multiphase switching converter. In one embodiment, when the controller is configured as the master controller, transmitting the data comprises providing a total current data and a phase current data through the first communication bus, or providing one of the total current data and the phase current data through the first communication bus. Wherein the total current data represents a total current flowing through the plurality of switching circuits, and the phase current data represents a current flowing through at least one of the switching circuits. In one embodiment, when the controller is configured as the slave controller, transmitting the data comprises receiving the total current data and the phase current data through the first communication bus, or receiving one of the total current data and the phase current data through the first communication bus, to regulate the total current flowing through the plurality of switching circuits controlled by the slave controller. Wherein the total current data represents the total current flowing through the plurality of switching circuits controlled by the master controller, and the phase current data represents the current flowing through at least one of the switching circuits controlled by the master controller. In one embodiment, when the controller is configured as the master controller, transmitting the data further comprises providing a preset ON time data through the first communication bus. In one embodiment, when the controller is configured as the slave controller, transmitting the data further comprises receiving the preset ON time data provided by the master controller through the first communication bus to configure an initial ON time period of each of the plurality of switching circuits controlled by the slave controller, such that the initial ON time periods of the plurality of switching circuits controlled by the slave controller are equal to the initial ON time periods of the plurality of switching circuits controlled by the master controller.

In one embodiment, the control method for the multiphase switching converter further comprises receiving a plurality of current sense signals representative of the current flowing through the plurality of switching circuits via a plurality of current sense pins, and coupling the total current pin to one or more other controllers, when the controller is configured as the slave controller, further providing a total current sense signal representative of the total current flowing through the plurality of switching circuits at a total current pin of the slave controller based on the plurality of current sense signals. When the controller is configured as the master controller, further providing the turn-on control signal based on the signal on the total current pin of the master controller.

Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.