Trench silicide contact with low interface resistance

An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

BACKGROUND

The present disclosure relates to semiconductor devices. More particularly, the present disclosure relates to metal semiconductor alloy contacts to semiconductor devices.

For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, methods for improving performance without scaling are being considered. One approach for doing this is to increase carrier (electron and/or hole) mobilities.

SUMMARY

In one embodiment, an electrical structure is provided that includes a dielectric layer present on a semiconductor substrate. A via opening is present through the dielectric layer. An interconnect is present within the via opening to a metal semiconductor alloy contact that is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that define the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

In another embodiment, a semiconductor device is provided that includes a gate structure on a channel portion of a semiconductor substrate. A source region and a drain region are present on opposing sides of the channel portion of the semiconductor substrate. A dielectric layer is present on the semiconductor substrate, the source region, the drain region and the gate structure. An interconnect is present extending through the dielectric layer into contact with a metal semiconductor alloy contact that is in electrical communication with at least one of the source region and the drain region. The metal semiconductor alloy contact has a convex curvature that extends into at least one of the source region and the drain region, wherein endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the interconnect and an upper surface of the semiconductor substrate.

In another aspect, a method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, wherein a source region and a drain region are present on opposing sides of the channel portion of the semiconductor substrate. A dielectric layer is formed over the gate structure.

A via opening is formed through the dielectric layer to form an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region.

An amorphous region is formed in the semiconductor substrate by an angled ion implantation through the via opening into the exposed surface of the semiconductor substrate. The amorphous region is removed to form a divot having a convex curvature relative to the centerline of the via opening. A metal-containing material is formed on the divot. The metal-containing material and a portion of the semiconductor substrate adjacent to the divot are converted into a metal semiconductor alloy contact. The metal semiconductor contact has a convex curvature that extends into at least one of the source region and the drain region. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening and an upper surface of the semiconductor substrate. An interconnect is formed within the via opening in direct contact with the metal semiconductor alloy contact.

DETAILED DESCRIPTION

The present disclosure relates to metal semiconductor alloy contacts. A “metal semiconductor alloy” is an alloy of a metal and semiconductor. An alloy is homogeneous mixture or solid solution, in which the atoms of the metal are replacing or occupying interstitial positions between the atoms of the semiconductor.

The metal semiconductor alloy contacts may be formed to semiconductor devices, such as field effect transistors (FETS). A field effect transistor (FET) is a semiconductor device in which output current, i.e., source-drain current, is controlled by the voltage applied to a gate structure. A field effect transistor (FET) has three terminals, i.e., a gate structure, a source and a drain region. The gate structure is a structure used to control output current, i.e., flow of carriers in the channel portion, of a semiconducting device, such as a field effect transistor (FET), through electrical or magnetic fields. The channel portion of the substrate is the region between the source region and the drain region of a semiconductor device that becomes conductive when the semiconductor device is turned on. The source region is a doped region in the semiconductor device, in which majority carriers are flowing into the channel portion. The drain region is the doped region in semiconductor device located at the end of the channel portion, in which carriers are flowing out of the semiconductor device through the drain region.

When forming semiconductor devices, such as field effect transistors, using replacement gate methods, the metal semiconductor alloy contacts to the source and drain regions of the semiconductor device are typically formed in a trench, i.e., via opening, that extends through a dielectric layer. The dielectric layer also provides the opening to the channel portion of the semiconductor substrate that contains the functioning gate structure, once the sacrificial gate has been removed. It has been determined that forming metal semiconductor alloy contacts on the upper surface of the source region and the drain region that is defined by the trench opening results in increased resistance of the contact to the channel portion of the substrate. More specifically, in comparison to metal semiconductor alloy contacts that are not confined within the trench, and extend along an entire upper surface of the source and drain regions substantially to the sidewall of the gate structure, metal semiconductor alloy contacts that are contained within trenches increase the resistance of the contact. The metal semiconductor alloy contacts that are contained within trenches have an increased resistance, because a semiconductor region that is free of higher conductivity metal is present between the metal semiconductor alloy contact that is contained within the trench and the channel portion of the semiconductor device. In one embodiment, the present disclosure provides a lower resistance contact to a doped region of a semiconductor substrate by forming a metal semiconductor alloy contact having a convex curvature, as depicted inFIG. 1.

FIG. 1depicts one embodiment of an electrical structure100that includes a dielectric layer10apresent on a semiconductor substrate5a, and an interconnect15apresent extending through the dielectric layer10ainto contact with a doped region6of the semiconductor substrate5a. Electrical communication between the interconnect15aand the doped region6of the semiconductor substrate5amay be provided by a metal semiconductor alloy contact20athat has a perimeter defined by a convex curvature R1.

Although, the present disclosure provides details concerning forming contact structures to the source region and the drain regions of a field effect transistor (FET), the metal semiconductor alloy contacts20adisclosed herein may provide electrical communication to any electrical device including, but not limited to, memory devices, resistors, diodes, capacitors, and other semiconductor devices, such as finFETs, Schottky barrier MOSFETS and bipolar junction transistors.

The semiconductor substrate5amay be composed of a silicon containing material. Si-containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof. The semiconductor substrate5ais not limited to only silicon containing materials, as the semiconductor substrate5amay be composed of any semiconducting material, such as compound semiconductors including Ge, GaAs, InAs and other like semiconductors. In the example, that is depicted inFIG. 1, the semiconductor substrate5ais a bulk-semiconductor substrate. Although not depicted inFIG. 1, the semiconductor substrate5amay include layered semiconductors, such as Si/Ge and Silicon-On-Insulators.

The semiconductor substrate5amay include a doped region6, which may also be referred to as a well. A doped region6is formed in the semiconductor substrate5aby adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. The doped region may be p-type or n-type. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to, antimony, arsenic and phosphorous. The dopant may be introduced by ion implantation or may be introduced to the semiconductor substrate5in situ. In situ means that the dopant is introduced during the process sequence that forms the material layers that provide the semiconductor substrate5a. In one embodiment, in which the dopant region6is implanted with arsenic or phosphorus for an n-type semiconductor device, such as an n-type field effect transistor (nFET), the dopant concentration of the dopant region may range from 1×1018atoms/cm3to 5×1021atoms/cm3. In another embodiment, in which the dopant region6is implanted with arsenic or phosphorus for an n-type semiconductor device, such as an n-type field effect transistor (nFET), the dopant concentration of the dopant region may range from 1×1019atoms/cm3to 1×1021atoms/cm3. In another embodiment, in which the dopant region6is implanted with boron or BF2for a p-type semiconductor device, such as a p-type field effect transistor (pFET), the dopant concentration of the dopant region may range from 1×1018atoms/cm3to 5×1021atoms/cm3. In another embodiment, in which the dopant region6is implanted with boron or BF2for a p-type semiconductor device, such as a p-type field effect transistor (pFET), the dopant concentration of the dopant region may range from 1×1019atoms/cm3to 1×1021atoms/cm3.

In one embodiment, the semiconductor substrate5ais composed of a single crystal material, such as single crystal silicon. As used herein, the term “single crystal” denotes a crystalline solid, in which the crystal lattice of the entire sample is substantially continuous and substantially unbroken to the edges of the sample, with substantially no grain boundaries. In another example, the source and drain area of the semiconductor substrate5aof could be a polycrystalline material, such as polysilicon.

A dielectric layer10amay be formed atop the semiconductor substrate5a. The dielectric layer10aamay be composed of any dielectric material including, but not limited to, oxides, nitrides, oxynitrides, and combinations thereof. In one example, the dielectric layer10ais composed of silicon nitride. The dielectric layer10amay also be composed of silicon oxide (SiO2). Other examples of materials that are suitable for the dielectric layer10ainclude silicon containing dielectric materials, such as Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the dielectric layer10ainclude any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable. The dielectric layer10amay have a thickness ranging from 20 nm to 100 nm.

An interconnect15ais present in a via opening14athrough the dielectric layer10a. The via opening14amay have a width W1ranging from 10 nm to 60 nm. In another embodiment, the via opening14amay have a width W1ranging from 20 nm to 40 nm. The via opening14aexposes an upper surface of the portion of the semiconductor substrate5ain which the doped region6is present.

The interconnect15amay be composed of any electrically conductive material. “Electrically conductive” as used through the present disclosure means a material typically having a room temperature conductivity of greater than 10−8(Ω−m)−1. Examples of materials that are suitable for the interconnect15ainclude metals and doped semiconductors. For example, in one embodiment, the interconnect15amay be composed of tungsten (W). Other metals that are suitable for the interconnect15ainclude, but are not limited to, copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), silver (Ag), aluminum (Al), platinum (Pt), gold (Au) and alloys thereof.

In one embodiment, electrical contact between the interconnect15aand the doped region6of the semiconductor substrate5ais provided by a metal semiconductor alloy contact20a. Electrical contact means that the interconnect15aand the doped region6of the semiconductor substrate5aare in electrical communication through the interfacing metal semiconductor alloy contact20a, wherein the interface between metal semiconductor alloy contact20aand each of the interconnect15aand the doped region6is electrically conductive with low resistance.

In one embodiment, the metal semiconductor alloy contact20aextends into the dopant region6of the semiconductor substrate5a. The metal semiconductor alloy contact20amay have a perimeter defined by a convex curvature R1relative to a centerline C1of the via opening14aat the interface I of the interconnect15aand the upper surface of the semiconductor substrate5a. The term “convex” as used herein to define the curvature of the line corresponding to the perimeter of the metal semiconductor alloy contact20ameans that the perimeter of the metal semiconductor alloy contact20ais curving out when viewed from the point of reference P1that is the interface of the interconnect15aand the upper surface of the semiconductor substrate5aat the centerline c1of the via opening14a.

In one embodiments, the endpoints E1, E2for the convex curvature R1that define the metal semiconductor alloy contact20aare aligned to an interface I1between a sidewall S2of the via opening14a, a sidewall S1of the interconnect15aand an upper surface of the semiconductor substrate5a. By aligned to it is meant that the endpoints of the E1, E2for the convex curvature R1are in direct contact with the interface I1at the sidewall S2of the via opening14a, the sidewall S1of the interconnect15aand the upper surface of the semiconductor substrate5a. In some embodiments, the geometry of the metal semiconductor alloy contact20amay be referred to as having a mushroom shape. It is further noted that in some embodiments, the curvature R1of the perimeter of the metal semiconductor alloy contact20ais non-uniform. By “non-uniform” it is meant that the radius of the curvature R1is not constant and may vary, resulting in an oblong geometry, as opposed to a circular geometry.

In one embodiment, at least a portion of the metal semiconductor alloy contact20aextends from the interface I1between the via opening14aand the upper surface of the semiconductor substrate5aunder the dielectric layer10a. In one embodiment, the metal semiconductor alloy contact20aextends under the dielectric layer10aby a dimension W2ranging from 5 nm to 30 nm. In another embodiment, the metal semiconductor alloy contact20aextends under the dielectric layer10aby a dimension W2ranging from 10 nm to 20 nm.

The metal semiconductor alloy contact20amay be composed of a silicide or germicide. In one example, the metal semiconductor alloy contact20amay be composed of nickel silicide (NiSi). Other examples of compositions for the metal semiconductor alloy contact20amay include, nickel platinum silicide (NiPtySix), cobalt silicide (CoSix), tantalum silicide (TaSix), titanium silicide (TiSix) and combinations thereof.

FIG. 2depicts one embodiment of a semiconductor device110that includes metal semiconductor alloy contacts20bthat have a convex curvature R2that extends into the source region25and drain region30of the semiconductor device110. The semiconductor device110may be a field effect transistor (FET). A field effect transistor (FET) is a semiconductor device in which output current, i.e., source-drain current, is controlled by the voltage applied to a gate structure. A field effect transistor (FET) has three terminals, i.e., a gate structure35, a source region25and a drain region30. The gate structure35is a structure used to control output current, i.e., flow of carriers in the channel40, of a semiconducting device110, such as a field effect transistor, through electrical or magnetic fields. The channel40is the region between the source region25and the drain region30of a field effect transistor (FET) that becomes conductive when the semiconductor device110is turned on. The source region25, is a doped region in the transistor, in which majority carriers are flowing into the channel portion40. The drain region30is the doped region in transistor located at the end of the channel portion40, in which carriers are flowing out of the semiconductor device through the drain region30. Although the semiconductor device110that is depicted inFIG. 2is a field effect transistor (FET), the metal semiconductor alloy contacts20bof the present disclosure are suitable for any semiconductor device including complementary metal oxide semiconductor (CMOS) devices, bipolar junction transistor (BJT) semiconductor devices, schottky barrier semiconductor devices, and finFET semiconductor devices.

In the embodiment depicted inFIG. 2, the semiconductor device110is formed on a semiconductor on insulator (SOI) substrate5bthat includes at least an upper semiconductor layer9overlying a buried dielectric layer8. A base semiconductor layer7may be present underlying the buried dielectric layer8.

The upper semiconductor layer9may include any semiconducting material including, but not limited to, Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, and InP, or any combination thereof. In one embodiment, the upper semiconductor layer9has a thickness ranging from 1.0 nm to 10.0 nm. In another embodiment, the upper layer9has a thickness ranging from 1.0 nm to 5.0 nm. In a further embodiment, the upper semiconductor layer9has a thickness ranging from 3.0 nm to 8.0 nm. The base semiconductor layer7may be a semiconducting material including, but not limited to; Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP as well as other III/V and II/VI compound semiconductors. The dielectric layer8that is present underlying the upper semiconductor layer9and atop the base semiconductor layer7may be formed by implanting a high-energy dopant into the substrate and then annealing the structure to form a buried oxide layer, i.e., buried dielectric layer. In another embodiment, the dielectric layer8may be deposited or grown prior to the formation of the upper semiconductor layer9. In yet another embodiment, the semiconductor on insulator (SOI) substrate5bmay be formed using wafer-bonding techniques, where a bonded wafer pair is formed utilizing glue, adhesive polymer, or direct bonding. Although not depicted inFIG. 2, the semiconductor device110may also be formed on a bulk semiconductor substrate that is similar to the semiconductor substrate5athat is depicted inFIG. 1.

Referring toFIG. 2, the gate structure35may include at least a gate conductor36atop a gate dielectric37. The gate conductor36may be a metal gate electrode. In one example, the gate conductor36is composed of TiN, TaN, Al or a combination thereof. The metal gate conductor36may be composed of any conductive metal including, but not limited to, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and alloys that include at least one of the aforementioned conductive elemental metals. In another embodiment, the gate conductor36may also be composed of a doped semiconductor material, such as n-type doped polysilicon.

Although not depicted inFIG. 2, the gate conductor36may be a multi-layered structure. For example, the gate conductor36may include a second conductive material atop a metal gate electrode. In one example, the second conductive material may be a doped semiconductor material, such as a doped silicon containing material, e.g., n-type doped polysilicon. When a combination of conductive elements is employed, an optional diffusion barrier material such as TaN or WN may be formed between the conductive materials.

The gate conductor36of the gate structure35is typically present on a gate dielectric37. The gate dielectric37may be a dielectric material, such as SiO2, or alternatively a high-k dielectric, such as oxides of Hf, Ta, Zr, Al or combinations thereof. In another embodiment, the gate dielectric37is comprised of an oxide, such as ZrO2, Ta2O5or Al2O3. In one embodiment, the gate dielectric37has a thickness ranging from 1 nm to 10 nm. In another embodiment, the gate dielectric37has a thickness ranging from 1.0 nm to 2.0 nm.

A spacer38may be in direct contact with the sidewalls of the gate structure35. The spacer38typically has a width ranging from 2.0 nm to 15.0 nm, as measured from the sidewall of the gate structure35. The spacer38may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof. In one example, the spacer38is composed of silicon nitride (Si3Ny).

The gate dielectric37and the gate conductor36of the gate structure35are present over the channel portion of the semiconductor on insulator (SOI) substrate5b. Source region25and drain region30may be on opposing sides of the channel portion40. The conductivity-type of the source region25and the drain region30determines the conductivity of the semiconductor device110. Conductivity-type denotes whether the source region25and the drain region30have been doped with a p-type or n-type dopant. N-type dopant in a silicon containing material layer includes type V elements from the Periodic Table of Elements, such as phosphorus and arsenic. P-type dopant in a silicon containing material layer includes type III elements from the Periodic Table of Elements, such as boron.

Each of the source region25and the drain region30may include an extension dopant region and a deep dopant region (not shown). Typically, the dopant concentration of the extension dopant region having p-type dopant ranges from 5×1019atoms/cm3to 5×1020atoms/cm3. In another embodiment, the extension dopant region having p-type dopant ranges from 7×1019atoms/cm3to 2×1020atoms/cm3. Typically, the dopant concentration of the extension dopant region having n-type conductivity ranges from 5×1019atoms/cm3to 5×1020atoms/cm3. In another embodiment, the extension dopant region having n-type conductivity ranges from 7×1019atoms/cm3to 2×1020atoms/cm3. The deep dopant regions typically have the same conductivity dopant that may be present in greater concentration at greater depths into the upper semiconductor layer9of the semiconductor on insulator (SOI) substrate5bthan the extension dopant region.

At least one dielectric layer10bmay be present over the semiconductor device110. In the embodiment that is depicted inFIG. 2, an interlevel dielectric layer11is present on the upper surface of the semiconductor on insulator (SOI) substrate5b. The interlevel dielectric layer11may have a composition that is equal to the composition of the dielectric layer10athat is described above with reference toFIG. 1. In one example, the interlevel dielectric layer11may be composed of silicon nitride. The upper surface of the interlevel dielectric layer11may be coplanar with the upper surface of the gate structure35. The interlevel dielectric layer11may have a thickness ranging from 5 nm to 40 nm. In another embodiment, the interlevel dielectric layer11has a thickness ranging from 10 nm to 20 nm.

In one embodiment, a planarization stop layer12may be present on an upper surface of the interlevel dielectric layer11and on an upper surface of the gate structure35. The planarization stop layer12may have a thickness ranging from 5 nm to 40 nm. In another embodiment, the planarization stop layer12has a thickness ranging from 10 nm to 20 nm. The planarization stop layer12is a nitride or oxynitride material. In one example, the planarization stop later 12 is composed of silicon nitride (Si3Ny).

Referring toFIG. 2, a via opening14bmay be present through the interlevel dielectric layer and the planarization layer12to each of the source region25and the drain region30. The via opening14bmay have a width W3ranging from 15 nm to 60 nm. In another embodiment, the via opening14bmay have a width W3ranging from 30 nm to 40 nm. In one example, the via opening14bexposes the upper surfaces of the semiconductor on insulator (SOI) substrate5bin which the source region25and the drain region30are present. The interconnect15bthat is contained within the via opening14bis similar to the interconnect15athat is described above with reference toFIG. 1. Therefore, the above-description of the interconnect15ato the doped region6that is depicted inFIG. 1is suitable for the interconnect15bto the source region25and drain region30that is depicted inFIG. 2.

In one embodiment, electrical contact between the interconnect15b, the source region25and the drain region30is provided by a metal semiconductor alloy contact20b. The composition of the metal semiconductor alloy contact20bthat is depicted inFIG. 2is similar to the metal semiconductor alloy contact20athat is depicted inFIG. 1. Therefore, the above-description of the metal semiconductor alloy contact20athat is depicted inFIG. 1is suitable for the metal semiconductor alloy contact20bthat is depicted inFIG. 2.

In one embodiment, the metal semiconductor alloy contact20bextends into the source region25and the drain region30of the semiconductor on insulator (SOI) substrate5b. Similar to the metal semiconductor alloy contact20athat is depicted inFIG. 1, the metal semiconductor alloy contact20bthat is depicted inFIG. 2includes a perimeter defined by a convex curvature R2relative to a centerline C2of the via opening14bat the interface of the interconnect15band the upper surface of the semiconductor on insulator (SOI) substrate5b. Similar to the metal semiconductor alloy contact20athat is depicted inFIG. 1, the endpoints E3, E4for the convex curvature R2that define the metal semiconductor alloy contact20bthat is depicted inFIG. 2are aligned to an interface I2between a sidewall S3of the via opening14b, a sidewall S4of the interconnect15band an upper surface of the semiconductor on insulator (SOI) substrate5b. In some embodiments, the geometry of the metal semiconductor alloy contact20bmay be referred to as having a mushroom shape. It is further noted that in some embodiments, the curvature R2of the perimeter of the metal semiconductor alloy contact20bis non-uniform.

In one embodiment, at least a portion of the metal semiconductor alloy contact20bextends from the interface I2between the via opening14band the upper surface of the semiconductor on insulator (SOI) substrate5bunder the interlevel dielectric layer11. In one embodiment, the metal semiconductor alloy contact20bextends under the interlevel dielectric layer11by a dimension ranging from 5 nm to 30 nm. In another embodiment, the metal semiconductor alloy contact extends under the interlevel electric layer11by a dimension ranging from 10 nm to 20 nm.

In comparison to metal semiconductor alloy contacts that do not extend beyond the sidewall of the trench containing the metal semiconductor alloy contacts, the metal semiconductor alloy contacts20bhaving a convex curvature R2that extends under the interlevel dielectric11reduces the distance that the metal semiconductor alloy contact is separated from channel portion40of the semiconductor device40. In one embodiment, by reducing the distance that the metal semiconductor alloy contacts20bis separated from the channel portion40, the metal semiconductor alloy contacts20bhaving the convex curvature R2provides a 15% reduction in serial resistance, when compared to metal semiconductor alloy contacts that are contained within a trench and do not include a portion that extends beneath the intralevel dielectric layer.

Although only one semiconductor device110is depicted inFIG. 2, any number of semiconductor devices110may be formed on the semiconductor on insulator (SOI) substrate5b. The spacing the gate structures35of adjacent semiconductor devices dictates the pitch. The term “pitch” means the center-to-center distance between two repeating elements of a circuit including semiconductor devices. In one embodiment, the pitch may be measured from the center of the upper surface of a first replacement gate structure to the center of the upper surface of an adjacent replacement gate structure. The actual dimensions for the pitch may depend upon the technology node. In one example, the gate pitch is selected to correspond to the 20 nm technology node. In one example, the pitch ranges from 80 nm to 100 nm.

One embodiment of forming the structure depicted inFIG. 2is now described with reference toFIGS. 3-8.FIG. 3depicts one embodiment of an initial structure used in a method to provide the metal semiconductor alloy contacts20bthat are depicted inFIG. 2. The initial structure may include a semiconductor on insulator substrate5b, a gate structure35, source region25, drain region30, and a dielectric layer10b, wherein a via opening14bis present through the dielectric layer10bto each of the source region25and the drain region30. The gate structure35that is depicted inFIG. 3may be formed using replacement gate technology. In replacement gate technology, a sacrificial material dictates the geometry and location of the later formed gate structure35. The sacrificial material is used to form the doped regions of the semiconductor on insulator (SOI) substrate5bsuch as the source region25and the drain region30. The sacrificial material is then replaced with the gate structure35. By employing a sacrificial material, the thermal budget that is applied to the gate structure35may be reduced.

In one embodiment, a method sequence for forming the structure depicted inFIG. 3begins with forming a sacrificial gate structure (not shown), i.e., a sacrificial material having the geometry of the subsequently formed gate structure35, on a semiconductor on insulator (SOI) substrate5b. The semiconductor on insulator (SOI) substrate5bhas been described above with reference toFIG. 2. The sacrificial gate structure may be composed of any material that can be etched selectively to the underlying upper semiconductor layer9of the semiconductor on insulator (SOI) substrate5b. In one embodiment, the sacrificial gate structure may be composed of a silicon-containing material, such as polysilicon. Although, the sacrificial gate structure is typically composed of a semiconductor material, the sacrificial gate structure may also be composed of a dielectric material, such as an oxide, nitride or oxynitride material, or amorphous carbon.

The sacrificial material may be patterned and etched to provide the sacrificial gate structure. Specifically, and in one example, a pattern is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.

In one embodiment, the etch process removes the exposed portions of the sacrificial material layer with an etch chemistry that is selective to the substrate10. In one another embodiment, the etch process that forms the sacrificial gate structure is an anisotropic etch. An anisotropic etch process is a material removal process in which the etch rate in the direction normal to the surface to be etched is greater than in the direction parallel to the surface to be etched. The anisotropic etch may include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used at this point of the present disclosure include ion beam etching, plasma etching or laser ablation.

The spacer38is then formed adjacent to the sacrificial gate structure, i.e., in direct contact with the sidewall of the sacrificial gate structure. The composition and dimensions of the spacer38have been described above with reference toFIG. 2. In one embodiment, the spacer38may be formed by using a blanket layer deposition, such as chemical vapor deposition, and anisotropic etchback method.

The source region25and the drain region30may then be formed in portions of the semiconductor on insulator (SOI) substrate5bon opposing sides of the portion of the semiconductor on insulator (SOI) substrate5bthat the sacrificial gate structure is present on. In one embodiment, the source region25and the drain region30are formed using an ion implantation process. More specifically, when forming a p-type extension region portion of the source region25and drain region30a typical dopant species is boron or BF2. Boron may be implanted utilizing implant energies ranging from 0.2 keV to 3.0 keV with an implant dose ranging from 5×1014atoms/cm2to 5×1015atoms/cm2. BF2may be implanted utilizing implant energies ranging from 1.0 keV to 15.0 keV and a dose ranging from 5×1014atoms/cm2to 5×1015atoms/cm2. A typical implant for the n-type extension dopant region of the source region25and the drain region30is arsenic. The n-type extension dopant region of the source region25and the drain region30can be implanted with arsenic using implant energies ranging from 1.0 keV to 10.0 keV with a dose ranging from 5×1014atoms/cm2to 5×1015atoms/cm2. The deep dopant region of the source region25and the drain region30may have the same conductivity as the extension dopant region, but may be implanted with a higher dose and implant energy. The source region25and drain region30may further include halo implant regions. Halo implant regions typically have the opposite conductivity as the extension dopant region and may be formed using an angled ion implantation.

Referring toFIG. 3, the interlevel dielectric layer11is deposited atop the semiconductor device110and the semiconductor on insulator (SOI) substrate5. The composition of the interlevel dielectric layer11has been described above with reference toFIG. 2. The interlevel dielectric layer11may be deposited using chemical vapor deposition (CVD). Chemical vapor deposition (CVD) is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (25° C. to 900° C.); wherein solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include but are not limited to Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and others. In addition to chemical vapor deposition (CVD), the interlevel dielectric layer11may also be formed using spinning from solution, spraying from solution, and evaporation.

Following deposition, the interlevel dielectric layer11is planarized until the upper surface of the sacrificial gate structure is exposed. “Planarization” is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface. In one embodiment, the planarization process includes chemical mechanical polishing (CMP) or grinding. Chemical mechanical planarization (CMP) is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface.

The sacrificial gate structure is removed to provide an opening39to an exposed portion of the semiconductor on insulator (SOI) substrate5b. The sacrificial gate structure is typically removed using a selective etch process that removes the sacrificial gate structure selective to the semiconductor on insulator (SOI) substrate5b, the spacer38and the intralevel dielectric11. The etch may be an isotropic etch or an anisotropic etch. The anisotropic etch may include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used at this point of the present disclosure include ion beam etching, plasma etching or laser ablation. In comparison to anisotropic etching, isotropic etching is non-directional. One example of an isotropic etch is a wet chemical etch. In one embodiment, in which the sacrificial gate structure is composed of polysilicon, the upper semiconductor layer9of the semiconductor on insulator substrate5bis a silicon-containing material, and the spacer38is composed of nitride (Si3N4), the wet etch chemistry for removing the sacrificial gate structure may be composed of DHF and hot NH3, or TetraMethyl Ammonium Hydroxide (TMAH).

A functional gate structure35is formed in the opening39in the interlevel dielectric layer11to the semiconductor on insulator (SOI) substrate5b. In one embodiment, a gate dielectric37is formed on the exposed upper surface of the upper semiconductor layer9of the semiconductor on insulator (SOI) substrate5b. The gate dielectric37may be composed of a high-k dielectric material. The term “high-k” denotes a material having a dielectric constant that is greater than the dielectric constant of silicon oxide (SiO2) at room temperature, i.e., 20° C. to 25° C. In one embodiment, the high-k dielectric that provides the gate dielectric37is comprised of a material having a dielectric constant that is greater than 4.0, e.g., 4.1. In another embodiment, the high-k gate dielectric that provides the gate dielectric layer37is comprised of a material having a dielectric constant greater than 7.0. In yet another embodiment, the high-k gate dielectric that provides the gate dielectric layer37is comprised of a material having a dielectric constant ranging from greater than 4.0 to 30. The dielectric constants mentioned herein are relative to a vacuum at room temperature, i.e., 20° C. to 25° C.

In one embodiment, the gate dielectric37is formed using a deposition process, such as chemical vapor deposition (CVD). In another embodiment, the gate dielectric37may be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. The gate dielectric37may have a thickness ranging from 1 nm to 5 nm. In another embodiment, the gate dielectric37has a thickness ranging from 1 nm to 2.5 nm. In yet another example, the gate dielectric37has a thickness that ranges from 15 Å to 20 Å.

A gate conductor36is formed on the gate dielectric37filling the opening39. In one embodiment, the gate conductor36is composed of a metal, such as a work function metal layer. In one embodiment, in which the semiconductor device110is an n-type semiconductor device, the work function metal layer that provides the gate conductor36is an n-type work function metal layer. As used herein, an “n-type work function metal layer” is a metal layer that effectuates an n-type threshold voltage shift. “N-type threshold voltage shift” as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device. The “conduction band” is the lowest lying electron energy band of the doped material that is not completely filled with electrons. In one embodiment, the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV.

In one embodiment, the n-type work function metal layer is composed of at least one of TiAl, TaN, TiN, HfN, HfSi, or combinations thereof. The n-type work function metal layer can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering or plating. In one embodiment, the n-type work function metal layer is composed of titanium aluminum (TiAl) and is deposited using sputtering. As used herein, “sputtering” means a method for depositing a film of metallic material, in which a target of the desired material, i.e., source, is bombarded with particles, e.g., ions, which knock atoms from the target, where the dislodged target material deposits on a deposition surface. Examples of sputtering apparatus that may be suitable for depositing the n-type work function metal layer include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In one example, an n-type work function metal layer composed of TiN is sputtered from a solid titanium target, in which the nitrogen content of the metal nitride layer is introduced by a nitrogen gas. In another example, an n-type work function metal layer composed of TiN is sputtered from a solid target comprised of titanium and nitrogen. In addition to physical vapor deposition (PVD) techniques, the n-type work function metal layer may also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).

In another embodiment, the work function metal layer may be a p-type work function metal layer. As used herein, a “p-type work function metal layer” is a metal layer that effectuates a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal layer24ranges from 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device110, e.g., transistor, by making the channel of the device conductive. The term “p-type threshold voltage shift” as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device. A “valence band” is the highest range of electron energies where electrons are normally present at absolute zero.

In one embodiment, the p-type work function metal layer may be composed of titanium and their nitrided/carbide. In one embodiment, the p-type work function metal layer is composed of titanium nitride (TiN). The p-type work function metal layer may also be composed of TiAlN, Ru, Pt, Mo, Co and alloys and combinations thereof. In one embodiment, the p-type work function metal layer comprising titanium nitride (TiN) may be deposited by a physical vapor deposition (PVD) method, such as sputtering. Examples of sputtering apparatus that may be suitable for depositing the p-type work function metal layer include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In addition to physical vapor deposition (PVD) techniques, the p-type work function metal layer may also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).

In another embodiment, the gate conductor36is provided by a doped semiconductor, such as n-type doped polysilicon. In one embodiment, the gate conductor36is planarized until the upper surface of the gate conductor36is coplanar with the upper surface of the interlevel dielectric11, as depicted inFIG. 3. In some examples, the gate conductor36may be planarized using chemical mechanical planarization (CMP).

A planarization stop layer12may be formed atop the upper surface of the interlevel dielectric layer11and the gate conductor36. In one example, the planarization layer12is composed of silicon nitride (Si3N4). The planarization layer12may be deposited using chemical vapor deposition (CVD). Variations of CVD processes include but are not limited to Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and others. In addition to chemical vapor deposition (CVD), the planarization layer12may also be formed using spinning from solution, spraying from solution, and evaporation.

Via openings14bmay be formed through the planarization layer12and the interlevel dielectric layer11to expose an upper surface of the upper semiconductor layer9in which the source region25and the drain region30are present. The via openings14bmay be formed using photolithography and etch processes. For example, a photoresist etch mask can be produced by applying a photoresist layer to the upper surface of the planarization stop layer12, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer. The photoresist etch mask may be positioned so that portions of the planarization stop layer12and the interlevel dielectric layer11are not protected by the photoresist etch mask in order to provide the via openings14b.

The exposed portion of the planarization stop layer12and the interlevel dielectric layer11is then removed by a selective etch. The selective etch may be an anisotropic etch or an isotropic etch. In one embodiment, the via holes14bare first formed in the planarization stop layer12with an etch that terminates on the interlevel dielectric11. Thereafter, the via holes14bare then extended through the interlevel dielectric layer11to the source region25and the drain region30. In one example, when the planarization stop layer12is composed of silicon oxide or silicon nitride, and the upper semiconductor layer9of the semiconductor on insulator (SOI) substrate5is composed of silicon, the etch chemistry for forming the via holes14bto the source region25and drain region30is composed of fluorine based chemical, such as CF4, CClF2, SF6and combinations thereof. The width W3of the via opening14bis described above with reference toFIG. 2.

FIG. 4depicts forming an amorphous region19in the upper semiconductor layer9of the semiconductor on insulator (SOI) substrate5b. As used herein, the term “amorphous” denotes a non-crystalline solid. The amorphous region19may be composed of amorphous silicon. As used herein, the term “amorphous Si” (α-Si) denotes a non-crystalline form of silicon. The amorphous region19may have a geometry similar to the subsequently formed metal semiconductor alloy contact. In one embodiment, the amorphous region19has a perimeter defined by a convex curvature. At least a portion of the amorphous region19extends under the interlevel dielectric layer11at each sidewall S3of the via opening14b.

In one embodiment, the amorphous region19may be formed by angled ion implantation16through the via opening14binto the exposed upper surface of the upper semiconductor layer9of the semiconductor on insulator (SOI) substrate5b. In one embodiment, the remaining portion of the upper semiconductor layer9that is noted doped by the angled ion implantation16is crystalline, such as single crystal silicon and polysilicon.

Angled ion implantation16as used throughout the instant application denotes that dopants are implanted towards the exposed surface of the upper semiconductor layer9along a plane PL1that forms an acute angle α when intersecting with the plane PL1that is substantially perpendicular to the upper surface of the semiconductor-containing layer6. The angled ion implantation9may include an angle α ranging from 3° to 75°. In another embodiment, the angled ion implantation9includes an angle α ranging from 5° to 60°. In an even further embodiment, the angled ion implantation9includes an angle α ranging from 15° to 45°. It is noted that other angles are suitable for the angled ion implantation16, so long as at least a portion of the dopant is introduced to a portion of the upper semiconductor layer9that extends under the interlevel dielectric layer11.

The dopant composition, implant dose, and implant energy are selected to disrupt the crystalline state of the upper semiconductor layer9so that it is amorphous. In one example, prior to the angled ion implantation16, the upper semiconductor layer9is crystalline, such as single crystal silicon or polysilicon, wherein after the angled ion implantation16the implanted portions of the upper semiconductor layer9are amorphous. The dopant composition may be an n-type dopant, such as arsenic and phosphorus, p-type dopant, such as BF2or aluminum, or a neutral conductivity type dopant. In one embodiment, the dopants are composed of carbon, arsenic, boron, phosphorus, germanium, xenon, argon, krypton, or a combination thereof. It is noted that other dopants are also contemplated and are within the scope of the invention, so long as the dopants convert the implanted portion of the upper semiconductor layer9from a crystalline material to a material having an amorphous crystal structure.

In one example, the angled implant16may include a boron dopant and may employ an implant having an ion dosage ranging from 1×1013atoms/cm2to 5×1015atoms/cm2. In one embodiment, the angled implant16is carried out using an ion implant apparatus that operates at an energy ranging from 5.0 keV to 60.0 keV. In another embodiment, the angled implant16is carried out using an energy of from 10.0 keV to 40.0 keV. The angled implant16may be carried out at a temperature ranging from 50° C. to 800° C. In another embodiment, the angled implant16is carried out with a temperature ranging from 100° C. to 400° C.

The concentration of the dopant in the amorphous region19of the upper semiconductor layer9may range from 1×1018atoms/cm3to 8×1021atoms/cm3. In another embodiment, the dopant concentration in the amorphous region19of the upper semiconductor layer9ranges from 1×1019atoms/cm3to 3×1020atoms/cm3.

FIG. 5depicts removing the amorphous region19to form a divot21having a convex curvature R3relative to the centerline C2of the via opening14b. The curvature R3of the divot21may be mushroom shaped. In some embodiments, the curvature of the perimeter of the divot21is non-uniform, i.e., the divot21has an oblong geometry.

In one embodiment, the amorphous region19may be removed using a selective etch process. For example, the amorphous region19may be removed by an etch that removes material having an amorphous crystal structure, such as amorphous silicon, selective to material having a crystalline structure, such as single crystal silicon. In one embodiment, the amorphous region19may be removed with an etch having a selectivity single crystal silicon of greater than 100:1.

The selective etch may be an isotropic etch. An “isotropic etch” is a etch process that is not a directional etch. An isotropic etch removes the material being etched at the same rate in each direction. Isotropic etch processes are contrary to anisotropic etch processes, which preferentially etch in one direction, such as reactive ion etch (RIE). One example, of an isotropic etch is a wet chemical etch. In one embodiment, in which the amorphous region19is composed of amorphous silicon, and the remaining portion of the upper semiconductor layer9that has not been doped by the angled ion implantation16is composed of single crystal silicon, the amorphous region19may be removed by a wet etch having a composition of 126 HNO3:60 H2O: 5 NH4F. In another embodiment, in which the amorphous region19is composed of amorphous silicon, and the remaining portion of the upper semiconductor layer9that has not been doped by the angled ion implantation16is composed of single crystal silicon, the amorphous region19may be removed by a wet etch having a potassium hydroxide (KOH) composition. In one embodiment, the etch temperature may range from 20° C. to 80° C.

In one embodiment, the divot21that is formed by removing the amorphous region may extend under the interlevel dielectric layer11by a dimension ranging from 5 nm to 30 nm, as measured from the sidewall (S2) of the via opening14b. In another embodiment, the divot21that is formed by removing the amorphous region21may extend under the interlevel dielectric layer11by a dimension ranging from 10 nm to 20 nm, as measured from the sidewall (S2) of the via opening14b.

FIG. 6depicts one embodiment of forming a metal containing material22on the divot21. The metal containing layer22may be deposited on the upper surface of the planarization stop layer12, the sidewalls S2of the via opening14b, and the base of the divot21. In one embodiment, the metal containing material22fills the divot21. The conformal deposited metal containing material22may be deposited on the convex curvature R3of the divot21including the portion of the divot21that extends under the interlevel dielectric layer11.

In one embodiment, the metal containing layer22is a conformally deposited layer. The term “conformal layer” and “conformally deposited layer” denotes a layer having a thickness that does not deviate from greater than or less than 20% of an average value for the thickness of the layer. The metal containing material22may be deposited using physical vapor deposition (PVD) methods or chemical vapor deposition (CVD) methods. Examples of physical vapor deposition (PVD) that are suitable for forming the metal containing material22include sputtering and plating. As used herein, “sputtering” means a method of depositing a film of material on a semiconductor surface. A target of the desired material, i.e., source, is bombarded with particles, e.g., ions, which knock atoms from the target, and the dislodged target material deposits on the semiconductor surface. Examples of sputtering apparatuses include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering.

In one example, the metal containing material22may be composed of nickel or nickel platinum alloy. The metal containing material22may also include at least one of nickel (Ni), cobalt, (Co), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), platinum (Pt) and combinations thereof. The metal containing material22may have a thickness ranging from 5 nm to 20 nm. In another embodiment, the metal containing material22may have a thickness ranging from 6 nm to 15 nm.

FIG. 7depicts one embodiment of converting the metal containing material22and a portion of the upper semiconductor layer9semiconductor on insulator (SOI) substrate5bthat is adjacent to the divot21into a metal semiconductor alloy contact20bthat has a convex curvature R2that extends into the source region25and the drain region30. Following deposition of the metal containing material22, the structure is subjected to an annealing step including, but not limited to, rapid thermal annealing. During annealing, the deposited metal containing material22reacts with the semiconductor material of the upper semiconductor layer9forming a metal semiconductor alloy contact20b, such as a metal silicide. In one embodiment, the thermal anneal is completed at a temperature ranging from 350° C. to 600° C. for a time period ranging from 1 second to 90 seconds. Following thermal anneal, the non-reacted portion of the metal containing layer22is removed. The non-reacted portion of the metal containing layer22may be removed by an etch process that is selective to the metal semiconductor alloy contact20b. The composition and the geometry of the metal semiconductor alloy contact20bhas been described above with reference toFIG. 2.

Referring toFIG. 2, an interconnect15bmay be formed in direct contact with the metal semiconductor alloy contact20b, wherein the interconnect15bis contained within the via opening14b. Interconnects15bare formed by depositing a conductive metal into the via openings14busing a deposition process, such as physical vapor deposition (PVD). Examples of physical vapor deposition (PVD) that are suitable for forming the interconnect15binclude sputtering and plating. Examples of sputtering apparatuses suitable for forming the interconnect15binclude DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. The interconnect15bmay also be formed using chemical vapor deposition. The interconnect15bmay be composed of a conductive metal, such as tungsten, copper, aluminum, silver, gold, and alloys thereof.

While the claimed methods and structures has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the presently claimed methods and structures.