Silicon controlled rectifier ESD structures with trench isolation

A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates generally to a structure and manufacturing process of a semiconductor device which provides improved ESD protection for internal active semiconductor devices and more particularly to a semiconductor SCR like device which when used with shallow trench isolation, provides improved parasitic bipolar characteristics resulting in improved ESD protection performance.

(2) Description of Prior Art

The discharge of electrostatic energy from the human body or other sources known as Electrostatic discharge (ESD) into the input or output pads of integrated circuit semiconductor devices has shown to cause catastrophic failures in these same circuits. This is becoming more important as modern metal oxide semiconductor circuit technology (MOS) is sealed down in size and increased in device and circuit density. Prevention of damage from ESD events is provided by protection devices or circuits on the input or output pads of the active logic circuits which shunt the ESD energy to a second voltage source, typically ground, thereby bypassing the active circuits protecting them from damage. Various devices such as silicon controlled rectifiers (SCR) have been utilized to essentially shunt the high ESD energy and therefore the ESD stress away from the active circuits.

Isolation is required between these ESD protection devices and the active circuit devices, as well as between the active devices themselves. Originally areas of local thick oxide, often called LOCOS or field oxide, have been used to provide this isolation. While having good isolation properties, this isolation method uses more surface area, or “real estate”, than an alternative isolation method using shallow, relatively narrow trenches filled with a dielectric, typically silicon oxide (SIO2), called shallow trench isolation (STI).

While providing good isolation properties, the STI structure has limiting effects on the current triggering and capacity of the SCR ESD protection devices. As discussed in the paper “Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks” by Voldman et al., EOS/ESD Symposium 98-151, pages 151 to 160, during STI formation, the STI region is exposed to the etching process, leading to non-planer STI edges where the silicon region extends above the isolation edge. The non-planer STI edge is called “STI pull-down”. The impact of STI pull-down, and the interaction with the salicide process typically used in current contact technology, as well as junction depth reduction of the diode elements bounded by the STI devices, all degrade ESD protection capabilities by reducing the parasitic bipolar current gain, beta, (β). This increases the holding voltage and trigger current of the lateral SCR, reduces lateral heat transfer capability, and possibly limits the type of ESD networks implemented. Among other things, this can result in device failure before the SCR is fully on, or a high on-resistance for the SCR reducing the ESD failure threshold.

FIG. 1Ais a simplified cross section of a typical prior art SCR ESD protection device. Shown is a P substrate10, with an N-well12and which contains contact regions N+16and P+18. The N-well12contact regions are isolated and bounded by the shallow trench isolation (STI) structures14A,14B and14C. The N-well12is also bounded by STI elements14A and14C. The P substrate also contains N+ contact20bounded by STI elements14C and14D, and P+ contact22bounded by STI structures14D and14E. Also depicted inFIG. 1Aare parasitic vertical PNP bipolar transistor T1and lateral NPN bipolar transistor T2with parasitic resistors R1and R2. As is well recognized, an SCR device is essentially a P-N-P-N structure as depicted in FIG.1B. The P+ contact18is the anode end of the device and is connected to the active circuit input or output pad8as well as to the N+ N-well contact16. The junction between the P+ contact region18and the N-well12is the first junction of the SCR.

The N-well12and the P substrate10form the second junction. The third device junction is formed by the substrate10and substrate N+ contact20, which also is the cathode terminal of the device. N+ contact20is connected to a second voltage source24, typically ground, and also to substrate P+ contact22.FIG. 1Crepresents the electrical schematic of the prior art device showing the parasitic vertical bipolar PNP transistor T1and parasitic lateral NPN bipolar transistor T2as well as the resistors R1and R2. A positive ESD voltage event will cause the T1base-collector junction to go into avalanche conduction, turning on T2and providing the regenerative conduction action shunting the ESD current to the second voltage source, typically ground. A negative ESD voltage pulse will forward bias the base-collector junction of T1, again shunting the current to the second voltage source.

However, as indicated above, the STI isolation structures inhibit lateral current conduction near the surface, lower the parasitic bipolar semiconductor current gain, and can interfere with device thermal characteristics.

FIG. 2Arepresents another prior art protection device, a low voltage trigger SCR (LVTSCR). There is no STI between the N-well N+ contact16and SCR P+ anode18. The STI structure has essentially been replaced by a N+ region28straddling the N-well to P substrate lateral boundary. A FET gate has been inserted between the N+ region28and the N+ region20which essentially become the drain and source of a NFET respectively. The NFET source region also functions as the SCR cathode. The prior art LVTSCR device operational trigger voltage is reduced by the NFET device breakdown voltage. The STI elements still reduce the desirable ESD protection characteristics as previously discussed.

FIG. 2Brepresents a prior art modified lateral SCR. This device does not have the NFET of the LVTSCR, but retains the N+ region28straddling the N-well12and the P substrate10lateral boundary and which provides an additional source of current for triggering the SCR thereby enabling a lower trigger voltage than a more conventional SCR.

The invention in various embodiments allows selective use of STI elements while improving ESD protection by the strategic use of polysilicon gates

The following patents describe ESD protection devices.

The following technical report discusses STI bound ESD protection networks

“Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks” by Voldman et al., EOS/ESD Symposium 98-151, pages 151 to 160.

SUMMARY OF THE INVENTION

Accordingly, it is the primary objective of the invention to provide a novel, effective structure and manufacturable method for protecting integrated circuits, in particular field effect transistor devices, from damage caused by electrostatic discharge (ESD) events during normal operation.

It is a further objective of the invention to improve ESD protection involving SCR elements employing shallow trench isolation (STI).

In addition, it is an objective of this invention to minimize degradation in the SCR diode device characteristics such as diode leakage.

It is yet another object of the invention to provide a manufacturable method for forming the SCR ESD protection structure while maintaining the required operating characteristics of the devices being protected.

The above objectives are achieved in accordance with the embodiments of the invention that describes a novel structure and process for a SCR like ESD protection device. The device is situated on a semiconductor substrate, typically P doped, and containing a N-well with P+ and N+ contact regions. A STI structure defines one N-well-substrate lateral boundary as well as the N-well N+ contact lateral boundary near the substrate surface. A second STI structure defines the N-well to P substrate lateral boundary near the substrate surface on the N-well opposite the N+ contact region. A third STI structure defines one lateral or horizontal boundary near the surface for the P+ substrate contact.

A N-well P+ contact and a N+ substrate contact are also defined. The N-well P+ region forms the anode of the SCR device, and is electrically connected to the N+ N-well contact and to the active logic device input or output pad. The substrate N+ element forms the SCR cathode and is electrically connected to the substrate P+ contact and to a second voltage source, typically ground. A feature of the invention uses gate elements, typically polysilicon with salicides, that overlay the surface regions between the N-well N+ and P+ contact regions and the N-well P+ contact region and adjacent STI. The N-well contacts and associated gate elements are electrically tied together and to the first voltage source, typically the active device input pad.

Similar gate elements overlay the surface regions between the substrate P+ and N+ contact regions and the substrate N+ and adjacent STI element. The substrate contacts and associated gate elements are electrically connected together and to the second voltage source, typically ground. The uniqueness of the invention structure is in the insertion of the gate elements and the elimination of the prior art STI structure between the anode N+-P+ contacts and the cathode N+ and P+ contacts.

In alternative invention embodiments, the gate structures are utilized in low voltage trigger SCR (LVTSCR) devices and also in the modified lateral SCR device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3Ashows a simplified cross section of one embodiment of the invention. A P doped substrate110with typical doping concentration of between 1E14 and 1E16 atoms/cm3(a/cm3) contains an N-well112with typical dopent concentration between 1E16 and 1E18 a/cm3. The N-well112is bounded at and near the surface by shallow trench isolation (STI) elements114A and114B, typically between 0.2 to 1 um wide and 0.4 to 2.5 um deep. The STI elements are filled with a dielectric, typically silicon oxide (SiO2). Within the N-well region112are a N+116and P+118contact regions, with typical dopent densities of between 1E19 and 1E21 a/cm3. The N+ region is bounded on the side away from the P+ contact118by the STI114A. Overlaying the surface between the N+ contact116, P+ contact118, and between P+ contact118and STI114B, is gate element126. As depicted inFIG. 3B, the gate element126is composed of gate oxide insulation126C, typically SiO2with a thickness between 50 and 180 angstroms (Å), and a doped polysilicon conductor element126B with a thickness between 1500 and 3000 Å and with a refractory metal126A such as titanium (Ti) or cobalt (Co). The polysilicon (poly) is typically doped with a donor element such as phosphorous to a density of between E17 and E21 a/cm3to improve conductivity. The use of this gate element enables the elimination of an STI isolation element between the two contacts, which improves the lateral current conduction and Joule heating capability for an ESD event.

The P+ contact18is the anode of the SCR device, and is electrically connected to the N+ contact116, the gate element126, and the active device input or output pad108.

The substrate110has N+ contact120and P+ contact122, with a typical dopent concentration of between 1E19 and 1E21 a/cm3of donor and receptor dopents respectively. A gate element132overlays the surface between the STI114B, the N+ contact120, and the P+ contact122. The P+ contact122is bounded by STI14C. As depicted inFIG. 3B, gate elements126and132are constructed of an insulator, SiO2126C/132C, a doped polysilicon conducting element126B/132B, and a silicide126A/132A. The presence of the gates126and132bounding the STI region114B have the effect of reducing leakage current when connected to the appropriate voltage sources, that is typically to the anode voltage for gate element126and to the cathode voltage for gate element132.

The N+ contact120is the SCR cathode and is electrically connected to the gate132, the substrate P+ contact122, and a second voltage source124, typically ground. The presence of the gate132allows for the elimination of an STI isolation structure between the N+ contact120and the P+ contact122, once again contributing to improved lateral current conduction and improved Joule heating characteristics for an ESD event. The connection of the gates126and132to the respective voltage sources also has the benefit of reducing device leakage during normal circuit operation.

As depicted inFIG. 4, the gate elements126and132have a rectangular horizontal topology that effectively bounds P+ contact region118and N+ contact region120respectively. The STI structures114A and114B are indicated by the dotted lines in FIG.4.

Another embodiment of the invention is shown in FIG.5. The unique design of the invention improves the ESD protection of a LVTSCR device. The SCR trigger voltage can be reduced by design by inserting a N+ doped region128on the lateral boundary between the N-well112and the substrate110. This region has a dopent concentration typically between 1E19 and 1E21 a/cm3and forms the drain of a N-channel thin oxide field effect transistor (FET). The FET N+ drain128connects to the N region N-well112base of the SCR and the FET N+ source120, which also serves as the SCR cathode, is connected to the second voltage source, typically ground. This arrangement has the effect of lowering the trigger voltage of the SCR by the design of the channel length and/or the gate oxide thickness of the FET to provide a LVSCR element. The unique structure of the invention design places gate126between the N-well N+ contact116and the SCR P+ anode118, and the P+ anode118and the FET drain120. Again, this eliminates the need for any STI structures between theses elements and at the same time limits leakage by connecting the gate to the SCR anode118. Similarly, the invention structure places gate132between the FET source120and the substrate P+ contact122. This gate12enables the elimination of STI element14D, and serves to reduce the leakage current between N+ region120and P+ region122

In yet another embodiment depicted inFIG. 6, the invention is applied to the modified lateral SCR, resulting in improved ESD protection capabilities over the prior art design. In the method of the invention, a polysilicon gate126with SiO2insulator, poly conductor and silicide contact element, bridges the N-well N+ contact116and the N-well P+ contact118, and also is between the P+ contact118and the N+ region128. Another gate element132bridges the substrate N+ contact120and the substrate P+ contact122. The N-well N+ contact116, gate126, and the N-well P+ contact118, which also serves as the device anode, are electrically connected together and to the active circuit input pad108.

The substrate N+ contact120, which also serves as the SCR cathode gate132, and the substrate P+ contact122are electrically connected together and to a second voltage source124, typically ground. A STI structure114F provides isolation between the N+ contact region128and the cathode N+ region120.

The process to develop an embodiment of the invention is outlined in FIG.7A throughFIG. 7Fwhich shows the structure for a P substrate in various stages of processing.FIG. 7Arepresents a patterned semiconductor substrate110with a nominal P doping level of between about 1E14 and 1E16 a/cm3. The substrate surface is covered by a thermally grown or chemical vapor deposition (CVD) first oxide layer140, sometimes called the pad oxide, which provides thermal stress relief. This layer is typically between 200 and 600 Å in thickness. A CVD layer of silicon nitride (SiN)142derived typically from a silane or dichlorosilane source element is placed over the pad oxide as a masking element to a thickness of between 1000 and 2000 Å. This in turn is covered by a conventional photolithographic masking material such as photo resist (PR)144with a thickness typically between 4000 and 10,000 Å. The structure as shown inFIG. 7Ahas been patterned in preparation for the N-well112doping. A donor dopent, typically phosphorous (P), is implanted with a typical dosage range of between 1E15 and 1E17 a/cm2) and with an energy range of between 30 and 80 KeV. This produces a N-well doping density of between 1E16 and 1E18 a/cm3.

FIG. 7Brepresents the partially completed device after the N-well masking elements have been removed, shallow trench isolation (STI) elements have been inserted into the structure, and the substrate patterned in preparation for the doping of the N+ contracts regions,116,120. The STI elements are created with an etching process, typically a dry anisotropic plasma etch to form the trenches, typically to a depth of between 0.4 and 2.5 um in depth and between 0.2 and 1 um in width. The trenches are subsequently filled with a silicon oxide (SiO2) by a low-pressure chemical vapor deposition (LPCVD), or a sub-atmospheric CVD (SACVD), or a high-density plasma process. After filling, the STI elements are planarized by either an etch process or, more typically, a chemical mechanical polish (CMP) process. The SiN layer142is removed, typically using a hot phosphoric acid (H3PO4) with a temperature between about 150 and 180 degrees centigrade (°C.), and the pad oxide has been removed typically using dilute hydrofluoric acid (HF).

A gate oxide layer146is then thermally grown to a thickness of between about 50 and 180 Å, and a layer of polysilicon (poly)148has been deposited by LPCVD to a thickness of between 1500 and 3000 Å to serve as part of the gate conductor system. The LPCVD poly process uses a 100% silane source, or, alternatively, a gas stream containing N2or H2. The poly is typically doped with a donor element such as As to produce a dopent concentration of between 1E17 and 1E21 a/cm3to improve conductivity. The N+ contact regions116and120are doped with a donor element as indicated inFIG. 7B, typically arsenic (As), with a dosage level between about 1E13 and 1E15 a/cm2, and with an energy between 20 and 40 KeV. This results in N+ contact regions with a donor concentration of between about 1E19 and 1E21 a/cm3.

FIG. 7Cshows the partially completed device patterned and prepared for the P+ contact region implant. This is done with an acceptor element, typically boron (B) with a dosage of between about 1E12 and 1E13 a/cm2, and an implant energy of between 40 and 80 KeV resulting in a P+ contact area with a dopent concentration of between 1E19 and 1E21 a/cm3. The device is then patterned to remove the gate oxide and polysilicon from regions where not required, and an oxide layer150, is deposited, typically by LPCVD as shown in FIG.7D.

This oxide150is patterned in preparation for etching metal contact opening, typically using a RIE anisotropic etch process, to the N+ regions116and120, and the P+ regions118and122, and the contact regions of gates126and132. This is followed by a blanket evaporation of metal, typically using aluminum or 1% silicon doped aluminum, but could be other alloys such as titanium platinum. The main metallurgy system could also be used in conjunction with refractory type “barrier” metals such as titanium-tungsten (TiW) or titanium nitride (TiN). Most commonly used methods for developing the metallurgy system on the wafer are vacuum evaporation using either filament, electron beam or flash hot plate as sources, or physical vapor deposition (PVD) commonly known as sputtering. Common sputtering methods would be RF sputtering or magnetron sputtering. With any method, the wafer is blanketed with the metal, the patterned and unwanted metal removed by etching resulting in a structure shown in FIG.7E.

The metal element152A electrically connects the SCR anode P+ region118with gate126and the N-well N+ contact116. Not shown is the completion of the conductor to the logic circuit input pad. Similarly, as depicted inFIG. 7E, the metal element152B electrically connects the SCR cathode N+ region120with the gate132and the substrate P+ contact122. Not shown is the electrical connection of the conductor to a second voltage source, typically ground.

As represented inFIG. 7F, after selective removal of unwanted metal, a final passivation covering layer154is deposited, typically SiO2, or silicon nitride (SiN), or borophosphorus silicate glass (BPSG).