Family of multiplexer/flip-flops with enhanced testability

A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is a high-performance flop with multiplexer at the input.

BACKGROUND OF THE INVENTION

The problem of invention is a high-performance flop with multiplexer built into the input. This combination virtually hides the delay of the multiplexer, reducing a level of logic on critical paths. For the Texas Instruments TMS320C6400 family of digital signal processors (DSPs) this combination yields approximately a 5% frequency improvement over not having this invention.

There is a problem with circuits of this type. Such circuits typically present a problem of stuck-at fault visibility. In prior art, test pin itself was not observable. This yields stuck-at-fault coverage loss. Latest reliability targets require greater than 99% stuck-at-fault coverage.

SUMMARY OF THE INVENTION

This invention is a multibit combined multiplexer and flip-flop circuit having a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for each of a plurality of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled a corresponding logical AND and said corresponding inverter.

The input section of each bit circuit may include a scan input and a scan input pass gate. The flip-flop section of each bit circuit further includes a scan output. Each per bit control section receives a scan enable input signal.

The input section of each bit circuit further includes a test input terminal and a test select input terminal. The test select input selects input of the test signal or the scan input.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Input section110receives data inputs d0and d1and selection input s0. Pass gates111and112are driven by opposite polarities of selection input s0employing inverter113. Depending upon the digital state of selection input s0, one and only one of pass gates111and112are conducting the other pass gate in non-conducting. If pass gate111is conducting and pass gate112is non-conducting, then input section110selects input d1. If pass gate112is conducting and pass gate111is non-conducting, then input section110selects input d0. The selected input signal supplies the input of pass gate114. When conducting pass gate114couples the selected input to master flip-flop section120.

Master flip-flop section120includes a latch formed by cross-coupled inverters121and122. Under the proper combination of input control signals the data from the selected data source d0or d1is stored in this latch. At the proper time in the cycle of clock clk pass gate124supplies the state of the master flip-flop to slave flip-flop section130.

Slave flip-flop section130includes a gated latch formed of inverters131and132and pass gate133. Inverter134generates a q output of the state of the latch. Inverter135generates a scan output signal so of the opposite state of the latch.

Control section140receives various input signal and generates control signals for pass gates111,112,114,124and133and controlled inverters121and122. Control section140receives a clock signal clk, a scan enable signal se and a scan data input si. Inverter141generates an inverted clock signal clkz1. Inverter142generates an inverted scan enable signal sez. NAND gate143combines clkz1and sez to generate int1. Inverter144generates the inverse signal int1z. The pair of signals int1and int1zcontrol pass gate114and controlled inverter122. NAND gate147combines clkz1and se to generate int0. Inverter148generates the inverse signal int0z. The pair of signals in01and int0zcontrol pass gate146and controlled inverter121. Inverter145inverts scan data input si. Inverter145supplies pass gate146controlled by int0and int0z. Depending upon the state of scan enable signal se only one of the paired signals int0/int0zor int1/int1zare active cycling with the clock signal clk.

Two-input multiplexer/flip-flop100operates generally as follows. Select signal s0determines selection of either input d0or input d1. When in normal mode as selected by scan enable signal se, the selected signal is passed to master flip-flop section120and then to slave flip-flop section130where it becomes available at output q. When in scan mode as selected by scan enable signal se, scan input si is input to master flip-flop section120. This scan input is passed to slave flip-flop section130and becomes available at scan output so. Table 1 summarizes this operation.

When scan is enabled (se=1), two-input multiplexer/flip-flop100ignores the data inputs d0and d1whatever the state of select signal s0(s0is X or don't care) and stores scan input si.

There are several disadvantageous aspects of the two-input multiplexer/flip-flop100. This circuit has a longer than necessary setup time. Note that the input path of two-input multiplexer/flip-flop100includes two layers of pass gates. An input signal must pass a first pass gate layer at pass gate111or112and a second pass gate layer at pass gate114. This leads to a larger setup than necessary. These two layers of pass gates require a larger driver circuit. Such a larger driver circuit requires greater silicon area and results in more power consumption. These factors all lead to a disadvantageous circuit combination.

FIG. 2illustrates a prior art four-input multiplexer/flip-flop200.FIG. 2illustrates a single bit circuit of what is generally a multi-bit circuit. Multiplexer/flip-flop200includes: input section210including pass gates211,212,213,214,216and217and driver215; master flip-flop section220is similar to master flip-flop section120; slave flip-flop section230is similar to slave flip-flop section130; and control section240including inverters241,242,243,244,245,246,247,249and251, NOR gates248and250.

Input section210receives data inputs d0, d1, d2and d3, selection signal pairs s0/s0z, s1/s1z, s2/s2zand s3/s3zand scan input si. Depending upon the state of the selection signal pairs s0/s0z, s1/s1z, s2/s2zand s3/s3zone of pass gates211,212,213and214passes the corresponding input signal d3, d2, d1or d0. The selection signals pairs s0/s0z, s1/s1z, s2/s2zand s3/s3zare controlled to open only one of the pass gates211,212,213and214. The selected input signal supplies the input of pass gate216. When conducting pass gate216couples the selected input to master flip-flop section220. This operation is very similar to that of input section110except that there are four inputs in input section210and they are uncoded as contrast to the coded input used in input section110. Pass gate217when enabled couples scan input s1to master flip-flop section220.

Input section210further includes a testz input driving the gates of dual MOS transistor driver215. A signal upon the testz input forces master flip-flop section220into a predetermined state regardless of other inputs. This testz input enables test of multiplexer/flip-flop200.

Master flip-flop section220is similar to master flip-flop section120and will not be described in detail.

Slave flip-flop section230is similar to slave flip-flop section130and will not be described in detail.

Control section240receives the control signals and generates corresponding signals used in multiplexer/flip-flop200. Control section240receives input signals clk, s0, s1, s2, s3, se and si and generates control signals for pass gates211,212,213,214,216and217and the controlled inverters in master flip-flop section220and slave flip-flop section230. Inverter241generates an inverted clock signal clkz1. Inverter242generates a further inverted clock signal clkb. Inverter243generates an inverted s0signal s0z. Control signals s0and s0zcontrol the operation of pass gate214. Inverter242generates an inverted s1signal s1z. Control signals s1and s1zcontrol the operation of pass gate213. Inverter245generates an inverted s2signal s2z. Control signals s2and s2zcontrol the operation of pass gate212. Inverter246generates an inverted s3signal s3z. Control signals s3and s3zcontrol the operation of pass gate211. Inverter247generates an inverted enable signal sez. NOR gate248combines clkz and se to generate clkd and inverter249generates its inverse clkdz. Signals clkd and clkdz control pass gate216. NOR gate250combines clk and sez to generate clks and inverter251generates its inverse clksz. Signals clks and clksz control pass gate217.

Four-input multiplexer/flip-flop200operates generally as follows. Select signals s0, s1, s2and s3determine selection of either input d0, d1, d2or d3. When enabled by scan enable signal se, the selected signal is passed to master flip-flop section220and then to slave flip-flop section230where it becomes available at output q. Testz places master flip-flop220in a known state. Si when enabled by clks/clksz places master flip-flop220in a known state.

There are several disadvantageous aspects of the four-input multiplexer/flip-flop200. As the case of two-input multiplexer/flip-flop100this circuit has a longer than necessary setup time. The input path of four-input multiplexer/flip-flop200includes two layers of pass gates. An input signal must pass a first pass gate layer at pass gate211,212,213or214and a second pass gate layer at pass gate216. This leads to a larger setup time than necessary. Such plural pass gate levels require a larger driver circuit. Such a larger driver circuit requires greater silicon area and results in more power consumption. These factors all lead to a disadvantageous circuit combination.

Four-input multiplexer/flip-flop200includes an additional disadvantage. Four-input multiplexer/flip-flop200includes no provision for testing the testz input. Failure of the testz input cannot be detected in four-input multiplexer/flip-flop200. This is disadvantageous in requiring indirect diagnosis of faults in the testz input.

FIG. 3illustrates a two-input multiplexer/flip-flop300according to this invention.FIG. 3generally illustrates a single bit circuit of what is generally a multi-bit circuit. Two-input multiplexer/flip-flop300is a substitute for prior art two-input multiplexer/flip-flop100. Two-input multiplexer/flip-flop300includes: input section310including pass gates311,312and314and inverter313; master flip-flop section320is similar to master flip-flop section120; slave flip-flop section330is similar to slave flip-flop section130; per bit control section340including inverters341,342,343and344; and shared control section350including inverters351,352and354and NAND gates353,355,356and357.

Input section310receives data inputs d0and d1and scan input si. Note that shared control section350receives selection input s0. Per bit control section340and shared control section350cooperate to generate the paired control signals s0_clk/s0_clkz, s1_clk/s1_clkz and se_clk/se_clkz. Paired control signals s0_clk/s0_clkz control pass gate312. Paired control signals s1_clk/s1_clkz control pass gate311. Pass gates311and312are driven by opposite polarities of selection input s0. Depending upon the digital state of selection input s0, one and only one of pass gates311and312is conducting the other pass gate in non-conducting. If pass gate311is conducting and pass gate312is non-conducting, then input section310selects input d1. If pass gate312is conducting and pass gate311is non-conducting, then input section310selects input d0. The selected input signal supplies the input of master flip-flop section320. Inverter313receives scan input s1and drives pass gate314. Pass gate314is controlled by the signal pair se_clk/se_clkz. Pass gate314when enabled supplies scan input si to master flop-flop section320.

Master flip-flop section320is similar to master flip-flop section120and will not be described in detail.

Slave flip-flop section330is similar to slave flip-flop section130and will not be described in detail.

Per bit control section340operates in conjunction with shared control section350. Shared control section350receives input signals clk, se and s0for a set of similarly controlled bit circuits and generates intermediate control signals s0_clkz, s1_clkz, se_clkz and fb_clk. Per bit control section340of each bit circuit receives these intermediate signals and generates control signals s0_clk, s1_clk, se_clk and fb_clkz which control operation of two-input multiplexer/flip-flop300.

Shared control section350includes inverters351,352and354and NAND gates353,355,356and357. Inverter351receives clock signal clk and generates inverse clock signal clkz. Inverter352receives enable signal se and generates inverse enable signal sez. NAND gate353receives signal fb_clkz and selection signal s0and generates signal s0_clkz. Inverter354receives selection signal s0and supplies one input to NAND gate355. Another input of NAND gate355receives signal fb_clkz. NAND gate355generates signal s1_clkz. NAND gate356receives inputs scan enable signal se and inverted clock signal clkz and generates signal se_clks. NAND gate356receives inverted scan enable signal sez and the inverted clock signal clkz and generates signal fb_clk.

Per bit control section340includes inverters341,342,343and344. Inverter341receives signal s0_clkz and generates signal s0_clk. Inverter342receives signal s1_clkz and generates signal s1_clk. Inverter343receives signal se_clkz and generates signal se_clk. Inverter344receives signal fb_clk and generates signal fb_clkz.

Two-input multiplexer/flip-flop300operates generally as follows. Select signal s0determines selection of either input d0or input d1. When enabled by scan enable signal se, the selected signal is passed to master flip-flop section120and then to slave flip-flop section130where it becomes available at output q. Scan input si supplies master flip-flop section320when enabled by scan enable signal se.

Two-input multiplexer/flip-flop300of this invention is advantageous over prior art two-input multiplexer/flip-flop100. The two layer pass gate input of prior art two-input multiplexer/flip-flop100is replaced by a single layer pass gate input in two-input multiplexer/flip-flop300of this invention. This reduction is pass gate layers is achieved by making input pass gates311and312of this invention controlled by clocked signal pairs s0_clk/s0_clkz and s1_clk/s1_clkz. This combines the input selection of pass gates111and112and the clocking of pass gate114in a single layer of pass gates. This results in reduced setup time, reduced driver size and reduced power consumption.

Input section410receives data inputs d0, d1, d2and d3, selection signal pairs s0_clk/s0_clkz, s1_clk/s1_clkz, s2_clk/s2_clkz and s3_clk/s3_clkz. Depending upon the state of the selection signal pairs s0_clk/s0_clkz, s1_clk/s1_clkz, s2_clk/s2_clkz and s3_clk/s3_clkzz one of pass gates411,412,413and414passes the corresponding input signal d3, d2, d1or d0. The selection signals pairs s0_clk/s0_clkz, s1_clk/s1_clkz, s2_clk/s2_clkz and s3_clk/s3_clkz are controlled to open only one of the pass gates411,412,413and414. The selected input signal supplies the input of master flip-flop section430.

Input section410further includes a testz input driving the gates of dual MOS transistor driver415. A signal upon the testz input forces master flip-flop section420into a predetermined state regardless of other inputs. This testz input enables test of multiplexer/flip-flop400.

Input section410further includes pass gate416receiving scan input signal si. Pass gate417receives test signal testz. Inverter418receives test active signal tc and generates its inverse. Pass gates416and417are driven by opposite polarities of test active signal tc. Depending on the signal level of test active signal tc only one of pass gates416or417is conducting. The output of pass gates416and417drive the input to inverter419. The output of inverter419drives the input of pass gate420. Pass gate420is controlled by the signal pair se_clk/se_clkz. Depending on the signal level of test active signal tc, one of initialization signal si or test signal testz is supplied to master flip-flop section430.

Master flip-flop section430is similar to master flip-flop section120and will not be described in detail.

Slave flip-flop section440is similar to slave flip-flop section130and will not be described in detail.

Per bit control section450operates in conjunction with shared control section460. Shared control section460receives clock signal clk, scan enable signal se and selection signals s0, s1, s2and s3for a set of similarly controlled bit circuits and generates intermediate control signals s0_clkz, s1_clkz, s2_clkz, s3_clkz, se_clkz and fb_clk. Per bit control section350of each bit circuit receives these intermediate signals and generates control signals s0_clk, s1_clk, s2_clk, s3_clk, se_clk and fb_clkz which control operation of two-input multiplexer/flip-flop400.

Shared control section460includes inverters461and462and NAND gates463,464,465,466,467and468. Inverter461receives clock signal clk and generates inverse clock signal clkz. Inverter462receives scan enable signal se and generates inverse scan enable signal sez. NAND gate463receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s0and generates signal s0_clkz. NAND gate464receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s1and generates signal s1_clkz. NAND gate465receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s0and generates signal s0_clkz. NAND gate466receives inverted clock signal clkz, inverted scan enable signal sez and selection signal s3and generates signal s3_clkz. NAND gate467receives inputs scan enable signal se and inverted clock signal clkz and generates signal se_clks. NAND gate468receives inverted scan enable signal sez and the inverted clock signal clkz and generates signal fb_clk.

Per bit control section450includes inverters451,452,453,454,455and456. Inverter451receives signal s0_clkz and generates signal s0_clk. Inverter452receives signal s1_clkz and generates signal s1_clk. Inverter453receives signal s2_clkz and generates signal s2_clk. Inverter454receives signal s3_clkz and generates signal s3_clk. Inverter455receives signal se_clkz and generates signal se_clk. Inverter456receives signal fb_clk and generates signal fb_clkz.

Four-input multiplexer/flip-flop200operates generally as follows. Select signals s0, s1, s2and s3determine selection of either input d0, d1, d2or d3. When enabled by scan enable signal se (scan disabled), the selected signal is passed to master flip-flop section4300and then to slave flip-flop section440where it becomes available at output q. Testz places master flip-flop430in a known state. Scan input si when enabled by clks/clksz supplies the input of master flip-flop430.

Four-input multiplexer/flip-flop400has two advantages over prior art four-input multiplexer/flip-flop200. The first advantage is a reduction in the number of pass gate layers in input section410. Control of pass gates411,412,413and414by clocked versions of the enable signals enables use of a single pass gate level (pass gates411,412,413and414) rather than the two pass gate levels (first211,212,213and214and second pass gate216) of prior art four-input multiplexer/flip-flop200. This advantage is described above in conjunction with two-input multiplexer/flip-flop300. Four-input multiplexer/flip-flop400includes another advantage in the second testz input. Four-input multiplexer/flip-flop400provides a second input for the testz signal by muliplexing with scan input signal si. This second input enables testing the original test input.

FIG. 5illustrates a six-input multiplexer/flip-flop500of this invention.FIG. 5illustrates a single bit circuit of what is generally a multi-bit circuit. Six-input multiplexer/flip-flop500includes: input section510including pass gates511,512,513,514,515,516,517,518and522, driver517and inverters520and521; master flip-flop section530is similar to master flip-flop section120; slave flip-flop section540is similar to output section130; per bit control section550including inverters551,552,553,554,555,556,557and558; and shared control section460including inverters561and562and NAND gates563,564,565,566,567,568,560and570. Six-input multiplexer/flip-flop500is very similar to four-input multiplexer/flip-flop400with the addition of two pass gates in input section510, two inverters in per bit control section550and two NAND gates in shared control section560to accommodate two additional inputs. Six-input multiplexer/flip-flop500includes the same advantages over the prior art as previously noted above in conjunction with four-input multiplexer/flip-flop400.

FIG. 6illustrates circuit600connecting plural two-input multiplexer/flip-flop sections611,612,613and614with shared control section660. Each of two-input multiplexer/flip-flop sections611,612,613and614receives a corresponding bit of two multibit signals a<3:0> and b<3:0> and generates a corresponding bit output q<3:0>. Each of two-input multiplexer/flip-flop circuits611,612,613and614and shared control section660receive the clock signal clk. Shared control section660also receives control signals s0and s1and scan enable signal se. Shared control section660generates intermediate signals s0_clkz, s1_clkz and se_clkx which are transmitted to each of the two-input multiplexer/flip-flop sections611,612,613,614,615and616. Two-input multiplexer/flip-flop section611receives scan input signal si. Each two-input multiplexer/flip-flop section611,612and613passes a scan output so to the scan input si of a next two-input multiplexer/flip-flop section612,613and614.

FIG. 7illustrates circuit700connecting plural four-input multiplexer/flip-flop sections711,712,713and714with shared control section760. Each of four-input multiplexer/flip-flop sections711,712,713and714receives a corresponding bit of four multibit signals a<3:0>, b<3:0>. c<3:0> and d<3:0> and generates a corresponding bit output q<3:0>. Each of four-input multiplexer/flip-flop circuits711,712,713and714and shared control section760receive the clock signal clk. Shared control section760also receives control signals s0, s1, s2and s3and an enable signal se. Shared control section760generates intermediate signals s0_clkz, s1_clkz, s2_clkz, s3_clkz and se_clkz which are transmitted to each of the four-input multiplexer/flip-flop sections711,712,713and714. Four-input multiplexer/flip-flop section711receives the scan input signal si. Each four-input multiplexer/flip-flop section711,712and713passes a scan output so to the scan input si of a next two-input multiplexer/flip-flop section712,713and714. Each of the four-input multiplexer/flip-flop sections711,712,713and714receives a test input testz and a test active signal tc.

Table 2 lists a comparison of propertied of the prior art four-input multiplexer/flip-flop200illustrated inFIG. 2with those of four-input multiplexer/flip-flop400illustrated inFIG. 4.

TABLE 2Prior Art 200Invention 400clk2q129.8629.85clk2q027.3527.90setup187.8254.71setup0109.2065.59hold030.7324.04hold131.6531.84BHT136.0695.44Vx/V1100%69%Fscaling100%143%Average Leakage−9.20E−06−1.35E−05Vx/V1100%147%Average clock non-−1.28E−14−1.40E 14toggling powerVx/V1100%109%
In Table 2: clk2q1 and clk2q0 are the times from the rising edge of the clock signal clk until corresponding data d1or d0arrives on the q output of the circuit; setup0 and setup1 are the length of the interval before the rising clock edge of the clk signal the respective data inputs d0and d1must be present to be sensed; hold0 and hold1 are the respective hold times for inputs d0and d1; BHT is the so-called black hole time which it the sum of the setup time and the clock to q time. The Vx/V1 rows are percentage comparisons with the prior art set to 100%. The Fscaling row shows the percentage improvement in BHT of this invention.