Method for producing substrate for mounting device and method for producing a semiconductor module

Methods for producing a substrate for mounting a device and for producing a semiconductor module are provided. The methods comprise preparing a metal plate on one major surface of which a plurality of projected electrodes are provided. An insulating resin layer is formed on the major surface so as to cover the top surface of the projected electrodes. The top surface of at least one of the plurality of projected electrodes is exposed by removing the insulating resin layer so that a major surface of the insulating resin layer opposite to the metal plate is level. A plurality of counter electrodes is arranged having a counterface to face the top face of the plurality of projected electrodes or a semiconductor device having a plurality of device electrodes is arranged to face the top face of the plurality of projected electrodes. The at least one of the plurality of projected electrodes, the top surface of which is exposed, is electrically connected with at least one of the plurality of counter electrodes facing the projected electrodes, by pressure-bonding the metal plate with the counter electrode. A wiring layer is formed by selectively removing the metal plate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a substrate for mounting a device and a method for producing the same, a semiconductor module and a method for producing the same, and a portable apparatus provided with the same.

2. Description of the Related Art

Amid the acceleration of high performance of portable electronic apparatuses such as portable phone, PDA, DVC, and DSC, in order to be accepted in the market, it is essential that such products are miniaturized and reduced in their weight. Hence, there is also a demand for miniaturization of semiconductor modules such as multi-chip module (MCM) or the like used in these electronic apparatuses. With respect to the demand, a semiconductor device is known in which an active device such as a semiconductor chip, and a passive device such as a capacitor, are covered by an insulating layer formed on a substrate, and the active device and the passive device are connected to a wiring on the insulating layer via the insulating layer. In recent years, with miniaturization and high performance of electronic apparatuses, there is a demand for further miniaturization of semiconductor devices used in the electronic apparatuses. With miniaturization of semiconductor devices, it is essential to narrow a pitch between electrodes for being implemented on a printed wiring board. As a surface-mounting method of a semiconductor device, a flip-chip mounting method is known in which a solder bump is formed on an electrode of the semiconductor device, and the solder bump and an electrode pad of a printed wiring board are soldered. However, in the flip-chip mounting method, there are limitations in narrowing the pitch between electrodes, because of restrictions resulting from the size of the solder bump itself and occurrence of bridges while soldering, or the like. As a structure for overcoming these restrictions, a structure is known in which a projected structure formed on a substrate is used as an electrode or a via, and a semiconductor device is mounted on the substrate via an insulating resin such as an epoxy resin, such that an electrode of the semiconductor device is connected to the projected structure.

However, in the conventional semiconductor devices, there are problems that miniaturization of a semiconductor module is suppressed and the number of the production processes is increased, because a passive device such as a capacitor or the like is mounted on a silicon substrate as a separate part. Further, in the structure in which a wiring layer of a substrate for mounting a device and a semiconductor device are made into one body via an insulating resin, such that a projected structure provided on the wiring layer and an electrode of the semiconductor device are connected, adhesion between the insulating resin and the semiconductor device is not high. Therefore, there is a fear that the insulating resin could peel from the semiconductor device by a thermal stress generated due to, for example, a change in temperature of the environment. In particular, in the case where an interval between the projected structures penetrating the insulating resin is large, as is in the conventional structure stated above, the insulating resin is easy to peel from the semiconductor device between the projected structures. And, in the case where the insulating resin peels from the semiconductor device, adhesion between the projected structure and the semiconductor device is decreased; and as a result, there is a fear that the connection reliability between the projected structure and the semiconductor device is decreased.

SUMMARY OF THE INVENTION

The present invention has been made in view of these situations, and a general purpose of the invention is to provide a technique in which further miniaturization of a semiconductor module can be achieved as well as reduction in the number of the production processes. Another purpose of the invention is to provide a technique in which the connection reliability between a projected structure and an electrode of a semiconductor device can be improved in the structure in which the two are connected to each other.

In order to solve the above-mentioned problems, an embodiment of the present invention is a substrate for mounting a device. The substrate for mounting a device comprises: an insulating resin layer; a wiring layer provided on one major surface of the insulating resin layer; a projected electrode that is connected to the wiring layer electrically and that projects toward the insulating resin layer from the wiring layer; and a metal member at least part of which is embedded in the insulating resin layer, wherein an embedded depth of the metal member is shallower than a projected length of the projected electrode.

In order to solve the above-mentioned problems, an embodiment of the present invention is a substrate for mounting a device. The substrate for mounting a device comprises: an insulating resin layer formed by an insulating resin; a wiring layer provided on one major surface of the insulating resin layer; a plurality of projected electrodes that are connected to the wiring layer electrically, and that project toward the insulating resin layer from the wiring layer; and a counter electrode that is provided at a position corresponding to each of the plurality of projected electrodes, on the other major surface of the insulating resin layer, and that has a counterface facing the top face of the projected electrode, wherein, among the plurality of projected electrodes, a projected length of part of the plurality of projected electrodes is smaller than that of the other projected electrodes, and wherein the part of the plurality of projected electrodes and the counter electrodes corresponding thereto are capacitively-coupled, and wherein the other projected electrodes and the counter electrodes corresponding thereto are connected electrically.

Still another embodiment of the present invention is a method for producing a substrate for mounting a device. The method for producing a substrate for mounting a device comprises: preparing a metal plate on which a plurality of projected electrodes are provided so as to project; adjusting, among the plurality of projected electrodes, a projected length of part of the plurality of projected electrodes so as to be smaller than that of the other projected electrodes; connecting the part of projected electrodes and the counter electrodes corresponding thereto in a way that the two are capacitively-coupled, and connecting the other projected electrodes and the counter electrodes corresponding thereto in a way that the two are connected electrically, after the metal plate is arranged on one major surface of the insulating resin layer such that the projected electrodes face the insulating resin layer side, while the other projected electrodes are exposed from the other major surface of the insulating resin layer, and a counter electrode having a counterface that faces the top face of the projected electrode is arranged at a position corresponding to each of the plurality of projected electrodes, on the other major surface the insulating resin layer; and removing selectively the metal plate to form the wiring layer.

Still another embodiment of the present invention is a method for producing a semiconductor module. The method for producing a semiconductor module comprises mounting a semiconductor device on the substrate for mounting a device produced by the method for producing a substrate for mounting a device according to any one of embodiments stated above.

Still another embodiment of the present invention is also a method for producing a semiconductor module. The method for producing a semiconductor module comprises: preparing a metal plate on which a plurality of projected electrodes are provided so as to project; adjusting, among the plurality of projected electrodes, a projected length of part of the plurality of projected electrodes so as to be smaller than that of the other projected electrodes; connecting the part of the projected electrodes and device electrodes corresponding thereto in a way that the two are capatively-coupled, and connecting the other projected electrodes and the device electrodes corresponding thereto in a way that the two are connected electrically, after the metal plate is arranged on one major surface of the insulating layer such that the projected electrodes face the insulating resin layer side, while the other projected electrodes are exposed from the other major surface of the insulating resin layer, and a semiconductor device provided with the device electrode corresponding to the projected electrode is arranged on the other major surface of the insulating resin layer; and removing selectively the metal plate to form the wiring layer.

In order to solve the above-mentioned problems, an embodiment of the present invention is a substrate for mounting a device. The substrate for mounting a device comprises: an insulating resin layer; a wiring layer provided on one major surface of the insulating resin layer; a projected electrode that is connected to the wiring layer electrically and projects toward the insulating resin layer from the wiring layer; and a backing member at least part of which is embedded in the insulating resin layer, and that is used for backing up the insulating resin layer.

Other embodiment of the present invention is a semiconductor module. The semiconductor module comprises: the substrate for mounting a device according to any one of embodiments stated above; and a semiconductor device provided with a device electrode facing the projected electrode, wherein the projected electrode penetrates the insulating resin layer to be connected to the device electrode electrically.

Still another embodiment of the present invention is a portable apparatus. On the portable apparatus, the semiconductor module according to any one of embodiments stated above is mounted.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, the present invention will now be described based on the preferred embodiments with reference to accompanying drawings. The same or like components, members, or processes illustrated in each drawing are denoted by the same reference numerals, and the duplicative descriptions will be appropriately omitted. The embodiments are not intended to limit the invention but to serve as particular examples thereof, and all features or combinations thereof described there are not always essential to the present invention.

FIG. 1is a schematic cross-sectional diagram illustrating a structure of a substrate10for mounting a device and a semiconductor module30using the same according to Embodiment 1. The semiconductor module30comprises the substrate10for mounting a device and a semiconductor device50mounted thereon.

The substrate10for mounting a device comprises: an insulating resin layer12formed by an insulating resin; a wiring layer14provided on one major surface S1of the insulating resin layer12; and a plurality of projected electrodes16that are connected to the wiring layer electrically, and that project toward the insulating resin layer12from the wiring layer14. The substrate10for mounting a device is provided with a counter electrode18that is provided at a position corresponding to each of the plurality of projected electrodes16on the other major surface S2of the insulating resin layer12, and that has a counterface181facing the top face161of the projected electrode16.

The insulating resin layer12is made of an insulating resin and formed with a material that induces a plastic flow when, for example, pressurized. An example of a material that induces a plastic flow when pressurized includes an epoxy-based thermosetting resin. As an epoxy-based thermosetting resin used for the insulating resin layer12, a material may be used as far as the material has a viscosity property of, for example, 1 kPa·s under the condition of a temperature of 160° C. and a pressure of 8 Mpa. When pressurized with a pressure of, for example, 5 to 15 Mpa under the condition of a temperature of 160° C., the epoxy-based thermosetting resin reduces its viscosity to ⅛th-fold in comparison to that when not pressurized. On the other hand, the epoxy resin in the B-stage before thermosetting is less viscous in the same level as that when not pressurized, and not viscous even when pressurized, under the condition of the glass transition temperature Tg or less. The epoxy-based thermosetting resin is a dielectric material with a dielectric constant of about 3 to 4.

The wiring layer14is provided on one major surface S1of the insulating resin layer12, and is formed with a conductive material, preferably a rolled metal, further preferably a rolled copper. A plurality of projected electrodes16are provided so as to project on the surface of the wiring layer14on the side of the insulating resin layer12. In the present embodiment, the wiring layer14and the projected electrodes16are formed into one body, but they are not particularly limited thereto. On the major surface of the wiring layer14opposite to the insulating resin layer12, solder bumps15are formed at certain positions. The positions where the solder bumps15are formed are ones where the wiring is put around, for example, in rewiring.

The projected electrode16has, for example, a rounded shape when seen in planar view, and has a side face formed such that the diameter thereof becomes progressively smaller toward the top of the electrode. The shape of the projected electrode16is not particularly limited to, and, for example, a cylindrical shape having a certain diameter is also possible. A polygonal shape such as a quadrangle when seen in planar view is also possible. Herein, among the plurality of projected electrodes16, a projected length (height or embedded depth) of part of the projected electrodes16a(metal material) from the wiring layer14is smaller (shallower) than that of the other projected electrodes16bfrom the wiring layer14.

That is, in the present embodiment, the projected electrode16bis composed of a metal layer162covering the top face161of the projected electrode16band the portion projecting from the wiring layer14; hence, the projected length of the projected electrode16ais smaller than that of the projected electrode16b. The metal layer162is a metal plated layer formed by an electrolytic plating process using a metal, for example, gold (Au), or by a non-electrolytic plating process; or a conductive paste layer formed by using a conductive paste. In the present embodiment, the metal layer162is structured by a Ni/Au plated layer that is made of gold (Au) and nickel (Ni). Alternatively, the projected length of the projected electrodes16acan also be made smaller than that of the other projected electrodes16bby removing the top portions of the part of the projected electrodes16aby etching, etc.

The counter electrode18is made of a metal such as copper (Cu) and aluminum (Al). The counter electrodes18are provided at the positions corresponding to each of the plurality of projected electrodes16on the other major surface S2of the insulating resin layer12. Because the projected length of the projected electrode16ais smaller than that of the projected electrode16b, the insulating resin layer12lies between the projected electrode16aand the counter electrode18acorresponding thereto. Therefore, the projected electrode16aand the counter electrode18aare capacitively-coupled to constitute a capacitor. On the other hand, the projected electrode16bhaving the projected length larger than that of the projected electrode16a, and the counter electrode18bcorresponding thereto are in contact with each other to be connected electrically (ohmic contact). In the present embodiment, a metal layer182made of Ni/Au is provided on a counterface181of the counter electrode18. Due to this, the projected electrode16band the counter electrode18bare connected by an Au—Au contact, allowing the connection reliability between the projected electrode16band the counter electrode18bto be improved.

In the present embodiment, the counter electrode18is a device electrode52of the semiconductor device50. The device electrodes52aand52bcorresponding to each of the projected electrodes16aand16bare provided on the semiconductor device50. A protecting layer54is stacked on the major surface of the semiconductor device50on the side where the device50is in contact with the insulating resin layer12, such that the device electrode52is opened. Specific example of the semiconductor device50includes a semiconductor chip such as an integrated circuit (IC) and a large-scale IC (LSI) or the like. Specific example of the protecting layer54includes a polyimide layer. The present embodiment illustrates an example in which the counter electrode18is the device electrode52of the semiconductor device50, but the semiconductor device50may also be implemented at any position of the substrate10for mounting a device by any process such as wire bonding.

In the present embodiment, the insulating resin layer12is provided between the substrate10for mounting a device and the semiconductor device50, and the substrate10for mounting a device is pressure-bonded to one major surface S1of the insulating resin layer12, and the semiconductor device50is pressure-bonded to the other major surface thereof. The projected electrode16bpenetrates the insulating resin layer12to be connected electrically to the counter electrode18b, that is, the device electrode52bprovided in the semiconductor device50. Because the insulating resin layer12is made of a material that induces a plastic flow when pressurized, it can be prevented that a residual layer of the insulating resin layer12lies between the projected electrode16band the device electrode52b, in the state where the substrate10for mounting a device, the insulating resin layer12, and the semiconductor device50are formed into one body in this order; hence the connection reliability can be improved.

(Method for Producing Substrate for Mounting Device and Semiconductor Module)

FIGS. 2A to 2Dare cross-sectional diagrams illustrating a method for forming the projected electrode16.

As illustrated inFIG. 2A, a copper plate13having a thickness larger than at least a total of the height of the projected electrode16and the thickness of the wiring layer14, is prepared.

As illustrated inFIG. 2B, resists70are subsequently formed selectively in accordance with the pattern of the projected electrodes16by a lithography process.

As illustrated inFIG. 2C, a certain pattern of the projected electrodes16is then formed on the copper plate13by using the resist70as a mask.

As illustrated inFIG. 2D, the resist70is subsequently removed. By the process stated above, the projected electrodes16are formed.

In the projected electrode16of the present embodiment, the diameter in the base portion, the diameter in the tip portion, and the height thereof are, for example, 100 μmφ, 50 μmφ, and 40 μm, respectively.

FIGS. 3A to 3DandFIGS. 4A to 4Care cross-sectional diagrams illustrating a method for connecting the projected electrode16and the counter electrode18or the device electrode52.

As illustrated inFIG. 3A, a resist71is stacked on the major surface of the copper plate13on the side where a plurality of projected electrodes16are formed, by a lithography process, and opening portions71aare provided at positions corresponding to the certain projected electrodes16.

As illustrated inFIG. 3B, the metal layers162are formed on top faces161of the projected electrodes16exposed at the opening portions71a. The metal layers162are formed as metal layers made of Ni/Au by, for example, an electrolytic plating process or a non-electrolytic plating process. With this, the projected length of the projected electrode16afrom the copper plate13, the metal layer162not being formed on the projected electrode16a, is made smaller than that of the projected electrode16bincluding the metal layer162from the copper plate13. The metal layer162is formed such that the Ni layer is in contact with the projected electrode16and the Au layer in contact with the counter electrode18. A method for forming the metal layer162is not particularly limited thereto, but may also be formed by using a conductive paste such as an Au paste. The thickness of the metal layer162is, for example, about 1.25 to 3.25 μm, 0.25 μm of which being the thickness of the Au layer and 1 to 3 μm of which being the thickness of the Ni layer.

As illustrated inFIG. 3C, the resist71is subsequently removed. The copper plate13is then arranged on one major surface S1of the insulating resin layer12such that the projected electrodes16face the insulating resin layer12side. The counter electrode18having a counterface181that faces the top face161of the projected electrode16, is arranged at a position corresponding to each of the projected electrodes16on the other major surface S2of the insulating resin layer12. The thickness of the insulating resin layer12is about the height of the projected electrode16b, that is, about 23 μm. On the counterface181of the counter electrode18, the Ni/Au metal layer182is formed in the same way as with the projected electrode16b.

As illustrated inFIG. 3D, the projected electrode16bis then exposed from the other major surface S2of the insulating resin layer12such that the projected electrode16aand the counter electrode18acorresponding thereto are capacitively-coupled, and the projected electrode16band the counter electrode18bcorresponding thereto are connected electrically. Because the projected length of the projected electrode16ais smaller than that of the projected electrode16bby the thickness of the metal layer162, the insulating resin layer12with a thickness similar to that of the metal layer162, lies between the projected electrode16aand the counter electrode18a, in the state where the projected electrode16bis engaged with the counter electrode18b. Due to this, the projected electrode16aand the counter electrode18aare capacitively-coupled to form a capacitor as a passive device. The capacitor can be changed in its capacity arbitrarily by adjusting the material of the insulating resin layer12, and the thickness of the insulating resin layer12lying between the projected electrode16aand the counter electrode18a, that is, the thickness of the metal layer162. On the top face161of the projected electrode16band on the counterface181of the counter electrode18b, the Ni/Au metal layer162and the metal layer182are formed, respectively; and the projected electrode16band the counter electrode18bare connected electrically by an Au—Au contact. Therefore, the connection reliability between the projected electrode16band the counter electrode18bcan be improved. It is also possible that the projected electrode16band the counter electrode18bare not provided with metal layers. In the case, the projected length of the part of the projected electrodes16acan be made smaller than that of the other projected electrodes16b, by removing part of the top portions of the projected electrodes16awith etching. In the case, a capacity of the capacitor can be changed arbitrarily by adjusting an amount of the part of the top portions to be removed of the projected electrode16a.

In the present embodiment, the semiconductor device50in which the device electrode52corresponding to the projected electrode16is provided, is arranged on the other major surface S2of the insulating resin layer12. In the case, the device electrode52corresponds to the counter electrode18. The copper plate13, the insulating resin layer12, and the semiconductor device50are formed into one body by pressure-bonding the copper plate13and the semiconductor device50by using a press machine via the insulating resin layer12. With this, the projected electrode16aand the device electrode52aare capacitively-coupled, and the projected electrode16band the device electrode52bare connected electrically. The pressure and temperature in the press working are about 5 Mpa and 200° C., respectively. With the press working, the insulating resin layer12induces a plastic flow so that the projected electrode16penetrates the insulating resin layer12. Then, the metal layer162of the projected electrode16band that 522 of the device electrode52bare pressure-bonded such that the projected electrode16band the device electrode52bare connected electrically. Because the projected electrode16has a shape in which the whole shape of the electrode becomes progressively thinner toward the tip thereof, the projected electrode16smoothly penetrates the insulating resin layer12.

As illustrated inFIG. 4A, resists72are subsequently formed selectively in accordance with the pattern of the wiring layer14by a lithography process. Specifically, resist72are formed selectively on the copper plate13in the following process: a resist film with a certain thickness is attached to the copper plate13by using a laminating apparatus, and exposed by using a photomask with the pattern of the wiring layer14; and the resist film is then developed with the use of an Na2CO3solution, and the resists in unexposed regions are removed. In order to improve the adhesion property with the resist, it is preferable that the surface of the copper plate13is subjected to a pretreatment such as grinding and washing or the like, before laminating the resist film, if needed. Alternatively, the copper plate13may also be adjusted so as to have a thickness similar to that of the wiring layer14by etching the whole face of the copper plate13opposite to the surface where the projected electrodes16are formed, before laminating the resist72, if needed.

As illustrated inFIG. 4B, the wiring layer14with a certain wiring pattern is then formed by etching the copper plate13with the use of a ferric chloride solution by using the resists72as masks. Thereafter, the resist is peeled off by using a parting agent such as NaOH solution. In the present embodiment, the thickness of the wiring layer14is about 15 μm.

As illustrated inFIG. 4C, solder bumps15are formed at certain positions of the wiring layer14. The positions where the solder bumps are formed are ones where the wiring is put around, for example, in rewiring.

The substrate10for mounting a device is formed by the production process described above. Or, when the semiconductor device50is pressure-bonded via the insulating resin layer12, and the counter electrode18is used as the device electrode52, the semiconductor module30is obtained.

In the present embodiment as stated above, among a plurality of projected electrodes16provided on the wiring layer14, part of the projected electrodes16aare capacitively-coupled with the counter electrodes18aor the device electrodes52a; and the other projected electrodes16bare connected to the counter electrodes18bor the device electrodes52belectrically. Therefore, it is not necessary to mount a capacitor, a passive device, on the substrate10for mounting a device as a separate part; hence, the semiconductor module30can be miniaturized. In addition, the projected electrode16aand the counter electrode18aor the device electrode52aare capacitively-coupled to form a capacitor at a same time when the projected electrode16bprovided on the wiring layer14so as to project, and the counter electrode18bor the device electrode52are connected electrically to form a rewiring. Therefore, the number of the production processes can be reduced in comparison to the case where a capacitor is mounted on the substrate10for mounting a device as a separate part; hence, the production processes can be simplified and the production cost can be reduced. Moreover, because a capacitor is formed by capacitively-coupling the projected electrode16athat is to be inserted into the insulating resin layer12, and the counter electrode18aor the device electrode52a, an interval between the electrodes can be small; hence, a capacity of the capacitor can be large. In addition, the capacitor can be changed in its capacity arbitrarily by adjusting the material of the insulating resin layer12, and the thickness of the insulating resin layer12lying between the projected electrode16aand the counter electrode18a.

In the above Embodiment 1, the substrate10for mounting a device or the semiconductor module30is formed by subjecting the copper plate13and the counter electrode18or the semiconductor device50to pressure molding with the insulating resin layer12sandwiched between the two such that they are formed into one body; however, the substrate10for mounting a device or the semiconductor module30may also be formed in the following process. Hereinafter, the present embodiment will be described. It is noted that the projected electrode16is formed in the same way as with Embodiment 1, and the same structure as in Embodiment 1 is denoted with the same reference numeral as in Embodiment 1, and the description with respect thereto is omitted.

FIGS. 5A to 5FandFIGS. 6A to 6Care cross-sectional diagrams illustrating a method for connecting the projected electrode16and the counter electrode18or the device electrode52.

As illustrated inFIG. 5A, a resist71is stacked on the major surface of the copper plate13on the side where a plurality of projected electrodes16are formed, by a lithography process, and opening portions71aare provided at positions corresponding to certain projected electrodes16.

As illustrated inFIG. 5B, metal layers162are then formed on the top faces161of the projected electrodes16exposed from the opening portions71a. Due to this, a projected length of the projected electrode16afrom the copper plate13, the metal layer162being not formed on the top face of the electrode16a, is made smaller than that of the projected electrodes16bincluding the metal layers162, from the copper plate13.

As illustrated inFIG. 50, the resist71is subsequently removed, and the copper plate13is arranged on one major surface S1of the insulating resin layer12such that the insulating resin layer12is pressure-bonded to the major surface of the copper plate13where the projected electrodes16are formed.

As illustrated inFIG. 5D, the other major surface S2of the insulating resin layer12opposite to the surface to which the copper plate13is pressure-bonded, is etched to expose the metal layers162of the projected electrodes16b.

As illustrated inFIG. 5E, the semiconductor device50is then arranged on the other major surface S2of the insulating resin layer12; and the copper plate13, the insulating resin layer12, and the semiconductor device50are formed into one body by pressure-bonding the copper plate13pressure-bonded to the insulating resin layer12, and the semiconductor device50, as illustrated inFIG. 5F. Due to this, the projected electrode16aand the device electrode52aare capacitively-coupled, and the projected electrode16band the device electrode52bare connected electrically.

As illustrated inFIG. 6A, resists72are then formed selectively in accordance with the pattern of the wiring layer14, by a lithography process.

As illustrated inFIG. 6B, a certain pattern of the wiring layer14is then formed by etching the copper plate13with the use of the resists72as masks, followed by removal of the resists72.

As illustrated inFIG. 6C, solder bumps are formed at certain positions of the wiring layer14.

The semiconductor module30is formed by the production process described above. Also, a counter electrode18may be used instead of the device electrode50, and in the case, the substrate10for mounting a device is obtained by the above process.

According to the present embodiment, the following advantages can be further obtained in addition to the above advantages of Embodiment 1. That is, in the present embodiment, the counter electrode18or the device electrode50is pressure-bonded to the insulating resin layer12after the metal layer162is exposed; hence, the projected electrode16and the counter electrode18or the device electrode52can be positioned accurately, allowing the connection reliability between the projected electrode16band the counter electrode18bor the device electrode52bto be improved. With this, the reliability of the substrate10for mounting a device or the semiconductor module30can be improved.

In the structures of the above Embodiments 1 and 2, the insulating resin layer12lies between the projected electrode16aand the counter electrode18aor the device electrode52a; however, a dielectric film layer having a dielectric constant larger than that of the insulating resin layer12may be provided between the projected electrode16aand the counter electrode18aor the device electrode52a, as illustrated in the present embodiment. Hereinafter, the present embodiment will be described. It is noted that the projected electrode16is formed in the same way as with Embodiment 1, and the same structure as in Embodiments 1 and 2 is denoted with the same reference numeral as in Embodiments 1 and 2, and the description with respect thereto is omitted.

FIGS. 7A to 7GandFIGS. 8A to 8Eare cross-sectional diagrams illustrating a method for connecting the projected electrode18and the counter electrode18or the device electrode52.

As illustrated inFIG. 7A, a dielectric film20is formed on the whole major surface of the copper plate13on the side where a plurality of projected electrodes16are formed. The dielectric film20is formed as, for example, a silicon nitride (SiN) film by a plasma CVD process or the like. The SiN film has a dielectric constant of about 7.

As illustrated inFIG. 7B, a resist73is then stacked on a position corresponding to the certain projected electrode16on the dielectric film20, by a lithography process.

As illustrated inFIG. 7C, the dielectric film20is etched with the use of the resist73as a mask to form a dielectric film layer22on the top face161of the certain projected electrode16.

As illustrated inFIG. 7D, a resist71is then stacked on the major surface of the copper plate13on the side where the plurality of projected electrodes16are formed, by a lithography process. Subsequently, opening portions71aare provided at positions corresponding to the projected electrodes16on which the dielectric film layers22are not formed.

As illustrated inFIG. 7E, metal layers162are then formed on the top faces161of the projected electrodes16exposed at the opening portions71a. With this, a projected length of the projected electrode16afrom the copper plate13, the metal layer162being not formed on the projected electrode16a, is made smaller than that of the projected electrode16bincluding the metal layer162from the copper plate13.

As illustrated inFIG. 7F, after the resist71is removed, the copper plate13is arranged on one major surface S1of the insulating resin layer12, and the insulating resin layer12is pressure-bonded to the major surface of the copper plate13on the side where the projected electrodes16are formed.

As illustrated inFIG. 7G, the other major surface S2of the insulating resin layer12opposite to the major surface pressure-bonded to the copper plate13, is etched such that the dielectric film layer22and the metal layer162are exposed.

As illustrated inFIG. 8A, the semiconductor device50is arranged on the other major surface S2of the insulating resin layer12; and the copper plate13pressure-bonded to the insulating resin layer12, and the semiconductor device50are pressure-bonded to form the copper plate13, the insulating resin layer12, and the semiconductor device50into one body, as illustrated inFIG. 8B. With this, the projected electrode16aand the device electrode52aare capacitively-coupled via the dielectric film layer22, and the projected electrode16band the device electrode52bare connected electrically.

As illustrated inFIG. 8C, resists72are then formed selectively in accordance with the pattern of the wiring layer14, by a lithography process.

As illustrated inFIG. 8D, the wiring layer14with a certain wiring pattern is subsequently formed by etching the copper plate13with the use of the resists72as masks, followed by removal of the resists72.

As illustrated inFIG. 8E, solder bumps are formed at certain positions of the wiring layer14.

The semiconductor module30is formed by the production process described above. Also, the facing device18may be used instead of the device electrode50, and in the case, the substrate10for mounting a device is obtained by the above process. In the present embodiment, the semiconductor device50is pressure-bonded after the insulating resin layer12is pressure-bonded to the copper plate13in the same way as with Embodiment 2; however, the copper plate13and the semiconductor device50may be pressure-bonded at an almost same time in the same way as with Embodiment 1, without being particularly limited thereto.

According to the present embodiment, the following advantages can be further obtained in addition to the above advantages of Embodiments 1 and 2. That is, in the present embodiment, the dielectric film layer22with a dielectric constant larger than that of the insulating resin layer12is provided between the projected electrode16aand the counter electrode18aor the device electrode52a. And, the projected electrode16aand the counter electrode18aor the device electrode18aare capacitively-coupled via the dielectric film layer22. Due to this, a capacity of the capacitor formed by the projected electrode16aand the counter electrode18aor the device electrode52acan be further increased.

In the present embodiment, an example of a structure is described in which the counter electrode18is part of other wiring layer provided on the other major surface S2of the insulating resin layer12. Hereinafter, the present embodiment will be described. It is noted that the projected electrode16is formed in the same way as with Embodiment 1, and the same structure as in Embodiments 1 to 3 is denoted with the same reference numeral as in Embodiments 1 to 3, and the description with respect thereto is omitted.

FIGS. 9A to 9G,FIGS. 10A to 10D, andFIGS. 11A and 11Bare cross-sectional diagrams illustrating a method for connecting the projected electrode16and the counter electrode18.

As illustrated inFIG. 9A, a resist71is stacked on the major surface of the copper plate13on the side where a plurality of projected electrodes16are formed, by a lithography process, and an opening portion71bis provided at a position corresponding to a certain projected electrode16.

As illustrated inFIG. 9B, part of the projected electrode16exposed at the opening portion71bis removed by etching the top portion thereof with the use of the resist71as a mask. Due to this, a projected length of the projected electrode16apart of which is removed, from the copper plate13is made smaller than that of the other projected electrodes16b, from the copper plate13, followed by removal of the resist71.

As illustrated inFIG. 9C, the copperplate13is then arranged on one major surface S1side of the insulating resin layer12to pressure-bond the insulating resin layer12to the major surface of the copper plate13on the side where the projected electrodes16are formed.

As illustrated inFIG. 9D, the top faces161of the projected electrodes16bare exposed by etching the other major surface S2of the insulating resin layer12opposite to the major surface pressure-bonded to the copper plate13.

As illustrated inFIG. 9E, the copper plate23is subsequently stacked on the other major surface S2of the insulating resin layer12. The copper plate23is stacked by, for example, an electrolytic plating process or a non-electrolytic plating process. The thickness of the copper plate23is almost the same as that of the wiring layer24.

As illustrated inFIG. 9F, resists74are formed selectively in accordance with the pattern of the wiring layer24, which is the other wiring layer, on the major surface of the copper plate23opposite to the insulating resin layer12.

As illustrated inFIG. 9G, the wiring layer24with a certain wiring pattern is formed by etching the copper plate23with the use of the resists74as masks, followed by removal of the resists74.

As illustrated inFIG. 10A, a resist75is then stacked on the major surface of the wiring layer24opposite to the insulating layer12by a lithography process, and opening portions75aare provided at certain positions corresponding to the wiring layer24.

As illustrated inFIG. 10B, electrodes26are formed within the opening portions75a. The electrodes26are formed by, for example, an electrolytic plating process or a non-electrolytic plating process. Thereafter, metal layers262are formed on the top faces261of the electrodes26, followed by removal of the resist75.

As illustrated inFIG. 100, the semiconductor device50is arranged on one major surface of the insulating resin layer28made of the same material as with the insulating resin layer12, and the copper plate13is arranged on the other major surface of the insulating resin layer28such that the electrodes26face the insulating resin layer28side. Then, as illustrated inFIG. 10D, the copper plate13, the insulating resin layer28, and the semiconductor device50are formed into one body by press-bonding the copper plate13and the semiconductor device50via the insulating resin layer28.

As illustrated inFIG. 11A, resists72are formed selectively in accordance with the pattern of the wiring layer14by a lithography process.

As illustrated inFIG. 11B, the wiring layer14with a certain wiring pattern is subsequently formed by etching the copper plate13with the use of the resists72as masks. The resists72are removed and solder bumps15are formed at certain positions of the wiring layer14.

The semiconductor module30is formed by the production process described above. Or, when the semiconductor device50is not pressure-bonded, the substrate10for mounting a device is obtained.

In the present embodiment, capacitive coupling is formed between the projected electrode16aprovided on the wiring layer14and the wiring layer24provided on the other major surface S2of the insulating resin layer12. That is, the counter electrode18is part of the wiring layer24provided on the other major surface S2of the insulating resin layer12.

According to the present embodiment, the following advantages can be further obtained in addition to the above advantages of Embodiment 1. That is, as illustrated in the present embodiment, a capacitor can be formed between the projected electrode16aand the wiring layer24; hence, the substrate10for mounting a device having a multi-layer structure in which a capacitor is formed into one body, and the semiconductor module30using the same can be formed.

In the present embodiment, an example of a structure is described in which the counter electrode18is part of the other wiring layer provided on the other major surface S2of the insulating resin layer12, which is different from Embodiment 4 in the production process. Hereinafter, the present embodiment will be described. It is noted that the projected electrode16is formed in the same way as with Embodiment 1, and the same structure as in Embodiments 1 to 4 is denoted with the same reference numeral as in Embodiments 1 to 4, and the description with respect thereto is omitted.

FIGS. 12A to 12F,FIGS. 13A to 13E, andFIGS. 14A to 14Care cross-sectional diagrams illustrating a method for connecting the projected electrode16and the counter electrode18.

As illustrated inFIG. 12A, a resist71is stacked on the major surface of the copper plate13on the side where a plurality of projected electrodes16are formed, by a lithography process, and an opening portion71bis provided at a position corresponding to a certain projected electrode16.

As illustrated inFIG. 12B, part of the projected electrode16exposed at the opening portion71bis removed by etching the top portion thereof with the use of the resist71as a mask. Due to this, a projected length of the projected electrode16apart of which is removed, from the copper plate13is made smaller than that of the other projected electrodes16b, from the copper plate13, followed by removal of the resist71.

As illustrated inFIG. 12C, the copper plate13is then arranged on one major surface S1side of the insulating resin layer12to pressure-bond the insulating resin layer12to the major surface of the copperplate13on the side where the projected electrodes16are formed.

As illustrated inFIG. 12D, the top faces161of the projected electrodes16bare exposed by etching the other major surface S2of the insulating resin layer12opposite to the major surface pressure-bonded to the copper plate13.

As illustrated inFIG. 12E, the copper plate25is subsequently stacked on the other major surface S2of the insulating resin layer12. The copper plate25is stacked by, for example, an electrolytic plating process or a non-electrolytic plating process. The thickness of the copper plate25is larger than at least the total of the thickness of the electrode27and the thickness of the wiring layer24, the two being described later.

As illustrated inFIG. 12F, resists76are formed selectively in accordance with the pattern of the electrode27by a lithography process.

As illustrated inFIG. 13A, the electrode27with a certain pattern is formed on the copper plate25with the use of the resists76as masks.

As illustrated inFIG. 13B, resists77are then formed selectively on the major surface of the copper plate25on the side opposite to the insulating resin layer12, in accordance with the pattern of the wiring layer24that is the other wiring layer.

As illustrated inFIG. 13C, the wiring layer24with a certain wiring pattern is formed by etching the copper plate25with the use of the resists77as masks, followed by removal of the resists77.

As illustrated inFIG. 13D, a resist78is then stacked on the major surface of the wiring layer24opposite to the insulating layer12by a lithography process, and opening portions78aare provided at certain positions corresponding to the projected electrodes27.

As illustrated inFIG. 13E, metal layers272are formed on the top faces of the electrodes27exposed at the opening portions78a, followed by removal of the resist78.

As illustrated inFIG. 14A, the semiconductor device50is arranged on one major surface of the insulating resin layer28made of the same material as with the insulating resin layer12, and the copper plate13is arranged on the other major surface of the insulating resin layer28such that the electrodes27face the insulating resin layer28side. Then, as illustrated inFIG. 14B, the copper plate13, the insulating resin layer28, and the semiconductor device50are formed into one body by press-bonding the copper plate13and the semiconductor device50via the insulating resin layer28.

As illustrated inFIG. 14C, resists (not illustrated) are formed selectively in accordance with the pattern of the wiring layer14by a lithography process, and the wiring layer14with a certain wiring pattern is formed by etching the copper plate13. The resists are then removed to form solder bumps at certain positions of the wiring layer14.

The semiconductor module30is formed by the production process described above. Or, when the semiconductor device50is not pressure-bonded, the substrate10for mounting a device is obtained.

In the present embodiment, capacitive coupling is formed between the projected electrode16aprovided on the wiring layer14and the wiring layer24provided on the other major surface S2of the insulating resin layer12. That is, the counter electrode18is part of the wiring layer provided on the other major surface S2of the insulating resin layer12.

As stated above, the substrate10for mounting a device having a multi-layer structure in which a capacitor is formed into one body, and the semiconductor module30using the same can also be formed by the method illustrated in the present embodiment.

The resent embodiment is different from Embodiments 1 to 5 in a method for forming the projected electrode16. Hereinafter, the present embodiment will be described. It is noted that a method for connecting the projected electrode16and the counter electrode18is the same as with Embodiments 1 to 5, and the same structure as in Embodiments 1 to 5 is denoted with the same reference numeral as in Embodiments 1 to 5, and the description with respect thereto is omitted.

FIGS. 15A to 15Dare cross-sectional diagrams illustrating a method for forming the projected electrode16.

As illustrated inFIG. 15A, a core substrate80comprising an insulating resin layer82made of an insulating resin, a first metal layer84formed on one major surface of the insulating resin layer82, and a second metal layer86formed on the other major surface thereof, is prepared. The first metal layer84and the second metal layer86are made of, for example, copper (Cu) or the like.

As illustrated inFIG. 15B, parts of the first metal layer84and the resin layer82are removed to the extent where the second metal layer86is exposed, by, for example, irradiating a laser beam from the first metal layer84side, such that opening portions85are formed. Herein, for example, a carbon dioxide gas laser can be used for irradiating a laser beam. The opening portions85are formed in accordance with the pattern of the projected electrodes16.

As illustrated inFIG. 15C, a metal plated layer87is formed by plating a metal such as copper (Cu) on the interior face of the opening portions85by an electrolytic plating process or a non-electrolytic plating process or the like. With this, a via conductor88is formed inside the opening portions85, and the first metal layer84and the second metal layer86are conducted through the via conductor88. As the result of the metal plated layer87being laminated on the first metal layer84, the total thickness of the first metal layer84and the metal plated layer87is adjusted so as to be larger or equal to the thickness of the wiring layer.

As illustrated inFIG. 15D, the second metal layer86and part of the resin layer82are then removed by etching. With this, the projected electrodes16are formed on the resin layer82.

As stated above, the substrate10for mounting a device and the semiconductor module30according to the present invention can also be formed by using the projected electrode16formed by the method illustrated in the present embodiment.

FIG. 16is a schematic plan diagram illustrating the semiconductor module1030directed to Embodiment 1.FIG. 17is a schematic cross-sectional diagram taken along line A-A ofFIG. 16, illustrating a structure of the substrate1010for mounting a device and the semiconductor module1030using the same. The semiconductor module1030comprises the substrate1010for mounting a device and the semiconductor device1050mounted on the substrate1010for mounting a device. The substrate1010for mounting a device comprises: an insulating resin layer1012; a wiring layer1014provided on one major surface S1001of the insulating resin layer1012; and a projected electrode1016that is connected to the wiring layer1014electrically and projects toward the insulating resin layer1012from the wiring layer1014. The substrate1010for mounting a device further comprises a backing member1018(metal member) at least part of which is embedded in the insulating resin layer1012, and that is used for backing up the insulating resin layer1012.

The insulating resin layer1012is made of an insulating resin and formed with a material that induces a plastic flow when, for example, pressurized. An example of a material that induces a plastic flow when pressurized includes an epoxy-based thermosetting resin. As an epoxy-based thermosetting resin used for the insulating resin layer1012, a material may be used as far as the material has a viscosity property of, for example, 1 kPa·s under the condition of a temperature of 160° C. and a pressure of 8 Mpa. When pressurized with a pressure of, for example, 5 to 15 Mpa under the condition of a temperature of 160° C., the epoxy-based thermosetting resin reduces its viscosity to ⅛th-fold in comparison to that when not pressurized. On the other hand, the epoxy resin in the B-stage before thermosetting is less viscous in the same level as that when not pressurized, and not viscous even when pressurized, under the condition of the glass transition temperature Tg or less.

The wiring layer1014is provided on one major surface S1001of the insulating resin layer1012, and is formed with a conductive material, preferably a rolled metal, further preferably a rolled copper. Alternatively, the wiring layer1014may be formed with an electrolyte copper or the like. On the wiring layer1014on the side of the insulating resin layer1012, the projected electrodes1016are provided so as to project, in the state of being connected to the wiring layer1014electrically. The wiring layer1014and the projected electrodes1016are preferably formed into one body. With this, occurrence of a crack or the like that is created by a thermal stress in the interfacial surface between the wiring layer1014and the projected electrode1016can be prevented, and the two can be connected more surely in comparison to the case where the two are formed as separate bodies. Further, because the device electrode1052and the wiring layer1014can be connected electrically at a same time when the projected electrode1016and the device electrode1052are pressure-bonded, which is described later, there is an advantage that the number of the production processes is not increased. In an end region of the wiring layer1014on the side opposite to the projected electrode1016, a land region that doubles as a wiring is formed in which a solder bump1022, which is described later, is arranged on the surface opposite to the side where the projected electrode1016is formed.

On the major surface of the wiring layer1014on the side opposite to the insulating resin layer1012, a protecting layer1020for preventing oxidation of the wiring layer1014or the like is provided. An example of the protecting layer1020includes a solder resist layer. An opening portion1020ais formed in a certain region of the protecting layer1020corresponding to the land region of the wiring layer1014such that the land region of the wiring layer1014is exposed at the opening portion1020a. A solder bump1022, as an external connection electrode, is formed inside the opening portion1020asuch that the solder bump1022and the wiring layer1014are connected electrically. The position where the solder bump1022is formed, that is, the region where the opening portion1020ais formed, is an end region where the wiring is put around, for example, in rewiring.

The projected electrode1016has, for example, a rounded shape when seen in planar view, and has a side face formed such that the diameter thereof becomes progressively smaller toward the top of the electrode. The shape of the projected electrode16is not particularly limited to, and, for example, a cylindrical shape having a certain diameter is also possible. A polygonal shape such as a quadrangle when seen in planar view is also possible. The top face of the projected electrode1016is covered with a metal layer1017such as a nickel (Ni)/gold (Au) plated layer formed by an electrolytic plating process or a non-electrolytic plating process. The metal layer1017may also be a conductive paste layer that is formed by using a conductive paste. In the present embodiment, the metal layer1017is formed by a Ni/An plated layer.

The backing member1018comprises: a planar portion1018ahaving an almost cross shape when seen in planar view, which is stacked on one major surface S1001of the insulating resin layer1012; and a plurality of projected portions1018bthat project toward the insulating resin layer1012from the planar portion1018a. The projected portion1018bhas a rounded shape when seen in planar view, and has a top face and a side face formed such that the diameter thereof becomes progressively smaller toward the top thereof; and the top face is embedded in the insulating resin layer1012from the major surface S1001of the insulating resin layer1012, in the state where the top face is parallel to the other major surface of the insulating resin layer1012. The projected portion1018bof the backing member1018enters the insulating resin layer1012to backup the insulating resin layer1012; hence, peeling of the insulating resin layer1012from the semiconductor device1050can be prevented.

It is preferable that the backing member1018is structured such that the top face of the projected portion1018bis positioned inside the insulating resin layer1012, that is, the top face of the projected portion1018bdoes not reach the other major surface of the insulating resin layer1012. In this case, the insulating resin layer1012is to lie between the top face of the projected portion1018bof the backing member1018and the semiconductor device1050. With this, because the insulating resin layer1012_lying between the top face of the projected portion1018band the semiconductor device1050, is sandwiched by the projected portion1018band the semiconductor device1050, peeling of the insulating resin layer1012from the semiconductor device1050can be prevented more effectively. In the present embodiment, a height (embedded depth) of the projected portion1018bis made smaller (shallower) than that of the projected electrode1016including the metal layer1017, by providing the metal layer1017on the top face of the projected electrode1016. Due to this, the insulating resin layer1012with a thickness similar to that of the metal layer1017, lies between the projected portion1018and the semiconductor device1050. Also, the top face of the projected portion1018bmay be in contact with the semiconductor device1050.

The backing member1018is provided between a pair of the projected electrodes1016. Herein, because the insulating resin layer1012is in pressure contact with the side of the semiconductor device1050by the projected electrode1016, adhesion between the insulating resin layer1012and the semiconductor device1050is relatively high near the projected electrode1016, while the adhesion is progressively lower as drawing away from the projected electrode1016. Accordingly, in the case where an interval between the projected electrodes1016penetrating the insulating resin layer1012is large, the insulating resin layer1012is easy to peel from the semiconductor device1050between the projected electrodes1016.

In the case where the semiconductor device1050has an almost quadrangle shape when seen in planar view, and the device electrode1052, which is described later, is positioned at the periphery of the semiconductor device1050in planar view, the projected electrode1016is to be positioned at the periphery of the substrate1010for mounting a device in planar view, corresponding to the device electrode1052. In the case, the central region of the insulating resin layer1012in planar view is spaced apart from the projected electrode1016positioned at the periphery thereof in planar view; hence the insulating resin layer1012is easy to peel from the semiconductor device1050. Therefore, the backing member1018is preferably provided at the center of the insulating resin layer1012in planar view.

The shape of the backing member1018is not particularly limited to, and, for example, the planar portion1018amay also have a shape of an almost quadrangle when seen in planar view. The projected portion1018bmay also have a cylindrical shape having a certain diameter or a quadrangle prism or the like, and the number of the projected portions1018bis not limited to. Further, the backing member1018may also have a structure in which the planar portion1018aenters the insulating resin layer1012without having the projected portions1018b, or may also have only the projected portion1018binstead of the planar portion1018a.

The semiconductor module1030is formed by mounting the semiconductor device1050on the substrate1010for mounting a device provided with the structure stated above. The semiconductor module1030according to the present embodiment has a structure in which the projected electrode1016of the substrate1010for mounting a device and the device electrode1052of the semiconductor device1050are connected electrically via the insulating resin layer1012.

The semiconductor device1050has the device electrode1052facing each of the projected electrodes1016. The surface of the device electrode1052is covered with a metal layer1053such as a Ni/Au plated layer. The metal layer1053may also be dispensable. An insulating film1054such as a silicon dioxide film is provided on the major surface of the semiconductor device1050on the side where the device electrode1052is provided. Further, a device protecting layer1056such as polyimide layer in which an opening portion is provided such that the device electrode1052is exposed, is laminated on the major surface of the semiconductor device1050on the insulating film1054and on the side in contact with the insulating resin layer1012. Specific example of the semiconductor device50includes a semiconductor chip such as an integrated circuit (IC) and a large-scale IC (LSI) or the like. In addition, for example, aluminum (Al) is used for the device electrode1052.

In the present embodiment, the insulating resin layer1012is provided between the substrate1010for mounting a device and the semiconductor device1050, and the projected electrode1016penetrating the insulating resin layer1012to be connected electrically to the device electrode1052provided in the semiconductor device1050. Because the surface of the projected electrode1016and that of the device electrode1052are respectively covered with Ni/Au plated layers, the two electrodes are connected via a contact of Au layers (Au—Au contact) that are arranged on the topmost surface. Therefore, the connection reliability between the projected electrode1016and the device electrode1052can be further improved.

(Method for Producing Substrate for Mounting Device and Semiconductor Module)

FIGS. 18A to 18EandFIGS. 19A and 19Bare cross-sectional diagrams illustrating a method for forming the projected electrode1016and the projected portion1018b. As illustrated inFIG. 18A, a copper plate1013is at first prepared as a metal plate having a thickness that is larger than at least the total of the height of the projected electrode1016and the thickness of the wiring layer1014.

As illustrated inFIG. 18B, resists1071are subsequently formed selectively in accordance with the pattern of the projected electrodes1016by a lithography process; and resists1072are formed selectively in accordance with the pattern of the projected portions1018bof the backing member1018. Specifically, the resists71and72are formed selectively on the copper plate1013in the following process: a resist film with a certain thickness is attached to the copper plate1013by using a laminating apparatus, and exposed by using a photomask with the patterns of the projected electrodes1016and the projected portions1018b; and the resist film is then developed. In order to improve the adhesion with the resists, it is preferable that the surface of the copper plate1013is subjected to a pretreatment such as grinding and washing or the like before laminating the resist film, if needed.

As illustrated inFIG. 18C, certain patterns of the projected electrodes1016and the projected portions1018bare then formed on the copper plate1013, respectively, by using the resists1071and1072as masks. Specifically, the projected electrodes1016and the projected portions1018bwith certain patterns are formed respectively by etching the copper plate1013with the use of the resists1071and1072as masks. After forming the projected electrodes1016and the projected portions1018b, the resists1071and1072are subsequently peeled off by using a parting agent.

As illustrated inFIG. 18D, a resist1073with a plating-resistant property is stacked on the major surface of the copperplate1013on the side where the projected electrodes1016and the projected portions1018bare formed, by a lithograph process, and opening portions1073aare formed at positions corresponding to the top faces of the projected electrodes1016.

As illustrated inFIG. 18E, metal layers1017are formed on the top faces of the projection electrodes1016exposed at the opening portions1073a. The metal layers1017are formed as Ni/Au metal layers by, for example, an electrolytic plating process or a non-electrolytic plating process. In the case where the metal layers1017are formed by an electrolytic plating process or a non-electrolytic plating process, the directions of the crystal grains of the metal that constitutes the metal layers1017are aligned in the direction perpendicular to the contact face of the device electrode1052. Therefore, when pressure-bonded to the device electrode1052, the pressure exerted on the device electrode1052can be absorbed by the metal layer1017; hence, the fear that the device electrode1052could be damaged can be reduced.

The metal layer constituting the metal layer1017is formed such that the Ni layer thereof is in contact with the projected electrode1016and the Au layer thereof is in contact with the device electrode1052. A method for forming the metal layer1017is not particularly limited thereto, and the metal layer1017may also be formed by using a conductive paste such as copper paste, silver paste, and gold paste. The height of the projected electrode1016including the metal layer1017is larger than that of the projected portion1018bof the backing member1018, by forming the metal layer1017on the top face of the projected electrode1016. The resist1073is peeled off by using a parting agent after forming the metal layer1017.

As illustrated inFIG. 19A, the insulating resin layer1012is then stacked on the major surface of the copper plate1013on the side where the projected electrodes1016and the projected portions1018bare formed.

As illustrated inFIG. 19B, a certain amount of the insulating resin layer1012is removed by subjecting the major surface of the insulating resin layer1012to an etching treatment by, for example, an O2plasma, such that the metal layer1017covering the top face of the projected electrode1016is exposed, making the projected electrode1016including the metal layer1017penetrate the insulating resin layer1012. The removal of the insulating resin layer1012for exposing the metal layer1017, may also be carried out by subjecting the insulating resin layer1012to mechanical grinding.

The projected electrodes1016and the projected portions1018bof the backing member1018are formed on the copper plate1013by the process stated above. In the projected electrode1016and the projected portion1018bof the present embodiment, the diameters in the base portions, the diameters in the tip portions, and the heights thereof are, for example, about 60 μmφ, about 40 μmφ, and about 20 μm, respectively. With respect to the thickness of the metal layer1017, the thickness of the Ni layer is about 1 to 3 μm, and that of the Au layer is about 0.25

FIGS. 20A to 20Eare cross-sectional diagrams illustrating a method for forming the wiring layer1014and the planar portion1018a, and a method for connecting the projected electrode1016and the device electrode1052. As illustrated inFIG. 20A, the copper plate1013on which the insulating resin layer1012is stacked, and the semiconductor device1050are arranged such that the projected electrodes1016and the device electrodes1052face with each other. The copper plate1013and the semiconductor device1050are then pressure-bonded by using a press machine. The pressure and the temperature at the press working are about 5 Mpa and 200° C., respectively. Due to this, the copper plate1013, the insulating resin layer1012, and the semiconductor device1050are formed into one body such that the projected electrodes1016and the device electrodes1052are pressure-bonded to be connected electrically, as illustrated inFIG. 20B. The insulating resin layer1012with a thickness similar to that of the metal layer1017, lies between the top face of the projected portion1018band the device protecting layer of the semiconductor device1050.

Resists (not illustrated) are then formed selectively in accordance with the patterns of the wiring layer1014and the planar portions1018aof the backing member1018, on the major surface of the copper plate13on the side opposite to the insulating resin layer1012. As illustrated inFIG. 20C, certain patterns of the wiring layer1014and the planar portions1018aare subsequently formed on the copper plate1013by etching the major surface of the copper plate1013with the use of the resists as masks, followed by removal of the resists. The planar portions1018aare formed in the regions where the projected portions1018bare present, and the backing member1018is completed by forming the planar portions1018a. In the present embodiment, the thickness of the wiring layer1014and the planar portion1018aare about 15 to 20 μm, respectively. Alternatively, the backing member1018may also be structured by only the projected portions1018bby etching the copper plate1013, without forming the resists at the position where the planar portions1018aare to be formed.

Herein, because the projected electrodes1016, the projected portions1018b, and the planar portions1018aare formed by the same copper plate1013, the backing member1018and the projected electrode1016are made of the same material. In addition, because the projected portions1018band the planar portions1018aare formed at a same time when the projected electrodes1016and the wiring layer1014are formed, respectively, the number of the production processes for forming the backing member1018is not needed to be increased, allowing an increase in the production cost to be suppressed.

As illustrated inFIG. 20D, a protecting layer1020having opening portions1020ain the regions corresponding to the positions where solder bumps1022are to be formed, is formed on the major surface of the wiring layer1014and the planar portions1018aon the side opposite to the insulating resin layer1012. As illustrated inFIG. 20E, the solder bumps1022are then formed within the opening portions1020a. A semiconductor module1030can be formed by the production process stated above. Or, when the semiconductor device1050is not mounted, the substrate1010for mounting a device can be obtained.

From a general overview of operation effects by the structure stated above, the substrate1010for mounting a device and the semiconductor module1030according to the present embodiment are provided with the backing member1018for backing up the insulating resin layer1012, on the insulating resin layer1012. In particular, the backing member1018is provided between a pair of the projected electrodes1016, further at the center of the insulating resin layer1012in planar view. And, the projected portion1018bof the backing member1018is embedded in the insulating resin layer1012to back up the insulating resin layer1012. With this, peel of the insulating resin layer1012from the semiconductor device1050can be prevented, allowing the connection reliability between the projected electrode1016and the device electrode1052to be improved. As a result, when the semiconductor module1030is implemented on a printed wiring board, the connection reliability between the semiconductor device1050and the printed wiring board can be improved.

Moreover, because the insulating resin layer1012lies between the top face of the projected portion1018band the semiconductor device1050, the insulating resin layer1012lying between the two is in the state of being sandwiched by the two. Therefore, peel of the insulating resin layer1012from the semiconductor device1050can be prevented more effectively. If the insulating resin layer1012is peeled from the semiconductor device1050, moisture or the like included in atmosphere enters a void created as a result of the peeling, which could be a cause of corrosion of the semiconductor module1030; however, creation of such a void can be suppressed according to the present embodiment, allowing the reliability of the semiconductor module1030to be improved.

Further, because the protecting layer1020covers the planar portion1018aof the backing member1018, the covering area thereof is large, allowing the adhesion property of the protecting layer1020to be improved. In addition, in the present embodiment, the backing member1018lies across the protecting layer1020and the insulating resin layer1012; hence, the adhesion between the protecting layer1020and the insulating resin layer1012, in particular, the adhesion against a horizontal stress is improve, allowing the connection reliability between the projected electrode1016and the device electrode1052to be more improved, further allowing the connection reliability between the substrate1010for mounting a device and the semiconductor device1050to be more improved.

In Embodiment 7 stated above, the height of the projected electrode1016including the metal layer1017is made larger than that of the projected portion1018bof the backing member1018by providing the metal layer1017on the top face of the projected electrode1016, thereby the insulating resin layer1012lying between the projected portion1018band the semiconductor device1050. Different from Embodiment 7, the insulating resin layer1012is made so as to lie between the projected portion1018band the semiconductor device1050by making the height of the projected portion1018bitself smaller than that of the projected electrode1016in Embodiment 8. Hereinafter, the present embodiment will be described. It is noted that the structures of the substrate1010for mounting a device and the semiconductor module1030or the like, the method for forming the wiring layer1014and the planar portion1018a, and the method for connecting the projected electrode1016and the device electrode1052are basically the same as with Embodiment 7; and the same structure as in Embodiment 7 is denoted with the same reference numeral as in Embodiment 7, and the description with respect thereto is omitted appropriately.

FIGS. 21 and 22are schematic cross-sectional diagrams illustrating a structure of the substrate1010for mounting a device and the semiconductor module1030using the same according to Embodiment 8. As illustrated inFIG. 21, the substrate1010for mounting a device according to the present embodiment is provided with the backing member1018having the projected portion1018cwith a height smaller than that of the projected electrode1016. Different from Embodiment 7, the height of the projected portion1018citself is smaller than that of the projected electrode1016; hence the insulating resin layer1012can be made so as to lie between the projected portion1018cand the device protecting layer1056of the semiconductor device1050, without providing the metal layer1017on the top face of the projected electrode1016. As illustrated inFIG. 22, the metal layer1017may also be provided on the top face of the projected electrode1016in order to improve the connection reliability between the projected electrode1016and the device electrode1052by connecting the two with an Au—Au contact.

FIGS. 23A to 23E, andFIGS. 24A and 24Bare cross-sectional diagrams illustrating a method for forming the projected electrodes1016and the projected portions1018c. A description will be made taking the case where the metal layer1017is provided, as an example.

As illustrated inFIG. 23A, a copper plate1013is at first prepared as a metal plate having a thickness that is larger than at least the total of the height of the projected electrode1016and the thickness of the wiring layer1014.

As illustrated inFIG. 23B, resists1071are subsequently formed selectively in accordance with the pattern of the projected electrodes1016by a lithography process; and resists1074are formed selectively in accordance with the pattern of the projected portions1018cof the backing member1018. The size of the resist1074should be smaller or equal to the resolution limit in etching the copper plate1013, which will be described later.

As illustrated inFIG. 23C, certain patterns of the projected electrodes1016and the projected portions1018care then formed on the copper plate1013, respectively, by using the resists1071and1072as masks. Herein, the size of the resist1074formed in accordance with the pattern of the projected portions1018cis smaller or equal to the resolution limit in etching. Therefore, when performing, for example, a wet etching that develops isotropically on the copper plate13, the copper plate1013directly below the resist1074is progressively etched from the side face thereof, as the etching develops. Therefore, the height of the projected portions1018cformed by the resist1074is made smaller than that of the projected electrode1016. Alternatively, the height of the projected portions1018cmay be made smaller than that of the projected electrode1016by removing the top portion of the projected portions1018cwith the use of etching or the like, after forming the projected portions1018chaving the same height as that of the projected electrodes1016. After forming the projected electrodes1016and the projected portions1018c, the resists1071and1074are peeled off by using a parting agent.

As illustrated inFIG. 23D, a resist1073awith a plating-resistant property is stacked on the major surface of the copper plate1013on the side where the projected electrodes1016and the projected portions1018care formed, by a lithograph process, and opening portions1073aare formed at the positions corresponding to the top faces of the projected electrodes1016. As illustrated inFIG. 23E, the metal layers1073are subsequently formed on the top faces of the projected electrodes1016exposed at the opening portions1073a, and the resist1073is peeled off by using a parting agent.

As illustrated inFIG. 24A, the insulating resin layer1012is then stacked on the major surface of the copper plate1013on the side where the projected electrodes1016and the projected portions1018care formed. Subsequently, as illustrated inFIG. 24B, a certain amount of the insulating resin layer1012are removed to expose the metal layers1017such that the projected electrodes1016including the metal layers1017penetrate the insulating resin layer1012.

The projected electrodes1016and the projected portions1018cof the backing member1018are formed on the copper plate1013by the process stated above. In the projected portion1018cof the present embodiment, the diameter in the base portion, the diameter in the top portion, and the height thereof are, for example, about 40 μmφ, about 20 μmφ, and about 15 μm, respectively.

The copper plate1013on which the projected electrodes1016and the projected portions1018care formed, and on which the insulating resin layer1012is stacked, by the process stated above, is pressure-bonded to the semiconductor device1050in the same way as with Embodiment 1; thereby, the projected electrodes1016and the device electrodes1052are connected electrically, allowing the semiconductor module1030to be formed.

As stated above, according to Embodiment 8, the following advantages can be further obtained in addition to the above advantages of Embodiment 7. That is, in the present embodiment, the insulating resin layer1012is made so as to lie between the projected portions1018cand the device protecting layer1056of the semiconductor device1050, by making the size of the projected portion1018citself of the backing member1018smaller than that of the projected electrode1016. Therefore, because the thickness of the insulating resin layer1012lying between the projected portion1018cand the device protecting layer1056can be freely set, peeling of the insulating resin layer1012from the semiconductor device1050can be prevented more effectively. As a result of that, the connection reliability between the projected electrode1016and the device electrode1052can be further improved.

A portable apparatus provided with the semiconductor module of the present invention will be described below. An example will be taken in which the semiconductor module is mounted on a portable phone as the portable apparatus; however, the portable apparatus may also be an electronic apparatus such as, for example, a personal digital assistance (PDA), a digital camcorder (DVC), and a digital still camera (DSC).

FIG. 25is a diagram illustrating the structure of a portable phone provided with the semiconductor modules30and1030directed to each Embodiment stated above. The portable phone111has a structure in which the first case112and the second case114are connected by the movable portion120. The first case112and the second case114are pivoted on the movable portion120. On the first case112, the display unit118displaying information such as characters and images or the like, and the speaker unit124are provided. On the second case114, the manipulation unit122such as manipulation buttons or the like, and the microphone unit126are provided. The semiconductor modules30and1030directed to each Embodiment of the present invention is mounted inside such portable phone111.

FIG. 26is a partial cross-sectional diagram of the portable phone illustrated inFIG. 25(cross-sectional diagram of the first case112). The semiconductor modules30and1030directed to each Embodiment of the present invention are mounted on the printed wiring board128via the solder bumps22and1022to be connected electrically to the display unit118or the like via such printed wiring board128. A heat-dissipating substrate116such as a metal substrate is provided on the back face side of the semiconductor modules30and1030(on the face opposite to the solder bumps22and1022) such that, for example, the heat generated by the semiconductor modules30and1030is efficiently dissipated toward the outside of the first case112without persisting therein.

The semiconductor module30directed to the above Embodiments 1 to 6 can be miniaturized and can be reduced in its production cost; hence the portable apparatuses in which such semiconductor module30is mounted can also be miniaturized and can be reduced in their production cost. In addition, according to the substrate1010for mounting a device and the semiconductor module1030directed to each of the above Embodiments 7 and 8, the connection reliability between the projected electrode1016and the device electrode1052can be improved; hence, the implementation reliability when the semiconductor module1030is implemented on a printed wiring board. Therefore, the reliability of the portable apparatuses directed to the present embodiment, in which such semiconductor module1030is mounted, can be improved.

The present invention should not be limited to each of the above embodiments, and various modifications, such as design modifications, may be made based on knowledge of a person skilled in the art. Embodiments in which such modifications are added should also fall within the scope of the present invention.

For example, in each above Embodiment, the wiring layer of the substrate for mounting a device has a single-layer or two-layer structure; however, the wiring layer may also have a multi-layer structure without being limited thereto. In addition, the wiring layer has the solder bumps formed on the exterior surface thereof, but the wiring layer should not be limited thereto. For example, the wiring layer may also have a MOS transistor adhered thereto, of which source electrode, drain electrode, and gate electrode are connected to the wiring layer electrically.

Moreover, the structure of the present invention can be applied to the production process of semiconductor packages referred to as the “Wafer Level CSP (Chip Size Package) Process”. With the process, semiconductor modules can be made thinner and be miniaturized.