Capacitance balance in dual sided contact switch

A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.

TECHNICAL FIELD

The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to capacitance and series resistance balance in a dual sided radio frequency switch with front-side contacts and backside contacts configured in accordance with a checker board layout.

BACKGROUND

The design complexity of integrated circuits (e.g., mobile radio frequency (RF) chips or transceivers) is complicated by added circuit functions to support communication enhancements. The design of these mobile RF transceivers may include the use of silicon-on-insulator technology. Silicon-on-insulator (SOI) technology replaces conventional semiconductor (e.g., silicon) substrates (e.g., wafers) with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance.

The active devices on the SOI layer may include complementary metal oxide semiconductor (CMOS) transistors. RF switch devices of mobile RF transceivers may be fabricated using CMOS transistors on SOI substrates. Unfortunately, successful fabrication of transistors using SOI technology is complicated by a parasitic environment (e.g., parasitic capacitance). Parasitic capacitance may be caused by a proximity of an active device on the semiconductor layer and a semiconductor substrate supporting a buried oxide (BOX) layer in SOI devices.

Parasitic capacitance may also be caused by the interconnects to gates and source/drain regions of the CMOS transistors. This form of contact/interconnect-to-gate capacitance is caused by a proximity between back-end-of-line (BEOL) interconnects and/or middle-of-line (MOL) trench contacts/interconnects and the transistor gates as well as the transistor gate interconnects. This parasitic capacitance adversely affects the performance of CMOS devices, resulting in circuit delays and losses. This capacitance is especially problematic for RF switch devices.

SUMMARY

A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.

A method of making a dual sided contact switch includes forming a first independent drain/source region of a multi-gate active device. The method also includes forming a first shared drain/source region of the multi-gate active device. The method includes forming a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The method also includes forming a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The method further includes forming a gate region between the first independent drain/source region and the first shared drain/source region, and between the second independent drain/source region and the second shared drain/source region.

A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a means for forming a portion of a first transistor and a second transistor. The multi-gate active device includes the first transistor and the second transistor. The dual sided contact switch also has a second independent drain/source region of the multi-gate active device, adjacent to the transistor forming means. The dual sided contact switch has a shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the transistor forming means, and also between the second independent drain/source region and the shared drain/source region.

A radio frequency front end module includes a dual sided contact switch having a first independent drain/source region of a multi-gate active device. The dual sided contact switch has a first shared drain/source region of the multi-gate active device. The dual sided contact switch also has a second independent drain/source region of the multi-gate active device adjacent to the first shared drain/source region. The dual sided contact switch has a second shared drain/source region of the multi-gate active device adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region. The dual sided contact switch also has a gate region between the second independent drain/source region and the second shared drain/source region. The radio frequency front end module has an antenna coupled to the dual sided contact switch.

DETAILED DESCRIPTION

As described herein, the use of the term “and/or” is intended to represent an “inclusive OR”, and the use of the term “or” is intended to represent an “exclusive OR”. As described herein, the term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” used throughout this description means “connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term “proximate” used throughout this description means “adjacent, very near, next to, or close to.” As described herein, the term “on” used throughout this description means “directly on” in some configurations, and “indirectly on” in other configurations.

It will be understood that the term “layer” includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described herein, the term “substrate” may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably.

Silicon-on-insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of a conventional silicon substrate in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, and improve performance. An integrated circuit built using SOI devices may show processing speed that is approximately thirty percent (30%) faster than a comparable bulk-based integrated circuit and power consumption reduced by as much as eighty percent (80%), which makes it ideal for mobile devices. SOI chips also reduce the soft error rate, which is data corruption caused by cosmic rays and natural radioactive background signals. SOI transistors offer a unique opportunity for CMOS architectures to be more scalable.

In some examples, a layer transfer process transfers a top active device portion of an SOI wafer to a handle wafer. In this process, the top portion of the SOI wafer is bonded to the handle wafer, and the bulk substrate layer (the sacrificial substrate) of the SOI wafer is removed. The process enables a backside connection system to be formed, in addition to a front-side connection system. For example, the back insulating layer may be thinned down. Openings may be formed in the back insulating layer so that backside contacts may be formed to connect to devices, such as a metal oxide semiconductor field effect transistor's (MOSFET's) source, drain, and/or body. In addition, one or more metal layers and vias may be formed on the back insulating layer to route power, ground, and/or signals to the devices. The backside contacts and one or more metal layers and vias form the backside connection system as compared to front-side contacts and metal layers and vias in the front-side connection system. Source and drain silicide is often specified to facilitate good connection between the front-side or backside connection system with the devices.

RF switch devices of mobile RF transceivers may be fabricated using CMOS transistors on SOI wafers. Unfortunately, successful fabrication of CMOS transistors using SOI technology is complicated by parasitic capacitance. For example, a parasitic capacitance in the form of contact/interconnect-to-gate capacitance may be caused by a proximity between back-end-of-line (BEOL) interconnects/middle-of-line (MOL) contacts and the transistor gates. This parasitic capacitance adversely affects the performance of CMOS devices, resulting in circuit delays and losses. This parasitic capacitance is especially problematic for RF switch devices.

Various aspects of the present disclosure provide techniques for balancing capacitance in a dual sided contact switch (e.g., RF switch). The process flow for semiconductor fabrication of the dual sided contact switch may include front-end-of-line (FEOL) processes, MOL processes, and BEOL processes.

The MOL process is the set of process steps that enable connection of the transistors to the back-end-of-line or BEOL interconnects (e.g., M1, M2, etc.) using MOL contacts. For example, parasitic capacitance in the form of contact/interconnect-to-gate capacitance is caused by proximity of the BEOL interconnects/MOL contacts and the transistor gates, drain, and source regions. The asymmetry of the parasitic capacitance adversely affects CMOS transistors, resulting in circuit delays and losses, which is especially problematic for RF switch devices. A layer transfer process may reduce the additional capacitance by moving some of the routing from a front-side to a backside of an RF integrated circuit. Moving some of the routing, however, may not sufficiently address the asymmetric issues with parasitic capacitance and series resistance.

To improve a figure of merit of the switch, a source and a drain of the switch can have contacts on different or opposite sides (e.g., a front-side and a backside) of the switch. Having the contacts on opposite sides of the switch reduces coupling capacitance and thereby improves (e.g., reduces) a figure of merit of the switch. The overall capacitance of a transistor between the source and drain, when off, is the contribution of the source-to-gate, drain-to-gate, source-to-channel, and drain-to-channel capacitances. A product of the resistance in an ON mode (Ron) and the capacitance in an OFF mode (Coff) of the stack in this RF domain yields a figure of merit (Ron*Coff) which represents the RF performance of the switch.

Having one contact on a drain of the switch/transistor on a first side of the switch and another contact on a source of the switch on a side that is opposite the first side introduces asymmetry. A parasitic environment introduced by source coupling to the gate is different than a parasitic environment introduced when the drain is coupled to the gate. For example, the asymmetry may be due to a difference in a sum of the parasitic capacitance on a front-side of the switch and a sum of the parasitic capacitance on the backside of the switch.

While the asymmetry, in this case, improves the figure of merit of the switch, there is a tradeoff with the linearity performance of the switch. For example, the switch operating under the asymmetric environment exhibits undesirable non-linear characteristics that adversely impact the performance of the switch. The undesirable non-linear characteristics may include harmonic distortion such as second harmonic distortion. Thus, while the asymmetric implementation improves the figure of merit, the performance of the switch is degraded due to second harmonic distortion.

Other implementations achieve symmetry by having contacts for the source and the drain on a same side of the switch. While these implementations reduce nonlinearity, the figure of merit of these implementations is degraded. Thus, it is desirable to introduce a switch with improved figure of merit and improved linearity.

Various aspects of the present disclosure are directed to an integrated circuit (e.g., a dual sided radio frequency switch) with improved figure of merit and improved linearity. The dual sided radio frequency switch balances capacitances and/or series resistance between the conductive (metal) layers of the integrated circuit. The dual sided radio frequency switch is a multi-gate active device.

In one aspect, the dual sided radio frequency switch includes a first unshared/independent drain/source region, a first shared drain/source region, a second independent drain/source region, a second shared drain/source region, a third independent drain/source region and a third shared drain/source region of the multi-gate active device. The shared drain/source regions and the independent drain/source regions are arranged in a checker board layout. For example, the shared drain/source regions and the independent drain/source regions are placed alternately to form a checker board layout.

The first shared drain/source region is between the first and the second independent drain/source regions and may be associated with a first active device and a second active device. For example, the first shared drain/source region is shared between the first active device and the second active device. Thus, the first independent drain/source region and at least a portion of the first shared drain/source region may be used to form the first active device. The second independent drain/source region and at least another portion of the first shared drain/source region may be used to form the second active device.

The third independent drain/source region is between the second and the third shared drain/source regions. For example, the second shared drain/source region is shared between a third active device and another active device. Thus, the third independent drain/source region and at least a portion of the second shared drain/source region may form a third active device. Similarly, the third shared drain/source region is shared between a fourth active device and yet another active device. Thus, the third independent drain/source region and at least a portion of the third shared drain/source region may be used to form a fourth active device.

The dual sided radio frequency switch further includes a first front-side conductive contact or interconnect on the first independent drain/source region and a second front-side contact on the second independent drain/source region. The dual-sided radio frequency switch further includes a first backside contact on the first shared drain/source region. Thus, the first backside contact is a shared source/drain contact. For example, the first backside contact is shared between the first active device and the second active device. In one aspect of the disclosure, the dual sided radio frequency switch includes a conductive bridge that connects the first front-side conductive contact or interconnect to the second front-side conductive contact.

The dual sided radio frequency switch further includes a third front-side conductive contact on the third independent drain/source region. The dual-sided radio frequency switch further includes a second backside contact on the second shared drain/source region and a third backside contact on the third shared drain/source region. Thus, the second backside contact is a shared source/drain contact that is shared between the third active device and another active device. The third backside contact is also a shared source/drain contact that is shared between the fourth active device and yet another active device. Similar to the shared drain/source regions and the independent drain/source regions, the front-side contacts and the backside contacts are arranged in the checker board layout.

FIG. 1is a schematic diagram of a wireless device100(e.g., a cellular phone or a smartphone) including the dual sided radio frequency switch implemented according to aspects of the present disclosure. Thus, the wireless device100benefits from the advantages of the dual sided radio frequency switch. The wireless device100may include a wireless local area network (WLAN) (e.g., WiFi) module150and an RF front-end module170for a chipset110. The WiFi module150includes a first diplexer160communicably coupling an antenna162to a wireless local area network module (e.g., WLAN module152). The RF front-end module170includes a second diplexer190communicably coupling an antenna192to the wireless transceiver120(WTR) through a duplexer180(DUP).

The wireless transceiver120and the WLAN module152of the WiFi module150are coupled to a modem (MSM, e.g., a baseband modem)130that is powered by a power supply102through a power management integrated circuit (PMIC)140. The chipset110also includes capacitors112and114, as well as an inductor(s)116to provide signal integrity. The PMIC140, the modem130, the wireless transceiver120, and the WLAN module152each include capacitors (e.g.,142,132,122, and154) and operate according to a clock118. The geometry and arrangement of the various inductor and capacitor components in the chipset110may reduce the electromagnetic coupling between the components.

The wireless transceiver120of the wireless device generally includes a mobile radio frequency (RF) transceiver to transmit and receive data for two-way communication. A mobile RF transceiver may include a transmit section for data transmission and a receive section for data reception. For data transmission, the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal having the proper output power level, and transmit the amplified RF signal via the antenna192to a base station. For data reception, the receive section may obtain a received RF signal via the antenna192and may amplify the received RF signal using a low noise amplifier (LNA) and process the received RF signal to recover data sent by the base station in a communication signal.

The wireless transceiver120may include one or more circuits for amplifying these communication signals. The amplifier circuits (e.g., LNA/PA) may include one or more amplifier stages that may have one or more driver stages and one or more amplifier output stages. Each of the amplifier stages includes one or more transistors configured in various ways to amplify the communication signals. Various options exist for fabricating the transistors that are configured to amplify the communication signals transmitted and received by the wireless transceiver120.

The wireless transceiver120and the RF front-end module170may be implemented using a layer transfer process to further separate the active device from a substrate as shown inFIGS. 2A to 2D.

FIGS. 2A to 2Dshow cross-sectional views of a radio frequency (RF) integrated circuit200during a layer transfer process according to aspects of the present disclosure. As shown inFIG. 2A, an RF device includes an active device210on an insulator layer220supported by a sacrificial substrate201(e.g., a bulk wafer). The RF device also includes interconnects250coupled to the active device210within a first dielectric layer204. As shown inFIG. 2B, a handle substrate202is bonded to the first dielectric layer204of the RF device. In addition, the sacrificial substrate201is removed. Removal of the sacrificial substrate201using the layer transfer process enables high-performance, low-parasitic RF devices by increasing the dielectric thickness. That is, a parasitic capacitance of the RF device is proportional to the dielectric thickness, which determines the distance between the active device210and the handle substrate202.

As shown inFIG. 2C, the RF device is flipped once the handle substrate202is secured and the sacrificial substrate201is removed. As shown inFIG. 2D, a post layer transfer metallization process is performed using, for example, a regular complementary metal oxide semiconductor (CMOS) process.

The active device210on the insulator layer220(e.g., BOX layer) may be a complementary metal oxide semiconductor (CMOS) transistor. The RF front-end module170(FIG. 1) may rely on these high performance CMOS RF switch technologies for successful operation.

FIG. 3Aillustrates a cross-section of a dual sided radio frequency switch300, according to aspects of the present disclosure. The dual sided radio frequency switch300may be fabricated using a layer transfer process. The dual sided radio frequency switch300has a first side337(e.g., a front-side) and a second side339(e.g., a backside) opposite the first side337.

The dual sided radio frequency switch300includes a first active device331(e.g., a transistor) and a second active device333, each having a gate and source/drain regions. Thus, the dual sided radio frequency switch300is a multi-gate active device. The dual sided radio frequency switch300further includes a first independent drain/source region372, a first shared drain/source region374, and a second independent drain/source region376. The first shared drain/source region374is between the first independent drain/source region372and the second independent drain/source region376.

The first active device331of the dual sided radio frequency switch300includes a first gate356, the first independent drain/source region372, at least a first portion of the first shared drain/source region374, and a first channel382formed on an isolation layer307. The first gate356has spacers344aand344b.

The second active device333of the dual sided radio frequency switch300includes a second gate358, the second independent drain/source region376, at least a second portion of the first shared drain/source region374, and a second channel384formed on the isolation layer307. The second gate358has spacers346aand346b.

In SOI implementations, the isolation layer307is a buried oxide (BOX) layer, and the body (e.g., including the first channel382and the second channel384) and the source/drain regions (e.g., the first independent drain/source region372, the first shared drain/source region374, and the second independent drain/source region376) are formed from an SOI layer (e.g., silicon) including shallow trench isolation (STI) regions.

One aspect of the present disclosure uses a silicidation process (e.g., a backside/front-side silicidation process) with layer transfer to form front-side/backside source/drain contacts. For example, a first front-side contact364, a backside contact366, and a second front-side contact368are respectively formed on the first independent drain/source region372, the first shared drain/source region374, and the second independent drain/source region376. A first gate contact336and a second gate contact338are respectively formed on the first gate356and on the second gate358of the dual sided radio frequency switch300. The first gate contact336, the second gate contact338, the first front-side contact364, the backside contact366, and the second front-side contact368can be silicide contacts.

In one aspect of the disclosure, the backside contact366is a backside shared source/drain contact. For example, the backside contact366is shared between the first active device331and the second active device333. This follows because the first shared drain/source region374is a shared source/drain region for the first active device331and the second active device333.

The dual sided radio frequency switch300further includes a first front-side conductive contact or interconnect324acoupled to the first independent drain/source region372/first front-side contact364and a second front-side contact326on the second independent drain/source region376/second front-side contact368. The dual sided radio frequency switch300further includes a backside contact394aon the first shared drain/source region374. As noted, the first shared drain/source region374is a shared source/drain region and the first backside contact394ais a shared source/drain contact for the first active device331and the second active device333.

The interconnects of the dual sided radio frequency switch300may also include trench interconnects and vias for coupling active devices formed during the FEOL process to metallization layers formed during the BEOL process. Front-side metallization layers are formed in a front-side dielectric layer348and backside metallization layers are formed in a backside dielectric378.

For example, the first front-side conductive contact or interconnect324ais connected or coupled to the first front-side contact364formed on the first independent drain/source region372. The second front-side conductive contact326is connected or coupled to the second front-side contact368formed on the second independent drain/source region376. The first front-side conductive contact324aand the second front-side conductive contact326, respectively, couple the first active device331and the second active device333to metallization in the BEOL layer.

The dual sided radio frequency switch300includes a backside trench interconnect and/or via396ato couple the first active device331and the second active device333to the backside metallization (e.g., a second conductive bridge397). In one aspect, the backside trench interconnect and/or via396ais coupled to the backside contact394a, which is shared between the first active device331and the second active device333.

In addition, the dual sided radio frequency switch300includes a first front-side trench interconnect and/or via328a, a second front-side trench interconnect and/or via329a, a third front-side trench interconnect and/or via334a, and a fourth front-side trench interconnect and/or via335a. The first front-side trench interconnect and/or via328acouples a first front-side metallization M1associated with the first active device331to a second front-side metallization M2associated with the first active device331. The second front-side trench interconnect and/or via329acouples the second front-side metallization M2associated with the first active device331to a third front-side metallization M3.

The third front-side trench interconnect and/or via334acouples a first front-side metallization M1associated with the second active device333to a second front-side metallization M2associated with the second active device333. The fourth front-side trench interconnect and/or via335acouples the second front-side metallization M2associated with the second active device333to the third front-side metallization M3. In one aspect of the disclosure, the third front-side metallization M3includes a first conductive bridge388that is common to the first active device331and the second active device333. For example, the first conductive bridge388couples the first active device331to the second active device333on the front-side337of the dual sided radio frequency switch300.

FIG. 3Billustrates another cross-section of the dual sided radio frequency switch300, according to aspects of the present disclosure. The cross-section ofFIG. 3Bis taken across an axis BB′ that is orthogonal to an axis AA′ of the cross-section ofFIG. 3A, as shown inFIG. 3C. For example, the cross-section ofFIG. 3Bincludes multiple first front-side conductive contacts324a,324b,324c, and324dassociated with multiple gates of the multi-gate active device. Each of the first front-side conductive contacts324a,324b,324c, and324dis coupled to the first front-side metallization M1.

The cross-section ofFIG. 3Bfurther includes multiple backside contacts (e.g., a first backside contact394aand a second backside contact394b). Multiple backside trench interconnects and/or vias396aand396b, respectively, couple the first backside contact394aand the second backside contact394bto the backside metallization that includes the second conductive bridge397. In one aspect, the second backside contact394bis fabricated on a fourth drain/source region (not shown).

FIG. 3Cillustrates a top view of a dual sided radio frequency switch with front-side contacts and backside contacts arranged in a checker board layout, according to aspects of the present disclosure. As noted, the cross-section ofFIG. 3Bis taken across the axis BB′ that is orthogonal to the axis AA′ of the cross-section ofFIG. 3A.

The dual sided radio frequency switch300includes a first set of front-side conductive contacts325in a first independent drain/source region372, a second set of front-side conductive contacts327in a second independent drain/source region376, and a third set of front-side conductive contacts355in a third independent drain/source region365. The independent drain/source regions372,376,365are arranged in a checker board layout or in an alternate configuration. That is, the first, second and third sets of front-side contacts (as well as independent drain/source regions) are offset from one another, as seen inFIG. 3C. Offsetting helps balance capacitance and series resistance.

The dual sided radio frequency switch300also includes multiple spacers344a,344b,346a, and346b. The first set of front-side conductive contacts325includes multiple first front-side conductive contacts for coupling the multiple active devices to the different metallization layers. The second set of front-side conductive contacts327and the third set of front-side conductive contacts355also include a same or different number of front-side conductive contacts as the first set of front-side conductive contacts325.

In one aspect, the first set of front-side conductive contacts325are associated with the first independent drain/source region372and the first front-side contact364. The second set of front-side conductive contacts327are associated with the second independent drain/source region376and the second front-side contact368. The third set of front-side conductive contacts355are associated with a third independent drain/source region365.

The dual sided radio frequency switch300includes a first set of backside conductive contacts357in a first shared drain/source region374, a second set of backside conductive contacts359in a second shared drain/source region363, and a third set of backside conductive contacts361in a third shared drain/source region367. The first shared drain/source region374is connected to the third drain/source region365to form a continuous drain/source region. The first independent drain/source region372is connected to the second shared drain/source region363to form a continuous drain/source region. The second independent drain/source region376is connected to the third shared drain/source region367to form a continuous drain/source region. Backside contacts394aand394bof the first set of backside conductive contacts357are larger than the front-side conductive contacts324a,324b,324c, and324(FIG. 3AandFIG. 3B) of the first set of front-side conductive contacts325, contributing to the asymmetric parasitics. The first, second and third sets of backside conductive contacts (as well as shared drain/source regions) are arranged in a checker board or alternative layout, as seen inFIG. 3C, to help balance the parasitics, e.g., capacitance and series resistance.

The first set of backside conductive contacts357includes multiple backside contacts394aand394bfor coupling the multiple active devices to the different metallization layers. The second set of backside conductive contacts359and the third set of backside conductive contacts361also include a same or different number of backside conductive contacts as the first set of backside conductive contacts357.

The first gate contact336in a first gate region is between the first independent drain/source region372and the first shared drain/source region374. The first gate contact336is also between the third independent drain/source region365and the second shared drain/source region363. The second gate contact338in a second gate region is between the second independent drain/source region376and the first shared drain/source region374. The second gate contact338is also between the third drain/source region365and the third shared drain/source region367.

FIG. 4is a process flow diagram illustrating a method400of fabricating a dual sided contact switch, according to an aspect of the present disclosure. In block402, a first independent drain/source region of a multi-gate active device is formed. In block404, a first shared drain/source region of the multi-gate active device is formed. In block406, a second independent drain/source region of the multi-gate active device is formed adjacent to the first shared drain/source region. In block408, a second shared drain/source region of the multi-gate active device is formed adjacent to the first independent drain/source region. In block410, a gate region is formed between the first independent drain/source region and the first shared drain/source region. The gate region is also formed between the second independent drain/source region and the second shared drain/source region.

According to a further aspect of the present disclosure, a dual sided contact switch is described. The dual sided contact switch includes means for forming a portion of a first transistor and a portion of a second transistor. The transistor forming means may be the first shared drain/source region374, shown inFIGS. 3A, 3B, and 3C. In another aspect, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

FIG. 5is a block diagram showing an exemplary wireless communication system500in which an aspect of the disclosure may be advantageously employed. For purposes of illustration,FIG. 5shows three remote units520,530, and550and two base stations540. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units520,530, and550include IC devices525A,525C, and525B that include the disclosed dual sided contact switch. It will be recognized that other devices may also include the disclosed dual sided contact switch, such as the base stations, switching devices, and network equipment.FIG. 5shows forward link signals580from the base station540to the remote units520,530, and550and reverse link signals590from the remote units520,530, and550to base stations540.

InFIG. 5, remote unit520is shown as a mobile telephone, remote unit530is shown as a portable computer, and remote unit550is shown as a fixed location remote unit in a wireless local loop system. For example, a remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading equipment, or other communications device that stores or retrieve data or computer instructions, or combinations thereof. AlthoughFIG. 5illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed dual sided contact switch.

FIG. 6is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the RF devices disclosed above. A design workstation600includes a hard disk601containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation600also includes a display602to facilitate a circuit design610or a dual sided contact switch design612. A storage medium604is provided for tangibly storing the circuit design610or the dual sided contact switch design612. The circuit design610or the dual sided contact switch design612may be stored on the storage medium604in a file format such as GDSII or GERBER. The storage medium604may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation600includes a drive apparatus603for accepting input from or writing output to the storage medium604.

Data recorded on the storage medium604may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium604facilitates the circuit design610or the dual sided contact switch design612by decreasing the number of processes for designing semiconductor wafers.