P-N junction in a vertical memory cell that creates a high resistance load

The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

FIELD OF THE INVENTION 
The present invention relates generally to semiconductor integrated circuit 
processing, and more specifically to a vertically oriented memory cell. 
BACKGROUND OF THE INVENTION 
The manufacturing costs of integrated circuits are largely dependent upon 
the chip area required to implement desired functions. The chip area, in 
turn, is defined by the geometries and sizes of the active components such 
as gate electrodes in metal-oxide-semiconductor (MOS) technology, and 
diffused regions such as MOS source and drain regions and bipolar emitters 
and base regions. 
With circuit advancement to the very-large-scale integration (VLSI) levels, 
more and more layers are added to the surface of the wafer. With these 
additional layers, the geometries and sizes of the active components are 
determined in part by the photolithography used to establish the 
horizontal dimensions of the various devices and circuits. The goal is to 
create a pattern which meets design requirements as well as to correctly 
align the circuit pattern on the surface of the wafer. Planarization 
techniques are generally incorporated to offset the effects of a varied 
topography to achieve the photolithography goals. 
In addition to the planarization techniques used to increase 
photolithographic resolution, the chip area also depends on the isolation 
technology used. Sufficient electrical isolation must be provided between 
active circuit elements so that leakage current does not cause functional 
or specification failures. Increasingly stringent specifications, together 
with the demand, for example, for smaller memory cells in denser memory 
arrays, places significant pressure on the isolation technology in memory 
devices, as well as in other modern integrated circuits. 
The size of a memory cell in a memory array also depends upon the 
particular devices used in the memory cell. The basic SRAM cell, for 
example, can be formed using cross-coupled CMOS inverters having 2 each 
n-channel and p-channel transistors. The cell is accessed by, typically, 2 
n-channel control gates for a standard SRAM cell and 4 control gates for 
2-port memory devices. To conserve physical layout space, the p-channel 
transistors are often replaced with resistive loads. 
Vertical orientation of the various devices used in a memory cell may also 
achieve additional packing density in VLSI devices. For example, a 
surrounding gate transistor (SGT) may allow for higher packing densities 
over the planar transistor counterpart. The SGT, where the gate electrode 
is arranged vertically around a pillar of silicon, has a source and drain 
in the pillar and substrate and uses the sidewall of the pillar as the 
channel. The channel length thus depends upon the height of the pillar and 
can be changed without changing the occupied area of the transistor. A 
vertical orientation of the remaining devices within the memory cell in 
conjunction with the SGT will reduce the area required even further. 
It is therefore an object of this invention to provide a method of forming 
a vertically oriented memory cell which allows for increased packing 
density by reducing the area required to build the cell while maintaining 
the electrical integrity and performance of the cell. 
It is a further object of this invention to provide such a method which 
utilizes conventional process flows. 
Other objects and advantages of the invention will be apparent to those of 
ordinary skill in the art having reference to the following specification 
together with the drawings. 
SUMMARY OF THE INVENTION 
The invention may be incorporated into a method for forming a semiconductor 
device structure, and the semiconductor device structure formed thereby, 
by etching a substrate to form a first and a second pillar. First and 
second surrounding gates are formed adjacent to the pillars. First and 
second interconnects are formed, wherein the first interconnect is formed 
over the first pillar and the second interconnect is formed over the 
second pillar. First and second pass transistors are formed, wherein the 
source/drain regions of the first pass transistor are formed over the 
first interconnect and the source/drain regions of the second pass 
transistor are formed over the second interconnect. First and second load 
resistors are formed wherein the first load resistor is formed over the 
source/drain regions of the first pass transistor and the second load 
resistor is formed over the source/drain regions of the second pass 
transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The process steps and structures described below do not form a complete 
process flow for manufacturing integrated circuits. The present invention 
can be practiced in conjunction with integrated circuit fabrication 
techniques currently used in the art, and only so much of the commonly 
practiced process steps are included as are necessary for an understanding 
of the present invention. The figures representing cross-sections of 
portions of an integrated circuit during fabrication are not drawn to 
scale, but instead are drawn so as to illustrate the important features of 
the invention. 
Referring to FIG. 1, an integrated circuit is to be formed on a silicon 
substrate 10. The silicon is patterned and a pillar or island 12 of 
silicon is formed from the substrate by etching away the silicon substrate 
from around the area where the pillar or island is to remain. A gate oxide 
layer 14 is formed over the substrate and along the sidewalls and on top 
of the pillar 12. A polysilicon layer is formed over the gate oxide layer 
14 and pillar 12. This polysilicon layer is then etched back to form a 
gate electrode shown as regions 16 and 18. This cross section indicates 
how the single gate electrode surrounds the pillar 12. The gate electrode 
also surrounds the pillar outside the plane of the drawing. An 
illustration of the formation of the surrounding gate transistors is 
described in "Impact of Surrounding Gate Transistor (SGT) for 
Ultra-High-Density LSI's" by Hiroshi Takato et al, in Transactions On 
Electron Devices, Vol. 38, No. 3, March 1991. For ease of illustration, 
reference will be made only to 18 as the gate electrode. The polysilicon 
gate 18, the pillar 12 and the substrate are then implanted with an N-type 
dopant to form an N.sup.' polysilicon gate and N.sup.' source/drain 
regions 17 and 19. The n-channel transistor thus comprises the gate 
electrode 18, gate oxide 14, pillar 12 comprising source/drain regions 17, 
19 and a channel region and the substrate. 
Alternatively, polysilicon layer 18 may be a deposited N+ polysilicon. An 
implant is then made into the pillar 12 and source/drain regions 17, 19 to 
achieve the required dopant level in these elements of the device 
transistor. A first dielectric layer 20 is then formed over the 
polysilicon gate 18 and the pillar 12 to separate these areas from 
subsequent layers. Dielectric layer 20 is a grown or deposited oxide 
having a thickness of between approximately 500-10000 angstroms. The 
silicon substrate 10 and source/drain regions 19 thus act as the Vss 
ground bus. 
Referring to FIG. 2, an opening 21 is etched, preferably by an anisotropic 
etch, to expose a portion of the source/drain region 17 in pillar 12 and a 
portion of the polysilicon gate 18. These openings will allow connections 
to be made to this transistor through the gate 18 and source/drain region 
17. 
Referring to FIG. 3, a conductive layer is formed over the integrated 
circuit, patterned and etched to form interconnects 22 and 24 in the 
openings 21. In the preferred embodiment, these interconnects are formed 
from N+ deposited polysilicon to form an ohmic contact to the underlying 
areas. Interconnect 22 forms an ohmic contact to the source/drain region 
17 and interconnect 24 forms an ohmic contact to the polysilicon gate 18. 
A second dielectric layer 26 is then formed over the integrated circuit. 
Dielectric layer 26 is a grown or deposited oxide having a thickness of 
between approximately 500-2000 angstroms. An opening 25 is formed in the 
second dielectric layer 26 to expose a portion of the interconnect 22 
disposed over the source/drain region 17 in pillar 12. 
Referring to FIG. 4, a polysilicon layer 28 is formed over the dielectric 
layer 26 and in the opening 25. The polysilicon layer 28 is preferably a 
deposited N-type layer. An oxide layer is formed over the polysilicon 
layer 28 and a polysilicon layer is formed over the oxide layer. The oxide 
layer and upper polysilicon layer are patterned and etched by conventional 
methods to form a gate oxide layer 30 and a polysilicon gate electrode 32. 
Polysilicon gate electrode is preferably a deposited P or N-type layer. 
The polysilicon layer 28 is then implanted with a P-type dopant. The 
channel region under the gate electrode 32 remains N-type, as represented 
by the N. Polysilicon layer 28 then becomes the source/drain and channel 
region for a thin film transistor comprising gate electrode 32, gate oxide 
30 and polysilicon layer 28. A portion of the source/drain 28 of the thin 
film p-channel transistor is physically located over the N-type 
interconnect 22 which is disposed over the pillar 12. A third dielectric 
layer 34 is formed over the polysilicon layer 28 and gate electrode 32. An 
opening is then formed in the dielectric layer 34 over opening 25. 
Alternatively, the gate electrode 32 may be formed underneath the 
source/drain layer 28 by forming a polysilicon layer and patterning and 
etching the layer to form the electrode. Layer 28 would then be formed 
over the electrode and appropriately doped to form the source, drain and 
channel regions of the thin film transistor. 
Referring to FIG. 5, a conductive layer 36 is formed over the dielectric 
layer 34 and in the opening 25 in dielectric layer 34. Layer 36 is 
preferably an N-type deposited or implanted polysilicon layer. 
Alternatively, layer 36 may be a deposited P-type layer which is then 
appropriately doped N-type. Layer 36 is then patterned and etched to form 
the power bus, such as a Vcc signal line, and an interconnect to the 
source/drain region of polysilicon layer 28. Layer 36 forms a part of the 
resistive load which is the reverse-biased p/n junction between layer 36 
and the source/drain region 28. A portion of layer 36 is formed over the 
interconnect 22 and pillar 12. A fourth dielectric layer 38 is formed over 
the polysilicon layers 36 and 28. Layer 38 is a grown or deposited oxide 
layer having a thickness of between approximately 1000-10000 angstroms. An 
opening 40 is then formed in dielectric layer 38 and 34 to expose a 
portion of the source drain region 28 of the p-channel thin film 
transistor. The various dielectric layers 20, 26, 34 and 38 may also be a 
planarizing film/dielectric composite layer such that an upper portion of 
the composite layer can promote planarization of the wafer's surface 
before subsequent layers are formed. For example, the composite layer may 
be a spin-on-glass layer disposed over an oxide layer wherein the 
spin-on-glass promotes planarization of the surface. 
One alternative to the above described invention which also uses a positive 
Vcc power supply provides for an n-channel thin film transistor instead of 
the p-channel transistor. The thin film transistor comprising gate 
electrode 32, gate oxide 30 and source/drain and channel regions in layer 
28 will form the n-channel transistor. Thus, the channel region will 
remain P-type after the source and drain regions are implanted with a 
N-type dopant. Layer 36, which forms the Vcc signal line will then be a 
deposited or implanted P-type layer. P-type layer 36 will be heavily doped 
by a low energy N-type implant so that the contact to layer 28 remains 
P-type while an upper portion of layer 36 is N-type to form the resistive 
element of the load device at positive voltage. 
A second alternative which utilizes an opposite power supply configuration 
wherein layer 36 acts as the Vss ground bus and the silicon substrate 10 
and source/drain regions 19 act as the Vcc power supply. This alternative 
incorporates a p-channel surrounding gate transistor as well as the 
p-channel thin film transistor. In this alternative, the polysilicon gate 
18, pillar 12 and the substrate are implanted with a P-type dopant to form 
a P-type gate electrode and P-type source and drain regions 17 and 19. 
Interconnect 22 will then be a P-type deposited polysilicon to form an 
ohmic contact to the source/drain region 17. Layer 36, which forms the Vcc 
signal line will be N-type polysilicon which is then implanted with a 
low-energy P-type dopant to form the reverse biased P/N junction within 
layer 36 which acts as the resistive load device. 
A third alternative which also utilizes this opposite power supply 
configuration which comprises a p-channel surrounding gate transistor, 
P-type interconnect 22, n-channel thin film transistor with its 
source/drain region in layer 28 and a P-type polysilicon layer 36. In this 
alternative, the reverse biased P/N junction is formed between layers 36 
and 28. 
Referring to FIG. 6, a conductive layer 42 is formed over the dielectric 
layer 38 and in the opening 40. Conductive layer 42 is preferably a metal 
such as aluminum or a refractory metal such as titanium or tungsten. 
Conductive layer 42 forms a contact to the source drain region 28 of the 
thin film transistor. 
Another alternative to the above described invention is shown in FIG. 7. An 
integrated circuit is to be formed on a silicon substrate 10. A field 
oxide region 42 is formed over a portion of the substrate 10. A planar 
transistor is formed instead of the above described surrounding gate 
transistor. The planar transistor comprises gate electrode 46 which is 
formed over gate oxide 44. The planar transistor is formed by conventional 
methods as known in the art. To achieve the vertical orientation of the 
memory cell, the process steps at this point follow those steps described 
above. The interconnect 22 is formed over the source/drain region 52. A 
portion of the P-type source/drain region 28 of the thin film transistor 
or pass gate is formed over the interconnect 22. The N-type polysilicon 
layer 36 is formed over the source/drain region 28 which is formed over 
the interconnect 22. Although the surrounding gate transistor achieves 
greater space savings than the planar transistor, the vertical orientation 
of the cell using the planar transistor utilizes less surface area than a 
conventional planar memory cell. 
Referring to FIG. 8, an electrical diagram is shown to illustrate the 
present invention. The active region 19 acts as a plate providing the Vss 
power supply. The T1 transistor is the surrounding gate transistor. In the 
preferred embodiment, T1 has an N-type source/drain region connected to 
the P-type source/drain region of the T3 thin film transistor or pass 
gate. The upper N-type polysilicon layer 36 shown in FIG. 6 forms a 
contact to the P-type source/drain region of T3. Layer 36 provides the Vcc 
power supply and forms the reverse biased diode between layer 36 and the 
source/drain region T3, shown as 28 in FIG. 6, which may act as a 
resistive load device R1. The gate electrode 18 of T1 will connect outside 
the plane of the drawing to the source/drain region of another thin film 
transistor T4. In other words, FIG. 6 will be duplicated elsewhere on the 
chip to provide, for example, the connection of the gate electrode through 
the interconnect (shown as 24 in FIG. 3) to the source/drain region of the 
thin film transistor or pass gate T4. The conductive layer 42 which 
contacts the source/drain region of the thin film transistor T3 through 
opening 40 (shown in FIG. 6) will provide one of the data bit lines (BL) 
to the memory cell. 
The vertical orientation of the memory cell wherein the resistive load 
device is disposed over the source/drain of the thin film transistor or 
pass gate T3 which is disposed over the source/drain of the n-channel 
transistor T1, offers a substantial reduction in the area required to form 
the memory cell while at the same time maintaining the desired functions 
of the circuit. In addition, the pass gate T3 and the resistive load 
device utilize much of the same surface area as the surrounding gate 
transistor T1. The surface area required to build this cell can save up to 
possibly as much as 40 to 50 percent over its planar counterpart. 
While the invention has been particularly shown and described with 
reference to a preferred embodiment, it will be understood by those 
skilled in the art that various changes in form and detail may be made 
therein without departing from the spirit and scope of the invention.