Drain extended PMOS transistor with increased breakdown voltage

A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

FIELD OF INVENTION

The present invention relates generally to semiconductor devices, and more particularly to a drain extended PMOS transistor having a split drain implant that facilitates an increased breakdown voltage.

BACKGROUND OF THE INVENTION

Power semiconductor products are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices for high power switching applications. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-to-source on-state resistance (Rdson), and the ability to withstand high blocking voltages without suffering voltage breakdown failure (high breakdown voltage ratings). Breakdown voltage is typically measured as drain-to-source breakdown voltage with the gate and source shorted together (BVdss), where DEMOS device designs often involve a tradeoff between breakdown voltage BVdss and Rdson.

Referring toFIG. 1Aa conventional drain extended PMOS control transistor CT1is illustrated in an integrated circuit or semiconductor device2with a p-type drain24spaced from a gate14,16having sidewall spacers20. The transistor CT1is formed in a p-doped silicon substrate4(P+) with a lower epitaxial silicon4a(P-lower epi) formed over the substrate4, where a p-type upper epitaxial silicon6(upper epi) is formed over the lower EPI4a, and an n-buried layer8(NBL) extends in an upper portion of the lower EPI4aand a lower portion of the upper EPI6. An N-WELL12is formed in an upper portion of the upper EPI6, leaving a p-type drift region6aoutside the N-WELL12, and various field oxide (FOX) isolation structures10are formed to separate different terminals of the transistor CT1from one another and from other components in the integrated circuit device2.

A p-type source (S)22is formed in the N-WELL12along one side of a channel region28of the N-WELL12, and an n-type backgate (BG)26, in the illustrated example, is spaced from the source22in the N-WELL12. A p-type extended drain (D)24is formed in the drift region6a, and is spaced from the other side of the channel28. The transistor gate structure (G) includes a thin gate dielectric or gate oxide14formed over the channel region28of the N-WELL12, which also partially overlies a portion of the p-drift region6a, with a conductive gate electrode16formed over the thin gate oxide14and sidewall spacers20formed along the lateral sides of the gate (G).

FIG. 1Bis a schematic illustration of an exemplary high voltage application in which the conventional DEPMOS CT1ofFIG. 1Ais employed as a control transistor for driving the gate of a bridge high-side driver DENMOS.FIG. 1Billustrates a half H-bridge driver circuit in the semiconductor device2powered by a DC supply voltage VCC, with the conventional DEPMOS control transistor CT1ofFIG. 1Aand a DENMOS control transistor CT2together forming an inverter for controlling a gate voltage of a high-side DENMOS drive transistor T2in the half bridge circuit. The circuit includes two load driving n-channel power devices such as DENMOS or LDMOS (lateral diffused MOS) devices T1and T2having corresponding sources S1and S2, drains D1and D2, and gates G1and G2, respectively, coupled to drive an inductive load. The transistors T1and T2are arranged as a pair of low and high-side drivers, respectively, with the load coupled between an intermediate node N1of the driver pair and ground.

A supply voltage VCC is coupled to the drain D2of the high-side driver T2, and can be a positive terminal of a battery source, wherein the ground may be the battery negative terminal, for example, in automotive applications. The low-side driver T1and the high-side driver T2are coupled in series between the supply voltage VCC and ground, where the high side driver transistor T2has a drain D2coupled to VCC and a source S2coupled with the intermediate node N1at the load. The low-side transistor T1has a drain D1coupled to the node N1and a source S1coupled to ground. The intermediate node N1between the transistors T1and T2is coupled to a first terminal of a load and the other load terminal is coupled to ground, wherein the load is typically not a part of the device2. The low and high side transistor gates G1and G2are controlled so as to drive the load in alternating fashion, wherein an inverter CT1, CT2(including the DEPMOS transistor CT1ofFIG. 1A) is illustrated to drive the high-side gate G2. When the high-side transistor T2is on, current flows through the high-side transistor T2and the load in a first direction, and when the low-side transistor T1is on, current flows through the load and the low-side transistor T1in a second opposite direction.

In the illustrated device2, the source S of the DEPMOS control transistor CT1is coupled to a high voltage VCC+VGS, where VGS is the gate-to-source voltage required to turn the high-side device T2on, and VCC is the supply voltage. In this configuration, the upper control transistor CT1must be designed to withstand high drain-to-source voltages without breakdown when the upper control transistor CT1is off and the lower control transistor CT2is on. In this condition, the drain D of the transistor CT1is essentially at ground potential, while the source S remains at VCC+VGS. In automotive and other applications in which bridge driver circuits are used for high wattage digital audio equipment or in other high power circuits, the supply voltage VCC can be very high, such as 65 to 80 volts DC, wherein the driver devices T1and T2need to withstand drain-to-source voltages of about VCC without breakdown. Furthermore, the DEPMOS control transistor CT1needs to withstand even higher drain-to-source voltages, since the drain D of the upper control transistor CT1may be near ground potential when the lower control transistor CT2is on. In particular, the VGS of the high-side driver transistor T2may be 5 to 15 volts DC, wherein the off-state drain-to-source voltage across the DEPMOS transistor CT1may be 100 volts or more.

As shown inFIG. 1A, the drain region24is spaced from the channel28and from the gate14,16(e.g., an extended-drain architecture) to provide the drift region6ain the p-type epitaxial silicon6between the channel28and the drain24. In operation, the spacing of the drain24and the channel28spreads out the electric fields, thereby increasing the breakdown voltage rating of the device (higher BVdss). However, the drain extension increases the resistance of the drain-to-source current path (Rdson), whereby DEMOS device designs often involve a tradeoff between high breakdown voltage BVdss and low Rdson.

Another breakdown voltage limitation of the transistor CT1relates to the thickness of the epitaxial silicon6in the device2, wherein the substrate4is grounded and the transistor source, drain, and channel (e.g., including the N-WELL12and the p-drift region6a) are formed in the epitaxial silicon6. In particular, when the control transistor CT1is on, the drain voltage is very high, and it is desirable to separate the p-type drain24and the drift region6afrom the underlying p-type substrate4that is grounded, to prevent punch-thru current between the drain24and the substrate4. Accordingly, a rather heavily doped n-buried layer8is typically formed prior to forming the upper epitaxial silicon layer6, in order to separate the drift region6aand the drain24from the substrate4, and to thereby inhibit on-state punch-thru current, with the n-buried layer8typically being connected to the n-type backgate26through the N-WELL12, whereby the n-buried layer8is tied to the source voltage (VCC+VGS). However, the presence of the n-buried later at such a high voltage may lead to off-state breakdown when the drain24is near ground potential. Thus, while the n-buried layer8operates to prevent on-state punch-thru current, the n-buried layer8limits the off-state breakdown voltage rating of the DEPMOS transistor CT1for a given epitaxial thickness and drift region doping amount.

In an “off” state of the transistor CT1, the drain24is essentially at ground, and the source voltage VCC+VGS is dropped across the drift region6aportion extending between the bottom of the drain24and the n-buried layer8, and also between the channel-side of the drift region6aand the drain24. If the breakdown occurs on the surface between the gate16and the p-type drain24, the lateral extension of the drift region6acan be increased (e.g., the lateral spacing of the drain24from the gate16may be increased to prevent lateral breakdown). However, the vertical spacing between the bottom of the p-type drain24and the n-buried layer8is more difficult to increase. One approach is to increase the thickness of the epitaxial silicon layer6, wherein a thicker layer6allows a deeper drift region6ato support higher voltages without suffering breakdown. However, increasing the epitaxial thickness is costly in terms of process complexity, larger spacing requirements, and larger design rules, particularly in forming the deep diffusions to connect to the n-buried layer8or other buried layers in the device2. Accordingly, there is a need for improved DEPMOS devices and fabrication methods by which increased voltage breakdown withstanding capabilities can be achieved, without increasing epitaxial silicon thicknesses and without sacrificing device performance.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The present invention relates to an improved drain extended PMOS (DEPMOS) transistor that has an increased breakdown voltage.

According to one or more aspects of the present invention, a method of fabricating a drain-extended MOS transistor is disclosed. The method includes providing a p-type semiconductor body, forming an n-buried layer in the semiconductor body and forming a p-type upper epitaxial layer over the semiconductor body. A left N-WELL region is then formed in the p-type upper epitaxial layer, followed by a split P-WELL region which is also formed in the p-type upper epitaxial layer. A gate is then formed over the p-type upper epitaxial layer, and a p-type source region is formed in the left N-WELL region adjacent to a left side of the gate. Subsequently, a p-type drain region is formed in the p-type upper epitaxial layer between a left P-WELL region and a right P-WELL region of the split PWELL region in the p-type upper epitaxial layer. The p-type drain region is formed to a right side of the gate.

The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which principles of the invention may be employed.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The invention provides drain extended PMOS (DEPMOS) transistors and associated fabrication techniques by which various shortcomings of conventional DEPMOS transistors can be mitigated or overcome, and which may be employed to facilitate increased breakdown voltage ratings without increased epitaxial silicon thicknesses.

Referring now toFIG. 2, an exemplary DEPMOS transistor CT1ais illustrated in a semiconductor device102in accordance with one or more aspects of the present invention. The transistor CT1amay be employed in any type of circuit, and provides particular advantages in applications requiring high breakdown voltage withstanding capabilities, such as in the upper inverter transistor ofFIG. 1Bfor controlling the gate voltage G2of a high-side bridge driver transistor, for example. The device102is formed in a composite semiconductor body104,106, beginning with a p-doped silicon substrate104(P+), where a lower epitaxial silicon104a(P-lower epi) is formed over the substrate104, and a p-type upper epitaxial silicon106(upper epi) is formed over the lower EPI104a. The semiconductor devices and DEPMOS transistors of the present invention may be fabricated in any type of semiconductor body104, including but not limited to semiconductor (e.g., silicon) wafers, silicon-over-insulator (SOI) wafers, epitaxial layers in a wafer, or other composite semiconductor bodies, etc., wherein the invention and the appended claims are not limited to the illustrated structures or materials.

An n-buried layer108(NBL) extends into an upper portion of the lower EPI104aand a lower portion of the upper EPI106. In the illustrated example, left and right N-WELL regions112a,112bare formed in an upper portion of the upper EPI106. Various field oxide (FOX) isolation structures110a-110eare formed to separate different terminals of the transistor CT1afrom one another and from other components in the device102, although other isolation techniques may be used (e.g., shallow trench isolation (STI), local oxidation of silicon (LOCOS), etc.).

The exemplary DEPMOS transistor CT1acomprises a gate (G) having a thin gate dielectric114that underlies a conductive gate electrode116, where the gate114,116overlies a channel region128in the semiconductor body104and is abutted by a left sidewall spacer120aalong a left lateral side and a right sidewall spacer120balong a right lateral side. A p-type source (S)122is formed in the semiconductor body within left N-WELL region112a. Similarly, left and right n-type backgates (BG)126a,126bare formed within left and right N-WELL regions112a,112b, respectively. The source122has left and right laterally opposite sides, with the right lateral side located along a left lateral side of a channel128proximate the left lateral side of the gate, where the left opposite side of the source122is separated from the left backgate126aby isolation structure110b.

A split P-WELL having left and right regions130a,130bis also formed in an upper portion of the upper EPI106such that a p-type drain (D)124formed in the semiconductor body overlies a region125of upper EPI106that is abutted by the left and right P-WELL regions130a,130b. The channel region128underlying the gate114,116is thereby established within some of the left N-WELL region112aand some of the left split P-WELL region130a. The p-type drain (D)124is spaced from the right side of the gate114,116to provide an extended drain, wherein the n-buried layer108is situated in the upper and lower epitaxial silicon layers106,104abeneath at least a portion of the gate114,116and the drain124.

With regard to some of the dimensions of the features, a distance140between about the right side of the source122and about a left side of isolation structure110cis about 0.5 um and above. A distance142between about the left side of isolation structure110cand about the right side of isolation structure110cis between about 0.5 um and about 5 um. Similarly, a distance144between about the left side of the isolation structure110cand the right side of the gate structure114,116is between about 0.3 um and about 2 um. A distance146between about the left side of isolation structure110dand about a left side of the right N-WELL112bis between about 0.5 um and about 5 um. Likewise, a distance148between about the left side of the right N-WELL112band about a right side of isolation structure110dis between about 0.5 um and about 5 um. Also, a distance150between about a right side of the left P-WELL region130aand about the right side of isolation structure110cis between 0 um and about 1 um. Similarly a distance152between about the left side of the right P-WELL region130band about the left side of isolation structure110dis between about 0 um and about 1 um. As a final example, a distance154between about a right side of the left N-WELL region112aand about the left side of isolation structure110cis between about 0.3 um and about 1.5 um. It will be appreciated that the left and right P-WELL regions130a,130bmay diffuse laterally under the drain124by about distances150and152respectively as a result of annealing or heat treating, for example. In so doing, areas of the EPI region125corresponding to these distances150,152may have a slightly increased p dopant concentration, such as between about low E16 cm2and about mid E16 cm2, for example, where the left and right P-WELL regions130a,130bhave a p dopant concentration of about low E16 cm2and the upper EPI106has an p dopant concentration of about low E15 cm2, for example.

A transistor formed according to that which is disclosed herein has a breakdown voltage BVdss that is increased to around 40 volts as compared to a comparable conventional transistor that has a lesser breakdown voltage of around 40 volts. The breakdown voltage is increased as the left and right P-WELL regions130a,130band the EPI region125underlying the drain124facilitate more evenly distributed field (lines) between the drain124and the NBL108. In this manner, the transistor breakdown voltage BVdss is essentially decoupled to an extent from the epitaxial thickness, and the breakdown voltage can be increased without having to make the upper epitaxial silicon106thicker.

Turning toFIG. 3, an exemplary method202for fabricating a semiconductor device and DEPMOS transistor, such as that depicted inFIG. 2, is illustrated in accordance with one or more aspects of the present invention.FIGS. 4A-4Gsimilarly illustrate an exemplary semiconductor device, such as that depicted inFIG. 2, where the device is illustrated at various stages of fabrication that are generally in accordance with the method202ofFIG. 3. Although the exemplary method202is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the fabrication of devices and DEPMOS transistors thereof which are illustrated and described herein as well as in association with other devices and structures not illustrated.

As illustrated inFIGS. 3 and 4A, the method202begins at204, with an n-buried layer (NBL)108(e.g., of Antimony (Sb)) being initially implanted at206into the lower EPI layer104aof a semiconductor substrate104using an implant mask302and an implantation process304, where the n-buried layer may optionally be thermally diffused at208following the implantation process304. In the exemplary semiconductor device102, an n-buried layer108is initially implanted or diffused in a prospective DEPMOS portion of the lower epitaxial silicon104a. It will be appreciated that other n-buried layers (e.g., layer108ainFIG. 4A) may be concurrently formed for use in other transistors of the device102, wherein the implanted n-type impurities may, but need not, extend into the silicon104beneath the lower EPI layer104a. It will also be appreciated that any suitable processing techniques may be used in forming an n-buried layer in a semiconductor body within the scope of the invention, including but not limited to implantation, diffusion, etc., using any suitable implantation mask302, process304, and equipment.

By way of example, as with all layers described herein (unless specifically indicated otherwise), n-buried layer108can, at least partially, be formed via lithographic techniques, where lithography generally refers to processes for transferring one or more patterns between various media. In lithography, a radiation sensitive resist coating is formed over one or more layers which are to be treated in some manner, such as to be selectively doped and/or to have a pattern transferred thereto. The resist, which is sometimes referred to as a photoresist, is itself first patterned by exposing it to radiation, where the radiation (selectively) passes through an intervening mask or template containing the pattern. As a result, the exposed or unexposed areas of the resist coating become more or less soluble, depending on the type of resist used. A developer is then used to remove the more soluble areas of the resist leaving a patterned resist. The pattered resist can then serve as a mask for the underlying layers which can be selectively treated, such as to receive dopants and/or undergo etching.

Referring toFIG. 4B, an epitaxial growth process is performed at210to grow the upper epitaxial silicon layer106above the substrate104and the lower EPI104a, thereby forming a composite semiconductor body104,106, wherein the upper epitaxial silicon is provided with p-type dopants to form the p-type upper epitaxial silicon layer106. Any suitable epitaxial growth processing may be employed at210by which an epitaxial silicon layer106is formed over the upper surface of the lower EPI104a. In the illustrated example inFIG. 4B, the upper epitaxial silicon layer106is formed using an epitaxial growth process322, wherein the thermal energy associated with the process322causes some upward diffusion of the n-buried layers108and108ainto the upper epitaxial silicon106.

Referring toFIG. 4C, wherein NBL108is focused in on (e.g., to the exclusion of layer108a—as is also the case inFIGS. 4Dthru4G), left and right N-WELL regions112a,112bare formed at212via an implantation process323in the upper portion of the epitaxial silicon106, where the N-WELL regions112a,112bmay then be thermally diffused at214. Any suitable implant masking and implantation process may be employed at212to form the N-WELL regions112a,112b, such as using a patterned mask303and a Phosphorus (P) implant, for example.

FIG. 4Dillustrates that a split P-WELL implant325is then performed at216to form left and right P-WELL regions130a,130bin an upper portion of the upper EPI106. It will be appreciated that this implant establishes EPI region125between the left and right P-WELL regions130a,130b. The P-WELL regions130a,130bmay then be thermally diffused at218whereby p-type dopant may creep into region125by amounts150,152as illustrated inFIG. 2. It will be appreciated that any suitable implant masking and implantation process may be employed at216to form the split P-WELL regions130a,130b, such as using a patterned mask305and a Boron (B) implant, for example.

At220inFIG. 3, isolation structures110a-110eare then formed in the upper portion of the upper EPI layer106using any suitable techniques, such as local oxidation of silicon (LOCOS), shallow trench isolation techniques (STI), deposited oxide, etc. In the exemplary device102, field oxide (FOX) structures are formed as illustrated inFIG. 4E.

As illustrated inFIG. 4F, a thin gate oxide114is formed (e.g. at222in the method202) over the upper surface of the epitaxial layer106. The gate oxide114can be formed by any suitable material formation process, such as thermal oxidation processing, for example. At224, a gate polysilicon layer116is deposited over the thin gate oxide114, and is patterned at226to form a gate structure114,116extending over channel region128formed within part of the left N-WELL region112aand part of the left P-WELL region130a. With the patterned gate structure formed, LDD, MDD, or other drain extension implants (not shown) are performed at228, for example, including a shallow p-type implant to initially define the p-type source122, and left and right sidewall spacers120a,120bare formed at230along the left and right lateral sidewalls of the patterned gate structure114,116, respectively, as shown inFIG. 4F.

Referring toFIG. 4G, a p-type source/drain implant (e.g., of boron (B)) is then performed at232to further define the source (S)122within the left N-WELL region112a, as well as the drain (D)124in region125of the upper portion of the p-type upper epitaxial layer106. As illustrated inFIG. 4G, respective backgates (BG)126a,126bare implanted with n-type dopants (e.g., phosphorous (P), arsenic (As), antimony (Sb)) at234in the left and right N-WELL regions112a,112bwherein any suitable masks and implantation processes may be used in forming the p-type source122, the p-type drain124, and the n-type backgates126a,126b. Silicide, metalization, and/or other back-end processing (not shown) are then performed at236and238to complete the device102, after which the method202ends at240inFIG. 3.

Note that although the present examples provided herein are provided in the context of a device having two EPI regions with one or more buried layers formed after the lower EPI is formed, but before the upper EPI is formed, the above structure may be formed in the starting material using high energy implants. For example, the n-buried layer can be formed with high energy implants, and such variations are contemplated as falling within the scope of the present invention.