Three-dimensional integrated circuit and testing method for the same

Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.

TECHNICAL FIELD

The present invention relates to three-dimensional layering technology, and in particular to technology for testing connections between circuits.

BACKGROUND ART

The demand exists for further improvement in the degree of integration of semiconductor integrated circuits. However, reducing the size of semiconductors has almost reached a limit. Therefore, technology for layering a plurality of chips, i.e. three-dimensional layering technology, is being developed.

Three-dimensional layering technology mainly uses a TSV (Through Silicon Via) as wiring and a terminal to connect chips, i.e. as a connection between chips. A TSV is formed by etching a through-hole in a silicon substrate and filling the hole with conductive material such as copper. Typically, the diameter of a TSV is between several μm and several dozen μm, whereas the depth of a TSV is several hundred μm. Forming a large number of TSVs on a chip raises the density of the TSVs, making TSVs with a high aspect ratio (height/diameter) necessary. As the aspect ratio increases, it becomes more difficult to fill the TSV, and the occurrence of cavities referred to as “voids” becomes more common. A void degrades the conducting state of a TSV, hampering inter-chip connection through the TSV. Furthermore, since TSVs are a fine structure, it is difficult to accurately align TSVs when layering two chips. Accordingly, in order to confirm a proper connection through a TSV between layered chips, three-dimensional layering technology also requires technology for testing both the conducting state of a TSV itself and the TSV-chip conducting state. Additionally, to maintain a high yield of integrated circuits manufactured using three-dimensional layering technology (hereinafter referred to as “three-dimensional integrated circuits”), it is necessary to test the circuits implemented on each chip before layering a plurality of chips. Therefore, in order to improve the yield upon manufacturing three-dimensional integrated circuits, it is effective to perform a test on each chip before layering a plurality of chips (Pre-Bonding Test). After layering a plurality of chips, a test is performed on the plurality of layered chips (Post-Bonding Test), and at this point it is effective to perform both a test on each chip as well as a test on the TSVs connecting chips. As compared to tests for a single layer integrated circuit, tests for three-dimensional integrated circuits are therefore complex. As a result, in order to reduce the cost of manufacturing three-dimensional integrated circuits, it is necessary to improve the efficiency of these two types of tests and to reduce the number of steps involved.

DFT (Design for Testability) is a known technology for improving the efficiency of tests performed when manufacturing integrated circuits. DFT is technology that aims to make a test for an integrated circuit easy by incorporating a circuit necessary to perform the test into the integrated circuit in the design phase. The technology disclosed in Non-Patent Literature 1 is an example of DFT that targets three-dimensional integrated circuits. This technology is an extension of the standard DFT in IEEE 1149.1/4/6 to three-dimensional integrated circuits. Specifically, a test circuit, such as a TAM (Test Access Mechanism), a scan chain, a TDC (Test Data Compression), or a BIST (Built-In Self-Test), for testing circuits implemented on a chip is incorporated into each chip. A dedicated testing pad is also provided in each chip for accessing to the test circuit from an external source. Each chip is also provided with a dedicated terminal for receiving a test signal from another chip which lies below the level of the chip, and with a switch for selectively connecting the test circuit either the dedicated terminal or the dedicated testing pad. When several tests are performed on each chip before a plurality of chips is layered, the switch in each chip connects the test circuit with the dedicated testing pad. As a result, the external test signal is sent through the dedicated testing pad to the test circuit of each chip. On the other hand, when tests are performed on the layered chips after a plurality of chips is layered, the switch connects the test circuit in each chip to the dedicated terminal. As a result, a test signal is sent from the bottom substrate through the dedicated terminal between chips to the test circuit of each chip.

The three-dimensional integrated circuit disclosed in Patent Literature 1 is also known. In this three-dimensional integrated circuit, each chip is provided with a mounting terminal and a testing terminal. Each terminal is a TSV. The mounting terminal is connected to a circuit implemented on the chip. The testing terminal is separated from a circuit implemented on the chip. Upon layering a plurality of chips, the testing terminals of the chips form a transmission path for a testing signal. When a new chip is further layered on top of this group of chips, the mounting terminal of the new chip is connected to the testing terminals of the group of chips, and a test signal is sent to the new chip through the testing terminals. In this way, the circuits implemented on the new chip and the mounting terminal can be tested. If the test results indicate no defects in the circuits and the mounting terminal, the mounting terminal of the new chip is reconnected to the mounting terminals of the group of chips. It is thus possible to layer only chips without any defects.

Patent Literature 2 discloses the following integrated circuit. Two chips in the integrated circuit are connected to each other through a plurality of connection terminals by wire bonding. A test output control circuit is implemented on one of the chips, and an expected value judgment circuit is implemented on the other chip. The test output control circuit outputs test data to the plurality of connection terminals. The test data is set so that the logical level is flipped between two adjacent connection terminals. The expected value judgment circuit receives the test data from the plurality of connection terminals and judges whether each piece of received test data matches the test data output by the test output control circuit. The judgment results indicate not only whether any of the connection terminals is disconnected, but also whether any pair of adjacent connection terminals has short-circuited.

CITATION LIST

Patent Literature 1: Japanese Patent Application Publication No. 2004-281633

Patent Literature 2: Japanese Patent Application Publication No. 2009-288040

SUMMARY OF INVENTION

Technical Problem

The technology listed in Non-Patent Literature 1 is for series transmission of a test signal from the bottom to the top of a plurality of layered chips. Accordingly, as the number of layered chips increases, it becomes difficult to shorten the test time. Furthermore, a different test circuit is used for testing before and after layering the plurality of chips. This makes it difficult to reduce the overall area of the test circuits incorporated into the chips. Patent Literature 1 does not disclose a method for testing the connection of mounting terminals after layering of the plurality of chips. By contrast, Patent Literature 2 does not disclose a method for testing the connection terminals before layering of the plurality of chips. For a DFT that targets three-dimensional integrated circuits, method that can efficiently test the terminals connecting the chips both before and after layering of a plurality of chips is unknown.

The present invention has been conceived in light of the above problems, and is an object thereof to provide a three-dimensional integrated circuit that can efficiently test the terminals connecting the chips both before and after layering of a plurality of chips.

Solution to Problem

In a three-dimensional integrated circuit according to one aspect of the present invention, a plurality of chips is layered. Each of the plurality of chips is provided with a pair of connections, a test signal generation circuit and a test result judgment circuit. The pair of connections is electrically connected with an adjacent chip among the plurality of chips. The test signal generation circuit outputs a test signal to one of the pair of connections. The test result judgment circuit receives a signal from the other of the pair of connections, and detects the conducting state of the transmission path for the signal in accordance with the state of the signal.

A test method for a three-dimensional integrated circuit according to an aspect of the present invention comprises the following steps. First, a first connection and a second connection formed in a first chip are connected with a conductor to form a series connection of the first connection and the second connection. Next, a first test signal is transmitted from a first test signal generation circuit formed in the first chip to one end of the series connection, the first test signal is received from the other end of the series connection by a first test result judgment circuit formed in the first chip, and the conducting state of the series connection is detected in accordance with the state of the first test signal. The conductor is then removed from the series connection, the first chip is layered on the second chip, and the first chip is electrically connected to the second chip through the first connection and the second connection. Furthermore, a second test signal is transmitted from the first test signal generation circuit to the first connection, the second test signal is received from the first connection by a second test result judgment circuit formed in the second chip, and the conducting state between the first connection and the second chip is detected in accordance with the state of the second test signal. A third test signal is then transmitted from the second test signal generation circuit formed in the second chip to the second connection, the third test signal is received from the second connection by the first test result judgment circuit, and the conducting state between the second connection and the second chip is detected in accordance with the state of the third test signal.

Advantageous Effects of Invention

In the three-dimensional integrated circuit according to the above aspect of the present invention, one of the pair of connections provided in each chip is connected to the test signal generation circuit, and the other is connected to the test result judgment circuit. Therefore, before layering the chips, a series connection is formed by connecting the pair of connections with the conductor, and the conducting state of each of the connections is detected based on the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between chips is tested. In this way, both before and after layering a plurality of chips, the conducting state of the connections between a plurality of chips can be tested efficiently.

DESCRIPTION OF EMBODIMENTS

The following describes embodiments of the present invention with reference to the drawings.

FIG. 1is a schematic diagram illustrating the planar structure of a chip100according to Embodiment 1 of the present invention. As illustrated inFIG. 1, the chip100includes a plurality of core circuits11, a TSV region12, a pair of test circuit regions13, and a JTAG (Joint Test Action Group) interface14. The components11,12,13, and14are covered by interconnection layers, not shown inFIG. 1, that interconnects these components. The core circuits11achieve the functions of a CPU, memory array, DSP (Digital Signal Processor), PLD (Programmable Logic Device), random logic circuit, and the like. The TSV region12is a region in which a plurality of TSVs is located in a grid. Each TSV is connected to one of the core circuits11. When this chip100is layered on top of another chip, the core circuits11are electrically connected to the other chip through the TSVs. The test circuit regions13are located along either side of the TSV region12and include a plurality of test signal generation circuits, test result judgment circuits, and switch circuits. These circuits are used for detection of the conducting state of each TSV. The JTAG interface14conforms to IEEE 1149.1/4/6 and relays serial data between a DFT test circuit, such as a BIST (Built-In Self Test) circuit, and a device external to the chip100. Through the JTAG interface14, a functional test and a timing test of each of the core circuits11can be performed. Furthermore, the JTAG interface14allows an external device to instruct the test signal generation circuits in the test circuit regions13to generate test signals, to set the switch circuits in the test circuit regions13, and to read information on the conducting state of each TSV from the test result judgment circuits in the test circuit regions13.

FIG. 2is a schematic diagram illustrating the planar structure of the TSV region12and the test circuit regions13illustrated inFIG. 1. As illustrated inFIG. 2, a plurality of TSVs21is placed in two rows in the TSV region12. The diameter of each TSV21is several micrometers. The interval between each TSV21is several dozen micrometers. In each of the test circuit regions13, sets of a test signal generation circuit22, a test result judgment circuit23and a switch circuit24are located adjacent to a pair of TSVs21. The switch circuit24receives an instruction from an external device through the JTAG interface14and, in response to the instruction, connects one of the pair of TSVs21to the test signal generation circuit22and connects the other to the test result judgment circuit23.

FIG. 3is a schematic diagram illustrating a cross-section of the chip100near the TSV region. As illustrated inFIG. 3, this cross-section includes a substrate101, a first transistor110, a second transistor120, a first TSV131, a second TSV132, a first interlayer insulator140through a sixth interlayer insulator145, a first interconnection151, a second interconnection152, a first microbump171, and a second microbump172. The substrate101is formed from silicon. The transistors110and120are MOS (Metal Oxide Semiconductor) transistors. The transistors110and120are formed on the substrate101and include a first diffusion region111, a second diffusion region112, a gate oxide film113, a gate electrode114, and side walls115. The first diffusion region111and the second diffusion region112are regions doped with impurity ions in the substrate101. One of these regions is used as a drain, and the other is used as a source. When the transistor110is an N-type transistor, the diffusion regions111and112are doped with a donor impurity such as phosphor, whereas when the transistor110is a P-type transistor, the diffusion regions111and112are doped with an acceptor impurity such as boron. A gap is provided between the two diffusion regions111and112and is covered by the gate oxide film113. The gate oxide film113is formed from silicon oxide (SiO2) or from high-dielectric constant (High-k) material. The gate electrode114is formed on top of the gate oxide film113and is electrically isolated from the diffusion regions111and112by the gate oxide film113. The gate electrode114is formed from polysilicon or metallic material. The side walls115cover the gate oxide film113and the sides of the gate electrode114and in particular electrically isolate the gate electrode114from the diffusion regions111and112. The side walls115are formed from silicon nitride (Si3N4). The TSVs131and132have a structure including a hole that penetrates through the substrate101and is filled with conductive material. Polysilicon, copper, tungsten, aluminum, or nickel is used as the conductive material. The first interlayer insulator140covers the surface of the substrate101, the transistors110and112, and the TSVs131and132. The second interlayer insulator141through the sixth interlayer insulator145are layered in order on top of the first interlayer insulator140. Each of the interlayer insulators140-145is formed from silicon oxide or from low-dielectric constant (Low-k) material. An aluminum or copper pattern is formed in each of the second interlayer insulator141through the sixth interlayer insulator145, and together the patterns form the interconnections151and152. In the first interlayer insulator140, a first contact hole160through fourth contact hole163are formed. The first contact hole160exposes the gate electrode114of the first transistor110. The second contact hole161exposes an end of the first TSV131. The third contact hole162exposes an end of the second TSV132. The fourth contact hole163exposes the gate electrode of the second transistor120. The first interconnection151passes through the first contact hole161to connect with the gate electrode114of the first transistor110and passes through the second contact hole161to connect with the first TSV131. The second interconnection152passes through the third contact hole162to connect with the second TSV132and passes through the fourth contact hole163to connect with the gate electrode of the second transistor120. The first and second interconnections,151and152, are isolated from each other, and therefore the first and the second TSVs,131and132, are isolated from each other. A plurality of transistors, the same as the transistors110and120, are combined to form the core circuits11illustrated inFIG. 1and the test signal generation circuit22, the test result judgment circuit23, and the switch circuit24illustrated inFIG. 2. While the transistors110and120are implemented on one surface of the substrate101, the microbumps171and172are implemented on the opposite surface of the substrate101; the microbumps171and172are formed from copper or aluminum. The first microbump171is connected to the tip of the first TSV131, and the second microbump172is connected to the tip of the second TSV132.

FIG. 4is a block diagram of four adjacent TSVs201-204in the TSV region12and of their surrounding circuits. As illustrated inFIG. 4, the surrounding circuits include a first test signal generation circuit211, a second test signal generation circuit212, a first test result judgment circuit221, a second test result judgment circuit222, a first switch circuit231, and a second switch circuit232. The test signal generation circuits211and212are instructed by an external device through the JTAG interface14, to begin generating a test signal. The first test signal generation circuit211generates a test signal in response to the instruction and outputs the test signal to the first switch circuit231. The second test signal generation circuit212generates a test signal in response to the above instruction and outputs the test signal to the second switch circuit232. The test result judgment circuits221and222store patterns of test signals in advance. The test result judgment circuits221and222are instructed by an external device through the JTAG interface14, or by the test signal generation circuits211and212, to begin judging the pattern of the test signal. In response to the instruction, the first test result judgment circuit221receives the signal from the first switch circuit231and judges whether the pattern of the signal matches the pattern of the test signal. In response to the above instruction, the second test result judgment circuit222receives the signal from the second switch circuit232and judges whether the pattern of the signal matches the pattern of the test signal. The results of judgment by the test result judgment circuits221and222represent the conducting state of the transmission path for the test signal. Information on the results of judgment is transmitted from each of the test result judgment circuits221and222to an external device through the JTAG interface14. The first switch circuit231connects each of the first test signal generation circuit211and the first test result judgment circuit221to either one of the first TSV201and the second TSV202. The second switch circuit232connects each of the second test signal generation circuit212and the second test result judgment circuit222to either one of the third TSV203and the fourth TSV204. The switch circuits231and232select a destination in response to an instruction received from an external device through the JTAG interface14.

First Connection Test

FIG. 5is a cross-section diagram illustrating conditions during a connection test between the pair of TSVs131and132in the chip100illustrated inFIG. 3. In this connection test, the conducting state of the pair of TSVs131and132is tested. Hereinafter, this connection test is referred to as the “first connection test”. As illustrated inFIG. 5, during the first connection test, a test support substrate300is mounted on a surface of the substrate101; on the opposite surface thereof the transistors110and120are implemented (i.e. the opposite surface is the circuit side). The test support substrate300includes an insulating plate301, an insulator302and a testing wire303. The insulating plate301is formed from silicon. The insulator302is formed from silicon oxide and covers the surface of the insulating plate301facing the chip100. The testing wire303is a copper, aluminum, or other-metal pattern layered on a portion of the insulator302. When the test support substrate300is mounted on the surface of the chip100, the pair of adjacent TSVs131and132is connected by the testing wire303which is connected with the two microbumps171and172.

Instead of silicon, the insulating plate301may be formed from epoxy resin, glass epoxy resin, or ceramic resin. In this case, the testing wire303may be formed directly on the insulating plate301, without forming the insulator302.

FIGS. 6A and 6Bare schematic diagrams illustrating conditions during the first connection test on the four TSVs201-204illustrated inFIG. 4. During the first connection test, the test support substrate is mounted on a chip. As a result, among the four TSVs201-204arranged in a grid, each pair of either vertically or horizontally adjacent TSVs is connected by the testing wire.

FIG. 6Ais a schematic diagram illustrating conditions when each pair of horizontally adjacent TSVs is connected by a testing wire. As illustrated inFIG. 6A, the first TSV201and the third TSV203are connected by a first testing wire401, whereas the second TSV202and the fourth TSV204are connected by a second testing wire402. The first switch circuit231connects the first test signal generation circuit211with the first TSV201and connects the first test result judgment circuit221with the second TSV202. On the other hand, the second switch circuit232connects the second test signal generation circuit212with the fourth TSV204and connects the second test result judgment circuit222with the third TSV203. As a result, the test signal output by the first test signal generation circuit211passes through the first switch circuit231, the first TSV201, the first testing wire401, the third TSV203, and the second switch circuit232, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the third TSV203. On the other hand, the test signal output by the second test signal generation circuit212passes through the second switch circuit232, the fourth TSV204, the second testing wire402, the second TSV202, and the first switch circuit231, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the second TSV202or the fourth TSV204.

FIG. 6Bis a schematic diagram illustrating conditions when each pair of vertically adjacent TSVs is connected by a testing wire. As illustrated inFIG. 6B, the first TSV201and the second TSV202are connected by the third testing wire403, whereas the third TSV203and the fourth TSV204are connected by the fourth testing wire404. The first switch circuit231connects the first test signal generation circuit211with the first TSV201and connects the first test result judgment circuit221with the second TSV202. On the other hand, the second switch circuit232connects the second test signal generation circuit212with the fourth TSV204and connects the second test result judgment circuit222with the third TSV203. As a result, the test signal output by the first test signal generation circuit211passes through the first switch circuit231, the first TSV201, the third testing wire403, the second TSV202, and the first switch circuit231, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the second TSV202. On the other hand, the test signal output by the second test signal generation circuit212passes through the second switch circuit232, the fourth TSV204, the fourth testing wire404, the third TSV203, and the second switch circuit232, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the third TSV203or the fourth TSV204.

The first connection test may be performed at the point which a plurality of chips are formed on one wafer (wafer level), or at the point which each chip is cut off the wafer (die level). When performing the first connection test at the die level, however, it is necessary to decrease the size of the test support substrate to approximately the same size as the chip. It is also necessary to mount the test support substrate on chips one at a time. For these reasons, it is more efficient to perform the first connection test at the wafer level.

Second Connection Test

FIG. 7is a cross-sectional diagram illustrating conditions when performing a connection test on a pair of TSVs131and132after layering the chip100illustrated inFIG. 3(hereinafter referred to as the “first chip”) on another chip500(hereinafter referred to as the “second chip”). Hereinafter, this connection test is referred to as the “second connection test”. As illustrated inFIG. 7, in the pair of chips according to Embodiment 1, the surface of an insulator545farthest towards the outside in the second chip (i.e. the circuit side) faces the surface of the substrate101in the first chip100. The first chip100and the second chip500may have core circuits with different functions or structures, or may have core circuits with the same functions and structures. In the second connection test, the conducting state of each pair of TSVs131and132is tested individually.

As illustrated inFIG. 7, the same as the first chip100, the second chip500includes a substrate501, a third transistor510, a fourth transistor520, a fifth TSV531, a sixth TSV532, interlayer insulator540-545, third interconnection551, and fourth interconnection552. The substrate501is formed from silicon. The transistors510and520are MOS transistors formed on the substrate101and include a first diffusion region511, a second diffusion region512, a gate oxide film513, a gate electrode514, and side walls515. Each of these components is the same as in the transistors110and120formed on the first chip100. The TSVs531and532have a structure including a hole that penetrates through the substrate501and is filled with conductive material. Polysilicon, copper, tungsten, aluminum, or nickel is used as the conductive material. The interlayer insulators540-545cover the surface of the second chip500and are formed like the interlayer insulators140-145covering the first chip100. An aluminum or copper pattern is formed on each of the interlayer insulators541-545, and together the patterns form the interconnections551and552. In the lowest interlayer insulator540, a fifth contact hole560through eighth contact hole563are formed. The fifth contact hole560exposes the gate electrode514of the third transistor510. The sixth contact hole561exposes an end of the third TSV531. The seventh contact hole562exposes an end of the fourth TSV532. The eighth contact hole563exposes the gate electrode of the fourth transistor520. The third interconnection551is connected through the fifth contact hole561to the gate electrode514of the third transistor510and connected through the sixth contact hole561to the third TSV531. The fourth interconnection552is connected through the seventh contact hole562to the fourth TSV532and connected through the eighth contact hole563to the gate electrode of the fourth transistor520. In the second chip500as well, a plurality of transistors, the same as the transistors510and520, are combined to form the core circuits11illustrated inFIG. 1and the test signal generation circuit22, the test result judgment circuit23, and the switch circuit24illustrated inFIG. 2.

As further illustrated inFIG. 7, between the first chip100and the second chip500, the first TSV131and the third interconnection551are connected by the first microbump171, and the second TSV132and the fourth interconnection552are connected by the second microbump172. As a result, the first TSV131is connected to the third TSV531, and the second TSV132is connected to the fourth TSV532. Furthermore, through the first TSV131and the second TSV132, the test signal generation circuits, test result judgment circuits, and switch circuits implemented on the first chip100are connected to the test signal generation circuits, test result judgment circuits, and switch circuits implemented on the second chip500. With the chips in this state, the second connection test is performed.

FIGS. 8A and 8Bare schematic diagrams illustrating conditions during the second connection test with the chips601and602layered as illustrated inFIG. 7.FIG. 8Ais a block diagram of four TSVs and their surrounding circuits in the upper chip601(hereinafter referred to as the “first chip”), andFIG. 8Bis a block diagram of four TSVs and their surrounding circuits in the lower chip602(hereinafter referred to as the “second chip”). The same as the four TSVs illustrated inFIG. 4, four TSVs611-614and621-624are adjacent to each other in the respective chips601and602, and are connected to different interconnections. Furthermore, between the first chip601and the second chip602, like the third interconnection551and the fourth interconnection552illustrated inFIG. 7, interconnections formed on the second chip602are connected to pairs of TSVs that are adjacent along a normal line between the chips601and602. Specifically, as indicated by the dashed lines inFIGS. 8A and 8B, a first TSV611and a fifth TSV621are connected, a second TSV612and a sixth TSV622are connected, a third TSV613and a seventh TSV623are connected, and a fourth TSV614and an eighth TSV624are connected.

The first chip601includes a first test signal generation circuit631, a second test signal generation circuit632, a first test result judgment circuit641, a second test result judgment circuit642, a first switch circuit651, and a second switch circuit652. The second chip602includes a third test signal generation circuit633, a fourth test signal generation circuit634, a third test result judgment circuit643, a fourth test result judgment circuit644, a third switch circuit653, and a fourth switch circuit654. The test signal generation circuits631-634are instructed by an external device through a JTAG interface, to begin generating a test signal. The test signal generation circuits631-634generate a test signal in response to the instruction and output the test signal to the TSVs611-614and621-624. The test result judgment circuits641-644store patterns of test signals in advance. The test result judgment circuits641-644are instructed by an external device through the JTAG interface, or by the test signal generation circuits631-634, to begin judging the pattern of the test signal. In response to the instruction, the test result judgment circuits641-644receive the signal from the TSVs611-614and621-624and judge whether the pattern of the signal matches the pattern of the test signal. The first switch circuit651connects each of the first test signal generation circuit631and the first test result judgment circuit641to either one of the first TSV611and the second TSV612. The second switch circuit652connects each of the second test signal generation circuit632and the second test result judgment circuit642to either one of the third TSV613and the fourth TSV614. The third switch circuit653connects each of the third test signal generation circuit633and the third test result judgment circuit643to either one of the fifth TSV621and the sixth TSV622. The fourth switch circuit654connects each of the fourth test signal generation circuit634and the fourth test result judgment circuit644to either one of the seventh TSV623and the eighth TSV624. The switch circuits651-654select a destination in response to an instruction received from an external device through the JTAG interface.

While not illustrated inFIGS. 8A and 8B, core circuits with a variety of functions are implemented on the chips601and602. The TSVs611-614and621-624are connected to the respective core circuits. The chips601and602may also include test circuits such as BIST circuits.

During the second connection test, the switch circuits651-654are set as illustrated inFIGS. 8A and 8B. Specifically, as illustrated inFIG. 8A, the first switch circuit651connects the first test signal generation circuit631with the first TSV611and connects the first test result judgment circuit641with the second TSV612. On the other hand, the second switch circuit652connects the second test signal generation circuit632with the fourth TSV614and connects the second test result judgment circuit642with the third TSV613. As illustrated inFIG. 8B, the third switch circuit653connects the third test signal generation circuit633with the sixth TSV622and connects the third test result judgment circuit643with the fifth TSV621. On the other hand, the fourth switch circuit654connects the fourth test signal generation circuit634with the seventh TSV623and connects the fourth test result judgment circuit644with the eighth TSV624.

The test signal output by the first test signal generation circuit631passes through the first switch circuit651, the first TSV611, and the third switch circuit653, and then the test signal is received by the third test result judgment circuit643. The third test result judgment circuit643compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the first TSV611and the second chip602due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the second test signal generation circuit632passes through the second switch circuit652, the fourth TSV614, and the fourth switch circuit654, and then the test signal is received by the fourth test result judgment circuit644. The fourth test result judgment circuit644compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the fourth TSV614and the second chip602due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the third test signal generation circuit633passes through the third switch circuit653, the second TSV612, and the first switch circuit651, and then the test signal is received by the first test result judgment circuit641. The first test result judgment circuit641compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second TSV612and the second chip602due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the fourth test signal generation circuit634passes through the fourth switch circuit654, the third TSV613, and the second switch circuit652, and then the test signal is received by the second test result judgment circuit642. The second test result judgment circuit642compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the third TSV613and the second chip602due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

FIGS. 9A,9B, and9C are schematic diagrams illustrating conditions during the second connection test with chips701,702, and703layered.FIG. 9Ais a block diagram of four TSVs and their surrounding circuits in the uppermost chip701(hereinafter referred to as the “first chip”),FIG. 9Bis a block diagram of four TSVs and their surrounding circuits in the middle chip702(hereinafter referred to as the “second chip”), andFIG. 9Cis a block diagram of four TSVs and their surrounding circuits in the lowest chip703(hereinafter referred to as the “third chip”). The same as the four TSVs illustrated inFIG. 4, four TSVs711-714,721-724, and731-734are adjacent to each other in the respective chips701-703, and are connected to different interconnections. Furthermore, between the first chip701and the second chip702, interconnections formed on the second chip702are connected to pairs of TSVs that are adjacent along a normal line between the chips701and702. Specifically, as indicated by the dashed lines inFIGS. 9A,9B, and9C, a first TSV711and a fifth TSV721are connected, a second TSV712and a sixth TSV722are connected, a third TSV713and a seventh TSV723are connected, and a fourth TSV714and an eighth TSV724are connected. Similarly, between the second chip702and the third chip703, interconnections formed on the third chip703are connected pairs of TSVs that are adjacent along a normal line between the chips702and703. Specifically, as indicated by the dashed lines inFIGS. 9A,9B, and9C, the fifth TSV721and a ninth TSV731are connected, the sixth TSV722and a tenth TSV732are connected, the seventh TSV723and an eleventh TSV733are connected, and the eighth TSV724and a twelfth TSV734are connected.

Like the chips601and602illustrated inFIGS. 8A and 8B, a group of a test signal generation circuit, a test result judgment circuit, and a switch circuit is connected to each pair of adjacent TSVs in the chips701-703. The test signal generation circuits are instructed by an external device through a JTAG interface, to begin generating a test signal. The test signal generation circuits generate a test signal in response to the instruction and output the test signal to the TSVs. The test result judgment circuits are instructed by an external device through the JTAG interface, or by the test signal generation circuits, to begin judging the pattern of the test signal. In response to the instruction, the test result judgment circuits receive the signal from the TSVs and judge whether the pattern of the signal matches the pattern of the test signal. The switch circuits connect each of the test signal generation circuits and the test result judgment circuits to either one of a pair of TSVs. The destination is selected in response to an instruction received from an external device through the JTAG interface.

During the second connection test, the switch circuits are set as shown inFIGS. 9A,9B, and9C. Specifically, in the first chip701, as illustrated inFIG. 9A, a first switch circuit761connects a first test signal generation circuit741with the first TSV711and connects a first test result judgment circuit751with the second TSV712. On the other hand, a second switch circuit762connects a second test signal generation circuit742with the fourth TSV714and connects a second test result judgment circuit752with the third TSV713. In the second chip702, as illustrated inFIG. 9B, a third switch circuit763isolates both a third test signal generation circuit743and a third test result judgment circuit753from the fifth TSV721and the sixth TSV722. Similarly, a fourth switch circuit764isolates both a fourth test signal generation circuit744and a fourth test result judgment circuit754from the seventh TSV723and the eighth TSV724. In the third chip703, as illustrated inFIG. 9C, a fifth switch circuit765connects a fifth test signal generation circuit745with the tenth TSV732and connects a fifth test result judgment circuit755with the ninth TSV731. On the other hand, the sixth switch circuit766connects a sixth test signal generation circuit746with the eleventh TSV733and connects a sixth test result judgment circuit756with the twelfth TSV734.

The test signal output by the first test signal generation circuit741passes through the first switch circuit761, the first TSV711, the fifth TSV721, and the fifth switch circuit765, and then the test signal is received by the fifth test result judgment circuit755. The fifth test result judgment circuit755compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the first TSV711and the second chip702, or between the fifth TSV721and the third chip703, due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the second test signal generation circuit742passes through the second switch circuit762, the fourth TSV714, the eighth TSV724, and the sixth switch circuit766, and then the test signal is received by the sixth test result judgment circuit756. The sixth test result judgment circuit756compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the fourth TSV714and the second chip702, or between the eighth TSV724and the third chip703, due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the fifth test signal generation circuit745passes through the fifth switch circuit765, the sixth TSV722, the second TSV712, and the first switch circuit761, and then the test signal is received by the first test result judgment circuit751. The first test result judgment circuit751compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second TSV712and the second chip702, or between the sixth TSV722and the third chip703, due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the sixth test signal generation circuit746passes through the sixth switch circuit766, the seventh TSV723, the third TSV713, and the second switch circuit762, and then the test signal is received by the second test result judgment circuit752. The second test result judgment circuit752compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the third TSV713and the second chip702, or between the seventh TSV723and the third chip703, due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

As has been described, in the three-dimensional integrated circuit according to Embodiment 1 of the present invention, each chip is provided with a set of a test signal generation circuit, a test result judgment circuit, and a switch circuit for each pair of TSVs. The switch circuit connects one of the corresponding TSV pair to the test signal generation circuit and connects the other to the test result judgment circuit. As a result, before layering a plurality of chips, it is possible to detect the conducting state of two TSVs by connecting the TSVs together. On the other hand, after layering the plurality of chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal; this enables the conducting state of TSVs between the chips to be detected. In this way, both before and after layering a plurality of chips, the same test circuits can be used to test the TSVs that connect the plurality of chips. Using the same test circuits improves the efficiency of testing.

Method of Manufacturing Three-Dimensional Integrated Circuits

FIG. 10is a flowchart of the method of manufacturing three-dimensional integrated circuits according to Embodiment 1 of the present invention. In this method of manufacturing, the first connection test is first performed on individual chips. The first connection test may be performed at either the wafer level or the die level. Next, chips that passed the first connection test are layered, and the second connection test is performed. At this point, the layering may be either of the following two forms. In the first form (Die to Die), two chips to be layered are cut off from the wafer and then layered. In the other form (Die to Wafer), a chip already cutt off from the wafer is layered onto a chip not yet cut off from the wafer.

In step S801, a plurality of chips to be layered is manufactured. The chips may be manufactured in parallel. For example, the structure illustrated inFIG. 1is formed on a substrate101. A plurality of chips to be layered may have core circuits with different functions or structures, or may have core circuits with the same functions and structures. Thereafter, processing proceeds to step S802.

In step S802, tests are performed on the circuits implemented on each chip. These tests include a functional test and the timing test and are performed by using a test circuit, such as a BIST circuit implemented on the chip using DFT. Thereafter, processing proceeds to step S803.

In step S803, it is determined whether the test results are normal or not. If the test results are normal, processing proceeds to step S804. Otherwise, processing proceeds to step S811.

In step S804, as illustrated inFIG. 5, a test support substrate is mounted onto the chip to connect a pair of TSVs connected to different interconnections. Thereafter, processing proceeds to step S805.

In step S805, the first connection test is performed individually on each chip. Specifically, as illustrated inFIGS. 6A and 6B, each switch circuit connects one of the pair of TSVs, which are connected by the testing wire, to the test signal generation circuit and connects the other to the test result judgment circuit. Next, the test signal generation circuits are instructed by an external device through the JTAG interface, to begin generating a test signal. The test signal generation circuits generate a test signal in response to the instruction and output the test signal to the TSVs. Furthermore, the test result judgment circuits are instructed by an external device through the JTAG interface, or by the test signal generation circuits, to begin judging the pattern of the test signal. In response to the instruction, each test result judgment circuit receives the signal from the TSV connected thereto by the switch circuit. Thereafter, processing proceeds to step S806.

In step S806, each test result judgment circuit compares the pattern of the received signal with the pattern of the test signal. If the pattern of each signal matches the pattern of the test signal, neither of the TSVs in the pair of TSVs that transmitted the signals has a connection fault due to a void. Processing therefore proceeds to step S807. If the pattern of each signal does not match the pattern of the test signal, one of the TSVs in the pair of TSVs that transmitted the signals has a connection fault due to a void. Processing therefore proceeds to step S811.

In step S807, the chips that passed the first connection test are layered onto other chips. The form of layering may be either Die to Die or Die to Wafer. As a result, as illustrated inFIG. 7, the TSVs in the upper chip are connected to the interconnections in the lower chip. Thereafter, processing proceeds to step S808.

In step S808, the second connection test is performed on the entire set of layered chips. Specifically, as illustrated inFIGS. 8A and 8B, the TSVs connecting two chips are each connected to the test signal generation circuit in one chip or the test result judgment circuit in the other chip. Next, the test signal generation circuits are instructed by an external device through the JTAG interface, to begin generating a test signal. The test signal generation circuits generate a test signal in response to the instruction and output the test signal to the TSVs. Furthermore, the test result judgment circuits are instructed by an external device through the JTAG interface or by the test signal generation circuits, to begin judging the pattern of the test signal. In response to the instruction, each test result judgment circuit receives the signal from the TSV connected thereto. Thereafter, processing proceeds to step S809.

In step S809, the test result judgment circuits compare the pattern of the received signal with the pattern of the test signal. If the pattern of the signal matches the pattern of the test signal, no connection fault has occurred between the TSV that transmitted the signal and the chip due to misalignment of a TSV, a junction fault at a microbump, or another such reason. If there is no connection fault in any of the TSVs connecting the chips, processing proceeds to step S810. If a connection fault has occurred in any of the TSVs, processing proceeds to step S811.

In step S810, since the layered chips and all the TSVs connecting the chips are normal, the chips are packaged as one three-dimensional integrated circuit. The three-dimensional integrated circuit according to Embodiment 1 of the present invention is thus complete.

In step S811, either a chip or a TSV is defective. Therefore, either an individual chip or an entire set of layered chips is screened as defective and discarded.

Modifications

(A) The TSVs illustrated inFIGS. 1 and 2are placed in a grid in the central region of the chip100. Alternatively, the TSVs may be placed at any other location in the chip. Furthermore, the circuit layout within the test circuit regions13illustrated inFIG. 2is only an example. As long as the group of the test signal generation circuit22, the test result judgment circuit23, and the switch circuit24is placed adjacent to a pair of TSVs21, the relative positions of these circuits may be freely modified. Additionally, inFIG. 4, the switch circuits231and232are connected to two vertically adjacent TSVs (201,202) and (203,204). The switch circuits231and232may instead be connected to two horizontally adjacent TSVs (201,203) and (202,204).

(B) During the first connection test, as illustrated inFIG. 5, two adjacent TSVs are connected by a testing wire. As a result, the lengths of the wires between the TSV region and the test circuit region, as well as the length of the testing wire, are reduced to the necessary minimum. Alternatively, two TSVs placed distant from each other may be connected like the pairs of TSVs illustrated inFIGS. 6A and 6B.

(C) InFIG. 7, the first TSV131and the third interconnection551are connected by the first microbump171, whereas the second TSV132and the fourth interconnection552are connected by the second microbump172. Alternatively, the first TSV131may be connected to the third interconnection551without the microbump, and the second TSV132may be connected to the fourth interconnection552without the microbump. Furthermore, an interposer may be inserted between the microbump and the interconnection layer of the lower chip, and the microbump may be connected to the interconnection layer of the lower chip by wires formed on the surface of the interposer.

(D) InFIG. 7, the substrate of the upper chip is connected to the interconnection layer of the lower chip. Alternatively, by flipping the top and bottom of the lower chip, the substrate of the upper chip may be connected to the substrate of the lower chip.

(E) In the flowchart illustrated inFIG. 10, after the functional test and the timing test performed in step S802, the first connection test is performed in step S805. Alternatively, the first connection test may be performed in parallel with the functional test and the timing test. This approach shortens the test time.

(F) In the flowchart illustrated inFIG. 10, in step S808, only the second connection test is performed on the entire set of layered chips. Alternatively, as in step S802, the functional test and the timing test may be performed on the circuits implemented on each chip. This approach allows for confirmation of whether layering of the chips has caused a defect to occur in circuitry other than the TSVs. Furthermore, these tests may be performed in parallel with the second connection test. This approach shortens the test time.

(G) In the flowchart illustrated inFIG. 10, in steps S806and S809, a chip is screened as defective if a connection fault occurs in any of the TSVs. Alternatively, a spare TSV referred to as a redundancy relief TSV may be provided in advance on the chip, and if a connection fault occurs in one of the TSVs, the redundancy relief TSV may be used in place of the TSV with a connection fault. This approach maintains a high chip yield.

Chips according to Embodiment 2 of the present invention differ from chips according to Embodiment 1 in that the test circuit region does not include a switch circuit. Other elements of the chips according to Embodiment 2 are similar to those of the chips according to Embodiment 1. Details on similar elements can be found in the description of Embodiment 1.

FIG. 11is a schematic diagram illustrating the planar structure of a TSV region12and of test circuit regions13L and13R in the chips of Embodiment 2. As illustrated inFIG. 11, a plurality of TSVs21is placed in two rows in the TSV region12. The diameter of each TSV21is several micrometers. The interval between each TSV21is several dozen micrometers. In the test circuit regions13L and13R, a pair of a test signal generation circuit22and a test result judgment circuit23is adjacent to each pair of TSVs21. Furthermore, with respect to the TSV region12, the placed order of the test signal generation circuits22and the test result judgment circuits23is reversed between the test circuit region13L on the left and the test circuit region13R on the right. As a result, as illustrated inFIG. 11, the test signal generation circuits22and the test result judgment circuits23are placed in a zigzag lattice pattern, with the TSV region12therebetween. Each test signal generation circuit22thus faces a test result judgment circuit23in another test circuit region, with the TSV region12therebetween.

FIG. 12is a block diagram of four adjacent TSVs201-204in the TSV region12and of their surrounding circuits. As illustrated inFIG. 12, the surrounding circuits include the first test signal generation circuit211, the second test signal generation circuit212, the first test result judgment circuit221, and the second test result judgment circuit222. The first test signal generation circuit211is connected to the first TSV201. The first test result judgment circuit221is connected to the second TSV202. The second test signal generation circuit212is connected to the fourth TSV204. The second test result judgment circuit222is connected to the third TSV203. The test signal generation circuits211and212are instructed by an external device through the JTAG interface14, to begin generating a test signal. The first test signal generation circuit211generates a test signal in response to the instruction and outputs the test signal to the first TSV201. The second test signal generation circuit212generates a test signal in response to the instruction and outputs the test signal to the fourth TSV204. The test result judgment circuits221and222store patterns of test signals in advance. The test result judgment circuits221and222are instructed by an external device through the JTAG interface14, or by the test signal generation circuits211and212, to begin judging the pattern of the test signal. In response to the instruction, the first test result judgment circuit221receives the signal from the second TSV202and judges whether the pattern of the signal matches the pattern of the test signal. In response to the instruction, the second test result judgment circuit222receives the signal from the third TSV203and judges whether the pattern of the signal matches the pattern of the test signal. The results of judgment by the test result judgment circuits221and222represent the conducting state of the transmission paths for the test signals. Information on the results of judgment is transmitted from each of the test result judgment circuits221and222to an external device through the JTAG interface14.

First Connection Test

During the first connection test, as illustrated inFIG. 5, a test support substrate is mounted onto the chip. As a result, as illustrated inFIGS. 6A and 6B, among the four TSVs201-204, each pair of either vertically or horizontally adjacent TSVs is connected by the testing wire.

As illustrated inFIG. 6A, when two horizontally adjacent TSVs are connected by the testing wire, the test signal output by the first test signal generation circuit211passes through the first TSV201, the first testing wire401, and the third TSV203to be received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the results of comparison, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the third TSV203. On the other hand, the test signal output by the second test signal generation circuit212passes through the fourth TSV204, the second testing wire402, and the second TSV202, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the second TSV202or the fourth TSV204.

As illustrated inFIG. 6B, when two vertically adjacent TSVs are connected by the testing wire, the test signal output by the first test signal generation circuit211passes through the first TSV201, the third testing wire403, and the second TSV202, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the second TSV202. On the other hand, the test signal output by the second test signal generation circuit212passes through the fourth TSV204, the fourth testing wire404, and the third TSV203, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the third TSV203or the fourth TSV204.

Second Connection Test

FIG. 13is a cross-sectional diagram illustrating conditions when performing the second connection test on two pairs of TSVs131,132and531,532, after layering the first chip100illustrated inFIG. 12on the second chip500. The first chip100and the second chip500may have core circuits with different functions or structures, or may have core circuits with the same functions and structures. As illustrated inFIG. 13, unlike the pair of chips according to Embodiment 1 illustrated inFIG. 7, the top and bottom of the second chip500are flipped in the pair of chips according to Embodiment 2, so that the surface of the substrate501of the second chip faces the surface of the substrate101of the first chip100. The remaining structure of the pair of chips according to Embodiment 2 is similar to the pair of chips according to Embodiment 1 illustrated inFIG. 7. Details on this similar structure can be found in the description of Embodiment 1.

As further illustrated inFIG. 13, the first microbump171and the second microbump172are formed on the surface of the substrate101of the first chip100in the gap between the first chip100and second chip500. A third microbump571and a fourth microbump572are formed on the surface of the substrate501of the second chip500. When the first chip100is placed on top of the second chip500, the first TSV131and the third TSV531are connected by the first microbump171and the third microbump571, whereas the second TSV132and the fourth TSV532are connected by the second microbump172and the fourth microbump572. As a result, the test signal generation circuit and the test result judgment circuit implemented on the first chip100are connected to the test signal generation circuit and the test result judgment circuit implemented on the second chip500through the four TSVs131,132,531, and532and the four microbumps171,172,571, and572. With the chips in this state, the second connection test is performed.

FIGS. 14A and 14Bare schematic diagrams illustrating conditions when performing the second connection test on chips901and902layered as illustrated inFIG. 13.FIG. 14Ais a block diagram of four TSVs and their surrounding circuits in the upper chip901(hereinafter referred to as the “first chip”), andFIG. 14Bis a block diagram of four TSVs and their surrounding circuits in the lower chip902(hereinafter referred to as the “second chip”). The same as the four TSVs illustrated inFIG. 4, four TSVs611-614and621-624are adjacent to each other in the respective chips901and902, and are connected by different interconnections. Furthermore, between the first chip901and the second chip902, as illustrated inFIG. 13, four microbumps171,172,571, and572are connected two by two to connect TSVs that are adjacent along a normal line between the chips901and902. As a result, as indicated by the dashed lines inFIGS. 14A and 14B, the first TSV611and the sixth TSV622are connected, the second TSV612and the fifth TSV621are connected, the third TSV613and the eighth TSV624are connected, and the fourth TSV614and the seventh TSV623are connected.

The first chip901includes the first test signal generation circuit631, the second test signal generation circuit632, the first test result judgment circuit641, and the second test result judgment circuit642. The second chip902includes the third test signal generation circuit633, the fourth test signal generation circuit634, the third test result judgment circuit643, and the fourth test result judgment circuit644. The test signal generation circuits631-634are instructed by an external device through a JTAG interface, to begin generating a test signal. The test signal generation circuits631-634generate a test signal in response to the instruction and output the test signal to the TSVs611,614,621, and624connected to the test signal generation circuits631-634. The test result judgment circuits641-644store patterns of test signals in advance. The test result judgment circuits641-644are instructed by an external device through the JTAG interface, or by the test signal generation circuits631-634, to begin judging the pattern of the test signal. In response to the instruction, the test result judgment circuits641-644receive the signal from the TSVs612,613,622, and623connected to the test result judgment circuits641-644and judge whether the pattern of the signal matches the pattern of the test signal.

While not illustrated inFIGS. 14A and 14B, core circuits with a variety of functions are implemented on the chips901and902. The TSVs611-614and621-624are connected to the respective core circuits. The chips901and902may also include test circuits such as BIST circuits.

The test signal output by the first test signal generation circuit631passes through the first TSV611and the sixth TSV622, and then the test signal is received by the third test result judgment circuit643. The third test result judgment circuit643compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the first TSV611and the sixth TSV622due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the second test signal generation circuit632passes through the fourth TSV614and the seventh TSV623, and then the test signal is received by the fourth test result judgment circuit644. The fourth test result judgment circuit644compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the fourth TSV614and the seventh TSV623due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the third test signal generation circuit633passes through the fifth TSV621and the second TSV612, and then the test signal is received by the first test result judgment circuit641. The first test result judgment circuit641compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second TSV612and the fifth TSV621due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output by the fourth test signal generation circuit634passes through the eighth TSV624and the third TSV613, and then the test signal is received by the second test result judgment circuit642. The second test result judgment circuit642compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the third TSV613and the eighth TSV624due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

As has been described, in the three-dimensional integrated circuit according to Embodiment 2 of the present invention, each chip is provided with a pair of a test signal generation circuit and a test result judgment circuit for each pair of TSVs. As a result, before layering a plurality of chips, it is possible to detect the conducting state of two adjacent TSVs by connecting the TSVs together with a testing wire. Furthermore, as illustrated inFIG. 11, the test signal generation circuits22and the test result judgment circuits23are placed in a zigzag lattice pattern, with the TSV region12therebetween. This pattern results in each test signal generation circuit22facing a test result judgment circuit23in another test circuit region, with the TSV region12therebetween. Accordingly, when layering two chips, the test result judgment circuit of one chip can receive the test signal output by the test signal generation circuit of the other chip by turning one of the chips upside down. It is therefore possible to detect the conducting state of the TSVs between the chips. In this way, both before and after layering a plurality of chips, the same test circuits can be used to test the TSVs that connect the plurality of chips. Using the same test circuits improves the efficiency of testing. Furthermore, unlike the chips according to Embodiment 1, the chips according to Embodiment 2 do not require a switch circuit, thereby reducing the area of the test circuit regions13L and13R.

Modifications

(H) Right and left may be reversed in the circuit layout of the test circuit regions13L and13R illustrated inFIG. 11. Furthermore, inFIG. 12, the sets of a test signal generation circuit and a test result judgment circuit (211,221) and (212,222) located in the test circuit regions13L and13R are respectively connected to two vertically adjacent TSVs (201,202) and (203,204). The sets of a test signal generation circuit and a test result judgment circuit (211,221) and (212,222) may instead be respectively connected to two horizontally adjacent TSVs (201,203) and (202,204).

(I) InFIG. 13, the two microbumps171and172formed on the surface of the substrate101of the first chip100are connected to the two microbumps571and572formed on the surface of the substrate501of the second chip500. Alternatively, microbumps may be formed on the surface of the substrate of only one of the first chip100and the second chip500, and the microbumps may then be connected directly to the TSVs of the other chip.

Chips according to Embodiment 3 of the present invention differ from chips according to Embodiment 1 in that TSVs in the TSV region are placed in three rows. Other elements of the chips according to Embodiment 3 are similar to those of the chips according to Embodiment 1. Details on similar elements can be found in the description of Embodiment 1.

FIG. 15is a schematic diagram illustrating the planar structure of the TSV region12and the test circuit regions13in the chips according to Embodiment 3. As illustrated inFIG. 15, a plurality of TSVs21is placed in three rows in the TSV region12. The diameter of each TSV21is several micrometers. The interval between each TSV21is several dozen micrometers. In each of the test circuit regions13, sets of a test signal generation circuit22, a test result judgment circuit23and a switch circuit24are located adjacent to a pair of TSVs21.

FIG. 16is a block diagram of six adjacent TSVs201-206in the TSV region12and of their surrounding circuits. As illustrated inFIG. 16, the surrounding circuits include the first test signal generation circuit211, the second test signal generation circuit212, the first test result judgment circuit221, the second test result judgment circuit222, the first switch circuit231, and a second switch circuit1032. The test signal generation circuits211and212are instructed by an external device through a JTAG interface, to begin generating a test signal. The first test signal generation circuit211generates a test signal in response to the instruction and outputs the test signal to the first switch circuit231. The second test signal generation circuit212generates a test signal in response to the instruction and outputs the test signal to the second switch circuit1032. The test result judgment circuits221and222are instructed by an external device through the JTAG interface, or by the test signal generation circuits211and212, to begin judging the pattern of the test signal. In response to the instruction, the first test result judgment circuit221receives the signal from the first switch circuit231and judges whether the pattern of the signal matches the pattern of the test signal. In response to the above instruction, the second test result judgment circuit222receives the signal from the second switch circuit1032and judges whether the pattern of the signal matches the pattern of the test signal. Information on the results of judgment is transmitted from each of the test result judgment circuits221and222to an external device through the JTAG interface. The first switch circuit231connects each of the first test signal generation circuit211and the first test result judgment circuit221to either one of the first TSV201and the second TSV202. The second switch circuit1032connects each of the second test signal generation circuit212and the second test result judgment circuit222to either one of the third TSV203, the fourth TSV204, a fifth TSV205, and a sixth TSV206. The switch circuits231and1032select the destination in response to an instruction received from an external device through the JTAG interface.

First Connection Test

FIGS. 17A,17B, and17C are schematic diagrams illustrating conditions when performing the first connection test on the six TSVs201-206illustrated inFIG. 16. During the first connection test, as illustrated inFIG. 5, a test support substrate is mounted onto the chip. As a result, as illustrated inFIGS. 17A,17B, and17C, among the six TSVs201-206, each pair of either vertically or horizontally adjacent TSVs is connected by the testing wire. There are three patterns for connection.

FIG. 17Ais a schematic diagram illustrating conditions when the six TSVs are connected in the first pattern. As shown inFIG. 17A, the first TSV201and the third TSV203are connected by a first testing wire1701, the second TSV202and the fourth TSV204are connected by a second testing wire1702, and the fifth TSV205and the sixth TSV206are connected by a third testing wire1703. In this case, the first switch circuit231connects the first test signal generation circuit211with the first TSV201and connects the first test result judgment circuit221with the second TSV202. When the first connection test is performed on the pair of the first TSV201and the third TSV203, the second switch circuit1032connects the second test result judgment circuit222to the third TSV203. When the first connection test is performed on the pair of the second TSV202and the fourth TSV204, the second switch circuit1032connects the second test signal generation circuit212to the fourth TSV204. When the first connection test is performed on the pair of the fifth TSV205and the sixth TSV206, the second switch circuit1032connects the second test signal generation circuit212to the sixth TSV206and connects the second test result judgment circuit222to the fifth TSV205. Based on the operations of the two switch circuits231and1032, the test signal output from the first test signal generation circuit211passes through the first switch circuit231, the first TSV201, the first testing wire1701, the third TSV203, and the second switch circuit1032, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the third TSV203. On the other hand, when the first connection test is performed on the pair of the second TSV202and the fourth TSV204, the test signal output by the second test signal generation circuit212passes through the second switch circuit1032, the fourth TSV204, the second testing wire1702, the second TSV202, and the first switch circuit231, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the second TSV202or the fourth TSV204. When the first connection test is performed on the pair of the fifth TSV205and the sixth TSV206, the test signal output from the second test signal generation circuit212passes through the second switch circuit1032, the fifth TSV205, the third testing wire1703, the sixth TSV206, and the second switch circuit1032, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the fifth TSV205or the sixth TSV206.

FIG. 17Bis a schematic diagram illustrating conditions when the six TSVs are connected in the second pattern. As shown inFIG. 17B, the first TSV201and the second TSV202are connected by a first testing wire1711, the third TSV203and the fifth TSV205are connected by a second testing wire1712, and the fourth TSV204and the sixth TSV206are connected by a third testing wire1713. In this case, the first switch circuit231connects the first test signal generation circuit211with the first TSV201and connects the first test result judgment circuit221with the second TSV202. When the first connection test is performed on the pair of the third TSV203and the fifth TSV205, the second switch circuit1032connects the second test signal generation circuit212to the third TSV203and connects the second test result judgment circuit222to the fifth TSV205. When the first connection test is performed on the pair of the fourth TSV204and the sixth TSV206, the second switch circuit1032connects the second test signal generation circuit212to the fourth TSV204and connects the second test result judgment circuit222to the sixth TSV206. Based on the operations of the first switch circuit231, the test signal output from the first test signal generation circuit211passes through the first switch circuit231, the first TSV201, the first testing wire1711, the second TSV202, and the first switch circuit231, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the second TSV202. On the other hand, when the first connection test is performed on the pair of the third TSV203and the fifth TSV205, the test signal output by the second test signal generation circuit212passes through the second switch circuit1032, the third TSV203, the second testing wire1712, the fifth TSV205, and the second switch circuit1032, based on the operations of the second switch circuit1032, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the third TSV203or the fifth TSV205. When the first connection test is performed on the pair of the fourth TSV204and the sixth TSV206, the test signal output by the second test signal generation circuit212passes through the second switch circuit1032, the fourth TSV204, the third testing wire1713, the sixth TSV206, and the second switch circuit1032, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the fourth TSV204or the sixth TSV206.

FIG. 17Cis a schematic diagram illustrating conditions when the six TSVs are connected in the third pattern. As shown inFIG. 17C, the first TSV201and the second TSV202are connected by a first testing wire1721, the third TSV203and the fourth TSV204are connected by a second testing wire1722, and the fifth TSV205and the sixth TSV206are connected by a third testing wire1723. In this case, the first switch circuit231connects the first test signal generation circuit211with the first TSV201, and connects the first test result judgment circuit221with the second TSV202. When the first connection test is performed on the pair of the third TSV203and the fourth TSV204, the second switch circuit1032connects the second test signal generation circuit212to the fourth TSV204and connects the second test result judgment circuit222to the third TSV203. When the first connection test is performed on the pair of the fifth TSV205and the sixth TSV206, the second switch circuit1032connects the second test signal generation circuit212to the sixth TSV206, and connects the second test result judgment circuit222to the fifth TSV205. Based on the operations of the switch circuit231, the test signal output from the first test signal generation circuit211passes through the first switch circuit231, the first TSV201, the first testing wire1721, the second TSV202, and the first switch circuit231, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the second TSV202. On the other hand, when the first connection test is performed on the pair of the third TSV203and the fourth TSV204, the test signal output by the second test signal generation circuit212passes through the second switch circuit1032, the fourth TSV204, the second testing wire1722, the third TSV203, and the second switch circuit1032, based on the operations of the second switch circuit1032, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the third TSV203or the fourth TSV204. When the first connection test is performed on the pair of the fifth TSV205and the sixth TSV206, the test signal output from the second test signal generation circuit212passes through the second switch circuit1032, the sixth TSV206, the third testing wire1723, the fifth TSV205, and the second switch circuit1032, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the fifth TSV205or the sixth TSV206.

Second Connection Test

Two chips according to Embodiment 3 are layered similarly to the two chips100and500according to Embodiment 1, as illustrated inFIG. 7. In particular, between the upper chip (hereinafter referred to as the “first chip”) and the lower chip (hereinafter referred to as the “second chip”), each pair of TSVs that are adjacent along a normal line between the chips is connected by microbumps and by traces in the second chip.

As illustrated inFIG. 16, in both the first chip and the second chip, six TSVs201-206are adjacent to each other. Around these TSVs are located two test signal generation circuits211and212, two test result judgment circuits221and222, and two switch circuits231and1032. The test signal generation circuits211and212are instructed by an external device through a JTAG interface, to begin generating a test signal. The test signal generation circuits211and212generate a test signal in response to the instruction and each output the test signal to one of the switch circuits231and1032. The test result judgment circuits221and222store patterns of test signals in advance. The test result judgment circuits221and222are instructed by an external device through the JTAG interface, or by the test signal generation circuits211and212, to begin judging the pattern of the test signal. In response to the instruction, the test result judgment circuits221and222each receive the signal from one of the switch circuits231and1032and judge whether the pattern of the signal matches the pattern of the test signal.

During the second connection test, the switch circuits231and1032on each chip operate as follows. In the first chip, the first switch circuit231connects the first test signal generation circuit211to the first TSV201and connects the first test result judgment circuit221to the second TSV202. When the second connection test is performed on the third TSV203and the second chip500, the second switch circuit1032connects the second test result judgment circuit222to the third TSV203. When the second connection test is performed on the fourth TSV204and the second chip500, the second switch circuit1032connects the second test signal generation circuit212to the fourth TSV204. When the second connection test is performed on the fifth TSV205and the second chip500, the second switch circuit1032connects the second test result judgment circuit222to the fifth TSV205. When the second connection test is performed on the sixth TSV206and the second chip500, the second switch circuit1032connects the second test signal generation circuit212to the sixth TSV206. In the second chip, the first switch circuit231connects the first test signal generation circuit211to the second TSV202and connects the first test result judgment circuit221to the first TSV201. When the second connection test is performed on the third TSV203and the second chip500, the second switch circuit1032connects the second test signal generation circuit212to the third TSV203. When the second connection test is performed on the fourth TSV204and the second chip500, the second switch circuit1032connects the second test result judgment circuit222to the fourth TSV204. When the second connection test is performed on the fifth TSV205and the second chip500, the second switch circuit1032connects the second test signal generation circuit212to the fifth TSV205. When the second connection test is performed on the sixth TSV206and the second chip500, the second switch circuit1032connects the second test result judgment circuit222to the sixth TSV206.

The test signal output from the first test signal generation circuit211in the first chip passes through the first switch circuit231and the first TSV201in the first chip and through the first switch circuit231in the second chip, and then the test signal is received by the first test result judgment circuit221in the second chip. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second chip and the first TSV201in the first chip due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

After passing through the second switch circuit1032in the first chip, the test signal output by the second test signal generation circuit212in the first chip is first sent to the fourth TSV204and then to the sixth TSV206. After passing through the TSVs204and206, the test signal passes through the second switch circuit1032in the second chip, and then the test signal is received by the second test result judgment circuit222in the second chip. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second chip and the fourth TSV204in the first chip, or between the second chip and the sixth TSV206in the first chip, due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

The test signal output from the first test signal generation circuit211in the second chip passes through the first switch circuit231in the second chip and the second TSV202and the first switch circuit231in the first chip, and then the test signal is received by the first test result judgment circuit221in the second chip. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second chip and the second TSV202of the first chip due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

After passing through the second switch circuit1032in the second chip, the test signal output by the second test signal generation circuit212in the second chip is first sent to the third TSV203in the first chip and then to the fifth TSV205in the first chip. After passing through the TSVs203and205, the test signal passes through the second switch circuit1032in the first chip, and then the test signal is received by the second test result judgment circuit222in the first chip. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second chip and the third TSV203in the first chip, or between the second chip and the fifth TSV205in the first chip, due to misalignment of a TSV, a junction fault at a microbump, or another such reason.

In the three-dimensional integrated circuit according to Embodiment 3 of the present invention, unlike the three-dimensional integrated circuit according to Embodiment 1, the TSVs21in the TSV region12are placed in three rows, as illustrated inFIG. 15. In this case, as illustrated inFIG. 16, the second switch circuit1032can connect a set of the test signal generation circuit212and the test result judgment circuit222to two pairs of TSVs (203,205) and (204,206). Compared to when the switch circuit can only connect a set of a test signal generation circuit and a test result judgment circuit to one pair of TSVs, the number of test signal generation circuits and test result judgment circuits is reduced, and thus the area of the test circuit region is reduced.

Like the switch circuit according to Embodiment 1, the switch circuit according to Embodiment 3 of the present invention connects one of two TSVs to a test signal generation circuit and connects the other to a test result judgment circuit. As a result, before layering a plurality of chips, it is possible to detect the conducting state of two TSVs in each of the chips by connecting the TSVs together. On the other hand, after layering the plurality of chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal; this enables the conducting state of TSVs between the chips to be detected. In this way, both before and after layering a plurality of chips, the same test circuits can be used to test the TSVs that connect the plurality of chips. Using the same test circuits improves the efficiency of testing.

Modifications

(J) InFIG. 16, one row of TSVs201and202is connected to the switch circuit231located in the test circuit region13L on the left side of the TSV region12, whereas two rows of TSVs203-206are connected to the switch circuit1032located in the test circuit region13R on the right side of the TSV region12. Conversely, one row of TSVs may be connected to the switch circuit located in the test circuit region13R on the right side of the TSV region12, and two rows of TSVs may be connected to the switch circuit provided in the test circuit region13L on the left side. Furthermore, the layout shown inFIG. 16and its mirror-reversed one may be combined with each other.

(K) In the layout shown inFIG. 16, the switch circuit231may be removed from the test circuit region13L on the left side of the TSV region12as in the layout shown inFIG. 12. In this case, the second connection test is performed by turning the lower chip upside down, as illustrated inFIG. 13, and connecting the TSVs at the left edge of the TSV region12in each chip.

Chips according to Embodiment 4 of the present invention differ from chips according to Embodiment 1 in that TSVs in the TSV region are placed in four rows. Other elements of the chips according to Embodiment 4 are similar to those of the chips according to Embodiment 1. Details on similar elements can be found in the description of Embodiment 1.

FIG. 18is a schematic diagram illustrating the planar structure of the TSV region12and the test circuit regions14in the chips according to Embodiment 4. As illustrated inFIG. 18, a plurality of TSVs21is placed in four rows in the TSV region12. The diameter of each TSV21is several micrometers. The interval between each TSV21is several dozen micrometers. In each of the test circuit regions13, sets of a test signal generation circuit22, a test result judgment circuit23and a switch circuit24are located adjacent to a TSV21.

FIG. 19is a block diagram of eight adjacent TSVs201-208in the TSV region12and of their surrounding circuits. As illustrated inFIG. 19, the surrounding circuits include four test signal generation circuits211,212,213, and214, four test result judgment circuits221,222,223, and224, and four switch circuits231,232,233, and234. The first test signal generation circuit211and the first test result judgment circuit221are connected to the first switch circuit231. The second test signal generation circuit212and the second test result judgment circuit222are connected to the second switch circuit232. The third test signal generation circuit213and the third test result judgment circuit223are connected to the third switch circuit233. The fourth test signal generation circuit214and the fourth test result judgment circuit224are connected to the fourth switch circuit234. The test signal generation circuits211-214are instructed by an external device through a JTAG interface, to begin generating a test signal. The test signal generation circuits211-214generate a test signal in response to the instruction and output the test signal to the switch circuits231-234connected thereto. The test result judgment circuits221-224are instructed by an external device through the JTAG interface, or by the test signal generation circuits211-214, to begin judging the pattern of the test signal. In response to the instruction, the test result judgment circuits221-224receive the signal from the switch circuits231-234connected thereto and judge whether the pattern of the signal matches the pattern of the test signal. Information on the results of judgment is transmitted from each of the test result judgment circuits221-224to an external device. The first switch circuit231is connected to the first TSV201and the second TSV202. The second switch circuit232is connected to the seventh TSV207and the eighth TSV208. The third switch circuit233is connected to the fifth TSV205and the sixth TSV206. The fourth switch circuit234is connected to the third TSV203and the fourth TSV204. Each of the switch circuits231-234connects a pair of a test signal generation circuit and a test result judgment circuit to a pair of TSVs. The switch circuits231-234select the connection destination in response to an instruction received from an external device through a JTAG interface.

First Connection Test

FIGS. 20A,20B,20C,20D, and20E are schematic diagrams illustrating conditions when performing the first connection test on the eight TSVs201-208illustrated inFIG. 19. During the first connection test, as illustrated inFIG. 5, a test support substrate is mounted onto the chip. As a result, as illustrated inFIGS. 20A,20B,20C,20D, and20E, among the eight TSVs201-208, each pair of either vertically or horizontally adjacent TSVs is connected by a testing wire. As illustrated inFIGS. 20A,20B,20C,20D, and20E, there are five patterns for connection by testing wires.FIG. 20Ashows the first pattern. In the first pattern, two horizontally adjacent TSVs are connected.FIG. 20Bshows the second pattern. In the second pattern, among the eight TSVs, the four TSVs201-204in the left half are connected vertically, whereas the four TSVs205-208in the right half are connected horizontally.FIG. 20Cshows the third pattern. In the third pattern, among the eight TSVs, the four TSVs201-204in the left half are connected horizontally, whereas the four TSVs205-208in the right half are connected vertically.FIG. 20Dshows the fourth pattern. In the fourth pattern, two vertically adjacent TSVs are connected.FIG. 20Eshows the fifth pattern. In the fifth pattern, the two TSVs201and202at the left edge are connected, the four TSVs203-206in the middle are connected horizontally, and the two TSVs207and208at the right edge are connected.

In the first pattern illustrated inFIG. 20A, the first TSV201and the third TSV203are connected by a first testing wire2001; the second TSV202and the fourth TSV204are connected by a second testing wire2002, the fifth TSV205and the seventh TSV207are connected by a third testing wire2003, and the sixth TSV206and the eighth TSV208are connected by a fourth testing wire2004. In this case, the first switch circuit231connects the first test signal generation circuit211with the first TSV201and connects the first test result judgment circuit221with the second TSV202. The second switch circuit232connects the second test signal generation circuit212with the eighth TSV208and connects the second test result judgment circuit222with the seventh TSV207. The third switch circuit233connects the third test signal generation circuit213with the fifth TSV205and connects the third test result judgment circuit223with the sixth TSV206. The fourth switch circuit234connects the fourth test signal generation circuit214with the fourth TSV204and connects the fourth test result judgment circuit224with the third TSV203. Based on the operations of the four switch circuits231-234, the test signal output from the first test signal generation circuit211passes through the first switch circuit231, the first TSV201, the first testing wire2001, the third TSV203, and the fourth switch circuit234, and then the test signal is received by the fourth test result judgment circuit224. The fourth test result judgment circuit224compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the first TSV201or the third TSV203. The test signal output by the second test signal generation circuit212passes through the second switch circuit232, the eighth TSV208, the fourth testing wire2004, the sixth TSV206, and the third switch circuit233, and then the test signal is received by the third test result judgment circuit223. The third test result judgment circuit223compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the sixth TSV206or the eighth TSV208. The test signal output by the third test signal generation circuit213passes through the third switch circuit233, the fifth TSV205, the third testing wire2003, the seventh TSV207and the second switch circuit232, and then the test signal is received by the second test result judgment circuit222. The second test result judgment circuit222compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the fifth TSV205or the seventh TSV207. The test signal output by the fourth test signal generation circuit214passes through the fourth switch circuit234, fourth TSV204, the second testing wire2002, the second TSV202, and the first switch circuit231, and then the test signal is received by the first test result judgment circuit221. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault due to a void has occurred in either the second TSV202or the fourth TSV204.

When the testing wires connect the TSVs in a different pattern, the switch circuits231-234connect one of two adjacent TSVs to a test signal generation circuit and connect the other to a test result judgment circuit as well. As a result, two each of the eight TSVs are connected between a pair of a test signal generation circuit and a test result judgment circuit, and that allows for judgment of whether a connection fault due to a void has occurred in either of the TSVs.

Second Connection Test

Two chips according to Embodiment 4 are layered similarly to the two chips100and500according to Embodiment 1, as illustrated inFIG. 7. In particular, between the upper chip (hereinafter referred to as the “first chip”) and the lower chip (hereinafter referred to as the “second chip”), each pair of TSVs that are adjacent along a normal line between the chips is connected by microbumps and by interconnections in the second chip.

As illustrated inFIG. 19, in both the first chip and the second chip, eight TSVs201-208are adjacent to each other. Around these TSVs are located four test signal generation circuits211-214, four test result judgment circuits221-224, and four switch circuits231-234. The test signal generation circuits211-214are instructed by an external device through a JTAG interface, to begin generating a test signal. The test signal generation circuits211-214generate a test signal in response to the instruction and each output the test signal to one of the switch circuits231-234. The test result judgment circuits221-224store patterns of test signals in advance. The test result judgment circuits221-224are instructed by an external device through the JTAG interface, or by the test signal generation circuits211-214, to begin judging the pattern of the test signal. In response to the instruction, the test result judgment circuits221-224each receive the signal from one of the switch circuits231-234and judge whether the pattern of the signal matches the pattern of the test signal.

During the second connection test, the switch circuits232-234on each chip operate as follows. In the first chip, the first switch circuit231connects the first test signal generation circuit211to the first TSV201and connects the first test result judgment circuit221to the second TSV202. The second switch circuit232connects the second test signal generation circuit212with the eighth TSV208and connects the second test result judgment circuit222with the seventh TSV207. The third switch circuit233connects the third test signal generation circuit213with the fifth TSV205and connects the third test result judgment circuit223with the sixth TSV206. The fourth switch circuit234connects the fourth test signal generation circuit214with the fourth TSV204and connects the fourth test result judgment circuit224with the third TSV203. In the second chip, the first switch circuit231connects the first test signal generation circuit211to the second TSV202and connects the first test result judgment circuit221to the first TSV201. The second switch circuit232connects the second test signal generation circuit212with the seventh TSV207and connects the second test result judgment circuit222with the eighth TSV208. The third switch circuit233connects the third test signal generation circuit213with the sixth TSV206and connects the third test result judgment circuit223with the fifth TSV205. The fourth switch circuit234connects the fourth test signal generation circuit214with the third TSV203and connects the fourth test result judgment circuit224with the fourth TSV204.

The test signal output from the first test signal generation circuit211passes through the first switch circuit231and the first TSV201in the first chip and through the first switch circuit231in the second chip, and then the test signal is received by the first test result judgment circuit221in the second chip. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second chip and the first TSV201of the first chip due to misalignment of a TSV, a junction fault at a microbump, or another such reason. Similarly, the test signals output by the test signal generation circuits212-214in the first chip pass through the eighth TSV208, the fifth TSV205, and the fourth TSV204in the first chip, respectively, and then the test signal is received by the test result judgment circuits222-224in the second chip. By comparing the pattern of the received signal with the pattern of the test signal, the test result judgment circuits222-224can determine whether a connection fault has occurred between the second chip and the TSVs208,205, and204in the first chip, respectively.

The test signal output from the first test signal generation circuit211in the second chip passes through the first switch circuit231in the second chip and the second TSV202and the first switch circuit231in the first chip, and then the test signal is received by the first test result judgment circuit221in the first chip. The first test result judgment circuit221compares the pattern of the received signal with the pattern of the test signal. Based on the comparison results, it is possible to determine whether a connection fault has occurred between the second chip and the second TSV201of the first chip due to misalignment of a TSV, a junction fault at a microbump, or another such reason. Similarly, the test signals output by the test signal generation circuits212-214in the second chip pass through the seventh TSV207, the sixth TSV206, and the third TSV203in the first chip, respectively, and then the test signal is received by the test result judgment circuits222-224in the first chip. By comparing the pattern of the received signal with the pattern of the test signal, the test result judgment circuits222-224can determine whether a connection fault has occurred between the second chip and the TSVs207,206, and203in the first chip, respectively.

In the three-dimensional integrated circuit according to Embodiment 4 of the present invention, unlike the three-dimensional integrated circuit according to Embodiment 1, the TSVs in the TSV region are placed in four rows. In this case as well, like the three-dimensional integrated circuit according to Embodiment 1, the switch circuit connects one of two TSVs to a test signal generation circuit and connects the other to a test result judgment circuit. As a result, before layering a plurality of chips, it is possible to detect the conducting state of two TSVs by connecting the TSVs together. On the other hand, after layering the plurality of chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal; this enables the conducting state of TSVs between the chips to be detected. In this way, both before and after layering a plurality of chips, the same test circuits can be used to test the TSVs that connect the plurality of chips. Using the same test circuits improves the efficiency of testing.

Modifications

(L) InFIG. 19, the switch circuits231-234are connected to two vertically adjacent TSVs (201,202); (203,204); and (205,206), respectively. Alternatively, one or all of the switch circuits231-234may be connected to two horizontally adjacent TSVs.

(M) In the layout illustrated inFIG. 19, as in the layout illustrated inFIG. 12, the switch circuits may be removed from the test circuit region on one side or both sides of the TSV region12. In this case, the second connection test is performed by turning the lower chip upside down, as illustrated inFIG. 13.

(N) TSVs may be placed in five rows or more in the TSV region by combining the layouts illustrated inFIGS. 4,16, and19. In this case as well, both before and after layering a plurality of chips, the same test circuits can be used to test the TSVs that connect the plurality of chips.

Supplementary Explanation

Based on the above embodiments, the present invention may also be characterized as follows.

A chip according to one aspect of the present invention is one among a plurality of chips layered into a three-dimensional integrated circuit and is provided with a pair of connections, a test signal generation circuit, and a test result judgment circuit. The pair of connections is electrically connected with an adjacent chip among the plurality of chips. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives the signal from the other one of the connections and, in accordance with the state of the signal, detects the conducting state of the transmission path for the signal.

In the chip according to this aspect of the present invention, as described above, one of the pair of connections provided in the chip is connected to the test signal generation circuit, and the other is connected to the test result judgment circuit. Therefore, before layering the chip on another chip, a series connection is formed by connecting the pair of connections with the conductor, and the conducting state of each of the connections is detected based on the conducting state of the series connection. After layering the chip on another chip, the test signal generation circuit in the chip outputs the test signal, and the test result judgment circuit in the other chip receives the test signal, and thus the conducting state of the connections between chips is tested. In this way, both before and after layering a plurality of chips, the conducting state of the connections between the plurality of chips can be tested efficiently.

The chip according to this aspect of the present invention may further be provided with a switch circuit. The switch circuit selects one of the connections, connects the selected connection to the test signal generation circuit, and connects the other connection to the test result judgment circuit. The layout of the test signal generation circuit and the test result judgment circuit can thus be freely designed.

The chip according to this aspect of the present invention may further be provided with a plurality of connections. Two adjacent connections among the plurality of connections constitute the above pair of connections. As a result, the wire length between the pair of connections and the test circuit region, as well as the testing wire length in the first connection test, can be reduced to the necessary minimum.

In the three-dimensional integrated circuit according to an aspect of the present invention, connections adjacent along a normal line between two adjacent chips among a plurality of chips may be electrically connected. This modification allows for simplification of the wiring structure in each chip.

In the test method for a three-dimensional integrated circuit according to an aspect of the present invention, the conductor may be an electrode formed on a test support substrate. In this case, when forming the series connection between the first connection and the second connection formed in the first chip, the electrode connects the first connection to the second connection by the first chip being placed on the test support substrate. In this way, the electrode formed on the test support substrate plays the role of the conductor, and therefore the first connection and the second connection can be reliably connected to each other

In the test method for a three-dimensional integrated circuit according to an aspect of the present invention, when forming the series connection between the first connection and the second connection formed in the first chip, a first switch circuit formed in the first chip may connect one end of the series connection to the first test signal generation circuit and connect the other end of the series connection to the first test result judgment circuit. Furthermore, when the first chip is layered on the second chip, the first switch circuit may connect the first connection to the first test signal generation circuit and connect the second connection to the first test result judgment circuit, and a second switch circuit formed in the second chip may connect the first connection to the second test result judgment circuit and connect the second connection to the second test signal generation circuit. Since the switch circuit formed in each chip connects the connections to a test signal generation circuit or a test result judgment circuit, the layout of the test signal generation circuit and the test result judgment circuit can be freely designed.

A method of manufacturing a three-dimensional integrated circuit according to an aspect of the present invention is a method for manufacturing a three-dimensional integrated circuit in which a first chip is layered on a second chip. The method comprises the following steps. First, a core circuit, a first test signal generation circuit, a first test result judgment circuit, a first connection, and a second connection are formed in the first chip, and a core circuit, a second test signal generation circuit, and a second test result judgment circuit are formed in the second chip. Next, a series connection is formed by connecting the first connection and the second connection with a conductor, a first test signal is transmitted from the first test signal generation circuit to one end of the series connection, the first test signal is received from the other end of the series connection by the first test result judgment circuit, and a conducting state of the series connection is detected in accordance with a state of the first test signal. The first chip is then layered on the second chip, and the first chip is electrically connected to the second chip through the first connection and the second connection. Furthermore, a second test signal is transmitted from the second test signal generation circuit to the first connection, the second test signal is received from the first connection by the first test result judgment circuit, and the conducting state between the first connection and the second chip is detected in accordance with the state of the second test signal. A third test signal is then transmitted from the first test signal generation circuit to the second connection, the third test signal is received from the second connection by the second test result judgment circuit, and the conducting state between the second connection and the second chip is detected in accordance with the state of the third test signal.

As described above, in the method of manufacturing a three-dimensional integrated circuit according to an aspect of the present invention, before layering the two chips, a series connection is formed by connecting the pair of connections with the conductor, and the conducting state of each of the connections is detected based on the conducting state of the series connection. After layering the two chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in the other chip receives the test signal, and thus the conducting state of the connections between the chips is tested. In this way, both before and after layering the two chips, the conducting state of the connections between the chips can be tested efficiently.

INDUSTRIAL APPLICABILITY

The present invention relates to a manufacturing method of three-dimensional integrated circuits and, both before and after layering a plurality of chips, performs connection tests on the terminals connecting the chips using the same test circuits. The present invention therefore clearly has industrial applicability.

REFERENCE SIGNS LIST

12TSV region of chip

13test circuit region of chip

211first test signal generation circuit

212second test signal generation circuit

221first test result judgment circuit

222second test result judgment circuit

231first switch circuit

232second switch circuit