SEMICONDUCTOR DIE INCLUDING AN ASYMMETRIC PAD ARRAYS, A SEMICONDUCTOR DIE STACK INCLUDING THE SEMICONDUCTOR DIE, AND A HIGH BANDWIDTH MEMORY INCLUDING THE SEMICONDUCTOR DIE STACK

A semiconductor die stack includes a lower semiconductor die and an upper semiconductor die. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region. The second upper bonding pad and the first lower bonding pad are vertically aligned and directly bonded to each other. The second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die.

The present application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0106083, filed on Aug. 24, 2022 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the preset invention disclosure relate to a semiconductor die, a semiconductor die stack including the semiconductor die, and a memory including the semiconductor die stack.

2. Description of the Related Art

Recently, high bandwidth memory including a number of stacked semiconductor die stacks has been proposed and is the subject of extensive development efforts.

SUMMARY

An embodiment of the present invention disclosure is directed to a semiconductor die that includes an asymmetrical bonding pad array.

Another embodiment of the present invention disclosure is directed to a semiconductor die stack that includes the semiconductor die.

Yet another embodiment of the present invention disclosure is directed to a memory stack that includes the semiconductor die stack.

A semiconductor die stack in accordance with an embodiment of the present invention disclosure may include a lower semiconductor die and an upper semiconductor die stacked in a face-to-face form. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region adjacent to a first edge side of the upper semiconductor die; and a second upper bonding pad disposed in a second upper bonding pad region adjacent to a second edge side of the upper semiconductor die, the first edge side and the second edge side of the upper semiconductor die being opposite to each other. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region adjacent to a first edge side of the lower semiconductor die; and a second lower bonding pad disposed in a second lower bonding pad region adjacent to a second edge side of the lower semiconductor die, the first edge side and the second edge side of the lower semiconductor die being opposite to each other. The second upper bonding pad and the first lower bonding pad are vertically aligned and directly bonded to each other. The second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die.

A memory stack in accordance with an embodiment of the present invention disclosure may includes a plurality of semiconductor die stacks and inter-stack bumps between the semiconductor die stacks. Each of the plurality of semiconductor die stacks includes an upper semiconductor die and a lower semiconductor die bonded in a face-to-face form. The upper semiconductor die includes an upper common pad disposed in an upper common pad region disposed in a central region of a front surface of the upper semiconductor die; a first upper bonding pad disposed in a first upper bonding pad region adjacent to a first edge side of the upper semiconductor die; and a second upper bonding pad disposed in a second upper bonding pad region adjacent to a second edge side of the upper semiconductor die. The lower semiconductor die includes a lower common pad disposed in a lower common pad region disposed in a central region of a front surface of the lower semiconductor die; a first lower bonding pad disposed in a first lower bonding pad region adjacent to a first edge side of the lower semiconductor die; and a second lower bonding pad disposed in a second lower bonding pad region adjacent to a second edge side of the lower semiconductor die. The upper common pad and the lower common pad are vertically aligned to be directly bonded with each other. The first upper bonding pad and the second lower bonding pad are vertically aligned to be directly bonded with other. The second upper bonding pad and the first lower bonding pad are vertically aligned to be directly bonded with each other. The upper common pad of a lower semiconductor die stack disposed at a lower position of the semiconductor die stacks and the lower common pad of an upper semiconductor die stack disposed at an upper position of the semiconductor die stacks are electrically connected with each other through an inter-stack bump. The first upper bonding pad of the lower semiconductor die stack disposed at the lower position of the semiconductor die stacks and the second lower bonding pad of the upper semiconductor die tack disposed at the upper position of the semiconductor die stacks are not electrically connected with each other.

A high bandwidth memory in accordance with an embodiment of the present invention disclosure may include an interposer; and a plurality of memory stacks and a processing unit mounted on the interposer. Each of the plurality of memory stacks includes a base die; and a semiconductor die stack stacked on the base die. The semiconductor die stack includes an upper semiconductor die and a lower semiconductor die boded bonded in a face-to-face form. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region adjacent to a first edge side of the upper semiconductor die; and a second upper bonding pad disposed in a second upper bonding pad region adjacent to a second edge side of the upper semiconductor die. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region adjacent to a first edge side of the lower semiconductor die; and a second lower bonding pad disposed in a second lower bonding pad region adjacent to a second edge side of the lower semiconductor die. The first upper bonding pad and the second lower bonding pad are vertically aligned to be directly bonded with each other. The second upper bonding pad and the first lower bonding pad are vertically aligned to be directly bonded with each other. The first upper bonding pad and the second lower bonding pad are electrically connected to an upper electrical circuit in the upper semiconductor die, and are not electrically connected to a lower electrical circuit in the lower semiconductor die. The second upper bonding pad and the first lower bonding pad are not electrically connected to the upper electrical circuit in the upper semiconductor die and are electrically connected to the lower electrical circuit in the lower semiconductor die.

A method of testing a semiconductor die stack which includes an upper semiconductor die and a lower semiconductor die stacked in a face-to-face form, wherein the upper semiconductor die includes an upper common pad disposed in an upper common pad region; a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region, wherein the lower semiconductor die includes a lower common pad disposed in a lower common pad region; a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region, wherein the lower common pad and the upper common pad are directly bonded with each other, wherein the first upper bonding pad and the second lower bonding pad are directly bonded with other, wherein the second upper bonding pad and the first lower bonding pad are directly bonded with other, wherein the method includes providing a common signal to the upper and lower common pads; providing a first signal to the first upper bonding pad and the second lower bonding pad; and providing a second signal to the second upper bonding pad and the first lower bonding pad. The first signal includes a first semiconductor chip selection signal for selecting and activating the upper semiconductor die. The second signal includes a second semiconductor chip selection signal for selecting and activating the lower semiconductor die.

A method of testing a semiconductor die stack which includes an upper semiconductor die and a lower semiconductor die stacked in a face-to-face form, wherein the upper semiconductor die includes an upper common pad disposed in an upper common pad region; a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region, wherein the lower semiconductor die includes a lower common pad disposed in a lower common pad region; a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region, wherein the lower common pad and the upper common pad are directly bonded to each other; wherein the first upper bonding pad and the second lower bonding pad are directly bonded to each other; and wherein the second upper bonding pad and the first lower bonding pad are directly bonded to each other, wherein the method includes providing a common signal to the upper and lower common pads; providing a first signal to the first upper bonding pad and the second lower bonding pad; and providing a second signal to the second upper bonding pad and the first lower bonding pad, wherein the first signal includes a first data signal for delivering data of the upper semiconductor die, and wherein the second signal includes a second data signal for delivering data of the lower semiconductor die.

DETAILED DESCRIPTION

Other expressions that explain the relationship between elements, such as “between”, “directly between”, “adjacent to” or “directly adjacent to” should be construed in the same way. The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.

FIG.1Ais a perspective view illustrating an upper semiconductor die10and a lower semiconductor die20according to an embodiment of the present invention disclosure.FIG.1Bis a perspective view illustrating bonding the upper semiconductor die10and the lower semiconductor die20in a face-to-face form. Referring toFIG.1A, an upper semiconductor die10according to an embodiment of the present invention disclosure may include upper bonding pad regions13,15, and16disposed on an upper front surface11FS of an upper body11of the upper semiconductor die10. A lower semiconductor die20may include lower bonding pad regions23,25, and26disposed on a lower front surface21FS of a lower body21of the lower semiconductor die20.

The upper body11may have four upper edge sides11TE,11BE,11LE, and11RE, and the lower body21may have four lower edge sides21TE,21BE,21LE, and21RE. For example, the upper body11may have and upper top edge side11TE, an upper bottom edge side11BE, an upper left edge side11LE, and an upper right edge side11RE, and the lower body21may have a lower top edge side21TE, a lower bottom edge side21BE, a lower left edge side21LE, and a lower right edge side21RE. The upper top edge side11TE may be opposite to the upper bottom edge side11BE, and the lower top edge side21TE may be opposite to the lower bottom edge side21BE. The upper left edge side11LE may be opposite to the upper right edge side11RE, and the lower left edge side21LE may be opposite to the lower right edge side21RE.

The upper semiconductor die10may include an upper common bonding pad region13, a first upper bonding pad region15, and a second upper bonding pad region16disposed on the upper front surface11FS of the upper body11. The lower semiconductor die20may include a lower common bonding pad region23, a first lower bonding pad region25, and a second lower bonding pad region26disposed on the lower front surface21FS of the lower body21.

The upper and lower common bonding pad regions13and23may be disposed in a central region on the upper and lower front surfaces11FS and21FS of the upper and lower semiconductor dies10and20to extend along a column direction in an elongated shape, respectively. The first upper and lower bonding pad regions15and25may be disposed adjacent to upper and lower first edge sides (e.g., upper and lower left edge sides11LE and21LE) of the upper and lower bodies11and21of the upper and lower semiconductor dies10and20, respectively. The second upper and lower bonding pad regions16and26may be disposed adjacent to the upper and lower second edge sides (e.g., upper and lower right edge sides,11RE and21RE) of the upper and lower bodies11and21of the upper and lower semiconductor dies and20, respectively. The upper and lower first edge sides and the upper and lower second edge sides may be opposite to each other. Accordingly, the first upper bonding pad region15and the second upper bonding pad region16may include first and second upper bonding pads arranged in a line symmetric form, and the first lower bonding pad region25and the second lower bonding pad region26may include first and second lower bonding pads arranged in a line symmetric form. In another embodiment, the upper first edge side of the upper body11of the upper semiconductor die10may be one of the four upper edge sides11TE,11BE,11LE, and11RE, and the upper second edge side of the upper body11of the upper semiconductor die may be another one of the four upper edge sides11BE,11TE,11RE, and11LE opposite to the upper first edge side. In another embodiment, the lower first edge side of the lower body21of the lower semiconductor die20may be one of the four lower edge sides21TE,21BE,21LE, and21RE, and the lower second edge side of the lower body21of the lower semiconductor die20may be another one of the four lower edge sides21BE,21TE,21RE, and21LE opposite to the upper first edge side.

Referring toFIG.1, the upper semiconductor die10and the lower semiconductor die20may be bonded to each other in the face-to-face form that the upper front surface11FS of the upper body11of the upper semiconductor die10and the lower front surface21FS of the lower body21of the lower semiconductor die20may be faced each other. For example, the upper top edge side11TE of the upper semiconductor die10and the lower top edge side21TE of the lower semiconductor die20may be adjacent to each other, the upper bottom edge side11BE of the upper semiconductor die10and the lower bottom edge side21BE of the lower semiconductor die20may be adjacent to each other, the upper left edge side11LE of the upper semiconductor die10and the lower right edge side21RE of the lower semiconductor die20may be adjacent to each other, and the upper right edge side11RE of the upper semiconductor die10and the lower left edge side21LE of the lower semiconductor die20may be adjacent to each other. The upper semiconductor die10and the lower semiconductor die20may be bonded so that the upper common bonding pad region13of the upper semiconductor die10and the lower common bonding pad region23of the lower semiconductor die20may face each other, the first upper bonding pad region15of the upper semiconductor die10and the second lower bonding pad region26of the lower semiconductor die20may face each other, and the second upper bonding pad region16of the upper semiconductor die10and the first lower bonding pad region25of the lower semiconductor die20may face each other. Accordingly, upper common bonding pads in the upper common bonding pad region13of the upper semiconductor die10and lower common bonding pads in the lower common bonding pad region23of the lower semiconductor die20may be bonded to each other, first upper bonding pads in the first upper bonding pad region15of the upper semiconductor die10and second lower bonding pads in the second lower bonding pad region26of the lower semiconductor die20may be bonded to each other, and second upper bonding pads in the second upper bonding pad region16of the upper semiconductor die10and first lower bonding pads in the first lower bonding pad region25of the lower semiconductor die20may be bonded to each other.

In another embodiment, the upper common bonding pad region13of the upper semiconductor die10may be disposed on the upper front surface11FS of the upper body11of the upper semiconductor die to extend along a row direction in an elongated form, and the lower common bonding pad region23of the lower semiconductor die20may be disposed on the lower front surface21FS of the lower body21of the lower semiconductor die20to extend along the low direction in an elongated form.

In the embodiments of the present invention disclosure, the upper and lower bonding pads in the upper and lower common bonding pad regions13and23may be operating bonding pads or common test bonding pads. The first and second upper and lower bonding pads in the first and second upper bonding pad regions15and16and the first and second lower bonding pad regions25and26may be test bonding pads for testing the upper and lower semiconductor dies10and20.

FIG.2Ais a side view schematically illustrating a semiconductor die stack100A according to an embodiment of the present invention disclosure,FIG.2Bis an enlarged view of an area A1ofFIG.2A, andFIG.2Cis an enlarged view of an area A2and an area A3ofFIG.2A. The area A1shows that the upper common bonding pad region13of the upper semiconductor die10and the lower common bonding pad region23of the lower semiconductor die20are bonded to each other, the area A2shows that the second upper bonding pad region16of the upper semiconductor die10and the first lower bonding pad region25of the lower semiconductor die20are bonded to each other, and the area A3shows that the first upper bonding pad region15of the upper semiconductor die10and the second lower bonding pad region26of the lower semiconductor die20are bonded to each other.

Referring toFIGS.2A to2C, a semiconductor die stack100A according to an embodiment of the present invention disclosure may include the lower semiconductor die20and the upper semiconductor die10bonded to and stacked on the lower semiconductor die20. The lower semiconductor die20and the upper semiconductor die10may be bonded to each other and stacked in the face-to-face form in which the upper and lower front surfaces11FS and21FS face each other. That is, the upper semiconductor die10and the lower semiconductor die20may be bonded to each other so that the upper first edge side (e.g., the upper left edge side11LE) of the upper semiconductor die10and the lower second edge side (e.g., the lower right edge side21RE) of the lower semiconductor die20may be vertically aligned to each other, and the upper second edge side (e.g., the upper right edge side11RE) of the upper semiconductor die10and the lower first edge side (e.g., the lower left edge side21LE) of the lower semiconductor die20may be vertically aligned. In another embodiment, the upper first edge side of the upper semiconductor die10may be one of the upper top edge side11TE, the upper bottom edge side11BE, and the upper right edge side11RE, and the upper second edge side of the upper semiconductor die10may be one of the upper bottom edge side11BE, the upper top edge side11TE, and the upper left edge side11LE opposite to the upper first edge side of the upper semiconductor die10. The lower second edge side of the lower semiconductor die20may be one of the lower bottom edge side21BE, the lower top edge side21TE, and the lower left edge side21LE, and the lower first edge side of the lower semiconductor die may be one of the lower top edge side21TE, the lower bottom edge side21BE, and the lower right edge side21RE opposite to the lower second edge side of the lower semiconductor die20.

Referring toFIGS.2A and2B, the upper semiconductor die10may include an upper common top metal pattern131, an upper common back-side pad132, an upper common through-via135, an upper common bonding pad137, and an upper bonding insulating layer18, and the lower semiconductor die20may include a lower common top metal pattern231, a lower common back-side pad232, a lower common through-via235, a lower common bonding pad237, and a lower bonding insulating layer28.

The upper common top metal pattern131may be disposed adjacent to the upper front surface11FS of the upper body11of the upper semiconductor die10. The upper common back-side pad132may be disposed adjacent to the upper back surface11BS of the upper semiconductor die10. The upper common through-via135may pass though the upper semiconductor die10to connect the upper common top metal pattern131to the upper common back-side pad132. The upper common bonding pad137may be disposed on the upper common top metal pattern131. The upper bonding insulating layer18may be disposed on the upper front surface11FS of the upper semiconductor die10to surround side surfaces of the upper common bonding pad137.

The lower common top metal patterns231may be disposed adjacent to the lower front surface21FS of the lower semiconductor die20. The lower common back-side pad232may be disposed adjacent to the lower back surface21BS of the lower semiconductor die20. The lower common through-via235may pass through the lower semiconductor die20and connect the lower common top metal pattern231to the lower common back-side pad232. The lower common bonding pad237may be disposed on the lower common top metal pattern231. The lower bonding insulating layer28may be disposed on the lower front surface21FS to surround side surfaces of the lower common bonding pad237.

The upper common bonding pad137of the upper semiconductor die10and the lower common bonding pad237of the lower semiconductor die20may be directly in contact and be bonded to each other. The upper bonding insulating layer18of the upper semiconductor die10and the lower bonding insulating layer28of the lower semiconductor die20may be directly in contact and bonded to each other. The upper bonding insulating layer18and the lower bonding insulating layer28may include silicon oxide.

The upper common top metal pattern131, the upper common back-side pad132, the upper common through-via135, and the upper common bonding pad137of the upper semiconductor die10, and the lower common top metal pattern231, the lower common back-side pad232, the lower common through-via235, and the lower common bonding pad237of the lower semiconductor die20may be commonly electrically connected to both upper and lower electrical circuits in the upper and lower semiconductor dies10and20.

Referring toFIGS.2A and2C, the upper semiconductor die10may include a first upper top metal pattern151, a first upper back-side pad152, a first upper through-via155, and a first upper bonding pad157disposed in the first upper bonding pad region15, a second upper top metal pattern161, a second upper back-side pad162, a second upper through-via165, and a second upper bonding pad167disposed in the second upper bonding pad region16. The lower semiconductor die20may include a first lower top metal pattern251and a first lower bonding pad257disposed in the first lower bonding pad region25, a second lower top metal pattern261and a second lower bonding pad267disposed in the second lower bonding pad region26. The lower semiconductor die20may not include a lower through-via and a lower back-side pad to be connected to the first lower top metal pattern251. In addition, the lower semiconductor die20may not include a lower through-via and a lower back-side pad to be connected to the second lower top metal pattern261.

The first and second upper top metal patterns151and161may be disposed adjacent to the upper front surface11FS of the upper1ssemiconductor die10. The first and second upper back-side pads152and162may be disposed adjacent to the upper back surface11BS of the upper semiconductor die10. The first upper through-via155may electrically connect the first upper top metal pattern151to the first upper back-side pad152passing through the upper semiconductor die10, and the second upper through-via165may electrically connect the second upper top metal pattern161to the second upper back-side pad162passing through the upper semiconductor die10. The first upper bonding pad157may be disposed on the first upper top metal pattern151, and the second upper bonding pad167may be disposed on the second upper top metal pattern161. The upper bonding insulating layer18may be disposed on the upper front surface11FS of the upper semiconductor die10to surround side surfaces of the first and second upper bonding pads157and167.

The first and second lower top metal patterns251and261may be disposed adjacent to the lower front surface21FS of the lower semiconductor die20. The first lower bonding pad257may be disposed on the second upper top metal pattern251, and the second lower bonding pad267may be disposed on the second lower top metal pattern261. The lower bonding insulating layer28may be disposed on the lower front surface21FS of the lower semiconductor die20to surround side surfaces of the first and second lower bonding pads257and267.

The first upper bonding pad region15of the upper semiconductor die10and the second lower bonding pad region26of the lower semiconductor die20may be vertically aligned with each other, and the second upper bonding pad region16of the upper semiconductor die10and the first lower bonding pad region25of the lower semiconductor die20may be vertically aligned with each other. For example, the first upper bonding pad157in the first upper bonding pad region15of the upper semiconductor die10and the second lower bonding pad267in the second lower bonding pad region26of and the lower semiconductor die20may be vertically aligned to be directly contacted and bonded to each other, and the second upper bonding pad167in the second upper bonding pad region16of the upper semiconductor die10and the first lower bonding pad257in the first lower bonding pad region25of the lower semiconductor die20may be vertically aligned to be directly contacted and bonded to each other. Accordingly, the conductive elements151,152,155, and157in the first upper bonding pad region15of the upper semiconductor die10and the conductive elements261and267in the second lower bonding pad region of the lower semiconductor die20may be electrically connected to each other. The conductive elements162,162,165, and167in the second upper bonding pad region16of the upper semiconductor die10and the conducive elements251and257in the first lower bonding pad region25of the lower semiconductor die20may be electrically connected to each other.

In one embodiment, any one of the first lower top metal pattern251and the second lower top metal pattern261may be electrically connected to a lower electrical circuit in the lower semiconductor die20, and the other one of the first lower top metal pattern251and the second lower top metal pattern261may not be electrically connected to the lower electrical circuit in the lower semiconductor die20. The first one of the first lower top metal pattern251and the second lower top metal pattern261may not be electrically connected to the electrical circuit in the upper semiconductor die10, and the second one of the first lower top metal pattern251and the other of the second lower top metal pattern261may be electrically connected to the electrical circuit in the lower semiconductor die10.

In one embodiment, any one of the first top metal pattern151and the second upper top metal pattern161may be electrically connected to an upper electrical circuit in the upper semiconductor die10, and the other one the first upper top metal pattern151and the second upper top metal pattern161may not be connected to the upper electrical circuit in the upper semiconductor die10. The one of the first upper top metal pattern151and the second upper top metal pattern161may not be electrically connected to the lower electrical circuit in the lower semiconductor die20, and the other one of the first upper top metal pattern151and the second upper top metal pattern161may be electrically connected to the lower electrical circuit in the lower semiconductor die20.

That is, the one of the first upper top metal pattern151and the second upper top metal pattern161may be electrically exclusively connected to the upper semiconductor die10, and the other one of the first upper top metal pattern151and the upper top metal pattern161may be electrically exclusively connected to the lower semiconductor die20. In one embodiment, the first upper top metal pattern151may selectively communicate with one of the upper semiconductor die10and the lower semiconductor die20, and the second upper top metal pattern161may selectively communicate with the other one of the upper semiconductor10and the lower semiconductor die20.

FIG.3Ais a side view schematically illustrating a semiconductor die stack100B according to an embodiment of the present invention disclosure, andFIG.3Bis an enlarged view of the area A4and area A5ofFIG.3A. Referring toFIGS.3A and3B, a semiconductor die stack100B according to an embodiment of the present invention disclosure may include a lower semiconductor die20and an upper semiconductor die10bonded and stacked on the lower semiconductor die20.

The upper semiconductor die10may include a first upper top metal pattern151, a first upper back-side pad152, a first upper through-via155, and a first bonding pad157disposed in a first upper bonding pad region15, a second top metal pattern161, a second upper back-side pad162, a second upper through-via155, and a first upper bonding pad157disposed in a second upper bonding pad region16. The lower semiconductor die20may include a first lower top metal pattern251and a first lower bonding pad257disposed in a first lower bonding pad region25. Compared to the connection structure ofFIG.2C, any conductive elements to be electrically connected to the first upper top metal pattern151or the first upper bonding pad157may not be disposed in the second lower bonding pad region26.

In one embodiment, the first upper bonding pad157in the first upper bonding pad region15of the upper semiconductor die10may not be formed.

In the present embodiment, the second upper top metal pattern161in the second upper bonding pad region16of the upper semiconductor die10may not be electrically connected to the upper electrical circuit in the upper semiconductor die10. That is, the second upper top metal pattern161, the second upper back-side pad162, the second upper through-via165, and the second upper bonding pad167in the second upper bonding pad region16may not be electrically connected to the upper electrical circuit in the upper semiconductor die10, and electrically connected to the first lower top metal pattern251and the first lower bonding pad257in the first lower bonding pad region of the lower semiconductor die20. That is, the conductive elements161,162,165, and167in the second upper bonding pad region16may be electrically connected to the lower electrical circuit in the lower semiconductor die20. Compared toFIG.2C, since there are no conductive elements in the second lower bonding pad region26of the lower semiconductor die20, the conductive elements151,152,155, and157in the first upper bonding pad region15of the upper semiconductor die10may not be electrically connected to the lower electrical circuits in the lower semiconductor die20.

That is, the conductive elements151,152,155, and157in the first upper bonding pad region15of the upper semiconductor die10may be electrically connected to the upper electrical circuit in the upper semiconductor die10, and the conductive elements161,162,165, and167in the second upper bonding pad region16of the upper semiconductor die10may be electrically connected to the lower electrical circuit in the lower semiconductor die20through the conductive elements251an257in the first lower bonding pad region of the lower semiconductor die20. The other reference numerals not described can be understood with reference toFIGS.2A to2C.

FIG.4Ais a side view schematically illustrating a semiconductor die stack100C according to an embodiment of the present invention disclosure, andFIG.4Bis an enlarged view of the area A6and area A7ofFIG.4A. Referring toFIGS.4A and4B, a semiconductor die stack100C according to an embodiment of the present invention disclosure may include a lower semiconductor die20and an upper semiconductor die10bonded and stacked on the lower semiconductor die20.

The upper semiconductor die10may include a first upper top metal pattern151, a first upper back-side pad152, a first upper through-via155, and a first upper bonding pad157disposed in a first upper bonding pad region15, and a second upper top metal pattern161, a second upper back-side pad162, a second upper back-side pad162, a second upper through-via165, and a second bonding pad167in a second upper bonding pad region16. The lower semiconductor die may include a first lower top metal pattern251, a first lower back-side pad252, a first lower through-via255, and a first lower bonding pad257disposed in a lower bonding pad region25, and a second lower top metal pattern261, a second lower back-side pad262, a second lower through-via265, and a second lower bonding pads267disposed in a second lower bonding pad region26.

The first and second lower back-side pads252and262may be disposed adjacent to the lower back-side21BS of the lower semiconductor die20. The first lower through-via255may pass through the lower semiconductor die20and electrically connect the first lower top metal pattern251to the first lower back-side pad252, and the second lower through-via265may pass through the lower semiconductor die20and electrically connect the second lower top metal pattern261to the second lower back-side pad262. The other reference numerals not described and the inventive concept of the embodiment can be understood with reference toFIGS.2A to2C and3A and3B.

FIGS.5A to5Care views illustrating a method of testing the upper semiconductor die10and the lower semiconductor die20of the semiconductor die stacks100A-100C according to an embodiment of the present invention disclosure. Referring toFIGS.5A to5C, a method of testing the semiconductor die stacks100A-100C according to an embodiment of the present invention disclosure may include preparing the semiconductor die stacks100A-100C each including the upper semiconductor die10and the lower semiconductor die20, providing a common signal S0to the conductive elements131,132,135, and137in the upper common bonding pad region13and the conductive elements231,232,235, and237in the lower common bonding pad region23, providing a first signal S1to the conductive elements151,152,155, and157in the first upper bonding pad region15and the conductive elements261,262,265, and267in the second lower bonding pad region26, and providing a second signal S2to the conductive elements161,162,165, and167in the second upper bonding pad region16and the conductive elements251,252,255, and257in the first lower bonding pad region25.

The common signal S0may be commonly provided to the upper semiconductor die10and the lower semiconductor die20. For example, a common signal S0may include a command signal CMD, an address signal ADDR, a data signal DQ, and a power signal PWR. The first signal S1may be provided to the upper semiconductor die10. The first signal S1may include a first chip selection signal CS1for selecting the upper semiconductor die10. The first signal S1may further include various reference voltage signals VDDs, VSS, and VPPE. The second signal S2may be provided to the lower semiconductor die20. The second signal S2may include a second chip selection signal CS2for selecting the lower semiconductor die20. The second signal S2may also further include various reference voltage signals VDDs, VSS, and VPPE. The upper semiconductor die10may be selected and activated by the first chip selection signal CS1, and the upper semiconductor die10may be tested by the common signal S0and the first signal S1. The lower semiconductor die20may be selected and activated by the second chip selection signal CS2, and the lower semiconductor die10may be tested by the common signal S0and the second signal S2. The first signal S1and the second signal S2can be provided exclusively. That is, the first signal S1and the second signal S2may not be simultaneously provided to the upper semiconductor die10and the lower semiconductor die20. Thus, the upper semiconductor die10and the lower semiconductor die may be selected and activated independently and can be tested independently.

FIGS.6A to6Care views illustrating a method of testing the upper semiconductor die10and lower semiconductor die20of the semiconductor die stacks100A-100C according to an embodiment of the present invention disclosure. Referring toFIGS.6A to6C, a method of testing the upper semiconductor die10and the lower semiconductor die20of the semiconductor die stacks100A-100C according to an embodiment of the present invention disclosure may include preparing the semiconductor die stacks100A-100C including the lower semiconductor die20and the upper semiconductor die10stacked on the lower semiconductor die20, providing a common signal S0to the conductive elements131,132,135, and137in the upper common bonding pad region13and the conductive elements231,232,235, and237in the lower common bonding pad region23, providing a first data signal DQ1to the conductive elements151,152,155, and157in the first upper bonding pad region15and the conductive elements261,262,265, and267in the second lower bonding pad region26, and providing a second data signal DQ2to the conductive elements161,162,165, and167in the second upper bonding pad region16and the conductive elements251,252,255, and257in the first lower bonding pad region25. The first data signal DQ1may transfer data of the upper semiconductor die10. The second data signal DQ2may transfer data of the lower semiconductor die20. As described above, the conductive elements151,152,155, and157in the first upper bonding pad region in which the first data signal DQ1is provided may not be electrically connected to the lower electrical circuit in the lower semiconductor die20. The conductive elements161,162,165, and167in the second upper bonding pad region16in which the second data signal DQ2is provided may not be electrically connected to the upper electrical circuit in the upper semiconductor die10. The conductive elements251and257in the first lower bonding pad region25may be electrically connected to the lower electrical circuits in the lower semiconductor die20.

In the present embodiment, the first chip selection signal CS1for selecting the upper semiconductor die10and the second chip selection signal CS2for selecting the lower semiconductor die20may be included in the common signal S0. For example, the upper semiconductor die10and the lower semiconductor die20may be selected and activated at the same time, but the data may be written and read out through different bonding pads, respectively.

In another embodiment, the first chip selection signal CS1may be provided to the conductive elements151,152,155, and157in the first upper bonding pad region15, and the second chip selection signal CS2may be provided to the conductive elements161,162,165, and167of the second upper bonding pad region16may be provided.

Referring toFIGS.5A to5C and6A to6C, the conductive elements151,152,155, and157in the first upper bonding pad region of the upper semiconductor die10and the conductive elements261,262,265, and267in the second lower bonding pad region26of the lower semiconductor die20may be used exclusively to test the upper semiconductor die10, and the conductive elements161,162,165, and167in the second upper bonding pad region16of the upper semiconductor die10and the conductive elements251,252,255, and257in the first lower bonding pad region25of the lower semiconductor die20may be used exclusively to test the lower semiconductor die20.

According to the various embodiments of the present invention disclosure, two stacked semiconductor dies10and20of the semiconductor die stacks100A-100C can be tested at the same time. That is, the upper semiconductor die10and the lower semiconductor die20may be tested simultaneously after bonded and stacked. Therefore, the test process for testing the semiconductor dies10and can be carried out fast. In addition, errors occurred in the bonding process can be easily detected.

FIGS.7A to7Care views schematically illustrating high bandwidth memories1000A-1000C according to embodiments of the present invention disclosure. Referring toFIGS.7A to7C, high-bandwidth memories1000A-1000C according to embodiments of the disclosure may include memory stacks300A-300C and a processing unit400on an interposer substrate500, respectively. Each of the memory stacks300A-300B may include a plurality of semiconductor die stacks100A-100C. The memory stacks300A-300C and the processing unit400may be bonded to be electrically connected to the interposer substrate500through interposer bumps55. The interposer bumps55may include solder materials or metals. The interposer substrate500may include internal interconnections. The memory stacks300A-300C and processing unit400may be electrically connected to each other through the internal interconnections of the interposer substrate500.

The memory stacks300A-300C may include the semiconductor die stacks100A-100C stacked on a base die200. The base die200and the semiconductor die stacks100A-100C may be electrically connected to each other through inter-stack bumps51.

The inter-stack bumps51may electrically connect the upper common back-side pads132of the upper semiconductor die10of each of the semiconductor die stacks100A-100C and the lower common back-side pads232of the lower semiconductor die20of each of the semiconductor die stacks100A-100C. Accordingly, the corresponding upper common back-side pad132in the upper bonding pad region13of the upper semiconductor die10and the corresponding lower back-side common bonding pad232in the lower common bonding pad region23of the lower semiconductor die20may be electrically connected each other through the inter-stack bumps51. The inter-stack bumps51may not be formed on the first upper back-side pad152in the first upper bonding pad region15and the second upper back-side pad162in the second upper bonding pad region16of the upper semiconductor die10of each of the semiconductor stacks100A-100C, and on the first lower back-side pad252in the first lower bonding pad region25and the second lower back-side pad262in the second back-side pad region26of the lower semiconductor die20of each of the semiconductor stacks100A-100C.

The conductive elements151,152,155,157,161,162,165, and167in the first and second upper bonding pad regions15and16of the upper semiconductor die10of the semiconductor die stacks100A-100C disposed at a lower position of the memory stacks300A-300C and the conductive elements251,252,255,257,261,262,265, and267in the first and second lower bonding pad regions25and26of the lower semiconductor die20of the semiconductor die stacks100A-100C disposed at an upper position of the memory stacks300A-300C may not be electrically and physically connected to each other.

Accordingly, in each of the memory stack300A-300C, the conductive elements151,152,155,157in the first upper bonding pad region15of the upper semiconductor die10of each of the semiconductor stacks100A-100C disposed at the lower position and the conductive elements261,262,265, and267in the second lower bonding pad region26of the lower semiconductor die20of each of the semiconductor die stacks100A-100C disposed at the upper position may be vertically aligned and may not be electrically connected with each other, respectively, and the conductive elements161,162,165,167in the second upper bonding pad region16of the upper semiconductor die10of each of the semiconductor stacks100A-100C disposed at the lower position and the conductive elements251,252,255, and257in the first lower bonding pad region25of the lower semiconductor die20of each of the semiconductor die stacks100A-100C disposed at the upper position may be vertically aligned and may not be electrically connected with each other, respectively.

According to embodiments of the present invention disclosure, the semiconductor dies include asymmetrically arrayed bonding pads, the semiconductor die stack includes the semiconductor dies bonded in the face-to-face form, accordingly, the stacked semiconductor dies can be tested at the same time.

According to the embodiments of the present invention disclosure, since the bonded semiconductor die can be tested at the same time, the test process for testing the semiconductor dies can be carried out quickly.

According to the embodiments of the present invention disclosure, an error generated in a bonding process may be detected because the test process for testing the semiconductor dies after performing the bonding process.