Solid-state imaging device having a vertical transistor with a dual polysilicon gate

A solid-state imaging device includes: a pixel part having a photoelectric conversion part photoelectrically converting incident light to obtain signal charge; and a peripheral circuit part formed on a periphery of the pixel part on a semiconductor substrate. The pixel part having a vertical transistor that reads out the signal charge from the photoelectric conversion part and a planar transistor that processes the signal charge read out by the vertical transistor. The vertical transistor has a groove part formed on the semiconductor substrate; a gate insulator film formed on an inner surface of the groove part; a conducting layer formed on a surface of the gate insulator film on the semiconductor substrate within and around the groove part; a filling layer filling an interior of the groove part via the gate insulator film and the conducting layer; and an electrode layer connected to the conducting layer on the filling layer.

The present application claims priority to Japanese Patent Application JP 2008-279471 filed in the Japan Patent Office on Oct. 30, 2008, the entire contents of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging device, a manufacturing method of the same, and an imaging apparatus.

2. Description of Related Art

A solid-state imaging device including both a vertical transistor and a planar transistor is disclosed (e.g., see JP-A-2005-223084).

It is very difficult to make both the vertical transistor and a CMOSFET (e.g., CMOSFET following the design rule of 0.18 μm or less) including the planar transistor on the same substrate.

For example, the case where non-doped polysilicon is used for the respective gate electrodes of the vertical transistor and the planar transistor will be described.

When a vertical hole of the vertical transistor is filled with non-doped polysilicon for gate electrode and closed, it becomes difficult to dope the polysilicon in the deep part of the vertical hole in the substrate.

For example, there is a method of filling the vertical hole forming the vertical transistor with polysilicon, and then, diffusing an impurity at high density of 1×1020cm−3from the surface to the bottom of the polysilicon filling in the vertical hole by thermal diffusion (see JP-A-2001-189456).

However, if the heat that diffuses the impurity at high density of 1×1020cm−3to the bottom of the polysilicon filling in the vertical hole is applied, in the planar CMOSFET part, the device isolation function is deteriorated due to thermal diffusion of the device isolation region formed by the diffusion layer. Further, if the impurity is allowed to reach the bottom of the vertical hole by ion implantation, the high-density impurity is implanted into the silicon substrate, and it may be impossible to form the channel of the vertical transistor.

Accordingly, it has been difficult to mount both the planar CMOSFET and the vertical transistor on the same semiconductor substrate.

SUMMARY OF THE INVENTION

There is need for solving the problem that it is difficult to mount both the planar CMOSFET and the vertical transistor on the same semiconductor substrate.

The present allows both a planar CMOSFET and a vertical transistor be mounted on the same semiconductor substrate using a thin film formed via a gate insulator film on the inner surface of a groove in which the vertical transistor is formed as an effective gate electrode.

A solid-state imaging device according to an embodiment of the invention includes a pixel part having a photoelectric conversion part that photoelectrically converts incident light to obtain signal charge and a peripheral circuit part formed on a periphery of the pixel part on a semiconductor substrate,

the pixel part has a vertical transistor that reads out the signal charge from the photoelectric conversion part and a planar transistor that processes the signal charge read out by the vertical transistor,

the vertical transistor has

a groove part formed on the semiconductor substrate,

a gate insulator film formed on an inner surface of the groove part,

a conducting layer formed on a surface of the gate insulator film on the semiconductor substrate within and around the groove part,

a filling layer filling an interior of the groove part via the gate insulator film and the conducting layer, and

an electrode layer connected to the conducting layer on the filling layer.

In the solid-state imaging device according to the embodiment of the invention, the gate electrode is formed by the conducting layer on the inner surface of the groove part via the gate insulator film, the filling layer filling the interior of the groove part, and the electrode layer connected to the conducting layer. Effectively, the conducting layer has a function of the gate electrode. Therefore, it is not necessary to fill the groove part with the conducting layer, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part in the polysilicon filling the groove part by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part in the polysilicon filling the groove part.

A manufacturing method of a solid-state imaging device (a first manufacturing method) according to an embodiment of the invention includes the step of forming a pixel part having a photoelectric conversion part that photoelectrically converts incident light to obtain an electric signal, a vertical transistor that reads out signal charge from the photoelectric conversion part, and a planar transistor that processes the read out signal charge, and a peripheral circuit part having a first conductivity-type-channel transistor and a second conductivity-type-channel opposite to the first conductivity-type on a periphery of the pixel part on a semiconductor substrate, and

the step of forming gate electrodes of the respective transistors of the pixel part and the peripheral circuit part includes the steps of

forming a groove part in a region where the gate electrode of the vertical transistor is formed on the semiconductor substrate,

forming a gate insulator film on a surface of the semiconductor substrate containing an inner surface of the groove part,

forming a first polysilicon film on the semiconductor substrate containing the inner surface of the groove part under a non-doped condition via the gate insulator film,

forming a conducting layer by doping a first conductivity-type impurity on the first polysilicon film in a pixel part formation region where the pixel part is formed,

forming a second polysilicon film also filling an interior of the groove part on the first polysilicon film under a non-doped condition,

doping the first conductivity-type impurity in the second polysilicon film in a region where the first conductivity-type-channel transistor is formed in the pixel part formation region and a peripheral circuit part formation region where the peripheral circuit part is formed, and doping a second conductivity-type impurity in the second polysilicon film and the first polysilicon film in a region where the second conductivity-type-channel transistor is formed, and

forming the gate electrode of the vertical transistor, the gate electrode of the planar transistor of the pixel part, and the gate electrodes of the respective transistors of the peripheral circuit part with the first polysilicon film and the second polysilicon film.

In the first manufacturing method of a solid-state imaging device according to the embodiment of the invention, the conducting layer that effectively functions as the gate electrode is formed by doping the conductivity-type impurity in the first polysilicon film formed on the inner surface of the groove part via the gate insulator film. Further, the gate electrode is formed by the filling layer of the non-doped second polysilicon film filling the interior of the groove part and the electrode layer of the second polysilicon film doped with the first conductivity-type impurity connected to the first polysilicon film. Effectively, the conducting layer has a function of the gate electrode. Therefore, it is not necessary to fill the groove part with the conducting layer, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part in the polysilicon filling the groove part by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part in the polysilicon filling the groove part.

Further, the gate electrodes of the planar transistors of the pixel part and the peripheral circuit part are formed by doping a predetermined conductivity-type impurity in the non-doped first polysilicon film and the non-doped second polysilicon film. Accordingly, the gate electrode of the N-channel-type transistor and the gate electrode of the P-channel-type transistor are separately formed in N-type and P-type, respectively. In addition, the gate electrode having a minute gate length can be formed.

A manufacturing method of a solid-state imaging device (a second manufacturing method) according to an embodiment of the invention includes the step of forming a pixel part having a photoelectric conversion part that photoelectrically converts incident light to obtain an electric signal, a vertical transistor that reads out signal charge from the photoelectric conversion part, and a planar transistor that processes the readout signal charge, and a peripheral circuit part having a first conductivity-type-channel transistor and a second conductivity-type-channel opposite to the first conductivity-type on a periphery of the pixel part on a semiconductor substrate, and

the step of forming gate electrodes of the respective transistors of the pixel part and the peripheral circuit part includes the steps of

forming a groove part in a region where the vertical transistor is formed on the semiconductor substrate,

forming a gate insulator film on a surface of the semiconductor substrate containing an inner surface of the groove part,

forming a polysilicon film on the semiconductor substrate containing the inner surface of the groove part under a non-doped condition via the gate insulator film,

doping a first conductivity-type impurity on the polysilicon film in a region where the first conductivity-type-channel transistor is formed in a pixel part formation region where the pixel part is formed and a peripheral circuit part formation region where the peripheral circuit part is formed,

doping a second conductivity-type impurity in the polysilicon film in a region where the second conductivity-type-channel transistor is formed in the peripheral circuit part formation region,

forming a metal film on the polysilicon film, and

forming the gate electrode of the vertical transistor, the gate electrode of the planar transistor of the pixel part and the gate electrodes of the respective transistors of the peripheral circuit part with the polysilicon film and the metal film.

In the second manufacturing method of a solid-state imaging device according to the embodiment of the invention, the conducting layer that effectively functions as the gate electrode is formed by doping the conductivity-type impurity in the polysilicon film formed on the inner surface of the groove part via the gate insulator film. Further, the gate electrode is formed by the filling layer of the metal film filling the interior of the groove part and the electrode layer connected to the conducting layer. Effectively, the conducting layer has a function of the gate electrode. Therefore, it is not necessary to fill the groove part with the conducting layer, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part in the polysilicon filling the groove part by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part in the polysilicon filling the groove part.

Further, the gate electrodes of the planar transistors of the pixel part and the peripheral circuit part are formed by doping a predetermined conductivity-type impurity in the non-doped polysilicon film. Accordingly, the gate electrode of the N-channel-type transistor and the gate electrode of the P-channel-type transistor are separately formed in N-type and P-type, respectively. In addition, the gate electrode having a minute gate length can be formed.

A manufacturing method of a solid-state imaging device (a third manufacturing method) according to an embodiment of the invention includes the step of forming a pixel part having a photoelectric conversion part that photoelectrically converts incident light to obtain an electric signal, a vertical transistor that reads out signal charge from the photoelectric conversion part, and a planar transistor that processes the readout signal charge, and a peripheral circuit part having a first conductivity-type-channel transistor and a second conductivity-type-channel opposite to the first conductivity-type on a periphery of the pixel part on a semiconductor substrate, and

the step of forming gate electrodes of the respective transistors of the pixel part and the peripheral circuit part includes the steps of

forming a groove part in a region where the vertical transistor is formed on the semiconductor substrate,

forming a gate insulator film on a surface of the semiconductor substrate containing an inner surface of the groove part,

forming a metal film or a metal compound film on the semiconductor substrate containing the inner surface of the groove part in a pixel part formation region via the gate insulator film,

forming a polysilicon film on the gate insulator film containing the metal film or the metal compound film under a non-doped condition,

doping a first conductivity-type impurity in the polysilicon film in a pixel part formation region where the pixel part is formed and the polysilicon film in a region where the first conductivity-type-channel transistor is formed in a peripheral circuit part formation region where the peripheral circuit part is formed and doping a second conductivity-type impurity in the polysilicon film in a region where the second conductivity-type-channel transistor is formed in the peripheral circuit part formation region, and

forming the gate electrode of the vertical transistor, the gate electrode of the planar transistor of the pixel part, and the gate electrodes of the respective transistors of the peripheral circuit part with the metal film or the metal compound film and the polysilicon film.

In the third manufacturing method of a solid-state imaging device according to the embodiment of the invention, the metal film or the metal compound film formed on the inner surface of the groove part via the gate insulator film effectively functions as the gate electrode. Further, the gate electrode is formed by the filling layer of the non-doped polysilicon film filling the interior of the groove part and the polysilicon film doped with the first conductivity-type impurity connected to the metal film or the metal compound film. Effectively, the metal film or the metal compound film has a function of the gate electrode. Therefore, it is not necessary to fill the groove part with the metal film or the metal compound film, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part in the polysilicon filling the groove part by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part in the polysilicon filling the groove part.

Further, the gate electrodes of the planar transistors of the pixel part and the peripheral circuit part are formed by doping a predetermined conductivity-type impurity in the non-doped polysilicon. Accordingly, the gate electrode of the N-channel-type transistor and the gate electrode of the P-channel-type transistor are separately formed in N-type and P-type, respectively. In addition, the gate electrode having a minute gate length can be formed.

A manufacturing method of a solid-state imaging device (a fourth manufacturing method) according to an embodiment of the invention includes the step of forming a pixel part having a photoelectric conversion part that photoelectrically converts incident light to obtain an electric signal, a vertical transistor that reads out signal charge from the photoelectric conversion part, and a planar transistor that processes the read out signal charge, and a peripheral circuit part having a first conductivity-type-channel transistor and a second conductivity-type-channel opposite to the first conductivity-type on a periphery of the pixel part on a semiconductor substrate, and

the step of forming gate electrodes of the respective transistors of the pixel part and the peripheral circuit part includes the steps of

forming a groove part in a region where the vertical transistor is formed on the semiconductor substrate,

forming a gate insulator film on a surface of the semiconductor substrate containing an inner surface of the groove part,

forming a first metal film or a first metal compound film on the semiconductor substrate containing the inner surface of the groove part in a region where the first conductivity-type-channel transistor is formed in a pixel part formation region where the pixel part is formed and in a peripheral circuit part formation region where the peripheral circuit part is formed via the gate insulator film,

forming the second metal film or a second metal compound film having a work function different from that of the first metal film or the first metal compound film on the gate insulator film containing the first metal film or the first metal compound film, and

forming a gate electrode of the vertical transistor, the gate electrode of the planar transistor of the pixel part, and the gate electrode of the first conductivity-type-channel transistor of the peripheral circuit part with the first metal film or the first metal compound film, and forming the gate electrode of the second conductivity-type-channel transistor of the peripheral circuit part with the second metal film or the second metal compound film.

In the fourth manufacturing method of a solid-state imaging device according to the embodiment of the invention, the first metal film or the first metal compound film formed on the inner surface of the groove part via the gate insulator film effectively functions as the gate electrode. Further, the gate electrode is formed by the filling layer of the second metal film or the second metal compound film filling the interior of the groove part and the second metal film or the second metal compound film connected to the first metal film or the first metal compound film. Therefore, it is not necessary to fill the groove part with the polysilicon film, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part in the polysilicon filling the groove part by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part in the polysilicon filling the groove part.

Further, the gate electrodes of the planar transistors of the pixel part and the peripheral circuit part are formed by the first metal film or the first metal compound film and the second metal film or the second metal compound film. For example, when the first conductivity-type is of the N-type and the second conductivity-type is of the P-type, the work function value of the second metal film or the second metal compound film is made larger than that of the first metal film or the first metal compound film. In addition, the gate electrode having a minute gate length can be formed.

An imaging apparatus according to an embodiment of the invention includes:

an imaging optical unit that collects incident light,

a solid-state imaging device that receives and photoelectrically converts the light collected by the imaging optical unit, and

a signal processing unit that processes a photoelectrically converted signal,

wherein the solid-state imaging device includes a pixel part having a photoelectric conversion part that photoelectrically converts incident light to obtain signal charge and a peripheral circuit part formed on a periphery of the pixel part on a semiconductor substrate,

the pixel part has a vertical transistor that reads out the signal charge from the photoelectric conversion part and a planar transistor that processes the signal charge read out by the vertical transistor, and

the vertical transistor has

a groove part formed on the semiconductor substrate;

a gate insulator film formed on an inner surface of the groove part,

a conducting layer formed on a surface of the gate insulator film on the semiconductor substrate within and around the groove part,

a filling layer filling an interior of the groove part via the gate insulator film and the conducting layer, and

an electrode layer connected to the conducting layer on the filling layer.

Therefore, the solid-state imaging device according to the embodiment is applied to the imaging apparatus according to the embodiment.

In the solid-state imaging device according to the embodiment of the invention, the vertical transistor and the planar transistors having minute gate lengths are mounted on the same semiconductor substrate. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized.

In the manufacturing method of a solid-state imaging device according to the embodiment of the invention, the vertical transistor and the planar transistors having minute gate lengths are mounted on the same semiconductor substrate. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized.

In the imaging apparatus according to the embodiment of the invention, the solid-state imaging device according to the embodiment of the invention is used, and there is an advantage that the higher definition and higher image processing speed can be realized.

DESCRIPTION OF PREFERRED EMBODIMENTS

As below, best modes (hereinafter, referred to as embodiments) for implementing the invention will be described.

1. First Embodiment

First Example of Configuration of Solid-State Imaging Device

An example (the first example) of a configuration of a solid-state imaging device according to the first embodiment of the invention will be explained using a schematic configuration sectional view ofFIG. 1.

As shown inFIG. 1, in a semiconductor substrate11, a photoelectric conversion part51that photoelectrically converts incident light to obtain an electric signal is formed. Further, in the semiconductor substrate11, a pixel part12including a vertical transistor21that reads out signal charge from the photoelectric conversion part51and a planar transistor22that processes the read out signal charge is formed. Furthermore, a peripheral circuit part13is formed on the periphery of the pixel part12. The peripheral circuit part13has a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET)23, and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET)24.

As below, details of the configuration will be explained. As the semiconductor substrate11, for example, a P-type semiconductor substrate is used.

The photoelectric conversion part51formed on the semiconductor substrate11includes a photodiode.

For example, an N-type semiconductor region (hereinafter, referred to as “high-density N-type region”)52is formed at the surface side of the semiconductor substrate11. Under the region, an N-type semiconductor region (hereinafter, referred to as “low-density N-type region”)53at the lower density than that of the high-density N-type region52is formed in junction with the region. Furthermore, P-type semiconductor regions (hereinafter, referred to as “low-density P-type regions”)54are formed on the high-density N-type region52.

Around the low-density P-type regions54, P-type semiconductor regions (hereinafter, referred to as “high-density P-type regions”)55at the higher density than that of the low-density P-type regions54are formed.

Further, in the semiconductor substrate11, the pixel parts12, the peripheral circuit part13, and first device isolation regions14that isolate the devices within the peripheral circuit part13are formed. In addition, a second device isolation region15that isolates the pixels is formed within the pixel part12.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

More over, though not shown, well regions are formed in the region where the photoelectric conversion part51is formed, the region where the transistors of the pixel part12are formed, the region where the NFET23and the PFET24of the peripheral circuit part13are formed, and so on.

A groove part31is formed in the region where the gate electrode of the vertical transistor on the semiconductor substrate11. The groove part31is formed to penetrate the low-density P-type regions54and reach the upper part of the high-density N-type region52, and have a width of 0.1 μm to 0.4 μm, for example.

A gate insulator film32is formed on the inner surface of the groove part31. The gate insulator film32is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Further, in the semiconductor substrate11at the bottom side of the groove part31and at the lower side thereof, a low-density P-type region56having nearly equal density to that of the low-density P-type regions54is formed.

On the inner surface of the groove part31and on the semiconductor substrate11around the part, a first polysilicon film33doped with a first conductivity-type impurity (e.g., an N-type impurity) is formed. The first polysilicon film33is formed to have a half thickness of the width of the groove part31so as not to fill the groove part31in a thickness of 30 nm or more, for example.

Further, a second polysilicon film34is formed to fill the groove part31. Regarding the second polysilicon film34, the part inside the groove part31is non-doped and the first conductivity-type impurity (e.g., N-type impurity) is doped on the groove part31.

When the N-type impurity is doped, for example, phosphorus (P) or arsenic (As) is used. Further, when the first conductivity-type impurity is a P-type impurity, for example, boron (B) is used. The doping density doped in the first polysilicon film33is set to density at which the impurity density of 1×1019cm−3can be secured or higher even when the dopant diffuses in the entire polysilicon including the second polysilicon film34within the groove part31.

Accordingly, the gate electrode21G of the vertical transistor21includes a conducting layer35of the first polysilicon film33doped with the N-type impurity, a filling layer36of the second polysilicon film34of the non-doped part, and an electrode layer37of the second polysilicon film34doped with the N-type impurity in the groove part31.

Further, on the semiconductor substrate11in the pixel part12, plural planar transistors22are formed. For example, there are a reset transistor22R, an amplification transistor22A, a selection transistor (not shown). In the drawing, the reset transistor22R and the amplification transistor22A are shown.

In the planar transistor22, for example, a gate electrode22G is formed by a polysilicon film having the same layers as those of the first polysilicon film33and the second polysilicon film34via the gate insulator film32in the pixel part12of the semiconductor substrate11. The polysilicon film is doped with the first conductivity-type impurity (e.g., the N-type impurity).

In the NFET23, for example, a gate electrode23G is formed by a polysilicon film having the same layers as those of the second polysilicon film34via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11. The polysilicon film is doped with the first conductivity-type impurity (e.g., the N-type impurity).

Further, in the PFET24, for example, a gate electrode24G is formed by a polysilicon film having the same layers as those of the second polysilicon film34via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11. The polysilicon film is doped with the second conductivity-type impurity (e.g., the P-type impurity).

On the semiconductor substrate11on both sides of the gate electrode22G of the planar transistor22, source and drain regions25,26are formed.

Here, for example, the source and drain region26of the reset transistor22R and the source and drain region25of the amplification transistor22A are formed by a common diffusion layer. Further, the source and drain region26of the amplification transistor22A and the source and drain region (not shown) of the selection transistor (not shown) are formed by a common diffusion layer.

Furthermore, the source and drain region25of the reset transistor22R at the vertical transistor side and the source and drain region of the vertical transistor21are common. The common diffusion layer is a floating diffusion FD.

In addition, these diffusion layers may be common or connected using metal wiring.

Therefore, the vertical transistor21is a transfer transistor that reads out the signal charge photoelectrically converted by the photoelectric conversion part51.

On the other hand, on the semiconductor substrate11on both sides of the gate electrode23G of the planar transistor23in the peripheral circuit part13, source and drain regions27,28are formed.

Further, on the semiconductor substrate11on both sides of the gate electrode24G of the planar transistor24, source and drain regions29,30are formed.

Note that, in the source and drain regions25to30of the planar transistors22to24, extension regions (not shown) may be formed according to need.

Further, on the semiconductor substrate11, a wiring layer81is formed. For example, the wiring layer81includes plural layers of wires82, plugs83connecting between the wires, and an insulator film84covering the wires82. The insulator film84is formed in plural layers, and the lowermost insulator film85covers the respective gate electrodes21G to24G. Furthermore, the plural layers of wires82are formed in two layers in the drawing, however, the number of layers may be three, four, or more according to need.

In addition, a support substrate (not shown) is formed at the wiring layer81side. The side of the semiconductor substrate11at which the photoelectric conversion part51is formed is formed to have a desired thickness, and a color filter layer, a collector lens (microlens), etc. are formed thereon.

In the solid-state imaging device1according to the embodiment of the invention, inside the groove part31, the conducting layer35formed via the gate insulator film32on the inner surface thereof, the filling layer36filing the interior of the groove part31, and the gate electrode21G formed by the electrode layer37connected to the conducting layer35are formed. Effectively, the conducting layer35has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

Therefore, the vertical transistor21can be configured and the vertical transistor and the planar transistors having minute gate lengths are mounted on the same semiconductor substrate. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized.

2. Second Embodiment

Second Example of Configuration of Solid-State Imaging Device

An example (the second example) of a configuration of a solid-state imaging device according to the second embodiment of the invention will be explained using a schematic configuration sectional view ofFIG. 2.

As shown inFIG. 2, in a semiconductor substrate11, a photoelectric conversion part51that photoelectrically converts incident light to obtain an electric signal is formed. Further, in the semiconductor substrate11, a pixel part12including a vertical transistor21that reads out signal charge from the photoelectric conversion part51and a planar transistor22that processes the read out signal charge is formed. Furthermore, a peripheral circuit part13is formed on the periphery of the pixel part12. The peripheral circuit part13has a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET)23, and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET)24.

As below, details of the configuration will be explained. As the semiconductor substrate11, for example, a P-type semiconductor substrate is used.

The photoelectric conversion part51formed on the semiconductor substrate11includes a photodiode.

For example, an N-type semiconductor region (hereinafter, referred to as “high-density N-type region”)52is formed at the surface side of the semiconductor substrate11. Under the region, an N-type semiconductor region (hereinafter, referred to as “low-density N-type region”)53at the lower density than that of the high-density N-type region52is formed in junction with the region. Furthermore, P-type semiconductor regions (hereinafter, referred to as “low-density P-type regions”)54are formed on the high-density N-type region52.

Around the low-density P-type regions54, P-type semiconductor regions (hereinafter, referred to as “high-density P-type regions”)55at the higher density than that of the low-density P-type regions54are formed.

Further, in the semiconductor substrate11, the pixel parts12, the peripheral circuit part13, and first device isolation regions14that isolate the devices within the peripheral circuit part13are formed. In addition, a second device isolation region15that isolates the pixels is formed within the pixel part12.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

More over, though not shown, well regions are formed in the regions where the photoelectric conversion parts51are formed, the regions where the transistors of the pixel part12are formed, the regions where the NFET23and the PFET24of the peripheral circuit part13are formed, and so on.

A groove part31is formed in the region where the gate electrode of the vertical transistor on the semiconductor substrate11. The groove part31is formed to penetrate the low-density P-type regions54and reach the upper part of the high-density N-type region52, and have a width of 0.1 μm to 0.4 μm, for example.

A gate insulator film32is formed on the inner surface of the groove part31. The gate insulator film32is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Further, in the semiconductor substrate11at the bottom side of the groove part31and at the lower side thereof, a low-density P-type region56having nearly equal density to that of the low-density P-type regions54is formed.

On the inner surface of the groove part31and on the semiconductor substrate11around the part, a conducting layer including a polysilicon film38doped with a first conductivity-type impurity (e.g., an N-type impurity) is formed. The conducting layer35is formed to have a half thickness of the width of the groove part31so as not to fill the groove part31in a thickness of 30 nm or more, for example.

When the N-type impurity is doped, for example, phosphorus (P) or arsenic (As) is used. Further, when the first conductivity-type impurity is a P-type impurity, for example, boron (B) is used. The doping density doped in the polysilicon film38is set to density at which the impurity density of 1×1019cm−3can be secured or higher.

Further, a metal (or a metal compound) film39is formed to fill the groove part31. For the metal film, for example, a metal such as tungsten or nickel may be used. For the metal compound film, for example, a metal nitride such as tungsten nitride or titanium nitride, or a metal silicide such as nickel silicide or cobalt silicide may be used.

Accordingly, the gate electrode21G of the vertical transistor21includes the conducting layer35, the filling layer36of the metal (or the metal compound) film39, and an electrode layer37.

Further, on the semiconductor substrate11in the pixel part12, plural planar transistors22are formed. For example, there are a reset transistor22R, an amplification transistor22A, a selection transistor (not shown). In the drawing, the reset transistor22R and the amplification transistor22A are shown.

In the planar transistor22, for example, a gate electrode22G is formed by a polysilicon film38having the same layers as those of the polysilicon film38and a metal (or a metal compound) film39having the same layers as those of the metal (or the metal compound) film39via the gate insulator film32in the pixel part12of the semiconductor substrate11. The polysilicon film38is doped with the first conductivity-type impurity (e.g., the N-type impurity).

Furthermore, on the semiconductor substrate11of the peripheral circuit part13, an NFET23and a PFET24of planar transistors are formed.

In the NFET23, for example, a gate electrode23G is formed by a polysilicon film38having the same layers as those of the polysilicon film38and a metal (or a metal compound) film39having the same layers as those of the metal (or the metal compound) film39via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11. The polysilicon film is doped with the first conductivity-type impurity (e.g., the N-type impurity).

Further, in the PFET24, for example, a gate electrode24G is formed by a polysilicon film40having the same layers as those of the polysilicon film38and doped with the second conductivity-type impurity (e.g., the P-type impurity) and a metal (or a metal compound) film39having the same layers as those of the metal (or the metal compound) film39via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11.

On the semiconductor substrate11on both sides of the gate electrode22G of the planar transistor22, source and drain regions25,26are formed.

Here, for example, the source and drain region26of the reset transistor22R and the source and drain region25of the amplification transistor22A are formed by a common diffusion layer. Further, the source and drain region26of the amplification transistor22A and the source and drain region (not shown) of the selection transistor (not shown) are formed by a common diffusion layer.

Furthermore, the source and drain region25of the reset transistor22R at the vertical transistor side and the source and drain region of the vertical transistor21are common. The common diffusion layer is a floating diffusion FD.

In addition, these diffusion layers may be common or connected using metal wiring.

Therefore, the vertical transistor21is a transfer transistor that reads out the signal charge photoelectrically converted by the photoelectric conversion part51.

On the other hand, on the semiconductor substrate11on both sides of the gate electrode23G of the planar transistor NFET23in the peripheral circuit part13, source and drain regions27,28are formed.

Further, on the semiconductor substrate11on both sides of the gate electrode24G of the planar transistor PFET24, source and drain regions29,30are formed.

Note that, in the source and drain regions25to30of the planar transistors22, NFET23, PFET24, extension regions (not shown) may be formed according to need.

Further, on the semiconductor substrate11, a wiring layer81is formed. For example, the wiring layer81includes plural layers of wires82, plugs83connecting between the wires, and an insulator film84covering the wires82. The insulator film84is formed in plural layers, and the lowermost insulator film85covers the respective gate electrodes21G to24G. Furthermore, the plural layers of wires82are formed in two layers in the drawing, however, the number of layers may be three, four, or more according to need.

In addition, a support substrate (not shown) is formed at the wiring layer81side. The side of the semiconductor substrate11at which the photoelectric conversion part51is formed is formed to have a desired thickness, and a color filter layer, a collector lens (microlens), etc. are formed thereon.

In the solid-state imaging device2according to the embodiment of the invention, inside the groove part31, the conducting layer35formed via the gate insulator film32on the inner surface thereof, the filling layer36filing the interior of the groove part31, and the gate electrode21G formed by the electrode layer37connected to the conducting layer35are formed. Effectively, the conducting layer35has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

Therefore, the vertical transistor21can be configured and the vertical transistor and the planar transistors22, NFET23, PFET24having minute gate lengths are mounted on the same semiconductor substrate11. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized.

Third Example of Configuration of Solid-State Imaging Device

An example (the third example) of a configuration of a solid-state imaging device according to the third embodiment of the invention will be explained using a schematic configuration sectional view ofFIG. 3.

As shown inFIG. 3, in a semiconductor substrate11, a photoelectric conversion part51that photoelectrically converts incident light to obtain an electric signal is formed. Further, in the semiconductor substrate11, a pixel part12including a vertical transistor21that reads out signal charge from the photoelectric conversion part51and a planar transistor that processes the read out signal charge is formed. Furthermore, a peripheral circuit part13is formed around on the periphery of the pixel part12. The peripheral circuit part13has a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET)23, and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET)24.

As below, details of the configuration will be explained. As the semiconductor substrate11, for example, a P-type semiconductor substrate is used.

The photoelectric conversion part51formed on the semiconductor substrate11includes a photodiode.

For example, an N-type semiconductor region (hereinafter, referred to as “high-density N-type region”)52is formed at the surface side of the semiconductor substrate11. Under the region, an N-type semiconductor region (hereinafter, referred to as “low-density N-type region”)53at the lower density than that of the high-density N-type region52is formed in junction with the region. Furthermore, P-type semiconductor regions (hereinafter, referred to as “low-density P-type regions”)54are formed on the high-density N-type region52.

Around the low-density P-type regions54, P-type semiconductor regions (hereinafter, referred to as “high-density P-type regions”)55at the higher density than that of the low-density P-type regions54are formed.

Further, in the semiconductor substrate11, the pixel parts12, the peripheral circuit part13, and first device isolation regions14that isolate the devices within the peripheral circuit part13are formed. In addition, a second device isolation region15that isolates the pixels is formed within the pixel part12.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

More over, though not shown, well regions are formed in the regions where the photoelectric conversion parts51are formed, the regions where the planar transistors of the pixel part12are formed, the regions where the planar transistors NFET23and PFET24of the peripheral circuit part13are formed, and so on.

A groove part31is formed in the region where the gate electrode of the vertical transistor on the semiconductor substrate11. The groove part31is formed to penetrate the low-density P-type regions54and reach the upper part of the high-density N-type region52, and have a width of 0.1 μm to 0.4 μm, for example. A gate insulator film32is formed on the inner surface of the groove part31. The gate insulator film32is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Alternatively, as the gate insulator film32, a film including an oxide, silicate, nitrided oxide, or oxidized nitrided silicate containing at least one kind selected from silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), lanthanum (La), hafnium (Hf), and tantalum (Ta) may be used.

Specifically, silicon oxide (SiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O3), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium titanate (ZrTiOx), hafnium aluminum oxide (HfAlOx), zirconium aluminum oxide (ZrAlOx), and further, nitride of them (silicon oxynitride (SiON), hafnium silicide oxynitride (HfSiON), etc.) are cited. The relative permittivity of these materials may slightly vary depending on composition and crystalline property. For example, the relative permittivity of HfO2is 25 to 30, and the relative permittivity of ZrO2is 20 to 25.

Further, in the semiconductor substrate11at the bottom side of the groove part31and at the lower side thereof, a low-density P-type region56having nearly equal density to that of the low-density P-type regions54is formed.

On the inner surface of the groove part31and on the semiconductor substrate11around the part, a conducting layer35including a metal film or metal compound film41is formed via the gate insulator film32. For the metal film, for example, hafnium (Hf) or lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31. As the metal compound film, for example, hafnium silicide or silicide of lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31.

Note that, a film that controls a work function may be used for the conducting layer35.

For example, in the case of NFET, its gate electrode has a work function less than 4.6 eV, desirably equal to less than 4.3 eV. In the case of PFET, its gate electrode has a work function equal to or more than 4.6 eV, desirably equal to more than 4.9 eV.

For example, an example of the work-function control film, there are metals of titanium (Ti), vanadium (V), nickel (Ni), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), Hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), alloys containing these metals, and compounds of these metals. As the metal compounds, there are metal nitrides and compounds of metal and semiconductor. The compounds of metal and semiconductor include a metal silicate as an example.

As an example of the work-function control film suitable for NFET, there are metals such as hafnium (Hf) and tantalum (Ta), and alloys containing these metals, and compounds of these metals, and specifically, hafnium silicate (HfSix) is more preferable. The hafnium silicate for nMOSFET has a work function of about 4.1 eV to 4.3 eV.

As an example of the work-function control film suitable for PFET, there are metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru) and alloys containing these metals, and compounds of these metals. Specifically, titanium nitride (TiN) or ruthenium (Ru) is more preferable. The titanium nitride for pMOSFET has a work function of about 4.5 eV to 5.0 eV.

Further, a polysilicon film42is formed to fill the groove part31. Regarding the polysilicon film42, the part inside the groove part31is a non-doped polysilicon film42and the part on the groove part31is a polysilicon film43doped with the first conductivity-type impurity (e.g., N-type impurity).

When the N-type impurity is doped, for example, phosphorus (P) or arsenic (As) is used. Further, when the first conductivity-type impurity is a P-type impurity, for example, boron (B) is used. The doping density doped in the polysilicon film43is set to density at which the impurity density of 1×1019cm−3can be secured or higher even when the dopant diffuses in the entire polysilicon including the polysilicon film42within the groove part31.

Accordingly, the gate electrode21G of the vertical transistor21includes the conducting layer35including the metal film or the metal compound film41, a filling layer36of the polysilicon film42of the non-doped part, and an electrode layer37of the polysilicon film43doped with the N-type impurity in the groove part31.

Further, on the semiconductor substrate11in the pixel part12, plural planar transistors22are formed. For example, there are a reset transistor22R, an amplification transistor22A, a selection transistor (not shown). In the drawing, the reset transistor22R and the amplification transistor22A are shown.

In the planar transistor22, for example, a gate electrode22G is formed by a polysilicon film having the same layers as those of the conducting layer35and the polysilicon film42via the gate insulator film32in the pixel part12of the semiconductor substrate11. The polysilicon film is doped with the first conductivity-type impurity (e.g., the N-type impurity).

In the NFET23, for example, a gate electrode23G is formed by a polysilicon film having the same layers as those of the polysilicon film42via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11. The polysilicon film is doped with the first conductivity-type impurity (e.g., the N-type impurity).

Further, in the PFET24, for example, a gate electrode24G is formed by a polysilicon film44doped with the second conductivity-type impurity (e.g., the P-type impurity) via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11.

On the semiconductor substrate11on both sides of the gate electrode22G of the planar transistor22, source and drain regions25,26are formed.

Here, for example, the source and drain region26of the reset transistor22R and the source and drain region25of the amplification transistor22A are formed by a common diffusion layer. Further, the source and drain region26of the amplification transistor22A and the source and drain region (not shown) of the selection transistor (not shown) are formed by a common diffusion layer.

Furthermore, the source and drain region25of the reset transistor22R at the vertical transistor side and the source and drain region of the vertical transistor21are common. The common diffusion layer is a floating diffusion FD.

In addition, these diffusion layers may be common or connected using metal wiring.

Therefore, the vertical transistor21is a transfer transistor that reads out the signal charge photoelectrically converted by the photoelectric conversion part51.

On the other hand, on the semiconductor substrate11on both sides of the gate electrode23G of the planar transistor23in the peripheral circuit part13, source and drain regions27,28are formed.

Further, on the semiconductor substrate11on both sides of the gate electrode24G of the planar transistor24, source and drain regions29,30are formed.

Note that, in the source and drain regions25to30of the planar transistors22to24, extension regions (not shown) may be formed according to need.

Further, on the semiconductor substrate11, a wiring layer81is formed. For example, the wiring layer81includes plural layers of wires82, plugs83connecting between the wires, and an insulator film84covering the wires82. The insulator film84is formed in plural layers, and the lowermost insulator film85covers the respective gate electrodes21G to24G. Furthermore, the plural layers of wires82are formed in two layers in the drawing, however, the number of layers may be three, four, or more according to need.

In addition, a support substrate (not shown) is formed at the wiring layer81side. The side of the semiconductor substrate11at which the photoelectric conversion part51is formed is formed to have a desired thickness, and a color filter layer, a collector lens (microlens), etc. are formed thereon.

In the solid-state imaging device3according to the embodiment of the invention, inside the groove part31, the conducting layer35formed via the gate insulator film32on the inner surface thereof, the filling layer36filing the interior of the groove part31, and the gate electrode21G formed by the electrode layer37connected to the conducting layer35are formed. Effectively, the conducting layer35has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

Therefore, the vertical transistor21can be configured and the vertical transistor and the planar transistors22, NFET23, PFET24having minute gate lengths are mounted on the same semiconductor substrate11. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized.

Fourth Example of Configuration of Solid-State Imaging Device

An example (the fourth example) of a configuration of a solid-state imaging device according to the fourth embodiment of the invention will be explained using a schematic configuration sectional view ofFIG. 4.

As shown inFIG. 4, in a semiconductor substrate11, a photoelectric conversion part51that photoelectrically converts incident light to obtain an electric signal is formed. Further, in the semiconductor substrate11, a pixel part12including a vertical transistor21that reads out signal charge from the photoelectric conversion part51and a planar transistor that processes the read out signal charge is formed. Furthermore, a peripheral circuit part13is formed around on the periphery of the pixel part12. The peripheral circuit part13has a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET)23, and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET)24.

As below, details of the configuration will be explained. As the semiconductor substrate11, for example, a P-type semiconductor substrate is used.

The photoelectric conversion part51formed on the semiconductor substrate11includes a photodiode.

For example, an N-type semiconductor region (hereinafter, referred to as “high-density N-type region”)52is formed at the surface side of the semiconductor substrate11. Under the region, an N-type semiconductor region (hereinafter, referred to as “low-density N-type region”)53at the lower density than that of the high-density N-type region52is formed in junction with the region. Furthermore, P-type semiconductor regions (hereinafter, referred to as “low-density P-type regions”)54are formed on the high-density N-type region52.

Around the low-density P-type regions54, P-type semiconductor regions (hereinafter, referred to as “high-density P-type regions”)55at the higher density than that of the low-density P-type regions54are formed.

Further, in the semiconductor substrate11, the pixel parts12, the peripheral circuit part13, and first device isolation regions14that isolate the devices within the peripheral circuit part13are formed. In addition, a second device isolation region15that isolates the pixels is formed within the pixel part12.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

More over, though not shown, well regions are formed in the regions where the photoelectric conversion parts51are formed, the regions where the transistors of the pixel part12are formed, the regions where the NFET23and the PFET24of the peripheral circuit part13are formed, and so on.

A groove part31is formed in the region where the gate electrode of the vertical transistor on the semiconductor substrate11. The groove part31is formed to penetrate the low-density P-type regions54and reach the upper part of the high-density N-type region52, and have a width of 0.1 μm to 0.2 μm, for example.

A gate insulator film32is formed on the inner surface of the groove part31. The gate insulator film32is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Alternatively, as the gate insulator film32, a film including an oxide, silicate, nitrided oxide, or oxidized nitrided silicate containing at least one kind selected from silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), lanthanum (La), hafnium (Hf), and tantalum (Ta) may be used.

Specifically, silicon oxide (SiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium titanate (ZrTiOx), hafnium aluminum oxide (HfAlOx), zirconium aluminum oxide (ZrAlOx), and further, nitride of them (silicon oxynitride (SiON), hafnium silicide oxynitride (HfSiON), etc.) are cited. The relative permittivity of these materials may slightly vary depending on composition and crystalline property. For example, the relative permittivity of HfO2is 25 to 30, and the relative permittivity of ZrO2is 20 to 25.

Further, in the semiconductor substrate11at the bottom side of the groove part31and at the lower side thereof, a low-density P-type region56having nearly equal density to that of the low-density P-type regions54is formed.

On the inner surface of the groove part31and on the semiconductor substrate11around the part, a first conducting layer47including a metal film or metal compound film is formed via the gate insulator film32. For the metal film, for example, hafnium (Hf) or lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31. As the metal compound film, for example, hafnium silicide or silicide of lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31.

Further, a film that controls a work function may be used for the first conducting layer47.

For example, in the case of NFET, its gate electrode has a work function less than 4.6 eV, desirably equal to less than 4.3 eV. In the case of PFET, its gate electrode has a work function equal to or more than 4.6 eV, desirably equal to more than 4.9 eV.

For example, an example of the work-function control film, there are metals of titanium (Ti), vanadium (V), nickel (Ni), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), alloys containing these metals, and compounds of these metals. As the metal compounds, there are metal nitrides and compounds of metal and semiconductor. The compounds of metal and semiconductor include a metal silicate as an example.

As an example of the work-function control film suitable for NFET, there are metals such as hafnium (Hf) and tantalum (Ta), and alloys containing these metals, and compounds of these metals, and specifically, hafnium silicate (HfSix) is more preferable. The hafnium silicate for nMOSFET has a work function of about 4.1 eV to 4.3 eV.

As an example of the work-function control film suitable for PFET, there are metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru) and alloys containing these metals, and compounds of these metals. Specifically, titanium nitride (TiN) or ruthenium (Ru) is more preferable. The titanium nitride for pMOSFET has a work function of about 4.5 eV to 5.0 eV.

The first conducting layer47has the gate electrode of NFET, and a work-function control film suitable for NFET is used therefor.

Further, a second conducting layer48including a metal layer or a metal compound layer is formed on the first conducting layer47to fill the groove part31.

Accordingly, the gate electrode21G of the vertical transistor21includes the conducting layer35of the first conducting layer47, a filling layer36of the second conducting layer48, and an electrode layer37of the second conducting layer48in the groove part31.

Further, on the semiconductor substrate11in the pixel part12, plural planar transistors22are formed. For example, there are a reset transistor22R, an amplification transistor22A, a selection transistor (not shown). In the drawing, the reset transistor22R and the amplification transistor22A are shown.

In the planar transistor22, for example, a gate electrode22G is formed by a polysilicon film having the same layers as those of the first conducting layer47and the second conducting layer48via the gate insulator film32in the pixel part12of the semiconductor substrate11.

In the NFET23, for example, a gate electrode23G is formed by a film having the same layers as those of the first conducting layer47and the second conducting layer48via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11.

Further, in the PFET24, for example, a gate electrode24G is formed by a film having the same layers as the second conducting layer48via the gate insulator film32in the peripheral circuit part13of the semiconductor substrate11. Therefore, the second conducting layer48forms the gate electrode of the NFET and it is preferable to use the work-function control film suitable for the NFET.

As an example of a material used for the second conducting layer48, there are metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru), alloys containing these metals, and compounds of these metals. Specifically, titanium nitride (TiN) or ruthenium (Ru) is more preferable. The titanium nitride for PFET has a work function of about 4.5 eV to 5.0 eV.

On the semiconductor substrate11on both sides of the gate electrode22G of the planar transistor22, source and drain regions25,26are formed.

Here, for example, the source and drain region26of the reset transistor22R and the source and drain region25of the amplification transistor22A are formed by a common diffusion layer. Further, the source and drain region26of the amplification transistor22A and the source and drain region (not shown) of the selection transistor (not shown) are formed by a common diffusion layer.

Furthermore, the source and drain region25of the reset transistor22R at the vertical transistor side and the source and drain region of the vertical transistor21are common. The common diffusion layer is a floating diffusion FD.

In addition, these diffusion layers may be common or connected using metal wiring.

Therefore, the vertical transistor21is a transfer transistor that reads out the signal charge photoelectrically converted by the photoelectric conversion part51.

On the other hand, on the semiconductor substrate11on both sides of the gate electrode23G of the planar transistor NFET23in the peripheral circuit part13, source and drain regions27,28are formed.

Further, on the semiconductor substrate11on both sides of the gate electrode24G of the planar transistor PFET24, source and drain regions29,30are formed.

Note that, in the source and drain regions25to30of the planar transistors22, NFET23, PFET24, extension regions (not shown) may be formed according to need.

Further, on the semiconductor substrate11, a wiring layer81is formed. For example, the wiring layer81includes plural layers of wires82, plugs83connecting between the wires, and an insulator film84covering the wires82. The insulator film84is formed in plural layers, and the lowermost insulator film85covers the respective gate electrodes21G to24G. Furthermore, the plural layers of wires82are formed in two layers in the drawing, however, the number of layers may be three, four, or more according to need.

In addition, a support substrate (not shown) is formed at the wiring layer81side. The side of the semiconductor substrate11at which the photoelectric conversion part51is formed is formed to have a desired thickness, and a color filter layer, a collector lens (microlens), etc. are formed thereon.

In the solid-state imaging device4according to the embodiment of the invention, inside the groove part31, the conducting layer35formed via the gate insulator film32on the inner surface thereof, the filling layer36filing the interior of the groove part31, and the gate electrode21G formed by the electrode layer37connected to the conducting layer35are formed. Effectively, the conducting layer35has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

Therefore, the vertical transistor21can be configured and the vertical transistor and the planar transistors22, NFET23, PFET24having minute gate lengths are mounted on the same semiconductor substrate. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized.

Further, in the solid-state imaging devices1to4, the main pn-junction of the photoelectric conversion part51is formed by the high-density P-type regions55and the high-density P-type regions52. Therefore, the pn-junction is formed within the semiconductor substrate11with a part of the pn-junction extending under the planar transistor22of the pixel part12. For example, seen from the side of the semiconductor substrate11surface (opposite to the light entrance side), the photodiode3is formed over the region adjacent unit pixels sectioned by the second device isolation region15for pixel isolation. Seen from the rear side of the semiconductor substrate11(the light entrance side), the region of the photoelectric conversion part51corresponds to the region of unit pixels.

In the solid-state imaging devices1to4, the photoelectric conversion part51is provided under the transfer transistor of the vertical transistor21, the reset transistor22R, the amplification transistor22A, the selection transistor (not shown) of the planar transistors22, etc. formed on the pixel part12. In this manner, the photoelectric conversion part51is sterically arranged with respect to the respective transistors of the pixel part12, and thus, as its area is increased, the pixel area can be reduced. Therefore, the larger area of the photoelectric conversion part51can be secured and the incident light can be taken from the rear surface of the semiconductor substrate11, and thereby, miniaturization of the pixel size can be realized without reduction in saturated charge quantity (Qs) and sensitivity.

The channel part of the vertical transistor21reads out the photoelectrically converted signal charge from the photoelectric conversion part51. For the purpose, the gate electrode21G of the vertical transistor21is located at the center of the photoelectric conversion part51, and the signal charge generated in the entire photoelectric conversion part51is efficiently read out through the channel part to the vertical transistor21. Therefore, the signal charge can be easily read out from the photoelectric conversion part51.

Further, the high-density N-type region52of the photoelectric conversion part51also serves as the source and drain region of the vertical transistor21, and the effective channel length is determined depending on the depth of the vertical transistor21.

Furthermore, in the vertical transistor21, its gate electrode and the bottom part of the gate insulator film32are formed in the position at the depth equal or more than the depth of the pn-junction part (the interface between the high-density N-type region52and the high-density P-type region55) of the photoelectric conversion part51. Thereby, the channel of the vertical transistor21is reliably formed between the photoelectric conversion part51and the source and drain region25, and the operation of the vertical transistor21can be reliably performed.

Moreover, the low-density P-type region56is formed between the gate insulator film32of the vertical transistor21and the high-density N-type region52of the photoelectric conversion part51, and thereby, generation of leak current due to defects of the photoelectric conversion part51is suppressed. In addition, the low-density P-type region54is formed between the gate insulator film32of the vertical transistor21and the high-density P-type region55of the photoelectric conversion part51, and thereby, charge transfer by the vertical transistor21becomes easier while the charge accumulation capacity of the photoelectric conversion part51is held.

Note that, in the solid-state imaging devices1to4, the configuration in which the vertical transistor21as the transfer transistor, the reset transistor22R, the amplification transistor22A, the selection transistor, etc. are connected by the diffusion layer has been illustrated, however, the respective transistors may be isolated by device isolation regions and connected by wiring.

[One Example of CMOS Solid-State Imaging Device to which Respective Solid-State Imaging Devices can be Applied]

Here, one example of CMOS solid-state imaging device to which the respective solid-state imaging devices1to4described inFIGS. 1 to 4can be applied will be explained according to a circuit configuration diagram ofFIG. 5.

As shown inFIG. 5, a solid-state imaging device (CMOS image sensor)201has a pixel part210in which pixels211containing photoelectric conversion parts are two-dimensionally arranged in a matrix (corresponding to the pixel part12inFIGS. 1 to 4), and a peripheral circuit part220(corresponding to the peripheral circuit part13inFIGS. 1 to 4) including drive circuits221that independently control control signal lines, a pixel vertical scan circuit223, a timing generator circuit225, a horizontal scan circuit227, etc. as a peripheral circuit thereof. The pixel part210corresponds to the pixel part12described usingFIGS. 1 to 4. The peripheral circuit part220corresponds to the peripheral circuit part13described usingFIGS. 1 to 4.

For the matrix arrangement of pixels211, an output signal line241is provided with respect to each column and a control signal line is provided with respect to each row. As these control signal lines, for example, transfer control lines242, reset control lines243and selection control lines244are provided. Furthermore, a reset line245that supplies a reset voltage is provided for each pixel211.

An example of the circuit configuration of the pixel221is shown. The unit pixel according to the circuit example includes a photodiode as a photoelectric conversion element in a light receiving part231and is a pixel circuit having four transistors of a transfer transistor232, a reset transistor233, an amplification transistor234, and a selection transistor235, for example. The photodiode corresponds to the photoelectric conversion part51described usingFIGS. 1 to 4. Further, the transfer transistor232corresponds to the vertical transistor21described usingFIGS. 1 to 4. Furthermore, the reset transistor233corresponds to the reset transistor22R described usingFIGS. 1 to 4and the amplification transistor234corresponds to the amplification transistor22A described usingFIGS. 1 to 4. Moreover, the selection transistor235corresponds to the selection transistor described usingFIGS. 1 to 4. Here, as the transfer transistor232, the reset transistor233, the amplification transistor234, and the selection transistor235, for example N-channel MOS transistors are used.

The transfer transistor232is connected between the cathode electrode of the photodiode in the light receiving part231and a floating diffusion part236as a charge-voltage conversion part. The floating diffusion part236corresponds to the floating diffusion part FD described usingFIGS. 1 to 4. The signal charge (here, electrons) photoelectrically converted and accumulated in the light receiving part231are transferred to the floating diffusion part236when a transfer pulse is provided to the gate electrode (control electrode) of the transfer transistor232.

In the reset transistor233, the drain electrode is connected to the reset line245and the source electrode is connected to the floating diffusion part236. When a reset pulse is provided to the gate electrode prior to the transfer of signal charge from the light receiving part231to the floating diffusion part236, the potential of the floating diffusion part236is reset to a reset voltage.

In the amplification transistor234, the gate electrode is connected to the floating diffusion part236and the drain electrode is connected to a pixel power supply Vdd. The transistor outputs the potential of the floating diffusion part236after reset by the reset transistor233as a reset level. Further, the transistor outputs the potential of the floating diffusion part236after the signal charge is transferred by the transfer transistor232as a signal level.

In the selection transistor235, for example, the drain electrode is connected to the source electrode of the amplification transistor234and the source electrode is connected to the output signal line241. The transistor is turned on when a selection pulse is provided to the gate electrode, and outputs the signal output from the amplification transistor234with the pixel211in the selected state to the output signal line241. Note that a configuration in which the selection transistor235is connected between the pixel power supply Vdd and the drain electrode of the amplification transistor234may be adopted.

The drive circuit221is adapted to perform readout operation of reading out the signal of each pixel211in the readout row of the pixel part210.

The pixel vertical scan circuit223includes a shift register, an address decoder, or the like. The circuit appropriately generates the reset pulse, the transfer pulse, the selection pulse, and the like, and thereby, vertically scans the respective pixels211of the pixel part210with respect to each electron shutter row and readout row in units of rows. Concurrently, the circuit performs electron shutter operation on the electron shutter rows for signal sweeping of the pixels211in the rows. The circuit performs electron shutter operation on the same row (electron shutter row) for the time corresponding to the shutter speed before the readout scan by the drive circuit221.

The horizontal scan circuit227includes a shift register, an address decoder, or the like, and performs horizontal scan with respect to each pixel column of the pixel part210.

The timing generator circuits225generates timing signals and control signals as reference for the operations of the drive circuits221, the pixel vertical scan circuit223, etc.

The configuration of the solid-state imaging device (CMOS image sensor)201is only an example, and not limited to the configuration.

One Example of First Manufacturing Method of Solid-State Imaging Device

Next, one example of the first manufacturing method of a solid-state imaging device according to the fifth embodiment of the invention will be explained using manufacturing process sectional views ofFIGS. 6 to 14.

The first manufacturing method of a solid-state imaging device according to the embodiment of the invention forms a photoelectric conversion part for photoelectrically converting incident light to obtain an electric signal, and a pixel part including a vertical transistor that reads out the signal charge from the photoelectric conversion part and planar transistors that process the read out signal charge. Concurrently, a peripheral circuit part is formed on the periphery of the pixel part. The peripheral circuit part is formed to have a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET), and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET).

The process of forming the gate electrodes of the respective transistors in the pixel part and the peripheral circuit part are as below.

[Manufacturing Process of Gates of Respective Transistors]

As shown in (1) inFIG. 6, in the semiconductor substrate11, first device isolation regions14that isolate a pixel part formation region16where the pixel part is formed and a peripheral circuit part formation region17where the peripheral circuit part are formed. Concurrently, a second device isolation region15that isolates the pixels is formed within the pixel part formation region16is formed.

Further, though not shown, well regions are formed in the region where the photoelectric conversion part is formed, the region where the transistors of the pixel part are formed, the region where NFET, OPFET of the peripheral circuit part are formed, and so on.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

Furthermore, though not shown in the drawing, the photoelectric conversion part, details of which will be described later, is formed in the semiconductor substrate11of the pixel part formation region16.

Then, a groove part31is formed in the region where the gate electrode of the vertical transistor of the semiconductor substrate11. The groove part31is formed by dry etching using a resist mask, for example, to have a width of 0.1 μm to 0.4 μm, for example. The resist mask used as the etching mask is removed after the groove part31is formed.

Then, a gate insulator film32is formed on the surface of the semiconductor substrate11including the inner surface of the groove part31. For example, the gate insulator film is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Then, as shown in (2) inFIG. 6, on the semiconductor substrate11including the inner surface of the groove part31, a first polysilicon film33is formed under the non-doped condition via the gate insulator film32. For example, by chemical vapor deposition, the first polysilicon film33is formed to have a half thickness of the width of the groove part31so as not to fill the groove part31in a thickness of 30 nm or more, for example.

Furthermore, a protector film61is formed on the first polysilicon film33. The protector film61is a silicon oxide film, for example, and formed to have a thickness equal to or more than 10 nm, for example. The silicon oxide film is formed by a film formation technology such as thermal oxidation, chemical vapor deposition, or the like.

Then, as shown in (3) inFIG. 7, a resist mask62is formed on the protector film61of the peripheral circuit part formation region17. Then, using the resist mask62as an etching mask, the protector film61is removed and the first polysilicon film33is exposed on the pixel part formation region16.

Then, the resist mask62is removed. In the drawing, the state immediately before the removal of the resist mask62is shown.

Then, as shown in (4) inFIG. 7, a first conductivity-type impurity (e.g., an N-type impurity) is doped in the first polysilicon film33of the pixel part formation region16. For example, isotropic doping such as vapor-phase doping is used. When the N-type impurity is doped, for example, phosphorus (P) or arsenic (As) is used, and, when a P-type impurity is doped, for example, boron (B) is used. The doping density is set to density at which the impurity density of 1×1019cm−3can be secured or higher even when the dopant diffuses in the entire polysilicon including a second polysilicon film, which will be formed later.

Then, the protector film61is removed. In the drawing, the state immediately before the removal of the protector film61is shown.

As a result, as shown in (5) inFIG. 8, the first polysilicon film33is doped with the impurity in the pixel part formation region16but non-doped in the peripheral circuit part formation region17.

Then, as shown in (6) inFIG. 8, the second polysilicon film34is formed on the first polysilicon film33under the non-doped condition.

Then, as shown in FIG.9(7), the N-type impurity is doped in the second polysilicon film34and the first polysilicon film33in the pixel part formation region16and the region where the NFET is formed on the peripheral circuit part formation region17. Here, the N-type impurity is not ion-implanted in the second polysilicon film34within the groove part31, the non-doped second polysilicon film34is left, and a filling layer36is formed. Note that, through the thermal process, the N-type impurity may be diffused.

Further, the second polysilicon film34and the first polysilicon film33on the region where the PFET is formed are doped with the P-type impurity.

For example, in the case of N-type, phosphorus (P) or arsenic (As) is used as the dopant, and the energy is set to 5 keV to 10 keV, the dose amount is set to 1×1015ions/cm2to 1×1016ions/cm2.

For example, in the case of P-type, boron (B) or BF2, indium (In) is used as the dopant, and the energy is set to 5 keV to 10 keV, the dose amount is set to 1×1015ions/cm2to 1×1016ions/cm2.

Then, as shown in FIG.9(8), with the first polysilicon film33and the second polysilicon film34, the gate electrode21G of the vertical transistor21, gate electrodes22G of the planar transistors of the pixel part, gate electrodes23G,24G of the respective transistors of the peripheral circuit part are formed.

Accordingly, the gate electrode21G includes a conducting layer35of the first polysilicon film33doped with the N-type impurity, the filling layer36, and a part of the second polysilicon film34doped with the N-type impurity. Further, the gate electrodes22G and the gate electrode23G include the first polysilicon film33doped with the first conductivity-type impurity and the second polysilicon film34doped with the first conductivity-type impurity. Furthermore, the gate electrode24G includes the first polysilicon film33and the second polysilicon film34doped with the second conductivity-type impurity.

In place of the first polysilicon film33, an amorphous silicon film may be used.

[Manufacturing Process of Photoelectric Conversion Part]

Here, an example of a method of forming the photoelectric conversion part will be described as below.

As shown in FIG.10(1), as the semiconductor substrate11, for example, a p-type semiconductor substrate is prepared.

A photoelectric conversion part51is formed on the semiconductor substrate11. The photoelectric conversion part51includes a photodiode.

For example, by ion implantation using a resist mask (not shown), an N-type semiconductor region (hereinafter, referred to as “high-density N-type region”)52is formed at the surface side of the semiconductor substrate11. Then, under the region, an N-type semiconductor region (hereinafter, referred to as “low-density N-type region”)53at the lower density than that of the high-density N-type region52is formed in junction with the region. Furthermore, by ion implantation of the p-type impurity, a P-type semiconductor region (hereinafter, referred to as “low-density P-type regions”)54is formed on the high-density N-type region52.

Then, the resist mask is removed.

Next, by ion implantation using a new resist mask (not shown), with the low-density P-type region54left in a part on the high-density N-type region52, around the region54, P-type semiconductor regions (hereinafter, referred to as “high-density P-type regions”)55at the higher density than that of the low-density P-type region54are formed. It is preferable that the low-density P-type region54is left at the center on the high-density N-type region52for easy readout of charge.

Then, as shown in FIG.11(2), a groove part31that has been explained using (1) inFIG. 6is formed, and a gate insulator film32is formed. The groove part31is formed to penetrate the low-density P-type region54and reach the upper part of the high-density N-type region52.

Then, as shown in FIG.12(3), by oblique ion implantation, in the semiconductor substrate11at the bottom side of the groove part31and at the lower side thereof, a low-density P-type region56having nearly equal density to that of the low-density P-type region54is formed.

Then, as shown in FIG.13(4), a second device isolation region15that isolates the pixels formed within the pixel part formation region16is formed. Note that the second device isolation region15may be formed after formation of the photoelectric conversion part51and before formation of the groove part31.

In this manner, the photoelectric conversion part51is formed.

[Manufacturing Process after Formation of Gate Electrodes of Transistors]

Furthermore, as shown inFIG. 14, after the gate electrodes21G to24G of the respective transistors are formed, in the same manner as described in the first manufacturing method, in the semiconductor substrate11on both sides of the respective gate electrodes21G to24G, extension regions (not shown) and source and drain regions25to30, and so on are formed. Moreover, on the semiconductor substrate11, a wiring layer81is formed.

Then, though not shown, after a support substrate is formed at the wiring layer81side, the side of the semiconductor substrate11at which the photoelectric conversion part51is formed is ground or polished so that the semiconductor substrate11may have a desired thickness.

Then, a color filter layer, a collector lens (microlens), etc. are formed at the semiconductor substrate11side.

In this manner, a solid-state imaging device1is completed.

In the first manufacturing method of a solid-state imaging device according to the embodiment of the invention, the conducting layer35that effectively functions as a gate electrode is formed by doping a conducting impurity in the first polysilicon film33formed on the inner surface of the groove part31via the gate insulating film32. Further, the gate electrode21G is formed by the filing layer36of the non-doped second polysilicon film34filling the interior of the groove part36and the electrode layer37of the second polysilicon film34doped with the first conductivity-type impurity connected to the first polysilicon film33. Effectively, the conducting layer35has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode of the vertical transistor unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

For example, Y. Nishida et al., IEDM Tech. Dig., pp. 869-872, December 2001 discloses that, typically, in a surface channel CMOSFET as a planar transistor, it is necessary to form the gate electrode of NFET in N-type and the gate electrode of PFET in P-type.

Further, a technology using in-situ doped polysilicon for the respective gate electrodes of the vertical transistor and the planar transistor has been known. In the technology, there is a method of filling the vertical hole in which the vertical transistor is formed and forming the gate electrode of CMOSFET of the planar transistor. However, according to the method, it is difficult to make the CMOSFET because the conductivity of the gate electrode of the NFET or PFET of the CMOSFET is inverted to the original conductivity.

In order to avoid this, it is conceivable that the gate electrodes of the vertical transistor and the planar transistor are separately made, however, in this case, the number of steps is increased and the cost is increased. Further, when the gate of the planar transistor is worked, there is a level difference of the vertical transistor that has been formed before, and residues are left in the gate etching of the planar transistor. Thereby, reduction in yield is caused.

On the other hand, in the first manufacturing method of a solid-state imaging device according to the embodiment of the invention, the gate electrodes23G,24G of the planar transistors (NFET23, PFET24) of the pixel part12and the peripheral circuit part13are formed by doping predetermined conductivity-type impurities in the non-doped first polysilicon film33and the non-doped second polysilicon film34. Accordingly, the gate electrode23G of the NFET23and the gate electrode24G of the PFET24are separately formed in N-type and P-type, respectively. In addition, the gate electrodes23G,24G having minute gate lengths can be formed.

Therefore, the vertical transistor21and the planar transistors22to24having minute gate lengths are mounted on the same semiconductor substrate. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized. Further, reduction in yield is not caused unlike the technology in the past.

Second Example of Manufacturing Method of Solid-State Imaging Device

Next, the second example of the manufacturing method of a solid-state imaging device according to the sixth embodiment of the invention will be explained using manufacturing process sectional views ofFIGS. 15 to 17.

The second manufacturing method of a solid-state imaging device according to the embodiment of the invention forms a photoelectric conversion part for photoelectrically converting incident light to obtain an electric signal, and a pixel part including a vertical transistor that reads out signal charge from the photoelectric conversion part and planar transistors that process the read out signal charge. Concurrently, a peripheral circuit part is formed on the periphery of the pixel part. The peripheral circuit part is formed to have a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET), and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET).

The process of forming the gate electrodes of the respective transistors in the pixel part and the peripheral circuit part are as below.

[Manufacturing Process of Gates of Respective Transistors]

As shown in (1) inFIG. 15, in the semiconductor substrate11, first device isolation regions14that isolate a pixel part formation region16where the pixel part is formed and a peripheral circuit part formation region17where the peripheral circuit part is formed. Concurrently, a second device isolation region15that isolates the pixels is formed within the pixel part formation region16.

Further, though not shown, well regions are formed in the region where the photoelectric conversion part is formed, the region where the transistors of the pixel part are formed, the region where NFET, OPFET of the peripheral circuit part are formed, and so on.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

Furthermore, though not shown in the drawing, the photoelectric conversion part, details of which have been described according toFIG. 14, is formed in the semiconductor substrate11of the pixel part formation region16.

Then, a groove part31is formed in the region where the gate electrode of the vertical transistor of the semiconductor substrate11is formed. The groove part31is formed by dry etching using a resist mask, for example, to have a width of 0.1 μm to 0.4 μm, for example. The resist mask used as the etching mask is removed after the groove part31is formed.

Then, a gate insulator film32is formed on the surface of the semiconductor substrate11including the inner surface of the groove part31. For example, the gate insulator film is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Then, as shown in (2) inFIG. 15, on the semiconductor substrate11including the inner surface of the groove part31, a polysilicon film63is formed under the non-doped condition via the gate insulator film32. For example, by chemical vapor deposition, the polysilicon film63is formed to have a half thickness of the width of the groove part31so as not to fill the groove part31in a thickness of 30 nm or more, for example.

Furthermore, a protector film64is formed on the polysilicon film63. The protector film64is a silicon oxide film, for example, and formed to have a thickness equal to or more than 10 nm, for example. The silicon oxide film is formed by a film formation technology such as thermal oxidation, chemical vapor deposition, or the like.

Then, as shown in (3) inFIG. 16, a resist mask65is formed on the protector film64of the formation region of the PFET of the peripheral circuit part formation region17. Then, using the resist mask65as an etching mask, the protector film64is removed and the polysilicon film63is exposed on the pixel part formation region16and the formation region of the NFET of the peripheral circuit part formation region17.

Then, the resist mask65is removed. In the drawing, the state immediately before the removal of the resist mask65is shown.

Then, as shown in (4) inFIG. 16, a polysilicon film38doped with the first conductivity-type impurity is formed by doping the first conductivity-type impurity (e.g., the N-type impurity) in the polysilicon film63in the pixel part formation region16and the formation region of the NFET of the peripheral circuit part formation region17. For example, isotropic doping such as vapor-phase doping is used. When the N-type impurity is doped as the first conductivity-type impurity, for example, phosphorus (P) or arsenic (As) is used. When a P-type impurity is doped, for example, boron (B) is used. The doping density is set to density at which the impurity density of 1×1019cm−3can be secured or higher for suppressing gate depletion even when the dopant diffuses in the entire polysilicon including a second polysilicon film, which will be formed later.

Then, the protector film64is removed. In the drawing, the state immediately before the removal of the protector film64is shown.

As a result, as shown in (5) inFIG. 17, when the N-type impurity is used as the first conductivity-type impurity, the polysilicon film63is doped with the N-type impurity in the pixel part formation region16and the formation region of the NFET of the peripheral circuit part formation region17and non-doped in the formation region of the PFET of the peripheral circuit part formation region17.

Then, a resist mask (not shown) is formed on the polysilicon film63, and an opening part (not shown) is formed on the region where the PFET is formed in the peripheral circuit part formation region of the resist mask. The resist mask is used as an ion implantation mask, the second conductivity-type impurity (e.g., the P-type impurity) is doped in the polysilicon film63, and thereby, a polysilicon film40doped with the second conductivity-type impurity is formed. Then, the resist mask is removed.

Then, as shown in (6) inFIG. 17, a metal film (or a metal compound film)39is formed on the polysilicon films38,40. For the metal film, for example, a metal such as tungsten or nickel may be used. For the metal compound film, for example, a metal nitride such as tungsten nitride or titanium nitride, or a metal silicide such as nickel silicide or cobalt silicide may be used.

Then, as shown in FIG.18(7), with the polysilicon films38,40and the metal film (or the metal compound film)39, a gate electrode21G of the vertical transistor, a gate electrode22G of the planar transistor22of the pixel part12, and gate electrodes23G,24G of the respective transistors of the peripheral circuit part13are formed.

Accordingly, the gate electrode21G includes the conducting layer35of the polysilicon film38doped with the N-type impurity, a filling layer36of the metal layer (or the metal compound layer)39, and an electrode layer37. Further, the gate electrode22G and the gate electrode23G include the polysilicon film38doped with the first conductivity-type impurity and the metal layer (or the metal compound layer)39. Furthermore, the gate electrode24G includes the polysilicon film40doped with the second conductivity-type impurity and the metal layer (or the metal compound layer)39.

In place of the polysilicon film63, an amorphous silicon film may be used.

[Manufacturing Process of Photoelectric Conversion Part]

Further, a manufacturing process of the photoelectric conversion part is performed in the same manner as that explained in the first manufacturing method. Here, the formation location of the groove31relative to the photoelectric conversion part51is the same as that explained in the first manufacturing method.

[Manufacturing Process after Formation of Gate Electrodes of Transistors]

Furthermore, after the gate electrodes21G to24G of the respective transistors are formed, in the same manner as described according toFIG. 14in the first manufacturing method, in the semiconductor substrate11on both sides of the respective gate electrodes21G to24G, extension regions (not shown) and source and drain regions25to30, and so on are formed. Moreover, on the semiconductor substrate11, a wiring layer81is formed.

Then, though not shown, after a support substrate is formed at the wiring layer81side, the side of the semiconductor substrate11at which the photoelectric conversion part51is formed is ground or polished so that the semiconductor substrate11may have a desired thickness.

Then, a color filter layer, a collector lens (microlens), etc. are formed at the semiconductor substrate11side.

In the second manufacturing method of a solid-state imaging device according to the embodiment of the invention, the conducting layer35that effectively functions as the gate electrode21G is formed by doping a conducting impurity in the polysilicon film63formed on the inner surface of the groove part31via the gate insulating film32. Further, the gate electrode21G is formed by the filing layer36of the metal film (or the metal compound film) filling the interior of the groove part31and the electrode layer37of the metal film (or the metal compound film) connected to the conducting layer35. Effectively, the conducting layer35has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode of the vertical transistor unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

For example, Y. Nishida et al., IEDM Tech. Dig., pp. 869-872, December 2001 discloses that, typically, in a surface channel CMOSFET as a planar transistor, it is necessary to form the gate electrode of NFET in N-type and the gate electrode of PFET in P-type.

Further, a technology using in-situ doped polysilicon for the respective gate electrodes of the vertical transistor and the planar transistor has been known. In the technology, there is a method of filling the vertical hole in which the vertical transistor is formed and forming the gate electrode of CMOSFET of the planar transistor. However, according to the method, it is difficult to make the CMOSFET because the conductivity of the gate electrode of the NFET or PFET of the CMOSFET is inverted to the original conductivity.

In order to avoid this, it is conceivable that the gate electrodes of the vertical transistor and the planar transistor are separately made, however, in this case, the number of steps is increased and the cost is increased. Further, when the gate of the planar transistor is worked, there is a level difference of the vertical transistor that has been formed before, and residues are left in the gate etching of the planar transistor. Thereby, reduction in yield is caused.

On the other hand, in the second manufacturing method of a solid-state imaging device according to the embodiment of the invention, the gate electrodes23G,24G of the planar transistors (NFET23, PFET24) of the pixel part12and the peripheral circuit part13are formed by doping predetermined conductivity-type impurities in the non-doped polysilicon film63formed immediately on the gate electrode32. Accordingly, the gate electrode23G of the NFET23and the gate electrode24G of the PFET24are separately formed in N-type and P-type, respectively. In addition, the gate electrodes23G,24G having minute gate lengths can be formed.

Therefore, the vertical transistor21and the planar transistors22, NFET23, PFET24having minute gate lengths are mounted on the same semiconductor substrate11. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized. Further, reduction in yield is not caused unlike the technology in the past.

Third Example of Manufacturing Method of Solid-State Imaging Device

Next, the third example of the manufacturing method of a solid-state imaging device according to the seventh embodiment of the invention will be explained using manufacturing process sectional views ofFIGS. 19 to 20.

The third manufacturing method of a solid-state imaging device according to the embodiment of the invention forms a photoelectric conversion part for photoelectrically converting incident light to obtain an electric signal, and a pixel part including a vertical transistor that reads out signal charge from the photoelectric conversion part and planar transistors that process the read out signal charge. Concurrently, a peripheral circuit part is formed on the periphery of the pixel part. The peripheral circuit part is formed to have a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET), and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET).

The process of forming the gate electrodes of the respective transistors in the pixel part and the peripheral circuit part are as below.

[Manufacturing Process of Gates of Respective Transistors]

As shown in (1) inFIG. 19, in the semiconductor substrate11, first device isolation regions14that isolate a pixel part formation region16where the pixel part is formed and a peripheral circuit part formation region17where the peripheral circuit part is formed. Concurrently, a second device isolation region15that isolates the pixels is formed within the pixel part formation region16.

Further, though not shown, well regions are formed in the region where the photoelectric conversion part is formed, the region where the transistors of the pixel part are formed, the region where NFET, OPFET of the peripheral circuit part are formed, and so on.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

Furthermore, though not shown in the drawing, the photoelectric conversion part, details of which have been described according toFIG. 14, is formed in the semiconductor substrate11of the pixel part formation region16.

Then, a groove part31is formed in the region where the gate electrode of the vertical transistor of the semiconductor substrate11. The groove part31is formed by dry etching using a resist mask, for example, to have a width of 0.1 μm to 0.2 μm, for example. The resist mask used as the etching mask is removed after the groove part31is formed.

Then, a gate insulator film32is formed on the surface of the semiconductor substrate11including the inner surface of the groove part31. For example, the gate insulator film is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Alternatively, as the gate insulator film32, a film including an oxide, silicate, nitrided oxide, or oxidized nitrided silicate containing at least one kind selected from silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), lanthanum (La), hafnium (Hf), and tantalum (Ta) may be used.

Specifically, silicon oxide (SiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium titanate (ZrTiOx), hafnium aluminum oxide (HfAlOx), zirconium aluminum oxide (ZrAlOx), and further, nitride of them (silicon oxynitride (SiON), hafnium silicide oxynitride (HfSiON), etc.) are cited. The relative permittivity of these materials may slightly vary depending on composition and crystalline property. For example, the relative permittivity of HfO2is 25 to 30, and the relative permittivity of ZrO2is 20 to 25.

Then, on the semiconductor substrate11including the inner surface of the groove part31, a conducting layer35including a metal film (or a metal compound film)41is formed via the gate insulator film32. For the metal film, for example, hafnium (Hf) or lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31. As the metal compound film, for example, hafnium silicide or silicide of lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31.

Note that, a film that controls a work function may be used for the conducting layer35.

For example, in the case of NFET, its gate electrode has a work function less than 4.6 eV, desirably equal to less than 4.3 eV. In the case of PFET, its gate electrode has a work function equal to or more than 4.6 eV, desirably equal to more than 4.9 eV.

For example, as an example of the work-function control film, there are metals of titanium (Ti), vanadium (V), nickel (Ni), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), alloys containing these metals, and compounds of these metals. As the metal compounds, there are metal nitrides and compounds of metal and semiconductor. The compounds of metal and semiconductor include a metal silicate as an example.

As an example of the work-function control film suitable for NFET, there are metals such as hafnium (Hf) and tantalum (Ta), and alloys containing these metals, and compounds of these metals, and specifically, hafnium silicate (HfSix) is more preferable. The hafnium silicate for nMOSFET has a work function of about 4.1 eV to 4.3 eV.

As an example of the work-function control film suitable for PFET, there are metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru) and alloys containing these metals, and compounds of these metals. Specifically, titanium nitride (TiN) or ruthenium (Ru) is more preferable. The titanium nitride for pMOSFET has a work function of about 4.5 eV to 5.0 eV.

Then, as shown in (2) inFIG. 19, a resist mask (not shown) is formed on the pixel part formation region16. Then, the conducting layer35of the peripheral circuit part formation region17is removed using the resist mask as an etching mask. As a result, the gate insulator film32of the peripheral circuit part formation region17is exposed.

Then, the resist mask is removed.

Then, as shown in (3) inFIG. 20, a polysilicon film42is formed under the non-doped condition on the gate insulator film32including the conducting layer35, for example.

Then, as shown in (4) inFIG. 20, the first conductivity-type impurity (e.g., N-type impurity) is doped in the polysilicon film42in the region where the pixel part formation region16and the region where the NFET of the peripheral circuit part formation region17are formed. Here, the N-type impurity is not ion-implanted in the polysilicon film42within the groove part31, and the non-doped polysilicon film42is left. Note that, through the thermal process, the N-type impurity may be diffused.

Further, a polysilicon film44doped with the second conductivity-type impurity is formed by doping the second conductivity-type impurity (e.g., the P-type impurity) in the polysilicon film42on the region where the PFET of the peripheral circuit part formation region17is formed.

For example, in the case of N-type, phosphorus (P) or arsenic (As) is used as the dopant, and the energy is set to 5 keV to 10 keV, the dose amount is set to 1×1015ions/cm2to 1×1016ions/cm2.

For example, in the case of P-type, boron (B) or BF2, indium (In) is used as the dopant, and the energy is set to 5 keV to 10 keV, the dose amount is set to 1×1015ions/cm2to 1×1016ions/cm2.

Then, with the conducting layer35and the polysilicon film42, the gate electrode21G of the vertical transistor, gate electrodes22G of the planar transistors of the pixel part, gate electrodes23G,24G of the respective transistors of the peripheral circuit part are formed.

Accordingly, the gate electrode21G includes the conducting layer35, a filling layer36including the non-doped polysilicon film42, and an electrode layer including the polysilicon film42doped with the first conductivity-type impurity. Further, the gate electrodes22G includes the conducting layer35and the polysilicon film42doped with the first conductivity-type impurity. Further, the gate electrode23G includes the polysilicon film42doped with the first conductivity-type impurity. Furthermore, the gate electrode24G includes the polysilicon film42doped with the second conductivity-type impurity.

[Manufacturing Process of Photoelectric Conversion Part]

Further, a manufacturing process of the photoelectric conversion part is performed in the same manner as that explained in the first manufacturing method. Here, the formation location of the groove31relative to the photoelectric conversion part51is the same as that explained in the first manufacturing method.

[Manufacturing Process after Formation of Gate Electrodes of Transistors]

Furthermore, after the gate electrodes21G to24G of the respective transistors are formed, in the same manner as described according toFIG. 14in the first manufacturing method, in the semiconductor substrate11on both sides of the respective gate electrodes21G to24G, extension regions (not shown) and source and drain regions25to30, and so on are formed. Moreover, on the semiconductor substrate11, a wiring layer81is formed.

Then, though not shown, after a support substrate is formed at the wiring layer81side, the side of the semiconductor substrate11at which the photoelectric conversion part51is formed is ground or polished so that the semiconductor substrate11may have a desired thickness.

Then, a color filter layer, a collector lens (microlens), etc. are formed at the semiconductor substrate11side.

In the third manufacturing method of a solid-state imaging device according to the embodiment of the invention, the conducting layer35of the metal film (or the metal compound film)41formed on the inner surface of the groove part31via the gate insulating film32effectively functions as the gate electrode21G. Further, the gate electrode21G is formed by the filing layer36of the non-doped polysilicon film42filling the interior of the groove part31and a polysilicon film43doped with the first conductivity-type impurity connected to the metal film (or the metal compound film)41. Effectively, the conducting layer35of the metal film (or the metal compound film)41has a function of the gate electrode21G. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode of the vertical transistor unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

For example, Y. Nishida et al., IEDM Tech. Dig., pp. 869-872, December 2001 discloses that, typically, in a surface channel CMOSFET as a planar transistor, it is necessary to form the gate electrode of NFET in N-type and the gate electrode of PFET in P-type.

Further, a technology using in-situ doped polysilicon for the respective gate electrodes of the vertical transistor and the planar transistor has been known. In the technology, there is a method of filling the vertical hole in which the vertical transistor is formed and forming the gate electrode of CMOSFET of the planar transistor. However, according to the method, it is difficult to make the CMOSFET because the conductivity of the gate of the NFET or PFET of the CMOSFET is inverted to the original conductivity.

In order to avoid this, it is conceivable that the gate electrode of the vertical transistor and the planar transistor are separately made, however, in this case, the number of steps is increased and the cost is increased. Further, when the gate of the planar transistor is worked, there is a level difference of the vertical transistor that has been formed before, and residues are left in the gate etching. Thereby, reduction in yield is caused.

On the other hand, in the third manufacturing method of a solid-state imaging device according to the embodiment of the invention, the gate electrodes23G,24G of the planar transistors (NFET23, PFET24) of the peripheral circuit part are formed by doping predetermined conductivity-type impurities in the non-doped polysilicon film42formed immediately on the gate electrode32. Accordingly, the gate electrode23G of the NFET23and the gate electrode24G of the PFET24are separately formed in N-type and P-type, respectively. In addition, the gate electrodes23G,24G having minute gate lengths can be formed.

Therefore, the vertical transistor21and the planar transistors22, NFET23, PFET24having minute gate lengths are mounted on the same semiconductor substrate11. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized. Further, reduction in yield is not caused unlike the technology in the past.

Fourth Example of Manufacturing Method of Solid-State Imaging Device

Next, the fourth example of the manufacturing method of a solid-state imaging device according to the eighth embodiment of the invention will be explained using manufacturing process sectional views ofFIGS. 21 to 22.

The fourth manufacturing method of a solid-state imaging device according to the embodiment of the invention forms a photoelectric conversion part for photoelectrically converting incident light to obtain an electric signal, and a pixel part including a vertical transistor that reads out the signal charge from the photoelectric conversion part and planar transistors that process the read out signal charge. Concurrently, a peripheral circuit part is formed on the periphery of the pixel part. The peripheral circuit part is formed to have a first conductivity-type (hereinafter, N-type, for example) channel transistor (hereinafter, referred to as NFET), and a second conductivity-type (hereinafter, P-type, for example) channel transistor (hereinafter, referred to as PFET).

The process of forming the gate electrodes of the respective transistors in the pixel part and the peripheral circuit part are as below.

[Manufacturing Process of Gates of Respective Transistors]

As shown in (1) inFIG. 21, in the semiconductor substrate11, first device isolation regions14that isolate a pixel part formation region16where the pixel part is formed and a peripheral circuit part formation region17where the peripheral circuit part is formed. Concurrently, a second device isolation region15that isolates the pixels is formed within the pixel part formation region16.

Further, though not shown, well regions are formed in the region where the photoelectric conversion part is formed, the region where the transistors of the pixel part are formed, the region where NFET, OPFET of the peripheral circuit part are formed, and so on.

The first device isolation regions14are formed by typical STI (Shallow Trench Isolation), for example. Further, the second device isolation region15is formed by a P-type diffusion layer, for example.

Furthermore, though not shown in the drawing, the photoelectric conversion part, details of which have been described according toFIG. 14, is formed in the semiconductor substrate11of the pixel part formation region16.

Then, a groove part31is formed in the region where the gate electrode of the vertical transistor of the semiconductor substrate11. The groove part31is formed by dry etching using a resist mask, for example, to have a width of 0.1 μm to 0.2 μm, for example. The resist mask used as the etching mask is removed after the groove part31is formed.

Then, a gate insulator film32is formed on the surface of the semiconductor substrate11including the inner surface of the groove part31. For example, the gate insulator film is formed by surface-oxidizing the surface of the semiconductor substrate11, for example.

Alternatively, as the gate insulator film32, a film including an oxide, silicate, nitrided oxide, or oxidized nitrided silicate containing at least one kind selected from silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), lanthanum (La), hafnium (Hf), and tantalum (Ta) may be used.

Specifically, silicon oxide (SiO2), hafnium oxide (HfO2) zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium titanate (ZrTiOx), hafnium aluminum oxide (HfAlOx), zirconium aluminum oxide (ZrAlOx), and further, nitride of them (silicon oxynitride (SiON), hafnium silicide oxynitride (HfSiON), etc.) are cited. The relative permittivity of these materials may slightly vary depending on composition and crystalline property. For example, the relative permittivity of HfO2is 25 to 30, and the relative permittivity of ZrO2is 20 to 25.

Then, on the semiconductor substrate11including the inner surface of the groove part31, a first conducting layer47including a first metal film (or a first metal compound film) is formed via the gate insulator film32. For the first metal film, for example, hafnium (Hf) or lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31. As the first metal compound film, for example, hafnium silicide or silicide of lanthanoid metal is used, and the film is formed to have a thickness from 5 nm to 30 nm so as not to fill the groove part31.

Note that, a film that controls a work function may be used for the first conducting layer47.

For example, in the case of NFET, its gate electrode has a work function less than 4.6 eV, desirably equal to less than 4.3 eV. In the case of PFET, its gate electrode has a work function equal to or more than 4.6 eV, desirably equal to more than 4.9 eV.

For example, as an example of the work-function control film, there are metals of titanium (Ti), vanadium (V), nickel (Ni), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), alloys containing these metals, and compounds of these metals. As the metal compounds, there are metal nitrides and compounds of metal and semiconductor. The compounds of metal and semiconductor include a metal silicide as an example.

As an example of the work-function control film suitable for NFET, there are metals such as hafnium (Hf) and tantalum (Ta), and alloys containing these metals, and compounds of these metals, and specifically, hafnium silicide (HfSix) is more preferable. The hafnium silicide for NFET has a work function of about 4.1 eV to 4.3 eV.

As an example of the work-function control film suitable for PFET, there are metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru) and alloys containing these metals, and compounds of these metals. Specifically, titanium nitride (TiN) or ruthenium (Ru) is more preferable. The titanium nitride for PFET has a work function of about 4.5 eV to 5.0 eV.

The first conducting layer47forms the gate electrode of the NFET and it is preferable to use the work-function control film suitable for the NFET.

Then, a resist mask (not shown) is formed on the pixel part formation region16and the formation region of the NFET of the peripheral circuit part formation region17. Then, the first conducting layer47in the formation region of the PFET of the peripheral circuit part formation region17is removed using the resist mask as an etching mask. As a result, the gate insulator film32of the region where the PFET of the peripheral circuit part formation region17is formed is exposed.

Then, the resist mask is formed is removed.

Then, as shown in (2) inFIG. 21, a second conducting layer48including a second metal film (or a second metal compound film) is formed on the gate insulator film32including the first conducting layer47. For the second conducting layer48, a conducting layer having a different work function different from that of the first conducting layer47is used. For example, when a film having a work function suitable for NFET is used for the first conducting layer47, a conducting layer having a work function suitable for PFET is used for the second conducting layer48.

Note that, when a film having a work function suitable for PFET is used for the first conducting layer47, a conducting layer having a work function suitable for NFET is used for the second conducting layer48.

The work function control film suitable for the PFET includes metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru), alloys containing these metals, and compounds of these metals. Specifically, titanium nitride (TiN) or ruthenium (Ru) is more preferable. The titanium nitride for PFET has a work function of about 4.5 eV to 5.0 eV.

Then, as shown in FIG.22(3), with the first conducting layer47and the second conducting layer48, a gate electrode21G of the vertical transistor, a gate electrode22G of the planar transistor of the pixel part, and a gate electrode23G of the NFET of the peripheral circuit part are formed. Further, with the second conducting layer48, a gate electrode24G of the PFET of the peripheral circuit part is formed.

Accordingly, the gate electrode21G includes the conducting layer35formed by the first conducting layer47, a filling layer36formed by the second conducting layer48, and an electrode layer37formed by the second conducting layer48. Further, the gate electrode22G and the gate electrode23G include the first conducting layer47and the second conducting layer48. The gate electrode24G includes the second conducting layer48.

[Manufacturing Process of Photoelectric Conversion Part]

Further, a manufacturing process of the photoelectric conversion part is performed in the same manner as that explained in the first manufacturing method. Here, the formation location of the groove31relative to the photoelectric conversion part51is the same as that explained in the first manufacturing method.

[Manufacturing Process after Formation of Gate Electrodes of Transistors]

Furthermore, after the gate electrodes21G to24G of the respective transistors are formed, in the same manner as described according toFIG. 14in the first manufacturing method, the semiconductor substrate11on both sides of the respective gate electrodes21G to24G, extension regions (not shown) and source and drain regions25to30, and so on are formed. Moreover, on the semiconductor substrate11, a wiring layer81is formed.

Then, though not shown, after a support substrate is formed at the wiring layer81side, the side of the semiconductor substrate11at which the photoelectric conversion part51is formed is ground or polished so that the semiconductor substrate11may have a desired thickness.

Then, a color filter layer, a collector lens (microlens), etc. are formed at the semiconductor substrate11side.

In the fourth manufacturing method of a solid-state imaging device according to the embodiment of the invention, the conducting layer35of the first conducting layer47including the first metal film or the first metal compound film formed on the inner surface of the groove part31via the gate insulating film32effectively functions as the gate electrode21G. Further, the gate electrode21G is formed by the filing layer36of the second metal film or the second metal compound film filling the interior of the groove part31, and an electrode layer37of the second metal film or the second metal compound film connected to the first conducting layer47. Therefore, it is not necessary to fill the groove part31with the conducting layer35, and thus, it is not necessary to diffuse the impurity to the bottom of the groove part31in the polysilicon filling the groove part31by high-temperature heat treatment for forming the gate electrode of the vertical transistor unlike the technology in the past. Further, it is not necessary to perform ion implantation with high energy to allow the implanted ions to reach the bottom of the groove part31in the polysilicon filling the groove part31.

For example, Y. Nishida et al., IEDM Tech. Dig., pp. 869-872, December 2001 discloses that, typically, in a surface channel CMOSFET as a planar transistor, it is necessary to form the gate electrode of NFET in N-type and the gate electrode of PFET in P-type.

Further, a technology using in-situ doped polysilicon for the respective gate electrodes of the vertical transistor and the planar transistor has been known. In the technology, there is a method of filling the vertical hole in which the vertical transistor is formed and forming the gate electrode of CMOSFET of the planar transistor. However, according to the method, it is difficult to make the CMOSFET because the conductivity of the gate of the NFET or PFET of the CMOSFET is inverted to the original conductivity.

In order to avoid this, it is conceivable that the gate electrode of the vertical transistor and the planar transistor are separately made, however, in this case, the number of steps is increased and the cost is increased. Further, when the gate of the planar transistor is worked, there is a level difference of the vertical transistor that has been formed before, and residues are left in the gate etching. Thereby, reduction in yield is caused.

On the other hand, in the fourth manufacturing method of a solid-state imaging device according to the embodiment of the invention, the gate electrodes23G,24G of the planar transistors (NFET23, PFET24) of the peripheral circuit part13are metal gates, and it is not necessary to separately form the gate electrode23G of the NFET23and the gate electrode24G of the PFET24in N-type and P-type, respectively. However, in the fourth manufacturing method, the gate electrode23G of the NFET23and the gate electrode24G of the PFET24are separately formed to have their optimum work functions. In addition, the gate electrodes23G,24G having minute gate lengths can be formed.

Therefore, the vertical transistor21and the planar transistors22, NFET23, PFET24having minute gate lengths are mounted on the same semiconductor substrate11. Accordingly, there are advantages that the higher definition and higher density packaging of the transistors can be achieved and the higher definition and higher image processing speed can be realized. Further, reduction in yield is not caused unlike the technology in the past.

In the respective embodiments, the case where the first conductivity-type is N-type and the second conductivity-type is P-type has been explained, however, the first conductivity-type may be P-type and the second conductivity-type may be N-type.

One Example of Configuration of Imaging Apparatus

One example of a configuration of an imaging apparatus according to the ninth embodiment of the invention will be explained according to a block diagram inFIG. 23. For example, the imaging apparatus includes a video camera, digital still camera, a camera for cellular phone, etc.

As shown inFIG. 23, an imaging apparatus300includes a solid-state imaging device (not shown) in an imaging unit301. An imaging optical unit302for collecting incident light and forming an image is provided at the light collection side of the imaging unit301. Further, to the imaging unit301, a signal processing unit303having a drive circuit that drives it, a signal processing circuit that processes signals photoelectrically converted by the solid-state imaging device into images, etc. are connected. Furthermore, the image signals processed by the signal processing unit may be stored in an image storage unit (not shown). In such an imaging apparatus300, the solid-state imaging devices1to4of the embodiments of the invention may be used for the solid-state imaging device.

In the imaging apparatus300, the solid-state imaging devices1to4of the embodiments of the invention are used. Since the solid-state imaging device that enables the higher definition and the higher speed of image processing speed is used, there is an advantage that high-definition video can be smoothly recorded.

Note that the imaging apparatus300is not limited to the above described configuration, but can be applied to any configuration as long as it is an imaging apparatus using a solid-state imaging device.

The solid-state imaging devices1to4may have forms of single chips or module forms having imaging functions in which the signal processing unit and the optical system are packaged together.

Further, the embodiments of the invention can be applied not only to the imaging apparatus but also to other imaging apparatuses. In this case, as the imaging apparatuses, higher image quality can be obtained. Here, the imaging apparatus refers to a portable device having a camera or imaging function. Further, “imaging” not only refers to shooting of images in the typical shooting with cameras, but also includes fingerprint detection in the broad sense.

The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2008-279471 filed in the Japan Patent Office on Oct. 30, 2008, the entire contents of which is hereby incorporated by reference.