PIXEL GROUP, ARRAY SUBSTRATE, AND DISPLAY PANEL

A pixel group includes a plurality of pixel circuits and a compensation circuit; where each of the pixel circuits is connected to the compensation circuit; each of the pixel circuits includes a driving transistor; the compensation circuit includes a third transistor; and the compensation circuit is capable of loading a threshold voltage of the third transistor to a control end of the driving transistor; and a channel region of the third transistor has a width to length ratio of a3, a channel region of the driving transistor has a width to length ratio of a1, and a3/a1 is in a range of 1-1.05.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular to a pixel group, an array substrate and a display panel.

BACKGROUND

An OLED display device controls a current flowing through a light-emitting device through a driving transistor, thereby achieving a display effect. The driving transistor is affected by its own characteristics and other factors during use, resulting in an offset in its threshold voltage, which in turn affects the current flowing through the light-emitting device, and results in an uneven display.

In the prior art, the above problem is solved by means of internal compensation and external compensation. Typically, however, more space is occupied when the internal compensation is performed, which is not conducive to realization of a high PPI (Pixels Per Inch, pixel density).

The above information disclosed in the background section is only intended to enhance understanding of the background of the present disclosure, and thus it may include information that does not constitute prior art known to those ordinary skilled in the art.

SUMMARY

An object of the present disclosure is to provide a pixel group, an array substrate and a display panel, where the pixel group reduces the space occupied by the compensation circuit in the display area of the display panel, and realizes a high PPI design of the display panel.

To achieve the above invention object, the present disclosure uses technical solutions as follows.

According to a first aspect of the present disclosure, there is provided a pixel group, including a plurality of pixel circuits and a compensation circuit; where each of the pixel circuits is connected to the compensation circuit;each of the pixel circuits includes a driving transistor;the compensation circuit includes a third transistor; and the compensation circuit is capable of loading a threshold voltage of the third transistor to a control end of each driving transistor; anda channel region of the third transistor has a width to length ratio of a3, the driving transistor has a width to length ratio of a1, and a3/a1=1-1.05.

In an exemplary embodiment of the present disclosure, the channel region of the third transistor has a same pattern as a channel region of the driving transistor.

In an exemplary embodiment of the present disclosure, each of the pixel circuits further includes:a data writing circuit, connected to a scanning signal end, a data signal end and a first node, and configured to provide, under control of a scanning signal from the scanning signal end, a data signal from the data signal end to the first node; anda storage capacitor, connected to a third node and the first node, and configured to store a voltage difference between the third node and the first node; wherethe first node is connected to the control end of the driving transistor, and the driving transistor is configured to output, under control of the first node, a driving current to a light-emitting device; andthe compensation circuit is connected to the third node.

In an exemplary embodiment of the present disclosure, the compensation circuit includes:a second transistor, connected to a compensation switch control signal end, a fourth node and the third node, and configured to conduct the third node and the fourth node under a compensation switch control signal from the compensation switch control signal end; andthe third transistor, where a gate and a second electrode of the third transistor are connected to the fourth node, and a first electrode of the third transistor is connected to a first power supply voltage end.

In an exemplary embodiment of the present disclosure, the compensation circuit further includes:a voltage regulator circuit, connected to the first power supply voltage end and the third node.

In an exemplary embodiment of the present disclosure, the voltage regulator circuit includes a first capacitor, and the first capacitor is connected to the first power supply voltage end and the third node.

In an exemplary embodiment of the present disclosure, the pixel group further includes:a first reset circuit, connected to a first reset control signal end, a first reset voltage end and the third node, and configured to reset the third node by providing, under control of a first reset control signal from the first reset control signal end, a first reset voltage from the first reset voltage end to the third node.

In an exemplary embodiment of the present disclosure, the driving transistor is connected to the first node, a second node and a fifth node, and the light-emitting device is connected to the fifth node;the pixel group is connected to a second reset circuit and a light-emitting control circuit;the second reset circuit is connected to a second reset control signal end, a second reset voltage end and the second node, and is configured to reset the second node by providing, under control of a second reset control signal from the second reset control signal end, a second reset voltage from the second reset voltage end to the second node; andthe light-emitting control circuit s connected to a light-emitting control signal end, the first power supply voltage end and the second node, and is configured to provide, under control of a light-emitting control signal from the light-emitting control signal end, a first power supply voltage from the first power supply voltage end to the second node.

In an exemplary embodiment of the present disclosure, a plurality of pixel groups are connected to the same second reset circuit or/and the same light-emitting control circuit.

In an exemplary embodiment of the present disclosure, the data writing circuit includes a fourth transistor, a gate of the fourth transistor is connected to the scanning signal end, a first electrode of the fourth transistor is connected to the data signal end, and a second electrode of the fourth transistor is connected to the first node;the first reset circuit includes a fifth transistor, where a gate of the fifth transistor is connected to the first reset control signal end, a first electrode of the fifth transistor is connected to the first reset voltage end, and a second electrode of the fifth transistor is connected to the third node;the second reset circuit includes a sixth transistor, where a gate of the sixth transistor is connected to the second reset control signal end, a first electrode of the sixth transistor is connected to the second reset voltage end, and a second electrode of the sixth transistor is connected to the second node; andthe light-emitting control circuit includes a seventh transistor, where a gate of the seventh transistor is connected to the light-emitting control signal end, a first electrode of the seventh transistor is connected to the first power supply voltage end, and a second electrode of the seventh transistor is connected to the second node.

In an exemplary embodiment of the present disclosure, the compensation switch control signal and the light-emitting control signal are the same signal; andthe first reset control signal and the second reset control signal are the same signal.

In an exemplary embodiment of the present disclosure, a channel region of the seventh transistor has a width to length ratio of a7, a channel region of the sixth transistor has a width to length ratio of a6, and a7/a6=2.45-2.55.

In an exemplary embodiment of the present disclosure, a channel region of the seventh transistor has a width to length ratio of a7, and a7/a1=5.75-7.05; and a channel region of the sixth transistor has a width to length ratio of a6, and a6/a1=2.25-2.86.

In an exemplary embodiment of the present disclosure, a channel region of the seventh transistor has a greater width to length ratio than the channel region of the driving transistor, a channel region of the second transistor, the channel region of the third transistor, a channel region of the fourth transistor, a channel region of the fifth transistor, and a channel region of the sixth transistor.

According to a second aspect of the present disclosure, there is provided an array substrate, including:a substrate; anda pixel group, where the pixel group is the pixel group according to the first aspect, and the pixel group is located at a side of the substrate.

In an exemplary embodiment of the present disclosure, in a plurality of pixel groups, at least two of the pixel groups include different numbers of the pixel circuits.

In an exemplary embodiment of the present disclosure, the pixel group includes the plurality of pixel circuits arranged in a plurality of rows and columns; and in the plurality of pixel groups, the pixel groups include a same number of rows of the pixel circuits, and at least two of the pixel groups include different numbers of columns of the pixel circuits.

In an exemplary embodiment of the present disclosure, more than one of the pixel groups are arranged along a row direction to form a row unit, the array substrate includes a plurality of rows of row units; and in the row unit, two adjacent ones of the pixel groups include different numbers of columns of the pixel circuits.

In an exemplary embodiment of the present disclosure, the pixel group includes the plurality of pixel circuits arranged in the plurality of rows and columns, and the compensation circuit is located between any two adjacent rows of the pixel circuits.

According to a third aspect of the present disclosure, there is provided an array substrate, including:a substrate; andan active semiconductor layer, located at a side of the substrate, and including an active layer of at least one pixel group, where the pixel group is the pixel group according to the first aspect, the active semiconductor layer includes a plurality of first semiconductor portion groups and a second semiconductor portion located between any two adjacent ones of the first semiconductor portion groups; wherethe first semiconductor portion group includes a second semiconductor portion sub-group, where the second semiconductor portion sub-group includes a plurality of second semiconductor sub-portions, and the second semiconductor sub-portion includes an active layer of the driving transistor; andthe second semiconductor portion includes an active layer of the third transistor.

In an exemplary embodiment of the present disclosure, the first semiconductor portion group further includes an active layer of the fourth transistor;the second semiconductor portion further includes an active layer of the second transistor, and an active layer of the fifth transistor; andthe active layer of the third transistor, the active layer of the second transistor, and the active layer of the fifth transistor are sequentially arranged along a row direction.

In an exemplary embodiment of the present disclosure, the array substrate further includes:a first conductive layer, located at a side of the active semiconductor layer away from the substrate; wherethe first conductive layer includes a first plate of the storage capacitor and a first plate of a first capacitor, where the first plate of the first capacitor has a greater length in the row direction than in a column direction.

In an exemplary embodiment of the present disclosure, the array substrate further includes:a second conductive layer, located at a side of the first conductive layer away from the substrate, where the second conductive layer includes second plates of a plurality of storage capacitors, and the second plates of the plurality of storage capacitors included in a single pixel group form an integrated structure.

In an exemplary embodiment of the present disclosure, the array substrate further includes a first power supply voltage line extending along the row direction; wherethe first power supply voltage line is connected to the first plate of the first capacitor; anda second electrode region of the active layer of the second transistor is electrically connected to the second plate of the storage capacitor, and the second plate of the storage capacitor is electrically connected to a second plate of the first capacitor.

In an exemplary embodiment of the present disclosure, the second electrode region of the second transistor is electrically connected to the second plate of the storage capacitor via a first adapter portion;the second plate of the storage capacitor is electrically connected to the second plate of the first capacitor via a second adapter portion; andthe first adapter portion and the second adapter portion are provided in a same layer.

In an exemplary embodiment of the present disclosure, the first adapter portion and the second adapter portion extend along the column direction;the array substrate further includes a reset voltage line extending along the row direction, where the reset voltage line and the first power supply voltage line are provided in a same layer, and orthographic projections, on the substrate, of the reset voltage line and the first power supply voltage line are located between orthographic projections, on the substrate, of two adjacent rows of the second plates of the storage capacitors;an orthographic projection of the first adapter portion on the substrate is at least partially overlapped with the orthographic projections, on the substrate, of the reset voltage line and the first power supply voltage line; andan orthographic projection of the second adapter portion on the substrate is at least partially overlapped with the orthographic projections, on the substrate, of the reset voltage line and the first power supply voltage line.

In an exemplary embodiment of the present disclosure, the first power supply voltage line and the reset voltage line are distributed in the second conductive layer; andthe array substrate further includes:a third conductive layer, located at a side of the second conductive layer away from the substrate; wherethe first adapter portion and the second adapter portion are distributed in the third conductive layer.

In an exemplary embodiment of the present disclosure, the first adapter portion and the second adapter portion are distributed in the second conductive layer, and the second adapter portion and the second plate of the first capacitor form an integrated structure; and the array substrate further includes:a third conductive layer, located at a side of the second conductive layer away from the substrate, where the first power supply voltage line and the reset voltage line are distributed in the third conductive layer.

In an exemplary embodiment of the present disclosure, the first adapter portion and the first power supply voltage line are provided in different layers.

In an exemplary embodiment of the present disclosure, the array substrate further includes:a fourth conductive layer, located at a side of the third conductive layer away from the substrate, where the fourth conductive layer includes a plurality of data signal lines extending along the column direction.

In an exemplary embodiment of the present disclosure, in two adjacent pixel groups, the second plates of the plurality of storage capacitors included in one of the pixel groups are separated from and disconnected with the second plates of the plurality of storage capacitors included in another one of the pixel groups.

In an exemplary embodiment of the present disclosure, the substrate includes a display area and a non-display area located at a periphery of the display area; and orthographic projections, on the substrate, of the driving transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are located in the display area; andorthographic projections, on the substrate, of the sixth transistor and the seventh transistor are located in the non-display area.

According to a fourth aspect of the present disclosure, there is provided a display panel, including the array substrate according to the second aspect.

In the pixel group provided by the present disclosure, a plurality of pixel circuits share one compensation circuit, each of the pixel circuits is connected to the compensation circuit, and internal compensation is uniformly performed for the driving transistors T1of the plurality of pixel circuits10by loading the threshold voltage of the third transistor T3to the control ends G of the driving transistors T1, thereby reducing the space occupied by the compensation circuit in the display area of the display panel, which facilitates the realization of the high PPI (Pixels Per Inch, pixel density) design of the display panel.

Reference numerals of main components in the figures are illustrated as follows.

DETAILED DESCRIPTION

The exemplary embodiments are now described more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments are capable of being implemented in a variety of forms and should not be construed as being limited to the examples set forth herein. Rather, the provision of these embodiments allows for the present disclosure to be more comprehensive and complete, and conveys the idea of the exemplary embodiments in a comprehensive manner to those skilled in the art. The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided, thereby giving a full understanding of the embodiments of the present disclosure.

In the figures, areas and thicknesses of layers may be exaggerated for clarity. The same reference numerals in the figures indicate the same or similar structures, and thus their detailed descriptions will be omitted.

The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided, thereby giving a full understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that it is possible to practice the technical solutions of the present disclosure without one or more of the described particular details, or that other methods, components, materials, etc. may be used. In other cases, the well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

When a certain structure is “on” another structure, it may mean that the certain structure is integrally formed on another structure, or that the certain structure is “directly” provided on another structure, or that the certain structure is “indirectly” provided on another structure through yet another structure.

The terms “a”, “an” and “the” are used for indicating an existence of one or more elements/components/etc.; and the terms “include” and “have” are used for indicating an open-ended inclusion and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc. The terms “first” and “second”, etc. are used merely as markers and not as quantitative limitations to the objects thereof.

In the related art, when internal compensation is performed in the display device, each pixel circuit may be configured with one compensation circuit. This setting method occupies a large amount of space and is not conducive to the realization of the high PPI.

As shown inFIGS.1and2, an embodiment of the present disclosure provides a pixel group1, including a plurality of pixel circuits10and a compensation circuit40; each of the pixel circuits10is connected to the compensation circuit40, each of the pixel circuits10includes a driving transistor T1, the compensation circuit40is capable of loading a threshold voltage of a third transistor T3to a control end G of each driving transistor T1, a channel region of the third transistor T3has a width to length ratio of a3, a channel region of the driving transistor T1has a width to length ratio of a1, and a3/a1=1-1.05.

In the pixel group1provided by the present disclosure, a plurality of pixel circuits10share one compensation circuit40, each of the pixel circuits10is connected to the compensation circuit40, and internal compensation is uniformly performed for the driving transistors T1of the plurality of pixel circuits10by loading the threshold voltage of the third transistor T3to the control ends G of the driving transistors T1, thereby reducing the space occupied by the compensation circuit40in the display area AA of the display panel, which facilitates the realization of the high PPI (Pixels Per Inch, pixel density) design of the display panel.

The components of the pixel group1provided by the embodiment of the present disclosure are described in detail below in conjunction with the accompanying drawings.

As shown inFIGS.1and2, the present disclosure provides a pixel group1located in the display area AA of the display panel, and the display panel may be an OLED display panel. The pixel group1enables the realization of internal compensation for a plurality of pixel circuits10simultaneously.

It should be noted herein that, in the present disclosure, the connections in the pixel group1refer to electrical connections. Electrical signals may be transmitted between the components that are connected to each other.

The pixel group1includes a plurality of pixel circuits10and one compensation circuit40, each of the pixel circuits10is connected to the compensation circuit40, each of the pixel circuits10includes the driving transistor T1, and the compensation circuit40is capable of compensating the threshold voltage of the driving transistor T1. The channel region of the third transistor T3has a width to length ratio of a3, the channel region of the driving transistor T1has a width to length ratio of a1, and a3/a1=1-1.05.

It should be noted herein that the channel region is a region where the active layer of the transistor is covered by the gate. The channel region of the third transistor T3means the region where the active layer of the third transistor T3is covered by the gate of the third transistor T3, and similarly, the channel region of the driving transistor T1means the region where the active layer of the driving transistor T1is covered by the gate of the driving transistor T1.

In the present disclosure, the width to length ratio of the channel region of the third transistor T3is substantially equal to the width to length ratio of the channel region of the driving transistor T1, which allows the threshold voltage of the third transistor T3to be substantially equal to the threshold voltage of the driving transistor T1, so that the threshold voltage of the third transistor T3can be used to compensate the threshold voltage of the driving transistor T1.

In some embodiments of the present disclosure, the pattern of the channel region of the third transistor T3is the same as the pattern of the channel region of the driving transistor T1. It should be noted herein that the pattern being the same herein means being substantially the same within the range of process errors.

The plurality of pixel circuits10may be arranged in an array along a row direction and a column direction. In some embodiments of the present disclosure, the pixel circuit10includes the driving transistor T1, a data writing circuit11and a storage capacitor C.

The data writing circuit11is connected to a scanning signal end Gate, a data signal end Data, and a first node N1, and is configured to provide, under control of a scanning signal from the scanning signal end Gate, a data signal from the data signal end Data to the first node N1.

The first node N1is connected to the control end G of the driving transistor T1, and the driving transistor T1is configured to output, under control of the first node N1, a driving current to a light-emitting device12.

The storage capacitor C is connected to a third node N3and the first node N1, and is configured to store a voltage difference between the third node N3and the first node N1. The compensation circuit40is connected to the third node N3, and is capable of compensating the threshold voltage of the driving transistor T1.

In some embodiments of the present disclosure, the pixel group1further includes a first reset circuit50that is connected to a first reset control signal end Rst1, a first reset voltage end Vref, and the third node N3, and is configured to reset the third node N3by providing, under control of a first reset control signal from the first reset control signal end Rst1, a first reset voltage from the first reset voltage end Vref to the third node N3. More than one of the pixel circuits10may share one first reset circuit50. For example, all pixel circuits10in one pixel group1share one first reset circuit50.

In some embodiments of the present disclosure, the driving transistor T1is connected to the first node N1, a second node N2, and a fifth node N5, and the light-emitting device12is connected to the fifth node N5and a second power supply voltage end VSS. The light-emitting device12may be a light-emitting diode or the like. The light-emitting diode may be an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED), etc.

The pixel group1is connected to a second reset circuit20and a light-emitting control circuit30. In some embodiments of the present disclosure, a plurality of pixel groups1may be connected to the same light-emitting control circuit30or/and the same second reset circuit20, i.e., a plurality of pixel groups1may share one second reset circuit20or one light-emitting control circuit30, or may share one second reset circuit20and one light-emitting control circuit30at the same time.

The second reset circuit20is connected to a second reset control signal end Rst2, a second reset voltage end Vinit, and the second node N2, and is configured to reset the second node N2by providing, under control of a second reset control signal from the second reset control signal end Rst2, a second reset voltage from the second reset voltage end Vinit to the second node N2.

The light-emitting control circuit30is connected to a light-emitting control signal end EM, the first power supply voltage end VDD, and the second node N2, and is configured to provide, under control of a light-emitting control signal from the light-emitting control signal end EM, a first power supply voltage from the first power supply voltage end VDD to the second node N2.

In some embodiments of the present disclosure, the compensation circuit40includes a second transistor T2and the third transistor T3. In some embodiments, the second transistor T2is connected to a compensation switch control signal end Com, a fourth node N4, and the third node N3, and is configured to conduct the third node N3and the fourth node N4under a compensation switch control signal from the compensation switch control signal end Com. A gate and a second electrode of the third transistor T3are connected to the fourth node N4, and a first electrode of the third transistor T3is connected to the first power supply voltage end VDD.

Furthermore, the compensation circuit40further includes a voltage regulator circuit, and the voltage regulator circuit is connected to the first power supply voltage end and the third node. Specifically, the voltage regulator circuit may include a first capacitor C01, and the first capacitor C01is connected to the first power supply voltage end VDD and the third node N3.

In some embodiments of the present disclosure, the data writing circuit11includes a fourth transistor T4, the first reset circuit50includes a fifth transistor T5, the second reset circuit20includes a sixth transistor T6, and the light-emitting control circuit30includes a seventh transistor T7.

A gate of the fourth transistor T4is connected to the scanning signal end Gate, a first electrode of the fourth transistor T4is connected to the data signal end Data, and a second electrode of the fourth transistor T4is connected to the first node N1.

A gate of the fifth transistor T5is connected to the first reset control signal end Rst1, a first electrode of the fifth transistor T5is connected to the first reset voltage end Vref, and a second electrode of the fifth transistor T5is connected to the third node N3.

A gate of the sixth transistor T6is connected to the second reset control signal end Rst2, a first electrode of the sixth transistor T6is connected to the second reset voltage end Vinit, and a second electrode of the sixth transistor T6is connected to the second node N2.

A gate of the seventh transistor T7is connected to the light-emitting control signal end EM, a first electrode of the seventh transistor T7is connected to the first power supply voltage end VDD, and a second electrode of the seventh transistor T7is connected to the second node N2.

In some embodiments of the present disclosure, the compensation switch control signal and the light-emitting control signal are the same signal; and the first reset control signal and the second reset control signal are the same signal.

In some embodiments of the present disclosure, the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7are P-type transistors.

In addition, it should be noted that the transistors used in the embodiments of the present disclosure may also be N-type transistors, and it is only required to connect the electrodes of the selected type of transistors accordingly with reference to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and to cause the corresponding voltage ends to provide the corresponding high voltages or low voltages. For example, for the N-type transistor, the input end thereof is the drain end, the output end thereof is the source end, and the control end thereof is the gate end; for the P-type transistor, the input end thereof is the source end, the output end thereof is the drain end, and the control end thereof is the gate end. For different types of transistors, levels of control signals of control ends of different types of transistors are also different. For example, for the N-type transistor, when the control signal is the high level, the N-type transistor is in the on state; and when the control signal is the low level, the N-type transistor is in the cut-off state. For the P-type transistor, when the control signal is the low level, the P-type transistor is in the on state; and when the control signal is the high level, the P-type transistor is in the cut-off state.

FIG.4is a timing diagram for driving the pixel group1inFIG.1. The working process of the pixel group1inFIG.1includes two phases, namely a data writing phase P1and a light-emitting phase P2. InFIG.1, three pixel circuits10are included, and the three pixel circuits10are located in different rows. The scanning signal ends Gate corresponding to the three pixel circuits10are Gate1, Gate2and Gate3respectively; the compensation switch control signal and the light-emitting control signal are the same signal, i.e., the light-emitting control signal EMS; and the first reset control signal and the second reset control signal are the same signal, i.e., the reset control signal RST.

At the data writing phase P1, the light-emitting control signal end EM and the compensation switch control signal end Com output the high level signal EMS, the first reset control signal end Rst1and the second reset control signal end Rst2output the low level signal RST, and the scanning signal ends Gate of the three pixel circuits10output low level signals GA1, GA2and GA3in sequence row by row; and the data signal ends Data of the three pixel circuits10output data signals DA.

At the data writing phase P1, the fifth transistor T5is on, the first reset voltage end Vref applies the first reset voltage Vre to the third node N3, and to the first plates of the storage capacitors C of the three pixel circuits10at the same time; the sixth transistor T6is on, the driving transistor T1is cut-off, and the second reset voltage end Vinit resets the second node N2by applying the second reset voltage Vin to the second node N2, thereby avoiding the influence on the other rows of pixel circuits10due to the voltage fluctuation of the second node N2when the data signals DA is written to the corresponding pixel circuits10row by row; the fourth transistors T4of the three pixel circuits10are on in sequence row by row, and the data signal ends Data writes the data signals DA to the first nodes N1of the corresponding pixel circuits10row by row.

At the data writing phase P1, the second transistor T2and the seventh transistor T7are cut-off.

It can be understood that at the data writing phase P1, the fifth transistor T5is on, the voltage of the third node N3is Vre, the fourth transistor T4is on, the voltage of the first node N1is Vda, and the voltage difference between the first node N1and the third node N3is Vda-Vre.

At the light-emitting phase P2, the light-emitting control signal end EM and the compensation switch control signal end Com output the low level signal EMS, the first reset control signal end Rst1and the second reset control signal end Rst2output the high level signal RST, and the scanning signal ends Gate of the three pixel circuits10output high level signals GA1, GA2and GA3.

At the light-emitting phase P2, the seventh transistor T7is on, the first power supply voltage end VDD outputs the first power supply voltage and applies it to the second node N2; the second transistor T2is on, the voltage of the third node N3is applied to the fourth node N4, the third transistor T3is on, the first power supply voltage end VDD charges the storage capacitors C of the three pixel circuits10by outputting the first power supply voltage which passes through the third transistor T3and the second transistor T2, that is, charging the first nodes N1(the control end G of the driving transistor T1) of the three pixel circuits10, and thus the voltages of the first nodes N1(the control end G of the driving transistor T1) gradually increase.

At the light-emitting phase P2, the sixth transistor T6, the fifth transistor T5, and the fourth transistors T4of the three pixel circuits10are cut-off.

It can be understood that at the light-emitting phase P2, the seventh transistor T7is on, and the voltage of the second node N2is Vdd; the second transistor T2is on, the initial voltage of the fourth node N4is Vre, the third transistor T3is on, and the voltage of the fourth node N4begins to increase; according to the characteristic of the third transistor T3itself, when the voltage of the fourth node N4increases to Vdd+Vth0, the third transistor T3is cut-off, where Vdd indicates the first power supply voltage, and Vth0 indicates the threshold voltage of the third transistor T3. Since the second transistor T2is on, the voltage of the third node N3increases gradually with the voltage of the fourth node N4, and is finally Vdd+Vth0 . Since the voltage difference between the first node N1and the third node N3is Vda−Vre, the voltage of the first node N1increases to Vdd+Vth0+Vda−Vre. The driving transistor T1emits light under the action of the voltage Vdd+Vth0+Vda−Vre. According to the driving transistor T1output current formula I=(μWCox/2L)(Vgs−Vth)2, where u is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T1, L is the length of the channel of the driving transistor T1, Vgs is the gate source voltage difference of the driving transistor T1, and Vth is the threshold voltage of the driving transistor T1, the output current I of the driving transistor T1in the pixel circuit10of the present disclosure is: I=(μWCox/2L)(Vdd+Vth0+Vda−Vref−Vdd−Vth)2. In the present disclosure, the threshold voltage of the third transistor T3and the threshold voltage of the driving transistor T1are equal, i.e., Vth0=Vth. Therefore, the output current I of the driving transistor T1in the pixel circuit10of the present disclosure is I=(μWCox/2L)(Vda−Vref)2, which can avoid the influence of the threshold value of the driving transistor T1on its output current.

In some embodiments of the present disclosure, the channel region of the seventh transistor T7has a width to length ratio of a7, the channel region of the driving transistor T1has a width to length ratio of a1, and a7/a1=5.75-7.05, which may specifically be 5.83, 6, 6.85, or 6.9, but is not limited to this, and may specifically be any value in the range of 5.75-7.05. In some embodiments, the width to length ratio of the channel region of the seventh transistor T7is a7=0.95-1.05, and the width to length ratio of the channel region of the driving transistor T1is a1=0.145-0.175. For example, the width to length ratio of the channel region of the seventh transistor T7is a7=5/5=1, and the width to length ratio of the channel region of the driving transistor T1is a1=2/12, 2/13.7, 2/13.3, or 1.5/8.75, etc., but is not limited to this.

The channel region of the sixth transistor T6has a width to length ratio of a6,the channel region of the driving transistor T1has a width to length ratio of a6, and a6/a1=2.25-2.86, which may specifically be 2.33, 2.4, 2.74, or 2.76, but is not limited to this, and may be any value in the range of 2.25-2.86. In some embodiments, the sixth transistor T6has a width to length ratio of a6=0.35-0.45. For example, the width to length ratio of the channel region of the sixth transistor T6is a6=2/5-0.4.

In the present disclosure, the width to length ratios of the channel regions of the sixth transistor T6and the seventh transistor T7are larger than the width to length ratio of the channel region of the driving transistor T1. This structural design facilitates providing the sixth transistor T6and the seventh transistor T7with sufficient current to drive a plurality of pixel groups1.

Furthermore, the channel region of the seventh transistor T7has a width to length ratio of a7, the channel region of the sixth transistor T6has a width to length ratio of a6, and a7/a6=2.45-2.55, which may specifically be 2.45, 2.5 or 2.55, but is not limited to this, and may specifically be any value in the range of 2.45-2.55.

In some embodiments of the present disclosure, all of the width to length ratio a1 of the channel region of the driving transistor T1, the width to length ratio a2 of the channel region of the second transistor T2, the width to length ratio a3 of the channel region of the third transistor T3, the width to length ratio a4 of the channel region of the fourth transistor T4, the width to length ratio a5 of the channel region of the fifth transistor T5, and the width to length ratio a6 of the channel region of the sixth transistor T6are smaller than the width to length ratio a7 of the channel region of the seventh transistor T7.

Specifically, the width to length ratio of the channel region of the second transistor T2is a2=0.75-0.85, e.g., a2=2/2.5=0.8, but is not limited thereto; the width to length ratio a3 of the channel region of the third transistor is substantially equal to the width to length ratio of the channel region of the driving transistor T1, where a3=0.145-0.175, e.g., a3=2/12, 2/13.7, 2/13.3, or 1.5/8.75, etc., but is not limited thereto; the width to length ratio of the channel region of the fourth transistor T4is a4=0.75-0.85, e.g., a4=2/2.5=0.8, but is not limited thereto; and the width to length ratio of the channel region of the fifth transistor T5is a5=0.35-0.45, e.g., a5=2/5=0.4, but is not limited thereto. The width to length ratio a6 of the channel region of the sixth transistor T6and the width to length ratio a7 of the channel region of the seventh transistor T7can refer to the above description, and will not be repeated in detail herein.

As shown inFIGS.2and3, the present disclosure also provides an array substrate including a substrate and a plurality of pixel groups1as described above, where the plurality of pixel groups1are located at a side of the substrate.

Each pixel group1in the plurality of pixel groups1includes a plurality of pixel circuits10and one compensation circuit40, the numbers of pixel circuits10in the pixel groups1may be the same or different, and at least two of the pixel groups include different numbers of the pixel circuits10. For example, the number of pixel circuits10in one pixel group1is 6, and the number of pixel circuits10in another pixel group1is 6 or 9, or some other greater numbers. Including different numbers of pixel circuits10in the pixel groups1is conducive to reducing the risk of uneven display brightness of the display panel.

The plurality of pixel circuits10in each of the pixel groups1are arranged in an array, i.e., each pixel group1includes the plurality of pixel circuits10arranged in a plurality of rows and columns. In some embodiments of the present disclosure, the pixel groups1include the same number of rows of the pixel circuits10, the same number of columns or different numbers of columns of the pixel circuits10, and at least two of the pixel groups1include different numbers of columns of the pixel circuits10.

In some embodiments of the present disclosure, more than one of the pixel groups1are arranged along the row direction to form a row unit01, the array substrate includes a plurality of rows of row units01, and separating lines1abetween two adjacent pixel groups1are staggered in two adjacent rows of the row units01. In the present disclosure, the separating line1abetween two adjacent pixel groups1refers to a dividing line between the two adjacent pixel groups1, and the two pixel groups are located at different sides of the dividing line. For example, the separating line1aof the row unit011and the separating line1aof the row unit012adjacent to the row unit011are staggered. This structural design, while reducing the process difficulty, is conducive to reducing the risk of uneven display brightness of the display panel. Furthermore, in the row unit01, the numbers of columns of the pixel circuits10included in two adjacent pixel groups1are different. For example, in two pixel groups1, one of the two pixel groups1includes two rows and three columns of pixel circuits10, that is, including six pixel circuits10, and the other one of the two pixel groups1includes two rows and nine columns of pixel circuits10, that is, including 18 pixel circuits10. In the present disclosure, the arrangement of the pixel groups1is conducive to reducing the brightness difference between the pixel groups01, blurring the display boundary between pixel groups1adjacent to each other, and thus reducing the mura risk of the display panel.

The substrate includes a display area AA and a non-display area FA located at a periphery of the display area AA, and an orthographic projection of the pixel group1on the substrate is located in the display area AA. The display area AA is used for displaying an image. The light-emitting control circuit30and the second reset circuit20to which the plurality of pixel groups1are connected are also located at a side of the substrate, and orthographic projections, on the substrate, of the light-emitting control circuit30and the second reset circuit20are located in the non-display area FA. Specifically, the orthographic projections, on the substrate, of the light-emitting control circuit30and the second reset circuit20may be located at two sides of the display area AA, or may be located at only one side of the display area AA, the specifics of which are not limited in the present disclosure. Preferably, to ensure the driving effect, the light-emitting control circuit30and the second reset circuit20are located at two sides of the display area AA. The array substrate may further include a gate driving circuit, and an orthographic projection of the gate driving circuit on the substrate is located in the non-display area FA. The light-emitting control circuit30and the second reset circuit20are located at a side of the gate driving circuit close to the display area AA.

The plurality of pixel groups1may share one light-emitting control circuit30and one second reset circuit20. For example, the plurality of rows of row units01may be jointly connected to one light-emitting control circuit30and one second reset circuit20, i.e., the plurality of rows of pixel groups1share one light-emitting control circuit30and one second reset circuit20; of course, it is also possible that each row of row units01is connected to one light-emitting control circuit30and one second reset circuit20, or that some of the pixel groups1in each row of row units01are connected to one light-emitting control circuit30and one second reset circuit20, and the remaining pixel groups1in that row of row units01are connected to another light-emitting control circuit30and another second reset circuit20, the specifics of which are not limited in the present disclosure.

In the present disclosure, the plurality of pixel groups1share one light-emitting control circuit30and one second reset circuit20, which is conducive to reducing the size of a single pixel group1, i.e., reducing the size of each pixel circuit10in the pixel group1, thereby helping to increase the PPI of the display panel and achieve a high PPI design effect.

Next, pattern structures of respective film layers of the pixel circuit10, the compensation circuit40and the first reset circuit50that are included in the array substrate are illustrated by using a certain pixel group1as an example. In addition, to more clearly illustrate the structural design of the array substrate in the present disclosure, pattern structures of respective film layers of the second reset circuit20and the light-emitting control circuit30are also illustrated simultaneously.

As shown inFIG.5, the array substrate further includes an active semiconductor layer100located at a side of the substrate. The active semiconductor layer100includes an active layer of at least one pixel group1. The active semiconductor layer100includes a plurality of first semiconductor portion groups110and a second semiconductor portion120located between any two adjacent ones of the first semiconductor portion groups110. Specifically, the active semiconductor layer100includes the plurality of first semiconductor portion groups110arranged along the column direction, and the second semiconductor portion120located between any two adjacent ones of the first semiconductor portion groups110. Orthographic projections, on the substrate, of the first semiconductor portion groups110and the second semiconductor portion120are located in the display area AA.

In some embodiments, the first semiconductor portion group110includes a first semiconductor portion sub-group and a second semiconductor portion sub-group. The first semiconductor portion sub-group is located at a side, along the column direction, of the second semiconductor portion sub-group, and specifically at a side of the second semiconductor portion sub-group away from the second semiconductor portion120, but is not limited thereto, for example, a side of the second semiconductor portion sub-group close to the second semiconductor portion120.

The first semiconductor portion sub-group includes a plurality of first semiconductor sub-portions111, the plurality of first semiconductor sub-portions111are arranged along the row direction, and the first semiconductor sub-portion111includes an active layer of the fourth transistor T4; the second semiconductor portion sub-group includes a plurality of second semiconductor sub-portions112, the second semiconductor sub-portions112are arranged along the row direction, and the second semiconductor sub-portion112includes an active layer of the driving transistor T1.

In an embodiment, the first semiconductor sub-portion111may be separated from and disconnected with the second semiconductor sub-portion112, as shown inFIG.5. In another embodiment, the first semiconductor sub-portion111and the second semiconductor sub-portion112may also be connected to form an integrated structure, the specifics of which are not limited in the present disclosure. In addition, the first semiconductor sub-portions111and the second semiconductor sub-portions112in two adjacent first semiconductor portion groups110may be in a mirror-symmetrical distribution. Referring specifically toFIG.5, the first semiconductor sub-portions111and the second semiconductor sub-portions112in two adjacent first semiconductor portion groups110are symmetrical with respect to an axis OL. The axis OL is a central axis of the pixel group1parallel to the row direction.

The first semiconductor sub-portion111and the second semiconductor sub-portion112may have various shapes. In an embodiment, the first semiconductor sub-portion111is substantially in a “1” shape, and the second semiconductor sub-portion112is substantially in an “S” shape. In another embodiment, the first semiconductor sub-portion111may be in a “T” shape, “S” shape, or other shapes, and the second semiconductor sub-portion112may also be in a “1” shape, “T” shape, or other shapes, the specifics of which are not limited in the present disclosure.

The second semiconductor portion120includes an active layer of the third transistor T3, an active layer of the second transistor T2, and an active layer of the fifth transistor T5. The active layer of the third transistor T3, the active layer of the second transistor T2, and the active layer of the fifth transistor T5are sequentially arranged along the row direction.

In an exemplary embodiment of the present disclosure, the active semiconductor layer100includes a channel region pattern and a doped region pattern of the transistor, and the doped region refers to a first electrode region and a second electrode region of the transistor. In an embodiment of the present disclosure, channel region patterns and doped region patterns of respective transistors are provided integrally.

It should be noted that inFIG.5, dashed boxes are used to mark regions in the active semiconductor layer100for the first electrode/second electrode regions and the channel regions of respective transistors.

The first semiconductor sub-portion111includes, in an order along the column direction, a first electrode region T4-s,a channel region T4-c,and a second electrode region T4-dof the fourth transistor T4. The second semiconductor sub-portion112includes, in an order along the column direction, a second electrode region T1-d,a channel region T1-c,and a first electrode region T1-sof the driving transistor T1. The first electrode regions T1-sof a plurality of second semiconductor sub-portions112arranged along the row direction are connected to form an integrated structure.

It should be noted herein that inFIG.5, the pixel group1includes two rows and six columns of pixel circuits10, i.e., including 12 pixel circuits10. The number of the first semiconductor sub-portions111and the number of the second semiconductor sub-portions112are equal to the number of the pixel circuits10.

The second semiconductor portion120includes, in an order along the row direction, a channel region T3-cof the third transistor T3, a channel region T2-cof the second transistor T2, and a channel region T5-cof the fifth transistor T5. The second semiconductor portion120further includes a first electrode region T3-sand a second electrode region T3-dof the third transistor T3, where the first electrode region T3-sis located at a side, along the column direction, of the channel region T3-cof the third transistor T3, and the second electrode region T3-dis located between the channel region T3-cof the third transistor T3and the channel region T2-cof the second transistor T2along the row direction. The second semiconductor portion120further includes a first electrode region T2-sand a second electrode region T2-dof the second transistor T2, where the second electrode region T3-dof the third transistor T3is used as the second electrode region T2-dof the second transistor T2, and the first electrode region T2-sof the second transistor T2is located between the channel region T2-cof the second transistor T2and the channel region T5-cof the fifth transistor T5along the row direction. The second semiconductor portion120further includes a first electrode region T5-sand a second electrode region T5-dof the fifth transistor T5, where the first electrode region T5-sof the fifth transistor T5is located at a side, along the row direction, of the channel region T5-cof the fifth transistor T5, and the first electrode region T2-sof the second transistor T2is used as the second electrode region T5-dof the fifth transistor T5.

In some embodiments of the present disclosure, the active semiconductor layer100further includes a third semiconductor portion130whose orthographic projection on the substrate is located in the non-display area FA. specifically, the third semiconductor portion130may be located at one or two sides, along the row direction, of the display area AA. Specifically, in an embodiment, the third semiconductor portion130is located at two sides of the display area AA, with only one side exemplarily shown inFIG.5, and the other side may be designed with reference to the structure inFIG.5. The third semiconductor portion130includes an active layer of the sixth transistor T6and an active layer of the seventh transistor T7. The active layer of the seventh transistor T7is located at a side, along the row direction, of a row of the first semiconductor portion groups110, and the active layers of the plurality of seventh transistors T7are arranged along the column direction. InFIG.5only two rows of the first semiconductor portion groups110, and two active layers of the seventh transistors T7are shown exemplarily. The active layer of the sixth transistor T6is located at a side, along the row direction, of the second semiconductor portion120. Furthermore, the active layer of the sixth transistor T6may be located between the active layers of two adjacent seventh transistors T7.

In some embodiments of the present disclosure, each row of the pixel circuits10in a single pixel group1is connected to one sixth transistor T6and one seventh transistor T7. The active layers of the sixth transistors T6connected to two adjacent rows of the pixel circuits10, and the active layers of the seventh transistors T7connected to two adjacent rows of the pixel circuits10are mirror symmetrical with respect to the central axis of the pixel group1parallel to the row direction. Referring toFIG.5, the active layers of the sixth transistors T6connected to two adjacent rows of the pixel circuits10and the active layers of the seventh transistors T7connected to two adjacent rows of the pixel circuits10are mirror symmetrical with respect to the axis OL. That is, the distances between the axis OL and the active layers of the sixth transistors T6that are connected to two adjacent rows of the pixel circuits10are equal, and the distances between the axis OL and the active layers of the seventh transistors T7that are connected to two adjacent rows of the pixel circuits10are equal.

Specifically, the active layer of the seventh transistor T7includes a first electrode region T7-s,a channel region T7-c,and a second electrode region T7-dof the seventh transistor T7. The first electrode region T7-sof the seventh transistor T7is located at a side, along the column direction, of the channel region T7-c,and is specifically located at a side away from the active layer of the sixth transistor T6. The second electrode region T7-dof the seventh transistor T7is substantially located at a side, along the row direction, of the channel region T7-c,and is specifically at a side close to the display area AA. The second electrode region T7-dof the seventh transistor T7is used as the second electrode region T6-dof the sixth transistor T6, and is further connected to the first electrode region T1-sof the driving transistor T1to form an integrated structure.

The first electrode region T6-sof the sixth transistor T6is located between the channel regions T7-cof two adjacent seventh transistors T7arranged along the column direction, and the channel region T6-cof the sixth transistor T6may be located at a side, along the row direction, of the first electrode region T6-sof the sixth transistor T6, such as at a side close to the display area AA, or/and at a side, along the column direction, of the second electrode region T6-dof the sixth transistor T6. In some embodiments, the sixth transistor T6may be a dual-gate transistor, and may have two channel regions T6-c.

In an embodiment of the present disclosure, the first electrode region may be a source region, and the second electrode region may be a drain region. The first electrode region and the second electrode region may be regions doped with P-type impurities.

As shown inFIGS.6and7, in some embodiments of the present disclosure, the array substrate further includes a first conductive layer200located at a side of the active semiconductor layer100away from the substrate, where the first conductive layer200includes a plurality of first conductive portion groups210and a second conductive portion group220located between any two adjacent ones of the first conductive portion groups210. Specifically, the first conductive layer200includes the plurality of first conductive portion groups210arranged along the column direction, and the second conductive portion group220located between any two adjacent ones of the first conductive portion groups210.

In some embodiments, the first conductive portion group210includes a scanning signal line GAL and gates T1-gof a plurality of driving transistors T1, and the number of the gates T1-gof the driving transistors T1is equal to the number of the second semiconductor sub-portions112. The gates T1-gof the plurality of driving transistors T1are arranged along the row direction. Orthographic projections, on the substrate, of the gates T1-gof the plurality of driving transistors T1are at least partially overlapped with orthographic projections of the second semiconductor sub-portions112on the substrate. The gate T1-gof the driving transistor T1is used as the first plate C1of the storage capacitor C. That is, the first conductive layer200includes the first plate C1of the storage capacitor C, and the first plate C1of the storage capacitor C, and the gate T1-gof the driving transistor T1may be the same structure.

The scanning signal line GAL extends along the row direction and across the display area AA and the non-display area FA. The scanning signal line GAL is located at a side, along the column direction, of the gates T1-gof the plurality of driving transistors T1, and may be specifically located at a side of the gates T1-gof the plurality of driving transistors T1away from the second conductive portion group220, but is not limited thereto. The scanning signal line GAL is connected to the scanning signal end Gate, and is configured to provide the scanning signal to the scanning signal end Gate. The portion, whose orthographic projection on the substrate is overlapped with the orthographic projection of the first semiconductor sub-portion111on the substrate, of the scanning signal line GAL is the gate of the fourth transistor T4.

The second conductive portion group220includes a first plate C11of the first capacitor C01. The first plate C11of the first capacitor C01has a length in the row direction that is greater than its length in the column direction. In some embodiments, the length, in the row direction, of the first plate C11of the first capacitor C01is at least greater than the length, in the row direction, of one pixel circuit, i.e., at least greater than the length, in the row direction, of one sub-pixel of the display panel. For example, the length, in the row direction, of the first plate C11of the first capacitor C01may be substantially the length, in the row direction, of two or three or more pixel circuits or sub-pixels.

Furthermore, the second conductive portion group220further includes the gate T3-gof the third transistor T3, a third conductive sub-portion221, and a fourth conductive sub-portion222. Specifically, the second conductive portion group220may include the first plate C11of the first capacitor C01, the gate T3-gof the third transistor T3, the third conductive sub-portion221, and the fourth conductive sub-portion222that are arranged along the row direction. It should be noted herein that the first plate C11of the first capacitor C01, the gate T3-gof the third transistor T3, the third conductive sub-portion221, and the fourth conductive sub-portion222are arranged in a manner that the present disclosure does not impose a special limitation, and the specifics may be set according to actual needs. The portion, whose orthographic projection on the substrate is overlapped with the orthographic projection of the second semiconductor portion120on the substrate, of the third conductive sub-portion221is the gate of the second transistor T2; and the portion, whose orthographic projection on the substrate is overlapped with the orthographic projection of the second semiconductor portion120on the substrate, of the fourth conductive sub-portion222is the gate of the fifth transistor T5.

In some embodiments, the gate pattern of the driving transistor T1is the same as the gate pattern of the third transistor T3; and the overlapped portion between the active layer and the gate of the driving transistor T1is of the same pattern as the overlapped portion between the active layer and the gate of the third transistor T3, so as to make the threshold voltage of the third transistor T3and the threshold voltage of the driving transistor T1equal. It should be noted herein that, due to process errors, the gate pattern of the driving transistor T1being the same as the gate pattern of the third transistor T3, and the overlapped portion between the active layer and the gate of the driving transistor T1being of the same pattern as the overlapped portion between the active layer and the gate of the third transistor T3refer to being the same within the range of process errors, and not being the same in an absolute sense. Similarly, the threshold voltages of the third transistor T3and the driving transistor T1are subject to a certain error, and therefore, in the present disclosure, the threshold voltage of the third transistor T3and the threshold voltage of the driving transistor T1being equal refers to being substantially equal, and not being equal in an absolute sense.

In some embodiments of the present disclosure, the first conductive layer200further includes an eighth conductive portion group230, and an orthographic projection of the eighth conductive portion group230on the substrate is located in the non-display area FA. The eighth conductive portion group230is located between two adjacent rows of scanning signal lines GAL. The eighth conductive portion group230includes a plurality of conductive portions231arranged along the column direction, and a conductive portion232located between adjacent ones of the conductive portions231. A region where the conductive portion231is overlapped with the active layer of the seventh transistor T7is the gate of the seventh transistor T7, and a region where the conductive portion232is overlapped with the active layer of the sixth transistor T6is the gate of the sixth transistor T6.

In some embodiments of the present disclosure, an insulating layer, such as a first gate insulating layer, is further provided between the active semiconductor layer100and the first conductive layer200.

As shown inFIG.8,FIG.9,FIG.15, andFIG.16, in some embodiments of the present disclosure, the array substrate further includes a second conductive layer300located at a side of the first conductive layer200away from the substrate. The second conductive layer300includes second plates C2of a plurality of storage capacitors C. The second plates C2of the plurality of storage capacitors C included in a single pixel group1form an integrated structure.

The array substrate further includes a first power supply voltage line VDDL extending along the row direction, where the first power supply voltage line VDDL is connected to the first plate C11of the first capacitor C01; a second electrode region T2-dof the active layer of the second transistor T2is electrically connected to the second plate C2of the storage capacitor C, and the second plate C2of the storage capacitor C is electrically connected to a second plate C12of the first capacitor C01. Specifically, the second electrode region T2-dof the second transistor T2is electrically connected to the second plate C2of the storage capacitor C via a first adapter portion; and the second plate C2of the storage capacitor C is electrically connected to the second plate C12of the first capacitor C01via a second adapter portion. In the present disclosure, by connecting the storage capacitor C to one plate of the first capacitor C01via the second adapter portion, and connecting the other plate of the first capacitor C01to the first power supply voltage line VDDL, the first power supply voltage line VDDL can provide a constant power supply voltage. This scheme can better regulate the voltage of the third node N3, and prevent the jump generated by the first node N1in writing data from affecting the third node N3.

The first adapter portion and the second adapter portion are provided in the same layer. In the present disclosure, providing in the same layer refers to being made by using the same material and the same process.

In some embodiments of the present disclosure, the first adapter portion and the second adapter portion extend along the column direction.

The array substrate further includes a reset voltage line VINL extending along the row direction. The reset voltage line VINL and the first power supply voltage line VDDL are provided in the same layer. Orthographic projections, on the substrate, of the reset voltage line VINL and the first power supply voltage line VDDL are located between orthographic projections, on the substrate, of two adjacent rows of the second plates C12of the storage capacitors C.

An orthographic projection of the first adapter portion on the substrate is at least partially overlapped with the orthographic projections, on the substrate, of the reset voltage line VINL and the first power supply voltage line VDDL; and an orthographic projection of the second adapter portion on the substrate is at least partially overlapped with the orthographic projections, on the substrate, of the reset voltage line VINL and the first power supply voltage line VDDL. In this scheme, the first adapter portion and the second adapter portion are at least partially overlapped with the first power supply voltage line VDDL, which is conducive to playing a certain role in voltage stabilizing for the first adapter portion and the second adapter portion, thereby further enhancing the display effect.

The first adapter portion and the first power supply voltage line VDDL are provided in different layers. That is, the first adapter portion and the second adapter portion are located in the same layer, and the first power supply voltage line VDDL and the reset voltage line VINL are located in another layer.

For example, the array substrate further includes a third conductive layer400located at a side of the second conductive layer300away from the substrate. The first power supply voltage line VDDL and the reset voltage line VINL are distributed in the second conductive layer300, and the first adapter portion and the second adapter portion are distributed in the third conductive layer400. Alternatively, the first adapter portion and the second adapter portion are distributed in the second conductive layer300, the second adapter portion and the second plate C12of the first capacitor C01form an integrated structure, and the first power supply voltage line VDDL and the reset voltage line VINL are distributed in the third conductive layer400.

The pattern structures of the second conductive layer300and the third conductive layer400will be described in detail below in connection with different embodiments.

As shown inFIGS.8and9, in some embodiments, the second conductive layer300includes a plurality of third conductive portion groups310arranged along the column direction, and a fourth conductive portion group320located between any two adjacent ones of the third conductive portion groups310. Specifically, the second conductive layer300includes the plurality of third conductive portion groups310arranged along the column direction, and the fourth conductive portion group320located between any two adjacent third conductive portion groups310.

The third conductive portion group310includes a first connection portion set and second plates C2of the plurality of storage capacitors C. The first connection portion set includes a plurality of first connection portions311, where the plurality of first connection portions311are arranged along the row direction. The first connection portion311is connected to the gate T1-gof the driving transistor T1, and the second electrode region T4-dof the active layer of the fourth transistor T4, which may be specifically connected through vias. InFIG.9, a black block structure indicates a via. The second plates C2of the plurality of storage capacitors C are located at a side, along the column direction, of the first connection set group, and specifically may be located at a side of the first connection portion set close to the fourth conductive portion group320.

It should be noted herein that, as shown inFIG.17, the second plates C2of the plurality of storage capacitors C included in a single pixel group1form an integrated structure, and second plates C2of storage capacitors C in two adjacent pixel groups1are separated from each other. The separated position is the separating line la between the two adjacent pixel groups1.

The third conductive portion group310further includes an eighth connection portion set, where the eighth connection portion set includes a plurality of eighth connection portions312arranged along the row direction. The eighth connection portion set is located at a side, along the column direction, of the first connection portion set, and specifically located at a side of the first connection portion set away from the second plate C2of the storage capacitor C. The eighth connection portion312is connected, through a via, to the first electrode region T4-s,which is exposed outside the first conductive layer200, of the active layer of the fourth transistor T4.

The fourth conductive portion group320includes the first power supply voltage line VDDL, a compensation switch control signal line COL, a fifth conductive portion sub-group321, the reset voltage line VINL, and a reset control signal line RSTL. The fifth conductive portion sub-group321includes the second plate C12of the first capacitor C01, and a second connection portion3211, where the second connection portion3211and the second plate C12of the first capacitor C01are arranged along the row direction. In some embodiments of the present disclosure, the compensation switch control signal line COL may be used as the light-emitting control signal line EML.

As shown inFIG.9, the first power supply voltage line VDDL is connected to the first power supply voltage end VDD, and is configured to provide the first power supply voltage to the first power supply voltage end VDD. The first power supply voltage line VDDL is connected, through a via, to the first electrode region T3-sof the active layer of the third transistor T3. The first power supply voltage line VDDL is connected, through a via, to the first plate C11of the first capacitor C01.

The first power supply voltage line VDDL extends to the non-display area FA along the row direction, and the first power supply voltage line VDDL is connected, through a via, to the first electrode region T7-sof the active layer of the seventh transistor T7.

The compensation switch control signal line COL is connected to the compensation switch control signal end Com, and is configured to provide the compensation switch control signal to the compensation switch control signal end Com. The compensation switch control signal and the light-emitting control signal are the same signal. The compensation switch control signal line COL is connected, through a via, to the gate of the second transistor T2. The compensation switch control signal line COL is used as the light-emitting control signal line EML, and is connected to the gate of the seventh transistor T7through a via.

The second connection portion3211is connected, through vias, to the gate T3-gof the third transistor T3, and the second electrode region T3-dof the active layer of the third transistor T3. The second electrode region T3-dof the third transistor T3is used as the second electrode region T2-dof the second transistor T2.

The reset voltage line VINL is connected to the first reset voltage end Vref, and is configured to provide the first reset voltage to the first reset voltage end Vref. The reset voltage line VINL is connected, through a via, to the first electrode region T5-s,which is exposed outside the first conductive layer200, of the active layer of the fifth transistor T5. The reset voltage line VINL may also be connected to the second reset voltage end Vinit, and configured to provide the second reset voltage to the second reset voltage end Vinit. The reset voltage line VINL may also be connected, through a via, to the first electrode region T6-s,which is exposed outside the first conductive layer200, of the active layer of the sixth transistor T6

The reset control signal line RSTL is connected to the first reset control signal end Rst1, and is configured to provide the first reset control signal to the first reset control signal end Rst1. The reset control signal line RSTL is connected to the gate of the fifth transistor T5through a via. The reset control signal line RSTL may also be connected to the second reset control signal end Rst2, and configured to provide the second reset control signal to the second reset control signal end Rst2. The reset control signal line RSTL is connected to the gate of the sixth transistor T6through a via.

Furthermore, an insulating layer, such as a second gate insulating layer, is further provided between the second conductive layer300and the first conductive layer200. The second gate insulating layer is provided with vias at certain positions to realize the above-described connections between certain regions of the second conductive layer300and the first conductive layer200or the active semiconductor layer100.

As shown inFIGS.10and11, the array substrate further includes a third conductive layer400located at a side of the second conductive layer300away from the substrate. The third conductive layer400includes a plurality of fifth conductive portion groups410arranged along the column direction, and a sixth conductive portion group420located between any two adjacent ones of the fifth conductive portion groups410. Specifically, the third conductive layer400includes the plurality of fifth conductive portion groups410arranged along the column direction, and the sixth conductive portion group420located between any two adjacent fifth conductive portion groups410. Orthographic projections, on the substrate, of the fifth conductive portion group410and the sixth conductive portion group420are located in the display area AA.

In some embodiments, the fifth conductive portion group410includes a plurality of fifth conductive portions411arranged along the row direction, and the fifth conductive portion411is connected, through a via, to the second electrode region T1-d,which is exposed outside the first conductive layer200, of the active layer of the driving transistor T1.

The sixth conductive portion group420includes a third connection portion421and a fourth connection portion422arranged along the row direction. The third connection portion421is the second adapter portion, and the fourth connection portion422is the first adapter portion. In some embodiments, the third connection portion421is connected, through vias, to the second plate C12of the first capacitor C01, and the second plates C2of the storage capacitors C of the plurality of third conductive portion groups310. The second plates C2of the storage capacitors C of the plurality of third conductive portion groups310are all connected to the second plate C12of the first capacitor C01through the third connection portion421. In the modules shown inFIGS.8and11, two third conductive portion groups310are included, each third conductive portion group310includes a plurality of storage capacitors C, the second plates of the plurality of storage capacitors C form an integrated structure, and the second plates C2of the storage capacitors C included in two conductive portion groups are all connected to the second plate C12of the first capacitor C01through the third connection portion421.

The fourth connection portion422is connected, through a via, to the second electrode region T5-dof the active layer of the fifth transistor T5, the second electrode region T5-dof the fifth transistor T5is used as the first electrode region T2-sof the second transistor T2, and the fourth connection portion422is connected, through vias, to the second plates C2of the storage capacitors C of the plurality of third conductive portion groups310. Similarly, the second plates C2of the storage capacitors C of the plurality of third conductive portion groups310are all connected to the second plate C12of the first capacitor C01through the fourth connection portion422.

The third conductive layer400further includes a ninth conductive portion group430, and an orthographic projection of the ninth conductive portion group430on the substrate is located in the non-display area FA. The ninth conductive portion group430includes a conductive portion431, a conductive portion432, a conductive portion433, a conductive portion434, and a conductive portion435that are sequentially arranged along the row direction. The conductive portion431is connected to the gates of different seventh transistors T7, and is connected to a peripheral control circuit. Specifically, the conductive portion431may be connected to the peripheral control circuit through the conductive portion233distributed in the first conductive layer200. The conductive portion432is connected to the first electrode region T6-sof the sixth transistor T6through a via, and may further be connected to the reset voltage line VINL. The conductive portion433is connected to the first electrode region T7-sof the seventh transistor T7through a via, and may further be connected to the first power supply voltage line VDDL. The conductive portion434is connected to the reset voltage line VINL through a via, and may further be connected to an output end at the periphery for transmitting the first reset voltage. The conductive portion435is connected to the gate of the seventh transistor T7through a via, and may further be connected to the light-emitting control signal line EML.

An insulating layer, such as an interlayer dielectric layer, is further provided between the second conductive layer300and the third conductive layer400.

As shown inFIGS.15and16, in other embodiments of the present disclosure, the layouts of the second conductive layer and the third conductive layer included in the array substrate are different from those in the above embodiments.

As shown inFIGS.15and16, in this embodiment, the second conductive layer300′ includes a plurality of third conductive portion groups310′, and a fourth conductive portion group320′ located between any two adjacent ones of the third conductive portion groups310′. Specifically, the second conductive layer300′ includes the plurality of third conductive portion groups310′ arranged along the column direction, and the fourth conductive portion group320′ located between any two adjacent third conductive portion groups310′.

The third conductive portion group310′ includes a first connection portion set and second plates C2′ of the plurality of storage capacitors C. The first connection portion set includes a plurality of first connection portions311′, and the plurality of first connection portions311′ are arranged along the row direction. The second plates C2′ of the plurality of storage capacitors C form an integrated structure. The second plates C2′ of the plurality of storage capacitors are located at a side, along the column direction, of the first connection portion set, specifically at a side of the first connection portion set close to the fourth conductive portion group320′. The first connection portion311′ is connected, through vias, to the gate T1-gof the driving transistor T1, and the second electrode region T4-dof the active layer of the fourth transistor T4.

The third conductive portion group310′ may further include an eighth connection portion set, where the eighth connection portion set includes a plurality of eighth connection portions312′ arranged along the row direction. The eighth connection portion set is located at a side, along the column direction, of the first connection portion set, specifically at a side of the first connection portion set away from the second plate C2′ of the storage capacitor C. The eighth connection portion312′ is connected, through a via, to the first electrode region T4-s,which is exposed outside the first conductive layer200, of the active layer of the fourth transistor T4.

The fourth conductive portion group320′ includes the second plate C12′ of the first capacitor C01, a sixth connection portion321′, and a seventh connection portion322′ that are arranged along the row direction. The second plate C12′ of the first capacitor C01is connected to the second plates C2′ of the plurality of storage capacitors C to form an integrated structure, and the connection structure between the second plate C12′ of the first capacitor C01and the second plates C2′ of the plurality of storage capacitors C is the second adapter portion. The sixth connection portion321′ is connected, through vias, to the gate T3-gof the third transistor T3, and the second electrode region T3-dof the active layer of the third transistor T3. The second electrode region T3-dof the third transistor is used as the second electrode region T2-dof the second transistor T2.

The seventh connection portion322′ is connected to the second plates C2′ of the plurality of storage capacitors to form an integrated structure, and the seventh connection portion322′ is connected, through a via, to the second electrode region T5-dof the active layer of the fifth transistor T5. The second electrode region T5-dof the fifth transistor T5is used as the first electrode region T2-sof the second transistor T2. The seventh connection portion322′ is the first adapter portion.

The third conductive layer400′ includes a plurality of fifth conductive portion groups410′ arranged along the column direction, and a sixth conductive portion group420′ located between any two adjacent ones of the fifth conductive portion groups410′.

In some embodiments, the fifth conductive portion group410′ includes a plurality of fifth conductive portions411′ arranged along the row direction, and the fifth conductive portion411′ is connected, through a via, to the second electrode region T1-d,which is exposed outside the first conductive layer200, of the active layer of the driving transistor T1.

The sixth conductive portion group420′ includes a first power supply voltage line VDDL', a compensation switch control signal line COL', a reset voltage line VINIL', and a reset control signal line RSTL' that are arranged along the column direction.

The first power supply voltage line VDDL' is connected to the first power supply voltage end VDD, and is configured to provide the first power supply voltage to the first power supply voltage end VDD. The first power supply voltage line VDDL' is connected, through a via, to the first electrode region T3-sof the active layer of the third transistor T3, and the first power supply voltage line VDDL' is connected to the first plate C11of the first capacitor C01through a via.

The compensation switch control signal line COL' is connected to the compensation switch control signal end Com, and is configured to provide the compensation switch control signal to the compensation switch control signal end Com. The compensation switch control signal and the light-emitting control signal are the same signal, and the compensation switch control signal line COL' is connected to the gate of the second transistor T2through a via. The compensation switch control signal line COL' is used as the light-emitting control signal line EML, and is connected to the gate of the seventh transistor T7through a via.

The reset voltage line VINIL' is connected to the first reset voltage end Vref, and is configured to provide the first reset voltage to the first reset voltage end Vref. The reset voltage line VINIL' is connected, through a via, to the first electrode region T5-s,which is exposed outside the first conductive layer200, of the active layer of the fifth transistor T5. The reset voltage line VINL' may also be connected to the second reset voltage end Vinit, and configured to provide the second reset voltage to the second reset voltage end Vinit. The reset voltage line VINL' may also be connected, through a via, to the first electrode region T6-s,which is exposed outside the first conductive layer200, of the active layer of the sixth transistor T6

The reset control signal line RSTL' is connected to the first reset control signal end Rst1, and is configured to provide the first reset control signal to the first reset control signal end Rst1. The reset control signal line RSTL' is connected to the gate of the fifth transistor T5through a via. The reset control signal line RSTL' may also be connected to the second reset control signal end Rst2, and configured to provide the second reset control signal to the second reset control signal end Rst2. The reset control signal line RSTL' is connected to the gate of the sixth transistor T6through a via.

It should be noted herein that only the pattern structures, in the display area AA, of the second conductive layer300′ and the third conductive layer400′ are shown inFIGS.15and16, and the pattern structures of the two located in the non-display area FA may be improved accordingly with reference toFIGS.8and10, and will not be repeated in detail herein.

As shown inFIGS.12and13, in some embodiments of the present disclosure, the array substrate further includes a fourth conductive layer500located at a side of the third conductive layer400away from the substrate. The fourth conductive layer500includes a plurality of data signal lines DAL and a plurality of seventh conductive portion groups510; and the data signal lines DAL extend along the column direction and are arranged along the row direction. The data signal line DAL is connected, through vias, to the first electrode regions T4-sof the active layers of a plurality of fourth transistors T4. Specifically, the data signal line DAL may be directly connected to the first electrode region T4-sof the active layer of the fourth transistor T4, or may be adapted through the eighth connection portion312. The seventh conductive portion group510includes a plurality of fifth connection portions511arranged along the row direction; the fifth connection portion511is connected to the fifth conductive portion411through a via, so as to subsequently realize the connection between the second electrode region T1-dof the driving transistor T1and the light-emitting device12by means of the fifth connection portion511and the fifth conductive portion411.

In some embodiments of the present disclosure, an insulating layer, such as a first planarization layer and/or a first passivation layer, may be further provided between the third conductive layer400and the fourth conductive layer500.

As shown inFIGS.14and18, in some embodiments of the present disclosure, the array substrate further includes a fifth conductive layer600located at a side of the fourth conductive layer500away from the substrate. The fifth conductive layer600includes a plurality of anodes610arranged in an array, and the anode610is connected to the fifth connection portion511through a via, specifically through a sub-region5110of the fifth connection portion511. Of course, the anode610may also be connected to the fifth conductive portion411through a via. In this embodiment, the anode610of the light-emitting device may be connected to the second electrode region T1-dof the driving transistor T1through the fifth connection portion511and the fifth conductive portion411, or the anode610of the light-emitting device may be directly connected to the second electrode region T1-dof the driving transistor T1through the fifth conductive portion411.

The anode610may be a structure of a variety of shapes. Specifically, it may be a rectangle as shown inFIG.14, or it may be a circle, a hexagon, an octagon, or an irregular shape, etc., the specifics of which are not limited.

The arrangement of the anodes610may be set according to the actual arrangement of sub-pixels. In the present disclosure, the sub-pixels may be arranged in RGB, RGBG, GGRB, etc., where R indicates a red sub-pixel, G indicates a green sub-pixel, and B indicates a blue sub-pixel. Specifically in an embodiment, an RGB arrangement is used, where a red sub-pixel, a green sub-pixel and a blue sub-pixel form a pixel unit, and this method is conducive to achieving a higher resolution.

An orthographic projection of the anode610on the substrate is at least partially overlapped with an orthographic projection, on the substrate, of the first plate C11or the second plate C12of the first capacitor C01. A pixel unit includes three sub-pixels, i.e., including three anodes610. Lengths, in the row direction, of these three anodes610are substantially equal to the length, in the row direction, of the first plate C11or the second plate C12of the first capacitor C01. That is, the length of one pixel unit in the row direction is substantially equal to the length, in the row direction, of the first plate C11or the second plate C12of the first capacitor C01.

In some embodiments, the orthographic projection of the anode610on the substrate is at least partially overlapped with an orthographic projection, on the substrate, of the first plate C1or the second plate C2of the storage capacitor C. Furthermore, a length, in the row direction, of the anode610is substantially equal to a length, in the row direction, of the first plate of the storage capacitor C. An orthographic projection, on the substrate, of a portion of the anodes610is at least partially overlapped with the orthographic projection of the third transistor T3on the substrate.

In some embodiments of the present disclosure, an insulating layer, such as a second planarization layer, is further provided between the fourth conductive layer500and the fifth conductive layer600.

It is noted herein that the pattern structures of the film layers after the third conductive layer400in the present disclosure differ significantly only in the display area AA, and thus the fourth conductive layer500and the fifth conductive layer600only show pattern structures located in the display area AA.

In some embodiments of the present disclosure, the array substrate further includes a pixel defining layer, a light-emitting layer and a cathode. The pixel defining layer may be provided with a plurality of openings, and each of the openings defines a range of a light-emitting device. The anode610is located in the opening, the light-emitting layer is located at a side of the anode610away from the substrate, the cathode is located at a side of the light-emitting layer away from the substrate, and the anode, the light-emitting layer and the cathode form the light-emitting device.

It should be noted herein that when the layouts of the second conductive layer and the third conductive layer of the array substrate are changed, the layouts of the fourth conductive layer and the fifth conductive layer may be adjusted accordingly in order to satisfy the correct connection relationship.

The present disclosure also provides a display panel, and the display panel may further include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, and the like. These components can use existing conventional components, and will not be described in detail herein.

For example, the display panel may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel, and the like. In addition, the display panel may be not only a flat panel, but also a curved panel or even a spherical panel. For example, the display panel may also have a touch control function, i.e., the display panel may be a touch control display panel.

The embodiments of the present disclosure also provide a display device that includes the display panel according to any of the embodiments of the present disclosure. The display device may be a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component having a display function.

It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components presented in this specification. The present disclosure is capable of being provided with other embodiments and being implemented and performed in a variety of ways. The foregoing deformed and modified forms fall within the scope of the present disclosure. It should be understood that the present disclosure, as disclosed and limited in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and/or accompanying drawings. All of these various combinations constitute a plurality of alternative aspects of the present disclosure. The embodiments of this specification illustrate the best ways known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.