Semiconductor package

A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2017-0175275 filed on Dec. 19, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package.

BACKGROUND

In accordance with an increase in sizes of displays for mobile apparatuses, the necessity to increase capacity of batteries has increased. In accordance with the increase in the capacity of the batteries, areas occupied by the batteries in the mobile apparatuses have increased, and it has thus been required to reduce a size of a printed circuit board (PCB). Therefore, an area in which components are mounted has reduced, such that interest in modularization has continuously increased.

Meanwhile, an example of the related art of mounting a plurality of components may include chip-on-board (COB) technology. COB is a method of mounting individual passive elements and a semiconductor package on a printed circuit board using surface mount technology (SMT). However, in such a method, a large mounting area is required in order to maintain a minimum interval between components, electromagnetic interference (EMI) between the components is large, and in particular, a distance between the semiconductor chip and the passive components is great, such that electric noise is increased.

SUMMARY

An aspect of the present disclosure may provide a semiconductor package in which a plurality of passive components may be modularized in advance and used and may be applied to various circuits.

An aspect of the present disclosure may also provide a stack-type passive component module capable of further improving mounting properties of a package and utilizing a backside redistribution layer, and a semiconductor package including the same.

According to an aspect of the present disclosure, a semiconductor package may be provided, in which a plurality of passive components are modularized in advance to improve mounting properties and reduce a size and may be configured to be tunable to be appropriate for various types of packages or may be optimized using a stack structure.

According to an aspect of the present disclosure, a semiconductor package may include: a core member having first and second surfaces opposing each other and having a cavity penetrating through the first and second surfaces; a semiconductor chip disposed in the cavity of the core member and having an active surface having connection pads disposed thereon; a passive component module disposed in the cavity of the core member, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the plurality of passive components are exposed; a connection member disposed on the second surface of the core member and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer; and an encapsulant encapsulating the passive component module and the semiconductor chip disposed in the cavity.

According to another aspect of the present disclosure, a stack-type passive component module may include: first and second passive component modules including, respectively, a plurality of passive components and resin portions encapsulating the plurality of passive components, and having, respectively, first surfaces from which connection terminals of the plurality of passive components are exposed and second surfaces opposing the first surfaces. The second surfaces of the first and second passive component modules may face each other, and the first surfaces of the first and second passive component modules may be provided as upper and lower surfaces, respectively.

According to another aspect of the present disclosure, a semiconductor package may include: a core member having first and second surfaces opposing each other, having a cavity penetrating through the first and second surfaces, and including a wiring structure connecting the first and second surfaces to each other; a semiconductor chip disposed in the cavity of the core member and having an active surface having connection pads disposed thereon; the stack-type passive component module as described above disposed in the cavity of the core member; a connection member disposed on the second surface of the core member and including a first redistribution layer connected to the connection pads of the semiconductor chip and connection terminals disposed on a lower surface of the stack-type passive component module; an encapsulant covering the first surface of the core member and encapsulating the stack-type passive component module and the semiconductor chip; and a second redistribution layer disposed on the encapsulant and connected to the wiring structure of the core member and the connection terminal disposed on an upper surface of the stack-type passive component module.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounting surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure.

In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the mainboard1010, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in oneself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not used in oneself, and is packaged and is used in an electronic device, or the like, in a package state.

The reason why semiconductor packaging is required is that there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the accompanying drawings.

Fan-in Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged, andFIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring toFIGS. 3A to 4, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection member2240may be formed depending on a size of the semiconductor chip2220on the semiconductor chip2220in order to redistribute the connection pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device, andFIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

Referring toFIG. 5, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an outer side of the semiconductor chip2220may be covered with an encapsulant2290, or the like. Alternatively, as shown inFIG. 6, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may further be formed on the connection member2140, and an underbump metal layer2160may further be formed in openings of the passivation layer2150. Solder balls2170may further be formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

In the present manufacturing process, the connection member2140may be formed after the encapsulant2130is formed outside the semiconductor chip2120. In this case, a process for the connection member2140is performed from the via connecting the redistribution layers and the connection pads2122of the semiconductor chip2120to each other and the redistribution layers, and the vias2143may thus have a width that becomes small as they become to the semiconductor chip (see an enlarged region).

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in the case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 9is a schematic plan view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure.FIG. 10is a cross-sectional view taken along line I-I′ of the semiconductor package ofFIG. 9.FIG. 11is an enlarged cross-sectional view illustrating a partial region (region A) of the semiconductor package illustrated inFIG. 9.FIG. 12is a schematic perspective view illustrating a passive component module used in the semiconductor package ofFIG. 9.FIG. 13is a bottom view illustrating the passive component module ofFIG. 12.

Referring to the drawings, a semiconductor package100according to the present exemplary embodiment may include a core member110having a first surface110A and a second surface110B opposing each other and having to third cavities110HA,110HB, and110HC, a semiconductor chip120disposed in the first cavity110HA of the core member110, a plurality of passive components221,222,223,224, and225disposed in the second and third cavities110HB and110HC of the core member110, a connection member140disposed on the second surface110B of the core member110, and an encapsulant130encapsulating the plurality of passive components221,222,223,224, and225and the semiconductor chip120.

The semiconductor chip120may have an active surface on which connection pads120P are disposed. The connection member140may have a redistribution layer142connected to the connection pads120P of the semiconductor chip120.

The plurality of passive components221to225used in the present exemplary embodiment may have different sizes and heights. For example, the plurality of passive components221to225may be capacitors such as multilayer ceramic capacitors (MLCCs) and low inductance chip capacitors (LICCs), inductors, beads, various other kinds of filters, or the like, and the semiconductor package100may include a combination of various passive components221to225depending on a function thereof. For example, several ten passive components may be mounted in one semiconductor package.

The plurality of passive components221to225may have various sizes and heights depending on their performance, capacitances, and the like. In the present exemplary embodiment, the plurality of passive components221to225may be divided into first to fifth passive components221to225in a sequence of a smaller size and height. As an example, the first to third passive components221,222, and223may have relatively small sizes and the fourth and fifth passive components224and225may have relatively large sizes.

In the present exemplary embodiment, the first to third passive components221,222, and223may be provided as first to third passive component modules200A,200B, and200C in which they are grouped depending on regions in which they are mounted. The first to third passive component modules200A,200B, and200C may include a plurality of first to third passive components221,222, and223and resin portions230packaging the plurality of first to third passive components221,222, and223to bind the plurality of first to third passive components221,222, and223.

In the passive components having the relatively small sizes, a delamination phenomenon may occur due to insufficient close adhesion caused by small mounting areas, or a serious alignment defect of the passive components having the relatively small sizes and heights may occur due to a rapid molding flow velocity in a space between the passive components having the relatively large sizes and heights in a molding process of forming the encapsulant130.

In order to prevent these defects, the passive components having the small sizes may be grouped depending on the regions in which they are mounted so that a handling unit becomes large, such that they may be provided as the passive component modules200A,200B, and200C.

In the present exemplary embodiment, the first to third passive component modules200A,200B, and200C may include the plurality of passive components221,222, and223and the resin portions230packaging the plurality of passive components221,222, and223.

The first to third passive component modules200A,200B, and200C may be disposed in different cavities, and may be mounted together with the passive components having the relatively large sizes. In addition, the first and second passive component modules200A and200B may be mounted together with other fourth and fifth passive components224and225in the second cavity110HB, and the third passive component module200C may be mounted together with other fourth passive components224having relatively large sizes in the third cavity110HC.

In the present exemplary embodiment, the first passive component module200A may include the first to third passive components221,222, and223having different sizes and heights. Similarly, the second passive component module200B may also include the second and third passive components222and223having different sizes and heights. To the contrary, the third passive component module200C may include only the third passive components223having the same size and height.

Entire structures of the first to third passive component modules200A,200B, and200C may be determined by shapes of the resin portions230, and may be rectangular structures (seeFIG. 12). However, sizes and shapes of the entire structures of the first to third passive component modules200A,200B, and2000are not limited thereto, but may be variously determined in consideration of sizes of large passive components positioned in the vicinity of the first to third passive component modules200A,200B, and200C or cavities in which the first to third passive component modules200A,200B, and200C are to be mounted.

In each of the first to third passive component modules200A,200B, and200C, the first to third passive components221,222, and223are coupled to each other by the resin portion230, and may thus be more densely disposed as compared to a case in which they are individually mounted. Therefore, an influence of electromagnetic waves increased as a distance between the components is increased may be decreased.

Particularly, in accordance with an increase in a size of displays for mobile apparatuses, the necessity to increase capacity of batteries has increased. Since areas occupied by the batteries in the mobile apparatuses are increased in accordance with the increase in the capacity of the batteries, a size of a printed circuit board (PCB) may be reduced by decreasing mounting areas of the components through the modularization of the passive components described above.

In the present exemplary embodiment, one surfaces of the first to third passive component modules200A,200B, and200C may be provided as mounting surfaces, and connection terminals221T,222T, and223T, of the plurality of passive components221,222, and223may be exposed from the mounting surfaces of the first to third passive component modules200A,200B, and200C (seeFIG. 13). These connection terminals may be connected to the redistribution layer142of the connection member140through vias143.

However, the first passive component module200A used in the present exemplary embodiment may be a module that may be tuned through selective connection of the vias143.

In detail, as illustrated inFIG. 11, in the first passive component module200A, the connection terminals221T and223T of the first and third passive components221and223may be connected to the redistribution layer142of the connection member140through the vias143, while the connection terminals222T of the second passive component222are not connected to the redistribution layer142of the connection member140, such that the second passive component222may not be used as a circuit of the semiconductor package. Alternatively, although not shown, the connection terminals222T of the second passive component222may be connected to the redistribution layer142of the connection member140, such that the second passive component222may also be used as a circuit of the semiconductor package.

As described above, the first passive component module200A according to the present exemplary embodiment may be configured to be used as a portion of a circuit in various packages rather than being designed to be customized to a specific package. To this end, the first passive component module200A may include a combination and an array of several kinds of passive components.

As illustrated inFIG. 11, in the first passive component module200A, only the first and third passive components221and223connected to the redistribution layer142and the vias143may be selectively used, the second passive component222may not be connected to the redistribution layer142, and the second passive component222that is not connected to the redistribution layer142may not be configured as the circuit of the semiconductor package.

As described above, the connection terminals of some of the plurality of passive components may be connected to the redistribution layer through the vias, while the connection terminals of the others of the plurality of passive components may not be connected to the redistribution layer. Through the selective connection of the vias, the first passive component module200A may be tuned so that only some passive components221and223are involved in the circuit of the semiconductor package.

A passivation layer150may be disposed on a lower surface of the connection member140, and underbump metal layers160electrically connected to the redistribution layer142may be disposed in openings of the passivation layer150. Electrical connection structures170may be electrically connected to the redistribution layer142through the underbump metal layers160.

The respective components included in the semiconductor package100according to the present exemplary embodiment will hereinafter be described in more detail.

The core member110may improve rigidity of the semiconductor package100depending on certain materials, and serve to secure uniformity of a thickness of the encapsulant130. As an example, the core member110used in the present exemplary embodiment may have the first to third cavities110HA,110HB, and110HC. The semiconductor chip120may be disposed in the first cavity110HA, and the first to third passive component modules200A,200B, and200C may be disposed together with the plurality of passive components224and225in the second and third cavities110HB and110HC. The semiconductor chip120may be spaced apart from other passive components224and225and the passive component modules200A,200B, and200C by a distance of sidewalls of the core member110. The number and shapes of cavities may be variously modified, if necessary.

A material of the core member110is not particularly limited. For example, an insulating material may be used as a material of the core member110. In this case, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass fabric, for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like, may be used as the insulating material. Alternatively, a PID resin may also be used as the insulating material.

The semiconductor package100according to the present exemplary embodiment may further include a metal layer181, a backside metal layer182, and backside vias183for blocking electromagnetic waves and dissipating heat. The metal layer181may be disposed on inner sidewalls of the second and third cavities110HB and110HC of the core member110, and may be disposed to surround the passive components224and225and the passive component modules200A,200B, and200C. The metal layer may not be formed on sidewalls of the first cavity110HA.

The metal layer181may extend in a plate shape to upper and lower surfaces of the core member110. The backside metal layer182may be formed in a plate shape on the encapsulant130to block an upper portion of the semiconductor package100. The backside vias183may penetrate through the encapsulant130to connect the metal layer181and the backside metal layer182to each other. The metal layer181, the backside metal layer182, and the vias183may include a conductive material such as copper (Cu), or the like, and may be formed by any known plating method, or the like. If necessary, the metal layer181and the backside metal layer182may be connected to a ground of the redistribution layer142of the connection member140to be thus used as a ground. A degassing hole for discharging moisture, gas, or the like, may be formed in the backside metal layer182.

Meanwhile, an EMI blocking structure for the redistribution layer142of the connection member140may also be implemented in the connection member140.

The semiconductor chip120may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. In this case, the integrated circuit may be, for example, a power management IC (PMIC), but is not limited thereto. Meanwhile, the semiconductor chip120may be an integrated circuit in a bare state in which a separate bump or redistribution layer is not formed. The integrated circuit may be formed on the basis of an active wafer. In this case, a base material of a body of the semiconductor chip120may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. The connection pads120P may electrically connect the semiconductor chip120to other components. A material of each of the connection pads120P may be a conductive material such as aluminum (Al), or the like. A passivation layer (not shown) exposing the connection pads120P may be formed on the body, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. An insulating layer, and the like, may further be disposed in other required positions.

The encapsulant130may encapsulate at least portions of the core member110, the semiconductor chip120, the plurality of passive components224and225, and the passive component modules200A,200B, and200C. In addition, the encapsulant130may fill at least portions of the first to third cavities110HA,110HB, and110HC. The encapsulant130may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as ABF, FR-4, BT, or the like. In addition, any known molding material such as an epoxy molding compound (EMC), or the like, may be used, and a photoimagable encapsulant (PIE) may be used, if necessary.

Alternatively, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated in an inorganic filler and/or a core material such as a glass fabric may also be used as the insulating material.

The connection pads120P of the semiconductor chip120may be extended and redistributed using the redistribution layer142of the connection member140, and the semiconductor chip120and the passive components221to225may be electrically connected to each other by the redistribution layer142. Several tens to several hundreds of connection pads120P of the semiconductor chip120having various functions may be redistributed by the connection member140, and may be physically or electrically externally connected through the electrical connection structures170depending on the functions. The connection member140may include insulating layers141, redistribution layers142disposed on the insulating layers141, and vias143penetrating through the insulating layers141and connecting the redistribution layers142to each other. The connection member140may be formed of a single layer, or may be formed of layers of which the number is greater than that illustrated in the drawings.

A material of each of the insulating layers141may be an insulating material. In this case, a photosensitive insulating material such as a PID resin may also be used as the insulating material. That is, the insulating layer141may be a photosensitive insulating layer. When the insulating layer141has photosensitive properties, the insulating layer141may be formed to have a smaller thickness, and a fine pitch of the via143may be achieved more easily. The insulating layer141may be formed of a photosensitive insulating resin including an insulating resin and an inorganic filler. When the insulating layers141are multiple layers, materials of the insulating layers141may be the same as each other, and may also be different from each other, if necessary. When the insulating layers141are the multiple layers, the insulating layers141may be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent.

The redistribution layers142may serve to substantially redistribute the connection pads120P. Each of the redistribution layers142may include, for example, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers142may perform various functions depending on designs of corresponding layers. For example, the redistribution layers142may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers142may include via pads, connection terminal pads, and the like.

The vias143may electrically connect the redistribution layers142, the connection pads120P, the connection terminals of the passive components221to225, and the like, formed on different layers to each other, resulting in reconfiguration of an electrical path in the semiconductor package100. The vias143may include, for example, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias143may be completely filled with the conductive material, and may have various shapes such as a tapered shape and a cylindrical shape.

The connection member140may include a heat dissipation structure (not illustrated) disposed on the active surface of the semiconductor chip120. The heat dissipation structure may have a stack via form, but is not limited thereto. The heat dissipation structure may be connected to the mainboard through the electrical connection structures170to effective dissipate heat generated from the semiconductor chip120.

The passivation layer150may protect the connection member140from external physical or chemical damage. The passivation layer150may have the openings exposing at least portions of the redistribution layer142of the connection member140. The number of openings formed in the passivation layer150may be several tens to several thousands. The passivation layer150may include an insulating resin and an inorganic filler, but may not include a glass fabric. For example, the passivation layer150may be formed of ABF or a solder resist, but is not limited thereto.

The underbump metal layers160may be improve connection reliability of the electronic connection structures170, resulting in improvement of board level reliability of the semiconductor package100. The underbump metal layers160may be connected to the redistribution layer142of the connection member140exposed through the openings of the passivation layer150. The underbump metal layers160may be formed in the openings of the passivation layer150by any known metallization method using any known conductive material such as a metal, but are not limited thereto.

The electrical connection structures170may be additionally configured to physically or electrically externally connect the semiconductor package100. For example, the semiconductor device100may be mounted on the mainboard of the electronic device through the electrical connection structures170. Each of the electrical connection structures170may be formed of a conductive material, for example, a low melting point metal such as an Sn—Al—Cu alloy. Each of the electrical connection structures170may be a land, a ball, a pin, or the like. The electrical connection structures170may be formed as a multilayer or single layer structure. When the electrical connection structures170are formed as a multilayer structure, the electrical connection structures170may include a copper (Cu) pillar and a ball formed of a low melting point metal. When the electrical connection structures170are formed as a single layer structure, the electrical connection structures170may include a tin-silver solder or copper (Cu). However, the electrical connection structures170are not limited thereto. The number, an interval, a disposition form, and the like, of electrical connection structures170are not particularly limited. For example, the electrical connection structures170may be provided in an amount of several tens to several thousands according to the number of connection pads120P, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

At least some of the electrical connection structures170may be disposed in a fan-out region. Here, the fan-out region refers to a region except for the region in which the semiconductor chip120is disposed. A fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness.

A method of manufacturing the passive component module used in the semiconductor package according to the present exemplary embodiment will hereinafter be described.

FIGS. 14A through 14Dare cross-sectional views for describing main processes of a method of manufacturing the passive component module used in the semiconductor package illustrated inFIG. 9. The method of manufacturing the passive component module according to the present exemplary embodiment may be understood as a method of manufacturing the first passive component module200A illustrated inFIGS. 12 and 13.

First, referring toFIG. 14A, the first to third passive components221,222, and223may be aligned on a carrier substrate200.

The present process may be a process of manufacturing two modules as an example, and the first to third passive components221,222, and223may be more densely arranged as compared to a surface mounting technology (SMT) process, and mounting areas of the passive components may thus be significantly decreased as compared to a case of individually mounting the same combination of passive components on a printed circuit board. The carrier substrate200may include a support layer201and a metal foil202formed on at least one surface of the support layer201. The support layer201may be formed of prepreg, and the metal foil202may be a plurality of coil foil portions. However, the support layer201and the metal foil202are not limited thereto.

Then, referring toFIGS. 14B and 14C, a process of forming the resin portion230to surround the first to third passive components221,222, and223may be performed.

In the present process, the resin portion230may be formed by disposing a first resin body230a, which is a sidewall structure surrounding array regions of the respective passive components, and disposing a second resin body230bon the first resin body230ain order to encapsulate the array regions of the respective passive components, as illustrated inFIG. 14B.

The first resin body230a, which is the sidewall structure, may be provided in advance on the carrier substrate200to suppress the first to third passive components221,222, and223from being separated in the process of forming the resin portion. For example, the first resin body230amay be an insulating resin body such as prepreg in which the array regions of the passive components are punched. For example, the second resin body230bmay be formed using prepreg, ABF, or a PID resin.

An encapsulating process using the second resin body230bmay be performed by a lamination process, as illustrated inFIG. 14B. At least one of the first and second resin bodies230aand230bmay be formed of the same material as that of the encapsulant130, if necessary.

Then, referring toFIG. 14D, the carrier substrate200may be removed, connection electrode layers235may be formed on exposed surfaces of connection terminals, and the passive component module may then be cut in an individual module unit.

The support layer201of the carrier substrate200may be removed using the metal foil202. The remaining metal foil202may be removed by etching. After the carrier substrate200is removed, the connection electrode layers235may be formed on the exposed surfaces of the connection terminals in order to facilitate a process of connecting the passive component module and the redistribution layer to each other. For example, the connection electrode layers235may be formed of Sn, Cu, and alloys thereof, and may be formed by a sputtering process using a mask.

FIG. 15is a schematic cross-sectional view illustrating a stack-type passive component module according to an exemplary embodiment in the present disclosure.

Referring toFIG. 15, a stack-type passive component module200′ according to the present exemplary embodiment may include first and second passive component modules200′A and200′B including, respectively, a plurality of passive components221,222, and223and resin portions230aand230bencapsulating the plurality of passive components221,222, and223. The first and second passive component modules200′A and200′B may have, respectively, first surfaces200′A-1and200′B-1from which connection terminals221T,222T, and223T of the plurality of passive components221,222, and223are exposed and second surfaces200′A-2and200′B-2opposing the first surfaces200′A-1and200′B-1.

In the stack-type passive component module200′ according to the present exemplary embodiment, the second surfaces200′A-2and200′B-2of the first and second passive component modules200′A and200′B may be bonded to each other to face each other, such that the first surfaces200′A-1and200′B-1of the first and second passive component modules200′A and200′B may be provided as upper and lower surfaces, respectively.

As illustrated inFIG. 15, the second surfaces200′A-2and200′B-2of the first and second passive component modules200′A and200′B may be bonded to each other by an adhesion layer240such as a die attach film (DAF). The first and second passive component modules200′A and200′B used in the present exemplary embodiment may further include connection electrode layers (not illustrated, but similar to the connection electrode layers235shown inFIG. 14D) disposed on connection terminals221T,222T, and223T exposed from the first surfaces200′A-1and200′B-1and protruding from the first surfaces200′A-1and200′B-1, as in the example described with reference toFIG. 14D.

FIG. 16is a cross-sectional view illustrating a semiconductor package in which the stack-type passive component module illustrated inFIG. 15is used. It may be understood that a semiconductor package illustrated inFIG. 16is similar to the semiconductor package illustrated inFIGS. 9 and 10although a semiconductor chip is not illustrated inFIG. 16and a cross section of a cavity110H (for example, a second cavity110HB) in which passive components are mounted is illustrated.

Referring toFIG. 16, it may be understood that a semiconductor package100A according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 9 and 10except that the stack-type passive component module200′, a core member110having a wiring structure115, and a second redistribution layer152and vias153are formed. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package100illustrated inFIGS. 9 and 10unless explicitly described to the contrary.

The core member110may include a dielectric layer111and the wiring structure115connecting upper and lower surfaces of the dielectric layer110to each other. The wiring structure115may include first and second wiring layers112aand112bdisposed on opposite surfaces of the dielectric layer111, respectively, and through-vias113penetrating through the dielectric layer111and connecting the first and second wiring layers112aand112bto each other. The second wiring layer112bof the core member110may be connected to a first redistribution layer142of a connection member140disposed on a second surface110B of the core member110. The semiconductor package100A according to the present exemplary embodiment may be utilized as a package for a package-on-package (PoP).

In the stack-type passive component module200′, the first surface200′B-1of the second passive component module200′B may be provided as a mounting surface in contact with the connection member140. The first redistribution layer142of the connection member140may be connected to some of the connection terminals221T,222T, and223T of the second passive component module200′B of the stack-type passive component module200′ together with connection pads (not illustrated) of a semiconductor chip through vias143, and the first redistribution layer142of the connection member140may not be connected to one of the connection terminals221T,222T, and223T of the second passive component module200′B. Alternatively, the first redistribution layer142of the connection member140may be connected to all of the connection terminals221T,222T, and223T of the second passive component module200′B of the stack-type passive component module200′ together with connection pads (not illustrated) of a semiconductor chip through vias143.

An encapsulant130may cover a first surface110A of the core member110, and encapsulate the stack-type passive component module200′ and the semiconductor chip (not illustrated). A second redistribution layer152may be disposed on a surface of the encapsulant130, and may be connected to some of the connection terminals221T,222T, and223T of the second passive component module200′A through vias153, and the second redistribution layer152may not be connected to one of the connection terminals221T,222T, and223T of the second passive component module200′A. Alternatively, the second redistribution layer152may be connected to all of the connection terminals221T,222T, and223T of the first passive component module200′A of the stack-type passive component module200′. As in the present exemplary embodiment, other passive components224′ may be connected to both of the first redistribution layer142and the second redistribution layer152, if necessary.

First and second passivation layers171and172may be configured to protect the connection member140and the second redistribution layer152, respectively, from external physical or chemical damage, or the like. The second passivation layer172may have openings exposing at least portions of the first wiring layer112a.

A material of each of the first and second passivation layers171and172is not particularly limited. For example, a solder resist may be used as the material of each of the first and second passivation layers171and172. In some exemplary embodiments, a material (for example, a PID resin, an ABF, or the like) that is the same as or similar to the insulating material used as the material of the core member110and/or the connection member140may be used as the material of each of the passivation layers171and172.

As set forth above, according to the exemplary embodiments in the present disclosure, the plurality of passive components may be modularized in advance and be tuned through the selective connection of the vias to be thus used as a module appropriate for various package circuits. Meanwhile, the stack-type passive component module configured so that the connection terminals are exposed from opposite surfaces opposing each other may be provided to further improve mounting properties and be usefully utilized for a package including a backside redistribution layer.