Techniques to operate a time division multiplexing(TDM) media access control (MAC)

Techniques to operate a time division multiplexing (TDM) media access control (MAC) module include examples of facilitating use of shared resources allocated to ports of a network interface based on a time slot mechanism. The shared resources allocated to process packet data received or sent through the ports of the network interface.

TECHNICAL FIELD

Descriptions are generally related to configuring resources used by network ports coupled with a network interface having a MAC.

BACKGROUND

Bandwidth is the maximum rate of data transfer across a given link or path. For example, in a data or communication network scenario, through the use of link aggregation, a number of connections between a source and destination may be aggregated into a single interface so that the bandwidth of a link or path between the source and destination is the sum of the maximum rate of transfer across all of the connections.

Local Area Networks (LANs) and Metropolitan Area Networks (MANs) may use the Institute of Electrical and Electronics Engineers (IEEE) 802.3 (Ethernet) protocol and frame format for data communication. The Ethernet protocol uses a common media access control (MAC) sublayer of a data link layer in the Open Systems Interconnection model (OSI model). The OSI model is a conceptual model that partitions a communication system into abstraction layers. The MAC sublayer is responsible for transferring data to and from a physical layer and encapsulates frames received from upper layers (for example, frames received from a network layer in the OSI reference model) into frames appropriate for the transmission medium. Speed specific media independent interfaces (MIIs) provide an interface to the physical layer that encodes frames for transmission and decodes received frames with the modulation specified for the speed of operation, transmission medium and supported link length.

The interface between the MAC sublayer and the physical layer includes signals for framing and collision detection, and transmit and receive serial bit streams. A basic MAC frame has a minimum length of 64 bytes and a maximum length of 1518 bytes. The basic MAC frame includes destination address, source address, length/type field, MAC client data, pad (if required), and frame check sequence (FCS).

A maximum length of a normal, non-jumbo Ethernet frame is 1518 bytes which includes 14 bytes of Ethernet header, 1500 bytes of data and 4 bytes of FCS. The FCS is a cyclic redundancy check (CRC) over all fields in the Ethernet frame (except the FCS). Between each transmitted frame there are two bytes of interframe gap and 8 bytes of preamble. Thus, each maximum length Ethernet frame consumes 1538 bytes of the bandwidth.

A lane is a bundle of signals that constitutes a logical subset of a point-to-point interconnect. A copper based Gigabit (Gb) Ethernet Network (1000 BaseT) link uses four lanes over all four cable pairs for simultaneous transmission in both directions. The theoretical maximum bandwidth on a Gigabit Ethernet network is defined by a node being able to send 1 Gb (125 Mega Bytes (MB)) each second. Bandwidth of the transmission medium may be increased by transmitting serial data over multiple lanes.

Ethernet protocols are being designed to handle substantially larger bandwidths than 1 Gb per second. For example, bandwidths for transmission mediums of 50 gigabits (50 G), 100 G, 200 G or 400 G are described by IEEE standard, Carrier sense Multiple access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Published in August 2018 (hereinafter “the IEEE 802.3-2018 specification”).

Data is transmitted and received over the transmission medium in serial format by the physical layer. The data is received (e.g., through a network interface port coupled with the transmission medium) and transmitted by the MAC sublayer in parallel format, e.g., via a data bus. As the bandwidth of the transmission medium is increased, additional buffer memory or larger receive queues are needed to handle this discrepancy. If additional buffer memory or larger capacity receive queues are not desired, the MAC sublayer must process the received data faster which requires increasing a system clock frequency for processing elements supporting the MAC sublayer or increase the amount of data processed per clock cycle by increasing the width of the data bus. For example, the processing elements supporting the MAC sublayer may operate at 800 megahertz (MHz). For this example, the MAC sublayer could scale to process data at a rate of 1.6 terabit per second (Tb/sec) if the width of the data bus is 256 bytes. A goal for a MAC sublayer of a network interface that uses as minimal amount of receive queue capacity, in some examples, is being capable of processing data received at a rate at least equal to the transmission medium bandwidth via which a network interface port couples with the transmission medium.

DETAILED DESCRIPTION

According to some examples, one or more network interface ports (e.g., ports for a NIC) coupled with a transmission medium may be designed to couple to transmission mediums having transmission medium bandwidths scaling from 1 Gb/s to 200 Gb/s. Typically, resources utilized by a MAC sublayer when processing data received via a network interface port are allocated on a per port basis. For example, registers, delay elements (e.g., flip-flops or latches), static random access memory (SRAM), etc., used to process data through a data bus may be allocated on a per port basis. As the upper ends of transmission medium bandwidths continue to scale to higher transmission medium bandwidths, a greater amount of these types of resources are needed to support each of the ports that are capable of scaling to the upper end of these transmission medium bandwidths when resources are allocated on a per port basis. In some cases, a MAC sublayer supporting multiple ports for a range of transmission medium bandwidths may become too large or costly to deploy in a low-to-high bandwidth scaling environment. Also, if some ports are coupled to a lower transmission medium bandwidth (e.g., 1 Gb/s), yet allocated resources based on processing data for a much higher transmission medium bandwidth (e.g., 200 Gb/s), then a substantial amount of those port allocated resources may not be utilized and/or are utilized inefficiently. It is with respect to these challenges that the examples described herein are needed.

FIG. 1illustrates an example NIC100. In some examples, NIC100may represent a type of network interface and as shown inFIG. 1, NIC100may include Ethernet port logic and includes a media access control (MAC) module102, a reconciliation sublayer (RS) module104and a physical layer module106. The physical layer module106includes a physical medium dependent (PMD) module114, a physical medium attachment (PMA) module112, an auto-negotiation (AN) module116, a forward error correction (FEC) module110, a physical coding sublayer (PCS) module108and one or more port(s)121. For these examples, each port from among port(s)121may separately include a transmitter port120including transmitter circuitry and a receive port122including receive circuitry. In some examples, one or more of the sublayer modules may be incorporated in, or otherwise form a portion of, another sublayer module. For example, part or all of the PMD module114, PMA module112, AN module116, and/or FEC module110may be incorporated in PCS module108.

According to some examples, each port from among port(s)121may be configured to operate as Ethernet ports coupled with one full-duplex communication lane from among respective one or more lane(s)130. The respective one or more lane(s)130may include a twisted pair conductor, an optical fiber, or an electric backplane connection. For full-duplex operation, the respective one or more lane(s)130may separately include two twisted pair conductors, one pair for transmitting data and the other pair for receiving data from one or more link partner(s)118.

In some examples, MAC module102is configured to implement aspects of the MAC layer operations and RS module104may be configured to implement reconciliation sublayer operations. For these examples, a link initialization of a lane from among lane(s)130communicatively coupling NIC100through a port among port(s)121to a link partner among link partner(s)118may occur. During the link initialization, AN module116may perform auto-negotiation of link speed and capabilities for the lane coupled to NIC100through the port.

According to some examples, PMD module114may located just above a medium dependent interface (MDI) (not shown). For these examples, PMD module114is responsible for interfacing to a transmission medium. Also, PMA module112may include functions for transmission, reception, collision detection, clock recovery and skew alignment. PMD module114and PMA module112may also be configured to transmit and receive serial binary data over a lane from among lane(s)130through a port from among port(s)121and to convert between serial binary data and parallel binary data. For example, PMD module114and PMA module112may receive serial binary data and convert the serial binary data to 32-bit parallel binary data. The serial to parallel binary data conversion may be performed by a serializer/de-serializer (SERDES) using, for example, a shift register. Serial binary data may be transmitted and received over the lane or multiple lanes at different frequencies.

In some examples, AN module116may be configured to auto-negotiate line transmission speed, mode of operation, and other communication parameters with a link partner from among link partner(s)118over a lane from among lane(s)130. AN module116may be a state machine or other logic capable of implementing an auto-negotiation protocol. For example, AN module116may implement the auto-negotiation protocol specified by the IEEE 802.3 specification.

According to some examples, FEC module110may decode data passed from the PMD module114and PMA module112to the PCS module108and encode data passed from the PCS module108to the PMD module114and PMA module112. The forward error correction code may improve the reliability of data transmission at higher line speeds.

In some examples, PCS module108is configured to decode parallel data received from PMD module114and PMA module112into decoded parallel data that may be processed by MAC module102, and to encode parallel data received from MAC module102into encoded parallel data that may be transmitted by PMD module114and PMA module112. Data transmitted over lane(s)130may be encoded, for example, to improve communication efficiency. For example, encoding the parallel data may add timing or synchronization symbols, align the data, add state transitions to the encoded data to improve clock recovery, or otherwise prepare the encoded data for serial transmission. PCS module108may be capable of encoding or decoding the parallel data using multiple line codes. For example, PCS module108may be capable of using a 64-bit/66-bit line code in which 64-bit blocks of data are encoded into 66-bit blocks of encoded data.

According to some examples, MAC module102may be configured to transfer data to and from physical layer module106. RS module104may be configured to serve as a mapping function that reconciles signals at a media independent interface (MII). For example, according to MAC-physical signaling sublayer (PLS) service definitions.

In some examples, for a transmit direction, MAC module102receives data to be transmitted in a MAC frame over lane(s)130, and generates the MAC frame that includes inter-packet gap (IPG), preamble, start of frame delimiter (SFD), padding, and cyclic redundancy check (CRC) bits in addition to the received data before passing the MAC frame to physical layer module106over a data bus. Physical layer module106encodes the MAC frame as required for reliable serial transmission over lane(s)130to link partner(s)118.

According to some examples, in the receive direction, MAC module102receives MAC frames over a data bus from physical layer module106. MAC module102accepts MAC frames from physical layer module106, performs Ethernet frame detection and validation, CRC validation, updates statistics counters, strips out the CRC, preamble, and SFD, and forwards the rest of the MAC frame that includes headers for use by other, higher level protocols to a next layer (for example, the Internet protocol (IP) layer).

In some examples, as described in more detail below, logic and/or features of MAC module102may separately share resources to process packet data received or transmitted through individual port(s)121arranged to couple with, for example, a transmission medium having a 1 G, 50 G, a 100 G or a 200 G transmission medium bandwidth included in one or more lanes from among lane(s)130. The resources may be shared based on a time-division multiplexing (TDM) architecture for MAC module102. The shared resources may include TDM storage resources that may be arranged to facilitate packet processing by MAC module102. TDM storage resources may include, but are not limited to, delay elements (e.g., flip-flops or latches), static random access memory (SRAM) or other types of memory structures to at least temporarily store data received by MAC module102via a data bus. The data associated with data packets received from or transmitted through port(s)121.

According to some examples, the TDM architecture for MAC module102may include sharing resources on a per port basis based on a time slot mechanism. The time slot mechanism, for example, may allow for a more efficient way to share resources such as TDM storage resources in operating scenarios where NIC100may couple with a wide range of transmission medium bandwidths. Also, as described more below, logic and/or features of MAC module102such as TDM resource logic103may facilitate activation of TDM storage resources for port(s)121in order for these ports to use shared resources such as TDM storage resources. Also, as described more below, once TDM resource logic103has activated the TDM storage resources for port(s)121, logic and/or features of MAC module102such as next state logic101may use the activated TDM storage resources to facilitate packet processing of packets received from or to be transmitted through port(s)121.

In some examples, registers105may represent programmable data structures that may be used to adjust various TDM parameters associated with using or implementing a TDM architecture. Once programmed, registers105may indicate TDM allocation information. For example, registers105may be programmed to set or establish a time period for a repeating sequence of time slots, a size of individual time slots (e.g., several nanoseconds or microseconds) included in the time period, which ports are assigned to respective time slots, or identify TDM storage resources included in the shared resources for use during the respective time slots. Examples are not limited to these examples of how registers105may be programmed or set. As shown inFIG. 1, registers105may be part of MAC module102or may be located on NIC100, separate from MAC module102but still accessible to logic and/or features of MAC module102.

In some examples, logic and/or features of MAC module102such as TDM resource logic103or next state logic101may be implemented by logic encoded in one or more tangible media (e.g., embedded logic provided in an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA)), digital signal processor (DCP) instructions, software (potentially inclusive or object code and source code) to be executed by a processor/processor circuit, or other similar machine, etc.), which may be inclusive of non-transitory computer-readable media/medium or machine-readable medium/medium. In some of these instances, memory elements located at or accessible to NIC100(not shown) may store data used for operations implemented by the logic and/or features of MAC module102such as TDM resource logic103or next state logic101. This includes the memory elements being able to store software, logic, code or processor instructions that are executed to carry out functions or activities described in this disclosure for the logic and/or features of MAC module102.

According to some examples, the term “packet” or “data packet”, as used herein, may refer to a unit of data that may be routed between a source (e.g., link partner(s)118) and a destination (e.g., a computing platform coupled with NIC100) on a packet switched network. For these examples, a packet includes a source network address and a destination network address. These network addresses can by IP addresses in a transmission control protocol (TCP)/IP messaging protocol. The term “data”, as used herein, may refer to any type of binary, numeric, voice, video, textual, or script data, or any type of source or object code, or any other suitable information in any appropriate format that may be communicated from one point to another in a system, electronic devices and/or networks. Additionally, messages, requests, responses, and queries are forms of network traffic, and may include packets, frames, signals, data, etc.

According to some examples, NIC100may be hosted by or coupled with a server. The server may be a server for a base transceiver station (BTS), a web server, a network server, an Internet server, a work station. In other examples, NIC100may be hosted by or coupled with a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, or combination thereof Also, although item100, in shown inFIG. 1as a NIC, a network interface may be another type of circuitry or device having physical layer ports arranged to couple with, for example, a transmission medium having a 1 G, 50 G, a 100 G or a 200 G transmission medium bandwidth included in one or more lanes from among lane(s)130. For example, it could be circuitry of any device that has an Ethernet interface such as a processor, Ethernet switch ASIC, FPGA, graphic processing unit (GPU), general purpose GPU (GPGPU), etc.

FIG. 2illustrates an example system200. According to some examples, system200illustrates an example of how functional elements of MAC module102implement a TDM architecture for sharing allocated resources on a per port basis. For these examples, as shown inFIG. 2, system200includes elements of NIC100such as port121-1to121-n(where “n” represents any whole, positive integer >3), next state logic101, TDM resource logic103and registers105.FIG. 2also depicts a TDM multiplexor (MUX)202, a data bus205, packet processing circuitry212and TDM storage resources222. These additional elements, as described more below, illustrate examples of additional logic and/or features of MAC module102associated with implementing a TDM architecture.

According to some examples, registers105may be set or programmed to establish how TDM MUX202is to switch between ports121-1to121-nbased on a time slot mechanism. For example, over a repeating time period, port121-1may be given a first portion of time slots of the repeating time period, port121-2may be given a second portion of time slots, port121-2may be given a third portion of time slots, etc. Each port may then have access to data bus205and to shared TDM storage resources222during their respectively assigned portions of the repeating time period. TDM storage resources222may include, but are not limited to, delay elements (e.g., flip-flops or latches), SRAM, a combination of delay elements and SRAM or other types of memory structures to at least temporarily store data received by MAC module102and to be processed by packet processing circuitry212. Also, packet processing circuitry212may process packet data for packets received through each port during their respectively assigned portions of the repeating time period and routed through data bus205.

In some examples, data bus205may have a width that is based on attempting to scale to a data processing rate to match a bandwidth of a transmission medium routed through port(s)121without needed to increase an operating bandwidth of packet processing circuitry212. For example, if a transmission medium routed through port(s)121had a bandwidth of 200 Gb/sec and packet processing circuitry212operated at 800 MHz, then a width of 32 bytes for data bus205would be needed. In another example, if packet processing circuitry212operated at 800 MHz and the transmission medium had a bandwidth of 1.6 Tb/sec, then a width of 256 bytes for data bus205would be needed. According to some examples, data bus205may be partitioned to be capable of processing multiple data packets or multiple chunks of one or more data packets per clock cycle. For example, a width of 256 bytes may be partitioned in four segments separately capable of sending either four packets of 64 bytes or four chunks of a packet that is larger than 256 bytes.

According to some examples, TDM resource logic103may implement a process to separately place into service a look ahead pattern to load to TDM storage resources222for each port from among ports121-1to121-n.As described more below, placing a per port look ahead pattern in service may include learning and verifying/validating a look ahead pattern while implementing a TDM architecture. Also, as described more below, next state logic101may use verified/valid look ahead patterns that are loaded to TDM storage resources222to process packet data received or sent through ports121-1to121-n.

In some examples, packet processing circuitry212may include various commercially available processors, including without limitation an AMD® Epyc®, Ryzen®, Athlon®, Duron® and Opteron® processors; ARM® application, embedded and secure processors; IBM® and Motorola® DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; Intel® Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon® or Xeon Phi® processors; and similar processors. According to some examples, packet processing circuitry212may also include an application specific integrated circuit (ASIC) and at least some elements, logic and/or features of packet processing circuitry212may be implemented as hardware elements of an ASIC. According to some examples, packet processing circuitry212may also include an FPGA and at least some elements, logic and/or features of packet processing circuitry212may be implemented as hardware elements of the FPGA.

FIG. 3illustrates example TDM allocations300. In some examples, as shown inFIG. 3, TDM allocations300include allocations310,320,330and340. For these examples, allocations300provide examples of how time slots may be allocated to one or more ports from among ports121-1to121-n.As shown inFIG. 3, a time period may be partitioned into time slots T1to Tm, where “m” is any whole, positive integer >7. Also, a height of each time slot may be representative of a data bus (DB) width. For simplicity purposes, individual time slots may be of an equal width or portion of the time period and the DB width may be a same DB width for the allocations shown inFIG. 3. In other examples, individual time slots and/or DB widths may be of various different dimensions to reflect possible differences in ports assigned to respective time slots and/or to reflect data stream or data packet characteristics of data routed through these ports.

According to some examples, allocation310shows an example of allocating all time slots to port121-1. For these example, port121-1may be coupled to a transmission medium having a data bandwidth of 200 Gb/sec and thus is identified as a 200 G port. Allocation310may indicate an example of when only a single port is active or coupled with a transmission medium.

In some examples, allocation320shows an example of allocating time slots between ports121-1and port121-2. For these examples, these ports may couple to separate transmission mediums have data bandwidths of 100 Gb/sec and thus are identified as 100 G ports. As shown inFIG. 3, ports121-1and121-2are separately allocated ½ of the time slots on an alternating basis. The alternating basis may minimize packet processing latencies for processing packets routed through these ports.

According to some examples, allocation330shows an example of allocating time slots between ports121-1,121-2,121-3and121-n.For these examples, these ports may couple to separate transmission mediums have data bandwidths of 50 Gb/sec and thus are identified as 50 G ports. As shown inFIG. 3, ports121-1,121-2,121-3and121-nare separately allocated ¼ of the time slots on an alternating base.

In some examples, allocation340shows an example of allocating time slots between ports121-1,121-2and121-3. For these examples, port121-1may be a 100 G port and ports121-2and121-3may be 50 G ports. As shown inFIG. 3, port121-1may be allocated ½ of the time slots. Meanwhile, ports121-2and121-3are separately allocated ¼ of the time slots. Port121-1may have alternating time slots from among all time slots. Ports121-2and121-3may have alternating time slots from among the ½ of time slots not allocated to port121-1.

FIG. 4illustrates an example process400. In some examples, process400may depict how logic and/or features of a MAC for a NIC may facilitate use of TDM storage resources. The TDM storage resources may be shared by one or more ports of the NIC based on a time slot mechanism that allocates time slots to the one or more ports. For these examples, process400may include use of various elements shown inFIG. 1such as NIC100, MAC module102, TDM resource logic103or registers105. Process400may also include use of various elements shown inFIG. 2such as ports121-1to121-n, TDM MUX202, data bus205, packet processing circuitry212or TDM storage resources222. Examples are not limited to these elements shown inFIG. 1 or 2.

Beginning at process4.1(Obtain TDM Allocation Information), logic and/or features of MAC module102such as TDM resource logic103may obtain TDM allocation information. In some examples, the TDM allocation information may be obtained from registers105. For these examples, the TDM allocation information may indicate a time period for a repeating sequence of time slots, a size (e.g., what portion of the time period) of individual time slots included in the time period and which ports from among ports121-1to121-nare assigned to respective time slots. According to some examples, the TDM allocation information may match allocation330shown inFIG. 3that has ports121-1to121-narranged as 50 G ports.

Moving to process4.2(Learn Pattern for Each Port), logic and/or features of MAC module102such as TDM resource logic103may implement a TDM port sequencer process to learn and verify look ahead patterns or sequences for ports121-1to121-nwhile respective ports have access to shared resources based on the TDM allocation information. For example, a repeating pattern indicating a count of how may chunks of data may be received from a port via data bus205for processing by packet processing circuitry212during allocated time slots before an end of a data packet is reached. The per port TDM port sequencer process to learn and verify a repeating pattern for each port to place verified repeating patterns in service is described more below in a separate process.

Moving to process4.3(Activated TDM Storage Resources with Verified Look Ahead Patterns), logic and/or features of MAC module102such as TDM resource logic103may compile information to indicate activated TDM storage resources with verified/valid look ahead patterns for ports121-1to121-n. The verified/valid look ahead patterns for ports121-2to121-nmay take several repeating TDM cycles to complete. For example, several time periods for allocation300may be completed before at least some ports from among ports121-1to121-nhave verified look ahead patterns to place in service. Ports not having verified look ahead patterns will have inactive TDM storage resources during their respective time slot allocations due to not having look ahead patterns that have been placed in service.

Moving to process4.4(Control Sequencing to Use of TDM Storage), logic and/or features of MAC module102such as TDM resource logic103may provide control sequencing information to load valid look ahead patterns to activated TDM storage resources. As described more below, the control sequencing may enable a verified/valid look ahead pattern to be loaded to TDM storage resources just prior to or as a port's respective time slot allocation arrives.

FIG. 5illustrates an example process500. In some examples, process500may depict how logic and/or features of a MAC for a NIC such as TDM resource logic103may implement a TDM port sequencer process to learn a look ahead pattern for a port while the port has access to shared storage resources based on TDM allocation information. For these examples, process500may include use of various elements shown inFIG. 1such as NIC100, MAC module102, TDM resource logic103or registers105. Process500may also include use of various elements shown inFIG. 2such as ports121-1to121-n, data bus205, packet processing circuitry212or TDM storage resources222. Examples are not limited to these elements shown inFIG. 1 or 2.

Beginning at process5.1(Initialize TDM Storage Resources to the IDLE State), logic and/or features of MAC module102such a TDM resource logic103causes unallocated TDM storage resources from among TDM storage resources222to move from inactive state to an IDLE state for a port from among ports121-1to121-nsuch as port121-1. In some examples, an IDLE state may result from identifying what amount of TDM storage is needed for port121-1, allocating that amount of TDM storage to port121-1and establishing timing for access to the TDM storage for temporarily storing data associated with receiving or sending data through port121-1. The timing, for example, may be based on TDM allocation information obtained by TDM resource logic103as mentioned above for process400. According to some examples, the TDM allocation information may match allocation330shown inFIG. 3that has ports121-1to121-narranged as 50 G ports.

Moving to process5.2(Port is not Active), TDM resource logic103maintains the initialized TDM storage resources in the IDLE state while waiting for port121-1to become active. According to some examples, port121-1remains inactive while ports121-2to121-nutilize their respective allocated timing slots according to allocation330.

Moving to process5.3(TDM Active on Port), port121-1's allocated timing slot has arrived and TDM is now active on port121-1(e.g., according to allocation330). In some examples, TDM resource logic103may cause the allocated TDM storage resources to move from the IDLE state to an active state responsive to arrival of the port121-1's allocated timing slot.

Moving to process5.4(Detect Sequence or Pattern), TDM resource logic103may detect a sequence or pattern associated with receiving or sending data through port121-1in order to learn the sequence or pattern. For example, a count of chunks of data that are sent to packet processing circuitry212before a tail or end of a packet is detected for each packet sent or received through port121-1during its allocated timing slot. A detected sequence or pattern of counts for packets sent or received through port121-1may serve as a look ahead pattern to be loaded to activated TDM resources during each of port121-1's allocated timing slots to facilitate a determination of when a tail or end of a packet is expected. Another type of detected sequence or pattern may include a detected sequence of a repeated slot pattern. For example, 0,2,0,2,0 . . . or 0,1,2,3,0,1,2,3,0 . . .

Moving to process5.5(TDM Inactive on Port), TDM resource logic103may be unable to detect and learn a sequence or pattern for packets received or sent through port121-1. In some examples, due to lack of detection of a sequence or pattern, TDM resource logic103does not place a pattern or sequence in service and may cause the TDM storage resources to move back to an inactive state for port121-1. Causing the TDM storage resources to be inactive may result in the TDM storage resources becoming at least temporarily unallocated for port121-1.

Moving to process5.6(TDM Active on Port), the port121-1's allocated timing slot is occurring and hence TDM is active for port121-1.

Moving to process5.7(Pattern Repeats?), TDM resource logic103may determine whether the learned sequence or pattern repeats to check/verify the learned sequence or pattern. In some examples, TDM resource logic103may check/verify the learned sequence or pattern over multiple allocated time slots for port121-1.

Moving to process5.8(TDM Inactive on Port), TDM resource logic103may be unable to verify the learned sequence or pattern. In some examples, due to lack of verification of a sequence or pattern, TDM resource logic103does not place the learned sequence or pattern in service and may then cause the TDM storage resources to move back to an inactive state for port121-1.

Moving to process5.9(TDM Active on Port), port121-1's allocated timing slot is occurring and hence TDM is active for port121-1.

Moving to process5.10(Look Ahead Pattern is Valid/Verified), TDM resource logic103may verify that the learned sequence or pattern repeats. In some examples, TDM resource logic103indicating that the learned sequence or pattern is valid or verified causes the learned sequence or pattern to be placed in service for port121-1. For these examples, the TDM storage resources for port121-1remain active.

Moving to process5.11(TDM Inactive on Port), following verification/validity of the learned sequence or pattern and the ending of port121-1's allocated timing slot, TDM resource logic103may cause the TDM storage resources to move back to an inactive state for port121-1. According to some examples, the verified/valid learned sequence or pattern may be deemed as a valid look ahead pattern that may be loaded to TDM storage resources222just prior to an allocated timing slot for port121-1. In some examples, if one or more lanes of lane(s)130coupled with port121-1is removed or goes down (e.g., Ethernet cable is removed) this may also cause the TDM to become inactive on port121-1until the one or more lanes are reestablished/reconnected.

According to some examples, TDM resource logic103may place verified look ahead patterns in service for ports121-2to121-nfollowing process500as described for port121-1.

FIG. 6illustrates an example process600. In some examples, process600may depict how logic and/or features of a MAC for a NIC may use a verified/valid look ahead pattern that has been placed in service for loading to TDM storage resources to facilitate processing packet data. For these examples, process600may include use of various elements shown inFIG. 1such as NIC100, MAC module102, next state logic101or TDM resource logic103. Process600may also include use of various elements shown inFIG. 2such as ports121-1to121-n, TDM MUX202, data bus205, packet processing circuitry212or TDM storage resources222. Examples are not limited to these elements shown inFIG. 1 or 2.

Beginning at process6.1(Previous Port), a previous port indicates that an allocated time slot for a previous port has expired or is about to expire. For example, a time slot allocated to port121-1(e.g., according to allocation330) has expired or is about to expire.

Moving to process6.2(Control Sequencing for Current Port), logic and/or features of MAC module102such as TDM resource logic103may cause a control sequencing for a port having a current allocated time slot to be sent to TDM storage resources222. In some examples, the current port may be port121-2and the control sequencing for port121-2may include information to load a verified or valid look ahead pattern to TDM storage resources222.

Moving to process6.3(Load Look Ahead Pattern), the verified/valid look ahead pattern is loaded in to TDM storage resources allocated from TDM storage resources222based on the information included in the control sequencing.

Moving to process6.4(Input Packet Data), input packet data for the current port may be received through the current port.

Moving to process6.5(Current State), a current state of the look ahead pattern is output from TDM storage resources222. In some examples, the current state indicates how much of the look ahead pattern has been completed according to the control sequencing received from TDM resource logic103. For example, the current state may be a counter or sequence of numbers such as 0, 1, 2, 3, 0, 1, 2, 3 . . . for a 4 port TDM or 0, 2, 0, 2 . . . for a 2 port TDM.

Moving to process6.6(Output Packet Data During Current State), logic and/or features of MAC module102such as next state logic101may cause packet data received through port121-2to be output (e.g., via data bus205) for processing by packet processing circuitry212during the current state.

Moving to process6.7(Next State Determination), logic and/or features of MAC module102such as next state logic101may monitor the current state output from TDM storage resources222and determine that when the look ahead pattern has been completed, a next state is determined. In some examples, the next state determination triggers a need to prepare TDM storage resources222for a next port (e.g., according to allocations300). For example, the next port is port212-3.

Moving to process6.8(Ready for Update), logic and/or features of MAC module102such as next state logic101may send a ready for update indication to TDM storage resources222based on a determination that the look ahead pattern loaded for port212-2has been completed and to indicate a need to prepare for loading another look ahead pattern for the next port.

Moving to process6.9(Control Sequencing for Next Port), logic and/or features of MAC module102such as TDM resource logic103may cause a control sequencing for the next port having a next allocated time slot to be sent to TDM storage resources222(e.g., according allocation330).

Moving to process6.10(Next Port), as mentioned above, the next port may be port212-2(e.g., according to allocation330).

Moving to process6.11(Input Packet Data for Next Port), input packet data for port212-2may start to be received. Process600then comes to an end.

FIG. 7illustrates an example block diagram for apparatus700. Although apparatus700shown inFIG. 7has a limited number of elements in a certain topology, it may be appreciated that the apparatus700may include more or less elements in alternate topologies as desired for a given implementation.

According to some examples, apparatus700may be include in a MAC module for a network face and/or may be included in a NIC. Apparatus700may be supported by circuitry720. For these examples, circuitry720may be at an ASIC, FPGA, configurable logic, processor, processor circuit, or CPU. For these examples, the ASIC, FPGA, configurable logic, processor, processor circuit, or CPU may support logic and/or features of a MAC module such as TDM resource logic103of MAC module102to facilitate use of shared resources allocated to ports of a network interface or a NIC based on a time slot mechanism for a TDM architecture. The shared resources allocated to process packet data received or sent through the ports of the network interface or NIC. Circuitry720may be arranged to execute one or more software or firmware implemented modules, components or logic722-a(module, component or logic may be used interchangeably in this context). It is worthy to note that “a” and “b” and “c” and similar designators as used herein are intended to be variables representing any positive integer. Thus, for example, if an implementation sets a value for a=4, then a complete set of software or firmware for modules, components or logic722-amay include logic722-1,722-2,722-3or722-4. The examples presented are not limited in this context and the different variables used throughout may represent the same or different integer values. Also, “logic”, “module” or “component” may also include software/firmware stored in computer-readable media, and although types of logic are shown inFIG. 7as discrete boxes, this does not limit these types of logic to storage in distinct computer-readable media components (e.g., a separate memory, etc.).

According to some examples, as mentioned above, circuitry720may include an ASIC, an FPGA, a configurable logic, a processor, a processor circuit, a CPU, or one or more cores of a CPU. Circuitry720may be generally arranged to execute one or more software components722-a. Circuitry720may be all or at least a part of any of various commercially available processors, including without limitation an AMD® Athlon®, Epyc®, Ryzen®, Duron® and Opteron® processors; ARM® application, embedded and secure processors; IBM® and Motorola® DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; Intel® Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon®, Xeon Phi® and; and similar processors.

According to some examples, apparatus700may include obtain logic722-1. Obtain logic722-1may be executed or supported by circuitry720to obtain TDM allocation information710that indicates a time period for a repeating sequence of time slots separately allocated to ports of a network interface for use of shared resources to process packet data received or sent through the ports. For these examples, TDM allocation information710may be obtained from registers located on or accessible to the network interface.

In some examples, apparatus700may include a detect logic722-2. Detect logic722-2may be executed or supported by circuitry720to cause a detection of separate patterns associated with receiving or sending data through respective ports of the network interface during time slots allocated to the respective ports. For these examples, detect logic722-2may use timing information715to determine the time of the time slots to detect patterns730.

According to some examples, apparatus700may include verify logic722-3. Verify logic722-3may be executed or supported by circuitry720to verify that the separate patterns repeat to validate the separate patterns.

In some examples, apparatus700may include a load logic722-4. Load logic722-4may be executed or supported by circuitry720to cause, for a first port from among the ports, a first validated pattern to be loaded to a TDM storage resource included in the shared resources, the first validated pattern to facilitate processing packet data received or sent through the first port during a first time slot from among the repeating sequence of time slots, the first time slot allocated to the first port for use of the shared resources. For these examples, the first validated pattern to be loaded to the TDM storage resource may be included in validated pattern735.

Various components of apparatus700and a MAC module, network interface or NIC via may include apparatus700may be a part of may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

A logic flow may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, a logic flow may be implemented by computer executable instructions stored on at least one non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. The embodiments are not limited in this context.

FIG. 8illustrates an example logic flow800. Logic flow800may be representative of some or all of the operations executed by one or more logic, features, or devices described herein, such as apparatus700. More particularly, logic flow800may be implemented by at least obtain logic722-1, detect logic722-2, verify logic722-3or load logic722-4.

According to some examples, logic flow800at block802may obtain TDM allocation information that indicates a time period for a repeating sequence of time slots for use of shared resources to process packet data received or sent through ports of a network interface. For these examples, obtain logic722-1may obtain the TDM allocation information.

In some examples, logic flow800at block804may detect separate patterns associated with receiving or sending data through respective ports of the network interface. For these examples, detect logic722-2may detect the separate patterns.

According to some examples, logic flow800at block806may verify that the separate patterns repeat to validate the separate patterns. For these examples, verify logic722-3may verify the separate patterns.

In some examples, logic flow800at block808may load, for a first port from among the ports, a first validated pattern to a TDM storage resource included in the shared resources, the first validated pattern to facilitate processing packet data received or sent through the first port during a first time slot from among the repeating sequence of time slots, the first time slot allocated to the first port for use of the shared resources. For these examples, load logic722-4may load the first validated pattern.

FIG. 9illustrates an example storage medium900. In some examples, storage medium900may be an article of manufacture. Storage medium900may include any non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. Storage medium900may store various types of computer executable instructions, such as instructions to implement logic flow800. Examples of a computer readable or machine readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The examples are not limited in this context.

FIG. 10illustrates and example system1000. In some examples, as shown inFIG. 10, system1000may include a host1002. Host1002may be any computing platform with compute, interconnect, memory, storage, and network resources (not shown). For example, host1002may include one or more processors, interconnects, one or more memory, one or more storage devices, and one or more network interfaces. Host1002may support one or more virtual machines (VMs)1004to1004-n. VMs1004-1to1004-N may be any VM supported by host1002. Also, VM queues1006-1to1006-nmay be associated with respective VMs1004-1to1004-N and may be included in memory resources maintained by host1002.

According to some examples, for a packet transmission, virtual switch1010may detect that a transmit packet and/or descriptor is formed in a VM queue and a virtual switch1010supported by host1002may request the packet header, payload, and/or descriptor be transferred to a NIC1050using a direct memory access (DMA) engine1052located at NIC1050. For these examples, descriptor queues1058may receive the descriptor for the packet to be transmitted. NIC1050may transmit the packet. For example, a packet may have a header that identifies the source of the packet, a destination of the packet, and routing information of the packet. A variety of packet protocols may be used, including, but not limited to Ethernet, FibreChannel, Infiniband, or Omni-Path. Host1002may transfer a packet to be transmitted from a VM queue from among VM queues1006-1to1006-nto NIC1050for transmission without use of an intermediate queue or buffer.

In some examples, a virtual switch1010supported by host1002may monitor properties of the transmitted packet header to determine if those properties are to be used to cause an update to a mapping table1056or add a mapping in mapping table1056. According to some examples, to program a mapping table, a source IP address of a packet may be transmitted from VM1004-1. For these examples, a mapping is created in mapping table1056between that source IP address and VM queue1006-1is assigned for that mapping. A packet received by NIC1050with a destination IP address equal to the value of the source IP address of VM1004-1is placed in mapped VM queue1006-1. Also, for these examples, the source IP address is used to program the mapping, but it is the destination IP address that is an inspected characteristic or property of packets received on NIC1050, to determine where to route these packets. Thereafter, a received packet having a property or properties that match the mapping rule is transferred from NIC1050to VM queue1006-1using DMA engine1052. For example, if VM1004-1requests packet transmission from a source IP address of 2.2.2.2, and if no mapping rule for VM1004-1is in mapping table1056, then virtual switch1010may add a mapping of a received packet with a destination IP address of 2.2.2.2 to VM queue1006-1, which is associated with VM1004-1.

Virtual switch1010may be any software and/or hardware device that provides one or more of: visibility into inter-VM communication; support for Link Aggregation Control Protocol (LACP) to control the bundling of several physical ports together to form a single logical channel; support for standard 802.1Q VLAN model with trunking; multicast snooping; IETF Auto-Attach SPBM and rudimentary required LLDP support; BFD and 802.1ag link monitoring; STP (IEEE 802.1D-1998) and RSTP (IEEE 802.1D-2004); fine-grained QoS control; support for HF SC qdisc; per VM interface traffic policing; network interface bonding with source-MAC load balancing, active backup, and L4 hashing; OpenFlow protocol support (including many extensions for virtualization), IPv6 support; support for multiple tunneling protocols (GRE, VXLAN, STT, and Geneve, with IPsec support); support for remote configuration protocol with C and Python bindings; support for kernel and user-space forwarding engine options; multi-table forwarding pipeline with flow-caching engine; and forwarding layer abstraction to ease porting to new software and hardware platforms. A non-limiting example of virtual switch1010is Open vSwitch (OVS), described at https://www.openvswitch.org/.

An orchestrator, cloud operating system, or hypervisor (not shown) may be used to program virtual switch1010. For example, OpenStack, described at https://www.openstack.org/can be used as a cloud operating system. The orchestrator, cloud operating system, or hypervisor can be executed on or supported by host1002or may be executed on or supported by a different physical computing platform.

According to some examples, for a received packet, NIC1050may use packet mapper1054to route received packets and/or associated descriptors to a VM queue supported by host1002. Descriptor queues1058may be used to store descriptors of received packets. Packet mapper1054may use mapping table1056to determine which characteristics of a received packet to use to map to a VM queue. A VM queue can be a region of memory maintained by host1002that is able to be accessed by a VM. Content maintained or stored in the VM queue may be accessed in first-received-first-retrieved manner or according to any order that a VM requests. For example, a source IP address of 2.2.2.2 specified in a header of a received packet can be associated with VM queue1006-1in mapping table1056. Based on mapping in mapping table1056, NIC1050may use DMA engine1052to copy a packet header, packet payload, and/or descriptor directly to VM queue1006-1, instead of copying the packet to an intermediate queue or buffer.

In some examples, as shown inFIG. 10, NIC1050may also include a transceiver1060, processor(s)1066, a transmit queue1068, a receive queue1070, a memory1072, and a bus interface1074. Transceiver1060may be capable of receiving and transmitting packets in conformance with applicable protocols such as Ethernet as described in the IEEE 802.3 specification, although other protocols may be used. Transceiver1060may receive and transmit packets from and to a network via a network medium or link. Transceiver1060may include PHY circuitry1062and MAC circuitry1064. PHY circuitry1062may include encoding and decoding circuitry (not shown) to encode and decode data packets. MAC circuitry1064can be configured to assemble data to be transmitted into packets, that include destination and source addresses along with network control information and error detection hash values. In some examples, MAC circuitry1064may implement a TDM architecture to allocated shared resources to process packet data to assemble data to be transmitted into packets (e.g., as described above for MAC module102). Processor(s)1066can be any processor, core, graphics processing unit (GPU), or other programmable hardware device that facilitates programming of NIC1050. For example, processor(s)1066may execute packet mapper1054. Memory1072may be any type of volatile or non-volatile memory device and may at least temporarily store instructions used to program one or more elements of NIC1050. In some examples, memory1072may also include programmable registers that may programmed to maintained TDM allocation information associated with MAC circuitry1064implementing a TDM architecture. Transmit queue1068may include data or references to data for transmission by NIC1050. Receive queue1070may include data or references to data that was received by NIC1050. Descriptor queues1058may reference data or packets in transmit queue1068or receive queue1070. In some examples, descriptor queues1058that include transmit and receive queues1068and1070may be maintained in system memory for host1002rather than at NIC1050. A bus interface1074may provide an interface with host1002. For example, bus interface1074can be compatible with PCI, PCI Express, PCI-x, Serial ATA, and/or USB compatible interface (although other interconnection standards may be used).

Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled” or “coupled with”, however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The follow examples pertain to additional examples of technologies disclosed herein.

An example apparatus may include circuity to obtain TDM allocation information. The TDM allocation information may indicate a time period for a repeating sequence of time slots for use of shared resources to process packet data received or sent through ports of a network interface. The circuitry may also cause a detection of separate patterns associated with receiving or sending data through respective ports of the network interface. The circuitry may also verify that the separate patterns repeat to validate the separate patterns. The circuitry may also cause, for a first port from among the ports, a first validated pattern to be loaded to a TDM storage resource included in the shared resources. The first validated pattern may facilitate processing packet data received or sent through the first port during a first time slot from among the repeating sequence of time slots, the first time slot allocated to the first port for use of the shared resources.

The apparatus of example 1, the TDM allocation information may further indicate a size of individual time slots in relation to the time period for the repeating sequence of time slots, which ports from among the ports of the network interface are assigned to the individual time slots, or identify the TDM storage resource included in the shared resources.

The apparatus of example 1, the use of the shared resources to process packet data may include use of the shared resources to process packet data at a MAC module.

The apparatus of example 3, the first validated pattern may be a pattern that indicates a count of chunks of data that are processed at the MAC module for the packet data received or sent through the first port before a tail or end of packet is detected.

The apparatus of example 1, the TDM storage resource may be static random access memory (SRAM), a plurality of latches, or a combination of latches and SRAM.

The apparatus of example 1, the circuitry to may also cause, for a second port from among the ports, a second validated pattern to be loaded to the TDM storage resource. The second validated pattern may facilitate processing packet data received or sent through the second port during a second time slot from among the repeating sequence of time slots. The second time slot may be allocated to the second port for use of the shared resources. The circuitry may also cause, for a third port from among the ports, a third validated pattern to be loaded to the TDM storage resource. The third validated pattern may facilitate processing packet data received or sent through the third port during a third time slot from among the repeating sequence of time slots. The third time slot may be allocated to the third port for use of the shared resources.

The apparatus of example 6 may also include the first port capable of coupling with a first transmission medium having a first data bandwidth and the second and third ports capable of coupling with a second transmission medium having a second data bandwidth. The first data bandwidth may be two times greater than the second data bandwidth. The first port may be allocated a half of a total number of the repeating sequence of time slots. The second and third ports may be separately allocated a fourth of the total number of the repeating sequence of time slots.

The apparatus of example 1, the network interface may be a NIC.

The apparatus of example 1 may also include one or more registers. The circuitry may obtain the TDM allocation information from the one or more registers.

An example method may include obtaining TDM allocation information that indicates a time period for a repeating sequence of time slots for use of shared resources to process packet data received or sent through ports of a network interface. The method may also include detecting separate patterns associated with receiving or sending data through respective ports of the NIC. The method may also include verifying that the separate patterns repeat to validate the separate patterns. The method may also include loading, for a first port from among the ports, a first validated pattern to a TDM storage resource included in the shared resources. The first validated pattern may facilitate processing packet data received or sent through the first port during a first time slot from among the repeating sequence of time slots. The first time slot may be allocated to the first port for use of the shared resources.

The method of example 10, the network interface may be a NIC. The method may include obtaining the TDM allocation information from one or more registers located on the NIC.

The method of example 10, the TDM allocation information may also indicate a size of individual time slots in relation to the time period for the repeating sequence of time slots, which ports from among the ports of the network interface are assigned to the individual time slots, or identify the TDM storage resource included in the shared resources.

The method of example 10, the use of the shared resources to process packet data may include to use the shared resources to process packet data at a media access control (MAC) module for the network interface.

The method of example 13, the first validated pattern may be a pattern that indicates a count of chunks of data that are processed at the MAC module for the packet data received or sent through the first port before a tail or end of packet is detected.

The method of example 10, the TDM storage resource may be static random access memory (SRAM), a plurality of latches, or a combination of latches and SRAM.

The method of example 10 may also include loading, for a second port from among the ports, a second validated pattern to the TDM storage resource. The second validated pattern may facilitate processing packet data received or sent through the second port during a second time slot from among the repeating sequence of time slots. The second time slot may be allocated to the second port for use of the shared resources. The method may also include loading, for a third port from among the ports, a third validated pattern to the TDM storage resource. The third validated pattern may facilitate processing packet data received or sent through the third port during a third time slot from among the repeating sequence of time slots. The third time slot may be allocated to the third port for use of the shared resources.

The method of example 16 may also include the first port capable of coupling with a first transmission medium having a first data bandwidth and the second and third ports capable of coupling with a second transmission medium having a second data bandwidth. The first data bandwidth may be two times greater than the second data bandwidth. The first port may be allocated a half of a total number of the repeating sequence of time slots The second and third ports may be separately allocated a fourth of the total number of the repeating sequence of time slots.

At example least one machine readable medium may include a plurality of instructions that in response to being executed by a system cause the system to carry out a method according to any one of examples 10 to 17.

An example apparatus may include means for performing the methods of any one of examples 10 to 17.

An example at least one machine readable medium may include a plurality of instructions that in response to being executed by a system, cause the system to obtain TDM allocation information that indicates a time period for a repeating sequence of time slots for use of shared resources to process packet data received or sent through ports of a network interface. The instructions may also cause the system to detect separate patterns associated with receiving or sending data through respective ports of the network interface. The instructions may also cause the system to verify that the separate patterns repeat to validate the separate patterns. The instructions may also cause the system to load, for a first port from among the ports, a first validated pattern to a TDM storage resource included in the shared resources. The first validated pattern may facilitate processing packet data received or sent through the first port during a first time slot from among the repeating sequence of time slots, the first time slot allocated to the first port for use of the shared resources.

The at least one machine readable medium of example 20, the network interface may be a NIC. The instructions may also cause the system to obtain the TDM allocation information from one or more registers located on the NIC.

The at least one machine readable medium of example 20, the TDM allocation information may further indicate a size of individual time slots in relation to the time period for the repeating sequence of time slots, which ports from among the ports of the network interface are assigned to the individual time slots, or identify the TDM storage resource included in the shared resources.

The at least one machine readable medium of example 20, the use of the shared resources to process packet data may include to use of the shared resources to process packet data at a MAC module for the network interface.

The at least one machine readable medium of example 23, the first validated pattern may include a pattern that indicates a count of chunks of data that are processed at the MAC for the packet data received or sent through the first port before a tail or end of packet is detected.

The at least one machine readable medium of example 20, the TDM storage resource may be static random access memory (SRAM), a plurality of latches, or a combination of latches and SRAM.

The at least one machine readable medium of example 20, further including the instructions to cause the system to load, for a second port from among the ports, a second validated pattern to the TDM storage resource. The second validated pattern may facilitate processing packet data received or sent through the second port during a second time slot from among the repeating sequence of time slots. The second time slot may be allocated to the second port for use of the shared resources. The instructions may also cause the system to load, for a third port from among the ports, a third validated pattern to the TDM storage resource. The third validated pattern may facilitate processing packet data received or sent through the third port during a third time slot from among the repeating sequence of time slots. The third time slot may be allocated to the third port for use of the shared resources.

The at least one machine readable medium of example 26 may also include the first port being capable of coupling with a first transmission medium having a first data bandwidth and the second and third ports capable of coupling with a second transmission medium having a second data bandwidth. The first data bandwidth may be two times greater than the second data bandwidth. The first port may be allocated a half of a total number of the repeating sequence of time slots. The second and third ports may be separately allocated a fourth of the total number of the repeating sequence of time slots.