Circuit for preventing simultaneous on operations

Providing a circuit for preventing simultaneous ON operations at a relay drive apparatus, which can prevent the simultaneous ON operations securely, the circuit includes a first diode, a second diode, a first transistor connected through the first diode with a first drive unit for controlling ON/OFF operation, a second transistor connected through the second diode with the second drive unit for controlling ON/OFF operation, a first junction point of the first resistor and the first drive unit, a second junction point of the second resistor and the second drive unit, a third junction point of the first diode and the first transistor, a fourth junction point of the second diode and the second transistor, a third diode connected with the second junction point and the third junction point, and a fourth diode connected with the first junction point and the fourth junction point.

The priority application Number Japan Patent Application 2005-007026 upon which this patent application is based is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a circuit for preventing simultaneous ON operations at a relay drive apparatus.

2. Description of the Related Art

As a circuit for preventing simultaneous ON operations at a relay drive apparatus, a usual inhibit circuit by a logic IC is applied.

FIG. 5is a circuit diagram of the circuit for preventing simultaneous ON operations at the usual relay drive apparatus. As shown inFIG. 5, in a relay drive circuit, an inhibit circuit4as a circuit for preventing simultaneous ON operations is connected between two semiconductor relays1,2and control signal output terminals P1, P2of a controller3having a microcomputer for controlling ON/OFF operation of the semiconductor relays1,2. The control signal output terminals P1, P2output respectively control signals, one of those is “H” level and the other of those is “L” level.

The semiconductor relay1includes a photo-coupler having a light emitting diode laconnected through a first resistor R1with +Vcc power supply and a semiconductor switch element1bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element1bis connected with one signal line (first signal line)5aof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

The semiconductor relay2includes a photo-coupler having a light emitting diode2aconnected through a second resistor R2with +Vcc power supply and a semiconductor switch element2bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element2bis connected with the other signal line (second signal line)5bof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

The inhibit circuit4includes four NAND gate elements with two input terminal4a,4b,4c,4d. Two input terminals of the NAND gate element4aare connected with the control signal output terminal P2, and an output terminal thereof is connected with one of two input terminals of the NAND gate element4b. The other of two input terminals of the NAND gate element4bis connected with the control signal output terminal P1, and an output terminal thereof is connected with the light emitting diode1aof the semiconductor relay1. Two input terminals of the NAND gate element4care connected with the control signal output terminal P1, and an output terminal thereof is connected with one of two input terminals of the NAND gate element4d. The other of two input terminals of the NAND gate element4dis connected with the control signal output terminal P2, and an output terminal thereof is connected with the light emitting diode2aof the semiconductor relay2.

In the above structure, when the control signal output terminal P1of the controller3is “H” level and the control signal output terminal P2is “L” level in normal operations, an output terminal of the NAND gate element4bof the inhibit circuit4accordingly becomes “L” level, and an output terminal of the NAND gate element4dbecomes “H” level. Thereby, the light emitting diode1aof the semiconductor relay1is turned on a light and the semiconductor switch element1bturns ON. The light emitting diode2aof the semiconductor relay2is OFF and the semiconductor switch element2bis OFF.

Oppositely, when the control signal output terminal P1of the controller3is “L” level and the control signal output terminal P2is “H” level, the output terminal of the NAND gate element4bof the inhibit circuit4accordingly becomes “H” level, and the output terminal of the NAND gate element4dbecomes “L” level. Thereby, the light emitting diode2aof the semiconductor relay2is turned on a light and the semiconductor switch element2bturns ON. The light emitting diode1aof the semiconductor relay1is OFF and the semiconductor switch element1bis OFF.

When the both control signal output terminals P1, P2become “H” level because of a malfunction or stampede of the microcomputer as an abnormal operating condition, the both output terminals of the NAND gate elements4b,4dbecome “H” level. Thereby, the both light emitting diodes1a,2aof the semiconductor relays1,2are OFF, and the both semiconductor switch elements1b,2bbecome OFF. Thus, on the abnormal operating condition, the semiconductor switch elements1b,2bare prevented from simultaneous ON operations.

A circuit for preventing ON operations, which is structured and works as mentioned above, is disclosed in Japan Patent Application Laid Open 2002-75622.

SUMMARY OF THE INVENTION

Objects to be Solved

The usual circuit as mentioned above has following problems:1) When the microcomputer stampedes or malfunctions, simultaneous ON operations of two outputs can be prevented securely. However, when the inhibit circuit4malfunctions (for example, latchup occurs), output terminals of two NAND gate elements4b,4dbecome “L” level together by themselves, the both light emitting diodes1a,2aare turned on a light, and the both semiconductor switch elements1b,2bturn ON.2) The inhibit circuit4is structured with logic ICs, so that it is weak for noise and voltage change of power supply, and weak to malfunction by strong noise by static electricity or unexpected input voltage.3) Cost of ICs structuring the inhibit circuit4is expensive.

To overcome the above problem, an object of the present invention is to provide a circuit for preventing simultaneous ON operations at a relay drive apparatus, which can prevent the simultaneous ON operations securely by low cost.

How to Attain the Object of the Present Invention

In order to attain the object of the present invention, a circuit for preventing simultaneous ON operations according to an aspect of the present invention is characterized at a relay drive apparatus, which includes a first relay having a first drive unit receiving drive current through a first resistor from a power supply and a first switch device connected with a first signal line to be driven by the first drive unit, a second relay having a second drive unit receiving drive current through a second resistor from said power supply and a second switch device connected with a second signal line to be driven by the second drive unit, and a controller having a first control signal output terminal for outputting a control signal to control the first drive unit and a second control signal output terminal for outputting a control signal to control the second drive unit in that includes a first diode, a second diode, a first transistor connected through the first diode with the first drive unit for controlling ON/OFF operation by the control signal derived from the first control signal output terminal of the controller, a second transistor connected through the second diode with the second drive unit for controlling ON/OFF operation by the control signal derived from the second control signal output terminal of the controller, a first junction point of the first resistor and the first drive unit, a second junction point of the second resistor and the second drive unit, a third junction point of the first diode and the first transistor, a fourth junction point of the second diode and the second transistor, a third diode, an anode of which is connected to the second junction point and a cathode of which is connected to the third junction point, and a fourth diode, an anode of which is connected to the first junction point and a cathode of which is connected to the fourth junction point.

A circuit for preventing simultaneous ON operations according to another aspect of the present invention is characterized at a relay drive apparatus, which includes a first relay having a first drive unit receiving drive current through a first resistor from a power supply and a first switch device connected with a first signal line to be driven by the first drive unit, a second relay having a second drive unit receiving drive current through a second resistor from said power supply and a second switch device connected with a second signal line to be driven by the second drive unit, and a controller having a first control signal output terminal for outputting a control signal to control the first drive unit and a second control signal output terminal for outputting a control signal to control the second drive unit in that includes a first diode being connected between the first resistor and the first drive unit, a second diode being connected between the second resistor and the second drive unit, a first transistor being connected with the first drive unit for controlling ON/OFF operation by the control signal derived from the first control signal output terminal of the controller, a second transistor being connected with the second drive unit for controlling ON/OFF operation by the control signal derived from the second control signal output terminal of the controller, a first junction point of the first resistor and the first drive unit, a second junction point of the second resistor and the second drive unit, a fifth junction point of the first drive unit and the first transistor, a sixth junction point of the second drive unit and the second transistor, a third diode, an anode of which is connected to the second junction point and a cathode of which is connected to the fifth junction point, and a fourth diode, an anode of which is connected to the first junction point and a cathode of which is connected to the sixth junction point.

A circuit for preventing simultaneous ON operations is further characterized in that the first diode and the fourth diode have a same characteristic, and the second diode and the fourth diode have a same characteristic.

A circuit for preventing simultaneous ON operations according to further aspect of the present invention is characterized at a relay drive apparatus, which includes a first relay having a first drive unit receiving drive current through a first resistor from a power supply and a first switch device connected with a first signal line to be driven by the first drive unit, a second relay having a second drive unit receiving drive current through a second resistor from said power supply and a second switch device connected with a second signal line to be driven by the second drive unit, and a controller having a first control signal output terminal for outputting a control signal to control the first drive unit and a second control signal output terminal for outputting a control signal to control the second drive unit in that includes a first diode, a second diode, a first transistor being connected with the first drive unit for controlling ON/OFF operation by the control signal derived from the first control signal output terminal of the controller, a second transistor being connected with the second drive unit for controlling ON/OFF operation by the control signal derived from the second control signal output terminal of the controller, a first junction point of the first resistor and the first drive unit, a second junction point of the second resistor and the second drive unit, a third transistor being connected through the first diode with the first junction point and through the second diode with the second junction point, a third diode being connected between the first control signal output terminal and the third transistor, and a fourth diode being connected between the second control signal output terminal and the third transistor.

EFFECT OF THE INVENTION

According to the above structure, a circuit for preventing simultaneous ON operations, which ON/OFF operation is securely acted and can prevent from turning drive outputs ON simultaneously even if the circuit for preventing simultaneous ON operations malfunctions, can be given. The circuit is built with discrete components, so that immunity against noise caused by static electricity can be improved. It will be low cost compared with a circuit by ICs.

According to the above structure, bad effects caused by dispersion of characteristics of diodes, such as an effect for an ON/OFF control voltage of the first and second transistors caused by dispersion of forward voltage drop of diodes, can be eliminated.

According to the above structure, a circuit for preventing simultaneous ON operations, which acts securely, can be given. Since the circuit is structured with discrete components, the immunity against noise caused by the static electricity is improved, and cost of the circuit is lower than that of the circuit with ICs.

The above and other objects and features of this invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENT

First Embodiment

FIG. 1is a circuit diagram showing a structure of a circuit for preventing simultaneous ON operations at a relay drive apparatus according to a first embodiment of the present invention.

InFIG. 1, a semiconductor relay drive circuit (relay drive apparatus) includes a controller3having two semiconductor relays (first and second relays)1,2and a microcomputer for controlling ON/OFF operation of the semiconductor relays1,2. A circuit for preventing simultaneous ON operations6is connected between the semiconductor relays1,2and control signal output terminals P1, P2of the controller3. The control signal output terminals P1, P2output respectively control signals; one of those is “H” level and the other of those is “L” level.

The semiconductor relay1includes a photo-coupler having a light emitting diode1a(first drive unit) connected through a first resistor R1with +Vcc power supply and a semiconductor switch element (first switch device)1bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element1bis connected with one signal line (first signal line)5aof two signal lines (first and second signal lines)5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

In detail, the semiconductor relay1is structured with a photo-coupler1A, which has the light emitting diode1aconnected with an input terminals1B,1C and a photo diode1creceiving light signals emitted by the light emitting diode1a, and the semiconductor switch element1bstructured by the MOS-FET turning ON/OFF to be controlled by the output from the photo-coupler1A, as shown inFIG. 2.

Similarly, the semiconductor relay2includes a photo-coupler having a light emitting diode (second drive unit)2aconnected through a second resistor R2with +Vcc power supply and a semiconductor switch element (second switch device)2bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element2bis connected with the other signal line (second signal line)5bof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations. For example, it is assumed that the signal line5ais a positive electric power line and the signal line5bis a negative electric power line, and when the semiconductor switch elements1b,2bturn ON simultaneously, the power supply is short-circuited. The semiconductor relay2has the same structure as the semiconductor relay1shown inFIG. 2, and the description of that is omitted.

The circuit for preventing simultaneous ON operations6includes first and second transistors Q1, Q2, diodes D1-D4and resistors R5-R8. The first transistor Q1is an NPN transistor; a base of which is connected through the resistor R5with the control signal output terminal P1of the controller3and through the resistor R6with ground; an emitter of which is grounded; and a collector of which is connected through a third junction point J03of the first diode D1and the first transistor Q1, and the first diode D1with the light emitting diode1aof the semiconductor relay1and connected through the third junction point J03and the third diode D3with a second junction point J02of the resistor R3and the light emitting diode2aof the semiconductor relay2. The first diode D1is connected in forward direction from a cathode of the light emitting diode1ato the collector of the first transistor Q1. The third diode D3is connected in forward direction from the second junction point J02of the second resistor R2and the light emitting diode2ato the collector of the first transistor Q1.

The second transistor Q2is an NPN transistor; a base of which is connected through the resistor R7with the control signal output terminal P2of the controller3and through the resistor R8with ground; an emitter of which is grounded; and a collector of which is connected through a fourth junction point J04of the second diode D2and the second transistor Q2, and the second diode D2with the light emitting diode2aof the semiconductor relay2and connected through the junction point J04and the fourth diode D4with a first junction point J01of the first resistor R1and the light emitting diode1aof the semiconductor relay1. The second diode D2is connected in forward direction from a cathode of the light emitting diode2ato the collector of the second transistor Q2. The third diode D3is connected in forward direction from the first junction point J01of the first resistor R1and the light emitting diode1ato the collector of the second transistor Q2.

In the above structure, when the control signal output terminal P1of the controller3is “H” level and the control signal output terminal P2of the controller3is “L” level in a normal operation, the first transistor Q1of the circuit for preventing simultaneous ON operations6turns ON accordingly. Thereby, the light emitting diode1aof the semiconductor relay1is turned on a light, and the semiconductor switch element1bis turned ON. The second transistor Q2is OFF, and the second junction point J02of the second resistor R2and the light emitting diode2aof the semiconductor relay2is connected through the third diode D3and the first transistor Q1with ground. Therefore, power supply to the light emitting diode2ais cut off, so that the light emitting diode2aturns OFF and the semiconductor switch element2bis turned OFF.

Oppositely, when the control signal output terminal P2of the controller3is “H” level and the control signal output terminal P1of the controller3is “L” level in a normal operation, the second transistor Q2of the circuit for preventing simultaneous ON operations6turns ON accordingly. Thereby, the light emitting diode2aof the semiconductor relay2is turned on a light, and the semiconductor switch element2bis turned ON. The first transistor Q1is OFF, and the first junction point J01of the first resistor R1and the light emitting diode1aof the semiconductor relay1is connected through the fourth diode D4and the second transistor Q2with ground. Therefore, power supply to the light emitting diode1ais cut off, so that the light emitting diode1aturns OFF and the semiconductor switch element1bis turned OFF.

At an abnormal condition when the control signal output terminals P1, P2of the controller3are both “H” level by malfunction or stampede of the microcomputer, the both first and second transistors Q1, Q2of the circuit for preventing simultaneous ON operations6turn ON. Thereby, the second junction point J02of the second resistor R2and the light emitting diode2aof the semiconductor relay2is connected through the third diode D3and the first transistor Q1with ground. The first junction point J01of the first resistor R1and the light emitting diode1aof the semiconductor relay1is connected through the fourth diode D4and the second transistor Q2with ground. Therefore, power supply to the light emitting diodes1aand2ais cut off, so that the light emitting diodes1a,2aturn OFF and the semiconductor switch elements1b,2bare turned OFF. Thus, simultaneous ON operations of the semiconductor switch elements1b,2bare prevented at the abnormal operation.

When the first and second transistors Q1, Q2are simultaneously short-circuited between each collector and each emitter by simultaneous malfunction, the second junction point J02of the second resistor R2and the light emitting diode2aof the semiconductor relay2is connected through the third diode D3and the first transistor Q1with ground, and the first junction point J01of the first resistor R1and the light emitting diode1aof the semiconductor relay1is connected through the fourth diode D4and the second transistor Q2with ground. Therefore, power supply to the light emitting diodes1aand2ais cut off, so that the light emitting diodes1a,2aturn OFF and the semiconductor switch elements1b,2bare turned OFF. Thus, simultaneous ON operations of the semiconductor switch elements1b,2bare prevented.

According to the first embodiment of the present invention, a circuit for preventing simultaneous ON operations, which ON/OFF operations is securely acted and can prevent from turning drive outputs ON simultaneously even if the circuit for preventing simultaneous ON operations malfunctions, can be given. The circuit is built with discrete components, so that immunity against noise caused by static electricity can be improved. It will be low cost compared with a circuit by ICs.

Second Embodiment

FIG. 3is a circuit diagram showing a structure of a circuit for preventing simultaneous ON operations at a relay drive apparatus according to a second embodiment of the present invention.

InFIG. 3, a semiconductor relay drive circuit includes a controller3having two semiconductor relays1,2and a microcomputer for controlling ON/OFF operation of the semiconductor relays1,2. A circuit for preventing simultaneous ON operations6is connected between the semiconductor relays1,2and control signal output terminals P1, P2of the controller3. The control signal output terminals P1, P2output respectively control signals; one of those is “H” level and the other of those is “L” level.

The semiconductor relay1includes a photo-coupler having a light emitting diode1aconnected through a first resistor R1with +Vcc power supply and a semiconductor switch element1bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element1bis connected with one signal line5aof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

Similarly, the semiconductor relay2includes a photo-coupler having a light emitting diode2aconnected through a second resistor R2with +Vcc power supply and a semiconductor switch element2bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element2bis connected with the other signal line5bof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

The circuit for preventing simultaneous ON operations6includes the first and second transistors Q1, Q2, diodes D1-D4and resistors R5-R8. The first transistor Q1is an NPN transistor; a base of which is connected through the resistor R5with the control signal output terminal P1of the controller3and through the resistor R6with ground; an emitter of which is grounded; and a collector of which is connected through a fifth junction point J05of the light emitting diode1aand the first transistor Q1with the light emitting diode1aand through the fifth junction point J05and the third diode D3with a second junction point J02of the second resistor R2and the light emitting diode2a. The third diode D3is connected in forward direction from the second junction point J02of the second resistor R2and the light emitting diode2ato the collector of the first transistor Q1.

The first diode D1is connected in forward direction from the first resistor R1to the light emitting diode1a.

The second transistor Q2is an NPN transistor; a base of which is connected through the resistor R7with the control signal output terminal P2of the controller3and through the resistor R8with ground; an emitter of which is grounded; and a collector of which is connected through a sixth junction point J06of the light emitting diode2aand the second transistor Q2with the light emitting diode2aand connected through the sixth junction point J06and the fourth diode D4with a first junction point J01of the first resistor R1and the light emitting diode1a. The fourth diode D4is connected in forward direction from the first junction point J01of the first resistor R1and the light emitting diode1ato the collector of the second transistor Q2.

The second diode D2is connected in forward direction from the second resistor R2to the light emitting diode2a. The second and third diodes D2, D3to be packaged in a package8have the same characteristics. The first and fourth diodes D1, D4to be packaged in a package7have the same characteristics.

In the above structure, when the control signal output terminal P1of the controller3is “H” level and the control signal output terminal P2of the controller3is “L” level in a normal operation, the first transistor Q1of the circuit for preventing simultaneous ON operations6turns ON accordingly. Thereby, the light emitting diode1aof the semiconductor relay1is turned on a light, and the semiconductor switch element1bis turned ON. The second transistor Q2is OFF, and the second junction point J02of the second resistor R2and the light emitting diode2ais connected through the third diode D3and the first transistor Q1with ground. Therefore, power supply to the light emitting diode2ais cut off, so that the light emitting diode2aturns OFF and the semiconductor switch element2bis turned OFF.

Oppositely, when the control signal output terminal P2of the controller3is “H” level and the control signal output terminal P1of the controller3is “L” level, the second transistor Q2of the circuit for preventing simultaneous ON operations6turns ON accordingly. Thereby, the light emitting diode2aof the semiconductor relay2is turned on a light, and the semiconductor switch element2bis turned ON. The first transistor Q1is OFF, and the first junction point J01of the first resistor R1and the light emitting diode1ais connected through the fourth diode D4and the second transistor Q2with ground. Therefore, power supply to the light emitting diode1ais cut off, so that the light emitting diode1aturns OFF and the semiconductor switch element1bis turned OFF.

At an abnormal condition when the control signal output terminals P1, P2of the controller3are both “H” level by malfunction or stampede of the microcomputer, the both first and second transistors Q1, Q2turn ON. Thereby, the second junction point J02of the second resistor R2and the light emitting diode2ais connected through the third diode D3and the first transistor Q1with ground. The first junction point J01of the first resistor R1and the light emitting diode1ais connected through the fourth diode D4and the second transistor Q2with ground. Therefore, power supply to the light emitting diodes1aand2ais cut off, so that the light emitting diodes1a,2aturn OFF and the semiconductor switch elements1b,2bare turned OFF. Thus, simultaneous ON operations of the semiconductor switch elements1b,2bare prevented at the abnormal operation.

When the first and second transistors Q1, Q2are simultaneously short-circuited between each collector and each emitter by simultaneous malfunction, the second junction point J02of the second resistor R2and the light emitting diode2ais connected through the third diode D3and the first transistor Q1with ground, and the first junction point J01of the first resistor R1and the light emitting diode1ais connected through the fourth diode D4and the second transistor Q2with ground. Therefore, power supply to the light emitting diodes1aand2ais cut off, so that the light emitting diodes1a,2aturn OFF and the semiconductor switch elements1b,2bare turned OFF. Thus, simultaneous ON operations of the semiconductor switch elements1b,2bare prevented. The first and fourth diodes D1, D4to be packaged in a package7have the same characteristics. The second and third diodes D2, D3to be packaged in a package8have the same characteristics. Bad effects caused by dispersion of characteristics of diodes, such as an effect for an ON/OFF control voltage of the first and second transistors caused by dispersion of forward voltage drop of diodes, can be eliminated.

According to the second embodiment of the present invention, a circuit for preventing simultaneous ON operations, which ON/OFF operations is securely acted and can prevent from turning drive outputs ON simultaneously even if the circuit for preventing simultaneous ON operations malfunctions, can be given. The circuit is built with discrete components, so that immunity against noise caused by static electricity can be improved. It will be low cost compared with a circuit by ICs. Bad effects caused by dispersion of characteristics of diodes can be eliminated.

Third Embodiment

FIG. 4is a circuit diagram showing a structure of a circuit for preventing simultaneous ON operations at a relay drive apparatus according to a third embodiment of the present invention.

InFIG. 4, a semiconductor relay drive circuit includes a controller3having two semiconductor relays1,2and a microcomputer for controlling ON/OFF operation of the semiconductor relays1,2. A circuit for preventing simultaneous ON operations6is connected between the semiconductor relays1,2and control signal output terminals P1, P2of the controller3. The control signal output terminals P1, P2output respectively control signals; one of those is “H” level and the other of those is “L” level.

The semiconductor relay1includes a photo-coupler having a light emitting diode1aconnected through a first resistor R1with +Vcc power supply and a semiconductor switch element1bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element1bis connected with one signal line5aof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

Similarly, the semiconductor relay2includes a photo-coupler having a light emitting diode2aconnected through a second resistor R2with +Vcc power supply and a semiconductor switch element2bstructured by a MOS-FET turning ON/OFF to be controlled by an output from the photo-coupler. The semiconductor switch element2bis connected with the other signal line5bof two signal lines5a,5bto be alternatively turned ON for danger by simultaneous ON operations.

The circuit for preventing simultaneous ON operations6includes first, second and third transistors Q1, Q2, Q3, diodes D1-D4and resistors R5-R11. The first transistor Q1is an NPN transistor; a base of which is connected through the resistor R5with the control signal output terminal P1of the controller3and through the resistor R6with ground; an emitter of which is grounded; and a collector of which is connected with the light emitting diode1a.

The second transistor Q2is an NPN transistor; a base of which is connected through the resistor R7with the control signal output terminal P2of the controller3and through the resistor R8with ground; an emitter of which is grounded; and a collector of which is connected with the light emitting diode2a.

The transistor Q3is an NPN transistor; a base of which is connected through the resistor R9and the third diode D3with the control signal output terminal P1of the controller3, and connected through the resistor R9and the fourth diode D4with the control signal output terminal P2of the controller3, and through the resistor R10with ground; an emitter of which is grounded; and a collector of which is connected through the first diode D1with the first junction point J01of the first resistor R1and the light emitting diode1aand connected through the second diode D2with the second junction point J02of the second resistor R2and the light emitting diode2a. +Vcc power supply is connected through the resistor R11with a junction point of the resistor R9, and the third and fourth diodes D3, D4.

The third diode D3is connected in forward direction from the resistor R9to the control signal output terminal P1. The fourth diode D4is connected in forward direction from the resistor R9to the control signal output terminal P2. The first diode D1is connected in forward direction from the first junction point J01of the first resistor R1and the light emitting diode1ato the collector of the transistor Q3. The second diode D2is connected in forward direction from the second junction point J02of the second resistor R2and the light emitting diode2ato the collector of the transistor Q3. The first and second diodes D1, D2to be packaged in a package9have the same characteristics. The third and fourth diodes D3, D4to be packaged in a package10have the same characteristics.

In the above structure, when the control signal output terminal P1of the controller3is “H” level and the control signal output terminal P2of the controller3is “L” level in a normal operation, the first transistor Q1of the circuit for preventing simultaneous ON operations6turns ON accordingly. Thereby, the light emitting diode1aof the semiconductor relay1is turned on a light, and the semiconductor switch element1bis turned ON. The second transistor Q2is OFF, and the light emitting diode2ais turned OFF. When the control signal output terminal P2becomes “L” level in the above condition, the fourth diode D4is in a conductive condition and the base of the transistor Q3becomes “L” level. Therefore, the transistor Q3is OFF.

Oppositely, when the control signal output terminal P2of the controller3is “H” level and the control signal output terminal P1of the controller3is “L” level, the second transistor Q2of the circuit for preventing simultaneous ON operations6turns ON accordingly. Thereby, the light emitting diode2aof the semiconductor relay2is turned on a light, and the semiconductor switch element2bis turned ON. Since the first transistor Q1is OFF, the light emitting diode1ais turned OFF, and the semiconductor switch element1bis turned OFF. When the control signal output terminal P1becomes “L” level in the above condition, the third diode D3is in a conductive condition, and the base of the transistor Q3becomes “L” level. Therefore, the transistor Q3is OFF.

At an abnormal condition when the control signal output terminals P1, P2of the controller3are both “H” level by malfunction or stampede of the microcomputer, the both first and second transistors Q1, Q2turn ON. Thereby, the third and fourth diodes D3, D4are not in a conductive condition and the base of the transistor Q3is supplied with “H” level voltage through the resistors R9, R11from the +Vcc power supply, so that the transistor Q3turns ON. Therefore, the first junction point J01of the first resistor R1and the light emitting diode1ais connected through the first diode D1and the third transistor Q3with ground, and the second junction point J02of the second resistor R2and the light emitting diode2ais connected through the second diode D2and the transistor Q3with ground. Thereby, power supply to the light emitting diodes1aand2ais cut off, so that the light emitting diodes1a,2aturn OFF and the semiconductor switch elements1b,2bare turned OFF. Thus, simultaneous ON operations of the semiconductor switch elements1b,2bare prevented at the abnormal operation.

The first and second diodes D1, D2to be packaged in a package9have the same characteristics. The third and fourth diodes D3, D4to be packaged in a package10have the same characteristics. Bad effects caused by dispersion of characteristics of diodes, such as an effect for an ON/OFF control voltage of the first and second transistors caused by dispersion of forward voltage drop of diodes, can be eliminated.

According to the third embodiment of the present invention, a circuit for preventing simultaneous ON operations, which ON/OFF operations is securely acted and can prevent from turning drive outputs ON simultaneously even if the circuit for preventing simultaneous ON operations malfunctions, can be given. The circuit is built with discrete components, so that immunity against noise caused by static electricity can be improved. It will be low cost compared with a circuit by ICs.

Although the present invention has been fully described by way of embodiments, it is to be noted that various change and modifications can be made with the scope of the present invention as defined by the following claims.

For example, instead of semiconductor relays used in the above embodiments, normal relays having an magnetizing coil and contact switches can be used.

Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various change and modifications can be made with the scope of the present invention as defined by the following claims.