Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same

The present invention relates to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same. The liquid crystal display device may include a gate line formed on the substrate; a data line crossed with the gate line to define a pixel region; a thin-film transistor (TFT) formed at an intersection of the gate and data line; an organic insulating layer formed to have an opening portion for exposing the TFT; a common electrode having an area formed at an upper portion of the organic insulating layer, and an auxiliary electrode pattern connected to the TFT through the opening portion; a passivation layer formed to expose the auxiliary electrode pattern connected to the TFT; and pixel electrodes electrically connected to the TFT through the exposed auxiliary electrode pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2011-0120367, filed on Nov. 17, 2011, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same.

2. Description of the Related Art

In general, the driving principle of a liquid crystal display device is based on optical anisotropy and polarization of liquid crystals. Liquid crystals having an elongated structure exhibit directivity in molecular arrangement, and thus the direction of their molecular arrangement can be controlled by artificially applying an electric field to liquid crystals.

Accordingly, if the molecular arrangement direction of liquid crystals is arbitrarily controlled, then the molecular arrangement of liquid crystals may be changed, and light is refracted in the molecular arrangement direction of liquid crystals by optical anisotropy to exhibit image information.

At present, an active matrix liquid crystal display device (AM-LCD; hereinafter, abbreviated as a “liquid crystal display device”) in which thin-film transistors and pixel electrodes connected to the thin-film transistors are arranged in a matrix form have been widely used due to its resolution and video implementation capability.

The liquid crystal display device may include a color filter substrate (i.e., upper substrate) formed with common electrodes, an array substrate (i.e., lower substrate) formed with pixel electrodes, and liquid crystals filled between the upper and lower substrates, in which liquid crystals are driven by an electric field applied in the vertical direction between the common electrode and pixel electrode, thereby having excellent transmittance and aperture ratio.

However, the driving of liquid crystals by an electric field applied in the vertical direction has a drawback of providing insufficient viewing angle characteristics. Accordingly, a driving method of liquid crystals by in-plane switching has been newly proposed to overcome the foregoing drawback, and the driving method of liquid crystals by in-plane switching has excellent viewing angle characteristics.

Such an in-plane switching mode liquid crystal display device may include a color filter substrate and an array substrate facing each other, and a liquid crystal layer is interposed between the color filter substrate and the array substrate.

A thin-film transistor, a common electrode and pixel electrode are provided for a plurality of pixels, respectively, defined on a transparent insulating substrate on the array substrate.

Furthermore, the common electrode and pixel electrode are configured to be separated from each other in parallel on the same substrate.

In addition, the color filter substrate may include a black matrix at a portion corresponding to a gate line, data line, and a thin-film transistor on a transparent insulating substrate, and a color filter corresponding to the pixel.

Moreover, the liquid crystal layer is driven by a horizontal electric field between the common electrode and pixel electrode.

Here, the common electrode and pixel electrode are formed with a transparent electrode to secure brightness.

Accordingly, a fringe field switching (FFS) technique has been proposed to maximize the brightness enhancement effect. The FFS technique allows liquid crystals to be controlled in a precise manner, thereby obtaining high contrast ratio with no color shift.

A method of fabricating a fringe field switching (FFS) mode liquid crystal display device according to the related art will be described with reference toFIGS. 1 and 2.

FIG. 1is a schematic plane view illustrating a fringe field switching (FFS) mode liquid crystal display device according to the related art.

FIG. 2is a schematic cross-sectional view illustrating a fringe field switching (FFS) mode liquid crystal display device, as a cross-sectional view along the line II-II ofFIG. 1.

An array substrate for a fringe field switching (FFS) mode liquid crystal display device according to the related art may include a plurality of gate lines13extended in one direction on a transparent insulating substrate11to be separated from one another in parallel; a plurality of data lines21crossed with the gate lines13to define pixel regions in the crossed areas; a thin-film transistor (T) provided at an intersection of the gate line13and the data line21, and made of a gate electrode13aextended from the gate line13in the vertical direction, a gate insulating layer15, an active layer17, an ohmic contact layer19, a source electrode21aand a drain electrode21b; a second passivation layer27formed on a front surface of the substrate including the thin-film transistor (T); a pixel electrodes29having a large area formed on the first passivation layer27and connected to the thin-film transistor (T); a second passivation layer31formed on the first passivation layer27including the pixel electrode29; and a plurality of pixel electrodes37formed on the passivation layer35; a plurality of common electrodes33formed to be separated from one another on the second passivation layer31to correspond to the pixel electrodes29, as illustrated inFIGS. 1 and 2.

Here, the pixel electrodes29having a large area are disposed in a pixel region in which the gate line13are data line21are crossed with each other.

Furthermore, the common electrode33is overlapped with the pixel electrode29by interposing the second passivation layer31therebetween. Here, the pixel electrode29and the plurality of common electrodes33are formed of Indium Tin Oxide (ITO) which is a transparent conductive material.

In addition, the pixel electrode29is electrically connected to the drain electrode21bthrough a drain contact hole27aformed on the first passivation layer27.

Moreover, though not shown in the drawing, a color filter layer (not shown) and a black matrix (not shown) disposed between the color filter layers to block the transmission of light are deposited on a color filter substrate (not shown) bonded to the insulating substrate11formed with the pixel electrode29and a plurality of common electrodes33, and an overcoat layer (not shown) may be formed on the black matrix and color filter layer to planarize between the black matrix and color filter layer.

Furthermore, though not shown in the drawing, a liquid crystal layer (not shown) may be formed between the color filter substrate (not shown) and the insulating substrate11bonded to each other.

As described above, according to a FFS mode liquid crystal display device in the related art, a drain contact hole should be formed to connect a pixel electrode and a drain electrode of the thin-film transistor to the passivation layer, and a liquid crystal disclination region hole is created at the circumference of the drain contact hole during the formation of the drain contact hole, thereby causing light leakage.

Accordingly, in the related art, in order to prevent light leakage caused by creating a liquid crystal disclination region at the circumference of the drain contact hole, the entire circumference portion of the drain contact hole should be covered by using a black matrix (BM), and thus an opening region thereof, namely, an area of the transmission region, may be reduced, thereby decreasing the transmittance of a pixel. In particular, the drain contact hole should be covered with a black matrix (BM) by taking a bonding margin into consideration as much as a distance to prevent light leakage caused by a disclination region of liquid crystals created by the drain contact hole, and thus the transmission region of a pixel may be reduced as much as the distance, thereby decreasing the transmittance to the extent.

Furthermore, it has a structure with no contact hole as well as a structure in which the common electrode is disposed at the uppermost portion, thereby causing a problem such as CT or horizontal line due to interference between data pixels.

Accordingly, in case of a structure in which the common electrode is disposed at the uppermost portion, it has a structure in which the pixel is located adjacent to the data line, thereby causing interference between the data line and pixel electrode.

SUMMARY OF THE INVENTION

The present invention is contrived to improve the foregoing problems, and an objective of the present invention is to provide a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same capable of maximizing an opening region of the pixel without separately forming a drain contact hole for connecting a drain electrode to a pixel electrode in a fringe field switching (FFS) mode liquid crystal display device, thereby increasing the transmittance.

In order to accomplish the foregoing objective, there is provided an array substrate for a fringe field switching (FFS) mode liquid crystal display device, and the array substrate may include a gate line formed in one direction on a surface of the substrate; a data line crossed with the gate line to define a pixel region; a thin-film transistor formed at an intersection of the gate line and data line; an organic insulating layer formed on an entire surface of the substrate including the thin-film transistor to have an opening portion for exposing the thin-film transistor; a common electrode having a large area formed at an upper portion of the organic insulating layer, and an auxiliary electrode pattern connected to the thin-film transistor through the opening portion; a passivation layer formed on an entire surface of the substrate including the common electrode and auxiliary electrode pattern to expose the auxiliary electrode pattern connected to the thin-film transistor; and a plurality of pixel electrodes formed at an upper portion of the passivation layer, and electrically connected to the thin-film transistor through the exposed auxiliary electrode pattern, and overlapped with the common electrode.

In order to accomplish the foregoing objective, there is provided a method of fabricating an array substrate for a fringe field switching (FFS) mode liquid crystal display device, and the method may include forming a gate line in one direction on a surface of the substrate; forming a data line crossed with the gate line to define a pixel region; forming a thin-film transistor at an intersection of the gate line and data line; forming an organic insulating layer on an entire surface of the substrate including the thin-film transistor to have an opening portion for exposing the thin-film transistor; forming a common electrode having a large area at an upper portion of the organic insulating layer, and an auxiliary electrode pattern connected to the thin-film transistor through the opening portion; forming a passivation layer on an entire surface of the substrate including the common electrode and auxiliary electrode pattern to expose the auxiliary electrode pattern connected to the thin-film transistor; and forming a plurality of pixel electrodes and electrically connected to the thin-film transistor through the exposed auxiliary electrode pattern, and overlapped with the common electrode at an upper portion of the passivation layer.

According to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same in accordance with the present invention, a drain contact hole in the related art that has been formed to electrically connect a drain electrode to a pixel electrode is removed, and an opening portion for exposing an upper portion of the thin-film transistor is formed on an organic insulating layer such that the exposed thin-film transistor and the pixel electrode are electrically connected to each other in a direct manner, and thus an area that has been used to form a drain contact hole in the related art can be used for an opening area, thereby enhancing the transmittance compared to the related art.

Furthermore, according to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same in accordance with the present invention, a contact hole through which the drain electrode and pixel electrode are electrically connected to each other is formed within the opening portion provided at an upper portion of the thin-film transistor, and thus an area of the drain contact hole can be reduced, thereby increasing the aperture ratio.

As a result, it has a structure in which the pixel electrode is disposed at the uppermost portion, thereby reducing CT and horizontal line due to capacitance between the data line and pixel electrode.

Furthermore, according to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same in accordance with the present invention, an amorphous silicon layer (n+ or p+) and an amorphous silicon layer (a-Si:H) containing foreign substances below a conductive layer portion corresponding to the source electrode and drain electrode and the data line are simultaneously patterned, thereby removing a trouble of causing an active tail.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, an array substrate for a fringe field switching (FFS) mode liquid crystal display device and method for fabricating the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3is a schematic plan view illustrating a fringe field switching (FFS) mode liquid crystal display device according to the present invention.

FIG. 4is an enlarged plan view illustrating a thin-film transistor portion in a fringe field switching (FFS) mode liquid crystal display device according to the present invention.

FIG. 5is a schematic cross-sectional view illustrating a fringe field switching (FFS) mode liquid crystal display device according to the present invention, as a cross-sectional view along the line V-V ofFIG. 4.

A fringe field switching (FFS) mode liquid crystal display device according to an embodiment of the present invention, as illustrated inFIGS. 3 through 5, may include a gate line103formed in one direction on a surface of the transparent insulating substrate101; a common line103bdisposed to be separated from the gate line103; a data line113acrossed with the gate line103to define a pixel region; a thin-film transistor (T) formed at an intersection of the gate line103and data line113a; an organic insulating layer117formed on an entire surface of the substrate including the thin-film transistor (T) to have an opening portion121for exposing the thin-film transistor (T); a common electrode123ahaving a large area formed at an upper portion of the organic insulating layer117, and an auxiliary electrode pattern123bconnected to the thin-film transistor (T) through the opening portion121; a passivation layer127formed on an entire surface of the substrate including the common electrode123aand auxiliary electrode pattern123bto expose the auxiliary electrode pattern123cconnected to the thin-film transistor (T); and a plurality of pixel electrodes133aformed at an upper portion of the passivation layer127, and electrically connected to the thin-film transistor (T) through the exposed auxiliary electrode pattern123c, and overlapped with the common electrode123a.

Here, the common electrode123ais disposed on an entire surface of the pixel region in which the gate line103and data line113aare crossed with each other, and a plurality of transparent rod-shaped pixel electrodes133aseparated from one another are disposed at an upper side of the pixel electrode133aby interposing the passivation layer127therebetween. Here, the common electrode123ais electrically connected to the common line103bdisposed in parallel with the gate line103through a common line connection pattern133bformed during the formation of the pixel electrode133a.

Furthermore, as illustrated inFIG. 5, the pixel electrode133ais connected to the auxiliary electrode pattern123cdirectly connected to a drain electrode113cthrough an opening portion121located at an upper portion of the thin-film transistor (T) without having a separate drain contact hole. Here, the opening portion121is formed to expose the source electrode113band drain electrode113cconstituting the thin-film transistor (T).

Furthermore, a black matrix143for blocking light on the upper substrate141corresponding to a region excluding the pixel region in which the gate line and data line are crossed with each other, and a color filter layer145including a red color filter layer (not shown), a green color filter layer (not shown) and a blue color filter layer (not shown) is formed between the black matrices143. Here, the color filter layer145may be applied with a Color filter On TFT (COT) structure formed on the insulating substrate101instead of the upper substrate141. In other words, the color filter layer145may be formed in the pixel region of the insulating substrate101in which the gate line103and data line113aare crossed with each other.

Moreover, a column spacer147is formed at an upper portion of the color filter layer145to maintain a predetermined cell gap of the liquid crystal display device. Here, the column spacer147may be formed at an upper portion of the insulating substrate101.

Accordingly, in case of the present invention, as illustrated inFIG. 5, the drain contact hole that has been formed in the prior art is removed, and thus the area of a region in which the drain contact hole is removed may be used for an opening region, thereby enhancing the transmittance to the extent.

In addition, a liquid crystal layer151may be formed between the insulating substrate101and upper substrate141to configure a fringe field switching (FFS) mode liquid crystal display device according to the present invention.

Through the foregoing configuration, the plurality of common electrodes123asupply a reference voltage for driving liquid crystals, namely, a common voltage, to each pixel.

The plurality of common electrodes123aare overlapped with the pixel electrode133ahaving a large area by interposing the passivation layer127therebetween at each pixel region to form a fringe field.

In this manner, if a data signal is supplied to the pixel electrode133athrough the thin-film transistor (T), then the common electrode123asupplied by a common voltage forms a fringe field so that liquid crystal molecules aligned in a horizontal direction between the insulating substrate101and the color filter substrate141are rotated by dielectric anisotropy, and thus the light transmittance of liquid crystal molecules passing through a pixel region varies according to the rotational degree, thereby implementing gradation.

According to an array substrate for a fringe field switching (FFS) mode liquid crystal display device in accordance with the present invention, a drain contact hole in the related art that has been formed to electrically connect a drain electrode to a pixel electrode is removed, and an opening portion for exposing an upper portion of the thin-film transistor is formed on a passivation layer such that the exposed thin-film transistor and the pixel electrode are electrically connected to each other in a direct manner, and thus an area that has been used to form a drain contact hole in the related art can be used for an opening area, thereby enhancing the transmittance compared to the related art.

Furthermore, an array substrate for a fringe field switching (FFS) mode liquid crystal display device in accordance with the present invention has a structure in which the pixel electrode is disposed at the uppermost portion, thereby reducing CT and horizontal line due to capacitance between the data line and pixel electrode.

Furthermore, according to an array substrate for a fringe field switching (FFS) mode liquid crystal display device in accordance with the present invention, an amorphous silicon layer (n+ or p+) and an amorphous silicon layer (a-Si:H) containing foreign substances below a conductive layer portion corresponding to the source electrode and drain electrode and the data line are simultaneously patterned, thereby removing a trouble of causing an active tail.

On the other hand, a method of fabricating an array substrate for a fringe field switching (FFS) mode liquid crystal display device having the foregoing configuration according to the present invention will be described below with reference toFIGS. 6A through 6Q.

FIGS. 6A through 6Qare fabrication process cross-sectional views illustrating an array substrate for a fringe field switching (FFS) mode liquid crystal display device according to the present invention.

As illustrated inFIG. 6A, a plurality of pixel regions including a switching function are defined on a transparent insulating substrate101, and a first conductive metal layer102is deposited on the transparent insulating substrate101by a sputtering method. In this case, at least one selected from the group consisting of aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), moly-tungsten (MoW), moly-titanium (MoTi), copper/moly-titanium (Cu/MoTi) may be used for a target material for forming the first conductive metal layer102. In this case, the first conductive metal layer102may be formed with a structure having at least one layer.

Next, a photoresist having a high transmittance is deposited at an upper portion of the first conductive metal layer102to form a first photosensitive layer105.

Subsequently, as illustrated inFIG. 6B, an exposure process is carried out on the first photosensitive layer105through a photolithography process technology using an exposure mask (not shown), and then the first photosensitive layer105is selectively removed through a development process to form a first photosensitive pattern105a.

Next, as illustrated inFIG. 6C, the first conductive metal layer102is selectively etched by using the first photosensitive pattern105aas a blocking layer to form a gate line103(refer toFIG. 3), a gate electrode103aextended from the gate line103, and a common line103bseparated from and in parallel with the gate line103at the same time.

Subsequently, the first photosensitive pattern105ais removed, and then a gate insulating layer107made of silicon nitride (SiNx) or silicon oxide (SiO2) is formed on an entire surface of the substrate including the gate electrode103a.

Next, as illustrated inFIG. 6D, amorphous silicon layer (a-Si:H)109and amorphous silicon layer (n+ or p+)111containing impurities are sequentially deposited on the gate insulating layer107. At this time, the amorphous silicon layer (a-Si:H)109and amorphous silicon layer (n+ or p+)111containing impurities are deposited using a Chemical Vapour Deposition (CVD) method. At this time, an oxide-based semiconductor material such as IGZO instead of amorphous silicon layer (a-Si:H)109may be formed on the gate insulating layer107.

Subsequently, a second conductive metal layer113is deposited on an entire surface of the substrate including the amorphous silicon layer (n+ or p+)111containing impurities using a sputtering method. At this time, at least one selected from the group consisting of aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), moly-tungsten (MoW), moly-titanium (MoTi), copper/moly-titanium (Cu/MoTi) may be used for a target material for forming the second conductive metal layer113.

Subsequently, though not shown in the drawing, a photoresist having a high transmittance is deposited at an upper portion of the second conductive metal layer113to form a second photosensitive layer (not shown).

Next, an exposure process is carried out on the second photosensitive layer (not shown) through a photolithography process technology using an exposure mask (not shown), and then the second photosensitive layer (not shown) is selectively removed through a development process to form a second photosensitive pattern115.

Subsequently, as illustrated inFIG. 6E, the second conductive layer113is selectively etched by using the second photosensitive pattern115as an etching mask to define a source electrode and drain electrode formation region (not shown) together with the data line113acrossed with the gate line103in a vertical direction.

Next, subsequently, a portion of the second conductive layer113corresponding to the source electrode and drain electrode formation region (not shown) and the amorphous silicon layer (n+ or p+)111containing impurities and amorphous silicon layer (a-Si:H)109below the data line113aare sequentially etched through an etching process to form an ohmic contact layer111aand an active layer109a. At this time, a portion of the second conductive layer113corresponding to the source electrode and drain electrode formation region (not shown) and the amorphous silicon layer (n+ or p+)111containing impurities and amorphous silicon layer (a-Si:H)109below the data line113aare patterned at the same time, thereby removing a trouble of causing an active tail.

Subsequently, as illustrated inFIG. 6E, a first passivation layer116and an organic insulating layer117are sequentially deposited on an entire surface of the substrate including the active layer109aand ohmic contact layer111a, a portion of the second conductive metal layer113corresponding to the source electrode and drain electrode formation region (not shown) and data line113a. At this time, an inorganic insulating material made of silicon nitride (SiNx) or silicon oxide (SiO2) is deposited for the first passivation layer116. Furthermore, a photo acryl material or other photosensitive organic insulating materials exhibiting photosensitivity may be used for the organic insulating layer117. Furthermore, since the photo acryl exhibits photosensitivity, an exposure process can be carried out without forming a separate photoresist during the exposure process. At this time, an inorganic insulating material may be used instead of the organic insulating layer117.

Next, as illustrated inFIG. 6F, an exposure process is carried out on the organic insulating layer117through a photolithography process technology using an exposure mask (not shown), and then the organic insulating layer117is selectively removed through a development process to form an organic insulating layer pattern117afor exposing an upper portion of the second metal conductive layer113and an upper portion of the common line103bcorresponding to the source electrode and drain electrode formation region (not shown).

Subsequently, as illustrated inFIG. 6G, a portion of the first passivation layer116disposed at an upper portion of the second metal conductive layer113and an upper portion of the common line103bcorresponding to the source electrode and drain electrode formation region (not shown) is selectively etched using the organic insulating layer pattern117aas an etching mask to form a first opening portion121aand a second opening portion121b. At this time, a thin-film transistor (T) formation portion, namely, the source electrode and drain electrode formation region is exposed to the outside through the first opening portion121a. Furthermore, the common line103bis exposed to the outside through the second opening portion121b.

Next, as illustrated inFIG. 6H, a transparent conductive material is deposited at an upper portion of the organic insulating layer117including the first and the second opening portion121a,121busing a sputtering method to form a first transparent conductive material layer123. At this time, any one composition target selected from a transparent conductive material group including Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), and the like is used for the transparent conductive material. Furthermore, the first transparent conductive material layer123is directly brought into contact with a surface of the conductive layer113corresponding to the source electrode and drain electrode formation region (not shown).

Next, a photoresist having a high transmittance is deposited at an upper portion of the first transparent conductive material layer123to form a third photosensitive layer125.

Next, as illustrated inFIG. 6I, an exposure process is carried out through a photolithography process technology using an exposure mask (not shown), and then the exposed third photosensitive layer125is selectively removed to form a third photosensitive pattern125a. At this time, an upper surface of the first transparent conductive material layer123at an upper portion of the channel region of the thin-film transistor is exposed to the outside.

Subsequently, as illustrated inFIG. 6J, the exposed first transparent conductive material layer123, the second conductive metal layer113thereunder and the ohmic contact layer111aare sequentially etched using the third photosensitive pattern125aas an etching mask, thereby forming the source electrode113band drain electrode113cseparated from each other while at the same time forming the common electrode123ahaving a large area, a dummy pattern123band an auxiliary electrode pattern123c. At this time, the ohmic contact layer111amay be also etched and separated therefrom, and thus a channel region (not shown) of the active layer109alocated at a lower portion thereof is exposed to the outside. Furthermore, the auxiliary electrode pattern123cis directly connected to the drain electrode113c, and the dummy pattern123bis directly connected to the source electrode113b. At this time, the dummy pattern123bis connected to only the source electrode113b, and thus a separate etching is not required.

Next, as illustrated inFIG. 6K, the third photosensitive pattern125ais removed, and then an inorganic insulating material or organic insulating material is deposited on an entire surface of the substrate to form a second passivation layer127, and then a photoresist having a high transmittance is coated at an upper portion of the second passivation layer127to form a fourth photosensitive layer129.

Subsequently, as illustrated inFIG. 6L, an exposure and development process is carried out by a photolithography process technology using an exposure mask (not shown) to remove the fourth photosensitive layer129to form a fourth photosensitive layer pattern129a.

Next, as illustrated inFIG. 6M, the second passivation layer127is selectively etched using the fourth photosensitive layer pattern129aas an etching mask to form a pixel electrode contact hole131a, a common electrode contact hole131band a common line contact hole131cfor exposing the auxiliary electrode pattern123c, common electrode123aand common line103b, respectively.

Subsequently, as illustrated inFIG. 6N, the fourth photosensitive layer pattern129ais removed, and then a transparent conductive material is deposited at an upper portion of the second passivation layer127including the pixel electrode contact hole131a, common electrode contact hole131band common line contact hole131cusing a sputtering method to form a second transparent conductive material layer133. At this time, any one composition target selected from a transparent conductive material group including Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), and the like is used for the transparent conductive material.

Next, a photoresist having a high transmittance is deposited at an upper portion of the second transparent conductive material layer133to form a fifth photosensitive layer135.

Subsequently, as illustrated inFIG. 6O, an exposure process is carried out on the fifth photosensitive layer135through a photolithography process technology using an exposure mask (not shown), and then the fifth photosensitive layer135is selectively removed through a development process to form a fifth photosensitive layer pattern135a.

Next, as illustrated inFIG. 6P, the second transparent conductive material layer133is selectively etched using the fifth photosensitive layer pattern135aas an etching mask to form a plurality of pixel electrodes133aconnected to the auxiliary electrode pattern123cand separated from one another as well as the common connection pattern133bfor electrically connecting the common electrode123aand common line103bthrough the common electrode131band common line contact hole131cat the same time. At this time, the pixel electrode133ais connected to the auxiliary electrode pattern123cand thus as a result, electrically connected to the drain electrode113c.

Subsequently, though not shown in the drawing, the remaining fifth photosensitive layer pattern135ais removed, and then a process of forming an alignment layer (not shown) on an entire surface of the substrate is additionally carried out, thereby completing a fabrication process of an array substrate for a fringe field switching (FFS) mode liquid crystal display device according to the present invention.

Then, as illustrated inFIG. 6Q, a black matrix143for blocking light is formed on the upper substrate141corresponding to a region excluding the pixel region in which the gate line103and data line113aare crossed with each other.

Next, a color filter layer145including a red color filter layer (not shown), a green color filter layer (not shown) and a blue color filter layer (not shown) is formed between the black matrices143. Here, the color filter layer145may be applied with a Color filter On TFT (COT) structure formed on the insulating substrate101instead of the upper substrate141. In other words, the color filter layer145may be formed in the pixel region of the insulating substrate101in which the gate line103and data line113aare crossed with each other in the process prior to forming the first passivation layer116.

Subsequently, a column spacer147is formed at an upper portion of the color filter layer145to maintain a predetermined cell gap of the liquid crystal display device. Here, the column spacer147may be formed at an upper portion of the insulating substrate101.

Accordingly, in case of the present invention, the drain contact hole that has been formed in the prior art is removed, and thus the area of a region in which the drain contact hole is removed may be used for an opening region, thereby enhancing the transmittance to the extent.

Next, a process of forming an alignment layer (not shown) on an entire surface of the upper substrate141is added thereto to complete the process of fabricating a color filter array substrate.

Then, a liquid crystal layer151is formed between the insulating substrate101and upper substrate141, thereby completing the process of fabricating a fringe field switching (FFS) mode liquid crystal display device according to the present invention.

As described above, according to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same in accordance with the present invention, a drain contact hole in the related art that has been formed to electrically connect a drain electrode to a pixel electrode is removed, and an opening portion for exposing an upper portion of the thin-film transistor is formed on an organic insulating layer such that the exposed thin-film transistor and the pixel electrode are electrically connected to each other in a direct manner, and thus an area that has been used to form a drain contact hole in the related art can be used for an opening area, thereby enhancing the transmittance compared to the related art.

Furthermore, according to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same in accordance with the present invention, a contact hole through which the drain electrode and pixel electrode are electrically connected to each other is formed within the opening portion provided at an upper portion of the thin-film transistor, and thus an area of the drain contact hole can be reduced, thereby increasing the aperture ratio.

Accordingly, it has a structure in which the pixel electrode is disposed at the uppermost portion, thereby reducing CT and horizontal line due to capacitance between the data line and pixel electrode.

In addition, according to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and a method for fabricating the same in accordance with the present invention, an amorphous silicon layer (n+ or p+) and an amorphous silicon layer (a-Si:H) containing foreign substances below a conductive layer portion corresponding to the source electrode and drain electrode and the data line are simultaneously patterned, thereby removing a trouble of causing an active tail.

Although the preferred embodiments of the present invention have been described in detail, it should be understood by those skilled in the art that various modifications and other equivalent embodiments thereof can be made.

Consequently, the rights scope of the present invention is not limited to the embodiments and various modifications and improvements thereto made by those skilled in the art using the basic concept of the present invention as defined in the accompanying claims will fall in the rights scope of the invention.