Flash memory cell and fabricating method thereof

A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 93123057, filed on Aug. 2, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile memory and fabricating method thereof. More particularly, the present invention relates to a flash memory cell and fabricating method thereof.

2. Description of the Related Art

Flash memory is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. The stored data will be retained even after power to the device is removed. With these advantages, flash memory has become one of the most widely adopted non-volatile memories for personal computer and electronic equipment.

A typical flash memory has a floating gate and a control gate fabricated using doped polysilicon. To program data into or erase data from a flash memory cell, an appropriate bias voltage is applied to the source region, the drain region and the control gate respectively so that electrons are injected into the floating gate or withdrawn from the floating gate. The most common mode for injecting electrons into a flash memory cell includes the channel hot-electron injection (CHEI) mode and the Fowler-Nordheim tunneling mode. In general, the types of programming and erasing operations carried out on the memory devices depend on the ways the electrons are injected or pulled out.

FIG. 1is a schematic cross-sectional view showing a single memory cell of a conventional flash memory. The flash memory cell mainly includes an n-type substrate100, a deep p-type well102, an n-type well104, a stacked gate structure106, an n-type source region108a, an n-type drain region108b, a p-type shallow doped region109, a p-type deep doped region110and a conductive plug112. The deep p-type well102is disposed in the substrate100and the n-type well104is disposed within the deep p-type well102. The stacked gate structure106is disposed on the substrate100. The stacked gate structure106includes a tunneling layer114, a floating gate116, a gate dielectric layer118and a control gate120sequentially stacked over the substrate100. The n-type source region108aand the n-type drain region108bare disposed in the n-type well104and the p-type deep doped region110on each side of the stacked gate structure106. The p-type shallow doped region109is disposed in the n-type well104underneath the stacked gate structure106. The p-type deep doped region110is disposed within the n-type well104on one side of the stacked gate structure106but adjacent to the p-type shallow doped region109. The conductive plug112in the substrate100extends downward to pass through the n-type drain region108band connect with a portion of the p-type deep doped region110.

To program data into the aforementioned flash memory cell, a bias voltage is applied to the source region, the drain region and the control gate respectively. However, the control gate and the source region of the memory cell are also connected to the control gate and the source region of a neighboring memory cell. That is, two memory cells share a common word line and source line. Consequently, a voltage applied to select one particular memory cell may interfere with other non-selected memory cells on the same word line leading to reliability problems in the memory devices.

In addition, the disposition of the control gate and the source region close to each other may increase the probability of having a leaky device when a flash memory cell is programmed.

Furthermore, the aforementioned programming operation may cause the flash memory cell to be over-programmed, thereby leading to subsequent read-out problems. Due to the restriction imposed by the over-programming problems, the operable threshold voltage range of the device is severely compressed. In other words, the flash memory cell is limited to the storage of a single data bit.

SUMMARY OF THE INVENTION

Accordingly, at least one objective of the present invention is to provide a flash memory cell capable of reducing the effect of a voltage applied to a flash memory cell from affecting a neighboring memory cell in a flash memory cell programming operation.

At least a second objective of the present invention is to provide a method of fabricating and operating a flash memory cell capable of improving the reliability of the device.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a flash memory cell. The flash memory cell includes a first conductive type deep well, a second conductive type well, a stacked gate structure, a second conductive type source region, a second conductive type drain region, a select gate, a first gate dielectric layer, a second gate dielectric layer, a first conductive type shallow doped region, a first conductive type deep doped region and a conductive plug. The first conductive type deep well is disposed in the substrate and the second conductive type well is disposed within the first conductive type deep well. The stacked gate structure is disposed on the substrate. The stacked gate structure includes a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the substrate. The second conductive type source region and the second conductive type drain region are disposed in the substrate on each side of the stacked gate structure. The select gate is disposed between the stacked gate structure and the second conductive type source region. The first gate dielectric layer is disposed between the select gate and the stacked gate structure. The second gate dielectric layer is disposed between the select gate and the substrate. The first conductive type shallow doped region is disposed in the second conductive type well underneath the stacked gate structure and the select gate. The second conductive type source region is disposed in the first conductive type shallow doped region. The first conductive type deep doped region is disposed in the second conductive type well on one side of the stacked gate structure but adjacent to the first conductive type shallow doped region. The second conductive type drain region is disposed in the first conductive type deep doped region. The conductive plug is disposed within the substrate. The conductive plug extends downward to pass through the second conductive type drain region and ends up with a portion inside the first conductive type deep doped region.

Because a select gate is deployed in the flash memory cell of the present invention, problems due to device leakage or over-programming in a conventional programming operation are effectively eliminated. Furthermore, programming a flash memory cell will no longer affect a neighboring flash memory cell. Hence, overall reliability of the memory device is improved. In addition, each flash memory cell can be used as a multi-bit storage cell.

The present invention also provides a method of fabricating a flash memory cell. First, a second conductive type deep well is formed in a first conductive type substrate and then a first conductive type well is formed in the second conductive type deep well. Thereafter, a second conductive type shallow doped region is formed in the first conductive type well. The shallow doped well is adjacent to the surface of the substrate. Next, a stacked gate structure is formed over the substrate. The stacked gate structure includes a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially formed over the substrate. A gate dielectric layer is formed between the stacked gate structure and the substrate. After that, a select gate is formed on one sidewall of the stacked gate structure. A deep doped region is formed in the substrate on the other side of the stacked gate structure. The deep doped region and the shallow doped region are adjacent to each other. Thereafter, a source region and a drain region are formed on each side of the select gate and the stacked gate structure respectively. The source region is formed in the substrate on one side of the select gate and the drain region is formed in the substrate on one side of the stacked gate structure. A dielectric layer is formed over the substrate to cover the stacked gate structure and the substrate. A contact opening is formed in the dielectric layer to expose a portion of the drain region and the deep doped region. Finally, a conductive plug is formed in the contact opening.

Because a select gate is deployed in the flash memory cell of the present invention, problems due to device leakage or over-programming in a conventional programming operation are effectively eliminated. Furthermore, the processes for forming the memory cell according to the present invention are compatible with the convention fabricating method. Hence, there is no need to purchase special equipment.

The present invention also provides a method of operating a flash memory cell. The operating method is suitable for operating the aforementioned flash memory cell. The operating method includes the following rules. To program data into the flash memory cell, a first positive voltage is applied to the source region and the drain region, a first negative voltage is applied to the control gate. Both the select gate and the first conductive type deep well are set to 0V. To erase data from the flash memory cell, a second positive voltage is applied to the control gate and a second negative voltage is applied to the source region and the first conductive type deep well. The drain region is maintained in a floating state and the select gate is set to 0V. To read data from the flash memory cell, a third positive voltage is applied to the source region and a fourth positive voltage is applied to the control gate and the select gate. The first conductive type deep well is set to 0V.

Because of the select gate inside the flash memory cell of the present invention, problems due to device leakage or over-programming in a conventional programming operation are effectively eliminated. Furthermore, programming a flash memory cell will no longer affect a neighboring flash memory cell. Hence, overall reliability of the memory device is improved. In addition, each flash memory cell can be used as a multi-bit storage cell.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following embodiment, the first conductive type is in an n-doped state and the second conductive type is in a p-doped stage. However, anyone familiar with the technique may interchange the doping conditions said above. In the following, only one set of dopant types is described in detail. In addition, a NOR type flash memory cell array having common source region is used in the following description.

FIGS. 2A through 2Care schematic cross-sectional views showing the steps for fabricating a flash memory cell according to one preferred embodiment of the present invention. As shown inFIG. 2A, a substrate200such as an n-type substrate is provided and then a p-type deep well202is formed in the substrate200. Thereafter, an n-type well204is formed within the p-type deep well202. A p-type shallow doped region206is formed in the n-type well204adjacent to the substrate200. The p-type deep well202, the n-type well204and the p-type shallow doped region206are formed, for example, by performing an ion implantation.

Thereafter, a stacked gate structure208is formed over the substrate200. The stacked gate structure208includes a tunneling layer210, a floating gate212, an inter-gate dielectric layer214and a control gate216sequentially formed over the substrate200. The stacked gate structure208is formed, for example, by sequentially forming a tunneling material layer (not shown), a floating gate material layer (not shown), an inter-gate dielectric material layer (not shown) and a control gate material layer (not shown) over the substrate200and then performing a photolithographic and etching process. The floating gate and the control gate are fabricated using doped polysilicon, for example. Since the process and related parameters for forming the stacked gate structure208should be familiar to those skilled in the art of semiconductor production, a detail description of these steps is omitted.

Thereafter, a gate dielectric layer218is formed between the stacked gate structure208and the substrate200. The gate dielectric layer218is a silicon oxide layer formed by performing a chemical vapor deposition process, for example. After that, a conductive material layer220is formed over the gate dielectric layer218. The conductive material layer220is a doped polysilicon layer or other suitable conductive material layer formed by performing a chemical vapor deposition process, for example.

As shown inFIG. 2B, a self-aligned etching process is carried out to form a pair of conductive spacers220aon the sidewalls of the stacked gate structure208. The self-aligned etching process is an anisotropic etching process, for example. Thereafter, one of the conductive spacers220aon the sidewalls of the stacked gate structure208and then the gate dielectric layer218not covered by the conductive spacer220aare removed to form the asymmetrical sidewall structure. It should be noted that the retained conductive spacer220ais disposed on the same side as a subsequently formed source region. The conductive spacer220ais subsequently used as a select gate.

Thereafter, a p-type deep doped region222is formed in the n-type well204on one side of the stacked gate structure208. The p-type deep doped region222is adjacent to the p-type shallow doped region206. The p-type deep doped region222is formed, for example, by performing an ion implantation. It should be noted that the p-type deep doped region222is disposed on the same side as a subsequently formed drain region.

As shown inFIG. 2C, an n-type source region224aand an n-type drain region224bare formed on each side of the select gate220aand the stacked gate structure208. The n-type source region224ais formed across the p-type shallow doped region206and extend to the n-type substrate200on one side of the select gate220a. For a NOR type flash memory cell array, every pair of neighboring stacked gate structures208uses a common n-type source region224a. The n-type drain region224bis formed in the p-type deep doped region222on another side of the stacked gate structure208. The n-type source region224aand the n-type drain region224bare formed in an ion implantation, for example.

A dielectric layer226is formed over the substrate200to cover the stacked gate structure208and the substrate200. Thereafter, a contact opening228is formed in the dielectric layer226to expose a portion of the drain region224band the p-type deep doped region222. The dielectric layer226is fabricated using silicon oxide, silicon oxynitride or other suitable material. The method of forming the dielectric layer226includes depositing a dielectric material layer over the substrate200and then performing a photolithographic and etching process to define the contact opening228.

After removing the drain region224band a portion of the deep doped region222inside the contact opening228, a conductive material is deposited into the contact opening228to form a conductive plug230. It should be noted that the conductive plug230shorts the drain region224band the deep doped region222together. The conductive plug230is fabricated using tungsten or other suitable conductive material, for example. The method of forming the conductive plug230includes, for example, depositing a conductive material into the contact opening228and performing a chemical-mechanical polishing to remove excess material outside the opening228.

Because a select gate is deployed in the flash memory cell of the present invention, problems due to device leakage or over-programming in a conventional programming operation are effectively eliminated. Furthermore, the processes for forming the memory cell according to the present invention are compatible with the convention fabricating method. Hence, there is no need to purchase special equipment.

FIG. 3is a schematic cross-sectional view of a flash memory cell according to one preferred embodiment of the present invention. As shown inFIG. 3, the flash memory cell mainly includes a substrate300, a stacked gate structure302, an n-type source region304a, an n-type drain region304b, a select gate306, a gate dielectric layer308, a p-type shallow doped region310, a p-type deep doped region312, a conductive plug314, an n-type well316and a p-type deep well318.

The p-type deep well318is disposed in the substrate300and the n-type well316is disposed within the p-type deep well318. The stacked gate structure302is disposed on the substrate300. The stacked gate structure302includes a tunneling layer320, a floating gate322, an inter-gate dielectric layer324and a control gate326sequentially stacked over the substrate300. The floating gate322and the control gate326are fabricated from doped polysilicon, for example. In addition, the n-type source region304aand the n-type drain region304bare disposed in the substrate300on each side of the stacked gate structure302.

Furthermore, the select gate306is disposed between the stacked gate structure302and the n-type source region304asuch that the select gate306backs on one of the sidewalls of the stacked gate structure302above a portion of the substrate300. The select gate306is fabricated from doped polysilicon, for example. The gate dielectric layer308is disposed between the select gate306and the stacked gate structure302and between the select gate306and the substrate300. The gate dielectric layer308is a silicon oxide layer, for example.

The p-type shallow doped region310is disposed in the n-type well316underneath the stacked gate structure302and the select gate306, wherein the n-type source region304ais disposed in the p-type shallow doped region310. In addition, the p-type deep doped region312is disposed in the n-type well316on one side of the stacked gate structure302but adjacent to the p-type shallow doped region310, wherein the n-type drain region304bis disposed in the p-type deep doped region312. The conductive plug314is disposed in the substrate300such that the conductive plug314extends downward passing through the n-type drain region304band ends up with a portion buried in the p-type deep doped region312. Hence, the drain region304band the deep doped region312are shorted together through the conductive plug314.

Because of the select gate inside the flash memory cell of the present invention, problems due to device leakage or over-programming in a conventional programming operation are effectively eliminated. Furthermore, programming a flash memory cell will no longer affect a neighboring flash memory cell. Hence, overall reliability of the memory device is improved. In addition, each flash memory cell can be used as a multi-bit storage cell.

In the following, the operating modes of a NOR type flash memory cell array in programming, erasing and reading are described.FIG. 4is an equivalent circuit diagram of a NOR type flash memory cell array. Table 1 below lists out all the actual bias voltages used in operating the flash memory cell array. However, the values in Table 1 is used as an illustration only and should by no means limit the scope of the present invention.

As shown inFIG. 4, a plurality of memory cells Qn1˜Qn8are aligned to form a 4*2 array. InFIG. 4, the selected word lines WL and the non-selected word lines WLxlinking the control gate of the vertical memory cells are also shown. In the present embodiment, the selected word lines WL connect the control gates in the same memory cell column such as the memory cells Qn3and Qn4. The non-selected word lines WLxconnect the control gates in the same memory cell column such as Qn1and Qn2(or memory cells Qn5and Qn6, Qn7and Qn8). Similarly, the selected select gate line SG and the non-selected select gate lines SGxconnect the same memory cell column. In the present embodiment, the selected select gate line SG connects the select gate of the memory cells in the same column such as Qn3and Qn4. The non-selected gate lines SGxconnect the select gates in the same memory cell column such as Qn1and Qn2(or memory cells Qn5and Qn6, Qn7and Qn8). The source line SL connects the source region in the same memory cell column, and the pair of neighboring memory cells in the same row uses the same source line SL. In the present embodiment, the source line SL connects the source region of the memory cells in the same column such as Qn3and Qn4. Furthermore, the pair of neighboring memory cells in the same row such as Qn1and Qn3uses the same source line SL. The selected bit lines SBL and the non-selected bit lines SBLxconnect the drain region in the same memory cell column. In the present embodiment, the select bit line SBL connects the drain of the memory cells in the same memory cell row such as Qn1, Qn3, Qn5and Qn7. Similarly, the non-selected bit line SBLxconnects the drain of the memory cells in the same memory cell row such as Qn2, Qn4, Qn6and Qn8.

As shown inFIGS. 3 and 4and Table 1, to program data into a flash memory cell (for example, Qn3), a positive voltage is applied to the source region304aand the drain region304band a negative voltage is applied to the control gate326. Both the select gate306and the deep p-type well318are set to 0V so that electric charges are induced to leave the floating gate322through F-N tunneling effect. During the programming operation, the voltage of the control gate, the bit line and the select gate of neighboring memory cells are set to 0V. In one preferred embodiment, the positive voltage is a voltage between 1 to 20V and the negative voltage is a voltage between −1 to −20V. In the present embodiment, the positive voltage is 6V while the negative voltage is −10V.

To erase data from a flash memory (for example, Qn3), a positive voltage is applied to the control gate326and a negative voltage is applied to the source region304aand the deep p-type well318. The select gate306is set to 0V and the drain region304bis set to a floating state so that electric charges are induced to enter the floating gate322through F-N tunneling effect. During the erasing operation, the same negative voltage applied to the source region304aand the deep p-type well318is applied to the control gate of neighboring memory cells while the bit line is set to a floating state and the select gate is set to 0V. In one preferred embodiment, the positive voltage is a voltage between 1 to 20V and the negative voltage is a voltage between −1 to −20V. In the present embodiment, the positive voltage is 10V while the negative voltage is −6V.

To read data from a flash memory (for example, Qn3), a first positive voltage is applied to the source region304aand a second positive voltage is applied to the control gate326and the select gate306. The drain region304band the deep p-type well318are set to 0V. During the reading operation, the control gate, the bit line and select gate of neighboring memory cells is set to 0V. In one preferred embodiment, the first positive voltage is a voltage between 1 to 15V and the second positive voltage is a voltage between 1 to 15V. In the present invention, the first positive voltage is 1.65 and the second positive voltage is 3.3V.

In the presence of a select gate inside the flash memory cell, the unexpected programming on non-selected cells in a programming operation will be alleviated. This is mainly because the voltage of the common source region is blocked by the select gate to avoid electrons in the floating gates being drain out. In other words, reliability of the memory device is improved.

Furthermore, for a single flash memory cell having a select gate between the control gate and the source region, device leakage during a programming operation is no longer a serious problem. Moreover, with the problem of over-programming a flash memory resolved, the present invention also eliminates read-out errors.

In addition, a programmed memory cell can have a larger threshold voltage window because a select gate is disposed between the control gate and the source region. As a result, the flash memory cell of the present invention can also be modified to serve as a multi-bit storage cell.