SYSTEMS AND METHODS FOR OSCILLATOR CALIBRATOR FOR INVERTER FOR ELECTRIC VEHICLE

A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a clock reference signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to align a clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller.

TECHNICAL FIELD

Various embodiments of the present disclosure relate generally to systems and methods for an oscillator calibrator for an inverter for an electric vehicle, and, more particularly, to systems and methods for an oscillator calibrator for a power switch for an inverter for an electric vehicle.

BACKGROUND

Inverters, such as those used to drive a motor in an electric vehicle, for example, are responsible for converting High Voltage Direct Current (HVDC) into Alternating Current (AC) to drive the motor. In an inverter, disparities in oscillator frequencies can contribute to the inefficiencies of the inverter.

SUMMARY OF THE DISCLOSURE

In some aspects, the techniques described herein relate to a system including: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a clock reference signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to align a clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller.

In some aspects, the techniques described herein relate to a system, wherein the low voltage phase controller includes a clock reference sampler configured to align the clock reference signal of the low voltage phase controller with a clock reference signal of an inverter controller.

In some aspects, the techniques described herein relate to a system, wherein the low voltage phase controller includes a clock reference sampler configured to align the clock reference signal of the low voltage phase controller with a clock reference signal of an inverter controller when the clock reference signal of the inverter controller is available, and with a clock reference signal of another low voltage phase controller when the clock reference signal of the inverter controller is unavailable.

In some aspects, the techniques described herein relate to a system, wherein the inverter further includes a point-of-use phase controller in the high voltage area, the point-of-use phase controller configured to align a clock reference signal of the point-of-use phase controller with the clock reference signal of the high voltage phase controller.

In some aspects, the techniques described herein relate to a system, wherein the low voltage phase controller includes a clock reference sampler configured to align the clock reference signal of the low voltage phase controller with a primary clock reference signal by counting a number of system clock pulses in one or more periods of the primary clock reference signal and comparing the counted number to an expected value.

In some aspects, the techniques described herein relate to a system, wherein the low voltage phase controller includes a clock calibrator configured to increase or decrease a period of an internal oscillator of the low voltage phase controller to align the counted number to the expected value.

In some aspects, the techniques described herein relate to a system, wherein the high voltage phase controller includes a clock reference sampler configured to align the clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller by counting a number of system clock pulses in one or more periods of the clock reference signal of the low voltage phase controller and comparing the counted number to an expected value.

In some aspects, the techniques described herein relate to a system, further including: the battery configured to supply the DC power to the inverter; and the motor configured to receive the AC power from the inverter to drive the motor.

In some aspects, the techniques described herein relate to a system including: a power module for an inverter for an electric vehicle, the power module including: a power switch including a drain terminal, a source terminal, and a gate terminal; a gate driver configured to provide a signal to the gate terminal to control an operation of the power switch; and a point-of-use phase controller configured to align a clock reference signal of the point-of-use phase controller with a clock reference signal of a high voltage phase controller, and control the gate driver based on the clock reference signal of the point-of-use phase controller.

In some aspects, the techniques described herein relate to a system, wherein the point-of-use phase controller is configured to align the clock reference signal of the point-of-use phase controller with the clock reference signal of the high voltage phase controller by counting a number of system clock pulses in one or more periods of the clock reference signal of the high voltage phase controller and comparing the counted number to an expected value.

In some aspects, the techniques described herein relate to a system, wherein the point-of-use phase controller is further configured to increase or decrease a period of an internal oscillator of the point-of-use phase controller to align the counted number to the expected value.

In some aspects, the techniques described herein relate to a system, wherein the point-of-use phase controller is further configured to iteratively perform the alignment of the oscillator of the point-of-use phase controller with the clock reference signal of the high voltage phase controller so that successive counts of the number of system clock pulses brings the oscillator of the point-of-use phase controller into alignment with the clock reference signal of the high voltage phase controller.

In some aspects, the techniques described herein relate to a system, wherein the point-of-use controller is configured to align the clock reference signal of the point-of-use phase controller with the clock reference signal of the high voltage phase controller using a command bus for an initial alignment after initialization of the point-of-use controller, and using a message bus for subsequent alignments after the initial alignment.

In some aspects, the techniques described herein relate to a system, wherein the clock reference signal of a high voltage phase controller has a frequency from approximately 100 Hz to approximately 10 kHz.

In some aspects, the techniques described herein relate to a system including: a first controller configured to: receive a clock reference signal of a primary controller; align an oscillator of the first controller with the clock reference signal of the primary controller; and provide a reference signal to a second controller based on a clock reference signal of the aligned oscillator of the first controller.

In some aspects, the techniques described herein relate to a system, wherein the first controller is further configured to count a number of system clock pulses in one or more periods of the clock reference signal of the primary controller, and compare the counted number to an expected value to align the oscillator of the first controller with the clock reference signal of the primary controller.

In some aspects, the techniques described herein relate to a system, wherein the first controller is further configured to increase or decrease a period of the oscillator of the first controller to align the counted number to the expected value to align the oscillator of the first controller with the clock reference signal of the primary controller.

In some aspects, the techniques described herein relate to a system, wherein the first controller is further configured to iteratively perform the alignment of the oscillator of the first controller with the clock reference signal of the primary controller so that successive counts of the number of system clock pulses brings the oscillator of the first controller into alignment with the clock reference signal of the primary controller.

In some aspects, the techniques described herein relate to a system, wherein the first controller is configured to provide the reference signal to the second controller upon alignment of the oscillator of the first controller with the clock reference signal of the primary controller.

In some aspects, the techniques described herein relate to a system, wherein the reference signal to the second controller is a defined number of clock pulses of the oscillator of the first controller for a defined period of time.

DETAILED DESCRIPTION OF EMBODIMENTS

The terminology used below may be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. For example, in the context of the disclosure, the switching devices may be described as switches or devices, but may refer to any device for controlling the flow of power in an electrical circuit. For example, switches may be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), or relays, for example, or any combination thereof, but are not limited thereto.

Various embodiments of the present disclosure relate generally to systems and methods for an oscillator calibrator for an inverter for an electric vehicle, and, more particularly, to systems and methods for an oscillator calibrator for a power switch for an inverter for an electric vehicle.

Inverters, such as those used to drive a motor in an electric vehicle, for example, are responsible for converting High Voltage Direct Current (HVDC) into Alternating Current (AC) to drive the motor. A three phase inverter may include a bridge with six power device switches (for example, power transistors such as IGBT or MOSFET) that are controlled by Pulse Width Modulation (PWM) signals generated by a controller. An inverter may include three half-H bridge switches to control the phase voltage, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate drivers. The PWM controller may generate signals to define the intended states of the system. The gate drivers may send the signals from the PWM controller to the half-H bridge switches. The half-H bridge switches may drive the phase voltage. The inverter may include an isolation barrier between low voltage and high voltage planes. Signals may pass from the PWM controller to the half-H bridge switches by passing across the isolation barrier, which may employ optical, transformer-based, or capacitance-based isolation. PWM signals may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. PWM signals may be distorted when passing through the gate driver, due to the galvanic isolation barrier and other delays within the gate driver. PWM signals may be distorted when the signals processed by the half-H switch via the gate driver output.

Gate drivers may tolerate common-mode transients that occur during field-effect transistor (FET) switching and when one side of the floating high voltage terminal is shorted to ground or subject to an electro-static discharge. These voltage transients may result in fast edges, which may create bursts of common-mode current through the galvanic isolation. A gate driver may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

Gate drivers may have a high-voltage domain in common to the voltage plane of an associated FET. Further, high-voltage planes may be supplied by a flyback converter that may be isolated through a transformer from the low-voltage plane. The high-voltage domain supply may be used to power circuits which source and sink gate current to drive the FET and which may detect FET faults so the faults can be acted upon and/or communicated to the low-voltage domain. Gate drivers may include a galvanic channel dedicated to FET commands, and one or more bidirectional or unidirectional galvanic channels dedicated to FET communications.

High current switching transients may create strong electro-magnetic (EM) fields that may couple into nearby metal traces. The magnitude and frequency of coupled currents may depend upon the layout of the FET packaging solution and the direction and length of metal traces between the FET and the control integrated circuit (IC). For example, typical values for coupled currents may be up to 1 A at AC frequencies up to 100 MHz. Typically, within a circuit, the gate driver IC may be placed far enough away from the FET that high EM fields do not couple directly into the internal metal traces within the gate driver IC. The gate driver is placed a distance from EM fields such that induced currents within the circuitry are below levels that will cause malfunction of the gate driver, or a metal shield is placed between the gate driver and the source of EM fields to protect the gate driver circuitry. The output terminals of the gate driver that connect to the FET are exposed to the EM fields at the point where the output terminals are no longer covered by a shield. The gate driver switches large currents (such as 5 A to 15 A, for example) through these exposed terminals. The switched large currents are generally greater in magnitude than the EM-induced currents. The gate driver is able to overdrive the induced currents to maintain control of the FETs. The high side of the gate drivers and the FET may share a common ground and a gate control signal trace, both of which may be susceptible to coupled currents.

Gate drivers may turn on low-resistance switches to source and sink gate currents. Series resistors may sometimes be added to limit gate current. Switched gate currents may be larger than coupled currents in order to maintain control of their respective FETs.

Gate drivers may be able to sense FET operating voltages or currents in order to provide feedback and react to faults. Over-current faults may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. Sensed voltages may be heavily filtered to reject coupled currents. Filtering may slow down the response to fault conditions, resulting in delays in response. For example, the rate of current increase due to a low resistance short circuit may reach damaging levels prior to being detected by the heavily filtered drain to source voltage detection strategy. The resulting short circuit may damage the FET or the vehicle, prior to being detected and shut off.

According to one or more embodiments, a FET driver circuit may provide rapid over-current detection by either shunt current sensing or by diverting a fraction of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a “point-of-use IC” where sensing circuitry is in close proximity to the FET. Even if a point-of-use IC and a remote controller are resistant to EM fields, communication between the point-of-use IC and remote controller remains susceptible to induced currents. Point-of-use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point-of-use ICs have not been used in high EM field applications. A high EM field may be a field (i) that induces a current within an IC that is in excess of an operating current of the IC and leads to malfunction, or (ii) that induces a differential voltage within an IC which is in excess of the operating differential voltage and leads to malfunction. A high EM field may be a field that is greater than approximately 10 A or approximately 100V, for example.

Gate driver circuits may include various oscillators to provide a clock reference signal used in various operations in the inverter. Oscillator frequency variation between multiple controllers connected by a common communications bus may be a major source of uncertainty in the exchange of information between controllers. For example, a first controller without onboard non-volatile memory may have a wide variation in oscillator frequency with respect to a second controller. This disparity in oscillator frequency may result in either degraded communications reliability or a complicated communications protocol in order to overcome the potential uncertainty in communications resulting from this disparity.

One or more embodiments may trim an oscillator frequency of a high voltage controller to an oscillator frequency of a low voltage controller to a high degree of accuracy. One or more embodiments may trim an oscillator frequency of a point-of use controller. One or more embodiments may include an isolated gate-driver with a low-voltage (LV) PWM signal domain and a high-voltage (HV) phase domain. One or more embodiments may include transceivers that allow communication between LV and HV domains. One or more embodiments may include a clock reference sampler to sample and align the LV domain to an external crystal clock reference, and may have less than a one percent error. One or more embodiments may include a clock calibrator to align the HV domain clock to the LV domain clock so that all timing is synchronized. One or more embodiments may synchronize all voltage domains of a phase switch to an absolute clock reference that has less than one percent error.

One or more embodiments may perform an initial trim operation during controller initialization using a handshaking procedure to ensure that both controllers are prepared to perform the trim operation. One or more embodiments may determine whether the trim operation should be performed, and may continuously and independently perform the determination on any controller with an oscillator.

The initial trim operation may use a waveform transmitted by a low voltage controller to the high voltage controller on a command bus over a galvanic isolation interface between the high voltage controller and the low voltage controller. The waveform may have a predetermined period, and the high voltage controller may use a successive approximation algorithm to manipulate trim inputs of the oscillator of the high voltage controller to attain the proper oscillator frequency.

After the initial trim operation has been performed, subsequent trim operations may be performed using a message bus, rather than the command bus, over the galvanic isolation interface using a message transmitted using a standard communications protocol. The subsequent trim operations may not interfere with command bus communications between the high voltage controller and the low voltage controller that may be occurring during the subsequent trim operations.

One or more embodiments may remove the need to have an oscillator trim value for a controller stored in non-volatile memory. One or more embodiments may correct any drift in oscillator frequency due to temperature effects and component drift or aging by performing the trim operation upon controller initialization and periodically during operation. One or more embodiments may remove the need for dedicated pins and external components to improve oscillator frequency matching between controllers. By removing the need for non-volatile memory on-board a controller, one or more embodiments may provide cost savings due to reduced component count, testing, and process complexity. One or more embodiments may provide more robust and faster communications between controllers due to simplifying a communication protocol. One or more embodiments may improve a low voltage controller oscillator using an external oscillator reference. One or more embodiments may improve timing measurements performed by peripheral controllers, such as a high voltage controller and a point-of use controller, for example, due to the trimming of oscillators of the peripheral controllers to match the oscillator of the low voltage controller. One or more embodiments may provide tight matching of clock frequency between controllers and cost savings due to performing the oscillator trim locally to the controllers.

FIG.1depicts an exemplary system infrastructure for a vehicle including a combined inverter and converter, according to one or more embodiments. In the context of this disclosure, the combined inverter and converter may be referred to as an inverter. As shown inFIG.1, electric vehicle100may include an inverter110, a motor190, and a battery195. The inverter110may include components to receive electrical power from an external source and output electrical power to charge battery195of electric vehicle100. The inverter110may convert DC power from battery195in electric vehicle100to AC power, to drive motor190of the electric vehicle100, for example, but the embodiments are not limited thereto. The inverter110may be bidirectional, and may convert DC power to AC power, or convert AC power to DC power, such as during regenerative braking, for example. Inverter110may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

FIG.2depicts an exemplary system infrastructure for the inverter110ofFIG.1with a point-of-use switch controller, according to one or more embodiments. Electric vehicle100may include inverter110, motor190, and battery195. Inverter110may include an inverter controller300(shown inFIG.3) to control the inverter110. Inverter110may include a low voltage upper phase controller120separated from a high voltage upper phase controller130by a galvanic isolator150, and an upper phase power module140. Upper phase power module140may include a point-of-use upper phase controller142and upper phase switches144. Inverter110may include a low voltage lower phase controller125separated from a high voltage lower phase controller135by galvanic isolator150, and a lower phase power module145. Lower phase power module145may include a point-of-use lower phase controller146and lower phase switches148. Upper phase switches144and lower phase switches148may be connected to motor190and battery195. Galvanic isolator150may be one or more of optical, transformer-based, or capacitance-based isolation. Galvanic isolator150may be one or more capacitors with a value from approximately 20 fF to approximately 100 fF, with a breakdown voltage from approximately 6 kV to approximately 12 kV, for example. Galvanic isolator150may include a pair of capacitors, where one capacitor of the pair carries an inverse data signal from the other capacitor of the pair to create a differential signal for common-mode noise rejection. Galvanic isolator150may include more than one capacitor in series. Galvanic isolator150may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

Inverter110may include a low voltage area, where voltages are generally less than 5V, for example, and a high voltage area, where voltages may exceed 500V, for example. The low voltage area may be separated from the high voltage area by galvanic isolator150. Inverter controller300may be in the low voltage area of inverter110, and may send signals to and receive signals from low voltage upper phase controller120. Low voltage upper phase controller120may be in the low voltage area of inverter110, and may send signals to and receive signals from high voltage upper phase controller130. Low voltage upper phase controller120may send signals to and receive signals from low voltage lower phase controller125. High voltage upper phase controller130may be in the high voltage area of inverter110. Accordingly, signals between low voltage upper phase controller120and high voltage upper phase controller130pass through galvanic isolator150. High voltage upper phase controller130may send signals to and receive signals from point-of-use upper phase controller142in upper phase power module140. Point-of-use upper phase controller142may send signals to and receive signals from upper phase switches144. Upper phase switches144may be connected to motor190and battery195. Upper phase switches144and lower phase switches148may be used to transfer energy from motor190to battery195, from battery195to motor190, from an external source to battery195, or from battery195to an external source, for example. The lower phase system of inverter110may be similar to the upper phase system as described above.

FIG.3depicts an exemplary system infrastructure for inverter controller300ofFIG.2, according to one or more embodiments. Inverter controller300may include one or more controllers.

The inverter controller300may include a set of instructions that can be executed to cause the inverter controller300to perform any one or more of the methods or computer based functions disclosed herein. The inverter controller300may operate as a standalone device or may be connected, e.g., using a network, to other computer systems or peripheral devices.

As shown inFIG.3, the inverter controller300may include a processor302, e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor302may be a component in a variety of systems. For example, the processor302may be part of a standard inverter. The processor302may be one or more general processors, digital signal processors, application specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other now known or later developed devices for analyzing and processing data. The processor302may implement a software program, such as code generated manually (i.e., programmed).

The inverter controller300may include a memory304that can communicate via a bus308. The memory304may be a main memory, a static memory, or a dynamic memory. The memory304may include, but is not limited to computer readable storage media such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, magnetic tape or disk, optical media and the like. In one implementation, the memory304includes a cache or random-access memory for the processor302. In alternative implementations, the memory304is separate from the processor302, such as a cache memory of a processor, the system memory, or other memory. The memory304may be an external storage device or database for storing data. Examples include a hard drive, compact disc (“CD”), digital video disc (“DVD”), memory card, memory stick, floppy disc, universal serial bus (“USB”) memory device, or any other device operative to store data. The memory304is operable to store instructions executable by the processor302. The functions, acts or tasks illustrated in the figures or described herein may be performed by the processor302executing the instructions stored in the memory304. The functions, acts or tasks are independent of the particular type of instructions set, storage media, processor or processing strategy and may be performed by software, hardware, integrated circuits, firm-ware, micro-code and the like, operating alone or in combination. Likewise, processing strategies may include multiprocessing, multitasking, parallel processing and the like.

As shown, the inverter controller300may further include a display310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid-state display, a cathode ray tube (CRT), a projector, a printer or other now known or later developed display device for outputting determined information. The display310may act as an interface for the user to see the functioning of the processor302, or specifically as an interface with the software stored in the memory304or in the drive unit306.

Additionally or alternatively, the inverter controller300may include an input device312configured to allow a user to interact with any of the components of inverter controller300. The input device312may be a number pad, a keyboard, or a cursor control device, such as a mouse, or a joystick, touch screen display, remote control, or any other device operative to interact with the inverter controller300.

The inverter controller300may also or alternatively include drive unit306implemented as a disk or optical drive. The drive unit306may include a computer-readable medium322in which one or more sets of instructions324, e.g. software, can be embedded. Further, the instructions324may embody one or more of the methods or logic as described herein. The instructions324may reside completely or partially within the memory304and/or within the processor302during execution by the inverter controller300. The memory304and the processor302also may include computer-readable media as discussed above.

In some systems, a computer-readable medium322includes instructions324or receives and executes instructions324responsive to a propagated signal so that a device connected to a network370can communicate voice, video, audio, images, or any other data over the network370. Further, the instructions324may be transmitted or received over the network370via a communication port or interface320, and/or using a bus308. The communication port or interface320may be a part of the processor302or may be a separate component. The communication port or interface320may be created in software or may be a physical connection in hardware. The communication port or interface320may be configured to connect with a network370, external media, the display310, or any other components in inverter controller300, or combinations thereof. The connection with the network370may be a physical connection, such as a wired Ethernet connection or may be established wirelessly as discussed below. Likewise, the additional connections with other components of the inverter controller300may be physical connections or may be established wirelessly. The network370may alternatively be directly connected to a bus308.

While the computer-readable medium322is shown to be a single medium, the term “computer-readable medium” may include a single medium or multiple media, such as a centralized or distributed database, and/or associated caches and servers that store one or more sets of instructions. The term “computer-readable medium” may also include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processor or that cause a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium322may be non-transitory, and may be tangible.

The inverter controller300may be connected to a network370. The network370may define one or more networks including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include a public network, such as the Internet, a private network, such as an intranet, or combinations thereof, and may utilize a variety of networking protocols now available or later developed including, but not limited to TCP/IP based networking protocols. The network370may include wide area networks (WAN), such as the Internet, local area networks (LAN), campus area networks, metropolitan area networks, a direct connection such as through a Universal Serial Bus (USB) port, or any other networks that may allow for data communication. The network370may be configured to couple one computing device to another computing device to enable communication of data between the devices. The network370may generally be enabled to employ any form of machine-readable media for communicating information from one device to another. The network370may include communication methods by which information may travel between computing devices. The network370may be divided into sub-networks. The sub-networks may allow access to all of the other components connected thereto or the sub-networks may restrict access between the components. The network370may be regarded as a public or private network connection and may include, for example, a virtual private network or an encryption or other security mechanism employed over the public Internet, or the like.

In accordance with various implementations of the present disclosure, the methods described herein may be implemented by software programs executable by a computer system. Further, in an exemplary, non-limited implementation, implementations can include distributed processing, component or object distributed processing, and parallel processing. Alternatively, virtual computer system processing can be constructed to implement one or more of the methods or functionality as described herein.

It will be understood that the operations of methods discussed are performed in one embodiment by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer-readable code) stored in storage. It will also be understood that the disclosure is not limited to any particular implementation or programming technique and that the disclosure may be implemented using any appropriate techniques for implementing the functionality described herein. The disclosure is not limited to any particular programming language or operating system.

FIG.4depicts an exemplary system infrastructure for the point-of-use switch controller ofFIG.2, according to one or more embodiments. For a three-phase inverter, each of the upper phase and the lower phase may include three phases correlating with phases A, B, and C. For example, upper phase power module140may include upper phase power module140A for upper phase A, upper phase power module140B for upper phase B, and upper phase power module140C for upper phase C. Upper phase power module140A may include point-of-use upper phase A controller142A and upper phase A switches144A. Upper phase power module140B may include point-of-use upper phase B controller142B and upper phase B switches144B. Upper phase power module140C may include point-of-use upper phase C controller142C and upper phase C switches144C. Each of the upper phase A switches144A, upper phase B switches144B, and upper phase C switches144C may be connected to motor190and battery195.FIG.4depicts details of the upper phase power module140. Although not shown, the lower phase power module145may include a similar structure as the upper phase power module140for lower phases A, B, and C.

FIG.5depicts an exemplary system infrastructure for the upper power module ofFIG.4, according to one or more embodiments. For example,FIG.5provides additional details of upper phase power module140A. Although not shown, upper phase power module140B, upper phase power module140C, and respective lower phase power modules of lower phase power module145may include a similar structure as the upper phase power module140A shown inFIG.5. Moreover, the terms upper, lower, north, and south used in the disclosure are merely for reference, do not limit the elements to a particular orientation, and are generally interchangeable throughout. For example, the upper phase power module140could be referred to a lower phase power module, a north phase power module, a south phase power module, a first phase power module, or a second phase power module.

Upper phase power module140A may include point-of-use upper phase A controller142A and upper phase A switches144A. Upper phase A switches144A may include one or more groups of switches. As shown inFIG.5, upper phase A switches144A may include upper phase A north switches144A-N and upper phase A south switches144A-S. Point-of-use upper phase A controller142A may include one or more memories, controllers, or sensors. For example, point-of-use upper phase A controller142A may include a communication manager405, a functional safety controller410, a testing interface and controller415, a north thermal sensor420A, a south thermal sensor420B, a self-test controller425, a command manager430, a waveform adjuster435, a memory440, north switches control and diagnostics controller450N, and south switches control and diagnostics controller450S. Point-of-use upper phase A controller142A may include more or less components than those shown inFIG.5. For example, point-of-use upper phase A controller142A may include more or less than two switch control and diagnostics controllers, and may include more than two thermal sensors.

Communication manager405may control inter-controller communications to and from point-of-use upper phase A controller142A and/or may control intra-controller communications between components of point-of-use upper phase A controller142A. Functional safety controller410may control safety functions of point-of-use upper phase A controller142A. Testing interface and controller415may control testing functions of point-of-use upper phase A controller142A, such as end-of-line testing in manufacturing, for example. North thermal sensor420A may sense a temperature at a first location in point-of-use upper phase A controller142A, and south thermal sensor420B may sense a temperature at a second location in point-of-use upper phase A controller142A. Self-test controller425may control a self-test function of point-of-use upper phase A controller142A, such as during an initialization of the point-of-use upper phase A controller142A following a power on event of inverter110, for example. Command manager430may control commands received from communication manager405issued to the north switches control and diagnostics controller450N and south switches control and diagnostics controller450S. Waveform adjuster435may control a waveform timing and shape of commands received from communication manager405issued to the north switches control and diagnostics controller450N and south switches control and diagnostics controller450S. Memory440may include one or more volatile and non-volatile storage media for operation of point-of-use upper phase A controller142A. North switches control and diagnostics controller450N may send one or more signals to north switches144A-N to control an operation of north switches144A-N, and may receive one or more signals from north switches144A-N that provide information about north switches144A-N. South switches control and diagnostics controller450S may send one or more signals to south switches144A-S to control an operation of south switches144A-S, and may receive one or more signals from south switches144A-S that provide information about south switches144A-S. As stated above, the terms north and south are merely used for reference, and north switches control and diagnostics controller450N may send one or more signals to south switches144A-S, and south switches control and diagnostics controller450S may send one or more signals to south switches144A-N.

FIG.6depicts an exemplary system infrastructure for an inverter with a controller including oscillator calibration, according to one or more embodiments.FIG.6may include an inverter600that includes a PWM controller602, an upper gate driver604, a lower gate driver606, an upper phase switch608, and a lower phase switch609. Upper phase switch608and lower phase switch609may provide a switchable connection between battery611and phase connector610, which may be connected to motor190, for example, to drive motor190. The PWM controller602may generate a primary clock reference signal, and may provide the primary clock reference signal as PWM signal603to upper gate driver604, and may provide the primary clock reference signal as PWM signal605to lower gate driver606.

The upper gate driver604may include a low voltage area612and a high voltage area614, which are separated by a galvanic isolator616. The low voltage area612may accept PWM signal603from the PWM controller602, and transfer the PWM signal across the galvanic isolator616to the high voltage area614, which may then drive upper phase switch608. Here, upper gate driver604may drive upper phase switch608, and lower gate driver606may drive lower phase switch609.

The inverter600may be an implementation of inverter110. PWM controller602may be an implementation of inverter controller300. Upper gate driver604may be an implementation of low voltage upper phase controller120and one or more of high voltage upper phase controller130or point-of-use upper phase controller142. Lower gate driver606may be an implementation of low voltage lower phase controller125and one or more of high voltage lower phase controller135or point-of-use lower phase controller146. Upper phase switch608may be an implementation of upper phase switches144. Lower phase switch609may be an implementation of lower phase switches148. Low voltage area612may be an implementation of low voltage upper phase controller120. High voltage area614may be an implementation of one or more of high voltage upper phase controller130or point-of-use upper phase controller142. Galvanic isolator616may be an implementation of galvanic isolator150.

The high voltage area614may include a phase switch on-time detector618, which may measure and store the actual on-time of upper phase switch608and send this information, in the form of an encoded message, for example, to the low voltage area612of the upper gate driver604. For example, phase switch on-time detector618may detect a number of pulses of a system clock that occurred while the upper phase switch608was detected to be turned on. Phase switch on-time detector618may measure on an actual on-time of upper phase switch608using a gate to source voltage, for example, of upper phase switch608. Phase switch on-time detector618may measure on an actual on-time of upper phase switch608using the absolute value of the current, for example, through the upper phase switch608. Phase switch on-time detector618may measure on an actual on-time of upper phase switch608using an absolute value of a drain to source voltage, for example, of upper phase switch608, such as when the voltage is above a threshold value.

For the gate to source voltage, the gate to source waveform may be divided into three charge phases: (i) Qgs1 phase—switching charge needed reach the threshold voltage, (ii) Qgd phase—switching charge needed to switch the drain to source voltage, and (iii) Qgs2 phase—switching charge needed to reach full enhancement. The phase switch on-time detector618may detect each of these three phases by monitoring the gate to source voltage and gate to source current of upper phase switch608. Shoot-through may be avoided if the upper phase switch608, which is switching off, has reached the Qgs1/Qgd boundary before the lower phase switch609, which is switching on, has started the Qgs1 phase. For example, the phase switch on-time detector618can start the on-time counter at the beginning of the Qgs1 turn-on phase and maintain the counter running while the upper phase switch608turns completely on through the end of the Qgs2 phase. The counter then continues to run after the upper phase switch608is commanded to turn off and stops counting when the upper phase switch608reaches the Qgd to Qgs1 boundary as upper phase switch608is commanded off. This defines “on-time” as the time where there is any possibility that the upper phase switch608can be conducting current and ensures that the on-time of opposing upper phase switch608and lower phase switch609do not overlap.

The low voltage area612may include an on-time comparator628configured to receive the information, such as in an encoded message providing a feedback signal, from the phase switch on-time detector618, and compare the received feedback signal to the PWM signal603as a feedback comparison. The low voltage area612may include a PWM on-time trimmer622, which may use the feedback comparison from on-time comparator628to generate a programmable delay of the rising or falling edges of PWM signal603. The programmable delay may be generated so that the commanded duty cycle at the upper phase switch608is the same as the incoming PWM duty cycle from the PWM controller602, as defined by PWM signal603.

The low voltage area612may further include a PWM delay trimmer620, which may trim the incoming signal such that the absolute delay of PWM edges is the same for parallel gate drivers, including upper gate driver604. For example, PWM signal603may be sent to two upper phase gate drivers, so that the two upper phase receive PWM signal603in parallel. The two upper phase gate drivers may have propagation delays and other circuit characteristics that are different from one another. Therefore, without correction, the different circuit delays result in output phase switch switching times that are different from one another, even though the PWM signal603input to the circuits is the same. PWM delay trimmer620provides a trim operation to delay the PWM signal603by an individual amount for each phase gate driver so that the two upper phase gate drivers have the same output phase switch switching times based on PWM signal603, even with different circuit characteristics.

The low voltage area612may further include a clock reference sampler624, which samples an external clock reference to align the low voltage domain clock to an external precision reference. For example, clock reference sampler624may be configured to align the clock reference signal of the upper gate driver604with a clock reference signal of the PWM controller602. Both the low voltage area612and high voltage area614may include a respective clock calibrator626to align the clocks, or oscillators, of the low voltage area612and high voltage area614. Respective clock calibrators626may each include an oscillator, or the oscillators may be separate from the respective clock calibrator626. The functions of clock calibrator626may be included in communication manager405, for example. For example, clock reference sampler624may count the number of system clock pulses in one or more periods of the incoming reference clock signal, and compare that number to an expected value. The reference clock frequency may be a value from approximately 100 Hz to approximately 10 kHz, for example. The clock calibrator626in low voltage area612may increase or decrease the period of an internal oscillator in low voltage area612to align the system clock count to the expected value. The procedure may occur in a single operation or may be iterative such that successive reference clock samples brings the LV internal oscillator into alignment with the reference clock. The clock alignment may run periodically over time to make adjustments to account for drift that may occur due to aging of the circuit or changes in temperature, for example.

The clock calibrator626in low voltage area612may send updates to clock calibrator626in high voltage area614when adjustments to the clock calibrator626in low voltage area612are made so that the low and high voltage clocks are aligned. The clock calibrator626in high voltage area614may operate in a similar manner to clock calibrator626in low voltage area612, and may receive a reference signal, compare the reference signal to an internally expected value, and make adjustments accordingly. The clock calibrator626in low voltage area612may send a data stream to the clock calibrator626in high voltage area614, and the data stream may be a defined number of LV system clock pulses. For example, the defined number may be a defined number of LV system clock pulses to last for approximately 1 mS. The clock calibrator626in high voltage area614may count the number of system clock pulses during this message time, compare the number to the reference value, and adjust an internal oscillator in the high voltage area614based on the comparison. The procedure may occur in a single operation or may be iterative such that successive LV clock samples brings the HV internal oscillator into alignment with the LV internal oscillator. The reference clock signal may be a signal from PWM controller602, or may be generated by one of upper gate driver604or lower gate driver606for use by the other gate driver. For example, when a clock signal from PWM controller602is available, upper gate driver604may synchronize an internal clock to PWM controller602, and lower gate driver606may synchronize an internal clock to upper gate driver604. When a clock signal from PWM controller602is unavailable, lower gate driver606may continue to synchronize an internal clock to upper gate driver604. The clock signal from PWM controller602may be unavailable due to a fault on the clock signal, such as a shorted high signal or an open low signal, for example, or a fault with the PWM controller602itself. For example, clock reference sampler624may set a “no clock” fault after a threshold time has elapsed without a change in the clock signal from PWM controller602.

Oscillator frequency variation between PWM controller602, low voltage area612, high voltage area614, and a point-of-use controller for upper phase switch608, for example, may be a major source of uncertainty in the exchange of information between the controllers, if no oscillator calibration is provided. High voltage area614of upper gate driver604may not include local non-volatile memory, which could result in a wide variation in oscillator frequency with respect to the low voltage area612of upper gate driver604, if no oscillator calibration is provided. This disparity in oscillator frequency may result in either degraded communications reliability or a complicated communications protocol to overcome the potential uncertainty.

One or more embodiments may include clock calibrator626to trim the oscillator frequency of the high voltage area614of upper gate driver604to the oscillator frequency of the low voltage area612of upper gate driver604, to a high degree of accuracy. Clock calibrator626may also be used to trim the oscillator frequency of point-of-use controller (such as point-of-use upper phase A controller142A, for example) for upper phase switch608, for example.

The initial trim operation may be performed during initialization of the upper gate driver604using a handshaking procedure to ensure that clock calibrator626in low voltage area612and clock calibrator626in high voltage area614are ready to perform the trim operation when required. Both clock calibrator626in low voltage area612and clock calibrator626in high voltage area614may continuously and independently determine whether the trim operation should be performed. For example, there may be several mechanisms that may trigger a recalibration after an initial calibration performed at power up. These mechanisms may include one or more of a periodic timeout, a command by the PWM controller602, a change in die temperature, an integrity check communication failure between the clock calibrator626in low voltage area612and clock calibrator626in high voltage area614, or a reset and subsequent re-initialization of one or more of upper gate driver604or lower gate driver606.

For the initial trim operation, clock calibrator626in low voltage area612may transmit a waveform on the command bus of galvanic isolator616to clock calibrator626in high voltage area614. The waveform may have a predetermined frequency, and clock calibrator626in high voltage area614may implement a successive approximation algorithm to manipulate oscillator circuit trim inputs to calibrate the proper oscillator frequency.

After the initial trim operation has been performed, subsequent trim operations may be performed using only the message bus of galvanic isolator616using a message transmitted using a communications protocol. For example, a subsequent trim operation may include a two-message sequence. First, a message may be sent with a header that alerts the high voltage area614that a trim operation is desired, so that high voltage area614may perform any housekeeping that needs to be performed prior to the trim operation. Next, the trim message itself may be sent. The header of the message may indicate a trim operation, and the message payload may be used by the clock calibrator626in high voltage area614to perform the trim operation. Similar to an initial trim operation, the message payload may be a waveform with a known period and duration. A message may include three fields: (1) a header field that includes address and identification information, (2) a payload field, the length of which is determined by the header field, and (3) a cyclic redundancy check (CRC) field used for message integrity checking. Using the message bus of galvanic isolator616for subsequent trim operations may ensure the oscillator calibration does not interfere with command bus communications that may be occurring during the subsequent trim operations.

A low voltage domain clock calibration between clock calibrator626in low voltage area612and clock calibrator626in high voltage area614may include various operations. For example, clock calibrator626in low voltage area612may receive an oscillator trim request via the message bus of galvanic isolator616. The oscillator trim request received via the message bus of galvanic isolator616from clock calibrator626in high voltage area614may be formulated such that the trim request will always win contention for the message bus and will initiate the oscillator trim procedure. The clock calibrator626in low voltage area612may send an oscillator trim acknowledgement via the message bus. The oscillator trim request and acknowledgement may have the same format (width, etc.) and may be formulated such that they always win contention over normal priority message bus communications, but may lose contention to an oscillator trim request from clock calibrator626in high voltage area614.

The clock calibrator626in low voltage area612may send an oscillator trim waveform via the command bus. The clock calibrator626in low voltage area612may receive an oscillator trim acknowledgement via the message bus. When an oscillator trim acknowledgement is not received after a threshold time, the clock calibrator626in low voltage area612may re-send the oscillator trim waveform via the command bus. When an oscillator trim acknowledgement is received, the clock calibrator626in low voltage area612may enter a mission mode operation.

In the mission mode operation, the clock calibrator626in low voltage area612may await an oscillator trim request and determine whether a clock calibration should be updated. When a clock calibration should be updated, the clock calibrator626in low voltage area612may send a clock calibration message via the message bus. The mission mode trim requests may be sent via a series of normal priority message bus messages. The header of the first message may inform the clock calibrator626in high voltage area614that an oscillator trim message will be sent, followed by the subsequent message, where the header informs the clock calibrator626in high voltage area614of the oscillator trim operation being performed. The payload of the message may include a number of bits that will be used by the clock calibrator626in high voltage area614to count clock cycles to determine the oscillator trim value needed to synchronize frequency of the clock calibrator626in high voltage area614with respect to the clock calibrator626in low voltage area612.

In a reset operation, the clock calibrator626in low voltage area612may complete a startup configuration, and await an oscillator trim request. When a post-configuration timeout has elapsed, the clock calibrator626in low voltage area612may send an oscillator trim request via the message bus. If an oscillator trim request is not received within a threshold time, the clock calibrator626in low voltage area612may re-send the oscillator trim request via the message bus. If the oscillator trim request is received, the clock calibrator626in low voltage area612may send an oscillator trim acknowledgement via the message bus and proceed with the trim operation. As described above, timeouts may exist for some of the operations in the trim procedure to ensure that the clock calibrator626in low voltage area612does not get stuck. For example, after device initialization/configuration is complete, if an oscillator trim request is not received within a threshold amount of time, the clock calibrator626in low voltage area612may initiate an oscillator trim request.

A high voltage domain clock calibration between clock calibrator626in low voltage area612and clock calibrator626in high voltage area614may include various operations. For example, in a reset operation, the clock calibrator626in high voltage area614may complete a startup configuration, and send an oscillator trim request via the message bus. If an oscillator trim request is not received within a threshold time, the clock calibrator626in high voltage area614may re-send the oscillator trim request via the message bus. If the oscillator trim request is received, the clock calibrator626in low voltage area612may trim the oscillator based on the oscillator trim waveform received via the command bus and send an acknowledgment on the message bus to acknowledge the oscillator trim operation in progress. The clock calibrator626in low voltage area612may enter a mission mode operation, and await an oscillator trim message. When the oscillator trim message is received via the message bus, the clock calibrator626in low voltage area612may trim the oscillator based on the oscillator trim waveform received via the message bus.

One or more embodiments may remove the need to have an oscillator trim value for the high voltage area614of upper gate driver604stored in non-volatile memory of the high voltage area614of upper gate driver604. In addition, any drift in oscillator frequency due to temperature effects and component drift or aging may be effectively corrected by performing the trim operation upon device initialization and periodically during operation of the upper gate driver604. One or more embodiments may remove the need for dedicated pins and external components to improve oscillator frequency matching between controllers. By removing the need for non-volatile memory on-board the high voltage area614of upper gate driver604, one or more embodiments may exhibit cost savings due to the associated circuit area savings, testing savings, and decreased process complexity. One or more embodiments may be useful for systems that require relatively tight matching of timing or frequency measurements but do not have robust control of on-board oscillator frequency between controllers.

One or more embodiments may include clock calibrator626of low voltage area612that determines an oscillator frequency difference between an oscillator of low voltage area612of upper gate driver604and an oscillator of high voltage area614of upper gate driver604, and provides a correction to clock calibrator626of high voltage area614via the message bus of galvanic isolator616.

One or more embodiments may provide communications between controllers that is more robust and faster than some solutions by avoiding the need to over specify the timing of the communication protocol. In addition, with the oscillator of low voltage area612being improved due to an external reference, such as clock reference sampler624from PWM controller602, for example, timing measurements performed by peripheral controllers may be improved due to the trimming of peripheral oscillators of high voltage area614of upper gate driver604and point-of-use controller for upper phase switch608to match the low voltage area612oscillator. One or more embodiments may allow tight matching of clock frequency between controllers while reducing costs of the high voltage area614of upper gate driver604due to performing the oscillator trim in situ.

Due to this clock alignment, the feedback signal from phase switch on-time detector618may be used by the on-time comparator628without errors that would occur due to a difference between clocks in the low voltage area612and high voltage area614. The clock alignment may further allow for PWM delay trimmer620to add a delay to PWM signal603on an individual phase gate driver basis so that all phase switches have the same total delay from the PWM input to the phase voltage output. A tester at end of line manufacturing may measure a time delay between a change of state in a PWM signal and a change of state in the phase voltage. This time delay may not be reduced due to inherent characteristics of the inverter600. However, the time delay may be increased for individual components. The PWM delay trimmer620may be set for each individual phase gate driver based on the longest delay of any individual phase gate driver, so that the final trimmed delay from PWM edge to Phase edge is the same for all phase gate drivers in inverter600. In this manner, transition times between upper and lower devices are standardized to reduce the possibility of shoot-through. This PWM delay trim may be performed at final end-of-line test, and the clock alignment may ensure that the delay trim remains valid for the life of the inverter600. As shown inFIG.6, the lower gate driver606may include all of the components and functions described herein for upper gate driver604, and does therefore not include detailed labels in the drawings or a description herein.

The PWM on-time trim algorithm may require that an on-time pulse be sent to the input of PWM on-time trimmer622, such as from the PWM controller602or by upper gate driver604itself in a test mode. This on-time pulse may be at least 5 μS, for example. The on-time comparator628may count the number of system clock pulses in the on-time pulse as the on-time pulse enters PWM on-time trimmer622. The on-time pulse may pass through PWM on-time trimmer622and PWM delay trimmer620without alteration, and phase switch on-time detector618may count the number of clock pulses for the on-time pulse using one of the methods discussed above. Phase switch on-time detector618may send the clock count to on-time comparator628, which compares the on-time comparator628count to the count received from phase switch on-time detector618. On-time comparator628may adjust settings in PWM on-time trimmer622to match the two clock counts. The process may be repeated and the expected result may be that on-time comparator628will observe that phase switch on-time detector618has reported the correct value. A PWM delay trim may require that a tester observe a change (rising or falling) in the PWM signal603and observe a change (rising or falling) of a voltage at the phase connector610. The delay between these two events may be the total propagation delay of the command signal. The tester may adjust the settings in PWM delay trimmer620to trim this delay to the same value on a part-by-part basis. For example, a delay trim value may be from approximately 100 nS to approximately 500 nS.

Some approaches may include a PWM command signal path from a PWM controller to the half-H switch, but do not include feedback from the high voltage side to the low voltage side for the purpose of fault feedback. Upper gate driver604of inverter600may include the addition of the phase switch on-time detector618in the high voltage area614. Upper gate driver604may include a path for sending on-time data of upper phase switch608from high voltage area614to on-time comparator628in low voltage area612. The path may pass through the galvanic isolator616of the upper gate driver604. Upper gate driver604may include PWM on-time trimmer622that may use the on-time data to de-skew the PWM signal path from PWM signal603to the upper phase switch608. Upper gate driver604may include a PWM delay trimmer620to adjust the absolute delay of PWM edges of PWM signal603so that all PWM signal paths within a given design are the same, regardless of circuit characteristics. Upper gate driver604may include a clock reference sampler624that may trim the low voltage domain clock to an external precision reference. Upper gate driver604may include a low voltage area612clock calibrator626that communicates with a high voltage area614clock calibrator626so that the low voltage and high voltage clocks are both aligned to an external reference, to ensure that the PWM on-time trimmer622and PWM delay trimmer620setpoints are stable over time and precisely set for individual paralleled gate drivers.

A respective PWM on-time trimmer622and PWM delay trimmer620may use a common timing reference for all low voltage and high voltage areas of all gate drivers to maintain timing alignment between all inverter gate drivers on a common phase or between adjacent phases. A respective phase switch on-time detector618in all gate drivers may allow the PWM on-time trimmer622to maintain the intended PWM duty cycle at the point of use for respective phase switches.

One or more embodiments may trim an oscillator frequency of a high voltage controller to an oscillator frequency of a low voltage controller to a high degree of accuracy. One or more embodiments may trim an oscillator frequency of a point-of use controller. One or more embodiments may include an isolated gate-driver with a low-voltage (LV) PWM signal domain and a high-voltage (HV) phase domain. One or more embodiments may include transceivers that allow communication between LV and HV domains. One or more embodiments may include a clock reference sampler to sample and align the LV domain to an external crystal clock reference, and may have less than a one percent error. One or more embodiments may include a clock calibrator to align the HV domain clock to the LV domain clock so that all timing is synchronized. One or more embodiments may synchronize all voltage domains of a phase switch to an absolute clock reference that has less than one percent error.

One or more embodiments may remove the need to have an oscillator trim value for a controller stored in non-volatile memory. One or more embodiments may correct any drift in oscillator frequency due to temperature effects and component drift or aging by performing the trim operation upon controller initialization and periodically during operation. One or more embodiments may remove the need for dedicated pins and external components to improve oscillator frequency matching between controllers. By removing the need for non-volatile memory on-board a controller, one or more embodiments may provide cost savings due to reduced component count, testing, and process complexity. One or more embodiments may provide more robust and faster communications between controllers due to simplifying a communication protocol. One or more embodiments may improve a low voltage controller oscillator using an external oscillator reference. One or more embodiments may improve timing measurements performed by peripheral controllers, such as a high voltage controller and a point-of use controller, for example, due to the trimming of oscillators of the peripheral controllers to match the oscillator of the low voltage controller. One or more embodiments may provide tight matching of clock frequency between controllers and cost savings due to performing the oscillator trim locally to the controllers.