CIRCUIT AND COMMUNICATION SYSTEM

A circuit includes: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC 119 from Japanese Patent application No. 2023-123355 filed on Jul. 28, 2023, the disclosure of which is incorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to a circuit and a communication system.

RELATED ART

Patent Document 1 (Japanese translation of PCT international application No. 2001-503182) discloses a receiving circuit for receiving data using a differential signal, which is a balanced signal transmitted by an alternating current (AC) coupling method (see FIG. 4 of Patent Document 1).

In the alternating current coupling method, a capacity element that removes a DC signal is placed in the transmission path. For this reason, while the data input to the receiving circuit continues to change, the capacity element is repeatedly charged and discharged, and the potentials of the two signals included in the differential signal, which change in a complementary manner, change to H level or L level. Thus, the receiving circuit may operate normally according to the differential signal.

However, when the input data does not change for a certain period of time, the energy stored in the capacity element continues to be discharged, and the potentials of the two signals may become approximately the same level. Thus, the receiving circuit is unable to detect the potential of the differential signal and may malfunction. For this reason, the conventional technology has room for improvement in terms of realizing stable operation of the receiving circuit.

The disclosure provides a circuit capable of realizing stable operation.

SUMMARY

The circuit according to the disclosure is an alternating current coupling circuit, including: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.

The communication system according to the disclosure includes a first semiconductor device, having a transmitting circuit for transmitting a first signal and a second signal; and a second semiconductor device having the above-mentioned circuit, wherein the first signal is supplied to the circuit via the first capacitive element, and the second signal is supplied to the circuit via the second capacitive element.

DESCRIPTION OF EMBODIMENTS

According to the disclosure, a circuit that is capable of achieving stable operation may be provided.

The embodiment is described below with reference to the drawings. In addition, the same or similar symbols are used for the same functions and configurations, and descriptions therefor are omitted as appropriate.

Embodiment

FIG.1is a diagram showing the configuration of the display device according to the embodiment of the disclosure. The display device100may be interpreted as a display device for a vehicle that is mounted on an automobile or the like. The display device100includes a display panel10, a timing controller11, driver integrated circuits (IC)12, and a gate driver13.

The display panel10may be interpreted as an image display device such as an LCD display panel or an organic electro luminescence (EL) panel. The timing controller11may control the display timing of an image on the display panel10by controlling a plurality of driver ICs12A and the gate driver13. The timing controller11may generate a clock signal and supply the same to the driver ICs12A. The timing controller11may supply a scan control signal synchronized with the video data to the gate driver13.

The driver IC12A may be interpreted as a semiconductor device having a receiving circuit, which is described later. The driver ICs12A control the lighting state of a plurality of light-emitting elements provided on the display panel10.

The gate driver13may generate a gate signal based on the signal supplied from the timing controller11and supply the gate signal to the display panel10.

The timing controller11and the driver ICs12A may constitute a communication system200. The communication system200may interpret a system that applies mini-LVDS (low voltage differential signaling). Mini-LVDS may be interpreted as an interface standard for connecting a liquid crystal controller and a liquid crystal driver.

Next, a specific configuration of the communication system200is described with reference toFIG.2.FIG.2is a diagram showing the configuration of the communication system according to the embodiment of the disclosure. The communication system200includes a timing controller11and a signal output circuit12. The timing controller11and the signal output circuit12are communicatively connected via a transmission path3.

The timing controller11includes a transmitting circuit111. The transmitting circuit111may be interpreted as a circuit that transmits data using a differential signal4. The differential signal4includes two signals that change in a complementary manner to each other. Specifically, the differential signal4includes a first signal41transmitted via a first capacitive element1provided in the transmission path3and a second signal42transmitted via a second capacitive element2provided in the transmission path3. The second signal42may be interpreted as a signal whose potential changes complementarily to the first signal41.

The signal output circuit12includes a receiving circuit121and a signal supply circuit122.

The receiving circuit121may be interpreted as an alternating current coupling data receiving circuit that is supplied with a differential signal4transmitted via a capacity element. The alternating current coupling method may be interpreted as a method of removing the direct current component of the input signal and transmitting only the alternating current component to the receiving circuit121. The receiving circuit121has a first input terminal IN1that inputs the first signal41and a second input terminal IN2that inputs the second signal42.

The receiving circuit121outputs a first logic signal51corresponding to the potential of the first signal41and a second logic signal52corresponding to the potential of the second signal42. Specifically, the first signal41and the second signal42are amplified, and the first logic signal51and the second logic signal52having voltage levels higher than the first signal41and the second signal42are output.

The first logic signal51is transmitted to the display panel10shown inFIG.1via a first output terminal OUT1, and is also input to a first input terminal S1of the signal supply circuit122.

The signal supply circuit122may be interpreted as a circuit for guaranteeing the potential of the first signal41and the potential of the second signal42. The signal supply circuit122includes a first input terminal S1that inputs the first logic signal51, a second input terminal S2that inputs the second logic signal52, a first output terminal Q1that outputs a first guarantee signal, and a second output terminal Q2that outputs a second guarantee signal.

The signal supply circuit122may supply a first guarantee signal having a potential corresponding to a value of the first logic signal51to the first input terminal IN1of the receiving circuit121via the first output terminal Q1as a signal for guaranteeing a potential of the first signal41. Further, the signal supply circuit122may supply a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal IN2of the receiving circuit121via the second output terminal Q2as a signal for guaranteeing a potential of the second signal42.

Next, the specific configuration of the signal output circuit12is described with reference toFIG.3.FIG.3is a diagram showing the configuration of the circuit according to the embodiment of the disclosure.

As shown inFIG.3, the receiving circuit121includes a first differential amplifier circuit121aand a second differential amplifier circuit121b.

The first signal41is input to the first differential amplifier circuit121avia the first input terminal IN1, and the second signal42is input to the first differential amplifier circuit121avia the second input terminal IN2. The output of the first differential amplifier circuit121ais input to the second differential amplifier circuit121b. The second differential amplifier circuit121bamplifies the input signals and outputs the same as the first logic signal51and the second logic signal52.

When the first guarantee signal61of a first potential VH is supplied to the first input terminal IN1of the receiving circuit121, the signal supply circuit122supply the second guarantee signal62of a second potential VL lower than the first potential VH to the second input terminal IN2of the receiving circuit121. When the first guarantee signal61of the second potential VL is supplied to the first input terminal IN1of the receiving circuit121, the signal supply circuit122supply the second guarantee signal62of the first potential VH to the second input terminal IN2of the receiving circuit121. The first potential VH and the second potential VL may be interpreted as a reference voltage with a restricted current supply capability.

Specifically, the signal supply circuit122includes a voltage divider circuit122aand a plurality of switches. The plurality of switches include a first switch122b1, a second switch122b2, a third switch122b3, and a fourth switch122b4.

The voltage divider circuit122amay be interpreted as a circuit that generates the first potential VH or the second potential VL by dividing a voltage applied to a resistor provided between two power sources (VDD, VSS). By using the voltage divider circuit122a, the first potential VH or the second potential VL may be generated with a simple configuration by using a power source common to the two power sources (VDD, VSS) supplied to the receiving circuit121.

It is noted that the signal supply circuit122may include a power source that outputs the first potential VH or the second potential VL, instead of the voltage divider circuit122aincluding a resistor.

When a value of the first logic signal51is a specific potential, the first switch122b1is turned on so as to supply the first guarantee signal61of the first potential VH to the first input terminal IN1. Specifically, when the value of the first logic signal51applied to the first input terminal S1is at H level, the first switch122b1is turned on so as to supply the first guarantee signal61of the first potential VH to the first input terminal IN1of the receiving circuit121via the first output terminal Q1.

When the value of the first logic signal51applied to the first input terminal S1is at L level, the first switch122b1is turned off. In this way, the output of the first guarantee signal61of the first potential VH is stopped.

When a value of the second logic signal52is a specific potential, the second switch122b2is turned on so as to supply the second guarantee signal62of the first potential VH to the second input terminal IN2. Specifically, when the value of the second logic signal52applied to the second input terminal S2is at H level, the second switch122b2is turned on so as to supply the second guarantee signal62of the first potential VH to the second input terminal IN2of the receiving circuit121via the second output terminal Q2.

When the value of the second logic signal52applied to the second input terminal S2is at L level, the second switch122b2is turned off. In this way, the output of the second guarantee signal62of the first potential VH is stopped.

When a value of the second logic signal52is a specific potential, the third switch122b3is turned on so as to supply the first guarantee signal61of the second potential VL to the first input terminal IN1. Specifically, when the value of the second logic signal52applied to the second input terminal S2is at H level, the third switch122b3is turned on so as to supply the first guarantee signal61of the second potential VL to the first input terminal IN1of the receiving circuit121via the first output terminal Q1.

When the value of the second logic signal52applied to the second input terminal S2is at L level, the third switch122b3is turned off. In this way, the output of the second guarantee signal62of the second potential VL is stopped.

When a value of the first logic signal51is a specific potential, the fourth switch122b4is turned on so as to supply the second guarantee signal62of the second potential VL to the second input terminal IN2. Specifically, when the value of the first logic signal51applied to the first input terminal S1is at H level, the fourth switch122b4is turned on so as to supply the second guarantee signal62of the second potential VL to the second input terminal IN2of the receiving circuit121via the second output terminal Q2.

When the value of the first logic signal51applied to the first input terminal S1is at L level, the fourth switch122b4is turned off. In this way, the output of the second guarantee signal62of the second potential VL is stopped.

Next, the operation of the signal output circuit12is described with reference toFIG.4,FIG.5, andFIG.6.FIG.4is a diagram for illustrating the operation of the circuit.

State “1” shown inFIG.4represents the following states.(1) The value of the first logic signal51applied to the first input terminal S1is at H level.(2) The value of the second logic signal52applied to the second input terminal S2is at L level.(3) The first switch122b1is turned on.(4) The second switch122b2is turned off.(5) The third switch122b3is turned off.(6) The fourth switch122b4is turned on.(7) The potential applied to the first output terminal Q1is the first potential VH.(8) The potential applied to the second output terminal Q2is the second potential VL.

State “2” shown inFIG.4represents the following states.(1) The value of the first logic signal51applied to the first input terminal S1is at L level.(2) The value of the second logic signal52applied to the second input terminal S2is at H level.(3) The first switch122b1is turned off.(4) The second switch122b2is turned on.(5) The third switch122b3is turned on.(6) The fourth switch122b4is turned off.(7) The potential applied to the first output terminal Q1is the second potential VL.(8) The potential applied to the second output terminal Q2is the first potential VH.

FIG.5andFIG.6are timing charts for illustrating the operation of the circuit.FIG.5shows the first logic signal51, the second logic signal52, and the like when data input to the receiving circuit121, that is, output data of the transmitting circuit111, continues to change.FIG.6shows the first logic signal51, the second logic signal52, and the like when the output data does not change for a certain period of time.

The first signal41input to the first input terminal IN1and the first logic signal51output from the first output terminal OUT1are in phase. The second signal42input to the second input terminal IN2and the second logic signal52output from the second output terminal OUT2are in phase. The first signal41and the second signal42are in opposite phase.

InFIG.5andFIG.6, the following signals are shown in order from the top.(1) The voltage levels of the first signal41and the second signal42, which are data output from the transmitting circuit111.(2) The voltage levels of the first signal41and the second signal42, which are data input to the receiving circuit121.(3) The voltage level of the first logic signal51, which is the data output from first output terminal OUT1.(4) The voltage level of second logic signal52, which is the data output from second output terminal OUT2.(5) The state of the first switch122b1.(6) The state of the second switch122b2.(7) The state of the third switch122b3.(8) The state of the fourth switch122b4.(9) The voltage level of the first output terminal Q1.(10) The voltage level of the second output terminal Q2.(11) A number corresponding to the “state” shown inFIG.4.

(In Case the Output Data Continues to Change)

As shown inFIG.5, when the first signal41is at H level and the second signal42is at L level from timing t1to timing t2, the first logic signal51is at H level, the second logic signal52is at L level, the first switch122b1is turned on, and the second switch122b2is turned off. In addition, the third switch122b3is turned off and the fourth switch122b4is turned on. As a result, the first potential VH from the voltage divider circuit122ais input to the first input terminal IN1via the first output terminal Q1. Further, the second potential VL from the voltage divider circuit122ais input to the second input terminal IN2via the second output terminal Q2.

When the first signal41is at L level and the second signal42is at H level from timing t2to timing t3, the first logic signal51is at L level, the second logic signal52is at H level, the first switch122b1is turned off, and the second switch122b2is turned on. In addition, the third switch122b3is turned on and the fourth switch122b4is turned off. As a result, the second potential VL from the voltage divider circuit122ais input to the first input terminal IN1via the first output terminal Q1. Further, the first potential VH from the voltage divider circuit122ais input to the second input terminal IN2via the second output terminal Q2.

When the first signal41changes to H level and the second signal42changes to L level at timing t3, during the period from timing t3to timing t4, similarly to the period from timing t1to timing t2, the first potential VH is input to the first input terminal IN1, and the second potential VL is input to the second input terminal IN2.

(In Case the Output Data does not Change for a Certain Period of Time)

In the period from timing t2to timing t3inFIG.6, the output data does not change for a certain period of time. Even when the output data does not change in this way, when the first signal41goes to the L level and the second signal42goes to the H level at timing t2, the first logic signal51goes to the L level and the second logic signal52goes to the H level. As a result, the first switch122b1is turned off and the second switch122b2is turned on. In addition, the third switch122b3is turned on and the fourth switch122b4is turned off.

Thus, the second potential VL is input to the first input terminal IN1via the first output terminal Q1. Further, the first potential VH is input to the second input terminal IN2via the second output terminal Q2. Then, the first potential VH and the second potential VL continue to be output until timing t3. Specifically, the potential of the first signal41transmitted via the first capacitive element1and the potential of the second signal42transmitted via the second capacitive element2are guaranteed until timing t3. More specifically, since the input data does not change for a certain period of time, the energy stored in the capacity element continues to be discharged, so that even in a situation where the potentials of the first signal41and the second signal42input to the receiving circuit121may decrease, by adding the first potential VH or the second potential VL to these signals, the potentials of the first signal41and the second signal42input to the receiving circuit121may be guaranteed.

Comparative Example

FIG.7is a diagram showing the communication system according to the comparative example. The communication system200A shown inFIG.7differs from the communication system200shown inFIG.2in that a signal output circuit12B is provided instead of the signal output circuit12. The signal output circuit12B does not include the signal supply circuit122shown inFIG.2, but only the receiving circuit121.

FIG.8is a timing chart for illustrating the operation of the circuit according to the comparative example. InFIG.8, the following signals are shown in order from the top.(1) The voltage levels of the first signal41and the second signal42, which are data output from the transmitting circuit111.(2) The voltage levels of the first signal41and the second signal42, which are data input to the receiving circuit121.(3) The voltage level of the first logic signal51, which is the data output from first output terminal OUT1.(4) The voltage level of second logic signal52, which is the data output from second output terminal OUT2.

As described above, in the alternating current coupling method, a capacity element is provided in a transmission path for the purpose of removing a direct current signal, so that the capacity element is repeatedly charged and discharged while the data input to the receiving circuit121continues to change. In this case, the potentials of the two signals included in the differential signal4that change complementarily to each other, that is, the first signal41and the second signal42, change to H level or L level within a certain period of time. Thus, the receiving circuit121may operate normally according to the differential signal4.

In contrast, in the case where the data does not change for a certain period of time, the energy stored in the capacity element continues to be discharged, and the potentials of the first signal41and the second signal42may decrease to approximately the same level during the period from timing t2ato timing t3inFIG.8. That is, the first signal41and the second signal42may be stuck to each other. As a result, the potentials of the first logic signal51and the second logic signal52of the receiving circuit121also drop, making the output of the receiving circuit121unstable.

As shown inFIG.3, the signal output circuit12according to the embodiment of the disclosure includes a signal supply circuit122, supplying a first guarantee signal61having a potential corresponding to a value of the first logic signal51to the first input terminal IN1as a signal for guaranteeing a potential of the first signal41, and supplying a second guarantee signal62having a potential that changes complementarily to the first guarantee signal61to the second input terminal IN2as a signal for guaranteeing a potential of the second signal42.

With this configuration, even in a situation where the potentials of the first signal41and the second signal42may decrease since the data from the transmitting circuit111does not change for a certain period of time, the potentials of the first signal41and the second signal42may be guaranteed by the guarantee signal from the signal supply circuit122. Thus, the potentials of the first logic signal51and the second logic signal52of the receiving circuit121are guaranteed, so that accurate data transfer may be achieved even when data is not transmitted between the transmitting circuit111and the receiving circuit121for a certain period of time using the alternating current coupling method.

Furthermore, when LVDS is applied to the communication system200of the disclosure, the potentials of the first logic signal51and the second logic signal52are guaranteed, thereby realizing high-speed serial transfer. By realizing high-speed serial transfer, the number of wires between the transmitting circuit111and the receiving circuit121may be reduced, and the manufacturing costs of the substrate associated with the wires may be reduced. Since LVDS is a differential current mode interface, it has high resistance to external noise and may also reduce crosstalk noise.

It is noted that regarding the embodiment of the disclosure described above, the following Appendix is further disclosed.

An alternating current coupling circuit, the circuit includes: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.

In the circuit according to Appendix 1, the signal supply circuit is configured to supply the second guarantee signal of a second potential lower than a first potential to the second input terminal when the first guarantee signal of the first potential is supplied to the first input terminal and supply the second guarantee signal of the first potential to the second input terminal when the first guarantee signal of the second potential is supplied to the first input terminal.

In the circuit according to Appendix 1 or Appendix 2, the signal supply circuit includes a voltage divider circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor provided between two power sources.

In the circuit according to any one of Appendix 1 to Appendix 3, the signal supply circuit includes: a first switch that is turned on when a value of the first logic signal is a specific potential so as to supply the first guarantee signal of the first potential to the first input terminal; a second switch that is turned on when a value of the second logic signal is a specific potential so as to supply the second guarantee signal of the first potential to the second input terminal; a third switch that is turned on when a value of the second logic signal is a specific potential so as to supply the first guarantee signal of the second potential to the first input terminal; and a fourth switch that is turned on when a value of the first logic signal is a specific potential so as to supply the second guarantee signal of the second potential to the second input terminal.

A semiconductor device includes the circuit according to any one of Appendix 1 to Appendix 4.

A communication system includes: a first semiconductor device, having a transmitting circuit for transmitting the first signal and the second signal according to any one of Appendix 1 to Appendix 5; and a second semiconductor device, having the circuit according to any one of Appendix 1 to Appendix 5, wherein the first signal is supplied to the receiving circuit via the first capacitive element, and the second signal is supplied to the receiving circuit via the second capacitive element.