Monolithically integrated resistive structure with power IGBT (insulated gate bipolar transistor) devices

A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a monolithically integrated resistive structure with power IGBT (Insulated Gate Bipolar Transistor) devices.

More specifically, the invention relates to a device being integrated on a semiconductor substrate of a first type of conductivity crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device and a method of manufacture thereof.

2. Description of the Related Art

As it is known, high voltage resistors integrated on a semiconductor material substrate or chip are widely used in the field of monolithically integrated power devices, for example, of devices manufactured with VIPower technology, according to which power devices are integrated in a first region of the chip, called the power region, whereas the relevant control devices are integrated in a second region of the same chip, called the control region, being distinct and electrically insulated from the power region.

Moreover, in other applications, it is also necessary to provide, inside the control region, a biasing voltage derived from a biasing voltage of the substrate by means of a divider realized by using a resistor connected between the substrate and the control region. However, in order for this resistor to be able to withstand the high values the substrate biasing voltage can reach, as it is known (up to 2 kV), it needs to have fairly high resistance values, which generally is 100 kΩ or higher so as to limit the power dissipation given by P=R*l2, P being the dissipated power value, R the resistance value of the resistor and l the current flowing in the resistor.

A prior art solution for manufacturing a resistor having the above cited resistance values provides the integration in a semiconductor substrate of a high resistant doped region having an opposite conductivity with respect to that of the substrate itself.

Although advantageous in several aspects, this solution has various drawbacks when a resistive structure has to be integrated in a semiconductor substrate made for integrating devices of the IGBT type as it is shown inFIG. 1.

In particular, in the case of IGBT applications, on a semiconductor substrate1, which comprises a first region2of the P+type and a second region3of the N type, a highly resistant doped region4is integrated having an opposite conductivity with respect to that of the second region3of the N type whereon it is integrated. This doped region4has a planar configuration and possibly it can also be serpentine-like and it comprises a high voltage resistor5.

The final device14thus comprises an insulating layer6, deposited on the second region3, whereon openings7are formed for performing the electrical connection with a metal layer8formed on the insulating layer6. The final device14is thus completed by forming a substrate electrode9on the back of the semiconductor substrate1.

As it is shown in the figure, the presence of the high voltage resistor5forms a PNP parasite transistor10whereon emitter and collector terminals11and12are respectively connected to the first region2and the doped region4, whereas the base terminal13is connected to the second region3.

Accordingly, there remains a need in the art to provide a monolithically integrated high voltage resistive structure with IGBT devices, having such structural and functional characteristics so as to avoid the growth of parasite transistors and to overcome the limits and drawbacks that still affect the devices realised according to the prior art.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the present invention provides a resistive structure in a same semiconductor layer wherein the device of the IGBT type is integrated, the resistive structure comprising an annular region formed in this semiconductor layer and having a different conductivity with respect to that of the semiconductor layer itself.

Advantageously, a side portion of this annular region forms a body region of the IGBT device.

A further embodiment of the invention provides a method for manufacturing a device integrated on a semiconductor substrate of a first type of conductivity comprising a resistive structure and an IGBT device, comprising, forming a semiconductor layer of a second type of conductivity on said semiconductor substrate, and forming a substantially annular region of the first type of conductivity which surrounds a portion of said semiconductor layer to provide said resistive structure.

The characteristics and advantages of the device and of the method according to the invention will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings.

DETAILED DESCRIPTION OF THE INVENTION

With reference to these drawings, a monolithically integrated resistive structure with a power IGBT (Insulated Gate Bipolar Transistor) device is described.

In particular, with reference toFIGS. 2 and 3a device is globally indicated with15, this device being integrated on a semiconductor substrate16, for example of the P+type, and comprising a resistive structure17and, by way of mere non limiting-example, a power IGBT transistor18having vertical structure.

In particular, the resistive structure17is integrated on a first semiconductor layer19, for example, of the N−type, which is formed on the semiconductor substrate16. The first semiconductor layer19is advantageously an epitaxial layer.

Advantageously, a second semiconductor layer20is present between the first semiconductor layer19of the N−type and the semiconductor substrate16. The second semiconductor layer20is also, for example, an epitaxial layer of the N+type.

The resistive structure17according to the invention comprises a closed region21a, for example of the annular type, of the P+type. The annular region21asurrounds a portion22of the first epitaxial layer19thus allowing the surround portion22to be laterally insulated from the region21a.

As shown inFIG. 2, a plurality of regions21acan be formed adjacent one another and parallelly connected in order to obtain a less resistive structure17. Thanks to this parallel configuration of the resistive structure17it is possible to fix resistive values with low tolerances.

In a preferred embodiment these resistive structures17are matrix arranged.

Advantageously, the device15comprises a transistor IGBT18formed by a vertical transistor MOS which drives a bipolar transistor. The conductive electrodes of the bipolar transistor are formed by the semiconductor substrate16and by a region21b. Region21b, for example, of the P type, called a body region, can be formed in the first epitaxial layer19, whereas the driving terminal is formed by the first epitaxial layer19itself.

The vertical MOS transistor comprises the body region21bwherein a source region23is integrated, for example of the N type. A gate region24, insulated from the first semiconductor layer19by means of an insulating layer25, completes the IGBT transistor18.

Advantageously, a side portion of the annular region21a, wherein a source region23is integrated, can be used as body region21bfor the IGBT transistor.

The resistive structure17is thus provided with an upper electrode26which contacts the portion22of the first semiconductor layer19, the upper electrode26being insulated from the portion21awith the first semiconductor layer19arranged on the back of the semiconductor substrate16.

The lower electrode27also forms a first output electrode of the IGBT device18, whereas a further electrode28which contacts the source regions23and which is insulated from the gate regions24by means of an insulating layer25, forms a second output electrode of the IGBT device18.

The method for manufacturing the integrated device15is now described, the device comprising the resistive structure17and the power transistor18according to the invention. In particular, on a monocrystalline silicon semiconductor substrate16with high doping impurity concentration of the P+type, a first epitaxial layer19is formed having a thickness and an impurity concentration chosen according to the highest voltage the integrated device15must be able to withstand; typically, the concentration of the impurities being present in the first epitaxial layer19varies between 1013and 1014atoms/cm3, whereas the thickness of the first epitaxial layer19is generally between 50 and 80 μm.

Advantageously, a second epitaxial layer20with higher concentration of the doping impurity of the same type as in19(e.g., N type) is formed between the first epitaxial layer19and the semiconductor substrate16. On the epitaxial layer19a plurality of regions21of the P+type is thus formed by ionic implantation and subsequent diffusion process. In particular, an annular-shaped first region21asurrounding a portion22of the epitaxial layer19is formed. According to the invention, the first region21aand the surrounded portion22form the resistive structure17.

On the epitaxial layer19a plurality of second regions21bare further realised which form a plurality of body regions, interconnected with each other, of a single IGBT transistor18. In fact the IGBT transistor18described in the figures by way of non-limiting example is formed with cells being interconnected with each other according to a mesh.

Nothing forbids the resistive structure17according to the invention to be formed together with a conventional IGBT device18.

The IGBT device18is completed through conventional steps which provide processes of deposition, photolithography and diffusion for forming source regions23of the N+type inside the body regions21b.

Advantageously, a region23aof the N+type is formed inside the portion22contained by the P+ring21ain order to form a surface contact with low resistivity of the portion22of the resistive structure17.

After having deposited an insulating layer24throughout the surface of the device15, gate electrodes24of the IGBT transistor18are formed inside this insulating layer24.

After having formed openings in correspondence of the source regions23and of the region22, through known processes of deposition and photolithography, an upper electrode26of the resistive structure17and an output electrode28of the IGBT transistor18are formed.

The device15is thus completed by forming an electrode27on the back of the device, to provide the lower electrode of the resistive structure17and simultaneously another output electrode of the IGBT transistor18.

Finally, the resistive structure17according to the invention has a totally vertical structure and current flux, a resistance which is a function of the volume of semiconductor material surrounded by the annular region21a, and an electrical behaviour which is a function of the depth of the annular region21a. In particular, the resistance value of the resistive structure17depends on the voltage applied to the portion22and to the annular region21a, and the resistive structure thus obtained acts as a resistive structure being voltage controlled. In one embodiment wherein a portion of the annular region21ais used as body region of the IGBT transistor18, the voltage of the annular region21ais kept fixed whereas the voltage applied to the portion22is changed. In this way, by integrating the resistive structure17with the IGBT transistor18, the biasing of the IGBT transistor18itself is not altered and, by applying a voltage different from zero to the portion22it is possible to obtain different resistance values across the resistive structure17according to the invention.

FIG. 4particularly shows the different resistance values being achievable across the resistive structure17when the voltage applied to the portion22varies.

In conclusion, the device15according to the invention allows for the integration of a resistive structure of minimum space in terms of silicon area used, with total freedom of arrangement inside a conventional IGBT structure, at the same time, eliminates the parasite effects which would jeopardise or limit the electrical characteristics.