Memory device for protecting memory cells during programming

Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to U.S. application Ser. No. 11/552,441, filed concurrently herewith, and entitled “METHOD FOR PROTECTING MEMORY CELLS DURING PROGRAMMING,” which is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to memory devices and, more particularly, to programming non-volatile memory devices.

2. Description of the Related Art

Memory devices that provide persistent data storage use non-volatile memory cells. The memory devices can typically be implemented by semiconductor chips. The semiconductor chips can be used internal to electronic systems or can be used within memory cards that can be removably attached to electronic systems. Memory cards are commonly used to store digital data for use with various products (e.g., electronic products). Memory cards often use Flash type or EEPROM type memory cells to store the data. Memory cards have a relatively small form factor and have been used to store digital data for electronic products (e.g., portable consumer electronic products). A major supplier of memory cards is SanDisk Corporation of Sunnyvale, Calif.

Several methods are known for programming non-volatile memory cells. One method applies a programming pulse of a sufficiently long duration to program a memory cell. In order to guarantee that every memory cell is able to be programmed using this method, programming time and power are set for worst-case conditions. Accordingly, this “over-provisioning” approach can result in excessive average programming time and power. In another method, a series of short, high-voltage programming pulses is applied to a memory cell. After each programming pulse, a nominal-voltage reading pulse is applied to determine whether the memory cell is in a programmed state. If the memory cell is in a programmed state, no further programming pulses are applied. Otherwise, an additional programming pulse is applied, and the sequence of reading and programming continues until the memory cell is eventually in a programmed state. One disadvantage of this approach is the time and power overhead associated with switching between program and read voltages. Another disadvantage of this approach is that the use of short programming pulses (as compared to a long, continuous programming pulse) tends to be less energy efficient.

More recently, a method for programming non-volatile memory cells made use of detection circuits. While a particular memory cell is being programmed, a detection circuit determines whether the memory cell is in a programmed state. Once the memory cell is detected to have reached the programmed state, the programming of the memory cell is terminated. Additional details on this method for programming are provided in U.S. Pat. No. 6,574,145. However, in programming memory cells, the memory cells can be subjected to high voltages and high power which are problematic when the memory cells become programmed and the programming voltage has not yet been removed. Although the programming voltage will be removed in due time after a memory cell has been programmed, the excessive power can cause damage to the already programmed memory cell.

Thus, there is still a need for improved memory devices and programming methods.

SUMMARY OF THE INVENTION

The invention relates to improved circuitry and methods for programming memory cells of a memory device. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card. The invention can be particularly useful for use with two-terminal memory cells.

The invention can be implemented in numerous ways, including as a method, system, device or apparatus. Several embodiments of the invention are discussed below.

As a memory device, one embodiment of the invention includes at least: a non-volatile memory element; a current monitor configured to monitor a program current flowing through the non-volatile memory element; and a current limiter configured to restrict the current flowing through the non-volatile memory element.

As a memory device, another embodiment of the invention includes at least: a memory array including a plurality of layers of memory cells stacked vertically above one another in a single chip; a detection circuit operative to detect, while a memory cell of the memory array is being programmed, when the memory cell is in a programmed state; and a memory cell protection circuit operative to protect the memory cell of the memory array against excessive electrical energy at least while the memory cell is being programmed.

As a memory device having an array of memory elements accessible via at least one bitline and at least one wordline, one embodiment of the invention includes at least: a first field-effect transistor having first, second and third terminals, the first terminal connected to a first potential; a second field-effect transistor having first, second and third terminals, the first terminal connected to the second terminal of the first field-effect transistor, and the second terminal connected to a bitline; a memory element connected to a wordline and to the bitline; a third field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a first node, and the third terminal connected to the third terminal of the first field-effect transistor; a fourth field-effect transistor having first, second and third terminals, the first terminal connected to the first node, the second terminal connected to a second potential; a fifth field-effect transistor having first, second and third terminals, the first terminal connected to a first current source, the second terminal connected to the second potential, and the third terminal is connected to the third terminal of the fourth field-effect transistor, the first terminal further being connected to the third terminal; a sixth field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a second node, and the third terminal connected to the third terminal of the first field-effect transistor; a seventh field-effect transistor having first, second and third terminals, the first terminal connected to the second node, the second terminal connected to the second potential; an eighth field-effect transistor having first, second and third terminals, the first terminal connected to a second current source, the second terminal connected to the second potential, and the third terminal is connected to the third terminal of the seventh field-effect transistor, the first terminal further being connected to the third terminal; program control circuitry connected to the second node; and a ninth field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to the third terminal of the first field-effect transistor, and the third terminal connected to the program control circuitry, wherein the third terminal of the second field-effect transistor is connected to the first node.

As an electronic system, one embodiment of the invention includes at least: a data acquisition device; and a data storage device removably coupled to the data acquisition device. The data storage device stores data acquired by the data acquisition device. The data storage device includes at least: an array of data storage elements; a detection circuit operative to detect, while a data storage element of the array is being programmed, when the data storage element is in a programmed state; and a protection circuit operative to protect the data storage element of the array against excessive electrical energy at least while the memory cell is being programmed.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to improved circuitry and methods for programming memory cells of a memory device. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card. The invention can be particularly useful for use with two-terminal memory cells.

FIG. 1is a block diagram of a memory device100according to one embodiment of the invention. The memory device100includes a memory element102. The memory element102is, for example, a non-volatile memory element. One implementation for a non-volatile memory element is a diode or antifuse type memory element. The memory element102is typically part of a memory array. The various memory elements within the memory array can be accessed by way of bitlines104and wordlines106. Hence, the memory element102is shown as being coupled between a bitline104and a wordline106. When programming the memory element102, a voltage is applied across the memory element102to invoke a physical characteristic change in the memory element102. As an example, when the memory element102corresponds to an antifuse type device, the programming of the memory element102is referred to as “popping” or “blowing” the antifuse.

The memory device100includes a programming switch108. The programming switch108couples to a voltage potential (Vp) used for programming. When the programming switch108is enabled by a program control circuit110, a program current (Ipmg) is supplied from the voltage potential (Vp) to a current monitor112. The current monitor112monitors the program current (Ipmg) that flows through the memory element102. Here, in this embodiment, the amount of current flowing through the memory element102provides an indication of whether or not the memory element102has been programmed. In other words, while the memory element102is being programmed by the program current (Ipmg), the current monitor112monitors the level of the program current (Ipmg). The monitored current level detected by the current monitor112is supplied to the program control circuit110. The program control circuit110based on the monitored current level determines whether the memory element102has been completely programmed. When the program control circuit110determines that the memory element102has been programmed, the program control circuit110can signal the programming switch108to deactivate the programming. In one embodiment, the program control circuit110can impose a delay prior to deactivating the programming.

The memory device100also includes a current limiter114. The current limiter114operates to limit the maximum amount of current that is permitted to be used when programming the memory element102. In other words, the current limiter114prevents the program current (Ipmg) from exceeding a maximum current level. The current limiter114thus protects the memory element102from damage during or after programming of the memory element102.

Besides providing protection for a memory element during programming, a current limiter can also protect a memory element when not being programmed. For example, in some embodiments, a pre-charging is performed in advance of programming to improve the programming. Hence, the protection for the memory cells can also be used to protect the memory elements during pre-charging.

The programming of the memory cells can be efficient with regard to programming time and power. For example, a memory cell can be pre-charged rapidly since the current used for pre-charge can be set to the maximum level that the memory cell can withstand. Additionally, in programming a memory cell, programming occurs only for as long as it is needed. That is, unlike a fixed program duration, once a memory cell becomes programmed, its programming can be stopped. Further, programming bandwidth (the number of memory cells that can be programmed per unit time) can be high. In one embodiment, a plurality of memory cells along a wordline can be programmed simultaneously.

The memory element being programmed can relate to a non-volatile memory cell (i.e., a memory cell whose data is not lost or altered when electrical power is removed). Although any suitable memory array can be used, in one embodiment, the memory cell is part of a three-dimensional memory array, which can provide economies in terms of reduced size and associated reductions in manufacturing cost. In one implementation, the memory array can include a vertical array of layers as memory cells. The memory array can be part of a compact, modular memory device used with portable consumer electronic products. In one embodiment, the memory cell is field-programmable. A field-programmable memory cell is a memory cell that is fabricated in an initial, un-programmed digital state and can be switched to an alternative, programmed digital state at a time after fabrication. Although any suitable type of memory cell can be used, in one embodiment, the memory cell is a write-once memory cell comprising an antifuse and a diode, for example as described in U.S. Pat. No. 6,034,882 and U.S. Pat. No. 6,515,888, both of which are hereby incorporated by reference. In its un-programmed state, the antifuse is intact, and the memory cell holds a Logic 1. When suitable voltages are applied to the appropriate wordline and bitline, the antifuse of the memory cell is blown, and the diode is connected between the wordline and the bitline. This places the memory cell in a programmed (Logic 0) state. Alternatively, the un-programmed state of the memory cell can be Logic 0, and the programmed state can be Logic 1. Memory cells that support multiple programmed states can also be used. If the memory is of the write-once type, the initial, un-programmed digital state cannot be restored once the memory cell is switched to the programmed digital state. Instead of being write-once, the memory cell can be write-many (re-writeable). Unlike the digital state of a write-once memory cell, the digital state of a write-many memory cell can be switched between “un-programmed” and “programmed” digital states. When referring to write-many memory cells, the un-programmed digital state refers to the digital state of the memory cell before a programming operation. Accordingly, the un-programmed digital state can refer to either Logic 0 or Logic 1 (in a two-state memory cell) and does not necessarily refer to the digital state in which that memory cell was fabricated.

FIG. 2is a flow diagram of a memory programming process200according to one embodiment of the invention. The memory programming process200is, for example, associated with programming a memory element, such as a memory element within a memory array provided within a memory device.

The memory programming process200initially activates202programming of a memory element. The memory element is one of a plurality of memory elements provided within a memory device. For example, the memory element to be programmed can pertain to the memory element102of the memory device100illustrated inFIG. 1.

A decision204then determines whether a program current (programming current) is greater than or equal to a maximum current. When the decision204determines that the program current is greater than or equal to the maximum current, the program current is limited206to the maximum current. Following the block206, or following the decision204when the program current is not greater than or equal to the maximum current, a decision208determines whether the program current is greater than or equal to a sense current. The sense current is an amount of current used to sense whether the programming element has been programmed. When the decision208determines that the program current is not greater than or equal to the sense current, then the memory programming process200returns to repeat the decision204and subsequent blocks so that the programming of the memory element can continue. In doing so, the memory element is protected from damage by the block206which prevents the program current from exceeding the maximum current. On the other hand, when the decision208determines that the program current is greater than the sense current, then programming of the memory element is deactivated210. Here, the programming of the memory element is deactivated210because the memory element has been programmed. In other words, when the program current reaches the level of the sense current, then the memory element is programmed. Following the block210, the memory programming process200ends.

Hence, in one embodiment, the programming of a memory element is efficient and effective. First, the program current used during programming can be high since the program current is guaranteed not to exceed the maximum current for the memory element. The high program current leads to rapid programming of the memory element. Second, the program time for the memory element is optimized to the memory element itself. That is, when the memory element becomes programmed, the programming of the memory element ceases.

FIG. 3is a schematic diagram of a memory device300according to one embodiment of the invention. The memory device300includes a memory element302. As depicted inFIG. 3, the memory element302is being programmed (written). The memory element302is coupled between a bitline304and a wordline306, which enables selection of the memory element302from a plurality of memory elements in the memory device300. The memory element302is programmed by supplying a programming voltage across the memory element302which induces a program current (Ipmg) through the memory element302. The program current (Ipmg) is supplied by a field-effect transistor (FET)308.

The program current (Ipmg) is also limited by a FET310. The FET310is controlled by a node312. The node312is provided between a FET314and a current source (Imax)316. When the program current (Ipmg) exceeds the maximum current (Imax), the node312is pulled high by the FET314. As a result, in such case, the FET312operates to restrict or stop the program current (Ipmg) from reaching the memory element302.

The memory device300also includes a FET318that couples between the programming potential (Vp) and a node320. The node320is also coupled to ground by way of a sense current source (Is)322. When the program current (Ipmg) exceeds the sense current (Is), the second node320is pulled high by the FET318. In such case, the program control circuit324can cause a FET326to turn off the FET308, thereby ceasing programming of the memory element302. Additionally, when the second node320is pulled high by the FET318, the program control circuit324can cause a FET328to turn off, thereby disconnecting the gate of the FET308from the drain of the FET308. The program control circuit324can turn off the FET328via an inverter330. In one implementation, the program control circuit324can induce a delay and thus need not be immediately responsive to a change in voltage level of the second node320.

FIG. 4is a schematic diagram of a memory device400according to another embodiment of the invention. The memory device400illustrated inFIG. 4is generally similar to the memory device300illustrated inFIG. 3. However, the memory device400includes additional implementation details that can be provided in accordance with one embodiment of the invention.

The memory device400includes a memory element402. The memory element402is coupled between a bitline404and a wordline406. The memory device400operates, in one mode, to program the memory element402by applying a voltage across the memory element402. The result of the voltage across the memory element402is to effectuate programming of the memory element. In one implementation, as the memory element402is being programmed, the program current (Ipmg) passing through the memory element402increases. At some point, the level of the program current (Ipmg) can signal that the memory element402has been adequately programmed.

The memory device400includes a first FET408that couples to a voltage potential (Vp) suitable for programming. The first FET408is utilized to provide the program current (Ipmg) that is used to program the memory element402. A second FET410couples between the first FET408and the memory element402. The second FET410is utilized to limit the amount of current that can flow through to the memory element402. In other words, the FET410is controlled to limit the program current (Ipmg) to a maximum level. A third FET412is also provided to bias a gate terminal of the FET408. A source terminal of the FET408is coupled to the voltage potential (Vp) and a drain terminal of the FET408is coupled to a drain terminal of the FET410at a node413. A source terminal of the FET410is coupled to the memory element402by way of the bitline404. A drain terminal of the FET412is coupled to the voltage potential (Vp), a gate terminal of the FET412is connected to the node413, and a source terminal of the FET412is coupled to the gate terminal of the FET408as well as to a bias current source (Ibias)414.

To control the FET410, the memory device400also includes a FET415, a node416, and FETs418and420. The FET415has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET408, and a drain terminal connected to the node416. The gate terminal of the FET410also connects to the node416. The FETs418and420are connected to form a current mirror circuit for a maximum reference current (Imax).

During operation, the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET408is mirrored to the FET415. This program current (Ipmg) is compared to a maximum current (Imax) at the node416. If the program current exceeds the maximum current, the node416is pulled high so as to restrict or prevent the program current (Ipmg) from being provided to the memory element402.

The memory device400also includes a FET422, a node424, and FETs426and428. The FET422has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET408and a drain terminal connected to a node424. The FETs426and428provide a current mirror circuit for a sense reference current (Is). A drain terminal of the FET426is coupled to the node424. The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET408is mirrored to the FET422. Hence, the node424can determine whether the program current (Ipmg) exceeds the sense reference current (Is). When the program current (Ipmg) exceeds the sense reference current (Is), the node424is pulled high. When the node424is pulled high, a program control circuit430understands that the programming of the memory element402has been completed. At this point, either immediately or following a predetermined delay, the program control circuit430can instruct a FET432to disable further programming of the memory element402. The FET432has its source terminal connected to the voltage potential (Vp) and a drain terminal connected to the gate terminal of the FET408. Further, the gate terminal of the FET432is connected to the program control circuit430.

To reduce power consumption, the current mirror circuits can use a different ratio than the programming circuitry. For example, the channel width for the FETs415and422can be made smaller than the channel width of the FET408, thereby producing lower currents in the current mirror circuits which in turn reduces power consumption. As another example, the FET408could be manufactured to be N-times that of the FETs415and422, where N is the desired current ratio. In such an example, the FET408can be implemented using N transistors used in parallel relative to using one transistor for the FETs415and422.

FIG. 5is a schematic diagram of a memory device500according to another embodiment of the invention. The memory device500illustrated inFIG. 5provides separate circuitry for monitoring programming and limiting program current as do the memory device300illustrated inFIG. 3and the memory device400illustrated inFIG. 4. The memory device500utilizes a double current mirror design.

The memory device500includes a memory element502. The memory element502is coupled between a bitline504and a wordline506. The memory device500operates, in one mode, to program the memory element502by applying a voltage across the memory element502. The result of the voltage across the memory element502is to effectuate programming of the memory element502. In one implementation, as the memory element502is being programmed, the program current (Ipmg) passing through the memory element502increases. At some point, the level of the program current (Ipmg) can signal that the memory element502has been adequately programmed.

The memory device500includes a first FET508that couples to a voltage potential (Vp) suitable for programming. The first FET508is utilized to provide the program current (Ipmg) that is used to program the memory element502. A second FET510couples between the first FET508and the memory element502. The second FET510is utilized to limit the amount of current that can flow through to the memory element502. In other words, the FET510is controlled to limit the program current (Ipmg) to a maximum level. A source terminal of the FET508is coupled to the voltage potential (Vp) and a drain terminal of the FET508is coupled to a drain terminal of the FET510. A source terminal of the FET510is coupled to the memory element502by way of the bitline504. A third FET512, a fourth FET514and a current source (Imax)516are connected in series to bias a gate terminal of the FET510such that the program current (Ipmg) does not exceed the maximum current (Imax). The FETs510and512are connected to form a current mirror circuit for a maximum reference current (Imax).

The memory device500also includes a FET518, a current source (Is)520and a node522. The FET518has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET508and a drain terminal connected to the node522. The FETs508and510provide another current mirror used to compare the program current (Ipmg) with a sense reference current (Is). The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET508is mirrored to the FET518. Hence, the node522can determine whether the program current (Ipmg) exceeds the sense reference current (Is). When the program current (Ipmg) exceeds the sense reference current (Is), the node522is pulled high. When the node522is pulled high, a program control circuit (not shown) understands that the programming of the memory element502has been completed. At this point, either immediately or following a predetermined delay, the program control circuit can disable further programming of the memory element502.

FIG. 6is a schematic diagram of a memory device600according to another embodiment of the invention. The memory device600illustrated inFIG. 6provides separate circuitry for monitoring programming and limiting program current. The memory device600utilizes a current mirror and a replicated memory element current path.

The memory device600includes a memory element602. The memory element602is coupled between a bitline604and a wordline606. The memory device600operates, in one mode, to program the memory element602by applying a voltage across the memory element602. The result of the voltage across the memory element602is to effectuate programming of the memory element602. In one implementation, as the memory element602is being programmed, the program current (Ipmg) passing through the memory element602increases. At some point, the level of the program current (Ipmg) can signal that the memory element602has been adequately programmed.

The memory device600includes a first FET608that couples to a voltage potential (Vp) suitable for programming. The first FET608is utilized to provide the program current (Ipmg) that is used to program the memory element602. A source terminal of the FET608is coupled to the voltage potential (Vp) and a drain terminal of the FET608is coupled to the memory element602by way of the bitline604. A second FET610and a current source (Imax)612are connected in series. A source terminal of the FET610is coupled to the voltage potential (Vp) and a drain terminal of the FET610is coupled to the current source (Imax)612. The gate terminals of the FETs608and610are connected together. The FET610and the current source (Imax)612operate to bias a gate terminal of the FET608such that the program current (Ipmg) does not exceed the maximum current (Imax). In other words, the FETs608and610are connected to form a current mirror circuit that operates to prevent the program current (Ipmg) from exceeding a maximum reference current (Imax).

The memory device600also includes a FET614, a comparator616and a FET518to replicate the memory element current path. The FETs614and618are connected in series between the voltage potential (Vp) and ground. A node615is provided at the connection of the FETs614and618. The comparator616compares the voltage at the node615with the voltage at node617, which is at the connection of the FET608and the memory element602. The output of the comparator616serves to bias the gate terminal of the FET618such that a monitored current (Im) is substantially the same (i.e., replicated) as the program current (Ipmg). Further, the memory device includes a FET620and current source (Is)622. The current source (Is)622is connected to the voltage potential (Vp) and to a node624. The FET620is connected between the node622and ground. The gate of the FET620is connected to the gate of the FET618such that a mirrored monitored current (Im′) is drawn from the node624by the FET620. Hence, the node624can determine whether the program current (Ipmg) exceeds the sense reference current (Is). When the program current (Ipmg) exceeds the sense reference current (Is), the node622is pulled low. When the node622is pulled low, a program control circuit (not shown) understands that the programming of the memory element602has been completed. At this point, either immediately or following a predetermined delay, the program control circuit can disable further programming of the memory element602.

FIG. 7is a schematic diagram of a memory device700according to another embodiment of the invention. The memory device700illustrated inFIG. 7provides monitoring for both programming current and excessive current.

The memory device700includes a memory element702. The memory element702is coupled between a bitline704and a wordline706. The memory device700operates, in one mode, to program the memory element702by applying a voltage across the memory element702. The result of the voltage across the memory element702is to effectuate programming of the memory element702. In one implementation, as the memory element702is being programmed, the program current (Ipmg) passing through the memory element702increases. At some point, the level of the program current (Ipmg) can signal that the memory element702has been adequately programmed.

The memory device700includes a first FET708that couples to a voltage potential (Vp) suitable for programming. The first FET708is utilized to provide the program current (Ipmg) that is used to program the memory element702. A second FET710couples between the first FET708and the memory element702. The second FET510can be utilized to limit the amount of current that can flow through to the memory element702. For example, the FET710can be controlled to limit the program current (Ipmg) to a maximum level. A source terminal of the FET708is coupled to the voltage potential (Vp) and a drain terminal of the FET708is coupled to a drain terminal of the FET710. A source terminal of the FET710is coupled to the memory element702by way of the bitline704.

The memory device700also includes a FET712and a current source (Is)714and a node716. The FET712has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET708and a drain terminal connected to the node716. The FETs708and712provide a first current mirror used to compare a mirrored program current (Ipmg′) with a sense reference current (Is). The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET708is mirrored to the FET712. Hence, the node716can determine whether the mirrored program current (Ipmg′) exceeds the sense reference current (Is). When the mirrored program current (Ipmg′) exceeds the sense reference current (Is), the node716is pulled high. When the node716is pulled high, a program control circuit718understands that the programming of the memory element702has been completed. At this point, either immediately or following a predetermined delay, the program control circuit718can disable further programming of the memory element702in any of a number of ways (including through use of the FET710).

Still further, the memory device700also includes a FET720and a current source (Imax)722and a node724. The FET720has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET708and a drain terminal connected to the node724. The FETs708and720provide a second current mirror used to compare a mirrored program current (Ipmg″) with a maximum current (Imax). The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET708is mirrored to the FET720. Hence, the node724can determine whether the mirrored program current (Ipmg″) exceeds the maximum current (Imax). When the mirrored program current (Ipmg″) exceeds the maximum current (Is), the node724is pulled high. When the node724is pulled high, a current limit control726understands that the program current is excessive and should be limited. At this point, the current limit control726can disable further programming of the memory element702. For example, as shown inFIG. 7, the current limit control726can supply a control signal (CTRL) to the gate of the FET710so that the program current (Ipmg) does not exceed the maximum current (Imax). In this embodiment, the limiting of the program current (Ipmg) is not directly provided in an analog domain as one or more other embodiments, but is instead provided by feedback control (e.g., in a digital domain) which has some inherent delay.

The invention can be particularly useful for use with two-terminal memory cells. Two-terminal memory cells, for example, can be formed from polysilicon diodes, transition metal oxide (e.g., NiO) memory elements, and chalcogenide-based memory elements. Two-terminal memory arrays can be formed in a compact manner when arranged into cross-point memory arrays. Additional details on some two-terminal memory cells are provided in the following papers which are hereby incorporated herein by reference: (i) Pirovano et al., “Electronic Switching in Phase-Change Memories,” IEEE Transactions on Electronic Devices, Vol. 51, No. 3, March 2003; (ii) Baek et al., “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application,” IEEE International Electron Devices Meeting, IEEE, 2005; (iii) Baek et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses,” IEEE International Electron Devices Meeting, IEEE 2004; and (iv) Hwang et al., “Writing Current Reduction for High-density Phase-change RAM,” IEEE International Electron Devices Meeting, IEEE, 2003. Additional details are also provided in U.S. Pat. No. 6,891,748, which is hereby incorporated herein by reference.

Additional details on detecting whether a memory cell being programmed is in a programmed state are provided in U.S. Pat. No. 6,574,145, which is hereby incorporated herein by reference. For additional information on program current control when programming memory elements, see (i) U.S. patent application Ser. No. 11/552,462, filed concurrently herewith, and entitled “METHOD FOR CONTROLLING CURRENT DURING PROGRAMMING OF MEMORY CELLS”, which is hereby incorporated herein by reference; and (ii) U.S. patent application Ser. No. 11/552,472, filed concurrently herewith, and entitled “MEMORY DEVICE FOR CONTROLLING CURRENT DURING PROGRAMMING OF MEMORY CELLS”, which is hereby incorporated herein by reference.

The invention is suitable for use with both single-level (binary) memories and multi-level (multi-state) memories. In multi-level memories, each data storage element stores two or more bits of data.

As used herein “operatively connected” refers to direct or indirect electrical connection between electrical components.

The various features, aspects, embodiments or implementations can be used alone or in any combination.

The invention can further pertain to an electronic system that includes a memory system as discussed above. A memory system is a system that includes at least a memory device that provides data storage. Memory systems (i.e., memory cards) are commonly used to store digital data for use with various electronics products. The memory system is often removable from the electronic system so the stored digital data is portable. The memory systems according to the invention can have a relatively small form factor and be used to store digital data for electronics products (e.g., consumer electronic products) that acquire data, such as cameras, hand-held or notebook computers, network cards, network appliances, set-top boxes, hand-held or other small media (e.g., audio) players/recorders (e.g., MP3 devices), personal digital assistants, mobile telephones, and medical monitors.

The advantages of the invention are numerous. Different embodiments or implementations may yield one or more of the following advantages. One advantage of the invention is that a programming current used to program a memory element (i.e., memory cell) is limited so as not exceed a maximum current. This serves to protect the memory element from potentially damaging high current levels, such as while programming the memory element or at other times. Another advantage of the invention is that sensing current to monitor programming of a memory element can be provided separate from limiting programming current to a maximum current. Still another advantage of the invention is that a higher programming voltage can be used for faster programming since the program current is otherwise limited to the maximum current. Another advantage of the invention is that memory elements to be programmed can be pre-charged while protecting the memory elements from excessive currents. Yet another advantage of the invention is that programming time to program a memory element can be optimized.

The many features and advantages of the present invention are apparent from the written description. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation as illustrated and described. Hence, all suitable modifications and equivalents may be resorted to as falling within the scope of the invention.