Compound semiconductor device and manufacturing method of the same

An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-334793, filed on Dec. 26, 2008, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are directed to a compound semiconductor device and a manufacturing method thereof.

BACKGROUND

Conventionally, a study relating to a high electron mobility transistor (HEMT) in which an AlGaN layer and a GaN layer are formed over a substrate by crystal growth, and the GaN layer functions as an electron transit layer has been performed. A band gap of GaN is 3.4 eV, and it is larger than a band gap of GaAs (1.4 eV). Accordingly, a withstand voltage of a GaN based HEMT is high, and it is expectable as a high withstand voltage electronic device for automobiles and so on.

Besides, there are a horizontal structure, in which a source and a drain are disposed in parallel to a surface of a substrate, and a vertical structure, in which a source and a drain are disposed perpendicularly to a surface of a substrate, as structures of the GaN based HEMT.

In the GaN based HEMT, a current flows in a channel because two-dimensional electron gas (2DEG) resulting from a difference between lattice constants exists at the channel positioning in a vicinity of a gate electrode, caused by a structure of the GaN based HEMT even in a case when a voltage is not applied to the gate electrode. Namely, a normally-on operation is performed. On the other hand, it is also conceivable that current flows between the source and the drain when “0” (zero) V is unintentionally applied to the gate electrode, when a power is turned on, when the gate electrode is broken, or the like. Accordingly, a normally-off operation of the GaN based HEMT is desired from a point of view of fail-safe.

It is known that the normally-off operation is enabled by a structure in which a recess is formed at a compound semiconductor layer positioning directly below the gate electrode (gate recess structure) as for the GaN based HEMT having the horizontal structure.

However, in the gate recess structure as stated above, the normally-off operation is enabled, but a threshold voltage is 1 V or less, and a leak current may be generated even though the gate voltage is “0” (zero) V. Besides, it is difficult to use it for an electronic device to which a high voltage is applied if the threshold voltage is 1 V or less, because noise increases and operations become unstable when the high voltage is applied. It is possible to increase the threshold voltage by changing a material from the GaN based material, but it may result in a case that a sufficient current cannot be obtained, or it becomes easy to break only by changing the material.

On the other hand, a study has also been performed to enable the normally-off operation in the GaN based HEMT having the vertical structure, but mass production thereof is difficult by either method.

The following are examples of related art of the present invention: Japanese Laid-open Patent Publication No. 2006-140368; International Publication Pamphlet No. WO 2006/001369; and Japanese Journal of Applied Physics vol. 46, No. 21, 2007, pp. L503-L505.

SUMMARY

According to an aspect of the embodiment, a first compound semiconductor device includes: an electron transit layer; a compound semiconductor layer formed over the electron transit layer; and a source electrode, a drain electrode and a gate electrode formed over the compound semiconductor layer. A recess portion is formed inside an area between the source electrode and the drain electrode of the compound semiconductor layer and at a portion separating from the gate electrode.

According to another aspect of the embodiment, a second compound semiconductor device, includes: an electron transit layer; a compound semiconductor layer formed over the electron transit layer; a gate electrode and a source electrode formed over the compound semiconductor layer, and a drain electrode formed below the electron transit layer. A recess portion is formed inside an area between the source electrode and the gate electrode of the compound semiconductor layer.

Additional objects and advantages of the embodiment will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DESCRIPTION OF EMBODIMENTS

First Embodiment

First, a first embodiment is described.FIG. 1is a sectional view illustrating a structure of a GaN based HEMT (compound semiconductor device) according to the first embodiment.

In the first embodiment, an undoped i-AlN layer2with a thickness of approximately 1 μm to 100 μm (for example, 25 μm) is formed on a substrate1such as an n-type conductive single-crystal SiC substrate. Relatively large concaves and convexes exist at a surface of the i-AlN layer2. An undoped i-AlN layer3of which thickness is 100 nm or less (for example, 20 nm to 50 nm) is formed on the i-AlN layer2. A GaN layer4of which thickness is approximately 0.1 μm to 10 μm (for example, 0.5 μm) is formed on the i-AlN layer3. Fe, which is a transition metal element, is contained in the GaN layer4as an impurity. A content ratio of Fe is, for example, approximately 1×1018cm−−3to 1×1020cm−−3. The thickness of the GaN layer4is approximately 0.1 μm to 10 μm, and therefore, a surface of the GaN layer4is flat even though the concaves and convexes exist at the surface of the i-AlN layer2. An undoped i-GaN layer5of which thickness is approximately 0.1 μm to 10 μm is formed on the GaN layer4. Fe is not contained in the i-GaN layer5. An n-type n-AlGaN layer6of which thickness is approximately 5 nm to 50 nm is formed on the i-GaN layer5. An n-type n-GaN layer7of which thickness is approximately 0.1 nm to 10 nm is formed on the n-AlGaN layer6. For example, Si is contained in the n-AlGaN layer6and the n-GaN layer7as an impurity with a concentration of approximately 5×1017cm−3to 5×1019cm−3.

A trench11for element isolation is formed in the n-AlGaN layer6and the n-GaN layer7, and an element isolation insulating film12is embedded in the trench11. A source electrode21sand a drain electrode21dare formed on the n-GaN layer7. The source electrode21sand the drain electrode21dmay be constituted by, for example, a Ta film and an Al film formed thereon, and the source electrode21sand the drain electrode21dform an ohmic junction with the n-GaN layer7.

Further, an SiN film22covering the n-GaN layer7, the source electrode21sand the drain electrode21dis formed, and a gate electrode21gis formed on the SiN film22between the source electrode21sand the drain electrode21d. A thickness of the SiN film22is approximately 10 nm to 2000 nm. Besides, an opening is formed in the SiN film22between the source electrode21sand the gate electrode21g, and a recess portion7ais formed at a portion exposing from this opening of the n-GaN layer7. The recess portion7amay either stop at the n-GaN layer7or extend up to the n-AlGaN layer6. A recess electrode21rextending upward from the recess portion7ais formed. The gate electrode21gand the recess electrode21rmay be constituted by, for example, an Ni film and an Au film formed thereon, and the recess electrode21rforms a schottky junction with the n-GaN layer7.

Besides, the source electrode21sand the recess electrode21rare grounded.

As stated above, a piece of GaN based HEMT is constituted. Further, the GaN based HEMTs as stated above are provided so as to be arranged in one direction via the element isolation insulating film12as illustrated inFIG. 2. A region surrounded by the element isolation insulating film12is an element region10. The GaN based HEMTs may be provided so as to be arranged in two directions via the element isolation insulating film12.

In the first embodiment as stated above, electrons are induced in a vicinity of an interface between the i-GaN layer5and the n-AlGaN layer6by a piezoelectric effect resulting from a lattice mismatch. As a result, two-dimensional electron gas (2DEG) appears, and this portion functions as an electron transit layer and the n-AlGaN layer6functions as an electron supply layer. Besides, the i-AlN layer2functions as an insulating layer insulating between the substrate1and compound semiconductor layers including the i-GaN layer5. Incidentally, it is desirable that a thickness of the i-GaN layer5is 0.5 μm or more so that the two-dimensional electron gas inside the i-GaN layer5is difficult to be affected by Fe added to the GaN layer4.

The two-dimensional electron gas appears at a surface layer portion of the i-GaN layer5as stated above, but in the present embodiment, the recess electrode21rforming the schottky-junction with the n-GaN layer7is provided inside the recess portion7a, and the recess electrode21ris grounded. Accordingly, the two-dimensional electron gas does not exist at the surface layer portion of the i-GaN layer5at downward of the recess electrode21r. Consequently, a leak current does not flow between the source electrode21sand the drain electrode21dunder a state in which the voltage is not applied to the gate electrode21gand an electric field seldom exists between the gate electrode21gand the source electrode21s. Namely, the normally-off operation is enabled. Besides, the current does not flow if the voltage higher than the conventional one is not applied to the gate electrode21g, because the two-dimensional electron gas does not exist at the surface layer portion of the i-GaN layer5at downward of the recess electrode21r. Namely, a threshold voltage increases.

FIG. 3is a band diagram illustrating an energy structure at downward of the recess electrode21r. As illustrated inFIG. 3, a conduction band at the recess electrode21rside of the i-GaN layer5is pulled up and the two-dimensional electron gas is unable to exist there under a state in which the voltage is not applied to the gate electrode21g. On the other hand, when a predetermined voltage (for example, 5V) is applied to the gate electrode21g, the conduction band becomes approximately even and the current flows. The normally-off operation is enabled as stated above.

FIG. 4is a graphic chart illustrating a relation between a drain current and a gate voltage in the first embodiment. This graphic chart represents a simulation result when the source electrode21sand the recess electrode21rare grounded and the voltage of +20 V is applied to the drain electrode21d. As illustrated inFIG. 4, a threshold voltage Vth exceeds 2 V, and the drain current when the voltage applied to the gate electrode21g(gate voltage) is “0” (zero) V is “0” (zero) A/m.

As stated above, according to the first embodiment, it is possible to obtain the high threshold voltage, and to reduce the leak current when the gate voltage is “0” (zero) V.

Next, a manufacturing method of the GaN based HEMT (compound semiconductor device) according to the first embodiment is described.FIG. 5AtoFIG. 5Iare sectional views illustrating the manufacturing method of the GaN based HEMT (compound semiconductor device) according to the first embodiment in process sequence.

In the first embodiment, first, the i-AlN layer2is formed on the substrate1by, for example, a hydride vapor phase epitaxy (HVPE) method, as illustrated inFIG. 5A. At this time, for example, trimethylaluminum gas, ammonia gas, and HCl gas are used as source gas, a growth pressure is set at an atmospheric pressure, and a growth speed is set at 100 μm/h.

Next, the i-AlN layer3, the GaN layer4, the i-GaN layer5, the n-AlGaN layer6, and the n-GaN layer7are sequentially formed on the i-AlN layer2by, for example, a metal organic chemical vapor deposition (MOCVD) method. When these layers are formed, the trimethylaluminum gas is used as a material of Al, trimethylgallium gas is used as a material of Ga, and the ammonia gas is used as a material of N. Besides, a flow rate of the ammonia gas is set at, for example, 100 ccm to 10 μM. Besides, the growth pressure is set at 50 Torr to 300 Torr, a growth temperature is set at 1000° C. to 1200° C. When the GaN layer4containing Fe is formed, for example, a metal-organic material containing Fe such as ferrocene is used as a material of Fe. Besides, when the n-AlGaN layer6and the n-GaN layer7are formed, for example, diluted SiH4is used as a material of Si. A flow rate of the diluted SiH4is set at, for example, a several ccm.

Subsequently, the trench11penetrating the n-GaN layer7and the n-AlGaN layer6and reaching the i-GaN layer5is formed by a photolithography and an etching, as illustrated inFIG. 5B. Next, the element isolation insulating film12is embedded in the trench11by, for example, a plasma CVD method. Incidentally, an element isolation region may be formed by an ion implantation of Ar or the like, instead of the formation of the trench11and the element isolation insulating film12.

The source electrode21sand the drain electrode21dare then formed on the n-GaN layer7by a lift-off method, as illustrated inFIG. 5C. A new resist pattern opening areas to form the source electrode21sand the drain electrode21dis formed, vapor depositions of Ta and Al are performed, and thereafter, Ta and Al adhered on the resist pattern are removed together with the resist pattern, to form the source electrode21sand the drain electrode21d. Thicknesses of a Ta film, an Al film are, for example, respectively approximately 20 nm, 200 nm. A heat treatment is performed from 400° C. to 1000° C., for example, at 600° C. in a nitride atmosphere to establish ohmic characteristics.

Next, the SiN film22is formed on a whole surface by, for example, a plasma CVD method, as illustrated inFIG. 5D.

After that, a resist pattern31having an opening31acorresponding to an area to form the recess portion7aand covering the other area is formed on the SiN film22, as illustrated inFIG. 5E.

Subsequently, an opening is formed in the SiN film22by etching the SiN film22while using the resist pattern31as a mask, and the recess portion7ais formed by further etching the surface layer portion of the n-GaN layer7, as illustrated inFIG. 5F. A remaining thickness of a portion where the recess portion7ais formed of the n-GaN layer7is preferable to be 10 nm or less, and it is set to be, for example, approximately 5 nm to 10 nm. The resist pattern31is then removed. Besides, it is preferable that a difference between the thickness (remaining thickness) of the portion where the recess portion7ais formed of the n-GaN layer7and the thickness of the other portion is 5 nm or more. A reason why the remaining thickness is preferable to be set at 10 nm or less is because there may be a case when the appearance of the two-dimensional electron gas cannot be suppressed enough if the remaining thickness exceeds 10 nm. Besides, a reason why the difference of the thicknesses is preferable to be set at 5 nm or more is because there may be a case when an effect of the recess cannot be fully obtained and the normally-off operation becomes difficult when the difference is less than 5 nm.

Next, a resist pattern32having an opening32gcorresponding to an area to form the gate electrode21gand an opening32aexposing the recess portion7a, and covering the other area is formed on the SiN film22, as illustrated inFIG. 5G.

After that, the gate electrode21gand the recess electrode21rare formed by performing vapor depositions of Ni and Au, as illustrated inFIG. 5H. Thicknesses of an Ni film and an Au film are, for example, respectively approximately 10 nm and 300 nm.

Subsequently, Ni and Au adhered on the resist pattern32are removed together with the resist pattern32, as illustrated inFIG. 5I. Thus, the gate electrode21gand the recess electrode21rcan be formed by a lift-off method.

Next, a wiring to ground the source electrode21sand the recess electrode21r, and so on are formed.

The GaN based HEMT according to the first embodiment is completed as stated above. After that, a semiconductor device in which the GaN based HEMTs are integrated is completed by forming a passivation film, external electrodes, and so on if necessary.

In the first embodiment, the recess electrode21rand the source electrode21sare separated from each other, and the SiN film22exists therebetween, but the recess electrode21rand the source electrode21smay be directly in contact.

Second Embodiment

Next, a second embodiment is described.FIG. 6is a sectional view illustrating a structure of a GaN based HEMT (compound semiconductor device) according to the second embodiment.

The recess electrode21rprovided in the first embodiment is not provided in the second embodiment. However, damages capturing electrons exist around the recess portion7a. The other constitution is the same as the first embodiment.

A piece of GaN based HEMT is constituted as stated above. Besides, the GaN based HEMTs are provided so as to be arranged in one direction via the element isolation insulating film12, as illustrated inFIG. 7. The region surrounded by the element isolation insulating film12is the element region10. The GaN based HEMTs may be provided so as to be arranged in two directions via the element isolation insulating film12.

The two-dimensional electron gas appears at the surface layer portion of the i-GaN layer5in the second embodiment as stated above as same as the first embodiment, and the two-dimensional electron gas does not exist at the surface layer portion of the i-GaN layer5at downward of the recess portion7a. This is because the electrons are captured by the damages around the recess portion7a, and a balance of electric charges is established.

FIG. 8is a graphic chart illustrating a relation between a drain current and a gate voltage in the second embodiment. This graphic chart represents a simulation result when the source electrode21sand the recess electrode21rare grounded, and a voltage of +20 V is applied to the drain electrode21d. As illustrated inFIG. 8, the threshold voltage Vth is approximately 1 V, but the drain current when the voltage applied to the gate electrode21g(gate voltage) is “0” (zero) V is “0” (zero) A/m.

As stated above, the leak current when the gate voltage is “0” (zero) V can also be reduced by the second embodiment. Besides, the structure is simple compared to the first embodiment, and therefore, a manufacture thereof is easy, and the cost can be reduced.

Next, a manufacturing method of the GaN based HEMT (compound semiconductor device) according to the second embodiment is described.FIG. 9AtoFIG. 9Care sectional views illustrating the manufacturing method of the GaN based HEMT (compound semiconductor device) according to the second embodiment in process sequence.

In the second embodiment, at first, the processes up to the formation of the recess portion7a(FIG. 5F) are performed as same as the first embodiment. Incidentally, for example, a dry etching such as a reactive ion etching (RIE) using chlorine gas is performed when the recess portion7ais formed. Besides, a pressure is set to be approximately 0.1 Pa to 10 Pa (for example, 2 Pa), and a flow rate of the chlorine gas is set to be approximately 0.1 sccm to 10 sccm (for example, 2.5 sccm). The n-GaN layer7is processed under the condition as stated above, and thereby, the recess portion7ain which many traps capturing electrons exist therearound is formed.

Next, the resist pattern31used for the formation of the recess portion7ais removed, and a resist pattern42having an opening42gcorresponding to an area to form the gate electrode21gand covering the other area is formed on the SiN film22, as illustrated inFIG. 9A.

After that, the gate electrode21gis formed by performing the vapor deposition of Ni and Au, as illustrated inFIG. 9B. Thicknesses of the Ni film and Au film are, for example, respectively approximately 10 nm and 300 nm.

Subsequently, Ni and Au adhered on the resist pattern42are removed together with the resist pattern42, as illustrated inFIG. 9C. The gate electrode21gcan be formed by the lift-off method as stated above.

The GaN based HEMT according to the second embodiment is completed as stated above.

In the first and second embodiments, the opening for the source electrode and the opening for the drain electrode may be formed only in the n-GaN layer7, and the source electrode21sand the drain electrode21dmay be formed in these openings. A part of the n-GaN layer7may remain or a part of the n-AlGaN layer6may be removed as for depths of these openings. Namely, the depths of the openings are not necessarily match with the thickness of the n-GaN layer7.

Besides, the gate electrode21gand the n-GaN layer7may be directly in contact, and the gate electrode21gmay form the schottky junction with the n-GaN layer7. Further, a recess portion may also be formed at the n-GaN layer7at downward of the gate electrode21g. Namely, a gate recess structure may be taken. A depth of the recess portion as stated above may match with the thickness of the n-GaN layer7, or the depth may either be shallower or deeper than the thickness of the n-GaN layer7. It should be noted that it is preferable to perform the etching evenly. When the gate recess structure is taken, it is suitable for a high-speed operation because a response becomes high-speed. On the other hand, when the gate recess structure is not taken, the leak current can be suppressed more certainly. Accordingly, an adoption of the gate recess structure may be selected depending on uses thereof.

An insulating film may exist between the recess electrode21rand the n-GaN layer7. Namely, it may be an MIS structure. For example, an SiN film, an SiO2film, an HfO film, an HfNO film, an Al2O3film, a TaO film, and so on can be cited as the insulating film. A thickness of this insulating film is, for example, approximately 0.1 nm to 50 nm. There may be a case when the leak current increases conversely or reliability decreases because of a reason that the insulating film may be formed in island state and so on when the thickness of the insulating film is less than 0.1 nm. There may be a case when the appearance of the two-dimensional electron gas cannot be fully suppressed because a distance between the recess electrode21rand the n-AlGaN layer6becomes too large when the thickness of the insulating film exceeds 50 nm.

It is also possible to suppress the appearance of the two-dimensional electron gas even when the recess electrode21ris provided between the gate electrode21gand the drain electrode21d. It should be noted that there are a case when a withstand voltage is easy to become low because a high voltage is applied to the drain electrode21d, and a case when it becomes difficult to suppress the appearance of the two-dimensional electron gas effectively, in the constitution as stated above. Accordingly, it is preferable that the recess electrode21ris provided between the gate electrode21gand the source electrode21s.

A silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, a GaN substrate, a GaAs substrate, and so on may be used as the substrate1. The substrate1may either be conductive, semi-insulating, or insulating.

Third Embodiment

Next, a third embodiment is described. Structures of the GaN based HEMTs according to the first and second embodiments are horizontal structures, but a structure of a GaN based HEMT according to the third embodiment is a vertical structure.FIG. 10is a sectional view illustrating a structure of the GaN based HEMT (compound semiconductor device) according to the third embodiment.

In the third embodiment, a non-doped i-AlN layer52having an opening52ais formed on an n-type n-GaN layer51. A thickness of the n-GaN layer51is approximately 0.1 μm to 100 μm (for example, 25 μm), and a thickness of the i-AlN layer52is approximately 0.02 μm to 20 μm. A planer shape of the opening52aas a current passing area is, for example, a rectangle of which lengths in horizontal and vertical are respectively 0.5 μm and 500 μm. Fe, which is a transition metal element, is contained in the n-GaN layer51as an impurity. A content ratio of Fe is approximately 1×1017cm−3to 5×1019cm−3. A GaN film53is formed in the opening52a.

Further, a non-doped i-GaN layer54, an n-type n-AlGaN layer55, and an n-type n-GaN layer56are formed on the i-AlN layer52and the GaN layer53. A thickness of the i-GaN layer54is approximately 1 μm to 2 μm. A thickness of the n-AlGaN layer55is approximately 20 nm to 30 nm. A thickness of the n-GaN layer56is approximately 3 nm to 8 nm. For example, Si is contained in the n-AlGaN layer55and the n-GaN layer56as an impurity with a concentration of approximately 1×1017cm−3to 5×1019cm−3.

A trench61for element isolation are formed in the n-AlGaN layer55and the n-GaN layer56, and element isolation insulating film62is embedded in the trench61. A source electrode71sof which planer shape is square is formed on the n-GaN layer56. The source electrode71smay be constituted by, for example, a Ta film and an Al film formed thereon, and the source electrode71sforms the ohmic junction with the n-GaN layer56.

Further, an SiN film72covering the n-GaN layer56and the source electrode71sis formed, and a gate electrode71gis formed on the SiN film72at an area surrounded by the source electrode71s. A thickness of the SiN film72is approximately 1 nm to 2000 nm. Besides, an opening is formed in the SiN film72between the source electrode71sand the gate electrode71g, and a recess portion56ais formed at a portion exposing from the opening of the n-GaN layer56. A recess electrode71rextending upward from the recess portion56ais formed. The gate electrode71gand the recess electrode71rmay be constituted by, for example, an Ni film and an Au film formed thereon, and the recess electrode71rforms the schottky junction with the n-GaN layer56.

Besides, the source electrode71sand the recess electrode71rare grounded.

Further, a drain electrode71dis formed at a rear surface of the n-GaN layer51. The drain electrode71dmay be constituted by, for example, a Ta film and an Al film formed thereon, and the drain electrode71dforms the ohmic junction with the n-GaN layer51.

As stated above, a piece of GaN based HEMT is constituted. Further, the GaN based HEMTs as stated above are provided so as to be arranged in one direction via the element isolation insulating film62as illustrated inFIG. 11. A region surrounded by the element isolation insulating film62is an element region60. The GaN based HEMTs may be provided so as to be arranged in two directions via the element isolation insulating film62.

In the third embodiment as stated above, the n-AlGaN layer55functions as an electron supplying layer supplying electrons to the i-GaN layer54(electron transit layer). A band gap of the n-AlGaN layer55is wide, and therefore, a deep potential well is formed in the i-GaN layer54at a region in the vicinity of an interface with the n-AlGaN layer55, and two-dimensional electron gas (2DEG) appears there. Besides, the i-AlN layer52functions as an insulating layer insulating between a compound semiconductor layer including the i-GaN layer54, and the n-GaN layer51and the drain electrode71d. Incidentally, it is desirable that a thickness of the i-GaN layer54is 0.5 μm or more so that the two-dimensional electron gas inside the i-GaN layer54is difficult to be affected by Fe added to the n-GaN layer51.

As stated above, the two-dimensional electron gas appears at a surface layer portion of the i-GaN layer54, but in the present embodiment, the recess electrode71rwhich forms the schottky junction with the n-GaN layer56is provided in the recess portion56a, and the recess electrode71ris grounded. Accordingly, the two-dimensional electron gas does not exist at the surface layer portion of the i-GaN layer54at downward of the recess electrode71rresulting from the same reason as the first embodiment. Consequently, a leak current does not flow between the source electrode71sand the drain electrode71dunder a state in which the voltage is not applied to the gate electrode71gand an electric field seldom exists between the gate electrode71gand the source electrode71s. Namely, the normally-off operation is enabled. Besides, the current does not flow if the voltage higher than the conventional one is not applied to the gate electrode71g, because the two-dimensional electron gas does not exist at the surface layer portion of the i-GaN layer54at downward of the recess electrode71r. Namely, the threshold voltage increases resulting from the same reason as the first embodiment.

According to the third embodiment, it is possible to obtain the high threshold voltage, and to reduce the leak current when the gate voltage is “0” (zero) V, in addition that the normally-off operation is enabled also in the vertical structure.

Next, a manufacturing method of the GaN based HEMT (compound semiconductor device) according to the third embodiment is described.FIG. 12AtoFIG. 12Nare sectional views illustrating the manufacturing method of the GaN based HEMT (compound semiconductor device) according to the third embodiment in process sequence.

Next, the opening52ais formed at the i-AlN layer52, as illustrated inFIG. 12B. As for the formation of the opening52a, for example, a resist pattern exposing an area to form the opening52ais formed on the i-AlN layer52, and the i-AlN layer52is etched by using this resist pattern as a mask. After that, the resist pattern is removed.

After that, the GaN layer53is formed in the opening52aby, for example, an MOCVD method, as illustrated inFIG. 12C.

Subsequently, the i-GaN layer54, the n-AlGaN layer55, and the n-GaN layer56are formed in this sequence on the i-AlN layer52and the GaN layer53by, for example, an MOCVD method, as illustrated inFIG. 12D.

Next, the trench61penetrating the n-GaN layer56and the n-AlGaN layer55and reaching the i-GaN layer54is formed by a photolithography and an etching, as illustrated inFIG. 12E. After that, the element isolation insulating film62is embedded inside the trench61by, for example, a plasma CVD method. Incidentally, an element isolation region may be formed by an ion implantation such as Ar, instead of the formation of the trench61and the element isolation insulating film62.

The source electrode71sis then formed on the n-GaN layer56by a lift-off method, as illustrated inFIG. 12F. In the formation of the source electrode71s, a new resist pattern opening an area to form the source electrode71sis formed, vapor depositions of Ta and Al are performed, and thereafter, Ta and Al adhered on the resist pattern are removed together with the resist pattern. Thicknesses of a Ta film, an Al film are set to be, for example, respectively approximately 20 nm, 200 nm. The heat treatment is performed from 400° C. to 1000° C., for example, at 600° C. in a nitride atmosphere to establish the ohmic characteristics.

Next, the SiN film72is formed on a whole surface by, for example, a plasma CVD method, as illustrated inFIG. 12G.

After that, a resist pattern81having an opening81acorresponding to an area to form the recess portion56aand covering the other area is formed on the SiN film72, as illustrated inFIG. 12H.

Subsequently, an opening is formed in the SiN film72by etching the SiN film72with using the resist pattern81as a mask, as illustrated inFIG. 12I, and the recess portion56ais formed by etching the surface layer portion of the n-GaN layer56. A remaining thickness of a portion where the recess portion56ais formed of the n-GaN layer56is preferable to be 10 nm or less, and it is set to be, for example, approximately 5 nm to 10 nm. The resist pattern81is then removed.

Next, a resist pattern82having an opening82gcorresponding to an area to form the gate electrode71gand an opening82aexposing the recess portion56aand covering the other area is formed on the SiN film72, as illustrated inFIG. 12J.

After that, the gate electrode71gand the recess electrode71rare formed by performing vapor depositions of Ni and Au, as illustrated inFIG. 12K. Thicknesses of an Ni film and an Au film are, for example, respectively approximately 10 nm and 300 nm.

Subsequently, Ni and Au adhered on the resist pattern82are removed together with the resist pattern82, as illustrated inFIG. 12L. As stated above, the gate electrode71gand the recess electrode71rcan be formed by a lift-off method.

Next, a surface protecting layer83is formed on a whole surface at a front surface side of the n-GaN layer51, as illustrated inFIG. 12M, and the front-and-rear of the n-GaN layer51are reversed. After that, the drain electrode71dis formed on the whole surface of the rear surface of the n-GaN layer51.

Subsequently, the front-and-rear of the n-GaN layer51are reversed as illustrated inFIG. 12N, and the surface protecting layer83is removed.

Next, wirings to ground the source electrode71sand the recess electrode71r, and so on are formed.

The GaN based HEMT according to the third embodiment is completed as stated above. After that, a semiconductor device in which the GaN based HEMTs are integrated is completed by forming the passivation film, external electrodes, and so on if necessary.

Incidentally, an n-type conductive GaN substrate may be used as the n-GaN layer51in the third embodiment. Besides, the n-GaN layer51may be formed on a conductive substrate.

Besides, the opening for the source electrode is formed only in the n-GaN layer56, and the source electrode71smay be formed in the opening. A part of the n-GaN layer56may remain or a part of the n-AlGaN layer55may be removed, as for a depth of the opening. Namely, the depth of the opening is not necessarily match with the thickness of the n-GaN layer56.

Besides, the gate electrode71gand the n-GaN layer56may be directly in contact, and the gate electrode71gmay form the schottky junction with the n-GaN layer56. Further, a recess portion may be formed at the n-GaN layer56also at downward of the gate electrode71g. Namely, the gate recess structure may be taken. A depth of the recess portion as stated above may match with the thickness of the n-GaN layer56, or the depth may be shallower than the thickness of the n-GaN layer56. It should be noted that it is preferable to perform the etching evenly. When the gate recess structure is taken, it is suitable for a high-speed operation because a response becomes high-speed. On the other hand, when the gate recess structure is not taken, the leak current can be suppressed more certainly. Accordingly, the adoption of the gate recess structure may be selected depending on uses thereof.

Incidentally, the structures of the gate electrode, the source electrode, the drain electrode and the recess electrode are not limited to the ones in the above-stated embodiments. For example, these electrodes may be constituted by a single layer. Besides, the formation method thereof is not limited to the lift-off method. Further, the heat treatment after the formations of the source electrode and the drain electrode may not be performed as long as the ohmic characteristics can be obtained. The heat treatment may be performed for the gate electrode and the recess electrode. Any one kind or a combination of two kinds or more from among gold, nickel, platinum, copper, tungsten nitride, titanium nitride, palladium, cobalt, rhodium, rhenium, and iridium can be cited as materials of the gate electrode and the recess electrode.

The thickness, the material, and so on of each layer are not limited to the ones in the above-stated embodiments. Besides, the recess electrode is not necessarily connected to the source electrode, and also, it is not necessary to be grounded as long as the electric potential different from the gate electrode is supplied thereto.

It is preferable that an insulating film of which relative dielectric constant is three or less is provided between the source electrode and the gate electrode. For example, a porous SiOH film, a carbon fluoride film, an organic silica film, and so on can be cited as the insulating film as stated above.

According to the above-stated compound semiconductor device and so on, it is possible to reduce the leak current at the power-off time because the appearance of the two-dimensional electron gas can be suppressed locally resulting from an influence of the schottky electrode.