Memory device with different memory film diameters in the same laminate level

According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film.

FIELD

Embodiments described herein relate generally to a non-volatile memory device.

BACKGROUND

In order to realize a non-volatile memory device for the next generation, a memory cell array of three-dimensional structure has been developed. The memory cell array of three-dimensional structure includes a plurality of stacked word lines, and memory cells formed inside memory holes passing through the word lines. Such a non-volatile memory device includes a memory cell which repeats writing and erasing of data, and a memory cell which retains predetermined data for a long time. Then, good retention characteristics are required for the memory cell which retains the data for a long time.

DETAILED DESCRIPTION

According to one embodiment, a non-volatile memory device includes a plurality of first electrodes, at least one first semiconductor layer, a first memory film, a plurality of second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the second semiconductor layer. An outer diameter of the first memory film provided between one of the first electrodes and the one first semiconductor layer is larger than an outer diameter of the second memory film provided between one of the second electrodes positioned in the same laminate level as the one of the first electrodes and the one second semiconductor layer.

Various embodiments will be described hereinafter with reference to the accompanying drawings. The same portions in the drawings are denoted by the same number, detailed description thereof will be appropriately omitted, and the other portions will be described. In addition, the drawings are schematic or conceptual drawings, and a relationship between a thickness and a width of each portion, a ratio of sizes of each portion, or the like is not necessarily limited to the same as actual ones. Even if the same portions are represented, there is also a case where the dimensions or the ratio of the same portions are represented differently from each other according to the drawing. There is a case where arrangement of each element is described using a direction of an x axis, a y axis, or a z axis illustrated in the drawing. There is a case where the x axis, the y axis, and the z axis are orthogonal to each other, the z axis direction is referred to as an upward direction, and an opposite direction thereto is referred to as a downward direction.

First Embodiment

FIGS. 1A and 1Bare examples of a schematic view showing a memory cell array1of a non-volatile memory device100according to a first embodiment.FIG. 1Ais a cross-sectional view taken along a line1A-1A shown inFIG. 1B.FIG. 1Bis a cross-sectional view taken along a line1B-1B shown inFIG. 1A.

A memory cell array1includes a plurality of first electrodes (hereinafter, referred to as word lines WL0ato WL7a), and a plurality of second electrodes (hereinafter, referred to as word lines WL0bto WL7b). Each of the word lines WL0ato WL7aand the word lines WL0bto WL7bis stacked in a first direction (hereinafter, referred to as a Z-direction). In addition, a laminate body110which includes the word lines WL0ato WL7a, and a laminate body120which includes the word lines WL0bto WL7bare arranged in parallel in a second direction (hereinafter, referred to as an X-direction).

The memory cell array1includes at least one first semiconductor layer (hereinafter, referred to as a channel body10a), and at least one second semiconductor layer (hereinafter, referred to as a channel body10b). The channel body10aextends in the Z-direction through a center of the word lines WL0ato WL7a. The channel body10bextends in the Z-direction through a center of the word lines WL0bto WL7b.

The memory cell array1further includes a first memory film (hereinafter, referred to as a memory film20a) and a second memory film (hereinafter, referred to as a memory film20b). The memory film20ais provided between each of the word lines WL0ato WL7aand the channel body10a. The memory film20bis provided between each of the word lines WL0bto WL7band the channel body10b.

A memory cell MC is formed between each word line WL and the channel body10. A first memory cell (hereinafter referred to as a memory cell MCa) is formed between each of the plurality of word lines WLa and the channel body10a, and includes the memory film20a. A second memory cell (hereinafter referred to as a memory cell MCb) is formed between each of the plurality of word lines WLb and the channel body10b, and includes the memory film20b.

In addition, in the specification, for example, there is a case where the plurality of word lined WL0ato WL7aare briefly represented by word lines WLa, and the plurality of word lines WL0bto WL7bare briefly represented by word lines WLb. In addition, there is a case where the plurality of word lines as a whole are represented by the word lines WL. In the same manner, there is a case where the memory cells MC0ato MC7aand the memory cells MC0bto MC7bare also represented by memory cells MCa, MCb and MC. In addition, this is the same as in the other configuration elements.

As shown inFIG. 1A, an outer diameter of the memory film20awhich is provided between one word line WLka (k is an integer) of the plurality of word lines WLa and the channel body10ais larger than an outer diameter of the memory film20bwhich is provided between one word line WLkb of the plurality of word lines WLb and the channel body10b. Here, the outer diameter refers to a diameter of an outer perimeter of the memory film20in the cross-section orthogonal to the Z-direction. In addition, the outer diameters of the memory films20are compared between the word lines WL which are positioned at the same laminate level (k is equal).

For example, the outer diameter D1of the memory film20awhich is provided between the word line WL7ain the top layer of the plurality of word lines WLa and the channel body10ais larger than the outer diameter D2of the memory film20bwhich is provided between the word line WL7bin the top layer of the plurality of word lines WLb and the channel body10b.

In this manner, the memory cell array1includes at least two types of memory films20aand20bhaving a different outer diameter from each other. For example, when the same voltage is applied to the memory cell MC7abetween the word line WL7aand the channel body10a, and to the memory cell MC7bbetween the word line WL7band the channel body10b, an electric field of the memory film20bis stronger than an electric field of the memory film20a, because of a curvature difference between the memory films20.

For example, if minimum electric fields of the memory films20aand20bwhich are required for writing (or erasing) data to the memory cells MC7aand MC7bare the same, a minimum value of a writing voltage of the memory cell MC7ais greater than a minimum value of a writing voltage of the memory cell MC7b(the same applies to an erasing voltage). This is because the memory cell MC7bis more greatly affected by the concentration of electric field towards a central portion of the memory cell and electric field relaxation at an outer perimeter portion of the memory cell, compared to the memory cell MC7a. A shape effect of such a memory cell appears not only in writing or erasing of the data, but also in other characteristics of the memory cell. That is, by making the outer diameter of the memory film large and by relaxing the concentration of electric field toward a tunnel insulating film, the memory cell MC7ahas better data retention characteristics than the memory cell MC7b. In addition, even with respect to read disturb at the time of data reading, the memory cell MC7ahas a smaller amount of data disturb than that of the memory cell MC7b.

According to an embodiment, for example, the memory cells MCa provided in the laminate body110all include the memory film20a. The memory cells MCb provided in the laminate body120all include the memory film20b. Then, the memory cell MCa of the laminate body110has better data retention characteristics than those of the memory cell MCb of the laminate body120.

In a fabricating process of the memory cell array of the three-dimensional structure, for example, an insulating film layer and an electrode layer are stacked in a first direction, and a memory hole is formed by etching the insulating film layer and the electrode layer all at once. Subsequently, in the memory hole, a memory film and a channel body are stacked towards a center of the memory hole. In addition, the memory film and the channel body are formed using, for example, a chemical vapor deposition (CVD) or an atomic layer deposition (ALD). Such film forming methods have a good coverage, and thus an approximately uniform film is formed on a side surface of the memory hole.

For example, the memory cells MCa and the memory cells MCb can be separately formed by forming memory hole patterns having different hole diameters in a photomask (reticle) at the time of forming the memory holes. The other process conditions with respect to the laminate body110and the laminate body120are all the same. Therefore, the memory film20aand the memory film20bhave the same structure and the same film thickness. Here, “the same” is not limited to “identical” in the strict sense, and for example, by allowing a difference caused by non-uniformity or the like in a surface direction and a stacking direction during the film formation process using the CVD or the ALD, “approximately the same” is included therein.

The embodiment is not limited to the above-described fabrication method, and the laminate body110and the laminate body120may be separately formed. For example, while the laminate body110or an area of the laminate body110is protected by a hard mask, the laminate body120is formed. Subsequently, while the laminate body120is protected by a hard mask, the laminate body110is formed. As a result, the memory film20amay be formed so as to have a structure and a film thickness which are different from the memory film20b.

Next, with reference toFIG. 1BtoFIG. 3, the structures of the non-volatile memory device100and the memory cell array1will be more specifically described. The following description is an example of the embodiment, and the invention is not limited to the example.

As shown inFIG. 1B, the laminate body110is provided over a source line SLa. The laminate body110includes the plurality of word lines WLa, a selection gate SGSa, and a selection gate SGDa. The laminate body120includes the plurality of word lines WLb, a selection gate SGSb, and a selection gate SGDb.

For example, the laminate bodies110and120are patterned in a rectangular body extending in the Y-direction. Each word line WL and the selection gates SGS are patterned in a rectangular shape extending in the Y-direction. A plurality of bit lines BLn are provided over the laminate bodies110and120. The bit lines BLn are respectively mounted over the laminate bodies110and120, and extend in the X-direction. InFIG. 1B, for the sake of simplicity, the insulating films are omitted in which the source lines, the word lines, the selection gate, and the bit lines BLn are electrically insulated with respect to each other.

The selection gate SGSa is provided between the source line SLa and the word line WL0a. The selection gate SGDa is provided between the word line WL7aand the bit line BLn. Then, at least one memory hole30ais provided in the direction (Z-direction) of the selection gate SGSa from the selection gate SGDa. The memory hole30ais connected to the source line SLa by passing through the plurality of word lines WLa, and the selection gates SGDa and SGSa.

The selection gate SGSb is provided between the source line SLb and the word line WL0b. The selection gate SGDb is provided between the word line WL7band the bit line BLn. At least one memory hole30bis provided in the direction (−Z-direction) of the selection gate SGSb from the selection gate SGDb. The memory hole30bis connected to the source line SLb by passing through the plurality of word lines WLb, and the selection gates SGDb and SGSb.

For example, the memory hole30ais formed in such a manner that a diameter in a cross-section perpendicular to the Z-direction of the memory hole30ais larger than a diameter in a cross-section perpendicular to the Z-direction of the memory hole30b. For example, the diameter in the memory hole30ais 80 nanometers (nm), and the diameter of the memory hole30bis 60 nm to 70 nm.

The channel body10aand the memory film20aare provided inside the memory hole30a. The memory film20ais formed on an inside wall of the memory hole30a. The channel body10ais formed over the memory film20a. An edge of the channel body10ais electrically connected to the source line SLa. The other edge of the channel body10ais electrically connected to the bit line BLn through a contact plug23. An insulating core40ais buried inside the memory hole30a.

The channel body10band the memory film20bare provided inside the memory hole30b. The memory film20bis formed on an inside wall of the memory hole30b. The channel body10bis formed over the memory film20b. An edge of the channel body10bis electrically connected to the source line SLb. The other edge of the channel body10bis electrically connected to the bit line BLn through the contact plug23. An insulating core40bis buried inside the memory hole30b.

The memory films20aand20bare simultaneously formed, for example, and thicknesses in a direction orthogonal to the Z-direction are the same. In addition, the channel bodies10aand10bare also simultaneously formed, and thicknesses in a direction orthogonal to the Z-direction are the same. The outer diameter of the memory film20awhich is formed inside the memory hole30ais larger than the outer diameter of the memory film20bwhich is formed inside the memory hole30b. The memory cell MCa which includes the memory film20ais formed between the channel body10aand each word line WLa. The memory cell MCb which includes the memory film20bis formed between the channel body10band each word line WLb.

A selection transistor SST having the memory film20as a gate insulating film is formed between the channel body10and the selection gate SGS. In addition, a selection transistor SDT having the memory film20as a gate insulating film is formed between the channel body10and the selection gate SGD.

For example, the memory film20includes a tunnel insulating film in contact with the channel body10, an electric charge storage layer, and a block insulating film in contact with the word line WL. The electric charge storage layer is provided between the tunnel insulating film and the block insulating film. For example, the memory film20includes a silicon oxide film, a silicon nitride film and a silicon oxide film which are sequentially stacked from the word line WL side. The tunnel insulating film and the block insulating film are formed by a silicon oxide film, and the electric charge storage layer is formed by a silicon nitride film.

In the above-described embodiment, the memory film20is continuously provided along the inside wall of the memory hole30. The embodiment is not limited thereto, and for example, the memory films20may be separately arranged between each of the plurality of word lines WL and the channel body10. In such a case, the memory film20can include a conducting film which functions as an electric field storage layer, for example, polycrystalline silicon (polysilicon).

For example, a predetermined electric field is applied to the tunnel insulating film in the memory cell MC including the memory film20, thereby electrons are injected into the electric charge storage layer from the channel body10through the tunnel insulating film, and data is written thereto. In addition, an electric field opposite to that at the time of writing data is applied to the tunnel insulating film, and thereby the electrons are emitted to the channel body10from the electric field storage layer through the tunnel insulating film, or positive holes are injected into the electric field storage layer from the channel body10through the tunnel insulating film, and data is erased.

Even if the same voltage is applied to the memory cell MCa and the memory cell MCb, the intensities of the electric fields of the tunnel insulating films are different from each other, in the memory cells MCa and MCb having different outer diameters of the memory films20from each other. That is, by an electric field concentration effect which depends on the curvature of the memory film20, a stronger electric field than that of the tunnel insulating film of the memory cell MCa occurs in the tunnel insulating film of the memory cell MCb. Thus, the memory cell MCb performs data writing or data erasing at a lower voltage than the voltage applied to the memory cell MCa. In addition, for the same reason as this, retention characteristics of the memory cell MCb are poorer than retention characteristics of the memory cell MCa. In other words, the memory cell MCb is inferior in the data retention characteristics to the memory cell MCa.

FIGS. 2A and 2Bare examples of a schematic view showing the non-volatile memory device100according to the first embodiment.FIG. 2Ais a block diagram illustrating a configuration of the non-volatile memory device100.FIG. 2Bis a schematic diagram illustrating a planar structure of the memory cell array1.

As shown inFIG. 2A, the non-volatile memory device100includes the memory cell array1and a peripheral circuit thereof. The peripheral circuit includes, for example, a sense amplifier7, a column decoder8, a row decoder9, a word line driving circuit13, a selection gate line driving circuit15, a source line driving circuit17, and a control circuit19.

The word line driving circuit13controls a potential of the word line WL, and the source line driving circuit controls a potential of the source line SL. The selection gate line driving circuit15controls potentials of the selection gates SGS and SGD, and controls turning on and turning off the selection transistor SST between the source line SL and the channel body10, and the selection transistor SDT between the bit line BLn and the channel body10.

For example, the control circuit19controls the word line driving circuit13through the row decoder9, and controls the selection gate line driving circuit15and the source line driving circuit17, thereby writing data to the memory cell array1, and erasing the data. The control circuit19reads the data stored in the memory cell array1from the sense amplifier7through the column decoder8.

As shown inFIG. 2B, the memory cell array1includes a plurality of memory cell blocks BLK0to BLK3. Each of the memory cell blocks BLK includes a plurality of memory cell groups GP0to GP3. Each of the memory cell groups GP includes a plurality of memory strings50.

FIG. 3is an example of a circuit diagram showing the non-volatile memory device100according to the first embodiment.FIG. 3is an equivalent circuit showing one memory cell block BLK.

As shown inFIG. 3, the memory cell block BLK includes the memory cell groups GP0to GP3. Each memory cell group GP includes, for example, one laminate body. For example, the memory cell group GP0includes a plurality of memory cells MC0to MC7provided in one laminate body.

The one memory string50included in the memory cell group GP0includes, for example, memory cells MC0to MC7provided inside the one memory hole30, and the selection gates SGS and SGD. The memory cells MC0to MC7and the selection gates SGS and SGD share the one channel body10.

The plurality of bit lines BL0to BLn (n: integer) are respectively and electrically connected to the one channel body10provided in each laminate body. Then, the plurality of channel bodies10provided in one laminate body share one source line SL.

As shown inFIG. 3, one bit line BL is connected to any of a plurality of sub units SA1to SAn in the sense amplifier7. In addition, the memory cell groups GP0and GP1share the source line SL0, and the source line SL0is connected to one sub unit SD0of the source line driving circuit17. The memory cell groups GP2and GP3share the source line SL1, and the source line SL1is connected to one sub unit SD1of the source line driving circuit17.

For example, the control circuit19controls voltages of the selection gates SGS and SGD through the selection gate line driving circuit15. As a result, any one of the memory cell groups GP0to GP3is selected. Specifically, for example, the selection transistors SSTa and SDTa of the memory cell group GP0are turned on, and the selection transistors SST and SDT of the other memory cell groups GP are turned off.

For example, the control circuit19controls the potential of the channel body10positioned between each of the bit lines BL0to BLn and the source line SL0, through the sense amplifier7and the source line driving circuit17. For example, the potential of one of the plurality of channel bodies10included in the memory cell group GP0is selectively controlled.

Furthermore, for example, the control circuit19controls a potential difference between each of the plurality of word lines WL0to WL7included in the memory cell group GP0, and the channel body10, through the word line driving circuit13. As a result, a potential difference which is applied to any one of the plurality of memory cells MC0to MC7arranged along the channel body10is selectively controlled.

In this manner, the control circuit19accesses one of the plurality of memory cells MC included in one memory cell block BLK, and drives the accessed memory cell MC. For example, when a voltage applied to the accessed memory cell MC is higher than that applied to another memory cell, it is possible to write data to the accessed memory cell MC. In addition, a voltage lower than a threshold is applied to the accessed memory cell MC, and a voltage higher than the threshold is applied to another memory cell MC. As a result, it is possible to read the data stored in the accessed memory cell MC.

For example, in the non-volatile memory device100, the memory cell MCa is arranged in the memory cell block BLK0, and the memory cell MCb is arranged in the memory cell blocks BLK1to BLK3. As described above, the memory cell MCa includes the memory film20a, and the memory cell MCb includes the memory film20b. The outer diameter D1of the memory film20ais larger than the outer diameter D2of the memory film20b. Thus, the data retention characteristics of the memory cell MCa arranged in the memory cell block BLK0are better than the data retention characteristics of the memory cells MCb arranged in the memory cell blocks BLK1to BLK3.

The control circuit19drives the memory cells MCa arranged in the memory cell block BLK0and the memory cells MCb arranged in the memory cell blocks BLK1to BLK3. Then, for example, the control circuit19operates in such a manner that the data which is longer in retention time than the data that is written to the memory cell MCb is written to the memory cell MCa. In other words, the control circuit19controls a data address in such a manner that the number of data writings to the memory cells MCb and data erasings in the memory cells MCb is greater than the number of data writings to the memory cells MCa and data erasings in the memory cells MCa.

In the embodiment, for example, a program which executes such an operation in the control circuit19is written to the memory cell block BLK0, in an initial state of the non-volatile memory device100. As a result, it is possible to improve a reliability of the non-volatile memory device100.

In another embodiment, for example, data which controls the operation of the non-volatile memory device100, a so-called firmware may be written to the memory cell block BLK0, in an initial state. Then, the firmware may be configured so as to include a program which stops erasing of the data stored in the memory block BLK0and writing of the data to the memory block BLK0, in the control circuit19. In other words, the memory cell block BLK0may be used as a read only memory (ROM). As a result, for example, it is possible to control malfunction at the time of powering on, and to improve the reliability of the non-volatile memory device100.

For example, in the above-described non-volatile memory device100, in an initial state before the data writing and data erasing are executed, the memory cell block BLK0having a large diameter of the memory hole stores the data. The other memory cell blocks do not store the data. That is, in an initial state, the distribution of threshold voltages of the memory cells MCa in the memory cell block BLK0is different from the distribution of threshold voltages of the memory cells MCa in the other memory cell blocks BLK1to BLK3.

For example, the number of the memory cells MCa provided in the memory cell block BLK0is smaller than the number of the memory cells MCb provided in the memory cell blocks BLK1to BLK3. For example, the size of the memory cell block BLK0which stores the ROM data is smaller than the sizes of the other memory cell blocks BLK. It is preferable that only the data which requires good data retention characteristics be retained in the memory cell block BLK0. For example, the memory cell block BLK0has a large memory hole diameter, and thus the bit storage density of the memory cell block BLK0is low. Thus, in order to suppress reduction of the entire storage capacity, it is preferable that the size of the memory cell block BLK0be smaller than the sizes of the other memory cell blocks BLK1to BLK3.

FIG. 4andFIG. 5are schematic views showing the characteristics of the non-volatile memory device100according to the first embodiment.FIG. 4is a schematic view illustrating the distribution of the memory hole diameter in the memory cell blocks BLK0to BLK3.FIG. 5is a graph showing a change of the threshold of the memory cell MC with time.

As shown inFIG. 4, the diameters of the plurality of memory holes formed in each of the memory cell blocks BLK have variation. For example, the diameters of the memory holes in each memory cell block BLK have a Gaussian distribution. If a median value (a diameter corresponding to a peak of frequency) of the distribution of the memory hole diameters of the memory cell blocks BLK0is represented by D1, and a median value (a diameter corresponding to a peak of frequency) of the distribution of the memory hole diameters of the memory cell blocks BLK1to BLK3is represented by D2, the formula D1>D2is satisfied.

For example, if a standard deviation of the diameter distribution of the memory holes in the memory cell blocks BLK1to BLK3is represented by σ2, it is preferable that D1>D2±σ2. In addition, if a standard deviation of the diameter distribution of the memory holes in the memory cell block BLK0is represented by σ1, it is more preferable that D1>D2+σ1+σ2.

In addition, the cross-sectional shape perpendicular to the Z-direction of the memory hole is not limited to a perfect circle, and for example, can be any shape, such as an ellipse, polygons or the like. In such a case, the memory hole diameter DHcan be calculated by using the following formula.
DH=2×(S/π)1/2(1)

Here, S is an area of the cross-section perpendicular to the Z-direction of the memory hole.

FIG. 5is a graph showing a result of simulation of a threshold voltage change of the memory cell MC. A horizontal axis represents data retention time, and a vertical axis represents the amount of change ΔVth of the threshold voltage.

The simulation is performed with respect to the memory cells MC provided in each of three memory holes with diameters of 60 nm, 70 nm and 80 nm. The memory film20has a structure in which the block insulating film, the electric charge storage layer and the tunnel insulating film are stacked towards a central direction of the memory holes.

The block insulating film includes a silicon nitride film with a thickness of 4 nm in contact with the word line, and a silicon oxide film with a thickness of 7 nm in contact with the silicon nitride film. The electric charge storage layer is formed by a silicon nitride film with a thickness of 5 nm. The tunnel insulating film is formed by a silicon oxide film with a thickness of 5 nm. The electric charge storage layer is in contact with the silicon oxide film in the block insulating film. Furthermore, a depth of the electron trap in the electric charge storage layer is set to 1.5 eV, and when electrons move from the electric charge storage layer to the channel body10, a barrier height of the tunnel insulating film is set to 3.2 eV.

As shown inFIG. 5, if the memory hole diameter is 70 nm, the threshold voltage of the memory cell MC falls by approximately 0.25 V at a data retention time of 1×108seconds. If the memory hole diameter is 60 nm, the threshold voltage falls even greater, that is, falls by approximately 0.63 V at the data retention time of 1×108seconds. In contrast to this, if the memory hole diameter is 80 nm, an amount by which the threshold voltage falls is suppressed to approximately 0.05 V at the data retention time of 1×108seconds.

FIG. 5shows a remarkable improvement of the data retention characteristics according to expansion of the memory hole diameter. For example, the variation of the threshold voltage of the memory cell MCa is smaller than the variation of the threshold voltage of the memory cell MCb. Thus, it is possible to have a greater number of multiple value levels of the memory cell MCa than the number of multiple value levels of the memory cell MCb. Then, if the rate of increase of storage bit density due to the introduction of multiple value levels is greater than the rate of decrease of the storage bit density due to enlargement of the memory hole diameter, it is also possible to increase the storage capacity of the non-volatile memory device100.

FIG. 6is an example of a schematic planar view showing a structure of the memory cell array1according to the first embodiment.FIG. 6shows a relationship between the memory holes30aand30b, and the plurality of bit lines BL which are arranged in the laminate bodies110and120.

As shown inFIG. 6, for example, the plurality of bit lines BL extend in the X-direction, and are provided so as to be mounted over the laminate bodies110and120. For example, each bit line BL is electrically connected to the channel body10provided inside any of the memory holes through the contact plug23. For example, each bit line BL is electrically connected to the channel body10aprovided inside any one of the plurality of memory holes30aarranged in the laminate body110. In addition, each bit line BL is electrically connected to the channel body10bprovided inside any one of the plurality of memory holes30barranged in the laminate body120.

According to the embodiment, the diameter of the memory hole30ais larger than the diameter of the memory hole30b. For example, if the sizes of the laminate bodies110and120are the same, the number of memory holes30aprovided in the laminate body110is smaller than the number of memory holes30bprovided in the laminate body120.

The non-volatile memory device100includes the plurality of bit lines BL which are electrically connected to at least one of the channel body10aand the channel body10b. As illustrated in FIG.6, the plurality of bit lines BL include a first bit line BLx and a second bit line BLy. The first bit line BLx is electrically connected to both the channel body10aand the channel body10b. The second bit line BLy is not electrically connected to the channel body10a, and is electrically connected to the channel body10b.

In another embodiment, for example, a width of the laminate body110widens in the X-direction, therefore the number of the memory holes30amay be the same as the number of the memory holes30b. In such a case, it is possible to configure in such a manner that the plurality of bit lines BL include only the first bit lines BLx which are electrically connected to both the channel body10aprovided in any one of the memory holes30aand the channel body10bprovided in any one of the memory holes30b.

FIGS. 7A and 7Bare examples of schematic planar views showing the memory cell arrays2and3according to variations of the first embodiment.FIG. 7AandFIG. 7Brespectively show the shapes of the cross-section perpendicular to the Z-direction of the memory holes60a,60b,70aand70b. In addition, the word lines WLa and WLb which are illustrated inFIGS. 7A and 7Bare positioned at the same laminate level among a plurality of word lines WL.

In the example shown inFIG. 7A, memory holes60aare provided in the laminate body110, and memory holes60bare provided in the laminate body120. Each cross-section of the memory holes60aand60bhas a rectangular shape, and four corners thereof are rounded. A radius of curvature of the four corners of the memory hole60ais, for example, Ra. A radius of curvature of the four corners of the memory hole60bis, for example, Rb.

The channel body10a, the memory film20a, and a core40aare provided inside the memory hole60a. The channel body10b, the memory film20b, and a core40bare provided inside the memory hole60b. The memory film20ahas a curved surface in which a radius of curvature of an outer perimeter is Ra. The memory film20bhas a curved surface in which a radius of curvature of an outer perimeter is Rb.

The radius of curvature Ra is larger than the radius of curvature Rb. Thus, a minimum voltage required for writing data to the memory cell MCa including the memory film20ais greater than a minimum voltage required for writing data to the memory cell MCb including the memory film20b(the same is also true for data erasing). In addition, for the same reason as this (the concentration of electric field towards the tunnel insulating film can be relieved because the radius of curvature is large), the memory cell MCa is better in data retention characteristics than the memory cell MCb.

In the example shown inFIG. 7B, memory holes70aare provided in the laminate body110, and memory holes70bare provided in the laminate body120. Each of cross-sections of the memory holes70aand70bhave an elliptical shape, and have radiuses of curvature different from each other in two axial directions of the ellipse.

For example, a cross-section perpendicular to the Z-direction of the memory hole70ahas radiuses of curvature Ra1and Ra2. The radius of curvature Ra1is smaller than the radius of curvature Ra2. For example, a cross-section perpendicular to the Z-direction of the memory hole70bhas radiuses of curvature Rb1and Rb2. The radius of curvature Rb1is smaller than the radius of curvature Rb2.

The channel body10a, the memory film20a, and the core40aare provided inside the memory hole70a. The channel body10b, the memory film20b, and the core40bare provided inside the memory hole70b. Radiuses of curvature of the perimeter of the memory film20aare Ra1and Ra2. Radiuses of curvature of the perimeter of the memory film20bare Rb1and Rb2.

In the memory cell MCa including the memory film20a, a minimum voltage for writing (or erasing) the data is determined by the radius of curvature Ra1which is the smaller one of the two radiuses of curvature Ra1and Ra2. In the memory cell MCb including the memory film20b, a minimum voltage for writing (or erasing) the data is determined by the radius of curvature Rb1which is the smaller one of the two radiuses of curvature Rb1and Rb2. Then, the radius of curvature Ra1is larger than the radius of curvature Rb1. Thus, the minimum voltage required for writing the data to the memory cell MCa is greater than the minimum voltage required for writing the data to the memory cell MCb. In addition, for the same reason as this (the concentration of electric field towards the tunnel insulating film can be relieved because the radius of curvature is large), the memory cell MCa including the memory film20ais better in data retention characteristics than the memory cell MCb including the memory film20b.

The embodiment is not limited to the examples shown inFIGS. 7A and 7B. For example, a cross-sectional shape perpendicular to the Z-direction of the memory hole may be an arbitrary shape with an arbitrary number of radiuses of curvature. Then, the minimum value of the radiuses of curvature of the cross-section perpendicular to the Z-direction of the memory film20aprovided between any one of the plurality of word lines WLa and the channel body10ais greater than the minimum value of the radiuses of curvature of the cross-section perpendicular to the Z-direction of the memory film20b.

FIG. 8is an example of a schematic planar view showing another memory cell array4according to the variation of the first embodiment.FIG. 8shows a cross-sectional shape perpendicular to the Z-direction of memory holes80a,80band80c. In addition, the word lines WLa, WLb and WLc are positioned at the same laminate level among the plurality of word lines WL.

In the example shown inFIG. 8, the memory hole80ais provided in the laminate body110, the memory hole80bis provided in the laminate body120, and the memory hole80cis provided in a laminate body130. The cross-sections of the memory holes80a,80band80chave diameters D1, D2and D3, respectively. Then, D1is larger than D2, and D2is larger than D3.

The channel body10a, the memory film20a, and the core40aare provided inside the memory hole80a. The channel body10b, the memory film20b, and the core40bare provided inside the memory hole80b. The channel body10cand the memory film20care provided inside the memory hole80c. The outer diameter of the memory film20ais D1, the outer diameter of the memory film20bis D2, and an outer diameter of the memory film20cis D3. For example, D1is set to be 120 nm, D2is set to be 100 nm, and D3is set to be 80 nm.

For example, the laminate body110is provided in the memory cell block BLK0. In addition, the laminate body120is provided in the memory cell block BLK1. The laminate body130is provided in the memory cell blocks BLK2and BLK3. Table 1 illustrates the characteristics of memory cells arranged in each memory cell block.

The outer diameter of the memory film20in the memory cell MCa of the memory cell block BLK0is the largest one, and the outer diameters of the memory films20in memory cells MCc of the memory cell blocks BLK2and BLK3are the smallest ones. In contrast to this, the data retention characteristics of the memory cell block BLK0is the best one, and the data retention characteristics of the memory cell blocks BLK2and BLK3are the poorest ones. The data retention characteristics of the memory cell block BLK1have an intermediate level between the data retention characteristics of the memory cell block BLK0and the memory cell blocks BLK2and BLK3.

For example, if the thicknesses in the direction perpendicular to the Z-direction of the memory films20ato20care the same as each other, a large voltage (that is, high energy) is required for writing (or erasing) data to the memory cell block BLK0including the memory film20awith a large outer diameter. Due to this, in the repeated operations of writing and erasing, the tunnel insulating film is degraded by the carriers (electrons and positive holes) with high energy. In addition, since the electric field of the block insulating film is strong at the time of writing and erasing in the memory cell MCa with a large outer diameter of the memory film20, a proportion of the carriers (electrons and positive holes) passing through the electric charge storage layer without being trapped is higher than that in the memory cell MCc with a small outer diameter of the memory film20. Due to this, in the memory cell MCa, an amount of electric charges passing through during the repeated operations of writing and erasing increases, and a rate of degrading of the memory film increases. Because of the above-described two reasons, the memory cell MCa with a large outer diameter of the memory film20has a low endurance with respect to repeated writing and erasing. That is, the memory cell block BLK0has good data retention characteristics in a fresh state, and has poor data retention characteristics after repeated operations of writing and erasing. Thus, for example, it is preferable that the memory cell block BLK0be used as a ROM (Read Only Memory) that stores the data which is not rewritten and erased.

Meanwhile, the memory cell blocks BLK2and BLK3have poor data retention characteristics in a fresh state, and have good data retention characteristics after repeated operations of writing and erasing. Thus, it is preferable that the memory cell blocks BLK2and BLK3be used as memory areas in which the data is frequently written and erased. It is preferable that the memory cell block BLK1with intermediate data retention characteristics be used as memory areas in which the number of writing and erasing operations is small. In addition, the data retention characteristics in the fresh state of the memory cell block BLK1are better than the data retention characteristics of the memory cell blocks BLK2and BLK3. Due to this, if it is assumed that the number of writing and erasing operation is small, the memory cell MCb arranged in the memory cell block BLK1can have better multiple value levels than the memory cell MCc arranged in the memory cell blocks BLK2and BLK3. For example, the memory cell MCb may be configured by a three-bit cell and the memory cell MCc may be configured by a two-bit cell.

As described above, for example, the non-volatile memory device100can include three or more types of memory cell blocks having memory hole diameters different from each other. Then, the data is stored by selecting the memory cell block which is appropriate for the number of required rewriting and for data retention time, and thereby it is possible to improve the reliability of the non-volatile memory device100.

Second Embodiment

FIG. 9is an example of a schematic cross-sectional view showing a memory cell array5of a non-volatile memory device200according to a second embodiment.FIG. 9shows a cross-section in parallel with an X-Z plane of a memory hole90.

As shown inFIG. 9, the memory hole90is provided in a tapered shape, a diameter of which becomes smaller downwardly from the top (−Z-direction). The memory hole90passes through word lines WL0to WLn. A memory film20, a channel body10, and a core40are sequentially formed in an inside wall of the memory hole90. The memory film20is positioned between each of the word lines WL0to WLn and the channel body10. In addition, for the sake of simplicity, word lines WL1to WLn−1 are not shown inFIG. 9.

For example, an outer diameter of the memory film20positioned between the word line WLn which is a top layer of the word lines WL0to WLn, and the channel body10, is DUM. An outer diameter of the memory film20positioned between the word line WL0which is a bottom layer of the word lines WL0to WLn, and the channel body10, is DLM. Then, the DUM is larger than the DLM. In addition, the DUM is larger than an outer diameter of the memory film20positioned between each of the plurality of word lines WL1to WLn−1 which are not shown, and the channel body10.

For example, a first memory cell (hereinafter, memory cell MCU) is formed between the word line WLn and the channel body10. A second memory cell (hereinafter, memory cell MCL) is formed between each of the word lines WL0to WLn−1 and the channel body10. That is, the outer diameter of the memory film20included in the memory cell MCU is larger than the outer diameter of the memory film20included in the memory cell MCL. Thus, the memory cell MCU has better data retention characteristics than those of the memory cell MCL.

For example, the non-volatile memory device200includes a peripheral circuit shown inFIG. 2A. Then, the control circuit19illustrated inFIG. 2Awrites the data having a longer retention time than that of the data which is written to the memory cell MCL, to the memory cell MCU. In other words, the control circuit19controls addresses of the data in such a manner that the number of writings and erasings of the data of the memory cell MCL is greater than the number of writings and erasings of the data of the memory cell MCU.

As shown inFIG. 9, if the memory hole90has a tapered shape, the memory film20positioned between the word line WL of an upper layer and the channel body10has a larger outer diameter than that of the memory film20positioned between the word line WL of a lower layer and the channel body10. Thus, the memory cell MC of the upper layer has better data retention characteristics than the memory cell MC of the lower layer. Therefore, the control circuit19may control the address in such a manner that the data having a longer retention time than that of the data which is written to the memory cell MC of the lower layer is written to the memory cell of the upper layer.

For example, the data with a long retention time may be written to the memory cell MC formed between each of the three word lines WLn-2to WLn of the upper layer and the channel body10, and the data with a short retention time may be written to the memory cell MC formed between the word line WL of the layer lower than those and the channel body10.

The cross-sectional shape in parallel with the X-Z plane of the memory hole is not limited to a tapered shape. That is, the control circuit19may control in such a manner that the data with a long retention time is written to the memory cell MCa including the memory film20having the largest outer diameter of the plurality of memory cells MC arranged in the Z-direction of one memory hole, and the data with a short retention time is written to the other memory cells MC.