SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate, a drain region; a source/gate region, an insulating layer located above the semiconductor layer, and a field plate located on the insulating layer, wherein the field plate includes an innermost periphery, an outermost periphery, a first straight line portion and a second straight line portion located between the innermost periphery and the outermost periphery, and a first connection portion connecting the first straight line portion and the second straight line portion, wherein each of the innermost periphery, the outermost periphery, the first straight line portion, the second straight line portion and the first connection portion is a part of a current path, and wherein each of the first straight line portion and the second straight line portion extends in a second direction intersecting with the first direction in a plan view.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application No. 2023-085987 filed on May 25, 2023. The entire contents of the above-identified application are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND

Japanese Patent Publication No. 2017-208420 discloses a semiconductor device including a junction field effect transistor (JFET). This semiconductor device includes a p-type semiconductor substrate, an n-type semiconductor layer formed on the semiconductor substrate, an n-type drain region formed at a surface region of an n-type semiconductor region, a plurality of n-type source regions formed at the surface region of the semiconductor region spaced apart from the drain region, a p-type gate region formed at the semiconductor region between the source regions, and a resistive field plate having a spiral shape in a plan view disposed on the semiconductor region between the drain region and the source region and electrically connected to the drain region and ground.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for identical elements or elements having identical functions, and redundant description will be omitted. “Identical” and words similar thereto in this specification are not limited to only “completely identical”. In addition, since the drawings are for conceptually describing the embodiments, the dimensions of each components represented and the ratios thereof may be different from actual ones.

FIG.1is a plan view showing a chip of a semiconductor device according to an embodiment. As shown inFIG.1, the semiconductor device100includes a chip101(semiconductor chip) made of silicon having a rectangular parallelepiped shape. The chip101has a first main face102and a second main face103that are a pair of main surfaces, and a first side face104A, a second side face104B, a third side face104C and a fourth side face104D that connect the first main face102and the second main face103. In the following description, an extending direction of the first side face104A and the second side face104B in a plan view is referred to as a first direction X, an extending direction of the third side face104C and the fourth side face104D in a plan view is referred to as a second direction Y, and a normal direction of the first main face102and the second main face103is referred to as a third direction Z. The second direction Y is a direction intersecting the first direction X in a plan view, and the third direction Z corresponds to a thickness direction of the chip101.

The first main face102and the second main face103are formed in a quadrangular shape when viewed from the third direction Z, but are not limited thereto. In the present embodiment, the first main face102is the top surface, and the second main face103is the bottom surface. Therefore, a configuration located near the first main face102in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device100, and a configuration located near the second main face103in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device100.

The semiconductor device100includes a plurality of divided device regions105on the first main face102. The number and arrangement of the plurality of device regions105are arbitrary. Each of the plurality of device regions105includes a functional device formed using regions inside and outside the chip101. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device and a passive device are combined.

The semiconductor switching device includes, for example, at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT) and a JFET. The semiconductor rectifying device may include at least one of a PN junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor and a fuse.

At least one of the plurality of device regions105includes an FET structure106(transistor structure). A voltage Vdg between drain and gate that applied to the FET structure106is, for example, 500 V or more and 1500 V or less. As described below, in the present embodiment, the FET structure106has a JFET structure. The structure of the FET structure106will be described below.

FIG.2is a schematic cross-sectional view taken along line II-II shown inFIG.1.FIG.3is an enlarged view of a portion surrounded by an alternate long and short dash line III shown inFIG.2.FIG.4is a cross-sectional view taken along line IV-IV shown inFIG.2.FIG.5is an enlarged view of a main part ofFIG.4.FIG.6Ais an enlarged view of a portion surrounded by a broken line VIa inFIG.4, andFIG.6Bis an enlarged view of a portion surrounded by a broken line VIb inFIG.4.FIG.7is an enlarged view of a main part ofFIG.4.FIG.8is a schematic cross-sectional view taken along line VIII-VIII shown inFIG.7.FIG.9is a schematic cross-sectional view taken along line IX-IX shown inFIG.7.

As shown inFIG.2and the like, the FET structure106includes a semiconductor substrate2having a first conductivity type and a semiconductor layer3located on the semiconductor substrate2and having a second conductivity type. In the present embodiment, the first conductivity type is p-type, and the second conductivity type is n-type.

The semiconductor substrate2is a high-resistance silicon substrate. The p-type impurity concentration of the semiconductor substrate2is set to a relatively low value. In the present embodiment, the p-type impurity concentration of the semiconductor substrate2is, for example, 1.0×1013cm−3or more and 1.0×1014cm−3or less.

The semiconductor layer3is an epitaxial layer formed on the semiconductor substrate2. The n-type impurity concentration of the semiconductor layer3is, for example, 1.0×1015cm−3or more and 1.0×1016cm−3or less. The thickness of the semiconductor layer3is, for example, 1 μm or more and 10 μm or less. A drain region4having the second conductivity type is located in the semiconductor layer3.

The drain region4is a region that functions as a drain of the FET structure106and has an oval ring shape in a plan view. The n-type impurity concentration of the drain region4is higher than the n-type impurity concentration of the semiconductor layer3. The n-type impurity concentration of the drain region4is, for example, 1.0×1019cm−3or more and 1.0×1020cm−3or less. An n-type drain-side well region5in contact with the drain region4is formed below the drain region4in the semiconductor layer3.

The drain-side well region5is a region covering a bottom portion and a side portion of the drain region4, and has an oval ring shape surrounding the drain region4in a plan view. The n-type impurity concentration of the drain-side well region5is higher than the n-type impurity concentration of the semiconductor layer3and lower than the n-type impurity concentration of the drain region4. The n-type impurity concentration of the drain-side well region5is, for example, 1.0×1016cm−3or more and 1.0×1017cm−3or less. An n-type drain buffer region6is formed below the drain-side well region5.

The drain buffer region6is a region that forms a PN junction with the semiconductor substrate2, and is located in the semiconductor substrate2and in the semiconductor layer3to cross the boundary between the semiconductor substrate2and the semiconductor layer3. Since the drain buffer region6and the semiconductor substrate2form a PN junction portion, the breakdown voltage of the semiconductor device100is increased. The drain buffer region6has an oval shape in a plan view. The peripheral edge of the drain buffer region6is located outside the outer peripheral edge of the drain region4in a plan view. The n-type impurity concentration of the drain buffer region6is higher than the n-type impurity concentration of the drain-side well region5and lower than the n-type impurity concentration of the drain region4. The n-type impurity concentration of the drain buffer region6is, for example, 1.0×1018cm−3or more and 1.0×1019cm−3or less.

As shown inFIGS.7to9, a source/gate region9including an n-type source region7and a p-type gate region8is formed in the semiconductor layer3. The n-type source region7and the p-type gate region8are electrically connected to each other and are alternately arranged at intervals. Therefore, a plurality of source regions7and a plurality of gate regions8are provided in the semiconductor layer3. In the present embodiment, the source/gate region9is spaced apart from the drain region4and has an oval ring shape located around the drain region4in a plan view.

The source region7is in an electrically floating state and has a quadrangular shape in a plan view. The n-type impurity concentration of the source region7is substantially identical to the n-type impurity concentration of the drain region4. The gate region8is electrically connected to ground (GND) and has a quadrangular shape in a plan view. The p-type impurity concentration of the gate region8is higher than the p-type impurity concentration of the semiconductor substrate2. The p-type impurity concentration of the gate region8is, for example, 1.0×1019cm−3or more and 1.0×1020cm−3or less.

The source/gate region9includes an n-type source-side well region10and a p-type gate-side well region11. A plurality of source-side well regions10is provided in the semiconductor layer3. The source-side well region10is located in the semiconductor layer3and below the source region7. The gate-side well region11is located in the semiconductor substrate2, in the semiconductor layer3and below the gate region8.

The source-side well region10is a region that is in contact with the source region7and covers a bottom portion and a side portion of the source region7. The plurality of source-side well regions10is intermittently formed. In a plan view, each source-side well region10surrounds the corresponding source region7. The source-side well region10has a quadrangular shape in a plan view, and has a projected portion10aprojecting toward the drain region4more than the gate-side well region11. A bottom portion of the source-side well region10is located in the semiconductor layer3. The n-type impurity concentration of the source-side well region10is substantially identical to the n-type impurity concentration of the drain-side well region5. Therefore, the n-type impurity concentration of the source-side well region10is lower than the n-type impurity concentration of the source region7.

The gate-side well region11is a region that contacts the gate region8and covers a bottom portion and a side portion of the gate region8. The gate-side well region11is formed in the semiconductor layer3so as to be in contact with a side portion and a bottom portion of the source-side well region10other than the projected portion10a.A contact portion between the gate-side well region11and the source-side well region10forms a PN junction portion. The gate-side well region11includes a first region11alocated between two adjacent source-side well regions10each other, a second region11bconnecting the adjacent first region11a,and a third region11clocated below the first region11aand the second region11b.

In the present embodiment, the p-type impurity concentration of the first region11ais identical to the p-type impurity concentration of the second region11b.The p-type impurity concentration of the third region11cis higher than the p-type impurity concentration of the first region11aand the p-type impurity concentration of the second region11b.The p-type impurity concentration of the first region11aand the second region11bis, for example, 1.0×1017cm−3or more and 1.0×1018cm−3or less. The p-type impurity concentration of the third region11cis, for example, 1.0×1018cm−3or more and 1.0×1019cm−3or less.

The first region11ais a region that covers the bottom portion and the side portion of the gate region8. The bottom portion of the first region11ais located in the semiconductor layer3and has a quadrangular shape in a plan view. The second region11bis a region located on the opposite side of the drain region4across the first region11a.A bottom portion of the second region11bis located in the semiconductor layer3and has an oval ring shape in a plan view. The third region11cis a region formed in the semiconductor substrate2and in the semiconductor layer3so as to cross the boundary between the semiconductor substrate2and the semiconductor layer3, and has an oval ring shape in a plan view. The third region11cis in contact with the bottom portion of the first region11a,the bottom portion of the second region11band a part of the bottom portion of each source-side well region10. A bottom portion of the third region11cis located in the semiconductor substrate2, but is not limited thereto.

The current flowing between the drain region4and the source region7via the semiconductor layer3is controlled by applying a predetermined control voltage to the source/gate region9. More specifically, when a predetermined control voltage is applied to the source region7, a depletion layer expands from the PN junction portion formed by the source-side well region10and the gate-side well region11. Thus, the source region7and the source-side well region10are depleted. As a result, a current path between the drain region4and the source region7is closed, so that no current flows between the drain region4and the source region7. On the other hand, when the application of the control voltage to the source region7is released, the depletion of the source region7and the source-side well region10is released. As a result, the current path between the drain region4and the source region7is opened, so that current flows between the drain region4and the source region7. In the FET structure106, the current flowing between the drain region4and the source region7is controlled in this manner.

As shown inFIGS.2,3,8and9, a local oxidation of silicon (LOCOS) film12as an example of an insulating layer that selectively exposes the drain region4and the source/gate region9is located above the semiconductor layer3. The LOCOS film12is located between the drain region4and the source/gate region9in a plan view. The thickness of the LOCOS film12is, for example, 5000 Å or more and 15000 Å or less.

The LOCOS film12includes an inner LOCOS film13which has an oval shape in a plan view and covers a region surrounded by the drain region4, and an outer LOCOS film14which has an oval ring shape in a plan view and covers a region between the drain region4and the source/gate region9. The outer LOCOS film14covers one end portion of the projected portion10aof the source-side well region10and one end portion of the gate-side well region11. In the present embodiment, each one end portion corresponds to an end portion located above the semiconductor layer3and closest to the drain region4.

In the semiconductor layer3, a region overlapping the outer LOCOS film14corresponds to a drift region15. The length of the drift region15is, for example, 80 μm or more and 200 μm or less. The length of the drift region15corresponds to the channel length of the FET structure106. A p-type resurf layer16is formed in a part of the semiconductor layer3which in contact with the outer LOCOS film14. The resurf layer16forms a PN junction portion with the drift region15in the semiconductor layer3. In a plan view, the resurf layer16has an elliptical ring shape along the planar shape of the outer LOCOS film14. The p-type impurity concentration of the resurf layer16is higher than the p-type impurity concentration of the semiconductor substrate2. The p-type impurity concentration of the resurf layer16is, for example, 1.0×1015cm−3or more and 1.0×1016cm−3or less.

A resistive field plate20forming a current path CP is located on the outer LOCOS film14. The field plate20has a function of suppressing disturbance of an electric field in the semiconductor layer3or the like, a function of suppressing local electric field concentration, a function of monitoring the voltage Vdg between drain and gate that is a high-voltage, and the like. The field plate20is disposed between the drain region4and the source/gate region9in a plan view. The field plate20functions as a resistor having a predetermined resistance value between the drain region4and ground. Thus, the field plate20forms the current path CP between the drain region4and ground. The resistance value of the field plate20is, for example, 20 MΩ or more and 100 MΩ or less. The field plate20comprises, for example, polysilicon which is rendered conductivity by doping. The impurity added to the polysilicon is phosphorus, boron, or the like. The resistance value of the field plate20can be adjusted by adjusting the quantity of the impurity (impurity concentration) added to the polysilicon. The impurity concentration in a part of the field plate20may be higher than the impurity concentration in other portions of the field plate20. The field plate20has an innermost periphery201, an outermost periphery202and an intermediate portion203.

The innermost periphery201is a portion electrically connected to the drain region4, and is closest to the drain region4in the field plate20. Therefore, in a plan view, no field plate20is present inside the innermost periphery201of the field plate20. The innermost periphery201constitutes a part of the current path CP formed by the field plate20. As shown inFIGS.6A and6B, the width W1of the innermost periphery201is larger than the width W2of the outermost periphery202, but is not limited thereto. The innermost periphery201has an oval shape in a plan view. The innermost periphery201includes: straight portions201a,201bwhich are separated from each other and extend along the second direction Y; a curved line portion201cwhich is connected to one end of the straight line portion201a,201band has a circular arc shape; and a curved line portion201dwhich is connected to the other end of the straight line portion201a,201band has a circular arc shape. Although not illustrated, each of the straight line portions201a,201bis located between the drain region4and the source/gate region9in the first direction X. Each of a part of the curved line portion201cand a part of the curved line portion201dis located outside the drain region4in the second direction Y. Therefore, the entirety of the straight line portions201a,201b,the other part of the curved line portion201cand the other part of the curved line portion201doverlap the region in which current flows in the FET structure106(operation region).

The outermost periphery202is a portion that is electrically connected to the source/gate region9and ground, and is closest to the source/gate region9in the field plate20. Therefore, no field plate20is present outside the outermost periphery202of the field plate20. As shown inFIGS.4and7, in a plan view, the outermost periphery202is located closer to the drain region4than the projected portion10a.The outermost periphery202, as same as the innermost periphery201, constitutes a part of the current path CP formed by the field plate20. The outermost periphery202has an oval shape in a plan view. The outermost periphery202includes: straight portions202a,202bthat are separated from each other and extend along the second direction Y; a curved line portion202cthat is connected to one ends of the straight portions202a,202b;and a curved line portion202dthat is connected to the other ends of the straight portions202a,202b.Although not shown, each of the straight line portions202a,202bis located between the drain region4and the source/gate region9. Each of at least a part of the curved line portion202cand at least a part of the curved line portion202dis located outside of the drain region4in the second direction Y and has an arc shape.

The innermost periphery201is located on the virtual ellipse VC1, and the outermost periphery202is located on the virtual ellipse VC2. The virtual ellipses VC1and VC2are respectively parts of concentric ellipses centered on the drain region4. Therefore, the innermost periphery201and the outermost periphery202are arranged on a virtual concentric ellipse having the drain region4as a center.

The intermediate portion203is a main portion in the field plate20and is located between the innermost periphery201and the outermost periphery202. The intermediate portion203includes a path portion210that forms the current path CP and a non-path portion220that is spaced apart from the path portion210and located outside of the path portion210in the second direction Y. The path portion210includes a first portion located between the straight line portions201a,202ain the first direction X and a second portion located between the straight line portions201b,202bin the first direction X. The first portion and the second portion have a substantially identical shape. The non-path portion220includes a third portion located between the curved line portions201c,202cin the second direction Y and a fourth portion located between the curved line portions201d,202din the second direction Y. The third portion and the fourth portion have a substantially identical shape. Therefore, the structure of the path portion210corresponding to the first portion and the structure of the non-path portion220corresponding to the third portion will be mainly described below.

The path portion210includes a plurality of straight line portions211extending along the second direction Y and spaced apart from each other, a plurality of first connection portions212connecting two straight line portions211adjacent to each other in the first direction X, a second connection portion213located closest to the innermost periphery201in the path portion210, and a third connection portion214located closest to the outermost periphery202in the path portion210. Each of the plurality of straight line portions211, the plurality of first connection portions212, the second connection portion213and the third connection portion214has a band shape in a plan view and constitutes a part of the current path CP. The plurality of straight line portions211is intermittently arranged in the first direction X. The interval between two adjacent straight line portions211is substantially constant. The width of each straight line portion211is also substantially constant. In the following description, among the plurality of straight line portions211, a portion located closest to the innermost periphery201is referred to as a first straight line portion211a,a portion located adjacent to the first straight line portion211ain the first direction X is referred to as a second straight line portion211b,and a portion located closest to the straight line portion202ain the outermost periphery202is referred to as an outermost straight line portion211c.The first straight line portion211ais located adjacent to the straight line portion201a(third straight line portion) in the innermost periphery201in the first direction X.

In the present embodiment, the plurality of straight line portions211, the plurality of first connection portions212, the second connection portion213and the third connection portion214are alternately disposed so that the path portion210has a bellows shape (zigzag shape) in a plan view. To be specific, one end of the first straight line portion211ain the second direction Y and one end of the second straight line portion211bin the second direction Y are connected to each other via one of the plurality of first connection portions212extending in the first direction X. At this time, each of an angle formed by the first straight line portion211aand one of the first connection portions212and an angle formed by the second straight line portion211band one of the first connection portions212is a right angle or substantially a right angle. The other end of the first straight line portion211ain the second direction Y and the straight line portion201ain the innermost periphery201are connected to each other via the second connection portion213extending in the first direction X. At this time, each of an angle formed by the first straight line portion211aand the second connection portion213and an angle formed by the straight line portion201aand the second connection portion213is a right angle or substantially a right angle. The other end of the second straight line portion211bin the second direction Y and another straight line portion211adjacent to the second straight line portion211bare connected to each other via another one of the plurality of first connection portions212. At this time, each of an angle formed by the second straight line portion211band another one of the first connection portions212and an angle formed by another straight line portion211and another one of the first connection portions212is a right angle or substantially a right angle. Similarly, one end of the outermost straight line portion211cin the second direction Y and the straight line portion202ain the outermost periphery202are connected to each other via the third connection portion214extending in the first direction X. At this time, each of an angle formed by the outermost straight line portion211cand the third connection portion214and an angle formed by the straight line portion202aand the third connection portion214is a right angle or substantially a right angle. In one example, while curved lines may not be used, only straight lines may be constituted to the path portion210in a plan view.

As shown inFIGS.4and5, the non-path portion220has a plurality of curved line portions221spaced apart from each other and disposed along the second direction Y. Each of the plurality of curved line portions221is spaced apart from the innermost periphery201, the outermost periphery202and the path portion210(i.e., the plurality of straight line portions211, the plurality of first connection portions212, the second connection portion213and the third connection portion214). Each of the plurality of curved line portions221has an arc shape and is provided on a concentric circle. The plurality of curved line portions221is intermittently arranged in the second direction Y. Two curved line portions221adjacent to each other in the second direction Y may be capacitive coupled to each other via an interlayer insulating film33described later. From the viewpoint of uniformizing the capacitance difference, the interval between two curved line portions221adjacent to each other in the second direction Y is substantially constant. From the viewpoint of accurately and uniformly maintaining the interval, a width W3of each curved line portion221may be larger as it is farther from the path portion210in the second direction Y. Hereinafter, among the plurality of curved line portions221, a portion positioned closest to the innermost periphery201is referred to as a first curved line portion221a,and a portion positioned adjacent to the first curved line portion221ain the second direction Y is referred to as a second curved line portion221b.The first curved line portion221ais adjacent to the curved line portion201cin the innermost periphery201in the second direction Y. The first curved line portion221ais capacitive coupled to the curved line portion201c.Among a plurality of the curved line portions221a,as closer to the first curved line portion221, its potential is higher or lower.

As shown inFIG.4, the first curved line portion221ais located on the virtual ellipse VC3(on the first virtual ellipse) together with the first straight line portion211a.The second curved line portion221bis located on the virtual ellipse VC4(on the second virtual ellipse) together with the second straight line portion211b.The virtual ellipses VC3and VC4are parts of concentric ellipses centered on the drain region4, similarly to the virtual ellipses VC1and VC2. For this reason, each of the plurality of straight line portions211in the path portion210and the plurality of curved line portions221in the non-path portion220is disposed on a virtual concentric ellipse centered on the drain region4.

As described above, the first portion and the second portion in the path portion210have a substantially identical shape, and the third portion and the fourth portion in the non-path portion220have a substantially identical shape. Therefore, each straight line portion included in the second portion is also arranged on the virtual concentric ellipse described above, and each curved line portion included in the fourth portion is also arranged on the virtual concentric ellipse described above. For example, among a plurality of the straight line portions included in the second portion, two straight line portions located on the opposite sides of the first straight line portion211aand the second straight line portion211bacross the innermost periphery201in the first direction X are located on the virtual ellipses VC1and VC2, respectively. Similarly, among a plurality of the curved line portions included in the fourth portion, two curved line portions located on the opposite sides of the first curved line portions221aand the second curved line portions221bacross the innermost periphery201in the second direction Y are located on the virtual ellipses VC1and VC2, respectively.

An outermost peripheral ground conductor film21electrically connected to ground is disposed on the outer LOCOS film14between the source/gate region9and the field plate20in a plan view. The outermost peripheral ground conductor film21has an annular shape surrounding the field plate20in a plan view. The outermost peripheral ground conductor film21is electrically connected to the gate region8and is not physically connected to the field plate20. That is, the outermost peripheral ground conductor film21is separated from the field plate20.

As shown inFIG.7, the outermost peripheral ground conductor film21crosses the projected portion10aof the source-side well region10and overlaps with the projected portion10ain a plan view. The outermost peripheral ground conductor film21includes polysilicon to which impurities are added. The impurity concentration of the outermost peripheral ground conductor film21is, for example, identical to the impurity concentration of the innermost periphery201and the impurity concentration of the outermost periphery202, but is not limited thereto.

A second ground conductor film50electrically connected to ground is disposed on the outer LOCOS film14between the field plate20and the outermost peripheral ground conductor film21in a plan view. In addition to the gate region8, the outermost periphery202and the outermost ground conductor film21, the second ground conductor film50is set to have the same potential (ground potential). By providing the second ground conductor film50, the breakdown voltage of the semiconductor device100can be improved.

The second ground conductor film50has an oval ring shape surrounding the field plate20in a plan view. The second ground conductor film50crosses the projected portion10ain a plan view and overlaps with the projected portion10a.In the present embodiment, the second ground conductor film50is formed integrally with the outermost peripheral ground conductor film21along the inner of the outermost peripheral ground conductor film21.

In such a configuration, the boundary between the semiconductor layer3and the projected portion10aof the source-side well region10is disposed in a region between the inner peripheral edge of the second ground conductor film50and the outermost periphery202of the field plate20in a plan view. Therefore, the outermost periphery202of the field plate20is disposed closer to the drain region4side than the boundary between the semiconductor layer3and the projected portion10aof the source-side well region10.

A drain metal30electrically connected to the drain region4, a gate metal31electrically connected to the gate region8and a source metal32electrically connected to the source region7are disposed above the semiconductor layer3. A plurality of interlayer insulating films33is laminated above the semiconductor layer3, and at least a part of the drain metal30, at least a part of the gate metal31and at least a part of the source metal32are selectively formed in the interlayer insulating film33.

The drain metal30includes a first drain metal34disposed above the drain region4and a second drain metal35disposed above the first drain metal34. The first drain metal34overlaps the drain region4and the innermost periphery201of the field plate20. The first drain metal34is electrically connected to the drain region4via a first contact36and electrically connected to the innermost periphery201via a second contact37. The second drain metal35is electrically connected to the first drain metal34via a third contact38.

The gate metal31includes a first gate metal39disposed above the gate region8and a second gate metal40disposed above the first gate metal39. The first gate metal39overlaps the gate region8, the outermost peripheral ground conductor film21and the outermost periphery202of the field plate20. The first gate metal39is electrically connected to the gate region8via a fourth contact41, electrically connected to the outermost peripheral ground conductor film21via a fifth contact42and electrically connected to the outermost periphery202via a sixth contact43. The second gate metal40is electrically connected to, for example, a ground electrode (not shown) for supplying a ground potential. The second gate metal40is electrically connected to the first gate metal39via a seventh contact44. As a result, the gate region8, the outermost periphery202of the field plate20and the outermost peripheral ground conductor film21are set to have the same potential (ground potential). In the present embodiment, the first gate metal39of the gate metal31functions as a connecting member that electrically connects the gate region8, the outermost periphery202and the outermost peripheral ground conductor film21each other. Therefore, the gate region8, the outermost periphery202and the outermost peripheral ground conductor film21have the same potential (ground potential) via the gate metal31.

The source metal32includes a first source metal45disposed above the source region7and a second source metal46disposed above the first source metal45. The first source metal45overlaps the source region7. The first source metal45is electrically connected to the source region7via an eighth contact47. The second source metal46is electrically connected to the first source metal45via a ninth contact48. The second source metal46set to be in an electrically floating state in a steady state. By applying a predetermined control voltage to the second source metal46, the current flow between the drain region4and the source region7is controlled.

The operation and effect achieved by the semiconductor device100according to the present embodiment described above will be described with reference to a comparative example described below.FIG.10is a schematic plan view showing a field plate included in an FET structure according to the comparative example. As shown inFIG.10, the field plate120included in the FET structure of the semiconductor device according to the comparative example has a shape of being spirally wound a plurality of times in a plan view. In the field plate120, straight line portions1211and curved line portions1221are alternately and continuously provided along the electric path. Therefore, in the field plate120, a current path is formed by both the straight line portions1211and the curved line portions1221. Here, the path of current flowing through the curved line portions1221are likely to be non-uniform compared to the path of current flowing through the straight line portions1211. Therefore, the actual electric resistance of the curved line portions1221are likely to vary more than the electric resistance of the straight line portions1211. Since a large number of curved line portions1221are included in the field plate120, variations in electric resistance of the curved line portions1221cannot be ignored depending on the use of the semiconductor device.

On the other hand, according to the present embodiment, in the field plate20included in the FET structure106, the path portion210of the intermediate portion203located between the innermost periphery201and the outermost periphery202includes the plurality of straight line portions211extending in the second direction Y and the plurality of first connection portions212connecting two straight line portions211adjacent to each other in the first direction X. In addition, the first connection portion212extends in the first direction X. Therefore, the proportion occupied by the portion where the electric resistance is less likely to vary, in the electric path formed by the field plate20, is larger than that in the comparative example. Therefore, according to the semiconductor device100of the present embodiment, it is possible to suppress the resistance variations of the field plate20.

In one example, each of the innermost periphery201, the outermost periphery202and the plurality of straight line portions211may be arranged in a virtual concentric oval shape centered on the drain region4. In this case, for example, variations in the capacitive coupling between the innermost periphery201and the first straight line portion211a,in the capacitive coupling between the outermost periphery202and the outermost straight line portion211cand in the capacitive coupling within the plurality of straight line portions211are suppressed.

In one example, the field plate20includes the plurality of curved line portions221spaced apart from the innermost periphery201, the outermost periphery202and the path portion210and adjacent to each other in the second direction Y. As a result, the breakdown voltage of the field plate20is favorably improved, so that the function of the field plate20is favorably exhibited.

In one example, the width W3of the plurality of curved line portions221may be larger as they are farther from the straight line portion211in the second direction Y. In this case, the interval between two curved line portions221adjacent to each other in the plurality of curved line portions221can be favorably maintained. As a result, the capacitive coupling adjacent two curved line portions221is less likely to vary.

In one example, the first connection portion212may be connected to one end of the first straight line portion211ain the second direction Y. In this case, a region the path portion210is provided can be efficiently utilized.

Hereinafter, a modification of the above-described embodiment will be described with reference toFIGS.11and12. In the description of the modification, description redundant with the above-described embodiment will be omitted, and different portions will be described. That is, the description of the above-described embodiment may be appropriately used to the modification within a technically possible range.

FIG.11is a schematic plan view showing a field plate according to the modification.FIG.12is a schematic cross-sectional view for explaining the electrical connection between the straight line portion and the curved line portion in the outermost periphery. As illustrated inFIG.11, in an outermost periphery202A included in a field plate20A, the straight line portions202a,202band the curved line portions202c,202dare physically separated from each other. Here, as shown inFIG.12, the straight line portion202aand the curved line portion202care electrically connected to each other via a conductive member60located on the field plate20A. The conductive member60has a contact61positioned on the straight line portion202aand contacting with the straight line portion202a,a contact62positioned on the curved line portion202cand contacting with the curved line portion202cand a bridge metal63contacting with the contacts61,62. The contacts61,62are conductive portions that is formed simultaneously with the first contact36, the second contact37, and the like. The bridge metal63is a conductive portion formed simultaneously with the first gate metal39and the like. Although not illustrated, in the outermost periphery202A, the straight line portion202aand the curved line portion202d,the straight line portion202band the curved line portion202c,and the straight line portion202band the curved line portion202dare electrically connected to each other via wiring similar to that of the conductive member60. As a result, the overall potential of the outermost periphery202A is favorably stabilized.

Also in the above-described modification, the same operation and effect as those of the above-described embodiment are exhibited. In the above-described embodiment and modification, the innermost periphery201may have a configuration similar to that of the outermost periphery202A. As a specific example, in the innermost periphery201, the straight line portions201a,201band the curved line portions201c,201dmay be physically separated from each other and electrically connected to each other via wiring or the like.

Although the embodiments and modifications of the present disclosure have been described above, the present disclosure can be implemented in still other forms.

In the above-described embodiment and modification, an example in which the LOCOS film is formed above the semiconductor layer has been described. However, STI (Shallow Trench Isolation) may be formed below the LOCOS film. The STI includes a trench formed by digging down a semiconductor layer and an insulator (silicon oxide, silicon nitride, or the like) buried in the trench.

In the above-described embodiment and modification, a configuration of which the conductivity types of various semiconductor regions are inverted may be adopted. That is, a p-type portion may be an n-type one, and an n-type portion may be a p-type one.

In the above-described embodiment and modification, the semiconductor device100can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source of, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, and the like. In addition, the semiconductor device100can be also applied to a power module used in an inverter circuit of a solar battery, a wind power generator, another power generation device, or the like. Alternatively, the semiconductor device100can be applied to a circuit module constituting an analog control power supply, a digital control power supply, or the like.

Although the embodiments and modification according to one aspect of the present disclosure have been described in detail, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

Hereinafter, characteristic examples extracted from the description of the specification and the drawings will be described.[A1]
A semiconductor device comprising:a semiconductor substrate having a first conductivity type;a semiconductor layer located above the semiconductor substrate, the semiconductor layer having a second conductivity type;a drain region located in the semiconductor layer, the drain region having the second conductivity type;a source/gate region including a source region having the second conductivity type and a gate region electrically connected to the source region, the gate region having the first conductivity type, the source/gate region being spaced from the drain region and located around the drain region;an insulating layer located above the semiconductor layer and between the drain region and the source/gate region; anda field plate located above the insulating layer, the field plate forming a current path,wherein the field plate includes an innermost periphery electrically connected to the drain region, an outermost periphery electrically connected to a ground, a first straight line portion and a second straight line portion located between the innermost periphery and the outermost periphery and adjacent to each other in a first direction in a plan view, and a first connection portion connecting the first straight line portion and the second straight line portion,wherein each of the innermost periphery, the outermost periphery, the first straight line portion, the second straight line portion and the first connection portion is a part of the current path,wherein each of the first straight line portion and the second straight line portion extends in a second direction intersecting with the first direction in a plan view, and
wherein the first connection portion extends in the first direction.[A2] The semiconductor device according to [A1], each of the innermost periphery, the outermost periphery, the first straight line portion and the second straight line portion is disposed on a virtual concentric ellipse centered on the drain region.[A3] The semiconductor device according to [A2], wherein the field plate further includes a first curved line portion and a second curved line portion adjacent to each other in the second direction, the first curved line portion and the second curved line portion being spaced apart from the innermost periphery, the outermost periphery, the first straight line portion and the second straight line portion,wherein the first straight line portion and the first curved line portion are located on a first virtual ellipse included in the virtual concentric ellipse, and
wherein the second straight line portion and the second curved line portion are located on a second virtual ellipse included in the virtual concentric ellipse.[A4] The semiconductor device according to [A3], wherein each of a width of the first curved line portion and a width of the second curved line portion is larger as the first curved line portion and the second curved line portion are farther from the first straight line portion and the second straight line portion in the second direction.[A5] The semiconductor device according to [A3] or [A4], wherein the field plate further includes a third curved line portion and a fourth curved line portion adjacent to each other in the second direction, the third curved line portion and the fourth curved line portion being spaced apart from the innermost periphery, the outermost periphery, the first straight line portion, the second straight line portion and the first connection portion,wherein the third curved line portion and the fourth curved line portion are located opposite to the first curved line portion and the second curved line portion across the innermost periphery in the second direction,wherein the third curved line portion is located on the first virtual ellipse, andwherein the fourth curved line portion is located on the second virtual ellipse.[A6] The semiconductor device according to any one of [A1] to [A5], wherein the first connection portion is connected to one end of the first straight line portion in the second direction.[A7] The semiconductor device according to [A6], wherein the innermost periphery includes a third straight line portion adjacent to the first straight line portion in the first direction,wherein the field plate further includes a second connection portion connecting the first straight line portion and the third straight line portion, and
wherein the second connection portion is connected to the other end of the first straight line portion in the second direction.[A8] The semiconductor device according to any one of [A1] to [A7], wherein at least one of the innermost periphery and the outermost periphery has an oval shape in a plan view.[A9] The semiconductor device according to any one of [A1] to [A8], wherein at least one of the innermost periphery and the outermost periphery has a straight line portion and a curved line portion spaced apart from each other, andwherein the straight line portion and the curved line portion are electrically connected via a conductive member located above the field plate.[A10] The semiconductor device according to any one of [A1] to [A9], wherein the field plate includes polysilicon.[A11] The semiconductor device according to any one of [A1] to [A10], wherein the semiconductor layer further includes:a gate well region in contact with the gate region, the gate well region having the first conductivity type; anda source well region in contact with the source region, the source well region having the second conductivity type, and
wherein the source well region includes a projected portion projecting toward the drain region more than the gate well region.[A12] The semiconductor device according to [A11], wherein, in a plan view, the outermost periphery is located closer to the drain region than the projected portion.

REFERENCE SIGNS LIST