CHARGING CIRCUIT

The present disclosure provides a charging circuit capable of operating stably under a charging current of a wide range. A first transistor is connected between an input terminal and an output terminal. A current setting terminal is connected to an external current setting resistor. A second transistor is connected between the input terminal and the current setting terminal, and has a gate connected to a gate of the first transistor. A constant current feedback circuit feedback-controls a gate voltage of the first transistor in a manner that a voltage of the current setting terminal approaches a reference voltage. The constant current feedback circuit is configured in a manner that a phase compensation parameter is variable according to a current flowing through the first transistor.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention claims priority under 35 U.S.C. § 119 to Japanese Application, 2021-053976, filed on Mar. 26, 2021, the entire contents of which being incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a charging circuit of a secondary battery.

BACKGROUND

A battery driven device represented by a cellphone terminal, a smartphone, a tablet terminal, a laptop computer or a portable audio player includes a rechargeable secondary battery. The secondary battery can be charged by a charging circuit built in an electronic device or an external charger.

A charging circuit operates in a current constant (CC) mode when a battery voltage is low and charges the battery by a constant current, and operates in a constant voltage (CV) mode if the battery is almost fully charged so as to adjust the charging current such that the battery voltage approaches a target voltage of a fully charged state.

PRIOR ART DOCUMENT

Patent Publication

SUMMARY

Problems to be Solved by the Present Disclosure

A designer of an electronic device or a charger wishes to individually designate the amount of a charging current in the CC mode according to the type or model of a battery. In response to the requirement above, a charging circuit is configured to be capable of setting the amount of a charging current in the CC mode.

The charging circuit includes a feedback loop that maintains the amount of a charging current in the CC mode at a target amount, wherein the stability of the feedback loop is greatly affected by the target amount of the charging current. Thus, if a wide range can be set for the charging current, the stability (that is, a phase margin or a gain margin) needs to be ensured within the wider range of currents, resulting in design complications of the feedback loop.

The present disclosure is completed in view of the situation above. It is an illustrative object of one aspect of the present disclosure to provide a charging circuit capable of operating stably under a charging current of a wide range.

Technical Means for Solving the Problem

According to an aspect of the present disclosure, a charging circuit includes: an input terminal; an output terminal; a first transistor, connected between the input terminal and the output terminal; a current setting terminal, to which an external current setting resistor is connectable; a second transistor, connected between the input terminal and the current setting terminal, and having a gate connected to a gate of the first transistor; and a constant current feedback circuit, feedback-controlling a gate voltage of the first transistor in a manner that a voltage of the current setting terminal approaches a reference voltage. The constant current feedback circuit is configured in a manner that a phase compensation parameter is variable according to a current flowing through the first transistor.

Moreover, configurations obtained from any combination of the elements above, and configurations obtained from conversions between expressions of the elements in terms of methods, devices and systems of the present disclosure may also effectively serve as embodiments of the present disclosure.

Effects of the Present Disclosure

According to an aspect of the present disclosure, a charging circuit is capable of operating stably under a charging current of a wide range.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Summary of the Embodiments

A summary of several exemplary embodiments of the present disclosure is given below. The summary serves as the preamble of the detailed description to be given shortly, and aims to provide fundamental understanding of the embodiments by describing several concepts of one or more embodiments in brief. It should be noted that the summary is not to be construed as limitations to the scope of the present disclosure. Moreover, the summary does not necessarily encompass all embodiments that can be taken into account, and does not provide definitions for essential constituent elements of the embodiments. For the sake of better description, “one embodiment” sometimes refers to one embodiment (an implementation example or a variation example) or multiple embodiments (implementation examples or variation examples) disclosed in this specification.

The summary is not a general summary of all embodiments that can be taken into account, nor does it intend to specify important elements or specific important elements of all embodiments or to define the scope of a part of or all aspects. The preamble of the more detailed description below aims to solely present some concepts of one or more embodiments in a simplified form.

A charging circuit according to an embodiment includes: an input terminal; an output terminal; a first transistor, connected between the input terminal and the output terminal; a current setting terminal, to which an external current setting resistor is connectable; a second transistor, connected between the input terminal and the current setting terminal, and having a gate connected to a gate of the first transistor; and a constant current feedback circuit, feedback-controlling a gate voltage of the first transistor in a manner that a voltage of the current setting terminal approaches a reference voltage. The constant current feedback circuit is configured in a manner that a phase compensation parameter is variable according to a current flowing through the first transistor.

In a resistance value of the current setting resistor, a current proportional to the charging current flowing through the first transistor and the output terminal flows, and so a voltage of the current setting terminal, that is, a voltage drop Vs of the current setting resistor, is proportional to a charging current ICHGand a resistance value RICHGof the current setting resistor.

When the voltage VSis stabilized into a reference voltage VREFby the constant current feedback circuit, the charging current ICHGis stabilized to a target current ICHG(REF)below.

That is to say, the charging current ICHG can be set to be inversely proportional to the resistance value of the current setting resistor.

Herein, the current setting resistor and its peripheral parasitic capacitance together produce a pole. The position of the pole shifts according to the resistance value of the current setting resistor. According to the configuration above, the phase compensation parameter of the constant current feedback circuit is variable according to the current flowing through the first transistor, in other words, according to the resistance value of the current setting resistor, so that a phase margin and a gain margin can be ensured to ensure stability of a current of a wide range.

In one embodiment, the constant current feedback circuit may include: a third transistor, having a first end connected to the input terminal and a second end connected to the gate of the first transistor; a constant current load, connected between the second end of the third transistor and a ground; and a differential amplifier, receiving the voltage of the current setting terminal and the reference voltage, and having an output node connected to a control terminal of the third transistor. In the configuration above, a pole of a first stage of the differential amplifier is included in an emitter-grounded type or source-grounded type amplification stage including the third transistor and the constant current load, and a pole of a second stage is formed by the second transistor and the current setting resistor to form a pole of a third stage. The phase compensation parameter of the first stage or the second stage is dynamically variable according to shifting of the pole of the third stage, hence ensuring stability.

In one embodiment, the constant current feedback circuit may further include a first resistor and a first capacitor connected in series and between the control terminal of the third transistor and the second end. At least one of a resistance of the first resistor and a capacitance of the first capacitor is the phase compensation parameter, which is variable. In this case, the position of a zero point is shifted according to the position of the pole determined by the current setting resistor.

In one embodiment, the first resistor may also include a first resistor element, and a series transistor and a second resistor element connected in series and between both ends of the first resistor element. A state of the series transistor may change according to the current flowing through the first transistor.

In one embodiment, the constant current feedback circuit may further include: a third transistor, having a first end connected to the input terminal and a second end connected to the gate of the first transistor; a constant current load, connected between the second end of the third transistor and a ground; a differential amplifier, receiving the voltage of the current setting terminal and the reference voltage, and having an output node connected to a control terminal of the third transistor; a first resistor element and a first capacitor, connected in series and between the control terminal of the third transistor and the second end; a first P-type transistor and a second resistor element, connected in series and between both ends of the first resistor element; a fourth transistor, having a gate connected to the gate of the first transistor and a source connected to a source of the first transistor; a current mirror circuit, having an input node connected to the fourth transistor and an output node connected to the first P-type transistor; and an impedance circuit, connected between the input terminal and the output node of the current mirror circuit. Accordingly, the position of a zero point can be set according to the position of the pole determined by the current setting resistor.

In one embodiment, the impedance circuit may include a second P-type transistor in which a gate/drain is connected.

In one embodiment, the constant current feedback circuit may supply a current proportional to the current flowing through the first transistor to the control terminal of the third transistor. Accordingly, a mirror current gets larger as the charging current increases, that is, as the current setting resistor gets smaller, so that the gain can be reduced and the gain margin can be increased.

In one embodiment, a gain of the differential amplifier may also be the phase compensation parameter, which is variable. The position of the pole determined by the gain of the differential amplifier can be changed according to the position of the pole determined by the current setting resistor.

In one embodiment, the differential amplifier may include: a differential input stage, and an emitter-grounded type or source-grounded type amplification stage that amplifies an output of the differential input stage. The constant current feedback circuit may be configured in a manner that an output impedance of the amplification stage is variable according to the current flowing through the first transistor.

In one embodiment, a collector load or a drain load of the amplification stage may be variably configured. In one embodiment, an impedance of a grounded emitter transistor or a grounded source transistor of the amplification stage may be variably configured.

In one embodiment, the constant current feedback circuit may include a fourth transistor, which has a gate connected to the gate of the first transistor and a source connected to a source of the first transistor. The phase compensation parameter of the constant current feedback circuit may change according to a current of the fourth transistor. In the fourth transistor, a current corresponding to the charging current flowing through the first transistor flows, in other words, a current corresponding to the resistance value of the current setting resistor flows. Thus, the phase compensation parameter of the constant current feedback circuit can be appropriately controlled with reference to the current of the fourth transistor.

In one embodiment, the constant current feedback circuit may include a sense resistor connected in series with the first transistor. The phase compensation parameter of the constant current feedback circuit may change according to a voltage drop of the sense resistor.

In one embodiment, the charging circuit may further include a voltage balance circuit connected between the second transistor and the current setting terminal to bring a voltage at one end of the second transistor closer to a voltage of the output terminal. Accordingly, a drain-source voltage of the second transistor can approach a drain-source voltage of the first transistor, so that the charging current can be monitored with high precision.

In one embodiment, the charging circuit may further include a constant voltage feedback circuit that feedback-controls the gate voltage of the first transistor such that a voltage of the output terminal approaches a second reference voltage.

Embodiments

Details of appropriate embodiments are given with the accompanying drawings below. The same or equivalent constituting elements, parts and processes are represented by the same denotations, and repeated description is omitted as appropriate. Moreover, the embodiments are illustrative and are non-limiting to the present disclosure. All features and combinations thereof described in the embodiments are not necessarily intrinsic characteristics of the present disclosure.

In this specification, an expression “a state of component A connected to component B” includes a situation where component A and component B are directly connected, or a situation where component A is indirectly connected to component B via another component, and the indirect connection does not result in substantial influences on their electrical connection or does not impair functions or effects exerted by their connection.

Similarly, an expression “a state of component C disposed between component A and component B” or “a stage of component C connected between component A and component B” includes, in addition to a situation where component A and component C, or component B and component C are directly connected, an indirect connection via another component, and the indirect connection does not result in substantial influences on their electrical connection or does not impair functions or effects exerted by their connection.

FIG. 1shows a block diagram of an electronic device100including a charging circuit200according to an embodiment. The electronic device100includes a battery102and the charging circuit200. The battery102is a repeatedly rechargeable secondary battery, and is, for example, a lithium ion battery or lithium ion polymer battery, a nickel hydride battery or a nickel cadmium battery.

In the charging circuit200, an input terminal VIN receives a direct-current (DC) input voltage VIN, and an output terminal VOUT is connected to the battery102. The charging circuit200supplies a charging current ICHGto the battery102, and charges the battery102. The charging circuit200is an integrated circuit (IC) integrated on a semiconductor substrate.

The charging circuit200includes a charging current setting terminal (to be simply referred to as a current setting terminal below) ICHG. The current setting terminal ICHG is connected to an external current setting resistor RICHG. A charging current ICHGgenerated by the charging circuit200can be set according to a resistance value of the current setting resistor RICHG, wherein the resistance value of the current setting resistor RICHGis determined based on a standard of the battery102by a designer of the electronic device100. In other words, regardless of the resistance value of the resistor RICHGconnected to the current setting terminal ICHG, the charging circuit200is required to operate stably without any vibration. Moreover, in this specification, the term “terminal” may refer to a pin of an integrated circuit package, or may be an electrode of a die (chip) in an integrated circuit package.

In general, the charging circuit200can switch between a constant current (CC) mode and a constant voltage (CV) mode according to a voltage VBATof the battery102; however, a configuration associated with the CC mode is depicted inFIG. 1and a configuration associated with the CV mode is omitted.

The charging circuit200includes a first transistor M1, a second transistor M2and a constant current feedback circuit210. The first transistor M1is a P-channel metal oxide semiconductor field effect transistor (MOSFET), and is connected between the input terminal VIN and the output terminal VOUT. The first transistor M1may also be a PNP bipolar transistor. A current flowing through the first transistor M1is the charging current ICHG. When the charging circuit200is in the CC mode, the charging current ICHGis stabilized by means of adjusting a gate voltage VGof the first transistor M1to the target current ICHG(REF).

The second transistor M2is of the same type as the first transistor M1, and is connected between the input terminal VIN and the current setting terminal ICHG. A gate of the second transistor M2is connected to a gate of the first transistor M1. A current IM2proportional to the charging current ICHGflowing through the first transistor M1flows through the second transistor M2.

The coefficient A is determined according to sizes of the first transistor M1and the second transistor M2. For example, when a size ratio of the first transistor M1to the second transistor M2is 1000:1, A= 1/1000.

A voltage drop is produced if the current IM2flows through the current setting resistor RICHG. The voltage drop is reflected as a voltage signal VICHG_Sat the current setting terminal ICHG.

The voltage signal VICHG_Sis fed back to the constant current feedback circuit210. The constant current feedback circuit210feedback-controls the gate voltage VGof the first transistor M1in a manner that the voltage VICHG_Sof the current setting terminal approaches a reference voltage VREF(CC).

With the feedback of the constant current feedback circuit210, VREF(CC)=VICHG_Sis established, and thus the charging current ICHGis stabilized to the target current ICHG(REF)represented by an equation below.

That is to say, the set value ICHG(REF)of the charging current of the charging circuit200is inversely proportional to the resistance value of the current setting resistor RICHG.

The current setting resistor RICHGand its peripheral parasitic capacitance together produce a pole. In general, in a semiconductor chip, each terminal has an electrostatic discharge (ESD) protection element (a diode), but a parasitic capacitance Cp of the ESD protection element and the current setting resistor RICHGtogether form one factor producing a pole. When the charging current ICHGis variable within a range between 1 mA and 300 mA, the position (frequency) of a pole generates a change that is 300 times. If a fluctuation in a power supply voltage or a fluctuation in the temperature is further considered, the frequency of the pole may even change within a range (a range between 1 kHz and 1 MHz, for example) of 1000 times.

To ensure the stability of the feedback loop, a zero point is usually introduced by phase compensation. When the pole changes within a range of 1000 times, it may be too difficult to ensure the stability of a feedback loop by the same phase compensation.

Thus, adaptive phase compensation is introduced in this embodiment. More specifically, the constant current feedback circuit210is configured in a manner that a phase compensation parameter is adaptively variable according to the charging current ICHGflowing through the first transistor M1.

As described above, the charging current ICHGis set according to the current setting resistor RICHG, and thus the charging current ICHGflowing through the first transistor M1represents a size of the current setting resistor RICHG, in other words, representing the position of a pole. Thus, by configuring the phase compensation parameter of the constant current feedback circuit210to dynamically and adaptively change according to the charging current ICHG, the position of a zero point is changed according to the position of the pole, or a loop gain is changed according to the position of the pole, thereby ensuring a phase margin or a gain margin.

A specific example of a variable phase compensation parameter is to be described below, wherein the phase compensation parameter is exemplified by a circuit constant, an operating point or a modification of a circuit configuration that helps stabilizing the feedback loop.

The present disclosure can be conceivable based on the block diagram or circuit diagram inFIG. 1, or relates to various devices and methods that are derived from the description and are not limited to specific configurations. More specific configuration examples or embodiments are to be described below to help better understand the essentials or operations of the present disclosure and to clarify such essentials or operations rather than restraining the scope of the present disclosure.

FIG. 2shows a circuit diagram of a specific configuration example of the charging circuit200. The constant current feedback circuit210further includes a third transistor M3and a constant current load CS3.

The third transistor M3is a P-channel MOSFET, and has a first terminal (a source) connected to the input terminal VIN. The constant current load CS3is connected between a second end (a drain) of the third transistor M3and a ground. A connection node of the third transistor M3and the constant current load CS3is connected to the gate of the first transistor M1.

In a differential amplifier (error amplifier)212, a non-inverting input terminal (+) receives the reference voltage VREF(CC), and an inverting input terminal (−) receives the voltage of the current setting terminal ICHG. In this example, a sense terminal ICHG_Shaving a potential equal to that of the current setting terminal ICHG is provided, and a voltage VICHG_Sof the sense terminal ICHG_S is supplied to the inverting input terminal (−) of the differential amplifier212. An output of the differential amplifier212is connected to a control terminal (a gate) of the third transistor M3.

The charging circuit200may be regarded as a three-stage amplifier. That is, a first stage STG1is the differential amplifier212, a second stage STG2is a source-grounded type amplifier including the third transistor M3and the constant current load CS3, and a third stage is a source-grounded type amplifier including the second transistor M2and the current setting resistor RICHG. In the three-stage amplifier, a pole is introduced to each of the first stage, the second stage and the third stage. A phase compensation circuit214is disposed in the constant current feedback circuit210.

The phase compensation circuit214includes a first resistor R1and a first capacitor C1connected in series between the control terminal (the gate) and a second end (a drain) of the third transistor M3, in other words, between an input and an output of the second-stage amplification stage (M3and CS3).

A pole (a third pole) generated in the third stage is determined according to the current setting resistance RICHGand the parasitic capacitance Cp. The parasitic capacitance Cp may include parasitic capacitances of ESD protection elements202and204disposed at the terminal ICHG or the terminal ICHG_S.

FIG. 3shows a diagram illustrating adaptive phase compensation of the charging circuit200. InFIG. 3, a sign “x” represents poles of the first stage, the second stage and the third stage. The frequency of the third pole varies within a range between, for example, 1 kHz and 1 MHz, and the frequency of the third pole moves more toward the high frequency side as the resistance value of the current setting resistor RICHGgets smaller, that is, as the set value of the charging current ICHGgets larger.

InFIG. 3, a sign “O” represents a zero point introduced by the phase compensation circuit214. According to the size of the charging current ICHG, in other words, according to the current setting resistor RICHG, the circuit constant of the phase compensation circuit214is changed, so as to adaptively set the position of the zero point of the first stage according to the third pole.

When the charging current ICHGis variable within a range between 1 mA and 300 mA, the resistance value of the current setting resistor RICHGchanges by 300 times, and hence the position (frequency) of the third pole is also variable within a range of 300 times. If a fluctuation in a power supply voltage or a fluctuation in the temperature is further considered, the frequency of the third pole may even change within a range (a range between 1 kHz and 1 MHz, for example) of 1000 times.

In one embodiment, a resistance value of the first resistor R1may be used as a variable phase compensation parameter of the constant current feedback circuit210, and the first resistor R1may then be configured as a variable resistor having a resistance value that varies according to the charging current ICHG.

FIG. 4shows a circuit diagram of the charging circuit200according to an embodiment. In this embodiment, the resistance value of the first resistor R1of the phase compensation circuit214is adaptively controlled according to the charging current ICHG.

In addition to the third transistor M3, the phase compensation circuit214and the constant current load CS3, the constant current feedback circuit210further includes a fourth transistor M4, a current mirror circuit230and an impedance circuit232so as to implement adaptive phase compensation.

The fourth transistor M4has a gate connected to the gate of the first transistor M1and a source connected to a source of the first transistor M1. Thus, a current IM4proportional to the charging current ICHGflowing through the first transistor M1flows in the fourth transistor M4. The current mirror circuit230folds back the current IM4. The impedance circuit232is connected between the input terminal VIN and an output node of the current mirror circuit230, and generates a voltage drop ΔV corresponding to a current IM4′ folded back by the current mirror circuit230, and more specifically, a voltage drop Δ positively correlated with the current IM4′.

The first resistor R1is a variable resistor, and has its resistance value variable according to a voltage VN1=VIN−ΔV of a connection node of the impedance circuit232and the current mirror circuit230. More specifically, the resistance value of the first resistor R1is variable within a range between Rc2and Rc1according to the voltage VN1, where Rc2<R1<Rc1.

A switch SW1is inserted between the source of the first transistor M1and the input terminal VIN.

FIG. 4shows a constant voltage feedback circuit250used for the CV mode. A differential amplifier252, a fifth transistor M5, a phase compensation circuit254and a constant current load CS3together form the constant voltage feedback circuit250. A feedback voltage VFBcorresponding to an output voltage VOUT, that is, the voltage of the battery102, is input to a feedback terminal VFB. For example, the feedback voltage VFBis a voltage from dividing the voltage of the battery.

The differential amplifier252is an error amplifier that amplifies an error between the voltage VFBof the feedback terminal VFB and a target reference voltage VREF(CV)of the feedback terminal VFB, and has an output connected to a gate of the fifth transistor M5. In the CV mode, the charging current ICHGis controlled in a manner that the voltage VOUTof the battery approaches the target voltage VOUT(REF)determined according to the reference voltage VREF(CV).

In addition, the charging circuit200inFIG. 4is provided with a voltage balance circuit240. In the configuration inFIG. 2excluding the voltage balance circuit240, the drain voltage of the first transistor M1is the battery voltage of the output terminal VOUT, and on the other hand, the drain voltage of the second transistor M2becomes the voltage VICHGof the current setting terminal ICHG, that is, the reference voltage VREF(CC), and these two are different. Thus, the drain-source voltages of the first transistor M1and the second transistor M2become unbalanced, and a current ratio A between the first transistor M1and the second transistor M2changes. The change in the ratio A causes reduced precision of the charging current ICHG.

The voltage balance circuit240inFIG. 4causes the drain voltage of the second transistor M2to approach the drain voltage of the first transistor M1, so that the drain-source voltage of the first transistor M1and the drain-source voltage of the second transistor M2become equal, thereby stabilizing the current ratio A between first transistor M1and the second transistor M2. Accordingly, the charging current ICHGcan be controlled with high precision.

FIG. 5shows a circuit diagram of a specific configuration example of the charging circuit200inFIG. 4. The impedance circuit232includes, for example, a second P-type transistor234in which a gate/drain is connected. In this example, two P-type transistors234are shown; however, the number of such can be determined according to the voltage drop ΔV desired to be generated in the impedance circuit232. The impedance circuit232may also be implemented by a resistor; however, in this case, the temperature characteristics of the resistance value or non-uniformity of a process may affect the position of the zero point. In contrast, when the impedance circuit232is implemented by a P-type transistor, and more specifically, by a P-channel MOSFET, the characteristics of the P-type transistor234follow the characteristics of other P-type transistors, so that the position of the zero point can be stabilized.

In this configuration example, the first resistor R1includes a first resistor element R11, a second resistor element R12and a P-type transistor M11. The second resistor element R12and the P-type transistor M11are connected in series between both ends of the first resistor element R11. The voltage VN1is input to a gate of the P-type transistor M11.

When the charging current ICHGis small, in other words, when the current setting resistor RICHGis large, the current IM4flowing through the fourth transistor M4is decreased, and so the voltage drop ΔV of the P-type transistor234becomes smaller, and VN1≈VIN. In this case, the P-type transistor M11is turned off, and so the resistance value Rc1of the first resistor R1is equal to that of the first resistor element R11.

At this point in time, the zero point is located on a lowermost side of the frequency.

When the charging current ICHGis large, in other words, when the current setting resistor RICHGis small, the current IM4flowing through the fourth transistor M4is increased, and so the voltage drop ΔV of the P-type transistor234becomes larger. In this case, a gate-source voltage of the P-type transistor M11becomes larger and a fully turned on state is achieved, and so the resistance value Rc2of the first resistor R1becomes being connected in parallel with the first resistor element R11and the second resistor element R12, where “//” represents a combined resistance of the parallel resistances.

The decrease in the resistance value of the first resistor R1causes the zero point to shift to the high frequency side.

That is to say, according to the configuration inFIG. 5, the resistance value of the first resistor R1can be controlled to be within a range of Rc2<R1<Rc1to shift the zero point.

Herein, adaptive phase compensation performed using shifting of a zero point is described; however, other approaches may also be used.

FIG. 6shows a diagram illustrating adaptive phase compensation based on loop gain reduction. For the sake of simplicity, a Bode plot of a two-stage amplifier is shown in the drawing. The solid lines indicate gain characteristics and phase characteristics when a second pole ωP2is low, and the dotted lines indicate gain characteristics and phase characteristics when the second pole ωP2is high. Given that adaptive phase compensation is not performed, when the second pole ωP2is high, the phase rotates by 180° under a frequency of one single gain, and a vibration is resulted.

In contrast, in adaptive phase compensation based on loop gain reduction, as shown by the single-dash dotted line, the loop gain is reduced as the second pole ωP2becomes higher. Accordingly, reducing the frequency of one single gain can ensure a phase margin ϕM.

FIG. 7shows a circuit diagram of another configuration example of the charging circuit200. In this configuration example, the output of the current mirror circuit230is connected to the gate of the third transistor M3, and the current mirror circuit230sinks the current IM4′ proportional to the charging current ICHGfrom the gate of the third transistor M3.

FIG. 8shows a circuit diagram of a variation example of the charging circuit200inFIG. 7. In this variation example, a drain of the fourth transistor M4is connected to the gate of the third transistor M3, and pulls the current IM4′ proportional to the charging current ICHGto the gate of the third transistor M3.

According to the configuration inFIG. 7orFIG. 8, the gain of the second stage is changed according to the charging current ICHG, further changing the loop gain.

FIG. 9shows a diagram of another configuration example of the charging circuit200. In the configuration examples inFIG. 4,FIG. 5,FIG. 7andFIG. 8, the charging current ICHGof the first transistor M1is duplicated by the fourth transistor M4, and adaptive phase compensation is performed based on the duplicated current IM4; however, the present disclosure is not limited to the examples above. In the charging circuit200inFIG. 9, a sense resistor Rs connected in series with the first transistor M1is inserted, and adaptive phase compensation is implemented based on a voltage drop Vcs of the sense resistor Rs.

In this configuration example, similar to the configuration example inFIG. 5, the resistance value of the first resistor R1is adaptively changed according to the voltage drop of the sense resistor Rs, in other words, according to the charging current ICHG.

An amplifier260includes resistors R21and R22, a transistor M22, and a differential amplifier (an error amplifier)262. When a virtual short in the differential amplifier262is established, a voltage drop RS×ICHGof the resistor Rs is equal to a voltage drop R21×Ia of the resistor R21. That is to say, a current Ia flowing through the resistor R21is proportional to the charging current ICHG.

The current Ia flows through the transistor M22and the resistor R22. Thus, an output voltage Va of the amplifier260is represented by an equation below, and is proportional to the charging current ICHG.

The resistance value of the first resistor R1of the phase compensation circuit214can be controlled according to the voltage Va. Accordingly, the position of the pole can be adaptively shifted.

FIG. 10shows a circuit diagram of yet another configuration example of the charging circuit200. The differential amplifier212of the constant current feedback circuit210includes a differential input stage216and an amplification stage218. The differential input stage216receives the voltage signal VICHG_Sof the current setting terminal ICHGand the reference voltage VREF(CC). The amplification stage218is an emitter-grounded type (or source-grounded type) amplification stage that amplifies a differential output signal of the front-stage amplification stage218.

The constant current feedback circuit210may also be configured in a manner that an output impedance of the amplification stage218is variable according to the current ICHGflowing through the first transistor M1. The emitter-grounded type amplification stage218includes an emitter-grounded transistor pair Q41and Q42, and a collector load219connected to collectors thereof. In this configuration example, an impedance (collector impedance) of the collector load219of the amplification stage218is variable.

The collector load219includes transistors M41to M43forming a current mirror circuit, and a variable resistor R41. The fourth transistor M4and the impedance circuit232are disposed in order to the control a resistance value of the variable resistor R41. The current IM4proportional to the charging current ICHGflowing through the first transistor M1flows in the fourth transistor M4, and the voltage drop ΔV proportional to the current IM4, that is, proportional to the charging current ICHG, is generated in the impedance circuit232. The resistance value of the variable resistor R41varies according to the voltage drop ΔV.

The collector load of the transistor Q42is a combined resistance of the transistors M42and M43and the variable resistor R41. Thus, with the resistance value of the variable resistor R41that varies according to the charging current ICHG, the impedance of one collector of the differential output of the amplification stage218is changed, so that the output impedance of the amplification stage218is varied.

That is to say, given a small set value of the charging current, when the resistance value RICHGof the current setting resistor is large, the resistance value of the variable resistor R41is increased as the set value of the charging current increases, that is, as the resistance value RICHGof the current setting resistor gets smaller, the resistance value of the variable resistor R41is decreased. That is to say, as the charging current ICHGincreases, the output impedance of the amplification stage218is increased, and the pole of the differential amplifier212shifts to the low band side. Accordingly, stability can be ensured.

FIG. 11shows a circuit diagram of a further configuration example of the charging circuit200. The differential amplifier212of the constant current feedback circuit210includes a differential input stage216and an amplification stage218. The differential input stage216receives the voltage signal VICHG_Sof the current setting terminal ICHGand the reference voltage VREF(CC). The amplification stage218is an emitter-grounded type (or source-grounded type) amplification stage that amplifies a differential output signal of the front-stage amplification stage218.

Similar toFIG. 10, the emitter-grounded type amplification stage218includes an emitter-grounded transistor pair Q41and Q42, and a collector load219connected to collectors thereof, and the constant current feedback circuit210is configured in a manner that the output impedance of the amplification stage218is variable according to the current ICHGflowing through the first transistor M1.

InFIG. 11, an impedance (in other words, a transconductance) of the emitter-grounded transistor Q42is variable according to the current ICHGflowing through the first transistor M1. The output impedance of the amplification stage218is a combined resistance of the impedance of the transistor Q42and the collector impedance, and thus the output impedance of the amplification stage218is caused to vary according to an impedance change of the transistor Q42.

The emitter-grounded transistor Q42includes transistors Q42aand Q42b,and a variable resistor R42. If the resistance value of the variable resistor R42is varied, a transconductance gm, in other words, an impedance of the emitter-grounded transistor Q42then varies.

The fourth transistor M4, the current mirror circuit230and the impedance circuit232are disposed in order to the control a resistance value of the variable resistor R42. The fourth transistor M4, the current mirror circuit230and the impedance circuit232operate similarly to those ofFIG. 4.

According to the charging circuit200inFIG. 11, as the charging current ICHGincreases, an impedance of the transistor Q42is increased, that is, the output impedance of the amplification stage218is increased, and the pole of the differential amplifier212shifts to the low band side. Accordingly, stability can be ensured.

FIG. 12shows a diagram of a configuration example of the charging circuit200. The configuration of adaptive phase compensation is omitted fromFIG. 12.

A CC/CV stabilization circuit270includes the third transistor M3, the constant current load CS3, the fifth transistor M5or the phase compensation circuits214and254inFIG. 4, and controls the gate voltage of the first transistor M1according to the output of the differential amplifier212or the output of the differential amplifier252.

A controller280comprehensively controls the entire charging circuit200. A reference voltage source296includes, for example, a bandgap reference circuit, and generates a reference voltage for reference of the blocks of the charging circuit200.

A sixth transistor M6has a gate connected to the gate of the first transistor M1and a source connected to a source of the first transistor M1. A current IM6proportional to the charging current ICHGflows through the sixth transistor M6. The current IM6flows through a resistor RITEMconnected to a terminal current setting terminal ITEM. A voltage VITEMproportional to the charging current ICHGis generated in the terminal current setting terminal ITEM. The voltage VITEMis input through a buffer284to a comparator286. The comparator286compares the voltage VITEMwith the threshold voltage VTH, and determines whether the charging current ICHGhas decreased to a terminal current ITERM. If the comparator286detects that the charging current ICHGhas decreased to the terminal current ITERM, the controller280stops the charging operation.

An overvoltage comparator282compares the voltage VFBof the feedback terminal VFB with the threshold voltage, and detects an overvoltage state. If an overvoltage state is detected, the controller280stops the charging operation.

If a voltage of recharging detection terminal VFBRE is lower than the threshold voltage, a recharging detection comparator288then generates a trigger for starting recharging. Once the trigger for starting recharging is received after the charging operation is complete, the controller280activates the CC/CV stabilization circuit270to start recharging.

An oscillator292oscillates at a predetermined frequency to generate a clock signal CLK. The controller280operates in synchronization with the clock signal CLK. For example, the controller280may include a timer281.

A UVLO/TSD circuit294generates a trigger for undervoltage lockout according to the input voltage VIN, and further generates a trigger for thermal shutdown protection according to the temperature.

A terminal NTC is connected to a thermistor104disposed close to the battery102. A comparator group290compares a voltage of the terminal NTC with different threshold voltages, and determines a temperature status of the battery102. The controller280can switch an operating state of the charging circuit200according to an output of the comparator group290.

A terminal LEDCNT is connected to an external light emitting diode (LED)106. The controller280controls light-on and light-off of the LED106by controlling on and off of the transistor M21.

The switch SW1includes transistors M31and M32. The controller280switches on and off of the transistor M31by controlling a gate voltage of the transistor M32.

The transistor M22is connected to a pin VFBG, and is controlled by the controller280. When the transistor M22is on, a voltage from dividing the output voltage VOUTis input to the terminal VFB and the terminal VFBRE, and when the transistor M22is off, the output voltage VOUTis directly input to the terminal VFB and the terminal VFBRE.

Variation Examples

The embodiments are described as above. A person skilled in the art should understand that, the embodiments are exemplary, and variation examples may be accomplished by combinations of the constituting elements and processes, and such variation examples are encompassed within the scope of the present disclosure. Details of such variation examples are given in the description below.

In the embodiment, the resistance value of the resistor R1of the phase compensation circuit214is set to be variable; however, the capacitance of the first capacitor C1may also be selected as a variable phase compensation parameter of the constant current feedback circuit210. The first capacitor C1is configured as a variable capacitor having a capacitance that varies according to the charging current ICHG.

Alternatively, the first resistor R1may be set as a variable resistor, the first capacitor C1may be set as a variable capacitor, so that both are variable according to the charging current ICHG.

InFIG. 7andFIG. 8, the gain of the second stage STG2is changed; however, the present disclosure is not limited to such example. Alternatively, the gain of the differential amplifier212of the first stage STG1may also be variable according to the charging current ICHG.

Moreover, when the adaptive gain control illustrated with reference toFIG. 6toFIG. 8is performed, the gain may be controlled according to the voltage drop Vs of the sense resistor Rs instead of the current flowing through the fourth transistor M4.

The transistors represented by P-channel MOSFETs and N-channel MOSFETs in the description may be replaced by PNP bipolar transistors and NPN bipolar transistors, and in this case, the gate, source and drain are respectively renamed as the base, emitter and collector.

The embodiments described in specific terms are for conveying principles and applications of the present disclosure, and variations and modifications to the configurations may be made to these embodiments without departing from the conceptive scope of the present disclosure defined in the appended claims.