Semiconductor wafer, semiconductor device, method for manufacturing the semiconductor device, circuit board, and electronic apparatus

A semiconductor wafer includes a semiconductor substrate having a plurality of integrated circuits and electrical interconnections electrically connected to each of the integrated circuits. The semiconductor substrate includes bonding pads formed on a surface of the semiconductor substrate. Each of the bonding pads is part of a corresponding electrical interconnection. First resin layers are each disposed on each of a plurality of areas on the semiconductor substrate and have ridged edges. Wirings are each disposed over a corresponding bonding pad and a corresponding first resin layer and are electrically connected to the corresponding bonding pad. External connection terminals are each disposed on a corresponding wiring and are electrically connected to the corresponding wiring.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor wafer, a semiconductor device, a method for manufacturing the semiconductor device, a circuit board, and an electronic apparatus.

2. Description of the Related Art

Bare chip mounting is preferable for high density mounting in semiconductor devices. However, quality control and handling of bare chips are difficult. For this reason, a semiconductor device to which the chip size/scale package (CSP) technology is applied has been developed. Particularly, in recent years, the wafer level CSP has received attention. In the wafer level CSP, wirings are formed on a first resin layer, the entire wafer is packaged, and then the wafer is cut into separated packages. In the CSP, the external connection terminals (for example, solder balls) and wirings can be formed on only restricted areas.

Accordingly, an advantage of the present invention is to provide increased areas for forming the external connection terminals or the wirings.

SUMMARY OF THE INVENTION

A semiconductor wafer according to an embodiment of the present invention includes a semiconductor substrate having a plurality of integrated circuits and electrical interconnections electrically connected to each of the integrated circuits. The semiconductor substrate includes bonding pads formed on a surface of the semiconductor substrate with each of the bonding pads being part of the corresponding electrical interconnections. First resin layers are each disposed on each of a plurality of areas on the semiconductor substrate and have ridged edges. Wirings are each disposed over the corresponding bonding pads and the corresponding first resin layer and are electrically connected to the corresponding bonding pad. External connection terminals are each disposed on the corresponding wiring and electrically connected to the corresponding wiring. According to an embodiment of the present invention, the first resin layer has ridged edges in which the surface area of each of the ridged edges is wider than the projected area thereof Thus, areas for forming the external connection terminals or the wirings increase on the first resin layer.

In this semiconductor wafer, each of the wirings may extend over the corresponding ridged edge and at least part of each of the external connection terminals may be disposed above the corresponding ridged edge.

A semiconductor device according to an embodiment of the present invention includes a semiconductor chip having an integrated circuit and electrical interconnections electrically connected to the integrated circuit. The semiconductor chip includes bonding pads formed on a surface of the semiconductor chip. Each of the bonding pads are part of the corresponding electrical interconnection. A first resin layer is disposed on the semiconductor chip and has ridged edges. Wirings are each disposed over the corresponding pad and the first resin layer and are electrically connected to the corresponding bonding pad. External connection terminals are each disposed on the corresponding wirings and electrically connected to the corresponding wiring. According to an embodiment of the present invention, the first resin layer has ridged edges. The surface area of each of the ridged edges is wider than the projected area of each of the same ridged edges. Thus, areas for forming the external connection terminals or the wirings increase.

According to an embodiment of the present invention, in the semiconductor device, each of the wirings extends over the corresponding ridged edge and at least part of each of the external connection terminals may be disposed above the corresponding ridged edge.

A circuit board according to an embodiment of the present invention includes the semiconductor device mounted on the circuit board. An electronic apparatus according to an embodiment of the present invention includes the semiconductor device.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes forming a resin precursor layer on a semiconductor substrate having an integrated circuit and electrical interconnections electrically connected to the integrated circuit. The semiconductor substrate includes bonding pads formed on a surface of the semiconductor substrate with each of the bonding pads being part of the corresponding electrical interconnection. The method also includes forming a first resin layer having ridged edges with the first resin layer being formed by curing shrinkage andforming wiring with each of the wirings being disposed over the corresponding bonding pad and the corresponding first resin layer and being electrically connected to the corresponding bonding pad. The method further includes forming external connection terminals with each of the external connection terminals being disposed on the corresponding wiring and being electrically connected to the corresponding wiring. According to the present invention, the first resin layer has ridged edges in which the surface area of each of the ridged edges is wider than the projected area of the corresponding ridged edge. Thus, areas for forming the external connection terminals or the wirings increase.

In the method for manufacturing the semiconductor device according to an embodiment of the present invention, each of the wirings may extend over the corresponding ridged edge.

Also, in the method for manufacturing the semiconductor device according to an embodiment of the present invention, at least part of each of the external connection terminals may be formed above the corresponding ridged edge.

Finally, in the method for manufacturing the semiconductor device according to an embodiment of the present invention, the resin precursor layer may be subjected to curing shrinkage by heating.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 to 5illustrate a method for manufacturing the semiconductor device according to the present invention. In this embodiment, a semiconductor substrate10is used. The semiconductor substrate10includes a plurality of integrated circuits12. When the semiconductor substrate10is cut into a plurality of separate semiconductor chips, the separated semiconductor chips have the respective integrated circuits12.

A passivation layer14may be formed on a surface of the semiconductor substrate10. For example, the passivation layer14may be formed of an inorganic material such as silicon dioxide (SiO2) or silicon nitride (SiN). The passivation layer14may include a plurality of sublayers. In this case, at least one sublayer (for example, the uppermost sublayer) may be formed of an organic material.

The bonding pads16are formed on the semiconductor substrate10. Each of the bonding pads16is part of, for example, an edge of the corresponding electrical interconnection electrically connected to the integrated circuits12(for example, semiconductor integrated circuits). The passivation layer14is not disposed on at least the middle area of each of the bonding pads16.

As shown inFIG. 1, resin precursor layers20are formed on the semiconductor substrate10. The resin precursor layers20may be formed on the semiconductor substrate10by applying or spin-coating a resin precursor, for example, a thermosetting resin precursor. In this embodiment, the resin precursor layers20are uncured. Each of the resin precursor layers20may include a plurality of sublayers or a single layer. The resin precursor layers20are electrical insulators. After the resin precursor layers20are cured (polymerized), the cured first resin layers may have a stress relieving function. The resin precursor layers20may be formed of a resin precursor, for example, a polyimide resin, a silicone modified polyimide resin, an epoxy resin, a silicone modified epoxy resin, benzocyclobutene (BCB), or polybenzoxazole (PBO). The resin precursor layers20cannot contain electrically conductive particles. The resin precursor layers20may be formed of a light shielding material.

The resin precursor layers20may be formed of a radiation-sensitive resin precursor that is sensitive to radiation such as light (ultraviolet light and visible light), X-rays, and an electron beam. The radiation-sensitive resin precursor such as a photosensitive resin precursor includes a negative type in which a radiation exposed area of the resin precursor becomes insoluble and a positive type in which a radiation exposed area of the resin precursor has increased solubility.

Each of the resin precursor layers20may not be disposed on the corresponding bonding pad16. The resin precursor layers20may not be disposed on areas for cutting the semiconductor substrate10. The resin precursor layers20may be patterned after the resin precursor layer and the resin precursor layer is continuously or integrally formed with the semiconductor substrate10.FIG. 2illustrates the patterned resin-precursor-layer.FIG. 1is a cross-sectional view taken along the line I—I inFIG. 2. As shown inFIG. 2, each of the resin precursor layers20may be formed on each of a plurality of areas on the semiconductor substrate10. Spaces are provided between adjacent resin precursor layers20. Side faces22of the resin precursor layers20may be perpendicular to the surface of the semiconductor substrate10. Top faces24of the resin precursor layers20may be flat, for example, parallel to the surface of the semiconductor substrate10.

As shown inFIG. 3, first resin layers26are formed by curing shrinkage of the resin precursor layers20. When the resin precursor layers20are composed of a thermosetting resin precursor, the resin precursor layers20are subjected to curing shrinkage by heating. The first resin layers26may have inclined side faces28inwardly relative to the side faces22of the resin precursor layers20. Alternatively, the first resin layers26may have the inwardly inclined side faces28formed by curing shrinkage of the side faces22, which are perpendicular to the surface of the semiconductor substrate10, of the resin precursor layers20. Top faces30of the first resin layers26may be flat, for example, parallel to the surface of the semiconductor substrate10. Each of the top faces30of the first resin layers26may also be inclined from the edge to the direction of the middle area on the surface of a corresponding first resin layer26.

Each of the first resin layers26has ridged edges32. The ridged edges32may be formed by curing shrinkage of the resin precursor layers20. The surface area of each of the ridged edges32is wider than the projected area of the same corresponding ridged edge. The actual surface area of each of the top faces30, which includes ridged edges32, of the first resin layers26is wider than the projected area of the same corresponding ridged edge. Thus, areas for forming the external connection terminals44or the wirings40increase on the first resin layer26.

As shown inFIG. 4, the wirings40are formed on the first resin layers26. The wirings40may be formed of a single layer or a plurality of sublayers. For example, a titanium tungsten (TiW) layer and a copper (Cu) layer are laminated by sputtering, and then a Cu layer may be further formed on the laminated layers. A known art can be applied for forming the composite. Each of the wirings40is formed so as to extend on the corresponding bonding pad16, in other words, to be electrically connected to the corresponding bonding pad16. Each of the wirings40extends over the corresponding bonding pad16and the corresponding first resin layer26. Each of the wirings40may extend over the corresponding side face28of the first resin layer26. Each of the wirings40is formed so as to extend over the corresponding ridged edge32. Since the wirings40are bent on the ridged edges32, the wirings barely break even if the resin precursor layers20deform. Each of the wirings40may be formed so as to have a land which has a wider width than that of the wirings. The land is an area to provide each of the external connection terminals44on the corresponding land.

Each of second resin layers42may be formed on the corresponding first resin layer26. The descriptions of the first resin layers26may also be applicable to the second resin layers42. Alternatively, the second resin layers42may be solder resists. Each of the second resin layers42may be formed so as to cover the entire or the part (for example, an area except for the middle area of the land) of the corresponding wiring40. The second resin layers42may be formed so as to expose areas for cutting the semiconductor substrate10.

The external connection terminals44are formed. At least part of each of the external connection terminals44may be disposed above the corresponding ridged edge32, for example, above the top faces of the corresponding ridged edge. The external connection terminals44may be composed of either soft solder or hard solder. Lead-free solder may be used for the soft solder. The lead-free solder such as tin-silver (Sn—Ag), tin-bismuth (Sn—Bi), tin-zinc (Sn—Zn), and tin-copper (Sn—Cu) based alloys may be used. These alloys may further contain at least any one of silver, bismuth, zinc, and copper. A known method can be applied to form the external connection terminals44.

Third resin layers46may be formed on the respective second resin layers42. The descriptions of the first resin layers26are applicable to the third resin layers46. The third resin layers46may be formed so as to cover the respective second resin layers42. The third resin layers46may be formed so as to expose areas for cutting the semiconductor substrate10. Each of the third resin layers46may cover the side faces of the corresponding second resin layer42adjacent to the cutting areas of the semiconductor substrate. Each of the third resin layers46may cover the part (for example, the base area) of each of the external connection terminals44. The third resin layers46may be formed by patterning a solid resin layer that is formed so as to cover the entire semiconductor substrate10. Alternatively, the third resin layers46may be formed by a solid resin layer on the entire external connection terminals44and then by removing the solid resin layer at the top ends of the third resin layers46. The descriptions of patterning for the resin precursor layer20are applicable to the patterning for forming the third resin layers. Alternatively, parts of the third resin layers46may be removed by laser irradiation or ashing.

The semiconductor wafer according to the present invention includes the semiconductor substrate10. The semiconductor substrate10includes a plurality of the integrated circuits12(seeFIG. 1) and the bonding pads16on a surface of the semiconductor substrate. Each of the bonding pads16is part of each of the electrical interconnections electrically connected to the corresponding integrated circuit12. Each of the first resin layers26having ridged edges is formed on each of the plurality of areas on the semiconductor substrate10. Each of the wirings40is disposed over the corresponding bonding pad16and the corresponding first resin layer26and is formed so as to be electrically connected to the corresponding bonding pad16. Each of the external connection terminals44is formed on the corresponding wiring40and is formed so as to be electrically connected to the corresponding wiring40. Other details are the same as described above. According to this embodiment, the first resin layer26has ridged edges32in which the surface area of each of the ridged edges32is wider than the projected area of the same ridged edge. Thus, areas for forming the external connection terminals44or the wirings40increase.

As shown inFIG. 5, the semiconductor substrate10may be cut by, for example, scribing or dicing. The first, second, and third resin layers26,42, and46are formed so as not to be formed on the cutting areas of the semiconductor substrate10. Thus, these resin layers are not cut; hence, clogging of a cutter (or a blade)48can be prevented. In this way, the semiconductor device can be obtained.

FIG. 6illustrates the semiconductor device according to this embodiment, andFIG. 7is a cross-sectional view taken along the line VII—VII inFIG. 6. The semiconductor device includes a semiconductor chip50. The semiconductor chip50includes the integrated circuit12(seeFIG. 1) and the bonding pads16on the surface of the semiconductor chip. Each of the bonding pads16is part of each of the electrical interconnections electrically connected to the integrated circuit12. The first resin layer26having the ridged edges is formed on the semiconductor chip50. Each of the wirings40is disposed over the corresponding bonding pad16and the corresponding first resin layer26and is formed so as to be electrically connected to the corresponding bonding pad16. Each of the external connection terminals44is formed on the corresponding wiring40and is formed so as to be electrically connected to the corresponding wiring40. The semiconductor chip50may be cut from the semiconductor substrate10. Other details are the same as described above.

FIG. 8shows a circuit board1000mounting a semiconductor device1described in above-mentioned embodiment.FIG. 9shows a notebook personal computer2000andFIG. 10shows a cellular phone3000as an electronic apparatus including this semiconductor device.

The present invention is not limited to above-mentioned embodiments and can include a variety of modifications. For example, the present invention includes a structure which is substantially equivalent to the structure described in the embodiments. The substantially equivalent structure is, for example, a structure that has the same function, method, and result, or the same object and result. Further, the present invention includes a structure in which an extrinsic part of the structure described in the embodiments is replaced. Furthermore, the present invention includes a structure that has the same effect or can achieve the same object as the structure described in the embodiments. In addition, the present invention includes a structure that is added a known art to the structure described in the embodiments.