Resistance variable memory elements and methods of formation

A method and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics have at least one metal-containing layer and a silver layer disposed between glass layers. At least one of the glass layers is a chalcogenide glass, preferably having a GexSe100−x composition.

FIELD OF THE INVENTION

The invention relates to the field of random access memory (RAM) devices formed using a resistance variable material, and in particular to a resistance variable memory element formed using chalcogenide glass.

BACKGROUND OF THE INVENTION

A well known semiconductor component is semiconductor memory, such as a random access memory (RAM). RAM permits repeated read and write operations on memory elements. Typically, RAM devices are volatile, in that stored data is lost once the power source is disconnected or removed. Non-limiting examples of RAM devices include dynamic random access memory (DRAM), synchronized dynamic random access memory (SDRAM) and static random access memory (SRAM). In addition, DRAMS and SDRAMS also typically store data in capacitors which require periodic refreshing to maintain the stored data.

In recent years, the number and density of memory elements in memory devices have been increasing. Accordingly, the size of each element has been shrinking, which in the case of DRAMs also shortens the element's data holding time. Typically, a DRAM memory device relies on element capacity for data storage and receives a refresh command in a conventional standardized cycle, about every 100 milliseconds. However, with increasing element number and density, it is becoming more and more difficult to refresh all memory elements at least once within a refresh period. In addition, refresh operations consume power.

Resistance variable memory elements, which includes programmable conductor memory elements, have been investigated for suitability as semi-volatile and non-volatile random access memory elements. Kozicki et al. in U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; and 6,084,796, disclose a programmable conductor memory element including an insulating dielectric material formed of a chalcogenide glass disposed between two electrodes. A conductive material, such as silver, is incorporated into the dielectric material. The resistance of the dielectric material can be changed between high resistance and low resistance states. The programmable conductor memory is normally in a high resistance state when at rest. A write operation to a low resistance state is performed by applying a voltage potential across the two electrodes. The mechanism by which the resistance of the element is changed is not fully understood. In one theory suggested by Kozicki et al., the conductively-doped dielectric material undergoes a structural change at a certain applied voltage with the growth of a conductive dendrite or filament between the electrodes effectively interconnecting the two electrodes and setting the memory element in a low resistance state. The dendrite is thought to grow through the resistance variable material in a path of least resistance.

The low resistance state will remain intact for days or weeks after the voltage potentials are removed. Such material can be returned to its high resistance state by applying a reverse voltage potential between the electrodes of at least the same order of magnitude as used to write the element to the low resistance state. Again, the highly resistive state is maintained once the voltage potential is removed. This way, such a device can function, for example, as a resistance variable memory element having two resistance states, which can define two logic states.

One preferred resistance variable material comprises a chalcogenide glass. A specific example is germanium-selenide (GexSe100−x) comprising silver (Ag). One method of providing silver to the germanium-selenide composition is to initially form a germanium-selenide glass and then deposit a thin layer of silver upon the glass, for example by sputtering, physical vapor deposition, or other known techniques in the art. The layer of silver can be irradiated, preferably with electromagnetic energy at a wavelength less than 600 nanometers, so that the energy passes through the silver and to the silver/glass interface, to break a chalcogenide bond of the chalcogenide material such that the glass is doped or photodoped with silver. Silver may also be provided to the glass by processing the glass with silver, as in the case of a silver-germanium-selenide glass. Another method for providing metal to the glass is to provide a layer of silver-selenide on a germanium-selenide glass.

In accordance with the current methods of incorporating silver into the glass, the degree and nature of the crystallinity of the chalcogenide material of the memory element has a direct bearing upon its programming characteristics. Accordingly, current processes for incorporating silver require the precise control of the amounts of GexSe100−xglass and silver, so as not to incorrectly dope the glass and improperly alter the crystallinity of the chalcogenide material. Current processes also require careful selection of the exact stoichiometry of the glass to ensure that silver is incorporated into the glass while the glass backbone remains in the glass forming region.

Furthermore, during semiconductor processing and/or packaging of a fabricated original structure that incorporates the memory element, the element undergoes thermal cycling or heat processing. Heat processing can result in substantial amounts of silver migrating into the memory element uncontrollably. Excessive silver incorporated into the memory element may result in faster degradation, i.e., a short life, and eventually, device failure.

U.S. application Ser. No. 10/120,521, the entire disclosure of which is incorporated herein by reference, describes a resistance variable memory element and a method of forming the resistance variable memory element. The resistance variable memory element includes a metal-containing layer formed between a first chalcogenide glass layer and a second glass layer. The resistance variable memory element provides improved memory retention and switching characteristics.

There remains a need, however, for a resistance variable memory element that is faster, is more temperature resilient, and has better cycling endurance.

BRIEF SUMMARY OF THE INVENTION

In a first embodiment, the invention provides a resistance variable memory element and a method of forming the resistance variable memory element. The resistance variable memory element includes a metal-containing layer and a silver layer formed between a first chalcogenide glass layer and a second glass layer. One or both of the glass layers may be doped with a metal, and one or more metal-containing layers may be provided between the glass layers.

In a narrower aspect of the first embodiment, the invention provides a memory element and a method of forming the memory element in which at least one layer of silver-selenide and a layer of silver are formed between a first chalcogenide glass layer and a second glass layer. The second glass layer may also be a chalcogenide glass layer. The stack of layers comprising a first chalcogenide glass, a silver-selenide layer, a silver layer, and a second glass layer are formed between two conductive layers or electrodes.

In a variation of the first embodiment of the invention, a stack of layers may contain more than one metal-containing layer, and a silver layer, between a chalcogenide glass layer and a second glass layer. In another variation of the first embodiment, a first chalcogenide glass layer may contain multiple chalcogenide glass layers, and a second glass layer may contain multiple glass layers. Thus the stack of layers may contain one or more metal-containing layers in serial contact with each other, and a silver layer, formed between a multi-layered chalcogenide glass layer and a multi-layered second glass layer. In yet another variation of the first embodiment, one or more of each of the first chalcogenide glass layers and the second glass layers may contain a metal dopant, such as, for example, a silver dopant.

According to a second embodiment, the invention provides a memory element and a method of forming a memory element comprising a plurality of alternating layers of chalcogenide glass layers, metal-containing layers, and silver layers, whereby the layers start with a first chalcogenide glass layer and end with a last chalcogenide glass layer, with the first chalcogenide glass layer contacting a first electrode and the last chalcogenide glass layer contacting a second electrode. Thus, the plurality of alternating layers of chalcogenide glass layers, metal-containing layers, and silver layers are stacked between two electrodes. The metal-containing layers preferably comprise a silver-chalcogenide, such as silver-selenide. In a variation of the second embodiment, the metal-containing layers may each contain a plurality of metal-containing layers. In another variation of the second embodiment, the chalcogenide glass layers may each contain a plurality of chalcogenide glass layers. In yet another variation of this embodiment, one or more of the chalcogenide glass layers may contain a metal dopant, such as, for example, a silver dopant.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to various specific embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical, and electrical changes may be made without departing from the spirit or scope of the invention.

The term “substrate” as used in the following description may include any supporting structure including but not limited to a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation.

The term “silver” is intended to include not only elemental silver, but silver with other trace metals or in various alloyed combinations with other metals as is known in the semiconductor industry, as long as such silver alloy is conductive, and as long as the physical and electrical properties of the silver remain unchanged.

The term “silver-selenide” is intended to include various species of silver-selenide, including some species which have a slight excess or deficit of silver, for instance, Ag2Se, Ag2+xSe, and Ag2−xSe.

The term “semi-volatile memory” is intended to include any memory device or element which is capable of maintaining its memory state after power is removed from the device for a prolonged period of time. Thus, semi-volatile memory devices are capable of retaining stored data after the power source is disconnected or removed. Accordingly, the term “semi-volatile memory” is also intended to include not only semi-volatile memory devices, but also non-volatile memory devices.

The term “resistance variable material” is intended to include chalcogenide glasses, and chalcogenide glasses comprising a metal, such as silver. For instance, the term “resistance variable material” includes silver doped chalcogenide glasses, silver-germanium-selenide glasses, and chalcogenide glass comprising a silver selenide layer.

The term “resistance variable memory element” is intended to include any memory element, including programmable conductor memory elements, semi-volatile memory elements, and non-volatile memory elements which exhibit a resistance change in response to an applied voltage.

The term “chalcogenide glass” is intended to include glasses that comprise an element from Group VIA (also known as Group 16) of the Periodic Table. Group VIA elements, also referred to as chalcogens, include oxygen (O), sulfur (S), selenium (Se), tellurium (Te), and polonium (Po).

As indicated above, U.S. application Ser. No. 10/120,521 describes a resistance variable memory element that includes a metal-containing layer formed between a first chalcogenide glass layer and a second glass layer. In the present invention, an additional layer, a layer of evaporated silver, is located adjacent to the metal-containing layer. As a result, the resistance variable memory element has fewer surface defects than a structure having only a metal-containing layer formed between a first chalcogenide glass layer and a second glass layer. In addition, by employing a method in which the layer of silver is evaporated, one can add the correct amount of silver directly to the metal-containing layer rather than trying to place the silver under the top electrode. As a result, devices are faster, more temperature resilient, and have better cycling endurance.

The invention will now be explained with reference toFIGS. 1–10, which illustrate exemplary embodiments of a resistance variable memory element100in accordance with the invention.FIG. 1depicts a portion of an insulating layer12formed over a semiconductor substrate10, for example, a silicon substrate. It should be understood that the resistance variable memory element can be formed on a variety of substrate materials and not just semiconductor substrates such as silicon. For example, the insulating layer12may be formed on a plastic substrate. The insulating layer12may be formed by any known deposition method, such as, for example, sputtering by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD). The insulating layer12may be formed of a conventional insulating oxide, such as silicon oxide (SiO2), a silicon nitride (Si3N4), or a low dielectric constant material, among many others.

A first electrode14is next formed over the insulating layer12, as also illustrated inFIG. 1. The first electrode14may comprise any suitable conductive material, such as, for example, tungsten, nickel, tantalum, aluminum, platinum, or silver, among many others. A first dielectric layer15is next formed over the first electrode14. The first dielectric layer15may comprise the same or different materials as those described above with reference to the insulating layer12.

Referring now toFIG. 2, an opening13extending to the first electrode14is formed in the first dielectric layer15. The opening13may be formed by known methods in the art, such as, for example, by a conventional patterning and etching process. A first chalcogenide glass layer17is next formed over the first dielectric layer15, to fill in the opening13, as shown inFIG. 3.

According to a first embodiment of the invention, the first chalcogenide glass layer17is a germanium-selenide glass having a GexSe100−xstoichiometry. The preferred stoichiometric range is between about Ge20Se80to about Ge43Se57and is more preferably about Ge40Se60. The first chalcogenide glass layer17preferably has a thickness of from about 100 Å to about 1000 Å, and more preferably has a thickness of about 150 Å.

The first chalcogenide glass layer serves as a glass backbone for allowing a metal-containing layer, such as a silver-selenide layer, to be directly deposited thereon. The use of a metal-containing layer, such as a silver-selenide layer, in contact with the chalcogenide glass layer makes it unnecessary to provide a metal (silver) doped chalcogenide glass, which would require photodoping of the substrate with ultraviolet radiation. However, it is possible to also metal (silver) dope the chalcogenide glass layer, which is in contact with the silver-selenide layer, as an optional variant.

The formation of the first chalcogenide glass layer17, having a stoichiometric composition in accordance with the invention may be accomplished by any suitable method. For example, evaporation, co-sputtering germanium and selenium in the appropriate ratios, sputtering using a germanium-selenide target having the desired stoichiometry, or chemical vapor deposition with stoichiometric amounts of GeH4and SeH2gases (or various compositions of these gases), which result in a germanium-selenide film of the desired stoichiometry are examples of methods which may be used to form the first chalcogenide glass layer17.

Referring now toFIG. 4, a first metal-containing layer18, preferably silver-selenide, is deposited over the first chalcogenide glass layer17. Although the first metal-containing layer18is preferably silver-selenide, any suitable metal-containing layer may be used. For example, other suitable metal-containing layers include silver-chalcogenide layers. Silver sulfide, silver oxide, and silver telluride are all suitable silver-chalcogenides that may be used. A variety of processes can be used to form the metal-containing layer18. For instance, physical vapor deposition techniques such as evaporative deposition and sputtering may be used. Other processes such as chemical vapor deposition, co-evaporation, or depositing a layer of selenium above a layer of silver to form silver-selenide can also be used.

The layers may be of any suitable thickness. The thickness of the layers depends upon the mechanism for switching. The thickness of the layers is such that the metal-containing layer18is thicker than the first chalcogenide glass layer17. The metal-containing layer18is also thicker than a second glass layer20(the second glass layer20is described below). More preferably, the thickness of the layers is such that a ratio of the metal-containing layer18thickness to the first chalcogenide glass layer17thickness is between about 5:1 and about 1:1. That is, the thickness of the metal-containing layer is from about 1 to about 5 times greater than the thickness of the first chalcogenide glass layer. Even more preferably, the ratio of the metal-containing layer thickness to the first chalcogenide glass layer thickness is between about 3.1:1 and about 2:1.

Referring now toFIG. 5, a layer of silver25is formed over the first metal-containing layer18. By using a low energy method of deposition, such as, for example, evaporation, the layer of silver25can be added directly onto the metal-containing layer18. In a preferred embodiment, the silver layer25is employed with a metal-containing layer18that is a silver-selenide layer. The silver layer25preferably has a thickness of from about 50 Å to about 250 Å. In a variation of the first embodiment, a second layer of silver can be added so that a layer of silver is located on each side of the metal-containing layer18. That is, a second silver layer is located on a side of the metal-containing layer opposite the side on which a first silver layer is located.

Adding the silver layer25directly to the metal-containing layer18is advantageous for at least the following reason. In general, a certain quantity of excess silver is required in a cell for the best operation. If a silver layer is located above a second glass layer, the silver must diffuse through the second glass layer. Thus, one must calculate the amount of silver that will diffuse through the second glass layer. Any variation in glass thickness or temperature, however, can limit the amount of silver diffusion. By adding the silver directly to the metal-containing layer, one can provide the exact amount of silver necessary rather than attempting to calculate diffusion through the second glass layer.

A second glass layer20is formed over the silver layer25. One function of the second glass layer is to prevent or regulate migration of metal from an electrode into the element. Accordingly, although the exact mechanism by which the second glass layer may regulate or prevent metal migration is not clearly understood, the second glass layer may act as a metal diffusion control layer. For use as a diffusion control layer, any suitable glass may be used, including but not limited to, chalcogenide glasses. If the second glass layer is a chalcogenide glass, the second glass layer may, but need not, have the same stoichiometric composition as the first chalcogenide glass layer17, i.e., GexSe100−x. Thus, the second glass layer20may be of a different material, different stoichiometry, and/or more rigid construction than the first chalcogenide glass layer17.

The second glass layer20, when used as a diffusion control layer, may generally comprise any suitable glass material with the exception of SiGe and GaAs. Suitable glass material compositions for the second glass layer20can include, for example, SiSe (silicon-selenide), AsSe (arsenic-selenide, such as AS3Se2), GeS (germanium-sulfide), and combinations of Ge, Ag, and Se. Any one of the suitable glass materials may further comprise small concentrations, i.e., less than about 3%, of dopants including nitrides, metals, and other Group IIIA-VIA (13–16) elements.

The thickness of the layers is such that the metal-containing layer thickness is greater than the thickness of the second glass layer20. Preferably, a ratio of the metal-containing layer thickness to the second glass layer thickness is between about 5:1 and about 1:1. More preferably, the ratio of the metal-containing layer thickness to the second glass layer thickness is between about 3.3:1 and about 2:1. The second glass layer20preferably has a thickness of from about 100 Å to about 1000 Å, and more preferably has a thickness of about 150 Å.

The formation of the second glass layer20may be effected by any suitable method. For instance, methods such as chemical vapor deposition, evaporation, co-sputtering, or sputtering using a target having the desired stoichiometry, may be used.

Referring now toFIG. 6, a second conductive electrode material22is formed over the second glass layer20. The second conductive electrode material22may comprise any electrically conductive material, such as, for example, tungsten, tantalum, or titanium, among many others. Thus, advantageously, the second glass layer20may be chosen to considerably slow or prevent migration of electrically conductive metals through the resistance variable memory element100.

Referring now toFIG. 7, one or more additional dielectric layers30may be formed over the second electrode22and the first dielectric layer15to isolate the resistance variable memory element100from other structure fabrication over the substrate10. Conventional processing steps can then be carried out to electrically couple the second electrode22to various circuits of memory arrays.

In accordance with a variation of the first embodiment of the invention, one or more layers of a metal-containing material, such as silver-selenide, may be deposited on the first chalcogenide glass layer17. Any number of metal-containing layers may be used. As shown inFIG. 8, an optional second metal-containing layer19may be deposited on the first metal-containing layer18subsequent to the processing step shown inFIG. 4.

The thickness of the layers is such that the total thickness of the combined metal-containing layers, e.g. silver-selenide layers, is greater than or equal to the thickness of the first chalcogenide glass layer17. The total thickness of the combined metal-containing layers is also greater than the thickness of the second glass layer20. It is preferred that the total thickness of the combined metal-containing layers is from about 1 to about 5 times greater than the thickness of the first chalcogenide glass layer17, and accordingly, from about 1 to about 5 times greater than the thickness of the second glass layer20. It is even more preferred that the total thickness of the combined metal-containing layers is from about 2 to about 3.3 times greater than the thickness of the first chalcogenide glass layer17, and from about 2 to about 3.3 times greater than the thickness of the second glass layer20.

In accordance with yet another variation of the invention, the first chalcogenide glass layer17may comprise one or more layers of a chalcogenide glass material, such as, for example, germanium-selenide. The second glass layer20may also comprise one or more layers of a glass material. The first chalcogenide glass layer17and/or the second glass layer20may comprise any suitable number of layers. However, it is to be understood that the total thickness of the metal-containing layer(s) should be thicker than the total thickness of the one or more layers of chalcogenide glass. Additionally, the total thickness of the metal-containing layer(s) should be thicker than the total thickness of the one or more layers of the second glass layer. Preferably a ratio of the total thickness of the metal-containing layer(s) to the total thickness of the one or more layers of chalcogenide glass is between about 5:1 and about 1:1. Also, preferably a ratio of the total thickness of the metal-containing layer(s) to the total thickness of the one or more layers of the second glass layer is between about 5:1 and about 1:1. It is even more preferred that the total thickness of the metal-containing layer(s) is from about 2 to about 3.3 times greater than the total thicknesses of the combined one or more layers of chalcogenide glass, and that the total thickness of the metal-containing layer(s) is from about 2 to about 3.3 times greater than the total thickness of the combined one or more layers of the second glass.

In accordance with yet another variant of the invention, one or more of the chalcogenide glass layers and second glass layers may also be doped with a dopant, such as a metal, preferably silver.

Referring now toFIG. 9, which shows a second embodiment of the invention subsequent to the processing step shown inFIG. 4, the stack of layers formed between the first and second electrodes may include alternating layers of chalcogenide glass, a metal-containing layer such as a silver-selenide layer, and a silver layer. As shown inFIG. 9, a first chalcogenide glass layer17is stacked atop a first electrode14, a first metal-containing layer18is stacked atop the first chalcogenide glass layer17, a first silver layer25is stacked atop the first metal-containing layer18, a second chalcogenide glass layer117is stacked atop the first silver layer25, a second metal-containing layer118is stacked atop the second chalcogenide glass layer117, a second silver layer125is stacked atop the second metal-containing layer118, a third chalcogenide glass layer217is stacked atop the second silver layer125, a third metal-containing layer218is stacked atop the third chalcogenide glass layer217, a third silver layer225is stacked atop the third metal-containing layer218, and a fourth chalcogenide glass layer317is stacked atop the third silver layer225. The second conductive electrode22is formed over the fourth chalcogenide glass layer317.

In accordance with the above-described second embodiment, the stack comprises at least three metal-containing layers, at least three silver layers, and at least four chalcogenide glass layers. However, it is to be understood that the stack may comprise numerous alternating chalcogenide glass layers, metal-containing layers, and silver layers, so long as the alternating layers start with a first chalcogenide glass layer and end with a last chalcogenide glass layer, with the first chalcogenide glass layer contacting a first electrode and the last chalcogenide glass layer contacting a second electrode. The thicknesses and ratios of the alternating metal-containing layers, silver layers, and chalcogenide glass layers are the same as described above, in that the metal-containing layers are preferably thicker than connecting chalcogenide glass layers. That is, a ratio of the metal-containing layers thickness to the connected chalcogenide glass layers thickness is between about 5:1 and about 1:1, and is more preferably between about 3.3:1 and 2:1.

In a variation of the second embodiment, one or more layers of a metal-containing material, such as, for example, silver-selenide, may be deposited between the chalcogenide glass layers. Any number of metal-containing layers may be used. As shownFIG. 10at a processing step subsequent to that shown inFIG. 4, an additional metal-containing layer418may be deposited on the first silver-selenide layer18, with a silver layer25deposited on metal-containing layer418, and an additional metal-containing layer518may be deposited on the third metal-containing layer218, with a silver layer225deposited on metal-containing layer518.

In accordance, with yet another variation of the invention, each of the chalcogenide glass layers may comprise one or more thinner layers of a chalcogenide glass material, such as, for example, germanium-selenide. Any suitable number of layers may be used to comprise the chalcogenide glass layers.

In yet another variation of the second embodiment of the invention, one or more of the chalcogenide glass layers may also be doped with a dopant such as a metal, preferably comprising silver.

Devices constructed according to the first embodiment of the invention, particularly, those having a silver-selenide layer and a silver layer disposed between two chalcogenide glass layers, show improved memory retention and write/erase performance over conventional memory devices. These devices have also shown low resistance memory retention of greater than 1200 hours at room temperature. The devices switch at pulse widths of less than 2 nanoseconds compared with conventional doped resistance variable memory elements that switch at about 100 nanoseconds. In addition, the devices are more temperature resilient and have better cycling endurance.

Although the embodiments described above refer to the formation of only one resistance variable memory element100, it should be understood that the invention contemplates the formation of any number of such resistance variable memory elements, which can be fabricated in a memory array and operated with memory element access circuits.

FIG. 11illustrates an exemplary processing system900which may utilize the memory device100of the present invention. The processing system900includes one or more processors901coupled to a local bus904. A memory controller902and a primary bus bridge903are also coupled the local bus904. The processing system900may include multiple memory controllers902and/or multiple primary bus bridges903. The memory controller902and the primary bus bridge903may be integrated as a single device906.

The memory controller902is also coupled to one or more memory buses907. Each memory bus accepts memory components908which include at least one memory device100of the present invention. The memory components908may be a memory card or a memory module. Examples of memory modules include single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). The memory components908may include one or more additional devices909. For example, in a SIMM or DIMM, the additional device909might be a configuration memory, such as a serial presence detect (SPD) memory. The memory controller902may also be coupled to a cache memory905. The cache memory905may be the only cache memory in the processing system. Alternatively, other devices, for example, processors901may also include cache memories, which may form a cache hierarchy with cache memory905. If the processing system900include peripherals or controllers which are bus masters or which support direct memory access (DMA), the memory controller902may implement a cache coherency protocol. If the memory controller902is coupled to a plurality of memory buses907, each memory bus907may be operated in parallel or different address ranges may be mapped to different memory buses907.

The primary bus bridge903is coupled to at least one peripheral bus910. Various devices, such as peripherals or additional bus bridges may be coupled to the peripheral bus910. These devices may include a storage controller911, a miscellaneous I/O device914, a secondary bus bridge915, a multimedia processor918, and a legacy device interface920. The primary bus bridge903may also be coupled to one or more special purpose high speed ports922. In a personal computer, for example, the special purpose port might be the Accelerated Graphics Port (AGP), used to couple a high performance video card to the processing system900.

The storage controller911couples one or more storage devices913, via a storage bus912, to the peripheral bus910. For example, the storage controller911may be a SCSI controller and storage devices913may be SCSI discs. The I/O device914may be any sort of peripheral. For example, the I/O device914may be a local area network interface, such as an Ethernet card. The secondary bus bridge may be used to interface additional devices via another bus to the processing system. For example, the secondary bus bridge may be a universal serial port (USB) controller used to couple USB devices917via to the processing system900. The multimedia processor918may be a sound card, a video capture card, or any other type of media interface, which may also be coupled to one additional devices such as speakers919. The legacy device interface920is used to couple legacy devices, for example, older styled keyboards and mice, to the processing system900.

The processing system900illustrated inFIG. 11is only an exemplary processing system with which the invention may be used. WhileFIG. 11illustrates a processing architecture especially suitable for a general purpose computer, such as a personal computer or a workstation, it should be recognized that well known modifications can be made to configure the processing system900to become more suitable for use in a variety of applications. For example, many electronic devices which require processing may be implemented using a simpler architecture which relies on a CPU901coupled to memory components908and/or memory devices100. These electronic devices may include, but are not limited to audio/video processors and recorders, gaming consoles, digital television sets, wired or wireless telephones, navigation devices (including system based on the global positioning system (GPS) and/or inertial navigation), and digital cameras and/or recorders. The modifications may include, for example, elimination of unnecessary components, addition of specialized devices or circuits, and/or integration of a plurality of devices.

The above description and the drawings are only to be considered illustrative of exemplary embodiments which achieve the features and advantages of the invention. Modifications of, and substitutions to, specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.