Display device capable of reducing resistance of driving voltage supply wires

A display device includes a display panel including a display area and a peripheral area, a plurality of data lines and a plurality of driving voltage lines provided in the display area, a plurality of data connection lines provided in the peripheral area and connected to the plurality of data lines, a first driving voltage transmission line provided in the peripheral area and overlapping the plurality of data connection lines, a second driving voltage transmission line provided in the peripheral area and disposed between the first driving voltage transmission line and the display area, and a plurality of driving voltage connection lines. The plurality of driving voltage connection lines are connected to the first driving voltage transmission line and the second driving voltage transmission line, and provided between the first driving voltage transmission line and the second driving voltage transmission line.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0041555, filed in the Korean Intellectual Property Office on Apr. 5, 2016, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

This disclosure relates to a display device capable of reducing resistance of driving voltage supply wires.

DISCUSSION OF RELATED ART

Examples of display devices include organic light emitting diode (OLED) displays, liquid crystal displays (LCD), field emission displays (FED), and the like. An OLED display device emits light when an electron injected from a cathode and a hole injected from a anode are coupled with each other in an organic emission layer to form an exciton and the exciton discharges energy. Since the OLED display device has a self-luminance characteristic and does not require a separate light source, unlike an LCD, thickness and weight thereof may be reduced.

The OLED display device includes a plurality of pixels in a display area where an image is displayed, and each pixel may include an organic light emitting diode (OLED), a capacitor, a switching transistor, and a driving transistor. A driving voltage is applied to the driving transistor and the capacitor through a driving voltage line. In a peripheral area of the display area, wires are provided to transmit the driving voltage to the driving voltage line. When the length or width of the wires is increased or decreased, current density and voltage drop may also increase or decrease, causing deterioration in luminance uniformity of the image displayed in the display area.

SUMMARY

According to an exemplary embodiment of the inventive concept, a display device includes a display panel including a display area and a peripheral area, a plurality of data lines and a plurality of driving voltage lines provided in the display area, a plurality of data connection lines provided in the peripheral area and connected to the plurality of data lines, a first driving voltage transmission line provided in the peripheral area and overlapping the plurality of data connection lines, a second driving voltage transmission line provided in the peripheral area and disposed between the first driving voltage transmission line and the display area, and a plurality of driving voltage connection lines. The plurality of driving voltage connection lines are connected to the first driving voltage transmission line and the second driving voltage transmission line, and provided between the first driving voltage transmission line and the second driving voltage transmission line.

The first driving voltage transmission line and the second driving voltage transmission line may substantially extend in a first direction, and the plurality of data connection lines and the plurality of driving voltage connection lines may substantially extend in a second direction that crosses the first direction.

The plurality of data connection lines and the plurality of driving voltage connection lines may be alternately arranged one by one along the first direction.

At least two data connection lines among the plurality of data connection lines may be disposed between a pair of driving voltage connection lines among the plurality of driving voltage connection lines. The pair of driving voltage connection lines are adjacent to each other in the first direction.

A line width of each of the driving voltage connection lines may be wider than a line width of each of the data connection lines.

The display device may further include a driving voltage supply line provided in the peripheral area and connected to the first driving voltage transmission line, and a pad portion provided between the first driving voltage transmission line and an edge of the display panel. The driving voltage supply line is connected to the pad portion.

The second driving voltage transmission line and the plurality of data connection lines may overlap each other.

The display device may further include a plurality of gate lines provided in the display area. A portion of the plurality of data connection lines, overlapping the first driving voltage transmission line and the second driving voltage transmission line, may be provided in the same layer as the plurality of gate lines.

The peripheral area may include a bending area, and a portion of the plurality of data connection lines, provided in the bending area, is provided in the same layer as the plurality of driving voltage connection lines.

The first driving voltage transmission line, the second driving voltage transmission line, and the plurality of driving voltage connection lines may be provided in the same layer as the plurality of driving voltage lines.

According to an exemplary embodiment of the inventive concept, a display device includes a display panel including a display area and a peripheral area, a plurality of data lines and a plurality of driving voltage lines provided in the display area, a data driver provided in the peripheral area, a plurality of data connection lines provided in the peripheral area and connecting the data driver and the plurality of data lines, a driving voltage supply line provided in the peripheral area, a first driving voltage transmission line provided between the display area and the data driver and connected with the driving voltage supply line, a second driving voltage transmission line, provided between the display area and the first driving voltage transmission line, in the peripheral area, and a plurality of driving voltage connection lines, connected to the first driving voltage transmission line and the second driving voltage transmission line, in the peripheral area. At least one of the plurality of driving voltage connection lines is provided between the plurality of data connection lines.

The first driving voltage transmission line and the second driving voltage transmission line may substantially extend in a first direction, and the plurality of data connection lines and the plurality of driving voltage connection lines may substantially extend in a second direction that crosses the first direction.

The plurality of data connection lines and the plurality of driving voltage connection lines may be alternately arranged one by one along the first direction.

At least two data connection lines among the plurality of data connection lines may be disposed between a pair of driving voltage connection lines among the plurality of driving voltage connection lines. The pair of driving voltage connection lines are adjacent to each other in the first direction.

A line width of each of the driving voltage connection lines may be wider than a line width of each of the data connection lines.

The display device may further include a pad portion provided between the first driving voltage transmission line and an edge of the display panel in the peripheral area. The driving voltage supply line may be connected to the pad portion.

The plurality of data connection lines may overlap the first driving voltage transmission line and the second driving voltage transmission line.

The display device may further include a plurality of gate lines provided in the display area. A portion of the plurality of data connection lines, overlapping the first driving voltage transmission line and the second driving voltage transmission line, may be provided in the same layer as the plurality of gate lines.

The peripheral area may include a bending area, and a portion of the plurality of data connection lines, provided in the bending area, may be provided in the same layer as the plurality of driving voltage connection lines.

The first driving voltage transmission line, the second driving voltage transmission line, and the plurality of driving voltage connection lines may be provided in the same layer as the plurality of driving voltage lines.

According to an exemplary embodiment of the inventive concept, a display device includes a display panel including a display area and a peripheral area. The display area includes a plurality of pixels and the peripheral area includes a bending area. The display device further includes a plurality of data connection lines extending through the bending area, a first driving voltage transmission line provided in the peripheral area, a second driving voltage transmission line provided in the peripheral area and disposed between the first driving voltage transmission line and the display area, and a plurality of driving voltage connection lines connecting the first driving voltage transmission line and the second driving voltage transmission line, and disposed alongside the plurality of data connection lines. The display device further includes a common voltage supply line, a first common voltage transmission line, a second common voltage transmission line, and a plurality of common voltage connection lines. The common voltage supply line extends through a portion of the peripheral area, substantially surrounds the display area, and supplies a common voltage to the plurality of pixels. The first common voltage transmission line is disposed in the peripheral area, in parallel with the first driving voltage transmission line, and connected to the common voltage supply line. The second common voltage transmission line is disposed in the peripheral area and in parallel with the second driving voltage transmission line. The plurality of common voltage connection lines connects the first common voltage transmission line and the second common voltage transmission line, and is alternatively disposed alongside the plurality of data connection lines.

The display device may further include a plurality of data lines, a plurality of gate lines, and a plurality of driving voltage lines provided in the display area. The plurality of data connection lines is connected to the plurality of data lines. A first and a second portion of the plurality of data connection lines, overlapping the first driving voltage transmission line and the second driving voltage transmission line, respectively, are provided in the same layer as the plurality of gate lines. A third portion of the plurality of data connection lines, provided in the bending area, is provided in the same layer as the plurality of driving voltage connection lines.

A width of the first portion of the plurality of data connection lines or the second portion of the plurality of data connection lines may be greater than a width of the third portion of the plurality of data connection lines.

The first portion of the plurality of data connection lines and the second portion of the plurality of data connection lines may have higher resistivity than the third portion of the plurality of data connection lines.

The first portion of the plurality of data connection lines and the second portion of the plurality of data connection lines may be made of a molybdenum-based metal, and the third portion of the plurality of data connection lines may be made of an aluminum-based metal.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

In the drawings, thicknesses and sizes of multiple layers and areas may be enlarged or reduced in order to clearly express layouts and relative positions thereof. However, the inventive concept is not limited thereto.

In the specification, it will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. If not particularly defined in the specification, “overlapping” means that at least some parts of a layer, a film, an area, a plate, or the like overlap with each other in a plan view.

Although an organic light emitting diode display will be described below as an example of as a display device according to an exemplary embodiment of the inventive concept, the inventive concept is not limited to the organic light emitting diode display. Any display device to which a driving voltage is supplied is applicable.

Exemplary embodiments of the inventive concept provide display devices that can reduce the resistance of a driving voltage supply wire.

FIG. 1is a schematic top plan view of a display device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1, a display device according to an exemplary embodiment of the inventive concept includes a display panel300. The display panel300includes a display area DA where an image may be displayed, and a peripheral area PA where elements and/or wires for generation and/or transmission of various signals applied to the display area DA are arranged.

A plurality of pixels PX is, for example, arranged in a matrix format in the display area DA of the display panel300. In the display area DA, signal lines such as a plurality of gate lines G1to Gn, a plurality of data lines D1to Dm, and a plurality of driving voltage lines P1to Po are arranged. The plurality of gate lines G1to Gn may substantially extend in a first direction DR1(e.g., a row direction), and the plurality of data lines D1to Dm and the plurality of driving voltage lines P1to Po may extend in a second direction DR2(e.g., a column direction) that crosses the first direction DR1. Each pixel PX is connected with a corresponding gate line among the gate lines G1to Gn, a corresponding data line among the data lines D1to Dm, and a corresponding driving voltage line among the driving voltage lines P1to Po to receive a gate signal, a data voltage, and a driving voltage from the signal lines.

A driving device including a driving circuit chip400and gate drivers500aand500bthat generate and/or process signals for driving the peripheral area PA provided in the display panel300.

The driving circuit chip400includes a data driver, and may be mounted as an integrated circuit chip on the display panel300. The driving circuit chip400may be disposed in an upper side or a lower side of the display area DA with respect to the top plan view. According to exemplary embodiments of the inventive concept, the display device may include a plurality of driving circuit chips400.

The gate drivers500aand500bmay be integrated with the display panel300. The gate drivers500aand500bmay include a first gate driver500adisposed in the left side in the display area DA and a second gate driver500bdisposed in the right side in the display area DA with respect to the top plan view. According to exemplary embodiments of the inventive concept, the gate driver may be disposed in only one of the left side or the right side, and may be electrically connected to the display panel in the form of a tape carrier package (TCP).

The driving circuit chip400includes a signal controller that controls the data driver and the gate drivers500aand500b. According to exemplary embodiments of the inventive concept, the signal controller may be provided as a chip that is separate from the data driver, and for example, may be provided as an integrated circuit chip on an external printed circuit board of the display panel300. Thus, the driving circuit chip400mounted on the display panel300may include only the data driver with the signal controller provided separately or externally.

A flexible printed circuit board (FPCB) that transmits an external signal to the display panel300is attached to the peripheral area PA of the display panel300. The FPCB may be attached to a pad portion PP that is disposed further from the display area DA than the driving circuit chip400in the peripheral area PA. Thus, the pad portion PP may be disposed between an outer edge of the display panel300and the driving circuit chip400. The driving circuit chip400may receive an image signal and a control signal of the image signal through the FPCB and the pad portion PP. When the signal controller is provided separately from the driving circuit chip400, the driving circuit chip400may receive image data, a data control signal, and the like, supplied from the signal controller through the FPCB and the pad portion PP.

The gate lines G1to Gn of the display area DA receive a gate signal that includes a gate on voltage and a gate off voltage through the gate drivers500aand500b. The gate drivers500aand500breceive a vertical start signal, a clock signal, and a low voltage at a predetermined level from the driving circuit chip400through a gate signal line19connected to the driving circuit chip400, so as to generate the gate signal. InFIG. 1, although it is shown as a single line, the gate signal line19may include one or more signal lines that correspond to the number of signals applied to the gate drivers500aand500b, or the number of signal lines may be smaller or greater than the number of signals. When the signal controller is provided separately from the driving circuit chip400, at least one of the gate signal lines19may be directly connected to the pad portion PP rather than connected to the driving circuit chip400.

The data lines D1to Dm receive a data voltage from the data driver. For this, a data connection line17, connected to the driving circuit chip400that includes the data driver and the data lines D1to Dm, is disposed in the peripheral area PA, e.g., in a fanout area FO.

The driving voltage lines P1to Po of the display area DA receive a driving voltage through a driving voltage supply wire disposed in the peripheral area PA. The driving voltage supply wire includes driving voltage supply lines10aand10b, a first driving voltage transmission line11, and a second driving voltage transmission line12. The driving voltage supply lines10aand10bare connected with the pad portion PP, to which the FPCB is attached, and substantially extend in parallel. The first driving voltage transmission line11extends substantially in a direction parallel with the first direction DR1from one end of the driving voltage supply line10ato one end of the driving voltage supply line10b. The second driving voltage transmission line12is separate from the first driving voltage transmission line11and extends substantially in a direction parallel with the first direction DR1(and thus, parallel with the first driving voltage transmission line11). The driving voltage supply wire also includes a plurality of driving voltage connection lines15, each of which has one end connected to the first driving voltage transmission line11and the other end connected to the second driving voltage transmission line12. The driving voltage supply lines10aand10breceive a driving voltage through the pad portion PP, and the driving voltage is transmitted to the driving voltage lines P1to Po through the first driving voltage transmission line11, the plurality of driving voltage connection lines15, and the second driving voltage transmission line12. According to exemplary embodiments of the inventive concept, the driving voltage supply lines10aand10bmay be connected to the driving circuit chip400and thus receive the driving voltage therethrough.

In the top plan view, the driving voltage supply lines10aand10bare disposed on the left side and the right side of the driving circuit chip400, respectively, and the first driving voltage transmission line11connects the ends of the driving voltage supply lines10aand10b, as described above. Thus, the driving circuit chip400may be surrounded by the driving voltage supply lines10aand10b, the first driving voltage transmission line11, and the pad portion PP. According to exemplary embodiments of the inventive concept, the driving voltage supply lines10aand10bmay be disposed at only one of the left or right sides of the driving circuit chip400, or may be disposed in plural on the left side and/or the right side of the driving circuit chip400.

Since the first driving voltage transmission line11and the second driving voltage transmission line12are disposed between the driving circuit chip400and the display area DA, they overlap with the data connection line17in a third direction DR3(e.g., when viewed in a plan view), which is perpendicular to the plane formed by the first direction DR1and the second direction DR2, in an insulated manner.

The plurality of driving voltage connection lines15connects to the first driving voltage transmission line11and the second driving voltage transmission line12at many points. In wire design, there is a limit to how much a line width of the driving voltage supply lines10aand10bmay be increased. Therefore, according to the present exemplary embodiment, the first driving voltage transmission line11is formed and then the first driving voltage transmission line11is connected to the second driving voltage transmission line12through the plurality of driving voltage connection lines15. As such, resistance in the driving voltage supply wires can be lower compared to the resistance when the driving voltage supply lines10aand10bare directly connected to the second driving voltage transmission line12. Since the resistance of the driving voltage supply wires is reduced, a load effect can be reduced, and accordingly, occurrence of a luminance difference in a light emission area of the display panel300can be prevented or reduced.

A common voltage supply line20is provided in the peripheral area PA of the display panel300to supply a common voltage to the pixels PX. The common voltage supply line20receives a common voltage at a predetermined level through the pad portion PP and applies the common voltage to a common electrode of each of the pixels PX. The common voltage supply line20may be disposed further from the driving circuit chip400than the driving voltage supply lines10aand10b. The common voltage supply line20may surround the display area DA, or may be disposed in a part of the display area DA. For example, in the top plan view, the common voltage supply line20may be disposed only on the left side and/or the right side of the display area DA.

FIG. 2is a schematic side view illustrating the display device ofFIG. 1in a bent state according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1andFIG. 2, the peripheral area PA of the display panel300may include a bending area BA, and the display panel300may be bent with a predetermined curvature in the bending area BA. For bending, the display panel300may be entirely made of a flexible material or at least the bending area BA may be made of a flexible material.

As described, when the display panel300is bent, the width of the peripheral area PA when being viewed from the front (e.g., the top plan view) can be reduced so that the width of a bezel that covers the peripheral area PA in the display device, such as a smart phone, can be reduced. However, to bend the display panel300, the width of the peripheral area PA, where the bending area BA is located, is increased and accordingly, a distance between the pad portion PP and the display area DA is increased. Since the distance between the pad portion PP and the display area DA is increased, the length of the driving voltage supply wire (e.g., the driving voltage supply lines10aand10b) is increased to transmit the driving voltage to the display area PA from the pad portion PP. As such, the length increase of the driving voltage supply wire causes an increase in wire resistance. According to exemplary embodiments of the inventive concept, resistance of the driving voltage supply wire can be reduced through the first driving voltage transmission line11and the plurality of driving voltage connection lines15, as described above. Accordingly, the load effect that may increase due to the bending area BA can be reduced.

Hereinabove, the display device according to an exemplary embodiment of the inventive concept has been described. A driving voltage supply wire according to exemplary embodiments of the inventive concept will be described below in relation to a data connection line.

FIG. 3is a top plan view illustrating the fanout area FO ofFIG. 1,FIGS. 4A and 4Bare cross-sectional views ofFIG. 3, taken along the lines IVA-IVA′ and IVB-IVB′, respectively,FIG. 5is a cross-sectional view ofFIG. 3, taken along the line V-V′, andFIG. 6is a cross-sectional view ofFIG. 3, taken along the line VI-VI′, according to exemplary embodiments of the inventive concept.

Referring toFIG. 3together withFIG. 1, the driving voltage supply lines10aand10bare formed in parallel with each other substantially along the second direction DR2, and the first driving voltage transmission line11that connects the ends of the driving voltage supply lines10aand10bis formed substantially in parallel with the first direction DR1. It is illustrated inFIG. 3that lateral ends of the first driving voltage transmission line11contact the ends of the driving voltage supply lines10aand10b. However, the lateral ends of the first driving voltage transmission line11may extend further than (e.g., past) the ends of the driving voltage supply lines10aand10b.

The second driving voltage transmission line12is distanced from the first driving voltage transmission line11in the second direction DR2, and is formed in parallel with the first driving voltage transmission line11along the first direction DR1. The second driving voltage transmission line12may be adjacent to the display area DA, and may have a length that is substantially the same as the width of the display area DA.

The plurality of driving voltage connection lines15connecting the first driving voltage transmission line11and the second driving voltage transmission line12may be substantially in parallel with the plurality of data connection lines17that connects the driving circuit chip400and the plurality of data lines D1to Dm. As an example, the driving voltage supply lines10aand10bmay each have approximately a micrometer-sized width, the first driving voltage transmission line11and the second driving voltage transmission line12may each have a width of about 50 to about 200 micrometers, and the driving voltage connection line17may have a width of about 3 micrometers. However, the inventive concept is not limited thereto.

In the illustrated exemplary embodiments, the driving voltage connection lines15and the data connection lines17are alternately disposed one by one. As described, when the plurality of driving voltage connection lines15are formed, the entire width of the driving voltage connection lines15can be increased even though each of the driving voltage connection lines15has a narrow width. The driving voltage supply lines10aand10bmay be directly connected to the second driving voltage transmission line12and the width of the driving voltage supply lines10aand10bmay be increased to reduce the resistance of the driving voltage wire. However, because of other wires, there is a limit to how much the width of the driving voltage supply lines10aand10bmay be increased. According to the exemplary embodiments of the inventive concept, the resistance of the driving voltage wire can be reduced without substantially affecting the alignment or arrangement of other wires. Although the driving voltage connection lines15are disposed at the outermost edge on the left and right sides inFIG. 3, the data connection lines17may instead be disposed at the outermost edge on at least one of the left side or the right side.

Referring toFIG. 4A,FIG. 4B,FIG. 5, andFIG. 6, several cross-sections ofFIG. 3are illustrated. A buffer layer111and a gate insulation layer140are disposed on a substrate110, and a first portion17aand a third portion17cof the data connection line17are disposed on the gate insulation layer140. A first passivation layer180a, which is an insulating layer, is disposed on the first and third portions17aand17c, and the first driving voltage transmission line11, the second driving voltage transmission line12, and the driving voltage connection line15are disposed on the first passivation layer180a. A second portion17bof the data connection line17is disposed on the first passivation layer180a, and the second portion17bis connected with the first portion17aand the third portion17cof the data connection line17through contact holes85aand85bformed in the first passivation layer180a. The second portion17bmay be disposed in the bending area BA in the peripheral area PA. A second passivation layer180bis disposed on the first driving voltage transmission line11, the second driving voltage transmission line12, the driving voltage connection line15, and the second portion17bof the data connection line17, and an encapsulation layer390may be disposed thereover. According to exemplary embodiments of the inventive concept, at least one of the buffer layer111, the gate insulation layer140, the second passivation layer180b, or the encapsulation layer400may be omitted. The buffer layer111and the gate insulation layer140may be eliminated from the bending area BA, and for example, at least a portion that overlaps with the first portion17aof the data connection line17inFIG. 4Amay not be included.

In the illustrated exemplary embodiment, the data connection lines17include the first portion17a, the second portion17b, and the third portion17c, and the second portion17bis formed in a layer that is different from a layer where the first portion17aand the third portion17care formed. InFIG. 4A, the first portion17aand the third portion17care disposed below the first driving voltage transmission line11and the second driving voltage transmission line12with the first passivation layer180ainterposed therebetween, and the second portion17bis disposed in the same layer as that of the first and second driving voltage transmission lines11and12. Accordingly, when the second portion17bis formed in a different layer from that of the first portion17aand the third portion17c, the second portion17bdisposed in the bending area BA can be made of a material that can be easily bent.

The first portion17aand the third portion17cof the data connection lines17may be made of substantially the same material and in the same layer as that of, for example, the gate lines G1to Gn. The second portion17bof the data connection lines17, the first driving voltage transmission line11, the second driving voltage transmission line12, and the driving voltage connection line15may be, for example, made of substantially the same material and in the same layer as that of the data lines D1to Dm. Here, a wire made of substantially the same material and in the same layer as that of the gate line is referred to as a gate conductor, and a wire made of substantially the same material and in the same layer as that of the data line is referred to as a data conductor. The gate conductor may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), or a metal alloy thereof. The data conductor may include a metal such as copper (Cu), aluminum (Al), silver (Ag), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Pt), palladium (Pd), tantalum (Ta), tungsten (W), titanium (Ti), nickel (Ni), or a metal alloy thereof. The gate conductor and/or the data conductor may be formed as a single layer or a multilayer.

In the exemplary embodiment of the inventive concept, the gate conductor may be made of a molybdenum-based metal such as molybdenum or a molybdenum alloy, and the data conductor may be made of an aluminum-based metal having a small-sized modulus, such as aluminum or an aluminum alloy. Because of their material, the second portion17bof the data connection lines17in the bending area BA and the driving voltage connection line15have low stress caused by strain such that the risk of a short-circuit or degradation due to bending can be reduced. In this case, since a molybdenum-based metal has higher resistivity than an aluminum-based metal, the width of the first and third portions17aand17cis formed to be wider than the width of the second portion17bor the thickness of the first and third portions17aand17cis formed to be thicker than the thickness of the second portion17bso that resistance throughout the data connection lines17can be more uniform. The data conductor may have a triple-layered structure of, for example, titanium/aluminum/titanium.

A data line171of the display area DA is connected to the third portion17cof the data connection lines17through a contact hole85cformed in the first passivation layer180aand thus receives a data voltage therefrom. A driving voltage line172of the display area DA may extend from the second driving voltage transmission line12, and thus may be made of substantially the same material and in the same layer as that of the data connection line17.

FIG. 7is a top plan view illustrating the fanout area ofFIG. 1, andFIG. 8is a cross-sectional view ofFIG. 7, taken along the line VIII-VIII′, according to exemplary embodiments of the inventive concept.

Referring toFIG. 7andFIG. 8, unlike the exemplary embodiment shown inFIG. 4A, the data connection lines17are formed as a single layer rather than two separate layers. Other wires11,12,15,171, and172may be substantially the same as those in the exemplary embodiment ofFIG. 4A. When both the gate conductor and the data conductor are made of a material having a low modulus, risks of short-circuits and degradation of the data connection lines17and the driving voltage connection line15provided in the bending area BA can be reduced.

FIG. 9is a top plan view illustrating the fanout area ofFIG. 1, andFIG. 10is a cross-sectional view ofFIG. 9, taken along the line X-X′, according to exemplary embodiments of the inventive concept.

Referring toFIG. 9andFIG. 10, an example in which the data connection lines17are disposed on the driving voltage supply wire is illustrated. The buffer layer111and the gate insulation layer140are disposed on the substrate110. The driving voltage supply wires, such as the driving voltage supply lines10aand10b, the first and second driving voltage transmission lines11and12, and the driving voltage connection lines15, are disposed above the buffer layer111and the gate insulation layer140. The first passivation layer180ais disposed above the driving voltage supply wires10a,10b,11,12, and15, and the data connection lines17are disposed above the first passivation layer180a. The data connection lines17are formed as a single layer rather than two separate layers. The data lines171and the driving voltage lines172are also disposed above the first passivation layer180a, and the driving voltage lines172are connected to a protrusion12′ of the second driving voltage transmission line12through contact holes85dformed in the first passivation layer180a. According to the present exemplary embodiment, the driving voltage supply wires10a,10b,11,12, and15may be formed as a gate conductor, and the data connection lines17, the data lines171, and the driving voltage lines172may be formed as a data conductor. When both the gate conductor and the data conductor are made of a material having a low modulus, risks of short-circuits and degradation of the data connection lines17and the driving voltage connection lines15provided in the bending area BA can be reduced.

FIG. 9andFIG. 10illustrate an example where the driving voltage connection line15is formed as a single layer, but the driving voltage connection line15may be formed as a plurality of layers. For example, similar to the data connection line17in the exemplary embodiments ofFIG. 3toFIG. 6, the driving voltage connection line15may include a portion disposed above the first passivation layer180aonly in the bending area BA and formed as a data conductor. The portion of the driving voltage connection line15above the first passivation layer180amay be connected to a portion of the driving voltage connection line15, disposed below the first passivation layer180a, through contact holes formed in the first passivation layer180a. In this case, although only the data conductor is made of a material having a smaller modulus, risks of short-circuits and degradation of the driving voltage connection line15and the data connection line17in the bending area BA can be reduced.

FIG. 11andFIG. 12are top plan views illustrating the fanout area FA ofFIG. 1, according to exemplary embodiments of the inventive concept.

Unlike the exemplary embodiment ofFIG. 3toFIG. 6where the driving voltage connection lines15and data connection lines17are alternately arranged one by one, a plurality of data connection lines17are disposed between adjacent driving voltage connection lines15in the exemplary embodiments ofFIG. 11andFIG. 12.FIG. 11illustrates two data connection lines17disposed between adjacent driving voltage connection lines15, andFIG. 12illustrates four or more data connection lines17disposed between adjacent driving voltage connection lines15. When the driving voltage connection lines15are so disposed, the number of driving voltage connection lines15may be reduced compared to the exemplary embodiment ofFIG. 3toFIG. 6, and accordingly, the entire resistance of the driving voltage connection lines15may be increased. To prevent the resistance increase, the driving voltage connection line15may have, for example, a width that is wider than the width of the data connection line17, as shown inFIG. 12. When sufficient space cannot be assured between the data connection lines17, only the driving voltage connection lines15disposed on the outermost left side and the outermost right side may have a relatively wider width. The alignment and relative width of the driving voltage connection lines15and the data connection lines17of the present exemplary embodiment may be applied to the exemplary embodiment ofFIG. 7andFIG. 8and the exemplary embodiment ofFIG. 9andFIG. 10, where the data connection line17is formed as a single layer.

The exemplary embodiments ofFIG. 3toFIG. 6,FIG. 11, andFIG. 12may be implemented in a variety of combinations. For example, a portion where data connection lines17and driving voltage connection lines15are alternately arranged one by one and a portion where a plurality of data connection lines17are arranged between adjacent driving voltage connection lines15may be formed in the fanout area FO. As another example, when the driving voltage connection lines15and the data connection lines17are alternately arranged one by one, the driving voltage connection lines15disposed on the outermost left side and the outermost right side may have a wide width. The above-stated various combinations and modifications may also be applied to the exemplary embodiment ofFIG. 7andFIG. 8and the exemplary embodiment ofFIG. 9andFIG. 10.

Hereinabove, several methods for reducing wire resistance in driving voltage supply wires have been described. A structure and alignment applied to the driving voltage supply wire may also be applied to the common voltage supply line or wire. Referring toFIG. 1, the common voltage supply line20is formed to surround the display area DA through the bending area BA from the pad portion PP. However, a portion of the common voltage supply line20, extending substantially in parallel with the second direction DR2from the pad portion PP, is connected to a first common voltage transmission line substantially extended in parallel with the first direction DR1. The first common voltage transmission line may be connected to a second common voltage transmission line, which substantially extends in parallel with the first direction DR1between the bending area BA and the display area DA, through a plurality of common voltage connection lines that may be alternatively disposed substantially alongside the data connection lines17. In this case, portions of the common voltage supply line20, disposed on the left side and the right side of the display area DA, may be connected to lateral ends of the second common voltage transmission line. When the common voltage supply wires are formed as described above, resistance of the common voltage supply wires can be reduced to then reduce a load effect.

The driving voltage supply wire may be typically formed (e.g., the driving voltage supply lines10aand10bare directly connected to the second driving voltage transmission line12) and only the common voltage supply line20may be provided as described above to reduce wire resistance, or the driving voltage supply wire and the common voltage supply line20may both be provided as described above to reduce wire resistance. In the latter case, the first common voltage transmission line and the second common voltage transmission line may be disposed between the first driving voltage transmission line11and the bending area BA and between the bending area BA and the second driving voltage transmission line12, respectively, or the driving voltage connection line15, the common voltage connection line, and the data connection line17may be substantially alternately disposed.

FIG. 13is a schematic top plan view of a display device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 13, compared to the display device according to the exemplary embodiment ofFIG. 1, a mounting location of the driving circuit chip400is different in the present exemplary embodiment. The driving circuit chip400is mounted on the FPCB rather than on the display panel300. In this case, the plurality of data connection lines17may be directly connected to the pad portion PP on the display panel300, to which the FPCB is attached.

Alignment and arrangement of other constituent elements of the display device may be substantially equivalent to the exemplary embodiment ofFIG. 1. For example, the driving voltage supply lines10aand10bare provided on the left side and the right side of the plurality of the data connection lines17, respectively, and are formed substantially in parallel with the second direction DR2, extending from the pad portion PP. The first driving transmission line11formed at the ends of the driving voltage supply lines10aand10bis formed substantially in parallel with the first direction DR1, and accordingly, crosses the plurality of data connection lines17in an overlapping manner. The second driving voltage transmission line12is distanced from the first driving voltage transmission line11, and extends substantially in parallel with the first direction DR1at the periphery of the display area DA. The plurality of driving voltage connection lines15connects the first driving voltage transmission line11and the second driving voltage transmission line12. Since the driving circuit chip400is disposed further from the display area DA than the pad portion PP, unlike the exemplary embodiment ofFIG. 1, the driving circuit chip400is not surrounded by the driving voltage supply lines10aand10b, the first driving voltage transmission line11, and the pad portion PP. However, the relationship between the driving voltage wire and the data connection lines, as described with reference toFIG. 3toFIG. 12, may be applied to the present exemplary embodiment.

Hereinabove, various signal lines, particularly, the driving voltage wires, have been described with reference to the peripheral area PA of the display device. With respect toFIG. 14,FIG. 15, andFIG. 16, the display device will be described below, focusing on the pixels disposed in the display area DA of the display device, according to exemplary embodiments of the inventive concept.

FIG. 14is an equivalent circuit diagram of one pixel in the display device according to an exemplary embodiment of the inventive concept,FIG. 15is a layout view of a pixel area of the display device according to an exemplary embodiment of the inventive concept, andFIG. 16is a cross-sectional view ofFIG. 15, taken along the line XVI-XVI′.

Referring toFIG. 14, the display device includes a plurality of signal lines and the plurality of pixels PX connected thereto.

The plurality of signal lines includes a plurality of gate lines121transmitting a gate signal, the plurality of data lines171transmitting a data voltage, and the plurality of driving voltage lines172transmitting a driving voltage ELVDD. Referring toFIG. 1andFIG. 13, the gate line121receives the gate signal from the gate drivers500aand500bthat may be disposed in the peripheral area PA of the display panel300. The data line171receives the data voltage through the data connection lines17connected to the driving circuit chip400or the pad portion PP. The driving voltage line172receives the driving voltage ELVDD through the driving voltage supply lines10aand10b, the first driving voltage transmission line11, the driving voltage connection lines15, and the second driving voltage transmission line12.

Each pixel PX includes a switching transistor Qs, a driving transistor Qd, a storage capacitor Cst, and a light emitting element LD.

In the switching transistor Qs, a control terminal is connected to the gate line121, an input terminal is connected to the data line171, and an output terminal is connected to the driving transistor Qd. The switching transistor Qs transmits the data voltage applied to the data line171to the driving transistor Qd in response to the gate signal applied to the gate line121.

In the driving transistor Qd, a control terminal is connected to the switching transistor Qs, an input terminal is connected to the driving voltage line172, and an output terminal is connected to the light emitting element LD. An output current Id flows through the driving transistor Qd. The intensity of the output current Id varies according to a voltage between the control terminal and the output terminal of the driving transistor Qd.

The storage capacitor Cst is connected between the control terminal and the input terminal of the driving transistor Qd. The storage capacitor Cst charges the data voltage applied to the control terminal of the driving transistor Qd and maintains it even after the switching transistor Qs is turned off.

The light emitting element LD, which may be an organic light emitting diode OLED, includes an anode connected to the output terminal of the driving transistor Qd and a cathode connected to a common voltage ELVSS. The light emitting element LD enables an image to be displayed by emitting light with different intensities according to the output current Id from the driving transistor Qd.

The switching transistor Qs and the driving transistor Qd may each be an n-channel field effect transistor (FET) or a p-channel field effect transistor. The connection relationship between the switching transistor Qs, the driving transistor Qd, the storage capacitor Cst, and the light emitting element LD may be changed.

Referring toFIG. 15andFIG. 16, the display device includes the substrate110and the plurality of layers formed thereover. The substrate110may be a transparent insulation substrate, e.g., a flexible substrate formed of a transparent polymer film. For example, the substrate110may be made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene ether ketone (PEEK), polycarbonate (PC), polyethylene sulfonate (PES), polyimide (PI), or polyarylate (PAR).

The buffer layer111may be formed right above the substrate110so as to prevent dispersion of an impurity that may cause deterioration of a semiconductor characteristic and to prevent permeation of moisture. The buffer layer111may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (Al2O3), hafnium oxide (HfO3), yttrium oxide (Y2O3), or the like. The buffer layer111may be formed throughout the substrate110, but may not be formed in the bending area BA shown inFIG. 1andFIG. 13. According to exemplary embodiments of the inventive concept, the buffer layer111may be disposed in the substrate110. For example, the substrate110may have a structure in which a plastic layer and a buffer layer are alternately layered.

A first semiconductor154aand a second semiconductor154bare formed above the buffer layer111. The first semiconductor154amay include a channel region, a source region, and a drain region. The source region and the drain region are disposed at lateral sides of the channel region and may be doped. The second semiconductor154bmay include a channel region152b, a source region153b, and a drain region155b. The source region153band the drain region155bare disposed at lateral sides of the channel region152band may be doped. The first semiconductor154aand the second semiconductor154bmay include polysilicon. The first semiconductor154aand the second semiconductor154bmay include a semiconductor oxide or amorphous silicon.

The gate insulation layer140, which can be made of silicon oxide, silicon nitride, or the like, is disposed on the first semiconductor154aand the second semiconductor154b. The gate insulation layer140may not be disposed in the bending area BA shown inFIG. 1andFIG. 13. The gate insulation layer140may be formed as a single layer or multiple layers.

A gate conductor including the gate line121, a first gate electrode124a, and a second gate electrode124bis formed on the gate insulation layer140. The first gate electrode124amay overlap the channel region of the first semiconductor154a, and the second gate electrode124bmay overlap the channel region152bof the second semiconductor154b. Referring toFIG. 4A, the first portion17aand the third portion17cof the data connection lines17may be formed as gate conductors in the peripheral area PA of the display panel300. Referring toFIG. 7andFIG. 8, the data connection line17may be wholly formed as the gate conductor.

The first passivation layer180ais disposed on the gate insulation layer140and the gate conductor. The first passivation layer180aand the gate insulation layer140include a contact hole183aoverlapping the source region of the first semiconductor154a, a contact hole185aoverlapping the drain region of the first semiconductor154a, a contact hole183boverlapping the source region153bof the second semiconductor154b, and a contact hole185boverlapping the drain region155bof the second semiconductor154b. Referring toFIG. 4A, the first passivation layer180amay further include the contact hole85aoverlapping the first portion17aof the data connection line17, the contact hole85boverlapping one end of the third portion17cof the data connection line17, and the contact hole85coverlapping the other end of the third portion17cof the data connection line17. The contact holes85a,85b, and85cof the peripheral area may be formed when the contact holes183a,183b,185a, and185bof the display area are formed, and therefore no additional process is required. The first passivation layer180ain the pixel area and the first passivation layer180ain the bending area BA may be made of different materials. For example, the first passivation layer180ain the pixel area may include an inorganic material such as silicon oxide, silicon nitride, or the like, and the first passivation layer180ain the bending area BA may include an organic material. A layer made of an inorganic material is susceptible to cracks when being bent, and wires may be damaged due to the cracks.

A data conductor, including the data line171, the driving voltage line172, a first source electrode173a, a second source electrode173b, a first drain electrode175a, and a second drain electrode175b, is formed above the first passivation layer180a. Referring toFIG. 4AtoFIG. 8,FIG. 11, andFIG. 12, in the peripheral area, the first driving voltage transmission line11, the second driving voltage transmission line12, the driving voltage connection line15, and the second portion17bof the data connection line17may be formed as a data conductor. Referring toFIG. 9andFIG. 10, the data connection line17may be wholly formed as a gate conductor.

Each of the first source electrode173aand the first drain electrode175amay be respectively connected with the source region and the drain region of the first semiconductor154athrough the contact holes183aand185a. The first drain electrode175amay be connected with the second gate electrode124bthrough a contact hole184. The second source electrode173band the second drain electrode175bmay be respectively connected with the source region153band the drain region155bof the second semiconductor154bthrough the contact holes183band185b. Referring toFIG. 4A, in the peripheral area, the second portion17bof the data connection line17may be connected with the first portion17aand the third portion17cthrough the contact holes85aand85b, and the data line171may be connected to the third portion17cthrough the contact hole85c.

The first gate electrode124a, the first source electrode173a, and the first drain electrode175aform a switching transistor Qs together with the first semiconductor154a, while the second gate electrode124b, the second source electrode173b, and the second drain electrode175bform a driving transistor Qd together with the second semiconductor154b. In the transistors Qs and Qd, the gate electrodes124aand124bare disposed above the semiconductors154aand154band therefore the transistors may be called top-gate transistors. The structure of the switching transistor Qs and the driving transistor Qd may be variously modified. For example, the gate electrodes of the transistors Qd and Qs may be disposed below the semiconductors154aand154b. In this case, the transistors may be called bottom-gate transistors.

The second passivation layer180b, which may be made of an organic material or an inorganic material such as silicon oxide, silicon nitride, or the like, may be provided on the data conductor. The second passivation layer180bmay have a flat surface in order to increase the light emission efficiency of an organic light emitting element to be formed thereon. A contact hole185cthat overlaps the second drain electrode175bmay be formed in the second passivation layer180b.

A pixel electrode191is provided on the second passivation layer180b. The pixel electrode191of each pixel is connected with the second drain electrode175bthrough the contact hole185cof the second passivation layer180b. The pixel electrode191may be made of a reflective or semi-transmissive conductive material, or a transparent conductive material. The pixel electrode191may be formed as a single layer or multiple layers.

A pixel defining layer360(also referred to as a barrier rib) having a plurality of openings that overlap with the pixel electrode191may be provided on the second passivation layer180b. The openings of the pixel defining layer360, exposing the pixel electrode191, may define each pixel area. According to an exemplary embodiment of the inventive concept, the pixel defining layer360may be omitted.

A light emitting member370is provided on the pixel defining layer360and the pixel electrode191. The light emitting member370may include a first organic common layer371, a light emission layer373, and a second organic common layer375that are sequentially layered.

The first organic common layer371may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). When the first organic common layer371includes both the hole injecting layer (HIL) and the hole transport layer (HTL), the hole injecting layer (HIL) and the hole transport layer (HTL) may be sequentially layered. The first organic common layer371may be formed on an entire surface of the display area DA in which pixels are disposed, or may be formed only on the pixel area.

The light emission layer373may be provided on the pixel electrode191of a corresponding pixel. The light emission layer373may be made of an organic material that uniquely emits light of one of the primary colors, e.g., red, green, and blue, and may have a structure in which a plurality of organic material layers that emit light of different colors are layered. According to exemplary embodiments of the inventive concept, the light emission layer373may include a white emission layer. A part of the light emission layer373may overlap with the driving transistor Qd.

The second organic common layer375may include at least one of an electron transport layer (ETL) and an electron injecting layer (EIL), and when the second organic common layer375includes both the electron transport layer (ETL) and the electron injecting layer (EIL), the electron transport layer (ETL) and the electron injecting layer (EIL) may be sequentially layered.

A common electrode270that transmits a common voltage is provided on the light emitting member370. The common electrode270is made of a transparent conductive material, or is formed by thinly layering metals, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), or the like, to have a light transmitting property. The common electrode270is connected to the common voltage supply line20in the peripheral area PA of the display panel300and thus receives the common voltage therefrom. The pixel electrode191, the light emitting member370, and the common electrode270of each pixel PX form a light emission element.

The encapsulation layer390is provided above the common electrode270. The encapsulation layer390encapsulates the light emitting member370and the common electrode270to prevent permeation of moisture or oxygen from the outside. The encapsulation layer390may also be provided in the peripheral area. For example, the encapsulation layer390may be provided in the peripheral area, excluding portions where the driving circuit chip400is attached or mounted. The encapsulation layer390may include at least one inorganic layer and at least one organic layer, and the inorganic layers and organic layers may be alternately layered. The encapsulation layer390provided in the bending area BA may not include an inorganic layer.

As described above, according to exemplary embodiments of the inventive concept, the resistance of the driving voltage supply wire can be reduced. Therefore, a load effect of the display device can be reduced, to suppress or prevent occurrence of a difference in luminance.

While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it is to be understood by those of ordinary skill in the art that various modifications in form and details may be made thereto without departing from the spirit and scope of the present inventive concept as defined by the following claims.