Alternate-logic head-to-head gate driver on array

The disclosure is related to head-to-head (H2H) gate on arrays (GOA) for pixel-based displays that may have reduced dimensions. In the described embodiments, the H2H design with alternate logic may be used to drive groups of pixels (e.g., a pixel row or column) with a primary and a secondary driver, located in opposite ends of the bezel of the electronic device. In the alternate-logic design, a shared shift-register may be used to enable two rows or columns. Embodiments in which more than two rows or columns are controlled by a single shift register are also described.

BACKGROUND

The present disclosure relates generally to display devices and, more specifically, to gate drivers on array circuitry of the display devices.

In many devices, such as televisions, smartphones, computer panels, smartwatches, among others, display panels are employed to provide a user interface for displaying information and facilitate interaction. For example, in organic light emitting diode (OLED) panels, pixels may be arranged in rows and columns, and may receive driving voltages and/or data signals to produce images. In many systems, power to pixels may be provided in a row-by-row basis or column-by-column basis.

The driving circuitry that powers the pixels may be disposed in the border region (e.g., a bezel) of the device and operate by gating each row sequentially. In compact devices, a decrease in the dimensions of the bezel may be limited by, among other things, the size of the driving circuitry.

SUMMARY

In certain pixel-based panels of electronic devices, pixels may receive power through gated power lines. To activate groups in an ordered manner (e.g., row-by-row, column-by-column), gate driver on array (GOA) circuitry may be used as part of the circuitry that controls the provision of power to the power lines driving the pixels. GOA may be used to gate the activation of groups of pixels in a display based on a synchronizing clock signal. Embodiments described herein are related to head-to-head (H2H) GOA designs that may employ an alternate-logic structure. In the H2H design, the group of pixels may be driven from both ends of the bezel to provide redundancy and better driving performance In the alternate-logic structure, a shared shift-register may be used to enable two rows, which may decrease the footprint of the GOA circuitry. As a result, embodiments of electronic devices having bezels (e.g., display borders) with reduced dimension are also described.

With the foregoing in mind, an electronic device is described. The electronic device may include a display that has an array of pixels arranged in groups and a gate on array circuitry. The gate on array circuitry may have a first driver that receives a first clock signal and a first gate-enable signal, also referred to herein as Q node, and may provide a driving output signal to a pixel group. The gate on array circuitry may have a second driver that receives a second clock signal and the same first gate-enable signal, and may provide a second driving output signal to a second pixel group. The gate on array circuitry may also have a single shift register that generates the common first gate-enable signal.

In another embodiment, a display is described. The display may have a display portion having multiple of rows and a bezel that includes first and second bezel portions that are located on opposite sides of the bezel. A first gate on array circuitry may be disposed in the first bezel portion and may have a first group of logic units. At least one logic unit may drive two rows. A second gate on array circuitry may be disposed in the second bezel portion and may have a second group of logic units. At least one logic unit of the second group of logic units may drive two rows and at least one of these two rows is common with the two rows driven by the at least one logic unit of the first group of logic units.

In another embodiment, a method for displaying image data in a display panel is disclosed. The display panel may have multiple pixel groups. The method may include enabling two driver circuits on a first side of the display panel using a first gate-enable signal. The method may also include enabling two driver circuits on an opposite side of the display panel using a second gate-enable signal. The method may also include a process for providing a driving output signal to a common pixel group from one of the two driver circuits of the first side of the display panel and one of the two driver circuits of the opposite side of the display panel.

In another embodiment, a display is described. The display may include a pixel array formed from a group of pixel rows. The display may also include a bezel located along the periphery of the pixel array and may have a bezel portion having a bezel width. The bezel portion may contain a gate on array circuitry formed from logic units. Each logic unit may have a shift register coupled, each, to a respective primary and a respective secondary driver. The bezel length may have a portion that associated with (e.g., limited by, related to) dimensions of the gate on array circuitry and, thus, a reduction in the dimensions of the gate on array circuitry may lead to reduction in the bezel length.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Many electronic devices may use display panels to provide user interfaces. User display panels may be pixel-based panels, such as liquid crystal displays (LCD) panels, light-emitting diode (LED) panels, organic light emitting diodes (OLED) panels and/or plasma panels. In these panels, pixels are typically be arranged in rows and columns, which may receive power through gated power lines. The power, provided as driving signals, may operate in coordination with data signals to facilitate the formation of images. For example, a display may have multiple rows that are sequentially activated (e.g., one row at a time) with driving signals which are sequentially provided at each display cycle. To that end, gate on array (GOA) circuitry may receive a power signal (e.g., a driving signal) and gate the signal to each power line individually. Synchronizing clock signals may be used to gate each of the rows.

Circuitry that generates driving signals, such as the GOA, may be dedicated circuitry that is located along the borders of the display within the device. In some systems, including head-to-head (H2H) GOA systems, GOA circuitry may be located in opposite sides of the bezel of the display, as further detailed below. The use of H2H architectures in GOA circuitry may provide redundancy in the driving of pixel rows, which may increase the manufacturing yield and the reliability of the electronic device. H2H architectures may also decrease interlaced artifacts by reducing differences in adjacent lines due to kickback voltages that may appear in conventional interlaced architecture. As such, H2H architectures may provide an improved performance for displays. However, conventional H2H architectures may employ larger circuitry than conventional interlaced circuitry due to the presence of circuitry on both ends.

Due to its disposition within, or next to, the bezel of the electronic device, a decrease in the dimensions of the bezel may be limited, at least in part, by the size of the GOA circuitry. Thus, reduction of the dimensions in the GOA logic may allow a decrease in border dimensions, which may lead to reduced size bezels. Embodiments described herein relate to display drivers and/or GOA circuitry that may have a reduced size by employing alternate-logic head-to-head architecture. In the embodiments described herein, the GOA logic units employed in the alternate-logic head-to-head architecture may include a gating component (e.g., a shift register) that may control two or more rows of pixels. Therefore, a portion of the GOA logic unit for two rows is shared, thus reducing the amount of logic required to drive the display. The GOA logic described herein may be arranged in a H2H architecture, providing a reduced bezel with the alternate logic circuitry with redundancy and the reduction and/or elimination of interlaced artifacts.

With the foregoing in mind, a general description of suitable electronic devices with reduced bezel dimensions that may employ alternate-logic GOA systems for display driving, as discussed herein, are provided below. Turning first toFIG. 1, an electronic device10according to an embodiment of the present disclosure may include, among other things, one or more processor(s)12, memory14, nonvolatile storage16, a display18, input structures22, an input/output (I/O) interface24, a network interface26, and a power source28. The various functional blocks shown inFIG. 1may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium) or a combination of both hardware and software elements. It should be noted thatFIG. 1is merely one example of an implementation and is intended to illustrate the types of components that may be present in electronic device10.

By way of example, the electronic device10may represent a block diagram of the notebook computer depicted inFIG. 2, the handheld device depicted inFIG. 3, the handheld device depicted inFIG. 4, the desktop computer depicted inFIG. 5, the wearable electronic device depicted inFIG. 6, or similar devices. It should be noted that the processor(s)12and other related items inFIG. 1may be generally referred to herein as “data processing circuitry.” Such data processing circuitry may be embodied wholly or in part as software, firmware, hardware, or any combination thereof. Furthermore, the data processing circuitry may be a single contained processing module or may be incorporated wholly or partially within any of the other elements within the electronic device10.

In the electronic device10ofFIG. 1, the processor(s)12may be operably coupled with the memory14and the nonvolatile storage16to perform various algorithms Such programs or instructions executed by the processor(s)12may be stored in any suitable article of manufacture that includes one or more tangible, computer-readable media at least collectively storing the instructions or routines, such as the memory14and the nonvolatile storage16. The memory14and the nonvolatile storage16may include any suitable articles of manufacture for storing data and executable instructions, such as random-access memory, read-only memory, rewritable flash memory, hard drives, and optical discs. In addition, programs (e.g., an operating system) encoded on such a computer program product may also include instructions that may be executed by the processor(s)12to enable the electronic device10to provide various functionalities.

In certain embodiments, the display18may be a liquid-crystal display (LCD), which may allow users to view images generated on the electronic device10. In some embodiments, the display18may include a touch screen, which may allow users to interact with a user interface of the electronic device10. Furthermore, it should be appreciated that, in some embodiments, the display18may include one or more organic light emitting diode (OLED) displays, or some combination of LCD panels and OLED panels. The display18may receive images, data, or instructions from processor(s)12or memory14, and provide an image in display18for interaction. The display panels in display18may be disposed within a border and/or a bezel38, which may include a portion of the driving circuitry, including the alternate logic GOA circuitry described herein.

The input structures22of the electronic device10may enable a user to interact with the electronic device10(e.g., pressing a button to increase or decrease a volume level). The I/O interface24may enable electronic device10to interface with various other electronic devices, as may the network interface26. The network interface26may include, for example, one or more interfaces for a personal area network (PAN), such as a Bluetooth network, for a local area network (LAN) or wireless local area network (WLAN), such as an 802.11x Wi-Fi network, and/or for a wide area network (WAN), such as a 3rd generation (3G) cellular network, 4th generation (4G) cellular network, long term evolution (LTE) cellular network, or long term evolution license assisted access (LTE-LAA) cellular network. The network interface26may also include one or more interfaces for, for example, broadband fixed wireless access networks (WiMAX), mobile broadband Wireless networks (mobile WiMAX), asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video broadcasting-terrestrial (DVB-T) and its extension DVB Handheld (DVB-H), ultra-Wideband (UWB), alternating current (AC) power lines, and so forth. As further illustrated, the electronic device10may include a power source28. The power source28may include any suitable source of power, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.

In certain embodiments, the electronic device10may take the form of a computer, a portable electronic device, a wearable electronic device, or other type of electronic device. Such computers may include computers that are generally portable (such as laptop, notebook, and tablet computers) as well as computers that are generally used in one place (such as conventional desktop computers, workstations, and/or servers). In certain embodiments, the electronic device10in the form of a computer may be a model of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, or Mac Pro® available from Apple Inc.

By way of example, the electronic device10, taking the form of a notebook computer10A, is illustrated inFIG. 2in accordance with one embodiment of the present disclosure. Notebook computer10A, or laptop computer, may be a MacBook®, MacBook® Pro, MacBook Air® by Apple, Inc. The depicted computer10A may include a housing or enclosure36, a display18framed by a bezel38of the enclosure36, input structures22, and ports of an I/O interface24. In one embodiment, the input structures22(such as a keyboard and/or touchpad) may be used to interact with the computer10A, such as to start, control, or operate a GUI or applications running on computer10A. For example, a keyboard and/or touchpad may allow a user to navigate a user interface or application interface displayed on display18.

FIG. 3depicts a front view of a handheld device10B, which represents one embodiment of the electronic device10. The handheld device10B may represent, for example, a portable phone, a media player, a personal data organizer, a handheld game platform, or any combination of such devices. By way of example, the handheld device10B may be a model of an iPhone® available from Apple Inc. of Cupertino, Calif. The handheld device10B may include an enclosure36to protect interior components from physical damage and to shield them from electromagnetic interference. The enclosure36may include bezel38, which surrounds the display18. The bezel38may also include portions of the GOA circuitry and/or other circuitry that drives rows and/or columns of pixels in display18. The I/O interfaces24may open through the enclosure36and may include, for example, an I/O port for a hard-wired connection for charging and/or content manipulation using a standard connector and protocol, such as the Lightning connector provided by Apple Inc., a universal service bus (USB), or other similar connector and protocol.

User input structures22, in combination with the display18, may allow a user to control the handheld device10B. For example, the input structures22may activate or deactivate the handheld device10B, navigate user interface to a home screen, a user-configurable application screen, and/or activate a voice-recognition feature of the handheld device10B. Other input structures22may provide volume control, or may toggle between vibrate and ring modes. The input structures22may also include a microphone may obtain a user's voice for various voice-related features, and a speaker may enable audio playback and/or certain phone capabilities. The input structures22may also include a headphone input may provide a connection to external speakers and/or headphones.

FIG. 4depicts a front view of another handheld device10C, which represents another embodiment of the electronic device10. The handheld device10C may represent, for example, a tablet computer, or one of various portable computing devices. By way of example, the handheld device10C may be a tablet-sized embodiment of the electronic device10, which may be, for example, a model of an iPad® available from Apple Inc. of Cupertino, Calif. The handheld device10C may include an enclosure36to protect interior components from physical damage and to shield them from electromagnetic interference. The enclosure36may include bezel38, which surrounds the display18. The bezel38may also include portions of the GOA circuitry and/or other circuitry that drives rows and/or columns of pixels in display18. The I/O interfaces24may open through the enclosure36and may include, for example, an I/O port for a hard-wired connection for charging and/or content manipulation using a standard connector and protocol, such as the Lightning connector provided by Apple Inc., a universal service bus (USB), or other similar connector and protocol.

Turning toFIG. 5, a computer10D may represent another embodiment of the electronic device10ofFIG. 1. The computer10D may be any computer, such as a desktop computer, a server, or a notebook computer, but may also be a standalone media player or video gaming machine. By way of example, the computer10D may be an iMac®, or other similar device by Apple Inc. It should be noted that the computer10D may also represent a personal computer (PC) by another manufacturer. A similar enclosure36may be provided to protect and enclose internal components of the computer10D such as the display18. The display18may be surrounded by a bezel38of the enclosure36. In certain embodiments, a user of the computer10D may interact with the computer10D using various peripheral input devices, such as the keyboard22A or mouse22B (e.g., input structures22), which may connect to the computer10D.

Similarly,FIG. 6depicts a wearable electronic device10E representing another embodiment of the electronic device10ofFIG. 1that may operate using the techniques described herein. By way of example, the wearable electronic device10E, which may include a wristband43, may be an Apple Watch® by Apple, Inc. However, in other embodiments, the wearable electronic device10E may include any wearable electronic device such as, for example, a wearable exercise monitoring device (e.g., pedometer, accelerometer, heart rate monitor), or other device by another manufacturer. The display18, framed by a bezel38of the enclosure36of the wearable electronic device10E may include a touch screen display18(e.g., LCD, OLED display, active-matrix organic light emitting diode (AMOLED) display, and so forth), as well as input structures22, which may allow users to interact with a user interface of the wearable electronic device10E.

FIG. 7provides a schematic diagram for a pixel-based display18. The display18may have a display panel80may be formed by an array of pixels82. Pixels82may be arranged in pixel rows84and pixel columns86. In the illustrated display panel80, the pixel rows84may be driven by an H2H GOA system70, which include two GOA modules90. The GOA modules90may drive the pixel rows84through driving lines91. The pixels82may also receive image data from a data driver92through data lines93. Pixels82may update the amount of emissions and/or colors based on the information received through a data line93and clocked by a driving signal received through a driving line91. The GOA modules90may generate driving signals to driving lines91based on a signal received from a power source94.

In the schematic diagram, the bezel38may have a width104, which may be, among other things, be at least as wide as a width105of the GOA module90. The display panel80may have a width106and a height108, which may be based on a resolution of the display panel80. For example, resolutions may be 1024×760, 1080p, or 4K. As discussed herein, the reduction in the size of the bezels may relate to a reduction in the width104of the bezel in absolute terms, a reduction of the width104relative to the length106of the display panel80, and/or a reduction of the width104based on the number of pixel rows84. It should be noted that, while the descriptions herein discuss the GOA modules90as operating on pixel rows84, it should be understood that the GOA modules90may drive pixel columns86, or any other groupings for the array of pixels82.

FIG. 8is a diagram that illustrates a portion of a GOA module90that implements an alternate-logic GOA system. The illustrated portion of the GOA module90includes gate logic units121A and121B. Gate logic unit121A may include a shift register122A and gate driver logic124A. Similarly, gate logic unit121B may include a shift register122B and gate driver logic124B. Shift registers122A and122B may receive power and clock signals from a power and clock bus126. Based on a received clock signal, each shift register122A,122B, may produce an output gate-enable signal, which may include an output Q signal and a complementary output QB signal. In the illustrated system, shift registers122A and122B produce Q signals128A and128B, respectively, and complementary QB signals130A and130B, respectively.

The Q and QB signals may control a gate driver logic. For example, Q signal128A and QB signal130A may control each of the gate driver output circuits134A and136A of the gate driver logic124A. In some embodiments, gate driver output circuits may include push-pull circuitry (e.g., a pull-up transistor and a pull-down transistor). Gate driver output circuits134A and134B may employ NMOS (i.e., n-type metal oxide semiconductor) transistors. A bootstrapping capacitor132A may be used to assist the pull-up and -down operation of the NMOS transistors of both gate driver output circuits134A and134B. It should be understood that other types of transistors, such as p-type metal oxide semiconductor (PMOS) transistors, may be used to generate this circuitry and adaptations to the placement of bootstrapping capacitors132A may be provided accordingly, in light of the teachings of provided herein.

The gate driver output circuit134A, in operation, may be controlled by the output of the shift register122A. When the Q signal128A is high, and thus QB signal130A is low, the output gate line91A is pulled up and down to the value provided by the clock signal141A. When the Q signal128A is low, and thus QB signal130A is high, the output gate line91A may be pulled to gate low-level, which may be negative. The gate driver output circuit136A may also be controlled by the same output of the shift register122A. By contrast, however, the output gate line91B is pulled up to the value provided by the clock signal141B. In order to provide the sequential activation of rows, the clock signal141A and141B may include a phase shift between them, which is detailed below.

FIG. 8also illustrates a second gate logic unit121B, that includes the shift register122B and the gate driver logic124B. As with gate logic unit121A, the gate logic unit121B may drive two gate lines91C and91D using a single shift register122B and two gate driver output circuits134B and136B. Gate driver output circuit134B may pull the output gate line91C up and down based on the clock signal141C, and gate driver output circuit136B may pull the output gate line91D up and down based on the clock signal141D. As discussed above, the two gate driver output circuits134B and136B may share a bootstrapping capacitor132B.

As opposed to conventional GOA circuitry, in which each row may be coupled to a dedicated shift register, the shared shift register122A,122B in the GOA circuitry described above (i.e., a single shift register driving multiple pixel rows) may decrease the size of the GOA system as well as the number of components used to form the GOA logic. For example, in a system where a shift register is shared between two rows, the size of the GOA logic may be reduced by up to 50%. Further reduction in the number of shared bootstrapping capacitors132A,132B may further decrease the size and/or power consumption of the GOA logic. It should be noted that, while the above illustrations describe a single shift register being used to drive two pixel rows, modifications of the systems above that may be used to drive three, four, or more pixel rows are contemplated, with adjustments performed in view of the teachings provided herein.

FIG. 9provides a chart150illustrating signals that drive the gating logics124A and124B and the output signals that may drive output gate lines91A,91B,91C, and91D ofFIG. 8. The signals in chart150may be related to one of the ends of the display (e.g., a left end). Specifically, chart150illustrates Q signals128A and128B, produced respectively by shift registers122A and122B, clock signals141A,141B,141C, and141D, and the output gate lines91A,91B,91C, and91D in a single display cycle (e.g., a refresh cycle, an update cycle). For example, Q signal128A becomes enabled at time152. At time154, the clock signal141A is enabled. As a result, the output gate line91A is pulled high, and leads to activation of the pixels in the corresponding row. Note that the pull-up response may cause an increase in the Q signal128A at time154. At time156, the clock signal141B is enabled. As a result, the output gate line91B is pulled high, and leads to activation of the pixels in the corresponding row. The Q signal128A may increase further at time156due to the pull-up response on both gate driver output circuits134A and136A. Once the clock signals141A and141B are disabled, at times158and160, respectively, the corresponding output gate lines91A and91B are disabled and pulled down to gate low-level. Furthermore, at time162, the Q signal128A may be disabled and the output gate lines91A and91B are maintained at low-level by the gate driver output circuits134A and136A and by the QB signal generated by gate driver logic.

The activation of output gate lines91C and91D during the display cycle is performed in a similar manner. The Q signal128B may become enabled at time172and the gate driver output circuits134B and136B of gate driver logic124B may be pull-up and -down output gate lines91B and91C to the voltage provided by clock signals141C and141D, respectively. Thus, when clock signal141C becomes enabled, at time174, the gate line91C is pulled high, leading to activation of the pixels in the corresponding row. Similarly, when clock signal141D becomes enabled, at time176, the gate line91D is pulled high, leading to activation of the pixels in the corresponding row. As with Q signal128A, the Q signal128B may be enhanced due to the operation of the gate driver output circuits134B and136B. Gate line91C is pulled down once the clock signal141C becomes disabled at time178. Gate line91D is pulled down once the clock signal141D becomes disabled at time162. Gate driver output circuits134B and136C may be secured by QB signal at low-level at time182, when the Q signal128B becomes disabled.

The schematic diagram ofFIG. 10illustrates how the shared shift registers (e.g., shift registers that drive more than a single row) may be used in an alternate logic H2H GOA system160to drive pixel rows84A,84B,84C, and84D. In the diagram of the alternate-logic H2H GOA system160, each pixel82is represented by a resistor-capacitor element along a gate line. Each pixel row is driven by gate line outputs. In particular, pixel row84A is driven by outputs161A and161B, pixel row84B is driven by outputs161C and161D, pixel row84C is driven by outputs161E and161F, and pixel row84D is driven by outputs161G and161H. Outputs161A,161B,161C,161D,161E,161F,161G, and161H are driven by the gate driver output circuits164A,164B,164C,164D,164E,164F,164G, and164H, respectively.

In the alternate logic H2H GOA system160, each shift register (not illustrated inFIG. 10) may drive two gate driver output circuits, in an arrangement similar to the one illustrated inFIG. 10. Gate driver output circuit164A may receive a Q signal128A and a QB signal130A from a first shift register in a left side of the circuit. Gate driver output circuits164B and164D may receive a common Q signal128B and QB signal130B from a second shift register in a right side of the circuit. Gate driver output circuits164C and164E may receive a common Q signal128C and QB signal130C from a third shift register in a left side of the circuit. Gate driver output circuits164F and164H may receive a common Q signal128D and QB signal130D from a fourth shift register in a right side of the circuit. Gate driver output circuit164G and164I may receive a Q signal128E from a fifth shift register in a left side of the circuit. The relationship between the shift registers and the pixel rows in the alternate-logic system is further discussed below, with respect toFIG. 11.

It should be noted that the bootstrapping capacitors may be directly coupled to only one of the gate driver output circuits that drives a given pixel row. For example, pixel row84A is driven by gate driver output circuits164A and164B. The bootstrapping capacitor132A is directly coupled to the gate driver output circuit164A, and the gate driver output circuit164B does not have a bootstrapping capacitor directly coupled. The other pixels rows may be similarly arranged. In pixel row84B, the bootstrapping capacitor132B is directly coupled to the gate driver output circuit164D, and the gate driver output circuit164C does not have a bootstrapping capacitor directly coupled. In pixel row84C, the bootstrapping capacitor132C is directly coupled to the gate driver output circuit164E, and the gate driver output circuit164F does not have a bootstrapping capacitor directly coupled. In pixel row84D, the bootstrapping capacitor132D is directly coupled to the gate driver output circuit164H, and the gate driver output circuit164G does not have a bootstrapping capacitor directly coupled. This regular arrangement (e.g., one capacitor per pixel row) may allow a balanced distribution of driver strength along the gate lines, reducing the presence of interlacing artifacts. Moreover, as discussed with respect toFIG. 8, the shared bootstrapping capacitors may facilitate operation of the two gate driver output circuits coupled to them. As an example, the bootstrapping capacitor132B, coupled to the common Q signal128B, allows regular operation of the NMOS buffer transistors in both the gate driver output circuit164B and gate driver output circuit164D in contrast with conventional GOA circuitry in which each gate driver output circuit may use a dedicated bootstrapping capacitor. As a result, the number of capacitors in the GOA circuitry may be reduced relative to conventional systems, without affecting the choice of the transistor (i.e., using a PMOS pull-up transistor to obviate the bootstrapping capacitor) and/or switch technology used in the GOA circuitry.

FIG. 11illustrates a method200for operating an alternate-logic H2H GOA system, such as the alternate-logic H2H GOA system160, described above. The method200may be implemented by embodiments that include digital circuitry and/or switching circuitry that may be coupled to pixel rows, drive the pixel rows sequentially, and are arranged in an H2H manner, as discussed above. Implementations may include digital logic, analog circuitry, and/or hybrid circuitry, and may be implemented in integrated circuits and/or printed circuit boards.

As shown in process block202, method200initialize the display of a first row. To that end, in process block204, gate logic circuitry from a first end may provide a gate driver enable signal. In process block204, gate logic circuitry from a second end may provide a second gate driver enable signal. In some embodiments, process blocks202and/or204may be associated with activation of dummy pixel rows. In a process block208, a clock signal associated with the first row to the gate driver circuitry may provide a driving signal to the first row.

The display cycle may proceed to the next row in process block210. Following the first row, the alternate-logic operation may be applied. A decision block212may be associated with the alternate-logic operation. That is, for even rows, gate enable signals may be initialized from the second end (process block214) and for odd rows, gate enable signals may be initialized from the first end (process block216). Note that, as illustrated, at least, inFIG. 9, each gate enable signal may be active for a period greater than that of the period of activation of two rows. As such, at the beginning of process block218, the pixel row associated with the iteration may have an enabled gate driving circuit in both ends. In process block218, a clock signal may be used to drive the pixels in the corresponding row. The process may proceed iteratively until the last row, as illustrated by decision block220and process block210. At the end of displaying the last row, a next display cycle may begin, as represented by process block222.

With the foregoing in mind,FIGS. 12, 13, 15, and 16provide a detailed description and results for an embodiment of an alternate-logic H2H GOA system.FIG. 12is a circuit diagram illustrating a GOA logic unit301that includes a shift register302and two output drivers, secondary driver304A, and primary driver304B.FIG. 13is a circuit diagram illustrating an implementation of the GOA logic unit301ofFIG. 12. The GOA logic unit301may receive power and/or clock signals306, which may be used to drive the GOA logic unit301.

As discussed above with respect toFIG. 8, the shift register302may output a Q signal316and a QB signal318, based on a received primary clock signal314, set signal320, and reset signal321. As illustrated inFIGS. 12 and 13, the shift register302may receive a set signal320, a reset signal321, and a primary clock signal314. The set signal320and the reset signal321may be carry signals received from neighboring shift registers, as detailed with respect toFIG. 14. Upon receiving the set signal320, the shift register302may provide a Q signal316and a QB signal318that may cause the secondary driver304A and the primary driver304B to pull the signals up to the voltage of the secondary clock signal312and the primary clock signal314, respectively. It should be noted, as illustrated inFIG. 13, that the primary driver304B has a bootstrapping capacitor354between the output332and the gate of the pull-up transistor. As such, every two drivers may share a shift register and a capacitor, in contrast with conventional systems in which each driver may employ a dedicated shift register and bootstrapping capacitor. This reduction in component may lead to a reduction in the GOA circuitry and allow smaller bezels around displays.

FIG. 14illustrates a circuit diagram for a portion of an alternate-logic H2H GOA system370that may use GOA logic units, such as the GOA logic unit301illustrated inFIG. 12. The alternate-logic H2H GOA system370may also use the GOA logic unit illustrated inFIG. 18, or other GOA logic units capable of performing the method200discussed inFIG. 11. The alternate-logic H2H GOA system370may have a left side circuitry372and a right side circuitry374, which may be disposed along or within a bezel of an electronic device, as discussed herein. In the illustrated portion, left side circuitry372may include logic units381A,381B,381C,381D, and381E and right side circuitry374may include logic units381F,381G,381H, and381I. Each logic unit may be have a shift register. In particular, logic units381A,381B,381C,381D,381E,381F,381G,381H, and381I include shift registers382A,382B,382C,382D,382E,382F,382G,382H, and382I, respectively.

Each shift register may provide Q signals and QB signals to a primary driver and a secondary driver. For example, shift register382A may provide signals to a secondary driver384A and a primary driver386A, shift register382B may provide signals to a secondary driver384B and a primary driver386B, and shift register382F may provide signals to a secondary driver384F and a primary driver386F. The primary drivers and the secondary drivers may drive pixel rows. The left side circuitry372and the right side circuitry374may drive pixel rows from each side of the alternate-logic H2H GOA system370in a redundant manner (e.g., in a manner similar to the one illustrated inFIG. 10). For example, signals398A and398B may drive a first pixel row, signals399A and399B may drive a second pixel row, signals400A and400B may drive a third pixel row, signals402A and402B may drive a fourth pixel row, signals404A and404B may drive a fifth pixel row, signals406A and406B may drive a sixth pixel row, signals408A and408B may drive a seventh pixel row, and signals410A and410B may drive an eight pixel row. The alternate-logic H2H GOA system370may generate more signals than described herein to drive more pixel rows in portions of the alternate-logic H2H GOA system370not illustrated inFIG. 14.

Each of the driving signals may be generated by a primary driver and a secondary driver. For example, a primary driver386A and a secondary driver384F generate, respectively, signals389A and398B that drive the first pixel row, as described above. In the second row, a secondary driver384B and a primary driver386F generate, respectively, signals399A and399B that drive the second pixel row. As discussed above, primary drivers (e.g., primary drivers386A,386B,386F) may include a bootstrapping capacitor (e.g., bootstrapping capacitors132A,132B,132C,132D,132D inFIG. 10) and, thus, may perform differently from the secondary driver (e.g., secondary drivers384A,384B,384F) of a logic unit. Therefore, the logic units from the left side circuitry372may be staggered in relation to the logic units from the right side circuitry374to provide a balanced design, in which every pixel row is coupled to one primary driver and one secondary driver. Due to the staggered design, a secondary driver384A may be coupled to a dummy load396, as it does not couple to a pixel row. An alternative arrangement, in which the logic units from the left side circuitry372and the right side circuitry374are aligned and in which the primary driver and the secondary drivers in the right side circuitry are aligned to provide the balanced design may also be used with the logic units described herein.

Each shift register may also generate CARRY signals that may be used as SET and/or RESET (e.g., RST) inputs to other shift registers on the same side of the alternate-logic H2H GOA system370. In the illustrated portion ofFIG. 14, a CARRY signal392from shift register382A may be used as a SET input for the shift register382C and the CARRY signal394may be used as a SET input for the shift register382E and RESET input for the shift register382A. Note that in the illustrated system, the SET input of a shift register may be coupled to a CARRY output of a shift register that is arranged two shift registers above. That is, SET [N]=CARRY [N−4], in which N is an index for shift registers from both left side circuitry372and right side circuitry374(e.g.,382A is N=1,382F is N=2,382B is N=3, etc.). Similarly, the RESET input of a shift register may be coupled to a CARRY output of a shift register that is two shift registers below. That is RST [N]=CARRY [N+6]. The alternate-logic H2H GOA system370may employ a different type of structure. As an example, an alternate-logic H2H GOA system370in which SET [N]=CARRY [N−4] and RST [N]=CARRY [N+4] may be obtained by connecting the wires of adjacent shift registers. This type of logical connection may facilitate the alternate-logic arrangement in the alternate-logic H2H GOA system370, which allows reduction in the number of shift registers relative to conventional GOA systems.

FIG. 15is a chart600that provides simulated results for a logic unit, such as the GOA logic unit301ofFIG. 12when arranged in an alternate-logic H2H GOA system, such the alternate-logic H2H GOA system370that ofFIG. 14. As such, the operation described herein may be understood in view of GOA logic unit301ofFIGS. 12 and 13. References to signals in the chart600may refer to signals with similar numbering as illustrated inFIG. 12. The chart600has subplot602, which indicates the logic signals in the shift register302. Specifically, subplot602illustrates the input set signal320, the input reset signal321, and the output carry signal322. The subplot604that indicates the output Q signal316and QB signal318of the shift register302. Subplots606and608illustrate, respectively, the primary clock signal314and the output332of the primary driver304B. Subplot610and612illustrate, respectively, the secondary clock signal312and the output330of the secondary driver304A.

As discussed above, the logic inputs set signal320and reset signal321may control the shift register302. At time621, the input set signal320may be asserted by a carry output signal of a neighboring shift register. As a result, the QB signal318becomes low and the Q signal316becomes high at time623. The secondary driver304A may receive the Q signal316and the QB signal318and the output330may be pulled to the secondary clock signal312. As a result, at time625, when the secondary clock signal312is asserted, the output330of the secondary driver304A is pulled up to a high level. Similarly, the primary driver304B may receive the Q signal316and the QB signal318and the output332may be pulled to the primary clock signal314. As a result, at time627, when the primary clock signal314is asserted, the output332of the primary driver304B is pulled up to a high level. When the set signal320is de-asserted, an output carry signal322may be asserted in the output of the shift register302at time629. At time631, when the input reset signal321is asserted, the Q signal316and the QB signal318may be inverted. The primary driver304B and the secondary driver304A may have their respective outputs332and330pulled down to a low-voltage level from a power supply. Note that the chart600relates to the system ofFIG. 14, in which the shift registers are coupled using a SET [N]=CARRY [N−4] and RST [N]=CARRY [N+6] arrangement. In such system, a time interval633may appear.

FIG. 16is a diagram illustrating a potential reduction in bezel width that may be obtained by using the display circuitry in the border of an electronic device. In particular,FIG. 16shows a border section430of a device431, that may employ a conventional H2H GOA system without alternate logic (i.e., each driver is coupled to a dedicated shift register), and a border section432of a device433, that may employ an alternate-logic H2H GOA system (i.e., a primary and a secondary driver may be share a shift register), such as the alternate-logic H2H GOA system370illustrated inFIG. 14. Devices431and433may have a display with resolution of 2732×2048 pixels. The table below illustrates estimated dimensions for embodiments of electronic devices431and433that have respective border sections430and432. Border sections430and432may, each, include a scribe and break (S/B) section442, a first metal bus section444, GOA circuitry440, and a second metal bus section446. As discussed above, the use of the alternate-logic design allows substantial reduction of the GOA circuitry440by obviating the use of two dedicated shift registers per row. In the alternate-logic design, the GOA system may have an average distribution of a single shift register per row. Note the reduction of 365 μm in the dimensions of the GOA section400, leading to an approximately 35% reduction in the GOA section length434and approximately 20% reduction in the bezel circuitry length435for the border section432.

As discussed above, the use of shift registers that may control one or more pixel row drivers may allow reduction of the circuitry in the border of a display, which may facilitate reduction of the bezel. In some embodiments, the reduction of the GOA may be associated with the number of pixel rows or pixel columns. The use of the alternate logic may allow a reduction in the bezel width of 5%, 10%, 15%, 20%, 25%, 30%, 40%, or 50% based, among other things, on the dimensions of other circuitry (e.g., the sizes of the shift register and the drivers, the dimensions of the transistors in the drivers, and the dimensions of other circuitry in the bezel). In some embodiments, the use of the alternative-logic GOA circuitry may reduce the dimension of the GOA circuitry in a particular dimension with respect to the metal bus circuitry and/or other circuitry. For example, the contribution of the dimension of the GOA circuitry (e.g., GOA section length434) relative to the total length435may be reduced from about 60% to about 50%, or less. In embodiments where each shift register controls four drivers, for example, the bezel thickness reduction may be of up to 75%. It should be understood that the presence of other circuitry may also impact the bezel width.