Integrated circuit and method of forming same and a system

An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.

BACKGROUND

The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. Some of these digital devices, such as level shifter circuits, are configured to enable operation of circuits capable of operation in different voltage domains. As ICs have become smaller and more complex, operating voltages of these digital devices continue to decrease affecting IC performance.

DETAILED DESCRIPTION

In accordance with some embodiments, an integrated circuit includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving current capability. The second flip-flop has a second driving current capability different from the first driving current capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop (MBFF) configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal. In some embodiments, by configuring the first flip-flop and the second flip-flop with different driving current capabilities, the MBFF is a mixed driving multi-bit flip-flop.

In some embodiments, the first driving current capability of the first flip-flop is based on a first number of fins in one or more transistors in the first flip-flop. In some embodiments, the second driving current capability of the second flip-flop is based on a second number of fins in one or more transistors in the second flip-flop. In some embodiments, the second number of fins is different from the first number of fins.

In some embodiments, the first driving current capability of the first flip-flop is based on a first threshold voltage of one or more transistors in the first flip-flop. In some embodiments, the second driving current capability of the second flip-flop is based on a second threshold voltage of one or more transistors in the second flip-flop. In some embodiments, the second threshold voltage is different from the first threshold voltage.

In some embodiments, by configuring the MBFF as a mixed driving multi-bit flip-flop, a number of duplicate inverters in the clock path of the MBFF are reduced resulting in the MBFF having less input pins for a corresponding clock signal, and the MBFF occupies less area compared with other approaches.

In some embodiments, by configuring the MBFF as a mixed driving multi-bit flip-flop, a number of duplicate inverters in the clock path of the MBFF are reduced resulting in a lower total clock dynamic power consumption compared with other approaches. In some embodiments, by configuring the MBFF as a mixed driving multi-bit flip-flop, the power consumption of each flip-flop in the MBFF is optimized compared with other approaches.

Furthermore, in some embodiments, by configuring the MBFF as a mixed driving multi-bit flip-flop, the power consumption of each flip-flop in the MBFF is optimized as flip-flops that may be debanked in the design flow order to fix timing violations in other approaches, are upsized or downsized in the design flow within the same MBFF rather than being debanked to another flip-flop as in the other approaches.

FIG. 1is a schematic diagram of a multi-bit flip-flop (MBFF)100, in accordance with some embodiments.

MBFF100comprises a flip-flop102, a flip-flop104, a flip-flop106, a flip-flop108, an inverter120, an inverter122and a clock input pin130. MBFF100is a four bit flip-flop. In other words, MBFF includes four flip-flops (e.g., flip-flops102,104,106and108). Other numbers of bits or corresponding flip-flops in MBFF100are within the scope of the present disclosure. In some embodiments, MBFF100is part of an integrated circuit (not shown) that includes other MBFF's, similar to MBFF100, or one or more other flip-flops.

MBFF100is configured to receive input signals D1, D2, D3and D4, and to receive clock signal CLK on the clock input pin130. MBFF100is configured to generate output signals Q1, Q2, Q3and Q4.

Each of flip-flops102,104,106and108is further configured (not shown) to receive clock signal CLK and inverted clock signal CLKB. Each of flip-flops102,104,106and108is coupled to inverters120and122. In some embodiments, each of flip-flops102,104,106and108is configured (not shown) to share input pin130. Each of flip-flops102,104,106and108is further configured to receive clock signal CLK from input pin130, and is configured to receive inverted clock signal CLKB from inverter120. In some embodiments, each of flip-flops102,104,106and108are configured to receive clock signal CLK′ from inverter122. In some embodiments, clock signal CLK′ is a buffered version of clock signal CLK. In some embodiments, inverted clock signal CLKB is inverted from the clock signal CLK.

In some embodiments, one or more of flip-flops102,104,106and108are edge triggered flip-flops. In some embodiments, one or more of flip-flops102,104,106and108includes a DQ flip-flop, an SR-flip-flop, a T flip-flop, a JK flip-flop, or the like. Other types of flip-flops or configurations for at least flip-flop102,104,106or108are within the scope of the present disclosure.

An input terminal of inverter120is coupled to the clock input pin130, and is configured to receive clock signal CLK. An output terminal of inverter120is coupled to an input terminal of inverter122and is configured to output inverted clock signal CLKB.

An input terminal of inverter122is configured to receive inverted clock signal CLKB. An output terminal of inverter120is configured to output clock signal CLK′. Other configurations for at least inverter120or122are within the scope of the present disclosure.

MBFF100is configured as a mixed driving multi-bit flip-flop. For example, MBFF100includes flip-flops configured with at least two different driving current capabilities. In some embodiments, each of the flip-flops contained in MBFF100are configured to have different driving current capability. Other numbers of different driving current capabilities for MBFF100are within the scope of the present disclosure. For example, in some embodiments, MBFF100includes three different flip-flops, each of the three different flip-flops is configured with a different driving current capability from the other.

Flip-flop102and flip-flop104(collectively referred to as “a set of flip-flops110”) are each configured to have a first driving current capability FF1. In some embodiments, the first driving current capability FF1corresponds to the driving current conducted by at least flip-flop102or flip-flop104.

Flip-flop106and flip-flop108(collectively referred to as “a set of flip-flops112”) are each configured to have a second driving current capability FF0. In some embodiments, the second driving current capability FF0corresponds to the driving current conducted by at least flip-flop106or flip-flop108. In some embodiments, the second driving current capability FF0is different from the first driving current capability FF1.

In some embodiments, the first driving current capability FF1of at least flip-flop102or flip-flop104is based on a first number of fins F1in one or more transistors in flip-flop102or flip-flop104.

In some embodiments, the second driving current capability FF0of at least flip-flop106or flip-flop108is based on a second number of fins F2in one or more transistors in flip-flop106or flip-flop108. In some embodiments, the first number of fins F1is different from the second number of fins F2. In some embodiments, at least the first number of fins F1or the second number of fins F2includes a single fin. In some embodiments, at least the first number of fins F1or the second number of fins F2includes multiple fins. In some embodiments, the use of multiple fins increases channel width and current driving strength of the transistors in the set of flip-flops110or112. In some embodiments, additional fins are used to add further current driving strength, and these arrangements are within the scope of the present disclosure.

In some embodiments, the first number of fins F1and the first driving current capability FF1have a direct relationship. For example, in some embodiments, as the first number of fins F1in one or more transistors in flip-flop102or flip-flop104is increased, the first driving current capability FF1is also increased. For example, in some embodiments, as the first number of fins F1in one or more transistors in flip-flop102or flip-flop104is decreased, the first driving current capability FF1is also decreased.

In some embodiments, the second number of fins F2and the second driving current capability FF0have a direct relationship. For example, in some embodiments, as the second number of fins F2in one or more transistors in flip-flop106or flip-flop108is increased, the second driving current capability FF0is also increased. For example, in some embodiments, as the second number of fins F2in one or more transistors in flip-flop106or flip-flop108is decreased, the second driving current capability FF0is also decreased.

Thus, by adjusting the first number of fins F1in at least flip-flop102or flip-flop104to be different from the second number of fins F2in at least flip-flop106or flip-flop108, the first driving current capability FF1and the second current driving capability FF0are also adjusted.

In some embodiments, the first driving current capability FF1of at least flip-flop102or flip-flop104is based on a first threshold voltage Vth1of one or more transistors in flip-flop102or flip-flop104.

In some embodiments, the second driving current capability FF0of at least flip-flop106or flip-flop108is based on a second threshold voltage Vth2of one or more transistors in flip-flop106or flip-flop108. In some embodiments, the first threshold voltage Vth1is different from the second threshold voltage Vth2. In some embodiments, the first threshold voltage Vth1is at least a high threshold voltage (HVT), a low threshold voltage (LVT) or a standard threshold voltage (SVT). In some embodiments, HVT is greater than at least LVT or SVT. In some embodiments, SVT is greater than LVT. In some embodiments, the second threshold voltage Vth2is at least HVT, LVT or SVT.

In some embodiments, the first threshold voltage Vth1and the first driving current capability FF1have an inverse relationship. For example, in some embodiments, as the first threshold voltage Vth1of one or more transistors in flip-flop102or flip-flop104is increased, the first driving current capability FF1is decreased. For example, in some embodiments, as the first threshold voltage Vth1of one or more transistors in flip-flop102or flip-flop104is decreased, the first driving current capability FF1is increased.

In some embodiments, the second threshold voltage Vth2and the second driving current capability FF0have an inverse relationship. For example, in some embodiments, as the second threshold voltage Vth2of one or more transistors in flip-flop106or flip-flop108is increased, the second driving current capability FF0is decreased. For example, in some embodiments, as the second threshold voltage Vth2of one or more transistors in flip-flop106or flip-flop108is decreased, the second driving current capability FF0is increased.

In some embodiments, the first threshold voltage Vth1is dependent upon at least an oxide thickness or an oxide material of the transistors in the set of flip-flops110, a doping profile of the transistors in the set of flip-flops110, a transistor device geometry including a channel width of the transistors in the set of flip-flops110, a transistor size of the transistors in the set of flip-flops110, or the like.

In some embodiments, the second threshold voltage Vth2is dependent upon at least an oxide thickness or an oxide material of the transistors in the set of flip-flops112, a doping profile of the transistors in the set of flip-flops112, a transistor device geometry including a channel width of the transistors in the set of flip-flops112, a transistor size of the transistors in the set of flip-flops112, or the like.

In some embodiments, by configuring MBFF100as a mixed driving multi-bit flip-flop, a number of duplicate inverters in the clock path of MBFF100are reduced resulting in MBFF100having less input pins for a corresponding clock signal, and MBFF100occupying less area compared with other approaches.

In some embodiments, by configuring MBFF100as a mixed driving multi-bit flip-flop, a number of duplicate inverters in the clock path of MBFF100are reduced resulting in a lower total clock dynamic power consumption compared with other approaches. In some embodiments, by configuring MBFF100as a mixed driving multi-bit flip-flop, the power consumption of each flip-flop in MBFF100is optimized compared with other approaches.

Furthermore, in some embodiments, by configuring MBFF100as a mixed driving multi-bit flip-flop, the power consumption of each flip-flop in MBFF100is optimized as flip-flops that may be debanked in order to fix timing violations in other approaches, are upsized or downsized within the same MBFF rather than being debanked to another flip-flop as in the other approaches. In other words, in some embodiments, MBFF100can maintain the benefits of being part of a multi-bit flip-flop without the timing violations or the extra power consumption of other approaches.

FIG. 2Ais a circuit diagram of a circuit200A, in accordance with some embodiments.

Circuit200A is an embodiment of MBFF100ofFIG. 1. In some embodiments, circuit200A or circuit200B (FIG. 2B) is an MBFF circuit. In some embodiments, circuit200A or circuit200B are part of an integrated circuit.

Circuit200A is a four bit flip-flop, and each bit is associated with a corresponding flip-flop (e.g., flip-flops202,204,206and208). In other words, circuit200A includes four flip-flops (e.g., flip-flops202,204,206and208). Other numbers of bits or numbers of corresponding flip-flops in circuit200A are within the scope of the present disclosure. In some embodiments, circuit200A is part of an integrated circuit (not shown) that includes other MBFFs, similar to MBFF100, or one or more other flip-flops.

Flip-flop202and flip-flop204(collectively referred to as “a set of flip-flops210”) are each configured to have the first driving current capability FF1. In some embodiments, the first driving current capability FF1corresponds to the driving current conducted by at least flip-flop202or flip-flop204.

Flip-flop206and flip-flop208(collectively referred to as “a set of flip-flops212”) are each configured to have the second driving current capability FF0. In some embodiments, the second driving current capability FF0corresponds to the driving current conducted by at least flip-flop206or flip-flop208.

Flip-flops202,204,206and208are embodiments of corresponding flip-flops102,104,106and108ofFIG. 1, and similar detailed description is omitted. Set of flip-flops210and212are embodiments of corresponding set of flip-flops110and112ofFIG. 1, and similar detailed description is omitted. Clock input pin230is an embodiment of clock input pin130ofFIG. 1, and similar detailed description is omitted.

Each of flip-flops202,204,206and208are a DQ flip-flop. In some embodiments, one or more of flip-flops202,204,206and208includes an SR-flip-flop, a T flip-flop, a JK flip-flop, or the like. Other types of flip-flops or configurations for at least flip-flop202,204,206and208are within the scope of the present disclosure.

Each of flip-flops202,204,206and208has a corresponding clock input terminal configured to receive clock signal CLK, a corresponding set input terminal configured to receive a set signal S1, and a corresponding reset input terminal configured to receive a reset signal R1.

In some embodiments, each of flip-flops202,204,206and208is configured to share the clock input pin230, a set input pin232and a reset input pin234. Each of flip-flops202,204,206and208is configured to receive the clock signal CLK from input pin230, is configured to receive the set signal S1from the set input pin232, and is configured to receive the reset signal R1from reset input pin234. In some embodiments, the set input terminals of flip-flops202,204,206and208are coupled together and configured to receive the set signal S1from the set input pin232. In some embodiments, the reset input terminals of flip-flops202,204,206and208are coupled together and configured to receive the reset signal R1from the set input pin234.

FIG. 2Bis a circuit diagram of a circuit200B, in accordance with some embodiments.

Circuit200B is an embodiment of circuit100ofFIG. 1.

Circuit200B is a variation of circuit200A, and similar detailed description is therefore omitted. For example, circuit200B illustrates an example of where circuit200B includes a 2 bit, scan chain multi-bit flip-flop.

Components that are the same or similar to those in one or more ofFIGS. 1, 2A-2B, 5A-5B and 6A-6D(shown below) are given the same reference numbers, and detailed description thereof is thus omitted.

Circuit200B comprises a flip-flop250, a flip-flop252, a multiplexer260, a multiplexer262, a clock input pin230′, a set input pin232′, a reset input pin234′, a scan enable pin270and a scan in pin272.

Circuit200B is a 2 bit MBFF arranged in a scan chain configuration. Each bit in circuit200B is associated with a corresponding flip-flop (e.g., flip-flops250and252). In other words, circuit200B includes two flip-flops (e.g., flip-flops250and252). Other numbers of bits or numbers of corresponding flip-flops in circuit200B are within the scope of the present disclosure. In some embodiments, circuit200B is part of an integrated circuit (not shown) that includes other MBFFs, similar to MBFF100, or one or more other flip-flops.

Flip-flop250is an embodiment of flip-flop102or106ofFIG. 1, flip-flop252is an embodiment of flip-flop104or108ofFIG. 1, and similar detailed description is omitted. Clock input pin230′ is an embodiment of clock input pin130ofFIG. 1or clock input pin230of FIG.2A, set input pin232′ is an embodiment of set input pin232ofFIG. 2A, reset input pin234′ is an embodiment of reset input pin234ofFIG. 2A, and similar detailed description is omitted.

Flip-flop250and flip-flop252are each configured to have the first driving current capability FF1or the second driving current capability FF0.

Each of flip-flops250or252are a DQ flip-flop. In some embodiments, one or more of flip-flops250or252includes an SR-flip-flop, a T flip-flop, a JK flip-flop, or the like. Other types of flip-flops or configurations for at least flip-flop250or252are within the scope of the present disclosure.

Each of flip-flops250or252has a corresponding clock input terminal configured to receive clock signal CLK, a corresponding set input terminal configured to receive a set signal S1, and a corresponding reset input terminal configured to receive a reset signal R1.

In some embodiments, each of flip-flops250and252is configured to share the clock input pin230′, a set input pin232′ and a reset input pin234′. Each of flip-flops250and252is configured to receive the clock signal CLK from input pin230′, is configured to receive the set signal S1from the set input pin232′, and is configured to receive the reset signal R1from reset input pin234′. In some embodiments, the set input terminals of flip-flops250and252are coupled together and configured to receive the set signal S1from the set input pin232′. In some embodiments, the reset input terminals of flip-flops250and252are coupled together and configured to receive the reset signal R1from the set input pin234′.

Multiplexer260has a first input terminal configured to receive input signal D1or D3, a second input terminal configured to receive scan in signal SI1, a third input terminal configured to receive the scan enable signal SE1, and an output terminal configured to output the input signal of flip-flop250(e.g., signal D1, D3or SI1).

Multiplexer262has a first input terminal configured to receive input signal D2or D4, a second input terminal configured to receive output signal Q1from flip-flop250, a third input terminal configured to receive the scan enable signal SE1, and an output terminal configured to output the input signal of flip-flop252(e.g., signal D2, D4or Q1).

In some embodiments, multiplexers260and262are coupled to and configured to share the scan enable input pin270. In some embodiments, the third terminals of multiplexer260and262are coupled together and configured to receive the scan enable signal SE1from the scan enable input pin270.

The first input terminal of multiplexer260is configured to receive input signal D1or D3, and the first input terminal of multiplexer262is configured to receive input signal D2or D4based on whether flip-flop250corresponds to an embodiment of flip-flop102or106ofFIG. 1, and whether flip-flop252corresponds to an embodiment of flip-flop104or108ofFIG. 1. For example, if flip-flop250is an embodiment of flip-flop102, then the first input terminal of multiplexer260is configured to receive input signal D1, and if flip-flop252is an embodiment of flip-flop104, then the first input terminal of multiplexer262is configured to receive input signal D2. For example, if flip-flop250is an embodiment of flip-flop106, then the first input terminal of multiplexer260is configured to receive input signal D3, and if flip-flop252is an embodiment of flip-flop108, then the first input terminal of multiplexer262is configured to receive input signal D4.

FIG. 3is a functional flow chart of at least a portion of an IC design and manufacturing flow300, in accordance with some embodiments. The design and manufacturing flow300utilizes one or more electronic design automation (EDA) tools for generating, optimizing and/or verifying a design of an IC before manufacturing the IC. The EDA tools, in some embodiments, are one or more sets of executable instructions for execution by a processor or controller or a programmed computer to perform the indicated functionality. In at least one embodiment, the IC design and manufacturing flow300is performed by a design house of an IC manufacturing system discussed herein with respect toFIG. 3.

At IC design operation310, a design of an IC is provided by a circuit designer. In some embodiments, the design of the IC comprises an IC schematic, i.e., an electrical diagram, of the IC. In some embodiments, the schematic is generated or provided in the form of a schematic netlist, such as a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist. Other data formats for describing the design are usable in some embodiments. In some embodiments, a pre-layout simulation is performed on the design to determine whether the design meets a predetermined specification. When the design does not meet the predetermined specification, the IC is redesigned. In at least one embodiment, a pre-layout simulation is omitted fromFIG. 3. In at least one embodiment, method300further includes a pre-layout simulation performed after operation310.

At Automatic Placement and Routing (APR) operation320, a layout diagram of the IC is generated based on the IC schematic. The IC layout diagram comprises the physical positions of various circuit elements of the IC as well as the physical positions of various nets interconnecting the circuit elements. For example, the IC layout diagram is generated in the form of a Graphic Design System (GDS) or GDSII file. Other data formats for describing the design of the IC are within the scope of various embodiments. In the example configuration inFIG. 3, the IC layout diagram is generated by an EDA tool, such as an APR tool. The APR tool receives the design of the IC in the form of a netlist as described herein. The APR tool performs floor planning to identify circuit elements, which are to be electrically connected to each other and which are to be placed in close proximity to each other, for reducing the area of the IC and/or reducing time delays of signals travelling over the interconnections or nets connecting the electrically connected circuit elements. In some embodiments, the APR tool performs partitioning to divide the design of the IC into a plurality of blocks or groups, such as clock and logic groups. In the example configuration inFIG. 3, the APR tool performs one or more of a power planning operation322, a cell placement operation324, a clock tree synthesis (CTS) operation326or a routing operation328.

At power planning operation322, the APR tool performs power planning, based on the partitioning and/or the floor planning of the IC design, to generate a power grid structure which includes several conductive layers, such as metal layers. In some embodiments, one metal layer of the metal layers includes power lines or power rails extending in one direction, e.g., horizontally in a plan view. In some embodiments, another metal layer of the metal layers includes power lines or power rails extending in an orthogonal direction, e.g., vertically in a plan view.

At cell placement operation324, the APR tool performs cell placement. For example, standard cells (also referred to herein as “cells”) configured to provide pre-defined functions and having pre-designed layout diagrams are stored in one or more cell libraries325. The APR tool accesses various cells from one or more cell libraries325, and places the cells in an abutting manner to generate an IC layout diagram corresponding to the IC schematic.

The generated IC layout diagram includes the power grid structure and a plurality of cells, each cell including one or more circuit elements and/or one or more nets. In some embodiments, each cell includes one or more flip-flops or one or more multi-bit flip-flops, similar to the multi-bit flip-flop100ofFIG. 1, the multi-bit flip-flops200A ofFIG. 2Aand the multi-bit flip-flop200B ofFIG. 2B. In some embodiments, a cell includes a logic gate cell. In some embodiments, a logic gate cell includes an AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock cells, or the like. In some embodiments, a cell includes a memory cell. In some embodiments, a memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM), a read only memory (ROM), or the like. In some embodiments, a circuit element is an active element or a passive element. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), or the like, FinFETs, planar MOS transistors with raised source/drains, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. Examples of nets include, but are not limited to, vias, conductive pads, conductive traces, and conductive redistribution layers, or the like.

At clock tree synthesis (CTS) operation326, the APR tool performs CTS to minimize skew and/or delays potentially present due to the placement of circuit elements in the IC layout diagram. The CTS includes an optimization process to ensure that signals are transmitted and/or arrived at appropriate timings. For example, during the optimization process within the CTS, one or more buffers are inserted into the IC layout diagram to add and/or remove slack (timing for signal arrival) to achieve a desired timing. In some embodiments, operation326includes performing a timing analysis (similar to operation404of method400(shown inFIG. 4)) of one or more critical paths that include one or more multi-bit flip-flops to determine timing violations in the one or more critical paths. The described CTS of operation326is an example. Other arrangements or operations are within the scope of various embodiments. For example, in one or more embodiments, one or more of the described operations are repeated or omitted.

At routing operation328, the APR tool performs routing to route various nets interconnecting the placed circuit elements. The routing is performed to ensure that the routed interconnections or nets satisfy a set of constraints. For example, routing operation328includes global routing, track assignment and detailed routing. During the global routing, routing resources used for interconnections or nets are allocated. For example, the routing area is divided into a number of sub-areas, pins of the placed circuit elements are mapped to the sub-areas, and nets are constructed as sets of sub-areas in which interconnections are physically routable. During the track assignment, the APR tool assigns interconnections or nets to corresponding conductive layers of the IC layout diagram. During the detailed routing, the APR tool routes interconnections or nets in the assigned conductive layers and within the global routing resources. For example, detailed, physical interconnections are generated within the corresponding sets of sub-areas defined at the global routing and in the conductive layers defined at the track assignment. After routing operation328, the APR tool outputs the IC layout diagram including the power grid structure, placed circuit elements and routed nets. The described APR tool is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the described operations are omitted.

At sign-off operation330, one or more physical and/or timing verifications are performed. For example, sign-off operation330includes one or more of a resistance and capacitance (RC) extraction, a layout-versus-schematic (LVS) check, a design rule check (DRC) or a timing sign-off check (also referred to as a post-layout simulation). In some embodiments, other verification processes are performed.

In some embodiments, an RC extraction is performed, e.g., by an EDA tool, to determine parasitic parameters, e.g., parasitic resistance and parasitic capacitance, of components in the IC layout diagram for timing simulations in a subsequent operation.

In some embodiments, an LVS check is performed to ensure that the generated IC layout diagram corresponds to the design of the IC. Specifically, an LVS checking tool, i.e., an EDA tool, recognizes electrical components as well as connections in the space between the patterns of the generated IC layout diagram. The LVS checking tool then generates a layout netlist representing the recognized electrical components and connections. The layout netlist generated from the IC layout diagram is compared, by the LVS checking tool, with the schematic netlist of the design of the IC. If the two netlists match within a matching tolerance, the LVS check is passed. Otherwise, correction is made to at least one of the IC layout diagram or the design of the IC by returning the process to IC design operation310and/or APR operation320.

In some embodiments, a DRC is performed, e.g., by an EDA tool, to ensure that the IC layout diagram satisfies certain manufacturing design rules, i.e., to ensure manufacturability of the IC. If one or more design rules is/are violated, correction is made to at least one of the IC layout diagram or the design of the IC by returning the process to IC design operation310and/or APR operation320. Examples of design rules include, but are not limited to, a width rule which specifies a minimum width of a pattern in the IC layout diagram, a spacing rule which specifies a minimum spacing between adjacent patterns in the IC layout diagram, an area rule which specifies a minimum area of a pattern in the IC layout diagram, or the like.

In some embodiments, a timing sign-off check (post-layout simulation) is performed, e.g., by an EDA tool, to determine, taking the extracted parasitic parameters into account, whether the IC layout diagram meets a predetermined specification of one or more timing requirements. If the simulation indicates that the IC layout diagram does not meet the predetermined specification, e.g., if the parasitic parameters cause undesirable delays, correction is made to at least one of the IC layout diagram or the design of the IC by returning the process to IC design operation310and/or APR operation320. Otherwise, the IC layout diagram is passed to manufacture or additional verification processes.

In operation340, the integrated circuit is manufactured based on the layout diagram. In some embodiments, the layout diagram of method300includes layout diagram600B or layout diagram600D which are usable to manufacture the integrated circuit, such as one or more of MBFF100, circuit200A ofFIG. 2Aor circuit200B ofFIG. 2B. In some embodiments, the integrated circuit manufactured by operation340includes at least MBFF100, circuit200A ofFIG. 2Aor circuit200B ofFIG. 2B. In some embodiments, operation340of method300comprises manufacturing at least one mask based on the layout diagram, and manufacturing the integrated circuit based on the at least one mask. In some embodiments, operation340is performed by IC manufacturing system800(FIG. 8). In some embodiments, one or more of the above-described operations are omitted.

An additional verification process involves a multi-bit flip-flop (MBFF) power analysis350. In some embodiments, the MBFF power analysis350is performed by the APR tool or by another EDA tool. In some embodiments, the MBFF power analysis350is performed to determine the power consumed by at least one flip-flop in the multi-bit flip-flop, such as MBFF100, or at least one flip-flop in an integrated circuit, e.g., circuit200A-200B ofFIGS. 2A-2B. In some embodiments, the MBFF power analysis350is also configured to perform a timing analysis of at least one flip-flop in the multi-bit flip-flop, such as MBFF100, or at least one flip-flop in an integrated circuit, e.g., circuit200A-200B ofFIGS. 2A-2B. In some embodiments, the MBFF power analysis350is configured to optimize the power consumed by one or more flip-flops, such as MBFF100or circuit200A or200B ofFIG. 2A or 2B, while also passing a timing analysis of the flip-flops in the integrated circuit. In some embodiments, portions of method400ofFIG. 4are an embodiment of at least the MBFF power analysis350.

In some embodiments, MBFF power analysis350is part of a banking engine or a de-banking engine. In some embodiments, a banking engine is a portion of APR320that is configured to bank or group a plurality of flip-flops into one or more multibit flip-flops (MBFFs), as implemented by operation402of method400or shown byFIGS. 5A-5B. In some embodiments, a de-banking engine is a portion of APR320that is configured to de-bank or de-group one or more flip-flops in the one or more MBFFs into one or more flip-flops not part of the one or more MBFFs. In some embodiments, the banking or de-banking engine are part of other portions of IC design and manufacturing flow300. For example, in some embodiments, the banking or de-banking engine are part of IC design operation310. In some embodiments, the banking engine or de-banking engine are aware of the analysis performed by MBFF power analysis350.

In some embodiments, MBFF power analysis350is performed at the cell or block level. For example, MBFF power analysis350is performed for a region of the IC, instead of the whole IC. In at least one embodiment, a region of the IC includes a standard cell. In at least one embodiment, a region includes a group or a block of standard cells of the same or similar type or function, e.g., a block or group of MBFF cells, or a block or group of flip-flop cells, or the like. In at least one embodiment, a region includes a group or block of standard cells of different types or functions coupled together provide a function or module for the IC, e.g., a communication interface.

Other arrangements for dividing the IC into multiple regions for the MBFF power analysis350are within the scopes of various embodiments. For simplicity, in the detailed description of one or more embodiments herein, a standard cell or cell is used as an example of a region of an IC.

In some embodiments, MBFF power analysis350is performed at an early design stage. In at least one embodiment, MBFF power analysis350is performed between cell placement operation324and clock tree synthesis operation326, as indicated by arrow360inFIG. 3. In at least one embodiment, MBFF power analysis350is performed between clock tree synthesis operation326and routing operation328, as indicated by arrow370inFIG. 3. In at least one embodiment, MBFF power analysis350is performed between routing operation328and sign-off operation330, as indicated at arrow380byFIG. 3. In at least one embodiment, MBFF power analysis350is performed multiple times in IC design flow300, for example, at two or more stages indicated by arrows360,370,380. In at least one embodiment, sign-off operation330still includes an MBFF power analysis350at the system level despite the fact that MBFF power analysis350has been performed earlier after one or more of cell placement324, clock tree synthesis operation326or routing operation328. In at least one embodiment, MBFF power analysis350is performed to determine power optimization of at least one standard cell stored in one or more cell libraries325, as indicated by arrow390inFIG. 3. In some embodiments, cell library325includes an MBFF library720(shown inFIG. 7) that includes a number of MBFF standard cells.

As described herein, in some embodiments, MBFF power analysis350is performed to optimize the power consumed by one or more flip-flops, such as MBFF100or circuit200A or200B ofFIG. 2A or 2B, while also passing a timing analysis of the flip-flops in the integrated circuit. In some embodiments, an example of MBFF power analysis350is shown as method400ofFIG. 4. In some embodiments, MBFF power analysis350includes replacing a group of flip-flops with a banked MBFF having a plurality of flip-flops having different current driving abilities.

In some embodiments, by having different driving current capabilities, the corresponding flip-flops are able to switch states fast enough in order to pass timing tests or timing violations, but also do not consume additional power by being overdesigned by having a driving current capability more than needed in order to pass the timing tests or timing violations. Thus, one or more embodiments of the present disclosure are configured to optimize power and pass timing violations during the same operation, resulting in MBFFs that consume less power and occupy less area than other approaches. Furthermore, in some embodiments, one or more embodiments of the present disclosure are configured to optimize power and pass timing violations during the same operation resulting in a design and manufacturing flow300that includes less steps than other approaches that always de-bank flip-flops that are part of an MBFF that does not pass one or more timing violations.

FIG. 4is a flow chart of a method400, in accordance with some embodiments.

In at least one embodiment, method400corresponds to MBFF power analysis350, and is performed in whole or in part by a processor, such as processor702ofFIG. 7.

It is understood that additional operations may be performed before, during, and/or after the method400depicted inFIG. 4, and that some other processes may only be briefly described herein. It is understood that method400utilizes features of one or more of MBFF100ofFIG. 1, or circuits200A-200B of correspondingFIGS. 2A-2B. While the details of method400are described with respect to circuit elements, such as flip-flops or MBFFs, it is understood that the details of method400is applicable to circuit elements within a corresponding layout diagram, such as layout diagram500A-500B ofFIGS. 5A-5Bor layout diagrams600A-600D of correspondingFIGS. 6A-6D. For example, it is understood that method400utilizes features of one or more of layout diagrams500A-500B of correspondingFIGS. 5A-5B, or layout diagrams600A-600D of correspondingFIGS. 6A-6D.

In operation402of method400, a set of flip-flops501A (FIG. 5A) are banked or grouped into at least one MBFF (e.g., MBFF501B ofFIG. 5B) having a same driving current capability. In some embodiments, whether a set of flip-flops are banked or grouped into at least one MBFF100depends upon a number of criteria. In some embodiments, the criteria includes the proximity or distance between the flip-flops, whether the flip-flops share a same clock signal CLK, a same set signal S1, a same reset signal R1, a same scan enable signal SE1or the like, or share a same corresponding pin. In other words, in these embodiments, flip-flops that are located from each other by a distance that will result in delays in at least the clock signal CLK, the set signal S1, the reset signal R1, or the scan enable signal SE1will likely cause timing violations (described below in operation406) which will prevent the set of flip-flops from being banked or grouped into at least one MBFF501B. In some embodiments, operation402of method will attempt to bank or group as many flip-flops as possible into the at least one MBFF provided no timing violations occur. In other words, in some embodiments, the timing violations are at least one upper limit on the number of flip-flops that can be banked or grouped together. In some embodiments, the at least one MBFF of method400includes two or more flip-flops or corresponding bits. Other numbers of bits or corresponding flip-flops in MBFF are within the scope of the present disclosure.

In some embodiments, the set of flip-flops501A includes flip-flops502a,502b,502cand502d(FIG. 5A). Other numbers of flip-flops of the set of flip-flops501A are within the scope of the present disclosure. In some embodiments, the MBFF501B includes flip-flops502′,504′,506′ and508′ (FIG. 5B). Other numbers of flip-flops in MBFF501B are within the scope of the present disclosure.

In some embodiments, each of the flip-flops in the set of flip-flops501A or MBFF501B has the first driving current capability FF1. Other driving current capability for the set of flip-flops501A or MBFF501B is within the scope of the present disclosure. For example, in some embodiments, each of flip-flops in the set of flip-flops501A or MBFF501B has the second driving current capability FF0.

In operation404of method400, a timing analysis of each flip-flop502′,504′,506′,508′ in at least multi-bit flip-flop501B is performed. In some embodiments, operation404includes operation406. In some embodiments, the timing analysis of operation404includes determining if a timing event occurs outside of a clock period of a clock signal CLK. For example, in some embodiments, a timing violation occurs if one or more of flip-flops502′,504′,506′ and508′ do not transition from a first state to a second state within a clock period of clock signal CLK.

In operation406of method400, a determination is made if a timing violation occurs for each flip-flop502′,504′,506′,508′ in at least multi-bit flip-flop501B. In some embodiments, a timing violation occurs for a negative slack on a path having a flip-flop. In some embodiments, slack is a difference between an actual time and a desired time for a timing path having a flip-flop of MBFF501B. Thus, a negative slack occurs when the actual time is greater than the desired time for the corresponding timing path. Similarly, a positive slack occurs when the actual time is less than the desired time for the corresponding timing path. In some embodiments, if a positive slack is determined in operation406, then no timing violation occurs for the corresponding flip-flop in the corresponding timing path, the result of operation406is a “no”, and method400proceeds to operation412. In some embodiments, if a negative slack is determined in operation406, then a timing violation occurs for the corresponding flip-flop in the corresponding timing path, the result of operation406is a “yes”, and method400proceeds to operation410. In some embodiments, at least operation404or406is performed by a static timing analysis EDA tool.

In operation408of method400, a set of flip-flops in at least the multi-bit flip-flop501B are downsized or upsized. For example, as shown inFIG. 6B, set of flip-flops612of MBFF601B are downsized. For example, as shown inFIG. 6D, set of flip-flops610of MBFF601D are upsized. In some embodiments, operation408includes at least operation410, operation412, operation414or operation416.

In operation410of method400, a set of flip-flops610in at least the multi-bit flip-flop501B are upsized (e.g., shown in MBFF601D). In some embodiments, if a timing violation occurs in a path, for example the determination of operation406is “yes”, then method400will upsize the flip-flops that had a timing violation in attempting to remove the timing violation. In some embodiments, upsizing the flip-flops that had a timing violation includes increasing the driving current capability of the corresponding flip-flops thereby increasing the switching speed of the corresponding flip-flops. For example, as shown inFIG. 6D, set of flip-flops610of MBFF601D are upsized and have a third driving current capability FF2, while the driving current capability of set of flip-flops506′ and508′ are maintained at their previous driving current capability (e.g., FF1).

After operation410, method400returns to operation404to perform additional timing analysis. In some embodiments, the additional timing analysis performed in operation404is to determine if the upsized flip-flops still have timing violations or new timing violations.

In operation412of method400, a determination is made if flip-flops can be downsized. In some embodiments, if the determination of operation412is “yes”, then method400proceeds to operation414where a set of flip-flops512will be downsized. In some embodiments, if the determination of operation412is “no”, then method400proceeds to operation416. In some embodiments, if a previous set of flip-flops were upsized in operation410, and then operation406determined that the upsized flip-flops path had no timing violation, then the result of operation412for the upsized flip-flops is “no,” since the upsized flip-flops path should not be downsized as it was just previously upsized and did not include a timing violation.

In operation414of method400, a set of flip-flops512in at least the multi-bit flip-flop501B are downsized (e.g., shown as the set of flip-flops612in MBFF601B ofFIG. 6B). In some embodiments, if no timing violation occurs in a path, for example the determination of operation406is “no”, then operation414of method400will downsize the flip-flops that did not have a timing violation in attempting to save power. In some embodiments, downsizing the flip-flops that did not have a timing violation includes decreasing the driving current capability of the corresponding flip-flops thereby decreasing the switching speed of the corresponding flip-flops thereby reducing the dynamic power consumed by the corresponding flip-flops. For example, as shown inFIG. 6B, set of flip-flops612of MBFF601B are downsized and have the second driving current capability FF0, while the driving current capability of set of flip-flops502′ and504′ are maintained at their previous driving current capability (e.g., FF1).

After operation414, method400returns to operation404to perform additional timing analysis. In some embodiments, the additional timing analysis performed in operation404is to determine if the downsized flip-flops have timing violations. In some embodiments, if the downsized flip-flops now have timing violations, then the downsized flip-flops are returned to their previous size (e.g., with their previous driving current capability).

In operation416of method400, a determination is made if more or additional flip-flops are available in the at least one MBFF (e.g., MBFF501B ofFIG. 5B) or the banked set of flip-flops. In some embodiments, if the determination of operation416is “yes”, then method400returns to operation404where additional timing analysis is performed on the additional flip-flops that are banked in the set of flip-flops512or additional timing analysis is performed for other critical paths having a corresponding flip-flop in the at least one MBFF. In some embodiments, if the determination of operation416is “no”, then method400proceeds to operation418.

In operation418of method400, a determination is made if more flip-flops are available in the layout diagram, such as layout diagram500A, that were not part of the at least one MBFF. In some embodiments, operation418further includes a determination if additional flip-flops were added to the layout diagram, such as layout diagram500A. In some embodiments, if the determination of operation418is “yes”, then method400proceeds to operation402where method400will attempt to bank the additional flip-flops into the at least one MBFF or into other MBFFs. In some embodiments, if the determination of operation418is “no”, then method400proceeds to operation420.

In operation420, method400is in an idle state. In some embodiments, the idle state corresponds to method400waiting for an update from one of the parameters of operations402-420. In some embodiments, method400remains in the idle state until additional flip-flops are added to the layout diagram, such as layout diagram500A. In some embodiments, if additional flip-flops are added to the layout diagram, such as layout diagram500A, then operation420may return (not shown inFIG. 4) to operation418. In some embodiments, the idle state of operation420may include the end of method400.

In some embodiments, at least operation402,404,406,408,410,412,414,416,418or420is performed by an EDA tool, such as system700ofFIG. 7.

In some embodiments, at least one method(s), such as method300or400discussed above, is performed in whole or in part by at least one EDA system, including system700. In some embodiments, an EDA system is usable as part of a design house of an IC manufacturing system800ofFIG. 8.

In some embodiments, one or more of the operations of method400is not performed. While method400was described above with reference toFIGS. 1, 2A-2B, it is understood that method400utilizes the features of one or more ofFIGS. 5A-5B & 6A-6D. In some embodiments, other operations of method400would be performed consistent with the description and operation of layout diagrams500A-500B &600A-600D of correspondingFIGS. 5A-5B & 6A-6D.

Furthermore, in some embodiments, one or more embodiments of the present disclosure are configured to optimize power and pass timing violations during the same operation resulting in a method400that includes less steps than other approaches that always de-bank flip-flops that are part of an MBFF that does not pass one or more timing violations.

Examples of Method400

FIGS. 5A-5Bare schematic views of layout diagrams500A-500B of flip-flops before and after modifications, in accordance with some embodiments. The modifications are made as part of method400described with respect toFIG. 4.

FIG. 5Ais a schematic view of a layout diagram500A of a set of flip-flops, e.g., set of flip-flops501A, before execution of operation402of method400ofFIG. 4.

The set of flip-flops501A includes flip-flops502a,502b,502cand502d. Other numbers of flip-flops of the set of flip-flops501A are within the scope of the present disclosure. Each of the flip-flops502a,502b,502cand502dhas a corresponding inverter520a,520b,520cand520d, and a corresponding inverter522a,522b,522cand522d. In some embodiments, each of the flip-flops in the set of flip-flops501A has the first driving current capability FF1. Other driving current capability for the set of flip-flops501A is within the scope of the present disclosure. For example, in some embodiments, each of flip-flops in the set of flip-flops501A has the second driving current capability FF0.

FIG. 5Bis a schematic view of a layout diagram500B of a multi-bit flip-flop, e.g., MBFF501B, after execution of operation402of method400ofFIG. 4.

MBFF501B includes flip-flops502′,504′,506′ and508′ and inverters520a′ and522a′. Other numbers of flip-flops in MBFF501B are within the scope of the present disclosure. In some embodiments, each of the flip-flops in MBFF501B has a same driving current capability or the first driving current capability FF1. Other driving current capability for MBFF501B is within the scope of the present disclosure. For example, in some embodiments, each of flip-flops in MBFF501B has the second driving current capability FF0.

FIGS. 6A-6Dare schematic views of layout diagrams600A-600D of flip-flops before and after modifications, in accordance with some embodiments. The modifications are made as part of method400described with respect toFIG. 4.

FIG. 6Ais a schematic view of a layout diagram600A of a multi-bit flip-flop, e.g., MBFF501B, before execution of operation414of method400ofFIG. 4.

MBFF501B includes flip-flops502′,504′,506′ and508′. In some embodiments, each of the flip-flops in MBFF501B has a same driving current capability or the first driving current capability FF1. Set of flip-flops512includes flip-flops506′ and508′. Set of flip-flops512in multi-bit flip-flop501B are to be downsized in operation414of method400.

FIG. 6Bis a schematic view of a layout diagram600B of a multi-bit flip-flop, e.g., MBFF601B, after execution of operation414of method400ofFIG. 4.

MBFF601B includes flip-flops502′,504′,606and608. Set of flip-flops612includes flip-flops606and608. Set of flip-flops612were downsized in operation414of method400. In some embodiments, flip-flops502′ and504′ have a same driving current capability or the first driving current capability FF1. In some embodiments, flip-flops606and608have a same driving current capability or the second driving current capability FF0.

FIG. 6Cis a schematic view of a layout diagram600C of a multi-bit flip-flop, e.g., MBFF501B, before execution of operation410of method400ofFIG. 4.

MBFF501B includes flip-flops502′,504′,506′ and508′ and inverters520a′ and522a′. In some embodiments, each of the flip-flops in MBFF501B has a same driving current capability or the first driving current capability FF1. Set of flip-flops510includes flip-flops502′ and504′. Set of flip-flops510in multi-bit flip-flop501B are to be upsized in operation410of method400.

FIG. 6Dis a schematic view of a layout diagram600D of a multi-bit flip-flop, e.g., MBFF601D, after execution of operation410of method400ofFIG. 4.

MBFF601D includes flip-flops602,604,506′ and508′. Set of flip-flops612includes flip-flops606and608. Set of flip-flops610were upsized in operation410of method400. In some embodiments, the set of flip-flops610had timing violations in operation406, and therefore were upsized in order to overcome the timing violations of operation406, and also optimized the total clock dynamic power consumption of MBFF601D.

In some embodiments, flip-flops602and604have a same driving current capability or the third driving current capability FF2. In some embodiments, the third driving current capability FF2is greater than the first driving current capability FF1and the second driving current capability FF0.

In some embodiments, by having different driving current capabilities, the corresponding flip-flops of MBFF601B or601D are able to switch states fast enough in order to pass timing tests or timing violations, but also do not consume additional power by being overdesigned by having a driving current capability more than needed in order to pass the timing tests or timing violations. Thus, one or more embodiments of the present disclosure are configured to optimize power and pass timing violations during the same operation, resulting in MBFF601B or601D consuming less power and occupying less area than other approaches.

FIG. 7is a schematic view of a system700for designing an IC layout design, in accordance with some embodiments. In some embodiments, system700is at least a part of an EDA system. In some embodiments, system700includes an automated placement and routing (APR) system. In some embodiments, system700generates or places one or more IC layout designs described herein. In some embodiments, the IC layout designs ofFIG. 7includes at least layout diagrams500A-500B of correspondingFIGS. 5A-5Band layout diagrams600A-600D of correspondingFIGS. 6A-6D.

System700includes a hardware processor702and a non-transitory, computer readable storage medium704(shown inFIG. 7as “Memory704”) encoded with, i.e., storing, the computer program code706, i.e., a set of executable instructions. Computer readable storage medium704is configured for interfacing with manufacturing machines for producing the integrated circuit. The processor702is electrically coupled to the computer readable storage medium704via a bus708. The processor702is also electrically coupled to an I/O interface710by bus708. A network interface712is also electrically connected to the processor702via bus708. Network interface712is connected to a network714, so that processor702and computer readable storage medium704are capable of connecting to external elements via network714. The processor702is configured to execute the computer program code706encoded in the computer readable storage medium704in order to cause system700to be usable for performing a portion or all of the operations as described in method300or400.

In some embodiments, the processor702is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In some embodiments, the storage medium704stores the computer program code706configured to cause system700to perform method300or400. In some embodiments, the storage medium704also stores information needed for performing method300or400as well as information generated during performing method300or400, such as MBFF engine716, user interface718, MBFF library720, cell library722, MBFF power analysis724and layout diagram726, and/or a set of executable instructions to perform the operation of method300or400. In some embodiments, layout diagram726comprises one or more of layout diagrams500A-500B of correspondingFIGS. 5A-5Band layout diagrams600A-600D of correspondingFIGS. 6A-6D.

In some embodiments, the storage medium704stores instructions (e.g., computer program code706) for interfacing with manufacturing machines. The instructions (e.g., computer program code706) enable processor702to generate manufacturing instructions readable by the manufacturing machines to effectively implement method300or400during a manufacturing process.

System700also includes network interface712coupled to the processor702. Network interface712allows system700to communicate with network714, to which one or more other computer systems are connected. Network interface712includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, method300or400is implemented in two or more systems700, and information such as MBFF engine, user interface, MBFF library, cell library, MBFF power analysis and layout diagram are exchanged between different systems700by network714.

System700is configured to receive information related to a layout diagram through I/O interface710or network interface712. The information is transferred to processor702by bus708to determine a layout diagram for producing MBFF100, circuit200A or200B. The layout diagram is then stored in computer readable medium704as layout design726. System700is configured to receive information related to an MBFF engine through I/O interface710or network interface712. The information is stored in computer readable medium704as MBFF engine716. System700is configured to receive information related to a user interface through I/O interface710or network interface712. The information is stored in computer readable medium704as user interface718. System700is configured to receive information related to a MBFF library through I/O interface710or network interface712. The information is stored in computer readable medium704as MBFF library720. System700is configured to receive information related to a cell library through I/O interface710or network interface712. The information is stored in computer readable medium704as cell library722. System700is configured to receive information related to a MBFF power analysis library through I/O interface710or network interface712. The information is stored in computer readable medium704as MBFF power analysis724.

In some embodiments, method300or400is implemented as a standalone software application for execution by a processor. In some embodiments, method300or400is implemented as a software application that is a part of an additional software application. In some embodiments, method300or400is implemented as a plug-in to a software application. In some embodiments, method300or400is implemented as a software application that is a portion of an EDA tool. In some embodiments, method300or400is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout diagram of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the layout is generated based on a netlist which is created based on the schematic design. In some embodiments, method300or400is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system700. In some embodiments, system700a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, system700ofFIG. 7generates layout designs of an integrated circuit that are smaller than other approaches. In some embodiments, system700ofFIG. 7generates layout designs of integrated circuit structure that occupy less area and provide better routing resources than other approaches.

FIG. 8is a block diagram of an integrated circuit (IC) manufacturing system800, and an IC manufacturing flow associated therewith, in accordance with at least one embodiment of the present disclosure.

InFIG. 8, IC manufacturing system800includes entities, such as a design house820, a mask house830, and an IC manufacturer/fabricator (“fab”)840, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device860. The entities in system800are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house820, mask house830, and IC fab840is owned by a single larger company. In some embodiments, two or more of design house820, mask house830, and IC fab840coexist in a common facility and use common resources.

Design house (or design team)820generates an IC design layout822. IC design layout822includes various geometrical patterns designed for an IC device860. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device860to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout822includes various IC features, such as an active region, gate electrode, source electrode and drain electrode, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house820implements a proper design procedure to form IC design layout822. The design procedure includes one or more of logic design, physical design or place and route. IC design layout822is presented in one or more data files having information of the geometrical patterns. For example, IC design layout822can be expressed in a GDSII file format or DFII file format.

Mask house830includes data preparation852and mask fabrication844. Mask house830uses IC design layout822to manufacture one or more masks to be used for fabricating the various layers of IC device860according to IC design layout822. Mask house830performs mask data preparation852, where IC design layout822is translated into a representative data file (“RDF”). Mask data preparation852provides the RDF to mask fabrication844. Mask fabrication844includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by mask data preparation852to comply with particular characteristics of the mask writer and/or requirements of IC fab840. InFIG. 8, mask data preparation852and mask fabrication844are illustrated as separate elements. In some embodiments, mask data preparation852and mask fabrication844can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation852includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication844, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation852includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab840to fabricate IC device860. LPC simulates this processing based on IC design layout822to create a simulated manufactured device, such as IC device860. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout822.

It should be understood that the above description of mask data preparation852has been simplified for the purposes of clarity. In some embodiments, data preparation852includes additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout822during data preparation852may be executed in a variety of different orders.

After mask data preparation852and during mask fabrication844, a mask or a group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed in various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication844is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes.

IC fab840uses the mask (or masks) fabricated by mask house830to fabricate IC device860. Thus, IC fab840at least indirectly uses IC design layout822to fabricate IC device860. In some embodiments, a semiconductor wafer842is fabricated by IC fab840using the mask (or masks) to form IC device860. Semiconductor wafer842includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

One aspect of this description relates to an integrated circuit. In some embodiments, the integrated circuit includes a first flip-flop having a first driving capability, and a second flip-flop having a second driving capability different from the first driving capability. In some embodiments, the first flip-flop and the second flip-flop are part of a multi-bit flip-flop configured to share at least a first clock pin configured to receive a first clock signal. In some embodiments, the first driving capability is based on the first flip-flop having a first threshold voltage, and the second driving capability is based on the second flip-flop having a second threshold voltage. In some embodiments, the first threshold voltage is different from the second threshold voltage. In some embodiments, the first driving capability is based on the first flip-flop having a first number of fins, and the second driving capability is based on the second flip-flop having a second number of fins. In some embodiments, the first number of fins is different from the second number of fins. In some embodiments, the integrated circuit further includes a third flip-flop having the first driving capability or the second driving capability. In some embodiments, the third flip-flop is part of the multi-bit flip-flop and is configured to share the first clock pin with the first flip-flop and the second flip-flop. In some embodiments, the integrated circuit further includes a fourth flip-flop including a second clock pin configured to receive the first clock signal. In some embodiments, the fourth flip-flop has a third driving capability different from the first driving capability or the second driving capability. In some embodiments, the fourth flip-flop is not part of the multi-bit flip-flop. In some embodiments, the first flip-flop and the second flip-flop are configured to share at least a pin configured to receive a signal. In some embodiments, the signal includes at least an input signal, a set signal, a reset signal or a scan enable signal. In some embodiments, the pin includes at least an input pin, a set pin, a reset pin or a scan enable pin.

Another aspect of this description relates to a method of forming an integrated circuit. In some embodiments, the method includes generating, by a processor, a standard cell layout of the integrated circuit, and manufacturing the integrated circuit based on the standard cell layout. In some embodiments, the generating of the standard cell layout includes banking a first set of flip-flops into at least a first multi-bit flip-flop. In some embodiments, each flip-flop in the first multi-bit flip-flop has a first driving current capability. In some embodiments, the generating of the standard cell layout further includes performing a first timing analysis of each flip-flop in the first multi-bit flip-flop, and downsizing or upsizing a second set of flip-flops in at least the first multi-bit flip-flop. In some embodiments, the second set of flip-flops has a second driving current capability different from the first driving current capability. In some embodiments, downsizing or upsizing the second set of flip-flops in at least the first multi-bit flip-flop includes upsizing the second set of flip-flops in at least the first multi-bit flip-flop. In some embodiments, each of the flip-flops in the second set of flip-flops has a corresponding timing violation. In some embodiments, the generating of the standard cell layout further includes performing a second timing analysis of each flip-flop in the second set of flip-flops. In some embodiments, downsizing or upsizing the second set of flip-flops in at least the first multi-bit flip-flop includes downsizing the second set of flip-flops in at least the first multi-bit flip-flop. In some embodiments, each of the flip-flops in the second set of flip-flops does not have a corresponding timing violation. In some embodiments, the generating of the standard cell layout further includes performing a second timing analysis of each flip-flop in the second set of flip-flops. In some embodiments, the first driving current capability is based on the first set of flip-flops having a first threshold voltage, the second driving current capability is based on the second set of flip-flops having a second threshold voltage, and the first threshold voltage is different from the second threshold voltage. In some embodiments, the first driving current capability is based on the first set of flip-flops having a first number of fins, the second driving current capability is based on the second set of flip-flops having a second number of fins, and the first number of fins is different from the second number of fins.

Yet another aspect of this description relates to a system for designing an integrated circuit. In some embodiments, the system includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. In some embodiments, the processor is configured to execute the instructions for banking a first set of flip-flops into at least a first multi-bit flip-flop, performing a first timing analysis of each flip-flop in the first multi-bit flip-flop, and downsizing or upsizing a second set of flip-flops in at least the first multi-bit flip-flop. In some embodiments, each flip-flop in the first multi-bit flip-lop has a first driving current capability. In some embodiments, the second set of flip-flops has a second driving current capability different from the first driving current capability. In some embodiments, the processor is configured to execute instructions where the first driving current capability is based on the first set of flip-flops having a first threshold voltage, the second driving current capability is based on the second set of flip-flops having a second threshold voltage, and the first threshold voltage is different from the second threshold voltage. In some embodiments, the processor is configured to execute instructions where the first driving current capability is based on the first set of flip-flops having a first number of fins, the second driving current capability is based on the second set of flip-flops having a second number of fins, and the first number of fins is different from the second number of fins.

A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration purposes. Embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logical value of various signals used in the above description is also for illustration. Various embodiments are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. In various embodiments, a transistor functions as a switch. A switching circuit used in place of a transistor is within the scope of various embodiments. In various embodiments, a source of a transistor can be configured as a drain, and a drain can be configured as a source. As such, the term source and drain are used interchangeably. Various signals are generated by corresponding circuits, but, for simplicity, the circuits are not shown.

Various figures show capacitive circuits using discrete capacitors for illustration. Equivalent circuitry may be used. For example, a capacitive device, circuitry or network (e.g., a combination of capacitors, capacitive elements, devices, circuitry, or the like) can be used in place of the discrete capacitor. The above illustrations include exemplary operations or steps, but the steps are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.