Three dimensional memory array adjacent to trench sidewalls

A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to three dimensional memory cell array devices and methods for forming such devices.

2. Description of Related Art

Some metal-oxides can be caused to change resistance between two or more suitable ranges by application of electrical pulses at levels suitable for implementation in integrated circuits. Metal-oxides have generated interest in use in resistive random access memory (RRAM) devices because of their simple structure, compatibility with standard CMOS processes, high speed, low power consumption, and potential for 3D stacking.

Tungsten oxide WOxbased RRAM has been shown to exhibit good resistive switching characteristics between two or more resistance ranges. See, U.S. Pat. No. 7,800,094 entitled “Memory Devices Having an Embedded Resistance Memory with Tungsten Compound and Manufacturing Methods,” filed 12 Dec. 2007.

As the amount of required data storage increases, it is important to maximize the number of memory cells that can be formed within an array on a single substrate. One solution is to just create a larger die and add more memory cells along the horizontal plane in which the memory cells are formed. Another solution is to create a three dimensional structure, wherein memory cells are stacked on top of each other. While stacked memory cell arrays provide increased data storage on a die having the same footprint as a die of a memory cell array formed from a single layer of memory cells, it is difficult to ensure that strong electrical contact is made over the entire input and output surfaces of a memory element of each memory cell of the array between the memory cell and the bit line, and between the memory cell and the word line. This ensures that a maximum amount of current is passed through the memory cell during program and read operations.

Furthermore, ensuring that good electrical contact is made between the entire input and output surfaces of the memory element and the word and bit lines, involves the implementation of multiple additional masks and etching steps. Such additional masks and etching steps ensure that the contact conductor is uniformly deposited to make complete contact over the entire and input and output surfaces, but require numerous steps that add to manufacturing costs.

It is therefore desirable to provide a memory cell array of a stacked structure that ensures that good electrical contact is made over the entire surfaces of the memory element between of each memory cell of the array through an inexpensive and easily implemented self-aligning process.

SUMMARY OF THE INVENTION

Stacked memory cell array structures and methods for creating such structure are described. The memory cell array structures include memory elements that are formed adjacent to opposing sides of a conductive line that is formed within a trench. The memory elements are formed adjacent to opposing sides of the conductive line in a stacked configuration whereby one memory cell is disposed vertically on top of the other. An array of vertical connectors can be used to electrically couple the memory elements to the overlying circuitry. The overlying circuitry can include word lines coupled to the array of vertical connectors. In one embodiment the conductive line is a bit line. The memory cell array structure can include a drive device layer disposed between the conductive line and the memory elements to control the amount of current passing through the memory cells and allow for further selectivity control during array program and read operations.

The structure can be specifically applied to stacked memory cell array structures using RRAM memory cells. The RRAM memory cells can include a plurality of conductive pads that are disposed adjacent to the opposing sides of a conductive line. Each conductive pad includes a proximal side that corresponds to one of the opposing sides of the conductive line. The proximal side is proximal to the conductive line within a trench. A metal oxide memory element is formed on the proximal sides of the conductive pads, such that the metal oxide memory element is disposed between the conductive pads and the conductive line.

Such structure can include an oxide growth barrier layer formed within the trench in which the conductive line is formed, to prevent growth of the resistive metal oxide memory into the trench during oxidation. The oxide growth barrier layer also can provide a surface upon which the conductive line can be formed, thereby creating a strongly bonded electrical contact.

In one embodiment at least two of the plurality of conductive pads are stacked such that at least a first conductive pad is disposed above a second conductive pad, and the first conductive pad has a distal side that is disposed closer to the conductive line than the distal side of the second conductive pad, the distal sides of the first and second conductive pads in electrical communication with corresponding ones of the array of vertical connectors.

In one embodiment the plurality of conductive pads each include a metal layer between one of the metal oxide memory elements and one of the array of vertical connectors. An oxide of the metal layer is a resistive metal oxide memory element, such that the resistive metal oxide memory element is disposed on the proximal side of the metal layers in the conductive pads. In one embodiment the plurality of conductive pads further includes a plurality of barrier metal layers in which the metal layer is disposed between at least two of the metal barrier layers. In one embodiment the plurality of conductive pads further includes at least one field enhancement structures adjacent to proximal ends of the metal oxide memory elements proximal to the corresponding one of the first and second sidewalls of the trench. In one embodiment an oxide growth barrier layer is disposed between at least one of the metal oxide memory elements and one of the corresponding first and second sides of the conductive line. In one embodiment a drive device layer is disposed between at least one of the metal oxide memory elements and one of the corresponding first and second sides of the conductive line.

The method of forming such structure includes the following steps:

forming a plurality of levels of a plurality of conductive pads adjacent to a first and a second sidewall of a trench, the plurality of conductive pads having proximal sides proximal to a corresponding one of the first and second sidewalls of the trench;

forming a plurality of metal oxide memory elements on the proximal sides of the plurality of conductive pads;

forming a conductive line within the trench such that the conductive line is in electrical communication with the plurality of metal oxide memory elements; and

forming an array of vertical connectors that are in electrical communication with respective conductive pads in the plurality of levels.

The method can further include the step of depositing a drive device layer within the trench such that the drive device layer is disposed between the memory elements and the conductive line.

The method can be specifically applied to stacked memory cell array structures using RRAM memory cells. Such method can further include forming an oxide growth barrier layer within the conductive line trench before the step of oxidation.

Other embodiments are disclosed herein.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to theFIGS. 1-15.

The memory cell array stacked structure described herein is described with specific reference to resistive metal oxide memory cells. The description of the three dimensional memory cell architecture, however, is not limited solely to use in resistive metal oxide memory cells and can be used with various memory cell designs. Such various memory cell designs include but are not limited to phase change memory cells, magneto resistive memory cells or spin-transfer torque magneto resistive memory cells. Furthermore, the memory cell array stacked structure is not limited to just two memory cells stacked on top of each other and can be used to create a design of greater than two memory cells stacked on top of each other.

FIG. 1is a simplified block diagram of an integrated circuit110including a memory array112of memory cells having metal-oxide memory elements which can be operated as described herein. A word line decoder114having read, program, program verify and high voltage program retry modes is coupled to and in electrical communication with a plurality of word lines116arranged along rows in the memory array112. A bit line (column) decoder118is in electrical communication with a plurality of bit lines120arranged along columns in the array112for reading and programming the metal-oxide memory cells in the memory array112. The plurality of bit lines are formed from a plurality of conductive lines that are each formed within a trench and coupled to stacks of memory cells that are adjacent to the sides of each conductive line. Addresses are supplied on bus122to word line decoder and drivers114and bit line decoder118. Sense amplifiers and data-in structures in block124, including voltage and/or current sources for the read, program, program verify and high voltage program retry modes are coupled to bit line decoder118via data bus126. Data is supplied via a data-in line128from input/output ports on integrated circuit110, or from other data sources internal or external to integrated circuit110, to data-in structures in block124. Other circuitry130may be included on integrated circuit110, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array112. Data is supplied via a data-out line132from the sense amplifiers in block124to input/output ports on integrated circuit110, or to other data destinations internal or external to integrated circuit110.

A controller134implemented in this example using a bias arrangement state machine, includes logic which controls the application of bias circuitry voltage and current sources136for the application of bias arrangements described herein. Controller134may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller134comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller134.

FIG. 2is a schematic circuit diagram showing a portion of the circuit of the memory array ofFIG. 1. The circuit includes a three dimensional array of stacked memory cells including memory cells elements150-165. Each memory cell within opposing stacked structures, for example memory cells150,151,154and155, are individually connected to a common line166through a separate switching element167. Such switching element can be a diode that limits the passing of current through each memory cell150-165. The common line166is connected to a transistor168that controls the bias voltage that is applied along the common line166to each memory cell within the opposing stacked structures, for example memory cells150,151,154and155. Each transistor168is connected to a first common word line171and a first common bit line172. The common word line171is connected to a transistor169that is next to transistor168. The common bit line172is connected to another transistor170that is next to transistor168.

Each memory cell element150-165in this example array has a corresponding memory cell element in an adjacent opposing stacked structure of memory cell elements. For example memory cell element151corresponds to memory cell element153, memory cell element150corresponds to memory cell element152, memory cell element154corresponds to memory cell element156and memory cell element155corresponds to memory cell element157. Corresponding memory cell elements are connected to shared lines. For example corresponding memory cell elements150and152are connected to a first shared line173. In addition, corresponding memory cell elements151and153are connected to a second shared line174. Each shared line is also connected to the corresponding memory elements that are in the adjacent stacked structures. For example, corresponding memory cell elements154and156are connected to a third shared line175. The third shared line175is also connected to corresponding memory cell elements158and160in the adjacent stacked structures of memory cell elements. Such configuration allows for the control of applied bias voltages to allow for the selective reading and writing of memory cell elements150-165within the three dimensional array of stacked memory cell elements150-165.

FIG. 3shows a cross sectional view of a memory cell array stacked structure. The three dimensional memory cell array200includes a first memory cell202, a second memory cell220, a third memory cell203and a fourth memory cell205. The first memory cell202is formed on substrate204, adjacent to trench234. The substrate204can be any material that is suitable for forming a memory cell on top of the substrate, including but not limited to SiO2.

The first memory cell202includes a conductive pad that is adjacent to trench234. The conductive pad includes the metal layer210that is sandwiched between barrier metal layers212. Like materials, such as the top and bottom barrier metal layers212of the sandwich, are shown with like texture in the figures. The conductive pad has a proximal side207that corresponds to the sidewall of the trench234. The proximal side207is proximal to the trench234. The barrier metal layers212can be of any suitable barrier metal material, including but not limited to Co, Ru, Ta, TaN, InN, TuN or TiN. The barrier metal layers212serve to prevent the diffusion of material from the metal layer210and the resistive metal oxide memory element206during the operational lifecycle of the memory cell. The barrier metal layers212further have a sufficient conductivity to create good electrical contact to a via, thereby allowing the flow of current through the metal layer210and resistive metal oxide memory element during device operation.

The first memory cell202includes a resistive metal oxide memory element206. The resistive metal oxide memory element206is formed along the surface of a metal layer210on the proximal side207of the conductive pad. The metal layer210can be any metal material that is suitable for oxidizing to form a resistive metal oxide material layer. The metal layer210can be of any suitable material for forming a resistive metal oxide adjacent to, including but not limited to W, Ti, Ni, Al, Cu, Zr, Nb, Ta, TiN, Cr-doped SrZr, Cr-doped SrTi, PCM or LaCaMn. The resistive metal oxide memory element206can be of any resistive metal oxide material that changes resistivity as different voltages are applied and after a sufficiently high current passes through the element206. Such change in resistance is used to represent a bit in the storage of data. Such materials include but are not limited to WO, TiO, NiO, AlO, CuO, ZrO, NbO, TaO, TiNO, Cr-doped SrZrO3, Cr-doped SrTiO3, PCMO or LaCaMnO.

A second memory cell220is positioned above the first memory cell202in a stacked structure. Such stacked structure creates a three dimensional array of memory cells. Such three dimensional stacked structure allows for the creation of a memory array with a larger number of cells, than a memory array with the same planar footprint.

The second memory cell220can be of a similar design to the first memory cell202. Specifically, the second memory cell includes a conductive pad that is adjacent to a side of the trench234. The conductive pad has a proximal side221that corresponds to the sidewall of the trench. The pad includes metal layer224that is sandwiched between barrier metal layers226. A resistive metal oxide memory element222is formed from a metal layer224. The metal layer224can be fabricated from the same materials as the metal layer210of the first memory cell202. The barrier material layers226, as with the first memory cell serve to prevent diffusion of material out of the resistive metal oxide memory element222and the metal layer224, while still being electrically conductive for the formation of electrode contacts. The barrier metal layers226of the second memory cell220can be formed from the same materials that are used to form the barrier metal layers212of the first memory cell202.

The second memory cell220includes a resistive metal oxide memory element222that is formed along the surface of the metal layer224that is along the proximal side221of the conductive pad.

The first and second resistive metal oxide memory elements206and222include respective memory element surfaces214and230that make up a portion of the sidewall of the trench234. The resistive metal oxide memory elements206and222have opposite sides—one side of the resistive metal oxide memory elements206and222is the memory element surfaces214and230, and another side of the resistive metal oxide memory elements206and222contacts the metal layers210and224along the proximal sides207and221of the conductive pads. The memory element surfaces214and222are disposed such that the current that flows through the surfaces214and222, also flows directly into or out of the resistive metal oxide memory elements206and222.

The first memory cell202and second memory cell220are separated by a first isolation layer228. Such first isolation layer228is formed out of an insulator material in order to prevent the flow of current between the memory cells, thereby electrically isolating the first memory cell202from the second memory cell220. The insulator material that is used to fabricate the isolation layer228can be but is not limited to SiN. The isolation layer is positioned between the bottom surface of the second memory cell220and the top surface of the first memory cell202. The first isolation layer228covers substantially all of the bottom surface of the second memory cell220to ensure that current does not leak from the second memory cell220to the first memory cell202and vice versa during programming and reading of the first and second memory cells202220.

The stacked memory cell structure also includes a second isolation layer242that is positioned on top of the second memory cell220. The second isolation layer can be made of any insulator material, including but not limited to SiN. The second isolation layer242serves to electrically isolate the second memory cell220. In particular, the second isolation layer242electrically isolates the second memory cell220from the portion of the conductive line that overhangs and contacts the top of the second isolation layer242. This helps to ensure that during device read and program operations, current leakage into the second memory cell from rest of the memory cell array200is minimized.

The first memory cell202, the second memory cell220and the isolation layers228and242are stacked on top of each other such that the resistive metal oxide memory element contact interfaces214and230of the first and second memory cells are aligned in the same plane. The isolation layers228and242includes sides232and244that are also in the same plane as the memory element surfaces214and230, thereby forming part of a planar surface. Such planar surface has a position along the sidewall of a conductive line trench234. The previously mentioned surfaces214and230and isolation sides232and244are also along the same planar surface having a position along the sidewall of the trench234.

A stacked structure similar to the first and second memory cells202and220is formed adjacent to the opposing side of the trench234. Such stacked structure formed adjacent to the opposing side includes third and fourth memory cells203and205. The third and fourth memory cells can be of a similar structure as the first and second memory cells202and220. Such similar stacked structure includes memory element surfaces on the resistive metal oxide memory element of each memory cell that are along the proximal side of the conductive pads. The proximal side is proximal to the trench234. The trench234has opposite sidewalls—one adjacent to first and second memory cells202and220, and another adjacent to third and fourth memory cells203and205. The memory element surfaces of the third and fourth memory cells203and205are positioned along a sidewall of the trench234that is adjacent to third and fourth memory cells203and205.

A conductive line is formed within the trench234to provide an electrical contract to both the first and second memory cells202and220and the third and fourth memory cells203and205. The conductive line forms a common line for the memory cells202,220,203and205in the array during program and read operations. As discussed previously, the memory element surfaces of the memory cells202,220,203and205are positioned along the sidewalls of the trench234. Forming the conductive line within the trench such that the entire trench is filled, ensures that good electrical contact is made between the conductive line and the entire surface of each of the memory element surfaces of the memory cells202,220,203and205. Thus, the process of forming the conductive line within a trench is a self-aligning process. This self-aligning process does not use any additional masks or etching processes to ensure that good electrical contact is made across the entire memory element surface of each resistive metal oxide memory element of the memory cells202,220,203and205within the three dimensional stacked array. Such a self-aligning process reduces the manufacturing costs of such devices and the risk of manufacturing defects.

In the embodiment shown inFIG. 3, the conductive line includes a barrier metal layer238that is deposited on the bottom and sidewalls of the trench234, and includes a metal layer240. The barrier metal layer238can be formed from any of the previously mentioned barrier metal materials. The metal layer240is formed adjacent to the barrier metal layer238within the trench234. The metal layer240may comprise, for example, one or more elements selected from the group consisting of Ti, W, Yb, Tb, Y, Sc, Hf, Zr, Nb, Cr, V, Zn, Re, Co, Rh, Pd, Pt, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru and combinations thereof. The barrier metal layer238serves as an adhesion layer to create a surface to which the metal layer240can bond more easily. The barrier metal layer238extends out of the trench234and around the metal layer240on the top of the stacked memory cell structure to encapsulate the metal layer240. Thus the barrier metal layer238of the conductive line forms the surface on the top of the stacked memory cell structure, to which electrical contact is made during subsequent processing and packaging. The use of a barrier metal layer238further provides an adhesive surface, to which electrical contact is made during subsequent processing and packaging can bond more easily than the resistive metal oxide memory element contact interfaces214and230.

Each memory cell202,220,203and205includes a corresponding array of vertical connectors. The array of vertical connectors provides electrical contact to overlying circuitry. The array of vertical connectors includes a first memory cell back via236that extends through the second isolation layer242, the second memory cell220and the first isolation layer228to the top surface of the barrier metal layer212of the first memory cell202. The via236includes a conductive material that is used to make electrical contact to the first memory cell202. The electrode may comprise, for example, one or more elements selected from the group consisting of Ti, W, Yb, Tb, Y, Sc, Hf, Zr, Nb, Cr, V, Zn, Re, Co, Rh, Pd, Pt, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru and combinations thereof. Such electrical contact between the conductive material within the via236and the first memory cell202allows current to flow through the barrier metal layer212into the metal layer210and the resistive metal oxide memory element206. The via236can include an insulating layer that is formed along the sidewalls of the via236. The insulating layer ensures that the conductive material filled within the via236remains electrically isolated from the second memory cell220.

A second memory cell via246extends through the second isolation layer242to the top surface of the barrier metal layer226of the second memory cell220. A conductive material is formed within the second memory cell via246to create good electrical contact between overlying circuitry and the second memory cell220. Conductive material within the second memory cell via246may comprise, for example, one or more elements selected from the group consisting of Ti, W, Yb, Tb, Y, Sc, Hf, Zr, Nb, Cr, V, Zn, Re, Co, Rh, Pd, Pt, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru and combinations thereof. As with the first memory cell via236, forming the second memory cell via246down to the top of the barrier metal layer226creates electrical contact as current can flow from the electrode, through the barrier metal layer226and into the metal layer224and the resistive metal oxide memory element222.

The third and fourth memory cells203and205can include a vias that make electrical contact with overlying circuitry. Such vias of the third and fourth memory cells203and205can be of the same structure as the vias236and246of the first and second memory cells202and220.

The first and second memory cell resistive metal oxide memory elements206and222can include field enhancement layers248. As shown inFIG. 3, the field enhancement layers248have a material that is formed adjacent to the barrier metal layers212and226and covers a portion of the top and bottom horizontal surfaces of the first and second memory cell resistive metal oxide elements206and222. The field enhancement layers248may for example comprise TiNO, SiO2, HfO, TiO, AlO, WO, etc, and is preferably chosen so that the material of the field enhancement layers248has a higher resistance than that of the memory cell resistive metal oxide elements206and222.

FIG. 4shows a layout view of a memory array250using the stacked memory cell structure as described inFIG. 3with the formed electrodes. The memory array250includes at least memory cell stacked structures251,252,253,254,255and257. The memory cell stacked structures can be positioned in a staggered fashion, whereby the memory cell stacked structures are not directly across from each other on adjacent sides of the trench262, such that mirror symmetry does not exist along the axis of the trench262.

Each memory cell stacked structure includes a first back via256and a second back via258. The first and second back vias256and258are disposed such that the isolation layer242separates the first and second back vias256and258along the top surface, to ensure that the first and second back vias256and258are electrically isolated from each other. Such electrical isolation between the back vias256and258allows the memory cells within the memory cell stacked structure251,252,253,254,255and257to be programmed or read in selected groups. Within each memory cell structure251,252,253,254,255and257, the back vias256and258electrically couple each memory cell to overlying circuitry.

Each stacked memory cell structure251,252,253,254,255and257is coupled to a conductive line260. The conductive line260is formed within a trench262. As discussed previously, the memory element surfaces of the memory cells of each stacked memory cell structure form a portion of the sidewalls of the trench262. Depositing the conductive line260within such trench262, where the memory element surfaces make up a portion of the sidewalls, ensures that the conductive line260makes complete electrical contact with the entire memory element surfaces of the resistive metal oxide memory elements of each memory cell within each stacked memory cell structure251,252,253,254,255and257. Thus the formation of the conductive line260in the trench262is a self aligning process that does not require the use of additional masks to ensure that complete electrical contact is made with the resistive metal oxide memory elements. The conductive line260can serve as a common line during a read or programming operation. Such conductive line, in serving as a common line, can be coupled to overlying circuitry, shown inFIG. 1.

The conductive line260and each first back via256and second back via258are separated by the second isolation layer242along the top surface of the memory array250. The second isolation layer, as previously described, can be any material that is capable of electrically isolating the components of the memory array, including the conductive line260and each first memory cell back electrode258and second memory cell back electrode258.

FIG. 5shows a cross sectional view of an alternate embodiment of a stacked memory cell array structure300including an oxide growth barrier layer306. The stacked memory cell array structure300inFIG. 5includes a first memory cell302and second memory cell304. The memory cells302and304within the stacked structure can be resistive metal oxide memory cells of the same structure as previously described inFIG. 3. The conductive line of the stacked memory array structure described inFIG. 5, includes an oxide growth barrier layer306. The oxide growth barrier layer306is formed within the trench in a layer along the sidewall before the resistive metal oxide memory elements are formed.

The oxide growth barrier layer306allows oxygen atoms to diffuse through the oxide growth barrier layer306during the oxidation process while still maintaining a bulk stoichiometry similar to the as-formed oxide growth barrier layer306throughout oxidation and other material deposition and etching processes. Furthermore, the oxide growth barrier layer306serves to prevent the generation of roughness and defects during oxidation on the metal oxide memory element interfaces312that comprise a portion of the sidewall of the trench. The oxide growth barrier layer306is formed on the contact interface of the metal oxide memory element312, thereby limiting growth of the oxide memory element into the shared trench during the oxidation process. Limiting the metal oxide memory element contact interfaces312into the trench305, ensures that a strong electrical contact is created between the oxide barrier growth layer306, the conductive line and the resistive metal oxide memory elements of the first and second memory cells302and304. Finally, the oxide growth barrier layer306provides a surface upon which the conductive line can adhere to more easily than the memory element surfaces312, The conductive line can include a barrier metal layer308formed between the oxide growth barrier layer306and the metal layer310. This ensures that a strong electrical contact is formed between the resistive metal oxide memory elements and the conductive line.

The oxide growth barrier layer306can be any material that is capable of allowing oxygen atoms to diffuse through it during oxidation processes. Furthermore, such oxide growth barrier layer306must be capable of maintaining a bulk stoichiometry similar to the as-formed oxide growth barrier layer at elevated oxidation and processing temperatures, to help ensure that atoms from within the oxide growth barrier layer do not diffuse into the memory cells. Finally, such oxide growth barrier layer306is capable of conducting charge either as a conductor or as a dielectric in an applied electric field. Such electrical conductivity of the oxide growth barrier layer306ensures that sufficient current passes from the resistive metal oxide memory element through the oxide growth barrier layer306and into the conductive line during memory cell program and read operations. The oxide growth barrier layer306can be TiNO or any other material with the characteristics described in this paragraph.

FIG. 6is a layout view of a memory cell array described inFIG. 5with an oxide growth barrier layer within the conductive line trench before the conductive line is formed. The layout view is otherwise similar toFIG. 4.

A first oxidation barrier layer261and second oxidation barrier layer263are disposed along opposing sidewalls of the trench262. Such oxidation barrier layers261and263cover the surface of a respective one of the sidewalls of the trench262. The oxidation barrier layers261and263serve to limit growth of the metal oxide memory elements of each memory cell stacked structure251,252,253,254,255and257into the trench262during the oxidation process. Furthermore, the conductive line that is deposited within the trench262can adhere more easily to the oxide barrier layers261and263than to the surfaces of the metal oxide memory elements of each memory cell stacked structure251,252,253,254,255and257.

FIG. 7shows a cross sectional view of an alternate embodiment of a stacked memory cell array structure320with a drive device layer322. The stacked memory cell array structure320inFIG. 6includes a first memory cell324and second memory cell326. The memory cells324and326within the stacked structure can be resistive metal oxide memory cells of the same structure as previously described. The drive device layer322is formed within the trench321, along sidewalls of the trench321, such that it makes contact with the memory element surfaces328. In the embodiment shown inFIG. 6, a conductive line is formed within the trench, around the driven device layer322such that the driven device layer322is positioned directly between the memory element surfaces328and the conductive line. The conductive line, as in the illustrated embodiment, can include a barrier metal layer330and a metal layer332.

Alternatively, an oxide growth barrier layer can be positioned between the driven device layer322and the memory element surfaces328. The oxide growth barrier layer serves to limit the growth of the resistive metal oxide memory elements into the trench321during the oxidation process. Furthermore, the oxide growth barrier layer creates a surface upon which the drive device layer322can adhere to more easily during formation of the drive device layer.

The drive device layer322can be of any structure and material that is capable of regulating current in one direction through the memory cells of the stacked memory cell structure320. In one embodiment, a diode can be used to regulate the current through the memory cells. The diode can be of any diode structure and comprise any material that is suitable for making such diode structure. For example, the drive device layer322can be a metal oxide diode structure. Alternatively, the driven device layer322can be a tunneling diode structure. The drive device layer322serves to control the current within a given memory cell or group of memory cells, during read and program operations. Biasing the drive device layer322so that current flows through a given memory cell creates a selection mechanism whereby those memory cells with current flowing through them can then be read or programmed.

Through the use of the stacked memory cell structure320, wherein the memory element surfaces328make up a portion of a sidewall of the trench321, the drive device layer322is easily incorporated within the structure through a simple deposition process. Beyond ease of manufacturing, incorporating the drive device layer332along the sidewall of the stacked memory cell structure320helps to ensure that the entire memory element surfaces328make electrical contact with the drive device layer322.

FIG. 8is a layout view of a memory cell array as described inFIG. 7with a drive device layer within the conductive line trench before the conductive line is formed. The layout view is otherwise similar toFIG. 4.

A first drive device layer323and a second drive device layer325are formed along opposing sidewalls of the trench262before the conductive line is formed within the trench262. The drive device layers323and325are formed along opposing sidewalls of the trench262, and are disposed between the respective metal oxide memory elements of the memory cell stacked structures251,252,253,254,255and257and the conductive line that is formed within the trench262. The drive device layers323and325serve to control the current that flows through the metal oxide memory element of the memory cell stacked structures251,252,253,254,255and257by limiting the current that flows between the corresponding metal oxide memory elements and the conductive line.

FIGS. 9-15illustrate the steps in various methods for fabricating memory cell array structures of the previously described embodiments.FIG. 9shows a cross sectional view of the stacked structure after the deposition of the layers that form the memory cell array stacked architecture but before the etching steps. The stacked structure includes a plurality of conductive pad layers. The stacked structure is formed on top of a substrate400. The substrate400can be of any material suitable for forming a memory cell on top of such substrate. In the shown embodiment, the substrate400is SiO2. The substrate400can be of a dielectric material that does not conduct charge unless it is placed in an electric field.

The first memory cell is formed within a first conductive pad layer that includes a first memory cell stack of barrier metal layer402, metal404and barrier metal layer402. The barrier metal layers402and metal layer404can be of any of the previously mentioned materials. The metal layer404is preferably of a metal that as an oxide acts as a resistive metal oxide memory element. A first isolation layer406is formed on top of the first memory cell stack of first memory cell barrier metal layer402, metal layer404and barrier metal layer402. The first isolation layer406serves to isolate the memory cell that is formed with the first memory cell stack from the memory cell formed on top of the isolation layer406.

A second memory cell is formed within a second conductive pad layer that includes a second memory cell stack of barrier metal layer402, metal layer408and barrier metal layer402, that is deposited on top of the insulation layer406. The barrier metal layers402and metal layer408can be of the same materials that are used to form barrier metal layers402and metal layer404of the first memory cell stack. A second isolation layer410is deposited on top of the second memory cell stack. The second isolation layer410serves to electrically isolate the memory cells that are formed in the second memory cell stacks, from materials on top of the second isolation layer410. The first and second isolation layers406and410can be of any suitable material, as previously described, that is capable of electrically isolation the memory cells. In the shown embodiment, the isolation layers406and410are SiN.

FIG. 10is a cross sectional view of the stacked structure after formation of the trench412. After the conductive pad layers are deposited, as described inFIG. 9, a trench412is formed that extends to the substrate. The trench412is etched to the substrate layer though the conductive pad layers forming a plurality of conductive pads. The conductive pads are formed along adjacent sides of the trench412, wherein each conductive pad has a proximal side that corresponds to a side of the trench. More specifically, the trench412is formed by etching through the second isolation layer410, the second memory cell stack (which includes a stack of top barrier metal layer402, metal layer408, and bottom barrier metal layer402), the first isolation layer406, and the first memory cell stack (which includes a stack of top barrier metal layer402, metal layer404, and bottom barrier metal layer402). The trench412is formed by etching through such layers to the substrate material400such that the top surface of the substrate material400makes up the bottom of the trench412.

FIG. 11is a cross sectional view of the memory cell array of a stacked structure of an alternate embodiment after the step of depositing an oxide barrier growth layer414after forming the trench412. In this step, according to an alternate embodiment, an oxide growth barrier layer is formed within the trench412after the step of forming the conductive line trench412. As mentioned previously, the oxide growth barrier layer414serves to prevent the growth of the resistive metal oxide element into the shared trench412during the oxidation process. Furthermore, the oxide growth barrier layer414provides a surface upon which the conductive line that forms the common line or a driven device layer can bond to more easily than the memory element surface. The oxide growth barrier layer414can be deposited using any suitable method including chemical vapor deposition or physical vapor deposition. The oxide growth barrier layer414is deposited so that a layer is formed along the sidewalls of the trench412. The oxide growth barrier layer can be any material that is suitable for allowing oxygen atoms to diffuse through the oxide growth barrier layer during the oxidation process and for conducting charge out of the resistive metal oxide memory elements to the conductive line during memory cell program and read operations. As illustrated inFIG. 9, the oxide growth barrier layer is TiN.

FIG. 12is a cross sectional view of the memory cell array of a stacked structure after oxidation to form the resistive metal oxide memory elements416and418of the first and second memory cells. During the oxidation process the layers within the trench are oxidized such that a portion of the metal layers408and404are oxidized to form resistive metal oxide memory elements418and416. The oxidation step can occur with or without an oxide growth barrier layer414. The oxide growth barrier layer can be of a material that oxidizes such as in the illustrated embodiment, thereby forming an oxidized oxide growth barrier layer414. In the embodiment shown inFIG. 10the oxide growth barrier layer is TiN and oxidizes to form TiNOx. The resistive metal oxide memory elements416and418form resistive metal oxide memory element contact interfaces422and424through which current passes into and out of the resistive metal oxide memory elements422and424.

In the embodiment shown inFIG. 12, the step of oxidation also includes forming field enhancement layers420on a portion of at least one of the top and bottom horizontal surfaces of the resistive metal oxide memory elements416and418. The field enhancement layers420can be formed such that the resistive metal oxide memory elements416and418are sandwiched between such field enhancement layers420. The field enhancement layers are formed from a material with a low conductivity, so that the current that passes through barrier metal layers402is directed out of the barrier metal layers402and into the resistive metal oxide memory elements416and418. This increases the current within the resistive metal oxide memory elements, allowing for the achievement of suitable read and program current levels at lower overall memory array operational currents. In the illustrated embodiment, the field enhancement layers are formed by oxidizing a portion of the barrier metal layers402during the oxidation process. As illustrated, the field enhancement layers can be formed from a TiNO material. In an alternative embodiment, the field enhancement layers420are not formed.

FIG. 13is a cross sectional view of a memory cell array of the stacked structure after the alternate embodiment step of forming a drive device layer426within the trench after the step of oxidation. The drive device layer426can be formed through deposition after the first and second resistive metal oxide memory elements416and418are formed through oxidation. As discussed previously, the drive device layer426can be formed of any suitable material and structure that is capable of regulating the current through the resistive metal oxide memory elements416and418. For example, the drive device layer426can be either a metal-oxide diode or a tunneling diode. Furthermore, the drive device layer426can be formed with a structure that utilizes an oxide growth barrier layer such that the drive device layer426is deposited on top of the oxide growth barrier layer.

FIG. 14is a cross section view of the stacked structure of an alternate embodiment including an oxide growth barrier layer414after formation of the conductive common line within the trench415. The step of forming a conductive common line within the trench415can include depositing a barrier metal layer428and a metal layer430within the trench415. More specifically, a barrier metal layer428is deposited on top of the oxide growth barrier metal layer within the trench415. The remainder of the trench415is filled with a metal430, and a barrier metal layer428is deposited on top of the trench415so that the metal430is completely encapsulated by the barrier metal layer428. The barrier metal layer428and the metal430can be formed from any of the previously described barrier metal or metal materials. The conductive line can be formed with or without an oxide growth barrier layer414within the trench415or with or without a drive device layer within the trench415, or any combination of the two different embodiments.

FIG. 15is a cross sectional view of the stacked structure of an alternate embodiment structure without an oxide growth barrier layer or a drive device layer after the step of forming an array of vertical connectors which includes forming the first and second back vias432and434. The first back via432is formed by the steps of etching through the second isolation layer410, the second memory cell stack (which includes a stack of top barrier metal layer402, metal layer408, and bottom barrier metal layer402), and the first isolation layer406. The etch exposes the top surface of the first memory cell stack (i.e. the surface of the top barrier metal layer402of the first memory cell stack). The step of forming the first back via432further includes filling the via with a conductive material such that an electrical contact is formed with the overlying circuitry and the first memory cell. The step of forming the array of vertical connectors also can include the step of etching through the second isolation layer410so that a second back via434is formed that extends to the top barrier metal layer402of the second memory cell stack. The step of forming the second back via434includes filling the back via with a conductive material to make an electrical contact with the second memory cell. The first and second memory cell back vias are physically and electrically isolated from each other so that the memory cells can be selectively programmed and read. While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.