Method of forming a capacitor and method of manufacturing a semiconductor device using the same

A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.

PRIORITY STATEMENT

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2011-0035878 filed on Apr. 18, 2011 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

The inventive concept relates to a method of fabricating a capacitor and to a method of manufacturing a semiconductor device including a capacitor.

2. Description of the Related Art

As semiconductor devices become more highly integrated, the footprint of capacitors of the devices becomes smaller and yet the capacitors still must provide a high capacitance. One way in which a capacitor having a small footprint can nonetheless provide a high capacity is for the capacitor to have a high aspect ratio (a high ratio of height to width). In this respect, a capacitor having sides that are vertical (perpendicular) with respect to a substrate, on which the capacitor is formed, is desirable because the height of a capacitor is maximal when the sides of the capacitor are vertical.

Typically, a capacitor of a semiconductor device is fabricated by forming a mold layer of an oxide on a substrate, forming an opening in the mold layer, and then forming a storage electrode along the sides of the opening. However, the process used to at least initially form the opening in the mold layer often leaves the opening without vertical sides. In particular, the higher the aspect ratio of the opening, the more difficult it is to form vertical sidewalls that define the sides of the opening.

SUMMARY

According to an aspect of the inventive concept, there is provided a method of manufacturing a capacitor in which a mold layer, comprising silicon but excluding oxides of silicon, is form on a substrate, an opening is formed through the mold layer, a barrier layer is formed along the sides of the opening, a lower electrode is formed in the opening including over the barrier layer, the mold layer and the barrier layer are then removed, and a dielectric layer and an upper electrode are sequentially formed on the lower electrode.

According to another aspect of the inventive concept, there is provided a method of manufacturing a capacitor in which a mold layer comprising doped or undoped polysilicon is formed on an upper surface of a substrate, the mold layer is etched to form an opening through the mold layer, a barrier layer is formed along the sides of the opening, a lower electrode is formed in the opening including over the barrier layer, the mold layer and the barrier layer are subsequently removed, and a dielectric layer and an upper electrode are sequentially formed on the lower electrode.

According to another aspect of the inventive concept, there is provided a method of manufacturing a capacitor in which a transistor is formed at an upper portion of a substrate, an insulating interlayer is formed on the substrate over the transistor, a contact plug is formed through the insulating interlayer, at least one mold layer comprising silicon but excluding oxides of silicon is formed on the insulating interlayer and the contact plug, an opening is formed through the at least one mold layer such that the opening exposes top surfaces of the contact plug and the insulating interlayer, a barrier layer is formed along the sides of the opening, a lower electrode is formed in the opening including over the exposed top surfaces of the contact plug and the insulating interlayer, and the barrier layer, then the mold layer and the barrier layer are removed, and a dielectric layer and an upper electrode are sequentially formed on the lower electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments and examples of embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the sizes and relative sizes and shapes of elements, layers and regions, such as implanted regions, shown in section may be exaggerated for clarity. In particular, the cross-sectional illustrations of the semiconductor devices and intermediate structures fabricated during the course of their manufacture are schematic. Also, like numerals are used to designate like elements throughout the drawings.

It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” or in contact with another element or layer, there are no intervening elements or layers present.

Furthermore, spatially relative terms, such as “upper,” and “lower” are used to describe an element's and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures. Obviously, though, all such spatially relative terms refer to the orientation shown in the drawings for ease of description and are not necessarily limiting as embodiments according to the inventive concept can assume orientations different than those illustrated in the drawings when in use.

Other terminology used herein for the purpose of describing particular examples or embodiments of the inventive concept is to be taken in context. For example, the terms “comprises” or “comprising” when used in this specification specifies the presence of stated features or processes but does not preclude the presence or additional features or processes.

A first embodiment of a method of forming a capacitor in accordance with the inventive concept will now be described with respect toFIGS. 1 and 7.

Referring first toFIG. 1, an insulating interlayer110is formed on a substrate100.

The substrate100is a semiconductor substrate. For example, the substrate100may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (Si—Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The substrate100may also be of material doped with n-type or p-type impurities.

The insulating interlayer110may be formed of an oxide such as silicon oxide. For example, the insulating interlayer110may be formed of at least one of boro-phosphor silicate glass (BPSG), undoped silicate glass (USG), and spin on glass (SOG). Accordingly, the insulating interlayer110may be formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

Additionally, a plug120is formed through the insulating interlayer110. For example, the insulating interlayer110is etched to form a hole (not shown) exposing a top surface of the substrate100, and a conductive layer is formed on the substrate100and the insulating interlayer110to such a thickness as to fill the hole. In this respect, the conductive layer may be formed of doped polysilicon or a metal by a CVD process, a PVD process, an atomic layer deposition (ALD) process or the like. Then the conductive layer may be planarized by a chemical mechanical polishing (CMP) process and/or an etch-back process until the upper surface of the insulating interlayer110is exposed and the plug120is left filling the hole.

Referring toFIG. 2, an etch stop layer130and a mold layer140are sequentially formed on the insulating interlayer110and the plug120.

The etch stop layer130may be formed of silicon nitride by a CVD process, a PVD process, an ALD process, or the like.

The mold layer140is formed of a silicon non-oxide material, e.g., amorphous silicon, amorphous silicon doped with impurities, polysilicon, or polysilicon doped with impurities. Thus, the mold layer140may be formed by a CVD process, a PVD process, or the like. The impurities that may be employed include carbon (C), boron (B), phosphorous (P), nitrogen (N), aluminum (Al), titanium (Ti), oxygen (O), and arsenic (As). In an example of this embodiment, the mold layer140has a thickness equal to or more than 1 μm.

Referring toFIG. 3, parts of the mold layer140and the etch stop layer130are removed to form an opening145exposing a top surface of the plug120. At this time, part of the top surface of the insulating interlayer110may be exposed by the opening145.

Specifically, a portion of the mold layer140may be dry etched to form the opening145, using a photoresist pattern (not illustrated) as an etching mask, until the etch stop layer130is exposed. As examples of such a dry etching process, the mold layer140is etched by an etching gas comprising hydrogen fluoride (HF), hydrogen bromide (HBr), tetrafluoromethane (CF4), hexafluoroethane (C2F6), trifluoromethane (CHF3), difluoromethane (CH2F2), methyl bromide (CH3Br), chlorotrifluoromethane (CClF3), trifluorobromomethane (CBrF3), carbon tetrachloride (CCl4), sulfur hexafluorid (SF6), chlorine (Cl2), or nitrogen trifluorude (NF3). Alternatively, the mold layer140may be wet etched, to form the opening145, by a solution of hydrogen fluoride (HF), ammonium hydroxide (NH4OH), potassium hydroxide (KOH), or sodium hydroxide (NaOH), for example, or a buffered oxide etch (BOE) solution.

The etch stop layer130is provided as a means to terminate this part of the etching process for forming the opening145. However, the exposed portion of the etch stop layer may be removed to complete the opening145. To this end, the etch stop layer130may be etched by an etching gas comprising monofluoromethane (CH3F), trifluoromethane (CHF3), tetrafluoromethane (CF4), hexafluoroethane (C2F6), or nitrogen trifluorude (NF3).

In any case, the opening145has substantially vertical sides, i.e., the sidewall of the mold layer140that defines the sides of the opening145is substantially perpendicular to the top surface of the substrate100, because the mold layer140is not formed of an oxide.

Referring toFIG. 4, a barrier layer is formed (not shown) on the substrate100to cover the top surfaces of the plug120and the insulating interlayer110exposed by the opening145and the sides of the opening145. Then the barrier layer is anisotropically etched to form a barrier layer pattern160on the sides of the opening145.

The barrier layer may be formed of at least one material selected from the group consisting of silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, silicon nitride, silicon oxynitride, silicon carbonitride, germanium oxide, germanium nitride, germanium oxynitride and germanium carbonitride. In this embodiment, the barrier layer pattern150is formed to a thickness of several angstroms or tens of angstroms. To these ends, the barrier layer may be formed by a CVD process, an ALD process, a molecular beam epitaxy (MBE) process, or the like

Referring toFIG. 5, a lower electrode160is formed on in the opening145, i.e., over the exposed top surfaces of the plug120and the insulating interlayer110and a sidewall of the barrier layer pattern150. Accordingly, the lower electrode is cup-shaped or cylindrical. The lower electrode160may be formed of a metal or a metal nitride on the substrate100. For example, a lower electrode layer may be formed of titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), tungsten (W), copper (Cu), titanium nitride, tantalum nitride, or tungsten nitride on the substrate. The lower electrode layer may be a conformal layer formed on the substrate100so as to not only cover the barrier layer pattern160, etc, but so as to cover the upper surface of the mold layer140, as well.

Additionally, a sacrificial layer pattern165may then be formed to fill the remaining portion of the opening145. In particular, the sacrificial layer pattern165may be formed of an oxide. Even more specifically, the oxide may be propylene oxide (PDX), phenyltriethoxysilane (PTEOS), boro-phosphoro silicate glass (BPSG), or phosphor silicate glass (PSG), for instance. Furthermore, the oxide as a sacrificial layer may be formed to such a thickness as to fill the remaining portion of the opening145and cover the lower electrode layer on the mold layer140.

Then a chemical mechanical polishing (CMP) process and/or an etch-back process may be performed to remove upper portions of the lower electrode layer and the sacrificial layer until a top surface of the mold layer140is exposed.

Alternatively, the lower electrode160is formed to fill the opening145(i.e., the sacrificial layer pattern165is not formed). In this case, the lower electrode160has the form of a pillar.

Referring toFIG. 6, the mold layer140, the sacrificial layer pattern165and the barrier layer pattern150are removed. In this process, the etch stop layer130may be removed together with the mold layer140, the sacrificial layer pattern165and the barrier layer pattern150. For example, the mold layer140, the sacrificial layer pattern165and the barrier layer pattern150are removed by a wet etching process.

Referring toFIG. 7, a dielectric layer170is formed on the insulating interlayer110to cover the lower electrode160, and an upper electrode180is formed on the dielectric layer170.

The dielectric layer170may be formed of silicon oxide, silicon nitride or a metal oxide having a high dielectric constant. Examples of the metal oxide that may be used include tantalum oxide, hafnium oxide, aluminum oxide, and zirconium oxide. These materials may be used alone or in combination. Furthermore, the dielectric layer170may be formed by a CVD process, a PVD process, an ALD process, or the like.

The upper electrode180may also be formed by a CVD process, a PVD process, an ALD process, or the like. Furthermore, the upper electrode180may be a blanket layer, like that shown inFIG. 7, or a relatively thin conformal layer having a uniform thickness.

In the above-described embodiment of a method of forming a capacitor in accordance with the inventive concept, the lower electrode160is formed on a barrier layer pattern so that the mold layer140and the lower electrode160do not contact each other. As a result, a metal silicide layer is not formed. Accordingly, the dielectric layer170may have a uniform thickness, unlike a dielectric layer formed on a metal silicide layer. Hence, a capacitor formed according to any of the methods described above may have all of those desirable characteristics provided by a uniformly thick upper electrode. Additionally, the dielectric layer170is readily formed because the opening145is not constricted by a metal silicide layer. Still further, the lower electrode160may have a vertical sidewall even at a high aspect ratio because the opening145, in which the lower electrode160is formed, is itself formed in a mold layer that is not an oxide.

Another embodiment of a method of forming a capacitor in accordance with the inventive concept will now be described with reference toFIGS. 8 to 13. The method is similar to that shown in and described with reference toFIGS. 1 to 7except for the forming of the barrier layer. Therefore, mainly only the differences between the embodiments will be described in detail hereinafter.

Referring toFIG. 8, an insulating interlayer110is formed on a substrate100, and a plug120is formed through the insulating interlayer110. Then, an etch stop layer130and a mold layer140are sequentially formed on the insulating interlayer110and the plug120.

Referring toFIG. 9, part of the mold layer140is removed to form an opening145.

Referring toFIG. 10, the mold layer140having the opening145therethrough is oxidized to form a barrier layer152on exposed surfaces of the mold layer140including a sidewall surface defining the sides of the opening145. As a result, the barrier layer152is of silicon oxide.

The oxidation process may be a radical oxidation process, an ozone-flushing process, a thermal oxidation process, or a dry oxidation process. For example, a radical oxidation process may be performed on the mold layer140to form silicon oxide having a uniform thickness on the sidewall and a top surface of the mold layer140. Such a radical oxidation process may be performed using a source gas including nitrogen or oxygen under a pressure of about 0.1 to about 1 torr. In this way, the barrier layer152of silicon oxide may be formed to a thickness of several angstroms or tens of angstroms, for example.

Referring toFIG. 11, the portion of the etch stop layer130exposed by the opening145is then removed to expose a top surface of the plug120. In this case, i.e., in the case of removing the exposed portion of the etch stop layer130after the oxidation process, an oxidation layer is not formed on the plug120.

In addition, the portion of the barrier layer152formed on the top surface of the mold layer140may be removed by an etching process. In this case, a barrier layer remaining on the sides of the opening145as a barrier layer pattern (not illustrated).

Referring toFIG. 12, a lower electrode160is then formed on the bottom of the opening145and sidewall of the barrier layer152, and a sacrificial layer pattern165may be formed on the lower electrode160to fill what remains of the opening145(or the lower electrode160may be formed to fill the opening145completely).

Referring toFIG. 13, the mold layer140, the sacrificial layer pattern165and the barrier layer152are removed. Then a dielectric layer170and an upper electrode180are sequentially formed on the insulating interlayer110to cover the lower electrode160.

Another embodiment of a method of forming a capacitor in accordance with the inventive concept will be described with reference toFIGS. 14 to 19. This embodiment is also similar to that shown in and described with reference toFIGS. 1 to 7except for the forming of the barrier layer. Thus, mainly only the differences between these embodiments will be described in detail hereinafter.

Referring toFIG. 14, an insulating interlayer110is formed on a substrate100, and a plug120is formed through the insulating interlayer110. Then an etch stop layer130and a mold layer140are sequentially formed on the insulating interlayer110and the plug120.

Referring toFIG. 15, part of the mold layer140is removed to form an opening145.

Referring toFIG. 16, the mold layer140having the opening145therethrough is then nitrided to form a barrier layer154on the sidewall of the mold layer140that defines the sides of the opening145and the top surface of the mold layer140. In this case, the barrier layer154comprises silicon nitride.

The nitridation process may be a plasma nitridation process using ammonia (NH3) or nitrogen (N2) as source gas, or a thermal nitridation process. As an example, the mold layer140may be formed of polysilicon and subjected to a plasma nitridation process using ammonia as source gas to form a layer of silicon nitride having a uniform thickness on the sidewall and top surface of the mold layer140. The source gas may be provided under a pressure of about 0.1 to about 1 torr. The resulting barrier layer154of silicon nitride may be formed to a thickness of several angstroms or tens of angstroms in this process.

Referring toFIG. 17, the exposed portion of the etch stop layer130may then be removed to expose the top surface of the plug120. In this way, a nitride layer is not formed on the plug120. Also, that portion of the barrier layer154which extends along the top surface of the mold layer140may be removed together with the exposed portion of the etch stop layer130. In this case, a barrier layer pattern156is formed on the sidewall of the opening145.

Referring toFIG. 18, a lower electrode160is then formed in the opening145. Furthermore, in the case in which the lower electrode160is formed as a conformal layer of conductive material, a sacrificial layer pattern165is formed on the lower electrode160to fill what remains of the opening145.

Referring toFIG. 19, the mold layer140, the sacrificial layer pattern165and the barrier layer pattern156are then removed. Again, with respect to this part of the method, the etch stop layer130may be removed together with the mold layer140, the sacrificial layer pattern165and the barrier layer pattern156.

Next, a dielectric layer170and an upper electrode180are sequentially formed on the insulating interlayer110to cover the lower electrode160.

A method of manufacturing a semiconductor device in accordance with the inventive concept will now be described in detail with reference toFIGS. 20 to 24.

Referring toFIG. 20, an isolation layer205is formed at the upper portion of a substrate200. In this example, the isolation layer205is formed by a shallow trench isolation (STI) process.

Next, a gate insulation layer, a gate electrode layer and a gate mask layer are sequentially formed on the substrate200. The gate insulation layer may be formed of silicon oxide or a metal oxide. The gate electrode layer may be formed of metal or doped polysilicon. The gate mask layer may be formed of silicon nitride. In any case, the gate insulation layer, the gate electrode layer and the gate mask layer are then patterned by a photolithography process to form a plurality of gate structures210each of which includes a gate insulation layer pattern212, a gate electrode214and a hard mask216sequentially stacked on the substrate200.

Impurities are then implanted into the substrate200using the gate structures210as an ion-implantation mask to form first and second impurity regions207and209at upper portions of the substrate200adjacent to the gate structures210. The first and second impurity regions207and209serve as source/drain regions of the transistors.

Furthermore, spacers218of silicon nitride, for example, may be formed on sidewalls of gate structures210.

Referring toFIG. 21, a first insulating interlayer220is then formed on the substrate200to cover the gate structures210and the spacers218. Part of the first insulating interlayer220is then removed to form first holes (not shown) exposing the impurity regions207and209. In this example, the first holes are self-aligned with the impurity regions207and209by the gate structures210and the spacers218.

A first conductive layer is formed on the exposed impurity regions207and209and the first insulating interlayer220to such a thickness as to fill the first holes. The first conductive layer may be formed of metal or doped polysilicon. The first conductive layer may then be planarized, until a top surface of the first insulating interlayer220is exposed, to form first and second plugs227and229electrically connected to the first and second impurity regions207and209, respectively. In this example, the first plug227serves as a bit line contact.

A second conductive layer (not shown) is formed on the first insulating interlayer220to contact the first plug227. The second conductive layer may be formed of metal or doped polysilicon. The second conductive layer is then patterned to form a bit line (not shown). Next, a second insulating interlayer230is formed on the first insulating interlayer220to cover the bit line. The second insulating interlayer230is then etched to form a second hole (not shown) exposing the second plug229. A third conductive layer is then formed on the second plug229and the second insulating interlayer230to such a thickness as to fill the second hole. The third conductive layer may be formed of metal or doped polysilicon. Furthermore, the third conductive layer is planarized by a CMP process and/or an etch-back process, until a top surface of the second insulating interlayer230is exposed, to form a third plug235filling the second hole. The second and third plugs229and235collectively serve as a capacitor contact.

In another example of this embodiment, the second plug229is not formed in the first insulating interlayer220. Rather, an opening is formed through the first and second insulating interlayers220and230to expose the second impurity region209, and the third plug235is formed in such an opening in contact with the second impurity region209. That is, in this example, the plug235serves as a capacitor contact alone.

Referring toFIG. 22, an etch stop layer240and mold layers250,270and290are sequentially formed on the second insulating interlayer230and the third plug235. The mold layers250,270and290may be formed of polysilicon or silicon doped with impurities. In the latter case, the impurities may be carbon (C), boron (B), phosphorous (P), nitrogen (N), aluminum (Al), titanium (Ti), oxygen (O), or arsenic (As).

Furthermore, supporting layer patterns260and280also are formed on the mold layers250and270, respectively, so as to extend between adjacent ones of the mold layers250,270and290. More specifically, a first supporting layer is formed on the first mold layer250, and the first supporting layer is patterned to form the first supporting layer pattern260. Likewise, a second supporting layer is formed on the second mold layer270, and the second supporting layer is patterned to form the second supporting layer pattern280. The supporting layer patterns260and280are formed of material having an etching selectivity with respect to the mold layers250,270and290, e.g., silicon oxide, silicon nitride, or silicon oxynitride.

As will become clearer from the description below, the supporting layer patterns260and280connect certain numbers of the capacitors to prevent the capacitors from leaning or collapsing once the mold layers are removed. In this example, three mold layers and consequently, two supporting layer patterns are formed; however, the method is not so limited as the number of supporting layer patterns (and thus, mold layers on which they are respectively formed) depends on the aspect ratio of the capacitors to be formed.

Referring toFIG. 23, portions of each of the first to third mold layers250,270and290, the first and second supporting layer patterns260and280and the etch stop layer240are removed to form an opening (not illustrated) exposing a top surface of the third plug235. Furthermore, a barrier layer is formed in the opening and in particular, along the exposed top surface of the third plug235and the sidewall that defines the sides of the opening. The barrier layer is then anisotropically etched to form a barrier layer pattern300along the sides of the opening. In this respect, the barrier layer may be formed by any of the embodiments ofFIGS. 1-19described above. In addition, the supporting layer patterns260and280are formed of material having an etching selectivity with respect to the barrier layer.

For example, the barrier layer may be formed of silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, etc. by a CVD process, an ALD process, or a molecular beam epitaxy (MBE) process.

Alternatively, the barrier layer may be formed of silicon oxide by an oxidation process, i.e., by oxidizing the mold layers250,270and290. Instead, the barrier layer may be formed of silicon nitride by nitriding the mold layers250,270and290. In either of these cases, as has been described above, the etch stop layer240is removed to expose the top surface of the third plug235after the barrier layer is formed. Accordingly, the silicon oxide or silicon nitride is not formed on the third plug235.

Referring still toFIG. 23, a cup-shaped or cylindrical lower electrode310is formed in the opening, i.e., on the exposed top surface of the third plug235and the sidewall of the barrier layer pattern300. Then, a sacrificial layer pattern315is formed to fill what remains of the opening.

More specifically, a lower electrode layer is formed conformally on the structure comprising the third plug235, the insulating interlayer230, the mold layers250,270and290and the supporting layer patterns260and280. A blanket sacrificial layer is then formed on the lower electrode layer to such a thickness as to fill the remaining portion of the opening. The lower electrode layer and the sacrificial layer are then planarized by a chemical mechanical polishing (CMP) process and/or an etch-back process, until a top surface of the third mold layer290is exposed, to form the lower electrode310and the sacrificial layer pattern315.

Alternatively, the lower electrode310may be formed to fill the opening completely. In this case, the lower electrode310has the form of a pillar.

Referring toFIG. 24, the mold layers250,270and290, the sacrificial layer pattern315and the barrier layer pattern300are removed. At this time, the etch stop layer240may be removed together with the mold layers250,270and290, the sacrificial layer pattern315and the barrier layer pattern300.

Next, a conformal dielectric layer320is formed on the second insulating interlayer230to cover the lower electrode310, and a blanket upper electrode330is formed on the dielectric layer320. Alternatively, a conformal upper electrode, i.e., a relatively thin upper electrode having a uniform thickness, is formed on the dielectric layer320.

Finally, embodiments of the inventive concept and examples thereof have been described above in detail. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments were described so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Thus, the true spirit and scope of the inventive concept is not limited by the embodiment and examples described above but by the following claims.