Semiconductor structure preparation method, semiconductor structure and semiconductor memory

Provided are a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed on a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface.

BACKGROUND

With the continuous development of the semiconductor technology, the structure of semiconductors becomes more and more complex. The same substrate is often divided into areas with different functions as required, and longitudinal structures of each area are different. Therefore, there is a height difference between semiconductor structures in each area, which brings difficulties to the processing of an integrated circuit.

In a semiconductor structure with a high-k metal gate (HKMG), the longitudinal structure becomes more complicated, and the height difference between the areas is enlarged. During processing, the surface structure of some areas of the semiconductor may be excessively eliminated, resulting in the risk of depression.

SUMMARY

The present disclosure relates, but is not limited, to a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory.

The embodiments of the present disclosure provide a method for preparing a semiconductor structure, which may include the following operations.

An initial semiconductor structure is formed in a substrate.

The initial semiconductor structure is etched to form an array area structure and a peripheral area structure. Herein the array area structure and the peripheral area structure have different heights on the substrate; the peripheral area structure includes a peripheral area gate structure and the array area structure and the peripheral area structure respectively include a first dielectric layer.

An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates.

A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure.

The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface.

The embodiments of the present disclosure further provide a semiconductor structure, which is prepared by the method of the above solution.

The embodiments of the present disclosure further provide a semiconductor memory, which includes the semiconductor structure in the above solution.

DETAILED DESCRIPTION

For making the objectives, technical solutions, and advantages of the present disclosure clearer, the technical solutions of the disclosure will further be described below in combination with the drawings and the embodiments in detail. The described embodiments should not be considered as limits to the disclosure. All other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the disclosure.

“Some embodiments” involved in the following descriptions describes a subset of all possible embodiments. However, it can be understood that “some embodiments” may be the same subsets or different subsets of all the possible embodiments, and may be combined with each other without conflicts.

If the similar descriptions of “first/second” appear in the disclosure documents, the following descriptions will be added. Terms “first/second/third” involved in the following descriptions are only for distinguishing similar objects and do not represent a specific sequence of the objects. It can be understood that “first/second/third” may be interchanged to specific sequences or orders if allowed to implement the embodiments of the disclosure described herein in sequences except the illustrated or described ones.

Unless otherwise defined, all technological and scientific terms used in the present disclosure have the same meanings as those usually understood by those skilled in the art of the disclosure. The terms used in the present disclosure are only adopted to describe the embodiments of the disclosure and not intended to limit the disclosure.

In the process of manufacturing an integrated circuit, the same substrate is often divided into areas with different functions as required, and longitudinal structures of each area are different. Therefore, there is a height difference between semiconductor structures in each area. For example, the thickness of a gate oxide layer of a thin gate structure is less than that of a thick gate structure, and the thickness difference there between may be 30˜40 Å (Angstrom). Thus, the height of the thin gate structure may be 20˜30 Å less than that of the thick gate structure. In a semiconductor structure with a high-k metal gate (HKMG), the longitudinal structures become more complicated, and the height difference between the areas is enlarged, which may reach 12 nm (1 nm=10 Å). If the semiconductor structures with the height difference are processed directly, the semiconductor structures with lower height may be over-processed, resulting in the risk of depression.

FIG.1is an optional flowchart of a method for preparing a semiconductor structure according to an embodiment of the disclosure, which will be described with reference to the steps shown inFIG.1.

At S101, an initial semiconductor structure is formed in a substrate.

In the embodiment of the disclosure, the initial semiconductor structure may be firstly form on the substrate by a semiconductor device. The substrate is a wafer made of a semiconductor single crystal material, and usually is a single crystal silicon material.

FIG.2is a diagrammatic cross-section of the initial semiconductor structure according to an embodiment of the disclosure. As shown inFIG.2, the initial semiconductor structure200is formed on the substrate20. According to different implementation functions, the substrate20is divided into an array area21, an NMOS thin peripheral area22, a PMOS thin peripheral area23, an NMOS thick peripheral area24and a PMOS thick peripheral area25. The initial semiconductor structure on the array area21includes a third dielectric layer211, a conductive layer212and a first dielectric layer213. The initial semiconductor structure on the NMOS thin peripheral area22includes a gate oxide layer221, a high-k material layer222, a conductive layer223and a first dielectric layer224. The initial semiconductor structure on the thin PMOS peripheral area23includes a strained layer231, a gate oxide layer232, a high-k material layer233, a work function layer234, a conductive layer235and a first dielectric layer236. The initial semiconductor structure on the NMOS thick peripheral area24includes a gate oxide layer241, a high-k material layer242, a conductive layer243and a first dielectric layer244. The initial semiconductor structure on the PMOS thick peripheral area25includes a gate oxide layer251, a high-k material layer252, a work function layer253, a conductive layer254and a first dielectric layer255.

It is apparent that the initial semiconductor structures in different areas are not the same and have a height difference. For example, the initial semiconductor structures in the NMOS thin peripheral area22, the PMOS thin peripheral area23, the NMOS thick peripheral area24and the PMOS thick peripheral area25respectively include the high-k material layers222,233,242and252, and the initial semiconductor structure in the array area21does not. The initial semiconductor structures in the PMOS thin peripheral area23and the PMOS thick peripheral area25respectively include work function layers234and253, and the initial semiconductor structures in the array area21, the NMOS thin peripheral area22and the NMOS thick peripheral area24do not. The initial semiconductor structure in the PMOS thin peripheral area23includes the strained layer231, and other areas do not. The gate oxide layers241and251in the NMOS and PMOS thick peripheral areas24and25are thicker than the gate oxide layers221and232in the NMOS and PMOS thin peripheral areas22and23.

In addition, the structures or the materials of the conductive layers212,223,235,243, and254in different areas may be different, which will also result in differences of heights of the initial semiconductor structures in different areas.

In the embodiment of the disclosure, the operation that the initial semiconductor structure200is formed on the substrate20by a semiconductor device may be completed through the following processes.

First, after the gate oxide layers221,232,241and251are deposited, a high-k material is deposited on the third dielectric layer211of the array area21and the gate oxide layers221,232,241and251of the peripheral areas22,23,24and25. The high-k material on the third dielectric layer211is removed, thereby leaving the high-k material layers222,233,242and252of the peripheral areas22,23,24and25.

Then, a conductive material is deposited and processed on the third dielectric layer211of the array area21and the high-k material layers222,233,242and252of the peripheral areas22,23,24and25, thereby forming the conductive layers212,223,235,243and254of the array area21and the peripheral areas22,23,24and25.

Finally, the first dielectric layers213,224,236,244and255are deposited on the conductive layers212,223,235,243and254of the array area21and the peripheral areas22,23,24and25, thereby forming the initial semiconductor structure200.

In the embodiment of the disclosure, the deposition processes with a semiconductor device may be various processes such as diffusion, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., which is not limited here.

At S102, the initial semiconductor structure is etched to form an array area structure and a peripheral area structure. The array area structure and the peripheral area structure have different heights on the substrate. The peripheral area structure includes a peripheral area gate structure. The array area structure and the peripheral area structure respectively include a first dielectric layer.

In the embodiment of the disclosure, the initial semiconductor structure may be etched by a semiconductor device to form the array area structure and the peripheral area structure including the peripheral area gate structure. The array area structure and the peripheral area structure have different heights on the substrate. The array area structure and the peripheral area structure respectively include the first dielectric layer.

In the embodiment of the disclosure, before etching the initial semiconductor structure, it needs to form a mask layer and a patterned photoresist layer on the initial semiconductor structure by a semiconductor device.FIG.3is a diagrammatic cross-section after the mask layer and the patterned photoresist layer is formed, on the basis ofFIG.2. TakingFIG.3as an example, the mask layers311,321,331,341and351are formed by a semiconductor device on the first dielectric layers213,224,236,244and255in each area, and then the patterned photoresist layers312,322,332,342and352are formed on the mask layers311,321,331,341and351by a photo masking process, respectively. The mask layers311,321,331,341, and351are configured to cooperate with the formation of the photoresist layers312,322,332,342, and352, such as increasing the adhesion of photoresist and preventing photoresist from penetrating downward.

It is to be noted that the photoresist layers312,322,332,342and352are patterned and contain all plane pattern information of the semiconductor structures to be formed in subsequent processes in each area, so that the corresponding semiconductor structure can be manufactured in subsequent processes. For example, the photoresist layer312covers all the top sections of the array area21, and the respective photoresist layers322,332,342and352only cover the middle parts of the top sections of the peripheral areas22,23,24and25. Therefore, the semiconductor structures, formed in subsequent processes, of the array area21and the peripheral areas22,23,24and25are different.

The mask layers may be formed by diffusion, CVD, PVD, spin-on coating and other processes, and is not limited here.

In the embodiment of the disclosure, after the mask layers and the patterned photoresist layers are formed, the mask layers may be etched at least once by a semiconductor device based on the patterned photoresist layers to form the array area structure and the peripheral area structure.FIG.4is a diagrammatic cross-section after etching based onFIG.3. TakingFIG.4as an example, the array area21and the middle sections of the peripheral areas22,23,24and25are covered with the photoresist layers, and are protected by the photoresist layers. The parts covered by the photoresist layers remain, and the parts exposed by the photoresist layers are etched away. Hence, parts of the first dielectric layers224,236,244, and255, that are not covered by the photoresist layers322,332,342, and352, are etched away in subsequent etching processes, that is, parts of both sides of the sections of the peripheral areas22,23,24, and25, which are not protected by the photoresist layers322,332,342, and352, are etched away till the top of the substrate20. Thus, as shown inFIG.4, the peripheral area gate structure400is formed in the peripheral areas22,23,24and25.

It is to be noted that in the process of forming the peripheral area gate structure400by the semiconductor device, different recipe may be correspondingly employed for etching several times according to the materials of each layer in the peripheral areas22,23,24and25.

At S103, an isolation wall surrounding the peripheral area gate structure is formed on the substrate of the peripheral area structure.

In the embodiment of the disclosure, after the peripheral area gate structure is formed, the isolation wall, which surrounds the peripheral area gate structure on the substrate of the peripheral area structure, may be formed by a semiconductor device. The isolation wall is configured to insulate and protect the peripheral area gate structure.

In the embodiment of the disclosure, the structure of the isolation wall may be an N—O—N (SiN—SiO—SiN) structure, namely, a silicon nitride-silicon oxide-silicon nitride structure.FIG.5is a diagrammatic cross-section after the isolation wall is formed on the basis ofFIG.4. TakingFIG.5as an example, the isolation walls of the N—O—N structure surrounding the peripheral area gate structure on the peripheral areas22,23,24and25are formed. The isolation walls respectively include first silicon nitride layers521,531,541and551, silicon oxide layers522,532,542and552, and second silicon nitride layers523,533,543and553. The peripheral area gate structure may be surrounded with a semiconductor device by firstly depositing the first silicon nitride layers521,531,541and551; then depositing the silicon oxide layers522,532,542and552surrounding the first silicon nitride layers521,531,541and551; and at last, depositing the second silicon nitride layers523,533,543and553surrounding the silicon oxide layers522,532,542and552. Thus, the isolation wall of the N—O—N structure is formed.

In the embodiment of the disclosure, the deposition of the isolation wall may executed by a semiconductor device with any of various processes such as diffusion, CVD and PVD, which is not limited here.

At S104, a second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure.

In the embodiment of the disclosure, the second dielectric layer may be deposited on the peripheral area gate structure including the isolation wall and on the array area structure by a semiconductor device.

FIG.6is a diagrammatic cross-section after the second dielectric layer is deposited on the basis ofFIG.5. TakingFIG.6as an example, second dielectric layers611,621,631,641and651are deposited by a semiconductor device on the array area structure of the array area21and outside the isolation walls on the peripheral areas22,23,24and25. The second dielectric layers611,621,631,641and651may be used as consumable materials to protect the semiconductor structure below them in subsequent consuming processes, and as isolation areas among the areas to insulate the areas.

In the embodiment of the disclosure, the material of the second dielectric layer may be silicon oxide. The deposition of the second dielectric layer may be executed by a semiconductor device with any of various processes such as diffusion, CVD and PVD, which is not limited here.

At S105, the second dielectric layers, the first dielectric layers and the isolation wall are etched to form a semiconductor structure with a flat surface.

In the embodiment of the disclosure, the second dielectric layers, the first dielectric layers and the isolation wall may be etched by a semiconductor device to form the semiconductor structure with a flat surface, that is, the height of the structure of each area on the substrate is consistent and there is no depression.

In the embodiment of the disclosure, when the material of the first dielectric layer is silicon nitride, the material of the second dielectric layer is silicon oxide, and the isolation wall is the silicon nitride-silicon oxide-silicon nitride structure, the second dielectric layer, the first dielectric layer and the isolation wall may be etched by the semiconductor device in a manner that the etching rate ratio of silicon oxide to silicon nitride is 1:1. The etching rate ratio of silicon oxide to silicon nitride is 1:1, which means that the silicon nitride material and silicon oxide material are consumed at the same rate in the etching process. In this way, in the etching process, the second dielectric layer, the first dielectric layer and the isolation wall are consumed at the same rate, so that surfaces are always flush, and finally the semiconductor structure with a flat surface is formed.

In the embodiment of the disclosure, in order to achieve the etching rate ratio of silicon oxide to silicon nitride of 1:1, a specific recipe may be adopted for etching. The specific recipe may include the following operations. A first gas introduced into a reaction chamber at a first flow rate and a second gas introduced into the reaction chamber at a second flow rate are as an etching gas. In an environment of a first pressure and a first temperature, the etching gas is treated to form plasma. The second dielectric layer, the first dielectric layer and the isolation wall are etched for a first duration with the plasma. The first gas may be carbon tetrafluoride, and the first flow rate is 80-120 sccm (standard milliliter/minute); the second gas may be nitrogen, and the second flow rate is 180-220 sccm. The first pressure is 3-7 torr. The first temperature is 20-50 degrees centigrade, which goes downward in the first duration. The first duration is 20-40 seconds.

In the embodiment of the disclosure, due to the fact that there is a height difference between the structures of each area on the substrate, the lowest height of each area structure on the substrate may be taken as an etching endpoint by the semiconductor device, or the surface of the first dielectric layer in the array area structure may be taken as the etching endpoint by the semiconductor device, thus forming the semiconductor structure with a flat surface.FIG.7is a diagrammatic cross-section after etching is executed on the basis ofFIG.6. TakingFIG.7as an example, the surface of the first dielectric layer213in the array area21is taken as the etching endpoint in the semiconductor device, and the semiconductor structures in the peripheral areas22,23,24and25are etched to be flush with the etching endpoint.

It is to be understood that the peripheral area gate structure is formed in the semiconductor device first, and the second dielectric layer, the first dielectric layer and the isolation wall are deposited for protection, so that excessive elimination of a semiconductor surface structure can be avoided and the risk of depression is reduced. Meanwhile, the second dielectric layer, the first dielectric layer and the isolation wall are etched with a specific etching rate ratio, so that the surface of the formed semiconductor structure is guaranteed to be flat.

In some embodiments of the disclosure, S801shown inFIG.8is further included between S104and S105shown inFIG.1, which will be explained with reference to each step.

At S801, thinning processing is executed to the second dielectric layer to reduce the thickness of the second dielectric layer.

In the embodiment of the disclosure, before etching the second dielectric layers, the first dielectric layers and the isolation wall, thinning processing to the second dielectric layers may be also performed in a semiconductor device to reduce the thickness of the second dielectric layer. The thinning processing may be completed with a chemical mechanical polishing (CMP) process, which can make the surface of the second dielectric layer flatter.FIG.9is a diagrammatic cross-section after the thinning processing on the basis ofFIG.6. TakingFIG.9as an example, the thicknesses of the second dielectric layers611,621,631,641and651is reduced inFIG.9compared withFIG.6.

It is to be understood that the operation that the thinning processing is executed on the second dielectric layers before etching can save time and cost for subsequent etching.

In some embodiments of the disclosure, S102shown inFIG.1may be implemented with S1001to S1003shown inFIG.10, which will be explained with reference to each step.

At S1001, a mask layer is formed on the initial semiconductor structure.

In the embodiment of the disclosure, with a semiconductor device the mask layer may be formed on the initial semiconductor structure first. The mask layer is configured to cooperate with the formation of the photoresist layer, such as increasing the adhesion of photoresist and preventing photoresist from penetrating downward.

In the embodiment of the disclosure, the mask layer may be formed by diffusion, CVD, PVD, spin-on coating or any other processes, which are not limited here.

At S1002, the patterned photoresist layer is formed on the mask layer.

In the embodiment of the disclosure, the patterned photoresist layer on the mask layer may be formed by a photo masking process by a semiconductor device. The photoresist layer is patterned and includes all desired pattern information of the semiconductor structures to be formed in subsequent processes, so that the needed semiconductor structure can be manufactured in subsequent processes.

At S1003, the mask layer is etched based on the patterned photoresist layer to form the array area structure and the peripheral area structure.

In the embodiment of the disclosure, after the mask layer and the patterned photoresist layer are formed with the semiconductor device, the mask layer may be etched at least once based on the patterned photoresist layer to form the array area structure and the peripheral area structure.

In some embodiments of the disclosure, the material of a first dielectric layer includes silicon nitride, the material of a second dielectric layer includes silicon oxide, and the isolation wall includes the silicon nitride-silicon oxide-silicon nitride structure. Thus, when etching is executed at the etching rate ratio of silicon oxide to silicon nitride of 1:1, the first dielectric layer, the second dielectric layer and the isolation wall are consumed at the same rate, so that surfaces are always flush.

In some embodiments of the disclosure, the peripheral area gate structure at least includes a first NMOS structure, a first PMOS structure, a second NMOS structure and a second PMOS structure. The array area structure, the first NMOS structure, the first PMOS structure, the second NMOS structure and the second PMOS structure may all have different heights on the substrate. TakingFIG.4as an example, the first NMOS structure421is on the NMOS thin peripheral area22. The first PMOS structure431is on the PMOS thin peripheral area23. The second NMOS structure441is on the NMOS thick peripheral area24. The second PMOS structure451is on the PMOS thick peripheral area25. The array area structure411is on the array area21. The array area structure411, the first NMOS structure421, the first PMOS structure431, the second NMOS structure441and the second PMOS structure451may all have different heights on the substrate.

In some embodiments of the disclosure, S105inFIG.1may be implemented by S1051, which will be explained with reference to each operation.

At S1051, the lowest height on the substrate among the heights of the array area structure, the first NMOS structure including the isolation wall, the first PMOS structure including the isolation wall, the second NMOS structure including the isolation wall and the second PMOS structure including the isolation wall is taken as the etching endpoint to form the semiconductor structure with a flat surface.

In the embodiment of the disclosure, a semiconductor device may take the lowest height on the substrate among the heights of the array area structure, the first NMOS structure including the isolation wall, the first PMOS structure including the isolation wall, the second NMOS structure including the isolation wall and the second PMOS structure including the isolation wall as the etching endpoint to form the semiconductor structure with a flat surface.

In some embodiments of the disclosure, S105inFIG.1may be implemented by S1052, which will be explained with reference to each operation.

At S1052, the surface of the first dielectric layer in the array area structure is taken as the etching endpoint to form the semiconductor structure with a flat surface.

In the embodiment of the disclosure, the semiconductor device may take the surface of the first dielectric layer in the array area structure as the etching endpoint to form the semiconductor structure with a flat surface.

In some embodiments of the disclosure, S105inFIG.1may be implemented by S1053, which will be explained with reference to each operation.

At S1053, the second dielectric layer, the first dielectric layer and the isolation wall are etched at an etching rate ratio of silicon oxide to silicon nitride.

In the embodiment of the disclosure, the second dielectric layer, the first dielectric layer and the isolation wall may be etched with the etching rate ratio of silicon oxide to silicon nitride by a semiconductor device, so as to keep the surface of the semiconductor structure to be flat.

In some embodiments of the disclosure, S105inFIG.1may be implemented by S1054, which will be explained with reference to each operation.

At S1054, the second dielectric layer, the first dielectric layer and the isolation wall are etched for the first duration under an environment with a first pressure and a first temperature by using an etching gas including the first gas and the second gas. The first gas is introduced into a reaction chamber at the first flow rate, and the second gas is introduced into the reaction chamber at the second flow rate.

In the embodiment of the disclosure, a semiconductor device may introduce the first gas into the reaction chamber at the first flow rate and introduce the second gas into the reaction chamber at the second flow rate as the etching gas. Under the environment of the first pressure and the first temperature, the etching gas is subjected to plasma to form Plasma. The second dielectric layer, the first dielectric layer and the isolation wall are etched for the first time by using the plasma.

In some embodiments of the disclosure, the etching rate ratio of silicon oxide to silicon nitride is 1:1. In this way, when the first dielectric layer of the silicon nitride material, the second dielectric layer of the silicon oxide material and the isolation wall of the silicon nitride-silicon oxide-silicon nitride structure are etched in the semiconductor device, the surface of the semiconductor structure can be kept flat.

In some embodiments of the disclosure, the first gas includes carbon tetrafluoride, and the first flow rate is 80-120 standard milliliter/minute; the second gas includes nitrogen, and the second flow rate is 180-220 standard milliliter/minute; the first pressure is 3-7 torr, the first temperature is 20-50 degrees centigrade and shows a downward trend in the first time, which is 20-40 seconds.

In some embodiments of the present disclosure, the array area structure further includes a third dielectric layer. The peripheral area structure also includes a high-k layer and a gate oxide layer. The array area structure and the peripheral area structure respectively further include: a conductive layer. TakingFIG.4as an example, the array area structure411includes the third dielectric layer211. The peripheral area structures in the peripheral areas22,23,24and25respectively include the high-k material layers222,233,242and252and the gate oxide layers221,232,241and251. The array area structure411and the peripheral area structures also respectively include the conductive layers212,223,235,243and254formed by various conductive materials.

In some embodiments of the disclosure, the first PMOS structure further includes a work function layer and a strained layer, and the second PMOS structure further includes a work function layer. TakingFIG.4as an example, the first PMOS structure431is formed on the PMOS thin peripheral area23and further includes the work function layer234and the strained layer231. The second PMOS structure451is formed on the PMOS thick peripheral area25and further includes the work function layer253.

In some embodiments of the disclosure, the material of the conductive layer includes one or more of tungsten, titanium nitride, polysilicon or lanthanum oxide. The material of the third dielectric layers includes silicon nitride. The material of the gate oxide layer includes silicon oxide. The material of the work function layer includes alumina. The material of the strained layer includes silicon germanium.

It is to be noted that the conductive layers in different areas may have different structures or materials, which will also bring height differences to the initial semiconductor structures in different areas.

In some embodiments of the disclosure, the first dielectric layer is deposited by a heat treatment process. The second dielectric layer is a spin-on coating dielectric layer.

The embodiments of the disclosure further provide a semiconductor structure110, as shown inFIG.11. The semiconductor structure110is formed by the preparation method provided by the above embodiments. Accordingly, excessive elimination of the semiconductor surface structure can be avoided, and the risk of recess is reduced. Meanwhile, etching is executed with a specific etching rate ratio, so that the surface of the formed semiconductor structure110is guaranteed to be flat.

The embodiments of the present disclosure further provide a semiconductor memory120. As shown inFIG.12, the semiconductor memory120at least includes the semiconductor structure110shown inFIG.11.

In some embodiments of the disclosure, the semiconductor memory120shown inFIG.12at least includes a dynamic random access memory (DRAM).

It is to be noted that the terms “include”, “comprise” or any other variations thereof in the present disclosure are intended to cover a non-exclusive inclusion, such that a process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements that are not explicitly listed, or includes elements inherent to the process, method, article or device. Under the condition of no more limitations, it is not excluded that additional identical elements further exist in the process, method, article or device including the element and defined by a sentence “including a . . . ”.

The serial numbers of the embodiments of the disclosure are merely for description and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in several method embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain a new method embodiment. The characteristics disclosed in several product embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain a new product embodiment. The characteristics disclosed in the several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain a new method embodiment or device embodiment.

The above is only the specific embodiment of the present disclosure and not intended to limit the scope of protection of the present disclosure. Any changes or replacements apparent to those skilled in the art within the technical scope disclosed by the disclosure shall fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subjected to the scope of protection of the claims.

INDUSTRIAL PRACTICABILITY

The embodiments of the present disclosure provide a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed in a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. On the substrate where the peripheral area structure locates, an isolation wall surrounding the peripheral area gate structure is formed. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, a first dielectric layer and the isolation wall are etched to form a semiconductor structure with a flat surface. Thus, the peripheral area gate structure is formed first, and the second dielectric layer, the first dielectric layer and the isolation wall are deposited for protection, so that excessive elimination of the semiconductor surface structure can be avoided, and the risk of depression is reduced.