Packaging method

A packaging method includes ultrasonically bonding a semiconductor device and a substrate together via bumps that include gold as a main component thereof. A contact surface of a primary bump on a surface of an aluminum pad on one side of the substrate contacts and is ultrasonically bonded to a distal end surface of each opposed secondary bump on one side of the semiconductor device. An area of the contact surface is larger than that of the opposed distal end surface. By this method, damage to the substrate from the ultrasonic can be reduced without using a reinforcing layer.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and incorporates herein by reference Japanese Patent Application No. 2005-216944 filed on Jul. 27, 2005.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a packaging method.

2. Description of Related Art

A packaging structure is disclosed in, for example, JP-11-8270-A (corresponding to WO98/58409). In this structure, a substrate and a semiconductor device are placed in such a manner that one side of the substrate and one side of the semiconductor device are opposed to each other. Furthermore, a primary bump formed on a surface of a pad on the one side of the substrate, and a secondary bump formed on the one side of the semiconductor device, are ultrasonically bonded together. The primary bump and the secondary bump include gold as a main component thereof, and the pad includes aluminum as a main component thereof.

In the course of the ultrasonic bonding, ultrasonic energy is applied to the substrate underneath the pad. Therefore, to prevent damage to the substrate, a conventional packaging method by means of the ultrasonic bonding includes controlling ultrasonic bonding conditions such as amplitude, a load, oscillation time, and temperature.

However, when the substrate is friable, the range of ultrasonic bonding conditions under which the damage is prevented is narrowed down. Hence, a bonding method having the broader range of ultrasonic bonding conditions is demanded.

A certain semiconductor substrate, for example, a silicon IC substrate may be employed for the substrate underneath the pad having aluminum as a main component thereof. Such a substrate includes a friable insulating layer, which is made of a silicon oxide-insulating layer such as a dielectric interlayer. In the above case, particularly, the range of ultrasonic bonding conditions under which the damage is prevented becomes extremely narrow, and thus the substrate is difficult to be put to practical use.

In order to address such difficulty, the inventors of the present application have produced a substrate10experimentally shown inFIG. 8. The substrate10is an IC substrate that includes a silicon semiconductor substrate. At one side of the substrate10, an insulating layer12, which is made of, for example, a silicon dioxide film or the like, is formed. Furthermore, pads13are formed on the insulating layer12.

On a surface of each pad13, a primary bump31that includes gold as a main component thereof is formed respectively, by means of, for example, plating, a wire bonding method, or the like. A reinforcing layer200that includes a Ni—Au plating or the like is positioned between the pad13and the primary bump31. Through the intervention of the reinforcing layer200, a load imposed during the ultrasonic bonding on a material underneath the pad13can be mitigated, and accordingly, damage to the material underneath the pad13, for example, to the insulating layer12or the like, can be reduced.

Nevertheless, the intervention of the reinforcing layer200entails, for example, a process whereby the reinforcing layer200is formed, which may lead to an increase in the number of processes and in production costs.

SUMMARY OF THE INVENTION

The present invention addresses the above disadvantages. Thus, it is an objective of the present invention to provide a packaging method for ultrasonically bonding a semiconductor device and a substrate together via bumps including gold as a main component thereof, whereby damage to the substrate from the ultrasonic is minimized without using the reinforcing layer described above.

To achieve the objective of the present invention, there is provided a packaging method. According to the packaging method, a substrate, which includes a primary bump formed on a surface of a pad, is provided. The pad is formed on a dielectric layer on one side of the substrate. The primary bump includes gold as a main component thereof, and the pad includes aluminum as a main component thereof. Furthermore, a semiconductor device, which includes a secondary bump formed on one side of the semiconductor device, is provided. A size of a distal end contact surface area of the primary bump is larger than a size of a distal end contact surface area of the secondary bump. The substrate and the semiconductor device are positioned in such a manner that the distal end contact surface of the primary bump is opposed to and contacts the distal end contact surface of the secondary bump. The distal end contact surface of the primary bump and the distal end contact surface of the secondary bump are ultrasonically bonded together while the primary bump and the secondary bump are urged against each other and are thereby plastically deformed.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described with reference to the accompanying drawings. Additionally, the same numerals are used to indicate the same parts in the following description and drawings for the purpose of simplifying the description.

FIRST EMBODIMENT

FIG. 1is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a first embodiment of the present invention. A substrate10is, for example, a commonly used silicon IC substrate, on which transistors and other components are formed through a semiconductor process.

At one side11of the substrate10(i.e., the upper side of the substrate10inFIG. 1), a silicon oxide-insulating layer12is formed to serve as a dielectric interlayer. The insulating layer12is made as a silicon dioxide film or a film, which includes the silicon oxide and other element(s). For instance, the insulating layer12may include boron-doped phospho-silicate glass (BPSG).

Pads13that consist primarily of aluminum are formed on the insulating layer12. Each pad13may be made of aluminum alone or made of an aluminum alloy (aluminum content being about 90%). For example, each pad13may be made of Al or an Al—Si—Cu alloy. In the case of the Al—Si—Cu alloy, the Al content may be 99% or higher, and Si and Cu constitute the rest of the alloy.

Further, primary bumps31, which consist primarily of gold, are formed on the surfaces of the pads13, respectively, of the substrate10. Each primary bump31may include 100% gold or 99% or more gold. Furthermore, the primary bumps31are formed by a bump forming process employing a commonly used wire bonding method.

In addition, the region of the one side11of the substrate10except for that of the pads13is coated with a protective film14made of silicon nitride, polyimide, or the like.

The semiconductor device20may be a typical flip chip or an IC chip. Secondary bumps32which consist primarily of gold are formed on one side21of the semiconductor device20(i.e., the lower side of the semiconductor device20inFIG. 1).

Similar to the primary bumps31, each secondary bump32may include 100% gold or 99% or more gold. Furthermore, the secondary bumps32are formed by a bump forming process employing the commonly used wire bonding method.

The substrate10and the semiconductor device20are placed in such a manner that the one side11of the substrate10and the one side21of the semiconductor device20are opposed to each other. Furthermore, the primary bumps31and the secondary bumps32are bonded together by means of ultrasonic bonding to form metal connections therebetween. Thus, the substrate10and the semiconductor device20are mechanically and electrically connected via the bumps31,32.

With reference toFIG. 2, a packaging method for producing the packaging structure indicated inFIG. 1will be described.FIG. 2is a schematic cross-sectional view indicating the packaging method. InFIG. 2, the substrate10and the semiconductor device20having the bumps31,32respectively are opposed to each other.

InFIG. 2, the substrate10is held on a stage100of the ultrasonic bonding device by, for example, vacuum suction, and, the semiconductor device20is held by a tool110through, for example, vacuum suction.

Like similar other known ultrasonic bonding devices, the ultrasonic bonding device of the present embodiment can control the temperature of the stage100and the tool110to heat the substrate10and the semiconductor device20. Furthermore, the tool110can apply the ultrasonic to the semiconductor device20while applying a load on the semiconductor device20, as indicated by the arrows inFIG. 2.

Firstly, by way of photolithographic technique and a spattering method, the pads13are formed on the one side of the substrate10. Each pad13may have a thickness of about 0.7 μm (measured in the top-to-bottom direction inFIG. 2).

Next, the primary bumps31made of gold are formed on the surface of the pads13by means of the commonly used wire bonding method employing gold wire. Then, the free end of each primary bump31is planarized through plastic deformation, to form a planar surface31a. The planar surface31aforms a contact surface31a, which contacts a distal end surface32aof the opposed secondary bump32on the semiconductor device20.

FIG. 3depicts an exemplary method for forming the contact surface31aof the primary bump31planarized through the plastic deformation.

After the formation of the primary bumps31on the surfaces of the pads13, respectively, the ends of the primary bumps31are planarized through the plastic deformation by the tool110. In a state where the ultrasonic is not applied, the tool110imposes loads via a plate120of silicon, glass or the like, on the ends of the primary bumps31. The planarization process using the plastic deformation will be hereinafter referred to as a leveling process.

Furthermore, by means of the commonly used wire bonding method employing gold wire, the secondary bumps32made of gold are formed on the one side of the semiconductor device20. Each secondary bump32is opposed to each primary bump31of the substrate10. Like other commonly used bumps, the bumps31,32take generally cylindrical forms that taper towards the ends thereof, and are several tens of micrometers in height.

The contact surface31aof each primary bump31contacts the distal end surface32aof each opposed secondary bump32. Each primary bump31is formed in such a manner that an area of its contact surface31ais larger than that of the opposed distal end surface32a.

The primary bumps31having such contact surfaces31acan be formed by changing a diameter of the wire employed for bump formation. Furthermore, they can also be formed by changing loads applied to the bumps31at the time of performing the above leveling process (i.e., pressure of the tool110applied on bumps31).

In the present example, the area of the contact surface31aof each primary bump31is at least 1.4 times larger than that of the distal end surface32aof each secondary bump32. More specifically, although the areas are not limited to these values, the diameter d2(SeeFIG. 2) of the surface32amay be 60 μm, and the diameter d1(SeeFIG. 2) of the surface31amay be 70 μm or more.

The bumps31,32are formed on the substrate10and on the semiconductor device20respectively in this manner. As shown inFIG. 2, the substrate10and the semiconductor device20are secured to the stage100and to the tool110respectively. As a result, the one side11of the substrate10is opposed to the one side21of the semiconductor device20.

The semiconductor device20is brought close to the substrate10by the tool110to mount the semiconductor device20on the substrate10. While the semiconductor device20is being mounted on the substrate10, the contact surface31aof each primary bump31and the distal end surface32aof each opposed secondary bump32are kept in contact.

The bumps31,32are ultrasonically bonded together by the tool110applying the ultrasonic to the semiconductor device20. Meanwhile, the substrate10and the semiconductor device20are heated by the stage100and the tool110respectively. Consequently, as compared to those shown inFIG. 2, the ends of the bumps31,32are somewhat crushed to form metal connections, which results in the packaging structure as shown inFIG. 1.

In the present embodiment, the area of the contact surface31aof each primary bump31is larger than that of the distal end surface32aof each secondary bump32. The justification for this arrangement will be given below.

In one test case, the secondary bumps32are formed on the semiconductor device20, and the diameter d2of the distal end surface32aof each secondary bump32is adjusted to 60 μm. Then, four different substrates10(i.e., a first substrate to a fourth substrate) are produced. Through the leveling process, the diameter d1of the contact surface31aof the primary bump31on the first substrate10is adjusted to 60 μm (d2, PROCESSED inFIG. 4). The diameter d1of the contact surface31aof the primary bump31on the second substrate10is adjusted to 70 μm (d2+10, PROCESSED inFIG. 4). The diameter d1of the contact surface31aof the primary bump31on the third substrate10is adjusted to 80 μm (d2+20, PROCESSED inFIG. 4). Lastly, the diameter d1of the contact surface31aof the primary bump31on the fourth substrate10is adjusted to 90 μm (d2+30, PROCESSED inFIG. 4). Additionally, another substrate10is produced. The diameter d1of the contact surface31aof the primary bump31on this substrate10is adjusted to 60 μm without the leveling process (d2, UNPROCESSED inFIG. 4).

Then, the ultrasonic bonding is carried out for each sample. The ultrasonic bonding conditions are, amplitude: 2.8 μm, oscillation time: 0.3 seconds, a peak load: 4N/4 bumps, and temperature of the tool and the stage: 150° C.

After the ultrasonic bonding, each package is immersed in hydrochloric acid (approximately 35%, at the room temperature), so that the pads13on the substrate10are etched to expose the insulating layer12underneath to allow visual observation through a microscope. For each pad13of all sample packages, the insulating layer12is examined for damage from the ultrasonic bonding.

Cases where cracks and distortion of the insulating layer12are observed through the optical microscope are defined as damage occurrences. The distortion of the insulating layer12is represented by an interference pattern that is observed through the optical microscope. A ratio of the number of damaged pads13to the total number of the examined pads13is defined as a rate of damage occurrence (%). The results of the damage examination are plotted onFIG. 4.

FIG. 4shows the relationship between the diameter d1of one of the primary bumps31and the rate of damage occurrence. As indicated inFIG. 4, the rate of damage occurrence is reduced as the diameter d1becomes larger than the diameter d2of the distal end surfaces32aof the opposed secondary bump32. That is, as the area of the surface31abecomes larger than that of the surface32a, the rate of damage occurrence reduces.

Reduced stress on underneath the pad13may account for the above tendency. That is to say, by making the area of the surface31aof the primary bump31larger than that of the surface32a, the load that is imposed by the opposed secondary bump32during the bonding is dispersed over the contact surface31a. Thus, in order to achieve the effect of reducing the rate of damage occurrence, the area of the contact surface31aof the primary bump31should be larger than that of the distal end surface32aof the opposed secondary bump32.

Furthermore, according toFIG. 4, the rate of damage occurrence is approximately 0 when the diameter d1of the contact surface31aof the primary bump31is more than 10 μm larger than the diameter d2of the distal end surface32aof the opposed secondary bump32. This corresponds to the area of the surface31abeing more than approximately 1.4 times larger than that of the surface32a.

Therefore, the area of the contact surface31aof the primary bump31should be (preferably at least 1.4 times) larger than that of the distal end surface32aof the opposed secondary bump32. When the contact and the ultrasonic bonding between the bumps31,32are performed under this condition, the damage to the substrate10from the ultrasonic can be reduced without the above reinforcing layer.

Therefore, the present embodiment leads to a wider range of ultrasonic bonding conditions that the damage be prevented than the previously proposed art.

Moreover, as indicated inFIG. 4, the rate of damage occurrence for the case of the leveling processed sample is significantly reduced, as compared to the rate for the case of the sample without the leveling process. Since the contact surface31aof the primary bump31is planarized through the plastic deformation, the primary bump31may have been even less subject to the deformation while being ultrasonically bonded to the opposed secondary bump32.

The primary bump31is deformed as a result of the load imposed thereon during the ultrasonic bonding. Furthermore, the deformation of the primary bump31may cause partial stress concentration on the substrate10, which may render the damage to the substrate10more likely. Through the leveling process, a possibility of occurrence of the stress concentration can be reduced.

By making the area of the contact surface31aof the primary bump31larger than that of the distal end surface32aof the opposed secondary bump32, a contour of the surface31abecomes larger than that of the surface32a. For this reason, adjustment of relative positions of the bumps31,32is facilitated to restrain their misalignment.

With reference toFIG. 5, a tangible effect of restraining the misalignment will be described. The misalignment of the bumps31,32is observed X-ray fluoroscopically. The same samples and ultrasonic bonding conditions as employed inFIG. 4are applied to the observation.

When the amount of protrusion of one of the bumps from the other is 40 μm or more, such protrusion is defined as misalignment occurrence. As indicated inFIG. 5, the misalignment of the bumps31,32can be restrained by means of the present embodiment.

SECOND EMBODIMENT

FIGS. 6A and 6Bare schematic cross-sectional views that depict a method for packaging a semiconductor device according to the second embodiment of the present invention. In the present embodiment, the ultrasonic bonding is performed with a resin member40added to the first embodiment. InFIG. 6A, the tool110is omitted. The stage100and the tool110are also omitted inFIG. 6B.

Like in the first embodiment, primary bumps31are formed on one side of the substrate10, whereas secondary bumps32are formed on one side of the semiconductor device20by the packaging method in the present embodiment. Similarly, the area of a contact surface31aof each primary bump31is larger than that of a distal end surface32aof the opposed secondary bump32, which is also employed in the first embodiment.

Secondly, the semiconductor device20is mounted on the substrate10with each primary bump31and the opposed secondary bump32in contact, via a resin member (a resin material)40. The resin member40is made of nonconductive resin, and intervenes between the above bumps, as shown inFIG. 6A.

NCF (Non Conductive Film) serving as a nonconductive resin layer, which softens during the ultrasonic bonding, is employed as the resin member40. The member40is adhered to the one side21of the semiconductor device20, so that the secondary bumps32are covered in the member40.

Then, the resin member40is heated to be softened via the substrate10and the semiconductor device20by means of the stage100and the tool110. Simultaneously, using the tool110, the semiconductor device20is pressed on the substrate10. As a result, the bumps31,32are brought into direct contact, pushing away the softened member40from the location between the bumps.

In the above state, similar to the first embodiment, the ultrasonic is applied to the semiconductor device20with the substrate10and the semiconductor device20heated. In consequence, the bumps31,32are ultrasonically bonded together, and the packaging structure of the present embodiment is produced as shown inFIG. 6B. In this structure, metal connection is formed between the bumps31,32through the intervention of the resin member40.

Next, the justification for the ultrasonic bonding of the bumps31,32through the intervention of the resin member40therebetween will be provided below.

In one test case, the secondary bumps32are formed on the one side of the semiconductor device20. The diameter d2of each distal end surface32ais adjusted to 60 μm. The primary bumps31are formed on the one side of the substrate10. Through the leveling process, the diameter d1of each contact surface31ais adjusted to 80 μm.

Following this, the ultrasonic bonding is implemented for each sample, with and without the intervention of the resin member40. The ultrasonic bonding conditions are, the amplitude: 2.5-3.5 μm, the oscillation time: 0.2-0.5 seconds, the peak load: 6N/4 bumps, the temperature of the stage: 150° C., and the temperature of the tool: 130° C.

After the bonding, each sample package is immersed in fuming nitric acid (approximately 70-90° C.), so that the resin member40is dissolved and removed. Then, each sample is immersed in hydrochloric acid (approximately 35%, at the room temperature). Consequently, the pads13on the substrate10are etched to expose the insulating layer12underneath to allow visual observation through the microscope.

For each pad13of all sample packages, the insulating layer12is examined for the damage from the ultrasonic bonding. Similar to the first embodiment, the rate of damage occurrence (%) is employed for a measure of the damage. The results of the damage investigation are plotted onFIG. 7.

FIG. 7shows the damage occurrence under varied ultrasonic bonding conditions with and without the intervention of the resin member40. Severeness of the ultrasonic bonding conditions is controlled by the amplitude (μm) and the oscillation time (second). As the amplitude grows larger and the oscillation time longer, the conditions become severer, rendering the rate of damage occurrence larger.

As shown inFIG. 7, the damage occurrence to the substrate10is prevented under severer bonding conditions with, than without, the intervention of the resin member40. Two dashed lines inFIG. 7indicate approximate upper limits of the bonding conditions, under which the damage to the substrate10does not occur. The two dashed lines “without the resin member” and “with the resin member” indicate the approximate upper limits when the member40does not, and does intervene between the bumps, respectively.

Thus, the intervention of the resin member40enables the prevention of the damage to the substrate10under severer ultrasonic bonding conditions. Accordingly, the extent of feasible conditions can be expanded in a severer direction when the member40intervenes, as indicated with the above dashed line “with the resin member” inFIG. 7.

Therefore, in the present embodiment, the damage to the substrate10can be even more effectively controlled by employing the packaging method through the intervention of the resin member40. The member40may mitigate ultrasonic oscillation energy applied to the substrate10via the bumps31,32.

OTHER EMBODIMENTS

As described above, the bumps31,32are ultrasonically bonded together to form metal connections by the tool110applying the ultrasonic thereto. If possible, application of the ultrasonic can be stopped or reduced on completion of the bonding of the bumps31,32.

For instance, through monitoring a load (force) imposed on the tool110that holds the semiconductor device20, the ultrasonic oscillation is stopped or reduced at the moment when the load changes. In conventional ultrasonic bonding devices, since the oscillation time is controlled by setting it beforehand, the ultrasonic oscillation cannot be stopped even after the completion of the bonding, which has contributed to damage occurrences. Hence, by stopping or reducing the ultrasonic oscillation as soon as the bonding is completed, additional ultrasonic oscillation energy can be prevented from being applied to the substrate10, and the damage occurrences can be averted.

In the second embodiment, although film-like substances such as NCF are employed for the resin member40, the member40can be one of those formed through application of paste.

In the above embodiments, while the leveling process is performed by means of the tool110of the ultrasonic bonding device, the leveling process can alternatively be carried out with some device that can impose loads.

With respect to the formation of the bumps31,32, instead of the wire bonding method, plating by use of masks, for example, can be employed.

In the above embodiments, the substrate10includes the silicon oxide-insulating layer12underneath the pads13. The present packaging method can be applied to substrates not having such insulating layers.