Electronic devices and methods for forming the same

Electronic devices, such as those having a flexible substrate and printed material on the flexible substrate. In one embodiment, the printed material and substrate are part of an electronic device having at least three terminals, wherein the electronic device has a charge carrier mobility of at least 10 cm2/V-s. Multi-terminal devices can have a substrate including a doped semiconductor layer and at least two doped regions formed upon the substrate. The doped regions can be doped oppositely from the semiconductor layer and exhibit a charge carrier mobility of greater than 10 cm2/V-s. Methods for making the same are also disclosed.

FIELD OF THE INVENTION

This invention relates to electronic devices and methods for forming the same, and, in one exemplary embodiment, more particularly to printed transistors with high charge carrier mobility and methods for forming the same.

BACKGROUND OF THE INVENTION

Traditionally, transistor production requires a highly complex, cost intensive, prolonged process. Today, due to highly developed inkjet technologies, printed transistors overcome these drawbacks and provide fast, low-cost production with high transistor yields. In addition to overcoming the drawbacks of traditional transistors, these printed transistors may be applied to flexible substrates thus allowing them to be implemented in many technologies, such as active matrix flat panel displays, RFID tags, and Smart Cards. However, because printed transistors inherently possess a charge carrier mobility drastically less than traditionally formed transistors, they have not entirely replaced conventional transistors in today's markets.

Charge carrier mobility is defined as electron or hole diffusivity per volt (cm2/V-s) and is a measure of how fast charge moves through a given material when an electric field is applied. High charge carrier mobility in a transistor correlates to higher switching speeds and thus permits a transistor with high charge carrier mobility to be implemented in many applications and technologies. Printed transistors typically possess a charge carrier mobility of only around 0.01 to 1 cm2/V-s, while traditionally formed transistors have charge carrier mobilities of over 100 cm2/V-s.

Materials with higher charge carrier mobility than used in printed transistors typically require annealing. However, the annealing process has not been used for conventional printed transistors. Printing utilizes a flexible substrate, and conventional flexible substrates are not able to withstand the high temperatures utilized in the annealing process. Therefore, conventional printed transistors have been suited only for applications which permit slow switching speeds.

In many applications, multi-terminal electronic devices made from thin-film amorphous/polycrystalline semiconductive material, such as amorphous silicon, copper indium diselenide or cadmium telluride, have high charge carrier mobility. However, such materials typically require annealing, and typical substrates used in printing cannot withstand the high temperatures used in annealing. Therefore, other more expensive processes are utilized to produce such devices.

SUMMARY OF THE INVENTION

One aspect of the present invention is a method for forming an electronic device. The method comprises applying materials to a flexible substrate to form an electronic device, wherein at least some of the materials are applied using a printing apparatus. The substrate is annealed when at least some of the materials reside thereon.

Another aspect of the present invention is an electronic device, comprising a flexible substrate and printed material on the flexible substrate. The printed material and substrate are part of an electronic device having at least three terminals, wherein the electronic device has a charge carrier mobility of at least 10 cm2/V-s.

Yet another aspect of the present invention is a method of forming a multi-terminal device. The method comprises printing dopant on a substrate having a semiconductor layer to produce a plurality of doped regions within the substrate as part of a multi-terminal device. The doped regions provide a charge carrier mobility of greater than 10 cm2/V-s.

Another aspect of the present invention is a multi-terminal device. The multi-terminal device comprises a substrate, wherein the substrate includes a doped semiconductor layer; at least two doped regions formed upon the substrate. The doped regions are doped oppositely from the semiconductor layer and they exhibit a charge carrier mobility of greater than 10 cm2/V-s. The multi-terminal device further comprises first and second electrodes, each electrode either being electrically coupled to the doped regions and a third electrode electrically isolated from the doped semiconductor layer. Each of the electrodes are electrically isolated from another electrode. At least one of the electrodes or at least one of the doped regions is formed by using a printing apparatus.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In general, and as illustrated by the flow diagram inFIG. 1, one embodiment of the invention relates to printing a multi-terminal device with at least three terminals, such as a transistor, that has high charge carrier mobilities, such as in the range of 10 cm2/V-s to 100 cm2/V-s. While the illustrative embodiment demonstrates a transistor, other multi-terminal devices may be achieved, such as a thyristor, a three terminal voltage regulator, or a TRIAC. In this embodiment, a flexible semiconductor substrate is provided which can be both processed by a printing apparatus (e.g., a printer, a copier, a multi-functional device having printing functionality, such as a printer-copier-scanner, and the like) and annealed, and on which the multi-terminal device may therefore be printed. This is shown at block12.

The substrate may be composed of a variety of stratified layers used in semiconductor technologies, and may include a semiconductor layer on a flexible backing. As shown at block13, the substrate may be cut, such that recesses may be defined within the substrate to expose a portion of the semiconductor layer for forming the terminals. This cutting process may be achieved in numerous manners and may eliminate only a few layers from the substrate.

A dopant may be applied to the recesses and subsequently diffused so as to create doped areas with high charge carrier mobility within the semiconductor layer, as shown at blocks14and15. These dopants may be donor or acceptor impurities sufficient to increase charge carrier mobilities in a semiconductor. The dopants may be applied by using a printing apparatus, such as a thermal ink jet printer for example.

The diffusing operation can include an annealing step wherein the substrate with dopants is heated to high temperatures such as by using a furnace, or a pulsed laser beam. A dielectric material may be applied to the substrate in such a manner so as to coat the substrate while also providing apertures therethrough, as shown at blocks16and17ofFIG. 1. The dielectric may be applied selectively to form the apertures by use of a printing apparatus, such as a laser printer for example, or by blanket coating the dielectric and then laser cutting the apertures. The apertures can provide access to the dopant and gate areas for application of conductive material. Accordingly, the conductive material may be provided in the form of an electrode such that the conductive material is provided within the dielectric apertures and electrically connected to various areas of the substrate to form terminals, as shown at block18. This material can be applied using a printer. Thus, according to the method ofFIG. 1, an annealable and flexible substrate is processed using a printing apparatus to form a multi-terminal device which can have high charge carrier mobility.

As discussed further herein, and as shown generally inFIG. 2, a printer20may be implemented to print a multi-terminal device on a flexible, annealable substrate34. Printer20may employ an external CPU32(e.g., PC or laptop) to provide print commands to an internal controller42, and may comprise a print head22, a print head motor24, a feed roller26and a feed roller motor28. External CPU32may be utilized to control various aspects of the device to be printed, and, in combination with the controller41, to control various aspects of the printer such as material or ink selection, print head speed, indexing of the substrate34, and selective application of the materials to the substrate.

Print head motor24may be utilized to control print head22which may include nozzles for selectively applying material (e.g., ink, dopant, dielectric or conductive material) to the substrate along the same axis as print head carrier30. Feed roller26and feed roller motor28may be utilized to supply substrate34through printer20, along an axis perpendicular to print head carrier30. Print head motor24and feed roller motor28may work in concert such that any point on substrate34may be accessed by print head22, thereby facilitating formation of multi-terminal devices anywhere on substrate34.

More specifically, and as demonstrated in the illustrative embodiment, printer20may be an inkjet printer which may apply dopant, dielectric and/or conductive material to create a transistor on substrate34. In such an embodiment, printer20may be any thermal inkjet printer capable of ejecting fluid droplets, such as dopant, dielectric or conductive material, onto substrate34from thermal nozzles within inkjet print head22by heating the material using heaters, such as resistors35, and ejecting the material through nozzles37. It should be understood that although printer20is illustrated as a thermal inkjet printer, other printers are contemplated, such as a piezoelectric inkjet printer or a laser printer, and such printers may have a variety of components, such as disclosed in U.S. Pat. No. 6,234,612, the entire disclosure of which is hereby incorporated herein by reference. Additionally, it should be understood that if a thermal inkjet printer is employed, the fluids in print head22may be limited to fluids conducive to ejection from such print head22.

In one illustrative embodiment and as demonstrated inFIG. 3, a multi-terminal device may be printed upon a stratified substrate134. As illustrated, stratified substrate134may comprise layered surfaces such as a gate electrode layer36, an oxide layer38, a semiconductor layer40, and a base substrate42. A suitable stratified substrate134is commercially available as Iowa Thin Films product PowerFilm, such as disclosed in U.S. Pat. No. 5,385,848, the entire disclosure of which is hereby incorporate herein by reference. Various methods may be utilized for creating the substrate134. For example, the substrate134may be formed by roll coating amorphous silicon and other layers onto a flexible substrate by using a thin strip of stainless steel, so as to create an annealable and flexible product that can be processed by a printer. However, it should be understood that although stratified substrate134is illustrated as comprising four specific layers, each layer may comprise various materials and thicknesses depending upon the desired multi-terminal device or desired application.

Base substrate42may consist of a material having sufficient surface tension such that other layers of material may be applied thereupon. Base substrate42may also be durable enough to withstand the intense heat required during an annealing process. Although as illustrated, base substrate42may comprise stainless steel, other materials may be implemented to achieve the desired surface tension, flexibility, and/or durability, such as copper foil, or aluminum foil.

It is further demonstrated in the present embodiment that base substrate42may be a flexible material. While a material such as stainless steel may be thinly distributed to achieve flexibility, other substrates and/or thicknesses may be employed to achieve the desired rigidity or flexibility. Semiconductor layer40may be included within stratified substrate134and may comprise any material sufficient to achieve charge carrier mobilities in the range of 10 cm2/V-s to 100 cm2/V-s.

Although semiconductor layer40is illustrated in the present embodiment as an amorphous silicon layer, other semiconductor materials may be used, such as copper indium diselenide or cadmium telluride. Additionally, in order to achieve charge mobilities in the range of 10 cm2/V-s to 100 cm2/V-s, semiconductor layer40may be doped with a concentration of impurities. The impurity may either be a donor impurity, as demonstrated in the illustrative embodiment, such that an n-type semiconductor with excess holes may be formed, or the impurity or may be an acceptor impurity such that a p-type semiconductor with excess electrons may be formed.

Oxide layer38may be included within stratified substrate134and may comprise any material sufficient to electrically isolate semiconductor layer40from gate electrode layer36. Although oxide layer38is illustrated in the present embodiment as a silicon oxide layer, other electrically isolating materials may be used, such as silicon nitride, or diamond-like carbon. Gate electrode layer36may be included within stratified substrate134and may comprise any material sufficient to ensure electrical contact with conductive material. Although gate electrode layer36is illustrated in the present embodiment as a polysilicon layer, other materials may be used, such as tungsten or tantalum silicide. Accordingly, substrate134is flexible and annealable and can be processed using a printer to form electronic devices with high charge carrier mobility, according to embodiments of the present invention.

As illustrated inFIG. 4, recesses44,46may be formed within stratified substrate134. These recesses44,46may be implemented such that semiconductor layer40may be exposed and dopant may be applied therein. Because recess size and depth constraints may influence the overall performance of a multi-terminal device, the illustrative embodiment demonstrates that recesses44,46may be formed via laser cutting. However, alternative processes known in the art may be employed to adhere to particular recess size and depth constraints, such as lithography (e.g., photolithography, etch masks, or shadow masks). In alternative embodiments, device or design variations may result in different recess configurations. For example, if the stratified layers within substrate134are varied, the depth of recesses44,46may differ as a result of the varying location of semiconductor layer40within stratified substrate134.

Similarly, when a continual cutting process is implemented, one continuous recess may be formed, such that other material may fill portions of the recess to define multiple recesses. Alternatively, depending on the multi-terminal device ultimately developed on substrate134, such as for example, a thyristor, a three terminal voltage regulator, or a TRIAC, the shape, quantity and location of recesses44,46may differ. Similarly, recesses44,46also may be configured to provide for an integrated circuit, wherein multi-terminal devices are located throughout the configuration of recesses44,46.

Still referring toFIG. 4, a gate portion48may be formed adjacent to recesses44,46and may comprise a section of gate electrode layer36and oxide layer38remaining from the formation of recesses44,46. Such gate portion48may provide electrical isolation from semiconductor layer40. Similar to recesses44,46, because the width of gate portion48may influence overall performance of a printed, multi-terminal device, the illustrative embodiment demonstrates that gate portion48may be formed via laser cutting. However, other alternative processes known in the art may be employed to adhere to particular width constraints, such as lithography (e.g., photolithography, etch masks, or shadow masks).

Similar again to recesses44,46, in alternative embodiments, device or design variations may result in different gate portion48configurations. For example, when the stratified layers within substrate134are varied, the size of gate portion48may change as a result of the varying depth of semiconductor layer40within stratified substrate134. Similarly, depending on the multi-terminal device ultimately developed upon substrate134, the width, location and quantity of gate portion48may differ.

As illustrated inFIG. 5, a dopant50may be applied to recesses44,46for later diffusion into semiconductor layer40of stratified substrate134. Dopant50may be a material sufficient to dope recesses44,46opposite from semiconductor layer40. For example, in the illustrative embodiment, n-type semiconductor layer40may be doped with an acceptor impurity such that a p-type semiconductor with excess holes may be created thereon. In an alternative embodiment, a p-type semiconductor layer40may be doped with a donor impurity such that a n-type semiconductor with excess electrons may be created thereon.

As demonstrated in the illustrative embodiment, dopant50may be an acceptor impurity of a Group III element material, such as Boron. As further demonstrated in the illustrative embodiment, dopant50may be applied via thermal inkjet printer wherein droplets of dopant50may be ejected from print head22. However, alternative embodiments are contemplated, wherein dopant50may be applied using other printing techniques such as piezoelectric inkjet, laser or screen printing.

As illustrated inFIG. 6, dopant50may be diffused into semiconductor layer40to create doped regions144,146which may be doped oppositely from semiconductor layer40. Many diffusion methods are known in the art and may be implemented, such as localized heating with a digital source, laser, or ion implantation. However, as demonstrated in the illustrated embodiment, an annealing process which heats stratified substrate134to about 600-800° C. may be implemented.

Referring again toFIGS. 2-6, it should be understood that stratified substrate134, dopant50, and the diffusion method may affect the range of charge carrier mobilities achieved in a particular application. In the illustrative embodiment, stratified substrate134may be implemented, dopant material50may be applied and stratified substrate134may be annealed in order to achieve a desired charge carrier mobility range of 10 cm2/V-s to 100 cm2/V-s. However, it should be understood that any suitable stratified substrate134, dopant50, and diffusion method may be implemented to achieve a charge carrier mobility range of 10 cm2/V-s to 100 cm2/V-s. In an exemplary embodiment, the flexibility of the substrate134allows for the dopant and/or other materials to be applied using a printer, such as a laser printer or an inkjet printer for example.

As illustrated inFIG. 7, a dielectric material52may be applied to stratified substrate134such that current flow through dielectric material52may be limited, thereby reducing leakage current and unwanted heat throughout a multi-terminal device implemented on stratified substrate134. In the illustrative embodiment, dielectric material52may be spun-on-glass and may be applied as a blanket coat using a spin coating process. However, in alternative embodiments, other dielectric materials may be implemented, such as polystyrene, and other application methods may be implemented, such as application via printer, reel-to-reel application or any other method known in the art. For example, dielectric material52could be selectively applied via a laser printer. Dielectric material52and the application method may be implemented to comport with a particular multi-terminal device, however, because dielectric material52may not be necessary in a particular multi-terminal device, dielectric material52may be absent altogether from stratified substrate134.

Still referring toFIG. 7, when dielectric material52is applied to stratified substrate134, apertures244,246may be created through dielectric material52and may provide access to doped regions144,146and gate portion48of stratified substrate134. If dielectric material52is blanket coated, as demonstrated in the illustrative embodiment, apertures244,246may be opened using laser cutting or any other method appropriate for selectively removing dielectric material, such as wet, or dry etching. If dielectric material52is applied via printer, apertures244,246may be formed by selectively applying dielectric material52around each desired aperture. It should be understood that apertures244,246are merely demonstrated to comport with a printed transistor by providing access to doped regions144,146and gate portion48, and may be any size, location or quantity depending upon the desired multi-terminal device or application.

As illustrated inFIG. 8, electrodes54,56may be electrically coupled to doped regions144,146while electrode58may be electrically coupled to gate portion48. In the illustrated embodiment, electrodes54,56and58may be applied via a thermal inkjet printer through apertures244,246and electrodes54,56and58may be any conductive material capable being ejected from a printer, such as silver ink or copper ink, or gold ink or other conductive ink. Although a thermal inkjet printer is demonstrated in the illustrative embodiment, as discussed above, other printing techniques may be implemented such as piezoelectric inkjet or laser printing. In the illustrative embodiment, electrodes54,56and58may be electrically coupled to produce terminals, such that electrodes54,56facilitate electron flow through semiconductor layer40and electrode56facilitates application of a particular charge to enable such electron flow. It should be understood that electrodes54,56and58are merely demonstrated to comport with a transistor by facilitating electron flow to doped regions144,146and application of a charge to gate portion48, and may be any size, location or quantity depending upon the desired multi-terminal device or application.

In the illustrative embodiment and still referringFIG. 8, the multi-terminal device printed on stratified substrate134may be a printed transistor. Such a transistor may comprise doped regions144,146within semiconductor layer40which are electrically coupled to electrodes54and56, respectively. The embodiment may also comprise a gate portion48which is electrically coupled to electrode58.

The structure formed by doped region144and electrode54may commonly be referred to as a source344and the structure formed by doped region146and electrode56may commonly be referred to as a drain346. Similarly, the other structure formed by gate portion48and electrode58may commonly be referred to as a gate348. As illustrated, gate348may be positioned between source344and drain346such that source344and drain346facilitate electron flow to the doped regions144,146of semiconductor layer40and gate348facilitates application of a particular polarity to enable electron flow therebetween. Consistent with the transistor illustrated inFIG. 8,FIG. 9illustrates an electrical representation of such transistor so that an additional illustrative embodiment may be demonstrated and understood.

As illustrated electrically inFIG. 10, an additional embodiment of a multi-terminal device may be a thyristor. Such a thyristor may comprise an anode, cathode and gate. It should be understood to one skilled in the art that similar components disclosed above comprise the current embodiment and that the current embodiment ay be achieved through similar methods. For example, and as illustrated inFIGS. 2-8, recesses204,206may be formed within a flexible, stratified substrate134such that n-type semiconductor layer40may be exposed and printed thereon using a printer. Additionally, n-type semiconductor layer40may be doped with an acceptor impurity such that a p-type semiconductor with excess holes may be created within recesses144,146. Similarly, dielectric material52may be provided over stratified substrate134.

Apertures244,246, together with electrodes54,56may provide electrical connection to doped regions144,146to create gate444and anode446, but aperture248may be provided outside doped regions144,146such that electrode56may be electrically connected to a gate portion48lying outside of doped regions144,146to create cathode156. The dopant50, dielectric52, electrodes54,56and58, and/or other materials can be applied by a printer to create this three terminal device. The device will exhibit high charge carrier mobility, such as in the range of 10 cm2/V-s to 100 cm2/V-s and therefore can be used in applications where high switching speed is desired.

The foregoing description of the various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many alternatives, modifications and variations will be apparent to those skilled in the art of the above teaching. Accordingly, while some of the alternative embodiments of the printed transistor with high charge carrier mobility and the methods for producing such have been discussed specifically, other embodiments will be apparent or relatively easily developed by those of ordinary skill in the art. Accordingly, this invention is intended to embrace all alternatives, modifications and variations that have been discussed herein.