CONNECTOR PLACEMENT FOR A SUBSTRATE INTEGRATED WITH A TOROIDAL INDUCTOR

A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

The present disclosure is generally related to connector placement for a substrate integrated with a toroidal inductor.

II. DESCRIPTION OF RELATED ART

Inductors are used in power regulation, frequency control, and signal conditioning applications in many electronic devices. For example, a radio frequency (RF) chipset may use toroidal inductors. Toroidal inductors can have certain functional benefits relative to other inductor configurations. For example, a magnetic field of a toroidal inductor is contained within coils of the inductor, which may reduce electromagnetic interference relative to other inductor configurations. However, because toroidal inductors are not space efficient, designing circuits with toroidal inductors may be difficult due to space constraints.

This disclosure presents particular embodiments that simplify use of toroidal inductors in circuits by efficiently utilizing space associated with the toroidal inductors. For example, using through via manufacturing technologies (e.g., through-glass-via or through-silicon-via technologies), a substrate may be integrated with a toroidal inductor. The toroidal inductor may include conductive vias that are electrically coupled together to form the toroidal inductor. Connectors for the toroidal inductor that enable the toroidal inductor to be coupled to devices external to the substrate may be positioned on surfaces of the substrate and may be surrounded by conductive vias of the toroidal inductor. Surrounding the connectors for the toroidal inductor with the conductive vias of the toroidal inductor may locate the connectors close to the toroidal inductor to limit additional resistance associated with leads that couple the toroidal inductor to the connectors. The additional resistance may degrade overall circuit performance in terms of additional power consumption. Surrounding the connectors of the toroidal inductor with the conductive vias of the toroidal inductor may utilize space associated with a central region of the toroidal inductor and result in a device with a smaller footprint than a device that has connectors external to the central region of the toroidal inductor.

In a particular embodiment, a device includes a substrate. The device includes a first connector coupled to a first surface of the substrate. The first connector is configured to be electrically coupled to a first device external to the substrate. The device includes a second connector coupled to a second surface of the substrate. The device includes a plurality of conductive vias extending through the substrate from the first surface to the second surface and surrounding the first connector and the second connector. The plurality of conductive vias are electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. Also, a second lead of the toroidal inductor is electrically coupled to the second connector.

In a particular embodiment, a method includes forming a first connector on a first surface of a substrate. The first connector is configured to be electrically coupled to a first device external to the substrate. The first connector is surrounded by a plurality of conductive vias that are electrically coupled together to form a toroidal inductor integral with the substrate. The method includes electrically coupling the first connector to the toroidal inductor. The method includes forming a second connector on a second surface of the substrate. The second conductor is configured to be electrically coupled to a second device external to the substrate. The second connector is surrounded by the plurality of conductive vias. The method also includes electrically coupling the second connector to the toroidal inductor.

In a particular embodiment, a computer-readable storage device stores instructions that, when executed by a processor, cause the processor to initiate formation of a first connector on a first surface of a substrate. The first connector is surrounded by a plurality of conductive vias that are electrically coupled together to form a toroidal inductor integral with the substrate. The first connector is electrically coupled to the toroidal inductor. The instructions also cause the processor to initiate formation of a second connector on a second surface of the substrate. The second connector is surrounded by the plurality of conductive vias. The second connector is electrically coupled to the toroidal inductor.

In a particular embodiment, a method includes a step for forming a first connector on a first surface of a substrate. The first connector is surrounded by a plurality of conductive vias that are electrically coupled together to form a toroidal inductor integral with the substrate. The first connector is electrically coupled to the toroidal inductor. The method also includes a step for forming a second connector on a second surface of the substrate. The second connector is electrically coupled to the toroidal inductor.

One particular advantage provided by at least one of the disclosed embodiments is that a device with a toroidal inductor integrated with a substrate with connectors of the toroidal inductor surrounded by conductive vias of the toroidal inductor is that the device may have a smaller footprint as compared to a similar device with a toroidal inductor integrated with a substrate with connectors of the toroidal inductor offset outwards from the conductive vias of the toroidal inductor. Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

V. DETAILED DESCRIPTION

Particular embodiments of devices that include a toroidal inductor integrated with a substrate, where connectors of the toroidal inductor that enable the toroidal inductor to be coupled to devices external to the device are surrounded by conductive vias of the toroidal inductor, are presented in this disclosure. It should be appreciated, however, that the concepts and insights used in the particular embodiments with respect to the designs of the devices may be embodied in a variety of contexts. The particular embodiments presented are merely illustrative, and do not limit the scope of this disclosure.

The present disclosure describes the particular embodiments in specific contexts. However, features, methods, structures or characteristics described according to the particular embodiments may also be combined in suitable manners to form one or more other embodiments. In addition, figures are used to illustrate the relative relationships between the features, methods, structures, or characteristics, and thus may not be drawn in scale. Directional terminology, such as “top,” “bottom,” “front,” “back,” etc. is used with reference to the orientation of the figures being described. As such, the directional terminology is used for purposes of illustration and is not meant to be limiting.

Referring toFIG. 1, a particular illustrative embodiment of a device with toroidal inductors102,104integrated in a substrate106is disclosed and generally designated100.FIG. 1depicts a top view of a particular illustrative embodiment of the device100. The device100may be an interposer device that facilitates connecting two or more devices together. The two or more devices may be, but are not limited to, circuit boards, integrated circuits, transistors, diodes, resistors, capacitors, inductors, other electrical devices, or combinations thereof.

The toroidal inductors102,104may be formed by a plurality of conductive vias that extend from a first side of the substrate106to a second side of the substrate106(e.g., the conductive vias204depicted inFIG. 2). The conductive vias may be electrically coupled together by a plurality of leads108. In other embodiments, the device100may include only a single toroidal inductor, two toroidal inductors located in other locations, or more than two toroidal inductors.

The substrate106may be made of a low-loss material (e.g., a dielectric, a wide-bandgap semiconductor, etc.). The low-loss material may include a dielectric material or a highly-insulative semiconductor material. The substrate106may include a glass substrate, a quartz substrate, a silicon-on-insulator (SOI) substrate, a silicon-on-sapphire (SOS) substrate, a high resistivity substrate (HRS), a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, a rogers laminate substrate, a polymeric substrate, or combinations thereof, as illustrative, non-limiting examples.

The device100may include a plurality of connectors110,112,114. The connectors110,112,114may be ball/bump pads or other types of connectors that enable the device100to be coupled to one or more devices external to the device100. The connectors110, which are not electrically coupled to the toroidal inductors102,104, may be electrically coupled by conductive vias that extend through the substrate106to corresponding connectors on an opposite side of the substrate106. The connector112may be electrically coupled to the first toroidal inductor102. The connector114may be electrically coupled to the second toroidal inductor104. In other embodiments, the device100may include fewer or more connectors that are located in regular patterns or non-regular patterns on the device100.

The connector112may be electrically coupled to the first toroidal inductor102by a lead116. A second connector on the opposite side of the substrate106may be electrically coupled to the first toroidal inductor102by another lead. The connector112and the second connector may be surrounded by conductive vias through the substrate106that are electrically coupled together by the leads108to form the toroidal inductor102. The connector114may be electrically coupled to the second toroidal inductor104by a lead118. A third connector on an opposite side of the substrate106may be electrically coupled to the second toroidal inductor104by another lead. The connector114and the third connector may be surrounded by conductive vias through the substrate106that are electrically coupled together by leads108to form the toroidal inductor104. The leads108,116,118and the connectors110,112,114may include, but are not limited to, solder, copper (Cu), tungsten (W), silver (Ag), gold (Au), or combinations or alloys thereof

FIG. 1depicts the device100with the connectors112,114of the toroidal inductors102,104positioned in central regions of the toroidal inductors102,104. The connectors112,114, and connectors for the toroidal inductors102,104on the second side of the substrate may be surrounded by conductive vias of the toroidal inductors102,104that are electrically coupled together by the leads108.

The device100may include one or more elongated toroidal inductors. For example, the toroidal inductor104is an elongated toroidal inductor with conductive vias surrounding the connector114. The connector114is coupled to a first end conductive via by the lead118. A corresponding connector is coupled to a second end conductive via by a lead on a second side of the substrate106. The connector110is located in a central region of the toroidal inductor104(e.g., between the leads108that electrically couple conductive vias of the toroidal inductor104together). A connector on the second side of the substrate106may be coupled to the connector110by a conductive via. Surrounding the connectors112,114of the toroidal inductors102,104with the conductive vias of the toroidal inductors102,104may utilize space associated with the central regions of the toroidal inductors102,104and may result in the device100having a smaller footprint than a device that has connectors external to the central regions of the toroidal inductors.

FIG. 2is a cross-sectional representation taken substantially along line2-2ofFIG. 1.FIG. 2depicts a portion of the device100with connectors112,202of the toroidal inductor102surrounded by conductive vias204of the toroidal inductor102. The connector112may be electrically coupled to a first end conductive via of the conductive vias204by a lead (e.g., by the lead116depicted inFIG. 1), and the connector202may be coupled to a second end conductive via of the conductive vias204by another lead. The end conductive vias may be a first particular conductive via that begins a toroid of the toroidal inductor102and a second particular conductive via that ends the toroid of toroidal inductor102.

The device100may include the substrate106. The device100may include the conductive vias204, which extend from a first side of the substrate106to a second side of the substrate106. The conductive vias204may be electrically coupled together by leads108. The conductive vias204may be metal filled, may include plated sides with empty cores, or may include plated sides with polymer filled cores. The metal of the conductive vias204may be, but is not limited to, copper (Cu), tungsten (W), silver (Ag), gold (Au), or combinations or alloys thereof. The polymer cores may include, but are not limited to, polyimides (PI), benzocyclobutenes (BCB), acrylics, polybenzoxazoles (PBO), photoresists (e.g., TMMR®, SU-8, or other types of photoresists), or combinations thereof. Having polymer cores or empty cores may enable the conductive vias204to provide structural support for the device100and may be more compatible with TGV fabrication techniques than completely filling the conductive vias204with metal. In addition, having empty cores or polymer cores may reduce material costs of the conductive vias104(e.g., polymer materials may cost less than metal).

Referring toFIG. 3, a particular illustrative embodiment of a circuit including a capacitor with a dielectric between a via and a plate of the capacitor is disclosed.FIG. 3depicts a cross-sectional representation of a particular illustrative embodiment of a portion of a device300having a toroidal inductor302integrated with a substrate304, where connectors306,308of the toroidal inductor302are surrounded by conductive vias310of the toroidal inductor302. The conductive vias306,308may be electrically coupled to end conductive vias of the conductive vias310by leads. The end conductive vias may be a first particular conductive via that begins a toroid of the toroidal inductor302and a second particular conductive via that ends the toroid of toroidal inductor302.

The device300may include the toroidal inductor302. The toroidal inductor302may include the conductive vias310that extend through the substrate304from a first side of the substrate304to a second side of the substrate304. The conductive vias310may be electrically coupled together to form the toroidal inductor302by leads312. The conductive vias310may surround the connectors306,308. The toroidal inductor302may be electrically coupled to a device external to the device300by a connector314that is electrically coupled to the connector306by a conductive via316.

The device300also includes a capacitor318coupled to the connector306. The capacitor318may include a dielectric320between a first plate322and the connector306, which may act as a second plate of the capacitor318. The dielectric320may include, but is limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOxNy), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), aluminum nitride (AlN), or combinations thereof. The first plate322may enable the capacitor318to be electrically coupled to a device external to the device300by a connector324that is electrically coupled to the first plate322by a connective via326. The capacitor318may be located in an inter-layer dielectric328to insulate the capacitor318from other devices or circuitry.

The toroidal inductor302and the capacitor318may form a resonant circuit. For example, when the capacitor318is charged with a first polarity and begins to discharge, an electric current may begin flowing through the toroidal inductor302. While the capacitor318discharges, a magnetic field of the toroidal inductor302may build as a result of the electric current flowing through the toroidal inductor302. After the capacitor318has discharged, the magnetic field may cause the capacitor114to charge with an opposite polarity to the first polarity as flow of the electric current through the toroidal inductor302reduces. A second electric current in an opposite direction of the electric current may then begin flowing through the toroidal inductor302as a strength of the magnetic field is reduced. The second electric current may discharge the capacitor318and then recharge the capacitor318with the first polarity. Voltage across the capacitor318and the toroidal inductor302may oscillate at a frequency (e.g., a resonant frequency) approximately equal to a capacitance value of the capacitor318multiplied by an inductance value of the toroidal inductor302. Losses in current due to resistance may dampen oscillations and may reduce efficiency of the circuit. Coupling the capacitor318to the connector306may result in small resistance losses for the resonant circuit as compared to connectors that are located external to the conductive vias310of the toroidal inductor302.

The device300may be a radio frequency (RF) device (e.g., a diplexer) for use in wireless communication devices. The device300may be formed using through-glass-via (TGV) technology to provide smaller size, higher performance, simplified manufacturing, and cost advantages as compared to a similar device formed by multi-layer chip diplexer (MLCD) technology. The capacitor318may be a metal-insulator-metal capacitor or other type of capacitor. The capacitor318may be coupled in series, or in parallel, with the inductor302to achieve designed circuit functions.

FIG. 3illustrates the capacitor318and the connector314coupled to the connector306. In other embodiments, the device300may include a capacitor coupled to the connector308, a capacitor and a connector coupled to the connector308, the capacitor318coupled to the connector306without the connector314and the conductive via316, or combinations thereof. The capacitor coupled to the connector308may be coupled in series, or in parallel, with the inductor302.

FIG. 4. depicts simulation results of inductance versus frequency and simulation results of quality factor (Q) versus frequency for a first device400and a second device430. The first device includes a toroidal inductor402integrated with a substrate404with connectors for the toroidal inductor402located outside of a central region406of the toroidal inductor402. The second device430includes a toroidal inductor432integrated with a substrate434with connectors436,438for the toroidal inductor432located inside of a central region440of the toroidal inductor432. For the top view representation of the first device400depicted inFIG. 4, solid lines indicate leads408on a top surface of the substrate404, dashed circles indicate conductive vias410beneath the leads408, and dashed lines indicate leads412on a bottom surface of the substrate404. Connectors for the toroidal inductor402are located outside of the central region406defined by the toroidal inductor402. The connectors for the toroidal inductor402are coupled to leads414,416.

For the top view representation of the second device430depicted inFIG. 4, solid lines indicate leads442,444and the first connector436on a top surface of the substrate434, dashed circles indicate conductive vias446beneath the leads442, and dashed lines indicate leads448,450and the second connector438on a bottom surface of the substrate434. Connectors436,438are surrounded by the conductive vias446that form the toroidal inductor432.

Curve470depicts simulation results of inductance versus frequency for the first device400, and curve472depicts simulation results of inductance versus frequency for the second device430. Curve480depicts simulation results of quality factor versus frequency for the first device400, and curve482depicts simulation results of quality factor versus frequency for the second device430. Table 1 depicts values from the simulation results at a frequency of 1 GHz. The curves470,472,480,482and the values from Table 1 show that a device formed with a toroidal inductor integrated in a substrate such that connectors for the toroidal inductor are surrounded by conductive vias of the toroidal inductor (e.g., the second device430ofFIG. 4) has comparable performance to a similar device with a toroidal inductor integrated in a substrate where the connectors of the toroidal inductor are not surrounded by conductive vias of the toroidal inductor (e.g., the first device400ofFIG. 4).

Referring toFIG. 5, a flow chart of a particular illustrative embodiment of a method of forming a device with connectors of a toroidal inductor integrated with a substrate so that the connectors are surrounded by conductive vias of the toroidal inductor is depicted and generally designated500. The device may be any of the devices100,300,430ofFIGS. 1-4.

The method500includes forming a first connector on a first surface of a substrate, at502. The first connector may be configured to electrically couple to a first device external to the device (e.g., a circuit board or a RF chip of a RF chip set). The first connector may be surrounded by a plurality of conductive vias that are electrically coupled together to form a toroidal inductor integral with the substrate. In a first particular embodiment, the first connector may be formed using one or more deposition processes, such as, but not limited to, electroplating, physical vapor deposition (PVD) (e.g., sputtering or evaporation), chemical vapor deposition (CVD), or combinations thereof. In a second particular embodiment, the first connector may be formed by mechanical removal, chemical removal, or both, of a metal layer deposited on the substrate. A planarization process may be used to remove unwanted or excess materials and to create a flat surface for subsequent processing. The planarization process may include, but is not limited to chemical-mechanical polish (CMP), an etch-back planarization process, or combinations thereof. In a particular embodiment, a solder ball or other electrically conductive material maybe coupled to the first connector to facilitate electrically coupling the first connector to the first device.

The method500includes electrically coupling the first connector to the toroidal inductor, at504. Electrically coupling the first connector to the toroidal inductor may include forming a lead between the first connector and a first end conductive via of the conductive vias that form the toroidal inductor. The lead may be formed using one or more deposition processes or by one or more removal processes. In a particular embodiment, electrically coupling the first connector to the toroidal inductor, at504, happens when the first connector is formed on the first surface of the substrate, at502(e.g., the first connector is formed coupled to the toroidal inductor).

The method500includes forming a second connector on a second surface of a substrate, at506. The second connector may be configured to electrically couple to a second device external to the device (e.g., a circuit board or a RF chip of a RF chip set). The second connector may be surrounded by the plurality of conductive vias. The second connector may be formed by one or more deposition processes; by mechanical removal, chemical removal, or both, of a metal layer deposited on the substrate; or by combinations thereof. A planarization process may be used to remove unwanted or excess materials and to create a flat surface for subsequent processing. In a particular embodiment, a solder ball or other electrically conductive material may be coupled to the second connector to facilitate electrically coupling the second connector to the second device.

The method500includes electrically coupling the second connector to the toroidal inductor, at508. Electrically coupling the second connector to the toroidal inductor may include forming a lead between the second connector and a second end conductive via of the conductive vias that form the toroidal inductor. The lead may be formed using one or more deposition processes or by one or more removal processes. In a particular embodiment, electrically coupling the second connector to the toroidal inductor, at508, happens when the second connector is formed on the second surface of the substrate, at506(e.g., the second connector is formed coupled to the toroidal inductor).

In some embodiments, the method may also include forming a dielectric layer on a portion of the first connector or on a portion of the second connector. A metal layer may be formed on top of the dielectric layer to form a capacitor.

The method ofFIG. 5may be initiated or controlled by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, firmware device, or any combination thereof. As an example, the method500ofFIG. 5may be performed by fabrication equipment including a processor that executes instructions stored at a memory (e.g., a non-transitory computer-readable medium), as described further with reference toFIG. 6. As another example, the method500ofFIG. 5may be performed by fabrication equipment including a processor that executes instructions stored at a memory (e.g., a non-transitory computer-readable medium), as described further with reference toFIG. 7.

Referring toFIG. 6, a block diagram of a particular illustrative embodiment of a wireless communication device is depicted and generally designated600. The device600includes a processor602(e.g., a digital signal processor (DSP)) coupled to a memory604(e.g., a random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art). The memory604may store instructions606executable by the processor602. The memory604may store data608accessible to the processor602.

The device600includes an interposer device610positioned between portions of the device600. The interposer device610may include a toroidal inductor integrated with a substrate. Connectors for the interposer device610may be located on surfaces of the substrate surrounded by a toroid of the toroidal inductor. The interposer device610may also include a capacitor. The capacitor and the toroidal inductor may form a resonant circuit612. In an illustrative embodiment, the interposer device610may correspond to one or more of the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof. For example, as depicted inFIG. 6, the interposer device610may be positioned between a wireless controller614and a RF interface616. The interposer device610may include the resonant circuit612.

FIG. 6also shows a display controller618that is coupled to the digital signal processor602and to a display620. A coder/decoder (CODEC)622can also be coupled to the digital signal processor602. A speaker624and a microphone626can be coupled to the CODEC622.FIG. 6also indicates that the wireless controller614can be coupled to the digital signal processor602and to a wireless antenna628via the interposer device610and the RF interface616.

In a particular embodiment, the DSP602, the memory604, the wireless controller614, the display controller618, and the CODEC622are included in a system-in-package or system-on-chip device630. In a particular embodiment, an input device632and a power supply634are coupled to the system-on-chip device630. Moreover, in a particular embodiment, as illustrated inFIG. 6, the display620, the input device632, the speaker624, the microphone626, the wireless antenna628, and the power supply634are external to the system-on-chip device630. However, each of the display620, the input device632, the speaker624, the microphone626, the wireless antenna628, and the power supply634can be coupled to a component of the system-on-chip device630, such as an interface or a controller.

The foregoing disclosed devices and functionalities may be designed and configured as computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.FIG. 7depicts a particular illustrative embodiment of an electronic device manufacturing process700.

Referring toFIG. 7, a particular illustrative embodiment of an electronic device manufacturing process is depicted and generally designated700. InFIG. 7, physical device information702is received at the manufacturing process700, such as at a research computer704. The physical device information702may include design information representing at least one physical property of an electronic device, such as a toroidal inductor integrated in a substrate including connectors surrounded by conductive vias that form the toroidal inductor (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof). For example, the physical device information702may include physical parameters, material characteristics, and structure information that is entered via a user interface706coupled to the research computer704. The research computer704includes a processor708, such as one or more processing cores, coupled to a computer readable medium such as a memory710. The memory710may store computer readable instructions that are executable to cause the processor708to transform the physical device information702to comply with a file format and to generate a library file712.

In a particular embodiment, the library file712includes at least one data file including the transformed design information. For example, the library file712may include a library of interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof) provided for use with an electronic design automation (EDA) tool714.

The library file712may be used in conjunction with the EDA tool714at a design computer716including a processor718, such as one or more processing cores, coupled to a memory720. The EDA tool714may be stored as processor executable instructions at the memory720to enable a user of the design computer716to design a circuit including the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof) of the library file712. For example, a user of the design computer716may enter circuit design information722via a user interface724coupled to the design computer716. The circuit design information722may include design information representing at least one physical property of a semiconductor device, such as the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof). To illustrate, the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device.

The design computer716may be configured to transform the design information, including the circuit design information722, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer716may be configured to generate a data file including the transformed design information, such as a GDSII file726that includes information describing the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof), in addition to other circuits or information.

The GDSII file726may be received at a fabrication process728to manufacture the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof), according to transformed information in the GDSII file726. For example, a device manufacture process may include providing the GDSII file726to a mask manufacturer730to create one or more masks, such as masks to be used with photolithography processing, illustrated as a representative mask732. The mask732may be used during the fabrication process to generate one or more wafers734, which may be tested and separated into dies, such as a representative die736. The die736includes a circuit including the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof).

The die736may be provided to a packaging process738where the die736is incorporated into a representative package740. For example, the package740may include the single die736or multiple dies, such as a system-in-package (SiP) arrangement. The package740may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.

Information regarding the package740may be distributed to various product designers, such as via a component library stored at a computer742. The computer742may include a processor744, such as one or more processing cores, coupled to a memory746. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory746to process PCB design information748received from a user of the computer742via a user interface750. The PCB design information748may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package740including the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof).

The computer742may be configured to transform the PCB design information748to generate a data file, such as a GERBER file752with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package740including the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof). In other embodiments, the data file generated by the transformed PCB design information may have a format other than a GERBER format.

The GERBER file752may be received at a board assembly process754and used to create PCBs, such as a representative PCB756, manufactured in accordance with the design information stored within the GERBER file752. For example, the GERBER file752may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB756may be populated with electronic components including the package740to form a representative printed circuit assembly (PCA)758.

The PCA758may be received at a product manufacture process760and integrated into one or more electronic devices, such as a first representative electronic device762and a second representative electronic device764. As an illustrative, non-limiting example, the first representative electronic device762, the second representative electronic device764, or both, may be selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof) is integrated. As another illustrative, non-limiting example, one or more of the electronic devices762and764may be remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 7illustrates remote units according to teachings of the disclosure, the disclosure is not limited to these illustrated units. Embodiments of the disclosure may be suitably employed in any device which includes active integrated circuitry including memory and on-chip circuitry.

A device that includes the interposer device (e.g., the devices100,300,430ofFIGS. 1-4, a device formed according to the method500ofFIG. 5, or a combination thereof), may be fabricated, processed, and incorporated into an electronic device, as described in the illustrative process700. One or more aspects of the embodiments disclosed with respect toFIGS. 1-3,5, and7may be included at various processing stages, such as within the library file712, the GDSII file726, and the GERBER file752, as well as stored at the memory710of the research computer704, the memory720of the design computer716, the memory746of the computer742, the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process754, and also incorporated into one or more other physical embodiments such as the mask732, the die736, the package740, the PCA758, other products such as prototype circuits or devices (not shown), or any combination thereof. Although various representative stages of production from a physical device design to a final product are depicted, in other embodiments fewer stages may be used or additional stages may be included. Similarly, the process700may be performed by a single entity or by one or more entities performing various stages of the process700.

In conjunction with the described embodiments, an apparatus is disclosed that includes means for supporting layers integrated with a means for storing energy in a magnetic field. The means for supporting layers may include the substrates ofFIGS. 1-3and5. The means for storing energy in a magnetic field may include the toroidal inductors depicted inFIGS. 1-3, and5.

The apparatus also includes means for making first electrical contact on the means for supporting layers and means for making second electrical contact on the means for supporting layers. The means for making first electrical contact and the means for making second electrical contact may include the connectors112,114,202,306,308,324,314,436, and438depicted inFIGS. 1-4.