INTEGRATED CIRCUITS WITH TWO-SIDE METALLIZATION AND EXTERNAL STIFFENING LAYER AND RELATED FABRICATION METHODS

An integrated circuit (IC) includes a plurality of first metallization layers on a front side of a circuit layer and a plurality of second metallization layers on a back side of the circuit layer. A semiconductor substrate on the back side of the circuit layer of the IC is thinned to improve access to devices from the back side. The plurality of second metallization layers are employed to provide increased interconnection among the devices without increasing area and may provide increased access to external contacts. Thinning the semiconductor substrate reduces structural rigidity needed for processing, so the IC also includes a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers to increase rigidity and first vias extending through the stiffening layer to couple to first contacts.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to integrated circuits (ICs) and, more particularly, to ICs with metallization layers on both sides.

Integrated circuits are based on circuit layers of transistors formed in one side of a semiconductor (e.g., silicon) substrate. Circuits are formed by connecting the transistors to each other and to external circuit contacts using metal interconnects in metallization layers that are formed on the circuit layer. The metallization layers include several metal layers that are substantially parallel to the circuit layer. Thus, the interconnects in these layers may be referred to as “horizontal.” The metal layers are separated in the “vertical” direction by a dielectric material and horizontal interconnects in different metal layers can be connected by vertical interconnect accesses (“vias”) that extend through the dielectric material. Spaces between the horizontal interconnects in the metal layers are also filled by the dielectric material. These interconnects can provide data signals, control signals, and power signals to the transistors. Because the pitch of transistors is small and continues to get smaller with advances in technology, the metal interconnects closest to the circuit layer also must be small but increase in size in the metal layers farther from the circuit layer, which limits the capacity for interconnection of the transistors. In addition, the metal layers may couple to even larger input/output (I/O) contacts on a top surface of the metallization layers. The I/O contacts may be efficiently arranged in arrays but, due to minimum contact sizes and minimum separation pitches, a limited number of contacts can fit on the top surface. Due to the need for more I/O contacts, some manufacturers of ICs have created through-silicon vias (TSVs) from the circuit layer through the semiconductor substrate to a back side of the IC. However, such TSVs can be large in cross-section and occupy areas of the circuit layer, known as “keep-out zones” in which no transistors can be formed. Thus, the number of such TSVs can be limited or can cause the size of an IC to be increased. Solutions are needed for providing sufficient numbers of I/O contacts on an IC as the numbers of transistors in a circuit layer continues to increase.

SUMMARY

Aspects disclosed herein include integrated circuits (ICs) with two-side metallization and external stiffening layers. Related methods of fabricating an IC with two-side metallization and external stiffening layers are also disclosed. An exemplary IC includes first metallization layers on a first, front side of a circuit layer and second metallization layers on a second, back side of the circuit layer. A semiconductor substrate on the second, back side of the circuit layer can be thinned to improve access to the second, back side of devices in the circuit layer. In this regard, the second metallization layers can provide increased interconnection between devices in the circuit layer and may provide increased access to the circuit layer from external contacts for data, control, and power signals. However, thinning a semiconductor substrate including the circuit layer may significantly reduce structural rigidity needed for processing. Thus, the exemplary IC also includes a stiffening layer on one of the first metallization layers and the second metallization layers and first vias extending through the stiffening layer to first contacts. The stiffening layer provides structural rigidity to reduce mechanical and electrical failures caused by flexing of the circuit layer during, for example, manufacturing processes. In some examples, the first metallization layers include front side metallization layers, and the second metallization layers include back side power rails and back side metallization layers. In some examples, the IC also includes second contacts on the metallization layers opposite to the stiffening layer. In this regard, electrical connections between the first contacts and the second contacts may be provided and the IC may be employed as a bottom or intermediate IC in a stack of ICs on a package substrate in an IC package.

In an exemplary aspect, an IC is disclosed. The IC includes a circuit layer and a plurality of first metallization layers disposed on a first side of the circuit layer and coupled to the circuit layer. The IC also includes a plurality of second metallization layers disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer and a stiffening layer disposed on one of the plurality of first metallization layers and the plurality of second metallization layers. The IC further includes a first via extending through the stiffening layer to couple the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact on the stiffening layer.

In another exemplary aspect, a method of fabricating an integrated circuit (IC) is disclosed. The method includes forming a circuit layer and forming a plurality of first metallization layers on a first side of the circuit layer. The method also includes forming a plurality of second metallization layers on a second side of the circuit layer opposite to the first side and disposing a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers. The method further includes forming a first via extending through the stiffening layer from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact on a second side of the stiffening layer.

In a further exemplary aspect, an IC package is disclosed. The IC package includes a first package substrate and an IC comprising a circuit layer, a plurality of first metallization layers disposed on a first side of the circuit layer and coupled to the circuit layer, and a plurality of second metallization layers disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer. The IC also includes a stiffening layer disposed on one of the plurality of first metallization layers and the plurality of second metallization layers and a first via extending through the stiffening layer from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact on a second side of the stiffening layer, wherein the first contact is coupled to the first package substrate.

DETAILED DESCRIPTION

Several exemplary aspects of the present disclosure are described in reference to the drawing figures. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

Aspects disclosed herein include integrated circuits (ICs) with two-side metallization and external stiffening layers. Related methods of fabricating an IC with two-side metallization and external stiffening layers are also disclosed. An exemplary IC includes first metallization layers on a first, front side of a circuit layer and second metallization layers on a second, back side of the circuit layer. A semiconductor substrate on the second, back side of the circuit layer can be thinned to improve access to the second, back side of semiconductor devices in the circuit layer. In this regard, the second metallization layers can provide increased interconnection between semiconductor devices in the circuit layer and may provide increased access to the circuit layer from external contacts for data, control, and power signals. However, thinning a semiconductor substrate including the circuit layer may significantly reduce structural rigidity needed for processing. Thus, the exemplary IC also includes a stiffening layer on one of the first metallization layers and the second metallization layers and first vias extending through the stiffening layer to first external contacts. The stiffening layer provides structural rigidity to reduce mechanical and electrical failures caused by the flexing of the circuit layer during, for example, manufacturing processes. In some examples, the first metallization layers include front side metallization layers and the second metallization layers include back side power rails and back side metallization layers. In some examples, the IC also includes second external contacts on the metallization layers opposite to the stiffening layer. In this regard, electrical connections between the first contacts and the second contacts may be provided, and the IC may be employed as a bottom or intermediate IC in a stack of ICs on a package substrate in an IC package.

In this regard,FIG.1is a cross-sectional side view of an exemplary IC package100including a first IC102on a package substrate104and a second IC106on the first IC102. The first IC102is coupled to the package substrate104through first contacts108. The second IC106is coupled to the first IC102through second contacts110and may be coupled to the package substrate104through the first IC102. In this manner, both the first IC102and the second IC106may be coupled to package contacts112on the package substrate104, providing electrical connections from the first IC102and the second IC106to external circuits (not shown). In this example, an encapsulant114(e.g., a polymer) is disposed over the first IC102and the second IC106for protection (e.g., mechanical and/or chemical) from the environment. It should be understood that the illustration of the IC package100is for purposes of explanation only and is not intended to be to scale or complete. In addition, only portions of the first IC102, the second IC106, and the package substrate104may be shown inFIG.1.

The first IC102includes a plurality of first metallization layers116disposed on a first, front side SIC1of a circuit layer118and coupled to the circuit layer118. The circuit layer118includes a semiconductor layer121including devices (not shown), such as transistors, that can be electrically coupled to form circuits that provide a functionality of the first IC102.

The devices in the circuit layer118may include memory devices, analog devices, and/or digital logic devices for sequential logic and/or combinational logic. Any of such devices may include transistors formed in a semiconductor substrate. The first IC102also includes a plurality of second metallization layers120on a second, back side SIC2of the circuit layer118opposite to the first side SIC1and coupled to the circuit layer118. The circuit layer118may be initially formed on a surface of the semiconductor substrate, most of which is removed by thinning (e.g., back grinding), leaving the circuit layer118comprising a semiconductor layer including active circuit devices. The semiconductor is thinned to make the circuit layer118more accessible from the back side SIC2.

The circuit layer118may also include first isolation layer125A and a second isolation layer125B provided on opposite sides of the semiconductor layer121to provide electrical isolation prior to formation of the first metallization layers116and second metallization layers120. The first and second isolation layers may be formed of an inter-layer dielectric (ILD) material, an inter-metal dielectric (IMD) material, or a shallow trench isolation (STI) material that provides electrical isolation. In some examples, the semiconductor layer121may have a thickness T118in a first direction (e.g., in the Z-axis direction) of less than 10 microns and may be in a range of less than 1 micron down to one-tenth (0.1) of a micron (μm). The first metallization layers116have a thickness T116in the first direction in the range of 1.0 to 5.0 microns (μm), and the second metallization layers120have a thickness T120in the first direction in the range of 1.0 to 5.0 microns, for example. In this manner, data signals, control signals, and/or power signals may be transmitted to and from the circuit layer118through either the first metallization layers116or the second metallization layers120. In some examples, a signal in the first metallization layers116may be coupled through the circuit layer118to the second metallization layers120. In some examples, the devices in the circuit layer118may be coupled to one or both of the first metallization layers116and the second metallization layers120. The circuit layer118may include semiconductor material sandwiched between dielectric material on the front side SIC1and the back side SIC2.

However, thinning the circuit layer118as described above reduces the structural integrity of the circuit layer118, causing it to be too weak for fabrication processes, such as transfer by an automated pick and place machine. To provide a desired level of structural rigidity to the first IC102, a stiffening layer122is disposed on the second metallization layers120on the back side SIC2. The stiffening layer122provides structural rigidity to the IC102to reduce mechanical or electrical failures due to flexing during manufacturing processes. The stiffening layer122also provides a thermal reservoir to moderate fluctuations in temperature due to changes in activity (e.g., heat generation) in the circuit layer118.

In other examples, as discussed below, the stiffening layer122may be disposed on and coupled to the first metallization layers116on the front side SIC1. The stiffening layer122may be any appropriate material, such as a semiconductor substrate (e.g., silicon). In the example of a silicon substrate, the stiffening layer122may have a thickness T1of at least twenty (20) microns (μm) and may be in a range of 20 to one hundred (100) microns (μm). Thus, the thickness T1of the stiffening layer122may be at least four (4) times the combined thickness T116of the thickness T116of the first metallization layers, the thickness T118of the circuit layer118, and the thickness T120of the second metallization layers. Since the stiffening layer122may be a semiconductor material, such as silicon, a film124is provided between the stiffening layer122and the second metallization layers120. The film124may be an oxide film, for example.

The first IC102includes vertical interconnect accesses (vias)126extending through the stiffening layer122to couple the second metallization layers120to the first contacts108disposed on the stiffening layer122. In this manner, the vias126and the first contacts108couple the circuit layer118to the package substrate104. The vias126may be through-silicon vias (TSVs) that extend from a first side SSL1of the stiffening layer122adjacent to the second metallization layers120to a first contact108on a second side SSL2of the stiffening layer122. The vias126may be formed of at least one of copper, tungsten, and other conductive metals or materials. The vias126may each have a height-to-width aspect ratio (e.g., Z-axis direction to X-axis direction) in the range from five to one (5:1) up to ten to one (10:1). On the front side SIC1, the first metallization layers116of the first IC102are coupled to the second IC106by the second contacts110. The stiffening layer122provides a space in which power distribution network capacitors (not shown) may be formed. For example, trench capacitors (not shown) may be formed in either the first side SSL1or the second side SSL2of the stiffening layer122.

The first metallization layers116include metal layers M0-MN, where the metal layer M0is closest to the circuit layer118on the first side SIC1, and the metal layers M1-MN are formed on the metal layer M0with the metal layer MN farthest from the circuit layer118. Dimensions of the metal layers M0-MN in a width direction (X-axis direction or Y-axis direction) and a height direction (Z-axis direction) are smallest in the metal layer M0and increase to the largest in the metal layer MN. The metal layer MN is compatible with a pitch PI of the second contacts110. The metal layers M0-MN are separated and electrically isolated from each other by dielectric material132, which may be an ILD, an IMD, or an STI material.

Similarly, the second metallization layer120includes bottom metal layers BM0-BMM, with the bottom metal layer BM0being closest to the back side SIC2of the circuit layer118and having the smallest width and height dimensions. The bottom metal layer BMM is farthest from the circuit layer118and has the largest width and height dimensions of any of the bottom metal layers BM0-BMM, which are compatible with a pitch P2of the first contacts108. The bottom metal layers BM0-BMM are also isolated from each other by an ILD, IMD, or STI material.

FIG.2is an illustration of an IC200, which may be the first IC102inFIG.1, including a stiffening layer202on a back side SIC2of a circuit layer204with vias206extending through the stiffening layer202to couple bottom metal layers BM0-BMM of second metallization layers208to first external contacts210. The IC200includes first metallization layers212including metal layers M0-MN, which may be optionally coupled to second external contacts214. In some examples, the IC200may not have a second IC (such as the second IC106inFIG.1) disposed on one side. In such examples, the IC200may be coupled to external circuits (not shown) only through the first external contacts210, such as to a package substrate as inFIG.1. In such examples, the first metallization layer212may be employed for interconnection of devices in the circuit layer204. In other examples, including second external contacts214on the first metallization layers212, one or more additional ICs, or another package substrate (not shown) may be coupled to the first side SIC1of the IC200and through the IC200to a package substrate and external circuits (not shown). As the first IC102was described in detail above and is substantially the same as the IC200inFIG.2, the IC200will not be described further here.

FIG.2is provided here for purposes of comparison to the IC300inFIG.3. The IC300has a stiffening layer302on a front side SIC1of a circuit layer304and includes vias306to couple first metallization layers308to second contacts310. The IC300also includes second metallization layers312that are optionally coupled to first contacts314.

The IC300inFIG.3differs from the IC200inFIG.2only with respect to a location of the stiffening layer302. In the IC300, the stiffening layer302is coupled to the first metallization layers308on the front side SIC1of the circuit layer304rather than on the second metallization layers312on the back side SIC2, as shown inFIG.2. In such example, bottom metal layers BM0-BMM of the second metallization layers312may be used for interconnection of devices (not shown) in the circuit layer304and the metal layers M0-MN may be used for both interconnection of devices within the circuit layer304and to connect the circuit layer304to the first contacts314by way of the vias306through the stiffening layer302.

Fabrication processes can be employed to fabricate an IC including a stiffening layer on a first side of a circuit layer with vias extending through the stiffening layer to couple metal layers of a plurality of second metallization layers to first external contacts including but not limited to the ICs100,200, and300inFIGS.1-3. In this regard,FIG.4is a flowchart illustrating an exemplary fabrication process400of fabricating an IC200including a stiffening layer202on a back side SIC2of a circuit layer204with vias206extending through the stiffening layer202to couple bottom metal layers BM0-BMM of second metallization layers208to first external contacts210. The fabrication process400inFIG.4is discussed with regard to the IC200inFIG.2, but note that the fabrication process400inFIG.4is not limited to fabricating an IC including a stiffening layer202on a back side SIC2of a circuit layer204with vias206extending through the stiffening layer202to couple bottom metal layers BM0-BMM of second metallization layers208to first external contacts210as shown inFIG.2.

In this regard, exemplary steps in fabricating the IC200inFIG.2include forming a circuit layer204(block402inFIG.4), forming first metallization layers212on the first side SIC1and disposed on the circuit layer204(block404), and forming second metallization layers208on a second side SIC2of the circuit layer204opposite to the first side SIC1and coupled to the circuit layer204(block406). The method400further includes disposing a stiffening layer202on one of the first metallization layers212and the second metallization layers208(block408) and forming a first via206extending through the stiffening layer202from a first side SSL1of the stiffening layer202adjacent to the one of the first metallization layers212and the second metallization layers208to a first external contact210on a second side SSL2of the stiffening layer202(block410). Other fabrication processes can also be employed to fabricate the IC200including a stiffening layer202on a back side SIC2of a circuit layer204with vias206extending through the stiffening layer202to couple bottom metal layers BM0-BMM of second metallization layers208to first external contacts210including but not limited to the ICs102,200, and300inFIGS.1-3. In this regard,FIGS.5A-5Mare a flowchart illustrating another exemplary fabrication process500of fabricating an IC200including a stiffening layer202on a back side SIC2of a circuit layer204with vias206extending through the stiffening layer202to couple bottom metal layers BM0-BMM of second metallization layers208to first external contacts210including but not limited to the ICs102,200, and300inFIGS.1-3.FIGS.6A-6Mare exemplary fabrication stages600A-600M during fabrication of the IC200including a stiffening layer202on a back side SIC2of a circuit layer204with vias206extending through the stiffening layer202to couple bottom metal layers BM0-BMM of second metallization layers208to first external contacts210, according to the fabrication process500inFIGS.5A-5M. The fabrication process500inFIGS.5A-5Mwill now be discussed in conjunction with the exemplary fabrication stages600A-600M inFIGS.6A-6Musing the IC200inFIG.2as an example. However, note that the fabrication process500inFIGS.5A-5Mrepresented by the fabrication stages600A-600M inFIGS.6A-6Mcould also be applicable to fabricate the IC102inFIG.1and the IC300inFIG.3as well.

In this regard, as shown in the fabrication stage500A inFIG.5A, a first step in the fabrication process includes forming a circuit layer502on a semiconductor substrate504. As noted above, the circuit layer602includes devices such as transistors coupled in circuits that provide functionality of the IC600. The method500further includes forming first metallization layers606on the first, front side SIC1of the circuit layer602. The first metallization layers606include metal layers M0-MN separated by dielectric material608. Forming the first metallization layers606includes repeating a sequence including forming a layer of a dielectric material608, forming vias610through the layer of dielectric material608, and forming one of the metal layers M0-MN. Such sequence is repeated until metal layer MN is formed. Step500A also includes forming a first non-conductive (e.g., oxide) layer614on the first metallization layers606, in particular the metal layer MN. Each of the metal layers MO-MN includes interconnects616that extend parallel to the circuit layer602(e.g., in a plane including the X-axis and the Y-axis). In this regard, the vias610extend between metal layers M0-MN in a first direction or “vertically” (e.g., in the Z-axis direction) and the interconnects616extend in second and third directions (e.g., the X-axis and Y-axis directions) or “horizontally”, which are orthogonal to each other and to the first direction.

FIG.6Bis the cross-sectional side view in the fabrication stage600B of fabricating the IC600according to step500B of the method500inFIG.5B. The step500B includes coupling a first carry wafer618to the first non-conductive layer614.

FIG.6Cis the cross-sectional side view in the fabrication stage600C of fabricating the IC600according to step500C of the method500inFIG.5C. The step500C includes thinning the semiconductor substrate604on the back side SIC2of the circuit layer602. The semiconductor substrate is thinned to the back sides of devices in the circuit layer602.

FIG.6Dis the cross-sectional side view in the fabrication stage600D of fabricating the IC600according to step500D of the method500inFIG.5D. The step500D includes forming second metallization layers620on the back side SIC2of the circuit layer602(shown inverted fromFIG.6C). Forming the second metallization layers620includes repeating a sequence including forming a layer of a dielectric material622, forming vias624through the layer of dielectric material622, and forming one of the bottom metal layers BM0-BMM. Such sequence is repeated until bottom metal layer BMM is formed. The bottom metal layers BM0-BMM include horizontal interconnects coupled in the vertical direction by the vias624.

FIG.6Eis the cross-sectional side view in the fabrication stage600E of fabricating the IC600according to step500E of the method500inFIG.5E. The step500E includes forming a film (e.g., oxide)626on a stiffening layer substrate628, which may be a semiconductor (e.g., silicon) substrate, forming vias630(e.g., TSVs) through the film626and through a first thickness T1of the stiffening layer substrate628.

FIG.6Fis the cross-sectional side view in the fabrication stage600F of fabricating the IC600according to step500F of the method500inFIG.5F. The step500F includes attaching a second carry wafer632to the stiffening layer substrate628and thinning the stiffening layer substrate628to a stiffening layer634. In particular, the second carry wafer632is coupled to the film626and the back side of the stiffening layer substrate628is thinned by mechanical grinding and/or chemical means. The stiffening layer substrate628is thinned to the thickness T1, leaving the stiffening layer634having the thickness T1and a surface636.

FIGS.6G and6Hare the cross-sectional side views in the fabrication stages600G and600H of fabricating the IC600according to steps500G and500H of the method500inFIGS.5G and5H. The steps500G include coupling a third carry wafer638to the stiffening layer634, as shown inFIG.6G, and removing the second carry wafer632from the stiffening layer634, as shown inFIG.6H. The third carry wafer638is coupled to the surface636of the stiffening layer634. Removing the second carry wafer632exposes the film626on the stiffening layer634.

FIG.6Iis the cross-sectional side view in the fabrication stage600I of fabricating the IC600according to step500I of the method500inFIG.5I. The step500I includes coupling the stiffening layer634(shown inFIG.6H) to the second metallization layers620(shown inFIG.6D). In particular, while the stiffening layer634is attached to the third carry wafer638, the film626is coupled to the bottom metal layer BMM of the second metallization layers620on the back side SIC2of the circuit layer602, which is attached to the first carry wafer618.

FIGS.6J and6Kare the cross-sectional side views in the fabrication stages600J and600K of fabricating the IC600according to steps500J and500K of the method500inFIGS.5J and5K. The step500J includes removing the third carry wafer638(seeFIG.6I) from the stiffening layer634and step500K includes forming a second non-conductive layer640on the stiffening layer634. The second non-conductive layer640may be patterned to expose the vias630that were formed in the stiffening layer634.

FIGS.6L and6Mare the cross-sectional side views in the fabrication stages600L and600M of fabricating the IC600according to steps500L and500M of the method500inFIGS.5L and5M. The step500L includes removing the first carry wafer618(seeFIG.6K) from the first non-conductive layer614, which is on the front side SIC1of the circuit layer602. Step500M includes forming first external contacts642on the back side SIC2of the circuit layer602and (optionally) forming second external contacts644on the front side SIC1of the circuit layer602. The first external contacts642are formed on the patterned second non-conductive layer640and coupled to the exposed vias630. Similarly, the second contacts644are formed on the first non-conductive layer614, which is also patterned, and coupled to the metal layer MN of the first metallization layers606.

Electronic devices that include ICs including first and second metallization layers on opposite sides of a circuit layer and a stiffening layer including vias coupled to one of the metallization layers, such as the ICs inFIGS.1-3and6A-6Mand according to, but not limited to, any of the exemplary fabrication processes inFIGS.4and5A-5M, and according to any aspects disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, laptop computer, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard,FIG.7illustrates a block diagram of an exemplary wireless communications device700that includes radio frequency (RF) components formed from one or more ICs702, wherein any of the ICs702can include first and second metallization (backside power rail and metallization) layers on opposite sides of a circuit layer and a stiffening layer including vias coupled to one of the metallization layers, such as the ICs inFIGS.1-3and6A-6Mand according to, but not limited to, any of the exemplary fabrication processes inFIGS.4and5A-5M, and according to any aspects disclosed herein. The wireless communications device700may include or be provided as examples in any of the above-referenced devices. As shown inFIG.7, the wireless communications device700includes a transceiver704and a data processor706. The data processor706may include a memory to store data and program codes. The transceiver704includes a transmitter708and a receiver710, which support bi-directional communications. In general, the wireless communications device700may include any number of transmitters708and/or receivers710for any number of communication systems and frequency bands. All or a portion of the transceiver704may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

The transmitter708or the receiver710may be implemented with a super-heterodyne or direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In the direct-conversion architecture, a signal is frequency-converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device700inFIG.7, the transmitter708and the receiver710are implemented with the direct-conversion architecture.

In the transmit path, the data processor706processes data to be transmitted and provides I and Q analog output signals to the transmitter708. In the exemplary wireless communications device700, the data processor706includes digital-to-analog converters (DACs)712(1),712(2) for converting digital signals generated by the data processor706into I and Q analog output signals, e.g., I and Q output currents, for further processing.

Within the transmitter708, lowpass filters714(1),714(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion. Amplifiers (AMPs)716(1),716(2) amplify the signals from the lowpass filters714(1),714(2), respectively, and provide I and Q baseband signals. An upconverter718upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator722through mixers720(1),720(2) to provide an upconverted signal724. A filter726filters the upconverted signal724to remove undesired signals caused by the frequency upconversion and noise in a receive frequency band. A power amplifier (PA)728amplifies the upconverted signal724from the filter726to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch730and transmitted via an antenna732.

In the receive path, the antenna732receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch730and provided to a low noise amplifier (LNA)734. The duplexer or switch730is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA734and filtered by a filter736to obtain a desired RF input signal. Downconversion mixers738(1),738(2) mix the output of the filter736with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator740to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs742(1),742(2) and further filtered by lowpass filters744(1),744(2) to obtain I and Q analog input signals, which are provided to the data processor706. In this example, the data processor706includes analog-to-digital converters (ADCs)746(1),746(2) for converting the analog input signals into digital signals to be further processed by the data processor706.

In the wireless communications device700ofFIG.7, the TX LO signal generator722generates the I and Q TX LO signals used for frequency upconversion, while the RX LO signal generator740generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A TX phase-locked loop (PLL) circuit748receives timing information from the data processor706and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator722. Similarly, an RX PLL circuit750receives timing information from the data processor706and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator740.

FIG.8illustrates a block diagram of an example of a processor-based system800that can employ ICs including first and second metallization layers on opposite sides of a circuit layer and a stiffening layer including vias coupled to one of the metallization layers, such as the ICs inFIGS.1-3and6A-6Mand according to, but not limited to, any of the exemplary fabrication processes inFIGS.4and5A-5M. In this example, the processor-based system800includes one or more central processor units (CPUs)802. which may also be referred to as CPU or processor cores, each including one or more processors804. The CPU(s)802may have cache memory806coupled to the processor(s)804for rapid access to temporarily stored data. The CPU(s)802is coupled to a system bus808and can intercouple master and secondary device devices included in the processor-based system800. As is well known, the CPU(s)802communicates with these other devices by exchanging address, control, and data information over the system bus808. For example, the CPU(s)802can communicate bus transaction requests to a memory controller810as an example of a slave device. Although not illustrated inFIG.8, multiple system buses808could be provided wherein each system bus808constitutes a different fabric.

Other master and slave devices can be connected to the system bus808. As illustrated inFIG.8, these devices can include a memory system812that includes the memory controller810and one or more memory arrays814, one or more input devices816, one or more output devices818, one or more network interface devices820, and one or more display controllers822, as examples. The input device(s)816can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s)818can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s)820can be any device configured to allow an exchange of data to and from a network824. The network824can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s)820can be configured to support any type of communications protocol desired.

The CPU(s)802may also be configured to access the display controller(s)822over the system bus808to control information sent to one or more displays826. The display controller(s)822sends information to the display(s)826to be displayed via one or more video processors828, which process the information to be displayed into a format suitable for the display(s)826. The display(s)826can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light-emitting diode (LED) display, etc.

Implementation examples are described in the following numbered clauses:1. An integrated circuit (IC), comprising:a circuit layer;a plurality of first metallization layers disposed on a first side of the circuit layer and coupled to the circuit layer;a plurality of second metallization layers disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer;a stiffening layer disposed on one of the plurality of first metallization layers and the plurality of second metallization layers; anda first via extending through the stiffening layer to couple the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact on the stiffening layer.2. The IC of clause 1, wherein the circuit layer comprises:a semiconductor layer comprising devices;a first isolation layer disposed on the devices on the first side of the circuit layer; anda second isolation layer disposed on the second side of the circuit layer.3. The IC of clause 2, wherein the first isolation layer and the second isolation layer comprise one of inter-layer dielectric (ILD) material, inter-metal dielectric (IMD) material, and shallow trench isolation (STI) material.4. The IC of any of clause 1 to clause 3, wherein a thickness of the circuit layer is less than two (2) microns (μm).5. The IC of any of clause 1 to clause 4, wherein the stiffening layer has a thickness in a range of twenty (20) to one hundred (100) microns (μm).6. The IC of any of clause 1 to clause 5, wherein a thickness of the stiffening layer is at least ten (10) times a thickness of the circuit layer.7. The IC of clause 2 or clause 3, further comprising back side vias extending from the semiconductor layer and through the second isolation layer to couple the devices to the plurality of second metallization layers.8 The IC of clause 2, clause 3, or clause 7, further comprising front side vias extending through the first isolation layer to couple the devices to the plurality of first metallization layers.9. The IC of any of clause 1 to clause 8, wherein a height-to-width ratio of the first via is in a range of five to one (5:1) to ten to one (10:1).10. The IC of any of clause 1 to clause 9, wherein a thickness of a first plurality of metal layers in the plurality of first metallization layers is in a range of 1.0 to 3.0 microns (μm).11. The IC of any of clause 1 to clause 10, wherein a thickness of a second plurality of metal layers in the plurality of second metallization layers is in a range of 1.0 to 3.0 microns (μm).12. The IC of any of clause 1 to clause 11, wherein the stiffening layer comprises silicon.13. The IC of any of clause 1 to clause 12, wherein the stiffening layer comprises a trench capacitor coupled to the first via.14. The IC of any of clause 1 to clause 13, further comprising a second contact coupled to the other one of the plurality of first metallization layers and the plurality of second metallization layers and configured to couple the circuit layer to an external circuit.15. The IC of any of clause 1 to clause 14, integrated into an integrated circuit package.16. The IC of any of clause 1 to clause 15, integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.17. A method of fabricating an integrated circuit (IC), the method comprising:forming a circuit layer;forming a plurality of first metallization layers on a first side of the circuit layer;forming a plurality of second metallization layers on a second side of the circuit layer opposite to the first side;disposing a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers; andforming a first via extending through the stiffening layer from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact on a second side of the stiffening layer.18. An integrated circuit (IC) package comprising:a first package substrate; andan IC comprising:a circuit layer;a plurality of first metallization layers disposed on a first side of the circuit layer and coupled to the circuit layer;a plurality of second metallization layers disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer;a stiffening layer disposed on one of the plurality of first metallization layers and the plurality of second metallization layers; anda first via extending through the stiffening layer from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact on a second side of the stiffening layer,wherein the first contact is coupled to the first package substrate.

19. The IC package of clause 18, further comprising:a second contact coupled to the other one of the plurality of first metallization layers and the plurality of second metallization layers; anda second IC coupled to the second contact.