Gate all around device structure and Fin field effect transistor (FinFET) device structure

A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack structure wrapping around the channel region.

BACKGROUND

Multiple gate field-effect transistors (MuGFETs) are a recent development in semiconductor technology which typically are metal oxide semiconductor FETs (MOSFETs) that incorporate more than one gate into a single device. One type of MuGFET is referred to as a FinFET, which is a transistor structure with a fin-like semiconductor channel that is raised vertically away from a substrate of an integrated circuit. A recent design for FinFETs is a gate all around (GAA) FinFET, which has a gate material that surrounds a channel region on all sides.

Although existing MuGFET devices and methods of fabricating MuGFET devices have been generally adequate for their intended purpose, they have not been entirely satisfactory in all aspects.

DETAILED DESCRIPTION

Embodiments for forming a vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided.FIGS. 1A-1Oshow cross-sectional representations of various stages of forming a semiconductor device structure100, in accordance with some embodiments of the disclosure.

Referring toFIG. 1A, a substrate102is provided. The substrate102may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate102may include other elementary semiconductor materials such as germanium (Ge). In some embodiments, the substrate102is made of a compound semiconductor such as silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate102is made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP). In some embodiments, the substrate102includes an epitaxial layer. For example, the substrate102has an epitaxial layer overlying a bulk semiconductor. In some other embodiments, the substrate102may be a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate.

Afterwards, a number of alignment marks104are formed in the substrate102. A hard mask layer106is formed on the alignment marks104and the substrate102. The hard mask layer106may be made of silicon oxide, silicon nitride, silicon oxynitride, or another applicable material.

Afterwards, a photoresist layer108is formed on the hard mask layer106and patterned to form the patterned photoresist layer108. In some embodiments, the photoresist layer108is pattered by a patterning process. The patterning process includes a photolithography process and an etching process. Photolithography processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

After the photoresist layer108is patterned, the hard mask layer106is patterned by using the patterned photoresist layer108as a mask as shown inFIG. 1B, in accordance with some embodiments of the disclosure. Therefore, the patterned hard mask layer106is formed.

Afterwards, a portion of the substrate102is removed by using the patterned hard mask layer106as a mask. The substrate102is removed by an etching process, such as a wet etching process or a dry etching process. As a result, a recess109is formed in the substrate102. The substrate102is divided into two regions including a device region10and an edge region20. The recess109is formed in the device region10, and the alignment marks104are formed in the edge region20. It should be noted that a top surface of the substrate102in device region10is lower than a top surface of the substrate102in the edge region20. The height difference between two top surfaces is marked as height H. In some embodiments, the height H is in a range from about 50 nm to about 300 nm.

After a portion of the substrate102is removed, a photoresist layer110is formed on the substrate102and then patterned as shown inFIG. 1C, in accordance with some embodiments of the disclosure. The patterned photoresist layer110is obtained and it is used to cover the underlying substrate102. Therefore, a portion of the substrate102is exposed.

Afterwards, a first implantation process50is performed on the exposed substrate102to form a first conductive type well region112. In some embodiments, the first conductive type well region112is an N-type well region.

After the first conductive type well region112is formed, a photoresist layer111is formed on the substrate102and then patterned as shown inFIG. 1D, in accordance with some embodiments of the disclosure. The patterned photoresist layer111is formed on the first conductive type well region112to expose a portion of the substrate102.

Afterwards, a second implantation process52is performed on the exposed substrate102to form a second conductive type well region114in the substrate102. The second conductive type well region114is adjoined to the first conductive type well region112. In some embodiments, the second conductive type well region114is a P-type well region.

After the second conductive type well region114is formed, a spacer116is formed on the first conductive type well region112, the second conductive type well region114, the hard mask layer106, and the substrate102as shown inFIG. 1E, in accordance with some embodiments of the disclosure. It should be noted that the spacer116is formed on a bottom portion and sidewall portion of the recess109.

The spacer116is made of silicon oxide, silicon nitride, silicon oxynitride or other applicable material. In some embodiments, the spacers116are formed by an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD) process or a low pressure chemical vapor deposition (LPCVD).

After the spacer116is formed, a portion of the spacer116is removed by a dry etching process as shown inFIG. 1F, in accordance with some embodiments of the disclosure. The remaining spacer116is formed on the sidewall portion of the recess109.

After the dry etching process, a first semiconductor material122, a second semiconductor material124and the third semiconductor material126are sequentially formed on the first conductive type well region112and the second conductive type well region114as shown inFIG. 1G, in accordance with some embodiments of the disclosure. In some embodiments, the first semiconductor material122is an epitaxial material. In some embodiments, the second semiconductor material124is an epitaxial material. In some embodiments, the third semiconductor material126is an epitaxial material.

In some embodiment, the first semiconductor material122, the second semiconductor material124and the third semiconductor material126are formed separately. In some embodiments, two materials of the first semiconductor material122and the second semiconductor material124, the first semiconductor material122and third semiconductor material126, or the second semiconductor material124and the third semiconductor material126are formed by an epitaxial process. In some other embodiments, the first semiconductor material122, the second semiconductor material124and the third semiconductor material126are formed by an epitaxial process.

It should be noted that because the spacer116is a dielectric/amorphous layer, the growth rate of a portion of the first semiconductor material122which is formed on the spacer116is slower than that which is formed on the first conductive type well region112or the second conductive type well region114. Therefore, the first semiconductor material122has a horizontal portion122aand a sloped portion122bsloping downward towards the spacer116.

In addition, since the second semiconductor material124is formed on the first semiconductor material122, the growth shape of the second semiconductor material124lines along the shape of the first semiconductor material122. Therefore, the second semiconductor material124also has a horizontal portion124aand a sloped portion124bsloping downward towards the spacer116. Furthermore, the third semiconductor material126has a horizontal portion126aand a sloped portion126bsloping downward towards the spacer116.

After the third semiconductor material126is formed, a polishing process is performed on the third semiconductor material126as shown inFIG. 1H, in accordance with some embodiments of the disclosure. Afterwards, the hard mask layer106is removed.

Afterwards, a hard mask layer128is formed on the third semiconductor material126as shown inFIG. 1I, in accordance with some embodiments of the disclosure. The hard mask layer128is then patterned to cover a portion of the first semiconductor material122, the second semiconductor material124and the third semiconductor material126. Afterwards, a portion of the second semiconductor material124and a portion of the third semiconductor material126are removed to form a recess129on the first conductive type well region112.

After the second recess129is formed, a second spacer130is formed on a bottom portion and sidewall portion of the second recess129as shown inFIG. 1J, in accordance with some embodiments of the disclosure. In addition, the second spacer130is formed on the hard mask layer128.

Afterwards, a portion of the second spacer130is removed as shown inFIG. 1K, in accordance with some embodiments of the disclosure. As a result, the second spacer130is formed on the sidewall portions of the first semiconductor material122, the remaining second semiconductor material124and the third semiconductor material126. In some embodiments, the second spacer130is made of silicon nitride (SiNx), silicon oxide (SiO2), silicon carbon nitride (SiCN) or the like.

Afterwards, a fourth semiconductor material132, a fifth semiconductor material134and a sixth semiconductor material136are formed on the first conductive type well region112and on the second spacer130as shown inFIG. 1L, in accordance with some embodiments of the disclosure. The fourth semiconductor material122, the fifth semiconductor material134and the sixth semiconductor material136independently includes Si, Ge, SiGe, SiC, InSb, InAs, GaAs, GaSb, InGaSb, InGaAs, or combinations thereof. In some embodiments, the fourth semiconductor material132, the fifth semiconductor material134and the sixth semiconductor material136are formed by the epitaxial processes.

In some embodiments, the first semiconductor material132is an epitaxial material. In some embodiments, the second semiconductor material134is an epitaxial material. In some embodiments, the third semiconductor material136is an epitaxial material.

In some embodiment, the first semiconductor material122, the second semiconductor material124and the third semiconductor material126are formed separately. In some embodiments, two materials of the first semiconductor material122and the second semiconductor material124, the first semiconductor material122and third semiconductor material126, or the second semiconductor material124and the third semiconductor material126are formed by an epitaxial process. In some other embodiments, the first semiconductor material122, the second semiconductor material124and the third semiconductor material126are formed by an epitaxial process.

Like the first semiconductor material122, the fourth semiconductor material132has a horizontal portion132aand a sloped portion132bsloping downward towards the second spacer130. In addition, the fifth semiconductor material134has a horizontal portion134aand a sloped portion134bsloping downward towards the second spacer130. The sixth semiconductor material136has a horizontal portion136aand a sloped portion136bsloping downward towards the second spacer130.

Afterwards, a polishing process is performed on the sixth semiconductor material136, and the hard mask layer128is removed. Afterwards, an isolation structure140is formed between the first semiconductor material122and the fourth semiconductor material132as shown inFIG. 1M, in accordance with some embodiments of the disclosure.

Afterwards, a portion of the fourth semiconductor material132, a portion of the fifth semiconductor134and a portion of the sixth semiconductor material136are removed to form a number of first vertical structures150, and a portion of the first semiconductor material122, a portion of the second semiconductor material124and a portion of the third semiconductor material126are removed to form a number of second vertical structures152as shown inFIG. 1N, in accordance with some embodiments of the disclosure.

In the first vertical structures150, a number of stack structures including the fourth semiconductor material132, the fifth semiconductor material134and the sixth semiconductor material136. The fourth semiconductor material132is used as a source region, the fifth semiconductor material134is used as a channel region, and the sixth semiconductor material136is used as a drain region. The channel region is formed between the source region and the drain region.

In the second vertical structures152, there are a number of stack structures that include the first semiconductor material122, the second semiconductor material124and the third semiconductor material126. The first semiconductor material122is used as a source region, the second semiconductor material124is used as a channel region, and the third semiconductor material126is used as a drain region.

As shown inFIG. 1N, in the first vertical structures150, a first distance D1between the horizontal portion134aof the fifth semiconductor material134(also called as the channel region) and the substrate102is greater than a second distance D2between sloped portion134bof the fifth semiconductor material134and the substrate102. In the second vertical structures152, a third distance D3between the horizontal portion124aof the second semiconductor material124(also called as the channel region) and the substrate102is greater than a fourth distance D4between the sloped portion124bof the second semiconductor material124and the substrate102.

After the first vertical structures150and the second vertical structures152are formed, a gate stack structure is formed in a space between two adjacent first vertical structures150and152as shown inFIG. 1O, in accordance with some embodiments of the disclosure.

The gate stack structure wraps around the channel region (such as the fifth semiconductor material134or the second semiconductor material124) to form a gate all around (GAA) device (transistor). In other words, the gate stack structure encircles the channel region. The gate stack structure includes an interfacial layer (IL) (not shown), a high-k dielectric layer162and a metal gate electrode164.

In addition, gate spacers160are formed between the source region and the high-k dielectric layer162, and between the drain region and the metal gate electrode164.

As shown inFIG. 1O, a first transistor structure150′ is formed on the first conductive type well region112, and a second transistor structure152′ is formed on the second conductive type well region114. In some embodiments, the first transistor structure150′ is a PMOS transistor structure and the second transistor structure152′ is an NMOS transistor structure. In some embodiments, because the epitaxial process for forming the first semiconductor material122and the fourth semiconductor material132is performed before the formation of the isolation structure, the fabrication processes fromFIG. 1AtoFIG. 1Oare called an epi first process.

It should be noted that the spacer130(such as silicon nitride) is formed on the sidewall portion of the first semiconductor material122, the second semiconductor material124and the third semiconductor material126. As a result, the fourth semiconductor material132, the fifth semiconductor material134and sixth semiconductor material136do not tend to form on the spacer130. Therefore, the fourth semiconductor material132, the fifth semiconductor material134and the sixth semiconductor material136respectively have sloped portions sloping downward toward the spacer130.

It should be noted that if no spacer formed adjacent to the sidewall of the first semiconductor material, the fourth semiconductor material may have a sloped portion sloping upward to the first semiconductor material. Likewise, the fifth semiconductor material which is used as a channel region also has an upward-sloping portion. The upward sloped portion has a smaller slope than the downward-sloping portion of the disclosure. However, the slope of the upward-sloping portion is smoothly changed for a wide range. Therefore, a spatial non-uniform channel length (Lg) is obtained when no spacer is formed adjacent to the sidewall portion of the first semiconductor material, the second semiconductor material and third semiconductor material. Compared with the upward-sloping portion, the slope of the downward-sloping portion of the disclosure is rapidly changed for a small range. With the spacer design, the downward-sloping portion of the disclosure is shorter and the uniform channel length (Lg) is obtained.

Referring toFIG. 1Nagain, the horizontal portion134aof the fifth semiconductor material134(or called as the channel region) has a first channel length L1, and the sloped portion134bof the fifth semiconductor material134has a second channel length L2. In some embodiments, a ratio (L1/L2) of the first channel length L1to the second channel length L2is in a range from about 30% to about 95%. Compared with the channel region having upward-sloping portion, a special channel length uniformity is improved by the downward-sloping channel portion.

The horizontal portion124aof the second semiconductor material124(or called as the channel region) has a third channel length L3, and the sloped portion124bof the second semiconductor material124has a fourth channel length L4. In some embodiments, a ratio (L3/L4) of the third channel length L3to the fourth channel length L4is in a range from about 30% to about 95%.

FIG. 2Ashows a top-view representation of the first vertical structures150and the second vertical structures152, in accordance with some embodiments of the disclosure. Each of the first vertical structures150and the second vertical structures152has a circular shape and is called a nanowire.

FIG. 2Bshows a top-view representation of the first vertical structures150and the second vertical structures152, in accordance with some embodiments of the disclosure. As shown inFIG. 2B, each of the first vertical structures150and the second vertical structures152has a bar-like shape along the Y-axis.

FIG. 2Cshows a top-view representation of the first vertical structures150and the second vertical structures152, in accordance with some embodiments of the disclosure. As shown inFIG. 2B, each of the first vertical structures150and the second vertical structures152has a bar-like shape along the X-axis.

FIGS. 3A-3Mshow cross-sectional representations of various stages of forming a horizontal gate all around (HGAA) device structure200, in accordance with some embodiments of the disclosure.

Referring toFIG. 3A, the substrate102is divided into the device region10and the edge region20. The first conductive type well region112and the second conductive type well region114are formed in the device region10. The alignment marks104are formed in the edge region20, and the hard mask layer106is formed on the alignment marks104. The recess109is formed in the device region10, and a spacer116is formed on the sidewall portion of the recess109.

Afterwards, the first semiconductor material122and the second semiconductor material124are formed on the first conductive type well region112and the second conductive type well region114as shown inFIG. 3B, in accordance with some embodiments of the disclosure.

It should be noted that the first semiconductor material122is formed by an epitaxial process, and it has a horizontal portion122aand a sloped portion122bsloping downward toward the spacer116. Like the first semiconductor material122, the second semiconductor material124also has a horizontal portion124aand a sloped portion124bsloping downward toward the spacer116.

After the second semiconductor material124is formed, a polishing process is performed on the second semiconductor material124as shown inFIG. 3C, in accordance with some embodiments of the disclosure. Afterwards, the hard mask layer106is removed.

Afterwards, the hard mask layer128is formed on the second semiconductor material124and patterned as shown inFIG. 3D, in accordance with some embodiments of the disclosure. Afterwards, a portion of the first semiconductor material122and the second semiconductor material124are removed to form the recess129.

After the recess129is formed, the second spacer130is formed on the sidewall of the first semiconductor material122and the second semiconductor material124as shown inFIG. 3E, in accordance with some embodiments of the disclosure.

After the second spacer130is formed, the fourth semiconductor material132and the fifth semiconductor material134are formed on the first conductive type well region112as shown inFIG. 3F, in accordance with some embodiments of the disclosure. It should be noted that the fourth semiconductor material132has a horizontal portion132aand a sloped portion132b, and the fifth semiconductor material134has a horizontal portion134aand a sloped portion134b.

Afterwards, a polishing process is performed on the fifth semiconductor material134, and the hard mask layer128is removed. Afterwards, the isolation structure140is formed between the first semiconductor material122and the fourth semiconductor material132as shown inFIG. 3G, in accordance with some embodiments of the disclosure. A fin structure is made of the first semiconductor material122and the second semiconductor material124, and another fin structure is made of the fourth semiconductor material132and the fifth semiconductor material134.

Afterwards, a first dummy gate electrode182ais formed on the fifth semiconductor material134, and a second dummy gate electrode182bis formed on the second semiconductor material124as shown inFIG. 3H, in accordance with some embodiments of the disclosure. In other words, the first dummy gate electrode182ais formed on the fin structure including the fifth semiconductor material134, and the second dummy gate electrode182bis formed on the fin structure including the second semiconductor material124.

Afterwards, a top portion of the isolation structure140is removed. The first sidewall spacers184aare formed on the sidewalls of the first dummy gate electrode182a, and the second sidewall spacers184bare formed on the sidewalls of the second dummy gate electrode182b. A first hard mask layer182ais formed on the first dummy gate electrode182a, and the second hard mask layer182bis formed on the second dummy gate electrode182b.

Afterwards, the first source/drain (S/D) structures186a, the second S/D structures186band an ILD layer190are formed as shown inFIG. 3I, in accordance with some embodiments of the disclosure.

At the left side of the isolation structure140, the first S/D structures186aare formed in the fifth semiconductor material134. The first S/D structures186aare adjacent to the first sidewall spacers184a. At the right side of the isolation structure140, the second S/D structures186bare formed in the second semiconductor material124.

After the ILD layer190is formed, the first dummy gate electrode182aand the second dummy gate electrode182bare removed as shown inFIG. 3J, in accordance with some embodiments of the disclosure. As a result, a first trench191ais formed by removing the first dummy gate electrode182a, and the second trench191bis formed by removing the second dummy gate electrode182b.

Afterwards, a photoresist layer202is formed on the first trench191aand on a portion of the ILD layer190as shown inFIG. 3K, in accordance with some embodiments of the disclosure. Afterwards, a portion of the first material122is removed to form a cavity193under the second material124.

FIG. 3K′ shows a perspective representation of region A of theFIG. 3K, in accordance with some embodiments of the disclosure.FIG. 3Kis a cross-section representation along the line XX′ ofFIG. 3K′. As shown inFIG. 3K′, the second trench191ais formed in the ILD layer190.

FIG. 3K-1shows a cross-section representation along the line Y1Y1′ ofFIG. 3K′. The cavity193is formed between the second semiconductor material124and the second conductive type well region114.

FIG. 3K-2shows a cross-section representation along the line Y2Y2′ ofFIG. 3K′. The second S/D structures186bare formed on the first semiconductor material122.

Afterwards, the photoresist layer202is removed, and another photoresist layer204is filled in the second trench191bas shown inFIG. 3L, in accordance with some embodiments of the disclosure. Afterwards, a portion of the first semiconductor material122is removed to form a cavity195under the fourth material134.

Afterwards, a first gate stack electrode196aand a second gate stack structure196bare filled into the first trench191aand the second trench191bas shown inFIG. 3M, in accordance with some embodiments of the disclosure. In some embodiments, the first gate stack electrode196aand the second gate stack structure196beach includes a high-k dielectric layer (not shown) and a metal layer.

FIG. 3M-1shows a cross-section representation along the line Y1Y1′ ofFIG. 3K′ after formation of the second gate stack structure196b, in accordance with some embodiments of the disclosure. It should be noted that the second gate stack structure196bencircles the second semiconductor124, and therefore a gate all around (GAA) structure is obtained.

FIGS. 4A-4Cshow cross-sectional representations of various stages of forming a fin field effect transistor (FinFET) device structure300, in accordance with some embodiments of the disclosure.

Referring toFIG. 4A, the isolation structure140is formed between the first conductive type well region112and the second conductive type well region114. The fifth semiconductor material134is formed on the fourth semiconductor material132, and the fourth semiconductor material132is formed on the first conductive type well region112. The first dummy gate electrode182ais formed on the fifth semiconductor material134. The ILD layer190is formed on the isolation structure140. The first dummy gate electrode182aand the second dummy gate electrode182bare formed in the ILD layer190.

In some embodiment, the channel region below the first dummy gate electrode182ais made of the combination of the fourth semiconductor material132and the fifth semiconductor material134or the combination of the first semiconductor material122and the second semiconductor material124. In some other embodiments, the channel region below the first dummy gate electrode182ais made of the first semiconductor material122or the fourth semiconductor material132.

It should be noted that the fifth semiconductor material134has a horizontal portion134aand a sloped portion134bsloping downward toward the isolation structure140.

After the ILD layer190is formed, the first dummy gate electrode182aand the second dummy gate electrode182bare removed as shown inFIG. 4B, in accordance with some embodiments of the disclosure. As a result, the first trench191aand the second trench191bare obtained.

Afterwards, the first gate stack electrode196aand the second gate stack structure196bare filled into the first trench191aand the second trench191bas shown inFIG. 4C, in accordance with some embodiments of the disclosure. In some embodiments, the first gate stack electrode196aand the second gate stack structure196beach includes a high-k dielectric layer (not shown) and a metal layer.

It should be noted that the fifth semiconductor134has a horizontal portion and a sloped portion sloping downward toward the isolation structure140and the ILD layer190. The channel length uniformity is improved by the downward-sloping portion.

Embodiments for forming a gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The GAA device structure includes a vertical structure formed on a substrate. The vertical structure includes a source region, a channel region and the drain region which are formed by the epitaxial processes. The source region, the source /the channel region or the source /the channel /the drain region has a horizontal portion and a downward-sloping portion. The vertical gate all around (VGAA) device structure includes a fin structure including a first semiconductor material and a second semiconductor material over the first semiconductor material. The second material includes a horizontal portion and a downward-sloping portion. The channel length uniformity is improved by the downward-sloping portion. Therefore, the performance of the semiconductor device structure and the VGAA device structure are improved.

In some embodiments, a vertical gate all around (VGAA) device structure is provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack wrapping around the channel region.

In some embodiments, a horizontal gate all around (HGAA) d device structure is provided. The HGAA device structure includes a substrate and an isolation structure formed on the substrate. The HGAA device structure also includes a fin structure extending above the substrate, and the fin structure includes a first semiconductor material and a second semiconductor material over the first semiconductor material. The HGAA device structure includes a gate stack structure encircling a portion of the second semiconductor material, and the second material includes a horizontal portion and a sloped portion, and the sloped portion sloping downward toward the isolation structure.

In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and an isolation structure formed on the substrate. The FinFET device structure includes a fin structure extending above the substrate, and the fin structure includes a first semiconductor material and a second semiconductor material over the first semiconductor material. The FinFET device structure further includes a gate stack structure formed on the fin structure, and the second semiconductor material includes a horizontal portion and a sloped portion sloping downward toward the isolation structure.