Method of forming a transistor with a channel region in a layer of composite material

The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and drain regions in a layer of composite material that includes silicon, germanium, and carbon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1is a cross-sectional view illustrating an example of a PMOS transistor100in accordance with the present invention.

FIG. 2is a cross-sectional view illustrating an example of a PMOS transistor200in accordance with an alternate embodiment of the present invention.

FIGS. 3A–3Eare a series of cross-sectional views illustrating an example of a method of forming a PMOS transistor in accordance with the present invention.

FIGS. 4A–4Dare cross-sectional views illustrating an example of a method of forming a PMOS transistor in accordance with an alternate embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows a cross-sectional view that illustrates an example of a PMOS transistor100in accordance with the present invention. As described in greater detail below, PMOS transistor100utilizes a layer of composite material to limit the diffusion of boron atoms into the channel region of the transistor, thereby minimizing undesired changes in the threshold voltage and channel length of the transistor.

As shown inFIG. 1, PMOS transistor100is formed in an n-type semiconductor material112, such as a substrate or well. In theFIG. 1example, material112is formed as an n-type well in a p-type substrate114. In addition, material112′ is surrounded by a trench isolation region116that has a substantially planar upper surface116A. (An isolation region with a non-planar upper surface can alternately be used.)

As further shown inFIG. 1, transistor100includes a layer of composite material120that is formed on semiconductor material112. In theFIG. 1example, composite layer120has an upper surface120A, and a lower surface120B that is substantially coplanar with the upper surface116A of trench isolation region116.

In the present invention, composite layer120includes a layer of n− silicon carbon120L that is formed on semiconductor material112, and a layer of n− silicon germanium120M, which is substantially free of carbon, that is formed over the layer of silicon carbon120L. (Layer120L can optionally include germanium.)

In addition, composite layer120includes a layer of n− silicon germanium carbon120U that is formed over the layer of silicon germanium120M, and a cap silicon layer120T that is formed on silicon germanium carbon layer120U. (Cap silicon layer120T can optionally be omitted. Layer120T allows a higher quality of gate oxide to be produced during manufacturing.) Composite layer120can alternately be formed to have additional layers.

The layers120T,120U,120M, and120L can have any thickness required by the device design. For example, silicon carbon layer120L can be 30 nM thick, silicon germanium layer120M can be 20 nM thick, silicon germanium carbon layer120U can be 10 nM thick, and cap silicon layer120T can be 10 nM thick.

Transistor100also includes spaced-apart p-type source and drain regions122and124that are formed in composite layer120, and a channel region126that is located between source and drain regions122and124. Source and drain regions122and124can be formed entirely within layer120, or can alternately extend into material112.

Transistor100additionally includes a thin layer of insulation material130, such as a layer of gate oxide, that is formed on composite layer120over channel region126. Further, transistor100includes a p-type polysilicon gate132that is formed on insulation layer130over channel region126.

FIG. 2shows a cross-sectional view that illustrates an example of a PMOS transistor200in accordance with an alternate embodiment of the present invention. PMOS transistor200is similar to PMOS transistor100and, as a result, utilizes the same reference numerals to designate structures that are common to both transistors.

As shown inFIG. 2, transistor200differs from transistor100with respect to the location of composite layer120. In transistor200, the bottom surface120B of composite layer120lies below the top surface116A of trench isolation region116, while the top surface120A of composite layer120is substantially coplanar with the top surface116A of trench isolation region116. Transistors100and200are operated in the same way as a conventional MOS transistor such as transistor100.

One advantage of the present invention is that the carbon in silicon layers120U and120L limits the vertical and lateral diffusion, respectively, of boron atoms into silicon germanium layer120M of channel region126during thermal cycling, such as annealing. As a result, the present invention limits undesirable shifts in the threshold voltage and shortening of the channel length that can lead to punch-through.

Another advantage of the present invention is that by locating the channel region in a silicon germanium layer, as described in the present invention, the mobility of the charge carriers (holes in a p-channel) is increased as compared to a channel region located in a region of silicon.

FIGS. 3A–3Eshow a series of cross-sectional views that illustrate an example of a method of forming a PMOS transistor in accordance with the present invention. As shown inFIG. 3A, the method utilizes a conventionally formed wafer that has an n-well312that is formed in a p-substrate314. In addition, the wafer has a trench isolation region316that isolates n-well312from laterally adjacent regions. Further, n-well312and trench isolation region316have upper surfaces that are substantially coplanar.

As shown inFIG. 3A, the method begins by forming and patterning a mask318, such as a hard mask, to expose n-well312. Next, a layer of composite material320is selectively epitaxially grown on the exposed surface of n-well312. With selective epitaxial growth, composite layer320is only grown on the silicon surface of n-well312.

Composite layer320is formed by first forming a layer of n−silicon carbon320L on the exposed surface of n-well312. After this, a layer of n− silicon germanium320M that is substantially free of carbon is formed on layer320L, followed by the formation of a layer of n− silicon germanium carbon320U on layer320M. Next, a layer of cap silicon320T that is free of carbon and germanium is optionally formed on layer320U.

The distribution and concentration of the carbon present in layers320L and320U depend on when the carbon is introduced, and the amount of carbon that is introduced, during the selective epitaxial growth process. By introducing and restricting carbon during the growth process, a plurality of silicon sub-layers with different carbon concentrations can be formed.

For example, the introduction of carbon near the beginning of the growth process forms lower silicon carbon layer320L. Stopping the introduction of carbon and introducing germanium near the middle of the process forms middle silicon germanium layer320M without carbon. In addition, re-introducing carbon near the end of the growth process forms upper silicon germanium carbon layer320U. Stopping the introduction of carbon and germanium, in turn, forms cap silicon layer320T.

Following the formation of composite layer320, the upper surface of layer320can optionally be planarized to create a substantially flat upper surface. The upper surface of composite layer320can be planarized using, for example, chemical mechanical polishing. Mask318is then removed.

As shown inFIG. 3B, once mask318has been removed, a layer of insulation material330, such as a layer of gate oxide, is formed over the exposed surfaces of composite layer320. Following this, a layer of polysilicon332is formed on gate oxide layer330. After polysilicon layer332has been formed, a mask334is formed and patterned on polysilicon layer332. Next, polysilicon layer332is anisotropically etched to remove the exposed regions of layer332that are not protected by mask334. Mask334is then removed.

As shown inFIG. 3C, the etch forms a gate342from polysilicon layer332. The method continues by implanting composite layer320and gate342with a p-type dopant344. The implant dopes gate342, and forms lightly-doped p-type regions352A and354A in composite layer320. Turning toFIG. 3D, a layer of insulation material362, such as an oxide, is next formed over trench isolation region316, gate oxide layer330, and gate342.

Following this, as shown inFIG. 3E, insulation material362is anisotropicly etched to remove insulation material from the top surfaces of trench isolation region316, portions of layer330, and gate342. The anisotropic etch forms an insulating spacer364on the side walls of gate342.

The method continues by again implanting composite layer320and gate342with p-type dopant atoms370. During the second implant, insulating spacer364blocks dopant atoms from entering the portions of source region352A and drain region354A that lie below insulating spacer364.

The second implant forms a heavily-doped p-type source region352B that contacts adjacent lightly doped p-type source region352A. In addition, the second implant also forms a heavily-doped p-type drain region354B that contacts adjacent lightly-doped p-type drain region354A. The second implant further dopes gate342. Following the second implant, the wafer is annealed to repair lattice damage caused by the implants. After the wafer has been annealed, the method continues with conventional back end processing steps.

FIGS. 4A–4Dshow a series of cross-sectional views that illustrate a method of forming a PMOS transistor in accordance with the present invention. As above, the method utilizes a conventionally formed wafer that has an n-well412that is formed in a p-substrate414. In addition, the wafer has a trench isolation region416that isolates n-well412from laterally adjacent regions. Further, n-well412and trench isolation region416have upper surfaces that are substantially coplanar.

As shown inFIG. 4A, the method begins by forming and patterning a mask418that exposes n-well412. Next, the exposed regions of n-well412are etched to remove a portion of n-well412so that a top surface412T of n-well412is recessed below the top surface of trench isolation region416. Mask418is then removed.

Next, as shown inFIG. 4B, a layer of composite material420is selectively epitaxially grown on the recessed surface412T of n-well412. (Composite layer420can alternately be epitaxially grown.) Composite layer420is formed by first forming a layer of n− silicon carbon420L on the exposed surface of n-well412. After this, a layer of n− silicon germanium420M that is substantially free of carbon is formed on layer420L, followed by the formation of a layer of n− silicon germanium carbon420U on layer420M. Next, a layer of cap silicon420T that is free of carbon and germanium is formed on layer420U.

As shown inFIG. 4C, after composite layer420has been grown, layer420is planarized using, for example, chemical-mechanical polishing. The planarization step forms composite layer420with a substantially planar upper surface that is substantially coplanar with the upper surface of trench isolation region416.

Once composite layer420has been formed and planarized, a layer of insulation material422, such as a layer of gate oxide, is formed over the exposed surfaces of layer420. Following this, a layer of polysilicon424is formed on gate oxide layer422. After polysilicon layer424has been formed, a mask426is formed and patterned on polysilicon layer424.

Next, as shown inFIG. 4D, polysilicon layer424is anisotropically etched to remove the exposed regions of layer424that are not protected by mask426. Mask426is then removed. The etch forms a gate430from polysilicon layer424. The method then continues as described above to form a source region, a spaced-apart drain region, and a side wall spacer. One of the advantages of the formation steps described inFIGS. 4A–4Dis that a transistor can be formed that has significantly less variation in surface planarity.

It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.