Buffered writes and memory page control

Machine-readable media, methods, and apparatus are described to issue transactions to a memory. In some embodiments, a memory controller may select pending transactions based upon selection criteria and may issue the selected transactions to memory. Further, the memory controller may close a page of the memory accessed by a write transaction in response to determining that the write transaction is the last write transaction of a series of one or more write transactions.

BACKGROUND

Computing devices typically comprise a processor, memory, and a memory controller to provide the processor as well as other components of the computing device with access to the memory. The performance of such computing devices is strongly influenced by the memory latency of the computing device. In general, the “memory read latency” is the length of time between when the processor requests the memory controller to retrieve data from the memory and when the memory controller provides the processor with the requested data. Similarly, the “memory write latency” is generally the length of time between when the processor requests the memory controller to write data to the memory and when the memory controller indicates to the processor that the data has been or will be written to the memory.

To reduce the effect of memory latency on the computing device, memory controllers typically buffer write transactions of the processor and later write the data of the transaction to memory at a more appropriate time. As far as the processor is concerned, the write transaction is complete once buffered by the memory controller. The processor, therefore, may continue without waiting for the data of the write transaction to be actually written to memory. Conversely, read transactions are not complete from the standpoint of the processor until the data is read from memory and returned to the processor. Accordingly, performance of a computing device is typically more dependent upon read latency than write latency.

Moreover, memory latency is influenced by the proportion of page-hit, page-miss, and page-empty transactions encountered. Computing devices typical comprise hierarchal memory arrangements in which memory is arranged in channels, ranks, banks, pages, and columns. In particular, each channel may comprise one or more ranks, each rank may comprise one or more banks, and each bank may comprise one or more pages. Further, each page may comprise one or more columns. When accessing memory, the memory controller typically opens a page of the memory and then accesses one or more columns of the opened page. For a page-hit access, the memory controller may leave a page open after accessing a column of the page for a previous memory request and may access a different column of the open page. For a page-miss access, the memory controller may close an open page of a bank, may open another page of the same bank, and may access a column of the newly opened page. A page-miss access generally has about three times the latency as a page-hit access. For a page-empty access, the memory controller may open a closed page of a bank, and may access a column of the newly opened page for the memory transaction. A page-empty access generally has about twice the latency as a page-hit access.

DETAILED DESCRIPTION

An example embodiment of a computing device100is shown inFIG. 1. The computing device100may comprise one or more processors102. The processors102may perform actions in response to executing instructions. For example, the processors102may issue transactions such as memory read transactions and memory write transactions on a processor bus104.

The computing device100may further comprise a chipset106. The chipset106may comprise one or more integrated circuit packages or chips that couple the processors102to memory108, Basic Input/Output System (BIOS) firmware110and other components112(e.g. a mouse, keyboard, video controller, hard disk, floppy disk, etc.). The chipset106may comprise a processor bus interface114to receive transactions from the processors102and to issue transactions to the processors102via the processor bus104. The chipset106may further comprise a memory controller116to issue read and write transactions to the memory108via a memory bus118. The chipset106may further comprise one or more component interfaces (not shown) to access the other components112via buses120such as, for example, peripheral component interconnect (PCI) buses, accelerated graphics port (AGP) buses, universal serial bus (USB) buses, low pin count (LPC) buses, and/or other I/O buses.

In one embodiment, the BIOS firmware110comprises routines which the computing device100may execute during system startup in order to initialize the processors102, chipset106, and other components of the computing device100. Moreover, the BIOS firmware110may comprise routines or drivers which the computing device100may execute to communicate with one or more components of the computing device100.

The memory108may comprise memory devices providing addressable storage locations that the memory controller116may read data from and/or write data to. The memory108may comprise one or more different types of memory devices such as, for example, dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, double data rate (DDR) SDRAM devices, quad data rate (QDR) SDRAM devices, or other volatile or non-volatile memory devices. Moreover, the memory108may be arranged in a hierarchal manner. For example, the memory108may be arranged in channels, ranks, banks, pages, and columns.

As depicted inFIG. 2, the memory controller116may comprise a write-cache198that comprises a read buffer200and a write buffer202. The memory controller116may further comprise control logic204and a memory interface206. The read buffer200may buffer the address and data of a read transaction until the requested data is retrieved from the memory108and returned to the requester (e.g. processor102). Similarly, the write buffer202may buffer the address and data of a write transaction until the data is written to the memory108. The read buffer200and write buffer202may each support buffering of one or more transactions.

The control logic204may select a transaction from the buffers200,202based upon various criteria and may request the memory interface206to service the selected transaction. Computer performance is typically more dependent upon memory read performance than memory write performance. Accordingly, the control logic204in one embodiment in general favors read transactions over write transactions and thus generally causes write transactions to wait until the read buffer is empty. In another embodiment, the control logic204may further wait until data needs to be evicted from the write-cache198before writing data of the write buffer202back to the memory108.

The control logic204, however, may select write transactions over read transactions under certain conditions such as, for example, the write buffer202becoming full or the number of pending write transactions in the write buffer202having a predetermined relationship to an upper threshold that indicates that the write buffer202is nearly full. In which case, the control logic204may completely flush the write buffer thus presenting all pending write transactions to memory interface206for servicing. The control logic204may alternatively partially flush the write buffer202. For example, the control logic204may present the memory interface206with a predetermined number of write transactions (e.g. 4) or may present the memory interface206with write transactions from the write buffer202until the number of pending write transactions has a predetermined relationship with a lower threshold.

The control logic204may further satisfy a read transaction with data stored in the write cache198. Satisfying the read transaction with data from the write buffer202may reduce the latency of the read transactions since the memory controller116is able to satisfy the request without retrieving the data from memory108. Further, servicing read transactions with cached data of the write buffer202may help reduce the latency of other read transactions due to fewer read transactions consuming bandwidth between the memory controller116and the memory108. Furthermore, the control logic204may combine, in the write buffer202, data of write transactions that target the same locations of the memory108. Again, combining write transactions in the write buffer202may reduce the latency of memory transactions since write combining may reduce the number of write transactions between the memory controller116and the memory108.

The memory interface206may read data from memory108in response to read transactions and may write data to memory108in response to write transactions. In particular, the memory interface206may decode an address of a transaction and may apply memory select signals to the memory in order to open pages of the memory108for reading and/or writing. Moreover, the memory interface208may close an opened page by issuing a precharge command or by issuing a transaction to the memory108with an auto-precharge qualifier that causes the memory108to close the page of the transaction after servicing the transaction.

As indicated above, the control logic204favors read transactions over write transactions. Accordingly, write transactions tend to be interspersed between read transactions that were issued by the processor102considerably after the write transactions. Read transactions in such an environment tend to exhibit poor spatial locality of reference to the write transactions due to their temporal separation. If pages accessed by write transactions are left open, then read transactions that follow the last write transactions of write transaction series tend to result in a higher proportion of page-miss accesses to page-hit access. In an effort to reduce overall memory latency, the control logic204in one embodiment closes a page accessed by a last write transaction to reduce the likelihood that a read transaction following the last write transaction results in a page-miss access. As stated previously, a page-empty access has about twice the latency of a page-hit access, but a page-miss access has about thrice the latency of a page-hit access. Therefore, if leaving the page accessed by the last write transaction of one or more consecutive write transactions would result in more page-miss accesses than page-hit access, then closing the page would reduce the latency of read transactions following write transactions.

Therefore, as shown inFIG. 3, the memory controller116in an attempt to reduce memory latency may schedule transactions and close pages in a manner that attempts to reduce overall memory latency experienced by the processor102. The method ofFIG. 3in general favors read transactions over write transactions and generally closes pages of a memory108that were accessed by the last write transactions of a series of one or more write transactions. However, the memory controller116may close pages of the memory108based upon additional criteria.

In response to determining that there is an available time slot for issuing a memory transaction, the control logic204in block300may determine whether there are any pending memory transactions. In particular, the control logic204may determine that there are no pending memory transactions if neither the read buffer200nor the write buffer202comprises transactions to be issued to the memory108. In response to determining there are no pending transactions, the control logic204may enter an idle state or exit the scheduling method ofFIG. 3until the next available time slot for issuing a memory transaction.

Otherwise, the control logic204in block302may select a transaction from the read buffer200or the write buffer202based upon selection criteria or rules. For example, in one embodiment, the control logic204may favor read transaction over write transactions and may select a read transaction if the read buffer200comprises a read transaction. In response to the read buffer200comprising no read transactions to be issued to the memory108, the control logic204may select a write transaction from the write buffer202. In another embodiment, the control logic204may further select a write transaction from the write buffer202even though the read buffer200comprises pending read transactions. In particular, the control logic204may select a write transaction in response to determining that the write buffer202is full or in response to determining that the write buffer202comprises an upper threshold of write transactions that indicates the write buffer202is nearly full. In yet another embodiment, after detecting that the write buffer202is full or nearly full, the control logic204may continue to select write transactions over read transactions until a predetermined number (e.g. 4) of write transactions have been selected, until the write buffer202is empty, or until the write buffer202comprises a lower threshold of write transactions. For example, the lower threshold may correspond to the write buffer202being half filled.

In block304, the control logic204may determine whether the selected transaction is a read transaction or a write transaction. In response to determining that the selected transaction is a read transaction, the control logic204in block306may cause the memory interface206to issue the selected read transaction to the memory to obtain the requested data from the memory108. Otherwise, the control logic204in block308may determine whether the selected write transaction is the last write transaction of a series of one or more write transactions. For example, in one embodiment, the control logic204may determine that selected write transaction is the last write transaction in response to determining that the write buffer202comprises no other pending transactions. In another embodiment, the control logic204may further determine that the selected write transaction is the last write transaction in response to determining that the read buffer200comprises at least one read transaction to issue to the memory108. The control logic204may further determine that the selected write transaction is the last write transaction of the series in response to determining that the write buffer comprises no more write transactions to the page of memory108to be accessed by the selected write transaction. The control logic204may also determine that the select write transaction is the last write transaction in response to memory interface206issuing a predetermined number of consecutive write transactions to the memory108. Further yet, the control logic204may determine that the selected write transaction is the last write transaction of the series in response to determining that write buffer202comprises a lower threshold of write transactions. It should be appreciated that the control logic204may determine the last write transaction of a series of one or more write transactions based upon one or more of the above identified criteria and/or other criteria.

In response to determining that the selected write transaction is not the last write transaction of a series of write transactions, the control logic204in block310may cause the memory interface206to issue the selected write transaction to the memory108in order to write the data supplied by the write transaction to the memory108. Otherwise, the control logic204in block312may instruct the memory interface206to close a page accessed by the write transaction.

In response to being instructed to close the page accessed by the write transaction, the memory interface206in block314may issue the selected write transaction to the memory108and may close the page accessed by the write transaction. In one embodiment, the memory interface206may issue the write transaction to the memory108and then may issue a precharge command to the memory108to close the page after the write transaction. In another embodiment, the memory interface206may issue the write transaction to the memory108with an auto-precharge qualifier that causes the memory108to close the page accessed by the write transaction after the data of the write transaction is written to the page.

The computing device100may perform all or a subset of the example method in response to executing instructions of a machine readable medium such as, for example, read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; and/or electrical, optical, acoustical or other form of propagated signals such as, for example, carrier waves, infrared signals, digital signals, analog signals. Furthermore, while the example method is illustrated as a sequence of operations, the computing device100in some embodiments may perform operations of the method in parallel or in a different order.

While certain features of the invention have been described with reference to example embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the example embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.