Ion implantation with multiple concentration levels

A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor processes, and more particularly, to ion implantation in semiconductor processes.

BACKGROUND OF THE INVENTION

The manufacture of integrated circuits on semiconductors involves several steps. Such steps include growing a semiconductor material, slicing the semiconductor material into planar structures, and polishing the surface of the semiconductor. Once the semiconductor is polished, circuit elements may be formed by selectively introducing impurities, or dopant, into portions of the semiconductor. Impurities alter the electrical behavior of the semiconductor in predictable ways to create various circuit elements. One method of introducing impurities into the semiconductor is through ion implantation.

Ion implantation is a process in which impurities are implanted into the semiconductor substrate to form circuit elements within the semiconductor crystalline structure. In a typical ion implantation process, various parts of the substrate are masked with a pattern that is made of photoresist or another suitable material that substantially prevents the ions from penetrating. The portions of the silicon in which the mask is absent, i.e. where voids in the mask are present, absorb the ions during implantation. In this manner, impurities may be selective implanted within the substrate.

In general, the ion implantation process itself involves multiple steps. In particular, a mask must first be designed in accordance with the circuit layout. Thereafter, the silicon and mask are bombarded by ions. The mask is then removed in a suitable manner, many of which are known in the art.

Many integrated circuits employ different circuit components that require different concentrations of dopant. To form such different concentrations, the ion implantation step may be repeated for every different level of doping concentration required in the integrated circuit. For example, a first mask may mask all but the areas requiring a high level of doping concentration. Once the mask is applied to the surface, the ion implantation device then bombards the silicon and mask at the highest level. After implantation and removal of the first mask, a second mask is applied to the surface to mask all but the areas requiring a lower level of doping concentration. Ion implantation then takes place at the lower level.

While the above method can reliably implant dopant into a silicon substrate at multiple concentration levels, the manufacturing process is extended in substantial part by the repeated ion implantation operations. For example, if a particular integrated circuit requires four or five different dopant concentration levels, the repeated masking and implantation steps significantly lengthen the manufacturing process.

There is a need, therefore, with a method of implanting impurities into semiconductor substrates at multiple levels that has reduced processing time.

SUMMARY OF THE INVENTION

The present invention addresses the above needs, as well as others, by providing a method of implanting ions into a semiconductor substrate that allows multiple concentration levels to be implanted during a single ion bombardment operation. In particular, the method employs a mask that has features having a width that are less than twice the diffusion length of the impurity within the semiconductor substrate. Using such features, the volume of ions to particular portion of the substrate may be reduced, yet may be distributed throughout that portion by diffusion of the ions.

Embodiments of the subject invention include a method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.

Other embodiments include a semiconductor product that is produced using the above-described method.

Still other embodiments of the subject invention include a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The diffusion length of the dopant is defined as a length of diffusion under heating of the semiconductor substrate to a temperature exceeding that of an ion bombardment step.

DETAILED DESCRIPTION

FIG. 1shows a flow diagram of an exemplary set of ion implantation operations in accordance with embodiments of the subject invention.FIGS. 2athrough2dshow a diagrammatic cross sectional view of a substrate undergoing the operations of FIG.1. Referring toFIG. 2a, the substrate12is a semiconductor substrate. In the exemplary embodiment described herein, the semiconductor substrate12is single crystal silicon. However, in alternative embodiments, the semiconductor substrate12may suitably be polysilicon, gallium arsenide, or other known semiconductor substrate.

The preparation of a semiconductor substrate is well known in the art. Typically, a semiconductor crystal is grown, sliced into wafers, and then polished. Ion implantation typically occurs on the polished wafer.FIG. 2ashows a diagrammatic cross section of the substrate12provided for ion implantation.

Referring now toFIG. 1, in step102, a mask is disposed on the surface of the semiconductor substrate. The mask is a layer of aluminum or silicon dioxide material that has a geometry that corresponds to the layout of the circuit or circuits that are to be integrated into the semiconductor substrate. The mask geometry operates to selectively allow ions to be implanted into the semiconductor substrate. A silicon dioxide mask is disposed on the substrate by treating the top layers of the initial silicon substrate. In the alternative, other types of masks may be separately formed on the substrate.

To this end, the mask includes both masking elements and voids that located between masking elements. As is known in the art, the mask operates to block ions from entering the portions of the surface of the substrate that are located immediately below the masking element, and to allow ions to enter portions of the substrate surface located within the voids. The selective ion implantation alters the electro-physical behavior of the semiconductor substrate in local areas so as to form various circuit elements.

FIG. 2bshows a diagrammatic cross section of the substrate12with portions of an exemplary mask14disposed thereon.FIG. 4shows an exemplary top plan diagrammatic view of the substrate12with the exemplary mask disposed thereon.

The mask14includes a plurality of elements14a-14fand a plurality of voids16a-16e. The mask14is further defined by continuous regions, each of which is intended to allow a select average dopant concentration on the substrate12.

In particular, the mask14includes a first region18defined completely by the element14aand therefore has no voids. Thus, the first region18is intended to receive substantially no impurities or dopant during the ensuing implantation process.

The mask14further includes a second region20having a plurality of masking elements14b-14e. A first small void16aseparates the first masking element14aof the first region18from the first element14bof the second region. The voids14bthrough14eare separated by corresponding voids16b-16d, respectively.

It is noted that the masking elements14b-14ehave a width d that is significantly smaller than the width d′ of the masking element14aof the first region18. The width d is chosen such that it is less than twice a diffusion length l of the ions to be implanted within the substrate12. As will be discussed below, the use of masking elements having a width that is less than twice the diffusion length of the ions within the substrate allows for the second region20to have a relatively continuous ion implantation of reduced density. As a consequence, a single ion implantation operation may provide differing densities of impurities in the substrate12.

The mask14further includes a third region22defined completely by single void16e. The third region22defines an area in which a relatively high concentration of impurities or dopant is intended. Finally, the mask14includes a fourth region24defined completely by an element14f. The element14fhas a width d″ that is several times d. The fourth region24, like the first region18, is intended to be substantially free of impurities after implantation.

Thus, the mask14shown inFIG. 2bincludes a region22intended for a first level of implantation, a region20intended for a second level of implantation, and regions18and24intended for a third level of implantation (i.e. substantially none). It will be appreciated that the mask14is given by way of example only. The mask14may be readily adapted to accommodate any circuit geometry in which at least two levels of non-zero implantation are desired.

It will be appreciated that the mask14may be physically disposed on the substrate by any suitable masking method known in the art. Once the mask14is disposed on the substrate12, step102is complete and step104may be executed.

In step104, the substrate12and the masking element14is bombarded with ions of a select dopant. The masking elements14a-14fsubstantially block the ions from penetrating into the substrate, while the voids allow the ions to enter the substrate, as illustrated byFIG. 2c.

As is known in the art, the bombardment occurs such that the ion travel is substantially normal to the plane defined by the surface of the substrate12. Accordingly, after bombardment in step104, the impurities are concentrated in the areas of the substrate12that are located below the voids16a-16e.FIG. 2dillustrates the substrate12and mask14after implantation, with the impurities located in the portions of the substrate12that correspond to the mask voids16a-16e.

Accordingly, as a result of step104, the ions are disposed in a somewhat discontinuous manner in the second region20, substantially directly below the voids16a-16e.FIG. 3shows a illustrative graph of the distribution of ions within the substrate12. The solid curve52shows the ion distribution as a function of position across the surface of the substrate12after step104. As can be seen, essentially two levels of concentration exist after step104: full density ion concentration at locations corresponding to the voids16a-16eand substantially null density ion concentration at locations corresponding to the masking elements14a-14f.

After step104, the implanted substrate12is heated in step106. In particular, the implant substrate12is heated to a temperature higher than that achieved during step104. The heating has the effect of diffusing the ions both laterally and vertically within the substrate12. The heating step may suitably be an annealing step commonly used in semiconductor manufacturing. Annealing typically occurs at temperatures of between 500° C. and 1000° C., depending on the substrate. Annealing is employed to repair damage done to the crystal during ion implantation, as is known in the art.

Regardless of how or why the heating occurs, application of heating in about the 500° C.-1000° C. range causes diffusion of the ions to a substantially predictable diffusion length. Diffusion length depends in part on the type of substrate used. For example, in an ordinary annealing operation, the diffusion length is typically 1-2 microns in a single-crystal silicon substrate, and is 7-8 microns in a polysilicon substrate.

As discussed further above, the masking elements14b-14ehave at least one dimension that is less than twice of the diffusion length of the implanted ions that is achieved during the heating operation. As a consequence, the heating operation of step106redistributes the ion concentration with the second region20of the substrate12such that the impurities are distributed over the entire second region. To achieve more even distribution of the impurities over the entire second region20, each of the masking elements14b-14ebe somewhat less than twice the diffusion length, as twice the diffusion length substantially represents the maximum size that any continuous distribution of dopant may be achieved.

FIG. 2eillustrates the substrate12after the heating operation of step106, and after removal of the mask14. As shown inFIG. 2e, the impurities are distributed throughout the second region20, as well as the third region22. Because of the presence of the masking features14b-14ein the second region20, however, the overall or average concentration of the impurities in the second region20is less than that of the third region22. Indeed, average concentration of the second region20may be estimated by calculating the ratio of the masking features14b-14eto voids16a-16dwithin the second region20and multiplying that ratio by the concentration of the unmasked regions, for example, the third region22. With regard to the fully masked regions18,24, little or no impurities diffuse into the first region18and the fourth region24because the masking elements14aand14fare several times the diffusion length of the ions.

Referring again toFIG. 3, the broken line54shows the relationship of ion concentration as a function of position on the substrate after the heating operation. As illustrated inFIG. 3the heating operation has the effect of averaging out the large swings in ion concentration with the second region20caused by the alternating small width voids and masking features within the second region20.

As illustrated by the above example described in connection withFIGS. 1 and 2a-2e, by employing a mask having masking elements that have a dimension of less than twice the diffusion length of the ions, and following up with a heating step to effect the diffusion, multiple levels of impurities may be introduced into a semiconductor substrate with a single uniform ion bombardment operation.

It will be appreciated that by creating masks having regions with different proportions of voids to masking features, multiple different concentrations of impurities may be created. For example, three, four or more different concentrations of impurities may be achieved with a single ion bombardment step by varying the ratio of masking feature surface area to void surface area. Regardless of the ratio, however, at least one dimension of the masking feature should be less than twice the diffusion length (that is achievable in the heating operation), and preferably less than one diffusion length to improve the evenness of the distribution.

FIG. 4shows an fragmentary top diagrammatic view of an exemplary layout of the substrate12. As shown inFIG. 4, the regions18,20,22and24are just a few of several regions within the substrate, each of which has a two-dimensional shape. As also shown inFIG. 4, the masking features14b-14erepresent only one of multiple rows of masking features in the second region20. As shown inFIG. 4, the masking features of the second region may form a checkerboard pattern in two dimensions in order to further aid in a relatively even distribution of the impurities after the heating operation. The masking features themselves may be of nearly any shape, including square, rectangular, triangular, rounded, circular or polygonal, so long as at least one dimension is less than twice the diffusion length of the impurities under the conditions of the heating operation.

It will be appreciated that the above described embodiments are merely exemplary, and that those of ordinary skill in the art may breadily devise their own implementations that incorporate the principles of the present invention and fall within the spirit and scope thereof.