Encapsulated wafer level package with protection against damage and manufacturing method

A packaged semiconductor device may include a substrate including at least one device layer and at least one connector arranged thereon, and a resin cover covering each side of the substrate, the resin cover on at least one side of the substrate including an opening exposing the connector and the resin cover on at least one other side of the substrate exposing a portion of the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate to semiconductor chip packages, and methods of manufacturing thereof. More particularly, embodiments of the present invention relate to wafer level chip packages and methods of manufacturing wafer level chip packages that are capable of providing improved protection against damage, e.g., during handling and/or subsequent wafer and/or chip processing, and reducing chipping and/or cracking defects.

2. Description of the Related Art

In general, semiconductor chip packages are provided to physically protect a semiconductor chip while establishing input and output connection portion(s) for connecting the semiconductor chip to other device(s). As electronic devices are becoming smaller and more complex, it is desirable to package a semiconductor chip as soon as possible after the semiconductor chip is formed to help protect the electronic devices of the semiconductor chip from damage that may occur during subsequent handling, etc. In some cases, the semiconductor chips of a wafer are first completely separated from the wafer before being packaged. In such cases, however, the semiconductor chips are susceptible to damage that may occur during the dicing process itself, i.e., process for separating the semiconductor chip(s) from the wafer.

Therefore, in some cases, wafer level packaging is employed to package the semiconductor chip(s) while the semiconductor chip(s) are still on the wafer. Wafer level packaging may offer many advantages, e.g., protection during dicing, relatively small, e.g., thinner, package size, relatively lighter package weight, and/or reduced manufacturing cost, etc. In general, conventional wafer level packages fail to cover all sides, e.g., all six sides, of a semiconductor chip, and/or conventional methods of wafer-level packaging semiconductor devices generally employ, e.g., multiple depositing steps and/or multiple planarization steps. Therefore, improved wafer level packages and simplified methods of packaging semiconductor chips at the wafer level are desired.

SUMMARY OF THE INVENTION

Embodiments of the present invention are therefore directed to semiconductor packages and methods of manufacturing such semiconductor packages, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

It is therefore a feature of an embodiment of the present invention to provide packages that completely encapsulate the semiconductor chip, except for connector(s) formed and predetermined protruding portion(s) of a substrate of the semiconductor chip.

It is therefore a separate feature of an embodiment of the present invention to provide simplified methods of manufacturing wafer level packages that completely encapsulate the semiconductor chip, except for connector(s) formed and predetermined protruding portion(s) of a substrate of the semiconductor chip.

It is therefore a separate feature of an embodiment of the present invention to provide a method of manufacturing wafer level packages that completely encapsulate the semiconductor chip, except for connector(s) formed and predetermined protruding portion(s) of a substrate of the semiconductor chip, which requires only a single resin covering step such that all sides of the semiconductor chip are simultaneously covered.

At least one of the above and other features and advantages of the present invention may be realized by providing a packaged semiconductor device, including a substrate including at least one device layer and at least one connector arranged thereon, and a resin cover covering each side of the substrate, wherein the resin cover on at least one side of the substrate may include an opening exposing the connector and the resin cover on at least one other side of the substrate may expose a portion of the substrate.

The resin cover may be an outermost layer on each of the sides of the substrate. Each outer surface of the resin cover may be substantially or completely planar. A portion of the resin cover exposing the portion of the substrate may abut a sidewall of the exposed portion of the substrate, and an outer surface of the abutting portion of the resin cover may extend along a same plane as a plane along which a surface of the exposed portion of the substrate extends.

The substrate may include a top side, a bottom side, and a plurality of lateral sides, and the top side may include a plurality of the connectors arranged thereon, the resin cover on the top side may include a plurality of openings respectively exposing the connectors, and the resin cover on the another side of the substrate may be on at least one of the lateral sides, and may expose a portion of at least one of the lateral sides of substrate.

The resin cover may expose a portion of each of the lateral sides of the substrate. The resin cover may expose a portion of only two of the lateral sides of the substrate, the two lateral sides may be opposite each other. The resin cover may expose a portion of only one of the lateral sides of the substrate.

Other than the exposed at least one connector and the exposed portion of the at least one other side, the resin cover may completely encapsulate the substrate. The resin cover may be a single continuous layer. The exposed portion of the substrate may correspond to a lateral corner portion of the substrate.

A portion of the resin cover on the side of the substrate including the at least one connector may surround a lower portion of the connector, and may have a height of about 10% to about 80% of a height of the at least one connector along a direction substantially perpendicular to a plane along which a surface of the substrate on which the connector is arranged extends.

The substrate may have been cut from a wafer along a scribe line of the wafer, the scribe line having a width, such that the substrate may be a portion of the semiconductor wafer, and a thickness, relative to the other side of the substrate, of at least a portion of the resin cover abutting the at least one exposed portion of the substrate may be equal to or less than about 50% of the width of the scribe lane. The packaged semiconductor may be an MCP.

At least one of the above and other features and advantages of the present invention may be separately realized by providing a method of manufacturing a wafer level package, including forming at least one opening in a portion of a wafer surrounding a predetermined sub-portion of the wafer corresponding to a device to be separated from a remaining portion of the wafer, the opening completely extending from a top side of the wafer to a bottom side of the wafer, and the wafer sub-portion remaining connected to the remaining portion of the wafer by at least one wafer connecting portion, covering the wafer sub-portion with a resin cover, wherein the resin cover may fill the opening formed in the portion of the wafer surrounding the wafer sub-portion and cover each side of the wafer sub-portion, and completely separate the wafer sub-portion from the remaining portion of the wafer along a boundary defined by the at least one wafer connecting portion and the portion of resin cover corresponding to the filled opening.

At least one side of the wafer sub-portion may include a connector arranged thereon, and covering the wafer sub-portion may include completely covering the side of the wafer sub-portion having the at least one connector arranged thereon, except for the at least one connector arranged thereon.

Covering the wafer sub-portion may include completely encapsulating the wafer sub-portion, other than the at least one connector of the device and a separated side of the wafer connecting portion, wherein the separated side may correspond to the side of the wafer connecting portion exposed when separating the wafer sub-portion from the remaining portion of the wafer.

Covering the wafer sub-portion with the resin cover may include one of dipping the wafer in a thermosetting epoxy resin solution, and applying an epoxy layer using a spin coating process. Applying the epoxy layer using a spin coating process may include coating at least a top portion of the at least one connector with a coating repellent before covering the wafer sub-portion with the resin cover.

Applying the epoxy layer using a spin coating process may include, during the spin coating process using a spin chuck, temporarily elevating the wafer sub-portion away from an upper surface of the spin chuck to cover the bottom side of the wafer while simultaneously filling the opening and covering each of the other sides of the wafer sub-portion.

Dipping the wafer in a thermosetting epoxy resin solution may include partially dipping the wafer in the epoxy resin solution such that, other than an upper portion of the at least one connector, a remainder of the wafer is dipped into the epoxy resin solution.

Forming the at least one opening may include using at least one of a diamond blade and a laser having a first width, and completely separating the wafer sub-portion may include using at least one of a diamond blade and a laser having a second width, wherein the first width may be greater than the second width.

Forming the at least one opening may include removing a portion of the wafer in a scribe line of the wafer, and a thickness of a remaining portion of the resin cover relative to the respective side of the wafer-sub portion may be equal to or less than about 50% of a width of the scribe line of the wafer.

Covering the wafer sub-portion with the resin cover may be performed in a single covering process such that the opening formed in the portion of the wafer surrounding the wafer sub-portion and each side of the wafer sub-portion may be simultaneously or substantially simultaneously filled and covered, respectively. The method may further include, before covering or before completely separating, stacking at least another wafer on the wafer, wherein the at least another wafer may include another device to be integrated with the device on the wafer.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2007-0031931, filed on Mar. 30, 2007, in the Korean Intellectual Property Office, and entitled: “WAFER LEVEL PACKAGE PREVENTING A CHIPPING DEFECT AND MANUFACTURING METHOD THEREOF,” is incorporated by reference herein in its entirety.

In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Additionally, it will be understood that when an element is referred to as being “continuous,” the element is a single integrally formed member, while “substantially continuous” corresponds to separate portions of a member arranged next to each other, e.g., abutting, relatively close to each other, to form the member. Like reference numerals refer to like elements throughout the specification.

FIG. 1illustrates a first exemplary embodiment of a wafer level package100A of a semiconductor chip104(seeFIGS. 5 and 7). The wafer level package100A may include a cover112, which may be formed of, e.g., a resin, other molding materials known in art, etc. In such embodiments, the resin may include, e.g., an epoxy resin, a phenolic resin, etc.

The semiconductor chip104covered by the wafer level package100A may include one or more connectors110, and at least one protruding portion116A exposed by the cover112of the wafer level package100A. In some embodiments of the invention, e.g., the connector(s)110may be provided on a first side, e.g., a top side, of the semiconductor chip104, and the protruding portion(s)116A may be provided on a different side(s), e.g., lateral side(s), of the semiconductor chip104. Embodiments of the invention are not, however, limited to such a configuration.

The connector(s)110may be arranged on at least one side of the semiconductor chip104, and may be employed to connect the semiconductor chip104to external devices (not shown). The connector(s)110may include conductive material, and may be, e.g., a solder ball, a solder bump, a Cu bump (or Cu pillar), or Cu+ solder bump/pillar.

The protruding portion(s)116A may be provided on at least one side of the semiconductor chip104, and may correspond, e.g., to a portion of a substrate (not shown) of the semiconductor chip104that protrudes beyond other portion(s) of the respective side of the substrate. That is, e.g., the protruding portion(s)116A may protrude beyond all other portion(s) of the respective side of the substrate from which it protrudes. More particularly, e.g., in some embodiments of the invention, the respective side(s) of the substrate including the protruding portion(s)116A may be substantially or completely planar, but for the protruding portion(s)116A protruding therefrom. Embodiments of the invention are not, however, limited to such substantially or completely planar sides. More particularly, the substrate may be, e.g., a respective portion of a semiconductor wafer102(seeFIG. 5) such as a silicon wafer corresponding to the semiconductor chip104, i.e., a portion of the semiconductor wafer diced from a remaining portion of the semiconductor wafer on which a plurality of semiconductor chips104may have been formed. Further, the protruding portion(s)116A may serve to help protect the semiconductor chip104even after the semiconductor chip104is packaged. That is, e.g., together with the cover112, the protruding portion(s)116A may serve to protect the semiconductor chip104from damage.

In the description of exemplary embodiments, it will be assumed that the semiconductor chip104has a rectangular shape including six sides, i.e., a top side, a bottom side, and four lateral sides extending between the top and bottom sides. For example, the top side may correspond to an upper surface extending along a XY plane, the bottom side may correspond to a lower surface, i.e., lower relative to a Z axis, extending along another XY plane, and the lateral sides may extend along different YZ or XZ planes. However, embodiments of the invention are not limited thereto. For example, the semiconductor chip may have a substantially circular or rounded shape along the XY plane, and in such cases, may have, e.g., a single continuous lateral surface. More particularly, in the description of exemplary embodiments, it will be assumed that the connector(s)110are provided on the top side of the semiconductor chip104, and the bottom side of the semiconductor chip is substantially or completely planar. Embodiments of the invention are not, however, limited thereto, and persons of ordinary skill in the art will appreciate the applicability of one or more aspects of the invention to a semiconductor chip irrespective of a shape thereof and/or the side(s) of the semiconductor chip including the connector(s)110and/or protruding portion(s)116A.

The protruding portion(s)116A may be provided at various portions, substantially central portion, corner portion, substantially left or right portion, etc., of the respective side of the semiconductor chip104. In the exemplary embodiment of the wafer level package100A illustrated inFIG. 1, the protruding portions116A are provided at substantially central portions of the respective lateral sides of the semiconductor chip104. The protruding portion(s)116A may occupy a relatively small portion of the respective side of the semiconductor chip104from which they protrude such that a majority of the sides of the semiconductor chip104are covered by the cover112.

Further, e.g., in some embodiments of the invention, only one protruding portion116A may be provided on the semiconductor chip104, while in other embodiments, e.g., more than one protruding portions116A may be provided. For example, in some embodiments at least one protruding portion116A may be provided on two sides, e.g., two opposing lateral sides, of the semiconductor chip104. In some other embodiments of the invention, a plurality of protruding portion116A may be provided on only one lateral side of the of the semiconductor chip104. In some other embodiments of the invention, a plurality of the protruding portions116A may be provided on a plurality of lateral sides of the semiconductor chip104. In yet some other embodiments of the invention, a single and/or a plurality of the protruding portions116A may be provided on each lateral side of the semiconductor chip104. More particularly, the exemplary wafer level package100A illustrated inFIG. 1, includes one protruding portion116A at a central portion of each lateral side of the semiconductor chip104and/or a central portion of each lateral side of the cover112. Embodiments of the invention are not, however, limited thereto.

In some embodiments of the invention, an exposed surface of the protruding portion(s)116A, i.e., surface(s) exposed by the cover112, may be substantially and/or completely planar, and may extend along a same plane as respective outer surface of portion(s) of the cover112. In some embodiments of the invention, while a surface may be substantially planar, the respective surface may not be a smooth surface, i.e., the surface may be rugged or rough. Further, while various surfaces may be described as being substantially and/or completely planar, embodiments of the invention are not limited thereto.

More particularly, the respective portion(s) of the cover112may abut, and substantially and/or completely align with the respective protruding portion(s)116A so as to form a substantially continuous surface. That is, e.g., in some embodiments of the invention, but for the connector(s)110, the resulting wafer level package100A may have substantially and/or completely planar surfaces as a result of respective portion(s) of the cover112, alone or in combination with the respective protruding portion(s)116A. More particularly, in some embodiments of the invention, the substantially continuous surface, e.g., two surfaces arranged close to and/or abutting each other, resulting from the abutting arrangement of the respective outer surface portion(s) of the cover112and the respective protruding portion(s)116A may be substantially and/or completely planar. Embodiments of the invention, however, are not limited to such planar and/or completely planar surfaces for the wafer level package100A and/or cover112. That is, e.g., the protecting nature of the cover112, may not depend on the respective surface(s) of the cover112being substantially and/or completely planar, i.e., may rather depend on a thickness of the cover112. Thus, while a relatively precise tool or method may be employed to completely separate the semiconductor chip104from the wafer102, the tool or method need not necessarily establish a smooth or planar surface.

More particularly, e.g., in some embodiments of the invention, the protruding portion116A may correspond to a substantially rectangular shaped portion of the substrate of the semiconductor chip104, and as shown inFIG. 1, other than the exposed surface(s) of the protruding portion116A, which may be aligned with the respective outer surface portion(s) of the cover112, the protruding portion(s)116(A) may be completely surrounded by the cover112.

As shown inFIG. 1, in some embodiments of the invention, except for the exposed connector(s)110and the protruding portion(s)116A, the cover112may substantially completely and/or completely encapsulate the semiconductor chip104.

Further, by providing portion(s) of the cover112even on the side(s), e.g., the top side, of the semiconductor chip104including the connector(s)110, respective portions of the cover112may support and/or surround the connectors110, and may improve joint reliability of the connector(s)110. That is, e.g., lower portions of the connector(s)110may be surrounded respective portions of the cover112. In some embodiments of the invention, the cover112may have a height H1(seeFIG. 13) of about 10% to about 80% of a height H2(seeFIG. 13) of the connector110relative to a respective surface, e.g., top surface, of the semiconductor chip104. For example, in embodiments of the invention in which the connector(s)110are provided on the top side of the semiconductor chip104extending along a XY plane, the cover112may have a height H1of about 10% to about 80% of the height H2of the connector110along the Z direction. More particularly, if, e.g., the height H1of the cover112is more than about 80% of the height H2of the connector110, electrical connectivity characteristics of the connector110may be threatened, and if, e.g., the height H1of the cover112is less than about 10% of the height H2of the connector110, the cover112may not adequate serve to improve joint reliability of the connector110to the semiconductor chip104.

A protruding height, i.e., thickness, of protruding portion(s)116A relative to the respective side of the substrate may be no more than about 50% of a width Ws of scribe line106(seeFIG. 7). As described in more detail below, the semiconductor chip104may be diced, i.e., separated from, the substrate, e.g., semiconductor wafer, by cutting within the scribe line(s)106surrounding the semiconductor chip104. More particularly, e.g., if two semiconductor dies are formed adjacent to each on the substrate with a respective scribe line therebetween, the substrate may be diced such that about 50% of the scribe line remains on each of the resulting semiconductor chips104. Further, in such embodiments, respective portion(s) of the cover112may have a thickness of less than about 50% of the width Ws of the corresponding scribe line106.

FIG. 2illustrates a second exemplary embodiment of a wafer level package100B of a semiconductor chip104A (seeFIG. 8) including at least one protruding portion(s)116B, arranged differently than protruding portion(s)116A of the first exemplary embodiment illustrated inFIG. 1. In general, only differences between the first exemplary wafer level package100A illustrated inFIG. 1and the second exemplary embodiment of the wafer level package100B will be described below.

Referring toFIG. 2, the wafer level package100B may include a cover112A, and the protruding portion(s)116B of the semiconductor substrate may be arranged at edge, e.g., corner, portion(s) of the semiconductor chip104A. Thus, according to this exemplary embodiment, at least one corner portion of the cover112A may correspond to an exposed portion of the substrate of the semiconductor chip104A. More particularly, in the exemplary embodiment illustrated inFIG. 2, each corner portion of the cover112A may include an exposed portion of the substrate of the semiconductor chip104A. Thus, in such an embodiment, assuming that the semiconductor chip104A has a rectangular shape, each of the four lateral corners of the wafer-level package100B may include a portion of the cover112A and a respective exposed portion of the substrate of the semiconductor chip104A.

FIG. 3illustrates a third exemplary embodiment of a wafer level package100C of a semiconductor chip104B (seeFIG. 9) including at least one protruding portion(s)116C, arranged differently than protruding portion(s)116A of the first exemplary embodiment illustrated inFIG. 1. In general, only differences between the first exemplary wafer level package100A illustrated inFIG. 1and the third exemplary embodiment of the wafer level package100C will be described below.

Referring toFIG. 3, the wafer level package100C may include a plurality of protruding portions116C and a cover112B. The protruding portions116C may be arranged on opposing lateral sides of the cover112B or opposing lateral sides of the semiconductor chip104B. More particularly, e.g., the exemplary wafer level package100C illustrated inFIG. 3includes two protruding portions116C arranged at substantially central portions of two opposing lateral sides of the cover112B, i.e., corresponding to substantially central portions of two opposing lateral sides of the semiconductor chip104B.

FIG. 4illustrates a fourth exemplary embodiment of a wafer level package100D of a semiconductor chip104C (seeFIG. 10) including at least one protruding portion(s)116D, arranged differently than protruding portion(s)116A of the first exemplary embodiment illustrated inFIG. 1. In general, only differences between the first exemplary wafer level package100A illustrated inFIG. 1and the fourth exemplary embodiment of the wafer level package100D will be described below.

Referring toFIG. 4, the wafer level package100D may include protruding portion(s)116D and a cover112C. The protruding portion(s)116D may be arranged off-center from, e.g., substantially to a left or right side of a respective lateral side of the cover112C or substantially to a left or right side of a respective lateral side of the semiconductor chip104C. More particularly, e.g., the exemplary wafer level package100D illustrated inFIG. 4includes a single protruding portion116D substantially to a left or right side of a lateral side of the cover112C. Embodiments of the invention are not limited, however, to such an arrangement. For example, the single protruding portion116D may be arranged at a substantially central portion or a corner portion of the cover112C.

Further, in some embodiments of the invention, a combination of the exemplary configurations illustrated in, e.g.,FIGS. 1 through 4may be employed.

An exemplary method of fabricating a wafer level package according to one or more aspects of the invention will be described below with reference toFIGS. 5 through 14.

FIG. 5illustrates a top view of a wafer102including a plurality of semiconductor chips104. As illustrated inFIG. 5, the plurality of semiconductor chips104, i.e., semiconductor dies corresponding to respective semiconductor chips104, may be formed on a wafer102, e.g., a semiconductor wafer. The semiconductor chips104may be diced, i.e., separated, from a remaining portion of the wafer102by, e.g., cutting or breaking within the scribe line106(seeFIG. 7) surrounding each semiconductor chip104. After being diced from the wafer102, the respective semiconductor chips104may each include a portion of the wafer102as the substrate of the semiconductor chip104. The wafer102may be, e.g., a semiconductor wafer such as a silicon wafer.

FIG. 6illustrates a flow-chart of an exemplary method for fabricating a wafer level package according to one or more aspects of the invention;FIG. 7illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 1;FIG. 8illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 2;FIG. 9illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 3;FIG. 10illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 4; andFIGS. 11,12,13and14illustrate additional stages in the exemplary method for fabricating the wafer level packages ofFIGS. 1 through 4according to one or more aspects of the invention.

Referring toFIGS. 1,6and7, fabricating the wafer level package100A according to one or more aspects of the invention may begin at step S60during which a wafer102including at least one semiconductor chip104formed thereon may be provided.

Still referring toFIGS. 6 and 7, the exemplary method may then proceed to step S64during which at least one opening108A may be formed in a portion of the wafer102surrounding the semiconductor chip104to partially separate the semiconductor wafer104from a remaining portion of the wafer102. The opening(s)108A may completely extend through a thickness of the wafer102, e.g., completely from the top side of the wafer102to the bottom side of the wafer102along the Z direction (e.g., a peek-hole like opening through the wafer102enabling one to see something arranged below the wafer102from a point above the wafer102). In embodiments of the invention, while the opening(s)108A may extend completely through a thickness of the wafer102, the opening(s)108A define at least one connecting portion136for keeping the semiconductor chip104partially connected to the remaining portion of the wafer102at this stage in exemplary the wafer level package fabricating method. At least some of the connecting portion136may be shared between two or more adjacent ones of the semiconductor chips104on the wafer102.

Referring toFIG. 7, the opening(s)108A may be formed within the scribe lines106surrounding the respective semiconductor chip104. The opening(s)108A may be formed by, e.g., sawing corresponding portion(s) of the wafer102using, e.g., a laser, a diamond blade, or other known cutting/sawing materials and/or methods. A width of the opening(s)108A may be substantially the same as or less than the width Ws of the scribe line106, e.g., a first cutting width of a first laser cutting step may be substantially the same as or less than the width Ws of the scribe line106. The openings108A may correspond to one or more of the semiconductor chips104. For example, in some embodiments, the openings108A may extend from one lateral side of the wafer102to an opposing lateral side of the wafer102and may be associated with a plurality of semiconductor chips104arranged in, e.g., a row or column, while in some other embodiments, the openings108A may be associated with, e.g., one, two or four semiconductor chips104.

The opening(s)108A may have various shapes depending on an arrangement of the at least one protruding portion116A to be provided. More particularly, e.g., the openings108A may be provided to form the wafer level package100A ofFIG. 1. The openings108A may form the connecting portion136on each lateral side of the semiconductor chip104. In this exemplary embodiment, a total of four connecting portions136may be provided as a result of, e.g., respective portions of, e.g., four openings108A partially surrounding the semiconductor chip104. More particularly, in this exemplary embodiment, the connecting portions136may be provided at a substantially central portion of each lateral side of the semiconductor chip104. Embodiments of the invention are not, however, limited to such an arrangement and/or number of openings108A and/or connecting portions136.

For example, referring toFIG. 8, openings108B may be provided to form the wafer level package100B ofFIG. 2. In general, only differences between the openings108B illustrated inFIG. 8and the openings108A illustrated inFIG. 7will be described below. Thus, e.g., the openings108B may also extend completely through a thickness of the wafer102. In this exemplary embodiment, the openings108B may form, e.g., a connecting portion136A at each corner of the semiconductor wafer104A. More particularly, in this exemplary embodiment, four connecting portions136A may be at least partially defined as a result of, e.g., respective portions of, e.g., four openings108B partially surrounding the semiconductor chip104A. The connecting portions136A may be provided at, e.g., each lateral corner portion of the semiconductor chip104A.

In another exemplary embodiment, referring toFIG. 9, openings108C may be provided to form the wafer level package100C ofFIG. 3. In general, only differences between the openings108C illustrated inFIG. 9and the openings108A illustrated inFIG. 7will be described below. Thus, e.g., the openings108C may also extend completely through a thickness of the wafer102. In this exemplary embodiment, the openings108C may form, e.g., a connecting portion136B at opposing lateral sides of the semiconductor wafer104B. More particularly, in this exemplary embodiment, two connecting portions136B may be defined as a result of, e.g., respective portions of, e.g., two openings108C partially surrounding the semiconductor chip104B. The connecting portions136B may be provided at, e.g., central portions of the respective lateral opposing sides of the semiconductor chip104A.

In another exemplary embodiment, referring toFIG. 10, openings108D may be provided to form the wafer level package100D ofFIG. 4. In general, only differences between the openings108D illustrated inFIG. 10and the openings108A illustrated inFIG. 7will be described below. Thus, e.g., the openings108D may also extend completely through a thickness of the wafer102. In this exemplary embodiment, the openings108D may form, e.g., a connecting portion136C at one lateral side of the semiconductor wafer104C. More particularly, in this exemplary embodiment, a single connecting portion136C may be defined as a result of a single opening108D partially surrounding the semiconductor chip104C. The connecting portion136C may be provided at, e.g., a central portion or a left or right side portion of the lateral side of the semiconductor chip104C. That is, in some embodiments of the invention, e.g., a single opening, such as opening108D, may be formed to define a single connecting portion136C for each of the semiconductor chips104C on the wafer102.

Referring back toFIG. 6, after forming the openings, e.g.,108A,108B,108C,108D during step S64, the exemplary method may then proceed to step S68. During step S68, the semiconductor chip, e.g.,104,104A,104B,104C, may be covered with, e.g., a resin.

More particularly, each side of the semiconductor chip, e.g.104,104A,104B,104C may be covered with resin and the respective opening(s), e.g.,108A,108B,108C,108D, may be filled. In some embodiments, a thickness of the resin on respective sides of the semiconductor chip, e.g.,104,104A,104B,104C, may be substantially uniform, while in some other embodiments, a thickness of the resin may vary on some or all sides of the semiconductor chip, e.g.,104,104A,104B,104C. While each side of the semiconductor chip, e.g.,104,104A,104B,104C may be completely covered with the resin, as shown inFIGS. 1 through 4, upper portions of the respective connectors110remain exposed. For simplicity, the remaining steps of the exemplary method will be described with reference to the exemplary wafer level package100A illustrated inFIG. 1. However, the method described may be used to form any of the described exemplary wafer level packages100A,100B,100C,100D and other embodiments of the invention.

FIG. 11illustrates an exemplary method of covering the semiconductor chip104with resin by dipping the wafer102including semiconductor chips104, including opening(s)108in a bath120containing, e.g., epoxy resin122, i.e., a thermosetting polymer. The epoxy resin122may include, e.g., a catalyzing agent, i.e., hardener, such that the cover112may be formed when the wafer102is covered by the epoxy resin122. More particularly, the wafer102may be partially dipped in the epoxy resin122such that upper portion(s) of the connector(s)110may remain resin-free, i.e., exposed. That is, by dipping the wafer102in the epoxy resin, all sides of the semiconductor chip(s)104and/or the respective opening(s)108may be simultaneously and/or substantially simultaneously covered with, e.g., epoxy resin122in a single processing step. Thus, embodiments of the invention may provide a simplified method of substantially completely encapsulating the semiconductor chip(s)104, e.g., completely encapsulating the semiconductor chip(s)104except for the connector(s)110and the at least one connecting portion136, in a single covering step.

More particularly, the bath120may be vibrated while the wafer102is dipped therein to help ensure that the epoxy resin122covers all sides of the semiconductor chip(s)104and fills, e.g., completely fills, the opening(s)108A surrounding the semiconductor chip(s)104. Although a dipping method is illustrated inFIG. 11for covering the semiconductor chip104with, e.g., the resin, other methods of covering the semiconductor chip104may be employed. More particularly, e.g., other known methods for simultaneously covering all sides of the semiconductor chip104in a single covering step may be employed.

FIG. 12illustrates a cross-sectional view of the wafer102after covering all the sides of the semiconductor chip(s)104, i.e., after the covering step S68, andFIG. 13illustrates a more detailed cross-sectional view of a portion of the wafer102after the covering step S68. As shown inFIG. 12, after the covering step S68, the cover112may substantially completely encapsulate the semiconductor chip(s)104, except for the connector(s)110and the at least one connecting portion136.

Referring toFIG. 13, in some embodiments of the invention, the height H1of the cover may be about 10% to about 80% of the height H2of the connector110.

Referring again toFIG. 6, after covering all the sides of the semiconductor chip(s)104on the wafer102, i.e., step S68, the method may proceed to step S72. During step S72, the semiconductor chip(s)104may be completely separated from the wafer102.

FIG. 14illustrates a cross-sectional view of the wafer102after covering all the sides of the semiconductor chip(s)104, i.e., after the covering step S68, including second cutting boundary114. Another cutting step employing, e.g., a laser or diamond blade, may be performed to completely separate the semiconductor chip(s)104by cutting along the respective cutting boundary114. The cutting boundary114may correspond to an imaginary predetermined line, lane or region between, e.g., the respective semiconductor chip(s)104. Further, after the completely separating step S72, portions of the respective connecting portion(s)136may correspond to the protruding portion(s)116A.

As discussed above, during the first cutting step for forming the opening(s)108, the width Ws of the scribe line106, corresponding to the first cutting width, i.e., step S64, may be substantially the same as or less than the width Ws of the scribe line106. In some embodiments of the invention, during the second cutting step for completely separating the semiconductor chip(s)104from the wafer102, i.e., step S72, a second cutting width may be less than the first cutting width. That is, in embodiments of the invention, step S72may be carried out so as to provide the resulting portion of the cover112, corresponding to where the resin122filled the opening(s)108, with a sufficient width to protect the semiconductor chip104afrom damage, e.g., external impact. That is, a relationship between the first cutting width and the second cutting width may determine a distance that the resulting protruding portion(s)116A may protrude from the respective side(s) of the semiconductor chip104, and thus, may determine an efficacy of the protruding portion116A as a protection member. More particularly, e.g., if the first cutting width was about 80 μm and the second cutting width is about 20 μm, a width of the resulting protruding portion116A of the cover112after step S72, may be about 30 μm. Referring toFIG. 6, the exemplary method may then be complete, i.e., step S76.

FIGS. 15,16,17and18illustrate stages in a second exemplary method for fabricating a wafer level package according to one or more aspects of the invention. In general, only differences between the exemplary embodiment illustrated inFIGS. 15-18and the exemplary embodiment described above will be described below.

Referring toFIG. 15, according to the second exemplary embodiment, the resin coating process includes a spin coating method instead of the dipping method. According to the second exemplary method, the process may begin by forming a coating repellent211on upper portions of each connector210provided on semiconductor chip204formed on a wafer202. In some embodiments of the invention, a thickness of the coating repellent211on the upper portion of each connector210may not exceed about 50% of a height of the connector210, e.g., a distance that the connector210projects above a top surface of the wafer202.

Next, referring toFIG. 16, at least one opening208may be formed in the wafer202around the respective semiconductor chip204. The opening208may correspond, e.g., to any of the exemplary openings108A,108B,108C,108D described above.

Next, referring toFIG. 17, a spin coating process may be performed to coat all sides of the semiconductor chip204during a single coating step. In this exemplary embodiment, the wafer202may be arranged on a chuck (not shown) and may be spun while resin is deposited thereon. While the wafer202is being spun by the chuck, the wafer may be slightly elevated above a surface of the chuck such that the resin may coat a bottom surface of the wafer202while coating a top surface thereof and filling, e.g., completely filling, the opening(s)208to form a cover212. The cover212may substantially completely encapsulate the semiconductor chip204, except for the connector(s)210and at least one protruding portion (not shown) thereof.

Next, referring toFIG. 18, similar to the process described above with regard toFIG. 14, the semiconductor chip(s)204may be completely separated from the wafer202by a second cutting step along a cutting boundary214using, e.g., a laser or a diamond blade having a width that less than a width of a laser or diamond blade used to form the opening(s)208. By using, e.g., a laser or diamond blade during the second cutting step, i.e., the completely separating step S72, that has a smaller width than a width of the laser or diamond blade used during the first cutting step, i.e., the partially separating step, a distance that resulting protruding portions protrude from a respective side of the semiconductor wafer204may be controlled to ensure that that cover212may serve to protect the semiconductor wafer204therein.

Multi-chip packages (MCPs) enable discrete components, which may be implemented in a same or different technology, to be integrated into a single IC package. MCPs are increasing in popularity for a wide range of applications, e.g., MCPs for mobile phone applications, MCP memories that integrate, e.g., flash memory and a controller. Aspects of packaging embodiments discussed above may be employed, e.g., to implement such MCPs. For example, when fabricating MCPs, the covering step S68and/or the completely separating step S72may be executed after vertically stacking wafers including discrete components of the MCP to be integrated.

FIG. 19illustrates an exemplary card system700, e.g., a multi-media card or a secure digital card, which may be implemented according one or more aspects of the invention. Referring toFIG. 19, the card700may include a controller710and a memory720. The memory720may be, e.g., a flash memory, a PRAM, a DRAM, etc. For example, the memory720, the controller710and an interface therebetween for exchanging, e.g., data and/or commands, may be packaged together as an MCP using one or more aspects of the invention.

FIG. 20illustrates an exemplary electronic system800, which may be implemented according to one or more aspects of the invention. Referring toFIG. 20, the system800may include a processor810, a memory820, an I/O (input/output) device830and a bus840. The system800may be, e.g., a mobile phone, an MP3 device, a navigation system, a solid state disk (SSD), a household appliance, etc. For example, the memory820, the processor810, the I/O device830and the bus840may be packaged together as an MCP using one or more aspects of the invention. More particularly, e.g., in some cases, one, some or all of the memory820, the processor810and the I/O device840may be vertically stacked on each other before being packaged as an MCP according to one or more aspects of the packaging embodiments described above.