Terahertz phased array system

Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. patent application Ser. No. 12/871,626, entitled “DOWNCONVERSION MIXER,” filed on Aug. 30, 2010, which is hereby incorporated by reference for all purposes.

TECHNICAL FIELD

The invention relates generally to a phased array and, more particularly, to an “on-chip” terahertz phased array system.

BACKGROUND

Phase array systems have become commonplace, having several uses. The most common use for phased array systems is radar systems (i.e., pulse radar and Doppler shift radars). As a matter of fact, phased array radar has replaced most of the previous generations of mechanical sweep radar systems because there is a lower likelihood of failure due to wear since mechanic components are replaced with electronics and because the sweep rates are much higher.

Turning toFIG. 1, block diagram illustrating the basic functionality of a conventional phased array system100. System100generally comprises a signal generator102, phase shifters104-1to104-k, a phased array110that includes radiators106-1to106-k, and a direction controller108. In operation, the signal generator102provides a signal that is to be transmitted (i.e., pulse for a pulse radar). Based on the desired direction, the direction controller108provides control signals to the phase shifters104-1to104-k, which varies the phase of the signal provided to each of the radiators106-1to106-kwithin the phased array. Because the signals transmitted through radiators106-1through106-kare generally out-of-phase with one another, constructive and destructive interference of the radiated signal forms a beam in a desired direction.

These conventional systems, though, have been limited to conventional radio frequency (RF) frequency ranges. For example, the frequency range for conventional radar is between 3 MHz (for HF-band radar) and 110 GHz (for W-band radar). A reason for the use of these relatively low frequency ranges is that there has, historically, been an unavailability of compact semiconductor sources of coherent radiation at the terahertz frequency range (which is generally between 0.1 THz and 10 THz). Generally, electronics and oscillators in the microwave range run out of power gain with increasing frequency, and typical broadband infrared blackbody sources begin losing available power within this region. Use of terahertz radiation, however, is highly desirable because of its unique properties. Namely, terahertz radiation has properties of lower frequency radiation (i.e., microwaves) in that it can be generated electrically and higher frequency radiation (i.e., visible light) in that it can be controlled using optics.

Today, there exists two general types of terahertz sources: incoherent source and coherent sources. The incoherent sources are generally broadband incoherent thermal sources, which includes ultra-short femtosecond pulsed laser exciting photo conductive antennas, nonlinear electro-optical crystals, or non-linear transmission lines that suffers from very poor conversion efficiency (1 W laser pulse produces broadband energy in the nW-mW range). The coherent sources are generally narrowband continuous wave (CW) coherent sources which include diode multiplying microwave oscillators, gas lasers using carbon dioxide laser pumping methanol or cyanic acid, optical down conversion by difference mixing, and semiconductor quantum lasing. These coherent sources, though, generally consume a large amount of power, are not compact, require exotic materials, and/or are expensive.

Therefore, there is a need for a compact source of terahertz radiation, namely integrated into an integrated circuit.

SUMMARY

A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a local oscillator that generates a local oscillator signal and a pulse signal; a distribution network that is coupled to the local oscillator so as to at least distribute the local oscillator signal; a plurality of transceivers, wherein each transceiver has a radiator, a transmit path that is coupled to the radiator, and a receive path that is coupled to the radiator, and wherein the transmit path for each transceiver includes: a phase shifter is coupled to the distribution network so as to receive the local oscillator signal; a multiplier that is coupled to the phase shifter so as to receive a phase shifted local oscillator signal; a injection-locked voltage controlled oscillator (ILVCO) that is coupled to the multiplier; and a power amplifier (PA) that is coupled to the ILVCO and that receives the pulse signal; and receiver circuitry that is coupled to the receive path for each of the transceivers.

In accordance with a preferred embodiment of the present invention, the local oscillator signal further comprises a first local oscillator signal, and wherein the local oscillator further comprises: a phase locked loop (PLL) that receives a reference signal and that generates the first oscillator signal and a second local oscillator signal; a counter that receives a control signal and that is coupled to the PLL; and a pulse generator that is coupled to the counter and the PLL, wherein the pulse generator generates the pulse signal based at least in part on the second local oscillator signal and an output from the counter.

In accordance with a preferred embodiment of the present invention, the PLL further comprises: a phase detector that receives the reference signal; a charge pump that is coupled to the phase detector; a low pass filter that is coupled to the charge pump; a voltage controlled oscillator (VCO) that is coupled to the low pass filter; an amplifier that is coupled to the VCO; and a plurality of dividers that are coupled in series with one another between the VCO and the phase detector.

In accordance with a preferred embodiment of the present invention, the transmit path for each transceiver further comprises an amplifier that is coupled between the phase shifter and the multiplier.

In accordance with a preferred embodiment of the present invention, the ILVCO further comprises: a first node; a second node; an inductive network that is coupled between the first and second nodes; a capacitive network that is coupled between the first and second nodes; a first MOS transistor that is coupled to the first node at its source or its drain and to the second node at its gate; a second MOS transistor that is coupled to the second node at its source or its drain and to the first node at its gate; a third MOS transistor that is coupled generally in parallel to the first MOS transistor; a fourth MOS transistor that is coupled generally in parallel to the second MOS transistor; and a balun that is coupled to the amplifier and that is coupled to the gates of the third and fourth MOS transistors.

In accordance with a preferred embodiment of the present invention, the PA further comprises: a first capacitor that receives an output from the ILVCO; a first inductor that is coupled to the first capacitor; a second inductor that is coupled to the first inductor; a second capacitor that is coupled to the second inductor; a third inductor; a fifth MOS transistor that is coupled to the first and second inductor at its gate and that is coupled to the third inductor; a fourth inductor; a fifth inductor; a sixth MOS transistor that receives the pulse signal at its gate and that is coupled between the fourth and fifth inductors; and a third capacitor that is coupled between the third and fifth inductors.

In accordance with a preferred embodiment of the present invention, the amplifier further comprises a first amplifier, and wherein the multiplier further comprises a first multiplier, and wherein the receive path for each transceiver further comprises: a low noise amplifier (LNA) that is coupled to the radiator; a second multiplier that is coupled to the first amplifier; a second amplifier that is coupled to second multiplier; a mixer that is coupled to the LNA and the second amplifier; and a third amplifier that is coupled to the mixer.

In accordance with a preferred embodiment of the present invention, the mixer further comprises a first mixer, and wherein the receive path for each transceiver further comprises: a second mixer that is coupled to the first and third amplifiers; and a fourth amplifier that is coupled to the second mixer.

In accordance with a preferred embodiment of the present invention, the amplifier further comprises a first amplifier, and wherein the transmit path for each transceiver further comprises a flip-flop that receives the pulse signal and that is coupled to the first amplifier, the ILVCO, and the PA, and wherein the multiplier further comprises a first multiplier, and wherein the receive path for each transceiver further comprises: an LNA that is coupled to the radiator; a second amplifier that is coupled to the ILVCO; a mixer that is coupled to the LNA and the second amplifier; and a third amplifier that is coupled to the mixer.

In accordance with a preferred embodiment of the present invention, each phase shifter further comprises: a first input terminal; a second input terminal; a first inductor that is coupled to the first input terminal; a second inductor that is coupled to the second input terminal; and a plurality of phase shifters, wherein each phase shifter includes: a first MOS transistor that is coupled to the first input terminal at its drain; a second MOS transistor that is coupled to the second input terminal at its drain; and a third MOS transistor that is coupled to the sources of the first and second MOS transistors at its drain.

In accordance with a preferred embodiment of the present invention, the multiplier further comprises: a differential choke; a rectifying interleaver that is coupled to the differential choke; and a VCO that is coupled to the rectifying interleaver.

In accordance with a preferred embodiment of the present invention, the receiver circuitry further comprises: a summing circuit that is coupled to the receive path for each transceiver; an amplifier that is coupled to the summing circuit; a filter that is coupled to the amplifier; and digitization circuit that is coupled to the amplifier.

In accordance with a preferred embodiment of the present invention, the local oscillator signal further comprises a first local oscillator signal, and wherein the local oscillator generates a second local oscillator signal, and wherein the receiver circuit further comprises a mixer that is coupled between the summing circuit and the amplifier and that receives the second local oscillator signal.

In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a local oscillator including: a phase detector that receives a reference signal; a charge pump that is coupled to the phase detector; a low pass filter that is coupled to the charge pump; a local oscillator VCO that generates a first local oscillator signal having that is greater than 40 GHz; a plurality of dividers coupled in series with one another between the local oscillator VCO and the phase detector so as to provide a feedback signal to the phase detector that is generated from the first local oscillator signal, wherein the at least one of the plurality of dividers generates a second local oscillator having a frequency that is greater than 20 GHz; a counter that receives the feedback signal and a control signal; and a pulse generator that receives the second local oscillator signal, that is coupled to the counter, and that generates a pulse signal; a distribution network that is coupled to the local oscillator so as to at least distribute the first local oscillator signal; a plurality of transceivers, wherein each transceiver has a radiator, a transmit path that is coupled to the radiator, and a receive path that is coupled to the radiator, and wherein the radiators are arranged into an array, and wherein the transmit path for each transceiver includes: a phase shifter is coupled to the distribution network so as to receive the first local oscillator signal; a multiplier that is coupled to the phase shifter so as to receive a phase shifted first local oscillator signal; an ILVCO having: a first node; a second node; an inductive network that is coupled between the first and second nodes; a capacitive network that is coupled between the first and second nodes; a first MOS transistor that is coupled to the first node at its source or its drain and to the second node at its gate; a second MOS transistor that is coupled to the second node at its source or its drain and to the first node at its gate; a third MOS transistor that is coupled generally in parallel to the first MOS transistor; a fourth MOS transistor that is coupled generally in parallel to the second MOS transistor; and a balun that is coupled to the first multiplier and the gates of the third and fourth MOS transistors; a PA that is coupled to the ILVCO and its radiator and that receives the pulse signal; and receiver circuitry that is coupled to the receive path for each of the transceivers.

In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a plurality of radiators that are arranged in a pattern for form an array; a local oscillator that generates a local oscillator signal and a pulse signal; a distribution network that is coupled to the local oscillator so as to at least distribute the local oscillator signal; a plurality of transmitter paths, wherein each transmitter path is coupled between the distribution network and at least one of the radiators, and wherein each transmit path includes: a phase shifter is coupled to the distribution network so as to receive the local oscillator signal; a multiplier that is coupled to the phase shifter so as to receive a phase shifted local oscillator signal; an ILVCO that is coupled to the multiplier; and a PA that is coupled to the ILVCO and that receives the pulse signal; and a plurality of receiver paths, wherein each receiver path is coupled to at least one of the radiators; receiver circuitry that is coupled to each receive path; and a controller that is coupled to each phase shifter.

In accordance with a preferred embodiment of the present invention, the summing circuit further comprises a summing amplifier tree.

DETAILED DESCRIPTION

Turning toFIG. 2, a phased array system200in accordance with a preferred embodiment of the present invention can be seen. The phase array system200generally comprises a LO202, a phased array224, a distribution network226, receiver circuitry228, and controller208. The phased array224generally comprises several transceivers204-1to204-N arranged in an array. The distribution network226generally comprises amplifiers206and208-1to208-N. Additionally the receiver circuitry generally comprises a summing circuit210, a mixer212, amplifier214, filter216, switches218-1to218-N, variable selector220, and ADCs222-1to222-N.

In operation, phased array system200(which is generally incorporated into an integrated circuit or IC) can generate a short range radar system that operates in the terahertz frequency range (which is generally between 0.1 THz and 10 THz). To accomplish this, local oscillator202generates a high frequency signal FL01that is on the order of tens to hundreds of gigahertz (i.e., 40 GHz, 50 GHz, 67 GHz, and 100 GHz.) and a pulse signal TPUSLE. The distribution network226then provides signal FL01to each of the transceivers204-1to204-N such that the signals received by each of transceivers104-1to204-N are substantially in-phase. A controller208provides a control signal to array224, which phase-adjusts the transceivers204-1to204-N with respect to one another to direct a beam of terahertz frequency radiation. The transceivers204-1to204-N can then receive reflected radiation back from a target, which is provided to summing circuit210. The output of summing circuit210is the converted to a digital signal by a mixer212, amplifier214, filter216, switches218-1to218-N, variable selector220, and ADCs222-1to222-N. Additionally, mixer212can receive a divided signal from LO202(i.e., FL01/2or another synthesized signal) or can be removed (typically for 40 GHtz or less).

Generally, this phased array system200has several different types of operational modes: pulsed, continuous, and stepped frequency. For a pulsed operational mode, a pulse of terahertz radiation is directed toward a target. The continuous operational mode uses a continuously generated beam, which is generally accomplished by effective “shutting off” the pulse signal TPULSE. Finally, stepped frequency allows to frequency of the terahertz beam to be changed, which can be accomplished by employing a bank of local oscillators (i.e.,202). For the pulsed operational mode, in particular, the range of the system200is governed by the following equation:

R=σ⁢PG2⁢λ⁢⁢nE⁡(n)(4⁢π)3⁢kTBF⁡(SN)4,(1)
where:R is distance that can be measured or range;σ is the radar cross section of the target (usually not equal to the physical cross section);S/N is single pulse SNR at the intermediate frequency IF filter output (envelope detector input);kTB is the effective incoming noise power in receiver bandwidth B (B≈1/pulsewidth);F is noise figure of the receiver (derived parameter);P is the peak transmitter power;G is the antenna power gain;λ is wavelength of the radiation (i.e., for 200 GHz, ≈1.5 mm);n is number of integrations of pulses in the receiver (multi-pulse averaging); andE(n) is the efficiency of integration.
For a monolithically integrated, low power IC that includes system200, this range is generally less than one meter.

Turning toFIG. 3, an example of the LO202can be seen in greater detail. Generally, this LO202employs a phase locked loop (PLL)326that generates signals FL01and FL02from reference signal REF and employs counter322and pulse generator324to produce the pulse signal TPULSE. PLL326is generally comprised of a phase detector302, charge pump304, low pass filter304, amplifiers310and312, voltage controlled oscillator (VCO)308, and dividers320,318,316, and314. In operation, the phase detector302receives a feedback signal from divider314and the reference signal REF, and (along with charge pump304and low pass filter306) generates a tuning voltage for VCO308. Typically, VCO308generates a high frequency signal (i.e., 100 GHz, 67 GHz, 50 GHz, or 40 GHz) which is amplified by amplifiers310and312, producing signal FL01. Divider320(which is generally an injection-locked, divide-by-2 frequency divider) receives the output of amplifier to output signal FL02. Signal FL02is then provided to divider318(which is generally a divide-by-2 current mode logic divider). The output of divider318is provided to divider316(which is generally a divide-by-8 current mode logic divider), and the output of divider316is provided to divider314(which is generally a divide-by-M CMOS divider) to generate the feedback signal. The counter322generates a count signal based on a control signal CNTL and the feedback signal from divider314, and the pulse generator234produces the pulse signal TPULSE based at least in part on the count signal from counter322and the outputs of dividers318and320.

InFIG. 4, an example of one of transceivers202-1to202-N (referred to as202-A) can be seen in greater detail. As shown, transceiver202-A generally includes a transmit path402-A and a receive path404-A that are each coupled to radiator426(i.e., antenna). During transmission, phase shifter404(which is generally controlled by controller230) receives signal FL01from LO202and phase-shifts signal FL01accordingly. This phase shifted signal is amplified by amplifier408and multiplied by multiplier410-A (which is typically a multiply-by-3 multiplier) that allows the signal FL01to be increase to the desired frequency range. For example, if signal FL01is about 67 GHz, then multiplier410-A would output a signal having a frequency of about 201 GHz. This multiplied signal is provided to ILVCO412, which is generally used to compensate for losses from multiplier410-A. Additionally, ILVCO412receives the pulse signal TPULSE. Power amplifier (PA)414then amplifies the output of ILVCO412for transmission through radiator426. Typically, the pulse widths of pulse signal TPULSE are about 30 ps, 60 ps, or 90 ps when the signal FL01has a frequency of about 67 GHz. During reception, radiator426receives a signal, which is amplified by amplifier420. This amplified signal is mixed with a signal having a frequency that is a multiple of signal FL01. Typically, multiplier416(which is generally a multiply-by-2 multiplier) receives an output from amplifier408, and the result is amplified by amplifier418and provided to mixer422. The mixed output is then amplified by amplifier424and provided to summing circuit210. Additionally, mixer422is described in co-pending of U.S. patent application Ser. No. 12/871,626 entitled “DOWNCONVERSION MIXER.”

Looking toFIG. 5, an alternative configuration for one of transceivers202-1to202-N (referred to as202-B) can be seen in greater detail. The transmit path402-B is similar to transmit path402-A; however, multiplier410-B has replaced multiplier410-B. Generally, multiplier410-B has a large range than multiplier410-B to accommodate a lower frequency signal FL01. For example, if signal FL01has a frequency of 50 GHz, then multiplier410-B can be a multiply-by-4 multiplier to generate a signal that is on the order of 200 GHz. Additionally, to accommodate a lower frequency signal FL01, receive path404-B includes a mixer428that mixes the outputs of amplifiers424and408and an amplifier430. Also, the pulse widths of pulse signal TPULSE can be about 40 ps or 80 ps when the signal FL01has a frequency of about 50 GHz.

Turning toFIG. 6, yet another alternative one of transceivers202-1to202-N (referred to as202-C) can be seen in greater detail. Here, D flip-flop432has been included in the path for the pulse signal TPULSE; namely, the input terminal of flip-flop432receives the pulse signal TPULSE, while flip-flop is clocked by the output of amplifier408. Additionally, multiplier416and amplifier418have been replaced by amplifier434. This arrangement is generally useful for even lower frequency ranges (i.e., 40 GHz), which can produce pulse widths for pulse signal TPULSE are about 50 ps or 100 ps.

InFIG. 7, another alternative one of transceivers202-1to202-N (referred to as202-D) can be seen in greater detail. Here, the transmit path402-D is similar to path204-A; however, multiplier410-A has been replaced with multiplier410-D, while amplifier408has been removed. Multiplier410-D generally has a lower range to accommodate a signal FL01with a high frequency. For example, if signal FL01has a frequency of about 100 GHz, then multiplier410-D can be a multiply-by-2 multiplier. Additionally, for receive path404-D, multiplier416and amplifier418have been removed so that mixer422mixes the output of LNA420with the output of phase shifter406.

Turning now toFIG. 8, a circuit diagram of an example of multipliers410and/or416can be seen. This type of multiplier410and/or416is generally employed within transceivers202-1to202-N to produce very high frequencies (i.e., 200 GHz) because direct production of these high frequency signals is very difficult. Generally, multiplier410and/or416employs a differential choke802, a rectifying interleaver804, and a VCO806. Typically, VCO806uses two oscillator tanks to generate two pairs of output signals from differential in-phase signals VIP and VIM and differential quadrature signals VQM and VQP. Typically, VCO806comprises MOS transistors Q5through Q12, inductors L3through L6, and capacitors C1and C2. Rectifying interleaver804employs two differential pairs of transistors Q1/Q2and Q3/Q4and current sources810and812to interleave the outputs from VCO806to generate a single-ended output signal OUT. Additionally, a termination808and inductors L1and L2(from differential choke802) are coupled to the rectifying interleaver804. Typically, power output is sufficient to lock ILCVO412(i.e., −20 bBm).

InFIG. 9, an example of phase adjuster406can be seen. Here, a differential input signal IN (which is generally signal FL01from LO202) is provided to differential pairs of MOS transistors Q13/14, Q15/Q16, Q17/Q18, and Q19/Q20(which are also coupled to inductors L7and L8). Based on control signals VC1through VC4received from controller236, transistors Q21through Q24can activate the differential pairs Q13/14, Q15/Q16, Q17/Q18, and Q19/Q20to generate a phase rotation of the differential input signal IN, having a total phase shift range of less than about ±22.5°. Typically, phase shifting is performed in the lower frequency domain (i.e., 50 GHz) to generally ease any bandwidth requirements and efficiently recover power losses.

Turning toFIG. 10, a circuit diagram of an example of ILVCO412can be seen. ILVCO412is generally employed because of the losses from multiplier410. Theoretically, ILVCO412can provide an infinite gain if the center frequencies match with a finite gain throughout the locking range. Typically, MOS transistors Q25and Q28are coupled at their respective gates to balun1002, which receives an output from multiplier410(i.e.,410-A,410-B, or410-C). In an alternative configuration, MOS transistor Q28can receive receives an output from multiplier410(i.e.,410-A,410-B, or410-C) at its gate, while MOS transistor Q28receives the pulse signal TPULSE at its gate. These transistors Q25and Q28are generally coupled in parallel to a gain stage (which is generally comprised of cross-coupled MOS transistors Q26and Q27) and the oscillator tank (which is generally comprised of capacitors C3and C4and inductors L9and L10). Alternatively, the second harmonic of the output can be used instead of first harmonic to relax any tuning range requirements, but with reduced output power. As an illustration, the properties of ILVCO412can be seen in Table 1 below using both the first and second harmonics.

InFIG. 11, a circuit diagram for an example of PA414and/or LNA420can be seen. Generally, the PA414and/or LNA420can provide linear amplification and isolation, and one of the features of PA414and/or LNA420is its ability to be power gated with a fast pulse time (i.e., tens of picoseconds). PA414and/or LNA420generally comprise inductors L11through L15, capacitors C5through C7, and transistors Q29and Q30. Here, the capacitors C5through C7are resonated by series or shunt inductors L11through L15to provide the amplification with transistors Q29and Q30. Additionally, the input and output of PA414and/or LNA420can be matched input or output impedances. For example, for PA414, the output impedance can be matched to the radiator426. Moreover, the circuit shown inFIG. 11can be cascaded in multiple stages, where the gain can be between 0 and 2 dB per stage.

Turning toFIG. 12, an example of a radiation426can be seen. Here, radiator426is shown as being a patch antenna formed over a substrate210. This patch antenna generally comprises a patch1204having slots128that are generally parallel to ground strips and radiating edges1202. For a frequency of about 410 GHz (which has a wavelength of about 0.75 mm in air), the width W and length L of patch1204are each about 200 μm, while the slots are 2 μm wide. The proportions of the patch antenna can then be varied so as to accommodate a desired emission frequency (and wavelength). These radiators426(i.e., patch antennas) can then be formed into an array as shown inFIG. 13. Alternatively, radiator426can be a bondwire Yagi-Uda antenna.

Because the data bandwidth of system200is very high (i.e., on the order of tens of gigahertz), it is generally impractical to employ an ADC that digitizes the signals receives through by the receiver circuitry228. InFIGS. 14 and 15, timing diagrams can be seen that generally depict the operation of the receiver circuitry228, where each uses a trigger signal to reconstruct the received signal. ForFIG. 14, variable selector220actuates switches218-1to218-N at various periods (i.e., Δ1to Δ4) following the trigger signal to allow each of the ADCs222-1to222-N to resolves a portion of the received signal.FIG. 15, on the other hand, use an envelop signal following the periods (i.e., Δ1to Δ4) as part of the control mechanism for switches218-1to218-N.

To accomplish this, there are several approaches that can be taken. InFIG. 16, an example for one arrangement can be seen. In this arrangement, the switches218-1to218-N are comprised of zener diodes D1to DN, capacitors CS1to CSN, and pulse circuits1602-1to1602-N (which are generally controlled by the variable selector220). These switches218-1to218-N operate as an input sampling network where each capacitor CS1to CSN is coupled to a “slow” ADC222-1to222-N. Generally, this approach may require very small apertures and very accurate clock generation.

Another arrangement can be seen inFIG. 17. For this arrangement, ADCs222-1to222-N (referred to as222) are low pass/band pass sigma-delta converters that can directly digitize about a 10 GHz bandwidth with a clock of about 100 GHz. ADC222generally comprises a filter1702, a quantizer1704, a delay1712, a digital-to-analog converter (DAC)1714, and amplifiers1716and1718. The quantizer1704generally comprises quantizers1706-1and1706-2, clock divider1710, and multiplexer1708. In operation, a feedback signal (which is amplified by amplifier1718) is combined with the input signal and filtered by filter1702. This filtered output is combined with the feedback signal (which is amplified by amplifier1716). Quantizer1704(which is generally an 2-bit, 2-way interleaved quantizer operating at 1.5 GHz) quantizes the signal (which is then delayed by delay1712and converted to a feedback signal by DAC1714).

The filter1702can be seen in greater detail inFIG. 18. In particular, the filter1702operates as amplifier and LC filter. To accomplish this, filter1702generally comprises a transconductor cell1804(which generally comprises transistors Q31through Q36, linearizer1802and switches51and S2) and a negative transconductor cell1806(which generally comprises transistors Q37through Q40) that are each coupled to an LC circuit1808(which generally comprises inductors L16and L17and capacitor C8).

Yet another approach can be seen inFIGS. 19A,19B, and19C. Here, a time to digital converter1902is coupled to each ADC222-1to222-N; only one ADC, labeled222, is shown, however. This converter1902has sub-picosecond resolution and, in operation, enabled when the input signal transitions to logic high or “1.” This activates the gated ring oscillator1904so that the counters1906can performed counting operations from the taps of the oscillator1904. The outputs from the counters1904can then be summed and stored in register1904.

Turning toFIG. 20, a circuit diagram of an example of summing circuit210can be seen. Typically, summing circuit210is a summing amplifier that is formed as a summing amplifier tree. As shown inFIG. 20, each summing circuit or summing amplifier2002receives a pair of input signals. At the first stage2004-1of the tree each summing circuit2002is coupled to a pair of transceivers (i.e.,204-1and204-1). Then each subsequence stage (i.e.,2004-2) receives input signals from a pair of summing circuits2002from the previous stage (i.e.,2004-1). As a result the tree has a depth of log2N, where N is the number of transceivers204-1to204-N.