Method of fabricating semiconductor device and semiconductor device

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-209849, filed on Aug. 18, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND

Recently, in accordance with miniaturization of a semiconductor element, a method capable of forming a pattern having a dimension beyond a resolution limit in lithography method is required.

As one sample of the method, a method is known, that includes steps of forming sidewall patterns on side surfaces of core materials, eliminating the core materials, and etching a workpiece film by using the sidewall patterns as a mask, for example, disclosed in JP-A-1996-55908.

Since the sidewall patterns and wiring patterns formed by using the sidewall patterns as a mask have closed loop shapes, a step of a closed loop cut for cutting a part of the closed loop shape is needed. In case that the other patterns exist close to the sites where the closed loop cut is carried out, generally, spaces are created between the other patterns in terms of a margin of displacement at the alignment in the lithography method.

BRIEF SUMMARY

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

A method of fabricating a semiconductor device according to another embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern having parts parallel to the first pattern which have a first distance between the linear parts of the first pattern, and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and forming a resist in the parts of the second pattern so as to have a second distance between the linear parts of the first pattern larger than the first distance, and carrying out a closed loop cut at the parts of the second pattern in which the resist is formed.

A method of fabricating a semiconductor device according to another embodiment includes forming a first pattern group including a plurality of first patterns arranged at a predetermined pitch, and second pattern group including a plurality of second patterns arranged at the predetermined pitch, the closest second patterns to at least the first pattern group of the plural second patterns having parallel parts parallel to the first pattern group and parts away from the second pattern group and constituting closed loop shapes independently of the first pattern group or in a state of being connected to the first pattern group and carrying out a closed loop cut at the parts of the second pattern away from the first pattern group.

A semiconductor device according to another embodiment includes a first pattern group including a plurality of first patterns arranged at a predetermined pitch and a second pattern group including a plurality of second patterns arranged at the predetermined pitch, wherein the closest second patterns to at least the first pattern group of the plural second patterns have parallel parts parallel to the first pattern group and nonparallel parts formed so as to be connected to the parallel parts, to be away from the first pattern group and to be not parallel to the first pattern group.

DETAILED DESCRIPTION

A method of fabricating a semiconductor device according to the embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

As the foundation layer, a substrate such as a silicon substrate or a workpiece film to be processed by using the first and second patterns as a mask can be used. Further, the workpiece film can be formed between the foundation layer and the first and second patterns.

As the first and second patterns, a bit-line and a word line constituting a memory device, a wiring by a line and space, or a pattern used as a mask can be used.

As the first pattern, for example, a pattern having a closed loop shape or a line pattern can be used. Further, the first pattern can include a part having a line width wider than that of the linear part of the constant line width.

The part of the second pattern close to the linear part of the first pattern is, for example, a parallel part close to and parallel to the linear part of the first pattern. The parallel part of the second pattern can have a linear shape or a carved shape, if it is parallel to the linear part of the first pattern.

FIGS. 1A to 1Hare cross-sectional views schematically showing each feature in a fabrication process of a semiconductor device according to the first embodiment.FIGS. 2A to 2Care plan views schematically showing processes of a closed loop cut carried out between the process shown inFIG. 1Dand the process shown inFIG. 1E.

As shown inFIG. 1A, a wiring material (a workpiece film)11for forming a wiring layer via a foundation layer10is formed on a semiconductor substrate such as a silicon substrate, a mask material12is formed on the wiring material11and core patterns13a,13bare formed on the mask material12by a lithography method and an etching process which use a resist. The core patterns13a,13bhave, for example, a line width (for example, 40 nm) near the resolution limit “W” of lithography method.

As the wiring material11, for example, Cu, W, Al or the like can be used. As the mask material12, for example, silicon oxide film or the like can be used. As the core patterns13a,13b, for example, amorphous silicon film or the like can be used.

Next, as shown inFIG. 1B, a slimming treatment is carried out so as to make the width of the core patterns13a,13bthin up to a half size by an anisotropic etching or the like. By this, the core patterns13a,13bhaving a line width (for example, 20 nm) of almost a half size of the resolution limit “W” can be obtained.

Next, as shown inFIG. 1C, a film to become a material of side wall patterns is deposited on the whole surfaces including the side surfaces of the core patterns13a,13bafter the slimming treatment, parts of the film which are deposited on the upper surfaces of the core patterns13a,13band the surface of the mask material12are eliminated by using the anisotropic etching or the like so as to form side wall patterns14a,14bon the side surfaces of the core patterns13a,13b. The side wall patterns14a,14bhas, for example, a line width and an distance of almost a half size of the resolution limit “W”.

The side wall patterns14a,14bare formed of a material having a high etching selectivity to the core patterns13a,13b, for example, if the core patterns13a,13bare formed of the amorphous silicon film, silicon nitride film or the like can be used as the material.

Next, as shown inFIG. 1D, the core patterns13a,13bare eliminated by a dry etching such as a chemical dry etching (CDE), a reactive ion etching (RIE) or the like so as to leave the side wall patterns14a,14bhaving a high etching selectivity to the core patterns13a,13b. At this time, each of the both end portions of the side wall patterns14a,14bforms a closed loop shape.

InFIG. 2A, the side wall patterns14bshow an object pattern (the second pattern) which is an object of the closed loop cut, and the side wall patterns14ashow an adjacency pattern (the first pattern) adjacent to the side wall patterns14b. In case of the embodiment, the side wall patterns14a,14binclude linear parts of a constant line width. Further, the adjacency pattern can be an object of the closed loop cut. In order to carry out the closed loop cut of the side wall patterns14b, in terms of a margin of displacement at the alignment in the lithography method, it is needed for a region of the side wall patterns14bwhere the closed loop cut is carried out to be away from the side wall patterns14aso that the resist15does not fall over the side wall patterns14a. Therefore, the side wall patterns14bare formed so as to have the following shape.

Namely, the side wall patterns14bare close to the side wall patterns14aso as to have a distance “d” (a first distance) between the side wall patterns14a, and has parallel parts140parallel to the side wall patterns14aand nonparallel parts141formed so as to be connected to the parallel parts140and to be not parallel to the side wall patterns14a, and cut regions141awhere the closed loop cut is carried out is formed in the nonparallel parts141. The nonparallel parts141are formed in a shape bent in an oblique direction from the joining point of the parallel part140and the nonparallel part141so as to be apart from the side wall patterns14a, but it can have a shape bent in a rectangular direction.

As shown inFIG. 2B, a space “S” (a second distance) is formed on the cut region141alocated at the end portions of the side wall patterns14b, between the side wall patterns14aand a resist15is formed, and as shown inFIG. 2C, the cut region141aof the side wall patterns14bis cut by the lithography method. The space “S” is formed so as to be larger than the distance “d” (the first distance) between the side wall patterns14aand the side wall patterns14b.

Next, as shown inFIG. 1E, the mask material12is eliminated by using the side wall patterns14a,14bas a mask and by a dry etching or the like where a gas such as CF4, CHF3is used so as to form mask patterns12a,12b, and as shown inFIG. 1F, the side wall patterns14a,14bare eliminated by a wet etching or the like.

Next, as shown inFIG. 1G, the wiring material11is etched by using the mask patterns12a,12bso as to form wiring patterns11a,11b, and as shown inFIG. 1H, the mask patterns12a,12bare eliminated by the wet etching or the like.

According to the first embodiment, even if the side wall patterns have an arrangement pitch less than the resolution limit “W” in lithography method, the closed loop cut of the side wall patterns can be carried out.

FIGS. 3A to 3Hare cross-sectional views schematically showing each feature in a fabrication process of a semiconductor device according to the second embodiment andFIGS. 4A to 4Care plan views schematically showing processes of a closed loop cut carried out after the process shown inFIG. 3H. In the first embodiment, the wiring material is preliminarily formed, the closed loop cut of the end portions of the side wall patterns are carried out, and then the wiring pattern is formed from the wiring material, but in the second embodiment, the wiring pattern having a closed loop shape is formed, and then the closed loop cut of the end portions of the side wall patterns is carried out.

As shown inFIG. 3A, the mask material12is formed on a semiconductor substrate such as a silicon substrate via the foundation layer10, and the core patterns13a,13bare formed on the mask material12by a lithography method and an etching process which use a resist. The core patterns13a,13bhave, for example, a line width (for example, 40 nm) near the resolution limit “W” of lithography method.

As the mask material12, for example, silicon oxide film or the like can be used. As the core patterns13a,13b, for example, amorphous silicon film or the like can be used.

Next, as shown inFIG. 3B, a slimming treatment is carried out so as to make the width of the core patterns13a,13bthin up to a half size by an anisotropic etching or the like. By this, the core patterns13a,13bhaving a line width (for example, 20 nm) of almost a half size of the resolution limit “W” can be obtained.

Next, as shown inFIG. 3C, a film to become a material of side wall patterns is deposited on the whole surfaces including the side surfaces of the core patterns13a,13bafter the slimming treatment, parts of the film which are deposited on the upper surfaces of the core patterns13a,13band the surface of the mask material12are eliminated by using the anisotropic etching or the like so as to form side wall patterns14a,14bon the side surfaces of the core patterns13a,13b. The side wall patterns14a,14bhas, for example, a line width and an distance of almost a half size of the resolution limit “W”.

Next, as shown inFIG. 3D, the core patterns13a,13bare eliminated by a dry etching such as CDE, RIE or the like so as to leave the side wall patterns14a,14bhaving a high etching selectivity to the core patterns13a,13b. Each of the both end portions of the side wall patterns14a,14bforms a closed loop shape similarly to the first embodiment.

Next, as shown inFIG. 3E, the mask material12is eliminated by using the side wall patterns14a,14bas a mask and by a dry etching or the like where a gas such as CF4, CHF3is used so as to form mask patterns12a,12b, and as shown inFIG. 3F, the side wall patterns14a,14bare eliminated by a wet etching or the like.

Next, as shown inFIG. 3G, the wiring material11is formed on the whole surfaces including grooves between the mask patterns12a,12bby a sputtering method, a plating method or the like, and then the wiring material11located outside the grooves is eliminated by a chemical mechanical polishing (CMP) so as to fill the wiring material11in the grooves between the mask patterns12a,12b. As the wiring material11, for example, Cu, W, Al or the like can be used.

Next, as shown inFIG. 3H, the mask patterns12a,12bare eliminated so as to form the wiring patterns11a,11band wide patterns11ehaving a width wider than that of the wiring patterns11a,11b. Both of the end portions of the wiring patterns11a,11bare formed in a closed loop shape.

InFIG. 4A, the wiring pattern11bshows an object pattern (the second pattern) which is an object of the closed loop cut, and the wiring pattern11ashows an adjacency pattern (the first pattern) adjacent to the wiring pattern11b. In case of the embodiment, the wiring patterns11a,11binclude linear parts of a constant line width. Further, the adjacency pattern can be an object of the closed loop cut. In order to carry out the closed loop cut of the wiring pattern11b, in terms of a margin of displacement at the alignment in the lithography method, it is needed for a region of the wiring pattern11bwhere the closed loop cut is carried out to be away from the wiring pattern11aso that the resist15does not fall over the wiring pattern11a. Therefore, the wiring pattern11bis formed so as to have the following shape.

Namely, the wiring pattern11bhas parallel parts110parallel to the wiring pattern11aand nonparallel parts111formed so as to be connected to the parallel parts110and to be not parallel to the wiring pattern11a, and cut regions111awhere the closed loop cut is carried out is formed in the nonparallel parts111. The nonparallel parts111are formed in a shape bent in an oblique direction from the joining point of the parallel part110and the nonparallel part111so as to be apart from the wiring pattern11a, but it can have a shape bent in a rectangular direction.

As shown inFIG. 4B, a space “S” (the second distance) is formed on the cut region111alocated at the end portion of the wiring pattern11b, between the wiring pattern11aand a resist15is formed, and as shown inFIG. 4C, the cut region111aof the wiring pattern11bis cut by the lithography method. The space “S” is formed so as to be larger than the distance “d” (the first distance) between the wiring pattern11aand the wiring pattern11b.

According to the second embodiment, even if the wiring pattern has an arrangement pitch less than the resolution limit “W” in lithography method, the closed loop cut of the wiring pattern can be carried out. The side wall patterns14bas the second pattern are close to the side wall patterns14aso as to have a distance “d” (a first distance) between the side wall patterns14a, and has parallel parts140parallel to the side wall patterns14aand nonparallel parts141formed so as to be connected to the parallel parts140and to be not parallel to the side wall patterns14a, and cut regions141awhere the closed loop cut is carried out is formed in the nonparallel parts141.

FIG. 5Ais a plan view schematically showing an example of side wall patterns used in a third embodiment andFIG. 5Bis a detail view of an “A” part of the side wall patterns shown inFIG. 5A. In the first embodiment, the side wall patterns14aas the first pattern have a linear shape and the side wall patterns14bas the second pattern have a nonlinear and bent shape, but in the third embodiment, the side wall patterns14aas the first pattern have a bent shape, and the side wall patterns14bas the second pattern have a linear shape and have the cut regions141ain the end portions where the closed loop cut is carried out.

According to the third embodiment, similarly to the first embodiment, even if the side wall patterns have an arrangement pitch less than the resolution limit “W” in lithography method, the closed loop cut of the side wall patterns can be carried out.

Next, the fourth to the eighth embodiments where the semiconductor device of the first embodiment is applied to a phase-change memory will be explained. The fourth to the eighth embodiments show a case that the wiring patterns11a,11bconstituting each of wiring pattern groups20A,20B include thirty-six (36) lines of 20 nm in line width respectively.

FIG. 6Ais a plan view schematically showing a structure of a wiring pattern in a wiring layer of a phase-change memory used in a fourth embodiment andFIG. 6Bis a detail view of a “B” part of the side wall patterns shown inFIG. 6A.

As shown inFIG. 6A, the phase-change memory1includes a memory cell region2, a WL extraction region3where word lines (WL) are extracted, formed on the right and left sides of memory cell region2, a BL extraction region4where bit lines (BL) are extracted, formed on the top and bottom sides of memory cell region2, and a peripheral circuit disposed under the memory cell region2.

The phase-change memory1includes a plurality of bit lines formed of the wiring patterns11a,11bextending in an “x” direction, a plurality of word lines formed of the wiring patterns21a,21bextending in an “y” direction, and a plurality of memory cells disposed in each of crossing parts of the bit lines and the word lines. The memory cell includes a series circuit having a variable resistive element formed of chalcogenide or the like and a diode such as a Schottky diode. In the phase-change memory1, signal lines for sell selection can be omitted so that high cell-integration can be achieved.

A three dimensional memory structure can be configured by that a cell array is configured so as to include a lower wiring layer where a plurality of word lines are formed, a memory layer having a plurality of memory cells and formed on the lower wiring layer, and an upper wiring layer formed on the memory cells, where a plurality of bit lines are formed, and a plurality of the cell arrays are disposed on a silicon substrate in a stacked state.

As shown inFIG. 6A, the bit lines constituting the upper wiring layer include a first wiring pattern group20A formed at a location totally shifted in the right side and including the wiring pattern11a(the first pattern) of a predetermined lines, and a second wiring pattern group20B formed at a location totally shifted in the left side and including the wiring pattern11b(the second pattern) of a predetermined lines.

As shown inFIG. 6A, the word lines constituting the lower wiring layer include a first wiring pattern group20C formed at a location totally shifted in the top side and including the wiring pattern21a(the first pattern) of a predetermined lines, and a second wiring pattern group20D formed at a location totally shifted in the bottom side and including the wiring pattern21b(the second pattern) of a predetermined lines.

The wiring patterns11a,11binclude terminals11cto which the closed loop cut is carried out in one end portion, and contact fringes11dformed in another end portion by that the closed loop cut is carried out after a treatment of leaving the core materials is conducted. The terminals11cand the contact fringes11dare formed in the WL extraction region3. The wiring patterns21a,21binclude terminals21cto which the closed loop cut is carried out in one end portion, and contact fringes21dformed in another end portion by that the closed loop cut is carried out after a treatment of leaving the core materials is conducted. The terminals21cand the contact fringes21dare formed in the BL extraction region4.

As shown inFIG. 6B, in the wiring pattern11bconstituting the second wiring pattern group20B of the upper wiring layer, a plurality of wiring patterns11badjacent to the first wiring pattern group20A include a parallel part110and a nonparallel part111, and a plurality of wiring patterns11blocated at a center portion do not have the nonparallel part111. The first wiring pattern group20A has also the same structure, and the first and second wiring pattern groups20C,20D on the lower wiring layer have also the same structure.

FIGS. 7A to 7Fare main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the fourth embodiment.FIGS. 7A to 7Dcorrespond toFIGS. 1A to 1Drespectively,FIG. 7Ecorresponds toFIG. 2BandFIG. 7Fcorresponds toFIG. 1H.

Similarly to the first embodiment, after the wiring material and the mask material are formed on the foundation layer, as shown inFIG. 7A, the core patterns13a,13bare formed on the mask material. A plurality of core patterns13bof the second wiring pattern group20B adjacent to the first wiring pattern group20A are bent in the end portions thereof in an oblique direction so as to be apart from the first wiring pattern group20A.

Next, as shown inFIG. 7B, a slimming treatment of the core patterns13a,13bis carried out, and as shown inFIG. 7C, the side wall patterns14a,14bare formed on the side surfaces of core patterns13a,13bafter the slimming treatment, and as shown inFIG. 7D, the core patterns13a,13bare eliminated by an etching so as to leave the side wall patterns14a,14b.

As shown inFIG. 7E, a space “S” is formed on the cut region located at the end portion of the side wall patterns14b, between the first wiring pattern group20A, and the resist15having a hexagonal shape is formed, and the cut regions of the side wall patterns14bare cut by the lithography method. The space “S” between the first wiring pattern group20A and the resist15is, for example, set to 140 nm, in terms of a margin of displacement at the alignment in the lithography method.

Next, the mask material is eliminated by using the side wall patterns14a,14bas a mask and by an etching so as to form mask patterns, and the side wall patterns14a,14bare eliminated. Next, the wiring material is etched by using the mask patterns so as to form wiring patterns11a,11b, and the mask patterns are eliminated. As shown inFIG. 7F, the wiring patterns11a,11bhaving a line width and distance of 20 nm are obtained.

According to the fourth embodiment, even if the side wall patterns have an arrangement pitch less than the resolution limit “W” in lithography method, the closed loop cut of the side wall patterns can be carried out. Further, the first and second wiring pattern groups are alternately shifted in the right and left sides, and the top and bottom sides so that the areas of the extraction regions3,4can be reduced, and high cell-integration of the phase-change memory can be achieved.

FIGS. 8A to 8Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the fifth embodiment.FIG. 8Acorresponds toFIG. 1D,FIG. 8Bcorresponds toFIG. 2B, andFIG. 8Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted.

As shown inFIG. 8A, in the side wall patterns14bconstituting the second wiring pattern group20B of the fifth embodiment, the side wall patterns14bclosest to the first wiring pattern groups20A are connected each other so as to form a closed loop shape and the other thirty-four (34) lines of the side wall patterns14bform the closed loop shapes between the side wall patterns14badjacent to each other.

After that, as shown inFIG. 8B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 8C, the wiring patterns11a,11bsimilar to those of the fourth embodiment are formed.

FIGS. 9A to 9Care main part plan views schematically showing each main part of upper wiring layers used in an example of a fabrication process according to the sixth embodiment.FIG. 9Acorresponds toFIG. 1D,FIG. 9Bcorresponds toFIG. 2B, andFIG. 9Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted.

As shown inFIG. 9A, in the side wall patterns14bconstituting the second wiring pattern group20B of the sixth embodiment, the side wall patterns14bclosest to the first wiring pattern groups20A are connected each other along the end portions of the other side wall patterns14bso as to form a closed loop shape and the other thirty-four (34) lines of the side wall patterns14bform the closed loop shapes between the side wall patterns14badjacent to each other.

After that, as shown inFIG. 9B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 9C, the wiring patterns11a,11bsimilar to those of the fourth embodiment are formed.

FIGS. 10A to 10Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to a seventh embodiment.FIG. 10Acorresponds toFIG. 1D,FIG. 10Bcorresponds toFIG. 2B, andFIG. 10Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted.

As shown inFIG. 10A, in the side wall patterns14bconstituting the second wiring pattern group20B of the seventh embodiment, twenty-six (26) lines of the side wall patterns14blocated at the side close to the first wiring pattern group20A are connected each other so as to form a closed loop shape between two side wall patterns14b, starting from the two side wall patterns14bclosest to the first wiring pattern groups20A. Further, the ten (10) lines of the side wall patterns14blocated interiorly form the closed loop shapes between the side wall patterns14badjacent to each other.

After that, as shown inFIG. 10B, a space “S” is formed on the cut region located at the end portion of the side wall patterns14b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 10C, the wiring patterns11a,11bsimilar to those of the fourth embodiment are formed.

FIGS. 11A to 11Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the eighth embodiment.FIG. 11Acorresponds toFIG. 1D,FIG. 11Bcorresponds toFIG. 2B, andFIG. 11Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted.

As shown inFIG. 11A, in the side wall patterns14bconstituting the second wiring pattern group20B of the eighth embodiment, the side wall patterns14bare connected each other so as to form a closed loop shape between two side wall patterns14b, starting from the side wall patterns14bclosest to the first wiring pattern groups20A.

After that, as shown inFIG. 11B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 11C, the wiring patterns11a,11bare formed.

According to the fourth to eighth embodiments, even if the side wall patterns formed by a line and space have an arrangement pitch less than the resolution limit “W” in lithography method, the closed loop cut of the side wall patterns can be carried out.

Next, the ninth to the thirteenth embodiments where the semiconductor device of the first embodiment is applied to a wiring by a line and space will be explained. The ninth to the thirteenth embodiments show a case that the wiring patterns11a,11bconstituting each of wiring pattern groups20A,20B include thirty-six (36) lines of 20 nm in line width respectively.

FIGS. 12A to 12Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the ninth embodiment.FIG. 12Acorresponds toFIG. 1D,FIG. 12Bcorresponds toFIG. 2B, andFIG. 12Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 11A, in the side wall patterns14bconstituting the second wiring pattern group20B of the ninth embodiment, the side wall patterns14bare connected each other so as to form a closed loop shape between the side wall patterns14b, starting from the side wall patterns14bclosest to the first wiring pattern groups20A, and to provide a symmetrical appearance.

After that, as shown inFIG. 12B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 12C, the wiring patterns11a,11bare formed.

FIGS. 13A to 13Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the tenth embodiment.FIG. 13Acorresponds toFIG. 1D,FIG. 13Bcorresponds toFIG. 2B, andFIG. 13Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 13A, in the side wall patterns14bconstituting the second wiring pattern group20B of the tenth embodiment, sixteen (16) lines of the side wall patterns14blocated at the sides close to the first wiring pattern groups20A are connected each other at the right-and-left end portions (not shown) so as to form the closed loop shapes between the side wall patterns14bclose to the first wiring pattern groups20A. Further, ten (10) lines of the side wall patterns14blocated interiorly are connected each other so as to form the closed loop shape between the side wall patterns14b, starting from the side wall patterns14bclosest to the first wiring pattern groups20A, and so as to provide a symmetrical appearance. Further, ten (10) lines of the side wall patterns14blocated further interiorly form the closed loop shapes between the side wall patterns14badjacent to each other, and provide a symmetrical appearance.

After that, as shown inFIG. 13B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 13C, the wiring patterns11a,11bare formed.

FIGS. 14A to 14Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the eleventh embodiment.FIG. 14Acorresponds toFIG. 1D,FIG. 14Bcorresponds toFIG. 2B, andFIG. 14Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 14A, in the side wall patterns14bconstituting the second wiring pattern group20B of the eleventh embodiment, two (2) lines of the side wall patterns14blocated at the sides closest to the first wiring pattern groups20A are connected each other at the right-and-left end portions (not shown) so as to form a loop shape between the two side wall patterns14b, and the other side wall patterns14blocated interiorly form the loop shapes between the side wall patterns14badjacent to each other, and provide a symmetrical appearance.

After that, as shown inFIG. 14B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 14C, the wiring patterns11a,11bare formed.

FIGS. 15A to 15Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the twelfth embodiment.FIG. 15Acorresponds toFIG. 1D,FIG. 15Bcorresponds toFIG. 2B, andFIG. 15Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 15A, the side wall patterns14bconstituting the second wiring pattern group20B of the twelfth embodiment have a structure that a side wall pattern14bhaving a hexagonal shape in the center portion is added to the side wall patterns14bof the eleventh embodiment, and the other parts are formed similarly to those of the eleventh embodiment.

After that, as shown inFIG. 15B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 15C, the wiring patterns11a,11bsimilar to those of the eighth embodiment are formed.

FIGS. 16A to 16Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the thirteenth embodiment.FIG. 16Acorresponds toFIG. 1D,FIG. 16Bcorresponds toFIG. 2B, andFIG. 16Ccorresponds toFIG. 1H. Further, drawings corresponding toFIGS. 1A to 1Care omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 16A, in the side wall patterns14bconstituting the second wiring pattern group20B of the thirteenth embodiment, two (2) lines of the side wall patterns14blocated at the sides closest to the first wiring pattern groups20A are connected each other at the right-and-left end portions (not shown) so as to form a loop shape between the two side wall patterns14b. Further, twenty-four (24) lines of the side wall patterns14blocated interiorly form the loop shapes between the side wall patterns14b, from the parts located externally to the parts located internally in order, and provide a symmetrical appearance. Ten (10) lines of the side wall patterns14blocated further interiorly form the loop shapes between the side wall patterns14badjacent to each other, and provide a symmetrical appearance.

After that, as shown inFIG. 16B, a space “S” is formed on the cut region located at the end portions of the side wall patterns14b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the side wall patterns14bis cut by the lithography method, and as shown inFIG. 16C, the wiring patterns11a,11bsimilar to those of the seventh embodiment are formed.

Next, the fourteenth to the seventeenth embodiments where the semiconductor device of the second embodiment is applied to a phase-change memory will be explained. The fourteenth to the seventeenth embodiments show a case that the wiring patterns11a,11bconstituting each of wiring pattern groups20A,20B include thirty-three (33) lines of 20 nm in line width respectively.

FIGS. 17A to 17Hare main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the fourteenth embodiment.FIGS. 17A to 17Dcorrespond toFIGS. 3A to 3D,FIG. 17Ecorresponds toFIG. 3G, andFIG. 17Fcorresponds toFIG. 3H.FIG. 17Gcorresponds toFIG. 4B, andFIG. 17Hcorresponds toFIG. 4C.

Similarly to the second embodiment, as shown inFIG. 17A, after a mask material is formed on a foundation layer, core patterns13a,13bare formed on the mask material. The core patterns13bconstituting the second wiring pattern group20B are connected each other so as to form a closed loop shape between two core patterns13b, starting from the two side wall patterns14bclosest to the first wiring pattern groups20A.

Next, as shown inFIG. 17B, a slimming treatment of the core patterns13a,13bis carried out, and as shown inFIG. 17C, side wall patterns14a,14bare formed on the side surfaces of the core patterns13a,13bafter the slimming treatment, and as shown inFIG. 17D, the core patterns13a,13bare eliminate by an etching so as to leave the side wall patterns14a,14b.

Next, as shown inFIG. 17E, the mask material is eliminated by an etching and by using the side wall patterns14a,14bas a mask so as to form mask patterns, and the side wall patterns14a,14bare eliminated.

Next, as shown inFIG. 17E, the wiring material11is filled in the peripheral of the mask patterns12a,12b.

Next, as shown inFIG. 17F, the mask patterns12a,12bare eliminated so as to form wiring patterns11a,11b. The wiring patterns11a,11bform closed loop shapes. Wide patterns11e are formed between the wiring pattern groups20A.

Next, as shown inFIG. 17G, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 17H, the wiring patterns11a,11bare formed.

FIGS. 18A to 18Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to a fifteenth embodiment.FIG. 18Acorresponds toFIG. 3H.FIG. 18Bcorresponds toFIG. 4B, andFIG. 18Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted.

As shown inFIG. 18A, the wiring patterns11bconstituting the second wiring pattern group20B of the fifteenth embodiment are connected each other on alternate lines so as to form closed loop shapes between the wiring patterns11b, further, the wiring patterns11aof the wiring pattern groups20A closest to the first wiring pattern group20B are also connected each other so as to form a closed loop shape between the wiring patterns11a.

After that, as shown inFIG. 18B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 18C, the wiring patterns11a,11bare formed.

FIGS. 19A to 19Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the sixteenth embodiment.FIG. 19Acorresponds toFIG. 3H.FIG. 19Bcorresponds toFIG. 4B, andFIG. 19Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted.

As shown inFIG. 19A, the wiring patterns11bconstituting the second wiring pattern group20B of the sixteenth embodiment are connected each other on alternate lines so as to form closed loop shapes between the wiring patterns11b, further, the wiring patterns11aof the wiring pattern groups20A closest to the first wiring pattern group20B are also connected each other so as to form a closed loop shape between the wiring patterns11a.

After that, as shown inFIG. 19B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 19C, the wiring patterns11a,11bsimilar to those of the twelfth embodiment are formed.

FIGS. 20A to 20Care main part plan views schematically showing an example of a fabrication process according to a seventeenth embodiment

FIGS. 20A to 20Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the seventeenth embodiment.FIG. 20Acorresponds toFIG. 3H.FIG. 20Bcorresponds toFIG. 4B, andFIG. 20Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted.

As shown inFIG. 20A, in the wiring patterns11bconstituting the second wiring pattern group20B of the seventeenth embodiment, twenty-four (24) lines of the wiring patterns11blocated at the side close to the first wiring pattern group20A are connected each other so as to form a closed loop shape between two wiring patterns11b, starting from the two wiring patterns11bclosest to the first wiring pattern groups20A. Further, nine (9) lines of the wiring patterns11blocated interiorly are connected alternatively to the wiring patterns11bhaving a closed loop shape and located most interiorly. Furthermore, the wiring patterns11aof the wiring pattern groups20A closest to the first wiring pattern group20B are also connected each other so as to form a closed loop shape between the wiring patterns11a.

After that, as shown inFIG. 20B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 20C, the wiring patterns11a,11bare formed.

Next, the eighteenth to twenty-second the embodiments where the semiconductor device of the second embodiment is applied to a wiring by a line and space will be explained. The eighteenth to twenty-second embodiments show a case that the wiring patterns11a,11bconstituting each of wiring pattern groups20A,20B include thirty-six (36) lines of 20 nm in line width respectively.

FIGS. 21A to 21Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the eighteenth embodiment.FIG. 21Acorresponds toFIG. 4A,FIG. 21Bcorresponds toFIG. 4B, andFIG. 21Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 21A, in the wiring patterns11bconstituting the second wiring pattern group20B of the eighteenth embodiment, thirty-two (32) lines of the wiring patterns11bexcept for the lines centrally located are connected each other so as to form a closed loop shape between the wiring patterns11b, starting from the wiring patterns11bclosest to the first wiring pattern groups20A, and to provide a symmetrical appearance.

After that, as shown inFIG. 21B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 21C, the wiring patterns11a,11bare formed.

FIGS. 22A to 22Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the nineteenth embodiment.FIG. 22Acorresponds toFIG. 4A,FIG. 22Bcorresponds toFIG. 4B, andFIG. 22Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 22A, the wiring patterns11bconstituting the second wiring pattern group20B of the nineteenth embodiment are alternatively connected to the wide patterns11eformed in the center portion so as to form the closed loop shapes and to provide a symmetrical appearance. Further, the wiring patterns11aof the first wiring pattern groups20A closest to the second wiring pattern group20B include a part (a triangular shape) having a wide line width formed in the vicinity of the cut region where the closed loop cut is carried out.

After that, as shown inFIG. 22B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 22C, the wiring patterns11a,11bsimilar to those of the twelfth embodiment are formed.

FIGS. 23A to 24Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the twentieth embodiment.FIG. 23Acorresponds toFIG. 4A,FIG. 23Bcorresponds toFIG. 4B, andFIG. 23Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 23A, the wiring patterns11bconstituting the second wiring pattern group20B of the twentieth embodiment are alternatively connected to circular patterns formed in the periphery of the wide patterns11ecentrally located so as to form the closed loop shapes and to provide a symmetrical appearance. Further, the wiring patterns11aof the first wiring pattern groups20A closest to the second wiring pattern group20B include a part (a triangular shape) having a wide line width formed in the vicinity of the cut region where the closed loop cut is carried out.

After that, as shown inFIG. 23B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having a hexagonal shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 23C, the wiring patterns11a,11bare formed.

FIGS. 24A to 24Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to a twenty-first embodiment.FIG. 24Acorresponds toFIG. 4A,FIG. 24Bcorresponds toFIG. 4B, andFIG. 24Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 21A, in the wiring patterns11bconstituting the second wiring pattern group20B of the twenty-first embodiment, twenty-six (26) lines of the wiring patterns11blocated at the side close to the first wiring pattern group20A are connected each other so as to form a closed loop shape between two wiring patterns11b, starting from the two wiring patterns11bclosest to the first wiring pattern groups20A, and so as to provide a symmetrical appearance. Further, the ten (10) lines of the wiring patterns11blocated interiorly are alternatively connected to the wiring patterns11bhaving a closed loop shape and located interiorly, and provide a symmetrical appearance. Further, the wiring patterns11aof the first wiring pattern groups20A closest to the second wiring pattern group20B include a part (a triangular shape) having a wide line width formed in the vicinity of the cut region where the closed loop cut is carried out.

After that, as shown inFIG. 24B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 24C, the wiring patterns11a,11bare formed.

FIGS. 25A to 25Care main part plan views schematically showing each of upper wiring layers used in an example of a fabrication process according to the twenty-second embodiment.FIG. 25Acorresponds toFIG. 4A,FIG. 25Bcorresponds toFIG. 4B, andFIG. 25Ccorresponds toFIG. 4C. Further, drawings corresponding toFIGS. 3A to 3Gare omitted. Furthermore, the embodiment shows a case that the second wiring pattern groups20B exist in the right-and-left sides.

As shown inFIG. 25A, in the wiring patterns11bconstituting the second wiring pattern group20B of the twenty-second embodiment, twenty-two (22) lines of the wiring patterns11blocated at the side close to the first wiring pattern group20A form the closed loop shapes between the wiring patterns11bin the right-and-left end portions (not shown) Further, the four (4) lines of the wiring patterns11blocated interiorly are connected each other so as to form a closed loop shape between the wiring patterns11b, starting from the wiring patterns11bclosest to the first wiring pattern groups20A, and so as to provide a symmetrical appearance. Further, nine (9) lines of the wiring patterns11blocated further interiorly are alternatively connected to the closed loop shapes located interiorly so as to provide a symmetrical appearance. Further, the wiring patterns11aof the first wiring pattern groups20A closest to the second wiring pattern group20B include a part (a triangular shape) having a wide line width formed in the vicinity of the cut region where the closed loop cut is carried out.

After that, as shown inFIG. 25B, a space “S” is formed on the cut region located at the end portions of the wiring patterns11b, between the first wiring pattern group20A, the resist15having an octagon shape is formed, the cut region of the wiring patterns11bis cut by the lithography method, and as shown inFIG. 25C, the wiring patterns11a,11bare formed.

Further, it should be noted that the present invention is not intended to be limited to the above-mentioned embodiments, and the various kinds of changes thereof can be implemented by those skilled in the art without departing from the gist of the invention.