The present invention discloses a hysteresis comparator comprising an input stage, a hysteresis current generating circuit and an output stage. In the operation of the hysteresis comparator, the input stage is configured to receive a pair of differential input signals to generate at least one differential current signal; the hysteresis current generating circuit is configured to generate at least one hysteresis current to adjust the differential current signal to generate an adjusted differential current signal, wherein the hysteresis current generating circuit includes a common mode voltage detecting circuit for detecting a common mode voltage of the differential input signal for generating the hysteresis current; and the output stage is configured to generate an output signal according to the adjusted differential current signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a hysteresis comparator.

2. Description of the Prior Art

In conventional hysteresis comparators, the hysteresis voltage changes with the change of the common mode voltage of the input signal. To solve this issue, some related art techniques, such as U.S. Pat. Nos. 9,651,091, 8,310,279 and 9,654,091, have provided some associated solutions to keep the hysteresis voltage at a fixed value. However, to implement any of the aforementioned related art techniques requires additional circuit elements, thus increasing the manufacturing cost and raising the complexity in design.

SUMMARY OF THE INVENTION

In view of the above, an objective of the present invention is to provide a hysteresis comparator, which requires less circuit elements to achieve the goal of maintaining the hysteresis voltage at a fixed value, so as to solve the problems encountered in related art techniques.

An embodiment of the present invention discloses a hysteresis comparator, which comprises an input stage, a hysteresis current generating circuit and an output stage. The input stage is configured to receive a pair of differential input signals to generate at least one differential current signal. The hysteresis current generating circuit is configured to generate at least one hysteresis current to adjust the differential current signal to generate an adjusted differential current signal, wherein the hysteresis current generating circuit comprises a common mode voltage detecting circuit to detect a common mode voltage of the differential input signals for generating the hysteresis current. The output stage is configured to generate an output signal according to the adjusted differential current signal.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating a hysteresis comparator100according to an embodiment of the present invention. As shown inFIG. 1, the hysteresis comparator100comprises an input stage110, a hysteresis current generating circuit120and an output stage130, wherein the hysteresis current generating circuit120comprises a common mode voltage generate circuit122.

In the operation of the hysteresis comparator100, the input stage110receives a pair of differential input signals Vin and Vip to generate at least one pair of differential current signals In and Ip. Next, the hysteresis current generating circuit120generates at least one hysteresis current Ihy according to an output signal Vout of the hysteresis comparator100and the inverse signal VoutB of the output signal Vout, in order to adjust differential current signals In and Ip to generate adjusted differential current signals In′ and Ip′, wherein the common mode voltage detecting circuit122in the hysteresis current generating circuit120detects a common mode voltage of the differential input signals Vin and Vip for generating the hysteresis current Ihy. At last, the output stage130generates the output signal Vout according to the adjusted differential current signals In′ and Ip′. In this embodiment, the hysteresis current Ihy generated by the hysteresis current generating circuit120is generated based on the common mode voltage of the differential current signals In and Ip, so as to keep the ratio of the hysteresis current Ihy to the tail current of the input stage110at a fixed value to stabilize a hysteresis voltage of the hysteresis comparator100. More specifically, please refer toFIG. 2, which is a diagram illustrating the operations of the hysteresis comparator100. InFIG. 2, when the signal Vip gradually increases to exceeding Vin (e.g. increasing to the level of VTH), the output signal Vout will change to the high voltage from the low voltage (i.e. switching to logic 1 from logic 0. Further, when the signal Vip gradually drops below Vin (e.g. dropping to the level of VTL), the output signal Vout will change to the low voltage from the high voltage (i.e. changing to logic 0 from logic 1), wherein “ΔV” inFIG. 2represents the hysteresis voltage of the hysteresis comparator100, and “ΔV” is proportional to the ratio of the hysteresis current Ihy to the tail current in the input stage110. Hence, in this embodiment, since the ratio of the hysteresis current Ihy generated by the hysteresis current generating circuit120to the tail current in input stage110can be kept at a fixed value, the hysteresis voltage ΔV of the hysteresis comparator100can be thus stabilized.

FIG. 3is a diagram illustrating the detailed circuit architecture of the hysteresis comparator100according to an embodiment of the present invention. As shown inFIG. 3, the input stage110comprises two first N-type transistors N1and N2, two first P-type transistors P1and P2, a first current source CS1and a second current source CS2, wherein the sources of the first N-type transistors N1and N2are coupled to the first current source CS1, and the gates of the first N-type transistors N1and N2receive differential input signals Vin and Vip respectively in order to generate differential current signals In1and Ip1at the respective drains thereof, wherein the tail current Itail1shown in the figure is the summation of the current that respectively flow through the first N-type transistors N1and N2. The sources of the first P-type transistors P1and P2are coupled to the second current source CS2, and the gates of the first P-type transistors P1and P2receive the differential input signals Vin and Vip respectively, in order to generate the differential current signal In2, Ip2at the respective drains thereof, wherein the tail current Itail2shown in the figure is the summation of the current that flow through the first P-type transistors P1and P2. The common mode voltage detecting circuit122in the hysteresis current generating circuit120comprises two second N-type transistors N3, N4and two P-type transistors P3, P4, and the hysteresis current generating circuit120further comprises two third N-type transistors N5, N6, two third P-type transistors P5, P6, a third current source CS3and a fourth current source CS4, wherein the sources of the second N-type transistors N3, N4are coupled to the third current source CS3, and the gates of the second N-type transistors N3, N4respectively receive the differential input signals Vin and Vip in order to provide the hysteresis current Ihy1to the sources of the third N-type transistors N5, N6, so that the sources of the third N-type transistors N5, N6may receive the output signal Vout and the inverse signal VoutB thereof to generate the hysteresis currents Ihy1n, Ihy1p, to adjust the differential current signals In1and Ip1to generate adjusted differential current signals In1′, Ip1′. The sources of the second P-type transistors P3, P4are coupled to the fourth current source CS4, and the gates of the second P-type transistors P3, P4receive the differential input signals Vin and Vip respectively, in order to provide the hysteresis current Ihy2to the sources of the third P-type transistors P5, P6, for the sources of the third P-type transistors P5, P6to receive the output signal Vout and the inverse signal VoutB thereof in order to generate the hysteresis currents Ihy2n, Ihy2p, thereby adjusting the differential current signals In2, Ip2to generate the adjusted differential current signals In2′, Ip2′. The output stage130comprises the P-type transistors P7, P8, P9and P10and the N-type transistors N7, N8, N9and N10, and is used to receive the adjusted differential current signals In1′, Ip1′ and the adjusted differential current signals In2′, Ip2′ to generate the output signal Vout.FIG. 3further depicts another output stage that comprises the P-type transistors P11, P12, the N-type transistor N11, N12and an inverter302, for generating the inverse signal VoutB of the output signal Vout and another output signal Vout′, wherein the gate of the P-type transistor P11and the gate of the N-type transistor N11are coupled to the bias voltages Vb1, Vb2, respectively.

In the embodiment ofFIG. 3, the differential input signals Vin and Vip are received by the first N-type transistors N1and N2receive respectively, and are also received by the second N-type transistors N3, N4comprised in the common mode voltage detecting circuit122respectively. Hence, when the common mode voltage of the differential input signals Vin and Vip drops/rises, the tail current Itail1in the input stage110and the hysteresis current Ihy1(e.g. the summation of Ihy1nand Ihy1p) generated by the hysteresis current generating circuit120will also drop/rise, making the ratio of the tail current Itail1to the hysteresis current Ihy1remain at a fixed value. Similarly, the differential input signals Vin and Vip are received by the first P-type transistors P1and P2, and are also received by the second P-type transistors P3, P4comprised in the common mode voltage detecting circuit122. Therefore, when the common mode voltage of the differential input signals Vin and Vip drops/rises, the tail current Itail2in the input stage110and the hysteresis current Ihy2(e.g. the summation of Ihy2nand Ihy2p) generated by the hysteresis current generating circuit120will also drop/rise, making the ratio of the tail current Itail2to the hysteresis current Ihy2remain at a fixed value. As illustrated above, the hysteresis comparator100may have a stable hysteresis voltage ΔV.

The hysteresis comparator100shown inFIG. 3adopts the double-side hysteresis at the both sides. Other than that, the present invention also comprises the scenario shown inFIG. 4where the hysteresis comparator100adopts a single-side hysteresis (i.e. the hysteresis voltage ΔV may equal to VTH or VTL inFIG. 2). The difference between the embodiment ofFIG. 4andFIG. 3lies in that the drains of the third N-type transistor N5inFIG. 4is coupled to a reference voltage (e.g. the supplying voltage VDD), and thus does not provide the hysteresis current Ihy1nwhich is used for adjusting the current signal In1, and the drain of the third P-type transistor P6inFIG. 4is coupled to a reference voltage (e.g. a grounded voltage), and thus does not provide the hysteresis current Ihy2pfor adjusting the current signal Ip2. Since one skilled in the art is readily to understand the associated operations of the embodiment inFIG. 4after referring to the embodiment ofFIG. 3, the detailed descriptions are omitted here for brevity.

In the embodiments of the present invention, as long as the common mode voltage detecting circuit122is set in the hysteresis current generating circuit120of the hysteresis comparator100, a certain ratio of the hysteresis current to the tail current of the input stage110can be effectively maintained to stabilize the hysteresis voltage ΔV. In addition, in the present invention, the common mode voltage detecting circuit122is not set in the input stage110, which means the tail current in the input stage110will not be adjusted because of the common mode voltage detecting circuit122, and thus the common mode voltage detecting circuit122only requires very few circuit elements (such as the second N-type transistors N3, N4and the second P-type transistors P3, P4inFIG. 3) to achieve the goal of stabilizing the hysteresis voltage ΔV.