Predict computing platform memory power utilization

A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.

RELATED APPLICATIONS

This application is related to U.S. application Ser. No. 10/887,368, filed by Udayan Mukherjee and Aniruddha Kundu and entitled “On-line Diagnostic System and Method.”

BACKGROUND

Power consumption and cooling constraints are typical challenges faced in a computing platform operating environment. These challenges are magnified in a typical telecommunication network or datacenter where a multitude of computing platforms (e.g., in a rack, cabinet, etc.) are deployed. Constant pressure is exerted on service providers and datacenter administrators to reduce the total cost of ownership for these deployments and yet increase performance. This may lead to a higher density of processing elements on a computing platform and/or on a rack level to improve performance. Minimizing power consumption is an important goal for service providers and datacenter administrators to hold down the cost of energy bills and total cost of ownership.

DETAILED DESCRIPTION

As mentioned in the background, minimizing power consumption is an important goal to hold down the total cost of ownership. While there has been a particular focus on reducing power utilized by processing elements (e.g., central processing units (CPUs)), current and proposed memory technologies are becoming significant sources of power consumption. This presents a challenge in designing a high performance computing platform and holding down the total cost of ownership.

In one example, one or more statistical prediction models are implemented to predict memory power utilization and reduce power consumption for a computing platform. This implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform. The prediction is to be based on the determined configuration parameter and the monitored operating parameter. One or more memory modules resident on the computing platform are transitioned to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the one or more statistical prediction models.

FIG. 1is an illustration of elements of an example computing platform100. In one example, as depicted inFIG. 1, computing platform100includes memory power utilization (MPU) manager110, network interface120, processing elements130, memory controller140, memory power planes150and memory modules160. Although not shown inFIG. 1, computing platform100may also include other hardware, software, firmware or a combination of these elements and be a part of a computing device. This computing device may be a single blade computer in a chassis and/or rack, a server, a desktop computer, a laptop computer, a notebook computer, a digital broadband telephony device, a digital home network device (e.g., cable/satellite/set top box, etc.), a personal digital assistant (PDA), System on Chip (SOC) and the like.

In one example, as described more below, MPU manager110determines configuration parameters for computing platform100and monitors operating parameters to predict memory power utilization. Elements on computing platform100(e.g., MPU manager110, memory controller140) may cause memory power planes150to transition one or more memory modules from one power state to another power state (seeFIG. 5).

In one example, MPU manager110is coupled to other elements of computing platform100via one or more communication links. These communication links, for example, are depicted inFIG. 1as communication links112,114,116and118. As described more below, MPU manager110, for example, includes an appropriate interface to these other elements to determine configuration parameters, monitor operating parameters and cause memory modules to transition to another power state.

In one example, network interface120includes the interface via which computing platform100is coupled to a network via network link101, e.g., a wired or a wireless local area network (LAN/WLAN), a wide area network (WAN/WWAN), a metropolitan area network (MAN), a personal area network (PAN) and a cellular or a wireless broadband telephony network. Network interface120, for example, includes hardware, software or firmware to transmit and receive data to this network. This may include one or more network interface cards, fabric interface cards or other elements to receive and transmit data via network link101. In one example, communication link122may be used by network interface120elements to make memory read/write requests to memory controller140. These requests may send/retrieve data to/from memory modules160. Although not shown inFIG. 1, MPU manager110, for example, may also couple to communication link101and directly monitor network bandwidth.

In one example, processing elements130include the software, hardware, and/or firmware to support one more processing operations on computing platform100. This may include software such as operating systems and/or applications, hardware such as microprocessors, network processors, service processors, microcontrollers, field programmable gate arrays (FPGAs), application specific integrated circuit (ASICs) and firmware to include executable code to initiate basic input/output systems (BIOS) and/or initiate computing platform100elements for virtualization operations. In one example, communication link132may be used by processing elements130to make memory read/write requests to memory controller140.

In one example, memory controller140handles/completes requests for data to be stored (written) and retrieved (read) into one or more memory modules of memory modules160. For example, these requests may be received via communication links122or132. In one implementation, memory controller140may use memory power planes150to transition these one or more memory modules into various power states based on predicted memory power utilization that is determined, for example, by MPU manager110.

In one example, memory controller140may be integrated with processing element130. For example, memory controller140may serve as an integrated memory controller for a microprocessor. In this example, MPU manager110may communicate with memory controller140through an interface coupled to processing elements130(e.g., via communication link112) or through an interface coupled directly to an integrated memory controller140(e.g., via communication link132).

In one implementation, memory power planes150provide power to memory modules160via power feeds152. Power feeds152as shown inFIG. 1, for example, are routed to each memory module from among memory modules160. Power feeds152may provide power in various different voltage (v) levels, e.g., 0.9 v, 1.5 v, 1.8 v, 3.3 v, 5 v, etc. These voltage levels, for example, are regulated to provide power within a range of voltages.

In one example, memory modules160include a plurality of memory modules. These memory modules are depicted inFIG. 1as160-1through160-n+1, with n representing any positive integer. In one implementation, pairs of these memory modules couple to memory controller140through at least one memory channel (e.g., including data transmit and data receive communication links). An example of this coupling is depicted inFIG. 1and includes memory channels162,164and166. This disclosure is not limited to only a pair of modules per channel but may include any number of memory modules per channel and may also include any number of memory channels. Data to be written to or read from each pair of memory modules is routed through these memory channels, for example, via point-to-point serial communication links. As described more below, these memory modules may consist of various types of memory that can be placed into various power states or levels based on predicted memory power utilization for computing platform100.

FIG. 2provides a block diagram of an example MPU manager110architecture. InFIG. 2, MPU manager110's example architecture includes power optimization logic210, control logic220, memory230, input/output (I/O) interfaces240and optionally one or more applications250.

In one example, the elements portrayed in FIG.2's block diagram are those elements to support or enable MPU manager110as described in this disclosure, although a given MPU manager may include some, all or more elements than those depicted inFIG. 2. For example, power optimization logic210and control logic220may each or collectively represent a wide variety of logic device(s) or executable content to implement the features of MPU manager110. These logic device(s) may include a microprocessor, network processor, service processor, microcontroller, FPGA, ASIC, sequestered thread or core of a multi-core/multi-threaded microprocessor, special operating mode of a processor (e.g., system management mode) or combination thereof.

InFIG. 2, power optimization logic210includes configuration feature212, monitor feature214, predict feature216and transition feature218. In one implementation, power optimization logic210uses these features to perform several operations. These operations include, for example, determining a configuration parameter, monitoring an operating parameter and predicting memory power utilization for computing platform100based on the determined configuration parameter and the monitored operating parameter. These operations may also include causing one or more memory modules to transition to various power states based at least in part on the predicted memory power utilization for computing platform100.

Control logic220may control the overall operation of MPU manager110and as mentioned above, may represent any of a wide variety of logic device(s) or executable content to implement the control of MPU manager110. In alternate examples, the features and functionality of control logic220are implemented within power optimization logic210.

According to one example, memory230stores executable content. The executable content may be used by control logic220and/or power optimization logic210to implement or activate features or elements of MPU manager110. Memory230may also temporarily maintain configuration and operating parameters obtained by power optimization logic210's features to predict memory power utilization for computing platform100.

I/O interfaces240may provide an interface via a communication medium or link between MPU manager110and elements resident on computing platform100. As mentioned above forFIG. 1, MPU manager110may couple to these elements via communication links112,114,116and118. I/O interfaces240, for example, include interfaces that operate according to various communication protocols to communicate over these communication links. For example, I/O interfaces240operate according to a communication protocol that is described in a specification such as the System Management Bus (SMBus) Specification, version 2.0, published August 2000, and/or later versions. As described in more detail below, elements of computing platform100may provide information in memory registers or memory tables that are referred to in this disclosure as “hooks.” Features of power optimization logic210may use I/O interface240to access these hooks via communication links112,114,116and118.

I/O interfaces240may also provide an interface to elements located remotely to computing platform100. As a result, I/O interfaces240may enable power optimization logic210or control logic220to receive a series of instructions from these elements. The series of instructions may enable power optimization logic210and/or control logic220to implement one or more features of MPU manager110.

In one example, MPU manager110includes one or more applications250to provide internal instructions to control logic220and/or power optimization logic210.

FIG. 3is an illustration of elements of MPU manager110to implement an example statistical prediction module300. In one example, the elements of MPU manager110are features of power optimization logic210. As depicted inFIG. 3, these features include configuration feature212, monitor feature214and predict feature216.

In one implementation, configuration feature212, monitor feature214and predict feature216are part of a statistical prediction or heuristics module activated by power optimization logic210. In one example, configuration feature212obtains configuration parameters associated with elements resident on computing platform100. These configuration parameters include, for example, the resources present on computing platform100(e.g., processing elements, network interfaces, memory, software, firmware, etc.) and the configuration of those resources. For example, memory modules160are used in various configurations that may impact memory power utilization in different ways. These usage configurations, for example, are obtained from memory controller140and include, but are not limited to, memory interleaving, memory mirroring, memory sparing and rank order allocation. Configuration parameters may also include information for monitor feature214to determine what operating parameters are to be monitored and how to obtain them.

In one example, configuration feature212obtains information that monitor feature214uses to obtain operating parameters placed in hooks associated with or maintained by elements of computing platform100. In one example, these hooks are maintained in memory tables or memory registers and are depicted inFIG. 3as hooks320,330340and360for network interface120, processing elements130, memory controller140and memory power planes150, respectively.

As shown inFIG. 4, table400lists examples of categories and operating parameters associated with hooks320,330,340and350. In one example, at least a portion of the contents of table400are obtained by configuration feature212(e.g., during power-up of computing platform100) and made accessible to monitor feature214(e.g., temporarily stored in memory230). Monitor feature214may then monitor operating parameters for computing platform100by accessing memory registers or memory tables associated with the hooks (e.g., via communication links112,114,116or118). In one example, configuration feature212and monitor feature214provide configuration and operating parameters to predict feature216. Predict feature216, for example, implements various statistical prediction models including the use of statistical parameters in prediction algorithms that are based on computing platform100's configuration and operating parameters to predict memory power utilization for computing platform100.

In one example, transition feature218may receive predictions of memory power utilization for computing platform100from predict feature216. Transition feature218, for example, triggers or causes transition of one or more memory modules in memory modules160to other power states based on the predictions received from predict feature216.

In one example, as shown inFIG. 4, hook320includes a network traffic category. Hook320for example includes information associated with the amount and/or rate of data received and forwarded through network interface120. This may also include network traffic statistics (e.g., usage patterns, throughput, congestion, types of data traffic, etc.) for data (e.g., packet-based) that is received from and forwarded to a network coupled to computing platform100through network interface120.

Hook330, for example, contains several categories of information associated with processing element utilization, performance, power states and memory allocation. For example, the processing element may include a microprocessor and its utilization may be based on idle times, input/out times, system times, user times or number of processes running on the microprocessor. The microprocessor's performance may be based on cache misses, memory loads and store requests and the microprocessor's power state may also be a monitored operating parameter maintained in hook330. In one example, the microprocessor's power state includes suspend, standby and deep sleep (e.g., microprocessor is halted and no instructions are being executed).

The processing element may also include an operating system and the operating system's memory management. In one example, this may include physical page allocations that are maintained in hook330. De-allocations, for example, may be another operating parameter maintained in hook330.

Hook340, for example, contains memory access pattern information. This may include the number of reads and writes that memory controller140services or completes for computing platform100during a given time period. This may also include the number of commands pending and the number of scrubs that memory controller140performs in the given time period. The amount of mirroring (e.g., redundant memory read/write requests) that memory controller140handles/completes may also be included as an operating parameter maintained in hook340.

Hook350, for example, contains memory module power state information. This may include the power levels being provided to memory modules160by memory power planes150.

Additional hooks may also be maintained by various other elements of computing platform100. Thus, this disclosure is not limited to only the operating parameters associated with hooks320,330,340and350, as described above.

In one example, as mentioned above, predict feature216uses statistical parameters in one or more prediction algorithms. These statistical parameters, in one implementation, can be learned or determined starting or beginning at the time computing platform100is initially powered-up. Learned or determined statistical parameters may also be tuned automatically or periodically during computing platform100's runtime. In one example, the statistical parameters can also be learned for a given period of time (e.g., a training period) or configured for one or more types of computing platform100resources and/or utilization parameters.

In one implementation, statistical parameters allows predict feature216to anticipate the need to transition memory modules160to different power states to meet memory utilization needs. This anticipation, for example, may reduce possible memory latencies or reduction in data throughputs for computing platform100as one or more memory modules160are transitioned to these different power states. Power budget limits based on a power budge profile for computing platform100, for example, also may influence memory utilization needs. As a result, predict feature216may anticipate transition needs to meet a given power budget profile for computing platform100. These statistical parameters used by predict feature216may include, but are not limited to, memory requests made to a memory controller, processing element utilizations, network bandwidth and power budget profile.

In one example, network traffic information obtained from hook320can go into a statistical parameter to anticipate network bandwidth. Memory utilization, for example, varies based on network bandwidth as computing platform100may use memory modules160to at least temporarily store information to be received from or transmitted to a network. Thus, a statistical parameter used to predict memory utilization may be adjusted based on the network traffic information obtained from hook320at start-up, periodically or over a given period of time.

In one implementation, memory access patterns for computing platform100are obtained from hook340during an initial training period or while running applications. This may result in learned statistical parameters that indicate peak, busy traffic times or off-peak or low memory traffic times for computing platform100. These busy or low traffic Limes may be based on time of day, day of year and holidays taking into account various traffic models associated with the applications. The busy or low traffic times may also be based on a sliding time window or a standard probabilistic distribution function with mean and variance parameters. The appropriate busy or low traffic pattern is determined during the training period and can also be imported in the statistical model via determined configuration parameters. These busy or low traffic times may be used in a prediction algorithm (for single or multiple memory modules160) as shown in table 1 below:

TABLE 1If (current_time == busy_traffic_time)Monitor operating parameters to confirm busy traffic time.If (memory_access_pattern == busy_traffic)Power State unchanged.Else if (memory access pattern == low traffic or no traffic)Adjust statistical parameters to learn this instance of lowtraffic time;Power State unchanged.Else if (current_time == low_traffic_time or idle_time)Determine appropriate low power state of memory modulebased on idle window and probability of remaining idle or in lowtraffic time for some duration based on learned statisticalparameters;Transition memory module into low power state;Start the end duration timer for transitioning memory out oflow power state based on expected duration of low or idle traffictime;Continue monitoring the operating parameters (memorycapacity utilization, CPU utilization, network traffic, memoryaccess pattern) to proactively transition memory module back intoactive state before it's required.

In another implementation, network traffic information obtained from hook320and memory access patterns obtained from hook340result in learned statistical parameters that indicate busy or low traffic times may be used along with learned statistical parameters resulting from information obtained from hook330. These statistical parameters resulting from information obtained from hook330may indicate peak memory utilization for processing elements130(e.g., CPU memory utilizations). In one example, computing platform100's configuration parameters include the memory capacity of memory modules160and this memory capacity may be compared to peak memory utilization and busy or low traffic times in an example prediction algorithm as shown in table 2 below. The busy or low traffic times may be based on rules described above (e.g., time of day, day of year, holidays, sliding time window, probabilistic distribution function).

TABLE 2If (current_time == busy_traffic_time)Monitor operating parameters or hooks (330) to confirmbusy traffic time;If (memory_capacity_utilization == peak_memory)Power State unchanged.Else if (memory_capacity_utilization == low_traffic orno_traffic)Adjust statistical parameters to learn this instance oflow traffic time;Power State unchanged.Else if (current_time == low_traffic_time or idle_time)Determine appropriate low power state of memory modulebased on idle window and probability of remaining idle or in lowtraffic time for some duration based on learned statisticalparameters;Transition memory module into low power state;Start the end duration timer for transitioning memory out oflow power state based on expected duration of low or idle traffic;Continue monitoring the operating parameters (e.g.memory capacity utilization, CPU utilization, network bandwidth)to proactively transition memory module back into active statebefore it's required.

In another implementation, a power budget profile for computing platform100along with power consumed by computing platform100is used to determine a need to limit power consumed by computing platform100by transitioning memory modules160into lower power states. In this implementation, information in hooks330and340are obtained to gather or monitor operating parameters for power consumed by computing platform100. For example, CPU utilization obtained from hook330and memory bandwidth obtained from hook340may relate to power consumed on computing platform100. The power budge profile may be compared to this power consumption in an example prediction algorithm as shown in table 3 below.

TABLE 3If (power_consumed > power_budget_profile);If (CPU_utilization > peak_CPU_utilization)Check the memory utilization (330, 340);If (low_memory_traffic)Transition memory modules into low powerstate to reduce power consumed;OrThrottle memory bandwidth to reduce powerconsumed;Continue monitoring power consumed;Else if (CPU_utilization == low_traffic)Transition CPU to different power state to reducepower consumed.

FIG. 5is an illustration of example memory power states500that transition feature218may transition one or more memory modules from among memory modules160. As shown inFIG. 5, memory power states500include offline state510, online state520, standby state530and suspend state540.

In one implementation, memory modules of memory modules160may be dual inline memory modules (DIMMs). In this implementation, a DIMM includes a buffer (not shown) to temporarily hold data written to or read to the DIMM. The DIMM including the buffer, for example, is referred to as a fully buffered DIMM or FB-DIMM. An FB-DIMM, for example, may operate as described in a proposed FB-DIMM standard by the JEDEC Solid State Technical Association. According to the proposed FB-DIMM standard, the buffer part of an FB-DIMM is referred to as an advanced memory buffer (AMB).

In one example, an FB-DIMM AMB couples to memory controller140via a memory channel. In one configuration, for example, 2 FB-DIMMS couple to memory controller140via a single memory channel. For example, AMB's for memory modules160-1and160-2couple via memory channel162, AMB's for memory modules160-3and160-4couple via memory channel164and AMB's for memory modules160-nand160-n+1 couple via communication channel166(seeFIG. 1). In this configuration, for example, data to be written to or read to a DIMM is first routed to the AMB and then forwarded to its destination (e.g., memory controller140or a DIMM).

According to one example, for an FB-DIMM, offline state510represents a power state where the AMB and the DIMM are powered off. Online state520, for example, is when the DIMM and the AMB are fully powered. Standby state530, for example, is when the DIMM is in a lower power mode as compared to being fully powered (e.g., in a power-down mode) and the interface on the AMB that couples the DIMM to memory manager140is turned off (e.g., transmit and receive communication links disabled for a short, fixed duration of time or for an extended, variable duration of time). Suspend state540may represent a power state where the AMB is powered off and the DIMM is in a self-refresh mode.

In one implementation, as portrayed inFIG. 5, an FB-DIMM can be transitioned from offline state510to online state520. In an online state520, for example, the FB-DIMM can be transitioned into either suspend state540or standby state530. From standby state530or suspend state540, the FB-DIMM may transition to online state520. Also, if in Standby state530, the FB-DIMM may transition to suspend state540. Finally, if in suspend state540, the FB-DIMM may transition to offline state510or to standby state530. This disclosure is not limited to only these types of memory power state transitions and is also not limited to only FB-DIMM memory types. Other types of memory may include, but are not limited to, generations of double data rate (DDR) static dynamic random access memory such as DDR (first generation), DDR2 (second generation) or DDR3 (third generation). Other types of memory may also include future generations of FB-DIMM or other memory technologies.

FIG. 6is a flow chart of an example method to predict memory power utilization and transition a memory module to another power state based on the prediction. In one example, computing platform100, as depicted inFIG. 1, is used to describe this method. In block610, for example, computing platform100is powered-on or powered-up. This power-up may occur as power is initially provided to computing platform100, or incident to a reset of computing platform100.

In block620, in one example, upon power-up of computing platform100, power optimization logic210in MPU manager110activates configuration feature212. Configuration feature212, in one example, obtains one or more configuration parameters associated with elements resident on computing platform100. These configuration parameters may include the resources and the configuration of those resources for computing platform100. Configuration feature212, in one example, compiles at least a portion of these configuration parameters into a table and temporarily stores that table in a memory (e.g., memory230). Configuration feature212may also compile a table similar to table400to indicate the hooks via which operating parameters can be monitored. This table, for example, is at least temporarily stored in a memory (e.g., memory230).

In block630, in one example, power optimization logic210activates monitor feature214. Monitor feature214, in one implementation, obtains or accesses the tables temporarily stored by configuration feature212. Monitor feature214, for example, uses the hooks described in the table similar to table400to facilitate the monitoring of computing platform100's operation parameters. For example, monitor feature214uses hooks320,330340and360to obtain operating parameters associated with network interface120, processing elements130, memory controller140and memory modules160, respectively.

In block640, in one example, power optimization logic210activates predict feature216. Predict feature216, in one example, gathers configuration parameters and operating parameters obtained by configuration feature212and monitor feature214. As mentioned above, predict feature216implements various statistical prediction models around computing platform100's configuration and operating parameters to predict memory power utilization for computing platform100.

In one implementation, predict feature216's implementation of various statistical prediction models that include the configuration and operating parameters allows predict feature216to predict changes in memory utilization by various computing platform100elements. For example, memory in a given memory module of memory module160is either being allocated heavily or not at all by one or more entities of processing elements130(e.g., operating systems and/or applications). This may be indicated when monitor feature214periodically obtains hook330from processing elements130. Based at least in part on the information in hook330and computing platform100's configuration parameters and learned or trained statistical parameters, predict feature216may be able to predict the utilization of the given memory module and its power may be changed accordingly to reduce memory latencies or to meet a given power budget profile for computing platform100.

In addition to usage patterns, in one example, predict feature216may also account for various configuration parameters for memory modules160such as memory interleaving, memory mirroring, memory sparing and rank order allocation. This accounting may allow predict feature216to determine the prediction that may least impact the performance of computing platform100elements (e.g., processing elements130) when a given memory module or modules is transitioned to another power state.

In one implementation, memory modules160-1-160-n+1 are FB-DIMMs as described above forFIG. 5. In one example, memory modules160-1-160-n+1 have a configuration of 2 DIMMs per communication channel per branch, although this disclosure is not limited to this type of memory module configuration. If, for example, BIOS has enabled a branch sequential and rank interleaving 4:1 configuration, the ranks in a given branch participate in the branch memory region and even lower order memory address accesses go to the DIMMs on a given branch. Hence, predict feature216may account for this interleaving and consider a set of four DIMMs as a single memory resource group which can potentially be transitioned into the same power state (e.g., from among power states500). Similarly, predict feature216may account for other types of memory interleaving configurations and may also account for power and performance friendly memory configurations for end user applications implemented on computing platform100.

In block650, in one example, power optimization logic210activates transition feature218. Transition feature218, in one example, receives a prediction from predict feature216that a given memory module or modules of memory modules160will not be utilized based on its implementation of at least one statistical prediction model. For example, the given memory module is memory module160-1. Thus, for example, transition feature218causes memory module160-1to transition into another power state to save power for computing platform100. This other power state may be one of the power states500depicted inFIG. 5. For example, if module160-1was in online state520, transition feature218may cause memory module160-1to transition to offline state510, standby state530or suspend state540.

In one example, after module160-1is transitioned into another power state, successive predictions by predict feature216based on configuration and operating parameters may absorb possible reactivation/latency penalties that could degrade the performance of computing platform100. Thus, the process may return to block620and/or630to predict the use of memory module160-1and then cause module160-1to be transitioned to another power state based on that predicted use or usage pattern.

Referring again to MPU manager110inFIG. 1. MPU manager110, for example, is depicted as an element of computing platform100that is separate from Network interface120, processing elements130and memory controller140. In this example, MPU manager110may be part of or hosted on a dedicated management microcontroller such as a service processor.

In another example, MPU manager110resides within a grouping of computing platform100resources that includes memory controller140(e.g., a chipset). MPU manager110, in this other example, may be part of a dedicated management microcontroller within the chipset or may be included within or hosted on memory controller140. MPU manager110, for example, obtains configuration and operating parameters through the various communication links coupled to memory controller140.

In yet another example, MPU manager110is part of a virtual partition of computing platform100. This may be a service operating system running on a dedicated sequestered core or portion of a core that operates using virtualization technology/virtual machine monitor (VT/VMM) support in processing elements130. MPU manager110, for example, may use various communication links coupled to processing elements130and/or to the virtual partition where MPU manager110exists or is executing to obtain configuration and operating parameters.

Referring again to memory230inFIG. 2. Memory230may include a wide variety of memory media including but not limited to volatile memory, non-volatile memory, flash, programmable variables or states, random access memory (RAM), read-only memory (ROM), flash, or other static or dynamic storage media.

In one example, machine-readable instructions can be provided to memory230from a form of machine-accessible medium. A machine-accessible medium may represent any mechanism that provides (i.e., stores and/or transmits) information or content in a form readable by a machine (e.g., an ASIC, special function controller or processor, FPGA, or other hardware device). For example, a machine-accessible medium may include: ROM; RAM; magnetic disk storage media; optical storage media; flash memory devices; and the like.

In the previous descriptions, for the purpose of explanation, numerous specific details were set forth in order to provide an understanding of this disclosure. It will be apparent that the disclosure can be practiced without these specific details. In other instances, structures and devices were shown in block diagram form in order to avoid obscuring the disclosure.

References made in this disclosure to the term “responsive to” are not limited to responsiveness to only a particular feature and/or structure. A feature may also be “responsive to” another feature and/or structure and also be located within that feature and/or structure. Additionally, the term “responsive to” may also be synonymous with other terms such as “communicatively coupled to” or “operatively coupled to,” although the term is not limited in his regard.