Semiconductor device

A semiconductor device includes: an insulating substrate; a first semiconductor element connected to the insulating substrate; a conductive member disposed on the insulating substrate, and including a first opposing portion and a second opposing portion located opposite each other with respect to the first semiconductor element in plan view; a first wire connected to the first semiconductor element and the first opposing portion; and a second wire connected to the first semiconductor element and the second opposing portion, and located opposite the first wire with respect to a connection point where the first wire and the first semiconductor element are connected to each other in plan view.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to semiconductor devices.

Description of the Background Art

Recent miniaturization of semiconductor elements and reduction in surface area of a semiconductor element sometimes make it difficult to bond a sufficient number of wires onto a semiconductor element, resulting in an increase in current density per wire. Heat generation of a wire caused by the increase in current density might impair reliability of a semiconductor device. Various techniques for solving such a problem have been proposed. For example, Japanese Patent Application Laid-Open No. 2009-206140 proposes a technique of bonding twice the normal number of wires onto a semiconductor element by stitch-bonding a wire onto a bus bar, the semiconductor element, and the bus bar.

In the technique proposed by Japanese Patent Application Laid-Open No. 2009-206140, however, an insulating layer to which the bus bar is provided is spaced apart from the semiconductor element. With such a configuration, the insulating layer is required to have a relatively large size to prevent displacement of the bus bar from an upper portion of the insulating layer. This results in a problem in that miniaturization of semiconductor devices is difficult.

SUMMARY

The present disclosure has been conceived in view of a problem as described above, and it is an object to provide a technique allowing for miniaturization of semiconductor devices.

A semiconductor device according to the present disclosure includes: an insulating substrate; a first semiconductor element connected to the insulating substrate; a conductive member disposed on the insulating substrate, and including a first opposing portion and a second opposing portion located opposite each other with respect to the first semiconductor element in plan view and electrically connected to each other; a first wire connected to the first semiconductor element and the first opposing portion; and a second wire connected to the first semiconductor element and the second opposing portion, and located opposite the first wire with respect to a connection point where the first wire and the first semiconductor element are connected to each other in plan view.

The semiconductor device can be miniaturized.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments will be described below with reference the accompanying drawings. Features described in each of the embodiments below are examples, and all the features are not necessary features. In description made below, components similar in a plurality of embodiments bear the same or similar reference signs, and description is made mainly on a different component. In description made below, specific locations and directions indicated by “upper”, “lower”, “left”, “right”, “front”, “back”, and the like do not necessarily match directions in actual use.

Description will be made below based on the assumption that a semiconductor device according to Embodiment 1 is a semiconductor module.FIG.1is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to Embodiment 1.FIG.1illustrates the schematic configuration of the semiconductor device, and thus slightly differs fromFIG.2and subsequent drawings.

The semiconductor device inFIG.1includes a base plate11, a case12, a lid13, an external control terminal21, an external connection terminal22, an insulating substrate31, a plurality of circuit patterns32, a first semiconductor element33a, a control wire34, an emitter wire35, a connection wire36, and a sealing member37. As with the first semiconductor element33a, the semiconductor device includes a second semiconductor element33b, although the second semiconductor element33bis not illustrated inFIG.1.

The case12is disposed on the base plate11made of metal, such as copper, and surrounds a portion of the base plate11. The base plate11and the case12constitute a container body containing the first semiconductor element33aand the like in an internal space. The lid13blocks an opening of the case12to seal the internal space of the container body.

The external control terminal21and the external connection terminal22are each formed of a metal plate, for example. One end of the external control terminal21is located external to the case12, and is connected to the exterior (e.g., an external terminal) of the semiconductor device. The other end of the external control terminal21is located internal to the case12, that is, in the internal space of the container body, and is connected to a component internal to the semiconductor device. Similarly, one end of the external connection terminal22is located external to the case12, and the other end of the external connection terminal22is located internal to the case12.

The circuit patterns32made of metal are arranged on an upper surface and a lower surface of the insulating substrate31. A plurality of circuit patterns32spaced apart from one another are arranged on the upper surface of the insulating substrate31. The insulating substrate31is connected to the portion of the base plate11surrounded by the case12through a circuit pattern32on the lower surface of the insulating substrate31and solder38a.

The first semiconductor element33ais connected to the insulating substrate31through the circuit patterns32on the upper surface and solder38b. The first semiconductor element33ais a semiconductor switching element, such as an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET).

The control wire34connects a portion of the external control terminal21located in the internal space and a control electrode (e.g., gate electrode) disposed on the first semiconductor element33a. The emitter wire35connects a controlled electrode (e.g., an emitter electrode) disposed on the first semiconductor element33aand a circuit pattern32. The connection wire36connects the circuit pattern32to which the emitter wire35is connected and a portion of the external connection terminal22located in the internal space.

The sealing member37is a gel, for example, and seals the insulating substrate31, the plurality of circuit patterns32, the first semiconductor element33a, the control wire34, the emitter wire35, the connection wire36, and the like.

FIG.2is a plan view illustrating a configuration of the semiconductor device according to Embodiment 1, andFIG.3is a side view illustrating a configuration of the semiconductor device according to Embodiment 1. A portion of the configuration inFIG.1is illustrated in each ofFIGS.2and3.

The circuit patterns32on the upper surface of the insulating substrate31inFIG.1include a collector pattern32a, an emitter pattern32b, and a control pattern32cinFIG.2. For example, wet etching allowing for formation of a pattern having a width of approximately 1 mm is used to form the circuit patterns32including the collector pattern32a, the emitter pattern32b, and the control pattern32c.

The collector pattern32ais a circuit pattern32connected to the first semiconductor element33athrough the solder38b. As with the first semiconductor element33a, the second semiconductor element33bconnected to the collector pattern32athrough the solder38bis illustrated inFIG.2. The second semiconductor element33bis a diode, such as a PN junction diode (PND) and a Schottky barrier diode (SBD).

The emitter pattern32bis a conductive member including a first opposing portion32b1and a second opposing portion32b2. The first opposing portion32b1and the second opposing portion32b2are located opposite each other with respect to the first semiconductor element33ain plan view. The second opposing portion32b2is located directly opposite the first opposing portion32b1with respect to the first semiconductor element33ain the example ofFIG.2, but the location is not limited to this location as will be described below. The first opposing portion32b1and the second opposing portion32b2are electrically connected to each other, and have the same potential.

The control pattern32cis connected only to the control wire34between the external control terminal21and the first semiconductor element33a.

The emitter wire35inFIG.1includes a first emitter wire35aas a first wire and a second emitter wire35bas a second wire inFIG.2.

The first emitter wire35ais connected to the controlled electrode on the first semiconductor element33aand the first opposing portion32b1. The second emitter wire35bis connected to the controlled electrode on the first semiconductor element33aand the second opposing portion32b2.

As illustrated inFIG.2, the second emitter wire35bis located opposite the first emitter wire35awith respect to a connection point where the first emitter wire35aand the first semiconductor element33aare connected to each other in plan view. In Embodiment 1, a direction of extension of the first emitter wire35aand a direction of extension of the second emitter wire35bform a straight angle (an angle of 180°) in plan view. As will be described in Embodiment 7, however, the direction of extension of the first emitter wire35aand the direction of extension of the second emitter wire35bmay form an obtuse angle (an angle more than 90° and less than 180°) in plan view.

The first emitter wire35aand the second emitter wire35bare a single stitch-bonded wire in the example ofFIG.2, but the first emitter wire35aand the second emitter wire35bare not limited to the single stitch-bonded wire, and may be separated from each other.

As with the first semiconductor element33a, the second semiconductor element33bis connected to the first opposing portion32b1with the first emitter wire35a, and is connected to the second opposing portion32b2with the second emitter wire35b.

FIG.4is a circuit diagram corresponding to the configuration ofFIG.2. The diode as the second semiconductor element33bis connected in parallel with the semiconductor switching element as the first semiconductor element33a, and functions as a freewheeling diode.

Collector wiring41inFIG.4corresponds to the collector pattern32ainFIG.2. Emitter wiring42inFIG.4corresponds to the emitter pattern32b, the first emitter wire35a, and the second emitter wire35binFIG.2. Control wiring43inFIG.4corresponds to the control pattern32cand the control wire34inFIG.2.

Summary of Embodiment 1

According to the semiconductor device according to Embodiment 1 as described above, the second emitter wire35bis located opposite the first emitter wire35awith respect to the connection point where the first emitter wire35aand the first semiconductor element33aare connected to each other in plan view. According to such a configuration, a wire can be bonded to the emitter pattern32b, the first semiconductor element33a, and the emitter pattern32b, which are arranged substantially in a straight line, in the stated order. The wire can thus be bonded even when a sufficient number of wires cannot be bonded to the first semiconductor element33ain a normal case. The number of wires and heat generation of a wire can be maintained without increasing the size of the semiconductor device, so that reliability of wiring can be improved.

In Embodiment 1, the emitter pattern32bis disposed on the insulating substrate31to which the first semiconductor element33ais connected. This can reduce a space for insulation between the first semiconductor element33aand the emitter pattern32bin plan view, so that the semiconductor device can be miniaturized. Furthermore, the layout of the emitter pattern32bcan easily be changed, so that versatility in the manufacture of the semiconductor device can be increased.

The semiconductor device according to Embodiment 1 includes the control pattern32c, but may not include the control pattern32c. A degree of freedom of a design layout, however, can be increased by including the control pattern32c, so that further miniaturization of the semiconductor device can be expected. The semiconductor device according to Embodiment 1 includes the second semiconductor element33b, but may not include the second semiconductor element33b.

FIG.5is a plan view illustrating a configuration of a semiconductor device according to Embodiment 2, and corresponds toFIG.2.

As illustrated inFIG.5, the semiconductor device according to Embodiment 2 includes a plurality of first semiconductor elements33aand a plurality of second semiconductor elements33b, but does not include the control pattern32c.

Each of the plurality of first semiconductor elements33ais connected to the emitter pattern32bwith the first emitter wire35aand the second emitter wire35bas with the first semiconductor element33ain Embodiment 1. The plurality of first semiconductor elements33aare thereby connected in parallel with one another with a plurality of first emitter wires35a, a plurality of second emitter wires35b, and the emitter pattern32b, and thus can be driven in parallel with one another. Similarly, the plurality of second semiconductor elements33bare connected in parallel with one another with a plurality of first emitter wires35a, a plurality of second emitter wires35b, and the emitter pattern32b.

According to the semiconductor device according to Embodiment 2 as described above, the plurality of first semiconductor elements33acan be driven in parallel with one another, so that an increase in capacity of the semiconductor device can be expected.

FIGS.6and7are plan views each illustrating a configuration of a semiconductor device according to Embodiment 3, and correspond toFIG.2.

The configuration in Embodiment 3 is similar to the configuration in Embodiment 2 inFIG.5to which the control pattern32chas been added. The plurality of first semiconductor elements33amay be provided with respective control patterns32cas illustrated inFIG.6, or the plurality of first semiconductor elements33amay share a single control pattern32cas illustrated inFIG.7. According to such a configuration, the degree of freedom of the design layout can be increased more than that of the configuration in Embodiment 2, so that miniaturization of the semiconductor device can be expected.

When the control pattern32cis disposed at an end of another circuit pattern32, such as the collector pattern32a, as in Embodiment 3, the likelihood of the control wire34being electrically connected to the other circuit pattern32can be reduced.

FIG.8is a plan view illustrating a configuration of a semiconductor device according to Embodiment 4, and corresponds toFIG.2.FIG.9is a side view illustrating a configuration of the semiconductor device according to Embodiment 4, and corresponds toFIG.3.

As illustrated inFIG.9, the control wire34between control electrodes of the plurality of first semiconductor elements33ais stitch-bonded to the control electrodes in Embodiment 4. Thus, in Embodiment 4, the plurality of first semiconductor elements33aare not provided with respective control wires34, but provided with a single control wire34. The control wire34is only required to be stitch-bonded to one or more control electrodes. According to the semiconductor device according to Embodiment 4 as described above, wiring with the control wire34is easy.

As illustrated inFIG.8, the control wire34passes above between an end of the first emitter wire35aremote from the second emitter wire35band an end of the second emitter wire35bremote from the first emitter wire35ain Embodiment 4. According to such a configuration, wiring with the control wire34is easy. When the first emitter wire35aand the second emitter wire35bare separated from each other in contrast to the example ofFIG.8, the control wire34may pass above a portion between the first emitter wire35aand the second emitter wire35b.

FIG.10is a plan view illustrating a configuration of a semiconductor device according to Embodiment 5, and corresponds toFIG.2.

As illustrated inFIG.10, the second semiconductor element33bis connected to the first emitter wire35abetween the first semiconductor element33aand the first opposing portion32b1or to the second emitter wire35bbetween the first semiconductor element33aand the second opposing portion32b2in Embodiment 5.

According to the semiconductor device according to Embodiment 5 as described above, the first semiconductor element33aand the second semiconductor element33bshare the first emitter wire35aor the second emitter wire35b. The number of wires of the semiconductor device as a whole can thereby be reduced, so that miniaturization or an increase in capacity of the semiconductor device can be expected.

FIG.11is a plan view illustrating a configuration of a semiconductor device according to Embodiment 6, and corresponds toFIG.2.FIG.12is a side view illustrating a configuration of the semiconductor device according to Embodiment 6, and corresponds toFIG.3.

The conductive member according to each of Embodiments 1 to 5 is the emitter pattern32bincluding the first opposing portion32b1and the second opposing portion32b2. In contrast, the conductive member according to Embodiment 6 includes an emitter pattern32bnot including the first opposing portion32b1and the second opposing portion32b2, a first copper block32b3, and a second copper block32b4as illustrated inFIGS.11and12.

As illustrated inFIG.12, the first copper block32b3and the second copper block32b4respectively correspond to the first opposing portion32b1and the second opposing portion32b2, and are arranged on the emitter pattern32bthrough solder38c. When the first copper block32b3and the second copper block32b4cannot be supported only by the solder38c, an insulating member39may be disposed between the collector pattern32aand each of the first copper block32b3and the second copper block32b4as illustrated inFIG.12. As illustrated inFIG.13, a plurality of first copper blocks32b3and a plurality of second copper blocks32b4may be arranged.

According to the semiconductor device according to Embodiment 6 as described above, the emitter pattern32bnot including the first opposing portion32b1and the second opposing portion32b2can be used. This can reduce a space for insulation between the first semiconductor element33aand each of the first opposing portion32b1and the second opposing portion32b2in plan view, so that the semiconductor device can be miniaturized.

FIG.14is a plan view illustrating a configuration of a semiconductor device according to Embodiment 7, and corresponds toFIG.2.

In each of Embodiments 1 and 6, the second opposing portion32b2is located directly opposite the first opposing portion32b1with respect to the first semiconductor element33ain plan view. The direction of extension of the first emitter wire35aand the direction of extension of the second emitter wire35bform the straight angle in plan view.

In contrast, as illustrated inFIG.14, the second opposing portion32b2is offset from the location directly opposite the first opposing portion32b1with respect to the first semiconductor element33ain Embodiment 7. The direction of extension of the first emitter wire35aand the direction of extension of the second emitter wire35bform an obtuse angle, and an angle θ between them is more than 90° and less than 180°.

According to the semiconductor device according to Embodiment 7 as described above, the degree of freedom of the design layout can be increased without impairing reliability of wiring, so that miniaturization or an increase in capacity of the semiconductor device can be expected.

In Embodiment 8, at least one of the first semiconductor element33aand the second semiconductor element33bincludes a wide bandgap semiconductor. The wide bandgap semiconductor includes silicon carbide (SiC), gallium nitride (GaN), and diamond, for example. According to Embodiment 8 as described above, miniaturization and parallelization of the semiconductor device can be expected.

Embodiments and modifications can freely be combined with each other, and can be modified or omitted as appropriate.