ASYNCHRONOUS MEMORY ALLOCATION

Apparatuses, systems, and techniques to allocate processor memory. In at least one embodiment, an application programming interface is used to execute instructions to asynchronously allocate memory locations to processors.

FIELD

At least one embodiment pertains to processing resources used to execute one or more CUDA programs. For example, at least one embodiment pertains to processors or computing systems used to execute one or more CUDA programs that implement asynchronous allocation and deallocation of memory.

BACKGROUND

Stream-ordered computational operations have memory provided by an operating system. Providing memory for stream-ordered computational operations synchronously can introduce significant delays, reducing system performance and can cause memory fragmentation, increasing memory usage. An amount of memory, time, and computing resources used to perform stream-ordered and other computational operations can be improved.

DETAILED DESCRIPTION

FIG.1illustrates an example computer system100where memory is asynchronously allocated, in accordance with at least one embodiment. In at least one embodiment, a processor102may be connected to a graphics processor108. In at least one embodiment, processor102is a single-core processor. In at least one embodiment, processor102is a multi-core processor. In at least one embodiment, one or more additional processors, not shown, are connected to processor102. In at least one embodiment, processor102is an element of a processing system such as processing system2000described herein. In at least one embodiment, processor102is an element of a computer system such as computer system2100described herein. In at least one embodiment, processor102is an element of a system such as system2200described herein. In at least one embodiment, processor102is an element of a computing system such as computing system2400described herein. In at least one embodiment, processor102is an element of a compute unit such as compute unit4840described herein.

In at least one embodiment, system memory112is memory of computer system100that may be instantiated and/or stored on a computer system, such as computer system100, using systems and methods such as those described herein. In at least one embodiment, computer system100includes functionality to create a virtual address for system memory112that is asynchronously allocated memory that may be asynchronously allocated and/or deallocated using systems and methods such as those described herein. In at least one embodiment, computer system100uses a memory manager106to manage system memory112. In at least one embodiment, computer system100includes functionality to associate a virtual address with memory that may be provided to graphics processor memory104for use by graphics processor108.

In at least one embodiment, memory is allocated asynchronously by providing a virtual memory pointer to a calling process. In at least one embodiment, a virtual memory pointer is provided to a calling process when a calling process requests asynchronously allocated memory using systems and methods such as those described herein. In at least one embodiment, backing memory associated with a virtual memory pointer is provided at a later time such as, before a kernel is executed, using systems and methods such as those described herein. In at least one embodiment, memory that is allocated asynchronously is deallocated asynchronously, for example, after kernel execution completes, using systems and methods such as those described herein. In at least one embodiment, memory that is allocated asynchronously is deallocated asynchronously by returning memory to a memory pool and freeing a virtual memory pointer associated with deallocated memory using systems and methods such as those described herein.

In at least one embodiment, processor102comprises one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor102comprises one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously allocated to one or more processes executing on one or more processors, such as those described here. In at least one embodiment, processor102has included thereon instructions that, when executed, perform an API to cause a virtual memory address to be associated with asynchronously allocated memory locations. In at least one embodiment, processor102has included thereon instructions that, when executed, perform an API to cause physical memory to be allocated and associated with a virtual memory address. In at least one embodiment, instructions for processor102that, when executed, cause one or more memory locations to be asynchronously allocated to one or more processors, are stored in processor memory (not shown inFIG.1) associated with processor102. In at least one embodiment, instructions for processor102that, when executed, cause one or more memory locations to be asynchronously allocated to one or more processors, are stored in system memory112. In at least one embodiment, an API to asynchronously allocate memory is a driver API. In at least one embodiment, an API to asynchronously allocate memory is a runtime API.

In at least one embodiment, processor102comprises one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, processor102comprises one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously deallocated from one or more processes executing on one or more processors, such as those described here. In at least one embodiment, processor102has included thereon instructions that, when executed, perform an API to cause a virtual memory address to be associated with asynchronously deallocated memory locations. In at least one embodiment, processor102has included thereon instructions that, when executed, perform an API to cause physical memory to be deallocated and disassociated with a virtual memory address. In at least one embodiment, instructions for processor102that, when executed, cause one or more memory locations to be asynchronously deallocated from one or more processors, are stored in processor memory (not shown inFIG.1) associated with processor102. In at least one embodiment, instructions for processor102that, when executed, cause one or more memory locations to be asynchronously deallocated from one or more processors, are stored in system memory112. In at least one embodiment, an API to asynchronously deallocate memory is a driver API. In at least one embodiment, an API to asynchronously deallocate memory is a runtime API.

In at least one embodiment, processor102comprises one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously allocated to one or more processors and to be asynchronously deallocated from one or more processors. In at least one embodiment, processor102comprises one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously allocated to and to be asynchronously deallocated from one or more processes executing on one or more processors, such as those described here. In at least one embodiment, instructions for processor102that, when executed, cause one or more memory locations to be asynchronously allocated to one or more processors and to be asynchronously deallocated from one or more processors, are stored in processor memory (not shown inFIG.1) associated with processor102. In at least one embodiment, instructions for processor102that, when executed, cause one or more memory locations to be asynchronously allocated to one or more processors and to be asynchronously deallocated from one or more processors are stored in system memory112. In at least one embodiment, an API to asynchronously allocate and to asynchronously deallocate memory is a driver API. In at least one embodiment, an API to asynchronously allocate and to asynchronously deallocate memory is a runtime API.

In at least one embodiment, memory manager106executes one or more commands to create, destroy, copy, map, and/or unmap memory. In at least one embodiment, memory manager106executes one or more commands to create, destroy, copy, map, and/or unmap system memory112. In at least one embodiment, memory manager106executes one or more commands to create, destroy, copy, map, and/or unmap graphics processor memory104. In at least one embodiment, memory manager106is a software component that executes on processor102. In at least one embodiment, memory manager106is a software component that executes on another processor, not shown inFIG.1. In at least one embodiment, memory manager106is a software component that executes on a processor or processing unit associated with computer system100.

In at least one embodiment, memory manager106receives one or more commands from processor102perform operations on memory such as system memory112and/or graphics processor memory104. In at least one embodiment, processor102sends API commands to memory manager106that cause memory manager106perform operations on memory such as system memory112and/or graphics processor memory104. In at least one embodiment, processor102executes one or more commands that cause memory manager106to perform operations on memory. In at least one embodiment, memory manager106receives one or more commands from graphics processor108perform operations on memory. In at least one embodiment, graphics processor108sends API instructions to memory manager106that cause memory manager106perform operations on memory. In at least one embodiment, graphics processor108executes one or more commands that cause memory manager106to perform operations on memory.

In at least one embodiment, one or more memory pages of memory are associated with graphics processor108and usable by graphics processor108. In at least one embodiment, one or more pages of memory are provided by memory manager106to a processor such as processor102and/or to a graphics processor such as graphics processor108. In at least one embodiment, a processor such as processor102and/or to a graphics processor such as graphics processor108uses one or more pages of memory provided by memory manager106to store instructions, perform computations, store results of computations, store intermediate results, and/or other such memory operations. In at least one embodiment, graphics processor108is a single-core processor. In at least one embodiment, graphics processor108is a multi-core processor. In at least one embodiment, one or more additional processors are connected to memory associated with graphics processor108. In at least one embodiment, graphics processor108is an element of a processing system such as processing system2000described herein. In at least one embodiment, graphics processor108is an element of a computer system such as computer system2100described herein. In at least one embodiment, graphics processor108is an element of a system such as system2200described herein. In at least one embodiment, graphics processor108is an element of an integrated circuit such as integrated circuit2300described herein. In at least one embodiment, graphics processor108is an element of a computing system such as computing system2400described herein. In at least one embodiment, graphics processor108is a graphics processor such as graphics processor2810described herein. In at least one embodiment, graphics processor108is a graphics processor such as graphics processor2840described herein. In at least one embodiment, graphics processor108is a graphics processor such as graphics multiprocessor3034described herein. In at least one embodiment, graphics processor108is a graphics processor such as graphics processor3100described herein. In at least one embodiment, graphics processor108is a graphics processor such as graphics processor3308described herein. In at least one embodiment, graphics processor108is a GPU such as GPU4692described herein.

In at least one embodiment, a control thread114executing on processor102executes one or more commands to dispatch kernels such as, for example, kernel116and/or pending kernel120, to graphics processor108, as described herein. In at least one embodiment, control thread114executes one or more commands to manage kernels, as described herein. In at least one embodiment, control thread114executes one or more commands to manage kernels using a stream order (not illustrated inFIG.1) that indicates an order of operation for dispatching kernels to graphics processor108.

In at least one embodiment, an operating system110executing on processor102executes one or more commands to control a computer system such as computer system100. In at least one embodiment, control thread114executes one or more API calls to cause operating system110to control a computer system such as computer system100.

In at least one embodiment, processor102performs an API to cause memory manager106to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor102performs an API to cause memory manager106to cause one or more memory locations to be asynchronously deallocated from one or more processors.

In at least one embodiment, control thread114executing on processor102performs an API to cause memory manager106to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, control thread114executing on processor102performs an API to cause memory manager106to cause one or more memory locations to be asynchronously deallocated from one or more processors.

In at least one embodiment, operating system110executing on processor102performs an API to cause memory manager106to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, operating system110executing on processor102performs an API to cause memory manager106to cause one or more memory locations to be asynchronously deallocated from one or more processors.

In at least one embodiment, graphics processor memory104is used when performing an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, graphics processor memory104is used when performing an API to cause one or more memory locations to be asynchronously deallocated from one or more processors.

In at least one embodiment, system memory112is used when performing an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, system memory112is used when performing an API to cause one or more memory locations to be asynchronously deallocated from one or more processors.

In at least one embodiment, a kernel116is executing on graphics processor108. In at least one embodiment, kernel116is a compute kernel that is a set of instructions that are compiled, using systems and methods such as those described herein, so that they may be executed on a processor such as graphics processor108. In at least one embodiment, kernel116is a GPU kernel. In at least one embodiment, kernel116is a shader. In at least one embodiment, kernel116is a vertex shader. In at least one embodiment, kernel116is a pixel shader. In at least one embodiment, a set of instructions for kernel116is expressed using a shader programming language (such as OpenCL C, OpenGL, C++AMP, CUDA, Vulkan, etc.).

In at least one embodiment, kernel116has an associated asynchronously allocated memory location118. In at least one embodiment, asynchronously allocated memory location118associated with executing kernel116is created asynchronously by providing a virtual memory address to associate with kernel116as described herein (for example, when an asynchronous memory allocation API is called, a virtual memory address is returned). In at least one embodiment, asynchronously allocated memory location118associated with executing kernel116is created asynchronously by allocating memory to associate with a virtual memory address of kernel116and associating allocated memory with an associated virtual memory address. In at least one embodiment, not shown inFIG.1, asynchronously allocated memory location118may be later deallocated from kernel116when, for example, execution of kernel116terminates. In at least one embodiment, asynchronously allocated memory location118may be later deallocated from kernel116by first disassociating allocated memory from asynchronously allocated memory location118as described herein. In at least one embodiment, asynchronously allocated memory location118associated with executing kernel116is provided by memory manager106. In at least one embodiment, asynchronously allocated memory location118associated with executing kernel116is provided when control thread114requests a memory location from memory manager106, using systems and methods such as those described herein. In at least one embodiment, asynchronously allocated memory location118associated with executing kernel116is deallocated or released for reuse, as described herein, when control thread114sends a request to deallocate memory to memory manager106, using systems and methods such as those described herein.

In at least one embodiment, a pending kernel120is prepared for execution on graphics processor108, but is not yet executing. In at least one embodiment, pending kernel120has an asynchronously allocated memory location122with a virtual memory address. In at least one embodiment, because pending kernel120is not yet executing, allocated memory may not yet be associated with asynchronously allocated memory location122. In at least one embodiment, not shown inFIG.1, before pending kernel120begins execution, allocated memory may then be associated with asynchronously allocated memory location122(for example, before execution of pending kernel120begins). In at least one embodiment, not shown inFIG.1, asynchronously allocated memory location122may be later deallocated from pending kernel120when, for example, after execution of pending kernel120terminates. In at least one embodiment, asynchronously allocated memory location122may be later deallocated from pending kernel120by first disassociating allocated memory from asynchronously allocated memory location122as described herein.

FIG.2illustrates an example computer system200where memory is asynchronously allocated from a memory pool, in accordance with at least one embodiment. In at least one embodiment, a control thread204is executing on a processor202. In at least one embodiment, processor202is a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, control thread204is a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, control thread204performs an API to cause one or more memory locations to be asynchronously allocated to one or more processors.

In at least one embodiment, control thread204performs an API to asynchronously allocate memory206for a graphics processor kernel (for example, for graphics processor kernel one220). In an embodiment, control thread204performs an API to cause a memory manager208to asynchronously allocate memory206for a graphics processor kernel. In at least one embodiment, memory manager208is a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, control thread204performs an API to cause memory manager208to asynchronously allocate memory206by sending one or more commands to memory manager208. In at least one embodiment, not shown inFIG.2, control thread204performs an API to cause memory manager208to asynchronously allocate memory206by sending one or more commands to memory manager208via an operating system such as operating system110described herein at least in connection withFIG.1.

In at least one embodiment, in response to receiving one or more commands from control thread204, memory manager208creates a virtual memory pointer210using systems and methods such as those described herein. In at least one embodiment, memory manager208provides virtual memory pointer210to control thread204. In at least one embodiment, a virtual memory pointer224in memory pool218is provided to control thread204. In at least one embodiment, virtual memory pointer224in memory pool218is an address in memory that does not have corresponding backing memory in memory pool218. In at least one embodiment, virtual memory pointer224in memory pool218is an address in memory that will have corresponding backing memory in memory pool218when kernel one220begins execution.

In at least one embodiment, in response to receiving one or more commands from control thread204, memory manager208determines whether a memory pool218exists. In at least one embodiment, if memory manager208determines that memory pool218does not exist, memory manager208creates214memory pool218. In at least one embodiment, in response to receiving one or more commands from control thread204, memory manager208creates a virtual memory pointer210that corresponds to a memory location in memory pool218that will be available for use by kernel one220before kernel one220begins execution.

In at least one embodiment, control thread204causes kernel one to be launched212on graphics processor216. In at least one embodiment, graphics processor216is a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, control thread204launches kernel one after control thread204performs an API to cause a memory manager208to asynchronously allocate memory206for a graphics processor kernel. In at least one embodiment, control thread204launches kernel one after control thread204receives a virtual memory pointer210from memory manager208. In at least one embodiment, control thread204performs an API to launch a kernel, using systems and methods such as those described herein.

In at least one embodiment, after memory pool218exists, as described above, memory manager208provides backing memory222for kernel one220using systems and methods such as those described herein. In at least one embodiment, when memory manager208provides backing memory222for kernel one, virtual memory pointer224that corresponds to backing memory when memory manager208provides backing memory222for kernel one220becomes memory pointer226, that corresponds to backing memory in memory pool218. In at least one embodiment, virtual memory pointer224and memory pointer226are identical.

In at least one embodiment, control thread204performs an API to cause a memory manager208to deallocate memory from kernel one228. In at least one embodiment, control thread204performs an API to cause memory manager208to deallocate memory from kernel one228after control thread204launches kernel one. In at least one embodiment, in response to an API that causes memory manager208to deallocate memory from kernel one228, memory manager208causes memory226that corresponds to backing memory in memory pool218to be returned230to memory pool218, using systems and methods such as those described herein. In at least one embodiment, when control thread204performs an API to cause memory manager208to deallocate memory from kernel one228, memory226that is returned230to memory pool218is made available for use by other processes, such as those described herein. In at least one embodiment, memory associated with memory pool218is not returned to an operating system such as operating system110described herein at least in connection withFIG.1until all graphics processes terminate. In at least one embodiment, memory associated with memory pool218is returned to an operating system such as operating system110described herein at least in connection withFIG.1when a synchronization operation (not shown inFIG.2) is performed by an operating system, or performed by a control thread, or performed by a graphics processor.

In at least one embodiment, a stream execution order (not shown inFIG.2) of control thread204performs an API to cause a memory manager208to asynchronously allocate memory206for a graphics processor kernel, then launches212kernel one on graphics processor216, and then performs an API to cause a memory manager208to deallocate memory from kernel one228. In at least one embodiment, memory manager208executes commands to create virtual memory pointer210, provide a virtual memory pointer, create memory pool214, provide backing memory222, and/or to cause memory available to kernel one220to be returned230to memory pool218asynchronously, using systems and methods such as those described herein.

FIG.3illustrates an example computer system300where memory for a stream-ordered execution thread is asynchronously allocated from a memory pool, in accordance with at least one embodiment. In at least one embodiment, kernel one316is executing on graphics processor312and kernel one316has backing memory318as described herein at least in connection withFIG.2. In at least one embodiment, graphics processor312is a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, backing memory318is backing memory such as backing memory222described herein at least in connection withFIG.2.

In at least one embodiment, a control thread304executes on processor302. In at least one embodiment, processor302is a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, control thread304is a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, control thread304performs an API to cause memory for a stream-ordered execution thread to be asynchronously allocated from a memory pool.

In at least one embodiment, control thread304performs an API to asynchronously allocate memory306for a kernel (for example, graphics processor kernel two322) using systems and methods such as those described herein. In an embodiment, control thread304performs an API to cause a memory manager308to asynchronously allocate memory306for a kernel. In at least one embodiment, memory manager308is a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, control thread304performs an API to cause memory manager308to asynchronously allocate memory306by sending one or more commands to memory manager308. In at least one embodiment, not shown inFIG.3, control thread304performs an API to cause memory manager308to asynchronously allocate memory306by sending one or more commands to memory manager308via an operating system such as operating system110described herein at least in connection withFIG.1.

In at least one embodiment, in response to receiving one or more commands from control thread304, memory manager308creates a virtual memory pointer310using systems and methods such as those described herein. In at least one embodiment, memory manager308provides virtual memory pointer310to control thread304also using systems and methods such as those described herein.

In at least one embodiment, control thread304causes kernel two to be launched320on graphics processor312. In at least one embodiment, control thread304launches kernel two after control thread304performs an API to cause a memory manager308to asynchronously allocate memory306for kernel two. In at least one embodiment, control thread304launches kernel two after control thread304receives a virtual memory pointer310from memory manager308. In at least one embodiment, control thread304performs an API to launch kernel two, using systems and methods such as those described herein.

In at least one embodiment, before control thread304launches kernel two, memory manager308provides backing memory324for kernel two using systems and methods such as those described herein. In at least one embodiment, when memory manager308provides backing memory324for kernel two, virtual memory pointer326that corresponds to backing memory when memory manager308provides backing memory324for kernel two322, becomes memory328, that corresponds to backing memory in memory pool314. In at least one embodiment, virtual memory pointer326and a pointer to memory328are identical. In at least one embodiment, kernel two322is executing while kernel one316is executing and memory318available to kernel one316differs from memory328available to kernel two322. In at least one embodiment, for example, memory318available to kernel one316may have a different address in memory pool314than memory328available to kernel two322. In at least one embodiment, not shown inFIG.3, kernel two322is not executing while kernel one316is executing and memory328available to kernel two322is has a same address in memory pool314as memory318available to kernel one316. In at least one embodiment, for example, memory318available to kernel one316may be reused and may have an identical address in memory pool314as memory328available to kernel two322.

In at least one embodiment, control thread304performs an API to cause a memory manager308to deallocate memory from kernel two330. In at least one embodiment, control thread304performs an API to cause memory manager308to deallocate memory from kernel two330after control thread304launches kernel two. In at least one embodiment, in response to an API that causes memory manager308to deallocate memory from kernel two330, memory manager308causes memory328in memory pool314available to kernel two to be returned332to memory pool314, using systems and methods such as those described herein. In at least one embodiment, when control thread304performs an API to cause memory manager308to deallocate memory from kernel two330, memory328that is returned332to memory pool314is made available for use by other processes, as described herein. In at least one embodiment, a stream execution order (not shown inFIG.3) of control thread304performs an API to cause a memory manager308to asynchronously allocate memory306for a graphics processor kernel, then launches320kernel two on graphics processor312, and then performs an API to cause a memory manager308to deallocate memory from kernel two330. In at least one embodiment, memory manager308executes commands to create virtual memory pointer310, provide a virtual memory pointer, provide backing memory324, and/or to cause memory available to kernel two322to be returned332to memory pool314asynchronously, using systems and methods such as those described herein.

FIG.4illustrates an example computer system400where memory for a stream-ordered execution thread is asynchronously deallocated and returned to a memory pool, in accordance with at least one embodiment. In at least one embodiment, kernel one406is executing on graphics processor416. In at least one embodiment, graphics processor416is a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, kernel one406has backing memory420in memory pool418, provided using systems and methods such as those described herein.

In at least one embodiment, a control thread404executing on processor402performs an API to asynchronously deallocate408memory for kernel one406using systems and methods such as those described herein. In at least one embodiment, when control thread404performs an API to cause memory manager412to deallocate408memory from kernel one406, memory420that is returned414to memory pool418is made available for use by other processes, such as those described herein. In at least one embodiment, control thread404is a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, processor402is a processor such as processor102described herein at least in connection withFIG.1.

In at least one embodiment, when control thread404performs an API to asynchronously deallocate memory408for kernel one406, a memory manager412asynchronously returns memory414to a memory pool418using systems and methods such as those described herein. In at least one embodiment, memory manager412is a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, memory pool418is a memory pool such as memory pool218described herein at least in connection withFIG.2. In at least one embodiment, control thread404performs an API to cause memory manager412to asynchronously deallocate memory408for kernel one406by sending one or more commands to memory manager412. In at least one embodiment, not shown inFIG.4, control thread404performs an API to cause memory manager412to asynchronously deallocate memory by sending one or more commands to memory manager412via an operating system such as operating system110described herein at least in connection withFIG.1.

In at least one embodiment, in response to receiving one or more commands from control thread404, memory manager412executes commands to return memory414to a memory pool418using systems and methods such as those described herein. In at least one embodiment, when memory manager412executes commands to return memory414to a memory pool418, memory420that was previously associated with memory in memory pool418for kernel one406becomes memory426that is no longer associated with memory in memory pool418.

In at least one embodiment, control thread404performs an API to asynchronously allocate memory410for kernel two422at some point after control thread404performs an API to asynchronously deallocate memory408for kernel one406. In at least one embodiment, when control thread404performs an API to asynchronously allocate memory410for kernel two422, memory manager412provides backing memory for kernel two428, as described herein. In at least one embodiment, memory426that is no longer associated with memory in memory pool418for kernel one406may be available to kernel two422using a virtual memory address, as described herein when memory manager412provides backing memory for kernel two428. In at least one embodiment, a virtual address associated with memory426that is no longer associated with memory in memory pool418for kernel one406may be reused to become memory424available to kernel two422, using systems and methods such as those described herein.

FIG.5illustrates an example process500for performing operations to asynchronously allocate memory, in accordance with at least one embodiment. In at least one embodiment, a processor such as processor102described herein at least in connection withFIG.1executes instructions to perform example process500illustrated inFIG.5.

In at least one embodiment, at step502of example process500, a request is generated for asynchronously allocated memory. In at least one embodiment, a generated request for asynchronously allocated memory is sent to a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, a request for asynchronously allocated memory is sent using an API. In at least one embodiment, a request for asynchronously allocated memory is a command. In at least one embodiment, a request for asynchronously allocated memory is an executable command. In at least one embodiment, a request for asynchronously allocated memory is an instruction. In at least one embodiment, a request for asynchronously allocated memory is an executable instruction. In at least one embodiment, a request for asynchronously allocated memory is sent using an API that indicates a location used to return an asynchronously allocated memory address, a size of memory requested, and an execution stream that at least indicates a stream order. In at least one embodiment, a request for asynchronously allocated memory is sent using an API that indicates a memory pool from which asynchronously allocated memory may be allocated. In at least one embodiment, not illustrated inFIG.5, a response to a request for asynchronously allocated memory is received. In at least one embodiment a response to a request for asynchronously allocated memory is received from a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, a response to a request for asynchronously allocated memory is received using an API. In at least one embodiment, a response to a request for asynchronously allocated memory is received using an API that indicates an error result. In at least one embodiment, after step502, execution of example process500advances to step504.

In at least one embodiment, at step504of example process500, a virtual memory address is received. In at least one embodiment, a virtual memory address is a a pointer to an address in virtual memory. In at least one embodiment, a virtual memory pointer is received in response to a request for asynchronously allocated memory as described in connection with step502. In at least one embodiment, a virtual memory address is received from a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, a virtual memory address is received using an API. In at least one embodiment, a virtual memory address is received using an API that indicates a location to store a virtual memory address. In at least one embodiment, not illustrated inFIG.5, a response to receiving a virtual memory address is generated. In at least one embodiment, a response to receiving a virtual memory address is generated using an API. In at least one embodiment, after step504, execution of example process500advances to step506.

In at least one embodiment, at step506of example process500, a request to execute a kernel using a provided virtual memory address such as a virtual memory address returned in step504is generated. In at least one embodiment, a request to execute a kernel is sent to a memory manager such as memory manager106described herein at least in connection withFIG.1using systems and methods such as those described in connection with step502. In at least one embodiment, a request to execute a kernel is sent to a graphics processor such as graphics processor108described herein at least in connection withFIG.1using systems and methods such as those described in connection with step502. In at least one embodiment, a request to execute a kernel is sent by inserting a request to execute a kernel in an execution queue of, for example, a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, not illustrated inFIG.5, a request to execute a kernel is sent to a graphics processor using a memory manager. In at least one embodiment, also not illustrated inFIG.5, a request to execute a kernel generates a request to allocate memory, using systems and methods such as those described herein. In at least one embodiment, for example, a request to execute a kernel generates a request to allocate memory automatically. In at least one embodiment, a request to allocate memory associated with a request to execute a kernel is sent using systems and methods such as those described herein in connection with502. In at least one embodiment, after step506, execution of example process500advances to step508.

In at least one embodiment, at step508of example process500, a request to deallocate asynchronously allocated memory is generated. In at least one embodiment, a generated request to deallocate asynchronously allocated memory is sent to a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, a request to deallocate asynchronously allocated memory is sent using an API. In at least one embodiment, a request generated to deallocate asynchronously allocated memory is a command. In at least one embodiment, a request generated to deallocate asynchronously allocated memory is an executable command. In at least one embodiment, a request generated to deallocate asynchronously allocated memory is an instruction. In at least one embodiment, a request generated to deallocate asynchronously allocated memory is an executable instruction. In at least one embodiment, a request to deallocate asynchronously allocated memory is sent using an API that indicates a location of previously asynchronously allocated memory address and an execution stream that at least indicates a stream order. In at least one embodiment, a request for asynchronously allocated memory is sent using an API that indicates a memory pool associated with asynchronously allocated memory. In at least one embodiment, not illustrated inFIG.5, a response to a generated request for asynchronously allocated memory is received. In at least one embodiment a response to a request to deallocate asynchronously allocated memory is received from a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, a response to a request to deallocate asynchronously allocated memory is received using an API. In at least one embodiment, a response to a request to deallocate asynchronously allocated memory is received using an API that indicates an error result. In at least one embodiment, after step508, example process500terminates. In at least one embodiment, after step508, example process500returns to step502to generate a new request for asynchronously allocated memory.

In at least one embodiment, operations of example process500illustrated inFIG.5are performed in a different order than indicated inFIG.5. In at least one embodiment, operations of example process500illustrated inFIG.5are performed simultaneously and/or in parallel. In at least one embodiment, operations of example process500illustrated inFIG.5are performed by a plurality of threads executing on a processor such as processor102described herein at least in connection withFIG.1.

FIG.6illustrates an example process600for performing operations to asynchronously allocate memory, in accordance with at least one embodiment. In at least one embodiment, a processor such as processor102described herein at least in connection withFIG.1executes instructions to perform example process600illustrated inFIG.6.

In at least one embodiment, at step602of example process600, a request is received to asynchronously allocate memory. In at least one embodiment, a received request to asynchronously allocate memory is received from a control thread. In at least one embodiment, a received request to asynchronously allocate memory is received from a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, a received request to asynchronously allocate memory is received from a control thread executing a process such as example process500illustrated inFIG.5. In at least one embodiment, a received request to asynchronously allocate memory is received from a control thread executing step502of example process500as described herein at least in connection withFIG.5. In at least one embodiment, a received request to asynchronously allocate memory is sent using an API. In at least one embodiment, a received request to asynchronously allocate memory is a command. In at least one embodiment, a received request to asynchronously allocate memory is an executable command. In at least one embodiment, a received request to asynchronously allocate memory is an instruction. In at least one embodiment, a received request to asynchronously allocate memory is an executable instruction. In at least one embodiment, a received request to asynchronously allocate memory is sent using an API as described herein at least in connection withFIG.5. In at least one embodiment, not illustrated inFIG.6, a response to a received request to asynchronously allocate memory is generated. In at least one embodiment a response to a received request to asynchronously allocate memory is sent to a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, a response to a received request to asynchronously allocate memory is sent using an API. In at least one embodiment, a response to a received request to asynchronously allocate memory is sent using an API that indicates an error result. In at least one embodiment, after step602, execution of example process600advances to step604.

In at least one embodiment, at step604of example process600, it is determined whether a memory pool exists that may be used to provide asynchronously allocated memory, using systems and methods such as those described herein. In at least one embodiment, at step604, if it is determined that a memory pool exists (“YES” branch), execution of example process600advances to step608. In at least one embodiment, at step604, if it is determined that a memory pool does not exist (“NO” branch), execution of example process600advances to step606.

In at least one embodiment, at step606of example process600, memory for a new memory pool is allocated. In at least one embodiment, after step606, execution of example process600advances to step608.

In at least one embodiment, at step608of example process600, a memory manager determines when memory will be needed for a request for asynchronously allocated memory. In at least one embodiment, a memory manager may determine when memory will be needed for a request for asynchronously allocated memory based at least in part on one or more other memory requests. In at least one embodiment, for example, if associated work such as, for example, a kernel is executing but will be done executing before memory will be needed for a request for asynchronously allocated memory, such memory may be used to fulfill a request for asynchronously allocated memory, using systems and methods such as those described herein. In at least one embodiment, after step608, execution of example process600advances to step610.

In at least one embodiment, at step610of example process600, it is determined whether a sufficiently sized memory pool exists. In at least one embodiment, if it is determined that a sufficiently sized memory pool exists (“YES” branch), execution of example process advances to step614. In at least one embodiment, if it is determined that a sufficiently sized memory pool does not exist (“NO” branch), execution of example process advances to step612. In at least one embodiment, not illustrated inFIG.6, step604and step610may be combined so that, for example, a memory manager simultaneously determines whether a sufficiently sized memory pool exists and, if not, allocates new and/or additional memory for a memory pool. In at least one embodiment, for example, memory for a new memory pool is allocated when there is not an existing memory pool and additional memory for a memory pool is allocated when there is an existing memory pool, but it is determined that an amount of memory in an existing memory pool is not sufficient to provide asynchronously allocated memory for a memory request.

In at least one embodiment, at step612of example process600, additional memory for an existing memory pool is allocated using systems and methods such as those described herein. In at least one embodiment, after step612, execution of example process600advances to step614.

In at least one embodiment, at step614of example process600, a memory manager generates a virtual memory pointer that corresponds to memory that will be used for a request for asynchronously when needed. In at least one embodiment, a memory manager returns a virtual memory pointer to a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, memory manager returns a virtual memory pointer to a control thread executing a process such as example process500illustrated inFIG.5. In at least one embodiment, memory manager returns a virtual memory pointer to a control thread performing step504of example process500described herein at least in connection withFIG.5. In at least one embodiment, after step614, execution of example process600advances to step616.

In at least one embodiment, at step616of example process600, a memory manager waits for a next request. In at least one embodiment, after step616, example process600continues at step502of example process500to wait for a next request. In at least one embodiment, after step616, example process600continues at step602to receive a new request to asynchronously allocate memory. In at least one embodiment, after step616, example process600continues at step702of example process700, described herein at least in connection withFIG.7, to receive a request to asynchronously deallocate memory. In at least one embodiment, after step616, example process600terminates.

In at least one embodiment, operations of example process600illustrated inFIG.6are performed in a different order than indicated inFIG.6. In at least one embodiment, operations of example process600illustrated inFIG.6are performed simultaneously and/or in parallel. In at least one embodiment, operations of example process600illustrated inFIG.6are performed by a plurality of threads executing on a processor such as processor102described herein at least in connection withFIG.1.

FIG.7illustrates an example process700for performing memory management operations to asynchronously deallocate memory, in accordance with at least one embodiment. In at least one embodiment, a memory manager such as memory manager106described herein at least in connection withFIG.1executes instructions to perform example process700illustrated inFIG.7.

In at least one embodiment, at step702of example process700, a request is received to asynchronously deallocate memory. In at least one embodiment, a received request to asynchronously deallocate memory is received from a control thread. In at least one embodiment, a received request to asynchronously deallocate memory is received from a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, a received request to asynchronously deallocate memory is received from a control thread executing a process such as example process500illustrated inFIG.5. In at least one embodiment, a received request to asynchronously deallocate memory is received from a control thread executing step508of example process500as described herein at least in connection withFIG.5. In at least one embodiment, a received request to asynchronously deallocate memory is sent using an API. In at least one embodiment, a received request to asynchronously deallocate memory is a command. In at least one embodiment, a received request to asynchronously deallocate memory is an executable command. In at least one embodiment, a received request to asynchronously deallocate memory is an instruction. In at least one embodiment, a received request to asynchronously deallocate memory is an executable instruction. In at least one embodiment, a received request to asynchronously deallocate memory is sent using an API as described herein at least in connection withFIG.5. In at least one embodiment, not illustrated inFIG.5, a response to a received request to asynchronously deallocate memory is generated. In at least one embodiment a response to a received request to asynchronously deallocate memory is sent to a control thread such as control thread114described herein at least in connection withFIG.1. In at least one embodiment, a response to a received request to asynchronously deallocate memory is sent using an API. In at least one embodiment, a response to a received request to asynchronously deallocate memory is sent using an API that indicates an error result. In at least one embodiment, after step702, execution of example process700advances to step704.

In at least one embodiment, at step704of example process700, a memory manager determines when asynchronously allocated memory will become available for reuse using systems and methods such as those described herein. In at least one embodiment, after step704, execution of example process700advances to step706.

In at least one embodiment, at step706of example process700, if it is determined, in step704, that asynchronously allocated memory is available for reuse (“YES” branch), execution of example process700advances to step708. In at least one embodiment, at step706, if it is determined, in step704, that asynchronously allocated memory is not yet available for reuse (“NO” branch), execution of example process700continues at step704, to wait for asynchronously allocated memory to become available for reuse. In at least one embodiment, not illustrated inFIG.7, a memory manager may perform other actions while waiting for asynchronously allocated memory to become available for reuse.

In at least one embodiment, at step708of example process700, a memory manager returns asynchronously allocated memory to a memory pool, using systems and methods such as those described herein. In at least one embodiment, after step708, execution of example process700advances to step710.

In at least one embodiment, at step710of example process700, a memory manager may perform one or more operations to mark asynchronously allocated memory as available for reuse. In at least one embodiment, after step710, execution of example process700advances to step712.

In at least one embodiment, at step712of example process700, a memory manager waits for a next request. In at least one embodiment, after step712, example process700continues at step502of example process500to wait for a next request. In at least one embodiment, after step712, example process700continues at step602of example process600to receive a new request to asynchronously allocate memory. In at least one embodiment, after step712, example process700continues at step702to receive a request to asynchronously deallocate memory. In at least one embodiment, after step712, example process700terminates.

In at least one embodiment, operations of example process700illustrated inFIG.7are performed in a different order than indicated inFIG.7. In at least one embodiment, operations of example process700illustrated inFIG.7are performed simultaneously and/or in parallel. In at least one embodiment, operations of example process700illustrated inFIG.7are performed by a plurality of threads executing on a memory manager such as memory manager106described herein at least in connection withFIG.1.

FIG.8illustrates an example data flow800where memory is allocated synchronously, in accordance with at least one embodiment. In at least one embodiment, a processor802performs operations to request memory804from a memory manager806. In at least one embodiment, processor802is a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, memory manager806is a memory manager such as memory manager106described herein at least in connection withFIG.1.

In at least one embodiment, memory manager806allocates memory808and, as example data flow800is not asynchronous, processor802waits810until memory manager806completes allocating memory808. In at least one embodiment, memory manager806then launches812kernel one on graphics processor814. In at least one embodiment, graphics processor814is a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, as example data flow800is not asynchronous, processor802may then wait818while kernel one is executing816on graphics processor814. In at least one embodiment, not shown inFIG.8, processor802may perform other actions while kernel one is executing816on graphics processor814.

In at least one embodiment, after kernel one is done executing, processor802can then release memory820by causing memory manager806to free memory822. In at least one embodiment, memory in graphics processor memory826is allocated828from a time when memory manager806allocates memory808until a time when memory manager806frees memory822. In at least one embodiment, graphics processor memory826is graphics processor memory such as graphics processor memory104described herein at least in connection withFIG.1. In at least one embodiment, memory manager806may clear memory824before it may be reused. In at least one embodiment, as example data flow800is not asynchronous, processor802may wait830until after memory manager806clears memory824before processor802can reuse memory832.

FIG.9illustrates an example first part of a data flow900where memory is asynchronously allocated and deallocated, in accordance with at least one embodiment. In at least one embodiment, a processor902requests memory904from a memory manager906. In at least one embodiment, processor902is a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, memory manager906is a memory manager such as memory manager106described herein at least in connection withFIG.1. In at least one embodiment, memory manager906may first determine whether a memory pool is available to use. In at least one embodiment, if a memory pool is not available to use, a memory manager906allocates a memory pool908to create a graphics processor memory pool912. In at least one embodiment, graphics processor memory pool912is identical to memory pool218described herein at least in connection withFIG.2.

In at least one embodiment, after a graphics processor memory pool912is available to use to allocate backing memory, a memory manager906determines a memory location910in graphics processor memory pool912using systems and methods such as those described herein. In at least one embodiment, memory manager906returns a virtual memory pointer916to processor902, as described herein. In at least one embodiment, memory manager906returns virtual memory pointer916to processor902asynchronously in that, as described herein, a virtual memory pointer is returned to a processor in response to a memory request, before backing memory is used by an execution stream.

In at least one embodiment, processor902executes a command to launch kernel one918with a provided virtual memory pointer. In at least one embodiment, a graphics processor924executes kernel one926. In at least one embodiment, graphics processor924is a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, when memory manager906determines a memory location910in graphics processor memory pool912, memory is reserved for use914. In at least one embodiment, memory is reserved for use914so that memory will be available for use by kernel one when graphics processor924executes kernel one926.

In at least one embodiment, processor902executes a command to free memory920associated with kernel one. In at least one embodiment, when kernel one completes, memory manager906releases backing memory930for later reuse, as described herein. In at least one embodiment, memory manager906releases backing memory930by returning backing memory to a memory pool. In at least one embodiment, memory manager906releases backing memory930by returning backing memory to a memory pool by making backing memory available for use or reuse. In at least one embodiment, memory manager906releases backing memory930by returning backing memory to a memory pool by releasing virtual memory pointer for reuse. In at least one embodiment, memory in graphics processor memory pool912is in use928while graphics processor924executes kernel one926. In at least one embodiment, memory in graphics processor memory pool912is available for reuse932after kernel one completes and after memory manager906releases backing memory930for later reuse.

In at least one embodiment, processor902may then make a request to allocate memory934for kernel two, launch kernel two936, and make a request to free memory938, all of which are described herein in connection withFIGS.10-12as, for example, a request to allocate memory1034for kernel two, launch kernel two1036, a request to free memory1038, a request to allocate memory1234for kernel two, launch kernel two1236, a request to free memory1238, etc.

FIG.10illustrates an example second part of a data flow1000where memory is asynchronously allocated and deallocated, in accordance with at least one embodiment. In at least one embodiment, example second part of a data flow1000continues from example first part of a data flow900, described in connection withFIG.9.

In at least one embodiment, a processor1002requests memory1034from a memory manager1006. In at least one embodiment, processor1002is identical to processor902described in connection withFIG.9. In at least one embodiment, memory manager1006is identical to memory manager906described in connection withFIG.9. In at least one embodiment, memory manager1006determines a memory location1040in graphics processor memory pool1012using systems and methods such as those described herein. In at least one embodiment, graphics processor memory pool1012is identical to graphics processor memory pool912described in connection withFIG.9. In at least one embodiment, memory manager1006returns a virtual memory pointer1044to processor1002, as described herein. In at least one embodiment, memory manager1006returns virtual memory pointer1044to processor1002asynchronously in that, as described herein, a virtual memory pointer is returned to a processor in response to a memory request, before backing memory is used by an execution stream.

In at least one embodiment, processor1002executes a command to launch kernel two1036with a provided virtual memory pointer. In at least one embodiment, a graphics processor1024executes kernel two1048. In at least one embodiment, graphics processor1024is identical to graphics processor924described in connection withFIG.9. In at least one embodiment, when memory manager1006determines a memory location1040in graphics processor memory pool1012, memory is reserved for use1042. In at least one embodiment, memory is reserved for use1042so that memory will be available for use by kernel two when graphics processor1024executes kernel two1048.

In at least one embodiment, processor1002executes a command to free memory1038associated with kernel two. In at least one embodiment, when kernel two completes, memory manager1006releases backing memory1052for later reuse, as described herein. In at least one embodiment, memory manager1006releases backing memory1052by returning backing memory to a memory pool and/or by making backing memory available for use or reuse and by releasing virtual memory pointer for reuse, as described herein. In at least one embodiment, memory in graphics processor memory pool1012is in use1050while graphics processor1024executes kernel two1048. In at least one embodiment, memory in graphics processor memory pool1012is available for reuse1054after kernel two completes and after memory manager1006releases backing memory1052for later reuse.

FIG.11illustrates an example third part of a data flow1100where memory is asynchronously allocated and deallocated, in accordance with at least one embodiment. In at least one embodiment, example third part of a data flow1100continues from example second part of a data flow1000, described in connection withFIG.10. In at least one embodiment, actions of a memory manager1106(which is identical to memory manager906described herein at least in connection withFIG.9and which is identical to memory manager1006described herein at least in connection withFIG.10) are identical to actions of memory manager906and/or are identical to actions of memory manager1006as described herein and such actions are not illustrated inFIG.11for clarity.

In at least one embodiment, processor1102requests memory1104, executes a command to launch kernel one1118, and executes a command to free memory1120, all as described herein at least in connection withFIG.9(where processor902requests memory904, executes a command to launch kernel one918, and executes a command to free memory920). In at least one embodiment, processor1102is identical to processor1002described herein in connection withFIG.10.

In at least one embodiment, when processor1102requests memory1104, memory is reserved for use1114. In at least one embodiment, while graphics processor1124is executing kernel one1126, memory is in use1128in graphics processor memory pool1112. In at least one embodiment, graphics processor1124is identical to graphics processor1024described herein in connection withFIG.10. In at least one embodiment, graphics processor memory pool1112is identical to graphics processor memory pool1012described herein in connection withFIG.10. In at least one embodiment, when processor1102executes a command to free memory1120associated with kernel one, and when kernel one completes, memory that was in use1128in graphics processor memory pool1112become available1132, as described herein.

In at least one embodiment, processor1102requests memory1134, executes a command to launch kernel two1136, and executes a command to free memory1138, all as described herein at least in connection withFIG.10such as, where processor1002requests memory1034, executes a command to launch kernel two1036, and executes a command to free memory1038. In at least one embodiment, when processor1102requests memory1134for kernel two, memory manager1106determines that memory that was in use1128in graphics processor memory pool1112will become available1132before it is used by kernel two. In at least one embodiment, memory manager reserves memory1142using memory that will become available1132for use by kernel two.

In at least one embodiment, processor1102executes a command to launch kernel two1136with a provided virtual memory pointer from memory that will become available1132. In at least one embodiment, a graphics processor1124executes kernel two1148. In at least one embodiment, graphics processor1124is identical to graphics processor1024described in connection withFIG.10. In at least one embodiment, when memory manager1106determines a memory location in graphics processor memory pool as described above, memory is reserved for use1142from memory that will become available1132. In at least one embodiment, memory is reserved for use1142so that memory will be available for use by kernel two when graphics processor1124executes kernel two1148.

In at least one embodiment, processor1102executes a command to free memory1138associated with kernel two. In at least one embodiment, when kernel two completes, memory manager1106releases backing memory for later reuse, as described herein. In at least one embodiment, memory manager1106releases backing memory by returning backing memory to a memory pool and/or by making backing memory available for use or reuse), and by releasing virtual memory pointer for reuse, as described herein. In at least one embodiment, memory in graphics processor memory pool1112is in use1150while graphics processor1124executes kernel two1148. In at least one embodiment, memory in graphics processor memory pool1112is available for reuse1154after kernel two completes and after memory manager1106releases backing memory for later reuse.

FIG.12illustrates an example fourth part of a data flow1200where memory is asynchronously allocated and deallocated, in accordance with at least one embodiment. In at least one embodiment, example fourth part of a data flow1200continues from example second part of a data flow1000, described in connection withFIG.10and is an alternative to example third part of a data flow1100, described herein in connection withFIG.10. In at least one embodiment, actions of a memory manager1206(which is identical to memory manager906described herein at least in connection withFIG.9, which is identical to memory manager1006described herein at least in connection withFIG.10, and which is identical to memory manager1106described herein at least in connection withFIG.11) are identical to actions of memory manager906and/or are identical to actions of memory manager1006as described herein and such actions are not illustrated inFIG.12for clarity.

In at least one embodiment, processor1202requests memory1204, executes a command to launch kernel one1218, and executes a command to free memory1220, all as described herein at least in connection withFIG.9such as, where processor902requests memory904, executes a command to launch kernel one918, and executes a command to free memory920. In at least one embodiment, processor1202is identical to processor1002described herein in connection withFIG.10.

In at least one embodiment, when processor1202requests memory1204, memory is reserved for use1214. In at least one embodiment, while graphics processor1224is executing kernel one1226, memory is in use1228in graphics processor memory pool1212. In at least one embodiment, graphics processor1224is identical to graphics processor1024described herein in connection withFIG.10. In at least one embodiment, graphics processor memory pool1212is identical to graphics processor memory pool1012described herein in connection withFIG.10. In at least one embodiment, when processor1202executes a command to free memory1220associated with kernel one, and when kernel one completes, memory that was in use1228in graphics processor memory pool1212become available1232, as described herein.

In at least one embodiment, processor1202requests memory1234, executes a command to launch kernel two1236, and executes a command to free memory1238, all as described herein at least in connection withFIG.10such as, where processor1002requests memory1034, executes a command to launch kernel two1036, and executes a command to free memory1038. In at least one embodiment, when processor1202requests memory1234for kernel two, memory manager1206determines that memory that was in use1228in graphics processor memory pool1212will not become available1232before it will be used by kernel two when, for example kernel one is still be executing. In at least one embodiment, memory manager reserves memory1242using other memory than memory that will become available1232.

In at least one embodiment, processor1202executes a command to launch kernel two1236with a provided virtual memory pointer from reserved memory1242. In at least one embodiment, a graphics processor1224executes kernel two1248. In at least one embodiment, graphics processor1224is identical to graphics processor1024described in connection withFIG.10. In at least one embodiment, when memory manager1206determines a memory location in graphics processor memory pool as described above, memory is reserved for use1242from memory that is not memory that will become available1232. In at least one embodiment, memory is reserved for use1242so that memory will be available for use by kernel two when graphics processor1224executes kernel two1248.

In at least one embodiment, processor1202executes a command to free memory1238associated with kernel two. In at least one embodiment, when kernel two completes, memory manager1206releases backing memory for later reuse, as described herein. In at least one embodiment, memory manager1206releases backing memory by returning backing memory to a memory pool and/or by making backing memory available for use or reuse)and by releasing virtual memory pointer for reuse, as described herein. In at least one embodiment, memory in graphics processor memory pool1212is in use1250while graphics processor1224executes kernel two1248. In at least one embodiment, memory in graphics processor memory pool1212is available for reuse1254after kernel two completes and after memory manager1206releases backing memory for later reuse.

FIG.13illustrates an example process1300for performing memory management operations to asynchronously allocate memory using a memory pool, in accordance with at least one embodiment. In at least one embodiment, a memory manager such as memory manager106described herein at least in connection withFIG.1executes instructions to perform example process1300illustrated inFIG.13.

In at least one embodiment, at step1302of example process1300, a request for asynchronously allocated memory associated with a kernel is received using systems and methods such as those described herein. In at least one embodiment a request for asynchronously allocated memory with an associated virtual memory address that may be used to execute a kernel is received from a process such as example process500executing on a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, a request for asynchronously allocated memory with an associated virtual memory address that may be used to execute a kernel is received using an API. In at least one embodiment, not illustrated inFIG.13, a response to a request for asynchronously allocated memory with an associated virtual memory address that may be used to execute a kernel is generated. In at least one embodiment, a response to receiving a request for asynchronously allocated memory with an associated virtual memory address that may be used to execute a kernel is generated using an API. In at least one embodiment, after step1302, execution of example process1300advances to step1304.

In at least one embodiment, at step1304of example process1300, it is determined whether a previously allocated memory pool exists such as, for example, memory that has been previously created as described herein. In at least one embodiment, at step1304, if it is determined that a previously allocated memory pool exists (“YES” branch), execution of example process advances to step1310. In at least one embodiment, at step1304, if it is determined that a previously allocated memory pool does not exist (“NO” branch), execution of example process advances to step1306.

In at least one embodiment, at step1306of example process1300, a memory pool is created by allocating memory for a memory pool using systems and methods such as those described herein. In at least one embodiment, after step1306, execution of example process1300advances to step1308.

In at least one embodiment, at step1308of example process1300, it is determined whether a memory pool was successfully created. In at least one embodiment, at step1308, if it is determined that a memory pool was successfully created (“YES” branch), execution of example process advances to step1310. In at least one embodiment, at step1308, if it is determined that a memory pool was not successfully created (“NO” branch), execution of example process advances to step1314.

In at least one embodiment, at step1310of example process1300, memory is allocated from a memory pool using systems and methods such as those described herein. In at least one embodiment, after step1310, execution of example process1300advances to step1312.

In at least one embodiment, at step1312of example process1300, it is determined whether memory was successfully allocated from a memory pool. In at least one embodiment, at step1312, if it is determined that memory was successfully allocated from a memory pool (“YES” branch), execution of example process advances to step1316. In at least one embodiment, at step1312, if it is determined that memory was not successfully allocated from a memory pool (“NO” branch), execution of example process advances to step1314.

In at least one embodiment, at step1314of example process1300, as a result of determining that memory was not successfully allocated from a memory pool (in step1310), an indication of failure is returned. In at least one embodiment, an indication of failure is returned to a requesting process. In at least one embodiment, an indication of failure is returned to a requesting process such as example process500executing on a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, an indication of failure is returned using an API. In at least one embodiment, an indication of failure is returned to a calling process using a signal. In at least one embodiment an indication of failure is returned to a calling process using a semaphore. In at least one embodiment, not illustrated inFIG.13, a response to an indication of failure is received. In at least one embodiment, after step1314, example process1300terminates. In at least one embodiment, after step1314, example process1300returns to step1302to receive a new request to execute a kernel with an associated virtual memory address.

In at least one embodiment, at step1316of example process1300, memory allocated from a memory pool is associated with a virtual memory address such as, for example, a virtual memory address received in step1302, using systems and methods such as those described herein. In at least one embodiment, after step1316, execution of example process1300advances to step1318.

In at least one embodiment, at step1318of example process1300as a result of determining that memory was not successfully allocated from a memory pool (in step1310), an indication of failure is returned using systems and methods such as those described in connection with step1314, using an API, using a signal, and/or using a semaphore. In at least one embodiment, after step1318, example process1300terminates. In at least one embodiment, after step1318, example process1300returns to step1302to1302to receive a new request to execute a kernel with an associated virtual memory address.

In at least one embodiment, operations of example process1300illustrated inFIG.13are performed in a different order than indicated inFIG.13. In at least one embodiment, operations of example process1300illustrated inFIG.13are performed simultaneously and/or in parallel. In at least one embodiment, operations of example process1300illustrated inFIG.13are performed by a plurality of threads executing on a memory manager such as memory manager106described herein at least in connection withFIG.1.

FIG.14illustrates an example computer system1400where memory management operations to asynchronously allocate memory using a memory pool for a single execution stream are performed, in accordance with at least one embodiment. In at least one embodiment, an execution stream1402indicates a stream order for operations that use one or more memory locations in asynchronously allocated memory allocated from a memory pool. In at least one embodiment, execution stream1402indicates ordered operations to allocate memory for kernel one1404, execute kernel one1410, release kernel one memory1412, allocate memory for kernel two1416, execute kernel two1420, and release kernel two memory1422.

In at least one embodiment, operations specified in execution stream1402may be implicit. In at least one embodiment, for example, an ordered operation to allocate memory for kernel one1404may be automatically executed when an ordered operation to execute kernel one1410is executed and an ordered operation to release kernel one memory1412may be automatically executed when an ordered operation to execute kernel one1410completes. In at least one embodiment, operations specified in execution stream1402may be explicitly called by, for example, an API, using systems and methods such as those described herein.

In at least one embodiment, when execution stream1402indicates execution of an ordered operation to allocate memory for kernel one1404, a memory manager1406(which is a memory manager such as memory manager106described herein at least in connection withFIG.1) provides backing memory1408from a memory pool using systems and methods such as those described herein. In at least one embodiment, for example, memory manager1406may provide backing memory from a memory pool at address 0X1000.

In at least one embodiment, when execution stream1402indicates execution of an ordered operation to release kernel one memory1412, memory manager1406may perform one or more operations to return backing memory to a memory pool1414, may perform one or more operations to mark backing memory as reusable, and/or may perform one or more operations to release a virtual memory pointer associated with said backing memory, using systems and methods such as those described herein.

In at least one embodiment, when execution stream1402indicates execution of an ordered operation to allocate memory for kernel two1416, memory manager1406provides backing memory1418from a memory pool using systems and methods such as those described herein. In at least one embodiment, memory manager1406reuses backing memory at address 0X1000 because, due to an order of operations specified by execution stream1402, memory manager1406determines that kernel one will complete before kernel two is executed and, accordingly, memory available to kernel one may be reused by kernel two and may, for example, be made available to kernel two).

In at least one embodiment, when execution stream1402indicates execution of an ordered operation to release kernel two memory1422, memory manager1406may perform one or more operations to return backing memory to a memory pool1424, may perform one or more operations to mark said backing memory as reusable, and/or may perform one or more operations to release a virtual memory pointer associated with said backing memory, using systems and methods such as those described herein.

FIG.15illustrates an example computer system1500where memory management operations to asynchronously allocate memory using a memory pool for a plurality of execution streams are performed, in accordance with at least one embodiment. In at least one embodiment, an execution stream indicates a stream order for operations that use one or more memory locations in asynchronously allocated memory allocated from a memory pool. In at least one embodiment, a first execution stream1502indicates ordered operations to allocate memory for kernel one1504, execute kernel one1510, and release kernel one memory1512. In at least one embodiment, a second execution stream1516indicates ordered operations to allocate memory for kernel one1518, execute kernel one1522, release kernel one memory1524, allocate memory for kernel two1528, execute kernel two1532, and release kernel two memory1534. In at least one embodiment, operations specified in first execution stream1502may be implicit, may be explicit, and/or may be called by an API and operations specified in second execution stream1516may also be implicit, may be explicit, and/or may called by an API.

In at least one embodiment, when first execution stream1502indicates execution of an ordered operation to allocate memory for kernel one1504, a memory manager1506(which is a memory manager such as memory manager106described herein at least in connection withFIG.1) provides backing memory1508from a memory pool using systems and methods such as those described herein. In at least one embodiment, for example, memory manager1506may provide backing memory from a memory pool at address 0X1000. In at least one embodiment, when first execution stream1502indicates execution of an ordered operation to release kernel one memory1512, memory manager1506may perform one or more operations to return backing memory to a memory pool1514, using systems and methods such as those described herein.

In at least one embodiment, when second execution stream1516indicates execution of an ordered operation to allocate memory for kernel one1518, memory manager1506provides backing memory1520from a memory pool using systems and methods such as those described herein. In at least one embodiment, for example, memory manager1506may provide backing memory from a memory pool at address 0X2000. In at least one embodiment, memory manager1506may not provide backing memory from a memory pool at address 0X1000 (may not reuse memory at address 0X1000) because execution of kernel one from execution stream1502may or may not be complete. In at least one embodiment, when second execution stream1516indicates execution of an ordered operation to release kernel one memory1524, memory manager1506may perform one or more operations to return backing memory to a memory pool1526, using systems and methods such as those described herein.

In at least one embodiment, when second execution stream1516indicates execution of an ordered operation to allocate memory for kernel two1518, memory manager1506provides backing memory1508from a memory pool using systems and methods such as those described herein. In at least one embodiment, memory manager1506may reuse backing memory1530at address 0X2000 because, due to an order of operations specified by execution stream1516, memory manager1506determines that kernel one will complete before kernel two is executed and, accordingly, memory available to kernel one may be reused by kernel two. In at least one embodiment, memory manager1506still may not provide backing memory from a memory pool at address 0X1000 (may not reuse memory at address 0X1000) because execution of kernel one from execution stream1502still may or may not be complete. In at least one embodiment, when second execution stream1516indicates execution of an ordered operation to release kernel two memory1534, memory manager1506may perform one or more operations to return backing memory to a memory pool1536, using systems and methods such as those described herein.

FIG.16illustrates an example process1600for performing memory management operations to reuse asynchronously allocated memory from a memory pool, in accordance with at least one embodiment. In at least one embodiment, a memory manager such as memory manager106described herein at least in connection withFIG.1executes instructions to perform example process1600illustrated inFIG.16.

In at least one embodiment, at step1602of example process1600, a request is received for asynchronously allocated memory. In at least one embodiment, a request for asynchronously allocated memory is received from a process such as example process500executing on a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, a request for asynchronously allocated memory is received using an API, as described herein at least in connection withFIG.5. In at least one embodiment, not illustrated inFIG.16, a response to receiving a request for asynchronously allocated memory is generated. In at least one embodiment, a response to receiving a request for asynchronously allocated memory is generated using an API. In at least one embodiment, after step1602, execution of example process1600advances to step1604.

In at least one embodiment, at step1604of example process1600, a determination is made as to whether previously used pool memory will be available prior to execution of work associated with a request for asynchronously allocated memory such as, for example, a kernel. In at least one embodiment, a determination is made as to whether previously used pool memory will be available prior to execution of work associated with a request for asynchronously allocated memory based at least in part on a stream execution order, as described herein at least in connection withFIG.14andFIG.15. In at least one embodiment, after step1604, execution of example process1600advances to step1606.

In at least one embodiment, at step1606of example process1600, if it is determined that previously used pool memory will be available prior to execution of work associated with a request for asynchronously allocated memory as described in step1604(“YES” branch), execution of example process advances to step1610. In at least one embodiment, at step1606, if it is determined that previously used pool memory will not be available prior to execution of work associated with a request for asynchronously allocated memory as described in step1604(“NO” branch), execution of example process advances to step1608.

In at least one embodiment, at step1608of example process1600, a new, not reused, virtual address is provided using systems and methods such as those described herein. In at least one embodiment, a new virtual address is provided to a requesting process such as example process500, described herein. In at least one embodiment, a new virtual address is provided to a requesting process executing on a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, a new virtual address is provided using an API as described herein at least in connection withFIG.5. In at least one embodiment, not illustrated inFIG.16, a response to a provided new virtual memory address is received. In at least one embodiment, a response to a provided new virtual memory address is received from a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, a response to a provided a provided new virtual memory address is received using an API. In at least one embodiment, after step1608, execution of example process1600advances to step1612.

In at least one embodiment, at step1610of example process1600, a reused virtual address such as, a virtual address that was previously used, as described herein in connection withFIG.14andFIG.15, is provided using systems and methods such as those described in connection with step1608. In at least one embodiment, after step1610, execution of example process1600advances to step1612.

In at least one embodiment, at step1612of example process1600, a request is received to execute work associated with a virtual memory address using systems and methods such as those described herein. In at least one embodiment, a request is received to execute work associated with a virtual memory address using systems and methods such as those described in connection with step1602such as, from a calling process and/or using an API. In at least one embodiment, after step1612, execution of example process1600advances to step1614.

In at least one embodiment, at step1614of example process1600, work that uses memory from a memory pool at an address provided in step1608or step1610is launched, using systems and methods such as those described herein. In at least one embodiment, after step1614, execution of example process1600terminates. In at least one embodiment, after step1614, example process1600returns to step1602to receive a new request for asynchronously allocated memory.

In at least one embodiment, operations of example process1600illustrated inFIG.16are performed in a different order than indicated inFIG.16. In at least one embodiment, operations of example process1600illustrated inFIG.16are performed simultaneously and/or in parallel. In at least one embodiment, operations of example process1600illustrated inFIG.16are performed by a plurality of threads executing on a memory manager such as memory manager106described herein at least in connection withFIG.1.

FIG.17illustrates an example computer system1700where memory management operations to reuse asynchronously allocated memory from a memory pool for a plurality of synchronized execution streams are performed, in accordance with at least one embodiment. In at least one embodiment, an execution stream indicates a stream order for operations that use one or more memory locations in asynchronously allocated memory allocated from a memory pool. In at least one embodiment, a first execution stream1702indicates ordered operations to allocate memory for work1704associated with asynchronously allocated memory, execute associated work1710, and release memory1712. In at least one embodiment, first execution stream1702indicates an ordered operation to sync1716with a second execution stream1718. In at least one embodiment, operations specified in first execution stream1702may be implicit, may be explicit, and/or may be called by an API.

In at least one embodiment, second execution stream1718indicates ordered operations to allocate memory for work1720associated with asynchronously allocated memory, execute work1724, release memory1726, and allocate memory for work1732. In at least one embodiment, not shown inFIG.17, second execution stream1718may also indicate ordered operations to execute work and release allocated memory. In at least one embodiment, second execution stream1718indicates an ordered operation to wait1730for a sync from execution stream1702. In at least one embodiment, operations specified in second execution stream1718may also be implicit, may be explicit, and/or may be called by an API.

In at least one embodiment, when first execution stream1702indicates execution of an ordered operation to allocate memory for work1704, a memory manager1706(which is a memory manager such as memory manager106described herein at least in connection withFIG.1) provides memory1708from a memory pool at address 0X1000 using systems and methods such as those described herein. In at least one embodiment, when first execution stream1702indicates execution of an ordered operation to release memory1712, memory manager1706may perform one or more operations to return backing memory to a memory pool1714, using systems and methods such as those described herein.

In at least one embodiment, when second execution stream1718indicates execution of an ordered operation to allocate memory for work1720, memory manager1706provides backing memory1722from a memory pool at address 0X2000 using systems and methods such as those described herein. In at least one embodiment, memory manager1706may not provide backing memory from a memory pool at address 0X1000 (may not reuse memory at address 0X1000) because execution of work from execution stream1702may or may not be complete. In at least one embodiment, when second execution stream1718indicates execution of an ordered operation to release memory1726, memory manager1706may perform one or more operations to return backing memory to a memory pool1728, using systems and methods such as those described herein.

In at least one embodiment, first execution stream1702indicates an ordered operation to sync1716with second execution stream1718and second execution stream1718indicates an ordered operation to wait1730for a sync from execution stream1702. In at least one embodiment, when second execution stream1718indicates execution of an ordered operation to allocate memory for work1732, memory manager1706provides backing memory1708from a memory pool using systems and methods such as those described herein. In at least one embodiment, memory manager1706may reuse backing memory1734at address 0X2000 because, due to an order of operations specified by second execution stream1718, memory manager1706can determine that work in execution stream1718will complete before other work is executed and, accordingly, memory available may be reused. In at least one embodiment, memory manager1706also reuse1734backing memory from a memory pool at address 0X1000 because execution of work from first execution stream1702will be complete before beginning execution of additional work from second execution stream1718due to sync and wait operations.

FIG.18illustrates an example process1800for performing memory management operations to reuse asynchronously allocated memory from a memory pool for a plurality of synchronized execution streams, in accordance with at least one embodiment. In at least one embodiment, a memory manager such as memory manager106described herein at least in connection withFIG.1executes instructions to perform example process1800illustrated inFIG.18.

In at least one embodiment, at step1802of example process1800, a request is received for asynchronously allocated memory for an execution stream, as described herein. In at least one embodiment, a request for an asynchronously allocated memory is received from a process such as process500, described herein at least in connection withFIG.5. In at least one embodiment, a request for asynchronously allocated memory is received from a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment, a process sends a request for asynchronously allocated memory on behalf of another process. In at least one embodiment, a request for asynchronously allocated memory is received using an API as described herein at least in connection withFIG.5. In at least one embodiment, not illustrated inFIG.18, a response to receiving a request for asynchronously allocated memory is generated. In at least one embodiment, a response to a request for asynchronously allocated memory is generated using an API. In at least one embodiment, after step1802, execution of example process1800advances to step1804.

In at least one embodiment, at step1804of example process1800, it is determined whether there is a synchronization event between a first execution stream and a second execution stream. In at least one embodiment, a memory manager may examine an execution stream to determine if there is a synchronization event between a first execution stream and a second execution stream. In at least one embodiment, a memory manager may examine a specification for a stream order of an execution stream to determine if there is a synchronization event between a first execution stream and a second execution stream. In at least one embodiment, a memory manager may examine a specification for an execution graph of an execution stream to determine if there is a synchronization event between a first execution stream and a second execution stream. In at least one embodiment, after step1804, execution of example process1800advances to step1806.

In at least one embodiment, at step1806of example process1800, if it is determined (in step1806) that there is a synchronization event between a first execution stream and a second execution stream (“YES” branch), execution of example process advances to step1808. In at least one embodiment, at step1806, if it is determined (in step1806) that there is not a synchronization event between a first execution stream and a second execution stream (“NO” branch), execution of example process advances to step1814.

In at least one embodiment, at step1808of example process1800, it is determined whether there is reusable memory in another execution stream and whether there is a synchronization event between a first execution stream and a second execution stream. In at least one embodiment, after step1808, execution of example process1800advances to step1810.

In at least one embodiment, at step1810of example process1800, if it is determined (in step1808) that there is reusable memory in another execution stream that may be released before a synchronization event (“YES” branch), execution of example process advances to step1812. In at least one embodiment, at step1810, if it is determined (in step1808) that there is not reusable memory in another execution stream that may be released before a synchronization event (“NO” branch), execution of example process advances to step1814.

In at least one embodiment, at step1812of example process1800, a reusable virtual address determined based on synchronization is provided. In at least one embodiment, a reusable virtual address determined based on synchronization is provided to a process such as example process500, described herein at least in connection withFIG.5. In at least one embodiment a reusable virtual address determined based on synchronization is provided to a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment a reusable virtual address determined based on synchronization is provided to a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, a reusable virtual address determined based on synchronization is provided using an API as described herein at least in connection withFIG.5.

In at least one embodiment, not illustrated inFIG.18, a response to a provided reusable virtual address determined based on synchronization is received. In at least one embodiment, a response to a provided reusable virtual address determined based on synchronization is received from a process such as example process500, described herein at least in connection withFIG.5. In at least one embodiment, a response to a provided reusable virtual address determined based on synchronization is received a processor such as processor102described herein at least in connection withFIG.1. In at least one embodiment a response to a provided reusable virtual address determined based on synchronization is received from a graphics processor such as graphics processor108described herein at least in connection withFIG.1. In at least one embodiment, a response to a provided reusable virtual address determined based on synchronization is received using an API. In at least one embodiment, after step1812, execution of example process1800advances to step1816.

In at least one embodiment, at step1814of example process1800, a new or a reusable virtual address is generated using systems and methods such as those described herein, at least in connection withFIGS.14-17and is provided using systems and methods such as those described in connection with step1812. In at least one embodiment, after step1814, execution of example process1800advances to step1816.

In at least one embodiment, at step1816of example process1800, a request is received to execute work associated with a virtual memory address using systems and methods such as those described herein. In at least one embodiment, a request is received to execute work associated with a virtual memory address using systems and methods such as those described in connection with step1802such as, from a calling process and/or using an API. In at least one embodiment, after step1816, execution of example process1600advances to step1818.

In at least one embodiment, at step1818of example process1800, work that uses memory from a memory pool at an address provided in step1812or step1814is launched, using systems and methods such as those described herein. In at least one embodiment, after step1818, execution of example process1800terminates. In at least one embodiment, after step1818, example process1800returns to step1802to receive a new request for asynchronously allocated memory.

In at least one embodiment, operations of example process1800illustrated inFIG.18are performed in a different order than indicated inFIG.18. In at least one embodiment, operations of example process1800illustrated inFIG.18are performed simultaneously and/or in parallel. In at least one embodiment, operations of example process1800illustrated inFIG.18are performed by a plurality of threads executing on a memory manager such as memory manager106described herein at least in connection withFIG.1.

In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details.

Data Center

FIG.19illustrates an exemplary data center1900, in accordance with at least one embodiment. In at least one embodiment, data center1900includes, without limitation, a data center infrastructure layer1910, a framework layer1920, a software layer1930and an application layer1940.

In at least one embodiment, as shown inFIG.19, data center infrastructure layer1910may include a resource orchestrator1912, grouped computing resources1914, and node computing resources (“node C.R.s”)1916(1)-1916(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s1916(1)-1916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s1916(1)-1916(N) may be a server having one or more of above-mentioned computing resources.

In at least one embodiment, resource orchestrator1912may configure or otherwise control one or more node C.R.s1916(1)-1916(N) and/or grouped computing resources1914. In at least one embodiment, resource orchestrator1912may include a software design infrastructure (“SDI”) management entity for data center1900. In at least one embodiment, resource orchestrator1912may include hardware, software or some combination thereof.

In at least one embodiment, as shown inFIG.19, framework layer1920includes, without limitation, a job scheduler1932, a configuration manager1934, a resource manager1936and a distributed file system1938. In at least one embodiment, framework layer1920may include a framework to support software1952of software layer1930and/or one or more application(s)1942of application layer1940. In at least one embodiment, software1952or application(s)1942may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer1920may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system1938for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler1932may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center1900. In at least one embodiment, configuration manager1934may be capable of configuring different layers such as software layer1930and framework layer1920, including Spark and distributed file system1938for supporting large-scale data processing. In at least one embodiment, resource manager1936may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system1938and job scheduler1932. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource1914at data center infrastructure layer1910. In at least one embodiment, resource manager1936may coordinate with resource orchestrator1912to manage these mapped or allocated computing resources.

In at least one embodiment, software1952included in software layer1930may include software used by at least portions of node C.R.s1916(1)-1916(N), grouped computing resources1914, and/or distributed file system1938of framework layer1920. One or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

In at least one embodiment, application(s)1942included in application layer1940may include one or more types of applications used by at least portions of node C.R.s1916(1)-1916(N), grouped computing resources1914, and/or distributed file system1938of framework layer1920. In at least one or more types of applications may include, without limitation, CUDA applications.

In at least one embodiment, any of configuration manager1934, resource manager1936, and resource orchestrator1912may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center1900from making possibly bad configuration decisions and possibly avoiding underutilized and/or poor performing portions of a data center.

In at least one embodiment, at least one component shown or described with respect toFIG.19is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of grouped computing resources1914and node C.R.1916(1-N) are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of grouped computing resources1914and node C.R.1916(1-N) are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of grouped computing resources1914and node C.R.1916(1-N) are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of grouped computing resources1914and node C.R.1916(1-N) are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of grouped computing resources1914and node C.R.1916(1-N) are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

The following figures set forth, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment.

FIG.20illustrates a processing system2000, in accordance with at least one embodiment. In at least one embodiment, processing system2000includes one or more processors2002and one or more graphics processors2008, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors2002or processor cores2007. In at least one embodiment, processing system2000is a processing platform incorporated within a system-on-a-chip (“SoC”) integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, processing system2000can include, or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system2000is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system2000can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system2000is a television or set top box device having one or more processors2002and a graphical interface generated by one or more graphics processors2008.

In at least one embodiment, one or more processors2002each include one or more processor cores2007to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores2007is configured to process a specific instruction set2009. In at least one embodiment, instruction set2009may facilitate Complex Instruction Set Computing (“CISC”), Reduced Instruction Set Computing (“RISC”), or computing via a Very Long Instruction Word (“VLIW”). In at least one embodiment, processor cores2007may each process a different instruction set2009, which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core2007may also include other processing devices, such as a digital signal processor (“DSP”).

In at least one embodiment, processor2002includes cache memory (“cache”)2004. In at least one embodiment, processor2002can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor2002. In at least one embodiment, processor2002also uses an external cache (e.g., a Level 3 (“L3”) cache or Last Level Cache (“LLC”)) (not shown), which may be shared among processor cores2007using known cache coherency techniques. In at least one embodiment, register file2006is additionally included in processor2002which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file2006may include general-purpose registers or other registers.

In at least one embodiment, one or more processor(s)2002are coupled with one or more interface bus(es)2010to transmit communication signals such as address, data, or control signals between processor2002and other components in processing system2000. In at least one embodiment interface bus2010, in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (“DMI”) bus. In at least one embodiment, interface bus2010is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., “PCI,” PCI Express (“PCIe”)), memory buses, or other types of interface buses. In at least one embodiment processor(s)2002include an integrated memory controller2016and a platform controller hub2030. In at least one embodiment, memory controller2016facilitates communication between a memory device and other components of processing system2000, while platform controller hub (“PCH”)2030provides connections to Input/Output (“I/O”) devices via a local I/O bus.

In at least one embodiment, memory device2020can be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as processor memory. In at least one embodiment memory device2020can operate as system memory for processing system2000, to store data2022and instructions2021for use when one or more processors2002executes an application or process. In at least one embodiment, memory controller2016also couples with an optional external graphics processor2012, which may communicate with one or more graphics processors2008in processors2002to perform graphics and media operations. In at least one embodiment, a display device2011can connect to processor(s)2002. In at least one embodiment display device2011can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device2011can include a head mounted display (“HMD”) such as a stereoscopic display device for use in virtual reality (“VR”) applications or augmented reality (“AR”) applications.

In at least one embodiment, platform controller hub2030enables peripherals to connect to memory device2020and processor2002via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller2046, a network controller2034, a firmware interface2028, a wireless transceiver2026, touch sensors2025, a data storage device2024(e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device2024can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as PCI, or PCIe. In at least one embodiment, touch sensors2025can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver2026can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (“LTE”) transceiver. In at least one embodiment, firmware interface2028enables communication with system firmware, and can be, for example, a unified extensible firmware interface (“UEFI”). In at least one embodiment, network controller2034can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus2010. In at least one embodiment, audio controller2046is a multi-channel high definition audio controller. In at least one embodiment, processing system2000includes an optional legacy I/O controller2040for coupling legacy (e.g., Personal System 2 (“PS/2”)) devices to processing system2000. In at least one embodiment, platform controller hub2030can also connect to one or more Universal Serial Bus (“USB”) controllers2042connect input devices, such as keyboard and mouse2043combinations, a camera2044, or other USB input devices.

In at least one embodiment, an instance of memory controller2016and platform controller hub2030may be integrated into a discreet external graphics processor, such as external graphics processor2012. In at least one embodiment, platform controller hub2030and/or memory controller2016may be external to one or more processor(s)2002. For example, in at least one embodiment, processing system2000can include an external memory controller2016and platform controller hub2030, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s)2002.

In at least one embodiment, at least one component shown or described with respect toFIG.20is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of processor(s)2002or external graphics processor2012are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of processor(s)2002or external graphics processor2012are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of processor(s)2002or external graphics processor2012are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of processor(s)2002or external graphics processor2012are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of processor(s)2002or external graphics processor2012are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.21illustrates a computer system2100, in accordance with at least one embodiment. In at least one embodiment, computer system2100may be a system with interconnected devices and components, an SOC, or some combination. In at least on embodiment, computer system2100is formed with a processor2102that may include execution units to execute an instruction. In at least one embodiment, computer system2100may include, without limitation, a component, such as processor2102to employ execution units including logic to perform algorithms for processing data. In at least one embodiment, computer system2100may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system2100may execute a version of WINDOWS' operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used.

In at least one embodiment, computer system2100may include, without limitation, processor2102that may include, without limitation, one or more execution units2108that may be configured to execute a Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, Calif.) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system2100is a single processor desktop or server system. In at least one embodiment, computer system2100may be a multiprocessor system. In at least one embodiment, processor2102may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor2102may be coupled to a processor bus2110that may transmit data signals between processor2102and other components in computer system2100.

In at least one embodiment, processor2102may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”)2104. In at least one embodiment, processor2102may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor2102. In at least one embodiment, processor2102may also include a combination of both internal and external caches. In at least one embodiment, a register file2106may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register.

In at least one embodiment, execution unit2108, including, without limitation, logic to perform integer and floating point operations, also resides in processor2102. Processor2102may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit2108may include logic to handle a packed instruction set2109. In at least one embodiment, by including packed instruction set2109in an instruction set of a general-purpose processor2102, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor2102. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor's data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across a processor's data bus to perform one or more operations one data element at a time.

In at least one embodiment, execution unit2108may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system2100may include, without limitation, a memory2120. In at least one embodiment, memory2120may be implemented as a DRAM device, an SRAM device, flash memory device, or other memory device. Memory2120may store instruction(s)2119and/or data2121represented by data signals that may be executed by processor2102.

In at least one embodiment, a system logic chip may be coupled to processor bus2110and memory2120. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”)2116, and processor2102may communicate with MCH2116via processor bus2110. In at least one embodiment, MCH2116may provide a high bandwidth memory path2118to memory2120for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH2116may direct data signals between processor2102, memory2120, and other components in computer system2100and to bridge data signals between processor bus2110, memory2120, and a system I/O2122. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH2116may be coupled to memory2120through high bandwidth memory path2118and graphics/video card2112may be coupled to MCH2116through an Accelerated Graphics Port (“AGP”) interconnect2114.

In at least one embodiment, computer system2100may use system I/O2122that is a proprietary hub interface bus to couple MCH2116to I/O controller hub (“ICH”)2130. In at least one embodiment, ICH2130may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory2120, a chipset, and processor2102. Examples may include, without limitation, an audio controller2129, a firmware hub (“flash BIOS”)2128, a wireless transceiver2126, a data storage2124, a legacy I/O controller2123containing a user input interface2125and a keyboard interface, a serial expansion port2127, such as a USB, and a network controller2134. Data storage2124may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment,FIG.21illustrates a system, which includes interconnected hardware devices or “chips.” In at least one embodiment,FIG.21may illustrate an exemplary SoC. In at least one embodiment, devices illustrated inFIG.21may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system2100are interconnected using compute express link (“CXL”) interconnects.

In at least one embodiment, at least one component shown or described with respect toFIG.21is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, processor2102is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, processor2102is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor2102is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor2102is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, processor2102is to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.22illustrates a system2200, in accordance with at least one embodiment. In at least one embodiment, system2200is an electronic device that utilizes a processor2210. In at least one embodiment, system2200may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

In at least one embodiment, system2200may include, without limitation, processor2210communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor2210is coupled using a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In at least one embodiment,FIG.22illustrates a system which includes interconnected hardware devices or “chips.” In at least one embodiment,FIG.22may illustrate an exemplary SoC. In at least one embodiment, devices illustrated inFIG.22may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components ofFIG.22are interconnected using CXL interconnects.

In at least one embodiment,FIG.22may include a display2224, a touch screen2225, a touch pad2230, a Near Field Communications unit (“NFC”)2245, a sensor hub2240, a thermal sensor2246, an Express Chipset (“EC”)2235, a Trusted Platform Module (“TPM”)2238, BIOS/firmware/flash memory (“BIOS, FW Flash”)2222, a DSP2260, a Solid State Disk (“SSD”) or Hard Disk Drive (“HDD”)2220, a wireless local area network unit (“WLAN”)2250, a Bluetooth unit2252, a Wireless Wide Area Network unit (“WWAN”)2256, a Global Positioning System (“GPS”)2255, a camera (“USB 3.0 camera”)2254such as a USB3.0camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)2215implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to processor2210through components discussed above. In at least one embodiment, an accelerometer2241, an Ambient Light Sensor (“ALS”)2242, a compass2243, and a gyroscope2244may be communicatively coupled to sensor hub2240. In at least one embodiment, a thermal sensor2239, a fan2237, a keyboard2236, and a touch pad2230may be communicatively coupled to EC2235. In at least one embodiment, a speaker2263, a headphones2264, and a microphone (“mic”)2265may be communicatively coupled to an audio unit (“audio codec and class d amp”)2262, which may in turn be communicatively coupled to DSP2260. In at least one embodiment, audio unit2262may include, for example and without limitation, an audio coder/decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”)2257may be communicatively coupled to WWAN unit2256. In at least one embodiment, components such as WLAN unit2250and Bluetooth unit2252, as well as WWAN unit2256may be implemented in a Next Generation Form Factor (“NGFF”).

In at least one embodiment, at least one component shown or described with respect toFIG.22is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, processor2210is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, processor2210is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor2210is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor2210is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment processor2210is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.23illustrates an exemplary integrated circuit2300, in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit2300is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit2300includes one or more application processor(s)2305(e.g., CPUs, DPUs), at least one graphics processor2310, and may additionally include an image processor2315and/or a video processor2320, any of which may be a modular IP core. In at least one embodiment, integrated circuit2300includes peripheral or bus logic including a USB controller2325, a UART controller2330, an SPI/SDIO controller2335, and an I2S/I2C controller2340. In at least one embodiment, integrated circuit2300can include a display device2345coupled to one or more of a high-definition multimedia interface (“HDMI”) controller2350and a mobile industry processor interface (“MIPI”) display interface2355. In at least one embodiment, storage may be provided by a flash memory subsystem2360including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller2365for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine2370.

In at least one embodiment, at least one component shown or described with respect toFIG.23is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of application processor2305, graphics processor2310, image processor2315, or video processor2320are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of application processor2305, graphics processor2310, image processor2315, or video processor2320are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of application processor2305, graphics processor2310, image processor2315, or video processor2320are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of application processor2305, graphics processor2310, image processor2315, or video processor2320are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of application processor2305, graphics processor2310, image processor2315, or video processor2320are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.24illustrates a computing system2400, according to at least one embodiment; In at least one embodiment, computing system2400includes a processing subsystem2401having one or more processor(s)2402and a system memory2404communicating via an interconnection path that may include a memory hub2405. In at least one embodiment, memory hub2405may be a separate component within a chipset component or may be integrated within one or more processor(s)2402. In at least one embodiment, memory hub2405couples with an I/O subsystem2411via a communication link2406. In at least one embodiment, I/O subsystem2411includes an I/O hub2407that can enable computing system2400to receive input from one or more input device(s)2408. In at least one embodiment, I/O hub2407can enable a display controller, which may be included in one or more processor(s)2402, to provide outputs to one or more display device(s)2410A. In at least one embodiment, one or more display device(s)2410A coupled with I/O hub2407can include a local, internal, or embedded display device.

In at least one embodiment, processing subsystem2401includes one or more parallel processor(s)2412coupled to memory hub2405via a bus or other communication link2413. In at least one embodiment, communication link2413may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCIe, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s)2412form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core processor. In at least one embodiment, one or more parallel processor(s)2412form a graphics processing subsystem that can output pixels to one of one or more display device(s)2410A coupled via I/O Hub2407. In at least one embodiment, one or more parallel processor(s)2412can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)2410B.

In at least one embodiment, a system storage unit2414can connect to I/O hub2407to provide a storage mechanism for computing system2400. In at least one embodiment, an I/O switch2416can be used to provide an interface mechanism to enable connections between I/O hub2407and other components, such as a network adapter2418and/or wireless network adapter2419that may be integrated into a platform, and various other devices that can be added via one or more add-in device(s)2420. In at least one embodiment, network adapter2418can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter2419can include one or more of a Wi-Fi, Bluetooth, NFC, or other network device that includes one or more wireless radios.

In at least one embodiment, computing system2400can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, that may also be connected to I/O hub2407. In at least one embodiment, communication paths interconnecting various components inFIG.24may be implemented using any suitable protocols, such as PCI based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and/or protocol(s), such as NVLink high-speed interconnect, or interconnect protocols.

In at least one embodiment, one or more parallel processor(s)2412incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (“GPU”). In at least one embodiment, one or more parallel processor(s)2412incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system2400may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s)2412, memory hub2405, processor(s)2402, and I/O hub2407can be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system2400can be integrated into a single package to form a system in package (“SIP”) configuration. In at least one embodiment, at least a portion of the components of computing system2400can be integrated into a multi-chip module (“MCM”), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I/O subsystem2411and display devices2410B are omitted from computing system2400.

In at least one embodiment, at least one component shown or described with respect toFIG.24is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of processor(s)2402or parallel processor(s)2412are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of processor(s)2402or parallel processor(s)2412are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of processor(s)2402or parallel processor(s)2412are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of processor(s)2402or parallel processor(s)2412are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of processor(s)2402or parallel processor(s)2412are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

Processing Systems

The following figures set forth, without limitation, exemplary processing systems that can be used to implement at least one embodiment.

FIG.25illustrates an accelerated processing unit (“APU”)2500, in accordance with at least one embodiment. In at least one embodiment, APU2500is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, APU2500can be configured to execute an application program, such as a CUDA program. In at least one embodiment, APU2500includes, without limitation, a core complex2510, a graphics complex2540, fabric2560, I/O interfaces2570, memory controllers2580, a display controller2592, and a multimedia engine2594. In at least one embodiment, APU2500may include, without limitation, any number of core complexes2510, any number of graphics complexes2550, any number of display controllers2592, and any number of multimedia engines2594in any combination. For explanatory purposes, multiple instances of like objects are denoted herein with reference numbers identifying the object and parenthetical numbers identifying the instance where needed.

In at least one embodiment, core complex2510is a CPU, graphics complex2540is a GPU, and APU2500is a processing unit that integrates, without limitation,2510and2540onto a single chip. In at least one embodiment, some tasks may be assigned to core complex2510and other tasks may be assigned to graphics complex2540. In at least one embodiment, core complex2510is configured to execute main control software associated with APU2500, such as an operating system. In at least one embodiment, core complex2510is the master processor of APU2500, controlling and coordinating operations of other processors. In at least one embodiment, core complex2510issues commands that control the operation of graphics complex2540. In at least one embodiment, core complex2510can be configured to execute host executable code derived from CUDA source code, and graphics complex2540can be configured to execute device executable code derived from CUDA source code.

In at least one embodiment, core complex2510includes, without limitation, cores2520(1)-2520(4) and an L3 cache2530. In at least one embodiment, core complex2510may include, without limitation, any number of cores2520and any number and type of caches in any combination. In at least one embodiment, cores2520are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core2520is a CPU core.

In at least one embodiment, each core2520includes, without limitation, a fetch/decode unit2522, an integer execution engine2524, a floating point execution engine2526, and an L2 cache2528. In at least one embodiment, fetch/decode unit2522fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine2524and floating point execution engine2526. In at least one embodiment, fetch/decode unit2522can concurrently dispatch one micro-instruction to integer execution engine2524and another micro-instruction to floating point execution engine2526. In at least one embodiment, integer execution engine2524executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine2526executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit2522dispatches micro-instructions to a single execution engine that replaces both integer execution engine2524and floating point execution engine2526.

In at least one embodiment, each core2520(i), where i is an integer representing a particular instance of core2520, may access L2 cache2528(i) included in core2520(i). In at least one embodiment, each core2520included in core complex2510(j), where j is an integer representing a particular instance of core complex2510, is connected to other cores2520included in core complex2510(j) via L3 cache2530(j) included in core complex2510(j). In at least one embodiment, cores2520included in core complex2510(j), where j is an integer representing a particular instance of core complex2510, can access all of L3 cache2530(j) included in core complex2510(j). In at least one embodiment, L3 cache2530may include, without limitation, any number of slices.

In at least one embodiment, graphics complex2540can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, graphics complex2540is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex2540is configured to execute operations unrelated to graphics. In at least one embodiment, graphics complex2540is configured to execute both operations related to graphics and operations unrelated to graphics.

In at least one embodiment, graphics complex2540includes, without limitation, any number of compute units2550and an L2 cache2542. In at least one embodiment, compute units2550share L2 cache2542. In at least one embodiment, L2 cache2542is partitioned. In at least one embodiment, graphics complex2540includes, without limitation, any number of compute units2550and any number (including zero) and type of caches. In at least one embodiment, graphics complex2540includes, without limitation, any amount of dedicated graphics hardware.

In at least one embodiment, each compute unit2550includes, without limitation, any number of SIMD units2552and a shared memory2554. In at least one embodiment, each SIMD unit2552implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit2550may execute any number of thread blocks, but each thread block executes on a single compute unit2550. In at least one embodiment, a thread block includes, without limitation, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit2552executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory2554.

In at least one embodiment, fabric2560is a system interconnect that facilitates data and control transmissions across core complex2510, graphics complex2540, I/O interfaces2570, memory controllers2580, display controller2592, and multimedia engine2594. In at least one embodiment, APU2500may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric2560that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to APU2500. In at least one embodiment, I/O interfaces2570are representative of any number and type of I/O interfaces (e.g., PCI , PCI-Extended (“PCI-X”), PCIe, gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces2570In at least one embodiment, peripheral devices that are coupled to I/O interfaces2570may include, without limitation, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.

In at least one embodiment, display controller AMD92displays images on one or more display device(s), such as a liquid crystal display (“LCD”) device. In at least one embodiment, multimedia engine2594includes, without limitation, any amount and type of circuitry that is related to multimedia, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers2580facilitate data transfers between APU2500and a unified system memory2590. In at least one embodiment, core complex2510and graphics complex2540share unified system memory2590.

In at least one embodiment, APU2500implements a memory subsystem that includes, without limitation, any amount and type of memory controllers2580and memory devices (e.g., shared memory2554) that may be dedicated to one component or shared among multiple components. In at least one embodiment, APU2500implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches2628, L3 cache2530, and L2 cache2542) that may each be private to or shared between any number of components (e.g., cores2520, core complex2510, SIMD units2552, compute units2550, and graphics complex2540).

In at least one embodiment, at least one component shown or described with respect toFIG.25is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of core complex2510or graphics complex2540are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of core complex2510or graphics complex2540are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of core complex2510or graphics complex2540are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of core complex2510or graphics complex2540are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of core complex2510or graphics complex2540are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.26illustrates a CPU2600, in accordance with at least one embodiment. In at least one embodiment, CPU2600is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, CPU2600can be configured to execute an application program. In at least one embodiment, CPU2600is configured to execute main control software, such as an operating system. In at least one embodiment, CPU2600issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU2600can be configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU2600includes, without limitation, any number of core complexes2610, fabric2660, I/O interfaces2670, and memory controllers2680.

In at least one embodiment, core complex2610includes, without limitation, cores2620(1)-2620(4) and an L3 cache2630. In at least one embodiment, core complex2610may include, without limitation, any number of cores2620and any number and type of caches in any combination. In at least one embodiment, cores2620are configured to execute instructions of a particular ISA. In at least one embodiment, each core2620is a CPU core.

In at least one embodiment, each core2620includes, without limitation, a fetch/decode unit2622, an integer execution engine2624, a floating point execution engine2626, and an L2 cache2628. In at least one embodiment, fetch/decode unit2622fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine2624and floating point execution engine2626. In at least one embodiment, fetch/decode unit2622can concurrently dispatch one micro-instruction to integer execution engine2624and another micro-instruction to floating point execution engine2626. In at least one embodiment, integer execution engine2624executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine2626executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit2622dispatches micro-instructions to a single execution engine that replaces both integer execution engine2624and floating point execution engine2626.

In at least one embodiment, each core2620(i), where i is an integer representing a particular instance of core2620, may access L2 cache2628(i) included in core2620(i). In at least one embodiment, each core2620included in core complex2610(j), where j is an integer representing a particular instance of core complex2610, is connected to other cores2620in core complex2610(j) via L3 cache2630(j) included in core complex2610(j). In at least one embodiment, cores2620included in core complex2610(j), where j is an integer representing a particular instance of core complex2610, can access all of L3 cache2630(j) included in core complex2610(j). In at least one embodiment, L3 cache2630may include, without limitation, any number of slices.

In at least one embodiment, fabric2660is a system interconnect that facilitates data and control transmissions across core complexes2610(1)-2610(N) (where N is an integer greater than zero), I/O interfaces2670, and memory controllers2680. In at least one embodiment, CPU2600may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric2660that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to CPU2600. In at least one embodiment, I/O interfaces2670are representative of any number and type of I/O interfaces (e.g., PCI , PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces2670In at least one embodiment, peripheral devices that are coupled to I/O interfaces2670may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.

In at least one embodiment, memory controllers2680facilitate data transfers between CPU2600and a system memory2690. In at least one embodiment, core complex2610and graphics complex2640share system memory2690. In at least one embodiment, CPU2600implements a memory subsystem that includes, without limitation, any amount and type of memory controllers2680and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU2600implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches2628and L3 caches2630) that may each be private to or shared between any number of components (e.g., cores2620and core complexes2610).

In at least one embodiment, at least one component shown or described with respect toFIG.26is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of core complex2610(1)-2610(n) are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of core complex2610(1)-2610(n) are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of core complex2610(1)-2610(n) are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of core complex2610(1)-2610(n) are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of core complex2610(1)-2610(n) are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.27illustrates an exemplary accelerator integration slice2790, in accordance with at least one embodiment. As used herein, a “slice” comprises a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engines may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

An application effective address space2782within system memory2714stores process elements2783. In one embodiment, process elements2783are stored in response to GPU invocations2781from applications2780executed on processor2707. A process element2783contains process state for corresponding application2780. A work descriptor (“WD”)2784contained in process element2783can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD2784is a pointer to a job request queue in application effective address space2782.

Graphics acceleration module2746and/or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending WD2784to graphics acceleration module2746to start a job in a virtualized environment may be included.

In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module2746or an individual graphics processing engine. Because graphics acceleration module2746is owned by a single process, a hypervisor initializes an accelerator integration circuit for an owning partition and an operating system initializes accelerator integration circuit for an owning process when graphics acceleration module2746is assigned.

In operation, a WD fetch unit2791in accelerator integration slice2790fetches next WD2784which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module2746. Data from WD2784may be stored in registers2745and used by a memory management unit (“MMU”)2739, interrupt management circuit2747and/or context management circuit2748as illustrated. For example, one embodiment of MMU2739includes segment/page walk circuitry for accessing segment/page tables2786within OS virtual address space2785. Interrupt management circuit2747may process interrupt events (“INT”)2792received from graphics acceleration module2746. When performing graphics operations, an effective address2793generated by a graphics processing engine is translated to a real address by MMU2739.

In one embodiment, a same set of registers2745are duplicated for each graphics processing engine and/or graphics acceleration module2746and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in accelerator integration slice2790. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

TABLE 1Hypervisor Initialized Registers1Slice Control Register2Real Address (RA) Scheduled Processes Area Pointer3Authority Mask Override Register4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Limit6State Register7Logical Partition ID8Real address (RA) Hypervisor Accelerator Utilization Record Pointer9Storage Description Register

Exemplary registers that may be initialized by an operating system are shown in Table 2.

TABLE 2Operating System Initialized Registers1Process and Thread Identification2Effective Address (EA) Context Save/Restore Pointer3Virtual Address (VA) Accelerator Utilization Record Pointer4Virtual Address (VA) Storage Segment Table Pointer5Authority Mask6Work descriptor

In one embodiment, each WD2784is specific to a particular graphics acceleration module2746and/or a particular graphics processing engine. It contains all information required by a graphics processing engine to do work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

In at least one embodiment, at least one component shown or described with respect toFIG.27is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, processor2707is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, processor2707is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor2707is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor2707is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, processor2707is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIGS.28A-28Billustrate exemplary graphics processors, in accordance with at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processors are for use within an SoC.

FIG.28Aillustrates an exemplary graphics processor2810of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment.FIG.28Billustrates an additional exemplary graphics processor2840of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor2810ofFIG.28Ais a low power graphics processor core. In at least one embodiment, graphics processor2840ofFIG.28Bis a higher performance graphics processor core. In at least one embodiment, each of graphics processors2810,2840can be variants of graphics processor2310ofFIG.23.

In at least one embodiment, graphics processor2810includes a vertex processor2805and one or more fragment processor(s)2815A-2815N (e.g.,2815A,2815B,2815C,2815D, through2815N-1, and2815N). In at least one embodiment, graphics processor2810can execute different shader programs via separate logic, such that vertex processor2805is optimized to execute operations for vertex shader programs, while one or more fragment processor(s)2815A-2815N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor2805performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s)2815A-2815N use primitive and vertex data generated by vertex processor2805to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s)2815A-2815N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

In at least one embodiment, graphics processor2810additionally includes one or more MMU(s)2820A-2820B, cache(s)2825A-2825B, and circuit interconnect(s)2830A-2830B. In at least one embodiment, one or more MMU(s)2820A-2820B provide for virtual to physical address mapping for graphics processor2810, including for vertex processor2805and/or fragment processor(s)2815A-2815N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more cache(s)2825A-2825B. In at least one embodiment, one or more MMU(s)2820A-2820B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s)2305, image processors2315, and/or video processors2320ofFIG.23, such that each processor2305-2320can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s)2830A-2830B enable graphics processor2810to interface with other IP cores within an SoC, either via an internal bus of the SoC or via a direct connection.

In at least one embodiment, graphics processor2840includes one or more MMU(s)2820A-2820B, caches2825A-2825B, and circuit interconnects2830A-2830B of graphics processor2810ofFIG.28A. In at least one embodiment, graphics processor2840includes one or more shader core(s)2855A-2855N (e.g.,2855A,2855B,2855C,2855D,2855E,2855F, through2855N-1, and2855N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor2840includes an inter-core task manager2845, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores2855A-2855N and a tiling unit2858to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

In at least one embodiment, at least one component shown or described with respect toFIGS.28A-28Bis utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of graphics processor2810or graphics processor2840are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of graphics processor2810or graphics processor2840are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of graphics processor2810or graphics processor2840are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of graphics processor2810or graphics processor2840are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of graphics processor2810or graphics processor2840are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.29Aillustrates a graphics core2900, in accordance with at least one embodiment. In at least one embodiment, graphics core2900may be included within graphics processor2310ofFIG.23. In at least one embodiment, graphics core2900may be a unified shader core2855A-2855N as inFIG.28B. In at least one embodiment, graphics core2900includes a shared instruction cache2902, a texture unit2918, and a cache/shared memory2920that are common to execution resources within graphics core2900. In at least one embodiment, graphics core2900can include multiple slices2901A-2901N or partition for each core, and a graphics processor can include multiple instances of graphics core2900. Slices2901A-2901N can include support logic including a local instruction cache2904A-2904N, a thread scheduler2906A-2906N, a thread dispatcher2908A-2908N, and a set of registers2910A-2910N. In at least one embodiment, slices2901A-2901N can include a set of additional function units (“AFUs”)2912A-2912N, floating-point units (“FPUs”)2914A-2914N, integer arithmetic logic units (“ALUs”)2916-2916N, address computational units (“ACUs”)2913A-2913N, double-precision floating-point units (“DPFPUs”)2915A-2915N, and matrix processing units (“MPUs”)2917A-2917N.

In at least one embodiment, FPUs2914A-2914N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs2915A-2915N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs2916A-2916N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs2917A-2917N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs2917-2917N can perform a variety of matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (“GEMM”). In at least one embodiment, AFUs2912A-2912N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

FIG.29Billustrates a general-purpose graphics processing unit (“GPGPU”)2930, in accordance with at least one embodiment. In at least one embodiment, GPGPU2930is highly-parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU2930can be configured to enable highly-parallel compute operations to be performed by an array of GPUs. In at least one embodiment, GPGPU2930can be linked directly to other instances of GPGPU2930to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU2930includes a host interface2932to enable a connection with a host processor. In at least one embodiment, host interface2932is a PCIe interface. In at least one embodiment, host interface2932can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU2930receives commands from a host processor and uses a global scheduler2934to distribute execution threads associated with those commands to a set of compute clusters2936A-2936H. In at least one embodiment, compute clusters2936A-2936H share a cache memory2938. In at least one embodiment, cache memory2938can serve as a higher-level cache for cache memories within compute clusters2936A-2936H.

In at least one embodiment, GPGPU2930includes memory2944A-2944B coupled with compute clusters2936A-2936H via a set of memory controllers2942A-2942B. In at least one embodiment, memory2944A-2944B can include various types of memory devices including DRAM or graphics random access memory, such as synchronous graphics random access memory (“SGRAM”), including graphics double data rate (“GDDR”) memory.

In at least one embodiment, compute clusters2936A-2936H each include a set of graphics cores, such as graphics core2900ofFIG.29A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters2936A-2936H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU2930can be configured to operate as a compute cluster. Compute clusters2936A-2936H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU2930communicate over host interface2932. In at least one embodiment, GPGPU2930includes an I/O hub2939that couples GPGPU2930with a GPU link2940that enables a direct connection to other instances of GPGPU2930. In at least one embodiment, GPU link2940is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU2930. In at least one embodiment GPU link2940couples with a high speed interconnect to transmit and receive data to other GPGPUs2930or parallel processors. In at least one embodiment, multiple instances of GPGPU2930are located in separate data processing systems and communicate via a network device that is accessible via host interface2932. In at least one embodiment GPU link2940can be configured to enable a connection to a host processor in addition to or as an alternative to host interface2932. In at least one embodiment, GPGPU2930can be configured to execute a CUDA program.

In at least one embodiment, at least one component shown or described with respect toFIGS.29A-29Bis utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of graphics core2900or general-purpose graphics processing unit (“GPGPU”)2930are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of graphics core2900or GPGPU2930are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of graphics core2900or GPGPU2930are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of graphics core2900or GPGPU2930are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of graphics core2900or GPGPU2930are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.30Aillustrates a parallel processor3000, in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor3000may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (“ASICs”), or FPGAs.

In at least one embodiment, parallel processor3000includes a parallel processing unit3002. In at least one embodiment, parallel processing unit3002includes an I/O unit3004that enables communication with other devices, including other instances of parallel processing unit3002. In at least one embodiment, I/O unit3004may be directly connected to other devices. In at least one embodiment, I/O unit3004connects with other devices via use of a hub or switch interface, such as memory hub3005. In at least one embodiment, connections between memory hub3005and I/O unit3004form a communication link. In at least one embodiment, I/O unit3004connects with a host interface3006and a memory crossbar3016, where host interface3006receives commands directed to performing processing operations and memory crossbar3016receives commands directed to performing memory operations.

In at least one embodiment, when host interface3006receives a command buffer via I/O unit3004, host interface3006can direct work operations to perform those commands to a front end3008. In at least one embodiment, front end3008couples with a scheduler3010, which is configured to distribute commands or other work items to a processing array3012. In at least one embodiment, scheduler3010ensures that processing array3012is properly configured and in a valid state before tasks are distributed to processing array3012. In at least one embodiment, scheduler3010is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler3010is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array3012. In at least one embodiment, host software can prove workloads for scheduling on processing array3012via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array3012by scheduler3010logic within a microcontroller including scheduler3010.

In at least one embodiment, processing array3012can include up to “N” clusters (e.g., cluster3014A, cluster3014B, through cluster3014N). In at least one embodiment, each cluster3014A-3014N of processing array3012can execute a large number of concurrent threads. In at least one embodiment, scheduler3010can allocate work to clusters3014A-3014N of processing array3012using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler3010, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing array3012. In at least one embodiment, different clusters3014A-3014N of processing array3012can be allocated for processing different types of programs or for performing different types of computations.

In at least one embodiment, processing array3012can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array3012is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array3012can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.

In at least one embodiment, processing array3012is configured to perform parallel graphics processing operations. In at least one embodiment, processing array3012can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array3012can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit3002can transfer data from system memory via I/O unit3004for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., a parallel processor memory3022) during processing, then written back to system memory.

In at least one embodiment, when parallel processing unit3002is used to perform graphics processing, scheduler3010can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters3014A-3014N of processing array3012. In at least one embodiment, portions of processing array3012can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters3014A-3014N may be stored in buffers to allow intermediate data to be transmitted between clusters3014A-3014N for further processing.

In at least one embodiment, processing array3012can receive processing tasks to be executed via scheduler3010, which receives commands defining processing tasks from front end3008. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler3010may be configured to fetch indices corresponding to tasks or may receive indices from front end3008. In at least one embodiment, front end3008can be configured to ensure processing array3012is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

In at least one embodiment, each of one or more instances of parallel processing unit3002can couple with parallel processor memory3022. In at least one embodiment, parallel processor memory3022can be accessed via memory crossbar3016, which can receive memory requests from processing array3012as well as I/O unit3004. In at least one embodiment, memory crossbar3016can access parallel processor memory3022via a memory interface3018. In at least one embodiment, memory interface3018can include multiple partition units (e.g., a partition unit3020A, partition unit3020B, through partition unit3020N) that can each couple to a portion (e.g., memory unit) of parallel processor memory3022. In at least one embodiment, a number of partition units3020A-3020N is configured to be equal to a number of memory units, such that a first partition unit3020A has a corresponding first memory unit3024A, a second partition unit3020B has a corresponding memory unit3024B, and an Nth partition unit3020N has a corresponding Nth memory unit3024N. In at least one embodiment, a number of partition units3020A-3020N may not be equal to a number of memory devices.

In at least one embodiment, memory units3024A-3024N can include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, memory units3024A-3024N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units3024A-3024N, allowing partition units3020A-3020N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory3022. In at least one embodiment, a local instance of parallel processor memory3022may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

In at least one embodiment, any one of clusters3014A-3014N of processing array3012can process data that will be written to any of memory units3024A-3024N within parallel processor memory3022. In at least one embodiment, memory crossbar3016can be configured to transfer an output of each cluster3014A-3014N to any partition unit3020A-3020N or to another cluster3014A-3014N, which can perform additional processing operations on an output. In at least one embodiment, each cluster3014A-3014N can communicate with memory interface3018through memory crossbar3016to read from or write to various external memory devices. In at least one embodiment, memory crossbar3016has a connection to memory interface3018to communicate with I/O unit3004, as well as a connection to a local instance of parallel processor memory3022, enabling processing units within different clusters3014A-3014N to communicate with system memory or other memory that is not local to parallel processing unit3002. In at least one embodiment, memory crossbar3016can use virtual channels to separate traffic streams between clusters3014A-3014N and partition units3020A-3020N.

In at least one embodiment, multiple instances of parallel processing unit3002can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit3002can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit3002can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit3002or parallel processor3000can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems.

FIG.30Billustrates a processing cluster3094, in accordance with at least one embodiment. In at least one embodiment, processing cluster3094is included within a parallel processing unit. In at least one embodiment, processing cluster3094is one of processing clusters3014A-3014N ofFIG.30. In at least one embodiment, processing cluster3094can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (“SIMD”) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread (“SIMT”) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster3094.

In at least one embodiment, operation of processing cluster3094can be controlled via a pipeline manager3032that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager3032receives instructions from scheduler3010ofFIG.30and manages execution of those instructions via a graphics multiprocessor3034and/or a texture unit3036. In at least one embodiment, graphics multiprocessor3034is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster3094. In at least one embodiment, one or more instances of graphics multiprocessor3034can be included within processing cluster3094. In at least one embodiment, graphics multiprocessor3034can process data and a data crossbar3040can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager3032can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar3040.

In at least one embodiment, each graphics multiprocessor3034within processing cluster3094can include an identical set of functional execution logic (e.g., arithmetic logic units, load/store units (“LSUs”), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

In at least one embodiment, instructions transmitted to processing cluster3094constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor3034. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor3034. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor3034. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor3034, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor3034.

In at least one embodiment, graphics multiprocessor3034includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor3034can forego an internal cache and use a cache memory (e.g., L1 cache3048) within processing cluster3094. In at least one embodiment, each graphics multiprocessor3034also has access to Level 2 (“L2”) caches within partition units (e.g., partition units3020A-3020N ofFIG.30A) that are shared among all processing clusters3094and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor3034may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit3002may be used as global memory. In at least one embodiment, processing cluster3094includes multiple instances of graphics multiprocessor3034that can share common instructions and data, which may be stored in L1 cache3048.

In at least one embodiment, each processing cluster3094may include an MMU3045that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU3045may reside within memory interface3018ofFIG.30. In at least one embodiment, MMU3045includes a set of page table entries (“PTEs”) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU3045may include address translation lookaside buffers (“TLBs”) or caches that may reside within graphics multiprocessor3034or L1 cache3048or processing cluster3094. In at least one embodiment, a physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

In at least one embodiment, processing cluster3094may be configured such that each graphics multiprocessor3034is coupled to a texture unit3036for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor3034and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor3034outputs a processed task to data crossbar3040to provide the processed task to another processing cluster3094for further processing or to store the processed task in an L2 cache, a local parallel processor memory, or a system memory via memory crossbar3016. In at least one embodiment, a pre-raster operations unit (“preROP”)3042is configured to receive data from graphics multiprocessor3034, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units3020A-3020N ofFIG.30). In at least one embodiment, PreROP3042can perform optimizations for color blending, organize pixel color data, and perform address translations.

FIG.30Cillustrates a graphics multiprocessor3096, in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor3096is graphics multiprocessor3034ofFIG.30B. In at least one embodiment, graphics multiprocessor3096couples with pipeline manager3032of processing cluster3094. In at least one embodiment, graphics multiprocessor3096has an execution pipeline including but not limited to an instruction cache3052, an instruction unit3054, an address mapping unit3056, a register file3058, one or more GPGPU cores3062, and one or more LSUs3066. GPGPU cores3062and LSUs3066are coupled with cache memory3072and shared memory3070via a memory and cache interconnect3068.

In at least one embodiment, instruction cache3052receives a stream of instructions to execute from pipeline manager3032. In at least one embodiment, instructions are cached in instruction cache3052and dispatched for execution by instruction unit3054. In at least one embodiment, instruction unit3054can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core3062. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit3056can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by LSUs3066.

In at least one embodiment, register file3058provides a set of registers for functional units of graphics multiprocessor3096. In at least one embodiment, register file3058provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores3062, LSUs3066) of graphics multiprocessor3096. In at least one embodiment, register file3058is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file3058. In at least one embodiment, register file3058is divided between different thread groups being executed by graphics multiprocessor3096.

In at least one embodiment, GPGPU cores3062can each include FPUs and/or integer ALUs that are used to execute instructions of graphics multiprocessor3096. GPGPU cores3062can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores3062include a single precision FPU and an integer ALU while a second portion of GPGPU cores3062include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor3096can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores3062can also include fixed or special function logic.

In at least one embodiment, GPGPU cores3062include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores3062can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores3062can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (“SPMD”) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

In at least one embodiment, memory and cache interconnect3068is an interconnect network that connects each functional unit of graphics multiprocessor3096to register file3058and to shared memory3070. In at least one embodiment, memory and cache interconnect3068is a crossbar interconnect that allows LSU3066to implement load and store operations between shared memory3070and register file3058. In at least one embodiment, register file3058can operate at a same frequency as GPGPU cores3062, thus data transfer between GPGPU cores3062and register file3058is very low latency. In at least one embodiment, shared memory3070can be used to enable communication between threads that execute on functional units within graphics multiprocessor3096. In at least one embodiment, cache memory3072can be used as a data cache for example, to cache texture data communicated between functional units and texture unit3036. In at least one embodiment, shared memory3070can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores3062can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory3072.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on the same package or chip as cores and communicatively coupled to cores over a processor bus/interconnect that is internal to a package or a chip. In at least one embodiment, regardless of the manner in which a GPU is connected, processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.

In at least one embodiment, at least one component shown or described with respect toFIGS.30A-30Cis utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of parallel processor3000, graphics multiprocessor3034, or graphics multiprocessor3096are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of parallel processor3000, graphics multiprocessor3034, or graphics multiprocessor3096are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of parallel processor3000, graphics multiprocessor3034, or graphics multiprocessor3096are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of parallel processor3000, graphics multiprocessor3034, or graphics multiprocessor3096are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of parallel processor3000, graphics multiprocessor3034, or graphics multiprocessor3096are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.31illustrates a graphics processor3100, in accordance with at least one embodiment. In at least one embodiment, graphics processor3100includes a ring interconnect3102, a pipeline front-end3104, a media engine3137, and graphics cores3180A-3180N. In at least one embodiment, ring interconnect3102couples graphics processor3100to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor3100is one of many processors integrated within a multi-core processing system.

In at least one embodiment, graphics processor3100receives batches of commands via ring interconnect3102. In at least one embodiment, incoming commands are interpreted by a command streamer3103in pipeline front-end3104. In at least one embodiment, graphics processor3100includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s)3180A-3180N. In at least one embodiment, for 3D geometry processing commands, command streamer3103supplies commands to geometry pipeline3136. In at least one embodiment, for at least some media processing commands, command streamer3103supplies commands to a video front end3134, which couples with a media engine3137. In at least one embodiment, media engine3137includes a Video Quality Engine (“VQE”)3130for video and image post-processing and a multi-format encode/decode (“MFX”) engine3133to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline3136and media engine3137each generate execution threads for thread execution resources provided by at least one graphics core3180A.

In at least one embodiment, graphics processor3100includes scalable thread execution resources featuring modular graphics cores3180A-3180N (sometimes referred to as core slices), each having multiple sub-cores3150A-550N,3160A-3160N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor3100can have any number of graphics cores3180A through3180N. In at least one embodiment, graphics processor3100includes a graphics core3180A having at least a first sub-core3150A and a second sub-core3160A. In at least one embodiment, graphics processor3100is a low power processor with a single sub-core (e.g., sub-core3150A). In at least one embodiment, graphics processor3100includes multiple graphics cores3180A-3180N, each including a set of first sub-cores3150A-3150N and a set of second sub-cores3160A-3160N. In at least one embodiment, each sub-core in first sub-cores3150A-3150N includes at least a first set of execution units (“EUs”)3152A-3152N and media/texture samplers3154A-3154N. In at least one embodiment, each sub-core in second sub-cores3160A-3160N includes at least a second set of execution units3162A-3162N and samplers3164A-3164N. In at least one embodiment, each sub-core3150A-3150N,3160A-3160N shares a set of shared resources3170A-3170N. In at least one embodiment, shared resources3170include shared cache memory and pixel operation logic.

In at least one embodiment, at least one component shown or described with respect toFIG.31is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, graphics processor3100is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, graphics processor3100is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, graphics processor3100is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, graphics processor3100is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, graphics processor3100is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.32illustrates a processor3200, in accordance with at least one embodiment. In at least one embodiment, processor3200may include, without limitation, logic circuits to perform instructions. In at least one embodiment, processor3200may perform instructions, including x86 instructions, ARM instructions, specialized instructions for ASICs, etc. In at least one embodiment, processor3210may include registers to store packed data, such as 64-bit wide MMXTM registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany SIMD and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors3210may perform instructions to accelerate CUDA programs.

In at least one embodiment, processor3200includes an in-order front end (“front end”)3201to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end3201may include several units. In at least one embodiment, an instruction prefetcher3226fetches instructions from memory and feeds instructions to an instruction decoder3228which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder3228decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops”or “uops”) for execution. In at least one embodiment, instruction decoder3228parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations. In at least one embodiment, a trace cache3230may assemble decoded uops into program ordered sequences or traces in a uop queue3234for execution. In at least one embodiment, when trace cache3230encounters a complex instruction, a microcode ROM3232provides uops needed to complete an operation.

In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder3228may access microcode ROM3232to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder3228. In at least one embodiment, an instruction may be stored within microcode ROM3232should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache3230refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM3232. In at least one embodiment, after microcode ROM3232finishes sequencing micro-ops for an instruction, front end3201of machine may resume fetching micro-ops from trace cache3230.

In at least one embodiment, out-of-order execution engine (“out of order engine”)3203may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down a pipeline and get scheduled for execution. Out-of-order execution engine3203includes, without limitation, an allocator/register renamer3240, a memory uop queue3242, an integer/floating point uop queue3244, a memory scheduler3246, a fast scheduler3202, a slow/general floating point scheduler (“slow/general FP scheduler”)3204, and a simple floating point scheduler (“simple FP scheduler”)3206. In at least one embodiment, fast schedule3202, slow/general floating point scheduler3204, and simple floating point scheduler3206are also collectively referred to herein as “uop schedulers3202,3204,3206.” Allocator/register renamer3240allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator/register renamer3240renames logic registers onto entries in a register file. In at least one embodiment, allocator/register renamer3240also allocates an entry for each uop in one of two uop queues, memory uop queue3242for memory operations and integer/floating point uop queue3244for non-memory operations, in front of memory scheduler3246and uop schedulers3202,3204,3206. In at least one embodiment, uop schedulers3202,3204,3206, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler3202of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler3204and simple floating point scheduler3206may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers3202,3204,3206arbitrate for dispatch ports to schedule uops for execution.

In at least one embodiment, execution block3211includes, without limitation, an integer register file/bypass network3208, a floating point register file/bypass network (“FP register file/bypass network”)3210, address generation units (“AGUs”)3212and3214, fast ALUs3216and3218, a slow ALU3220, a floating point ALU (“FP”)3222, and a floating point move unit (“FP move”)3224. In at least one embodiment, integer register file/bypass network3208and floating point register file/bypass network3210are also referred to herein as “register files3208,3210.” In at least one embodiment, AGUSs3212and3214, fast ALUs3216and3218, slow ALU3220, floating point ALU3222, and floating point move unit3224are also referred to herein as “execution units3212,3214,3216,3218,3220,3222, and3224.” In at least one embodiment, an execution block may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination.

In at least one embodiment, register files3208,3210may be arranged between uop schedulers3202,3204,3206, and execution units3212,3214,3216,3218,3220,3222, and3224. In at least one embodiment, integer register file/bypass network3208performs integer operations. In at least one embodiment, floating point register file/bypass network3210performs floating point operations. In at least one embodiment, each of register files3208,3210may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files3208,3210may communicate data with each other. In at least one embodiment, integer register file/bypass network3208may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file/bypass network3210may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

In at least one embodiment, execution units3212,3214,3216,3218,3220,3222,3224may execute instructions. In at least one embodiment, register files3208,3210store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor3200may include, without limitation, any number and combination of execution units3212,3214,3216,3218,3220,3222,3224. In at least one embodiment, floating point ALU3222and floating point move unit3224may execute floating point, MMX, SIMD, AVX and SSE, or other operations. In at least one embodiment, floating point ALU3222may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs3216,3218. In at least one embodiment, fast ALUS3216,3218may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU3220as slow ALU3220may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be executed by AGUs3212,3214. In at least one embodiment, fast ALU3216, fast ALU3218, and slow ALU3220may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU3216, fast ALU3218, and slow ALU3220may be implemented to support a variety of data bit sizes including sixteen, thirty-two,128,256, etc. In at least one embodiment, floating point ALU3222and floating point move unit3224may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU3222and floating point move unit3224may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, uop schedulers3202,3204,3206dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor3200, processor3200may also include logic to handle memory misses. In at least one embodiment, if a data load misses in a data cache, there may be dependent operations in flight in pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanisms of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

In at least one embodiment, the term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of a processor (from a programmer's perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data.

In at least one embodiment, at least one component shown or described with respect toFIG.32is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, processor3200is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, processor3200is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor3200is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, processor3200is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, processor3200is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.33illustrates a processor3300, in accordance with at least one embodiment. In at least one embodiment, processor3300includes, without limitation, one or more processor cores (“cores”)3302A-3302N, an integrated memory controller3314, and an integrated graphics processor3308. In at least one embodiment, processor3300can include additional cores up to and including additional processor core3302N represented by dashed lined boxes. In at least one embodiment, each of processor cores3302A-3302N includes one or more internal cache units3304A-3304N. In at least one embodiment, each processor core also has access to one or more shared cached units3306.

In at least one embodiment, internal cache units3304A-3304N and shared cache units3306represent a cache memory hierarchy within processor3300. In at least one embodiment, cache memory units3304A-3304N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as an L2, L3, Level 4 (“L4”), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units3306and3304A-3304N.

In at least one embodiment, processor3300may also include a set of one or more bus controller units3316and a system agent core3310. In at least one embodiment, one or more bus controller units3316manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, system agent core3310provides management functionality for various processor components. In at least one embodiment, system agent core3310includes one or more integrated memory controllers3314to manage access to various external memory devices (not shown).

In at least one embodiment, one or more of processor cores3302A-3302N include support for simultaneous multi-threading. In at least one embodiment, system agent core3310includes components for coordinating and operating processor cores3302A-3302N during multi-threaded processing. In at least one embodiment, system agent core3310may additionally include a power control unit (“PCU”), which includes logic and components to regulate one or more power states of processor cores3302A-3302N and graphics processor3308.

In at least one embodiment, processor3300additionally includes graphics processor3308to execute graphics processing operations. In at least one embodiment, graphics processor3308couples with shared cache units3306, and system agent core3310, including one or more integrated memory controllers3314. In at least one embodiment, system agent core3310also includes a display controller3311to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller3311may also be a separate module coupled with graphics processor3308via at least one interconnect, or may be integrated within graphics processor3308.

In at least one embodiment, a ring based interconnect unit3312is used to couple internal components of processor3300. In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor3308couples with ring interconnect3312via an I/O link3313.

In at least one embodiment, I/O link3313represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module3318, such as an eDRAM module. In at least one embodiment, each of processor cores3302A-3302N and graphics processor3308use embedded memory modules3318as a shared LLC.

In at least one embodiment, processor cores3302A-3302N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores3302A-3302N are heterogeneous in terms of ISA, where one or more of processor cores3302A-3302N execute a common instruction set, while one or more other cores of processor cores3302A-33-02N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores3302A-3302N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more cores having a lower power consumption. In at least one embodiment, processor3300can be implemented on one or more chips or as an SoC integrated circuit.

In at least one embodiment, at least one component shown or described with respect toFIG.33is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of processor3300or graphics processor3308are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of processor3300or graphics processor3308are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of processor3300or graphics processor3308are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of processor3300or graphics processor3308are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of processor3300or graphics processor3308are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.34illustrates a graphics processor core3400, in accordance with at least one embodiment described. In at least one embodiment, graphics processor core3400is included within a graphics core array. In at least one embodiment, graphics processor core3400, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core3400is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core3400can include a fixed function block3430coupled with multiple sub-cores3401A-3401F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.

In at least one embodiment, fixed function block3430includes a geometry/fixed function pipeline3436that can be shared by all sub-cores in graphics processor3400, for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, geometry/fixed function pipeline3436includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers.

In at least one embodiment, fixed function block3430also includes a graphics SoC interface3437, a graphics microcontroller3438, and a media pipeline3439. Graphics SoC interface3437provides an interface between graphics core3400and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller3438is a programmable sub-processor that is configurable to manage various functions of graphics processor3400, including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline3439includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline3439implements media operations via requests to compute or sampling logic within sub-cores3401-3401F.

In at least one embodiment, SoC interface3437enables graphics core3400to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared LLC memory, system RAM, and/or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface3437can also enable communication with fixed function devices within an SoC, such as camera imaging pipelines, and enables use of and/or implements global memory atomics that may be shared between graphics core3400and CPUs within an SoC. In at least one embodiment, SoC interface3437can also implement power management controls for graphics core3400and enable an interface between a clock domain of graphic core3400and other clock domains within an SoC. In at least one embodiment, SoC interface3437enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline3439, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline3436, geometry and fixed function pipeline3414) when graphics processing operations are to be performed.

In at least one embodiment, graphics microcontroller3438can be configured to perform various scheduling and management tasks for graphics core3400. In at least one embodiment, graphics microcontroller3438can perform graphics and/or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays3402A-3402F,3404A-3404F within sub-cores3401A-3401F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core3400can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller3438can also facilitate low-power or idle states for graphics core3400, providing graphics core3400with an ability to save and restore registers within graphics core3400across low-power state transitions independently from an operating system and/or graphics driver software on a system.

In at least one embodiment, graphics core3400may have greater than or fewer than illustrated sub-cores3401A-3401F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core3400can also include shared function logic3410, shared and/or cache memory3412, a geometry/fixed function pipeline3414, as well as additional fixed function logic3416to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic3410can include logic units (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within graphics core3400. Shared and/or cache memory3412can be an LLC for N sub-cores3401A-3401F within graphics core3400and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry/fixed function pipeline3414can be included instead of geometry/fixed function pipeline3436within fixed function block3430and can include same or similar logic units.

In at least one embodiment, graphics core3400includes additional fixed function logic3416that can include various fixed function acceleration logic for use by graphics core3400. In at least one embodiment, additional fixed function logic3416includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry/fixed function pipeline3416,3436, and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic3416. In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic3416can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as a cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, a cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, a full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase.

In at least one embodiment, additional fixed function logic3416can also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for accelerating CUDA programs.

In at least one embodiment, each graphics sub-core3401A-3401F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores3401A-3401F include multiple EU arrays3402A-3402F,3404A-3404F, thread dispatch and inter-thread communication (“TD/IC”) logic3403A-3403F, a 3D (e.g., texture) sampler3405A-3405F, a media sampler3406A-3406F, a shader processor3407A-3407F, and shared local memory (“SLM”)3408A-3408F. EU arrays3402A-3402F,3404A-3404F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD/IC logic3403A-3403F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler3405A-3405F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler3406A-3406F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core3401A-3401F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores3401A-3401F can make use of shared local memory3408A-3408F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

In at least one embodiment, at least one component shown or described with respect toFIG.34is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of graphics processor core3400is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of graphics processor core3400is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of graphics processor core3400is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of graphics processor core3400is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of graphics processor core3400is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.35illustrates a parallel processing unit (“PPU”)3500, in accordance with at least one embodiment. In at least one embodiment, PPU3500is configured with machine-readable code that, if executed by PPU3500, causes PPU3500to perform some or all of processes and techniques described herein. In at least one embodiment, PPU3500is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU3500. In at least one embodiment, PPU3500is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as an LCD device. In at least one embodiment, PPU3500is utilized to perform computations such as linear algebra operations and machine-learning operations.FIG.35illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment.

In at least one embodiment, one or more PPUs3500are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs3500are configured to accelerate CUDA programs. In at least one embodiment, PPU3500includes, without limitation, an I/O unit3506, a front-end unit3510, a scheduler unit3512, a work distribution unit3514, a hub3516, a crossbar (“Xbar”)3520, one or more general processing clusters (“GPCs”)3518, and one or more partition units (“memory partition units”)3522. In at least one embodiment, PPU3500is connected to a host processor or other PPUs3500via one or more high-speed GPU interconnects (“GPU interconnects”)3508. In at least one embodiment, PPU3500is connected to a host processor or other peripheral devices via a system bus or interconnect3502. In at least one embodiment, PPU3500is connected to a local memory comprising one or more memory devices (“memory”)3504. In at least one embodiment, memory devices3504include, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device.

In at least one embodiment, high-speed GPU interconnect3508may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs3500combined with one or more CPUs, supports cache coherence between PPUs3500and CPUs, and CPU mastering. In at least one embodiment, data and/or commands are transmitted by high-speed GPU interconnect3508through hub3516to/from other units of PPU3500such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated inFIG.35.

In at least one embodiment, I/O unit3506is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated inFIG.35) over system bus3502. In at least one embodiment, I/O unit3506communicates with host processor directly via system bus3502or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I/O unit3506may communicate with one or more other processors, such as one or more of PPUs3500via system bus3502. In at least one embodiment, I/O unit3506implements a PCIe interface for communications over a PCIe bus. In at least one embodiment, I/O unit3506implements interfaces for communicating with external devices.

In at least one embodiment, I/O unit3506decodes packets received via system bus3502. In at least one embodiment, at least some packets represent commands configured to cause PPU3500to perform various operations. In at least one embodiment, I/O unit3506transmits decoded commands to various other units of PPU3500as specified by commands. In at least one embodiment, commands are transmitted to front-end unit3510and/or transmitted to hub3516or other units of PPU3500such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated inFIG.35). In at least one embodiment, I/O unit3506is configured to route communications between and among various logical units of PPU3500.

In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU3500for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible (e.g., read/write) by both a host processor and PPU3500—a host interface unit may be configured to access buffer in a system memory connected to system bus3502via memory requests transmitted over system bus3502by I/O unit3506. In at least one embodiment, a host processor writes a command stream to a buffer and then transmits a pointer to the start of the command stream to PPU3500such that front-end unit3510receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU3500.

In at least one embodiment, front-end unit3510is coupled to scheduler unit3512that configures various GPCs3518to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit3512is configured to track state information related to various tasks managed by scheduler unit3512where state information may indicate which of GPCs3518a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit3512manages execution of a plurality of tasks on one or more of GPCs3518.

In at least one embodiment, scheduler unit3512is coupled to work distribution unit3514that is configured to dispatch tasks for execution on GPCs3518. In at least one embodiment, work distribution unit3514tracks a number of scheduled tasks received from scheduler unit3512and work distribution unit3514manages a pending task pool and an active task pool for each of GPCs3518. In at least one embodiment, pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC3518; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs3518such that as one of GPCs3518completes execution of a task, that task is evicted from active task pool for GPC3518and one of other tasks from pending task pool is selected and scheduled for execution on GPC3518. In at least one embodiment, if an active task is idle on GPC3518, such as while waiting for a data dependency to be resolved, then the active task is evicted from GPC3518and returned to a pending task pool while another task in the pending task pool is selected and scheduled for execution on GPC3518.

In at least one embodiment, work distribution unit3514communicates with one or more GPCs3518via XBar3520. In at least one embodiment, XBar3520is an interconnect network that couples many units of PPU3500to other units of PPU3500and can be configured to couple work distribution unit3514to a particular GPC3518. In at least one embodiment, one or more other units of PPU3500may also be connected to XBar3520via hub3516.

In at least one embodiment, tasks are managed by scheduler unit3512and dispatched to one of GPCs3518by work distribution unit3514. GPC3518is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC3518, routed to a different GPC3518via XBar3520, or stored in memory3504. In at least one embodiment, results can be written to memory3504via partition units3522, which implement a memory interface for reading and writing data to/from memory3504. In at least one embodiment, results can be transmitted to another PPU3504or CPU via high-speed GPU interconnect3508. In at least one embodiment, PPU3500includes, without limitation, a number U of partition units3522that is equal to number of separate and distinct memory devices3504coupled to PPU3500.

In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on host processor to schedule operations for execution on PPU3500. In at least one embodiment, multiple compute applications are simultaneously executed by PPU3500and PPU3500provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver kernel to generate one or more tasks for execution by PPU3500and the driver kernel outputs tasks to one or more streams being processed by PPU3500. In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads including instructions to perform a task and that exchange data through shared memory.

In at least one embodiment, at least one component shown or described with respect toFIG.35is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, parallel processing unit3500is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, parallel processing unit3500is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, parallel processing unit3500is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, parallel processing unit3500is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, parallel processing unit3500is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.36illustrates a GPC3600, in accordance with at least one embodiment. In at least one embodiment, GPC3600is GPC3518ofFIG.35. In at least one embodiment, each GPC3600includes, without limitation, a number of hardware units for processing tasks and each GPC3600includes, without limitation, a pipeline manager3602, a pre-raster operations unit (“PROP”)3604, a raster engine3608, a work distribution crossbar (“WDX”)3616, an MMU3618, one or more Data Processing Clusters (“DPCs”)3606, and any suitable combination of parts.

In at least one embodiment, operation of GPC3600is controlled by pipeline manager3602. In at least one embodiment, pipeline manager3602manages configuration of one or more DPCs3606for processing tasks allocated to GPC3600. In at least one embodiment, pipeline manager3602configures at least one of one or more DPCs3606to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC3606is configured to execute a vertex shader program on a programmable streaming multiprocessor (“SM”)3614. In at least one embodiment, pipeline manager3602is configured to route packets received from a work distribution unit to appropriate logical units within GPC3600and, in at least one embodiment, some packets may be routed to fixed function hardware units in PROP3604and/or raster engine3608while other packets may be routed to DPCs3606for processing by a primitive engine3612or SM3614. In at least one embodiment, pipeline manager3602configures at least one of DPCs3606to implement a computing pipeline. In at least one embodiment, pipeline manager3602configures at least one of DPCs3606to execute at least a portion of a CUDA program.

In at least one embodiment, PROP unit3604is configured to route data generated by raster engine3608and DPCs3606to a Raster Operations (“ROP”) unit in a partition unit, such as memory partition unit3522described in more detail above in conjunction withFIG.35. In at least one embodiment, PROP unit3604is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine3608includes, without limitation, a number of fixed function hardware units configured to perform various raster operations and, in at least one embodiment, raster engine3608includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, a setup engine receives transformed vertices and generates plane equations associated with geometric primitive defined by vertices; plane equations are transmitted to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for a primitive; the output of the coarse raster engine is transmitted to a culling engine where fragments associated with a primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to a fine raster engine to generate attributes for pixel fragments based on plane equations generated by a setup engine. In at least one embodiment, the output of raster engine3608comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within DPC3606.

In at least one embodiment, each DPC3606included in GPC3600comprise, without limitation, an M-Pipe Controller (“MPC”)3610; primitive engine3612; one or more SMs3614; and any suitable combination thereof. In at least one embodiment, MPC3610controls operation of DPC3606, routing packets received from pipeline manager3602to appropriate units in DPC3606. In at least one embodiment, packets associated with a vertex are routed to primitive engine3612, which is configured to fetch vertex attributes associated with vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM3614.

In at least one embodiment, SM3614comprises, without limitation, a programmable streaming processor that is configured to process tasks represented by a number of threads. In at least one embodiment, SM3614is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a SIMD architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on same set of instructions. In at least one embodiment, all threads in group of threads execute same instructions. In at least one embodiment, SM3614implements a SIMT architecture wherein each thread in a group of threads is configured to process a different set of data based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, a call stack, and an execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within a warp diverge. In another embodiment, a program counter, a call stack, and an execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In at least one embodiment, an execution state is maintained for each individual thread and threads executing the same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM3614is described in more detail in conjunction withFIG.37.

In at least one embodiment, MMU3618provides an interface between GPC3600and a memory partition unit (e.g., partition unit3522ofFIG.35) and MMU3618provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU3618provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in memory.

In at least one embodiment, at least one component shown or described with respect toFIG.36is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, general processing cluster3600is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, general processing cluster3600is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, general processing cluster3600is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, general processing cluster3600is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, general processing cluster3600is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.37illustrates a streaming multiprocessor (“SM”)3700, in accordance with at least one embodiment. In at least one embodiment, SM3700is SM3614ofFIG.36. In at least one embodiment, SM3700includes, without limitation, an instruction cache3702; one or more scheduler units3704; a register file3708; one or more processing cores (“cores”)3710; one or more special function units (“SFUs”)3712; one or more LSUs3714; an interconnect network3716; a shared memory/L1 cache3718; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on GPCs of parallel processing units (PPUs) and each task is allocated to a particular Data Processing Cluster (DPC) within a GPC and, if a task is associated with a shader program, then the task is allocated to one of SMs3700. In at least one embodiment, scheduler unit3704receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM3700. In at least one embodiment, scheduler unit3704schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit3704manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores3710, SFUs3712, and LSUs3714) during each clock cycle.

In at least one embodiment, “cooperative groups” may refer to a programming model for organizing groups of communicating threads that allows developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative launch APIs support synchronization amongst thread blocks for execution of parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads at smaller than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, cooperative groups enable programmers to define groups of threads explicitly at sub-block and multi-block granularities, and to perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, a sub-block granularity is as small as a single thread. In at least one embodiment, a programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

In at least one embodiment, a dispatch unit3706is configured to transmit instructions to one or more of functional units and scheduler unit3704includes, without limitation, two dispatch units3706that enable two different instructions from same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit3704includes a single dispatch unit3706or additional dispatch units3706.

In at least one embodiment, each SM3700, in at least one embodiment, includes, without limitation, register file3708that provides a set of registers for functional units of SM3700. In at least one embodiment, register file3708is divided between each of the functional units such that each functional unit is allocated a dedicated portion of register file3708. In at least one embodiment, register file3708is divided between different warps being executed by SM3700and register file3708provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM3700comprises, without limitation, a plurality of L processing cores3710. In at least one embodiment, SM3700includes, without limitation, a large number (e.g., 128 or more) of distinct processing cores3710. In at least one embodiment, each processing core3710includes, without limitation, a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores3710include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

In at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores3710. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiply uses 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with other intermediate products for a 4×4×4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as a CUDA-C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, a warp-level interface assumes 16×16 size matrices spanning all 32 threads of a warp.

In at least one embodiment, each SM3700comprises, without limitation, M SFUs3712that perform special functions (e.g., attribute evaluation, reciprocal square root, and like). In at least one embodiment, SFUs3712include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs3712include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to produce sampled texture values for use in shader programs executed by SM3700. In at least one embodiment, texture maps are stored in shared memory/L1 cache3718. In at least one embodiment, texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In at least one embodiment, each SM3700includes, without limitation, two texture units.

In at least one embodiment, each SM3700comprises, without limitation, N LSUs3714that implement load and store operations between shared memory/L1 cache3718and register file3708. In at least one embodiment, each SM3700includes, without limitation, interconnect network3716that connects each of the functional units to register file3708and LSU3714to register file3708and shared memory/L1 cache3718. In at least one embodiment, interconnect network3716is a crossbar that can be configured to connect any of the functional units to any of the registers in register file3708and connect LSUs3714to register file3708and memory locations in shared memory/L1 cache3718.

In at least one embodiment, shared memory/L1 cache3718is an array of on-chip memory that allows for data storage and communication between SM3700and a primitive engine and between threads in SM3700. In at least one embodiment, shared memory/L1 cache3718comprises, without limitation, 128 KB of storage capacity and is in a path from SM3700to a partition unit. In at least one embodiment, shared memory/L1 cache3718is used to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache3718, L2 cache, and memory are backing stores.

In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of capacity, texture and load/store operations can use remaining capacity. In at least one embodiment, integration within shared memory/L1 cache3718enables shared memory/L1 cache3718to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In at least one embodiment, fixed function GPUs are bypassed, creating a much simpler programming model. In at least one embodiment and in a general purpose parallel computation configuration, a work distribution unit assigns and distributes blocks of threads directly to DPCs. In at least one embodiment, threads in a block execute the same program, using a unique thread ID in a calculation to ensure each thread generates unique results, using SM3700to execute a program and perform calculations, shared memory/L1 cache3718to communicate between threads, and LSU3714to read and write global memory through shared memory/L1 cache3718and a memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM3700writes commands that scheduler unit3704can use to launch new work on DPCs.

In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), a PDA, a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in an SoC along with one or more other devices such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter (“DAC”), and like.

In at least one embodiment, PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, a graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU may be an integrated GPU (“iGPU”) included in chipset of motherboard.

In at least one embodiment, at least one component shown or described with respect toFIG.37is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, streaming multiprocessor3700is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, streaming multiprocessor3700is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, streaming multiprocessor3700is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, streaming multiprocessor3700is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, streaming multiprocessor3700is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

Software Constructions for General-Purpose Computing

The following figures set forth, without limitation, exemplary software constructs for implementing at least one embodiment.

FIG.38illustrates a software stack of a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. A programming platform may be accessible to software developers through libraries, compiler directives, and/or extensions to programming languages, in at least one embodiment. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by Khronos group), SYCL, or Intel One API.

In at least one embodiment, a software stack3800of a programming platform provides an execution environment for an application3801. In at least one embodiment, application3801may include any computer software capable of being launched on software stack3800. In at least one embodiment, application3801may include, but is not limited to, an artificial intelligence (“AI”)/machine learning (“ML”) application, a high performance computing (“HPC”) application, a virtual desktop infrastructure (“VDI”), or a data center workload.

In at least one embodiment, application3801and software stack3800run on hardware3807. Hardware3807may include one or more GPUs, CPUs, FPGAs, AI engines, and/or other types of compute devices that support a programming platform, in at least one embodiment. In at least one embodiment, such as with CUDA, software stack3800may be vendor specific and compatible with only devices from particular vendor(s). In at least one embodiment, such as in with OpenCL, software stack3800may be used with devices from different vendors. In at least one embodiment, hardware3807includes a host connected to one more devices that can be accessed to perform computational tasks via application programming interface (“API”) calls. A device within hardware3807may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory, as opposed to a host within hardware3807that may include, but is not limited to, a CPU (but may also include a compute device) and its memory, in at least one embodiment.

In at least one embodiment, software stack3800of a programming platform includes, without limitation, a number of libraries3803, a runtime3805, and a device kernel driver3806. Each of libraries3803may include data and programming code that can be used by computer programs and leveraged during software development, in at least one embodiment. In at least one embodiment, libraries3803may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and/or message templates. In at least one embodiment, libraries3803include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries3803may include, but are not limited to, functions for performing mathematical, deep learning, and/or other types of operations on devices. In at least one embodiment, libraries3803are associated with corresponding APIs3802, which may include one or more APIs, that expose functions implemented in libraries3803.

In at least one embodiment, application3801is written as source code that is compiled into executable code, as discussed in greater detail below in conjunction withFIGS.43-45. Executable code of application3801may run, at least in part, on an execution environment provided by software stack3800, in at least one embodiment. In at least one embodiment, during execution of application3801, code may be reached that needs to run on a device, as opposed to a host. In such a case, runtime3805may be called to load and launch requisite code on the device, in at least one embodiment. In at least one embodiment, runtime3805may include any technically feasible runtime system that is able to support execution of application S01.

In at least one embodiment, runtime3805is implemented as one or more runtime libraries associated with corresponding APIs, which are shown as API(s)3804. One or more of such runtime libraries may include, without limitation, functions for memory management, execution control, device management, error handling, and/or synchronization, among other things, in at least one embodiment. In at least one embodiment, memory management functions may include, but are not limited to, functions to allocate, deallocate, and copy device memory, as well as transfer data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions to launch a function (sometimes referred to as a “kernel” when a function is a global function callable from a host) on a device and set attribute values in a buffer maintained by a runtime library for a given function to be executed on a device.

Runtime libraries and corresponding API(s)3804may be implemented in any technically feasible manner, in at least one embodiment. In at least one embodiment, one (or any number of) API may expose a low-level set of functions for fine-grained control of a device, while another (or any number of) API may expose a higher-level set of such functions. In at least one embodiment, a high-level runtime API may be built on top of a low-level API. In at least one embodiment, one or more of runtime APIs may be language-specific APIs that are layered on top of a language-independent runtime API.

In at least one embodiment, device kernel driver3806is configured to facilitate communication with an underlying device. In at least one embodiment, device kernel driver3806may provide low-level functionalities upon which APIs, such as API(s)3804, and/or other software relies. In at least one embodiment, device kernel driver3806may be configured to compile intermediate representation (“IR”) code into binary code at runtime. For CUDA, device kernel driver3806may compile Parallel Thread Execution (“PTX”) IR code that is not hardware specific into binary code for a specific target device at runtime (with caching of compiled binary code), which is also sometimes referred to as “finalizing” code, in at least one embodiment. Doing so may permit finalized code to run on a target device, which may not have existed when source code was originally compiled into PTX code, in at least one embodiment. Alternatively, in at least one embodiment, device source code may be compiled into binary code offline, without requiring device kernel driver3806to compile IR code at runtime.

In at least one embodiment, at least one component shown or described with respect toFIG.38is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of software stack3800of a programming platform is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of software stack3800of a programming platform is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of software stack3800of a programming platform is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of software stack3800of a programming platform is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of software stack3800of a programming platform is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.39illustrates a CUDA implementation of software stack3800ofFIG.38, in accordance with at least one embodiment. In at least one embodiment, a CUDA software stack3900, on which an application3901may be launched, includes CUDA libraries3903, a CUDA runtime3905, a CUDA driver3907, and a device kernel driver3908. In at least one embodiment, CUDA software stack3900executes on hardware3909, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, Calif.

In at least one embodiment, application3901, CUDA runtime3905, and device kernel driver3908may perform similar functionalities as application3801, runtime3805, and device kernel driver3806, respectively, which are described above in conjunction withFIG.38. In at least one embodiment, CUDA driver3907includes a library (libcuda.so) that implements a CUDA driver API3906. Similar to a CUDA runtime API3904implemented by a CUDA runtime library (cudart), CUDA driver API3906may, without limitation, expose functions for memory management, execution control, device management, error handling, synchronization, and/or graphics interoperability, among other things, in at least one embodiment. In at least one embodiment, CUDA driver API3906differs from CUDA runtime API3904in that CUDA runtime API3904simplifies device code management by providing implicit initialization, context (analogous to a process) management, and module (analogous to dynamically loaded libraries) management. In contrast to high-level CUDA runtime API3904, CUDA driver API3906is a low-level API providing more fine-grained control of the device, particularly with respect to contexts and module loading, in at least one embodiment. In at least one embodiment, CUDA driver API3906may expose functions for context management that are not exposed by CUDA runtime API3904. In at least one embodiment, CUDA driver API3906is also language-independent and supports, e.g., OpenCL in addition to CUDA runtime API3904. Further, in at least one embodiment, development libraries, including CUDA runtime3905, may be considered as separate from driver components, including user-mode CUDA driver3907and kernel-mode device driver3908(also sometimes referred to as a “display” driver).

In at least one embodiment, CUDA libraries3903may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and/or signal/image/video processing libraries, which parallel computing applications such as application3901may utilize. In at least one embodiment, CUDA libraries3903may include mathematical libraries such as a cuBLAS library that is an implementation of Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA libraries3903may include deep learning libraries such as a cuDNN library of primitives for deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

In at least one embodiment, at least one component shown or described with respect toFIG.39is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of CUDA software stack3900is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of CUDA software stack3900is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of CUDA software stack3900is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of CUDA software stack3900is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of CUDA software stack3900is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.40illustrates a ROCm implementation of software stack3800ofFIG.38, in accordance with at least one embodiment. In at least one embodiment, a ROCm software stack4000, on which an application4001may be launched, includes a language runtime4003, a system runtime4005, a thunk4007, and a ROCm kernel driver4008. In at least one embodiment, ROCm software stack4000executes on hardware4009, which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, Calif.

In at least one embodiment, application4001may perform similar functionalities as application3801discussed above in conjunction withFIG.38. In addition, language runtime4003and system runtime4005may perform similar functionalities as runtime3805discussed above in conjunction withFIG.38, in at least one embodiment. In at least one embodiment, language runtime4003and system runtime4005differ in that system runtime4005is a language-independent runtime that implements a ROCr system runtime API4004and makes use of a Heterogeneous System Architecture (“HSA”) Runtime API. HSA runtime API is a thin, user-mode API that exposes interfaces to access and interact with an AMD GPU, including functions for memory management, execution control via architected dispatch of kernels, error handling, system and agent information, and runtime initialization and shutdown, among other things, in at least one embodiment. In contrast to system runtime4005, language runtime4003is an implementation of a language-specific runtime API4002layered on top of ROCr system runtime API4004, in at least one embodiment. In at least one embodiment, language runtime API may include, but is not limited to, a Heterogeneous compute Interface for Portability (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. HIP language in particular is an extension of C++ programming language with functionally similar versions of CUDA mechanisms, and, in at least one embodiment, a HIP language runtime API includes functions that are similar to those of CUDA runtime API3904discussed above in conjunction withFIG.39, such as functions for memory management, execution control, device management, error handling, and synchronization, among other things.

In at least one embodiment, thunk (ROCt)4007is an interface4006that can be used to interact with underlying ROCm driver4008. In at least one embodiment, ROCm driver4008is a ROCk driver, which is a combination of an AMDGPU driver and a HSA kernel driver (amdkfd). In at least one embodiment, AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs similar functionalities as device kernel driver3806discussed above in conjunction withFIG.38. In at least one embodiment, HSA kernel driver is a driver permitting different types of processors to share system resources more effectively via hardware features.

In at least one embodiment, various libraries (not shown) may be included in ROCm software stack4000above language runtime4003and provide functionality similarity to CUDA libraries3903, discussed above in conjunction withFIG.39. In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and/or other libraries such as a hipBLAS library that implements functions similar to those of CUDA cuBLAS, a rocFFT library for computing FFTs that is similar to CUDA cuFFT, among others.

In at least one embodiment, at least one component shown or described with respect toFIG.40is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of ROCm software stack4000is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of ROCm software stack4000is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of ROCm software stack4000is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment at least one element of ROCm software stack4000is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of ROCm software stack4000is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.41illustrates an OpenCL implementation of software stack3800ofFIG.38, in accordance with at least one embodiment. In at least one embodiment, an OpenCL software stack4100, on which an application4101may be launched, includes an OpenCL framework4110, an OpenCL runtime4106, and a driver4107. In at least one embodiment, OpenCL software stack4100executes on hardware3909that is not vendor-specific. As OpenCL is supported by devices developed by different vendors, specific OpenCL drivers may be required to interoperate with hardware from such vendors, in at least one embodiment.

In at least one embodiment, application4101, OpenCL runtime4106, device kernel driver4107, and hardware4108may perform similar functionalities as application3801, runtime3805, device kernel driver3806, and hardware3807, respectively, that are discussed above in conjunction withFIG.38. In at least one embodiment, application4101further includes an OpenCL kernel4102with code that is to be executed on a device.

In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to the host. In at least one embodiment, an OpenCL framework provides a platform layer API and a runtime API, shown as platform API4103and runtime API4105. In at least one embodiment, runtime API4105uses contexts to manage execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, which runtime API4105may use to manage command queues, program objects, and kernel objects, share memory objects, among other things, for that device. In at least one embodiment, platform API4103exposes functions that permit device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices, among other things. In addition, OpenCL framework provides various built-in functions (not shown), including math functions, relational functions, and image processing functions, among others, in at least one embodiment.

In at least one embodiment, a compiler4104is also included in OpenCL frame-work4110. Source code may be compiled offline prior to executing an application or online during execution of an application, in at least one embodiment. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler4104, which is included to be representative of any number of compilers that may be used to compile source code and/or IR code, such as Standard Portable Intermediate Representation (“SPIR-V”) code, into binary code. Alternatively, in at least one embodiment, OpenCL ap-plications may be compiled offline, prior to execution of such applications.

In at least one embodiment, at least one component shown or described with respect toFIG.41is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of OpenCL software stack4100is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of OpenCL software stack4100is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of OpenCL software stack4100is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of OpenCL software stack4100is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of OpenCL software stack4100is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.42illustrates software that is supported by a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform4204is configured to support various programming models4203, middlewares and/or libraries4202, and frameworks4201that an application4200may rely upon. In at least one embodiment, application4200may be an AI/ML application implemented using, for example, a deep learning framework such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and/or NVIDA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computing on underlying hardware.

In at least one embodiment, programming platform4204may be one of a CUDA, ROCm, or OpenCL platform described above in conjunction withFIG.39,FIG.40, andFIG.41, respectively. In at least one embodiment, programming platform4204supports multiple programming models4203, which are abstractions of an underlying computing system permitting expressions of algorithms and data structures. Programming models4203may expose features of underlying hardware in order to improve performance, in at least one embodiment. In at least one embodiment, programming models4203may include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and/or Vulcan Compute.

In at least one embodiment, libraries and/or middlewares4202provide implementations of abstractions of programming models4204. In at least one embodiment, such libraries include data and programming code that may be used by computer programs and leveraged during software development. In at least one embodiment, such middlewares include software that provides services to applications beyond those available from programming platform4204. In at least one embodiment, libraries and/or middlewares4202may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. In addition, in at least one embodiment, libraries and/or middlewares4202may include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries providing communication routines for GPUs, a MIOpen library for deep learning acceleration, and/or an Eigen library for linear algebra, matrix and vector operations, geometrical transformations, numerical solvers, and related algorithms.

In at least one embodiment, application frameworks4201depend on libraries and/or middlewares4202. In at least one embodiment, each of application frameworks4201is a software framework used to implement a standard structure of application software. Returning to the AI/ML example discussed above, an AI/ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks, in at least one embodiment.

In at least one embodiment, at least one component shown or described with respect toFIG.42is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least element of application4200is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least element of application4200is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least element of application4200is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least element of application4200is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least element of application4200is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.43illustrates compiling code to execute on one of programming platforms ofFIGS.38-41, in accordance with at least one embodiment. In at least one embodiment, a compiler4301receives source code4300that includes both host code as well as device code. In at least one embodiment, complier4301is configured to convert source code4300into host executable code4302for execution on a host and device executable code4303for execution on a device. In at least one embodiment, source code4300may either be compiled offline prior to execution of an application, or online during execution of an application.

In at least one embodiment, source code4300may include code in any programming language supported by compiler4301, such as C++, C, Fortran, etc. In at least one embodiment, source code4300may be included in a single-source file having a mixture of host code and device code, with locations of device code being indicated therein. In at least one embodiment, a single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code4300may include multiple source code files, rather than a single-source file, into which host code and device code are separated.

In at least one embodiment, compiler4301is configured to compile source code4300into host executable code4302for execution on a host and device executable code4303for execution on a device. In at least one embodiment, compiler4301performs operations including parsing source code4300into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code4300includes a single-source file, compiler4301may separate device code from host code in such a single-source file, compile device code and host code into device executable code4303and host executable code4302, respectively, and link device executable code4303and host executable code4302together in a single file, as discussed in greater detail below with respect toFIG.44.

In at least one embodiment, host executable code4302and device executable code4303may be in any suitable format, such as binary code and/or IR code. In the case of CUDA, host executable code4302may include native object code and device executable code4303may include code in PTX intermediate representation, in at least one embodiment. In the case of ROCm, both host executable code4302and device executable code4303may include target binary code, in at least one embodiment.

In at least one embodiment, at least one component shown or described with respect toFIG.43is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of host executable code4302or device executable code4303specified in source code4300are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of host executable code4302or device executable code4303specified in source code4300are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of host executable code4302or device executable code4303specified in source code4300are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of host executable code4302or device executable code4303specified in source code4300are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of host executable code4302or device executable code4303specified in source code4300are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.44is a more detailed illustration of compiling code to execute on one of programming platforms ofFIGS.38-41, in accordance with at least one embodiment. In at least one embodiment, a compiler4401is configured to receive source code4400, compile source code4400, and output an executable file4410. In at least one embodiment, source code4400is a single-source file, such as a .cu file, a .hip.cpp file, or a file in another format, that includes both host and device code. In at least one embodiment, compiler4401may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or a HCC compiler for compiling HIP code in .hip.cpp files.

In at least one embodiment, compiler4401includes a compiler front end4402, a host compiler4405, a device compiler4406, and a linker4409. In at least one embodiment, compiler front end4402is configured to separate device code4404from host code4403in source code4400. Device code4404is compiled by device compiler4406into device executable code4408, which as described may include binary code or IR code, in at least one embodiment. Separately, host code4403is compiled by host compiler4405into host executable code4407, in at least one embodiment. For NVCC, host compiler4405may be, but is not limited to, a general purpose C/C++ compiler that outputs native object code, while device compiler4406may be, but is not limited to, a Low Level Virtual Machine (“LLVM”)-based compiler that forks a LLVM compiler infrastructure and outputs PTX code or binary code, in at least one embodiment. For HCC, both host compiler4405and device compiler4406may be, but are not limited to, LLVM-based compilers that output target binary code, in at least one embodiment.

Subsequent to compiling source code4400into host executable code4407and device executable code4408, linker4409links host and device executable code4407and4408together in executable file4410, in at least one embodiment. In at least one embodiment, native object code for a host and PTX or binary code for a device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code.

In at least one embodiment, at least one component shown or described with respect toFIG.44is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, executable file4410specified in source code4400is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, executable file4410specified in source code4400is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, executable file4410specified in source code4400is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, executable file4410specified in source code4400is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, executable file4410specified in source code4400is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.45illustrates translating source code prior to compiling source code, in accordance with at least one embodiment. In at least one embodiment, source code4500is passed through a translation tool4501, which translates source code4500into translated source code4502. In at least one embodiment, a compiler4503is used to compile translated source code4502into host executable code4504and device executable code4505in a process that is similar to compilation of source code4300by compiler4301into host executable code4302and device executable4303, as discussed above in conjunction withFIG.43.

In at least one embodiment, a translation performed by translation tool4501is used to port source4500for execution in a different environment than that in which it was originally intended to run. In at least one embodiment, translation tool4501may include, but is not limited to, a HIP translator that is used to “hipify” CUDA code intended for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, translation of source code4500may include parsing source code4500and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as discussed in greater detail below in conjunction withFIGS.46A-47. Returning to the example of hipifying CUDA code, calls to CUDA runtime API, CUDA driver API, and/or CUDA libraries may be converted to corresponding HIP API calls, in at least one embodiment. In at least one embodiment, automated translations performed by translation tool4501may sometimes be incomplete, requiring additional, manual effort to fully port source code4500.

In at least one embodiment, at least one component shown or described with respect toFIG.45is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of host executable code4504or device executable code4505specified in source code4500are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of host executable code4504or device executable code4505specified in source code4500are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of host executable code4504or device executable code4505specified in source code4500are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of host executable code4504or device executable code4505specified in source code4500are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of host executable code4504or device executable code4505specified in source code4500are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

Configuring GPUs for General-Purpose Computing

The following figures set forth, without limitation, exemplary architectures for compiling and executing compute source code, in accordance with at least one embodiment.

FIG.46Aillustrates a system4600configured to compile and execute CUDA source code4610using different types of processing units, in accordance with at least one embodiment. In at least one embodiment, system4600includes, without limitation, CUDA source code4610, a CUDA compiler4650, host executable code4670(1), host executable code4670(2), CUDA device executable code4684, a CPU4690, a CUDA-enabled GPU4694, a GPU4692, a CUDA to HIP translation tool4620, HIP source code4630, a HIP compiler driver4640, an HCC4660, and HCC device executable code4682.

In at least one embodiment, CUDA source code4610is a collection of human-readable code in a CUDA programming language. In at least one embodiment, CUDA code is human-readable code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable in parallel on a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU4690, GPU46192, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU4690.

In at least one embodiment, CUDA source code4610includes, without limitation, any number (including zero) of global functions4612, any number (including zero) of device functions4614, any number (including zero) of host functions4616, and any number (including zero) of host/device functions4618. In at least one embodiment, global functions4612, device functions4614, host functions4616, and host/device functions4618may be mixed in CUDA source code4610. In at least one embodiment, each of global functions4612is executable on a device and callable from a host. In at least one embodiment, one or more of global functions4612may therefore act as entry points to a device. In at least one embodiment, each of global functions4612is a kernel. In at least one embodiment and in a technique known as dynamic parallelism, one or more of global functions4612defines a kernel that is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N (where N is any positive integer) times in parallel by N different threads on a device during execution.

In at least one embodiment, each of device functions4614is executed on a device and callable from such a device only. In at least one embodiment, each of host functions4616is executed on a host and callable from such a host only. In at least one embodiment, each of host/device functions4616defines both a host version of a function that is executable on a host and callable from such a host only and a device version of the function that is executable on a device and callable from such a device only.

In at least one embodiment, CUDA source code4610may also include, without limitation, any number of calls to any number of functions that are defined via a CUDA runtime API4602. In at least one embodiment, CUDA runtime API4602may include, without limitation, any number of functions that execute on a host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code4610may also include any number of calls to any number of functions that are specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API that is designed for use by CUDA code. In at least one embodiment, CUDA APIs include, without limitation, CUDA runtime API4602, a CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment and relative to CUDA runtime API4602, a CUDA driver API is a lower-level API but provides finer-grained control of a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

In at least one embodiment, CUDA compiler4650compiles input CUDA code (e.g., CUDA source code4610) to generate host executable code4670(1) and CUDA device executable code4684. In at least one embodiment, CUDA compiler4650is NVCC. In at least one embodiment, host executable code4670(1) is a compiled version of host code included in input source code that is executable on CPU4690. In at least one embodiment, CPU4690may be any processor that is optimized for sequential instruction processing.

In at least one embodiment, CUDA device executable code4684is a compiled version of device code included in input source code that is executable on CUDA-enabled GPU4694. In at least one embodiment, CUDA device executable code4684includes, without limitation, binary code. In at least one embodiment, CUDA device executable code4684includes, without limitation, IR code, such as PTX code, that is further compiled at runtime into binary code for a specific target device (e.g., CUDA-enabled GPU4694) by a device driver. In at least one embodiment, CUDA-enabled GPU4694may be any processor that is optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, CUDA-enabled GPU4694is developed by NVIDIA Corporation of Santa Clara, Calif.

In at least one embodiment, CUDA to HIP translation tool4620is configured to translate CUDA source code4610to functionally similar HIP source code4630. In a least one embodiment, HIP source code4630is a collection of human-readable code in a HIP programming language. In at least one embodiment, HIP code is human-readable code in a HIP programming language. In at least one embodiment, a HIP programming language is an extension of the C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a HIP programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, for example, a HIP programming language includes, without limitation, mechanism(s) to define global functions4612, but such a HIP programming language may lack support for dynamic parallelism and therefore global functions4612defined in HIP code may be callable from a host only.

In at least one embodiment, HIP source code4630includes, without limitation, any number (including zero) of global functions4612, any number (including zero) of device functions4614, any number (including zero) of host functions4616, and any number (including zero) of host/device functions4618. In at least one embodiment, HIP source code4630may also include any number of calls to any number of functions that are specified in a HIP runtime API4632. In at least one embodiment, HIP runtime API4632includes, without limitation, functionally similar versions of a subset of functions included in CUDA runtime API4602. In at least one embodiment, HIP source code4630may also include any number of calls to any number of functions that are specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API that is designed for use by HIP code and/or ROCm. In at least one embodiment, HIP APIs include, without limitation, HIP runtime API4632, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

In at least one embodiment, CUDA to HIP translation tool4620converts each kernel call in CUDA code from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, CUDA to HIP translation tool4620converts any number of calls to functions specified in CUDA runtime API4602to any number of calls to functions specified in HIP runtime API4632.

In at least one embodiment, CUDA to HIP translation tool4620is a tool known as hipify-perl that executes a text-based translation process. In at least one embodiment, CUDA to HIP translation tool4620is a tool known as hipify-clang that, relative to hipify-perl, executes a more complex and more robust translation process that involves parsing CUDA code using clang (a compiler front-end) and then translating resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual edits) in addition to those performed by CUDA to HIP translation tool4620.

In at least one embodiment, HIP compiler driver4640is a front end that determines a target device4646and then configures a compiler that is compatible with target device4646to compile HIP source code4630. In at least one embodiment, target device4646is a processor that is optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver4640may determine target device4646in any technically feasible fashion.

In at least one embodiment, if target device4646is compatible with CUDA (e.g., CUDA-enabled GPU4694), then HIP compiler driver4640generates a HIP/NVCC compilation command4642. In at least one embodiment and as described in greater detail in conjunction withFIG.46B, HIP/NVCC compilation command4642configures CUDA compiler4650to compile HIP source code4630using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command4642, CUDA compiler4650generates host executable code4670(1) and CUDA device executable code4684.

In at least one embodiment, if target device4646is not compatible with CUDA, then HIP compiler driver4640generates a HIP/HCC compilation command4644. In at least one embodiment and as described in greater detail in conjunction withFIG.46C, HIP/HCC compilation command4644configures HCC4660to compile HIP source code4630using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command4644, HCC4660generates host executable code4670(2) and HCC device executable code4682. In at least one embodiment, HCC device executable code4682is a compiled version of device code included in HIP source code4630that is executable on GPU4692. In at least one embodiment, GPU4692may be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, GPU4692is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment GPU,4692is a non-CUDA-enabled GPU4692.

For explanatory purposes only, three different flows that may be implemented in at least one embodiment to compile CUDA source code4610for execution on CPU4690and different devices are depicted inFIG.46A. In at least one embodiment, a direct CUDA flow compiles CUDA source code4610for execution on CPU4690and CUDA-enabled GPU4694without translating CUDA source code4610to HIP source code4630. In at least one embodiment, an indirect CUDA flow translates CUDA source code4610to HIP source code4630and then compiles HIP source code4630for execution on CPU4690and CUDA-enabled GPU4694. In at least one embodiment, a CUDA/HCC flow translates CUDA source code4610to HIP source code4630and then compiles HIP source code4630for execution on CPU4690and GPU4692.

A direct CUDA flow that may be implemented in at least one embodiment is depicted via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment and as depicted with bubble annotated A1, CUDA compiler4650receives CUDA source code4610and a CUDA compile command4648that configures CUDA compiler4650to compile CUDA source code4610. In at least one embodiment, CUDA source code4610used in a direct CUDA flow is written in a CUDA programming language that is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment and in response to CUDA compile command4648, CUDA compiler4650generates host executable code4670(1) and CUDA device executable code4684(depicted with bubble annotated A2). In at least one embodiment and as depicted with bubble annotated A3, host executable code4670(1) and CUDA device executable code4684may be executed on, respectively, CPU4690and CUDA-enabled GPU4694. In at least one embodiment, CUDA device executable code4684includes, without limitation, binary code. In at least one embodiment, CUDA device executable code4684includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

An indirect CUDA flow that may be implemented in at least one embodiment is depicted via dotted lines and a series of bubbles annotated B1-B6. In at least one embodiment and as depicted with bubble annotated B1, CUDA to HIP translation tool4620receives CUDA source code4610. In at least one embodiment and as depicted with bubble annotated B2, CUDA to HIP translation tool4620translates CUDA source code4610to HIP source code4630. In at least one embodiment and as depicted with bubble annotated B3, HIP compiler driver4640receives HIP source code4630and determines that target device4646is CUDA-enabled.

In at least one embodiment and as depicted with bubble annotated B4, HIP compiler driver4640generates HIP/NVCC compilation command4642and transmits both HIP/NVCC compilation command4642and HIP source code4630to CUDA compiler4650. In at least one embodiment and as described in greater detail in conjunction withFIG.46B, HIP/NVCC compilation command4642configures CUDA compiler4650to compile HIP source code4630using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command4642, CUDA compiler4650generates host executable code4670(1) and CUDA device executable code4684(depicted with bubble annotated B5). In at least one embodiment and as depicted with bubble annotated B6, host executable code4670(1) and CUDA device executable code4684may be executed on, respectively, CPU4690and CUDA-enabled GPU4694. In at least one embodiment, CUDA device executable code4684includes, without limitation, binary code. In at least one embodiment, CUDA device executable code4684includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

A CUDA/HCC flow that may be implemented in at least one embodiment is depicted via solid lines and a series of bubbles annotated C1-C6. In at least one embodiment and as depicted with bubble annotated C1, CUDA to HIP translation tool4620receives CUDA source code4610. In at least one embodiment and as depicted with bubble annotated C2, CUDA to HIP translation tool4620translates CUDA source code4610to HIP source code4630. In at least one embodiment and as depicted with bubble annotated C3, HIP compiler driver4640receives HIP source code4630and determines that target device4646is not CUDA-enabled.

In at least one embodiment, HIP compiler driver4640generates HIP/HCC compilation command4644and transmits both HIP/HCC compilation command4644and HIP source code4630to HCC4660(depicted with bubble annotated C4). In at least one embodiment and as described in greater detail in conjunction withFIG.46C, HIP/HCC compilation command4644configures HCC4660to compile HIP source code4630using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command4644, HCC4660generates host executable code4670(2) and HCC device executable code4682(depicted with bubble annotated C5). In at least one embodiment and as depicted with bubble annotated C6, host executable code4670(2) and HCC device executable code4682may be executed on, respectively, CPU4690and GPU4692.

In at least one embodiment, after CUDA source code4610is translated to HIP source code4630, HIP compiler driver4640may subsequently be used to generate executable code for either CUDA-enabled GPU4694or GPU4692without re-executing CUDA to HIP translation tool4620. In at least one embodiment, CUDA to HIP translation tool4620translates CUDA source code4610to HIP source code4630that is then stored in memory. In at least one embodiment, HIP compiler driver4640then configures HCC4660to generate host executable code4670(2) and HCC device executable code4682based on HIP source code4630. In at least one embodiment, HIP compiler driver4640subsequently configures CUDA compiler4650to generate host executable code4670(1) and CUDA device executable code4684based on stored HIP source code4630.

FIG.46Billustrates a system4604configured to compile and execute CUDA source code4610ofFIG.46Ausing CPU4690and CUDA-enabled GPU4694, in accordance with at least one embodiment. In at least one embodiment, system4604includes, without limitation, CUDA source code4610, CUDA to HIP translation tool4620, HIP source code4630, HIP compiler driver4640, CUDA compiler4650, host executable code4670(1), CUDA device executable code4684, CPU4690, and CUDA-enabled GPU4694.

In at least one embodiment and as described previously herein in conjunction withFIG.46A, CUDA source code4610includes, without limitation, any number (including zero) of global functions4612, any number (including zero) of device functions4614, any number (including zero) of host functions4616, and any number (including zero) of host/device functions4618. In at least one embodiment, CUDA source code4610also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP translation tool4620translates CUDA source code4610to HIP source code4630. In at least one embodiment, CUDA to HIP translation tool4620converts each kernel call in CUDA source code4610from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA source code4610to any number of other functionally similar HIP calls.

In at least one embodiment, HIP compiler driver4640determines that target device4646is CUDA-enabled and generates HIP/NVCC compilation command4642. In at least one embodiment, HIP compiler driver4640then configures CUDA compiler4650via HIP/NVCC compilation command4642to compile HIP source code4630. In at least one embodiment, HIP compiler driver4640provides access to a HIP to CUDA translation header4652as part of configuring CUDA compiler4650. In at least one embodiment, HIP to CUDA translation header4652translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler4650uses HIP to CUDA translation header4652in conjunction with a CUDA runtime library4654corresponding to CUDA runtime API4602to generate host executable code4670(1) and CUDA device executable code4684. In at least one embodiment, host executable code4670(1) and CUDA device executable code4684may then be executed on, respectively, CPU4690and CUDA-enabled GPU4694. In at least one embodiment, CUDA device executable code4684includes, without limitation, binary code. In at least one embodiment, CUDA device executable code4684includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

FIG.46Cillustrates a system4606configured to compile and execute CUDA source code4610ofFIG.46Ausing CPU4690and non-CUDA-enabled GPU4692, in accordance with at least one embodiment. In at least one embodiment, system4606includes, without limitation, CUDA source code4610, CUDA to HIP translation tool4620, HIP source code4630, HIP compiler driver4640, HCC4660, host executable code4670(2), HCC device executable code4682, CPU4690, and GPU4692.

In at least one embodiment and as described previously herein in conjunction withFIG.46A, CUDA source code4610includes, without limitation, any number (including zero) of global functions4612, any number (including zero) of device functions4614, any number (including zero) of host functions4616, and any number (including zero) of host/device functions4618. In at least one embodiment, CUDA source code4610also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP translation tool4620translates CUDA source code4610to HIP source code4630. In at least one embodiment, CUDA to HIP translation tool4620converts each kernel call in CUDA source code4610from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in source code4610to any number of other functionally similar HIP calls.

In at least one embodiment, HIP compiler driver4640subsequently determines that target device4646is not CUDA-enabled and generates HIP/HCC compilation command4644. In at least one embodiment, HIP compiler driver4640then configures HCC4660to execute HIP/HCC compilation command4644to compile HIP source code4630. In at least one embodiment, HIP/HCC compilation command4644configures HCC4660to use, without limitation, a HIP/HCC runtime library4658and an HCC header4656to generate host executable code4670(2) and HCC device executable code4682. In at least one embodiment, HIP/HCC runtime library4658corresponds to HIP runtime API4632. In at least one embodiment, HCC header4656includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code4670(2) and HCC device executable code4682may be executed on, respectively, CPU4690and GPU4692.

In at least one embodiment, at least one component shown or described with respect toFIGS.46A-46Cis utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one element of system4600, system4604, or system4606is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one element of system4600, system4604, or system4606is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of system4600, system4604, or system4606is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one element of system4600, system4604, or system4606is used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one element of system4600, system4604, or system4606is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.47illustrates an exemplary kernel translated by CUDA-to-HIP translation tool4620ofFIG.46C, in accordance with at least one embodiment. In at least one embodiment, CUDA source code4610partitions an overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can independently be solved using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub-problem is partitioned into relatively fine pieces that can be solved cooperatively in parallel by threads within a thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.

In at least one embodiment, CUDA source code4610organizes thread blocks associated with a given kernel into a one-dimensional, a two-dimensional, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and a grid includes, without limitation, any number of thread blocks.

In at least one embodiment, a kernel is a function in device code that is defined using a “_global_” declaration specifier. In at least one embodiment, the dimension of a grid that executes a kernel for a given kernel call and associated streams are specified using a CUDA kernel launch syntax4710. In at least one embodiment, CUDA kernel launch syntax4710is specified as “KernelName<<<GridSize, BlockSize, SharedMemorySize, Stream>>>(KernelArguments);.” In at least one embodiment, an execution configuration syntax is a “<<< . . . >>>” construct that is inserted between a kernel name (“KernelName”) and a parenthesized list of kernel arguments (“KernelArguments”). In at least one embodiment, CUDA kernel launch syntax4710includes, without limitation, a CUDA launch function syntax instead of an execution configuration syntax.

In at least one embodiment, “GridSize” is of a type dim3and specifies the dimension and size of a grid. In at least one embodiment, type dim3is a CUDA-defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, then z defaults to one. In at least one embodiment, if y is not specified, then y defaults to one. In at least one embodiment, the number of thread blocks in a grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, “BlockSize” is of type dim3and specifies the dimension and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread that executes a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., “threadIdx”).

In at least one embodiment and with respect to CUDA kernel launch syntax4710, “SharedMemorySize” is an optional argument that specifies a number of bytes in a shared memory that is dynamically allocated per thread block for a given kernel call in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax4710, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax4710, “Stream” is an optional argument that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order with respect to one another or concurrently.

In at least one embodiment, CUDA source code4610includes, without limitation, a kernel definition for an exemplary kernel “MatAdd” and a main function. In at least one embodiment, main function is host code that executes on a host and includes, without limitation, a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment and as shown, kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, main function defines a threadsPerBlock variable as 16 by 16 and a numBlocks variable as N/16 by N/16. In at least one embodiment, main function then specifies kernel call “MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);.” In at least one embodiment and as per CUDA kernel launch syntax4710, kernel MatAdd is executed using a grid of thread blocks having a dimension N/16 by N/16, where each thread block has a dimension of 16 by 16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in such a grid executes kernel MatAdd to perform one pair-wise addition.

In at least one embodiment, while translating CUDA source code4610to HIP source code4630, CUDA to HIP translation tool4620translates each kernel call in CUDA source code4610from CUDA kernel launch syntax4710to a HIP kernel launch syntax4720and converts any number of other CUDA calls in source code4610to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax4720is specified as “hipLaunchKernelGGL(KernelName,GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);.” In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax4720as in CUDA kernel launch syntax4710(described previously herein). In at least one embodiment, arguments SharedMemorySize and Stream are required in HIP kernel launch syntax4720and are optional in CUDA kernel launch syntax4710.

In at least one embodiment, a portion of HIP source code4630depicted inFIG.47is identical to a portion of CUDA source code4610depicted inFIG.47except for a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment, kernel MatAdd is defined in HIP source code4630with the same “_global_” declaration specifier with which kernel MatAdd is defined in CUDA source code4610. In at least one embodiment, a kernel call in HIP source code4630is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);,” while a corresponding kernel call in CUDA source code4610is “MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);.”

FIG.48illustrates non-CUDA-enabled GPU4692ofFIG.46Cin greater detail, in accordance with at least one embodiment. In at least one embodiment, GPU4692is developed by AMD corporation of Santa Clara. In at least one embodiment, GPU4692can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, GPU4692is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, GPU4692is configured to execute operations unrelated to graphics. In at least one embodiment, GPU4692is configured to execute both operations related to graphics and operations unrelated to graphics. In at least one embodiment, GPU4692can be configured to execute device code included in HIP source code4630.

In at least one embodiment, GPU4692includes, without limitation, any number of programmable processing units4820, a command processor4810, an L2 cache4822, memory controllers4870, DMA engines4880(1), system memory controllers4882, DMA engines4880(2), and GPU controllers4884. In at least one embodiment, each programmable processing unit4820includes, without limitation, a workload manager4830and any number of compute units4840. In at least one embodiment, command processor4810reads commands from one or more command queues (not shown) and distributes commands to workload managers4830. In at least one embodiment, for each programmable processing unit4820, associated workload manager4830distributes work to compute units4840included in programmable processing unit4820. In at least one embodiment, each compute unit4840may execute any number of thread blocks, but each thread block executes on a single compute unit4840. In at least one embodiment, a workgroup is a thread block.

In at least one embodiment, each compute unit4840includes, without limitation, any number of SIMD units4850and a shared memory4860. In at least one embodiment, each SIMD unit4850implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit4850includes, without limitation, a vector ALU4852and a vector register file4854. In at least one embodiment, each SIMD unit4850executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory4860.

In at least one embodiment, programmable processing units4820are referred to as “shader engines.” In at least one embodiment, each programmable processing unit4820includes, without limitation, any amount of dedicated graphics hardware in addition to compute units4840. In at least one embodiment, each programmable processing unit4820includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back ends, workload manager4830, and any number of compute units4840.

In at least one embodiment, compute units4840share L2 cache4822. In at least one embodiment, L2 cache4822is partitioned. In at least one embodiment, a GPU memory4890is accessible by all compute units4840in GPU4692. In at least one embodiment, memory controllers4870and system memory controllers4882facilitate data transfers between GPU4692and a host, and DMA engines4880(1) enable asynchronous memory transfers between GPU4692and such a host. In at least one embodiment, memory controllers4870and GPU controllers4884facilitate data transfers between GPU4692and other GPUs4692, and DMA engines4880(2) enable asynchronous memory transfers between GPU4692and other GPUs4692.

In at least one embodiment, GPU4692includes, without limitation, any amount and type of system interconnect that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to GPU4692. In at least one embodiment, GPU4692includes, without limitation, any number and type of I/O interfaces (e.g., PCIe) that are coupled to any number and type of peripheral devices. In at least one embodiment, GPU4692may include, without limitation, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU4692implements a memory subsystem that includes, without limitation, any amount and type of memory controllers (e.g., memory controllers4870and system memory controllers4882) and memory devices (e.g., shared memories4860) that may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU4692implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache4822) that may each be private to or shared between any number of components (e.g., SIMD units4850, compute units4840, and programmable processing units4820).

In at least one embodiment, at least one component shown or described with respect toFIG.48is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one of GPU4692or programmable processing units4820are used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one of GPU4692or programmable processing units4820are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of GPU4692or programmable processing units4820are used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one of GPU4692or programmable processing units4820are used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one of GPU4692or programmable processing units4820are used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.49illustrates how threads of an exemplary CUDA grid4920are mapped to different compute units4840ofFIG.48, in accordance with at least one embodiment. In at least one embodiment and for explanatory purposes only, grid4920has a GridSize of BX by BY by 1 and a BlockSize of TX by TY by 1. In at least one embodiment, grid4920therefore includes, without limitation, (BX*BY) thread blocks4930and each thread block4930includes, without limitation, (TX*TY) threads4940. Threads4940are depicted inFIG.49as squiggly arrows.

In at least one embodiment, grid4920is mapped to programmable processing unit4820(1) that includes, without limitation, compute units4840(1)-4840(C). In at least one embodiment and as shown, (BJ*BY) thread blocks4930are mapped to compute unit4840(1), and the remaining thread blocks4930are mapped to compute unit4840(2). In at least one embodiment, each thread block4930may include, without limitation, any number of warps, and each warp is mapped to a different SIMD unit4850ofFIG.48.

In at least one embodiment, warps in a given thread block4930may synchronize together and communicate through shared memory4860included in associated compute unit4840. For example and in at least one embodiment, warps in thread block4930(BJ,1) can synchronize together and communicate through shared memory4860(1). For example and in at least one embodiment, warps in thread block4930(BJ+1,1) can synchronize together and communicate through shared memory4860(2).

In at least one embodiment, at least one component shown or described with respect toFIG.49is utilized to implement techniques and/or functions described in connection withFIGS.1-18. In at least one embodiment, at least one thread of exemplary CUDA grid4920is used to perform asynchronous memory allocation and/or asynchronous memory deallocation. In at least one embodiment, at least one thread of exemplary CUDA grid4920is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one thread of exemplary CUDA grid4920is used to perform an API to cause one or more memory locations to be asynchronously allocated to one or more processors. In at least one embodiment, at least one thread of exemplary CUDA grid4920is used used to perform an API to cause one or more memory locations to be asynchronously deallocated from one or more processors. In at least one embodiment, at least one thread of exemplary CUDA grid4920is used to perform at least one aspect described with respect to example computer system100, example computer system200, example computer system300, example computer system400, example process500, example process600, example process700, example process800, example data flow900, example first part of a data flow1000, example second part of a data flow1100, example third part of a data flow1200, example process1300, example computer system1400, example computer system1500, example process1600, example computer system1700, and/or example process1800.

FIG.50illustrates how to migrate existing CUDA code to Data Parallel C++ code, in accordance with at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture proprietary languages that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for a specific accelerator. DPC++ use similar and/or identical C and C++ constructs in accordance with ISO C++ which developers may be familiar with. DPC++ incorporates standard SYCL from The Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on underlying concepts, portability and efficiency of OpenCL that enables code for heterogeneous processors to be written in a “single-source” style using standard C++. SYCL may enable single source development where C++ template functions can contain both host and device code to construct complex algorithms that use OpenCL acceleration, and then re-use them throughout their source code on different types of data.

In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code which can be deployed across diverse hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across diverse hardware targets and a DPC++ compatibility tool can be used to migrate CUDA applications to a multiplatform program in DPC++. In at least one embodiment, a DPC++ base tool kit includes a DPC++ compiler to deploy applications across diverse hardware targets; a DPC++ library to increase productivity and performance across CPUs, GPUs, and FPGAs; a DPC++ compatibility tool to migrate CUDA applications to multi-platform applications; and any suitable combination thereof.

In at least one embodiment, a DPC++ programming model is utilized to simply one or more aspects relating to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. DPC++ programming language may be utilized to code reuse for hosts (e.g., a CPU) and accelerators (e.g., a GPU or FPGA) using a single source language, with execution and memory dependencies being clearly communicated. Mappings within DPC++ code can be used to transition an application to run on a hardware or set of hardware devices that best accelerates a workload. A host may be available to simplify development and debugging of device code, even on platforms that do not have an accelerator available.

In at least one embodiment, CUDA source code5000is provided as an input to a DPC++ compatibility tool5002to generate human readable DPC++5004. In at least one embodiment, human readable DPC++5004includes inline comments generated by DPC++ compatibility tool5002that guides a developer on how and/or where to modify DPC++ code to complete coding and tuning to desired performance5006, thereby generating DPC++ source code5008.

In at least one embodiment, CUDA source code5000is or includes a collection of human-readable source code in a CUDA programming language. In at least one embodiment, CUDA source code5000is human-readable source code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., GPU or FPGA) and may include or more parallelizable workflows that can be executed on one or more processor cores of a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU, GPU, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In least one embodiment, some or all of host code and device code can be executed in parallel across a CPU and GPU/FPGA. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU. CUDA source code5000described in connection withFIG.50may be in accordance with those discussed elsewhere in this document.

In at least one embodiment, DPC++ compatibility tool5002refers to an executable tool, program, application, or any other suitable type of tool that is used to facilitate migration of CUDA source code5000to DPC++ source code5008. In at least one embodiment, DPC++ compatibility tool5002is a command-line-based code migration tool available as part of a DPC++ tool kit that is used to port existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool5002converts some or all source code of a CUDA application from CUDA to DPC++ and generates a resulting file that is written at least partially in DPC++, referred to as human readable DPC++5004. In at least one embodiment, human readable DPC++5004includes comments that are generated by DPC++ compatibility tool5002to indicate where user intervention may be necessary. In at least one embodiment, user intervention is necessary when CUDA source code5000calls a CUDA API that has no analogous DPC++ API; other examples where user intervention is required are discussed later in greater detail.

In at least one embodiment, a workflow for migrating CUDA source code5000(e.g., application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using a DPC++ compatibility tool5002; completing migration and verifying correctness, thereby generating DPC++ source code5008; and compiling DPC++ source code5008with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, a compatibility tool provides a utility that intercepts commands used when Makefile executes and stores them in a compilation database file. In at least one embodiment, a file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile command to a DPC compatibility command.

In at least one embodiment, intercept-build is a utility script that intercepts a build process to capture compilation options, macro defs, and include paths, and writes this data to a compilation database file. In at least one embodiment, a compilation database file is a JSON file. In at least one embodiment, DPC++ compatibility tool5002parses a compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional, but highly recommended for Make or CMake based environments. In at least one embodiment, a migration database includes commands, directories, and files: command may include necessary compilation flags; directory may include paths to header files; file may include paths to CUDA files.

In at least one embodiment, DPC++ compatibility tool5002migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ wherever possible. In at least one embodiment, DPC++ compatibility tool5002is available as part of a tool kit. In at least one embodiment, a DPC++ tool kit includes an intercept-build tool. In at least one embodiment, an intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, a compilation database generated by an intercept-built tool is used by DPC++ compatibility tool5002to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool5002generates human readable DPC++5004which may be DPC++ code that, as generated by DPC++ compatibility tool5002, cannot be compiled by DPC++ compiler and requires additional plumbing for verifying portions of code that were not migrated correctly, and may involve manual intervention, such as by a developer. In at least one embodiment, DPC++ compatibility tool5002provides hints or tools embedded in code to help developers manually migrate additional code that could not be migrated automatically. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

In at least one embodiment, DPC++ compatibility tool50002is able to successfully migrate all portions of CUDA code to DPC++ and there may simply be an optional step for manually verifying and tuning performance of DPC++ source code that was generated. In at least one embodiment, DPC++ compatibility tool5002directly generates DPC++ source code5008which is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify DPC++ code generated by DPC++ compatibility tool5002. In at least one embodiment, DPC++ compatibility tool generates compile-able DPC++ code which can be optionally tuned by a developer for performance, readability, maintainability, other various considerations; or any combination thereof.

In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files at least partially using DPC++ compatibility tool5002. In at least one embodiment, CUDA source code includes one or more header files which may include CUDA header files. In at least one embodiment, a CUDA source file includes a <cuda.h> header file and a <stdio.h> header file which can be used to print text. In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:

In at least one embodiment and in connection with CUDA source file presented above, DPC++ compatibility tool5002parses a CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, DPC++ header files includes helper declarations. In CUDA, there is a concept of a thread ID and correspondingly, in DPC++ or SYCL, for each element there is a local identifier.

In at least one embodiment and in connection with CUDA source file presented above, there are two vectors A and B which are initialized and a vector addition result is put into vector C as part of VectorAddKernel( ). In at least one embodiment, DPC++ compatibility tool5002converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via a local ID as part of migrating CUDA code to DPC++ code. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool5002can be optimized—for example, by reducing dimensionality of an nd_item, thereby increasing memory and/or processor utilization.

In at least one embodiment and in connection with CUDA source file presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc( ) is migrated to a unified shared memory SYCL call malloc device( ) to which a device and context is passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device may have multiple queues to which jobs can be submitted; each device may have a context; and a context may have multiple devices and manage shared memory objects.

In at least one embodiment and in connection with CUDA source file presented above, a main( ) function invokes or calls VectorAddKernel( ) to add two vectors A and B together and store result in vector C. In at least one embodiment, CUDA code to invoke VectorAddKernel( ) is replaced by DPC++ code to submit a kernel to a command queue for execution. In at least one embodiment, a command group handler cgh passes data, synchronization, and computation that is submitted to the queue, parallel_for is called for a number of global elements and a number of work items in that work group where VectorAddKernel( ) is called.

In at least one embodiment and in connection with CUDA source file presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating point variables) is migrated as is, without being modified by DPC++ compatibility tool5002. In at least one embodiment, DPC++ compatibility tool5002modify CUDA APIs for memory setup and/or host calls to execute kernel on the acceleration device. In at least one embodiment and in connection with CUDA source file presented above, a corresponding human readable DPC++5004(e.g., which can be compiled) is written as or related to:

In at least one embodiment, human readable DPC++5004refers to output generated by DPC++ compatibility tool5002and may be optimized in one manner or another. In at least one embodiment, human readable DPC++5004generated by DPC++ compatibility tool5002can be manually edited by a developer after migration to make it more maintainable, performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool50002such as DPC++ disclosed can be optimized by removing repeat calls to get current device( ) and/or get default context( ) for each malloc_device( ) call. In at least one embodiment, DPC++ code generated above uses a 3 dimensional nd_range which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer can manually edit DPC++ code generated by DPC++ compatibility tool5002replace uses of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool5002has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool5002is verbose because it is using a general template to migrate CUDA code to DPC++ code that works for a large number of cases.

In at least one embodiment, a CUDA to DPC++ migration workflow includes steps to: prepare for migration using intercept-build script; perform migration of CUDA projects to DPC++ using DPC++ compatibility tool5002; review and edit migrated source files manually for completion and correctness; and compile final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of DPC++ source code may be required in one or more scenarios including but not limited to: migrated API does not return error code (CUDA code can return an error code which can then be consumed by the application but SYCL uses exceptions to report errors, and therefore does not use error codes to surface errors); CUDA compute capability dependent logic is not supported by DPC++; statement could not be removed. In at least one embodiment, scenarios in which DPC++ code requires manual intervention may include, without limitation: error code logic replaced with (*,0) code or commented out; equivalent DPC++ API not available; CUDA compute capability-dependent logic; hardware-dependent API (clock( ); missing features unsupported API; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS API; and more.

In at least one embodiment, one or more techniques described herein utilize a oneAPI programming model. In at least one embodiment, a oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, a DPC++ programming language is based at least in part on C and/or C++ programming languages. In at least one embodiment, a oneAPI programming model is a programming model such as those developed by Intel Corporation of Santa Clara, Calif.

In at least one embodiment, oneAPI and/or oneAPI programming model is utilized to interact with various accelerator, GPU, processor, and/or variations thereof, architectures. In at least one embodiment, oneAPI includes a set of libraries that implement various functionalities. In at least one embodiment, oneAPI includes at least a oneAPI DPC++ library, a oneAPI math kernel library, a oneAPI data analytics library, a oneAPI deep neural network library, a oneAPI collective communications library, a oneAPI threading building blocks library, a oneAPI video processing library, and/or variations thereof.

In at least one embodiment, a oneAPI DPC++ library, also referred to as oneDPL, is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions such as parallel algorithms, iterators, function object classes, range-based API, and/or variations thereof. In at least one embodiment, oneDPL implements one or more classes and/or functions of a C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

In at least one embodiment, a oneAPI math kernel library, also referred to as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and/or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and/or linear algebra package (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions.

In at least one embodiment, a oneAPI data analytics library, also referred to as oneDAL, is a library that implements various data analysis applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, validation, and decision making for data analytics, in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and/or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to a traditional C++ interface and enables GPU usage for various algorithms.

In at least one embodiment, a oneAPI deep neural network library, also referred to as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and/or variations thereof.

In at least one embodiment, a oneAPI collective communications library, also referred to as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built upon lower-level communication middleware, such as message passing interface (MPI) and libfabrics. In at least one embodiment, oneCCL enables a set of deep learning specific optimizations, such as prioritization, persistent operations, out of order executions, and/or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU functions.

In at least one embodiment, a oneAPI threading building blocks library, also referred to as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based, shared parallel programming on a host. In at least one embodiment, oneTBB implements generic parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and usable on various processors, such as GPUs, PPUs, CPUs, and/or variations thereof.

In at least one embodiment, a oneAPI video processing library, also referred to as oneVPL, is a library that is utilized for accelerating video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language is a programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a DPC++ programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are performed using a oneAPI programming model using a DPC++ programming language.

It should be noted that, while example embodiments described herein may relate to a CUDA programming model, techniques described herein can be utilized with any suitable programming model, such HIP, oneAPI, and/or variations thereof.

At least one embodiment of the disclosure can be described in view of the following clauses:1. A processor comprising:one or more circuits to perform an application programming interface (“API”) to cause one or more memory locations to be asynchronously allocated to one or more processors.2. The processor of clause 1, wherein one or more of the one or more processors comprises a graphics processing unit (“GPU”).3. The processor of clause 1 or 2, wherein the one or more memory locations are to be asynchronously allocated using a virtual memory address provided in response to the API.4. The processor of any of clauses 1-3, wherein the one or more memory locations are to be asynchronously allocated using backing memory allocated from a memory pool.5. The processor of any of clauses 1-4, wherein the one or more memory locations are to be asynchronously allocated using backing memory allocated when a process executes on the one or more processors.6. The processor of any of clauses 1-5, wherein the API at least indicates a location used to return an asynchronously allocated memory address, a size of memory requested, and an execution stream that indicates a stream order of operations that use the one or more memory locations.7. The processor of any of clauses 1-6, wherein the one or more memory locations are memory locations in GPU memory.8. The processor of any of clauses 1-7, wherein the one or more memory locations use backing memory returned to a memory pool after a previous allocation.9. A computer-implemented method, comprising:performing an application programming interface (“API”) to cause one or more memory locations to be asynchronously allocated to one or more processors.10. The computer-implemented method of clause 9, wherein one or more of the one or more processors comprises a graphics processing unit (“GPU”).11. The computer-implemented method of clause 9 or 10, wherein one or more of the one or more processors comprises a parallel processing unit (“PPU”).12. The computer-implemented method of any of clauses 9-11, further comprising:generating a virtual memory address in response to the API; andproviding the virtual memory address to a process executing on the one or more processors.13. The computer-implemented method of any of clauses 9-12, further comprising:creating a memory pool;allocating backing memory from the memory pool; andassociating the backing memory with the one or more memory locations.14. The computer-implemented method of any of clauses 9-13, further comprising: allocating backing memory asynchronously when a process begins execution on the one or more processors.15. The computer-implemented method of any of clauses 9-14, further comprising: deallocating backing memory asynchronously when a process completes execution on the one or more processors.16. The computer-implemented method of any of clauses 9-15, further comprising:determining, based at least in part on a stream order specified in the API, whether a set of allocated memory from a memory pool will be available when a process begins execution on the one or more processors; andallocating backing memory asynchronously from the set of allocated memory when the process begins execution based at least in part on the determination.17. A computer system comprising one or more processors and memory storing executable instructions that, as a result of being executed by the one or more processors, cause the computer system to perform an application programming interface (“API”) to asynchronously allocate one or more memory locations to one or more processors.18. The computer system of clause 17, wherein one or more of the one or more processors comprises a graphics processing unit (“GPU”).19. The computer system of clause 17 or 18, wherein the one or more memory locations are memory locations in GPU memory.20. The computer system of any of clauses 17-19, wherein the API indicates a stream order of one or more of the one or more executable instructions.21. The computer system of any of clauses 17-20, wherein the API indicates a memory pool usable to asynchronously allocate the one or more memory locations.22. The computer system of any of clauses 17-21, wherein the one or more executable instructions at least include executable instructions to execute a process on the one or more processors.23. The computer system of any of clauses 17-22, wherein the one or more memory locations are to be asynchronously allocated using a virtual memory address.24. The computer system of any of clauses 17-23, wherein the one or more memory locations are to be asynchronously allocated using backing memory allocated from a memory pool when a process executes on the one or more processors.25. A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to perform an application programming interface (“API”) to asynchronously allocate one or more memory locations to one or more processors.26. The machine-readable medium of clause 25, wherein one or more of the one or more processors comprises a graphics processing unit (“GPU”).27. The machine-readable medium of clause 25 or 26, wherein the one or more memory locations are memory locations in GPU memory.28. The machine-readable medium of any of clauses 25-27, wherein:the one or more memory locations are to be asynchronously allocated using a virtual memory address provided in response to the API;the one or more memory locations are to be asynchronously allocated using backing memory allocated from a memory pool; andthe virtual memory address is associated with the backing memory.29. The machine-readable medium of any of clauses 25-28, the API at least indicates a location used to return an asynchronously allocated memory address, a size of memory requested, and an execution stream that indicates a stream order of operations that use the one or more memory locations.30. The machine-readable medium of any of clauses 25-29, wherein the one or more memory locations are determined, based at least in part on, a stream execution order indicated by the API.31. The machine-readable medium of any of clauses 25-31, wherein the one or more memory locations are determined, based at least in part on, one or more synchronization events between a plurality of processes executing on the one or more processors.32. The machine-readable medium of any of clauses 25-31, wherein:the one or more memory locations are to be asynchronously allocated to the one or more processors before a process executes on the one or more processors; andthe one or more memory locations are to be asynchronously deallocated from the one or more processors after a process executes on the one or more processors.

In at least one embodiment, an arithmetic logic unit is a set of combinational logic circuitry that takes one or more inputs to produce a result. In at least one embodiment, an arithmetic logic unit is used by a processor to implement mathematical operation such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement logical operations such as logical AND/OR or XOR. In at least one embodiment, an arithmetic logic unit is stateless, and made from physical switching components such as semiconductor transistors arranged to form logical gates. In at least one embodiment, an arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, an arithmetic logic unit may be constructed as an asynchronous logic circuit with an internal state not maintained in an associated register set. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or a memory location.

In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to an arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on an instruction code provided to inputs of the arithmetic logic unit. In at least one embodiment, the instruction codes provided by the processor to the ALU are based at least in part on the instruction executed by the processor. In at least one embodiment combinational logic in the ALU processes the inputs and produces an output which is placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on the output bus so that clocking the processor causes the results produced by the ALU to be sent to the desired location.