Infrared communication system

An infrared communication system includes a recongifurable RAM-based programmable logic device (PLD), an EPROM to provide configuration instructions to the PLD, and a clock supplying a clock signal to the PLD. A data input device and infrared transceiver are coupled to the PLD. The configured PLD uses the clock signal to synchronize data transfer between the data input device and the infrared transceiver.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to infrared communication. More specifically, the invention is an infrared communication system that is easily tested and reconfigurable to work in a variety of applications.

2. Description of the Related Art

Infrared communication to and from remotely located devices is prevalent in many fields. Typically, infrared communication links are used to minimize disturbances along conventional interface wiring, to minimize the amount of physical bulk of conventional wiring, and/or to minimize electronics noise which can accompany other forms of wireless communication such as radio frequency (RF) communication. Accordingly, new and better infrared transceivers are constantly being made available.

In order to evaluate possible advantages of the latest infrared transceiver technology, it is desirable to test transmission/reception protocol with existing remotely-located devices. Ideally, such testing would be controlled from a user interface such as a personal computer. Further, the system for testing and/or controlling an infrared transceiver should be easily reconfigurable to adapt to the latest infrared transceiver technology.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an infrared communication system.

Another object of the present invention is to provide an reconfigurable infrared communication system.

Still another object of the present invention is to provide an infrared communication system that is easily tested.

In accordance with the present invention, an infrared communication system includes a RAM-based programmable logic device (PLD) having a configuration port over which configuration instructions are received. The RAM-based PLD further has first and second input/output (I/O) ports. An erasable programmable read only memory (EPROM) and/or a data input device is coupled to the configuration port to provide the configuration instructions at power up of the RAM-based PLD. A clock is coupled to the RAM-based PLD to supply a clock signal thereto. Another data input device is coupled to the first I/O port of the RAM-based PLD. An infrared transceiver is coupled to the second I/O port of the RAM-based PLD. The RAM-based PLD uses the clock signal to synchronize data transfer between the data input device coupled to the first I/O port and the infrared transceiver through the RAM-based PLD.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Referring now to the drawings, and more particularly to FIG. 1 , an infrared communication system is shown and referenced generally by numeral 100 . Infrared communication system 100 can send/receive infrared transmissions 12 to and from a target device 10 or multiple target devices.

At the heart of infrared communications system 100 is a random access memory (RAM-based) programmable logic device (PLD) 102 . RAM-based PLD 102 is a static random access memory device that is configured internally in accordance with prescribed hardware logic or configuration instructions each time it is powered up. The configuration instructions are passed to RAM-based PLD 102 over its configuration port 102 A. Such RAM-based PLDs are known in the art and are available commercially from, for example, Altera Corporation, San Jose, Calif.; Actel Corporation, Sunnyvale, Calif.; and Lucent Technologies Inc., Murray Hill, N.J. The configuration instructions are preferably written in Very High Speed Integrated Circuit Hardware Description Language (VHDL) because VHDL is an industry standard PLD configuration language that is widely known and easy to modify.

The configuration instructions can be provided to RAM-based PLD 102 from a permanent memory such as an erasable programmable read only memory (EPROM) 104 , from memory onboard a personal computer 106 , or by manual input thereof using an input device such as personal computer 106 . While only one source of configuration instructions will be used during the powering up of RAM-based PLD 102 , several source options can be made a part of infrared communication system 100 . Accordingly, a switch 108 can be provided to selectively couple either EPROM 104 or personal computer 106 to configuration port 102 A. Note that the configuration instructions supplied (i.e., either stored or manually entered) by personal computer 106 are typically passed over a serial port 106 A.

RAM-based PLD 102 has input/output (I/O) ports 102 B and 102 C for the transfer of data therethrough. Coupled to I/O port 102 B is a data input device which, as mentioned above, can be the same personal computer 106 or a different dedicated personal computer. If personal computer 106 is used, I/O port 102 B is typically coupled to another serial port 106 B (e.g., RS-232 type) of personal computer 106 . An infrared transceiver 110 is coupled to I/O port 102 C. Data passing between personal computer 106 and infrared transceiver 110 is transformed, e.g., transcribed, converted in speed and form, undergoes protocol translation, etc., by RAM-based PLD 102 . Since transmission/reception speeds of personal computer 106 and infrared transceiver 110 will generally be different, a system clock 112 is provided to supply a clock signal to RAM-based PLD 102 . The clock signal will be manipulated as needed to suit a particular application as will be described further below.

FIG. 2 depicts a configuration of RAM-based PLD 102 at power up. First and second divide circuits 1021 and 1022 are configured to receive the clock signal produced by clock signal 112 . For accurate asynchronous transmission, it is desirable to provide at least 8 ( eight times ) oversampling of data transferred from either personal computer 106 or infrared transceiver 110 . Accordingly, divide circuits 1021 and 1022 are configured with a divisor to provide a clock signal that is at least eight times that of the data rates of personal computer 106 and infrared transceiver 110 , respectively. So that only one system clock is required, system clock 112 has a clock speed that is at least eight times the greater of the data rates of personal computer 106 and infrared transceiver 110 . For example, if serial port 106 B is an RS-232 serial port with a data rate of 115.2 kilobits per second (kbs) and infrared transceiver 110 transfers data at a rate of 4 megabits per second (Mbs), system clock 112 would have to produce a clock signal at a minimum of 32 MHz. In such a case, the divisor of divide circuit 1021 would be 35 and the divisor of divide circuit 1022 would be 1.

The altered clock signals are passed to respective first and second universal asynchronous receiver/transmitter (UART) circuits 1023 and 1024 . In general, the receiver portion of UART 1023 receives a serial (RS-232) data stream from personal computer 106 and stores same in order to form a parallel byte that is typically either 8, 16 or 32 bits in length. Each single parallel byte is passed to UART 1024 and reformatted to be suitable for infrared transmission by infrared transceiver 110 . Conversely, the receiver portion of UART 1024 prepares the data from infrared transceiver 110 for reformatting to RS-232 format by the transmitter portion of UART 1023 prior to transmission to personal computer 106 . Note that each of UART 1023 and UART 1024 can also be configured as an individual universal asynchronous receiver and an individual universal asynchronous transmitter as will be explained further below.

By way of illustrative example, a specific configuration of a RAM-based PLD in accordance with the present invention will be described. As illustrated in FIG. 3 , data is transferred at the RS-232 serial rate of 115.2 kbs from a personal computer 206 to RAM-based PLD 202 . An infrared transceiver 210 is assumed to be a standard Infrared Developer's Association (IRDA) transceiver module capable of transferring data at a rate of 4 Mbs. A system clock 212 provides a clock signal at 32 MHz. In this example, an EPROM 204 is used to supply the configuration instructions to RAM-based PLD 202 .

Once configured, RAM-based PLD 202 defines a divide circuit 2021 , a personal computer (PC) universal asynchronous receiver (UAR) 2022 , a PC-universal asynchronous transmitter (UAT) 2023 , an infrared (IR) universal asynchronous transmitter (UAT) 2024 , and an IR-UAR 2025 . In terms of data moving from personal computer 206 to infrared transceiver 210 , divide circuit 2021 divides the clock signal from system clock 212 by 35 to produce a 921.6 kHz internal square wave clock, i.e., to accomplish 8 oversampling by PC-UAR 2022 and PC-UAT 2023 . PC-UAR 2022 receives each incoming 8-bit serial data byte on RXD from serial port 206 A of personal computer 206 and converts same to a parallel byte on DOUT and pulses DVALID when the byte of data is valid. The parallel byte DOUT and pulse DVALID are passed to DIN and LOAD, respectively, of IR-UAT 2024 . The 32 MHz clock signal from system clock 212 is fed directly to IR-UAT 2024 to serve as the 8 oversampling clock. In response to inputs on DIN and LOAD, IR-UAT 2024 asserts BUSY, sends a start or synchronization pattern out at TXD, and clocks out the received parallel byte on TXD. The start or synchronization pattern can be a simple 3-bit pattern such as 110 . The 11 pattern allows infrared transceiver 210 to charge up while the trailing 0 allows infrared transceiver 210 to synchronize itself on the 1 to 0 transition.

In terms of data moving from infrared transceiver 210 to personal computer 206 , IR-UAR 2025 monitors its RXD input. Data received at RXD is clocked out at DOUT and the DVALID line is pulsed. In response, PC-UAT 2023 asserts BUSY, sends a start bit out at its TXD and follows this with the data clocked out serially at one-eighth the frequency of the clock signal received from divide circuit 2021 .

The advantages of the present invention are numerous. Any type of target device using infrared transceiving can use the present invention for testing or as an integral interface with a remotely-located data input device, e.g., a personal computer. The RAM-based PLD is easily re-configured by one of a variety of easily-reprogrammed configuration sources, e.g., an EPROM, a personal computer, etc. The present invention is readily adaptable in terms of data transfer rates and protocol by simply changing the VHDL configuration instructions and, possibly, the system clock.