Digital filter for the luminance channel of a color-television set

A digital filter for the digital luminance channel of a color-television set contains an even number of cascaded delay elements whose junctions as well as the input and the output of the cascade serve as taps. Each of the taps of the half on the input side is connected to an input of a first switch, and each of the taps of the half on the output side is connected to an input of a second switch, such that the two switches are simultaneously set to two taps which are symmetrical with respect to a center tap. The center tap is connected to the first input of a single multiplier, whose second input is fed with a signal corresponding to a constant, and whose output is coupled to the first input of an adder. The output of the first switch and that of the second switch are connected, respectively, to the second and third inputs of the adder, whose output is the output of the subnetwork. Digital filters with at least one such subnetwork can be used as peaking filters in the luminance channel of color-television sets.

The present invention pertains to a digital filter integrated circuit for 
the digital luminance channel of a color-television set. More 
specifically, one digital filter to which the invention pertains includes 
a three-input adder, delay elements connected in series in groups of two 
and each providing a delay equal to the period of the clock signal of the 
digital filter, and multipliers, with part of the groups of two cascaded, 
the inputs of the groups of two and the output of the last group of two 
having taps, and the frequency of the clock signal being four times the 
frequency of the chrominance-subcarrier reference. A digital filter of 
this kind is disclosed in the journal "Fernsehund Kino-Technik", 1981, 
pages 317 to 323, particularly FIG. 4 on page 319. 
The prior art digital filter contains a subnetwork consisting of two groups 
of two delay elements in which the input of the first delay element and 
the output of the last each have a multiplier connected thereto which 
multiply the signals applied to them by the same factor. The outputs of 
these two multipliers are connected to the three-input adder mentioned 
above. 
From this network structure it is readily apparent that the prior art 
digital filter evaluates input signals of zero frequency differently, 
namely depending on the above-mentioned factor. Therefore, different 
amplitude characteristics achieved by varying this factor have different 
DC components. If, however, this digital filter is used in the digital 
luminance channel of a color-television set, this property must be 
compensated for, i.e., at least one further multiplier is required which 
compensates for the above-mentioned dependence on the multiplicative 
factor of the two filter multipliers. This additional multiplier is not 
shown in the above-mentioned FIG. 4 of the cited reference, but its 
presence is evident from the amplitude characteristics of FIG. 5, where 
the individual characteristics have a constant DC component. 
The three multipliers required in the subnetwork add considerably to the 
expense of the circuit. 
SUMMARY OF THE INVENTION 
The object of the invention is to improve the prior art digital filter in 
such a way that particularly the additional compensating multiplier can be 
dispensed with, i.e., to achieve different amplitude characteristics not 
by varying a multiplier factor but by other means. The advantage of the 
prior art circuit of having a constant group delay is to be preserved. 
Another feature to be preserved is, of course, that the digital filter has 
an attenuation pole (transfer-function zero) at the frequency of the 
chrominance-subcarrier reference, but, in addition, the digital filter is 
to have an attenuation pole at 6 MHz, which frequency is used by the 
German Bundespost in type tests of color-television sets. 
In accordance with the principles of the invention, a digital filter for 
the digital luminance channel of a color-television set contains an even 
number of cascaded delay elements whose junctions as well as the input and 
the output of the cascade serve as taps. Each of the taps of the half on 
the input side is connected to an input of a first switch, and each of the 
taps of the half on the output side is connected to an input of a second 
switch, such that the two switches are simultaneously set to two taps 
which are symmetrical with respect to a center tap. The center tap is 
connected to the first input of a single multiplier, whose second input is 
fed with a signal corresponding to a constant, and whose output is coupled 
to the first input of an adder. The output of the first switch and that of 
the second switch are connected, respectively, to the second and third 
inputs of the adder, whose output is the output of the subnetwork. Digital 
filters with at least one such subnetwork can be used as peaking filters 
in the luminance channel of color-television sets.

DETAILED DESCRIPTION 
In the subnetwork for a digital filter of FIG. 1 those circuit components 
essential to the filter response, namely the delay elements v, the 
multiplier p, and the adder ad, are interconnected so as to illustrate the 
signal flow. Each of the delay elements v is assumed to give a delay equal 
to the period of the clock signal of the digital filter. In the present 
case, i.e., if the filter is used in the digital luminance channel of a 
color-television set, the frequency of this clock signal is four times the 
frequency of the chrominance-subcarrier reference fc. In FIG. 1, eight 
delay elements v, i.e., an even number of delay elements v, are connected 
in cascade, the input of each delay element and the output of the last 
delay element being provided with taps. The taps, in turn, are connected 
to the inputs of the two electronic multiway switches u1, u2 in a manner 
described below. The center tap of the cascade of delay elements v, i.e., 
the tap between the fourth and fifth delay elements, is shown as a triple 
tap for graphic reasons only, and is connected to the first input of the 
single multiplier p, whose second input is fed with a signal corresponding 
to a constant k. 
Starting from and including the center tap, the taps of that half of the 
delay elements v located on the input side are designated 0, 1, 2, 3, 4. 
In a mirror image of the input side the taps of that half of the delay 
elements located on the output side are also designated 0 to 4. These taps 
are also the inputs to the two electronic multiway switches u1, u2. By 
selecting a suitable tap in the first and the second half, different 
amplitude characteristics can be set. 
The output of the multiplier p is connected to the first input of the adder 
ad, and the outputs of the first and second electronic multiway switches 
u1 and u2 are connected, respectively, to the second and third inputs of 
this adder. The output of the adder ad is also the output of the 
subnetwork. 
FIG. 2 shows the variation of the amplitude g with the frequency f for the 
arrangement of FIG. 1 if the two electronic multiway switches u1, u2 are 
set to taps designated by the same reference numeral. In FIG. 2, 
corresponding characteristics curves are marked with these reference 
numerals. FIG. 2 shows that, depending on the switch positions of the 
electronic multiway switches u1, u2, different characteristics are present 
with respect to the clock frequency fs. The curve 4, for example, has a 
minimum at the frequency fc of the chrominance-subcarrier reference and 
multiples thereof, while the curve 2 has a maximum and a minimum at the 
frequency fc and at twice this frequency, respectively. This property can 
be used in the implementation of digital filters to supply attenuation 
poles (transfer-function zeroes). 
FIG. 3 shows amplitude characteristics which are achieved with a subcircuit 
as shown in FIG. 1 that is followed by a digital low-pass filter lp shown 
in dotted lines in FIG. 1 and having an upper cutoff frequency 
approximately equal to or lower than the frequency fc of the 
chrominance-subcarrier reference. 
FIG. 4 is a schematic digital filter diagram of another embodiment in which 
two subnetworks with the structure of FIG. 1 are cascaded. The two 
subnetworks contain the same number of components interconnected in the 
same manner. Elements in the second subnetwork have the same designators 
as the corresponding elements in the first subnetwork but with the 
addition of a prime, thus switch u1 in the first network corresponds to 
switch u1' in the second subnetwork. They differ only in the multiplier 
factors chosen, which are designated k1 in the input subnetwork of FIG. 4, 
and k2 in the output subnetwork, these two factors k1, k2 are thus 
unequal. 
Each subnetwork of FIG. 4 differs from the arrangement of FIG. 1 in that 
only four cascaded delay elements v or v' are present, so that the two 
electronic switches u1, u2 or u1', u2' are only three-position switches. 
By setting the switches in different positions m,n, different amplitude 
characteristics can be achieved with the arrangement of FIG. 4. 
If a digital low-pass filter lp is added at the output of the second 
subnetwork of FIG. 4 as shown in dotted lines, characteristics as shown in 
FIG. 5 are obtained. This figure shows a family of eight curves whose 
family parameter is c. The individual curves are obtained for the values 
of m and n given in the table contained in FIG. 5. Numerical values are 
given for the ordinate and the abscissa. From these numbers, particularly 
those of the abscissa, it is apparent that the digital filter in 
accordance with the invention can be implemented by choosing the numerical 
value of the clock frequency fs both the color-television sets according 
to the European standard and for those according to the American NTSC 
standard. FIG. 5 also shows that there is an attenuation pole at the 
chrominance-subcarrier frequency (4.43 MHz in the system). A 
corresponding attenuation pole is supplied at the chrominance-subcarrier 
frequency of the NTSC standard. The curve c=8, for which m=n=0, gives the 
curve of the above-mentioned low-pass filter, which has an upper cutoff 
frequency of approximately 1.70 MHz for (for NTSC correspondingly 
less). In the case of the curve c=8, the arrangement of FIG. 4 has a 
constant amplitude characteristic for all frequencies. The numerical 
values for the ordinate in FIG. 5 are obtained if, in the arrangement of 
FIG. 4, the factor k1=-3 and the factor k2=-6. 
One of the advantages of the invention over the prior art digital filter 
mentioned at the beginning is that signal delay through the subnetwork is 
constant, irrespective of which amplitude characteristic is selected by 
setting the electronic switches u1, u2 or u1', u2'. 
As the amplitude characteristics show, the digital filter in accordance 
with the invention can be used to produce sharper contrasts in the 
luminance channel ("peaking"). This means that luminance contrasts on the 
screen, i.e., black-white transitions or transitions from light to dark 
gray values, are enhanced. Since the digital filter in accordance with the 
invention has the same DC value for all degrees of contrast enhancement 
according to the amplitude characteristic selected, there is no change in 
gray level, however.