Memory sub-system for managing flash translation layers table updates in response to unmap commands

Method for managing flash translation layers (FTL) table updates in response to unmap commands starts with an unmap controller receiving unmap command that comprises a listing of regions in at least one memory component to be unmapped. Unmap controller updates an unmap regions list based on the unmap command. Unmap controller receives a write command to non-volatile memory component. Unmap controller determines, using the unmap regions list, if a write command occurs in a portion of an unmapped region of the non-volatile memory component. In response to determining that write command occurs in the portion of the unmapped region of the non-volatile memory component, unmap controller loads logical-to-physical (L2P) row to volatile memory. L2P row comprises a set of L2P entries mapping the portion of the unmapped region of the non-volatile memory component. Unmap controller then causes the set of L2P entries to be unmapped.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to a memory sub-system managing flash translation layers (FTL) table updates in response to unmap commands to decrease activity performed by media components and further help return unmap commands quickly.

BACKGROUND

A memory system can be a storage system, such as a solid-state drive (SSD), and can include one or more memory components that store data. For example, a memory system can include memory devices such as non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory system to store data at the memory devices of the memory system and to retrieve data stored at the memory system.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to a memory sub-system managing flash translation layers (FTL) table updates in response to unmap commands to decrease latencies and work performed by media components during unmap commands. A memory sub-system is also hereinafter referred to as a “memory device”. An example of a memory sub-system is a storage device that is coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input/output bus, a storage area network). Examples of storage devices include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, and a hard disk drive (HDD). Another example of a memory sub-system is a memory module that is coupled to the CPU via a memory bus. Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), a non-volatile dual in-line memory module (NVDIMM), etc. In some embodiments, the memory sub-system is a hybrid memory/storage sub-system. In general, a host system can utilize a memory sub-system that includes one or more memory components. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

The memory sub-system can include multiple memory components that can store data from the host system. An unmap command (or trim command) indicates to a memory component (e.g., SSD, NAND flash memory, etc.) which blocks of data are no longer considered in use and can be deleted internally. Executing an unmap command requires managing FTL table data within the memory components which forces many reads and write operations from the memory components. For example, the process of unmapping includes loading a logical-to-physical (L2P) table row which includes a set of L2P entries, forwarding each of the entries, performing mechanics on each of the entries and rewriting the L2P row or chunk of L2P row back to the memory component. Further, the process of unmapping can impact many parts of the FTL tables simultaneously which requires the loading and manipulation of each of the FTL tables. A conventional memory sub-system updates the FTL tables immediately upon receipt of the unmap command. This can cause high latency before the unmap command completes due to the increased activity required to be performed by the memory components.

Aspects of the present disclosure address the above and other deficiencies by having a memory sub-system that manages when the FTL table updates caused by unmap commands are performed. The memory sub-system maintains an unmap regions list that is an updated list of regions in the memory components that are unmapped. The memory sub-system checks against the unmap regions list before accessing the FTL tables stored within the memory components to avoid loading and modifying FTL tables that are only affected by the unmap command. Accordingly, the memory sub-system can delay FTL table updates and opportunistically perform the unmapping when the appropriate regions are already loaded into the volatile memory (e.g., RAM) from the memory components (e.g., NAND). This ultimately decreases the total number of write operations needed to be performed to accomplish the unmapping, decreases write amplification, and increases the performance of the unmapping, especially in the case of large unmap operations.

FIG. 1illustrates an example computing environment100that includes a memory sub-system110in accordance with some embodiments of the present disclosure. The memory sub-system110can include media, such as memory components112A to112N. The memory components112A to112N can be volatile memory components, non-volatile memory components, or a combination of such. In some embodiments, the memory sub-system is a storage system. An example of a storage system is an SSD. In some embodiments, the memory sub-system110is a hybrid memory/storage sub-system. In general, the computing environment100can include a host system120that uses the memory sub-system110. For example, the host system120can write data to the memory sub-system110and read data from the memory sub-system110.

The host system120can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such computing device that includes a memory and a processing device. The host system120can include or be coupled to the memory sub-system110so that the host system120can read data from or write data to the memory sub-system110. The host system120can be coupled to the memory sub-system110via a physical host interface. As used herein. “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between the host system120and the memory sub-system110. The host system120can further utilize an NVM Express (NVMe) interface to access the memory components112A to112N when the memory sub-system110is coupled with the host system120by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system110and the host system120.

The memory components112A to112N can include any combination of the different types of non-volatile memory components and/or volatile memory components. An example of non-volatile memory components includes a negative-and (NAND) type flash memory. Each of the memory components112A to112N can include one or more arrays of memory cells such as single level cells (SLCs) or multi-level cells (MLCs) (e.g., triple level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include both an SLC portion and a MLC portion of memory cells. Each of the memory cells can store one or more bits of data (e.g., data blocks) used by the host system120. Although non-volatile memory components such as NAND type flash memory are described, the memory components112A to112N can be based on any other type of memory such as a volatile memory. In some embodiments, the memory components112A to112N can be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magneto random access memory (MRAM), negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. Furthermore, the memory cells of the memory components112A to112N can be grouped as memory pages or data blocks that can refer to a unit of the memory component used to store data.

The memory system controller115(hereinafter referred to as “controller”) can communicate with the memory components112A to112N to perform operations such as reading data, writing data, or erasing data at the memory components112A to112N and other such operations. The controller115can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller115can include a processor (processing device)117configured to execute instructions stored in local memory119. In the illustrated example, the local memory119of the controller115includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system110, including handling communications between the memory sub-system110and the host system120. In some embodiments, the local memory119can include memory registers storing memory pointers, fetched data, etc. The local memory119can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system110inFIG. 1has been illustrated as including the controller115, in another embodiment of the present disclosure, a memory sub-system110may not include a controller115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

The memory sub-system110includes an unmap controller113that can be used to manage the FTL tables within the memory devices using an unmap regions list to accomplish the unmapping process. In some embodiments, the controller115includes at least a portion of the unmap controller113. For example, the controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, the unmap controller113is part of the host system110, an application, or an operating system.

The unmap controller113can maintain an unmap regions list that is an updated list of unmapped regions in the memory components112A to112N of the memory sub-system110. The unmap controller113can refer to the unmap regions list that is stored in a non-volatile memory to determine whether a region is unmapped and thus, contains no data. Rather than perform updating the FTL tables within a non-volatile memory component upon receipt of an unmap command, the regions indicated in the unmap command to be unmapped are added to the list of unmap regions list. Using the unmap regions list, the unmap controller113can opportunistically perform unmapping when unmapped regions are loaded into the volatile memory. For example, upon receiving a write command to a non-volatile memory component such as a NAND (flash) memory, the unmap controller113determines, using the unmap regions list, if the write command occurs in an unmapped region of the NAND memory. If the write command occurs in the unmapped region of the NAND memory, the unmap controller113can opportunistically perform the unmapping of the unmapped region since the region will be loaded into the volatile memory (e.g., RAM) in response to the write command. For example, when the write command is determined to occur in the unmapped region of the NAND memory, the unmap controller113can load into a RAM a logical-to-physical (L2P) row from the NAND's FTL table that includes a set of L2P entries mapping the unmapped region of NAND memory and cause the set of L2P entries to be unmapped. By delaying the update of the FTL table, the total number of write operations needed to be performed to accomplish the unmapping is decreased. Further details with regards to the operations of the unmap controller113are described below.

FIG. 2is an example of an unmap regions list in accordance with some embodiments of the present disclosure. The unmap regions list200comprises a plurality of entries that include an identification of the media component112A to112N, an identification of the unmap region, and an availability flag. The number of entries can be dynamically adjusted according to workflows. The unmap region can be indicated as the logical or physical addresses of blocks of data. The availability flag is a flag that indicates whether the entry in the unmap regions list is available or not available. The availability flag for an entry in the unmap regions list is set to available when the L2P entries in an L2P row corresponding to the region in the entry of the unmap regions list have been unmapped. For example, inFIG. 2, the availability flag for the third entry is set to available when the L2P entries in the L2P row in media component112B corresponding to blocks C1-C3have been unmapped.

At operation301, the unmap controller113receives an unmap command that includes a listing of the regions in at least one of the memory components112A to112N to be unmapped. At operation302, the unmap controller113updates an unmap regions list based on the unmap command. To update the unmap regions list, in operation302, the unmap controller113can add entries corresponding to the listing of the regions in the unmap command to the unmap regions list. To add entries to the unmap regions list, the unmap controller113can determine if a first region in the listing of the regions in the unmap command is adjacent to a region indicated in an existing entry that one of the entries in the unmap regions list and extend the region indicated in the existing entry to include the first region when the first region is adjacent to the existing entry. Thus, new unmaps (e.g., the first region) that are Logical Block Addresses (LBA) adjacent with an unmapped region (e.g., range corresponding to an existing entry in the unmap regions list) will cause the existing range to be extended to include the new unmap. For example, referring toFIG. 2, if the first region in the listing of the regions in the unmap command includes data blocks C4-C5in media component112B, the unmap controller113determines that the blocks C4-C5in media component112B are adjacent to block C3in media component112B listed in the third entry, and extends the region in the third listing from blocks C1-C3to blocks C1-C5.

The unmap controller113, as shown at operation303, receives a write command to the non-volatile memory component. The write component can be received from the host and the non-volatile memory component can be a NAND memory component. At operation304, the unmap controller113determines, using the unmap regions list, if the write command occurs in a portion of an unmapped region included in the non-volatile memory component. In one embodiment, the portion of the unmapped region included in the non-volatile memory component is an entirety of the unmapped region. The non-volatile memory includes a flash translation layers (FTL) table that maps Logical Block Addresses (LBA) from the host to Physical Block Addresses (PBA) on the non-volatile memory component. The FTL table includes a plurality of logical-to-physical (L2P) rows. Each of the L2P rows includes a L2P entries.

As shown at operation305, in response to determining that the write command does not occur in a portion of an unmapped region included in the non-volatile memory component, the unmap controller113issues the write command to the non-volatile memory component.

Thereafter, in response to determining that the write command occurs in the portion included in the unmapped region of the non-volatile memory component, the unmap controller113loads to the volatile memory an L2P row that comprises a set of L2P entries mapping the portion of the unmapped region included in the non-volatile memory component (see at operation306).

At operation307, the unmap controller113causes the set of L2P entries to be unmapped. In one embodiment, if the portion of the unmapped region included in the non-volatile memory component is mapped by L2P entries that are included in a plurality of L2P rows, each of the rows are loaded in operation306and the L2P entries are unmapped in operation307.

As shown at operation308, the unmap controller113updates the unmap regions list after causing the set of L2P entries to be unmapped. When the L2P row encompasses all of a region indicated in an existing entry in the unmap regions list, the unmap controller113updates the unmap regions list to indicate that the existing entry is available. In one embodiment, the unmap controller modifies the availability flag for the existing entry to indicate that the existing entry is available.

When the L2P row splits a region indicated in an existing entry in the unmap regions list, the unmap controller113updates the unmap regions list by splitting the existing entry into two separate entries (e.g., first split entry and second split entry) that includes unmap regions, respectively. In one embodiment, the unmap controller113determines whether the first or the second split entry is associated with a smaller unmap region. In response to determining that the first split entry is associated with a smaller unmap region than the second split entry, the unmap controller113loads the L2P row that maps the smaller unmap region into the non-volatile memory can causes the L2P entries in the L2P row to the be unmapped. In one embodiment, each of the L2P entries in the L2P row is unmapped according to the boundaries of the unmap region of the first split entry.

Once the unmap regions list is updated in operation308, the unmap controller issues the write command to the non-volatile memory component. In one embodiment, the unmap regions list is stored in another non-volatile memory component included in the memory components112A-112N.

The unmap controller113can load the unmap regions list to the volatile memory. The unmap controller113can also reload the unmap regions list to the volatile memory when an activity is performed that causes the unmap regions list to be removed from the volatile memory. For example, the unmap controller113can reload the unmap regions list to the volatile memory after power cycles or sleep operations.

At operation401, a processor117receives an unmap command that includes a listing of the regions in at least one of the memory components112A to112N to be unmapped. The memory components112A to112N can include a non-volatile memory component and a volatile memory component. The processor117, at operation402, updates an unmap regions list based on the unmap command. To update the unmap regions list, in operation402, the processor117can add entries corresponding to the listing of the regions in the unmap command to the unmap regions list. To add entries to the unmap regions list, the processor117can determine if a first region in the listing of the regions in the unmap command is adjacent to a region indicated in an existing entry that one of the entries in the unmap regions list and extend the region indicated in the existing entry to include the first region when the first region is adjacent to the existing entry.

The processor117receives a write command to the non-volatile memory component at operation403and determines, using the unmap regions list, if the write command occurs in a portion of an unmapped region of the non-volatile memory component, at operation404. As shown at operation405, in response to determining that the write command occurs in a portion of an unmapped region included in the non-volatile memory component, the processor117loads to the volatile memory a logical-to-physical (L2P) row and causes a set of L2P entries to be unmapped. The L2P row that is loaded in volatile memory comprises the set of L2P entries that map the portion of the unmapped region included in the non-volatile memory component. The L2P row is loaded from a flash translation layers (FTL) table included in the non-volatile memory component. In one embodiment, the processor117updates the unmap regions list after causing the set of L2P entries to be unmapped and issues the write command to the non-volatile memory.