Power reduction circuits and methods

An integrated circuit device may include a plurality of external connections, any one of the connections providing both a power voltage path for the integrated circuit (IC) as well as an information signal path for the IC. At least one switch may be coupled to provide a power supply voltage to one of the external connections.

TECHNICAL FIELD

The present disclosure relates generally to integrated circuit devices, and more particularly to devices and methods for providing power to an integrated circuit device.

DETAILED DESCRIPTION

Various embodiments will now be described that show devices and methods for providing power to an integrated circuit device. Such embodiments may allow an integrated circuit to switch from a low power state to a high power state according to an input signal at any one of a number of inputs. This is in contrast to device that switch power states in response to a dedicated input (e.g., “wake” input).

Referring toFIGS. 1A and 1B, an integrated circuit device according to a first embodiment is shown in a plan view and designated by the general reference character100. Device100may include an integrated circuit in packaged form with electrical connections for providing inputs to, or outputs from, the device. Such connections may be external package connections (e.g., leads, pins, balls), integrated circuit die connections (e.g., bond pads), or conductive paths between such points (e.g., bond wires, package traces)

The particular embodiment ofFIGS. 1A and 1Bshows a packaged integrated circuit device100with n+1 external pins, identified as pin “0” to pin “n”. Pins 0 to 3 may be “multi-function” pins102, while the remaining pins104may provide other functions or be non-connected pins, providing no function. In one very particular embodiment, none of the remaining pins104may be power supply pins. That is, power for the device may be derived from multi-function pins, and not any dedicated power supply pin (e.g., VCC or VDD pins).

As shown inFIG. 1B, multi-function pins102may be both input and power supply pins. That is, such pins may receive input signals representing data input, and at the same time, the application of any such inputs signal may be sufficient to power the device to execute predetermined functions. In some embodiments, such provided power may be “wake” power that enables a device100to switch from a low power consuming state (with little or no device functions), to a higher power consuming state (that may provide various functions). In other embodiments, such power may be operational power for executing device functions.

An embodiment like that ofFIGS. 1A and 1Bmay be used in an electronic device to reduce power consumption. In one very particular embodiment, physical inputs of such an electronic device (e.g., buttons) may provide an input signal (and hence power) to the device. This may eliminate the use for a “wake” type button for switching the electronic device between different power consuming states.

In this way, an integrated circuit device may include external connections that may both power an integrated circuit device, as well as provide an information input signal to the integrated circuit device.

Referring toFIGS. 2A and 2B, an integrated circuit device according to a further embodiment is shown in a plan view and designated by the general reference character200. Device200may include an integrated circuit in packaged form like that ofFIG. 1A.

The particular embodiment ofFIGS. 2A and 2Bshows a packaged integrated circuit device200with n+1 external pins, identified as pin “0” to pin “n”. Such pins (Pin 0 to Pin n) may include “multi-function” pins202, a dedicated low power supply pin206, and a dedicated high power supply pin208.

As shown inFIG. 2B, multi-function pins202may be any of: an input connection, an output connection, or a wake connection. An input connection may be a connection for receiving an information signal. An output connection may be a connection for providing output signals. A wake connection may be a connection that “wakes” device200from a lower power consuming state to a higher power consuming state. More particularly, a wake connection may provide wake power to a device200that may enable the device200to switch between such different power consuming states. In one embodiment, all of multi-function pins202may provide wake connections, while any of multi-function pins202may be an input connection, an output connection or both input and output connection.

A low power supply connection206may be a dedicated connection for applying a low power supply voltage (e.g., VSS, ground) to a device200. That is, such a connection does not provide either a data input or output connection. Similarly, high power supply connection208may be a dedicated connection for applying a high power supply voltage (e.g., VDD, VCC) to a device200. That is, such a connection does not provide either a data input or output connection.

Optionally, a device200may include a power supply switch (PS_SW) output210, shown in the particular embodiment ofFIGS. 2A and 2Bas pin4. A PS_SW output210may provide a control signal for enabling a power supply switch (not shown) that connects a low power supply voltage to low power supply connection206and/or a high power supply voltage to a high power supply connection208. In such an embodiment, upon receiving wake power via any of multi-function pins202, a device200may output a power supply switch control signal on PS_SW output210to enable “standard” power supply voltages to be applied at high and low power supply connections206and208. The application of standard power supply voltages may enable a device200to switch from a low power consuming, limited function state, to a higher power consuming, fully functional state.

In this way, an integrated circuit device may include external connections that may provide wake power to an integrated circuit device, as well as provide an information input or output signal to the integrated circuit device. At the same time, the device may have separate dedicated power supply connections.

Referring toFIGS. 3A and 3B, an integrated circuit device according to another embodiment is shown in a plan view and designated by the general reference character300. Device300may include an integrated in packaged form like that ofFIG. 1A.

The particular embodiment ofFIGS. 3A and 3Bshows a packaged integrated circuit device300with n+1 external pins, identified as pin “0” to pin “n”. Such pins (Pin 0 to Pin n) may include general purpose input/output/wake (GPIO/wake) connections,312, a dedicated low power supply pin306, and a dedicated high power supply pin308.

As shown inFIG. 3B, GPIO/wake pins312may be programmable between different modes (digital or analog). More particularly, when programmed as a digital connection, a GPIO/wake may be a digital input/output (I/O). However, when programmed as an analog connection, a GPIO/wake may be an analog input and a wake input. That is, such a connection may receive an input signal that may also wake device300from a lower power consuming state to a higher power consuming state. More particularly, like the embodiment ofFIGS. 2A and 2B, such an analog input/wake connection may provide wake power to a device300that may enable the device300to switch between such different power consuming states.

Low and high power supply connections (306and308) may be like those ofFIGS. 2A and 2B.

Optionally, one of GPIO/wake pins312may be programmed to provide a control signal for enabling a power supply switch (not shown), as described in the embodiment ofFIGS. 2A and 2B.

In this way, an integrated circuit device may include general purpose I/Os that may also provide wake power to an integrated circuit device.

Referring now toFIG. 4, an integrated circuit device according to another embodiment is shown in a partial top plan view, and designated by the general reference character400. Device400may be an integrated circuit formed in a substrate414. Device400may include multi-function connections402, corresponding p-n junctions416, an internal power supply network418, and a function circuit420. It is noted that p-n junctions416may provide a “diode” like response: providing a low impedance path when exceeding a particular threshold voltage (i.e., is forward biased), and maintaining a high impedance path in response to voltages below such a threshold (i.e., is reverse biased). Accordingly, for this and other embodiments, other structures providing a diode like response may be utilized in place of, or in addition to, p-n junctions.

In one embodiment, multi-function connections402may be bond pads of an integrated circuit in die form. Each such connection402may have a conductive connection to a p-n junction416formed in a substrate414. As will be described in other embodiments below, some or all of p-n junctions416may be a characteristic already present in circuits for receiving input signals and/or driving output signals on connections402.

P-n junctions416may be conductively connected to power supply network418which may provide a power supply voltage to function circuit420. A function circuit420may execute predetermined functions upon receiving a sufficient power supply voltage on power supply network418.

When any of p-n junctions416is forward biased, it may provide a supply voltage from its corresponding connection402to power supply network418, and hence, provide power to function circuit420. Such a power supply voltage may be a standard supply voltage that enables function circuit402to perform all of its intended functions. Alternatively, such a power supply voltage may be a wake voltage that allows function circuit420to execute operations that switch device400from a lower power consumption state, to a higher power consumption state.

In some embodiments, at the same time input signals cause p-n junctions416to be forward biased, such signals may also provide information to function circuit420. In addition or alternatively, p-n junctions may be forwarded biased to provide wake power, and then reverse biased as standard power is applied. Once reverse biased, corresponding connections402may provide data input signals.

In this way, an integrated circuit may include p-n junctions formed in a substrate that may be forward biased by input signals at external connections to provide a power supply voltage to a function circuit.

Referring now toFIG. 5, an integrated circuit device according to still another embodiment is shown in a block schematic diagram and designated by the general reference character500. An integrated circuit device500may include input connections502, p-n junctions516, a low power supply connection506, a high power supply connection508, a power supply voltage source522, and input switches524. One input switch524may correspond to each input connection502.

In the particular embodiment ofFIG. 5, a power supply voltage source522may provide a high supply voltage at a switch supply node526, and a low supply voltage to low power supply connection506. Each of input switches524may have one terminal connected to switch supply node526, and another terminal connected to a corresponding input connection502. Each of p-n junctions516, which may be conceptualized as semiconductor diodes, may have a p-type portion (i.e., anode) connected to a corresponding input connection502, and have an n-type portion (i.e., cathode) connected to a supply network528. Supply network528may also be connected to a high power supply connection508.

It is noted that each of input connections502may also be connected to a signal path to function circuit520. That is, such input connections506are not dedicated power supply connections.

In operation, when any of input switches524is activated (placed into a low impedance state), a high supply voltage from power supply voltage source522may be applied to a p-type portion of the corresponding p-n junction516. If a potential at the corresponding n-type portion is lower than the built-in potential of the junction, the junction may be forward biased, resulting in high power supply connection508being driven to a high potential (e.g., the supply voltage from source522, less the built-in junction potential and any resistance voltage drop in the path). In some embodiments, such a high potential may be sufficient to provide standard power to function circuit520. In other embodiments, such a high potential may provide a wake power to such a circuit that enables the subsequent application of standard power to the device.

Optionally, a device500may include a power supply control path530between power supply voltage source522and high power supply connection508. A power supply control path530may alter a voltage at high power supply connection508from any voltage received on supply network528. Particular examples of power supply control paths are shown in more detail below, and may include without limitation, a power supply switch and/or a voltage regulator.

Referring toFIG. 6, an integrated circuit device according to still another embodiment is shown in a block schematic diagram and designated by the general reference character600. Device600may include similar items to those shown inFIG. 5, accordingly, like items are referred to by the same reference character but with the first digit being a “6” instead of a “5”.

The embodiment ofFIG. 6varies from that ofFIG. 5in that each of p-n junctions616may have an n-type portion (i.e., cathode) connected to a corresponding input connection602, and have p-type portions (i.e., anodes) commonly connected at a supply network628. Further, supply network628may be connected to a low power supply connection606.

In operation, when any of input switches624is activated (placed into a low impedance state), a low supply voltage from power supply voltage source622may be applied to an n-type portion of the corresponding p-n junction616. If the p-type portion is higher than the built-in potential of the junction, the junction may be forward biased, resulting supply network628being driven to a low potential (e.g., the low supply voltage from source622, plus the built-in junction potential and resistance drop). In some embodiments, such a low potential may be sufficient to provide standard power to function circuit620, or in other embodiments, such a low potential may provide wake power to such a circuit.

In this way, an integrated circuit device may include input connections with p-n junctions that may be forward biased by operation of switches to provide power to the integrated circuit.

Referring now toFIG. 7, an integrated circuit device according to another embodiment is shown in block schematic diagram, and designated by the general reference character700. Device700may include some items like those ofFIG. 5, accordingly, like items are referred to by the same reference character but with the first digit being “7” instead of “5”.

UnlikeFIG. 5,FIG. 7shows device700with a control section720-0, function section720-1, and p-n junctions716formed in a same semiconductor substrate714as sections720-0/1. In addition, a power supply switch732may be disposed between a power supply voltage source722and a high power supply connection708. Further, a current limiting impedance736may be formed between power supply voltage source722and switch supply node726.

A control section720-0may be situated between supply network728and low power supply connection706. Upon receiving a sufficient wake voltage due to the forwarding biasing of one or more p-n junctions716, a control section720-0may activate a switch control signal at power supply switch output710to control power supply switch732. Function section720-1may provide predetermined operations in response to various inputs, including inputs received on input connections702.

A power supply switch732may have a power supply input734-0connected to power supply voltage source722, a power supply output734-1connected to high power supply connection708, and a control input734-2connected to power supply switch output710. In response to a signal received at control input734-2, power supply switch732may provide a low or high impedance between input734-0and output734-1.

Current limiting impedance736may limit the amount of current flowing into substrate714when any of switches724is enabled, while at the same time, such an impedance may be selected to ensure a sufficient wake voltage drop is generated across control section720-0when a switch is initially enabled to wake device700from a low power consuming state to a higher power consuming state.

Particular wake operations for the embodiment ofFIG. 7will be described at a later point herein.

Referring toFIGS. 8A and 8B, particular examples of power supply switches that may be included in the embodiments are shown in schematic diagrams. In particular embodiments, such power supply switches may be included in power supply switch shown as732inFIG. 7.

Referring toFIG. 8A, a power supply switch832-A may include a power supply input834-0, power supply output834-1, and a control input834-2. A power supply switch832-A may include a pnp bipolar transistor Q80, a first resistance R80, and a second resistance R82. Transistor Q80may have an emitter connected to a power supply input834-0, a collector connected to a power supply output834-1, and a base. First resistance R80may be connected between power supply input834-0and a base of Q80. Second resistance R82may be connected between a base of transistor Q80and control input834-2.

Referring now toFIG. 8B, a power supply switch832-B may have the same general configuration as that shown inFIG. 8A, however an insulated gate (e.g., MOS) type switch transistor P80may be included in place of a pnp transistor.

Referring to now toFIG. 9, an integrated circuit device according to another embodiment is shown in block schematic diagram, and designated by the general reference character900. Device900may include some items like those ofFIG. 6, accordingly, like items are referred to by the same reference character but with the first digit being “9” instead of “6”.

FIG. 9differs fromFIG. 6in that it includes features like that ofFIG. 7. In particular, device900may include a control section920-0, function section920-1, and p-n junctions916formed in a same semiconductor substrate914as sections920-0/1. In addition, a power supply switch932may be disposed between a power supply voltage source922and a low power supply connection908, and a current limiting impedance934may be formed between power supply voltage source922and switch supply node926.

FIGS. 10A and 10Bshow particular examples of power supply switches that may be included in the embodiments. In particular embodiments, such power supply switches may be included in power supply switch shown as932inFIG. 9.

Referring toFIG. 10A, a power supply switch1032-A may have the same general configuration as that shown inFIG. 8A, but includes an npn bipolar transistor Q100. Similarly,FIG. 10Bshows a power supply switch1032-B that may have the same general configuration asFIG. 8B, but with an n-channel insulated gate field effect transistor N100.

It is noted that whileFIGS. 8A,8B,10A and10B show transistor based circuits as a power supply switch, other embodiments may include alternate structures. For example, a power supply switch may include a relay or other electronically controlled switch.

In this way, an integrated circuit device may include a control section that activates a power supply switch in response to wake power applied by forward biasing one or more p-n junctions formed at input connections of the device.

Referring now toFIGS. 11A to 11Ca “pull-down” input structure that may be included in the embodiments is shown in a block schematic diagram and designated by the general reference character1100.FIG. 11Ashows an input structure1100prior to a wake/input operation.FIG. 11Bshows input structure1100during a wake/input operation.FIG. 11Cshows input structure receiving a input signal in a standard operation.

Input structure1100may include an input connection1102, a p-n junction1116, a power supply voltage source1122, an input switch1124, a switch supply node1126, a supply network1128, a current limiting impedance1136, a pull-down impedance1138, and an input buffer1140.

A pull-down impedance1138may be situated between input connection1102and a low power supply node1142. In some embodiments, a pull-down impedance1138may be separate from an integrated circuit substrate containing p-n junction1116. In other embodiments, a pull-down impedance1138may be formed in a same integrated circuit substrate as p-n junction1116. A pull-down impedance1138may be switchable to selectively provide a pull-down function. As but one example, a switch (e.g., transistor) may be formed between a pull-down impedance1138and VSS.

An input buffer1140may have an input connected to input connection1102and an output that may provide a signal to other sections within an integrated circuit device. Input buffer1140may be formed in the same integrated circuit substrate as p-n junction1116.

Referring toFIG. 11A, prior to a wake operation, an input switch1124may be open (i.e., high impedance state). As a result, pull-down impedance1138may drive input connection toward a low power supply voltage VSS. It is assumed at this time that supply network1128may be at a potential that maintains p-n junction1116in a reverse bias state (RB).

Referring toFIG. 11B, in a wake operation, an input switch1124may be closed (i.e., low impedance state). As a result, a positive supply voltage Vsupp+ may be applied to input connection1102through current limiting impedance1136. It is assumed that such a potential is sufficient to place p-n junction1116into a forward biased state (FB), causing a wake voltage Vwake to be applied on supply network1128. Such a voltage may activate other circuits that may wake a larger integrated circuit device. Optionally, the application of Vsupp+ at input connection1102may result in input buffer1140driving its output accordingly (in this case high).

Referring toFIG. 11C, in a standard operation, a supply network1128may be driven to a high power supply voltage VDD, which is assumed to be sufficient to reverse bias p-n junction1116. In such an arrangement, when input switch1124is closed, a positive supply voltage Vsupp+ may be applied to input connection1102through current limiting impedance1136. The application of Vsupp+ at input connection1102may result in input buffer1140driving its output accordingly (in this case high).

Referring now toFIGS. 12A to 12Ca “pull-up” input structure that may be included in the embodiments is shown in a block schematic diagram and designated by the general reference character1200.FIG. 12Ashows an input structure1200prior to a wake/input operation.FIG. 12Bshows input structure1200during a wake/input operation.FIG. 12Cshows input structure receiving a signal in a standard input operation.

The embodiment ofFIGS. 12A to 12Cincludes some of the same features as that ofFIGS. 11A to 11C, thus like items are referred to by the same reference character but with the first digits being “12” and “11”.

The embodiment ofFIGS. 12A to 12Coperates in the same general fashion asFIGS. 11A to 11C, but with a pull-up impedance1244pulling input connection1202toward a high power supply voltage VDD at a high power supply node1246. Further, when input switch1224is closed, a low supply voltage (shown as VSS) is applied to input connection1202to forward bias p-n junction1216and provide a wake voltage (Vwake′) in a wake mode (FIG. 12B), or result in input buffer1240driving its output accordingly (in this case low) in a standard mode (FIG. 12C). Like the embodiment ofFIGS. 11A to 11C, a pull-up impedance1244may be switchable with respect to VDD.

In this way, input structures may include p-n junctions that are forward biased in a wake mode to provide wake power through an input connection, and then reverse biased in standard mode to allow input signals to propagate through the input connection.

Referring now toFIGS. 13A and 13Ban input/output (I/O) circuit that may be included in embodiments is shown in schematic diagram and cross sectional view, and designated by the general reference character1300. I/O circuit1300may include a p-n junction that may be forward biased in a wake operation. Such a p-n junction may be a characteristic present in I/O circuit1300. That is, such a p-n junction may be part of circuitry included in the I/O circuit having a function apart from providing a wake voltage.

Referring toFIG. 13A, an I/O circuit1300may receive input signals on an external connection and provide them to other circuits as signal INPUT STATE. I/O circuit1300may also receive signals internal signals (OUTPUT STATE) and drive such signals as output signals.

In the very particular embodiment ofFIG. 13, an I/O circuit1300may include an I/O connection1302, p-n junctions1316-0/1, high supply network1328-0, low supply network1328-1, input buffer1340, output control1348, p-channel driver transistor P130, and n-channel driver transistor N130. In particular embodiments, p-n junctions1316-0/1are not separate from the other circuitry of I/O circuit1300, and in one particular embodiment are formed by portions of transistors P130and N130.

Input buffer1340may have an input connected to I/O connection1302and an output that provides signal INPUT STATE. Transistor P130may have a source connected to high supply network1328-0, a drain connected to I/O connection1302, and a gate connected to an output of output control1348. Transistor N130may have a source connected to low supply network1328-1, a drain connected to I/O connection1302, and a gate connected to an output of output control1348. Output control1348may commonly drive gates of transistors P130and N130to provide a path from I/O connection1302to either of high or low supply networks1328-0/1.

It is noted that one of supply networks1328-0/1may be maintained at a power supply potential depending upon which p-n junction is forward biased to provide a wake power supply. For example, if a high wake voltage is applied by forwarding biasing p-n junction1316-0, a low supply network1328-1may be maintained at a low power supply voltage (e.g., VSS). Conversely, if a low wake voltage is applied by forwarding biasing p-n junction1316-1, a high supply network1328-1may be maintained at a high power supply voltage (e.g., VDD).

Referring toFIG. 13B, a portion of the circuit shown inFIG. 13Ais represented by a cross sectional view.FIG. 13Bshows transistors P130and N130formed in a substrate1314. P-n junction1316-0may include a p-type drain diffusion of transistor P30, and n-type well1339portion of substrate1314. P-n junction1316-1may include an n-type drain diffusion of transistor N30, and p-type substrate1314.

Referring now toFIGS. 14A and 14Ban input circuit that may be included in embodiments is shown in schematic diagram and cross sectional view, and designated by the general reference character1400. Input circuit1400may also include a p-n junction that may be forward biased in a wake operation. Such a p-n junction may be a characteristic already present in input circuit1400. That is, such a p-n junction may be part of circuitry included in the I/O circuit having a function apart from providing a wake voltage.

Referring toFIG. 14A, an I/O circuit1400may receive input signals on external connection and provide them to other circuits as signal INPUT STATE. Input circuit1400may include an input connection1402, p-n junction1416, high power supply connection1408, a low supply network1428, an input buffer1440, and an electrostatic discharge (ESD) protection circuit1450. An input buffer1440may include p-channel input transistor P140and n-channel input transistor N140. ESD protection circuit1450may include p-channel transistor N142.

In particular embodiments, p-n junction1416is not separate from the other circuitry of input circuit1400, and may be formed by portions of transistors N142.

Input1440may have an input connected to I/O connection1402and an output that provides signal INPUT STATE. Transistor P140may have a source connected to high supply connection1408, a drain connected to an input signal node1452, and a gate connected to input connection1402. Transistor N140may have a source connected to low supply network1428, a drain connected to input signal node1452, and a gate connected to input connection1402. Transistor P142of ESD protection circuit1450may have a drain connected to input connection1402and a source and gate connected to low supply network1428.

Referring toFIG. 14B, a portion of the circuit shown inFIG. 14Ais represented by a cross sectional view.FIG. 14Bshows transistor P142formed in a substrate1414. P-n junctions1416may include an n-type drain region of transistor N142, as well as p-type substrate1414.

In this way, diode type structures, such as p-n junctions as but one example, may be forward biased to provide a wake voltage and may be structures already present in input and/or output circuitry.

Referring now toFIGS. 15A to 15Ca particular wake operation for the embodiment ofFIG. 7is a shown in sequence of block schematic diagrams. It is assumed that prior to the actions shown inFIG. 15A, a device700may be in a low power consuming sleep mode.

Referring toFIG. 15A, at the start of wake operation any input switches724-0to724-nmay be closed. In the particular example shown, input switch724-0may be closed. As but one example, such a switch may be closed by pushing a button on electronic device, or some other switching mechanism (e.g., reed switch, etc.). As a result, a high power source voltage (shown by a bold solid line) may be applied through current limiting impedance736to multifunction connection702-0. This voltage may forward bias p-n junction716-0, applying a wake voltage to at least control section720-0. A low power supply voltage (shown by a bold dashed line) may be applied to control section720-0through low power supply connection706.

Referring toFIG. 15B, upon receiving a wake voltage (Vwake) and a low power supply voltage (VSS), control section720-0may generate a switch on signal (SW_ON) at power supply switch output710, which may be applied to a control input734-2of power supply switch732.

Referring toFIG. 15C, in response to signal SW_ON, power supply switch732may apply a standard high power supply voltage (VDD) at high power supply connection708. This may drive VDD on supply network728, which may reverse bias p-n junction716-0and provide a full power supply voltage to function section720-1. Consequently, function section720-1may execute predetermined operations in response to input signals received on connections702-0to702-n.

In this way, a device may be woken from a sleep mode into a fully operational mode by a voltage applied at any one of multiple input connections.

Referring now toFIG. 16, a semiconductor device according to yet another embodiment is shown in a block schematic diagram and designated by the general reference character1600.

Device1600may include items like those shown in the embodiment ofFIG. 7. Such like items are referred to by the same reference character but with the leading digits being “16” instead of “7”.

FIG. 16differs fromFIG. 7in that it may include two different high power supply connections: an I/O high power supply connection1608-0, and a main high power supply connection1608-1. Further,FIG. 16also shows a power on reset (POR) section1658, a voltage regulator1664, and a core section1666. It is noted that while power supply connections1608-0and1608-1are shown connected externally, in other embodiments, such a connection may be made internally.

An I/O high power supply connection1608-0may provide a high power supply voltage to I/O circuits, including to supply network1628. A main high power supply connection1608-1may provide a power supply voltage for other circuits within a device1600, including POR section1658and voltage regulator circuit1664. I/O and main high power supply connections (1608-0and1608-1) may be commonly connected to power supply output1634-1from power supply switch1632.

In a standard operation mode (i.e., not a sleep or wake mode), a device1600may operate with two different power supply voltages. A regulated power supply voltage (VCC) may be applied on a second internal power supply node1656, while a larger main power supply voltage (VDD) may be applied on a first internal power supply node1654.

A POR section1658may have one input connected to first internal power supply node1654, another input connected to second internal power supply node1656, and an output that provide a POR signal to core1666. A POR section1658may activate signal POR in response to predetermined stable voltage levels being achieved on first and second internal power supply node (1654and1656). In the very particular embodiment ofFIG. 16, a POR section1658may include a supply POR circuit1660-0, a regulated POR circuit1660-1, and POR logic1662. A supply POR circuit1660-0may monitor a voltage at first internal power supply node1654, and in response to such a voltage, provide an output signal to POR logic1662. In a similar fashion, a regulated POR circuit1660-1may monitor a voltage at second internal power supply node1656, and in response to such a voltage, provide a second output signal to POR logic1662. POR logic1662may output POR signal to core section1666. In a very particular embodiment, supply POR circuit1660-0may activate its output in response to a wake voltage at first supply node1654, which may be less than a VDD value. Similarly, a regulated POR circuit1660-1may activate its output in response to a regulated wake voltage at second supply node1656, which may be less than a VCC value.

A voltage regulator circuit1664may regulate a voltage received at first internal power supply node1654to generate a regulated power supply voltage at second internal power supply node1656. In a particular embodiment, a regulated voltage may be lower than that at a first power supply node1654. More particularly, in a standard mode of operation, voltage regulator circuit1664may receive a voltage VDD at first internal power supply node1654, and regulate such a voltage to generate VCC on second internal power supply node1656. Similarly, in a wake mode of operation, voltage regulator circuit1664may receive a main wake voltage (Vwmain) on first internal power supply node1654, which may be less than VDD, and regulate such a voltage to generate a regulated wake voltage Vwreg on second internal power supply node1656, where Vwreg may be less than or equal to VCC.

A core section1666may provide predetermined functions, for example, execute operations in response to input signals received on any of connections1602-0to1602-n. A core section1666may operate on the regulated power supply voltage at second internal power supply node1656.

It is noted that while capacitor C162is shown as an internal component, in other embodiments, such a capacitor may be an external component connected to an external power supply connection.

Referring now toFIGS. 17A to 17Ca particular wake operation for the embodiment ofFIG. 16is a shown in sequence of block schematic diagrams. It is assumed that prior to the actions shown inFIG. 17A, a device1600may be in a low power consuming sleep mode.

Referring toFIG. 17A, any of input switches1624-0to1624-nmay be closed. In the operation shown, input switch1624-0may be closed. As a result, a high power source voltage (shown by a bold solid line) may be applied to multifunction connection1602-0. This voltage may forward bias p-n junction1616-0, applying a main wake voltage (Vwmain) to first internal power supply node1654via I/O and main power supply connections (1608-0and1608-1). As noted previously, in other embodiments a supply network1628may be directly connected to internal power supply node1654, in which case a wake voltage may be applied to power supply node1654directly via a multifunction connection (e.g.1602-0to1602-n). In response to main wake voltage (Vwmain), voltage regulator circuit1664may generate a regulated wake voltage (Vwreg). Supply POR circuit1660-0may monitor voltage Vwmain, while regulated POR circuit1660-1may monitor voltage Vwreg.

Referring toFIG. 17B, it is assumed that supply POR circuit1660-0determines that voltage Vwmain is within predetermined tolerances, and so activates an output signal applied to POR logic1662. It is also assumed that regulated POR circuit1660-1determines that voltage Vwreg is within predetermined tolerances, and so activates its corresponding output signal to POR logic1662. In response to such indications from both POR circuits (1660-0and1660-1), POR logic1662may activate a POR signal. Upon receiving an active POR signal, a core section1666may activate a switch-on signal (SW_ON) that is applied to power supply switch1632.

Referring toFIG. 17C, in response to signal SW_ON, power supply switch1632may apply a standard high power supply voltage (VDD) at I/O and main high power supply connections1608-0/1. This may reverse bias p-n junction1616-0and provide a full power supply voltage (VDD) at first internal power supply node1654. In response to VDD and first power supply node1654, voltage regulator circuit1654may generate a fully regulated voltage VCC at second internal power supply node1656.

In this way, a device having separately voltage regulated sections may be woken from a sleep mode into a fully operational mode by a signal applied at an input connection.

Referring now toFIG. 18A to 18C, a semiconductor device according to another embodiment is shown in a block schematic diagram and designated by the general reference character1800. Device1800may include items like those shown in the embodiment ofFIG. 16. Such like items are referred to by the same reference character but with the leading digits being “18” instead of “16”.

The embodiment shown inFIGS. 18A to 18Cdiffers from that ofFIG. 16in that it does not include a voltage regulator, and a POR section1858monitors a voltage at a single power supply node1845.

Referring now toFIGS. 18A to 18Ca particular wake operation for device1800will now be described.

Referring toFIG. 18A, any of input switches1824-0to1824-nmay be closed (in this case1824-0), resulting in a high power source voltage (shown by a bold solid line) may be applied to multifunction connection1802-0. This voltage may forward bias p-n junction1816-0, applying a wake voltage (Vwake) to internal power supply node1854. POR section1858may monitor voltage Vwake.

Referring toFIG. 18B, it is assumed that supply POR section1858determines that voltage Vwake is within predetermined tolerances, and so activates a POR signal. Upon receiving an active POR signal, a core section1866may activate a switch-on signal (SW_ON) that is applied to power supply switch1832.

Referring toFIG. 18C, in response to signal SW_ON, power supply switch1832may apply a standard high power supply voltage (VDD) at power supply connection1808. This may reverse bias p-n junction1816-0and provide a full power supply voltage (VDD) at internal power supply node1854.

In this way, a device having separately powered internal sections may be woken from a sleep mode into a fully operational mode by a signal applied at an input connection.

Referring now toFIG. 19, an electronic device according to a further embodiment is shown in a perspective view and designated by the general reference character1900. A device1900may be an electronic device having multiple inputs any of which can be activated to switch the device from a low power consuming “sleep” mode to a fully functional active mode. In particular embodiments, such inputs do not include a “wake” input (i.e., one input dedicated to waking a device from the sleep mode). Further, in other embodiments, such inputs are not periodically scanned by applying voltages in sequences at particular locations.

A device1900may include an integrated circuit device according to any of the embodiments shown above, or equivalents. Multiple (or all) inputs of the electronic device1900may be connected to multifunction connections of the integrated circuit device. In such an arrangement, when any input of device1900is activated, the device may wake from the sleep mode.

In the very particular embodiment ofFIG. 18, a device1900may be a remote control having an integrated circuit device1970assembled therein. Integrated circuit device1970may include devices shown in the above embodiments or equivalents.

In this way, an electronic device may be switched between a sleep mode and an active mode by operation of any of multiple inputs on the device.

It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.