Semiconductor memory device provided with DRAM cell including two transistors and common capacitor

A semiconductor memory device is provided such as a random-access memory (DRAM) including a plurality of DRAM memory cells. Each of the DRAM cells includes an N-type transistor, a P-type transistor, and a common capacitor. The components are disposed in the same direction as the bit-line, with the common capacitor occupying the center region between the N- and P-type transistors. The common capacitor is a metal insulator metal (MIM) capacitor configured by connecting three capacitor elements in parallel. The three capacitors include a first capacitor element formed on a first source/drain region of the N-type transistor, a second capacitor element formed on a first source/drain region of the P-type transistor, and a third element over the field isolation region between the transistors. A bottom electrode of each of these capacitor elements connects the first source/drain region of the N-type transistor to a first source/drain region of the P-type transistor.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor memory device such as a dynamic random-access memory (DRAM) memory, and in particular, relates to a new structure of capacitors of DRAM cells, each DRAM cell including an N-type transistor, a P-type transistor, and a common capacitor.

Description of Related Art

In DRAMs, information data is stored by accumulating electric charges in a capacitor via memory-cell transistor. The area occupied by the DRAM memory cells decreases as process technology scales down.

Semiconductor process scaling and network technology advances have been generating new mobile device markets such as mobile phones, tablet PCs and IOT applications.

FIG. 3shows a block diagram of a typical mobile device200, which includes a host circuit201, a CPU202, a DRAM203, a flash memory204, a communication device205, a camera and sensor interface206, a graphics controller207, a serial data transfer interface208, an I/O interface209, an analog/digital device and interface210, a signal processor211and an inner CPU bus212. The mobile device200further includes an LCD driver IC213including a serial data transfer interface214, a simple graphics controller216, a frame buffer217, an X-driver output221and a Y-driver output223; an LCD panel device220including an LCD screen225, a X-driver224and a Y-driver222; a high voltage generator218; and a battery226.

The mobile device200receives several kinds of data by equipped interfaces as shown inFIG. 3. For example, a huge amount of compressed data such as high-resolution motion picture is transferred to the mobile device200from a cloud environment and processed in the communication device205to be viewed by the LCD screen225. The compressed data is decoded by using the CPU202and by the signal processor211, and then, is modified by the graphics controller207by using memories, such as the DRAM203or the flash memory204. Thereafter, the data are sent from the host circuit201to the LCD driver IC213through the serial interfaces208and214of both sides. The data sent to the LCD driver IC213is temporarily stored in the frame buffer217, and finally the data are viewed on the LCD screen225.

When a motion picture is displayed, the host circuit201, mainly the graphics controller207, the DRAM203, the signal processor211and the serial data transfer interface208are made in active state without interruption. These uninterrupted circuit operations consume large electric power stored in the battery226which is generally only a power source of the mobile device200.

In order to reduce the power consumption of the battery226, especially when a still picture is displayed, the simple graphics controller216and the frame buffer217are used. The frame buffer217generally includes an embedded SRAM, and a SRAM cell thereof generally includes six transistors widely known to those in the art, where this kind of SRAM cell having six transistors is called “6T-SRAM”.

When a still picture is displayed, data of one picture are stored in the frame-buffer217which is controlled by the simple graphics controller216. Because the same frame picture stored in the frame buffer217is refreshed by the LCD driver IC213, the host circuit201can be in a stand-by mode for power saving. This makes the mobile battery226power consumption significantly lower. Because of this power reduction, the frame buffer217is regarded as an indispensable device for mobile devices200.

As required pixel processing speed for mobile devices200has become much faster by the increased LCD screen resolution, the increase of the power consumption of mobile devices has become evident. To this date, power reduction technology of the mobile device has not yet fully caught-up with power reduction requirements.

Requirements for IC chips in the mobile device200, such as the CPU202, the graphics controllers,207and216and the memories203,204and217, sometimes conflict with each other. For an example, the requirements for the mobile devices on random access memories are “compact chip size”, “higher band-width”, “larger data storage”, “lower cost” and “lower power consumption”. In particular, the requirements such as “larger memory storage size and lower cost” and “higher band-width and lower power” conflict with one another. In order to overcome the problems of the conflicting requirements, choosing “system on chip solution with embedded SRAM” and “using smaller process node” have been reasonable solutions.

In some new market as mobile applications which require more memory size, embedded DRAM logic process has been reviewed again, because of the reason that its relatively high process cost can be offset by chip area savings.

As described above, the widely used embedded SRAM uses six-transistor cells. On the other hand, the embedded DRAM cell uses only one capacitor and one transistor cells as shown inFIG. 2B, since a DRAM cell capacitor is fabricated over a transistor, roughly, DRAM cell size is ⅕ to ⅙ of that of 6T-SRAM cell. The area advantage of DRAM embedded process is evident than that of SRAM embedded process. Further,FIG. 2Cshows an equivalent circuit of another conventional DRAM cell including two transistors and one capacitor.

However, in a DRAM embedded logic process, for having a cell capacitor enough to guarantee DRAM functionalities, additional unique process steps are required. This is a cost increase factor of the embedded DRAM logic process.

In order to overcome this disadvantage, some ideas to form DRAM cells without using special process steps have been proposed, but large-enough DRAM capacitor with reasonable area has been difficult to achieve. Because of the scaling of the embedded DRAM logic process, there are two problems when used in “high speed and low power mobile devices as200shown inFIG. 3”. One problem is the voltage drop across the transfer transistor, due to both threshold and on-resistance, which can reduce storage level and memory access speed. Another problem is a smaller capacitance of the shrunk capacitor, which requires frequent refresh, and which can lead to larger stand-by power consumption.

In order to solve these two problems on the embedded DRAM logic process, several new ideas by US patents, which use a DRAM cell having two transistors, have been proposed.

U.S. Pat. No. 7,505,299B2 by Riichiro TAKEMURA shows a new idea to make use of a dual-port DRAM cell by activating two word-lines at the same timing, and equivalently, halves the transistor's on-resistance. This helps to improve the access speed. U.S. Pat. No. 7,488,664B2 by Keith Cook shows a new idea to connect two DRAM cell capacitors for a dual-port DRAM cell. U.S. Pat. No. 8,890,227B1 by Wenliang Chen shows a similar two-transistor structure with that of U.S. Pat. No. 7,505,299B2.

A difference is that U.S. Pat. No. 8,890,227B1 uses an N-type transistor and a P-type transistor for a two-transistor cell. The DRAM cell of U.S. Pat. No. 8,890,227B1 also uses two capacitors, which can make the capacitor size double. The use of P-type transistor can eliminate boost voltage VPP, which is used for word-line drive in widely used conventional DRAMs, and this means stand-by current for VPP pumping is eliminated.

Next, a functionality of a conventional DRAM0is explained by using a block diagram of a conventional DRAM0, which includes plural number of one-transistor DRAM cell100-1shown inFIG. 1.FIG. 2Ashows a simplified memory array8A of conventional one-transistor and one capacitor DRAM cell and control blocks thereof. For this explanation, the simplified memory array8A has a 4×5 structure, namely, four rows by five columns, memory cells.FIG. 2Bshows an equivalent circuit of a conventional one-transistor and one capacitor DRAM cell100-1.

The conventional DRAM0includes a memory array8A including a plurality of a column units108A. The column unit108includes a pair of bit-lines116, a BLy or a BLyB (y=i, j, k, l or m), and a plurality of DRAM cell units MC100-1. The DRAM cell unit MC100-1includes an N-type transistor32, and the N-type transistor32includes a gate being13-1connected to a world-line WLx (x=i, j, k or l), a first source/drain14-1including a cell-node52and being connected to a capacitor35, a second source/drain14-1including a cell-plate-node56which is connected to a bit-line BLy (y=i, j, k, l or m). The DRAM cell unit MC100-1further includes a capacitor35including two electrode plates; a first plate being connected to the cell-node52, a second plate connected to a cell plate at a node56; the cell-plate node56connected to a plate potential VPLT which is generated by a VPLT generator2-7.

The conventional DRAM0further includes a row decoder3, including a plurality of row decoder units XDCs107, which selecting a word-line WLx (x=i, j, k or l) among a plurality of word lines according to an internal ROW address XAx. The internal Row address XAx is generated by an address buffer2-4A, and a boosted level potential VPP, which is generated by VPP generator2-2, is supplied to the Row decoder3for driving a selected word-line WLx to the boosted voltage level VPP.

The conventional DRAM0further includes a column decoder5including a plurality of column decoder units YDCs118which is provided for selecting a column switch unit YSW among from column switches115by a Column switch signal YDy (y=i, j, k, l or m) according to the internal column address YAy (y=i, j, k, l or m) which is generated by the address buffer2-4A. The selected column-switch YSW connects a bit-line pair, Bly and BLyB, to a relevant data-bus pair DBy, DBiB (y=i, j, k, l or m), respectively.

The conventional DRAM0further includes a BL equalize circuit111including a plurality of bit-line equalize units BLEs102which is provided for equalizing the voltage levels of a connected bit line pair, BLy and BLyB (y=i, j, k, l and m), in a DRAM's reset cycle by an inputted bit-line equalize signal EQ at a reset timing. The bit-line equalize signal EQ charges the voltage level of the bit-line pairs to a bit-line precharged voltage level VBL. In this case, generally, the VBL equals to half of a peripheral circuit source voltage VPERI. The voltage VBL is generated by a BL voltage generator2-6.

The conventional DRAM0further includes a sense amps and I/O control circuit7. In the circuit7, a sense amplifier circuit114including a plurality of sense amplifier units, each of which is connected to a common pull up node VSP and a pull-down node VSN. Data bus amplifiers109includes a plurality of amplifier units AMP, each of which connected to corresponding data bus pairs DBy, DBiB (y=i, j, k, l or m). A sense amplifier driver113includes a sense amplifier pull-up transistor119, a sense amplifier pull-down transistor120and an inverter113, which is driven by a sense amplifier drive signal SAD generated by a “Input buffers and memory control signal generator”2-7. A sense amplifier reset circuit SRS106is provided for initializing sense amplifier nodes VSP and VSN to a supplied VPLT voltage level.

The conventional DRAM0further includes a self-refresh control circuit9for controlling the refresh functions of the conventional DRAM0by generating a refresh Row address ARX in refresh cycles.

The conventional DRAM0further includes a memory control circuit2, which generates DRAM control signals and several internal voltages by using supplied external source voltage VDD. The memory control circuit2includes an address buffer2-4A, and a control signal input buffers and DRAM control signal generator2-4B including input buffer units and DRAM control signals generator (not shown inFIG. 1), where the control signals include external DRAM control signals such as external address ADD, memory clock CLK, Read/Write control signals R/W and so on are inputted to the memory control circuit2from a CPU1. The memory control circuit2further includes a cell plate voltage VPLT generator2-7, a peripheral voltage VPERI generator2-1, a boost voltage VPP generator2-2, an Array voltage generator2-3, and a bit-line voltage generator2-6.

A source voltage for peripheral circuit blocks in the Memory control2is a VPERI, which is generated by a VPERI generator2-1in the memory control2. The VPERI is used almost all the memory control blocks as shown inFIG. 1.

FIG. 4shows a memory array8B including a plurality of DRAM cells MC2and control blocks thereof, and the DRAM cell MC2includes two transistors as proposed in the prior art provided by as U.S. Pat. No. 7,505,299 B2 and U.S. Pat. No. 8,890,227B1. Hereafter, a DRAM cell including two transistors is referred to as a “two-transistor DRAM cell”.

Since a basic structure of the MC2is originally a dual-port DRAM cell including two transistors and a common capacitor, which can be accessed from either of the two transistors as conventional one-transistor DRAM cell, the memory array8A, including one-transistor DRAM cells, and the memory array8B, including two-transistor DRAM cells, are controlled almost same circuit blocks as shown inFIG. 2AandFIG. 4. Only difference is that the two-transistor DRAM cells are driven by two word-lines and the one-transistor DRAM cell is driven by one word-line. So, the two-transistor cell DRAM's control can be done by using the circuit blocks shown inFIG. 1.

Next, improvements of the two-transistor DRAM cells, proposed by prior art, to the conventional one transistor DRAM cell by the DRAM's functional margin, are explained.

Compared prior art DRAM cells are identified and grouped into the following:

(1) A case-100A: A conventional one-transistor and one capacitor DRAM cell;

(2) A case-100B: A two-transistor DRAM cell including two N-type transistors and a capacitor being proposed by U.S. Pat. No. 7,505,299 B2;

(3) A case-100C: A two-transistor DRAM cell including two N-type transistors and two capacitors by a process technique proposed by U.S. Pat. No. 7,488,664B2; and

(4) A case-100D: A two-transistor DRAM cell changing one of the two N-type transistors in the case-100C to a P-type transistor proposed by U.S. Pat. No. 8,890,227B1.

FIG. 5Ashows a simple equivalent circuit to drive a conventional one-transistor and a one-transistor DRAM cell MCA. The equivalent circuit includes the MCA, an N-type transistor32and a capacitor C1, and word-line drive inverter INV-1, assuming a memory cell MCA is accessed by a word-line WLi selected by an internal Row address XAi. Hereafter, this circuit case is defined as a “case-100A”.

FIG. 5Bshows a simple equivalent circuit comprises a two-transistor DRAM cell MC2A, including two N-type transistors32and33, and a capacitor C1, and word-line drives107-1including inverters INV-1and INV-2. Word-lines WLiA and WLiB are activated simultaneously by a same Row address XAi as shown inFIG. 5Bas proposed by U.S. Pat. No. 7,505,299 B2. Hereafter, this circuit case is defined as “case-100B”.

FIG. 5Cshows DRAM cells' functional margin difference between the case-100A and the case-100B by comparing waveforms of a bit line pair BLi and BLiB. For clarifying an expected margin difference by the waveforms of the bit line pair, BLi and BLiB, the wave forms, just after a rising time of the word-line WLi, WLiA and WLiB, are shown magnified in a circle shown inFIG. 5C.

Next, prior art DRAM functional margin differences between a one-transistor DRAM cell in case-100A and a two-transistor DRAM cell in case-B are explained by using voltage difference, Delta-V, of a pair of bit lines, BLi and BLiB, showing waveforms at the following timings t1to t6. In this case, a positive charge, which is equivalent to a digital data “1”, is stored in the cell capacitor C1, and the N-type transistor/transistors32,33, is/are connected to a bit-line BLi. As for DRAM control signals inFIG. 5C, seeFIG. 1andFIG. 2A.

At the timing t1, a bit-line equalize signal EQ, which equalized and pre-charged the bit-line pair BLi and BLiB, before t1, to a bit line reset voltage VBL level, goes low.

At the timing t2, the word-line WLi is selected by an internal Row address XAi. The word-line voltage level goes from zero volt to boosted VPP level with some delay time.

At the timing t3, when the voltage level of the word-line WLi exceeds the threshold voltage Vtn of the N-type transistors,32and33, the N-type transistor/transistors turns/turn on, and then, the charge stored in the memory cell C1is transferred to the connected bit-line BLi.

Because the charge stored in C1had a polarity of plus, the voltage level of the connected bit line BLi gradually goes to slightly higher level than that of the bit-line equalized voltage level VBL from the timing t3until to the timing t4.

“Delta-V” shown inFIG. 5Cis a voltage difference between BLi and BLiB, which is generally regarded as an indicator of the DRAM's sensing margin by those skilled in the art. Because the opposite bit-line BLiB of the complementary bit line remains at the bit-line equalize voltage level VBL, a voltage difference Delta-V gradually widens. Since a spreading speed of Delta-V is proportional to the on-conductance of the transistor of the DRAM cell, as shown in the circle ofFIG. 6C, the spreading speed of the voltage difference between the bit line pair wave-forms,100BH and100BL, of case-100B, is faster than that of the voltage difference in the case-100A of the waveforms100AH and100AL of the bit-line pair.

In the case-100B, because two word-lines WLA and WLiB, are simultaneously activated and two-transistors are used for transferring a charge stored in the capacitor C1to the bit-line BLi, the on-resistance of the case-100B is half compared with that of the case-100A. The halved on-resistance will speed up the transfer of the charge from the capacitor C1to the bit-line BLi

At the timing t4, a sense-amp activation signal SAD, shown inFIG. 2A, goes high and sense-amps114are activated. The “Delta-V” developed by the charge transferred from capacitor C1to the bit-line pair, BLi and BLiB at the timing t3, is amplified by a sense-amp103the latter being connected to the corresponding bit-line pair.

The functional margin of the sense amplifier is related to the delta-V at the timing t4as known by those in the art. As shown inFIG. 5C, the case-100B has the ability to make the DRAM access faster than the case-100A because charge transfer from capacitor C1to bit-line BLi in the case-100B is much faster than that of case-100A. This is one of the merits being proposed by U.S. Pat. No. 7,505,299B2.

At the timing t5, the column switch signal YDi goes high and turns-on a relevant column switch unit YSW. Before the timing t5, a data bus pair121DBi and DBiB, which is supposed to be connected to the bit-line pair116, BLi and BLiB, is equalized and pre-charged to a peripheral source voltage level VPERI. The data on the bit-line pair116, BLi and BLiB, starts to be sent to a corresponding data bus pair121Di and DiB through the column switch unit YSW.

At the timing t6, just after the moment when the selected column switch YSW is on, Delta-V which is widened before the timing t5will show a sudden narrowing, looks like a “bottleneck”, in a short period to a minimum value by a charge flow from the data-bus pair121to the bit-line pair116. The narrowest Delta-V value can be an indicator of the bit line of the DRAM to data-bus data transfer margin.

In this case, the minimum Delta-V value at around the timing t6is defined as “V100A” in the case-100A and “V100B” in the case-100B. As shown inFIG. 5B, when the capacitor size is same as the case-100A and the case-100B, a V100A and a V100B is same. This means that use of the two transistors can make sensing margin higher, however, the bit-line pair to data-bus pair data-transfer margin will not be improved without increasing the capacitor size.

FIG. 6Ashows a simple equivalent circuit comprises a two-transistors DRAM cell MC2C including two N-type transistors,32and33, and two capacitors, C1and C2, and word-line drives INV-1and INV-2. A basic idea thereof is proposed by prior art as U.S. Pat. No. 7,505,299 B2 but the capacitor is replaced to connected-two-capacitor idea according to U.S. Pat. No. 7,488,664B2. Hereafter, this circuit case is defined as “case-100C”.

FIG. 6Bshows a functional margin difference of the DRAM cells between the case-100A and the case-100C as explained by usingFIG. 5C. In the case-100C, because the capacitor size is doubled, bit-line to data-bus transfer margin is further improved.

The maximum voltage level of the word-line WLi in the case-100A, case-100B and case-100C is a boosted level VPP, which is generated by a VPP voltage pumping circuit2-2A in the VPP generator2-2. To be prepared for an unexpected DRAM access and asynchronously occurred self-refresh cycles, the VPP voltage pumping circuit2-2A has to be kept running even in a stand-by period.

For DRAMs which use conventional one-transistor DRAM cell, the VPP pumping in stand-by period is one of the main components of conventional stand-by power consumption, which leads to deterioration of battery226life.

When it comes to the case-100B and case-100C, because two-transistor DRAM cells require to activate two word-line WLiA and WLiB at the same timings for one bit DRAM access, the two-transistor DRAM need to drive double number of word-lines. This means that loading of the VPP generator is doubled compared with that of one-transistor DRAM cells.

By the doubled VPP loading, a VPP leakage current is expected to be also doubled, which requires much stronger VPP pumping to the VPP voltage pumping circuit2-2A. The stronger VPP pumping will increase DRAM stand-by power. This stand-by power consumption increase is an evident short coming of the prior arts, case-100B and case-100C. Keeping the merits of the case-100C, the idea proposed by U.S. Pat. No. 8,890,227B1, eliminates or lowers the stand-by power consumed in the VPP generator2-1.

FIG. 6Cshows a simple equivalent circuit including a two-transistors DRAM cell MC2C, which includes two different type two-transistors,32and34, and capacitors C1and C2, and word-line drives107-2including INV-1and INV-2; the idea thereof is proposed by U.S. Pat. No. 8,890,227B1. Hereafter, this circuit case is defined as “case-100D”.

FIG. 6Dshows a functional margin difference of the DRAM cells between the case-100A and the case-100D as explained inFIG. 5C. In the case-100D, because the capacitor size is doubled same as case-100C, the bit-line to data-bus transfer margin is improved as compared with the case-100A. The case-100D's evident difference with case-100C is that an N-type transistor33in the case-100C is changed to a P-type transistor34and a word-line drivers107-2, including an inverter INV-1and an inverter INV-3, they do not use boosted voltage VPP, and the INV-1and the INV-2are serially connected to generate different polarity word-lines, WLi and WLiB, in order to drive the N-type transistor32and P-type transistor34at a same timing. The evident characteristic of case-100D, using N-type transistor and P-type transistor in two-transistor DRAM cell as proposed by U.S. Pat. No. 8,890,227B1, is not to use boosted level VPP for word-line drives. Not to mention, as far as the two-transistor DRAM cells, MC2C and MC2D, are fabricated by using conventional DRAM process, doubled capacitor size is effective for enhancing DRAM functional margin as show inFIG. 6BandFIG. 6D.

Next, a disadvantage of the above explained prior arts are explained.

In the DRAMs, it is believed that a DRAM cell capacitor needs to have around 15-fF capacitance for keeping stable functionality by those skilled in the art. By using the two-transistor cells, MCF or MC2D, enough capacity can be expected as far as standard DRAM process is used. However, even using the two-transistor DRAM cells using two DRAM cell capacitors, MC2C or MC2D, as for an embedded DRAM memory macro based on cheaper general logic process, enough DRAM cell capacitance cannot be obtained. This is the disadvantage of the prior arts mentioned above.

SUMMARY OF THE INVENTION

The objective of the present invention is to provide a semiconductor memory device including new DRAM cells, capable of improving the disadvantages of the prior arts based on the two-transistor DRAM cells to be fabricated by using expensive DRAM process.

According to a first aspect of the present invention, a semiconductor device is provided which includes a memory array (8B) including a plurality of DRAM cells (MC2), two synchronously operated complementary word-lines (WLi, WLiB), and a bit-line (20) including a layer which is a first metal (20). Each of DRAM cell (MC2) is selected among from the plurality of DRAM cells by a row address (XAx), and a column address (YAy) which is generated by an address buffer (2-4A). The two synchronously operated complemental word-lines (WLi, WLiB) include a high-active word-line (WLi), and a low-active word-line (WLiB).

Each of the DRAM cells (MC2) includes an N-type transistor (32) including a gate (13-1), a first source/drain region (14-1), and a second source/drain region (14-1); a P-type transistor (34) including a gate (13-2), a first source/drain region (14-2), and second source/drain region (14-2); and a common capacitor (CCOM).

The gate (13-1) of the N-type transistor (32) is connected to the high-active word-line (WLi), the first source/drain region (14-1) of the N-type transistor (32) is connected to the common capacitor (CCOM) directly, and the second source/drain region (14-1) of the N-type transistor (32) is connected to the bit-line (20) via a cell contact (20-1,20-3or20-5,20-7). The gate (13-2) of the P-type transistor (34) is connected to the low-active word-line (WLiB), the first source/drain region (14-2) of the P-type transistor (34) is connected to a common capacitor (CCOM) directly, and the second source/drain region of the P-type transistor (34) is connected to the bit-line (20).

The plurality of DRAM cells (MC2) is aligned in a bit-line direction (BLDIR) of the bit-line (20) so that the common capacitor (CCOM) is arranged at substantially a center of each of the DRAM cell (MC2). The common capacitor (CCOM) includes a first capacitor element (C1); a second capacitor element (C2); and a third capacitor element (C3).

The first capacitor element (C1) includes an outer metal cylinder (70), an inner metal cylinder (72), and a dielectric layer (71). The outer metal cylinder (70) of the first capacitor element (C1) includes a sidewall metal layer (70S) and a bottom metal layer (70B), the inner metal cylinder (72) of the first capacitor element (C1) includes a side-wall metal surface (72S) and a bottom metal layer (72B), the dielectric layer (71) of the first capacitor element (C1) includes a side-wall dielectric layer (71S) and a bottom dielectric layer (71B), and the bottom metal layer (70B) of the outer metal cylinder (70) is connected to a surface (SURN) of the first source/drain region (14-1) of the N-type transistor (32).

The second capacitor element (C2) includes an outer metal cylinder (73), inner metal cylinder (75), and a dielectric layer (74). The outer metal cylinder (73) of the second capacitor element (C2) includes a sidewall metal layer (73S) and a bottom metal layer (73B), the inner metal cylinder (75) includes a side-wall metal surface (75S) and a bottom metal layer (72B), the dielectric layer (74) of the second capacitor element (C2) includes a side-wall dielectric layer (74S) and a bottom dielectric layer (74B), and the bottom metal layer (73B) of the outer metal cylinder (73) is connected to a surface (SURP) of the first source/drain region (14-2) of the P-type transistor (34).

The third capacitor element (C3) includes a bottom metal electrode plate (48-1), a top metal electrode plate (49-1), and a dielectric layer (50-1). The bottom metal electrode plate (48-1) of the third capacitor element (C3) is connected to the sidewall metal layer (70S) of the outer metal cylinder (70) of the first capacitor element C1, and the sidewall metal layer (73S) of the outer metal cylinder (73) of the second capacitor element C2. The top metal electrode plate (49-1) of the third capacitor element (C3) is connected to the sidewall metal layer (72S) of the inner metal cylinder (72) of the first capacitor element C1, and the sidewall metal layer (75S) of the inner metal cylinder (75) of the second capacitor element (C2).

The dielectric layer (50-1) of the third capacitor element (C3) is connected to the side-wall dielectric layer (71S) of the dielectric layer (71) of the first capacitor element (C1), and the side-wall dielectric layer (74S) of the dielectric layer (74) of the second capacitor element (C2).

According to a second aspect of the present invention, there is provided a semiconductor memory device including a memory array (8B), which includes a plurality of DRAM cells (MC2), two synchronously operated complemental word-lines (WLi, WLiB), and a bit-line (20) including a first metal layer. Each of the DRAM cells (MC2) is selected among from the plurality of DRAM cells by a row address (XAx) and a column address (YAy) which is generated by an address buffer (2-4A), and the two synchronously operated complemental word-lines (WLi, WLiB) includes a high-active word-line (WLi) and a low-active word-line (WLiB).

Each of the DRAM cells (MC2) includes an N-type transistor (32) including a gate (13-1), a first source/drain region (14-1) and a second source/drain region (14-1); a P-type transistor (34) including a gate (13-2), a first source/drain region (14-2) and a second source/drain region (14-2); and a common capacitor (CCOM).

The gate (13-1) of the N-type transistor (32) is connected to the high-active word-line (WLi), the first source/drain region (14-1) of the N-type transistor (32) is connected to the bottom electrode of the common capacitor (CCOM); the second source/drain region (14-1) of the N-type transistor (32) is connected to the bit-line (20) via a cell contact (20-1,20-3or20-5,20-7).

The gate (13-2) of the P-type transistor (34) is connected to the low-active word-line (WLiB), and the first source/drain region (14-2) of the P-type transistor (34) is connected to the bottom electrode of the common capacitor (CCOM); the second source/drain region of the P-type transistor (34) is connected to the bit-line (20).

The plurality of DRAM cells (MC2) is aligned in a bit-line direction (BLDIR) of the bit-line (20) so that the common capacitor (CCOM) is arranged at substantially a center of each of the DRAM cells (MC2).

The top electrode of the common capacitor CCOM is connected to the storage plate supply (VPLT) via the first available interconnect metal which runs in the word-line direction (WLDIR).

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following detailed description, numerous specific details are set forth to provide a thorough understanding of claimed subject matter. For purposes of explanation, specific numbers, systems and/or configurations are set forth, for example. However, it should be apparent to one skilled in the relevant art having benefit of this disclosure that claimed subject matter may be practiced without specific details.

In other instances, well-known features may be omitted and/or simplified so as not to obscure claimed subject matter. While certain features have been illustrated and/or described herein, many modifications, substitutions, changes and/or equivalents may occur to those skilled in the art.

It is, therefore, to be understood that appended claims are intended to cover any and all modifications and/or changes as fall within claimed subject matter. Reference throughout this specification to one implementation, an implementation, one embodiment, an embodiment and/or the like may mean that a particular feature, structure, or characteristic described in connection with a particular implementation or embodiment may be included in at least one implementation or embodiment of claimed subject mat ter. Thus, appearances of such phrases, for example, in various places throughout this specification are not necessarily intended to refer to the same implementation or to any one particular implementation described.

Furthermore, it is to be understood that particular features, structures, or characteristics described may be combined in various ways in one or more implementations. In general, of course, these and other issues may vary with context. Therefore, particular context of description or usage may provide helpful guidance regarding inferences to be drawn. Operations and/or processing, such as in association with networks, such as computer and/or communication networks, for example, may involve physical manipulations of physical quantities.

Typically, although not necessarily, these quantities may take the form of electrical and/or magnetic signals capable of, for example, being stored, transferred, combined, processed, compared and/or otherwise manipulated. It has proven convenient, at times, principally for reasons of common usage, to refer to these signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, and/or the like.

It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are intended to merely be convenient labels. Likewise, in this context, the terms “coupled”, “connected,” and/or similar terms, may be used. It should be understood that these terms are not intended as synonyms. Rather, “connected” may be used to indicate that two or more elements or other components, for example, are in direct physical and/or electrical contact; while, “coupled” may mean that two or more components are in direct physical or electrical contact; however, “coupled” may also mean that two or more components are not in direct contact, but may nonetheless co-operate or interact.

The term “coupled” may also be understood to mean indirectly connected, for example, in an appropriate context. The terms, “and”, “or”, “and/or” and/or similar terms, as used herein, may include a variety of meanings that also are expected to depend at least in part upon the particular context in which such terms are used. Typically, “or” if used to associate a list, such as A, B or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B or C, here used in the exclusive sense.

In addition, the term “one or more” and/or similar terms may be used to describe any feature, structure, and/or characteristic in the singular and/or may be used to describe a plurality or some other combination of features, structures and/or characteristics. Though, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Again, particular context of description or usage may provide helpful guidance regarding inferences to be drawn.

Referring now to the drawings, embodiments according to the present invention will be described in detail hereinafter.

Throughout the drawings to explain the embodiments, like reference characters designate like or corresponding members and the repetitive explanation will be omitted. In addition, the circuit symbol of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with no arrow mark attached is distinguished as an N-type MOSFET (NMOS transistor), while that with an arrow mark attached is distinguished as a P-type MOSFET (PMOS transistor). Hereinafter MOSFET is called just a transistor.

In drawings showing cross-sectional views, oblique views and waveforms for explaining the embodiments, where the dimensions of each part are drawn differently from the actual magnitude relation in order to clarify the explanation visually.

The process of the present invention provides methods to fabricate two major kinds of embodiments, a first embodiment and a second embodiment, and their modification embodiments for fabricating a metal-insulator-metal or MIM capacitor in a two transistor DRAM cell.

First Embodiment

FIG. 7is a cross sectional view of an example of a DRAM cell according to a first embodiment of the invention, showing a structure taken on a line A-A′ ofFIG. 8A, which shows a layout drawing of the DRAM cell.FIG. 8Ashows one example of a first memory cell layout configuration of the DRAM cell by the first embodiment of the invention.

The feature of the layout of the first embodiment of the invention is that an N-type transistor32, a P-type transistor34and a common capacitor CCOM are aligned in a bit-line direction BLDIR of the bit line20as shown inFIG. 8A, so that the common capacitor CCOM is arranged between the N-type transistor and the P-type transistor, and at substantially a center of the DRAM cell. The top electrode of the common capacitor CCOM connects to a storage plate VPLT supply line31-1which is aligned in the word-line direction WLDIR as shown inFIG. 8A.

FIG. 8Bshows a second cell layout configuration, in which a first metal layer20and a contact20-5penetrating the third insulating layer18-3.FIG. 8Cshows a third DRAM cell layout configuration, in which a second metal layer31-1, which forms a memory cell plate voltage VPLT wirings, and second metal bit-line pads20-4sare removed from the second layout configuration shown inFIG. 8B.

FIG. 9is a perspective view of key components of the first embodiment of the invention, in which the key elements includes an N-type transistor32, a P-type transistor34, and a common capacitor CCOM, which includes a first capacitor element C1, a second capacitor element C2and a third capacitor element C3. A cell plate contact23is added to the key components ofFIG. 9for a later explanation of modifications of the first embodiment of the invention. As shown inFIG. 9, the common capacitor CCOM has a shape of letter “n”.FIG. 10is a cross sectional view of the first embodiment of the invention, taken on a line X-X′ ofFIG. 9.

Next, referring toFIG. 7toFIG. 11, the key components of the first embodiment of the invention and their structures are explained.

As shown inFIG. 7, the DRAM cell100-2according to the first embodiment of the invention includes

(1) the N-type transistor32including a gate polysilicon layer13-1, which is conformally covered with a first stop layer19-1and is connected to a high-active word-line WLi;

(2) a first source/drain region14-1having a cell-node52on a surface thereof, and a second source/drain region14-1electrically connected to a bit-line20through a first contact20-7penetrating a first insulating layers18-1and a second insulating layer18-2, and a second contact20-5penetrating a third insulating layer18-3via a third metal layer20-4;

(3) the P-type transistor34, including a gate polysilicon gate13-2, which is typically covered with the first stop layer19-1and is connected to a low-active word-line WLiB, a first source/drain region14-2having a cell-node54on a surface thereof, and a second source/drain region14-2electrically connected to the bit-line20through a second contact20-7penetrating a first insulating layers18-1and a second insulating layer18-2, and a first contact20-5penetrating a third insulating layer18-3via a second metal layer20-4; and

(4) the common capacitor CCOM including parallelly-connected three elements, which include a first capacitor element C1, a second capacitor element C2and a third capacitor element C3.

In this case, the first capacitor element C1includes an outer metal cylinder70, an inner metal cylinder72and a dielectric layer71, the outer metal cylinder70including a sidewall metal portion70S and a bottom metal layer portion70B. The inner metal cylinder72includes a side-wall metal portion72S and a bottom metal layer portion72B, and the dielectric portion71includes a side-wall dielectric layer71S and a dielectric bottom portion71B. The bottom metal layer portion70B of the outer metal cylinder70is connected to a surface SURN of the first source/drain region14-1of the N-type transistor32as shown inFIG. 9.

The second capacitor element C2includes an outer metal cylinder73, inner metal cylinder75and a dielectric layer74, the outer metal cylinder73including a sidewall metal portion73S and a bottom metal layer portion73B. The inner metal cylinder75includes a side-wall metal portion75S and a bottom metal layer72B, and the dielectric layer74includes a side-wall dielectric portion74S and a dielectric bottom portion74B. The bottom metal layer portion73B of the outer metal cylinder73is connected to a surface SURP of the first source/drain region14-2of the P-type transistor34as shown inFIG. 9.

The third capacitor element C3includes a bottom metal electrode plate48-1, a top metal electrode plate49-1and a dielectric layer50-1.

Next, a connection-relation among the first capacitor element C1, the second capacitor element C2and the third capacitor element C3, is explained.

In an actual fabrication process, the three capacitor elements, namely, the first to third capacitor elements C1, C2and C3are fabricated in one piece, however, for a visual understanding, the three elements are divided into three parts and shown by 3D views to explain complex electrical connections as shown inFIG. 11A.

As shown inFIG. 11A, the first capacitor element C1has a connection zone PGHA at the top portion thereof, the second capacitor element C2similarly has a connection zone PGHB at the top portion thereof, and the third (plate) capacitor element C3has two contact zones matching the PGHA and PGHB. The cylinders PGA and PGB have two-terminals, namely, an outer terminal and an inner terminal. The contact zones PGHA and PGHB similarly have two terminals, where the two terminals include a bottom terminal, and a top terminal. When the columns are connected to the plate, the outer terminal of the columns is connected to the bottom terminal of the plate, the inner terminal of the columns is connected to the top terminal of the plate, and the dielectric filling of the columns (71S,74S) and that of the top plate (50-1) are contiguous.

FIG. 12shows a first modification of the first embodiment of the invention. In an actual semiconductor process, while a contact layout mask data is rectangle the physical shape of the contact holes may be cylindrical or nearly cylindrical because angles of the rectangle are rounded. When the process was good enough, shaping a rectangle contact hole without angle rounding might be possible. Then, the inner metal cylinders72,74, outer metal cylinders70,73and via metal contact23used in the first embodiment of the invention might be rectangular shapes as shown inFIG. 12.

FIG. 13shows an equivalent circuit to drive a DRAM cell MC2E100-2, which is the invention; in terms of circuitry, all the embodiments and their modifications of the invention explained are same. Simply, the invention is an idea to add additional unique structure third capacitor element C3to a prior art being taught by U.S. Pat. No. 8,890,227B1. The functionality of the prior art has been explained by usingFIG. 6CandFIG. 6D. The circuit case has been defined as “case-100D”.

FIG. 14shows a simplified equivalent circuit of a set of word-line drivers107-3and a DRAM cell MC2E of the invention. Hereafter, this circuit case in this invention is defined as “case-100E”. A difference of the case-100E to the case-100D is that the case-E has an additional third capacitor element C3. The evident advantage of the invention is that the invention enables the prior art DRAM cell provided by U.S. Pat. No. 8,890,227B1 to fabricate an additional capacitor element between the two transistors, with increasing no or not much layout area increase, under the condition that the same semiconductor process is used. Further, the connection between the first N- and P-transistor source/drain areas is completed without using interconnect metal resource.

FIG. 15shows a functional margin difference of the DRAM cells between the case-100D and the case-100E by comparing the voltage differences Delta-V of the bit-line pairs BLi and BLiB as already explained. The timings of the control signals and wave forms inFIG. 15are same with those explained inFIG. 6D.

In the case-100E, because the third capacitor element C3is added to the case-100D by the embodiment of the invention, the voltage differences Delta-Vin the case-100E at the timing t4is wider than that in the case-100D. This means that the present embodiment improves the sensing margin in the case-100D to be better than that of the prior arts. In addition, when the minimum values of decreased voltage differences Delta-V are compared with each other between the case-100D and the case-E at around the timing t6, when a Y-switch signal YDi goes high, it is evident that “bit-line pair to data-bus pair data-transfer margin” in the case-100E becomes better because the minimum value of decreased Delta-V, V100E, in the case-100E is larger than that of the voltage difference Delta-V, V100D. This means that the first embodiment also improves the “bit-line pair to data-bus pair data-transfer margin” as compared with those of the prior arts.

FIG. 16shows a cross-sectional view of a second modification of the first embodiment of the invention. The modification is a removal of the cell plate contact23from the first embodiment of the invention. This modification is provided for supporting such a case that the cell plate voltage VPLT is supplied by a metal wiring on the second stop layer19-2. In this case, cell-plate contact23is not required; but plate supply is still needed.

Next, a simple example of how to fabricate the first embodiment of the invention is explained according to generally used process steps with reference toFIG. 24toFIG. 42.

Referring toFIG. 24, firstly, a pad oxide layer64, which is a very thin oxide layer, is grown over a silicon substrate10.

Referring toFIG. 25, by using a nitride mask30, a shallow trench hole11A is defined, and the trench hole11A is dug by oxide under-etching. After a growth of the pad oxide layer64, the layer64may be a silicon nitride (Si3N4) layer30, which is used as a photo mask for selective etching later, then the layer30is deposited by chemical vapor deposition or CVD thereon for digging a hole for a shallow trench insulating region or STI layer11. There is a large variety deposition methods of CVD such as APCVD, SACVD, LPCVD.

A trench for the STI layer11, which will electrically isolate devices, is etched into the silicon substrate10by active-area-patterning and oxide planarization or CMP, Chemical Mechanical Polish. Widely, nitride is used as CMP stop point since CMP rate is much smaller in nitride than in oxide. For one embodiment, the material of the nitride mask30may be silicon nitride, however, the nitride mask30is a sacrificial layer and may be any material that can function as an etch or planarization stop layer and that is selective to removal over surrounding layers.

Referring toFIG. 26, an oxidation of STI layer11and N-well15and P-well61formations are done. After a chemical treatment of the damaged pad oxide layer64by a high energy implantation for a formation of N-well15and P-well61on top surface of active area. As a replacement, as shown inFIG. 26, a new thin oxide layer13may be a nitride oxide layer, and the layer is grown on the surface of the N-well15, the P-well61and the STI layer by CVD. Because the gate oxide layer13determines the characteristic of transistors, the thickness thereof should be uniform and the quality thereof should be homogeneous.

Referring toFIG. 27, firstly, gate patterning is done by using a nitride mask30deposited on the poly-silicon layer13.

Not shown in theFIG. 28, the formation process of N-type transistor32and a P-transistor34is done and side-walls17sare formed at the both sides of each transistor gates13-1and13-2. Then, as shown inFIG. 28, a thin gate oxide layer12-1is formed under the gate of N-type transistor32and a thin gate oxide layer12-2is formed under the gate13-2of the P-type transistor34.

Referring toFIG. 29, a silicidation process, which is for lowering gate resistance and source/drain region resistances, is done. In this case, a silicide layer68is formed on the source/drain region14-1, source/drain region14-2and the transistors' gates13-1and13-2. For making this process-step-explanation drawing simple, the silicide layer68is not shown on drawings hereafter.

Referring toFIG. 30, a first conformal silicon oxynitride layer19-1, which is also a first stop layer, is deposited over the device structures. Then, a first thick insulating layer18-1, such as CVD deposited silicon dioxide, phosphosilicates glass (PSG), high density plasma oxide, or so, is deposited over the gate electrodes13-1and13-2. Then, the insulating layer18-1is planarized, for example by CMP to obtain a flat surface. The insulating layer18-1should have a thickness of about 600-1500 Angstroms over the gate electrodes after CMP. After the formation of flat surface a first insulator18-1as shown, the second stop layer19-2deposited over the insulating layer18-1. For example, the stop layer19-2may comprise silicon oxynitride or silicon nitride and have a thickness of between about 300 and 1000 Angstroms.

Referring toFIG. 31, next, holes42A.43A are etched, by using generally used contact etching process, through the second stop layer19-2, an insulating layer18-1and a first stop layer19-1to source/drain regions14-1and14-2, which will form the memory cell storage portions by using nitride mask30as shown inFIG. 31.

Referring toFIG. 32, then, a thin barrier metal layer24, which is composed of such as tantalum nitride or titanium nitride, is deposited over the top surface of the device structure including on the side-walls of the hole openings and the opening bottoms thereof by CVD. The thin barrier metal24works not only as a barrier, which is a help for next tungsten deposition and low resistance contact material, but the barrier metal layer24becomes one of the two capacitor plates as an important element of the first embodiment of the invention. The thin barrier metal24works not only as one of the two capacitor plates but also works as a conductor to connect the N-type transistor32to the P-type transistor34as an important element of the first embodiment of the invention.

Next, a capacitor dielectric material25, which has a high dielectric constant such as tantalum oxide, is deposited over the thin barrier metal layer24by CVD. As a final step to form a prototype metal-insulator-metal structure, again, a thin barrier metal layer26, such as tantalum nitride or titanium nitride, is deposited onto the capacitor dielectric material layer25. The thin second barrier metal26works as one of the two capacitor plates as an important element of the first embodiment of the invention.

Referring toFIG. 33, a tungsten plug27is deposited to fill the rest of the capacitor contact hole27A. By the sandwich structure of the barrier metal layers,24and26, and dielectric layer25, a capacitor is built-up on the substrate10.

Referring toFIG. 34, by the patterning using nitride mask30, a large capacitor, shown inFIG. 33, is separated to each unit capacitor which is configured by three parallelly-connected capacitor elements including the first to third capacitor elements C1, C2and C3. In this case, the first capacitor element C1is formed on a side-wall and a bottom of the filled hole42shown inFIG. 33, the second capacitor element C2is formed on a side-wall and a bottom of the filled hole43shown inFIG. 33, and the third capacitor element C3is formed to connect the first capacitor element C1to the second capacitor element C2with its plates serving as bridge conductors.

The common capacitor CCOM is made by a parallel connection of the three first to third capacitor elements C1, C2and C3. The bottom electrode plate including76B,76S,48-1,79S and79B, of the common capacitor CCOM electrically connects a cell-node52on a first source/drain region14-1of the N-type transistor32and a cell-node54on a first source/drain region14-2of the P-type transistor34as an important element of the first embodiment of the invention.

Referring toFIG. 35, a thick second insulating layer18-2is deposited over the memory cell capacitance units formed inFIG. 34. Next, the top of the thick insulator layer18-2is planarized, for example by CMP. Then, a third stop layer19-3is deposited on the flatten insulator18-2's surface.

Referring toFIG. 36, next, bit-line contact holes20-7A are etched through the third stop layer19-3, second insulator layer18-2, second stop layer19-2, the first insulator layers18-1and the first stop layer19-1to the source/drain regions14-1and14-2, which will form memory cell bit-line nodes by using nitride mask30by the patterning using nitride mask30. At the same timing, a memory cell plate contact hole23A is also etched through the third stop layer19-3, the second insulator layer18-2to the top surface of the top metal electrode plate49-1.

Referring toFIG. 37, then a barrier metal21, which comprises titanium and titanium nitride, for example, is deposited on the inside the contact holes20-7A, then, a tungsten plug22is filled in the hole. Next, a first metal layer31is deposited over the third stop layer19-3.

Referring toFIG. 38, then, the nitride mask30is deposited over a first metal layer31. Next, by the patterning of the nitride mask30, the first metal31over the stop layer19-3is separated to cell plate pads31-1and bit-line pads20-4.

Referring toFIG. 39, after the formations of bit-line pads20-4and cell plate pads31-1, a third insulator layer18-3is deposited. Then, the insulator layer18-3is planarized, for example by CMP to obtain a flat surface and a fourth stop layer19-4is deposited.

Referring toFIG. 40, next, the nitride mask30is deposited over the fourth stop layer19-4. By the patterning of the nitride mask30, bit-line contact holes20-5A are formed by etching through the fourth stop layer19-4and the second insulator layer18-3to the bit-line pads20-4.

Referring toFIG. 41, then, a barrier metal21, which includes titanium and titanium nitride, for example, is deposited on the inside the contact holes20-5A, then, tungsten plug22is filled in the contact hole20-5A.

Referring toFIG. 42, finally, a first metal layer20, which will be a bit-line, is deposited over the fourth stop layer19-4.

Not shown inFIG. 42, but, after forming the bit-lines by the patterning of this first metal layer20by using nitride mask, by next process steps, the final form of the memory cell unit100-2of the first embodiment of the invention will be fabricated.

Second Embodiment

FIG. 17is a cross sectional view of an example of a DRAM cell according to a second embodiment of the invention, showing a structure taken on line B-B′ ofFIG. 18A, which shows an example of a first layout configuration of the DRAM cell.FIG. 18Bshows a second cell layout configuration, in which a first metal layer20and contacts20-5penetrating the third insulating layer18-3, shown inFIG. 18A, are removed.FIG. 18Cshows a third DRAM cell layout configuration, in which a second metal layer31-1, which forms a memory cell plate voltage VPLT wirings, and second metal bit-line pads20-4are removed from the second layout configuration shown inFIG. 18B.

The feature of the layout of the second embodiment of the invention is that an N-type transistor32, a P-type transistor34and a common capacitor CCOM are aligned in a bit-line direction BLDIR of the bit-line20ofFIG. 8A, so that the common capacitor CCOM is arranged between the N-type transistor32and the P-type transistor34, and at substantially a center of the DRAM cell. The top electrode of the common capacitor CCOM connects to a storage plate VPLT supply line31-1which is aligned in the word-line direction WLDIR as shown inFIG. 18A.

The main difference between the second embodiment and the first embodiment of the invention is the structure of the common capacitor CCOM. In the first embodiment of the invention, the common capacitor CCOM has a shape of letter “π”. In the second embodiment of the invention, the CCOM has a shape of an elliptic cylinder. In the first embodiment, in terms of connections to an adjacent peripheral layer, the third capacitor element C3of the common capacitance CCOM is formed on the second stop layer19-2on the first insulating layer18-1above the STI layer11. On the other hand, in the second embodiment, the third capacitor element C3is formed directly on the STI layer11as shown inFIG. 17. Beside the common capacitor CCOM's structure, other structures and features are similar to those of the first embodiment of the invention.

FIG. 19Ais a perspective view of the main parts of the second embodiment of the invention, and the main parts include the N-type transistor32, the P-type transistor34and an elliptic cylinder, which is an entity of the common capacitor CCOM. A cell plate contact23is added to the same structure for a later modification's explanation.

As show inFIG. 19A, the outline of the common capacitor CCOM has a shape of elliptic cylinder ELIP, to be more specifically, the elliptic cylinder ELIP is formed by a skin portion CSKIN forming an entity of the common capacitor CCOM including two concentric metal elliptic cylinders and an inside-plugged elliptic cylinder ELPLUG. Not shown inFIG. 19A, the skin portion CSKIN includes an inner elliptic metal cylinder ELCIN, an outer metal cylinder ELCO and dielectric layer DIEL0in-between as shown inFIG. 19B, which is a cross sectional view of the second embodiment of the invention, taken on a line XIXB-XIXB′ ofFIG. 19A.

The common capacitor CCOM of the second embodiment includes three capacitor elements, namely, a first capacitor element C1, a second capacitor element C2and a third capacitor element C3. The common capacitor CCOM of the second embodiment of the invention is formed on three locations as shown inFIG. 19A, the first capacitor element C1is formed on a surface SURN, including a cell-node52thereon, of a first source/drain region14-1of N-type transistor32. The second capacitor element C2is formed on a surface SURP, including a cell-node54thereon, of a first source/drain region14-2of the P-type transistor34. The third capacitor element C3is formed on a surface SURSTI of a shallow trench insulating region11.

As for a modification, there is such a case that the third capacitor element is formed on a stop layer being formed on the surface SURSTI of a shallow trench insulating region11.

FIG. 19Cshows a modification example of theFIG. 19B, showing such a case that a buffer polysilicon layer60is formed as a hard-etching stop layer on a surface SURSTI of shallow trench insulating region11. By the additional buffer polysilicon layer60, a center portion of bottoms, over a node57, of the outer metal cylinder ELCO and inner elliptic metal cylinder ELCIN rise to increase the third capacitor element at the portions of an AINCI and an AINCO as shown inFIG. 19C.

FIG. 20is an exploded perspective view of four main parts of the common capacitor CCOM, including the first capacitor element C1, the second capacitor element C2, the third capacitor element C3, and the inside plugged elliptic cylinder ELPLUG, which is also shown inFIG. 19A. As shown inFIG. 20, the first capacitor element C1and the second capacitor element C2have a shape of semicircular cylinder, and the third capacitor element C3has a shape of U-shaped groove.FIGS. 20A, 20B and 20Cshow respective three capacitor elements C1, C2and C3, more precisely.

In this case, the first capacitor element C1includes an outer metal semicircular cylinder76and an inner metal semicircular cylinder78as shown inFIG. 20A. The second capacitor element C2includes an outer metal semicircular cylinder79and an inner metal semicircular cylinder81as shown inFIG. 20C. The third capacitor element C3includes an outer metal U-shaped groove48-2and an inner metal U-shaped groove49-2as shown inFIG. 20B.

The first capacitor element C1is formed in metal side-wall portions76S and78S, and bottom portions76B and78B of the inner and outer metal semicircular cylinders76and78as shown inFIG. 20A. The second capacitor element C2is similarly formed in metal side-wall portions79S and81S, and bottom portions79B and81B of the inner and outer metal semicircular cylinders79and81, as shown inFIG. 20C. The third capacitor element C3is formed in each left metal side-wall portion48-2SL and48-2SL, and in each right metal side-wall portion48-2SR and49-2SR, and in each bottom portion48-2B and49-2B, of the outer and inner metal U-shaped grooves48-2and49-2as shown inFIG. 20B.

In the first capacitor element C1, a dielectric layer77is sandwiched between the outer metal semicircular cylinder76and the inner metal semicircular cylinder78as shown inFIG. 20D. In the second capacitor element C2, a dielectric layer80is sandwiched between the outer metal semicircular cylinder79and the inner metal semicircular cylinder81as shown inFIG. 20F. In the third capacitor element C3, a dielectric layer50-2is sandwiched between the outer metal U-shaped groove48-2and the inner metal U-shaped groove49-2as shown inFIG. 20E.

In the cross-sectional view shown inFIG. 20D, the portions ENDLA and ENDRA of capacitor edge structure being top end portions of the left and right metal side-wall, have a unique layer structure in a length of a distance “DIS” from a top end level of the side-walls of the first capacitor element C3, as shown inFIG. 20D, which is one of the present invention's uniqueness. In the portions ENDLA and ENDRA, the portions of the dielectric side-wall layer77S of the dielectric layer77and the metal side-wall78S of the inner metal semicircular cylinder78make a unique cross-sectional pattern, that is, two letter “L”s by the two layers are inverted up and down to face each other and to connect perfectly, while a bottom-end of the metal side-wall76S is placed below of them having the distance “DIS” from the top end of the metal side-wall78S of the inner metal semicircular cylinder78.

This structure is important feature for the common capacitor CCOM of the second embodiment of the invention, because the unique structure enables to prevent an expected electrical-short between the metal side-wall76S, which is not only the outer semicircular cylinder76and but also the bottom metal electrode plate of the first capacitor element C1, and the metal side-wall78S, which is the outer semicircular cylinder78but also the top metal electrode plate of the first capacitor element C1, by not exposing both end-planes of the metal side-walls, side-by-side on a common top-ends' cut-section plane, and by placing the top-end of the metal side-wall76S below thereof keeping an enough distance “DIS” from the top-end of the metal side-wall78S and keep an internal distance “DDIE” in-between thereof inside the side-wall of the first capacitor element C1by a thickness of the dielectric layer′77, shown inFIG. 20D.

Hereafter, the unique structure is named as “Double Inverted Facing L-shapes” for the convenience of following explanation. Note that the “Double Inverted Facing L-shapes” can be seen anywhere at the top-end of the side-wall of the first capacitor element C1.

As shown inFIG. 20E, portions ENDLC and ENDRC have also the same “Double Inverted Facing L-shapes” at the same places with the portions ENDLA and ENDRA. As the portions ENDLA and ENDRA, the portions ENDLC and ENDRC also work to prevent outer metal U-shaped groove48-2, which is the bottom metal electrode plate of the third capacitor element C3, and the inner metal U-shaped groove49-2's electrical short, where the inner metal U-shaped groove49-2is the top metal electrode plate of the third capacitor element C3, Note that, as shown in the explanation of the portions ENDLA and ENDRA, the “Double Inverted Facing L-shapes” can be seen anywhere at the top-end of the left and right side-walls of the third capacitor element C3.

As shown inFIG. 20F, portions ENDLB and ENDRB have also the same “Double Inverted Facing L-shapes” at the same places with the portions ENDLA and ENDRA. In a manner similar to those of the portions ENDLA and ENDRA, the portions ENDLB and ENDRB work to prevent outer metal semicircular cylinder79, which is the bottom metal electrode plate of the second capacitor element C2, and the inner metal semicircular cylinder81's electrical short, where the inner metal semicircular cylinder81is the top metal electrode plate of the second capacitor element C2. Note that, as shown in the explanation of the portions ENDLA and ENDRA, the “Double Inverted Facing L-shapes” can be seen anywhere at the top-end of the side-wall of the second capacitor element C2.

FIG. 20G,FIG. 20HandFIG. 20Ishow cross-sectional views cutting the first, third and second capacitor elements C1, C3and C2, horizontally, respectively. No matter where these capacitor elements C1, C2and C3being cut side-ways below the distance “DIS”, anywhere under the “Double Inverted Facing L-shapes”, Metal-Insulator-Metal capacitor structure can be seen.

When it comes to the “Double Inverted Facing L-shapes”, as shown inFIG. 20J,FIG. 20KandFIG. 20L, top views of the first capacitor element C1, the third capacitor element C3and the second capacitor element C2show the physical characteristic evidently, respectively.

In the top views, the top-ends of the outer semicircular cylinders' sidewalls, the metal side wall76S for the first capacitor element C1, the metal side wall48-2S for the third capacitor element C3and the metal side wall79S for the second capacitor element C2, are not observed: because they are hidden by the dielectric side-wall77S, the dielectric layer50-2S and the dielectric side-wall80S by the “Double Inverted Facing L-shapes”.

In summary of the characteristics of the second embodiment of the invention, the CSKIN, shown inFIGS. 19A, 19B and 19C, is an entity of the common capacitor CCOM including a Metal-Insulator-Metal or M-I-M capacitor composed of a metal side-wall portion and a bottom metal layer portion, and the edge-line portion of the top-end of the CSKIN have the “Double Inverted Facing L-shapes” structure all over for ensuring the protection of expected current leak problem between the edge of the top metal electrode plate and the edge of the bottom metal electrode plate of the common capacitor CCOM.

The unique cross-sectional pattern, “Double Inverted Facing L-shapes” is one of important features of the second embodiment of the invention.

FIG. 20Mis a perspective view of a first modification of the first modification of the second embodiment of the invention. In an actual semiconductor process, when a contact layout mask data size is made by using around minimum design rule size when conventional semiconductor process technology is used, even if a rectangle contact mask data is used, the physical shape of the contact hole becomes cylindrical or nearly cylindrical because angles of the rectangle are rounded. However, when the contact process was good enough to shape a rectangle hole without not so much angle rounding, rectangle shape common capacitor in the second embodiment might be considered as shown inFIG. 20M, in which the cell-plate contact23and common capacitor CCOM's actual outline RECT have shapes of rectangular as shown inFIG. 20M.

FIG. 21shows a second modification of the second embodiment of the invention. This is a modification where there is no cell-plate contact32and no second metal line31-1to which the cell plate voltage VPLT is supplied. Instead of the cell-plate contact32and second metal31-1, the second modification of the second embodiment has a second metal layer31-1electrically connected to the top metal electrode plate49-1of the third capacitor C3for a wiring to the cell plate voltage VPLT.

FIG. 22shows a third modification of the second embodiment of the invention. This is a modification to add a buffer polysilicon gate60over a shallow trench insulating region11as shown inFIG. 22. The buffer polysilicon gate60works as a reliable etching stop when forming a hole in which the common capacitor CCOM is fabricated. Without a hard-stop layer as the buffer polysilicon gate60over a shallow trench insulating region11, there is such a risk that an over-etching might erode the shallow trench insulating region11, and might cause an electrical short between an N-type transistor and a P-type transistor.

FIG. 23shows a modification of the second modification of the second embodiment of the invention. As shown inFIG. 23, a buffer polysilicon gate60is added to the second modification of the second embodiment, which is shown inFIG. 21.

Next, how to fabricate the second embodiment of the invention is explained according to the following process steps with reference toFIG. 43toFIG. 51. Previous process steps beforeFIG. 43is omitted because the process step beforeFIG. 43are similar to the process steps with F26-30used for the explanation of the first embodiment.

Referring toFIG. 43, by using contact etching process, a big hole44A is etched through a second stop layer19-2, a first insulating layer18-1and a first stop layer19-1to the surfaces of source/drain regions,14-1and14-2, and shallow trench insulating region11.

Referring toFIG. 44, not shown, a first barrier metal layer24made of such as tantalum nitride or titanium nitride, is deposited over the top surface of the device structure including on the inside side-walls and a bottom surface of the big contact hole44A shown inFIG. 43by CVD.

Not explained detailed process here, after forming a first metal electrode plate24-1by processing the deposited first barrier metal layer24, which is supposed to be a bottom metal electrode of the common capacitor CCOM, a capacitor dielectric material25, which has a high dielectric constant such as silicon oxide, silicon nitride, silicon oxy-nitride, or tantalum oxide, is conformally deposited over the surface of all top structures including the first metal electrode plate24-1.

Next, as a final step to form a metal-insulator-metal structure, a second barrier metal layer26, which is supposed to be a top metal electrode of the common capacitor CCOM, is deposited over the capacitor dielectric material layer25, which is made of such as tantalum nitride or titanium nitride.

Then, by removing the deposited capacitor dielectric material layer25and the deposited second barrier metal layer26on the second stop layers19-2, the first insulating layers18-1thereon, a second metal electrode plate26-1, which is supposed to be a top metal electrode of the common capacitor CCOM, is formed with a dielectric material plate25-1.

Here, a formation of a basic structure of the common capacitor CCOM, including the first metal electrode plate24-1, the dielectric material plate25-1and the second metal electrode plate26-1, is completed as shown inFIG. 44.

As explained above, the common capacitor CCOM including three capacitor elements, namely, the first to third capacitor elements C1, C2and C3as shown inFIG. 20, is formed.

Referring toFIG. 45, a second tungsten plug layer27is deposited over all the surface of the structure by CVD. Then, the cavity of the big contact hole44A is filled with the tungsten plug layer27.

Referring toFIG. 46, the top surface of the deposited first tungsten plug layer27is removed at the level of the second insulating layer19-2by a planarization process as Chemical Mechanical Polishing of CMP. Next, the top surface of the second insulating layer18-2is planarized, for example by CMP. Then, a third stop layer19-3is deposited on a surface of the flatten second insulating layer18-2.

Referring toFIG. 47, next, by using a patterning using nitride mask30, bit-line contact holes20-7As are defined and etched through the third stop layer19-3, second insulator layer18-2, second stop layer19-2, the first insulator layers18-1and the first stop layer19-1to the surfaces of a second source/drain regions,14-1and14-2, of the N-type and P-type transistors,32and34, respectively. At the same timing, a memory cell plate contact hole23A is also etched through the third stop layer19-3, the second insulator layer18-2to the top of a surface of the tungsten plug27as shown inFIG. 47.

Referring toFIG. 48, next, the nitride mask30is removed and a contact barrier metal21made of titanium and titanium nitride, for example, is deposited on the inside the bit-line contact holes20-7A and a memory cell plate contact hole23A, and then, a Tungsten plug layer22is deposited in the gap of the holes,20-7As and23A. Next, a second metal layer31is deposited over the third stop layer19-3as shown inFIG. 48.

Referring toFIG. 49, then, a nitride mask30is deposited over a first metal layer31. Next, by the patterning of the nitride mask30, the first metal31, shown inFIG. 48, over the third stop layer19-3is separated to cell plate pads31-1and bit-line pads20-4as shown inFIG. 49.

Referring toFIG. 50, not shown, after the formations of the bit-line pads20-4and the cell plate pad31-1, a third insulator layer18-3is deposited. Then, the insulator layer18-3is planarized, for example by CMP to obtain a flat surface and a fourth stop layer19-4is deposited. Next, the nitride mask30is deposited over the fourth stop layer19-4. Then, by the patterning of the nitride mask30, bit-line contact holes20-5A are formed by etching through the fourth stop layer19-4and the second insulator layer18-3to the bit-line pads20-4as shown inFIG. 50.

Referring toFIG. 51, then, a contact barrier metal21, which is made of titanium and titanium nitride, for example, is deposited on the inside the contact holes20-5A, then, a tungsten plug22is filled in the contact hole20-5A. Finally, a first metal layer20, which will be a bit-line, is deposited over the fourth stop layer19-4. Not shown inFIG. 51, however, after forming bit-lines by a patterning of this first metal layer20by using nitride mask, by next process steps, the final form of the memory cell unit100-2of the second embodiment of the invention will be fabricated.