Array substrate for liquid crystal display device and the seal pattern in the periphery of the display

A substrate for a display device includes a plurality of first lines on the substrate in a display area of the display device, a plurality of link lines on the substrate in a link region, the link lines electrically connected to the first lines and the link region being in a non-display area of the display device, an insulating layer on the first lines and the link lines, a plurality of second lines on the insulating layer, patterns on the insulating layer in the link region and at least partially overlapping the link lines, the patterns including an intrinsic semiconductor material, and a passivation layer on the second lines and the patterns, the passivation layer having at least one through hole exposing the intrinsic semiconductor material of at least one of the patterns.

The present invention claims the benefit of Korean Patent Application No. 2005-0097475 filed in Korea on Oct. 17, 2005, which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device, and more particularly, relates to an array substrate for a liquid crystal display (LCD) device and a manufacturing method of the same.

2. Discussion of the Related Art

Our information-based society has an increasing demand for flat panel display (FPD) devices. FPD devices include plasma display panel (PDP) devices, field emission display (FED) devices, electroluminescent display (ELD) devices, liquid crystal display (LCD) devices, and so on. Since they are small and lightweight and have low power consumption, FPD devices are taking the place of cathode ray tube (CRT) display devices.

Among the various FPD devices, LCD devices are particularly useful in notebook computers and desktop monitors, because they provide excellent resolution, color display and image quality. An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image. Liquid crystal molecules are aligned with directional characteristics resulting from their long, thin shapes and are arranged at specified pre-tilt angles. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. Varying an applied electric field influences alignment of the liquid crystal molecules. Because of the optical anisotropy of liquid crystal molecules, refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling the applied electric field, a desired image can be produced.

A typical LCD panel includes an upper substrate, a lower substrate facing the upper substrate, and a liquid crystal material layer interposed therebetween. An electric field is generated in the LCD panel by applying voltages to electrodes formed on the upper and lower substrates and changes alignment of the liquid crystal molecules, to thereby change light transmission and to display images.

In general, the LCD panel is fabricated by forming an array substrate that includes a thin film transistor as a switching element and a pixel electrode connected to the thin film transistor in a pixel region, forming a color filter substrate that includes at least red, green and blue color filters corresponding to the pixel region and a common electrode, attaching the array substrate and the color filter substrate by a seal pattern, and then injecting a liquid crystal material between the attached array substrate and color filter substrate.

A seal pattern generally contacts a passivation layer of the array substrate. In particular, because a passivation layer typically is formed of an organic insulating material, which has poor adhesion to a seal material, there exists a need to improve seal adhesion between the array substrate and the color filter substrate.

FIG. 1is a plan view illustrating an array substrate for an LCD device according to the related art, andFIG. 2is a cross-sectional view along II-II ofFIG. 1. InFIG. 1, a substrate10includes a display area AA and a non-display area NA. The non-display area NA includes a gate link region GLA, a gate pad region GPA, a data link region (not shown), and a data pad region (not shown). In the display area AA, gate lines12are formed in a horizontal direction, and data lines22are formed in a vertical direction. The gate lines12and the data lines22cross each other to define pixel regions P, and a thin film transistor Tr is formed at each crossing of the gate lines12and the data lines22.

In the gate pad region GPA, gate pads42are formed and are connected to outer driving circuits (not shown), and in the gate link region GLA, gate link lines14are formed and are connected to the gate pads42and the gate lines12. Although not shown, in the data pad region, data pads are formed and are connected to the outer driving circuits, and the data link region, data link lines are formed and are connected to the data pads and the data lines22. In addition, a passivation layer38is formed on the array substrate over the thin film transistor Tr, the gate lines12, the gate link lines14, and the data lines22.

To attach the array substrate to a color filter substrate, a seal pattern70is formed on the passivation layer38. In particular, the seal pattern70is disposed around the display area AA in the gate link region GLA and the data link region (not shown).

However, because the passivation layer38is formed of an organic insulating material, which has poor adhesion to the seal pattern70, there exists a need to improve seal adhesion between the array substrate and the color filter substrate. Thus, through holes are made in the passivation layer38, such that the seal pattern70contacts a layer other than the passivation layer.

Still, when the passivation layer38is etched for forming the through-holes, a gate insulating layer under the passivation layer is frequently etched due to thickness differences of the passivation layer or due to over-etching of the passivation layer to expose the gate link line14. As a result, corrosion along the gate link line14is likely to occur. To address this problem, the dummy patterns21are formed under the passivation layer as an etch stopper.

In particular, a plurality of dummy patterns21are formed under the passivation layer38in the gate link region GLA, are in the same layer as the data lines22, and has the same material as the data lines22. Thus, the dummy pattern21has a multi-layered structure including an amorphous silicon layer21a, a doped amorphous silicon layer21b, and a metal layer21c.

In addition, the passivation layer38is etched to form a plurality of through-holes to expose the doped amorphous silicon layer21band the metal layer21cof the dummy pattern21. As a result, in addition to contacting the passivation layer38, the seal pattern70also contacts the doped amorphous silicon layer21band the metal layer21c, to thereby provide additional adhesion between the array substrate and the color filter substrate.

To effectively prevent the gate insulating layer17from being etched when the passivation layer38is patterned, the dummy pattern21has a larger size than the through hole40. Thus, the metal pattern21cremains at the edge portion of the dummy pattern21. That is, a portion of the dummy pattern21has a three-layer structure and another portion has a two-layer structure.

Nonetheless, there may be electrical short between the metal pattern of the dummy pattern and the gate link lines. For example, when the array substrate and the color filter substrate are attached, the array substrate and the color filter substrate are under high voltage and high temperature for several hours and are pressured. The pressure can create cracks in the gate insulating layer and result hillock or migration of a metallic material for the gate link lines being in the cracks. Such metallic materials can contact the metal pattern of the dummy pattern causing an electric short and creating a defect.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an array substrate for a liquid crystal display device and a manufacturing method of the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide an array substrate for a liquid crystal display device and a manufacturing method of the same that improve adhesion of a seal pattern.

Another object of the present invention is to provide an array substrate for a liquid crystal display device and a manufacturing method of the same that reduce manufacturing costs, simplify manufacturing processes and prevent electrical short.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a substrate for a display device includes a plurality of first lines on the substrate in a display area of the display device, a plurality of link lines on the substrate in a link region, the link lines electrically connected to the first lines and the link region being in a non-display area of the display device, an insulating layer on the first lines and the link lines, a plurality of second lines on the insulating layer, patterns on the insulating layer in the link region and at least partially overlapping the link lines, the patterns including an intrinsic semiconductor material, and a passivation layer on the second lines and the patterns, the passivation layer having at least one through hole exposing the intrinsic semiconductor material of at least one of the patterns.

In another aspect of the present invention, a substrate for a display device includes a plurality of first lines on a substrate, a link line in a peripheral region of the substrate, the link line electrically connected to one of the first lines, an insulating layer on the first lines and the link line, a plurality of second lines on the insulating layer, a pattern on the insulating layer in the peripheral region and at least partially overlapping the link line, the pattern including a undoped semiconductor material, and a passivation layer on the second lines and the pattern, the passivation layer having at least one through hole exposing the undoped semiconductor material of the pattern.

In yet another aspect of the present invention, a manufacturing method of a substrate for a display device includes forming a plurality of first lines on the substrate in a display area of the display device, forming a plurality of link lines on the substrate in a link region, the link lines electrically connected to the first lines and the link region being in a non-display area of the display device, forming an insulating layer on the first lines and the link lines, forming a plurality of second lines on the insulating layer, forming patterns on the insulating layer in the link region, the patterns at least partially overlapping the link lines and an intrinsic semiconductor material, forming a passivation layer on the second lines and the patterns, and patterning the passivation layer to form at least one through hole in the passivation layer, the at least one through hole exposing the intrinsic semiconductor material of at least one of the patterns.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

FIG. 3is a plan view illustrating an array substrate for an LCD device according to an embodiment the present invention. InFIG. 3, the array substrate includes a display area AA and a non-display area NA. The non-display area NA includes a gate link region GLA, a gate pad region GPA, a data link region (not shown), and a data pad region (not shown).

In the display area AA, gate lines112are formed in a horizontal direction in the context of the figure, and data lines125are formed in a vertical direction in the context of the figure. The gate lines112and the data lines125cross each other to define pixel regions P, and a thin film transistor Tr is formed at each crossing of the gate lines112and the data lines125. A pixel electrode145is formed at each pixel region P and is connected to the thin film transistor Tr. Although not shown, one or both of the gate lines112and the date lines125may instead be formed in a non-linear direction.

In the gate pad region GPA, gate pads147are formed and are electrically connected to exterior driving circuits (not shown). In the gate link region GLA, gate link lines116are formed and are electrically connected to the gate pads147and the gate lines112. Although not shown, data pads are formed in the data pad region and are electrically connected to exterior driving circuits, and data link lines are formed in the data link region and are electrically connected to the data pads and the data lines125.

Dummy patterns121may be formed in the gate link region GLA. The dummy patterns121overlap the gate link lines116and have a single-layer structure of a semiconductor material, more particularly, an intrinsic amorphous silicon material. In addition, the dummy patterns121may function as an etch stopper during a manufacturing method, which will be explained in details later. The intrinsic amorphous silicon material is not electrically charged as compared to a metallic material. Thus, although conductive materials for the gate link lines116contact the dummy patterns21due to hillock or migration through cracks in an insulating layer, there is no electrical short problem.

A passivation layer (not shown) covers the dummy patterns121and has a plurality of through-holes144smaller than the dummy patterns121.

To attach the array substrate to a color filter substrate, a seal pattern150may be formed on the passivation layer. In particular, the seal pattern150may be disposed around the display area AA in the gate link region GLA and the data link region (not shown). Alternatively, the seal pattern150instead may be formed on a region of the color filter substrate corresponding to the gate link region GLA and the data link region (not shown) of the array substrate.

The structure of the array substrate will be explained in more detail with reference to the attached drawings of cross-sectional views.

FIG. 4is a cross-sectional view along IV-IV ofFIG. 3, andFIG. 5is a cross-sectional view along V-V ofFIG. 3. In particular,FIG. 4illustrates the pixel region including a thin film transistor in the display area, andFIG. 5illustrates a part of the gate link region including a dummy pattern. For convenience of explanation, a region in which a thin film transistor is formed also may be referred to as a switching region.

As shown inFIGS. 4 and 5, a pixel region P, a switching region TrA, and a gate link region GLA are defined on a substrate110. A gate electrode115and a gate line (not shown) are formed of a first conductive material. The gate electrode115is disposed in the switching region TrA, and the gate line is electrically connected to the gate electrode115and extended in a first direction. In the gate link region GLA, a gate link line116may be formed of the same material in the same layer as the gate line. The gate link line116is electrically connected to the gate line and may be extended from one end of the gate line.

In addition, a gate insulating layer117is formed on the substrate110including the gate electrode115and the gate link lines116. The gate insulating layer117may include an inorganic insulating material. A semiconductor layer120is formed on the gate insulating layer117in the switching region TrA. The semiconductor layer120includes an active layer120aof intrinsic amorphous silicon, e.g., undoped silicon, and an ohmic contact layer120bof doped amorphous silicon on the active layer120a. Source and drain electrodes128and130are formed of a conductive material, for example, molybdenum (Mo), on the ohmic contact layer120b. The source and drain electrodes128and130are spaced apart from each other over the gate electrode115. The ohmic contact layer120bmay have the same shape as the source and drain electrodes128and130.

Further, a data line125is formed on the gate insulating layer117and is electrically connected to the source electrodes128. The data line125crosses the gate line (not shown). The data line125may be formed of the same material in the same layer as the source and drain electrodes128and130. In addition, an intrinsic amorphous silicon pattern125a, e.g., a undoped amorphous silicon pattern, and a doped amorphous silicon pattern125bare formed under the data line125.

In the gate link region GLA, a dummy pattern121of an intrinsic amorphous silicon material is formed on the gate insulating layer117.

A passivation layer140is formed on the substrate110including the source and drain electrodes128and130, the data line125and the dummy pattern121. The passivation layer140may include an organic insulating material, such as benzocyclobutene (BCB) or photo acryl. The passivation layer140has a drain contact hole143exposing the drain electrode130and/or the ohmic contact layer120bunder the drain electrode130. The passivation layer140also has a through-hole144in the gate link region GLA exposing the dummy pattern121. The shape of the through-hole144may have about a similar shape as the dummy pattern121but smaller in size than the dummy pattern121.

Moreover, a pixel electrode145is formed on the passivation layer140in the pixel region P. The pixel electrode145is formed of a transparent conductive material and is electrically connected to the drain electrode130through the drain contact hole143. Although not shown, a portion of the pixel electrode145may overlap the data line125. Further, when the passivation layer140is over-etched, a region of the drain electrode130may be substantially entirely removed, and the ohmic contact layer120bmay be exposed through the drain contact hole143. In this case, the pixel electrode145may be connected to the exposed ohmic contact layer120band sides of the drain electrode130.

Furthermore, a seal pattern150may be formed on the passivation layer140in the gate link region GLA. The seal pattern150may contact the passivation layer140and the dummy pattern121through the through-hole144.

When the above array substrate and a color filter substrate are attached, cracks may be formed in the gate insulating layer117in the gate link region GLA due to pressures. Therefore, there may occur migration or hillock of conductive materials from the gate link lines116through the cracks, and the conductive materials from the gate link lines116may contact the dummy pattern121. However, because the dummy pattern121is not a conductor, an electrical short between the gate link lines116and the dummy pattern121can be prevented, to thereby improve device performance.

FIGS. 6A to 6GandFIGS. 7A to 7Gare cross-sectional views illustrating a manufacturing method of an array substrate according to an embodiment of the present invention. In particular,FIGS. 6A to 6Gillustrate the manufacturing method of a region of the substrate that corresponds to cross-sections along IV-IV ofFIG. 3, andFIGS. 7A to 7Gillustrate the manufacturing method of a region of the substrate that corresponds to cross-sections along V-V ofFIG. 3.

As shown inFIG. 6AandFIG. 7A, a substrate110has a pixel region P, a switching region TrA, and a gate link region GLA. The substrate110may be transparent and may be formed of glass. In addition, the switching region TrA may be within the pixel region P.

Although not shown, a gate material and a photoresist material are deposited sequentially on the substrate110, and a photoresist pattern is formed on the gate material by a photoresist coating, selective exposure and developing process. For example, the gate material may include one or more conductive materials, and the photoresist material may be coated on the substrate110, exposed to light through a mask, and developed, to thereby form the photoresist pattern.

After forming the photoresist pattern, the gate material is etched using the photoresist pattern as an etching mask to form a gate electrode115in the switching region TrA, a gate line (not shown), and a gate link line116in the gate link region GLA. After etching, remaining of the photoresist pattern is stripped from the substrate. In particular, the gate electrode115, the gate line (not shown) and the gate link line116are electrically connected to one another. For example, the gate electrode115may protrude from the gate line (not shown), and the gate link line116may extended from an end of the gate line (not shown).

As shown inFIG. 6BandFIG. 7B, a gate insulating layer117is formed on the substrate110including the gate line, the gate electrode115and the gate link line116. The gate insulating layer117may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx). Subsequently, an intrinsic amorphous silicon layer118, a doped amorphous silicon layer119, and a conductive layer122are formed on the gate insulating layer117by sequentially depositing an intrinsic amorphous silicon material, a doped amorphous silicon material, and a conductive material. The conductive layer122may include molybdenum (Mo).

As shown inFIG. 6CandFIG. 7C, a photoresist layer180is formed on the conductive layer122, and a mask191is disposed over the photoresist layer180. Then, the photoresist layer180is exposed to light through the mask191and developed to form a photoresist pattern. The mask191includes a light-transmitting portion TA that transmits about 100% of light, a light-blocking portion BA that blocks about 100% of light, and a half-transmitting portion HTA that selectively transmits light in a range of 0% to 100%.

In addition, the photoresist layer180may be a negative type, where a portion, that is exposed to light, remains after developing. In this case, the light-transmitting portion TA of the mask191corresponds to regions in which a data line and source and drain electrodes are formed, the half-transmitting portion HTA of the mask191corresponds to a region over the gate electrode116and between the source and drain electrodes and a region in which a dummy pattern is formed, and the blocking portion BA of the mask191corresponds to other regions.

Alternatively, the photoresist layer180may be a positive type, where a portion, that is exposed to light, is removed by developing. In this case, arrangements of the light-transmitting portion TA and the light-blocking portion BA of the mask191are exchanged to obtain the same pattern as when the photoresist layer180being the negative type.

As shown inFIG. 6DandFIG. 7D, the resultant photoresist pattern may have a varying thickness. In particular, a first portion of the photoresist pattern180ahas a first thickness t1and a second portion of the photoresist pattern180bhas a second thickness t2. The first thickness t1may be greater than the second thickness t2. For example, when the photoresist layer180(shown inFIGS. 6C and 7C) is the negative type, the first portion of the photoresist pattern180aand the second portion of the photoresist pattern180brespectively correspond to the light-transmitting portion TA and the half-transmitting portion HTA of the mask191(shown inFIGS. 6C and 7C), and the portion of the photoresist layer180that corresponds to the light-blocking portion BA of the mask191, is substantially removed to expose the conductive layer122.

After forming the photoresist pattern, the conductive layer122, the doped amorphous silicon layer119, and the intrinsic amorphous silicon layer118(shown inFIGS. 6C and 7C) are etched using the photoresist pattern as an etching mask to form a data line125, a source-drain pattern127, a semiconductor pattern120, and an initial dummy pattern123. In addition, an intrinsic amorphous silicon pattern125aand a doped amorphous silicon pattern125bare further formed under the data line125.

In particular, the pixel region may be defined by the intersection of the data line125and the gate line (not shown). More specifically, because the gate insulating layer117is between the data line125and the gate line (not shown), the data line125and the gate line (not shown) do not contact each other at the intersection. In addition, the source-drain pattern127is in the switching region TrA and is electrically connected to the data line125. For example, the source-drain pattern127may protrude from the data line125. Further, the semiconductor layer120is under the source-drain pattern. The initial dummy pattern123is in the gate link region GLA and includes an intrinsic amorphous silicon pattern123a, a doped amorphous silicon pattern123b, and a conductive pattern123c.

As shown inFIG. 6EandFIG. 7E, the substrate is further etched and the second portion of the photoresist pattern180bshown inFIGS. 6D and 7Dis ultimately removed. In particular, the substrate may undergo an ashing process to shape the photoresist pattern. Consequently, a portion of the source-drain pattern127, the doped amorphous silicon pattern123b, and the conductive pattern123cshown inFIGS. 6D and 7Dare exposed and etched. A dry-etching process may be used. Although the thickness of the first portion of the photoresist pattern180aalso decreases due to the ashing and etching, the first portion of the photoresist pattern remains on the substrate110covering non-exposed portions of the semiconductor layer120and the data line125.

In particular, the substrate is etched until the exposed portion of the source-drain pattern127, the doped amorphous silicon pattern123b, and the conductive pattern123c(shown inFIGS. 6D and 7D) are removed to form source and drain electrodes128and130, an ohmic contact layer120b, and an active layer120ain the switching region TrA and to expose the intrinsic amorphous silicon pattern123a. A small portion of the active layer120aand the intrinsic amorphous silicon pattern123aalso may be etched to ensure that the doped amorphous silicon pattern123bis completely removed. In particular, the active layer120afunctions as a channel of a thin film transistor, and the remaining intrinsic amorphous silicon pattern123abecomes a dummy pattern121. As a result, the data line125, the source and drain electrodes128and130, the ohmic contact layer120b, the active layer120a, and the dummy pattern121are formed through a second mask process. After etching, remaining of the photoresist pattern is stripped from the substrate.

As shown inFIG. 6FandFIG. 7F, a passivation layer140is formed on the substrate110including the source and drain electrodes128and130, the data line125and the dummy pattern121. The passivation layer140may include an organic insulating material, such as benzocyclobutene (BCB) or photo acryl.

Although not shown, a photoresist material is deposited sequentially on the substrate110, and another photoresist pattern is formed on the passivation layer140by a photoresist coating, selective exposure and developing process. After forming the photoresist pattern, the passivation layer140is etched using the photoresist pattern as an etching mask to form a drain contact hole143in the switching region TrA and to form a through-hole144in the gate link region GLA. The drain contact hole143exposes an upper surface of the drain electrode130, or a side surface of the drain electrode130and the ohmic contact layer120bunder the drain electrode130. In addition, the through-hole144exposes a portion of the dummy pattern121. For example, the through-hole144may have a shape similar to the dummy pattern121but smaller than the dummy pattern121.

A dry-etching process may be used. In particular, the passivation layer140may be over-etched to expose a portion of the drain electrode130. In particular, the dummy pattern121may function as an etch stopper in the gate link region GLA, such that the gate insulating layer117under the dummy pattern121is not removed. In the switching region TrA, the ohmic contact layer120bmay function as an etch stopper, such that the active layer120ais removed.

As shown inFIG. 6G, a pixel electrode145is formed on the passivation layer140in the pixel region P. Although not shown, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and a photoresist material are deposited sequentially on the substrate110, and another photoresist pattern is formed through a fourth mask process. After forming the photoresist pattern, the transparent conductive material is etched using the photoresist pattern as an etching mask to form the pixel electrode145. The pixel electrode145is electrically connected to the upper surface or the side surface of the drain electrode130through the drain contact hole143. Although not shown, a portion of the pixel electrode145may overlap the data line125.

As shown inFIG. 7G, a seal pattern150is formed on the passivation layer140in the gate link region GLA. The seal pattern150also contacts the dummy pattern121through the through-hole144. In addition, the seal pattern150may be formed in a non-display area including the gate link region GLA along peripheral portions of the substrate110. Further, although not shown, the seal pattern150alternatively may be formed in a region of another substrate that corresponds to the gate link region GLA, such that when the substrate110may be attached to the other substrate by the seal pattern in the gate link region GLA.

Although the patterns in the gate link region are referred to as ‘dummy’ patterns, these patterns function as etch stoppers during manufacturing and may have other functions.

An array substrate is manufactured through the above processes and then is attached to a color filter substrate. A liquid crystal material is interposed between the attached array substrate and color filter substrate to thereby fabricate a liquid crystal display device.

In embodiments of the present invention, since through-holes are formed in a passivation layer, adhesion between the passivation layer and a seal pattern is improved. In addition, dummy patterns are formed under the passivation layer, thereby preventing exposure of the gate link lines. Since the dummy patterns include intrinsic amorphous silicon, there is no electrical short between the gate link lines and the dummy patterns even if hillock occurs in the gate link region.

Moreover, because an array substrate according to embodiments of the present invention is manufactured through four-mask processes, the one-layer dummy patterns include the same intrinsic semiconductor material as the active layer of the switching element, manufacturing processes and costs are not increased. Further, the one-layer dummy patterns according to an embodiment of the present invention may be employed in other types of display devices, such as organic light emitting diode (OLED) display devices.

It will be apparent to those skilled in the art that various modifications and variations can be made in the array substrate for a liquid crystal display device and a manufacturing method of the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.