Input signal correction device

An input signal correction device for reducing power consumption is compatible with a variety of display panels, and includes an input circuit, extension/degeneration circuit, separation/recovery circuit and delay adjustment circuit operating at frequency f, demura circuit operating at frequency f/2, and adder circuit. The extension/degeneration circuit outputs a preprocessing signal increasing the input signal cycle length by 2 or outputs by degenerating the input signal to ½, based on a control signal, the demura circuit outputs a correction signal correcting the preprocessing signal from the extension/degeneration circuit, the separation/recovery circuit outputs a differential signal reducing the correction signal cycle length to ½ or reduces cycle length to ½ and outputs the same differential signal over two cycles, based on a control signal, the delay adjustment circuit outputs a delay signal delaying the input signal, and the adder circuit outputs a signal adding the differential signal to the delay signal.

TECHNICAL FIELD

The present invention relates to an input signal correction device for correcting input signals for a display panel having R, G and B subpixels.

BACKGROUND ART

Conventionally, as described in Patent Document 1, LCD, OLED, micro LED and other display panels having unequal numbers of R, G and B subpixels, also called a PenTile (registered trademark) structure, are known. Display panels having such a structure are able to secure a resolution with a small number of subpixels, and have recently been widely employed in smartphone displays and other devices.

As shown inFIG.9, in a display panel1having an RGBG pixel structure, a 1st pixel P1includes an R subpixel P1Rand a G subpixel P1G, a 2nd pixel P2includes a B subpixel P2Band a G subpixel P2G, a (2 k+1)th pixel P(2k+1)(where k is an integer greater than or equal to 1) includes an R subpixel P(2k+1)Rand a G subpixel P(2k+1)G, and a (2 k+2)th pixel P(2k+2)includes an B subpixel P(2k+2)Band a G subpixel P(2k+2)G. This display panel1may have an input signal correction device2such as shown inFIG.10, so that even if the panel body of the display panel1is structurally susceptible to mura defects, input image signals are corrected with software to remove (reduce) mura defects (hereinafter, this process will be referred to as “de-mura” or “demura”) before being output to the panel body.

The input signal correction device2includes an input circuit3configured to operate at operating frequency f and to receive input of R, G and B input signals (image signals), an extension circuit4configured to operate at operating frequency f and to output preprocessing signals RiA and BiA by extending the cycle length of an input signal Ri relating to R subpixels and an input signal Bi relating to B subpixels, out of the R, G and B input signals input to the input circuit3, by a factor of 2, a delay circuit5configured to operate at operating frequency f and to output a preprocessing signal GiA at approximately the same time as output of the preprocessing signals RIA and BiA by the extension circuit4by delaying an input signal Gi relating to G subpixels, out of the R, G and B input signals input to the input circuit3, a demura circuit6configured to operate at operating frequency f and to output correction signals ΔRo, ΔBo and ΔGo by correcting the preprocessing signals RiA, BiA and GiA, a delay adjustment circuit7configured to operate at operating frequency f and to output delay signals RiD, BiD and GiD by delaying the input signals Ri, Bi and Gi, an adder circuit8configured to output output signals Ro, Bo and Go (Ro=RiD+ΔRo, Bo=BiD+ΔBo, Go=GiD+ΔGo) by respectively adding the correction signals ΔRo, ΔBo and ΔGo to the delay signals RiD, BiD and GiD, and a clock circuit9configured to generate a clock signal of operating frequency f to be input to the input circuit3, the extension circuit4, the delay circuit5, the demura circuit6and the delay adjustment circuit7. As described in Patent Document 2, mura defects of the panel body are corrected by inputting the output signals Ro, Bo and Go to the panel body rather than directly inputting the input signals Ri, Bi and Gi.

CITATION LIST

Patent Document

SUMMARY OF INVENTION

Technical Problem

Incidentally, in the past, the mura correction performance of the input signal correction device was important for technical competitiveness, but with the marked improvements in display panel performance in recent years, reduction in power consumption is now becoming the differentiating point. In particular, increases in the screen size and processor speed of mobile devices such as smartphones has meant that batteries are more easily drained, and reduction in power consumption relating to display panels has become an issue.

In view of this, the inventors of the present application invented an input signal correction device capable of reducing power consumption (JP 2020-052410), although this input signal correction device is for display panels having unequal numbers of R, G and B subpixels, and, moreover, the semiconductor circuit that applies this input signal correction device is only compatible with a specific panel model (e.g., RGBG display panels in which G is unequal), and is not compatible with other panel models (e.g., RBGB display panels in which B is unequal, GRBR display panels in which R is unequal, display panels in which RGB are equal), thus meaning that a semiconductor circuit has to be developed and manufactured for each display panel, which is costly.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an input signal correction device capable of reducing power consumption and being compatible with a variety of display panels.

Solution to Problem

In order to solve the above problems, the present invention is an input signal correction device for correcting input signals for a display panel in which numbers of R, G and B subpixels are equal or unequal at a ratio of minority subpixels to majority subpixels of 1:N, where N is an integer of 2 or more, including an input circuit configured to operate at operating frequency f and, for each of the R, G and B subpixels, to receive input of an input signal, an extension/degeneration circuit configured to operate at operating frequency f and to receive input of a first control signal and, for each of the R, G and B subpixels, output a preprocessing signal by increasing a cycle length of the input signal by a factor of N or output a preprocessing signal by degenerating the input signal to 1/N, based on the first control signal, a correction circuit configured to operate at operating frequency f/N and, for each of the R, G and B subpixels, to output a correction signal by correcting the preprocessing signal, a separation/recovery circuit configured to operate at operating frequency f and to receive input of a second control signal and, for each of the R, G and B subpixels, output a differential signal by reducing the cycle length of the correction signal to 1/N or reduce the cycle length of the correction signal to 1/N and output a same differential signal over N cycles, based on the second control signal, a delay adjustment circuit configured to operate at operating frequency f and, for each of the R, G and B subpixels, to output a delay signal by delaying the input signal, and an adder circuit configured to, for each of the R, G and B subpixels, add the differential signal to the delay signal.

This input signal correction device may include a clock circuit configured to generate a clock signal of operating frequency f to be input to the input circuit, the extension/degeneration circuit, the separation/recovery circuit and the delay adjustment circuit, and a frequency divider circuit configured to generate a clock signal of operating frequency f/N to be input to the correction circuit, by dividing the frequency of the clock signal of operating frequency f.

Alternatively, the present invention is an input signal correction device for correcting input signals for a display panel in which numbers of R, G and B subpixels are equal or unequal at a ratio of minority subpixels to majority subpixels of 1:N, where N is an integer of 2 or more, including an input circuit configured to operate based on a clock signal of frequency f and, for each of the R, G and B subpixels, to receive input of an input signal, an extension/degeneration circuit configured to operate based on the clock signal and to receive input of a first control signal and, for each of the R, G and B subpixels, output a preprocessing signal by increasing a cycle length of the input signal by a factor of N or output a preprocessing signal by degenerating the input signal to 1/N, based on the first control signal, a correction circuit configured to operate based on the clock signal and to receive input of a clock enable signal for switching between enabling and disabling the clock signal at frequency f/N and, for each of the R, G and B subpixels, output a correction signal by correcting the preprocessing signal, a separation/recovery circuit configured to operate based on the clock signal and to receive input of a second control signal and, for each of the R, G and B subpixels, output a differential signal by reducing the cycle length of the correction signal to 1/N or reduce the cycle length of the correction signal to 1/N and output a same differential signal over N cycles, based on the second control signal, a delay adjustment circuit configured to operate based on the clock signal and, for each of the R, G and B subpixels, to output a delay signal by delaying the input signal, and an adder circuit configured to, for each of the R, G and B subpixels, add the differential signal to the delay signal.

This input signal correction device may include a clock circuit configured to generate the clock signal, and a clock enable circuit configured to generate the clock enable signal based on the clock signal.

Furthermore, the correction circuit may output the correction signal by correcting the preprocessing signal to reduce mura defects of the display panel.

Advantageous Effects of Invention

According to an input signal correction device of the present invention, power consumption can be reduced, and the input signal correction device is also compatible with a variety of display panels.

DESCRIPTION OF EMBODIMENTS

Embodiments of the invention will be described using the drawings.

FIG.1shows an input signal correction device according to the present embodiment. This input signal correction device10superposes a signal obtained by inverting the polarity of a mura signal acquired in advance on an input image signal and cancels mura defects of the panel body in a display panel11shown inFIG.2having an RGBG pixel structure similarly to the display panel1and in other display panels.

In the panel body of the display panel11, a pixel consisting of an R subpixel and a G subpixel and a pixel consisting of a B subpixel and a G subpixel are alternately arrayed horizontally and vertically. Specifically, a 1st pixel P1includes an R subpixel P1Rand a G subpixel P1G, a 2nd pixel P2includes a B subpixel P2Band a G subpixel P2G, a (2 k+1)th pixel P(2k+1)includes an R subpixel P(2k+1)Rand a G subpixel P(2k+1)G, and a (2 k+2)th pixel P(2k+2)includes a B subpixel P(2k+2)Band a G subpixel P(2k+2)G.

Also, the input signal correction device10includes an input circuit12, extension/degeneration circuits13R,13B and13G, a demura circuit14, separation/recovery circuits15R,15B and15G, a delay adjustment circuit16, an adder circuit17, a clock circuit18, and a frequency divider circuit19.

The input circuit12is configured to operate at operating frequency f and, when input signals (image signals) for the R, G and B subpixels are input, to respectively output these input signals to the extension/degeneration circuits13R,13B and13G.

The extension/degeneration circuit13R is configured to operate at operating frequency f and to receive input of a control signal SEL_R and, based on the control signal SEL_R, outputs a preprocessing signal RiA by extending the cycle length of an input signal Ri relating to R subpixels input from the input circuit12by a factor of 2 or output a preprocessing signal RiA by degenerating the input signal Ri to ½ (“degeneration” involves converting data of X pixel into data of Y pixel (Y<X) by deriving an arithmetic mean value, weighted mean value, central value, etc.).

In the extension/degeneration circuit13R, as shown inFIG.3A, an extension circuit20R that outputs the preprocessing signal RiA by extending the cycle length of the input signal Ri by a factor of 2 and a degeneration circuit21R that outputs the preprocessing signal RiA by degenerating the input signal Ri to ½ are connected to a selector22R, and the extension circuit20R is selected if the control signal SEL_R input to the selector22R is “0”, and the degeneration circuit21R is selected if the control signal SEL_R is “1”.

The control signal SEL_R is for controlling the selector22R based on the ratio of the numbers of R, G and B subpixels of the display panel to which the input signal correction device10is applied, and, here, “0” (extension) or “1” (degeneration) is determined by the ratio of the numbers of R, G and B subpixels, as shown inFIG.4.

The extension/degeneration circuit13B is configured to operate at operating frequency f and to receive input of a control signal SEL_B and, based on the control signal SEL_B, output a preprocessing signal BiA by extending the cycle length of an input signal Bi relating to B subpixels input from the input circuit12by a factor of 2 and or output a preprocessing signal BiA by degenerating the input signal Bi to ½.

In the extension/degeneration circuit13B, as shown inFIG.3B, an extension circuit20B that outputs the preprocessing signal BiA by extending the cycle length of the input signal Bi by a factor of 2 and a degeneration circuit21B that outputs the preprocessing signal BiA by degenerating the input signal Bi to ½ are connected to a selector22B, and the extension circuit20B is selected if the control signal SEL_B input to the selector22B is “0”, and the degeneration circuit21B is selected if the control signal SEL_B is “1”.

The control signal SEL_B is for controlling the selector22B based on the ratio of the numbers of R, G and B subpixels of the display panel to which the input signal correction device10is applied, and “0” (extension) or “1” (degeneration) is determined by the ratio of the numbers of R, G and B subpixels (seeFIG.4).

The extension/degeneration circuit13G is configured to operate at operating frequency f and to receive input of a control signal SEL_G and, based on the control signal SEL_G, output a preprocessing signal GiA by extending the cycle length of an input signal Gi relating to G subpixels input from the input circuit12by a factor of 2 or output a preprocessing signal GIA by degenerating the input signal Gi to ½.

In the extension/degeneration circuit13G, as shown inFIG.3C, an extension circuit20G that outputs the preprocessing signal GiA by extending the cycle length of the input signal Gi by a factor of 2 and a degeneration circuit21G that outputs the preprocessing signal GiA by degenerating the input signal Gi to ½ are connected to a selector22G, and the extension circuit20G is selected if the control signal SEL_G input to the selector22G is “0”, and the degeneration circuit21G is selected if the control signal SEL_G is “1”.

The control signal SEL_G is for controlling the selector22G based on the ratio of the numbers of R, G and B subpixels of the display panel to which the input signal correction device10is applied, and “0” (extension) or “1” (degeneration) is determined by the ratio of the numbers of R, G and B subpixels.

In the case of the display panel11having an RGBG pixel structure, the extension circuit20R is selected by the selector22R due to the control signal SEL_R being “0”, the extension circuit20B is selected by the selector22B due to the control signal SEL_B being “0”, and the degeneration circuit21G is selected by the selector22G due to the control signal SEL_G being “1”.

Then, as shown inFIG.5, when a signal R1relating to the R subpixel P1Rof the 1st pixel P1is input to the extension circuit20R of the extension/degeneration circuit13R in a first cycle, and a signal relating to an R subpixel of the 2nd pixel P2is not input to the extension circuit20R in a second cycle because such a signal does not exist, the preprocessing signal RiA obtained by extending the signal R1of the first cycle to two cycles is generated in the extension circuit20R and output from the extension/degeneration circuit13R.

A signal B2relating to the B subpixel P2Bof the 2nd pixel P2is input to the extension circuit20B of the extension/degeneration circuit13B in a second cycle, and the preprocessing signal BiA obtained by adding a dummy signal that has no data in a first cycle to the input signal B2is generated in the extension circuit20B and output from the extension/degeneration circuit13B.

A signal G1relating to the G subpixel P1Gof the 1st pixel P1is input to the degeneration circuit21G of the extension/degeneration circuit13G in a first cycle and a signal G2relating to the G subpixel P2Gof the 2nd pixel P2is input to the degeneration circuit21G in a second cycle, and the preprocessing signal GiA obtained by assigning a signal (G1+G2)/2 obtained by taking the arithmetic mean of the signal G1and the signal G2to the second cycle and adding a dummy signal in the first cycle is generated in the degeneration circuit21G and output from the extension/degeneration circuit13G.

The demura circuit14is configured to operate at operating frequency f/2 and to correct the preprocessing signals RiA, BiA and GiA and respectively output correction signals ΔRo, ΔBo and ΔGo for the R, G and B subpixels. That is, the signals R1, B2and (G1+G2)/2, which are the second cycle of the preprocessing signals RiA, BiA and GiA, are input to the demura circuit15, and signals ΔRo1, ΔBo2and ΔGo, are generated in the demura circuit14as the correction signals ΔRo, ΔBo and ΔGo, by correcting the signals R1, B2and (G1+G2)/2 based on correction data stored in the demura circuit15. At this time, the operating frequency of the demura circuit15is f/2, and thus the signal lengths of the correction signals ΔRo1, ΔBo2, and ΔGo12will be doubled (equivalent to two cycles).

The separation/recovery circuit15R is configured to operate at operating frequency f and to receive input of a control signal SEL_R and, based on the control signal SEL_R, output a differential signal ΔroR by reducing the cycle length of the correction signal ΔRo relating to R subpixels to ½ or reduce the cycle length of the correction signal ΔRo to ½ and output the same differential signal ΔRoR over two cycles.

In the separation/recovery circuit15R, as shown inFIG.6A, a separation circuit23R that outputs the differential signal ΔRoR by reducing the cycle length of the correction signal ΔRo to ½ and a recovery circuit24R that reduces the cycle length of the correction signal ΔRo to ½ and outputs the same differential signal ΔRoR over two cycles are connected to a selector25R, and the separation circuit23R is selected if the control signal SEL_R input to the selector25R is “0” and the recovery circuit24R is selected if the control signal SEL_R is “1”.

The control signal SEL_R is for controlling the selector25R based on the ratio of the numbers of R, G and B subpixels of the display panel to which the input signal correction device10is applied, and, here, is the same as the control signal that is input to the extension/degeneration circuit13R.

The separation/recovery circuit15B is configured to operate at operating frequency f and to receive input of a control signal SEL_B, and, based on the control signal SEL_B, output a differential signal ΔBoR by reducing the cycle length of the correction signal ΔBo relating to B subpixels to ½ or reduce the cycle length of the correction signal ΔBo to ½ and output the same differential signal ΔBoR over two cycles.

In the separation/recovery circuit15B, as shown inFIG.6B, a separation circuit23B that outputs the differential signal ΔBoR by reducing the cycle length of the correction signal ΔBo to ½ and a recovery circuit24B that reduces the cycle length of the correction signal ΔBo to ½ and outputs the same differential signal ΔBoR over two cycles are connected to a selector25B, and the separation circuit23B is selected if the control signal SEL_B input to the selector25B is “0” and the recovery circuit24B is selected if the control signal SEL_B is “1”.

The control signal SEL_B is for controlling the selector25B based on the ratio of the numbers of R, G and B subpixels of the display panel to which the input signal correction device10is applied, and, here, is the same as the control signal that is input to the extension/degeneration circuit13B.

The separation/recovery circuit15G is configured to operate at operating frequency f and to receive input of a control signal SEL_G, and, based on the control signal SEL_G, output a differential signal ΔGoR by reducing the cycle length of the correction signal ΔGo relating to G subpixels to ½ or reduce the cycle length of the correction signal ΔGo to ½ and output the same differential signal ΔGoR over two cycles.

In the separation/recovery circuit15G, as shown inFIG.6C, a separation circuit23G that outputs the differential signal ΔGoR by reducing the cycle length of the correction signal ΔGo to ½ and a recovery circuit24G that reduces the cycle length of the correction signal ΔGo to ½ and outputs the same differential signal ΔGoR over two cycles are connected to a selector25G, and the separation circuit23G is selected if the control signal SEL_G input to the selector25G is “0” and the recovery circuit24G is selected if the control signal SEL_G is “1”.

The control signal SEL_G is for controlling the selector25G based on the ratio of the numbers of R, G and B subpixels of the display panel to which the input signal correction device10is applied, and, here, is the same as the control signal that is input to the extension/degeneration circuit13G.

In the case of the display panel11having an RGBG pixel structure, the separation circuit23R is selected by the selector25R due to the control signal SEL_R being “0”, and the separation circuit23B is selected by the selector25B due to the control signal SEL_B being “0”, and the recovery circuit24G is selected by the selector25G due to the control signal SEL_G being “1”.

Then, when the signal ΔRo1is input as the correction signal ΔRo to the separation circuit23R of the separation/recovery circuit15R in the first cycle, a signal ΔRoR1obtained by adding a dummy signal in the second cycle to the signal ΔRo1and separating the signal ΔRo1in the first cycle is generated in the separation circuit23R and output from the separation/recovery circuit15R (seeFIG.5).

The signal ΔBo2is input as the correction signal ΔBo to the separation circuit23B of the separation/recovery circuit15B in the second cycle, and a signal ΔBoR2obtained by adding a dummy signal in the first cycle to the signal ΔBo2and separating the signal ΔBo2in the second cycle is generated in the separation circuit23B and output from the separation/recovery circuit15B.

The signal ΔGo12is input as the correction signal ΔGo to the recovery circuit24G of the separation/recovery circuit15G in the first cycle, and, in the recovery circuit24G, the signal ΔGo12is also copied to the second cycle and recovered in two cycles (signal relating to G subpixel P1Gof 1st pixel P1and signal relating to G subpixel P2Gof 2nd pixel P2) similarly to the input signal Gi, and a signal ΔGoR12is generated and output from the separation/recovery circuit15G.

The delay adjustment circuit16is configured to operate at operating frequency f and to delay the input signals Ri, Bi and Gi and respectively output delay signals RiD, BiD and GiD for the R, G and B subpixels, and, inFIG.5, in the delay adjustment circuit16, when input of the signals R1, B1and G1is received, signals RiD1, BiD1and GiD1obtained by delaying the signals R1, B1and G1are generated.

The adder circuit17is configured to output output signals Ro, Bo and Go (Ro=RiD+ΔRoR, Bo=BiD+ΔBoR, Go=GiD+ΔGoR; note that differential signals ΔRoR, ΔBoR and ΔGoR may be positive or may be negative) by respectively adding the differential signals ΔRoR, ΔBoR and ΔGoR to the delay signals RiD, BiD and GiD, and, inFIG.5, in the adder circuit17, a signal Ro1is generated by the signal ΔRo1being added to a signal RiD1, a signal Bo2is generated by the signal ΔBo2being added to a signal BiD2, a signal Go1is generated by the signal ΔGo12being added to a signal GiD1, and a signal Go1is generated by the signal ΔGo12being added to a signal GiD2.

The clock circuit18generates a clock signal of operating frequency f to be input to the input circuit12, the extension/degeneration circuits13R,13B and13G, the separation/recovery circuits15R,15B and15G, and the delay adjustment circuit16, and the frequency divider circuit19generates a clock signal of operating frequency f/2 to be input to the demura circuit14by dividing the frequency of the clock signal of operating frequency f by 2.

The input signal correction device10according to the present embodiment includes an input circuit12configured to operate at operating frequency f and to receive input of input signals Ri, Bi and Gi for the R, G and B subpixels, the extension/degeneration circuit13R configured to operate at operating frequency f and to receive input of a control signal SEL_R, and, for R subpixels, output the preprocessing signal RiA by increasing the cycle length of the input signal Ri by a factor of 2 or output the preprocessing signal RiA by degenerating the input signal Ri to ½, based on the control signal SEL_R, the extension/degeneration circuit13B configured to operate at operating frequency f and to receive input of a control signal SEL_B, and, for B subpixels, output the preprocessing signal BiA by increasing the cycle length of the input signal Bi by a factor of 2 or output the preprocessing signal BiA by degenerating the input signal Bi to ½, based on the control signal SEL_B, the extension/degeneration circuit13G configured to operate at operating frequency f and to receive input of a control signal SEL_G, and, for G subpixels, output the preprocessing signal GiA by increasing the cycle length of the input signal Gi by a factor of 2 or output the preprocessing signal GiA by degenerating the input signal Gi to ½, based on the control signal SEL_G, the demura circuit14configured to operate at operating frequency f/2 and, for R, G and B subpixels, to output the correction signals ΔRo, ΔBo and ΔGo by correcting the preprocessing signals RiA, BiA and GiA, the separation/recovery circuit15R configured to operate at operating frequency f and to receive input of a control signal SEL_R, and, for R subpixels, output the differential signal ΔRoR by reducing the cycle length of the correction signal ΔRo to ½ or reduce the cycle length of the correction signal ΔRo to ½ and output the same differential signal ΔRoR over two cycles, based on the control signal SEL_R, the separation/recovery circuit15B configured to operate at operating frequency f and to receive input of a control signal SEL_B, and, for B subpixels, output the differential signal ΔBoR by reducing the cycle length of the correction signal ΔBo to ½ or reduce the cycle length of the correction signal ΔBo to ½ and output the same differential signal ΔBoR over two cycles, based on the control signal SEL_B, the separation/recovery circuit15G configured to operate at operating frequency f and to receive input of a control signal SEL_G, and, for G subpixels, to output the differential signal ΔGoR by reducing the cycle length of the correction signal ΔGo to ½ or reduce the cycle length of the correction signal ΔGo to ½ and output the same differential signal ΔGoR over two cycles, based on the control signal SEL_G, the delay adjustment circuit16configured to operate at operating frequency f and, for R, G and B subpixels, to output the delay signals RiD, BiD and GiD by delaying the input signals Ri, Bi and Gi, and the adder circuit17configured to, for R, G and B subpixels, output the output signals Ro, Bo and Go by respectively adding the differential signals ΔRoR, ΔBoR and ΔGoR to the delay signals RiD, BiD and GiD. Due to the input signals Ri, Bi and Gi being degenerated to ½ by any or all of the extension/degeneration circuits13R,13B and13G, the operating frequency of the demura circuit14can be lowered to ½, and thus power consumption required in the demura process (mura correction) can be substantially halved.

Also, the extension/degeneration circuits13R,13B and13G are able to select whether to function as an extension circuit or as a degeneration circuit depending on control signals, and the separation/recovery circuits15R,15B and15G are able to select whether to function as a separation circuit or as a recovery circuit depending on control signals, and thus by changing the control signals for each display panel (e.g., by selecting the extension circuit and the separation circuit for subpixels that are fewer in number and selecting the degeneration circuit and the recovery circuit for subpixel that are larger in number, out of the R, G and B subpixels), the input signal correction device10is compatible with a variety of display panels, and this also leads to a significant reduction in the development cost of semiconductor circuits.

FIG.7shows another input signal correction device according to the present embodiment. This input signal correction device30superposes a signal obtained by inverting the polarity of a mura signal acquired in advance on an input image signal and cancels mura defects of the panel body in the display panel11, and, apart from the operations of the demura circuit14being different from the input signal correction device10and a clock enable circuit31being provided instead of the frequency divider circuit19, has a similar configuration to the input signal correction device10.

In the input signal correction device30, the clock enable circuit31generates a clock enable signal for switching between enabling and disabling the clock signal at frequency f/N, based on the clock signal of frequency f generated by the clock circuit18, and outputs this clock enable signal to the demura circuit14.

The demura circuit14, as shown inFIG.8, is configured to operate based on the clock signal of frequency f generated by the clock circuit18, and to receive input of the clock enable signal generated by the clock enable circuit31, and, similarly to the case of the input signal correction device10, the signals R1, B2and (G1+G2)/2, which are the second cycle of the preprocessing signals RiA, BiA and GiA, are input to the demura circuit14at the timing at which the clock enable signal is High (at this time, the clock signal is enabled, and when the clock enable signal is Low, the clock signal is disabled). In the demura circuit14, the signals ΔRo1, ΔBo2and ΔGo12are generated as the correction signals ΔRo, ΔBo and ΔGo, by correcting the signals R1, B2and (G1+G2)/2 based on correction data stored in the demura circuit14.

This input signal correction device30includes the input circuit12configured to operate based on the clock signal of frequency f, and to receive input of the input signals Ri, Bi and Gi for the R, G and B subpixels, the extension/degeneration circuit13R configured to operate based on the clock signal of frequency f and to receive input of a control signal SEL_R, and, for R subpixels, output the preprocessing signal RiA by increasing the cycle length of the input signal Ri by a factor of 2 or output the preprocessing signal RiA by degenerating the input signal Ri to ½, based on the control signal SEL_R, the extension/degeneration circuit13B configured to operate based on the clock signal of frequency f and to receive input of a control signal SEL_B, and, for B subpixels, output the preprocessing signal BiA by increasing the cycle length of the input signal Bi by a factor of 2 or output the preprocessing signal BiA by degenerating the input signal Bi to ½, based on the control signal SEL_B, the extension/degeneration circuit13G configured to operate based on the clock signal of frequency f and to receive input of a control signal SEL_G, and, for G subpixels, output the preprocessing signal GiA by increasing the cycle length of the input signal Gi by a factor of 2 or output the preprocessing signal GiA by degenerating the input signal Gi to ½, based on the control signal SEL_G, the demura circuit14configured to operate based on the clock signal of frequency f and to receive input of the clock enable signal for switching between enabling and disabling the clock signal at frequency f/2, and output the correction signals ΔRo, ΔBo and ΔGo by correcting the preprocessing signals RiA, BiA and GiA, the separation/recovery circuit15R configured to operate based on the clock signal of frequency f and to receive input of a control signal SEL_R, and, for R subpixels, output the differential signal ΔRoR by reducing the cycle length of the correction signal ΔRo to ½ or reduce the cycle length of the correction signal ΔRo to ½ and output the same differential signal ΔRoR over two cycles, based on the control signal SEL_R, the separation/recovery circuit15B configured to operate based on the clock signal of frequency f and to receive input of a control signal SEL_B, and, for B subpixels, output the differential signal ΔBoR by reducing the cycle length of the correction signal ΔBo to ½ or reduce the cycle length of the correction signal ΔBo to ½ and output the same differential signal ΔBoR over two cycles, based on the control signal SEL_B, the separation/recovery circuit15G configured to operate based on the clock signal of frequency f and to receive input of a control signal SEL_G, and, for G subpixels, output the differential signal ΔGoR by reducing the cycle length of the correction signal ΔGo to ½ or reduce the cycle length of the correction signal ΔGo to ½ and output the same differential signal ΔGoR over two cycles, based on the control signal SEL_G, the delay adjustment circuit16configured to operate based on the clock signal of frequency f and, for R, G and B subpixels, to output the delay signals RiD, BiD and GiD by delaying the input signals Ri, Bi and Gi, and the adder circuit17configured to, for R, G and B subpixels, output the output signals Ro, Bo and Go by respectively adding the differential signals ΔRoR, ΔBoR and ΔGoR to the delay signals RiD, BiD and GiD. Due to the input signals Ri, Bi and Gi being degenerated to ½ by any or all of the extension/degeneration circuits13R,13B and13G, and the clock enable signal being input to the demura circuit14, the operating frequency of the demura circuit14can be made equivalent to the input signal correction device10, and power consumption required in the demura process can be reduced.

Also, in the input signal correction device30, the extension/degeneration circuits13R,13B and13G are able to select whether to function as an extension circuit or as a degeneration circuit depending on control signals, and the separation/recovery circuits15R,15B and15G are able to select whether to function as a separation circuit or as a recovery circuit depending on control signals, and thus the input signal correction device30is also compatible with a variety of display panels similarly to the input signal correction device10.

Although embodiments of the present invention are illustrated above, the embodiments of the invention are not limited to those described above, and changes and the like can be made as appropriate within a scope that does not depart from the spirit of the invention.

For example, the panel body of the display panel to which the input signal correction device is applied is not limited to that having an RGBG pixel structure, and may have an RBGB pixel structure in which pixels including an R subpixel and a B subpixel and pixels including a G subpixel and a B subpixel are combined, an RBRG pixel structure in which pixels including a G subpixel and an R subpixel and pixels including a G subpixel and an R subpixel are combined, a pixel structure in which the numbers of R, G and B subpixels are equal, or a pixel structure including subpixels of colors other than R, G and B.

Also, in the case of a display panel in which the numbers of R, G and B subpixels are not equal, it is not essential to satisfy a ratio of minority subpixels to majority subpixels of 1:2, and, for example, a configuration may be adopted in which the ratio of minority subpixels to majority subpixels is 1:3, the extension/degeneration circuit degenerates the signal of the majority subpixels to ⅓ rather than ½, and the frequency divider circuit is a divide-by-3 frequency divider circuit rather than a divide-by-2 frequency divider circuit.

Furthermore, the control signal of the extension/degeneration circuit and the control signal of the separation/recovery circuit may be different control signals, another degeneration function such as weighted mean instead of arithmetic mean may be employed in the degeneration circuit, and correction of input signals is not limited to mura correction, and the input signal correction device according to the present invention may perform any manner of correction.

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