Tank circuit and frequency hopping for isolators

Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

BACKGROUND

The present disclosure generally relates to circuits for transmitting power across an isolation barrier and applying frequency hopping for power transmission.

Some integrated circuits include two or more voltage domains that are galvanically isolated from one another. In such integrated circuits, it may be desirable to transmit power from one domain to another. Existing circuits to transmit power from one domain to another, while maintaining galvanic isolation, suffer from a variety of drawbacks. For example, some conventional tank circuits use cross-coupled metal oxide semiconductor (MOS) transistors, which lead to poor efficiency and poor electromagnetic interference (EMI) performance.

Therefore, the inventors recognized a need in the art for circuits and methods to efficiently transmit power between galvanically-isolated domains and improve EMI performance.

DETAILED DESCRIPTION

Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

Embodiments of the present disclosure may provide controller method for generating an oscillation frequency. The method may include at a first time instance: activating a first pair of transistors of the tank circuit, each coupled between a respective terminal of an inductor having a pair of terminals and a reference voltage along a source-to-drain path of the transistor; coupling, as a result of the activating, a first of a pair of capacitors of the tank circuit provided in a signal path between a source or drain terminal of a first transistor in the first pair and a gate of a second transistor in the first pair; and coupling, as a result of the activating, a second of the pair of capacitors provided in a signal path between a source or drain terminal of the second transistor in the first pair and a gate of the first transistor in the first pair, wherein a voltage having an oscillation frequency is generated at the terminals of the inductor to transmit power over an isolation barrier.

Embodiments of the present disclosure may provide a circuit. The circuit may include a means for activating a first pair of transistors of an inductor-capacitor (LC) tank at a first time instance, each transistor coupled between a respective terminal of an inductor having a pair of terminals and a reference voltage along a source-to-drain path of the transistor. The circuit may also include a first means for coupling, as a result of the activating, a first of a pair of capacitors of the tank circuit provided in a signal path between a source or drain terminal of a first transistor in the first pair and a gate of a second transistor in the first pair. The circuit may further include a second means coupling, as a result of the activating, a second of the pair of capacitors provided in a signal path between a source or drain terminal of the other transistor in the first pair and a gate of the first transistor in the first pair, wherein a voltage having the oscillation frequency is generated at the terminals of the inductor to transmit power over an isolation barrier.

FIG. 1illustrates an oscillator circuit100according to an embodiment of the present disclosure. The oscillator circuit100may include an LC tank110controlled by a controller120. The LC tank110may include a pair of inductors L1.1, L1.2, a pair of capacitors C0.1, C0.2, a pair of double-diffused metal oxide semiconductor (DMOS) transistors D0.1, D0.2, and a pair of disabling transistors TD0.1, TD0.2.

The pair of inductors L1.1, L1.2may be coupled in series to form a center tap and a pair of terminals (VN, VP). The center tap may be coupled to a power source VDD. The pair of DMOS transistors D0.1, D0.2may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L1.1, L1.2and a reference voltage GND. The capacitor C0.1may be provided in a signal path between the inductor L1.1coupled to DMOS transistor D0.1and a gate of the DMOS transistor D0.2. Similarly, the capacitor C0.2may be provided in a signal path between the inductor L1.2coupled to DMOS transistor D0.2and a gate of the DMOS transistor D0.1. The pair of disabling transistors TD0.1, TD0.2may have their gates coupled to a control input (OFF) (logic high) and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D0.1, D0.2, respectively, and the reference voltage GND. The disabling transistors TD0.1, TD0.2may be implemented as any known transistor type (e.g., MOS, FET, BJT, DMOS, etc.).

The controller120may provide a control signal OFF (logic high) to the gates of the disabling transistors TD0.1, TD0.2to activate the disabling transistors T0.1, T0.2. When activated, the disabling transistors TD0.1, TD0.2may pull the gates of the DMOS transistors D0.1, D0.2low, thereby turning off the DMOS transistors D0.1, D0.2and disabling the LC tank210. When the disabling transistors TD0.1, TD0.2are deactivated (i.e., no OFF signal), the DMOS transistors D0.1, D0.2may be activated, coupling the capacitors C0.1, C0.2to the inductors L1.1, L1.2, respectively. Consequently, the LC tank110may resonate or oscillate at a resonance or oscillation frequency fosc and transmit power from the power source VDD to a second voltage domain130via a pair of inductors L2.1, L2.2. An isolation barrier may be provided in between inductors L1.1, L1.2and inductors L2.1, L2.2; therefore, the inductors L2.1, L2.2may be magnetically coupled to, but galvanically isolated from, the inductors L1.1, L1.2. In an embodiment, the inductors L1.1, L1.2may be the first winding of a transformer and the inductors L2.1, L2.2may the secondary winding of the transformer. A peak-to-peak voltage of an oscillation voltage of the LC tank110, between nodes VNand VP, may be two to three times the voltage of the power source VDD.

The oscillation frequency fosc of the oscillator circuit100may be related to the inductances of the inductors L1.1, L1.2, the capacitances of the capacitors C0.1, C0.2, and the capacitances of the DMOS transistors D0.1, D0.2. Therefore, the oscillation frequency fosc may be tuned by tuning the sizes of the inductors L1.1, L1.2, the capacitors C0.1, C0.2, and the DMOS transistors D0.1, D0.2during fabrication of the LC tank110. Ideally, the inductors L1.1, L1.2would have substantially the same inductances, the capacitors C0.1, C0.2would have substantially the same capacitances, and the DMOS transistors D0.1, D0.2would be sized to have substantially identical (parasitic) capacitances. In practice, however, due to manufacturing variations and other factors, the inductances and capacitances may not be perfectly matched. In one embodiment, the DMOS transistors D0.1, D0.2and the disabling transistors TD0.1, TD0.2may be fabricated as n-type transistors.

FIG. 2illustrates an oscillator circuit200according to an embodiment of the present disclosure. The oscillator circuit200may include an LC tank210, a plurality of sub-tanks240.1-240.N, and a controller220. The LC tank210may include a pair of inductors L1.1, L1.2, a pair of capacitors C0.1, C0.2, a pair of DMOS transistors D0.1, D0.2, and a pair of disabling transistors T0.1, T0.2. Each sub-tank240.1-240.N may include a pair of capacitors C1.1, C1.2-CN.1, CN.2, a pair of DMOS transistors D1.1, D1.2-DN.1, DN.2, a pair of disabling transistors TD1.1, TD1.2-TDN.1, TDN.2, and a pair of enabling transistors TE1.3, TE1.4-TEN.3, TEN.4.

In the LC tank210, the pair of inductors L1.1, L1.2may be coupled in series to form a center tap and a pair of terminals. The center tap may be coupled to a power source VDD. The pair of DMOS transistors D0.1, D0.2may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L1.1, L1.2and a reference voltage GND. The capacitor C0.1may be provided in a signal path between the inductor L1.1coupled to DMOS transistor D0.1and a gate of the DMOS transistor D0.2. Similarly, the capacitor C0.2may be provided in a signal path between the inductor L1.2coupled to DMOS transistor D0.2and a gate of the DMOS transistor D0.1. The pair of disabling transistors TD0.1, TD0.2may have their gates coupled to a control input (OFF) and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D0.1, D0.2, respectively, and the reference voltage GND.

As shown inFIG. 2, each sub-tank240.1-240.N may be coupled in parallel with the LC tank210across the pair of terminals (VN, VP) of the inductors L1.1, L1.2. In each sub-tank240.1-240.N, the pair of DMOS transistors D1.1, D1.2-DN.1, DN.2may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L1.1, L1.2and the reference voltage GND. The capacitor C1.1-CN.1may be provided in series with the enabling transistor TE1.3-TEN.3in a signal path between the inductor L1.1coupled to DMOS transistor D1.1-DN.1and a gate of the DMOS transistor D1.2-DN.2. Similarly, the capacitor C1.2-CN.2may be provided in series with the enabling transistor TE1.4-TEN.4in a signal path between the inductor L1.2coupled to DMOS transistor D1.2-DN.2and a gate of the DMOS transistor D1.1-DN.1. The enabling transistors TE1.3-TEN.3and TE1.4-TEN.4may have their gates coupled to respective control inputs (CTRL1.1-CTRLN.1). The pair of disabling transistors TD1.1, TD1.2-TDN.1, TDN.2may have their gates coupled to another control input (CTRL1.2-CTRLN.2), and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D1.1, D1.2-DN.1, DN.2, respectively, and the reference voltage GND.

The controller220may provide control signals CTRL1.2-CTRLN.2(e.g., logic high) to the gates of the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2to activate the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2. The control signals CTRL1.2-CTRLN.2each may be formed by the controller as a logical OR of the control signal OFF and an inverted corresponding one of the control signals CTRL1.1-CTRLN.1. When activated, the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2may pull the gates of the DMOS transistors D0.1, D0.2-DN.1, DN.2low, thereby turning off the DMOS transistors D0.1, D0.2-DN.1, DN.2and disabling the LC tank210and the sub-tanks240.1-240.N.

When the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2are deactivated, the DMOS transistors D0.1, D0.2may be activated, placing the capacitors C0.1, C0.2in series with the inductors L1.1, L1.2, respectively. Consequently, the LC tank210may resonate or oscillate at a resonance or oscillation frequency fosc and transmit power from the power source VDD to a second voltage domain230via a pair of inductors L2.1, L2.2. The inductors L2.1, L2.2may be magnetically coupled to, but galvanically isolated from, the inductors L1.1, L1.2. The inductors L1.1, L1.2may be the first winding of a transformer and the inductors L2.1, L2.2may the secondary winding of the transformer.

When the disabling transistors TD1.1, TD1.2-TDN.1, TDN.2are deactivated, the controller220may also activate one or more of the sub-tanks240.1-240.N with control signals CTRL1.1-CTRLN.1, respectively. The controller220may provide the control signal CTRL1.1, . . . , CTRLN.1(e.g., logic high) to the gates of the enabling transistors TE1.3, TE1.4-TN.3, TN.4to enable the enabling transistors TE1.3, TE1.4-TEN.3, TEN.4. Consequently, the DMOS transistors D1.1, D1.2-DN.1, DN.2may be activated, placing the capacitor C1.1-CN.1in parallel with the capacitor C0.1, and the capacitor C1.2-CN.2in parallel with the capacitor C0.2, thereby increasing the effective capacitance of the oscillator circuit200and decreasing the oscillation frequency fosc. Therefore, the oscillation frequency fosc may be set to a plurality of discrete values based on the combination/permutation of the sub-tanks240.1-240.N activated by the controller220. The controller220may be programmed to “hop” from one oscillation frequency fosc to another at a predetermined time step tstep by selectively activating the sub-tanks240.1-240.N based on a predetermined oscillation frequency fosc sequence. The predetermined oscillation frequency fosc sequence may last for a time period T and may be repeated thereafter. The predetermined oscillation frequency fosc sequence may be in an ascending order, a descending order, a random order, or any other suitable order.

The oscillation frequency fosc, with the sub-tanks240.1-240.N deactivated, may be tuned by tuning the sizes of the inductors L1.1, L1.2, the capacitors C0.1, C0.2, and the DMOS transistors D0.1, D0.2during fabrication of the LC tank210. Ideally, the inductors L1.1, L1.2would have substantially identical inductances, the capacitors C0.1, C0.2would have substantially identical capacitances, the DMOS transistors D0.1, D0.2would be sized to have substantially identical capacitances. In practice, however, due to manufacturing variations and other factors, the inductances and capacitances may not be perfectly matched. In one embodiment, the DMOS transistors D0.1, D0.2-DN.1, DN.2, the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2, and the enabling transistors TE1.3, TE1.4-TEN.3, TEN.4may be fabricated as n-type transistors.

The sub-tanks240.1-240.N may be fabricated to be identical such that, when activated, each sub-tank240.1, . . . ,240.N may decrease the oscillation frequency fosc by a frequency step fstep. The frequency step fstep may be tuned by tuning the sizes of capacitors C1.1, C1.2-CN.1, CN.2and the DMOS transistors D1.1, D1.2-DN.1, DN.2. Ideally, the capacitors C1.1, C1.2-CN.1, CN.2would have substantially identical capacitances and the DMOS transistors D1.1, D1.2-DN.1, DN.2would be sized to have substantially identical capacitances. In practice, however, due to manufacturing variations and other factors, the capacitances may not be perfectly matched. The time step tstep, the time period T, and the frequency step fstep may be set based on the application of the oscillator circuit200and the electromagnetic interference (EMI) requirements, for example. Further, the number of sub-tank circuits may correspond to the number of bits in the frequency hopping scheme. For example, for a 4 bit frequency hopping scheme, 15 sub-tank circuits (24−1) may be provided. The 15 sub-tank circuits and the LC tank circuit may provide 16 carriers for the 4 bit frequency hopping scheme.

FIG. 3illustrates a frequency “hopping” control method300according to an embodiment of the present disclosure. The method300may be performed by the oscillator circuit200ofFIG. 2, for example. The method300starts at step310and, at step320, a predetermined oscillation frequency fosc sequence {(t0, f0), (t1, f1), . . . , (tN, fN)} may be loaded. The predetermined oscillation frequency fosc sequence may be in an ascending order, a descending order, a random order, or any other suitable order. The predetermined oscillation frequency fosc sequence may define different oscillation frequencies at different times. At step330, the time is t0; therefore, select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=f0. At step340, the time is t1; therefore, select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=f1. At step350, the time is t2; therefore, select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=f2. The method may continue until the end of the time period T at tN, where select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=fN at step360. Thereafter, the frequency hopping steps (i.e, steps330-360) may be repeated for the subsequent time periods T.

FIG. 4illustrates an exemplary frequency hopping diagram400according to an embodiment of the present disclosure. The diagram400illustrates how an oscillation frequency fosc of an oscillator circuit (e.g., the oscillator circuit200) may be changed at a time step tstep to follow a predetermined oscillation frequency fosc sequence {(t0, f0), (t1, f1), . . . , (tN, fN)} over a time period T (e.g., by the controller220employing the method300ofFIG. 3). The predetermined oscillation frequency fosc sequence in this example is in a random order. However, as discussed, the predetermined oscillation frequency fosc sequence may also be set to be in an ascending order, a descending order, a random order, or any other suitable order.

FIG. 5illustrates a topology for an integrated circuit500according to an embodiment of the present disclosure. The integrated circuit500may include a first die502and a second die504. The first die502may include an LC tank510and a plurality of sub-tanks540.1-540.N connected in parallel with the LC tank510, and a secondary inductor550. The LC tank510may include a primary inductor512fabricated to be adjacent to the secondary inductor550such that the primary inductor512may be magnetically coupled to, but galvanically isolated from, the secondary inductor550. The secondary inductor550may be coupled to the second die540, via bonding wires for example.

The LC tank510and the sub-tanks540.1-540.N may correspond respectively to the LC tank210and the sub-tanks240.1-240.N ofFIG. 2. The primary inductor512may correspond to the pair of inductors L1.1, L1.2and the secondary inductor550to the pair of inductors L2.1, L2.2. Thus, with the layout shown inFIG. 5, the integrated circuit500may transmit power from the first die502(i.e., a first voltage domain) to the second die504(i.e., a second voltage domain via the secondary inductor550).

Several embodiments of the disclosure are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the disclosure are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the disclosure. Further variations are permissible that are consistent with the principles described above.