Pinhole-free growth of epitaxial CoSi.sub.2 film on Si(111)

Pinhole-free epitaxial CoSi.sub.2 films (14') are fabricated on (111)-oriented silicon substrates (10) with a modified solid phase epitaxy technique which utilizes (1) room temperature stoichiometric (1:2) codeposition of Co and Si followed by (2) room temperature deposition of an amorphous silicon capping layer (16), and (3) in situ annealing at a temperature ranging from about 500.degree. to 750.degree. C.

TECHNICAL FIELD 
The present invention relates to metal base transistors, and, more 
particularly, to the formation of CoSi.sub.2 films on silicon surfaces 
oriented along (111) 
BACKGROUND ART 
Epitaxial CoSi.sub.2 films have been grown on Si(111) substrates under 
ultra-high vacuum conditions using a variety of growth techniques. The 
most widely used technique is that of solid phase reactive epitaxy (SPRE), 
in which a pure cobalt layer is deposited at room temperature onto the 
substrate and then annealed at an elevated temperature. 
In addition, the techniques of molecular beam epitaxy (MBE) and reactive 
deposition epitaxy (RDE) have been examined. In the foregoing methods, 
either pure cobalt is deposited (the latter technique) or cobalt and 
silicon atoms are codeposited in stoichiometric ratio (the former 
technique) onto a silicon substrate held at an elevated temperature. 
Thin epitaxial CoSi.sub.2 films, about 1 to 100 nm thick, formed by these 
techniques generally have a high density (&gt;10.sup.7 cm.sup.-2) of pinholes 
in the silicide layer, which results in an electrical shorting problem for 
multilayer structures. 
It is known that a modified SPRE technique which utilizes the deposition of 
an amorphous silicon (a-Si) capping layer following the deposition of pure 
cobalt prior to annealing helps to reduce the size and density of pinholes 
to approximately 5.times.10.sup.6 cm.sup.-2. In the process disclosed 
herein, a modified solid-phase epitaxy (SPE) technique is used to produce 
CoSi.sub.2 layers on Si(111) which are pinhole-free within a detection 
limit of 10.sup.3 cm.sup.-2. In contrast to the deposition of pure cobalt 
used in the modified SPRE technique of the prior art, the modified SPE 
technique disclosed herein uses the room temperature codeposition of 
cobalt and silicon in the stoichiometric ratio of 1:2, followed by the 
deposition of an a-Si capping layer. 
The growth of so-called pinhole-free CoSi.sub.2 films has been reported, 
but the pinhole detection limit is generally not specified. The techniques 
of scanning electron microscopy and transmission electron microscopy have 
been used in these reports to determine the pinhole density, and these 
techniques are typically limited to a detection level of about 10.sup.5 
pinholes per cm.sup.2. Therefore, the term "pinhole-free" CoSi.sub.2 has, 
in the past, been used to describe CoSi.sub.2 films with pinhole densities 
less than or equal to .apprxeq.10.sup.5 pinholes per cm.sup.2. In the 
present disclosure, pinhole-free CoSi.sub.2 refers to a film with pinhole 
density less than 10.sup.3 per cm.sup.2. 
Recently, Henz et al, Solid State Communications, Vol. 63, pp. 445-449 
(1987) reported a pinhole-free SPE technique employing the stoichiometric 
codeposition of cobalt and silicon at room temperature, followed by 
appropriate annealing (.ltoreq.450.degree. C). No a-Si capping layer was 
used in between the codeposition and the annealing. The low annealing 
temperature is required for the pinhole-free growth, since the present 
inventors observed pinholes with densities of 10.sup.7 to 10.sup.8 
cm.sup.-2 in CoSi.sub.2 films using this technique, but annealed at 
temperatures higher than 500.degree. C. The low annealing temperature of 
.gtoreq.450.degree. C. required for pinhole-free growth in the technique 
of Henz et al results in CoSi.sub.2 films of lower crystalline quality, as 
evidenced in results by the present inventors using Rutherford 
backscattering spectroscopy in the channeling mode. Furthermore, 
CoSi.sub.2 films annealed at low temperature have higher resistivity than 
films annealed at higher temperatures. A CoSi.sub.2 film with a high 
resistivity is less desirable for device applications. 
One possible mechanism for silicide pinhole formation is the high surface 
energy of CoSi.sub.2 (111) relative to Si(111). By exposing the underlying 
silicon surface through the formation of pinholes in the CoSi.sub.2 film, 
the total energy of the epitaxial system can be reduced. One approach to 
reduce the total energy without pinhole formation is to cover the high 
energy CoSi.sub.2 surface with a silicon cap. However, the prior art a-Si 
cap technique does not achieve pinhole-free growth, since the a-Si cap is 
consumed during the silicide formation and the CoSi.sub.2 surface is 
exposed. 
Thus, a process is required for the formation of pinhole-free CoSi.sub.2 
films on Si(111) while retaining high crystalline quality of the 
subsequent epitaxial growth. 
DISCLOSURE OF INVENTION 
In accordance with the invention, a modified solid phase epitaxy technique 
is provided for pinhole-free growth of CoSi.sub.2 films on silicon 
surfaces oriented along (111). The process of the invention comprises room 
temperature codeposition of cobalt and silicon in stoichiometric ratio 
(1:2), followed by the deposition of an amorphous silicon capping layer 
and subsequent in situ annealing at a temperature ranging from about 
500.degree. to 750.degree. C. 
Since the Co/Si mixture is in a stoichiometric ratio, no additional silicon 
is consumed from either the substrate or the cap for silicide formation, 
so that the silicon cap is preserved and covers the high energy CoSi.sub.2 
surface. Thus, the energetic driving force for pinhole formation is 
removed, and pinhole-free CoSi.sub.2 films can be fabricated with 
annealing temperatures as high as 750.degree. C. Furthermore, the 
amorphous silicon cap is converted to crystalline silicon in the annealing 
process and serves as a template for subsequent silicon overgrowth, which 
is expected to improve surface morphology. 
No pinholes can be detected in the resulting CoSi.sub.2 films, with a 
detection resolution of 10.sup.3 cm.sup.-2 CoSi.sub.2 films grown without 
the silicon cap are found to have a pinhole density of greater than 
2.times.10.sup.7 cm.sup.-2 when annealed at similar temperatures. This is 
the first pinhole-free growth of epitaxial CoSi.sub.2 films at annealing 
temperatures higher than about 500.degree. C.

BEST MODES FOR CARRYING OUT THE INVENTION 
Referring now to the Figures, wherein like numerals of reference designate 
like elements throughout, a (111) silicon substrate 10 is shown in FIG. 1. 
Prior to CoSi.sub.2 deposition, the major surface 12 upon which the film 
is to be deposited is cleaned by well-known techniques. 
Co and Si atoms are co-evaporated at a ratio of 1:2, respectively, using 
two electron gun sources, in a high vacuum environment, with the pressure 
less than 10.sup.-9 Torr. Other deposition procedures may be used that 
co-deposit the constituent atoms in a stoichiometric ratio in a clean 
environment. The deposition temperature is at ambient. 
The resulting Co/Si amorphous mixture, depicted as film 14 in FIG. 2, is 
formed to a thickness ranging from about 1 to 150 nm, and preferably about 
5 to 10 nm. The nature of the crystallization process (i.e., solid-phase 
epitaxy) limits the thickness of high-quality crystalline material that 
can be obtained. Beyond about 150 nm, the crystalline quality of the 
CoSi.sub.2 layer begins to degrade. 
Next, an amorphous layer 16 of silicon is deposited onto the Co/Si 
amorphous mixture 14, such as by evaporation immediately following 
formation of the Co/Si amorphous layer. The a-Si layer 16 is formed to a 
thickness ranging from about 0.5 to 2 nm, and preferably about 1 to 2 nm. 
The a-Si layer 16 is used to cover the high surface energy silicide layer 
14 during the annealing process in order to eliminate pinhole formation. 
When the a-Si layer is less than about 0.5 nm, the layer is not effective 
in eliminating the formation of pinholes, presumably due to incomplete 
surface coverage of the a-Si. There is no advantage gained in depositing 
an a-Si layer thicker than about 2 nm. The resulting assembly 18 is 
depicted in FIG. 3. Layer 16 is also deposited at ambient temperature. 
Annealing of the assembly 18 is then performed, at a temperature ranging 
from about 500.degree. to 750.degree. C., and preferably at a temperature 
ranging from about 550.degree. to 600.degree. C., to form an epitaxial, 
crystalline layer 14'. It has been found that although epitaxial 
CoSi.sub.2 layers can be formed at annealing temperatures less than 
200.degree. C., the crystalline quality of the resulting layers is poor. 
High crystalline quality material can be obtained for annealing 
temperatures in the range of about 500.degree. to 750.degree. C. Beyond 
750.degree. C., the CoSi.sub.2 layer begins to segregate into islands. 
The annealing time ranges from about 1 to 60 minutes, and preferably for a 
time of about 10 to 20 minutes, the longer times generally associated with 
the lower temperatures. The actual annealing times used for a given 
annealing temperature were established using reflection high energy 
electron diffraction to monitor the crystalline perfection of the silicide 
layer 14. In general, the lower the annealing temperature, the longer it 
takes for the cobalt and silicon atoms in the codeposited layer 14 to 
arrange themselves in an epitaxial relationship with the substrate to 
produce layer 14', 
During the annealing process, the amorphous silicon cap layer 16 is 
converted to a crystalline silicon layer 16', 
The CoSi.sub.2 layers formed by the codeposition technique are of good 
crystalline quality and occur in type B orientation. Type B orientation is 
one in which the silicide crystal is rotated 180 about the surface normal. 
The type A orientation, in which the silicide crystal is not rotated with 
respect to the underlying substrate, has been observed by others. It is 
not desirable to have a mixture of A and B grains in the silicide layer, 
since this will result in an inhomogeneity in the layer properties. 
No pinholes are observed for CoSi.sub.2 films grown in accordance with the 
invention. The detection resolution is 10.sup.3 cm.sup.-2. In contrast, if 
the silicon cap 16 is omitted, pinhole densities of 10.sup.7 to 10.sup.8 
cm.sup.-2 are observed in the CoSi.sub.2 films. 
EXAMPLES 
The samples described herein were grown in a RIBER EVA 32 Si MBE system 
with a base pressure of 3.times.10.sup.-11 Torr. Prior to deposition, 
Si(111) substrates were cleaned in accordance with a prior art procedure. 
An in situ silicon beam technique was used to remove the protective oxide 
remaining after the chemical clean (at a substrate temperature of 
700.degree. C. and Si flux of 1.times.10.sup.13 cm.sup.-2 s.sup.-1). The 
substrates were then cooled to room temperature (&lt;100.degree. C.) and Co 
and Si atoms were co-evaporated at a ratio of 1:2, respectively, from two 
electron gun sources. The chamber pressure during the deposition process 
was less than 5.times.10.sup.-10 Torr Co:Si ratios were previously 
calibrated by quartz crystal monitors and controlled during deposition by 
a Sentinel III deposition controller. Amorphous Si layers with thicknesses 
of 1 to 2 nm were immediately evaporated onto the codeposited layer. 
Samples were annealed in situ at temperatures ranging from 550.degree. to 
600.degree. C. for 10 minutes. Final CoSi.sub.2 thicknesses ranged from 5 
to 10 nm. 
The films were characterized in situ by reflection high-energy electron 
diffraction (RHEED), and ex situ by transmission electron microscopy 
(TEM), scanning electron microscopy (SEM), and Rutherford backscattering 
spectroscopy (RBS). The CoSi.sub.2 films were of high crystalline quality 
and occurred with type B orientation with respect to the underlying 
silicon substrate. TEM studies revealed that the CoSi.sub.2 layers were 
uniform in thickness and that there was an abrupt CoSi.sub.2 /Si interface 
with roughness corresponding to single atomic steps (3 .ANG.). Minimum RBS 
channeling yields of less than 3% indicated that the CoSi.sub.2 films had 
good crystallinity. The a-Si cap was converted to single-crystal Si in the 
annealing process as indicated by RHEED patterns. However, the crystalline 
quality of the Si cap was not characterized by RBS and TEM because of its 
small dimension (0.5 to 2 nm). 
Pinhole formation in CoSi.sub.2 layers was studied by utilizing a CF.sub.4 
plasma etching technique to increase the visibility of the pinholes. This 
technique selectively etches Si relative to CoSi.sub.2 with a selectivity 
of more than 100 to 1, thereby forming an etched crater in the Si wherever 
a pinhole in the CoSi.sub.2 layer 14 occurs. This crater is large compared 
to the original size of the pinhole and is easier to detect by 
conventional scanning electron microscopy techniques. If a Si capping 
layer is present, it is also removed by the CF.sub.4 plasma. The use of 
this plasma etching technique improved the detection limit to 
1.times.10.sup.3 pinholes per cm.sup.2. The surface morphology of 
Co-Si.sub.2 layers after CF.sub.4 plasma etch was studied by SEM. Pinhole 
densities of 10.sup.7 to 10.sup.8 were observed for CoSi.sub.2 layers 
grown without the presence of a capping layer, while no pinholes were 
observed for CoSi.sub.2 films grown with a Si cap. The results are 
summarized in the Table below. 
TABLE 
______________________________________ 
Pinhole Study of CoSi.sub.2 
-a-Si cap Annealing 
Pinhole 
thick- CoSi.sub.2 thick- 
Temperature, 
Density, 
Sample ness, nm ness, nm .degree.C. 
cm.sup.-3 
______________________________________ 
1 2 10 577 .sup. 0.sup.a 
2 2 10 577 0 
3 1 10 577 0 
4 1 5 577 0 
5 .sup. NA.sup.b 
10 550 1 .times. 10.sup.8 
6 NA 10 577 5 .times. 10.sup.7 
7 NA 10 550 1.3 .times. 10.sup.8 
______________________________________ 
.sup.a Below the detection resolution of 1 .times. 10.sup.3 cm.sup.-3 by 
using the CF.sub.4 plasma etch technique 
.sup.b Formed without an -aSi cap. 
INDUSTRIAL APPLICABILITY 
The process of the invention is expected to find use in the fabrication of 
metal base transistors. 
Thus, there has been disclosed a process for the formation of pinhole-free, 
high quality, thin films of CoSi.sub.2 on Si(111). Various changes and 
modifications of an obvious nature will occur to those of ordinary skill 
in this art, and all such changes and modifications are considered to fall 
within the scope of the invention, as defined by the appended claims.