Flexible merge scheme for source/drain epitaxy regions

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, three-dimensional transistors such as a Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. Although existing FinFET devices and methods of fabricating FinFET devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, the FinFETs for different circuits such as core (logic) circuits and Static Random Access Memory (SRAM) circuits may have different designs, and the source/drain epitaxy regions grown from neighboring fins may need to be merged for some circuits (such as logic circuits), and need to be separated from each other for other circuits (such as SRAM circuits). However, to save manufacturing cost, the epitaxy for different regions is performed simultaneously. This causes difficulty for selectively making epitaxy regions merged for some circuits, and not merged for other circuits. Accordingly, the merged epitaxy regions need to be trimmed to separate the merged epitaxy regions from each other.

DETAILED DESCRIPTION

Fin Field-Effect Transistor (FinFETs) and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages in the formation of the FinFETs are illustrated. The variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS. 1A through 10Cillustrate the intermediate stages in the formation of FinFETs. The steps shown inFIG. 1A through 10Care also illustrated schematically in the process flow500shown inFIG. 12. Each of the figure numbers inFIGS. 1A through 10Cmay include letter “A,” “B,” or “C,” wherein letter “A” indicates that the respective figure illustrates a perspective view, and letter “B” indicates that the respective figure is obtained from the plane same as the vertical plane containing line B-B inFIG. 1A, and letter “C” indicates that the respective figure is obtained from (and combined) the planes same as the vertical planes containing lines C-C inFIG. 1A. Accordingly, the figures whose numbers include letter “B” show the cross-sectional views obtained from the vertical planes parallel to the lengthwise directions of gate stacks, and the figures whose numbers include letter “C” show the cross-sectional views obtained from the vertical planes parallel to the lengthwise directions of semiconductor fins, which will be discussed in detail in subsequent paragraphs.

FIG. 1Aillustrates a perspective view in the formation of a structure including substrate20, isolation regions22, semiconductor strips24between isolation regions22, and semiconductor fins26over the top surfaces of isolation regions22. Substrate20is a semiconductor substrate, which may be a silicon substrate, a silicon carbon substrate, or a substrate formed of other semiconductor materials such as III-V compound semiconductor materials. Substrate20may be lightly doped with a p-type or an n-type impurity.

Isolation regions22may be, for example, Shallow Trench Isolation (STI) regions. The formation of STI regions22may include etching semiconductor substrate20to form trenches, and filling the trenches with a dielectric material(s) to form STI regions22. STI regions22may include silicon oxide, and other dielectric materials such as nitrides may also be used. Semiconductor fins26overlap the underlying semiconductor strips24. The formation of semiconductor fins26may include recessing STI regions22, so that the portions of semiconductor material between the removed portions of STI regions22become semiconductor fins26. Semiconductor fins26and some or substantially entireties of semiconductor strips24may be formed of silicon (with no germanium therein) or other silicon-containing compound including, and not limited to, silicon carbon, silicon germanium, or the like.

A plurality of parallel gate stacks28is formed on semiconductor fins26. Gate stacks28are parallel to each other, and cover portions of semiconductor fins26, while leaving some other portions of semiconductor fins26uncovered. Gate stacks28include gate dielectrics32on the sidewalls and the top surfaces of semiconductor fins26, and gate electrodes34over gate dielectrics32. Gate dielectrics32may be selected from silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, combinations thereof, and multi-layers thereof. Gate electrodes34may be formed of a conductive material that includes polysilicon, a refractory metal, or the respective compound including, e.g., polysilicon, Ti, W, TiAl, TaC, TaCN, TaAlC, TaAlCN, TiN, and TiW. In other examples, gate electrodes34include nickel (Ni), gold (Au), copper (Cu), or the alloys thereof.

In accordance with some embodiments of the present disclosure, gate stacks28remain in the final FinFETs, and form the gate stacks of the final FinFETs. In accordance with alternative embodiments of the present disclosure, gate stacks28are dummy gate stacks that will be replaced by replacement gates in subsequent steps. Accordingly, gate stacks28may include dummy gate electrodes (which is also denoted as34), which may comprise polysilicon, for example. Dummy gate dielectrics32may, or may not, be formed between dummy gate electrodes34and semiconductor fins26.

Gate stacks28may also include hard masks35and36formed over gate electrodes34. In accordance with some embodiments, hard masks35are formed of silicon oxide, silicon oxycarbo-nitride (SiOCN), or the like. Hard masks36may be formed of silicon nitride (SiN), SiOCN, SiOC, or other dielectric materials in accordance with some embodiments.

The perspective view show inFIG. 1Aillustrates the exemplary layouts of circuits602and604as schematically represented by dashed boxes. In accordance with some embodiments, each of circuits602and604is selected from logic circuits or SRAM circuits, and circuits602and604may be same types of circuits or different types of circuits. In the following discussion, circuits602and604are referred to as a logic circuit and an SRAM circuit, respectively as an example, while other combinations are also contemplated.

In accordance with some embodiments, circuit602is formed in a device region including n-type FinFET region100and p-type FinFET region200, and circuit604is formed in a device region including n-type FinFET region300and p-type FinFET region400. Device regions100,200,300, and400are also illustrated inFIGS. 1B and 1C through 10C. Semiconductor fins126,226,326, and426are formed in regions100,200,300, and400, respectively, and are referred to collectively as semiconductor fins26. Gate stacks28are formed in the directions perpendicular to the lengthwise directions of semiconductor fins26. It is noted that although the gate stacks28are illustrated as continuously extending into different device regions100,200,300, and400for a compact illustration purpose, the gate stacks28in different device regions may be physically separated from each other, or some gate stacks28in some of device regions may be connected in any combination, while the gate stacks28in other device regions are separated.

FIG. 1Billustrates the cross-sectional views of semiconductor fins26in device regions100,200,300, and400, wherein the cross-sectional view is obtained from the plane crossing line B-B inFIG. 1A. Also, the plane of cross-sectional view is obtained from the middle of two neighboring gate stacks28(as schematically illustrated inFIG. 1C). As shown inFIG. 1B, distance D1between neighboring fins126may be greater than, equal to, or smaller than, distance D1′ between neighboring fins326. Distance D2between neighboring fins226may be greater than, equal to, or smaller than, distance D2′ between neighboring fins426. The illustrated view inFIG. 1Breflects the structures shown in the regions marked by dashed lines602and604inFIG. 1A(also refer toFIG. 11).

FIG. 1Cillustrates the cross-sectional views of device regions100,200,300, and400, wherein the cross-sectional views are obtained from the planes crossing lines C-C inFIG. 1A.

As shown inFIGS. 1A, 1B, and 1C, dielectric layer38is formed. The respective step is illustrated as step502in the process flow shown inFIG. 12. Dielectric layer38is alternatively referred to as a spacer layer. In accordance with some embodiments of the present disclosure, spacer layer38is formed of silicon nitride, silicon oxide, silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), silicon oxynitride (SiON), while other dielectric materials may be used. Spacer layer38may have a thickness in the range between about 2 nm and about 5 nm.

Spacer layer38is formed as a conformal layer, and hence covers the top surfaces and the sidewalls of semiconductor fins26(FIG. 1B) and gate stacks28(FIG. 1C). The portions of spacer layer38on the sidewalls of semiconductor fins26are used to form fin spacers, as shown inFIG. 2B, and the portions of spacer layer38on the sidewalls of semiconductor fins26are used to form gate spacers.

Mask layer40is formed over spacer layer38. The respective step is also illustrated as step502in the process flow shown inFIG. 12. The material of mask layer40is selected to have a high etching selectivity with relative to the material of spacer layer38. In accordance with some embodiments of the present disclosure, the material of mask layer40is also selected from silicon nitride, silicon oxide, silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), and silicon oxynitride (SiON). Mask layer40may have a thickness in the range between about 2 nm and about 10 nm. Mask layer40is also formed as a conformal layer. The formation of spacer layer38and mask layer40may be selected from conformal deposition methods such as Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD). Both spacer layer38and mask layer40extend into device regions100,200,300, and400.

FIGS. 2A, 2B, and 2Cillustrate the patterning of spacer layer38in region100. First, photo resist42is applied and patterned, wherein the photo resist42is illustrated inFIGS. 2B and 2C, and not inFIG. 2A, although it still exists inFIG. 2A. Photo resist42may be a single-layer photo resist, or a tri-layer photo resist including an inorganic layer (known as middle layer) sandwiched between two photo resists (known as under layer and upper layer). The patterned photo resist42covers regions200,300, and400, and leaves region100uncovered. Next, an etching step is performed to remove the portions of mask layer40from region100. The respective step is illustrated as step504in the process flow shown inFIG. 12. Depending on the process and the distance between neighboring fins126(FIG. 1C), mask layer40may or may not have a residue portion left between neighboring fins126, as shown inFIG. 2B. After mask layer40is removed, the portion of spacer layer38in region100is exposed, and an anisotropic etching is performed to etch spacer layer38in region100, so that the top portions of spacer layer38on top of fins126are removed, exposing fins126. The respective step is illustrated as step506in the process flow shown in FIG.12. The remaining portions of spacer layer38on the sidewalls of gate stacks28become gate spacers144(FIG. 2C), and the remaining portions of spacer layer38on the sidewalls of fins126(FIG. 1B) become fin spacers146(FIG. 2B). The etching time of spacer layer38is selected so that fin spacers146have appropriate height H1(FIG. 2B).

In a subsequent step, the exposed semiconductor fins126are recessed, for example, in an anisotropic or isotropic etching step, so that recesses148(FIGS. 2B and 2C) are formed to extend into semiconductor fins126. The respective step is illustrated as step508in the process flow shown inFIG. 12. The bottoms of recesses148may be higher than, level with, or lower than the top surfaces of STI regions22. The etching is performed using an etchant that attacks fins126, and hardly attacks fin spacers146. Accordingly, in the etching step, the height of fin spacers146is substantially not reduced. After the formation of recesses148, photo resist42is removed, for example, in an ashing step.

FIGS. 3A, 3B, and 3Cillustrate the patterning of spacer layer38in region300. First, photo resist50is applied and patterned, wherein the photo resist50is illustrated inFIGS. 3B and 3C, and not inFIG. 3A, although it still exists inFIG. 3A. Photo resist50may also be a single-layer photo resist or a tri-layer photo resist. The patterned photo resist50covers regions100,200, and400, and leaves region300uncovered. Next, an etching step is performed to remove the portions of mask layer40in region300. The respective step is illustrated as step510in the process flow shown inFIG. 12. Depending on the process and the distance between neighboring fins326(FIG. 2C), mask layer40may, or may not have a residue portion left between neighboring fins326(FIG. 3C). After mask layer40is removed, the portion of spacer layer38in region300is exposed, and an anisotropic etching is performed to etch spacer layer38, so that the top portions of spacer layer38on top of fins326are removed, exposing fins326. The respective step is illustrated as step512in the process flow shown inFIG. 12. The remaining portions of spacer layer38on the sidewalls of gate stacks28become gate spacers344(FIG. 3C), and the remaining portions of spacer layer38on the sidewalls of fins326(FIG. 3B) become fin spacers346(FIG.3B). The etching time of spacer layer38is selected so that fin spacers346will have appropriate height H3(FIG. 3B).

In a subsequent step, the exposed semiconductor fins326are recessed, for example, in an anisotropic or isotropic etching step, so that recesses348(FIGS. 3B and 3C) are formed to extend into semiconductor fins326. The respective step is illustrated as step514in the process flow shown inFIG. 12. The bottoms of recesses348may be higher than, level with or lower than the top surfaces of STI regions22. The etching is performed using an etchant that attacks fins326, and hardly attacks fin spacers346. Accordingly, in the etching step, the height of fin spacers346is substantially not reduced. After the formation of recesses348, photo resist50is removed.

FIGS. 4A, 4B, and 4Cillustrate the simultaneously epitaxy for forming epitaxy semiconductor regions152and352(which are source/drain regions of FinFETs) in regions100and300, respectively. The respective step is illustrated as step516in the process flow shown inFIG. 12. In accordance with some embodiments of the present disclosure, the formation of epitaxy regions152and352includes epitaxially growing silicon phosphorous (SiP) or phosphorous-doped silicon carbon (SiCP), and the resulting FinFETs formed in regions100and300are n-type FinFETs. As shown inFIG. 4B, in the initial stage of the epitaxy, the grown epitaxy regions152and352are confined by fin spacers146and346. After the epitaxy regions152and352are grown to higher than the top ends of epitaxy regions152and352, respectively, lateral growth also occurs along with the vertical growth, and epitaxy regions152and352expand laterally.

The portions of epitaxy regions152grown from neighboring recesses148may be merged as a large epitaxy region, or remain separated from each other when the epitaxy if finished. The portions of epitaxy regions352grown from neighboring recesses348may also be merged into a large epitaxy region, or remain separated from each other when the epitaxy if finished. In addition, voids153and353may be formed when mergence occurs. Whether the mergence occurs or not depends on the heights of the respective fin spacers146and346, and how long the epitaxy lasts. Accordingly, by adjusting heights H1and H3(FIG. 4B), one of the following four scenarios may occur: the mergence occurs for both epitaxy regions152and352, the mergence occurs for epitaxy regions152but not for epitaxy regions352, the mergence occurs for epitaxy regions352but not for epitaxy regions152, and the mergence doesn't occur for either of epitaxy regions152and352.FIG. 4Dillustrates some exemplary embodiments, wherein the un-merged epitaxy regions152and352are illustrated if the corresponding epitaxy portions608in dashed lines don't exist.

Referring back toFIG. 4B, if, for example, it is desirable that the mergence occur for epitaxy regions152but not for epitaxy regions352, fin spacers146may be formed to have height H1smaller than height H3of fin spacers346. As a result, the lateral expansion occurs earlier for epitaxy regions152than epitaxy regions352, and epitaxy regions152merge while epitaxy regions352don't merge. In accordance with some embodiments of the present disclosure, to make height H1smaller than height H3, the period of time TP1for etching spacer layer38(the step shown inFIG. 2B) may be selected to be longer than the period of time TP3for etching spacer layer38(the step shown inFIG. 3B). In accordance with some embodiments of the present disclosure, ratio TP1/TP3may be greater than about 1.5, and may be in the range between about 1.5 and about 5.0. As a result, height H3/H1may be greater than about 1.5, and may be in the range between about 1.5 and about 5.0. With the merging of neighboring epitaxy regions, the resulting FinFET may have a higher drive (saturation current). With the neighboring epitaxy regions not merged, the resulting FinFETs may be more compact. Accordingly, different requirements of different circuits may be met at the same time without requiring the epitaxy regions to be formed by different epitaxy processes.

Converse to the above discussion, if it is desirable that the mergence occur for epitaxy regions352but not form epitaxy regions152, fin spacers146may be formed to have height H1greater than height H3of fin spacers346. In accordance with some embodiments of the present disclosure, ratio TP3/TP1may be greater than about 1.5, and may be in the range between about 1.5 and about 5.0. Also, height H1/H3may be greater than about 1.5, and may be in the range between about 1.5 and about 5.0.

In accordance with some embodiments, after the epitaxy, an implantation is performed to implant an n-type impurity such as phosphorous or arsenic into epitaxy regions152and352to form source/drain regions, which are also referred to using reference numerals152and352. In accordance with alternative embodiments, no implantation of any n-type impurity is performed, and the n-type impurity was provided through the in-situ doping occurred during the epitaxy.

FIGS. 5A through 10Cillustrate the formation of epitaxy regions for the FinFETs in regions200and400, wherein the respective steps are similar to the repetition of the steps for forming epitaxy regions in device regions100and300, except the conductivity types of some regions are inversed. First, an etching step is performed to remove remaining portions of mask layer40from regions100,200,300, and400. The respective step is illustrated as step518in the process flow shown inFIG. 12. Some residue portions of mask layer40may (or may not) be left after the etch. The resulting structure is shown inFIGS. 5A, 5B, and 5C.

Next, as shown inFIGS. 6A, 6B, and 6C, mask layer56is formed. The respective step is illustrated as step520in the process flow shown inFIG. 12. The material and the formation methods of mask layer56may be selected from the same candidate materials and candidate methods for forming mask layer40. For example, the material of mask layer56may be selected from silicon nitride, silicon oxide, SiCN, SiOCN, and SiON. Mask layer56may also be formed using ALD or CVD. The thickness of mask layer56may be in the range between about 2 nm and about 10 nm.

FIGS. 7A, 7B, and 7Cillustrate the patterning of spacer layer38in region200. First, photo resist58is applied and patterned, wherein the photo resist58is illustrated inFIGS. 7B and 7C, and not inFIG. 7A, although it still exists inFIG. 7A. The patterned photo resist58covers regions100,300, and400, and leaves region200uncovered. Next, an etching step is performed to remove the portions of mask layer56in region200. Depending on the process and the distance between neighboring fins226(FIG. 2C), mask layer56may, or may not have a residue portion left between neighboring fins226(FIG. 7B). After mask layer56is removed, the portion of spacer layer38in region200is exposed, and an anisotropic etching is performed to etch spacer layer38, so that the top portions of spacer layer38on top of fins226(FIG. 6B) are removed, hence exposing fins226. The remaining portions of spacer layer38on the sidewalls of gate stacks28become gate spacers244(FIG. 7C), and the remaining portions of spacer layer38on the sidewalls of fins226(FIG. 7B) become fin spacers246. The etching time of spacer layer38is selected so that fin spacers246have appropriate height H2(FIG. 7B).

In a subsequent step, the exposed semiconductor fins226(FIG. 6B) are etched, for example, in an anisotropic or isotropic etching step, so that recesses248(FIGS. 7B and 7C) are formed to extend into semiconductor fins226. The bottoms of recesses248may be higher than, level with, or lower than the top surfaces of STI regions22. The etching is performed using an etchant that attacks fins226, and hardly attacks fin spacers246. Accordingly, in the etching step, the height H2of fin spacers246is substantially not reduced. After the formation of recesses248, photo resist58is removed.

FIGS. 8A, 8B, and 8Cillustrate the patterning of spacer layer38in region400. First, photo resist62is applied and patterned, wherein the photo resist62is illustrated inFIGS. 8B and 8C, and not inFIG. 8A, although it still exists inFIG. 8A. The patterned photo resist62covers regions100,200, and300, and leaves region400uncovered. Next, an etching step is performed to remove the portions of mask layer56in region400. Depending on the process and the distance D2′ between neighboring fins426(FIG. 2C), mask layer56may, or may not have a residue portion left between neighboring fins426(FIG. 8B). After mask layer56is removed, the portion of spacer layer38in region400is exposed, and an anisotropic etching is performed to etch spacer layer38, so that the top portions of spacer layer38on top of fins426(FIG. 7B) are removed, exposing fins426. The remaining portions of spacer layer38on the sidewalls of gate stacks28become gate spacers444(FIG. 8C), and the remaining portions of spacer layer38on the sidewalls of fins426(FIG. 8B) become fin spacers446. The etching time of spacer layer38is selected so that fin spacers446have appropriate height H4(FIG. 8B).

In a subsequent step, the exposed semiconductor fins426(FIG. 7B) are etched, for example, in an anisotropic or isotropic etching step, so that recesses448(FIGS. 8B and 8C) are formed to extend into semiconductor fins426. The bottoms of recesses448may be higher than, level with or lower than the top surfaces of STI regions22. The etching is performed using an etchant that attacks fins426, and hardly attack fin spacers446. Accordingly, in the etching step, the height of fin spacers446is substantially not reduced. After the formation of recesses448, photo resist62is removed.

FIGS. 9A, 9B, and 9Cillustrate the simultaneously epitaxy for forming epitaxy regions252and452(which are source/drain regions of FinFETs) in regions200and400, respectively. In accordance with some embodiments of the present disclosure, the formation of epitaxy regions252and452includes epitaxially growing silicon germanium, wherein boron may be in-situ doped, so that the resulting FinFETs formed in regions200and400are p-type FinFETs. As also shown inFIG. 9B, in the initial stage of the epitaxy, the grown epitaxy regions252and452are confined by fin spacers246and446, respectively. After epitaxy regions252and452are grown to higher than the top ends of epitaxy regions252and452, respectively, lateral growth also occurs along with the vertical growth, and epitaxy regions252and452expand laterally.

The portions of epitaxy regions252grown from neighboring recesses248may be merged into a large epitaxy region. In accordance with some embodiments of the present disclosure, the portions of epitaxy regions452grown from neighboring recesses148are not merged. This is achieved by making height H4(FIG. 9B) of fin spacers446to be greater than height H2of fin spacers246. To make height H4to be greater than height H2, the period of time TP4for etching spacer layer38(the step shown inFIG. 8B) may be selected to be shorter than the period of time TP2for etching spacer layer38(the step shown inFIG. 7B). In accordance with some embodiments of the present disclosure, ratio TP2/TP4may be greater than about 1.5, and may be in the range between about 1.5 and about 5.0. As a result, height H4/H2may be greater than about 1.5, and may be in the range between about 1.5 and about 5.0.

In accordance with alternative embodiments, the processes for forming fin spacers236and446may be adjusted to adjust heights H2and H4, and to result in one of the following results: the mergence occurs for both epitaxy regions252and452(height H2and H4are substantially equal, for example, with difference smaller than about 10 percent), the mergence occurs for epitaxy regions452but not for epitaxy regions252(with height H2>H4), and the mergence doesn't occur for either of epitaxy regions252and452.

In accordance with some embodiments, after the epitaxy, an implantation is performed to implant a p-type impurity such as boron or indium into epitaxy regions252and452to form source/drain regions, which are also referred to using reference numerals252and452. In accordance with alternative embodiments, no implantation of p-type impurity is performed.

An etching step is then performed to remove remaining portions of mask layer56from regions100,200,300, and400, andFIGS. 10A, 10B, and 10Cillustrate the structure after mask layer56is removed. N-type FinFET166, p-type FinFET266, n-type FinFET366, and p-type FinFETs466are thus formed in regions100,200,300, and400, respectively. In subsequent steps, source/drain silicide regions (not shown) are formed on the top surfaces of source/drain regions152,252,352, and452. An Inter-Layer Dielectric (ILD, not shown) is formed to cover the illustrated FinFETs, and source/drain contact plugs (not shown) may be formed in the ILD to contact the source/drain silicide regions. Gate contact plugs (not shown) may also be formed to contact the illustrated gate electrodes in gate stacks28. Also, the illustrate gate stacks28may be replaced with replacement gate stacks if gate stacks28are dummy gate stacks.

The embodiments of the present disclosure have some advantageous features. By separating the formation of fin spacers in different device regions, the heights of the fin spacers in different device regions may be adjusted separately. This advantageously results in the flexibility in forming merged or un-merged epitaxy source/drain regions. The formation of the fin spacers shares a common deposition process, and the epitaxy for forming source/drain regions for different device regions is also a common process. The manufacture cost is thus reduced.

In accordance with some embodiments of the present disclosure, a method includes forming a first gate stack extending on top surfaces and sidewalls of first semiconductor fins with the first semiconductor fins being parallel to and neighboring each other, forming a second gate stack extending on top surfaces and sidewalls of second semiconductor fins with the second semiconductor fins being parallel to and neighboring, each other, and forming a dielectric layer. The dielectric layer includes a first portion extending on the first gate stack and the first semiconductor fins, and a second portion extending on the second gate stack and the second semiconductor fins. In a first etching process, the first portion of the dielectric layer is etched to form first fin spacers on sidewalls of the first semiconductor fins. The first fin spacers have a first height. In a second etching process, the second portion of the dielectric layer is etched to form second fin spacers on sidewalls of the second semiconductor fins. The second fin spacers have a second height greater than the first height. The first semiconductor fins are recessed to form first recesses between the first fin spacers. The second semiconductor fins are recessed to form second recesses between the second fin spacers. The method further includes simultaneously growing first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions grown from neighboring ones of the first recesses merge with each other. The second epitaxy semiconductor regions grown from neighboring ones of the second recesses are separate from each other.

In accordance with some embodiments of the present disclosure, a method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

In accordance with some embodiments of the present disclosure, a method includes, in a common deposition process, forming a dielectric layer including a first portion on top surfaces and sidewalls of first semiconductor fins and a second portion on top surfaces and sidewalls of second semiconductor fins. In separate etching processes, the first portion of the dielectric layer and the second portion of the dielectric layer are etched to form first fin spacers and second fin spacers, respectively. The first fin spacers have a first height, and the second fin spacers have a second height greater than the first height. The first semiconductor fins are etched to form first recesses between the first fin spacers. The second semiconductor fins are etched to form second recesses between the second fin spacers. In a common epitaxy process, first epitaxy semiconductor regions are growth from the first recesses, and second epitaxy semiconductor regions are grown from the second recesses. The first epitaxy semiconductor regions merge with each other, and the second epitaxy semiconductor regions are discrete from each other.