Semiconductor structure and method for wafer scale chip package

An embodiment semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Additionally, the semiconductor structure includes an under-bump metal (UBM) layer disposed on the RDL platform and a solder bump disposed on the UBM layer, where the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bump and the metal layer.

TECHNICAL FIELD

The present application relates in general to semiconductor circuit packaging and, in particular, to a semiconductor structure and method for wafer scale chip package.

BACKGROUND

In wafer scale chip scale packaging (WCSP), chips are directly mounted on boards. Individual chips are diced, and bump connections are used to mount the chips directly on the boards without packaging.

SUMMARY

An embodiment semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Additionally, the semiconductor structure includes an under-bump metal (UBM) layer disposed on the RDL platform and a solder bump disposed on the UBM layer, where the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bump and the metal layer.

An embodiment semiconductor structure includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars supporting the RDL platform. The semiconductor structure also includes a first polyimide layer between the plurality of RDL pillars and on a first side of the RDL platform and a second polyimide layer on a second side of the RDL platform, the second side of the RDL platform opposite the first side of the RDL platform.

An embodiment method of forming a semiconductor structure includes depositing a metal layer on a wafer and forming a polyimide layer over the metal layer. The method also includes forming pillar openings in the polyimide layer and depositing a redistribution layer (RDL) in the pillar openings and over a portion of the polyimide layer, where the polyimide layer is disposed between the metal layer and the RDL.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the illustrative example arrangements and are not necessarily drawn to scale.

DETAILED DESCRIPTION

In wafer scale chip scale packaging (WCSP), die mount directly on a printed circuit board (PCB), instead of going through a packaging processes and mounting the packaged device on a PCP. WCSP structures may be small, due to the lack of additional packaging. Additionally, the use of direct connections in WCSP enables a low resistance and high current operations.

In an example, a rigid bump stack structure is used for WSPC. A solder bump is placed on an under bump metal (UBM) layer, which is coupled on a lower metal layer. This rigid structure is poorly suited for handling mechanical stress. Mechanical stress may be especially problematic during thermal cycling in subsequent processing steps. Mechanical stress may lead to breakage and reduced.

Power transistors, such as bipolar junction transistors (BJTs), thyristors, insulated gate bipolar transistors (IGBTs), or power metal oxide semiconductor field effect transistors (MOSFETs), such as NexFETs™ devices, produced by Texas Instruments, may be well suited for WCSP. Power transistors may be large in size and have a high stress in WCSP, associated with the WCSP environment. Also, power transistors may operate at high currents, and may desire low resistance connections.

In an example, a bump structure includes a redistribution layer (RDL). The RDL may include an RDL platform supported by RDL pillars. In an example, an array of bumps with an RDL structure is used for power transistors. In an example, an RDL reduces mechanical stress on a bump structure. In an example, an RDL enables a low electrical resistance connection, with a high current capability. For example, an embodiment bump structure has a resistance of less than 2.5 mohm. An embodiment has two polyimide layers for absorbing horizontal and vertical stress, and reducing breakage. An embodiment enables the mounting of a large power transistor, for example larger than 1 mm by 1 mm, using WCSP. An embodiment has good electro migration capability.

FIG.1illustrates a cross-sectional view of the semiconductor structure100. The substrate302contains at least one transistor or integrated circuit, for example one or more power transistor such as a BJT, a thyristor, IGBTs or power MOSFETs, such as NexFET™ devices, produced by Texas Instruments. In an example, the substrate302contains analog circuitry, for example high power analog circuitry. The substrate302may be a semiconductor substrate, for example silicon, with various metal, dielectric, and/or semiconductor layers. The metal layer304is disposed on the substrate302. In an example, the metal layer304is a metal 1 (MET1) layer, a metal 2 (MET2) layer, a metal 3 (MET3) layer, or another metal layer. The metal layer304may be copper, aluminum, or another metal, for example a metal alloy. In one embodiment, the thickness of the substrate302and the metal layer304is between 7 mm and 14 mm, for example between 8-9 mm. On the opposite side of the substrate302from the metal layer304is the backside metal layer306. In some embodiments, the backside metal layer306is not present. In one example, the backside metal layer306is composed of silver, nickel, or gold. The backside metal layer306may be between 1 μm and 5 μm thick, for example approximately 3.4 μm thick. A passivation layer332is disposed on the metal layer304. The passivation layer332is an oxide layer, such as silicon dioxide. The polyimide layer334is disposed on the passivation layer332. The polyimide layer334is composed of a polymer of imide monomers. In an example, the polyimide layer334is between 5 μm and 10 μm, for example 7.5 μm.

Pad openings104and106extend through the passivation layer332and the polyimide layer334. The redistribution layer (RDL) structure352has an RDL platform356disposed over the polyimide layer334and RDL pillars354extending through the pad openings104and106to the metal layer304, between the RDL platform356and the metal layer304. The RDL is composed of a metal, such as copper. In an example, the RDL platform356is between 3 μm and 7 μm, for example 5 μm thick. Over the RDL platform356is the polyimide layer372, a second polyimide layer. The polyimide layer372may mostly encase the RDL platform356, covering the sides of the RDL platform356and a portion of the top of the RDL platform356, with an opening374. In an embodiment, the polyimide layer372is between 5 μm and 10 μm thick, for example 7.5 μm thick. In one example, the polyimide layer372has the same thickness as the polyimide layer334. In other examples, the polyimide layer372is thicker than the polyimide layer334. In additional examples, the polyimide layer372is thinner than the polyimide layer334. The under bump metal (UBM) layer392contacts the RDL platform356through the opening374in the polyimide layer372. The UBM layer392is composed of a metal, such as Ti, TiW, or another titanium alloy. The solder bump102is over the UBM layer392. The solder bump102provides a physical and electrical connection to a PCB. The solder bump102may be composed of lead solder or lead-free solder.

The UBM layer392, the RDL platform356, and the RDL pillars354, form an electrical connection between the solder bump102and the metal layer304. This electrical connection provides a low resistance electrical connection between the solder bump102and the metal layer304. For example, the electrical connection may have a resistance of less than 2.5 mohm. Also, the electrical connection between the solder bump102and the metal layer304supports a high current, for example 10 A. The solder bump102is connected to the UBM layer392, which is also connected to the RDL structure352. The RDL pillars354extend through the pad openings104and106provide a low resistance electrical connection to the metal layer304. The RDL pillars354are depicted not directly under the solder bump102but outside the solder bump102, but they may be fully or partially underlying the bump102. In an embodiment, the pillars are near the periphery of the RDL layer. The polyimide layer334under the RDL platform356and between the RDL pillars354, as well as surrounding the RDL pillars354, provides lateral and vertical flexibility. The polyimide layer372above and around the RDL platform356provides additional physical support. The semiconductor structure100is able to withstand a high level of mechanical stress while handling a high current with low resistance.

FIGS.2A-Dillustrate top views of several example semiconductor structures. Each pillar cross section may be combined with each number and distribution of pillars, and with each RDL platform geometry.FIG.2Aillustrates a top view of the semiconductor structure200, which may show the top view of the semiconductor structure100illustrated byFIG.1. The bump208is in the center of the semiconductor structure200. In some embodiments, the bump208is offset from the center of the semiconductor structure200. The RDL platform204, which is below the bump208, is disk shaped. In other embodiments, the RDL may have other shapes, for example it may be oval shaped, or irregularly shaped. Also, the RDL pillars206are arranged in a ring around the center of the bump208. The RDL pillars206support the RDL platform204. The RDL pillars206are illustrated as having circular cross sections, but may have other cross sections, for example oval, or irregular cross sectional shapes. Eight pillars are depicted, but another number of pillars may be present. For example, there may be between four pillars and sixteen pillars. In some examples, more pillars, for example sixteen to 32 pillars, are present.

FIG.2Billustrates a top view of the semiconductor structure210. The bump218is in the semiconductor structure210, and the RDL platform214is below the bump218. As depicted, the RDL platform214is square, but the RDL platform214may be another shape, for example rectangular, or square with rounded corners. The RDL pillars216support the RDL platform214, and couple the RDL platform214to lower metal layers. Four RDL pillars are present, but another number of pillars, for example six or eight pillars, may be used.

FIG.2Cillustrates the semiconductor structure230. The bump238is in the semiconductor structure230, and the RDL platform234is disposed below the bump238. The RDL platform234is shaped as an octagon, but may be shaped as another polygon, such as a pentagon, hexagon, heptagon, nonagon, decagon, hendecagon, or dodecagon. The polygons may be equilateral or may have edges that are different lengths. The RDL pillars236support the RDL platform234and electrically connect the RDL platform234to lower conductive layers. In an example, there is the same number of pillars as there are polygon sides. In other examples, there are more pillars than the number of polygon sides, or fewer pillars than the number of polygon sides.

FIG.2Dillustrates the semiconductor structure240. The bump248is in the semiconductor structure240. The RDL244is disposed below the bump248. The RDL pillars246support the RDL244, and electrically couple the RDL244to lower conductive layers. The RDL pillars have another shape, for example a rectangle, another polygon, or an irregular shape.

FIGS.3A-3Jillustrate the fabrication of the semiconductor structure100, illustrated inFIG.1.FIG.3Aillustrates a semiconductor structure, which contains the substrate302. The substrate302, still in wafer form, may be a silicon substrate containing transistors and/or integrated circuits, with various semiconductor, metal, and dielectric layers. The substrate302may include a power device, such as one or more power transistor, or power analog elements. Disposed on the substrate302is the metal layer304. The metal layer304may be a MET1 layer, a MET2 layer, a MET3 layer, or another metal layer. The substrate302may have a backside metal layer306on the opposite side of the substrate302than the metal layer304. The backside metal layer306may be composed of silver, nickel, or gold.

InFIG.3B, the system deposits the passivation layer312on the metal layer304. The passivation layer312may be an oxide layer, such as silicon dioxide. The passivation layer312may be deposited, for example, by chemical vapor deposition (CVD). InFIG.3C, the system deposits the polyimide layer322on the passivation layer312. The polyimide layer may be formed using step-growth polymerization or solid-phase synthesis. In theFIG.3Dthe system etches a pillar pattern, including pad openings104and106, in the passivation layer332and the polyimide layer334. To accomplish this, the system spins photoresist on the polyimide layer322. Then, the system exposes the photoresist layer using a photolithography mask, which may be a positive mask or a negative mask. This exposure transfers the pattern of the photolithography mask to the photoresist. Then, etching transfers the pattern from the photoresist layer to the polyimide layer322, to generate the polyimide layer334, and to the passivation layer312, to generate the passivation layer332. After etching, the system may remove the remaining photoresist.

InFIG.3E, the system deposits the RDL342on the polyimide layer334. The system may deposit the RDL342using evaporation, sputtering, or CVD. The RDL342fills the pad openings104and106as it is deposited and forms RDL pillars354. In an embodiment, the RDL342is composed of copper. InFIG.3F, the system patterns the RDL342, to generate the RDL structure352. The system applies photoresist to the RDL342. Then, the system exposes the photoresist using a photolithography mask, which may be a positive mask or a negative mask. This exposure transfers the pattern from the photolithography mask to the photoresist layer. Then, the system etches the RDL, to transfer the pattern from the photoresist to the RDL. The system may remove the remaining photoresist.

InFIG.3G, the system applies the polyimide layer362. In some examples, the polyimide layer362is composed of the same material as the polyimide layer334. In other examples, the polyimide layer362is composed of a different polyimide material than the polyimide layer334. InFIG.3H, the system patterns the polyimide layer362, to generate the polyimide layer372. The system performs photolithography by applying photoresist to the polyimide layer362. Then, the system etches the polyimide layer362, forming the opening374in the polyimide layer372. The system may also remove the remaining photoresist.

InFIG.3I, the system applies the UBM382to the polyimide layer372and to the RDL structure352via the opening374. The system may apply the UBM382using evaporation, sputtering, or CVD. The UBM layer392may be a metal, such as Ti, TiW, or another titanium alloy. As shown in theFIG.1, the solder bump102is applied to the UBM layer392. The solder bump102is composed of solder, which may be lead free solder. Bumping may be performed with repassivation with wet film or with dry film. With bumping with passivation and wet film, the system applies photoresist, exposes the photoresist, and develops the photoresist on the UBM layer392. Then, the system performs plating with copper/solder or copper/nickel/solder plating. The system then strips the photoresist. Then, the system etches UBM material. Finally, the system performs reflow by heating the UBM material. In bumping with dry film, the system performs dry film lamination, exposure, and developing. Then, the system plates using Cu/Ni/solder plating to the dry film. Next, the system strips the dry film, followed by etching the UBM. Finally, the system performs reflowing on the UBM layer392.

FIG.4illustrates the transistor structure500, which has an RDL polyimide structure for WCSP. The transistor structure500contains the structures502,504,506,508,510,512,514, and516, which have bump structures, such of the semiconductor structure100illustrated inFIG.1. The structures502,504,506,508,510,512,514, and516are NexFET™ devices, produced by Texas Instruments, in which current flows vertically. The structures502,504,506, and508are the sources, and the structures510,512,514, and516are the drains. Backside metal (not pictured) connects the sources and the drains.

FIG.5illustrates the flowchart600for an embodiment method of fabricating a semiconductor structure, such as the semiconductor structure100illustrated inFIG.1. In the block601, the system obtains a wafer. The wafer may include a substrate, such as silicon, containing at least one transistor or integrated circuit. The wafer may include various metal, semiconductor, and dielectric layers. The transistor or integrated circuit may include one or more power transistor, such as NexFET™ devices, made by Texas Instruments, or analog power electronics.

In the block602, the system backgrinds the wafer. For example, the wafer is background to between 6 mil and 14 mil, for example to between 8 mil and 9 mil. The system cleans the top surface of the wafer. Also, the system applies protective tape over the top surface of the wafer, to protect the wafer from mechanical damage and contamination. The system loads the wafer onto a cassette, which is placed in a cassette holder of the backgrinding machine. The backgrinding machine picks up the backside of the wafer with a robotic arm, which positions the wafer for backgrinding. A grinding wheel performs backgrinding on the wafer. The system may continuously wash the wafer with deionized water during backgrinding. After backgrinding, the wafer is returned to the cassette. The system removes the backgrinding tape from the wafer, for example using a de-tape tool.

In the block604, the system deposits backside metal to the back side of the wafer. The metal may be applied using radio frequency (RF) or direct current (DC) sputtering and electron beam evaporation. The backside metallization layer may have a good ohmic contact layer, such as silver, nickel, or gold.

In the block606, the system deposits one or more metal layer to the front side of the wafer via metallization. The block606may be performed before the block602, between block602and block604, or after the block604. The metal layer may be applied by sputtering, evaporation, or CVD. Sputtering may be, for example, ion-beam sputtering, reactive sputtering, ion-assisted deposition (IAD), high-target utilization sputtering (HiTUS), high-power impulse magnetron sputtering (HiPIMS), or gas flow sputtering. In an embodiment, pulsed laser deposition is used. Examples of evaporation include thermal evaporation, electron-beam evaporation, flash evaporation, or resistive evaporation. A pattern may be applied to the metal layer, for example by performing etching or liftoff. With etching, the metal layer is deposited, and a photoresist layer is applied to the metal layer. A pattern is transferred from a photolithography mask to the photoresist via exposure. Then, the pattern from the photoresist is transferred to the metal layer via etching. In liftoff, a photoresist layer is applied before the metal layer. A pattern is transferred to the photoresist layer from a photolithography mask by exposure. Then, the metal is deposited over the photoresist, and into the openings in the photoresist. Next, the photoresist is removed, leaving the metal that was deposited into the openings while removing the metal portions on the photoresist layer. The metal layer may copper, another metal, such as aluminum, or an alloy.

In the block608, the system deposits a passivation layer to the metal layer applied in the block606. The passivation layer may be an oxide, such as silicon dioxide. The passivation layer may be deposited by CVD.

In the block610, the system forms a first polyimide layer to the passivation layer deposited in the block608. The first polyimide layer may be formed using step-growth polymerization or solid-phase synthesis.

In the block612, the system patterns the passivation layer, deposited in the block608, and the first polyimide layer, formed in the block610. A layer of photoresist is applied to the passivation layer. Then, the photoresist layer is patterned using a photolithography mask. The mask may be a positive mask or a negative mask. Then, the first polyimide layer and the passivation layer are etched. Accordingly, openings are formed in the first polyimide layer and the passivation layer. Next, the remaining photoresist may be removed.

In the block614, the system deposits the RDL to the first polyimide layer and in the openings of the first polyimide layer and the passivation layer. The RDL maybe copper or another metal. The system deposits the RDL using sputtering, evaporation, or CVD. The RDL is deposited into pillars based on the pattern in the first polyimide layer. The system also patterns the RDL. In one example, photoresist is deposited on the polyimide layer and patterned before the deposition of the RDL. Then, liftoff is performed to pattern the RDL. In another embodiment, photolithography and etching is performed on the RDL.

In the block618, the system forms and patterns a second polyimide layer. The system may form the second polyimide layer using step-growth polymerization or solid-phase synthesis. The second polyimide layer may be the same thickness as the first polyimide layer, thinner than the first polyimide layer, or thicker than the first polyimide layer. The system patterns the second polyimide layer using photolithography and etching. Photoresist is applied to the second polyimide layer. The photoresist is exposed by a photolithography mask. Then, the second polyimide layer is etched in the regions where the photoresist has been removed. The photoresist may be removed.

In the block622, the system deposits an UBM layer. The UBM may be composed of titanium or a titanium alloy, such as TiW. The UBM may be deposited by sputtering, evaporating, or electroless plating.

In the block626, the system forms a solder bump to the UBM layer deposited in the block622. The solder bump may be composed of Sn/Pb, Pb, Sn/Ag/Cu, Sn/Ag, or another alloy, which may be lead based solder or lead free solder. Bumping may be performed with repassivation with wet film or with dry film. With bumping with passivation and wet film, the system applies, exposes, and develops photoresist on the UBM. Then, the system performs copper/solder plating or copper/nickel/solder plating. The system strips the photoresist, and etches the UBM. Finally, the system reflows the UBM, to form the solder ball. In bumping with dry film, the system performs dry film lamination, exposure, and developing. Then, the system plates the dry film lamination Cu/Ni/solder plating. Next, dry film stripping is performed, followed by UBM etching. Finally, the system performs reflowing, to form the solder bump.

FIG.6illustrates the flowchart700for an embodiment method of utilizing a semiconductor structure in WCSP. In the block702, the system dices chips, to form die. Multiple chips may each contain a bump structure, such as the semiconductor structure100illustrated byFIG.1. The wafer dicing may be performed by scribing and breaking, mechanical sawing, for example using a dicing saw, or laser cutting. The wafer may be mounted on dicing tape during dicing.

In the block704, the die are separately mounted on PCBs. The die are flipped and positioned with the solder ball facing the appropriate circuitry on the PCB. The solder balls are remelted, for example using hot air reflow. The mounted chip may be underfilled using electrically-insulating adhesive, to provide support and protection.

In the block706, the circuits of the die on the PCB operate. For example, a power transistor, such as NexFET™ devices, made by Texas Instruments, may perform power switching. The power transistor may operate with low resistance and high current density. In one example, the power transistor may operate with up to 5 A.

Although the example illustrative arrangements have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the present application as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular illustrative example arrangement of the process, machine, manufacture, and composition of matter means, methods and steps described in this specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding example arrangements described herein may be utilized according to the illustrative arrangements presented and alternative arrangements described, suggested or disclosed. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.