System level crosstalk mitigation

An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to system level mitigation of crosstalk in serial lanes.

BACKGROUND

SUMMARY

An information handling system includes a receiver having a margin detector and a first control module. The margin detector derives an eye plot for a plurality of signals received via a plurality of high speed serial lanes. The first control module identifies a weakest lane of the high speed serial lanes, and compares eye plots for the first signal on the weakest lane from one crosstalk minimization iteration to a next crosstalk minimization iteration. A transmitter includes a second control module and a phase shift module. The second control module receives a signal from the first control module indicating whether an eye plot of the first signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each crosstalk minimization iteration until the eye plot of the first signal is optimized. The phase shift module phase shifts the aggressor signals during each iteration of the crosstalk minimization iterations.

DETAILED DESCRIPTION OF DRAWINGS

Serial channel100includes a transmitter110, multiple transmission channels, such a transmission channels120and122, and a receiver130. Serial channel100represents one half of a bi-directional serial data link for communicating data from transmitter110located at a first component to receiver130located at a second component. The other half of the bi-directional serial data link is similar to serial channel100, but with a receiver in the first component, and a transmitter in the second component, for communicating data back from the second component to the first component. Here, the components can be understood to include elements within an information handling system, such as components that are attached to one or more printed circuit board of the information handling system, where transmission channel120can represent one or more circuit traces on the printed circuit board, and can include one or more connectors. The components can also be understood to include devices of an information handling system, such as a hard drive, a storage array, and the like, that are separate from the printed circuit board of the information handling system, where transmission channel120can include one or more transmission cables. An example of serial channel100includes a PCI-Express (PCIe) channel that is in compliance with one or more PCIe specification, up to, and including the PCIe 4.0 Specification, a Serial ATA (SATA) channel that is in compliance with one or more SATA specification, up to, and including the SATA 3.2 Specification, a SAS channel that is in compliance with one or more SAS specification, up to and including the Serial Attached SCSI 4.0 Standard, user programmatic interface (UPI), Infiniband, extended attachment unit interface (XAUI), or another high speed serial channel.

Serial channel100operates to provide back channel adaptation where transmitter110and receiver130communicate with each other to optimize and adjust various compensation values within the transmitter and the receiver to compensate for the insertion loss of transmission channel120. A determination is made as to whether or not a set of compensation values is satisfactory based upon a determination of the bit error rate (BER) associated with the set of values. It is possible for multiple different sets of compensation values to result in acceptable BER in serial channel100. Moreover, even on a particular information handling system, operating at different times, the back channel adaptation mechanism may operate to provide different sets of compensation values based upon minute variations in the operating condition of the information handling system.

As such, serial channel100operates to perform the back channel adaptation repeatedly, recording the set of compensation values for each iteration of the back channel adaptation, in order to determine a most common or most frequently recurring set of compensation values. Then serial channel100further operates to use the most frequently recurring set of compensation values as a seed for further optimization of the receiver eye in order to determine the final run time set of compensation values.

For example, a typical back channel adaptation operation can operate at a 10 gigabit per second (Gb/s) data rate, and can provide a training sequence of 2000 bits, such that the back channel adaptation operation takes 200 microseconds (μs), and serial channel100can operate to provide 1000 iterations of the back channel adaptation operation, such that the common set of compensation values is determined in 0.2 s. Using the common set of compensation values, serial channel100can adjust each value of the common set of compensation values by +/−1 setting value, and re-run the back channel adaptation operation in order to determine if the receiver eye is improved. Serial channel100can then select the set of values that produces the best receiver eye.

Transmitter110includes a de-emphasis module112, a channel management module114, and a phase shift module116. In operation, serial data is provided to de-emphasis module112, and the de-emphasis module operates to provide a reduction in the signal levels of the serial data after a first data bit is transmitted, in order to de-emphasize the subsequent data bits. The phase shift module116operates to receive the de-emphasized data bits, to provide a phase shift to the data bits, and to transmit the phase shifted de-emphasized serial data to receiver130via transmission channel120. Channel management module114.

Receiver130includes a multiplexor132, a continuous time linear equalization (CTLE) module134, an automatic gain control (AGC) module136, a decision feedback equalization (DFE) module138, a margin detector140, a control logic module152, and a channel management module154. During back channel adaption operation, the CTLE module134, the AGC module136, and the DFE module138perform an iterative process to ensure that the receiver130compensates for channel loss. In operation, during the back channel adaption operation, the first serial data provided to the receiver130is not phase shift, such that the serial data is only de-emphasized. The de-emphasized serial data is received by multiplexor132, the multiplexor provides the received signal to CTLE module134, and the CTLE module operates to provide compensation for inter-signal interference (ISI) in order to open the signal eye of the received signal. The amount of compensation is determined based upon an equalization setting. For example, receiver130can support21equalization settings which each prescribe a different amount of equalization, from 0 dB to 10 dB, in 0.5 dB steps. Other numbers of settings and amounts of equalization prescribed by the equalization setting can be utilized, as needed or desired.

The equalized signal is provided from CTLE module134to AGC module136. AGC module136operates to provide linear gain to the signal received from CTLE module134to further open the signal eye of the received signal. The amount of gain is determined by a gain setting, and can support21gain settings which each prescribe a different amount of gain, for example, from 0 dB to 10 dB, in 0.5 dB steps. Other numbers of settings and amounts of gain prescribed by the gain setting can be utilized, as needed or desired.

The amplified signal is provided from AGC module136to DFE module138. DFE module138operates to provide feedback based compensation to the received signal. The amount of compensation is determined by enabling a number of circuit feedback taps. For example, DFE module138can support up to 16 taps that provide compensation based upon up to 16 previous data points. In a particular embodiment, DFE module138can be turned off, thereby reducing the power consumed by receiver130. In another embodiment, one or more tap of DFE module138can be turned on based upon the taps setting, while the rest of the taps are placed into a tri-state condition, that is, with power applied, but with the taps not providing feedback to the resultant DFE compensation. In yet another embodiment, one or more tap of DFE module138can be turned on based upon the taps setting, while the rest of the taps are turned off, thereby reducing the power consumed by receiver130. Other numbers of taps can be utilized, as needed or desired.

Register150stores the eye height and eye width information in order to determine a set of compensation values that provides the best receiver eye for receiver130. A management controller160operates to coordinate the determination of receiver eye information for multiple serial channels similar to serial channel100. As such, multiplexor132operates to receive inputs from multiple transmission channels similar to transmission channel120, and selectively routes the received signals to margin detector140. In this way, a multi-channel device can include a single set of elements for determining the receiver eye information of multiple transmission channels.

In operation, control logic module152performs the back channel adaptation repeatedly, recording the set of compensation values for each iteration of the back channel adaptation in a memory of receiver130, in order to determine a most common or most frequently recurring set of compensation values. In a particular embodiment, only the set of compensation values for receiver130are considered in determining the most frequently recurring set of compensation values. In another embodiment, the compensation values for both transmitter110and receiver130are considered in determining the most frequently recurring set of compensation values. In a particular embodiment, the memory includes a counter associated with each particular combination of compensation value settings, and each time a particular set of compensation values is derived, the counter is incremented. Then, when the iterations of the back channel adaptation are complete, control logic module152determines which counter includes the highest count. In another embodiment, receiver130includes a number of storage locations that is equal to the number of iterations, and on each successive iteration, the set of compensation values for that iteration are stored in the associated storage location. Then, when the iterations of the back channel adaptation are complete, control logic module152parses the values of the storage locations to determine the most common value.

Control logic module152then uses the most common set of compensation values as a seed for further optimization of the receiver eye, by directing the phase shift module116to iteratively adjust the phase shift of the serial data in neighboring transmission channels by +/−one (1) setting value, and direct the signal received on transmission channel120through multiplexor132to margin detector140to determine the receiver eye height and eye width of the serial data on transmission channel120associated with each adjusted setting. Also, during the back channel adaption operation, the channel management modules154and114can communicate to reduce crosstalk between the different communication channels in the system, such as communication channels120and122. The channel management module154can provide data associated with an eye plot to the channel management module114, which in turn can cause the phase shift module116to provide phase shift signals to compensate for crosstalk between the high speed lanes of the communication channels as shown in a pin-out of a printed circuit board (PCB)200ofFIG. 2, that the transmitter receives the signals from.

FIG. 2illustrates multiple groups of high speed serial lanes pin-out on the PCB200, which includes multiple groups of high speed serial lanes202,204,206,208,210, and212. As the speed of high speed serial interfaces increases, variations in circuit design, component manufacture, environmental conditions, and other factors make it increasingly difficult to ensure highly reliable data transmission. In particular, transmitter and receiver equalization mechanisms to compensate for channel loss and crosstalk are calibrated on a best-effort basis, where settings that result in a “good enough” compensation solution are quickly obtained, in favor of iterative processes that might yield a more optimal solution, but which require an inordinate amount of time for such link training.

The groups of high speed lanes202,204,206,208,210, and212can be PCIe groups, UPI groups, Infiniband groups, XAUI groups, or the like. In an embodiment, the pin-out of the different groups202,204,206,208,210, and212can cause the pins of one group to be coupled to the pins of another group, such that crosstalk coupling can result across the different groups. The group of high speed lane or lanes with the weakest signal, such as group202, can be the group affected the most by crosstalk from other groups. As shown by the arrows inFIG. 2, groups204,206,208,210, and212can all be coupled to group202, such that these groups can weaken the signal or signals transmitted on the communication channel connected to the pin-outs of group202on PCB200. Therefore, during the back channel adaption operation, the channel management modules154and114can communicate to reduce crosstalk between the different communication channels in the groups202,204,206,208,210, and212as will be discussed with respect toFIG. 1.

Referring back toFIG. 1, the channel management module154can determine the weakest signal received from the transmitter110. The transmitter110can then send a predetermined signal to the receiver130over the weakest serial lane, such as communication channel120, at the same time that the transmitter sends signals across the other serial lanes, such as communication channel122. In an embodiment, the signals sent on the other serial lanes can be referred to as aggressor signals. In an embodiment, the aggressor signals can be signals transmitted over all other serial lanes, can be the signals transmitted over a select number of serial lanes, such as the serial lanes nearest to the weakest lane on the PCB200, or the like. The margin detector150can then derive an eye for the predetermined signal received on the communication channel120, and store data for the eye in the register150.

If the aggressor signals are defined as the signal transmitted across all of the other serial lanes in the transmitter110, the crosstalk minimization operation can be referred to as a brute force operation because the channel management modules154and114do not identify the serial lanes that have the most effect on the weakest lane. However, the channel management modules154and114can introduce intelligence into the crosstalk minimization operation by identifying the serial lanes that cause the most crosstalk on the signal of the weakest lane. In this situation, identification of the serial lanes that cause the most crosstalk can be via board review of the PCB200, heuristic analysis of similar PCBs that can be stored in a database of register130, detection of lanes/groups of lanes nearest in proximity to the weakest lane on the PCB200, or the like. Thus, the channel management modules154and114can identify the aggressor signals as either the signals on all other serial lanes, or the signals on the serial lanes that cause the most crosstalk on the weakest lane.

After the channel management module154and114have identified the aggressor signals, the channel management module114can cause the phase shift module116to introduce a phase shift into aggressor signals prior to signal being transmitted by the weakest lane and the lanes transmitting the aggressor signals. In an embodiment, the phase shift can be in any amount, such as 0.1 unit interval (UI) of a clock signal utilized in the transmission of the signals. The phase shift can also be in either the positive or negative direction.

The margin detector140can then derive a new eye plot for the signal on the weakest lane after reception of the signal on the weakest lane and the reception of the signals on the aggressor lanes. The margin detector140can then store the data for the new eye plot in register150. The channel management module154can then determine whether an eye opening of the eye for the signal on the weakest serial lane has improved in response to phase shift of the aggressor signals. If the eye opening for the signal on the weakest lane has improved in response to the phase shift, the channel management module114can cause the phase shift module116to provide a second phase shift to the aggressor signals. Thus, the channel management modules154and114can cause an iterative process of increasing the phase shift of the aggressor signals until no improvement is detected in the eye plot of the signal on the weakest lanes.

When the eye opening for the signal on the weakest lane has not improved in response to most recent the phase shift, the channel management module154can store the data associated with the most recent phase shift of the aggressor signals, and provide a signal to channel management module114to cause a phase shift on the aggressor signals in a direction opposite to the direction of the first iterative phase shift process. The channel management modules154and114can then control the iterative phase shift process in the second direction, and the margin detector150can derive an eye plot for the signal on the weakest lane after each iteration and the channel management module154can determine whether the eye of the current eye plot has improved. When the eye opening for the signal on the weakest lane has not improved in response to most recent the phase shift, the channel management module154can store the data associated with the most recent phase shift of the aggressor signals. The channel management module114can then determine the phase shift of the aggressor signals that resulted in the most improvement for the eye plot of the signal on the weakest lane and store the data associated with this phase shift along with the other derived data from the back channel adaptation. The transmitter110can then start sending signals to the receiver130using the data of the back channel adaption including the phase shift of the aggressor signals. In an embodiment, the phase shift can be for neighboring aggressor signals and not for all aggressor signals in the PCB200.

FIG. 3illustrates a method300for reducing crosstalk in a weakest serial link of a system according to an embodiment of the present disclosure. At block302, a weakest serial lane in the system is identified. In an embodiment, the weakest serial lane can be identified by as the serial lane that has the highest level of signal attenuation as compared to the other serial lanes in the system. In an embodiment, the serial lanes can be grouped into one or more groups as shown inFIG. 2above. At block304, auto-negotiation is performed. Link training is begun at block306. During link training, a transmitter and receiver in the system perform a back channel adaption operation as described above with respect toFIG. 1.

At block308, a predetermined signal is sent to the receiver on the weakest serial lane. An eye for the predetermined signal is derived at block310. In an embodiment, the eye is derived based values derived during the back channel adaption operation. At block312, a phase shift is introduced into aggressor signals in a positive direction. In an embodiment, an aggressor signal is any signal that causes crosstalk with the signal in the weakest serial lane, such as signals transmitted on links or lane within the same group as the weakest serial lane, or signals transmitted on lanes within other groups in the system. The phase shift can be in any amount, such as 0.1 unit interval (UI) of a clock signal utilized in the transmission of the signals in the different transmission channels. In an embodiment, the phase shift is applied to all of the other signals in the system, and the phase shift can be applied to each of the other signals at the same time, at different intervals, or the like. In an embodiment, block311is executed prior to block312. In this embodiment, a determination is made as to the lanes that create a greatest amount of crosstalk on the weakest serial lane at block311.

The addition of block311into the method can provide intelligence into the crosstalk minimization instead of utilizing brute force phase shifting. In an embodiment, the brute force method applies the phase shifting to all other signals in the system. However, the intelligence phase shifting determines the lanes that have the greatest amount of crosstalk with the weakest lane as described above.

At block314, a determination is made whether an eye opening of the eye for the signal on the weakest serial lane has improved in response to phase shift of the aggressor signals. If the eye opening for the signal on the weakest lane has improved in response to the phase shift, the flow continues as stated above at block312and another interval of phase shifting is applied to the signals on the aggressor lanes. However, if the eye opening for the signal on the weakest lane has not improved in response to most recent the phase shift, the flow continues at bock316and a phase shift is introduced into aggressor signals in a negative direction.

At block318, a determination is made whether an eye opening of the eye for the signal on the weakest serial lane has improved in response to phase shift of the aggressor signals. If the eye opening for the signal on the weakest lane has improved in response to the phase shift, the flow continues as stated above at block316and another interval of phase shifting is applied in the negative direction to the signals on the aggressor lanes. However, if the eye opening for the signal on the weakest lane has not improved in response to most recent the phase shift, the flow continues at block320and the phase shift is locked for all of the aggressor signals. At block322, the crosstalk minimization operation is ended. Data is communicated across the serial lanes at block324.

Information handling system400can include devices or modules that embody one or more of the devices or modules described above, and operates to perform one or more of the methods described above. Information handling system400includes a processors402and404, a chipset410, a memory420, a graphics interface430, include a basic input and output system/extensible firmware interface (BIOS/EFI) module440, a disk controller450, a disk emulator460, an input/output (I/O) interface470, and a network interface480. Processor402is connected to chipset410via processor interface406, and processor404is connected to the chipset via processor interface408. Memory420is connected to chipset410via a memory bus422. Graphics interface430is connected to chipset410via a graphics interface432, and provides a video display output436to a video display434. In a particular embodiment, information handling system400includes separate memories that are dedicated to each of processors402and404via separate memory interfaces. An example of memory420includes random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/EFI module440, disk controller450, and I/O interface470are connected to chipset410via an I/O channel412. An example of I/O channel412includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. Chipset410can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/EFI module440includes BIOS/EFI code operable to detect resources within information handling system400, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module440includes code that operates to detect resources within information handling system400, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller450includes a disk interface452that connects the disc controller to a hard disk drive (HDD)454, to an optical disk drive (ODD)456, and to disk emulator460. An example of disk interface452includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator460permits a solid-state drive464to be connected to information handling system400via an external interface462. An example of external interface462includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive464can be disposed within information handling system400.

I/O interface470includes a peripheral interface472that connects the I/O interface to an add-on resource474, to a TPM476, and to network interface480. Peripheral interface472can be the same type of interface as I/O channel412, or can be a different type of interface. As such, I/O interface470extends the capacity of I/O channel412when peripheral interface472and the I/O channel are of the same type, and the I/O interface translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel472when they are of a different type. Add-on resource474can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource474can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system400, a device that is external to the information handling system, or a combination thereof.

Network interface480represents a NIC disposed within information handling system400, on a main circuit board of the information handling system, integrated onto another component such as chipset410, in another suitable location, or a combination thereof. Network interface device480includes network channels482and484that provide interfaces to devices that are external to information handling system400. In a particular embodiment, network channels482and484are of a different type than peripheral channel472and network interface480translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels482and484includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels482and484can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.