LIGHT RECEIVING ELEMENT AND DISTANCE MEASURING SYSTEM

The present technology relates to a light receiving element and a distance measuring system capable of achieving high PDE while preventing edge break. A light receiving element includes a pixel in which a multiplication region is formed in a region where a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first semiconductor region are joined, and a planar region of the second semiconductor region formed at a position closer to a light receiving surface than the first semiconductor region is formed to be larger. The present technology can be applied to, for example, a distance measuring system or the like that detects a distance to a subject in a depth direction.

TECHNICAL FIELD

The present technology relates to a light receiving element and a distance measuring system, and more particularly to a light receiving element and a distance measuring system capable of achieving high PDE while preventing edge break.

BACKGROUND ART

In recent years, a distance measuring sensor that measures a distance by a Time-of-Flight (ToF) method has attracted attention. Examples of the distance measuring sensor include a distance measuring sensor using a single photon avalanche diode (SPAD) as a light receiving pixel. In the SPAD, avalanche amplification occurs when one photon enters a PN junction region of a high electric field in a state where a voltage larger than a breakdown voltage (hereinafter referred to as excess bias (ExcessBias)) is applied. By detecting the timing at which the current instantaneously flows at that time, the distance can be measured with high accuracy.

For example, Patent Document 1 discloses a pixel structure in which an area of a p-type semiconductor region of a multiplication region including an n-type semiconductor region and a p-type semiconductor region is formed smaller than an n-type semiconductor region in order to reduce a strong electric field (edge break) at an end portion of the multiplication region where avalanche amplification occurs.

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

However, the pixel structure of Patent Document 1 has high internal resistance, requires a large excessive bias, and has room for improvement.

The present technology has been made in view of such a situation, and an object thereof is to make it possible to achieve high photon detection efficiency (PDE) while preventing edge break.

Solutions to Problems

A light receiving element according to a first aspect of the present technology includes a pixel in which a multiplication region is formed in a region where a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first semiconductor region are joined, and a planar region of the second semiconductor region formed at a position closer to a light receiving surface than the first semiconductor region is formed to be larger.

A distance measuring system according to a second aspect of the present technology includes a lighting device that emits irradiation light, and a light receiving element that receives reflected light obtained by reflecting the irradiation light by a subject, in which the light receiving element includes a pixel in which a multiplication region is formed in a region where a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first semiconductor region are joined, and a planar region of the second semiconductor region formed at a position closer to a light receiving surface than the first semiconductor region is formed to be larger.

In the first and second aspects of the present technology, a multiplication region is formed in a region where a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first semiconductor region are joined, and a planar region of the second semiconductor region formed at a position closer to a light receiving surface than the first semiconductor region is formed to be larger.

The light receiving element and the distance measuring system may be independent devices, or may be modules incorporated in other devices.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, modes for carrying out the present technology (hereinafter referred to as an embodiment) will be described with reference to the accompanying drawings. Note that in the description and the drawings, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant descriptions are omitted. The description will be made in the following order.1. Pixel circuit using SPAD2. First pixel structure of pixel3. Modification example of first pixel structure of pixel4. Second pixel structure of pixel5. Third pixel structure of pixel6. Fourth pixel structure of pixel7. Fifth pixel structure of pixel8. Sixth pixel structure of pixel9. Seventh pixel structure of pixel10. Manufacturing method of seventh pixel structure11. Modification example of seventh pixel structure of pixel12. Eighth pixel structure of pixel13. Ninth pixel structure of pixel14. Tenth pixel structure of pixel15. Configuration example of stacked structure16. Pixel circuit that performs active quenching17. Configuration example of light receiving element18. Configuration example of distance measuring system19. Application example to electronic device20. Application example to mobile body

Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from the actual ones. Furthermore, the drawings may include portions having different dimensional relationships and ratios.

Furthermore, definitions of directions such as up and down in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present disclosure. For example, when an object is observed by rotating the object by 90°, the upper and lower sides are read by converting into left and right, and when an object is observed by rotating the object by 180°, the upper and lower sides are read by inverting.

FIG.1illustrates a pixel circuit using a single photon avalanche diode (SPAD) applicable to a light receiving element of a distance measuring sensor that measures a distance by a time-of-flight (ToF) method.

The pixel10inFIG.1includes a SPAD21, a constant current source22, a transistor23, and an inverter24.

A cathode of the SPAD21is connected to the constant current source22, and is connected to an input terminal of the inverter24and a drain of the transistor23. An anode of the SPAD21is connected to a power supply VSPAD.

The SPAD21is a photodiode (single photon avalanche photodiode) that performs avalanche amplification of generated electrons and outputs a signal of a cathode voltage VS when incident light is incident. The power supply VSPAD supplied to the anode of the SPAD21is, for example, a negative bias (negative potential) having the same voltage as the breakdown voltage VBD of the SPAD21.

The constant current source22includes, for example, a P-type MOS transistor that operates in a saturation region, and performs passive quenching by acting as a quenching resistor. A power supply voltage VE (VE>0) is supplied to the constant current source22. Note that for the constant current source22, a pull-up resistor or the like can also be used instead of the P-type MOS transistor.

In order to detect light (photons) with sufficient efficiency, a voltage (hereinafter referred to as excess bias (ExcessBias)) larger than the breakdown voltage VBD of the SPAD21is applied to the SPAD21.

The drain of the transistor23is connected to the cathode of the SPAD21, the input terminal of the inverter24, and the constant current source22, and a source of the transistor23is connected to the ground (GND). A gating control signal VG is supplied to a gate of the transistor23from a pixel drive section that drives a pixel.

In a case where the pixel10is an active pixel, a low (Lo) gating control signal VG is supplied from the pixel drive section to the gate of the transistor23. On the other hand, in a case where the pixel10is an inactive pixel, a high (Hi) gating control signal VG is supplied from the pixel drive section to the gate of the transistor23.

The inverter24outputs a Hi PFout signal when the cathode voltage VS as an input signal is Lo, and outputs a Lo PFout signal when the cathode voltage VS is Hi.

Next, an operation in a case where the pixel10is set as an active pixel will be described with reference toFIG.2.FIG.2is a graph illustrating a change in the cathode voltage VS of the SPAD21in response to incidence of photons and a detection signal PFout.

First, in a case where the pixel10is an active pixel, the transistor23is set to off by the Lo gating control signal VG.

At a time before time to inFIG.2, since the power supply voltage VE is supplied to the cathode of the SPAD21and the power supply VSPAD is supplied to the anode, a reverse voltage larger than the breakdown voltage VBD is applied to the SPAD211, thereby setting the SPAD21to the Geiger mode. In this state, the cathode voltage VS of the SPAD21is the same as the power supply voltage VE.

When photons are incident on the SPAD21set in Geiger mode, avalanche multiplication occurs, and a current flows through the SPAD21.

When avalanche multiplication occurs at time to and a current flows through the SPAD21, after time to, by the current flowing through the SPAD21, a current also flows through the P-type MOS transistor as the constant current source22, and a voltage drop occurs due to a resistance component of the MOS transistor.

When the cathode voltage VS of the SPAD21becomes lower than 0 V at time t2, the voltage becomes lower than the breakdown voltage VBD, so that the avalanche amplification stops. Here, a quenching operation is such that the current generated by the avalanche amplification flows through the constant current source22to generate a voltage drop, and the cathode voltage VS becomes lower than the breakdown voltage VBD along with the generated voltage drop, thereby stopping the avalanche amplification.

When the avalanche amplification is stopped, the current flowing through the constant current source22(P-type MOS transistor) gradually decreases, and at time t4, the cathode voltage VS returns to the original power supply voltage VE again, making it capable of detecting a next new photon (recharging operation).

The inverter24outputs the Lo (low) PFout signal when the cathode voltage VS, which is an input voltage, is equal to or higher than a predetermined threshold voltage Vth (=VE/2), and outputs the Hi PFout signal when the cathode voltage VS is lower than the predetermined threshold voltage Vth. In the example ofFIG.4, the Hi (high) PFout signal is output in a period from time t1to time t3.

Note that, in a case where the pixel10is an inactive pixel, the Hi gating control signal VG is supplied from the pixel drive section to the gate of the transistor23, and the transistor23is turned on. Thus, the cathode voltage VS of the SPAD21becomes 0 V (GND), and an anode-cathode voltage of the SPAD21becomes equal to or lower than the breakdown voltage VBD, and thus no reaction occurs even if photons enter the SPAD21.

<2. First Pixel Structure of Pixel>

FIG.3is a view illustrating a first pixel structure of the pixel10using the SPAD21described above.

FIG.3illustrates a pixel structure of a portion corresponding to one pixel among a plurality of pixels formed on a semiconductor substrate31including silicon or the like, and A ofFIG.3is a cross-sectional view of the pixel10.

In the cross-sectional view of the pixel10illustrated in A ofFIG.3, only the structure of the semiconductor substrate31is illustrated, and a lower side of A ofFIG.3is a back surface side of the semiconductor substrate31, which is an incident surface side on which an on-chip lens or the like are formed, and reflected light that is reflected from the object is incident.

On the other hand, an upper side of A ofFIG.3is a front surface side of the semiconductor substrate31, and although not illustrated, a wiring layer including a circuit for driving the pixel and the like is formed.

B ofFIG.3is a plan view of the pixel10of A ofFIG.3as viewed from the front surface side of the semiconductor substrate31.

As illustrated in A ofFIG.3, the pixel10includes an n-well41, an n-type semiconductor region42, a high-concentration n-type semiconductor region43, a p-type semiconductor region44, a hole accumulation region45, and a high-concentration p-type semiconductor region46. Then, an avalanche multiplication region47is formed by a depletion layer formed in a region where the n-type semiconductor region42and the p-type semiconductor region44are bonded.

The n-well41is formed by being controlled to n-type (n-) in which impurity concentration of the semiconductor substrate31is thin, and forms an electric field that transfers electrons generated by photoelectric conversion in the pixel10to the avalanche multiplication region47. Note that instead of the n-well41, a p-well in which the impurity concentration of the semiconductor substrate31is controlled to p-type may be formed.

As illustrated in B ofFIG.3, the n-type semiconductor region42is a thick n-type (first conductivity type) semiconductor region (first semiconductor region) formed at a predetermined depth from the front surface side of the semiconductor substrate31in a central portion of the pixel region. Then, in the n-type semiconductor region42, in particular, the vicinity of a surface of a central portion is controlled to have a high concentration (n+) of impurities to form the high-concentration n-type semiconductor region43. The high-concentration n-type semiconductor region43is a contact portion (first contact portion) connected to a contact electrode51as a cathode for supplying a negative voltage for forming the avalanche multiplication region47. The power supply voltage VE is applied from the contact electrode51to the high-concentration n-type semiconductor region43.

The p-type semiconductor region44is a thick p-type (second conductivity type) semiconductor region (second semiconductor region) formed from a depth position in contact with a bottom surface of the n-type semiconductor region42in the semiconductor substrate31over the entire surface of the pixel region with a predetermined thickness (depth).

Here, the impurity concentration of the n-well41is set to a low concentration of, for example, 1E+14/cm3or less, and the impurity concentration of each of the n-type semiconductor region42and the p-type semiconductor region44forming the avalanche multiplication region47is desirably controlled to have a high concentration of 1E+16/cm3or more.

The hole accumulation region45is a p-type semiconductor region (p) formed so as to surround a side surface and a bottom surface of the n-well41, and accumulates holes generated by photoelectric conversion. Furthermore, the hole accumulation region45traps electrons generated at the interface with the pixel separation portion48and also has an effect of suppressing a dark count rate (DCR). A region in the vicinity of the substrate front surface side of the hole accumulation region45is particularly controlled to have a high impurity concentration (p+) to form the high-concentration p-type semiconductor region46. The high-concentration p-type semiconductor region46is a contact portion (second contact portion) connected to the contact electrode52as an anode of the SPAD21. The power supply VSPAD is applied from the contact electrode52to the high-concentration p-type semiconductor region46. The hole accumulation region45can be formed by ion implantation, and may be formed by solid-phase diffusion.

A pixel separation portion48that isolates pixels from each other is formed at a pixel boundary portion of the pixel10, which is a boundary with an adjacent pixel. For example, the pixel separation portion48may include only an insulating layer such as a silicon oxide film, or may have a double structure such that an outer side (n-well41side) of a metal layer such as tungsten is covered with an insulating layer such as a silicon oxide film.

As described above, in the pixel10according to the first pixel structure, regarding planar regions of the n-type semiconductor region42and the p-type semiconductor region44in which the avalanche multiplication region47is formed, the planar region of the p-type semiconductor region44is formed larger than the planar region of the n-type semiconductor region42. Furthermore, regarding depth positions of the n-type semiconductor region42and the p-type semiconductor region44from the substrate front surface, the p-type semiconductor region44is formed at a deeper position than the depth position of the n-type semiconductor region42. In other words, the p-type semiconductor region44is formed at a position closer to a light receiving surface than the n-type semiconductor region42.

Note that, in the plan view illustrated in B ofFIG.3in which the pixel10is viewed from the front surface side of the semiconductor substrate31, the region between the n-type semiconductor region42and the high-concentration p-type semiconductor region46is exactly the n-well41, but the p-type semiconductor region44lower than the n-well41illustrated in order to illustrate a difference in region size between the n-type semiconductor region42and the p-type semiconductor region44.

The first pixel structure inFIG.3is an example of a structure in which electrons are read out as signal charges (carriers), but a structure in which holes are read out may be used. In this case, the n-type semiconductor region42having a small planar size is changed to a p-type semiconductor region, and the high-concentration n-type semiconductor region43is changed to a high-concentration p-type semiconductor region. The p-type semiconductor region44having a large planar size is changed to an n-type semiconductor region, and the high-concentration p-type semiconductor region46is changed to a high-concentration n-type semiconductor region. The power supply VSPAD is applied from the contact electrode51to the contact portion changed from the high-concentration n-type semiconductor region43to the high-concentration p-type semiconductor region, and the power supply voltage VE is applied from the contact electrode52to the contact portion changed from the high-concentration p-type semiconductor region46to the high-concentration n-type semiconductor region.

<Operations and Effects of First Pixel Structure>

The effect of the structure in which the planar region of the p-type semiconductor region44is formed larger than the planar region of the n-type semiconductor region42in which the avalanche multiplication region47is formed will be described with reference toFIGS.4and5.

In the description ofFIG.4, the same reference numerals as those inFIG.3are given to facilitate understanding.

In general, as illustrated in A ofFIG.4, a structure is conceivable in which the n-type semiconductor region42and the p-type semiconductor region44in which the avalanche multiplication region47is formed are formed in the same plane region so that connection regions overlap.

In this case, as illustrated in the electric field graph on a lower side of A ofFIG.4, an end of the avalanche multiplication region47becomes a strong electric field, and edge breakdown occurs.

Therefore, as illustrated in B ofFIG.4, by reducing the planar sizes of the n-type semiconductor region42and the p-type semiconductor region44in which the avalanche multiplication region47is formed, it is possible to form the avalanche multiplication region47using, so to speak, only the strong electric field portion only at the end portion in A ofFIG.4and having a strong and uniform electric field. In order to form such an avalanche multiplication region47having a uniform electric field, for example, the diameter of the n-type semiconductor region42is preferably two μm or less, and a relative distance in a depth direction between the n-type semiconductor region42and the p-type semiconductor region44is preferably 1000 nm or less.

Therefore, by reducing the planar size of the avalanche multiplication region47, the electric field can be made uniform and the edge breakdown can be prevented, but in the first pixel structure ofFIG.3, the p-type semiconductor region44extends to the hole accumulation region45in a pixel peripheral portion.

The effect of the p-type semiconductor region44extending to the hole accumulation region45in the pixel peripheral portion will be described with reference toFIG.5.

Holes generated by the avalanche amplification move to the hole accumulation region45via the p-type semiconductor region44. An outer peripheral region61, which is a region of the p-type semiconductor region44outside the n-type semiconductor region42in a planar direction, forms a hole current path and has an effect of improving internal resistance (reducing hole resistance).

Furthermore, since the p-type semiconductor region44is formed in the outer peripheral region61of the avalanche multiplication region47in the planar direction, electrons generated in the n-well41by incidence of incident light move to the avalanche multiplication region47inside the outer peripheral region61. That is, the p-type semiconductor region44of the outer peripheral region61has a shielding effect, and the electrons of the n-well41move to the avalanche multiplication region47in a barrierless manner. A barrierless structure from the n-well41to the avalanche multiplication region47achieves high charge collection efficiency.

Therefore, with the first pixel structure of the pixel10illustrated inFIG.3, high PDE can be achieved while edge break is prevented. The achievement of high PDE also allows for low overbias.

<3. Modification Example of First Pixel Structure of Pixel>

FIG.6is a cross-sectional view illustrating a first modification example of the pixel10according to the first pixel structure.

Note that, inFIG.6and subsequent drawings, parts corresponding to those of the first pixel structure illustrated inFIG.3are denoted by the same reference numerals, and description of the parts will be omitted as appropriate.

In the first modification example ofFIG.6, the p-type semiconductor region44forming the avalanche multiplication region47in the first pixel structure illustrated inFIG.3is changed to a p-type semiconductor region44′.

In the first pixel structure illustrated inFIG.3, the planar region of the p-type semiconductor region44extends until reaching the hole accumulation region45in the pixel peripheral portion, but the p-type semiconductor region44′ of the first modification example ofFIG.6does not extend to reach the hole accumulation region45, and an n-well41(fourth semiconductor region) is formed between the p-type semiconductor region44′ and the hole accumulation region45. However, the planar region of the p-type semiconductor region44′ is formed to be larger than the planar region of the n-type semiconductor region42.

As described above, even in a case where the p-type semiconductor region44′ is not formed large enough to be in contact with the hole accumulation region45, since the p-type semiconductor region44′ is formed larger than at least the n-type semiconductor region42, the region (the outer peripheral region61inFIG.5) of the p-type semiconductor region44outside the n-type semiconductor region42in the planar direction forms the hole current path, and thus an effect of improving the internal resistance (reducing hole resistance) is obtained.

FIG.7is a cross-sectional view illustrating a second modification example of the pixel10according to the first pixel structure.

In the first pixel structure illustrated inFIG.3, the pixel separation portion48that separates pixels from each other is formed at the pixel boundary portion of the pixel10, and the hole accumulation region45is formed on the side surface (near the pixel boundary portion) on the pixel center side of the pixel separation portion48.

On the other hand, in the second modification example ofFIG.7, the pixel separation portion48ofFIG.3is omitted. Thus, as compared with the first pixel structure inFIG.3, the hole accumulation region45is provided in the outer peripheral portion so as to be in contact with the boundary portion with the adjacent pixel, and the region of the n-well41is formed to be wider than the first pixel structure inFIG.3.

In this manner, the pixel separation portion48can be omitted.

A ofFIG.8illustrates a plan view of four pixel regions in which the pixels10according to the first pixel structure illustrated inFIG.3are arrayed in 2×2, as viewed from the front surface side of the semiconductor substrate31.

B ofFIG.8illustrates a plan view of four pixel regions in which the pixels10according to the second modification example illustrated inFIG.7are arrayed in 2×2, as viewed from the front surface side of the semiconductor substrate31. In A and B ofFIG.8, dashed lines indicate boundaries of the pixels10.

In a case where the pixel separation portion48is formed at the boundary portions of the pixels10, as illustrated in A ofFIG.8, the pixel separation portion48is arranged around the pixels10, and in an array of a plurality of pixels, the pixel separation portion48is arranged in a lattice pattern.

On the other hand, in a case where the pixel separation portion48is not formed at the boundary portions of the pixels10, as illustrated in B ofFIG.8, the hole accumulation regions45are arranged around the pixels10, and in an array of a plurality of pixels, the hole accumulation regions45are arranged in a lattice pattern.

FIG.9is a third modification example of the pixel10according to the first pixel structure, and illustrates a modification example of the planar shape of the n-type semiconductor region42. The structure other than the n-type semiconductor region42is similar to the first pixel structure illustrated inFIG.3.

In the first pixel structure illustrated inFIG.3, the planar shape of the n-type semiconductor region42is a circular shape, but the planar shape of the n-type semiconductor region42is not limited to a circular shape, and may be a quadrangle, a pentagon, or other polygonal shapes.

A ofFIG.9illustrates an example in which the planar shape of the n-type semiconductor region42is a quadrangular shape.

B ofFIG.9illustrates an example in which the planar shape of the n-type semiconductor region42is a pentagonal shape.

<4. Second Pixel Structure of Pixel>

FIG.10is a cross-sectional view illustrating a second pixel structure of the pixel10using the SPAD21. Note that a plan view of the pixel10according to the second pixel structure as viewed from the front surface side of the semiconductor substrate31is similar to B ofFIG.3in the first pixel structure, and thus is omitted.

When the pixel10according to the second pixel structure ofFIG.10is compared with the pixel10according to the first pixel structure illustrated inFIG.3, an n-type semiconductor region81(fourth semiconductor region) of n-type (n-) having an impurity concentration higher than that of the n-well41is formed in a region deeper (closer to the light receiving surface) than the n-type semiconductor region42and the p-type semiconductor region44forming the avalanche multiplication region47.

In other words, in the pixel10according to the first pixel structure illustrated inFIG.3, the n-well41surrounded by the p-type semiconductor region44and the hole accumulation region45is replaced with the n-well41having a low impurity concentration and the n-type semiconductor region81having an impurity concentration higher than that of the n-well41, and the n-type semiconductor region81is arranged between the n-well41and the p-type semiconductor region44.

Thus, a potential gradient is formed such that carriers (electrons) generated in the n-well41easily drift toward the avalanche multiplication region47.

Note that, depending on the design of the potential gradient, not the n-type semiconductor region81having the same conductivity type as the n-well41but a p-type semiconductor region81′ (fourth semiconductor region) having a conductivity type different from that of the n-well41and a lower impurity concentration than the p-type semiconductor region44may be used as illustrated inFIG.11.

The n-type semiconductor region81and the p-type semiconductor region81′ can be formed by ion implantation in which n-type or p-type ions are implanted.

<5. Third Pixel Structure of Pixel>

FIG.12is a cross-sectional view illustrating a third pixel structure of the pixel10using the SPAD21.

When the pixel10according to the third pixel structure inFIG.12is compared with the pixel10according to the first pixel structure illustrated inFIG.3, the pixel separation portion48formed at the pixel boundary portion is replaced with an inter-pixel trench portion101penetrating the semiconductor substrate31from the front surface side to the back surface side and insulating layers102. The inter-pixel trench portion101is formed by, for example, a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN), or a conductive material such as polysilicon, and a negative voltage larger than that of the anode electrode (contact electrode52) of the SPAD21is applied from the front surface side of the semiconductor substrate31on which the wiring layer is formed. The insulating layers102are formed by, for example, SiO2.

The planar arrangement of the inter-pixel trench portion101and the insulating layers102has a lattice shape similar to that of the pixel separation portion48illustrated in A ofFIG.8.

By forming such inter-pixel trench portion101and insulating layers102, the influence of adjacent pixels can be further reduced, and crosstalk can be further reduced. Furthermore, formation of a lateral electric field makes it easy to collect carriers in the high electric field region, and PDE can be improved.

<6. Fourth Pixel Structure of Pixel>

FIG.13is a cross-sectional view illustrating a fourth pixel structure of the pixel10using the SPAD21.

When the pixel10according to the fourth pixel structure inFIG.13is compared with the pixel10according to the first pixel structure illustrated inFIG.3, a fixed charge film121is formed between the pixel separation portion48and the hole accumulation region45formed at the pixel boundary portion. The fixed charge film121is also formed outside the hole accumulation region45on the back surface side of the semiconductor substrate31in addition to side surfaces between the pixel separation portion48and the hole accumulation region45.

The fixed charge film121is a negative fixed charge film. A hole accumulation region is formed inside the fixed charge film121by induction of holes by the fixed charge film121. A dark current can be suppressed by combining the hole accumulation region formed by the fixed charge film121and the hole accumulation region45formed inside the hole accumulation region, and the DCR can be suppressed. Furthermore, it is possible to easily collect carriers in a high electric field region by reducing crosstalk and forming the lateral electric field, and the PDE can be improved.

<7. Fifth Pixel Structure of Pixel>

A ofFIG.14is a cross-sectional view illustrating a fifth pixel structure of the pixel10using the SPAD21, and B ofFIG.14is a plan view of the pixel10in A ofFIG.14as viewed from the front surface side of the semiconductor substrate31.

When the pixel10according to the fifth pixel structure inFIG.14is compared with the pixel10according to the first pixel structure illustrated inFIG.3, an insulating layer141formed by shallow trench isolation (STI) is newly added.

As illustrated in B ofFIG.14, the insulating layer141is formed on the outer peripheries of the n-type semiconductor region42and the high-concentration n-type semiconductor region43connected to the contact electrode51as the cathode of the SPAD21in the planar direction, and electrically separates the anode and the cathode of the SPAD21from each other.

Note that, because of its purpose to electrically separate the anode and the cathode of the SPAD21, the insulating layer141is not always necessary to be arranged in the periphery adjacent to the n-type semiconductor region42, and is only required to be arranged between the n-type semiconductor region42and the high-concentration n-type semiconductor region43electrically connected to the contact electrode51and the high-concentration p-type semiconductor region46electrically connected to the contact electrode52. For example, the insulating layer141may be formed on the inner peripheral side of the high-concentration p-type semiconductor region46near the substrate front surface.

In B ofFIG.14, the region between the n-type semiconductor region42and the high-concentration p-type semiconductor region46is exactly the n-well41, but the point that the p-type semiconductor region44lower than the n-well41is illustrated is similar to B ofFIG.3.

<8. Sixth Pixel Structure of Pixel>

A ofFIG.15is a cross-sectional view illustrating a sixth pixel structure of the pixel10using the SPAD21, and B ofFIG.15is a plan view of the pixel10in A ofFIG.15as viewed from the front surface side of the semiconductor substrate31.

The pixel10according to the fifth pixel structure illustrated inFIG.14has a configuration in which the anode and the cathode of the SPAD21are separated in the planar direction using the insulating layer141, but the pixel10according to the sixth pixel structure illustrated inFIG.15has a configuration in which the anode and the cathode of the SPAD21are separated by arranging the anode and the cathode of the SPAD21at different depth positions of the semiconductor substrate31.

Specifically, when the pixel10according to the sixth pixel structure inFIG.15is compared with the pixel10according to the first pixel structure illustrated inFIG.3, the pixel separation portion48at the pixel boundary portion of the pixel10is replaced with a conductive member161penetrating the substrate surface on the opposite side from the back surface side or the front surface side of the semiconductor substrate31and an insulating film162formed on both outer sides (inside the pixel) thereof. The conductive member161is formed by, for example, a metal material such as polysilicon or tungsten (W), and the insulating film162is formed by, for example, SiO2.

Furthermore, the high-concentration p-type semiconductor region46, which is the contact portion of the anode of the SPAD21, is embedded and arranged in the semiconductor substrate31. In the example of A ofFIG.15, the position in the depth direction of the high-concentration p-type semiconductor region46is formed at the same position as the p-type semiconductor region44, but the positions in the depth direction of the high-concentration p-type semiconductor region46and the p-type semiconductor region44are not necessarily the same. The high-concentration p-type semiconductor region46on the anode side and the n-type semiconductor region42and the high-concentration n-type semiconductor region43on the cathode side are only required to be arranged at different depth positions.

The conductive member161is connected to the contact electrode52on an upper surface of the front surface of the semiconductor substrate31, and is connected to the high-concentration p-type semiconductor region46in the semiconductor substrate31, and the high-concentration p-type semiconductor region46is electrically connected to the contact electrode52via the conductive member161. The outer peripheral portion of the conductive member161other than the connection region connected to the high-concentration p-type semiconductor region46is covered with the insulating film162, and is electrically separated from the n-well41and the hole accumulation region45.

As described above, the configuration in which the anode and the cathode of the SPAD21are arranged at the different positions in the depth direction of the semiconductor substrate31and separated is effective in a case where the pixel size is reduced. That is, when the anode and the cathode of the SPAD21are arranged on the same plane, there is a limit in a case where the pixel size is miniaturized. Furthermore, since the anode and the cathode of the SPAD21are close to each other, electrical separation is difficult. By arranging the pixels so as to be shifted in the depth direction, the pixel size can be further reduced as compared with a case where the pixels are arranged on the same plane.

<9. Seventh Pixel Structure of Pixel>

A ofFIG.16is a cross-sectional view illustrating a seventh pixel structure of the pixel10using the SPAD21, and B ofFIG.16is a plan view of the pixel10taken along line X-X′ in A ofFIG.16.

InFIGS.16to28to be referred to below, the same reference numerals are given to portions common to the above-described first pixel structure, and the description of the portions will be appropriately omitted.

In the pixel10according to the seventh pixel structure, the point that the avalanche multiplication region47is formed by the depletion layer formed in the junction region between the high-concentration n-type semiconductor region43connected to the contact electrode51as the cathode and the p-type semiconductor region44formed therebelow is similar to the first to sixth pixel structures described above.

In the cross-sectional view of A ofFIG.16, an on-chip lens816omitted in the above-described first to sixth pixel structures is illustrated. The on-chip lens816is formed on the back surface side of the semiconductor substrate31, which is a lower side of A ofFIG.16. The contact electrode51as a cathode, the contact electrode52as an anode, and the like are formed on the front surface of the semiconductor substrate31.

Between the high-concentration n-type semiconductor region43connected to the contact electrode51as a cathode and the high-concentration p-type semiconductor region46connected to the contact electrode52as an anode in the substrate planar direction (lateral direction inFIG.16), a separation layer801physically and electrically separating them is formed. This separation layer801is formed by, for example, a silicon oxide film (SiO2), and has a function similar to that of the insulating layer141of the pixel10according to the fifth pixel structure illustrated inFIG.14. That is, by electrically separating the anode and the cathode of the SPAD21by the separation layer801, edge breakdown in the planar direction between the anode and the cathode can be suppressed. In particular, even in a case where the pixel size of the pixel10is reduced and the distance between the anode and the cathode is shortened, the edge breakdown can be reliably suppressed.

A low-concentration n-type semiconductor region802(sixth semiconductor region) having the same conductivity type (n-type) as the high-concentration n-type semiconductor region43and a lower impurity concentration than the high-concentration n-type semiconductor region43is formed between the separation layer801and the high-concentration n-type semiconductor region43. Moreover, between the separation layer801and the high-concentration p-type semiconductor region46, a high-concentration p-type semiconductor region803(fifth semiconductor region) having a conductivity type (p-type) opposite to that of the high-concentration n-type semiconductor region43and an impurity concentration higher than that of the p-type semiconductor region44is formed. Note that, in the drawings (for example,FIG.14and the like) illustrating the first to sixth pixel structures described above, the impurity concentration of the high-concentration p-type semiconductor region46is represented by “p+”, and inFIG.16, it is also represented by “p+” for the high-concentration p-type semiconductor region803. However, the high-concentration p-type semiconductor region46has an impurity concentration higher than that of the high-concentration p-type semiconductor region803. The impurity concentration of the high-concentration p-type semiconductor region46can be expressed as “p++” in comparison with the high-concentration p-type semiconductor region803.

A one-dot chain line in A ofFIG.16indicates the boundary of the pixel10in the planar direction of the semiconductor substrate31, and a pixel separation portion811is formed at the pixel boundary portion of the pixel10. The pixel separation portion811includes a metal DTI812using tungsten or the like, and a silicon oxide film (insulating layer)813formed inside the metal DTI (on the n-well41side). The pixel separation portion811is another form of the pixel separation portion48such as the pixel10according to the first pixel structure illustrated inFIG.3. Furthermore, the metal DTI812and the silicon oxide film813can also be said to be other forms of the inter-pixel trench portion101and the insulating layer102of the third pixel structure illustrated inFIG.12. A negative voltage may be applied to the metal DTI812as in the third pixel structure illustrated inFIG.12. At a pixel boundary portion on the light incident surface side of the semiconductor substrate31, an inter-pixel light-shielding film814is formed using the same material as the metal DTI812. A silicon oxide film815formed simultaneously with the silicon oxide film813constituting the pixel separation portion811is formed on the interface on the back surface side of the semiconductor substrate31.

As illustrated in B ofFIG.16, the planar shapes of the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, and the separation layer801are circular. The low-concentration n-type semiconductor region802is formed so as to surround the outer periphery of the high-concentration n-type semiconductor region43formed in a circular shape, and the separation layer801is further formed so as to surround the outer periphery of the low-concentration n-type semiconductor region802. The high-concentration p-type semiconductor region803is formed in a region between the separation layer801and the pixel separation portion811formed at the pixel boundary portion and including the metal DTI812and the silicon oxide film813. The separation layer801physically and electrically separates the n-type semiconductor regions of the high-concentration n-type semiconductor region43and the low-concentration n-type semiconductor region802from the p-type semiconductor regions of the high-concentration p-type semiconductor region803and the high-concentration p-type semiconductor region46in the planar direction.

The pixel10according to the seventh pixel structure configured as described above is greatly different from the fifth pixel structure illustrated inFIG.14in that a region above the p-type semiconductor region44(substrate front surface side) in a cross-sectional view and outside the separation layer801in a plan view, in other words, a region between the separation layer801and the high-concentration p-type semiconductor region46is changed from the n-well41to the high-concentration p-type semiconductor region803.

Here, a potential on a line Y-Y′-Y″ indicated by a one-dot chain line in A ofFIG.17is illustrated in B ofFIG.17. Assuming that a point Y is a start point and a point Y″ is an end point, the line Y-Y′-Y″ passes through the high-concentration p-type semiconductor region803, the p-type semiconductor region44, the n-well41, the p-type semiconductor region44, and the high-concentration n-type semiconductor region43in this order, and a potential gradient is formed in which the potential decreases from the point Y toward the point Y″ via the point Y′ as illustrated in B ofFIG.17. The p-type semiconductor region44of the avalanche multiplication region47is depleted.

That is, since the high-concentration p-type semiconductor region803is formed in the region near the substrate front surface above the p-type semiconductor region44, the potential gradient is formed in which the potential decreases from the point Y toward the point Y″ via the point Y′. Thus, the electrons photoelectrically converted in the region near the front surface of the semiconductor substrate31where the high-concentration p-type semiconductor region803is formed can be moved to the avalanche multiplication region47without escaping to the outside of the pixel, so that the PDE can be improved.

Note that the impurity concentration of the high-concentration p-type semiconductor region803is higher than the impurity concentration of the p-type semiconductor region44, but is lower than that of the high-concentration p-type semiconductor region46connected to the anode (contact electrode52). In other words, the energy level of the high-concentration p-type semiconductor region803is lower than the Fermi level, and the impurity concentration of the high-concentration p-type semiconductor region803is a concentration value at which the photoelectrically converted electrons and holes do not recombine. The region having the impurity concentration exceeding the Fermi level is only the high-concentration p-type semiconductor region46connected to the anode (contact electrode52).

The structure around the cathode contact including the separation layer801illustrated as a region831in the cross-sectional view in A ofFIG.17will be described.

A ofFIG.18is an enlarged view of the region831around the cathode contact in A ofFIG.17.

The separation layer801is in contact with the low-concentration n-type semiconductor region802on an inner wall surface (inner peripheral wall surface) in the planar direction, and in contact with the high-concentration p-type semiconductor region803on an outer wall surface (outer peripheral wall surface) in the planar direction, and physically separates the low-concentration n-type semiconductor region802and the high-concentration p-type semiconductor region803. Thus, as described above, the edge breakdown in the planar direction between the anode and the cathode can be suppressed, and the electrons photoelectrically converted in the region near the front surface of the semiconductor substrate31can be moved to the avalanche multiplication region47, so that the PDE can be improved.

A region in contact with the inner peripheral wall surface of the separation layer801is the low-concentration n-type semiconductor region802having an impurity concentration lower than that of the high-concentration n-type semiconductor region43forming the avalanche multiplication region47. Thus, the electric field on the inner peripheral wall surface of the separation layer801can be relaxed.

Furthermore, the separation layer801also has a function of preventing radiation light generated in the avalanche multiplication region47from diffusing outward in the planar direction and entering the adjacent pixels10. Thus, crosstalk caused by the radiation light generated in the avalanche multiplication region47can be reduced.

Note that, in the above description, the separation layer801is formed by a silicon oxide film, but the separation layer801may be formed by another material. For example, the separation layer801may be formed by a low-k film having a low dielectric constant. As a specific material of the low-k film, fluorinated silicate glass, parylene, SiOC, Teflon (registered trademark), SiLK, polyimide, fluorinated amorphous carbon, porous silica, or the like may be mentioned.

B and C ofFIG.18are enlarged views of the region831illustrating another configuration example of the separation layer801.

B ofFIG.18illustrates an example in which the separation layer801is configured by an air gap.

C ofFIG.18illustrates an example in which the separation layer801has a double structure formed by a plurality of materials instead of a single material. The separation layer801in C ofFIG.18has a double structure in which the inside is an air gap841and the outside is a silicon oxide film842. The silicon oxide film842is in contact with the low-concentration n-type semiconductor region802on an inner wall surface (inner peripheral wall surface) in the planar direction, in contact with the high-concentration p-type semiconductor region803on an outer wall surface (outer peripheral wall surface) in the planar direction, and in contact with the p-type semiconductor region44on a bottom surface in the downward direction.

Next, depths of the separation layer801and the low-concentration n-type semiconductor region802in a substrate thickness direction will be described with reference toFIG.19.

In the above-described example, the depths of the separation layer801and the low-concentration n-type semiconductor region802from the substrate front surface are set to the same depth as the pn junction surface of the high-concentration n-type semiconductor region43and the p-type semiconductor region44in which the avalanche multiplication region47is formed, for example, as illustrated in A ofFIG.18.

However, the depth of the separation layer801may be set to a position deeper than the pn junction surface as illustrated in A ofFIG.19. The depth of the low-concentration n-type semiconductor region802can also be formed at the same depth as the separation layer801.

Note that the depth of the low-concentration n-type semiconductor region802does not need to be formed at the same depth as the separation layer801, in other words, on the entire inner peripheral wall surface of the separation layer801, and may be shallower than the separation layer801as illustrated in B ofFIG.19. The depth of the low-concentration n-type semiconductor region802is only required to be a depth between the depth of the high-concentration n-type semiconductor region43on the inside and the depth of the separation layer801on the outside. Even in a case where the separation layer801is formed with a depth in this range, similar effects to the effects described above can be obtained. For example, it can contribute to suppression of edge breakdown due to physical separation between the n-type semiconductor region and the p-type semiconductor region in the planar direction, reduction of crosstalk caused by the radiation light generated in the avalanche multiplication region47, and the like.

FIG.20is a modification example of the pixel10according to the seventh pixel structure, and illustrates another example of the planar shape of the high-concentration n-type semiconductor region43and the like.

In the example of the seventh pixel structure illustrated inFIG.16, the planar shapes of the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, and the separation layer801are circular shapes, but are not limited to the circular shapes, and may be quadrangular, pentagonal, or other polygonal shapes.

A ofFIG.20illustrates an example in which the respective planar shapes of the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, and the separation layer801are quadrangular shapes.

B ofFIG.20illustrates an example in which the respective planar shapes of the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, and the separation layer801are pentagonal shapes.

<10. Manufacturing Method of Seventh Pixel Structure>

Next, a manufacturing method of the separation layer801of the pixel10according to the seventh pixel structure will be described.

<Manufacturing Method in Case where Separation Layer is Formed by Oxide Film>

First, a manufacturing method in a case where the separation layer801is formed by a silicon oxide film will be described with reference toFIG.21. Note thatFIG.21illustrates only a portion corresponding to the region831around the cathode contact illustrated in A ofFIG.17.

First, as illustrated in A ofFIG.21, a silicon oxide film871is formed as an ion-implanted through film on the upper surface on the front surface side of the semiconductor substrate31. Thereafter, ion implantation is performed to form the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, and the high-concentration p-type semiconductor region803in a region near the front surface side of the semiconductor substrate31.

Next, as illustrated in B ofFIG.21, a silicon nitride film872is formed on the silicon oxide film871. By etching the high-concentration p-type semiconductor region803at a position to be the separation layer801using the silicon nitride film872as a hard mask, an opening873is formed at the formation position of the separation layer801as illustrated in C ofFIG.21.

Next, as illustrated in D ofFIG.21, the silicon oxide film871is formed on the semiconductor regions of a bottom surface and a side wall surface of the opening873by, for example, a thermal oxidation method.

Next, as illustrated in E ofFIG.21, a silicon oxide film874is embedded in the opening873by, for example, chemical vapor deposition (CVD) using high density plasma. At this time, the silicon oxide film874is also formed on an upper surface of the silicon nitride film872.

Then, as illustrated in F ofFIG.21, the silicon oxide film874is planarized by chemical mechanical polishing (CMP) to remove the silicon oxide film874formed on the upper surface of the silicon nitride film872. The silicon oxide film874and the silicon oxide film871embedded in the opening873correspond to the separation layer801.

Through the above steps, the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, the separation layer801, and the high-concentration p-type semiconductor region803are completed in the region near the front surface side of the semiconductor substrate31.

<Manufacturing Method in Case where Separation Layer is Formed by Double Structure of Air Gap and Oxide Film>

Next, a manufacturing method in a case where the separation layer801has a double structure of the air gap841and the silicon oxide film842will be described with reference toFIG.22. Note that, inFIG.22, only a portion corresponding to the region831around the cathode contact illustrated in A ofFIG.17is illustrated.

First, as illustrated in A ofFIG.22, a silicon oxide film891is formed as an ion-implanted through film on the upper surface on the front surface side of the semiconductor substrate31. Thereafter, ion implantation is performed to form the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, and the high-concentration p-type semiconductor region803in a region near the front surface side of the semiconductor substrate31.

Next, as illustrated in B ofFIG.22, dry etching is performed to form an opening892at the formation position of the separation layer801. This step is similar to C ofFIG.21, but is in a state in which a hard mask such as a silicon nitride film is removed.

Next, as illustrated in C ofFIG.22, a silicon oxide film891A is formed on a bottom surface and a side wall of the opening892by, for example, CVD. At this time, the silicon oxide film891A can be deposited in a step coverage non-uniform manner by adjusting the gas flow rate, and a silicon oxide film891B is closed and a cavity893can be formed as illustrated in D ofFIG.22by increasing the deposition amount at an upper corner of the opening892. Thus, the cavity893corresponds to the air gap841in C ofFIG.18, and the silicon oxide film891B corresponds to the silicon oxide film842in C ofFIG.18.

Through the above steps, the high-concentration n-type semiconductor region43, the low-concentration n-type semiconductor region802, the separation layer801, and the high-concentration p-type semiconductor region803are completed in the region near the front surface side of the semiconductor substrate31.

<11. Modification Example of Seventh Pixel Structure of Pixel>

FIG.23illustrates a first modification example of the pixel10according to the seventh pixel structure.

A ofFIG.23is a cross-sectional view illustrating the first modification example of the seventh pixel structure, and B ofFIG.23is a plan view of the pixel10taken along line X-X′ in A ofFIG.23.

When the first modification example illustrated inFIG.23is compared with the pixel10according to the seventh pixel structure illustrated inFIG.16, the formation region of the high-concentration p-type semiconductor region803is different, and the other points are common.

That is, in the seventh pixel structure illustrated inFIG.16, the high-concentration p-type semiconductor region803is formed in the entire region in the planar direction from the outer peripheral wall surface of the separation layer801to reach the high-concentration p-type semiconductor region46. On the other hand, in the first modification example ofFIG.23, the high-concentration p-type semiconductor region803is reduced to a region from the outer peripheral wall surface of the separation layer801to before reaching the high-concentration p-type semiconductor region46, and the n-well41is formed between the high-concentration p-type semiconductor region803and the high-concentration p-type semiconductor region46.

As described above, the high-concentration p-type semiconductor region803formed on a substrate front surface side with respect to the p-type semiconductor region44is not required to be formed in the entire region in the planar direction between the separation layer801and the high-concentration p-type semiconductor region46. However, the p-type semiconductor region44needs to be formed in the entire planar region inside (the silicon oxide film813of) the pixel separation portion811in order to prevent electrons photoelectrically converted in the n-well41from escaping to the substrate front surface side.

A ofFIG.24is a cross-sectional view illustrating a second modification example of the pixel10according to the seventh pixel structure.

The second modification example illustrated in A ofFIG.24is the same as the first modification example illustrated inFIG.23in that the high-concentration p-type semiconductor region803is formed in a region from the outer peripheral wall surface of the separation layer801to before reaching the high-concentration p-type semiconductor region46, and the n-well41is formed between the high-concentration p-type semiconductor region803and the high-concentration p-type semiconductor region46.

On the other hand, in the first modification example illustrated inFIG.23, the high-concentration p-type semiconductor region803is formed from an interface on the substrate front surface side to the depth of the p-type semiconductor region44, whereas in the second modification example illustrated in A ofFIG.24, the high-concentration p-type semiconductor region803is not in contact with the interface on the substrate front surface side. In the second modification example, the high-concentration p-type semiconductor region803is formed from a predetermined depth position from the interface on the substrate front surface side to the depth of the p-type semiconductor region44. An n-well41is formed in a region from the interface on the substrate front surface side to where the high-concentration p-type semiconductor region803is formed. The other points are similar to those of the first modification example illustrated inFIG.23.

As described above, the high-concentration p-type semiconductor region803does not necessarily have to be formed so as to be in contact with the interface on the substrate front surface side. In other words, the high-concentration p-type semiconductor region803may be formed in a region buried by a predetermined amount from the interface on the substrate front surface side.

B ofFIG.24is a cross-sectional view illustrating a third modification example of the pixel10according to the seventh pixel structure.

In the third modification example illustrated in B ofFIG.24, the high-concentration p-type semiconductor region803is similar to that of the seventh pixel structure illustrated inFIG.16. That is, the high-concentration p-type semiconductor region803is formed in the entire region in the planar direction from the outer peripheral wall surface of the separation layer801to reach the high-concentration p-type semiconductor region46.

On the other hand, in the third modification example in B ofFIG.24, the planar region of the p-type semiconductor region44is a region from below the high-concentration n-type semiconductor region43forming the avalanche multiplication region47to below the separation layer801, and is not formed in the entire planar region inside the pixel separation portion811. The other points are similar to those of the seventh pixel structure illustrated inFIG.16.

As described above, in a case where the high-concentration p-type semiconductor region803is formed in the entire region in contact with the interface on the substrate front surface side, the p-type semiconductor region44may not be formed in the entire planar region, and may be a planar region of about a lower side of the separation layer801centered on the avalanche multiplication region47.

As described above, if one of the high-concentration p-type semiconductor region803and the p-type semiconductor region44is formed in the entire planar region inside the pixel separation portion811of the pixel10, the other is not required to be formed in the entire planar region.

If both the high-concentration p-type semiconductor region803and the p-type semiconductor region44are not formed in the entire planar region, as illustrated inFIG.25, electrons photoelectrically converted in the n-well41pass through a region where neither the high-concentration p-type semiconductor region803nor the p-type semiconductor region44is formed and escape to the substrate front surface side. Therefore, by forming at least one of the high-concentration p-type semiconductor region803or the p-type semiconductor region44in the entire planar region, electrons photoelectrically converted in the n-well41can be moved to the avalanche multiplication region47, and high PDE can be achieved.

<12. Eighth Pixel Structure of Pixel>

A ofFIG.26is a cross-sectional view illustrating an eighth pixel structure of the pixel10using the SPAD21, and B ofFIG.26is a plan view of the pixel10taken along line X-X′ in A ofFIG.26.

InFIG.26, the same reference numerals are given to portions common to the seventh pixel structure illustrated inFIG.16, and the description of the portions will be appropriately omitted.

The pixel10according to the eighth pixel structure illustrated inFIG.26is different from the seventh pixel structure illustrated inFIG.16in further including a reflection structure in the high-concentration p-type semiconductor region803formed on the substrate front surface side of the p-type semiconductor region44, and is common to the seventh pixel structure illustrated inFIG.16in other points.

For example, as illustrated inFIG.26, the reflection structure formed in the high-concentration p-type semiconductor region803is configured by arranging a plurality of pillars921having a predetermined depth, which do not reach the p-type semiconductor region44from the interface of the substrate front surface, in a grid shape at predetermined intervals. In the plan view of B ofFIG.26, the pillars921are regularly arranged, and illustration of a part of the pillars921is omitted. Note that the plurality of pillars921is not necessarily regularly arranged, and may be arranged at random intervals. The pillar921can be formed by a material different from the high-concentration p-type semiconductor region803, for example, the silicon oxide film.

According to the eighth pixel structure, a structure is formed in which two layers having different refractive indexes of the high-concentration p-type semiconductor region803and the pillars921formed by the silicon oxide film are mixed at the interface on the substrate front surface side, and the light incident on the n-well41from the on-chip lens816and trying to pass through to the substrate front surface side can be secondarily diffracted and confined in the pixel. Thus, the amount of incident light to be photoelectrically converted in the semiconductor substrate31can be further increased, and quantum efficiency (QE) can be improved.

<13. Ninth Pixel Structure of Pixel>

FIG.27is a cross-sectional view illustrating a ninth pixel structure of the pixel10using the SPAD21.FIG.27illustrates a cross-sectional view of two adjacent pixels, and a one-dot chain line indicates a pixel boundary as inFIG.16and the like.

Also inFIG.27, the same reference numerals are given to portions common to the seventh pixel structure illustrated inFIG.16, and the description of the portions will be appropriately omitted.

The pixel10according to the ninth pixel structure illustrated inFIG.27is different from the seventh pixel structure in that the pixel separation portion811formed at the pixel boundary portion in the seventh pixel structure illustrated inFIG.16is omitted, and is common to the seventh pixel structure illustrated inFIG.16in other points.

The pixel10illustrated inFIG.27includes the separation layer801on the outer periphery of the high-concentration n-type semiconductor region43forming the avalanche multiplication region47, so that the influence of the radiation light generated in the avalanche multiplication region47can be suppressed. Therefore, as in the ninth pixel structure, the pixel separation portion811at the pixel boundary portion may be omitted. Since the pixel separation portion811is omitted, absorption of the incident light by the metal DTI812constituting the pixel separation portion811can be eliminated, so that the PDE can be further improved.

<14. Tenth Pixel Structure of Pixel>

A ofFIG.28is a cross-sectional view illustrating a tenth pixel structure of the pixel10using the SPAD21, and B ofFIG.28is a plan view of the pixel10taken along line X-X′ in A ofFIG.28. Also inFIG.28, a one-dot chain line indicates a pixel boundary.

Also inFIG.28, the same reference numerals are given to portions common to the seventh pixel structure illustrated inFIG.16, and the description of the portions will be appropriately omitted.

A pixel10according to a tenth pixel structure illustrated inFIG.28has a structure in which the polarity of the pixel10according to the seventh pixel structure illustrated inFIG.16is inverted. In other words, the pixel10according to the seventh pixel structure illustrated inFIG.16is an example of a structure in which electrons are read out as signal charges (carriers), but the pixel10according to the tenth pixel structure illustrated inFIG.28is an example of a structure in which holes are read out as signal charges. In this case, the conductivity types of the semiconductor region connected to the contact electrode51as the cathode and the semiconductor region connected to the contact electrode52as the anode are opposite.

More specifically, a high-concentration p-type semiconductor region1043is formed in the contact electrode51as a cathode instead of the high-concentration n-type semiconductor region43, and a high-concentration n-type semiconductor region1046is formed in the contact electrode52as an anode instead of the high-concentration p-type semiconductor region46.

In a plan view of B ofFIG.28, a low-concentration p-type semiconductor region1802having an impurity concentration lower than that of the high-concentration p-type semiconductor region1043is formed on an outer periphery of the high-concentration p-type semiconductor region1043. The separation layer801is formed on an outer periphery of the low-concentration p-type semiconductor region1802. On a further outer periphery of the separation layer801, a high-concentration n-type semiconductor region1803is formed instead of the high-concentration p-type semiconductor region803.

As illustrated in A ofFIG.28, an n-type semiconductor region1044is formed with a predetermined thickness in the entire planar region below the formation region of the high-concentration p-type semiconductor region1043, the low-concentration p-type semiconductor region1802, the separation layer801, and the high-concentration n-type semiconductor region1803, and the avalanche multiplication region47is formed by a depletion layer formed in the junction region between the high-concentration p-type semiconductor region1043and the n-type semiconductor region1044formed therebelow.

Furthermore, the voltage applied from the contact electrode51as the cathode to the high-concentration p-type semiconductor region1043and the voltage applied from the contact electrode52as the anode to the high-concentration n-type semiconductor region1046are also opposite. That is, the power supply VSPAD is applied from the contact electrode51as the cathode to the high-concentration p-type semiconductor region1043, and the power supply voltage VE is applied from the contact electrode52as the anode to the high-concentration n-type semiconductor region1046.

Other configurations of the pixel10according to the tenth pixel structure inFIG.28are similar to those of the pixel10according to the seventh pixel structure illustrated inFIG.16, and thus the description thereof will be omitted.

The effect of the pixel10according to the tenth pixel structure inFIG.28is similar to the effect described in the seventh pixel structure illustrated inFIG.16.

As described above, in the description of the first pixel structure illustrated inFIG.3, it has been described that a signal charge (carrier) can be either an electron or a hole, but this is not limited to the first pixel structure, and either an electron or a hole can be the signal charge in any of the second to ninth pixel structures described above.

<15. Configuration Example of Stacked Structure>

The light receiving element in which the plurality of pixels10using the SPAD21is formed can be formed using one semiconductor substrate or can be formed by stacking a plurality of semiconductor substrates.

FIG.29is a cross-sectional view illustrating an example of a stacked structure in a case where a light receiving element is formed by stacking two semiconductor substrates.

The pixel10inFIG.29is formed by bonding a first substrate201and a second substrate202. The first substrate201includes the semiconductor substrate31formed by silicon or the like and a wiring layer212. On the other hand, the second substrate202includes a semiconductor substrate311formed by silicon or the like and a wiring layer312. A bonding surface between the first substrate201and the second substrate202is indicated by a one-dot chain line.

Hereinafter, the wiring layer212will be referred to as a sensor-side wiring layer212in order to be easily distinguished from the wiring layer312on the second substrate202side. The wiring layer312on the second substrate202side will be referred to as a logic-side wiring layer312. A surface on which the sensor-side wiring layer212is formed with respect to the semiconductor substrate31is a front surface, and in the drawing, a lower surface on which the sensor-side wiring layer212is not formed is a back surface of the semiconductor substrate31and is a light receiving surface on which incident light is incident. Since the structure of the semiconductor substrate31is similar to the first pixel structure illustrated inFIG.3, the description thereof will be omitted.

The sensor-side wiring layer212includes a contact electrode51, a contact electrode52, a metal pad331, a metal pad332, and an interlayer insulating film333. The metal pad331is electrically and physically connected to the metal pad351of the logic-side wiring layer312by metal bonding such as Cu—Cu. The metal pad332is electrically and physically connected to the metal pad352of the logic-side wiring layer312by metal bonding such as Cu—Cu.

In the drawing, a plurality of MOS transistors Tr (Tr1, Tr2, or the like) and a logic-side wiring layer312are formed on a front surface side of the semiconductor substrate311which is the lower side. The logic-side wiring layer312includes a metal pad351, a metal pad352, and an interlayer insulating film353.

The metal pad351is electrically and physically connected to the metal pad331of the sensor-side wiring layer212by metal bonding of Cu—Cu or the like. The metal pad352is electrically and physically connected to the metal pad332of the sensor-side wiring layer212by metal bonding of Cu—Cu or the like.

On the second substrate202, a plurality of MOS transistors Tr formed on the semiconductor substrate311and a plurality of layers of metal wiring (not illustrated) form, for example, a readout control circuit that controls signal readout of the pixel10, such as the constant current source22, the transistor23, and the inverter24(FIG.1), and a logic circuit corresponding to a pixel drive section511, an MUX513, a time measurement section514(FIG.31), and the like.

With such a wiring structure, for example, the power supply VSPAD supplied to the anode of the SPAD21of the pixel10is supplied to the high-concentration p-type semiconductor region46via the metal pad352of the logic-side wiring layer312, the metal pad332of the sensor-side wiring layer212, and the contact electrode52. Furthermore, the power supply voltage VE supplied to the cathode of the SPAD21of the pixel10is supplied to the high-concentration n-type semiconductor region43via the metal pad351of the logic-side wiring layer312, the metal pad331of the sensor-side wiring layer212, and the contact electrode51.

In the example ofFIG.29, an example in which the first pixel structure illustrated inFIG.3is employed to have a stacked structure has been described, but it goes without saying that other second to tenth pixel structures can similarly have a stacked structure.

<16. Pixel Circuit that Performs Active Quenching>

The circuit configuration of the pixel10illustrated inFIG.1is a configuration of a passive circuit that performs passive quenching, but a configuration of an active circuit that performs active quenching, active recharging, and holdoff can also be employed.

FIG.30illustrates a circuit configuration of the pixel10as an active circuit that performs active quenching, active recharging, and holdoff.

The pixel10inFIG.30includes an inverter401, a variable inverter402, a NOR circuit403, an inverter404, and a P-type MOS transistor405, in addition to the SPAD21, the constant current source22, the transistor23, and the inverter24, which are similar to those inFIG.1.

The detection signal PFout output from the inverter24is also input to the inverter401and the variable inverter402. The inverter401inverts and outputs the detection signal PFout, and the variable inverter402inverts and outputs the detection signal PFout after a predetermined time elapses.

The NOR circuit403executes a NOR operation of the inverter401and the variable inverter402, and outputs the execution result to the inverter404and the gate of the transistor23. The inverter404inverts the output of the NOR circuit403and outputs the inverted output to the gate of the P-type MOS transistor.

In the pixel10ofFIG.30, avalanche multiplication occurs, and after a predetermined time determined by the variable inverter402has elapsed since an output of the Hi detection signal PFout, a hold pulse (hold_pulse) output from the NOR circuit403becomes Hi. By the Hi hold pulse, the transistor23is turned on and connected to GND to perform active quenching, and the P-type MOS transistor405is turned on to maintain (hold off) the cathode voltage VS at 0 V (GND).

When the hold pulse of Hi is controlled to be Lo by a hold control circuit which is not illustrated after the hold pulse of Hi is held for a predetermined time, the transistor23and the P-type MOS transistor405are turned off, so that the cathode voltage VS returns to the original power supply voltage VE again, making it capable of detecting a next new photon (active recharging operation).

As in the case of the passive circuit ofFIG.1, the control of setting the pixel10as the active pixel or the inactive pixel is performed by the hold control circuit, which is not illustrated, controlling the hold pulse to turn on and off the transistor23.

The inverter401, the variable inverter402, the NOR circuit403, the inverter404, and the P-type MOS transistor405for performing active quenching and active recharging are a part of a readout control circuit that controls signal reading of the pixel10.

<17. Configuration Example of Light Receiving Element>

The pixel10according to the first to tenth pixel structures described above can be applied to, for example, the pixel of the light receiving element illustrated inFIG.31.

FIG.31is a block diagram of a light receiving element including the pixel10described above.

The light receiving element501inFIG.31includes a pixel drive section511, a pixel array512, a multiplexer (MUX)513, a time measurement section514, and an input-output section515.

The pixel array512has a configuration in which pixels521that detect incidence of photons and output the detection signal PFout indicating a detection result as a pixel signal are two-dimensionally arranged in a matrix in a row direction and a column direction. Here, the row direction refers to the arrangement direction of the pixels521in the pixel row, that is, the horizontal direction, and the column direction refers to the arrangement direction of the pixels521in the pixel column, that is, the vertical direction. InFIG.31, the pixel array512is illustrated in a pixel array configuration of 10 rows and 12 columns due to paper surface restriction, but the number of rows and the number of columns of the pixel array512are not limited thereto and are arbitrary.

The pixel drive line522is wired along the horizontal direction for each pixel row with respect to the matrix-like pixel array of the pixel array512. The pixel drive line522transmits a drive signal for driving the pixels521. The pixel drive section511drives each pixel521by supplying a predetermined drive signal to each pixel521via the pixel drive line522. Specifically, the pixel drive section511performs control such that a part of the pixels521among the plurality of pixels521two-dimensionally arranged in a matrix form are set as active pixels and the remaining pixels521are set as inactive pixels at a predetermined timing corresponding to a light emission timing signal supplied from the outside via the input-output section515. The active pixel is a pixel that detects incidence of photons, and the inactive pixel is a pixel that does not detect incidence of photons. As the configuration of the pixel521, any one of the first to tenth pixel structures of the pixel10described above can be employed.

Note that, inFIG.31, the pixel drive line522is illustrated as one wiring, but may include a plurality of wirings. One end of the pixel drive line522is connected to an output terminal corresponding to each pixel row of the pixel drive section511.

The MUX513selects an output from the active pixel according to switching between the active pixel and the inactive pixel in the pixel array512. Then, the MUX513outputs the pixel signal input from the selected active pixel to the time measurement section514.

On the basis of the pixel signal of the active pixel supplied from the MUX513and the light emission timing signal indicating the light emission timing of the light emitting source (a light source632inFIG.32), the time measurement section514generates a count value corresponding to the time from when the light emitting source emits light to when the active pixel receives the light. The light emission timing signal is supplied from the outside (a control section642of an imaging device622inFIG.32) via the input-output section515.

The input-output section515outputs the count value of the active pixel supplied from the time measurement section514to the outside (a signal processing circuit653inFIG.32) as a pixel signal. Furthermore, the input-output section515supplies the light emission timing signal supplied from the outside to the pixel drive section511and the time measurement section514.

<18. Configuration Example of Distance Measuring System>

FIG.32is a block diagram illustrating a configuration example of an embodiment of a distance measuring system in which the light receiving element501ofFIG.31is incorporated.

The distance measuring system611is, for example, a system that captures a distance image using the ToF method. Here, the distance image is an image formed by a distance pixel signal based on a detected distance by detecting a distance in a depth direction from the distance measuring system611to the subject for each pixel.

The distance measuring system611includes a lighting device621and an imaging device622.

The lighting device621includes a lighting control section631and a light source632.

The lighting control section631controls a pattern in which the light source632emits light under the control of the control section642of the imaging device622. Specifically, the lighting control section631controls a pattern in which the light source632emits light according to an irradiation code included in the irradiation signal supplied from the control section642. For example, the irradiation code has two values of 1 (High) and0(Low), and the lighting control section631turns on the light source632when the value of the irradiation code is 1 and turns off the light source632when the value of the irradiation code is 0.

The light source632emits light in a predetermined wavelength region under the control of the lighting control section631. The light source632includes, for example, an infrared laser diode. Note that the type of the light source632and the wavelength range of the irradiation light can be arbitrarily set according to the application of the distance measuring system611and the like.

The imaging device622is a device that receives reflected light obtained by reflecting light (irradiation light) emitted from the lighting device621by the subject612, the subject613, and the like. The imaging device622includes an imaging section641, a control section642, a display section643, and a storage section644.

The imaging section641includes a lens651, a light receiving element652, and a signal processing circuit653.

The lens651forms an image of the incident light on the light receiving surface of the light receiving element652. Note that the configuration of the lens651is arbitrary, and for example, the lens651can be configured by a plurality of lens groups.

The light receiving element652includes, for example, a sensor using a SPAD for each pixel. Under the control of the control section642, the light receiving element652receives reflected light from the subject612, the subject613, and the like, and supplies a pixel signal obtained as a result to the signal processing circuit653. This pixel signal represents a digital count value obtained by counting a time from when the lighting device621emits the irradiation light to when the light receiving element652receives the irradiation light. The light emission timing signal indicating the timing at which the light source632emits light is also supplied from the control section642to the light receiving element652. As a configuration of the light receiving element652, the light receiving element501inFIG.31including the pixel10described above is employed.

The signal processing circuit653processes the pixel signal supplied from the light receiving element652under the control of the control section642. For example, the signal processing circuit653detects the distance to the subject for each pixel on the basis of the pixel signal supplied from the light receiving element652, and generates a distance image indicating the distance to the subject for each pixel. Specifically, the signal processing circuit653acquires a time (count value) from when the light source632emits light to when each pixel of the light receiving element652receives the light a plurality of times (for example, several thousands to several tens of thousands of times) for each pixel. The signal processing circuit653creates a histogram corresponding to the acquired time. Then, by detecting a peak of the histogram, the signal processing circuit653determines the time until the light emitted from the light source632is reflected by the subject612or the subject613and returns. Moreover, the signal processing circuit653performs an arithmetic operation to obtain the distance to the object on the basis of the determined time and light speed. The signal processing circuit653supplies the generated distance image to the control section642.

The control section642includes, for example, a control circuit such as a field programmable gate array (FPGA) or a digital signal processor (DSP), a processor, and the like. The control section642controls the lighting control section631and the light receiving element652. Specifically, the control section642supplies an irradiation signal to the lighting control section631and supplies a light emission timing signal to the light receiving element652. The light source632emits irradiation light according to the irradiation signal. The light emission timing signal may be an irradiation signal supplied to the lighting control section631. Furthermore, the control section642supplies the distance image acquired from the imaging section641to the display section643and causes the display section643to display the distance image. Moreover, the control section642stores the distance image acquired from the imaging section641in the storage section644. Furthermore, the control section642outputs the distance image acquired from the imaging section641to the outside.

The display section643includes, for example, a panel type display device such as a liquid crystal display device or an organic electro luminescence (EL) display device.

The storage section644can include an arbitrary storage device, a storage medium, or the like, and stores a distance image or the like.

By employing the above structure of the pixel10in the light receiving element501and the distance measuring system611described above, it is possible to generate and output a distance image achieving the high PDE (photon detection efficiency) while preventing edge break.

<19. Application Example to Electronic Device>

The above-described distance measuring system611can be mounted, for example, on electronic devices such as a smartphone, a tablet terminal, a mobile phone, a personal computer, a game machine, a television receiver, a wearable terminal, a digital still camera, and a digital video camera.

FIG.33is a block diagram illustrating a configuration example of a smartphone as an electronic device equipped with the distance measuring system611.

As illustrated inFIG.33, a smartphone701is configured by connecting a distance measuring module702, an imaging device703, a display704, a speaker705, a microphone706, a communication module707, a sensor unit708, a touch panel709, and a control unit710via a bus711. Furthermore, the control unit710has functions as an application processing section721and an operation system processing section722by the CPU executing a program.

The distance measuring system611inFIG.32is applied to the distance measuring module702. For example, the distance measuring module702is arranged in front of the smartphone701, and performs distance measurement for the user of the smartphone701, so that the depth value of the surface shape of the face, hand, finger, or the like of the user can be output as a distance measurement result.

The imaging device703is arranged in front of the smartphone701and performs imaging with the user of the smartphone701being a subject, to thereby acquire an image in which the user is captured. Note that, although not illustrated, the imaging device703may also be arranged on the back surface of the smartphone701.

The display704displays an operation screen for performing processing by the application processing section721and the operation system processing section722, an image captured by the imaging device703, and the like. The speaker705and the microphone706output the voice of the other party and collect the voice of the user, for example, when making a call using the smartphone701.

The communication module707performs communication via a communication network. The sensor unit708senses speed, acceleration, proximity, and the like, and the touch panel709acquires a touch operation by the user on an operation screen displayed on the display704.

The application processing section721performs processing for providing various services by the smartphone701. For example, the application processing section721can perform processing of creating a face by computer graphics that virtually reproduces the expression of the user on the basis of the depth map supplied from the distance measuring module702, and displaying the face on the display704. Furthermore, the application processing section721can perform processing of creating three-dimensional shape data of an arbitrary three-dimensional object on the basis of the depth map supplied from the distance measuring module702, for example.

The operation system processing section722performs processing for achieving basic functions and operations of the smartphone701. For example, the operation system processing section722can perform processing of authenticating the user's face and unlocking the smartphone701on the basis of the depth map supplied from the distance measuring module702. Furthermore, the operation system processing section722can perform, for example, processing of recognizing a gesture of the user on the basis of the depth map supplied from the distance measuring module702and processing of inputting various operations according to the gesture.

In the smartphone701configured as described above, for example, the depth map can be generated with high accuracy and high speed by applying the above-described distance measuring system1. Thus, the smartphone701can more accurately detect distance measurement information.

<20. Application Example to Mobile Object>

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

FIG.34is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

A vehicle control system12000includes a plurality of electronic control units connected via a communication network12001. In the example illustrated inFIG.34, the vehicle control system12000includes a driving system control unit12010, a body system control unit12020, an outside-vehicle information detecting unit12030, an in-vehicle information detecting unit12040, and an integrated control unit12050. Furthermore, as a functional configuration of the integrated control unit12050, a microcomputer12051, a sound/image output section12052, and an onboard network interface (I/F)12053are illustrated.

The body system control unit12020controls operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit12020functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit12020. The body system control unit12020receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The microcomputer12051can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040, and output a control command to the driving system control unit12010. For example, the microcomputer12051can perform cooperative control for the purpose of achieving functions of the advanced driver assistance system (ADAS) including vehicle collision avoidance or impact mitigation, following traveling based on an inter-vehicle distance, vehicle speed maintaining traveling, vehicle collision warning, or vehicle lane departure warning, and the like.

In addition, the microcomputer12051can perform cooperative control intended for automated driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040.

The sound/image output section12052transmits an output signal of at least one of a sound or an image to an output device capable of visually or auditorily notifying an occupant of the vehicle or the outside of the vehicle of information. In the example ofFIG.34, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display or a head-up display.

FIG.35is a diagram illustrating an example of the installation position of the imaging section12031.

The imaging sections12101,12102,12103,12104, and12105are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the cabin of the vehicle12100. The imaging section12101provided to the front nose and the imaging section12105provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided in the side mirrors mainly obtain images of sides of the vehicle12100. The imaging section12104provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The forward image obtained by the imaging sections12101and12105are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

Incidentally,FIG.35illustrates an example of photographing ranges of the imaging sections12101to12104. An imaging range12111represents the imaging range of the imaging section12101provided on the front nose, imaging ranges12112and12113represent the imaging ranges of the imaging sections12102and12103provided on the side mirrors, respectively, and an imaging range12114represents the imaging range of the imaging section12104provided in the rear bumper or the back door. For example, by overlaying image data captured by the imaging sections12101to12104, an overhead image of the vehicle12100viewed from above can be obtained.

For example, the microcomputer12051can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects, and the like on the basis of the distance information obtained from the imaging sections12101to12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer12051identifies obstacles around the vehicle12100as obstacles that the driver of the vehicle12100can recognize visually and obstacles that are difficult for the driver of the vehicle12100to recognize visually. Then, the microcomputer12051determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer12051can output a warning to the driver via the audio speaker12061and the display section12062, or perform forced deceleration or avoidance steering via the driving system control unit12010, to thereby perform assistance in driving for collision avoidance.

The example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the outside-vehicle information detecting unit12030and the in-vehicle information detecting unit12040among the above-described configurations. Specifically, by using distance measurement by the distance measuring system1as the outside-vehicle information detecting unit12030and the in-vehicle information detecting unit12040, it is possible to perform processing of recognizing a gesture of the driver, execute various operations (for example, an audio system, a navigation system, and an air conditioning system) according to the gesture, and more accurately detect the state of the driver. In addition, the unevenness of the road surface can be recognized using the distance measurement by the distance measuring system1and reflected in the control of the suspension.

The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

The plurality of present technologies which has been described in the present description can be each implemented independently as a single unit as long as no contradiction occurs. Of course, any plurality of the present technologies can also be used and implemented in combination. Furthermore, part or all of any of the above-described present technologies can be implemented by using together with another technology that is not described above.

Further, for example, a configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). Conversely, configurations described above as a plurality of devices (or processing units) may be combined and configured as one device (or processing unit). Furthermore, a configuration other than those described above may of course be added to the configuration of each device (or each processing unit). Moreover, if the configuration and operation of the entire system are substantially the same, a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or another processing unit).

Moreover, in the present description, a system means a set of a plurality of components (devices, modules (parts), and the like), and it does not matter whether or not all components are in the same housing. Therefore, both of a plurality of devices housed in separate housings and connected via a network and a single device in which a plurality of modules is housed in one housing are systems.

Note that the effects described in the present description are merely examples and are not limited, and effects other than those described in the present description may be provided.

Note that the present technology can have the following configurations.

A light receiving element includinga pixel in which a multiplication region is formed in a region where a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first semiconductor region are joined, and a planar region of the second semiconductor region formed at a position closer to a light receiving surface than the first semiconductor region is formed to be larger.
(2)

The light receiving element according to (1) above, in whichthe pixel further includes a third semiconductor region of the second conductivity type on a surface opposite to the light receiving surface and a side surface near a boundary portion of the pixel.
(3)

The light receiving element according to (2) above, in whichthe second semiconductor region is formed up to the third semiconductor region formed on the side surface near the boundary portion of the pixel.
(4)

The light receiving element according to (2) or (3) above, further includinga fourth semiconductor region of the first conductivity type provided between the second semiconductor region and the third semiconductor region formed on the side surface near the boundary portion of the pixel.
(5)

The light receiving element according to any one of (2) to (4) above, in whichthe pixel further includes a fixed charge film having a fixed charge on a surface outside the third semiconductor region.
(6)

The light receiving element according to any one of (2) to (5) above, in whichthe pixel further includes a pixel separation portion that separates pixels from each other at the pixel boundary portion outside the third semiconductor region.
(7)

The light receiving element according to (6) above, in whicha predetermined voltage is applied to the pixel separation portion.
(8)

The light receiving element according to any one of (2) to (7) above, further includinga separation layer electrically separating a first contact portion of the first semiconductor region connected to one electrode of an anode or a cathode and a second contact portion of the third semiconductor region connected to the other electrode between the first contact portion and the second contact portion.
(9)

The light receiving element according to (8) above, further includinga fifth semiconductor region of the second conductivity type provided between the separation layer and the third semiconductor region.
(10)

The light receiving element according to (8) or (9) above, further includinga sixth semiconductor region having a same conductivity type as the first semiconductor region and a lower impurity concentration than the first semiconductor region between the first semiconductor region and the separation layer.
(11)

The light receiving element according to (9) above, further includinga reflection structure formed by a material different from a material of the fifth semiconductor region in a region of the fifth semiconductor region.
(12)

The light receiving element according to any one of (2) to (8) above, in whicha first contact portion of the first semiconductor region connected to one electrode of an anode or a cathode and a second contact portion of the third semiconductor region connected to the other electrode are arranged at different depth positions.
(13)

The light receiving element according to any one of (1) to (8) above, further includinga fourth semiconductor region of the first conductivity type and a fifth semiconductor region having a same conductivity type as the fourth semiconductor region and a lower impurity concentration than the fourth semiconductor region at a position closer to the light receiving surface than the second semiconductor region.
(14)

The light receiving element according to any one of (1) to (8) above, further includinga fourth semiconductor region having a same conductivity type as the second semiconductor region and a lower impurity concentration than the second semiconductor region, and a fifth semiconductor region having a different conductivity type from the fourth semiconductor region at a position closer to the light receiving surface than the second semiconductor region.
(15)

The light receiving element according to any one of (1) to (14) above, in whicha planar shape of the first semiconductor region is a circular shape.
(16)

The light receiving element according to any one of (1) to (15) above, in whicha diameter of the first semiconductor region is 2 μm or less.
(17)

The light receiving element according to any one of (1) to (16) above, in whicha relative distance in a depth direction of the first semiconductor region and the second semiconductor region is 1000 nm or less.
(18)

The light receiving element according to any one of (1) to (17) above, in whichan impurity concentration of each of the first semiconductor region and the second semiconductor region is 1E+16/cm3or more.
(19)

The light receiving element according to any one of (1) to (18) above, in whichthe light receiving element has a stacked structure in which a first semiconductor substrate and a second semiconductor substrate are stacked,the first semiconductor region and the second semiconductor region are formed in the first semiconductor substrate, anda readout control circuit that controls signal reading of the pixel is formed on the second semiconductor substrate.
(20)

A distance measuring system including:a lighting device that emits irradiation light; anda light receiving element that receives reflected light obtained by reflecting the irradiation light by a subject, in whichthe light receiving element includesa pixel in which a multiplication region is formed in a region where a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first semiconductor region are joined, a planar region of the second semiconductor region is formed to be larger, and a planar region of the second semiconductor region formed at a position closer to a light receiving surface than the first semiconductor region is formed to be larger.

REFERENCE SIGNS LIST