Solid-state imaging element and electronic

The present disclosure relates to a solid-state imaging element and electronic equipment that make it possible to sufficiently secure a time width of a pulse signal. In an AD converter for each unit pixel, a pulse generation circuit feeds back a delay signal obtained by delaying an output signal of the comparator to the comparator and arithmetically operates the output signal and the delay signal to generate a pulse signal. A latch circuit latches the pulse signal generated by the pulse generation circuit. The present disclosure can be applied to a solid-state imaging element of a stacked type and a back side illumination type.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase of International Patent Application No. PCT/JP2017/047265 filed on Dec. 28, 2017, which claims priority benefit of Japanese Patent Application No. JP 2017-004081 filed in the Japan Patent Office on Jan. 13, 2017. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a solid-state imaging element and electronic equipment, and particularly relates to a solid-state imaging element and electronic equipment that make it possible to sufficiently secure a time width of a pulse signal.

BACKGROUND ART

A system has been proposed in which, in order to allow an imaging element, in which pixels are disposed two-dimensionally, to deal with speeding up of image signal outputting, an analog to digital conversion device is disposed in each pixel such that analog to digital conversion is performed simultaneously by all pixels to speed up analog to digital conversion. In this system, a comparison section compares an analog image signal and a reference signal with each other. Then, when the voltage of the reference signal transits from a state in which it is lower than the voltage of the analog image signal to a state in which it is higher than the voltage of the analog image signal or from a state in which it is higher the voltage of the analog image signal to a state in which it is lower the voltage of the analog image signal, this voltage change is detected and outputted as a comparison result. Further, a digital code corresponding to the voltage of the reference signal is inputted to a latch circuit, and the inputted digital code is retained by the latch circuit on the basis of the detection result by the comparison circuit. Thereafter, the digital code retained in the latch circuit is outputted as the result of the analog to digital conversion.

The imaging device in PTL 1 is configured such that it has a function for feeding back an output signal of the comparator into the comparator in order to accelerate the signal transition in the comparator. Then, an effective Window is provided using the signal, and the start and the end of a data validity period of the latch circuit is adjusted.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

However, in order to secure such a pulse width sufficient to allow a signal from a repeater to be acquired, it is necessary to increase a circuit area.

The present disclosure has been made in view of such a situation as described above and makes it possible to sufficiently secure a time width of a pulse signal.

Solution to Problem

A solid-state imaging element according to one aspect of the present technology includes a pixel array section in which unit pixels each having a photoelectric conversion section are disposed, and an AD converter for each of the unit pixels, in which the AD converter includes a pulse generation circuit that feeds back a delay signal obtained by delaying an output signal of a comparator to the comparator and performs arithmetic operation of the output signal and the delay signal to generate a pulse signal, and a latch circuit that latches a data code using the pulse signal generated by the pulse generation circuit.

The pulse generation circuit may include a delay element that delays the output signal of the comparator to generate the delay signal, and an arithmetic element that arithmetically operates the output signal and the delay signal to generate the pulse signal.

The arithmetic element includes a NOR circuit.

The arithmetic element includes a NAND circuit.

In the pulse generation circuit, a logical threshold value of a gate element is adjusted.

In the pulse generation circuit, the logical threshold value of the gate element is adjusted by changing an element number of transistors.

In the pulse generation circuit, the logical threshold value of the gate element is adjusted by setting the threshold value of each of the elements of transistors to a high threshold value and a low threshold value.

The pulse generation circuit may further include a selection circuit that selects a path used when a delay signal obtained by delaying the output signal of the comparator is to be fed back to the comparator and the output signal and the delay signal are arithmetically operated to generate a pulse signal and another path used when the output signal of the comparator is to be used as it is.

Electronic equipment according to the one aspect of the present technology includes: a solid-state imaging element including a pixel array section in which unit pixels each having a photoelectric conversion section are disposed, and an AD converter for each of the unit pixels, in which the AD converter includes a pulse generation circuit that feeds back a delay signal obtained by delaying an output signal of a comparator to the comparator and performs arithmetic operation of the output signal and the delay signal to generate a pulse signal, and a latch circuit that latches a data code using the pulse signal generated by the pulse generation circuit; a signal processing circuit that processes an output signal outputted from the solid-state imaging element; and an optical system that enters incident light into the solid-state imaging element.

In the one aspect of the present technology, a delay signal formed by delaying an output signal of the comparator by the AD converter of each of the unit pixels, which are disposed in the pixel array section and each include the photoelectric conversion section, is fed back to the comparator, and the output signal and the delay signal are arithmetically operated to generate a pulse signal. Then, a data code is latched using the generated pulse signal.

Advantageous Effects of Invention

With the present technology, a time width of a pulse signal can be secured sufficiently.

It is to be noted that the advantageous effects described in the present specification are merely examples, and the advantageous effects of the present technology are not restricted to the advantageous effects described in the present specification and there may be additional advantageous effects.

DESCRIPTION OF EMBODIMENT

In the following, a mode for carrying out the present disclosure (hereinafter referred to as an embodiment) is described. It is to be noted that the description is given in the following order.

0. Description of Device

2. Example of Use of Image Sensor

3. Example of Electronic Equipment

4. Application Example to In-Vivo Information Acquisition System

5. Application Example to Endoscopic Surgery System

6. Application Example to Moving Body

0. Description of Device

<Schematic Configuration Example of Solid-State Imaging Device>

FIG. 1depicts a schematic configuration example of one example of a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging element applied to embodiments of the present technology.

As depicted inFIG. 1, a solid-state imaging element (element chip)1includes a pixel region (so-called imaging region)3in which a plurality of pixels2each including a photoelectric conversion element is arrayed regularly and two-dimensionally on a semiconductor substrate11(for example, a silicon substrate), and a peripheral circuit region.

Each pixel2includes a photoelectric conversion element (for example, a PD (Photo Diode)) and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can include, for example, three transistors of a transfer transistor, a reset transistor, and an amplification transistor. Also, the plurality of pixel transistors can include four transistors, further adding a selection transistor to the three transistors above.

Also it is possible for the pixels2to have a shared pixel structure. The shared pixel structure includes a plurality of photodiodes, a plurality of transfer transistors, a single shared floating diffusion, and other pixel transistors shared one by one. The photodiodes are photoelectric conversion elements.

The peripheral circuit region includes a vertical driving circuit4, a column signal processing circuit5, a horizontal driving circuit6, an outputting circuit7, and a control circuit8.

The control circuit8receives an input clock and data that instructs an operation mode and so forth and outputs data of internal information and so forth of the solid-state imaging element1. In particular, the control circuit8generates a clock signal that becomes a reference to operation of the vertical driving circuit4, the column signal processing circuit5, and the horizontal driving circuit6, and a control signal on the basis of a vertical synchronizing signal, a horizontal synchronizing signal and a master clock. Then, the control circuit8inputs the signals to the vertical driving circuit4, the column signal processing circuit5, and the horizontal driving circuit6.

The vertical driving circuit4is configured, for example, from a shift register, and selects a pixel driving wiring line and supplies a pulse for driving a pixel2to the selected pixel driving line to drive pixels2in units of rows. In particular, the vertical driving circuit4selectively scans the pixels2of the pixel array3in units of rows successively in a vertical direction and supplies a pixel signal based on a signal charge generated in response to a received light amount, for example, at the photoelectric conversion element of each of the pixels2through a vertical signal line9to the column signal processing circuit5.

The column signal processing circuit5is disposed, for example, for each column of the pixels2and performs signal processing of signals outputted from the pixels2for one row such as noise removal for each pixel column. In particular, the column signal processing circuit5performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise unique to the pixels2, signal amplification, A/D (Analog/Digital) conversion, and so forth. A horizontal selection switch (not depicted) is provided in the output stage of the column signal processing circuit5such that it is connected between the column signal processing circuit5and a horizontal signal line10. It is to be noted that part of the signal processing described above may be processed for each pixel.

The horizontal driving circuit6is configured, for example, from a shift register, and sequentially outputs a horizontal scanning pulse to select each of the column signal processing circuits5, and then, a pixel signal is outputted from each of the column signal processing circuits5to the horizontal signal line10.

The outputting circuit7performs signal processing for each of signals successively supplied from the column signal processing circuits5through the horizontal signal line10and outputs a resulting signal. For example, the outputting circuit7sometimes performs only buffering or sometimes performs black level adjustment, column dispersion correction, various digital signal processes and so forth.

Input/output terminals12are provided to transfer a signal to and from the outside.

FIG. 2is a block diagram depicting a configuration example of part of a solid-state imaging element to which the present technology is applied. The present technology is applied to a solid-state imaging element not of the example that includes an AD conversion device for each column as depicted inFIG. 1but of an example in which an AD (Analog-Digital) conversion device61is provided for each pixel2.

In the example ofFIG. 2, a pixel2and an AD conversion device61that receives a pixel signal from the pixel2and a reference signal from a control circuit8as inputs thereto and converts them into digital signals as well as a repeater31, a RAM CDS32and a Gray Code33that are disposed for each predetermined pixel column in the subsequent stage to the AD conversion device61are depicted. It is to be noted that the AD conversion device61is configured particularly from an AD converter51and a latch circuit26.

The AD conversion device61includes a comparison circuit22, an auto zero (AZ)23, a PFB (Possitive Feed Back)24, a pulse generation circuit25, and a latch circuit26. The comparison circuit22receives a pixel signal and a reference signal as inputs thereto and outputs a result of comparison of them to the PFB24. The auto zero23has a function for resetting the comparison circuit22. The PFB24is a speeding up circuit, and receives an inversion signal from the comparison circuit22and a feedback (Feed Back) signal from the pulse generation circuit25as inputs thereto and outputs a comparison signal to the pulse generation circuit25of the subsequent stage.

The pulse generation circuit25includes a delay element41, an arithmetic element42, and an inversion element43. The pulse generation circuit25performs delay arithmetic operation for providing an effective Window for acquiring data and receives the inversion signal and a delay signal obtained by delaying the inversion signal as inputs thereto to generate a pulse signal (VCO PULSE). Then, the pulse generation circuit25outputs the generated pulse signal to the latch circuit26, and inverts the delay signal and feeds back the inverted delay signal as a feedback signal to the PFB24. The latch circuit26stores a data code using the pulse signal for a predetermined period of time and outputs the stored data code to the repeater31.

In particular, in PTL 1, the AD conversion device61is configured such that a comparison signal from a comparator40is fed back as a feedback signal to the comparison circuit22as depicted inFIG. 3. It is to be noted that the comparator40includes the comparison circuit22and the PFB24. Meanwhile, although the AD conversion device61of the example ofFIG. 4it includes the delay element41and the arithmetic element42, even if the delay element41is provided, a comparison signal from the comparator40is fed back to the comparator40in front of the delay element41.

On the other hand, in the AD conversion device61to which the present technology is applied, a delay signal after delay arithmetic operation is completed through the delay element41is used as a feedback signal that is fed back to the comparator40.

Consequently, a feedback function for accelerating inversion transition of an output of the comparator40and a pulse generation function sufficient to acquire a signal from the repeater31using a delay signal are both achieved.

FIG. 6is a circuit diagram depicting a configuration example of a pulse generation circuit.

The pulse generation circuit25ofFIG. 6receives an inverted output (VCO) of the comparison circuit22(comparator40) as an input signal thereto and generates a delay signal using the delay element41that is an inverter. Further, the pulse generation circuit25receives the delay signal and the inverted output of the comparator40to an arithmetic element42that is a NOR circuit as inputs thereto and generates a pulse signal (VCO PULSE). Then, as a feedback signal (PFB) for accelerating signal transition of the second stage of the comparison circuit22, a delay signal inverted by the inversion element43that is an inverter is used. In particular, in the example ofFIG. 6, the delay element41and the inversion element43each include an inverter, and the arithmetic element42includes a NOR circuit.

FIG. 7is a circuit diagram depicting a configuration example of part of a solid-state imaging element to which the present technology is applied. It is to be noted that, in the case of the example ofFIG. 7, an example of a pixel2that includes one PD for one FD is illustrated.

In the example ofFIG. 7, as part of the solid-state imaging element1, a pixel2including FD, PD, TX and OFG, a comparison circuit22including a differential pair of nMOS and pMOS, an AZ23, a PFB24including 2ND and a NOR circuit, and inverters71and72interposed between the PFB24and a latch circuit26.

In this circuit configuration, nMOS of the differential pair of the comparison circuit22(in the circuit ofFIG. 7, an input differential pair) is an upper chip81, and elements following nMOS are a lower chip. The upper and lower chips are connected to each other at totaling two places including each one node of the differential pair of the comparison circuit22.

It is to be noted that the connection places of the upper and lower chips are not limited to those of the circuit ofFIG. 7but are determined from various factors such as area restriction or circuit characteristics.

FIG. 8is a circuit diagram depicting a different configuration example of part of the solid-state imaging element to which the present technology is applied. It is to be noted that, although the circuit configuration ofFIG. 8is different from that ofFIG. 7in that it has a pixel sharing configuration including four PDs for one FD, the configuration of the other part ofFIG. 8is common to the circuit configuration ofFIG. 7. In other words, the present technology can be applied also to a pixel sharing configuration.

It is to be noted that the circuit configuration is not limited to any of the circuits depicted inFIGS. 7 and 8but can be applied to a pixel AD type solid-state imaging element of any other configuration. For example, in a solid-state imaging element of the pixel AD type of a different configuration, the comparison circuit22including pMOS of a differential pair is adopted and, in addition, an FD is made not a component of the comparison circuit22but is connected through a source follower circuit. In this case, connection between the upper and lower chips is performed only at one place of the comparator and the input node of the terminal.

FIG. 9is a circuit diagram depicting a different configuration example of the pulse generation circuit ofFIG. 6.

In the pulse generation circuit25ofFIG. 9, the element number of transistors configuring the pulse generation circuit25ofFIG. 6is changed to adjust the logical threshold value of the transistors. In particular, the pulse generation circuit25ofFIG. 9receives an inverted output (VCO) of the comparison circuit22as an input thereto and generates a delay signal using the delay element41that is an inverter having low logic.

Further, in the pulse generation circuit25, the delay signal and the inverted output of the comparison circuit22are inputted to the arithmetic element42that is a NOR circuit having a high logical threshold value to generate a pulse signal (VCO PULSE). Then, as the feedback signal (PFB) for accelerating signal transition in the second stage of the comparison circuit22, a delay signal inverted by the inversion element43that is an inverter is used.

FIG. 10is a circuit diagram depicting a further configuration example of the pulse generation circuit ofFIG. 6.

In the pulse generation circuit25ofFIG. 10, the elements of the transistors configuring the pulse generation circuit25ofFIG. 6are changed to those having different threshold values (HVT: High Vth Tr. and LVT: Low Vth Tr.) to adjust the logical threshold value of each of the transistors. In particular, the pulse generation circuit25ofFIG. 10receives an inverted output (VCO) of the comparison circuit22as an input thereto and generates a delay signal using the delay element41that is an inverter having low logic.

Further, the pulse generation circuit25inputs the delay signal and the inverted output of the comparison circuit22to the arithmetic element42that is a NOR circuit having a high logical threshold value and generates a pulse signal (VCO PULSE). Then, as the feedback signal (PFB) for accelerating signal transition in the second stage of the comparison circuit22, a delay signal inverted by the inversion element43that is an inverter is used.

FIG. 11is a circuit diagram depicting a configuration example of the pulse generation circuit ofFIG. 6in the case where a NAND circuit is used as the arithmetic element.

The pulse generation circuit25ofFIG. 11uses an arithmetic element42that is a NAND circuit and generates a pulse signal (VCO XPULSE) of an opposite phase to that of the pulse generation circuit25ofFIG. 6. In particular, the pulse generation circuit25ofFIG. 11receives the inverted output (VCO) of the comparison circuit22as an input signal thereto and generates a delay signal using a delay element41-1and another delay element41-2that are inverters having low logic.

Further, in the pulse generation circuit25, the delay signal and a signal obtained by inverting the inverted output of the comparison circuit22by the inversion element43are inputted to the arithmetic element42that is a NAND circuit, so that a pulse signal (VCO PULSE) is generated. Then, as the feedback signal (PFB) for accelerating signal transition in the second stage of the comparison circuit22, a delay signal delayed by the delay element41-1and the delay element41-2is used. In particular, in the example ofFIG. 11, the delay elements41-1and41-2and the inversion element43includes an inverter, and the arithmetic element42includes a NAND circuit. It is to be noted that it is necessary for the logical threshold value of the inversion element43to become higher than that of the delay element41-1. This provides an effect that a time width of the pulse signal is further increased. It is to be noted that, at this time, the delay element41-2preferably has a high logical threshold value.

FIG. 12is a circuit diagram depicting a configuration example of the pulse generation circuit ofFIG. 9in the case where a NAND circuit is used as the arithmetic element.

In particular, in the pulse generation circuit25ofFIG. 12, the element number of transistors configuring the pulse generation circuit25ofFIG. 11is changed to adjust the logical threshold value of the transistors. In particular, the pulse generation circuit25ofFIG. 12receives the inverted output (VCO) of the comparison circuit22as an input thereto and generates a delay signal using the delay element41-1that is an inverter having a low logical threshold value and the delay element41-2that is an inverter having a high logical threshold value.

Further, the delay signal and a signal obtained by inverting the inverted output of the comparison circuit22by the inversion element43are inputted to the arithmetic element42that is a NAND circuit, so that a pulse signal (VCO PULSE) is generated. Then, as the feedback signal (PFB) for accelerating signal transition in the second stage of the comparison circuit22, a delay signal delayed by the delay element41-1and the delay element41-2is used.

FIG. 13is a circuit diagram depicting a configuration example of the pulse generation circuit ofFIG. 10in the case where a NAND circuit is used as the arithmetic element.

In particular, in the pulse generation circuit25ofFIG. 13, the elements of transistors configuring the pulse generation circuit25ofFIG. 13are changed to those of different threshold values (HVT: High Vth Tr. and LVT: Low Vth Tr.) of the pulse generation circuit25ofFIG. 11to adjust the logical threshold value of the transistors. In particular, the pulse generation circuit25ofFIG. 13receives the inverted output (VCO) of the comparison circuit22as an input signal thereto and generates a delay signal using the delay element41-1that is an inverter having a low logical threshold value and the delay element41-2that is an inverter having a high logical threshold value.

Further, in the pulse generation circuit25, the delay signal and a signal obtained by inverting the inverted output of the comparison circuit22by the inversion element43are inputted to the arithmetic element42that is a NAND circuit, so that a pulse signal (VCO PULSE) is generated. Then, as the feedback signal (PFB) for accelerating signal transition in the second stage of the comparison circuit22, a delay signal delayed by the delay element41-1and the delay element41-2is used.

FIG. 14is a circuit diagram depicting a configuration example of the pulse generation circuit ofFIG. 6in the case where a selector circuit is inserted.

In the pulse generation circuit25ofFIG. 14, a selector circuit85is inserted in the following stage of the arithmetic element42to make it possible to use a SEL signal to select a case in which the data-through period of the latch circuit26is controlled and in another case in which an output of the comparison circuit22is used directly.

By such a configuration as just described, it is possible to deal with a case in which the time width of a pulse signal cannot be secured.

FIG. 15is a block diagram depicting a configuration example of an AD conversion device to which the present technology is applied.

The CIS of the pixel AD method has such premises that the area restriction is severe, that an AD conversion device is disposed for each pixel, and that a circuit of a small area is preferable.

In the AD conversion device61ofFIG. 15, for the object of implementing a small area circuit, a PFB24that is a speeding up circuit is adopted in the comparator40in order to accelerate signal transition in the comparison circuit22(comparator40). The PFB24requires a feedback signal. Although a comparison signal has been used as the feedback signal in the past, in the present technology, a delay signal is used as the feedback signal. By this, the acceleration timing of signal transition is delayed. Accordingly, a period within which the signal transition is comparatively gentle is provided. In the pulse generation circuit25for controlling the data-through period of the latch circuit26, by the provision of the delay element41within this period, a delay signal is generated at the high and low levels of the logical threshold value. Then, a pulse signal is generated through the arithmetic element42from the delay signal and the comparison signal. Effects expected from this are such as described below.

1. The time width of a pulse signal can be secured sufficiently.

2. The pulse generation circuit can be formed with a small area.

3. Reduction in power consumption can be anticipated by data-through period control.

FIG. 16is a view depicting a configuration example of a solid-state imaging element of the pixel AD type.

In the solid-state imaging element1ofFIG. 16, a pixel region3is mounted on an upper chip101, and an AD conversion device61and a logic circuit111are mounted on a lower chip102, and the upper chip101and the lower chip102are stacked using a Cu—Cu joining technology or the like. Since one AD conversion device61corresponds to one pixel, a contact between the upper and lower chips is provided for each pixel. It is to be noted that the number of stacked layers is not limited to two layers and may be any number as long as it is equal to or greater than 2.

2. Example of Use of Image Sensor

FIG. 17is a view depicting an example of use in which the solid-state imaging element described above is used.

The solid-state imaging element (image sensor) described above can be used in various cases in which light such as visible light, infrared light, ultraviolet light, or an X ray is sensed, for example, in the following manner.An apparatus for imaging an image to be provided for appreciation such as a digital camera or portable equipment with a camera functionAn apparatus used for traffic such as a vehicle-carried sensor for imaging forwardly or rearwardly, around or within an automobile for the object of safe driving such as automatic stopping or recognition of a state of the driver, a surveillance camera for monitoring a traveling vehicle or a road, a distance measurement sensor for measuring the distance between vehicles or the likeAn apparatus used in household appliances such as a TV set, a refrigerator or an air conditioner for imaging a gesture of a user and performing an apparatus operation in accordance with the gestureAn apparatus for medical use or healthcare use such as an endoscope or a device for imaging a blood vessel by reception of infrared lightAn apparatus for security use such as a surveillance camera for a security application or a camera for a personal authentication applicationAn apparatus for cosmetic use such as a skin measuring instrument for imaging the skin or a microscope for imaging the scalpAn apparatus for sports use such as an action camera or a wearable camera for a sports application or the likeAn apparatus for agricultural use such as a camera for monitoring the state of fields and crops

3. Example of Electronic Equipment

<Configuration Example of Electronic Equipment>

Further, the present technology is not restricted to application to a solid-state imaging element but can be applied also to an imaging apparatus. Here, the imaging apparatus signifies electronic equipment having an imaging function such as a camera system of a digital still camera or a digital video camera or a mobile phone. It is to be noted that the imaging apparatus may be in the form of a module incorporated in electronic equipment, namely, a camera module.

Here, a configuration example of electronic equipment of the present technology is described with reference toFIG. 18.

The electronic equipment300depicted inFIG. 18includes a solid-state imaging element (device chip)301, an optical lens302, a shutter device303, a driving circuit304, and a signal processing circuit305. As the solid-state imaging element301, the solid-state imaging element1of the present technology described hereinabove is provided.

The optical lens302forms an image of image light (incident light) from an imaging object on an imaging plane of the solid-state imaging element301. Consequently, signal charge is accumulated for a fixed period into the solid-state imaging element301. The shutter device303controls a light irradiation period and a light blocking period for the solid-state imaging element301.

The driving circuit304supplies driving signals for controlling a signal transfer operation of the solid-state imaging element301, a shutter operation of the shutter device303, and a light emission operation of a light emitting section not depicted. The driving circuit304controls various operations using parameters set by a CPU not depicted. The solid-state imaging element301performs signal transfer in response to a driving signal (timing signal) supplied from the driving circuit304. The signal processing circuit305performs various signal processes for a signal outputted from the solid-state imaging element301. An image signal for which the signal processes have been performed is stored into a storage medium such as a memory or outputted to a monitor.

4. Application Example to In-Vivo Information Acquisition System

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

FIG. 19is a block diagram depicting an example of a schematic configuration of an in-vivo information acquisition system of a patient using a capsule type endoscope, to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

The in-vivo information acquisition system10001includes a capsule type endoscope10100and an external controlling apparatus10200.

The capsule type endoscope10100is swallowed by a patient at the time of inspection. The capsule type endoscope10100has an image pickup function and a wireless communication function and successively picks up an image of the inside of an organ such as the stomach or an intestine (hereinafter referred to as in-vivo image) at predetermined intervals while it moves inside of the organ by peristaltic motion for a period of time until it is naturally discharged from the patient. Then, the capsule type endoscope10100successively transmits information of the in-vivo image to the external controlling apparatus10200outside the body by wireless transmission.

The external controlling apparatus10200integrally controls operation of the in-vivo information acquisition system10001. Further, the external controlling apparatus10200receives information of an in-vivo image transmitted thereto from the capsule type endoscope10100and generates image data for displaying the in-vivo image on a display apparatus (not depicted) on the basis of the received information of the in-vivo image.

In the in-vivo information acquisition system10001, an in-vivo image imaged a state of the inside of the body of a patient can be acquired at any time in this manner for a period of time until the capsule type endoscope10100is discharged after it is swallowed.

A configuration and functions of the capsule type endoscope10100and the external controlling apparatus10200are described in more detail below.

The capsule type endoscope10100includes a housing10101of the capsule type, in which a light source unit10111, an image pickup unit10112, an image processing unit10113, a wireless communication unit10114, a power feeding unit10115, a power supply unit10116and a control unit10117are accommodated.

The light source unit10111includes a light source such as, for example, a light emitting diode (LED) and irradiates light on an image pickup field-of-view of the image pickup unit10112.

The image pickup unit10112includes an image pickup element and an optical system including a plurality of lenses provided at a preceding stage to the image pickup element. Reflected light (hereinafter referred to as observation light) of light irradiated on a body tissue which is an observation target is condensed by the optical system and introduced into the image pickup element. In the image pickup unit10112, the incident observation light is photoelectrically converted by the image pickup element, by which an image signal corresponding to the observation light is generated. The image signal generated by the image pickup unit10112is provided to the image processing unit10113.

The image processing unit10113includes a processor such as a central processing unit (CPU) or a graphics processing unit (GPU) and performs various signal processes for an image signal generated by the image pickup unit10112. The image processing unit10113provides the image signal for which the signal processes have been performed thereby as RAW data to the wireless communication unit10114.

The wireless communication unit10114performs a predetermined process such as a modulation process for the image signal for which the signal processes have been performed by the image processing unit10113and transmits the resulting image signal to the external controlling apparatus10200through an antenna10114A. Further, the wireless communication unit10114receives a control signal relating to driving control of the capsule type endoscope10100from the external controlling apparatus10200through the antenna10114A. The wireless communication unit10114provides the control signal received from the external controlling apparatus10200to the control unit10117.

The power feeding unit10115includes an antenna coil for power reception, a power regeneration circuit for regenerating electric power from current generated in the antenna coil, a voltage booster circuit and so forth. The power feeding unit10115generates electric power using the principle of non-contact charging.

The power supply unit10116includes a secondary battery and stores electric power generated by the power feeding unit10115. InFIG. 19, in order to avoid complicated illustration, an arrow mark indicative of a supply destination of electric power from the power supply unit10116and so forth are omitted. However, electric power stored in the power supply unit10116is supplied to and can be used to drive the light source unit10111, the image pickup unit10112, the image processing unit10113, the wireless communication unit10114and the control unit10117.

The control unit10117includes a processor such as a CPU and suitably controls driving of the light source unit10111, the image pickup unit10112, the image processing unit10113, the wireless communication unit10114and the power feeding unit10115in accordance with a control signal transmitted thereto from the external controlling apparatus10200.

The external controlling apparatus10200includes a processor such as a CPU or a GPU, a microcomputer, a control board or the like in which a processor and a storage element such as a memory are mixedly incorporated. The external controlling apparatus10200transmits a control signal to the control unit10117of the capsule type endoscope10100through an antenna10200A to control operation of the capsule type endoscope10100. In the capsule type endoscope10100, an irradiation condition of light upon an observation target of the light source unit10111can be changed, for example, in accordance with a control signal from the external controlling apparatus10200. Further, an image pickup condition (for example, a frame rate, an exposure value or the like of the image pickup unit10112) can be changed in accordance with a control signal from the external controlling apparatus10200. Further, the substance of processing by the image processing unit10113or a condition for transmitting an image signal from the wireless communication unit10114(for example, a transmission interval, a transmission image number or the like) may be changed in accordance with a control signal from the external controlling apparatus10200.

Further, the external controlling apparatus10200performs various image processes for an image signal transmitted thereto from the capsule type endoscope10100to generate image data for displaying a picked up in-vivo image on the display apparatus. As the image processes, various signal processes can be performed such as, for example, a development process (demosaic process), an image quality improving process (bandwidth enhancement process, a super-resolution process, a noise reduction (NR) process and/or image stabilization process) and/or an enlargement process (electronic zooming process). The external controlling apparatus10200controls driving of the display apparatus to cause the display apparatus to display a picked up in-vivo image on the basis of generated image data. Alternatively, the external controlling apparatus10200may also control a recording apparatus (not depicted) to record generated image data or control a printing apparatus (not depicted) to output generated image data by printing.

An example of an in-vivo information acquisition system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the image pickup unit10112from within the configuration described hereinabove. In particular, for example, the solid-state imaging element1ofFIG. 16can be applied to the image pickup unit10112. By applying the technology according to the present disclosure to the image pickup unit10112, the time width of a pulse signal can be secured sufficiently, and the pixel size can be reduced. Accordingly, it is possible to downsize the apparatus, for example. Further, reduction in power consumption can be anticipated.

5. Application Example to Endoscopic Surgery System

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

FIG. 21is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG. 20.

An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the endoscope11100or the (image pickup unit11402of the) camera head11102from within the configuration described hereinabove. For example, the solid-state imaging element1ofFIG. 16can be applied to the endoscope11100or (the image pickup unit11402of) the camera head11102. By applying the technology according to the present disclosure to the endoscope11100or (the image pickup unit11402of) the camera head11102, it is possible to sufficiently secure a time width of a pulse signal and reduce a pixel size, and therefore, for example, the apparatus can be downsized. Further, it is possible to achieve reduction of power consumption.

It is to be noted that, while an endoscopic surgery system is described here as an example, the technology according to the present disclosure can be applied, for example, to a microsurgery system.

6. Application Example to Moving Body

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be implemented as an apparatus that is incorporated in any type of moving body such as an automobile, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, or a robot.

An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied, for example, to the imaging section12031(including the imaging sections12101to12104) or the like from within the configuration described above. In particular, for example, the solid-state imaging element1ofFIG. 16can be applied to the imaging section12031(including the imaging sections12101to12104). By applying the technology according to the present disclosure to the imaging section12031(including the imaging sections12101to12104), it is possible to sufficiently secure a time width of a pulse signal and reduce a pixel size, and therefore, for example, the apparatus can be downsized. Further, it is possible to achieve reduction of power consumption.

It is to be noted that, in the present specification, the steps that describe the series of processes described hereinabove not only include processes that are performed in a time series in accordance with the order described but also include processes that are executed in parallel or individually even if they are not necessarily be processed in a time series.

Further, the embodiment in the present disclosure is not limited to the embodiments described hereinabove and can be altered in various manners without departing from the subject matter of the present disclosure.

Further, a component described as one apparatus (or processing section) in the foregoing description may be divided so as to be configured as a plurality of apparatuses (or processing sections). Conversely, components described as a plurality of apparatuses (or processing sections) in the foregoing description may be collected so as to be configured as a single apparatus (or processing section). Naturally, a component other than those described hereinabove may be added to the configuration of each apparatus (or each processing section). Furthermore, if a configuration or operation as an entire system is substantially same, part of components of a certain apparatus (or processing section) may be included in a configuration of some other apparatus (or some other processing section). In short, the present technology is not limited to the embodiments described above and can be altered in various manners without departing from the subject matter of the present technology.

Although the preferred embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the disclosure is not limited to such examples as described above. It is apparent that persons who have common knowledge in the technical field to which the present disclosure pertains could have conceived various alterations or modifications within the scope of the technical idea described in the claims, and it is understood that those naturally fall within the technical scope of the present disclosure.

It is to be noted that the present disclosure can assume such a configuration as described below.

a pixel array section in which unit pixels each having a photoelectric conversion section are disposed; and

an AD converter for each of the unit pixels, in which the AD converter includesa pulse generation circuit that feeds back a delay signal obtained by delaying an output signal of a comparator to the comparator and performs arithmetic operation of the output signal and the delay signal to generate a pulse signal, anda latch circuit that latches a data code using the pulse signal generated by the pulse generation circuit.

(2) The solid-state imaging element according to (1) above, in which

the pulse generation circuit includes:a delay element that delays the output signal of the comparator to generate the delay signal; andan arithmetic element that arithmetically operates the output signal and the delay signal to generate the pulse signal.

(3) The solid-state imaging element according to (2) above, in which

the arithmetic element includes a NOR circuit.

(4) The solid-state imaging element according to (2) above, in which

the arithmetic element includes a NAND circuit.

(5) The solid-state imaging element according to any one of (1) to (4) above, in which in the pulse generation circuit, a logical threshold value of a gate element is adjusted.

(6) The solid-state imaging element according to (5) above, in which

in the pulse generation circuit, the logical threshold value of the gate element is adjusted by changing an element number of transistors.

(7) The solid-state imaging element according to (5) above, in which

in the pulse generation circuit, the logical threshold value of the gate element is adjusted by setting the threshold value of the elements of transistors to a high threshold value and a low threshold value.

(8) The solid-state imaging element according to any one of (1) to (7) above, in which

the pulse generation circuit further includes a selection circuit that selects a path used when a delay signal obtained by delaying the output signal of the comparator is to be fed back to the comparator and the output signal and the delay signal are arithmetically operated to generate a pulse signal and another path used when the output signal of the comparator is to be used as it is.

(9) The solid-state imaging element according to any one of (1) to (8) above, in which

the solid-state imaging element includes a stacked type solid-state imaging element.

a solid-state imaging element includinga pixel array section in which unit pixels each having a photoelectric conversion section are disposed, andan AD converter for each of the unit pixels, in which the AD converter includesa pulse generation circuit that feeds back a delay signal obtained by delaying an output signal of a comparator to the comparator and performs arithmetic operation of the output signal and the delay signal to generate a pulse signal, anda latch circuit that latches a data code using the pulse signal generated by the pulse generation circuit;

a signal processing circuit that processes an output signal outputted from the solid-state imaging element; and

an optical system that enters incident light into the solid-state imaging element.

REFERENCE SIGNS LIST