Multi-layered metal line of semiconductor device for preventing diffusion between metal lines and method for forming the same

A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean patent application number 10-2006-0137203 filed on Dec. 28, 2006, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a multi-layered metal line of a semiconductor device and a method for forming the same, and more particularly to a multi-layered metal line of a semiconductor device which prevents diffusion between upper and lower metal lines brought into contact with each other and a method for forming the same.

Memory cells in a semiconductor memory device operating in a high speed are formed in a stacked structure. Further, the metal line for carrying the electric signals to the respective cells is formed in a multi-layered structure. The multi-layered metal line offers advantageous design flexibility and allows the wiring resistance and current capacity to be set to an acceptable margin.

Al has been a material of choice for a metal line due to its excellent electric conductivity and its relatively easy-to-process characteristics. However, problems appear when Al is applied to form a metal line in a highly integrated semiconductor device due to undesirably increased resistance of the metal line formed with Al. In dealing with this problem caused by the increased wiring resistance due to the high integration of a semiconductor device, Cu instead of Al is currently being adopted as the suitable material for a metal line, as Cu offers relatively lower resistance than Al.

However, using Cu for all multi-layered metal lines is not considered preferable in consideration of the device characteristics and reasonable manufacturing cost. Therefore, recently, a method for forming a multi-layered metal line has been suggested, in which a lower metal line and an upper metal line are formed using Al and Cu, respectively.

Hereafter, a conventional method for forming a multi-layered metal line of a semiconductor device, in which a lower metal line and an upper metal line are respectively formed using Al and Cu, will be described with reference toFIG. 1.

A passivation layer130is formed on a semiconductor substrate100having a lower Al line110and an interlayer dielectric120formed thereon, to prevent the lower Al line110from being damaged in a subsequent process. A first insulation layer140and an etch barrier150for preventing the first insulation layer140from being etched in a subsequent process for etching a second insulation layer are sequentially formed on the passivation layer130. A second insulation layer160is then formed on the etch barrier150.

A via hole171is defined to expose the lower Al line110by etching the second insulation layer160, the etch barrier150, the first insulation layer140, and the passivation layer130. By additionally etching the second insulation layer160over the via hole171using the etch barrier150as an etch stop layer until the etch barrier150is exposed, a trench172is formed to delimit (or define) a metal line forming region. In this way, a dual type damascene pattern170composed of the via hole171and the trench172is formed.

A diffusion barrier180is formed on the surface of the damascene pattern170. The diffusion barrier180is made of a stack of a Ti layer181and a TiN layer182. A Cu layer is deposited in the damascene pattern170, which is formed with the diffusion barrier180. Through this, a via contact190for connecting the lower Al line110and an upper Cu line is formed in the via hole171of the damascene pattern170, and the upper Cu line191is formed in the trench172of the damascene pattern170.

As described above, when forming the multi-layered metal line according to the conventional method of forming the lower metal line of Al and the upper metal line of Cu, the diffusion barrier180is necessarily formed between the lower Al line110and the upper Cu line190,191in order to prevent diffusion between the lower Al line110and the upper Cu line190,191.

In general, the stack of the Ti layer181and the TiN layer182is mainly used as a diffusion barrier in a multi-layered metal line, in which a lower metal line110and an upper metal line190,191are formed using Al and Cu respectively.

However, the stack of the Ti layer181and the TiN layer182of the diffusion barrier180does not provide the sufficient thickness to effectively suppress the diffusion between the lower Al line110and the upper Cu line which190,191that are brought into contact with each other.

Increasing the thickness of the diffusion barrier180formed by the Ti layer181and the TiN layer182could suppress the diffusion between the lower Al line110and the upper Cu line190,191brought into contact with each other. Nevertheless, the increased thickness of the Ti layer181and the TiN layer182reduces the overall area of the damascene pattern170in which the Cu layer190,191is to be filled, and this in turn causes the resistance to increase due to the reduction of the area of the metal line.

Also, when the thickness of the Ti layer181and the TiN layer182increases, it is difficult to fill the Cu layer in the via hole171of the damascene pattern170by which a void can be created in the via hole171, and the presence of voids causes a significant increase in resistance.

Accordingly, it is not practical to adopt the way of increasing the thickness of the diffusion barrier layer180(having the Ti layer181and the TiN layer182) to suppress the diffusion between the lower Al line110and the upper Cu line190,191brought into contact with each other.

SUMMARY OF THE INVENTION

An embodiment of the present invention is directed to a multi-layered metal line of a semiconductor device which prevents diffusion between upper and lower metal lines brought into contact with each other and a method for forming the same.

In one embodiment, a multi-layered metal line of a semiconductor device comprises a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.

The lower metal line is made of an Al layer.

The lower metal line is recessed by a thickness corresponding to 1/20˜½ of an overall thickness of the lower metal line.

The glue layer is made of a Ti layer.

The glue layer has a thickness of 10˜200 Å.

The first diffusion barrier is made of a TiN layer.

The second diffusion barrier is made of a TiCN layer.

The second diffusion barrier has a thickness of 5˜50 Å.

The third diffusion barrier is made of a Ta or TaN layer.

The third diffusion barrier has a thickness of 10˜100 Å.

The upper metal line is made of a Cu layer.

In another embodiment, a method for forming a multi-layered metal line of a semiconductor device comprises the steps of forming an insulation layer on a semiconductor substrate formed with a lower metal line; etching the insulation layer and thereby forming a damascene pattern for exposing the lower metal line and for delimiting an upper metal line forming region; recessing an exposed portion of the lower metal line; forming a glue layer on a surface of the recessed portion of the lower metal line; forming a first diffusion barrier on the glue layer to fill the recessed portion of the lower metal line; forming a second diffusion barrier on the first diffusion barrier and the glue layer; forming a third diffusion barrier on the second diffusion barrier and on a surface of the damascene pattern; and forming an upper metal line on the third diffusion barrier to fill the damascene pattern.

The lower metal line is made of an Al layer.

The step of etching the lower metal line is implemented in a manner such that the lower metal line is etched by a thickness corresponding to 1/20˜½ of an overall thickness of the lower metal line.

The glue layer is made of a Ti layer through CVD or PVD.

The glue layer is formed to have a thickness of 10˜200 Å.

The first diffusion barrier is made of a TiN layer through CVD.

The second diffusion barrier is made of a TiCN layer.

The second diffusion barrier is formed to have a thickness of 5˜50 Å.

The second diffusion barrier is formed through heat treatment or plasma treatment of the first diffusion barrier and the glue layer using a hydrocarbon-based source gas.

The hydrocarbon-based gas is CH3or C2H5gas.

The plasma treatment is implemented under an atmosphere of CH3or C2H5at conditions including a temperature of 200˜500° C., a pressure of 1˜100 torr and an RF power of 0.1˜1 kW.

The third diffusion barrier is made of a Ta or TaN layer.

The third diffusion barrier is formed to have a thickness of 10˜100 Å.

The upper metal line is made of a Cu layer.

DESCRIPTION OF SPECIFIC EMBODIMENTS

In the present invention, in order to suppress the diffusion between upper and lower metal lines brought into contact with each other, a diffusion barrier, which is inserted as a contact interface between Al forming the lower metal line and Cu forming the upper metal line, is made of a stack of a TiN layer, a TiCN layer, and a Ta or TaN layer.

Since the TiCN layer has excellent diffusion prevention characteristics, the diffusion barrier made of the stack of the TiN layer, the TiCN layer, and the Ta or TaN layer retains excellent capability for preventing diffusion between the lower Al line and the upper Cu line brought into contact with each other.

Accordingly, when forming a multi-layered metal line by using Al for the lower metal line and Cu for the upper metal line in a ultra-high-integrated semiconductor device, the present invention makes it possible to form an excellent diffusion barrier for suppressing diffusion between the lower Al line and the upper Cu line brought into contact with each other. As a result, it is possible to prevent a metallic compound of high resistance from being formed due to diffusion between the upper and lower metal lines.

Therefore, since the present invention makes it possible to prevent a metallic compound of high resistance from being formed due to diffusion between the upper and lower metal lines brought into contact with each other, the performance characteristics of a semiconductor device are improved.

Hereafter, a method for forming a multi-layered metal line of a semiconductor device in accordance with an embodiment of the present invention will be described in detail with reference toFIGS. 2A through 2E.

Referring toFIG. 2A, an interlayer dielectric220is formed on a semiconductor substrate200with a lower Al line210formed thereon. A passivation layer230is formed on the interlayer dielectric220to prevent the lower Al line210from being damaged in a subsequent etching process. A first insulation layer240, an etch barrier250, and a second insulation layer260are formed on the passivation layer230. Each of the first and second insulation layers240and260is made of an oxide-based layer, and the etch barrier250is made of a nitride-based layer.

By etching the second insulation layer260, the etch barrier250, the first insulation layer240, and the passivation layer230, a via hole271is defined to expose the lower Al line210. By additionally etching the second insulation layer260over the via hole271using the etch barrier250as an etch stop layer until the etch barrier250is exposed, a trench272is formed to delimit (or define) an upper metal line forming region. In this way, a dual type damascene pattern270composed of the via hole271and the trench272is formed. Here, while the dual type damascene pattern270is formed by defining the trench272after defining the via hole271, the sequence of forming the dual type damascene pattern270can be reversed.

Referring toFIG. 2B, the exposed portion of the lower Al line210is recessed. Recessing of the lower Al line210is implemented in a manner such that the lower Al line210is etched by a thickness corresponding to 1/20˜½ of the overall thickness of the lower Al line210.

A glue layer281is formed on the surfaces of the via hole271and the trench272including the recessed portion of the lower Al line210. The glue layer281is made of a Ti layer through a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process to a thickness of 10˜200 Å.

A first diffusion barrier282is formed on the glue layer281to fill the damascene pattern270. The first diffusion barrier282is made of a TiN layer through CVD.

Referring toFIG. 2C, the first diffusion barrier282and the glue layer281are removed such that the first diffusion barrier282and the glue layer281remain only on the recessed portion of the lower Al line210. A second diffusion barrier283is formed on the first diffusion barrier282and the glue layer281. The second diffusion barrier283is made of a TiCN layer through heat treatment or plasma treatment of the TiN layer282serving as the first diffusion barrier and the Ti layer281serving as the glue layer using a hydrocarbon-based gas, to have a thickness of 5˜50 Å.

The hydrocarbon-based gas includes CH3or C2H5gas. When the TiN layer282serving as the first diffusion barrier and the Ti layer281serving as the glue layer are plasma-processed, the plasma treatments conducted under an atmosphere of CH3or C2H5at conditions including a temperature of 200˜500° C., a pressure of 1˜100 torr and an RF power of 0.1˜1 kW.

Referring toFIG. 2D, a third diffusion barrier284is formed on the TiCN layer283serving as the second diffusion barrier and on the damascene pattern270to have a thickness of 10˜100 Å. Here, the third diffusion barrier284is made of a Ta or TaN layer.

Referring toFIG. 2E, a Cu layer for an upper metal line is deposited on the third diffusion barrier284to fill the damascene pattern270. By etching the Cu layer until the second insulation layer260is exposed, a via contact290is formed in the via hole271of the damascene pattern270, and an upper Cu line291(which along with290is brought into contact with the lower Al line210) is formed in the trench272of the damascene pattern270.

As described above, because the TiCN layer283of the present invention having excellent diffusion prevention characteristics is formed through surface treatment of the Ti layer281serving as the glue layer and the TiN layer282serving as the first diffusion barrier, the diffusion barrier characteristics is improved in the present invention.

Since the TiCN layer283has excellent diffusion prevention characteristics, it is possible to form an excellent diffusion barrier capable of suppressing diffusion between the lower Al line210and the upper Cu line290,291brought into contact with each other by forming the diffusion barrier which is composed of the TiN layer282serving as the first diffusion barrier, the TiCN layer283serving as the second diffusion barrier, and the Ta or TaN layer284serving as the third diffusion barrier.

As is apparent from the above description, by forming a multi-layered metal line in a semiconductor device by using Al for a lower metal line and Cu for an upper metal line, the present invention makes it possible to form an excellent diffusion barrier for suppressing diffusion between the lower Al line and the upper Cu line brought into contact with each other. As a result, it is possible to prevent a metallic compound of high resistance from being formed due to diffusion between the metal lines.

Therefore, when forming a multi-layered metal line composed of the lower Al line and the upper Cu line, the characteristics of a semiconductor device of the present invention are improved since a metallic compound of high resistance due to diffusion between the upper and lower metal lines brought into contact with each other is prevented from being formed.