SOI MOSFET

A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device formed on an SOI (Silicon On Insulator) substrate and a method for manufacturing the same.

2. Description of the Related Art

FIGS. 1A and 1Bshow a conventional transistor on an SOI substrate (hereinafter, referred to as an SOI transistor) disclosed in Japanese Laid Open Patent Application (JP-P-Heisei 4-34980).FIG. 1Ais a plan view of a structure of the conventional SOI transistor, andFIG. 1Bis a cross sectional view along a dotted line X-X′ in FIG.1A.

In the conventional SOI transistor, an SOI substrate has a silicon substrate101, an insulating film102on the silicon substrate101, and a silicon layer103(hereinafter, referred to as an SOI layer) on the insulating film102. An active region is formed in the SOI layer103, which includes a channel region108, a source region109and a drain region110. A gate electrode105is formed on the SOI layer103through a gate insulating film104. An isolation insulating film106is formed on the SOI layer103around the active region. A well region111is formed under the isolation insulating film106, into which impurity with the same conductivity type as in the channel region108is introduced. A body contact107is formed on a predetermined area of the well region111to penetrate the isolation insulating film106. Contact holes113are formed in the interlayer insulating film112to reach the source and drain regions109and110. Wiring layers114are formed to fill the contact holes113. A wiring layer115is formed on the body contact107to electrically connect to the well region111. This structure is characterized in that excess carriers in the channel region108can escape out of the SOI transistor through the well region111, resulting in suppression of the floating body effects. Such a path through which excess carriers can escape from the channel region108is referred to as a “carrier path”, hereinafter.

A method of forming the isolation insulating film106is not disclosed in the JP-P-Heisei 4-34980. The isolation insulating film106may be formed by using a conventional method which have been generally adopted in a FET (Field Effect) transistor on a bulk substrate, as shown inFIGS. 2Ato2C. First, impurity is introduced into the SOI layer103(FIG.2A). Next, the isolation insulating film106is formed on the SOI layer103through a thermal oxidation process or a CVD (Chemical Vapor Deposition) process (FIG.2B). After that, a part of the isolation insulating film106is etched through a wet etching process to form the structure shown in FIG.2C. The active region is to be formed under the region where the isolation insulating film106is removed. The carrier path is formed under the remaining isolation insulating film106. In this case, therefore, it is impossible to introduce impurity into the carrier path with higher density than in the channel region.

FIGS. 3Ato3C show another method of forming the isolation insulating film106inFIG. 1B. Amask pattern such as a photo resist or a SiO2film is formed on a predetermined area of the SOI layer103, and then impurity is introduced into the SOI layer103(FIG.3A). After the mask pattern is removed, the isolation insulating film106is formed on the SOI layer103(FIG.3B). Next, a part of the isolation insulating film106is etched (FIG.3C). In this case, an edge of the active region deviates from an edge of the carrier path as shown inFIG. 3C, i.e., the edge of the active region can not be located to self-align with the edge of the carrier path.

FIG. 4is a cross sectional view showing a structure of another conventional SOI transistor disclosed in IEEE, Electron Device Letter, Vol. 18, pp. 102-104. In the conventional SOI transistor, an SOI substrate has a silicon substrate130, an insulating film121on the silicon substrate130, and an SOI layer122on the insulating film121. An active region is formed in the SOI layer122, which includes a source region124and a drain region123. A gate electrode125is formed on the SOI layer122through a gate insulating film126. An isolation insulating film129(hereinafter, referred to as a LOCOS region) is formed adjacent to the active region by a LOCOS (Local Oxidation of Silicon) method. A carrier path127is formed in a residue semiconductor layer under the LOCOS region129. A body contact region128is connected to the carrier path127. Excess carriers can escape out of the SOI transistor through the carrier path127, resulting in suppression of the floating body effects.

Other conventional SOI transistors similar to the transistor shown inFIG. 4are disclosed in the Symposium on VLSI Technology 1996, pp. 92-93, and Japanese Laid Open Patent Application (JP-P2000-294794A). In the other conventional transistor disclosed in JP-P2000-204794A, a full isolating trench is also provided next to the active region to reach the insulating film121. In these conventional transistors mentioned above, as shown inFIG. 4, the carrier path127is formed under the LOCOS region129, i.e. in the residue semiconductor layer. Therefore, thickness of the SOI layer122around the carrier path127becomes thinner than that in the active region.

FIG. 5is a cross sectional view showing a structure of still another conventional SOI transistor disclosed in the Symposium on VLSI Technology 2000, pp. 154-155. In the conventional SOI transistor, an SOI substrate has a silicon substrate130, an insulating film121on the silicon substrate130, and an SOI layer122on the insulating film121. An active region is formed in the SOI layer122, which includes a source region124and a drain region123. A gate electrode125is formed on the SOI layer122through a gate insulating film126. Isolating trenches131and132exist in the SOI layer122around the active region, which are formed through an STI (Shallow Trench Isolation) process. The isolating trench131adjacent to the active region (hereinafter, referred to as a partial STI) does not reach the insulating film121. A carrier path127is formed in a residue semiconductor layer under the partial STI131. A body contact region128is connected to the carrier path127. Excess carriers can escape out of the SOI transistor through the carrier path127, resulting in suppression of the floating body effects.

Another conventional SOI transistor similar to the transistor shown inFIG. 5is disclosed in Japanese Laid Open Patent Application (JP-P2002-217420A). In these conventional transistors mentioned above, as shown inFIG. 5, the carrier path127is formed under the partial STI131, i.e. in the residue semiconductor layer. Therefore, thickness of the SOI layer122around the carrier path127becomes thinner than that in the active region.

When an SOI transistor such as a full-depletion SOI MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is designed to have a very thin SOI layer (typically 10 to 50 nm thickness), a carrier path in the SOI transistor also becomes very thin and hence resistivity of the carrier path increases. Therefore, it is necessary to increase impurity density in the carrier path more than that in the channel region of the SOI transistor. Also, it is preferable to locate the edge of the carrier path self-aligned with the edge of the active region of the SOI transistor. Moreover, when the carrier path is formed under a LOCOS region or a partial STI as inFIGS. 4 and 5, the carrier path becomes further thinner than the SOI layer. Such a carrier path is insufficient for avoiding the floating body effects. It is also preferable to make the carrier path applicable to an SOI transistor having an extremely thin SOI layer such as a full-depletion SOI MOSFET.

Also, when impurity density in the well region becomes too high in the conventional SOI transistor shown inFIGS. 1A and 1B, the strength of electric field between the source/drain region and the well region increases and hence leak current increases. Also, if the impurity density in the well region becomes high, a parasitic capacitance between the source/drain region and the well region increases, resulting in deterioration of operation speed of the SOI transistor. It is preferable to reduce the resistivity of the carrier path as possible with the leak current and the parasitic capacitance between the source/drain region and the well region being kept low.

Also, with regard to the processes shown inFIGS. 2C and 3C, when the isolation insulating film106is processed by a wet etching, the etching proceeds isotropically and hence the edge of the isolating insulating film106does not become steep. Also, the isolating insulating film106is etched horizontally due to the isotropic etching, which causes reduction of the area of the isolating insulating film106. On the other hand, when the isolating insulating film106is processed by a dry etching, the surface of the SOI layer103where the active region is to be formed is exposed to plasmas used in the dry etching, which causes various defects. Moreover, there is a possibility that the SOI layer103is etched, because an etching selection rate of SiO2to silicon is lower in the dry etching than in the wet etching. A device isolation method is desired with which the edge of the isolation insulating film is formed to be steep and the SOI layer where the active region is to be formed is not etched during the device isolation process.

Also, in the conventional SOI transistor shown inFIGS. 1A and 1B, the surface of the isolation insulating film106is located upper than the surface of the SOI layer103where the active region is to be formed, as shown inFIGS. 2C and 3C. Therefore, deposition of material of the gate electrode105over the SOI substrate results in a concavo-convex surface of the material layer. If the surface of the material layer is not flat when forming the gate electrode105, the resist pattern and hence the formed gate electrode105would be deformed. Also, if the top and bottom surfaces of the material layer are not flat when forming the gate electrode105through an etching process such as an RIE (Reactive Ion Etching), the etching of a part of the material layer would finish earlier than the other part of the material layer, resulting in exposure of the gate insulating film104. If the etching is continued to remove the remaining material layer, the exposed gate insulating film104and moreover the SOI layer would be etched. Thus, the structure of the SOI transistor can not be achieved. A method is desired with which the top and bottom surfaces of the material layer for the gate electrode can be formed to be planar so that deformation of the gate electrode is not caused in the etching process.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a semiconductor device having an SOI transistor and a method for manufacturing the same, in which a carrier path is thick enough to avoid the floating body effects even in the case of a very thin SOI layer.

Another object of the present invention is to provide a semiconductor device having an SOI transistor and a method for manufacturing the same, in which resistivity of the carrier path is reduced, while leak current and parasitic capacitance between the carrier path and the source/drain regions of the SOI transistor are kept low.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device having an SOI transistor, in which impurity density in the carrier path can be made higher than that in a channel region of the SOI transistor, and an edge of the carrier path can be formed to self-align with an edge of an active region of the SOI transistor.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device having an SOI transistor, in which the SOI layer where the active region is to be formed is not etched during a device isolation process, and an edge of an isolation insulating film is formed to be steep and self-align with the edge of the active region.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device having an SOI transistor, in which top and bottom surfaces of a material layer for a gate electrode are formed to be planar.

In an aspect of the present invention, a semiconductor device includes: a field effect transistor having a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, and source/drain regions formed in the semiconductor layer on both sides of the gate electrode by heavily introducing a first conductivity type impurity; a body contact region in which a second conductivity type impurity is heavily introduced into the semiconductor layer; a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and an impurity with the same conductivity type as the body contact region is introduced into the semiconductor layer; and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions of the field effect transistor.

The gate electrode includes a first gate electrode layer having substantially the same thickness as the field insulating film and a second gate electrode layer formed on the first gate electrode layer and extending over a carrier path.

The first gate electrode layer and the second gate electrode layer can be made of a material deposited in different processes. The first gate electrode layer and the second gate electrode layer can be made of different materials.

An impurity density in the semiconductor layer in a part of the partial isolating region contiguous to a device region in which the field effect transistor is provided can be lower than an impurity density in the semiconductor layer in the other part of the partial isolating region.

An impurity density in the semiconductor layer in a part of the partial isolating region contiguous to a device region in which the field effect transistor is provided can be lower than an impurity density in the semiconductor layer in the other part of the partial isolating region and can be the same as an impurity density in the semiconductor layer in the device region.

The full isolating region can be formed to be in contact with the whole sides parallel to the first direction of the source/drain regions of the field effect transistor. The full isolating region can be formed to be in contact with the whole sides parallel to the first direction of the source/drain regions of the field effect transistor and a part of a side perpendicular to the first direction of the source/drain regions. The full isolating region can be formed to be in contact with a part of a side parallel to the first direction of the source/drain regions of the field effect transistor and the whole of one side perpendicular to the first direction of the source/drain regions.

Only the full isolating region can be provided between the adjacent field effect transistors. A plurality of the field effect transistors can be provided in one block surrounded by the full isolating region.

The p-channel field effect transistor and the n-channel type field effect transistor can be provided in different blocks surrounded by the full isolating region, respectively. A plurality of the p-channel type field effect transistors and a plurality of the n-channel type field effect transistors can be provided in different blocks surrounded by the full isolating region, respectively.

The full isolating region defining a block including a plurality of the field effect transistors can be formed to be in contact with a side of the source/drain regions. The full isolating region defining a block including one field effect transistor can be formed to be in contact with a side of the source/drain regions.

In another aspect of the present invention, a method for manufacturing a semiconductor device includes: (a) forming a CMP (Chemical Mechanical Polishing) mask to cover a device region and a body contact region on a semiconductor layer on an insulator, the CMP mask being composed of an upper mask layer resistant to a CMP and a lower mask layer made of a conductive material or a material which can be made conductive by introducing impurity; (b) introducing a second conductivity type impurity into at least a portion of the semiconductor layer which is not covered by the CMP mask, the second conductivity type impurity is different from an impurity which is to be introduced into source/drain regions; (c) forming a full isolating region by removing the semiconductor layer on the insulator in a part of a region contiguous to the CMP mask; (d) forming wholly a second insulating film different from a material of the CMP mask and planarizing the second insulating film by a CMP; (e) removing the upper mask layer of the CMP mask and forming an upper gate electrode layer made of a conductive material or a material which can be made conductive by introducing impurity; (f) removing the upper gate electrode layer and the lower mask layer of the CMP mask in the body contact region and a part of the device region, to form a gate electrode composed of a residual of the upper gate electrode layer and the lower mask layer of the CMP mask and extending in a first direction; and (g) forming source/drain regions in the semiconductor layer on both sides of the gate electrode to form a field effect transistor. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions of the field effect transistor.

The (d) forming step can be carried out after the (c) forming step. The (c) forming step can be carried out after the (d) forming step.

A method for manufacturing a semiconductor device may include (h) forming a CMP (Chemical Mechanical Polishing) mask to cover a device region and a body contact region on a semiconductor layer on an insulator, the CMP mask being composed of an upper mask layer resistant to a CMP and a lower mask layer made of a conductive material or a material which can be made conductive by introducing impurity; (i) introducing a second conductivity type impurity into at least a portion of the semiconductor layer which is not covered by the CMP mask, the second conductivity type impurity is different from an impurity which is to be introduced into source/drain regions; (j) forming wholly a second insulating film different from a material of the CMP mask and planarizing the second insulating film by a CMP; (k) removing the upper mask layer of the CMP mask and forming an upper gate electrode layer made of a conductive material or a material which can be made conductive by introducing impurity; (l) removing the upper gate electrode layer and the lower mask layer of the CMP mask in the body contact region and a part of the device region, to form a gate electrode composed of a residual of the upper gate electrode layer and the lower mask layer of the CMP mask and extending in a first direction; (m) forming source/drain regions in the semiconductor layer on both sides of the gate electrode to form a field effect transistor; (n) covering the field effect transistor by an interlayer insulating film and planarizing the interlayer insulating film; and (o) forming a full isolating region by removing the semiconductor layer in a part of a region contiguous to the source/drain regions. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions of the field effect transistor.

The CMP mask can be a multiple-layer including a Si3N4film as a top layer. The CMP mask can be a multiple-layer including a SiO2film as a top layer and a Si3N4film as a second layer under the top layer. The CMP mask is a multiple-layer including a Si3N4film as a top layer and a polysilicon film as a second layer under the top layer. The CMP mask is a multiple-layer including a Si3N4film as a top layer, a SiO2film as a second layer under the top layer, and a polysilicon film as a third layer under the second layer.

The (b) introducing step can be carried out such that the second conductivity type impurity is the same as an impurity which is to be introduced into the semiconductor layer in the body contact region.

Materials of the lower mask layer of the CMP mask and the upper gate electrode layer can be polysilicon. The upper gate electrode layer can be a multiple-layer made of a conductive material or a material which can be made conductive by introducing impurity. The lower mask layer of the CMP mask can be made of polysilicon and the upper gate electrode layer can be made of metal.

A side wall can be formed next to the CMP mask after the (a) forming step. The (b) introducing step is carried out such that the second conductivity type impurity is introduced into at least a portion of the semiconductor layer which is not covered by the CMP mask and the side wall.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention relates to U.S. patent application Ser. No. 10/163,984, filed on Jun. 6, 2002. The disclosure of the application is incorporated herein by reference.

FIG. 6is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.FIGS. 7A,7B and7C are cross sectional views along dashed lines Y-Y′, X1-X1′ and X2-X2′ inFIG. 6, respectively.

An SOI substrate is composed of a silicon substrate201, a buried insulating film202on the silicon substrate201, and an SOI layer203on the buried insulating film202(seeFIGS. 7Ato7C). A gate insulating film204is formed on the SOI layer203. As shown inFIG. 6, a transistor active region209(a device region) is formed in a predetermined area of the SOI substrate. A body contact region212is formed in the SOI substrate apart from the transistor active region209. Impurity is introduced to the SOI layer203of a region other than the transistor active region209and the body contact region212to form a carrier path208(an area other than a hatched area in FIG.6). The carrier path208electrically connects the transistor active region209and the body contact region212.

As shown inFIG. 7B, source/drain regions215are formed in the SOI layer203of the transistor active region209.

As shown inFIG. 7C, a heavily doped layer216is formed in the SOI layer203of the body contact region212. A silicide layer218is formed on the heavily doped layer216and is connected to a wiring223(indicated by a thick line inFIG. 6) through a contact220penetrating an interlayer insulating film219. Excess carriers in the transistor active region209can escape out of the SOI transistor through the carrier path208and the body contact region212. Thus, the floating body effects can be suppressed.

A field insulating film213is formed on the SOI substrate. In a full isolating region210(indicated by a heavily hatched area in FIG.6), the field insulating film213reaches the buried insulating film202as shown in FIG.7B. In a partial isolating region211, the field insulating film213is formed over the carrier path208as shown inFIGS. 7Ato7C. In the SOI transistor according to the present embodiment, device isolation is achieved without using a LOCOS (Local Oxidation of Silicon) region as inFIG. 4or an STI (Shallow Trench Isolation) as in FIG.5. Instead, the field insulating film213is “elevated” over the SOI layer203(the carrier path208). Hence, thickness of the carrier path208in the partial isolating region211is substantially the same as that of the SOI layer203in the transistor active region209and the body contact region212. Therefore, even when the SOI layer is extremely thin (e.g. 5 to 50 nm) as in a full-depletion SOI MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the carrier path is effective in avoiding the floating body effects.

As shown inFIG. 7B, the silicide layers218are formed on the source/drain regions215. Each of the silicide layers218is connected to a wiring223(indicated by a thick line inFIG. 6) through a contact220penetrating the interlayer insulating film219. A gate electrode is formed on the gate insulating film204. The gate electrode includes a lower gate electrode layer205and an upper gate electrode layer214. The lower gate electrode layer205is between the field insulating film213of the partial isolating region211as shown in FIG.7A. The upper gate electrode layer214is formed on the lower gate electrode layer205and extends over the field insulating film213. The direction in which the upper gate electrode layer214extends is referred to as a first direction, hereinafter. A silicide layer218formed on the upper gate electrode layer214is connected to a wiring223through a contact220penetrating the interlayer insulating film219. The gate electrode is surrounded by a gate side wall217made of an insulating film.

The high impurity density in the carrier path208generally causes increase in leak current and parasitic capacitance between the transistor active region209and the carrier path208. In the present invention, however, the full isolating region210indicated by the heavily hatched area inFIG. 6is provided in contact with a side of the source/drain regions215(transistor active region209). According to the present embodiment, the full isolating region210is provided in contact with two sides of the source/drain regions215along the dashed line Y-Y′ (first direction). The full isolating region210can be formed to be in contact with at least one of a first side of the source region215parallel to the first direction and a second side of the drain region215parallel to the first direction. Other two sides of the transistor active region209(along the dashed line X1-X1′) are partly in contact with the full isolating region210. A part of the transistor active region209is connected to the carrier path208as shown in FIG.7A. Thus, the leak current and the parasitic capacitance between the transistor active region209and the carrier path208are reduced with suppressing the floating body effects.

A method for manufacturing the semiconductor device shown in FIG.6andFIGS. 7Ato7C will be described below in detail.

As shown inFIG. 8, an SOI substrate is provided, which includes the silicon substrate201, the buried insulating film202formed on the silicon substrate201, and the SOI layer203formed on the buried insulating film202. Here, the buried insulating film202is made of SiO2, whose thickness is 100 nm for example. Thickness of the SOI layer203is typically 5 to 50 nm. The gate insulating film204of 1.5 nm in thick is formed on the SOI layer203through a thermal oxidation process. A first polysilicon layer205(corresponding to the lower gate electrode layer205) of 50 nm in thick and a Si3N4film206of 150 nm in thick are formed in this order through a thin film deposition method such as a CVD (Chemical Vapor Deposition).

A resist207is formed to cover predetermined regions where the transistor active region209and the body contact region212are to be formed (see FIG.9). After that, the Si3N4film206and the first polysilicon layer205are etched through an RIE (Reactive Ion Etching) by using the resist207as a mask. Then, impurity is introduced into the SOI layer203through an ion implantation process by using the resist207or the Si3N4film206as a mask, to form the carrier path208. The region of the carrier path208is indicated by a white area other than a hatched area in FIG.9.FIGS. 10Ato10C are cross sectional views along dashed lines Y-Y′, X1-X1′ and X2-X2′ inFIG. 9, respectively.

The conductivity type of the implanted impurity ion is a p-type around a region where an n-channel transistor is to be formed (hereinafter, referred to as an n-channel transistor region), and n-type around a region where a p-channel transistor is to be formed (hereinafter, referred to as a p-channel transistor region). As the p-type impurity ion, for example, B+, BF2+and In can be used. As the n-type impurity ion, for example, As+, P+and Sb+can be used. A method of introducing different impurities into the SOI layer203around the p-channel transistor region and the n-channel transistor region is as follows. The resist207is first removed. In the case of introducing the impurity around the n-channel transistor region, a new photo resist is formed over and around the p-channel transistor region. The ion implantation is carried out by using the new photo resist and the Si3N4film206exposed at the n-channel transistor region as a mask. Similar processes are carried out in the case of the p-channel transistor region. The impurity density in the carrier path208is typically in a range from 1×1018cm−3to 1×1020cm−3. The amount of dose is typically in a range from 1×10—cm−2to 1×1015cm−2.

As described above, the impurity is introduced into the SOI layer203to form the carrier path208after covering by the mask the region where the transistor active region209is to be formed. Thus, the edge of the carrier path208can be formed to self-align with the edge of the transistor active region209. Moreover, the carrier path208and the transistor active region209are formed to be exclusive to each other. The impurity density in the carrier path208and that in the transistor active region209can be controlled independently. Therefore, the impurity density in the carrier path208can be made higher than that in the channel region in order to reduce resistivity of the carrier path208.

It should be noted that the impurity should be introduced at least along a path connecting the transistor active region209and the body contact region212(see FIG.6). It is possible that the impurity is not introduced in a region other than the path.

Next, an opening area221indicated by a dashed rectangular inFIG. 9is provided in the mask (resist207and the new photo resist mentioned above). After that, in a part of the region next to the transistor active region209, the gate insulating film204and the SOI layer203(carrier path208) are removed by using the resist pattern and the Si3N4film206as a mask. Then, the resist pattern is removed.FIG. 11is a plan view showing a structure of the semiconductor device at this time.FIGS. 12Ato12C are cross sectional views along dashed lines Y-Y′, X1-X1′ and X2-X2′ inFIG. 11, respectively. Here, the buried insulating film202is exposed in the full isolating region210indicated by a heavily hatched area in FIG.11.

Next, the whole area is covered by the field insulating film213(SiO2film) through a CVD process. Then, the field insulating film213is planarized by a CMP (Chemical Mechanical Polishing). Here, the Si3N4film206acts as a stopper layer.FIGS. 13Ato13C are cross sectional views at this time along dashed lines Y-Y′, X1-X1′ and X2-X2′, respectively. The field insulating film213in the full isolating region210is in contact with the buried insulating film202and a side of the transistor active region209, and extends over the carrier path208to form the partial isolating region211.

As described above, in the SOI transistor according to the present embodiment, device isolation is achieved without using a LOCOS region or an STI. Instead, the field insulating film213is “elevated” over the carrier path208. Hence, thickness of the carrier path208in the partial isolating region211is substantially the same as that of the SOI layer203in the transistor active region209and the body contact region212as shown inFIGS. 13Ato13C. Therefore, the carrier path208is effective in avoiding the floating body effects even in the case of a very thin SOI layer203. Moreover, the full isolating region210is provided in contact with a side of the transistor active region209(see FIG.11). Thus, the leak current and the parasitic capacitance are kept low between the transistor active region209and the carrier path208. Also, the edge of the field insulating film213reflects the vertical edge of the transistor active region209formed by RIE (seeFIGS. 10Ato10C). Thus, the edge of the field insulating film213is formed to be steep and self-align with the edge of the active region209. Also, the field insulating film213is formed and processed while the transistor active region209is covered by the mask. Therefore, the SOI layer203in the transistor active region209is not damaged during the device isolation process.

Next, the Si3N4film206is removed by a wet etching using heated phosphoric acid or a dry etching such as an RIE. Here, it is preferable to carry out the etching under a condition that the Si3N4film206and the field insulating film213are etched at a same etching rate, so that the top of the first polysilicon layer205and the top of the field insulating film213align with each other. In the body contact region212, the first polysilicon layer205is also removed. FIGS.14A to14C are cross sectional views at this time along dashed lines Y-Y′, X1-X1′ and X2-X2′, respectively.

The following steps will be described with reference toFIGS. 15 and 16Ato16C.FIG. 15is a plan view showing a structure of the semiconductor device.FIGS. 16Ato16C are cross sectional views along dashed lines Y-Y′, X1-X1′ and X2-X2′ inFIG. 15, respectively.

A second polysilicon layer214(corresponding to the upper gate electrode layer214) is formed over the first polysilicon layer205. Then, the first and second polysilicon layers in a predetermined area are removed by an etching process such as an RIE by using a resist as a mask. A gate electrode222is obtained, which is composed of the lower gate electrode layer205and the upper gate electrode layer214. Here, the upper gate electrode layer214is designed to cover at least a part of the region where the transistor active region209is connected to the partial isolating region211(see FIGS.15and16A).

As described above, the second polysilicon layer214is formed after the first polysilicon layer205is planarized. Therefore, material for the gate electrode (the first polysilicon layer205, the second polysilicon layer214or a dummy gate electrode layer) has a planar surface. Also, since the edge of the field insulating film213is formed to be substantially vertical unlike in the case shown inFIGS. 2C and 3C, the bottom surface of the material is also planar. Therefore, the gate electrode222can be formed without any difficulty, because the top and bottom surfaces of the material are planar and an over etching is not caused in forming the gate electrode222through the lithography and the RIE.

Next, impurity is heavily introduced into the SOI layer203of the transistor active region209through an ion implantation process by using the gate electrode222and the field insulating film213as a mask, to form the source/drain regions215(see FIG.16B). Also, impurity with a different conductivity type from that of the source/drain regions215is heavily introduced into the SOI layer203in the body contact region212through an ion implantation process, to form the heavily doped layer216(see FIG.16C). Next, the gate side wall217, the silicide layers218, the interlayer insulating layer219, the contacts220and the wiring223are formed according to normal processes. In this way, the semiconductor device shown inFIGS. 6 and 7Ato7C is obtained.

In the manufacturing method mentioned above, a SiO2film231can be formed successively after forming the Si3N4film206which is the top layer of a CMP mask in FIG.8. In this case, the structures shown inFIGS. 8 and 10Bare changed to structures shown inFIGS. 17A and 17B, respectively, and the top layer of the CMP mask is the SiO2film231. The SiO2film231is effective to prevent the Si3N4film206from being etched due to difference in the etching selection rate at the time of the etching for forming the full isolating region210through the opening area221indicated by the dashed rectangular in FIG.9. The SiO2film231is removed together at the time when planarizing the field insulating film213by the CMP (seeFIGS. 14Ato14C).

The material of the upper gate electrode layer214and the material of the lower gate electrode layer205may be the same and different. For example, both the upper and lower gate electrode layers can be made of the same material such as polysilicon, silicon germanium, metal silicide, metal and so on. The upper and lower gate electrode layers can be made of respective different conductive materials such as polysilicon, silicon germanium, metallic silicide, metal and so on. In a typical example, the lower gate electrode layer is made of polysilicon or polysilicon-germanium which has a high selective etching ratio to the gate insulating film and has a great processability. The upper gate electrode layer is made of metal or metallic silicide such as tungsten silicide, TiN, cobalt silicide which have low resistivity. This combination has an advantage of the great processability and the low resistivity. Also, the lower gate electrode layer can be made of semiconductor, semiconductor silicide, metallic nitride, metallic compound, metal and so on such as TiN, MoN, WN, platinum silicide, erbium silicide, silicon germanium mixed crystal, germanium and the like for the purpose of controlling gate work function. The upper gate electrode layer can be made of material with low resistivity such as metallic silicide and metal different from the material of the lower gate electrode layer. Also, the upper and lower gate electrode layers can have respective multiple-layers composed of conductive materials such as polysilicon, silicon germanium, metallic silicide, metal and so on. In a typical example, the upper gate electrode layer has a structure including a polysilicon layer and a silicide layer of cobalt silicide, nickel silicide and the like formed on the polysilicon layer. Also, another typical example is that a bottom portion of the lower gate electrode layer is made of semiconductor, semiconductor silicide, metallic nitride, metallic compound, metal and so on such as TiN, MoN, WN, platinum silicide, erbium silicide, silicon germanium mixed crystal, germanium and the like for the purpose of controlling gate work function. When the lower gate electrode layer is not made of polysilicon, the CMP mask (for example, indicated by numerals205and206inFIGS. 13A to13C) used in the CMP process is a multiple-layer film composed of a Si3N4film as a top layer and a material layer other than polysilicon as a second layer under the top layer. Also, in the process shown inFIG. 17, the CMP mask is a multiple-layer film composed of a SiO2film as a top layer, a Si3N4film as a second layer under the top layer and a material layer other than polysilicon as a third layer under the second layer.

The process of removing the SOI layer203to form the full isolating region210(seeFIGS. 11 and 12Ato12C) can be carried out at any stage after providing the transistor active region209(FIGS. 9 and 10Ato10C).FIGS. 18A and 18Bshow an example of the other method for forming the full isolating region210. After forming the structure shown inFIGS. 10Ato10C, the field insulating film213is formed and then planarized through a CMP. After that, a resist pattern232having the opening area221indicated by a dashed rectangular inFIG. 9is formed as shown in FIG.18A. The field insulating film213, the gate insulating film204, and the SOI layer203are removed by using the resist pattern232and the Si3N4film206as a mask to form the full isolating region210, as shown in FIG.18B. After that, an insulating film (SiO2) is formed again through a CVD process, and a second CMP is carried out, to obtain the same structure as in FIG.13B.

Similarly,FIGS. 19A and 19Bshow another example of the method for forming the full isolating region210. After forming the source/drain regions215, the silicide layers218, the upper and lower gate electrode layers205and214, and the gate side wall217in the transistor active region209, the interlayer insulating film219is formed and then planarized through a CMP. After that, a resist pattern232having the opening area221indicated by a dashed rectangular inFIG. 9is formed. The interlayer insulating film219, the field insulating film213, the gate insulating film204, and the SOI layer203are removed by using the resist pattern232and the silicide layers218as a mask to form the full isolating region210, as shown in FIG.19A. The interlayer insulating film219is formed and planarized again. Then, the contacts220and the wirings223are formed, to obtain a structure as shown in FIG.19B. In these manufacturing methods, the full isolating region210is formed after the formation and planarization of the field insulating film213or the interlayer insulating film219, and the manufacturing methods have an advantage of an excellent resist pattern because the resist pattern232is formed on the planar surface.

Also, the first polysilicon layer205can be removed after the structure shown inFIGS. 14A and 14Bis obtained. Or, the first polysilicon layer205can be removed after the field insulating film213is planarized and then the Si3N4film206and the field insulating film213is etched back. In this case, a new material for the gate electrode is deposited again and then processed to form the gate electrode222. The formation of the second polysilicon layer214can be omitted. The first polysilicon layer205formed in the step shown inFIG. 8is not used as the material for the gate electrode. Therefore, the first polysilicon layer205can be substituted by a layer of other material such as an insulating film. The double-layer of the polysilicon layer205and the Si3N4film206inFIG. 8can be substituted by a single-layer of the Si3N4film206. Moreover, before depositing the new material for the gate electrode, the gate insulating film204formed inFIG. 8can be removed and then a new gate insulating film can be formed again. After all, the gate electrode of the accomplished transistor does not become the double-layer gate electrode as inFIG. 7Bbut becomes a single-layer gate electrode233as shown in FIG.20.

Also, after the structure shown inFIGS. 14A and 14Bis obtained and the second polysilicon layer214is formed on the first polysilicon layer205, a new Si3N4film can be formed on the second polysilicon layer214. In this case, the polysilicon layers205and214are first processed in the similar way as in FIG.16B. After that, the interlayer insulating film219is formed and then planarized through a CMP by using the new Si3N4film as a mask. Then, the new Si3N4film and the first and second polysilicon layers205and214are removed, to obtain a cavity within the interlayer insulating film219. In addition to that, the gate insulating film204can be removed too. After that, a new gate electrode or a new gate insulating film and a new gate electrode are formed in the cavity. Also in this case, the gate electrode of the accomplished transistor does not become the double-layer gate electrode as inFIG. 7Bbut becomes a single-layer gate electrode233as shown in FIG.20.

FIG. 21is a plan view showing a structure of a semiconductor device according to a second embodiment of the present invention (corresponding to the structure inFIG. 11according to the first embodiment).FIGS. 22A and 22Bare cross sectional views along a dashed line Y-Y′ inFIG. 21, showing two examples according to the present embodiment.

The structure in the present embodiment is essentially the same as that in the first embodiment, except for the partial isolating region211. As shown inFIG. 21, a lightly doped region234is formed in the carrier path208next to the transistor active region209, in which the impurity density is lower than that in the carrier path208. The impurity density in the lightly doped region234can be higher and lower than that in the transistor active region209. Therefore, when the impurity density in the transistor active region209is lower than that in the carrier path208, the impurity density in the lightly doped region234can be the same as that in the transistor active region209, as shown in FIG.22A.FIG. 22Bshows another example of the present embodiment, in which a lightly doped layer235is formed in the lightly doped region234. The impurity density in the lightly doped layer235is lower than that in the carrier path208and is different from that in the transistor active region209. The lightly doped region234is effective in reducing leak current and parasitic capacitance between the source/drain regions215in the transistor active region209and the carrier path208in the partial isolating region211.

The lightly doped layer235can be formed by introducing the impurity in a predetermined region of the SOI layer203by the use of an appropriate resist pattern. It is also possible to set an opening of a photo resist for introducing the impurity to form the carrier path208apart from the transistor active region209.

FIGS. 23A and 23Bshow other methods for manufacturing the semiconductor devices shown inFIGS. 22A and 22B, respectively. Both figures show a structure corresponding to the structure shown inFIG. 10Aaccording to the first embodiment. The resist207inFIG. 10Ais removed before introducing the impurity to form the carrier path208. After that, a side wall236made of an insulating film such as SiO2is formed through a CVD process and an etch back process. Then, the carrier path208is formed by introducing the impurity through an ion implantation and the like by using the Si3N4film206and the side wall236as a mask (see FIGS.22A and23A). Also, it is possible to introduce the impurity into the SOI layer203through an ion implantation and the like to form the lightly doped layer235by the use of the Si3N4film206as a mask, before forming the side wall236. After that, the side wall236is formed and then the impurity is introduced to form the carrier path208(see FIGS.22B and23B). In any case, the transistor active region209and the carrier path208can be formed to be exclusive with each other as in the first embodiment, which is one of characteristics of the present embodiment. When manufacturing a CMOS (Complementary Metal Oxide Semiconductor), the lightly doped layer235and the carrier path208are formed differently in an n-channel transistor and a p-channel transistor. In this case, the impurity is introduced into one transistor, while the other transistor is covered with a resist mask. It should be noted that the side wall236can be made of other materials such as Si3N4film, amorphous carbon, amorphous carbon fluoride, BCB (benzocyclobutene) and so on.

In the first and the second embodiment, the full isolating region210is formed contiguous not only to two sides of the source/drain regions215parallel to the dashed line Y-Y′ but also to a part of two sides of the transistor active region209parallel to the dashed line X1-X1′ (see FIGS.6and21). However, it is also possible to form the full isolating region210contiguous to at least a part of sides of the source/drain regions215.

FIGS. 24A and 24Bshow examples of such a semiconductor device according to a third embodiment of the present invention. InFIG. 24A, for example, the full isolating region210(indicated by a heavily hatched area) is formed contiguous only to a first side of the source region215parallel to the dashed line Y-Y′ and a second side of the drain region215parallel to the dashed line Y-Y′. InFIG. 24B, the full isolating region210is formed contiguous to only a part of the first and second sides of the source/drain regions215parallel to the dashed line Y-Y′.

The leak current and the parasitic capacitance between the transistor active region209and the carrier path208are inversely proportional to length of the sides of the transistor active region209(source/drain regions215) to which the full isolating region210is contiguous. Therefore, the larger the area of the sides of the transistor active region209contiguous to the full isolating region210becomes, the more the leak current and the parasitic capacitance are reduced. In particular, the leak current and the parasitic capacitance are reduced effectively, when more than half of the first and second sides of the source/drain regions215parallel to the dashed line Y-Y′ is contiguous to the full isolating region210. Also, the full isolating region210can be formed contiguous to a part of only one side of the source/drain regions215parallel to the dashed line Y-Y′. In this case, another side of the source/drain regions215is not contiguous to the full isolating region210. In particular, the present invention is still effective even when the full isolating region210is formed only on the second side of the drain region215. It should be noted that, in the present embodiment, the lightly doped region234can be formed as in the second embodiment.

FIGS. 25A and 25Bshow a structure of a semiconductor device according to a fourth embodiment of the present invention.FIGS. 25A and 25Bare plan views corresponding toFIGS. 9 and 11in the first embodiment, respectively. As shown inFIG. 25A, in the present embodiment, an opening area221can be provided in “U” shape. Thus, the full isolating region210(indicated by a heavily hatched area) can be formed to be contiguous further to whole area of one side of the transistor active region209parallel to a dashed line X1-X1′, as shown in FIG.25B. The transistor active region209is connected to the body contact region212through the carrier path208contacting another side of the transistor active region209parallel to the dashed line X1-X1′.

FIG. 26Ais a cross sectional view along a dashed line Y-Y′ in FIG.25B.FIG. 26Bis a cross sectional view showing a structure of the completed semiconductor device according to the present embodiment (corresponding to the structure shown inFIG. 7Aaccording to the first embodiment). As shown inFIG. 26B, the channel region in the transistor active region209is exposed to the full isolating region210on a side parallel to the dashed line X1-X1′ in FIG.25B. It may be possible to add a process before depositing the field insulating film213(seeFIG. 26A) that modifies the property of the side of the transistor active region209through a thermal oxidation process and hence reduces the interface state.

FIG. 27Ais a plan view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.FIG. 27Bis a cross sectional view along a dashed line X1-X1′ in FIG.27A. In the present embodiment, the semiconductor device includes a plurality of SOI transistors (a plurality of transistor active regions209), each of which is similar to the SOI transistor described in the previous (first to fourth) embodiments. In this case, the plurality of SOI transistors are disposed next to each other, and only the full isolating region210exists between two adjacent transistor active regions209(source/drain regions).

A semiconductor device according to a sixth embodiment of the present invention will be described with reference toFIGS. 28Ato28G. In the semiconductor devices described in the first to fifth embodiments, the transistor active region209should be connected to at least one body contact region212through the carrier path208. A unit structure composed of a transistor active region (SOI transistor) and a body contact region can be isolated by the full isolating region (a block isolating film)210as shown inFIGS. 28Ato28G. The unit structure isolated by the full isolating region210can be composed of a plurality of transistor active regions209and one body contact region212. The unit structure can be composed of one transistor active region209and a plurality of body contact regions212(see FIGS.28B and28C). The unit structure can be composed of a plurality of transistor active regions209and a plurality of body contact regions212(see FIGS.28A and28D).

In the present embodiment, a plurality of FET transistors can be formed within one block surrounded by the full isolating region (a block isolating film)210as shown in FIG.28A. An n-channel transistor and a p-channel transistor can be formed in respective blocks surrounded by the full isolating region210. Also, a plurality of n-channel transistors and a plurality of p-channel transistors can be formed in respective blocks surrounded by the full isolating region210(see FIG.28A). For example, blocks241and242inFIG. 28Acan be for the plurality of n-channel transistors and the plurality of p-channel transistors, respectively. A part of the full isolating region210can be formed contiguous to a side of the source/drain regions215to determine the block containing a plurality of transistors (see FIG.28D). Also, a part of the full isolating region210which determines the block containing one transistor can be formed contiguous to a side of the source/drain regions215(seeFIGS. 28C,28E,28F and28G). Also, one block surrounded by the full isolating region210can contain an n-channel transistor and a p-channel transistor together, if the separation between the n-channel transistor and the p-channel transistor is enough to avoid a short circuit in the carrier paths in the both transistors. It should be noted that an arbitrary positional relationship is possible between the gate electrode222and the body contact region212. That is to say, the body contact region212may or may not be located on the extension of the gate electrode222.

Modifications of the present invention will be described below, which can be adopted in any one of the above-mentioned embodiments. The buried insulating film202, normally made of SiO2, may be made of other insulators such as Si3N4and porous SiO2. Also, a cavity can be formed in the buried insulating film202. Also, the buried insulating film202can be multi-layer film composed of a plurality of insulators. For example, the buried insulating film202can be double-layer film composed of a top Si3N4layer and a bottom SiO2layer, or can be triple-layer film composed of a top SiO2film, a middle Si3N4film and a bottom SiO2film. The thickness of the buried insulating film202is generally in a range from 80 nm to 1 μm. However, the thickness can be out of this range.

The SOI substrate may not have the substrate. That is to say, the SOI substrate may have a structure including only an insulating film and a semiconductor layer on the insulating film, such as an SOS (Silicon on Sapphire) substrate and a semiconductor layer on a glass substrate. Also, instead of the SOI layer203, a semiconductor layer made of other than silicon can be used. Also, a combination of more than two kinds of semiconductors is possible for the semiconductor layer. The thickness of the SOI layer203in a full-depletion SOI MOSFET is typically in a range from 10 nm to 50 nm. The SOI layer203can be thicker in cases of partial-depletion SOI MOSFET and a transistor with a long gate length (typically more than 0.35 μm). Also, the SOI layer203can be thinner in a case where the gate length is short and the short channel effect is to be restrained. It should be noted that when the material and size of the structures inFIG. 1are changed, the corresponding structures in the following processes should be considered to have the similar change in the material and the region. Also, when the material and size of the structures in a figure other thanFIG. 1are changed, the corresponding structures in the following processes should be considered to have the similar change in the material and the region.

An impurity density in the surface of the SOI layer203in both the source/drain region and the body contact region is typically in a range from 5×1018cm−3to 1×1021cm−3, and more typically in a range from 3×1019cm−3to 1×1020cm−3. The impurity is introduced by ion implantation or vapor-phase diffusion. The dose at the time of the ion implantation is typically in a range from 1×1014cm−2to 3×1015cm−2, and more typically in a range from 3×1014cm−2to 1×1015cm−2.

The impurity which is to be introduced to the source/drain regions215should have n-type conductivity type in a case of an n-channel transistor, and have p-type conductivity type in a case of a p-channel transistor. The impurity which is to be introduced to the body contact region212and the partial isolating region211(carrier path208) should have p-type conductivity type in a case where the regions are connected to an n-channel transistor, and have n-type conductivity type in a case where the regions are connected to an p-channel transistor. As a result, the source/drain regions215in the n-channel transistor and the p-channel transistor are formed to be n-type and p-type, respectively. The body contact region212and the carrier path208connected to the n-channel transistor and those connected to the p-channel transistor are formed to be p-type and n-type, respectively.

In the ion implantation process in any of the above-mentioned embodiments, ion species such as B+, BF2+and In+are used for forming the p-type region (including p+-type and p−-type). Also, ion species such as As+, P+and Sb+are used for forming the n-type region (including n+-type and n−-type). It is also possible to use any other ions with which the p-type region or the n-type region can be formed. The ion species is not limited to such ion species having monovalent charge as mentioned above, but can have divalent charges or more. It is also possible to implant a cluster composed of impurity with respective conductivity types. Also, the ion implantation can be replaced with another impurity introducing method such as plasma doping, vapor-phase diffusion, solid-phase diffusion and so forth.

The gate insulating film204, which is formed by thermal oxidation of silicon in the above-mentioned embodiments of the present invention, can be replaced with a SiO2film formed by other methods such as radical oxidation method for example. Also, the gate insulating film204can be replaced with an insulating film other than a SiO2film. Also, the gate insulating film204can be replaced with a multi-layer film composed of a SiO2film and another insulating film or a multi-layer film composed of other insulating films. Also, the gate insulating film204can be replaced with a material with high dielectric constant such as Ta2O5and the like. Such a gate insulating film is preferable because parasitic capacitance between the gate and the semiconductor layer in the isolating region becomes relatively lower than the gate capacitance, if the dielectric constant of the gate insulating film204is higher than that of the field insulating film213. The gate insulating film204can be a laminated film or a film whose composition varies in the vertical direction. Such a gate insulating film is also preferable because parasitic capacitance between the gate and the semiconductor layer in the isolating region becomes relatively lower than the gate capacitance, if the dielectric constant of a part of the gate insulating film204is higher than that of the field insulating film213.

The ion energy in the ion implantation process is typically in a range from 0.5 KeV to 20 KeV. Here, the ion energy can be lower in a case when the impurity is particularly desired to be distributed in a shallow region of the SOI layer203. Also, the ion energy can be higher in a case when the impurity is desired to be distributed in a deep region of the SOI layer203, for example, in a case when the SOI layer203is thick. The activation of the impurity introduced through the ion implantation is carried out by a heating process such as annealing by a normal electric furnace or lamp annealing.

When the impurity is introduced into the channel region in any of the above-mentioned embodiments, the ion implantation is carried out after forming a sacrificial oxide film. A heating process for activating the implanted ion can be carried out immediately after the ion implantation or can be carried out together with a heating process for activating the impurity introduced into the source/drain region. The impurity density is typically in a range from 0 to 2×1018cm−3when the thickness of the SOI layer203is 50 nm. The typical density can be in a lower range when the SOI layer203is thicker than 50 nm and can be in a higher range when the SOI layer203is thinner than 50 nm. For example, when the SOI layer203is 10 nm thick, the impurity density is typically in a range from 0 to 5×1018cm−3. Also, the different density can be possible if it is necessary to meet the requirement from the setting the threshold voltage. Also, when a material other than polysilicon is used for the gate electrode, the setting of the threshold voltage is independent of the introduction of the impurity. Therefore, the introduction of the impurity can be omitted.

When the material of the gate electrode is a semiconductor such as polysilicon-germanium mixed crystal and the like, the impurity can be introduced into the gate at the same time when the impurity is introduce into the source/drain region or the material of the gate electrode is deposited. Also, the impurity can be introduced into the gate after depositing the material of the gate electrode and before processing the material to form the gate electrode.

If the impurity is introduced into the material of the gate electrode before forming the gate electrode in manufacturing a CMOS, and if the conductivity type of the gate electrode of an n-channel transistor is different from that of a p-channel transistor, the impurities can be introduced by using an appropriate resist mask into respective regions where the n-channel and the p-channel transistors are to be formed. Here, the impurities have respective conductivity types. Generally, the gate of the n-channel transistor includes the n-type impurity and the gate of the p-channel transistor includes the p-type impurity. The optimum etching condition for forming the gate electrode may differ depending on the conductivity type (n-type or p-type) of the impurity which is introduced into the material of the gate electrode. In this case, forming the gate electrode of the n-channel transistor and forming the gate electrode of the p-channel transistor can be carried out in a different process by using an appropriate resist mask.

The impurity can be introduced into the gate electrode before etching the deposited material of the gate electrode through RIE to form the gate electrode or after the etching process or before and after the etching process. The material of the gate electrode should have the appropriate conductivity type and the work function necessary for setting the threshold voltage of the transistor. The material of the upper gate electrode layer should have the appropriate conductivity type.

A silicon layer (SOI layer) is used as the semiconductor layer in the above-mentioned embodiments of the present invention. The semiconductor layer can be made of a material other than silicon. Also, the semiconductor layer can be made of a combination of silicon and a material other than silicon.

It is preferable that the SOI layers203in the transistor active region209, the carrier path208and the body contact region212have substantially the same thickness. The difference in the thickness of the SOI layer203between the three regions should be a minute difference caused unavoidably in the manufacturing processes such as gate oxidation and etching of the insulating (SiO2) film on the SOI layer203. No intended process is included in the present invention, in which any one of the SOI layers203of the transistor active region209, the carrier path208and the body contact region212is formed to be thinner than the others.

From the viewpoint of the ion implantation, it is preferable not to amorphize the whole SOI layer203. That is to say, it is preferable that the implanted ion does not distribute all over the thickness of the SOI layer203. Therefore, the ion injection energy is controlled such that the ion penetrates into less than 70-80% of the thickness of the SOI layer203.

Also, it is preferable that the top of the gate electrode on the transistor active region209is substantially aligned with that on the partial isolating region211. From the viewpoint of the stability of lithography process and gate etching process, the step is preferably within 40 nm, and more preferably within 20 nm. In order to attain the predetermined step, it is preferable to control the CMP condition and the thickness of the material of the gate electrode.

It will be obvious to one skilled in the art that the present invention may be practiced in other embodiments that depart from the above-described specific details. The scope of the present invention, therefore, should be determined by the following claims.