Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process

Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth in recent years. Technological advances in IC materials and design have produced various types of ICs that serve different purposes. The fabrication of some types of ICs may require forming a III-V family layer on a substrate, for example forming a III-V family layer on a substrate. These types of IC devices may include, as examples, light-emitting diode (LED) devices, radio frequency (RF) devices, and high power semiconductor devices.

Traditionally, manufacturers have formed the III-V family layer on a sapphire substrate. However, sapphire substrates are expensive. Thus, some manufacturers have been exploring forming III-V family layers on a silicon substrate, which is cheaper. However, existing methods of forming a III-V family layer on a silicon substrate may suffer from various drawbacks. One of these drawbacks involves outgas sing of the III-V family layer in one or more fabrication stages. The outgas sing of the III-V family layer may result in contamination of the silicon substrate. Therefore, existing fabrication processes may need to form a protective coating layer around the silicon substrate to prevent such contamination. The formation of the protective coating layer requires additional fabrication processes and therefore lengthens fabrication time and increases fabrication costs.

Therefore, while existing methods of forming III-V family layers on silicon substrates have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

DETAILED DESCRIPTION

Illustrated inFIG. 1is a flowchart of a method10for fabricating a semiconductor device according to various aspects of the present disclosure. Referring toFIG. 1, the method includes block15, in which a silicon nitride layer is formed over a front side and a back side of a silicon substrate. A first segment of the silicon nitride layer is formed over the front side of the substrate. A second segment of the silicon nitride layer is formed over the back side of the substrate. The method10includes block20, in which the first segment of the silicon nitride layer is patterned, thereby forming a patterned first segment of the silicon nitride layer. The method10includes block25, in which a plurality of recesses is etched in the substrate from the front side. The patterned first segment of the silicon nitride layer serves as an etching mask during the etching. The method10includes block30, in which a silicon oxide layer is formed over the front side of the substrate. The silicon oxide layer fills the recesses. The method10includes block35, in which the patterned first segment of the silicon nitride layer is removed without removing the second segment of the silicon nitride layer.

It is understood that additional processes may be performed before, during, or after the blocks15-35shown inFIG. 1to complete the fabrication of the semiconductor device, but these additional processes are not discussed herein in detail for the sake of simplicity.

FIGS. 2 to 10are diagrammatic fragmentary cross-sectional side views of a semiconductor device at various fabrication stages according to embodiments of the method10ofFIG. 1. It is understood thatFIGS. 2 to 10have been simplified for a better understanding of the inventive concepts of the present disclosure.

Referring toFIG. 2, a silicon wafer40is provided. The silicon wafer40may also be referred to as a silicon substrate40. The silicon wafer40has a side or a surface50, and a side or a surface60that is located opposite the side50. In the illustrated embodiment, the side or surface50may be referred to as a front side or front surface, and the side or surface60may be referred to as a back side or back surface.

A dielectric layer70is formed on the side50of the silicon wafer40. In an embodiment, the dielectric layer70includes a silicon oxide material and may be referred to as a pad oxide layer. The dielectric layer70has a thickness80(measured vertically inFIG. 2). In an embodiment, the thickness80is in a range from about 5 nanometers to about 20 nanometers.

Referring now toFIG. 3, a dielectric coating layer90is formed around the silicon wafer40. In an embodiment, the dielectric coating layer90includes a silicon nitride material. The dielectric coating layer90is coated completely around the silicon wafer40, such that the silicon wafer40is surrounded by the dielectric coating layer90. As illustrated inFIG. 3, a portion or segment90A of the dielectric coating layer90is formed over the surface50(and more specifically, on the dielectric layer70) of the silicon wafer40, and a portion or segment90B of the dielectric coating layer90is formed over the surface60of the silicon wafer40. In an embodiment, the dielectric coating layer90is formed by a low pressure chemical vapor deposition (LPCVD) process100. The dielectric coating90has a thickness110. In an embodiment, the thickness110is in a range from about 5 nanometers to about 20 nanometers.

Referring now toFIG. 4, a patterning process120is performed to pattern the segment90A of the dielectric coating layer90into a patterned dielectric hard mask130. The patterning process120may be carried out using a photolithography process known in the art, which may include one or more masking, exposing, developing, baking, and rinsing processes (not necessarily in this order). For example, a patterned photoresist mask may be formed, and the photoresist mask may be used to pattern the segment90A into the dielectric hard mask130. The dielectric hard mask130contains a plurality of openings. Openings150,151, and152are shown herein as examples.

Referring now toFIG. 5, an etching process160is performed to extend the openings150-152further into the silicon wafer, thereby forming a plurality of recesses150A-152A. The recesses150A-152A may be referred to as trenches. The etching process160is performed using the dielectric hard mask130as an etching mask. The etching process160may include a wet etching process or a dry etching process.

Referring now toFIG. 6, a deposition process170is performed to fill the recesses150A-152A with a dielectric material180. In an embodiment, the deposition process170includes a high-density plasma (HDP) deposition process. In other embodiments, the deposition process170may include other deposition techniques known in the art, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable technique. In an embodiment, the dielectric material180includes silicon oxide. The dielectric material180completely fills the recesses150A-152A. Portions of the dielectric material180also cover surfaces of the dielectric hard mask130.

Referring now toFIG. 7, a polishing process190is performed on the dielectric material180. In an embodiment, the polishing process190includes a chemical-mechanical-polishing (CMP) process. In an embodiment, the CMP process has a relatively high etching selectivity between a silicon oxide material and a silicon nitride material. For example, the etching selectivity between silicon oxide and silicon nitride may be greater than about 10:1. Generally, etching selectivity refers to the respective rates at which different materials are removed. A high etching selectivity results in a faster removal of one material in comparison with another material. The etching selectivity can be tuned by factors such as CMP slurry selection and downward pressure application (i.e., force applied to a CMP polishing head).

Here, the CMP process may be tuned in a manner such that silicon oxide (e.g., the dielectric material180) is polished away while silicon nitride (e.g., the dielectric hard mask130) substantially remains on the wafer. The polishing process190may be performed until a substantially smooth and planarized surface is achieved. The portions of the dielectric material180remaining in the recesses150A-152A form shallow trench isolation (STI) structures200-202.

Referring now toFIG. 8, a removal process210is performed to remove the dielectric hard mask130(which includes patterned portions of the segment90A of the dielectric layer90) from the silicon wafer40. In an embodiment, the removal process210involves a single wafer dielectric material removal process. In more detail, a plurality of additional silicon wafers similar to the silicon wafer40may be provided. Each of these silicon wafers has undergone similar fabrication processes as the silicon wafer40. To remove the dielectric hard masks (containing silicon nitride in the present embodiment), the single wafer dielectric material removal process is performed by applying a chemical solution from the front side to each individual wafer's dielectric hard mask. In an embodiment, the chemical solution includes hot phosphoric acid. The chemical solution is sprayed onto one silicon wafer, and then the next. Since the chemical solution is sprayed from the front side, the removal process210does not affect the segment90B of the dielectric coating layer. Rather, only the remaining portions of the segment90A of the dielectric coating layer—the dielectric hard mask130—is removed by the removal process210.

Meanwhile, the other portions of the dielectric coating layer90, for example the segment90B covering the back side60of the silicon wafer, remain intact and are largely unaffected by the single wafer dielectric material removal process. Hence, the silicon wafer40is still coated with the dielectric coating layer90on its back surface60as well as its side surfaces even after the single wafer dielectric material removal process is performed.

In comparison, traditional fabrication processes typically employ a batch removal approach to remove a dielectric hard mask. Namely, a batch of wafers may be placed inside a container containing a chemical solution, and the chemical solution effectively removes the dielectric coating layer from all surfaces or sides of these wafers. In other words, the batch removal process removes the dielectric coating layer segment on the front side of each wafer, as well as the dielectric coating layer segments on the back side of each wafer. Therefore, it can be seen that one difference between the traditional fabrication processes and the one discussed above according to the various aspects of the present disclosure is the following: the dielectric coating layer is completely removed for the traditional fabrication processes, whereas the dielectric coating layer90is only partially removed for the embodiments disclosed herein.

After the dielectric hard mask130is removed from the front side50of the silicon wafer40, additional polishing processes may be performed to ensure that the front side surface of the silicon wafer remains smooth and planarized. In some embodiments, the pad oxide layer70may also be removed.

FIGS. 2-8and the associated descriptions above disclose a first fabrication flow according to the various aspects of the present disclosure. A second fabrication flow according to the various aspects of the present disclosure is illustrated inFIG. 9. For the sake of clarity and consistency, similar components and processes are labeled the same throughoutFIGS. 2-9. In the second fabrication flow, processes substantially identical to those illustrated inFIGS. 2-6are performed to the silicon wafer40as well. That is, a dielectric coating layer90is formed around the silicon wafer40, the portion of the dielectric coating layer90formed over the front side50of the silicon wafer40is patterned into a dielectric hard mask130having openings, trenches are etched into the silicon wafer40from the front side50while using the dielectric hard mask130as an etching mask, and a dielectric material is deposited over the front side50of the silicon wafer40, such that the trenches are filled with the dielectric material.

Referring now toFIG. 9, at this stage of fabrication, instead of performing the polishing process190ofFIG. 7(where a high etching selectivity between silicon oxide and silicon nitride is used), a polishing process240is performed on the dielectric material180. In an embodiment, the polishing process240includes a CMP process with a relatively low etching selectivity between silicon oxide and silicon nitride, for example, an etching selectivity about 1:1. Thus, the silicon oxide material (e.g., the dielectric material180and the pad oxide layer70) and the silicon nitride material (e.g., the dielectric hard mask130) are removed at substantially the same rates. Therefore, the dielectric material180outside the recesses150A-152A (FIG. 5) are polished away at the same time that the dielectric hard mask130and the pad oxide layer70are polished away. The polishing process240stops when a silicon surface of the silicon wafer40is reached. The polishing process240forms STI structures200-202filling the trenches150A-152A. The front surface50of the silicon wafer40is substantially smooth and planarized after the completion of the polishing process240.

Since the polishing process240is configured to remove the dielectric hard mask130from the silicon wafer, no subsequent single wafer dielectric material removal process needs to be performed. That is, the silicon wafer40(as well as other similar silicon wafers) does not need to undergo a single wafer dielectric material removal process where a chemical solution (such as hot phosphoric acid) is sprayed onto the wafer surface from the front side for each individual wafer to remove the dielectric hard mask containing silicon nitride. Rather, the removal of the dielectric hard mask130can be carried out using the polishing process240. Hence, the polishing process240may also be referred to as a dielectric material removal process.

It can also be seen that the polishing process240does not affect the back side60of the silicon wafer40. The segment90B of the dielectric coating layer90still remains on the back side after the polishing process240is performed. Therefore, similar to the first fabrication flow discussed above, the second fabrication flow still involves removing only a portion of the dielectric coating layer90—the portion formed over the front side50of the silicon wafer.

The selective partial removal of the dielectric coating layer90according to the present disclosure (for example, either the first fabrication flow according toFIGS. 2-8or the second fabrication flow according toFIGS. 2-6and9) offers advantages over traditional fabrication processes. It is understood, however, that other embodiments may offer different advantages, and that no particular advantage is required for all embodiments. One advantage is that the present disclosure eliminates or bypasses many processing steps that are required by traditional fabrication processes.

In more detail, in the traditional fabrication processes, to prevent contamination caused by outgassing of a III-V family layer (formed on the silicon wafer in a later fabrication stage), a silicon nitride layer needs to be formed on the back side of the silicon wafer. Thus, after the batch dielectric material removal process (where all of the dielectric coating layer is removed from the silicon wafer), the silicon wafer is turned over (flipped upside down). A cleaning process is then performed to clean the back surface of the silicon wafer. After the cleaning, a silicon nitride layer is formed on the back side of the silicon wafer. Thereafter, the silicon wafer is turned over again so that front side processing of the silicon wafer may continue, where one of the front side processes includes the formation of a III-V family layer. These extra fabrication steps (e.g., flipping the wafer over, cleaning the back side, forming a silicon nitride layer, flipping the wafer back) prolong fabrication time, waste fabrication resources, and increase fabrication costs.

In contrast, the first fabrication flow and the second fabrication flow of the present disclosure each bypass these additional fabrication processes required in traditional fabrication processes. The single wafer dielectric material process of the first fabrication flow and the polishing process of the second fabrication flow each selectively remove the portion of the dielectric coating layer from the front side of the silicon wafer, while leaving the portion of the dielectric coating layer on the back side of the silicon wafer intact. In this manner, the portion of the dielectric coating layer on the back side of the silicon wafer can serve as a protective mask to prevent contamination caused by III-V family layer outgas sing.

In other words, according to the present disclosure, the formation of a silicon nitride protective mask on the back side of the silicon wafer does not require a dedicated process. Instead, through calculated and carefully fabrication processing steps, remnants of the dielectric coating layer (which would have been completely removed by existing fabrication processes) can now be used as the protective silicon nitride layer on the back side of the silicon wafer. Consequently, processing steps such as wafer flipping, wafer back side cleaning, silicon nitride deposition on the wafer back side, and wafer flipping again may all be eliminated. The elimination of all these processing steps shortens fabrication time and reduces fabrication costs.

Another advantage offered by the embodiments disclosed herein is reduced risks of causing wafer damage during processing. It is understood that electronic circuit components may be formed on the front side of the silicon wafer. These electronic circuit components may include transistors, resistors, capacitors, and inductors, etc. In conventional fabrication processes, flipping the silicon wafer upside down (and then later back up again) may cause damages on the wafer, specifically damages to these electronic circuit components. For example, these damages may be caused by suboptimal handling of the wafer during the flipping processes. The damaged electronic circuit components may reduce yield, and may even result in scrapped silicon wafers. As such, these extra fabrication processes dedicated to the formation of a back side silicon nitride layer in a traditional fabrication process increases risk of wafer damage, and are therefore undesirable.

In comparison, the embodiments of the present disclosure need not flip the wafers upside down to form a protective silicon nitride layer on the back side of the silicon wafer. Therefore, the embodiments of the present disclosure reduce risks of wafer damage by eliminating unnecessary handling of the wafer during its fabrication.

It is understood that in some embodiments, the first fabrication flow and the second fabrication flow discussed above may be combined. For example, a low selectivity wafer polishing process may be performed, and thereafter a single wafer dielectric material removal process may be performed. This combined fabrication flow entails substantially the same advantages discussed above. Namely, it achieves the objective of providing a silicon nitride protective back side layer to prevent III-V family layer outgassing, while offering shortened process time and reduced fabrication costs, as well as decreased risks of wafer damage.

Additional fabrication processes may be performed to complete the fabrication of the semiconductor device discussed herein. For the sake of providing an example,FIG. 10illustrates the formation of a III-V family layer on the silicon wafer40. Referring toFIG. 10, a III-V family layer290is formed over the front side50of the silicon wafer40. The III-V family layer includes an element from a “III” family of the periodic table, and another element from a “V” family of the periodic table. For example, the III family elements may include: Boron, Aluminum, Gallium, etc, and the V family elements may include: Nitrogen, Phosphorous, Arsenic, etc. Thus, one example of a III-V family layer is a gallium nitride layer.

The III-V family layer290may be formed by one or more epitaxial-growth processes known in the art, which may be performed at high temperatures. In some embodiments, the high temperatures range from about 800 degrees Celsius to about 1400 degrees Celsius. Although not illustrated, it is understood that a buffer layer may be formed between the silicon wafer40and the III-V family layer290. It is further understood that a cladding layer (not illustrated herein) may be formed over the III-V family layer290to enhance its electrical properties.

Various types of semiconductor devices can be formed using a III-V family layer such as the III-V family layer290ofFIG. 10. For example, a high power semiconductor device320may be formed. The semiconductor device320includes the silicon wafer40and the III-V family layer290. The high power semiconductor device320also includes an additional III-V family layer340that is formed over the III-V family layer290. The III-V family layer340includes a different material composition than the III-V family layer290.

The high power semiconductor device320includes a transistor formed by a gate device360and source/drain regions370. The gate device360(or gate structure) is formed over the III-V family layer340, and source/drain regions370are formed in the III-V family layer340and partially in the III-V family layer290. The gate device360may include a gate dielectric component and a gate electrode component. The source/drain regions370may be formed by one or more doping or implantation processes. When the transistor device is turned on, a conductive channel is formed below the gate device360and between the source/drain regions370. An electrical current will flow in the conductive channel.

The high power semiconductor device320also includes an interconnect structure400formed over the aluminum III-V family layer340. The interconnect structure400includes a plurality of interconnect layers, also referred to as metal layers. Each metal layer contains a plurality of metal lines that route electrical signals. The metal layers are interconnected together by vias. Contacts are also formed over the gate device360and the source/drain regions370so that connections may be established with external devices. For the sake of simplicity, these metal lines, vias and contacts are not specifically illustrated inFIG. 10. Also, additional fabrication processes may be performed to finish the fabrication of the high power device320, such as passivation, testing, and packaging processes. These processes are also not shown or discussed herein for reasons of simplicity.

It is understood that the high power device320shown inFIG. 10and discussed above merely illustrates an example use of a III-V family layer formed over a silicon wafer. In other embodiments, the methods disclosed herein may be used to form hetero-structure devices, light-emitting diode (LED) devices, radio-frequency (RF) devices, and high electron mobility transistor (HEMT) devices. In fact, as long as it is desirable to form a III-V family layer on a silicon substrate, the method and structure disclosed by the present disclosure may be applied to achieve the various advantages discussed above.

One of the broader forms of the present disclosure involves a method. The method includes: forming a first dielectric layer over a first surface and a second surface of a silicon substrate, the first and second surfaces being opposite surfaces, wherein a first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate; forming openings that extend into the substrate from the first surface; filling the openings with a second dielectric layer; and removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.

Another of the broader forms of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a silicon nitride layer over a front side and a back side of a silicon substrate, wherein a first segment of the silicon nitride layer is formed over the front side of the substrate, and wherein a second segment of the silicon nitride layer is formed over the back side of the substrate; patterning the first segment of the silicon nitride layer, thereby forming a patterned first segment of the silicon nitride layer; etching a plurality of recesses in the substrate from the front side, wherein the patterned first segment of the silicon nitride layer serves as an etching mask during the etching; forming a silicon oxide layer over the front side of the substrate, the silicon oxide layer filling the recesses; and removing the patterned first segment of the silicon nitride layer without removing the second segment of the silicon nitride layer.

Still another of the broader forms of the present disclosure involves a method of fabricating a semiconductor device. The method includes: providing a plurality of silicon wafers; coating each of the wafers with a silicon nitride material; performing a patterning process from a front side of the wafers on the silicon nitride material to form a plurality of patterned silicon nitride masks; etching, through the patterned silicon nitride masks, a plurality of trenches in each of the wafers, wherein the etching is performed from the front side of the wafers; filling the trenches with a silicon oxide material; and removing the patterned silicon nitride masks by dispensing an acid from the front side to each individual wafer, wherein the removing is carried out in a manner such that the silicon nitride material coated around a back side of each wafer is not removed by the removing.