Multi-step gate structure and method for preparing the same

A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

BACKGROUND OF THE INVENTION

(A) Field of the Invention

The present invention relates to a multi-step gate structure and method for preparing the same, and more particularly, to a multi-step gate structure having an increased channel length by incorporating a semiconductor substrate with multi-step structure and method for preparing the same.

(B) Description of the Related Art

FIG. 1illustrates a metal-oxide-semiconductor field effect transistor (MOSFET)10according to the prior art. The transistor10is an important basic electronic device including a gate20consisting of a semiconductor substrate12, a gate oxide layer14and a conductive metal layer16, and two doped regions18serving as the source and the drain in the semiconductor substrate12at two sides of the gate20. The transistor10may further include a nitride spacer22positioned on the sidewall of the conductive metal layer16for isolating the conductive metal layer16from the other electronic devices on the semiconductor substrate12.

As semiconductor fabrication technology continues to improve, sizes of electronic devices are reduced, and the size and the channel length of the transistor10also decrease correspondingly. The transistor10has been widely used in the integrated circuit; however, the decreasing of the size and the channel length of the transistor10results in a serious interaction between the two doped regions18and a carrier channel24in the semiconductor substrate12under the gate oxide layer14such that the controlling ability of the conductive metal layer16on the switching operation of the carrier channel24is reduced, i.e., causes the so-called short channel effect, which impedes the functioning of the transistor10.

SUMMARY OF THE INVENTION

One aspect of the present invention provides a multi-step gate structure having an increased channel length by incorporating a semiconductor substrate with a multi-step structure and method for preparing the same, which can adjust the threshold voltage of a transistor using the multi-step gate structure by controlling the thickness of a gate oxide layer on each step surface of the multi-step structure or by controlling the dopant concentration and types of the dopants in the semiconductor substrate under the multi-step structure.

A multi-step gate structure according to this aspect of the present invention comprises a semiconductor substrate having a multi-step structure including at least a first depression and a second depression, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the thickness of the gate oxide layer on one step surface of the multi-step structure may be different from the thickness of the gate oxide layer on another step surface of the multi-step structure. In addition, the multi-step gate structure may comprise a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure.

Another aspect of the present invention provides a method for preparing a multi-step gate structure comprising the steps of forming a semiconductor substrate having a multi-step structure, performing a thermal oxidation process to form a gate oxide layer on the multi-step structure and forming a conductive layer on the gate oxide layer. The step of forming a semiconductor substrate having a multi-step structure forms a mask layer covering a predetermined portion of the semiconductor substrate, and the mask layer is used as a first etching mask in an etching process to remove a portion of the semiconductor substrate not covered by the first etching mask to form a first depression. Subsequently, a first spacer is formed on a sidewall of the first depression by deposition and etching processes, and the mask layer and the first spacer are used as a second etching mask in another etching process to remove a portion of the semiconductor substrate not covered by the second etching mask to form a second depression.

In addition, the step of forming a semiconductor substrate having a multi-step structure may further comprise a plurality of implanting processes to implant dopants into the semiconductor substrate under the multi-step structure, wherein the plurality of implanting processes may be performed with different dosages and different types of dopants. Particularly, the dopants used in the implanting processes are nitrogen-containing dopants selected from the group consisting of ions of nitrogen atom, nitrogen gas, nitrous oxide and nitric oxide, which can inhibit the reaction rate of the subsequent thermal oxidation process, i.e., can control the thickness of the gate oxide layer. Further, the plurality of implanting processes may use boron-containing dopants or phosphorous-containing dopants, which allows adjusting the threshold voltage of a transistor using the multi-step gate structure.

In comparison with the conventional gate having a horizontally positioned carrier channel with a channel length substantially equal to the lateral width of the gate, one embodiment of the present invention provides a multi-step gate structure having a channel length substantially equal to the summation of the lateral width and the vertical height of the multi-step gate structure. Obviously, the channel length of the multi-step gate structure is longer than that of the conventional gate, and the short channel effect can then be effectively solved. In addition, several implanting processes with different dosages and different types of dopants can be performed during the fabrication process of the multi-step structure to control the thickness of the gate oxide layer and the threshold voltage of a transistor using the multi-step gate structure.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2toFIG. 8illustrate a method for preparing a multi-step gate structure30according to one embodiment of the present invention. A mask layer34is formed on a semiconductor substrate32such as a silicon substrate, and a predetermined portion of the mask layer34is removed by lithographic and etching processes, while the remaining mask layer34′ covers a predetermined portion of the semiconductor substrate32. Preferably, the mask layer34is made of dielectric material such as silicon oxide possessing a certain etching selectivity with respect to the silicon substrate. Subsequently, the mask layer34′ is used as an etching mask in an etching process to remove a portion of the semiconductor substrate32not covered by the mask layer34′ to form a first depression36A. Preferably, an implanting process is performed to implant dopants into the semiconductor substrate32to form a doped region38A under the first depression36A, as shown inFIG. 3.

Referring toFIG. 4, a deposition process is performed to form a dielectric layer40on the semiconductor substrate32, and an etching process is then performed to form a first spacer40′ on the sidewall of the first depression36A, wherein the first spacer40′ is preferably made of dielectric material such as silicon oxide possessing a certain etching selectivity with respect to the silicon substrate. The first spacer40′ and the mask layer34′ are used as an etching mask in an etching process to remove a portion of the semiconductor substrate32not covered by the etching mask down to a predetermined depth to form a second depression36B. The depth D1of the first depression36A is smaller than the depth D2of the second depression36B. Preferably, an implanting process is performed to implant dopants into the semiconductor substrate32to form a second doped region38B under the second depression36B, as shown inFIG. 5.

Referring toFIG. 6, a second spacer42′ is formed on the sidewall of the second depression36B by deposition and etching processes, and the second spacer42′ is preferably made of dielectric material such as silicon oxide possessing a certain etching selectivity with respect to the silicon substrate. The mask layer34′, the first spacer40′ and the second spacer42′ are used as an etching mask in an etching process to remove a portion of the semiconductor substrate32not covered by the etching mask down to a predetermined depth to form a third depression36C. Subsequently, an implanting process is performed to implant dopants into the semiconductor substrate32to form a doped region38C under the third depression36C.

Referring toFIG. 7, the mask layer34′, the first spacer40′ and the second spacer42′ are removed by an etching process to form a multi-step structure44consisting of the first depression36A, the second depression36B and the third depression36C. Subsequently, a thermal oxidation process is performed to form a gate oxide layer46on the surface of the multi-step structure44, and a deposition process is then performed to form a conductive layer48on the gate oxide layer46. The lithographic and etching processes are performed to remove a portion of the gate oxide layer46and the conductive layer48serving as a continuous multi-step gate to complete the multi-step gate structure30, and an implanting process is then performed using the multi-step gate structure30as an implanting mask to form two doped regions52serving as a drain and a source in the semiconductor substrate32at two sides of the multi-step gate structure30, as shown inFIG. 8. Particularly, there is a carrier channel50in the semiconductor substrate32under the multi-step structure44, and the overall length of the carrier channel50is substantially the summation of the lateral width (W) of the lateral portion and the vertical height (H) of the vertical portion of the multi-step structure44. The gate oxide layer46under the multi-step gate is continuous and the carrier channel50between the two doped regions52is continuous as well.

The implanting processes performed inFIG. 3,FIG. 5andFIG. 6may have different dosages, i.e., the dopant concentrations in the doped regions38A,38B and38C may be different from one to another. These implanting processes may implant dopants not only into the semiconductor substrate32under the bottom surface of each depression, but also into the entire surface of each depression. These implanting processes may use nitrogen-containing dopants selected from the group consisting of ions of nitrogen atom, nitrogen gas, nitrous oxide and nitric oxide, which can inhibit the reaction rate of the subsequent thermal oxidation process, i.e., allow control of the thickness of the gate oxide layer46on each step surface of the multi-step structure44. Consequently, the different dosages of nitrogen-containing dopants cause the gate oxide layer46to have different thicknesses on each step surface of the multi-step structure44, i.e., the thickness of the gate oxide layer46on one step surface of the multi-step structure44may be different from that on another step surface of the multi-step structure44, which allows control of the threshold voltage of a transistor using the multi-step gate structure30. Instead of using nitrogen-containing dopants, these implanting processes may use boron-containing dopants or phosphorous-containing dopants, i.e., these implant processes may use different dopants. Particularly, boron-containing dopants or phosphorous-containing dopants can increase the carrier concentration in the carrier channel50so as to control the threshold voltage of a transistor having the multi-step gate structure30.

FIG. 9toFIG. 12illustrate a method for preparing a multi-step gate structure60according to another embodiment of the present invention. A mask layer62is formed on a semiconductor substrate32, a predetermined portion62A of the mask layer62is then removed by lithographic and etching processes, and the maintaining mask layer62′ covers a predetermined portion of the semiconductor substrate32. Preferably, the mask layer62is a photoresist layer or a dielectric layer, for example, made of silicon oxide or silicon nitride. Subsequently, the mask layer62′ is used as an etching mask in an etching process to remove a portion of the semiconductor substrate32not covered by the etching mask62′ to form a step64A on the semiconductor substrate32, as shown inFIG. 10.

Referring toFIG. 11, a predetermined portion62B of the mask layer62′ is removed by lithographic and etching processes to form a mask layer62″. The mask layer62″ is used in an etching process to remove a portion of the semiconductor substrate32not covered by the etching mask62″ to form a multi-step structure60including two steps64A and64B, as shown inFIG. 12. Particularly, multi-step structures with different numbers of steps can be prepared by repeating the processes shown inFIG. 11andFIG. 12.

In comparison with the conventional gate having a horizontally positioned carrier channel with a channel length substantially equal to the lateral width of the gate, one embodiment of the present invention provides a multi-step gate structure30having a carrier channel50with a channel length substantially equal to the summation of the lateral width (W) and the vertical height (H) of the multi-step gate structure30. Obviously, the channel length of the multi-step gate structure30is longer than that of the conventional gate, and the short channel effect can then be effectively solved. In addition, several implanting processes with different dosages and dopants can be performed during the fabrication process of the multi-step structure44to control the thickness of the gate oxide layer46and the threshold voltage of a transistor using the multi-step gate structure30.