Configuration update for a memory device based on a temperature of the memory device

Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.

BACKGROUND

The following relates generally to memory devices, and more specifically to temperature updates for memory devices.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices have two states, often denoted by a logic “1” or a logic “0.” In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored state in the memory device. To store information, the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor. A charged capacitor may, however, become discharged over time through leakage currents, resulting in the loss of the stored information. Certain features of volatile memory may offer performance advantages, such as faster read or write speeds, while features of non-volatile memory, such as the ability to store data without periodic refreshing, may be advantageous.

FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices. In some cases, a ferroelectric memory device may perform a temperature update, but components involved in this update may introduce noise or create other problems. This problems may disrupt operations of the memory cell or other components, may cause signal instability.

DETAILED DESCRIPTION

A ferroelectric memory device may perform a temperature update to update voltages, power supplies, or other operating characteristics that may change with temperature or other operating parameters. In some examples, components involved in temperature updates during other operations (e.g., a sense operation), however, may introduce noise. This noise may disrupt operations of the memory cell or other components, and may cause instability in signals, including when the temperature is near a switching threshold.

In some examples, during a temperature update, a reference voltage may be changed according to different temperatures. In some cases, a temperature update may occur during at least one other operation (e.g., a sense operation). In some examples, the temperature update of a memory cell may occur during a time interval that prevents or limits distortion of the signal that is discharged by the memory cell or a related component during an operation (e.g., a read operation). For example, the device or a device component may designate a duration to delay or withhold any temperature update while some operations (e.g., critical operations, operations such as writing or reading operations) are performed. During this time, at least a part of (e.g., a subset of) a refresh cycle (e.g., a second type of interval) may be used to access the temperature sensor, sample the temperature, and perform other operations to facilitate a temperature update. In some cases, before sampling the temperature, a settling time may be designated or used to allow the memory cell and/or at least one other component to reconfigure and achieve stable levels.

In some examples, memory devices—such as FeRAM—may contain components that operate with varying characteristics with respect to temperature. In some cases, the memory array or a memory cell may be designed to compensate for temperature to maximize performance and minimize power. For example, at cold temperatures, the voltage of the cell may be increased based on at least one component or operation, while at hot temperatures, the voltage of the cell may be decreased based on at least one component or operation. At cold temperatures, a FeRAM cell may polarize or perform a sense operation at a slower rate. In some cases, in order to regain performance at cold temperatures, the voltage of the cell may be increased. In some cases, sustaining a high voltage circuit may cause the cell to spend more power and energy at higher temperatures.

In some cases, based on the temperature update, the temperature sensor outputs may be used to reconfigure circuits (e.g., high voltage circuits). At higher voltages, the cell may require a small voltage adjustment from a digital-to-analog converter (DAC). In some cases, the cell may require reconfiguration. For example, the cell may be reconfigured to engage a charge pump and supply power to a regulator. In some cases, the charge pump may increase current flow to the regulator for higher voltages if there is not enough headroom for the non-pump power supply. In some applications, the device may perform a temperature update during a predefined interval to reduce power at cold temperatures and avoid higher voltages supplied by the pump.

As described herein, the device may perform a temperature update according to variable latency. For example, instead of increasing the voltage at cold temperatures, the cell may operate with longer latencies at cold temperatures. To notify the system of the latency at a given time, the information may be passed to the system through mode registers. In some cases, the device may initiate a temperature update command to notify the system when the update may occur. The device may perform a temperature update with variable latency to reduce the complexity of adding additional pumps to the die.

Features of the disclosure introduced above are further described below in the context of a memory array. Specific examples are then described for temperature updates for memory devices. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to temperature updates for memory devices.

FIG. 1illustrates an example memory array100that supports temperature updating for a memory device in accordance with various embodiments of the present disclosure. Memory array100may also be referred to as an electronic memory apparatus. Memory array100includes memory cells105that are programmable to store different states. As described herein, discussion of a cell or a memory cell may apply to a memory cell105and/or a memory array100unless otherwise described. Each memory cell105may be programmable to store two states, denoted as a logic 0 and a logic 1. In some cases, memory cell105is configured to store more than two logic states. A memory cell105may include a capacitor to store a charge representative of the programmable states; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may commonly use such a design, and the capacitor employed may include a dielectric material with linear electric polarization properties. By contrast, a ferroelectric memory cell may include a capacitor that has a ferroelectric as the dielectric material. Different levels of charge of a ferroelectric capacitor may represent different logic states. Ferroelectric materials have non-linear polarization properties; some details and advantages of a ferroelectric memory cell105are discussed below.

Operations such as reading and writing may be performed on memory cells105by activating or selecting the appropriate word line110and digit line115. Word lines110may also be referred to as access lines and digit lines115may also be referred to as bit lines. Activating or selecting a word line110or a digit line115may include applying a voltage to the respective line. Word lines110and digit lines115are made of conductive materials. For example, word lines110and digit lines115may be made of metals (such as copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, or the like. According to the example ofFIG. 1, each row of memory cells105is connected to a single word line110, and each column of memory cells105is connected to a single digit line115. By activating one word line110and one digit line115(e.g., applying a voltage to the word line110or digit line115), a single memory cell105may be accessed at their intersection. Accessing the memory cell105may include reading or writing the memory cell105. The intersection of a word line110and digit line115may be referred to as an address of a memory cell.

According to the techniques described herein, a temperature update may be performed before a read operation that occurs during a first type of interval. Thus, the temperature received by the temperature sensor may accurately reflect the temperature of the memory cell105. In some cases, if an operation (e.g., a read operation) occurs during the temperature update, the noise may disrupt the operations of the memory cell105and may cause instability in a related signal or limit the accuracy of the temperature update operation.

In some architectures, the logic storing device of a cell, e.g., a capacitor, may be electrically isolated from the digit line by a selection component. The word line110may be connected to and may control the selection component. For example, the selection component may be a transistor and the word line110may be connected to the gate of the transistor. Activating the word line110results in an electrical connection or closed circuit between the capacitor of a memory cell105and its corresponding digit line115. The digit line may then be accessed to either read or write the memory cell105.

Accessing memory cells105may be controlled through a row decoder120and a column decoder130. In some examples, a row decoder120receives a row address from the memory controller140and activates the appropriate word line110based on the received row address. Similarly, a column decoder130receives a column address from the memory controller140and activates the appropriate digit line115. For example, memory array100may include multiple word lines110, labeled WL_1through WL_M, and multiple digit lines115, labeled DL_1through DL_N, where M and N depend on the array size. Thus, by activating a word line110and a digit line115, e.g., WL_2and DL_3, the memory cell105at their intersection may be accessed.

Upon accessing, a memory cell105may be read, or sensed, by sense component125to determine the stored state of the memory cell105. For example, after accessing the memory cell105, the ferroelectric capacitor of memory cell105may discharge onto its corresponding digit line115. Discharging the ferroelectric capacitor may be based on biasing, or applying a voltage, to the ferroelectric capacitor. The discharging may induce a change in the voltage of the digit line115, which sense component125may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell105. For example, if digit line115has a higher voltage than the reference voltage, then sense component125may determine that the stored state in memory cell105was a logic 1 and vice versa. Sense component125may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of memory cell105may then be output through column decoder130as output135.

A memory cell105may be set, or written, by activating the relevant word line110and digit line115. As discussed above, activating a word line110electrically connects the corresponding row of memory cells105to their respective digit lines115. By controlling the relevant digit line115while the word line110is activated, a memory cell105may be written—i.e., a logic value may be stored in the memory cell105. Column decoder130may accept data, for example input135, to be written to the memory cells105. A ferroelectric memory cell105may be written by applying a voltage across the ferroelectric capacitor. This process is discussed in more detail below.

According to the techniques described herein, a temperature update may be performed before or after an operation (e.g., a write operation) that occurs during a first type of interval. Thus, the temperature received by the temperature sensor may accurately reflect the temperature of the memory device. In some cases, if an active operation (e.g., a write operation) occurs during the temperature update, the noise may disrupt the operations of the memory cell105and may cause instability in the temperature update.

In some memory architectures, accessing the memory cell105may degrade or destroy the stored logic state and re-write or refresh operations may be performed to return the original logic state to memory cell105. In DRAM, for example, the capacitor may be partially or completely discharged during a sense operation, corrupting the stored logic state. So the logic state may be re-written after a sense operation. Additionally, activating a single word line110may result in the discharge of all memory cells in the row; thus, several or all memory cells105in the row may need to be re-written. According to techniques described herein, a temperature update may be performed during a refresh cycle or be based on a refresh operation (e.g., a second type of interval). Thus, the device may designate a duration to withhold from temperature updates while the memory cell105is performing critical operations.

Some memory architectures, including DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. With increasingly larger memory arrays, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supplies, heat generation, material limits, etc.), especially for mobile devices that rely on a finite power source, such as a battery. As discussed below, ferroelectric memory cells105may have beneficial properties that may result in improved performance relative to other memory architectures.

The memory controller140may control the operation (e.g., read, write, re-write, refresh, etc.) of memory cells105through the various components, such as row decoder120, column decoder130, and sense component125. Memory controller140may generate row and column address signals in order to activate the desired word line110and digit line115. Memory controller140may also generate and control various voltages used during the operation of memory array100. In general, the amplitude, shape, or duration of an applied voltage discussed herein may be adjusted or varied and may be different for the various operations for operating memory array100. Furthermore, one, multiple, or all memory cells105within memory array100may be accessed simultaneously; for example, multiple or all cells of memory array100may be accessed simultaneously during a reset operation in which all memory cells105, or a group of memory cells105, are set to a single logic state.

The memory controller140may control at least one component to perform the temperature update. In some applications, the memory controller140may initiate a command to perform a temperature update. For example, the memory controller140may isolate, section out, or lock out portions of the memory array100to restrict operations (e.g., critical operations, operations such as sensing or access operations) and access to the memory array100. In other applications, the temperature update may occur independently of memory controller140. For example, the memory controller140may perform sensing operations during a first interval independent of the temperature update. In some cases, memory controller140may adjust a voltage associated with the memory cell105during a second period based on the temperature update. For example, critical operations such as sensing or access operations may be restricted during a second period. In some examples, memory control140may perform the temperature update of the memory array100periodically.

FIG. 2illustrates an example circuit200that supports temperature updating for a memory device in accordance with various embodiments of the present disclosure. Circuit200may be an example of memory array100, includes a memory cell105-a, word line110-a, digit line115-a, and sense component125-a, which may be examples of a memory cell105, word line110, digit line115, and sense component125, respectively, as described with reference toFIG. 1. Memory cell105-amay include a logic storage component, such as capacitor205that has a first plate, cell plate230, and a second plate, cell bottom215. Cell plate230and cell bottom215may be capacitively coupled through a ferroelectric material positioned between them. The orientation of cell plate230and cell bottom215may be flipped without changing the operation of memory cell105-a. Circuit200also includes selection component220and reference line225. Cell plate230may be accessed via plate line210and cell bottom215may be accessed via digit line115-a. As described above, various states may be stored by charging or discharging capacitor205.

The stored state of capacitor205may be read or sensed by operating various elements represented in circuit200. Capacitor205may be in electronic communication with digit line115-a. For example, capacitor205can be isolated from digit line115-awhen selection component220is deactivated, and capacitor205can be connected to digit line115-awhen selection component220is activated. Activating selection component220may be referred to as selecting memory cell105-a. In some cases, selection component220is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. Word line110-amay activate selection component220; for example, a voltage applied to word line110-ais applied to the transistor gate, connecting capacitor205with digit line115-a.

In other examples, the positions of selection component220and capacitor205may be switched, such that selection component220is connected between plate line210and cell plate230and such that capacitor205is between digit line115-aand the other terminal of selection component220. In this embodiment, selection component220may remain in electronic communication with digit line115-athrough capacitor205. This configuration may be associated with alternative timing and biasing for read and write operations.

Due to the ferroelectric material between the plates of capacitor205, and as discussed in more detail below, capacitor205may not discharge upon connection to digit line115-a. In one scheme, to sense the logic state stored by ferroelectric capacitor205, word line110-amay be biased to select memory cell105-aand a voltage may be applied to plate line210. In some cases, digit line115-ais virtually grounded and then isolated from the virtual ground, which may be referred to as “floating,” prior to biasing plate line210and word line110-a. Biasing plate line210may result in a voltage difference (e.g., plate line210voltage minus digit line115-avoltage) across capacitor205. The voltage difference may yield a change in the stored charge on capacitor205, where the magnitude of the change in stored charge may depend on the initial state of capacitor205—e.g., whether the initial state stored a logic 1 or a logic 0. This may cause a change in the voltage of digit line115-abased on the charge stored on capacitor205. Operation of memory cell105-aby varying the voltage to cell plate230may be referred to as “moving the cell plate.”

The change in voltage of digit line115-amay depend on its intrinsic capacitance. That is, as charge flows through digit line115-a, some finite charge may be stored in digit line115-aand the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical characteristics, including the dimensions, of digit line115-a. Digit line115-amay connect many memory cells105so digit line115-amay have a length that results in a non-negligible capacitance (e.g., on the order of picofarads (pF)). The resulting voltage of digit line115-amay then be compared to a reference (e.g., a voltage of reference line225) by sense component125-ain order to determine the stored logic state in memory cell105-a. Other sensing processes may be used.

Sense component125-amay include various transistors or amplifiers to detect and amplify a difference in signals, which may be referred to as latching. Sense component125-amay include a sense amplifier that, during a sense operation, receives and compares the voltage of digit line115-aand reference line225, which may be a reference voltage. According to the techniques described herein, a temperature update may occur before or after a sense operation to limit noise that may otherwise be introduced into the signal and cause instability. The sense amplifier output may be driven to the higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For instance, if digit line115-ahas a higher voltage than reference line225, then the sense amplifier output may be driven to a positive supply voltage. In some cases, the sense amplifier may additionally drive digit line115-ato the supply voltage. Sense component125-amay then latch the output of the sense amplifier and/or the voltage of digit line115-a, which may be used to determine the stored state in memory cell105-a, e.g., logic 1. Alternatively, if digit line115-ahas a lower voltage than reference line225, the sense amplifier output may be driven to a negative or ground voltage. Sense component125-amay similarly latch the sense amplifier output to determine the stored state in memory cell105-a, e.g., logic 0. The latched logic state of memory cell105-amay then be output, for example, through column decoder130as output135with reference toFIG. 1.

To write memory cell105-a, a voltage may be applied across capacitor205. Various methods may be used. In one example, selection component220may be activated through word line110-ain order to electrically connect capacitor205to digit line115-a. A voltage may be applied across capacitor205by controlling the voltage of cell plate230(through plate line210) and cell bottom215(through digit line115-a). To write a logic 0, cell plate230may be taken high, that is, a positive voltage may be applied to plate line210, and cell bottom215may be taken low, e.g., virtually grounding or applying a negative voltage to digit line115-a. The opposite process is performed to write a logic 1, where cell plate230is taken low and cell bottom215is taken high.

In some examples, the memory array100may be reconfigured in one or more ways based on one or more operations. In some cases, the memory array100may be reconfigured based on engaging a charge pump235related to or based on a condition. For example, the charge pump235may be activated or initiated when a first voltage (e.g., the output voltage240) is less than a second voltage (e.g., the supply voltage245) of the memory cell105-a. In some cases, a first voltage (e.g., the output voltage240), may be an example of an adjusted voltage. The charge pump235may be activated or initiated to increase current flow to a regulator based at least in part on the adjusted voltage. Additionally or alternatively, the charge pump235may be activated or initiated based on a timing or a type of one or more other operations occurring during an interval. In some cases, the charge pump235may be in electronic communication with a switch250. Switch250may be turned on and off which may introduce noise into the signal and discontinuity in the output voltage240. In some cases, there may not be enough headroom to run a regulator. Based on this, the memory array100may activate a charge pump235to increase current flow to a regulator. For example, a charge pump235may be selectively activated based on a detected temperature (e.g., when a temperature falls below a threshold) to limit noise that may otherwise be introduced into the signal and cause discontinuity in the output voltage240.

In some cases, the memory array100may perform a temperature update based on sampling a temperature in a temperature sensor255. For example, temperature sensor255may be capable of measuring one or more parameters (e.g., electrical parameters) of the memory array100(e.g., heat sensor, digital sensor, analog sensor,). Some examples of the temperature sensor255may include, but are not limited to, a thermistor (e.g., a Negative Temperature Coefficient (NTC) thermistor, a Resistance Temperature Detector (RTD), a thermocouple, a semiconductor based sensor, a contact temperature sensor, a non-contact temperature sensor, another type, a combination of two or more sensor types). In some embodiments, one or more temperature sensors255may sample the temperature of the memory cell104, a portion of the memory array, or some combination. The temperature sensor255may be in electronic communication with the memory cell105-a, a counter (not shown), a latch260, other components, or some combination. The counter may determine an interval of the second type based at least in part on a predetermined interval cycle. In some cases, the counter may identify the beginning of a temperature update (e.g., every Nth “stolen” refresh interval). The latch260may receive and store the temperature associated with the temperature sensor255. Based on this, the temperature sensor255may output a digital value corresponding to the temperature. In some cases, the temperature sensor255may initiate or activate (e.g., unlocking, opening) a latch260and allow the outputted value corresponding to the current temperature of the memory cell105-ato drive the look-up table during a temperature update. For example, the look-up table may further include an array of slots (e.g. different temperature ranges) that serves as an address for the outputted value corresponding to the current temperature of the memory cell105-a. The look-up table may output a digital-to-analog converter (DAC) value that corresponds to a voltage. In some examples, a DAC value may be updated with a temperature change. For example, accessing a value in a look-up table based on the sampled temperature, and/or adjusting a DAC value based on the DAC value and the sampled temperature may update the analog circuit and reconfigure the memory array100. In some cases, a temperature update may initiate activating (e.g., locking, closing) latch260and limit or prevent further temperature update operations or additional updates. In some examples, the switch250may respond to the value stored in the latch260. Based on this, the temperature update may occur during a predefined interval (e.g., a second type of interval).

FIG. 3illustrates an example of non-linear electrical properties with hysteresis curves300-aand300-bfor a ferroelectric memory cell that is operated in accordance with various embodiments of the present disclosure. Hysteresis curves300-aand300-billustrate an example ferroelectric memory cell writing and reading process, respectively. Hysteresis curves300depict the charge, Q, stored on a ferroelectric capacitor (e.g., capacitor205ofFIG. 2) as a function of a voltage difference, V.

A ferroelectric material is characterized by a spontaneous electric polarization, i.e., it maintains a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electric polarization within a ferroelectric capacitor results in a net charge at the ferroelectric material's surface and attracts opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization may be maintained in the absence of an externally applied electric field for relatively long times, even indefinitely, charge leakage may be significantly decreased as compared with, for example, capacitors employed in DRAM arrays. This may reduce the need to perform refresh operations as described above for some DRAM architectures.

Hysteresis curves300may be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Likewise, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. Additionally, it should be understood that the voltages in hysteresis curves300represent a voltage difference across the capacitor and are directional. For example, a positive voltage may be realized by applying a positive voltage to the terminal in question (e.g., a cell plate230) and maintaining the second terminal (e.g., a cell bottom215) at ground (or approximately zero volts (0V)). A negative voltage may be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal—i.e., positive voltages may be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage difference shown in hysteresis curves300.

As depicted in hysteresis curve300-a, the ferroelectric material may maintain a positive or negative polarization with a zero voltage difference, resulting in two possible charged states: charge state305and charge state310. According to the example ofFIG. 3, charge state305represents a logic 0 and charge state310represents a logic 1. In some examples, the logic values of the respective charge states may be reversed to accommodate other schemes for operating a memory cell.

A logic 0 or 1 may be written to the memory cell by controlling the electric polarization of the ferroelectric material, and thus the charge on the capacitor terminals, by applying voltage. For example, applying a net positive voltage315across the capacitor results in charge accumulation until charge state305-ais reached. Upon removing voltage315, charge state305-afollows path320until it reaches charge state305at zero voltage potential. Similarly, charge state310is written by applying a net negative voltage325, which results in charge state310-a. After removing negative voltage325, charge state310-afollows path330until it reaches charge state310at zero voltage. Charge states305-aand310-amay also be referred to as the remnant polarization (Pr) values, i.e., the polarization (or charge) that remains upon removing the external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero.

To read, or sense, the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge, Q, changes, and the degree of the change depends on the initial charge state—i.e., the final stored charge (Q) depends on whether charge state305-bor310-bwas initially stored. For example, hysteresis curve300-billustrates two possible stored charge states305-band310-b. Voltage335may be applied across the capacitor as discussed with reference toFIG. 2. In other cases, a fixed voltage may be applied to the cell plate and, although depicted as a positive voltage, voltage335may be negative. In response to voltage335, charge state305-bmay follow path340. Likewise, if charge state310-bwas initially stored, then it follows path345. The final position of charge state305-cand charge state310-cdepend on a number of factors, including the specific sensing scheme and circuitry.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if the capacitor is electrically connected to the digit line and voltage335is applied, the voltage of the digit line may rise due to its intrinsic capacitance. So a voltage measured at a sense component may not equal voltage335and instead may depend on the voltage of the digit line. The position of final charge states305-cand310-con hysteresis curve300-bmay thus depend on the capacitance of the digit line and may be determined through a load-line analysis—i.e., charge states305-cand310-cmay be defined with respect to the digit line capacitance. As a result, the voltage of the capacitor, voltage350or voltage355, may be different and may depend on the initial state of the capacitor.

By comparing the digit line voltage to a reference voltage, the initial state of the capacitor may be determined. The digit line voltage may be the difference between voltage335and the final voltage across the capacitor, voltage350or voltage355—i.e., (voltage335-voltage350) or (voltage335-voltage355). A reference voltage may be generated such that its magnitude is between the two possible voltages of the two possible digit line voltages in order to determine the stored logic state—i.e., if the digit line voltage is higher or lower than the reference voltage. For example, the reference voltage may be an average of the two quantities, (voltage335-voltage350) and (voltage335-voltage355). Upon comparison by the sense component, the sensed digit line voltage may be determined to be higher or lower than the reference voltage, and the stored logic value of the ferroelectric memory cell (i.e., a logic 0 or 1) may be determined.

As discussed above, reading a memory cell that does not use a ferroelectric capacitor may degrade or destroy the stored logic state. A ferroelectric memory cell, however, may maintain the initial logic state after a read operation. For example, if charge state305-bis stored, the charge state may follow path340to charge state305-cduring a read operation and, after removing voltage335, the charge state may return to initial charge state305-bby following path340in the opposite direction.

In some cases, voltage350or voltage355may not accurately represent the charge stored at or other operating characteristic related to a memory cell105. For example, if uncompensated, variations in the output voltage240related to various components involved in a temperature update may result in variations in voltage350or voltage355, which may in turn lead to operation errors (e.g., read errors). As described herein, in some examples, the variation in output voltage240may be accounted for by using a charge pump235to achieve an output voltage240higher than the supply voltage245.

FIG. 4illustrates an example of a timing cycle400that supports temperature updating for a memory device. Timing cycle400may include a first interval405(which may be an interval of a first type) and a second interval410(which may be an interval of a second type). In some examples, during the first interval405-d, one or more memory operations (e.g., access operations) related to a memory array100or a memory cell105may be performed. For example, a read operation related to the memory array100or a memory cell105may be performed, a write operation related to the memory array100or a memory cell105may be performed, an operation activating one or more components (e.g., activating sense component125) related to the memory array100or a memory cell105may be performed, or a precharging operation related to a component of the memory array100may be performed.

In some examples, during the second interval410-d, the temperature sensor255may measure the temperature based on an electrical response of the memory array100. In some cases, based on a refresh operation, the memory cell105may be refreshed during the second interval410-d. In some examples, the first interval405-dmay be of a first type and the second interval410-dmay be of a second type that is different from the first type. In some cases, the first interval405-dmay be an active operation interval such as an access operation, a write operation, a read operation, activating a sense component, precharging a component, another operation, or a combination thereof, and the second interval410-dmay include a refresh operation, a sampling operation, another operation, or a some combination thereof.

As described herein, the second interval410-dmay, in some examples, occur according to a predetermined interval cycle or schedule. The predetermined interval cycle may be determined based on frequency of memory array100usage, operations, disturbances, other characteristics, or some combination related to the memory array100or a memory cell105. During the second interval410-d, operations that may occur in the first interval405-dmay be prohibited during or delayed for at least a part of the second interval410-d. For example, the temperature may be measured based on an electrical response from the memory array100during a first part of the second interval410-d, as referenced in block415. In some cases, the temperature may be resampled from a portion of the memory array100or the memory cell105after an initial sampling. In some cases, the controller may isolate portions of the memory array100to resample a temperature from a portion of the memory array100. In some examples, the resampling may occur during a subsequent part of the same second interval410-d. In some examples, the resampling may occur during a subsequent interval of the same type (e.g., second interval410-e), a subsequent interval of a different type (e.g., first interval405-e), or some combination. In some examples, performing a temperature update according to a predetermined interval cycle may account for temperature variations independent of performed or scheduled operations or the memory controller140.

In some examples, multiple temperature updates may occur during intervals of the same type, different types, or some combination. For example, a first temperature update may occur during second interval410-dand a second temperature update may occur during another interval of a same type (e.g., second interval410-e). Other variations are also contemplated. In some cases, a first temperature update may occur during second interval410-dand a second temperature update may occur during the same interval of the same type (e.g., second interval410-d). In some examples, at least some first intervals (e.g., first interval405-a, first interval405-b) may be of a same type, of different types, have the characteristics, may relate to the same or different operations performed during the first intervals, or some combination. In some examples, some second intervals (e.g., second interval410-a, second interval410-b) may be of a same type, of different types, have the characteristics, may relate to the same or different operations performed during the first intervals, or some combination.

In some cases, the memory array100may be configured according to a voltage configuration (e.g., a high voltage configuration). For example, a charge pump235may be enabled for operation at the sampled temperature, as illustrated in block420. The charge pump235may be engaged when the output voltage240of the memory cell105is less than the supply voltage245of the memory cell105. For example, the memory array100may engage a charge pump235to increase current flow to a regulator. To engage the charge pump235, switch250may regulate an operating state of the charge pump235(e.g., regulate on state, operating state, off state). Switching the charge pump235on and off may introduce noise into the signal and discontinuity in the output voltage240.

As referenced herein at block425, reconfiguring the memory array100may, in some examples, include updating an analog circuit. To perform a temperature update, a temperature sensor255may be in electronic communication with the memory cell105or the memory array. For example, temperature sensor255may be capable of measuring electrical parameters of the memory array100(e.g., heat sensor, digital sensor, analog sensor, etc.). In some cases, the temperature sensor255may also be in electronic communication with a counter, a latch260, other components, or some combination. The counter may determine an interval of the second type based at least in part on a predetermined interval cycle. In some cases, the counter may identify the beginning of a temperature update (e.g., every Nth “stolen” refresh interval). In some cases, the latch260may receive and store the temperature associated with the temperature sensor255. In some cases, the temperature sensor255may output a digital value corresponding to the current temperature of the memory cell105. For example, the digital value may drive the look-up table and output a digital-to-analog converter (DAC) value that corresponds to a voltage. In some examples, a DAC value may be updated with a temperature change. For example, updating the analog circuit may occur on a die-by-die basis (e.g., based on the voltage that corresponds to the outputted DAC value). Updating the analog circuit may include accessing a value in a look-up table based on the sampled temperature, and/or adjusting a DAC value based on the DAC value and the sampled temperature. In some cases, discontinuities associated with the temperature change may cause instability on the output voltage240.

Additionally or alternatively, the memory array100may be reconfigured as referenced in block430based on latency information. For example, memory array100(or a related component) may output latency information to the controller via the mode register. The memory array100may run with variable latencies with respect to temperature. For example, latency information may affect a first duration of the second interval410-drelating to a temperature at or below a threshold (e.g., colder temperatures), or a second duration based on a temperature at or above threshold (e.g., hotter temperatures). In some cases, the output latency information may be passed to the system through mode registers to notify the system of the latency at a given time. In some cases, the memory array100may initiate a command (e.g., a temperature update command, scheduling command,) to notify the system when the update may occur and other information. For example, the memory array100may issue a first temperature update command, read the mode register, and run at the given variable latency until a predetermined time which may be based on the memory array100issuing a second temperature updated command. In some applications, the interval may be set aside for a refresh operation and used for temperature sampling. In some cases, the memory device may perform a temperature update periodically (e.g., every Nth “stolen” refresh interval). For example, a temperature update may occur every 5 ms in which ‘N’ equals 16, a first duration of the first interval405-dis 300 us, and a first duration of the second interval410-dis 30 ns. Additionally or alternatively, as described in block435, a settling time may be used to allow the memory array100to reconfigure and achieve stable levels before operations begin in the first interval405-d.

FIG. 5shows a block diagram500of a memory array505that supports temperature updating for a memory device in accordance with various examples of the present disclosure. Memory array505may be referred to as an electronic memory apparatus, and may be an example of a component of a memory array100as described with reference toFIG. 1.

Memory array505may include one or more memory cells510, a memory controller515, a word line520, a plate line525, a reference component530, a sense component535, a digit line540, and a latch545. These components may be in electronic communication with each other and may perform one or more of the functions described herein. In some cases, memory controller515may include biasing component550and timing component555.

Memory controller515may be in electronic communication with word line520, digit line540, sense component535, and plate line525, which may be examples of word line110, digit line115, sense component125, and plate line210described with reference toFIGS. 1, and 2. Memory array505may also include reference component530and latch545. The components of memory array505may be in electronic communication with each other and may perform examples of the functions described with reference toFIGS. 1 through 4. In some cases, reference component530, sense component535, and latch545may be components of memory controller515.

In some examples, digit line540is in electronic communication with sense component535and a ferroelectric capacitor of ferroelectric memory cells510. A ferroelectric memory cell510may be writable with a logic state (e.g., a first or second logic state). Word line520may be in electronic communication with memory controller515and a selection component of ferroelectric memory cell510. Plate line525may be in electronic communication with memory controller515and a plate of the ferroelectric capacitor of ferroelectric memory cell510. Sense component535may be in electronic communication with memory controller515, digit line540, latch545, and reference line560. Reference component530may be in electronic communication with memory controller515and reference line560. Sense control line565may be in electronic communication with sense component535and memory controller515. These components may also be in electronic communication with other components, both inside and outside of memory array505, in addition to components not listed above, via other components, connections, or busses.

Memory controller515may be configured to activate word line520, plate line525, or digit line540by applying voltages to those various nodes. For example, biasing component550may be configured to apply a voltage to operate memory cell510to read or write memory cell510as described above. In some cases, memory controller515may include a row decoder, column decoder, or both, as described with reference toFIG. 1. This may enable memory controller515to access one or more memory cells105. Biasing component550may also provide or apply voltage to reference component530in order to generate a reference signal for sense component535. Additionally, biasing component550may provide or apply voltage for the operation of sense component535.

In some cases, memory controller515may perform its operations using timing component555. For example, timing component555may control the timing of the various word line selections or plate biasing, including timing for switching and voltage application to perform the memory functions, such as reading and writing, discussed herein. In some cases, timing component555may control the operations of biasing component550.

Reference component530may include various components to generate a reference signal for sense component535. Reference component530may include circuitry configured to produce a reference signal. In some cases, reference component530may be implemented using other ferroelectric memory cells105. Sense component535may compare a signal from memory cell510(through digit line540) with a reference signal from reference component530. In some cases, sense component535may include a temperature sensor255such as described with reference toFIG. 2. In some applications, temperature sensor255may also be, be part of, or include a temperature sampling component. In some examples, temperature sensor255and the related temperature sampling component may be present as a separate component from sense component535. Upon determining the logic state, the sense component may then store the output in latch545, where it may be used in accordance with the operations of an electronic device that memory array505is a part. Sense component535may include a sense amplifier in electronic communication with the latch and the ferroelectric memory cell.

Memory controller515may be an example of the temperature manager715described with reference toFIG. 7. Memory controller515may operate a memory array according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval, sample a temperature related to a temperature of at least a portion of the memory array during an interval of the second type, reconfigure the memory array based on a sampled temperature during the interval of the second type, and perform the first type of operation on a reconfigured memory array during an interval of the first type. In some examples, during the first interval, one or more memory operations (e.g., access operations) related to a memory array or a memory cell may be performed. For example, a read operation related to the memory array or a memory cell may be performed, a write operation related to the memory array or a memory cell may be performed, an operation activating one or more components (e.g., activating sense component) related to the memory array or a memory cell may be performed, or a precharging operation related to a component of the memory array may be performed. In some cases, based on a refresh operation, the memory cell may be refreshed during the second interval. In some cases, during part or an entire second interval (e.g., an interval potentially set aside for a refresh operation) a temperature related to a temperature of at least a portion of the memory array may be sampled, the memory array may be reconfigured based on the sampled temperature during the interval (and/or other intervals), other operations may be performed, or some combination. In some applications, the interval may be set aside for a refresh operation and used for temperature sampling. Memory array100may be sampled periodically (e.g., without limitation of every 8, 16, or 32 refresh intervals). In some cases, after reconfiguring of the memory array (or a memory cell and/or another component), a first type of operation (e.g., an access operation) may be performed on the reconfigured memory array during a subsequent interval (e.g., an interval of the first type).

FIG. 6shows a block diagram600of a temperature manager615that supports temperature updating for a memory device in accordance with various examples of the present disclosure. The temperature manager615may be an example of examples of a temperature manager715described with reference toFIGS. 4, 5, and 7. The temperature manager615may include biasing component620, timing component625, operation timing component630, temperature sampling component635, memory array configuration component640, voltage component645, analog circuit component650, and latency output component655. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

Operation timing component630may operate a memory array according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second interval and perform the first type of operation on a reconfigured memory array during an interval of the first type. In some cases, the first type of operation includes at least one of an accessing a cell of the memory array, reading from a cell of the memory array, writing to a cell of the memory array, activating a sensing component, precharging a component of the memory array, or any combination thereof. In some cases, the second type of operation includes refreshing a cell of the memory array or sampling the temperature of at least the portion of the memory array. In some cases, the first type of operation is prohibited during intervals of the second type.

Temperature sampling component635may sample a temperature related to a temperature of at least a portion of the memory array during an interval of the second type and resample the temperature of the memory cell and/or of the portion of the memory array after sampling. In some cases, the controller may isolate one or more portions of the memory array100to resample a temperature from at least one portion of the memory array100.

Memory array configuration component640may reconfigure the memory array based on a sampled temperature during the interval of the second type, reconfigure the memory array based on receiving a command from a controller, and reconfigure the memory array based on periodically resampling the memory array.

Voltage component645may adjust the voltage of the memory array based on comparing the sampled temperature to a predetermined value and engaging a charge pump to increase current flow to a regulator based on the adjusted voltage. In some cases, reconfiguring the memory array includes adjusting a voltage associated with the memory array based on the sampled temperature and evaluating an adjusted voltage of the reconfigured memory array, where the adjusted voltage is less than a supply voltage.

Analog circuit component650may access the look-up table with different entry values based on the sampled temperature and adjust a digital-to-analog converter (DAC) value based on the sampled temperature and the value. In some cases, reconfiguring the memory array includes updating an analog circuit. In some cases, updating the analog circuit includes accessing a value in a look-up table.

Latency output component655may receive a value from the mode register and perform an operation associated with the memory array based on the temperature update command and the value from the mode register. In some cases, reconfiguring the memory array further includes outputting latency information to a controller via a mode register. In some cases, outputting latency information includes initiating a temperature update command.

FIG. 7shows a diagram of a system700including a device705that supports temperature updating for a memory device in accordance with various examples of the present disclosure. Device705may include the components of memory array100as described above, e.g., with reference toFIG. 1. Device705may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including temperature manager715, memory cells720, basic input/output system (BIOS) component725, processor730, I/O controller735, and peripheral components740. These components may be in electronic communication via one or more busses (e.g., bus710).

Memory cells720may store information (i.e., in the form of a logical state) as described herein. BIOS component725be a software component that includes BIOS operated as firmware, which may initialize and run various hardware components. BIOS component725may also manage data flow between a processor and various other components, e.g., peripheral components, input/output control component, etc. BIOS component725may include a program or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

Processor730may include an intelligent hardware device, (e.g., a general-purpose processor, a digital signal processor (DSP), a central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA), a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor730may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor730. Processor730may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting temperature updates for memory devices).

I/O controller735may manage input and output signals for device705. I/O controller735may also manage peripherals not integrated into device705. In some cases, I/O controller735may represent a physical connection or port to an external peripheral. In some cases, I/O controller735may utilize an operating system such as iOS®, ANDROID®, MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, or another known operating system.

Peripheral components740may include any input or output device, or an interface for such devices. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

Input745may represent a device or signal external to device705that provides input to device705or its components. This may include a user interface or an interface with or between other devices. In some cases, input745may be managed by I/O controller735, and may interact with device705via a peripheral component740.

Output750may also represent a device or signal external to device705configured to receive output from device705or any of its components. Examples of output750may include a display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, output750may be a peripheral element that interfaces with device705via peripheral component(s)740. In some cases, output750may be managed by I/O controller735

The components of device705may include circuitry designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry out the functions described herein. Device705may be a computer, a server, a laptop computer, a notebook computer, a tablet computer, a mobile phone, a wearable electronic device, a personal electronic device, or the like. Or device705may be a portion, component, element, or aspect of such a device.

FIG. 8shows a flowchart illustrating a method800for temperature updating for a memory device in accordance with various examples of the present disclosure. The operations of method800may be implemented by a memory array100or its components as described herein. For example, the operations of method800may be performed by a temperature manager as described with reference toFIGS. 5 through 7. In some examples, a memory array100may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory array100may perform examples the functions described below using special-purpose hardware.

At block805the method may include operating a memory array according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. The operations of block805may be performed according to the methods described with reference toFIGS. 1 and 4. In some cases, the first type of operation includes at least one of an accessing a cell of the memory array100, reading from a cell of the memory array100, writing to a cell of the memory array100, activating a sensing component, precharging a component of the memory array100, or any combination thereof. In some cases, the second type of operation includes refreshing a cell of the memory array100or sampling the temperature of at least the portion of the memory array100. In certain examples, examples of the operations of block805may be performed by a operation timing component as described with reference toFIGS. 5 through 7.

At block810the method may include sampling a temperature related to a temperature of at least a portion of the memory array during an interval of the second type. In some cases, the sampling of the temperature includes using a temperature sensor to sample a temperature of at least a portion of a memory array or a memory apparatus. The operations of block810may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block810may be performed by a temperature sampling component as described with reference toFIGS. 5 through 7.

At block815the method may include reconfiguring the memory array based at least in part on a sampled temperature during the interval of the second type. In some cases, reconfiguring the memory array includes adjusting a voltage associated with the memory array based at least in part on the sampled temperature. Reconfiguring the memory array may, in some cases, include evaluating an adjusted voltage of the reconfigured memory array, where the adjusted voltage is less than the a supply voltage and engaging a charge pump to increase current flow to a regulator based at least in part on the adjusted voltage. In some applications, reconfiguring the memory array includes updating an analog circuit. Reconfiguring the memory array, in some cases, may also include outputting latency information to a controller via a mode register. The operations of block815may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block815may be performed by a memory array configuration component as described with reference toFIGS. 5 through 7.

At block820the method may include performing the first type of operation on a reconfigured memory array during an interval of the first type. The operations of block820may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block820may be performed by a operation timing component as described with reference toFIGS. 5 through 7.

FIG. 9shows a flowchart illustrating a method900for temperature updating for a memory device in accordance with various examples of the present disclosure. The operations of method900may be implemented by a memory array100or its components as described herein. For example, the operations of method900may be performed by a temperature manager as described with reference toFIGS. 5 through 7. In some examples, a memory array100may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory array100may perform examples the functions described below using special-purpose hardware.

At block905the memory array100may operate a memory array according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. The operations of block905may be performed according to the methods described with reference toFIGS. 1 and 4. In some cases, the first type of operation includes at least one of an accessing a cell of the memory array100, reading from a cell of the memory array100, writing to a cell of the memory array100, activating a sensing component, precharging a component of the memory array100, or any combination thereof. In some cases, the second type of operation includes refreshing a cell of the memory array100or sampling the temperature of at least the portion of the memory array100. In certain examples, examples of the operations of block905may be performed by a operation timing component as described with reference toFIGS. 5 through 7.

At block910the memory array100may sample a temperature related to a temperature of at least a portion of the memory array during an interval of the second type. In some cases, the sampling of the temperature includes using a temperature sensor to sample a temperature of at least a portion of a memory array or a memory apparatus. The operations of block910may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block910may be performed by a temperature sampling component as described with reference toFIGS. 5 through 7.

At block915the memory array100may reconfigure the memory array based at least in part on a sampled temperature during the interval of the second type. In some cases, reconfiguring the memory array includes adjusting a voltage associated with the memory array based at least in part on the sampled temperature. Reconfiguring the memory array, in some cases, includes evaluating an adjusted voltage of the reconfigured memory array, where the adjusted voltage is less than the a supply voltage and engaging a charge pump to increase current flow to a regulator based at least in part on the adjusted voltage. In some applications, reconfiguring the memory array includes updating an analog circuit. Reconfiguring the memory array, in some cases, may also include outputting latency information to a controller via a mode register. The operations of block915may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block915may be performed by a memory array configuration component as described with reference toFIGS. 5 through 7.

At block920the memory array100may perform the first type of operation on a reconfigured memory array during an interval of the first type. The operations of block920may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block920may be performed by a operation timing component as described with reference toFIGS. 5 through 7.

At block925the memory array100may resample the temperature of the portion of the memory array after the sampling. The operations of block925may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block925may be performed by a temperature sampling component as described with reference toFIGS. 5 through 7.

At block930the memory array100may reconfigure the memory array based at least in part on periodically resampling the memory array. In some cases, resampling the temperature may be periodically repeated at the Nth interval of the second type, where N is an integer number. (e.g., without limitation, 8, 16, 32, etc.) The operations of block930may be performed according to the methods described with reference toFIGS. 1 and 4. In certain examples, examples of the operations of block930may be performed by a memory array configuration component as described with reference toFIGS. 5 through 7.

As used herein, the term “virtual ground” refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly connected with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. “Virtual grounding” or “virtually grounded” means connected to approximately 0V.

The term “electronic communication” refers to a relationship between components that supports electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed). A switch, for example, that is in contact with other components may facilitate electronic communication between the components.

The term “isolated” refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

As used herein, the term “shorting” refers to a relationship between components in which a conductive path is established between the components via the activation of a single intermediary component between the two components in question. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables the flow of charge between components (or lines) that are in electronic communication.