Phase calculation circuitry in digital television receiver

An angle .alpha. from 0.degree. to 45.degree. is determined from an equation .alpha..degree.=LK.iota.(tan .alpha.).sup..iota., where .iota. is an index varying from 0 to n. The value of tan .alpha. is arrived at by dividing the smaller of the I,Q magnitude values by the larger of the two magnitude values. The angle .alpha. from 0.degree. to 45.degree. is transposed to the corresponding phase angle .theta. of the vector sum C of the orthogonal I,Q signals over the full range of values from 0.degree. to 360.degree..

The present invention relates to circuitry for calculating the value of the 
phase of the vector sum of two orthogonally-related component signals. 
More particularly, it is directed toward reducing the circuitry needed to 
perform the required arctangent calculations. The invention has general 
applicability, but is particularly useful in digital television receivers 
where it is desired to perform digital video signal processing with a 
minimum of hardware. 
BACKGROUND OF THE INVENTION 
In many electronic systems, it is necessary to determine the phase of the 
vector sum of a pair of orthogonal signals with respect to one of its 
components. For example, in digital TV receivers, it is convenient to 
perform automatic flesh color correction by manipulating the phase and 
magnitude of the chrominance vector. The chrominance signal, is usually 
available in the form of two quadrature signals represented by the I and Q 
color mixture signals or the (R-Y) and (B-Y) color difference signals. 
Thus, to perform the required manipulation, the phase of the chrominance 
vector must be determined from its perpendicularly-disposed component 
parts. 
It is well known that the instantaneous phase of the vector sum of a pair 
of orthogonal signals may be ascertained by generating the arctangent of 
the ratio of the instantaneous magnitude values of the respective signal 
components --i.e., .theta.=Arctangent (Q/I). Typically, this is 
accomplished by using a read-only memory (ROM) to which tan .theta. (i.e., 
Q/I) values are applied as address codes, and which is programmed to 
contain the associated .theta. values at the respective memory locations. 
SUMMARY OF THE INVENTION 
The vector sum phase calculating circuitry, in accordance with the present 
invention, generates sample values representing tangents of angles .alpha. 
over the range of zero to forty-five degrees by dividing the magnitude of 
the smaller of the first and second quadrature signals I and Q by the 
magnitude of the larger of the two signals. The tangent values are 
converted to corresponding angle-related values by using an equation 
.alpha.=.SIGMA.K.iota.(tan .alpha.).iota., where .iota. is an index 
varying from zero to n. The constants K.iota. can be determined, for 
example, by using the multiple regression technique. 
Pursuant to a further feature of the invention, the angle-related values of 
.alpha. are transposed to the corresponding angle values .theta. 
representing the instantaneous phase of the chrominance vector C with 
respect to one of the two orthogonal component signals I and Q.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The circuitry 20 of FIG. 1 exemplifies an apparatus for performing 
auto-flesh correction in a digital television receiver. The auto-flesh 
correction circuitry 20 is located in the color signal processing section 
of the receiver and operates upon the quadrature-related color component 
vectors I and Q of the chrominance signal C after separation thereof from 
the composite video signal. The presumption is made that the chrominance 
signal samples C occur at 4 times the color subcarrier rate (e.g., 3.58 
MHz), and that the samples are phased to correspond with the I and Q axes. 
This results in a stream of I and Q sample values in a certain sequence: 
+I.sub.n, +Q.sub.n, -I.sub.n, -Q.sub.n, +I.sub.n+1, +Q.sub.n+1, 
-I.sub.n+1, -Q.sub.n+1 and so on, where n, n+1, etc., represent the cycle 
numbers of the sampled chrominance signal C and the + and - signs 
represent sampling phase, and not the sample polarity. It is further 
assumed that the sample values are in the digital format (e.g., 8-bit 
parallel PCM signals). A detailed description of a circuit of this type 
may be found in a copending U.S. patent application, Ser. No. 501,896, and 
entitled "AN AUTO TINT CIRCUIT FOR A TV RECEIVER" incorporated herein by 
reference. Reference may be also made to U.S. Pat. No. 4,402,005, issued 
to Lewis, Jr., and entitled "CLOCK GENERATOR FOR A DIGITAL COLOR 
TELEVISION SIGNAL RECEIVER", for a description of an illustrative circuit 
for generating a suitable stream of I and Q amplitude values. 
Briefly the FIG. 1 circuit 20 operates as follows. Auto-flesh correction is 
performed by rotating the chrominance vector C toward the I component 
vector whenever the phase angle of the chrominance vector is within a 
particular range of values associated with flesh colors. The chrominance 
vector C, however, is represented by its component parts in the form of 
the orthogonal color mixture signal vectors I and Q or alternatively, by 
the orthogonal color difference signals (R-Y) and (B-Y). For descriptive 
purposes, the invention will be explained using the I and Q component 
signals. The circuit 20 outputs a rotated chrominance signal represented 
by substantially orthogonal color mixture signals I' and Q' corresponding 
to the rotated chrominance vector C'. 
The I and Q signal sample stream is applied to terminal 22 from which it is 
routed to a magnitude detector 24 and an angle detector 26. The magnitude 
detector 22 generates a magnitude value of the vector sum C of the 
orthogonal I and Q signal components e.g., C =.sqroot.I.sup.2 +Q.sup.2 and 
produces this signal on bus 28. The angle detector 26, in accordance with 
the present invention, produces a signal on bus 30 representing the angle 
.theta. corresponding to the angle between the chrominance vector C and 
the I sampling axis. The angle signal .theta. is applied as address codes 
to ROM's 32 and 34 which produce respectively, the sine and cosine values 
of the arguments corresponding to the address codes applied to their 
address inputs. For angles .theta., which do not reside within the range 
of angles ascribed to flesh tones, the ROM's are programmed to output the 
sines and cosines of the applied angle values. For angles .theta., which 
are within the range of angles associated with flesh tones, the ROM's 
produce sines and cosines of angles corresponding to 
.theta.+.DELTA..theta. where .DELTA..theta. represents the desired 
rotation and is a function of .theta.. 
The cosine and sine values are respectively applied to multipliers 36 and 
38 wherein they are multiplied by the magnitude values C generating the 
flesh-corrected component vectors I'=C cos .theta.' and Q'=C sin .theta.' 
on the buses 40 and 42. 
FIG. 2 illustrates the circuitry embodying the present invention, which may 
be substituted for the phase detector 26 of FIG. 1. Basically, the FIG. 2 
circuitry 26 generates the tangent values of angles varying from zero to 
forty-five degrees by dividing the magnitudes of the smaller of the 
orthogonal I and Q signals by the magnitudes of the larger of the two 
orthogonal signals, and then transposes these angle values between 
0.degree. to 45.degree. into the associated instantaneous phase angles of 
the chrominance vector C over the full range from 0.degree. to 
360.degree.. 
To this end, the signal sample sequence comprising I and Q sample values 
present at the terminal 22 is applied via an input bus 50 to the element 
52, which produces the logarithmic values Log.sub.B .vertline.I.vertline. 
and Log.sub.B .vertline.Q.vertline. to the base B on the output bus 54. 
The element 52 may include a ROM having an input port to which the I and Q 
sample values are applied as address codes. The memory locations 
corresponding to the respective address codes may be programmed to provide 
the associated logarithmic values at the output port of the ROM 52. The 
use of a ROM for determining logarithmic values eliminates the necessity 
of real time calculations. 
The base B to which logarithms are taken is selected to obtain high 
accuracy by maximizing the use of the available bits of the digital 
logarithms. Specifically, for a system arranged to process N-bit 
logarithmic values corresponding to M-bit signal samples including a sign 
bit, the logarithmic base B is equal to 
##EQU1## 
where Ln designates the Naperian logarithm. 
The Log.sub.B .vertline.I.vertline. and the Log.sub.B .vertline.Q.vertline. 
values on the bus 54 are temporarily stored in the respective latches 56 
and 58, along with the associated sign bits present on the link 60, in 
response to the appropriate I and Q clock signals. 
The I and Q samples on the bus 50 are also fed to an element 62, which 
generates a zero-value flag (e.g., 1) on the output connection 64 whenever 
either I or Q samples assume a value equal to zero. The latches 56 and 58 
additionally store the zero-value flags in response to the respective I 
and Q clock signals. The zero-value flags, available on the output links 
66 and 68 of the respective latches 56 and 58, are applied to an element 
70, which, in turn, produces another zero-value flag (e.g., 1) on its 
output connection 72, any time either I or Q sample value is zero. The 
zero-value flag on the output connection 72 is used to set the calculated 
value of the angles .alpha. equal to zero in the manner indicated later. 
The Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. 
values, present on the respective buses 74 and 76, are fed to a subtracter 
78, which generates a value equal to Log.sub.B .vertline.Q.vertline. 
-Log.sub.B .vertline.I.vertline. on the output bus 80. An element 82, 
coupled to the subtracter 78, produces on its output bus 84 the absolute 
negative value corresponding to the associated input value. The absolute 
negative value determining element 82 may, in turn, consist of a device 
that determines the absolute positive value followed by a device that 
determines a 2's complement. This arrangement produces on the bus 84 a 
value equal to the logarithm of the smaller of the I,Q magnitude values 
minus the logarithm of the larger of the two magnitude values, without 
actually having to determine which of the two sample values is larger and 
vice versa. The value on the bus 84 corresponds to the logarithm of a 
quotient obtained by dividing the smaller of the I,Q magnitude values by 
the larger of the two magnitude values. 
Alternatively, it is possible to replace the subtracter 78 and the absolute 
negative value determining element 82 with a device for determining the 
larger and the smaller of the respective Log.sub.B .vertline.I.vertline. 
and Log.sub.B .vertline.Q.vertline. magnitude values, and a subtracter for 
subtracting the larger logarithmic sample value from the smaller 
logarithmic sample value. Reference may be made to U.S. patent 
application, Ser. No. 554,083, of Fling et al., and entitled "A HUE 
CORRECTION CIRCUIT FOR A DIGITAL TV RECEIVER" for an illustration of the 
alternative arrangement of the aforesaid type. 
The value on the bus 84 representative of the logarithm of the quotient 
formed by dividing the smaller of the I and Q magnitude values by the 
larger of the two values is fed to an element 86, which produces an angle 
.alpha. equal to the arctangent of the respective quotient, over a 
0.degree. to 45.degree. range, on the output bus 88 in the manner 
explained subsequently. 
The relationship between the angle .alpha. in degrees calculated by the 
element 86 and the phase .theta. of the vector sum C of the mutually 
perpendicular component signals I and Q will now be explained in 
conjunction with FIGS. 3 and 4. FIG. 3 is a phasor diagram showing the 
axes of the I and Q chrominance signal components and an instantaneous 
chrominance vector C. The intersection of the I and Q axes form four 90 
degree quadrants, with the zero angular reference being along the positive 
I axis. The phase angle .theta. of the chrominance vector C is measured 
from the positive I axis in the clockwise direction, as indicated in FIG. 
3, for the purpose of the description of the preferred embodiments. The 
four quadrants are divided into eight sectors 1-8 each of which 
encompasses a 45 degree sector. 
The angle .alpha. is defined herein as the angle subtended by the 
chrominance vector C with the axis representing the larger of the two I 
and Q magnitude values. Putting it differently, 
##EQU2## 
In the first section, both I.sub.1 and Q.sub.1 are positive, and I.sub.1 
&gt;Q.sub.1 (i.e., .vertline.Q.sub.1 .vertline.-.vertline.I.sub.1 .vertline. 
is negative). In this sector, .theta..degree..sub.1 =.alpha..degree..sub.1 
or .theta..degree..sub.1 =0.degree.+.alpha..degree..sub.1. The sector 
angle, defined as the angle with which the .alpha..degree. value is 
combined to arrive at the phase angle .theta..degree., is zero degrees. 
The sign of the angle .alpha..degree. in the equation defining the 
relationship between .theta..degree. and .alpha..degree. is positive. FIG. 
4 sets forth the sectors, the various signs, the .theta./.alpha. 
equations, the sector angles and the signs of .alpha. in the 
.theta./.alpha. equations. 
When the chrominance vector or phasor C moves into the sector 6, both 
I.sub.2 and Q.sub.2 become negative and .vertline.Q.sub.2 
.vertline.&gt;.vertline.I.sub.2 .vertline. or .vertline.Q.sub.2 
.vertline.-.vertline.I.sub.2 .vertline. is positive. The relationship 
between .theta..degree..sub.2 and .alpha..degree..sub.2 is 
.theta..degree..sub.2 =27.degree.-.alpha..degree..sub.2. From this 
equation, it is seen that the sector angle is 270.degree. and the sign of 
.alpha..degree..sub.2 is negative. Other relations indicated in FIG. 4 can 
be derived in a similar fashion. 
Referring again to FIG. 2, a control element 90 generates the signs of the 
angle .alpha. and the associated sector angles, in accordance with the 
table set forth in FIG. 4, in response to the signs of I,Q and Log.sub.B 
.vertline.Q.vertline.-Log.sub.B .vertline.I.vertline. sample values on the 
respective lines 92, 94 and 96. Circuit 90 may be a lookup ROM, which is 
addressed by the sign signals. An inverter 98 selectively inverts the 
value of .alpha..degree. in response to the control signal on the bus 100 
representing the sign of the angle .alpha..degree. in the .theta./.alpha. 
equation. The value of the angle .alpha..degree. on the bus 102 is passed 
through a gating circuit 104 to a summing circuit 108, where it is 
combined with the sector angle on the bus 110 to generate the phase 
.theta. of the chrominance vector C in the manner indicated in FIG. 4. 
The gating circuit 104 forces the angle .alpha..degree., calculated by the 
element 86, to zero in response to the zero-value flag on the bus 72, 
whenever either I or Q value is zero. This arrangement avoids generation 
of erroneous phase angles any time the chrominance vector C coincides with 
either I or Q axes. 
It will be noted that is not necessary to calculate the actual value of the 
angle .alpha. between 0.degree. to 45.degree. for the purposes of this 
invention. With appropriate modifications, the FIG. 2 circuit can generate 
the phase angle .theta. of the chrominance vector C from any value 
proportional to the actual value of the angle .alpha. --e.g., .alpha.' 
=M.alpha., where M is a proportionality constant. However, for descriptive 
purposes only, the invention herein is often explained in conjunction with 
the value of the angle .alpha. in degrees. 
FIG. 5 depicts the circuitry incorporating the present invention, which may 
be substituted for the element 86 in FIG. 2. The FIG. 5 circuitry 86 
generates an angle .alpha. between 0.degree. and 45.degree. , which is 
related to the phase angle .theta..degree. of the chrominance vector C in 
the manner indicated in FIG. 4. 
The basic equation used to compute the angle .alpha. in radians is as 
follows: 
##EQU3## 
A multiple regression model was fitted to this equation for .alpha. varying 
from 0 to 0.85 radians (about 45.degree.). The values of the constants 
were found to be: 
K.sub.0 =-0.0041 
K.sub.1 =1.0768 
K.sub.2 =-0.2863 
Because K.sub.0 is very small and because it is desirable to avoid large 
percentage errors near .alpha.=0, K.sub.0 is set equal to zero. Thus, the 
new approximation becomes: 
##EQU4## 
The operation of the circuit element 86 can be better understood from the 
following development. 
##EQU5## 
The circuit elements 86 estimates the angle .alpha..degree. from the 
associated value Log.sub.B (tan .alpha.) by using the equation 10. 
Basically, the FIG. 5 circuit 86 has two parts. The upper part calculates 
the value identified by the Roman numeral I in the expression given in the 
equation 10. The lower part, on the other hand, computes the value of the 
expression indicated by the Roman numeral II in the equation 10. 
To this end, a summing circuit 120 adds a value equal to Log.sub.B (L) 
+Log.sub.B (K.sub.1) to the value Log.sub.B (tan .alpha.) on the bus 84. 
The output of the summing circuit 120 is fed via a bus 122 to an 
antilogarithm determining element 124, which may be a ROM 
(read-only-memory) that is programmed to produce on its output bus 126 
values equal to the antilogarithms of the input values applied to the ROM 
as the respective address codes. The value present on the bus 126, 
corresponding to the expression indicated by the Roman numeral I in the 
equation 10, is fed to an adder 128. 
To compute the expression designated by the Roman numeral II in the 
equation 10, the value of Log.sub.B (tan .alpha.) is multiplied by a 
factor of 2 in a multiplier 130 to generate on its output bus 132 a value 
equal to 2.multidot.Log.sub.B (tan .alpha.). The 2's multiplier 130 may be 
a register, where the output bits are left shifted one bit as compared to 
the input. 
A summing circuit 134 adds to the value on the bus 132, equal to 
2.multidot.Log.sub.B (tan .alpha.), a value equal to Log.sub.B (L) 
+Log.sub.B (.vertline.K.sub.2 .vertline.). The output of the summing 
circuit 134 on the bus 136 is applied to an antilogarithm determining 
element 138, which may also be a ROM, to produce on its output bus 140 a 
value corresponding to the expression II in the equation 10. 
The polarity of the value on the bus 140 is reversed by a 2's complement 
circuit 142, and the output thereof on the bus 144 is applied to the adder 
128. The adder 128 combines the values on the buses 126 and 144, 
corresponding to the expressions designated respectively by the Roman 
numerals I and II, in accordance with the equation 10 to generate the 
value of the angle .alpha. in degrees on the bus 88. 
The value of .degree. between 0.degree. and 45.degree. on the bus 88 is 
transformed in the manner indicated in FIG. 2 to produce the associated 
phase angle .theta. of the chrominance vector C. 
For some applications, it is desirable instead to calculate the value of 
.alpha. in some arbitrary units, and not in degrees. For these 
applications, the basic equation 6 for .alpha. can be rearranged as 
follows: 
##EQU6## 
From a comparison of the equations 9 and 12, it will be seen that the 
hardware for calculating the angle .alpha. in the arbitrary units will be 
similar to the FIG. 5 hardware for calculating the angle .alpha. in 
degrees. The only difference is that the term Log.sub.B (L) in the 
equation 9 is replaced by a term Log.sub.B (M) in the equation 12. In the 
interest of brevity, the operation of the circuitry for calculating the 
angle .alpha. in the arbitrary units will not be repeated. 
The modified FIG. 5 circuit for generating the angle .alpha. in the 
arbitrary units can be embodied into the FIG. 2 circuit with appropriate 
changes, so that the angle values .alpha.' in the arbitrary units may be 
translated into the phase angle .theta. of the chrominance vector. 
For other applications, it is not necessary to estimate the actual value of 
the angle .alpha. either in degrees or in the arbitrary units. For these 
applications, it is adequate if a proportional value .alpha." equal to N 
(.alpha./K.sub.1) is generated instead, where N is an arbitrary constant 
(e.g., 256). To this end, the foregoing equation 6 is rearranged as 
follows: 
##EQU7## 
The equation 14 can also be rearranged in the following format: 
##EQU8## 
FIGS. 6 and 7, respectively, depict the circuitry for implementing the 
equations 16 and 18. In the FIG. 6 circuit, the top and the bottom parts 
respectively calculate the values given by the mathematical expressions V 
and VI in the equation 16. On the other hand, the upper and the lower 
parts in the FIG. 7 circuit respectively compute the values corresponding 
to the mathematical expressions indicated by the Roman numerals VII and 
VIII in the equation 18. 
In the FIG. 6 circuit, the value Log.sub.B (tan .alpha.) on the bus 84 is 
fed to the first input of an adder 150. The adder 150 adds a value equal 
to Log.sub.B (N) to its first input, and the output thereof is applied to 
an antilog determining element 152, which produces on the output bus 154 
thereof a value equal to N tan .alpha.. The antilog determining element 
152 may be a ROM. The value of N tan .alpha. on the bus 154 is channeled 
to a subtracter 156. 
In the lower part of the FIG. 6 circuit, the value of Log.sub.B (tan 
.alpha.) on the bus 150 is multiplied by a factor of 2 in a multiplier 158 
to generate on the output bus 160 thereof a value equal 
2.multidot.Log.sub.B (tan .alpha.). A summing circuit 162 adds to the 
value on the bus 160 a value equal to Log.sub.B (N) +Log.sub.B 
(.vertline.K.sub.2 .vertline.) -Log.sub.B (K.sub.1). The output of the 
summing circuit on the bus 164 is applied to another antilog determining 
element 166. The subtracter 156 combines the output of the antilog 
determining element 166 on the bus 168 with the value of N tan .alpha. on 
the bus 154 to produce on its output port a proportional value 
.alpha."=N(.alpha./K.sub.1) in accordance with the equation 16. 
In the FIG. 7 circuit, an adder 180 and an antilog determining element 182 
perform the same functions as the adder 150 and the antilog determining 
element 152 in FIG. 6. The output, N tan .alpha., of the antilog 
determining element 182 on the bus 184 is routed to a subtracter 186. 
In the lower half of the FIG. 7 circuit, a multiplier 188 multiplies the 
value of Log.sub.B (tan .alpha.) on the input bus by a factor 2 to 
generate a value equal to 2.multidot.Log.sub.B (tan .alpha.) on its output 
bus 190. The element 192 determines the antilogarithm of the respective 
input values. The output of the element 192 is multiplied by a factor 
equal to N (.vertline.K.sub.2 .vertline./K.sub.1) in element 196, and the 
output thereof on the bus 198 is fed to the subtracter 186. The subtracter 
186 combines the respective inputs to generate a value .alpha.' equal to N 
(.alpha./K.sub.1) in accordance with the equation 18. 
To simplify the construction of the multiplier 196 in the FIG. 7 circuitry, 
the factor N (.vertline.K.sub.2 .vertline./K.sub.1) can be replaced by a 
value which is equal to the nearest integer power of two. Then a simple 
shift register type circuit may be substituted for the multiplier 196. 
This could provide a good approximation for certain applications. 
The circuitry of FIGS. 6 and 7 may be incorporated into the FIG. 2 circuit 
with appropriate modifications, so that the proportional value .alpha."=N 
(.alpha./K.sub.1) can be transposed into the phase angle .theta. of the 
chrominance vector. 
The subject invention provides a satisfactory approximation for the 
calculation of the phase angle .theta. of the vector sum C of a pair of 
orthogonal signals at lower hardware costs compared to other techniques 
mentioned above.