Biosensor field effect transistor having specific well structure and method of forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a gate structure over a first surface of the substrate, and a source region and a drain region in the substrate adjacent to the gate structure. The semiconductor structure further comprises a channel region interposing the source and drain regions and underlying the gate structure. The semiconductor structure further comprises a first layer over a second surface of the substrate opposite to the first surface, and a second layer over the first layer. The semiconductor structure further comprises a sensing film over the channel region and at least a portion of the first and second layers, and a well over the sensing film and cutting off the first layer and the second layer.

FIELD

The present disclosure relates generally to a semiconductor structure and more particularly to a semiconductor structure of a biosensor.

BACKGROUND

Biosensors are devices for sensing and detecting biomolecules and operate on the basis of electronic, electrochemical, optical, and mechanical detection principles. Biosensors that include transistors are sensors that electrically sense charges, photons, and mechanical properties of bio-entities or biomolecules. The detection can be performed by detecting the bio-entities or biomolecules themselves, or through interaction and reaction between specified reactants and bio-entities/biomolecules. Such biosensors can be manufactured using semiconductor processes, can quickly convert electric signals, and can be easily applied to integrated circuits (ICs) and MEMS.

BioFETs (biologically sensitive field-effect transistors, or bio-organic field-effect transistors) are a type of biosensor that includes a transistor for electrically sensing biomolecules or bio-entities. While BioFETs are advantageous in many respects, challenges in their fabrication and/or operation arise, for example, due to compatibility issues between the semiconductor fabrication processes, the biological applications, restrictions and/or limits on the semiconductor fabrication processes, integration of the electrical signals and biological applications, and/or other challenges arising from implementing a large scale integration (LSI) process.

DETAILED DESCRIPTION

In a BioFET, the gate of a metal-oxide-semiconductor field-effect transistor (MOSFET), which controls the conductance of the semiconductor between the BioFET's source and drain contacts, is replaced by a bio- or biochemical-compatible layer or a biofunctionalized layer of immobilized probe molecules that act as surface receptors. Essentially, a BioFET is a field-effect biosensor with a semiconductor transducer. A decided advantage of BioFETs is the prospect of label-free operation. Specifically, BioFETs can avoid costly and time-consuming labeling operations such as the labeling of an analyte with, for instance, fluorescent or radioactive probes.

A typical detection mechanism for BioFETs is the conductance modulation of the transducer due to the binding of a target biomolecule or bio-entity to a sensing surface or a receptor molecule immobilized on the sensing surface of the BioFET. When the target biomolecule or bio-entity is bonded to the sensing surface or the immobilized receptor, the drain current of the BioFET is varied by the potential from the sensing surface. This change in the drain current can be measured and the bonding of the receptor and the target biomolecule or bio-entity can be identified. A great variety of biomolecules and bio-entities may be used to functionalize the sensing surface of the BioFET such as ions, enzymes, antibodies, ligands, receptors, peptides, oligonucleotides, cells of organs, organisms and pieces of organic tissue. For instance, to detect ssDNA (single-stranded deoxyribonucleic acid), the sensing surface of the BioFET may be functionalized with immobilized complementary ssDNA strands. Also, to detect various proteins such as tumor markers, the sensing surface of the BioFET may be functionalized with monoclonal antibodies.

A well is formed in a semiconductor structure of a BioFET. The well is used for receiving the target biomolecule or bio-entity. Because forming the well may comprise oxide thinning processes, dry etching processes and wet etching processes, dimensions of the well are difficult to control. Because of the variations in the processes of manufacturing a BioFET, the sensing surface is non-uniform and the sensing signals are unstable.

A method100of fabricating a BioFET is illustrated inFIG. 1. The method100may include forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. It is understood that additional steps can be provided before, during, and after the method100, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. Further, it is understood that the method100includes steps having features of a typical CMOS technology process flow and thus, are only described briefly herein.

FIG. 1is a flowchart of a method of manufacturing a BioFET as shown inFIGS. 2A-2K. In operation101, a substrate is provided. In operation102, a gate structure is formed over a first surface of the substrate. In operation103, a source region and a drain region are formed in the substrate and adjacent to the gate structure. In operation104, a channel region is formed to interpose the source and drain regions and underlying the gate structure. In operation105, a first layer is formed over a second surface of the substrate opposite to the first surface. In operation106, a second layer is formed over the first layer. In operation107, a sensing film is formed over the channel region and over at least a portion of the first and second layers. In operation108, a well is formed over the sensing film and cuts off the first layer and the second layer.

FIGS. 2A-2Kschematically illustrate operations of the method ofFIG. 1. InFIG. 2A, a substrate201is provided.FIG. 2Aschematically illustrates the operation101. InFIG. 2B, a gate structure205is formed over a first surface203of the substrate201. The gate structure205comprises a gate electrode202and a gate dielectric layer204and/or other suitable layers.FIG. 2Bschematically illustrates the operation102. InFIG. 2C, a source region (206or207) and a drain region (206or207) in the substrate201adjacent to the gate structure205are formed. In some embodiments, the thicknesses of the source region and the drain region (206and207) are equal to or less than the thickness of the substrate201.FIG. 2Cschematically illustrates the operation103. InFIG. 2D, a channel region208is formed to interpose the source region (206or207) and the drain region (206or207) and underlying the gate structure205.FIG. 2Dschematically illustrates the operation104. The source and drain regions (206and207), the channel region208and the gate structure205form a field effect transistor (FET)209. The FET209may be an n-type FET or a p-type FET. The source/drain regions (206and207) may comprise n-type dopants or p-type dopants depending on the FET configuration. InFIG. 2E, a first layer210is formed over a second surface211of the substrate201opposite to the first surface203.FIG. 2Eschematically illustrates the operation105. InFIG. 2F, a second layer212is formed over the first layer210. In some embodiments, the first layer210may be one of a nitride layer and an oxide layer, and the second layer212may be another one of a nitride layer and an oxide layer different from the first layer210.FIG. 2Fschematically illustrate the operation106. InFIG. 2G, a photoresist213is formed and patterned over the second layer212. InFIG. 2H, a portion of the second layer212not protected by the photoresist213is removed. InFIG. 2I, a portion of the first layer210is removed. InFIG. 2J, the photoresist213is removed. InFIG. 2K, a sensing film214is formed over the channel region208and over at least a portion of the first layer210and the second layer212. A well215is formed over the sensing film214and cuts off the first layer210and the second layer212.FIGS. 2G-2Kschematically illustrate the operations107and108. The semiconductor structure ofFIG. 2Kcan be used to control dimensions of the well215.

In some embodiments, the gate electrode202includes polysilicon. Other exemplary gate electrodes include metal gate electrodes including metal such as, Cu, W, Ti, Ta, Cr, Pt, Ag, Au; suitable metallic compounds like TiN, TaN, NiSi, CoSi; combinations thereof; and/or other suitable conductive materials. In some embodiments, the gate dielectric204is composed of silicon oxide. Other exemplary gate dielectrics include silicon nitride, silicon oxynitride, a dielectric with a high dielectric constant (high k) ranging from about 5 to about 100, and/or combinations thereof. Examples of high k materials include hafnium silicate, hafnium oxide, zirconium oxide, aluminum oxide, tantalum pentoxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or combinations thereof. The FET209may be formed using typical CMOS processes such as, photolithography; ion implantation; diffusion; deposition including physical vapor deposition (PVD), metal evaporation or sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HDPCVD), atomic layer CVD (ALCVD), or spin on coating; etching including wet etching, dry etching, and plasma etching; and/or other suitable CMOS processes.

In some embodiments, the first layer210and the second layer212are adjacent and differ in etch rate to a predetermined etchant. As illustrated inFIG. 2I, the predetermined etchant can be the etchant used to remove the first layer210thereby exposing a surface201aof the substrate201. The exposed surface201aof the substrate is on an opposite side of the gate structure205. In some embodiments, the exposed surface201ais substantially located around the second surface211if the substrate201is highly resistant to the predetermined etchant. In some embodiments, the exposed surface201ais proximal to the first surface203compared to the second surface211. Therefore, a recessed portion of the second surface211might be observed wherein a lateral width W1of the recessed portion is defined by the removed portion of the first layer210.

FIG. 2Jillustrates the stacked structure including first layer210and second layer212over the second surface211. In the stacked structure, a recess222is formed to expose a portion of the substrate201. The sidewall of the recess222is in a stepped configuration. A portion of the sidewall is defined by the opening in the first layer210. Another portion of the sidewall is defined by the opening in the second layer212. The opening in the first layer210has a lateral width W1, which is greater than the lateral width W2of the second layer. Relative to the first layer210, the second layer212has a protrusion212aextended inwardly toward the center of the recess222, therefore making the opening of the recess222being smaller than its closed end.

In some embodiments, the first layer210and the second layer212may be one of a nitride layer and an oxide layer. In some embodiments, the first layer210and the second layer212are made of different materials. In some embodiments, the first layer210is a nitride layer. In some embodiments, the first layer210is a silicon nitride layer. In some embodiments, the second layer212is an oxide layer. In some embodiments, the second layer212is a silicon oxide layer. The oxide layer and nitride layer have high etching selectivities of oxide to nitride. The oxide layer and nitride layer can also be etch stop layers for each other. In some embodiments, the thickness of the second layer212is greater than that of the first layer210. For example, the thickness of the first layer210is 1000 angstrom and that of the second layer212is 8000 angstrom. In some embodiments, a portion of the second layer212is removed by etching. An etchant for etching the second layer212stops etching on the first layer210. The etchant may have a selectivity of oxide to nitride greater than 10. In some embodiments, a portion of the first layer210is removed by using materials such as H3PO4. The material removes a portion of the first layer210and stops on the second surface211of the substrate201. In some embodiments, the removed portions of the first layer210and that of the second layer212may be different.

In some embodiments, the sensing film214is made of a high-k material. In some embodiments, the sensing film214is selected from the group comprising Si3N4, Al2O3, TiO2, HfO2, Ta2O5, SnO2and combinations thereof. In some embodiments, the thickness of the sensing film214is about 30 angstrom to about 100 angstrom. As a further example, exemplary sensing film214include HfO2, Ta2O5, Pt, Au, W, Ti, Al, Cu, oxides of such metals, SiO2, Si3N4, Al2O3, TiO2, TiN, ZrO2, SnO, SnO2; and/or other suitable materials. The sensing film214may be formed using CMOS processes such as, for example, physical vapor deposition (PVD) (sputtering), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HDPCVD), or atomic layer CVD (ALCVD). In some embodiments, the sensing film214may include a plurality of layers.

In some embodiments, the sensing film214is considered as a conformal layer capping on the stacked structure over the second surface211. As inFIG. 2K, the sensing film214substantially follows the profile of the recess222inFIG. 2Jso as to form a well215with similar feature of the stacked first layer210and the second layer212. The sidewall of the well215is also in a stepped configuration. A portion of the well215is defined by the opening in the first layer210and the thickness of the sensing film214. Another portion of the well215is defined by the opening in the second layer212and the thickness of the sensing film214. The well215has at least two different lateral widths, wherein W2is the lateral width of the portion close to the opening of the well215and W1′ is the lateral width of the portion close to the closed end of the well215. The closed end of the well215is also configured as a surface for receiving the biomolecules.

Referring back toFIG. 2F, the second layer212is formed over the first layer210. In some embodiments, a third layer216can be formed over the second layer212. Referring toFIG. 2L, a third layer216is formed over the second layer212. In some embodiments, the third layer216is deposited over the second layer212. InFIG. 2M, a photoresist213is formed and patterned over the third layer216. InFIG. 2N, a portion of the third layer216not protected by the photoresist213is removed. InFIG. 2O, a portion of the second layer212is removed. InFIG. 2P, a portion of the first layer210is removed. InFIG. 2Q, the photoresist213is removed. InFIG. 2R, a sensing film214is formed over the channel region208and over at least a portion of the first layer210, the second layer212and the third layer216. A well215is formed over the sensing film214and cuts off the first layer210, the second layer212and the third layer216.

In some embodiments, the third layer216is one of a nitride layer and an oxide layer. In some embodiments, the material of the third layer216is the same as that of the first layer210. In some embodiments, the thickness of the third layer216is greater than that of the first layer210and the second layer212. For example, the thickness of the third layer216is 8000 angstrom, the thickness of the first layer210is 1000 angstrom and the thickness of the second layer212is also 1000 angstrom. The first, second, and third layers can each be an etch stop layer for one another. In some embodiments, a portion of the third layer216is removed by etching. A first etchant for etching the third layer216stops etching on the second layer212. The first etchant may have a selectivity of oxide to nitride greater than 10. In some embodiments, a portion of the second layer21is removed by etching. A second etchant for etching the second layer212stops etching on the first layer210. The second etchant may have a selectivity of oxide to nitride different from the first etchant. In some embodiments, the second etchant may have a lesser selectivity of oxide to nitride than the first etchant. For example, the second etchant may have a selectivity of oxide to nitride greater than 5. In some embodiments, a portion of the first layer210is removed using a material such as a buffer oxide etch (BOE). The material removes the portion of the first layer210and stops on the second surface211of the substrate201. In some embodiments, the removed portions of the first layer210, the second layer212and the third layer216may be different. In some embodiments, the width of the removed portion of the third layer216and that of the first layer210are greater than that of the second layer212. The semiconductor structure ofFIG. 2Rcan be used to control dimensions of the well215.

In some embodiments, the first layer210, the second layer212and the third layer216are adjacent and differ in etch rate to a predetermined etchant. As illustrated inFIG. 2P, the predetermined etchant can be the etchant used to remove the first layer210thereby exposing a surface201aof the substrate201. The exposed surface201aof the substrate is on an opposite side of the gate structure205. In some embodiments, the exposed surface201ais substantially located around the second surface211if the substrate201is highly resistant to the predetermined etchant. In some embodiments, the exposed surface201ais proximal to the first surface203compared to the second surface211. Therefore, a recessed portion of the second surface211might be observed. The recessed portion of the second surface211has a lateral width W3which is defined by the removed portion of the first layer210.

FIG. 2Qillustrates the stacked structure including first layer210, the second layer212and the third layer216over the second surface211. In the stacked structure, a recess222is formed to expose a portion of the substrate201. The sidewall of the recess222is in a stepped configuration. One portion of the sidewall is defined by the opening in the first layer210. Another portion of the sidewall is defined by the opening in the second layer212. The other portion of the sidewall is defined by the opening in the third layer216. The opening in the first layer210has a lateral width W3, which is greater than the lateral width W4of the second layer. The opening in the third layer216has a lateral width W5, which is greater than the lateral width W4of the second layer. The lateral width W5of the opening in the third layer216may be greater than, equal to or less than the lateral width W3of the first layer210. Relative to the first layer210, the second layer212has a protrusion212aextended inwardly toward the center of the recess222.

In some embodiments, the sensing film214is considered as a conformal layer capping on the stacked structure and over the second surface211. As inFIG. 2R, the sensing film214substantially follows the profile of the recess222inFIG. 2Qso as to form a well215with similar feature of the stacked first layer210, second layer212and third layer216. The sidewall of the well215is also in a stepped configuration. One portion of the well215is defined by the opening in the first layer210and the thickness of the sensing film214. Another portion of the well215is defined by the opening in the second layer212and the thickness of the sensing film214. The other portion of the well215is defined by the opening in the third layer216and the thickness of the sensing film214. The well215has three different lateral widths, wherein W4′ is the lateral width of the portion of the middle of the opening of the well215, W3′ is the lateral width of the portion close to the closed end of the well215, and W5′ is the lateral width of the portion close to the opening of the well215. The closed end of the well215is also configured as a surface for receiving the biomolecules.

In some embodiments, the substrate201inFIG. 2Ais a semiconductor on insulator (SOI) substrate. As shown inFIG. 3A, a SOI substrate201may include a buried oxide (BOX) layer302formed over a semiconductor layer301. The BOX layer302may be formed by a process such as separation by implanted oxygen (SIMOX), and/or other suitable processes. A first surface of the SOI substrate201is the device side where the gate structure209is formed. In some embodiments, the thickness of the BOX layer302is initially 10,000 angstrom, as shown inFIG. 3A. In some embodiments, the BOX layer302is thinned down to 1000 angstrom by BOE, as shown inFIG. 3B. In some embodiments, the removal of the BOX layer302may be accomplished by mechanical or chemical means. For example, mechanical means includes polishing or grinding, such as chemical mechanical polishing (CMP). A chemical means includes wet etch, such as HNA or TMAH, or dry etch including plasma and non-plasma etch. In some embodiments, a portion of the BOX layer302may be remained and configured as the first layer210, as shown inFIG. 3B. In some embodiments, the BOX layer302of the SOI substrate201is completely removed. Under such condition, the substrate201is a semiconductor substrate, as shown inFIG. 3C. In some embodiments, the BOX layer302is removed to expose a second surface303of the SOI substrate201. The substrate201inFIG. 3Cmay be a silicon substrate. Alternatively, the substrate201may comprise another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide; an alloy semiconductor including silicon germanium; or combinations thereof.

The same reference numerals in different drawings refer to the same element.FIG. 4illustrates a semiconductor structure formed with the substrate201inFIG. 3B. The difference between the structure inFIGS. 4 and 2Ris that the first layer210inFIG. 4is formed from a portion of the BOX layer302inFIG. 3Bwhile the first layer210inFIG. 2Ris formed with the substrate201inFIG. 3C. The other operations for manufacturing the semiconductor structure shown inFIGS. 2R and 4are substantially the same. Relative to the first layer210, the second layer212has a protrusion212aextended inwardly toward the center of the well215, therefore forming a necking portion in the well215.

In some embodiments, the sensing film214may be formed prior to forming the first layer210. InFIG. 5A, a field effect transistor (FET)209is provided. A sensing film214is formed over the second surface211of the substrate201opposite to the first surface203. InFIG. 5B, a first layer210is formed over the sensing film214. InFIG. 5C, a second layer212is formed over the first layer210. In some embodiments, the first layer210may be one of a nitride layer and an oxide layer, and the second layer212may be another one of a nitride layer and an oxide layer different from the first layer210. InFIG. 5D, a third layer216is formed over the second layer212. InFIG. 5E, a photoresist213is formed and patterned over the third layer216. InFIG. 5F, a portion of the third layer216not protected by the photoresist213is removed. InFIG. 5G, a portion of the second layer212is removed. InFIG. 5H, a portion of the first layer210is removed. InFIG. 5I, the photoresist213is removed. A well215is formed over the sensing film214and cuts off the first layer210, the second layer212and the third layer216. The semiconductor structure ofFIG. 5Ican be used to control dimensions of the well215.

FIG. 5Iillustrates the stacked structure including first layer210, the second layer212and the third layer216over the second surface211. In some embodiments, the opening in the first layer210has a lateral width W6, which is greater than the lateral width W7of the second layer212. The opening in the third layer216has a lateral width W8, which is also greater than the lateral width W7of the second layer212. In some embodiments, the lateral width W8of the opening in the third layer216may be greater than, equal to or less than the lateral width W6of the first layer210. In some embodiments, the lateral lengths W6, W7and W8may be the same. In some embodiments, relative to the first layer210, the second layer212has a protrusion212aextended inwardly toward the center of the well215.

As inFIG. 5I, the sensing film214substantially overlies on the second surface211of the substrate. The sidewall of the well215is in a stepped configuration. One portion of the well215is defined by the opening in the first layer210. Another portion of the well215is defined by the opening in the second layer212. The other portion of the well215is defined by the opening in the third layer216. The well215has three lateral widths, wherein W7is the lateral width of the portion of a necking portion of the opening of the well215, W6is the lateral width of the portion close to the closed end of the well215and W8is the lateral width of the portion close to the opening of the well215. The closed end of the well215is also configured as a surface for receiving the biomolecules.

Referring toFIG. 6A, the FET device209includes a gate structure205formed over a first surface203of the substrate201and a channel region208in the substrate201below the gate structure205. A BOX layer601is formed over a second surface211of the substrate201. Referring toFIG. 6B, the first surface203of the substrate201is attached to a carrier substrate602. In some embodiments, additional layer(s)603is formed over the FET209, including metal interconnect layers, dielectric layers, passivation layers, bonding metal layers, and any other material layers typically formed to complete a semiconductor device. InFIG. 6B, a layer603is disposed over the FET209between the FET209and a carrier substrate602. The layer603may include a multi-layer interconnect (MLI) structure. The MLI structure may include conductive lines, conductive vias, and/or interposing dielectric layers (e.g., interlayer dielectric (ILD)). The MLI structure may provide physical and electrical connections to the FET209at the source and drain regions (206and207) and at the gate electrode layer202. The conductive lines may comprise copper, aluminum, tungsten, tantalum, titanium, nickel, cobalt, metal silicide, metal nitride, poly silicon, combinations thereof, and/or other materials possibly including one or more layers or linings. The interposing or inter-layer dielectric layers (e.g., ILD layer(s)) may comprise silicon dioxide, fluorinated silicon glass (FGS), SILK (a product of Dow Chemical of Michigan), BLACK DIAMOND (a product of Applied Materials of Santa Clara, Calif.), and/or other insulating materials. The MLI may be formed by suitable processes typical in CMOS fabrication such as CVD, PVD, ALD, plating, spin-on coating, and/or other processes.

The carrier substrate602is attached to the substrate by bonding. In some embodiments, the carrier substrate602is bonded to the last MLI layer. In an embodiment, the carrier substrate is bonded to a passivation layer formed on the MLI and/or ILD layers of the substrate. The carrier substrate602may be attached to the substrate201using fusion, diffusion, eutectic bonding, and/or other suitable bonding methods. Exemplary compositions for the carrier substrate602include silicon, glass, and quartz. In some embodiments, the carrier substrate602may include other functionalities such as; interconnect features, bonding sites, defined cavities, and/or other suitable features.

Referring toFIG. 6C, the channel region208of the FET209is exposed away from the second surface211of the substrate201. Depending on the type of substrate201, a number of methods may be used to expose the channel region208. In some embodiments, the substrate201is formed with an SOI substrate. The BOX layer of the SOI substrate is first thinned until the second surface211of the substrate201. A first thinning may be accomplished by grinding, wet etch, dry etch, plasma etch and/or other suitable processes. In order to avoid plasma induced damage (PID) with residual charge at the channel region208of the FET209, a non-plasma etch is used in this operation or at least as the last thinning step. In some embodiments, a wet etch or a non-plasma dry etch is used to thin the entire substrate201from the second surface211to the channel region208. In some embodiments, a first thinning, which may include plasma etch, is performed first to reduce the thickness of the substrate201, and a last etch operation uses a non-plasma etch to expose the channel region208at the second surface211of the substrate201. The non-plasma etch avoids plasma induced damage (PID) with residual charge at the channel region208of the FET209.

Referring toFIG. 6D, a sensing film214is formed over the second surface211of the substrate201opposite to the first surface203. In some embodiments, the sensing film is selected from the group comprising Si3N4, Al2O3, TiO2, HfO2, Ta2O5, SnO2and combinations thereof. InFIG. 6E, a first layer210is formed over the sensing film214. InFIG. 6F, a second layer212is formed over the first layer210. InFIG. 6G, a photoresist213is formed and patterned over the second layer212. InFIG. 6H, a portion of the second layer212not protected by the photoresist213is removed. InFIG. 6I, a portion of the first layer210is removed. InFIG. 6J, the photoresist213is removed and a well215is formed over the sensing film214and cuts off the first layer210and the second layer212. In some embodiments, a third layer can be formed over the semiconductor structure shown inFIG. 6J. The semiconductor structure comprising the third layer is similar to the semiconductor structure shown inFIG. 5I.

In some embodiments, a semiconductor structure comprises a substrate, a gate structure over a first surface of the substrate, and a source region and a drain region in the substrate adjacent to the gate structure. The semiconductor structure further comprises a channel region interposing the source and drain regions and underlying the gate structure. The semiconductor structure further comprises a first layer over a second surface of the substrate opposite to the first surface, and a second layer over the first layer. The semiconductor structure further comprises a sensing film over the channel region and at least a portion of the first and second layers, and a well over the sensing film and cutting off the first layer and the second layer.

In some embodiments, the first layer is one of a nitride layer and an oxide layer. In some embodiments, the second layer is one of a nitride layer and an oxide layer. In some embodiments, the first and second layers are of different materials. In some embodiments, the semiconductor structure further comprises a third layer over the second layer. In some embodiments, the third layer is one of a nitride layer and an oxide layer. In some embodiments, the material of the third layer is the same as that of the first layer. In some embodiments, the thickness of the third layer is different from that of the first layer. In some embodiments, the sensing film comprises a material with a dielectric constant ranging from 5 to 100. In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate.

In some embodiments, a semiconductor structure comprises a FET device on a substrate, wherein the FET device includes a gate structure formed over a first surface of the substrate and a channel region in the substrate below the gate structure. In some embodiments, the first surface of the substrate is attached to a carrier substrate and the channel region is away from a second surface of the substrate. In some embodiments, a sensing film is formed over the channel region on the second surface of the substrate opposite to the first surface. In some embodiments, a first layer is formed over the sensing film and a second layer is formed over the first layer. In some embodiments, a well is formed over the sensing film and cutting off the first layer and the second layer.

In some embodiments, the semiconductor structure further comprises a third layer over the second layer. In some embodiments, relative to the first layer, the second layer has a protrusion extended inwardly toward the center of the well. In some embodiments, the well is defined by the openings in the first, second and third layers. In some embodiments, the lateral widths of the first, second and third layer are different. In some embodiments, the lateral width of the first layer is greater than the widths of the second and third layers.

In some embodiments, a method for forming a semiconductor structure comprises forming a substrate, forming a gate structure over a first surface of the substrate, and forming a source region and a drain region in the substrate adjacent to the gate structure. The method further comprises forming a channel region interposing the source and drain regions and underlying the gate structure. The method further comprises forming a first layer over a second surface of the substrate opposite to the first surface and forming a second layer over the first layer. The method further comprises forming a sensing film over the channel region and over at least a portion of the first and second layers, and forming a well over the sensing film and cutting off the first layer and the second layer.

In some embodiments, the method further comprises forming a third layer over the second layer. In some embodiments, the etching selectivity of the second layer and that of the third layer are different. In some embodiments, forming the well over the channel region and cutting off the first layer and the second layer further comprises removing a portion of the first layer and the second layer by etching.