Obscuring information in virtualization environment

A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated it is provided to the hypervisor.

BACKGROUND

The present disclosure relates to hypervisor operation, and more specifically, to obscuring time-base information from a hypervisor in a multi-tenant server.

Applications and operating systems may operate on a computer system. The computer system may be a memory, processor, and input output interface (I/O). The computer system may be a virtual computer system operated by a hypervisor. Some clients may prefer the flexibility of a virtual computer system. These clients may also prefer more security over information while operating on a virtual computer system.

SUMMARY

According to some embodiments, disclosed is a system, method and computer program product. A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining that the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated, it is provided to the hypervisor.

DETAILED DESCRIPTION

Aspects of the present disclosure relate to hypervisor operation; more particular aspects relate to obscuring time-base information from hypervisor in a multi-tenant server. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

In an application and operating system (OS) hosting environment, OS instances provided by a provider may run on a hypervisor maintained by the provider. For example, in a cloud environment, OS instances can run as guest machines on a hypervisor maintained by the cloud provider, with the OS instances running as separate partitions on the same physical system. In some situations, a hypervisor is entitled to access any partition's data. Access of any partition by a hypervisor may create a security risk, as a provider could access any information from the OS (and applications running inside the OS) including sensitive data of users. This issue may be compounded as cloud providers may guarantee data privacy or regulations may dictate the protection of sensitive data.

One class of solutions involve introducing a privilege level above the hypervisor (e.g., the privilege level above the hypervisor is a privilege level that is considered trusted) which may intercept any exceptions from the partitions considered secure going to the hypervisor. For example, an ultravisor may have an elevated privilege level in comparison to a hypervisor.

An elevated privilege handler for exceptions (e.g., at a level above the hypervisor) may obscure the values of hardware registers accessible to the hypervisor. For example, values in various hardware registers store information from user programs or OS (“applications”). These values and hardware registers that correspond to applications operating on a virtual machine provided by a hypervisor may be inspected and viewed by the hypervisor. Providing an elevated level of privilege above the hypervisor may allow for various values and hardware registers that correspond to applications to be viewed as encrypted from the point of view of the hypervisor.

In another example, a save operation or a restore operation (“memory operation”) to some portion of memory (e.g., virtual memory provided to the applications by a hypervisor) and the hypervisor may be able to access the same portions of virtual memory. By not allowing a hypervisor access to a portion of memory, certain memory operations may be prevented. A portion of virtual memory not accessible by a hypervisor may be a secure memory. The hypervisor in these examples may be provided only the exact amount of information necessary to perform the various operations and may not be provided access to the secure memory.

There are issues with elevated privilege levels such as those used by ultravisors. Many modern computer architectures operate on techniques called multiprocessing. Multiprocessing may allow a user program or an OS to handle multiple processes or threads at the same time. Multiprocessing may allow these applications to perform with increased efficiency or with higher processing throughput. Multiprocessing may rely on very specific hardware requests. For example, applications may send hardware requests to various registers of a processor to perform a multithreading operation. These various registers may be special purpose registers such as counters, decrementers, or incrementers.

A counter (a register that counts down with processor clock and generates a timer interrupt when it crosses zero) may be an essential register to a user program or an OS, as it is the source of timer interrupts. A counter may be a fundamental hardware mechanism for pre-emptive process scheduling deployed in many modern operating systems. The counter may be hypervisor accessible in certain cases (e.g., due to legacy reasons). With the introduction of an ultravisor, the counter may also be obscured from the hypervisor; obscuring a counter may be beneficial to try and prevent the hypervisor from being otherwise exploited for performing timing attacks by the hypervisor.

If various special purpose registers such as the counter are obscured from the hypervisor, an unintended consequence is that the applications running in the virtual machine may run with worse performance. For example, certain counters and other special purpose registers are used to accurately share processing resources and to perform context switches between various components. A scheduler, a context switcher, a stack pointer, a program counter, or other relevant processing hardware register may rely on accurate counter values from the processors (and in the case of virtual machines, the hypervisor). During the operations of some ultravisors and other elevated privilege operations, obscured counters are provided to and received from the hypervisor. The ultravisor records the original values, stores the values in some secure region of memory inaccessible to the hypervisor, and restores the values before going back into the guest virtual machine or process. This method may be sufficient for registers that do not decrement or increment with processor clocks or are not a function of a processor clock (i.e., registers not intended for time measurement in any way), but for the registers that are indeed related with the processor clock, this method leads to the restored value from secure memory being incorrect.

When a guest virtual machine or application operates based on obscured values, processes and threads may be given more or less computer resources to perform operations than they require. For example, inaccurate time slicing of multiple parallel executions of program code (e.g., threads, processes) may prevent certain program code from finishing in time. If a certain portion of program code does not finish before being interrupted, it may be requeued, become stalled, or even crash. With an inaccurate counter a portion of program code may be finished without an interrupt corresponding to the program finishing. A lagging interrupt coming after actual finishing of program code execution may consequently cause a processor to sit idle for many cycles. Further, programs that do not finish and are requeued may lead to repeated switches between processes/threads to reperform the work that was finished and interrupted, causing wasted cycles or program slowdowns. Further, the act of stopping executing of a first segment of program code and starting execution of a second program code may have overhead in processing, memory, or I/O of the computer.

A counter aware ultravisor (CAUV) may overcome the issues of other ultravisors by providing obscured or scrambled counters to a hypervisor while translating and returning counters to applications that provide relevant values for performing multiprocessing. A CAUV may provide a placeholder value to a hypervisor that may obscure information from the hypervisor. The CAUV may also measure the time spent in the hypervisor and may adjust the value after operation is performed by the hypervisor but before restoring the values to the OS or any programs running on the OS. By obscuring information before providing it to a hypervisor, a CAUV may maintain security for all guest virtual machines that run with an ultravisor or other relevant elevated privilege system. By keeping track of the various system-level counters and special purpose hardware registers involved in a multiprocessing operation of applications, the CAUV may enable an OS to maintain the accuracy of low-level program counters and provide accurate quality of service.

FIG.1depicts an example computing environment100that leverages secure guest machines and time-based accuracy, consistent with some embodiments of the disclosure. Computing environment100, may include the following: a plurality of computer systems110-1,110-2,110-3to110-n(collectively,110); one or more guest computers120-1,120-2to120-n(collectively,120); and a virtualization environment130for hosting the guest computers120. Computer systems110may include physical memory, physical processing resources, and physical I/O for facilitating and hosting the virtualization environment130.FIG.3depicts an example computer system300capable of performing hosting consistent with some embodiments of the disclosure. The computer systems110may be located at a datacenter. In some embodiments, the computer systems110may be separated geographically. For example, computer system110-1may be located at a first location, and computer system110-2geographically disparately from computer system110-1.

The guest computers120may be in the form of virtual machines and secure virtual machines. For example, guest computer120-1may be a virtual machine that is served hardware resources of computer system110-1and110-3from the virtualization environment130. In another example, guest computer120-2may be a secure virtual machine that is server hardware resources from the virtualization environment130. The guest computers120may make reference to hardware in the form of hardware requests (e.g., arithmetic logic units of a processor, memory references to cache, counters, read commands to dynamic random access memory (DRAM), and store commands to tertiary storage devices).

The virtualization environment130may be configured to host various computer systems, including guest computers120. The virtualization environment130may be a combination of hardware, firmware, and software for hosting virtual machines and may execute on the computer systems110. Virtualization environment130may be provided by a service provider that is operated by a separate entity from the guest computers120. For example, virtualization environment130may be a cloud-based service provider that provides computer systems110to various clients. A service provider of the virtualization environment130may guarantee various levels of privacy and computer performance.

The virtualization environment130may include the following: a memory space140for storing program data, operating system data, and virtualized hardware registers; a secure memory space150for storing program data, operating system data, and virtualized hardware registers; a hypervisor160for serving various hardware requests of the guest computers120; and an ultravisor for serving various hardware requests of the guest computers120. Virtualization environment130may also include other components, such as a trusted platform module (TPM) (not depicted).

The virtualization environment130may instantiate or create guest computers120in response to requests from parties requesting computer resources from the cloud provider. For example, a client may request computer resources, and responsively, the hypervisor160may allocate guest computer120-1by reserving resources of the underlying computer systems and reserving a portion of memory space140for the execution of guest computer. The programs122-1and124-1may operate on guest computer120-1and all low-level registers and memory corresponding to operation of the guest computer120-1may be stored in the memory space140. As program122-1executes and as various program counters, context switches, and other relevant multiprocessing operations are performed, the hypervisor160can observe the data related to these elements.

The virtualization environment130may also instantiate or create guest computers120with elevated security and privacy from the hypervisor. At manufacturing of the computer systems110or the firmware of the virtualization environment130, the creation of a public and private key may be performed—for example, keys generated by the TPM of the virtualization environment130. In some embodiments, each computer system110may generate a separate public and private key. The private key(s) may not be accessible by the provider of the virtualization environment130or by the hypervisor160.

A virtual machine may make a request to be secured and may wrap an encryption key with the public key(s). Responsive to the request, the virtualization environment130may operate to secure the virtual machine from the hypervisor160. For example, guest computer120-2may be created by the hypervisor160in response to a request from a client. Guest computer120-2at this point may be operating as a virtual machine in the memory space140allocated to it by the hypervisor160. A client may generate a security request for sending and receiving data with the guest computer120-2. The guest computer120-2may encrypt the security request with the public key(s) of the virtualization environment130. The ultravisor170may receive the security request from guest computer120-2and, using the public key(s), may move the virtual machine to the secure memory space150, consequently making guest computer120-2a secure virtual machine. Further executing of the OS and user programs (e.g., user program122-2) may exist in the secure memory space150, and the ultravisor170may operate to secure any data inputs of various hardware requests to the hypervisor160. For example, the ultravisor170may intercept and obscure various data inputs of hardware requests, such that the hypervisor160cannot read or otherwise discern information of the data inputs.

The virtualization environment130may also implement a CAUV to maintain accurate counter data of the guest computers120that are operating as secure virtual machines. The CUAV may also protect information from the hypervisor160. For example, a hardware request180may be sent from secure virtual machine120-2to the virtualization environment130. The hardware request180may be directed towards the hypervisor160. The ultravisor170may detect the hardware request180and may determine that the request includes a counter with a counter value (e.g., an 8-bit decrementer). The ultravisor170may intercept the hardware request180before it is sent to the hypervisor160. The ultravisor170may store the counter value in the secure memory space150, and the hypervisor may not be able to access the counter value. The ultravisor170may generate a scrambled or obscured version of the counter value, and may provide the scrambled counter value to the hypervisor160, such that the hypervisor may perform the hardware request with the scrambled counter value. Depicted inFIG.1are a plurality of example operations182for performing an interception of a hardware request to scramble/obscure a counter consistent with some embodiments of the disclosure. The ultravisor170may store the scrambled counter value in the memory space140.

Further, a response190to the hardware request180may be sent by the hypervisor160. The response190may include an updated counter. The updated counter may be based off of the scrambled counter value, obscured by the ultravisor170. The ultravisor170may intercept the response190and may unobscure the update counter. The ultravisor170may unobscure the updated counter by offsetting the counter value stored in the secure memory space150with the difference between the scrambled version of the counter value and the updated counter value of the hypervisor160. The ultravisor170may send the unobscured updated counter in the response190to the virtual machine120-2. Depicted are a plurality of example operation192for performing an interception of a hardware response to descramble/unobscure a counter consistent with some embodiments of the disclosure.

FIG.2depicts an example method200for performing obscuring of timing registers and counter values, consistent with some embodiments of the disclosure. Method200may be performed by a computer system. Computer system300depicted inFIG.3may be configured to perform one or more parts of method200. Method200may be performed by a CAUV consistent with some embodiments of the disclosure.

From start at205, a hypervisor may be monitored at210for traffic between applications and a hypervisor. In some embodiments, applications may be user programs, such as an engineering simulation program, a word processing program, or a graphical rendering program. In some embodiments, applications may be an OS, such as a guest computer hosted by a virtualization system. Monitoring traffic may include monitoring for applications that are running within a secure virtual machine—for example, applications that have initiated a secure session with a CAUV that protects memory and certain operation information from inspection from a hypervisor. In some embodiments, monitoring of traffic may include obscuring, scrambling, or otherwise randomizing (such as by a random number generator) certain data inputs provided to a hypervisor. For example, if a hardware request includes a certain register value, pointer, or other data element that is not necessary for the hypervisor to perform operations for a guest computer, the ultravisor may hide, zero-out, randomize, data shift, or otherwise obscure the data element.

If a hardware request is detected, at215: Y, it will be determined if there is a counter within the hardware request at220. If there is not a counter (220: N), method200ends at295. If there is a counter (220: Y), then the hardware request may be intercepted at230. Intercepting the hardware request may be an active operation. For example, an ultravisor may detect that a hardware request has been placed within a queue for processing by the hypervisor. The ultravisor may intercept the hardware request before the hypervisor can see or inspect the request. The interception of hardware requests may be a reactive operation. For example, hardware requests from secure virtual machines may be encrypted such that only the ultravisor or another secure element of a virtualization environment can read the hardware request while the hypervisor cannot read the hardware request until it has been unencrypted.

A counter within the intercepted hardware request may be saved at240. The counter may be a reference, pointer, value, or other data element of a computer system (e.g., a program counter, a decrementer, a special purpose register, a multiprocessing register, a multithreading register). The counter may include a counter value (e.g., a 3-bit value, an 8-bit value). The counter value in the intercepted request may be obscured at250. Obscuring of the counter value may include scrambling, randomizing (e.g., by a TPM), byte shifting, zeroing-out, or otherwise inserting data unrelated to the counter value. Obscuring of the counter value may include changing the counter value such that upon inspection by a hypervisor, no meaningful information may be discerned by the hypervisor. The obscured counter value may be saved in a memory (e.g., a memory space shared with the hypervisor, or a secure memory space inaccessible by the hypervisor).

At260the updated hardware request may be provided to the hypervisor. Providing the updated hardware request may include providing the hardware request with the obscured counter in a decrypted form to the hypervisor. Providing the updated hardware request may include moving the hardware request with the obscured counter to a queue of the hypervisor. For example, the hypervisor may have a memory space where various requests and working memory of the hypervisor reside. Providing the updated request at260, may include an ultravisor moving the updated request to the memory space from a secure memory not accessible by the hypervisor. After providing the updated request at260, method200may end at295. In some embodiments, method200may begin again at205and the hypervisor may continue to be monitored at210.

If there is not a hardware request (215: N), a response to a hardware request may be identified at270. In some embodiments, if there is a response identified (270: Y), the response may be blocked from being sent back to the application intended by the hypervisor (e.g., the application that sent the hardware request corresponding to the response). If there is a response to the hardware request by the hypervisor (270: Y), the counter may be descrambled at280.

Descrambling of the counter may include determining the updated counter value from the hypervisor in the response. Descrambling of the counter may include generating an update amount. For example, an ultravisor may compare the updated counter value from the response to the stored obscured counter that was previously provided to the hypervisor. By comparing the values (e.g., subtracting, adding) an updated amount may be calculated. For example, if an obscured counter value is “1011”, and if the updated counter value is “0010”, an updated amount may be “1001.” The updated amount may, consequently, be the difference between a counter value before and after being operated on by the hypervisor. The updated amount may be used to calculate an updated unobscured counter value (e.g., a counter value relevant to the counter provided by an application of a guest computer). For example, if the counter value before being obscured was “1101” and the descrambled counter has an updated amount of “1001”, a calculated updated unobscured counter value would be “0100.” Calculating the updated unobscured counter value may include subtracting the counter value before being obscured from the difference between the obscured counter value and the updated counter value from the hypervisor.

At290the updated unobscured counter value may be provided to the application that sent a hardware request with a counter. Providing the updated unobscured counter value may include inserting the value into the response. Providing the updated unobscured counter value may include encrypting the response before placing the response in an output queue for the guest computer of the application. After the updated unobscured counter value is provided, method200ends at295. In some embodiments, after the updated unobscured counter value is provided, at290, method200may continue to monitor the hypervisor at210.

FIG.3depicts the representative major components of an example computer system300(alternatively, computer) that may be used, in accordance with some embodiments of the present disclosure. It is appreciated that individual components may vary in complexity, number, type, and\or configuration. The particular examples disclosed are for example purposes only and are not necessarily the only such variations. The computer system300may comprise a processor310, memory320, an input/output interface (herein I/O or I/O interface)330, and a main bus340. The main bus340may provide communication pathways for the other components of the computer system300. In some embodiments, the main bus340may connect to other components such as a specialized digital signal processor (not depicted).

The processor310of the computer system300may be comprised of one or more cores312A,312B,312C,312D (collectively312). The processor310may additionally include one or more memory buffers or caches (not depicted) that provide temporary storage of instructions and data for the cores312. The cores312may perform instructions on input provided from the caches or from the memory320and output the result to caches or the memory. The cores312may be comprised of one or more circuits configured to perform one or more methods consistent with embodiments of the present disclosure. In some embodiments, the computer system300may contain multiple processors310. In some embodiments, the computer system300may be a single processor310with a singular core312.

The memory320of the computer system300may include a memory controller322. In some embodiments, the memory320may comprise a random-access semiconductor memory, storage device, or storage medium (either volatile or non-volatile) for storing data and programs. In some embodiments, the memory may be in the form of modules (e.g., dual in-line memory modules). The memory controller322may communicate with the processor310, facilitating storage and retrieval of information in the memory320. The memory controller322may communicate with the I/O interface330, facilitating storage and retrieval of input or output in the memory320.

The I/O interface330may comprise an I/O bus350, a terminal interface352, a storage interface354, an I/O device interface356, and a network interface358. The I/O interface330may connect the main bus340to the I/O bus350. The I/O interface330may direct instructions and data from the processor310and memory320to the various interfaces of the I/O bus350. The I/O interface330may also direct instructions and data from the various interfaces of the I/O bus350to the processor310and memory320. The various interfaces may include the terminal interface352, the storage interface354, the I/O device interface356, and the network interface358. In some embodiments, the various interfaces may include a subset of the aforementioned interfaces (e.g., an embedded computer system in an industrial application may not include the terminal interface352and the storage interface354).

Logic modules throughout the computer system300—including but not limited to the memory320, the processor310, and the I/O interface330—may communicate failures and changes to one or more components to a hypervisor or operating system (not depicted). The hypervisor or the operating system may allocate the various resources available in the computer system300and track the location of data in memory320and of processes assigned to various cores312. In embodiments that combine or rearrange elements, aspects and capabilities of the logic modules may be combined or redistributed. These variations would be apparent to one skilled in the art.

Characteristics are as follows:

Service Models are as follows:

Deployment Models are as follows:

Virtualization layer70provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers71; virtual storage72; virtual networks73, including virtual private networks; virtual applications and operating systems74; and virtual clients75. Virtual applications and operating systems74may operate based on a CAUV consistent with some embodiments of the disclosure.