Modulation methods and systems

A modulation system includes an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to modulation methods and systems for recording digital data on an information medium such as an optical disc, more particularly to modulation methods and systems for minimizing a cumulative digital sum value (DSV) for high-density optical storage systems.

2. Description of the Prior Art

Prior to transmission or recording of digital data, the digital data is usually converted to another data pattern through a certain modulation method. In compact disc (CD) recording systems, the data to be recorded on a compact disc is modulated using EFM (eight-to-fourteen modulation), whereas the data to be recorded on a digital versatile disc (DVD) is modulated using EFM+(eight-to-sixteen modulation). However, during the process of EFM or EFM+modulation, it is important to keep the DSV value as close to zero as possible to allow reliable tracking and reliable detection of high frequency signals. Therefore, there were several methods proposed for keeping the absolute value of the DSV as low as possible to suppress DC (direct current) content during a modulation procedure. In advanced optical discs such as Blu-ray disc (BD), and high density DVD (HD-DVD), to improve the ability of suppressing DC (direct current) content during the modulation procedure, DC (DSV) control bits are included in 17PP modulation for BD and eight-to-twelve modulation for HD-DVD. By controlling the values of DC control bits, the absolute value of the cumulative DSV could be kept as low as possible to suppress DC content during the modulation procedure.

FIG. 1shows a functional block diagram of an 8-16 (EFM+) modulation system for transforming 8bit data word B(t) into 16-bit code words X(t). During the modulation procedure, each 8-bit data word B(t) associated with a current state S(t) is converted to a main code word Xm(t) having 16 channel bits and a main next state Sm(t+1) through a main conversion table11. If the data word B(t) is less than eighty-eight, a comparator13enables a substitution conversion table12to simultaneously output a sub code word Xs(t) and a sub next state Ss(t+1). Meanwhile, a DSV controller14is also enabled to calculate a DSV corresponding to each of the main and sub code words, and select one of the code words to be the output code word X(t). The code word X(t) is selected so as to minimize the absolute value of the cumulative DSV. If the main code word Xm(t) is selected as the code word X(t), the main next state Sm(t+1) is designated as the next state S(t+1). The next state S(t+1) is temporarily stored in the state register15. Similarly, if the sub code word Xs(t) is selected as the code word X(t), the sub next state Ss(t+1) is designated as the next state S(t+1). For DVD modulation, a code word X(t) is obtained through the aforesaid conversion tables11and12when a data word B(t) and the corresponding current state S(t) are known. The code word X(t) is independent from subsequent data word B(t+1).

During the modulation process for a high density optical storage system such as HD-DVD, Blu-ray, or AOD system, a modulation code word is obtained after determination of the DSV control bit. A DSV control bit may not exist in each data word, and ideally, the determination of the DSV control bits should depend upon all the data words so that the overall cumulative DSV is kept to the minimum. Consequently, a large number of registers is required for storing data words or code words during the modulation process, which also result in a long latency delay.

SUMMARY OF THE INVENTION

Modulation methods and systems for recording digital data on an optical storage medium are provided. A DSV control bit is determined before, after, or while converting the data words into codes words, and the determined DSV control bit is used to modify the DSV control bit of a corresponding code word. Embodiments of the modulation method and system are capable of reducing the required buffer capacity, and keeping a constant latency for determining code words.

The DSV control bit is determined when detecting at least one subsequent DSV control bit so as to suppress DC (direct current) content of the signal during modulation.

A modulation system comprises an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.

In some other embodiments, a modulation system comprises an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit after a predetermined delay. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.

In some other embodiments, a modulation system comprises an encoder for transferring data words to tentative code words. A partial DSV generator generates partial digital sum values (DSVs) according to the data words or tentative code words, a DSV accumulator for cumulating the partial DSVs as cumulative DSVs for possible values of a DSV control bit. A DSV control bit generator determines the value of a DSV control bit according to the cumulative DSVs, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.

DETAILED DESCRIPTION

FIG. 2is a block diagram showing an embodiment of a modulation system20in a high-density recording system. For example, in an HD-DVD recording system, 8-bit data words will be transformed into 12-bit code words through a modulation system20as shown inFIG. 2, and the 12-bit code words is for recording on an optical disc. During the modulation procedure, the 8bit data word B(t) associated with a current state S(t) read from a state register22is converted to a pre-connection word X(t) through a conversion table21, and in the meanwhile, a next state S(t+1) is also derived and stored in the state register22.FIG. 3expresses an example of a portion of the code conversation table21. Concatenation rules for code words should be applied to connect the pre-connection code words X(t) derived from the conversion table21. If adjoining pre-connection code words X(t) fit in some specific patterns, these pre-connection code words X(t) should be modified by a code connector23. The code connector23generates and outputs pre-DSV code words Y(t), and if a pre-connection code word X(t) includes a DSV control bit, it also outputs a DSV control bit indicator IDDSVto a DSV controller24. The DSV controller24determines the value of a current DSV control bit which minimizes the absolute cumulative DSV when it detects a subsequent DSV control bit from the code connector23or after a predetermined delay, and generate a post-DSV code word Z(t) according to the corresponding pre-DSV code word Y(t) and the determined current DSV control bit to achieve a minimized absolute cumulative DSV. The post-DSV code word Z(t) may be generated by modifying, inserting, or updating the corresponding pre-DSV code word Y(t) according to the determined current DSV control bit. Another way to generate the post-DSV code word Z(t) is to generate more than one possible code words corresponding to the corresponding pre-DSV code word Y(t). Z(t) is selected from one of the possible code words corresponding to the determined current DSV control bit. The conversion table21, state register22, and code connector23act as an encoder25. In some embodiments, the timing for the DSV controller24to determine the value of the current DSV control bit may not depend upon the detection of the subsequent DSV control bit. The DSV controller24may wait until a second, a third, or a fourth subsequent DSV control bit has arrived, and then determine the current DSV control bit which minimizes the absolute cumulative DSV. It is also possible that the DSV controller24may determines more than one DSV control bit at a time. In some other embodiments such as a Blu-ray system, the current DSV control bit may be determined before the arrival of the subsequent DSV control bit.

FIG. 4shows an embodiment of the DSV controller24, the DSV controller24includes a DSV control bit generator151, a DSV control bit detector152, a DSV location determiner153, a storage device154, and an insertion circuit155. The DSV control bit generator151calculates a cumulative DSV for each possible value corresponding to a current control bit, and determines the current DSV control bit BDSV that minimizes the cumulative DSV. The DSV control bit detector152detects whether any DSV control bit exists in the current code word according to the DSV control bit indicator IDDSV. When a DSV control bit is detected, the DSV control bit detector152notifies the DSV location determiner153. The storage device154stores each of the pre-DSV code words Y(t) generated by the code connector. In some embodiments, the storage device154comprises a series of pipe registers, delay registers, or shift registers, wherein each register stores one of the pre-DSV code word Y(t). In some other embodiments, the storage device154may be a first-in first-out (FIFO) memory, or a random access memory (RAM) with a write/read address generator. The number of registers is preferably greater than or equal to the maximum number of code words (or data words) between the occurrences of two consecutive DSV control bits. In an embodiment, the maximum number of code words between two consecutive DSV control bits may be the number of words in one frame, for example, 93 words, and it may be the number of words in two frames if considering that the DSV control bit in the frame sync field is used for ROPC (read optimum power calibration). The pre-DSV code words Y(t) are sequentially piped in the storage device154. The DSV location determiner153records the location of each code word having a DSV control bit. For example, the DSV location determiner153keeps tracking the storage location of the code word having a first DSV control bit until receiving the code word having a second DSV control bit. When the DSV location determiner153receives a DSV control bit indicator IDDSVindicating the arrival of the second DSV control bit, it sends an enabling signal (E1, E2, . . . ,En) to a register of the storage device154storing the code word having the first DSV control bit. If the code word having the first DSV control bit is currently stored in the mthregister of the storage device154, the DSV location determiner153outputs the enabling signal Emto instruct the storage device154to allow the insertion of the determined current DSV control bit from the insertion circuit155to the mthregister. By analogy, the second DSV control bit is determined and inserted into the corresponding register of the storage device154when the DSV location determiner153receives a DSV control bit indicator IDDSVindicating the arrival of the third DSV control bit, and so on. In this way, a DSV control bit is determined and inserted into the corresponding register of the storage device154when the DSV location determiner153receives a DSV control bit indicator IDDSVindicating the arrival of the subsequent DSV control bit. Instead of inserting a single DSV control bit into a code word, a code word might have two DSV control bits. In this case, it would be necessary to keep track of the individual bits within the code word to control the insertion of the two DSV control bits. In some other embodiments, the DSV control bits originally existed in the code words or data words are default values or arbitrary values, which will be modified in accordance to the determined DSV control bits generated by the DSV control bit generator. In some other embodiments, the digital words corresponding to the possible DSV control bits values are stored in the registers, then one of the digital words is selected in accordance to the determined DSV control bits generated by the DSV control bit generator. The digital words may be data words, final code words, or tentative code words, where the tentative code words are generated from the data words during modulation, and are used for generating the final code words.

FIG. 5is a block diagram showing an embodiment of the DSV control bit generator151inFIG. 4. Because a DSV control bit has two possible values, 0 and 1, the DSV control bit generator151determines the value which minimizes the absolute cumulative DSV. A partial DSV generator1511simultaneously generates two partial DSVs, PSD0and PSD1, according to a tentative code word Y(t). If the tentative code word Y(t) does not have any DSV control bit, the two partial DSVs, PSD0and PSD1, generated by the partial DSV generator1511are the same. If the tentative code word Y(t) has a DSV control bit as indicated by IDDSV, the two partial DSVs, PSD0(assuming the current DSV control bit BDSV=0)and PSD1(assuming the current DSV control bit BDSV=1), are generated by the partial DSV generator1511, respectively. The DSV0calculator1512adds the partial DSV PSD0to the cumulative DSV DSVA0, or substrates the partial DSV PSD0from the cumulative DSV DSVA0according to the polarity of the cumulative DSV DSVA0. When the subsequent tentative code word Y(t) output from the code connector23does not have any DSV control bit, the cumulative DSV DSVA0is selected from the value stored in the corresponding register1516. After calculation, the value calculated by the DSVO calculator1512is stored in the register1516to update the original stored value. In the same manner, the DSV1calculator1513adds the partial DSV PSD1to the cumulative DSV DSVA1, or substrates the partial DSV PSD1from the cumulative DSV DSVA1according to the polarity of the cumulative DSV DSVA1. When the subsequent tentative code word Y(t) output from the code connector23does not have any DSV control bit, the cumulative DSV DSVA1is selected from the value stored in the corresponding register1517. The value calculated by the DSV1calculator1513is then stored in the register1517. When a subsequent DSV control bit is detected as indicated by IDDSV, the DSV comparator1519compares the cumulative DSVs DSV0and DSV1and chooses the minimum absolute value among which as the updated cumulative DSVA. Besides, the DSV comparator1519also designates the bit value corresponding to a minimum absolute value as the value of the current DSV control bit BDSV. Meanwhile, the two multiplexes,1514and1515, select the updated cumulative DSVA as the cumulative DSVs of the two branches, that is, DSVA0and DSVA1for cumulative DSV calculations in the DSV0calculator1512and DSV1calculator1513. After cumulative DSV calculation, the values calculated by the DSV0calculator1512and DSV1calculator1513are stored to the corresponding registers1516and1517as the newly updated cumulative DSVs. In this way, a DSV control bit could be determined by comparing the two branches of cumulative DSV calculations when a subsequent DSV control bit is detected.

As shown in the example ofFIG. 6, the current DSV control bit is determined by comparing two possible values corresponding to the current DSV control bit, which are absolute cumulative DSVs DSV0and DSV1, when detecting a subsequent DSV control bit at time T1. In some other embodiments, time T1, the timing for comparing the cumulative DSVs, may be a constant predetermined interval. In the example ofFIG. 6, DSV0is smaller than DSV1at time T1, and hence the current DSV control bit is selected as 0.

Moreover, the current DSV control bit can be determined when two subsequent DSV control bits are detected, as shown in the example ofFIG. 7. The current DSV control bit is not determined when the first subsequent DSV control bit is detected at time T1. Each of the cumulative DSVs is split into two branches after time T1. When the second subsequent DSV control bit is detected at time T2, the DSV comparator1519determines the current DSV control bit by comparing the four possible values corresponding to both the current and first subsequent DSV control bits, which are the absolute cumulative DSVs, DSV00, DSV01, DSV10, and DSV11, or in some embodiments, both the current and subsequent DSV control bits can be determined accordingly. In this example, PSD01is the minimum out of the four absolute cumulative DSVs, and hence the current DSV control bit is designated as 0.

FIG. 8shows another embodiment of a modulation system70. In this embodiment, a DSV control bit generator72determines the DSV control bits according to tentative code words encoded by an encoder71. The tentative code words are sequentially stored in a code word FIFO74. A final code word generator75inserts the determined DSV control bits sequentially stored in a DSV bit FIFO73into corresponding code words read from the code word FIFO74. In some other embodiments, the final code word generator75modifies the original DSV control bit of the tentative code words with the DSV control bit stored in the DSV control bit FIFO73.

In comparison with the modulation system70, the modulation system80inFIG. 9further comprises a second encoder85, so that the buffer84may store data words instead of code words, consequently, reducing the memory size required by the data word FIFO84. The capacity for storing data words is less than the capacity for storing code words, for example, in an HD-DVD recording system, there are eight bits in a data word, but twelve bits in a code word. A DSV control bit generator82determines DSV control bits according to tentative code words encoded by a first encoder81, and outputs the determined DSV control bits to a DSV bit FIFO83. The second encoder85modulates the data words stored in the data word FIFO84into tentative code words. The determined DSV control bits output from the DSV control bit FIFO83are combined into corresponding tentative code words by a final code word generator86.

Since the input of the DSV control bit generator72in the modulation system70and the input of the DSV control bit generator82in the modulation system80are tentative code words Y(t), which is the same as that in modulation system20, one embodiment of the DSV control bit generator72and the DSV control bit generator82could be the same as the DSV control bit generator151in the modulation system20as shown inFIG. 5.

FIG. 10is a block diagram showing an embodiment of a modulation system50. Data words B(t) are provided to a DSV control bit generator51and a data word FIFO53. By utilizing the data word FIFO53to store data words B(t) instead of code words, the buffer size of the data word FIFO53is reduced. The data word FIFO53then provides the data words B(t) to an encoder54to transform the data words into code words with undetermined DSV control bits, or so called tentative code words. The DSV control bit generator51determines a current DSV control bit to minimize the absolute cumulative DSV when detecting at least one subsequent DSV control bit. The determined current DSV control bit is temporarily stored in a DSV control bit FIFO52, and then is read out from the DSV control bit FIFO52. A final code word generator55modifies the DSV control bit in the tentative code word according to the current DSV control bit stored in the DSV control bit FIFO52. By storing the DSV control bit in the DSV control bit FIFO52, the DSV control bit can be accessed and controlled more easily. In other embodiments, the DSV control bit generator51can also use a mapping table to determine the DSV control bit based on the data word. By using a mapping table, the cumulative DSV can be calculated by searching for corresponding values using the data words.

FIG. 11is a block diagram showing an embodiment251of the DSV control bit generator51inFIG. 10. Elements 2512-2519 in the DSV control bit generator shown inFIG. 11are the same as elements 1512-1519 inFIG. 5, thus the description of elements 2512-2519 are omitted. The detailed description of the partial DSV table2511will be explained as follows. Since the input of the DSV control bit generator51is a signal carrying data words B(t), a partial DSV table2511simultaneously maps two partial DSVs, PSD0and PSD1, and a DSV control bit indicator IDDSVaccording to the data word B(t). A portion of an exemplary partial DSV table2511is shown inFIG. 12. If the data word B(t) does not have any DSV control bit, the value of the DSV control bit indicator IDDSVis 0, and the two partial DSVs, PSD0and PSD1, generated by the partial DSV generator1511are the same. If the data word B(t) has a DSV control bit, the value of the DSV control bit indicator IDDSVis 1, and the two partial DSVs, PSD0(assuming the current DSV control bit BDSV=0)and PSD1(assuming the current DSV control bit BDSV=1), are generated by the partial DSV generator1511, respectively. Besides, the bit asterisk “*” and code connection rules are also taken into consideration for determination of DSV control bit. An offset value will be added to the partial DSVs when the bit asterisk “*” and code concatenation rules are encountered. The offset value is determined according to the previous, current, and subsequent data words.

FIG. 13is a block diagram showing another embodiment of a modulation system60. In comparison with the modulation system50, the modulation system60encodes the data words B(t) into code words through an encoder63, and instead of storing the data words, the system60stores the code words with undetermined DSV control bits in a code word FIFO64. Similarly, the data words are provided to a DSV control bit generator61for determining DSV control bits, and the determined DSV control bits are temporarily stored in a DSV control bit FIFO62waiting to be retrieved by a final code word generator65. Since the input of the DSV control bit generator61in the modulation system60is a stream of data words B(t), which is the same as that in the modulation system50ofFIG. 10, one embodiment of the DSV control bit generator61could be the same as the DSV control bit generator51in the modulation system50as shown inFIG. 11.

FIGS. 8(A),9(A),10(A), and11(A) are based onFIGS. 8,9,10, and11. In these embodiments70A,80A,50A,60A, a DSV control bit generator determines the DSV control bits according to data words or code words and sequentially outputs the determined DSV control bits to a DSV control bit FIFO. An encoder in the modulation system of these embodiments encodes each data word B(t) into one or more than one different tentative code words depending on whether any DSV control bit exists in the tentative code words. If no DSV control bit exists in the tentative code words, the tentative code words corresponding to a data word B(t) are the same. If a DSV control bit exists in the tentative code words, two different tentative code words corresponds to a data word B(t) are generated for each possible DSV control value. If two DSV control bit exists in the tentative code words, four different tentative code words corresponds to a data word B(t) are generated for each possible value of the two DSV control bits. Finally, the determined DSV control bits output from the DSV control bit FIFO select the corresponding tentative code words as the post-DSV code word Z(t)through a multiplexer79,89,59,69.

For a Blu-ray disc (BD) system, 17PP modulation is used to convert a data word to a code word from 2-bit to 3-bit. Please refer toFIGS. 14 and 15, which illustrate a 17PP modulator200for use with a Blu-ray disc recorder. A data word B(t) is simultaneously input to a DSV control bit generator220and a data word FIFO210. The data word FIFO210stores a plurality of data words212, where each data word212contains a 2-bit ID and10bits of data. The 2-bit ID indicates whether a DSV control bit is present in the corresponding10bits of data and the location of the DSV control bit. The DSV control bit generator220determines a current DSV control bit by calculating two cumulative DSV values222and224corresponding to a DSV control bit of 0 and 1. The absolute values of the two calculated DSV values222and224are compared with a comparator226to determine which control bit produces the smallest DSV value. In other words, the DSV control bit generator220minimizes the absolute cumulative DSV by parallel processing several 2-bit channel bits221when detecting at least one subsequent DSV control bit or after a predetermined delay. The buffer size of the data word FIFO210determines the predetermined delay used for detecting the DSV control bit since the number of data words that the data word FIFO210can store depends on the buffer size of the data word FIFO210.

In other embodiments, the DSV control bit generator220can also use a mapping table to determine the DSV control bit based on the data word.FIG. 16represents an example of the so-called mapping table that converts data words to partial DSVs. The length of data words inFIG. 16is not constant, so that the effect of a 2-bits data word may have already been calculated in the previous operation of transferring a data word to the DSV value according to the mapping table inFIG. 16. The effect of a 2-bits data word to the DSV should be ignored if it had been calculated in the previous operation, otherwise the effect should be added into the DSV calculation. The MASK signal is used to indicate whether a 2-bits data word is effective or not. By using a mapping table such as the tables previously mentioned, the cumulative DSV can be calculated by searching for corresponding values using the data words. Afterward, the original DSV control bit of a data word is modified by the DSV control bit determined by the DSV control bit generator220by a final data word generator230, which is shown as a multiplexer inFIG. 15. The data words combined with the determined DSV control bit are modulated into code words X(t) by an encoder240in parallel. The parallel modulation utilizes a plurality of modulators242, and means that several 2-bit channel bits of the data word B(t) are simultaneously converted into 3-bit modulated bits of the code words X(t).FIG. 17shows an example implementation of the encoder240for the conversion from data word to code word.

Please refer toFIGS. 18 and 19, which illustrate a 17PP modulator300for serial processing data. As shown inFIG. 18, a data word B(t) is simultaneously input into a DSV control bit generator320and a data word FIFO310. The data word FIFO310stores a plurality of sequential 2-bit channel bits312of the data word B(t). The DSV control bit generator320determines a current DSV control bit by calculating two cumulative DSV values322and324corresponding to a DSV control bit of 0 and 1. The absolute values of the two calculated DSV values322and324are compared with a comparator326to determine which control bit produces the smallest DSV value. In other words, the DSV control bit generator320minimizes the absolute cumulative DSV by serially processing sequential 2-bit channel bits321when detecting at least one subsequent DSV control bit. Afterward, a determined DSV control bit is inserted into a corresponding data word by a final data word generator330. The data words combined with the determined DSV control bit are temporally buffered in a post-DSV data word FIFO340. An encoder350serially reads the data words342from the post-DSV data word FIFO340for encoding them into code words X(t) channel-bit to channel-bit.

Please refer toFIG. 20andFIG. 21, which illustrate embodiments500,520of modulation systems. The embodiments500,520can make use of either serial or parallel implementations, such as the parallel implementation shown inFIG. 14and the serial implementation shown inFIG. 18.

In these embodiments, an insertion circuit502inserts each DSV control bit into the corresponding positions within the stream of the data words. Because each DSV control bit has two possible values, 0 and 1, two different streams of data words corresponding to each possible value of a DSV control bit are produced after the insertion circuit502. The two different streams of data words are provided to a data word FIFO504and a DSV control bit generator (determiner)506for determining each DSV control bit within the two different streams of data words. In the embodiment ofFIG. 20, the determined DSV control bit selects a corresponding data word stream for encoding. The DSV control bit selects the corresponding data word through a multiplexer508, and an encoder510encodes the result. In the embodiment ofFIG. 21, an encoder522modulates the two streams of data words stored in the data word FIFO504into two respective streams of code words. Then, the determined DSV control bit uses multiplexer524to select a corresponding stream of code words as the post-DSV code word Z(t).

Please refer toFIG. 22, which is a summarized structural diagram of a modulation system400according to the above disclosure. In the modulation system400, blocks402-406represent required blocks and blocks410-418represent optional ones. A digital word FIFO402may store either data words or tentative code words, and the input source may be data words or tentative code words. Similarly, the source of the DSV control bit generator404may be data words or tentative code words. Final word generator406may generate either final data words or final code words as output by either modifying, replacing, inserting, or selecting the final word according to DSV control bits determined by the DSV control bit generator404.

For the optional units, one or more encoders410,412,414,418may be placed in many possible positions, and it is also possible that multiple encoders are included in the system. A DSV control bit FIFO416can be included in some embodiments, whereas in some other embodiments, the DSV control bit may be directly transferred to the final word generator406without the FIFO, for example, by knowing where to insert/modify the DSV control bit by calculating its position.