Methods of forming a semiconductor circuit element and semiconductor circuit element

The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure generally relates to methods of forming a semiconductor circuit element and to a semiconductor circuit element, and, more particularly, to forming a semiconductor circuit element having two semiconductor devices, one of which comprises a ferroelectric high-k material and the other comprising a high-k material different from the ferroelectric high-k material.

2. Description of the Related Art

In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep sub-micron regime; the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than discreet circuits composed of independent circuit components. The majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area. Typically, present-day integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.

The basic function of a FET or a MOSFET is that of an electronic switching element, wherein a current through a channel region between two contact regions, referred to as source and drain, is controlled by a gate electrode, which is disposed over the channel region and to which a voltage relative to source and drain is applied. Particularly, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of a MOSFET is changed and the characteristic voltage level, usually called “threshold voltage” and in the following referred to as Vt, characterizes the switching behavior of a MOSFET. In general, Vt depends nontrivially on the transistor's properties, e.g., materials, dimensions, etc., such that the implementation of a desired Vt involves plural steps of adjustment and fine-tuning during the fabrication process.

Currently, the most common digital integrated circuits built today use CMOS logic, which is fast and offers a high circuit density and low power per gate. CMOS devices or “complementary symmetry metal oxide semiconductor” devices, as sometimes referred to, make use of complementary and symmetrical pairs of P-type and N-type MOSFETs for implementing logic functions. Two important characteristics of CMOS devices are the high noise immunity and low static power consumption of a CMOS device because the series combination of complementary MOSFETs in a CMOS device draws significant power only momentarily during switching between on- and off-states, since one transistor of a CMOS device is always in the off-state. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example, transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state. In current CMOS technologies, standard transistors and IO devices have the same high-k dielectric and metal electrode, whereas, in comparison with standard devices, the SiO2oxide of IO devices is thicker.

In efforts to improve memory arrays, ferroelectric gate field effect transistors (FeFETs) have been recently in the focus of research. In general, ferroelectric materials have dielectric crystals which show a spontaneous electric polarization similar to ferromagnetic materials showing a spontaneous magnetization. Upon applying an appropriate external electric field to a ferroelectric material, the direction of polarization can be reoriented. The basic idea is to use the direction of spontaneous polarization in ferroelectric memories for storing digital bits. In FeFETs, the effect that one makes use of is the possibility to adjust the polarization state of a ferroelectric material on the basis of appropriate electrical fields which are applied to the ferroelectric material which, in a FeFET, is usually the gate oxide. Since the polarization state of a ferroelectric material is preserved unless it is exposed to a high, with regard to the polarization state, counter-oriented electrical field or a high temperature, it is possible to “program” a capacitor formed of ferroelectric material such that an induced polarization state reflects an information unit. Therefore, an induced polarization state is preserved, even upon removing an accordingly “programmed” device from a power supply. In this way, FeFETs allow the implementation of non-volatile electrically-switchable data storage devices.

On the basis of ferroelectric materials, it is possible to provide non-volatile memory devices, particularly random-access memory devices similar in construction to DRAM devices, but differing in using a ferroelectric layer instead of a dielectric layer such that non-volatility is achieved. For example, the 1T-1C storage cell design in a FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor—a linear dielectric is used in a DRAM cell capacitor, whereas, in a FeRAM cell capacitor, the dielectric structure includes a ferroelectric material. Other types of FeRAMs are realized as 1T storage cells which consist of a single FeFET employing a ferroelectric dielectric instead of the gate dielectric of common MOSFETs. The current-voltage characteristic between source and drain of a FeFET depends in general on the electric polarization of the ferroelectric dielectric, i.e., the FeFET is in the on- or off-state, depending on the orientation of the electric polarization state of the ferroelectric dielectric. Writing of a FeFET is achieved in applying a writing voltage to the gate relative to source, while a 1T-FeRAM is read out by measuring the current upon applying a voltage to source and drain. It is noted that reading out of a 1T-FeRAM is non-destructive.

Though a FeFET or a ferroelectric capacitor represent in theory very promising concepts for complex semiconductor devices, it is a difficult task to identify appropriate ferroelectric materials which are compatible with existing advanced manufacturing processes of complex devices, particularly at very small scales. For example, commonly-known ferroelectric materials, such as PZT or perovskites, are not compatible with standard CMOS processes. According to present understanding, hafnium (Hf) materials which are used in current fabrication technologies exhibit a paraelectric behavior due to the predominantly monoclinic crystal structure present in HfO2. However, recent research results indicate that dielectric materials on the basis of hafnium oxide may represent promising candidates for materials with ferroelectric behavior to be used in the fabrication of ferroelectric semiconductor devices of ICs. For example, it was shown that the monoclinic structure may be suppressed in Zr, Si, Y and Al-doped hafnium oxide materials and stabilized crystal structures of ferroelectric nature were obtained in experiments with accordingly-doped samples.

In conventional HK/MG (high-k/metal gate) FEOL (front end of line) process flows, the thick high-k material of FeFET devices is formed in parallel to the high-k gate oxide of logic devices. Herein, a stack is formed in conventional integration approaches over high-k materials in the gate structure of FeFET devices, the stack comprising ferroelectric high-k material and the logic high-k material. Although this stack of ferroelectric high-k material and logic high-k material shows ferroelectric properties, the speed and function of the FeFET devices is negatively affected by parasitic capacitances appearing in the stack. This problem is present in FeFET integration, independent of whether a gate last or replacement gate technique or a gate first technique is employed.

Gate last or replacement gate techniques suffer the problem that the critical dimension of gate structures of FeFET devices is limited by the thick high-k layer of FeFET devices. The reason is that, with gate trenches being filled after gate patterning in replacement gate techniques, the additional ferroelectric layer structures to be formed in the gate trenches reduce the space in the gate trench which is left to the replacement gate materials. For example, in comparing gate structures of gate last and gate first techniques, the initial critical dimension of gate structures in gate last or replacement gate techniques has to be increased by at least 20 nm in comparison to gate first approaches in order to accommodate for the work function adjusting material layer(s) and the gate electrode material.

Furthermore, in gate last or replacement gate approaches close to the 28 nm technology node employing early nickel silicide, an activation anneal for ferroelectric high-k material is limited to temperatures at 450° C. or less. Alternative approaches using replacement gate schemes with late nickel silicidation considerably increase the complexity of conventional gate last or replacement gate process flows.

In view of the above-described situation, it is, therefore, desirable to integrate a full functional FeFET device into existing process flows in gate first and gate last approaches without increasing the complexity of existing process flows and addressing, at least partially, the aforementioned issues.

SUMMARY OF THE INVENTION

The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

In a first aspect of the present disclosure, a method of forming a semiconductor circuit element having a first semiconductor device and a second semiconductor device is provided. In some illustrative embodiments herein, the method includes providing the first semiconductor device in and on a first active region of a semiconductor substrate, the first semiconductor device including a first gate structure with a first gate dielectric layer, and providing the second semiconductor device in and on a second active region of the semiconductor substrate adjacent to the first active region, the second semiconductor device including a second gate structure with a second gate dielectric layer, wherein the first gate dielectric layer is formed by providing a buried ferroelectric material in the first active region, and wherein the second gate dielectric layer is formed by forming a high-k material over the second active region, the high-k material being different from the ferroelectric material.

In a second aspect of the present disclosure, a method of forming a semiconductor circuit element is provided. In some illustrative embodiments herein, the method includes forming a recess in a first active region of a semiconductor substrate, providing a ferroelectric material in the recess, forming a high-k material over a second active region of the semiconductor substrate adjacent to the first active region, the high-k material being different from the ferroelectric material, forming a gate electrode material over the first and second active regions, forming a first gate structure over the first active region by patterning the ferroelectric material and the gate electrode material, and forming a second gate structure over the second active region by patterning the high-k material and the gate electrode material.

In a third aspect of the present disclosure, a method of forming a semiconductor circuit element is provided. In some illustrative embodiments herein, the method includes forming a recess in a first active region of a semiconductor substrate, forming an amorphous film of material in the recess, the amorphous film of material exhibiting ferroelectric behavior in a crystalline phase, covering the amorphous film of material by a first cap layer, forming a high-k material over a second active region of the semiconductor substrate adjacent to the first active region after the cap layer is formed over the amorphous film of material, the high-k material being different from the amorphous film of material, crystallizing the amorphous film of material for forming a ferroelectric material buried in the first active region, forming a first gate dielectric layer over the first active region by patterning the ferroelectric material, and forming a second gate dielectric layer over the second active region by patterning the high-k material.

In a fourth aspect of the present disclosure, a semiconductor circuit element is provided. In some illustrative embodiments herein, the semiconductor circuit element includes a first semiconductor device formed over and in a first active region of a semiconductor substrate, the first semiconductor device including first source/drain regions in the first gate structure with a first gate dielectric layer, and a second semiconductor device formed over and in a second active region of the semiconductor substrate adjacent to the first active region, the second semiconductor device including second source/drain regions and a second gate structure with a second gate dielectric layer, wherein the first gate dielectric layer comprises a ferroelectric material and the second gate dielectric layer comprises a high-k material different from the ferroelectric material, and wherein an upper surface of the first active region below the first gate structure is lowered in the semiconductor substrate relative to an upper surface of the second active region.

DETAILED DESCRIPTION

The present disclosure relates to semiconductor circuit elements comprising semiconductor devices that are integrated on or in a chip, such as FETs, e.g., MOSFETs or MOS devices. When referring to MOS devices, the person skilled in the art will appreciate that, although the expression “MOS device” is used, no limitation to a metal-containing gate material and/or to an oxide-containing gate dielectric material is intended.

Semiconductor circuit elements of the present disclosure, and particularly semiconductor devices as illustrated by means of some illustrative embodiments, concern elements and devices may be fabricated by using advanced technologies. Semiconductor circuit elements of the present disclosure may be fabricated by technologies applied to approach technology nodes smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm, i.e., ground rules smaller or equal to 45 nm are imposed. After a complete reading of the present application, a person skilled in the art will appreciate that the present disclosure suggests semiconductor circuit elements that may have structures with minimal length and/or width dimensions smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm. For example, the present disclosure may provide for semiconductor devices fabricated by using 45 nm technologies or below, e.g., 28 nm or below.

After a complete reading of the present application, a person skilled in the art understands that semiconductor devices may be fabricated as MOS devices, such as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors, and both may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. A circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor circuit element being designed.

In some aspects of the present disclosure, a semiconductor circuit element having a first semiconductor device and a second semiconductor device may be formed. In accordance with some illustrative embodiments herein, the first semiconductor device may comprise a first gate structure disposed on a first active region which is provided in a semiconductor substrate, the first gate structure comprising a first gate dielectric layer provided by a ferroelectric material buried into the first active region. The second semiconductor device may comprise a second gate structure disposed on a second active region of the semiconductor substrate adjacent to the first active region, the second gate structure comprising a second gate dielectric layer formed by a high-k material different from the ferroelectric material. After a complete reading of the present application, a person skilled in the art will appreciate that, in approaches employing gate last techniques, the first and second gate structures may further comprise a dummy gate electrode structure which is, after the formation of the first and second gate dielectric layers, replaced by first and second gate electrode structures. The first and second gate electrode structures may comprise a layer of a work function-adjusting material and a gate electrode material, such as polysilicon, amorphous silicon or aluminum.

In some illustrative embodiments, the ferroelectric material may be provided by forming an amorphous film of material buried into the first active region, wherein the amorphous film of material is substantially different from the high-k material formed over the second active region, and wherein the amorphous film of material exhibits ferroelectric behavior in a crystalline phase. Subsequently to forming the buried amorphous film of material, a process for crystallizing the amorphous film of material is performed such that the buried ferroelectric material is obtained. In accordance with illustrative examples herein, the amorphous film of material is encapsulated by a cap layer prior to crystallizing the amorphous film of material. In accordance with some illustrative examples, the amorphous film of material may be crystallized upon forming the cap layer over the first active region, e.g., when the cap layer is deposited at a temperature greater than or equal to the crystallization temperature of the amorphous film of material. In accordance with some other illustrative examples, the amorphous film of material may be crystallized by performing an annealing process for crystallizing the amorphous film of material. Herein, the cap layer is formed prior to the crystallization, wherein the cap layer is formed at temperatures less than the crystallization temperature of the amorphous film of material.

In some illustrative embodiments, the cap layer may be formed on the amorphous film of material prior to forming the high-k material over the second active region. For example, the cap layer may be formed after appropriately masking the semiconductor substrate such that the second active region is covered by a mask or hardmask, while the first active region is at least partially exposed to further processing. After having formed the cap layer, the masking pattern may be removed such that the second active region is exposed to further processing.

In some illustrative embodiments, the high-k material may be formed on the cap layer when forming the high-k material over the second active region. For example, the high-k material may be blanket-deposited over the first and second active regions.

In some illustrative embodiments, the high-k material may be removed from above the cap layer in using the cap layer as an etch stop. For example, over the first active region, the high-k material may be selectively etched relative to the material of the cap layer to remove the high-k material from above the first active region.

In accordance with some illustrative embodiments of the present disclosure, the cap layer may comprise TiN. In some special examples herein, the cap layer may be formed by a layer of TiN.

In some illustrative embodiments of the present disclosure, particularly upon employing a gate last or replacement gate approach, a dummy gate electrode may be formed over the buried ferroelectric material after the high-k material is formed on the second active region. Herein, the dummy gate electrode may be subsequently replaced by a work function-adjusting material and a gate electrode material. In some illustrative embodiments herein, the buried ferroelectric material may be formed by forming a buried amorphous film of material in the first active region and by forming a cap layer on the buried amorphous film of material prior to forming the high-k material over the second active region, wherein the amorphous film of material exhibits ferroelectric behavior in a crystalline phase. Herein, the cap layer is provided before the dummy gate electrode is formed such that the cap layer may be used as an etch stop when replacing the dummy gate electrode over the first active region. Accordingly, a hybrid gate last or replacement gate approach may be employed, wherein the ferroelectric material is reliably encapsulated by the cap layer during formation and replacement of the dummy gate electrode.

In accordance with some illustrative embodiments of the present disclosure, the ferroelectric material in the first active region may be buried by forming a recess in the first active region and forming an amorphous film of material in the recess, the amorphous film of material exhibiting ferroelectric behavior in a crystalline phase. For example, the amorphous film of material may be deposited by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process at a deposition temperature smaller than the crystallization temperature of the amorphous film of material. Subsequently, a cap layer may be formed on the amorphous film of material in the recess for encapsulating the amorphous film of material. Accordingly, the amorphous film of material may be reliably encapsulated during subsequent processing. Alternatively, the amorphous film of material may be crystallized when depositing the cap layer. Otherwise, a subsequent crystallization process may be performed after the amorphous film of material is encapsulated by the cap layer. In accordance with some illustrative embodiments herein, the high-k material may be formed over the second active region after the cap layer is formed on the amorphous film of material and prior to the crystallization process. In accordance with some illustrative embodiments herein, the second gate dielectric layer may be formed prior to the formation of the first gate dielectric layer, wherein the first and second gate dielectric layers are formed by sequentially patterning the high-k material and the buried ferroelectric material.

In other aspects of the present disclosure, a semiconductor circuit element is formed. In accordance with some illustrative embodiments herein, a recess may be formed in a first active region of a semiconductor substrate and an amorphous film of material may be formed in the recess, wherein the amorphous film of material exhibits ferroelectric behavior in a crystalline phase. The amorphous film of material may be covered by a cap layer. Over a second active region of the semiconductor substrate adjacent to the first active region, a high-k material that is different from the amorphous film of material may be formed after the cap layer is formed over the amorphous film of material. Subsequently, the amorphous film of material may be crystallized for forming a ferroelectric material buried into the first active region. Then, a first gate dielectric layer may be formed over the first active region by patterning the ferroelectric material and a second gate dielectric layer may be formed over the second active region by patterning the high-k material.

In accordance with some illustrative embodiments, forming the first and second gate dielectric layers may be comprised of forming a first gate structure comprising the first gate dielectric layer over the first active region and forming a second gate structure comprising the second gate dielectric layer over the second active region. Herein, a gate electrode material may be formed over the ferroelectric material and the high-k material prior to the formation of the gate dielectric layers. For example, a first gate structure may be formed over the first active region by patterning the ferroelectric material and the gate electrode material over the first active region and a second gate structure may be formed over the second active region by patterning the high-k material and the gate electrode material over the second active region. Depending on whether a gate first or a gate last approach is chosen, the gate electrode material formed on at least one of the ferroelectric material and the high-k material may be either a dummy gate electrode material which is to be subsequently replaced by a work function adjusting material and a final gate electrode material, or may remain in the gate structure.

In some illustrative embodiments, the second gate structure may be formed before the formation of the first gate structure is completed.

In some illustrative embodiments, a further cap layer may be formed over the high-k material prior to the crystallization.

In further aspects of the present disclosure, a semiconductor circuit element may be provided. In accordance with some illustrative embodiments herein, the semiconductor circuit element may comprise a first semiconductor device formed over and in a first active region of a semiconductor substrate and a second semiconductor device formed over and in a second active region of the semiconductor substrate adjacent to the first active region. The first semiconductor device may comprise first source/drain regions and a first gate structure with a first gate dielectric layer, while the second semiconductor device may comprise second source/drain regions and a second gate structure with a second gate dielectric layer. Herein, the first gate dielectric layer may comprise a ferroelectric material and a second gate dielectric layer may comprise a high-k material different from the ferroelectric material. Furthermore, an upper surface of the first active region below the first gate structure may be lowered in the semiconductor substrate relative to an upper surface of the second active region.

In some illustrative embodiments, the first and second gate structures may extend along a normal direction of the upper surface of one of the first active region and the second active region up to a mutual height level. For example, the first and second gate structures may have an upper surface at an equal height level above the first active region or the second active region.

In some illustrative embodiments, a thickness of the first gate electrode layer may be greater than a thickness of the second gate dielectric layer.

In some illustrative embodiments of the various aspects of the present disclosure, the ferroelectric material may be a ferroelectric high-k material and the amorphous film of material may comprise an amorphous high-k material. In accordance with some illustrative examples, the ferroelectric material may comprise one of ZrO and a hafnium-based material. In some special illustrative example, the ferroelectric high-k material may be ZrO. In accordance with some other illustrative examples, the ferroelectric material may be one of pure HfO2and HfSiO2and HfZrO2and HfYO2.

In the following, semiconductor circuit elements and methods of forming semiconductor circuit elements in accordance with various exemplary embodiments of the present disclosure will be described with regard to the attached figures. The described process steps, procedures and materials are to be considered as only exemplary and to illustrate to one of ordinary skill in the art illustrative methods for practicing the subject matter disclosed herein. However, it is to be understood that the invention is not exclusively limited to the illustrated and described exemplary embodiments, as many possible modifications and changes may exist which will become clear to the person skilled in the art when studying the present detailed description together with the accompanying drawings and the above background and summary of the invention. Illustrated portions of semiconductor devices may include only a limited number of elements, although those skilled in the art will recognize that actual implementations of semiconductor devices may include a large number of such elements. Various steps in the manufacture of semiconductor devices are well known and so, in the interests of brevity, many conventional steps will only be mentioned briefly or will be omitted entirely without providing the well-known process details.

FIG. 1aschematically shows in a cross-sectional view a semiconductor circuit element100in accordance with some illustrative embodiments of the present disclosure. The semiconductor circuit element100is provided on a semiconductor substrate102. The semiconductor substrate may be, for example, a bulk substrate or represent an active layer of a silicon-on-insulator (SOI) substrate or silicon/germanium-on-insulator (SGOI) substrate. In general, the terms “substrate.” “semiconductor substrate” or “semiconducting substrate” should be understood to cover all semiconductor materials and all forms of such semiconductor materials and no limitation to a special kind of substrate is intended.

Within the semiconductor substrate102, two active regions112,122separated by an isolation structure, such as a shallow trench isolation (STI)104, are formed in the semiconductor substrate. Optionally, at least one of the active regions112,122may be doped. For example, the active regions112,122may be similarly doped or counter-doped or one of the active regions112,122may be one of P-type doped and N-type doped. After a complete reading of the present application, a person skilled in the art will appreciate, in accordance with some explicit examples herein, a doping of active regions with dopants may be achieved by performing an appropriate implantation process for implanting the dopants.

As illustrated inFIG. 1a, the active regions112,122may be separated by a single STI104. However, this does not pose any limitation to the present disclosure and the person skilled in the art will appreciate that, alternatively at least one or more active regions may be formed in between the active regions112and122.

After a complete reading of the present application, a person skilled in the art will appreciate that the active region112is comprised of a semiconductor device110, while the active region122is comprised of a semiconductor device120. In accordance with the illustration inFIG. 1a, a masking pattern may be formed over the semiconductor substrate such that the active region112is covered, while the active region122is at least partially exposed. In the illustrated example, the active region122is partially exposed. The masking pattern may be provided by a hard mask, as illustrated inFIG. 1a, e.g., by a nitride layer106and a lithographically patterned photoresist108.

FIG. 1bschematically illustrates the semiconductor circuit element100at a subsequent stage during fabrication, wherein processes P1and P2are performed. Particularly, the illustrated stage corresponds to a stage in the process flow at which the process P1is completed and before the process P2is performed. As a result of process P1, a recess132is formed in the nitride layer106and in the active region122in accordance with the patterned photoresist108(FIG. 1a). Subsequently, the patterned photoresist108may be removed in a cleaning process (not illustrated). After the process P1is performed and the photoresist108is removed in a subsequent cleaning process (not illustrated), the process P2is performed.

FIG. 1cschematically illustrates the semiconductor circuit element100at a stage during fabrication, when the process P2has been completed, prior to a process P3being performed. In process P2, an amorphous high-k material134was formed in the recess132, at least partially filling the recess132with the amorphous high-k material134. As is illustrated inFIG. 1c, the amorphous high-k material is deposited on the nitride layer106outside the recess132and on inner sidewalls of the recess132and on the bottom of the recess132such that any portion of the active region122being exposed in the recess132is covered by the amorphous high-k material134.

Subsequent to the formation of the high-k material134, an insulating material136different from the nitride material106is formed over the semiconductor circuit element100and particularly over the semiconductor device110and the semiconductor device120. In accordance with some illustrative embodiments herein, the insulating material layer136is formed directly on the amorphous high-k material134, as illustrated inFIG. 1c. For example, the insulating material of the insulating material layer136may be an oxide material, such as silicon oxide deposited by TEOS deposition or silane pyrolysis.

Subsequent to the formation of the amorphous high-k material134and the insulating material layer136, a process P3is performed for substantially exposing the active region112and the active region122with a buried amorphous high-k material124(FIG. 1d) which is a portion of the high-k material134. The high-k material134is buried into the active region122as illustrated inFIG. 1d.

In some illustrative examples, the process P3may be a CMP (chemical mechanical polishing) process using the nitride layer106for end-point detection. Optionally, an additional strip process may be performed for removing the nitride layer106. Although the layer106is described above as a nitride layer, the person skilled in the art will appreciate that this does not pose any limitation on the present disclosure. In accordance with other illustrative embodiments of the present disclosure, the layer106may be provided by an oxide material, e.g., silicon oxide, whereas the material of the insulating material layer136may be a nitride material, e.g., silicon nitride.

FIG. 1dschematically shows the semiconductor circuit element100after the process P3is completed. The active region112of the semiconductor device110is exposed to further processing. In the semiconductor device120, the buried amorphous high-k material124and part of the material of the active region122is exposed. Due to the CMP process P3, the upper surfaces of the active region112, and active region122and the buried amorphous high-k material124are level.

Subsequently, a cap layer138is formed over the active region122and the buried amorphous high-k material124, as shown inFIG. 1e. Particularly, the buried amorphous high-k material124may be encapsulated by the cap layer138such that the buried amorphous high-k material124is buried into the active region122and encapsulated by the cap layer138in the active region122.

In some illustrative examples herein, the cap layer138may comprise TiN. For example, the cap layer138may be formed by depositing TiN material over the semiconductor circuit element100, masking the semiconductor circuit element100such that the semiconductor device110is exposed, while the semiconductor device120is covered by a mask (not illustrated). In a subsequent RIE (reactive ion etch) or a wet etch, the cap material is removed from above the active region112such that the cap layer138remains over the active region122. Alternatively, the active region112may be covered by a photolithographically patterned mask such that the active region122is exposed to a deposition process for forming the cap layer138over the active region122.

After a complete reading of the present application, a person skilled in the art will appreciate that, in accordance with some illustrative embodiments of the present disclosure, an annealing process (not illustrated) may be performed for crystallizing the buried amorphous high-k material124such that, at least partially, the buried amorphous high-k material124may crystallize in a stable ferroelectric crystal configuration, e.g., in the orthorhombic phase. In accordance with some alternative embodiments of the present disclosure, the crystallization of the buried amorphous high-k material124may take place upon forming the cap layer138on the amorphous high-k material124as described above. After a complete reading of the present application, a person skilled in the art will appreciate that at the stage during fabrication illustrated inFIG. 1e, the buried high-k material124may be either amorphous or in the ferroelectric phase. As the buried high-k material124may be either ferroelectric or amorphous, it will be referred to in the following as “the buried high-k material124.” The buried high-k material124is to be understood as being either ferroelectric or amorphous, unless explicitly stated.

With regard toFIGS. 2a-2d, a process sequence for forming a high-k material different from the buried high-k material124over the active region112is schematically illustrated.FIG. 2aschematically shows the semiconductor circuit element100at a stage during fabrication, in which a process P4is completed, prior to the application of a process P5. In the process P4, a high-k material142is formed above the active region112and a cap layer144is formed on the high-k material layer142over the active region112. The high-k material142may be different from the high-k material124. For example, in case that the high-k material124is ferroelectric at the illustrated stage during fabrication, the high-k material142may differ from the high-k material134at least in that the high-k material142is in a stable paraelectric configuration or in that the thickness of the high-k material142is smaller than the thickness of the buried high-k material124. In some illustrative, but not limiting, examples herein, the thickness of the high-k material142may be within a range from about 40 Angstrom (or 4 nm) to about 150 Angstrom (or 15 nm) thick, such as, for example, about 80 Angstrom (or 8 nm). Additionally or alternatively, the thickness of the buried high-k material124may be within a range from about 20 Angstrom (or 2 nm) to about 40 Angstrom (or 4 nm), such as, for example, about 20 Angstrom (or 2 nm). In case the high-k material124is amorphous at the illustrated stage during fabrication, the high-k material142may differ from the buried high-k material124in that the high-k material142is at least crystalline, preferably in a stable nonferroelectric configuration. In some examples herein, the high-k material142and the buried high-k material124may be substantially different chemical materials. In some illustrative embodiments, as it is shown inFIG. 2a, the high-k material142and the cap layer144may be deposited on the active region112and over the active region122, particularly, on the cap layer138.

Subsequent to the process P4, the process P5is performed for forming a masking pattern over the active regions112,122.FIG. 2bschematically illustrates the semiconductor circuit element100after the process P5is completed. The masking pattern146may comprise, for example, a photolithographically patterned photoresist146. The patterned photoresist146covers the cap layer144over the active region112, while the cap layer144over the active region122remains exposed to further processing. Subsequently, a process P6may be applied to the semiconductor circuit element100, to which the semiconductor device120and particularly the cap layer144is exposed. In some illustrative embodiments of the present disclosure, the process P6may comprise an RIE process for removing the cap layer144and the high-k material142from above the active region122. Herein, the cap layer138may be used as an etch stop for the process P6. After a strip of the photolithographically patterned photoresist146, a process P7may be performed as illustrated inFIG. 2c.

In accordance with some illustrative embodiments, the process P7may comprise front end of line annealing steps for activating the ferroelectric nature of the ferroelectric high-k material, healing crystal damages due to possible implantation process (not illustrated) and/or activating dopants implanted during possible implantation sequences (not illustrated).

Furthermore, the process P7may comprise a sub-process for equalizing the thickness of the layers142′ and138to form a layer144′ of substantially equal thickness over the semiconductor devices110and120. In some illustrative embodiments herein, a wet TiN removal combined with a re-deposition of TiN may be performed. Therefore, as shown inFIG. 2d, a semiconductor circuit element100may be obtained, wherein the semiconductor devices110and120comprise a buried ferroelectric high-k material124in the active region122and a high-k material142′ disposed on or above the active region112. Accordingly, a stack configuration for high-k materials in the semiconductor device120as is usually present in conventional semiconductor devices with ferroelectric high-k material, is not necessary.

Subsequently, a sequence of processes P8, P9and P10is performed as illustrated inFIG. 2d.

FIG. 3aschematically illustrates the semiconductor circuit element100at a stage during fabrication, after the sequence of processes P8, P9and P10is completed and prior to the application of a process P11. At the illustrated stage during fabrication, the buried high-k material124represents a ferroelectric high-k material as described above.

In some illustrative embodiments, the process P8may be performed for depositing a gate electrode material layer152over the semiconductor devices110and120. In some explicit example, amorphous silicon or polysilicon may be deposited during the process P8.

In process P9, a cap layer154is formed on the gate electrode material layer152over the semiconductor devices110and120. For example, a nitride material, such as silicon nitride, may be deposited.

In the process P10, a photoresist material is formed on the cap layer154and subsequently photolithographically patterned to form the patterned photoresist structure156. The patterned photoresist structure156is patterned in accordance with gate structures to be formed over the active regions112and122of the semiconductor devices110and120.

Subsequently, a process P11is performed for patterning the cap layer154, the gate electrode material layer152and the high-k material142′ over the active region112and to pattern the cap layer154, the gate electrode material layer152and the cap layer144′ over the active region122.

FIG. 3bschematically illustrates the semiconductor circuit element at a stage during fabrication, particularly after the process P11is completed and the patterned photoresist structure156is removed. Herein, a gate structure111is formed on the active region112for the semiconductor device110. The gate structure111comprises a gate cap119, a gate electrode layer118, a TiN layer116and a gate dielectric layer114comprising the high-k material.

After completing the process P11, the semiconductor device120substantially has a pre-gate structure121′ comprising a gate cap129, a gate electrode layer128, a TiN layer126and a partially patterned ferroelectric high-k material124. Optionally, a thin nitride liner may be deposited over the gate structures110and120to protect the high-k materials. After forming a masking pattern covering the semiconductor device110and at least leaving the gate structure121′ and the exposed buried ferroelectric high-k material124exposed for further processing, e.g., masking structure158shown inFIG. 3c, an etching process is performed to remove the ferroelectric high-k material on the active region122in alignment with the gate structure121′, i.e., all ferroelectric high-k material unless that covered by the gate structure121′, such that the gate structure121′ is formed. In some illustrative embodiments, suitable dry etch processes may be performed on RIE tools with elevated process temperatures to etch the ferroelectric high-k material.

FIG. 4schematically illustrates a semiconductor circuit element200comprising semiconductor devices210and220, the semiconductor circuit element200being obtained from the semiconductor circuit element100after the masking pattern158is removed and source/drain regions166together with silicide regions and contact structures168contacting the source/drain regions166are formed. Furthermore, gate contact regions162,164are formed on respective gate structures221and211. The contact structure168may be formed in an ILD layer172as known in the art. In this way, an illustrative semiconductor circuit element200with semiconductor devices210and220may be formed in accordance with gate first techniques of some illustrative embodiments of the present disclosure.

FIG. 5schematically shows in a cross-sectional view a semiconductor circuit element300in accordance with gate last techniques of some illustrative embodiments of the present disclosure, in which subsequently to the processing illustrated inFIG. 3c, the gate electrode layers118and128are removed and, thus, a hybrid replacement gate approach is implemented. In an illustrative hybrid replacement gate approach, the gate electrode layers118,128as illustrated inFIG. 3crepresent dummy gate electrodes and are subsequently replaced by a work function-adjusting metal318and a gate electrode material319for the semiconductor device310, while a work function-adjusting material layer328is formed in the gate structure221of the semiconductor device320together with gate electrode material329. Herein, the gate electrode materials319,329may comprise aluminum.

After a complete reading of the present application, a person skilled in the art will appreciate that the ferroelectric high-k material124is reliably protected by the cap layer126during the replacement of the gate electrode material layer128by the work function adjusting material328and the gate electrode material329. Furthermore, a hybrid replacement gate approach is proposed in which parallel gate structures of the parallel semiconductor devices310,320have different high-k materials114and124. Particularly, the high-k material114may have a thickness which is smaller than a thickness of the buried ferroelectric high-k material124. In some illustrative embodiments of the present disclosure, the thickness of the high-k material114may be in a range of about 1-4 nm and the thickness of the buried ferroelectric high-k material124may be in a range from about 4-15 nm. In some explicit examples herein, the ferroelectric high-k material124and the high-k material114may be different in that both only differ by the respective thickness values. In spite of the ferroelectric high-k material124being thicker than the high-k material114, the gate structure211and the gate structure221extend along a normal direction of an upper surface of one of the active regions112and122up to a mutual height level as indicated inFIG. 5by the height level H1relative to an upper surface of the active region112and a height level H2relative to an upper surface of the active region122.

Furthermore, due to the initially buried high-k material124, the gate structure221of the semiconductor device320is positioned lower in the semiconductor substrate102relative to an upper surface of the active region112as indicated by the height difference h inFIG. 5. A similar height difference is implemented in the semiconductor circuit element200as illustrated inFIG. 4, although the height difference is not explicitly depicted.

After a complete reading of the present application, a person skilled in the art will appreciate that in the methods according to the various illustrative embodiments of the present disclosure, gate structures in semiconductor devices of logic and ferroelectric areas of a semiconductor circuit element have a substantially equal height level and, therefore, result in a semiconductor circuit element which is compatible with gate first and replacement gate approaches. For example, the semiconductor devices120,220,320may represent a FeFET device, while the semiconductor devices110,210,310may represent a logic device.

It is noted that the ferroelectric high-k material layer of one semiconductor device is decoupled from the high-k material of another semiconductor device such that the gate dielectric layers of ferroelectric FETs and logic devices are decoupled.

After a complete reading of the present application, a person skilled in the art will appreciate that no thermal budget limitations arise in comparison to conventional process flows as the ferroelectric high-k material is formed at an early stage in the process flow. Particularly, nickel silicide degradation due to possibly high activation annealing temperatures for ferroelectric high-k material is avoided without implementing a complex process flow. Particularly, the process flow of replacement gate approaches is not affected by the early inclusion of the ferroelectric high-k material because the ferroelectric high-k material is patterned before dummy gate structures are replaced.

In the present disclosure it is generally proposed to form a ferroelectric high-k material layer very early in the front end of line process flow by burying a ferroelectric high-k material into the substrate prior to the formation of gate structures and gate oxides. A cap layer is further patterned to protect the ferroelectric high-k layer from any etch attack, such as RIE and HF etch processes in front end of line process flows prior to the gate formation. As a further advantage, the cap layer may later be used as an etch stop, allowing for a selective removal of high-k layers of other semiconductor devices, such as logic devices, without damaging the ferroelectric high-k material of ferroelectric semiconductor devices.