Transistor, a transistor arrangement and method thereof

A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

PRIORITY STATEMENT

This application claims the benefit of Korean Patent Application No. 2006-48947, filed on May 30, 2006, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Example embodiments of the present invention relate generally to a transistor, transistor arrangement and method thereof.

2. Description of the Related Art

Semiconductor devices may include one or more transistors each having one of a plurality of sizes, and which may be driven by one of a plurality of voltages. Higher-voltage transistors may generally be driven by higher voltages and may include thicker gate insulation layers. Source/drain regions of the higher-voltage transistors may employ a lightly doped drain (LDD) structure having a lower-concentration impurity-doped region and a higher-concentration impurity-doped region in order to reduce punchthrough and increase breakdown voltage characteristics.

However, in order to implement higher-voltage transistors within products such as semiconductor devices, the higher-voltage transistor may be configured to have a given size so as to conform to a desired physical layout. Typical transistor design characteristics may include a gate length and a gate width, respectively, of a transistor gate. A higher-voltage transistor may have typically have a constant gate length, and the higher-voltage transistor may generally be adjusted via changes to the gate width only.

Conventional higher-voltage transistors may be configured to maintain a relatively constant resistance per a unit length of a gate width. Thus, while different conventional higher-voltage transistors may include different gate widths, the different higher-voltage transistors may be desired to have identical and/or substantially similar characteristics. However, conventional higher-voltage transistors may have different respective resistances per a unit length of a gate width if sizes (e.g., gate widths) of the respective transistors are changed (e.g., to accommodate a desired physical layout).

SUMMARY OF THE INVENTION

An example embodiment of the present invention is directed to a method of configuring a transistor, including determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted.

Another example embodiment of the present invention is directed to a transistor, including a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

Another example embodiment of the present invention is directed to a method of designing a higher-voltage transistor whose resistance per a unit length of a gate width is substantially constant irrespective to a change of a gate width of the higher-voltage transistor.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Detailed illustrative example embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Example embodiments of the present invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

Accordingly, while example embodiments of the invention are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the invention to the particular forms disclosed, but conversely, example embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like numbers may refer to like elements throughout the description of the Figures.

FIG. 1is a plan view illustrating a higher-voltage transistor according to an example embodiment of the present invention.FIG. 2is a sectional view taken by cuttingFIG. 1along I-I′ line.

In the example embodiment ofFIGS. 1 and 2, a first higher-voltage transistor100may include a semiconductor substrate1. A device isolation layer3may be disposed on the semiconductor substrate1to define an active region. The semiconductor substrate1may be doped with P-type impurities, for example. Although not shown inFIGS. 1and/or2, a well may be disposed in the semiconductor substrate1. A gate insulation layer5may be disposed on the semiconductor substrate1. A first gate line (e.g., or a “gate electrode”)7may be disposed on the gate insulation layer5. In an example, the gate insulation layer5may be include a thermal oxide and may have a thickness sufficient to endure a higher voltage. The first gate line7may include a conductive material, such as a metal-containing layer or a polysilicon doped by impurities. Although not shown inFIGS. 1and/or2, a capping layer may be disposed on the first gate line7. A first lower-concentration impurity-doped region9may be disposed in the semiconductor substrate1at first and second sides of the first gate line7, A first higher-concentration impurity-doped region11may be disposed in the first lower-concentration impurity-doped region9. The first higher-concentration impurity-doped region may be spaced apart from the first gate line7by a first distance L1and from the device isolation3by a second distance L2. The first distance L1and the second distance L2may be greater than a given threshold distance (e.g., greater than zero) so as to reduce or prevent an occurrence of a punchthrough or leakage current and/or for improving a breakdown voltage characteristic. In an example, the given threshold distance may be in the range 0.1˜10 μm. The gate line7of the first higher-voltage transistor100may include a first gate width L3. In an example, the first higher-voltage transistor100may be operated with an operation voltage between 3.3V˜50V.

In the example embodiment ofFIGS. 1 and 2, the second distance L2may be determined based on the first gate width L3. For example, based on the first gate width L3, it may be possible to determine 2×L2, which may be a sum of lengths of the first lower-concentration impurity-doped region9overlapping with a straight line D1that is parallel to the gate line7and crossing over the first lower-concentration impurity-doped region9, and the first higher-concentration impurity-doped region11. For example, if the first gate width L3is tripled, the second distance L2may likewise be tripled. Alternatively, if the first gate width L3is reduced by half, the second L2may be reduced by half, and so on.

FIG. 3is a plan view illustrating a higher-voltage transistor according to another example embodiment of the present invention.

In the example embodiment ofFIG. 3, a second higher-voltage transistor200may include a device isolation layer3, a second gate line7a, a second lower-concentration impurity-doped region9aand a second higher-concentration impurity-doped region11a. The second gate line7amay have a second gate width L5. The second higher-concentration impurity-doped region11amay be spaced apart from the second gate line7aby a first distance L1and from the device isolation layer3by a third distance L4.

In the example embodiments ofFIGS. 1,2and3, in an example, the second gate width L5may correspond to half of the first gate width L3, and the third distance L4may correspond to half of the second distance L2. In another example, the types and dose amounts of impurities doped in the first higher-concentration impurity-doped region11may be substantially similar (e.g., identical) to those doped in the second higher-concentration impurity-doped region11a. In another example, the types and dose amounts of impurities doped in the first lower-concentration impurity-doped region9may be substantially similar (e.g., identical) to those doped in the second lower-concentration impurity-doped region9a.

In the example embodiment ofFIGS. 1 and 2, in the first higher-voltage transistor100, a resistance per a unit length of the first lower-concentration impurity-doped region9adjacent to the first gate line7may be calculated as follows:

In the example embodiment ofFIG. 3, in the second higher-voltage transistor200, a resistance per a unit length of the second lower-concentration impurity-doped region9aadjacent to the second gate line7amay be calculated as follows:

In Equations 1 and 2, R1may correspond to resistances of the lower-concentration impurity-doped regions9and9alocated between the gate lines7and7aand the higher-concentration impurity-doped regions11and11a, and R2may correspond to resistances of the lower-concentration impurity-doped regions9and9alocated at edges of the higher-concentration impurity-doped regions11and11a.

In an example, referring to equation 2, if L5is equal to half of L3and L4is equal to half of L2, Equation 2 may be reduced to Equation 1. Therefore, during an operation of the transistors100and200ofFIGS. 1,2and3, respectively, a resistance per a unit length of the first gate width L3, which may be applied to the first lower-concentration impurity-doped region9adjacent to the first gate line7of the first higher voltage transistor100, may be equal to a resistance per a unit length of the second gate width L5, which may be applied to the second lower-concentration impurity-doped region9aadjacent to the second gate line7aof the second higher voltage transistor200.

In the example embodiment ofFIG. 3, the second high-voltage transistor200may be a unit higher-voltage transistor or a sub higher-voltage transistor. The higher-voltage transistor200may be modified by arranging a plurality of the unit and/or sub higher-voltage transistor to a given active region jointly in a vertical or/and horizontal direction, as will now be explained in greater detail with respect to the example embodiment ofFIG. 4.

FIG. 4is a plan view illustrating a higher-voltage transistor according to another example embodiment of the present invention.FIG. 5is a plan view illustrating a higher-voltage transistor according to another example embodiment of the present invention.

In the example embodiment ofFIG. 4, a third higher-voltage transistor300may be formed by arranging two of the second higher-voltage transistors200to a given active region jointly in a vertical direction. For example, the third higher-voltage transistor300may be symmetrical to a straight line D4crossing a center of gate lines7aand7b. Lower-concentration impurity-doped regions9aand9band higher-concentration impurity-doped regions11aand11bmay be arranged at first and second sides of the gate lines7aand7b. The higher-concentration impurity-doped regions11aand11bmay be spaced apart from the gate lines7aand7bas a first distance L1and from the device isolation layer3as a third distance L4. At a given side of the gate lines7aand7b, the higher-concentration impurity-doped regions11aand11bmay be spaced apart from each other by a fourth distance L6. In an example, the fourth distance L6may be substantially equal to a double of the third distance L4. In another example, a whole gate width of the gate lines7aand7bmay be substantially equal to the first gate width L3of the first higher-voltage transistor100ofFIG. 1. In an ex ample, a sum of lengths of the lower-concentration impurity-doped regions9aand9boverlapping with a straight line D3, which may be parallel to the gate lines7aand7band crossing over the higher-concentration impurity-doped regions11aand11band the lower-concentration impurity-doped regions9aand9b, may be expressed as 2L4+L6, and the sum may be equal to 2×L2(e.g., seeFIG. 1).

In the example embodiment ofFIG. 4, because the third higher-voltage transistors300may be formed by arranging two of the second high-voltage transistors200and a resistance per a unit length of a gate width of the second high-voltage transistor200may be substantially equal to that of the first higher-voltage transistor100(e.g., see Equations 1 and 2), a resistance per a unit length of a gate width of the third higher-voltage transistor300may be configured to be substantially equal to that of the first higher-voltage transistor100.

In the example embodiment ofFIG. 5, a fourth higher-voltage transistor400may be formed by arranging two of the second higher-voltage transistor200within a given active region jointly in a horizontal direction. For example, the fourth higher-voltage transistor400may be symmetrical to a straight line D5located between two gate lines7aand7b. The gate lines7aand7bmay be electrically connected to each other. Like the third higher-voltage transistor300, the fourth higher-voltage transistor400may be configured to have substantially the same resistance per a unit length of a gate width as the first higher-voltage transistor100. Thus, the first, second, third and fourth higher-voltage transistors100,200,300and400may have substantially the same resistance per a unit length of a gate width irrespective of their different forms and/or sizes. Therefore, in another example the first, second, third and fourth higher-voltage transistors100,200,300and400may be configured to have a relatively equivalent performance.

In another example embodiment of the present invention, higher-voltage transistors may be configured to have a given resistance per a unit length of a gate width based on controlling or adjusting a distance between a higher-concentration impurity-doped region and a device isolation layer. In an example, the adjusted distance may be based on a gate width. For example, adjusting (e.g., increasing or decreasing) the sum of lengths of lower-concentration impurity-doped regions overlapping with a straight line, which may be parallel to the gate line and crossing over the lower-concentration impurity-doped region and the higher-concentration impurity-doped region, may be performed based on a ratio of increasing or decreasing a gate width. Higher-voltage transistors may thereby be produced to have desired properties irrespective of physical design characteristics, such as a size or form of the higher-voltage transistor, thereby allowing design engineers greater flexibility with regard to transistor implementation. Accordingly, an efficiency of a semiconductor design process may be increased.

Example embodiments of the present invention being thus described, it will be obvious that the same may be varied in many ways. For example, while example embodiments of the present invention are above-described as directed to higher-voltage transistors, it is understood that “higher-voltage” is a relative term, and may vary from application to application. Accordingly, the above-described example embodiments of the present invention may generally be directed to transistors having any voltage characteristics, and are not intended to be limited to what a “higher-voltage” transistor may qualify as within any particular application.

Such variations are not to be regarded as a departure from the spirit and scope of example embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.