Doric pillar supported maskless airgap structure for capacitance benefit with unlanded via solution

Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2015/037835, filed Jun. 25, 2015, entitled “DORIC PILLAR SUPPORTED MASKLESS AIRGAP STRUCTURE FOR CAPACITANCE BENEFIT WITH UNLANDED VIA SOLUTION,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

FIELD OF THE INVENTION

Embodiments of the present invention relate generally to the manufacture of semiconductor devices. In particular, embodiments of the present invention relate to interconnect structures for semiconductor devices and methods for manufacturing such devices.

BACKGROUND OF THE INVENTION

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. The interconnects and vias are typically separated from each other by an interlayer dielectric material. As the pitch between interconnect lines and the spacing between layers continues to be scaled down, capacitive coupling between lines and vias increase. Accordingly, typical back-end interconnect stacks utilize low-k dielectric materials to reduce the capacitance. In some back-end interconnect stacks, air-gaps may be used to replace portions of the low k-dielectric materials in order to further decrease the capacitance.

Air-gaps are typically formed with an “air-gap etch” that removes portions of the interlayer dielectric material. After the interlayer dielectric material is removed, a non-conformal material is deposited over the openings formed by the air-gap etch in order to form an intentional “key-hole void”. However, the formation of air-gaps with an air-gap etching process has several disadvantages. For example, unlanded or partially landed vias produce the risk of a short-circuit. During the via formation, an unlanded or partially landed via may punch through the non-conformal fill material and provide an opening into the air-gap. When the via metal is deposited the metal will also fill the air-gap and may result in a short. Accordingly, the risk of shorting the device needs to be mitigated by using additional masks that block the formation of air-gaps near vias. Additionally, the air-gap etching process that is presently used is a dry etching process. Accordingly, the interlayer dielectric material is only able to be removed from between interconnect lines due to the anisotropic nature of dry-etching processes. As such, the dielectric material below the interconnect lines remains behind and there is not a beneficial reduction in the layer-to-layer capacitance.

Thus, improvements are needed in the area of via manufacturing technologies.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention include interconnect layers with floating interconnect lines. As used herein, floating interconnect lines are conductive lines formed in an interconnect layer that include a bottom surface that is at least partially unsupported. The unsupported bottom surface is boarded by an air-gap that allows for increased reduction in capacitive coupling between interconnect layers. Embodiments of the invention provide support to the floating interconnect lines by forming pillars and vias below portions of the bottom surface of the interconnect lines. Additionally, embodiments of the invention include forming air-gaps between neighboring interconnect lines within an interconnect layer, and forming air-gaps between vias. Accordingly, embodiments of the invention allow for greater reductions in line-to-line capacitive coupling and layer-to-layer capacitive coupling than is possible with prior “air-gap etching” processes, such as those described above. Furthermore, embodiments of the invention provide self-aligned etchstop layers over the floating interconnect lines that prevents unlanded, or partially landed vias from breaking through to the air-gaps. As such, additional masking operations are not needed to prevent the formation of air-gaps proximate to locations where a via is desired.

Referring now toFIGS. 1A-1M, a series of plan views and corresponding cross-sectional views are used to illustrate various processing operations that may be used to form floating interconnect lines with air-gaps between vias and below the interconnect lines, according to embodiments of the invention.

Referring now toFIG. 1A, a plan view illustration of an interconnect layer100with a plurality of openings120formed into with sacrificial material layer160is shown. According to an embodiment, the sacrificial material layer160is a material that may be selectively removed with a chemical process through a permeable layer. In one embodiment, the sacrificial material160may be removed with a wet etching chemistry or is otherwise soluble in a particular solvent. Additional embodiments may include a sacrificial material that is removable through a permeable layer with a vapor phase process, with a plasma process, or the like. Removal of the sacrificial material layer160through a permeable layer allows for the sacrificial material layer160to be removed through a permeable etchstop layer formed in a subsequent processing operation. Prior to the removal of the sacrificial material layer160, the sacrificial material layer160provides structure (e.g., scaffolding) for the interconnect lines, vias, and pillars to be formed over. Embodiments include a sacrificial material layer160that may also be a material that can be patterned with a dry-etching process. In an embodiment, the sacrificial material may be any material that can be selectively removed through a permeable layer while at the same time the removal process does not damage the pillars, vias, and interconnect lines. Embodiments of the invention include a sacrificial material layer160that is a metal oxide, a metal nitride, a ceramic, an amorphous silicon, an amorphous carbon, or the like. By way of example, the sacrificial material layer160may be a dielectric material such as such as titanium nitride.

According to an embodiment, the openings120are formed through the entire thickness of the sacrificial material layer160to expose an underlying substrate110, as illustrated inFIG. 1A. According to an embodiment, the openings120may be formed at every potential location where a via or a pillar may be formed. Embodiments of the invention may form the openings120with any patterning process that provides a suitable pitch and critical dimension needed for the formation of vias in the interconnect structure. By way of example, the openings120may be patterned with one or more photolithography patterning process, with directed self-assembly (DSA) processes, or the like.

In an embodiment, the interconnect layer100may be one layer in a back end of line (BEOL) stack that includes a plurality of interconnect layers. As such, the interconnect layer100may be formed over another interconnect layer. For example, the underlying substrate110may be an etchstop layer formed over an additional interconnect layer. Additional embodiments may include forming the interconnect layer100as the first interconnect layer over a semiconductor material on which one or more transistors or other devices are formed. Implementations of the invention may be formed or carried out on an underlying substrate110, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the scope of the present invention.

Referring now toFIG. 1B, photoresist material180is deposited into the openings120. In an embodiment, the photoresist material may be spun-on. The photoresist material180may be any suitable photoresist material, such as a positive or negative photoresist material. By way of example, the photoresist material180may be a chemically amplified resist (CAR).

Referring now toFIG. 1C, the photoresist material180is patterned in order to define openings120that will be used to form via openings120V. For example, a photolithography mask (not shown) may be used to selectively expose desired openings120. Thereafter, the exposed photoresist material180may be developed in order to clear the exposed portions of the photoresist material. In the illustrated embodiment, the photoresist material180is removed from each of the openings120where a via opening120Vis not desired. It is to be appreciated that, while two via openings120Vare illustrated inFIG. 1C, additional embodiments may include as few as one via opening120Vor more than two via openings120V.

Referring now toFIG. 1D, a dielectric material is deposited into each of the openings120. The dielectric material is used to form pillars135that will support the floating interconnect lines that will be formed in a subsequent processing operation. As illustrated in the cross-sectional view along line b-b′, two pillars135are formed in openings120, though embodiments are not limited to such configurations. According to an embodiment, the pillars135may be formed with a low-k dielectric material. In an embodiment, the pillars135may be a hardmask material. By way of example, the pillars may be silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, silicon nitrides, metal oxides, metal nitrides, or the like. Additional embodiments may include other dielectric materials, such as fluorocarbon based dielectrics, oxyfluorides, carbon based dielectrics, or the like. Embodiments include depositing the pillars135into the openings120with any suitable process, such as, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a spin coating process, or the like. According to an embodiment, any overburden from the deposition process may be removed with a polishing operation.

Referring now toFIG. 1E, the photoresist material180is removed from the via openings120V. In an embodiment, the photoresist material180may be removed with an ashing process. Though not illustrated inFIG. 1E, it is to be appreciated that if the underlying substrate110is an etchstop layer, then an etching process may be implemented to extend the openings120Vthrough the underlying substrate110so that contact to an underlying interconnect layer may be made.

Referring now toFIG. 1F, vias125are formed in the via openings120V. According to an embodiment, the vias125may be any suitable conductive material, stacks of conductive materials, and/or conductive alloys. By way of example, the vias125may include Ag, Au, Co, Cu, Mo, Ni, NiSi, Pt, Ru, TiN, W, or the like. Embodiments of the invention include depositing the vias125with any suitable deposition process, such as PVD, CVD, ALD, electroplating, electroless plating, or the like. Overburden from the deposition of the conductive material may then be recessed, (e.g., with a polishing process) to ensure that a top surface of the vias125are substantially coplanar with a top surface of the pillars135.

Referring now toFIG. 1G, the thickness of the sacrificial material layer160is increased by depositing a second layer of sacrificial material layer160over the top surfaces of each of the vias125and the pillars135. According to an embodiment, the thickness of the sacrificial material160is increased so that an interconnect line trench may be patterned over the top surfaces of the vias125and the pillars135. Additionally, a permeable etchstop layer170is disposed over the top surface of the sacrificial material160. As illustrated in the plan view, the locations of the openings120,120Vare illustrated as dashed lines in order to indicate that they are formed below the surface of the permeable etchstop layer170. The permeable etchstop layer170is a material that will allow the sacrificial material160to be removed through it. For example, in a subsequent processing operation, the sacrificial material160may be dissolved and the dissolved sacrificial material is able to pass through the permeable etchstop layer170in order to remove the sacrificial material160from the interconnect layer100. According to an embodiment, the permeable etchstop layer170is a porous dielectric material that has a k-value that is sufficient for use as an etchstop material. In an embodiment, the permeable etchstop layer170may be a porous oxide or nitride of silicon or aluminum. By way of example, the permeable etchstop layer170may include carbon-doped silicon oxides, silicon-nitrides, or the like. In an embodiment, once the sacrificial material160is removed through the permeable etchstop layer170, the porosity of the permeable etchstop layer170may be reduced. For example, the pores in the permeable etchstop layer170may be plugged with an additional dielectric material with a plugging process that will be described in greater detail below.

Referring now toFIG. 1H, interconnect line trenches192are formed through the permeable etchstop layer170and the sacrificial material160. According to an embodiment, the trenches may be patterned with a photolithography process known in the art and etched with a dry etching process. As illustrated, the trenches192expose top surfaces of the vias125and the pillars135.

Referring now toFIG. 1I, interconnect lines154are formed in the interconnect line trenches192. According to an embodiment, the interconnect lines154may be formed with any suitable deposition process and with any suitable conductive material, such as those described above with respect to the materials used to form the vias125. In one embodiment, the interconnect lines154are formed with the same material used to form the vias125. As illustrated inFIG. 1I, the interconnect lines are supported from below by the vias125and the pillars135in addition to the sacrificial material160.

Referring now toFIG. 1J, the interconnect lines154may be recessed and an etchstop layer157may be formed over the top surface of the interconnect lines154. According to an embodiment, the top surface of the interconnect lines154are recessed with an etching process. After the interconnect lines154are recessed, the etchstop layer157is deposited over the top surface of the interconnect lines154. Overburden from the deposition of the etchstop layer157may be polished or etched back to ensure that a top surface of the etchstop layer157is substantially coplanar with a top surface of the permeable etchstop layer170. Recessing the interconnect lines154allows for the etchstop layer157to be self-aligned with the interconnect lines154. According to an embodiment, the etchstop layer157is a material that is etch selective to the permeable etchstop layer170. The differences in etch selectivity between the etchstop layer157and the permeable etchstop layer170allow for the formation of vias in subsequent interconnect lines to be misaligned from the interconnect line154, as will be described in greater detail below. By way of example, the etchstop layer157may be any suitable hardmask material, such as SiOxCyNzmaterials, SiOXCYmaterials, metal oxide materials, metal nitride materials, or the like.

Referring now toFIG. 1K, the sacrificial material160is removed from the interconnect layer100. According to an embodiment of the invention, the sacrificial material160may be removed with a wet etching process. The wet etching chemistry may dissolve the sacrificial material160which can then be removed through the permeable etchstop layer170. According to an embodiment, the wet etching process utilizes an etching chemistry that selectively removes the sacrificial material160without substantially removing portions of the interconnect lines154, the vias125, or the pillars135. Since the interconnect lines154are supported from below by the vias125and the pillars135, the removal of the sacrificial material does not decrease the structural integrity of the interconnect layer100. By way of example, when the sacrificial material160is TiN, the sacrificial material160may be removed with a wet etching chemistry that comprises an aqueous solution of hydrogen peroxide having a concentration of about 3-50% by volume, a hydroxide source having a concentration of about 50 to 1,000 ppm by volume, and a corrosion inhibitor having a concentration of about 100 to 4,000 ppm by volume. In a specific embodiment, the removal chemistry comprises an aqueous solution of hydrogen peroxide having a concentration of about 15% by volume, potassium hydroxide having a concentration of about 100 to 250 ppm by volume and a 1,2,4-triazole corrosion inhibitor having a concentration of about 100 to 250 ppm by volume. The removal of the sacrificial material layer160can be performed in an immersion mode or a spinning mode. In the immersion mode, the entire structure is dipped into the removal chemistry to remove the sacrificial material layer160. In the spinning mode, the removal chemistry is sprayed or drained onto the surface of the structure that is spinning. In one embodiment, the removal of the sacrificial material layer160is performed at a temperature of about 40 to 60 degrees Celsius for a time duration of about 3 to 10 minutes.

As illustrated, the removal of the sacrificial material160produces air gaps140in the interconnect layer100. For example, air gaps140may be formed between sidewalls151of neighboring interconnect lines154, and below the bottom surface152of the interconnect lines154. Accordingly, the interconnect lines154may be referred to as floating interconnect lines, because portions of the bottom surface152of the interconnect lines154may not be supported by any material. In such embodiments, the floating interconnect lines154may be supported along portions of the bottom surface152by one or more vias125and one or more pillars135. As illustrated, the interconnect line154in the cross-sectional view along line b-b′ is supported by two vias125and two pillars135, however it is to be appreciated that embodiments of the invention are not limited to such configurations. For example, a floating interconnect line may be supported by one or more vias125. Additionally, embodiments of the invention may also include no pillars135below the interconnect lines154. The number of supports (either vias125or pillars135) needed to support an interconnect line154may be dependent on the length of the interconnect line154. In an embodiment, the interconnect line154may need support from below at a regular spacing along its length. The spacing between each support may be dependent on the thickness of the interconnect line154, the width of the interconnect line154, the material the interconnect line154is formed from, or the like. By way of example, supports may need to be formed at intervals of approximately 20 nm or less. In an embodiment, the interconnect line154may need to be supported at intervals of approximately 10 nm or less.

Referring now toFIG. 1L, the permeable etchstop layer170is hardened to increase the structural integrity of the interconnect layer100. For example, the permeable etchstop layer170may be hardened by applying a fill material (not shown) that fills the pores of the permeable etchstop layer170to form a hardened etchstop layer171. For example, the hardening may be performed by spin coating a dielectric layer over the surface of the permeable etchstop layer170. The viscosity of the coating may be chosen so that it readily fills the pores. In an embodiment, the fill material may be a polymer material. The polymer chosen may be chosen so that the molecular size and functional groups of the polymer are adequately sized to fill pores of the permeable etchstop layer170. By way of example, one polymer that may be used as a fill material is poly(methyl methacrylate) (PMMA). In an embodiment, the fill material may be spun on over the surface, and an anneal process (e.g., a thermal anneal, remote plasma, microwave anneal, laser spiking anneal, or the like) may be implemented to drive the polymer into the permeable etchstop layer170and remove solvents on the surface of the etchstop layer. According to an embodiment, the fill material chosen to harden the etchstop layer171may also increase the etch selectivity of the hardened etchstop layer171with respect to the etchstop layer157.

Referring now toFIG. 1M, the next interconnect layer is formed over the top surfaces of the hardened etchstop layer171and the etchstop layer157formed over the interconnect lines154. According to an embodiment, the next interconnect layer may be formed in a dielectric layer166. By way of example, the dielectric layer166may be a low-k or ultra low-k dielectric material. Additional embodiments may include a dielectric layer166that is a sacrificial dielectric material similar to sacrificial material160. In such embodiments, the subsequently formed interconnect layer may also include air gaps similar to those illustrated inFIG. 1L. As illustrated, interconnect lines164are formed in the dielectric layer166. Additionally, one or more vias163may be formed between an interconnect line164and an interconnect line154.

According to an embodiment, the via163may not be perfectly aligned with the interconnect line154. For example, a portion of the via163may not be formed over a top surface of the interconnect line154. Since the etchstop material157is etch selective to the hardened etchstop layer171, the etching process used to form the via opening for via163will only remove the etchstop material157and the hardened etchstop layer171remains substantially unaltered. In such an embodiment, a bottom surface of the via163may contact the interconnect line154and a top surface161of the hardened etchstop layer171, as shown in the cross-sectional view along line b-b′ inFIG. 1M.

Embodiments of the invention may also form floating interconnect lines that are supported from below with dual damascene processes. In contrast to the method of forming floating interconnect lines described above with respect toFIGS. 1A-1Mwhere the vias125and the interconnect lines154were formed with separate metal deposition processes, embodiments of the invention may also include forming the vias and the interconnect lines with a single metal deposition process (i.e., a dual damascene process). An example of the formation of a floating interconnect line with a dual damascene process is described below with respect toFIGS. 2A-2N.

Referring now toFIG. 2A, a cross-sectional view of an interconnect layer is illustrated according to an embodiment. InFIG. 2A, a first trench292is formed through a permeable etchstop layer270and into a sacrificial material layer260formed over an underlying substrate210. According to an embodiment, the sacrificial material260, the permeable etchstop layer270and the underlying substrate210are substantially similar to those described above with respect toFIGS. 1A-1M. In an embodiment, the first trench292is formed with a length that is substantially the length required for a floating interconnect line that will be formed in a subsequent processing operation. By way of example, the first trench292may be formed with a dry-etching process.

Referring now toFIG. 2B, a cross-grating pattern215is formed over the sacrificial material layer260in the first trench. The cross-grating pattern215may be substantially similar to the pattern formed in the sacrificial material160described inFIGS. 1A-1N. As such, a plurality of openings220may be formed. According to an embodiment, each of the openings220may be used for the formation of a via or a pillar. It is to be appreciated that the cross-grating pattern215does not need to be a sacrificial material that is dissolvable. Accordingly, embodiments of the invention may include a cross-grating pattern215formed with a hardmask material, such as a carbon hardmask. By way of example, the cross-grating pattern may be formed with one or more photolithography patterning operations, DSA patterning, or the like.

Referring now toFIG. 2C, photoresist material280is deposited into the openings220. In an embodiment, the photoresist material may be spun-on. The photoresist material280may be any suitable photoresist material, such as a positive or negative photoresist material. By way of example, the photoresist material280may be a chemically amplified resist (CAR).

Referring now toFIG. 2D, the photoresist material280is patterned in order to define openings220that will be used to form via openings220V. For example, a photolithography mask (not shown) may be used to selectively expose desired via openings220V. Thereafter, the exposed photoresist material280may be developed in order to clear the exposed portions of the photoresist material280in each of the openings220where a via opening220Vis desired. After the photoresist material280is removed from via openings220V, the underlying sacrificial material260is removed, for example with a dry-etching process. It is to be appreciated that, while two via openings220Vare illustrated inFIG. 2C, additional embodiments may include as few as one via opening220Vor more than two via openings220V.

Referring now toFIG. 2E, a sacrificial fill material213is deposited into each of the via openings220V. According to an embodiment, any overburden from the deposition of the sacrificial fill material213may be removed with an etching process. Referring now toFIG. 2F, the remaining photoresist material280is removed from the openings220. In an embodiment, the photoresist material280may be removed with an ashing process.

Referring now toFIG. 2G, the sacrificial material260below the openings220is removed. By way of example, the sacrificial material may be removed with a dry-etching process that utilizes the sacrificial fill material213and the cross-grating pattern215as an etch mask. Thereafter, inFIG. 2H, the pillars235are formed in the openings220. According to an embodiment, the pillars235may be formed with a low-k dielectric material. In an embodiment, the pillars235may be a hardmask material. By way of example, the pillars235may be silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, silicon nitrides, metal oxides, metal nitrides, or the like. Additional embodiments may include other dielectric materials, such as fluorocarbon based dielectrics, oxyfluorides, carbon based dielectrics, or the like. Embodiments include depositing the pillars235into the openings220with any suitable process, such as, for example, PVD, CVD, ALD, spin coating, or the like. In an embodiment, any overburden from the deposition of the pillars235may be removed with an etching process.

Referring now toFIG. 2I, the sacrificial fill material213and the cross-grating pattern215are removed. In an embodiment, the sacrificial fill material213and the cross-grating pattern215may be removed with one or more etching processes that selectively remove the sacrificial fill material213and the cross-grating pattern215without substantially removing the sacrificial material260and the pillars235.

Referring now toFIG. 2J, vias225and interconnect line254are formed with a deposition process. According to an embodiment, the vias225and the interconnect line254may be formed with any suitable conductive material. By way of example, the conductive material may include Ag, Au, Co, Cu, Mo, Ni, NiSi, Pt, Ru, TiN, W, or the like. Embodiments of the invention include depositing the vias125with any suitable deposition process, such as PVD, CVD, ALD, electroplating, electroless plating, or the like. In an embodiment, overburden from the deposition of the conductive material may then be recessed, with a polishing process to ensure that a top surface of the interconnect line254is substantially coplanar with a top surface of the permeable etchstop layer270. As illustrated, the vias225are separated from the interconnect line254by a dashed line. However, it is to be appreciated that a single deposition process may be used to form both the interconnect line254and the vias225, and therefore, there may be no discernable distinction between the two features in a finished device.

Referring now toFIG. 2K, the interconnect line254may be recessed to form a recess293. By way of example, the recess293may be formed with an etching process. Forming the recess293allows for the formation of an etchstop layer257that is self-aligned over the interconnect line254, as illustrated inFIG. 2L. According to an embodiment, the etchstop layer257may be a material that is etch selective to the permeable etchstop layer270. As such, misaligned vias in a subsequently formed interconnect layer will be prevented from breaking through to the air-gaps below.

Referring now toFIG. 2M, the sacrificial material260is removed from the interconnect layer. According to an embodiment of the invention, the sacrificial material260may be removed with a wet-etching process. The wet-etching chemistry may dissolve the sacrificial material260which can then be removed through the permeable etchstop layer270. According to an embodiment, the wet-etching process utilizes an etching chemistry that selectively removes the sacrificial material260without substantially removing portions of interconnect lines254, the vias225, or the pillars235. Additional embodiments may include a sacrificial material260that is removable through the permeable layer270with a vapor phase process, with a plasma process, or the like. Since the interconnect lines254are supported from below by the vias225and the pillars235, the removal of the sacrificial material260does not decrease the structural integrity of the interconnect layer. By way of example, when the sacrificial material260is TiN, the sacrificial material260may be removed with a wet etching chemistry that comprises an aqueous solution of hydrogen peroxide having a concentration of about 3-50% by volume, a hydroxide source having a concentration of about 50 to 1,000 ppm by volume, and a corrosion inhibitor having a concentration of about 100 to 4,000 ppm by volume.

As illustrated, the removal of the sacrificial material260produces air gaps240in the interconnect layer. For example, air gaps240may be formed between sidewalls of the interconnect lines254, and below the bottom surface of the interconnect lines254. Accordingly, the interconnect lines254may be referred to as floating interconnect lines, because portions of the bottom surface of the interconnect lines254may not be supported by any material. In such embodiments, the floating interconnect lines254may be supported along the bottom surface by one or more vias225and one or more pillars235. As illustrated, the interconnect line254is supported by two vias225and two pillars235, however it is to be appreciated that embodiments of the invention are not limited to such configurations. For example, a floating interconnect line may be supported by one or more vias225. Additionally, embodiments of the invention may also include no pillars235below the interconnect line254. The number of supports (either vias225or pillars235) needed to support an interconnect line may be dependent on the length of the interconnect line. In an embodiment, the interconnect line254may need support from below at a regular spacing along its length. The spacing between each support may be dependent on the thickness of the interconnect line254, the width of the interconnect line, the material the interconnect line is formed from, or the like. By way of example, supports may need to be formed at intervals of approximately 20 nm or less. In an embodiment, the interconnect line254may need to be supported at intervals of approximately 10 nm or less.

Referring now toFIG. 2N, the permeable etchstop layer270is hardened to increase the structural integrity of the interconnect layer. For example, the permeable etchstop layer270may be hardened by applying a fill material (not shown) that fills the pores of the permeable etchstop layer270to form a hardened etchstop layer271. For example, the hardening may be performed by spin coating a dielectric layer over the surface of the permeable etchstop layer270. The viscosity of the coating may be chosen so that it readily fills the pores. According to an embodiment, the fill material chosen to harden the etchstop layer271may also increase the etch selectivity of the hardened etchstop layer271with respect to the etchstop layer257. Embodiments of the invention may utilize a fill material, such as a polymer, that is substantially similar to those described above with respect to the fill materials used to harden the etchstop layer171. After the permeable etchstop layer270is hardened into a hardened etchstop layer271, an additional interconnect layer may be formed over the etchstop layer257and the hardened etchstop layer271, according to an embodiment. The formation of a subsequent interconnect layer is substantially similar to the process described above with respect toFIG. 1M, and therefore, will not be repeated here.

Additional embodiments of the invention may also include a process for forming floating interconnect lines with an additional dual damascene process. Such an embodiment is described below with respect toFIGS. 3A-3F.

Referring now toFIG. 3A, an interconnect structure substantially similar to the interconnect structure described above with respect toFIG. 2Bis shown. In the illustrated embodiment, a trench392is formed through a permeable etchstop layer370and into a sacrificial material360with a cross-grating pattern315formed in the trench.

Referring now toFIG. 3B, openings320vand320are formed through the sacrificial material360to expose an underlying substrate310. The openings320vand320may be formed with a dry-etching process that utilizes the cross-grating pattern315as an etch mask. According to an embodiment, two via openings320Vand two pillar openings320are formed.

Referring now toFIG. 3C, the openings320Vand320are filled with a photoresist material380. In an embodiment, the photoresist material380may be spun-on. The photoresist material380may be any suitable photoresist material, such as a positive or negative photoresist material. By way of example, the photoresist material380may be a chemically amplified resist (CAR).

Referring now toFIG. 3D, the photoresist material380in the pillar openings320is patterned. For example, a photolithography mask (not shown) may be used to selectively expose desired pillar openings320. Thereafter, the exposed photoresist material380may be developed in order to clear the exposed portions of the photoresist material from the pillar openings320. Thereafter, the pillar openings320may be filled with a dielectric material to form pillars335, as illustrated inFIG. 3E. According to an embodiment, the pillars335may be formed with a low-k dielectric material. In an embodiment, the pillars335may be a hardmask material. By way of example, the pillars may be silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, silicon nitrides, metal oxides, metal nitrides, or the like. Additional embodiments may include other dielectric materials, such as fluorocarbon based dielectrics, oxyfluorides, carbon based dielectrics, or the like. Embodiments include depositing the pillars335into the openings320with any suitable process, such as, for example, PVD, CVD, ALD, a spin coating process, or the like. According to an embodiment, the pillars335may be etched back to the desired height after the dielectric material has been deposited.

Referring now toFIG. 3F, the remaining photoresist material380may be removed from the via openings320Vand the cross-grating pattern315may be removed. For example, the photoresist material380may be removed with an ashing process and the sacrificial cross-grating pattern315may be removed with an etching process. After the removal of the photoresist material380and the cross-grating material315, the interconnect layer inFIG. 3Fis substantially similar to the interconnect structure illustrated inFIG. 2I. Accordingly, the vias and interconnect lines may be formed according to substantially the same processing operations disclosed with respect toFIGS. 2K-2Nin order to form floating interconnect lines with air gaps between and below each interconnect line.

FIG. 4illustrates an interposer400that includes one or more embodiments of the invention. The interposer400is an intervening substrate used to bridge a first substrate402to a second substrate404. The first substrate402may be, for instance, an integrated circuit die. The second substrate404may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer400is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer400may couple an integrated circuit die to a ball grid array (BGA)406that can subsequently be coupled to the second substrate404. In some embodiments, the first and second substrates402/404are attached to opposing sides of the interposer400. In other embodiments, the first and second substrates402/404are attached to the same side of the interposer400. And in further embodiments, three or more substrates are interconnected by way of the interposer400.

The interposer may include metal interconnects408and vias410, including but not limited to through-silicon vias (TSVs)412. The interposer400may further include embedded devices414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer400.

In accordance with embodiments of the invention, apparatuses that include floating interconnect lines with air gaps below and between interconnect lines or processes for forming such devices disclosed herein may be used in the fabrication of interposer400.

FIG. 5illustrates a computing device500in accordance with one embodiment of the invention. The computing device500may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device500include, but are not limited to, an integrated circuit die502and at least one communication chip508. In some implementations the communication chip508is fabricated as part of the integrated circuit die502. The integrated circuit die502may include a CPU504as well as on-die memory506, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device500may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory510(e.g., DRAM), non-volatile memory512(e.g., ROM or flash memory), a graphics processing unit514(GPU), a digital signal processor516, a crypto processor542(a specialized processor that executes cryptographic algorithms within hardware), a chipset520, an antenna522, a display or a touchscreen display524, a touchscreen controller526, a battery528or other power source, a power amplifier (not shown), a global positioning system (GPS) device528, a compass530, a motion coprocessor or sensors532(that may include an accelerometer, a gyroscope, and a compass), a speaker534, a camera536, user input devices538(such as a keyboard, mouse, stylus, and touchpad), and a mass storage device540(such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor504of the computing device500includes one or more devices, such as transistors that are coupled to one or more self-aligned interconnect lines, vias, or plugs that are formed in an interconnect structure that that are formed with a subtractive patterning operation that utilizes a textile patterned hardmask layer, according to an embodiment of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip508may also include one or more devices, such as transistors that are coupled to one or more floating interconnect lines with air gaps below and between interconnect lines, according to an embodiment of the invention.

In further embodiments, another component housed within the computing device500may contain one or more devices, such as transistors that are coupled to one or more floating interconnect lines with air gaps below and between interconnect lines, according to an embodiment of the invention.

Embodiments of the invention include an interconnect layer that comprises an interconnect line, wherein first portions of a bottom surface of the interconnect line are bordered by an air-gap; and one or more vias formed in contact with second portions of the bottom surface of the interconnect line, wherein the one or more vias are bordered by air-gaps.

Additional embodiments of the invention include an interconnect layer that further comprises: one or more pillars formed in contact with the second portions of the bottom surface of the interconnect line, wherein the one or more pillars are bordered by air-gaps.

Additional embodiments of the invention include an interconnect layer, wherein the pillars are a low-k dielectric material.

Additional embodiments of the invention include an interconnect layer, wherein the one or more pillars are spaced apart from each other by 20 nm or less.

Additional embodiments of the invention include an interconnect layer, wherein a first etchstop layer is formed over a top surface of the interconnect line.

Additional embodiments of the invention include an interconnect layer, wherein a second etchstop layer that is etch selective to the first etchstop layer is formed adjacent to the first etchstop layer, and wherein the second etchstop layer is formed over the air-gaps.

Additional embodiments of the invention include an interconnect layer, wherein the second etchstop layer is a porous dielectric material that has pores filled with a pore plugging dielectric material.

Additional embodiments of the invention include an interconnect layer that further comprises a next level via formed through the first etchstop layer and in contact with a top surface of the interconnect line and wherein the next level via also contacts a top surface of the second etchstop layer.

Additional embodiments of the invention include an interconnect layer that further comprises a second interconnect line, wherein first portions of a bottom surface of the second interconnect line are bordered by an air-gap.

Additional embodiments of the invention include an interconnect layer, wherein a sidewall of the second interconnect line is separated from a sidewall of the first interconnect line by an air-gap.

Embodiments of the invention include a method of forming an interconnect layer, that comprises: forming a plurality of openings in a first sacrificial material layer, wherein the openings include one or more pillar openings and one or more via openings; forming pillars in the pillar openings and vias in the via openings; forming a second sacrificial material layer over a top surface of the pillars, the vias, and the first sacrificial material layer; forming a permeable etchstop layer over a top surface of the second sacrificial layer; forming an interconnect line trench through permeable etchstop layer and into the second sacrificial layer so that the vias and the pillars are exposed; forming an interconnect line in the interconnect line trench, wherein a top surface of the interconnect layer is covered by an etchstop layer, wherein a top surface of the etchstop layer is substantially coplanar with a top surface of the permeable etchstop layer; removing the first and second sacrificial material layers through the permeable etchstop layer; and hardening the permeable etchstop layer so that the permeable etchstop layer is no longer permeable.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the first and second sacrificial material layers are titanium nitride.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein removing the first and second sacrificial material layers includes applying a wet etching chemistry that dissolves the first and second sacrificial layers and removing the dissolved first and second sacrificial materials through the permeable etchstop layer.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein hardening the permeable etchstop layer includes applying a plugging material over the surface of the permeable etchstop layer.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the plugging material is spin coated over the surface of the permeable etchstop layer.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the etchstop layer formed over the interconnect line is self-aligned with the interconnect line.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the etchstop layer formed over the interconnect line is self-aligned with the interconnect line by recessing the interconnect line so that a top surface of the interconnect line is below a top surface of the permeable etchstop layer, and then filling the recess above the interconnect line with the etchstop layer so that a top surface of the etchstop layer is substantially coplanar with a top surface of the permeable etchstop layer.

Embodiments of the invention include a method of forming an interconnect layer, comprising: forming a first opening through a permeable etchstop layer and into a sacrificial material layer formed below the permeable etchstop layer; forming a cross-grating pattern in the first opening, wherein the cross-grating pattern includes a plurality of pillar openings and via openings; removing the sacrificial material below the pillar openings and the via openings; forming a masking material in the via openings; forming pillars in the pillar openings; removing the masking material in the via openings; forming vias in the via openings and an interconnect line above the vias and the pillars, wherein a top surface of the interconnect layer is covered by an etchstop layer, and wherein a top surface of the etchstop layer is substantially coplanar with a top surface of the permeable etchstop layer; removing the sacrificial material layer through the permeable etchstop layer; and hardening the permeable etchstop layer so that the permeable etchstop layer is no longer permeable.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the sacrificial material below the pillar openings and the sacrificial material below the via openings are removed with the same etching process.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the masking material in the via openings is a photoresist material.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the sacrificial material below the pillar openings and the sacrificial material below the via openings are removed with different etching processes.

Additional embodiments of the invention include a method of forming an interconnect layer, wherein the masking material in the via openings is a sacrificial hardmask material.

Embodiments of the invention include an interconnect layer that comprises an interconnect line, wherein first portions of a bottom surface of the interconnect line are bordered by an air-gap, and wherein a first etchstop layer is formed over a top surface of the interconnect line; one or more vias formed in contact with second portions of the bottom surface of the interconnect line, wherein the one or more vias are bordered by air-gaps; one or more pillars formed in contact with the second portions of the bottom surface of the interconnect line, wherein the one or more pillars are bordered by air-gaps; and a second etchstop layer that is etch selective to the first etchstop layer formed adjacent to the first etchstop layer and over the air-gaps, wherein the second etchstop layer is a porous dielectric material that has pores filled with a pore plugging material.

Additional embodiments of the invention include an interconnect layer that further comprises a next level via formed through the first etchstop layer and in contact with a top surface of the interconnect line and wherein the next level via also contacts a top surface of the second etchstop layer.

Additional embodiments of the invention include an interconnect layer, wherein the sacrificial material is titanium nitride.