Semiconductor integrated circuit

A semiconductor integrated circuit includes a local memory permitting high-speed access. The local memory has at least first and second ports. The first port of the local memory is connected to a CPU by a first bus and the second port of the local memory is connected to an access control unit by a second bus. An external device is connected to the access control unit. When the CPU and/or the external device accesses the local memory, the CPU sends a control signal and data to the first port (CPU-access port) of the local memory via the first bus, and the access control unit sends another control signal and data to the second port (external-device-access port) of the local memory via the second bus. The local memory then executes data writing or reading based on the control signal(s) and data thus introduced to the access port(s). The external device can access the local memory via the access control unit to transfer data at high speed to and from the local memory.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit that performs information processing by using a central processing unit (CPU), and, more particularly, to a semiconductor integrated circuit that is capable of transferring data at high speed to and from the outside.

2. Description of the Related Art

Conventionally, a CPU in a semiconductor integrated circuit that performs information processing is connected to a main memory via a bus, and is designed to transfer information to and from the outside (e.g., an external device or network) via the main memory. Because the access speed of the main memory is low (slow) in comparison with the processing speed of the CPU, the CPU is also connected to a cache memory that has a higher (faster) access speed than the main memory. The CPU accelerates information processing by temporarily storing a portion of the information stored in the main memory in the cache memory, and then delivering the information to and from the cache memory. An example of this kind of CPU is disclosed in Japanese Patent Kokai (Laid Open Publication) No. H8-180008.

In this semiconductor integrated circuit, when information is transferred to and from the external device via the main memory, the CPU is unable to transfer information at high speed because the main memory access speed is low. If the CPU has a cache memory, direct access to the cache memory from the external device may be considered. However, the cache memory requires the information stored in the cache memory to be the same as the information stored in the main memory. Therefore, it is not feasible to write and read information into and from the cache memory unless the same information is stored in the main memory.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a semiconductor integrated circuit that is capable of transferring information at high speed to and from the external device.

According to one aspect of the present invention, there is provided a semiconductor integrated circuit that includes a central processing unit, a main memory control unit for controlling a main memory, and an I/O channel control unit for controlling a peripheral device. The central processing unit, main memory control unit and I/O channel control unit are connected to one another by a first bus. The semiconductor integrated circuit also includes a local memory for storing information. The local memory is connected to the central processing unit by a second bus. The semiconductor integrated circuit also includes an access controller connected to the local memory by a third bus. The access controller accesses the local memory in accordance with a request from outside (e.g., an external device or network).

The local memory preferably includes a first access port connected to the second bus and a second access port connected to the third bus. If the local memory has two access ports, the local memory can be accessed by the CPU and from the external device independently. Therefore, even when the CPU is operating, data can be transferred between the external device and the local memory. In addition, because the local memory access speed is faster that that of the main memory, data can be transferred at high speed between the semiconductor integrated circuit and the external device via the local memory.

It should be noted that the local memory may have a sole access port. Such local memory affords benefits such as a further increase in the data transfer speed and a reduced mounting area, when compared with the local memory having two access ports.

The semiconductor integrated circuit may further include a selector connected between the second and third buses and the local memory. The selector may select the second bus or the third bus, and connect the selected bus to the local memory.

In this case, the semiconductor integrated circuit preferably further includes an arbitrator device that issues instructions to the selector regarding the selection of the bus, on the basis of access requests to the local memory from the central processing unit and the access controller.

Other objects, aspects and advantages of the present invention will become apparent to those skilled in the art to which the invention pertains from the following detailed description and appended claims when read and understood in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the semiconductor integrated circuit according to the present invention will be described in detail with reference to the attached drawings.

Referring toFIG. 1, the semiconductor integrated circuit1includes a central processing unit (CPU)10, local memories12and14, an access control unit16, a main memory control unit18, and an I/O channel control unit20. The CPU10, main memory control unit18, and I/O channel control unit20are connected to each other by a bus30. The CPU10is connected to the local memories12and14by buses32and34respectively. The local memory14and access control unit16are connected to each other by a bus36. The access control unit16is connected to the outside (e.g., an external device or a network)40by a bus38.

A main memory22and peripheral device24provided outside the semiconductor integrated circuit1are connected to the main memory control unit18and I/O channel control unit20respectively. The buses32,36, and38include an address line, write data line, read data line, element select line, and/or read/write select line, for example, and thus constitute transmission channels for transmitting addresses, write data, read data, element select signals, and read/write select signals.

The CPU10is a computation/control device that executes predetermined processing by reading commands, data, and so forth, from the main memory22and generally has a built-in cache memory. The large-capacity main memory22, which stores programs, data, and so forth, is connected to the main memory control unit18. The main memory control unit18controls the reading and writing of programs, data, and so forth from and to the main memory22in accordance with commands from the CPU10. The peripheral device(s)24, such as a display and a printer, is (are) connected to the I/O channel control unit20. The I/O channel control unit20controls the operation of the peripheral device(s)24in accordance with the commands from the CPU10. The I/O channel control unit20also controls information transfer and other operations in accordance with the commands from the CPU10.

The local memories12and14are a semiconductor memory with a smaller capacity than the main memory22but with a faster access speed than the main memory22. Thus, the local memories12and14permit high-speed access. In this embodiment, the local memories12and14do not assume a cache memory function. Therefore, information that is different from the information stored in the main memory22can be stored in the local memories12and14. The local memory12is constituted by, for example, a memory for storing information, such as RAM (Random Access Memory). The CPU10is able to access the local memory12at any time via the dedicated bus32.

The local memory14is a memory that stores information and has at least two access ports. In this embodiment, the local memory14is a dual-port RAM; one port is used as a port dedicated to CPU access and the other port is used as a port dedicated to external device access. The CPU10is connected to the CPU-access port by the bus34and the access control unit16is connected to the external-device-access port by the bus36. The access control unit16operates as an interface between the local memory14and the external device40, and accesses the local memory14in accordance with a request from the external device40that is supplied via the bus38.

The local memory14therefore has a CPU-access port and an external-device-access port that can each be accessed independently of the other. Hence, the CPU10is able to access the local memory14irrespective of access to the local memory14from the external device40, and the local memory14can be accessed by the external device40irrespective of access to the local memory14by the CPU10. Therefore, even when the CPU10is operating, data can be transferred between the local memory14and the external device40, and data can be simultaneously read from the same address in the local memory14by the CPU10and the external device40.

The operation of the semiconductor integrated circuit1will now be described.

For example, the CPU10writes a program with a high usage frequency to the local memory12and executes information processing by reading this program. When accessing the local memory14, the CPU10and access control unit16issue data (in the case of data writing) and a control signal (address, element select signal, and read/write select signal, for example) to the local memory14via the buses34and36, respectively.

The local memory14captures the data and control signal(s) from the buses34and36and executes the data writing or data reading on the basis of the data and control signal(s) thus captured. When data writing is executed, the data thus read out is output to the bus34or36. The CPU10captures the data from the bus34, and the access control unit16captures the data from the bus36and outputs this data to the external device40via the bus38.

As described above, the local memory14includes a CPU-access dedicated port and an external-device-access dedicated port, so that the CPU10and access control unit16are able to access the local memory14independently of one another. It should be noted that, however, that this excludes simultaneous data writing to the same address from the CPU10and access control unit16(or the external device40).

Therefore, even when the CPU10is accessing the local memory14, the external device40can read data stored in the local memory14. In addition, because the access speed of the local memory14is faster than that of the main memory22, the external device40can read data stored in the local memory14within a short(er) time.

FIG. 2is a block diagram showing another embodiment of the semiconductor integrated circuit according to the present invention. Referring now toFIG. 2, the semiconductor integrated circuit2includes a local memory50in place of the local memory14of the semiconductor integrated circuit1shown inFIG. 1. The semiconductor integrated circuit2also includes the central processing unit (CPU)10, the local memory12, the access control unit16, the main memory control unit18, the I/O channel control unit20, a selector52, and an arbitration circuit54. InFIGS. 1 and 2, similar reference symbols are assigned to similar elements.

Similar to the first embodiment shown inFIG. 1, the CPU10, main memory22, and peripheral device24constitute a general-purpose computer. The CPU10and local memory12are connected to each other by a bus32. The CPU10and selector52are connected to each other by a bus60. The CPU10is connected to the local memory50and the access control unit16by a bus62. The access control unit16and selector52are connected to each other by a bus64. The selector52and local memory50are connected to each other by a bus66. The arbitration circuit54is connected to the CPU10and access control unit16by interconnects68and70respectively. The selector52is connected to the arbitration circuit54by an interconnect69.

In this embodiment, the buses60,64and66include write data lines for transmitting write data, address lines for transmitting addresses, element select lines, and/or read/write select lines. The bus62is a read data line that transmits read data (data read from the local memory50).

Similar to the local memory14inFIG. 1, the local memory50is a memory that is mainly for storing data temporarily, such as semiconductor memory constituted by RAM. The local memory50has a smaller capacity than the main memory22but permits higher-speed access than the main memory22. Similar to the local memory14inFIG. 1, the local memory50does not assume a cache memory function. Unlike the local memory14, however, the local memory50has a sole access port. Hence, the local memory50cannot be accessed by the CPU10and the external device40simultaneously. The selector52and arbitration circuit54are therefore provided in this embodiment to arbitrate between an access request from the CPU10and an access request from the external device40.

In the semiconductor integrated circuit1ofFIG. 1, the local memory14is constituted by a dual-port RAM. Therefore, by rendering one port a CPU-access port and the other port an external-device-access port, the local memory14can be accessed by the CPU10and the external device40independently of one another. However, the dual-port RAM requires a larger mounting area than a single-port RAM, and operates with a slower access speed than the single-port RAM. Therefore, where emphasis is placed on the mounting area and/or the access speed, the local memory50constituted by a RAM with a single access port is preferred, as in this embodiment.

The selector52is a circuit that selectively connects either one of the bus60and bus64to the bus66in accordance with a select signal supplied via the interconnect69by the arbitration circuit54. More specifically, the selector52connects the bus60to the bus66when the select signal carries an instruction to connect the CPU10to the local memory50, and connects the bus64to the bus66when the select signal carries an instruction to connect the access control unit16to the local memory50. Upon this selection, addresses, write data, element select signals and read/write select signals that are output by the CPU10or access control unit16are introduced to the local memory50, and data writing or reading is executed in the local memory50.

In this embodiment, when desiring access to the local memory50, the CPU10and access control unit16issue an access request signal (e.g., an element select signal) to the arbitration circuit54via the interconnects68and70. The arbitration circuit54generates a select signal for connecting either of the CPU10and access control unit16to the local memory50on the basis of the access request signal that is supplied from the CPU10and access control unit16. The arbitration circuit54then sends this select signal to the selector52.

More specifically, upon (or prior to) receiving an access request signal from either the CPU10or the access control unit16, the arbitration circuit54determines whether the local memory50is executing data reading or writing, or not. If the local memory50is executing neither the data reading nor writing, the arbitration circuit54generates a select signal instructing a connection between the bus66and the bus60or64(the bus60when the CPU10makes the access request, and the bus64when the access control unit16makes the access request) and then supplies this select signal to the selector52. When access request signals are received simultaneously from the CPU10and access control unit16, the access request from the CPU10is prioritized, and thus a select signal instructing a connection between the bus60and bus66is generated and delivered to the selector52. The arbitration circuit54generates a selection display signal (or selection result signal) indicating the result of selection of the bus60or64, and sends it to the external device40via an interconnect72. It should be noted that the arbitration circuit54may give priority to the access request from the access control unit16when there is a conflict between access requests from the CPU10and access control unit16.

The operation of the semiconductor integrated circuit2will now be described. When desiring access to the local memory50, the CPU10and access control unit16issue an access request signal to the arbitration circuit54via the interconnects68and70respectively, and send addresses, write data (in the case of data writing), element select signals, read/write select signals, and so forth, to the buses60and64(or to the selector52) respectively.

When an access request signal is issued to the arbitration circuit54from the CPU10, and the local memory50is not currently being accessed by the access control unit16, the arbitration circuit54outputs a select signal instructing a connection between the buses60and66to the selector52. When an access request signal is issued from the access control unit16, and the local memory50is not being accessed by the CPU10and there is no conflict with an access request from the CPU10, the arbitration circuit54outputs a select signal instructing a connection between the buses64and66to the selector52. Then the arbitration circuit54outputs a selection result signal to the external device40via the interconnect72. The external device40can determine from this selection result signal whether the local memory50is being accessed by the CPU10.

The selector52connects the bus66to the bus60or bus64in accordance with a select signal from the arbitration circuit54. Accordingly, the addresses, write data, element select signals, and read/write select signals that are present on the bus60or bus64from the CPU10or access control unit16are then introduced to the local memory50via the selector52. The local memory50executes data writing or data reading based on the inputted addresses, write data, element select signals, and read/write select signals. When data is read, the local memory50outputs this data to the bus62. Then, the CPU10or access control unit16, which has made the access request, captures the data on the bus60. The access control unit16sends the captured data to the external device40via the bus38.

Therefore, according to this embodiment, when the CPU10is not accessing the local memory50, the local memory50can be directly accessed by the external device40even when the CPU10is operating, and hence data stored in the local memory50can be read by the external device40and data can be written to the local memory50by the external device40. Because the access speed of the local memory50is faster than that of the main memory22, the external device40can read the data stored in the local memory50at high speed.

This application is based on a Japanese patent application No. 2003-340511, and the entire disclosure thereof is incorporated herein by reference.