A semiconductor device includes: a first semiconductor chip having a metal layer on a top surface; a first wiring member arranged to face the metal layer; a sintered-metal layer arranged between the metal layer and the first wiring member, having a first region and a plurality of second regions provided inside the first region, the second regions having lower tensile strength than the first region; and a metallic member arranged inside the sintered-metal layer, wherein the second regions of the sintered-metal layer have lower tensile strength than the metal layer of the first semiconductor chip.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

2. Description of the Related Art

A general power semiconductor device includes a semiconductor element, such as an insulated gate bipolar transistor (IGBT), a MOS field effect transistor (MOSFET) and the like, an insulated circuit board, and a heat dissipation base. A lead frame may be used for joining between the semiconductor element, the insulated circuit board and the heat dissipation base with a joint material, such as a joining wire, a solder, and the like. In recent years, large-scale integration of circuits in power semiconductor devices has been expanding due to the demand for advanced features as well as reduction in size and weight. Further, development for application to a semiconductor device using a semiconductor element such as silicon carbide (SiC) capable of high-temperature operation has been promoted, and high reliability of the semiconductor device in a high-temperature operating environment is required.

A solder, such as tin antimony (SnSb), tin silver (SnAg) and the like, has been applied commonly as the joint material in the semiconductor device. However, as the operating temperature of the semiconductor device rises close to the melting point of the solder, reduced reliability may occur. Therefore, the application of a metal sintering paste or a sintered metal sheet that utilizes sintering of metal particles is being studied as the joint material capable of high-temperature operation. In JP 2012-138470 A, JP 2010-251457 A and JP 2010-245227 A, a structure in which a sintered metal material is used as a joining layer between the semiconductor element, the insulated circuit board and the wiring member has been proposed.

In the power semiconductor device, stress due to differences in thermal expansion coefficients between the members of the device may be generated in the joint layer during energization of the device or by a temperature change in the outer peripheral environment. Repeated stress generation may cause cracks in the joint layer due to thermal fatigue degradation. When the cracks extend and the extension lengths of the cracks increase, the thermal resistance increases and the temperature of heat generation during the energization rises. Thus, the semiconductor device may be led to the failure.

Regarding the failure mode caused by the cracks in the joint layer, the sintered metal, having 3 to 4 times higher strength than the solder materials, has been expected to prevent cracking and contribute to high temperature operation and improvement of reliability. However, it has been found that in the actual energization cycle, the cracks may not be generated in the sintered metal layer, but may be likely generated in the aluminum (Al) alloy layer of the electrode of the semiconductor chip. In the extending process of cracks generated in the electrode layer of the semiconductor element, the circuit may be broken by the semiconductor chip, resulting in an early failure.

Solutions to the occurrence of the cracks in the electrode layer of the semiconductor element are being studied. For example, JP 2010-245227 A describes that the recess is formed in the wiring layer of the insulated circuit board to concentrate the stress in the region of the joint layer in contact with the recess, so as to preferentially generate the cracks in the region in contact with the recess, and to prevent crack generation in the region of the joint layer where the joint layer is not in contact with the recess. Further, J P 2010-251457 A and WO 2017/002793 propose that the Al metal layer having a yield stress lower than that of the joint layer is used as the wiring layer of the insulated circuit board, and thus, the cracks are generated and extended in the wiring layer to improve the reliability of the joint layer. However, the Al alloy used for the electrode layer of the semiconductor chip and the Al metal of the wiring layer have comparable strength, and thus, it is difficult to control which layer the cracks occur. In addition, as the cracks occur and extend, the thermal resistance of the joint layer may increase, and the heat dissipation properties of the semiconductor chip may deteriorate. U.S. Pat. No. 8,987,879 describes that a plurality of protrusions are provided in the contact area of the contact clip connected to the lead frame, and the contact area is attached to the semiconductor element by using a solder member. However, U.S. Pat. No. 8,987,879 has no description about deterioration of the semiconductor chip due to the cracks. U.S. Pat. No. 9,929,111 describes the layer structure including two layers having different porosities. JP 2013-258122 A describes the adhesive containing silver particles of 90 mass % or more, and zinc particles of 0.01 mass % or more and 0.6 mass % or less.

SUMMARY OF THE INVENTION

An aspect of the present invention inheres in a semiconductor device, including: (a) a first semiconductor chip having a metal layer on a top surface; (b) a first wiring member arranged to face the metal layer; (c) a sintered-metal layer arranged between the metal layer and the first wiring member, having a first region and a plurality of second regions provided inside the first region, the second regions having lower tensile strength than the first region; and (d) a metallic member arranged inside the sintered-metal layer, wherein the second regions of the sintered-metal layer have lower tensile strength than the metal layer of the first semiconductor chip.

Another aspect of the present invention inheres in a method for manufacturing a semiconductor device, including: (a) joining a first semiconductor chip on a wiring layer arranged on an upper surface of an insulated circuit board; (b) stacking a first sintered-metal layer by drying a metal sintering paste applied to an upper surface of the first semiconductor chip; (c) arranging a first metal plate on the first sintered-metal layer so that the lower surface of the first metal plate is in contact with the first sintered-metal layer, the first metal plate having a plurality of first groove portions on a lower surface and a plurality of second groove portions on an upper surface; (d) stacking a second sintered-metal layer by drying a metal sintering paste applied to the upper surface of the first metal plate; (e) arranging a first wiring member on the second sintered-metal layer; and (0pressurizing and heating the first sintered-metal layer and the second sintered-metal layer, so that the first sintered-metal layer is joined to the lower surface of the first metal plate and the first semiconductor chip so that the first sintered-metal layer fills in the first groove portions, and the second sintered-metal layer is joined to the upper surface of the first metal plate and the first wiring member so that the second sintered-metal layer fills in the second groove portions.

DETAILED DESCRIPTION

Hereinafter, first and second embodiments of the present invention will be described with reference to the drawings. In the descriptions of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate explanation is omitted. However, the drawings are schematic, the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, etc. may be different from the actual one. In addition, parts having different dimensional relations and ratios may also be included between drawings. In addition, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the invention does not specify the material, shape, structure, or arrangement of the elements described below.

In the following descriptions, the terms relating to directions, such as “left and right” and “top and bottom” are merely defined for illustration purposes, and thus, such definitions do not limit the technical idea of the present invention. Therefore, for example, when the paper plane is rotated by 90 degrees, the “left and right” and the “top and bottom” are read in exchange. When the paper plane is rotated by 180 degrees, the “top” is changed to the “bottom”, and the “bottom” is changed to the “top”. Similarly, if the paper plane is rotated by 180 degrees, the inverted terms are defined for the relationship between “front” and “back”.

First Embodiment

A semiconductor device according to the present invention encompasses a first semiconductor chip having a metal layer on a top surface, a first wiring member arranged to face the metal layer, a sintered metal layer arranged between the metal layer and the first wiring member, having a first region and a plurality of second regions which are provided within the first region and have a lower tensile strength than the first region, and a metallic member arranged inside the sintered metal layer. The second regions of the sintered metal layer have lower tensile strength than the metal layer of the first semiconductor chip. As illustrated inFIG.1, the semiconductor device according to a first embodiment of the present invention includes a semiconductor chip (a first semiconductor chip)1, joint portions2,2a, an insulated circuit board8, and a wiring member (a first wiring member)7. The insulated circuit board8has an insulating plate81, conductor layers (wiring layers)82aand82bdelineated on an upper surface of the insulating plate81, and a conductor layer (a heat dissipation layer)83provided on a lower surface of the insulating plate81. The upper surface of the semiconductor chip1is electrically connected to an end of the wiring member7via the joint portion2. The lower surface of the semiconductor chip1is electrically connected to the conductor layer82aof the insulated circuit board8via the joint portion2a. The other end of the wiring member7is electrically connected to the conductor layer82bof the insulated circuit board8via a joint portion6. The conductor layer83of the insulated circuit board8is connected to a heat dissipation base10via a joint portion9.

The power semiconductor element implementing the semiconductor chip1includes a three-terminal element, such as an IGBT or MOSFET, a two-terminal element, such as a free wheel diode (FWD) and a Schottky barrier diode (SBD). For the wiring member7, a lead frame, a metal plate, a metal foil or the like, made of copper (Cu), aluminum (Al) and the like having a plating layer, such as a silver (Ag) layer or a gold (Au) layer, on the surface may be used. The insulated circuit board8is, for example, a direct copper bonding (DCB) substrate in which copper is eutectically bonded to the surface of a ceramic substrate, and an active metal brazing (AMB) substrate in which a metal is disposed on the surface of a ceramic substrate by an AMB method, and the like may be adopted. For a material of the ceramic substrate, such as silicon nitride (Si3N4), aluminum nitride (AlN), alumina (Al2O3) and the like may be adopted. In addition, as will be described later, it is desirable to provide a plating layer made of Ag, Au and the like, on the surface of the conductor layers82a,82b,83of the insulated circuit board8in consideration of joining with Ag nanoparticles or the like.

FIG.2is an enlarged view of the part A inFIG.1, that is, a joining part between the semiconductor chip1and the wiring member7. As illustrated inFIG.2, the semiconductor chip1includes a semiconductor layer1A such as a SiC layer, and an electrode layer (1B,1C), that is a metal layer (1B,1C). The electrode layer (1B,1C) has an electrode metal layer1B made of Al or Al alloy, and an outer plated metal layer1C made of silver (Ag) or gold (Au). The joint portion2includes a sintered metal layer (a first sintered metal layer)4aarranged on the outer plated metal layer1C, a sintered metal layer (a second sintered metal layer)4barranged on the first sintered metal layer4aand under the wiring member7, and a metal plate3having a plurality of through holes5, arranged between the sintered metal layer4aand the sintered metal layer4b. In the through holes5, each portion filled with the sintered metal layer4ais defined as a first groove portion15a, and each portion filled with the sintered metal layer4bis defined as the second groove portion15b. As illustrated inFIG.3, the through holes5having circular shapes are arranged in a matrix on the metal plate3in a plan view. As illustrated inFIG.4, the through holes5has the same diameter on upper and lower surfaces of the metal plate3. The arrangement of the through holes5is not limited to the matrix, and may be a striped arrangement or a random arrangement. Further, each shape of the through holes5is not limited to the circular shape, and may be an elliptical shape, a rectangular shape, a polygonal shape, or the like.

The sintered metal layer4ahas a plurality of regions having different tensile strengths. Also, the sintered metal layer4bhas a plurality of regions having different tensile strengths. The metal plate3, that is the metallic member or the first metal plate, is arranged between regions having the higher tensile strength in the sintered metal layer4aand regions having the higher tensile strength in the sintered metal layer4b.

A sintered metal layer (4a,4b) is implemented by the sintered metal layer4aarranged between the metal material3and the semiconductor chip1and the sintered metal layer4barranged between the metal material3and the wiring member7. The metallic member3(first metal plate) has the first groove portions15aon the lower surface, the second groove portions15bon the upper surface, and a plane portion3eon each of the lower and upper surfaces where the first groove portion15aand the second groove portion15bare not provided.

FIG.5is an enlarged view of the part C inFIG.1, that is, a joining part between the semiconductor chip1and the insulated circuit board8. As illustrated inFIG.5, the semiconductor chip1includes the semiconductor layer1A such as the SiC layer, and an electrode layer (1D,1E), that is a metal layer (1D,1E). The electrode layer (1D,1E) has an electrode metal layer1D made of Al or Al alloy, and an outer plated metal layer1E made of silver (Ag) or gold (Au). The joint portion2aincludes a sintered metal layer4carranged below the outer plated metal layer1E, a sintered metal layer4darranged on the conductor layer82aof the insulating circuit substrate8and below the sintered metal layer4c, and a metal plate3ahaving a plurality of through holes5a, arranged between the sintered metal layers4cand4d. Similarly to the metal plate3illustrated inFIGS.3and4, the through holes5ahaving circular shapes are arranged in a matrix on the metal plate3ain a plan view. Each shape of the through holes5ais not limited to the circular shape, and may be an elliptical shape, a rectangular shape, a polygonal shape, or the like. Further, the arrangement of the through holes5ais not limited to the matrix, and may be a zigzag arrangement, a striped arrangement, or a random arrangement.

Nanometer-scale Ag nanoparticles may be used for a material of the sintered metal layers4a,4b,4c,4d. Alternatively, the material of the sintered metal layers4a,4b,4c,4dmay be a composite material containing a micrometer-scale Ag powder in the Ag nanoparticles. For a material of the metal plate3, a metal, such as Ag or Au, may be desirable in consideration of joining with the sintered metal layers4e,4f. Further, the metal plate3may be a metal plate made of copper (Cu), Al, Al alloy or the like, in which a surface is Ag-plated or Au-plated. It is desirable to use sintered metal for the joint portions6,9illustrated inFIG.1. However, since the joint portions6,9are separated from the semiconductor chip1which is the heat source, a commonly-used joint member such as solder may be used.

The sintered metal has a tensile strength (hereinafter, also simply referred to as a strength), for example, a yield stress represented by 0.2% proof stress (hereinafter, also simply referred to as a yield stress) by three to four times as much as a conventional solder joint material. Further, the yield stress may be by about five times as much as Al or Al alloy which is an electrode material of a semiconductor element. For example, as illustrated inFIG.6, similarly to the conventional semiconductor device, the semiconductor chip1and the wiring member7such as a lead frame may be joined with a sintered metal layer4zmade of Ag nanoparticles. In the semiconductor device joined with the sintered metal layer4zhaving higher strength, the entire wiring member7repeatedly undergoes thermal expansion and contraction in an energization cycle test, so that the sintered metal layer4zas a joint portion, is repeatedly strained. Since the sintered metal layer4zas the joint portion has sufficient strength against the stress repeatedly applied to the joint portion, the joint portion is prone to cracking to easily extend a crack Ca to the electrode metal layer1B made of Al or Al alloy, which has lower strength. Also, possibly a generated crack Cb may extend to the semiconductor layer1A of the semiconductor chip1. Thus, the electrodes of the semiconductor chip1may deteriorate, resulting in an early failure of the semiconductor device.

In the semiconductor device according to the first embodiment, the strengths of the sintered metal layers4a,4bare controlled by using the metal plate3having the through holes5, between the sintered metal layers4aand4b. First, a relationship of the cross-sectional structure of the joint portion with respect to applied pressure to the sintered metal will be described with reference toFIGS.7to12. A nano-Ag sintering paste in which Ag nanoparticles are dispersed in a solvent are printed on a flat underlying layer such as a metal layer by a printing method. After printing, the base layer is dried to remove the solvent. The dried sintered metal layer made of the Ag nanoparticles after drying the solvent has a thickness of about ½ the printed layer of the Ag nanoparticles. Here, a thickness of the dried sintered metal layer after drying the solvent is defined as a “supply-thickness”. Incidentally, a sintered metal sheet or a sintered metal preform, which are made of Ag nanoparticles, may be adopted. In such case, drying procedure for solvent may be omitted. The dried sintered metal layer is pressurized with a pressing tool while being heated at a temperature in a range of 200° C. or higher and 300° C. or lower, for example, 250° C. to be joined to the underlying layer. Each cross-sectional structure of the laminated sintered metal layers changing a pressure in a range of 0.25 MPa to 50 MPa has been observed by a scanning electron microscope (SEM). Here, a thickness of the laminated sintered metal layer after pressurization is defined as a “laminate-thickness”.

FIGS.7to12are scanning electron microscope (SEM) images of cross-sectional structures of the sintered metal layers laminated by changing pressures in a range of 0.25 MPa to 50 MPa. In each of the SEM images illustrated inFIGS.7to12, a bright portion corresponds to sintered metal and a dark portion corresponds to pores. At a low pressure of 1 MPa or less, as illustrated inFIGS.7and8, dimensions of the voids are large and a sintering density of the sintered metal is low. When the pressure is increased in a range of 5 MPa to 7.5 MPa, dimensions of the voids decreases sharply as illustrated inFIGS.9and10. Further, when the pressure is increased in range of 30 MPa to 50 MPa, as illustrated inFIGS.11and12, dimensions of the voids becomes extremely small and the sintered metal layer is densified.

FIGS.13and14illustrate relationships of the tensile strength and the sintering density to the pressure applied to the sintered metal layer when changing the pressure in a range of 0.25 MPa to 50 MPa. As illustrated inFIG.13, the yield stress represented by 0.2% proof stress and the maximum stress increase sharply as the pressures increase from about 0 to about 10 MPa, and gradually increase as the pressures increase from about 10 MPa to about 50 MPa. As illustrated inFIG.14, the sintering density also increases sharply as the pressure increases from about 0 to about 10 MPa, and gradually increases as the pressure increase from about 10 MPa to about 50 MPa. As observed in the SEM images ofFIGS.7to12, by increasing the pressurization, the sintered metal powders of the sintered metal layer can be densely packed with each other to increase the sintering density and to increase the tensile strength of the sintered metal layer.

FIG.15illustrates a relationship between the sintering density of the sintered metal layer and the tensile strength. As illustrated inFIG.15, the yield stress of the sintered metal layer depends on the sintering density. Here, percent of variation in the laminate-thickness in a thickness direction with respect to the supply-thickness of the sintered metal layer is defined as a “compression rate”. Specifically, considering that the compression of the sintered metal layer by pressurization occurs substantially in a pressurizing direction, that is, in the thickness direction, the “compression rate” can be obtained from variation in the sintering density.FIG.16illustrates a relationship between the compression rate and the sintering density. As illustrated inFIG.16, when the compression rate is around 0%, the sintered metal layer contains the voids of about 60%. Also, when the compression rate is around 50%, the voids may be almost eliminated in the sintered metal layer.FIG.17illustrates a relationship between the compression rate and the tensile strength. As the compression rate of the sintered metal layer increases, the tensile strength increases. Further, considering that the compression of the sintered metal layer occurs substantially one-dimensionally in the pressurizing direction, the laminate-thickness of the sintered metal layer can be obtained by using the compression rate or the sintering density.FIG.18illustrates a relationship between the laminate-thickness and the tensile strength. As illustrated inFIG.18, the tensile strength decreases as the laminate-thickness of the sintered metal layer increases. As described above, a strength corresponding to the yield stress of the sintered metal layer can be controlled by a pressure applied by a press machine. Alternatively, a strength of the yield stress of the sintered metal layer can also be detected by the sintering density, the compression rate and the laminate-thickckness of the sintered metal layer.

In the first embodiment, the stress generated during the energization of the semiconductor device is dispersed in the joint portion2, by controlling the sintering densities of the sintered metal layers4a,4bso as to have the same or lower strength than the electrode metal layer1B of the semiconductor chip1. In order to control the yield stress of the sintered metal layers4a,4bof the joint portion2, as illustrated inFIGS.1to4, the metal plate3having the through holes5is arranged between the sintered metal layer4aand the sintered metal layer4b. Table inFIG.19illustrates results of tensile strength tests on an Al metal having a purity of 99.99% (4N) and an Al alloy containing 1.0% Si (Al-1.0% Si alloy) used for the electrode metal layer1B, each using a test piece with a diameter of about 6 mm and a gauge length of about 30 mm. As illustrated inFIG.19, the yield stress is about 27 MPa for the Al metal and about 35 MPa for the Al-1.0% Si alloy. Therefore, in order to prevent the occurrence of cracks in the electrode metal layer1B, the strength of the sintered metal layers4a,4bmay be controlled to a strength equal to or less than the tensile strength of the Al metal or the Al alloy, for example, in a range of about 20 MPa to about 40 MPa. As illustrated inFIG.15, in order to control the strengths of the sintered metal layers4a,4bin the range of about 20 MPa to about 40 MPa, the sintering densities may be in a range of about 72% or more and about 78% or less. Alternatively, as illustrated inFIG.17, in order to control the strength of the sintered metal layers4a,4bin the range of about 20 MPa to about 40 MPa, the compression rates may be in a range of about 10% or more and about 20% or less.

Further, a thickness Tm of the metal plate3is preferably less than 50% of the supply-thickness or less than 63% of the laminate-thickness. When the thickness Tm of the metal plate3is 50% or more of the supply-thickness, each compression rate of the sintered metal layers4a,4bin the respective upper and lower regions of the metal plate3may increase, and thus, the pressurization to the regions of the through holes5may be insufficient. In such case, since contact areas between the sintered metal layer4aand the semiconductor chip1, and between the sintered metal layer4band the insulated circuit board8may be reduced, the joint strength may be decreased and the thermal resistance may be increased. Further, in case any metal plate is not used, a conventional method for heating and pressurizing a sintered metal layer has to be adopted. For example, when a plurality of semiconductor chips having different thicknesses are used, or when a semiconductor chip having warpage or inclination is used, it is difficult to control the sintering density because the pressurization may be excessive or insufficient by the position. Therefore, the thickness Tm of the metal plate3is required to some extent.

In the first embodiment, in joining the semiconductor chip1and the wiring member7, the strengths of the sintered metal layers4a,4bin the regions of the through holes5illustrated inFIG.2are controlled in the range of about 20 MPa to about 40 MPa, for example, about 35 MPa. In such case, the sintering density corresponds to about 76% and the compression rate corresponds to about 18%. For example, when each supply-thickness of the sintered metal layers4a,4bin the regions of the through holes5is about 100 μm, the laminate-thickness Ts illustrated inFIG.2is about 82 μm, and thus, the amount of deformation due to compression is about 18 μm. In such case, the sintering densities of the sintered metal layers4a,4bin the respective upper and lower regions of the metal plate3are greater than about 76% and less than about 90%. The supply-thickness of the sintered metal layers4a,4bis preferably in a range of about 50 μm or more and about 1000 μm or less, and the laminate-thickness is in a range of about 41 μm or more and about 820 μm or less.

In the semiconductor device according to the first embodiment, as illustrated inFIG.2, the metal plate3having the through holes5is arranged between the sintered metal layer4aand the sintered metal layer4bto disperce the stress generated during energization in the joint portion2. The sintered metal layers4a,4bin the upper and lower regions of the metal plate3have higher strengths than in the regions of the through holes5. The sintered metal layers4a,4bin the regions of the through holes5in which the strengths are lower, are localized surrounded by the sintered metal layers4a,4bin the upper and lower regions of the metal plate3in which the strengths are higher. Therefore, even if the cracks occur in the sintered metal layers4a,4bin the regions of the through holes5, it is possible to prevent from extending to the entire sintered metal layers4a,4bincluding the upper and lower regions of the metal plate3. As a result, deterioration of the semiconductor chip1can be prevented, and the reliability of the semiconductor device can be improved.

Further, a thickness Tb of the sintered metal layer4bbetween the metal plate3and the wiring member7is desirably thicker than a thickness Ta of the sintered metal layer4abetween the metal plate3and the semiconductor chip1. When the sintered metal layer4bis thicker than the sintered metal layer4a, the strength of the sintered metal layer4bmay be smaller than the sintered metal layer4a. Thus, the cracks may occur in the sintered metal layer4bbetween the wiring member7and the metal plate3, and it is possible to prevent the cracks from extending toward the semiconductor chip1.

In a planar pattern, an occupied area of the through holes5defined as a sum of surface areas of entire openings of the through holes5is desirably 25% or more and 75% or less with respect to a total surface area defined as a sum of a surface area of the metal plate3and the surface areas of the entire openings of the through holes5. When the occupied area of the through holes5is less than 25%, the ratio of the portion having higher strength in the sintered metal layers4a,4bincreases, and possibility of the crack-occurrence in the electrode metal layers1B,1D increases. When the occupied area of the through holes5exceeds 75%, the ratio of the portion having lower strength in the sintered metal layers4a,4bincreases, and possibility of crack-occurrence in the sintered metal layers4a,4bincreases. Further, as illustrated inFIG.20, in order to lower the strength of the sintered metal layer4bon the wiring member7as compared to the strength of the sintered metal layer4aon the semiconductor chip1, the occupied area of openings may be adjusted by using a metal plate3bhaving a through hole5b. In the through hole5b, an opening size w1of the first groove portion55aon the semiconductor chip1is smaller than an opening size w2of the second groove portion55bon the wiring member7. Therefore, the strength of the sintered metal layer4bon the wiring member7may be smaller than that of the sintered metal layer4aon the semiconductor chip1. In addition, as illustrated inFIG.21, a metal plate3chaving a through hole5cmay be used. The through hole5chas an inclined side wall in which an opening size w2on the wiring member7is larger than an opening size w1on the semiconductor chip1.

Similarly, in joining the semiconductor chip1and the wiring layer82aof the insulated circuit board8, the strengths of the sintered metal layers4c,4din the regions of the through holes5aillustrated inFIG.5are controlled in the range of 20 MPa or more and 40 MPa or less, for example, about 35 MPa. For example, assuming that each supply-thickness of the sintered metal layers4c,4dis about 100 μm, the laminate-thickness Ts illustrated inFIG.5is about 82 μm, that is, the amount of deformation due to compression is about 18 μm. In such case, the sintering density corresponds to about 76% and the compression rate corresponds to about 18%. Further, the thickness Tm of the metal plate3ais preferably less than 50% of the supply-thickness.

Further, as illustrated inFIG.5, a thickness Td of the sintered metal layer4dbetween the metal plate3aand the wiring layer82aof the insulated circuit board8is desirably thicker than a thickness Tc of the sintered metal layer4cbetween the metal plate3aand the semiconductor chip1. When the sintered metal layer4dis thicker than the sintered metal layer4c, the strength of the sintered metal layer4dmay be smaller than the strength of the sintered metal layer4c. Thus, the cracks occur in the sintered metal layer4dbetween the wiring layer82aand the metal plate3a, and it is possible to prevent the cracks from extending toward the semiconductor chip1. Further, in order to lower the strength of the sintered metal layer4don the insulated circuit board8in comparison to the strength of the sintered metal layer4con the semiconductor chip1, a metal plate having different opening sizes on respective sides of the semiconductor chip1and the insulated circuit board8as illustrated inFIGS.20and21, may be used.

Next, a manufacturing method of the semiconductor device according to the first embodiment will be described with reference toFIGS.1and2. First, a metal sintering paste in which Ag nanoparticles are dispersed in a solvent is applied to the upper surface of the electrode layers (1B,1C) of the semiconductor chip1joined to the wiring layer82aof the insulated circuit board8by a printing method, a dispensing method or the like. The applied metal sintering paste is dried in a temperature range of about 100° C. or higher and about 150° C. or lower in which sintering of the Ag nanoparticles does not occur, to remove the solvent, and thus, the sintered metal layer4ais laminated. The metal plate3having a plurality of through holes5is arranged on the sintered metal layer4a. The metal sintering paste in which the Ag nanoparticles are dispersed in the solvent is applied onto the metal plate3by a printing method, a dispensing method, or the like. The applied metal sintering paste is dried in a temperature range of about 100° C. or higher and about 150° C. or lower to remove the solvent, and thus, the sintered metal layer4bis laminated. In such way, the joint portion2having the sintered metal layer4a, the metal plate3, and the sintered metal layer4bis formed on the upper surface of the semiconductor chip1. The sintered metal layers4a,4bare physically connected to each other in the through holes5.

The wiring member7such as a lead frame is arranged on the joint portion2, and the sintered metal layers4a,4bare pressurized while heating in a range of about 200° C. or higher and about 300° C. or lower, for example, at about 250° C. from above the wiring member7by a pressure molding apparatus such as a pressing machine. Pressurization is executed at a pressure in which the compression rate of the sintered metal layers4a,4bis in a range of about 10% or more and about 20% or less in the regions of the through holes5. By the pressurization, the semiconductor chip1and the sintered metal layer4a, and the sintered metal layer4band the wiring member7are joined, respectively. In the through holes5, the sintered metal layers4a,4bare metallurgically connected, and the sintering densities of the sintered metal layers4a,4bare in a range of about 72% or more and about 78% or less. On the other hand, in the regions on the metal plate3, the sintering densities of the sintered metal layers4a,4bare higher than the sintering densities of the sintered metal layers4a,4bin the regions of the through holes5. Thus, the semiconductor device in which the semiconductor chip1is joined to the insulated circuit board8and the wiring member7by the sintered metal layers4a,4bis manufactured.

In the above description, the metal sintering paste is used for laminating the sintered metal layers4aand4b, but a sintered metal sheet or a sintered metal preform, which are made of Ag nanoparticles, may be adopted. Further, for the joint portion2, a multilayer plate (a cladded material) in which sintered metal layers are previously arranged on front and back surfaces of a metal plate having through holes may be used.

As mentioned above, although the case of joining one semiconductor chip1has been described, a plurality of semiconductor chips may be adopted. When each thickness of the semiconductor chips is different, the difference in thickness may be adjusted by a buffer member such as heat-resistant rubber arranged between the semiconductor device and a press mold of the pressure molding apparatus. For example, as illustrated inFIG.22, as the semiconductor device, a semiconductor chip (a first semiconductor chip)1such as an IGBT or MOSFET and a semiconductor chip (a second semiconductor chip)21such as FWD or SBD may be used. The semiconductor chip1is joined to the wiring layer82avia the joint portion2a. An end of the wiring member7is joined to the semiconductor chip1via the joint portion2. The other end of the wiring member7is joined to the wiring layer82bvia the joint portion6. Similarly, the semiconductor chip21is joined to the wiring layer82avia the joint portion22a. An end of the wiring member27is joined to the semiconductor chip21via the joining portion22. The other end of the wiring member27is joined to the wiring layer82cvia the joint portion26. Each of the joint portions22,22ahave a structure in which a metal plate having through holes is sandwiched between sintered metal layers, similarly to the joint portions2,2aillustrated inFIGS.2and5. For example, when the semiconductor chip21is thicker than the semiconductor chip1, a buffer member32is arranged on a pressurizing face of a press mold31such that a portion of the buffer member32in contact with the wiring member27to the semiconductor chip21is thinned less than another portion of the buffer member32in contact with the wiring member7to the semiconductor chip1. Thus, it is possible to simultaneously pressurize to collectively join the plural semiconductor chips to the wiring members by using the press mold31of the pressure molding apparatus via the buffer member32.

Moreover, it is also possible to adjust the difference in the thicknesses of the semiconductor chips with the metal plate used for the joint. For example, as illustrated inFIG.23, the joint portion2includes the sintered metal layer4a, the sintered metal layer4b, and the metal plate3. The metal plate3is arranged between the sintered metal layer4aand the sintered metal layer4b, and has the through holes (not illustrated). The joint portion22includes a sintered metal layer24a, a sintered metal layer24b, and a metal plate23. The metal plate23is arranged between the sintered metal layer24aand the sintered metal layer24b, and has a plurality of through holes (not illustrated). A thickness Tm2of the metal plate23is made thinner than a thickness Tm1of the metal plate3, so that the upper surface of the wiring member7of the semiconductor chip1and the upper surface of the wiring member27of the semiconductor chip21are at the same level. As a result, as illustrated inFIG.23, the buffer member32arranged on the pressurizing face of the press mold31can be in contact with the wiring members7,27by a flat surface, and it is possible to simultaneously pressurize to collectively join the semiconductor chips1,21to the wiring members7,27, respectively. In addition, the level of the upper surfaces of the wiring members7,27may be adjusted by the thickness of the metal plate used for each of the joint portion2aof the semiconductor chip1and the joint portion22aof the semiconductor chip21. Alternatively, the level of the upper surface of the wiring members7,27may be adjusted by a sum of the thicknesses of the metal plates used in the joints2,2aand a sum of the thicknesses of the metal plates used in the joints22,22a.

Second Embodiment

As illustrated inFIG.24, a semiconductor device according to a second embodiment includes the semiconductor chip1, a joint portion2cto join the semiconductor chip1and the insulated circuit board8, and a joint portion2bto join the semiconductor chip1and the wiring member7.FIG.25is an enlarged view of Part D inFIG.24. As illustrated inFIG.25, the joint portion2bis arranged between the electrode layer (1B,1C) and the wiring member7. The joint portion2bincludes a sintered metal layer4earranged on the outer plated metal layer1C, a sintered metal layer4farranged below the wiring member7, and a metal plate3darranged between the sintered metal layers4e,4f. The metal plate3dhas a plurality of first groove portions15aand a plurality of second groove portions15bseparately on a lower surface and an upper surface, respectively. The first groove portions15aare provided on one side of the metal plate3dfacing the semiconductor chip1. The second groove portions15bare provided on another side of the metal plate3dfacing the wiring member7. The semiconductor device according to the second embodiment differs from the first embodiment in including the metal plate3dhaving the first groove portions15aand the second groove portions15bseparately on the lower surface and the upper surface, respectively. The other configurations are the same as those of the semiconductor device according to the first embodiment, and thus, redundant descriptions will be omitted.

As illustrated inFIG.26, in the metal plate3d, the first groove portions15ahaving a circular shape provided on the lower surface and the second groove portions15bhaving a circular shape provided on the upper surface are arranged in a matrix in a plan view. Each shape of the first and second groove portions15a,15bis not limited to a circular shape, and may be an elliptical shape, a rectangular shape, a polygonal shape, or the like. Further, each arrangement of the first and second groove portions15a,15bis not limited to the matrix, and may be a striped arrangement or a random arrangement. As illustrated inFIG.27, the first groove portions15aare provided on one side of the metal plate3dfacing the semiconductor chip1and each has a depth Da. The second groove portions15bare provided on another side of the metal plate3dfacing the wiring member7and each has a depth Db. The depth Da and the depth Db may be the same or different from each other. For a material of the metal plate3d, a metal, such as Ag or Au, may be desirable in consideration of joining with the sintered metal layers4e,4fcontaining the Ag particles, the Ag powder and the like. Further, the metal plate3dmay be a metal plate made of Cu, Al, Al alloy or the like, in which a surface is Ag-plated or Au-plated.

In the semiconductor device according to the second embodiment, the strengths of the sintered metal layers4e,4fare controlled by using the metal plates3dhaving the first and second groove portions15aand15bbetween the sintered metal layers4eand4f. The sintering densities of the sintered metal layers4e,4fare controlled so that the strengths of the sintered metal layers4e,4fare equal to or less than that of the electrode metal layer1B of the semiconductor chip1, and the stress generated when the semiconductor device is energized may be dispersed in the joint portion2b. As illustrated inFIG.19, the yield stress is about 27 MPa for the Al metal and about 35 MPa for the Al-1.0% Si alloy. Therefore, the strengths of the sintered metal layers4e,4fare controlled in a range of about 20 MPa or more and about 40 MPa or less. As illustrated inFIG.15, in order to control the strengths of the sintered metal layers4eand4fin the range of about 20 MPa or more and about 40 MPa or less, the sintering densities may be in a range of about 72% or more and about 78% or less. Alternatively, as illustrated inFIG.17, in order to control the strengths of the sintered metal layers4e,4fin the range of about 20 MPa or more and about 40 MPa or less, the compression rates may be in a range of about 10% or more and about 20% or less.

A thickness Tm of the metal plate3dis desirably less than 50% of the supply-thickness. When the thickness Tm of the metal plate3dis 50% or more of the supply-thickness, each compression rate of the sintered metal layers4e,4fin the regions of the metal plate3dother than the first and second groove portions15a,15bmay increase, and thus, the pressurization to the regions of the first and second groove portions15a,15bmay be insufficient. In such case, the contact area between the semiconductor chip1and the insulated circuit board8may be reduced, the joint strength may be decreased and the thermal resistance may be increased. Further, in case any metal plate is not used, the conventional method for heating and pressurizing a sintered metal layer have to be adopted. For example, when a plurality of semiconductor chips having different thicknesses are used, or when a semiconductor chip having warpage or inclination is used, it is difficult to control the sintering density because the pressurization may be excessive or insufficient by the position. Therefore, the thickness Tm of the metal plate3dis required to some extent. Moreover, the depths Da, Db of the first and second groove portions15a,15bare preferably larger than 0 and smaller than the thickness Tm of the metal plate3d.

In the second embodiment, in joining between the semiconductor chip1and the wiring member7, the strengths of the sintered metal layers4e,4fin the respective regions of the first and second groove portions15a,15billustrated inFIG.25are controlled in the range of 20 MPa or more and 40 MPa or less, for example, about 35 MPa. In such case, the sintering density corresponds to about 76% and the compression rate corresponds to about 18%. For example, when each supply-thickness of the sintered metal layers4e,4fis about 100 μm, a laminate-thickness Tsa of the sintered metal layer4eand a laminate-thickness Tsb of the sintered metal layer4fillustrated inFIG.25are about 82 μm, respectively, that is, the amount of deformation due to compression is about 18 μm. When the respective depths Da, Db of the first and second groove portions15a,15bare more than 0 and less than the thickness Tm of the metal plate3d, the sintering densities of the sintered metal layer4e,4fin the regions of the metal plate3dother than the first and second groove portions15a,15bare greater than about 76% and less than about 90%.

In the semiconductor device according to the second embodiment, as illustrated inFIG.25, the metal plate3dhaving the first and second groove portions15a,15bis provided between the sintered metal layer4eand the sintered metal layer4f. The stress generated during energization is dispersed in the joint portion2b. The sintered metal layers4e,4fin the regions of the metal plate3dother than the first and second groove portions15a,15bhave higher strength than the sintered metal layers4e,4fin the regions of the first and second groove portions15a,15b. In the sintered metal layers4e,4f, the regions of the first and second groove portions15a,15b, in which the strengths are lower, are localized surrounded by the regions of the metal plate3dother than the first and second groove portions15a,15b, in which the strengths are higher. Therefore, even if the cracks occur in the sintered metal layers4e,4fin the regions of the first and second groove portions15aand15b, it is possible to prevent from extending to the entire sintered metal layers4e,4f.

The depth Db of the second groove portion15bof the metal plate3dis desirably deeper than the depth Da of the first groove portion15aof the metal plate3d. When the second groove portion15bis deeper than the first groove portion15a, the strength of the sintered metal layer4fmay be smaller than that of the sintered metal layer4e, and the cracks may occur in the sintered metal layer4fbetween the wiring member7and the metal plate3dto prevent from extending toward the semiconductor chip1. As a result, deterioration of the semiconductor chip1can be prevented, and the reliability of the semiconductor device can be improved.

In a planar pattern, each occupied area of the first groove portion15aand the second groove portion15bis desirably 25% or more and 75% or less with respect to the total area of the metal plate3dincluding the upper surface of the metal plate3dand the openings of the first groove portions15aor the lower surface of the metal plate3dand the openings of the second groove portions15b. Further, the thickness Tb of the sintered metal layer4fbetween the upper surface of the metal plate3dand the wiring member7is desirably thicker than the thickness Ta of the sintered metal layer4ebetween the lower surface of the metal plate3dand the semiconductor chip1. When the sintered metal layer4fis thicker than the sintered metal layer4e, the strength of the sintered metal layer4fmay be smaller than that of the sintered metal layer4e, and the cracks may occur in the sintered metal layer4fbetween the wiring member7and the metal plate3d, and it is possible to prevent the cracks from extending toward the semiconductor chip1.

Further, in order to lower the strength of the sintered metal layer4fon the wiring member7as compared with the sintered metal layer4eon the semiconductor chip1, as illustrated inFIG.28, opening areas of the first and second groove portions15a,15bin the metal plate3dmay be adjusted. An opening size Wa of the first groove portion15afacing the semiconductor chip1is smaller than an opening size Wb of the second groove portion15bfacing the wiring member7. Therefore, the strength of the sintered metal layer4fon the wiring member7may be smaller than that of the sintered metal layer4eon the semiconductor chip1side.

Similarly, in joining the semiconductor chip1and the wiring layer82aof the insulated circuit board8as illustrated inFIG.24, the joint portion2chas a structure in which a metal plate having the first and second groove portions15a,15billustrated inFIG.25is arranged between sintered metal layers. The strengths of the sintered metal layers in the respective regions of the first and second groove portions15a,15bare controlled in the range of 20 MPa or more and 40 MPa or less, for example, about 35 MPa. For example, when each supply-thickness of the sintered metal layers is about 100 μm, the laminate-thicknesses Tsa and Tsb illustrated inFIG.25are about 82 μm, respectively, that is, the amount of deformation due to compression is about 18 μm. In such case, the sintering density corresponds to about 76% and the compression rate corresponds to about 18%. Further, the thickness Tm of the metal plate is preferably less than 50% of the supply-thickness.

Further, the thickness of the sintered metal layer between the metal plate in the joint portion2cand the wiring layer82aof the insulated circuit board8is desirably thicker as compared with the thickness of the other sintered metal layer between the metal plate in the joint portion2cand the semiconductor chip1, as illustrated inFIG.24. When the sintered metal layer on the insulated circuit board8side is thicker, the strength of the sintered metal layer on the insulated circuit board8may be smaller than the other sintered metal layer on the semiconductor chip1, Thus, the cracks may occur in the sintered metal layer in the joint portion2con the wiring layer82a, and it is possible to prevent the cracks from extending toward the semiconductor chip1. In addition, in the first embodiment and the second embodiment, the metal plate (metallic member)3,3dmay be made of any one of metal particles, metallic fibers, and metallic nets.

Other Embodiments

While the present invention has been described above by reference to the embodiments and modified examples, it should be understood that the present invention is not intended to be limited to the descriptions of the Specification and the drawings implementing part of this disclosure. Various alternative embodiments, examples, and technical applications will be apparent to those skilled in the art according to the spirit and scope of the disclosure of the embodiments. It should be noted that the present invention includes various embodiments, which are not disclosed herein, including elements optionally modified as alternatives to those illustrated in the above embodiments and modified examples. Therefore, the scope of the present invention is defined only by the subject matter according to the claims reasonably derived from the description heretofore.