FLOATING POINT PRE-ALIGNMENT STRUCTURE FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

BACKGROUND

Technical Field

The present disclosure relates to a floating point pre-alignment structure and a computing method thereof. More particularly, the present disclosure relates to a floating point pre-alignment structure for computing-in-memory applications and a computing method thereof.

Description of Related Art

Computing-In-Memory (CIM) is a promising solution that can reduce the energy consumption of artificial intelligence (AI) chip multiplication and accumulation (MAC) operations. In order to increase the bandwidth and reduce the power consumption of each operation, CIM would turn on multiple word lines (WL) in a memory array to compute at the same time. The computing results will accumulate on bit lines (BL) and read out by readout circuit or digital circuit that both are the current development directions. However, most conventional CIM structures only support integer (INT) operation. For different applications, such as cloud deep learning (DL) which requires higher precision for neural network (NN) inference and training, supporting floating point (FP) CIM is necessary. Comparing with INT, FP has more complicated operation. Realizing CIM FP operation and operate FP efficiently are the challenges for wide application higher precision in CIM.

When operating FP, there are exponent (EXP) part and mantissa (MAN) part. When operating MAC, the conventional CIM structures need to align to same EXP value so as to accumulate each other. The conventional CIM structures cannot support directly floating-point accumulation. In addition, the conventional CIM MAC operation is restricted by the structure, thus causing CIM cannot directly accumulate FP and reducing the application of CIM. When using conventional digital circuit to perform MAC operation of FP, it will cause more power consumption, area and access time. Accordingly, a FP pre-alignment structure for CIM applications and a computing method thereof having the features of supporting floating point, reducing power consumption and enhancing FP CIM performance are commercially desirable.

SUMMARY

According to one aspect of the present disclosure, a floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents. The time domain exponent computing block includes a time domain exponent computing array, a winner-take-all circuit and a dynamic logic block. The time domain exponent computing array is configured to delay a plurality of exponent input signals by a plurality of delay time periods to generate a plurality of exponent delay output signals. Each of the delay time periods is determined by adding one of the original input exponents and one of the original weight exponents. The winner-take-all circuit is connected to the time domain exponent computing array and configured to find out one of the exponent delay output signals as a maximum exponent adding signal. The one of the exponent delay output signals is corresponding to a minimum one of the delay time periods. The dynamic logic block is connected to the winner-take-all circuit and is configured to compare the maximum exponent adding signal with the exponent delay output signals to generate a plurality of flags. The input mantissa pre-align block is connected to the time domain exponent computing block. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas.

According to another aspect of the present disclosure, a computing method of a floating point pre-alignment structure for computing-in-memory applications includes performing a voltage level applying step and a computing step. The voltage level applying step includes applying a plurality of voltage levels to a plurality of exponent input signals, a plurality of original input exponents, a plurality of original weight exponents and a plurality of original input mantissas. The computing step is performed to configure a time domain exponent computing block to compute the original input exponents and the original weight exponents. The computing step includes performing a first computing step, a second computing step, a third computing step and a fourth computing step. The first computing step includes configuring a time domain exponent computing array to delay the exponent input signals by a plurality of delay time periods to generate a plurality of exponent delay output signals, and each of the delay time periods is determined by adding one of the original input exponents and one of the original weight exponents. The second computing step includes configuring a winner-take-all circuit to find out one of the exponent delay output signals as a maximum exponent adding signal, and the one of the exponent delay output signals is corresponding to a minimum one of the delay time periods. The third computing step includes configuring a dynamic logic block to compare the maximum exponent adding signal with the exponent delay output signals to generate a plurality of flags. The fourth computing step includes configuring an input mantissa pre-align block to receive the original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas.

According to further another aspect of the present disclosure, a floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is connected to the time domain exponent computing block. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described with reference to the drawings. For clarity, some practical details will be described below. However, it should be noted that the present disclosure should not be limited by the practical details, that is, in some embodiments, the practical details are unnecessary. In addition, for simplifying the drawings, some conventional structures and elements will be simply illustrated, and repeated elements may be represented by the same reference numerals.

It will be understood that when an element (or device) is referred to as be “connected to” another element, it can be directly connected to the other element, or it can be indirectly connected to the other element, that is, intervening elements may be present. In contrast, when an element is referred to as be “directly connected to” another element, there are no intervening elements present. In addition, the terms first, second, third, etc. are used herein to describe various elements or components, and these elements or components should not be limited by these terms. Consequently, a first element or component discussed below could be termed a second element or component.

Before describing any embodiments in detail, some terms used in the following are described. A voltage level of “1” represents that the voltage is equal to a power supply voltage VDD. The voltage level of “0” represents that the voltage is equal to a ground voltage GND. A PMOS transistor and an NMOS transistor represent a P-type MOS transistor and an N-type MOS transistor, respectively. Each transistor has a source, a drain and a gate.

Reference is made toFIG.1.FIG.1shows a schematic view of a floating point pre-alignment structure100for computing-in-memory (CIM) applications according to a first embodiment of the present disclosure. The floating point pre-alignment structure100for CIM applications includes a time domain exponent computing block TD-ECB and an input mantissa pre-align block IM-PAB. The time domain exponent computing block TD-ECB is configured to compute a plurality of original input exponents IN0EXP[7:0]-IN127EXP[7:0] and a plurality of original weight exponents W0EXP[7:0]-W127EXP[7:0] to generate a plurality of flags FLAG0-FLAG127. Each of the flags FLAG0-FLAG127is determined by adding one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0]. The input mantissa pre-align block IM-PAB is connected to the time domain exponent computing block TD-ECB. The input mantissa pre-align block IM-PAB is configured to receive a plurality of original input mantissas IN0MAN[7:0]-IN127MAN[7:0] and shift the original input mantissas IN0MAN[7:0]-IN127MAN[7:0] according to the flags FLAG0-FLAG127to generate a plurality of weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0], and sparsity of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] is greater than sparsity of the original input mantissas IN0MAN[7:0]-IN127MAN[7:0]. Each of the flags FLAG0-FLAG127has a negative correlation with a sum of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0]. The sparsity has a positive correlation with the number of “0”.

Therefore, the floating point pre-alignment structure100for CIM applications of the present disclosure can utilize the time domain exponent computing block TD-ECB and the input mantissa pre-align block IM-PAB to shift the original input mantissas IN0MAN[7:0]-IN127MAN[7:0] according to the exponent part of the input and the exponent part of the weight and then perform the multiplication and accumulation (MAC) operation of the mantissa part, thereby realizing the concept of input mantissa pre-alignment and improve the problem of conventional CIM operating floating point. In addition, the floating point pre-alignment structure100for CIM applications of the present disclosure does not lose accuracy and increases the sparsity of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] (i.e., increase input sparsity), thereby reducing power consumption and enhancing floating point CIM performance.

Reference is made toFIGS.1,2,3,4,5and6.FIG.2shows a schematic view of a floating point pre-alignment structure100afor CIM applications according to a second embodiment of the present disclosure.FIG.3shows a schematic view of a serial delay computing circuit220(Serial DCCs) of the floating point pre-alignment structure100afor CIM applications ofFIG.2.FIG.4shows a schematic view of a winner-take-all circuit400of the floating point pre-alignment structure100afor CIM applications ofFIG.2.FIG.5shows a schematic view of an input mantissa pre-align block IM-PAB of the floating point pre-alignment structure100afor CIM applications ofFIG.2.FIG.6shows a timing diagram associated with a plurality of exponent input signals RE_IN0-RE_IN127, a plurality of exponent delay output signals RE_OUT0-RE_OUT127and a maximum exponent adding signal RE_MAX ofFIG.2. The floating point pre-alignment structure100afor CIM applications includes a time domain exponent computing block TD-ECB and the input mantissa pre-align block IM-PAB. The time domain exponent computing block TD-ECB is configured to compute the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the original weight exponents W0EXP[7:0]-W127EXP[7:0]. The time domain exponent computing block TD-ECB includes a time domain exponent computing array TD-ECA, a word line input driver unit300, a winner-take-all circuit400and a dynamic logic block500.

The time domain exponent computing array TD-ECA is configured to delay a plurality of exponent input signals RE_IN0-RE_IN127by a plurality of delay time periods to generate a plurality of exponent delay output signals RE_OUT0-RE_OUT127. Each of the delay time periods is determined by adding one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0]. In detail, the exponent input signals RE_IN0-RE_IN127are rising edge input signals and are the same with each other. The time domain exponent computing array TD-ECA includes a plurality of exponent computing modules200(e.g., EXP compute Block #0-EXP compute Block #127), and each of the exponent computing modules200includes a memory array210and a serial delay computing circuit (Serial DCCs)220.

The memory array210includes a plurality of memory cells. The memory cells store the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0]. The memory cells may be formed in an 8×16 array, but the present disclosure is not limited thereto. In one embodiment, each of the memory cells includes a six-transistor static random access memory (6T SRAM) cell.

The serial delay computing circuit220is connected to the memory array210. The serial delay computing circuit220is configured to receive one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0], and delay each of the exponent input signals RE_IN0-RE_IN127by each of the delay time periods to generate each of the exponent delay output signals RE_OUT0-RE_OUT127. In detail, each of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] may be represented by bits IN[7], IN[6], IN[5], IN[4], IN[3], IN[2], IN[1], IN[0]. Each of the original weight exponents W0EXP[7:0]-W127EXP[7:0] may be represented by bits W[7], W[6], W[5], W[4], W[3], W[2], W[1], W[0]. InFIG.3, the serial delay computing circuit220includes a plurality of time delay circuits serially connected to each other, and the time delay circuits include two first time delay circuits221,222, two second time delay circuits223,224, two third time delay circuits225,226and two fourth time delay circuits227,228.

The two first time delay circuits221,222receive the bits IN[7], W[7], respectively. One (221) of the two first time delay circuits221,222is configured to determine whether to delay eight unit time periods (+8t) according to a first bit (IN[7]) of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0], and another (222) of the two first time delay circuits221,222is connected to the one (221) of the two first time delay circuits221,222and configured to determine whether to delay the eight unit time periods (+8t) according to a first bit (W[7]) of the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0]. For example, in response to determining that the first bit (IN[7]) is equal to one, the first time delay circuit221determines to bypass and not to delay. In response to determining that the first bit (IN[7]) is equal to zero, the first time delay circuit221determines to delay the exponent input signal RE_IN (e.g., one of the exponent input signals RE_IN0-RE_IN127) by the eight unit time periods (+8t).

The two second time delay circuits223,224receive the bits IN[6], W[6], respectively. One (223) of the two second time delay circuits223,224is connected to the another (222) of the two first time delay circuits221,222and configured to determine whether to delay four unit time periods (+4t) according to a second bit (IN[6]) of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0], and another (224) of the two second time delay circuits223,224is connected to the one (223) of the two second time delay circuits223,224and configured to determine whether to delay the four unit time periods (+4t) according to a second bit (W[6]) of the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0].

The third time delay circuits225,226receive the bits IN[5], W[5], respectively. One (225) of the two third time delay circuits225,226is connected to the another (224) of the two second time delay circuits223,224and configured to determine whether to delay two unit time periods (+2t) according to a third bit (IN[5]) of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0], and another (226) of the two third time delay circuits225,226is connected to the one (225) of the two third time delay circuits225,226and configured to determine whether to delay the two unit time periods (+2t) according to a third bit (W[5]) of the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0].

The fourth time delay circuits227,228receive the bits IN[4], W[4], respectively. One (227) of the two fourth time delay circuits227,228is connected to the another (226) of the two third time delay circuits225,226and configured to determine whether to delay one unit time period (+1t) according to a fourth bit (IN[4]) of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0], and another (228) of the two fourth time delay circuits227,228is connected to the one (227) of the two fourth time delay circuits227,228and configured to determine whether to delay the one unit time period (+1t) according to a fourth bit (W[4]) of the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0].

Each of the delay time periods is equal to a sum of total unit time periods delayed by all of the time delay circuits of the serial delay computing circuit220. Each of the delay time periods has a negative correlation with a sum of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0]. InFIG.3, each of the delay time periods represents a delay time difference between the exponent delay output signal RE_OUT (e.g., one of the exponent delay output signals RE_OUT0-RE_OUT127) and the exponent input signal RE_IN (e.g., one of the exponent input signals RE_IN0-RE_IN127). The serial delay computing circuit220is configured to process most significant 4 bits (IN[7]-IN[4]) of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and most significant 4 bits (W[7]-W[4]) of the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0], i.e., the serial delay computing circuit220is configured to process one round, and the one round including adding the most significant 4 bits (IN[7]-IN[4]) and the most significant 4 bits (W[7]-W[4]). In another embodiment, the serial delay computing circuit220can be configured to process two rounds including a first round and a second round. The first round includes adding the most significant 4 bits (IN[7]-IN[4]) and the most significant 4 bits (W[7]-W[4]), i.e., INEXPM4b+WEXPM4b. In the first round, the two first time delay circuits221,222, the two second time delay circuits223,224, the two third time delay circuits225,226and the two fourth time delay circuits227,228receive the bits IN[7], W[7], IN[6], W[6], IN[5], W[5], IN[4], W[4], respectively. The second round includes adding least significant 4 bits (IN[3]-IN[0]) of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and least significant 4 bits (W[3]-W[0]) of the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0], i.e., INEXPL4b+WEXPL4b. In the second round, the two first time delay circuits221,222, the two second time delay circuits223,224, the two third time delay circuits225,226and the two fourth time delay circuits227,228receive the bits IN[3], W[3], IN[2], W[2], IN[1], W[1], IN[0], W[0], respectively.

The word line input driver unit300is connected to each of the exponent computing modules200via word lines, first input lines and second input lines. The word line input driver unit300generates a plurality of exponent input signals RE_IN0-RE_IN127, RE_TDC and the original input exponents IN0EXP[7:0]-IN127EXP[7:0]. The first input lines are configured to transmit the exponent input signals RE_IN0-RE_IN127, RE_TDC. The exponent input signals RE_IN0-RE_IN127, RE_TDC are rising edge input signals and are the same with each other. The second input lines are configured to transmit the original input exponents IN0EXP[7:0]-IN127EXP[7:0]. The word line input driver unit300is represented by “WL/INDRV & Edge Generator” and is located on a left side of the exponent computing modules200.

The winner-take-all circuit400is connected to the time domain exponent computing array TD-ECA and configured to find out one of the exponent delay output signals RE_OUT0-RE_OUT127as a maximum exponent adding signal RE_MAX. The one of the exponent delay output signals RE_OUT0-RE_OUT127is corresponding to a minimum one of the delay time periods. In detail, inFIG.4, the winner-take-all circuit400includes a plurality of first transistors N0-N127(i.e., N0, N1, N2, . . . , N127), a second transistor P1and an inverter INV. The first transistors N0-N127are controlled by the exponent delay output signals RE_OUT0-RE_OUT127, respectively. The second transistor P1is connected to the first transistors N0-N127and controlled by the maximum exponent adding signal RE_MAX. The inverter INV has an input node and an output node. The input node is connected to the first transistors N0-N127and the second transistor P1. The input node receives a maximum exponent adding signal bar RE_MAXB. The output node generates the maximum exponent adding signal RE_MAX according to the one of the exponent delay output signals RE_OUT0-RE_OUT127. Each of the first transistors N0-N127is the NMOS transistor. The second transistor P1is the PMOS transistor.

The dynamic logic block500is connected to the winner-take-all circuit400and configured to compare the maximum exponent adding signal RE_MAX with the exponent delay output signals RE_OUT0-RE_OUT127to generate a plurality of flags FLAG0-FLAG127. In detail, the dynamic logic block500includes a plurality of dynamic logic circuits. The dynamic logic circuits are connected to the winner-take-all circuit400and the time domain exponent computing array TD-ECA. Each of the dynamic logic circuits is coupled to the maximum exponent adding signal RE_MAX and each of the exponent delay output signals RE_OUT0-RE_OUT127, and configured to generate the flags FLAG0-FLAG127by comparing the maximum exponent adding signal RE_MAX and each of the exponent delay output signals RE_OUT0-RE_OUT127. Each of the dynamic logic circuits may be implemented by comparators or time to digital converters. Each of the flags FLAG0-FLAG127is a multi-bit signal and has a negative correlation with a sum of the one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the one of the original weight exponents W0EXP[7:0]-W127EXP[7:0].

In one embodiment, the time domain exponent computing block TD-ECB further includes a time to digital converter (TDC)600. The time to digital converter600is connected to the winner-take-all circuit400. The time to digital converter600is configured to receive the maximum exponent adding signal RE_MAX from the winner-take-all circuit400and generate a maximum input exponent MAX_EXP[7:0] according to the maximum exponent adding signal RE_MAX. In detail, the time to digital converter600is connected between the word line input driver unit300and the winner-take-all circuit400. The time to digital converter600is configured to receive the maximum exponent adding signal RE_MAX and the exponent input signal RE_TDC, and generate the maximum input exponent MAX_EXP[7:0] according to the exponent input signal RE_TDC and the maximum exponent adding signal RE_MAX. The maximum input exponent MAX_EXP[7:0] and the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] are configured to perform the MAC operation of the mantissa part.

The input mantissa pre-align block IM-PAB is connected to the time domain exponent computing block TD-ECB. The input mantissa pre-align block IM-PAB is configured to receive a plurality of original input mantissas INnMAN[7:0] (e.g., IN0MAN[7:0]-IN127MAN[7:0], one may be “1M6M5M4M3M2M1M0”) and shift the original input mantissas INnMAN[7:0] according to the flags FLAG0-FLAG127to generate a plurality of weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0]. n may be equal to 0-127. Sparsity of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] is greater than sparsity of the original input mantissas INnMAN[7:0]. In detail, the input mantissa pre-align block IM-PAB includes a plurality of shifters700. The shifters700are connected to the dynamic logic block500. Each of the shifters700is configured to receive one (1M6M5M4M3M2M1M0) of the original input mantissas INnMAN[7:0] and shift the one of the original input mantissas INnMAN[7:0] according to one (FLAG) of the flags FLAG0-FLAG127to generate one of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0], and each of the shifters700includes at least one multiplexer (MUX), as shown inFIG.5.

Reference is made toFIGS.1,2,5and7.FIG.7shows a schematic view of a relationship between a plurality of weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] and a plurality of sums of original input exponents IN0EXP[7:0]-IN127EXP[7:0] and original weight exponents W0EXP[7:0]-W127EXP[7:0]. InFIG.7, the original input mantissas INnMAN[7:0] is corresponding to “1M6M5M4M3M2M1M0”. Each of the bits M6, M5, M4, M3, M2, M1, M0may be 1 or 0. The input mantissa pre-align block IM-PAB is configured to shift the original input mantissas INnMAN[7:0] according to the flags FLAG0-FLAG127to generate the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0]. The flags FLAG0-FLAG127are corresponding to the sums of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the original weight exponents W0EXP[7:0]-W127EXP[7:0].

In detail, when the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to a maximum exponent adding value MAX(EXP), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “1M6M5M4M3M2M1M0”. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 1 (i.e., MAX(EXP)−1), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “01M6M5M4M3M2M1” that is the original input mantissa INnMAN[7:0] right shifted by 1 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 2 (i.e., MAX(EXP)−2), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “001M6M5M4M3M2” that is the original input mantissa INnMAN[7:0] right shifted by 2 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 3 (i.e., MAX(EXP)−3), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “0001M6M5M4M3” that is the original input mantissa INnMAN[7:0] right shifted by 3 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 4 (i.e., MAX(EXP)−4), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “00001M6M5M4” that is the original input mantissa INnMAN[7:0] right shifted by 4 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 5 (i.e., MAX(EXP)−5), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “000001M6M5” that is the original input mantissa INnMAN[7:0] right shifted by 5 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 6 (i.e., MAX(EXP)−6), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “0000001M6” that is the original input mantissa INnMAN[7:0] right shifted by 6 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is equal to the maximum exponent adding value MAX(EXP) minus 7 (i.e., MAX(EXP)−7), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “00000001” that is the original input mantissa INnMAN[7:0] right shifted by 7 bit. When the sum (INEn+WEn) of one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0] is smaller than the maximum exponent adding value MAX(EXP) minus 7 (i.e., <MAX(EXP)−7), the weighted input mantissa (WINnMAN[7:0]) is corresponding to “00000000” (i.e., all 0 input) that is the original input mantissa INnMAN[7:0] right shifted by 8 bit.

Therefore, the floating point pre-alignment structure100afor CIM applications of the present disclosure can utilize the time domain exponent computing block TD-ECB and the input mantissa pre-align block IM-PAB to shift the original input mantissas INnMAN[7:0] according to the exponent part of the input and the exponent part of the weight and then perform the MAC operation of the mantissa part, thereby realizing the concept of input mantissa pre-alignment and improve the problem of conventional CIM operating floating point. In addition, the floating point pre-alignment structure100afor CIM applications of the present disclosure does not lose accuracy and increases the sparsity of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] (i.e., increase input sparsity), thereby reducing power consumption and enhancing floating point CIM performance.

Reference is made toFIGS.1,2and8.FIG.8shows a flow chart of a computing method S0of a floating point pre-alignment structure for CIM applications according to a third embodiment of the present disclosure. The floating point pre-alignment structure for CIM applications may be the floating point pre-alignment structure100for CIM applications ofFIG.1or the floating point pre-alignment structure100afor CIM applications ofFIG.2. The computing method S0includes performing a voltage level applying step S02and a computing step S04. The voltage level applying step S02includes applying a plurality of voltage levels to a plurality of exponent input signals RE_IN0-RE_IN127, a plurality of original input exponents IN0EXP[7:0]-IN127EXP[7:0], a plurality of original weight exponents W0EXP[7:0]-W127EXP[7:0] and a plurality of original input mantissas INnMAN[7:0] (e.g., IN0MAN[7:0]-IN127MAN[7:0]). The computing step S04is performed to configure a time domain exponent computing block TD-ECB to compute the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and the original weight exponents W0EXP[7:0]-W127EXP[7:0]. In detail, the computing step S04includes performing a first computing step S042, a second computing step S044, a third computing step S046and a fourth computing step S048.

The first computing step S042includes configuring a time domain exponent computing array TD-ECA to delay the exponent input signals RE_IN0-RE_IN127by a plurality of delay time periods to generate a plurality of exponent delay output signals RE_OUT0-RE_OUT127, and each of the delay time periods is determined by adding one of the original input exponents IN0EXP[7:0]-IN127EXP[7:0] and one of the original weight exponents W0EXP[7:0]-W127EXP[7:0].

The second computing step S044includes configuring a winner-take-all circuit400to find out one of the exponent delay output signals RE_OUT0-RE_OUT127as a maximum exponent adding signal RE_MAX, and the one of the exponent delay output signals RE_OUT0-RE_OUT127is corresponding to a minimum one of the delay time periods.

The third computing step S046includes configuring a dynamic logic block500to compare the maximum exponent adding signal RE_MAX with the exponent delay output signals RE_OUT0-RE_OUT127to generate a plurality of flags FLAG0-FLAG127.

The fourth computing step S048includes configuring an input mantissa pre-align block IM-PAB to receive a plurality of original input mantissas INnMAN[7:0] and shift the original input mantissas INnMAN[7:0] according to the flags FLAG0-FLAG127to generate a plurality of weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0], and sparsity of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] is greater than sparsity of the original input mantissas INnMAN[7:0].

Therefore, the computing method S0of the present disclosure can shift the original input mantissas INnMAN[7:0] according to the exponent part of the input and the exponent part of the weight and then perform the MAC operation of the mantissa part, thereby realizing the concept of input mantissa pre-alignment and improve the problem of conventional CIM operating floating point. Moreover, the computing method S0of the present disclosure does not lose accuracy and increases the sparsity of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0], thereby reducing power consumption and enhancing floating point CIM performance.

In one embodiment, the number of exponent computing modules200, the number of the exponent input signals RE_IN0-RE_IN127, the number of the exponent delay output signals RE_OUT0-RE_OUT127, the number of the original input exponents IN0EXP[7:0]-IN127EXP[7:0], the number of the original weight exponents W0EXP[7:0]-W127EXP[7:0], the number of the flags FLAG0-FLAG127, the number of original input mantissas INnMAN[7:0] and the number of the weighted input mantissas WIN0MAN[7:0]-WIN127MAN[7:0] are all 128, but the present disclosure is not limited thereto.

According to the aforementioned embodiments and examples, the advantages of the present disclosure are described below.1. The floating point pre-alignment structure for CIM applications of the present disclosure and the computing method thereof of the present disclosure can utilize the time domain exponent computing block and the input mantissa pre-align block to shift the original input mantissas according to the exponent part of the input and the exponent part of the weight and then perform the MAC operation of the mantissa part, thereby realizing the concept of input mantissa pre-alignment and improve the problem of conventional CIM operating floating point.2. The floating point pre-alignment structure for CIM applications of the present disclosure and the computing method thereof of the present disclosure do not lose accuracy and increase the sparsity of the weighted input mantissas, thereby reducing power consumption and enhancing floating point CIM performance.