Power Semiconductor Module with Two Opposite Half-Bridges

A power semiconductor module (10) includes: a multilayer circuit board (18); a first semiconductor chip (T1) and a second semiconductor chip (T2) bonded to a first outer conducting layer (20a); a third semiconductor chip (T3) and a fourth semiconductor chip (T4) bonded to a second outer conducting layer (20b); a first substrate (42a) attached to the first semiconductor chip (T1) and the second semiconductor chip (T2); and a second substrate (42b) attached to the third semiconductor chip (T3) and the fourth semiconductor chip (T4). The first outer conducting layer (20a) is structured into a first DC+ area (26a), a first AC area (28a) and a first DC− area (30a) that interconnect the first semiconductor chip (T1) and the second semiconductor chip (T2) into a half-bridge. The second outer conducting layer (20b) is structured into a second DC+ area (26b), a second AC area (28b) and a second DC− area (30b), which interconnect the third semiconductor chip (T3) and the fourth semiconductor chip (T4) into a half-bridge. The first DC− area (30a) is connected via the first substrate (42) and a traversing conducting post (50) with an intermediate DC− area (32) of the intermediate conducting layer (24) and the second DC− area (30b) is connected via the second substrate (42b) and the traversing conducting post (50) with the intermediate DC− area (32). The traversing conducting post (50) runs through the multilayer circuit (18) between the first substrate (42a) and the second substrate (42b).

CROSS-REFERENCE TO RELATED APPLICATION

The present application is related and has right of priority to German Patent Application No. 102022202898.8 filed on Mar. 24, 2022, which is incorporated by reference in its entirety for all purposes.

FIELD OF THE INVENTION

The invention relates generally to a power semiconductor module.

BACKGROUND

In automotive applications with electrical drives, such as electrical cars and trucks, half-bridge modules are used for assembling inverters, which generate the AC current for driving an electrical motor, from a DC current, which may be provided by an electrical battery. Currently, such half-bridge modules include silicon (Si) semiconductors. However, due to their higher operation voltages and the possible higher switching frequencies, which may result in lower losses and a more efficient application of the half-bridge modules, it is also considered to use high bandgap semiconductors.

Such power semiconductor modules based on high bandgap semiconductors may benefit from new module designs, since higher switching frequencies usually result in different and/or higher electromagnetic radiation and losses. Also, an operation at higher voltages may need better local cooling capabilities.

SUMMARY OF THE INVENTION

Example aspects of the present invention provide a power semiconductor module

A first example aspect of the invention relates to a power semiconductor module. A power semiconductor module is a device for mechanically and electrically interconnecting power semiconductor chips. Here and in the following, the term “power” refers to devices and elements adapted for processing voltages of more than one hundred volts (100 V) and/or more than ten amps (10 A).

According to an example embodiment of the invention, the power semiconductor module includes a multilayer circuit board with a first outer conducting layer, a first isolating or insulation layer, an intermediate conducting layer, a second isolating or insulation layer and a second outer conducting layer. These layers may be arranged in this order in a direction orthogonal to an extension direction of the layers. The first isolating layer is sandwiched between the first outer conducting layer and the intermediate conducting layer. The second isolating layer is sandwiched between the second outer conducting layer and the intermediate conducting layer. The conducting layers may be made of metal, such as copper, and/or may be metallization layers. The isolating layers may be made of plastics and/or ceramics. The multilayer circuit board may be a PCB (printed circuit board), a DBC (direct bonded copper) substrate or an IMS (insulated metal substrate).

According to an example embodiment of the invention, the power semiconductor module includes a first semiconductor chip and a second semiconductor chip, which are bonded to the first outer conducting layer and a third semiconductor chip and a fourth semiconductor chip, which are bonded to the second outer conducting layer. Such semiconductor chips may have a plastics housing, which encloses a die made of a semiconductor material, which provides the functionality of the chip. The semiconductor chips may include controllable switches, such as transistors and/or thyristors. In particular, the semiconductor chips may include HEMTs. Every semiconductor chip may provide two power electrodes to be supplied with the main current through the device (such as drain and source electrodes, or emitter and collector electrodes) and a control electrode for switching the main current (such as a gate electrode or a base electrode).

Here and in the following, bonding may refer to a process for electrically and mechanically connecting two metallic elements, such as soldering, welding and sintering.

According to an example embodiment of the invention, the power semiconductor module includes a first substrate attached to the first semiconductor chip and the second semiconductor chip, such that the first semiconductor chip and the second semiconductor chip are arranged between the first substrate and the multilayer circuit board. Furthermore, the power semiconductor module includes a second substrate attached to the third semiconductor chip and the fourth semiconductor chip, such that the third semiconductor chip and the fourth semiconductor chip are arranged between the second substrate and the multilayer circuit board. The first substrate may include a first conducting layer and the second substrate may include a second conducting layer, which conducting layers are used for electrically interconnecting the intermediate conducting layer with DC− areas of the outer conducting layer of the multilayer circuit board. The first substrate and/or the second substrate may be a PCB (printed circuit board), a DBC (direct bonded copper) substrate or an IMS (insulated metal substrate).

According to an example embodiment of the invention, wherein the first outer conducting layer of the multilayer circuit board is structured into a first positive direct current (DC+) area, a first alternating current (AC) area and a first negative direct current (DC−) area, which interconnect the first semiconductor chip and the second semiconductor chip into a half-bridge. Furthermore, the second outer conducting layer of the multilayer circuit board is structured into a second positive direct current (DC+) area, a second alternating current (AC) area and a second negative direction current (DC−) area, which are separated from each other on the second isolating layer and which interconnect the third semiconductor chip and the fourth semiconductor chip into a half-bridge. The first DC+ area, the first AC area and the first DC− area may be separated from each other on the first isolating layer. The second DC+ area, the second AC area and the second DC− area may be separated from each other on the second isolating layer. “separated from each other on the isolating layer” may mean that the corresponding components are electrically isolated from each other, when the respective semiconductor chips are not present, i.e. bonded to them.

It also may be that the first outer conducting layer and/or the second outer conducting layer includes a control electrode area, which is separated from the other areas. Control electrodes of the semiconductor chips may be bonded to the control electrode areas. The power electrodes and optionally the control electrode of a semiconductor chip may be provided on the same side of the semiconductor chip.

In this way, the first semiconductor chip and the second semiconductor chip are connected into a half-bridge and the third semiconductor chip and the fourth semiconductor chip are connected into a half-bridge. A half-bridge is a circuit, in which the corresponding two semiconductor chips, each of which includes a semiconductor switch, are series connected.

According to an example embodiment of the invention, the first DC− area is connected via the first substrate and a traversing conducting post with the intermediate conducting layer and the second DC− area is connected via the second substrate and the traversing conducting post with the intermediate conducting layer. The traversing conducting post runs through the multilayer circuit, i.e. traverses the multiplayer circuit, between the first substrate and the second substrate. In particular, the traversing conducting post is connected with an intermediate DC− area provided by the intermediate conducting layer.

Since the DC− areas are connected to the intermediate layer, which conducts the current through the DC− side of the power semiconductor module between the semiconductor chips and their electrical interconnection, the power semiconductor module has a low inductance of the power conductor loop. This power conductor loop is further reduced by guiding the current above the second and fourth semiconductor chip through conducting layers of the first substrate and the second substrate. This results in a lower stray inductance of power conductor loops formed by the power semiconductor module together with further electrical components to which the power semiconductor module is connected. This may be beneficial, when the power semiconductor chips are switched with higher frequencies as ordinary devices, which may be the case for chips based on a wide bandgap material.

Furthermore, a symmetric arrangement of the first semiconductor chip and the second semiconductor chip with respect to the third semiconductor chip and the fourth semiconductor chip results in an even current distribution inside the power semiconductor module. The symmetric arrangement may be mirror symmetric. The first outer conducting layer and the second outer conducting layer may be arranged (mirror) symmetric. The first substrate and the second substrate may be arranged (mirror) symmetric.

The DC− current runs through the first substrate and the second substrate, to which cooling elements may be attached directly. Thus, the current path through the module may be cooled more efficiently.

Due to the half-bridges on each side of the multilayer circuit board, the power semiconductor module provides a high power density. The arrangement of the components of the power semiconductor module results in a compact design. The usually substantially cuboid-shaped space occupied by the power semiconductor module may be designed to be more like a cube than a flat box. This may result in more freedom for assembling the semiconductor module into an inverter.

According to an example embodiment of the invention, the traversing conducting post is arranged between the first semiconductor chip and the second semiconductor chip and/or is arranged between the third semiconductor chip and the fourth semiconductor chip. The intermediate DC− area may solely be arranged between the first semiconductor chip and third semiconductor chip. The intermediate DC− area may be connected at a side to the traversing conducting post.

According to an example embodiment of the invention, the traversing conducting post is connected to the intermediate DC− area of the intermediate conducting layer inside the multilayer circuit board. For example, the traversing conducting post may be or may include a through via of the multilayer circuit board, which is connected inside the multilayer circuit board, in particular between the two isolating layers, with the intermediate DC− area.

According to an example embodiment of the invention, the first substrate includes a conducting layer and an isolating or insulating layer, wherein the conducting layer of the first substrate is structured to provide a third negative direct current (DC−) area which is connected to the first DC− area of multilayer circuit board and the traversing conducting post. Analogously, the second substrate includes a conducting layer and an isolating layer, wherein the conducting layer of the second substrate is structured to provide a fourth negative direct current (DC−) area which is connected to the second DC− area of multilayer circuit board and the traversing conducting post. The conduction layers may be made of metal. A part of the conducting layers of the first substrate and the second substrate may be used for connecting the respective DC− areas with the traversing conducting post. The conducting layers of the first substrate and the second substrate may be arranged to face the semiconductor chips.

According to an example embodiment of the invention, the traversing conducting post is connected to a third negative direct current (DC−) area of the first substrate, which third DC− area is connected to the first DC− area, wherein the first DC− area and the third DC− area are connected via a first conducting post. Analogously, the traversing conducting post is connected to a fourth negative direct current (DC−) area of the second substrate, which fourth DC− area is connected to the second DC− area, wherein the second DC− area and the fourth DC− area are connected via a second conducting post. The first and second conducting posts may be made of metal pins and/or blocks, which are bonded to the multilayer circuit board and the first substrate and the second substrate, respectively.

According to an example embodiment of the invention, the first conducting post is arranged besides the second semiconductor chip opposite to the traversing conducting post. Analogously, the second conducting post is arranged besides the fourth semiconductor chip opposite to the traversing conducting post. Thus, the DC− current may run around the second semiconductor chip via the first conducting post, the third DC− area of the first substrate and the traversing conducting post. Also, the DC− current may run around the fourth semiconductor chip via the second conducting post, the fourth DC− area of the second substrate and the traversing conducting post.

According to an example embodiment of the invention, the intermediate DC− area is arranged between the first DC+ area and the second DC+ area. The DC− current may further be guided between the first semiconductor chip and the second semiconductor chip.

According to an example embodiment of the invention, the intermediate DC− area is arranged between the first AC area and the second AC area. It may be that at least partially, the intermediate DC− area is also arranged between the AC areas.

According to an example embodiment of the invention, the intermediate DC− area is arranged between the first semiconductor chip and the third semiconductor chip. As already mentioned, the DC− current may be guided between the first semiconductor chip and the second semiconductor chip.

According to an example embodiment of the invention, the first AC area and the second AC area are connected to an intermediate AC area of the intermediate conducting layer. The intermediate conducting layer may be structured into the intermediate DC− area and the intermediate AC area. The intermediate AC area may be arranged between the first DC− area and the second DC− area. The intermediate AC area may be arranged between the second semiconductor chip and the fourth semiconductor chip. The AC current may be guided between the third semiconductor chip and the fourth semiconductor chip as well as between the first DC− area and the second DC− area.

According to an example embodiment of the invention, an AC terminal is connected to the intermediate AC area. The AC terminal may be provided on a side of the power semiconductor module, which is opposite to a side, where DC terminals are arranged.

It may be that the first AC area and the second AC area are connected, for example via an AC terminal and/or via the intermediate AC area. It also may be that the first DC+ area and the second DC+ area are connected with each other, for example, via a DC− terminal. In such a way, the two half-bridges formed by the first and second semiconductor chips as well as third and fourth semiconductor chips are paralleled in the power semiconductor module.

According to an example embodiment of the invention, a DC+ terminal is connected to the DC+ area of the first outer conducting layer and to the DC+ area of the second outer conducting layer. Also, a DC− terminal may be connected to the intermediate conducting layer and in particular to the intermediate DC− area. The terminals, i.e. the DC terminals and/or the AC terminals, may be parts of the power semiconductor module, where the power semiconductor module is electrically connected to further devices.

The terminals may be connected to the multilayer circuit board, such that the two half-bridges formed by the semiconductor chips are connected in parallel with respect to DC+, DC− and AC. Such half-bridges may be used for generating the phase of an AC current from a DC current. The power semiconductor module also may be seen as a half-bridge module.

According to an example embodiment of the invention, the DC+ terminal and the DC− terminal are arranged at the same first side of the power semiconductor module. An AC terminal connected to the first AC area and the second AC area, for example via the intermediate AC area, is arranged on a second side of the power semiconductor module, which second side is opposite to the first side. The layers of the multilayer circuit board may extend substantially parallel to a plane. Also, the sides of the multilayer circuit board to which the semiconductor chips are bonded extend in this plane. The small sides of the multilayer circuit board are located at a border of the multilayer circuit board, which may have a substantially rectangular shape. The DC+ terminal and the DC− terminal may be arranged at the same small side. This may reduce the size of the power conductor loops.

According to an example embodiment of the invention, the first semiconductor chip and the third semiconductor chip are arranged opposite to each other with respect to the multilayer circuit board. Analogously, the second semiconductor chip and the fourth semiconductor chip are arranged opposite to each other with respect to the multilayer circuit board. With respect to a view direction onto the plane of the multilayer circuit board, the first (or second) semiconductor chip and the third (or fourth) semiconductor chip may overlap each other substantially completely. As already mentioned, the semiconductor chip may be arranged mirror symmetric with respect to a middle plane of the multilayer circuit board.

According to an example embodiment of the invention, the first DC+ area and the second DC+ area are arranged opposite to each other with respect to the multilayer circuit board. Also, the first AC area and the second AC area may be arranged opposite to each other with respect to the multilayer circuit board. Furthermore, the first DC− area and the second DC− area may be arranged opposite to each other with respect to the multilayer circuit board. It also may be that the third DC− area and the fourth DC-area are arranged opposite to each other with respect to the multilayer circuit board. All these areas may be arranged mirror symmetric with respect to a middle plane of the multilayer circuit board. With respect to a view direction onto the plane of the multilayer circuit board, the DC+ areas, AC areas and/or respective DC− areas may overlap each other substantially completely.

According to an example embodiment of the invention, the first semiconductor chip and the second semiconductor chip are arranged in a row along the first DC+ area, the first AC area and the first DC− area. Analogously, the third semiconductor chip and the fourth semiconductor chip are arranged in a row along the second DC+ area, the second AC area and the second DC− area.

According to an example embodiment of the invention, wherein a first cooling element is attached to a backside of the first substrate opposite to the multilayer circuit board and/or a second cooling element is attached to a backside of the second substrate opposite to the multilayer circuit board. The backside of a semiconductor chip may be located opposite to a power electrodes side with the power electrodes of the semiconductor chip. The semiconductor chips may have all its electrodes on a first side, i.e. the power electrodes side. The second side or backside may be cooled with the respective cooling element. Such cooling elements may have radiators or heat sinks and/or may be water cooled and/or air cooled.

According to an example embodiment of the invention, spacers are arranged between the multilayer circuit board and the first substrate and the second substrate. The spacers may be used for mechanically supporting the first substrate and the second substrate on the multilayer circuit board. The spacers also may be used for thermally connecting the first substrate and the first cooling element and the second substrate and the second cooling element to the multilayer circuit board. Such spacers may be made of an electrically insulating material and/or thermally conducting material. The spacers may be used for directly cooling the DC+ area, the AC area and/or the DC− areas provided on the multilayer circuit board. In such a way, it may be avoided that these areas, which may be directly connected to the power electrode side of the semiconductor chips, become too hot.

According to an example embodiment of the invention, each of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip has power electrodes on a side facing the multilayer circuit board. The power electrode side of the respective semiconductor chip may be bonded to the respective conducting layer of the multilayer circuit board.

According to an example embodiment of the invention, the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip are based on a wide bandgap semiconductor material, for example GaN (gallium nitride) or SiC (silicon carbide). The die of each semiconductor chip may be made of a wide bandgap material. Such semiconductor chips allow for higher switching frequencies and/or higher operation voltages.

The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols below. In principle, identical parts are provided with the same reference symbols in the figures.

DETAILED DESCRIPTION

FIG.1shows a circuit diagram of a power semiconductor module10, which includes four power semiconductor chips T1, T2, T3and T4, which may be GaN or SiC transistors. Such wide bandgap semiconductor chips T1, T2, T3, T4provide the possibility to operate the power semiconductor module10with higher voltages and/or higher switching frequencies.

The semiconductor chips T1, T2are connected in series to form a first half-bridge and the semiconductor chips T3, T4are connected in series to form a second half-bridge. The two half-bridges are connected in series at a DC+ terminal, a DC− terminal and an AC terminal. Each of the power semiconductor chips T1, T2, T3, T4has two power electrodes12and a control electrode14. The series connection of the power semiconductor chips T1, T2, T3, T4is via the power electrodes12.

FIG.1furthermore shows stray and/or parasitic inductances16a,16b,16cwhich can be reduced with the design such as shown inFIG.2.

FIG.2shows a power semiconductor module10with a circuit diagram such as shown inFIG.1. Same parts inFIG.1andFIG.2are depicted with the same reference numerals.

The power semiconductor module10includes a multilayer circuit board18, which in this order includes a first outer conducting layer20a, a first isolating layer22a, an intermediate conducting layer24, a second isolating layer22band a second outer conducting layer20b. The multilayer circuit board18may be provided by a printed circuit board, by a DBC (direct bonded copper) substrate or IMS (insulated metal substrate). The conducting layers20a,20b,24may be metallization layers, such as copper layers. The isolating layers22a,22bmay be made of plastics or ceramics. It also may be that the multilayer circuit board18includes more than five layers.

The multilayer circuit board18defines a plane, to which all the layers of the multilayer circuit board18and also the layers of the first and second substrate (see below) run in parallel. This plane may be seen as main extension plane of the power semiconductor module10.

The first outer conducting layer20ais structured to provide a first DC+ area26a, a first AC area28aand a first DC− area30a, which are separated from each other on the first isolating layer22a. The second outer conducting layer20bis structured to provide a second DC+ area26b, a second AC area28band a second DC− area30b, which are separated from each other on the second isolating layer22b. These areas may be seen as conductor paths and/or tracks, which provide a part of the electric circuitry of the power semiconductor module10, such as shown inFIG.1.

The semiconductor chip T1is bonded with an electrode side to the DC+ area26aand the AC area28aof the conducting layer20a, in particular such that one power electrode12is bonded to the DC+ area26aand that the other one power electrode12is bonded to the AC area28a. The semiconductor chip T2is bonded with an electrode side to the AC area28aand the DC− area30aof the conducting layer20a, in particular such that one power electrode12is bonded to the AC area28aand that the other one power electrode12is bonded to the DC− area30a.

The semiconductor chip T3is bonded with an electrode side to the DC+ area26band the AC area28bof the conducting layer20b, in particular such that one power electrode12is bonded to the DC+ area26band that the other one power electrode12is bonded to the AC area28b. The semiconductor chip T4is bonded with an electrode side to the AC area28band the DC− area30bof the conducting layer20b, in particular such that one power electrode12is bonded to the AC area28band that the other one power electrode12is bonded to the DC− area30b.

As mentioned above, such power electrodes12may include drain, source, emitter and collector electrodes.

Each of the semiconductor chips T1, T2, T3, T4has a substantial cuboid body with a height substantially (such as at least five (5) times) smaller than a width and a length. The cuboid bodies may be oriented in parallel to the plane defined by the multilayer circuit board18. On one side, which may be seen as the front side or power electrode side, the power electrodes12are arranged. The opposite side may be seen as the backside of the respective semiconductor chip T1, T2, T3, T4. On the power electrode side, also a control electrode may be arranged.

The first semiconductor chip T1and the second semiconductor chip T2are arranged in a row along the DC+ area26a, the AC area28aand the DC− area30aof the first outer conducting layer20a. The third semiconductor chip T3and the fourth semiconductor chip T4are arranged in a row along the DC+ area26b, the AC area28band the DC− area30bof the second outer conducting layer20b. The semiconductor chips T1and T2are electrically connected via the areas26a,28a,30ainto a first half-bridge and the semiconductor chips T3and T4are electrically connected via the areas26b,28b,30binto a second half-bridge.

As indicated inFIG.2, the DC+ areas26aand26bmay be interconnected with each other. For example, this may be done with one or more through vias (not shown), which run through the intermediate layer24without being connected to the intermediate layer24.

The first semiconductor chip T1and the third semiconductor chip T3are arranged opposite to each other with respect to the multilayer circuit board18. Also, the second semiconductor chip T2and the fourth semiconductor T4chip are arranged opposite to each other with respect to the multilayer circuit board18. With respect to a view direction onto the multilayer circuit board18and/or onto the plane defined by the multilayer circuit board18, the chips T1and T2as well as the chips T3and T4substantially overlap each other.

The same applies to the areas26a,26b,28a,28b,30a,30b: The DC+ area26aof the first outer conducting layer20aand the DC+ area26bof the second outer conducting layer20bare arranged opposite to each other with respect to the multilayer circuit board18. The AC area28aof the first outer conducting layer20aand the AC area28bof the second outer conducting layer20bare arranged opposite to each other with respect to the multilayer circuit board18. The DC− area30aof the first outer conducting layer20aand the DC− area30bof the second outer conducting layer20bare arranged opposite to each other with respect to the multilayer circuit board18. With respect to a view direction onto the multilayer circuit board18and/or onto the plane defined by the multilayer circuit board18, the areas26a,26band/or28a,28band/or30a,30b, which are arranged opposite to each other, substantially overlap each other.

The intermediate layer24is structured into an intermediate DC− area32and an intermediate AC area34. The intermediate DC− area32is arranged between the first DC+ area26aand the second DC+ area26b. Also, the intermediate DC− area32is arranged between the first AC area28aand the second AC area28band/or the intermediate DC− area32is arranged between the first semiconductor chip T1and the third semiconductor chip T3.

The AC areas28a,28bmay be interconnected with each other. This may be done with a through via36which runs through the intermediate layer24and is connected to the intermediate layer24. The AC area28aand the AC area28bare connected to an intermediate AC area34of the intermediate conducting layer24. The intermediate AC area34is arranged between the first DC− area30aand the second DC− area30band/or the intermediate AC area34is arranged between the second semiconductor chip T2and the fourth semiconductor chip T4.

A DC+ terminal may be connected to the first DC+ area26aand the second DC+ area26band a DC− terminal may be connected to the intermediate DC− area32. The DC+ terminal may be provided by a part of the conducting layers20aand/or20b, which part may protrude from the multilayer circuit board18. It also is possible that the DC+ terminal is a conducting plate or post bonded to the conducting layers20aand/or20b.

An AC terminal is connected to the intermediate AC area34. The AC terminal may be provided by a part of the intermediate conducting layer24, which part may protrude from the multilayer circuit board18. It also is possible that the AC terminal is a conducting plate or post bonded to the intermediate conducting layer24.

The DC+ terminal and the DC− terminal are arranged at the same first side38of the power semiconductor module10. The AC terminal is arranged on a second side40of the power semiconductor module10, which second side40is opposite to the first side38. The small sides38,40of the multilayer circuit board18may be defined as sides of the multilayer circuit board18, which run substantially orthogonal to the plane defined by the multilayer circuit board18. From the point of view inFIG.2, the small sides38,40are left and right with respect to the multilayer circuit board18.

The power semiconductor module10furthermore includes a first substrate42aattached, for example bonded to the first semiconductor chip T1and the second semiconductor chip T2, and a second substrate42battached, for example bonded, to the third semiconductor chip T3and the fourth semiconductor chip T4.

The first substrate42aincludes a conducting layer44aand an isolating layer46a. The conducting layer44aof the first substrate42ais structured to provide a third DC− area48awhich is connected to the first DC− area30aand a traversing conducting post50. The second substrate42bincludes a conducting layer44band an isolating layer46b. The conducting layer44bof the second substrate42bis structured to provide a fourth DC− area48bwhich is connected to the second DC− area30band the traversing conducting post50.

The traversing conducting post50is used for connecting the third DC− area48aand the fourth DC− area48bto the intermediate DC− area32of the intermediate conducting layer24. In such a way, the first DC− area30ais connected via the first substrate42aand the traversing conducting post50with the intermediate DC− area32and the second DC− area30bis connected via the second substrate42band the traversing conducting post50with the intermediate DC− area32.

The traversing conducting post50runs through the multilayer circuit18and/or traverses the multilayer circuit18between the first substrate42aand the second substrate42b. The traversing conducting post50runs through the first conducting layer20aand in particular the AC area28awithout being connected to them and/or the traversing conducting post50runs through the second conducting layer20band in particular the AC area28bwithout being connected to them. The traversing conducting post50runs through the first isolating layer22aand the second isolating layer22b. The traversing conducting post50runs through the intermediate layer24and is connected to the intermediate DC− area32and is disconnected from the intermediate AC area34. The traversing conducting post50is connected to the intermediate DC− area32inside multilayer circuit board18.

The traversing conducting post50is arranged between the first semiconductor chip T1and the second semiconductor chip T2and is arranged between the third semiconductor chip T3and the fourth semiconductor chip T4. This may be seen with respect to a direction in which the chips T1and T2as well as T3and D4are arranged.

The traversing conducting post50is connected to the third DC− area48aof the first substrate42a, which is connected via a first conducting post52awith the first DC− area30a. The traversing conducting post50is also connected to the fourth DC− area48bof the second substrate42b, which is connected via a second conducting post50with the second DC− area30b.

The first conducting post52ais arranged besides the second semiconductor chip T2opposite to the traversing conducting post50and the second conducting post52bis arranged besides the fourth semiconductor chip T4opposite to the traversing conducting post50. In such a way, two current loops for the DC− current are formed around the semiconductor chips T2, T4.

It may be that the first substrate42aincludes a further conducting layer54aand/or that the second substrate42bincludes a further conducting layer54b.54a/54bis thermal conducting layer but not electronic conducting layer

The semiconductor module10may further include a first cooling element56aand a second cooling element56b, which are arranged oppositely to each other with respect to the multilayer circuit board18. The first cooling element56ais bonded or otherwise attached to backsides of the semiconductor chips T1and T2. The second cooling element56bis bonded or otherwise attached to backsides of the semiconductor chips T3and T4. The cooling elements56a,56bmay be any kind of cooling element and/or may be based on air and water cooling.

For increasing the mechanical stability and improving the cooling performance of the power semiconductor module10, spacers48may be provided, which are arranged between the multilayer circuit board18and the substrates42a,42b. Each of the spacers48may be a post or bar, which is in contact with the multilayer circuit board18and one of the substrates42a,42b. The spacers48may be made of an electrically isolating material with good thermal conducting properties. For example, the heat conducting coefficient of the spacers48may be higher than the one of the semiconductor chips T1, T2, T3, T4.

As an example, the spacers48are bonded or otherwise attached to the outer conducting layers20a,20bof the multilayer circuit board18, for example to the AC areas28a,28b, and to the conducting layers44a,44bof the substrates42a,42b.

Due to the design as shown inFIG.2with the DC− terminal between and close to the DC+ areas26and the DC− areas30and the small current loops around the semiconductor chips T2, T4, the stray inductances16afor the power loops are reduced. Due to the intermediate AC area34between the DC− areas30a,30b, also the stray inductances16cfor the AC side are reduced in this way.

Furthermore, the symmetric layout for the paralleled power semiconductor chips T1, T2, T3and T4results in a good current balance. The power loop inductance for the power semiconductor chips T1, T3is nearly the same as for the power semiconductor chips T2, T4.

LIST OF REFERENCE SYMBOLS