Early cache prefetching in preparation for exit from idle mode

A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.

BACKGROUND

Field of the Disclosure

The present disclosure relates generally to computing systems and, more particularly, to power management in computing systems.

Description of the Related Art

Computing systems often utilize power-saving techniques in which the state of a processing component is temporarily saved to memory and the processing component is then placed in a low power state while in an idle mode. When the processing component exits the idle mode to return to an active mode, the saved state is accessed from the memory and used to restore the processing component to its previous state before entering the idle mode. However, when the processing component enters the idle mode, one or more caches associated with the processing component typically are flushed to a cache level or memory outside of the power domain of the processing component, and the flushed cache is then placed in a low power state in which the cache cannot reliably retain data. As such, when the processing component exits the idle mode, the cache is empty of valid data and the processing component suffers a “cold start” penalty because the initial memory accesses performed after the exit from the idle mode result in cache misses and thus must be serviced by memory or a higher level of cache. As memory accesses to memory or higher level caches exhibit higher latency than accesses to lower levels of cache, this cold start penalty can introduce significant performance losses.

DETAILED DESCRIPTION OF EMBODIMENT(S)

As the one or more caches associated with a processor core or other functional unit of a computing system are flushed when the functional unit is prepared for entry into a low power state, the reentry of the functional unit to an active mode can result in a significant cold start penalty due to the one or more empty caches. To reduce or eliminate this cold start penalty,FIGS. 1-9describe example techniques for reinitializing the functional unit prior to a predicted exit from an idle mode and using the reinitialized functional unit to at least partially repopulate the one or more caches so that the functional unit is ready to resume instruction execution using the repopulated cache data, rather than having to rely on higher-latency memory accesses for the needed data. In at least one embodiment, when the functional unit transitions from an active mode to an idle mode, the contents of the one or more caches in the same power domain as the functional unit are flushed. Further, a prediction unit predicts the duration that functional unit will be in the idle mode based on one or more factors, such as a history of idle durations under similar circumstances. At a specified time prior to the lapse of this predicted duration, a power management unit triggers the functional unit to transition back to the active mode. As part of this transition, a cache repopulation unit operates to repopulate the one or more flushed caches with at least a portion of the data they stored prior to the idle mode transition (hereinafter, “the previously cached data”). As such, when the actual idle mode exit trigger occurs (e.g., the receipt of an interrupt), the functional unit may begin processing of the interrupt or other trigger using the repopulated data in the one or more caches, thus avoiding the cache misses and resulting high-latency memory accesses that plague conventional idle-to-active transition techniques.

FIG. 1illustrates a computing system100utilizing early cache prefetching in anticipation of exit from an idle mode in accordance with some embodiments. The computing system100may include, for example, a desktop computer, laptop computer, a tablet computer, a computing-enabled cellular phone, a gaming console, a personal digital assistant, a computing-enabled watch or other computing enabled wearable device, and the like. In the depicted example, the computing system100includes a processing device102coupled to a memory104(e.g., system memory), a display106, and one or more peripherals108(e.g., keyboard, mouse, printer, and the like). The processing device102may be implemented as a single integrated circuit, or as a combination of multiple integrated circuits, such as a system-on-a-chip (SoC). To illustrate, the processing device102(and the functional units formed thereon) may forming part of one semiconductor die, while the memory106forms part of a different semiconductor die.

The processing device102includes one or more functional units coupled to a northbridge110, which in turn is coupled to a memory controller112, one or more input/output (I/O) interfaces114, a display interface116, a graphics engine118(also referred to as a graphics processing unit or GPU), a clock source120, and a voltage regulator122. The functional units can comprise any of a variety of processing components configured to execute software or firmware instructions. Examples of such functional units include central processing unit (CPU) cores, GPU cores, digital signal processors (DSPs), and the like. For ease of reference, the techniques of the present disclosure are described in the example context of processor cores as functional components, such as the plurality of processor cores131,132, and133illustrated inFIG. 1. However, the described techniques may be employed for any of a variety of functional units, such as for the graphics engine118, a DSP, and the like, using the guidelines provided herein.

As illustrated by an expanded view134of processor core131, each of the processor cores131-133includes an execution pipeline136, at least one cache138, and a cache population unit140. The execution pipeline136includes various stages or components used in executing instructions from an operating system or application being executed by the processing device102, such as a prefetcher142, a dispatch unit (not shown), an integer execution unit or arithmetic logic unit (ALU) (not shown), a floating point unit (FPU) (not shown), a retirement unit (not shown), and the like. The one or more caches138of the processor core form a cache hierarchy for temporarily storing data (including instructions) that may be accessed by the execution pipeline136with less latency than a memory access to the memory104. For ease of illustration, the processor core is described as having a single cache; however, in other embodiments, the processor core may have multiple levels of caches within its power domain, or one or more caches may be shared by multiple processor cores. As described in greater detail herein, the cache population unit140operates to facilitate the repopulation of the one or more caches138with data in anticipation of a transition of the processor core from an idle mode to an active mode. The cache population unit140may be implemented as a hardware state machine143, a dedicated set144of microcode instructions stored in a microcode read only memory (ROM)145(also referred to as a “control store”) of the processor core, or a combination thereof.

The northbridge110provides a variety of interface functions for each of the processor cores131-133, including interfacing with the memory104and to the peripherals108. In addition, in the depicted embodiment, the northbridge110provides power management functionality for the processor cores131-133and the other functional units of the processing device102. To this end, the northbridge110includes a power management unit146coupled to a prediction unit148. The power management unit146controls the power states of the processor cores131-133via control of one or both of the clock source120(which provides clock signals to the processor cores131-133) and the voltage regulator122(which provides regulated supply voltages to the processor cores131-133). The power management unit146independently controls the N clock signals provided by the clock source120to the N processor cores via signaling denoted as “SetF[N:0]” and controls the N supply voltages provided by the voltage regulator122to the N processor cores via signaling denoted as “SetV[N:0]”.

In at least one embodiment, the processor cores131-133have at least two general modes: an active mode, in which the processor core is doing useful work; and an idle mode, in which the CPU is idle (that is, not doing useful work). While in the active mode, the processor core may employ any of a number of different performance states or operating points, with corresponding pairings of clock frequency and voltage, as controlled by the power management unit146. When a processor core is in the idle mode, the power management unit146may elect to place the processor core in a low power state (or an operating system (OS) may elect to do so via signaling provided to the functional unit). However, there is overhead in entering a low power state in terms of energy costs and performance costs. Accordingly, in deciding whether to transition an idle processor core to a low power state, the power management unit146may determine whether entry into a low power state may provide power savings at or beyond a break-even point. For example, entry into the low power state may require flushing of one or more caches, saving architectural state, powering down phase locked loops (PLLs), and so on. Upon exit from the low power state, the PLLs may require a warm-up period before becoming fully operational, and restoration of a previous state may also be required upon exit from the low power state. As such, a relatively short idle mode duration may cause the cost/benefits evaluation to fall short of the break-even point, whereas a relatively long idle mode duration may provide power savings in excess of the power/performance costs of the low power state entry and exit transitions.

Accordingly, to facilitate this cost/benefit evaluation, the prediction unit148operates to predict the duration of the current idle mode (that is the, iteration of the idle mode which the processor core has entered, or is about to enter), and thus predict when the exit from the idle mode is to occur. The prediction unit148can utilize any of a variety of prediction methodologies in estimating or otherwise predicting the duration of the current idle mode. For example, the prediction unit148may implement the idle phase exit prediction process outlined in U.S. Patent Application Publication No. 2014/0181,556, entitled “Idle Phase Exit Prediction” and filed on Jun. 26, 2014, the entirety of which is incorporated by reference herein. As disclosed by this reference, the prediction unit148may store and analyze information regarding respective durations of a number of previously occurring idle modes for each processor core and respective durations of a number of previously occurring active modes for each processor core. The duration information for each processor core may be arranged in bins and the prediction unit148may then predict the duration of the current idle mode for each processor core based on this binned information. In other embodiments, the prediction unit148may use a different prediction process, such as assuming a predefined average duration for all idle modes, employing a lookup table or other data structure that is pre-populated with defined average idle mode durations based on the various criteria, such as the workload performed by the processor core prior to entry into the idle mode, and the like.

Using the predicted idle mode duration provided by the prediction unit148, the power management unit146determines whether to place an idle processor core into a low power state. Thus, if the prediction unit148predicts that the current idle mode may be of a relatively short duration, the power management unit146may forgo entry into a low power state, as the costs incurred in doing so may outweigh the benefit of the power savings that may be obtained. Conversely, if the prediction unit148predicts that the current idle mode may be of a relatively long duration, the power savings obtained by entry into a low power state may outweigh costs of entry into that state. Thus, in the latter case, the power management unit146may place an idle processor core into a low power state responsive to determining that the predicted idle duration is sufficiently long to justify the costs of powering down and then subsequently powering up the idle processor core.

Typically, the power management unit146places an idle processor core into a low power state by one or both of power gating or clock gating the power domain of the processor core. The power management unit146may clock gate a processor core by controlling the clock source120via the corresponding bit of the SetF signal to inhibit the clock signal supplied to the processor core or to reduce the frequency of the clock signal to below a minimum operational frequency. The power management unit146may power gate a processor core by controlling the voltage regulator122via the corresponding bit of the SetV signal to drop the supply voltage provided to the processor core to a level below a minimum retention threshold of the circuitry of the processor core or to inhibit the supply of the supply voltage completely.

The power gating of a processor core typically causes the processor core to lose its architectural state at the time of entry into the low power state. Accordingly, in anticipation of a transition to a low power state, the processor core stores a copy of the pertinent architectural state to the memory104, and when the processor core transitions out of the low power state, the saved architectural state is restored to the processor core, thereby allowing the processor core to effectively resume where it left off. The cache138is in the same power domain as the rest of the processor core, and thus when the processor core is power gated, the data stored in the cache138is lost. Accordingly, in at least one embodiment, in anticipation of the transition to a low power state, the cache population unit140operates to store cache restoration information in the memory104, or to a cache outside of the power domain of the processor core, whereby the cache restoration information is representative of the data stored in the cache at the time of transition to the low power state (that is, the “previously-cached data”). Then, when the processor core is to transition back to an active mode, the cache population unit140operates to coordinate with the prefetcher142and other components of the execution pipeline136to perform a set of load operations that prefetch at least some of the data previously stored in the cache138so as to at least partially repopulate the cache138with the previously cached data.

In at least one embodiment, the power management unit146triggers the cache prefetching process prior to the predicted exit from the low power state so that the cache138is, at the time of the predicted exit, at least partially repopulated with previously cached data. In some embodiments, this early cache prefetching process is triggered a specified time prior to predicted exit. To illustrate, analysis or modeling of the performance of an implementation of the processing device102may reveal that X microseconds are needed, on average, to sufficiently repopulate the cache138using the techniques described herein, and thus the power management unit146may trigger the prefetching process at X seconds before the predicted exit. In other embodiments, the specified time before the predicted exit may be proportional to the number of valid cache lines in the cache138before it is flushed. For example, if modeling or analysis reveals it takes X microseconds to repopulate a completely full cache138, then the specified time before the predicted exit may be set to Y=f(X*F), where F represents the ratio of valid lines to total cache lines of the cache138, or “fullness” of the cache138, at the time of flushing. Other techniques for determining this predetermined duration before the predicted exit time may be utilized in accordance with the guidelines provided herein.

As described above, the conventional approach to low power state exit transitions results in the cache being empty when a processor core exits the low power state to process an incoming interrupt or other idle mode exit trigger. This results in a significant cold start penalty whereby the initial data requests by the processor core result in cache misses due to the empty cache, and thus must instead be serviced by accesses to memory. This reliance on memory accesses to access data after resuming execution incurs a significant time penalty due to the relatively high latency of memory accesses compared to cache accesses. In contrast, the early triggering of cache prefetching (that is, initiating cache prefetching before the predicted exit of the low power state) at least partially repopulates the cache138with its previously cached data, and thus when an interrupt arrives to trigger the processor core to exit the low power state, the processor core will experience fewer, if any, cache misses, and thus will incur a much smaller cold start penalty, if any at all.

FIG. 2illustrates the power management unit146and the prediction unit148in greater detail in accordance with some embodiments. In the depicted example, the prediction unit148includes an activity monitor212coupled to receive indications of activity from the various processor cores131-133. The types of activity monitored by the activity monitor212may include (but are not limited to) instructions executed, instructions retired, memory requests, and so forth. The prediction unit148further includes a plurality of timers213. One timer213may be included for each of the functional blocks for which activity is to be monitored. Each of the timers213may be reset when activity is detected from its corresponding processor core by the activity monitor212. After being reset, a given timer213may begin tracking the time since the most recent activity. Each timer213may report the time since activity was most recently detected in its corresponding processor core. After the time since the most recent activity has reached a certain threshold for a given processor core, activity monitor212may indicate that the given core is idle. The activity monitor212further may continue to record the time that the processor core is idle, based on the time value received from the corresponding timer213, until the core resumes activity. As an alternative to implementing the activity monitor212, entry into an idle mode may be determined responsive to a halt instruction from the operating system executed by the processing device102. In general, any suitable mechanism can be used to determine if a processor core is idle, and such mechanisms may be implemented using hardware, software, or any combination thereof.

When a processor core has resumed activity after having been in the idle mode, the activity monitor212may record the duration of the idle mode in that core in event storage214. In the embodiment shown, the event storage214may store the duration for each of the most recent N instances of the idle mode, as idle mode times are being monitored for each of the processor cores. In one embodiment, the event storage214may include a plurality of first-in, first-out (FIFO) memories, one for each processor core. Each FIFO in the event storage214may store the duration of the most recent N instances of the idle mode for its corresponding processor core. As the durations of new instances of idle modes are recorded in a FIFO corresponding to a given core, the durations for the oldest idle mode instances may be overwritten.

Binning storage215(illustrated as a single joint storage with event storage214) stores, for each processor core, counts of idle mode durations in corresponding bins in order to generate a distribution of idle mode durations. The binning storage215may include logic to read the recorded durations from the event storage214and may generate the count values for each bin. As old duration data is overwritten by new duration with the occurrence of additional instances of the idle mode, the logic in the binning storage215may update the count values in the bins. Prediction logic218is coupled to the binning storage215. Based on the distribution of idle mode durations for a given processor core, predictor logic218generates a prediction as to the duration of the current idle mode. An example binning methodology and various example prediction methodologies used to generate the prediction based on the binning results are described in greater detail in reference to the aforementioned U.S. Patent App. Publication No. 2014/0181556.

In addition to predictions for the duration of the idle mode, predictor logic218may also generate indications for specified times at which low power states may be exited based on the idle mode duration predictions. For example, in one embodiment, if a processor core is placed in a sleep state (i.e. power and clock are both removed therefrom) during an instance of the idle mode, the power management unit146may cause that core to exit the sleep state at a specified time based on the predicted idle mode duration. This exit from the sleep state may be invoked without any other external event (e.g., an interrupt from a peripheral device) that would otherwise cause an exit from the sleep state. Moreover, the exit from the sleep state may be invoked before the predicted duration of the idle mode has fully elapsed. If the prediction of idle mode duration is reasonably accurate, the preemptive exit from the sleep state may provide various performance advantages. For example, the restoring of a previously stored state may be performed between the time of the exit from the sleep state and the resumption of the active mode, thus enabling the processor core to begin executing instructions faster than it might otherwise be able to do so in the case of a reactive exit from the sleep state. Further, the restoring of at least a portion of the data stored in the cache138likewise may be performed between the time of the exit from the sleep state and the resumption of the active mode, and thus enabling the processor core to rapidly access data from the cache138. Additional details regarding the preemptive exit from a low power state are provided below.

Predictions made by the predictor logic218may be forwarded to a decision unit205of the power management unit146. In the depicted embodiment, the decision unit205may use the prediction of idle mode time, along with other information, to determine whether to place an idle processor core in a low power state. Additionally, the decision unit205may determine what type of low power state the idle processor core is to be placed. For example, if the predicted idle duration is relatively short, the decision unit205may reduce power consumption by reducing the frequency of a clock signal provided to the processor core, reducing the voltage supplied to the processor core, or both. In another example, if the predicted idle duration is long enough such that it exceeds a break-even point, decision unit205may cause the idle processor core to be placed in a sleep state (one particular example of a low power state) in which neither power nor an active clock signal is provided to the core. Responsive to determining into which power state a processor core is to be placed, the decision unit205may provide power state information (“PWR_STATE”) to that core. A processor core receiving updated power state information from the decision unit205may perform various actions associated with entering the updated power state (e.g., a state save in the event that the updated power state information indicates that the processor core will be entering the low power state).

The power management unit146further includes a frequency control unit201and a voltage control unit202. The frequency control unit201operates to generate control the signals SetF[N:0] provided to the clock source120for adjusting the frequency of the clock signals provided to each of the processor cores. The frequency of a clock signal provided to a given one of processor cores may be adjusted independently of the clock signals provided to the other cores. The voltage control unit202operates to generate the control signal SetV[N:0] provided to the voltage regulator122for independently adjusting the respective supply voltages received by each of the processor core. Voltage control signals may be used to reduce a supply voltage provided to a given processor core, increase a supply voltage provided to that core, or to turn off that core by inhibiting it from receiving any supply voltage. Both the frequency control unit201and the voltage control unit202may generate their respective control signals based on information provided to them by the decision unit205.

FIGS. 3-5illustrate a low power state entry transition process (FIG. 4) and a low power state exit transition process (FIG. 5) with reference to an example entry/exit transition depicted byFIG. 3in accordance with some embodiments. In particular, the timeline300depicted inFIG. 3represents a sequence of events, or stages, occurring in the transition of a processor core into a low power state in response to the processor core entering an idle mode (entry transition process400ofFIG. 4), and then a transition of the processor core from the low power state to an active mode so as to process an incoming interrupt (exit transition process ofFIG. 5).

In response to detecting that a processor core has become idle at time t0, at block402the power management unit146employs a hysteresis countdown timer (not shown) to prevent premature entry into a low power state when there is a high frequency of interrupts, as depicted by stage301of timeline300. When the timer expires at time t1, the decision unit205of the power management unit146initiates the transition of the idle processor core to a low power state through configuration of a signal denoted PWR_STATE (FIG. 3). In response to this signaling, at block404the idle processor core prepares for the low power state by saving a copy of its architectural state to the memory104or to a cache level outside of the core's power domain, as illustrated by stage302of timeline300.

At block406, the cache population unit140prepares and stores cache restoration information to the memory104or to a cache level outside of the core's power domain, as illustrated by stage303of timeline300. The cache restoration information includes data or other information that is used by the cache population unit140to manage a cache prefetching process in order to repopulate the cache138in anticipation of the predicted exit from the low power state. As described in detail below with reference toFIGS. 6-8, this cache restoration information can include, for example, state information from the prefetcher142, tag array information from the cache138, history information representing a sequence of instruction pointers (IP) of instructions executed by the execution pipeline136leading up to the processor core's entry into the idle mode, and the like.

At block408, the processor core flushes the contents of its cache hierarchy sharing the same power domain as the idle processor core (e.g., cache138), as represented by stage304of timeline300. At this point, it should be noted that whileFIGS. 3 and 4illustrate an example sequence of the processes for saving the architectural state, saving the cache restoration information, and flushing the cache, these processes may be performed in an order that differs from that shown. With these preparations complete, at block410the power management unit146places the processor core into the low power state by one or both of power gating or clock gating the processor core, as illustrated by stage305beginning at time t2of timeline300.

Referring now to the exit transition process500ofFIG. 5, at block502the prediction unit148predicts the duration that the processor core will be in the idle mode before being transitioned back to an active mode by an interrupt or other waking triggers. As noted, the prediction unit148can use any of a variety of predictive exit techniques to predict this duration, such as the one described by the aforementioned U.S. Patent Application Publication No. 2014/0181556. In the illustrated example of timeline300, the duration is predicted to extend to time t6; that is, the predicted exit from the idle mode is time t6.

With the predicted idle mode duration information from the prediction unit148, at block504the power management unit146starts a countdown timer that is set to expire at a specified amount of time prior to the predicted exit from the low power state. As described above, this specified time prior to the predicted exit may be a fixed amount of time, an amount of time that is a function of a property of the valid data in the cache138at the time of entry into the low power mode, and the like. In the illustrated example, this specified time prior to the predicted exit is depicted as time t3. Thus, when the timer expires at time t3, the power management unit146ceases to power gate/clock gate the processor core and then signals the processor core to begin a restoration process to prepare for the anticipated transition to the active mode. Thus, in response to this signaling, at block506the processor core accesses the architectural state saved to the memory104and uses this information to restore the architectural state of the processor core, as illustrated by stage306of timeline300. Likewise, at block508the cache population unit140access the copy of the cache restoration information stored at the memory104, as illustrated by stage307of timeline300. At block510the cache population unit140uses this cache restoration information to coordinate with the prefetcher142and other components of the processor core to begin prefetching data from the memory104so as to repopulate the cache138with at least a portion of the data that was in the cache138when the processor core entered the idle mode, as illustrated by stage308of timeline300. Timeline300depicts stages307and308as overlapping to reflect that the early prefetching may start as each successive portion of the cache restoration information is accessed from the memory104.

In the particular example ofFIG. 3, an interrupt arrives at time t4, which is slightly prior to the predicted exit at time t6. Also in this example, the cache restoration process represented by stage308does not finish until time t5, which is slightly after the arrival of the interrupt at time t4. Thus, in this example, there is some possibility that an interrupt handling routine executed at stage309to handle the interrupt may request data yet to be restored to the cache138, and thus incur a cache miss and corresponding need for a memory access to obtain this data. As such, in this particular example, the processor core may experience a slight cold start penalty represented by the time between when the interrupt is received at time t4and the time that cache repopulation completes at time t5. However, this cold start penalty is significantly less than the cold start penalty that would be incurred in a conventional system, since the cache would be completely empty at the time of arrival of the interrupt at time t4, and thus a significant time would pass (well past time t5) before the cache would be repopulated with data following the interrupt arrival. Moreover, the example presented byFIG. 3represents an extreme case for purposes of illustration. In many instances, the timing of the cache repopulation process represented by stages307and308could be configured to ensure that the cache repopulation process will complete before an interrupt is received in most cases, thereby eliminating any cold start penalty.

FIGS. 6-8illustrate various example implementations of the cache restoration information utilized by the cache population unit140for early prefetching to restore the cache138in anticipation of exit from a low power state. As described above, the cache population unit140stores the cache restoration information to the memory104or to a higher level cache unaffected by the processor core entering the low power state when the processor core transitions to a low power state, and the cache population unit140then accesses this cache restoration information from the memory104or higher-level cache prior to a predicted exit from the low power state in order to restore at least a portion of the previously cached data back into the cache138. To restore the previously cached data, the memory addresses of the data are needed to perform a set of one or more load operations used to access this data from the memory104or a higher level cache for transfer to the cache138. In some embodiments, the cache restoration information directly represents the memory addresses for the previously cached information in some manner. In other embodiments, the cache restoration information represents state or other information that permits some or all of the memory addresses of the previously cached data to be indirectly determined, such as through a replay of instructions executed by the processor core immediately prior to its entry into the idle mode.

FIG. 6illustrates an example implementation of the cache restoration information as based on tag array information of the cache138. As with a typical cache, the cache138is composed of a tag array602and a data array604. The data array604has a plurality of cache lines, each cache line configured to store a corresponding segment of data from the memory104, and the tag array602has a plurality of tag lines, each tag line associated with a corresponding cache line and configured to store at least a portion of the memory address of the data stored in the corresponding cache line. As such, the address portions in the tag array602, in conjunction with the page tables stored and restored as part of the architectural state of the processor core, identify the memory addresses of the previously cached data. Accordingly, in at least one embodiment, when preparing to enter a low power state, the cache population unit140operates to store the tag array information606of the tag array602, or a representation thereof, as cache restoration information. As the data array604may have both valid data and invalid data, in some embodiments, the cache population unit140may filter the address data of the tag array602so as to store the address portions for only the valid lines of the cache138. Subsequently, when activated at a specified time prior to the predicted exit from the idle mode, the cache population unit140accesses the tag array information606from the memory104, and sequences through each address portion contained therein to determine a target memory address represented by the address portion, and controls the prefetcher142to initiate a load operation to prefetch the data stored at the target memory address (as translated in conjunction with the restored page tables) into the cache138.

FIG. 7illustrates an example implementation700of the cache restoration information as based on state information for the prefetcher142in accordance with some embodiments. In the course of operation, the state of the prefetcher142develops to reflect the data recently prefetched for an instruction stream and the data to soon be prefetched for this instruction stream. As such, the state of the prefetcher142at entry into an idle mode reflects at least a portion of the data cached in the cache138, as well as a portion of the data about to be cached in the cache138, at entry into the idle mode. Accordingly, in some embodiments, when preparing to enter a low power state, the cache population unit140operates to store some or all of prefetcher state information706as cache restoration information in memory104or in a higher level cache. To illustrate, the prefetcher142may track the addresses of frequently missed cache blocks that were accessed during a previous, but recent, low-power state exit. These blocks are highly likely to be used by the cores that transition from a low-power state (e.g., a C6 state) to the normal state (e.g., a C0 state). Thus, the data representing this tracking information (one example of the prefetcher state) may be used as the prefetcher state information706. As another example, the prefetcher142may track a “base” memory address and a detected stride in the memory accesses for each of one or more memory access streams, which are used by the prefetcher142to predict the next prefetch target address for each monitored stream. Thus, the prefetcher state information706may comprise this base address and stride information for one or more of the memory access streams.

In some embodiments, the prefetcher state is stored in conjunction with the other saved architectural state of the processor core during the low power mode transition, while in other embodiments the prefetcher state is stored separately. Subsequently, when activated at a specified time prior to the predicted exit from the idle mode, the cache population unit140accesses the prefetcher state information706from the memory104and restores the prefetcher142to the state represented by this cache restoration information. So restored, the prefetcher142is configured to commence prefetching at the point it left off upon transition into the low power mode. Accordingly, the prefetcher142begins performing a set of load operations so as to begin populating the cache138with data anticipated to be accessed in the instruction stream resumed upon the processor core's reentry into the active mode.

FIG. 8illustrates an example implementation800of the cache restoration information as configured to support a “dummy” replay of the instruction stream that led up to the entry into the low power state in accordance with some embodiments. As the cache138stores data that was accessed from the memory104(or higher level cache) through execution of load instructions in the instruction stream of the processor core, the load instructions executed by the execution pipeline136of the processor core leading up to the entry into the idle mode reflect at least a portion of the data cached in the cache138at the time of entry into the idle mode. Thus, the cache population unit140may operate to buffer instruction history information composed of a sliding window of a stream of instruction pointers (IPs) representing the instruction stream executed by the execution pipeline136. In response to the power management unit146signaling an imminent transition to a low power state, the cache population unit140stores the buffered IP stream segment (which represents the stream of instructions leading up to the low power state transition) as cache restoration information806in memory104or in a higher level cache. In some embodiments, the cache population unit140may filter the IP stream segment before storage so as to remove IPs representing instructions that ultimately have no bearing on the load instructions represented in the IP stream segment. Subsequently, when activated at a specified time prior to the predicted exit from the idle mode, the cache population unit140accesses the cache restoration information806from the memory104and triggers the execution pipeline136to replay the instruction stream run by the processor core immediately before entering the low power state by sequentially feeding to the execution pipeline136each IP of the IP stream segment represented by the cache restoration information806. Each load instruction represented in this IP stream segment triggers the prefetcher142to prefetch the corresponding data from the memory104and to store the resulting data in the cache138, and thus the replay of the IP stream segment results in at least a portion of the previously cached data being restored to the cache138and thus available for access upon the processor core's reentry into the active mode.

FIG. 9is a flow diagram illustrating an example method900for the design and fabrication of an IC device implementing one or more aspects in accordance with some embodiments. As noted above, the code generated for each of the following processes is stored or otherwise embodied in non-transitory computer readable storage media for access and use by the corresponding design tool or fabrication tool.

At block902a functional specification for the IC device is generated. The functional specification (often referred to as a micro architecture specification (MAS)) may be represented by any of a variety of programming languages or modeling languages, including C, C++, SystemC, Simulink, or MATLAB.

At block904, the functional specification is used to generate hardware description code representative of the hardware of the IC device. In some embodiments, the hardware description code is represented using at least one Hardware Description Language (HDL), which comprises any of a variety of computer languages, specification languages, or modeling languages for the formal description and design of the circuits of the IC device. The generated HDL code typically represents the operation of the circuits of the IC device, the design and organization of the circuits, and tests to verify correct operation of the IC device through simulation. Examples of HDL include Analog HDL (AHDL), Verilog HDL, SystemVerilog HDL, and VHDL. For IC devices implementing synchronized digital circuits, the hardware descriptor code may include register transfer level (RTL) code to provide an abstract representation of the operations of the synchronous digital circuits. For other types of circuitry, the hardware descriptor code may include behavior-level code to provide an abstract representation of the circuitry's operation. The HDL model represented by the hardware description code typically is subjected to one or more rounds of simulation and debugging to pass design verification.

After verifying the design represented by the hardware description code, at block906a synthesis tool is used to synthesize the hardware description code to generate code representing or defining an initial physical implementation of the circuitry of the IC device. In some embodiments, the synthesis tool generates one or more netlists comprising circuit device instances (e.g., gates, transistors, resistors, capacitors, inductors, diodes, etc.) and the nets, or connections, between the circuit device instances. Alternatively, all or a portion of a netlist can be generated manually without the use of a synthesis tool. As with the hardware description code, the netlists may be subjected to one or more test and verification processes before a final set of one or more netlists is generated.

Alternatively, a schematic editor tool can be used to draft a schematic of circuitry of the IC device and a schematic capture tool then may be used to capture the resulting circuit diagram and to generate one or more netlists (stored on a computer readable media) representing the components and connectivity of the circuit diagram. The captured circuit diagram may then be subjected to one or more rounds of simulation for testing and verification.

At block908, one or more EDA tools use the netlists produced at block906to generate code representing the physical layout of the circuitry of the IC device. This process can include, for example, a placement tool using the netlists to determine or fix the location of each element of the circuitry of the IC device. Further, a routing tool builds on the placement process to add and route the wires needed to connect the circuit elements in accordance with the netlist(s). The resulting code represents a three-dimensional model of the IC device. The code may be represented in a database file format, such as, for example, the Graphic Database System II (GDSII) format. Data in this format typically represents geometric shapes, text labels, and other information about the circuit layout in hierarchical form.

At block910, the physical layout code (e.g., GDSII code) is provided to a manufacturing facility, which uses the physical layout code to configure or otherwise adapt fabrication tools of the manufacturing facility (e.g., through mask works) to fabricate the IC device. That is, the physical layout code may be programmed into one or more computer systems, which may then control, in whole or part, the operation of the tools of the manufacturing facility or the manufacturing operations performed therein.