Optical waveguide apparatus and method of fabrication thereof

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

BACKGROUND

Optical waveguides, which confine and guide electromagnetic waves, are used as components in integrated optical circuits that provide various photonic functions. Integrated optical waveguides typically provide functionality for signals imposed on optical wavelengths in the visible or infrared spectrum and, with sub-micron dimensions, have even been observed to provide functionality for signals imposed on optical wavelengths in the infrared spectrum. However, thermo-optic coefficients of conventional optical waveguides make them extremely sensitive to temperature variations, which can result in malfunction of integrated optical circuits. Though new materials having lower thermo-optic coefficients are being explored for optical waveguides, it has been observed that to achieve desired confinement and guiding applications, optical waveguides made from the new materials often require design changes (e.g., increasing dimensions and/or sizes) to the optical circuits in which the optical waveguides are integrated. Improvements in optical waveguides and fabrication of optical waveguides are thus needed to meet IC scaling demands.

DETAILED DESCRIPTION

Optical waveguides, which confine and guide electromagnetic waves, are used as components in integrated optical circuits that provide various photonic functions. Integrated optical waveguides typically provide functionality for signals imposed on optical wavelengths in the visible or infrared spectrum and, with sub-micron dimensions, have even been observed to provide functionality for signals imposed on optical wavelengths in the infrared spectrum. However, thermo-optic coefficients of conventional optical waveguides make them extremely sensitive to temperature variations, which can result in malfunction of integrated optical circuits. Though new materials having lower thermo-optic coefficients are being explored for optical waveguides, it has been observed that to achieve desired confinement and guiding applications, optical waveguides made from the new materials often require design changes (e.g., increasing dimensions and/or sizes) to the optical circuits in which the optical waveguides are integrated, resulting in increase of fabrication cost. Improvements in optical waveguides and fabrication of optical waveguides are thus needed to meet IC scaling demands.

For example, photonics devices for data-communication and tele-communication application employ light with a wavelength of 1310 nm (O-band) and 1550 nm (C-band), respectively. Silicon waveguides with sub-micron dimensions are able to confine infrared light (i.e., λ>700 nm) due to its strong refractive index contrast to its cladding layer, which may be formed of silicon oxide. The refractive index of silicon is about 3.47 while the refractive index of silicon oxide is about 1.45. Using silicon as waveguide materials is not without its challenges. As silicon has a high thermo-optic coefficient (dn/dT>2.5×10−4K−1), silicon is sensitive to temperature variation. In some cases, temperature changes may result in malfunction of silicon photonic devices. To combat the temperature sensitivity issues, silicon optical wave guide devices may require thermal tuning by use of a thermal heater or a feedback control mechanism. Such thermal tuning may be only one direction and require overhead margins as the temperature can only be increased, not decreased. Various low-thermo-optic coefficient materials have been proposed to be incorporated into temperature-sensitive optical devices. Silicon nitride is a low-thermo-optic coefficient material. Silicon nitride has a thermo-optic coefficient about 1.7×10−5K−1, which is about one order of magnitude lower than that of silicon. Efficient light coupling between silicon photonics chip and silicon nitride waveguide may be implemented using spot size converters (i.e. optical edge couplers). Silicon nitride has a much lower refractive index between about 1.86 and 2.0 than silicon. For that reason, the thickness of a silicon nitride waveguide needs to be more than about 400 nm and about 600 nm to confine light in O-band (1310 nm) and C-band (1550 nm) applications. Additionally, to couple a silicon waveguide and a silicon nitride waveguide, the silicon waveguide and the silicon nitride have to be spaced apart by a spacing determined by the wavelength. For 0-band and C-band applications, the spacing is about 200 nm. As the required thickness of silicon nitride waveguide and the required waveguide-to-waveguide spacing may not fit well with existing structure, implementation of silicon nitride waveguides in O-band or C-band applications may involve structural changes, which may be costly and undesirable. Implementation of silicon nitride waveguides allows improved routability and ready fabrication of silicon nitride ring oscillators, optical couplers, optical splitters, and optical combiners.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIGS.1,35,44, and66are flowcharts illustrating methods100,300,400, and500of forming a semiconductor device from a workpiece according to embodiments of the present disclosure. Methods100,300,400, and500are merely examples and are not intended to limit the present disclosure to what is explicitly illustrated in methods100,300,400, and500. Additional steps can be provided before, during and after the methods100,300,400, and500, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the methods. Not all steps are described herein in detail for reasons of simplicity. Methods100,300,400and500are described below in conjunction withFIGS.2-34,36-43,45-65, and67-68, which are fragmentary cross-sectional views of a workpiece200at different stages of fabrication according to embodiments of methods100,300,400, and500. Because the workpiece200is to be formed into an apparatus or a semiconductor structure after the fabrication processes, the workpiece200may also be referred an apparatus200or a semiconductor structure200. Additionally, throughout the present disclosure, like reference numerals are used to denote like features, unless otherwise excepted.

Referring toFIGS.1and2, method100includes a block102where a workpiece200is provided. As shown inFIG.2, the workpiece200includes a substrate202, a buried oxide (BOX) layer204on the substrate202, and a semiconductor layer205on the buried oxide layer204. In one embodiment, the substrate202may be a silicon (Si) substrate. In some other embodiments, the substrate202may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The BOX layer204may include silicon oxide and the semiconductor layer205may include silicon (Si). In some implementations where the substrate202and the semiconductor layer205are formed of silicon (Si) and the BOX layer204is formed of silicon oxide, the substrate202, the BOX layer204, and the semiconductor layer205may be portions of a silicon-on-insulator (SOI) substrate.

Referring toFIGS.1and3-4, method100includes a block104where trenches212are formed in the semiconductor layer205to define silicon features206. To define the silicon features206, a first patterned hard mask208is formed over the semiconductor layer205as shown inFIG.3. The first patterned hard mask208may be a single layer or a multi-layer and may include silicon oxide, silicon nitride, or a combination thereof. In an example process, a hard mask layer is blanketly deposited on the semiconductor layer205and is then patterned using photolithography and etch processes to form the first patterned hard mask208. Referring toFIG.4, the semiconductor layer205is etched using the first patterned hard mask208as an etch mask to form the trenches212that define the silicon features206. In some embodiments, the etching at block104may include dry etching, reactive ion etching (RIE), and/or other suitable processes. As shown inFIG.4, the silicon features206are disposed on the BOX layer204and are separated from one another by trenches212. In some alternative embodiments illustrated inFIG.68, a ridge-type or rib-type silicon features2060may be formed. A method500to form the ridge-type silicon feature2060will be described below.

Referring toFIGS.1and5, method100includes a block106where a fill dielectric layer214is deposited over the workpiece200. The fill dielectric layer214may include silicon oxide or silicon-oxide-containing dielectric material. In some embodiments, the fill dielectric layer214may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials and may be deposited using spin-on coating or flowable chemical vapor deposition (FCVD). In some other embodiments, the fill dielectric layer214may include silicon oxide and may be deposited using CVD, plasma-enhanced CVD (PECVD), or other suitable process. After the deposition of the fill dielectric layer214, the workpiece200may be subject to a planarization process, such as a chemical mechanical polishing (CMP) process. After the planarization process, the silicon features206may remain covered by the fill dielectric layer214, as shown inFIG.5.

Referring toFIGS.1and6-7, method100includes a block108where doped silicon features218are formed to interleave first waveguide features206. Doped silicon features218provide electrical connection between electrical signal and the optical component when active waveguides are desired. Operations at block108determine whether a silicon feature206may be doped to become a doped silicon feature218or remain a silicon feature206to serve as the first waveguide features206. Because a silicon feature206not doped at block108will serve as a waveguide, they may also be referred to a first waveguide feature206from block108forward. Block108forms a first implantation mask216(shown inFIG.6) to expose a predetermined group of silicon features206and implements a first doping process1100(shown inFIG.7) to selectively dope the predetermined group of silicon features206with an n-type dopant (such as phosphorus (P) or arsenic (As)) or a p-type dopant (such as boron (B) or boron difluoride (BF2)), as required by the design of the apparatus200. In some embodiments, the first implantation mask216may include silicon, silicon oxide, silicon nitride, a metal, a metal nitride, a metal oxide, or a metal silicide. In some alternative embodiments, the first implantation mask216may be a soft mask that includes polymeric materials. As shown inFIG.7, the first doping process1100forms doped silicon features218that interleave the silicon features206covered by the first implantation mask216. That is, each first waveguide feature206is adjacent to one or two doped silicon features218. In some instances, because the first implantation mask216does not block all the ions from the first doping process1100, the first waveguide features206may be partially doped near their top surfaces. In some embodiments, an anneal process may be performed to activate the dopants in the doped silicon features218. After the first doping process1100, the first implantation mask216is removed.

Referring toFIGS.1and8, method100includes a block110where an interlayer dielectric (ILD) layer220is formed over the workpiece200. The ILD layer220may include silicon oxide or silicon-oxide-containing dielectric material. In some embodiments, the ILD layer220may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials and may be deposited using spin-on coating or flowable chemical vapor deposition (FCVD). In some other embodiments, the ILD layer220may include silicon oxide and may be deposited using CVD, plasma-enhanced CVD (PECVD), or other suitable process. In some instances, the ILD layer220may have a thickness (along the Z direction) between about 250 nm and about 350 nm.

Referring toFIGS.1and9-11, method100includes a block112where contact features228are formed to couple to the doped silicon features218. In an example process, openings224are formed in the ILD layer220to expose the doped silicon features218, as shown inFIG.9. To form the openings224, a second patterned hard mask222is formed over the ILD layer220. Because the formation and composition of the second patterned hard mask222may be similar to those of the first patterned hard mask208, detailed description of the second patterned hard mask222is omitted for brevity. Still referring toFIG.9, the ILD layer220is then etched using the second patterned hard mask222as an etch mask until the doped silicon features218are exposed in the openings224. Reference is made toFIG.10. With the doped silicon features218exposed, a silicide layer226is formed on the exposed silicon features218. In an example process, a metal precursor is deposited over the workpiece200and an anneal process is performed to bring about silicidation between the metal precursor and the doped silicon features218to form the silicide layer226. A suitable metal precursor may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The silicide layer226may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). In some implementations, the metal precursor that is not converted to the silicide layer226may be selectively removed. The silicide layer226functions to reduce contact resistance to the doped silicon features218. After the formation of the silicide layer226, a metal fill layer may be deposited into the openings224on the silicide layer226. The metal fill layer may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). A planarization process may follow to remove excess metal fill layer over the first ILD layer220, thereby forming the contact features228in the first ILD layer220, as shown inFIG.11. In some instances, the contact features228may have a thickness (along the Z direction) between about 350 nm and about 380 nm. Depending on the design, while some contact features228are physically disposed on and electrically coupled to underlying doped silicon features218, some contact features228are not coupled to any doped silicon features218and are electrically floating. Such an electrically floating contact feature228may be referred to as a dummy contact feature.FIG.11illustrates a dummy contact feature228D. The contact features228and dummy contact features228D are situated in a first interconnect layer over doped silicon features218. The dummy contact features228D are either inserted into isolated areas (where there are less contact features) to reduce process loading effect or are inserted as isolation structures. The dummy contact features228D do not perform any circuit functions and may be electrically floating. After the formation of the contact features228and the dummy contact features228D, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to provide a planar top surface. After the CMP process, top surfaces of the first ILD layer220, the contact features228, and the dummy contact features228D are coplanar.

Referring toFIGS.1and12, method100includes a block114where a first intermetal dielectric (IMD) layer230is deposited over the workpiece200. The first IMD layer230may include silicon oxide or silicon-oxide-containing dielectric material. In some embodiments, the first IMD layer230may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials and may be deposited using spin-on coating or flowable chemical vapor deposition (FCVD). In some other embodiments, the first IMD layer230may include silicon oxide and may be deposited using CVD, plasma-enhanced CVD (PECVD), or other suitable process. In some instances, the first IMD layer230may have a thickness (along the Z direction) between about 180 nm and about 200 nm. As shown inFIGS.11and12, the first IMD layer230is disposed on the first ILD layer220, the contact features228and the dummy contact features228D.

Referring toFIGS.1and13-17, method100includes a block116where lower metal features238are formed over the contact features228. Operations at block116may include formation of a third hard mask layer232(shown inFIG.13), patterning the third hard mask layer232and etching the first IMD layer230(shown inFIG.14), removal of the patterned hard mask232(shown inFIG.15), depositing a metal fill layer236over the workpiece200(shown inFIG.16), and planarizing the workpiece200to form the lower metal features238(shown inFIG.17). Referring toFIGS.13and14, the third hard mask layer232is deposited over the workpiece200and patterned to form the third patterned hard mask232. As the formation and composition of the third patterned hard mask232are similar to those of the first patterned hard mask208, detailed description of the third patterned hard mask232is omitted for brevity. InFIG.14, the third patterned hard mask232is applied as an etch mask to etch the first IMD layer230to expose the contact features228(as well as dummy contact feature228D) in openings234. The third patterned hard mask232is then removed by a dry etch process selective to the third patterned hard mask232, as shown inFIG.15. Referring toFIG.16, a metal fill layer236is deposited over the workpiece200, including over the openings234. The metal fill layer236may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). Referring toFIG.17, a planarization process is then performed to remove excess metal fill layer236over the first IMD layer230to form the lower metal features238in the first IMD layer230. A lower metal feature238disposed over and coupled to a dummy contact feature228D does not serve any circuit function and may be referred to as a dummy lower metal feature238D. The lower metal features238and dummy lower metal features238D are situated in a second interconnect layer over the first interconnect layer where contact features228are situated. The dummy lower metal features238D are either inserted into isolated areas (where there are less lower metal features) to reduce process loading effect or are inserted as isolation structures. The dummy lower metal features238D do not perform any circuit functions and may be electrically floating.

Referring toFIGS.1and18-23, method100includes a block118where second waveguide features are formed between adjacent lower metal features238and adjacent contact features228. Operations at block118include deposition of a second IMD layer240(shown inFIG.18), formation of a fourth patterned hard mask242(shown inFIG.19), formation of waveguide trenches244in the ILD layer220, the first IMD layer230and the second IMD layer240(shown inFIG.20), removal of the fourth patterned hard mask242(shown inFIG.21), deposition of a waveguide material246over the workpiece200(shown inFIG.22), and planarization of the workpiece200to form second waveguide features248(shown inFIG.23). Referring toFIG.18, the second IMD layer240is blanketly deposited over the workpiece200. As the deposition and composition of the second IMD layer240are similar to those of the first IMD layer230, detailed description of the second IMD layer240is omitted for brevity. As shown inFIG.19, the fourth patterned hard mask242is formed over the workpiece200. The formation and composition of the fourth patterned hard mask242may be similar to those of the first patterned hard mask208. Detailed description of the fourth patterned hard mask242is therefore omitted for brevity. The fourth patterned hard mask242includes openings243directly over first waveguide features206while covering the lower metal features238. Referring toFIG.20, the fourth patterned hard mask242is applied as an etch mask to etch the second IMD layer240, the first IMD layer230, and the ILD220to form waveguide trenches244. In the depicted embodiment, the waveguide trenches244do not extend through the ILD220or the fill dielectric layer214. That is, the first waveguide features206are not exposed in the waveguide trenches244. As shown inFIG.21, the workpiece200is subject to an etch back process to remove the fourth patterned hard mask242. With the fourth patterned hard mask242removed, the waveguide material246is deposited over the workpiece200, including over the waveguide trenches244, as illustrated inFIG.22. The waveguide material246includes silicon nitride and may be deposited using CVD, FCVD, PECVD, spin-on coating, or a suitable method. Referring toFIG.23, a planarization process, such a chemical mechanical polishing (CMP) process, may be performed to remove excess waveguide material over the second IMD layer240, thereby forming and defining the second waveguide features248.

Referring toFIGS.1and24-26, method100includes a block120where a third IMD layer250, an etch stop layer (ESL)252, and a fourth IMD layer254are deposited over the workpiece200. Operations at block120include deposition of the third IMD layer250(shown inFIG.24), deposition of the ESL252over the third IMD layer250(shown inFIG.25), and deposition of the fourth IMD layer254over the ESL252(shown inFIG.26). Referring toFIG.24, the third IMD layer250is deposited over the workpiece200, including over the second waveguide features248and the second IMD layer240. As the deposition and composition of the third IMD layer250are similar to those of the first IMD layer230, detailed description of the third IMD layer250is omitted for brevity. Then, as shown inFIG.25, the ESL252is deposited over the third IMD layer250. The ESL252may include silicon nitride, silicon oxynitride, and/or other suitable dielectric material and may be formed by CVD, ALD, PECVD, or other suitable deposition techniques. Referring toFIG.26, the fourth IMD layer254is then deposited over the ESL252. As the deposition and composition of the fourth IMD layer254are similar to those of the first IMD layer230, detailed description of the fourth IMD layer254is omitted for brevity.

Referring toFIGS.1and27-34, method100includes a block122where upper metal features263and via features264are formed over the lower metal features238. Operations at block122include formation of a fifth patterned hard mask256(shown inFIG.27), etching through the fifth patterned hard mask256to expose the lower metal features238(shownFIG.28), removal of the fifth patterned hard mask256(shown inFIG.29), deposition of a sixth hard mask layer260(shown inFIG.30), patterning the sixth hard mask layer260to form the sixth patterned hard mask260(shown inFIG.31), etching the fourth IMD layer254(shown inFIG.32), depositing a metal fill layer262(shown inFIG.33), and planarization of the workpiece200to form upper metal features263and via features264(shown inFIG.34).

Referring toFIG.27, the fifth patterned hard mask256is deposited over the fourth IMD layer254. The formation and composition of the fifth patterned hard mask256may be similar to those of the first patterned hard mask208. Detailed description of the fifth patterned hard mask256is therefore omitted for brevity. The fifth patterned hard mask256covers areas over the second waveguide features248but exposes areas over the lower metal features238. With the fifth patterned hard mask256serving as the etch mask, the fourth IMD layer254, the ESL252, and the third IMD layer250, and the second IMD layer240are etched using a dry etch process to expose the lower metal features238in openings258, as shown inFIG.28. Referring toFIG.29, the fifth patterned hard mask256is removed by a dry etch process that etches the lower metal features238at a slower rate than it does the fifth patterned hard mask256. Reference is then made toFIG.30, which illustrates that the sixth hard mask260is conformally deposited over the workpiece200, including over the openings258. Then, as shown inFIG.31, the sixth hard mask260is patterned to form sixth patterned hard mask260. The formation and composition of the sixth patterned hard mask260may be similar to those of the first patterned hard mask208. Detailed description of the sixth patterned hard mask260is therefore omitted for brevity. As shown inFIG.31, the sixth patterned hard mask260includes upper portions on top surfaces of the fourth IMD layer254and lower portions on the lower metal features238. Widths of the upper portions are smaller than widths of the top surfaces of the fourth IMD layer254. That is, the upper portions are not coterminous with the top surfaces of the fourth IMD layer254and edge portions of the fourth IMD layer254are not covered by the sixth patterned hard mask260.

Referring toFIG.32, with the sixth patterned hard mask260serving as an etch mask, the fourth IMD layer254is etched to trim the edge portions until the ESL252is exposed. As a result, along the X direction, a width of the fourth IMD layer254is smaller than a width of the ESL252. As shown inFIG.32, at this point, hybrid contact openings259are formed through the fourth IMD layer254, the ESL252, the third IMD layer250, and the second IMD layer240. Each of the hybrid contact openings259includes a lower portion259L and an upper portion259U over the lower portion259L. Because of the removal of the edge portions of the fourth IMD layer254, the upper portion259U is wider than the lower portion259L along the X direction. Reference is made toFIG.33. A metal fill layer262is deposited over the workpiece200, including over the hybrid contact openings259. The metal fill layer262may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN) and may be deposited using PVD. Referring toFIG.34, a planarization process is then performed to remove excess metal fill layer262over the fourth IMD layer254to form upper metal features263in the lower portions259L and via features264in the upper portions259U.

An upper metal feature263disposed over and coupled to a dummy lower metal feature238D does not serve any circuit function and may be referred to as a dummy upper metal feature263D. Similarly, a via feature264disposed over and coupled to a dummy upper metal feature263D does not serve any circuit function and may be referred to as a dummy via feature264D. The upper metal features263and dummy upper metal features263D are situated in a third interconnect layer over the second interconnect layer where the lower metal features238are situated. The via features264and dummy via features264D are situated in a fourth interconnect layer over the third interconnect layer where the upper metal features263are situated. The dummy via features264D are either inserted into isolated areas (where there are less via features) to reduce process loading effect or are inserted as isolation structures. The dummy via features264D do not perform any circuit functions and may be electrically floating.

In some embodiments, second waveguide features248may be patterned using the method300inFIG.35to form tip portions. Such tip portions allow the second waveguide features248to efficiently coupled to the firm waveguide feature. Embodiments of method300are described below in conjunction withFIGS.37-44.

Referring toFIGS.35and36, method300includes a block302where a workpiece200prepared by following blocks102-118of method100is received. At block302, method300may begin with a workpiece200that has gone through operations in blocks102-118. As shown theFIG.36, the workpiece200received at block302includes the substrate202, the BOX layer204, doped silicon features218disposed on the BOX layer204, and first waveguide features206on the BOX layer204. The workpiece200includes contact features228coupled to the doped silicon features218by way of the silicide layer226. Lower metal features238, which are disposed in the first IMD layer230and the second IMD layer240, are formed on the contact features228. Second waveguide features248are disposed between two adjacent contact features228as well as between two adjacent lower metal features238. Each of the second waveguide features248is spaced apart from adjacent contact features228by the ILD layer220and is spaced part from adjacent lower metal features238by the first IMD layer230.

Referring toFIGS.35and36, method300includes a block304where a seventh patterned hard mask270is formed to expose a second waveguide feature248. Like the first patterned hard mask208, the seventh patterned hard mask270may be a single layer or a multi-layer and may include silicon oxide, silicon nitride, or a combination thereof. In an example process, a hard mask layer is blanketly deposited on the second IMD layer240and the second waveguide features248and is then patterned using photolithography and etch processes to form the seventh patterned hard mask270. As shown inFIG.36, the seventh patterned hard mask270exposes at least one of the second waveguide features248and covers the rest of the workpiece200.

Referring toFIGS.35,37and38, method300includes a block306where the exposed second waveguide feature2480is recessed. With the seventh patterned hard mask270serving as an etch mask, the at least one of the second waveguide features2480exposed in the seventh patterned hard mask270is recessed, as shown inFIG.37. In embodiments where the second waveguide features2480are formed of silicon nitride, the recess at block306may be selective to silicon nitride. The recess at block306may reduce the thickness of the second waveguide feature2480to between about 100 nm and about 300 nm, thereby forming the recessed second waveguide feature2480. As shown inFIG.38, after the formation of the recessed second waveguide feature2480, the seventh patterned hard mask270is removed by etching.

Referring toFIGS.35and39-42, method300includes a block308where the recessed second waveguide feature2480is patterned to form a tip portion2482. Operations at block308include formation of an eighth patterned hard mask272(shown inFIGS.39and40), etching of the recessed second waveguide feature2480to form a tip portion (shown inFIGS.41and42). Referring toFIG.39, an eighth hard mask layer272is conformally deposited over the workpiece200, including over the second IMD layer240and the recessed second waveguide feature2480. The eighth hard mask layer272is then patterned to form the eighth patterned hard mask272, as shown inFIG.40. The formation and composition of the eighth patterned hard mask272may be similar to those of the seventh patterned hard mask270. Detailed description of the eighth patterned hard mask272is therefore omitted for brevity. Using the eighth patterned hard mask272as an etch mask, the recessed second waveguide feature2480is trimmed to form the tip portion2482, as shown inFIG.41. While the tip portion2482remains disposed over the underlying first waveguide feature206, the tip portion2482is narrower than the second waveguide feature2480and is farther away from adjacent contact features228. InFIG.42, the eighth patterned hard mask272is removed by etching.

Referring toFIGS.35and43, method300includes a block310where a fifth IMD layer274is deposited over the workpiece200. As shown inFIG.43, the fifth IMD layer274is deposited over the workpiece200to cover the tip portion2482. The fifth IMD layer274may include silicon oxide or silicon-oxide-containing dielectric material. In some embodiments, the fifth IMD layer274may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials and may be deposited using spin-on coating or flowable chemical vapor deposition (FCVD). In some other embodiments, the fifth IMD layer274may include silicon oxide and may be deposited using CVD, plasma-enhanced CVD (PECVD), or other suitable process.

In some embodiments, the first waveguide feature206may be coupled to an active device using the method400inFIG.44. Embodiments of method400are described below in conjunction withFIGS.45-65.

Referring toFIGS.44and45, method100includes a block402where a workpiece200is provided. Similar to what is shown inFIG.2, the workpiece200inFIG.45includes a substrate202, a buried oxide (BOX) layer204on the substrate202, and a semiconductor layer205on the buried oxide layer204. In one embodiment, the substrate202may be a silicon (Si) substrate. In some other embodiments, the substrate202may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The BOX layer204may include silicon oxide and the semiconductor layer205may include silicon (Si). In some implementations where the substrate202and the semiconductor layer205are formed of silicon (Si) and the BOX layer204is formed of silicon oxide, the substrate202, the BOX layer204, and the semiconductor layer205may be portions of a silicon-on-insulator (SOI) substrate.

Referring toFIGS.44and45-46, method400includes a block404where a first silicon feature2061, a second silicon feature2062, and a third silicon features2063are formed. Operations at block404include forming shallow trenches210that do not extend through the semiconductor layer205(shown inFIG.45) and formation of the first silicon feature2061, the second silicon feature2062and the third silicon feature2063(shown inFIG.46). In some embodiments represented inFIG.45, the formation of the shallow trenches210includes etching the semiconductor layer205through the first patterned hard mask208described above with respect to method100. While a similar etch process is performed to etch the semiconductor layer205at block404, the etch process lasts a shorter period of time such that the shallow trenches210does not extend through the semiconductor layer205to expose the BOX layer204. While not explicitly shown in the figures, another patterned hard mask may be formed for further patterning the semiconductor layer205to form the first silicon feature2061, the second silicon feature2062, and the third silicon feature2063that are connected by the leftover base semiconductor layer205B. In the depicted embodiment, the patterning at block404may also form one or more silicon features206. The etch process at block404may include dry etching, reactive ion etching (RIE), and/or other suitable processes. As shown inFIG.46, after the formation of the first silicon feature2061, the second silicon feature2062, and the third silicon feature2063, the fill dielectric layer214is deposited over the workpiece200to form the shallow trenches210and trenches212(not shown inFIG.45, but shown inFIG.4). The fill dielectric layer214may be planarized to provide a planar top surface.

Referring toFIGS.44and47-49, method400includes a block406where a second doping process1200is selectively performed to a portion of the second silicon feature2062and the third silicon feature2063. At block406, a second implantation mask215is formed over the fill dielectric layer214to expose a portion of the second silicon feature2062and the third silicon feature2063, while another portion of the second silicon feature2062and the first silicon feature2061remain protected by the second implantation mask215, as shown inFIG.47. Thereafter, with the second implantation mask215in place, the second doping process1200is performed to the workpiece200to selectively implant the exposed portion of the second silicon feature2062and the exposed third silicon features2063, as illustrated inFIG.48. In some embodiments, the second doping process1200implants an n-type dopant, such as phosphorus (P) or arsenic (As) at a first dose. The second implantation mask215may be similar to the first implantation mask216in terms of formation and composition. After the second doping process1200, the second implantation mask215is removed. As shown inFIG.49, the second doping process1200forms a first n-doped region217.

Referring toFIGS.44and50-52, method400includes a block408where a third doping process1300is selectively performed to the third silicon feature2063. At block408, a third implantation mask219is formed over the fill dielectric layer214to expose the third silicon feature2063and a portion of the fill dielectric layer214between the second silicon feature2062and the third silicon feature2063. The second silicon feature2062and the first silicon feature2061remain protected by the third implantation mask219, as shown inFIG.50. Thereafter, with the third implantation mask219in place, the third doping process1300is performed to the workpiece200to selectively implant the exposed third silicon features2063, as illustrated inFIG.51. In some embodiments, the third doping process1300implants an n-type dopant, such as phosphorus (P) or arsenic (As) at a second dose greater than the first dose. The third implantation mask219may be similar to the first implantation mask216in terms of formation and composition. After the third doping process1300, the third implantation mask219is removed, as shown inFIG.52. As shown inFIG.52, the third doping process1300transform a portion of the first n-doped region217into a second n-doped region221. The n-type dopant concentration in the second n-doped region221is greater than that in the first n-doped region217.

Referring toFIGS.44and53-55, method400includes a block410where a fourth doping process1400is selectively performed to the third silicon feature2063. At block410, a fourth implantation mask223is formed over the fill dielectric layer214to expose the third silicon feature2063alone. The second silicon feature2062, the first silicon feature2061, and the fill dielectric layer214remain protected by the fourth implantation mask223, as shown inFIG.53. Thereafter, with the fourth implantation mask223in place, the fourth doping process1400is performed to the workpiece200to selectively implant the exposed third silicon features2063, as illustrated inFIG.54. In some embodiments, the fourth doping process1400implants an n-type dopant, such as phosphorus (P) or arsenic (As) at a third dose greater than the second dose. The fourth implantation mask223may be similar to the first implantation mask216in terms of formation and composition. After the fourth doping process1400, the fourth implantation mask223is removed, as shown inFIG.55. As shown inFIG.55, the fourth doping process1400transform a portion of the second n-doped region221into a third n-doped region225. The n-type dopant concentration in the third n-doped region225is greater than that in the second n-doped region221.

Referring toFIGS.44and56-58, method400includes a block412where a fifth doping process1500is selectively performed to a portion of the second silicon feature2062and the first silicon feature2061. At block412, a fifth implantation mask227is formed over the fill dielectric layer214to expose the first silicon feature2061and another portion of the second silicon feature2062. The doped portion of the second silicon feature2062and the third silicon feature2063remain protected by the fifth implantation mask227, as shown inFIG.56. Thereafter, with the fifth implantation mask227in place, the fifth doping process1500is performed to the workpiece200to selectively implant the exposed first silicon features2061and the exposed portion of the second silicon feature2062, as illustrated inFIG.57. In some embodiments, the fifth doping process1500implants a p-type dopant, such as boron (B) or boron difluoride (BF2) at a fourth dose. The fifth implantation mask227may be similar to the first implantation mask216in terms of formation and composition. After the fifth doping process1500, the fifth implantation mask227is removed, as shown inFIG.58. As shown inFIG.58, the fifth doping process1500forms a first p-doped region229.

Referring toFIGS.44and59-61, method400includes a block414where a sixth doping process1600is selectively performed to the first silicon feature2061. At block414, a sixth implantation mask231is formed over the fill dielectric layer214to expose the first silicon feature2061and a portion of the fill dielectric layer214between the first silicon feature2061and the second silicon feature2062. The second silicon feature2062and the third silicon feature2063remain protected by the sixth implantation mask231, as shown inFIG.59. Thereafter, with the sixth implantation mask231in place, the sixth doping process1600is performed to the workpiece200to selectively implant the exposed first silicon features2061, as illustrated inFIG.60. In some embodiments, the sixth doping process1600implants a p-type dopant, such as boron (B) or boron difluoride (BF2) at a fifth dose greater than the fourth dose. The sixth implantation mask231may be similar to the first implantation mask216in terms of formation and composition. After the sixth doping process1600, the sixth implantation mask231is removed, as shown inFIG.61. As shown inFIG.61, the sixth doping process1600transforms a portion of the first p-doped region229into a second p-doped region233. The p-type dopant concentration in the second p-doped region233is greater than that in the first p-doped region229.

Referring toFIGS.44and62-64, method400includes a block416where a seventh doping process1700is selectively performed to the first silicon feature2061. At block416, a seventh implantation mask235is formed over the fill dielectric layer214to expose the first silicon feature2061alone. The second silicon feature2062and the third silicon feature2063remain protected by the seventh implantation mask235, as shown inFIG.62. Thereafter, with the seventh implantation mask235in place, the seventh doping process1700is performed to the workpiece200to selectively implant the exposed first silicon features2061, as illustrated inFIG.63. In some embodiments, the seventh doping process1700implants a p-type dopant, such as boron (B) or boron difluoride (BF2) at a sixth dose greater than the fifth dose. The seventh implantation mask235may be similar to the first implantation mask216in terms of formation and composition. After the seventh doping process1700, the seventh implantation mask235is removed, as shown inFIG.64. As shown inFIG.64, the seventh doping process1700transforms a portion of the second p-doped region233into a third p-doped region237. The p-type dopant concentration in the third p-doped region237is greater than that in the second p-doped region233.

Upon conclusion of the operations at block416, an active device1000is formed. The active device1000includes the first n-doped region217, the first p-doped region229, the second n-doped region221, the second p-doped region233, third n-doped region225, and the third p-doped region237. The active device1000serves as a phase modulator to control a bias voltage applied across a first waveguide feature206coupled to the active device1000. In that regard, the active device1000may also be referred to as a phase modulator1000. The third n-doped region225and the third p-doped region237are heavily doped to function as low-resistance contacts of the phase modulator1000. When activated, the phase modulator1000may modulate the refractive index of the first waveguide feature206coupled thereto. An alternative phase modulator1002is illustrated inFIGS.75and76. Compared the phase modulator1002, the alternative phase modulator1002further includes a substantially undoped region (a portion of the second silicon feature2062) disposed between the first n-doped region217and the first p-doped region229. The phase modulator1000includes a P-N junction and is configured to depletion mode operation where charge carriers are depleted. The alternative phase modulator1002includes a P-I-N (I for intrinsic) junction and is configured for accumulation mode operations where charge carriers are pooled in the undoped region. Because charge carrier densities may affect the refractive index of the waveguide, the phase modulator1000or the alternative phase modulator1002may modulate the refractive index of the waveguides of the present disclosure.

Referring toFIGS.44and65, method400includes a block418where the ILD layer220is deposited. The ILD layer220may include silicon oxide or silicon-oxide-containing dielectric material. In some embodiments, the ILD layer220may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials and may be deposited using spin-on coating or flowable chemical vapor deposition (FCVD). In some other embodiments, the ILD layer220may include silicon oxide and may be deposited using CVD, plasma-enhanced CVD (PECVD), or other suitable process. In some instances, the ILD layer220may have a thickness (along the Z direction) between about 250 nm and about 350 nm.

In some embodiments, method500inFIG.66may be performed to form ridge-type or rib-type waveguide feature2060that includes wider bottom portion206B and a narrow top portion206T, illustrated inFIG.68. Embodiments of method500are described below in conjunction withFIGS.67-68.

Referring toFIGS.66and67, method500includes a block502where a workpiece200is provided. At block502, method500may begin with a workpiece200. Similar to what is shown inFIG.2, the workpiece200inFIG.67includes a substrate202, a buried oxide (BOX) layer204on the substrate202, and a semiconductor layer205on the buried oxide layer204. In one embodiment, the substrate202may be a silicon (Si) substrate. In some other embodiments, the substrate202may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The BOX layer204may include silicon oxide and the semiconductor layer205may include silicon (Si). In some implementations where the substrate202and the semiconductor layer205are formed of silicon (Si) and the BOX layer204is formed of silicon oxide, the substrate202, the BOX layer204, and the semiconductor layer205may be portions of a silicon-on-insulator (SOI) substrate.

Referring toFIGS.66and67, method500includes a block504where shallow trenches210are formed in the semiconductor layer205to define a top portion206T on a base portion of the semiconductor layer205. Operations at block504include forming shallow trenches210that do not extend through the semiconductor layer205. In some embodiments represented inFIG.67, the formation of the shallow trenches210includes etching the semiconductor layer205through the first patterned hard mask208described above with respect to method100. While a similar etch process is performed to etch the semiconductor layer205at block504, the etch process lasts a shorter period of time such that the shallow trenches210does not extend through the semiconductor layer205to expose the BOX layer204. The formation of the shallow trenches210define the top portion206T, which is disposed on the based portion of the semiconductor layer205, not on the BOX layer204.

Referring toFIGS.66and68, method500includes a block506where the base portion of the semiconductor layer205is patterned to form ridge-type silicon features2060. While not explicitly shown in the figures, another patterned hard mask may be formed for further patterning the base portion of the semiconductor layer205to form the ridge-type silicon feature2060. The ridge-type silicon feature2060may be referred to as ridge-type waveguide feature2060due to its shapes or as a ridge-type first waveguide feature2060due to its relative location with the second waveguide feature248. As shown inFIG.68, the ridge-type waveguide feature2060includes a bottom portion206B and a top portion206T disposed on the bottom portion206B. Along the X direction, the bottom portion206B is wider than the top portion. This profile gives the name—ridge-type silicon feature2060. After the ridge-type silicon feature2060is formed, the fill dielectric layer214is deposited over the workpiece200. The fill dielectric layer214may be planarized to provide a planar top surface, as shown inFIG.68.

Methods100,300,400, and500may be performed to the same workpiece200to form various waveguide structures. For example,FIGS.69-74include a first example structure andFIGS.75-79illustrate a second example structure.

Reference is first made toFIG.69, which illustrates a top view of a semiconductor structure200that includes a first waveguide feature206and a second waveguide feature248that are aligned along the Y direction and partially overlapped. For ease of illustration,FIG.69is simplified to remove all structures surrounding the first waveguide feature206and the second waveguide feature248. Along the Y direction, the first waveguide feature206may be divided into a non-tapered portion206NT and a tapered portion206TP and the second waveguide feature248may be divided into a non-taper portion248NT, a tapered portion248TP, and a tip portion2482. The tip portion2482partially overlaps the tapered portion206TP to form a spot size converter or an optical edge coupler to optically couple the first waveguide feature206and the second waveguide feature248. Along the X direction, a width of the tapered portion206TP decreases from a width of the non-tapered portion206NT as the tapered portion206TP tapers away from the non-tapered portion206NT. Along the X direction, a width of the non-tapered portion248NT is greater than a width of the tip portion2482. The tapered portion248TP serves as a transition between the non-tapered portion248NT and the tip portion2482. In some embodiments described above, the first waveguide feature206may be formed of silicon and the second waveguide feature248may be formed of silicon nitride. Method300inFIG.35or variation thereof may be used to form the tip portion2482or the tapered portions206TP and248TP.

Fragmentary cross-sectional views along section A-A′, B-B′, C-C′ and D-D′ inFIG.69are provided to illustrate structures surrounding the first waveguide feature206and the second waveguide feature248.FIG.70andFIG.71illustrate a fragmentary cross-sectional view along section A-A′ in two example embodiments. InFIG.70, the first waveguide feature206is not ridge-type while theFIG.71illustrates an embodiment where the ridge-type first waveguide feature2060is employed. In bothFIGS.70and71, the first waveguide feature206(or the ridge-type first waveguide feature2060) is disposed between two doped silicon features218. By way of the silicide layer226, the two doped silicon features218are coupled to contact features228, which are in turn coupled to the lower metal features238, the upper metal features263, and the via features264. Along section A-A′, no second waveguide features248are present over the first waveguide feature206(or the ridge-type first waveguide feature2060). The first waveguide feature206may be fabricated using method100while the ridge-type first waveguide feature2060may be fabricated using method500.

FIG.72illustrates a fragmentary cross-sectional view along section B-B′. At section B-B′, the tip portion2482vertically overlaps the tapered portion206TP. In the depicted embodiment, the tapered portion206TP is not disposed between two doped silicon features218but is disposed alongside a single doped silicon feature218. The first waveguide feature206is embedded in the fill dielectric layer214. As it is not coupled to any doped silicon feature below, the dummy contact feature228D is disposed over the fill dielectric layer214. The tip portion2482is disposed between a contact feature228and the dummy contact feature228D. Features described in conjunction withFIGS.70and71will not be repeated for brevity.FIG.73illustrates a fragmentary cross-sectional view along section C-C′. At section C-C′, the tip portion2482is disposed between a dummy contact feature228D and a contact feature228. It is noted however, the dummy contact feature228D inFIG.73is not the same dummy contact feature228D inFIG.72. Additionally, at cross-section C-C′, the tip portion2482is not disposed over any portion of the first waveguide feature206. For brevity, description of similar features will not be repeated.

FIG.74illustrates a fragmentary cross-sectional view along section D-D′. InFIG.74, the non-tapered portion248NT of the second waveguide feature248is disposed between two contact features228, between two lower metal features238, as well as between two upper metal features263. The non-tapered portion248NT is spaced apart from adjacent contact features228by the ILD layer220. The non-tapered portion248NT is spaced apart from adjacent lower metal features238by the first IMD layer230. The non-tapered portion248NT is spaced apart from adjacent upper metal features263by the second IMD layer240. The non-tapered portion248NT is not disposed over any portion of the first waveguide feature206and may have a thickness between about 400 nm and about 600 nm. The non-tapered portion248NT of the second waveguide feature248may be fabricated using method100inFIG.1.

Reference is now made toFIG.75, which illustrates a top view of a semiconductor structure200that includes an active waveguide construction. Similar to the semiconductor structure200inFIG.69, the semiconductor structure inFIG.75also includes the first waveguide feature206and the second waveguide feature248that are aligned along the Y direction and partially overlap. The first waveguide feature206may be divided into a non-tapered portion206NT and a tapered portion206TP and the second waveguide feature248may be divided into a non-taper portion248NT, a tapered portion248TP, and a tip portion2482. The tip portion2482and the tapered portion206TP are spot size converters. They partially overlap to function as an optical edge coupler to optically couple the first waveguide feature206and the second waveguide feature248. Different from the semiconductor structure200inFIG.69, the non-tapered portion206NT inFIG.75is coupled to an active region that includes the third n-doped region225, the second n-doped region221, and the first n-doped region217, the third p-doped region237, the second p-doped region233, and the first p-doped region229. The active region may be formed using method400inFIG.44. In some embodiments, a portion of the first waveguide feature206(such as a portion of the second silicon feature2062, see alsoFIG.47) may remain substantially undoped and is sandwiched between the first n-doped region217and the first p-doped region229.

Fragmentary cross-sectional views along section AA-AA′, BB-BB′, CC-CC′ and DD-DD′ inFIG.75are provided to illustrate structures surrounding the first waveguide feature206and the second waveguide feature248.FIG.76illustrates a fragmentary cross-sectional view along section AA-AA′ inFIG.75. Each of the third n-doped region225and the third p-doped region237is coupled to an overlying contact feature228by way of the silicide layer226. The contact features228inFIG.76are in turn coupled to the lower metal features238, the upper metal features263, and the via features264. The dotted area inFIG.76illustrates where the non-tapered portion206NT is coupled to the active region.FIG.77illustrates a fragmentary cross-sectional view along section BB-BB′ inFIG.75, which may be similar to the fragmentary cross-sectional view shown inFIG.72.FIG.78illustrates a fragmentary cross-sectional view along section CC-CC′ inFIG.75, which may be similar to the fragmentary cross-sectional view shown inFIG.73.FIG.79illustrates a fragmentary cross-sectional view along section DD-DD′ inFIG.75, which may be similar to the fragmentary cross-sectional view shown inFIG.74. Detailed descriptions ofFIGS.77-79are therefore omitted for brevity.

Embodiments of the present disclosure provide advantages. The present disclosure provides apparatus or semiconductor structure that includes a first waveguide feature disposed between doped silicon features and a second waveguide feature disposed between contact features coupled to the doped silicon features. The second waveguide feature is also disposed between lower metal features disposed over the contact features as well as upper metal features disposed over the lower metal features. In some embodiments, the first waveguide features are formed of silicon and the second waveguide feature is formed of silicon nitride. Because the second waveguide feature is allowed to extend vertically between features in more than one interconnect layers, the second waveguide feature may have a sufficient thickness for O-Band or C-Band applications without increasing the thickness of the contact features.

In one exemplary aspect, the present disclosure is directed to an apparatus. The apparatus includes a plurality of doped silicon features over a substrate, a plurality of contact features disposed over and electrically coupled to the plurality of doped silicon features, a plurality of lower metal features disposed over and electrically coupled to the plurality of contact features, a plurality of upper metal features disposed over and electrically coupled to the plurality of lower metal features, a first waveguide feature disposed between two adjacent ones of the plurality of doped silicon features, and a second waveguide feature disposed over the first waveguide feature, wherein a top surface of the second waveguide feature is higher than top surfaces of the plurality of contact features such that the second waveguide feature is disposed between two adjacent ones of the plurality of lower metal features, and two adjacent ones of the plurality of upper metal features.

In some embodiments, the first waveguide feature has a first refractive index and the second waveguide feature has a second refractive index different from the first refractive index. In some implementations, the first waveguide feature includes silicon and the second waveguide feature includes silicon nitride. In some instances, the first waveguide feature includes a first non-tapered portion and a first tapered portion extending from the first non-tapered portion, the second waveguide feature includes a second non-tapered portion, a second tapered portion extending from the second non-tapered portion, and a tip portion extending from the second tapered portion, and the tip portion overlaps the first tapered portion of the first waveguide feature. In some embodiments, the apparatus further includes a plurality of via features disposed over and electrically coupled to the plurality of upper metal features. The first waveguide feature extends lengthwise along a first direction and, along a second direction perpendicular to the first direction, a width of each of the plurality of via features is greater than a width of each of the plurality of upper metal features. In some embodiments, the apparatus further includes a silicide layer disposed between the plurality of doped silicon features and the plurality of contact features. In some instances, the first waveguide feature and the second waveguide feature are configured to operate with infrared having a wavelength of about 1310 nm, about 1550 nm, or both. In some implementations, the plurality of contact features include a thickness between about 350 nm and about 380 nm. In some embodiments, the second waveguide feature is disposed in more than one dielectric layer and the more than one dielectric layer includes silicon oxide.

In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a plurality of contact features disposed in the second dielectric layer, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. A top surface of the second waveguide feature is higher than top surfaces of the plurality of contact features and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

In some embodiments, the semiconductor structure further includes a first metal interconnect layer disposed in the second dielectric layer, the first metal interconnect layer including a first contact feature and a second contact feature, and a second metal interconnect layer disposed in the third dielectric layer, the second metal interconnect layer including a first metal feature and a second metal feature. The second waveguide feature is disposed between the first contact feature and the second contact feature as well as between the first metal feature and the second metal feature. In some embodiments, the first waveguide feature includes a first refractive index and the second waveguide feature includes a second refractive index different from the first refractive index. In some instances, the first waveguide feature includes silicon and the second waveguide feature includes silicon nitride. In some implementations, the semiconductor structure further includes a first doped silicon feature and a second doped silicon feature in the first dielectric layer. The first waveguide feature is disposed between the first doped silicon feature and the second doped silicon feature. In some instances, the first waveguide feature includes a bottom portion on the buried oxide layer and a top portion disposed on the bottom portion and a width of the bottom portion is greater than a width of the top portion. In some embodiments, a thickness of the second waveguide feature is greater than a thickness of the first waveguide feature.

In yet another exemplary aspect, the present disclosure is directed to a method. The method includes providing a workpiece including a substrate, a buried oxide layer over the substrate, and a silicon layer over the buried oxide layer, patterning the silicon layer into first silicon features and second silicon features, the first silicon features and the second silicon features being divided from one another by trenches, depositing a fill dielectric layer in the trenches, doping the second silicon features with a dopant, forming contact features over the doped second silicon features, forming lower metal features over the contact features, and forming a plurality of silicon nitride features, wherein each of the plurality of silicon nitride features is disposed between two adjacent ones of the contact features as well as two adjacent ones of the lower metal features.

In some embodiments, the method further includes before the forming of the contact features, forming a silicide layer on the doped second silicon features. In some implementations, the forming of the contact features includes depositing a first dielectric layer over the fill dielectric layer, the first silicon features, and the second silicon features. In some instances, the method further includes after the forming of the plurality of silicon nitride features, forming upper metal features over the lower metal features.