SEMICONDUCTOR STRUCTURE FABRICATION METHOD, SEMICONDUCTOR STRUCTURE AND MEMORY

The present application provides a semiconductor structure fabrication method, a semiconductor structure and a memory. The semiconductor structure fabrication method includes: providing a substrate, the substrate including a first surface and a second surface opposite to each other; forming a first dielectric layer on the first surface of the substrate, wherein semiconductor devices are formed in the first dielectric layer; forming first trenches extending into the substrate in the first dielectric layer; forming a first barrier layer on the first dielectric layer, the first barrier layer covering inner walls of the first trenches and a surface of the first dielectric layer; forming second trenches corresponding to the first trenches on the second surface of the substrate; and forming a second barrier layer on the substrate, the second barrier layer covering the second surface and inner walls of the second trenches.

TECHNICAL FIELD

The present application relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure fabrication method, a semiconductor structure and a memory.

BACKGROUND

With the development of semiconductor technologies, due to the constant reduction in feature sizes of integrated circuits and the constant increase in the density of interconnection between devices, conventional two-dimensional packaging can no longer meet the requirements of the industry. Therefore, with the key technological advantages of short-distance interconnection and high-density integration, a stacked packaging method based on Through-Silicon Via (TSV for short) vertical interconnection has become a mainstream direction of the development of packaging technologies.

The TSV technique is a technique which fabricates vertical vias by etching, laser drilling or other methods between different device structures and then deposits a conducting material in the vertical vias by electroplating or other methods to form conducting pillars to achieve electrical interconnection. At present, the TSV process flow mainly depends on a TSV middle process or a TSV last process to form a TSV structure, requiring a large region to be reserved for TSVs, which results in tremendous waste.

Therefore, how to solve the aforementioned problem has become a problem to be solved urgently by those skilled in the art.

SUMMARY

The embodiments of the present application provides a semiconductor structure fabrication method, including:

providing a substrate, the substrate including a first surface and a second surface opposite to each other;

forming a first dielectric layer on the first surface of the substrate, wherein semiconductor devices are formed in the first dielectric layer;

forming first trenches extending into the substrate in the first dielectric layer;

forming a first barrier layer on the first dielectric layer, the first barrier layer covering inner walls of the first trenches and a surface of the first dielectric layer, wherein the first barrier layer is connected to the semiconductor devices;

forming second trenches corresponding to the first trenches on the second surface of the substrate, wherein the first barrier layer serves as a stop layer when the second trenches are formed; and

forming a second barrier layer on the substrate, the second barrier layer covering the second surface and inner walls of the second trenches, wherein the second barrier layer is connected to the first barrier layer.

The embodiments of the present application provides a semiconductor structure, including:

a substrate including a first surface and a second surface opposite to each other; and

a first dielectric layer formed on the first surface of the substrate, semiconductor devices being formed in the first dielectric layer; wherein the semiconductor structure includes first trenches formed in the first dielectric layer and extending into the substrate; and

a first barrier layer formed on the first dielectric layer, the first barrier layer covering inner walls of the first trenches and a surface of the first dielectric layer, the first barrier layer being connected to the semiconductor devices; wherein the semiconductor structure includes: second trenches formed on the second surface of the substrate and corresponding to the first trenches, the first barrier layer serving as a stop layer when the second trenches are formed; and

a second barrier layer covering the second surface and inner walls of the second trenches, wherein the second barrier layer is connected to the first barrier layer.

The embodiments of the present application provides a memory, including the aforementioned semiconductor structure.

DETAILED DESCRIPTION

With the development of semiconductor technology, due to the constant reduction in feature sizes of integrated circuits and the constant increase in the density of interconnection between devices, conventional two-dimensional packaging can no longer meet the requirements of the industry. Therefore, with the key technological advantages of short-distance interconnection and high-density integration, a stacked packaging method based on Through-Silicon Via (TSV for short) vertical interconnection has become a mainstream direction of the development of packaging technology.

The TSV technique is a technique which fabricates vertical vias by etching, laser drilling or other methods between different device structures and then deposits a conducting material in the vertical vias by electroplating or other methods to form conducting pillars to achieve electrical interconnection. At present, the TSV process flow mainly depends on a TSV middle process or a TSV last process to form a TSV structure, requiring a large region to be reserved for TSVs, which results in tremendous waste.

In some embodiments, since the cost of silicon on insulator is high, at least ten times that of bulk silicon materials, it is a waste to only fabricate semiconductor devices on the front of silicon on insulator in a conventional way. Moreover, the fabrication of a system on a chip on one plane results in a large structure area. Furthermore, since each subsystem can adopt only one process node, failing to fully utilize a surface of silicon on insulator, the manufacturing cost is high, and the subsystems inside the system cannot be flexibly interconnected. Therefore, how to design a system on a chip with powerful functionality in which semiconductor devices can be fabricated on both the front and back of silicon on insulator has become a problem confronting those skilled in the art.

As shown inFIG.1, the present application provides a semiconductor structure fabrication method, including:

(S110) providing a substrate, the substrate including a first surface and a second surface opposite to each other;

(S120) forming a first dielectric layer on the first surface of the substrate, wherein semiconductor devices are formed in the first dielectric layer;

(S130) forming first trenches extending into the substrate in the first dielectric layer;

(S140) forming a first barrier layer on the first dielectric layer, the first barrier layer covering inner walls of the first trenches and a surface of the first dielectric layer, wherein the first barrier layer is connected to the semiconductor devices;

(S150) forming second trenches corresponding to the first trenches on the second surface of the substrate, wherein the first barrier layer serves as a stop layer when the second trenches are formed;

(S160) forming a second barrier layer on the substrate, the second barrier layer covering the second surface and inner walls of the second trenches, wherein the second barrier layer is connected to the first barrier layer.

In the embodiments of the present application, in a first aspect, the TSV process flow is optimized; by employing a TSV first process to form the first trenches and the second trenches on the two opposite surfaces of the substrate (i.e., wafer) respectively, the problems of large wafer fabrication area and excessive cost caused by the fabrication of semiconductor devices and the reservation of a TSV fabrication area on a same surface of a wafer can be solved; according to the present application, by forming the second trenches on the second surface of the substrate, the number of the first trenches of the first surface of the substrate can be reduced, effectively controlling the wafer fabrication area and saving the fabrication cost of a semiconductor. In a second aspect, since the two opposite surfaces of the substrate are sufficiently utilized to form a TSV structure in the form of a 3D architecture composed of the first trenches and the second trenches and the second barrier layer in the second trenches is in metallic interconnection with the first barrier layer in the first trenches, a 3D architecture of subsystems in a system on a chip is achieved, the interconnection between the subsystems is more flexible, interconnection lines are shorter, and the performance of the semiconductor is improved.

In some embodiments,FIGS.2to7provide schematic structural diagrams presented by steps S110to S140in the flow of the semiconductor structure fabrication method according to the embodiment of the present application.FIGS.2to7are sectional views of a semiconductor structure in the manufacturing process, which illustrate a substrate10, a first dielectric layer20formed on the substrate10, a first surface11and a second surface12of the substrate10, and formed first trenches40.

Any substrate10in the prior art may be used as the substrate10as required, and a structure and material of the substrate10may also be adaptively adjusted as required. For example, the material of the substrate10may be one or a combination of any of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator (SOI) or germanium on insulator (GOI).

In some embodiments, referring toFIG.7, in step S120, the first dielectric layer20is formed on the first surface11of the substrate10, wherein semiconductor devices are formed in the first dielectric layer. As shown inFIGS.2to12, the semiconductor device includes a capacitor structure21, a first metal plug22, a second metal plug23, a device24and a trench isolator25. The capacitor structure21is formed on the first surface11of the substrate10, the first metal plug22is connected to the capacitor structure21, and a top exposed surface of the first metal plug22covers a first barrier layer70. The trench isolator25is formed in the substrate10, the device24is formed on the first surface11of the substrate10, the second metal plug23is connected to the device24, and the top exposed surface of the second metal plug23covers the first barrier layer70. A material of the first dielectric layer20may be selected from at least one of SiN (silicon nitride), SiO2(silicon oxide), SiON (silicon oxynitride) and BARC (bottom anti-reflective coating). As shown inFIG.7, the semiconductor devices are formed on the first surface11of the substrate10. The present application employs a deposition process to form the first dielectric layer20on the first surface11of the substrate10, with the first dielectric layer20formed to cover the semiconductor devices. The semiconductor devices include, but are not limited to, NMOS devices, PMOS devices, CMOS devices, resistors, capacitors, inductors or the like.

In some embodiments, referring toFIGS.2to12, in step S130, the first trenches40extending into the substrate10is formed in the first dielectric layer20, wherein the first trenches40are formed in the substrate10by employing the TSV first process. It can be seen from the above accompanying drawings that the first trenches40running through the first dielectric layer20and extending into the substrate10are formed by processing a surface of the first dielectric layer20away from the substrate10by employing the TSV first process. The first trenches40are formed between the adjacent semiconductor devices.

In some embodiments, referring toFIG.7, in step S140, the first barrier layer70is formed on the first dielectric layer20, the first barrier layer70covering inner walls of the first trenches40and a surface of the first dielectric layer20, wherein the first barrier layer70is connected to the semiconductor devices. It should be understood that in some embodiments, the first barrier layer70is a metallic interconnection layer. Continuing to refer toFIG.7, a plurality of trenches are formed in the first dielectric layer20, including the first trenches40, with each trench correspondingly formed on the top of each semiconductor device to expose the surface of the semiconductor device, and the first barrier layer70is formed to cover the surface of the first dielectric layer20, and is connected to the exposed surface of each semiconductor device.

In some embodiments, the forming the first trenches40extending into the substrate10in the first dielectric layer20in step S130includes:

(S131) forming a first mask pattern on the first dielectric layer20;

Referring toFIG.2, the first mask pattern is formed on a surface of the first dielectric layer20away from the substrate10.

(S132) etching the first dielectric layer20by utilizing the first mask pattern to form the first trenches40extending from the first dielectric layer20into the substrate10.

Continuing to refer toFIG.2, the first mask pattern defines etching windows, and the first dielectric layer20and the substrate10are etched according to the etching windows to form the trenches in the first dielectric layer20. The trenches include the trenches corresponding to the semiconductor devices and the first trenches40. The trenches corresponding to the semiconductor devices use the semiconductor devices as an etching stop layer and expose the surfaces of the semiconductor devices after etching. The first trenches40are formed to run through the first dielectric layer20and stop in the substrate10.

In some embodiments, the forming a first mask pattern on the first dielectric layer20in step S131includes:

(S1311) forming a first hard mask layer30on the first dielectric layer20.

The first hard mask layer30is formed on a surface of the first dielectric layer20away from the substrate10by employing the deposition process.

(S1312) forming the first mask pattern on the first hard mask layer30.

In some embodiments, a photoresist layer is formed on the first hard mask layer30by employing a spin-coating process, the photoresist layer is patterned by employing an exposure process, and the first hard mask layer30is etched according to the patterned photoresist layer to form a first mask pattern.

In some embodiments, subsequent to the etching the first dielectric layer20by utilizing the first mask pattern to form the first trenches40extending from the first dielectric layer20into the substrate10in step S132, the semiconductor structure fabrication method further includes:

(S170) forming a second hard mask layer50covering the first mask pattern and the first trenches40;

Referring toFIG.3, the second hard mask layer50is formed on a surface of the first mask pattern (formed by patterning the first hard mask layer30using the etching process) away from the substrate10, and fills the etching windows of the first mask pattern and the trenches formed in the first dielectric layer20.

(S180) forming a patterned photoresist layer60on the second hard mask layer50.

Referring toFIG.4, the patterned photoresist layer60is formed on a surface of the second hard mask layer50away from the substrate10. It can be understood that the patterned photoresist layer60can be formed on the second hard mask layer50by employing the spin-coating process and patterned by employing the exposure process.

(S190) transferring the pattern of the patterned photoresist layer60to the first dielectric layer20by employing a dry etching process.

Referring toFIG.5, the second hard mask layer50is dry-etched according to the patterned photoresist layer60, and the pattern of the patterned photoresist layer60is transferred to the second hard mask layer50, the first hard mask layer30and the first dielectric layer20, so that one side of the first dielectric layer20away from the substrate10is formed into a patterned structure.

In some other embodiments, subsequent to the transferring the pattern of the patterned photoresist layer60to the first dielectric layer20by employing a dry etching process in step S190, the semiconductor structure fabrication method further includes:

(S191) removing the hard masks and the photoresist on the first dielectric layer20by employing a wet cleaning process.

The hard masks and the photoresist on the first dielectric layer20are removed by employing the wet cleaning process, and the hard masks include the first hard mask layer30and the second hard mask layer50which are laminated on the first dielectric layer20after pattern transferring. Referring toFIG.6,FIG.6shows a semiconductor structure after cleaning. It can be seen in the drawing that a pattern structure has been formed on one side of the first dielectric layer20away from the substrate10, a trench is correspondingly formed over each semiconductor device to expose a surface of the semiconductor device, and the formed first trenches40expose a surface of the substrate10.

In yet other embodiments, subsequent to the forming a first barrier layer70on the first dielectric layer20in step S140, the semiconductor structure fabrication method further includes:

(S200) forming a first metal layer80covering the first barrier layer70.

Referring toFIG.7, a first metal layer80is formed on one side of the first dielectric layer20where the pattern structure is formed, and covers the surface of the first barrier layer70, and the first barrier layer70is located between the first metal layer80and the first dielectric layer20. The first metal layer80fills the trenches in the first dielectric layer20, specifically including the trenches corresponding to the semiconductor devices and the first trenches40. A material of the first metal layer80may be copper.

In some embodiments, subsequent to the forming second trenches100corresponding to the first trenches40on the second surface12of the substrate10in step S150, the semiconductor structure fabrication method further includes:

(S210) turning over the substrate10.

The substrate10is turned over, so that the second surface12of the substrate10serves as a fabrication surface in the semiconductor structure manufacturing process. Referring toFIGS.8to12, it can be seen that the substrate10is turned over by 180 degrees.

(S220) thinning the second surface12of the substrate10.

The second surface12is lapped by employing a chemical mechanical polish (CMP) process to reduce the thickness of the substrate10.

In some embodiments, the forming second trenches100corresponding to the first trenches40on the second surface12of the substrate10in step S150includes:

(S151) forming a second mask pattern on the second surface12of the substrate10.

Referring toFIG.8, a second mask pattern is formed on the second surface12of the substrate10, and the second mask pattern defines etching windows.

(S152) etching the substrate10by utilizing the second mask pattern to form the second trenches100stopping at the first barrier layer70.

Referring toFIG.9, the substrate10is etched according to the etching windows defined by the second mask pattern and with the first barrier layer70as a stop layer to form second trenches100stopping at the first barrier layer70.

In some embodiments, the forming a second mask pattern on the second surface12of the substrate10in step S151includes:

(S1511) forming a third hard mask layer90on the second surface12of the substrate10.

Referring toFIG.8, the third hard mask layer90is formed on the second surface12of the substrate10by employing the deposition process.

(S1512) processing the third hard mask layer90by employing the exposure process to form the second mask pattern.

A photoresist layer is formed on the third hard mask layer90by employing the spin-coating process, the photoresist layer is patterned by employing the exposure process, and the third hard mask layer90is etched according to the patterned photoresist layer to form a second mask pattern, which defines etching windows for the etching of the second trenches100.

In some embodiments, prior to the forming a second barrier layer120on the substrate10in step S160, the semiconductor structure fabrication method further includes:

(S230) forming a second dielectric layer110on the substrate10, the second dielectric layer110covering the second surface12and inner walls of the second trenches100.

Referring toFIG.10, a second dielectric layer110is formed on the substrate10by employing the deposition process, with the second dielectric layer110formed to cover the second surface12and inner walls of the second trenches100. A material of the second dielectric layer110may be selected from at least one of SiN (silicon nitride), SiO2(silicon oxide), SiON (silicon oxynitride) and BARC (bottom anti-reflective coating). Continuing to refer toFIG.10, the second dielectric layer110located at bottoms of the second trenches100is connected to the first barrier layer70.

In some embodiments, subsequent to the forming a second dielectric layer110on the substrate10in step S230, the semiconductor structure fabrication method further includes:

(S240) removing the second dielectric layer110formed at the bottoms of the second trenches100by employing the etching process.

Referring toFIG.11, the second dielectric layer110at the bottoms of the second trenches100is etched with the first barrier layer70as an etching stop layer to expose the surface of the first barrier layer70.

In some embodiments, subsequent to the forming a second barrier layer120on the substrate10in step S160, the semiconductor structure fabrication method further includes:

(S250) forming a second metal layer130covering the second barrier layer120.

Referring toFIG.12, a second metal layer130is formed on a surface of the second barrier layer120, with the second barrier layer120located between the second metal layer130and the second dielectric layer110. The second metal layer130fills the second trenches100. Continuing to refer toFIG.12, the second barrier layer120and the first barrier layer70are connected at the bottoms of the second trenches100, achieving the interconnection between the first barrier layer70and the second barrier layer120. A material of the second metal layer130is copper.

In the embodiments of the present application, in a first aspect, the TSV process flow is optimized; by employing a TSV first process to form the first trenches40and the second trenches100on the two opposite surfaces of the substrate10(i.e., wafer) respectively, the problems of large wafer fabrication area and excessive cost caused by the fabrication of semiconductor devices and the reservation of a TSV fabrication area on a same surface of the wafer can be solved; according to the present application, by forming the second trenches100on the second surface12of the substrate10, the number of the first trenches40of the first surface11of the substrate10can be reduced, effectively controlling the wafer fabrication area and saving the fabrication cost of a semiconductor. In a second aspect, since the two opposite surfaces of the substrate10are sufficiently utilized to form a TSV structure in the form of a 3D architecture composed of the first trenches40and the second trenches100and the second barrier layer120in the second trenches100is in metallic interconnection with the first barrier layer70in the first trenches40, a 3D architecture of subsystems in a system on a chip is achieved, the interconnection between the subsystems is more flexible, interconnection lines are shorter, and the performance of the semiconductor is improved.

In some embodiments, numbers of the first trenches40and the second trenches100are plural, and the plurality of second trenches100and the plurality of first trenches40are arranged in one-to-one correspondence. The first trench40is formed between two adjacent semiconductor devices.

In the embodiments of the present application, since the two opposite surfaces of the substrate10are sufficiently utilized to form a TSV structure in the form of a 3D architecture composed of the first trenches40and the second trenches100and the second barrier layer120in the second trenches100is in metallic interconnection with the first barrier layer70in the first trenches40, a 3D architecture of subsystems in a system on a chip is achieved, the interconnection between the subsystems is more flexible, interconnection lines are shorter, and the performance of the semiconductor is improved.

In some embodiments, a cross section of the second trench100is wedge-shaped, and an opening size of the second trench100is gradually reduced along a direction from the second surface12to the first surface11.

According to a second aspect of the present application, the present application provides a semiconductor structure, which includes a substrate10, a first dielectric layer20, a first barrier layer70and a second barrier layer120. The substrate10includes a first surface11and a second surface12opposite to each other. A first dielectric layer20is formed on the first surface11of the substrate10, and semiconductor devices are formed in the first dielectric layer20; and the semiconductor structure includes first trenches40formed in the first dielectric layer20and extending into the substrate10. The first barrier layer70is formed on the first dielectric layer20and covers inner walls of the first trenches40and a surface of the first dielectric layer20, and the first barrier layer70is connected to the semiconductor devices. The semiconductor structure includes second trenches100formed on the second surface12of the substrate10and corresponding to the first trenches40, and the first barrier layer70serves as a stop layer when the second trenches100are formed. The second barrier layer120is formed on the substrate10and covers the second surface12and inner walls of the second trenches100. The second barrier layer120is connected to the first barrier layer70.

In the embodiments of the present application, in a first aspect, the TSV process flow is optimized; by employing a TSV first process to form the first trenches40and the second trenches100on the two opposite surfaces of the substrate10(i.e., wafer) respectively, the problems of large wafer fabrication area and excessive cost caused by the fabrication of semiconductor devices and the reservation of a TSV fabrication area on a same surface of the wafer can be solved; according to the present application, by forming the second trenches100on the second surface12of the substrate10, the number of the first trenches40of the first surface11of the substrate10can be reduced, effectively controlling the wafer fabrication area and saving the fabrication cost of a semiconductor. In a second aspect, since the two opposite surfaces of the substrate10are sufficiently utilized to form a TSV structure in the form of a 3D architecture composed of the first trenches40and the second trenches100and the second barrier layer120in the second trenches100is in metallic interconnection with the first barrier layer70in the first trenches40, a 3D architecture of subsystems in a system on a chip is achieved, the interconnection between the subsystems is more flexible, interconnection lines are shorter, and the performance of the semiconductor is improved.

In some embodiments, the semiconductor structure further includes a first metal layer80, which is formed to cover the first barrier layer70.

In some embodiments, the semiconductor structure further includes a second dielectric layer110, which is formed on the substrate10. The second dielectric layer110covers the second surface12and the inner walls of the second trenches100.

In some embodiments, the semiconductor structure further includes a second metal layer130, which is formed to cover the second barrier layer120.

In some embodiments, the numbers of the first trenches40and the second trenches100are plural, and the plurality of second trenches100and the plurality of first trenches40are arranged in one-to-one correspondence.

In the embodiments of the present application, since the two opposite surfaces of the substrate10are sufficiently utilized to form a TSV structure in the form of a 3D architecture composed of the first trenches40and the second trenches100and the second barrier layer120in the second trenches100is in metallic interconnection with the first barrier layer70in the first trenches40, a 3D architecture of subsystems in a system on a chip is achieved, the interconnection between the subsystems is more flexible, interconnection lines are shorter, and the performance of the semiconductor is improved.

It can be understood that the semiconductor structure fabricated according to the embodiments described above can be applied to the fabrication of various integrated circuit (IC). An IC according to the present application is, for example, a memory circuit, such as a random access memory (RAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), or a read-only memory (ROM) or the like. The IC according to the present application may also be a logic device, such as a programmable logic array (PLA), an application specific integrated circuit (ASIC), a merged DRAM logic integrated circuit (buried DRAM), a radio frequency circuit or any other circuit device. The IC chip according to the present application may be used in, for example, electronic products for consumers, such as personal computers, portable computers, game consoles, cellular phones, personal digital assistants, video cameras, digital cameras, mobile phones and other electronic products.

According to a third aspect of the present application, the present application provides a memory, including the aforementioned semiconductor structure.

In the description of the present specification, the description of reference terms, such as “some embodiments”, “other embodiments” and “ideal embodiments”, means that the specific features, structures, materials or characteristics described in the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the schematic description of the aforementioned terms does not necessarily refer to the same embodiment or example.

All the technical features of the aforementioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the aforementioned embodiments are described. However, as long as there is no contradiction between the combinations of these technical features, they should be considered as the scope recorded in the present specification.

The aforementioned embodiments only represent several embodiments of the present application, and although their descriptions are specific and detailed, they cannot be understood as a limitation to the scope of the present patent application. It should be pointed out that those of ordinary skill in the art can also make a plurality of alterations and improvements without departing from the concept of the present application, and these alterations and improvements shall fall within the protection scope of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.