Multi-fin device by self-aligned castle fin formation

The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.

BACKGROUND

Integrated circuits have progressed to advanced technologies with high packing densities and smaller feature sizes, such as 45 nm, 32 nm, 28 nm and 20 nm. In these advanced technologies, three dimensional transistors each having a multi-fin structure are often desired for enhanced device performance. However, existing methods and structures for such structures have various concerns and disadvantages associated with device quality and reliability. For example, various defects can be induced by merging an epitaxial (epi) feature. In another example, source and drain resistances are increased due to poor quality of merged source/drain epi features. In another example, the fabrication cost is higher due to additional process steps, such as the need for an additional mask to define an intra-device region. Therefore, there is a need for a new structure and method for a multi-fin device to address these concerns for enhanced performance and reduced fabrication cost.

DETAILED DESCRIPTION

FIG. 1is a flowchart of a method100for making a semiconductor device constructed according to an embodiment of the present invention. The semiconductor device includes a multi-fin structure and a dual-depth isolation structure.FIGS. 2 through 7are sectional views of an embodiment of a semiconductor structure200at various fabrication stages and constructed according to the method100. The semiconductor structure200and the method100of making the same are collectively described with reference toFIGS. 1 through 7.

Referring toFIGS. 1 and 2, the method100begins at step102by providing a semiconductor substrate210. The semiconductor substrate210includes silicon. Alternatively, the substrate includes germanium, silicon germanium or other proper semiconductor materials. The semiconductor substrate210also includes various doped regions such as n-well and p-wells. In one embodiment, the semiconductor substrate210includes an epitaxy (or epi) semiconductor layer. In another embodiment, the semiconductor substrate210includes a buried dielectric material layer for isolation formed by a proper technology, such as a technology referred to as separation by implanted oxygen (SIMOX).

Still referring toFIGS. 1 and 2, the method100proceeds to step104by forming a patterned mask layer212. In one embodiment, the patterned mask layer212is a hard mask layer having one or more suitable dielectric materials. For example, the mask layer212includes a silicon nitride (SiN) layer. In the present embodiment, the mask layer212includes a silicon oxide (SiO) layer214formed on the semiconductor substrate210and a SiN layer216formed on the SiO layer214. In one example, the SiO layer214includes a thickness ranging between about 5 nm and about 15 nm. In another example, the SiN layer216includes a thickness ranging between about 40 nm and about 120 nm. In another embodiment, step104includes forming the SiO layer214by thermal oxidation and forming the SiN layer216by chemical vapor deposition (CVD). For example, the SiN layer216is formed by CVD using chemicals including Hexachlorodisilane (HCD or Si2Cl6), Dichlorosilane (DCS or SiH2Cl2), Bis(TertiaryButylAmino) Silane (BTBAS or C8H22N2Si) and Disilane (DS or Si2H6).

Step104further includes patterning the mask layer212by a procedure including a lithography patterning process and an etching process. In the present embodiment, a patterned photoresist layer is formed on the hard mask layer212using a photolithography process including photoresist coating, soft baking, exposing, post-exposure baking (PEB), developing, and hard baking. Then, the mask layer212is etched through the openings of the patterned photoresist layer, forming a patterned mask layer212, by the etching process. The patterned photoresist layer is removed thereafter using a suitable process, such as wet stripping or plasma ashing. In one example, the etching process includes applying a dry (or plasma) etch to remove the mask layer212within the openings of the patterned photoresist layer. In another example, the etching process includes applying a plasma etch to remove the SiN layer216within the openings of the patterned photoresist layer, and a wet etch with a hydrofluoric acid (HF) solution to remove the SiO layer214within the openings. In another example, the etching process includes applying a plasma etch to remove the SiN layer216within the openings but the SiO layer214remains at this processing stage.

The patterned mask layer212includes multiple openings defining a multi-fin device region (or multi-fin region)218and one or more intra-device regions220in the semiconductor substrate210. The multi-fin region218is configured for a multi-fin device, such as a multi-fin field-effect transistor (FET). In the present embodiment, the multi-fin device includes three exemplary fins. In a particular example, the multi-fin FET includes a metal-oxide-semiconductor (MOS) FET. The inter-device regions220are configured for isolation between two neighboring multi-fin transistors.

FIG. 2illustrates one multi-fin device. Other multi-fin devices may present. For example, another multi-fin device is approximate the multi-fin device in the multi-fin region218from the left side and separated by the inter-device region220in the left side.

Further, the patterned mask layer212includes multiple features222within the multi-fin region218. Each of the multiple features222defines a fin-like active region. The multiple features222are separated by intra-device regions224, respectively. The intra-device regions224are designed for intra-device isolation between the fin-like active regions.

The patterned mask layer212includes a first openings226aligned with the inter-device regions220and a second openings228aligned with the intra-device regions224. The first openings226(and the corresponding inter-device regions220) each include a first width W1. The second openings228(and the corresponding intra-device regions224) each include a second width W2. The first width W1is substantially greater than the second width W2. In the present embodiment, the first width W1is greater than about 200 nm and the second width W2ranges between about 10 nm and about 30 nm. A pitch P of the multi-fin device is defined as a distance from a location of a fin to the same location of a neighboring fin. In the present embodiment, the pitch of the multi-fin device is less than about 80 nm.

Referring toFIGS. 1 and 3, the method100proceeds to step106by forming a material layer232on the semiconductor substrate210and the patterned mask layer212. The exemplary mask layers214and216are not shown here for simplicity. The thickness T of the material layer232is equal to or greater than half the second width W2, formulated as T=>W2/2, such that the material layer232substantially fills in the second openings228. The thickness T of the material layer232is substantially less than half of the first width W1, formulated as T<W1/2, such that the first openings226is not substantially filled, as illustrated inFIG. 3. In the present embodiment, the thickness T is equal to or greater than about 5 nm if the second width is about the 10 nm or is equal to or greater than about 15 nm if the second width is about the 30 nm. The material layer232includes a dielectric material. In the present embodiment, the material layer232includes silicon oxide, formed by CVD or other suitable technology.

Referring toFIGS. 1 and 4, the method100proceeds to step108by performing a first etching process to the material layer232. The material layer232within the first openings226is substantially removed by the first etching process such that the semiconductor substrate210within the first openings220is exposed. The material layer232on the multiple features222of the patterned mask layer212is substantially removed by the first etching process as well. However, only top portions of the material layer232within the second openings228are removed. The semiconductor substrate210within the second opening228is still covered by the remained portions of the material layer232. In one embodiment, the first etching process implements a wet etch using an etch solution that effectively removes the material layer232. In the present embodiment, the material layer232includes silicon oxide and the first etching process uses a HF solution to etch the material layer232. If the SiO layer214of the mask layer212is not removed at step104, then the first etching process collectively removes the SiO layer214and the material layer232within the first openings226.

Under the relationships among the first width W1, second width W2and the thickness T, the first etching process is aligned to completely remove the material layer232within the first openings220. The material layer232is thus patterned to expose the semiconductor substrate210within the first openings226. The material layer232is thus patterned by the first etching process self-aligned to the first openings226without using a lithography patterning process. Therefore, the first etching process is referred to as a self-aligned etching process. The fabrication cost is reduced and the defect issue is reduced as well.

Referring toFIGS. 1 and 5, the method100proceeds to step110by performing a second etching process to the semiconductor substrate210using the material layer232and the mask layer212as an etch mask. The semiconductor substrate210within the first openings226is etched by the second etching process, forming first trenches234in the inter-device region220(and within the first openings226) having a certain depth D0. In one embodiment, the depth D0ranges between about 1000 angstrom and about 1400 angstrom.

In one embodiment, the second etching process implements a dry etch. For example, the etchant of the second etching process includes plasma HBr, Cl2, SF6, O2, Ar, and He. In another example, the etchant includes plasma CF4, C3F8, C4F8, CHF3, CH2F2, or a combination thereof.

Referring toFIGS. 1 and 6, the method100proceeds to step112by performing a third etching process to the material layer232. The third etching process removes the material layer232, such as those within the second openings228. In one embodiment, the third etching process implements a wet etch. In the present example, the material layer232includes silicon oxide and the third etching process uses a HF solution to remove the material layer232. After the completion of the third etching process, the semiconductor substrate210within the first and openings are exposed.

Referring toFIGS. 1 and 7, the method100proceeds to step114by performing a fourth etching process to the semiconductor substrate210using the mask layer212as an etch mask. The semiconductor substrate210within the first openings226is further etched by the fourth etching process. Thus the first trenches234in the inter-device region220are deeper and reach a first depth D1. The semiconductor substrate210within the second openings228is etched by the fourth etching process, forming second trenches236in the intra-device region218(and within the second openings228) having a second depth D2less than the first depth D1. In one embodiment, the first depth D1ranges between about 1600 angstrom and about 2000 angstrom, and the second depth D2ranges between about 400 angstrom and about 800 angstrom.

In one embodiment, the fourth etching process is similar to the second etching process. For example, the fourth etching process implements a dry etch. In one particular example, the etchant of the fourth etching process includes plasma HBr, Cl2, SF6, O2, Ar, and He. In another particular example, the etchant includes plasma CF4, C3F8, C4F8, CHF3, CH2F2, or a combination thereof.

FIG. 8is a flowchart of a method300for making a semiconductor device constructed according to various aspects of the present disclosure in another embodiment. The semiconductor device includes a multi-fin structure and a dual-depth isolation structure.FIGS. 9 through 14are sectional views of a semiconductor structure400at various fabrication stages and constructed according to other embodiments. The method300is similar to the method100ofFIG. 1. However, the fourth etching process ofFIG. 1is implemented prior to the formation of the material layer232according to the present embodiment. The semiconductor structure400and the method300of making the same are collectively described with reference toFIGS. 8 through 14.

Referring toFIGS. 8 and 9, the method300begins at step302by providing a semiconductor substrate210. The semiconductor substrate210includes silicon. Alternatively, the substrate includes germanium, silicon germanium or other proper semiconductor materials. The semiconductor substrate210also includes various doped regions such as n-well and p-wells. In one embodiment, the semiconductor substrate210includes an epi semiconductor layer. In another embodiment, the semiconductor substrate210includes a buried dielectric material layer for isolation formed by a proper technology.

Still referring toFIGS. 8 and 9, the method300proceeds to step304by forming a patterned mask layer212. In one embodiment, the patterned mask layer212is a hard mask layer having one or more suitable dielectric materials. In the present embodiment, the mask layer212includes a SiO layer214formed on the semiconductor substrate210and a SiN layer216formed on the SiO layer214(not shown for simplicity). In one example, the SiO layer214includes a thickness ranging between about 5 nm and about 15 nm. In another example, the SiN layer216includes a thickness ranging between about 40 nm and about 120 nm. In another embodiment, step104includes forming the SiO layer214by thermal oxidation and forming the SiN layer216by chemical vapor deposition (CVD).

Step104further includes patterning the mask layer212by a procedure including a lithography patterning process and an etching process. In the present embodiment, a patterned photoresist layer is formed on the hard mask layer212using a photolithography process. Then, the mask layer212is etched through the openings of the patterned photoresist layer, forming a patterned mask layer212, by the etching process. The patterned photoresist layer is removed thereafter using a suitable process, such as wet stripping or plasma ashing. In one example, the etching process includes applying a dry etch to remove the mask layer212within the openings of the patterned photoresist layer. In another example, the etching process includes applying a plasma etch to remove the SiN layer216within the openings of the patterned photoresist layer, and a wet etch with a HF solution to remove the SiO layer214within the openings.

The patterned mask layer212includes multiple openings defining a multi-fin device region (or multi-fin region)218and one or more intra-device regions220in the semiconductor substrate210. The multi-fin region218is configured for a multi-fin device, such as a multi-fin FET. In the present embodiment, the multi-fin device includes three exemplary fins. In a particular example, the multi-fin FET includes a MOS FET. The inter-device regions220are configured for isolation between two neighboring multi-fin transistors.

Further, the patterned mask layer212includes multiple features222within the multi-fin region218. Each of the multiple features222defines a fin-like active region. The multiple features222are separated by intra-device regions224, respectively. The intra-device regions224are designed for intra-device isolation between the fin-like active regions.

The patterned mask layer212includes a first openings226aligned with the inter-device regions220and a second openings228aligned with the intra-device regions224. The first openings226(and the corresponding inter-device regions220) each include a first width W1. The second openings228(and the corresponding intra-device regions224) each include a second width W2. The first width W1is substantially greater than the second width W2. In the present embodiment, the first width W1is greater than about 200 nm and the second width W2ranges between about 10 nm and about 30 nm. A pitch P of the multi-fin device is defined as a distance from a location of a fin to the same location of a neighboring fin. In the present embodiment, the pitch of the multi-fin device is less than about 80 nm.

Referring toFIGS. 8 and 10, the method300proceeds to step306by performing a firth etching process to the semiconductor substrate210using the mask layer212as an etch mask. The semiconductor substrate210within the first openings226and the second openings228is etched by the first etching process, forming first trenches234and second trenches236, as illustrated inFIG. 10. The first trenches234are within the inter-device region220. The second trenches234are within the intra-device region224. The first and second trenches now have the second depth D2. In one embodiment, the second depth D2ranges between about 400 angstrom and about 800 angstrom.

In one embodiment, the first etching process is similar to the fourth etching process ofFIG. 1. For example, the fourth etching process implements a dry etch. In one particular example, the etchant of the fourth etching process includes plasma HBr, Cl2, SF6, O2, Ar, and He. In another particular example, the etchant includes plasma CF4, C3F8, C4F8, CHF3, CH2F2, or a combination thereof.

Referring toFIGS. 8 and 11, the method300proceeds to step308by forming a material layer232on the semiconductor substrate210and the patterned mask layer212. The thickness T of the material layer232is equal to or greater than half the second width W2, formulated as T=>W2/2, such that the material layer232substantially fills in the second openings228. The thickness T of the material layer232is substantially less than half of the first width W1, formulated as T<W1/2, such that the first openings226is not substantially filled the first trenches, as illustrated inFIG. 11. In the present embodiment, the thickness T is equal to or greater than about 5 nm if the second width is about the 10 nm or is equal to or greater than about 15 nm if the second width is about the 30 nm. The material layer232includes a dielectric material. In the present embodiment, the material layer232includes silicon oxide, formed by CVD or other suitable technology.

Referring toFIGS. 8 and 12, the method300proceeds to step310by performing a second etching process to the material layer232. The material layer232within the first trenches234is substantially removed by the second etching process such that the semiconductor substrate210within the first openings220is exposed. The material layer232on the multiple features222of the patterned mask layer212is substantially removed by the second etching process as well. However, only top portions of the material layer232within the second openings228are removed. The semiconductor substrate210within the second opening228is still covered by the remained portions of the material layer232. In one embodiment, the second etching process implements a wet etch using an etch solution that effectively removes the material layer232. In another embodiment, the second etching process includes a dry etch. In the present embodiment, the second etching process implements a dry etch to the material layer232, resulting in spacers of the material layer232formed on the side of the first trenches234.

Under the relationships among the first width W1, second width W2and the thickness T, the second etching process is aligned to completely remove the material layer232within the first trenches234. The material layer232is thus patterned to expose the semiconductor substrate210within the first openings226. The material layer232is thus patterned by the second etching process self-aligned to the first openings226without using a lithography patterning process. Therefore, the second etching process is referred to as a self-aligned etching process. The fabrication cost is reduced accordingly.

Referring toFIGS. 8 and 13, the method300proceeds to step312by performing a third etching process to the semiconductor substrate210using the material layer232and the mask layer212as an etch mask. The third etching process is similar to the second etching process ofFIG. 1. The semiconductor substrate210within the first openings226is further etched by the third etching process. The first trenches234in the inter-device region220(and within the first openings226) now have the first depth D1. In one embodiment, the depth D1ranges between about 1400 angstrom and about 2000 angstrom. In the present embodiment, a step-wise sidewall may be formed in the first trenches234.

In one embodiment, the second etching process implements a dry etch. For example, the etchant of the second etching process includes plasma HBr, Cl2, SF6, O2, Ar, and He. In another example, the etchant includes plasma CF4, C3F8, C4F8, CHF3, CH2F2, or a combination thereof.

Referring toFIGS. 8 and 14, the method300proceeds to step314by performing a fourth etching process to the material layer232. The fourth etching process is similar to the third etching process ofFIG. 1. The fourth etching process removes the material layer232, such as those within the intra-device regions224. In one embodiment, the fourth etching process implements a wet etch. In the present example, the material layer232includes silicon oxide and the fourth etching process uses a HF solution to remove the material layer232. After the completion of the fourth etching process, the first trenches234have the first depth D1and the second trenches236have the second depth D2less than the first depth D1. In one embodiment, the first depth D1ranges between about 1600 angstrom and about 2000 angstrom, and the second depth D2ranges between about 400 angstrom and about 800 angstrom.

Other processing steps may be implemented subsequently. In one embodiment, a dielectric material layer is partially filled in the first trenches234and the second trenches236, forming first shallow trench isolation (STI) features in the inter-device regions220and second STI features in the intra-device regions224. The formation of various STI features includes filling the trenches by one or more dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench. In one embodiment, filling various STI features includes growing a thermal oxide trench liner to improve the trench interface, filling the trench with silicon oxide or silicon nitride using a CVD technology, and optionally performing an thermal annealing.

In another embodiment, the method100further includes an etch step to remove the patterned mask layer212by a suitable etching process. In one example when the mask layer212having the SiO layer214and the SiN layer216, the etch step includes a hot phosphoric acid (H3PO4) solution to remove silicon nitride. In another embodiment, the first etching process additionally includes a HF solution to remove silicon oxide after the H3PO4 solution is applied.

In yet another embodiment, the method100further includes forming epi semiconductor layer on the active regions within the multi-fin device region218using an epi growth technology. In one example, the epi semiconductor layer includes a semiconductor material different from the semiconductor material of the semiconductor substrate201.

In an alternative embodiment, the trenches234and236are completely filled with one or more dielectric materials. Then the semiconductor material of the active regions within the multi-fin device region218is etched back. Thereafter, an epi growth is performed to form multi-fin semiconductor features within the multi-fin device region218. In furtherance of this alternative embodiment, the processing steps includes filling the trenches by one or more dielectric materials (such as silicon oxide, silicon nitride, or silicon oxynitride); performing a chemical mechanical planarization (CMP) process to remove the excessive dielectric material(s) and planarize the substrate surface; etching back the semiconductor material of the active areas within the multi-fin device region218; and performing an epi growth to form one or more multi-fin semiconductor features within the multi-fin device region218.

In another embodiment, the method100includes a procedure to form a gate stack over the multiple fin-like active regions. The gate stack includes a gate dielectric material layer and a gate electrode disposed on the gate dielectric material layer. The gate dielectric layer includes silicon oxide, high k dielectric material or combinations thereof. The gate electrode includes polysilicon, metal, other conductive material with proper work functions (for n-type FET and p-type FET, respectively), and combinations thereof. The formation of gate stack includes deposition steps, lithography patterning step and etching step. The gate stack is configured perpendicular to the multiple fin-like active regions.

In another embodiment, the method100includes another procedure to form source and drain regions in the multi-fin device region218. In one example, the source and drain regions include light doped drain (LDD) regions and heavily doped source and drain (S/D) features, collectively referred to as source and drain regions, formed by various ion implantation processes. When the multi-fin device region218includes both n-type FETs (nFETs) and p-type FETs (pFETs), the source and drain regions are formed for the n-type FETs and the p-type FETs, respectively, using proper doping species. As one example for nFETs, the LDD features are formed by an ion implantation with a light doping dose. Thereafter, spacers are formed by dielectric deposition and anisotropic etch, such as plasma etch. Then the heavily doped S/D features are formed by an ion implantation with a heavy doping dose. The various source and drain features of the pFETs can be formed in a similar procedure but with opposite doping type. In one embodiment of the procedure to form various source and drain features for both nFETs and pFETs, the LDD features of nFETs are formed by an ion implantation while the regions of pFETs are covered by a patterned photoresist layer; the LDD features of pFETs are formed by an ion implantation while the regions of nFETs; then spacers are formed to nFET gate stacks and pFET gate stacks by deposition and etch. the S/D features of nFETs are formed by ion implantation while the regions of pFETs are covered by another patterned photoresist layer; and the S/D features of pFETs are formed by ion implantation while the regions of nFETs are covered by another patterned photoresist layer. In one embodiment, a high temperature annealing process is followed to activate the various doping species in the source and drain regions.

In yet another embodiment, an inter-level dielectric (ILD) layer is formed on the semiconductor substrate210. The ILD layer includes silicon oxide, low k dielectric material, other suitable dielectric materials, or combinations thereof. The ILD layer is formed by a suitable technique, such as CVD. For example, a high density plasma CVD can be implemented to form the ILD layer.

In yet another embodiments, the method100further includes a procedure to form various interconnection features designed to couple various devices (including various multi-fin devices) to form functional circuits. The interconnection features include vertical interconnects, such as contacts and vias, and horizontal interconnects, such as metal lines. The various interconnection features may use various conductive materials including copper, tungsten and silicide. In one example, a damascene process is used to form copper-based multilayer interconnection structure. In another embodiment, tungsten is used to form tungsten plug in the contact holes. In another example, silicide is used to form various contact on source and drain regions for reduced contact resistance.

In another embodiment, a pFET has a strained structure for enhanced carrier mobility and improved device performance. In furtherance of the embodiment, silicon germanium (SiGe) is formed in the source and drain regions of the pFET to achieve a proper stress effect. In another embodiment, an nFET has a strained structure for enhanced carrier mobility and improved device performance. In furtherance of the embodiment, silicon carbide (SiC) is formed in the source and drain regions of the nFET to achieve a proper stress effect.

The present disclosure can be used in various applications where multi-fin devices are incorporated for enhanced performance. For example, the multi-fin devices can be used to form static random access memory (SRAM) cells. In other examples, the multi-fin devices can be incorporated in various integrated circuit, such as logic circuit, dynamic random access memory (DRAM), flash memory, or imaging sensor.

Thus, the present disclosure provides a method of forming a multi-fin device. The method includes forming, on a semiconductor substrate, a patterned mask layer that includes a first opening having a first width W1and a second opening having a second width W2less than the first width, and defines a multi-fin device region and an inter-device region. The inter-device region is aligned with the first opening. The multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.

In one embodiment, the forming of the material layer includes forming the material layer having a thickness T that satisfies W1>2*T>=W2. In another embodiment, the method further includes performing a fourth etching process to etch the semiconductor substrate in the first and second openings, forming a second trench in the intra-device region. In one embodiment, the fourth etching process is implemented after the third etching process. In an alternative embodiment, the fourth etching process is implemented before the forming of the material layer. The first trench has a first depth D1and the second trench has a second depth D2substantially less than the first depth D1. In another embodiment, the fourth etching process includes a dry etching process. In other embodiments, the forming of the material layer includes implementing a chemical vapor deposition (CVD) process to form a silicon oxide layer; and the forming of the patterned mask layer includes forming a silicon nitride layer using another CVD process. In yet other embodiments, the second etching process includes a dry etching process; and the third etching process includes a wet etching process. The first etching process removes only top portion of the material layer within the second opening.

The present disclosure also provides another embodiment of a method of forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate, wherein the patterned mask layer includes a first opening having a first width W1and a second opening having a second width W2less than the first width W1; forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer has a thickness T satisfying W1>2*T>=W2and substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening using the patterned mask layer and the material layer as an etch mask; and performing a third etching process to remove the material layer in the second opening.

The patterned mask layer defines a multi-fin device region and an inter-device region. The inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. In one embodiment, the method further includes performing a fourth etching process to the semiconductor substrate within the first and second openings, wherein the second and fourth etching processes form a first trench and a second trench of the semiconductor substrate, wherein the first trench is aligned with the first opening and has a first depth D1, and the second trench is aligned with the second opening and has a second depth D2less than the first depth D1. In other embodiments, the performing of the second etching process implements a dry etching process to the semiconductor substrate within the first opening; and the performing of the fourth etching process implements another dry etching process to the semiconductor substrate within the first opening and the second opening. In another embodiment, the fourth etching process is implemented before the forming of the material layer. In an alternative embodiment, the fourth etching process is implemented after the performing of the third etching process. In yet another embodiment, the patterned mask layer includes a thermal silicon oxide layer and a silicon nitride layer on the thermal silicon oxide layer. In yet another embodiment, the forming of the material layer includes implementing a chemical vapor deposition (CVD) process to form a silicon oxide layer. In yet another embodiment, the method further includes forming a multi-fin field-effect transistor in the multi-fin device region.

The present disclosure also provide one embodiment of a multi-fin device. The multi-fin device includes a multi-fin transistor formed on a semiconductor substrate, wherein the multi-fin transistor includes at least two fin-like active regions; an inter-device isolation feature formed in the semiconductor substrate, adjacent the multi-fin transistor, and having a first width W1and a first depth D1; and an intra-device isolation feature formed in the semiconductor substrate, disposed between the two fin-like active regions, and having a second width W2less than W1and a second depth D2less than D1.