Digital gain controller and gain control method

A current optimal gain can be calculated directly from an effective value of an input signal by increasing the speed of the initial response without using a feedback loop, in a manner such that a mean power of the input signal and the square-root of the mean power are calculated as an inverse of the effective value, and the input signal is multiplied by the product of this inverse of the number and predetermined effective value.

BACKGROUND OF THE INVENTION 
The present invention relates to a digital gain controller and gain control 
method in a modulator-demodulator (MODEM). 
A signal processing section in a conventional MODEM which is standardized 
by the CCITT recommendation V.29, V.27 ter is generally comprised of a 
software of digital signal processor (DSP). 
In general, a signal level which is inputted into a reception-side MODEM 
from a communication line differs every time of communication. The signal 
level needs to be amplified to be a constant level so that precision of a 
signal processing can be improved by efficiently utilizing the limited 
dynamic range of the DSP. Otherwise, the data error rate is increased due 
to the low precision of the signal processing. 
Therefore, an automatic gain controller (AGC) adjusting an amplifying gain 
is internally placed in the MODEM in response to a reception signal level. 
In the MODEM V.29, V.27 ter, a training signal sequence is transmitted 
prior to a data transmission for initializing each signal processor in the 
reception-side MODEM. The PN segment in this training signal sequence is a 
signal for initializing an adaptive equalizer. If the PN segment is not 
correctly demodulated, the initialization cannot be processed. Therefore, 
a correctly demodulated signal needs to be obtained in a manner such that 
initializations for the signal processors except for the equalizer are 
completed prior to the PN segment. For this reason, the AGC gain must be 
converged before the PN segment. That is, an AGC having quick initial 
response is required. 
However, efficiency of the DSP has been improved recently and the bit 
length of a signal to be processed and operation speed are both increased. 
Therefore, the signal processing which was conventionally performed 
outside of the DSP because of the precision of the signal processing to be 
obtained and the limitation of operation time to be spent can now be 
executed inside of the DSP. In the case of the AGC, an analog type AGC 
circuit has been conventionally arranged outside of the DSP, however, a 
digital type AGC generally comprises the DSP software at present. 
FIG. 13 is a block diagram illustrating the structure of the conventional 
feedback type digital AGC. The character .delta. is a positive constant, 
P.sub.0 is a predetermined power, and r.sub.0 (n), r.sub.0 '(n), P.sub.0 
(n), e.sub.0 (n), g.sub.0 (n) are signal values at each section (which 
will be described later) at the sampling time n, which respectively 
represent an input signal, output signal, mean power signal of output, 
error signal, and gain signal. 
In FIG. 13, the gain signal g.sub.0 (n-1) which has been decided in one 
sampling earlier than n and stored in the delay 22 is multiplied by the 
input signal r.sub.0 (n). The output signal r.sub.0 '(n) is obtained by: 
EQU r.sub.0 '(n)=g.sub.0 (n-1).multidot.r.sub.0 (n) (1) 
Then, this output signal r.sub.0 '(n) is squared by the multiplier 27 and 
averaged by the low pass filter (LPF) 26. The mean power signal P.sub.0 
(n) is obtained by: 
EQU P.sub.0 (n)=E(r.sub.0 '(n).sup.2) (2) 
The "E" represents "mean". 
Then, an error signal e.sub.0 (n) of the above-mentioned mean power signal 
P.sub.0 (n) and the predetermined power P.sub.0 is calculated in the power 
error calculator 25 by: 
EQU e.sub.0 (n)=P.sub.0 -P.sub.0 (n) (3) 
As apparent from the above equation (3), in the case where the mean power 
of the output signal r.sub.0 '(n) is greater than the predetermined power, 
the error signal e.sub.0 (n) becomes negative, while in the case where the 
mean power is smaller than the predetermined power, it becomes positive. 
Then, the error signal e.sub.0 (n) is multiplied by a constant in the 
constant multiplier 24, and a cumulative addition is performed by the 
adder 23 and delay 22. 
The gain signal which is stored in the delay 22 is obtained as the 
following and used as a gain at the sampling time n+1: 
EQU g.sub.0 (n)=g.sub.0 (n-1)+.delta..multidot.e.sub.0 (n)=g.sub.0 
(n-1)+.delta.[P.sub.0 -P.sub.0 (n)] (4) 
As apparent from the equation (4), in the conventional AGC circuit, in the 
case where the mean power P.sub.0 (n) of the output signal is greater than 
the predetermined power P.sub.0, a gain is decreased. While in the case 
where the mean power P.sub.0 (n) is smaller than the predetermined power 
P.sub.0, a gain is increased. That is, in the AGC method, the algorithm 
which sequentially corrects a gain so that the error e.sub.0 (n) of the 
mean power P.sub.0 (n) of the output signal and predetermined power 
P.sub.0 approaches to zero is directed. If a value of the positive 
constant .delta. is appropriately selected, the mean power P.sub.0 (n) of 
the output signal is eventually converged into the predetermined power 
P.sub.0 by repeating this operation. 
Since it is apparent from the equation (3) that e.sub.0 (n)=0, and from the 
equation (4), g.sub.0 (n)=g.sub.0 (n-1), the gain is converged into a 
certain value. 
The traceability of the AGC gain has a relation with the positive constant 
.delta.. That is, a change of the gain for an operation is obtained from 
the equation (4) as the following: 
EQU .vertline.g.sub.0 (n)-g.sub.0 (n-1).vertline.=.delta..vertline.e.sub.0 
(n).vertline. (5) 
Therefore, if .delta. is set to a large value, the change of the gain is 
increased, and the traceability of the gain is quickened. 
As described above, the characteristics that an initial response is as 
quick as possible and the gain is not fluctuated after the PN segment so 
that the correctly demodulated signal can be obtained are required for the 
AGC. Therefore, in general, the speed of the traceability before the PN 
segment is increased by changing the positive constant .delta., and the 
speed of traceability after the PN segment is decreased. 
However, in the aforementioned conventional feedback type digital AGC, if 
the constant .delta. is increased to increase the speed of the 
traceability, large fluctuation is caused because the gain change becomes 
susceptible. In the worst case, the gain is diverged. That is, the 
conventional feedback type digital AGC has the limitation to increase the 
speed of the initial response since the gain is sequentially corrected. 
Therefore, in the case where a signal level is quite large, the drawback is 
that the convergence of the gain cannot be completed before the PN segment 
and the adaptive equalizer cannot be initialized correctly. 
SUMMARY OF THE INVENTION 
Accordingly, it is an object of the present invention to provide a digital 
gain controller and gain control method which calculates a current optimal 
gain obtained directly from the effective value of an input signal by 
increasing an initial response without using a feedback loop. 
According to the present invention, the foregoing object is attained by 
providing a digital gain controller comprising: operation means for 
calculating the inverse of an effective value of an input signal; first 
signal generation means for generating a gain signal in a manner such that 
the inverse of the effective value is multiplied by a predetermined 
effective value; and second signal generation means for generating an 
output signal in a manner such that the input signal is multiplied by the 
gain signal. 
It is another object of the present invention to provide a digital gain 
controller capable of converging a gain before a PN segment regardless of 
reception signal level. 
According to the present invention, the foregoing object is attained by 
providing a digital gain controller comprising: operation means for 
calculating a mean amplification of an input signal; first gain controller 
for generating an amplification signal which is proportional to the input 
signal having one-fourth of the ratio of the effective value of the input 
signal to the mean amplification based on the input signal as an effective 
value; and second gain controller for generating an output signal which is 
proportional to the amplification signal having an effective value which 
is equal to the predetermined effective value. 
Other features and advantages of the present invention will be apparent 
from the following description taken in conjunction with the accompanying 
drawings, in which like reference characters designate the same or similar 
parts throughout the figures thereof.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Preferred embodiments of the present invention will now be described in 
detail in accordance with the accompanying drawings. 
First Embodiment 
FIG. 1 illustrates a signal processing in the digital gain controller 
(which is referred to as a "controller" thereinafter) according to the 
first embodiment in the present invention. As shown in the diagram, the 
present controller is comprised of the multiplier 11, low pass filter 
(LPF) 12, operation apparatus 13 which calculates the inverse square-root 
of x for an arbitrary positive number x, constant multiplier 14, and 
multiplier 15. In the diagram, V.sub.0 is a predetermined effective value, 
and r(n), r'(n), Pi(n), g(n) are signal values in each portion of the 
controller at the sampling time n, which respectively represent an input 
signal, output signal, mean power signal of input, and gain signal. 
Furthermore, the present controller is comprised of the software of the 
floating point type DSP for the signal processing. 
The mean power signal P.sub.i (n) is obtained in a manner such that the 
input signal r(n) is squared by the multiplier 11 and averaged by the LPF 
12. That is: 
EQU P.sub.i (n)=E(r(n).sup.2) (6) 
Then, the mean power signal P.sub.i (n) is inputted into the operation 
apparatus 13 and P.sub.i (n).sup.-1/2 is calculated. The value P.sub.i 
(n).sup.-1/2 which is outputted from the operation apparatus 13 is 
multiplied by the predetermined effective value V.sub.0 in the constant 
multiplier 14, and the gain signal g(n) is obtained by: 
##EQU1## 
The denominator of the above equation (7), the square root of 
E(r(n).sup.2), represents an effective value of the input signal r(n). 
The output signal r'(n) is obtained in a manner such that the gain signal 
g(n) is multiplied by the input signal r(n) in the multiplier 15. That is: 
##EQU2## 
By the equation (8), the effective value of the output signal r'(n) is: 
##EQU3## 
It is apparent from the above equation that the effective value of the 
output signal is equal to the predetermined effective value V.sub.0. 
Accompanying with the flowcharts in FIGS. 2A and 2B, the internal 
processing in the operation apparatus 13 according to the present 
embodiment is described in detail. In the same flowcharts, a, b, c, d, de, 
and df respectively represent values inputted in the registers a, b, c, d, 
de, and df. As shown in FIG. 3, the register d is comprised of the sign 
bit S, M-bit exponent de, and N-bit mantissa df. The register de 
represents integers 0.about.(2.sup.M -1) and the register df represents 
decimals 0.about.(1-2.sup.-N). These registers can be processed as 
independent registers. 
In the DSP used in the controller according to the present embodiment, the 
following relation is formed: 
EQU d=(-1).sup.S .times.(1+df).times.2.sup.de-K (10) 
where K represents a constant integer in 0.about.(2.sup.M -1). In addition, 
the structure of the register is similar to that of the register shown in 
FIG. 3, and the relation indicated in the equation (10) can be also formed 
on the registers a and b. 
First, an input signal to the operation apparatus 13 is inputted into the 
register d. The value of the input signal at this time is set to as the 
following: 
EQU d.sub.0 =(-1).sup.0 .times.(1+df.sub.0).times.2.sup.de0.sub.-K (11) 
The principal of the operation apparatus 13 is to multiply the 
inverse-square root of the mantissa (1+df.sub.0) by the inverse-square 
root of the exponent 2.sup.de0.sub.-K. In the procedure of processings 
which will be described below, steps S2-S9 are the operations for the 
mantissa and other steps are for the exponent. 
In FIG. 2A, in step S1, as a preparation for the operations for the 
exponent after step S10, de=de.sub.0 is saved in the address M0 in the 
memory. Then, in step S2, the constant integer K is inputted into the 
register de. If d is determined as d.sub.2 at this time, only the mantissa 
is appeared as the following: 
EQU d.sub.2 =(1+df.sub.0).times.2.sup.K-K =(1+df.sub.0) (12) 
For df.sub.0 and d.sub.2, the following relations are formed: 
EQU 0.ltoreq.df.sub.0 .ltoreq.(1-2.sup.-N) (13) 
EQU 1.ltoreq.d.sub.2 .ltoreq.(2-2.sup.-N) (14) 
Therefore, the mantissa is d.sub.2.sup.-1/2, the inverse-square root of 
d.sub.2 which is in the range of 1.about.2. To obtain d.sub.2.sup.-1/2, an 
approximate value of d.sub.2.sup.-1/2 is calculated by the approximate 
polynomial. The obtained value is determined as an initial value and 
converged into a true value by the iterative method. 
In step S3, d=d.sub.2 is saved in the register a for later processings. In 
step 4, the approximate value f(d.sub.2) of d.sub.2.sup.-1/2 is 
calculated by the following approximate polynomial and the result is 
inputted into the register d: 
EQU f(x).apprxeq.x.sup.-1/2 (1.ltoreq.x.ltoreq.2) (15) 
In this process, the value in the register a needs to be kept. 
If the value d at the completion of step S4 is determined as d.sub.4, the 
following equation is obtained: 
EQU d.sub.4 =f(d.sub.2).apprxeq.d.sub.2.sup.-1/2 (16) 
From the view of the amount of operation, a desirable approximate 
polynomial used here is one in which the order is as low as possible 
having an efficient approximate precision. For this reason, a coefficient 
of the polynomial f(x) is determined so that f(x) becomes a Chebyshev 
approximation of x.sup.-1/2. As more particularly describing, a 
coefficient of the polynomial f(x) of p-th order is determined so as to 
minimize the following: 
##EQU4## 
In steps S5-S8, d4.apprxeq.d.sub.2.sup.-1/2 is determined as an initial 
value and a true value of d.sub.2.sup.-1/2 is calculated by the iterative 
method. That is, in step S5, a number of occurrence R is inputted into the 
repeat counter C, and in step S6, the value d is renewed by the 
two-variable function g(x, y). Again, the value in the register a needs to 
be kept here. 
Furthermore, the function g(x, y) is determined so that the series {X.sub.n 
} which is defined by the following recursion formula (18) is to be as the 
following equation (19): 
##EQU5## 
In steps S7 and S8, in the case where the value of the repeat counter C is 
not 1, decrement is performed and the process returns to step S6. Since 
when the processing enters to this processing loop, a=d.sub.2, d=d.sub.4 
.apprxeq.d.sub.2.sup.-1/2, if the value d is repeatedly renewed in step S6 
(that is, g(d, a).fwdarw.d), the value d approaches to a.sup.-1/2 
=d.sub.2.sup.-1/2. 
Since when the processing in step S6 is iterated for R times, the value of 
the repeat counter C becomes to 1 and the processing gets out of the 
aforementioned processing loop. The value d at this time is determined as 
d.sub.8. 
If the number of occurrence R is selected so that an error 
.vertline.d.sub.8 -d.sub.2.sup.-1/2 .vertline. at the completion of 
iteration is less than a numeric precision of the DSP, d.sub.8 can be 
regarded as a true value of d.sub.2.sup.-1/2. Therefore, from the equation 
(12), the following equation is obtained: 
EQU d.sub.8 =d.sub.2.sup.-1/2 =(1+df.sub.0).sup.-1/2 (20) 
In this way, the inverse square-root of the exponent of d.sub.0 is 
obtained. 
In step S9 in FIG. 2B, d=d.sub.8 is saved in the register a for later 
processings. In step S10, de=de.sub.0 which was saved in the address M0 in 
step S1 is returned to the register de and the NOT (inverse) operation is 
performed. This value is again saved in the address M0. At this time, the 
value of the address M0 is as the following: 
EQU (M0)=de.sub.0 =(2.sup.M -1)-de.sub.0 (21) 
In step S11, by using de=de.sub.0 , the following is calculated and the 
result is inputted into the register b: 
##EQU6## 
The [X] represents a maximum integer which is less than x. In step S11, 
the value in the register a needs to be kept. Furthermore, the value b at 
the completion of the processing in step S11 is: 
##EQU7## 
In step S12, a=d.sub.8 which was saved in step S9 is multiplied by the 
value b which was calculated in step S11, and the result is inputted into 
the register a. In this case, from the equations (20) and (22), the 
following equation is obtained: 
##EQU8## 
In step S13, de=de.sub.0 which has been saved in the address M0 in step 
S10 is returned to the register de and multiplied by 1/2. Thus, the 
integer [de.sub.0 /2] can be obtained. Furthermore, the register df is 
cleared. 
If the value d at this time is determined as d.sub.13, the following 
equation is formed: 
##EQU9## 
In step S14, the value a obtained in step S12 is multiplied by the value d 
obtained in step S13, and the result is inputted into the register d. If 
the value d at this time is determined as d.sub.14, the following equation 
is obtained from the equations (23) and (24): 
##EQU10## 
If the equation (21) is substituted in the equation (25), the following 
equation is obtained: 
EQU d.sub.14 =(1+df.sub.0).sup.-1/2 .times.(2.sup.de0-K).sup.-1/2(26) 
Thus, the inverse-square root of the exponent is obtained. If the equation 
(11) is used, the following equation can be obtained: 
EQU d.sub.14 ={(1+df.sub.0).times.2.sup.de0.sub.-K)}.sup.-1/2 
=d.sub.0.sup.-1/2(27) 
Thus, the value d at the completion of the processing in FIG. 2B is the 
inverse square-root of d at the beginning of the processing. 
In this way, the operation apparatus 13 is comprised of the software of the 
floating point type DSP. 
As described above, an optimum gain can be obtained directly from the 
effective value of the input signal in the digital gain controller without 
using the feedback loop in a manner such that the inverse of the effective 
value of the input signal is calculated, and is multiplied by the 
predetermined effective value, which is a gain. 
In the controller according to the present embodiment, since the initial 
response is quickened in comparison with that of the feedback type AGC, 
the gain can be converged before the PN segment regardless of the signal 
level. 
Then, the modified embodiment of the first embodiment is described. 
Modification 
The structure of the register d of the DSP according to the modified 
embodiment is shown in FIG. 4. The register d is comprised of the M-bit 
exponent de and the N-bit mantissa df, and the following relation is 
formed: 
EQU d={(-1).sup.S .times.1/2+df}.times.2.sup.de (10-1) 
The "S" in the mantissa is a sign bit, and the formats for de and df are 
both complements of 2. The "de" represents integers in -2.sup.M-1 
.about.2.sup.M-1 -1, and "df" represents decimals in -2.sup.-1 
.about.2.sup.-1 -2.sup.-N. 
Furthermore, the input signal value to the operation apparatus 13 is 
determined as the following: 
EQU d.sub.0 =(1/2+df.sub.0).times.2.sup.de0 (d.sub.0 .gtoreq.0) (11-1) 
The principle of the operation apparatus 13 is that the inverse square-root 
of the mantissa (1/2+df.sub.0) is multiplied by the inverse square-root of 
the exponent 2.sup.de0. 
In the procedure of the processings according to the modified embodiment, 
when the register de is cleared in the processing in step S2A, the value 
d.sub.2 is as following: 
EQU d.sub.2 =(1/2+df.sub.0).times.2.sup.0 =1/2+df.sub.0 (12-1) 
Since the input signal d.sub.0 is over 0, the following relations are 
formed: 
EQU 0.ltoreq.df.sub.0 .gtoreq.2.sup.-1 -2.sup.-N (13-1) 
EQU 2.sup.-1 .ltoreq.d.sub.2 .ltoreq.1-2.sup.-N (14-1) 
The mantissa is the inverse square-root of d.sub.2 in the range of 2.sup.-1 
.about.1. 
Therefore, as an approximate polynomial, the following is used: 
EQU f(x).apprxeq.x.sup.-1/2 (2.sup.-1 .ltoreq.x.ltoreq.1) (15-1) 
The approximate value f(d.sub.2) of d.sub.2.sup.-1/2 is calculated by the 
above inequalities, and the result is inputted into the register d. The 
polynomial f(x) is a polynomial of the p-th order to the fixed p having a 
coefficient such that the following inequalities to be the minimum value: 
##EQU11## 
By repeating the renewal of the value d in steps S6-S8 in FIG. 2A, the 
value d.sub.8, which is the value d when the processing gets out of the 
loop is: 
EQU d.sub.8 =d.sub.2.sup.-1/2 =(1/2+df.sub.0).sup.-1/2 (20-1) 
Thus, the inverse square-root of the mantissa of d.sub.0 can be obtained. 
In the processing corresponding to that of step S11 in FIG. 2B in the 
modified embodiment, the following can is calculated by using de=de.sub.0 
: 
EQU 2.sup.{3/2+(de/2-[de/2])} (21-2) 
The result is inputted into the register b. Therefore, the value b at the 
completion of this processing is: 
EQU b=2.sup.{3/2+(de0/2-[de0 .sub./2])} (22-1) 
Furthermore, in step S12, the following equation is obtained from the 
equations (20-1) and (22-1): 
##EQU12## 
In the modified embodiment, the value d, that is, the value d.sub.13 at 
the completion of step S13 is: 
EQU d.sub.13 =(1/2+0).times.2.sup.[de0/2] =2.sup.[de0/2]-1 (24-1) 
When the obtained value a is multiplied by d=d.sub.13, the value d, that 
is, d.sub.14 is as the following from the equations (23-1) and (24-1): 
##EQU13## 
Since de.sub.0 +1=-de.sub.0, the value d.sub.14 is obtained as following: 
EQU d.sub.14 =(1/2+df.sub.0).sup.-1/2 .times.(2.sup.de0).sup.-1/2(26-1) 
In this way, the inverse square-root of the exponent can be obtained. 
Furthermore, from the equation (11-1), the following equation is obtained: 
EQU d.sub.14 ={(1/2+df.sub.0).times.2.sup.de0 }.sup.-1/2 =d.sub.0.sup.-1/2( 
27-1) 
Therefore, the value d after the completion of the processing is the 
inverse square-root of d which is at the beginning of the processing. 
Second Embodiment 
The second embodiment according to the present invention is described 
below. 
FIG. 5 illustrates the structure of the digital automatic gain controller 
(which is referred to as a "controller" thereinafter) according to the 
second embodiment. The controller shown in FIG. 5 is comprised of the 
multiplier 31, low pass filter (LPF) 32, multiplier 33 multiplying by 
2.sup.n operation apparatus 34 calculating x.sup.-1/2 for 1/2.ltoreq.x&lt;1, 
multiplier 35 multiplying by the value in which the absolute value is 
larger than or equal to 1, multiplier 36 multiplying by the value in which 
the absolute value is less than 1, and constant multipliers 37 and 38. 
V.sub.0 is a predetermined effective value. 
Furthermore, r.sub.2 (n), r.sub.2 '(n), s.sub.2 (n), t.sub.2 (n), P.sub.i2 
(n), q.sub.2 (n), and K(n) are signal values at each portion of the 
controller at the sampling time n. Among those, K(n) is an integer and the 
other values are decimals in which the absolute values are less than 1. 
The controller shown in FIG. 5 is comprised of the software of the fixed 
point DSP. 
FIG. 6 is a fixed point format of the DSP according to the present 
embodiment. In the diagram, the character S, black dot, and character N 
respectively represent a sign bit, decimal, and total bit. Furthermore, 
the character M represents the total bit of the input signal r.sub.2 (n) 
and inputted into the upper M bit. However, (M-1).times.2.ltoreq.N-1 needs 
to be satisfied. 
In the controller shown in FIG. 5, the input signal r.sub.2 (n) is squared 
by the multiplier 31 and averaged by the LPF 32. The mean power signal 
P.sub.i2 can be obtained by: 
EQU P.sub.i2 (n)=E(r.sub.2 (n).sup.2) (28) 
Then, in the multiplier 33, the mean power signal P.sub.i2 is multiplied by 
2.sup.K(n)-1 while the following is calculated: 
EQU K(n)=-[log.sub.2 P.sub.i2 (n)] (29) 
In this way, the normalized power signal q.sub.2 is obtained. However, [x] 
represents a maximum integer which is less than x. The multiplier 33 
outputs q.sub.2 (n) and K(n) to the operation apparatus 34 and multiplier 
35 respectively. 
From the equation (29), q.sub.2 (n) is obtained by: 
##EQU14## 
Since 
EQU -1.ltoreq.log.sub.2 P.sub.i2 (n)-[log.sub.2 P.sub.i2 (n)]-1&lt;0 (30-1) 
the normalized power signal q.sub.2 (n) satisfies the following: 
EQU 2.sup.-1 .ltoreq.q.sub.2 (n)&lt;1 (30-2) 
In the operation apparatus 34, the gain correction signal (1/2)q.sub.2 
(n).sup.-1/2 is calculated. In the multiplier 35, the input signal 
r.sub.2 (n) is amplified based on K(n) which is inputted from the 
multiplier 33, and the amplification signal s.sub.2 (n) is obtained by: 
EQU S.sub.2 (n)=r.sub.2 (n).times.2.sup.(k(n)-5)/2 (31) 
The amplification signal S.sub.2 (n) is multiplied by the gain correction 
signal (1/2)q.sub.2 (n).sup.-1/2 in the multiplier 36, and the value 
t.sub.2 is obtained. By using the equations (30) and (31), the value 
t.sub.2 (n) can be obtained by: 
##EQU15## 
Furthermore, t.sub.2 (n) is multiplied by the predetermined effective value 
V.sub.0 and 8 by the constant multipliers 37 and 38. The output signal 
r.sub.2 '(n) is obtained by: 
##EQU16## 
Therefore, the gain is: 
##EQU17## 
By the way, in the case where the mean power signal P.sub.i2 (n) is 
constant, the effective value of the output signal r.sub.2 '(n) is is 
given from the equations (28) and (33): 
##EQU18## 
Thus, the effective value of the output signal r.sub.2 '(n) is equal to 
the predetermined effective value V.sub.0. 
Then, the internal processing in the multiplier 33 is described along with 
the flowchart in FIG. 7. In step S21, the mean power signal P.sub.i2 (n) 
which is an input signal to the multiplier 33 is inputted into the 
register d of the DSP. Then, in step S22, the integer 1 is inputted to the 
register l. 
In step S23, the process is branched off based on the value of the register 
d. In the case where 1/2.ltoreq.d&lt;1, the process proceeds to step S27. In 
other cases, the process proceeds to step S24 where the process is 
branched off based on the value in the register 1. The value in the 
register l is regarded as an integer, and if it is larger than 2M-2, the 
process proceeds to step S26. If not, the process proceeds to step S25. 
In step S25, the value in the register d is doubled and the value of the 
register l is increased by 1 when the value of the register l is regarded 
as an integer. That is, the steps S23, S24, and S25 are repeated until 
1/2.ltoreq.d&lt;1 or 1 .gtoreq.2M-2 is formed. 
If the values of the register d and l in the processing at the j-th time to 
the processing in step S23 are determined as d.sub.j and l.sub.j 
respectively, it is apparent from the flowchart shown in FIG. 7 that 
d.sub.j is a geometrical progression in which the first term is P.sub.i2 
(n) and common ratio is 2. That is: 
EQU d.sub.j =P.sub.i2 (n) 2.sup.j-1 (j.gtoreq.1) (36) 
Furthermore, l.sub.j is an arithmetical progression in which the first term 
is 1 and common difference is 1. That is: 
EQU l.sub.j =1+(j-1).times.1=j (j.gtoreq.1) (37) 
From the above equations (36) and (37), the following equation is formed: 
EQU d.sub.j =P.sub.i2 (n) 2.sup.lj-1 (38) 
That is, if the values d and l for the processing to step S23 are 
respectively determined as d.sub.A and d.sub.B, the following relation is 
formed: 
EQU d.sub.A =P.sub.i2 (n) 2.sup.l.sbsp.A.sup.-1 
=2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+l.sbsp.A.sup.-1} (39) 
When the processing gets out of the loop of steps S23-S25, there are two 
ways. One is that the processing passes through step S26 (passing through 
D in the flowchart) and the other is the process does not pass through 
step S26 (passing through B). If the values d and l when the processing is 
passing through A and B are determined as d.sub.B and l.sub.B 
respectively, since there is no difference between the value d passing A 
and the value l passing B, the following equation is formed as the 
equation (39): 
EQU d.sub.B =P.sub.i2 (n) 2.sup.l.sbsp.B.sup.-1 
=2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+l.sbsp.B.sup.-1} (40) 
Furthermore, it is apparent from the flowchart that the following relation 
is formed: 
EQU 1/2.ltoreq.d.sub.B &lt;1 (41) 
Therefore, from the equation (40), the following relation is further 
formed: 
##EQU19## 
That is: 
EQU -1.ltoreq.log.sub.2 P.sub.i2 (n)+l.sub.B -1&lt;0 (42-1) 
EQU .thrfore.-l.sub.B .ltoreq.log.sub.2 P.sub.i2 (n)&lt;-(l.sub.B -1) (42-2) 
Since -l.sub.B is a maximum integer which is less than log.sub.2 P.sub.i2 
(n), it is expressed as the following: 
EQU -l.sub.B =[log.sub.2 P.sub.i2 (n)] (43) 
Therefore, from the equations (29) and (43), l.sub.B is obtained by: 
EQU l.sub.B =-[log.sub.2 P.sub.i2 (n)]=K(n) (44) 
Furthermore, if the equation (44) is substituted in the equation (40), the 
following equation can be obtained from the equation (30): 
EQU d.sub.B =P.sub.i2 (n).sup.K(n)-1 =q.sub.2 (n) (45) 
Therefore, the values d and l in the output B can be outputted as q.sub.2 
(n) and K(n). 
On the other hand, from the equation (42-2), the following relation is 
formed: 
EQU 2.sup.-lB .ltoreq.P.sub.i2 (n) (46) 
At the same time, from the flowchart, the following relation is formed: 
EQU l.sub.B .ltoreq.2M-2 (47-1) 
EQU .thrfore.2.sup.-lB .gtoreq.2.sup.-2(M-1) (47-2) 
Therefore, from the equations (46) and (47-2), in the case where the 
processing passes through B, the following relation is formed: 
EQU P.sub.i2 (n).gtoreq.2.sup.-2(M-1) (48-1) 
That is: 
EQU Passing through B.fwdarw.P.sub.i2 (n).gtoreq.2.sup.-2(M-1) (48-2) 
The pair of this condition is: 
EQU P.sub.i2 (n)&lt;2.sup.-2(M-1) .fwdarw.Not passing through B (48-3) 
Furthermore, since it is obvious that the loop of steps S23-S25 is not an 
infinite loop, the processing always passes either the process B or D. 
Therefore, the following conditions (49) and (50) are formed: 
EQU Not passing through B.revreaction.Passing through D (49) 
EQU Not passing through D.revreaction.Passing through B (50) 
Therefore, the following relation is formed: 
EQU P.sub.i2 (n)&lt;2.sup.-2(M-1) .fwdarw.Passing through D (51) 
By the way, in the case where 1&gt;2M-2 is formed when 1/2.ltoreq.d&lt;1 has not 
formed yet in the loop, the process branches into D and gets out of this 
loop. If the values d and l at this time are respectively determined as 
d.sub.D and l.sub.D, since d.sub.A =d.sub.D, l.sub.A =l.sub.D according to 
the flowchart, the following relation is formed such as the equation (39): 
EQU d.sub.D =P.sub.i2 (n) 2.sup.l.sbsp.D.sup.-1 
=2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+1.sbsp.D.sup.-1} (52) 
Furthermore, from that in the case where the determination in step S23 is 
NO and the determination in step S24 is YES, the process branches into 
step S26, and that d&lt;1 from the fixed point format, the following 
relations are formed: 
EQU d.sub.D &lt;1/2 (53) 
EQU l.sub.D =2M-2 (54) 
Therefore, from the equations (52), (53), and (54), in the case where the 
processing passes through D, the following relations are formed: 
EQU 2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+2M-3} &lt;1/2 (55) 
EQU P.sub.i2 (n).times.2.sup.2M-3 &lt;2.sup.-1 (55-1) 
EQU .thrfore.P.sub.i2 (n)&lt;2.sup.-2(M-1) (55-2) 
That is: 
EQU Passing through D.fwdarw.P.sub.i2 (n)&lt;2.sup.-2(M-1) (56) 
If the pair of this condition is obtained and the equation (50) is used, 
the following relation is formed: 
EQU P.sub.i2 (n).gtoreq.2.sup.-2(M-1) .revreaction.Passing through B (57) 
At last, from the equations (48-2) and (57), the following condition is 
obtained: 
EQU P.sub.i2 (n).gtoreq.2.sup.-2(M-1) .revreaction.Passing through B (58) 
Furthermore, from the equations (51) and (56), the following condition is 
obtained: 
EQU P.sub.i2 (n)&lt;2.sup.-2(M-1) .revreaction.Passing through D (59) 
According to the equation (59), in the case where the processing passes D, 
the effective value of the input signal r.sub.2 (n) satisfies the 
following: 
##EQU20## 
Since the input signal r.sub.2 (n) is a decimal in M bit including a sign, 
in the case where the equation (60) is satisfied, the input signal is 
regarded as 0. At this time, if the definitions of the equations (29) and 
(30) are directed, K(n) becomes indefinite and q.sub.2 (n) is not 
determined. 
However, since the actual apparatus can express the only definite and 
determined values, in the case where the processing passes D, the 
following values are outputted: 
EQU q.sub.2 (n)=1/2 (61) 
EQU K(n)=2M-2 (62) 
In the case where the processing passes D, since 1=2M-2, 1/2 is inputted 
into the register d in step S26 and the process branches into step S27, 
the values q.sub.2 (n) and K(n) which satisfy the equations (61) and (62) 
are outputted. 
By the way, outputting the values q.sub.2 (n) and K(n) corresponds to that 
the mean power P.sub.i2 (n) of the input signal is regarded as the 
following from the equation (30): 
EQU P.sub.i2 (n)=q.sub.2 (n).times.2.sup.-K(n)+1 =1/2.times.2.sup.-(2M-2)+1 
=2.sup.-2(M-1) (63) 
As apparent from the equations (58) and (59), the value P.sub.i2 
(n)=2.sup.-2(M-1) is a border value between the case passing through B and 
the case passing through D. 
That is, in the case where the processing passes D, the mean power P.sub.i2 
(n) of the input signal should be regarded as 0. However, in the actual 
apparatus, it is regarded that the minimum P.sub.i2 (n) which can pass 
through B is inputted, and the values q.sub.2 (n) and K(n) are outputted. 
In this way, the definite and determined q.sub.2 (n), K(n) can be outputted 
with respect to an arbitrary P.sub.i2 (n). 
Then, the detailed structure of the multiplier 35 is described. 
FIG. 8 is a block diagram illustrating the structure of the multiplier 35. 
As shown in the diagram, the multiplier 35 is comprised of the constant 
multiplier 50, multiplier 51 multiplying by 2.sup.n, multiplier 52 
multiplying by a number in which the absolute value is less than 1, adder 
53, operation apparatus 54 calculating the fixed point value 
2.sup.(L/2-[L/2]) -1 for the inputted integer L, and constant subtracter 
55. Furthermore, r.sub.2 (n), x(n), s.sub.2 (n), K(n), L(n), u(n), v(n), 
and a(n) are signal values at each portion of the multiplier at the 
sampling time n. Among those, the values except K(n) and L(n) are decimals 
in which the absolute values are less than 1. The present controller is 
also comprised of the fixed point DSP. 
In FIG. 8, the input signal r.sub.2 (n) is multiplied by 1/2 by the 
constant multiplier 50 and x(n)=(1/2)r.sub.2 (n) is obtained. In the 
constant subtracter 55, L(n)=K(n)-3 is calculated based on the value K(n) 
which is inputted from the multiplier 33 shown in FIG. 5. Furthermore, 
x(n) is multiplied by 2.sup.[L(n)/2] in the multiplier 51 by using L(n), 
and u(n) is obtained as the following: 
EQU u(n)=x(n).times.2.sup.[L(n)/2] =(1/2)r.sub.2 (n).times.2.sup.[(K(n)-3)/2]( 
64) 
Furthermore, in the operation apparatus 54, the fixed point value v(n) is 
calculated from the integer L(n)=K(n)-3, and the value v(n) is: 
EQU v(n)=2.sup.((K(n)-3)/2-[(K(n)-3)/2]) -1 (65) 
Furthermore, in the multiplier 52, u(n) is multiplied by v(n), and the 
value a (n) is obtained. Then, a (n) and u(n) are added, and the value 
s.sub.2 (n) is obtained. That is, from the equations (64) and (65), the 
following equations are obtained: 
##EQU21## 
Therefore, the multiplier 35 in FIG. 5 which has shown in FIG. 8 calculates 
s.sub.2 (n) of the equation (31) from the values r.sub.2 (n) and K(n). 
Then, the internal processing in the operation apparatus 34 is described. 
FIG. 9 is a flowchart illustrating a detailed processing in the operation 
apparatus 34. In step S31, the input signal q.sub.2 (n) to the operation 
apparatus 34 is inputted into the register d of the DSP. If the value in 
the register d at this time is determined as d.sub.1, d.sub.1 =q.sub.2 
(n), and from the equation (30-2), the following relation is formed: 
EQU 1/2.ltoreq.d.sub.1 &lt;1 (68) 
In order to obtain (1/2)d.sub.1.sup.-1/2 for d.sub.1 in this range, an 
approximate value of (1/2)d.sub.1.sup.-1/2 is calculated by the 
approximate polynomial. The obtained value is set to as an initial value 
and converged to a true value by the iterative method. 
In step S32, d=d.sub.1 is saved in the register a for the later 
processings. Then, in step S33, the approximate value f(d.sub.1) of 
(1/2)d.sub.1.sup.-1/2 is calculated by using the following polynomial: 
EQU f(x).apprxeq.(1/2) x.sup.-1/2 (1/2.ltoreq.x.ltoreq.1) (69) 
The calculated value is inputted into the register d and the value in the 
register a needs to be kept. 
If the value d at the completion of the processing in step S33 is 
determined as d.sub.3, the value d.sub.3 is: 
EQU d.sub.3 =f(d.sub.1).apprxeq.(1/2) d.sub.1.sup.-1/2 (70) 
From the view of the amount of operation, a desirable approximate 
polynomial used here is one in which the order is as low as possible 
having an efficient approximate precision. For this reason, a coefficient 
of the polynomial f(x) is determined so that f(x) becomes a Chebyshev 
approximation of (1/2)x.sup.-1/2. As more particularly describing, a 
coefficient of the polynomial f(x) of p-th order is determined so as the 
following to be minimum: 
EQU max.vertline.f(x)-(1/2)x.sup.-1/2 .vertline. 1/2.ltoreq.x.ltoreq.2 (71) 
In steps S34-S37, d.sub.3 .apprxeq.(1/2)d.sub.1.sup.-1/2 is determined as 
an initial value and a true value of (1/2)d.sub.2.sup.-1/2 is calculated 
by the iterative method. That is, in step S34, a number of occurrence R is 
inputted into the repeat counter C, and in step S35, the value d is 
renewed by the two-variable function g(x, y). Again, the value a needs to 
be kept here. 
Furthermore, the function g(x, y) is determined so that the series {X.sub.n 
} which is defined by the following recursion formula (72) is to be as the 
following equation (73): 
##EQU22## 
In steps S36 and S37, the processing is branched off based on the value of 
the repeat counter C. That is, the value of the register c is regarded as 
an integer. Then, if the value is not 1, the value of the repeat counter C 
is decreased by 1 and the process returns to step S35. Since when the 
processing enters to the loop, a=d.sub.1, d=d.sub.3 
.apprxeq.(1/2)d.sub.1.sup.-1/2, if the value d is repeatedly renewed in 
step S35 (that is, g(d, a).fwdarw.d), the value d approaches to 
(1/2)a.sup.-1/2 =(1/2)d.sub.2.sup.-1/2. 
Since when the processing in step S35 is iterated for R times, C=1, the 
processing gets out of the aforementioned loop. The value d at this time 
is determined as d.sub.6. 
If the number of occurrence R is selected so that an error 
.vertline.d.sub.6 -(1/2)d.sub.1.sup.1/2 .vertline. at the completion of 
iteration is less than the numeric precision of the DSP, the value d.sub.6 
can be regarded as a true value of (1/2)d.sub.1.sup.-1/2. Therefore, the 
value d.sub.6 of the register d at the completion of the processing in 
FIG. 9 is as the following: 
EQU d.sub.6 =(1/2)d.sub.1.sup.-1/2 =(1/2) q.sub.2 (n).sup.-1/2 (74) 
Therefore, it is understood that the processing in the operation apparatus 
34 in FIG. 5 is realized by the processing shown in the flowchart in FIG. 
9. 
Third Embodiment 
The third embodiment according to the present invention is described. 
FIG. 10 is a block diagram illustrating the structure of a digital 
automatic gain controller (which is referred to as a "controller") 
according to the third embodiment of the present invention. The controller 
is comprised of the full-wave rectifier 311 which obtains an absolute 
value of a signal, low pass filters (LPFs) 312 and 110 which average a 
signal, operation apparatuses 112 and 314 which calculate (1/2)x.sup.-1/2 
for 1/2.ltoreq.x.ltoreq.1, multipliers 315 and 319, multipliers 114 and 
317, and constant multipliers 318, 111, 113, 115, and 116. V.sub.0 is a 
predetermined effective value. 
Furthermore, r.sub.3 (n), r.sub.31 (n), r.sub.32 (n), r.sub.33 (n), r.sub.3 
'(n), v.sub.3 (n), u.sub.3 (n), t.sub.3 (n), g.sub.1 (n), K'(n), P.sub.i3 
(n), q.sub.3 (n), and g.sub.2 (n) are signal values at each portion of the 
controller at the sampling time n. Among those, K'(n) is an integer and 
the other values are decimals in which absolute values are less than 1. 
The processing in the present controller is comprised of the software of 
the fixed point DSP. FIG. 11 illustrates a fixed point format of the DSP. 
The "S", black dot, "N" respectively represent a sign bit, a decimal, and 
the total bit. 
As shown in FIG. 10, the structure of the AGC in the present controller is 
that the two-stage feed forward type AGC is successively connected The 
first stage is a part to obtain the amplification signal r.sub.32 (n) from 
the input signal r.sub.3 (n). The second step is a part to obtain the 
amplification output signal r.sub.3 '(n) from the amplification signal 
r.sub.32 (n). 
In the first stage AGC, the signal is roughly amplified, and in the second 
stage AGC, the signal is corrected so that the effective value of the 
output signal r.sub.3 '(n) is to be the predetermined value v.sub.0. 
First of all, the absolute value of the input signal r.sub.3 (n) is 
obtained by the full-wave rectifier 311 and averaged by the LPF 312. The 
mean amplification v.sub.3 (n) of the input signal r.sub.3 (n) is obtained 
as the following: 
EQU v.sub.3 (n)=E.vertline.r.sub.3 (n).vertline. (75) 
Then, in the multiplier 313, the following equation is calculated: 
EQU K'(n)=-[log.sub.2 v.sub.3 (n)] (76) 
At the same time, the mean amplitude v.sub.3 (n) is multiplied by 
2.sup.K'(n)-1, and the normalized amplitude u.sub.3 (n) is obtained. 
However, [x] represents a maximum integer which is less than x. The 
multiplier 313 outputs u.sub.3 (n) and K'(n) to the operation apparatus 
314 and multiplier 16 respectively. 
From the above equation (76), u.sub.3 (n) is obtained as the following: 
##EQU23## 
Then, the following relation is formed: 
EQU -1.ltoreq.log.sub.2 v.sub.3 (n)-[log.sub.2 v.sub.3 (n)]-1&lt;0 (78) 
Therefore, the normalized amplitude u.sub.3 (n) satisfies the following 
condition: 
EQU 2.sup.-1 .ltoreq.u.sub.3 (n)&lt;1 (79) 
In the operation apparatus 314, the following equation is calculated: 
EQU t.sub.3 (n)=(1/2)u.sub.3 (n).sup.-1/2 (80) 
Furthermore, t.sub.3 (n) is squared by the multiplier 315 and the 
amplification gain g.sub.1 (n) is obtained by: 
##EQU24## 
Furthermore, the value r.sub.31 (n) is obtained in a manner such that the 
input signal r.sub.3 is multiplied by 2.sup.n in the multiplier 16 based 
on K'(n) which is inputted from the multiplier 313. That is: 
EQU r.sub.31 (n)=r.sub.3 (n).times.2.sup.k'(n)-3 (82) 
If r.sub.31 (n) is multiplied by the amplification gain g.sub.1 (n) by the 
multiplier 317, and the product is then multiplied by 4, an amplification 
signal r.sub.32 (n) can be obtained by using the equation (81) by: 
##EQU25## 
That is, the equivalent divider is comprised of the combination of the 
operation apparatus 314, multiplier 315, multiplier 317, and constant 
multiplier 318. 
If the equations (77) and (82) are substituted in the above equation (83), 
the following equation is obtained: 
##EQU26## 
If the mean amplitude v.sub.3 (n) is a certain value, the effective value 
of the amplification signal r.sub.32 (n) which is an output of the first 
stage AGC can be obtained from the equation (84): 
##EQU27## 
Suppose that the proportion of the effective value of the input signal 
r.sub.3 (n) (a square-root of Er.sub.3 (n).sup.2) to the mean amplitude 
v.sub.3 (n)=E.vertline.r.sub.3 (n).vertline. of the value r.sub.3 is as 
the following: 
##EQU28## 
Then, the equation (85) becomes as the following: 
##EQU29## 
However, the range of .alpha. is the empirical value. That is, the first 
stage AGC is operated so that the effective value of the amplification 
signal r.sub.32 (n) is one-fourth of the proportion of the effective value 
of the input signal r.sub.3 (n) to the mean amplitude. Furthermore, from 
the equations (86) and (87), the following relation is formed: 
##EQU30## 
Since the peak values of r.sub.3 (n), r.sub.31 (n), r.sub.32 (n), r.sub.33 
(n), and r.sub.3 '(n) are empirically known that they are smaller than the 
tripled effective values of r.sub.3 (n), r.sub.31 (n), r.sub.32 (n), 
r.sub.33 (n), and r.sub.3 '(n), it is apparent that the following relation 
is formed: 
##EQU31## 
That is, the amplification signal r.sub.32 (n) is amplified so as not to 
overflow in the fixed point format shown in FIG. 11. 
The effective value of the output signal r.sub.32 (n) of the first stage 
AGC is .alpha./4 as indicated in the equation (87). In the second stage 
AGC, the effective value of the output signal r.sub.3 '(n) is corrected to 
be the predetermined value V.sub.0. 
First, the amplification signal r.sub.32 (n) is squared by the multiplier 
319 and averaged by the LPF 110. The mean power P.sub.i3 (n) of the 
amplification signal r.sub.32 (n) can be obtained by: 
EQU i P.sub.i3 (n)=Er.sub.32 (n).sup.2 (90) 
Then, the mean power P.sub.i3 (n) is multiplied by 8 by the constant 
multiplier 111 and the normalized power q.sub.3 is obtained. When the 
equations (87) and (90) are used, the the normalized power q.sub.3 is 
obtained by: 
##EQU32## 
From the equation (86), the normalized power q.sub.3 satisfies the 
following relation: 
EQU 2.sup.-1 .ltoreq.q.sub.3 (n)&lt;1/2.multidot.(4/3).sup.2 =8/9&lt;1 (92) 
Then, the correction gain g.sub.2 (n) is calculated by the operation 
apparatus 112 from the normalized power q.sub.3 (n) as the following: 
EQU g.sub.2 (n)=(1/2) q.sub.3 (n).sup.-1/2 (93) 
On the other hand, the amplification signal r.sub.32 (n) is multiplied by 
1/.sqroot.2 by the constant multiplier 113, and the value r.sub.33 (n) is 
obtained. Furthermore, the value r.sub.33 (n) is multiplied by the 
correction gain g.sub.2 (n) by the multiplier 114, and further multiplied 
by the predetermined effective value v.sub.0 and 8 by the constant 
multipliers 115 and 116 respectively. Then, the output signal r.sub.3 '(n) 
is obtained by: 
##EQU33## 
When the equations (90), (91), (93), and (94) are used, r.sub.3 '(n) is 
obtained by: 
##EQU34## 
That is, the second stage AGC has the function that the amplification 
signal r.sub.32 (n) is divided by the effective value (the square root of 
the mean power) and multiplied by the predetermined effective value. 
If the effective value of the output signal r.sub.3 '(n) of the second 
stage AGC is obtained, from the equation (96), the following is obtained: 
##EQU35## 
It is obvious that the output signal r.sub.3 '(n) is equal to the 
predetermined effective value v.sub.0 from the above equation. 
The internal signal processing in the multiplier 313 is described below 
along with FIG. 12. As shown in the diagram, the multiplier 313 is 
comprised of the constant subtracters 411, 421, 431, 441, the operation 
apparatuses 412, 413, 422, 423, 432, 433, 442, 443 which select an output 
value according to the sign of an inputted signal, the multipliers 414, 
424, 434, 444, and the adder 425, 435, 445. Furthermore, V.sub.k (n) and 
I.sub.k (n) (k=1, 2, 3, 4) are signal values at each portion of the 
multiplier at the sampling time n. The value V.sub.k (n) is a decimal in 
which the absolute value is less than 1, and I.sub.k (n) is an integer. 
The case where the mean amplitude v.sub.3 (n) which was inputted into the 
multiplier 13 satisfies the following condition is now to be described: 
EQU 2.sup.-15 .ltoreq.v.sub.3 (n)&lt;1 (98) 
First, 2.sup.-8 is subtracted from the inputted mean amplitude v.sub.3 (n) 
by the constant subtracter 411. The result of v.sub.3 (n)-2.sup.-8 is 
outputted to the operation apparatuses 412 and 413. Then, in the operation 
apparatuses 412 and 413, the following equations are calculated based on 
the sign of the result of v.sub.3 (n)-2.sup.-8 : 
EQU I.sub.1 (n)=8.multidot.max(0, -sgn(v.sub.3 (n)-2.sup.-8)) (99) 
EQU v.sub.31 (n)/v.sub.3 (n)=max(1, -2.sup.-8 .multidot.sgn(v.sub.3 (n) 
-2.sup.-8)) (100) 
The results are outputted to the multiplier 414 and adder 425. However, to 
an arbitrary real number, the following condition is satisfied: 
##EQU36## 
It should be noted that max(x, y) represents the value x or y which is 
greater than the other. From the equation (100), the following is 
obtained: 
##EQU37## 
The output v.sub.31 (n)/v.sub.3 (n) of the operation apparatus 413 is 
multiplied by v.sub.3 (n) by the multiplier 414, and the following is 
obtained: 
##EQU38## 
It is obvious that v.sub.31 (n) satisfies the following condition: 
EQU 2.sup.-8 .ltoreq.v.sub.31 (n)&lt;1 (104) 
Furthermore, a logarithm of the both sides of the equation (102) is as the 
following: 
##EQU39## 
In the summary: 
EQU 2.sup.-8 .ltoreq.v.sub.31 (n)&lt;1 (106) 
EQU log.sub.2 v.sub.31 (n)-log.sub.2 v.sub.3 (n)=I.sub.1 (n) (107) 
Similarly, from FIG. 12, the following relations are formed: 
EQU 2.sup.-4 .ltoreq.v.sub.32 (n)&lt;1 (108) 
EQU log.sub.2 v.sub.32 (n)-log.sub.2 v.sub.31 (n)=I.sub.2 (n)-I.sub.1 (n) (109) 
EQU 2.sup.-2 .ltoreq.v.sub.33 (n)&lt;1 (110) 
EQU log.sub.2 v.sub.33 (n)-log.sub.2 v.sub.32 (n)=I.sub.3 (n)-I.sub.2 (n) (111) 
EQU 2.sup.-1 .ltoreq.u.sub.3 (n)&lt;1 (112) 
and 
EQU log.sub.2 u.sub.3 (n)-log.sub.2 v.sub.33 (n)=I.sub.4 (n)-I.sub.3 (n) (113) 
If the terms of the equations (105), (109), (111), and (113) are 
respectively added in each side, the following is obtained: 
EQU log.sub.2 u.sub.3 (n)-log.sub.2 v.sub.33 (n)=I.sub.4 (n) (114) 
Finally, 1 is added to I.sub.4 (n) by the adder 445 and K'(n) is obtained. 
If the equation (114) is used: 
EQU K'(n)=I.sub.4 (n)+1=log.sub.2 u.sub.3 (n)-log.sub.2 v.sub.33 (n)+1 
.thrfore. log.sub.2 v.sub.33 (n)=log.sub.2 u.sub.3 (n)-K'(n)+1 (115) 
From the equation (112), the following relation is formed: 
EQU -1.ltoreq.log.sub.2 u.sub.3 (n)&lt;0 (116) 
Therefore, the following relations are obtained: 
EQU -1+(-K'(n)+1).ltoreq.log.sub.2 u.sub.3 (n)+(-K'(n)+1)&lt;-K'(n)+1 
.thrfore.-K'(n).ltoreq.log.sub.2 u.sub.3 (n)-K'(n)+1&lt;-K'(n)+1 (117) 
If the equation (115) is substituted, the following is obtained: 
EQU -K'(n).ltoreq.log.sub.2 v.sub.3 (n)&lt;-K'(n)+1 (118) 
That is, since -K'(n) is a maximum integer which is not larger than 
log.sub.2 v.sub.3 (n), it can be expressed as the following: 
EQU -K'(n)=[log.sub.2 v.sub.3 (n)] (119) 
Therefore, K'(n) and v.sub.3 (n) in FIG. 12 satisfy the equation (76) which 
defines K'(n) and v.sub.3 (n). 
Furthermore, from the equation (115) the following relation is formed: 
##EQU40## 
Therefore, it is indicated that u.sub.3 (n) in FIG. 12 satisfies the 
equation (77). 
As described above, u.sub.3 (n) and K'(n) which are obtained in the signal 
processing apparatus shown in FIG. 12 satisfy the definition equations for 
u.sub.3 (n) and K'(n) which are the outputs of the multiplier 13 in FIG. 
10. 
Furthermore, since the internal processing in the operation apparatuses 314 
and 112 in the controller shown in FIG. 10 is the same as that in the 
operation apparatus 34 in the second embodiment shown in FIG. 5, the 
description is omitted here. 
As described above, according to the third embodiment, in the digital 
automatic gain controller having the two-stage feed forward type AGC, it 
is corrected so that the effective value of the output signal is equaled 
to the predetermined value in the second stage AGC without using a 
feedback loop in a manner such that the effective value of the first stage 
AGC is amplified to be approximately 1/4 of the original value in the 
first stage AGC when an equivalent division is performed in the both AGCs. 
In this way, the effective value of the output signal can be equaled to 
the predetermined value without using the feedback loop. Furthermore, in 
the contract to the the feedback type AGC, an optimal gain control at the 
current time can be performed in a manner such that a gain is successively 
corrected, not converged. 
Therefore, principally, the initial response becomes quick and the gain can 
be converged before the PN segment regardless of the reception signal 
level. 
Furthermore, in the third embodiment, the case where the input v.sub.3 (n) 
to the multiplier 13 is over 2.sup.-15 has been described. However, more 
subtle signal can be processed in a manner such that the controller shown 
in FIG. 12 is developed in the same structure. 
The present invention is not limited to the above described first to third 
embodiment. Various changes and modifications may be made in the invention 
without departing from the spirit and scope thereof. For example, in the 
internal processing in the operation apparatus, the order of the 
operations on the mantissa and exponent can be switched and the 
application using the register and memory can be also modified. 
Furthermore, it goes without saying that the structure of the AGC is not 
comprised of the DSP, but of a general purpose microprocessor. 
The present invention can be applied to a system constituted by a plurality 
of devices, or to an apparatus comprising a single device. Furthermore, it 
goes without saying that the invention is applicable also to a case where 
the object of the invention is attained by supplying a program to a system 
or apparatus. 
As many apparently widely different embodiments of the present invention 
can be made without departing from the spirit and scope thereof, it is to 
be understood that the invention is not limited to the specific 
embodiments thereof except as defined in the appended claims.