SRAM split write control for a delay element

A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

FIELD

The present invention relates generally to the field of integrated circuit random access memories and more particularly a radiation hardened SRAM with split write control.

BACKGROUND

When speed is an important requirement, digital processing and storage circuits often use a Static Random Access Memory (SRAM), which, in contrast to a Dynamic Random Access Memory (DRAM), does not need to be periodically refreshed.

An SRAM includes arrays of individual SRAM cells. Each cell is addressed and accessed so that it may be “read” from or “written” to. Each cell includes a pair of cross-coupled inverters that store either a “high” or “low” voltage level. The cross-coupled inverters are coupled with a pass gate, such as a transistor to bit lines, that allows the cross-coupled inverters to be read from or written to. Unfortunately, in radiation environments, such as space and aerospace, the data state held by these cross-coupled inverters and other transistors are susceptible to upset from radiation events.

Because SRAM cells are made from semiconductor materials, such as silicon, a radiation event, such as a particle strike, may induce charge. This charge, or glitch, if large enough, may cause a node within the cross-coupled inverters to change state. If the state change results in a bit-flip or a change in state of the SRAM cell, it is referred to as a Single Event Upset (SEU) or a soft error.

One method that circuit and system designers use to prevent radiation events from causing an SEU in an SRAM is to introduce a resistive hardening element in the feedback loop between the two cross coupled inverters of the SRAM cell. The resistive hardening element is generally referred to as a delay element or a delay. Typically, except for during a write, the delay is enabled. When an SEU occurs, the delay increases the response time of a cell by preventing a radiation induced state change from propagating around the feedback loop until the charge deposited from the SEU is dissipated. During a write, however, the delay is disabled. Disabling the delay decreases the propagation time around the feedback loop and therefore, decreases the write time of the cell.

FIG. 1Ashows an example SRAM cell10in a radiation hardened configuration. SRAM cell10includes inverter12cross-coupled with inverter14. Inverter12includes Field Effect Transistor (FET)16coupled with FET18. Inverter14includes FET20coupled with FET22. The coupled drains of FETs16and18are coupled to a delay24. Delay24is coupled to the gates of FETs20and22and it receives delay and bypass signals at a delay input25.

In operation, data ports26and28input data signals, where the data signal on data port28is an inverse of the data signal on data port26. To write and read SRAM cell10, FETs30and32serve as pass gates that open and close a data path to inverters12and14. Enable inputs34receive an enable signal that opens and closes this data path. For instance, when SRAM cell10is being written, FETs30and32open, and write drivers (not shown) use data ports26and28to communicate a voltage to inverters12and14. On the other hand, when SRAM10cell is being read, FETs30and32also open; instead of receiving a voltage, however, inverters12and14output a voltage to data ports26and28.

To increase radiation hardness, SRAM cell10includes delay element24in a feedback loop through the gates and drains of FETS16-22. Delay24, when enabled, delays propagation through the loop between a node36and a node38. Delay24typically includes elements that can be controlled to increase or decrease the delay time of the feedback loop through delay input25.FIG. 1Bshows circuit elements that delay24may include. In this instance, delay24includes a FET46coupled with a resistance, such as a resistor48. When FET46receives a bypass signal, a signal may then propagate through FET48and bypass resistor48. On the other hand, when FET46receives a delay signal, it forces the signal to propagate through resistor48, and thus increases the delay time of the feedback loop. The delay time of the feedback loop may be tailored by adding additional elements to the delay or bypass paths of the delay24.

An example of SEU prevention is demonstrated as follows. If the voltage at node38is low, for instance, an SEU induced state change may cause the voltage at node38to go high. This high voltage will drive node36low. Delay24, however, will continue to hold the gates of FETs20and22high so that node38returns low. Delay24effectively delays the switching, or response time, of the cross-coupled inverters. If the response time is greater than the time it takes for the radiation induced charge to dissipate (i.e., the recovery time), SRAM cell10has been effectively radiation hardened.

An SRAM includes column and row arrays of SRAM memory cells. Typically, memory cells are grouped together in order to store multiple bits; such a grouping is referred to as a memory word. A memory word contains at least one memory cell, and each memory cell within a memory word share a common write line. Also, each bit within a memory word is accessed by a set of bit lines.

FIG. 2shows SRAM cell10located with a first row and a first column of an SRAM100. For simplicity, SRAM100includes memory words that consist of a single memory cell. In other instances, an SRAM will contain memory words that comprise multiple memory cells. In the example ofFIG. 2, SRAM100includes bit lines101-108, word lines111-114, and write-word lines121-124. Bit lines101-108are coupled to column MUX130, which is coupled to column lines131-132. SRAM cell10, FETs20and22are respectively coupled to bit lines101and105, enable inputs34are coupled to word line111, and delay input25is coupled to write word-line121. During a write and a read of SRAM cell10, bit lines101-105exchange data through MUX130and ultimately with column lines131-132. During a read, word line111carries an enable signal to the pass gates of SRAM cell10and to the pass gates of all of the other memory cells that share a row with SRAM cell10. Mux130then selects bit lines101and105and the data stored at SRAM cell10may be communicated to column inputs131-132. During a write, word line111also enables the pass gates of SRAM cell10and pass gates of the other memory cells in the first row. The write word-line121then carries a bypass signal to SRAM cell10(and all of the other memory cells that share a row with SRAM cell10). Next, a write driver (not shown) drives new data through MUX130to the selected bit-lines101&105and up to SRAM cell10. Thus, SRAM cell10is written.

Unfortunately, because write-word line121also communicates the bypass signal to all of the SRAM cells that share a row with SRAM cell10, all of the other SRAM cells within the row are bypassed and are therefore vulnerable to an SEU.

SUMMARY

A Static Random Access Memory (SRAM) and a method of operation are presented. The SRAM includes column and row arrays of individual memory cells. Each memory cell includes a delay coupled with a pair of cross coupled inverters. The SRAM includes a plurality of memory words that are comprised of at least one memory cell. A dedicated write-word line is coupled to each memory word within the SRAM. The write-word line carries delay and bypass signals. The delay signal indicates that an individual memory word is to be delayed. The bypass signal indicates that the individual memory word is to be bypassed. By operating the SRAM in this manner, a Soft Error Rate (SER) of the SRAM is reduced.

In another example, a reduced number of memory words within an SRAM share a dedicated write-word line. In this manner, an SRAM may increase its dynamic SER but reduce the amount of dedicated write-word lines it uses.

These as well as other aspects and advantages will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference where appropriate to the accompanying drawings. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the claims.

DETAILED DESCRIPTION

Returning toFIG. 2, when a memory word within SRAM100is written, its delay is bypassed. As described above, this creates a vulnerability for other memory cells that share a row with the memory word being written. The memory word that is being written is protected because it is being written to and it is not in a storage state). The unprotected memory cells, however are particularly vulnerable to SEUs and result in an increase in the dynamic SER of SRAM100. The dynamic SER is a function of speed and can be calculated using information about the memory architecture, the hardened mode static error rate and the un-hardened mode static error rate. The hardened mode static rate is the probability of an upset when the delay of a memory cell is not-bypassed. The unhardened mode static rate is the probability of an upset when the delay of a memory cell is bypassed. The dynamic SER of a memory may be calculated as follows:
dynamic SER=hardened SER×(# bits not accessed)+unhardened SER×(# bits accessed)×(write %)+hardened SER×(# bits accessed)×(1−write %)
Where dynamic SER is the dynamic error rate, hardened SER is the static error rate with a non-bypassed delay, unhardened SER is the static error rate of a bypassed delay, write % is the percentage of time dedicated to a write, # bits not accessed is the number of bits not accessed during a write, and # bits accessed is the number of bits accessed during a write. For example, for the SRAM100, if a single cell is being written, assuming writing 50% of a clock cycle for 30% of the clock time, the dynamic SER would be:
dynamic SER=hardened SER×(12)+unhardened SER×(4)×0.5×0.3 hardened SER×(4)×(1−0.5×0.3)

In general, if the unhardened SER is much less than the hardened SER, a small number of memory cells may become a significant contribution to the dynamic SER. Moreover, as the frequency of the clock cycles and the write times increase, the dynamic SER will likewise increase.

FIG. 3shows an SRAM200having an improved dynamic SER that uses a split write control. SRAM200includes a plurality of memory cells that are accessed by bit lines201-208, write lines211-214, and write-word lines221-224,231-234,241-244, and251-254. SRAM200, in a similar fashion to SRAM100, uses bit lines201-208to exchange data signals. MUX260channels these data signals to column lines261and262. Each cell within SRAM200may be a similar or equivalent in design to SRAM cell10. For simplicity, SRAM200is shown having memory words that comprise a single memory cell. In other instances, however, an SRAM may have memory words that include a plurality of individual memory cells.

Under normal operation, every memory word that is not being written, receives a delay signal on its dedicated write-word line. To read and write a memory word within SRAM200, column MUX260first selects the appropriate column. Then, one of the word lines211-214communicates an enable signal to each memory cell within the appropriate row. The SRAM can then be read, or, if it is to be written, one of the write-word lines communicates a bypass signal to the appropriate memory cell. For instance, to write memory cell270, write line212would communicate an enable signal, write-word line234would communicate a bypass signal, and write driver (not shown) would drive bit lines204and208(via MUX260).

SRAM cell200improves its dynamic SER by only allowing a cell to be written to when it receives both an enable signal and a bypass signal. Therefore the dynamic SER rate of SRAM cell200is as follows:
dynamic SER=hardened SER×(# bits in memory)
Where dynamic SER is the dynamic error rate, hardened SER is the static error rate with a non-bypassed delay, # bits in memory is the number of bits in a memory.

FIG. 4shows a method300of operating an SRAM having a split write control. Method300may be applied to write any memory word within an SRAM, such as SRAM250for instance. At block302, all of the memory cells within an SRAM have their delays enabled. In SRAM200, this would be carried out by communicating a delay signal to each memory cell within SRAM200. Next, at block304, when a memory word is to be written, only the delays of the memory cells within the memory word are disabled. In SRAM200, this would be carried when the appropriate write-word line communicates a bypass signal to the delay of the memory cell. At this time, a write line may also communicate an enable signal to the pass gates of the memory cell. In some instances, the enable signal may be communicated to the memory cell prior to the bypass signal.

At block306, the memory word is written. A write driver, for instance, may drive each bit line that is coupled to the memory word in order to set its voltage. Throughout the write, all the other memory cells within an SRAM that are not being written are disabled. At block308, after the memory word is written, the delays of all the memory cells within the memory word are re-enabled.

As an additional or alternative example, multiple memory words may be written to at the same time. For instance, inFIG. 3, if MUX260allowed multiple write drivers to access multiple memory cells within SRAM200, a bypass signal would be communicated to each memory cell that was being written. Again, similar to the examples described above, only the memory cells that are being written to should have disabled delays.

In another example, an SRAM may have an improved dynamic SER by having some memory words share a write-word line. For instance,FIG. 5Ashows an SRAM400that splits a write-word line between two memory cells. Instead of having a write-word dedicated to a single memory cell, a write-word is dedicated to two memory cells. As an example, memory cells402and404share a single write-word line406. When memory cell402is being written, memory cells402and404have a bypassed delay. Instead of the entire row that memory cell402shares being vulnerable to an SEU, only memory cell404is vulnerable. Consequently the dynamic SER of SRAM400is improved with respect to SRAM100. By having at least some memory cells share a write-word line, an SRAM may balance the benefits of an improved dynamic SER with an area penalty associated with an increased number of dedicated write-word lines.

SRAM200and400may include memory cells that are similar in structure to SRAM cell10. Alternative SRAMs having a split write control may include a variety of inverters, transistors, and other circuit elements. For instance, although the described examples show a pair of cross-coupled inverters as feedback elements, an SRAM may include alternative feedback elements such as current starved inverters, tri-state inverters, and NAND gates. These alternative feedback elements may be arranged in a variety of configurations, such as a multiple interleaved configuration. In addition, other types of radiation hardened memories having memory cells that include a delay element may also benefit from the described methods. It should be understood that the illustrated examples are examples only and should not be taken as limiting the scope of the present invention. For instance, the illustrated SRAMs are comprised of sixteen memory words that each comprises a single memory cell. These illustrations contain a reduced number of cells in order to generally convey the structure and method of operating an SRAM with split write control. Also, in most scenarios, SRAMs with a far greater number of memory cells may benefit from a split write control. The claims should not be read as limited to the described order or elements unless stated to that effect. Therefore, all examples that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.