Method of dicing a wafer and semiconductor chip

A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to German Patent Application Serial No. 10 2015 100 783.5, which was filed Jan. 20, 2015, and is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Various embodiments relate generally to a method of dicing a wafer and to a semiconductor chip.

BACKGROUND

Particularly wafers including small chips, for example chips formed using a 65 nm technology (or even smaller), may include layers with a small dielectric constant, so-called low-k-layers. The low-k-layers may be rather brittle, for example more brittle than silicon dioxide or other typically used dielectrics. This may cause problems when the wafer is sawed for dicing it into individual chips. The individual chips may suffer from so-called chipping (small chips of material broken off at newly formed edges of the chips). The chipping may be so severe that the chips have to be discarded.

In order to avoid a functionality of the chips to suffer from the chipping, a separation between functional areas of the chips, in which the dicing may be performed, may be enlarged. However, this may decrease a number of chips per wafer and thereby increase manufacturing costs.

Alternatively, the brittle layers may be separated using a laser, e.g. by laser ablation (also referred to as laser grooving). However, both the ablated material (which may settle on the chips) and/or heat introduced by the laser into the wafer, e.g. into active regions of the chips, may cause damage to the chips, which may have to be discarded. This means that a yield of the production process may be reduced, thereby increasing manufacturing costs.

SUMMARY

A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method further includes processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

DESCRIPTION

Various aspects of the disclosure are provided for devices, and various aspects of the disclosure are provided for methods. It will be understood that basic properties of the devices also hold for the methods and vice versa. Therefore, for sake of brevity, duplicate description of such properties may have been omitted.

In the following, an “active region” may refer to a region in a semiconductor wafer or a semiconductor chip that may include at least one electronic component, e.g. a transistor, a diode or the like. It may for example include an integrated circuit.

In the following, a “separation region” may refer to a region between two adjacent active regions in a wafer (and/or to a region between an active region and an edge of the wafer).

In various embodiments, for singulating a wafer into individual chips, also referred to as dicing, new processes may be incorporated for improving a dicing result for narrow separation regions (typically, a separating the wafer into individual chips may be carried out in the separation regions), and for lowering manufacturing costs at the same time. The narrower separation regions may allow for more chips to be arranged on a wafer.

Furthermore, the dicing may include an etching process, and a depth to which the etching may be carried out may be adjusted such that a thermal impact on the active regions of the chips, which may be sensitive to heat, may be avoided by directing a heat introduced by a laser dicing process away from the active regions, e.g. towards deeper regions of the chip.

In various embodiments, in a wafer dicing process, a plasma etching process and a second dicing process may be combined. The plasma etching may be carried out in a plurality of separation regions, which may be arranged between active regions of a plurality of chips extending from a surface of the wafer into the wafer, in such a way that a trench formed by the plasma etching process may extend further from the surface of the wafer into the wafer than the active regions. The second dicing process may be used for forming a separation in material remaining in the separation regions, thereby completing the separating the plurality of chips.

FIG. 1AtoFIG. 1Fshow various stages of a method of dicing a wafer in accordance with various embodiments.

As shown inFIG. 1A, a wafer102may, in various embodiments, have a first surface1021on a first side of the wafer and a second surface1022on a second side of the wafer opposite the first surface1021. The wafer102may be a semiconductor wafer, e.g. a silicon wafer, a germanium wafer, a silicon germanium wafer, a gallium nitride wafer or the like. In other words, the wafer may include a semiconductor material, e.g. silicon, germanium, gallium nitride, or the like. The wafer may have a thickness102T.

In various embodiments, the wafer102may include a material with a low dielectric constant, also referred to as low-k material104or low-k dielectric104. The low-k material104may be formed on the first side of the wafer102. It may, at least partially, for example, as shown inFIG. 1A, completely, form the first surface1021of the wafer102. The low-k material104may, in various embodiments, be formed as a layer or as a plurality of layers, or as a portion of a layer or as portions of the plurality of layers. The low-k material104may for example be formed as a structured layer or as a plurality of structured layers. The low-k material104may be rather brittle.

In various embodiments, the method of dicing a wafer102may include forming a plurality of active regions110in the wafer102. Each active region110of the plurality of active regions110may extend from the first surface1021of the wafer102into the wafer102by a height. The height of each active region110of the plurality of active regions110may also be referred to as its thickness110T. In various embodiments, the thickness110T may be smaller than the thickness102T of the wafer102. The thickness110T may for example be smaller than about 95% of the thickness102T of the wafer102, e.g. smaller than about 80%, e.g. smaller than about 50%, e.g. smaller than about 10%.

In various embodiments, a portion of the wafer102underneath a level of the plurality of active regions110may be referred to as the substrate portion of the wafer102. In various embodiments, the wafer102may have a thickness102TS underneath the level of the plurality of active regions110, i.e. the substrate portion of the wafer102may have the thickness102TS. In other words, the thickness102T of the wafer102may be a sum of the thickness110T of the plurality of active regions110and the thickness102TS of the substrate portion of the wafer102.

In the following, unless specified differently, “each active region110” and/or “the active region110” may refer to each/the active region110of the plurality of active regions110, and “active regions110” may refer to the plurality of active regions110.

In various embodiments, each active region110may include at least one material different from the semiconductor material of the wafer102. Each active region110may for example include a metal or a metal alloy, e.g. copper, aluminum, copper-tin, titanium, or the like, for example for providing a redistribution layer, a via and/or an electrically conductive contact. Each active region may for example include at least one metallization layer, for example a plurality of metallization layers. The metallization layer closest to the second surface1022of the wafer102may be referred to as the lowest metallization layer or as the bottom metallization layer.

In various embodiments, each active region110may for example include a dielectric, e.g. silicon dioxide, silicon nitride, a material with a small dielectric constant (relative to, e.g., pure bulk silicon dioxide), e.g. the low-k material104, e.g. fluorine-doped silicon dioxide, porous silicon dioxide, organic polymeric dielectrics, or the like, for example for electrically insulating electrically conductive structures from each other.

In various embodiments, during the forming of the active regions110, a plurality of separation regions112may be formed. The plurality of active regions110may be separated by separation regions112of the plurality of separation regions112. In other words, the active regions110may be formed in the wafer102in such a way that all active regions110of the plurality of active regions110that are adjacent to each other are separated by a separation region112of the plurality of separation regions112. Furthermore, the active regions110may be formed in the wafer102in such a way that a separation region112of the plurality of separation regions112may be arranged between an active region110that is adjacent to an edge, e.g. a circumferential edge, of the wafer102and the edge of the wafer102. In other words, the plurality of separation regions112may be arranged between and around the plurality of active regions110.

In various embodiments of the method of dicing a wafer, the active regions110may be formed in the wafer102in such a way that the plurality of separation regions112may be free from metal, e.g. free from a metal layer (or a metal alloy layer) or from a portion of a metal layer (or a portion of a metal alloy layer). In other words, the plurality of separation regions112may not contain a metal or a metal alloy. In other words, a layout of the wafer102may be made such that the plurality of separation regions112is formed metal-free. In various embodiments, none of the plurality of separation regions112may contain a metal or a metal alloy.

In various embodiments, the plurality of separation regions112may furthermore be free from the low-k-dielectric104.

In various embodiments, the plurality of separation regions112may only include the semiconductor material of the semiconductor wafer. In various embodiments, the plurality of separation regions112may include the semiconductor material of the semiconductor wafer and a regular (as opposed to low-k) dielectric material, e.g. silicon dioxide and/or silicon nitride.

In various embodiments, the method of dicing a wafer may include forming a mask106, e.g. a structured mask106, over the first surface1021of the wafer102. The mask106may be a mask as it is commonly used in plasma etching processes, e.g. a photolithographic mask. The mask may for example include or essentially consist of a photoresist. The mask106may be structured, e.g. using photolithographic processes. In various embodiments, the mask106may be a hard mask, e.g. including silicon dioxide and/or silicon nitride.

In various embodiments, the mask106may be formed, e.g. structured, in such a way that at least a portion of the plurality of separation regions112at the first surface1021of the wafer102may be free from the mask106. In other words, the mask106may include at least one opening108, e.g. a trench, wherein the at least one opening108may be arranged over the plurality of separation regions112.

As shown inFIG. 1B, in various embodiments, the method of dicing a wafer may include forming at least one trench114in the wafer102. The at least one trench114may be formed by plasma etching in at least one separation region112from the first surface1021of the wafer102. A plasma etching process, e.g. an anisotropic etching process, e.g. a deep reactive ion etching, e.g. a Bosch etching process, may be used for forming the at least one trench114in the wafer102. In various embodiments, since the at least one separation region112may be free from metal, an etching process suitable for etching metal may be omitted. In other words, a single plasma etching process suitable for etching the semiconductor material of the wafer102, e.g. an anisotropic etching process, may be used for forming the at least one trench114.

In various embodiments, the at least one trench114may have a width114W in a range from about 10 μm to about 70 μm, e.g. in a range from about 15 μm to about 30 μm.

In various embodiments, the at least one trench114may be formed fully within the at least one separation region112. In other words, side walls of the at least one trench114may not be formed at or in the plurality of active regions110. As a consequence, the side walls of the at least one trench114may be free from metal (not labelled here, but seeFIG. 3, where an upper surface230SU of a semiconductor chip230may correspond to a side wall of at least one trench114formed during a dicing process of the semiconductor chip230).

In various embodiments, the at least one trench114may extend into the wafer102farther than the plurality of active regions110. A bottom of the at least one trench114may for example be arranged at a level, in a vertical direction, between the second surface1022of the wafer102and the lowest metallization layer of the plurality of active regions110. In other words, a depth114D of the trench114may be larger than the thickness110T of the plurality of active regions110. In yet other words, the trench114may extend into the substrate portion of the wafer102. In yet other words, a difference ΔDT=114D−110T may be larger than zero.

In various embodiments, the single plasma etching process may be sufficient for forming the at least one trench114with the depth114D being larger than the thickness of the plurality of active regions110.

In various embodiments, the depth114D of the trench114may be smaller than the thickness102T of the wafer102. In other words, after the etching of the trench114, a portion of the separation region112below a level of a bottom of the trench114may remain. This is indicated by a dashed rectangle in e.g.FIG. 1B. The portion of the separation region112may be referred to as the remaining portion112R or as the bottom portion112R.

In various embodiments, the depth114D of the trench114may be substantially larger than the thickness110T of the plurality of active regions110. The depth114D of the trench114may for example be larger by more than about 1 nm, e.g. by more than about 5 nm. This may for example be the case if, during a subsequent processing of the wafer102for completing the dicing of the wafer102, heat may be introduced into the wafer102, e.g. during a laser processing of the wafer102. In various embodiments, the difference ΔDT may be adjusted according to an amount of heat introduced in to the wafer102, for example depending on a laser output power, a wavelength of the laser light, etc. The higher the amount of heat introduced into the wafer102, the larger the difference ΔDT that may be selected for the forming of the trench114. By way of example, when using an infrared laser for the further dicing process, the difference ΔDT may be larger than in a case where a blue laser is used.

In various embodiments, the depth114D of the trench114may be substantially larger than the thickness110T of the plurality of active regions110without later laser processing.

In various embodiments, the depth114D of the trench114may be only slightly larger than the thickness110T of the plurality of active regions110. The depth114D of the trench114may for example be larger by less than about 1 nm, e.g. by less than about 500 nm. This may for example be the case if, during a subsequent processing of the wafer102for completing the dicing of the wafer102, mechanical processes, e.g. sawing, may be used. However, the depth114D of the trench114may be only slightly larger than the thickness110T of the plurality of active regions110even if laser processing is carried out for dicing the wafer102.

In various embodiments, by having the at least one trench114extend into the substrate region of the wafer102, a damage to one or more of the active regions110, e.g. by overheating, may be avoided, because a portion of the plurality of separation regions112that may remain after the forming the at least one trench114and may need to be separated, e.g. by laser processing, e.g. laser ablation or laser stealth dicing, may be far enough away from the plurality of active regions110to cause a temperature increase to a damaging level at the plurality of active regions110. In other words, the at least one trench114may be formed deep enough, with a large enough difference ΔDT, to ensure that the temperature at the plurality of active regions110stays below a damaging level.

In various embodiments, by having the at least one trench114extend into the substrate region of the wafer102, a damage to one or more of the active regions110, e.g. by causing a crack to extend into one or more of the active regions110, may be avoided, because a portion of the plurality of separation regions112that may remain after the forming the at least one trench114and may need to be separated, e.g. by sawing or by cracking as part of the laser stealth dicing, may be far enough away from the plurality of active regions110and/or may be broad enough such that a crack that may for example start in the remaining portion of the plurality of separation regions112(e.g. deliberately as part of the stealth dicing and/or accidentally) may propagate towards the trench114and end there, rather than propagating into one or more of the plurality of active regions110.

In various embodiments, after the etching, the mask106may be removed, e.g. the photoresist may be stripped.

In various embodiments, as shown inFIG. 1CtoFIG. 1F, the remaining portion112R may be processed, e.g. treated, to separate the wafer102into individual chips (e.g. like a chip230shown inFIG. 3). The separating of the wafer102into individual chips may also be referred to as dicing of the wafer102.

As shown inFIG. 1C, in various embodiments, the method of dicing a wafer may further include attaching a layer116to the first surface1021of the wafer102, e.g. fixing a layer116to the first surface1021of the wafer102. The layer116may for example be a grinding tape. The wafer102may be mounted for grinding from the second surface1022of the wafer102. As the layer116, a typical grinding layer, e.g. a typical grinding tape, for example a soft, adhesive, UV- or heat releasable PET film, may be used.

In various embodiments, the method of dicing a wafer may further include grinding the wafer102. The wafer102may be ground from the second surface1022of the wafer102. After the grinding, as shown inFIG. 1D, the thickness102T of the wafer102may be reduced to a reduced thickness102TR. The reduced thickness102TR of the wafer102may be larger than the depth of the trench114D. In other words, the grinding may not completely remove the remaining portion112R.

In various embodiments, the method of dicing a wafer may further include mounting, e.g. re-mounting, the wafer102onto a dicing layer220, e.g. on a dicing tape220. The dicing layer220may be attached to the first surface1021of the wafer102. Thus, the second surface1022of the wafer102may be accessible for processing, e.g. for laser processing. Alternatively, the dicing layer220may be attached to the second surface1022of the wafer102, e.g. in a case where processing the remaining portion112R from the first side of the wafer102may be possible, e.g. if an aspect ratio of the trench114, e.g. a ratio of the depth114D of the trench114over the width114W of the trench, is small enough such that the remaining portion112R may be treated from the first side of the wafer102, or for example in a case processing the remaining portion112R from the second side of the wafer102may be possible despite a presence of the dicing layer220, e.g. if the dicing layer220is essentially transparent for light emitted by the laser.

As the dicing layer220, e.g. the dicing tape220, a typical dicing layer220, e.g. a typical dicing tape, e.g. a typical dicing tape suitable for laser (e.g. stealth) dicing may be used. The dicing layer220may for example be configured to withstand a large amount of heat that may be introduced into the dicing layer220during the dicing process by the laser, and/or the dicing layer220may be for example be porous and/or provide strong adhesion for draining/withstanding water that may be supplied for cooling purposes during the laser dicing process, and/or the dicing layer220may for example be transparent to the laser wavelength.

In various embodiments, as shown inFIG. 1E, the processing, e.g. treating, the remaining portion102B of the wafer102may include laser stealth dicing. The laser stealth dicing may include irradiating the remaining portion112R with a laser, such that a region224with a modified structure, e.g. a modified crystal structure, may form. The region224with the modified structure may form a defect region. By way of example, the irradiating with the laser may change a monocrystalline semiconductor material to a polycrystalline semiconductor material. However, the semiconductor material of the wafer102may not—or at least not significantly—be removed by the irradiating with the laser. The region224with the modified structure may be more fragile than portions of the wafer102that may not have been treated with the laser. In various embodiments, the conventional laser stealth dicing process may be carried out.

In various embodiments, the region224may have a width in a range from about 5 μm to about 30 μm, e.g. about 10 μm.

In various embodiments, the width114W of the trench114may be larger than the width of the region224. Thereby, it may be ensured that one end of a fracture228(seeFIG. 2F) to be caused in the region224as described below may be located at a bottom of the trench114.

In various embodiments, the laser used for the laser stealth dicing may be an infrared laser. A wavelength of the laser may for example be larger than about 750 nm. The laser may for example be a Nd:YAG laser, e.g. a pulsed Nd:YAG laser, with a wavelength of 1064 nm. In various embodiments, a laser with a different wavelength and/or with other differing properties may be used for the laser stealth dicing.

As a consequence, as shown inFIG. 1F, by applying an expanding lateral force on the wafer102including the region224with the modified structure, the wafer102may fracture at the region224with the modified structure. By way of example, a fracture228(also referred to as crack228or separation228) may form in the region224with the modified structure, extending from the second surface1022of the wafer102to the trench114.

For applying the expanding lateral force on the wafer102, the wafer102may be attached to, e.g. fixed on, an expanding layer226, e.g. on an expanding tape226. As the expanding layer226, a typical expanding layer226, e.g. a typical expanding tape, e.g. an expandable synthetic resin film, may be used. In various embodiments, the dicing layer220may be expandable, such that no dedicated expanding layer226may be required.

By pulling an edge or edges of the expanding layer226in opposite lateral directions, e.g. in two pairs of opposite lateral directions or in radial directions, the expanding lateral force on the wafer102may be applied. The wafer102may crack at the one or more regions224with the modified structure. The wafer102may form the separation228. Thereby, a plurality of individual semiconductor chips230may be formed.

In various embodiments, as shown inFIG. 2F, the expanding layer226may be applied to the second surface1022of the wafer102. Alternatively, the expanding layer226may be applied to the first surface1021of the wafer102.

In various embodiments, as described above, the method of dicing a wafer may include attaching the wafer102to a temporary support structure116,220,226. The temporary support structure116,220,226may, in various embodiments, include or essentially consist of a grinding layer116, a dicing layer220and/or an expanding layer226. In various embodiments, exactly one temporary support structure116,220,226may be attached to the wafer102while the wafer102is being processed. Depending on the process that may be carried out with the wafer102being attached, e.g. fixed, to the temporary support structure116,220,226, the temporary support structure116,220,226may be attached to the first surface1021or to the second surface1022of the wafer102.

FIGS. 2A to 2Fshow various stages of a method of dicing a wafer102in accordance with various embodiments.

In various embodiments, the processes shown inFIG. 2AtoFIG. 2Dmay be identical to the processes shown inFIG. 1AtoFIG. 1D, respectively.

The process shown inFIGS. 2A to 2Fmay differ from the process shown inFIGS. 1A to 1Fmainly in that, as shown inFIG. 2E, the treating the remaining portion112R of the wafer102may not include laser stealth dicing.

In various embodiments, the treating the remaining portion112R of the wafer102may include laser ablating. In other words, a laser may be used for partly removing semiconductor material from the separation region112of the wafer102.

In various embodiments, the laser used for the laser ablating may be similar or identical to the laser described above used for the laser stealth dicing. However, the laser may be configured to partially remove the semiconductor material. In various embodiments, one or more parameters of the laser and/or its operation may be modified as compared to the laser stealth dicing, such that an energy introduced into a treated portion of the separation region112of the wafer102may be sufficient for ablating the semiconductor material. By way of example, the laser energy, pulse duration, pulse frequency, and/or scanning speed, etc. may be adjusted for the ablating of the semiconductor material.

In various embodiments, using the laser ablating, a separation228may be formed in the wafer102, e.g. in the separation region112of the wafer102, e.g. in the remaining portion112R of the separation region112.

In various embodiments, the separation228formed by the laser ablating may have a width in a range from about 5 μm to about 20 μm, e.g. about 10 μm.

In various embodiments, the treating the remaining portion112R of the wafer102may include sawing. Using the sawing, the separation228may be formed in the wafer102, e.g. in the separation region112of the wafer102, e.g. in the remaining portion112R of the separation region112.

In various embodiments, the sawing may be carried out, e.g. using a thin sawing blade, e.g. a sawing blade with a thickness in a range from about 10 μm to about 50 μm. Thus, the separation228formed by the sawing may have a width in a range from about 10 μm to about 50 μm.

In various embodiments, other processes may be used for forming the separation228in the remaining portion112R of the separation region112.

In various embodiments, a width114W of the trench114may be larger than the separation228, which may correspond to a separation between individual chips230formed by the treating the remaining portion112R of the wafer102.

In various embodiments, by the laser ablating, the sawing or the like, the separation228may be formed. Thereby, the wafer102may be separated (diced) into individual chips230. As opposed to the process shown inFIG. 1AtoFIG. 1F, the separated individual chips230may already be present after the process shown inFIG. 2E, i.e. after the forming the separation228by laser ablating, sawing, or the like.

In various embodiments, as shown inFIG. 2F, an optional expanding using an expanding layer226and an expanding process as described in context withFIG. 1F, may be used for increasing the width of the separation228.

FIG. 3shows a schematic cross-sectional view of a semiconductor chip230in accordance with various embodiments.

In various embodiments, the semiconductor chip230may include a first surface1021C including at least one active region110, a second surface1022C opposite the first surface1021C, and at least one side surface230SU,230SL connecting the first surface1021C and the second surface1022C. The semiconductor chip230may for example have an approximately cuboid shape, and the at least one side surface230SU,230SL may be four side surfaces230SU,230SL connecting the first surface1021C and the second surface1022C.

In various embodiments, the first surface1021C of the semiconductor chip230may be a portion of the first surface1021of the wafer102described above, and the second surface1022C of the semiconductor chip230may be a portion of the second surface1022of the wafer102described above.

In various embodiments, a first part230SU of the at least one side surface230SU,230SL forming a common edge with the first surface1021C may be formed by plasma etching.

The first part230SU of the at least one side surface230SU,230SL, also referred to as the upper part230SU of the at least one side surface230SU,230SL, may for example be formed as a part, e.g. a side wall, of the at least one trench114described above.

In various embodiments, a shape of the first part230SU of the at least one side surface230SU,230SL may be characteristic for a formation by plasma etching. The first part230SU of the at least one side surface230SU,230SL may for example have an undulating wall shape, which may also be described as a comb-like wall shape or a wavy shape, that may originate from an alternating of etching and passivation during an execution of the plasma etching, e.g. a deep reactive-ion etching. The plasma etching may be carried out for example as described above.

The first part230SU of the at least one side surface230SU,230SL may have a height114D (which may be identical to the depth of the trench114described above) that may be larger than a thickness110T of the active region110, as described above.

In various embodiments, a second part230SL of the at least one side surface230SU,230SL forming a common edge with the second surface1022C, may be formed by laser treatment and/or mechanical dicing.

The second part230SL of the at least one side surface230SU,230SL, also referred to as the lower side surface230SL of the at least one side surface230SU,230SL, may for example be formed, as described above, by a process carried out for the further processing of the remaining portion114R of the wafer102in the separation region114to separate the wafer into individual chips230. It may for example be formed by laser stealth dicing (i.e. laser irradiation followed by mechanical separation), by laser ablation, by sawing or by other (e.g. mechanical) suitable separation methods.

In various embodiments, a shape of the second part230SL of the at least one side surface230SU,230SL may be characteristic for a formation by the process used for the further processing of the remaining portion112R of the wafer102in the separation region112to separate the wafer into individual chips230. The shape of the second part230SL of the at least one side surface230SU,230SL may for example be characteristic for a formation by laser stealth dicing, e.g. a very smooth surface, or for laser ablation, e.g. a very smooth surface that may show some indication of melting, or a moderately rough surface characteristically formed by sawing.

In various embodiments, as described above, the at least one trench114may be formed completely within the separation region112. As a consequence, the at least one side surface230SU,230SL may be free from metal.

FIG. 4shows a schematic process flow600of a method of dicing a wafer in accordance with various embodiments.

In various embodiments, the method may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal (in610).

In various embodiments, the method may further include forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer, wherein the at least one trench is extending into the wafer farther than the plurality of active regions (in620).

In various embodiments, the method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips (in630).

In various embodiments, a method of dicing a wafer is provided. The method may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions, and processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

In various embodiments, the treating the remaining portion of the wafer may include at least one of laser ablating or laser stealth dicing. A wavelength of a laser used for the laser ablating or the laser stealth dicing may be larger than about 750 nm. In various embodiments, the treating the remaining portion of the wafer may include sawing. In various embodiments, the method may further include fixing the first surface of the wafer to a temporary support structure before the treating the remaining portion of the wafer.

In various embodiments, the method may further include fixing a second surface of the wafer opposite the first surface to a temporary support structure before the treating the remaining portion of the wafer. In various embodiments, the treating the remaining portion of the wafer may be carried out from a first side of the wafer, wherein the first surface of the wafer may be located on the first side of the wafer. The treating the remaining portion of the wafer may be carried out from a second side of the wafer opposite the first side of the wafer. A width of the trench may be larger than a separation between the individual chips formed by the treating the remaining portion of the wafer.

In various embodiments, a semiconductor chip is provided. The semiconductor chip may include a first surface including at least one active region, a second surface opposite the first surface, and at least one side surface connecting the first surface and the second surface. A first part of the at least one side surface forming a common edge with the first surface may be formed by plasma etching. A second part of the at least one side surface forming a common edge with the second surface may be formed by laser treatment and/or mechanical dicing. The at least one side surface may be free from metal.