High power and high linearity cascode amplifier

An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to an intermediate signal. The first circuit may be implemented using a first transistor type. The second circuit may be configured to generate the intermediate signal in response to (i) an input signal and (ii) a feedback of the output signal. The second circuit may be implemented using a second transistor type. The output signal is an amplified version of the input signal while maintaining linearity.

FIELD OF THE INVENTION

The present invention relates to amplifiers generally and, more particularly, to a method and/or apparatus for implementing a high power and high linearity cascode amplifier.

BACKGROUND OF THE INVENTION

Conventional Gallium Nitride (GaN) amplifier solutions offer high power performance, especially by enabling performance at high voltage. GaN solutions do not offer a linear response over a wide range of frequencies. Conventional heterojunction bipolar transistor (HBT) devices provide a linear response over a wide range of frequencies, but only operate with limited supply voltages. HBT devices have limited power levels. In the conventional approaches, an all FET (field-effect transistor) common source drain with a FET common gate configuration can be used to implement an amplifier.

It would be desirable to provide a power amplifier with improved linearity implemented using GaN devices.

SUMMARY OF THE INVENTION

The present invention concerns an apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to an intermediate signal. The first circuit may be implemented using a first transistor type. The second circuit may be configured to generate the intermediate signal in response to (i) an input signal and (ii) a feedback of the output signal. The second circuit may be implemented using a second transistor type. The output signal is an amplified version of the input signal while maintaining linearity.

The objects, features and advantages of the present invention include providing an amplifier that may (i) provide high power output, (ii) provide a linear response over a target range of frequencies, (iii) be implemented using HBT and GaN transistors, (iv) implement a cascode configuration, (v) provide high power and high voltage characteristics of a GaN implementation, (vi) provide linear and/or gain characteristics of a HBT implementation, (vii) provide current amplification and/or voltage amplification on the same package, (viii) improve broadband performance of the topology by raising input impedance to allow broadband matching, (ix) provide the combination of a low voltage driver stage with a high voltage output device, and/or (x) be implemented on an integrated circuit package.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In an example embodiment, one transistor type, such as bipolar transistors (or heterojunction bipolar transistors), may be used to implement an input stage. In another example, the input stage may be implemented using a Darlington configuration. In one example, another transistor type, such as a high breakdown voltage FET, may be used to implement an output stage. In general, the high breakdown voltage FET may include pHEMT (pseudomorphic high electron mobility transistor) and/or HFET (heterostructure field-effect transistor) technology capable of providing high breakdown voltages. In one example, a GaN HEMT (high electron mobility transistor) may be used to implement the output stage. In general, HBT devices may have a maximum operating voltage of 5V allowing signal swings of approximately 10V. In general, a high breakdown voltage may be considered to be a breakdown voltage of greater than 10V. For example, GaN devices offer breakdown and operating voltages greater than 50V. Such an implementation takes advantage of each of the benefits of each transistor technology. In one example, the bipolar transistors may provide current amplification. In another example, the GaN HEMT may provide voltage amplification. In one implementation, the two processes may be fabricated on different substrates, then bonded together using bond wires to make one integrated circuit (IC) package. In general, the GaN transistors may not provide a linear response over a wide range of frequencies. Pairing the GaN transistors with one or more bipolar transistors may be used to implement a power amplifier with a linear response over a wide range of frequencies and/or bandwidth matching.

Embodiments of the invention may be implemented to pair the high voltage and/or high power characteristics of GaN devices with the linear response and/or gain characteristics of HBT devices. In one example, GaN and HBT devices may be combined in a cascode arrangement where a high output voltage is spread across the common gate GaN field-effect transistor (FET) which is driven by a common emitter HBT. In a cascode arrangement, the HBT device may experience a limited voltage swing, even with a very large voltage swing at the GaN FET output. The cascode arrangement may take advantage of each of the benefits of each type of transistor. For example, the bipolar transistors may provide current amplification. The GaN transistor may provide voltage amplification. GaN transistors may be used for the output stage. The HBT device has a linear conductance, Gm. Use of a Darlington configuration at the HBT driving stage further improves broadband performance of the topology by raising input impedance to allow broadband matching. In addition, the HET device offers low knee voltage which keeps more voltage available for the GaN device to maximize output power.

Referring toFIG. 1, a block diagram of a circuit100is shown illustrating an example embodiment of the invention. The circuit100(or device, or integrated circuit, or system)100may be implemented as an amplifier. The circuit100generally comprises a block (or circuit)102, and a block (or circuit)104. The circuit102may be an input stage (or input circuitry). The circuit104may be an output stage (or output circuitry). The circuit100may have an input110that receives a signal (e.g., IN), and an output (e.g.,120), that may present a signal (e.g., OUT). The signal OUT may be an amplified version of the signal IN. The signal OUT may maintain a linear response compared with the signal IN.

The circuit102may have an output130that may present a signal (e.g., INT). The signal INT may be transferred to an input140of the circuit104. The signal INT generally conveys an amplified version of the signal IN from the circuit102to the circuit104while maintaining a linear response. The circuit102may provide current amplification. In one example, the circuit102may be implemented as a bipolar transistor, such as an HBT. The circuit104may present the signal OUT. The signal OUT may be an amplified version of the signal INT. The circuit104may provide voltage amplification. In one example, the circuit104may be implemented as a high breakdown voltage FET, such as a GaN transistor.

A signal (e.g., FEEDBACK) is shown connected from the circuit104to the circuit102. The signal FEEDBACK may be a feedback of the signal OUT presented to the circuit102. The signal FEEDBACK may be used to set target radio frequency (RF) gain and/or impedance levels. In the example shown, 4 volts may be presented to the GaN transistor at the gate. The gate absorbs voltages of approximately 1 volt. 19 volts is left available to power the GaN transistor.

Referring toFIG. 2, a more detailed diagram of the circuit100is shown. The circuit100illustrates a single-ended implementation. The circuit102generally comprises a transistor Q1and a resistor R1. The transistor Q1may be an HBT transistor. The transistor Q1may be connected in a common emitter configuration. The resistor R1may set an RF gain and/or an impedance level.

The circuit104generally comprises a transistor Q2, a resistor R3, a resistor R4, and/or a capacitor C3. In one example, the transistor Q2may be implemented as a GaN transistor. The transistor Q2may be configured in a common gate configuration. The resistors R3and/or R4may set a desired voltage at the gate of the transistor Q2. The capacitor C3may provide RF ground for a common gate operation.

The signal IN may be presented to a base of the transistor Q1through a capacitor C1. The signal IN and the signal FEEDBACK may be presented to the transistor Q1through a capacitor C2and/or a resistor R2. The signal INT may be generated by the circuit102. The signal INT may be generated by the collector of the transistor Q1. The signal INT may be connected between the collector of the transistor Q1and the source of the transistor Q2. The drain of the transistor Q2may generate the signal OUT. The signal OUT may be presented as the output120of the circuit100. The various passive components shown may provide target DC bias conditions and/or may set gain and/or impedance levels.

The circuit100may split a high DC supply voltage VDD across the transistor Q2and/or the transistor Q1. In general, HBT transistors do not operate with high collector voltages. In order to limit the collector voltage of transistor Q1, the gate of the transistor Q2may be set to a target low voltage with the resistor R3and/or the resistor R4. The voltage drop from gate to source of the transistor Q2(Vgs) may be set by intrinsic characteristics of the GaN transistor (e.g., based on operating current, etc.). The gate to source voltage Vgs is typically in the range of −1V to −2V. By setting the voltage at the gate of the transistor Q2, an optimally large amount of supply voltage may be generated across the high voltage transistor Q2while keeping voltage on the collector of the transistor Q1low enough for reliable operation while still high enough for optimal linear performance.

In a typical target application, such as a cable television (CATV) infrastructure, the supply voltage VDD may be 24V. The collector voltage of the transistor Q1may be set to approximately 5V. The output of the transistor Q2may then have 19V available. Even under large RF signal conditions (and high RF currents) the voltage swing at the collector of the transistor Q1may be relatively small because of the high transconductance of the transistor Q2.

The current through transistor Q1and/or the transistor Q2may be set by the amount of current presented to the base of the transistor Q1. Such current may be defined by the following current gain formula:
β=Ic/Ib

The base current may be set by sizing a resistor R5. In more robust implementations, the resistor R5may be replaced with more bias networks to set a constant base current when there is potential variation in temperature, resistor values and/or β.

The resistors R1and/or R2may provide feedback to set a desired RF gain and/or impedance level. The capacitor C3may provide an RF ground for common gate operation. The capacitors C1, C2and/or C4may provide DC blocking. The inductor Ll may provide high RF impedance with low DC resistance to feed supply voltage and/or current to the amplifier.

Referring toFIG. 3, a diagram of a circuit100′ is shown. The circuit100′ is shown illustrating a cascode implementation using a Darlington pair of transistors. The circuit100′ generally comprises a circuit102′ and a circuit104′. The circuit102′ may include the transistor Q1and a transistor Q3, arranged in a Darlington configuration. The transistor Q1may be configured as a pre-driver transistor. The transistor Q3may be configured as a driver transistor. In a Darlington configuration, the transistor Q1may be a small transistor that may drive the transistor Q3. The transistor Q3may be implemented as a primary common emitter device with a shared collector terminal. The shared collector terminal may generate a signal (e.g., INT′) at the output130′ of the circuit102′.

A resistor R6may have one end connected to ground and the other end connected to the emitter of the transistor Q3. The resistor R6may allow the adjustment of DC current in the transistor Q3. The resistor R1may have one end connected to the base of the transistor Q3and the emitter of the transistor Q1, and the other end connected to ground. The resistor R1may allow an additional discharge path for the charges stored in the base of the transistor Q3. The resistor R1may allow independent adjustment of the DC current in the transistor Q1.

The Darlington configuration shown is common in bipolar transistor amplifiers. The Darlington configuration may provide benefits desired for larger devices in power amplification (e.g., higher gain, broader bandwidth, better noise figure, and higher input impedance).

The circuit104′ may have a configuration similar to the circuit104. An input140′ of the circuit104′ may receive the signal INT′. The circuit104′ may present the signal OUT. The signal OUT may be an amplified version of the signal INT′. A signal (e.g., FEEDBACK′) is shown connected from the circuit104′ to the circuit102′. The signal FEEDBACK′ may be a feedback of the signal OUT presented to the circuit102′. The signal FEEDBACK′ may be used to set target radio frequency (RF) gain and/or impedance levels.

Referring toFIG. 4, a diagram of a circuit100″ is shown. The circuit100″ illustrates a Darlington cascode amplifier with two amplifiers driven in Push-Pull configuration. A balun (e.g., B1) may be used at the input110. A balun (e.g., B2) may be used at the output120. The baluns B1and/or B2may allow for a balanced operation. A capacitor at the common gate of the GaN transistors Q2aand/or Q2bin circuits104aand104bmay not be needed because of the virtual ground created by the balanced operation. A circuit102amay include a transistor Q1aand a transistor Q3a. A circuit102bmay include a transistor Q1band a transistor Q3b. The transistors Q1a/Q3aand/or the transistors Q1b/Q3bmay be arranged in the Darlington configuration.

The balun B1may present input signals of opposite phase to the Darlington pair circuits102aand102b. Capacitors (e.g., C1aand/or C1b) may allow for fine tuning of the input impedance. The shared collector terminal of the Q1aand/or Q3atransistors of the circuit102amay generate a signal (e.g., INT_a) at an output130aof the circuit102a. The shared collector terminal of the Q1band/or Q3btransistors of the circuit102bmay generate a signal (e.g., INT_b) at an output130bof the circuit102b. Resistors (e.g., R1aand/or R1b) may allow each Darlington pair of transistors in the circuits102aand/or102bto rapidly discharge stored charges. The resistors R1aand/or Rib may allow for independent adjustments to the DC current through the transistors Q1aand/or Q1b. Resistors (e.g., R6aand/or R6b) may join the emitter of the transistors Q3aand Q3bto create an additional path for adjustment of the AC current in the transistors Q3aand/or Q3b.

The signal INT_a may be presented to an input140aof the circuit104a. The signal INT_b may be presented to an input140bof the circuit104b. The circuit104amay generate a signal (e.g., FEEDBACK_a). The signal FEEDBACK_a may be presented to the circuit102a. The signal FEEDBACK_a may be provided through an RC network (e.g., R2aand/or C2a). The circuit104bmay generate a signal (e.g., FEEDBACK_b). The signal FEEDBACK_b may be presented to the circuit102b. The signal FEEDBACK_b may be provided through an RC network (e.g., R2band/or C2b). The circuit104amay be in-phase with the circuit102a. The circuit104bmay be in-phase with the circuit102b. The circuits102aand104amay be out-of-phase with the circuits102band104b.

A DC voltage source (e.g., VDDa) may be connected to the input of the circuit102athrough a resistor network (e.g., R5a) to provide bias voltage for the transistors Q1aand/or Q3a. A DC voltage source (e.g., VDDb) may be connected to the input of the circuit102bthrough a resistor network (e.g., R5b) to provide bias voltage for the transistors Q1band/or Q3b. The DC voltage sources VDDa and/or VDDb may be connected to the balun B2. The output of the circuit104aand/or the output of the circuit104bmay be presented to the balun B2. The balun B2may generate the signal OUT.

The balun B1may present an input signal of increasing amplitude to the circuit102aand an input signal of decreasing amplitude to the circuit102b. An increasing current may be drawn from the DC voltage sources VDDa through the transistor Q2a. A decreasing current may be drawn from the DC voltage source VDDb through the transistor Q2b. The total resultant output through the balun B2may be the sum of the charge flow through the balun B2. A corresponding response occurs when the balun B1presents an input signal of decreasing amplitude to the circuit102aand an input signal of decreasing amplitude to the circuit102b.

Referring toFIGS. 5-8, simulation results are shown for the amplifier100described inFIG. 2. The simulation results indicate the benefits of the cascode topology. The benefits of the cascode topology may include enabling the combination of a low voltage driver stage with a high voltage output device. Mixing the HBT and GaN technologies may provide the benefits of each process. GaN technology may support large voltage operations. HBT technology may provide a linear response and/or lower cost.

Referring toFIG. 5, a graph illustrating the gain against output power for the amplifier100described inFIG. 2with a simulation frequency of 500 MHz is shown. The X axis of the graph may represent the output power (e.g., POUT1) of the circuit100measured in dBm. The Y axis of the graph may represent the gain (e.g., GAIN1) of the circuit100measured in dB.

A point M3may represent a point on the graph where GAIN1is 24.7 dB, and POUT1is 15.7 dBm. A point M4may represent a point on the graph where GAIN1is 24.4 dB, and POUT1is 33.9 dBm. The input power is swept until the gain begins to compress (is reduced). Gain compresses when output power is beyond the linear operating region of the amplifier, as indicated by the point M4. The points M3and M4may indicate the limits of output power where the amplifier100remains linear.

Referring toFIG. 6, a graph illustrating the current through a HBT transistor Q1against the voltage at a collector over a range of simulated input power levels for the amplifier100described inFIG. 2is shown. The X axis of the graph may represent the voltage (e.g., VC1) at the collector of the transistor Q1measured in volts. The Y axis of the graph may represent the current (e.g., IQ1) of the transistor Q1measured in amperes.

The voltage VC1at the collector of the transistor Q1is shown ranging from approximately 3.5V to 6V. Even as the full amplifier enters gain compression, the voltage swing may generally be less than +/−1.5V beyond a small signal operating point. Since HBT devices can not operate with high collector voltages, the graph indicates that an HBT device may still be able to operate with the configuration described in the circuit100.

Referring toFIG. 7, a graph illustrating the current through the GaN transistor Q2against a drain to source voltage over a range of simulated input power levels for the amplifier100described inFIG. 2is shown. The X axis may represent the drain to source voltage (e.g., VDS2) across the transistor Q2measured in volts. The Y axis may represent the current (e.g., IQ2) of the transistor Q2measured in amperes.

The drain to source voltage VDS2across the transistor Q2is shown from an initial small signal value of 19V as having a range from as low as 1V up to 41V. The large voltage swing range indicates that the transistor Q2may provide high power and high voltage amplification with the configuration described in the circuit100.

Referring toFIG. 8, a graph illustrating the current against the voltage for the transistors Q1and Q2on the same plot for the amplifier100described inFIG. 2is shown. The X axis may represent VC1for the transistor Q1and VDS2for the transistor Q2measured in volts. The Y axis may represent IQ1for the transistor Q1and IQ2for the transistor Q2measured in amperes.

The plot indicates that the voltage of the transistor Q1is relatively constant compared to the voltage swing for the output transistor Q2. With the cascode configuration described in the circuit100, a low voltage HBT driver device may safely be chosen which has high gain and a linear response in combination with a high breakdown voltage common gate device.

Referring toFIG. 9, a graph illustrating currents through a pHEMT device versus drain-to-source voltages over a range of gate bias voltages is shown. The pHEMT device may be a 1 mm pHEMT device. The X axis represents a drain-to-source voltage (e.g., VDS) measured in volts. The Y axis represents a current (e.g., IDS) measured in milliamperes. Each curve on the graph represents a DC I-V curve at a particular gate bias voltage (e.g., VGS). In one example, a point M7represents a point on a curve with a VGS of −0.4V. At the point M7the VDS value may be 5.0V, and the IDS value may be 125 mA.

Referring toFIG. 10, a graph illustrating transconductance against gate bias voltage for the pHEMT is shown. The X axis represents a gate bias voltage VGS measured in volts. The Y axis may represent a transconductance (e.g., GM1). Transconductance is a ratio change in current divided by change in gate bias voltage. The transconductance GM1is calculated at the VDS value of 5V. A point M21may represent a point where the VGS is −0.7V and the transconductance GM1is 0.136. Transconductance is directly correlated to device gain. Generally, for linear operation the transconductance may be nearly constant over a range of input signal levels.

Referring toFIG. 11, a graph illustrating currents through an HBT device against voltages of the HBT device over a range of base bias voltages. The HBT device may be a 1280 μm2HBT device. The HBT device may be sized to handle the same 5V and/or 125 mA as the pHEMT. The X axis may represent a voltage (e.g., VCC) for the HBT device measured in volts. The Y axis may represent a current (e.g., ICC) through the HBT device measured in milliamperes. Each curve on the graph may represent a DC I-V curve at a particular base bias voltage (e.g., VB). In one example, a point M3may represent a point on a curve with a VB of −2.1V. At the point M7the VCC value may be 5.0V, and the IDS value may be 118 mA.

Referring toFIG. 12, a graph illustrating transconductance against base bias voltage for the HBT device. The X axis may represent a base bias voltage VB measured in volts. The Y axis may represent a transconductance GM1. The transconductance GM1is calculated at the VAS value of 5V. A point M6may represent a point where the VB is 2.1V and the transconductance GM1is 0.145.

The HBT device (described inFIG. 10) may include emitter resistance to yield a similar peak transconductance GM1as the pHEMT device (described inFIG. 12). Comparing the graphs described inFIGS. 11 and 12with the graphs described inFIGS. 9 and 10, the HBT device has a relatively constant current and transconductance compared to the pHEMT. The relatively constant current and transconductance may yield a relatively constant and linear gain for the HBT device.

Referring toFIG. 13, a graph illustrating output third order intermodulation intercept of cascode arrangements. Output third order intermodulation intercept is a common measure of linearity. The X axis may represent an output power (e.g., POUT) measured in dBm. The Y axis may represent an output third order intermodulation intercept (e.g., OIP3) measured in dBm. The dashed line curve may represent an amplifier configured in a cascode arrangement comprising a pHEMT at the driver stage and a GaN device at the output stage. The solid line curve may represent an amplifier configured in a cascode arrangement comprising an HBT device at the driver stage and a GaN device at the output stage, similar to the circuit100. Both amplifiers may operate with a 24V supply and 200 mA. The HBT device and GaN device arranged in a cascode arrangement provides a 2.5 dB improvement in output third order intermodulation intercept over the cascode arrangement implemented with a pHEMT at the driver stage. The improvement in output third order intermodulation intercept indicates improved linear gain.