Resin sealed semiconductor device having power source by-pass connecting line

A resin sealed semiconductor device having: a semiconductor chip having an electric circuit therein and an elongated main connection line respectively formed thereon; a plurality of leads disposed near the chip; electrical connecting wires for electrically connecting together the chip and the leads; at least one by-pass connection line formed in correspondence with the main connection line; and by-pass connecting wires for electrically connecting the main connection line near at one end thereof to the by-pass connection line near at one end thereof, and electrically connecting the main connection line near at the other end thereof to the by-pass connection line near at the other end thereof.

FIELD OF THE INVENTION 
The present invention relates to a resin sealed semiconductor device which 
allows a voltage applied to one end of a narrow connection line of the 
semiconductor chip to propagate correctly to the other end of the line, 
even if the line, for example, a power supply line, is formed very finely. 
BACKGROUND OF THE INVENTION 
As a means for electrically connecting a semiconductor element (hereinafter 
called a chip) to external leads of a semiconductor device having a 
plurality of terminals or pins, such as ICs and LSIs, there are known wire 
bonding and wireless bonding methods. The wire bonding method is a method 
whereby a bonding wire made of a fine metal such as gold and aluminum and 
having a 20 to 30 .mu.m diameter, connects a bonding pad on a chip to an 
external lead. Bonding wire is bound, for example, by means of a 
thermocompression bonding method, an ultrasonic bonding method, or both 
the methods. The wireless bonding method is a method whereby a plurality 
of gold pads on a chip are connected to a plurality of external leads at a 
time using specific bumps or metal leads. This method is executed by a 
known tape carrier scheme, flip chip scheme, beam lead scheme, or the 
like. As well known, in order to protect a chip from contamination or 
defect by ambient atmosphere, the chip and its peripheral area are sealed 
with resin. 
FIG. 1 is a plan view of a chip of a resin sealed semiconductor having a 
well known zigzag in-line package (ZIP). Referring to FIG. 1, at the 
peripheral area of a chip 1, there are formed bonding pads 2, a V.sub.ss 
potential bonding pad 3, and a V.sub.cc potential bonding pad 4, at 
positions corresponding to the layout of a lead frame for ZIP. The 
V.sub.SS potential bonding pad 3 is connected to a V.sub.SS potential 
connection line 20 of a closed loop formed at the peripheral area of the 
chip 1. A V.sub.CC potential connection line (not shown) is also formed at 
the side of the V.sub.SS potential connection line, the detailed 
description of this line being omitted because it is not closely related 
to the present invention. As described above, a chip has a number of power 
supply lines and a number of electrodes (bonding pads) for supplying 
input/output signals and power sources. A connection line, particularly a 
power source line, occupies a large area of wiring space, providing one of 
obstacles against high integration of a semiconductor device. 
FIG. 2 is a plan view of a conventional lead frame on which the chip shown 
in FIG. 1 is mounted. A semiconductor mount section (hereinafter called a 
bed) 5 is formed at the central area of the frame, and leads are formed 
externally of the bed. Each lead is comprised by an inner lead 9 directly 
connected to a bonding pad, and an outer lead 8 integrally formed with the 
inner lead 9. At the tip of the inner lead 9, there is formed a metal 
plated layer 9A such as gold and silver. One of the inner leads 9 is used 
as a V.sub.SS potential lead 10, and another is used as a V.sub.CC 
potential lead 13. 
The bed 5 is suspended by a side section 7 of the lead frame via suspension 
pins 6. A metal plated layer 5A such as gold and silver is also formed on 
the surface of the bed 5. Reference numeral 7A represents a hole for 
transporting the lead frame. 
FIG. 3 is a plan view of the finished semiconductor device wherein the chip 
1 shown in FIG. 1 and mounted on the lead frame shown in FIG. 2, is sealed 
with resin and the side section 7 of the lead frame is removed. FIG. 3 is 
shown as seeing through the resin sealed portion of the semiconductor 
device. The chip 1 is attached to the bed 5 using mount paste. Next, the 
bonding pads 2, V.sub.SS potential bonding pad 3, and V.sub.CC potential 
bonding pad 4, respectively on the chip 1, are connected to leads 9 (10, 
13) using bonding wires 11. Thereafter, the chip 1 is sealed with resin 12 
such as epoxy resin, and the leads are cut from the side section and bent. 
In this manner, the resin sealed semiconductor device is formed, with the 
side section 7 of the lead frame being removed. 
FIG. 4 shows another conventional resin sealed semiconductor device of a 
thin small out-one package (TSOP) type. FIG. 4 is shown as seeing through 
resin 12. This device has leads extending from two opposite sides, and 
suspension pins 6 being formed at the other two opposite sides. These 
points differ from the device shown in FIGS. 2 and 3. 
Recently, semiconductor devices such as ICs and LSIs are becoming more and 
more integrated, so the number of pads on a chip for supplying 
input/output signals and power sources is increasing greatly. Furthermore, 
the chip size is becoming more and more reduced, so the design rule is 
becoming finer. Therefore, the resistance of a connection line becomes 
high posing a problem of signal noises. 
A connection line, particularly a power source line, occupies most of the 
chip wiring area. This power source line is therefore becoming more and 
more fine, resulting in noise generation by power source lines in many 
cases. For example, the chip 1 shown in FIG. 1 has its V.sub.SS potential 
bonding pad 3 on the A side. Assuming that the pad 3 is connected to the 
V.sub.SS potential side (ground), the V.sub.SS potential connection line 
20 takes a V.sub.SS potential. However, the potential at the B side of the 
connection line 20 is not V.sub.SS in practice. Since the V.sub.SS 
potential connection line is made fine because of high integration of the 
semiconductor device, the resistance of the V.sub.SS potential connection 
line 20 becomes high. It is a tendency therefore that the potential of the 
connection line 20 at the B side opposite to the A side becomes higher 
than V.sub.SS potential. More specifically, if the connection line width 
becomes equal to or less than about 100 .mu.m, the V.sub.SS potential 
rises about 0.1 V from 0 V. Accordingly, noises are superposed upon 
input/output signals within a chip, posing the problem that operation 
speed cannot be made high. 
The above problem can be solved if, for example, the V.sub.SS potential is 
supplied to both sides of a chip, at the areas near the A and B sides. 
However, from the viewpoint of package lead frame designs, it is 
impossible to increase the number of V.sub.SS leads. 
As described above, semiconductor devices are becoming more and more 
integrated, so the design rule is becoming finer. Therefore, the 
resistance of a connection line becomes high posing a problem of signal 
noises. 
SUMMARY OF THE INVENTION 
The present invention has been made in consideration of the above-described 
circumstances. It is an object of the present invention to provide a 
semiconductor device having a wiring structure capable of reducing a 
potential fluctuation of a connection line, e.g., a power source line, and 
hence eliminating noise generation. 
According to the present invention, a lead is provided outside of a chip, 
the lead serving to by-pass the potential of a connection line, e.g., a 
power source line. With such an arrangement, irrespective of an increased 
resistance of a fine connection line in a highly integrated chip, the 
potential can be correctly propagated within the chip. Therefore, the 
potential fluctuation within the chip can be suppressed, solving the 
problem of noise generation and ensuring the performance specific to the 
chip.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The embodiments of the present invention will be described with reference 
to the accompanying drawings. 
The first embodiment will be described. 
FIG. 5 is a partial plan view of a lead frame for a ZIP type according to 
the present invention. FIG. 6 shows a resin sealed chip mounted on the 
lead frame shown in FIG. 5. FIG. 6 is shown as seeing through the resin 
portion. FIG. 7 is a side view of FIG. 6 with resin being seen through. 
In the lead frame shown in FIG. 5, like elements to the conventional lead 
frame shown in FIG. 2 are represented by using identical reference 
numerals, and the description thereof is omitted. 
A by-pass lead 100 which is a characteristic feature of the present 
invention is formed at an upper area of a bed 5. The surface of the 
by-pass lead 100 is also coated with a metal plated layer 100A. The lead 
100 has two bonding areas 100B.sub.a and 100B.sub.b at slightly inner 
positions thereof. The bonding areas 100B.sub.a and 100B.sub.b are used 
for wire bonding, and are wider than other areas 100C of the lead 100. The 
width of the narrower area 100C of the lead 100 is about 0.2 mm. This 
width may be about 0.1 mm to 2 mm. 
A chip is mounted on the lead frame shown in FIG. 5 and sealed with resin. 
As particularly shown in FIG. 7, a chip 1 is fixedly mounted on the bed 5 
using conductive adhesive agent 150 such as epoxy resin contained with 
silver. The adhesive agent is not necessarily conductive, but may be an 
insulator, for example, using only epoxy resin. As seen from FIG. 6, the 
chip 1 mounted on the bed 5 is slightly different from a conventional 
chip. Namely, there are formed two bonding pads 90 and 91 on a V.sub.SS 
potential connection line 20, the bonding pads 90 and 91 being connected 
to the bonding areas 100B of the by-pass lead 100 by bonding wires 11. 
Bonding wires 11 for electrical connection between the leads 100 and chip 
1 are made of material such as gold and aluminum. Bonding wires 11 made of 
material such as gold and aluminum also provide connections between the 
bonding pads 2 on the chip 1 and inner leads 9, between a V.sub.SS 
potential bonding pad 3 and a V.sub.SS potential lead 10, and between a 
V.sub.CC potential bonding pad 4 and a V.sub.CC potential lead 13. As the 
bonding technique, a desired one of known methods such as ultrasonic 
bonding and thermocompression bonding may be used. Thereafter, the chip 1 
is sealed with resin 12 such as epoxy resin. Then, leads are cut and bent 
to obtain a resin sealed semiconductor device shown in FIGS. 6 and 7, with 
a side section 7 of the lead frame being removed. 
According to the first embodiment, the V.sub.SS potential supplied to one 
side of the chip 1 in the lateral direction is propagated to the other 
side via the by-pass lead 100 formed above the bed 5. More particularly, 
the V.sub.SS potential is propagated via the route of the V.sub.SS 
potential lead 10, bonding wire 11, V.sub.SS potential bonding pad 3, 
V.sub.SS potential connection line 20, bonding pad 90 on the V.sub.SS 
potential connection line 20, bonding wire 11, bonding area 100B.sub.a, 
by-pass lead 100, bonding area 100B.sub.b, bonding wire 11, and bonding 
pad 91 on the V.sub.SS potential connection wire 20. In this manner, the 
V.sub.SS potential can be propagated from the A side to B side of the 
V.sub.SS potential connection line 20, without the influence of the 
resistance of the connection line 20. Therefore, potential fluctuation 
within a chip, which has been the conventional problem, will not occur. 
Furthermore, since the by-pass lead 100 can be formed at the marginal area 
of the lead frame, the device will not be prevented from being made finer 
by the presence of the by-pass lead. 
The second embodiment will be described which uses two by-pass leads. 
FIG. 8 shows a resin sealed semiconductor device of a thin small out-line 
package (TSOP). FIG. 8 shows a plan view of the device with a chip mounted 
on a lead frame and sealed with resin, with the resin portion being seen 
through. In FIGS. 8 and 9, like elements to those shown in FIGS. 5 to 7 
are represented by using identical reference numerals. A lead frame (not 
shown) used with this semiconductor device has leads 8 and 9 formed on the 
right and left sides as shown in FIG. 8. A pair of suspension pins 6 is 
formed at the upper and lower portions. In this embodiment, two by-pass 
leads 100 are formed at the areas between the two pairs of suspension pins 
6. 
The V.sub.SS potential supplied from a V.sub.SS lead 10 is propagated in 
the similar manner to the first embodiment. Specifically, the V.sub.SS 
potential is propagated via the route of the V.sub.SS lead 10, bonding 
wire 11, pad 3, connection line 20, pad 90, wire 11, bonding area 
100B.sub.a, lead 100, bonding area 100B.sub.b, wire 11, and pad 91. 
The number of by-pass leads is not limited, but any necessary number of 
leads may be used. 
The material of a lead frame is not specifically limited. As the material, 
in addition to an Fe-42 Ni alloy (42 alloy), other metals such as copper 
may be used. 
As the semiconductor of a chip, in addition to silicon (Si), Ge and 
compound semiconductor such as GaAs and InP may be used. 
The width and length of a by-pass lead may be set as desired while 
considering the advantageous effects of the present invention. For 
example, in the first embodiment, the length of the by-pass lead is 
substantially the same as the semiconductor device (whose size is about 
5.times.15 mm). 
In the first and second embodiments, there is used a lead frame of the type 
that bonding wires are used for electrical connection between inner leads 
and bonding pads of a chip. However, the present invention is not limited 
to this type. For example, the film carrier method may be used whereby 
inner leads are directly connected to bonding pads of a chip. The scope of 
the present invention obviously contains this method. 
According to the present invention, power source lines can be made finer at 
the stage of designing a chip, which is very efficient in reducing the 
chip size. 
The package type is not limited to TSOP and ZIP, but other types such as 
DIP and SOJ may also be used.