Semiconductor circuit, control method of semiconductor circuit, and electronic apparatus

A semiconductor circuit of the disclosure includes: a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2017/030087 having an international filing date of 23 Aug. 2017, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2016-195757 filed 3 Oct. 2016, the entire disclosures of each of which are incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a semiconductor circuit including a non-volatile storage element, a control method of such a semiconductor circuit, and an electronic apparatus including such a semiconductor circuit.

BACKGROUND ART

For electronic apparatuses, low power consumption is desired from a viewpoint of ecology. In semiconductor circuits, often used is a so-called power gating technique that includes, for example, selective interruption of power supply to some of circuits in order to attain reduction in power consumption. For a circuit to which power supply is thus interrupted, desired is quick restoration, after a restart of the power supply, to an operation slate before the interruption of the power supply. One of methods of achieving such restore operation in a short lime is to incorporate a non-volatile storage element in the circuit (for example, PTL 1 and other documents).

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

However, continuous rewriting over many years causes possibility of so-called aging deterioration in non-volatile storage elements. What is desired is, therefore, to make it possible to suppress influences on circuit operation even in a case with such aging deterioration.

It is desirable to provide a semiconductor circuit, a control method of a semiconductor circuit, and an electronic apparatus that make it possible to suppress influences on circuit operation even in a case with aging deterioration in a non-volatile storage element.

A semiconductor circuit according to an embodiment of the disclosure includes a sequential circuit unit and a first memory. The sequential circuit unit includes a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements. The sequential circuit unit performs, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register. The first memory stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to tire first data. The first memory stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

A control method of a semiconductor circuit according to an embodiment of the disclosure includes: allowing a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements to perform, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and allowing a first memory to store, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

An electronic apparatus according to an embodiment of the disclosure includes a semiconductor circuit and a battery that supplies the semiconductor circuit with a power supply voltage. The semiconductor circuit includes a sequential circuit unit and a first memory. The sequential circuit unit includes a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements. The sequential circuit unit performs, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage stales in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register. The first memory stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data. The first memory stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

In the semiconductor circuit, the control method of the semiconductor circuit, and the electronic apparatus according to the embodiments of the disclosure, in the first term, in the sequential circuit unit, performed are the store operation and the shift operation. In the store operation, by the storage elements in the plurality of the logic circuit units, stored are the respective voltage states in the plurality of the logic circuit units. In the shift operation, the flip flops in the plurality of the logic circuit units operate as the shift register. Moreover, the first data outputted from the shift register by the shift operation, or the second data corresponding to the first data is stored in the first memory.

According to the semiconductor circuit, the control method of the semi conductor circuit, and the electronic apparatus of the embodiments of the disclosure, the logic circuit units are provided with the respective non-volatile storage elements. The first data outputted from the shift register by the shift operation, or the second data is stored in the first memory. Hence, it is possible to suppress the influences on the circuit operation even in the case with the aging deterioration in the non-volatile storage element. It is to be noted that the effects described here are not necessarily limited, and any effect described in the present disclosure may be provided.

MODES FOR CARRYING OUT THE INVENTION

In the following, some embodiments of the disclosure are described in detail with reference to the drawings. It is to be noted that description is made in the following order.1. Embodiment2. Application Example1. Embodiment

Configuration Example

FIG. 1illustrates one configuration example of a semiconductor circuit (semiconductor circuit1) according to one embodiment. The semiconductor circuit1is configured to perform a so-called scan test to make it possible to attain easier evaluation. It is to be noted that a control method of a semiconductor circuit according to an embodiment of the disclosure is embodied by this embodiment, and is therefore described together.

The semiconductor circuit1includes a power supply transistor51, N combinational circuit units10(combinational circuit units10(1) to10(N)), (N-1) sequential circuit units20(sequential circuit units20(1) to20(N-1)), selection units52and53, a test unit54, a memory55, and a control unit56.

The power supply transistor51is, in this example, a F type MOS (Metal Oxide Semiconductor) transistor, and includes a gate to be supplied with a control signal, a source to be supplied with a power supply voltage VDD, and a drain coupled to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54.

With this configuration, in the semiconductor circuit1, it is possible to achieve steep mode operation. Specifically, in the sleep mode operation, the power supply transistor51is brought to an off state, to interrupt power supply to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54. Moreover, in normal operation, the power supply transistor51is brought to an on state, to supply the power supply voltage VDD to these circuits. In the semiconductor circuit1, so-called power gating as mentioned above makes it possible to reduce power consumption.

The combinational circuit units10each include a so-called combinational circuit in which an output signal is univocally determined solely by a signal that is being currently inputted. In this example, the combinational circuit units10each generate a plurality of signals on the basis of a plurality of signals supplied. Specifically, for example, the combinational circuit unit10(1) generates M signals DI(1) to DI(M) on tire basis of a plurality of signals supplied from outside of the semiconductor circuit1, and supplies the signals DI(1) to DI(M) to the sequential circuit unit20(1). Moreover, the combinational circuit unit10(2) generates a plurality of signals on the basis of M signals DO(1) to DO(M) supplied from the sequential circuit unit20(1), and supplies the plurality of the signals generated, to the sequential circuit unit20(2). The same also applies to the combinational circuit units10(3) to10(N-1). Moreover, the combinational circuit unit10(N) generates a plurality of signals on the basis of a plurality of signals supplied from the sequential circuit unit20(N-1), and supplies the plurality of the signals generated, to the outside of the semiconductor circuit1. In this way, in the semiconductor circuit1, the combinational circuit units10(1) to10(N) and the sequential circuit units20(1) to20(N-1) are alternately disposed.

The sequential circuit units20each include a so-called sequential circuit that generates an output signal on the basis of not only a signal that is being currently inputted but also a signal that has been inputted before. The sequential circuit units20perform different kinds of operation in accordance with a scan enable signal SE.

Specifically, as described later, in a case where the scan enable signal SE is “0” (non-active), the sequential circuit units20each generate the plurality of the signals on the basis of the plurality of the signals supplied from the pre-stage combinational circuit unit10and on the basis of a clock signal CLK, and supplies the plurality of the signals generated, to the post-stage combinational circuit unit10. Specifically, for example, the sequential circuit unit20(1) generates the plurality of the signals DO(1) to DO(M) on the basis of the plurality of the signals DI(1) to DI(M) supplied from the pre-stage combinational circuit unit10(1) and on the basis of the clock signal CLK, and supplies the plurality of the signals DO(1) to DO(M) to the post-stage combinational circuit unit10(2). The sequential circuit unit20(2) generates the plurality of the signals on the basis of the plurality of the signals supplied from the pre-stage combinational circuit unit10(2) and on the basis of the clock signal CLK, and supplies the plurality of the signals generated, to the post-stage combinational circuit unit10(3). The same also applies to the sequential circuit units20(3) to20(N-2). Moreover, the sequential circuit unit20(N-1) generates the plurality of the signals on the basis of the plurality of the signals supplied from the pre-stage combinational circuit unit10(N-1) and on the basis of the clock signal CLK, and supplies the plurality of the signals generated, to the post-stage combinational circuit unit10(N).

Moreover, in a case where the scan enable signal SE is “1” (active), the sequential circuit units20perform scan shift operation. Specifically, for example, the sequential circuit unit20(1) receives a signal S(1) supplied from the selection unit52, while generating a signal S(2) by operating as a shift register, and supplies the signal S(2) to the post-stage sequential circuit unit20(2). The sequential circuit unit20(2) receives the signal S(2), while generating a signal S(3) by operating as a shift register and supplies the signal S(3) to the post-Stage sequential circuit unit20(3). The same also applies to the sequential circuit units20(3) to20(N-2). Moreover, the sequential circuit unit20(N-1) receives a signal S(N-1) supplied from the sequential circuit unit20(N-2), while generating a signal S(N) by operating as a shift register, and supplies the signal S(N) to the selection unit53.

FIG. 2illustrates one configuration example of the sequential circuit unit20(1). It is to be noted that the same also applies to the sequential circuit units20(2) to20(N-1). The sequential circuit unit20(1) includes M selectors21(selectors21(1) to21(M)), M flip flops22(flip flops22(1) to22(M)), and the M storage units23(storage units23(1) to23(M)). The M selectors21, the M flip flops22, and the M storage units23are provided in corresponding relation to the M signals DI(I) to DI(M).

The selectors21each select, on the basis of the scan enable signal SE, one of a signal inputted to a first input terminal and a signal inputted to a second input terminal, and outputs the selected signal. Specifically, for example, the selector21(1) selects, in the case where the scan enable signal SE is “0” (non-active), the signal DI(1) and outputs the selected signal as a signal D(1). The selector21(1) selects, in the case where the scan enable signal SE is “1” (active), the signal S(1) and outputs the selected signal as the signal D(1). The selector21(2) selects, in the case where the scan enable signal SE is “0” (non-active), the signal DI(2) and outputs the selected signal as a signal D(2). The selector21(2) selects, in the case where the scan enable signal SE is “1” (active), the signal DO(1) and outputs the selected signal the signal D(2). The same also applies to the selectors21(3) to21(M-1). Moreover, the selector21(M) selects, in the case where the scan enable signal SE is “0” (non-active), the signal DI(M) and outputs the selected signal as a signal D(M). The selector21(M) selects, in the case where the scan enable signal SE is “1” (active), the signal DO(M-1) and outputs the selected signal as the signal D(M).

The flip flops22are each a D type flip flop. The flip flops22each perform, on the basis of a rising edge of the clock signal CLK, sampling of a signal inputted to a data input terminal D, and outputs a result of the sampling through a data output terminal Q. Specifically, the flip flop22(1) performs, on the basis of the rising edge of the clock signal CLK, sampling of the output signal D(1) of the selector21(1), and outputs a result of the sampling as the signal DO(1). The flip flop22(2) performs, on the basis of the rising edge of the clock signal CLK, sampling of the output signal D(2) of the selector21(2), and outputs a result of the sampling as the signal DO(2). The same also applies to the flip flops22(3) to22(M-1). Moreover, the flip flop22(M) performs, on the basis of the rising edge of the clock signal CLK, sampling of the output signal D(M) of the selector21(M), and outputs a result of the sampling as the signal DO(M), while outputting the result of the sampling as the signal S(2).

The storage units23are each a non-volatile storage unit, and each store a voltage state of the corresponding flip flop22, on the basis of signals SR and CTRL. Specifically, on the basis of the signals SR and CTRL, the storage unit23(1) stores a voltage slate of the flip flop22(1) (store operation), or sets the voltage stale of the flip flop22on the basis of information stored (restore operation). The same also applies to the storage units23(2) to23(M).

FIG. 3illustrates one configuration example of the flip flop22(1) and the storage unit23(1). It is to be noted that the same also applies to the flip flops22(2) to22(M) and the storage units23(2) to23(M). The flip flop22(1) includes inverters24and25, a master latch30, and a slave latch40. The storage unit23(1) includes transistors46and47, and storage elements48and49.

The inverter24inverts the clock signal CLK to generate a clock signal CB. The inverter25inverts the clock signal CB to generate a clock signal C.

The master latch30includes an inverter31, transmission gate32, inverters33and34, and a transmission gate35. The inverter31includes an input terminal that is coupled to the data input terminal D of the flip flop22(1) and is supplied with the signal D(1), and an output terminal coupled to one end of the transmission gate32. The transmission gate32includes the one end coupled to the output terminal of the inverter31, and another end coupled to a node N31. The transmission gate32is brought to an on state between the one end and the other end in a case where the clock signal C is at a low level, and is brought to an off state between the one end and the other end in a case where the clock signal C is at a high level. The inverter53includes an input terminal coupled to the node N31, and an output terminal coupled to a node N32. The inverter34includes an input terminal coupled to the node N32, and an output terminal coupled to one end of the transmission gate35. The transmission gate35includes the one end coupled to the output terminal of the inverter34, and another end coupled to the node N31. The transmission gate35is brought to an on state between the one end and the other end in the case where the clock signal C is at the high level, and is brought to an off state between the one end and the other end in the case where the clock signal C is at the low level.

The slave latch40includes a transmission gate41, inverters42and43, a transmission gale44, and an inverter45. The transmission gate41includes one end coupled to the node N32, and another end coupled to a node N41. The transmission gate41is brought to an on state between the one end and the other end in the case where the clock signal C is at the high level, and is brought to an off stale between the one end and the other end in the case where the clock signal C is at the low level. The inverter42includes an input terminal coupled to the node N41, and an output terminal coupled to a node N42. The inverter43includes an input terminal coupled to the node N42, and an output terminal coupled to one end of the transmission gate44. The transmission gate44includes the one end coupled to the output terminal of the inverter43, and another end coupled to the node N41. The transmission gate44is brought to an on state between the one end and the other end in the case where the clock signal C is at the low level and is brought to an off state between the one end and the oilier end in the case where the clock signal C is at the high level. The inverter45includes an input terminal coupled to the node N42, and an output terminal coupled to the data output terminal Q of the flip flop22(1). The inverter45outputs the signal DO(1).

The transistors46and47are each, in this example, an N type MOS transistor. The transistor46includes a drain coupled to the node N41, a gate supplied with the signal SR, and a source coupled to one end of the storage element48. The transistor47includes a drain coupled to the node N42, a gate supplied with the signal SR, and a source coupled to one end of the storage element49.

The storage elements48and49are each a non-volatile storage element, and are each, in this example, a magnetic tunnel junction (MTJ) element of a spin transfer torque (STT) type in which spin injection causes a change in a direction of magnetization of a free layer F (described later) to store information. The storage element48includes the one end coupled to the source of the transistor46, and another end supplied with the signal CTRL. The storage element49includes the one end coupled to the source of the transistor47, and another end supplied with the signal CTRL.

In the following, description is given with the storage element48as an example. It is to be noted that the same also applies to the storage element49. The storage element48includes a pinned layer P, a tunnel barrier layer I, and the free layer F. The pinned layer P includes a ferromagnetic body in which a direction of magnetization PJ is fixed at, for example, a direction perpendicular to a film surface. The free layer F includes a ferromagnetic body in which a direction of magnetization FJ changes in, for example, the direction perpendicular to the film surface, in accordance with a spin polarized current flowing therein. The tunnel barrier layer I breaks magnetic coupling of the pinned layer P and the free layer F, while functioning to allow a tunnel current to flow therethrough.

With this configuration, in the storage element48, for example, a current flow from the free layer F to the pinned layer P causes polarized electrons to be injected from the pinned layer P to the free layer F. The polarized electrons have moment (spin) in the same direction as the magnetization PJ of the pinned layer P. Thus, the direction of the magnetization FJ of the free layer F is brought to the same direction as the direction of the magnetization PJ of the pinned layer P (parallel state). In the storage element48, in the parallel state as mentioned above, a resistance value between both ends becomes low (low resistance state RL).

Moreover, for example, a current flow from the pinned layer P to the free layer F causes electrons to be injected from the free layer F to the pinned layer P. At this occasion, out of the injected electrons, polarized electrons having moment in the same direction as the magnetization PJ of the pinned layer P pass through the pinned layer P, while polarized electrons having moment in an opposite direction to the magnitization PJ of the pinned layer P are reflected from the pinned layer P and are injected to the free layer F. Thus, the direction of the magnetization FJ of the free layer F is brought to the opposite direction to the magnetization PJ of the pinned layer P (anti-parallel stale). In the storage element48, in the anti-parallel state as mentioned above, the resistance value between both ends becomes high (high resistance state RH).

As described, in the storage elements48and49, the direction of the magnetization FJ of the free layer F changes according to the direction of the current flow. This causes a resistance state to change between the high resistance state RH and the low resistance state RL. The storage elements48and49set the resistance state in this way, making it possible to store information.

As described, in the semiconductor circuit1, the storage units23are provided in corresponding relation to the respective flip flops22. Thus, for example, the storage units23perform, in the sleep mode operation, the store operation immediately before the interruption of the power supply, to store the voltage states of the flip flops22. Moreover, the storage units23perform the restore operation after a restart of the power supply, to set the voltage states of the flip flops22on the basis of the information stored in the storage units23. Thus, in the semiconductor circuit1, it is possible to restore, after the restart of the power supply, in a short time, the voltage states of the respective flip flops22to the voltage slates before the interruption of the power supply.

The selection unit52(FIG. 1) selects, on the basis of a control signal supplied from the control unit56, one of a signal SI and a signal SA, and outputs the selected signal as the signal S(1). The signal SI is supplied from the outside of the semiconductor circuit1. The signal SA is supplied from the test unit54.

The selection unit53supplies the signal S(N) to the test unit54as a signal SB, or outputs the signal S(N) to the outside of the semiconductor circuit1as a signal SO, on the basis of a control signal supplied from the control unit56. The signal S(N) is supplied from the sequential circuit unit20(N-1).

The test unit54restarts the power supply in the sleep mode operation, and after the storage units23in the respective sequential circuit units20(1) to20(N-1) performs the restore operation, carries out a test of the information stored in each of the flip flops22. Specifically, as described later, firstly, before the interruption of the power supply, the test unit54acquires the information stored in each of the flip flops22, and performs ECC (Error Correcting Code) processing on the basis of the information acquired, to generate an error correction code CODE1. Moreover, the test unit54allows the memory55to store the error correction code CODE1. Moreover, after the power supply is restarted and the storage units23each perform the restore operation, the test unit54acquires again the information stored in each of the flip flops22, to generate an error correction code CODE2on the basis of the information acquired. Moreover, the test unit54compares the error correction code CODE2and the error correction code CODE1that is stored in the memory55, to carry out the test of the information stored in each of the flip flop22. Moreover, in a case where the error correction code CODE2is incoincident with the error correction code CODE1, the test unit54generates, on the basis of the error correction code CODE1, the information stored in each of the flip flops22before the interruption of the power supply, and supplies the information to each of the flip flops22.

The memory55includes, in this example, an SRAM (Static Random Access Memory), and stores the error correction code CODE1generated by the test unit54. In this example, the memory55is configured to be supplied with the power supply voltage VDD even in a case where the power supply transistor51is brought to the off state. It is to be noted that in this example, the memory55includes the SRAM, bat this is non-limiting. Instead, the memory55may include a volatile memory such as a DRAM (Dynamic Random Access Memory). Alternatively, the memory55may include a non-volatile memory.

The control unit56controls operation of the sequential circuit units20(1) to20(N-1), the selection units52and53, the test unit54, the memory55, and the power supply transistor51. For example, the control unit56may include hardware, or alternatively, the control unit56may include a processor that is able to execute a program.

Here, the selectors21, the nip flops22, and the storage units23correspond one specific example of “logic circuit units” in the disclosure. The sequential circuit units20each correspond to one specific example of a “sequential circuit unit” in the disclosure. The combinational circuit units10each correspond to one specific example of a “first combinational circuit unit” and a “second combinational circuit unit” in the disclosure. The memory55corresponds to one specific example of a “first memory” in the disclosure. The error correction code CODE1corresponds to one specific example of a “first error correction code” in the disclosure. The error correction code CODE2corresponds to one specific example of a “second error correction code” in the disclosure.

Operation and Workings

Description is given next of operation and workings of the semiconductor circuit1of this embodiment.

Outline of Overall Operation

First, with reference toFIG. 1, described is an outline of overall operation of the semiconductor circuit1. In the following, described are a case where normal operation OP1is performed, a case where sleep mode operation OP2is performed, and a case where a test (scan test operation OP3) after manufacture of the semiconductor circuit1is carried out.

FIG. 4illustrates operation of the semiconductor circuit1in performing the normal operation OP1. InFIG. 4, major signals in the normal operation OP1are denoted by thick lines. The combinational circuit unit10(1) generates the M signals DI(1) to DI(M) on the basis of the plurality of the signals supplied from the outside of the semiconductor circuit1. The sequential circuit unit20(1) generates the plurality of the signals DO(1) to DO(M) on the basis of the plurality of the signals DI(1) to DI(M) supplied from the combinational circuit unit10(1) and on the basis of the clock signal CLK. The combinational circuit unit10(2) generates the plurality of the signals on the basis of the M signals DO(1) to DO(M) supplied from the sequential circuit unit20(1). The same also applies to the combinational circuit units10(3) to10(N-1) and the sequential circuit units20(2) to20(N-2). The sequential circuit unit20(N-1) generates the plurality of the signals on the basis of the plurality of the signals supplied from the combinational circuit unit10(N-1) and on the basis of the clock signal CLK. Moreover, the combinational circuit unit10(N) generates the plurality of the signals on the basis of the plurality of the signals supplied from the sequential circuit unit20(N-1), and supplies the plurality of the signals generated, to the outside of the semiconductor circuit1.

FIG. 5illustrates operation of the semiconductor circuit1in performing the sleep mode operation OP2. InFIG. 5, major signals in the sleep mode operation OP2are denoted by thick lines. In the sleep mode operation OP2, the semiconductor circuit1performs preprocessing operation OP21before the interruption of the power supply, and thereafter, interrupts the power supply. Moreover, the semiconductor circuit1performs postprocessing operation OP22after the restart of the power supply.

In the preprocessing operation OP21, first, the sequential circuit units20(1) to20(N-1) perform the scan shift operation. The selection unit S3supplies the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54as the signal SB. The test unit54performs the ECC processing on the basis of the signal SB, to generate the error correction code CODE1, and allows the memory55to store the error correction code CODE1. Moreover, the storage units23of the respective sequential circuit units20(1) to20(N-1) perform the store operation, to store the voltage states of the corresponding flip flops22. Moreover, the power supply transistor51is brought to the off state on the basis of the control signal from the control unit56. This causes the interruption of the power supply to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54.

Moreover, in the postprocessing operation OP22, first, the power supply transistor51is brought to the on stale on the basis of the control signal from the control unit56. This causes the restart of the power supply to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54. Moreover, in accompaniment with the restart of the power supply, the storage units23of the respective sequential circuit units20(1) to21(N-1) perform the restore operation, to set the voltage states of the corresponding flip flops22on the basis of the information stored in the storage units23. Thereafter, the sequential circuit units20(1) to20(N-1) perform the scan shift operation. The selection unit S3supplies the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54as the signal SB. The test unit54performs the ECC processing on the basis of the signal SB, to generate the error correction code CODE2, and compares the error correction code CODE2and the error correction code CODE1that is stored in the memory55, to carry out the test of the information stored in each of the flip flops22. Moreover, in the case where the error correction code CODE2is incoincident with the error correction code CODE1, the test unit54generates, on the basis of the error correction code CODE1, the information stored in each of the flip flops22before the sleep mode operation, and outputs the resultant information as the signal SA. The selection unit52supplies the signal SA supplied from the test unit54, to the sequential circuit unit20(1) as the signal S(1). Moreover, the sequential circuit units20(1) to20(N-1) perform the scan shift operation.

FIG. 6illustrates operation of the semiconductor circuit1in performing the scan test operation OP3. InFIG. 6, major signals in the scan test operation OP3are denoted by thick lines. The selection unit52supplies the signal SI supplied from outside (e.g., a tester), to the sequential circuit unit20(1) as the signal S(1). The sequential circuit units20(1) to20(N-1) perform the scan shift operation. Thus, information included in the signal supplied from the outside is set in the flip flops22of the respective sequential circuit units20(1) to20(N-1). Moreover, the semiconductor circuit1performs the normal operation OP1(FIG. 4) while being supplied with the clock signal CLK by a single pulse from the outside. Thereafter, the sequential circuit units20(1) to20(N-1) perform the scan shift operation again. Moreover, the selection unit S3supplies die signal S(N) supplied from the sequential circuit unit20(N-1), to the outside (e.g., the tester) as the signal SO. In this way, the (ester sets input data of each of the combinational circuit units10while acquiring output data of each of the combinational circuit units10. Moreover, the tester compares the output data with data to be expected. In the semiconductor circuit1, as described, performing tests of the combinational circuit units10(1) to10(N) independently makes it possible to perform a test of the semiconductor circuit1effectively.

Regarding Sleep Mode Operation OP2

Described next are details of the preprocessing operation OP21and the postprocessing operation OP22, in the sleep mode operation OP2.

FIG. 7illustrates one example of the preprocessing operation OP21. In the preprocessing operation OP21, the test unit54generates the error correction code CODE1on the basis of the information stored in each of the flip flops22, and allows the memory55to store the error correction code CODE1, while the storage units23perform the store operation. In what follows, detailed description is given on this operation.

First, the test unit54acquires the information stored in each of the flip flops22, and generates the error correction code CODE1on the basis of the information acquired (step S1). Specifically, first, the sequential circuit units20(1) to20(N-1) perform the scan shift operation on the basis of the control signal supplied from the control unit56. Moreover, the selection unit53supplies, on the basis of the control signal supplied from the control unit56, the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54as the signal SB. Moreover, the test unit54performs the ECC processing on the basis of the signal SB, to generate the error correction code CODE1.

At this occasion, the test unit54outputs, as the signal SA, the signal SB as it is. Moreover, the selection unit52supplies, on the basis of the control signal supplied from the control unit56, the signal SA to the sequential circuit unit20(1) as the signal S(1). Moreover, the sequential circuit units20(1) to20(N-1) continue the scan shift operation until the information stored in each of the flip flops22becomes the same information as before a start of the scan shift operation.

Thereafter, the test unit54allows, on the basis of the control signal supplied from the control unit56, the memory55to store the error correction code CODE1generated in step S1(step S2).

Thereafter, the control unit56brings the signal SR to a high level, to bring the transistors46and47in the storage units23in the respective sequential circuit units20(1) to20(N-1) to the on slate (step S3). This causes the storage units23to be electrically coupled to the respectively corresponding flip flops22.

Thereafter, the storage units23in the respective sequential circuit units20(1) to20(N-1) perform the store operation (step S4).

FIGS. 8A and 8Billustrate one operation example of the slave latch40of the flip flop22, and the storage unit23, in the store operation. InFIGS. 8A and 8B, the transmission gates41and44, and the transistors46and47are depicted as switches that denote their operation states.

In the store operation, the clock signal CLK is stopped, and is fixed at a low level. This brings the clock signal C to the low level, while bringing the clock signal SB to a high level. As a result, the transmission gate41is brought to the off state, while the transmission gate44is brought to the on state. Thus, in the slave latch40, the inverter42inverts a voltage of the node N41, and outputs a result of the inversion to the node N42. The inverter43inverts a voltage of the node N42, and outputs a result of the inversion to the node N41through the transmission gale44. In other words, the slave latch40functions as a so-called bistable circuit.

First, the control unit56brings a voltage of the signal CTRL to a low level voltage VL (ground level) (FIG. 8A). This causes, in the storage units23, a current to flow through one of the storage elements48and49in accordance with the information stored in the slave latch40. In this example, a voltage VN41of the node N41is a high level voltage VH, while a voltage VN42of the node N42is the low level voltage VL. Accordingly, a store current Istore1flows through the inverter43, the transmission gale44, the transistor46, and the storage element48in this order. At this occasion, in the storage element48, the store current Istore1flows from the pinned layer P to the free layer F, bringing the direction of the magnetization FJ of the free layer F to the opposite direction to the direction of the magnetization PJ of the pinned layer P (anti-parallel state). As a result, the resistance state of the storage element48is brought to the high resistance state RH.

Thereafter, the control unit56brings the voltage of the signal CTRL to the high level voltage VH (FIG. 8B). This causes, in the storage units23, a current to How through another of the storage elements48and49in accordance with the information stored in the slave latch40. In this example, a store current Istore2flows through the storage element49, the transistor47, the transmission gate44, and the inverter42in this order. At this occasion, in the storage element49, the store current Istore2flows from the free layer F to the pinned layer P, bringing the direction of the magnetization FJ of the free layer F to the same direction as the direction of the magnetization PJ of the pinned layer P (parallel state). As a result, the resistance state of the storage element49is brought to the low resistance state RL.

As described, in the sequential circuit units20(1) to20(N-1), the respective storage units23store the voltage states of the corresponding flip flops22.

Thereafter, the control unit56brings the signal SR to a low level, bringing the transistors46and47in the storage units23in the respective sequential circuit units20(1) to20(N-1) to the off state (step S5). Thus, the storage units23are electrically disconnected from the respectively corresponding flip flops22.

Thereafter, the control unit56brings the power supply transistor51to the oil state (step S6). This causes the interruption of the power supply to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54. It is to be noted that the power supply to the memory55and the control unit56is maintained.

Thus, the preprocessing operation OP21is ended. Moreover, the semiconductor circuit1performs the postprocessing operation OP22after a lapse of time.

FIG. 9illustrates one example of the postprocessing operation OP22. In the postprocessing operation OP22, the storage units23perform the restore operation, and thereafter, the test unit54carries out the test of the information stored in each of the flip flops22. In what follows, detailed description is given on this operation.

First, the control unit56brings the signal SR to the high level, to bring the transistors46and47of the storage units23in the respective sequential circuit units20(1) to20(N-1) to the on stale (step S11. This causes the storage units23to be electrically coupled to the respectively corresponding flip flops22.

Thereafter, the control unit56brings the power supply transistor51to the on state (step S12). This causes the restart of the power supply to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54.

Moreover, in accompaniment with the restart of the power supply, the storage units23in the respective sequential circuit units20(1) to20(N-1) perform the restore operation (step S13).

FIG. 10illustrates one operation example of the slave latch40of the flip flop22, and the storage unit23, in the restore operation. In the restore operation, as with the store operation, the clock signal CLK is stopped, and is fixed at the low level. This brings the transmission gate41to the off state, while bringing the transmission gate44to the on state. Moreover, the control unit56brings the voltage of the signal CTRL to the low level voltage VL (ground level).

Thus, the node N41is grounded through the transistor46and the storage element48, while the node N42is grounded through the transistor47and the storage element49. At this occasion, because the resistance slates of the storage elements48and49differ from each other, a voltage state in the slave latch40is determined in accordance with the resistance states of the storage elements48and49. In this example, the resistance stale of the storage element48is the high resistance state RH, while the resistance state of the storage element49is the low resistance state RL. Accordingly, the node N41is pulled down by the high resistance value, while the node N42is pulled down by the low resistance value. Thus, the voltage VN41of the node N41is brought to the high level voltage VH, while the voltage VN42of the node N42is brought to the low level voltage VL.

In this way, in the sequential circuit units20(1) to20(N-1), the storage units23set the voltage states of the respectively corresponding flip flops22on the basis of the information stored.

Thereafter, the control unit56brings the signal SR to the low level, bringing the transistors46and47of the storage units23in the respective sequential circuit units20(1) to20(N-1) to the off state (step S14). This causes the storage units23to be electrically disconnected from the respectively corresponding flip flops22.

Thereafter, the test unit54acquires the information stored in each of the flip flops22, and generates the error correction code CODE2on the basis of the information acquired (step S15). Specifically, first, the sequential circuit units20(1) to20(N-1) perform the scan shift operation on the basis of the control signal supplied from the control unit56. Moreover, the selection unit53supplies, on the basis of the control signal supplied from the control unit56, the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54as the signal SB. Moreover, the test unit54performs the ECC processing on the basis of the signal SB, to generate the error correction code CODE2.

At this occasion, the test unit54outputs, as the signal SA, the signal SB as it is. Moreover, the selection unit52supplies, on the basis of the control signal supplied from the control unit56, the signal SA to the sequential circuit unit20(1) as the signal S(1). Moreover, the sequential circuit units20(1) to20(N-1) continue the scan shift operation until the information stored in each of the flip flops22becomes the same information as before the start of the scan shift operation.

Thereafter, the test unit54compares the error correction code CODE2generated in step S15, with the error correction code CODE1stored in the memory55(step S16). Moreover, in a case where the error correction codes CODE1and CODE2are coincident (“Y” in step S17), the flow is ended.

Meanwhile, in a case where the error correction codes CODE1and CODE2are incoincident (“N” in step S17), the test unit54generates, on the basis of the error correction code CODE1, the information stored in each of the flip flops22before the interruption of the power supply, and supplies the information generated, to the sequential circuit units20(1) to20(N-1) (step S18). Specifically, the test unit54outputs the information generated, as the signal SA. Moreover, the selection unit52supplies, on the basis of the control signal supplied from the control unit56, the signal SA supplied from the test unit54, to the sequential circuit unit20(1) as the signal S(1). Moreover, the sequential circuit units20(1) to20(N-1) perform the scan shift operation. Thus, the semiconductor circuit1sets the flip flops22of the respective sequential circuit units20(1) to20(N-1), on the basis of the information generated by the test unit54.

Thus, the postprocessing operation OP22is ended. After this, the semiconductor circuit1performs the normal operation OP1.

As described, in the semiconductor circuit1, provided are the storage units23that store the voltage states of the respective flip flops22. Hence, it is possible to restore the voltage states of the respective flip flops22to the voltage stales before the interruption of the power supply, after the restart of the power supply, in a short time and with little energy. Specifically, for example, let us consider a case where no storage units23are provided and in the postprocessing operation OP22, the information stored in each of the flip flops22before the interruption of the power supply is generated on the basis of the error correction code CODE1stored in the memory55, and the information generated is supplied to the sequential circuit units20(1) to20(N-1). In this case, there is possibility that processing of restoring the voltage states of the respective flip flops22takes time and energy. Meanwhile, in the semiconductor circuit1, provided are the storage units23that store the voltage states of the respective flip flops22. Hence, it is possible to restore the voltage states of the respective flip flops22in a short time and with little energy.

Moreover, in the semiconductor circuit1, in the postprocessing operation OP22, in the case where the error correction code CODE1and the error correction code CODE2are coincident, the normal operation OP1is promptly performed. Hence, it is possible to start the normal operation OP1after the restart of the power supply in a short time and with little energy.

Moreover, in the semiconductor circuit1, after the power supply is restarted, and the storage units23in the respective sequential circuit units20(1) to20(N-1) perform the restore operation, the test of the information stored in each of the flip flops22is carried out. Hence, it is passible to suppress influences on circuit operation even in a case with aging deterioration in the storage elements48and49in the respective storage units23. Specifically, in general, continuous rewriting over many years may cause possibility of the aging deterioration in non-volatile storage elements. In this case, for example, in spite of attempts to allow the storage elements to store information, there is possibility of a failure in allowing them to store information correctly. In the semiconductor circuit1, the error correction code CODE1is generated in the preprocessing operation OP21, while the error correction code CODE2is generated in the postprocessing operation OP22. The error correction code CODE1and the error correction code CODE2are compared to carry out the test of the information stored in each of the flip flops22. Thus, in the case where the error correction codes CODE1and CODE2are incoincident with each other, the test unit54determines that in the preprocessing operation OP21, the storage elements48and49has failed in storing the information correctly because of the aging deterioration. The test unit54generates, on the basis of the error correction code CODE1, the information stored in each of the flip flops22before the interruption of the power supply. Hence, in the semiconductor circuit1, it is possible to suppress the influences on the circuit operation, even in the case with the aging deterioration in the storage elements48and49.

Moreover, in the semiconductor circuit1, in the preprocessing operation OP21, the test unit54acquires the information in each of the flip flops22to generate the error correction code CODE1(step S1), and thereafter, the storage units23perform the store operation (step S4). Hence, it is possible to reduce possibility of erroneous circuit operation. Specifically, while the storage units23perform the store operation, as illustrated inFIGS. 8A and 8B, the store currents Istore1and Istore2flow, in a case where current values of the store currents Istore1and Istore2are large, for example, the information stored in the slave latch40is lost, causing possibility of so-called disturbance. Accordingly, if the storage units23perform the store operation, and thereafter, the test unit54acquires the information in each of the flip flops22to generate the error correction code CODE1, there is possibility that the test unit54generates the error correction code CODE1on the basis of incorrect information. Meanwhile, in the semiconductor circuit1, the test unit54acquires the information in each of the flip flops22to generate the error correction code CODE1, and thereafter, the storage units23perform the store operation (step S4). Thus, even if disturbance occurs in the store operation, the error correction code CODE1is kept from being influenced by the disturbance. Hence, it is possible to reduce the possibility of the erroneous circuit operation.

Moreover, in the semiconductor circuit1, the error correction code CODE1is stored in the memory55. Hence, it is possible to reduce storage capacity of the memory55, as compared to a case where the information stored in each of the flip flops22is stored in the memory55as it is.

Moreover, in the semiconductor circuit1, the test of the information stored in each of the flip flops22is carried out in the sleep mode operation OP2, with the utilization of a system of the test (scan test operation OP3) after the manufacture of the semiconductor circuit1. Hence, it is possible to carry out the test of the information stored in each of the flip flops22, while simplifying a circuit configuration.

Effects

As described, in this embodiment, provided are the storage units that store the voltage states of the respective flip flops. Hence, it is possible to restore the voltage states of the respective flip flops to the voltage states before the interruption of the power supply, after the restart of the power supply, in a short time and with little energy.

In this embodiment, in the postprocessing operation, in the case where the error correction codes are coincident with each other, the normal operation is promptly performed. Hence, it is possible to start the normal operation after the restart of the power supply, in a short time and with little energy.

In this embodiment, the test of the information stored in each of the Hip flops is carried out, after the power supply is restarted, and the flip flops each perform the restore operation. Hence, it is possible to suppress the influences on the circuit operation even in the case with the aging deterioration in the storage elements.

In this embodiment, in the preprocessing operation, the test unit acquires the information in each of the flip flops to generate the error correction code CODE1, and thereafter, the storage units perform the store operation. Hence, it is possible to reduce the possibility of the erroneous circuit operation.

In this embodiment, the error correction code CODE1is stored in the memory. Hence, it is possible to reduce the storage capacity of the memory.

Modification Example 1

In the forgoing embodiment, the drain of the power supply transistor51is coupled to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54. However, this is non-limiting. Instead, as in a semiconductor circuit1A illustrated inFIG. 11, the drain of the power supply transistor51may be further coupled to a memory55A. In this example, the memory55A includes a non-volatile memory such as a magnetoresisttve memory (MRAM; Magnetoresistive Random Access Memory), a phase change memory (PCRAM; Phase Change Random Access Memory), and a resistance change type memory (ReRAM; Resistive Random Access Memory). The memory55A is supplied with the power supply voltage VDD, by bringing the power supply transistor51to the on state. In the semiconductor circuit1A, in the sleep mode operation, bringing the power supply transistor51to the off slate causes the interruption of the power supply to the memory55A, in addition to the N combinational circuit units10, the (N-1) sequential circuit units20, the selection units52and53, and the test unit54. Hence, in the semiconductor circuit1A, it is possible to reduce power consumption.

Moreover, as in a semiconductor circuit1B illustrated inFIG. 12, a memory57B and a control unit56B may be provided. The memory57B stores various kinds of information, and includes a non-volatile memory of the same kind as the memory55A. The memory57A is supplied with the power supply voltage VDD, by bringing the power supply transistor51to the on state. The control unit56B controls operation of the semiconductor circuit1B. Here, the memory57B corresponds to one specific example of a “second memory” in the disclosure.

In the semiconductor circuit1B, it is desirable that a size of a storage element of the memory55A is larger than a size of a storage element of the memory57B. Specifically, because the memory55A stores the error correction code CODE1, a low writing error rate is desirable. By allowing the size of the storage element of the memory55A to be larger than the size of the storage element of the memory57B, reduction in the writing error rate is expected.

Modification Example 2

In the forgoing embodiment, the test unit54and the memory55are provided separately. However, this is non-limiting. Instead, for example, as in a semiconductor circuit1C illustrated inFIG. 13, a test unit54C may be provided inside a memory55C. Specifically, in general, inside a memory, provided is a block that performs the ECC processing. Using such a memory as the memory55C leads to a simplified configuration.

Modification Example 3

In the forgoing embodiment, the test unit54performs the ECC processing to generate the error correction codes CODE1and CODE2. However, this is non-limiting. In what follows, described are details of a semiconductor circuit1D according to this modification example.

FIG. 14illustrates one configuration example of the semiconductor circuit1D according to this modification example. The semiconductor circuit1D includes a test unit54D and a memory55D. The test unit54D allows, in the preprocessing operation OP21, the memory55D to store the information acquired from each of the flip flops22, as saved data DATA, and compares, in the postprocessing operation OP22, the information acquired from each of the flip flops22and the saved data DATA. The memory55D stores the saved data DATA.

Described next are details of the preprocessing operation OP21and the postprocessing operation OP22, in the sleep mode operation OP2related to the semiconductor circuit1D.

FIG. 15illustrates one example of the preprocessing operation OP21. First, the test unit54D acquires the information stored in each of the flip flops22(step S21). Specifically, first, the sequential circuit units20(1) to20(N-1) perform the scan shift operation, on the basis of the control signal supplied from the control unit56. Moreover, the selection unit53supplies, on the basis of the control signal supplied from the control unit56, the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54D as the signal SB. Thereafter, the test unit54D allows, on the basis of the control signal supplied from the control unit56, the memory55D to store the information acquired in step S21, as the saved data DATA (step S22). Moreover, the control unit56brings the transistors46and47of the storage units23in the respective sequential circuit units20(1) to20(N-1) to the on state (step S3). The storage units23each perform the store operation (step S4). The control unit56brings the transistors46and47of each of the storage units23to the off state (step S5). The control unit56brings the power supply transistor51to the off state (step S6).

FIG. 16illustrates one example of the postprocessing operation OP22. First, the control unit56brings the transistors46and47of the storage units23in the respective sequential circuit units20(1) to20(N-1) to the on state (step S11), and brings the power supply transistor51to the on state (step S12). The storage units23each perform the restore operation (step S13). The control unit56brings the transistors46and47of each of the storage units23to the off state (step S14).

Thereafter, the test unit54D acquires the information stored in each of the flip flops22(step S35). Specifically, first, the sequential circuit units20(1) to20(N-1) perform the scan shift operation on the basis of the control signal supplied from the control unit56. Moreover, the selection unit53supplies, on the basis of the control signal supplied from the control unit56, the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54D as the signal SB.

Thereafter, the test unit54D compares the information acquired in step S35with the saved data DATA stored in the memory55D (step S36). Moreover, in a case where the information acquired in step S35and the saved data DATA are coincident (“Y” in step S37), the flow is ended.

Meanwhile, in a case where the information acquired in step S35and the saved data DATA are incoincident (“N” in step S37), the test unit54D supplies the saved data DATA to the sequential circuit units20(1) to20(N-1) (step S38). Specifically, the test unit54D outputs the saved data DATA as the signal SA. Moreover, the selection unit52supplies, on the basis of the control signal supplied from the control unit56, the signal SA supplied from the test unit54D, to the sequential circuit unit20(1) as the signal S(1). Moreover, the sequential circuit units20(1) to20(N-1) perform the scan shift operation. In this way, the semiconductor circuit1D sets the flip flops22of the respective sequential circuit units20(1) to20(N-1), on the basis of the saved data DATA. Thus, the flow is ended.

As described, in the semiconductor circuit1D, the test unit54D keeps from performing the ECC processing. Hence, it is possible to simplify a configuration of the test unit54D.

Modification Example 4

In the forgoing embodiment, the test unit54performs the ECC processing to generate the error correction codes CODE1and CODE2, and compares the error correction codes CODE1and CODE2. However, this is non-limiting. Described below are details of a semiconductor circuit1E according to this modification example.

The semiconductor circuit1E includes a test unit54E. In the preprocessing operation OP21, the test unit54E operates similarly to the case of the forgoing embodiment (FIG. 7). Meanwhile, in the postprocessing operation QP22, the test unit54E generates, on the basis of the error correction code CODE1, the information stored in each of the flip flops22before the interruption of the power supply, and compares the information generated, and the information acquired from each of the flip flops22.

FIG. 17illustrates one example of the postprocessing operation OP22related to the semiconductor circuit1E. First, the control unit56brings the transistors46and47of the storage units23in the respective sequential circuit units20(1) to20(N-1) to the on state (step S11), and brings the power supply transistor51to the on state (step S12). The storage units23each perform the restore operation (step S13). The control unit56brings the transistors46and47of each of the storage units23to the off state (step S14).

Thereafter, the test unit54E generates, on the basis of the error correction code CODE1stored in the memory55, the information stored in each of the flip flops22before the interruption of the power supply (data DATA1) (step S45).

Thereafter, the test unit54E acquires the data stored in each of the flip flops22(data DATA2) (step S46). Specifically, first, the sequential circuit units20(1) to20(N-1) perform the scan shift operation on the basis of the control signal supplied from the control unit56. Moreover, the selection unit53supplies, on the basis of the control signal supplied from the control unit56, the signal S(N) supplied from the sequential circuit unit20(N-1), to the test unit54E as the signal SB.

Thereafter, the test unit54E compares the data DATA1generated in step S45and the data acquired in step S46(step S47). Moreover, in a case where the data DATA1and the data DATA2are coincident (“Y” in step S48), the flow is ended.

Meanwhile, in a case where the data DATA1and the data DATA2are incoincident (“N” in step S48), the test unit54E supplies the data DATA1to the sequential circuit units20(1) to20(N-1) (step S38). Thus, the flow is ended.

With this configuration as well, it is possible to produce similar effects to the case of the forgoing embodiment.

Modification Example 5

In the forgoing embodiment, in the preprocessing operation OP21, the test unit54acquires the information in each of the flip flops22to generate the error correction code CODE1, and thereafter, the storage units23perform the store operation. However, this is non-limiting. Instead, for example, in a case with a configuration in which disturbance is unlikely to occur in the store operation, as illustrated inFIG. 18, the storage units23may perform the store operation (step S4) and thereafter, the test unit54may acquire the information in each of the flip flops22to generate the error correction code CODE1(step S1).

Modification Example 6

In the forgoing embodiment, the storage elements48and49include the magnetic tunnel junction elements of the spin transfer torque type. However, this is non-limiting. Any storage elements may be used insofar as they are able to store the voltage states of the flip flops22. Specifically, for example, storage elements of a current drive type may be used, or alternatively, storage elements of a voltage drive type may be used. Examples applicable to the storage elements of the current drive type include storage elements used in the phase change random access memory (PCRAM) and storage elements used in the resistive random access memory (ReRAM) in addition to the MTJ elements. These storage elements may be of a unipolar type, or alternatively, the storage elements may be of a bipolar type. Examples applicable to the storage elements of the voltage drive type include storage elements used in a ferroelectric memory (FeRAM; Ferroelectric Random Access Memory) and a magnetic memory (MeRAM; Magnetoelectric Random Access Memory).

Modification Example 7

In the forgoing embodiment, as illustrated inFIG. 2, the sequential circuit units20include the flip flops22, but this is non-limiting. Instead, the sequential circuit units may include various logic circuits. Specifically, for example, inFIG. 2, a set of circuitry including the selector21, the flip flop22, and the storage unit23may be replaced with a circuit described in PTL 1 (e.g., a logic circuit60illustrated inFIG. 19).

The logic circuit60includes an NMOS logic circuit61, flip flops62and63, a through current control circuit64, non-volatile resistors R1and R2, and transistors P1to P8. Described below is corresponding relation in a case of replacement of the selector21(1), the flip flop22(1), and the storage unit23(1) in the forgoing embodiment. A signal Din corresponds to, for example, the signal DI(1) to be inputted to the selector21(1) illustrated inFIG. 2. Signals TDin and /TDin correspond to, for example, the signal S(1) to be inputted to the selector21(1) illustrated inFIG. 2. A signal CUC corresponds to the clock signal CLK illustrated inFIG. 2. Signals TE and /TE correspond to the scan enable signal SB illustrated inFIG. 2. Signals Q, /Q, TDout, and /TDout correspond to the signal DO(1) illustrated inFIG. 2. Here, the logic circuit60corresponds to one specific example of a “logic circuit unit” in the disclosure.

In the normal operation OP1, on the basis of the signal Din, generated are the signals Dout, /Dout, Q, and /Q corresponding to a logic of the NMOS logic circuit61. Moreover, in the sleep mode operation OP2and the scan test operation OP3, the signals TDout and /TDout are generated on the basis of the signals TDin and /TDin.

With this configuration, the sequential circuit units20is able to perform various operations in accordance with the NMOS logic circuit61, leading to higher degree of freedom of operation.

Other Modification Examples

Moreover, two or more of these modification examples may be combined.

2. Application Example

Description is given next of an application example of the semiconductor circuits described in the forgoing embodiment and the modification examples.

FIG. 20illustrates an external appearance of a smartphone to which the semiconductor circuits according to the forgoing example embodiments are applied. The smartphone includes, for example, a main body310, a display unit320, and a battery330.

The semiconductor circuits of the forgoing example embodiments are applicable to electronic apparatuses of various fields, e.g., a digital camera, a notebook personal computer, a portable game machine, and a video camera, in addition to the smartphone as mentioned above. In particular, the technology is effective for application to portable electronic apparatuses including batteries.

Although description has been made by giving the embodiment and the modification examples, and their specific applied examples and the application example to the electronic apparatus as mentioned above, the contents of the technology are not limited to the above-mentioned example embodiments and may be modified in a variety of ways.

For example, in the forgoing example embodiments, the power supply transistor51is provided and is turned on or off to control supply of the power supply voltage VDD. However, this is non-limiting. Instead, for example, a transistor may be provided on ground side and be turned on or off to control supply of a voltage VSS. In another alternative, for example, an internal circuit may be provided with a regulator circuit that supplies a power supply voltage. The supply of the power supply voltage may be controlled by turning on or off operation of the regulator circuit.

It is to be noted that the effects described in this specification are mere examples and non-limiting, and there may be other effects.

It is to be noted that the technology may have the following configurations.

a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and

a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

(2) The semiconductor circuit according to (1), further including a test unit,

in which the sequential circuit unit performs, in a second term after the first term, restore operation and the shift operation in order, the restore operation including setting the voltage states of the plurality of the logic circuit units on the basis of information stored in the storage elements in the plurality of the logic circuit units, and

the test unit carries out, in the second term, on the basis of the first data or the second data, a test of third data outputted from the shift register by the shift operation, the first data or the second data being stored in the first memory.

(3) The semiconductor circuit according to (2), in which

the test unit generates, in the second term, fourth data on the basis of a result of the test of the third data, and supplies the fourth data to the shift register, and

the sequential circuit unit performs, in the second term, the shift operation to set the fourth data at initial data of the flip flops in the plurality of the logic circuit units.

(4) The semiconductor circuit according to (2) or (3), further including.

a first combinational circuit that supplies fifth data to the sequential circuit unit; and

a second combinational circuit that operates on the basis of sixth data,

in which the sequential circuit unit performs, in a third term after the second term, processing operation that includes generating the sixth data on the basis of the fifth data.

(5) The semiconductor circuit according to (3) or (4), in which

the first memory stores the second data.

the test unit generates, in the first term, a first error correction code on the basis of the first data, and

the second data is the first error correction code.

(6) The semiconductor circuit according to (5), in which the test unit obtains, in the second term, a second error correction code on the basis of the third data, and compares the first error correction code and the second error correction code to carry out the test of the third data.

(7) The semiconductor circuit according to (6), in which the test unit generates the fourth data on the basis of the first error correction code, on the condition that the first error correction code and the second error correction code are incoincident.

(8) The semiconductor circuit according to (5), in which in the second term, the test unit generates the first data on the basis of the first error correction code, and compares the first data and the third data to carry out the test of the third data.

(9) The semiconductor circuit according to (8), in which the test unit supplies, as the fourth data, the first data to the shift register, on the condition that the first data and the third data are incoincident.

(10) The semiconductor circuit according to (3) or (4), in which

the first memory stores the first data, and

the test unit compares, in the second term, the third data and the first data to carry out the test of the third data, the first data being stored in the first memory.

(11) The semiconductor circuit according to (10), in which the test unit supplies, as the fourth data, the first data to the shift register, on the condition that the third data and the first data are incoincident, the first data being stored in the first memory.

(12) The semiconductor circuit according to any one of (2) to (11), further including a control unit that performs a power supply control, to perform, in the first term and the second term, power supply to the sequential circuit unit, and to interrupt in a fourth term between the first term and the second term, the power supply to the sequential circuit unit.

(13) The semiconductor circuit according to any one of (1) to (12), in which in the first term, the sequential circuit unit performs the store operation after performing the shift operation.

(14) The semiconductor circuit according to any one of (1) to (12), in which in the first term, the sequential circuit unit performs the shift operation after performing the store operation.

(15) The semiconductor circuit according to any one of (1) to (14), in which

the flip flops each include a master latch and a slave latch, and

the storage elements are each configured to be connectable to the slave latch.

(16) The semiconductor circuit according to (15), in which the slave latch includes

a first circuit configured to generate, on the basis of a voltage at a first node, an inverted voltage of the relevant voltage, and to be able to apply the inverted voltage to a second node, and

a second circuit configured to generate, on the basis of a voltage at the second node, an inverted voltage of the relevant voltage, and to be able to apply the inverted voltage to the first node, and

the storage elements each include a first storage element and a second storage element, the first storage element being configured to be connectable to the first node, and the second storage element being configured to be connectable to the second node.

(17) The semiconductor circuit according to any one of (1) to (16), in which the storage elements each store information on the basis of a current to be applied.

(18) The semiconductor circuit according to (17), in which the storage elements are each an element of a unipolar type or a bipolar type.

(19) The semiconductor circuit according to any one of (1) to (16), in which the storage elements each store information on the basis of a voltage to be applied.

(20) The semiconductor circuit according to any one of (1) to (19), further including a second memory including a storage element of a same kind as a storage element of the first memory,

in which a size of the storage element of the first memory is larger than a size of the storage element of the second memory.

(21) A control method of a semiconductor circuit, the control method including:

allowing a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements to perform, in a first term, store operation in which the Storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and

allowing a first memory to store, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

(22) The control method of the semiconductor circuit according to (21), further including:

allowing the sequential circuit unit to perform, in a second term after the first term, restore operation and the shift operation in order, the restore operation including setting the voltage slates of the plurality of the logic circuit units on the basis of information stored in the storage elements in the plurality of the logic circuit units, and allowing a test unit to carry out, in the second term, on the basis of data stored in the first memory, a test of third data outputted from the shift register by the shift operation.

(23) An electronic apparatus including:

a semiconductor circuit; and

a battery that supplies the semiconductor circuit with a power supply voltage,

the semiconductor circuit including

a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register, and

a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

This application claims the benefit of Japanese Priority Patent Application JP2016-195757 filed with the Japan Patent Office on Oct. 3, 2016, the entire contents of which are incorporated herein by reference.