Slew rate control

A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.

BACKGROUND

Universal Serial Bus (USB) devices that communicate with a host over USB include USB printers, scanners, digital cameras, storage devices, card readers, and the like. USB based systems may require that a USB host controller be present in the host system, and that the operating system (OS) of the host system support USB and USB Mass Storage Class Devices. USB2 devices may communicate over the USB bus at low speed (LS), full speed (FS), or high speed (HS). A connection between a USB device and a host may be established via a four wire interface that includes a power line, a ground line, and a pair of data line, differential voltage plus (D+) and differential voltage minus (D−), or for the case of USB On-The-Go (OTG), a fifth line named ID (identification pin) may be added. When a USB device connects to the host, the USB device may first pull a D+ line high (or the D− line if the device is a low speed device) using a pull up resistor on the D+ line when connecting as FS (Full Speed) mode. The host may respond by resetting the USB device. If the USB device is a high-speed USB device, the USB device may “chirp” by driving the D− line high during the reset. The host may respond to the “chirp” by alternately driving the D+ and D− lines high. The USB device may then electronically remove the pull up resistor and continue communicating at high speed if both communicating devices are HS capable. Disconnection at high-speed happens when a cable is removed and HS RX terminal on USB device is removed. It results in doubling HS amplitude on the USB host transmitter. The USB2 specification defines a mechanism to detect differential line voltage using differential difference receiver detectors.

The success of USB2.0 technology has enjoyed wide adoption in almost every computing device, with tremendous ecosystem support not only in terms of device choice to support various platform features, but also in terms of technology development with well-established hardware IP portfolios and standardized software infrastructure. It is foreseeable that the great asset of USB2.0 technology will continue to benefit the ecosystem for years to come. As power efficiency becomes increasingly critical in today's computing devices, there is a need for IO technology to be optimized for both active and idle power. USB2.0 technology, originally optimized for external device interconnect, is primed to be enhanced for inter-chip interconnect such that the link power can be further optimized. Meantime, silicon technology continues to scale. Device dimensions are getting smaller and therefore more devices can be packed onto a single integrated chip. However, the device reliability challenge arising from the densely packed transistors has become more profound. The manufacturing cost for an advanced process technology to support 3.3V IO signaling has grown exponentially. A low voltage USB2.0 solution is therefore required to address the gap. Embedded USB is a newer standard to fill the gap caused due to advance silicon processes.

At system level, eUSB2 to USB2.0 bridge (eUSB2 repeater) is required to support host (SoC) communication to external USB2.0 compliant devices via USB connectors. eUSB2/USB2 and USB2/USB2 repeaters require both squelch detector (SQD) and disconnect detector (DCD) at USB2.0 connector port for highspeed (HS) communication (SQD and DCD for USB2 port and SQD for eUSB port). Each of the SQD and DCD work at 480 Mbps range, but support different functionalities. The invention describes method to combine squelch detector and disconnect detector in an eUSB2 or USB2 repeater.

SUMMARY

In one embodiment, slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse

In some examples, the impedance control circuit includes one or more resistors each coupled with a switch in series. The impedance control circuit includes a second resistor that is coupled in parallel with the one or more resistors and the switch. The value of the second resistor is equivalent to a predetermined output impedance of the slew rate control circuit. The slew rate control circuit may also include an one shot generation circuit to generate the one shot pulse at a rising edge of the input signal. The one shot generation circuit further configured to generate the one shot pulse at a falling edge of the input signal. The one shot generation circuit includes one or more RC stages. The number of the one or more RC stages depends on a desired pulse width of the one shot pulse. The trim code is disabled/enabled during a pulse width of the one shot pulse to turn the switches of the weighted resistors on or off. The slew rate control circuit may also include a decoder to increase a width of the trim code and the decoded trim code is used to drive switches coupled in series with the one or more resistors. The decoded trim code is configured to turn off one or more switches coupled in series with the one or more resistors to temporarily increase the adjustable impedance during a pulse width period of the one shot pulse. The impedance control circuit is configured to revert back the adjustable impedance to an original value that exists prior to the rising edge of the one shot pulse at a falling edge of the one shot pulse.

In some examples, the slew rate control circuit may be employed in USB repeater or transceiver or the slew rate control circuit may also be employed in a USB to embedded USB (eUSB) repeater.

In some examples, the trim code is predetermined and remains same during a plurality of pulse of the input signal. However, in some other embodiments, the trim code may be generated using a feedback loop. The feedback loop is configured to receive an input from the output port and to generate the trim code based on the input from the output port.

In another embodiment, a slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port, a feedback loop configured to receive an input from the output port to generate a one shot pulse width control signal and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using the trim code and the one shot pulse. The trim code is enabled during a pulse width of the one shot pulse to temporality increase or decrease a value of the adjustable impedance.

The feedback loop may include a slew rate measurement module configured to measure a slew rate at the output port and an one shot pulse width adjustment module to generate a pulse width control signal based on the measured slew rate and a prestored desired slew rate value.

DETAILED DESCRIPTION

Embodiments herein describe a slew rate or pulse rise/fall control circuit or circuits. Even though the description has used USB to describe the embodiments, a person skilled in the art would appreciate that the embodiment described herein may also be used in other application where there is a need to control the rise/fall time of a pulse.

FIG. 1shows a simplified eUSB/USB2 or USB2/USB2 repeater100which is fully or semi differential. The repeater100includes input ports eusb_dp or usb2_dp (e.g., USB D+) and eusb_dm or usb2_dm (e.g., USB D−). Two input stages102-1,102-2are included to receive the input signals. The input stages102-1,102-2may include circuits to filter the noise and amplify the input signals. A logic circuit104may be included to combine predefined controlled bits to the input signals. The output of the logic circuit104is received by a Low Speed (LS)/Full Speed (FS) transmitter (Tx)106. The LS/FS Tx106may also include an input signal fsls_mode to select FS mode or LS mode of transmission. The appropriate transmission mode can be selected based on a destination device that is receiving the data. Typically, in LS mode, the LS/FS Tx106will transmit data at 1.5 Mbps and in FS mode, the data transmission rate can be 12 Mbps. In some embodiments, a high speed mode (HS) may be included to transmit data at 480 Mbps.

The output of the LS/FS Tx106is coupled with a termination stage108to provide a required output impedance. Typically, USB2 standards require a typical output impedance of 45 ohms with an acceptable range from 40 to 50 ohms. Process variation without trimming or calibration, depends on the employed technology, can be ˜±15-30% instead of ˜±10% allowable range which leads to need of trimming/calibration. The termination stage108includes a resistor Rs (one for each D+ and D− lines) that includes a first terminal110and a second terminal112. The termination stage108includes a port to receive a control signal CTRL. The termination stage108is configured to change its impedance based on the control signal CTRL.

FIG. 2shows the termination stage108coupled with a control circuit that generates the control signal CTRL. The control circuit includes one or more AND gates114, each receive one bit of a trim code and a one-shot pulse. In some examples, the trim code may be predetermined through the process of calibration of the USB repeater100to achieve a desired slew rate at the output of the USB repeater100. The trim code may be N bit wide where N can be equal to or more than one. The output of one or more AND gates114is inputted to a N-to-M decoder116to convert the N bit trim code to a M bit control signal (CTRL). One or more bits of the M bit control signal each is used to drive a switch (e.g., S1, S2. . . SMthat are coupled in series with resistors R1, R2. . . RMrespectively). At least one resistor R0does not include a switch in the series, hence even if all switches (S1, S2. . . . SM) are off, there will still be a predefined resistance between the terminals110and112. In the USB2 example, the value of equal resistor, RS=R0∥B1R1∥ . . . ∥BMRM(are bits of the decoded trimming/calibration code which can be 0 or 1 depending on captured code) can be 45 ohms. However, the value of equal resistor, RSmay be different for different types of applications.

FIG. 3shows the control circuit ofFIG. 2in another embodiment. In this example, a trim code may be inputted to one or more AND gates and the outputs of each of these AND gates may drive the switches S1, S2. . . SMdirectly instead of using a decoder116(ofFIG. 2). In some embodiment, gate drivers to amplify signals may be used at the output of the AND gates.

FIG. 4shows a sample one-shot pulse generation circuit200. The circuit200includes two parallel symmetrical paths, for D+ and D− inputs. the input IPcorresponds to D+ and the input INcorresponds to D−. A Disable input port may be included to enable and disable the generation of one-shot pulses. The inputs IPand INeach is coupled to the of a NOR gate202. The output of the NOR gate202is bifurcated into two paths, one path, through a NOT gate, is inputted to the first input of a XNOR gate206and the second path is inputted to the second input of the XNOR gate206. The second path includes one or more RC (resistor-capacitor) stages204. Each of the RC stages204includes or preceded by a NOT gate. The number of RC stages204or the values of RC components in the RC stages204determines the pulse width of the output one shot pulses. One shot pulses are generated at the rising and falling edges of the input pulse IP/IN. Therefore, for each input pulse, there will be two one shot pulses. To keep the one-shot pulse symmetrical during the rising and falling edges of the single ended signal, one-shot signal is generated based both on the positive and negative signals (e.g., D+ and D−). An AND (not shown) or OR gate208can be used to pick either the narrower or wider one-shot signal. The one-shot pulse generation circuit200described here provides a better tolerance to process related variances.

FIG. 5depicts a sample circuit122to describe the concept implemented through the embodiments described herein. The circuit122is a simplified representation of Rs ofFIG. 1. In the USB examples, in one example, when I2C setting is OFF, the required rise/fall time can be between 8-15 ns. When I2C setting is ON, the required rise/fall time can be between 4-10 ns. To cater to both these settings, the rise/fall time of I2C ON settings should be increased to close to 8-15 ns. The rise/fall times can be increased by increasing the output impedance (e.g., the impedance of the terminating stage108). However, doing so would make the USB repeater100noncompliant to the USB standards what requires an output impedance of 45 ohms. In one possible solution, a switchable capacitor may be included on-chip. However, such solutions have a big area penalty because capacitors take relatively more space on the chip. In one conventional method, the pre-driver (now shown) in the USB repeater is slowed down by introducing RC time constant in between the driver and pre-driver. However, this method requires a relatively larger die area on the silicon and consumes more power, yet the method may not provide highly accurate results. The embodiments described herein saves silicon area and power compared to conventional methods.FIG. 5shows a rising part of an input signal pulse120. The circuit122includes two resistors coupled in parallel. In this examples, each of the two resistors are equal value and each has a value that is double than the required output impedance (e.g., 45 ohms). One of the two resistors are coupled with a switch124that is controllable by the control signal CTRL. A capacitor CL is coupled at the output. An output pulse126is illustrated to show the voltage rise VPINat PIN. When the switch closed, the total impedance is R0(which can be 45 ohms in this example) and the curve128is resulted. However, the slew rate of the curve128needs to be reduced without making the USB repeater100out of compliance. If the switch124is opened for a brief period when the input pulse start to rise, the impedance seen at PINwill be 2R0. This increased impedance will cause the rise of the pulse at the output to slow to result in the curve130. The switch124may be opened for a brief duration of time through the control signal CTRL that is generated by a one-shot circuit as described above.

FIG. 6illustrates an input pulse VIN, one-shot pulses and the output pulse showing various rise/fall curves. The curve160is a rising curve and the curve166is a falling curve if some or all switches S1, S2. . . SMare closed (through the trim code or the control signal CTRL) such that the overall impedance of the termination stage108is R0(e.g., 45 ohms in the USB example). The curve160and166need to be slowed during a brief period of time as defined by the pulse widths TWP, TWNof the one-shot pulses. The pulse widths TWP, TWNcan be equal or different and in some examples, the widths are narrow enough so that the one-shot pulses disappear before a reflection arrives from the output. The pulse widths can also be predetermined through a test or calibration process by altering the one-shot pulse generation circuit114.

As pointed out by the arrow152, the one-shot pulse is generated when the VINpulse rises. Similarly, as pointed out by the arrow156, another one-shot pulse is generated at the falling edge of the VINpulse. During the period TWP, the one-shot signal input to the circuit that generates the control signal CTRL based on the trim code (seeFIGS. 2, 3) turns off one or more switches S1, S2. . . SMthus causing to increase the overall impedance during the period TWP. The increased impedance during the time TWPcauses the output voltage rise slowly (e.g., the curve162). As pointed out by the arrow154, at the end of the one-shot pulse (e.g., after the time TWP), the one or more switches that were opened are now closed and the output voltage has started to rise rapidly to follow the curve164. Similarly, as pointed by the arrow156, at the falling edge of the input pulse, the second one-shot pulse is generated. The second one-shot pulse has the width of TWN. During this time TWN, one or more switches S1, S2. . . SMare opened to cause an increased impedance. The increased impedance during the period TWN, cause the output pulse to follow the curve168, which shows a slower fall than the curve166. After the period TWN, the one or more switches S1, S2. . . SMthat were opened to increase the impedance closes again, thus reducing the impedance of the termination stage108. The reduced impedance cause the output signal to fall comparatively rapidly to follow the curve170. The trim code may be changed, for example, to achieve a different slew rate.

As shown, the switch over of the impedances during the rise and fall time of the input signal pulse may cause a non-smooth curve (e.g., the curve162+ the curve164). However, the curves172and174are the curves seen by the output because parasitic components creates a filter that naturally smooths out the bump between the curve162and the curve164. The embodiments described herein can be used with any type of Tx driver that is required to show a certain output impedance for slew rate control purposes.

As stated above, even though the embodiments herein are described using a USB application, these embodiments can be employed in application where a slew rate needs to be controlled by temporarily changing the output impedance. The slew rate can be increased or decreased using the embodiments described using by using an appropriate trim code. In some other examples, a feedback loop300as shown inFIG. 7may be employed to achieve a desired predetermined slew rate. From the output of a circuit, a slew rate measurement module302may take samples at predetermined intervals (e.g., 1-2 ns) to determine the slew rate. A pulse width adjustment module304compares the measure slew rate with the prestored desired slew rate that may be stored in a buffer or may be inputted to the pulse width adjustment module304, and generates a pulse width control signal to either increase the pulse width of the one shot pulse if the measured slew rate is faster than the prestored slew rate or decrease the pulse width of the one shot pulse if the measured slew rate is slower than the prestored slew rate by changing the number of the RC stages204(FIG. 4). In this example, the RC stages204may be bypassed using bypass switches (not shown) coupled in parallel. The bypass switches are controllable by the pulse width control signal.

The computer-useable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of non-transitory computer-useable and computer-readable storage media include a semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), and a digital video disk (DVD).

Alternatively, embodiments of the invention may be implemented entirely in hardware or in an implementation containing both hardware and software elements. In embodiments that use software, the software may include but is not limited to firmware, resident software, microcode, etc.