Logic cell with improved multiplexer, barrel shifter, and crossbarring efficiency

Logic circuits that provide improved efficiency are described. In one general embodiment, this is accomplished by feeding outputs of LEs in the logic circuit to multiplexers that receive their select signals from input terminals of the LEs in the logic circuit. In one embodiment, each of the LEs provides one output signal. The first LE in the logic circuit provides an output signal to one multiplexer, while each of the remaining LEs in the logic circuit provides an output signal to two multiplexers. In another embodiment, each of the LEs provides two output signals. The first LE in the logic circuit provides two output signals to one multiplexer, while each of the remaining LEs in the logic circuit provides two output signals to four multiplexers.

BACKGROUND OF THE INVENTION

Programmable logic devices (“PLDs”) (also sometimes referred to as complex PLDs (“CPLDs”), programmable array logic (“PALs”), programmable logic arrays (“PLAs”), field PLAs (“FPLAs”), erasable PLDs (“EPLDs”), electrically erasable PLDs (“EEPLDs”), logic cell arrays (“LCAs”), field programmable gate arrays (“FPGAs”), or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits. However, it is possible to provide an ASIC that has a portion or portions that are programmable. Thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.

PLDs have configuration elements that may be programmed or reprogrammed. Configuration elements may be realized as random access memory (“RAM”) bits, flip-flops, electronically erasable programmable read-only memory (“EEPROM”) cells, or other memory elements. Placing new data into the configuration elements programs or reprograms the PLD's logic functions and associated routing pathways. Configuration elements that are field programmable are often implemented as RAM cells (sometimes referred to a “configuration RAM” (“CRAM”)). However, many types of configurable elements may be used including static or dynamic RAM (“SRAM” or “DRAM”), electrically erasable read-only memory (“EEROM”), flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. For purposes herein, the generic term “configuration element” will be used to refer to any programmable element that may be configured to determine functions implemented by other PLD elements.

PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks” (“CLBs”)). Typically, the basic functional block of a LAB is a logic element (“LE”) that is capable of performing logic functions on a number of input variables. LEs, which are sometimes referred to by other names, e.g., “logic cells”, may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. PLDs typically combine together large numbers of such LEs through an array of programmable interconnects to facilitate implementation of complex logic functions. LABs (comprising multiple LEs) may be connected to horizontal and vertical conductors that may or may not extend the length of the PLD.

A LE is sometimes used to perform a multiplexing function on its data input variables. In many cases, the LUT within a LE performs the multiplexing function. The number of data input variables on which multiplexing may be performed is determined by the number of input terminals of the LUT. The sum of the number of data input variables to be multiplexed and the number of select signals necessary for selecting from among the data input variables must be less than or equal to the number of input terminals of the LUT. There are a number of known ways of increasing the number of data input variables that are multiplexed. In one method, LEs are coupled in series. In other words, the outputs of a first stage of LEs are fed into a second stage of LEs. More specifically, the outputs of LUTs in the first stage of LEs are fed into the LUTs in the second stage of LEs, where both the first stage LUTs and second stage LUTs perform a multiplexing function on their respective data input variables. In another method, the outputs of multiple LEs (or LUTs therein) which perform a multiplexing function on their data input variables are fed into hardwired multiplexer(s).

Another function performed by LEs is barrel shifting. Those skilled in the art know that barrel shifting is the process of shifting data input signals by a number of bits depending on select signals that determine the extent of the shift. Those skilled in the art also know that there are generally two types of barrel shifting. In one type of barrel shifting, N data bits (where N is an integer) are shifted down by m bits and the top m bits (where m is an integer less than or equal to N) are all replaced by binary low signals, i.e., zeros, or by binary high signals, i.e., ones. For example, data input signals on input terminals 1 to 16, may be shifted by 5 bits such that input data “abcdefghijklmnop” is barrel shifted and “00000abcdefghijk” is output. In another type of barrel shifting (sometimes referred to as rotating barrel shifting), the shifted out data is placed at the top of the data stream. For example in a rotating barrel shifting process, a 5 bit shift of “abcdefghijklmnop” results in “lmnopabcdefghijk”.

Yet another function performed by LEs is crossbarring of input data. Crossbarring is a more general case of barrel shifting. In barrel shifting, both the input data and the select signals are the same. On the other hand, in the case of crossbarring, the input data are the same, but the select signals are different. In other words, the same input data are selected using different sets of select signals as a result of which different subsets of input data are selected.

Some known methods for implementing one or more of multiplexers, barrel shifters, and crossbars suffer from inefficiencies in the number of LEs required and/or the number of levels of LEs required to perform the desired function. The number of LEs required to perform the function is at times referred to as the LE density. The number of levels of LEs required to perform the function is at times referred to as the depth of the logic circuit. The depth of the logic circuit affects the speed with which the logic circuit performs its intended functions. Generally, all else being equal, logic circuits with lower depth perform functions faster than those with higher depth. As used herein, improved logic circuit efficiency refers to improved density (i.e., lower density) and/or improved depth (i.e., lower depth).

The present invention is directed to improving the efficiency of logic circuits for implementing one or more of multiplexers, barrel shifters, and crossbars, and to improve the consistency of delay through the multiplexing structure of the logic circuit with minimum impact on the routing algorithms of the PLD of which the logic circuit is a part.

SUMMARY OF THE INVENTION

In one aspect, an embodiment of the present invention provides a logic circuit that provides more efficient multiplexing and barrel shifting than a prior art logic circuit. In one general embodiment, this is accomplished by feeding outputs of LEs in the logic circuit to multiplexers that receive their select signals from input terminals of the LEs in the logic circuit. In one embodiment, each of the LEs provides one output signal. The first LE in the logic circuit provides an output signal to one multiplexer, while each of the remaining LEs in the logic circuit provides an output signal to two multiplexers. In one embodiment, each of the LEs is an eight input LE that includes a six input LUT that functions as a 4:1 multiplexer, and each of the multiplexers is a 2:1 multiplexer. Use of LUTs that can function as 4:1 multiplexers allows for achieving the intended multiplexing function with lower depth than would be required when using LUTs that can function only as multiplexers smaller than 4:1 multiplexers. In another embodiment, each of the LEs provides two output signals. The first LE in the logic circuit provides two output signals to one multiplexer, while each of the remaining LEs in the logic circuit provides two output signals to four multiplexers. In one embodiment, each of the LEs is an eight input LE that includes two four input LUTs each of which acts as a 2:1 multiplexer, and each of the multiplexers is a 2:1 multiplexer.

In another aspect, an embodiment of the present invention provides a logic circuit that is particularly efficient in crossbarring and barrel shifting data input signals. In this embodiment, the logic circuit includes a plurality of LEs, where each of the LEs uses a shared LUT mask (SLM) and multiplexes the data input signals using two different sets of select signals. In this embodiment, the logic circuit also includes a plurality of multiplexers. Each of these multiplexers receives output signals from two of the LUTs and multiplexes the output signals. A first set of the multiplexers is coupled to a first select signal line from which each of the multiplexers in the first set receives a first select signal. A second set of the multiplexers is coupled to a second select signal line from which each of the multiplexers in the second set receives a second select signal. In one embodiment, each of the LEs is an eight input LE and includes a 6-input LUT. In one embodiment, each of the 6-input LUTs provides two separate 4:1 multiplexing results. In one embodiment, the first and second select signal lines are LAB-wide select signal lines. In other words, all the logic circuits in a LAB use the same select signal lines.

DETAILED DESCRIPTION OF THE INVENTION

The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of particular applications and their requirements. Various modifications to the exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

FIG. 1is a block diagram of one embodiment of the logic circuit of the present invention. InFIG. 1, logic circuit100includes logic blocks190and191and multiplexer170. Logic block190includes LEs110,120,130, and140, and multiplexers150,155, and160. LEs110,120,130, and140receive signals on LE input terminals111,121,131, and141, respectively. With the following exception, logic block191is identical to logic block190. Therefore, details of logic block191are not shown in order to avoid unduly complicatingFIG. 1. In logic block191, the LE (not shown) that corresponds to LE140in logic block190does not include an LE input terminal coupled to the select terminal of multiplexer170. An output terminal of each of logic blocks190and191is coupled to multiplexer170. In one embodiment, each of LEs110,120,130, and140includes eight LE input terminals. Also, in one embodiment, each of multiplexers150,155,160, and170is a 2:1 multiplexer.

In one embodiment each of LEs110,120,130, and140includes a 6-input LUT that is fracturable. In other words, each 6-input LUT includes smaller LUTs. In one embodiment, each 6-input LUT includes two 5-input LUTs. Each of the 5-input LUTs in turn includes two 4-input LUTs. InFIG. 1, two of the 4-input LUTs included in LE110are represented by reference numbers110-1and110-2. Similarly, two of the 4-input LUTs included in LE120are represented by reference numbers120-1and120-2, two of the 4-input LUTs included in LE130are represented by reference numbers130-1and130-2, and two of the 4-input LUTs includes in LE140are represented by reference numbers140-1and140-2. A fracturable LUT is described in greater detail in U.S. patent application Ser. No. 10/364,310, which was filed on Feb. 10, 2003, is entitled “Fracturable Lookup Table And Logic Element”, and is incorporated herein by reference in its entirety.

In one embodiment, when each of LEs110,120,130, and140includes a 6-input LUT, each of LEs110,120,130, and140functions as a 4:1 multiplexer using the 6-input LUT therein. Thus, each of LEs110,120,130, and140outputs the result of 4:1 multiplexing of the input data signals that it receives on input terminals111,121,131, and141, respectively.

When each of LEs110,120,130, and140functions as one 4:1 multiplexer, for each of LEs110,120,130, and140, four input terminals receive data input signals to be multiplexed, while two other input terminals receive select signals for selecting one of the four data input signals. The other remaining two input terminals may receive other signals. In the embodiment shown inFIG. 1, one of the remaining input terminals receives a select signal for a 2:1 multiplexer. As shown inFIG. 1, each of multiplexers150,155,160, and170receives a select signal from an input terminal of LEs110,120,130, and140, respectively. In one embodiment, each of the select terminals of multiplexers150,155,160, and170is hardwired to an input terminal of LEs110,120,130, and140, respectively.

As noted above, in one embodiment, each of each of LEs110,120,130, and140functions as a 4:1 multiplexer. Multiplexer150receives input data signals from LEs10and120and outputs one signal in response. Thus, multiplexer150in conjunction with LEs110and120acts as an 8:1 multiplexer and provides the result of an 8:1 multiplexing of the data input signals received at input terminals111and121of LEs110and120. Multiplexer155receives input data signals from LEs130and140and outputs one signal in response. Thus, multiplexer155in conjunction with LEs130and140acts as an 8:1 multiplexer and provides the result of an 8:1 multiplexing of the data input signals received at input terminals131and141of LEs130and140. Multiplexer160receives input data signals from multiplexers150and155. Thus, multiplexer160in conjunction with LEs110,120,130, and140and multiplexers150and155acts as a 16:1 multiplexer and provides the result of a 16:1 multiplexing of the data input signals received at input terminals111,121,131, and141of LEs110,120,130, and140. Multiplexer170receives input data signals from multiplexer160and another 16:1 multiplexer (not shown) in logic block191. This other 16:1 multiplexer is coupled to respective 2:1 multiplexers and LEs in a manner similar to the coupling of multiplexer160to multiplexers150and155and LEs110,120,130, and140. As multiplexer170receives two 16:1 multiplexing results and provides the multiplexing result thereof, it provides a 32:1 multiplexing result. The 32:1 multiplexing result is the result of 32:1 multiplexing of the input data signals received at input terminals111,121,131, and141of LEs110,120,130, and140in logic block190and at input terminals of another set of four LEs, like LEs110,120,130, and140, included in logic block191.

As explained above, logic circuit100provides a 32:1 multiplexing result. With additional LEs and multiplexers, logic circuit100may function as a larger multiplexer, e.g., as a 64:1 or 128:1 multiplexer. For example to obtain a 64:1 multiplexer, the output of multiplexer170and that of another similarly situated multiplexer (not shown) that provides a 32:1 output would be provided to a 2:1 multiplexer (not shown) which in turn would output a 64:1 multiplexing result.

In the embodiment shown inFIG. 1, each of LEs110,120,130, and140provides a 4:1 multiplexing result. In another embodiment, the LEs may provide an N:1 multiplexing result, where N is an integer equal to or greater than 2. In such an embodiment, the outputs of LEs and multiplexers would provide a correspondingly different multiplexing result.

Logic circuit100provides four 8:1 multiplexing results, two 16:1 multiplexing results, and one 32:1 multiplexing results in one level of logic, i.e., by having the signals go through only one level of LEs. It is to be noted that logic circuit100provides these multiplexing capabilities without using general routing other than the normal routing for LE inputs. This is an improvement over other circuits that either use additional routing or have greater depth. Furthermore, in logic circuit100, there is one 2:1 multiplexer per each LE. As such, logic circuit100is more efficient, in terms of density, than similar circuits that use a larger number of hardwired multiplexers per LE.

FIG. 2is a block diagram of another embodiment of the logic circuit of the present invention. InFIG. 2, logic circuit200includes LEs210,220,230, and240and multiplexers215,216,225,226,235,236,245, and246. Each of LEs210,220,230, and240is an eight input LE. LEs210,220,230, and240receive signals on LE input terminals211,221,231, and241, respectively. LE input terminals211include LE input terminals211-1and211-2. LE input terminals221include LE input terminals221-1and221-2. LE input terminals231include LE input terminals231-1and231-2. LE input terminals241include LE input terminals241-1and241-2. There are two 2:1 multiplexers associated with each of LEs210,220,230, and240. LE210is coupled to the two 2:1 multiplexers associated therewith, i.e., multiplexers215and216. Each of LEs220,230, and240is coupled to four 2:1 multiplexers.

In one embodiment each of LEs210,220,230, and240includes a 6-input LUT that is fracturable. In one embodiment, each 6-input LUT includes two 5-input LUTs, each of which in turn includes two 4-input LUTs. InFIG. 2, two of the 4-input LUTs included in LE210are represented by reference numbers210-1and210-2. Similarly, two of the 4-input LUTs included in LE220are represented by reference numbers220-1and220-2, two of the 4-input LUTs included in LE230are represented by reference numbers230-1and230-2, and two of the 4-input LUTs includes in LE240are represented by reference numbers240-1and240-2.

Each 6-input LUT can function as a 4:1 multiplexer. Similarly, each 4-input LUT can function as a 2:1 multiplexer. In logic circuit200, each of LEs210,220,230, and240can operate as one 4:1 multiplexer using the 6-input LUT or as two 2:1 multiplexers using two of the 4-input LUTs that are a part of the 6-input LUT.

As noted above, in one embodiment, each of LEs210,220,230, and240outputs two 2:1 multiplexing results. The two output signals from LE210are provided to the two 2:1 multiplexers215and216. Multiplexers215and216receive their other input data signals from LE220. A select input of multiplexer215is driven by one of inputs of LE211-1and a select input of multiplexer216is driven by one of inputs211-2. The two output signals from LE220are also provided to the two 2:1 multiplexers225and226Multiplexers225and226receive their other input data signals from LE230. A select input of multiplexer225is driven by one of inputs221-1and a select input of multiplexer226is driven by one of inputs221-2. The two output signals from LE230are also provided to the two 2:1 multiplexers235and236. Multiplexers235and236receive their other input data signals from LE240. A select input of multiplexer235is driven by one of inputs231-1and a select input of multiplexer236is driven by one of inputs LE231-2. The two output signals from LE240are also provided to the two 2:1 multiplexers245and246. Multiplexers245and246receive their other input data signals from an LE (not shown) below LE240. A select input of multiplexer245is driven one of inputs241-1and a select input of multiplexer246is driven by one of inputs241-2. In one embodiment, the select inputs of multiplexers215,216,225,226,235,236,245and246are hardwired to the respective LE input driving each select input.

In one embodiment, when each of LEs210,220,230, and240provides two 2:1 multiplexing results, each of multiplexers215,216,225,226,235,236,245, and246outputs a 4:1 multiplexing result. In order to obtain 8:1 multiplexing results, the eight output signals from multiplexers215,216,225,226,235,236,245, and246are fed into a set of four 2:1 multiplexers. Alternatively, they are fed into two LEs similar to LE220, for example, where each LE is configured as two 2:1 multiplexers. In order to obtain 16:1 multiplexing results, the eight output signals from multiplexers215,216,225,226,235,236,245, and246are fed into two LEs similar to LE220, for example, which is configured as a 4:1 multiplexer.

As noted above, each of LEs210,220,230, and240can operate as a 4:1 multiplexer using a 6-input LUT therein. When each of LEs210,220,230, and240provides a 4:1 multiplexing result, each of multiplexers215,216,225,226,235,236,245, and246outputs a 8:1 multiplexing result. Since a traditional N:1 multiplexer does not share data signals not all multiplexer outputs can generate 8:1 multiplexing at the same time. Either multiplexer215or216can use LEs210and220to generate an 8:1 multiplexer. Either multiplexer225or226can use LEs220and230to generate an 8:1 multiplexer. Either multiplexer235or236can use LEs230and240to generate an 8:1 multiplexer. Either multiplexer245or246can use LEs240and the next LE not shown to generate an 8:1 multiplexer. In order to obtain 16:1 multiplexing results, the two output signals of independent 8:1 multiplexers are fed into a 2:1 multiplexer. For example, the outputs of multiplexers215and235or multiplexers216and236are fed into a 2:1 multiplexer. Alternatively, they are fed into an LE similar to LE320, for example, where the LE is configured as a 2:1 multiplexer. In order to obtain 32:1 multiplexing results, the four output signals from either multiplexers215,225,235and245or multiplexers216,226,236and246, are fed into a single LEs similar to LE220, for example, which is configured as a 4:1 multiplexer.

It is to be noted that when operating as a 4:1 multiplexer, logic circuit200also acts as a four bit barrel shifter. When implementing a shift by 4 barrel shifter, each LE210,220,230and240is configured as two 2:1 multiplexers and all eight of the outputs of multiplexers215,216,225,226,235,236,245and246are used. Similarly, when operating as a 8:1 multiplexer, logic circuit200also acts as an eight bit barrel shifter. When implementing a shift by 8 barrel shifter in logic circuit200, each LE210,220,230and240is configured as a 4:1 multiplexer and either 2:1 multiplexers215,225,235and245or 2:1 multiplexers216,225,235and245are used. To implement a shift by 16 barrel shifter, each LE210,220,230and240is configured as two 2:1 multiplexers and all eight 2:1 multiplexers215,216,225,226,235,236,245and246can, for example, drive two LEs similar to LE220where each LE is configured as a 4:1 multiplexer. In a similar manner, logic circuit200, with additional LEs and multiplexers arranged as those shown inFIG. 2, may provide thirty-two, or sixty-four bit barrel shifting. It is to be noted that logic circuit200provides improved efficiency, in terms of density, over prior art circuits for barrel shifting.

Similarly, logic circuit200provides for crossbarring by four, eight, and sixteen bits. In particular for four bit cross-barring, each LE210,220,230and240is configured as a 2:1 multiplexer and all eight of the outputs of multiplexers215,216,225,226,235,236,245and246are used. When implementing 8 bit cross-barring, each LE210,220,230and240is configured as a 4:1 multiplexer and either 2:1 multiplexers215,225,235and245or 2:1 multiplexers216,225,235and245are used. When implementing 16 bit cross-barring each LE210,220,230and240is configured as a 4:1 multiplexer and either 2:1 multiplexers215,225,235and245or 2:1 multiplexers216,225,235and245, can, for example, drive two LEs similar to LE220where each LE is configured as a 4:1 multiplexer. In a similar manner, logic circuit200, with additional LEs and multiplexers arranged as those shown inFIG. 2can also implement 32 bit and 64 bit cross-barring.

FIG. 3is a block diagram of yet another embodiment of the logic circuit of the present invention. InFIG. 3, logic circuit300includes LEs310,320,330, and340and multiplexers315,316,325,326,335,336,345, and346.

In one embodiment, each of LEs310,320,330, and340is an eight input LE. LEs310,320,330, and340receive signals on LE input terminals311,321,331, and341, respectively. In one embodiment each of LEs310,320,330, and340includes a 6-input LUT that is fracturable. In one embodiment, each 6-input LUT includes two 5-input LUTs, each of which in turn includes two 4-input LUTs. InFIG. 3, two of the 4-input LUTs included in LE310are represented by reference numbers310-1and310-2. Similarly, two of the 4-input LUTs included in LE320are represented by reference numbers320-1and320-2, two of the 4-input LUTs included in LE330are represented by reference numbers330-1and330-2, and two of the 4-input LUTs included in LE340are represented by reference numbers340-1and340-2. Also in one embodiment, each of multiplexers315,316,325,326,335,336,345, and346is a 2:1 multiplexer.

There are two 2:1 multiplexers associated with each of LEs310,320,330, and340. LE316is coupled to the two 2:1 multiplexers associated therewith, i.e., multiplexers315and316. Each of LEs320,330, and340is coupled to four 2:1 multiplexers.

In one embodiment, each of LEs310,320,330, and340outputs two multiplexing results. The two output signals from LE310are provided to the two 2:1 multiplexers315and316. Multiplexers315and316receive their other input data signals from LE320. The two output signals from LE320are also provided to the two 2:1 multiplexers325and326. Multiplexers325and326receive their other input data signals from LE330. The two output signals from LE330are also provided to the two 2:1 multiplexers335and336. Multiplexers335and336receive their other input data signals from LE340. The two output signals from LE340are also provided to the two 2:1 multiplexers345and346. Multiplexers345and346receive their other input data signals from an LE (not shown) below LE340. Multiplexers315,325,335, and345receive the select signal S1as their select signal, while multiplexers316,326,336, and346receive the select signal S2as their select signal. In one embodiment, select signals S1and S2are LAB-wide select signals. In other words, all the logic circuits within a LAB receive the same select signals S1and S2.

As noted above, in logic circuit300, multiplexers315,325,335, and345receive select signal S1, while multiplexers316,326,336, and346receive select signal S2. It is to be noted that select signals S1and S2are not received from LE input terminals. This constitutes one of the main differences between logic circuits200and300. As the select signals for the multiplexers315,316,325,326,335,336,345, and346are not received from the LE input terminals, each LE in logic circuit300has two more LE input terminals available for receiving an independent signals than its counterpart LE in logic circuit200.

As LEs in logic circuit300have a greater number of LE input terminals available than their counterparts in logic circuit200, they provide greater flexibility than their counterparts in logic circuit200. In logic circuit300, as each LE has eight input terminals, it can provide two different 4:1 multiplexing results by using four of its input terminals for receiving data signals and four of the remaining input terminals to receive two different sets of select signals for selecting from the four data signals. With one set of two select signals, the LE310provides a first 4:1 multiplexing result, while with the other set of two select signals, it provides a second, separate 4:1 multiplexing result. As noted above, each of LEs310,320,330, and340includes a 6-input fracturable LUT that includes four 4-input LUTs. In one embodiment, LEs of logic circuit300use a SLM to provide two separate 4:1 multiplexing results. A SLM is described in greater detail in U.S. patent application Ser. No. 10/351,026, which was filed on Jan. 24, 2003, is entitled “Logic Circuitry With Shared Lookup Table”, and is incorporated herein by reference in its entirety.

When each of LEs310,320,330, and340provides 4:1 multiplexing results, each of multiplexers315,316,325,326,335,336,345, and346outputs a 8:1 multiplexing result. Since a traditional N:1 multiplexer does not share data signals not all multiplexer outputs can generate 8:1 multiplexing at the same time. Either multiplexer315or316can use LEs310and320to generate an 8:1 multiplexer. Either multiplexer325or326can use LEs320and330to generate an 8:1 multiplexer. Either multiplexer335or336can use LEs330and340to generate an 8:1 multiplexer. Either multiplexer345or346can use LEs340and the next LE not shown to generate an 8:1 multiplexer. In order to obtain 16:1 multiplexing results, the two output signals of independent 8:1 multiplexers are fed into a 2:1 multiplexer. For example multiplexers315and335or multiplexers316and336are fed into a 2:1 multiplexer. Alternatively, they are fed into an LE similar to LE320, for example, where the LE is configured as a 2:1 multiplexer. In order to obtain 32:1 multiplexing results, the four output signals from either multiplexers315,325,335, and345or316,326,336, and346are fed into two LEs similar to LE320, for example, where each LE includes a 4:1 multiplexer.

It is also to be noted that logic circuit300, with additional LEs and multiplexers arranged as those shown inFIG. 3, may provide barrel shifting. To implement a 4 bit barrel shifter, each LE310,320,330and340is configured as two 2:1 multiplexers and all eight of the outputs of multiplexers315,316,325,326,335,336,345and346are used. Similarly, when operating as a 8:1 multiplexer, logic circuit300also acts as an eight bit barrel shifter. When implementing a shift by 8 barrel shifter in logic circuit300, each LE310,320,330and340is configured as a 4:1 multiplexer and either 2:1 multiplexers315,325,335and345or 2:1 multiplexers316,325,335and345are used. To implement a shift by 16 barrel shifter, each LE310,320,330and340is configured as two 2:1 multiplexers and all eight of the outputs of multiplexers315,316,325,326,335,336,345and346, can, for example, drive two LEs similar to LE320where each LE is configured as a 4:1 multiplexer. In a similar manner, logic circuit300, with additional LEs and multiplexers arranged as those shown inFIG. 3, may provide thirty-two, or sixty-four bit barrel shifting.

Similarly, logic circuit300provides for cross-barring. Because each LE310,320,330or340can implement two 6-LUTs with 4 shared inputs and 2 independent inputs each, 4×2 cross-barring can be implements in each LE310,320,330and340. To implement 8×2 cross-barring LEs310and320are each configured as a 4×2 crossbar and outputs are taken from multiplexers315and316. A second 8×2 crossbar can also be implemented by configuring LEs330and340as 4×2 crossbars and taking outputs from multiplexers335and336. To implement 16×2 cross-barring two 8×2 cross-bars are implemented as above, each LE310,320,330and340is configured as a 4×2 crossbar and outputs can be taken from multiplexers315,316,335and336. The outputs of multiplexers315and335are connected to a 2:1 multiplexer and the outputs of multiplexers316and336are connected to a 2:1 multiplexer. The two 2:1 multiplexers can be implemented in a LE similar to LE310. In a similar manner, logic circuit300, with additional LEs and multiplexers arranged as those shown inFIG. 3, may provide thirty-two, or sixty-four bit cross-barring.

In another embodiment, logic circuit300can function in a manner identical to that described above for logic circuit200with the following exception. In such an embodiment of logic circuit300, the select signals for the multiplexers315,316,325,326,335,336,345, and346are received from the select signal lines instead of the LE input terminals of LEs310,320,330, and340.

FIG. 4illustrates an exemplary data processing system including an exemplary PLD in which logic circuits in accordance with the present invention might be implemented.

FIG. 4illustrates, by way of example, a PLD410in a data processing system400. As one example, logic circuits of this invention may be implemented in LEs of PLDs such as PLD410. PLD410includes a plurality of LABs such as LAB411(only one LAB is shown to avoid overcomplicating the drawing). LAB411includes one or more logic circuits, such as logic circuit412(only one logic circuit is shown to avoid overcomplicating the drawing). Logic circuit412may be one of logic circuits100,200, or300shown inFIG. 1,2, or3, respectively. In one embodiment, logic circuit412and LAB411are on the same die/chip as PLD410. Data processing system400may include one or more of the following components: a processor440; memory450; input/output (I/O) circuitry420; and peripheral devices430. These components are coupled together by a system bus465and are populated on a circuit board460which is contained in an end-user system470. A data processing system such as system400may include a single end-user system such as end-user system470or may include a plurality of systems working together as a data processing system.

System400can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, DSP, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD410can be used to perform a variety of different logic functions. For example, PLD410can be configured as a processor or controller that works in cooperation with processor440(or, in alternative embodiments, a PLD might itself act as the sole system processor). PLD410may also be used as an arbiter for arbitrating access to shared resources in system400. In yet another example, PLD410can be configured as an interface between processor440and one of the other components in system400. It should be noted that system400is only exemplary.

In one embodiment, system400is a digital system. As used herein a digital system is not intended to be limited to a purely digital system, but also encompasses hybrid systems that include both digital and analog subsystems.

While the present invention has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications and adaptations may be made based on the present disclosure, and are intended to be within the scope of the present invention. While the invention has been described in connection with what are presently considered to be the most practical and preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiment but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.