Fin-based laterally diffused structure having a gate with two adjacent metal layers and method for manufacturing the same

A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.

BACKGROUND

The present disclosure relates to radio frequency (RF) devices, and more specifically, to a FinFET structure with two adjacent metal layers in the gate structure. The metal layers may have different thicknesses and/or work functions.

Radio frequency (RF) devices employ laterally diffused metal-oxide semiconductors (LDMOS) devices. Transconductance (Gm) is the ratio of the change in current at the output terminal to the change in the voltage at the input terminal of an active device. Transconductance improvements in LDMOS devices will improve RF performance.

SUMMARY

An aspect of the disclosure is directed to a structure, comprising: a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin; and a gate structure over the channel region and the drain extension, the gate structure including: a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, wherein the first metal layer and the second metal layer have different thicknesses, and a contiguous gate conductor over the first metal layer and the second metal layer.

Another aspect of the disclosure includes a laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising: a first source/drain region and a second source/drain region in a semiconductor fin; a trench isolation between the first and second source/drain regions in the semiconductor fin; a first doping region about the first source/drain region, the first doping region defining a channel region in the semiconductor fin; a second doping region about the second source/drain region, the second doping region defining a drain extension in the semiconductor fin; and a gate structure over the channel region and the drain extension, the gate structure including: a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, wherein the first metal layer and the second metal layer have different thicknesses, and a contiguous gate conductor over the first metal layer and the second metal layer.

Another aspect of the disclosure relates to a method, comprising: forming a first doping region about a first source/drain region in a semiconductor fin, and a second doping region about a second source/drain region in the semiconductor fin, the first doping region defining a channel region in the semiconductor fin, the second doping region defining a drain extension in the semiconductor fin; and forming a gate dielectric layer over the channel region and the drain extension; forming a first metal layer adjacent a second metal layer over the gate dielectric layer wherein the first metal layer and the second metal layer have different thicknesses; and forming a contiguous gate conductor over the first metal layer and the second metal layer.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure provide a structure for use in, for example, a fin-type field effect transistor (FinFET). The structure may be used in laterally-diffused metal-oxide semiconductor (LDMOS) device having advantage relative to radio frequency (RF) applications. The structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET that includes the structure.

FIGS. 1-11are cross-sectional views of a method to form a structure100(FIGS. 8-11) according to various embodiments of the disclosure. For purposes of description, structure100may be implemented as a FinFET102(FIGS. 8-11) in the form of a LDMOS device104(FIGS. 8-11), but it is emphasized that it can also be applied in other types of MOS devices.

FIG. 1shows a cross-sectional view of forming a preliminary structure108, including forming a first doping region130about a first source/drain region110in a semiconductor fin116, and a second doping region132about a second source/drain region112in semiconductor fin116. Semiconductor fin116may be part of a semiconductor body114that includes semiconductor fin116over a (bulk) semiconductor substrate118. Semiconductor body114may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion or entire semiconductor substrate may be strained.

Semiconductor substrate118may include a dopant. In one embodiment, the dopant may include a p-type dopant, which may include but is not limited to: boron (B), indium (In) and gallium (Ga). P-type dopants are elements introduced to semiconductor to generate a free hole by “accepting” electron from semiconductor atom and “releasing” the hole at the same time. The dopant may be introduced to semiconductor substrate118in any now known or later developed fashion, e.g., in-situ doping during formation, or ion implanting. Usually in doping, a dopant, a dosage and an energy level are specified and/or a resulting doping level may be specified. A dosage may be specified in the number of atoms per square centimeter (cm2) and an energy level (specified in keV, kilo-electron-volts), resulting in a doping level (concentration in the substrate) of a number of atoms per cubic centimeter (cm3). The number of atoms is commonly specified in exponential notation, where a number like “3E15” means 3 times 10 to the 15th power, or a “3” followed by 15 zeroes (3,000,000,000,000,000). An example of doping is implanting with B (boron) with a dosage of between about 1E12 and 1E13 atoms/cm2, and an energy of about 40 to 80 keV to produce a dopant concentration of between 1E17 and 1E18 atoms/cm3.

Preliminary structure108includes first source/drain region110and second source/drain region112in semiconductor fin116. Source/drain regions110,112may be formed using any now known or later developed semiconductor fabrication technique. For example, source/drain regions110,112may be formed by mask-directed doping by ion implantation followed by an anneal to drive in the dopants. Source/drain regions110,112may be doped with an n-type dopant. N-type dopants may include but are not limited to: phosphorous (P), arsenic (As), or antimony (Sb). N-type is an element introduced to semiconductor to generate free electrons by “donating” electrons to the semiconductor.

Forming preliminary structure108may also include forming a trench isolation120between first and second source/drain regions110,112in semiconductor body114, i.e., where structure100is part of LDMOS device104. Trench isolation120may take any form of an isolating structure or material, but typically includes a shallow trench isolation (STI). Trench isolation120may be formed using any now known or later developed semiconductor fabrication technique. Generally, a trench122is etched into semiconductor fin116, and filled with an insulating material such as oxide, to isolate one region of semiconductor body114from an adjacent region of the body. Trench isolation120may be formed of any currently-known or later developed substance for providing electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPS G), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof.

Preliminary structure108formation also includes forming first doping region130about first source/drain region110. First doping region130may take the form of a p-type doped well, (hereafter “p-well”)130. The p-type dopant may be the same as semiconductor body114, but with a higher dopant concentration. P-well130may be formed using any now known or later developed semiconductor fabrication technique, e.g., mask-directed ion implantation prior to formation of first source/drain region110. Structure100also includes a second doping region132about second source/drain region112. Trench isolation120is within second doping region132. Second doping region132may be between second source/drain region112and trench isolation120, although this is not necessary in all cases. Second doping region132may take the form of an n-type doped well, or n-well (hereafter “n-well”)132. The n-type dopant may be the same as source/drain regions110,112, but with a lower dopant concentration. N-well132may be formed using any now known or later developed semiconductor fabrication technique, e.g., mask-directed ion implantation prior to formation of second source/drain region112. As understood in the field, a space between first source/drain region110and an edge136of p-well130defines a channel region138of the device; and a space between trench isolation120and edge140of n-well132defines a drain extension142. While edges136,140are shown as co-linear, that is not necessary in all instances.

FIGS. 2-3show cross-sectional views of forming a gate dielectric layer150over channel region138and drain extension142. Gate dielectric layer150may include may include gate dielectric including but not limited to: hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k material or any combination of these materials. Gate dielectric layer150may be formed using any now known or later developed semiconductor fabrication technique, e.g., deposition. “Depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. In one example, tetraethyl orthosilicate, Si(OC2H5)4(TEOS) based ALD may be used to form silicon oxide (SiO2).In one embodiment, as shown inFIG. 2, forming gate dielectric layer150includes forming the gate dielectric layer with a uniform thickness over channel region138and drain extension142. The uniform thickness may be thinner than conventionally used. In another embodiment, shown inFIG. 3, gate dielectric layer150is thicker over drain extension142than over channel region138. That is, gate dielectric layer150may have a first, thicker portion150A over drain extension142and a second, thinner portion150B over channel region138. A thinner gate dielectric layer over channel region138improve the gate control and hence improves transconductance and performance, and a thicker gate dielectric layer over drain extension142reduces hot carrier injection (HCI). HCI refers to a situation where an electron or a “hole” gains sufficient energy to overcome a barrier required to break an interfacial state. When charge carriers become trapped in gate dielectric layer150, it can change the switching characteristics of the device. The different thickness portions150A,150B may be formed using any now known or later developed technique. For example, both portions150A,150B may be deposited, then a mask (not shown) may be formed over thinner portion150B, and further depositing performed to create thicker portion150A. In the example shown, gate dielectric layer150may be deposited having the thickness of first, thicker portion150A, a mask152may then be formed over an area of first, thicker portion150A, and an etching carried out to form second, thinner portion150B. Etching generally refers to the removal of material from a substrate (or structures formed on the substrate), and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases, which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as STI trenches. Here, a RIE may be used to thin second portion150B.

FIGS. 4-7show cross-sectional views of forming a first metal layer160adjacent a second metal layer162over gate dielectric layer150.FIGS. 4 and 6show forming the layers over theFIG. 2embodiment with uniform thickness gate dielectric layer150, andFIGS. 5 and 7show forming the layers over theFIG. 3embodiment with gate dielectric layer portions150A,150B with different thicknesses. Metal layers160,162may have different work functions to improve the performance of the particular FinFET being formed. First metal layer160is over channel region138, and second metal layer162is over drain extension142. The work function is the minimum energy (usually measured in electron volts) needed to remove an electron from a solid to a point immediately outside the solid surface (or energy needed to move an electron from the Fermi energy level into vacuum). Here “immediately” means that the final electron position is far from the surface on the atomic scale but still close to the solid on the macroscopic scale. The magnitude of the work function is usually about a half of the ionization energy of a free atom of the metal. Work function metals for PFET or NFETs include, for example: aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and/or combinations thereof. In certain embodiments, metal layers160,162may have different thicknesses to create different work functions and improve transconductance in different areas of the device, e.g., channel region138and/or drain extension142. In this regard, forming first and second metal layers160,162also includes forming the metal layers to have non-coplanar upper surfaces164,166.

In certain embodiments, as shown inFIGS. 4 and 5, metal layers160,162may include the same material such as but not limited to titanium nitride. Here, the different, selective thicknesses alone can be used to tune the performance of the device. First and second metal layers160,162may be formed using any now known or later developed technique. For example, both metal layers160,162may be deposited, then a mask (not shown) may be formed over first, thinner metal layer160. Further depositing may be performed to create second, thicker metal layer162. In the example shown, metal layer160,162may be deposited having the thickness of first, thicker portion150A, a mask152may then be formed over an area of first, thicker portion150A, and an etching carried out to form second, thinner portion150B. The etching may include, for example, a wet etch.

In certain embodiments, as shown inFIGS. 6 and 7, metal layers160,162may include different materials with different work functions, such as but not limited to titanium nitride and tantalum nitride. Here, the different thicknesses and/or the different materials with different work functions provide different transconductances to allow tuning of the performance of the device. First and second metal layers160,162may be formed using any now known or later developed technique. For example, first metal layer160may be deposited. Subsequently, a mask (not shown) may be formed thereover and an appropriate etch performed to remove it from an area for second metal layer162, and then the mask may be removed. Second metal layer162may then be deposited. Subsequently, a mask (not shown) may be formed thereover and an appropriate etch performed to remove it from an area over first metal layer160, and then the mask may be removed. Regardless of how formed, first and second metal layers160,162are immediately adjacent each other, i.e., they contact one another with no intervening structure.

FIGS. 8-11show cross-sectional views of forming a contiguous gate conductor170over first metal layer160and second metal layer162, i.e., to complete a gate structure172. Gate conductor170may be any now known or later developed gate conductor material such as but not limited to copper. Gate conductor170may be formed using any know known or later developed technique, e.g., depositing, etching, and planarization.FIG. 8shows forming gate conductor170over theFIG. 4embodiment with uniform thickness gate dielectric layer150and same material metal layers160,162;FIG. 9shows forming gate conductor170over theFIG. 5embodiment with different thickness gate dielectric layer150and same material metal layers160,162;FIG. 10shows forming gate conductor170over theFIG. 6embodiment with uniform thickness gate dielectric layer150and different material metal layers160,162; andFIG. 11shows forming gate conductor170over theFIG. 7embodiment with different thickness gate dielectric layer150and different material metal layers160,162.

FIGS. 8-11also show various embodiments of structure100in a FinFET102(LDMOS device104). Structure100includes semiconductor fin116, first source/drain region110and second source/drain region112in semiconductor fin116. Structure100also includes first doping region130about first source/drain region110, defining channel region138in semiconductor fin116; and second doping region132about second source/drain region112, defining drain extension142in semiconductor fin116. Gate structure172is over channel region138and drain extension142. Gate structure172includes gate dielectric layer150; first metal layer160adjacent second metal layer162over gate dielectric layer150; and contiguous gate conductor170over first metal layer160and second metal layer162. First metal layer160is over channel region138, and second metal layer162is over drain extension142. First metal layer160and second metal layer162have different thicknesses. For example, first metal layer160is thinner than second metal layer162. InFIGS. 8 and 10, gate dielectric layer150has a uniform thickness over channel region138and drain extension142. In contrast, inFIGS. 9 and 11, gate dielectric layer150is thicker (first portion150A) over drain extension142than over channel region138(second portion150B), i.e., to improve transconductance and HCI. First and second metal layers160,162may have non-coplanar upper surfaces164,166(FIGS. 4-7). InFIGS. 8 and 9, first metal layer160and second metal layer162are the same material, e.g., titanium nitride. The different thicknesses create different work functions in each area. In contrast, inFIGS. 10 and 11, first metal layer160and second metal layer162have different materials with different work functions. Structure100may also include trench isolation120between first and second source/drain regions110,112in semiconductor fin116.

While embodiments of the disclosure have been disclosed with a particular arrangement of dopant types that create the various doping regions, i.e., for an NFET, it is apparent that the various structures may have the opposite doping types for an opposite type device, i.e., for PFET. That is, semiconductor body114may be doped with an n-type dopant, first doping region130may be an n-well, second doping region132may be a p-well, and third doping region140/charge trap section142may be doped with a p-type dopant.

Embodiments of the disclosure provide a structure100, FinFET102and LDMOS104with improved transconductance that finds advantage relative to RF applications. Embodiments of the disclosure can also act to customize threshold voltage (Vt). The metal layers may have different thicknesses and/or work functions that improve the transconductance, and/or customize threshold voltage. In one non-limiting example, first metal layer160may have a thickness of 15.6 Angstroms (Å), resulting in a saturation voltage (Vtsat) of 0.28 Volts (V), and second metal layer162may have a thickness of 38.9 A, resulting in Vtsat of 0.43V. A thinner gate dielectric layer over channel region138and a thinner gate dielectric layer over drain extension142may also be selectively used to improve transconductance and reduce HCI.