Techniques relating to oscillators

An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

BACKGROUND

The present invention relates to electronic circuits, and more particularly to techniques relating to oscillators.

FIG. 1illustrates a configuration of a prior art voltage-controlled oscillator (VCO)104. VCO104is part of a phase-locked loop (PLL) circuit. The PLL includes a PLL loop filter101, a voltage buffer102, a low pass filter (LPF)103, and VCO104. PLL loop filter101generates a control voltage VCL that is based on the difference between the phase and the frequency of a reference clock signal and the phase and the frequency of a feedback clock signal. Voltage buffer102buffers VCL to generate an oscillator supply voltage VOS.

A supply voltage VCC is filtered by LPF103to generate a filtered supply voltage VFL. The filtered supply voltage VFL is provided to a supply input of voltage buffer102. VCO104is a ring oscillator that includes two differential VCO cells105-106. VCO cells105-106are differential inverting delay circuits. The oscillator supply voltage VOS is provided to supply inputs of VCO cells105and106. VCO cell106generates a differential output signal OUT/OUTB.

FIG. 2is a schematic diagram of a prior art VCO cell that is used to implement VCO104. The VCO cell circuit structure shown inFIG. 2is in VCO cell105. The VCO cell circuit structure shown inFIG. 2is also in VCO cell106. VCO cell105/106includes p-channel metal oxide semiconductor field-effect transistors (MOSFETs)201-202and n-channel MOSFETs203-206. INP is the non-inverting (+) input of VCO cell105/106, and INN is the inverting (−) input of VCO cell105/106. OUTP is the non-inverting output of VCO cell105/106, and OUTN is the inverting output of VCO cell105/106. The inverting outputs of VCO cells105/106are represented by circles in VCO104. The oscillator supply voltage VOS is provided to the sources of transistors201-202.

FIG. 3is a graph that illustrates the frequency response and the gain of VCO104. The frequency response of VCO104refers to the frequency of differential output signal OUT/OUTB. The gain (KVCO) of VCO104refers to the change in frequency of OUT/OUTB versus the change in the control voltage VCL. VCO104provides a tuning range for OUT/OUTB from about 1-14 GHz as shown inFIG. 3. The gain of VCO104varies from about 7 GHz/volt to a maximum of about 12 GHz/volt over the tuning range of VCO104.

VCO104is very susceptible to generating jitter in output signals OUT and OUTB in response to supply voltage noise in VOS, particularly at high frequencies. Noise in VOS can, for example, be generated in response to noise in VFL or noise in VCL.

BRIEF SUMMARY

According to some embodiments, an oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

In other embodiments, a phase-locked loop circuit includes phase detection circuitry, a voltage buffer, and variable delay circuits. The phase detection circuitry generates a control voltage that varies based on changes in a phase difference between two clock signals. The voltage buffer generates a variable supply voltage that is based on the control voltage using current that is supplied from a supply source. The variable delay circuits are coupled together to form a ring oscillator. The variable supply voltage is provided to first and second transistors in each of the variable delay circuits. A constant supply voltage is provided to third and fourth transistors in each of the variable delay circuits. The ring oscillator generates a minimum frequency of oscillation in a periodic output signal using the constant supply voltage when the voltage buffer blocks current from the supply source through the first and the second transistors.

Various objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings.

DETAILED DESCRIPTION

FIG. 4illustrates an example of a phase-locked loop (PLL) circuit400, according to an embodiment of the present invention. PLL400includes phase frequency detector (PFD) circuit401, charge pump circuit402, loop filter circuit403, voltage buffer circuit404, low pass filter (LPF) circuit405, voltage-controlled oscillator (VCO) circuit408, frequency divider circuit409, voltage buffer410, and LPF411. VCO408includes VCO cells406and407that are coupled together to form a ring oscillator.

PLL400is typically fabricated on an integrated circuit. PLL400can, for example, be fabricated on an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a memory integrated circuit, a processor or controller integrated circuit, an analog integrated circuit, etc.

Phase-frequency detector (PFD)401compares the phase and the frequency of an input reference clock signal REFCLK to the phase and the frequency of a feedback clock signal FBCLK generated by frequency divider409. PFD401generates UP and DN (down) error signals that are indicative of the differences between the phases and the frequencies of the input reference clock signal REFCLK and the feedback clock signal FBCLK. The UP and DN error signals are transmitted to charge pump402. Charge pump402converts the UP and DN error signals into a control voltage VCL, and loop filter403filters the control voltage VCL. Loop filter403is a low pass filter that attenuates high frequency components of control voltage VCL.

Low pass filter (LPF)405filters a supply voltage VCC to generate a filtered supply voltage VLP. Supply voltage VLP is provided to a supply input of voltage buffer404and to a supply input of voltage buffer410.

The control voltage VCL is transmitted to a control input of voltage buffer404. Voltage buffer404buffers VCL to generate an oscillator supply voltage VOS. Oscillator supply voltage VOS is transmitted to first supply inputs of VCO cells406and407in voltage-controlled oscillator (VCO)408. Each of the VCO cells406and407is a differential variable delay circuit. The delays of VCO cells406-407vary based on changes in the oscillator supply voltage VOS.

Voltage buffer404can, for example, be a native n-channel MOSFET having a low threshold voltage near zero volts. In this example, VCL is provided to the gate of the n-channel MOSFET, VLP is provided to the drain of the n-channel MOSFET, and VOS is generated at the source of the n-channel MOSFET.

VCO408generates two differential output clock signals OUT1/OUT1B and OUT2/OUT2B. The first differential output clock signal OUT1/OUT1B is generated at the outputs of VCO cell407, and the second differential output clock signal OUT2/OUT2B is generated at the outputs of VCO cell406. Signals OUT2and OUT2B are 180 degrees out of phase from each other. Signals OUT1and OUT are also 180 degrees out of phase from each other. Signals OUT1and OUT2are offset in phase by 90 degrees from each other. Signals OUT1, OUT2, OUT1B, and OUT2B have relative phases of 0°, 90°, 180°, and 270°.

VCO408varies the frequency of its differential output clock signals OUT1/OUT1B and OUT2/OUT2B within a frequency range based on changes in the oscillator supply voltage VOS. VOS varies based on changes in the control voltage VCL.

Frequency divider circuit409divides the frequency of the OUT1/OUT1B clock signal from VCO408to generate the feedback clock signal FBCLK. Frequency divider409can be, for example, a divide-by-N counter circuit. Frequency divider409allows VCO408to generate output clock signals having frequencies greater than the frequency of the input reference clock signal REFCLK.

PLL400adjusts the control voltage VCL until both the phase and the frequency of feedback clock signal FBCLK match the phase and the frequency of reference clock signal REFCLK. When the frequency of clock signal REFCLK is greater than the frequency of clock signal FBCLK, PFD401generates high pulses in the UP signal that are longer than high pulses in the DN signal. Charge pump402increases control voltage VCL in response to high pulses in the UP signal that are longer than high pulses in the DN signal. Voltage buffer404increases voltage VOS in response to the increase in control voltage VCL. VCO408increases the frequency of clock signals OUT1/OUT1B and OUT2/OUT2B in response to the increase in voltage VOS. The frequency of FBCLK increases in response to the increased frequency of OUT1/OUT1B.

When the frequency of clock signal FBCLK is greater than the frequency of clock signal REFCLK, PFD401generates high pulses in the DN signal that are longer than high pulses in the UP signal. Charge pump402decreases control voltage VCL in response to high pulses in the DN signal that are longer than high pulses in the UP signal. Voltage buffer404decreases voltage VOS in response to the decrease in control voltage VCL. VCO408decreases the frequency of clock signals OUT1/OUT1B and OUT2/OUT2B in response to the decrease in voltage VOS. The frequency of FBCLK decreases in response to the decreased frequency of OUT1/OUT1B. PLL400maintains VCL and VOS constant when FBCLK and REFCLK are aligned in phase and have the same frequency. VCO408maintains the frequency of its output clock signals constant in response to VOS remaining at a constant voltage.

Low pass filter411filters high frequency noise from an input voltage VIN to generate a bias voltage VBS that is transmitted to a control input of voltage buffer410. Voltage buffer410generates a constant supply voltage VCON at its output. The voltage of VCON is based on the voltage VBS at the control input of buffer410and the voltage VLP at the supply input of buffer410. The constant supply voltage VCON is provided to second supply inputs of VCO cells406-407, as shown inFIG. 4.

Voltage buffer410can be, for example, a native n-channel MOSFET having a low threshold voltage near zero volts. The native n-channel MOSFET in voltage buffer410has a drain that receives voltage VLP, a gate that receives voltage VBS, and a source that generates voltage VCON.

FIG. 5is a schematic diagram that illustrates an example of a VCO cell, according to an embodiment of the present invention. VCO cell406has the VCO cell circuit architecture shown inFIG. 5. VCO cell407has the VCO cell circuit architecture shown inFIG. 5. Thus, each of the VCO cells406and407in VCO408has the VCO cell circuit structure shown inFIG. 5.

The VCO cell shown inFIG. 5includes p-channel metal oxide semiconductor field-effect transistors (MOSFETs)501-504and n-channel MOSFETs505-508. INP is the non-inverting (+) input of VCO cell406/407, and INN is the inverting (−) input of VCO cell406/407. OUTP is the non-inverting output of VCO cell406/407, and OUTN is the inverting output of VCO cell406/407. The inverting outputs of VCO cells406-407are represented by circles inFIG. 4.

The gates of transistors501,503, and505are coupled to input INP, and the gates of transistors502,504, and506are coupled to input INN. The drains of transistors501,503,505, and507are coupled to output OUTN. The drains of transistors502,504,506, and508are coupled to output OUTP. Transistors507and508are cross-coupled with each other. The sources of transistors505-508are at a ground voltage. The oscillator supply voltage VOS is provided to the source and bulk terminals of transistors501-502. The constant supply voltage VCON is provided to the source and bulk terminals of transistors503-504.

Transistors503and505function as a first inverter, and transistors504and506function as a second inverter. When the voltage at INN is in a logic high state, and the voltage at INP is in a logic low state, the VCO cell ofFIG. 5pulls the voltage at OUTP to a logic low state and the voltage at OUTN to a logic high state. Conversely, when the voltage at INN is in a logic low state, and the voltage at INP is in a logic high state, the VCO cell ofFIG. 5pulls the voltage at OUTP to a logic high state and the voltage at OUTN to a logic low state. Cross-coupled transistors507and508cause the differential output voltages of the VCO cell at outputs OUTP and OUTN to have opposite polarities, so that VCO408generates oscillating clock signals.

The constant supply voltage VCON generated at the output of voltage buffer410is a programmable voltage. The voltage of VCON can be programmed to a different value by varying the programmable voltage of VIN. The voltage of VCON is programmed to a desired value prior to the operation of PLL400. During the operation of PLL400when VCO408is generating oscillating output clock signals, VCON remains at a constant voltage. If appropriate voltages are selected for VIN, VBS, and VLP, and voltage buffer410is an n-channel transistor, the n-channel transistor in buffer410prevents backflow current from VCO408to LPF405when VOS increases above VCON.

The voltage of VCON and the voltage range of VOS determine the frequency range that VCO408generates in its output clock signals OUT1/OUT1B and OUT2/OUT2B. The frequency of the output clock signals of delay cells406-407varies based on changes in the oscillator supply voltage VOS. The voltage of VCON determines the starting frequency and the minimum frequency of the output clock signals OUT1/OUT1B and OUT2/OUT2B of VCO408. The current supplied from voltage buffer410allows VCO408to generate a minimum frequency of oscillation in output clock signals OUTVOUT1B and OUT2/OUT2B when voltage buffer404is off and not providing current from LPF405to VCO408. Voltage buffer404may be off if voltage VCL is too low to turn voltage buffer404on.

VCON can be programmed to set a desired minimum frequency for the output clock signals of VCO408. For example, VCON can be programmed to be a voltage between 0 and 1.5 volts, and VCL can vary between 0.4 and 1.6 volts during the operation of PLL400.

The constant supply voltage VCON is maintained at a large enough voltage during the operation of PLL400to allow transistors503-504and transistors505-508to be switched on and off. As a result, VCO delay cells406and407generate oscillations in output clock signals OUT1/OUT1B and OUT2/OUT2B using current from voltage buffer410, even when the voltage of VOS is not large enough by itself to generate oscillations in output clock signals OUT1/OUT1B and OUT2/OUT2B. Providing a supply voltage VCON to transistors503-504that is large enough to allow transistors503-508to be switched on and off increases the minimum frequency that VCO408generates in output clock signals OUT1/OUT1B and OUT2/OUT2B.

Providing a constant supply voltage VCON to transistors503-504also reduces the tuning range of frequencies that VCO408generates in its output clock signals. Because the frequency tuning range of VCO408is reduced, the gain of VCO408is reduced relative to VCO104inFIG. 1. The reduction in the gain of VCO408causes VCO408to be less sensitive to supply voltage noise and parasitic coupling. As a result, VCO408generates significantly less jitter in its output clock signals than VCO104.

FIG. 6is a graph that illustrates examples of the frequency response and the gain of VCO408shown inFIG. 4. The frequency tuning range for the differential output clock signal OUT1/OUT1B of VCO408varies from about 6.5 GHz to about 15.8 GHz in the example shown in the graph ofFIG. 6. The frequency tuning range of VCO408is substantially reduced compared to the frequency tuning range of VCO104shown inFIG. 3. The minimum frequency of VCO408(about 6.5 GHz) is substantially larger than the minimum frequency of VCO104(about 1 GHz). The gain (KVCO) of VCO408has a maximum value of about 9.6 GHz/volt, compared to a maximum gain of about 12 GHz/volt for VCO104. The reduction in gain allows VCO408to generate significantly less jitter in its output clock signals than VCO104.

The VCO cell ofFIG. 5causes VCO408to be less sensitive to noise in the oscillator supply voltage VOS. Charge pump reference spurs that are caused by non-idealities in the switches in charge pump402are reduced in the output clock signals of VCO408.

As data rates increase, the PLLs in data transmission systems need to generate clock signals with larger frequencies for sampling data transmitted at higher data rates. If the minimum frequency of the VCO output clock signals remains the same, while the maximum frequency of the VCO output clock signals increases, the gain of the VCO increases, and the VCO generates more jitter in its output clock signals. VCO408shown inFIGS. 4-5generates substantially less jitter in its output clock signals at greater frequencies, because VCO408has a reduced gain and a reduced tuning range. In general, a wide VCO tuning range is desirable, but a wide VCO tuning range causes increased VCO gain.

Larger transistors can tolerate more voltage stress than smaller transistors. As transistor sizes are reduced, the voltage range of the control voltage in a phase-locked loop is reduced to prevent breakdown of the transistor in the voltage buffer404. A reduction in the voltage range of the control voltage increases the gain of a VCO in a PLL. VCO408reduces the VCO gain or limits the increase in the VCO gain that occurs when the control voltage range of VCL is reduced to prevent a significant increase in the jitter in the VCO output clock signals.

In some embodiments, VCO408provides at least an octave of tuning range in its output clock signals. An octave of tuning range refers to the maximum frequency that VCO408can generate in its output clock signals being two times the minimum frequency that VCO408can generate in its output clock signals. Frequency divider circuits can be used to divide the frequency of the output clock signals of VCO408to generate clock signals having a wide continuous range of frequencies that support a wide range of data rates in a data transmission system.FIG. 6illustrates the frequency response for an example implementation of VCO408that provides at least an octave of tuning range in its output clock signals.

FIG. 7is a simplified partial block diagram of a field programmable gate array (FPGA)700that can include aspects of the present invention. FPGA700is merely one example of an integrated circuit that can include features of the present invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), application specific integrated circuits (ASICs), memory integrated circuits, central processing units, microprocessors, analog integrated circuits, etc.

FPGA700includes a two-dimensional array of programmable logic array blocks (or LABs)702that are interconnected by a network of column and row interconnect conductors of varying length and speed. LABs702include multiple (e.g., 10) logic elements (or LEs).

An LE is a programmable logic circuit block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.

FPGA700also includes a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks704, blocks706, and block708. These memory blocks can also include shift registers and first-in-first-out (FIFO) buffers.

FPGA700further includes digital signal processing (DSP) blocks710that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs)712located, in this example, around the periphery of the chip, support numerous single-ended and differential input/output standards. IOEs712include input and output buffers that are coupled to pads of the integrated circuit. The pads are external terminals of the FPGA die that can be used to route, for example, input signals, output signals, and supply voltages between the FPGA and one or more external devices. It is to be understood that FPGA700is described herein for illustrative purposes only and that the present invention can be implemented in many different types of integrated circuits.

The present invention can also be implemented in a system that has an FPGA as one of several components.FIG. 8shows a block diagram of an exemplary digital system800that can embody techniques of the present invention. System800can be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system800can be provided on a single board, on multiple boards, or within multiple enclosures.

System800includes a processing unit802, a memory unit804, and an input/output (I/O) unit806interconnected together by one or more buses. According to this exemplary embodiment, an FPGA808is embedded in processing unit802. FPGA808can serve many different purposes within the system ofFIG. 8. FPGA808can, for example, be a logical building block of processing unit802, supporting its internal and external operations. FPGA808is programmed to implement the logical functions necessary to carry on its particular role in system operation. FPGA808can be specially coupled to memory804through connection810and to I/O unit806through connection812.

Processing unit802can direct data to an appropriate system component for processing or storage, execute a program stored in memory804, receive and transmit data via I/O unit806, or other similar functions. Processing unit802can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU.

For example, instead of a CPU, one or more FPGAs808can control the logical operations of the system. As another example, FPGA808acts as a reconfigurable processor that can be reprogrammed as needed to handle a particular computing task. Alternatively, FPGA808can itself include an embedded microprocessor. Memory unit804can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means.

The foregoing description of the exemplary embodiments of the present invention has been presented for the purposes of illustration and description. The foregoing description is not intended to be exhaustive or to limit the present invention to the examples disclosed herein. In some instances, features of the present invention can be employed without a corresponding use of other features as set forth. Many modifications, substitutions, and variations are possible in light of the above teachings, without departing from the scope of the present invention.