Startup protection for standby amplifiers

Embodiments herein relate to protection of a standby amplifier of a memory device. Specifically, an input voltage of the standby amplifier may be reduced to decrease an occurrence of damage to the standby amplifier or components thereof. In some embodiments, the input voltage may be reduced using a voltage divider that provides the reduced input voltage to the standby amplifier during a power up operation. Upon completion of the power up operation, the input voltage of the standby amplifier may return to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate to drain voltage of one or more transistors of the standby amplifier below a maximum.

BACKGROUND

The present disclosure generally relates to computing systems and, more particularly, to reducing a startup voltage of a standby amplifier to reduce a breakdown of an input device of the standby amplifier.

Generally, a computing system includes a host sub-system and a memory sub-system. The memory sub-system may store data accessible to processing circuitry of the host sub-system. For example, to perform an operation, the processing circuitry may execute instructions retrieved from a memory device implemented in the memory sub-system. In some instances, input data for the operation may also be retrieved from the memory device. Additionally or alternatively, data output (e.g., resulting) from the operation may be stored in the memory device, for example, to enable subsequent retrieval. However, in some instances, operational efficiency of the computing system may be limited by the architecture of the memory sub-system and, in particular, to circuitry related to the column-select operation for retrieving data stored in the memory device.

DETAILED DESCRIPTION

The present disclosure provides apparatus and techniques that facilitate improved operating efficiency and/or operating performance of computing systems, for example, by reducing a voltage of an enable signal for a startup amplifier while minimizing an increase of a physical size of the computing system.

A computing system generally includes various computing sub-systems, such as a host (e.g., processing) sub-system and a memory sub-system. The host sub-system may include processing circuitry, for example, implemented in one or more processors and/or one or more processor cores. The memory sub-system may include one or more memory devices (e.g., chips or integrated circuits), for example, implemented on a memory module, such as a dual in-line memory module (DIMM), and/or organized to implement one or more memory arrays (e.g., banks of memory cells).

Generally, during operation of the computing system, processing circuitry implemented in the processing sub-system may perform various operations by executing instructions stored in the memory sub-system. For example, the processing sub-system may determine output data by executing a data processing operation based on input data. Additionally, a processing sub-system may generally include one or more registers and/or one or more processor-side caches, which provide storage locations directly accessible to the processing sub-system. However, storage capacity implemented in a processing sub-system is generally limited.

As such, the processing sub-system is often communicatively coupled to a memory sub-system via one or more memory buses (e.g., external communication, command, and/or data buses). In some cases, a computing system may include multiple memory buses, for example, each dedicated to different types of communication. For example, the computing system may include a memory command (e.g., control and/or request) bus dedicated to communication of command (e.g., control) signals indicative of memory access command (e.g., a memory read or write command), and a memory data bus dedicated to communication of data signals indicative of a data block to be stored (e.g., written) in a memory device of the memory sub-system (e.g., in response to a memory write command and/or a memory read command).

Moreover, in some instances, memory in a memory sub-system may be implemented using multiple different memory types. For example, the memory sub-system may include one or more volatile memory devices, such as a dynamic random-access memory (DRAM) device and/or a static random-access memory (SRAM) device, one or more non-volatile memory devices, such as a flash (e.g., NAND) memory device, a phase-change memory (e.g., 3D XPoint™) device, and/or a ferroelectric random access memory (FeRAM) device

The memory device(s) in a memory sub-system generally includes various amplifiers (e.g., regulators), including a standby amplifier and an active amplifier. The active amplifier may be a main amplifier of the memory device and may support a relatively large amount of current, for example during a read or write operation. The standby amplifier may be operational when there is no current demand or minimal current demand from the memory device. The standby amplifier may ensure that voltages in the memory device are maintained at a specified level when there is no or minimal current demand. A maximum current provided by the standby amplifier may be about ten to twenty percent of a maximum current of the active amplifier. For example, if a maximum current of the active amplifier is about five milliamps (mA), the standby amplifier may provide up to about 500 microamps (μA). The standby amplifier may be powered on at startup (e.g., power up) and during operation of a respective memory device.

Protection of memory devices and associated amplifiers may be critical during startup because voltages of the memory device may be in a meta-stable state. To protect a startup amplifier of the memory device, an input voltage (e.g., enable voltage) of the startup amplifier may be reduced. Embodiments presented herein provide apparatus and techniques to reduce a startup voltage of a standby amplifier to improve an operating performance and prolong a life of one or more components thereof. Further, the reduced startup voltage may be clamped to the standby amplifier only during the startup operation and thus may not affect the standby amplifier or memory device during a normal operation mode (e.g., after startup).

FIG.1is a simplified block diagram of an example of a computing system10(e.g., an apparatus), which includes a processing (e.g., host) sub-system12and a memory sub-system14, according to an embodiment of the present disclosure. It should be understood that the computing system10may include computing sub-systems not shown inFIG.1, such as a networking sub-system, a communication sub-system, a radio frequency sub-system, a user input sub-system, a display sub-system, or a combination thereof.

In some embodiments, the computing system10may be implemented in a single electronic device, such as a desktop computer, a workstation computer, a laptop computer, a server, a mobile phone, a virtual-reality headset, and/or the like. In other embodiments, the computing system10may be distributed between multiple electronic devices. For example, the processing sub-system12and the memory sub-system14may be implemented in a host device while other computing sub-systems, such as the user input and/or display sub-systems, may be implemented in a client (e.g., remote) device. In some embodiments, a computing sub-system may be distributed between multiple electronic devices. For example, a first portion of the processing sub-system12and/or a first portion of the memory sub-system14may be implemented in a host device while a second portion of the processing sub-system12and/or a second portion of the memory sub-system14may be implemented in a client device.

As shown, the processing sub-system12may include processing circuitry16. The processing circuitry16may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof. During operation, the processing sub-system12may perform various operations such as determining output data by executing, via the processing circuitry16, instructions to perform a data processing operations based on input data. The processing sub-system12may also include one or more caches22which may be integrated with the processing circuitry16. The one or more caches22may provide storage locations directly accessible to the processing circuitry16. The processing sub-system12may be coupled to one or more memory controllers28via one or more buses27to control storage of the one or more caches22.

The memory sub-system14generally stores data accessible by the processing sub-system12via one or more memory devices18. The memory devices18may include integrated circuits or chips with one or more memory cells (e.g., circuitry) organized into one or more memory arrays and thus, may include one or more tangible, non-transitory, computer-readable media. For example, the memory sub-system14may include one or more dynamic random-access memory (DRAM) devices, one or more static random-access memory (SRAM) devices, one or more flash (e.g., NAND) memory devices, one or more phase-change memory (e.g., 3D XPoint™) memory devices, one or more ferroelectric random access memory (FeRAM), or any combination thereof.

In some embodiments, multiple memory devices18may be implemented on a memory module, such as a dual in-line memory module (DIMM) or a single in-line memory module (SIMM). For example, a memory module may include a printed circuit board (PCB) and multiple memory devices18each disposed on a flat or planar (e.g., front or back) surface of the printed circuit board. Additionally, the memory devices18may be coupled to external pins formed along an (e.g., bottom) edge of the printed circuit board via conductive traces formed on the printed circuit board.

It should be understood that one or more of the memory devices18may be implemented using other packing techniques. For example, the memory devices18may be coupled to a (e.g., silicon) interposer to implement a 2.5D configuration. Additionally or alternatively, the memory devices18may be stacked to implement a 3D configuration. Furthermore, in some embodiments, the memory devices18may be implemented using organic packaging techniques. In other words, the techniques described in the present disclosure may be implemented as an on-package solution.

The memory sub-system14also includes one or more memory caches24. Although implemented in the memory sub-system14, the memory cache24may nevertheless provide faster data communication compared to a memory array implemented in the memory devices18. For example, the memory cache24may be implemented with static random-access memory (SRAM) while the memory devices18may be implemented with dynamic random-access memory (DRAM). Additionally or alternatively, a memory cache24and a memory array implemented in the one or more memory devices18may utilize the same memory type (e.g., DRAM). In fact, in some embodiments, one or more of the memory caches24may be implemented in the memory devices18. To control storage of the one or more memory caches24, the memory sub-system14may be coupled to the one or more memory controllers28via the one or more buses27.

As shown, the processing sub-system12is communicatively coupled to the memory sub-system14via one or more memory buses20. The data buses20may include one or more cables, one or more wires, one or more conductive traces, one or more communication networks, or any combination thereof. Each of the one or more memory buses20may be dedicated to different communication types between the memory sub-system14and the processing sub-system12. For example, the memory buses20may include a memory command bus and a memory data bus.

FIG.2is a schematic diagram of an example circuit50of a standby amplifier52of a memory device18implemented in the memory sub-system14ofFIG.1, according to an embodiment of the disclosure. The example circuit50includes a protection circuit54coupled to the standby amplifier52. In some cases, the standby amplifier52may be referred to as a operational transconductance amplifier (OTA). In some cases, the standby amplifier may include the OTA52and the protection circuit54. The standby amplifier52includes transistors T1, T2, T3, and T4. The transistors T1and T2may form a first input pair of the standby amplifier52and the transistors T3and T4may form a second input pair of the standby amplifier52. The standby amplifier52may have a finite bandwidth and thus a gate voltage of the transistors T1and T3may increase slowly.

The protection circuit54includes transistors T9and T10. The transistors T9and T10may be enabled (e.g., closed) when an enable voltage En58is applied to a gate thereof via a node56. A larger enable voltage En58may close the transistors T9and T10more quickly and thus increase a voltage across the transistors T1and T3to a high voltage (e.g., VPP) more quickly.

The example circuit50also includes transistors T5, T6, T7, and T8coupled to the amplifier52. As shown, each of the transistors T1-T10may be n-channel transistors. It should be understood that the transistors T1-T10may be different types (n-channel or p-channel) and may be disposed in a different configuration than shown. In some cases, the standby amplifier52may provide up to about 500 microamps (μA).

In some embodiments, a maximum voltage of the transistor T1may be, for example, about 1.4 volts from drain-to-source, gate-to-drain, or gate-to-source. If one of those voltage measurements exceeds about 1.4 volts, the transistor T1may be damaged beyond repair and the standby amplifier52may no longer be operational. To prevent damage to the transistor T1(and the transistor T3) and/or the standby amplifier52, the protection circuit54may ensure that a drain voltage of the transistor T1does not exceed a gate voltage of the transistor T9minus a threshold voltage VTof the transistor T9. That is, a drain voltage of the transistor T1may be less than the enable voltage En58at a gate of the transistor T9minus the threshold voltage VTof the transistor T9. The transistor T10may have a threshold voltage similar to that of the transistor T9. A drain voltage of the transistor T3may be the same or substantially similar to the drain voltage of the transistor T9. In this way, the transistors T9and T10of the protection circuit54may limit a voltage of the transistors T1and T3of the standby amplifier52.

At startup of the standby amplifier52, a gate voltage of the transistors T1and T2may be about 1 volt and a gate voltage of the transistors T3and T4may be zero volts. However, a drain of the transistors T1and T3may be a high voltage (e.g., about 2.2 volts). In that case, a voltage across the transistors T1and T3may be larger than the maximum voltage of about 1.4 volts. Thus, the transistors T1and/or T3may be damaged.

Embodiments disclosed herein present apparatus and techniques to reduce and/or limit the enable voltage En58supplied to the transistors T1and T3via the protection circuit54during a startup operation. Once the startup operation is complete, the enable voltage En58may return to a previous voltage level. Advantageously, the reduced enable voltage En58may reduce an occurrence of damage to components (e.g., transistors T1-T4) of the standby amplifier52during the startup operation without impacting performance or operation thereafter.

FIG.3is a schematic diagram of an example circuit80for generating the enable signal for the standby amplifier52ofFIG.2, according to an embodiment of the disclosure. As shown, the circuit80may receive various inputs82and88-94. Specifically, an input of the circuit80may include a power up signal90. When the power up signal90is high (e.g., between about 1 volt and about 1.5 volts, such as about 1.2 volts), the enable voltage En58may be high (e.g., about 2 volts). The circuit80includes a number of components including a number of inverters84, switches96, a logical NOR gate100, and a logical NAND gate102.

The enable voltage En58is output from the example circuit80via an output node120. The enable voltage En58may be supplied to the protection circuit54via the node56as discussed with respect toFIG.2. That is, the node56of the standby amplifier52may be coupled to the output node120of the circuit80.

FIG.4is a schematic diagram of an example circuit150for generating a reduced enable voltage EnDy152for the standby amplifier52ofFIG.2, according to an embodiment of the disclosure. The example circuit150is a voltage divider that generates a reduced enable voltage EnDy152from the enable voltage En58. That is, the voltage divider150receives the enable voltage En58via the node output120of the circuit80ofFIG.3.

In some embodiments, the voltage divider150may be a resistive divider. As shown, the voltage divider150includes a number of resistors R1-R7. In some embodiments, a resistance of each of the resistors R1-R7may be the same. For example, a resistance of each of the resistors may be about 30 kilo-ohms (kΩ). In other embodiments, the resistance of each resistor R1-R7may be different. In some cases, an area of each resistor R1-R7may be about 1 micrometer.

The reduced enable voltage EnDy152may be generated by tapping the voltage divider150between the resistors R2and R3via a switch156. Thus, the reduced enable voltage EnDy152may be about 30% less than the enable voltage En58. In some embodiments, the reduced enable voltage EnDy152may be about 15% less than the enable voltage En58by closing (or opening) the switch156such that the switch156taps the voltage divider150between the resistors R1and R2.

The reduced enable voltage EnDy152may be provided to the standby amplifier52until an inverse power up signal154transitions from a logic high voltage (e.g.,1) to a logic low voltage (e.g.,0). That is, the inverse power up signal154may be a logic high before the power up operation and until the power up operation is complete. When the power up operation is complete, the power up signal90may transition from a logic low to a logic high. That is, the logic high of the inverse power up signal154may close the transistor T12such that a current flows through the voltage divider150and the reduced enable voltage EnDy152is provided to the standby amplifier52. Once the power up operation is complete, the inverse power up signal154may transition from the logic high to the logic low, causing the transistor T12to open and stop current flowing through the resistors R1-R7. In that case, the enable voltage En58may be coupled to the protection circuit54after the power up operation is complete. In this way, the transistor T12may control a voltage level provided to the protection circuit54such that a reduced enable voltage (e.g., EnDy152) may be provided to the protection circuit during the power up operation.

In this way, the voltage divider150may provide the reduced enable voltage EnDy152to the standby amplifier52to reduce an occurrence of damage to the standby amplifier52and/or components thereof during the startup operation. Upon completion of the startup operation, the voltage divider150may provide the enable voltage En58(e.g., not reduced) to the standby amplifier52to ensure normal operation. It should be understood that the voltage divider150is merely an example and that many other configurations including different layouts and/or more or fewer resistors are possible to obtain different values of the reduced enable voltage EnDy152. For example, the reduced enable voltage EnDy152may be generated by tapping the voltage divider150between different resistors than discussed above, such as between the resistors R3and R4. Advantageously, the reduced enable voltage EnDy152may reduce an occurrence of damage to one or more components of the standby amplifier52and thus, may prolong a lifespan of the components and/or the standby amplifier.

FIG.5is a graph180illustrating signal waveforms of the standby amplifier52ofFIG.2using the example circuit80ofFIG.3, according to an embodiment of the disclosure. As shown, the graph180includes the power up signal90, the enable voltage En58, a gate voltage184of the transistor T1or the transistor T3ofFIG.2, a drain voltage186of the transistor T1or the transistor T3, a gate to drain voltage (VGD)188across the transistor T1or the transistor T3, and an output voltage190of the standby amplifier52.

In operation, when the power up signal90transitions from low to high (e.g., from about 0 volts to about 1 volt), the gate to drain voltage (VGD)188across the transistor T1or the transistor T3increases to over 1.4 volts. That is, the gate to drain voltage (VGD)188across the transistor T1or the transistor T3exceeds the maximum voltage of the transistor T1or the transistor T3. Thus, during the power up operation, the transistor T1or the transistor T3may be damaged by the relatively high voltage. In some cases, the high voltage (e.g., greater than 1.4 volts) may be applied across the transistor T1or the transistor T3for a relatively long time period (e.g., between about 1 microsecond (μs) and about 4 μs), increasing the damage to the transistor T1or the transistor T3.

If the transistor T1or the transistor T3is not catastrophically damaged during a particular power up operation, the damage may be cumulative and thus the transistor T1or the transistor T3may be catastrophically damaged during a subsequent power up operation. As discussed above, embodiments herein present techniques to reduce the voltage supplied to the transistor T1or the transistor T3(and thus across the transistor T1or the transistor T3) to substantially reduce an occurrence of damage caused thereby.

FIG.6is a graph200illustrating signal waveforms of the standby amplifier52ofFIG.2using the example circuits80and150ofFIGS.3and4, according to an embodiment of the disclosure. That is, the graph200illustrates signal waveforms using the voltage divider150to provide the reduced enable voltage EnDy152to the standby amplifier52. As shown, the enable voltage En of the standby amplifier52ofFIG.2is clamped to the reduced enable voltage EnDy152for a time period204during the power up operation of the standby amplifier52. As a result of the reduced enable voltage EnDy152, the gate to drain voltage (VGD)188across the transistor T1or the transistor T3may be reduced to about 1 volt. Once the power up operation is complete, the input voltage of the standby amplifier52may return to the enable voltage En58voltage level (e.g., when the power up signal90transitions from low to high and the inverse power up signal154transitions from high to low).

That is, the reduced enable voltage EnDy152maintains the gate to drain voltage (VGD)188below the maximum voltage (e.g., 1.4 volts) of the transistor T1or the transistor T3. In this way, the reduced enable voltage EnDy152may reduce an occurrence of damage to one or more components of the standby amplifier52and thus, may prolong a lifespan of the components and/or the standby amplifier.