Gate structure

A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode.

BACKGROUND

Example embodiments relate to a gate structure, a method of forming a gate structure and a method of manufacturing a semiconductor device including a gate structure. More particularly, example embodiments relate to a gate structure including an upper portion having a width smaller than that of a lower portion, a method of forming the gate structure and a method of manufacturing a semiconductor device including the gate structure.

2. Description of the Related Art

Generally, a contact structure such as a contact plug penetrates an insulation interlayer interposed between a lower conductor and an upper conductor to electrically connect the lower and upper conductors to each other.

As the degree of integration of semiconductor devices continues to increase, the interconnect wiring width and or the spacing between the wirings becomes smaller. Thus, the spacing margin between the wiring and any contact plugs positioned between neighboring wiring segments is decreased.

As the distance between gate electrodes of a semiconductor device is decreased, the distance between a neighboring contact plug and a gate electrode is also decreased, and thus the problem of electrical shorting between the contact plug and the gate electrode is more likely to occur. In particular, contact plugs tend to widen at their upper portions. In this case, the width of an upper portion of the contact plug is greater than that of a lower portion of the contact plug, with the lower portion being connected to an impurity region formed in the substrate adjacent a gate electrode. Accordingly, an upper portion of the nearby gate electrode can inadvertently make contact with the neighboring contact plug more often than a lower portion of the gate electrode, causing a shorting problem.

SUMMARY

Example embodiments provide a gate structure capable of preventing an electrical short between a contact plug and a neighboring gate electrode and a method of forming the gate structure.

Example embodiments provide a semiconductor device including the gate structure and a method of manufacturing the semiconductor device.

According to an aspect of example embodiments, a gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode.

In an example embodiment, the gate electrode can be partially oxidized to form the protecting layer pattern. The upper portion and the central portion of the gate electrode can include silicon, and the protecting layer pattern can include silicon oxide.

In some example embodiments, the third width of the upper portion of the gate electrode can be substantially smaller than the first width, and the third width can be substantially the same as or substantially similar to the second width.

In other example embodiments, the third width of the upper portion of the gate electrode can be substantially smaller than the first width, and the third width can be substantially greater than the second width. The gate structure can further include a metal silicide pattern enclosing the upper portion of the gate electrode.

In an example embodiment, the gate structure can further include a second spacer on the first spacer and the protecting layer pattern.

According to another aspect of example embodiments, there is provided a method of forming a gate structure. In the method of forming the gate structure, a gate insulation layer pattern is formed on a substrate. A preliminary gate electrode is formed on the gate insulation layer pattern. A first spacer is formed on a lower sidewall of the preliminary gate electrode. A portion of the preliminary gate electrode exposed by the first spacer is partially oxidized to form a protecting layer so that the preliminary gate electrode is changed into a gate electrode including a lower portion having a first width and an upper portion having a second width. The protecting layer is partially removed to form a protecting layer pattern on a central sidewall of the gate electrode.

In an example embodiment, an upper portion and a central portion of the preliminary gate electrode can include silicon, and the protecting layer can include silicon oxide.

In an example embodiment, the protecting layer can be formed by a thermal oxidation process or a plasma oxidation process.

In an example embodiment, forming the protecting layer pattern can include forming a second spacer on the first spacer and a sidewall of the protecting layer, and partially removing the protecting layer exposed by the second spacer.

In an example embodiment, the protecting layer can be removed by a wet etching process to form the protecting layer pattern.

In an example embodiment, the method can further include forming a metal silicide pattern in the upper portion of the gate electrode. Forming the metal silicide pattern can include forming a metal layer on the gate electrode and the substrate, thermally treating the metal layer to form a metal silicide layer on the substrate and the gate electrode, and removing unreacted metal layer.

According to still another aspect of example embodiments, there is provided a method of manufacturing a semiconductor device. In the method of manufacturing the semiconductor device, a gate insulation layer pattern is formed on a substrate. A preliminary gate electrode is formed on the gate insulation layer pattern. A first spacer is formed on a lower sidewall of the preliminary gate electrode. A portion of the preliminary gate electrode exposed by the first spacer is partially oxidized to form a protecting layer so that the preliminary gate electrode is changed into a gate electrode including a lower portion having a first width and an upper portion having a second width. An impurity region is formed in the substrate adjacent to the gate electrode. The protecting layer is partially removed to form a protecting layer pattern on a central sidewall of the gate electrode. An insulation interlayer is formed on the substrate to cover the gate electrode. A plug is formed to penetrate the insulation interlayer and is connected to the impurity region.

In an example embodiment, an upper portion and a central portion of the preliminary gate electrode can include silicon, and the protecting layer can include silicon oxide.

In an example embodiment, the protecting layer can be formed by a thermal oxidation process or a plasma oxidation process.

In an example embodiment, forming the protecting layer pattern can include forming a second spacer on the first spacer and a sidewall of the protecting layer, and partially removing the protecting layer exposed by the second spacer.

In an example embodiment, the method can further include forming a metal silicide pattern in the upper portion of the gate electrode.

In an example embodiment, the method can further include forming an etch stop layer on the gate electrode before forming the insulation interlayer.

According to example embodiments, because a gate electrode is provided where the upper portion of the gate electrode has a width that is smaller than the lower portion of the gate electrode, and because the protecting layer pattern is formed on the central sidewall of the gate electrode, even in cases where the contact or the plug is positioned between the gate electrodes that are spaced apart from each other by a reduced distance due to the reduction of the fabrication design rule, the plug can be prevented from contacting the gate electrode, to thereby improve the resulting reliability of a semiconductor device that includes the gate electrode and the plug.

DESCRIPTION OF EMBODIMENTS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2008-32595, filed on Apr. 8, 2008 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

FIG. 1is a cross-sectional view illustrating a gate structure in accordance with example embodiments.

Referring toFIG. 1, a gate structure142includes a gate insulation layer pattern110formed on a substrate100, a gate electrode114on the gate insulation layer pattern110, a first spacer122on a lower sidewall of the gate electrode114, and a protecting layer pattern132on a central sidewall of the gate electrode114.

In example embodiments, the substrate100can include a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, and other suitable substrates.

The gate insulation layer pattern110is provided on the substrate. The gate electrode114is formed on the gate insulation layer pattern110. In an example embodiment, the gate insulation layer pattern110can include an oxide such as silicon oxide, and the gate electrode114can include doped polysilicon.

In some example embodiments, the gate electrode can have a multi-layered structure where a metal layer pattern (not illustrated) and a doped polysilicon pattern (not illustrated) are sequentially formed on the gate insulation layer pattern110. For example, the metal layer pattern can include titanium (Ti), tungsten (W), tantalum (Ta), rubidium (Rb), tantalum nitride (TaNx), tungsten nitride (WNx), titanium nitride (TiNx), hafnium nitride (HfNx), hafnium silicon nitride (HfSixNy), titanium silicon nitride (TiSixNy), tantalum silicon nitride (TaSixNy), hafnium aluminum nitride (HaAlxNy), etc. The metal layer pattern can reduce a depletion effect due to impurities of the polysilicon layer pattern from occurring. In an example embodiment, at least the central portion and an upper portion of the gate electrode114can include silicon.

The first spacer122is positioned on the lower sidewall of the gate electrode114. The first spacer122covers only a sidewall of the gate electrode122. A central portion of the gate electrode114is covered by the protecting layer pattern132. The spacer122can include, for example, an insulative material such as oxide or nitride. For example, the first spacer122can include silicon oxide or silicon nitride.

The protecting layer pattern132is positioned on a central portion of the sidewall of the gate electrode114. In an example embodiment, the protecting layer pattern132can include an oxide such as silicon oxide. The central portion of the gate electrode114exposed by the first spacer122can be subject to thermal oxidation to form the protecting layer pattern132. For example, the central portion of the gate electrode114exposed by the first spacer122can be selectively oxidized by a thermal oxidation process or a plasma oxidation process, to form the protecting layer pattern132. That is, the central portion of the gate electrode114including silicon can be partially oxidized to form the protecting layer pattern132including silicon oxide through a selective oxidation process.

In example embodiments, by a selective oxidation process, the protecting layer pattern132can be grown to have a first width (L1) inward with respect to the lower sidewall of the gate electrode114and a second width (L2) outward with respect to the lower sidewall of the gate electrode114. Here, a ratio between the first width (L1) and the second width (L2) can be in a range of about 1.0.0.6 to about 1.0:0.9. For example, when the first width (L1) is about 5 mm, the second width (L2) is about 3 nm. By forming the protecting layer pattern132, a lower portion of the gate electrode114can have a first width (W1) and the central portion of the gate electrode114can have a second width (W2) substantially smaller than the first width (W1). The difference between the first width (W1) and the second width (W2) of the gate electrode114can correspond to the first width (L1) of the protecting layer pattern132.

In example embodiments, a metal silicide pattern152is formed on the upper portion of the gate electrode114exposed by forming the protecting layer pattern132. The metal silicide pattern can be formed on an upper surface and an upper sidewall of the gate electrode114to improve electrical properties of the gate electrode114. The metal silicide pattern152can include a metal having a high melting point. Examples of the metal can include cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), titanium (Ti), and other suitable metal materials.

In some example embodiments, the gate electrode114can include the lower portion having the first width (W1), the central portion having the second width (W2) smaller than the first width (W1) and the upper portion having a third width (W3). Here, the third width (W3) of the upper portion of the gate electrode114can be substantially smaller than the first width (W1) and can be substantially the same as, or substantially greater than, the second width (W2). For example, when the metal silicide pattern152is formed, the third width (W3) of the upper portion of the gate electrode114can be substantially greater than the second width (W2).

In example embodiments, an impurity region102can be formed in substrate100adjacent to the gate electrode114by an ion implantation process. The metal silicide pattern can further be formed on the impurity region102to reduce contact resistance between the impurity region102and a contact or a plug (not illustrated).

FIG. 2is a cross-sectional view illustrating a semiconductor device including a gate structure in accordance with example embodiments.

Referring toFIG. 2, a semiconductor device190includes a gate structure having a gate electrode114, an impurity region102formed in a substrate100adjacent to the gate electrode114, an insulation interlayer170formed on the substrate100to cover the gate structure142, and a contact or a plug180penetrating the insulation interlayer170to be connected to the impurity region102. In the semiconductor device190as illustrated inFIG. 2, the gate structure142can have a construction substantially the same or substantially similar to that described above with reference toFIG. 1.

The impurity region102is formed under a surface of the substrate100adjacent to the gate electrode114. The impurity region102can include N type or P type impurities according to the desired type of semiconductor device190.

In example embodiments, a metal silicide pattern152can be formed on the impurity region102. An etch stop layer160can be further formed on the substrate100to cover the gate structure142. The etch stop layer160can include nitride or oxynitride. For example, the etch stop layer160can include silicon nitride or silicon oxynitride.

The insulation interlayer170is formed on the substrate100to have a sufficient height such that the gate structure142is sufficiently covered with the insulation interlayer170. For example, the insulation interlayer170can include an insulative material containing oxide such as BPSG, PSG, USG, SOG, FOX, TOSZ, BPSG, PSG, TEOS, PE-TEOS, and other materials suitable for this purpose.

A contact hole172is formed in the insulation interlayer170to expose the impurity region102adjacent to the gate structure142. The contact hole172can be formed, for example, by a photolithography process. In an example embodiment, an upper portion of the contact hole172can have a width greater than that of a lower portion of the contact hole172.

The contact or the plug180is formed in the contact hole172. The plug180is connected to the impurity region180, to electrically connect the impurity region102to a pad or wiring (not illustrated) formed on, or otherwise connected to an upper surface of, the plug180. An upper portion of the plug180can have a width greater than that of a lower portion of the plug180according to the shape of the contact hole172.

As described above, because the upper portion of the gate electrode114has a width substantially smaller than that of the lower portion of the gate electrode114, even in situations where the gate electrodes114are formed relatively close to each other, the upper portions of the adjacent gate electrodes114can be sufficiently spaced apart from one another. That is, even though the semiconductor device is manufactured under a relatively fine design rule, the upper portions of the adjacent gate electrodes114can be sufficiently spaced apart from one another by a suitable distance. Further, because the protecting layer pattern132covers the central portion of the gate electrode114, a shorting failure between the gate electrode114and the plug180formed between the adjacent gate electrodes114can be prevented.

FIGS. 3 to 9are cross-sectional views illustrating a method of forming a gate structure in accordance with example embodiments.

Referring toFIG. 3, a gate insulation layer pattern110and a preliminary gate electrode112are formed on a substrate100. For example, the substrate100can include a silicon substrate, a SOI substrate, a germanium substrate, a GOI substrate, a silicon-germanium substrate, and other types of substrate materials. An isolation layer (not illustrated) can be formed in the substrate100to define an active region and a field region. In this case, the isolation layer can be formed using an insulative oxide, such as silicon oxide.

In example embodiments, after a gate insulation layer (not illustrated) and a gate conductive layer (not illustrated) are sequentially formed on the substrate100, the gate insulation layer and the gate conductive layer are patterned to form the gate insulation layer pattern110and the preliminary gate electrode112. The gate insulation layer pattern110and the preliminary gate electrode112can be formed using a photoresist pattern or a hard mask pattern as an etching mask pattern. The gate insulation layer can include silicon oxide. The gate insulation layer can be formed by a thermal oxidation process or a chemical vapor deposition process. The gate conductive layer can be formed using a material including silicon. For example, after a polysilicon layer is formed on the gate insulation layer, impurities are implanted into the polysilicon layer to form the gate conductive layer. Alternatively, the gate conductive layer can include a metal layer and a doped polysilicon layer. Accordingly, at least an upper portion and a central portion of the preliminary gate electrode112can include silicon.

Referring toFIG. 4, a first insulation layer120is formed on the substrate100and the preliminary gate electrode112. The first insulation layer120is later patterned to form a first spacer122(SeeFIG. 5). The first insulation layer120can be formed using nitride or oxynitride. For example, silicon nitride or silicon oxynitride can be deposited on the substrate100and the preliminary gate electrode112by a chemical vapor deposition process to form the first insulation layer120.

Referring toFIG. 5, the first insulation layer120is etched to form a first spacer122so that the first spacer remains only on a lower sidewall of the preliminary gate electrode112. The first spacer122can be formed by an anisotropic etching process. By the anisotropic etching process, the first insulation layer120on the substrate100can be removed to expose the substrate100between the preliminary gate electrodes112.

In example embodiments, as process conditions such as an etching rate, an etching gas or an etching solution and an etching time can be properly controlled, the portions of the first insulation layer120positioned on the upper portion and the central portion of the preliminary gate electrode112are removed. Thus, the first spacer122is formed only on the lower sidewall of the preliminary gate electrode112, and sidewalls of an upper portion and a lower portion of the preliminary gate electrode112are exposed.

Referring toFIG. 6, the preliminary gate electrode112is partially oxidized to form a protecting layer130and the preliminary gate electrode112is thereby changed in size to form a gate electrode114.

In example embodiments, the exposed upper and the central portions of the preliminary gate electrode112can be selectively oxidized by a thermal oxidation process or a plasma oxidation process. Because the upper and the central portions of the preliminary gate electrode112exposed by forming the first spacer122include silicon, as the upper and central portions of the preliminary gate electrode112are consumed by a selective oxidation process, silicon oxide is grown from the upper and the central portions of the preliminary gate electrode112to form the protecting layer130. Thus, the protecting layer130covers an upper portion and a central portion of the gate electrode114. Silicon oxide can also be grown from the portions of the substrate100that are exposed between the preliminary gate electrodes112during the selective oxidation process.

In an example embodiment, a thermal oxidation process can be performed under a pressure of about 0.25 Torr to about 2.0 Torr and at a temperature of about 900° C. to about 100° C., to form the protecting layer130. In this case, the protecting layer130can have about 3 nm to about 14 nm.

By the selective oxidation process, the protecting layer130is grown to a first width (L1) inward from the former boundary of the preliminary gate electrode112and is grown to a second width (L2) outward from the former boundary of the preliminary gate electrode112. Here, a ratio between the first width (L1) and the second width (L2) can be about 1.0:0.6 to about 1.0:0.9. For example, when the first width (L1) is about 5 nm, the second width (L2) is about 3 nm. By forming the protecting layer130, the preliminary gate electrode112is changed into the gate electrode114including a lower portion having a first width (W1) and an upper portion having a second width (W2). In this case, the second width (W2) of the gate electrode114can be substantially smaller than the first width (W1) of the gate electrode114.

As illustrated inFIG. 6, impurities are implanted into the substrate100exposed between the gate electrodes114to form an impurity region102. The impurity region102can be provided as a source/drain region. In some example embodiments, the impurity region102can be formed before the protecting layer130is formed. Here, the first spacer122can prevent the impurities from diffusing excessively to the substrate100under the gate electrode112.

Referring toFIG. 7, the protecting layer130is partially removed to form a protecting layer pattern132on a central sidewall of the gate electrode114. The protecting layer pattern132can be formed by a wet etching process. For example, the protecting layer130can be partially removed using an etching solution including hydrogen fluoride (HF).

By the etching process, the protecting layer pattern132is formed on the central sidewall of the gate electrode114to expose an upper portion of the gate electrode114. In this case, silicon oxide that is formed on the substrate100between the gate electrodes114is removed together by the etching process for forming the protecting layer pattern132. Thus, a first gate structure140including the gate insulation layer pattern110on the substrate100, the gate electrode114on the gate insulation layer pattern110, the first spacer122on the lower sidewall of the gate electrode114and the protecting layer pattern132on the central sidewall of the gate electrode114are formed.

Referring toFIG. 8, a metal layer150is formed conformally on the gate electrode114and the substrate100. The metal layer150can include a metal having a high melting point. Examples of the metal can include cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), titanium (Ti), etc. The metal layer150can be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an electroless plating process, and other suitable processes.

In example embodiments, a capping layer (not illustrated) is further formed on the metal layer150. The capping layer can prevent a surface of the metal layer150from oxidizing during a following thermal treatment process. For example, the capping layer can be formed using titanium (Ti) and/or titanium nitride (TiN). In some example embodiments, the process of forming the capping layer can be omitted for simplification.

Referring toFIG. 9, the metal layer150formed on the substrate100is thermally treated to react the metal layer150with silicon included in the upper portion of the gate electrode114. For example, the thermal treatment can include a rapid thermal annealing (RTA) process that is performed under a pressure of about 10−8Torr to about 3,000 Torr and at a temperature of about 300° C. to about 1,000° C. During the RTA process, metal of the metal layer150reacts with silicon included in the substrate100and the upper portion of the gate electrode114exposed by the protecting layer pattern132, to form a metal silicide pattern152. The metal silicide pattern152is formed in the upper portion of the gate electrode114and the substrate100exposed between the gate electrodes114. The metal silicide pattern152can improve conductivity of the gate electrode114and reduce contact resistance between the impurity region102and a contact or plug together.

After the thermal treatment, the unreacted metal layer150remaining on the first spacer122and the protecting layer pattern132is removed to complete a metal silicide pattern152. For example, the remaining metal layer150can be removed by a stripping process. However, the process for forming the metal silicide pattern152can be omitted for a simplification.

According to example embodiments, a second gate structure142including the gate electrode114is formed on the substrate100. The gate electrode114includes the lower portion having the first width (W1), the central portion having the second width (W2) substantially smaller than the first width (W1) and the upper portion having a third width (W3). The metal silicide pattern152can be formed in the upper portion of the gate electrode114, the protecting layer pattern132is formed on the central sidewall of the gate electrode114and the first spacer122is formed on the lower sidewall of the gate electrode114. Here, the third width (W3) of the upper portion of the gate electrode114can be smaller than the first width (W1) and can be substantially the same as, or substantially greater than, the second width (W2) of the central portion. For example, when the metal silicide pattern152is formed, the third width (W3) of the upper portion of the gate electrode114can be substantially greater than the second width (W2).

FIGS. 10 and 11are cross-sectional views illustrating a method of manufacturing a semiconductor device including a gate structure in accordance with example embodiments. InFIGS. 10 and 11, processes of forming the gate structure142are substantially the same as or substantially similar to those described with reference toFIGS. 3 to 9.

Referring toFIG. 10, after the second gate structure142is formed, an etch stop layer160is formed on the second gate structure142and the substrate100. The etch stop layer160can be formed using a nitride or an oxynitride by a chemical vapor deposition process. For example, the etch stop layer142can include silicon nitride or silicon oxynitride.

An insulation interlayer170is formed on the etch stop layer142to cover the second gate structures142, completely filling a gap between the second gate structures142. The insulation interlayer170can be formed, for example, using an oxide such as silicon oxide. In an example embodiment, an upper surface of the insulation interlayer170can be planarized by a planarization process. For example, the insulation interlayer170can be planarized by a chemical mechanical polishing process and/or an etch-back process.

Referring toFIG. 11, the insulation interlayer170is partially etched to form an opening or a contact hole172that exposes the metal silicide pattern152on the impurity region102. For example, after a photoresist pattern (not illustrated) is formed on the insulation interlayer170, the insulation interlayer170is etched using the photoresist pattern as an etching mask to form the contact hole172that exposes the metal silicide pattern152on the impurity region102. Here, an upper portion of the contact hole172can have a width greater than that of a lower portion of the contact hole172.

A conductive layer (not illustrated) is formed on the insulation interlayer170and the exposed metal silicide pattern152to fill the contact hole172. The conductive layer can be formed using doped polysilicon, metal and/or metal compound.

An upper surface of the conductive layer is planarized until the insulation interlayer170is exposed, to form a contact or plug180that fills the contact hole172. For example, the plug180can be formed by a chemical mechanical polishing process and/or an etch-back process. An upper portion of the plug180can have a width greater than that of a lower portion of the plug180according to the shape of the contact hole172. The plug180is electrically connected to the impurity region102through the metal silicide pattern152.

In a conventional semiconductor device, a plug that expands in size toward its top portion tends to make contact with the upper portion of the gate electrode, to thereby cause frequent shorting problems between the plug and gate electrode. However, according to example embodiments, because the upper portion of the gate electrode114has a width smaller than the lower portion of the gate electrode114, and because the protecting layer pattern132is formed on the central sidewall of the gate electrode114, even though the plug180is positioned between the gate electrodes114that are spaced apart from each other by a reduced distance according to a reduction of the fabrication design rule, the plug180can be prevented from contacting the gate electrode114, to thereby improve the resulting reliability of a semiconductor device that includes the gate electrode114and the plug180.

FIG. 12is a cross-sectional view illustrating a gate structure in accordance with example embodiments. The gate structure inFIG. 12is substantially the same as or substantially similar to the gate structure described with reference toFIG. 1, with the exception being that the gate structure inFIG. 12includes a second spacer adjacent the first spacer and opposite the gate electrode.

Referring toFIG. 12, a gate structure252includes a gate insulation layer pattern210formed on a substrate200, a gate electrode214on the gate insulation layer pattern210, a first spacer222on a lower sidewall of the gate electrode214, a protecting layer pattern232on a central sidewall of the gate electrode214, and a second spacer242on sidewalls of the first spacer222and the protecting layer pattern232.

The gate electrode214is electrically insulated from the substrate200by the gate insulation layer pattern210. The first spacer222covers the lower sidewall of the gate electrode214and the protecting layer pattern232covers the central sidewall of the gate electrode214. Accordingly, an upper portion of the gate electrode214is exposed by the first spacer222and the protecting layer pattern232.

In example embodiments, a portion of the gate electrode214exposed by the first spacer222can be selectively oxidized to form the protecting layer pattern232. For example, the protecting layer pattern232can be formed by a thermal oxidation process or a plasma oxidation process. Here, as silicon included in the gate electrode214is consumed by a selective oxidation process, silicon oxide can be grown to form the protecting layer pattern232. By the selective oxidation process, the protecting layer pattern232can be grown to have a first width (L1) inward wither respect to the lower sidewall of the gate electrode214and a second width (L2) outward with respect to the lower sidewall of the gate electrode214. A ratio between the first width (L1) and the second width (L2) can be about 1.0:0.6 to about 1.0:0.9. For example, when the first width (L1) can be about 5 nm, the second width (L2) can be about 3 nm. By forming the protecting layer pattern132, a lower portion of the gate electrode214can have a first width (W1) and a central portion of the gate electrode214can have a second width (W2) substantially smaller than the first width (W1).

As illustrated inFIG. 12, the second spacer242is provided on the first spacer222and the protecting layer pattern232. By forming the second spacer242, an upper surface of the protecting layer pattern232and the upper portion of the gate electrode214are exposed.

In example embodiments, a metal silicide pattern262including a metal having a high melting point can be formed in the upper portion of the gate electrode214exposed by forming the second spacer242. The metal silicide pattern262can improve electrical properties of the gate electrode214. When the metal silicide pattern262is formed, the upper portion of the gate electrode214can have a width that is substantially smaller than the first width (W1) of the lower portion and that is greater than the second width (W2) of the central portion. Accordingly, the gate electrode214can have an upper portion having a width that is substantially smaller than that of the lower portion. That is, the gate electrode214can include the lower portion having the first width (W1), the central portion having the second width (W2) substantially smaller than the first width (W2) and the upper portion having a third width (W3). While the third width (W3) of the upper portion of the gate electrode214is substantially smaller than the first width (W1) of the lower portion, the third width (W3) of the upper portion of the gate electrode214can be substantially smaller or substantially greater than the second width (W2) of the central portion. On the other hand, the third width (W3) of the upper portion of the gate electrode214can be substantially the same as the second width (W2) of the central portion. For example, when the metal silicide pattern262is formed, the third width (W3) of the upper portion of the gate electrode214can be substantially greater than the second width (W2) of the central portion.

FIG. 13is a cross-sectional view illustrating a semiconductor device including a gate structure in accordance with example embodiments.

Referring toFIG. 13, a semiconductor device290includes a gate structure252having a gate electrode214, an impurity region206formed in a substrate200adjacent to the gate electrode214, an insulation interlayer272formed on the substrate200to cover the gate structure252, and a contact or plug280penetrating the insulation interlayer272to be connected to the impurity region206.

The impurity region206is formed in the substrate200between the neighboring or adjacent gate electrodes214. The impurity region206can include a first impurity region202and a second impurity region204to be provided as a source/drain region of a lightly doped drain (LDD) structure. Here, the second impurity region204can have an impurity concentration that is substantially greater than that of the first impurity region202.

The insulation interlayer272is formed on the substrate200to have a sufficient height such that the gate structure252is sufficiently covered with the insulation interlayer272. A contact hole276is formed in the insulation interlayer272to selectively expose the substrate200between the gate structures252. For example, an upper portion of the contact hole276can have a width substantially greater than that of a lower portion of the contact hole276. The contact or plug280is formed in the contact hole276to be connected to the impurity region206. Here, an upper portion of the plug280can have a width substantially greater than that of a lower portion of the plug280.

In example embodiments, the upper portion of the gate electrode214can have a width that is substantially smaller than that of the lower portion of the gate electrode214, and the protecting layer pattern232is formed on the central portion of the gate electrode214. Therefore, even in situations where the gate electrodes214are formed relatively close to each other, a shorting failure between the gate electrode214and the plug280can be prevented.

FIGS. 14 to 20are cross-sectional views illustrating a method of forming a gate structure in accordance with example embodiments. InFIGS. 14 to 20, the process of forming the gate structure252is substantially the same as or substantially similar to the process described above with reference toFIGS. 3 to 9, with the exception being the steps of forming the impurity region206and the second spacer242.

Referring toFIG. 14, after a first insulation layer (not illustrated) is formed on a substrate on which a gate insulation layer pattern210and a preliminary gate electrode212are formed, the first insulation layer is partially etched to form a first spacer222so that the first spacer remains on only a lower sidewall of the preliminary gate electrode212.

Impurities are implanted into the portions of the substrate200exposed between the neighboring preliminary gate electrodes212at a low impurity concentration to form a first impurity region202. In this case, the first spacer222can prevent impurities from diffusing excessively into the substrate100under the preliminary gate electrode212during the implantation process.

Referring toFIG. 15, a portion of the preliminary gate electrode212exposed by the first spacer222is selectively oxidized to form a protecting layer230. For example, the preliminary gate electrode212can be partially oxidized by a thermal oxidation process or a plasma oxidation process to form the protecting layer230. As silicon included in the upper and central portions of the preliminary gate electrode212exposed by forming the first spacer222are consumed by the selective oxidation process, silicon oxide is grown to form the protecting layer230. Silicon oxide can also be grown from the portions of the substrate200that are exposed between the preliminary gate electrodes212during the selective oxidation process.

By the selective oxidation process, the protecting layer230is grown to a first width (L1) inward from the former boundary of the preliminary gate electrode212and is grown to a second width (L2) outward from the former boundary of the preliminary gate electrode212. Here, a ratio between the first width (L1) and the second width (L2) can be about 1.0:0.6 to about 1.0:0.9. For example, when the first width (L1) can be about 5 nm, the second width (L2) can be about 3 nm. By forming the protecting layer230, the preliminary gate electrode212is changed into a gate electrode214including a lower portion having a first width (W1) and an upper portion having a second width (W2) that can be substantially smaller than the first width (W1).

Referring toFIG. 16, a second insulation layer240is formed on the substrate200and the gate electrode214. The second insulation layer240is patterned by a subsequent process to form a second spacer242(SeeFIG. 17). For example, the second insulation layer240can be formed using silicon nitride or silicon oxynitride by a chemical vapor deposition process.

Referring toFIG. 17, the second insulation layer240is anisotropically etched to form the second spacer242that exposes an upper portion of the protecting layer230. That is, the second spacer242is formed on the first spacer222and a sidewall of the protecting layer230. During an etching process for forming the second spacer242, the portion of the second insulation layer240that lies on the substrate200is contemporaneously removed. In some example embodiments, as process conditions of the etching process for forming the second spacer242, such as an etching rate, an etching gas or etching solution and an etching time can be properly controlled, the second insulation layer240on the upper portion of the protecting layer230can be efficiently removed. Thus, the second spacer242is formed only at a side of or on the first spacer222and the sidewall of the protecting layer230, and the upper portion of the protecting layer230is exposed by the second spacer242.

Impurities are implanted into the substrate200exposed between the gate electrodes214on which the second spacer242is formed to form a second impurity region204having a high impurity concentration. Accordingly, an impurity region206including the first impurity region202and the second impurity region204is formed in the substrate200to be provided as a source/drain region of an LDD structure.

Referring toFIG. 18, the upper portion of the protecting layer230exposed by the second spacer242is partially removed to form a protecting layer pattern232on the central sidewall of the gate electrode214. In one embodiment, the protecting layer pattern232can be formed by a wet etching process. For example, the protecting layer230can be partially removed using an etching solution including hydrogen fluoride (HF). In this case, silicon oxide that is formed on the substrate200between the gate electrodes214is contemporaneously removed by the etching process for forming the protecting layer pattern232.

Thus, a first gate structure250including the gate insulation layer pattern210on the substrate200, the gate electrode214on the gate insulation layer pattern210, the first spacer222on the lower sidewall of the gate electrode214, the protecting layer pattern232on the central sidewall of the gate electrode214, and the second spacer242on the sidewall of the first spacer222and the sidewall of the protecting layer pattern232is formed.

Referring toFIG. 19, a metal silicide pattern262(SeeFIG. 20) can be further formed on the gate electrode214exposed by the protecting layer pattern232and the impurity region206to improve conductivity of the gate electrode214. However, the details of the process of forming the metal silicide pattern262are well known in the art and can be omitted in this example for simplification. For example, a metal layer260can be formed on the gate electrode214and the substrate200using a metal having a high melting point, such as cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd) or titanium (Ti), and then the substrate200in which the metal layer260is formed is thermally treated to form the metal silicide pattern262.

In another example embodiment, a capping layer (not illustrated) can be further formed on the metal layer260to prevent a surface of the metal layer260from oxidizing during a subsequent thermal treatment process. For example, the capping layer can be formed using titanium (Ti) and/or titanium nitride (TiNx). However, the details of the process of forming the capping layer, can be omitted for simplification.

Referring toFIG. 20, the unreacted metal layer260is removed to complete the metal silicide pattern262on the gate electrode214exposed by the protecting layer pattern232and the impurity region206. For example, the unreacted metal layer260can be removed by a stripping process.

By the above-mentioned processes, a second gate structure252including the gate electrode214is formed on the substrate200. The gate electrode214includes the lower portion having the first width (W1), the central portion having the second width (W2) substantially smaller than the first width (W1) and the upper portion having a third width (W3). Here, the upper portion of the gate electrode214includes the metal silicide pattern262, and thus the upper portion of the gate electrode214has the third width (W3) substantially smaller than the first width (W1) and substantially greater than the second width (W2).

FIGS. 21 and 22are cross-sectional views illustrating a method of manufacturing a semiconductor device including a gate structure in accordance with example embodiments. InFIGS. 21 and 22, processes of forming the gate structure252on the substrate200are substantially the same as or substantially similar to those described with reference toFIGS. 14 to 19.

Referring toFIG. 21, after forming the gate structure252on the substrate200, an etch stop layer270is formed on the second gate structure252and the substrate200. The etch stop layer270can be formed conformally on sidewalls and an upper surface of the second gate structure252, for example using silicon nitride by a chemical vapor deposition process.

An insulation interlayer272is formed to cover the second gate structures252, completely filling a gap between the second gate structures252. An upper surface of the insulation interlayer272can be planarized by a planarization process such as a chemical mechanical polishing process and/or an etch-back process. The insulation interlayer272can be formed, for example, using silicon oxide by a chemical vapor deposition process.

Referring toFIG. 22, after the insulation interlayer272is partially etched to form a contact hole276that exposes the impurity region206, a plug280is formed in the contact hole276to be connected to the impurity region206. Thus, a semiconductor device290including the gate structure252on the substrate200, the impurity region206formed in the substrate between the gate structures252and the plug180electrically connected to the impurity region206is completed.

In a conventional semiconductor device, since a distance between adjacent or neighboring gate electrodes is reduced in accordance with a reduction of the fabrication design rule, and thus, an alignment margin of the plug is decreased, shorting problems between the plug and the gate electrode can frequently occur. However, according to example embodiments, the upper portion of the gate electrode214has a width smaller than the lower portion of the gate electrode214, and the central portion of the gate electrode214is covered with the protecting layer pattern232. Accordingly, even though the gate electrodes114are arranged to be spaced apart from each other by a reduced distance, the plug280can be prevented from contacting the gate electrode214, to thereby prevent shorting problems between the gate electrode214and the plug280.

According to example embodiments, because the gate electrode where the upper portion of the gate electrode has a width substantially smaller than the lower portion of the gate electrode is provided, and because the protecting layer pattern is formed on the central sidewall of the gate electrode, even though the contact or the plug is positioned between the gate electrodes that are spaced apart from each other by a reduced distance according to a reduction of the fabrication design rule, the plug can be prevented from contacting the gate electrode, to thereby improve the resulting reliability of the semiconductor device that includes the gate electrode and the plug.