Semiconductor package

A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2020-0103753 filed on Aug. 19, 2020 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package.

2. Description of Related Art

Semiconductor devices require high-capacity data processing while the volume thereof is becoming smaller. Accordingly, to apply a package-on-package (POP) of a semiconductor package including different semiconductor chips, a pad connected to an upper package is formed on an upper surface of a lower package, thereby forming a connection bump connecting the lower package and the upper package to each other.

SUMMARY

It is an aspect to provide a semiconductor package having improved reliability.

According to an aspect of one or more example embodiments, there is provided a semiconductor package includes a first semiconductor package including a first package substrate including a redistribution layer, a first semiconductor chip disposed on the first package substrate and electrically connected to the redistribution layer, a molded member disposed on the first package substrate and covering the first package substrate and the first semiconductor chip, a wiring structure disposed on the molded member and having an upper surface on which a plurality of upper pads are arranged, and a frame disposed between the first package substrate and the wiring structure, having a through-hole in which the first semiconductor chip is disposed, the frame electrically connecting the redistribution layer and the plurality of upper pads; a second semiconductor package disposed on the first semiconductor package, and including a second package substrate having a lower surface on which a plurality of lower redistribution pads are arranged, and a second semiconductor chip disposed on the second package substrate and electrically connected to the plurality of lower redistribution pads; and a plurality of connection bumps electrically connecting the plurality of upper pads and the plurality of lower redistribution pads. The plurality of upper pads include a first upper pad adjacent to a corner of the upper surface of the wiring structure, and a second upper pad closer to a center of the upper surface of the wiring structure than the first upper pad, the plurality of connection bumps include a first connection bump disposed in a position corresponding to the first upper pad and a second connection bump disposed in a position corresponding to the second upper pad, a first width of the first upper pad is greater than a second width of the second upper pad, a maximum width of the first connection bump is greater than a maximum width of the second connection bump, and the wiring structure further includes a contact layer disposed on the first upper pad between the first upper pad and the first connection bump.

According to another aspect of one or more example embodiments, there is provided a semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip, the wiring structure having an upper surface on which a plurality of pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the plurality of pads; and a passivation layer disposed on the wiring structure and having a plurality of openings at least partially exposing a region of each of the plurality of pads. The plurality of pads include a first pad adjacent to a corner of an upper surface of the wiring structure, and a second pad closer to a center of the upper surface of the wiring structure than the first pad, a first width of the first pad is greater than a second width of the second pad, and the semiconductor package further includes a contact layer disposed on the first pad in an opening of the plurality of openings that at least partially exposes the region of the first pad.

According to yet another aspect of one or more example embodiments, there is provided a semiconductor package includes a first semiconductor package; a second semiconductor package disposed on the first semiconductor package; and a plurality of connection bumps electrically connecting the first and second semiconductor packages. The first semiconductor package includes a first package substrate including a redistribution layer, a first semiconductor chip disposed on the first package substrate and electrically connected to the redistribution layer, a wiring structure disposed on the semiconductor chip and having an upper surface on which a plurality of upper pads are arranged, and a vertical connection structure disposed on the first package substrate and electrically connecting the redistribution layer and the plurality of upper pads, the second semiconductor package includes a second package substrate having a lower surface on which a plurality of lower redistribution pads are arranged, and a second semiconductor chip disposed on the second semiconductor package and electrically connected to the plurality of lower redistribution pads, the plurality of connection bumps include a first connection bump that is at least a portion of outermost connection bumps arranged along edges of the wiring structure and the second package substrate, and a second connection bump, other than the first connection bump, and a first thickness of the first connection bump in a vertical direction on the wiring structure is less than a second thickness of the second connection bump.

DETAILED DESCRIPTION

FIG.1is a schematic plan view of a semiconductor package according to example embodiments.FIG.1is a plan view as viewed from the top of a first semiconductor package100A.FIG.2is a schematic cross-sectional view of the semiconductor package ofFIG.1, according to example embodiments.FIG.2is a cross-sectional view illustrating an area taken along line I-I″ ofFIG.1.FIGS.3A and3Bare partially enlarged views of the semiconductor package ofFIG.2, according to example embodiments.FIG.3Ais an enlarged view of area “A” ofFIG.2.FIG.3Bis an enlarged view of area13′ ofFIG.2.

Referring toFIGS.1to3B, a first semiconductor package100A may include a vertical connection structure110, a first semiconductor chip120, a molded member130, a first package substrate140including a redistribution layer142, and a wiring structure170that includes a plurality of upper pads173and a contact layer175disposed on at least a portion of the plurality of upper pads173. In an example embodiment, the first semiconductor package100A may include a second passivation layer180covering a portion of the wiring structure170.

In an example embodiment, the first semiconductor package100A may further include a first passivation layer150disposed on the first package substrate140and protecting the redistribution layer142, and a first metal bump160disposed on the first passivation layer150.

The vertical connection structure110is disposed on one surface of the first package substrate140and electrically connects the redistribution layer142and the plurality of upper pads173. For example, the vertical connection structure110may electrically connect the redistribution layer142and the plurality of upper pads173by penetrating through at least a portion of the molded member130. The vertical connection structure110may be directly disposed on the upper surface of the first package substrate140. The vertical connection structure110may be disposed between the first package substrate140and the wiring structure170. The vertical connection structure110may be a frame including a plurality of insulating layers111aand111b, a plurality of wiring layers112aand112b, and a plurality of wiring vias113aand113b. The frame may include a first insulating layer111ain contact with the first package substrate140, a first wiring layer112ain contact with the first package substrate140and buried in the first insulating layer111a, a second wiring layer112bdisposed on the opposite side of a side of the first insulating layer111ain which the first wiring layer112ais buried, a second insulating layer111bdisposed on the first insulating layer111aand covering the second wiring layer112b, and a third wiring layer112cdisposed on the opposite side of a side of the second insulating layer111bin which the second wiring layer112bis buried. The first to third wiring layers112a,112band112cmay be electrically connected to the redistribution layer142. The first wiring via113amay penetrate through the first insulating layer111aand may electrically connect the first wiring layer112aand the second wiring layer112b. The second wiring via113bmay penetrate through the second insulating layer111band may electrically connect the second wiring layer112band the third wiring layer112c.

The vertical connection structure110may further improve the rigidity of the semiconductor package according to a material of the insulating layers111aand111b, and may secure uniform thickness of the molded member130. The vertical connection structure110may have a through-hole110H penetrating through the insulating layers111aand111b. The first semiconductor chip120may be disposed in the through-hole110H. For example, the through-hole110H may accommodate the first semiconductor chip120therein. In some example embodiments, the through-hole110H may have a wall surface surrounding the first semiconductor chip120, but the configuration is not limited thereto.

A material of the insulating layers111aand111bof the vertical connection structure110is not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, Ajinomoto Build-up Film (ABF), or the like may be used. Alternatively, a material in which the above-described resin may be impregnated in glass fibers (Glass Fiber, Glass Cloth, Glass Fabric) together with an inorganic filler, for example, a prepreg may be used.

The wiring layers112a,112band112cmay provide an upper/lower electrical connection path of the first semiconductor package100A together with the wiring vias113aand113b, and may serve as a structure that redistributes the connection pad120P. The wiring layers112a,112band112cmay include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers112a,112band112cmay include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, and a signal pattern depending on the corresponding layer. The signal pattern may include various signals, for example, data signals, excluding a ground (GND) pattern, a power (PWR) pattern, and the like. In some example embodiments, the ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the wiring layers112a,112band112cmay respectively include various types of via pads. The wiring layers112a,112band112cmay be formed by a known plating process, and may be each formed of a seed layer and a conductor layer.

The wiring vias113aand113belectrically connect the wiring layers112a,112band112cformed on different layers, and as a result, an electrical path may be formed in the vertical connection structure110. The wiring vias113aand113bmay include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring vias113aand113bmay include a signal via, a power via, and a ground via, and in some example embodiments the power via and the ground via may be the same via. The wiring vias113aand113bmay be filled-type vias filled with a metallic material, or may be conformal-type vias in which a metallic material is formed along a wall surface of the via hole. The wiring vias113aand113bmay be formed by a plating process, and may be formed of a seed layer and a conductor layer.

The first semiconductor chip120may be disposed on the first package substrate140. The first semiconductor chip120may be electrically connected to the redistribution layer142. The first semiconductor chip120may have an active surface on which the connection pads120P are disposed, and an inactive surface that is opposite to the active surface. The first semiconductor chip120may be a logic chip or a memory chip. For example, the first semiconductor chip120may include a Large scale integration (LSI), a logic circuit, a CMOS imaging sensor (CIS), a memory device such as DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, MRAM, High bandwidth memory (HBM), Hybrid memory cubic (HMC) or the like, Microelectromechanical System (MEMS) device, or the like. Separate connection members may be disposed between the connection pads120P and the redistribution layer142. In some example embodiments, the connection members may include a solder ball or a copper pillar. For example, the first semiconductor chip120may be mounted on the first package substrate140in a flip-chip bonding method. In this case, an underfill resin surrounding the connection members may be formed between the first semiconductor chip120and the first package substrate140.

The molded member130is disposed on the first package substrate140and may cover at least portions of the vertical connection structure110and the first semiconductor chip120. The molded member130may include an insulating material, and as the insulating material, a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with a reinforcing material such as an inorganic filler, in detail, ABF, FR-4, BT, resin, or the like may be used. In addition, a molding material such as EMC or a photosensitive material such as Photo Imageable Encapsulant (PIE) may also be used.

The first package substrate140may include an insulating layer141, the redistribution layer142disposed on the insulating layer141, and redistribution vias143penetrating through the insulating layer141and electrically connecting the redistribution layer142, the vertical connection structure110and the connection pads120P of the first semiconductor chip120. The first package substrate140may redistribute the connection pads120P of the first semiconductor chip120to a fan-out area, and may physically and/or electrically connect the connection pads120P externally through the first metal bump160. The number of the insulating layers141, the redistribution layers142, and the redistribution vias143may be greater or less than those illustrated in the drawings.

The insulating layer141of the first package substrate140may include an insulating material. For example, a photoimageable dielectric (PID) material may be used as the insulating material, and in this case, a fine pitch may be implemented through a photo via. The boundary of the insulating layers141of the first package substrate140may be distinguished, or may be unclear.

The redistribution layer142may redistribute the connection pads120P of the first semiconductor chip120to be electrically connected to the vertical connection structure110and the first metal bump160. For example, the redistribution layer142may include a connection pattern portion electrically connecting the connection pad120P. The redistribution layers142may be connected to each other via an area not illustrated in the drawing.

The redistribution layer142may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layer142may perform various functions according to a design. For example, the redistribution layer142may include a ground (GND) pattern, a power (PWR) pattern, a signal pattern, and the like. In some example embodiments, the ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the redistribution layer142may include a redistribution via pad and a connection bump pad. The redistribution layer142may be formed through a plating process, and may include a seed layer and a conductor layer.

The redistribution vias143may electrically connect the redistribution layers142formed on different layers. The redistribution vias143may electrically connect the connection pad120P of the first semiconductor chip120and the vertical connection structure110to the redistribution layer142. The redistribution vias143may physically contact the connection pad120P in example embodiments in which the first semiconductor chip120is a bare die.

The redistribution vias143may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution vias113may include a signal via, a power via, a ground via, and the like, and in some example embodiments, the power via and the ground via may be the same via. The redistribution vias113may be filled-type vias filled with a metallic material, or may be conformal-type vias in which a metallic material is formed along a wall surface of the via hole. The redistribution vias143may be formed through a plating process, and may be formed of a seed layer and a conductor layer.

The first passivation layer150is configured to protect the first package substrate140from physical and chemical damage. The first passivation layer150may include a thermosetting resin. In some example embodiments, the first passivation layer150may include, for example, ABF, but the configuration thereof is not limited thereto. For example, in some example embodiments, the first passivation layer150and may include other types of insulating materials. The first passivation layer150may have an opening that exposes at least a portion of a lowermost redistribution layer142among the redistribution layers142. In some embodiments, the opening may be tens of openings to tens of thousands of openings, and in other example embodiments may have a number of openings more or less than tens to tens of thousands. In some example embodiments, each opening may be formed of a plurality of holes.

The first metal bump160may be formed in an opening of the first passivation layer150to be electrically connected to an exposed lowermost redistribution layer142.

The first metal bump160is a component for physically and/or electrically connecting the first semiconductor package100A externally. For example, the first semiconductor package100A may be mounted on a main board of an electronic device through the first metal bump160. The first metal bump160may be disposed on the first passivation layer150. The first metal bump160may be formed of a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). In some example embodiments, the first metal bump160may include solder, but the material is not particularly limited.

The first metal bump160may be a land, a ball, a pin, or the like. The first metal bump160may be formed of a multilayer or a single layer. When the first metal bump160is formed of multiple layers, the first metal bump160may include a copper pillar and solder, and when formed as a single layer, tin-silver solder or copper may be included, but example embodiments are not limited thereto. The number, spacing, arrangement shape, and the like of the first metal bumps160are not particularly limited, and in various example embodiments may be sufficiently modified.

At least one of the first metal bumps160may be disposed in the fan-out area. The fan-out area refers to a region outside of the region in which the first semiconductor chip120is disposed. A fan-out package is more reliable than a fan-in package, may implement multiple I/O terminals, and facilitates3D interconnection. In addition, compared to a Ball Grid Array (BGA) package and a Land Grid Array (LGA) package, the package thickness of the fan-out package may be relatively reduced, and the price competitiveness is excellent.

The wiring structure170may be disposed on the upper surface of the molded member130. The wiring structure170may include a plurality of vertical connection vias171penetrating through a portion of the molded member130, and a plurality of upper pads173disposed on the vertical connection vias171, respectively. The wiring structure170may include an upper surface on which a plurality of upper pads173are arranged. In an example embodiment, the wiring structure170may further include a contact layer175disposed on a first upper pad173aadjacent to a corner of the upper surface of the wiring structure170, among the plurality of upper pads173. For example, in some example embodiments, the contact layer175may be disposed only on first upper pads173adisposed in four corners of the first semiconductor package100A.

The vertical connection vias171are disposed on the vertical connection structure110and may be electrically connected to the vertical connection structure110. The vertical connection vias171may be disposed on an uppermost third wiring layer112camong the wiring layers. The wiring structure170includes a line-shaped redistribution pattern connected to the connection vias171that is connected to the third wiring layer112c, and a partial region (mainly an end portion) of the redistribution pattern may be provided as the plurality of upper pads173. The vertical connection vias171may be formed by a plating process together with a redistribution pattern, and in some example embodiments may include a seed layer and a conductor layer.

The plurality of upper pads173may be electrically connected to the vertical connection structure110through the vertical connection vias171. A partial region of the plurality of upper pads173may be covered by the second passivation layer180disposed on the molded member130. The redistribution pattern having the plurality of upper pads173may provide a redistribution circuit on one surface of the first semiconductor package100A. The redistribution pattern and the plurality of upper pads173may include a conductive material. For example, the conductive material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution pattern and the plurality of upper pads173may perform various functions, and for example, may include a ground (GND) pattern, a power (PWR) pattern, or a signal pattern.

The plurality of upper pads173may include a first upper pad173aadjacent to a corner of the upper surface of the wiring structure170, and a second upper pad173bcloser to the center of the upper surface of the wiring structure170than the first upper pad173a. In some example embodiments, the first upper pads173amay be disposed adjacent to corners of the upper surface of the wiring structure170, and the second upper pads173bmay be disposed between the first upper pads173a. In other example embodiments, the first upper pads173amay be at least a portion of outermost upper pads173arranged along the edge of the upper surface of the wiring structure170, and the second upper pads173bmay be disposed further inside than the first upper pads173a. As illustrated inFIG.1, the first upper pads173amay be upper pads disposed at corners, among outermost upper pads173arranged along the edge of the upper surface of the wiring structure170, and the second upper pads173bmay be upper pads except for the first upper pads173a, among the plurality of upper pads173. In some example embodiments, the first upper pads173amay be disposed on the outermost side of the wiring structure170, and the second upper pads173bmay be adjacent to the first upper pads173a.

A first width a1of the first upper pad173amay be wider than a second width a2of the second upper pad173b, as illustrated inFIG.1. In an example embodiment, the first width a1of the first upper pad173amay be about 5% to about 10% wider than the second width a2of the second upper pad173b. In an example embodiment, the first width a1of the first upper pad173amay be about 10 μm to about 40 μm wider than the second width a2of the second upper pad173b. In an example embodiment, the first width a1of the first upper pad173amay range from about 250 μm to about 270 μm. In an example embodiment, the second width a2of the second upper pad173bmay range from about 230 μm to about 250 μm. When the first width a1of the first upper pad173ais wider than the second width a2of the second upper pad173b, a package-on-package (POP) between the first semiconductor package100A and another semiconductor package may increase connection reliability.

The contact layer175may be disposed on the first upper pad173a. The contact layer175may be disposed in a first opening180aH of the second passivation layer180covering a partial area of the first upper pad173a(seeFIG.3A). In some example embodiments, the distance D1from the lower surface of the first upper pad173ato the upper surface of the contact layer175may be greater than a distance D2from the lower surface of the second upper pad173bto the upper surface of the second upper pad173b. In an example embodiment, the upper surface of the contact layer175may be disposed at a lower level than the upper surface of the second passivation layer180. The side surface of the contact layer175may be surrounded by the second passivation layer180. The contact layer175may not be disposed on the second upper pad173b. The contact layer175may include a low melting point metal, for example, tin (Sn) or an alloy (Sn—Ag—Cu) including tin (Sn). A thickness t1of the contact layer175in the vertical direction on the first package substrate140may range from about 5 μm to about 15 μm.

The second passivation layer180may be disposed on the wiring structure170. The second passivation layer180may be disposed on the molded member130. The second passivation layer180may have an opening that exposes at least a portion of the wiring structure170. In an example embodiment, the opening may have lower and upper widths different from each other. In an example embodiment, a width of an upper portion of the opening may be wider than a width of a lower portion of the opening. For example, in some example embodiments, W3>W1and W4>W2. The second passivation layer180may cover a partial region of each of the plurality of upper pads173. The second passivation layer180may cover a side surface and a portion of an upper surface of each of the plurality of upper pads173.

The second passivation layer180is a component for protecting the wiring structure170from physical and chemical damage. In some example embodiments, the second passivation layer180may include a thermosetting resin, for example, ABF, but the material is not limited thereto. In some example embodiments, the opening may be provided as tens to tens of thousands of openings.

The opening of the second passivation layer180may include a first opening180aH at least partially exposing a region of the first upper pad173a, and a second opening180bH at least partially exposing a region of the second upper pad173b. For example, the second passivation layer180surrounding a portion of the upper surface and a side surface of the first upper pad173amay have the first opening180aH, and the second passivation layer180surrounding a portion of the upper surface and a side surface of the second upper pad173bmay have the second opening180bH.

In some example embodiments, a first width, which may be an average width of the first opening180aH, may be wider than the second width, which may be an average width of the second opening180bH. In other words, in some example embodiments, the average of W1and W3of a single first opening180aH may be greater than the average of W2and W4of a single second opening180bH. In an example embodiment, the first width of the first upper pad173amay be about 5% to about 10% wider than the second width of the second upper pad173b. A width W1of a lowermost portion of the first opening180aH may be wider than a width W2of a lowermost portion of the second opening180bH. A width W3of an uppermost portion of the first opening180aH may be wider than a width W4of an uppermost portion of the second opening180bH. Accordingly, the first upper pad173amay have a larger area of a region exposed by the second passivation layer180than that of the second upper pad173b. In other example embodiment, the first width, which may be an the average width of the plurality of first openings180aH, may be about 10 μm to about 40 μm wider than the second width, which may be an average width of the plurality of second openings180bH. In other words, in other example embodiments, the average width of the plurality of first openings180aH in the first semiconductor package100A may be greater than the average width of the plurality of second openings180bH in the first semiconductor package100A. In an example embodiment, the width W1of the lowermost portion of the first opening180aH may be in the range of about 225 μm to about 245 μm, and the width W2of the lowermost portion of the second opening180bH may range from about 205 μm to about 220 μm. The width W3of the uppermost portion of the first opening may range from about 240 μm to about 260 μm, and the width W4of the uppermost portion of the second opening may range from about 220 μm to about 240 μm.

FIGS.4A and4Bare schematic partially enlarged views of a semiconductor package according to example embodiments.

Referring toFIGS.4A and4B, in a semiconductor package100B, the wiring structure170may further include a barrier layer174disposed on the upper pads173. The width of the barrier layer174is illustrated to be the same as the upper pads173, but is not limited thereto, and in some example embodiment, the width of the barrier layer174may be less than that of the upper pads173, for example.

The barrier layer174may be disposed between the first upper pad173aand the contact layer175. The barrier layer174disposed on the second upper pad173bmay have an upper surface exposed by the passivation layer180. In an example embodiment, the barrier layer174may be formed of a material different from the material of the upper pads173. The barrier layer174may be formed of, for example, nickel (Ni) or gold (Au). In an example embodiment, the barrier layer174may be a single layer including nickel (Ni) or a multilayer including nickel (Ni) and gold (Au). The barrier layer174may be formed through a plating process.

FIG.5is a schematic plan view of a semiconductor package according to example embodiments.FIG.5is a plan view as viewed from the top of a first semiconductor package100C. InFIG.5, like reference designators refer to like elements described above and repeated description thereof is omitted for conciseness.

Referring toFIG.5, in the first semiconductor package100C, upper pads173may include first upper pads173adisposed along an edge of an upper surface of the first semiconductor package100C, and second upper pads173bdisposed further inside than the first upper pads173a. In the example embodiment illustrated inFIG.5, unlike the first semiconductor package100A ofFIG.1, the first upper pads173ahaving a width relatively wider than that of the second upper pads173bmay be disposed on the entire edge rather than a portion of the edge.

FIG.6is a schematic cross-sectional view of a semiconductor package according to example embodiments.

Referring toFIG.6, in a first semiconductor package100D, a second molded member135disposed on the first molded member130may be further included.

The second molded member135may be an insulating layer disposed on the back side of the semiconductor package100D and on a side close to a surface (inactive surface) on which the connection electrode120P of the semiconductor chip120is not disposed. The second molded member135may be connected to a portion of the upper pads173to cover the redistribution patterns in an area not illustrated. The second molded member135may surround the vertical wiring vias171. The second passivation layer180may be disposed on the second molded member135.

The second molded member135may include an insulating material, and as the insulating material, a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with a reinforcing material such as an inorganic filler, for example, ABF, FR-4, BT, resin, or the like may be used. In an example embodiment, as a material of the second molded member135, a molding material such as EMC may be used, and a photosensitive material such as Photo Imageable Encapsulant (PIE) may be used. The second molded member135may be formed of the same material as the first molded member130or may be formed of a different material.

FIG.7is a schematic cross-sectional view of a semiconductor package according to example embodiments.

Referring toFIG.7, in a semiconductor package100E, a vertical connection structure110may be a conductive post disposed on one surface of the first package substrate140, penetrating through at least a portion of the molding member130and electrically connecting the redistribution layer142and the upper pad173. The vertical connection structure110may include a plurality of conductive posts disposed around (i.e., on sides of) the semiconductor chip120. The conductive post may include a conductive material. The conductive post may be completely filled with a conductive material, and may have, for example, a cylindrical shape or a polygonal column shape. The shape of the conductive post is not particularly limited and may have various shapes.

It is noted that, components having the same reference numerals as inFIGS.1to3Bamong the components illustrated inFIGS.4A to7are similar in structure and function to the components illustrated inFIGS.1to3B, and thus, repeated descriptions thereof have been be omitted for conciseness.

FIG.8is a schematic cross-sectional view of a package-on-package structure according to example embodiments.FIG.8is a cross-sectional view illustrating an area taken along line I-I′ ofFIG.1.

FIGS.9A and9Bare partially enlarged views of the semiconductor package ofFIG.8, according to example embodiments.FIG.9Ais an enlarged view of area ‘C’ ofFIG.8.FIG.9Bis an enlarged view of area ‘D’ ofFIG.8.

Referring toFIGS.8to9B, a semiconductor package300A may include a second semiconductor package200combined with the first semiconductor package100A described with reference toFIGS.1to3B. In other example embodiments, the semiconductor packages100B,100C,100D, and100E according to the example embodiments ofFIGS.4A to7may be applied inFIG.8to a region corresponding to the first semiconductor package100A.

In the semiconductor package300A, the second semiconductor package200may include a second package substrate210including a plurality of lower pads211, a second semiconductor chip220, and an encapsulant230. In addition, the semiconductor package300A may include a plurality of connection bumps240electrically connecting the first semiconductor package100A and the second semiconductor package200. In some example embodiments, the second semiconductor package200may include the plurality of connection bumps240. The semiconductor package300A may further include a metal compound layer S disposed between the first connection bump240aand the contact layer175.

The second package substrate210may include lower redistribution pads211and upper redistribution pads212, which may be electrically connected to components external to the second semiconductor substrate210, on an upper surface and a lower surface thereof, respectively. The second package substrate210may include redistribution patterns connected to the redistribution pads211and212inside of the second package substrate210. The redistribution patterns may redistribute a second connection electrode220P of the second semiconductor chip220to the fan-out area.

The second semiconductor chip220may include second connection electrodes220P, and the second connection electrodes220P may be electrically connected to the second package substrate210by second metal bumps222. In an example, the second semiconductor package200may further include an underfill material223surrounding the second metal bumps222. The underfill material223may be an insulating material including an epoxy resin or the like. The second metal bump222may include a solder ball or a copper pillar.

Unlike illustrated inFIGS.8-9B, in some example embodiments, the second connection electrodes220P of the second semiconductor chip220may directly contact the upper surface of the second package substrate210, and may be electrically connected to the redistribution patterns through internal vias.

The encapsulant230may include a material identical to or similar to the molded member130of the semiconductor package100A.

The second semiconductor package200may be physically/electrically connected to the semiconductor package100A by the connection bumps240. The connection bumps240may be electrically connected to the redistribution patterns inside of the second package substrate210through the lower redistribution pads211on the lower surface of the second package substrate210. Alternatively, the connection bumps240may be electrically connected to redistribution patterns inside of the second package substrate210through an under-bump metal disposed on the lower redistribution pads211on the lower surface of the second package substrate210. Each of the connection bumps240may be formed of a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). In an example embodiment, the connection bump240may be formed of solder or the like, which is only an example, and thus, the material is not limited thereto.

The plurality of connection bumps240may electrically connect the plurality of upper pads173of the first semiconductor package100A and the plurality of lower redistribution pads211of the second semiconductor package200. The plurality of connection bumps240may include first connection bumps240aadjacent to the corners of the upper surface of the wiring structure170, and second connection bumps240bcloser to the center of the upper surface of the wiring structure170than the first connection bumps240a. In some example embodiments, the first connection bumps240amay be disposed at corners of the upper surface of the wiring structure170, and the second connection bumps240bmay be between the first connection bumps240a. The first connection bumps240amay be disposed in a position corresponding to the first upper pads173a, and the second connection bumps240bmay be disposed in a position corresponding to the second upper pads173b. In other example embodiments, the first connection bumps240amay be at least a portion of outermost connection bumps240arranged along the edge of the upper surface of the wiring structure170, and the second connection bumps240bmay be disposed further inside than the first connection bumps240a. The first connection bumps240amay be disposed on the outermost sides of the wiring structure170, and the second connection bumps240bmay be adjacent to the first connection bumps240a. In some example embodiments, the first connection bumps240amay be a portion of the outermost connection bumps arranged along the upper surface of the wiring structure170and the edge of the lower surface of the second package substrate210, and the second connection bumps240bmay be connection bumps excluding the first connection bumps240a, among the plurality of connection bumps240.

The first connection bumps240amay be disposed on the first upper pads173a. The first connection bump240amay be disposed on the contact layer175, and may contact the contact layer175. The first connection bump240amay be disposed between the contact layer175and the lower redistribution pad211. In an example embodiment, the connection bump240may be formed of the same material as the contact layer175, but in other example embodiments may be formed of a different material. In an example embodiment, the connection bump240and the contact layer175may be formed of materials having different compositions. When the first connection bump240acontacts the contact layer175, a metal compound layer S may be formed between the first connection bump240aand the contact layer175. The metal compound layer (S) may be an inter metal compound (IMC).

The second connection bumps240bmay be disposed on the second upper pads173b. The second connection bump240bmay contact the second upper pad173b.

A first width b1, which is a maximum width of the first connection bump240a, may be wider than a second width b2, which is a maximum width of the second connection bump240b. In an example embodiment, the first width b1of the first connection bump240amay be about 5% to about 10% greater than the second width b2of the second connection bump240b. In an example embodiment, the first width b1of the first connection bump240amay be about 10 μm to about 40 μm wider than the second width b2of the second connection bump240b. In an example embodiment, the first width b1of the first connection bump240amay range from about 220 μm to about 240 μm. In an example embodiment, the second width b2of the second connection bump240bmay range from about 200 μm to about 220 μm.

A first thickness T1of the first connection bump240aon a first package substrate140in a vertical direction may be less than a second thickness T2of the second connection bump240b. In an example embodiment, a thickness t1of the contact layer175may be substantially identical to the difference between the first thickness T1of the first connection bump240aand the second thickness T2of the second connection bump240b. Since the contact layer175is disposed below the first connection bump240a, a difference in heights between the first connection bump240aand the second connection bump240bmay be compensated for. The contact layer175is not disposed on the second connection bump240b. The contact layer175is disposed only on the first upper pad173aon which the first connection bump240ais disposed, and thus, distances between the upper surface of the wiring structure170and the second package substrate210may be substantially the same in the outermost area and the inner area. According to an example embodiment, in a package-on-package structure, the connection distances between the first semiconductor package100A and the second semiconductor package200by the connection bump240may be substantially the same.

Referring toFIGS.4A and4Btogether, when the first semiconductor package100B is applied to the lower package, the first connection bump240amay be disposed on the contact layer175and may contact the contact layer175, and the second connection bump240bmay be disposed on the barrier layer174and may contact the barrier layer174.

It is noted that components having the same reference numerals as inFIGS.2to3Bamong the components illustrated inFIGS.8to9B, are similar in structure and function to the components illustrated inFIGS.2to3B, and thus, repeated descriptions thereof will be omitted for conciseness.

FIG.10is a schematic cross-sectional view of a semiconductor package according to example embodiments.

Referring toFIG.10, in a semiconductor package300B having a package-on-package structure, a first semiconductor package100F may include a plurality of semiconductor chips120aand120b, and a second semiconductor package200B may include a semiconductor stacked structure225, and conductive wires W electrically connecting the semiconductor stacked structure225to upper and lower redistribution pads211and212aof a second package substrate210. The semiconductor stacked structure225may include a plurality of semiconductor chips225a,225b, and225csequentially stacked.

Each of the plurality of semiconductor chips120aand120bmay have an active surface on which connection pads120Pa and120Pb are disposed, respectively, and an inactive surface opposite to the active surface. The first semiconductor chip120aand the second semiconductor chip120bof the first semiconductor package100F may include an integrated circuit (IC) in which hundreds to millions of devices are integrated. For example, each of the first semiconductor chip120aand the second semiconductor chip120bmay be a power management integrated circuit (PMIC) or an Application Processor (AP) chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller or the lie, or a volatile memory (e.g., DRAM) chip, non-volatile memory (e.g., ROM) chip, flash memory chip, or a logic chip, etc.

It is noted that components having the same reference numerals inFIGS.2to3Bamong the components illustrated inFIG.10are similar in structure and function to the components illustrated inFIGS.2to3B, and thus, repeated descriptions thereof will be omitted for conciseness.

As set forth above, according to various example embodiments, when a package on package (POP) of a semiconductor package is applied, connection reliability between a lower package and an upper package may be improved.

While various example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.