Semiconductor device packages with electromagnetic interference shielding

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

FIELD OF THE INVENTION

The invention relates generally to semiconductor device packages. More particularly, the invention relates to semiconductor device packages with electromagnetic interference shielding.

BACKGROUND

Semiconductor devices have become progressively more complex, driven at least in part by the demand for enhanced processing speeds and smaller sizes. While the benefits of enhanced processing speeds and smaller sizes are apparent, these characteristics of semiconductor devices also can create problems. In particular, higher clock speeds can involve more frequent transitions between signal levels, which, in turn, can lead to a higher level of electromagnetic emissions at higher frequencies or shorter wavelengths. Electromagnetic emissions can radiate from a source semiconductor device, and can be incident upon neighboring semiconductor devices. If the level of electromagnetic emissions at a neighboring semiconductor device is sufficiently high, these emissions can adversely affect the operation of that semiconductor device. This phenomenon is sometimes referred to as electromagnetic interference (“EMI”). Smaller sizes of semiconductor devices can exacerbate EMI by providing a higher density of those semiconductor devices within an overall electronic system, and, thus, a higher level of undesired electromagnetic emissions at a neighboring semiconductor device.

One way to reduce EMI is to shield a set of semiconductor devices within a semiconductor device package. In particular, shielding can be accomplished by including an electrically conductive casing or housing that is electrically grounded and is secured to an exterior of the package. When electromagnetic emissions from an interior of the package strike an inner surface of the casing, at least a portion of these emissions can be electrically shorted, thereby reducing the level of emissions that can pass through the casing and adversely affect neighboring semiconductor devices. Similarly, when electromagnetic emissions from a neighboring semiconductor device strike an outer surface of the casing, a similar electrical shorting can occur to reduce EMI of semiconductor devices within the package.

While an electrically conductive casing can reduce EMI, the use of the casing can suffer from a number of disadvantages. In particular, the casing is typically secured to an exterior of a semiconductor device package by an adhesive. Unfortunately, the casing can be prone to peeling or falling off, since binding characteristics of the adhesive can be adversely affected by temperature, humidity, and other environmental conditions. Also, when securing the casing to the package, the size and shape of the casing and the size and shape of the package should match within relatively small tolerance levels. This matching of sizes and shapes and associated precision in relative positioning of the casing and the package can render manufacturing operations costly and time consuming. Because of this matching of sizes and shapes, it also follows that semiconductor device packages of different sizes and shapes can require different casings, which can further increase manufacturing cost and time to accommodate the different packages.

It is against this background that a need arose to develop the semiconductor device packages and related methods described herein.

SUMMARY

One aspect of the invention relates to semiconductor device packages with EMI shielding. In one embodiment, a semiconductor device package includes: (1) a substrate unit including (a) an upper surface, (b) a lower surface, (c) a lateral surface disposed adjacent to a periphery of the substrate unit and fully extending between the upper surface and the lower surface of the substrate unit, and (d) a grounding element disposed adjacent to the periphery of the substrate unit and at least partially extending between the upper surface and the lower surface of the substrate unit, the grounding element including an indented portion that is disposed adjacent to the lateral surface of the substrate unit; (2) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including exterior surfaces that include a lateral surface; and (4) an EMI shield disposed adjacent to the exterior surfaces of the package body and the lateral surface of the substrate unit, the EMI shield being electrically connected to the grounding element and being inwardly recessed adjacent to the indented portion of the grounding element.

In another embodiment, the semiconductor device package includes: (1) a substrate unit including (a) a first surface, (b) a second opposing surface, and (c) a grounding element at least partially extending between the first surface and the second opposing surface of the substrate unit, the grounding element including a plated channel remnant and a filler member, the plated channel remnant being inwardly recessed so as to accommodate the filler member, the plated channel remnant and the filler member defining a lateral surface of the grounding element that is disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to the first surface of the substrate unit and electrically connected to the substrate unit; (3) a package body disposed adjacent to the first surface of the substrate unit and covering the semiconductor device, the package body including exterior surfaces; and (4) an EMI shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element, wherein a lateral profile of the semiconductor device package is substantially planar and is substantially orthogonal with respect to the second opposing surface of the substrate unit.

Another aspect of the invention relates to methods of forming semiconductor device packages with EMI shielding. In one embodiment, a method includes: (1) providing a substrate including a grounding via and a core member, the grounding via at least partially extending between an upper surface and a lower surface of the substrate, the grounding via defining a via channel that is substantially filled by the core member; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to the upper surface of the substrate to form a molded structure covering the semiconductor device; (4) forming cutting slits fully extending through the molded structure and the substrate, the cutting slits being aligned with the substrate, such that: (a) the substrate is sub-divided to form a separated substrate unit; (b) the molded structure is sub-divided to form a separated package body disposed adjacent to the substrate unit, the package body including exterior surfaces; and (c) a remnant of the grounding via and a remnant of the core member correspond to a grounding element disposed adjacent to a periphery of the substrate unit, the grounding element including an exposed connection surface; and (5) subsequent to forming the cutting slits, applying an EMI coating to the exterior surfaces of the package body and the connection surface of the grounding element to form an EMI shield.

Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.

DETAILED DESCRIPTION

Definitions

The following definitions apply to some of the aspects described with respect to some embodiments of the invention. These definitions may likewise be expanded upon herein.

As used herein, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a grounding element can include multiple grounding elements unless the context clearly dictates otherwise.

As used herein, the term “set” refers to a collection of one or more components. Thus, for example, a set of layers can include a single layer or multiple layers. Components of a set also can be referred to as members of the set. Components of a set can be the same or different. In some instances, components of a set can share one or more common characteristics.

As used herein, the term “adjacent” refers to being near or adjoining. Adjacent components can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent components can be connected to one another or can be formed integrally with one another.

As used herein, relative terms, such as “inner,” “interior,” “inward,” “inwardly,” “outer,” “exterior,” “outward,” “outwardly,” “upper,” “upwardly,” “lower,” “downwardly,” “vertical,” “vertically,” “lateral,” “laterally,” “above,” and “below,” refer to an orientation of a set of components with respect to one another, such as in accordance with the drawings, but do not require a particular orientation of those components during manufacturing or use.

As used herein, the terms “connect,” “connected,” and “connection” refer to an operational coupling or linking. Connected components can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of components.

As used herein, the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical tolerance levels of the manufacturing operations described herein.

As used herein, the terms “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current, while the terms “electrically non-conductive” and “electrical non-conductivity” refer to a lack of ability to transport an electric current. Electrically conductive materials typically correspond to those materials that exhibit little or no opposition to flow of an electric current, while electrically non-conductive materials typically correspond to those materials within which an electric current has little or no tendency to flow. One measure of electrical conductivity (or electrical non-conductivity) is in terms of Siemens per meter (“S·m−1”). Typically, an electrically conductive material is one having a conductivity greater than about 104S·m−1, such as at least about 105S·m−1or at least about 106S·m−1, while an electrically non-conductive material is one having a conductivity less than about 104S·m−1, such as no greater than about 103S·m−1or no greater than about 102S·m−1Electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, electrical conductivity of a material is defined at room temperature.

Attention first turns toFIG. 1andFIG. 2, which illustrate a semiconductor device package100implemented in accordance with an embodiment of the invention. In particular,FIG. 1illustrates a perspective view of the package100, whileFIG. 2illustrates a cross-sectional view of the package100, taken along line A-A ofFIG. 1.

In the illustrated embodiment, sides of the package100are substantially planar and have a substantially orthogonal orientation so as to define a lateral profile that extends around substantially an entire periphery of the package100. Advantageously, this orthogonal lateral profile allows a reduced overall package size by reducing or minimizing a footprint area of the package100. However, it is contemplated that the lateral profile of the package100, in general, can be any of a number of shapes, such as curved, inclined, stepped, or roughly textured. It is also contemplated that the lateral profile of the package100can be substantially planar, albeit inwardly recessed at a set of locations as further described below.

Referring toFIG. 2, the package100includes a substrate unit102, which includes an upper surface104, a lower surface106, and lateral surfaces142and144disposed adjacent to sides of the substrate unit102and extending between the upper surface104and the lower surface106. In the illustrated embodiment, the lateral surfaces142and144are substantially planar and have a substantially orthogonal orientation with respect to the upper surface104or the lower surface106, although it is contemplated that the shapes and orientations of the lateral surfaces142and144can vary for other implementations. The substrate unit102can be implemented in a number of ways, and includes electrical interconnect to provide electrical pathways between the upper surface104and the lower surface106of the substrate unit102. The electrical interconnect can include, for example, a set of electrically conductive layers that are incorporated within a set of dielectric layers. The electrically conductive layers can be connected to one another by internal vias, and can be implemented so as to sandwich a core formed from a suitable resin, such as one based on bismaleimide and triazine or based on epoxy and polyphenylene oxide. For example, the substrate unit102can include a substantially slab-shaped core that is sandwiched by one set of electrically conductive layers disposed adjacent to an upper surface of the core and another set of electrically conductive layers disposed adjacent to a lower surface of the core. For certain implementations, a thickness of the substrate unit102, namely a distance between the upper surface104and the lower surface106of the substrate unit102, can be in the range of about 0.1 millimeter (“mm”) to about 2 mm, such as from about 0.2 mm to about 1.5 mm or from about 0.4 mm to about 0.6 mm. While not illustrated inFIG. 2, it is contemplated that a solder mask layer can be disposed adjacent to either, or both, the upper surface104and the lower surface106of the substrate unit102.

As illustrated inFIG. 2, the substrate unit102includes grounding elements118aand118b, which are disposed adjacent to a periphery of the substrate unit102. More particularly, the grounding elements118aand118bare disposed substantially at the periphery of the substrate unit102, and are disposed adjacent to the lateral surfaces142and144, respectively. The grounding elements118aand118bare connected to other electrical interconnect included in the substrate unit102and, as further described below, provide electrical pathways to reduce EMI. In the illustrated embodiment, the grounding elements118aand118bare implemented as grounding vias and, more particularly, as remnants of grounding vias in accordance with a set of singulation operations as further described below. Referring toFIG. 2, each of the grounding elements118aand118bincludes an upper via pad remnant146aor146b, which is disposed adjacent to the upper surface104of the substrate unit102, a lower via pad remnant148aor148b, which is disposed adjacent to the lower surface106of the substrate unit102, and a plated channel remnant150aor150b, which extends between the upper via pad remnant146aor146band the lower via pad remnant148aor148b. While the grounding elements118aand118bare illustrated as fully extending between the upper surface104and the lower surface106of the substrate unit102, it is contemplated that the extent of the grounding elements118aand118bcan vary for other implementations.

Still referring toFIG. 2, the grounding elements118aand118binclude connection surfaces S1and S2, respectively, which are lateral surfaces that face away from an interior of the package100and are disposed adjacent to the periphery of the substrate unit102. More particularly, the connection surfaces S1and S2are electrically exposed substantially at the periphery of the substrate unit102, and are electrically exposed adjacent to the lateral surfaces142and144, respectively. In the illustrated embodiment, the connection surfaces S1and S2correspond to electrically exposed surfaces of the upper via pad remnants146aand146b, the lower via pad remnants148aand148b, and the plated channel remnants150aand150b. Advantageously, the relatively large areas of the connection surfaces S1and S2can enhance reliability and efficiency of electrical connections for reducing EMI. The grounding elements118aand118bare formed from a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. For certain implementations, a height H1of the grounding elements118aand118b, namely a vertical extent of the grounding elements118aand118b, can be substantially the same as the thickness of the substrate unit102, and can be in the range of about 0.1 mm to about 2 mm, such as from about 0.2 mm to about 1.5 mm or from about 0.4 mm to about 0.6 mm. A width W1of the grounding elements118aand118b, namely a lateral extent adjacent to the upper surface104or the lower surface106, can be in the range of about 75 micrometer (“μm”) to about 275 μm, such as from about 100 μm to about 250 μm or from about 125 μm to about 225 μm.

As illustrated inFIG. 2, the package100also includes semiconductor devices108a,108b, and108c, which are disposed adjacent to the upper surface104of the substrate unit102, and electrical contacts110a,110b, and110c, which are disposed adjacent to the lower surface106of the substrate unit102. The semiconductor device108bis wire-bonded to the substrate unit102via a set of wires112, which are formed from gold or another suitable electrically conductive material, and the semiconductor devices108aand108care surface mounted to the substrate unit102. In the illustrated embodiment, the semiconductor device108bis a semiconductor chip, while the semiconductor devices108aand108care passive devices, such as resistors, capacitors, or inductors. The electrical contacts110a,110b, and110cprovide input and output electrical connections for the package100, and at least a subset of the electrical contacts110a,110b, and110care electrically connected to the semiconductor devices108a,108b, and108cvia electrical interconnect included in the substrate unit102. In the illustrated embodiment, at least one of the electrical contacts110a,110b, and110cis a ground electrical contact, and is electrically connected to the grounding elements118aand118bvia electrical interconnect included in the substrate unit102. While three semiconductor devices are illustrated inFIG. 2, it is contemplated that more or less semiconductor devices can be included for other implementations, and that semiconductor devices, in general, can be any active devices, any passive devices, or combinations thereof. It is also contemplated that the number of electrical contacts can vary from that illustrated inFIG. 2.

Still referring toFIG. 2, the package100also includes a package body114that is disposed adjacent to the upper surface104of the substrate unit102. In conjunction with the substrate unit102, the package body114substantially covers or encapsulates the grounding elements118aand118b, the semiconductor devices108a,108b, and108c, and the wires112to provide mechanical stability as well as protection against oxidation, humidity, and other environmental conditions. The package body114is formed from a molding material, and includes exterior surfaces, including lateral surfaces120and122disposed adjacent to sides of the package body114. In the illustrated embodiment, the lateral surfaces120and122are substantially planar and have a substantially orthogonal orientation with respect to the upper surface104or the lower surface106, although it is contemplated that the lateral surfaces120and122can be curved, inclined, stepped, or roughly textured for other implementations. Also, the lateral surfaces120and122are substantially aligned or co-planar with the lateral surfaces142and144, respectively. More particularly, this alignment is accomplished while allowing the connection surfaces S1and S2to be electrically exposed, such as by reducing or minimizing coverage of the connection surfaces S1and S2by the package body114. For other implementations, it is contemplated that the shape of the lateral surfaces120and122and their alignment with the lateral surfaces142and144can be varied from that illustrated inFIG. 2, while allowing the connection surfaces S1and S2to be at least partially electrically exposed.

As illustrated inFIG. 1andFIG. 2, the package100further includes an EMI shield124that is disposed adjacent to the exterior surfaces of the package body114, the connection surfaces S1and S2of the grounding elements118aand118b, and the lateral surfaces142and144of the substrate unit102. The EMI shield124is formed from an electrically conductive material, and substantially surrounds the semiconductor devices108a,108b, and108cwithin the package100to provide protection against EMI. In the illustrated embodiment, the EMI shield124includes an upper portion126and a lateral portion128, which extends around substantially the entire periphery of the package body114and defines the orthogonal lateral profile of the package100. As illustrated inFIG. 2, the lateral portion128extends downwardly from the upper portion126and along the lateral surfaces142and144of the substrate unit102, and includes a lower end that is substantially aligned or co-planar with the lower surface106of the substrate unit102. However, it is contemplated that the extent of the lateral portion128and the alignment of its lower end with the lower surface106can be varied for other implementations.

As illustrated inFIG. 2, the EMI shield124is electrically connected to the connection surfaces S1and S2of the grounding elements118aand118b. When electromagnetic emissions radiated from an interior of the package100strike the EMI shield124, at least a portion of these emissions can be efficiently grounded via the grounding elements118aand118b, thereby reducing the level of emissions that can pass through the EMI shield124and adversely affect neighboring semiconductor devices. Similarly, when electromagnetic emissions from a neighboring semiconductor device strike the EMI shield124, a similar grounding can occur to reduce EMI of the semiconductor devices108a,108b, and108cwithin the package100. During operation, the package100can be disposed on a printed circuit board (“PCB”) and electrically connected to the PCB via the electrical contacts110a,110b, and110c. As previously described, at least one of the electrical contacts110a,110b, and110cis a ground electrical contact, and the ground electrical contact can be electrically connected to a ground voltage provided by the PCB. Grounding of electromagnetic emissions incident upon the EMI shield124can occur through an electrical pathway including the grounding elements118aand118b, other electrical interconnect included in the substrate unit102, and the ground electrical contact. Because the lower end of the EMI shield124is substantially aligned with the lower surface106of the substrate unit102, the lower end also can be electrically connected to a ground voltage provided by the PCB, thereby providing an alternative electrical pathway for grounding undesired electromagnetic emissions. Alternatively, or in conjunction, the lower via pad remnants148aand148bcan be electrically connected to a ground voltage provided by the PCB.

In the illustrated embodiment, the EMI shield124is a conformal shield that is formed as a set of layers or films. Advantageously, the EMI shield124can be formed adjacent to and in direct contact with an exterior of the package100without the use of an adhesive, thereby enhancing reliability and resistance to temperature, humidity, and other environmental conditions. Also, the conformal characteristics of the EMI shield124allow similar EMI shields and similar manufacturing operations to be readily applied to semiconductor device packages of different sizes and shapes, thereby reducing manufacturing cost and time to accommodate the different packages. For certain implementations, a thickness of the EMI shield124can be in the range of about 1 μm to about 500 μm, such as from about 1 μm to about 100 μm, from about 1 μm to about 50 μm, or from about 1 μm to about 10 μm. Such reduced thickness of the EMI shield124, relative to a typical casing, allows a reduced overall package size, and is a further advantage of the illustrated embodiment.

Attention next turns toFIG. 3A, which illustrates an enlarged, cross-sectional view of a portion of the package100ofFIG. 1andFIG. 2. In particular,FIG. 3Aillustrates a particular implementation of the EMI shield124that is disposed adjacent to the package body114.

As illustrated inFIG. 3A, the EMI shield124is multi-layered and includes an inner layer300, which is disposed adjacent to the package body114, and an outer layer302, which is disposed adjacent to the inner layer300and is exposed at the exterior of the package100. In general, each of the inner layer300and the outer layer302can be formed from a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. For example, each of the inner layer300and the outer layer302can be formed from aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel, or a combination thereof. The inner layer300and the outer layer302can be formed from the same electrically conductive material or different electrically conductive materials. For example, a metal, such as nickel, can be selected for both the inner layer300and the outer layer302. In some instances, different electrically conductive materials can be selected for the inner layer300and the outer layer302to provide complementary functionalities. For example, a metal with a higher electrical conductivity, such as aluminum, copper, gold, or silver, can be selected for the inner layer300to provide EMI shielding functionality. On the other hand, a metal with a somewhat lower electrical conductivity, such as nickel, can be selected for the outer layer302to protect the inner layer300against oxidation, humidity, and other environmental conditions. In this case, the outer layer302also can contribute to the EMI shielding functionality, while providing the protection functionality. While two layers are illustrated inFIG. 3A, it is contemplated that more or less layers can be included for other implementations.

Attention next turns toFIG. 3BandFIG. 3C, which illustrate an enlarged, perspective view of a portion of the package100ofFIG. 1andFIG. 2. In particular,FIG. 3Billustrates one particular implementation of the grounding element118b, whileFIG. 3Cillustrates another particular implementation of the grounding element118b. For ease of presentation, the following features are described with reference to the grounding element118bthat is disposed adjacent to the lateral surface144of the substrate unit102, although it is contemplated that the features can be similarly applicable to other grounding elements of the package100, such as the grounding element118a.

Referring first toFIG. 3B, the grounding element118bis implemented as a remnant of a grounding via in accordance with a set of singulation operations, and includes the upper via pad remnant146b, the lower via pad remnant148b, and the plated channel remnant150b. The plated channel remnant150bcorresponds to an indented portion of the grounding element118b, and is inwardly recessed relative to the lateral surface144of the substrate unit102. More particularly, the plated channel remnant150bis inwardly recessed so as to define a cutout or a groove, which includes a lateral surface that is curved in a substantially concave manner and is electrically exposed to allow electrical connection to the EMI shield124. As illustrated inFIG. 3B, the upper via pad remnant146b, the lower via pad remnant148b, and the plated channel remnant150binclude lateral surfaces that are substantially planar and are substantially aligned or co-planar with the lateral surface144of the substrate unit102, and the connection surface S2of the grounding element118bincludes the substantially concave, lateral surface of the plated channel remnant150bas well as the substantially planar, lateral surfaces of the upper via pad remnant146b, the lower via pad remnant148b, and the plated channel remnant150b. Advantageously, the inward recessing of the plated channel remnant150bprovides a relatively large area of the connection surface S2, thereby enhancing reliability and efficiency of electrical connections for reducing EMI. Still referring toFIG. 3B, formation of the EMI shield124yields the orthogonal lateral profile of the package100that is substantially planar, albeit inwardly recessed at a particular set of locations. In particular, the EMI shield124conformally coats the connection surface S2, which includes the substantially concave, lateral surface of the plated channel remnant150, such that the lateral portion128of the EMI shield124is inwardly recessed adjacent to the plated channel remnant150.

Turning next toFIG. 3C, the grounding element118bis also implemented as a remnant of a grounding via in accordance with a set of singulation operations, and includes the upper via pad remnant146b, the lower via pad remnant148b, and the plated channel remnant150b. Here, the grounding element118balso includes a filler or plug member304, which is accommodated by and substantially fills the cutout defined by the plated channel remnant150b. As further described below, the filler member304is implemented as a remnant of a core member that is accommodated by and substantially fills a via channel defined by the grounding via, and carrying out a set of singulation operations yields a lateral surface of the filler member304that is substantially planar and is electrically exposed to allow electrical connection to the EMI shield124. More particularly, the lateral surface of the filler member304is substantially aligned or co-planar with the lateral surface144of the substrate unit102. The filler member304can be formed from a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material, in which case the connection surface S2of the grounding element118bincludes the substantially planar, lateral surface of the filler member304as well as the substantially planar, lateral surfaces of the upper via pad remnant146b, the lower via pad remnant148b, and the plated channel remnant150b. Advantageously, the inclusion of an electrically conductive, filler member304provides a relatively large area of the connection surface S2as well as improved structural rigidity for the grounding element118b, thereby enhancing reliability and efficiency of electrical connections for reducing EMI. It is also contemplated that the filler member304can be formed from an electrically non-conductive material, in which case the connection surface S2of the grounding element118bincludes the substantially planar, lateral surfaces of the upper via pad remnant146b, the lower via pad remnant148b, and the plated channel remnant150b. The inclusion of an electrically non-conductive, filler member304can provide improved structural rigidity for the grounding element118b, thereby enhancing reliability of electrical connections for reducing EMI. Still referring toFIG. 3C, formation of the EMI shield124yields the orthogonal lateral profile of the package100that is substantially planar and is substantially devoid of inward recessing in the lateral portion128.

While the grounding element118bis illustrated inFIG. 3BandFIG. 3Cas fully extending across the thickness of the substrate unit102, it is contemplated that the extent of the grounding element118bcan vary for other implementations. In particular and as further described below, the grounding element118bcan partially extend across the thickness of the substrate unit102, and can be implemented as, for example, a remnant of a blind grounding via or an internal grounding via.

FIG. 4Aillustrates a cross-sectional view of a semiconductor device package400implemented in accordance with another embodiment of the invention. Certain aspects of the package400are implemented in a similar manner as previously described for the package100ofFIG. 1throughFIG. 3Cand, thus, are not further described herein.

Referring toFIG. 4A, the package400includes grounding elements418aand418b, which are disposed substantially at the periphery of the substrate unit102. In the illustrated embodiment, the grounding elements418aand418bare implemented as remnants of blind grounding vias that extend between the upper surface104of the substrate unit102and an electrically conductive layer452, which is disposed between the upper surface104and the lower surface106of the substrate unit102and serves as an internal grounding layer. In particular, each of the grounding elements418aand418bincludes an upper via pad remnant446aor446b, which is disposed adjacent to the upper surface104of the substrate unit102, a lower via pad remnant448aor448b, which is electrically connected to the electrically conductive layer452and is disposed above and at a certain spacing apart from the lower surface106of the substrate unit102, and a plated channel remnant450aor450b, which extends between the upper via pad remnant446aor446band the lower via pad remnant448aor448b. While the grounding elements418aand418bare illustrated as partially extending between the upper surface104and the lower surface106of the substrate unit102, it is contemplated that the extent of the grounding elements418aand418bcan vary for other implementations. In the illustrated embodiment, the grounding elements418aand418binclude connection surfaces S1′ and S2′, respectively, which are electrically exposed adjacent to the lateral surfaces142and144, respectively. Advantageously, the relatively large areas of the connection surfaces S1′ and S2′ can enhance reliability and efficiency of electrical connections for reducing EMI. For certain implementations, a height H2of the grounding elements418aand418bcan be somewhat less than the thickness of the substrate unit102, and can be in the range of about 0.1 mm to about 1.8 mm, such as from about 0.2 mm to about 1 mm or from about 0.3 mm to about 0.5 mm. A width W2of the grounding elements418aand418b, namely a lateral extent adjacent to the upper surface104, can be in the range of about 75 μm to about 275 μm, such as from about 100 μm to about 250 μm or from about 125 μm to about 225 μm.

As illustrated inFIG. 4A, the package400also includes a semiconductor device408b, which is a semiconductor chip that is disposed adjacent to the upper surface104of the substrate unit102. In the illustrated embodiment, the semiconductor device408bis flip chip-bonded to the substrate unit102, such as via a set of solder bumps. It is contemplated that the semiconductor device408bcan be electrically connected to the substrate unit102in another manner, such as by wire-bonding.

FIG. 4Billustrates a cross-sectional view of a semiconductor device package460implemented in accordance with another embodiment of the invention. Certain aspects of the package460are implemented in a similar manner as previously described for the package100ofFIG. 1throughFIG. 3Cand the package400ofFIG. 4Aand, thus, are not further described herein.

Referring toFIG. 4B, the package460includes grounding elements462aand462b, which are disposed substantially at the periphery of the substrate unit102. In the illustrated embodiment, the grounding elements462aand462bare implemented as remnants of blind grounding vias that extend between the lower surface106of the substrate unit102and an electrically conductive layer464, which is disposed between the upper surface104and the lower surface106of the substrate unit102and serves as an internal grounding layer. In particular, each of the grounding elements462aand462bincludes an upper via pad remnant466aor466b, which is electrically connected to the electrically conductive layer464and is disposed below and at a certain spacing apart from the upper surface104of the substrate unit102, a lower via pad remnant468aor468b, which is disposed adjacent to the lower surface106of the substrate unit102, and a plated channel remnant470aor470b, which extends between the upper via pad remnant466aor466band the lower via pad remnant468aor468b. Advantageously, the positioning of the grounding elements462aand462bbelow the upper surface104of the substrate unit102conserves valuable area of the upper surface104that would otherwise be taken up for EMI shielding functionality, and, in turn, allows a reduced overall package size by reducing or minimizing a footprint area of the package460. However, it is contemplated that the positioning and extent of the grounding elements462aand462bcan vary for other implementations. In the illustrated embodiment, the grounding elements462aand462binclude connection surfaces S1″ and S2″, respectively, which are electrically exposed adjacent to the lateral surfaces142and144, respectively. Advantageously, the relatively large areas of the connection surfaces S1″ and S2″ can enhance reliability and efficiency of electrical connections for reducing EMI, while achieving the goal of a reduced overall package size. For certain implementations, a height HBof the grounding elements462aand462bcan be somewhat less than the thickness of the substrate unit102, and can be in the range of about 0.1 mm to about 1.8 mm, such as from about 0.2 mm to about 1 mm or from about 0.3 mm to about 0.5 mm. A width WBof the grounding elements462aand462b, namely a lateral extent adjacent to the lower surface106, can be in the range of about 75 μm to about 275 μm, such as from about 100 μm to about 250 μm or from about 125 μm to about 225 μm.

FIG. 4Cillustrates a cross-sectional view of a semiconductor device package480implemented in accordance with another embodiment of the invention. Certain aspects of the package480are implemented in a similar mariner as previously described for the package100ofFIG. 1throughFIG. 3C, the package400ofFIG. 4A, and the package460ofFIG. 4Band, thus, are not further described herein.

Referring toFIG. 4C, the package480includes grounding elements482aand482b, which are disposed substantially at the periphery of the substrate unit102. In the illustrated embodiment, the grounding elements482aand482bare implemented as remnants of buried or internal grounding vias that extend between a pair of electrically conductive layers484aand484b, which are disposed between the upper surface104and the lower surface106of the substrate unit102and serve as a pair of internal grounding layers. In particular, each of the grounding elements482aand482bincludes an upper via pad remnant486aor486b, which is electrically connected to the electrically conductive layer484aand is disposed below and at a certain spacing apart from the upper surface104of the substrate unit102, a lower via pad remnant488aor488b, which is electrically connected to the electrically conductive layer484band is disposed above and at a certain spacing apart from the lower surface106of the substrate unit102, and a plated channel remnant490aor490b, which extends between the upper via pad remnant486aor486band the lower via pad remnant488aor488b. Advantageously, the positioning of the grounding elements482aand482bbetween the upper surface104and the lower surface106of the substrate unit102conserves valuable area of both the upper surface104and the lower surface106that would otherwise be taken up for EMI shielding functionality, and, in turn, allows a reduced overall package size by reducing or minimizing a footprint area of the package480. However, it is contemplated that the positioning and extent of the grounding elements482aand482bcan vary for other implementations. In the illustrated embodiment, the grounding elements482aand482binclude connection surfaces S1″′ and S2″′, respectively, which are electrically exposed adjacent to the lateral surfaces142and144, respectively. Advantageously, the relatively large areas of the connection surfaces S1″′ and S2″′ can enhance reliability and efficiency of electrical connections for reducing EMI, while achieving the goal of a reduced overall package size. For certain implementations, a height HCof the grounding elements482aand482bcan be somewhat less than the thickness of the substrate unit102, and can be in the range of about 0.1 mm to about 1.6 mm, such as from about 0.2 mm to about 0.8 mm or from about 0.2 mm to about 0.4 mm. A width WCof the grounding elements482aand482b, namely a lateral extent adjacent to the electrically conductive layer484aor484b, can be in the range of about 75 μm to about 275 μm, such as from about 100 μm to about 250 μm or from about 125 μm to about 225 μm.

FIG. 5AthroughFIG. 5Eillustrate a method of forming a semiconductor device package, according to an embodiment of the invention. For ease of presentation, the following manufacturing operations are described with reference to the package100of FIG.1throughFIG. 3C. However, it is contemplated that the manufacturing operations can be similarly carried out to form other semiconductor device packages, such as the package400ofFIG. 4A, the package460ofFIG. 4B, and the package480ofFIG. 4C.

Referring first toFIG. 5AandFIG. 5B, a substrate500is provided. To enhance manufacturing throughput, the substrate500includes multiple substrate units, including the substrate unit102and an adjacent substrate unit102′, thereby allowing certain of the manufacturing operations to be readily performed in parallel or sequentially. The substrate500can be implemented in a strip manner, in which the multiple substrate units are arranged sequentially in a linear fashion, or in an array manner, in which the multiple substrate units are arranged in a two-dimensional fashion. For ease of presentation, the following manufacturing operations are primarily described with reference to the substrate unit102and related components, although the manufacturing operations can be similarly carried for other substrate units and related components.

As illustrated inFIG. 5AandFIG. 5B, multiple grounding vias are disposed adjacent to a periphery of each substrate unit. In particular, grounding vias502a,502b,502c,502d, and502eare disposed adjacent to sides of the substrate unit102. In the illustrated embodiment, each grounding via includes an upper via pad, such as an upper via pad546aor546b, a lower via pad, such as a lower via pad548aor548b, and a plated channel, such as a plated channel550aor550b. The grounding vias502a,502b,502c,502d, and502ecan be formed in any of a number of ways, such as photolithography, chemical etching, laser drilling, or mechanical drilling to form openings, along with plating of the openings using a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. Plating of the openings can be carried out to a thickness in the range of about 1 μm to about 20 μm, such as from about 5 μm to about 20 μm or from about 10 μm to about 15 μm, while leaving via channels that extend substantially across vertical extents of the grounding vias502a,502b,502c,502d, and502e. For certain implementations, an electrically conductive material can be applied to and drawn into the via channels so as to form electrically conductive, core members that are accommodated by and substantially fill the via channels. For example, the electrically conductive material can include a metal, such as copper, a solder, such as any of a number of fusible metal alloys having melting points in the range of about 90° C. to about 450° C., or an electrically conductive adhesive, such as silver glue, epoxy with a copper filler, or any of a number of other resins having an electrically conductive filler dispersed therein. For other implementations, an electrically non-conductive material can be applied to and drawn into the via channels so as to form electrically non-conductive, core members that are accommodated by and substantially fill the via channels. For example, the electrically non-conductive material can include a solder mask, an electrically non-conductive adhesive, such as epoxy substantially devoid of an electrically conductive filler, or any of a number of other suitable resins. Filling the via channels can yield larger areas for resulting connection surfaces, enhanced structural rigidity, or both, thereby further enhancing reliability and efficiency of electrical connections for reducing EMI. While the grounding vias502a,502b,502c,502d, and502eare illustrated as fully extending between an upper surface504and a lower surface524of the substrate500, it is contemplated that the extent of the grounding vias502a,502b,502c,502d, and502ecan vary for other implementations. For example, it is contemplated that at least one of the grounding vias502a,502b,502c,502d, and502ecan be implemented as a blind grounding via or an internal grounding via.

In the illustrated embodiment, a via pad, such as the upper via pad546aor546b, has an annular shape, and a plated channel, such as the plated channel550aor550b, defines a via channel that is shaped in the form of a circular cylinder, including a substantially circular cross-section. It is contemplated that the shapes of a via pad and a via channel, in general, can be any of a number of shapes. For example, a via channel can have another type of cylindrical shape, such as an elliptic cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape, or can have a non-cylindrical shape, such as a cone, a funnel, or another tapered shape. It is also contemplated that lateral surfaces of a via channel can be curved or roughly textured. For certain implementations, a lateral extent W3of each via channel (also sometimes referred to as a via size) can be in the range of about 50 μm to about 350 μm, such as from about 100 μm to about 300 μm or from about 150 μm to about 250 μm, while a lateral extent W4of each via pad (also sometimes referred to as a via pad size) can be in the range of about 150 μm to about 550 μm, such as from about 200 μm to about 500 μm or from about 250 μm to about 450 μm. If a via channel or a via pad has a non-uniform shape, the lateral extent W3or W4can correspond to, for example, an average of lateral extents along orthogonal directions.

To enhance reliability and efficiency of electrical connections for reducing EMI, grounding vias are disposed adjacent to all four sides of each substrate unit, although the grounding vias also can be disposed adjacent to a subset of the four sides. It is also contemplated that grounding vias can be disposed adjacent to all four corners of each substrate unit or a subset of the four corners. For certain implementations, a spacing L1of nearest-neighbor grounding vias of a substrate unit (also sometimes referred to as a via pitch) can be in the range of about 0.1 mm to about 3 mm, such as from about 0.2 mm to about 2 mm or from about 0.5 mm to about 1.5 mm. Referring toFIG. 5B, a dashed boundary within each substrate unit defines a “keep-out” portion, within which semiconductor devices are disposed. To reduce or minimize adverse impact on the operation of semiconductor devices, grounding vias of a substrate unit can be spaced apart from the “keep-out” portion by a spacing L2(also sometimes referred to as a “keep-out” distance). For certain implementations, the spacing L2can be in the range of about 50 μm to about 300 μm, such as from about 50 μm to about 200 μm or from about 100 μm to about 150 μm. It is contemplated that the number of grounding vias and their positioning within the substrate500can vary from that illustrated inFIG. 5AandFIG. 5B. It is also contemplated that multiple rows of grounding vias can be disposed adjacent to a periphery of each substrate unit. It is further contemplated that the spacing L2need not be allocated in the case of blind grounding vias, which are disposed below the upper surface504, or in the case of internal grounding vias. In particular, such blind or internal grounding vias can be partially or fully disposed within the “keep-out” portion and below semiconductor devices, so as to reduce or minimize adverse impact on the operation of the semiconductor devices while achieving the goal of a reduced overall package size.

Once the substrate500is provided, the semiconductor devices108a,108b, and108care disposed adjacent to the upper surface504of the substrate500, and are electrically connected to the substrate unit102. In particular, the semiconductor device108bis wire-bonded to the substrate unit102via the wires112, and the semiconductor devices108aand108care surface mounted to the substrate unit102. Referring toFIG. 5A, the lower surface524of the substrate500is disposed adjacent to a tape506, which can be implemented as a single-sided or double-sided adhesive tape. Advantageously, the tape506secures the substrate unit102with respect to adjacent substrate units, and allows various subsequent operations to be carried out with those components disposed adjacent to the tape506, without requiring inversion or transfer to a separate carrier.

Next, as illustrated inFIG. 5C, a molding material514is applied to the upper surface504of the substrate500so as to substantially cover or encapsulate the grounding vias502aand502b, the semiconductor devices108a,108b, and108c, and the wires112. The molding material514can include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO2. The molding material514can be applied using any of a number of molding techniques, such as compression molding, injection molding, and transfer molding. Once applied, the molding material514is hardened or solidified, such as by lowering the temperature to below a melting point of the molding material514, thereby forming a molded structure526. To facilitate proper positioning of the substrate500during subsequent singulation operations, fiducial marks can be formed in the molded structure526, such as using laser marking. Alternatively, or in conjunction, fiducial marks can be formed adjacent to a periphery of the substrate500.

Singulation is next carried out with respect to an upper surface516of the molded structure526. Such manner of singulation can be referred to as “front-side” singulation. Referring toFIG. 5CandFIG. 5D, the “front-side” singulation is carried out using a saw518, which forms cutting slits, including cutting slits520aand520b. In particular, the cutting slits520aand520bextend downwardly and completely through the molded structure526and the substrate500and partially through the tape506, thereby sub-dividing the molded structure526and the substrate500into discrete units, including the package body114and the substrate unit102. Such manner of singulation can be referred to as “full-cut” singulation, since sub-division of the molded structure526and the substrate500at each of various locations can occur through one singulation operation, rather than multiple singulation operations, such as multiple “half-cut” singulations. Advantageously, the use of “full-cut” singulation, rather than “half-cut” singulation, enhances manufacturing throughput by reducing the number of singulation operations and the time involved for those operations. Also, manufacturing cost is reduced by enhancing an utilization ratio of the substrate500, and an overall yield rate is enhanced by reducing the probability of defects resulting from sawing errors. As illustrated inFIG. 5D, the tape506secures the substrate unit102and the package body114with respect to adjacent substrate units and package bodies during the “full-cut” singulation.

Still referring toFIG. 5D, the saw518is laterally positioned and substantially aligned with each grounding via, such that a resulting cutting slit removes a certain volume or weight percentage of the grounding via, such as from about 10 percent to about 90 percent, from about 30 percent to about 70 percent, or from about 40 percent to about 60 percent by volume or by weight. If core members are included, a resulting cutting slit also removes a certain volume or weight percentage of each core member, such as from about 10 percent to about 90 percent, from about 30 percent to about 70 percent, or from about 40 percent to about 60 percent by volume or by weight. In such manner, the grounding elements118aand118bare formed and include the connection surfaces S1and S2, respectively, which are exposed to the surroundings at the periphery of the substrate unit102. The alignment of the saw518during singulation can be aided by fiducial marks, which allow proper positioning of the saw518when forming the cutting slits520aand520b. For certain implementations, a width C1of each of the cutting slits520aand520b(also sometimes referred to as a full-cut width or full-cut sawing street) can be in the range of about 100 μm to about 600 μm, such as from about 200 μm to about 400 μm or from about 250 μm to about 350 μm.

Next, as illustrated inFIG. 5E, an EMI coating522is formed adjacent to exposed surfaces, including the exterior surfaces of the package body114, the connection surfaces S1and S2of the grounding elements118aand118b, and the lateral surfaces142and144of the substrate unit102. The EMI coating522can be formed using any of a number of coating techniques, such as chemical vapor deposition, electroless plating, electrolytic plating, printing, spraying, sputtering, and vacuum deposition. For example, the EMI coating522can include a single layer that is formed from nickel using electroless plating and with a thickness of at least about 5 μm, such as from about 5 μm to about 50 μm or from about 5 μm to about 10 μm. If the EMI coating522is multi-layered, different layers can be formed using the same coating technique or different coating techniques. For example, an inner layer can be formed from copper using electroless plating, and an outer layer can be formed from nickel using either electroless plating or electrolytic plating. As another example, an inner layer (serving as a base layer) can be formed from copper using either sputtering or electroless plating and with a thickness of at least about 1 μm, such as from about 1 μm to about 50 μm or from about 1 μm to about 10 μm, and an outer layer (serving as an anti-oxidation layer) can be formed from stainless steel, nickel, or copper using sputtering and with a thickness no greater than about 1 μm, such as from about 0.01 μm to about 1 μm or from about 0.01 μm to about 0.1 μm. In these examples, surfaces to which the EMI coating522is applied can be subjected to certain pre-treatment operations to facilitate formation of the inner layer and the outer layer. Examples of such pre-treatment operations include surface roughening, such as by chemical etching or mechanical abrasion, and formation of a seed layer. Separating the substrate unit102and related components from the tape506, such as using a pick-and-place technique, results in the package100including the EMI shield124.

FIG. 6illustrates a method of forming a semiconductor device package, according to another embodiment of the invention. For ease of presentation, the following manufacturing operations are described with reference to the package400ofFIG. 4A. However, it is contemplated that the manufacturing operations can be similarly carried out to form other semiconductor device packages, such as the package100ofFIG. 1through FIG.3C, the package460ofFIG. 4B, and the package480ofFIG. 4C. Also, certain aspects of the manufacturing operations are implemented in a similar manner as previously described forFIG. 5AthroughFIG. 5Eand, thus, are not further described herein.

Referring toFIG. 6, a substrate600along with a hardened molding material614are disposed adjacent to a tape606, which can be implemented as a single-sided or double-sided adhesive tape. Singulation is next carried out with respect to an upper surface616of the hardened molding material614. As illustrated inFIG. 6, the singulation is carried out using a saw618, which forms cutting slits620aand620bthat extend downwardly and completely through the hardened molding material614and the substrate600and partially through the tape606, thereby sub-dividing the hardened molding material614and the substrate600into discrete units, including the package body114and the substrate unit102. In particular, the saw618is laterally positioned and substantially aligned with each grounding via, such that a resulting cutting slit sub-divides the grounding via into two grounding elements that are separated from one another and are disposed adjacent to respective substrate units. If core members are included, a resulting cutting slit also sub-divides each core member into two filler members. In such manner, the grounding elements418aand418bare formed and include the connection surfaces S1′ and S2′, respectively, which are exposed to the surroundings at the periphery of the substrate unit102. Advantageously, the manner of singulation illustrated inFIG. 6enhances manufacturing throughput by further reducing the number of singulation operations and the time involved for those operations, reduces manufacturing cost by further enhancing an utilization ratio of the substrate600, and enhances an overall yield rate by further reducing the probability of defects resulting from sawing errors. For certain implementations, a via size W5of each grounding via can be in the range of about 100 μm to about 700 μm, such as from about 200 μm to about 600 μm or from about 300 μm to about 500 μm, while a via pad size W6of each grounding via can be in the range of about 300 μm to about 1,100 μm, such as from about 400 μm to about 1,000 μm or from about 500 μm to about 900 μm. A width C2of each of the cutting slits620aand620bcan be substantially the same as the width C1previously described above with reference toFIG. 5D, and can be in the range of about 100 μm to about 600 μm, such as from about 200 μm to about 400 μm or from about 250 μm to about 350 μm. However, it is contemplated that the width C2can vary for other implementations, and can be adjusted relative to the via size W5or the via pad size W6of a grounding via to allow its sub-division into multiple grounding elements. For example, the width C2, in general, can be represented as: C2<W5<W6.