Power source device and image forming apparatus

A power source device includes a transformer including a primary winding and a secondary winding; a switching element for enabling or disabling supply of electric power to the primary winding by a switching operation; a controller for controlling the switching operation, wherein the controller is capable of effecting continuous control in which the switching operation is continued and intermittent control in which a switching period in which the switching operation is performed and a rest period in which the switching operation is at rest are repeated, a calculating portion not operating in the rest period; and a measuring portion continuing operation even in the rest period. When a predetermined time has elapsed from a start of the rest period, the measuring portion causes the calculating portion to resume the operation thereof, and starts the switching period.

FIELD OF THE INVENTION AND RELATED ART

The present invention relates to a power source device for effecting control of a switching power source using an insulating transformer and an image forming apparatus including the power source device.

In the switching power source, a switching operation is performed when an AC voltage of a commercial power source is converted into a DC voltage. In the switching power source, in order to reduce electric power consumption during sleep of a device in which a switching power source is mounted, in a state in which electric power outputted to a load is small (hereinafter referred to as a low load state), efficiency of the switching power source has been required to be improved. Here, the efficiency of the switching power source is represented as a ratio of electric power outputted by the switching power source to electric power supplied to the switching power source.

As a controller of the switching power source, a control logic circuit such as a CPU, a microcomputer or an ASIC is used, and a power source using the control logic circuit (hereinafter, referred to as a digital control power source) has been known. For example, as a known example of a method of improving the power source efficiency of the digital control power source in the low load state, an electric power supplying device as disclosed in Japanese Laid-Open Patent Application 2014-027793 has been proposed.

However, in the digital control power source using the insulating transformer, when intermittent control in the low load state is effected, the power source efficiency has been required to be further improved. Further, in the digital control power source, also in the low load state, there is a need to effect control while supplying a power source voltage so that the controller provided in a primary side of the insulating transformer can continue an operation.

SUMMARY OF THE INVENTION

The present invention enables not only an improvement in efficiency of a power source device in a low load state but also a continuous operation of a controller provided in a primary side of the power source device.

According to an aspect of the present invention, there is provided a power source device comprising: a transformer including a primary winding and a secondary winding; a switching element for enabling or disabling supply of electric power to the primary winding by a switching operation; a controller for controlling the switching operation, wherein the controller is capable of effecting continuous control in which the switching operation is continued and intermittent control in which a switching period in which the switching operation is performed and a rest period in which the switching operation is at rest are repeated, a calculating portion not operating in the rest period; and a measuring portion continuing operation even in the rest period, wherein when a predetermined time has elapsed from a start of the rest period, the measuring portion causes the calculating portion to resume the operation thereof, and starts the switching period.

According to another aspect of the present invention, there is provided an image forming apparatus comprising: an image forming portion for forming an image; and a power source device for supplying electric power to the image forming apparatus, wherein the power source device includes, a transformer including a primary winding and a secondary winding, a switching element for enabling or disabling supply of electric power to the primary winding by a switching operation, a controller for controlling the switching operation, wherein the controller is capable of effecting continuous control in which the switching operation is continued and intermittent control in which a switching period in which the switching operation is performed and a rest period in which the switching operation is at rest are repeated, a calculating portion not operating in the rest period, and a measuring portion continuing operation even in the rest period, wherein when a predetermined time has elapsed from a start of the rest period, the measuring portion causes the calculating portion to resume the operation thereof, and starts the switching period.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be described specifically with reference to the drawings.

FIG. 1Ais a schematic view of a digital control power source100using an active clamp type in Embodiment 1. An AC power source10such as a commercial power source outputs an AC voltage, and the AC outputted from the AC power source is rectified by a bridge diode BD1which is a full-wave rectifying means. A voltage V in rectified by the bridge diode BD1is inputted into the digital control power source100. A smoothing capacitor C3is a smoothing means for the voltage Vin, and a low-side potential of the smoothing capacitor C3is DCL, and a high-side potential of the smoothing capacitor C3is DCH.

The digital control power source100outputs a voltage Vout from the voltage Vin charged in the smoothing capacitor C3to an insulated secondary side. In this embodiment, as the voltage Vout, for example, a constant voltage of 24 V is outputted. The digital control power source100includes an insulating transformer T1in which a primary winding P1and an auxiliary winding Ps are provided in a primary side and in which a secondary winding S1is provided in the secondary side.

From the primary winding P1to the secondary winding S1of the transformer T1, energy is supplied by a switching operation of a FET (field-effect transistor)1and FET2which are switching elements described later. The auxiliary winding P2of the transformer T1rectifies and smooths a forward voltage of the voltage V in, applied to the primary winding P1, by a diode D4and a capacitor C4, and is used for supplying a voltage V1. In the primary side of the digital control power source100, the FET1and the FET2are connected. Specifically, the FET1is series-connected with the primary winding P1of the transformer T1. The FET2series-connected with a capacitor C2for voltage clamp is parallel-connected with the primary winding P1of the transformer T1. Further, in the primary side of the digital control power source100, a control logic circuit110as a control means for the FET1and the FET2and an FET driving circuit120are provided. A capacitor C1, for voltage resonance, parallel-connected with the FET1is provided for reducing loss when the FET1and the FET2are changed from an on state to an off state. A diode D1is a body diode for the FET1. Similarly, a diode D2is a body diode for FET2.

In the secondary side of the digital control power source100, a diode D11and a capacitor C11as a secondary-side rectifying and smoothing means for a flyback voltage generating in the secondary winding S1of the transformer T1are provided. Further, in the secondary side of the digital control power source100, a feed-back circuit140as a feed-back means used for feeding back, toward the primary side, a voltage Vout to be outputted at the secondary side is provided.

In this embodiment, as the control logic circuit110, a digital control circuit, such as a CPU or an ASIC, operating by a clock signal generated by a clock oscillating portion115described later is used. Details of the control logic circuit110will be described later with reference toFIG. 1B. By using the digital control circuit such as the CPU, complicated waveform control of control signals D1, D2can be realized by an inexpensive integrated circuit.

Between a VC terminal of the control logic circuit110and a G terminal connected with a DCL side, a voltage V2generated by a DC/DC converter150. The control logic circuit110outputs control signals D1, D2on the basis of a voltage signal inputted into a feed-back terminal. The control signal D1is driving signal for controlling the FET1, and the control signal Dd2is a driving signal for controlling the FET2. The control logic circuit110effects control of the FET1and the FET2via an FET driving circuit120. A VS terminal of the control logic circuit110is used for detecting a voltage Vin charged in a smoothing capacitor C3through detection of the voltage V1, obtained by rectifying and smoothing the forward voltage generated in the auxiliary winding P2of the transformer T1, by division by a resistor R3and a resistor R4.

The FET driving circuit120generates a gate driving signal DL of the FET1in accordance with the control signal D1inputted from the control logic circuit110and generates a gate driving signal DH of the FET2in accordance with the control signal D2from the control logic circuit110. The voltage V1is supplied to between the VC terminal and the GH terminal of the FET driving circuit120. Further, in order to drive the FET2, by a charge pump circuit constituted by a capacitor C5and a diode D5, the voltage V1is supplied to between a VH terminal and a GH terminal. When the control signal D1inputted from the control logic circuit110becomes a high level, the FET driving circuit120sets the gate driving signal DL of the FET1at a high level and puts the FET1in an on state. Similarly, when the control signal D2inputted from the control logic circuit110becomes a high level, the FET driving circuit120sets the gate driving signal DH of the FET2at a high level and puts the FET2in an on state.

The DC/DC converter150is a 3-terminal regulator or a step-down digital control power source and outputs a voltage V2to an OUT terminal from the voltage V1inputted between the VC terminal and the G terminal of the DC/DC converter150. An actuating circuit130is a 3-terminal regulator or a step-down digital control power source and outputs the voltage V1to an OUT terminal from the voltage Vin inputted between the VC terminal and the G terminal thereof. The actuating circuit130operates only in the case where the voltage V1supplied from the auxiliary winding P1is not more than a predetermined voltage value and is used for supplying the voltage V1during actuation of the digital control power source100.

The feed-back circuit140is used for controlling a voltage Vout to a predetermined constant voltage. A voltage value of the voltage Vout is set by a reference voltage of a reference terminal REF of a shunt regulator IC5, the resistor R52and the resistor R53. When the voltage Vout is higher than a predetermined voltage (24 V in this embodiment), a current increases from a cathode terminal K of the shunt regulator IC5, so that a current flowing through a secondary-side diode PC5aof a photo-coupler PC5via a pull-up resistor R51increases. Thereafter, a discharging current of electric charges of a capacitor C6by a primary-side transistor PC5bof the photo-coupler PC5increases, and therefore a voltage of the FB terminal of the control logic circuit110lowers.

Further, when the voltage Vout is not more than 24 V, the current flowing through the secondary-side diode PC5aof the photo-coupler PC5decreases, so that the discharging current of the electric charges of the capacitor C6by the primary-side transistor PC5bof the photo-coupler PC5decreases. For this reason, a charging current flowing from the voltage V2to the capacitor C6via the resistor R2becomes larger, so that the voltage of the FB terminal of the control logic circuit110increases. The control logic circuit110effects feed-back control for controlling the voltage Vout to the predetermined constant voltage by detecting the voltage of the FB terminal (FB terminal voltage). Thus, the control logic circuit110is capable of indirectly effecting the feed-back control of the voltage Vout by monitoring the FB terminal voltage. Further, in place of the feed-back circuit140, a control logic circuit110is provided in a secondary side and monitors the voltage Vout, so that the voltage Vout may also be directly subjected to the feed-back control.

Further, the control logic circuit110monitors the FB terminal voltage and thus can discriminate a state of a load of the digital control power source100. This is because with a larger secondary-side load, a voltage drop of the voltage Vout by a secondary-side diode D11and capacitor C11and the like is liable to generate, so that the FB terminal voltage of the control logic circuit110becomes larger. For this reason, the control logic circuit110can effect proper control depending on the load state by monitoring the FB terminal voltage. In order to accurately discriminate the load state, a current detecting means (not shown) may also be provided in a path along which electric power is supplied to the FET1or a load of the digital control power source100. The means for discriminating the low load state in this embodiment will be described as use of the FB terminal voltage of the control logic circuit110. That is, in this embodiment, the control logic circuit110functions as a discriminating means for discriminating the low load state. Into the control logic circuit110, a voltage obtained by dividing the voltage V2, generated by the DC/DC converter150, by the resistors R5, R6is inputted as a reference voltage Vref described later.

FIG. 1Bis a schematic diagram of a circuit constitution of the control logic circuit110. The control logic circuit110is divided into a block1and a block2. The block1includes a clock oscillating portion115, a timer controller116, a PWM current portion117and a comparison controller118. The block2includes a calculating controller111as a calculating means, a main storing portion112such as an RAM, an external storing portion113such as an ROM or a flash memory (FLASH), and an AD converting portion114. The control logic circuit110is, for example, a microcomputer formed with one-chip integrated circuit. The calculating controller111is capable of setting a set value in the timer controller116as a measuring means.

The calculating controller111operates on the basis of a clock signal indicated by a broken-line arrow inputted from the clock oscillating portion115as a generating means and reads an instruction and data stored in the external storing portion113in the main storing portion112, and then effect consecutive operation. On the basis of the FB terminal voltage detected by the AD converting portion114, the calculating controller111effects control of the FET1and FET2by controlling set values (e.g., control start timing, period, duty) of the two control signals D1, D2outputted from the PWM output portion117. The calculating controller111compares the FB terminal voltage detected by the AD converting portion114with FBL1described later, and discriminates whether or not a period changes from a switching period to a rest period which are described later. Incidentally, into the AD converting portion114, the voltage obtained by dividing, by the resistors R3, R4, the voltage V1obtained by rectifying and smoothing the forward voltage generated in the auxiliary winding P2of the transformer T1is inputted, and the control logic circuit110detects the voltage Vin.

The timer controller116is a timer used for controlling a length of the rest period of intermittent control described later with reference toFIG. 3, ad includes a circuit for storing the length of the rest period as a set value. The comparison controller118as a comparing means is a circuit for comparing the feed-back terminal voltage with the predetermined reference voltage Vref which is a second value, and is used in the intermittent control described with reference toFIG. 3. The reference voltage Vref is generated by dividing the voltage V2by the resistors R5, R6. Details of control by the timer controller116and the comparison controller118will be described with reference toFIGS. 3 and 4.

Then, the block1and the block2of the control logic circuit110will be described. To the block1, the voltage V2generated by the DC/DC converter150is always supplied. The clock oscillating portion115, the timer controller116, the PWM current portion117and the comparison controller118of the block1can continue operations thereof even in a non-connection state in which a switch119as a connecting means for sleep control is disconnected (hereinafter referred to as an off state). Here, a state in which the switch119is in the off state and operations of the respective portions of the block2are at block refers to as a sleep state of the control logic circuit110.

To the block2of the control logic circuit110, the voltage V2is supplied only in a connection state in which the switch119is connected (hereinafter referred to as an on state), and thus the block2can operate. The block2of the control logic circuit110is in a state in which the voltage V2is not supplied, in the off state of the switch119(i.e., in the sleep state of the control logic circuit110). For that reason, in the control logic circuit110, it is possible to reduce electric power corresponding to electric power consumption by the respective functional portions disposed in the block2.

In the control of the control logic circuit110in this embodiment, during a start of the rest period of the intermittent control described with reference toFIG. 3, the switch119is placed in the off state (“OFF” inFIG. 1B) by the calculating controller111, so that supply of the voltage V2to the block2is stopped. Further, the timing when the rest period of the intermittent control is ended is detected by the timer controller116or the comparison controller118of the block1. When the timer controller116or the comparing controller118detects the timing when the rest period of the intermittent control ends, the switch119is placed in the on state (“ON” inFIG. 1B), and the supply of the voltage V2to the block2is resumed. As a result, the calculating controller111is in a state in which the calculating controller111can resume the control.

As a similar method usable in place of the control logic circuit110, a control logic circuit810having another constitution is shown inFIG. 2A. InFIG. 2A, constituent elements identical to those inFIG. 1Bare represented by the same reference numerals or symbols and will be omitted from description. In the control logic circuit810inFIG. 2A, the voltage V2generated by the DC/DC converter150is always supplied to the blocks1,2. Further, in the control logic circuit810inFIG. 2A, the switch119is provided to a signal line of the clock signal outputted from the clock oscillating portion115to the block2. InFIG. 2A, when the calculating controller111puts the switch119in the off state during the start of the rest period of the intermittent control and the timer controller116or the comparison controller118detects the timing when the rest period of the intermittent control ends, the switch119is in the on state.

Thus, the control logic circuit810can reduce the electric power consumption of the circuit of the block2also by stopping, during the sleep, input of the clock signal, into the block2, supplied to the functional portions disposed in the block2. Incidentally, as in the control logic circuit110, in the constitution in which the voltage V2supplied to the functional portions disposed in the block2is stopped, also a leak current of the functional portions disposed in the block2can be reduced. For this reason, in the constitution ofFIG. 1A, the electric power consumption can be further reduced.

As another similar method usable in place of the control logic circuit110, there is a method in which a cyclic period of the clock signal supplied to the functional portions disposed in the block2in the sleep state is made extremely late. Further, as another similar method, there is a method in which the voltage V2supplied to the functional portions disposed in the block2is lowered. Further, it would be considered that a combination of the above-described methods is used. In this embodiment, at least by the timer controller116, the timing of ending the sleep state in the rest period of the intermittent control is detected and then the sleep state is eliminated, so that the period changes from the rest period to the switching period of the intermittent control.

Further, as shown in a control logic circuit820ofFIG. 2B, all or a part of the main storing portion112is disposed in the block1. As a result, in the sleep state of the control logic circuit820, even when the switch119is in the off state, it is possible to form a state in which the main storing portion112is operable. Further, the set value of the timer controller116is stored in the main storing portion112in advance, and then the timer controller116may also operate on the basis of the set value stored in the main storing portion112. As a result, in the control logic circuit820, there is an advantage that there is no need to provide the timer controller116with a circuit for storing the set value.

[Control Method Using Active Clamp Type]

InFIG. 3, (a) to (c) are time charts for illustrating control methods of the digital control power source100using an active clamp type. In (a) to (c) ofFIG. 3, (i) shows a waveform of the control signal D1outputted from the control logic circuit110to the FET driving circuit120and thus can also be said that (i) shows a waveform of the gate driving voltage DL of the FET1outputted from the FET driving circuit120. (ii) shows a waveform of the control signal D1outputted from the control logic circuit110to the FET driving circuit120and thus can also be said that (ii) shows a waveform of the gate driving voltage DH of the FET2outputted from the FET driving circuit120. (iii) shows a drain current of the FET1, (iv) shows a voltage between the drain terminal and the source terminal of the FET1, and (v) shows the FB terminal voltage of the control logic circuit110.

In (a) ofFIG. 3, continuous control in which a switching period in which a switching operation of the FET1and the FET2is continuously performed is continuously controlled will be described. In the switching period, the control logic circuit110provides a dead time which is a period in which not only the FET1but also the FET2are turned off and repetitively controls the FET1and the FET2by alternately turning on and off the FET1and the FET2. As described above, the control logic circuit110in this embodiment discriminates the load state on the basis of the FB terminal voltage. So long as the FB terminal voltage is kept in a state in which the FB terminal voltage is larger than the predetermined voltage value FBL1which is a first value, the control logic circuit110discriminates that the heavy load state of the digital control power source100continues, and effects the continuous control in which the switching period is continued. In the continuous control shown in (a) ofFIG. 3, when the FB terminal voltage is high, a ratio of an on-time of the FET1to an on-time of the FET2is controlled so as to be made high.

Incidentally, on the basis of the voltage Vin detected by the VS terminal, the control logic circuit110effects control so that the on-time of the FET1is corrected so as to be shorter with an increasing voltage Vin. In other words, the control logic circuit110effects control so that the on-time of the FET1is corrected so as to be inversely proportional to the voltage value of the voltage Vin. Further, in this embodiment, the control logic circuit110enables detection of the load on the basis of the FB terminal voltage by effecting control using the VS terminal.

In (b) ofFIG. 3, intermittent control in which the switching period and the rest period in which the switching operation of the FET1and the FET2is at rest are repetitively provided will be described. When the continuous control described with reference to (a) ofFIG. 3is effected in the low load state of the digital control power source100, efficiency of the digital control power source100lowers due to resistance loss by the primary-side current of the digital control power source100, switching loss of the FETs1,2and the like. For that reason, in the low load state of the digital control power source100, as shown in (b) ofFIG. 3, the intermittent control in which the switching period and the rest period which is described later are repeated is effected. As a result, by reducing the primary-side current of the digital control power source100and the number of times of switching of the FETs1,2electric power efficiency of the digital control power source100in the low load state can be improved.

In this embodiment, when the FB terminal voltage of the control logic circuit110is lower than FBL1, the control logic circuit110discriminates that the digital control power source100is in the low load state, the change in period to the rest period is carried out. After the change to the rest period, when the FB terminal voltage is not less than the reference voltage Vref (FBL2) set in the comparison controller118, the period of the control logic circuit110changes again to the switching period. In the digital control power source100, the reference voltage Vref (FBL2) is set at a voltage larger than FBL1(FBL2>FBL1), and uses overshooting and undershooting of the FB terminal voltage. As a result, the intermittent control shown in (b) ofFIG. 3is realized. Here, a period in which the switching period and the rest period are repetitively controlled is referred to as an intermittent control period. FBL1is a threshold used for switching the period from the switching period to the rest period, and vref (FBL2) is a threshold used for switching the period from the rest period to the switching period.

In (c) ofFIG. 3, a control method of the intermittent control period will be described. When the load of the digital control power source100is in a further low load state than the state of (b) ofFIG. 3and thus is insubstantially no load state, the rest period becomes a very long period. In the no load state, a state in which the FB terminal voltage is lower than the reference voltage Vref (FBL2) is maintained for a long period in some cases. When the rest period is longer than the predetermined period, a state in which the auxiliary winding P2of the transformer T1for outputting the voltage V1and the electric power supplied to the DC/DC converter for generating the voltage V2are insufficient is formed. Then, operations of the FET driving circuit120and the control logic circuit110cannot be continued, and therefore there is a need to supply electric power also from the actuating circuit130. However, in the case where the voltage V1is supplied from the voltage Vin charged in the smoothing capacitor C3by using the actuating circuit130, loss generating due to a potential difference between the voltage Vin and the voltage V2becomes very large. In this case, the power source efficiency of the digital control power source100in the no load state lowers. Therefore, in this embodiment, by using the timer controller116, a longest rest period Toff_max which is a first time is provided, and control is effected so that the rest period is not longer than the longest rest period Toff_max. As a result, in this embodiment, control is effected so that the voltage V1supplied from the auxiliary winding P2of the toner T1is not insufficient.

Further, in the control method shown in (c) ofFIG. 3, the longest rest period Toff_max is provided, and therefore the electric power supplied to the voltage Vout cannot be controlled by the length of the rest period. Therefore, in the case where the FB terminal voltage of the control logic circuit110lowers, FB control of the voltage Vout outputted at the secondary side is effected by shortening the on-time of the FET1in the switching period. The digital control power source100using the active clamp type has the following characteristic. That is, the digital control power source100has a characteristic such that the electric power can be supplied to the auxiliary winding P2of the transformer T1without increasing the voltage Vout outputted at the secondary side, by setting the ratio of the on-time of the FET1to the on-time of the FET2at a sufficiently small value. By this characteristic, it is possible to supply the electric power to the auxiliary winding P2of the transformer T1for generating the voltage V1and the DC/DC converter150for generating the voltage V2.

In the control of (c) ofFIG. 3, in the case where the FB terminal voltage lowers, the control logic circuit110effects control of supplying the electric power to the auxiliary winding P2in order to generate the voltages V1, V2without increasing the voltage Vout outputted at the secondary side. As a result, in this embodiment, also in the no load state of the digital control power source100, the operations of the FET driving circuit120and the control logic circuit110can be continued without operating the actuating circuit130. Thus, the longest rest period Toff_max is provided using the timer controller116, whereby it is possible to effect control so as to make the intermittent control period longer to the possible extent without operating the actuating circuit130.

[Control in this Embodiment]

FIG. 4is a flowchart for illustrating a control sequence of the digital control power source100by the control logic circuit110in this embodiment. An AC power source10is connected with the digital control power source100, and when a state in which the electric power is supplied to the digital control power source100is formed, the control logic circuit110starts the following control. In S(step)301, on the basis of the FB terminal voltage, the control logic circuit110effects control of the switching period in which the on-times of the FETs1,2described with reference to (a) ofFIG. 3are controlled. In S302, the control logic circuit110discriminates whether or not the FB terminal voltage is larger than the predetermined value FBL1for discriminating the low load state. In S302, in the case where the control logic circuit110discriminated that the FB terminal voltage is larger than FBL1, the control logic circuit110returns the process to S301and effects the continuous control ((a) ofFIG. 3) in which the switching period is continued. In S302, in the case where the control logic circuit110discriminated that the FB terminal voltage is not more than FBL1, the control logic circuit110causes the process to go to S303.

In S303, the control logic circuit110causes the calculating controller111to set the longest rest period Toff_max in the timer controller116, and the timer is started. Incidentally, as in this embodiment, in the case where a period necessary to be set in the timer controller116is only one, the set value of the timer controller116may also be a fixed value. In S304, the control logic circuit110causes the calculating circuit110to put the switch119in the off state, so that the supply of the voltage V2(electric power supply) to the block2is stopped (terminated).

In S305, the control logic circuit110discriminates whether or not the FB terminal voltage is larger than the reference voltage Vref (FBL2) by the comparison controller118. In S305, in the case where the control logic circuit110discriminated that the FB terminal voltage is larger than the reference voltage Vref, the control logic circuit110causes the process to go to S307. In S307, the control logic circuit110causes the comparison controller118to put the switch119in the on state, and resumes the supply of the voltage V2(electric power supply) to the block2, so that control by the calculating controller111is in a resumable state, and the process is returned to S301. As a result, the period changes from the rest period to the switching period. In the process of S307, the switch119is turned on depending on that the FB terminal voltage is discriminated as being larger than the reference voltage Vref (FBL2) by the comparison controller118, and this shows the intermittent control in (b) ofFIG. 3.

In S305, in the case where the control logic circuit110discriminated that the FB terminal voltage is not more than the reference voltage Vref, the control logic circuit110causes the process to go to S306. In S306, the control logic circuit110discriminates whether or not the longest rest period Toff_max set in S303has elapsed by the timer controller116. In S306, in the case where the control logic circuit110discriminated that the longest rest period Toff_max has elapsed, the control logic circuit110causes the process to go to S308. In S308, the control logic circuit110causes the timer controller116to put the switch119in the on state, and resumes the supply of the voltage V2(electric power supply) to the block2, so that control by the calculating controller111is in a resumable state, and the process is returned to S301. As a result, the period changes from the rest period to the switching period. In the process of S308, the switch119is turned on depending on the discrimination by the timer controller116that the longest rest period Toff_max has elapsed, and this shows the intermittent control in (c) ofFIG. 3. In S306, in the case where the control logic circuit110discriminated that the longest rest period Toff_max has not elapsed, the control logic circuit110returns the process to S305. As a result, the rest period is continued. By repeating the above-described control, the control logic circuit110effects the control of the digital control power source100.

The digital control power source100in this embodiment possesses the following features.

(1) In the low load state of the digital control power source100, the intermittent control in which the switching period and the rest period are repetitively provided is effected.

(2) In the rest period of the intermittent control, the sleep state in which the supply of the voltage V2to the block2of the control logic circuit110is stopped is formed.

(3) In the case where the rise of the FB terminal voltage is detected by the comparison controller118, the supply of the voltage V2to the block2of the control logic circuit110is resumed, and a state in which control by the calculating controller111is enable is formed, so that the rest period is changed to the switching period.

(4) In the case where the timer controller116discriminated that the longest rest period Toff_max has elapsed, the supply of the voltage V2to the block2of the control logic circuit110is resumed, and a state in which the control by the calculating controller111is enable is formed, so that the rest period is changed to the switching period.

Thus, the intermittent control is effected in the low load state of the digital control power source100, and during the rest period of the intermittent control, the control logic circuit110is put in the sleep state in which the control by the timer controller116is enable. As a result, the intermittent control can be suitably controlled, so that it is possible to effect control so that not only the efficiency in the low load state can be improved but also the operation of the controller (control logic circuit110, FET driving circuit120and the like) disposed in the primary side can be continued. As described above, according to this embodiment, not only the efficiency of the power source device in the low load state can be improved, but also the controller disposed in the primary side can continue the operation thereof.

[Control Method Using Active Clamp Type]

In a control method described in Embodiment 2, a difference from the control method described in Embodiment 1 is that control such that the intermittent control period is longer than a predetermined shortest intermittent control period Tmin is added. InFIG. 5, (a) to (c) are time charts each illustrating the control method of the digital control power source100using the active clamp type in this embodiment. The description of the continuous control state is the same as that described with reference to (a) ofFIG. 3and therefore will be omitted from description. In this embodiment, in the case where the FB terminal voltage exceeds FBL4which is the first value, the continuous control is effected. In (a), (b) and (c) ofFIG. 5, first intermittent control, second intermittent control and third intermittent control, respectively, in this embodiment will be described. Incidentally, inFIG. 5, (i) to (v) show the same waveforms, signals or the like as those inFIG. 3. In this embodiment, Vref (FBL3) which is the second value is a threshold used for switching the period from the rest period to the switching period in the second intermittent control described later.

In the control of (a) ofFIG. 5, the control is effected so that the intermittent control period is not excessively short, whereby control such that a high-frequency noise generated from the transformer T1in the intermittent control state of the digital control power source100is suppressed is effected. As described later with reference toFIG. 6, by using control by the timer controller116, Tmin is set as a shortest time of the intermittent control period. Hereinafter, Tmin is referred to as a shortest intermittent control period. In the intermittent control shown in (a) ofFIG. 5, on the basis of the FB terminal voltage, the control logic circuit110controls the number of times of switching of the FET1during the intermittent control period, whereby feed-back control of the voltage Vout outputted at the secondary side is effected. The control of (a) ofFIG. 5is the first intermittent control.

When the load state of the digital control power source100lowers from the load state of (a) ofFIG. 5, finally, control of decreasing the number of times of switching of the FET1to a predetermined number (once in this embodiment) is effected. Further, the load state of the digital control power source100lowers, and in the case where the FB terminal voltage lowers to not more than Vref (FBL3), the control of the control logic circuit110changes to the control of (b) ofFIG. 5. For example, in the switching period, the control logic circuit110effects control such that is turns on the FET2and then turns on the FET1, and thereafter turns on the FET2.

In the control of (b) ofFIG. 5, the number of times of switching during the intermittent control period is a predetermined number (once in this embodiment). In the control of (b) ofFIG. 5, control is effected in such a manner that the FET2is turned on and then the FET1is turned on once, and thereafter the FET2is turned, so that the length of the intermittent control period is controlled. As a result, feed-back control of the voltage Vout outputted at the secondary side is effected. The control logic circuit110continues the rest period of the intermittent control until a voltage higher than the reference voltage Vref (FBL3) set in the comparison controller118is detected after a lapse of the shortest intermittent control period Tmin. The control described with reference to (b) ofFIG. 5is the second intermittent control.

In the control shown in (c) ofFIG. 5, similarly as in the intermittent control described with reference to (c) ofFIG. 3, a control method of supplying the voltage V1in the no load state of the digital control power source100is carried out. In the control shown in (c) ofFIG. 5, the number of times of switching during the intermittent control period is determined by control in which the FET2is turned on and then the FET1turned on once, and then the FET2is turned on again, and control in which the rest period is the longest rest period Toff_max.

In the control shown in (c) ofFIG. 5, the on-time of the FET2is a fixed time, and the control logic circuit110effects, on the basis of the FB terminal voltage, the feed-back control of the V Vout outputted at the secondary side by controlling the on-time of the FET1. Incidentally, the on-time of the FET2may also be changed and may only be required to be controlled so that the ratio of the on-time of the FET1to the on-time of the FET2lowers. As regards the method of supplying the electric power to the auxiliary winding P2of the transformer T1without increasing the voltage Vout outputted at the secondary side, the method is similar to the method of (c) ofFIG. 3, and therefore will be omitted from description. The control described in (c) ofFIG. 5is the third intermittent control.

As described above, in this embodiment, the continuous control is effected in the case where the FB terminal voltage exceeds FBL4(FBL4<(FB terminal voltage)) and is changed to the first intermittent control in the case where the FB terminal voltage is not more than FBL4(FBL4≥(FB terminal voltage)). Further, in this embodiment, the period is changed to the rest period in the second intermittent control in the case where the FB terminal voltage is not more than Vref (FBL3) (FBL3≥(FB terminal voltage)). Further, in this embodiment, the period is changed to the switching period in the second intermittent control in the case where the FB terminal voltage is larger than Vref (FBL3) (FBL3>(FB terminal voltage)).

[Control in this Embodiment]

FIG. 6is a flowchart for illustrating a control sequence of the digital control power source100by the control logic circuit110in this embodiment. A method in which the first intermittent control, the second intermittent control and the third intermittent control described with reference toFIG. 5are effected by the control logic circuit110will be described. An AC power source10is connected with the digital control power source100, and when a state in which the electric power is supplied to the digital control power source100is formed, the control logic circuit110starts the following control. In S501, on the basis of the FB terminal voltage, the control logic circuit110effects control of the switching period in which the on-times of the FETs1,2described with reference to (a) ofFIG. 3are controlled (continuous control state). In S502, the control logic circuit110discriminates whether or not the FB terminal voltage is larger than the predetermined value FBL4. In S502, in the case where the control logic circuit110discriminated that the FB terminal voltage is larger than FBL4, the control logic circuit110returns the process to S501and continuous the switching period (continuous control state). In S502, in the case where the control logic circuit110discriminated that the FB terminal voltage is not more than FBL4, the control logic circuit110causes the process to go to S503.

In S503, the control logic circuit110causes the calculating controller111to set a predetermined value α as the rest period Toff in the timer controller116, and the measurement of the time is started. Here, the rest period α is set as a period sufficiently shorter than the shortest intermittent control period Tmin described later (α<<Tmin) so as not to lower a load response characteristic of the digital control power source100, and is used as a rest period during the change from the continuous control to the intermittent control.
Rest timeToff=α(fixed value)
In S504, the control logic circuit110causes the calculating circuit110to put the switch119in the off state, so that the supply of the voltage V2(electric power supply) to the block2is stopped (terminated).
(First Intermittent Control)

The first intermittent control method described with reference to (a) ofFIG. 5are shown in S505-S511. In S505, the control logic circuit110discriminates, by the timer controller116, whether or not the rest period Toff has elapsed. In S505, in the case where the control logic circuit110discriminated that the rest period Toff has not elapsed, the control logic circuit110returns the process to S505, and in the case where the control logic circuit110discriminated that the rest period Toff has elapsed, the control logic circuit110causes the process to go to S506. In S506, the control logic circuit110causes the timer controller116to put the switch119in the on state and resumes the supply of the voltage V2to the block2, so that the control logic circuit110puts the calculating controller111in a state in which the control is resumable.

In S507, the control logic circuit110discriminates, by the timer controller116, whether or not the FB terminal voltage is larger than FBL4, and in the case where the control logic circuit110discriminated that the FB terminal voltage is larger than FBL4, the control logic circuit110returns the process to S501, and changes in state to the continuous control state. In S507, in the case where the control logic circuit110discriminated that the FB terminal voltage is not more than FBL4, the control logic circuit110causes the process to go to S508.

In S508, the control logic circuit110discriminates, by the timer controller116, whether or not the FB terminal voltage is larger than Vref (FBL3). In S508, in the case where the control logic circuit110discriminated that the FB terminal voltage is larger than Vref (FBL3), the control logic circuit110causes the process to go to S509, and in the case where the control logic circuit110discriminated that the FB terminal voltage is not more than FBL3, the control logic circuit110causes the process to go to S512. In S512, the control logic circuit110changes in control to the second intermittent control or the third intermittent control.

In S509, the control logic circuit110effects the first intermittent control in which the number of times of switching is controlled on the basis of the FB terminal voltage ((a) ofFIG. 5). The switching period in the first intermittent control is controlled so that the switching period is started by the turning-on of the FET2and is ended by the turning-off of the FET2. In the first intermittent control in S509, the control logic circuit110effects the control so that the number of times of switching is larger with a higher FB terminal voltage and is smaller with a lower FB terminal voltage. The control logic circuit110controls the FET1and the FET2depending on the number of times of switching on the basis of the FB terminal voltage, and when the switching period is ended, the control logic circuit110causes the process to go to S510.

In S510, the control logic circuit110causes the timer controller116to set the rest period Toff so that a predetermined intermittent control period in the first intermittent control is Tmin. Here, the control logic circuit110measures a length of the switching period in the intermittent control by using an unused timer of the timer controller116or calculates the switching period length from the number of times of switching set in S509and the on-times of the FETs1,2((a) ofFIG. 5). For this reason, the rest period Toff which is the second time in the first intermittent control such that the intermittent control period is the shortest intermittent control period Tmin is obtained from the shortest intermittent control period Tmin being a known value and the switching period in accordance with the following formula.
Rest periodToff=Tmin(shortest intermittent control period)−(switching period)

In S511, the control logic circuit110causes the calculating controller111to put the switch119in the off state and stop the supply of the voltage to the block2, and returns the process to S505. Thus, the control logic circuit110repetitively effects the control of S505to S511, so that the control logic circuit110carries out the first intermittent control of the digital control power source100. In the first intermittent control, the intermittent control period is not shorter than the shortest intermittent control period, and therefore the high-frequency noise of the transformer T1can be reduced.

(Second Intermittent Control Method and Third Intermittent Control Method)

The second intermittent control method and the third intermittent control method which are described with reference to (b) ofFIG. 5and (c) ofFIG. 5, respectively, will be described using s512to S520. In S512, the control logic circuit110causes the calculating controller111to set the longest rest period Toff_max in the timer controller116. In S513, the control logic circuit110causes the calculating circuit110to put the switch119in the off state, so that the supply of the voltage V2to the block2is stopped (terminated).

In S514, the control logic circuit110discriminates whether or not the FB terminal voltage is larger than the reference voltage Vref (FBL3) by the comparison controller118. In S514, in the case where the control logic circuit110discriminated that the FB terminal voltage is larger than the reference voltage Vref (FBL3), the control logic circuit110causes the process to go to S516, and changes in control to the second intermittent control of S516and S517((b) ofFIG. 5).

In S514, in the case where the control logic circuit110discriminated that the FB terminal voltage is not more than the reference voltage Vref, the control logic circuit110causes the process to go to S515. In S515, the control logic circuit110discriminates whether or not the rest period Toff set in S512, i.e., Toff_max, has elapsed by the timer controller116. In S515, in the case where the control logic circuit110discriminated that the rest period Toff (the longest rest period Toff_max) has not elapsed, the control logic circuit returns the process to S514and continues the rest period, and then repetitively effects the control of S514and S515. In S515, in the case where the control logic circuit110discriminated that the rest period Toff (the longest rest period Toff_max) has elapsed, the control logic circuit110causes the process to go to S519and changes in control to the third intermittent control of S519and S520((c) ofFIG. 5).

The switching period control method in the second intermittent control described using (b) ofFIG. 5will be described. In S516, the control logic circuit110causes the comparison controller118to put the switch119in the on state and resumes the supply of the voltage V1to the block2, and thus in a state in which the control of the calculating controller111resumable. In S517, the control logic circuit110subjects the FETs1,2to the switching control by a predetermined number of times. For example, in this embodiment, as shown in (b) ofFIG. 5, control such that the FET2is turned on and then the FET1is turned on once, and then the FET2is turned on again is effected. In S517, the control logic circuit110controls the FET1in a determined on-time by the predetermined number of times, and therefore controls the electric power by controlling the switching period length.

In S518, the control logic circuit110causes the timer controller116to set a fixed value σ as the rest period Toff, and causes the process to go to S511. The rest period σ is set as a period sufficiently shorter than the shortest intermittent control period Tmin so as not to lower the load response characteristic of the digital control power source100, and is used as a rest period when the switching periods of the second intermittent control and the third intermittent control are ended. Incidentally, strictly, the rest period Toff is Toff_max+σ, but σ is the period sufficiently shorter than Toff_max. For this reason, in (c) ofFIG. 5, only Toff_max is shown. Further, in S518, similarly as in S510, a process of setting the rest period Toff from the shortest intermittent control period Tmin and the switching period (the period of S517in this case) may also be carried out.

Next, the switching period control method in the third intermittent control described using (c) ofFIG. 5will be described. In S519, the control logic circuit110causes the timer controller116to put the switch119in the on state, and resumes the supply of the voltage V2(electric power supply) to the block2. In S520, the control logic circuit110effects the switching control so as to turn on the FETs1,2by the predetermined number of times, and causes the process to go to S518. For example, in this embodiment, as shown in (c) ofFIG. 5, control such that the FET2is turned on and then the FET1is turned on once, and then the FET2is turned on again is carried out. In the third intermittent control, the control logic circuit110effects control so that the on-time of the FET2is fixed, and the on-time of the FET is made variable on the basis of the FB terminal voltage. Specifically, the control logic circuit110determines the on-time so that the on-time of the FET1is longer with a higher FB terminal voltage and is shorter with a lower FB terminal voltage, and thus effects control. In S520, the control logic circuit110effects control of the electric power by controlling the on-time of the FET1since the rest period is fixed (Toff_max).

By repetitively effecting the above-described control of S501to S520, the control logic circuit110carries out the continuous control, the first intermittent control, the second intermittent control and the third intermittent control of the digital control power source100.

Thus, in the control method described in this embodiment, the intermittent control period in the first intermittent control can be suitably controlled while reducing the electric power consumption of the control logic circuit110by the control using the timer controller116described using (a) ofFIG. 5. Further, the control method described in this embodiment can prevent the high-frequency noise by the transformer T1. In this embodiment, in the first intermittent control, the intermittent control period is the fixed period Tmin.

The control method of the digital control power source100described usingFIGS. 5 and 6in this embodiment possesses the following features in addition to the features described in Embodiment 1.

(1) The intermittent control period is controlled by the timer controller116so as to be longer than the shortest intermittent control period Tmin.

(2) When the intermittent control is effected using the shortest intermittent control period Tmin, it is possible to carry out the first intermittent control in which the feed-back control of the power source voltage Vout outputted at the secondary side is effected by controlling the number of times of switching of the FET1per (one) period.

(3) In the case where the rise of the FB terminal voltage is detected by the comparison controller118, the rest period is changed to the switching period, and the second intermittent control in which the switching control of the FETs1,2is carried out by the predetermined number of times can be effected.

(4) In the case where the timer controller116discriminated that the longest rest period Toff_max has elapsed, the rest period is changed to the switching period, and the third intermittent control in which the switching control of the FETs1,2is carried out by the predetermined number of times can be effected.

Thus, in this embodiment, the intermittent control is effected in the low load state of the digital control power source100, and during the rest period of the intermittent control, the control logic circuit110is put in the sleep state in which the control by the timer controller116is enable. As a result, the intermittent control can be suitably controlled, so that it is possible to effect control so that not only the efficiency in the low load state can be improved but also the high-frequency noise of the transformer can be prevented and the operation of the controller (control logic circuit110, FET driving circuit120and the like) disposed in the primary side can be continued. As described above, according to this embodiment, not only the efficiency of the power source device in the low load state can be improved, but also the controller disposed in the primary side can continue the operation thereof.

A digital control power source600in Embodiment 3 will be described.FIG. 7Ais a circuit diagram of a power source device in this embodiment, andFIG. 7Bis a schematic view of a control logic circuit in this embodiment. The digital control power source600has a power source constitution of a flyback type using a surge absorbing circuit620in place of the active clamp circuit using the FET2and the capacitor C2for the voltage clamp as in Embodiments 1 and 2. Further, a control logic circuit610of the digital control power source600has a constitution in which the comparison controller118in Embodiments 1 and 2 is not used. A control method using the timer controller116and the AD converting portion114in place of the comparison controller118will be described. For this reason, the reference voltage Vref inputted into the comparison controller118is not used. Constituent elements similar to those inFIG. 1are represented by the same reference numerals or symbols and will be omitted from description.

The digital control power source600has a constitution in which only the FET1is used as the switching element. A serge voltage generating when the FET1is turned off is absorbed by the serge absorbing circuit620constituted by a snubber circuit or the like.

The control logic circuit610of the digital control power source600effects, on the basis of the FB terminal voltage, the feed-back control of the power source V Vout outputted at the secondary side by controlling the on-time of the FET1.

The control logic circuit610is a low-functional CPU which does not include the comparison controller1118compared with the control logic circuit110in Embodiments 1, 2. Further, the timer controller116has not only the function of controlling the rest period Toff described in Embodiments 1, 2 but also the function of outputting the PWM control signal used for generating the PWM signal in the switching period by the PWM outputting portion117. Further, compared with the control logic circuit110in Embodiments 1, 2, the control logic circuit610in this embodiment does not include also the VS terminal, and thus does not detect the input voltage Vin.

[Control in this Embodiment]

FIG. 8is a flowchart for illustrating a control sequence of the digital control power source600by the control logic circuit610in this embodiment. InFIG. 8, a method in which the intermittent control of the digital control power source600will be described by using the control logic circuit600which does not include the comparison controller118. An AC power source10is connected with the digital control power source600, and when a state in which the electric power is supplied to the digital control power source600is formed, the control logic circuit610starts the following control. Further, the control logic circuit610initializes a counter N described later in advance. In S701, on the basis of the FB terminal voltage, the control logic circuit610effects PWM control (control of the switching period) of the FET1. In this embodiment, the timer controller116generates the PWM control signal and outputs the PWM control signal to the PWM outputting portion117. The PWM control signal has a fixed cyclic period, and on the basis of a value (set value) set by the calculating controller111, duty control of the on-time of the FET1is carried out. In S702, the control logic circuit610discriminates whether or not the FB terminal voltage is larger than the predetermined value FBL1. In S702, in the case where the control logic circuit610discriminated that the FB terminal voltage is larger than FBL1, the control logic circuit610returns the process to S701and continuous the switching period (continuous control state). In S702, in the case where the control logic circuit610discriminated that the FB terminal voltage is not more than FBL1, the control logic circuit610causes the process to go to S703.

In S703, the control logic circuit610causes the calculating controller111to set a detection period Tad which is a third time of AD conversion in the timer controller116. At this time, the control logic circuit610switches the function of the timer controller116from the function of generating the PWM control signal to the function of controlling the rest period in the intermittent control. The control signal D1outputted from the PWM outputting portion117during the rest period is kept at a low level. In S704, the control logic circuit110causes the calculating circuit110to put the switch119in the off state, so that the supply of the voltage V2(electric power supply) to the block2is stopped (terminated).

In S705, the control logic circuit610discriminates, by the timer controller116, whether or not the AD conversion detection period Tad has elapsed. In S705, in the case where the control logic circuit610discriminated that the detection period Tad has not elapsed, the control logic circuit610returns the process to S705, and in the case where the control logic circuit610discriminated that the detection period Tad has elapsed, the control logic circuit610causes the process to go to S706. In S706, the control logic circuit610causes the timer controller116to put the switch119in the on state and resumes the supply of the voltage V2to the block2, so that the control logic circuit110puts the calculating controller111in a state in which the control is resumable. Further, by the process of S706, also the AD converting portion114and the calculating controller111are operable. Then, by the AD converting portion114and the calculating controller111, discrimination based on the FB terminal voltage can be carried out.

In S707, the control logic circuit610discriminates, on the basis of a detection result of the AD converting portion114, whether or not the FB terminal voltage is larger than FBL2. This control is equivalent to the control using the reference voltage Vref by the comparison controller118described using (b) ofFIG. 3, and the reference voltage Vref=FBL2. In S707, in the case where the control logic circuit610discriminated that the FB terminal voltage is larger than FBL2, the control logic circuit610causes the process to go to S710. In S710, the control logic circuit610resets the counter N (N=0), and thereafter returns the process to S701, and then changes in period to the switching period. At this time, the control logic circuit610switches the function of the timer controller116from the function of controlling the rest period in the intermittent control to the function of generating the PWM control signal.

In S707, in the case where the control logic circuit610discriminated that the FB terminal voltage is not more than the predetermined voltage, specifically not more than FBL2, the control logic circuit610causes the process to go to S708, and increments the counter N by 1 (N=N+1) in S708. In S709, the control logic circuit610discriminates whether or not a value obtained by multiplying the counter N by the AD conversion detection period Tad (i.e., N×Tad) is larger than the longest rest period Toff_max. As a result, the control logic circuit610discriminates whether or not the longest rest period Toff_max has elapsed. In S709, in the case where the control logic circuit610discriminated that the voltage obtained by multiplying the counter N by the detection period Tad is larger than the longest rest period Toff_max, i.e., that the longest rest period Toff_max has elapsed, the control logic circuit610causes the process to go to S710. In S709, in the case where the control logic circuit610discriminated that the voltage obtained by multiplying the counter N by the detection period Tad is not more than the longest rest period Toff_max, i.e., that the longest rest period Toff_max has not elapsed, the control logic circuit610returns the process to S703, and continues the rest period. By repetitively carrying out the control of S701to S710described above, the control logic circuit610effects the control of the digital control power source600.

Incidentally, in the control shown inFIG. 8, there is a need to resume the electric power supply to the block2of the control logic circuit610for each of the AD conversion detection periods during the rest period in the intermittent control. For this reason, compared with the control logic circuit110described in Embodiments 1, 2, there is a liability that the electric power consumption of the control logic circuit610increases. Further, when the detection period is set to be long, there is liability that responsiveness to the output voltage Vout of the digital control power source100lowers. For that reason, the control using the comparison controller118as in the case of the control logic circuit110is suitable control. However, as in the case of the control logic circuit610, in the case were an inexpensive microcomputer or the like which does not have the function of the comparison controller118, the control method described usingFIG. 8is effective.

The digital control power source600described usingFIG. 7in this embodiment possesses the following features in addition to the features of the method described in Embodiment 1.

(1) The control of the rest period in the intermittent control is effected by using the timer controller116and the AD converting portion114in combination in place of the comparison controller118.

(2) The single timer function of the timer controller116is used for the control of the PWM outputting portion117and the control of the rest period of the intermittent control in combination.

Further, as described in this embodiment, the intermittent control method in this embodiment is also applicable to the digital control power source600which does not include the active clamp circuit (the FET2and the voltage clamping capacitor C2).

Incidentally, the control using the control logic circuits110,810,820in Embodiments 1, 2 is also applicable to the digital control power source600of the flyback type in Embodiment 3. Further, the control using the control logic circuit610in Embodiment 3 is also applicable to the digital control power source100of the active clamp type in Embodiments 1, 2. Further, the control logic circuits110,810,820in Embodiments 1, 2 and the control logic circuit610in Embodiment 3 are also applicable to control of various power sources such as a power source of a forward type, a power source of a current resonance type, and a forward power source of an active clamp type. As described above, according to this embodiment, not only the efficiency of the power source device in the low load state can be improved, but also the controller disposed in the primary side can continue the operation thereof.

The digital control power sources100,600as the power source devices described in Embodiments 1 to 3 are applicable to a low-voltage source of the image forming apparatus, i.e., a power source for supplying electric power to a driving portion such as a controller or a motor. In the following, a constitution of an image forming apparatus to which the power source devices of Embodiments 1 to 3 are applicable.

As an example of the image forming apparatus, a laser beam printer will be described.FIG. 9illustrates a schematic structure of the laser beam printer which is an example of an electrophotographic printer. A laser beam printer300includes a photosensitive drum311as an image bearing member for forming an electrostatic latent image, a charging portion (charging means)317for electrically charging the photosensitive drum311uniformly, and a developing portion (developing means)312for developing, with a toner, the electrostatic latent image formed on the photosensitive drum311. The toner image formed on the photosensitive drum311is transferred by a transfer portion (transfer means)318onto a sheet (not shown) as a recording material supplied from a cassette316, and then the toner image transferred on the sheet is fixed by a fixing device314and thereafter the sheet is discharged onto a tray315. The photosensitive drum310, the charging portion317, the developing portion312and the transfer portion318constitute an image forming portion. Further, the laser beam printer300includes a power source device400having the same constitution as those of the digital control power sources100,600as described in Embodiments 1 to 3. The image forming apparatus to which the power source device400in Embodiments 1 to 3 applicable is not limited to the image forming apparatus shown inFIG. 9, but may also be an image forming apparatus including a plurality of image forming portions, for example. The image forming apparatus may also be an image forming apparatus including a primary transfer portion where the toner image is transferred from the photosensitive drum311onto an intermediary transfer belt and a secondary transfer portion where the toner image is transferred from the intermediary transfer belt onto the sheet.

The laser beam printer300includes a controller320for controlling an image forming operation by the image forming portion and a sheet feeding operation, and the power source device supplies electric power to the controller320, for example. Further, the power source device400supplies the electric power to a motor or the like for driving various rollers for rotating the photosensitive drum311for feeding the sheet. In the case where the power source device400in this embodiment is the digital control power sources100,600, in Embodiments 1 to 3, the following control is effected. The control logic circuit110causes the timer controller116to put the switch119in the on state so that the rest period in the intermittent control is not longer than the longest rest period, so that the period thereof changes to the switching period. As a result, not only the efficiency in the low load state can be improved, but also the controller disposed in the primary side can continue the operation thereof. Further, the power source device400in this embodiment is the digital control power source100in Embodiment 2, the following control is effected. The control logic circuit110effects control so that the intermittent control period in the intermittent control is not shorter than the shortest intermittent control period Tmin. As a result, not only the efficiency in the low load state can be improved, but also the controller disposed in the primary side can continue the operation thereof, and it is also possible to reduce the high-frequency noise. Further, in the case where the power source device400is the digital control power source600in Embodiment 3, the control can also be effected by the control logic circuit610using the inexpensive microcomputer or the like which does not include the comparison controller.

Further, the image forming apparatus in this embodiment is operable in the normal operation mode, the stand-by mode and the sleep mode. For example, the normal operation mode corresponds to the mode of (a) ofFIG. 3. In the stand-by mode, the image forming operation can be carried out soon when the image forming apparatus receives the print instruction, while reducing the electric power consumed in the mode compared with the normal operation mode. For example, the stand-by mode corresponds to the mode of (b) ofFIG. 3. In the sleep mode, the electric power consumed in the mode is further reduced compared with the stand-by mode. For example, the sleep mode corresponds to the mode of (c) ofFIG. 3. As described above, according to this embodiment, it is possible to not only improve the electric power of the power source device in the low load state but also realize continuation of the operation of the controller disposed in the primary side.

This application claims the benefit of Japanese Patent Application No. 2015-247609 filed on Dec. 18, 2015, which is hereby incorporated by reference herein in its entirety.