Pulse train conditioning circuits and related methods

Pulse train conditioning circuits and related methods are disclosed. An example circuit includes a first transistor having a first current terminal and a first gate terminal, a second transistor having a second current terminal and a second gate terminal, a third transistor having a third current terminal and a third gate terminal, a fourth transistor having a fourth current terminal and a fourth gate terminal, the fourth gate terminal coupled to the first through third gate terminals, a first switch having first through third terminals, the first terminal coupled to the first current terminal, the second terminal coupled to the third current terminal, and the third terminal coupled to the fourth current terminal, and a second switch having fourth through sixth terminals, the fourth terminal coupled to the second current terminal, the fifth terminal coupled to the third current terminal, and the sixth terminal coupled to the fourth current terminal.

FIELD OF THE DISCLOSURE

This disclosure relates generally to pulse train conditioning circuits and, more particularly, to pulse train conditioning circuits and related methods.

BACKGROUND

Electronic circuits have a propagation or time delay between inputs and outputs. Time delays may vary within an integrated circuit due to manufacturing process variations. Time delays within an integrated circuit associated with a power converter can affect operation of the power converter. Trim circuits can be utilized in the integrated circuit associated with the power converter to adjust time delays to affect the operation of the power converter.

DETAILED DESCRIPTION

The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. Connection references (e.g., attached, coupled, connected, and joined) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and in fixed relation to each other.

Integrated circuits are electrical circuits composed of individual electrical components or elements. The elements must be properly connected to each other to form an interconnect network. Through the interconnect network, an element may obtain an input signal and process the input signal to generate an output signal. The output signal may be transmitted to another element within the interconnect network. An integrated circuit operation to obtain, process, generate, and/or transmit a signal can cause propagation delay in connection with the signal.

The propagation delay of a signal is a relatively small, yet finite, amount of time between the input and the output of an element. To control propagation delay, integrated circuits may include trim circuits that include trimmable delay elements to harmonize delay between integrated circuits. For example, different integrated circuits may generate similar outputs with different delays as a result of variations in manufacturing. The trim circuits may be used to adjust the different delays to be within a specified tolerance so that the different delays are substantially similar.

In some instances, a trim circuit may switch between different states to affect an output of the trim circuit. A first state may correspond to charging a capacitor (e.g., charging a fully discharged capacitor) included in the trim circuit and a second state may correspond to discharging the capacitor (e.g., discharging a fully charged capacitor). Active switching elements may control the transition between states to increase or decrease a delay of transmitting a signal to a different circuit, device, etc., such as a gate driver, a power converter, etc., coupled to the trim circuit.

Conventional trim circuits including a first trim circuit and a second trim circuit may provide selectable delay but require a significant number of elements for resolution at larger delay values. The first trim circuit may be a voltage-based delay circuit. Disadvantageously, once a delay trim associated with the first trim circuit is completed, the delay trim becomes fixed and cannot be changed for each application and/or with variations in temperature. Accordingly, the first trim circuit is a static trim circuit and cannot be changed in operation. The second trim circuit may be a current-based delay circuit. Disadvantageously, both the first and second trim circuits may consume a relatively large portion of an integrated circuit to implement exponential delay variation. Advantageously, examples disclosed herein improve conventional trim circuits, such as the first and second trim circuit, by providing dynamically selectable and dynamically continuous delay control with a significantly smaller area compared to the conventional trim circuits.

The first trim circuit may include a chain of digital or resistor-capacitor (RC) unit delays with trim. The first trim circuit may provide selectable delay, where the delay is dependent on component parameters. An output from the first trim circuit may vary with manufacturing and/or temperature variations. Accordingly, cumulative error and/or variations may be relatively large in instances where multiple ones of the first trim circuit are in series. In some instances, the first trim circuit may have a large dynamic range as a result of the first trim circuit having a correspondingly large area to implement linear delay variation. In such instances, the first trim circuit can have a greater dynamic range by increasing the quantity of components included in the first trim circuit that, in turn, increases the area of the first trim circuit.

The second trim circuit may include a current-based digital-to-analog converter (DAC) delay circuit. The second trim circuit may provide a selectable and continuous delay. In some instances, the second trim circuit may control delay better than the first trim circuit because the second trim circuit can control delay based on current, unlike the aforementioned first trim circuit that is RC based, which is affected by process and/or temperature variations. Like the first trim circuit, the second trim circuit may have a large dynamic range as a result of the second trim circuit having a correspondingly large area to implement exponential delay variation.

Example delay circuits (e.g., pulse train conditioning circuits) disclosed herein reduce pulse delay differences between integrated circuit dies and/or between batches of integrated circuit dies as a result of application level delay choice, manufacturing variations, temperature variations, etc. Example delay circuits disclosed herein can reduce pulse delay differences by providing exponential delay variation for selectable delay control and using current for continuous delay control.

Example delay circuits disclosed herein implement exponential delay variation by controlling a delay of a signal (e.g., a rising edge of a signal, a falling edge of a signal, etc.) based on an approximation of an exponential function. For example, the delay circuits can generate a non-linear change in delay output based on a linear change in selection input. Example delay circuits disclosed herein include one or more switches, such as transistors, for the selectable delay control. For example, one or more switches can be disabled, enabled, etc., to select a specified delay of an output. In such examples, the delay circuits can generate the non-linear change in delay output by making a linear adjustment, such as turning on, turning off, etc., one or more of the one or more switches. Example delay circuits disclosed herein include dynamically adjustable one or more current sources. For example, the delay circuits disclosed herein can facilitate the continuous delay control by adjusting the one or more current sources.

Example delay circuits disclosed herein utilize exponential delay variation to reduce area (e.g., a portion of area available to an integrated circuit, a portion of area included in an integrated circuit, etc.) compared to areas associated with the first or second trim circuits described above. For example, to achieve a 10-bit delay range with 5-bit control, example delay circuits disclosed herein can include 32 units (e.g., 32 transistors, 32 circuits, etc.) in an example exponential delay variation delay circuit. In such examples, the 32 circuits are less than 1024 units needed to achieve the same 10-bit delay range using the first or second trim circuits described above. As the first and second trim circuits implement linear control, the first and second trim circuits need 10-bit control (e.g., 1024 units) to implement a 10-bit delay range. Advantageously, the example delay circuits disclosed herein can include a fewer number of transistors and/or other hardware components than may be required to implement the first or second trim circuits as described above.

Example delay circuits disclosed herein can control a delay on one or both edges (e.g., a rising edge, a falling edge, etc.) of a signal (e.g., a pulse) by controlling a discharge time of capacitors. For example, the delay circuits can include current mirrors to control one or more transistors operative as current sinks to discharge capacitors of the delay circuits at a controlled rate to provide delay at one or both edges.

In some disclosed examples, switches of the delay circuits are set based on a switch setting code obtained from trim memory. For example, the switches can control transistors to generate a current ratio to control a delay of a signal (e.g., a power converter enable signal to be transmitted to a power converter). In such examples, the current ratio can provide the exponential delay variation for the selectable control delay. The controller can control the switches to generate a current ratio that can sweep a dynamic delay range based on the approximation of the exponential function. For example, the controller can control a trim circuit to configure and/or otherwise set the switches in a desired configuration.

FIG. 1depicts an example implementation of a power conversion system100including a power converter102and a gate driver104including delay logic106to control operation of the power converter102. InFIG. 1, the power conversion system100includes an example controller108to control and/or otherwise invoke the gate driver104to turn off, turn on, etc., the power converter102.

In the illustrated example ofFIG. 1, the controller108is coupled to the gate driver104via one or more pins (e.g., integrated circuit (IC) pins), one or more electrical contacts, etc., and/or a combination thereof. In some examples, the controller108can be implemented using hardware logic, machine readable instructions, hardware implemented state machines, etc., and/or a combination thereof. For example, the controller108can be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)). In other examples, the controller108can be implemented using a transconductance amplifier (i.e., a GM amplifier).

In the illustrated example ofFIG. 1, an example current generator110transmits an example current IS114to control a first example gate drive circuit112A included in the gate driver104. For example, the current generator110can correspond to a resistor or other discrete hardware component on a printed-circuit board on which the gate driver104is included. In such examples, the current IS114can be set external to the gate driver104while the current IS114can be sensed and/or otherwise measured internally to the gate driver104.

In the illustrated example ofFIG. 1, the controller108includes an example control signal generator116to control the first gate drive circuit112A. InFIG. 1, the control signal generator116generates an example control signal118and transmits the control signal118to the delay logic106included in the first gate drive circuit112A. InFIG. 1, the control signal118is a square-wave signal that corresponds to a gate drive input. Alternatively, the control signal118may be any other type of pulse signal.

In the illustrated example ofFIG. 1, the power conversion system100includes the power converter102to convert a first example voltage (V_IN) (e.g., an input voltage)122to a second example voltage (V_OUT) (e.g., an output voltage)124. InFIG. 1, the power converter102is coupled to an example load125. For example, the load125can correspond to an electric vehicle, one or more batteries in the electric vehicle, an electric motor in the electric vehicle, a traction inverter included in the electric vehicle, etc.

In the illustrated example ofFIG. 1, a first current terminal (e.g., a source, a source terminal, etc.)130of the first transistor126is coupled to a second current terminal (e.g., a drain, a drain terminal, etc.)132of the second transistor128. InFIG. 1, the first current terminal130and the second current terminal132are coupled to a first end of an example inductor134having an inductance of L_OUT. InFIG. 1, a second end of the inductor134is coupled to a first end of an example capacitor136having a capacitance of C_OUT. InFIG. 1, the second transistor128and a second end of the capacitor136are coupled to an example reference voltage rail (e.g., a ground rail)138.

In the illustrated example ofFIG. 1, the gate driver104is coupled to the power converter102. InFIG. 1, the gate driver104includes (1) the first gate drive circuit112A to control the first transistor126and (2) a second example gate drive circuit112B to control the second transistor128. InFIG. 1, the first gate driver circuit112A and the second gate drive circuit112B are integrated circuits. InFIG. 1, the second gate drive circuit112B is a copy or an instance of the first gate drive circuit112A. Alternatively, the second gate drive circuit112B may be different from the first gate drive circuit112A.

In the illustrated example ofFIG. 1, the first gate drive circuit112A includes the delay logic106, an example trim circuit140, and an example gate drive142. InFIG. 1, the delay logic106is a circuit (e.g., a delay circuit, a delay logic circuit, etc.). For example, the delay logic106can include one or more components (e.g., a resistor, a capacitor, etc.), one or more amplifiers (e.g., a differential amplifier, an operational amplifier, etc.), one or more transistors, etc., and/or a combination thereof.

In the illustrated example ofFIG. 1, the first gate drive circuit112A includes the delay logic106to delay transmission, propagation, etc., of the control signal118to the gate drive142using selectable control to generate exponential-type or based delay (e.g., an exponential delay, an approximated exponential delay, a substantially exponential delay, etc.). In some examples, the delay logic106includes a plurality of switches coupled to a respective transistor to adjust a rate of discharging of a charge storage element or device (e.g., a capacitor). For example, the delay logic106can implement the selectable control by opening, closing, etc., one or more of the plurality of switches to adjust a discharge current path from the capacitor, etc. In such examples, the delay logic106can generate the exponential delay based on an arrangement, coupling, structuring, etc., of the plurality of the transistors included in the delay logic106.

In some examples, the trim circuit140stores a configuration (e.g., a trim configuration, a delay configuration, etc.), a setting (e.g., a trim setting, a delay setting, etc.), etc. For example, the trim circuit140can be set and/or otherwise configured by an IC manufacturer, an end-user, a customer, etc. InFIG. 1, the trim circuit140is coupled and/or otherwise in circuit or communication with an example computing system141. For example, the computing system141can be a mobile device (e.g., an Internet-enabled smartphone or table), a laptop computer, a server, etc. In such examples, the computing system141can include, correspond to, and/or otherwise be representative of automated test equipment.

In some examples, the trim circuit140includes memory (e.g., trim memory) that stores one or more digital words. For example, the trim memory can correspond to a set of one or more registers that can each be loaded with a number (e.g., a trim) to determine a delay based on specified conditions. In some examples, the one or more digital words can be 5-bit digital words representative of 5-bit codes. For example, the computing system141can transmit a command, a machine readable instruction, etc., representative of a 5-bit digital word (e.g., ‘00101’) to the trim circuit140. In such examples, in response to obtaining the command, the trim circuit140can determine the 5-bit digital word based on the command (e.g., based on interpreting signal(s) corresponding to the command) and store the 5-bit digital word in the trim memory.

In some examples, the trim circuit140controls the plurality of switches based on a trim setting corresponding to the one or more digital words. For example, the trim circuit140can determine a 5-bit digital word of ‘00101’ based on the command. In such examples, the trim circuit140can map the 5-bit digital word of ‘00101’ to a trim setting that corresponds to a quantity of switches to control. For example, the trim circuit140can map the 5-bit digital word of ‘00101’ to a quantity of 32 switches to control. In such examples, the trim circuit140can control switches to couple transistors associated with a capacitor to increase or decrease a discharge rate of the capacitor. Advantageously, the delay logic106can selectively control an increase or a decrease of a delay in transmitting the control signal118based on a quantity of transistors adaptively coupled to the capacitor. Advantageously, the delay logic106can facilitate non-linear changes in delay in response to linear, discrete, or incremental changes in a quantity of the transistors to be coupled to the capacitor.

In the illustrated example ofFIG. 1, the trim circuit140is a circuit. For example, the trim circuit140can include one or more components (e.g., a resistor, a capacitor, etc.), one or more amplifiers (e.g., a differential amplifier, an operational amplifier, etc.), one or more transistors, etc., and/or a combination thereof. InFIG. 1, the gate drive142is a circuit. For example, the gate drive142can include one or more FETs, one or more bipolar junction transistors (BJTs), etc. An output of the trim circuit140is coupled to a first input of the delay logic106.

In the illustrated example ofFIG. 1, a first output of the delay logic106is coupled to a first input of the gate drive142. InFIG. 1, a first output of the gate drive142is coupled to a first example gate (e.g., a gate terminal)144of the first transistor126. InFIG. 1, an output of the second gate drive circuit112B is coupled to a second example gate146of the second transistor128.

In example operation, the current generator110generates and transmits (e.g., continuously transmits) IS114to a second input of the delay logic106and a second input of the gate drive142. For example, the current generator110can facilitate continuous delay control by the delay logic106by generating (e.g., continuously generating) IS114. In example operation, the controller108generates and transmits the control signal118to a third input of the delay logic106. In example operation, the trim circuit140can adjust the delay based on a code, a setting, etc., stored in memory of the trim circuit140. In example operation, the trim circuit140can invoke one or more switches included in the delay logic106to change states (e.g., from closed to open, from open to closed, etc.) to adjust a discharge current associated with a capacitor of the delay logic106.

In example operation, the delay logic106can increase or decrease a delay of the control signal118by coupling one or more corresponding transistors to a discharge current path associated with the capacitor of the delay logic106. In example operation, the delay logic106can increase or decrease a delay of the control signal118by de-coupling one or more corresponding transistors from the discharge current path associated with the capacitor. Advantageously, the delay logic106can adaptively adjust the delay of the control signal118based on a code, a configuration, etc., stored in trim memory, the current IS114set by the current generator110, etc., and/or a combination thereof.

FIG. 2is a schematic illustration of an example delay circuit200including an example current mirror circuit202. The delay circuit200ofFIG. 2is an example implementation of the delay logic106ofFIG. 1. The current mirror circuit202includes a first example transistor (MN1)204having a gate (e.g., a gate terminal)204G, a drain (e.g., a current terminal, a drain terminal, etc.)204D, and a source (e.g., a current terminal, a source terminal, etc.)204S. The current mirror circuit202includes a third example transistor (MN3)206having a gate206G, a drain206D, and a source206S. InFIG. 2, the delay circuit200includes a second example transistor (MN2)208having a gate208G, a drain208D, and a source2085. InFIG. 2, the first, second, and third transistors204,206,208are N-channel FETs (e.g., N-channel MOSFETs). Alternatively, one or more of the transistors204,206,208may be a different type of FET, a BJT, etc.

In the illustrated example ofFIG. 2, MN1204, MN2208and MN3206are coupled in a current mirror arrangement. InFIG. 2, the gate204G of MN1204is coupled to the gate206G of MN3206. InFIG. 2, the source204S of MN1204is coupled to the source206S of MN3206. InFIG. 2, the delay circuit200includes an example switch210having a first example switch terminal210A, a second example switch terminal210B, a third example switch terminal210C, and a fourth example switch terminal (e.g., a control terminal, a switch control terminal, etc.)210D. InFIG. 2, the drain206D of MN3206is coupled to the first switch terminal210A, the drain208D of MN2208is coupled to the second switch terminal210B, and the drain204D of MN1204is coupled to the third switch terminal210C.

In the illustrated example ofFIG. 2, the delay circuit200includes the switch208to adjust a coupling of the drain206D of MN3206to generate different current ratios. For example, the trim circuit140ofFIG. 1can transmit a first control signal to the fourth switch terminal210D to invoke and/or otherwise cause the switch210to couple the first switch terminal210A to the second switch terminal210B. In such examples, an example capacitor212included in the delay circuit200can discharge at a first discharge rate. For example, the switch210can couple the drain206D of MN3206to the drain208D of MN2208to prevent discharge of the capacitor212through MN3206.

In some examples, the trim circuit140can transmit a second control signal to the fourth switch terminal210D to invoke and/or otherwise cause the switch210to couple the first switch terminal210A to the third switch terminal210C. In such examples, the capacitor212can discharge at a second discharge rate that is greater than the first discharge rate. For example, the switch210can couple the drain206D of MN3206to the drain204D of MN1204to adjust a discharge path of the capacitor212to flow through MN1204and MN3206. Advantageously, by adjusting the coupling of the transistors206,208in the current mirror circuit202, the current mirror circuit202can cause exponentially scaled discharge current to flow from the capacitor212to an example reference rail214via MN3206and/or any additional transistors coupled to the capacitor212.

FIGS. 3-4depict an example delay circuit (e.g., a pulse train conditioning circuit)300to delay an example signal (e.g., a pulse signal, a pulse train, a pulse train signal, etc.)302generated by an example signal source304. In some examples, the signal302corresponds to the control signal118ofFIG. 1. In some examples, the signal source304corresponds to the controller108ofFIG. 1. InFIG. 3, the delay circuit300is another example implementation of the delay logic106ofFIG. 1. For example, the delay circuit300can correspond to the current mirror circuit200ofFIG. 2. InFIG. 3, the delay circuit300can selectively control an exponential delay of the signal302. In some examples, the exponential delay can span multiple magnitudes from a first end of the selective control to a second end of the selective control, where the first end is opposite the second end. For example, the delay circuit300ofFIG. 3can generate a 10-bit range of delay (e.g., a range of 1024 units of delay) based on 5-bit range of control (e.g., a range of 32 units of control). In such examples, each setting of the 5-bit control can generate more than one unit of delay. Advantageously, the delay circuit300can generate exponential delay based on linear control.

In the illustrated example ofFIG. 3, the delay circuit300includes an example discharge current control circuit306and a first example delay unit308. InFIG. 3, the delay circuit300includes the discharge current control circuit306to control a discharge rate of an example capacitor (C0)310included in the delay circuit300. InFIG. 3, the delay circuit300includes the first delay unit308to delay transmission of the signal302to a different delay unit, a different circuit, etc., based on the discharge rate of the capacitor310.

In the illustrated example ofFIG. 3, the discharge current control circuit306includes an example drive current (IDRV)314, a first example transistor (MN0)316, second example transistors (MNX1-MNX31)318, and example switches (SW1-SW31)320. For example, IDRV314can correspond to and/or otherwise be set by M*IS ofFIG. 1. In other examples, IDRV314can correspond to IDRV ofFIG. 2. InFIG. 3, the second transistors318can be discharge current transistors. For example, one(s) of the second transistors318can cause a change in a discharge rate of the capacitor310in response to a change in state(s) of the one(s) of the second transistors318, where the change in state can be a change from open to closed (e.g., the transistor changes from not conducting current to conducting current), closed to open (e.g., the transistor changes from conducting current to not conducting current), etc. InFIG. 3, MN0316and/or any of one or more of MNX1-MNX31318that are coupled to a drain316D of MN0316can correspond to a transistor array. InFIG. 3, the switches320correspond to a switch array. InFIG. 3, the discharge current control circuit306can implement continuous control of the delay of the signal302by changing and/or otherwise adjusting IDRV314.

In the illustrated example ofFIG. 3, the discharge current control circuit306includes 31 of the second transistors318, however, only two are depicted for clarity. Alternatively, the discharge current control circuit306may include fewer or more than 31 of the second transistors318. InFIG. 3, the first transistor316and the second transistors318are N-channel FETs (e.g., N-channel MOSFETs). InFIG. 3, MN0316, the second transistors318, and a third example transistor (MN3)322have substantially the same size and/or substantially the same electrical, physical, etc., characteristics. In some examples, MN3322can be included in and/or otherwise correspond to the discharge current control circuit306. In some examples, MN3322can be included in and/or otherwise correspond to the delay unit308.

In the illustrated example ofFIG. 3, the discharge current control circuit306includes 31 of the switches320, however, only two are depicted for clarity. Alternatively, the discharge current control circuit306may include fewer or more than 31 of the switches320. InFIG. 3, the switches320are transistors (e.g., FETs). Alternatively, one or more of the switches320may be implemented with different hardware.

In the illustrated example ofFIG. 3, a first example gate316G of the first transistor316is coupled to a first example drain316D of the first transistor, and second example gates318G of the second transistors318. For example, the gate318G of MNX1318is coupled to the gate318G of MNX2318, the gate318G of MNX31, etc. InFIG. 3, a first example source316S is coupled to second example sources318S and a second end of the capacitor310. For example, the source318S of MNX1318is coupled to the source318S of MNX2318, the source318S of MNX31, etc.

In the illustrated example ofFIG. 3, the switches320have example terminals (e.g., switch terminals, switch contacts, etc.)320A,320B,320C including a first example terminal320A, a second example terminal320B, and a third example terminal320C. InFIG. 3, second example drains318D of the second transistors318are coupled to respective first terminals320A of the switches320. For example, the drain318D of MNX1318is coupled to the first terminal320A of SW1320, the drain318D of MNX2318is coupled to the first terminal320A of SW2320, the drain318D of MNX31318is coupled to the first terminal320A of SW31320, etc.

In the illustrated example ofFIG. 3, a trim circuit, such as the trim circuit140ofFIG. 1, controls the switches320. For example, the trim circuit140ofFIG. 1can control one or more of the switches320to switch from a first switch position, a first switch contact (e.g., the second terminal320B), a first state (e.g., a first switch state), etc., to a second switch position, a second switch contact (e.g., the third terminal320C), a second state (e.g., a second switch state), etc. InFIG. 3, the second terminals320B of the switches320are coupled to the first drain316D, the first gate316G, the second gates318G, and a third example gate322G of MN3322. InFIG. 3, the third terminals320C of the switches320are coupled to a third example drain322D of MN3322.

In the illustrated example ofFIG. 3, a first switch position can correspond to one of the drains318D of the second transistors318coupled to the drain316D of MN0316. For example, a first switch position of SW1320can correspond to the drain318D of MNX1318coupled to the drain316D of MN0316when the first terminal320A of SW1320is coupled to the second terminal320B of SW1320. InFIG. 3, a second switch position can correspond to the one of the drains318D of the second transistors318coupled to the third drain322D of MN3322. For example, a second switch position of SW1320can correspond to the drain318D of MNX1318coupled to the third drain322D when the first terminal320A of SW1320is coupled to the third terminal320C of SW1320.

In the illustrated example ofFIG. 3, the MN3322is a N-channel FET. For example, a second switch position of SW1320can correspond to the drain318D of MNX1318coupled to the third drain322D of MN3322. InFIG. 3, the discharge current control circuit306includes MN0316to generate a bias voltage, a gate voltage, etc., associated with MN3322. For example, MN0316can have a gate voltage at the first gate316G that causes the same gate voltage to be generated at the third gate322G of MN3322.

In the illustrated example ofFIG. 3, the first delay unit308includes the capacitor310, the third transistor322, a fourth example transistor MN4324, and a sixth example transistor MP0326. InFIG. 3, MN4is a N-channel FET. InFIG. 3, MP0is a P-channel FET (e.g., a P-channel MOSFET). InFIG. 3, the coupling of MP0326and MN4324form and/or otherwise correspond to an inverter (e.g., an inverter logic circuit). InFIG. 3, a gate326G of MP0326is coupled to a gate324G of MN4324and the first end of the signal source304. InFIG. 3, the signal source304generates an input pulse train (e.g., the signal302, the control signal118ofFIG. 1, etc.). InFIG. 3, a drain326D of MP0326is coupled to a drain324D of MN4324and a first end of the capacitor310. InFIG. 3, a source324S of MN4324is coupled to the drain322D of MN3322and the third terminal320C.

In example operation, the trim circuit140ofFIG. 1can adjust as switch position of one or more of the switches320. For example, the trim circuit140can adjust SW1-SW10to move to the second switch position while SW11-SW31remain in the first switch position. In such examples, a respective drain318D of MNX1-MNX10318can be coupled to the drain316D of MN0316and a respective drain318D of MNX11-MNX31318can be coupled to the drain322D of MN3. In other examples, the trim circuit140can adjust SW11-SW31to move from the second switch position to the first switch position.

In example operation, a discharge current associated with C0310can be determined by the example of Equation (1) below:

In the example of Equation (1) above, IDISCHARGEcorresponds to a discharge current, or a first current flowing from C0310to discharge C0310, IDRVcorresponds to IDRV314, and NUMERATOR corresponds to a first quantity of the second transistors318that are coupled to the third drain322D of MN3322, and DENOMINATOR corresponds to a second quantity of the second transistors318that are coupled to the first drain316D of MN0316. In the example of Equation (1) above, the ratio of NUMERATOR and DENOMINATOR corresponds to a current ratio. For example, the discharge current can have a value based on a multiplication of the drive current and the current ratio.

Advantageously, C0310can be discharged quicker by increasing a ratio of the NUMERATOR and the DENOMINATOR. Further description in connection with the NUMERATOR is described below in connection with the second column704of the table700ofFIG. 7. Further description in connection with the DENOMINATOR is described below in connection with the third column706of the table700ofFIG. 7. Further description in connection with the current ratio is described below in connection with the fourth column708of the table700ofFIG. 7.

In example operation, a logic low signal (e.g., a current, a voltage, etc., corresponding to a digital zero) is present at a first example node (A)328. For example, the logic low signal can correspond to a falling edge of the signal302. Other nodes of interest inFIGS. 3-4include a second example node (Ab)330and a third example node (A1)332. In example operation, the logic low signal (e.g., the falling edge of the signal302) turns on MP0326and turns off MN4324. In example operation, MN3322is always turned on. In example operation, MP0326conducts current and causes the capacitor310to be charged. In example operation, a fifth example transistor MN5334included in the delay circuit300turns on in response to the capacitor310having a voltage that meets and/or otherwise satisfies a turn-on threshold voltage of MN5334. In example operation, an example current IDC336flows through MN5334. IDC336flowing through MN5334results in the first node328being low (e.g., a logic low signal). For this transition from high to low at the first node328, the delay incurred in transmitting a logic low from the signal source304to the third node332is minimal as charge-up current of C0310is not restricted. In the delay circuit300, a first end of an example voltage clamp338is coupled to the source326S of MP0326. In example operation, the voltage clamp338takes IDC336when MN5334is off, which causes a logic high signal at the third node332.

In example operation, the signal source304can generate a square wave signal as the signal302to cause a logic high signal (e.g., a current, a voltage, etc., corresponding to a digital one) to be present at the first node328. For example, the logic high signal can correspond to a rising edge of the signal302. In such examples, the signal302can correspond to the control signal118ofFIG. 1. In example operation, the logic high signal (e.g., the rising edge of the signal302) turns off MP0326and turns on MN4324. In example operation, current from the capacitor310flows through MN4324, MN3322, and MNX1-MNX10318. This discharge current is set by the gate voltage at the gate322G of MN3322, where the gate voltage is developed, generated, etc., by (1) MN0316and (2) MNX11-MNX31, which behave like MN0316when coupled to the drain316D of MN0316. In example operation, MN5334turns off in response to discharging the capacitor310below the turn-on threshold voltage of MN5334. For example, a change in coupling of one(s) of MNX11-MNX31from MN0316to MN3322(or from MN3322to MN0316) can cause a change in the bias voltage, the gate voltage, etc., at the gate terminals of MN0316, MN3322, MNX11-MNX31, etc. In example operation, in response to turning off MN5334, IDC336does not flow through MN5334as described below in connection withFIG. 4and the third node332is pulled high. For this transition from low to high, the delay incurred in transmitting a logic high from the first node328to the third node332is controlled (e.g., not minimal) as the charge-down current of C0310is restricted as determined by IDRV314(e.g., as determined by the example of Equation (1) above).

In the illustrated example ofFIG. 3, the delay circuit300can increase a discharge rate of the capacitor310by switching one or more of SW11-SW31320from the first switch position to the second switch position. In some examples, for each one of SW11-SW31320that are switched by the trim circuit140, a non-linear or non-proportional change in a time delay of propagating the signal302to a different delay unit can be facilitated. Advantageously, the delay circuit300ofFIG. 3can execute selective control by controlling one or more of the switches320to facilitate an exponential-based change in time delay output of the signal302.

Turning to the illustrated example ofFIG. 4, the delay circuit300includes a second example delay unit402. The delay circuit300ofFIGS. 3-4is a two-unit delay chain including the first delay unit308and the second delay unit402. InFIG. 4, the second delay unit402includes example P-channel FETs MP1404and MP2406. InFIG. 4, the second delay unit402includes example N-channel FETs MN6408, MN7410, and MN8412. InFIG. 4, the second delay unit402includes another example capacitor C1414.

In example operation, in response to turning off MN5334, a logic high signal is present at the third node332. In example operation, the logic high signal turns off MP1404and turns on MN6408causing a logic low signal to be present at a fourth example node (Alb)416. The logic low signal at the fourth node416turns on MP2406and turns off MN6410causing a logic high signal to be present at a fifth example node (A2)418and, thus, charge C1414. In example operation, in response to charging C1414to generate a voltage that meets and/or otherwise satisfies a turn-on voltage threshold of MN9420to turn on MN9420and cause a logic low signal to be present at a sixth example node (A2b)422. In response to turning on MN9420, MP3424turns on and MN10426turns off to cause a logic high signal to be present at a seventh example node (A3)428. In some examples, the seventh node428is coupled to the gate drive142ofFIG. 1to turn on the first transistor126of the power converter102ofFIG. 1. For example, the first delay unit308is coupled to the second delay unit402and the second delay unit402is coupled to the power converter102ofFIG. 1. In such examples, the first delay unit308, the second delay unit402, etc., can delay a switching operation associated with the power converter by delaying a propagation of the signal302ofFIG. 3. Advantageously, the delay circuit300ofFIGS. 3-4can execute selective control by controlling one or more of the switches320ofFIG. 3to facilitate an exponential-based change in time delay output of the signal302from the first node328to the seventh node428. In some examples, only one edge of the signal302is delayed. For example, the first delay unit308can directly drive the gate driver104ofFIG. 1that drives the power converter102ofFIG. 1.

FIG. 5depicts a first example timing diagram500corresponding to example operation of the delay circuit300ofFIGS. 3-4and/or, more generally, the delay logic106ofFIG. 1. InFIG. 5, the first timing diagram500depicts example waveforms of signals at the first node328, the second node330, the fifth node418, the sixth node422, and the seventh node428ofFIGS. 3 and/or 4. For example, the waveforms ofFIG. 5can correspond to the signal302being propagated, transmitted, etc., to different nodes of the delay circuit300.

In the illustrated example ofFIG. 5, at a first example time (T1)502, the signal source304generates a logic high signal for the signal302ofFIG. 3. At the first time502, the first node328has a first voltage corresponding to the logic high signal and the second node330has the first voltage corresponding to the voltage of the capacitor310(e.g., the capacitor310is fully or substantially charged). The first voltage turns off MP0326and turns on MN4324. In response to turning on MN4324, the capacitor310discharges current through MN4324, MN3322, and one or more of the second transistors318that are coupled to MN3322.

In the illustrated example ofFIG. 5, at a second example time (T2)504, the voltage of the capacitor310drops below a turn-on threshold voltage of MN5334causing a logic high signal to be present at the third node332. The logic high signal at the third node332turns on MN6408to cause a logic low signal to be present at the fourth node416. At the second time504, the logic low signal at the fourth node416turns on MP2406to cause a logic high signal to be present at the fifth node418as depicted inFIG. 5. At the second time504, the logic high signal at the fifth node418turns off MN9420causing a logic low signal to be present at the sixth node422.

In the illustrated example ofFIG. 5, at a third example time (T3)506, the signal source304generates a logic low signal for the signal302causing the logic low signal to be present at the first node328. At the third time506, the logic low signal at the first node328turns on MP0326and turns off MN4324to cause a logic high signal to appear at the second node330. At the third time506, the logic high signal at the second node330turns on MN5334causing a logic low signal to appear at the third node332. The logic low signal at the third node332turns on MP1404and turns off MN6408causing a logic high signal to be present at the fourth node416. The logic high signal at the fourth node416turns off MP2406and turns on MN8410causing current from C1414to flow through MN8410and MN7408, which causes the voltage at the fifth node418to decrease from the third time506until at least a fourth example time (T4)508. At the fourth time508, MN9420turns off in response to C1414discharging below a turn-on threshold voltage of MN9420. In response to turning off MN9420, a logic high signal is present at the sixth node422causing MP3424to turn off and MN10426to turn on causing a logic low signal at the seventh node428.

In the timing diagram500ofFIG. 5, the delay circuit300ofFIGS. 3-4and/or, more generally, the delay logic106ofFIG. 1can increase a discharge rate of C0310by switching one or more of SW11-SW31320from the first switch position to the second switch position while at the same increase the gate voltage for an increased discharge rate. In the timing diagram500ofFIG. 5, the discharge rate is represented by a first example waveform510corresponding to voltage at the second node330. For example, the delay circuit300can increase the discharge rate and, thus, decrease a time to reduce the voltage at the second node330from the first voltage to a second voltage, where the second voltage is substantially zero.

In the illustrated example ofFIG. 5, the discharge rate of C0310(e.g., the discharge rate represented by the first waveform510) corresponds to a first time duration beginning at the first time502and ending at substantially the second time504. In some examples, for each one of SW1-SW31320ofFIG. 3that are switched by the trim circuit140, a non-linear or non-proportional change in a time delay of propagating the signal302to a different delay unit can be facilitated. For example, the trim circuit140can selectively control one or more of SW1-SW31320to switch from the first switch position to the second switch position to reduce the first time duration to a second time duration, where the second time duration is less than the first time duration. In such examples, the second time duration can correspond to a time duration beginning at the first time502and end before the second time504.

Advantageously, the delay circuit300ofFIGS. 3-4can execute selective control by controlling one or more of the switches320to facilitate an exponential-based change in time delay output of the signal302by increasing the discharge rate of C0310as depicted in the timing diagram500ofFIG. 5. In some examples, by increasing the discharge rate, the delay circuit300can decrease a time delay associated with the propagation of the signal302to the seventh node428and, ultimately, to the power converter102ofFIG. 1. In some examples, the delay circuit300delays only one edge of the signal302and, thus, can decrease a time delay associated with the propagation of the signal302to the third node332, the fifth node418, the sixth node422, the seventh node428, etc. In some examples, by decreasing the discharge rate, the delay circuit300can increase a time delay associated with the propagation of the signal302to the seventh node428and, ultimately, to the power converter102ofFIG. 1.

FIG. 6depicts a second example timing diagram600corresponding to example operation of the delay circuit300ofFIGS. 3-4and/or, more generally, the delay logic106ofFIG. 1. The second timing diagram600depicts example waveforms602,604,606,608,610,612,614. InFIG. 6, the waveforms602,604,606,608,610,612,614include a first example waveform602corresponding to a voltage at the first node328ofFIGS. 3-4. InFIG. 6, the waveforms602,604,606,608,610,612,614include a second example waveform604corresponding to a voltage at the second node330ofFIGS. 3-4based on a first delay generation setting. InFIG. 6, the waveforms602,604,606,608,610,612,614include a third example waveform606corresponding to a voltage at the second node330based on a second delay generation setting. InFIG. 6, the waveforms602,604,606,608,610,612,614include a fourth example waveform608corresponding to a voltage at the second node330based on a third delay generation setting.

In the illustrated example ofFIG. 6, the waveforms602,604,606,608,610,612,614include a fifth example waveform610corresponding to a voltage at the third node332ofFIG. 4based on the first delay generation setting. InFIG. 6, the waveforms602,604,606,608,610,612,614include a sixth example waveform612corresponding to a voltage at the third node332based on the second delay generation setting. InFIG. 6, the waveforms602,604,606,608,610,612,614include a seventh example waveform614corresponding to a voltage at the third node332based on the third delay generation setting.

In the illustrated example ofFIG. 6, the first delay generation setting corresponds to a first quantity of the second transistors318being coupled to the drain322D of MN3322ofFIG. 3and a second quantity of the second transistors318being coupled to the first drain316D of MN0316ofFIG. 3. For example, the first quantity can be 31 and the second quantity can be 0. In such examples, MNX1-MNX30318can be coupled to MN3322and none of318coupled to MN0316.

In the illustrated example ofFIG. 6, the second delay generation setting corresponds to a third quantity of the second transistors318being coupled to the drain322D of MN3322ofFIG. 3and a fourth quantity of the second transistors318being coupled to the first drain316D of MN0316ofFIG. 3. The third quantity is less than the first quantity and the fourth quantity is more than the second quantity. For example, the third quantity can be 12 and the fourth quantity can be 19. In such examples, MNX1-MNX11318can be coupled to MN3322and MNX12-MNX31318can be coupled to MN0316.

In the illustrated example ofFIG. 6, the third delay generation setting corresponds to a fifth quantity of the second transistors318being coupled to the drain322D of MN3322ofFIG. 3and a sixth quantity of the second transistors318being coupled to the first drain316D of MN0316ofFIG. 3. The fifth quantity is less than the third quantity and the sixth quantity is more than the fourth quantity. For example, the fifth quantity can be 7 and the sixth quantity can be 24. In such examples, MNX1-MNX6318can be coupled to MN3322and MNX7-MNX31318can be coupled to MN0316.

In the second timing diagram600ofFIG. 6, the first delay generation setting generates a first current path from C0310. InFIG. 6, the first current path causes the voltage at the second node330to decrease from a first example voltage616to a second example voltage618during a first example time duration620. The first time duration620corresponds to a first example discharge rate622of C0310. InFIG. 6, the first time duration620begins substantially at a first example time (T1)624and ends substantially at a second example time (T2)626. InFIG. 6, the first waveform602is representative of the voltage at the first node328corresponding to a logic high signal at the first time624. InFIG. 6, the fourth waveform610is representative of the voltage at the third node332corresponding to a logic high signal at the second time626.

In the second timing diagram600ofFIG. 6, the second delay generation setting generates a second current path from C0310different from the first current path. InFIG. 6, the second current path causes the voltage at the second node330to decrease from the first voltage616to the second voltage618during a second example time duration628. The second time duration628corresponds to a second example discharge rate630of C0310. InFIG. 6, the second time duration628begins substantially at the first time624and ends substantially at a third example time (T3)632.

In the second timing diagram600ofFIG. 6, the third delay generation setting generates a third current path from C0310different from the first and second current paths. InFIG. 6, the third current path causes the voltage at the second node330to decrease from the first voltage616to the second voltage618during a third example time duration634. The third time duration634corresponds to a third example discharge rate636of C0310. InFIG. 6, the third time duration634begins substantially at the first time624and ends substantially at a fourth example time (T4)635.

Advantageously, the delay circuit300ofFIGS. 3-4can generate exponential-based delay generation in response to linear control. For example, the delay circuit300can individually and/or otherwise independently change switch positions of the switches320ofFIG. 3. By changing delay generation settings, the delay circuit300can adjust one or more of the switches320to switch between switch positions to generate different current paths associated with C0310. As depicted in the second timing diagram600ofFIG. 6, the delay circuit300can cause non-linear and/or otherwise non-proportional changes in the time durations620,628,634based on linear control of the switches320.

As depicted in the second timing diagram600ofFIG. 6, by increasing the quantity of the second transistors318being coupled to the drain322D of MN3322ofFIG. 3, while simultaneously reducing the quantity of the second transistors318being coupled to the drain316D of MN0316, the discharge rates622,630,636can increase (e.g., changing from the second or third delay generation setting to the first delay generation setting). As depicted in the second timing diagram600ofFIG. 6, by decreasing the quantity of the second transistors318being coupled to the drain322D of MN3322ofFIG. 3while simultaneously increasing the quantity of the second transistors318being coupled to the drain316D of MN0316, the discharge rates622,630,636can decrease (e.g., changing from the first delay generation setting to the second or third delay generation setting).

FIG. 7is an example table700corresponding to example data that can be stored in memory of the trim circuit140and/or, more generally, the gate driver104ofFIG. 1. The table700ofFIG. 7includes a first example column702, a second example column704, a third example column706, a fourth example column708, and a fifth example column710.

In the table700ofFIG. 7, the first column702includes example codes (e.g., switch setting codes, data values, etc.) in a range of 0 to 31. Although the codes are depicted inFIG. 7in decimal format, the codes can be stored in any other machine readable format such as in binary (e.g., in a range from binary 00000 to binary 11111), hexadecimal (e.g., in a range from 0x0 to 0x1F), etc. For example, the codes included in the first column702can be stored as 5-bit digital words in trim memory of the trim circuit140ofFIG. 1. The codes depicted in the first column702are representative of 5-bit selective control that can be executed by the trim circuit140ofFIG. 1and/or, more generally, the delay logic106ofFIG. 1.

In the table700ofFIG. 7, the second column704includes numerator values in a range of 1 to 32. The numerator values depicted in the second column704are representative of a quantity of transistors coupled to C0310ofFIGS. 3-4, a quantity of transistors that correspond to and/or otherwise form a current path from C0310, etc. For example, a numerator value of 7 can correspond to (1) the third drain322D of MN3322and (2) the drains318D of MNX1-MNX6coupled to the first end of C0310.

In the table700ofFIG. 7, the third column706includes denominator values in a range of 1 to 32. The denominator values depicted in the third column706are representative of a quantity of transistors coupled to MN0316ofFIGS. 3-4, a quantity of transistors that correspond to and/or otherwise form a current path, etc. For example, a denominator value of 26 can correspond to (1) the first drain316D of MN0316and (2) the drains318D of MNX7-MNX31coupled to the first end of IDRV314ofFIG. 3.

In the table700ofFIG. 7, the fourth column708includes ratio values, such as current ratio values, in a range of 0.03125 to 32. The ratio values depicted in the fourth column708are representative of a ratio of a numerator value and a corresponding denominator value. For example, a ratio of 0.32 can correspond to a ratio of a numerator value of 8 and a denominator value of 25 (e.g., 0.32=8/25). Advantageously, the delay circuit300ofFIGS. 3-4and/or, more generally, the delay logic106can implement a 10-bit delay variation range of 1024 (e.g., 1024=32/0.03125) with a 5-bit control (e.g., codes 0-31, 32 step control, etc.). For example, the current mirror arrangement associated with MN0316, the second transistors318, and MN3322depicted inFIG. 3can be adjusted (e.g., adjusted by the trim circuit140ofFIG. 1), reconfigured, arranged, etc., to move with the ratio values of the fourth column708to implement the range of the sweep of the ratio values.

In the table700ofFIG. 7, the ratios included in the fourth column708are representative of the delay circuit300configuring at least one of MN0316, one or more of the second transistors318, or MN3322in an arrangement that generates a non-linear, approximately exponential based change in the current ratio of the fourth column708by implementing an example mathematical approximation of

1+x1-x≈e2⁢x,
which results from me mathematical expression illustrated in the example of Equation (2) below:

loge⁡(1+x1-x)=2⁡[x+x33+x55+…+x2⁢n-12⁢n-1+…],⁢-1<x<1Equation⁢⁢(2)
As illustrated in the example of Equation (2) above, the delay circuit300and/or, more generally, the delay logic106ofFIG. 1can execute selective, linear control by controlling a switch position of one or more of the second transistors318to generate a non-linear, approximately exponential change in ratio. For example, a first change in codes from 29 to 30 causes a first change in current ratio of 10 to 15.5 while a second change (e.g., a subsequent change from the first change to the second change) in codes from 30 to 31 causes a second change in current ratio of 15.5 to 32. In such examples, a linear change in codes causes a non-linear, exponential-based change in current ratio.

In the table700ofFIG. 7, the fifth column710includes multiplier (MULT) values in a range of 1.13 to 2.06. The multiplier values correspond to ratios of the ratios of the fourth column708. For example, a multiplier value of 2.06 corresponds to a ratio of 0.03125 and 0.064516 (e.g., 2.06=0.064516/0.03125).

FIG. 8depicts another example delay circuit800. The delay circuit800ofFIG. 8is another example implementation of the delay logic106ofFIG. 1. The delay circuit800ofFIG. 8is an RC delay circuit including an example resistor802and an example capacitor804. The delay circuit800ofFIG. 8can delay signal (DLY_IN)806by a fixed time proportional to a product (e.g., a multiplication) of the resistance of the resistor802and the capacitance of the capacitor804. The resistor802ofFIG. 8changes electrical characteristics based on temperature variations. Advantageously, the delay circuit300ofFIGS. 3-4is an improvement over the delay circuit800ofFIG. 8as the delay circuit300can generate different delay outputs independent or controlled dependence on of temperature through choice of IDRV.

In some examples, a gate driver (e.g., the gate driver104ofFIG. 1) includes 1024 instances of the delay circuit800ofFIG. 8to implement a 10-bit delay range. Advantageously, a gate driver can include the delay circuit300ofFIGS. 3-4to implement the same 10-bit delay range of 1024 instances of the delay circuit800ofFIG. 8. Advantageously, the delay circuit300ofFIGS. 3-4is substantially smaller in size compared to 1024 instances the delay circuit800ofFIG. 8as the have a greater size compared to that ofFIG. 3to execute changes in delay output.

FIG. 9depicts yet another example delay circuit900. InFIG. 9, the delay circuit900is another example implementation of the delay logic106ofFIG. 1. The delay circuit900ofFIG. 9is a digital-to-analog converter (DAC) based delay circuit. The delay circuit900ofFIG. 9can execute selectable control by controlling switches902and correspondingly coupled transistors904. InFIG. 9, the switches902are controlled by signals (M1<7:1>)906and an inverse of the signals (M1B<7:1>)908. For example, changing a setting of the switches902can control a change in the delay generated by the delay circuit900.

In some examples, a gate driver (e.g., the gate driver104ofFIG. 1) includes 1024 instances of the array including the switches902and the transistors904to implement a 10-bit delay range. Advantageously, a gate driver can include the delay circuit300ofFIGS. 3-4to implement the same 10-bit delay range as 1024 DAC elements (e.g., transistors and switches). Advantageously, the delay circuit300ofFIGS. 3-4is substantially smaller in size compared to the delay circuit900ofFIG. 9as only 32 elements (e.g., transistors and switches) ofFIGS. 3-4are needed compared to the delay circuit900ofFIG. 9to execute changes in delay output.

A flowchart representative of example hardware logic, machine readable instructions, hardware implemented state machines, and/or any combination thereof for implementing the computing system141ofFIG. 1and/or the gate driver104ofFIG. 1is shown inFIG. 10. The machine readable instructions may be one or more executable programs or portion(s) of an executable program for execution by one or more computer processors, one or more microcontrollers, etc., associated with and/or otherwise included in the computing system141ofFIG. 1. For example, the machine readable instructions may be executed by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. For example, the one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers may be semiconductor based (e.g., silicon based) device(s). The program may be embodied in software stored on a non-transitory computer readable storage medium such as non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), etc., and/or any other type of random access memory (RAM) device), etc., associated with the one or more computer processors, the one or more microcontrollers, etc., but the entire program and/or parts thereof could alternatively be executed by a device other than the one or more computer processors, the one or more microcontrollers, etc., and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowchart illustrated inFIG. 10, many other methods of implementing the computing system141and/or the gate driver104may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware.

The machine readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: assembly or assembler language, C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

FIG. 10is a flowchart representative of example machine readable instructions1000that may be executed to implement the computing system141and/or the gate driver104ofFIG. 1. The machine readable instructions1000begin at block at1002, at which a determination of whether to adjust a delay of a signal is made. For example, the computing system141can generate and transmit a command to the gate driver104to increase delay of the signal302ofFIG. 3, decrease delay of the signal302, etc.

If, at block1002, the determination is made to not adjust the delay of the signal control waits at block1002. If, at block1002, the determination is made to adjust the delay of the signal control by increasing the delay, control proceeds to block1004.

At block1004, the gate driver104identifies switch(es) to control based on a code. For example, the trim circuit140of the first gate drive circuit112A can extract a code (e.g., one of the codes included in the first column702of the table700ofFIG. 7) of 7 from a command obtained from the computing system141. In such examples, the trim circuit140can map the code of 7 to a corresponding numerator value of 8, a denominator value of 25, etc., in the table700. In some examples, the trim circuit140can identify SW1-SW7320to switch to the first switch position based on the numerator value of 8. In some examples, the trim circuit140can identify SW8-SW31320to switch to the second switch position based on the denominator value of 25.

At block1006, the gate driver104controls the identified switch(es) to change switch position(s). For example, based on the numerator value of 8, the denominator value of 25, etc., the trim circuit140can adjust a switch position of SW1-SW7320ofFIG. 3to couple the drain318D of MNX1-MNX7318to the third drain322D of MN3322. In such examples, based on the numerator value of 8, the denominator value of 25, etc., the trim circuit140can adjust a switch position of SW8-SW31320ofFIG. 3to couple the drain318D of MNX8-MNX31318to the first drain316D of MN0316.

At block1008, the gate driver104increases a discharge time of a capacitor based on the changed switch position(s). For example, the trim circuit140can invoke the delay circuit300and/or, more generally, the delay logic106ofFIG. 1to increase a discharge time of C0310based on the changed switch positions of SW1-SW7320(e.g., reducing a quantity of the second transistors318coupled to the third drain322D to discharge C0310).

At block1010, the gate driver104increases a delay of the signal based on the increased discharge time. For example, the delay circuit300and/or, more generally, the delay logic106can increase a time duration during which the signal302is propagated from the first node328ofFIGS. 3-4to the seventh node428ofFIG. 4based on the increased discharge time associated with C0310. In response to increasing the delay of the signal based on the increased discharge time at block1010, control returns to block1002to determine whether to adjust the delay of the signal.

If, at block1002, the determination is made to adjust the delay of the signal control by decreasing the delay, control proceeds to block1012.

At block1012, the gate driver104identifies switch(es) to control based on a code. For example, the trim circuit140of the first gate drive circuit112A can extract a code (e.g., one of the codes included in the first column702of the table700of FIG.7) of 25 from a command obtained from the computing system141. In such examples, the trim circuit140can map the code of 25 to a corresponding numerator value of 26, a denominator value of 7, etc., in the table700. In some examples, the trim circuit140can identify SW1-SW25320to switch to the first switch position based on the numerator value of 26. In some examples, the trim circuit140can identify SW26-SW31320to switch to the second switch position based on the denominator value of 7.

At block1014, the gate driver104controls the identified switch(es) to change switch position(s). For example, based on the numerator value of 26, the denominator value of 7, etc., the trim circuit140can adjust a switch position of SW1-SW25320ofFIG. 3to couple the drain318D of MNX1-MNX25318to the third drain322D of MN3322. In such examples, based on the numerator value of 26, the denominator value of 7, etc., the trim circuit140can adjust a switch position of SW26-SW31320ofFIG. 3to couple the drain318D of MNX26-MNX31318to the first drain316D of MN0316.

At block1016, the gate driver104decreases a discharge time of a capacitor based on the changed switch position(s). For example, the trim circuit140can invoke the delay circuit300and/or, more generally, the delay logic106ofFIG. 1to decrease a discharge time of C0310based on the changed switch positions of SW1-SW25320(e.g., increasing a quantity of the second transistors318coupled to the third drain322D to discharge C0310).

At block1018, the gate driver104decreases a delay of the signal based on the decreased discharge time. For example, the delay circuit300and/or, more generally, the delay logic106can decrease a time duration during which the signal302is propagated from the first node328ofFIGS. 3-4to the seventh node428ofFIG. 4based on the decreased discharge time associated with C0310. In response to decreasing the delay of the signal based on the decreased discharge time at block1018, control returns to block1002to determine whether to adjust the delay of the signal.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed for implementing pulse train conditioning circuits. The disclosed systems, methods, apparatus, and articles of manufacture use and/or otherwise approximate an exponential function to generate a range of multiple orders of magnitude delay. The disclosed systems, methods, apparatus, and articles of manufacture can provide non-linear changes in delay output in response to selectable, defined input changes. The disclosed systems, methods, apparatus, and articles of manufacture use exponentially spaced delay points, control steps, etc., to facilitate a delay variation range implemented by different implementations of delay circuits but with substantially less number of elements, instances of delay circuits, and/or area on chip or on a semiconductor substrate.

Example methods, apparatus, systems, and articles of manufacture for pulse train conditioning circuits and related methods are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes a delay circuit comprising a first transistor having a first current terminal and a first gate terminal, a second transistor having a second current terminal and a second gate terminal, a third transistor having a third current terminal and a third gate terminal, a fourth transistor having a fourth current terminal and a fourth gate terminal, the fourth gate terminal coupled to the first gate terminal, the second gate terminal, and the third gate terminal, a first switch having a first terminal, a second terminal, and a third terminal, the first terminal coupled to the first current terminal, the second terminal coupled to the third current terminal, and the third terminal coupled to the fourth current terminal, and a second switch having a fourth terminal, a fifth terminal, and a sixth terminal, the fourth terminal coupled to the second current terminal, the fifth terminal coupled to the third current terminal, and the sixth terminal coupled to the fourth current terminal.

Example 2 includes the delay circuit of example 1, wherein the first switch and the second switch are in a first switch state, the first switch in the first switch state by coupling the first terminal to the second terminal, the first current terminal to be coupled to the third current terminal when the first switch is in the first switch state, the second switch in the first switch state by coupling the fourth terminal to the fifth terminal, the second current terminal to be coupled to the third current terminal when the second switch is in the first switch state.

Example 3 includes the delay circuit of example 1, wherein the first switch is in a first switch state and the second switch is in a second switch state different from the first switch state, the first switch in the first switch state by coupling the first terminal to the second terminal, the first current terminal to be coupled to the third current terminal when the first switch is in the first switch state, the second switch in the second switch state by coupling the fourth terminal to the sixth terminal, the second current terminal to be coupled to the fourth current terminal when the second switch is in the second switch state.

Example 4 includes the delay circuit of example 1, wherein the first switch and the second switch are in a first switch state, the first switch in the first switch state by coupling the first terminal to the third terminal, the first current terminal to be coupled to the fourth current terminal when the first switch is in the first switch state, the second switch in the first switch state by coupling the fourth terminal to the sixth terminal, the second current terminal to be coupled to the fourth current terminal when the second switch is in the first switch state.

Example 5 includes the delay circuit of example 1, wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor are field-effect transistors or bipolar junction transistors.

Example 6 includes the delay circuit of example 1, further including a fifth transistor having a fifth gate terminal, a fifth current terminal, and a sixth current terminal, the sixth current terminal coupled to the fourth current terminal, a sixth transistor having a sixth gate terminal and a seventh current terminal, the seventh current terminal coupled to the fifth current terminal, the fifth gate terminal coupled to the sixth gate terminal, a capacitor coupled to the fifth current terminal and the seventh current terminal, and a signal source coupled to the fifth gate terminal and the sixth gate terminal.

Example 7 includes the delay circuit of example 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), and the sixth transistor is a P-channel MOSFET.

Example 8 includes an apparatus comprising a first transistor having a first current terminal and a first gate terminal, a second transistor having a second current terminal and a second gate terminal, the second gate terminal coupled to the first gate terminal, a third transistor having a third current terminal and a third gate terminal, the third gate terminal coupled to the first gate terminal and the second gate terminal, and a first switch coupled to the first current terminal, the second current terminal, and the third current terminal, the first switch configured to couple the third current terminal to the first current terminal or the second current terminal based on a code to adjust a ratio of a first quantity of one or more transistors over a second quantity of one or more transistors, the first quantity including at least the first transistor, the second quantity including at least the second transistor.

Example 9 includes the apparatus of example 8, further including fourth transistors having respective fourth gate terminals, the fourth gate terminals coupled to the first gate terminal, the second gate terminal, and the third gate terminal, the fourth transistors including the third transistor, and wherein each subsequent change in coupling of one of the fourth transistors from the first current terminal to the second current terminal causes an exponential change in current flowing through the second transistor based on a change in the ratio.

Example 10 includes the apparatus of example 8, further including a fourth transistor and a capacitor, the fourth transistor coupled to the capacitor and the second transistor, and when the third current terminal is coupled to the second current terminal, the fourth transistor to facilitate a current to flow from the capacitor through the second transistor, the third transistor, and the fourth transistor.

Example 11 includes the apparatus of example 8, wherein when the third current terminal is coupled to the first current terminal, a current is to flow through the first transistor and the third transistor.

Example 12 includes the apparatus of example 8, further including a fourth transistor and a capacitor, the fourth transistor coupled to the capacitor and the second transistor, and wherein the third transistor to reduce a discharge rate of the capacitor when the third current terminal is coupled to the first current terminal, and the third transistor to increase the discharge rate of the capacitor when the third current terminal is coupled to the second current terminal.

Example 13 includes the apparatus of example 8, wherein the ratio is a first ratio, and the adjustment of the first ratio adjusts a second ratio of a first current flowing through the first transistor over a second current flowing through the second transistor.

Example 14 includes the apparatus of example 8, further including a fourth transistor and a capacitor, the fourth transistor coupled to the capacitor and the second transistor, and wherein the capacitor is to discharge at a first rate in response to the first quantity being greater than the second quantity, and the capacitor is to discharge at a second rate in response to the first quantity being less than the second quantity, the first rate less than the second rate.

Example 15 includes the apparatus of example 8, further including a capacitor, a fourth transistor having a fourth gate terminal, the fourth transistor coupled to the capacitor and the second transistor, and a controller coupled to the fourth gate terminal, the controller to generate a pulse signal to control the fourth transistor to adjust a voltage associated with the capacitor.

Example 16 includes a system comprising a power converter, a gate driver coupled to the power converter, the gate driver including a trim circuit, and delay logic coupled to the trim circuit, the delay logic including first transistors, a second transistor coupled to the first transistors, a third transistor coupled to the second transistor, switches, each of the switches coupled to a respective one of the first transistors, the switches to couple a set of the first transistors to a current terminal of the third transistor, a capacitor, and a fourth transistor coupled to the capacitor and the third transistor, the fourth transistor to discharge the capacitor by facilitating a current to flow from the capacitor through the set of the first transistors, the third transistor, and the fourth transistor.

Example 17 includes the system of example 16, wherein the power converter includes a first Gallium Nitride (GaN) transistor and a second GaN transistor, the first GaN and the second GaN coupled to the gate driver, and further including a load coupled to the power converter.

Example 18 includes the system of example 16, wherein the current is a first current flowing through the third transistor, the switches coupling the set of the first transistors to the current terminal of the third transistor adjusts a ratio of the first current and a second current flowing through the second transistor, and each subsequent change in coupling of one of the first transistors from the second transistor to the current terminal of the third transistor causes an exponential change in the ratio.

Example 19 includes the system of example 16, wherein the set of the first transistors is a first set, the current is based on a current ratio, and the current ratio is determined by dividing a first quantity of transistors by a second quantity of transistors, the first quantity of transistors corresponding to a first sum of the third transistor and the first set of the first transistors, the second quantity of transistors corresponding to a second sum of the second transistor and a second set of the first transistors.

Example 20 includes the system of example 19, wherein the capacitor is to discharge at a first rate in response to the first quantity of transistors being greater than the second quantity of transistors, and the capacitor is to discharge at a second rate in response to the first quantity of transistors being less than the second quantity of transistors, the first rate greater than the second rate.