Semiconductor device

A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling the substrate bias voltage of the transistor, high-speed equalization is performed, and an increase in leak current at times of standby and activation is prevented.

The present invention relates to a semiconductor device. More specifically, the invention relates to a semiconductor device including a bit line equalize transistor.

BACKGROUND

An equalize circuit is used for bit lines of a semiconductor memory device. Especially when the potential of a bit line targeted for data reading and the potential of a bit line that serves as a comparison reference for the bit line targeted for data reading are amplified by a differential-type sense amplifier and read or refreshed in a DRAM (dynamic random access memory) or the like, it is necessary to equalize the bit lines so that a potential difference between the bit lines is eliminated before data is read onto the bit line from a memory cell.

FIG. 1 of Patent Document 1 and description of FIG. 1 describe high-speed equalization using a signal φEQL as a gate control signal for an equalize transistor13. The signal φEQL has been level converted to a voltage higher than an externally applied supply voltage by a level conversion circuit16.

Patent Document 2 describes that power consumption in a standby state can be reduced, and an operation speed in an active state can be improved by switching a substrate bias of an NMOS transistor between the active state and the standby state and varying the threshold value of the NMOS transistor in a semiconductor device such as a DRAM or an SRAM, including NMOS transistors.[Patent Documents 1] JP Patent Kokai Publication No. JP-A-7-130175, which corresponds to U.S. Pat. No. 5,689,461.[Patent Documents 2] JP Patent Kokai Publication No. JP-A-6-89574, which corresponds to U.S. Pat. No. 5,557,231.

SUMMARY

The above Patent Documents are incorporated herein by reference thereto.

The following analyses are given by the present invention. When a chip size is to be reduced by reducing the number of sense amplifier columns in a semiconductor memory device, the number of memory cells connected to a bit line increases. As a result, a time constant of the bit line increases, and a precharging time therefore increases.

When the signal of which a voltage level has been converted to the voltage level (boosted voltage level) higher than the externally applied supply voltage is employed as the control signal for the equalize circuit as described in the above-mentioned Patent Document 1, driving capability of the equalize transistor can be increased, and a precharging time can be reduced. In that case, however, a high voltage is applied to a gate voltage of the equalize transistor. Thus, a film thickness of the gate insulating film of the equalize transistor must be increased, and a gate withstand voltage must be thereby increased. Further, a high-voltage signal is used as the control signal for the equalize circuit. Thus, there is also a problem that power consumption of the equalize circuit increases.

Patent Document 2 describes control of the substrate bias of the NMOS transistor according to whether the semiconductor device is in the active state or the standby state. Patent Document 2, however, does not cover an equalize transistor.

A semiconductor device according to one aspect of the present invention comprises:

first and second bit lines;

a transistor coupled between the first and second bit lines; and

a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor as a substrate bias voltage.

A semiconductor device according to another aspect of the present invention comprises:

a sense amplifier that amplifies a potential difference between a first sense line and a second sense line;

an equalize transistor with one of first and second electrodes thereof connected to the first sense line and the other of the first and second electrodes thereof connected to the second sense line, an equalize signal that controls an equalization operation of the first and second sense lines being supplied to a control terminal the equalize transistor; and

a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the equalize transistor as a substrate bias voltage;

the substrate bias control circuit supplying the second substrate bias voltage to the equalize transistor before activation of the equalize signal and supplying the first substrate bias voltage to the equalize transistor after potentials of the first and second sense lines have become generally equal.

According to the semiconductor device of the present invention, a first substrate bias potential or a second substrate bias potential is supplied to the transistor that connects the bit lines. Thus, even if a high withstand voltage transistor is not used for the transistor, high-speed equalization of the bit lines can be performed, and leak current between the bit lines can be prevented. Operation after the equalization is not thereby adversely affected.

According to the semiconductor device of the present invention, even if the high withstand voltage transistor is not used, high-speed equalization of sense lines can be performed, and leak current between the sense lines after the equalization is prevented. Amplification operation after the equalization is not thereby adversely affected.

PREFERRED MODES

An overview of the present invention will be described with reference to drawings, as necessary. The drawings and reference characters of the drawings cited in the description of the overview are shown as an example of an exemplary embodiment, and do not thereby limit a variation of the exemplary embodiment of the present invention.

According to the exemplary embodiment of the present invention, a shallow second substrate bias voltage VB2can be supplied to a transistor21provided between bit lines to reduce the absolute value of the threshold value of the transistor21. Thus, high-speed equalization can be performed. After the equalization has been completed, a deeper first substrate bias voltage VB1can be supplied to the transistor21to increase the absolute value of the threshold value. Thus, leak current between the bit lines is prevented, and operation after the equalization is not thereby adversely affected. Further, by dynamically performing threshold value control by the substrate bias voltage, an on-resistance of the transistor21can be reduced even if a high voltage is not applied to the gate of the transistor21. Thus, it is not necessary to use a high withstand voltage transistor for the transistor21. With this configuration, a precharging time can be reduced without using a signal of a boosted voltage level as a control signal for the equalize circuit. An increase in the leak current at times of standby and activation can also be suppressed.

In addition to a semiconductor memory device, the present invention can also be applied to a semiconductor device that uses a sense amplifier that amplifies a potential difference between first and second sense lines. An equalize transistor is used between the sense lines in the sense amplifier. High-speed equalization can be performed without using a high withstand voltage transistor as the equalize transistor and leak current between the sense lines after the equalization can be prevented. A detailed description will be given about examples, with reference to drawings.

First Example

FIG. 1is a block diagram of a semiconductor memory device1in a first example. The semiconductor memory device1in the first example includes a command decode circuit17that decodes a command supplied from a command signal input terminal CMD in synchronization with a clock signal supplied from a clock signal input terminal CLK, thereby controlling overall operation of the semiconductor memory device1, a bank region10including a memory cell array11and a peripheral circuit of the memory cell array11, and a substrate bias control circuit16that controls a substrate bias which is supplied to a transistor provided for bit line equalization. In addition to the memory cell array11, the bank region10includes row decoders12each of which specifies a row address of the memory cell array11, sense amplifier columns14in which a plurality of sense amplifiers SA are disposed, and an equalize control circuit13that controls equalization between bit lines.

The command decode circuit17receives the command supplied from the command signal input terminal in synchronization with the clock signal supplied from the clock signal input terminal CLK, and generates an internal command signal corresponding to the input command.

The memory cell array11includes a plurality of word lines (WL) and a plurality of bit lines (BLT, BLB, and the like) and includes memory cells15provided corresponding to intersections between the respective bit lines and the respective word lines. The sense amplifiers SA and the like each connected between a pair of the bit lines are disposed between the memory cell arrays11, as the sense amplifier columns14.

An equalizing precharge signal PRE-EQ is connected to the substrate bias control circuit16from the command decode circuit17. A precharge signal PRET from the command decode circuit17is connected to the row decoder12and the equalize control circuit13through a delay circuit Delay.

The command decode circuit17supplies an act signal ACT corresponding to an active command (ACT command) and a precharge command (PRE command) supplied from an outside to the row decoder12. The command decode circuit17supplies the precharge signal PRET corresponding to the active command and the precharge command supplied from the outside to the row decoder12and the equalize control circuit13through the delay circuit Delay. Further, the command decode circuit17supplies the equalizing precharge signal PRE-EQ corresponding to the active and precharge commands supplied from the outside to the substrate bias control circuit16.

The substrate bias control circuit16is a circuit that controls a substrate bias voltage Vbbc that is supplied to the transistor provided for bit line equalization, and supplies the substrate bias voltage Vbbc to the transistor for bit line equalization, in response to the equalizing precharge signal PRE-EQ supplied from the command decode circuit17.

FIG. 2is a more detailed block diagram of the bank region10in the vicinity of the sense amplifier SA. A bit line equalize transistor21and a bit line precharge circuit22are disposed in the vicinity of the sense amplifier SA. Two bit lines BLT and BLB, which forms a pair, are connected to the sense amplifier SA. The bit lines BLT and BLB, which forms the pair, are respectively connected to a plurality of the memory cells15.

The bit line equalize transistor21is an N-type MOS transistor (NMOS transistor), and is connected between the bit lines BLT and BLB, which forms the pair. One of a source and a drain of the bit line equalize transistor21is connected to the bit line BLT, while the other of the source and the drain of the bit line equalize transistor21is connected to the bit line BLB. The precharge signal PRET is supplied to a gate (control terminal) of the transistor21from the equalize control circuit13, as an equalize signal. Further, the substrate bias voltage Vbbc output from the substrate bias control circuit16is supplied to a back gate of the equalize transistor21. This bit line equalize transistor21turns on when the precharge signal PRET assumes a high level that indicates an active state, and equalizes potentials of the pair of the bit lines (BLT, BLB). The precharge circuit22is a circuit that supplies a predetermined precharge potential to each of the pair of the bit lines (BLT, BLB). An inverted precharge signal PREB is supplied to the precharge circuit22from the equalize control circuit13. The equalize control circuit13generates the inverted precharge signal PREB from the precharge signal PRET. The sense amplifier SA is a circuit that amplifies a potential difference between the pair of the bit lines (BLT, BLB).

FIG. 3is a more detailed circuit diagram of a portion in the vicinity of the sense amplifier SA showing even configurations of internal circuits of the sense amplifier SA and the precharge circuit22. The sense amplifier SA, bit line equalize transistor21, and precharge circuit22shown inFIG. 3may be disposed in the sense amplifier column14inFIG. 1. The sense amplifier SA includes two CMOS inverters that are cross connected between a high-potential power supply SAP and a low-potential power supply SAN given at a time of a sense amplifier operation. An input terminal of a first CMOS inverter including a PMOS transistor31and an NMOS transistor33is connected to the bit line BLT, and an output terminal of the first CMOS inverter is connected to the bit line BLB. An input terminal of a second CMOS inverter including a PMOS transistor32and an NMOS transistor34is connected to the bit line BLB, and an output terminal of the second CMOS inverter is connected to the bit line BLT. When the power supplies SAP and SAN are supplied to the sense amplifier SA and a potential difference is generated between the pair of the bit lines BLT and BLB after the pair of the bit lines BLT and BLB have been equalized by the transistor21, the potential difference is amplified by these two inverters.

A potential VPP is supplied to each of the PMOS transistors31and32that constitute this sense amplifier SA as a substrate potential, while a potential VBB is supplied to each of the NMOS transistors33and34as a substrate potential. The PMOS transistors31and32and the NMOS transistors33and34constitute this sense amplifier SA. These NMOS transistors33and34and the equalize transistor21are all connected to the common pair of the bit lines (BLT, BLB), and the equalize transistor21is disposed in the vicinity of the sense amplifier SA. It is necessary to supply to the equalize transistor21a substrate bias voltage that is different from a substrate bias voltage for the NMOS transistors33and34of the sense amplifier SA. Thus, a P well for forming the NMOS transistors33and34that constitute the sense amplifier SA and a P well for forming the equalize transistor21are separately provided. Each of the P well for forming the NMOS transistors33and34and the equalize transistor21is formed so that the substrate bias voltage may be independently applied to the P well.

The precharge circuit22includes PMOS transistors35and36. One end of a source and a drain of the PMOS transistor35is connected to the bit line BLT, while the other end of the source and the drain of the PMOS transistor35is connected to a precharging power supply VBLT. One end of a source and a drain of the PMOS transistor36is connected to the bit line BLB, and the other end of the source and the drain of the PMOS transistor36is connected to the precharging power supply VBLT. A potential VPP is supplied to a back gate of each of the PMOS transistors35and36as a substrate potential, as in the case of the PMOS transistors31and32that form the sense amplifier.

FIG. 4is a block diagram of the substrate bias control circuit16. The substrate bias control circuit16that generates the substrate voltage for the equalize transistor21includes a switching control unit41, a reference voltage switching unit42, and a back bias generation unit43.

The switching control unit41receives the equalizing precharge signal PRE-EQ, and outputs a substrate bias selection signal select that is a signal which controls an operation of whether a first substrate bias voltage VB1or a second substrate bias voltage VB2is supplied to the bit line equalize transistor21. As shown inFIG. 4, for example, the switching control unit41may be constituted from a delay circuit (inverter)44which receives the equalizing precharge signal PRE-EQ and outputs an inverted signal that is delayed with respect to the input signal and an AND circuit45that receives the equalizing precharge signal PRE-EQ and the equalizing precharge signal PRE-EQ which has been delayed and inverted by the inverter44. According to the configuration of the switching control unit41inFIG. 4, after the equalizing precharge signal PRE-EQ has risen from low to high, the switching control unit41outputs the substrate bias selection signal select at a high level for a certain period. Otherwise, the switching control unit41outputs the substrate bias selection signal select at a low level. The certain period in which the substrate bias selection signal select outputs the high level is determined by a transmission delay time of the inverter44.

The reference voltage switching unit42receives a first reference voltage signal VB1REF that provides a reference for the first substrate bias voltage VB1and a second reference voltage signal VB2REF that provides a reference for the second substrate bias voltage VB2. The reference voltage switching unit42selects the first reference voltage signal VB1REF or the second reference voltage signal VB2REF, based on the substrate bias selection signal select, and outputs the selected reference voltage signal as a control voltage signal VR. The potential of the first reference voltage signal VB1REF is lower than the potential of the second reference voltage signal VB2REF.

The back bias generation unit43is a circuit that generates the substrate bias voltage Vbbc to be supplied to the bit line equalize transistor21, based on the control voltage signal VR. The back bias generation unit43includes a voltage comparison circuit46that compares a voltage of the control voltage signal VR with the substrate bias voltage Vbbc, a ring oscillator47of which operation is controlled by a result of comparison by the voltage comparison circuit46, and a charge pump circuit48that generates the substrate bias voltage Vbbc based on a clock generated by the ring oscillator47.

The voltage comparison circuit46receives the control voltage signal VR output by the reference voltage switching unit42and a voltage obtained by resistive division by resistors49and50connected in series between a high-potential supply voltage VDD and the substrate bias voltage Vbbc. When the voltage of the control voltage signal VR is high, the voltage comparison circuit46performs control so that oscillation of the ring oscillator47is stopped. When the voltage of the control voltage signal VR is low, the voltage comparison circuit46performs control so that the ring oscillator47oscillates.

The charge pump circuit48is constituted from waveform shaping inverters51and52, a capacitor53, and diodes54and55. The charge pump circuit48inFIG. 4is the charge pump circuit48that generates a negative voltage according to orientations of the diodes54and55. The back bias generation unit43as a whole controls a voltage value of the substrate bias voltage Vbbc so that the voltage obtained by resistive division by the resistors49and50between the substrate bias voltage Vbbc and the high-potential power supply VDD has the same potential as the control voltage signal VR.

Next, an operation of the semiconductor memory device1in the first example will be described, using a waveform diagram inFIG. 5. It is assumed that the semiconductor memory device1is in an activated state (active state) before a time T0. At the time T0, the command decode circuit17captures the precharge command (PRE) supplied from the outside, in synchronization with the clock signal received from the clock signal input terminal CLK. According to capture of the precharge command by the command decode circuit17, the act signal ACT transitions from a high level which is an active level to a low level which is an inactive level. The equalizing precharge signal PRE-EQ transitions from a low level which is an inactive level to a high level which is an active level.

In response to the inactive level of the act signal ACT, the potential of a predetermined word line (WL) which has been at a high level of a selection state transitions to a low level of a nonselection state. Further, in response to the active level of the equalizing precharge signal PRE-EQ, the switching control unit41of the substrate bias control circuit16causes the selection signal select to transition from the low level to the high level.

In response to the high level of the selection signal select, the reference voltage switching unit42of the substrate bias control circuit16switches the control voltage signal VR to be supplied to the back bias generation unit43from a voltage VB1REF to a voltage VB2REF that has a higher potential. In response to switching of the control voltage signal VR to the voltage VB2REF, the back bias generation unit43of the substrate bias control circuit16switches the substrate bias voltage Vbbc of the bit line equalize transistor21to the shallower (higher-voltage) substrate bias voltage VB2from the deep (lower-voltage) substrate bias voltage VB1.

The precharge signal PRET transitions from a low level of an inactive level to a high level of an active level after a predetermined time of delay (at a time T1inFIG. 5) through the delay circuit Delay after capture of the precharge command by the command decode circuit17. When the precharge signal PRET assumes the active level, the bit line equalize transistor21turns on. Bit line equalization is thereby started.

At a time T2, an output of the inverter circuit44provided at the substrate bias control circuit16for signal delay is inverted to a low level, and an output signal of the AND circuit45is inverted due to that inversion. Then, the selection signal select transitions from the high level to the low level. In response to transition of the selection signal select to the low level, the potential of the control voltage signal VR switches from the voltage VB2REF to the voltage VB1REF, and the substrate bias voltage Vbbc generated by the back bias generation unit43also switches from the shallow substrate bias VB2to the deeper substrate bias voltage VB1.

The timing (timing at the time T2) at which the selection signal select transitions to the low level again after activation of the equalizing precharge signal PRE-EQ may be at least after bit line pair equalization has been completed. Preferably, this switch timing (timing at which the substrate bias voltage of the bit line equalize transistor21is returned to the deeper voltage, or the timing of the time T2) is set after completion of the bit line equalization and before a timing at which an amplification operation (which will be described later) of a potential difference of a bit line pair by the sense amplifier is completed. This setting is made for the following reason. When the selection signal select transitions to the low level from the high level before completion of the bit line pair equalization and then the substrate bias of the bit line equalize transistor21is reduced (becomes deeper) during the bit line equalization, current driving capability of the bit line equalize transistor21is reduced. As a result, a bit line equalization time after reduction of the current driving capability is increased. Further, after the amplification operation by the sense amplifier has been completed, a potential difference between the bit line pair, or a source-to-drain voltage of the bit line equalize transistor21is increased. Off current that flows through the bit line equalize transistor is therefore increased. Current consumption of the semiconductor memory device1is thus increased. Thus, the setting described above is made.

At a time T3, the command decode circuit17causes the equalizing precharge signal PRE-EQ to transition from the high level of the active level to the low level of the inactive level. After an elapse of a predetermined delay time from transition from the active level to the inactive level of the equalizing precharge signal PRE-EQ, the precharge signal (PRET) transitions from the high level of the active level to the low level of the inactive level (at a time T4inFIG. 5).

In response to transition of the precharge signal PRET to an inactive state, the bit line equalize transistor21turns off, and the semiconductor memory device1assumes a stand-by state (idle state).

At a time T5, the command decode circuit17captures the active command (ACT) supplied from the outside, in synchronization with the clock (CLK). In response to capture of the active command by the command decode circuit17, the act signal ACT transitions from the low level of the inactive level to the high level of the active level.

In response to the high level of the active level of the act signal ACT, the semiconductor memory device1assumes the active state. Specifically, the potential of the word line (WL) corresponding to the row address supplied from the outside transitions from the low level of the nonselection state to the high level of the selection state. Then, data (electric charge) held in the memory cell connected to the word line that has assumed the selection state is read onto the pair of the bit lines (BLT/BLB), and a potential difference between the pair of the bit lines is amplified by the sense amplifier. Then, a read command or a write command is supplied from the outside. The semiconductor memory device1thereby performs a desired operation (not shown). When the precharge command (PRE) is supplied again from the outside after the desired operation has been finished, time is returned to the time T0shown inFIG. 5. The operations are thereby repeated.

Second Example

FIG. 6is a block diagram of a semiconductor memory device according to a second example. Same reference characters are assigned to components that are comparable to those in the first example, thereby omitting detailed description. In the second example, in addition to the equalizing precharge signal PRE-EQ, the act signal ACT is also supplied to the substrate bias control circuit16from the command decode circuit17. The second example is different from the first example in this respect. The other configurations are the same as those in the first example.

FIG. 7is a block diagram of the substrate bias control circuit16in the second example. The substrate bias control circuit16in the second example is different from the substrate bias control circuit (inFIG. 4) in the first example in the configuration of the switching control unit41. Configurations of the reference voltage switching unit42and the back bias generation unit43except the switching control unit41are the same as those in the first example.

In addition to the equalizing precharge signal PRE-EQ, the act signal ACT is connected to the switching control unit41in the second example, as an input signal. When the equalizing precharge signal PRE-EQ transitions from the low level to the high level in the second example, the switching control unit41outputs a high level to a selection signal select, and switches the substrate bias voltage Vbbc to the shallow substrate bias voltage VB2. A condition in which this substrate bias voltage Vbbc is switched to the shallow substrate bias voltage VB2continues also after the equalizing precharge signal PRE-EQ has returned to the low level, and continues until the act signal ACT goes high. When the act signal ACT goes high from low, the selection signal select goes low from high, thereby switching the substrate bias voltage Vbbc to the deep substrate bias voltage VB1.

As described inFIG. 7in the form of an example, the switching control unit41that implements such a function may be implemented by providing a flip-flop circuit (constituted from NOR circuits71and72) that is set by the equalizing precharge signal PRE-EQ and is reset by the act signal ACT, and by setting an output of the flip-flop circuit as the selection signal select in the circuit configuration of the switching control unit41.

FIG. 8is a waveform diagram of the semiconductor device1in the second example. Referring toFIG. 8, description of components of which operations are the same as those inFIG. 5that is the waveform diagram of the first example, will be omitted, and components of which operations are different from those inFIG. 5will be described.

Referring toFIG. 8, upon receipt of the precharge command (PRE), the equalizing precharge signal PRE-EQ rises, the selection signal select rises, and the substrate bias voltage Vbbc of the bit line equalize transistor21changes from the voltage VB1to the voltage VB2. These operations are the same as those in the first example. The word line WL assumes the nonselection state in response to a fall of the act signal ACT, and bit line equalization is started when the delayed precharge signal PRET rises. These operations are also the same as those in the first example.

The first example is different from the second example in a timing at which the selection signal select falls, and the substrate bias voltage Vbbc of the bit line equalize transistor21changes from the voltage VB2to the voltage VB1. In the second example, the condition in which the substrate bias voltage Vbbc is the shallow substrate bias voltage VB2continues until the active command (ACT) is supplied to the command decode circuit17. When the active command (ACT) is supplied from an outside at a time T4in synchronization with the clock signal CLK, the command decode circuit17activates the act signal ACT. When the act signal ACT is activated to go high, the switching control unit41of the substrate bias control circuit16causes the selection signal select to fall from high to low. Thus, the substrate bias voltage Vbbc output from the substrate bias control circuit16changes to the deep first substrate bias voltage VB1from the shallow second substrate bias voltage VB2. The word line WL selected upon receipt of the active command is activated, data from a selected memory cell is read onto the bit line due to activation of the word line WL, and the potential of the bit line is amplified by the sense amplifier SA. These operations are the same as those in the first example.

In the first example, after the precharge command has been received and the substrate bias voltage Vbbc of the bit line equalize transistor21has become the shallow second substrate bias voltage VB2, the substrate bias voltage Vbbc automatically returns to the deep first substrate bias voltage VB1after a certain period of time. On contrast therewith, in the second example, after the substrate bias voltage Vbbc of the bit line equalize transistor21has become the shallow second substrate bias voltage VB2due to reception of the precharge command, the condition where the substrate bias voltage Vbbc is the shallow voltage continues until the active command has been received. With execution of the active command, the substrate bias voltage Vbbc returns to the deep first substrate voltage VB1. These operations are different from those in the first example.

The threshold value of the transistor21at a time of equalization may be a low threshold value corresponding to a depletion transistor, in the first and second examples. It is because, before cell data is read onto a bit line due to activation of a word line, it is possible to return the substrate bias voltage to the deep voltage and return the threshold value of the bit line equalize transistor21to a high voltage. When equalization is not performed, Ioff current can be reduced by deepening the substrate bias voltage more than in a related art.

In the first and second examples, the bit line equalize transistor21was described as the N-type MOS transistor. A P-type MOS transistor, however, may also be used as the bit line equalize transistor21. In this case as well, the substrate bias control circuit16may control the substrate bias voltage Vbbc so that the threshold voltage of the bit line equalize transistor is reduced according to activation of the equalizing precharge signal PRE-EQ and the threshold voltage of the bit line equalize transistor is increased according to transition of the select signal select from the high level to the low level or reception of the active command. That is, when the P-type MOS transistor is used as the bit line equalize transistor21, the substrate bias control circuit16may perform control so that the substrate bias voltage Vbbc is reduced according to activation of the equalizing precharge signal PRE-EQ and the substrate bias voltage Vbbc is increased according to transition of the select signal select from the high level to the low level or reception of the active command.

Description was given about each of the examples where bit lines of the semiconductor memory device are equalized. The present invention may be applied to equalization before amplification of a difference voltage between two sense lines by the sense amplifier, in addition to bit line equalization. By controlling the substrate bias voltage of the equalize transistor, high-speed equalization can be performed, and leak current between the sense lines can be prevented at a timing in a period other than a period of the equalization.

The above description was given about the examples. The present invention is not limited to only configurations of the examples described above, and of course includes various variations and modifications that could be made by those skilled in the art within the range of the present invention.