Imaging device

An imaging device includes a semiconductor substrate including a semiconductor region including an impurity of a first conductivity type, a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region, a first transistor that includes a first gate electrode and that includes the second diffusion region as one of a source and a drain, a contact plug electrically connected to the second diffusion region, a capacitive element one end of which is electrically connected to the contact plug, and a second transistor that includes a second gate electrode, the second gate electrode being electrically connected to the one end of the capacitive element.

BACKGROUND

1. Technical Field

The present disclosure relates to an imaging device.

2. Description of the Related Art

Charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors are widely used for digital cameras and the like. As widely known, these image sensors each include photodiodes formed on a semiconductor substrate.

In order to form photoelectric conversion units such as photodiodes and peripheral circuits on a semiconductor substrate in such an image sensor, a method for reducing pixel size while achieving a dynamic range has been conceived (Japanese Unexamined Patent Application Publication No. 2015-233122).

SUMMARY

It is desired to increase a dynamic range while reducing dark current.

In one general aspect, the techniques disclosed here feature an imaging device including a semiconductor substrate including semiconductor region including an impurity of a first conductivity type, first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type different from the first conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region; a first transistor that includes a first gate electrode located on the semiconductor substrate and that includes the second diffusion region as one of a source and a drain; a contact plug electrically connected to the second diffusion region; a capacitive element one end of which is electrically connected to the contact plug; and a second transistor that includes a second gate electrode located on the semiconductor substrate, the second gate electrode being electrically connected to the one end of the capacitive element.

It should be noted that a general or specific aspect may be implemented as an element, a device, a module, a system, a method, or any selective combination thereof.

DETAILED DESCRIPTION

In the imaging device described in Japanese Unexamined Patent Application Publication No. 2015-233122, a dynamic range is increased by providing a pixel circuit such as a signal detection circuit in a layer different from one in which a photodiode is provided. In the imaging device described in Japanese Unexamined Patent Application Publication No. 2015-233122, however, it is difficult to say that the dynamic range can be increased while reducing dark current. It is desired to increase the dynamic range while reducing dark current.

An outline of an aspect of the present disclosure is as follows.

An imaging device including:

a semiconductor substrate includinga semiconductor region including an impurity of a first conductivity type,a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type different from the first conductivity type, and that converts incident light into charges, anda second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region;

a first transistor that includes a first gate electrode located on the semiconductor substrate and that includes the second diffusion region as one of a source and a drain;

a contact plug electrically connected to the second diffusion region;

a capacitive element one end of which is electrically connected to the contact plug; and

a second transistor that includes a second gate electrode located on the semiconductor substrate, the second gate electrode being electrically connected to the one end of the capacitive element.

The imaging device according to Item 1, wherein the semiconductor substrate includes a third diffusion region that covers an upper surface of the first diffusion region and that includes an impurity of the first conductivity type.

The imaging device according to Item 1, wherein

the semiconductor substrate includes a well region including an impurity of the first conductivity type, and

the second diffusion region is located in the well region.

The imaging device according to Item 2, wherein the semiconductor substrate includes a first isolation region that electrically insulates the second diffusion region and the third diffusion region from each other.

The imaging device according to Item 4, wherein

the first isolation region includes a second isolation region, and

a concentration of the impurity of the first conductivity type in the second isolation region is higher than a concentration of the impurity of the first conductivity type in the third diffusion region.

The imaging device according to Item 1, wherein the semiconductor substrate includes a fourth diffusion region that is in contact with the first diffusion region and the second diffusion region and that includes an impurity of the second conductivity type.

The imaging device according to Item 3, wherein the second diffusion region faces the first diffusion region through the well region.

The imaging device according to Item 1, wherein

the semiconductor substrate includes a fifth diffusion region including an impurity of the second conductivity type,

the first transistor includes the fifth diffusion region as the other of the source and the drain, and

a concentration of the impurity of the second conductivity type in the second diffusion region is lower than a concentration of the impurity of the second conductivity type in the fifth diffusion region.

The imaging device according to Item 1, wherein

the semiconductor substrate includes a fifth diffusion region including an impurity of the second conductivity type,

the first transistor includes the fifth diffusion region as the other of the source and the drain, and

when viewed in a direction perpendicular to the semiconductor substrate, an area of the second diffusion region is smaller than an area of the fifth diffusion region.

In addition, an outline of another aspect of the present disclosure is as follows.

An imaging device according to the other aspect of the present disclosure includes a semiconductor substrate including a first surface and a second surface opposite the first surface, a well region that is located in the semiconductor substrate and that includes an impurity of a first conductivity type, a photoelectric conversion unit that includes a first diffusion region in contact with the well region and including an impurity of the second conductivity type different from the first conductivity type, and a third diffusion region exposed on the first surface, in contact with the first diffusion region, and including an impurity of the first conductivity type and that converts incident light into charges, a second diffusion region that is exposed on the first surface, that is located in the well region, that is electrically connected to the first diffusion region in the semiconductor substrate, that includes an impurity of the second conductivity type, and that accumulates the charges, a first transistor including the second diffusion region as one of a source and a drain, a contact plug connected to the second diffusion region, a capacitive element electrically connected to the second diffusion region through the contact plug, and a second transistor a gate of which is electrically connected to the capacitive element.

As described above, when the third diffusion region is provided in the photoelectric conversion unit between the first diffusion region and the first surface of the semiconductor substrate, dark current that can be caused due to a defect at an interface between the first diffusion region and the semiconductor substrate is pinned in the third diffusion region. As a result, dark current at the interface between the first diffusion region and the semiconductor substrate can be reduced more effectively.

In addition, when both the first diffusion region and the second diffusion region include an impurity of the second conductivity type and the second diffusion region is electrically connected to the first diffusion region, charges generated in the first diffusion region can be directly accumulated in the second diffusion region. A transfer transistor that transfers charges generated as a result of photoelectric conversion from the first diffusion region to the second diffusion region, therefore, becomes unnecessary. When charges are transferred through the transfer transistor, dark current is caused due to the transfer transistor. In the imaging device according to the other aspect of the present disclosure, however, the first diffusion region of the photoelectric conversion unit and the second diffusion region that accumulates charges are directly connected to each other electrically, dark current caused during the accumulation of charges can be reduced. In addition, since the transfer transistor is not necessary, a pixel circuit can be reduced in size. As a result, a large photoelectric conversion unit can be formed, and a dynamic range of the imaging device can be increased.

In addition, since the second diffusion region that accumulates charges and the capacitive element are electrically connected to each other, the second diffusion region can achieve a higher capacitance. The dynamic range, therefore, can be further increased.

For example, the imaging device according to the other aspect of the present disclosure may further include a first isolation region that electrically insulates the second diffusion region and the third diffusion region from each other.

As a result, dark current caused between the third diffusion region, which includes the impurity of the first conductivity type, and the second diffusion region, which includes the impurity of the second conductivity, can be reduced.

For example, the imaging device according to the other aspect of the present disclosure may further include a second isolation region that is located around the first isolation region and that includes an impurity of the first conductivity type with a concentration higher than in the third diffusion region.

The imaging device according to the other aspect of the present disclosure thus includes, around the first isolation region, that is, at an interface between the first isolation region and the third diffusion region and an interface between the first isolation region and the second diffusion region, for example, the second isolation region including the impurity of the first conductivity type whose concentration is higher than that of the impurity of the first conductivity type in the third diffusion region. As a result, a potential barrier is formed between the second diffusion region and the third diffusion region, and the second diffusion region and the third diffusion region can be more strongly insulated from each other electrically. Dark current caused between the second diffusion region and the third diffusion region can be further reduced.

For example, the imaging device according to the other aspect of the present disclosure may further include a fourth diffusion region in contact with the first diffusion region and the second diffusion region and including an impurity of the second conductivity type.

With this configuration, the first diffusion region and the second diffusion region can be securely connected to each other electrically through the fourth diffusion region.

For example, in the imaging device according to the other aspect of the present disclosure, the first diffusion region and the second diffusion region may face each other through the well region.

With this configuration, the well region serves as a potential region, and if the amount of charge accumulated in the first diffusion region becomes equal to or larger than a certain value, charges flow into the third region.

For example, in the imaging device according to the other aspect of the present disclosure, the concentration of the impurity of the second conductivity type in the second diffusion region may be lower than in the other of the source and the drain of the first transistor.

Since the concentration of the impurity of the second conductivity type included in the second diffusion region is lower than in the other of the source and the drain of the first transistor, contact concentration at a contact between the second diffusion region and the well region decreases. Dark current in the second diffusion region, therefore, can be reduced.

For example, in the imaging device according to the other aspect of the present disclosure, when viewed in a direction perpendicular to the semiconductor substrate, the second diffusion region may be smaller in area than the other of the source and the drain of the first transistor.

By making the second diffusion region small in area, dark current in the second diffusion region can be reduced.

An embodiment of the present disclosure will be described in detail hereinafter with reference to the drawings. The following embodiment is a general or specific example. Values, shapes, materials, components, arrangement and connection modes of the components, steps, order of the steps, and the like mentioned in the following embodiment are examples, and do not limit the present disclosure. Various aspects described herein may be combined together insofar as no contradiction is caused. Among the components described in the following embodiment, ones not described in the independent claim, which defines a broadest concept, will be described as optional components. Components having substantially the same functions are given the same reference numerals in the drawings, and redundant description thereof might be omitted or simplified.

Various elements illustrated in the drawings are schematically illustrated to facilitate understanding of the present disclosure, and dimensions and appearances thereof might be different from reality.

A light receiving side of an imaging device will be referred to as an “upper side” and an opposite side of the imaging device will be referred as a “lower side” herein. Surfaces of members oriented on the light receiving side of the imaging device will be referred to as “upper surfaces”, and surfaces of the members oriented on the opposite side of the imaging device will be referred to as “lower surfaces”. The terms “upper side”, “lower side”, “upper surfaces”, and “lower surfaces” are used to specify relative orientations of the members and not intended to limit an attitude of the imaging device during use.

Embodiment

FIG. 1is a diagram illustrating the circuit configuration of an imaging device100A according to the present embodiment.

The imaging device100A illustrated inFIG. 1includes a plurality of pixels10A and peripheral circuits. The pixels10A are arranged on a semiconductor substrate in two dimensions to form a pixel area.

In an example illustrated inFIG. 1, the pixels10A are arranged in row and column directions. The row and column directions herein refer to directions in which rows and columns extend. That is, a length direction of the drawings is the column direction, and a width direction of the drawings is the column direction. The pixels10A may be arranged in one dimension, instead.

The pixels10A are each connected to a power supply line50. A certain power supply voltage Vdd is supplied to each of the pixels10A through the power supply line50. As described in detail later, the pixels10A each include a photoelectric conversion unit12(also referred to as a “photodiode12”) in the semiconductor substrate. The photoelectric conversion unit12includes a first diffusion region2(refer toFIG. 2) that converts incident light into charges. As illustrated inFIG. 1, the imaging device100A includes accumulation control lines51for applying a constant voltage to anodes of all the photodiodes12.

The peripheral circuits of the imaging device100A include a vertical scanning circuit30(also referred to as a “row scanning circuit”), load circuits42, column signal processing circuits43(also referred to as “row signal accumulation circuits”), a horizontal signal reading circuit40(also referred to as a “column scanning circuit”), and inverting amplifiers45. In the example of the configuration illustrated inFIG. 1, a column signal processing circuit43, a load circuit42, and an inverting amplifier45is provided for each column of the pixels10A arranged in two dimensions. That is, in this example, the peripheral circuits include a plurality of column signal processing circuits43, a plurality of load circuits42, and a plurality of inverting amplifiers45.

Address signal lines31and reset signal lines32are connected to the vertical scanning circuit30. The vertical scanning circuit30outputs certain voltages to the address signal lines31to select the pixels10A in units of rows. As a result, signal voltages of the selected pixels10A are read and pixel electrodes are reset, the latter of which will be described later.

The pixels10A arranged in each column are electrically connected to one of the column signal processing circuits43through a corresponding vertical signal line41. Each vertical signal line41is connected to a corresponding one of the load circuits42. The column signal processing circuits43perform noise reduction signal processing typified by correlated double sampling, analog-to-digital conversion (A/D conversion), and the like. The horizontal signal reading circuit40is connected to the column signal processing circuits43provided in correspondence with the columns of the pixels10A. The horizontal signal reading circuit40sequentially reads signals from the column signal processing circuits43to a horizontal common signal line44.

In the example of the configuration illustrated inFIG. 1, the inverting amplifiers45are provided in correspondence with the columns of the inverting amplifiers45. Negative input terminals of the inverting amplifiers45are connected to the corresponding vertical signal lines41. A certain voltage is supplied to positive input terminals of the inverting amplifiers45. The certain voltage is, for example, a positive voltage of 1 V or about 1 V. Output terminals of the inverting amplifiers45are connected to pixels10A connected to the negative input terminals of the inverting amplifiers45through feedback lines46provided in correspondence with the columns. The inverting amplifiers45constitute a part of feedback circuits47for negatively feeding back outputs of the pixels10A. The inverting amplifiers45may be referred to as feedback amplifiers.

The photodiodes12are photoelectric conversion regions that receive incident light and that cause positive and negative charges, that is, hole-electron pairs. The photodiodes12are, for example, p-n junction photodiodes. The photodiodes12are connected to the accumulation control lines51, and a certain voltage is applied to the accumulation control lines51during operation of the imaging device100A. By applying the certain voltage to the accumulation control lines51, either positive charges or negative charges generated as a result of photoelectric conversion are used as signal charges.

The pixels10A each include a signal detection circuit electrically connected to the photodiode12. In the example of the configuration illustrated inFIG. 1, the signal detection circuits each include an amplifier transistor22and a reset transistor23. In this example, the signal detection circuits each further include an address transistor21. The amplifier transistor22, the reset transistor23, and the address transistor21of each signal detection circuit are typically field-effect transistors (FETs) formed on the semiconductor substrate. In the following description, an example in which n-channel metal-oxide-semiconductor (MOS) transistors are used as the transistors will be described. Assignment of a source and a drain to two diffusion layer of each FET is determined on the basis of the polarity of the FET and potentials at the time. Assignment of a source and a drain can therefore vary depending on an operation state of each FET.

The pixels10A each further include a capacitive element60. The capacitive element60has a structure in which a dielectric layer such as an insulating film is sandwiched between electrodes. The electrodes herein are not limited to ones composed of a metal and may be interpreted to broadly include a polysilicon layer or the like. The electrodes herein may be parts of the semiconductor substrate.

In the example of the configuration illustrated inFIG. 1, a second diffusion region3(refer toFIG. 2) and one of the electrodes of each capacitive element60together form a charge accumulation region. A gate of each amplifier transistor22is also a part of the charge accumulation region. The charge accumulation region will also be referred to as a floating diffusion node. Here, the floating diffusion node refers to wires electrically connecting a drain of each reset transistor23, an electrode of each capacitive element60that is not connected to a reference voltage PVDD, the gate of each amplifier transistor22, and a cathode of each photodiode12and the second diffusion region3. Charges generated by each photodiode12are accumulated in the charge accumulation region. InFIG. 1, the second diffusion region3is the drain of each reset transistor23. The second diffusion region3may be either a source or a drain of a transistor other than the reset transistor23, instead.

A drain of each amplifier transistor22is connected to the power supply line50for supplying the certain power supply voltage Vdd (e.g., about 3.3 V) to each pixel10A during operation of the imaging device100A. In other words, each amplifier transistor22outputs a signal voltage according to the amount of signal charge generated by the corresponding photodiode12. A source of the amplifier transistor22is connected to a drain of the address transistor21.

The vertical signal lines41are connected to sources of the address transistors21. As illustrated inFIG. 1, the vertical signal line41is provided for each column of the pixels10A, and the load circuit42and the column signal processing circuit43are connected to each of the vertical signal lines41. Each load circuit42forms a source follower circuit together with the corresponding amplifier transistor22.

The address signal lines31are connected to gates of the address transistors21. The address signal line31is provided for each row of the pixels10A. The address signal lines31are connected to the vertical scanning circuit30, and the vertical scanning circuit30applies row selection signals for turning on or off the address transistors21to the address signal lines31. As a result, rows to be read are scanned in a vertical direction (column direction) and selected. The vertical scanning circuit30controls turning on and off of the address transistors21through the address signal lines31to read outputs of the amplifier transistors22of the selected pixels10A to the corresponding vertical signal lines41. The arrangement of each address transistor21is not limited to the example illustrated inFIG. 1. Each address transistor21may be provided between the drain of the amplifier transistor22and the power supply line50, instead.

The signal voltages from the pixels10A output to the vertical signal lines41through the address transistors21are input to the corresponding column signal processing circuit43among column signal processing circuits43provided for the columns of the pixels10A in correspondence with the vertical signal lines41.

The reset signal lines32connected to the vertical scanning circuit30are connected to the gates of the reset transistor23. As with the address signal lines31, the reset signal line32is provided for each row of the pixels10A. The vertical scanning circuit30applies row selection signals to the address signal lines31to select pixels10A to be reset in units of rows. The vertical scanning circuit30also applies reset signals for controlling turning on and off of the reset transistors23to the gates of the reset transistors23through the reset signal lines32to turn on the reset transistors23in the selected rows. When the reset transistor23are turned on, potentials of the charge accumulation regions are reset.

In this example, a source of the reset transistor23is connected to one of the feedback lines46provided for the columns of the pixels10A. That is, in this example, voltages of the feedback lines46are supplied to the charge accumulation regions as reset voltages for initializing charges of the photodiodes12. Here, the feedback line46is connected to the output terminal of a corresponding one of the inverting amplifiers45provided for the columns of the pixels10A.

One of the columns of the pixels10A will be focused upon hereinafter. As illustrated inFIG. 1, the input terminal of the inverting amplifier45is connected to the vertical signal line41in the column. The output terminal of the inverting amplifier45is connected to one or more pixels10A in the column through the feedback line46. During operation of the imaging device100A, a certain voltage Vref (e.g., a positive voltage of 1 V or about 1 V) is supplied to a non-inverting input terminal of the inverting amplifier45. By selecting one of the one or more pixels10A in the column and turning on the address transistor21and the reset transistor23, a feedback path for negatively feeding back the output of the pixel10A can be formed. As a result of the formation of the feedback path, the voltage of the vertical signal line41is restricted to the voltage Vref input to the non-inverting terminal of the inverting amplifier45. In other words, as a result of the formation of the feedback path, the voltage of the charge accumulation region is reset to a voltage with which the voltage of the vertical signal line41becomes Vref. As the voltage Vref, any voltage within a range of the power supply voltage (e.g., 3.3 V) to ground voltage (0 V) may be used. The imaging device100A thus includes the feedback circuits47, each including the inverting amplifier45as a part of the feedback path.

As widely known, thermal noise called kTC noise is caused as a transistor is turned on or off. Noise caused as a reset transistor is turned on or off is called reset noise. Reset noise caused as the reset transistor23is turned off after the charge accumulation region is reset undesirably remains in the charge accumulation region before signal charges are accumulated. In the example of the configuration illustrated inFIG. 1, however, an alternating current component of kTC noise is fed back to the source of the reset transistor23as a result of the formation of the feedback path. Since the feedback path is formed until immediately before the reset transistor23is turned off in the example of the configuration illustrated inFIG. 1, reset noise caused as the reset transistor23is turned off can be reduced.

Next, the configuration of the pixels10A according to the embodiment will be described with reference toFIG. 2.FIG. 2is a diagram illustrating the configuration of each of the pixels10A of the imaging device100A according to the present embodiment.

In the present embodiment, an example in which the transistors are n-channel MOS transistors is described. A first conductivity type will be referred to as a p-type and a second conductivity type will be referred to as an n-type hereinafter.

The imaging device100A according to the present embodiment includes a semiconductor substrate1and the pixels10A. The semiconductor substrate1includes a p-type region90and an n-type region80. The semiconductor substrate1also includes a first surface1aand a second surface1bopposite the first surface1a. The first surface1ais a surface in contact with an insulating layer7. Contact plugs8aand8b, contact plugs18aand18b, a first wire71, a second wire72, a third wire73, a fourth wire74, and the like are provided in the insulating layer7.

The pixels10A each include, in the p-type region90, a well region11including a p-type impurity, a photoelectric conversion unit12that converts incident light into charges, and the second diffusion region3that accumulates charges.

The photoelectric conversion unit12includes the first diffusion region2and a third diffusion region6. The first diffusion region2is in contact with the p-type region90and the well region11and includes an n-type impurity, which is different from a p-type impurity. The third diffusion region6covers an upper surface of the first diffusion region. The third diffusion region6is exposed on the first surface1aof the semiconductor substrate1, in contact with the first diffusion region2, and includes a p-type impurity. The first diffusion region2and the third diffusion region6together form a photodiode.

In the photoelectric conversion unit12, the third diffusion region6is thus provided between the first diffusion region2and the first surface1aof the semiconductor substrate1, and dark current that can be caused due to a defect at an interface between the first diffusion region2and the p-type region90is pinned. As a result, dark current at the interface between the first diffusion region2and the p-type region90can be reduced more effectively.

The second diffusion region3is exposed on the first surface1aof the semiconductor substrate1, located in the well region11, electrically connected to the first diffusion region2in the p-type region90, includes an n-type impurity, and accumulates charges.

As a result, charges generated in the first diffusion region2can be directly accumulated in the charge accumulation region. In a conventional configuration, a transfer transistor is provided between a photodiode and a charge accumulation region. With this conventional configuration, dark current is caused due to the transfer transistor. In the imaging device according to the present disclosure, however, the first diffusion region2and the charge accumulation region are directly connected to each other electrically, and dark current caused during accumulation of charges can be reduced. As a result, charge accumulation efficiency can be improved. In addition, since each pixel circuit does not include a transfer transistor, the pixel circuit can be reduced. As a result, large photoelectric conversion units can be formed, and a dynamic range of the imaging device can be increased.

The pixels10A each include a first transistor (hereinafter referred to as a reset transistor23) including the second diffusion region3as either a source or a drain, the contact plug8aconnected to the second diffusion region3, the capacitive element60electrically connected to the second diffusion region3through the contact plug8a, and a second transistor (hereinafter referred to as an amplifier transistor22) whose gate is electrically connected to the capacitive element60.

In the examples illustrated inFIGS. 1 and 2, the reset transistors23each include the second diffusion region3, a gate electrode4, and an n-type impurity region5a. The second diffusion region3is either the source or the drain of the reset transistor23, and the n-type impurity region5ais the other of the source and the drain of the reset transistor23. The n-type impurity region5ais electrically connected to the corresponding feedback line46, and the gate electrode4is electrically connected to the corresponding reset signal line32. The amplifier transistors22each include an n-type impurity region5b, a gate electrode4, and an n-type impurity region5c. The n-type impurity region5bis one of the source and the drain of the amplifier transistor22, and the n-type impurity region5cis the other of the source and the drain of the amplifier transistor22. The n-type impurity region5bis electrically connected to the certain power supply voltage Vdd, and the gate electrode4is electrically connected to the capacitive element60through the contact plug8b. The address transistors21each include the n-type impurity region5c, a gate electrode4, and an n-type impurity region5d. The n-type impurity region5cis one of the source and the drain of the address transistor21, and the n-type impurity region5dis the other of the source and the drain of the address transistor21. The n-type impurity region5dis electrically connected to the corresponding vertical signal line41through the contact plug18a, and the gate electrode4is electrically connected to the corresponding address signal line31.

The capacitive element60may be provided in the semiconductor substrate1, or may be provided in a layer other than the semiconductor substrate1, namely, for example, the insulating layer7stacked on the semiconductor substrate1. In the present embodiment, the capacitive element60is provided in the insulating layer7stacked on the semiconductor substrate1. The capacitive element60includes an upper electrode161, a lower electrode163, and a dielectric film162located between the upper electrode161and the lower electrode163. The upper electrode161is connected to the reference voltage PVDD of the capacitive element60. The lower electrode163is in contact with the contact plug18b. As a result, the capacitive element60is connected to the second diffusion region3through the contact plug18band the contact plug8aand to the gate electrode4of the amplifier transistor22through the contact plug18b, the first wire71, and the contact plug8b.

As described with reference toFIG. 1, the capacitive elements60each have a structure in which a dielectric (here, the dielectric film162) is sandwiched between two electrodes (here, the upper electrode161and the lower electrode163) composed of a metal or a metal compound. The structure in which a dielectric is sandwiched between two electrodes composed of a metal or a metal compound will be referred to as a “metal-insulator-metal (MIM) structure” hereinafter. In the present embodiment, the capacitive elements60are formed as capacitive elements60having a so-called MIM structure. The second diffusion regions3and the capacitive elements60formed in this manner are electrically connected to each other, so that the charge accumulation regions can achieve higher capacitances. The imaging device according to the present disclosure, therefore, can further increase the dynamic range.

In addition, for example, by setting the capacitances of the capacitive elements60twice or more as high as the capacitances of the second diffusion regions3, saturation performance of the pixels10A can be further improved. In order to set the capacitances of the capacitive elements60twice or more as high as the capacitances of the second diffusion regions3, for example, the capacitive elements60may have the MIM structure and a relative dielectric constant of each dielectric film162sandwiched between the upper electrode161and the lower electrode163may be 10 or more. A dielectric film whose relative dielectric constant is 10 or more is, for example, a film composed of hafnium oxide. A relative dielectric constant of hafnium oxide is about 20. A relative dielectric constant of silicon oxide, which is used as a material of a conventional dielectric film having the MIM structure, is about 3.8 to 4. By making the relative dielectric constant of each dielectric film162larger, the capacitance of the capacitive element60can be made higher.

The pixels10A each include a signal detection circuit electrically connected to the photoelectric conversion unit12. In the example of the configuration illustrated inFIG. 2, the signal detection circuit includes the address transistor21, the amplifier transistor22, and the reset transistor23. As illustrated inFIG. 2, the reset transistor23includes the second diffusion region3, the n-type impurity region5a, a part of a gate insulating film (not illustrated), and the gate electrode4on the gate insulating film. The second diffusion region3and the n-type impurity region5afunction as a drain region and a source region, respectively, of the reset transistor23. The second diffusion region3is a region for temporarily accumulating signal charges generated by the first diffusion region2of the photoelectric conversion unit12.

In addition, in the present embodiment, the reset transistor23is provided in the well region11. The well region11has a p-type impurity concentration (p) slightly higher than a p-type impurity concentration (p-) of the p-type region90.

Furthermore, in the present embodiment, an n-type impurity concentration of the second diffusion region3is lower than that of the n-type impurity region5a, which is the other of the source and the drain of the reset transistor23. As a result, a contact concentration at a contact part between the second diffusion region3and the well region11becomes lower, and dark current at an interface between the second diffusion region3and the well region11is reduced.

When viewed in a direction perpendicular to the semiconductor substrate1, the second diffusion region3is smaller in area than the n-type impurity region5a, which is the other of the source and the drain of the reset transistor23. At this time, the area of the second diffusion region3and the n-type impurity region5amay be, when viewed in the direction perpendicular to the semiconductor substrate1, the area of the second diffusion region3and the n-type impurity region5aexcept for overlaps with the gate electrode4of the reset transistor23. That is, the area of the second diffusion region3and the n-type impurity region5amay be, when viewed in the direction perpendicular to the semiconductor substrate1, the area of parts of the second diffusion region3and the n-type impurity region5athat do not overlap the gate electrode4of the reset transistor23.

By making the area of the second diffusion region3smaller, dark current in the second diffusion region3can be reduced.

In the imaging device100A according to the present embodiment, isolation regions9are provided between adjacent pixels10A in such a way as to surround the pixels10A when viewed in the direction perpendicular to the semiconductor substrate1. The isolation regions9are insulating films for electrically separating adjacent pixels10A from one another and provided in the p-type region90. As a result, the signal detection circuits can be electrically separated from one another between adjacent pixels10A. With this configuration, mixing of colors and blooming can be suppressed in the semiconductor substrate1between adjacent pixels10A.

The isolation regions9may be provided in such a way as not only to electrically separate adjacent pixels10A from one another but also to, for example, electrically separate adjacent elements provided in each pixel10A from one another. In this case, for example, the isolation regions9are provided around the address transistor21and a combination of the amplifier transistor22and the reset transistor23.

The isolation regions9are formed using an oxide such as silicon dioxide. Furthermore, the isolation regions9may be coated by a high-concentration p-type impurity. In this case, dark current caused at an interface between each isolation region9and an adjacent board or element can be reduced.

First Modification

Next, the configuration of pixels according to a first modification of the present embodiment will be described with reference toFIG. 3.FIG. 3is a diagram illustrating the configuration of each of a plurality of pixels10B according to the present modification. The circuit configuration of an imaging device according to the present modification is the same as that of the imaging device according to the embodiment illustrated inFIG. 1.

Components different from those according to the embodiment will be described hereinafter.

In the imaging device according to the present modification, the pixels10B each include a first isolation region19for electrically insulating the third diffusion region6and the second diffusion region3from each other. As a result, dark current caused between the third diffusion region6, which includes a p-type impurity, and the second diffusion region3, which includes an n-type impurity, can be reduced.

As with the isolation regions9, the first isolation region19is composed of an oxide such as silicon dioxide.

Second Modification

Next, the configuration of pixels according to a second modification of the present embodiment will be described with reference toFIG. 4.FIG. 4is a diagram illustrating the configuration of each of a plurality of pixels10C according to the present modification.

Components different from those according to the embodiment and the first modification will be described hereinafter.

In an imaging device according to the present modification, the pixels10C each include a second isolation region20that is located around the first isolation region19and that includes a p-type impurity with a concentration higher than in the third diffusion region6.

As described above, the first isolation region19is composed of an oxide such as silicon dioxide. A defect might occur at an interface between the first isolation region19and the second diffusion region3, and dark current might be caused due to the defect at the interface. By coating the first isolation region19with the second isolation region20composed of a high-concentration p-type impurity, therefore, a potential barrier is formed between the third diffusion region6and the second diffusion region3, and the third diffusion region6and the second diffusion region3can be insulated more strongly from each other electrically. As a result, dark current caused between the third diffusion region6and the second diffusion region3can be further reduced.

Third Modification

Next, the configuration of pixels according to a third modification of the present embodiment will be described with reference toFIG. 5.FIG. 5is a diagram illustrating the configuration of each of a plurality of pixels10D according to the present modification.

Components different from those according to the embodiment will be described hereinafter.

In an imaging device according to the present modification, the pixels10D each include a fourth diffusion region (hereinafter referred to as a “connection region13”) that is in contact with the first diffusion region2and the second diffusion region3and that includes an n-type impurity. In the imaging device according to the present modification, the first diffusion region2and the second diffusion region3are securely connected to each other electrically through the connection region13. Charges generated in the first diffusion region2, therefore, directly flow into the connection region13and are accumulated in the charge accumulation region including the second diffusion region3.

Fourth Modification

Next, the configuration of pixels according to a fourth modification of the present embodiment will be described with reference toFIG. 6.FIG. 6is a diagram illustrating the configuration of each of a plurality of pixels10E according to the present modification.

Components different from those according to the embodiment will be described hereinafter.

In each of the pixels10E of an imaging device according to the present modification, the first diffusion region2and the second diffusion region3face each other through the well region11. As described above, the well region11includes a p-type impurity. In this structure in which a p-type impurity region is sandwiched between the first diffusion region2and the second diffusion region3, which are n-type impurity regions, the p-type impurity region functions as a potential barrier. If the amount of charge generated in the first diffusion region2becomes equal to or larger than a certain value, therefore, charges flow into the second diffusion region3from the first diffusion region2.

Although the imaging device according to the present disclosure has been described on the basis of an embodiment and modifications, the present disclosure is not limited to the embodiment and the modifications. The present disclosure also includes modes achieved by modifying the embodiment and the modifications in various ways conceivable by those skilled in the art and other modes achieved by combining together some components in the embodiment and the modifications, insofar as the scope of the present disclosure is not deviated from.

As described above, although the imaging device100A according to the present embodiment includes the inverting amplifiers45(refer toFIG. 1) in the circuit configuration, feedback transistors may be included instead of the inverting amplifiers45.FIG. 7is a diagram illustrating an example in which each of a plurality of pixels10F includes a feedback transistor24. Here, only components different from those of each of the pixels10A illustrated inFIG. 1will be described.

The pixels10F are different from the pixels10A in that the pixels10F each include the feedback transistor24and a second capacitive element61. In the configuration illustrated inFIG. 7, the vertical scanning circuit30(refer toFIG. 1) is also connected to feedback control lines (not illustrated). A gate of the feedback transistor24is connected to the corresponding feedback control line (not illustrated). By applying a certain voltage to the corresponding feedback control line (not illustrated) from the vertical scanning circuit30, a feedback circuit for feeding back an output of a signal detection circuit to the second diffusion region3through the second capacitive element61or the reset transistor23can be formed. The second capacitive element61is a so-called coupling capacitor.

Referring back toFIG. 2, although the area of the second diffusion region3and the area of the n-type impurity region5awhen viewed in the direction perpendicular to the semiconductor substrate1are compared with each other in the present embodiment, distances between contact plugs connected to the second diffusion region3and the n-type impurity region5aand the gate electrode4may be compared with each other. Here, the pixels10A each include the contact plug8aconnected to the second diffusion region3and a contact plug (not illustrated) connected to the n-type impurity region5a. The contact plug (not illustrated) is connected to the feedback line46. In this case, the distance between the contact plug8aof the second diffusion region3and the gate electrode4of the reset transistor23is smaller than the distance between the contact plug (not illustrated) of the n-type impurity region5aand the gate electrode4of the reset transistor23.

As a result, the distance between the contact plug8aof the second diffusion region3and the gate electrode4of the reset transistor23becomes short, thereby reducing an increase in a resistance of the second diffusion region3.

In addition, according to the embodiment and the modifications of the present disclosure, an effect of dark current can be reduced, and an imaging device capable of performing high-quality imaging is provided. The above-described address transistor21, amplifier transistor22, and reset transistor23may each be an n-channel MOS transistor or a p-channel MOS transistor. When each transistor is a p-channel MOS transistor, an impurity of the second conductivity type is a p-type impurity, and an impurity of the first conductivity type is an n-type impurity. Not all these transistors need to be either an n-channel MOS transistor or a p-channel MOS transistor. When each of the transistors in a pixel is an n-channel MOS transistor and electrons are used as signal charges, positions of the source and the drain of each of the transistors may be switched.

Although each of the pixels of the imaging device100A according to the present embodiment includes a photoelectric conversion unit having the same sensitivity, each of the pixels may include two pixels having different sensitivities, instead.

FIG. 8is a diagram illustrating an example of the circuit configuration of a pixel cell10G including two pixels110A and110B having different sensitivities. The pixel cell10G includes a first photoelectric conversion unit120A, a first transfer transistor121, a second photoelectric conversion unit120B, a second transfer transistor123, a charge accumulation unit124, a switch transistor125, a reset transistor126, an amplifier transistor127, a first charge accumulation region128, and a second charge accumulation region129. InFIG. 8, a high-sensitivity pixel110A surrounded by a broken line corresponds to the first photoelectric conversion unit120A, the first charge accumulation region128, and the first transfer transistor121. A low-sensitivity pixel110B corresponds to the second photoelectric conversion unit120B, the second charge accumulation region129, the second transfer transistor123, and the charge accumulation unit124.

The first photoelectric conversion unit120A (hereinafter also referred to as a “first photodiode120A”) is a photodiode formed in a semiconductor substrate and converts light into signal charges.

The first transfer transistor121turns on when a transfer control line TGL is at high level. As a result, the first transfer transistor121transfers signal charges obtained by the first photoelectric conversion unit120A as a result of photoelectric conversion to the first charge accumulation region128.

The second photoelectric conversion unit120B (hereinafter referred to as a “second photodiode120B”) is a photodiode formed in the semiconductor substrate, has a light receiving area smaller than the first photoelectric conversion unit120A, and converts light into signal charges.

The second transfer transistor123turns on when, for example, the transfer control line TGS is at high level. As a result, the second transfer transistor123transfers, to the second charge accumulation region129, signal charges obtained by the second photoelectric conversion unit120B as a result of photoelectric conversion and accumulated in the charge accumulation unit124. In the configuration illustrated inFIG. 8, a second diffusion region that accumulates charges generated by the second photoelectric conversion unit120B is a drain of the second transfer transistor123. The second diffusion region is electrically connected to the second photoelectric conversion unit120B, and charges generated by the second photoelectric conversion unit120B can be directly accumulated in the second diffusion region.

The charge accumulation unit124is a capacitive element that accumulates signal charges generated by the second photoelectric conversion unit120B as a result of photoelectric conversion. The charge accumulation unit124is formed as having the MIM structure and includes two electrode portions. One of the two electrode portions is connected to the power supply voltage PVDD, and the other electrode portion is connected to the drain of the second transfer transistor123. The charge accumulation unit124accumulates signal charges generated by the second photoelectric conversion unit120B as a result of photoelectric conversion. The signal charges accumulated in the charge accumulation unit124are transferred by the second transfer transistor123to the second charge accumulation region129when the transfer control line TGS is at high level. The charge accumulation unit124plays a role of significantly increasing a maximum accumulation capacity (i.e., saturation signal charge) of signal charges generated by the second photoelectric conversion unit120B as a result of photoelectric conversion. The charge accumulation unit124may have the same configuration as the capacitive element60(e.g., refer toFIG. 2).

When a switch control line SW is at high level, for example, the switch transistor125makes the first charge accumulation region128and the second charge accumulation region129electrically conductive to each other.

When a reset control line RS is at high level, for example, the reset transistor126resets the second charge accumulation region129to high level.

The amplifier transistor127forms a source follower circuit in combination with a constant current source in a constant current source circuit, converts the potential of the first charge accumulation region128into a voltage, and outputs the voltage to a vertical signal line VL.

The first charge accumulation region128includes a floating diffusion layer formed in the semiconductor substrate and holds signal charges transferred from the first transfer transistor121.

The second charge accumulation region129includes a floating diffusion layer formed in the semiconductor substrate and holds signal charges transferred from the second transfer transistor123.

As described above, by adding the charge accumulation unit124to the second photoelectric conversion unit120B, whose light receiving area is smaller than that of the first photoelectric conversion unit120A, saturation charge can be increased although the sensitivity of the second photoelectric conversion unit120B is lower than that of the first photoelectric conversion unit120A. The low-sensitivity pixel110B, therefore, can achieve a wide dynamic range. As a result, the high-sensitivity pixel110A mainly captures low-illuminance images, and the low-sensitivity pixel110B captures high-illuminance images, thereby obtaining images of a wide dynamic range. In addition, although the above-described kTC noise is caused in the low-sensitivity pixel110B of the pixel cell10G, an effect of the kTC noise is small since the low-sensitivity pixel110B mainly captures high-illuminance images and a signal component is large compared to the kTC noise.

Next, the operation of the example of the circuit of the pixel cell10G illustrated inFIG. 8will be described specifically.

As illustrated inFIG. 8, in the pixel cell10G in this example of the circuit, the high-sensitivity pixel110A and the low-sensitivity pixel110B share the switch transistor125, the reset transistor126, and the amplifier transistor127. That is, the high-sensitivity pixel110A includes elements for performing photoelectric conversion, namely, for example, the first photoelectric conversion unit120A and the first transfer transistor121. The low-sensitivity pixel110B includes the second photodiode120B, the second transfer transistor123, and the charge accumulation unit124. In addition, the pixel cell10G includes the switch transistor125, the reset transistor126, and the amplifier transistor127shared between the high-sensitivity pixel110A and the low-sensitivity pixel110B. As the transistors121,123,125,126, and127(hereinafter referred to as the “transistors121to127”), for example, n-channel MOS transistors may be used. The n-channel MOS transistors turn on when gate potential is at “high” level and turn off when the gate potential is at “low” level. P-channel MOS transistors, on the other hand, are assumed to turn on when the gate potential is at “low” level and turn off when the gate potential is at “high” level. In the example illustrated inFIG. 8, the transistors121to127are n-channel MOS transistors.

The first transfer transistor121is connected between a cathode electrode of the first photodiode120A and the first charge accumulation region128. The transfer control line TGL is connected to a gate electrode of the first transfer transistor121. When “high” level is supplied to the gate electrode of the first transfer transistor121from the transfer control line TGL through transfer pulses, the first transfer transistor121turns on, and the first photodiode120A performs photoelectric conversion. As a result, signal charges accumulated in the first photodiode120A are transferred to the first charge accumulation region128. In this example, the signal charges are electrons.

The second transfer transistor123is connected between the electrode portion of the charge accumulation unit124connected to the semiconductor substrate and the second charge accumulation region129. The transfer control line TGS is connected to a gate electrode of the second transfer transistor123. When “high” level is supplied to the gate electrode of the second transfer transistor123from the transfer control line TGS using transfer pulses, the second transfer transistor123turns on, and the second photodiode120B performs photoelectric conversion. As a result, signal charges accumulated in the second photodiode120B and signal charges accumulated between the electrode portion of the charge accumulation unit124and the semiconductor substrate are transferred to the second charge accumulation region129.

The reset control line RS is connected to a gate electrode of the reset transistor126. The power supply voltage VDDC is applied to a drain electrode through a power supply wire, and the second charge accumulation region129is connected to a source electrode. In addition, with regard to the switch transistor125, the switch control line SW is connected to a gate electrode, the second charge accumulation region129is connected to a drain electrode, and the first charge accumulation region128is connected to a source electrode.

First, reading control performed by the high-sensitivity pixel110A will be described.

“High” level is supplied to the gate electrode of the reset transistor126through the reset control line RS using reset pulses φRS before the first photodiode120A transfers signal charges to the first charge accumulation region128. In addition, “high” level is supplied to the gate electrode of the switch transistor125through the switch control line SW using switch pulses. As a result, the reset transistor126and the switch transistor125turn on. Consequently, potentials of the first charge accumulation region128and the second charge accumulation region129are reset to the power supply voltage VDDC. After the potentials of the first charge accumulation region128and the second charge accumulation region129are reset to the power supply voltage VDDC, “high” level is supplied to the gate electrode of the reset transistor126using the reset pulses and “low” level is supplied to the gate electrode of the switch transistor125using switch pulses. As a result, a reset operation for the first charge accumulation region128is completed.

A gate electrode of the amplifier transistor127is connected to the first charge accumulation region128, the power supply voltage VDDC is applied to a drain electrode of the amplifier transistor127through a power supply wire, and the vertical signal line VL is connected to a source electrode of the amplifier transistor127. The amplifier transistor127outputs a potential of the first charge accumulation region128reset by the reset transistor126and the switch transistor125, to the vertical signal line VL as reset level. The amplifier transistor127outputs a potential of the first charge accumulation region128after the first transfer transistor121transfers signal charges, to the vertical signal line VL as signal level.

Next, reading control performed by the low-sensitivity pixel110B will be described. The reset transistor126and the switch transistor125are turned on to reset the potentials of the first charge accumulation region128and the second charge accumulation region129to the power supply voltage VDDC before the charge accumulation unit124transfers signal charges to the second charge accumulation region129. After the potentials of the first charge accumulation region128and the second charge accumulation region129are reset to the power supply voltage VDDC, “low” level is supplied to the gate electrode of the reset transistor using the reset pulses φRS. In addition, “high” level is supplied to the gate electrode of the switch transistor using switch pulses. As a result, the reset operation is completed with the first charge accumulation region128and the second charge accumulation region129electrically connected to each other.

The amplifier transistor127outputs, to the vertical signal line VL as reset level, the potentials of the first charge accumulation region128and the second charge accumulation region129reset by the reset transistor126and the switch transistor125. Furthermore, the amplifier transistor127outputs, to the vertical signal line VL as signal level, the potentials of the first charge accumulation region128and the second charge accumulation region129after the second transfer transistor123transfers signal charges.

Here, the first charge accumulation region128and the second charge accumulation region129transmit a voltage according to the amount of signal charge to the amplifier transistor127. An equation for converting the amount of signal charge into voltage is ΔV=Q/C, and conversion efficiency η is represented by η=1/C. The conversion efficiency η is determined by capacitances C of the first charge accumulation region128and the second charge accumulation region129. When signal charges of the low-sensitivity pixel110B are read, the first charge accumulation region128and the second charge accumulation region129are connected to the gate electrode of the amplifier transistor127. When signal voltage of the high-sensitivity pixel110A is read, on the other hand, only the first charge accumulation region128is connected to the gate electrode of the amplifier transistor127. The conversion efficiency η of the low-sensitivity pixel110B, therefore, is lower than the conversion efficiency η of the high-sensitivity pixel110A.

Here, the amount of signal charge can be more efficiently converted into voltage and a voltage of signal amplitude becomes higher as the conversion efficiency η becomes higher. As a result, a ratio S/N of a pixel signal S to a noise component N caused by a constant current source circuit and a reading circuit connected to the vertical signal line VL improves, and a high-quality image can be obtained.

The high-sensitivity pixel110A obtains image data regarding a subject in a low-illuminance environment, and the low-sensitivity pixel110B obtains an image data of a subject in a high-illuminance environment. By combining together image data obtained from two pixels having different sensitivities, image data of a wider dynamic range than that of image data obtained from pixels having the same sensitivity can be obtained.

The imaging device is required to generate high-quality images so that images can be obtained in various environments. In order to obtain high-quality images in a low-illuminance environment, especially with an illuminance of less than 1 lux, the high-sensitivity pixel110A is required to achieve higher conversion efficiency η. In order to achieve higher conversion efficiency, the capacitance C of the first charge accumulation region128needs to be smaller.

In order to obtain high-quality images in a high-illuminance environment, especially in direct sunlight, on the other hand, the charge accumulation unit124of the low-sensitivity pixel110B needs to accumulate a larger amount of signal charge. For this purpose, lower conversion efficiency η is required. In order to achieve lower conversion efficiency, the capacitance C of the second charge accumulation region129needs to be higher.

In the configuration illustrated inFIG. 8, the switch transistor125is provided between the first charge accumulation region128and the second charge accumulation region129, and the amplifier transistor127is connected to the first charge accumulation region128. When signal charges of the high-sensitivity pixel110A are read, the switch transistor125is turned off. As a result, the gate electrode of the amplifier transistor127is connected only to the first charge accumulation region128, and higher conversion efficiency η is achieved. In addition, when signal charges of the low-sensitivity pixel110B are read, the switch transistor125is turned on. As a result, the first charge accumulation region128and the second charge accumulation region129are connected to the gate electrode of the amplifier transistor127, and lower conversion efficiency η is achieved.

Here, in order to achieve desired conversion efficiency η for the low-sensitivity pixel110B, a capacitor may be provided for the second charge accumulation region129. At this time, because the high-sensitivity pixel110A reads signal charges with the switch transistor125turned off, the conversion efficiency η of the high-sensitivity pixel110A is not affected, and high image quality can be maintained.

When the switch transistor125is turned on in the reading operation performed by the high-sensitivity pixel110A, it is desirable to turn off the reset transistor126as in the reading operation performed by the low-sensitivity pixel110B. As a result, signal charges can be read with the conversion efficiency η of the first charge accumulation region128and the second charge accumulation region129reduced. When an image of a subject is captured in a high-illuminance environment, the amount of signal charge accumulated in the first photodiode120A of the high-sensitivity pixel110A is larger than the amount of signal charge when an image of a subject is captured in a low-illuminance environment. The above method, therefore, is effective as means for preventing the voltage ΔV of the amount of signal charge from exceeding a dynamic range of the vertical signal line VL.

In addition, although one high-sensitivity pixel110A and one low-sensitivity pixel110B share the switch transistor125, the reset transistor126, and the amplifier transistor127in the pixel cell10G, two high-sensitivity pixels110A and two low-sensitivity pixels110B may share the switch transistor125, the reset transistor126, and the amplifier transistor127, instead.

In addition, a selection transistor for selecting a row corresponding to a reading row of a pixel array may be connected between the source of the amplifier transistor127and the vertical signal line VL.

Although a mode in the above embodiment and modifications in which light enters the photoelectric conversion unit12from a side of the second wire72to the fourth wire74(hereinafter referred to as “wiring”), that is, although an imaging device of a front surface illumination type, has been described, an imaging device of a back illumination type illustrated inFIG. 9may be used, instead.FIG. 9is a diagram illustrating the configuration of each of a plurality of pixels10H of an imaging device according to another embodiment. Differences from the pixels according to the above embodiment and modifications will be described through comparison.

In an imaging device of the front illumination type, for example, light enters the photoelectric conversion unit12from the side of the wiring as in the cases of the pixels10A to10E illustrated inFIGS. 2 to 6, respectively. In an imaging device of the back illumination type, on the other hand, light enters the photoelectric conversion unit12from a side of the semiconductor substrate1, for example, as illustrated inFIG. 9. In an imaging device of the front illumination type, the photoelectric conversion unit12and the wiring need to be arranged such that light incident on the photoelectric conversion unit12is not blocked by the wiring. It is therefore difficult to increase the light receiving area of the photoelectric conversion unit12to a certain value or more. In addition, space in which the wiring is arranged is also limited. In the imaging device of the back illumination type illustrated inFIG. 9, on the other hand, the wiring is provided on a side opposite a side on which light enters the photoelectric conversion unit12, and the wiring does not block light incident on the photoelectric conversion unit12. As a result, the light receiving area of the photoelectric conversion unit12can be increased. In addition, the wiring can be arranged arbitrarily. InFIG. 9, for example, the second wire72, the third wire73, and the fourth wire74are arranged above the photoelectric conversion unit12. In the imaging device illustrated inFIG. 9, the n-type region80may be formed thinly. As a result, light easily enters the photoelectric conversion unit12.

According to the present disclosure, since a dynamic range can be increased while reducing dark current, an imaging device capable of performing high-quality imaging can be provided. The imaging device in the present disclosure, for example, is effective as an image sensor, a digital camera, or the like. The imaging device in the present disclosure can be used for a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, or the like.