METHODS FOR WIRE BONDING AND TESTING AND FLASH MEMORIES FABRICATED BY THE SAME

The invention introduces a method for wire bonding and testing, performed by wire-bonding equipment, including at least the following steps: providing a substrate and dies, where the substrate has exposed fingers and each die has exposed pads; controlling a motor to hold the substrate by a metal frame, where all the exposed fingers are floating from the metal frame to avoid ESD (electrostatic discharge) fail; and performing a wire bonding to make interconnections between the pads on the dies and the fingers on the substrate to fabricate a semi-finished flash-memory product.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No. 106122504, filed on Jul. 5, 2017, the entirety of which is incorporated by reference herein.

BACKGROUND

Technical Field

The present invention relates to flash memory, and in particular to methods for wire bonding and testing and flash memories fabricated by the same.

Description of the Related Art

Flash memory devices typically include NOR flash devices and NAND flash devices. NOR flash devices are random access—a host accessing a NOR flash device can provide the device any address on its address pins and immediately retrieve data stored in that address on the device's data pins. NAND flash devices, on the other hand, are not random access but serial access. It is not possible for NOR to access any random address in the way described above. Instead, the host has to write into the device a sequence of bytes which identifies both the type of command requested (e.g. read, write, erase, etc.) and the address to be used for that command. The address identifies a page (the smallest chunk of flash memory that can be written in a single operation) or a block (the smallest chunk of flash memory that can be erased in a single operation), and not a single byte or word. In reality, the NAND flash device always reads from the memory cells and writes to the memory cells complete pages. After a page of data is read from the array into a buffer inside the device, the host can access the data bytes or words one by one by serially clocking them out using a strobe signal.

Wire bonding is the method of making interconnections between ICs (integrated circuits) and a PCB (printed circuit board) during semiconductor device fabrication. To improve the performance, a flash memory device typically includes dies holding a controller and storage sub-units, and wires being produced to connect dies. However, a bad wire bonding and testing method may introduce ESD (Electrostatic Discharge) fail to damage one or more of the controller and storage sub-units. Accordingly, what is needed are methods for wire bonding and testing and flash memories fabricated by the methods to address the aforementioned problems.

BRIEF SUMMARY

An embodiment of the invention introduces a method for wire bonding and testing, performed by wire-bonding equipment, including at least the following steps: providing a substrate and dies, where the substrate has exposed fingers and each die has exposed pads; controlling a motor to hold the substrate by a metal frame, where all the exposed fingers are floating from the metal frame to avoid ESD (electrostatic discharge) fail; and performing a wire bonding to make interconnections between the pads on the dies and the fingers on the substrate to fabricate a semi-finished flash-memory product.

An embodiment of the invention introduces a flash memory including at least a substrate, a first die disposed on the substrate, and second dies disposed on the substrate. The substrate has exposed fingers, in which no metal line is formed to connect one of the exposed fingers to an edge of the substrate to avoid ESD (electrostatic discharge) fail when a wire bonding is performed. The first die comprises IC (Integrated Circuit) of a controller, and exposed pads. Each second die comprises IC of a storage sub-unit, and exposed pads.

DETAILED DESCRIPTION

FIG. 1is the system architecture of a flash memory according to an embodiment of the invention. The system architecture10of the flash memory contains a processing unit110being configured to write data into a designated address of a storage unit180, and read data from a designated address thereof. Specifically, the processing unit110writes data into a designated address of the storage unit180through an access interface170and reads data from a designated address thereof through the same interface170. The system architecture10uses several electrical signals for coordinating commands and data transfer between the processing unit110and the storage unit180, including data lines, a clock signal and control lines. The data lines are employed to transfer commands, addresses and data to be written and read. The control lines are utilized to issue control signals, such as CE (Chip Enable), ALE (Address Latch Enable), CLE (Command Latch Enable), WE (Write Enable), etc. The access interface170may communicate with the storage unit180using a SDR (Single Data Rate) protocol or a DDR (Double Data Rate) protocol, such as ONFI (open NAND flash interface), DDR toggle, or others. The processing unit110may communicate with a host160through an access interface150using a standard protocol, such as USB (Universal Serial Bus), ATA (Advanced Technology Attachment), SATA (Serial ATA), PCI-E (Peripheral Component Interconnect Express), NVMe (Non-Volatile Memory Express), Open-Channel SSD (Solid State Disk) or others.

The storage unit180may contain multiple storage sub-units and one or more storage sub-units may be practiced in a single die and use an access sub-interface to communicate with the processing unit110.FIG. 2is a schematic diagram illustrating interfaces to storage units of a flash memory according to an embodiment of the invention. The flash memory10may contain j+1 access sub-interfaces170_0to170_j, where the access sub-interfaces may be referred to as channels, and each access sub-interface connects to i+1 storage sub-units. That is, i+1 storage sub-units may share the same access sub-interface. For example, assume that the flash memory10contains 4 channels (j=3) and each channel connects to 4 storage sub-units (i=3): The flash memory10has 16 storage sub-units180_0_0to180_j_iin total. The control unit110may direct one of the access sub-interfaces170_0to170_jto read data from the designated storage sub-unit. Each storage sub-unit has an independent CE control signal. That is, it is required to enable a corresponding CE control signal when attempting to perform data read from a designated storage sub-unit via an associated access sub-interface. It is apparent that any number of channels may be provided in the flash memory10, and each channel may be associated with any number of storage sub-units, and the invention should not be limited thereto.FIG. 3is a schematic diagram depicting connections between one access sub-interface and multiple storage sub-units according to an embodiment of the invention. The processing unit110, through the access sub-interface170_0, may use independent CE control signals320_0_0to320_0_ito select one of the connected storage sub-units180_0_0and180_0_i, and then read data from the designated location of the selected storage sub-unit via the shared data line310_0. The system architecture10of the flash memory may include a data buffer120for temporarily storing data received from the host160and to be programmed into the storage unit180via the access interface170, and data received from the storage unit180and to be clocked out to the host160via the access interface150. The system architecture10of the flash memory may include a DRAM (Dynamic Random Access Memory) for storing data, such as variables, data tables, etc., required during data access.

FIG. 4is the sectional diagram of a flash memory according to an embodiment of the invention. A flash memory may contain a substrate410and multiple dies420and430ato430d.The substrate may contain multiple layers, the upper surface of the top layer has multiple exposed fingers450and the lower surface of the bottom layer has multiple exposed solder balls470. The die420contains ICs (Integrated Circuits) of a controller, in which at least the processing unit110, the data buffer120, the DRAM130, and the access interfaces150and170are implemented. Multiple pads are exposed and disposed on the die420and each pad is connected to one of the fingers450of the substrate410by a wire. The dies430ato430dcontain ICs of storage sub-units180_0_0to180_0_3, respectively, and are stacked on the substrate410. The dies430ato430dmay be referred to as the first- to forth-layer die from the bottom to the top. Multiple exposed pads431aare exposed and disposed on the die430a, multiple pads431bare exposed and disposed on the die430b,multiple pads431care exposed and disposed on the die430c,and multiple pads431dare exposed and disposed on the die430d.Wire-bonding equipment connects each pad to one of the fingers450by a wire.

FIG. 5is a flowchart illustrating a method for wire bonding and testing according to an embodiment of the invention. The method is performed by wire-bonding equipment. First, a substrate and dies to be disposed on the substrate are provided (step S510), one or more motors are controlled to hold the substrate by a metal frame (step S520), pads of the dies are wired to interconnect fingers of the substrate so as to manufacture a semi-finished flash-memory product (step S530), and a open/short test is performed to the semi-finished flash-memory product (step S550). Next, the wire-boding equipment determines whether the semi-finished flash-memory product that is undergone the wire bonding completely has passed the open/short test (step S570). If so (the “Yes” path of step S570), then the wire bonding is successful (step S591). Otherwise (the “No” path of step S580), the wire bonding is failed (step S593).

FIG. 6Ais a schematic diagram of a substrate according to some implementations. In some implementations, at least one metal line610presented on a substrate410′ being provided in step5510is connected between a finger450′ and an edge of the substrate410′. The metal line610may be formed by an electroplating process or a non-plating process.FIG. 7is a schematic diagram illustrating the connecting of a semi-finished flash-memory product to the wire-bonding equipment according to some implementations. During the wire bonding, a metal frame is used to clamp the edges of the substrate410′ and a sensor711of the wire-bonding equipment710is connected to the metal frame730. When the metal frame clamps the edges of the substrate410′, the metal frame730is the ground of components of the dies420and430a-430d,thereby enabling the wire-bonding equipment710, when bonding each wire in step S530, receives an electrical signal through the sensor411and performs a non-sticking test. Therefore, the wire-bonding equipment710knows whether electrical connections between the die and the substrate410′, or any of the dies430ato430dand the substrate410′ have satisfied the requirements. Charges generated during the wire bonding are flowed in conductive paths. However, after over hundreds times of the wire bonding, some charges may be flowed and accumulated in some components of the dies. ESD (electrostatic discharge) fail happens to damage the controller of the die420or the storage sub-units of one of the dies430ato430d.

To avoid the above ESD fail, the embodiments of the invention provide a new substrate.FIG. 6Bis a schematic diagram of a substrate according to an embodiment of the invention. Refer toFIG. 7. The substrate held by the metal frame730is replaced with a substrate410″ as shown inFIG. 6Band no metal line is formed on the substrate410″ to connect between the fingers450″ and the edges of the substrate410″. When the metal frame730clamps the edges of the substrate410″ in step S520, all fingers450″ are floating from the metal frame730, so that the metal frame730does not become a ground of the ICs of the controller and the storage sub-units. When all fingers450″ are floating from the metal frame730, there is no conductive path and charges generated during the wire bonding cannot move, so that the charges are not accumulated in a specific component of a die to induce ESD fail. To conform to the provided substrate410″, the wire-bonding equipment710, when bonding each wire in step S530, does not perform a non-sticking test. After the wire bonding, the open/short test performed in step S570verifies whether all pins corresponding to the solder balls470of the flash memory are correctly connected to the internal circuits of the flash memory and whether a short circuit is formed between pins or between one pin and the power/ground pin. The charges generated in the wire bonding flow to the outside of the semi-product of the flash memory along multiple conductive paths through the solder balls470when the open/short test is performed in step S550. Although the embodiment describes one substrate inFIG. 6, those skilled in the art may realize that one metal frame holds multiple uncut substrates to perform the wire bonding for multiple flash memories and the invention should not be limited thereto.

Although the embodiment has been described as having specific elements inFIGS. 1 to 4, it should be noted that additional elements may be included to achieve better performance without departing from the spirit of the invention. While the process flow described inFIG. 5includes a number of operations that appear to occur in a specific order, it should be apparent that these processes can include more or fewer operations, which can be executed serially or in parallel (e.g., using parallel processors or a multi-threading environment).