Widened conductive line structures and staircase structures for semiconductor devices

Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and more particularly, to widened conductive line structures and staircase structures for semiconductor devices.

BACKGROUND

Memory is often implemented in electronic systems, such as computers, cell phones, hand-held devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM). Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, nitride read only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random-access memory), cross-point memory, ferroelectric random-access memory (FeRAM), or the like.

As design rules shrink, less semiconductor space is available to fabricate memory, including DRAM arrays. A respective memory cell for DRAM may include an access device, (e.g., a transistor), having a first and a second source/drain regions separated by a channel region. A gate may oppose the channel region and be separated therefrom by a gate dielectric. An access line, such as a world line, is electrically connected to the gate of the DRAM cell. A DRAM cell can include a storage node, such as a capacitor cell, coupled by the access device to a conductive line. The access device can be activated (e.g., to select the cell) by an access line coupled to an access transistor. The capacitor can store a charge corresponding to a data value of a respective cell (e.g., a logic “1” or “0”).

DETAILED DESCRIPTION

Embodiments of the present disclosure describe widened conductive line structures and staircase structures for semiconductor devices. Semiconductor memory devices may include vertical stacks, each vertical stack including layers of semiconductor and dielectric materials. Conductive lines may be formed within one or more dielectric material layers.

In some instances, it may be useful to form one or more conductive line contacts to connect conductive lines of one tier of a vertical stack to sense amplifiers or other circuitry (e.g., word line drivers). However, this requires a great deal of precision, time, and resources, since the conductive line contacts must make contact with the conductive lines that have relatively small widths, leaving a very little margin of error.

The embodiments of the present disclosure include methods and apparatuses for forming wider conductive lines creating layers of conductive material to serve as interconnections between a conductive line and a conductive line contact. Embodiments of the present disclosure provide a greater area on which a conductive line contact may be formed. Therefore, some advantages of the embodiments described herein include reduced precision, time, and resources required to form conductive line contacts, among other advantages.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, reference numeral107may reference element “07” inFIG.1, and a similar element may be referenced as207inFIG.2. Multiple analogous elements within one figure may be referenced with a reference numeral followed by a hyphen and another numeral or a letter. For example,607-1may reference element607-1inFIGS.3and607-2may reference element607-2, which may be analogous to element607-1. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements607-1and607-2or other analogous elements may be generally referenced as607. The use of a letter, such as607-N, is used to illustrate that in an embodiment shown in a particular figure, any number of items607may be utilized.

FIG.1is a block diagram of an apparatus in accordance with a number of embodiments of the present disclosure.FIG.1illustrates a circuit diagram showing a cell array of a three dimensional (3D) semiconductor memory device according to embodiments of the present disclosure.FIG.1illustrates that a cell array may have a plurality of sub cell arrays101-1,101-2, . . . ,101-N. The sub cell arrays101-1,101-2, . . . ,101-N may be arranged along a second direction (D2)105. Each of the sub cell arrays (e.g., sub cell array101-2) may include a plurality of access lines103-1,103-2, . . . ,103-Q (which also may be referred to as word lines). Also, each of the sub cell arrays (e.g., sub cell array101-2) may include a plurality of digit lines107-1,107-2, . . . ,107-Q (which also may be referred to as bitlines, data lines, or sense lines). InFIG.1, the digit lines107-1,107-2, . . . ,107-Q are illustrated extending in a first direction (D1)109and the access lines103-1,103-2, . . . ,103-Q are illustrated extending in a third direction (D3)111.

The first direction (D1)109and the second direction (D2)105may be considered in a horizontal (“X-Y”) plane. The third direction (D3)111may be considered in a vertical (“Z”) direction (e.g., transverse to the X-Y plane). Hence, according to embodiments described herein, the access lines103-1,103-2, . . . ,103-Q are extending in a vertical direction (e.g., third direction (D3)111).

A memory cell (e.g.,110) may include an access device (e.g., access transistor) and a storage node located at an intersection of each access line103-1,103-2, . . . ,103-Q and each digit line107-1,107-2, . . . ,107-Q. Memory cells may be written to, or read from, using the access lines103-1,103-2, . . . ,103-Q and digit lines107-1,107-2, . . . ,107-Q. The digit lines107-1,107-2, . . . ,107-Q may conductively interconnect memory cells along horizontal columns of each sub cell array101-,101-2, . . . ,101-N, and the access lines103-1,103-2, . . . ,103-Q may conductively interconnect memory cells along vertical rows of each sub cell array101-1,101-2, . . . ,101-N. One memory cell, e.g.,110, may be located between one access line (e.g.,103-2) and one digit line (e.g.,107-2). Each memory cell may be uniquely addressed through a combination of an access line103-1,103-2, . . . ,103-Q and a digit line107-1,107-2, . . . ,107-Q.

The digit lines107-1,107-2, . . . ,107-Q may be or include conducting patterns (e.g., metal lines) disposed on and spaced apart from a substrate. The digit lines107-1,107-2, . . . ,107-Q may extend in a first direction (D1)109. The digit lines107-1,107-2, . . . ,107-Q in one sub cell array (e.g.,101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3)111).

The access lines103-1,103-2, . . . ,103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction with respect to the substrate (e.g., in a third direction (D3)111). The access lines in one sub cell array (e.g.,101-2) may be spaced apart from each other in the first direction (D1)109.

A gate of a memory cell (e.g., memory cell110) may be connected to an access line (e.g.,103-2) and a first conductive node (e.g., first source/drain region) of an access device (e.g., transistor) of the memory cell110may be connected to a digit line (e.g.,107-2). Each of the memory cells (e.g., memory cell110) may be connected to a storage node (e.g., capacitor). A second conductive node (e.g., second source/drain region) of the access device (e.g., transistor) of the memory cell110may be connected to the storage node (e.g., capacitor).

Storage nodes, such as capacitors, can be formed from ferroelectric and/or dielectric materials such as zirconium oxide (ZrO2), hafnium oxide (HfO2) oxide, lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), a combination of these with or without dopants, or other suitable materials.

While first and second source/drain region reference are used herein to denote two separate and distinct source/drain regions, it is not intended that the source/drain region referred to as the “first” and/or “second” source/drain regions have some unique meaning. It is intended only that one of the source/drain regions is connected to a digit line (e.g.,107-2) and the other may be connected to a storage node.

FIG.2illustrates a perspective view showing a 3D semiconductor memory device (e.g., a portion of a sub cell array101-2shown inFIG.1as a vertically oriented stack of memory cells in an array) according to some embodiments of the present disclosure.FIG.3illustrates a perspective view showing unit cell (e.g., memory cell110shown inFIG.1) of the 3D semiconductor memory device shown inFIG.2.

As shown inFIG.2, a substrate200may have formed thereon one of the plurality of sub cell arrays (e.g.,101-2) described in connection withFIG.1. For example, the substrate200may be or include a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. Embodiments, however, are not limited to these examples.

As shown in the example embodiment ofFIG.2, the substrate200may have fabricated thereon a vertically oriented stack of memory cells (e.g., memory cell110inFIG.1) extending in a vertical direction (e.g., third direction (D3)111). According to some embodiments the vertically oriented stack of memory cells may be fabricated such that each memory cell (e.g., memory cell110inFIG.1) is formed on plurality of vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). The repeating, vertical levels, L1, L2, and L3, may be arranged (e.g., “stacked”) a vertical direction (e.g., third direction (D3)111shown inFIG.1) and may be separated from the substrate200by an insulator material220. Each of the repeating, vertical levels, L1, L2, and L3may include a plurality of discrete components (e.g., regions) to the laterally oriented access devices230(e.g., transistors) and storage nodes (e.g., capacitors) including access line103-1,103-2, . . . ,103-Q connections and digit line107-1,107-2, . . . ,107-Q connections. The plurality of discrete components to the laterally oriented access devices230(e.g., transistors) may be formed in a plurality of iterations of vertically, repeating layers within each level and may extend horizontally in the second direction (D2)205, analogous to second direction (D2)105shown inFIG.1.

The plurality of discrete components to the laterally oriented access devices230(e.g., transistors) may include a first source/drain region221and a second source/drain region223separated by a channel region225, extending laterally in the second direction (D2)205, and formed in a body of the access devices. In some embodiments, the channel region225may include silicon, germanium, silicon-germanium, and/or indium gallium zinc oxide (IGZO). In some embodiments, the first and the second source/drain regions,221and223, can include an n-type dopant region formed in a p-type doped body to the access device to form an n-type conductivity transistor. In some embodiments, the first and the second source/drain regions,221and223, may include a p-type dopant formed within an n-type doped body to the access device to form a p-type conductivity transistor. By way of example, and not by way of limitation, the n-type dopant may include phosphorous (P) atoms and the p-type dopant may include atoms of boron (B) formed in an oppositely doped body region of polysilicon semiconductor material. Embodiments, however, are not limited to these examples.

The storage node227(e.g., capacitor) may be connected to one respective end of the access device. As shown inFIG.2, the storage node227(e.g., capacitor) may be connected to the second source/drain region223of the access device. The storage node may be or include memory elements capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and/or a variable resistance body which includes a phase change material, etc. Embodiments, however, are not limited to these examples. In some embodiments, the storage node associated with each access device of a unit cell (e.g., memory cell110inFIG.1) may similarly extend in the second direction (D2)205, analogous to second direction (D2)105shown inFIG.1.

As shown inFIG.2a plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q extend in the first direction (D1)209, analogous to the first direction (D1)109inFIG.1. The plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q may be analogous to the digit lines107-1,107-2, . . . ,107-Q shown inFIG.1. The plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q may be arranged (e.g., “stacked”) along the third direction (D3)211. The plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q may include a conductive material. For example, the conductive material may include one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.) a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and/or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) Embodiments, however, are not limited to these examples.

Among each of the vertical levels, (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g., memory cell110inFIG.1) may be spaced apart from one another horizontally in the first direction (D1)209. However, as described in more detail below in connection withFIG.4A, et seq., the plurality of discrete components to the laterally oriented access devices230(e.g., first source/drain region221and second source/drain region223separated by a channel region225), extending laterally in the second direction (D2)205, and the plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q, extending laterally in the first direction (D1)209, may be formed within different vertical layers within each level. For example, the plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q, extending in the first direction (D1)209, may be disposed on, and in electrical contact with, top surfaces of first source/drain regions221and orthogonal to laterally oriented access devices230(e.g., transistors) extending laterally in the second direction (D2)205. In some embodiments, the plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q, extending in the first direction (D1)209are formed in a higher vertical layer, farther from the substrate200, within a level (e.g., within level (L1)) than a layer in which the discrete components (e.g., first source/drain region221and second source/drain region223separated by a channel region225) of the laterally oriented access device are formed. In some embodiments, the plurality of horizontally oriented digit lines207-1,207-2, . . . ,207-Q, extending in the first direction (D1)209, may be connected to the top surfaces of the first source/drain regions221directly and/or through additional contacts including metal silicides.

As shown in the example embodiment ofFIG.2, the access lines,203-1,203-2, . . . ,203-Q, extend in a vertical direction with respect to the substrate200(e.g., in a third direction (D3)211). Further, as shown inFIG.2, the access lines,203-1,203-2, . . . ,203-Q, in one sub cell array (e.g., sub cell array101-2inFIG.1) may be spaced apart from each other in the first direction (D1)209. The access lines,203-1,203-2, . . . ,203-Q, may be provided, extending vertically relative to the substrate200in the third direction (D3)211between a pair of the laterally oriented access devices230(e.g., transistors) extending laterally in the second direction (D2)205, but adjacent to each other on a level (e.g., first level (L1)) in the first direction (D1)209. Each of the access lines,203-1,203-2, . . . ,203-Q, may vertically extend, in the third direction (D3), on sidewalls of respective ones of the plurality of laterally oriented access devices230(e.g., transistors) that are vertically stacked.

For example, and as shown in more detail inFIG.3, a first one of the vertically extending access lines (e.g.,203-1) may be adjacent a sidewall of a channel region225to a first one of the laterally oriented access devices230(e.g., transistors) in the first level (L1)213-1, a sidewall of a channel region225of a first one of the laterally oriented access devices230(e.g., transistors) in the second level (L2)213-2, and a sidewall of a channel region225a first one of the laterally oriented access devices230(e.g., transistors) in the third level (L3)213-P, etc. Similarly, a second one of the vertically extending access lines (e.g.,203-2) may be adjacent a sidewall to a channel region225of a second one of the laterally oriented access devices230(e.g., transistors) in the first level (L1)213-1, spaced apart from the first one of laterally oriented access devices230(e.g., transistors) in the first level (L1)213-1in the first direction (D1)209. And the second one of the vertically extending access lines (e.g.,203-2) may be adjacent a sidewall of a channel region225of a second one of the laterally oriented access devices230(e.g., transistors) in the second level (L2)213-2, and a sidewall of a channel region225of a second one of the laterally oriented access devices230(e.g., transistors) in the third level (L3)213-P, etc. Embodiments are not limited to a particular number of levels.

The vertically extending access lines,203-1,203-2, . . . ,203-Q, may include a conductive material, such as, for example, one of a doped semiconductor material, a conductive metal nitride, metal, and/or a metal-semiconductor compound. The access lines,203-1,203-2, . . . ,203-Q, may correspond to word lines (WL) described in connection withFIG.1.

As shown in the example embodiment ofFIG.2, a conductive body contact295may be formed extending in the first direction (D1)209along an end surface of the laterally oriented access devices230(e.g., transistors) in each level (L1)213-1, (L2)213-2, and (L3)213-P above the substrate200. The body contact295may be connected to a body, as shown by336inFIG.3, (e.g., body region) of the laterally oriented access devices230(e.g., transistors) in each memory cell (e.g., memory cell110inFIG.1). The body contact295may include a conductive material such as, for example, one of a doped semiconductor material, a conductive metal nitride, metal, and/or a metal-semiconductor compound.

Although not shown inFIG.2, an insulating material may fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may include one or more of a silicon oxide material, a silicon nitride material, and/or a silicon oxynitride material, etc. Embodiments, however, are not limited to these examples.

FIG.3illustrates in more detail a unit cell (e.g., memory cell110inFIG.1) of the vertically stacked array of memory cells (e.g., within a sub cell array101-2inFIG.1) according to some embodiments of the present disclosure. As shown inFIG.3, the first and the second source/drain regions,321and323, may be impurity doped regions to the laterally oriented access devices330(e.g., transistors). The first and the second source/drain regions,321and323, may be analogous to the first and the second source/drain regions221and223shown inFIG.2. The first and the second source/drain regions may be separated by a channel325formed in a body of semiconductor material (e.g., body region326) of the laterally oriented access devices330(e.g., transistors). The first and the second source/drain regions,321and323, may be formed from an n-type or p-type dopant doped in the body region326. Embodiments are not so limited.

For example, for an n-type conductivity transistor construction, the body region326of the laterally oriented access devices330(e.g., transistors) may be formed of a low doped (p−) p-type semiconductor material. In some embodiments, the body region326and the channel325separating the first and the second source/drain regions,321and323, may include a low doped, p-type (e.g., low dopant concentration (p−)) polysilicon material consisting of boron (B) atoms as an impurity dopant to the polycrystalline silicon. The first and the second source/drain regions,321and323, may also comprise a metal, and/or metal composite materials containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and/or at least one of indium oxide (In2O3), or indium tin oxide (In2-xSnxO3), formed using an atomic layer deposition process, etc. Embodiments, however, are not limited to these examples.

As used herein, a degenerate semiconductor material is intended to mean a semiconductor material, such as polysilicon, containing a high level of doping with significant interaction between dopants (e.g., phosphorous (P), boron (B), etc.). Non-degenerate semiconductors, by contrast, contain moderate levels of doping, where the dopant atoms are well separated from each other in the semiconductor host lattice with negligible interaction.

In this example, the first and the second source/drain regions,321and321, may include a high dopant concentration, n-type conductivity impurity (e.g., high dopant (n+)) doped in the first and the second source/drain regions,321and323. In some embodiments, the high dopant, n-type conductivity first and second drain regions321and323may include a high concentration of phosphorus (P) atoms deposited therein. Embodiments, however, are not limited to this example. In other embodiments, the laterally oriented access devices330(e.g., transistors) may be of a p-type conductivity construction in which case the impurity (e.g., dopant) conductivity types would be reversed.

As shown in the example embodiment ofFIG.3, the first source/drain region321may occupy an upper portion in the body326of the laterally oriented access devices330(e.g., transistors). For example, the first source/drain region321may have a bottom surface324within the body326of the laterally oriented access device330which is located higher, vertically in the third direction (D3)311, than a bottom surface of the body326of the laterally, horizontally oriented access device330. As such, the laterally, horizontally oriented transistor330may have a body portion326which is below the first source/drain region321and is in electrical contact with the body contact (e.g.,295shown inFIG.2). Further, as shown in the example embodiment ofFIG.3, a digit line (e.g.,307-1) analogous to the digit lines207-1,207-2, . . . ,207-Q inFIGS.2and107-1,107-2, . . . ,107-Q shown inFIG.1, may disposed on a top surface322of the first source/drain region321and electrically coupled thereto.

As shown in the example embodiment ofFIG.3, an access line (e.g.,303-1analogous to the access lines203-1,203-2, . . . ,203-Q inFIGS.2and103-1,103-2, . . . ,103-Q inFIG.1) may be vertically extending in the third direction (D3)311adjacent sidewall of the channel region325portion of the body326to the laterally oriented access devices330(e.g., transistors) horizontally conducting between the first and the second source/drain regions321and323along the second direction (D2)305. A gate dielectric material304may be interposed between the access line303-1(a portion thereof forming a gate to the laterally oriented access devices330(e.g., transistors) and the channel region325.

The gate dielectric material304may include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or a combination thereof. Embodiments are not so limited. For example, in high-k dielectric material examples the gate dielectric material304may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobite, etc.

FIG.4is an overhead view of a conductive line and staircase structure in accordance with one or more embodiments of the present disclosure. A memory device may include a 3D array of vertically stacked memory cells440(i.e., a memory cell array). The 3D array440of vertically stacked memory cells may include a vertical stack of horizontally oriented conductive lines (e.g.,407-1, . . . ,407-N). Each conductive line407-1, . . . ,407-N formed within the array440may include a first portion441extending in a first horizontal direction (D1)409. Each conductive line407may further include a second portion442extending in a second horizontal direction D2, at an angle to the first horizontal direction (D1)409. In other words, the memory cell array440may include a number of multi-direction conductive lines407(also referred to as bent conductive lines or bent access lines).

For example, as shown inFIG.4, in some embodiments, the second portion442of each conductive line407may extend in a second horizontal direction (D2)405at an angle to the first portion (e.g., perpendicular to the first horizontal direction (D1)409).

As shown inFIG.4, the 3D vertical array440may include a plurality of vertical levels L1LN of the staircase contact decreasing in vertical height along the first direction409(D1). Levels L1, . . . LN may also be referred to as a plurality of groups of layers. Each vertical level may include one or more layers with one or more conductive lines407formed therein. In some embodiments, the lengths of the first portions441of the conductive lines407may descend from the top of the 3D vertical array440to the bottom. Thus, if the 3D array is comprised of levels L1, L2, . . . , LN and L1is the top level of the vertical stack, the lengths of the first portions441of conductive lines407may descend from L1to LN.

As shown inFIG.4, the 3D vertical array440may include a plurality of tiers448-1, . . . ,448-N decreasing in vertical height along the second direction405(D2) from a portion441to a reference line Y. Each tier448-1, . . . ,448-N may include one or more layers with one or more conductive lines407formed therein. In some embodiments, the lengths of the second portions442of the conductive lines407may ascend from the bottom of the 3D vertical array440to the top. Thus, if the 3D array440is comprised of tiers448-1, . . . ,448-N and448-1is at the top level of the vertical stack, the lengths of the second portions442of conductive lines407may ascend from448-N to448-1.

In some embodiments, the 3D memory array440may be symmetrical about reference line Y with regard to the lengths of conductive lines407portions441and442. For example, portions441on the left side of reference line Y and441on the right side of reference line Y may be of equivalent lengths.

In some embodiments, it may be desirable to form vertical conductive line contacts439to connect conductive lines407of one tier448(e.g.,448-1). However, small conductive line widths can make this task difficult, since a great deal of precision is required to create a contact439. Thus, wider conductive line portions442may be desirable.

FIG.5. is a perspective view of a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure. A widened conductive line and staircase structure includes a substrate500. The substrate500may be or include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. Embodiments, however, are not limited to these examples.

A staircase contact structure501is formed on a working surface of the substrate500. The staircase contact structure501may include, for example, alternating layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeating iterations. The staircase contact structure501may be a contact to one or more conductive lines, such as conductive line507. Each conductive line507includes a portion541extending in a first horizontal direction509. Each conductive line507also includes one or more portions542extending in a second horizontal direction505. The second horizontal direction505may be, for example, perpendicular to the first horizontal direction509. Portions542may be wider than portion541. As shown inFIG.5, staircase contact structure501may include a number of tiers548-1, . . . ,548-N descending in vertical height from a digit line portion541and along the second direction505. For example, tier548-N may be of a greater height than tier548-1. In accordance with embodiments of the present disclosure, contacts may be formed to connect each portion542at a different tier548of staircase contact structure501.

As shown inFIG.5, the staircase contact structure501may decrease in both vertical height, along the first horizontal direction509, and also along the second horizontal direction505, creating a staircase structure in the first horizontal direction509and a staircase structure in the second horizontal direction505.

FIG.6is an overhead view of a conductive line and staircase structure in accordance with one or more embodiments of the present disclosure. As shown inFIG.6, a memory cell array640may be coupled to one or more conductive lines607(e.g.,607-1and607-2). Although only two conductive lines607-1and607-2are shown inFIG.6, embodiments of the present disclosure are not so limited. Each conductive line607may include a portion641extending in horizontal direction609and portions642extending in horizontal direction605.

In some embodiments, it may be desirable to form one or more vertical contacts639between a conductive line607and a sense amplifier or other circuitry (e.g., word line driver). However, conventional conductive line widths require a high level of precision and a low margin of error. Thus, improved conductive line and staircase structures may be beneficial in some implementations.

FIG.7is an overhead view of a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure. As shown inFIG.7, conductive lines707may be comprised of portions741-1, . . . ,741-N extending in horizontal direction709and portions742extending in horizontal direction705. Two portions (e.g., portions741-2and741-3) may extend from a horizontal center line X of a memory cell array740above and along a staircase contact structure701. The two portions741-2and741-3may be coupled to one or more portions742.

Between two portions742, one or more pad contact vias772may be formed. As will be described herein, the pad contact vias772may be vertically oriented and may intersect one or more layers of a dielectric material (e.g., dielectric material1033inFIG.10B). Dielectric material of one or more layers may be removed through the pad contact vias772, as described in connection withFIGS.10C and11C. Horizontally oriented conductive pads (e.g., conductive pads1035inFIG.10E) may then be formed by depositing a conductive material into each of the horizontal openings once containing the dielectric material through the pad contact vias772. Any excess conductive material remaining in the pad contact vias772may then be removed, and the pad contact vias may then be filled with a substrate dielectric material728to electrically isolate portions of the conductive pads.

A substrate dielectric material728may include any suitable type of dielectric material. Substrate contact dielectric material728may include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or a combination thereof. Embodiments are not so limited. For example, in high-k dielectric material examples, the substrate dielectric material728may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobite, etc.

The one or more pad contact vias772may extend to a substrate upon which the staircase contact structure701is formed (e.g., substrate500inFIG.5). The substrate dielectric material728may be of the same material from which a substrate (e.g., substrate500inFIG.5) is formed.

Conductive line contacts739may be also be formed between two portions742. Although not shown inFIG.7, the conductive line contacts739may allow for direct contact with conductive layers of the staircase contact structure701, wherein the conductive layers are in direct, electric contact with conductive lines formed within the staircase contact structure701. Thus, the conductive line contacts739may serve as contacts to the conductive lines707.

Conductive line contacts may be formed from any conductive material. Conductive material may include, for example, a conductive polymer material. The conductive material may include one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.) a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and/or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) Embodiments, however, are not limited to these examples. In some embodiments, the conductive line contacts739may form doped body contacts to conductive layers described in connection withFIGS.9A-D,10A-F, and11A-E.

FIGS.8A-Dillustrate a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure.FIG.8Ais an overhead view of a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure. As shown inFIG.8A, a memory device may include a memory cell array840.

The memory cell array840may be electrically coupled to at least one conductive line807, the conductive line807extending along the perimeter of the memory cell array840. Memory cell array840may include a staircase contact structure801. Although not shown inFIG.8A, the staircase contact structure801may be formed on a working surface of a substrate (e.g., substrate800shown inFIG.8B). The staircase contact structure801allows for direct, electrical contact with conductive lines807via portions842. Although not shown inFIG.8A, a memory device in accordance with the present disclosure may include a stack of conductive lines807, which each conductive line807is capable of being in direct, electrical contact (e.g., with sense amplifiers and other circuitry) via staircase contact structure801.

Conductive line807may include portions841-1, . . . ,841-N extending in a first horizontal direction809and portions842extending in a second horizontal direction805. A dielectric837(e.g., a spin on dielectric) may be formed so as to make contact with conductive line807via staircase contact structure801. For example, dielectric837may make contact with portions841-1,841-3, and841-5of conductive line807.

A number of conductive line contact openings873may be formed. Each conductive line contact opening873may be formed adjacent to a pad contact via872-1, . . . ,872-N. In some embodiments, each region between consecutive portions842-1, . . . ,842-N (e.g. between842-1and842-2) may contain a number of conductive line contact openings873equal to the number of pad contact vias872-1, . . . ,872-N between portions consecutive portions842-1, . . . ,842-N.

FIG.8Bis a cross-sectional view along line A inFIG.8A. As shown inFIG.8B, a staircase contact structure801is formed on a working surface of a substrate800. The staircase contact structure801includes alternating layers of dielectric material830and dielectric material833, with each dielectric material833having one or more conductive line portions842-1, . . . ,842-N formed therein.

As illustrated inFIG.8B, a staircase contact structure801may include alternating layers of a first dielectric material,830-1, . . . ,830-D (collectively referred to as first dielectric material830) and a second dielectric material,833-1, . . . ,833-D (collectively referred to as second dielectric material833), in repeating iterations to form a vertical stack on a working surface of a substrate800, analogous to substrate500inFIG.5.

In some embodiments, the first dielectric material may be an interlayer dielectric (ILD). By way of example, and not by way of limitation, the first dielectric material may include a silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the first dielectric material may include a silicon oxy-carbide material (SiOxNY) material (also referred to herein as “SiON”), and/or combinations thereof. Embodiments are not limited to these examples.

In some embodiments, the second dielectric material may be an interlayer dielectric (ILD). By way of example, and not by way of limitation, the second dielectric material may include a nitride material. The nitride material may be a silicon nitride (SixN4) material (also referred to herein as (“SiN”).

In another example, the second dielectric material833may include a silicon oxy-carbide (SiOC) material. In another example, the second dielectric material may include silicon oxy-nitride (SiON), and/or combinations thereof. Embodiments are not limited to these examples. However, according to some embodiments, the second dielectric material can be purposefully chosen to be different in material or composition than the first dielectric material, such that a selective etch process may be performed on one of the first and second dielectric layers, selective to the other one of the first and second dielectric layers, (e.g., the second SiN dielectric material may be selectively etched relative to a staircase dielectric831).

The repeating iterations of alternating first dielectric material830layers and second dielectric material833layers may be formed according to a semiconductor fabrication process such as chemical vapor deposition (CVD) in a semiconductor fabrication apparatus. Embodiments, however, are not limited to this example, and other suitable fabrication techniques may be used to form the alternating layers of a first dielectric material, a semiconductor material, and a second dielectric material, in repeating iterations to form the staircase contact structure801.

In the example ofFIG.8B, thirteen levels of the repeating iterations are shown. Embodiments, however, are not limited to this example, and more or fewer repeating iterations may be included.

In some embodiments, conductive lines807(i.e., portions842-1, . . . ,842-N of conductive lines807inFIG.8A) may be formed within the one or more layers of the second dielectric material833-D of the staircase contact structure801. This may be achieved through a conductive line formation process including, for example, forming a vertical opening, selectively removing the second dielectric833(e.g., via a lateral etch process through a vertical opening) to form a first horizontal opening by removing the second dielectric material833to a first distance back from a reference line (e.g., a center line in a vertical opening between one staircase contact structure and another staircase contact structure of the same semiconductor memory device).

The conductive line formation process may further include forming a conductive material into the vertical opening. In some embodiments, this may include conformally forming the conductive material into a portion of a vertical opening (e.g., using a chemical vapor deposition (CVD) process) such that the conductive material may also be formed into the first horizontal opening. In some embodiments, the conductive material may include a titanium nitride (TiN) material. The conductive material may form a horizontally (e.g., laterally) oriented conductive line.

Each pad contact via872-1, . . . ,872-N may create an opening in staircase dielectric831through which one or more conductive pads835may be formed. Each pad contact via872-1, . . . ,872-N also intersects one or more tiers848of staircase contact structure801. After, the conductive pads835are formed, the substrate contact dielectric828may be formed through each of the pad contact vias872-1, . . . ,872-N to provide electrical isolation between the tiers848.

The conductive pads835are formed from a conductive material. The conductive material may include, for example, a conductive polymer material. In some embodiments, the conductive material may form a doped body contact to the pad contact vias872-1, . . . ,872-N. Each conductive pad835may also be in direct, electrical contact with one or more conductive line portions842-1, . . . ,842-N.

FIG.8Cis a cross-sectional view along line B. As shown inFIG.8C, after the conductive pads835are formed, substrate dielectric828may be formed into one or more pad contact vias872-1,872-2. It should be noted that pad contact vias872-1and872-2ofFIG.8Care not necessarily equivalent in position to pad contact vias872-1and872-2ofFIGS.8A and8B.

Although some pad contact vias872-1, . . . ,872-N may intersect and form openings in conductive pads835(e.g., pad contact via872-1), other pad contact vias872-1, . . . ,872-N may conductive pads835intact and simply run adjacent (e.g., pad contact via872-2) to each other.

One or more conductive line contacts839-1and839-2may be formed by forming a conductive material into each of the one or more conductive line contact openings873. Unlike the pad contact vias872-1and872-2, each of the conductive line contact openings873may be configured to make contact with a conductive pad835of a unique tier848of staircase contact structure801.

FIG.8Dis a cross-sectional view along line C. As shown inFIG.8D, a staircase contact structure801may include more layers of dielectric material833-1, . . . ,833-D with conductive contacts835formed therein. Layers of dielectric material833-1, . . . ,833-D may be formed, for example, by removing a portion of a dielectric material833from layers of dielectric material833-1, . . . ,833-N through a substrate contact opening872-1and forming a conductive pad835into a horizontal opening designated for that conductive pad835, as shown inFIGS.9A-D,FIGS.10A-F, andFIGS.11A-E.

AlthoughFIG.8Dillustrates two conductive line contacts839-1and839-2, embodiments of the present disclosure are not so limited and can include any number of conductive line contacts839-1, . . . ,839-N. Conductive line contacts839-1and839-2may be formed in the same manner as described in connection withFIG.8C, and each conductive line contact839-N may be in direct, electrical contact with a conductive contact835. In some embodiments, each conductive line contact839-1and839-2may be electrically coupled to a unique conductive pad835, thereby forming the staircase contact structure.

FIGS.9A-Eare an overhead view of a method of forming a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure.FIG.9Aillustrates a first step of the method. As shown inFIG.9A, a memory device900may include a memory cell array940. The memory device900may include a conductive line907, wherein at least a portion of the conductive line907extends along the perimeter of the memory cell array940. Conductive line907includes portions941extending in a first horizontal direction909and portions942extending in a second horizontal direction905. Memory device900may include a staircase contact structure901formed with portions942of the conductive lines907.

A method of forming a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure may include selectively removing material from a region994. For example, although not shown inFIG.9A, in some embodiments, a hard mask material (e.g., a photoresist layer) may be formed over region994of the staircase contact structure901. In other embodiments, a hard mask material may be formed over a portion of the memory cell array940. The hard mask material may serve to protect the memory cell array region940and portions of the staircase contact structure901during subsequent processing steps described below (e.g., staircase formation steps). In other words, the hard mask material may serve as a protective layer to keep the portions of the memory cell array940and staircase contact structure901that are not being removed intact during the removal process.

In some embodiments, a masking, patterning, and etching process can be used to open region994and form a widened conductive line and staircase structure as described below. Region994may include vertically stacked groups of layers. For example, region994may include vertically stacked groups of layers, where each group of layers includes a first dielectric material layer, and a second dielectric material layer with conductive lines907formed therein.

FIG.9Billustrates another step of the method. As shown inFIG.9B, a dielectric material937may be formed over region994ofFIG.9A. The dielectric material937may be formed as to make contact with one or more conductive lines (e.g., conductive line907). Pad contact vias972-1, . . . ,972-N may be formed between conductive line portions942-1, . . . ,942-N. For example, one or more pad contact vias972-1, . . . ,972-4may be formed between portions942-2, and942-3of conductive line907. Although not shown inFIG.9B, substrate contact openings972-1, . . . ,972-4may allow contact with a substrate of the staircase contact structure901(e.g., substrate1000ofFIGS.10A-F). Although not shown inFIG.9B, staircase contact structure901may include one or more layers of dielectric material (e.g. dielectric material described in connection withFIGS.10A-FandFIGS.11A-E). Dielectric material may be removed from staircase contact structure901through the pad contact vias972-1, . . . ,972-N. Although not shown inFIG.9B, pad contact vias972-1, . . . ,972-N be formed through a mask material.

FIG.9Cillustrates another step of a method of forming a widened conductive line and staircase structure for a semiconductor device in accordance with one or more embodiments of the present disclosure. As shown inFIG.9C, a conductive material996may be formed into each of the pad contact vias972-1, . . . ,972-N. Although not shown inFIG.9C, forming conductive material996may form one or more conductive pads in place of the one or more removed layers of dielectric material (see, for example,FIG.10D). A portion of conductive material996may be removed from pad contact vias972-1, . . . ,972-N so as to allow another material to be formed into the substrate contact openings972-N and make contact with the substrate.

FIG.9Dillustrates another step of a method of forming a widened conductive line and staircase structure for a semiconductor device in accordance with one or more embodiments of the present disclosure. As shown inFIG.9D, a substrate contact dielectric material928may be formed into each of the pad contact vias972-1, . . . ,972-N. Although not shown inFIG.9D, the substrate contact dielectric material928may serve to electrically isolate each tier of a staircase structure (e.g., tiers1048-1, . . . ,1048-N ofFIG.10A).

FIG.9Eillustrates another step of a method of forming a widened conductive line and staircase structure for a semiconductor device in accordance with one or more embodiments of the present disclosure. One or more conductive line contact openings973may be formed. Each conductive line contact opening973may be positioned horizontally adjacent to two pad contact vias972-1, . . . ,972-N. Although not shown inFIG.9E, each conductive line contact opening973may allow contact with the one or more conductive pads formed in the staircase contact as described in connection withFIG.9C. A conductive material may be formed into each of the conductive line contact openings973, thereby forming one or more conductive line contacts (e.g., conductive line contacts1039-1, . . . ,1039-N shown inFIG.10F).

FIGS.10A-Fare a cross-sectional view of a method of forming a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure.FIGS.10A-Fare a cross-sectional view along line ‘A’ ofFIG.9A.FIG.10Ais a cross-sectional view of a first step of the method. As shown inFIG.10A, a staircase contact structure1001such as the one described in connection withFIG.8may be formed on a substrate1000. That substrate may include a dielectric material. The staircase contact structure1001may include repeating vertical iterations of a layer of a dielectric material1033and a layer of another dielectric material1030. Dielectric materials1033and1030may include similar components. Dielectric materials1033and1030may also include similar components as the substrate1000. For example, both the dielectric material layers1033and the substrate1000may include nitride, although embodiments of the present disclosure are not so limited. Although not shown inFIGS.10A-F, each iteration may also include a layer of semiconductor material.

The staircase contact structure1001may include one or more tiers1048-1, . . . ,1048-N. Each tier1048-1, . . . ,1048-N may include dielectric material1033-N and1030-N and may be of a unique length. The tiers1048-1, . . . ,1048-N may be ordered such that the tier of the shortest length (i.e., tier1048-N) is the top-most tier of the staircase contact structure1001and the tier of the longest length (i.e., tier1048-1) is the bottom-most tier of the staircase contact structure1001.

Dielectric material1037makes contact with each conductive line1007of the staircase contact structure1001. Dielectric material1037also can make contact with the substrate1000and a staircase dielectric1031, as illustrated inFIG.10. The staircase dielectric1031may be formed over layers of dielectric material1033.

FIG.10Bis a cross-sectional view of another step of the method. A number of pad contact vias1072-1, . . . ,1072-N are formed. The pad contact vias1072-1, . . . ,1072-N may be vertical openings. Each of the pad contact vias1072-1, . . . ,1072-N may intersect at least one of the layers of dielectric material1033. Pad contact vias1072-1, . . . ,1072-N extend down to the substrate1000. In some embodiments, pad contact vias1072-1, . . . ,1072-N may be more narrow near the bottom of the staircase contact structure1001(i.e. near the substrate1000) than near the top of the staircase contact openings1072(i.e. above conductive lines1007).

FIG.10Cis a cross-sectional view of another step of the method. Dielectric material1033ofFIGS.10A and10Bmay be removed via the pad contact vias1072-1, . . . ,1072-N. Dielectric material1033may be removed such that none of the dielectric material1033remains in the staircase contact structure1001. Although dielectric material1033is removed, dielectric material1030and conductive lines1007may remain intact in the staircase contact structure1001. Although not shown inFIG.10C, if the staircase contact structure1001includes layers of a semiconductor material, the dielectric material1033may be selectively etched relative to the semiconductor material.

FIG.10Dis a cross-sectional view of another step of the method. A number of conductive pads1035may be formed by forming conductive material (e.g., conductive material996ofFIG.9C) into each of the pad contact vias1072-1, . . . ,1072-N. Portions of the conductive material may be removed from each of the pad contact vias1072-1, . . . ,1072-N. This process may expose vertical sidewalls of the conductive material. The portions of the conductive material removed may be vertical portions such that the conductive pads1035remain intact.

The process of removing a portion of the conductive material may include using reactive ion etching or other suitable techniques. For example, the conductive material may be etched using an atomic layer etching (ALE) process. In some embodiments, the conductive material may be etched using an isotropic etch process.

FIG.10Eis a cross-sectional view of another step of the method. A substrate contact dielectric1028may be formed into each of pad contact vias1072-1, . . . ,1072-N to electrically isolate each tier1048-1, . . . ,1048-N. In some embodiments, the substrate contact dielectric1028may be similar in composition to the substrate1000. For example, the substrate contact dielectric1028and the substrate1000may each include a nitride material.

FIG.10Fis a cross-sectional view of another step of the method. A number of conductive line contact openings1073may be formed. As illustrated inFIG.9F, each of the conductive line contact openings1073may be positioned horizontally adjacent to at least one pad contact via1072-1, . . . ,1072-N. Each of the conductive line contact openings1073may allow contact with a conductive pad1035. Another conductive material may be formed into each of the conductive line contact openings1073to form a number of conductive contacts1039to conductive lines1007.

FIGS.11A-Eare another cross-sectional view of a method of forming a widened conductive line and staircase structure in accordance with one or more embodiments of the present disclosure.FIGS.11A-Eillustrate a cross-sectional view of line B inFIGS.9A and9B. As illustrated inFIG.11A, a staircase contact structure1101may include a number of layers. The number of layers may include dielectric material layers1133, wherein each of the dielectric material layers1133-N has two or more horizontal conductive lines1107formed therein. The number of layers may also include dielectric material layers1130. Each dielectric material layer1130may be positioned below a dielectric material layer1133. Although not shown inFIGS.11A-F, staircase contact structure1101may also include a number of semiconductor material layers.

FIG.11Billustrates another step of the method. As shown inFIG.11B, the method may include forming a number of pad contact vias1172-1, . . . ,1172-N. Each of the pad contact vias1172-1, . . . ,1172-N may intersect one or more dielectric material layers1133and1130. Each of the pad contact vias1172-1, . . . ,1172-N may be positioned horizontally between two conductive lines1107, wherein each of the two conductive lines1107are formed within the same dielectric material layer1133.

FIG.11Cillustrates another step of the method. As shown inFIG.11C, portions of dielectric material1133may be selectively removed via pad contact vias1172-1, . . . ,1172-N. As such, portions of the dielectric material1133may be removed while dielectric material layers1130remain intact. The removed portions of material1133may be portions between each conductive line1107and each substrate contact opening1172-1, . . . ,1172-N. Likewise, intact portions of material1133may be portions between two conductive lines1107.

FIG.11Dillustrates another step of the method. As shown inFIG.11D, a conductive material may be formed into each of the pad contact vias1172-1, . . . ,1172-N. As such, horizontal conductive pads1135may be formed on each tier1148-1, . . . ,1148-N of the staircase contact structure1101.

The method may further involve removing portions of the conductive material from each of the pad contact vias1172-1, . . . ,1172-N. The portions of the conductive material removed may be vertical portions such that conductive pads1035remain intact but conductive material remaining in the pad contact vias1172-1, . . . ,1172-N has been mostly removed. The conductive pads1135may make contact with conductive lines1107.

FIG.11Eillustrates another step of the method. The method may include forming a substrate dielectric1128into each of the pad contact vias1172-1, . . . ,1172-N. Conductive pads1135may make contact with the substrate dielectric1128and thus serve as a contact to conductive lines1107.

FIG.12is a block diagram of an apparatus in the form of a computing system1200including a memory device1203in accordance with a number of embodiments of the present disclosure. As used herein, a memory device1203, a memory array1210, and/or a host1202, for example, might also be separately considered an “apparatus.” According to embodiments, the memory device1202may include at least one memory array1210with a memory cell formed having a conductive line and staircase contact, according to the embodiments described herein. A memory array1210may be, for example, array840described previously. The memory device1202may be, for example, a portion of a sub cell array101-2shown inFIG.1as a vertically oriented stack of memory cells in an array.

In this example, system1200includes a host1202coupled to memory device1203via an interface1204. The computing system1200can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Internet-of-Things (IoT) enabled device, among various other types of systems. Host1202can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing memory1203. The system1200can include separate integrated circuits, or both the host1202and the memory device1203can be on the same integrated circuit. For example, the host1202may be a system controller of a memory system comprising multiple memory devices1203, with the system controller1205providing access to the respective memory devices1203by another processing resource such as a central processing unit (CPU).

In the example shown inFIG.12, the host1202is responsible for executing an operating system (OS) and/or various applications (e.g., processes) that can be loaded thereto (e.g., from memory device1203via controller1205). The OS and/or various applications can be loaded from the memory device1203by providing access commands from the host1202to the memory device1203to access the data comprising the OS and/or the various applications. The host1202can also access data utilized by the OS and/or various applications by providing access commands to the memory device1203to retrieve said data utilized in the execution of the OS and/or the various applications.

For clarity, the system1200has been simplified to focus on features with particular relevance to the present disclosure. The memory array1210can be a DRAM array comprising at least one memory cell having multi-direction conductive lines and staircase contacts formed according to the techniques described herein. For example, the memory array1210can be an unshielded DL 4F2 array such as a 3D-DRAM memory array. The array1210can include memory cells arranged in rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by conductive lines (which may be referred to herein as digit lines, sense lines, or data lines). Although a single array1210is shown inFIG.1, embodiments are not so limited. For instance, memory device1203may include a number of arrays1210(e.g., a number of banks of DRAM cells).

The memory device1203includes address circuitry1206to latch address signals provided over an interface1204. The interface can include, for example, a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data/address/command bus). Such protocol may be custom or proprietary, or the interface1204may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or the like. Address signals are received and decoded by a row decoder1208and a column decoder1212to access the memory array1210. Data can be read from memory array1210by sensing voltage and/or current changes on the sense lines using sensing circuitry1211. The sensing circuitry1211can comprise, for example, sense amplifiers that can read and latch a page (e.g., row) of data from the memory array1210. The I/O circuitry1207can be used for bi-directional data communication with the host1202over the interface1204. The read/write circuitry1213is used to write data to the memory array1210or read data from the memory array1210. As an example, the circuitry1213can include various drivers, latch circuitry, etc.

Control circuitry1205decodes signals provided by the host1202. The signals can be commands provided by the host1202. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array1210, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry1205is responsible for executing instructions from the host1202. The control circuitry1205can include a state machine, a sequencer, and/or some other type of control circuitry, which may be implemented in the form of hardware, firmware, or software, or any combination of the three. In some examples, the host1202can be a controller external to the memory device1203. For example, the host1202can be a memory controller which is coupled to a processing resource of a computing device.

The term semiconductor can refer to, for example, a material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film-transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a base semiconductor structure, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor in the preceding description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying materials containing such regions/junctions.

As used herein, “a number of” or a “quantity of” something can refer to one or more of such things. For example, a number of or a quantity of memory cells can refer to one or more memory cells. A “plurality” of something intends two or more. As used herein, multiple acts being performed concurrently refers to acts overlapping, at least in part, over a particular time period. As used herein, the term “coupled” may include electrically coupled, directly coupled, and/or directly connected with no intervening elements (e.g., by direct physical contact), indirectly coupled and/or connected with intervening elements, or wirelessly coupled. The term coupled may further include two or more elements that co-operate or interact with each other (e.g., as in a cause and effect relationship). An element coupled between two elements can be between the two elements and coupled to each of the two elements.

As used herein, the term “secondary portion” may be used synonymously with the term “second portion”, meaning a portion extending in a different direction than a “first portion” or “primary portion”. For example, a first portion may extend in a first direction, and a number of secondary portions may extend in a second direction perpendicular to the first direction.

The terms “first portion” and “second portion” may be used herein to denote two portions of a single element. For example, a “first portion” of a conductive line and a “second portion” of a conductive line may denote two portions of a single conductive line. It is not intended that the portions referred to as the “first” and/or “second” portions have some unique meaning. It is intended only that one of the “portions” extends in a different direction than another one of the “portions”

It should be recognized the term vertical accounts for variations from “exactly” vertical due to routine manufacturing, measuring, and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term “perpendicular.” For example, the vertical can correspond to the z-direction. As used herein, when a particular element is “adjacent to” another element, the particular element can cover the other element, can be over the other element or lateral to the other element and/or can be in direct physical contact the other element. Lateral to may refer to the horizontal direction (e.g., the y-direction or the x-direction) that may be perpendicular to the z-direction, for example.