SEMICONDUCTOR DEVICE HAVING A BONDED STRUCTURE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME

A semiconductor device includes: a first structure including a first substrate and a peripheral circuit disposed on the first substrate; and a second structure including a common source plate and a cell stack disposed on the common source plate and including a plurality of gate electrodes and channel structures, wherein the cell stack includes a plurality of cell blocks including a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region overlaps the plurality of main blocks, and the dummy common source line region is separated from the main common source line region and overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0101584, filed on Aug. 12, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor device and an electronic system including the same, and more particularly, to a semiconductor device having a bonded structure and an electronic system including the same.

DISCUSSION OF THE RELATED ART

Electronic systems having data storage demand a semiconductor device capable of storing a large amount of data. Accordingly, research on a method capable of increasing a data storage capacity of a semiconductor device is being conducted. For example, as one of the methods of increasing a data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been under development. In addition, a semiconductor device in a manner of forming a portion of the semiconductor device on a first substrate, forming the other portion of the semiconductor device on a second substrate, and bonding the first substrate to the second substrate has been under development.

SUMMARY

According to an example embodiment of the present inventive concept, a semiconductor device includes: a first structure including a first substrate, a peripheral circuit disposed on the first substrate, a first insulating structure disposed on the peripheral circuit and the first substrate, and a first bonding pad disposed on the first insulating structure; and a second structure including a common source plate, a cell stack, a second insulating structure, a second bonding pad, and an interconnect structure electrically connecting the cell stack to the second bonding pad, wherein the cell stack is disposed on the common source plate and includes a plurality of gate electrodes and a plurality of channel structures connected to the common source plate by passing through the plurality of gate electrodes, wherein the second insulating structure is disposed on the cell stack and being in contact with the first insulating structure, wherein the second bonding pad is disposed on the second insulating structure and is in contact with the first bonding pad, wherein the cell stack includes a plurality of cell blocks defined between a plurality of stack insulating layers extending in a first horizontal direction by passing through the cell stack, and wherein the plurality of cell blocks includes a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region vertically overlaps the plurality of main blocks, wherein the dummy common source line region is separated from the main common source line region and vertically overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.

According to an example embodiment of the present inventive concept, a semiconductor device includes: a first structure including a first substrate, a peripheral circuit disposed on the first substrate, a first insulating structure disposed on the peripheral circuit and the first substrate, and a first bonding pad disposed on the first insulating structure; and a second structure including a common source plate, a cell stack, a second insulating structure, and a second bonding pad disposed on the second insulating structure and being in contact with the first bonding pad, wherein the cell stack is disposed on the common source plate and includes a plurality of gate electrodes and a plurality of channel structures passing through the plurality of gate electrodes, wherein the second insulating structure is disposed on the cell stack and is in contact with the first insulating structure, wherein the cell stack includes a main block and a dummy block disposed at one side of the main block, wherein the common source plate includes: a main common source line region connected to a first channel structure in the main block among the plurality of channel structures; and a dummy common source line region connected to a second channel structure in the dummy block among the plurality of channel structures and separated from the main common source line region, wherein the dummy common source line region is configured to float when a common source voltage is applied to the main common source line region.

According to an example embodiment of the present inventive concept, an electronic system includes: a main substrate; a semiconductor device disposed on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device includes: a first structure including a first substrate, a peripheral circuit disposed on the first substrate, a first insulating structure disposed on the peripheral circuit and the first substrate, and a first bonding pad disposed on the first insulating structure; a second structure including a common source plate, a cell stack, a second insulating structure, a second bonding pad, and an interconnect structure electrically connecting the cell stack to the second bonding pad, wherein the cell stack is disposed on the common source plate and includes a plurality of gate electrodes and a plurality of channel structures connected to the common source plate by passing through the plurality of gate electrodes, wherein the second insulating structure is disposed on the cell stack and is in contact with the first insulating structure, wherein the second bonding pad is disposed on the second insulating structure and is in contact with the first bonding pad, wherein the cell stack includes a plurality of cell blocks defined between a plurality of stack insulating layers extending in a first horizontal direction by passing through the cell stack, and the plurality of cell blocks includes a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks; and a connection structure including an outer insulating layer and an input-output pad, wherein the connection structure covers the common source plate and is disposed on the second structure, and wherein the input-output pad is disposed on the outer insulating layer and is electrically connected to the interconnect structure, wherein at least a portion of the input-output pad vertically overlaps at least a portion of the at least one dummy block, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region vertically overlaps the plurality of main blocks, wherein the dummy common source line region is separated from the main common source line region and vertically overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present inventive concept are described in detail with reference to the accompanying drawings.

FIG.1is a block diagram of a semiconductor device10according to an example embodiment of the present inventive concept.

Referring toFIG.1, the semiconductor device10may include a memory cell array20and a peripheral circuit30. The memory cell array20includes a plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn may include a plurality of memory cells. The plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn may be connected to the peripheral circuit30through bit lines BL, word lines WL, string select lines SSL, and ground select lines GSL.

The peripheral circuit30may include a row decoder32, a page buffer34, a data input-output circuit36, and a control logic38. For example, the peripheral circuit30may further include an input-output interface, a column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplification circuit, and the like.

The memory cell array20may be connected to the page buffer34through the bit lines BL and connected to the row decoder32through the word lines WL, the string select lines SSL, and the ground select lines GSL. In the memory cell array20, each of a plurality of memory cells included in each of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn may be a flash memory cell. The memory cell array20may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells vertically stacked on a substrate and connected to a plurality of word lines WL.

The peripheral circuit30may receive an address ADDR, a command CMD, and a control signal CTRL from the outside (e.g., an external device) of the semiconductor device10and transmit and receive data DATA to and from a device outside the semiconductor device10.

The row decoder32may select at least one of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn in response to the address ADDR from the outside and may select a word line WL, a string select line SSL, and a ground select line GSL of the selected memory cell block. The row decoder32may provide, to the word line WL of the selected memory cell block, a voltage for performing a memory operation.

The page buffer34may be connected to the memory cell array20through the bit lines BL. The page buffer34may operate as a write driver during a program operation to apply, to the bit lines BL, a voltage according to the data DATA that is to be stored in the memory cell array20, and may operate as a sensing amplifier during a read operation to sense the data DATA stored in the memory cell array20. The page buffer34may operate in response to a control signal PCTL provided from the control logic38.

The data input-output circuit36may be connected to the page buffer34through data lines DLs. During a program operation, the data input-output circuit36may receive the data DATA from a memory controller and provide the data DATA to the page buffer34as program data based on a column address C_ADDR provided from the control logic38. During a read operation, the data input-output circuit36may provide the data DATA stored in the page buffer34to the memory controller as read data based on the column address C_ADDR provided from the control logic38.

The data input-output circuit36may provide an input address or instruction to the control logic38or the row decoder32. The peripheral circuit30may further include an electrostatic discharge (ESD) circuit and a pull-up/pull-down driver.

The control logic38may receive the command CMD and the control signal CTRL from the memory controller. The control logic38may provide a row address R_ADDR to the row decoder32and provide the column address C_ADDR to the data input-output circuit36. The control logic38may generate various kinds of internal control signals to be used inside the semiconductor device10, in response to the control signal CTRL. For example, the control logic38may adjust voltage levels to be provided to the word lines WL and the bit lines BL during a memory operation, such as a program operation or an erase operation.

FIG.2is a circuit diagram of a memory cell array MCA in the semiconductor device10, according to an embodiment of the present inventive concept.

Referring toFIG.2, the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, . . . , and BLm), a plurality of word lines WL (WL1, WL2, . . . , WLn−1, and WLn), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. The plurality of memory cell strings MS may be formed between the plurality of bit lines BL (BL1, BL2, . . . , and BLm) and the common source line CSL. AlthoughFIG.2shows that each of the plurality of memory cell strings MS includes two string select lines SSL, the present inventive concept is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string select line SSL.

Each of the plurality of memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn. A drain region of the string select transistor SST may be connected to a bit line BL (BL1, BL2, . . . , or BLm), and a source region of the ground select transistor GST may be connected to the common source line CSL. The common source line CSL may be a region to which source regions of a plurality of ground select transistors GST are commonly connected.

The string select transistor SST may be connected to a string select line SSL, and the ground select transistor GST may be connected to a ground select line GSL. The plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn may be connected to the plurality of word lines WL (WL1, WL2, . . . , WLn−1, and WLn), respectively.

FIGS.3to8illustrate a semiconductor device100according to embodiments of the present inventive concept. Particularly,FIG.3is a perspective view illustrating a representative configuration of the semiconductor device100according to an example embodiment of the present inventive concept andFIG.4is a top view illustrating the semiconductor device100ofFIG.3.FIG.5is a magnified view of part A1ofFIG.4,FIG.6is a magnified view of part A2ofFIG.4,FIG.7is a cross-sectional view taken along line B1-B1′ ofFIG.6, andFIG.8is a cross-sectional view taken along line B2-B2′ ofFIG.6.

Referring toFIGS.3to8, the semiconductor device100may include a first structure SS1and a second structure SS2that are bonded to each other in a vertical direction Z. The semiconductor device100may further include a connection structure IS that is disposed on the second structure SS2. The first structure SS1may include the peripheral circuit30described with reference toFIG.1, and the second structure SS2may include the memory cell array20described with reference toFIG.1. The connection structure IS may include an input-output terminal for an electrical connection between the peripheral circuit30and an external device. In a top view, the semiconductor device100may include a memory cell region MCR, a connection region CON, and a pad region PR.

The second structure SS2may include a plurality of cell blocks, and the plurality of cell blocks may include a plurality of main blocks BLKm and at least one dummy block BLKd. The plurality of main blocks BLKm may include the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn described with reference toFIG.1. Each of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKn may include three-dimensionally arranged memory cells.

The first structure SS1may include a first substrate110, a peripheral circuit120that is disposed on the first substrate110, a first interconnect structure130electrically connected to the peripheral circuit120, a first insulating structure140that is disposed on the first substrate110and the peripheral circuit120, and a first bonding pad150that is disposed on the first insulating structure140.

The first substrate110may include a semiconductor material, e.g., a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or SiGe. The first substrate110may be provided as a bulk wafer or an epitaxial layer. In an example embodiment of the present inventive concept, the first substrate110may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The first substrate110may have an active region AC defined by a device isolation layer112, and a plurality of peripheral circuits120may be formed on the active region AC. Each of the plurality of peripheral circuits120may include a peripheral circuit gate122and a source/drain regions124, which are disposed in portions of the first substrate110at both sides of the peripheral circuit gate122.

The first interconnect structure130may include a plurality of peripheral circuit contacts132and a plurality of peripheral circuit wiring layers134. The first insulating structure140may cover the peripheral circuit120and the first interconnect structure130on the first substrate110. The first bonding pad150may be on the first insulating structure140and may be electrically connected to the peripheral circuit120and/or the first substrate110via the first interconnect structure130. The first bonding pad150may have an upper surface substantially coplanar with an upper surface of the first insulating structure140.

In some example embodiments of the present inventive concept, the first insulating structure140may include an insulating material, such as silicon oxide, silicon nitride, a low-k material, or a combination thereof. The low-k material is a material having a lower dielectric constant than silicon oxide and may include, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicate glass (OSG), spin-on-glass (SOG), spin-on-polymer, or a combination thereof. The first bonding pad150may include a conductive material, such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof.

The second structure SS2may include a common source plate210, a cell stack220on the common source plate210, a second interconnect structure240, which is electrically connected to the cell stack220and includes a plurality of contacts242, and a plurality of wiring layers244, a second insulating structure250covering the cell stack220and the second interconnect structure240, and a second bonding pad260that is disposed on the second insulating structure250.

The cell stack220may include a plurality of gate electrodes222and a plurality of insulating layers224alternately disposed on the common source plate210, and the cell stack220may further include a plurality of channel structures230extending in the vertical direction Z by passing through the plurality of gate electrodes222and the plurality of insulating layers224. The cell stack220may include a plurality of cell blocks provided between a plurality of stack insulating layers228extending in a first horizontal direction X by passing through the cell stack220, and the plurality of cell blocks may include the plurality of main blocks BLKm and the at least one dummy block BLKd. For example, the at least one dummy block BLKd may be at both sides of the plurality of main blocks BLKm, and the at least one dummy block BLKd may include a plurality of dummy memory cells formed to have the same or similar structure as or to that of the plurality of main blocks BLKm but not to function as a memory cell.

The common source plate210may function as a source region configured to supply a current to memory cells that are formed in the second structure SS2. In some example embodiments of the present inventive concept, the common source plate210may include at least one of, for example, Si, Ge, SiGe, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and a mixture thereof. In addition, the common source plate210may include a semiconductor doped with n-type impurities. In addition, the common source plate210may have a crystal structure including at least one of a monocrystalline structure, an amorphous structure, and a polycrystalline structure. In some example embodiments of the present inventive concept, the common source plate210may include polysilicon doped with n-type impurities.

The common source plate210may include a main common source line region210mand a dummy common source line region210d. The dummy common source line region210dmay be separated from the main common source line region210min a second horizontal direction Y and may be electrically isolated from the main common source line region210m. For example, the dummy common source line region210dmay float when a common source voltage is applied to the main common source line region210m.

The main common source line region210mmay vertically overlap the plurality of main blocks BLKm, and channel structures230included in the plurality of main blocks BLKm may be in contact with the main common source line region210mby passing through the plurality of gate electrodes222and the plurality of insulating layers224.

The dummy common source line region210dmay vertically overlap the at least one dummy block BLKd, and channel structures230included in the at least one dummy block BLKd may be in contact with the dummy common source line region210dby passing through the plurality of gate electrodes222and the plurality of insulating layers224.

The common source plate210may include an opening210H, and a common source isolation insulating layer212may be disposed in the opening210H. The main common source line region210mmay be separated and electrically isolated from the dummy common source line region210dby the common source isolation insulating layer212. In some example embodiments of the present inventive concept, the common source isolation insulating layer212may extend in the first horizontal direction X along the length of the cell stack220in the first horizontal direction X, and for example, a length of the common source isolation insulating layer212in the first horizontal direction X may be greater than or equal to the length of the cell stack220in the first horizontal direction X. For example, the common source isolation insulating layer212may extend in the first horizontal direction X along the entire length of the cell stack220in the first horizontal direction X.

In some example embodiments of the present inventive concept, the common source isolation insulating layer212may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxide carbon nitride (SiOCN), silicon carbon nitride (SiCN), or a combination thereof. For example, the opening210H may be formed by removing a portion of the common source plate210, and the common source isolation insulating layer212may be formed by filling the opening210H with an insulating material. The common source isolation insulating layer212may include an upper surface, which is close to the connection structure IS, and a lower surface, which is close to the cell stack220. In some example embodiments of the present inventive concept, the common source isolation insulating layer212may have a side wall inclined so that a width of the upper surface of the common source isolation insulating layer212is greater than a width of the lower surface of the common source isolation insulating layer212. In some example embodiments of the present inventive concept, the common source isolation insulating layer212may have a side wall inclined so that the width of the lower surface of the common source isolation insulating layer212is greater than the width of the upper surface of the common source isolation insulating layer212.

As shown inFIG.5, because the common source isolation insulating layer212has a rectangular shape or a straight line shape extending in the first horizontal direction X, in a top view, the dummy common source line region210dmay have a rectangular horizontal cross-section, and the main common source line region210mmay have a rectangular horizontal cross-section.

In some example embodiments of the present inventive concept, the plurality of gate electrodes222may correspond to at least one ground select line GSL, the plurality of word lines WL (WL1, WL2, . . . , WLn−1, and WLn), and at least one string select line SSL constituting a memory cell string MS (seeFIG.2). For example, a gate electrode222closest to the common source plate210may function as a ground select line GSL, and two gate electrodes222farthest from the common source plate210may function as string select lines SSL. The other gate electrodes222may function as the plurality of word lines WL. Accordingly, a memory cell string MS having a ground select transistor GST, two string select transistors SST, and memory cell transistors MC1, MC2, . . . , MCn−1, and MCn connected in series may be provided.

In some example embodiments of the present inventive concept, at least one of the plurality of gate electrodes222may function as a dummy word line. For example, at least one additional gate electrode222may be between the gate electrode222functioning as the ground select line GSL and the common source plate210, at least one additional gate electrode222may be between the gate electrode222functioning as the ground select line GSL and a gate electrode222functioning as a word line WL, or at least one additional gate electrode222may be between a gate electrode222functioning as a word line WL and a gate electrode222functioning as a string select line SSL.

The plurality of channel structures230may extend in the vertical direction Z by passing through the plurality of gate electrodes222and the plurality of insulating layers224from the upper surface of the common source plate210on the memory cell region MCR. The plurality of channel structures230may be separated from each other by a certain interval from each other in the first horizontal direction X, the second horizontal direction Y, and a third horizontal direction (e.g., a diagonal direction). The plurality of channel structures230may be arranged in a zigzag shape, a staggered shape or an alternating arrangement.

In some example embodiments of the present inventive concept, the cell stack220may have a double stack structure, for example, the cell stack220may include a first sub-stack220_1and a second sub-stack220_2stacked on each other in the vertical direction Z, and the first sub-stack220_1may be closer to the common source plate210than the second sub-stack220_2. The plurality of channel structures230may include a first channel part230_1, which passes through the first sub-stack220_1of the cell stack220, and a second channel part230_2, which is connected to the first channel part230_1by passing through the second sub-stack220_2of the cell stack220at a position where the second channel part230_2vertically overlaps the first channel part230_1. In some example embodiments of the present inventive concept, the first sub-stack220_1of the cell stack220may be formed first, and then, the first channel part230_1passing through the first sub-stack220_1may be formed. Then, the second sub-stack220_2of the cell stack220may be formed, and then the second channel part230_2passing through the second sub-stack220_2may be formed. However, the present inventive concept is not limited thereto, and the cell stack220may have a single stack structure or a structure in which three or more sub-stacks are stacked.

A stack insulating layer228may be in a plurality of stack isolation openings220H extending in the first horizontal direction X by passing through the cell stack220, and the plurality of gate electrodes222between a pair of stack isolation openings220H may constitute a cell block. The stack insulating layer228may include, for example, silicon oxide, silicon nitride, SiON, SiOCN, SiCN, or a combination thereof. The plurality of bit lines BL may extend in the second horizontal direction Y and be separated from each other in the first horizontal direction X, and each bit line BL may be electrically connected to a channel structure230by a bit line contact BLC.

In some example embodiments of the present inventive concept, a channel structure230included in the plurality of main blocks BLKm may be electrically connected to a bit line BL by a bit line contact BLC, whereas no bit line contact BLC may be formed on a channel structure230dincluded in the at least one dummy block BLKd, and accordingly, the channel structure230dincluded in the at least one dummy block BLKd may be electrically isolated from the bit line BL.

As shown inFIG.7, the channel structure230dincluded in the at least one dummy block BLKd may be covered by a portion of the second insulating structure250, e.g., an upper insulating layer252, and this portion may be referred to as a bit line non-connection portion UBL. A first end portion of the channel structure230dincluded in the at least one dummy block BLKd may be electrically connected to the dummy common source line region210d, and a second end portion opposite to the first end portion may be covered by the bit line non-connection portion UBL and thus electrically isolated from the bit line BL. Therefore, the at least one dummy block BLKd may be electrically isolated from the plurality of main blocks BLKm.

As shown inFIG.7, within one cell block in the memory cell region MCR, two gate electrodes222farthest from the common source plate210may be divided into two parts by a string division opening in a top view. For example, the string division opening may divide the plurality of gate electrodes222corresponding to one cell block into two parts in the second horizontal direction Y, and a string isolation insulating layer229may be in the string division opening.

On the connection region CON, the plurality of gate electrodes222may constitute a pad part PAD. In the connection region CON, the plurality of gate electrodes222may extend to have a length gradually decreasing in the first horizontal direction X or the second horizontal direction Y as distance away from the upper surface of the common source plate210increases. For example, the plurality of gate electrodes222may form a staircase shape. The pad part PAD may indicate staircase-shaped parts of the plurality of gate electrodes222. In some example embodiments of the present inventive concept, the pad part PAD may have a staircase shape in both the first horizontal direction X and the second horizontal direction Y. In some example embodiments of the present inventive concept, the pad part PAD may have a staircase shape in the first horizontal direction X only. AlthoughFIG.8shows that the plurality of gate electrodes222, which constitute the pad part PAD, are formed with the same thickness as that of the plurality of gate electrodes222in the memory cell region MCR, in some example embodiments of the present inventive concept, the plurality of gate electrodes222constituting the pad part PAD may have a greater thickness than the plurality of gate electrodes222in the memory cell region MCR. For example, a portion of a gate electrode222constituting the pad part PAD may be thicker than another portion of the gate electrode222in the memory cell region MCR.

For example, a plurality of dummy channel structures, which extend in the vertical direction Z from the upper surface of the common source plate210by passing through the plurality of gate electrodes222and the plurality of insulating layers224, may be formed in the connection region CON. The dummy channel structure may be formed to prevent leaning, bending, or the like of the gate electrode222and ensure the structural stability of the gate electrode222in a manufacturing process of the semiconductor device100. In some example embodiments of the present inventive concept, the dummy channel structure may have the same height and shape as the channel structure230and may include an insulating material. In some example embodiments of the present inventive concept, the plurality of dummy channel structures may have a similar structure and shape as that of the plurality of channel structures230.

The second insulating structure250may be on the plurality of gate electrodes222constituting the pad part PAD. The second insulating structure250may include a plurality of insulating layers, and each of the plurality of insulating layers may cover the pad part PAD, the cell stack220, the bit line contact BLC, and the second interconnect structure240.

On the connection region CON, a cell contact MC1that is connected to the gate electrode222by passing through the second insulating structure250may be disposed. A cell contact plug MC2at the same vertical level as the bit line contact BLC may be on the cell contact MC1(or below the cell contact MC1as shown inFIG.7), and the cell contact plug MC2may be connected to the second interconnect structure240.

By making the second insulating structure250be in contact with the first insulating structure140and making the second bonding pad260be in contact with the first bonding pad150corresponding thereto, the second structure SS2may be bonded to the first structure SS1. For example, the first structure SS1and the second structure SS2may be bonded to each other by metal-oxide hybrid bonding, and accordingly, the second interconnect structure240included in the second structure SS2may be electrically connected to the peripheral circuit120included in the first structure SS1.

The connection structure IS may be on the second structure SS2, and the connection structure IS may include an outer insulating layer270, which is disposed on the common source plate210, an input-output pad280, which is disposed on the outer insulating layer270, and a connection via290connecting the input-output pad280to a peripheral contact plug244P by passing through the outer insulating layer270. In some example embodiments of the present inventive concept, the connection via290may vertically overlap the dummy common source line region210d, and in this case, an insulating layer282may be formed on a side wall of the connection via290to electrically isolate the connection via290from the dummy common source line region210d.

As shown inFIG.5, the input-output pad280may vertically overlap the memory cell region MCR at an edge of the memory cell region MCR, e.g., vertically overlap the at least one dummy block BLKd and the plurality of main blocks BLKm. At least a portion of the input-output pad280may vertically overlap the at least one dummy block BLKd, and the at least one dummy block BLKd may be on the dummy common source line region210delectrically isolated from the main common source line region210m. Therefore, it may be configured that the dummy common source line region210dfloats even when the common source voltage is applied to the main common source line region210m, and the plurality of main blocks BLKm operate, and accordingly, an input-output capacitance by the input-output pad280may be reduced, thereby reducing common source line noise or increasing input-output performance.

FIGS.9to11are magnified cross-sectional views illustrating the channel structure230according to example embodiments of the present inventive concept.FIGS.9to11are magnified views of a part corresponding to part A3ofFIG.7.

Referring toFIG.9, each of the plurality of channel structures230may be in a channel hole230H on the memory cell region MCR (seeFIG.6). Each of the plurality of channel structures230may include a gate insulating layer232, a channel layer234, a buried insulating layer236, and a conductive plug. The gate insulating layer232and the channel layer234may be sequentially disposed on a side wall of the channel hole230H. For example, the gate insulating layer232may be conformally formed on the side wall of the channel hole230H, and the channel layer234may be conformally formed on the side wall and a bottom portion of the channel hole230H. The channel layer234may be disposed on the upper surface of the common source plate210at the bottom portion of the channel hole230H. For example, the channel layer234may be in contact with the upper surface of the common source plate210at the bottom portion of the channel hole230H. The buried insulating layer236filling a residual space of the channel hole230H may be disposed on the channel layer234. The conductive plug being in contact with the channel layer234and covering the entrance of the channel hole230H may be at an upper side of the channel hole230H (e.g., in a portion of the channel hole230H that is closer to the first structure SS1). In some example embodiments of the present inventive concept, the buried insulating layer236may be omitted, and the channel layer234may be formed in a pillar shape filling the residual space of the channel hole230H.

The gate electrode222may include a metal, such as W, nickel (Ni), cobalt (Co), or Ta, a conductive metal nitride, such as titanium nitride, tantalum nitride, or tungsten nitride, metal silicide, such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide, doped polysilicon, or a combination thereof. A dielectric liner239may be between the gate electrode222and the insulating layer224, and the dielectric liner239may include a high-k material, such as aluminum oxide.

The gate insulating layer232may have a structure sequentially including a tunneling dielectric layer232A, a charge storage layer232B, and a blocking dielectric layer232C disposed on an outer wall of the channel layer234. Relative thicknesses of the tunneling dielectric layer232A, the charge storage layer232B, and the blocking dielectric layer232C constituting the gate insulating layer232are not limited to the thicknesses shown inFIG.9and may be variously modified.

The tunneling dielectric layer232A may include, for example, silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. The charge storage layer232B is a region in which electrons having passed through the tunneling dielectric layer232A from the channel layer234may be stored, and may include, for example, silicon nitride, boron nitride, silicon boron nitride, or impurity-doped polysilicon. The blocking dielectric layer232C may include, for example, silicon oxide, silicon nitride, or metal oxide having a greater dielectric constant than that of the silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

Referring toFIG.10, the channel structure230may further include a contact semiconductor layer234_L and a bottom insulating layer232_L at the bottom portion of the channel hole230H (herein, the bottom portion indicates a first end portion of the channel hole230H adjacent to the common source plate210). The channel layer234might not be in direct contact with the common source plate210, and the channel layer234may be electrically connected to the common source plate210via the contact semiconductor layer234_L. In some example embodiments of the present inventive concept, the contact semiconductor layer234_L may include a silicon layer formed by a selective epitaxy growth (SEG) process using the common source plate210at the bottom portion of the channel hole230H as a seed layer.

The bottom insulating layer232_L may be between the contact semiconductor layer234_L and a lowermost gate electrode222_L that is most adjacent to the common source plate210. In some example embodiments of the present inventive concept, the bottom insulating layer232_L may include silicon oxide, and for example, the bottom insulating layer232_L may be formed by performing an oxidation process on a portion of a side wall of the contact semiconductor layer234_L.

Referring toFIG.11, the channel structure230may have a structure electrically connected to a horizontal semiconductor layer214via a side wall of the channel layer234instead of being electrically connected to the common source plate210. For example, the horizontal semiconductor layer214and the support layer216may be sequentially stacked on the upper surface of the common source plate210, and the cell stack220(seeFIG.7) including the insulating layer224and the gate electrode222may be on the support layer216.

In some example embodiments of the present inventive concept, the horizontal semiconductor layer214may include polysilicon doped with impurities or without doped with impurities. The horizontal semiconductor layer214may function as a portion of a common source region connecting the common source plate210to the channel layer234. For example, the support layer216may include doped or undoped polysilicon. The support layer216may prevent a mold stack from collapsing or falling in a process of removing a sacrificial material layer for forming the horizontal semiconductor layer214.

The gate insulating layer232may be on an inner wall and the bottom portion of the channel hole230H. A bottom surface of the channel layer234may be on the gate insulating layer232so as not to be in direct contact with the common source plate210, and a side wall of a bottom portion of the channel layer234may be at least partially surrounded by the horizontal semiconductor layer214.

FIGS.9to11schematically show the channel structure230having representative structures employable in example embodiments of the present inventive concept, and it would be understood that the channel structure230in some example embodiments of the present inventive concept may have different structures from the structures described with reference toFIGS.9to11.

FIG.12is a cross-sectional view illustrating a semiconductor device100A according to an example embodiment of the present inventive concept.FIG.12is a cross-sectional view corresponding to the cross-section taken along line B1-B1′ ofFIG.6.

Referring toFIG.12, the channel structure230dincluded in the at least one dummy block BLKd might not be electrically connected to the bit line BL. The bit line BL may vertically overlap the plurality of main blocks BLKm and might not vertically overlap the at least one dummy block BLKd, and accordingly, the bit line contact BLC that is on the channel structure230d, which is included in the at least one dummy block BLKd, might not be connected to a corresponding bit line BL. For example, the bit line contact BLC that is on the channel structure230d, which is included in the at least one dummy block BLKd, may be covered by a portion of the second insulating structure250, and this portion of the second insulating structure250may be referred to as the bit line non-connection portion UBL.

The first end portion of the channel structure230dincluded in the at least one dummy block BLKd may be electrically connected to the dummy common source line region210d, and the bit line contact BLC connected to the second end portion opposite to the first end portion may be covered by the bit line non-connection portion UBL and thus might not be electrically connected to the bit line BL. Therefore, the at least one dummy block BLKd may be electrically isolated from the plurality of main blocks BLKm.

According to the embodiment described above, it may be configured that the dummy common source line region210dfloats even when the common source voltage is applied to the main common source line region210m, and the plurality of main blocks BLKm operate, and accordingly, the input-output capacitance by the input-output pad280may be reduced, thereby reducing the common source line noise or increasing the input-output performance.

FIG.13is a cross-sectional view illustrating a semiconductor device100B according to an example embodiment of the present inventive concept.FIG.13is a cross-sectional view corresponding to the cross-section taken along line B2-B2′ ofFIG.6.

Referring toFIG.13, it may be configured that the dummy common source line region210dfloats, and the plurality of gate electrodes222of the at least one dummy block BLKd float while the common source voltage is applied to the main common source line region210m, and a gate voltage (e.g., a word line voltage, a ground select line voltage, and a string select line voltage) is applied to the plurality of gate electrodes222of the plurality of main blocks BLKm. The channel structure230dincluded in the at least one dummy block BLKd might not be electrically connected to the bit line BL, and the plurality of gate electrodes222at least partially surrounding the channel structure230dmight not be electrically connected to the peripheral circuit120included in the first structure SS1. For example, the pad part PAD included in one dummy block BLKd might not be connected to the second bonding pad260because a portion of the second interconnect structure240is omitted, and the omitted portion of the second interconnect structure240may be referred to as a cell contact non-connection portion UMC.

In some example embodiments of the present inventive concept, a contact242between two wiring layers244, of the wiring layers244, most adjacent to the second bonding pad260may be omitted. For example, when the second interconnect structure240includes first to third wiring layers ML1, ML2, and ML3having different vertical distances from an end portion of the channel structure230d, no contact242may be formed between the second wiring layer ML2and the third wiring layer ML3, and thus, the second wiring layer ML2might not be electrically connected to the third wiring layer ML3.

In some example embodiments of the present inventive concept, unlike shown inFIG.13, the plurality of gate electrodes222surrounding the channel structure230dincluded in the at least one dummy block BLKd might not be electrically connected to the peripheral circuit120included in the first structure SS1because any one of the first to third wiring layers ML1, ML2, and ML3or any one of contacts242between the first to third wiring layers ML1, ML2, and ML3may be omitted.

In some example embodiments of the present inventive concept, unlike shown inFIG.13, the plurality of gate electrodes222surrounding the channel structure230dincluded in the at least one dummy block BLKd might not be electrically connected to the peripheral circuit120included in the first structure SS1because either the cell contact MC1or the cell contact plug MC2is omitted.

In some example embodiments of the present inventive concept, unlike shown inFIG.13, the plurality of gate electrodes222of the at least one dummy block BLKd may be electrically connected to the peripheral circuit120included in the first structure SS1without forming the cell contact non-connection portion UMC (for example, a portion of the second interconnect structure240connected to the plurality of gate electrodes222of the at least one dummy block BLKd might not be omitted). In this case, it may be configured that the channel structure230dof the at least one dummy block BLKd floats by applying a dummy gate voltage (e.g., a dummy word line voltage, a dummy ground select line voltage, and a dummy string select line voltage), which is different from the gate voltage, to the plurality of gate electrodes222of the at least one dummy block BLKd while the gate voltage (e.g., the word line voltage, the ground select line voltage, and the string select line voltage) is applied to the plurality of gate electrodes222of the plurality of main blocks BLKm.

According to the embodiment described above, it may be configured that the dummy common source line region210dfloats even when the common source voltage is applied to the main common source line region210m, and the plurality of main blocks BLKm operate. Accordingly, the input-output capacitance by the input-output pad280may be reduced, thereby reducing the common source line noise or increasing the input-output performance.

FIG.14is a top view illustrating a semiconductor device100C according to an example embodiment of the present inventive concept.

Referring toFIG.14, in a top view, a plurality of dummy blocks BLKd may be at one side of the plurality of main blocks BLKm, and the region of the input-output pad280may vertically overlap the plurality of dummy blocks BLKd. The common source isolation insulating layer212may extend in the first horizontal direction X between the plurality of dummy blocks BLKd and the plurality of main blocks BLKm, and accordingly, the region of the input-output pad280may be on the dummy common source line region210d.

FIG.15is a top view illustrating a semiconductor device100D according to an example embodiment of the present inventive concept.

Referring toFIG.15, in a top view, the plurality of dummy blocks BLKd may be at one side of the plurality of main blocks BLKm, and the region of the input-output pad280may vertically overlap the plurality of dummy blocks BLKd. The common source isolation insulating layer212may be between the plurality of dummy blocks BLKd and the plurality of main blocks BLKm. The common source isolation insulating layer212may include a first part212P1, which extends in the first horizontal direction X, and a second part212P2, which extends in the second horizontal direction Y. In a top view, the first part212P1and the second part212P2may surround at least a portion of the input-output pad280.

The dummy common source line region210dmay have a first width w11, which is in the second horizontal direction Y at a portion vertically overlapping the input-output pad280, and have a second width w12, which is less than the first width w11, in the second horizontal direction Y at a portion (e.g., a region between two adjacent input-output pads280) not vertically overlapping the input-output pad280. A portion of the main common source line region210min the region between two adjacent input-output pads280may extend toward the dummy common source line region210d, and a portion of the main common source line region210mbetween the adjacent two input-output pads280may be referred to as an extension part210me. Because the main common source line region210mincludes the extension part210me, a common source line resistance may be reduced.

FIG.16is a top view illustrating a semiconductor device100E according to an example embodiment of the present inventive concept.

Referring toFIG.16, at least a portion of the input-output pad280may vertically overlap the extension part210meof the main common source line region210m. For example, a first region280R1of the input-output pad280may vertically overlap the dummy common source line region210d, and a second region280R2of the input-output pad280may vertically overlap the extension part210meof the main common source line region210m.

According to some example embodiments of the present inventive concept, because the main common source line region210mincludes the extension part210me, the common source line resistance may be reduced, and because the first region280R1of the input-output pad280vertically overlaps the dummy common source line region210d, the input-output capacitance by the input-output pad280may be reduced, thereby increasing the input-output performance.

FIG.17is a top view illustrating a semiconductor device100F according to an example embodiment of the present inventive concept, andFIG.18is a magnified view of part A4ofFIG.17.

Referring toFIGS.17and18, the semiconductor device100F may have the pad region PR formed at a central part thereof, and the at least one dummy block BLKd may be in a region of the memory cell region MCR that is adjacent to the pad region PR.

FIG.19is a top view illustrating a semiconductor device100G according to example embodiment of the present inventive concept.FIG.20is a cross-sectional view taken along line B3-B3′ ofFIG.19.

Referring toFIGS.19and20, the dummy common source line region210ddescribed with reference toFIGS.3to8may be omitted, and the at least one dummy block BLKd may vertically overlap the outer insulating layer270. The outer insulating layer270may be between the input-output pad280and the at least one dummy block BLKd. In some example embodiments of the present inventive concept, by removing the dummy common source line region210dand filling the outer insulating layer270in a portion from which the dummy common source line region210dhas been removed, the semiconductor device100G described with reference toFIGS.19and20may be formed. According to some example embodiments of the present inventive concept, by disposing the outer insulating layer270between the input-output pad280and the at least one dummy block BLKd, the input-output capacitance by the input-output pad280may be reduced, thereby reducing the common source line noise or increasing the input-output performance.

FIG.21is a block diagram of an electronic system1000including a semiconductor device, according to an example embodiment of the present inventive concept.

Referring toFIG.21, the electronic system1000may include at least one semiconductor device1100and a memory controller1200electrically connected to the at least one semiconductor device1100. The electronic system1000may be, for example, a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including the at least one semiconductor device1100.

A semiconductor device1100may be a nonvolatile semiconductor device, and for example, the semiconductor device1100may be a NAND flash semiconductor device including one of the semiconductor devices10,100,100A,100B,100C,100D,100E,100F, and100G described with reference toFIGS.1to20. The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. The first structure1100F may be a peripheral circuit structure including a row decoder1110, a page buffer1120, and a logic circuit1130.

The second structure1100S may be a memory cell structure including the plurality of bit lines BL, the common source line CSL, the plurality of word lines WL, first and second string select lines UL1and UL2, first and second ground select lines LL1and LL2, and a plurality of memory cell strings CSTR disposed between the plurality of bit lines BL and the common source line CSL.

In the second structure1100S, each of the plurality of memory cell strings CSTR may include ground select transistors LT1and LT2, string select transistors UT1and UT2, and a plurality of memory cell transistors MCT. The ground select transistors LT1and LT2may be adjacent to the common source line CSL, and the string select transistors UT1and UT2may be adjacent to a bit line BL. The plurality of memory cell transistors MCT may be between the ground select transistors LT1and LT2and the string select transistors UT1and UT2. The number of ground select transistors LT1and LT2and the number of string select transistors UT1and UT2may be variously modified according to example embodiments of the present inventive concept.

In some embodiments of the present inventive concept, the first and second ground select lines LL1and LL2may be connected to gate electrodes of the ground select transistors LT1and LT2, respectively. The plurality of word lines WL may be connected to gate electrodes of the plurality of memory cell transistors MCT, respectively. The first and second string select lines UL1and UL2may be connected to gate electrodes of the string select transistors UT1and UT2, respectively.

The common source line CSL, the first and second ground select lines LL1and LL2, the plurality of word lines WL, and the first and second string select lines UL1and UL2may be connected to the row decoder1110. The plurality of bit lines BL may be electrically connected to the page buffer1120.

The semiconductor device1100may communicate with the memory controller1200through input-output pads1101that are electrically connected to the logic circuit1130. The input-output pads1101may be electrically connected to the logic circuit1130.

The memory controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In some example embodiments of the present inventive concept, the electronic system1000may include a plurality of semiconductor devices1100, and in this case, the memory controller1200may control the plurality of semiconductor devices1100.

The processor1210may control a general operation of the electronic system1000including the memory controller1200. The processor1210may operate according to certain firmware and control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221configured to process communication with the semiconductor device1100. Through the NAND interface1221, a control command for controlling the semiconductor device1100, data to be written on the plurality of memory cell transistors MCT in the semiconductor device1100, data read from the plurality of memory cell transistors MCT in the semiconductor device1100, and the like may be transferred. The host interface1230may provide a communication function between the electronic system1000and an external host. When a control command is received from the external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.22is a perspective view schematically illustrating an electronic system2000including a semiconductor device, according to an example embodiment of the present inventive concept.

Referring toFIG.22, the electronic system2000according to an example embodiment of the present inventive concept may include a main substrate2001and a memory controller2002, a semiconductor package2003, and dynamic random access memory (DRAM)2004mounted on the main substrate2001. The semiconductor package2003and the DRAM2004may be connected to the memory controller2002through a plurality of wiring patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins coupled to an external host. The number and the arrangement of pins in the connector2006may vary according to a communication interface between the electronic system2000and the external host. In some example embodiments of the present inventive concept, the electronic system2000may communicate with the external host according to any one of interfaces, such as a USB interface, a peripheral component interconnect express (PCI-Express) interface, a serial advanced technology attachment (SATA) interface, and an M-Phy interface for a universal flash storage (UFS). In some example embodiments of the present inventive concept, the electronic system2000may operate by power received from the external host through the connector2006. The electronic system2000may further include a power management integrated circuit (PMIC) configured to distribute the power received from the external host to the memory controller2002and the semiconductor package2003.

The memory controller2002may write or read data on or from the semiconductor package2003and increase an operating speed of the electronic system2000.

The DRAM2004may be a buffer memory configured to mitigate a speed difference between the semiconductor package2003, which is a data storage space, and the external host. The DRAM2004included in the electronic system2000may operate as a kind of cache memory and provide a space in which data is temporarily stored in a control operation on the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the memory controller2002may further include a DRAM controller configured to control the DRAM2004in addition to a NAND controller configured to control the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bseparated from each other. Each of the first and second semiconductor packages2003aand2003bmay include a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, the plurality of semiconductor chips2200on the package substrate2100, an adhesive layer2300beneath each of the plurality of semiconductor chips2200, a plurality of connection structures2400electrically connecting the plurality of semiconductor chips2200to the package substrate2100, and a molding layer2500covering the plurality of semiconductor chips2200and the plurality of connection structures2400on the package substrate2100.

The package substrate2100may be a printed circuit board including a plurality of package upper pads2130. Each of the plurality of semiconductor chips2200may include input-output pads2210. The input-output pads2210may correspond to the input-output pads1101ofFIG.21. Each of the plurality of semiconductor chips2200may include at least one of the semiconductor devices10,100,100A,100B,100C,100D,100E,100F, and100G described with reference toFIGS.1to20.

In some example embodiments of the present inventive concept, the plurality of connection structures2400may be bonding wires electrically connecting the input-output pads2210to the plurality of package upper pads2130. Therefore, in the first and second semiconductor packages2003aand2003b, the plurality of semiconductor chips2200may be electrically connected to each other by a bonding wire scheme and electrically connected to the plurality of package upper pads2130of the package substrate2100. In some example embodiments of the present inventive concept, in the first and second semiconductor packages2003aand2003b, the plurality of semiconductor chips2200may be electrically connected to each other through a connection structure including through silicon vias (TSVs) instead of the plurality of connection structures2400of the bonding wire scheme.

In some example embodiments of the present inventive concept, the memory controller2002and the plurality of semiconductor chips2200may be included in one package. In some example embodiments of the present inventive concept, the memory controller2002and the plurality of semiconductor chips2200may be mounted on a separate interposer substrate other than the main substrate2001, and the memory controller2002may be connected to the plurality of semiconductor chips2200through wirings formed on the interposer substrate.

FIG.23is a cross-sectional view illustrating the semiconductor package2003according to an example embodiment of the present inventive concept.FIG.23is a cross-sectional view taken along line II-II′ ofFIG.22.

Referring toFIG.23, in the semiconductor package2003, the package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body part2120, the plurality of package upper pads2130(seeFIG.22), which are on an upper surface of the package substrate body part2120, a plurality of lower pads2125disposed on or exposed through a lower surface of the package substrate body part2120, and a plurality of internal wirings2135, which are disposed inside the package substrate body part2120to electrically connect the plurality of package upper pads2130(seeFIG.22) to the plurality of lower pads2125. As shown inFIG.22, the plurality of package upper pads2130may be electrically connected to the plurality of connection structures2400. As shown inFIG.23, the plurality of lower pads2125may be connected, through a plurality of conductive bumps2800, to the plurality of wiring patterns2005on the main substrate2001of the electronic system2000shown inFIG.22. Each of the plurality of semiconductor chips2200may include at least one of the semiconductor devices10,100,100A,100B,100C,100D,100E,100F, and100G described with reference toFIGS.1to20.