Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines

A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.

TECHNICAL FIELD

The present invention relates to software tools in general, and, in particular, to a method within a software tool for designing integrated circuits. Still more particularly, the present invention relates to a method for providing static random memory cells that allow multiple variations of metal level assignments for bitlines and wordlines.

DESCRIPTION OF RELATED ART

Static random access memory (SRAM) cells having different bitline and wordline personalizations are in existence today. For example, some SRAM cells have bitlines built on a metal-3 (M3) layer and wordlines built on a metal-2 (M2) layer, and some SRAM cells have bitlines built on a M2 layer and wordlines built on a M3 layer. Thus, a wafer foundry has to be able to manufacture different SRAM cell architectures in order to cater to different customers that utilize various metal line personalizations.

However, the development of different bitline and wordline personalizations can incur huge expenses. In addition, with various new effects, such as shallow trench isolation (STI) compression, and n-well scattering becoming major modeling issues for devices that operate in the submicron regime, the development of custom SRAM cell device models as well as the associated model-to-hardware can be a burden on various resources such as technology development, yield learning and modeling resources.

Consequently, it would be desirable to provide an improved method for providing SRAM cells that allow multiple variations of metal level assignments for bitlines and wordlines such that some of the above-mentioned expenses can be consolidated.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the present invention, a memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The area and aspect ratio of static random access memory (SRAM) cells are typically common among foundry customers. Thus, they can usually be shared by different foundry customers. However, sometimes different foundry customers would prefer to develop different SRAM cells for different SRAM cell architectures. For example, some foundry customers build their SRAM cells with bitlines on a metal-2 layer and wordlines on a metal-3 layer, and other foundry customers build their SRAM cells with bitlines on a metal-3 layer and wordlines on a metal-2 layer.

In order to accommodate the various needs of different foundry customers for SRAM cells to have bitlines and wordlines on different metal levels, the present invention provides a common SRAM cell with a shared front-end (which includes diffusions, polysilicons, n-wells, p-wells, contacts, and a metal-1 layer) but with several personalized back-ends (which includes metal-2, metal-3 and metal-4 layers). Specifically, the common SRAM cell of the present invention includes two cell elements. Both cell elements are identically processed up to the metal-1 layer. Then, each of the two cell elements is processed differently for the metal-2 layer and above.

Referring now to the drawings and in particular toFIG. 1, there is depicted a method for providing SRAM cells that allow multiple variations of metal level assignments for bitlines and wordlines, in accordance with a preferred embodiment of the present invention. The starting point of the method is a metal-1 (M1) layer on which transistors are built, as shown in block10. A determination is made as to whether a metal-2 (M2) layer or a metal-3 (M3) layer is the preferred metal layer for bitlines, as depicted in block11.

If the preferred metal layer for bitlines is the M2 layer, then the M1-to-M2 transition layer (i.e., VIA1) is personalized with the pattern for bitlines on the M2 layer, as shown in block12. The M2 layer is subsequently personalized with the pattern for vertical bitlines, as depicted in block13. The M2-to-M3 transition layer (i.e., VIA2) is then personalized via the pattern for wordlines on the M3 layer, as shown in block14. Next, the M3 layer is personalized with the pattern for the horizontal wordlines, as depicted in block15, and the conventional processing process flow can be resumed, as shown in block20.

Otherwise, if the preferred metal layer for bitlines is the M3 layer, then the M1-to-M2 transition layer (i.e., VIA1) is personalized with the pattern for wordlines on the M2 layer, as shown in block16. The M2 layer is subsequently personalized with the pattern for horizontal wordlines, as depicted in block17. The M2-to-M3 transition layer (i.e., VIA2) is then personalized with the pattern for bitlines on the M3 layer, as shown in block18. Next, the M3 layer is personalized with the pattern for vertical bitlines, as depicted in block19, and the conventional process flow can be resumed, as shown in block20.

With reference now toFIG. 2, there is graphically depicted an SRAM memory cell having identical front-ends but different personalizations for back-ends, in accordance with a preferred embodiment of the present invention. As shown, an SRAM cell includes a cell element31and a cell element32. Both cell elements31and32share identical processing steps up to the M1 layer, as shown in stage21. Then, the processing steps for cell elements31and32differs according to different personalization schemes.

In stage22, VIA1s are added to cell elements31and32at different locations. In stage23, cell element31is processed at the M2 layer according to blocks12–13ofFIG. 1, and cell element32is processed at the M2 layer according to blocks16–17ofFIG. 1. In stage24, VIA2s are added to cell elements31and32at different locations. In stage25, cell element31is processed at the M3 layer according to blocks14–15ofFIG. 1, and cell element32is processed at the M3 layer according to blocks18–19ofFIG. 1. As a result, cell element31has bitlines on the M2 layer and wordlines on the M3 layer, and cell element32has wordlines on the M2 layer and bitlines on the M3 layer. Any physical shapes requiring a ground rule waiver are implemented below the M1 layer. In other words, the two different personalizations in cell elements31and32are achieved in a completely ground rule clean fashion.

As has been described, the present invention provides a method for providing an SRAM cell that enables multiple variations of metal level assignments for bitlines and wordlines. Basically, the present invention provides a method for making an SRAM cell (or memory cells in general) with two cell elements, each of the cell elements has an identical front-end level (i.e., diffusions, polysilicons and contacts) but different metal layer personalization at the back-end. As a result, each of the cell elements can have bitlines and wordlines located on different metal layers. Since most of the ground rule waivers in SRAM cells are typically related to the front-end metal layers, the two cell elements are allowed to have common front-end shapes where the most technology learning, such as lithography, model-based optical process correction, and yield learning, has to be acquired. In contrast, the differently personalized back-ends are ground rule clean and so typically little attention other than the general technology learning is required.

With the present invention, foundry customers can choose between two metalization options for the wiring of bitlines and wordlines of an SRAM cell. The two metalization options provide foundry customers with a practically “generic” SRAM cell that can be used across various SRAM architectures, regardless of the orientation of the wordlines and bitlines. Also, by maintaining the same front-end of the line mask levels (i.e., device topology), SRAM cell performance (such as beta ratio, Qcritand Ion/Ioff) for both metalization schemes would remain constant.

While different SRAM cells can be used to achieve the same purpose as mentioned above, the present invention helps to share development across multiple SRAM cells and thus the total cost of memory cell development can be defrayed. The work associated with maintaining multiple SRAM cell designs along with characterization and modeling to account for new issues across the life of a product is substantial. The present invention helps to collapse the potentially multiple costs for multiple SRAM cell designs into one combined cost for a single SRAM cell platform.

Referring now toFIG. 3, there is depicted a block diagram of a computer system in which a preferred embodiment of the present invention can be implemented. As shown, a computer system50includes a main processor51coupled to a main memory52and a multiple-function I/O processor (MFIOP)53. Main processor51may include a single processor or multiple processors. Several peripheral storage devices, such as a diskette drive56, a tape drive57, and a direct access storage devices (DASDs)58, are controlled by MFIOP53. In addition, MFIOP53provides communications to other devices via communications ports such as COMM 1 and COMM 2.

A workstation controller54is coupled to a communications I/O processor (CIOP)55via a system bus59. Workstation controller54provides communications between main processor51and workstations60that may be connected to computer system50. CIOP55provides communications to other devices via communication ports such as COMM3, COMM4, and COMM5.

Although the present invention has been described in the context of a fully functional computer system, those skilled in the art will appreciate that the mechanisms of the present invention are capable of being distributed as a program product in a variety of forms, and that the present invention applies equally regardless of the particular type of signal bearing media utilized to actually carry out the distribution. Examples of signal bearing media include, without limitation, recordable type media such as floppy disks or CD ROMs and transmission type media such as analog or digital communications links.