Memory operations with consideration for wear leveling

As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

BACKGROUND

Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on a user input to the computing system, the processing circuitry may request that a memory module retrieve data corresponding to the user input from its memory devices. In some instances, the retrieved data may include firmware, or instructions executable by the processing circuitry to perform an operation, and/or may include data to be used as an input for the operation. In addition, in some cases, data output from the operation may be stored in memory, for example, to enable subsequent retrieval. In instances where firmware is retrieved from non-volatile memory (e.g., media, storage), a pattern of retrieval of the information stored in memory may be inefficient. Each memory chip is made up of sub-units sometimes referred to as memory banks. Memory banks may share input/output circuitry but may otherwise operate independent of each other. In this way, a computing system may reference a portion of one memory bank without referencing a portion of another memory bank. A memory unit may be a single memory chip or a collection of memory chips. Memory units may be thought to be made up of memory “banks.” Since memory banks may operate independently, a read or write instruction to one memory bank may proceed to execute while another memory bank is busy processing a previous read/write instruction. This means that a memory chip may operate simultaneous operations in multiple banks. However, if operations are issued to the same bank, the memory chip may wait to process next operation until any previous operations are finished. Thus, a read/write speed of a given memory system (e.g., one or more memory units) may depend on how data being transferred to/from the memory is distributed across different banks. For example, if all data is stored in the same bank, a total duration of time used for performing memory operations is expected to be longer relative to a total duration of time used for performing memory operations when the data is stored and/or distributed across multiple banks.

In storage systems, an address translation table may be used to map memory addresses from logical to physical addresses. For example, data (e.g., the information stored in the memory) may be mapped from logical to physical addresses of the memory using a logical-to-physical (L2P) translation table. Over time, some physical addresses of the memory may be accessed more often than other physical addresses of the memory in response to memory access patterns, which may age portions of the memory corresponding to the more accessed physical addresses at a relatively faster rate than other portions of the memory. Uneven aging of a memory is generally undesirable. A more efficient memory accessing operation may be desired to improve memory management operations (e.g., improve performance, reduce an amount of time used to perform memory operations) and improve wear leveling (e.g., reduction of uneven access patterns, evening out of access patterns as to promote even aging of the memory).

DETAILED DESCRIPTION

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. One or more specific embodiments of the present embodiments described herein will be described below. In an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Generally, hardware of a computing system includes processing circuitry and memory implemented using one or more processors and/or one or more memory devices (e.g., as chips, as integrated circuits). During operation of the computing system, the processing circuitry may perform various operations (e.g., tasks) by executing corresponding instructions, for example, based on a user input to determine output data by performing operations on input data. To facilitate operation of the computing system, data accessible to the processing circuitry may be stored in a memory device, such that the memory device stores the input data, the output data, data indicating the executable instructions, or any combination thereof.

Additionally, in some instances, memory devices may be implemented using different memory types. For example, a memory device may be implemented as volatile memory, such as dynamic random-access memory (DRAM) or static random-access memory (SRAM). Alternatively, the memory device may be implemented as non-volatile memory, such as flash (e.g., NAND, NOR) memory, phase-change memory (e.g., 3D XPoint™), or ferroelectric random access memory (FeRAM). In any case, memory devices generally include at least one memory die (e.g., an array of memory cells configured on a portion or “die” of a semiconductor wafer) to store data bits (e.g., “0” bit or “1” bit) transmitted to the memory device through a channel (e.g., data channel, communicative coupling, bus interface) and may be functionally similar from the perspective of the processing circuitry even when the memory devices include different memory types.

During operation of the host device, applications or programs of the host device, or other components of the host device, may generate or access information stored in the memory. Information stored as the data within the memory may be stored at physical locations. These physical locations within the memory may be accessed by components of the host device via referenceable logical addresses. A memory controller may control operation of the memory and/or act as an intermediary device between the memory and the host device. In this way, when the memory receives a command from the host device, the command may include an instruction (e.g., read instruction, write instruction) and an indication of a logical address (e.g., a string of bits that indicate a location in memory that the component of the host device desires to access). The memory controller, after receiving the command, may reference a logical-to-physical translation table (L2P table) to determine the physical address that corresponds to the logical address of the command, where the physical address is the physical location within the memory at which the host device desires to access with the command.

Over time, some physical addresses of the memory may be accessed more often than other physical addresses of the memory. Unequal access distributions and/or uneven access patterns of accessing the memory may age some portions of the memory at a relatively faster rate than other portions of the memory. Uneven aging of the memory is generally undesirable since it may shorten a lifespan of a device and operations to even aging of the memory (e.g., evening access to the memory) may be referred to as “wear leveling” operations.

As described herein, to compensate for memory access patterns, such as to reduce uneven wear from uneven memory accesses and/or to improve a total duration of time used to process memory commands, the memory controller may adjust the L2P table based on commands issued by the host device. For example, the memory controller may adjust the L2P table with consideration for physical addresses that are accessed relatively more often than other physical addresses and/or with consideration for logical addresses that are commonly access sequential, or a duration of time subsequent to each other such that processing of a first command is still ongoing as to delay an initiation of processing of the subsequent command. By adjusting the L2P table based on address access patterns (e.g., traffic patterns), the memory controller may preemptively reduce or eliminate uneven wear and promote wear leveling and/or may improve speeds of performing memory operations (e.g., by increasing a number of memory accesses that may be performed in parallel). In some embodiments, the memory controller may also consider performance when adjusting the L2P table to improve (e.g., make more even) physical address access distributions and to improve wear leveling (e.g., make accesses more equal in number).

In this way, the L2P translation may be used to improve performance of a memory system (e.g., reduce a time used to perform memory operations). Since the L2P table provides the ability to store data in arbitrary physical locations in memory while the data may still be in contiguous logical address space, the L2P table may be leveraged to optimize and/or improve memory access patterns. In some cases, an optimal data storage pattern is memory access dependent, thus each software application of a computing system (e.g., each software application that has or uses access to the memory system) may have its own optimal pattern. Thus, in some embodiments, the memory system and/or the computing system may analyze software application access of the memory system to determine traffic patterns. Through deployment of deep learning algorithms, the traffic patterns may be used to generate L2P translation tables designed to improve access of the memory system based on actual access tendencies of the software application.

In some cases, a L2P table may be generated that represents an optimum behavior or relatively improved performance for multiple software applications. The L2P table generated based on traffic patterns for two or more software applications may be used and/or accessed as a default L2P table for the memory system. By using L2P tables adjusted based on traffic patterns of software application, performance of the memory system may improve since logical addresses that are relatively frequently accessed subsequent to one another may be defined to reference physical addresses in different banks. These L2P tables may also be used to manage wear levelling, such as by distributing memory access across one or more memory banks. Furthermore, it is noted that since these wear levelling algorithms modify the L2P table during operation of the memory system to optimize for wear levelling and/or expected sequence of memory accesses, memory operations do not need to be delayed while these determinations are being performed.

To help illustrate,FIG. 1depicts an example of a computing system10, which includes one or more remote computing devices12. As in the depicted embodiment, the remote computing devices12may be communicatively coupled to the one or more client devices14via a communication network16. It should be appreciated that the depicted embodiment is merely intended to be illustrative and not limiting. For example, in other embodiments, the remote computing devices12may be communicatively coupled to a single client device14or more than two client devices14. Furthermore, depending on the computing system10, the memory controller34may not be just on the memory module26. In this way, depicted is a generic use of the described techniques where the memory controller34is wholly on the memory module26. However, other examples may include a memory controller without a memory module and/or may use a processing circuit24as the memory controller34.

In any case, the communication network16may enable data communication between the client devices14and the remote computing devices12. In some embodiments, the client devices14may be physically remote (e.g., separate) from the remote computing devices12, for example, such that the remote computing devices12are located at a centralized data center. Thus, in some embodiments, the communication network16may be a wide area network (WAN), such as the Internet. To facilitate communication via the communication network16, the remote computing devices12and the client devices14may each include a network interface18.

In addition to the network interface18, a client device14may include input devices20and/or an electronic display22to enable a user to interact with the client device14. For example, the input devices20may receive user inputs and, thus, may include buttons, keyboards, mice, trackpads, and/or the like. Additionally or alternatively, the electronic display22may include touch sensing components that receive user inputs by detecting occurrence and/or position of an object touching its screen (e.g., surface of the electronic display22). In addition to enabling user inputs, the electronic display22may facilitate providing visual representations of information by displaying a graphical user interface (GUI) of an operating system, an application interface, text, a still image, video content, or the like.

As described above, the communication network16may enable data communication between the remote computing devices12and one or more client devices14. In other words, the communication network16may enable user inputs to be communicated from a client device14to a remote computing device12. Additionally or alternatively, the communication network16may enable results of operations performed by the remote computing device12based on the user inputs to be communicated back to the client device14, for example, as image data to be displayed on its electronic display22.

In fact, in some embodiments, data communication provided by the communication network16may be leveraged to make centralized hardware available to multiple users, such that hardware at client devices14may be reduced. For example, the remote computing devices12may provide data storage for multiple different client devices14, thereby enabling data storage (e.g., memory) provided locally at the client devices14to be reduced. Additionally or alternatively, the remote computing devices12may provide processing for multiple different client devices14, thereby enabling processing power provided locally at the client devices14to be reduced.

Thus, in addition to the network interface18, the remote computing devices12may include processing circuitry24and one or more memory modules26(e.g., sub-systems) communicatively coupled via a data bus28. In some embodiments, the processing circuitry24and/or the memory modules26may be implemented across multiple remote computing devices12, for example, such that a first remote computing device12includes a portion of the processing circuitry24and the first memory module26A, while an Mth remote computing device12includes another portion of the processing circuitry24and the Mth memory module26M. Additionally or alternatively, the processing circuitry24and the memory modules26may be implemented in a single remote computing device12.

In any case, the processing circuitry24may generally execute instructions to perform operations, for example, indicated by user inputs received from a client device14. Thus, the processing circuitry24may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof. In some embodiments, the processing circuitry24may additionally perform operations based on circuit connections formed (e.g., programmed) in the processing circuitry24. Thus, in such embodiments, the processing circuitry24may additionally include one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or any combination of suitable processing devices.

Additionally, a memory module26may provide data storage accessible to the processing circuitry24. For example, a memory module26may store data received from a client device14, data resulting from an operation performed by the processing circuitry24, data to be input to the operation performed by the processing circuitry24, instructions executable by the processing circuitry24to perform the operation, or any combination thereof. To facilitate providing data storage, a memory module26may include one or more memory devices30(e.g., chips or integrated circuits). In other words, the memory devices30may each include a tangible, non-transitory, computer-readable medium that stores data accessible to the processing circuitry24.

Since hardware of the remote computing devices12may be utilized by multiple client devices14, at least in some instances, a memory module26may store data corresponding to different client devices14. In some embodiments, the data may be grouped and stored as data blocks32. In fact, in some embodiments, data corresponding with each client device14may be stored as a separate data block32. For example, the memory devices30in the first memory module26A may store a first data block32A corresponding with the first client device14A and an Nth data block32N corresponding with the Nth client device14N. One or more data blocks32may be stored within a memory die of the memory device30.

Additionally or alternatively, in some embodiments, a data block32may correspond to a virtual machine (VM) provided to a client device14. In other words, as an illustrative example, a remote computing device12may provide the first client device14A a first virtual machine via the first data block32A and provide the Nth client device14N an Nth virtual machine via the Nth data block32N. Thus, when the first client device14A receives user inputs intended for the first virtual machine, the first client device14A may communicate the user inputs to the remote computing devices12via the communication network16. Based at least in part on the user inputs, the remote computing device12may retrieve the first data block32A, execute instructions to perform corresponding operations, and communicate the results of the operations back to the first client device14A via the communication network16.

Similarly, when the Nth client device14N receives user inputs intended for the Nth virtual machine, the Nth client device14N may communicate the user inputs to the remote computing devices12via the communication network16. Based at least in part on the user inputs, the remote computing device12may retrieve the Nth data block32N, execute instructions to perform corresponding operations, and communicate the results of the operations back to the Nth client device14N via the communication network16. Thus, the remote computing devices12may access (e.g., read and/or write) various data blocks32stored in a memory module26.

To facilitate improving access to stored data blocks32, a memory module26may include a memory controller34that controls storage of data in its memory devices30. In some embodiments, the memory controller34may operate based on circuit connections formed (e.g., programmed) in the memory controller34. Thus, in such embodiments, the memory controller34may include one or more application-specific integrated circuits (ASICs), one or more field programmable logic gate arrays (FPGAs), or any combination of suitable processing devices. In any case, as described above, a memory module26may include memory devices30that use different memory types, for example, which provide varying tradeoffs between data access speed and data storage density. Thus, in such embodiments, the memory controller34may control data storage across multiple memory devices30to facilitate leveraging the various tradeoffs, for example, such that the memory module26provides fast data access speed as well as high data storage capacity.

To help illustrate,FIG. 2depicts an example of a memory module26including different types of memory devices30. In particular, the memory module26may include one or more non-volatile memory devices30and one or more volatile memory devices30. In some embodiments, the volatile memory devices30may be dynamic random-access memory (DRAM) and/or static random-access memory (SRAM). In other words, in such embodiments, the memory module26may include one or more DRAM devices (e.g., chips or integrated circuits), one or more SRAM devices (e.g., chips or integrated circuits), or any combination of suitable memory devices.

Additionally, in some embodiments, the non-volatile memory devices30may be flash (e.g., NAND) memory, phase-change (e.g., 3D XPoint™) memory, and/or FeRAM. In other words, in such embodiments, the memory module26may include one or more NAND memory devices, one or more 3D XPoint™ memory devices, one or more FeRAM memory devices, or any combination of suitable memory devices. In fact, in some embodiments, the non-volatile memory devices30may provide storage class memory (SCM), which, at least in some instance, may facilitate reducing implementation associated cost, for example, by obviating other non-volatile data storage devices in the computing system10.

In any case, in some embodiments, the memory module26may include the memory devices30on a flat (e.g., front and/or back) surface of a printed circuit board (PCB). To facilitate data communication via the data bus28, the memory module26may include a bus interface44(bus I/F). For example, the bus interface44may include data pins (e.g., contacts) formed along an (e.g., bottom) edge of the printed circuit board. Thus, in some embodiments, the memory module26may be a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or the like.

Additionally, in some embodiments, the bus interface44may include logic that enables the memory module26to communicate via a communication protocol of the data bus28. For example, the bus interface44may control timing of data output from the memory module26to the data bus28and/or interpret data input to the memory module26from the data bus28in accordance with the communication protocol. Thus, in some embodiments, the bus interface44may be a double data rate fourth-generation (DDR4) interface, a double data rate fifth-generation (DDR5) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile dual in-line memory module (e.g., NVDIMM-P) interface, a cache coherent interconnect for accelerators (CCIX) interface, or the like.

In any case, as described above, a memory controller34may control data storage within the memory module26, for example, to facilitate improving data access speed and/or data storage efficiency by leveraging the various tradeoffs provided by memory types of the memory module26. Thus, as in the depicted example, the memory controller34may be coupled between the bus interface44and the memory devices30via one or more internal buses37, for example, provided as conductive traces formed on the printed circuit board. For example, the memory controller34may control whether a data block32is stored in the memory devices30. In other words, the memory controller34may transfer a data block32from a first memory device30into a second memory device30or vice versa.

To facilitate data transfers, the memory controller34may include buffer memory46, for example, to provide temporary data storage. In some embodiments, the buffer memory46may include static random-access memory (SRAM) and, thus, may provide faster data access speed compared to the volatile memory devices30and the non-volatile memory devices30. The buffer memory46may be DRAM or FeRAM in some cases. Additionally, to facilitate accessing stored data blocks32, the memory module26may include an logical-to-physical address translation table (L2P table) and/or other parameters stored in the buffer memory46, a non-volatile memory device (e.g., a portion of memory devices30), a volatile memory device (e.g., a portion of memory devices30), a dedicated address map memory device (e.g., a portion of memory devices30), or any combination thereof. The other parameters may include a physical experience table that stores parameters and/or data related to operation of the memory module26and/or one or more components of the computing system10.

In addition, the remote computing device12may communicate with a service processor and/or a service bus included in or separate from the processing circuitry24and/or the data bus28. The service processor, processing circuitry24, and/or the memory controller34may perform error detection operations and/or error correction operations (ECC), and may be disposed external from the remote computing device12such that error detection and error correction operations may continue if power to the remote computing device12is lost. For simplicity of description, the operations of the service processor are described as being included in and performed by the memory controller34, but it should be noted that in some embodiments the error correction operations or data recovery operations may be employed as functions performed by the service processor, processing circuitry24, or additional processing circuitry located internal or external to the remote computing device12or the client device14.

The memory module26is depicted inFIG. 2as a single device that includes various components or submodules. In some examples, a remote computing device12may include one or several discrete components equivalent to the various devices, modules, and components that make up the memory module26. For instance, a remote computing device12may include non-volatile memory, volatile memory, and a controller positioned on one or several different chips or substrates. In other words, the features and functions of the memory module26need not be employed in a single module to achieve the benefits described herein.

As described above, the memory module26may store information as data in the data blocks32. Die48of the memory module26may store the data blocks32. The data blocks32may be stored in one portion50of the die48or across multiple portions50. The portions50may store any amount of bits, and thus may be designed for a particular application of the memory module26. As an example, a portion50of memory may store 512 megabits (MB). In this way, a portion50of memory may be considered a memory cell, a memory bank, a memory partition, a portion of a memory module26, an entire memory module26, or the like. As depicted, however, for ease of discussion, the portion50may be a portion of memory that is considered smaller than a portion of memory allocated as the die30.

When the processing circuitry24requests access to data stored in the memory module26, the processing circuitry24may issue a command. The command may include an instruction to perform a read operation, such as to operate the memory controller34to facilitate the retrieval of information stored in one of the portions50. Sometimes, the command includes an instruction to perform a write operation, such as to operate the memory controller34to facilitate the storage of information in one of the portions50. Other commands may be used to instruct the memory controller34to perform other operations.

Over time, some physical addresses of the memory may be accessed more often than other physical addresses of the memory which may age some portions of the memory at a relatively faster rate than other portions of the memory. To elaborate,FIG. 3is a block diagram of the memory module ofFIG. 2after a duration of time. The memory module26ofFIG. 3may be affected by relatively uneven aging and/or uneven memory accesses, which is illustrated by the use of different shading to emphasize relatively more or relatively less accesses to the portions50. For example, the memory device30B was accessed relatively more than the memory device30D, and thus the portions50of the memory device30B may experience component aging at a faster rate than the portions50of the memory device30D.

To compensate for under-optimized memory accesses, the memory controller34may adjust the L2P table based on commands issued by the host device (e.g., historical datasets that are indicative of traffic patterns associated with accesses of the memory controller34). For example, the memory controller34may adjust the L2P table with consideration for physical addresses that are accessed relatively more often than other physical addresses and/or for consideration for physical addresses accessed subsequent to other physical addresses relatively more often. By adjusting the L2P table based on the most frequently accessed physical addresses, the memory controller34may preemptively reduce or eliminate uneven aging and/or uneven memory accesses since the adjusted L2P table may make the traffic patterns between portions of memory relatively more even or equal. Additionally or alternatively, by adjusting the L2P table based on frequent subsequently accessed physical addresses, addresses that are expected to be accessed subsequent to each other may be used to address physical locations of memory that are independent from each other, such as different memory banks and/or different portions of memory.

An example of the controller34operating to compensate for under-optimized memory access patterns is shown inFIG. 4.FIG. 4is an illustration of the memory controller34operating to adjust an original logical-to-physical table (L2P table) to preemptively compensate for frequent sequentially accessed addresses (e.g., memory access patterns). The memory controller34may receive as inputs various traffic datasets60(60A,60B,60C) and a current L2P table62. The current L2P table62may be an original L2P table or may be a previously adjusted L2P table that the memory controller34is currently referencing for memory operations (e.g., read operations, write operations).

The memory controller34may use the traffic datasets60to dynamically alter the current L2P table62into a new L2P table64. To do so, the memory controller34may analyze one or more of the traffic datasets60. From the analysis, the memory controller34may learn which portions of the memory module26are frequency accessed sequential to each other. For example, the memory controller34may analyze one of the traffic datasets60to determine that a first portion50is frequently accessed right before a second portion50is accessed (e.g., sequentially accessed a threshold amount of times). In response to the memory controller34identifying portions of the memory module26that are accessed more often by a threshold amount of accesses and/or accessed sequentially by a threshold amount of accesses, the memory controller34may generate the new L2P table64to compensate for these access patterns.

The memory controller34may alter L2P mapping of the memory module26to compensate for any undesired access patterns. For example, the memory controller34may change physical locations addressed by subsequently accessed logical address to reference locations on independently operating portions of memory (e.g., different memory banks, portions of memory on different memory die50). The memory controller34may interchange memory addresses, such that one or more frequently accessed addresses are replaced by less frequently accessed addresses, for example, the most frequently accessed address may be replaced by the least frequently accessed address, the second most accessed address may be replaced by the second least frequently accessed address, and so on.

Portions50may be interchanged in some cases, but it should be understood that undesired memory access patterns may be compensated for at any suitable granularity of memory access, such as at the memory die48level. In some cases, the memory controller34may not be the controller that adjusts the memory access patterns in response to traffic datasets60. When the controller adjusting the memory access patterns is the processing circuitry24, or some other system-level controller (e.g., as opposed to memory module-level memory controller34), the current L2P table62may be adjusted to compensate for undesired access patterns between memory modules26.

Each of the traffic datasets60may include real-time traffic data, test traffic data, historical traffic data, or the like. In this way, each of the traffic datasets60may be representative traffic samples for a given workload. Real-time traffic data may be information associated with memory read and write operations that is stored and analyzed by the memory controller34in real-time, or while the memory read and write operations are ongoing. Memory transactions (e.g., individual read or write operation occurrences) may be recorded by the memory controller34over time until a particular amount of memory transaction data is recorded to form a traffic dataset60(e.g.,60A,60B,60C). The particular amount of memory transaction data may be defined by a threshold, such that the memory controller34monitors and records the memory transactions until a number of memory transactions is greater than or equal to a threshold amount of memory transactions. In response to the number of memory transactions being greater than or equal to the threshold amount, the memory controller34may associate the memory transactions as part of a traffic dataset60. In this way, the traffic dataset60may indicate real memory operations. When using test traffic data, memory transactions may be simulated or sample sets of data based on real memory transactions or typically expected memory traffic patterns may be used. Furthermore, in some cases, data values which may or may not mimic or represent real memory traffic patterns may be used as the test traffic data, or as typically expected memory traffic patterns. Furthermore, in some cases, the memory controller34may store memory transaction data over time, and use the stored memory transaction data as the traffic datasets60at a later time, for example several days or months later.

In some embodiments, the memory controller34may also consider performance when adjusting the L2P table to improve physical address access distributions (e.g., reduce an amount of sequential accesses to a same portion50of memory). For example, the memory controller34may use a deep learning operation that uses read or write operation times as a cost (e.g., input) and the new L2P table64as a knob (e.g., variable) to adjust to optimize the cost. An example of the deep learning operation may include use of a long short-term memory (LSTM) artificial recurrent neural network. In this way, the memory controller34may test various eligible address assignments before selecting a final address assignment combination to be output as the final L2P table64. The memory controller34may determine an arrangement of address assignments that minimizes the cost while maximizing the reassignment of some addresses (in particular, the addresses that relatively more frequently access one-after-another or a duration of time sequentially such that processing of the second command waits until processing of the first command finishes). In this way, the memory controller34may consider memory access latencies (e.g., cost defined as read or write operations times) and reassignment percentages (e.g., a percentage of overused or relatively more sequentially-accessed portions of memory reassigned to relatively less sequentially-accessed portions of memory) when reassigning a physical address to a logical address. For example, the memory controller34may consider a comparison between a total duration of time used to perform one or more read and/or write operations for a first L2P table adjustment option and for a second L2P table adjustment option to determine which resulting L2P table corresponds to a more suitable adjustment and/or optimization.

When the memory controller34uses the deep learning operation, the memory controller34may train the final L2P table64on one or more traffic datasets60. A subset of the traffic data of the traffic datasets60may be reserved for testing of the trained L2P table64, such as to verify performance of the adjusted logical-to-physical address assignments. Performance of the trained L2P table64may be tested to see how access speeds or access distributions changed after the training or adjustment. For example, the memory controller34may verify performance of the new L2P table64(e.g., trained L2P table64) by comparing performance results of the new L2P table64to previous performance results of the current L2P table62or to a default setting of the logical-to-physical assignments (e.g., an original L2P table for the memory controller34).

Changes may be applied to the new L2P table64over time and/or as part of an iterative process, such as by adjusting a subset of logical addresses from a set of logical addresses to be adjusted. In this way, the memory controller34may perform one or more rounds of improvement to the current L2P table62such that the new L2P table64becomes incrementally improved over time. For example, a first current L2P table62may be adjusted and output as a new L2P table64, which is used at a next iteration as a second current L2P table62, adjusted, and output as a subsequent new L2P table64. Any number of iterations may be performed by the memory controller34to adjust the current L2P table62to compensate for sequential access patterns. In some cases, a threshold number of iterations may be defined and used to control a maximum number of iterations to be performed by the memory controller34.

Since the memory controller34is monitoring accesses and access patterns, the memory controller34may preemptively compensate for memory access patterns before the memory access patterns affect components of the computing system10. For example, when the memory controller34adjusts the L2P table before the undesired access patterns affect the memory module26, sequential accesses may be preemptively (e.g., proactively) prevented since access to the portions of memory is proactively compensated. Preemptive adjustment of the L2P table may occur in response to the memory controller34determining that queued commands correspond to non-independent portions of memory and determining to adjust the L2P table to change, for example, a location in memory where to write data as to be able to be performed simultaneous to another memory access.

To elaborate on example operations of the memory controller34,FIG. 5is a flowchart of a process76to preemptively compensate for memory access patterns. The memory controller34is described below as performing the process76, but it should be understood that any suitable processing circuitry may additionally or alternatively perform the process76. Furthermore, although the process76is described below as being performed in a particular order, it should be understood that any suitable order may be used to perform individual operations of the process76.

At block78, the memory controller34may receive a training dataset. The training dataset may include one or more traffic datasets60and/or one or more portions of one or more traffic datasets60. As described above, the traffic datasets60may include real-time traffic data, test traffic data, historical traffic data, or the like. In some cases, the memory controller34may divide the traffic datasets60and/or portions of data of the traffic datasets60into training datasets and into testing datasets.

At block80, the memory controller34may use the training dataset and/or the traffic datasets60to determine one or more sequentially accessed logical addresses. The memory controller34may use thresholds to identify a trend of expected sequentially accessed logical addresses. For example, the memory controller34may use a threshold amount of memory accesses to determine when a sequential access pattern occurs enough times to correspond to an expected (e.g., preemptively anticipated) sequential access pattern since a relatively few amount (e.g., less than the threshold amount of occurrences) of sequential accesses of two or more logical addresses may not necessarily benefit from a reassignment or adjustment to the L2P table. The threshold may define a threshold number of memory accesses relative to other amounts of memory accesses. In this way, the memory controller34may identify a portion of the memory module26that is accessed a number of times greater than a threshold amount relative to a different portion of memory, and thus determine that a first portion of memory (e.g., first portion50on same die48) is accessed sequential to an access of a second portion of memory (e.g., second portion50on same die48).

At block82, the memory controller34may generate a new L2P table64to compensate for the sequentially accessed logical addresses. In this way, the memory controller34may adjust the logical address to physical address assignments to cause sequentially referenced logical addresses to translate to physical addresses associated with independent portions of memory (e.g., different memory banks, different die48, different portions50). As discussed above, the memory controller34may interchange physical addresses assigned to logical addresses via the L2P table such that portions50, die48, and/or memory devices30are accessed in a different pattern according to the same logical addressing. The memory controller34may adjust the current L2P table62to generate the new L2P table64and/or generate a new L2P table64independent of an existing data structure storing the current L2P table62. The memory controller34, in some cases, may generate a set of eligible new L2P tables64and use operations of block84to evaluate the set of eligible new L2P tables64for selection at block86. To generate each of the set of eligible new L2P tables64, the memory controller34may systemically change one or more aspects (e.g., variables) of a first new L2P table64to test different options for the new L2P table64. In this way, the memory controller34may determine a suitable arrangement of the L2P table that minimizes read or write latencies while improving distributions of logical addresses relatively more frequently accessed of the memory (e.g., reassigning to physical addresses corresponding to independent portions of memory). Thus, the memory controller34may adjust the current L2P table62to test various eligible address assignments (e.g., set of eligible new L2P tables64) before selecting a final address assignment combination to be output as the final L2P table64. For example, in response to determining that the first portion50of memory is accessed sequential to the access of the second portion50of memory, the memory controller34may generate a multiple logical-to-physical tables that each include an assignment of a logical address originally corresponding to a physical address of the first portion50of memory to now correspond to a physical address of a third portion50of memory (e.g., a portion of memory independent from the second portion50of memory).

At block84, the memory controller34may evaluate performance of the set of eligible new L2P tables64. The memory controller34may test each of the set of eligible new L2P tables64using a testing dataset (e.g., one or more portions of the traffic datasets60) to obtain performance metrics. Each performance metric for each of the set of eligible new L2P tables64may be compared to a corresponding performance metric for the current L2P table62or a default setting for the memory controller34. The comparison between the performance metrics may yield performance improvement metrics that indicate whether the performance did improve or did not improve (e.g., yielded faster memory accesses, yielded equal memory access speeds with relatively more even access distributions, yielded reduced read or write latencies). A performance improvement metric may indicate an improvement in performance of a particular L2P table of the set of eligible new L2P tables64. In this way, the memory controller34may evaluate the performances of the set of eligible new L2P tables64based at least in part on the performance improvement metrics to determine a suitable combination of changes to the current L2P table62that yield desirable or maximized performances. In some cases, the memory controller34may use a deep learning operation (e.g., LSTM) that uses read or write operation times (e.g., read or write latencies) as a cost and the new L2P table64as a knob (e.g., variable) to adjust to optimize the cost.

At block86, the memory controller34may select a final new L2P table64from the set of eligible new L2P tables64and may use the final new L2P table64in the buffer memory46. Thus, a L2P table may be selected from the multiple L2P tables generated and tested at block84to evaluate memory access latencies for each of the multiple L2P tables. The current L2P table62, in some cases, may be retained in memory as a backup L2P table and/or for future reference. The new L2P table64may be written to the buffer memory46to overwrite the current L2P table62. In this way, the memory controller34replaces the current L2P table62and uses the new L2P table64for future memory accesses (e.g., memory controller34uses the new L2P table64). For example, the memory controller34may store a first L2P table (e.g., current L2P table62) as an original logical-to-physical table in the buffer memory46, generate a second L2P table (e.g., new L2P table64) using the first L2P table after adjusting the first L2P table, such as at block82, and may write over the first L2P table in the buffer memory46with the second L2P table such that the memory controller34uses the second L2P table when performing logical-to-physical address translations.

It is noted that although, inFIG. 1, the client devices14are depicted as communicatively coupled to the remote computing devices12, in some embodiments, the systems and methods described above may be used in a memory controller34of the client device14. The techniques described herein may be used in combination with a variety of memory types and computing structures to achieve the benefits described herein.

In some cases, the memory controller34may use traffic datasets60that include an indication of a workload type. In this way, resulting new L2P tables64may be selected based at least in part on the workload type that operates the memory controller34. For example, some memory (e.g., memory chips) have a number of memory banks able to operate in parallel, such as sixteen memory banks that sometimes operate in parallel. The current L2P tables62for different workloads may be optimized, or designed, to increase the probability that successive commands are for different memory banks, and thus may be executed in parallel, yielding performance improvements of the memory (e.g., faster speed of completing memory transactions). Examples of workflows may include different software applications used by a same computing device and that access, during execution of the software application, the memory module26. When designing L2P tables for a particular workload, logical addresses may originally reference a physical address of a portion50of memory disposed or located within a same memory die48or a same memory device30. During an example workflow, a memory controller34may sequentially access logical addresses that reference portions50of memory not able to be processed in parallel (e.g., same portions of memory, same memory die48, same memory device30. These sequential access patterns involving the logical addresses may be identified, and the logical addresses may be reassigned physical addresses corresponding to portions50disposed on or within different memory die48or different memory devices30, such that the logical addresses are assigned to physical addresses referencing independent portions of memory. In this way, the workload that sequentially accesses the logical addresses may cause the memory controller34to access the different portions50of memory in parallel since the physical addresses reference portions50of memory able to be processed in parallel (e.g., since the physical addresses reference portions50of memory that operate independent). In some embodiments, a workload type may be identified to the memory controller34, which is able to preload the selected new L2P table64in response to the type of workload. For example, L2P tables64may be stored and loaded by a computing device (e.g., memory controller34of the computing device) in response to a corresponding software application being executed on the computing device.

In some embodiments, the refinement of a current L2P table62(e.g., to generate a new L2P table64) may be performed after a time of manufacturing during operation of the computing system10. In this way, the current L2P table62may update over time and over the device life of the computing system10. In some cases, the refinement of the L2P table may be performed while the computing system10is in a reduced power mode, is idle, is offline, or is otherwise not accessing the memory module26, such that the new L2P table64may be used by the memory controller34without interruption to an ongoing memory process. For example, operations ofFIG. 5may be performed by the memory controller34when the memory controller34is not in the middle of performing another memory operation (e.g., read operation, write operation, refresh operation).

In some embodiments, determining relatively more accessed portions of the memory module26and/or determining a final adjustment to the L2P table may include the memory controller34performing a difference analysis to identify differences in access amounts that are greater than a threshold amount of accesses. For example, a first portion50may have been accessed 10 times, a second portion50may have been accessed 50 times, and the threshold amount of accesses may be a difference equaling 15 accesses. Since the difference between accesses of the first portion50and the second portion50is 40 and the threshold amount of accesses corresponds to a difference equaling 15 accesses, the memory controller34may identify the second portion50as relatively more overused. In this way, the memory controller34may sometimes adjust the logical address to physical address assignments to cause the less accessed portions of the memory module26to be accessed relatively more frequent.

Additionally or alternatively, in some embodiments, identifying overused portions of the memory module26, at block80ofFIG. 5, may include identifying physical addresses of the overused portions and/or relatively less used portions of the memory module26. For example, the memory controller34may determine that the first portion50is more frequently accessed than the second portion50at least in part by analyzing a first number of memory transactions (e.g., memory read operation, memory write operation, memory refresh operation) involving the first portion50during a time period, analyzing a second number of memory transactions involving the second portion50during the same time period, and determining that the first number is greater than the second number. The time period may be for the same duration of time, such that the time period shares a starting and ending time, and/or the time period may be a same duration of time relative to a start time (e.g., equal durations periods of time that do not necessarily start at a same start time). The time periods may be a monitoring period to use when comparing accesses to portions of memory and/or analyzing traffic patterns associated with memory accesses. It is noted that in some embodiments, counters may be used to count physical address accesses. A counter may count up to a threshold value of accesses or may count down from the threshold value of accesses in response to a particular physical address being accessed. Any suitable type and number of counter may be used, for example, each address may correspond to a counter and/or sets of addresses may correspond to a counter.

Technical effects of the present disclosure may include improving memory operations by compensating for memory access patterns (e.g., uneven access patterns, sequential logical address access patterns) of a memory. A memory controller may identify logical addresses that are frequently accessed sequential to each other and reassign, for the logical address corresponding to the identified sequentially accessed logical addresses, to a different physical address. This may cause the logical address to be reassigned a physical address corresponding to a portion of memory that is less used and/or that correspond to independent portions of memory, thereby permitting parallel memory access operation of the independent portions of memory. The reassignment of logical addresses to new or adjusted physical addresses may be stored in a new and/or updated L2P table. A memory controller managing accesses to memory according to the new and/or updated L2P table may improve performance of the memory system.

With these technical effects in mind, multiple memory devices may be included on a memory module, thereby enabling the memory devices to be communicatively coupled to the processing circuitry as a unit. For example, a dual in-line memory module (DIMM) may include a printed circuit board (PCB) and multiple memory devices. Memory modules respond to commands from a memory controller communicatively coupled to a client device or a host device via a communication network. Or in some cases, a memory controller may be used on the host-side of a memory-host interface; for example, a processor, microcontroller, FPGA, ASIC, or the like may each include a memory controller. This communication network may enable data communication there between and, thus, the client device to utilize hardware resources accessible through the memory controller. Based at least in part on user input to the client device, processing circuitry of the memory controller may perform one or more operations to facilitate the retrieval or transmission of data between the client device and the memory devices. Data communicated between the client device and the memory devices may be used for a variety of purposes including, but not limited to, presentation of a visualization to a user through a graphical user interface (GUI) at the client device, processing operations, calculations, or the like. Thus, with this in mind, the above-described improvements to memory controller operations and memory writing operations may manifest as improvements in visualization quality (e.g., speed of rendering, quality of rendering), improvements in processing operations, improvements in calculations, or the like.