High density ReRAM integration with interconnect

A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

BACKGROUND

The present invention relates generally to the field of integrated circuits, and more particularly to formation of a logic circuit and ReRAM array.

BRIEF SUMMARY

DETAILED DESCRIPTION

As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrations or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. The terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of the filing of the application. For example, about can include a range of ±8%, or 5%, or 2% of a given value. In another aspect, the term “about” means within 5% of the reported numerical value. In another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

Various process used to form a micro-chip that will packaged into an integrated circuit (IC) fall in four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etching process (either wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implant dopants. Films of both conductors (e.g. aluminum, copper, etc.) and insulators (e.g. various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage.

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Embodiments of the invention are generally directed to an apparatus and method for concurrently forming a logic circuit and a crossbar ReRAM array on the same device.

Resistive random-access memory (ReRAM) memory is integrated in higher level of BEOL interconnect, and it is desired to incorporate ReRAM into lower BEOL level. ReRAM stack typically includes TiN electrodes for compatibility with CMOS flow. Incorporation of ReRAM in Cu Damascene process requires additional metal layer (e.g. TaN) on top of ReRAM stack for protection during TiN hard mask removal. In addition, sidewall protection is needed since dimensions of Cu Via are typically larger than those of ReRAM stack pillars. A conventional spacer is damaged during a Via open process and weak spot for TiN wet etching can be created.

ReRAM is considered as a promising technology for electronic synapse devices or memristor for neuromorphic computing as well as high-density and high-speed non-volatile memory application. In neuromorphic computing applications, a resistive memory device can be used as a connection (synapse) between a pre-neuron and post-neuron, representing the connection weight in the form of device resistance. Multiple pre-neurons and post-neurons can be connected through a crossbar array of ReRAMs, which naturally expresses a fully connected neural network.

A crossbar ReRAM structure comprises ReRAM stack sandwiched between lower and upper metal lines. A first metal liner is present between the lower metal line and an underlying layer. A second metal liner is present between the upper metal line and the ReRAM stack. However, there is no metal liner on the sidewalls of the ReRAM stack and there is no metal liner on the side walls of the lower metal line. A method of forming crossbar ReRAM structure comprises forming bottom metal layer and forming a ReRAM stack over bottom metal layer. The ReRAM stack and bottom metal layer are patterned into lines and a dielectric layer is formed to fill the space between the lines. A top metal layer is formed on top of the dielectric layer and the top metal layer is etched into a second set of lines. The second set of lines runs perpendicular to the lines comprised of the lower metal layer and the ReRAM stack.

FIG.1Aillustrates a top down view of the BEOL interconnect of a logic circuit100, in accordance with an embodiment of the present invention. The logic circuit100is located on the same substrate as the crossbar ReRAM array200and the logic circuit100is connected to the ReRAM array200. The following descriptions that contain the letter “A” in theFIGS.2-12number refers to cross section A as illustrated inFIG.1A. Cross section A is a perpendicular slice along three of the lower bars in the logic circuit100and a slice along the length of the upper bar.

FIG.1Billustrates a top down view of a ReRAM array, in accordance with an embodiment of the present invention. The crossbar ReRAM array200is on the same substrate as the logic circuit100. The following descriptions that contain the letter “B, C, or D” in theFIGS.2-12number refers to cross section B, C, or D as illustrated inFIG.1B. Cross section B is slice along one of the upper pillars that runs perpendicular atop of a plurality of lower pillars. Cross section C is slice along one of the lower pillars that runs perpendicular below a plurality of upper pillars. Cross section D is a slice along the space between two of the lower pillars where a plurality of the upper pillars cross.

FIG.2Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention.

An underlying device105serves as the base for the logic circuit100. The underlying device105can consist of, for example, a substrate, a silicon wafer, a sapphire wafer, MOS device, CMOS device, BTJ device, diodes, resistors, capacitors, metal layers, dielectric layers, or any type of material for the logic circuit100to be fabricated on. The first metal liner110is formed on top of the underlying device105through appropriate deposition techniques. The material of the first metal liner110may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. The first metal layer115is formed on top of the first metal liner110through appropriate deposition techniques. The material of the first metal layer115may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer.

FIG.2Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention.

An underlying device205serves as the base for the ReRAM array200. The underlying device105can be, for example, a substrate, a silicon wafer, a sapphire wafer, MOS device, CMOS device, BTJ device, diodes, resistors, capacitors, metal layers, dielectric layers, or any type of material for the ReRAM array200to be fabricated on. The figures illustrate that the ReRAM array200and the logic circuit100are fabricated on same underlying device105,205. However, ReRAM array200and the logic circuit100may be fabricated on separate underlying devices105,205. The first metal liner210is formed on top of the underlying device105through appropriate deposition techniques. The material of the first metal liner210may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. The first metal layer215is formed on top of the first metal liner210through appropriate deposition techniques. The material of the first metal layer215may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer.

FIG.3Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention.FIG.3Billustrates cross section B of the ReRAM array during fabrication, in accordance with an embodiment of the present invention. The ReRAM stack is comprised of a plurality of layers that are formed on top of the first metal layer115,215during the same process. The ReRAM stack is composed of a first layer120,220, a second layer125,225, a third layer130,230, a fourth layer126,226, and a fifth layer121,221. The first layer120,220and the fifth layer121,221are composed of the same material, for example, TaN. The second layer125,225and the fourth layer126,226are composed of the same material for example TiN. The third layer130,230can be comprised of, for example, HfO2. These materials listed for the ReRAM stack are only meant to for illustrative purposes only and are not meant to be limiting. Any type of material that can be used to form a ReRAM stack can be utilized here.

FIG.4Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention. The ReRAM stack was formed uniformly across the logic circuit100and the ReRAM array200. ReRAM stack is removed from the logic circuit100region using appropriate etching process, since the ReRAM stack is not need in the logic circuit100. This is achieved by forming a patterning mask, such as optical planarization layer (OPL) over the devices, followed by lithography process to define the region where the ReRAM stack will be removed, followed by etching away the OPL and also the ReRAM stack in that region, and the first metal layer115is exposed after that.

FIG.4Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. As described in previous paragraph, the optical planarization layer235is not removed in ReRAM array region on top of the fifth layer221. The optical planarization layer235protects the ReRAM stack from being damaged as the ReRAM layers are being removed from the logic circuit100region.

FIG.5Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention. A hard mask140is formed on the top surface of first metal layer115. The material of the hard mask140may include, for example, SiO2, SiN, SiBCN, SiCO, SiC, or other suitable hard mask materials. The hard mask140is planarized by CMP to make the top of the hard mask140planar with the top of the fifth layer221of the ReRAM stack.

FIG.5Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. The optical planarization layer235is removed to expose the surface of the fifth layer221. After that, the hard mask140is deposited on top of the fifth layer221of the ReRAM stack. The combined height of the hard mask140and the ReRAM stack is higher than the top surface of the hard mask140located on the logic circuit100. Since the hard mask between the logic circuit100and the ReRAM array200are at different height it affects the downstream processing of the components. Therefore, a CMP process is applied to polish away the hard mask140material over the fifth layer221, such that the top surface of the fifth layer221is planar with the top surface of hard mask140.

FIG.6Aillustrates cross section A of the Logic array100during fabrication, in accordance with an embodiment of the present invention. Additional hard mask material is deposited on top of the hard mask140to allow the formation of a hard mask240on top of the ReRAM stack while maintaining the planar top surface between the logic circuit100the ReRAM array200. Therefore, the thickness of the hard mask140increases with the additional hard mask material.

FIG.6Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. A hard mark240is formed on top of the fifth layer221. The formation of hard mask240causes the thickness of the hard mask140to increase. Hard mask240is formed is needed on top of the ReRAM stack since the hard mask240is necessary for the patterning of the layers.

FIG.7Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention. The hard mask140is pattern to determine which portions of the logic circuit100that will be etched to form the desired pattern. The etching process can utilize any etching tech that will remove the desired layers at the specified locations in down to the underlying layer105. The etching process creates pillars (that extend into the foreground and background) of the multiple layers where each pillar is comprised of the first metal line110, the first metal layer115, and the hard mask140.FIG.7Aappears to give the impression that pillars only extend vertically, butFIG.7Aillustrates cross-section A of the logic circuit100.FIG.1Aillustrates that the three pillars extend a distance to and from the area of the cross-section A.

FIG.7Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. The hard mask240is pattern to determine which portions of the ReRAM array that will be etched to from the desired pattern. The etching process can utilize any etching tech that will remove the desired layers at the specified locations in down to the underlying layer205. The etching process creates pillars (that extend into the foreground and background) of the multiple layers where each pillar is comprised of the first metal line210, the first metal layer215, first layer220, second layer225, third layer230, fourth layer226, fifth layer221, and the hard mask240. A benefit from this design is that a metal liner is not formed on the sidewalls of the pillars, meaning there is not metal liner on the sidewalls of the ReRAM stack. By not having the metal linear in direct contact with the sidewalls of each of the layers of the ReRAM stack the resistance of the ReRAM may be better controlled. Furthermore, by not having the metal liner, the damage to the underlying layers caused by the formation and patterning of the metal liner can be avoided. Furthermore, the ReRAM stack is self-aligned with the first metal layer215, since the ReRAM stack was formed directly on first metal layer215prior to patterning of the pillars.

FIG.8Aillustrates cross section A of the logic array100during fabrication, in accordance with an embodiment of the present invention. A dielectric layer145is deposited on the logic circuit100. The dielectric layer145will form on top each of the pillars during the deposition process. The dielectric layer145is planarized by, for example, chemical mechanical planarization (CMP), to expose the top of hard mask140on each of the pillars. The dielectric layer145is in direct contact with the sidewalls of each of the pillars on the logic circuit100.

FIG.8Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. A dielectric layer245is deposited on the ReRAM array200to fill in the space between each of the pillars. The dielectric layer245is in direct contact with the sidewalls of each of the first metal layer215, the first layer220, the second layer225, the third layer230, the fourth layer226, and the fifth layer221. The dielectric layer245will form on top each of the pillars during the deposition process. The dielectric layer245is planarized by, for example, chemical mechanical planarization (CMP), to expose the top of hard mask240on each of the pillars. A benefit from this design is that a metal liner is not formed on the sidewalls of each of the pillars, which allows for the dielectric layer245to come into direct contact with the sidewalls of the ReRAM stack and the sidewalls of the first metal layer215.

FIG.9Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention. An optical planarization layer136is deposited on the top surface of the dielectric layer145and on top of the exposed hard mask140. Depending on the design of the logic circuit100, portions of the optical planarization layer136can be removed. The removal of these portions of the optical planarization layer136exposed the hard mask140. The exposed sections of hard mask140can be removed to expose the top surface of the first metal layer115, as illustrated byFIG.9A. By removing the hard mask140a channel is created by the dielectric layer145extending higher than the top of the first metal layer115. This channel allows for the extension of the second metal layer155to extend downwards to make a connection with the first metal layer215.

FIG.9Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. An optical planarization layer136is deposited on the top surface of the dielectric layer245and on top of the exposed hard mask240. The optical planarization layer136is removed to expose the underlying hard mask240sections and the top surface of the dielectric layer245. The exposed hard mask240is removed, as illustrated byFIG.9B. By removing the hard mask240a channel is created by the dielectric layer245extending higher than the top of the fifth layer221. These channels allow for the extension of the second metal layer255to extend downwards to make a connection with the ReRAM stack. Furthermore, these channels allow for the second metal layer255to aligned with the top of the exposed ReRAM stack.

FIG.10Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention. The optical planarization layer136is removed to expose the top surface of the dielectric layer145, and the top surface of the hard mask140that remains on some of the pillars. The thin liner layer150is formed on the top surface of the dielectric layer145, the top surface of the hard mask140, the sidewalls of the dielectric layer145where the hard mask140was removed, and on the top surface of the first metal layer115. Thus, the thin liner layer150lines the channel that was created by the removal of the hard mask140. The material of the thin liner layer150may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. A second metal layer155is formed on the top surface of the thin liner layer150. The second metal layer155extends downwards into the channel and makes an electrical connection with the first metal layer115through the thin liner layer150. The material of the second metal layer255may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer. The second metal layer155and the first metal layer115can be comprised of the same material or different material.

FIG.10Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. A thin liner layer250is deposited on the top surface of the dielectric layer245, the sidewalls of the dielectric layer245where the hard mask240was removed, and on the top surface of the fifth layer221. Thus, the thin liner layer250lines the channel that was created by the removal of the hard mask240. The material of the thin liner layer250may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. A second metal layer255is formed on the top surface of the thin liner layer250. The second metal layer255extends downwards into the channel and makes an electrical connection with the fifth layer221of the ReRAM stack through the thin liner layer250. The material of the second metal layer255may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer. The second metal layer255and the first metal layer215can be comprised of the same material or different material.

FIG.10Cillustrates cross section C of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. Cross section C of the ReRAM array200is perpendicular to cross section B as illustrated byFIG.1B. A thin liner layer250is deposited on the top surface of the fifth layer221. The material of the thin liner layer250may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. A second metal layer255is formed on the top surface of the thin liner layer250. The material of the second metal layer255may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer. The second metal layer255and the first metal layer215can be comprised of the same material or different material.

FIG.10Dillustrates cross section D of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. Cross section D of the ReRAM array200is parallel to cross section C. The dielectric layer245is formed directly on top of the underlying layer205, the thin liner layer250is formed on top of the dielectric layer245, and the second metal layer255is formed on top of the thin liner layer250.

FIG.11Aillustrates cross section A of the logic circuit100during fabrication, in accordance with an embodiment of the present invention. A hard mask141is formed on top of the second metal layer155. Based on the logic circuit100design, portions of the hard marks141, the second metal layer155and the thin liner layer150are removed.FIG.10Aillustrates that the right section is removed, which corresponds to the section along cross section A inFIG.1Athat does not have the second metal layer155.FIG.11Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. A hard mask241is formed along the top surface of the second metal layer255.FIG.11Cillustrates cross section C of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. The hard mask241is patterned and in the areas that are not patterned the material of the underlying layers are removed. The layers are removed down to the first metal layer215.FIG.11Cillustrates three pillars were created which corresponds to the three columns cross section C cuts across as illustrated byFIG.1B.FIG.11Dillustrates cross section D of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. The hard mask241is patterned and the underlying layers are removed. The layers are removed down to the dielectric layer245.FIG.11Cillustrates three pillars were created which corresponds to the three columns cross section D cuts across as illustrated byFIG.1B. The process steps shown inFIGS.11A-Dare done simultaneously so that there only one lithography step and one etching step.

FIG.12Aillustrates cross section A of the logic array100during fabrication, in accordance with an embodiment of the present invention. Additional dielectric layer145is formed on top of the exposed surfaces to fill in any of the areas. The dielectric layer145is CMP to remove the excess material and to create a planar top surface.FIG.12Billustrates cross section B of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention.FIG.12Cillustrates cross section C of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention.FIG.12Dillustrates cross section D of the ReRAM array200during fabrication, in accordance with an embodiment of the present invention. Additional dielectric layer245is formed on top of the exposed surfaces to fill in any of the areas. The dielectric layer245is CMP to remove the excess material and to create a planar top surface. The process steps shown inFIGS.12A-Dare done simultaneously so that there only one dielectric deposition step and only one CMP step.

The ReRAM stack formed by the process described above is aligned with the first metal layer215and the with the second metal layer255. Since the ReRAM stack is self-aligned with the first and second metal layer215and255, it allows for the ReRAM array200to be designed for different scales. Furthermore, since a metal liner is in direct or any type of contact with the sidewalls of the ReRAM stack allows for more control of the resistance of the ReRAM stack.

The above method describes the formation of the logic circuit100and the ReRAM array200occur on the same time on the same wafer. The two devices can be connected to each through with high density interconnect (not shown). This allows for the simplification of the fabrication process since the high-density interconnect can be fabricated at the same time as the logic circuit100and the ReRAM array200.