Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate dielectric film and thereafter applies a second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-44106, filed on Mar. 6, 2013; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

In some semiconductor memory devices, a ferroelectric field-effect transistor (FeFET) is used as a memory cell to cope with scaling of memory cells. Ferroelectric field-effect transistors can store data by inverting the polarization direction of a ferroelectric film.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate dielectric film and thereafter applies a second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage.

A semiconductor memory device according to embodiments will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

FIG. 1is a block diagram illustrating the schematic configuration of a semiconductor memory device according to the first embodiment.

InFIG. 1, this semiconductor memory device includes a memory cell array1, a row selection circuit2, a well potential setting circuit3, a source potential setting circuit4, a column selection circuit5, a data input/output buffer6, a control circuit7, and a sense amplifier circuit8.

In the memory cell array1, memory cells, which store data, are arranged in a matrix in a row direction and a column direction. A cell transistor in which a ferroelectric film is provided as a gate dielectric film can be used as a memory cell. One memory cell may store 1 bit of data or may perform multi-level recording to be able to store 2 or more bits of data.

The memory cell array1is divided into n (n is a positive integer) number of blocks B1to Bn. Each of the blocks B1to Bn can be configured by arraying a plurality of NAND cells in the row direction.

At the time of read, write, and erase operations of a memory cell, the row selection circuit2can select memory cells in the row direction in the memory cell array1. At the time of read, write, and erase operations of a memory cell, the well potential setting circuit3can set a well potential of the memory cell array1. At the time of read, write, and erase operations of a memory cell, the source potential setting circuit4can set a source potential of the memory cell array1. At the time of read, write, and erase operations of a memory cell, the column selection circuit5can select memory cells in the column direction of the memory cell array1. The sense amplifier circuit8can determine data read from memory cells for each column. The data input/output buffer6can send a command or an address received from the outside to the control circuit7and can perform reception and transmission of data between the sense amplifier circuit8and the outside.

The control circuit7can control operations of the row selection circuit2, the well potential setting circuit3, the source potential setting circuit4, and the column selection circuit5on the basis of a command and an address. When data is stored in a memory cell, the control circuit7can apply a first voltage to the gate dielectric film thereof and thereafter apply a second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage. The amplitude of the first voltage is set such that it is equal to or higher than the polarization inversion threshold of a ferroelectric film used as a gate dielectric film in a memory cell. The amplitude of the second voltage is set such that it is lower than the polarization inversion threshold of a ferroelectric film used as a gate dielectric film in a memory cell.

FIG. 2is a circuit diagram illustrating the schematic configuration of a block of the semiconductor memory device inFIG. 1.

InFIG. 2, in each of the blocks B1to Bn, h (h is a positive integer) number of word lines WL1to WLh, select gate lines SGD and SGS, and a source line SCE are provided. Moreover, in the blocks B1to Bn, m (m is a positive integer) number of bit lines BL1to BLm are provided in common.

In each of the blocks B1to Bn, m number of NAND cells NU1to NUm are provided and the NAND cells NU1to NUm are connected to the bit lines BL1to BLm, respectively.

In each of the NAND cells NU1to NUm, cell transistors MT1to MTh and select transistors MS1and MS2are provided. One memory cell in the memory cell array1can be composed of one cell transistor. A NAND string is configured by connecting the cell transistors MT1to MTh in series and the select transistors MS1and MS2are connected to both ends of the NAND string, thereby forming each of the NAND cells NU1to NUm.

In each of the NAND cells NU1to NUm, the word lines WL1to WLh are connected to the control gate electrodes of the cell transistors MT1to MTh, respectively. A plurality of memory cells in the row direction that share each of the word lines WL1to WLh form a page. Moreover, in each of the NAND cells NU1to NUm, one end of the NAND string composed of the cell transistors MT1to MTh is connected to a corresponding one of the bit lines BL1to BLm via the select transistor MS1and the other end of the NAND string is connected to the source line SCE via the select transistor MS2. The gate electrodes of the select transistors MS1are connected to the select gate line SGD and the gate electrodes of the select transistors MS2are connected to the select gate line SGS.

FIG. 3Ais a cross-sectional view illustrating one example of the cell transistor of the semiconductor memory device inFIG. 1andFIG. 3Bis a cross-sectional view illustrating another example of the cell transistor of the semiconductor memory device inFIG. 1.

InFIG. 3A, a control gate electrode35is provided on a well31with a ferroelectric film34therebetween. The well31is provided with a source layer33and a drain layer32arranged on both sides of the control gate electrode35. For the well31, it is possible to use semiconductors, such as Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, and ZnSe. For the ferroelectric film34, for example, HfO2can be used and 2 to 3 mol % of Si may be added to the HfO2. For the control gate electrode35, for example, polycrystalline silicon can be used.

InFIG. 3B, a control gate electrode47is provided on a well41with an interface dielectric film44, a ferroelectric film45, and a barrier metal film46, which are arranged sequentially in the order that they appear in this sentence, therebetween. Moreover, the well41is provided with a source layer43and a drain layer42arranged on both sides of the control gate electrode47. For the well41, it is possible to use semiconductors, such as Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, and ZnSe. For the interface dielectric film44, for example, SiO2can be used. For the ferroelectric film45, for example, HfO2can be used and 2 to 3 mol % of Si may be added to the HfO2. For the barrier metal film46, for example, TiN can be used. For the control gate electrode47, for example, polycrystalline silicon can be used.

In the following description, the cell transistor inFIG. 3Awill be explained as an example. Transition of the threshold of the cell transistor from a low value to a high value is referred to as a write operation and transition of the threshold of the cell transistor from a high value to a low value is referred to as an erase operation.

FIG. 4Ais a cross-sectional view illustrating a write voltage applying method in the semiconductor memory device inFIG. 1,FIG. 4Bis a cross-sectional view illustrating a state of a cell transistor after a write voltage is applied inFIG. 4A, andFIG. 4Cis a cross-sectional view illustrating a weak-erase-voltage applying method in the semiconductor memory device inFIG. 1.

In the write operation, after the first voltage is collectively applied to the gate dielectric films in the memory cells per block B1to Bn at the time of writing, the second voltage can be collectively applied to the gate dielectric films in the memory cells per block B1to Bn at the time of weak erasing.

Specifically, inFIG. 4A, at the time of writing, 0 V is applied to the word lines WL1to WLh of the blocks B1to Bn and the well potential of the memory cell array1is set to the write voltage Vpp (for example, 6 V). The source layer33and the drain layer32can be set to the write voltage Vpp. At this time, a high voltage is applied to the ferroelectric film34such that the channel side becomes positive and the control gate electrode35side becomes negative. Therefore, as illustrated inFIG. 4B, polarization37occurs in the ferroelectric film34such that the channel side becomes negative and the control gate electrode35side becomes positive, and the threshold of the cell transistor increases. At this time, positive trapped charge36is trapped in the ferroelectric film34so as to cancel the increase in the threshold of the cell transistor.

Next, as illustrated inFIG. 4C, at the time of weak erasing, the weak erase voltage Vwp (for example, 0.5 V) is applied to the word lines WL1to WLh of the blocks B1to Bn and the well potential of the memory cell array1is set to 0V. The source layer33and the drain layer32can be set to 0 V. At this time, an electric field is applied to the ferroelectric film34in the direction opposite to that applied at the time of writing. Therefore, the trapped charge36trapped in the ferroelectric film34is extracted and the effect of suppressing the increase in the threshold of the cell transistor due to the trapped charge36is eliminated.

The absolute value of the weak erase voltage Vwp can be set to a value smaller than the polarization inversion threshold of the ferroelectric film34. For example, when the polarization inversion threshold of the ferroelectric film34is 2.5 V, the absolute value of the weak erase voltage Vwp can be set to a value smaller than 2.5 V. Consequently, the trapped charge36trapped in the ferroelectric film34can be extracted without destroying the written state of the memory cell.

As described above, the difference between the erased state and the written state with regard to the threshold of a cell transistor can be expanded by performing weak erasing after writing; therefore, a read margin can be increased and stability of the threshold after polarization inversion of a cell transistor can be improved.

In the method inFIG. 4A, an explanation is given of a method of applying the write voltage Vpp to the well31, the source layer33, and the drain layer32of a memory cell and applying 0 V to the control gate electrode35at the time of writing; however, 0 V may be applied to the well31, the source layer33, and the drain layer32of a memory cell and −Vpp may be applied to the control gate electrode35.

FIG. 5is a flowchart illustrating an operation performed by the semiconductor memory device inFIG. 1at the time of writing.

InFIG. 5, when the write operation is started, the write voltage Vpp is applied to a memory cell such that polarization inversion occurs in the ferroelectric film34(S1).

Next, the weak erase voltage Vwp is applied to the memory cell such that an electric field is applied to the ferroelectric film34in the direction opposite to that applied at the time of writing and data written in the memory cell is not erased (S2).

FIG. 6is a timing chart illustrating an operation performed by the semiconductor memory device inFIG. 1at the time of writing.

InFIG. 6, before writing, the control gate voltage and the source/drain/well voltages are set to the ground potential GND. Then, when the write instruction signal rises from the ground potential GND to the power supply potential Vcc, the source/drain/well voltages rise from the ground potential GND to the write voltage Vpp. Therefore, the polarization37occurs in the ferroelectric film34such that the channel side becomes negative and the control gate electrode35side becomes positive. Thus, the threshold of the cell transistor increases.

Next, when the write instruction signal falls from the power supply potential Vcc to the ground potential GND, the source/drain/well voltages fall from the write voltage Vpp to the ground potential GND. Then, when the weak erase instruction signal rises from the ground potential GND to the power supply potential Vcc, the control gate voltage rises from the ground potential GND to the weak erase voltage Vwp. Therefore, the trapped charge36trapped in the ferroelectric film34is extracted and thus the effect of suppressing the increase in the threshold of the cell transistor due to the trapped charge36is eliminated. Then, when the weak erase instruction signal falls from the power supply potential Vcc to the ground potential GND, the control gate voltage falls from the weak erase voltage Vwp to the ground potential GND.

At this time, the write voltage Vpp and the weak erase voltage Vwp can be set such that the absolute value of the electric field applied to the ferroelectric film34when the trapped charge in the ferroelectric film34is extracted is smaller than the absolute value of the electric field applied to the ferroelectric film34when the polarization in the ferroelectric film34is inverted. The time twe (for example, 50 ns) during which the electric field due to the weak erase voltage Vwp is applied to the ferroelectric film34can be set shorter than the time tw (for example, 100 ns) during which the electric field due to the write voltage Vpp is applied to the ferroelectric film34. Moreover, the height or width of the voltage pulse of the weak erase voltage Vwp may be variable. Moreover, the height or width of the voltage pulse of the weak erase voltage Vwp can be specified from the outside.

In the above description, an explanation is given of a method in which, in the write operation, after the first voltage is collectively applied to gate dielectric films in memory cells per block B1to Bn at the time of writing, the second voltage is collectively applied to the gate dielectric films in the memory cells per block B1to Bn at the time of weak erasing. As another method, it may be such that after the first voltage is collectively applied to gate dielectric films in memory cells per block B1to Bn at the time of writing, the second voltage is applied to a gate dielectric film in a memory cell per bit at the time of weak erasing. In this weak erasing, the voltage applied to the control gate electrode35of a selected cell in a NAND string can be set larger than the voltage applied to the control gate electrodes35of nonselected cells in the NAND string. For example, the weak erase voltage Vwp (for example, 1 V) is applied to the selected word line and 0 V is applied to the selected bit line. A voltage (for example, 0.8 V) sufficient to turn on the nonselected cells in the NAND string that includes the selected cell is applied to the nonselected word lines and an erase inhibit voltage Vfe (for example, 0.5 V) is applied to the nonselected bit lines. Moreover, a voltage that turns the select transistors MS1on is applied to the select gate line SGD and a voltage that turns the select transistors MS2off is applied to the select gate line SGS.

As still another method, it may be such that after the first voltage is collectively applied to gate dielectric films in memory cells per block B1to Bn at the time of writing, the second voltage is applied to gate dielectric films in memory cells per NAND string at the time of weak erasing. In this weak erasing, the voltage applied to the ferroelectric films34in memory cells in a selected NAND string can be set larger than the voltage applied to the ferroelectric films34in memory cells in nonselected NAND strings. For example, the weak erase voltage Vwp (for example, 0.8 V) is applied to the selected word lines WL1to WLh, and moreover, whereas 0 V is applied to the bit line to which the selected NAND string is connected, the erase inhibit voltage Vfe (for example, 0.5 V) is applied to the bit lines to which the nonselected NAND strings are connected. Moreover, a voltage that turns the select transistors MS1on is applied to the select gate line SGD and a voltage that turns the select transistors MS2off is applied to the select gate line SGS.

FIG. 7Ais a cross-sectional view illustrating an erase voltage applying method of a semiconductor memory device according to the second embodiment,FIG. 7Bis a cross-sectional view illustrating a state of a cell transistor after an erase voltage is applied inFIG. 7A, andFIG. 7Cis a cross-sectional view illustrating a weak-write-voltage applying method of the semiconductor memory device according to the second embodiment.

In the erase operation, after the first voltage is applied to a gate dielectric film in a memory cell per bit at the time of erasing, the second voltage can be collectively applied to gate dielectric films in memory cells per block B1to Bn at the time of weak writing.

Specifically, inFIG. 7A, at the time of erasing, the erase voltage Ve (for example, 6 V) is applied to the selected word line and 0 V is applied to the selected bit line. A voltage (for example, 0.8 V) sufficient to turn on the nonselected cells in the NAND string that includes the selected cell is applied to the nonselected word lines and the erase inhibit voltage Vfe (for example, 0.5 V) is applied to the nonselected bit lines. Moreover, a voltage that turns the select transistors MS1on is applied to the select gate line SGD and a voltage that turns the select transistors MS2off is applied to the select gate line SGS.

Then, the voltage of 0 V applied to the selected bit line is transferred to the selected cell via the select transistor MS1and the nonselected cells, and the well31, the source layer33, and the drain layer32are set to 0 V. At this time, the erase voltage Ve is applied to the selected word line; therefore a high voltage is applied to the ferroelectric film34such that the channel side becomes negative and the control gate electrode35side becomes positive. Therefore, as illustrated inFIG. 7B, polarization39occurs in the ferroelectric film34such that the channel side becomes positive and the control gate electrode35side becomes negative, and the threshold of the cell transistor decreases. At this time, negative trapped charge38is trapped in the ferroelectric film34so as to cancel the decrease in the threshold of the cell transistor.

On the other hand, in the NAND cells connected to the nonselected bit lines, the erase inhibit voltage Vfe is applied to the nonselected bit lines; therefore, the select transistors MS1are turned off. As a result, the cell transistors MT1to MTh of the NAND cells connected to the nonselected bit lines become a floating state and the potential of the channels of the nonselected cells connected to the selected word line increases following the erase voltage Ve applied to the selected word line (self-boosting). Therefore, the voltage applied to the ferroelectric film34decreases in the nonselected cells connected to the selected word line. Thus, the polarization39of the ferroelectric film34can be prevented from being changing.

Next, as illustrated inFIG. 7C, at the time of weak writing, the weak write voltage Vwe (for example, −0.5 V) is applied to the word lines WL1to WLh of the blocks B1to Bn and the well potential of the memory cell array1is set to 0 V. The source layer33and the drain layer32can be set to 0 V. At this time, an electric field is applied to the ferroelectric film34in the direction opposite to that applied at the time of erasing. Therefore, the trapped charge38trapped in the ferroelectric film34is extracted and the effect of suppressing the decrease in the threshold of the cell transistor due to the trapped charge38is eliminated.

The absolute value of the weak write voltage Vwe can be set to a value smaller than the polarization inversion threshold of the ferroelectric film34. For example, when the polarization inversion threshold of the ferroelectric film34is 2.5 V, the absolute value of the weak write voltage Vwe can be set to a value smaller than 2.5 V. Consequently, the trapped charge38trapped in the ferroelectric film34can be extracted without destroying the erased state of the memory cell.

As described above, the difference between the erased state and the written state with regard to the threshold of a cell transistor can be expanded by performing the weak write operation after the erase operation; therefore, a read margin can be increased and stability of the threshold after polarization inversion of a cell transistor can be improved.

FIG. 8is a flowchart illustrating an operation performed by the semiconductor memory device according to the second embodiment at the time of erasing.

InFIG. 8, when the erase operation is started, the erase voltage Ve is applied to a memory cell such that polarization inversion of the ferroelectric film34occurs (S11).

Next, the weak write voltage Vwe is applied to the memory cell such that an electric field is applied to the ferroelectric film34in the direction opposite to that applied at the time of erasing and writing is not performed on the memory cell (S12).

FIG. 9is a timing chart illustrating an operation performed by the semiconductor memory device according to the second embodiment at the time of erasing.

InFIG. 9, before erasing, the control gate voltage and the source/drain/well voltages are set to the ground potential GND. Then, when the erase instruction signal rises from the ground potential GND to the power supply potential Vcc, the control gate voltage rises from the ground potential GND to the erase voltage Ve. Therefore, the polarization39occurs in the ferroelectric film34such that the channel side becomes positive and the control gate electrode35side becomes negative. Thus, the threshold of the cell transistor decreases.

Next, when the erase instruction signal falls from the power supply potential Vcc to the ground potential GND, the control gate voltage falls from the erase voltage Ve to the ground potential GND. Then, when the weak write instruction signal rises from the ground potential GND to the power supply potential Vcc, the control gate voltage falls from the ground potential GND to the weak write voltage Vwe. Therefore, the trapped charge38trapped in the ferroelectric film34is extracted and the effect of suppressing the decrease in the threshold of the cell transistor due to the trapped charge38is eliminated. Then, when the weak write instruction signal falls from the power supply potential Vcc to the ground potential GND, the control gate voltage rises from the weak write voltage Vwe to the ground potential GND.

At this time, the erase voltage Ve and the weak write voltage Vwe can be set such that the absolute value of the electric field applied to the ferroelectric film34when the trapped charge38in the ferroelectric film34is extracted is smaller than the absolute value of the electric field applied to the ferroelectric film34when the polarization of the ferroelectric film34is inverted. The time twe during which the electric field due to the weak write voltage Vwe is applied to the ferroelectric film34can be set shorter than the time tw during which the electric field due to the erase voltage Ve is applied to the ferroelectric film34. Moreover, the height or width of the voltage pulse of the weak write voltage Vwe may be variable. Moreover, the height or width of the voltage pulse of the weak write voltage Vwe can be specified from the outside.

In the above description, an explanation is given of a method in which, in the erase operation, after the first voltage is applied to a gate dielectric film in a memory cell per bit at the time of erasing, the second voltage is collectively applied to gate dielectric films in memory cells per block B1to Bn at the time of weak erasing. As another method, it may be such that after the first voltage is collectively applied to gate dielectric films in memory cells per block B1to Bn at the time of erasing, the second voltage is collectively applied to the gate dielectric films in the memory cells per block B1to Bn at the time of weak erasing.

Moreover, the first embodiment describes the method of performing the weak erase operation after the write operation and the second embodiment describes the method of performing the weak write operation after the erase operation; however, both operations may be performed.

FIG. 10is a block diagram illustrating the schematic configuration of a semiconductor memory device according to the third embodiment.

InFIG. 10, this semiconductor memory device includes a control circuit27instead of the control circuit7in the semiconductor memory device inFIG. 1. When data is stored in a memory cell, the control circuit27can apply the first voltage to the gate dielectric film thereof and thereafter apply the second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage, on the basis of the read result of the data from the memory cell. The second voltage can be applied per bit. At this time, when the data read from the memory cell is not correct, the second voltage can be applied to the memory cell and, when the data read from the memory cell is correct, the second voltage can be prevented from being applied. Moreover, at the time of writing to a memory cell, when the second voltage is applied per bit, the voltage applied to the control gate electrode35of a selected cell in a NAND string can be set larger than the voltage applied to the control gate electrodes35of nonselected cells in the NAND string.

FIG. 11is a flowchart illustrating an operation performed by the semiconductor memory device inFIG. 10at the time of writing. In the following description, when ‘1’ is stored in a memory cell, the memory cell is in a written state and when ‘0’ is stored in a memory cell, the memory cell is in an erased state.

InFIG. 11, when the write operation is started, the write voltage Vpp is applied to the memory cells such that polarization inversion occurs in the ferroelectric films34(S31). Next, a memory cell to be a target for verification is selected (S32) and data is read from the selected cell (S33). A memory cell can be selected per bit.

Next, it is determined whether the data stored in the selected cell is ‘1’ or ‘0’ (S34). When the data stored in the selected cell is ‘0’, the weak erase voltage Vwp is applied to the selected cell such that an electric field is applied to the ferroelectric film34in the direction opposite to that applied at the time of writing and the data written in the selected cell is not erased (S35).

On the other hand, when the data stored in the selected cell is ‘1’, it is determined whether all the memory cells have been selected (S36). When not all the memory cells have been selected, the processes in S31to S35are repeated until all the memory cells are selected.

The weak erase voltage Vwp is applied to the selected cell only when the data stored in the selected cell is ‘0’; therefore, the thresholds of the memory cells can be prevented from becoming excessively high. Therefore, it can be prevented that data cannot be read from different memory cells in the same NAND string. Moreover, excessive weak erasing can be prevented from being performed from the beginning; therefore, polarization inversion can be prevented.

FIG. 12is a timing chart illustrating an operation performed by the semiconductor memory device inFIG. 10at the time of writing.

InFIG. 12, before writing, the control gate voltage, the bit line voltage, the drain voltage, and the source/well voltages are set to the ground potential GND. Then, when the write instruction signal rises from the ground potential GND to the power supply potential Vcc, the bit line voltage, the drain voltage, and the source/well voltages rise from the ground potential GND to the write voltage Vpp. Therefore, the polarization37occurs in the ferroelectric film34such that the channel side becomes negative and the control gate electrode35side becomes positive. Thus, the threshold of the cell transistor increases. Then, when the write instruction signal falls from the power supply potential Vcc to the ground potential GND, the bit line voltage, the drain voltage, and the source/well voltages fall from the write voltage Vpp to the ground potential GND.

Next, the read operation is performed after the write operation is performed. In this read operation, the control gate voltage of a selected cell rises from the ground potential GND to the read voltage Vrg by applying the read voltage Vrg to the selected word line. An intermediate voltage (for example, 2.5 V) sufficient to turn on the cell transistors is applied to the nonselected word lines. Moreover, an intermediate voltage sufficient to turn on the select transistors MS1and MS2is applied to the select gate lines SGD and SGS. Moreover, a precharge voltage is applied to the selected bit line and 0 V is applied to the source line SCE.

At this time, when the threshold of the selected cell has not reached a read level, the charge stored in the selected bit line is discharged via the NAND string; therefore, the potential of the selected bit line becomes a low level. On the other hand, when the threshold of the selected cell has reached a read level, the charge stored in the selected bit line is not discharged via the NAND string; therefore, the potential of the selected bit line becomes a high level.

Then, it is determined whether the threshold of the selected cell has not reached a read level by determining whether the potential of the selected bit line is a low level or a high level, whereby the data stored in the selected cell is read. For example, when the data stored in the selected cell is ‘0’ even if the write operation is performed on the selected cell, the potential of the selected bit line becomes a low level. On the other hand, after the write operation is performed on the selected cell, when the data stored in the selected cell is ‘1’, the potential of the selected bit line becomes a high level. When the weak erase operation is performed after the read operation is performed on the selected cell, the potential of the selected bit line after the read operation can be held until the weak erase operation.

Next, after the read voltage Vrg falls, the weak erase instruction signal rises from the ground potential GND to the power supply potential Vcc. Then, the control gate voltage rises from the ground potential GND to the weak erase voltage Vwp and weak erasing is performed per bit in accordance with the data read from the selected cell.

When this weak erasing is performed per bit, the voltage applied to the control gate electrode35of the selected cell in the NAND string can be set larger than the voltage applied to the control gate electrodes35of the nonselected cells in the NAND string. Moreover, the potential of the selected bit line after the read operation can be applied to the selected bit line. For example, when the data stored in the selected cell is ‘0’, the weak erase voltage Vwp (for example, 1 V) is applied to the selected word line and 0 V is applied to the selected bit line. A voltage (for example, 0.8 V) sufficient to turn on the nonselected cells in the NAND string that includes the selected cell is applied to the nonselected word lines and the erase inhibit voltage Vfe (for example, 0.5 V) is applied to the nonselected bit lines. Moreover, a voltage that turns the select transistors MS1on is applied to the select gate line SGD and a voltage that turns the select transistors MS2off is applied to the select gate line SGS.

Then, the voltage of 0 V applied to the selected bit line is transferred to the selected cell via the select transistor MS1and the nonselected cells, and the well31, the source layer33, and the drain layer32are set to 0 V. When the data stored in the selected cell is ‘0’, the potential of the selected bit line is at a low level; therefore, the weak erase voltage Vwp is applied between the well31and the control gate electrode35of the selected cell. Therefore, the trapped charge36trapped in the ferroelectric film34is extracted and the effect of suppressing the increase in the threshold of the cell transistor due to the trapped charge36is eliminated. Then, when the weak erase instruction signal falls from the power supply potential Vcc to the ground potential GND, the control gate voltage falls from the weak erase voltage Vwp to the ground potential GND.

At this time, a voltage sufficient to turn on the nonselected cells in the NAND string is also applied to the ferroelectric films34in the nonselected cells; however, the voltage applied to the control gate electrodes35of the nonselected cells is smaller than the voltage applied to the control gate electrode35of the selected cell. Therefore, weak erasing can be prevented from being performed in the nonselected cells.

On the other hand, when the data stored in the selected cell is ‘1’, the potential of the selected bit line is at a high level. Therefore, the weak erase voltage Vwp is not applied between the well31and the control gate electrode35of the selected cell. Thus, the threshold of the selected cell can be prevented from becoming excessively high.

On the other hand, in the NAND cells connected to the nonselected bit lines, the erase inhibit voltage Vfe is applied to the nonselected bit lines; therefore, the select transistors MS1are turned off. As a result, the cell transistors MT1to MTh of the NAND cells connected to the nonselected bit lines become a floating state and the potential of the channels of the nonselected cells connected to the selected word line increases following the weak erase voltage Vwp applied to the selected word line (self-boosting). Therefore, the voltage applied to the ferroelectric film34decreases in the nonselected cells connected to the selected word line. Thus, in the nonselected cells connected to the selected word line, the voltage applied to the ferroelectric film34decreases and weak erasing can be prevented from being performed.

Moreover, in the NAND memory, the weak erase operation can be performed on all the memory cells that share the same word line. At this time, the read operation and the weak erase operation can be performed until data ‘1’ is read from all the bits in a page after writing or until the number of weak erase operations reaches the maximum number of repetitions.

In the above embodiment, an explanation is given where the voltage and duration of the weak erase operation are each the same over a plurality of weak erase operations; however, the voltage during the weak erase operation may be sequentially increased or the duration of the weak erase operation may be sequentially extended.

Consequently, it becomes possible to sequentially increase the degree of erasing starting from lower weak erasing. Therefore, it is possible to perform lower weak erasing on a memory cell for which the effect of weak erasing is large and perform higher weak erasing on a memory cell for which the effect of weak erasing is small.

When the voltage applied to the control gate electrode35of a selected cell in a NAND string is set equal to or lower than the voltage applied to the control gate electrodes35of nonselected cells in the NAND string, a voltage equal to or higher than the weak erase voltage Vwp is applied to the control gate electrodes35of the nonselected cells in the NAND string. Therefore, weak erasing is performed on the nonselected cells as well as the selected cell in the NAND string. Thus, weak erasing can be performed per NAND string.