FinFET device and methods of forming the same

FinFET device and method of forming the same are provided. The method of forming the FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.

BACKGROUND

Such scaling down has also increased the complexity of manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed. For example, a three dimensional transistor, such as a fin-type field-effect transistor (FinFET), has been introduced to replace a planar transistor. Although existing FinFET devices and methods of forming FinFET devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

FIG. 1AtoFIG. 1Fare simplified top views of a method of forming a FinFET device in accordance with a first embodiment of the disclosure, in which few elements such as fins, hybrid fins, gate lines, and insulating structures are shown for simplicity and clarity of illustration.FIGS. 2A and 2BtoFIGS. 12A and 12Bare schematic cross-sectional views of a method of forming a FinFET device in accordance with the first embodiment of the disclosure.

Referring to FIG. JA,FIG. 2AandFIG. 2B, a substrate10with multiple fins11thereon is provided. In some embodiments, the substrate10is a semiconductor substrate, such as a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate10may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate10may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Depending on the requirements of design, the substrate10may be a P-type substrate, an N-type substrate or a combination thereof and may have doped regions therein. The doped regions may be configured for an N-type FinFET device, a P-type FinFET device or a combination thereof.

In some embodiments, the method of forming the substrate10with the fins11includes forming a mask layer on a bulk substrate, and removing a portion of the bulk substrate by performing an etching process using the mask layer as an etch mask. The etching process may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching process may be anisotropic or isotropic. In alternative embodiments, the method of forming the substrate10with fins11includes performing a sidewall image transfer (SIT) technique. In some embodiments, the fins11are formed with an inclined sidewall, as shown inFIG. 2B, but the disclosure is not limited thereto. In alternative embodiments, the fins11may be formed with a substantially vertical sidewall. In some embodiments, the fin11has a height H1ranging from 25 nm to 70 nm, such as 54 nm. The fins11are semiconductor strips. In some embodiments, the fins11are extending in a first direction D1, and arranged along a second direction D2, as shown inFIG. 1A.

Still referring toFIG. 2AandFIG. 2B, the substrate10further has an isolation structure12formed thereon. In some embodiments, the isolation structure12surrounds and covers lower portions (lower sidewalls) of the fins11and exposes upper portions (upper sidewalls and top surfaces) of the fins11. In other words, the fins11protrude from the top surface of the isolation structure12. In some embodiments, the isolation structure12is a shallow trench isolation (STI) structure. The isolation structure12includes an insulation material, which may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof.

The method of forming the isolation structure12includes forming an isolation material layer covering sidewalls and top surfaces of the fins11by chemical vapor deposition (CVD), high density plasma CVD (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. In some embodiments, the isolation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. Thereafter, a portion of the isolation material layer on the top surfaces of the fins11are removed by a planarization process such as chemical mechanical polishing (CMP) and/or etching back, such that top surfaces of the fins11are exposed. The isolation material layer is further recessed to form the isolation structure12, such that upper sidewalls of the fins11are exposed. The isolation material layer may be recessed using an acceptable etching process, such as one that is selective to the isolation material. For example, a chemical oxide removal using a CERTAS® etch or an Applied Materials SICONI tool or dilute hydrofluoric (DHF) acid may be used. The top surface of the isolation structure12may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. It is understood that, the forming method of the fins11and the isolation structure12described above are merely for illustration, and the disclosure is not limited thereto.

In some embodiments, the fins11and the substrate10are made of the same material, such as silicon. In alternative embodiments, the fins11include a material different from that of the substrate10. For example, the substrate10includes silicon, and the fin11includes silicon germanium (SiGe). In some embodiments, the substrate10includes silicon, and the fins11may include silicon and other impurities or dopants. In some embodiments, doped regions including impurities may be formed in the fins11. For example, the fin11may include n-type impurities such as phosphorus, arsenic, or the like or combinations thereof for n-type FinFET device, or include p-type impurities such as boron, BF2, or the like or combinations thereof for p-type FinFET device.

Still referring toFIG. 1A,FIG. 2AandFIG. 2B, in some embodiments, a plurality of hybrid fins (or referred to as dummy fins)13are formed on the isolation structure12and aside the fins11. In some embodiments, the material of the hybrid fin13is different from that of the fin11. In some embodiments, the hybrid fins13are made of dielectric materials (or referred to as insulating material). The dielectric materials include oxide such as silicon oxide, nitride such as silicon nitride, high-K dielectric material, or the like, or combinations thereof. The high-K material includes metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, combinations thereof, or other suitable dielectric material. The hybrid fin13may be a single layer structure or a multi-layer structure. In some embodiments, the hybrid fins13may be formed by the following processes: after the fins11are formed, one or more hybrid fin material layers are formed on the isolation structure12and on the fins11by a deposition process such as CVD, HDP-CVD, FCVD, or the like, or combinations thereof. Thereafter, a removal process is performed to partially remove the hybrid fin material layer(s) to form the hybrid fins13. In some embodiments, the hybrid fin material layers include a bottom layer conformally deposited to cover the fins11and a top layer blanket deposited on the bottom layer and fill up recess between two adjacent fins11. The removal process may include performing a planarization process such as CMP to remove portions of the top and bottom layers to expose the top surface of the fins11, and following performing an etching back process to remove another portion of the bottom layer not cover by the remaining top layer in the recess. In alternative embodiments, the removal process may be a patterning process including photolithograph process and one or more etching processes (such as dry etching).

Referring toFIG. 1A, in some embodiments, the hybrid fins13are strips extending along the first direction D1and arranged along the second direction D2, which is the same as the fins11. In some embodiments, the fins11and the hybrid fins13are arranged alternately along the second direction D2. For example, as shown inFIG. 1A, one hybrid fin13is disposed between two adjacent fins11, and one fin11is located between two adjacent hybrid fins13, but the disclosure is not limited thereto. In some other embodiments, two or more hybrid fins13may be disposed between two adjacent fins11, and two or more fins11may be configured between two adjacent hybrid fins13according to the product design. The width W2in the second direction D2of the hybrid fin13maybe the same as or different from the width W1in the second direction D2of the fin11. In some embodiments, the width W2of the hybrid fin13is larger than the width W1of the fin11, but the disclosure is not limited thereto.

Referring toFIG. 2B, in some embodiments, the hybrid fin13is formed with an inclined sidewall, but the disclosure is not limited thereto. In alternative embodiments, the hybrid fin13may be formed with a substantially vertical sidewall. The cross-section shape of the hybrid fin13may be square, rectangle, trapezoid, or the like. The top surface of the hybrid fin13may be higher than, coplanar with or lower than the top surface of the fin11. In some embodiments, the hybrid fin13has a height H2ranging from 25 nm to 70 nm. In some embodiments, the sum value of the height H2and the height of the isolation structure12is equal to the height H1of the fin11, but the disclosure is not limited thereto.

Referring to FIG. JA,FIG. 4AandFIG. 4B, in some embodiments, a plurality of gate lines G are formed on the substrate10across the fins11and the hybrid fins13, extending in a second direction D2different from (e.g., perpendicular to) the first direction D1. The forming method of the gate lines G may include the following processes.

Referring back toFIG. 2AandFIG. 2B, in some embodiments, after the fins11and the hybrid fins13are formed, multiple dummy gate electrodes DG are formed on the substrate10across the fins11and the hybrid fins13. The dummy gate electrodes DG may be formed by the following processes: in some embodiments, a dummy layer is formed on the substrate10covering the fins11, the hybrid fins13and the isolation structure12, and is then patterned by photolithography and etching processes. In some embodiments, the dummy layer may be a conductive material and may be selected from a group including polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to create polysilicon. In some embodiments, the dummy layer may include a silicon-containing material such as polysilicon, amorphous silicon or combinations thereof. The dummy layer may be formed by a deposition process such as physical vapor deposition (PVD), CVD, or other suitable deposition process. In some embodiments, the dummy gate electrodes DG extend in the second direction D2different from (e.g., perpendicular to) the first direction D1.

In some embodiments, prior to forming the dummy gate electrode DG, an interfacial layer14is formed on the fins11by a thermal oxidation process, or formed on the fins11, the hybrid fins13and on the isolation structure12by a deposition process such as CVD, ALD or other suitable process. In other words, in some embodiments, the interfacial layer14is formed between the dummy gate electrode DG and the corresponding fins11. In some other embodiments, the interfacial layer14is formed between dummy gate electrode DG and the fins11, between the dummy gate electrodes and the hybrid fins13, and between the dummy gate electrodes and the isolation structure12(not shown). The interfacial layer14includes silicon oxide, silicon nitride, silicon oxynitride or combinations thereof. In some embodiments, a dummy gate dielectric layer (not shown) is further formed between the interfacial layer14and the dummy gate electrode DG, the dummy gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride or the like, and formed by CVD, ALD, or other suitable process known in the art.

Thereafter, spacers15are formed aside the dummy gate electrodes DG. The spacers15are extending in the second direction D2and respectively formed on the sidewalls of the dummy gate electrodes DG. The spacer15may be a single layer structure or a multi-layer structure. In some embodiments, the spacers15may be formed by the following processes: a spacer material layer is formed on the substrate10covering the dummy gate electrodes DG, and an etching process such as an anisotropic etching process is performed to remove a portion of the spacer material layer. In some embodiments, the spacer material layer includes SiO2, SiN, SiCN, SiOCN, SiOR (wherein R is an alkyl group such as CH3, C2H5or C3H7), SiC, SiOC, SiON, combinations thereof or the like, and may be formed by a suitable deposition process such as CVD, ALD or the like.

Afterwards, multiple strained layers16are formed in the fins11on opposite sides of the dummy gate electrodes DG. The strained layers16may be formed by-epitaxial growing process such as selective epitaxial growing process. In some embodiments, recesses are formed in the fins11, and the strained layers16are formed by selectively growing epitaxy layers from the recesses. In some embodiments, the top surfaces of the stained layers16are substantially coplanar with the top surface of the fin11, but the disclosure is not limited thereto. In some other embodiments, the strained layers16are formed within the recesses and may extend upwardly along the sidewalls of the corresponding spacers15(not shown), and thus have top surfaces higher than the top surface of the fin11. In some embodiments, the strained layers16include silicon germanium (SiGe) for a P-type FinFET device. In alternative embodiments, the strained layers16include silicon carbon (SiC), silicon phosphate (SiP), SiCP or a SiC/SiP multi-layer structure for an N-type FinFET device. In some embodiments, the strained layers16may be optionally implanted with an N-type dopant or a P-type dopant as needed. Following the formation of the strained layers16, silicide layers (not shown) may be formed on the strained layers16by a self-align silicide (salicide) process.

Still referring toFIG. 2AandFIG. 2B, an interlayer dielectric layer (ILD)18is formed aside or around the dummy gate electrodes DG. In some embodiments, a contact etch stop layer (CESL)17is also formed on the spacer15and on the stained layer16prior to forming the ILD18, and the CESL17includes SiN, SiC, SiON, or the like. The CESL17may be formed by CVD, PECVD, FCVD, ALD or the like. The ILD18includes a material different from that of the CESL17. In some embodiments, the ILD18includes carbon-containing oxide, silicate glass, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD18may be a single layer structure or a multi-layer structure.

The ILD18may be formed by forming an ILD material layer on the substrate10until its top surface is higher than the top surfaces of the dummy gate electrodes DG, through a suitable process, such as CVD, PECVD, FCVD or the like. A planarization process such as CMP is then performed to remove the excess ILD material layer over the dummy gate electrodes DG. In some embodiments, after the planarization process is performed, a pull-back process is performed on the ILD18. The “pull-back” process may be equivalently referred to as an “etch-back” process. A top portion of the ILD material layer may be recessed by way of the pull-back process, resulting in recessed ILD18which has a top surface lower than the top surfaces of the dummy gate electrodes DG. In some embodiments, the pull-back process may include a dry etching process, a wet etching process, and/or combinations thereof. The recessed ILD18may have a planar, concave or convex top surface.

In some embodiments, a helmet19is then formed on the ILD18for protecting the ILD18and underlying devices in the subsequent processes. The helmet19may also be referred to as a hard mask layer. The helmet19may have a high etching selectivity relative to the ILD18. The material of the helmet19is different from that of the ILD18. In some embodiments, the helmet19includes a dielectric material such as low-k material or a high-k material, or the like. The low-k material may have a dielectric constant lower than 7 and may include SiN, SiCN, SiOC, SiOCN or combinations thereof. The high-k material has a dielectric constant greater than about 7 or 10. In some embodiments, the high-k material includes metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, HfAlOx, HfSiOx, combinations thereof, or a suitable material. The helmet19may be formed by forming a helmet material layer through a deposition process such as CVD, PECVD, FCVD, ALD or the like, thereafter, a planarization process such as CMP or an etching back process is performed to remove the helmet material layer over the dummy gate electrode DG. In some embodiments, the top surface of the helmet19is substantially coplanar with the top surfaces of the dummy gate electrodes DG, the spacers15and the CESLs17. In some embodiments, the cross-sectional view of the helmet is square, rectangle, or the like. The profile of the bottom surface of the helmet19may be planar, and the profile of the top surface of the ILD18is also planar, but the disclosure is not limited thereto. In some other embodiments, as shown in the enlarged view ofFIG. 2A, the cross-sectional view of the helmet19may be semi-elliptical, semi-circular or the like. The profile of the bottom surface of the helmet19is arced, and convex toward the top surface of the substrate10. The top surface of the ILD18is also arced and concavely recessed toward the top surface of the substrate10. In other words, the ILD18includes two side portions at a higher level than a middle portion, and a bottom of the helmet19is laterally located between the side portions of the ILD18.

Referring toFIG. 2AandFIG. 2BtoFIG. 3AandFIG. 3B, a gate replacement process is then performed to replace the dummy gate electrodes DG with metal gate electrodes21. In some embodiments, the dummy gate electrodes DG are removed to form gate trenches in the dielectric layer18. Thereafter, a gate dielectric layer20is formed extending along the surface of the gate trenches, and the metal gate electrodes21are filled in the gate trenches. In some embodiments, the gate dielectric layer20surrounds the sidewalls and bottom of the metal gate electrodes21and on the tops and sidewalls of the fins11and the hybrid fins13. In some embodiments, the interfacial layer14is remained, and located between the gate dielectric layer20and the fins11, as shown inFIG. 3AandFIG. 3B, but the disclosure is not limited thereto. In some other embodiments, the interfacial layer14may be removed along with the dummy gate electrodes DG, resulting in the gate dielectric layer20contacting with the fins11(not shown).

In some embodiments, the gate dielectric layer20includes a high-k material having a dielectric constant greater than about 7 or 10. In some embodiments, the high-k material includes metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, combinations thereof, or a suitable material. In alternative embodiments, the gate dielectric layer20may optionally include a silicate such as HfSiO, LaSiO, AlSiO, combinations thereof, or a suitable material. The gate dielectric layer20may have a high etching selectivity relative to the hybrid fins13. The material of the gate dielectric layer20may be different from the material of the hybrid fins13underlying thereof. In some embodiments, the metal gate electrode21includes a work function metal layer and a metal fill layer on the work function metal layer. The work functional metal layer is configured to tune a work function of its corresponding FinFET to achieve a desired threshold voltage Vt. The work function metal layer maybe an N-type work function metal layer or a P-type work function metal layer. In some embodiments, the P-type work function metal layer includes a metal with a sufficiently large effective work function and may comprise one or more of the following: TiN, WN, TaN, conductive metal oxide, and/or a suitable material, or combinations thereof. In alternative embodiments, the N-type work function metal layer includes a metal with sufficiently low effective work function and may comprise one or more of the following: tantalum (Ta), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable metals, suitable conductive metal oxide, or combinations thereof. The metal fill layer includes copper, aluminum, tungsten, cobalt (Co), or a suitable material. In some embodiments, the metal gate electrode21may further include a liner layer, an interface layer, a seed layer, an adhesion layer, a barrier layer, combinations thereof or the like.

The metal gate electrodes21are extending along the second direction D2across the fins11and the hybrid fins13. In some embodiments, the top surfaces of the metal gate electrodes21, the gate dielectric layer20, the spacer15, the CESL17and the helmet19are substantially coplanar with each other.

Referring toFIG. 3AandFIG. 3BtoFIG. 4AandFIG. 4B, in some embodiments, a removal process is performed to remove portions of the metal gate electrodes21and portions of the gate dielectric layers20, so as to form metal gate electrodes21aand gate dielectric layers20a. The removal process includes one or more etching processes (such as etching back process). As such, the height of the metal gate electrodes21is reduced. In some embodiments, the top surfaces of the metal gate electrodes21aare substantially coplanar with the top surfaces of the gate dielectric layers20aand lower than the top surfaces of the helmets19.

Thereafter, another removal process is performed to remove portions of the spacers15and portions of the CESL17by using the helmet19as an etching mask, such that spacers15aand CESLs17awith reduced height are formed. The removal process may include an etching process such as an isotropic process, an anisotropic process, or a combination thereof. In some embodiment, the top surfaces of the spacers15aand the top surfaces of the CESLs17are higher than the top surfaces of the metal gate electrodes21aand the gate dielectric layer20a, and lower than the top surfaces of the helmets19. In some embodiment, the top surfaces of the spacers15aand the top surfaces of the CESLs17are substantially coplanar with each other, or located at different levels. The sequence of the removal processes of the metal gate electrodes21a, the gate dielectric layer20a, the spacers15aand the CESL17described above are merely for illustration, and the disclosure is not limited thereto. In some other embodiments, the metal gate electrodes21aand the gate dielectric layer21amay be partially removed after the spacers15aand the CESL17are partially removed.

Referring toFIG. 4A, in some embodiments, after the removal processes are performed, a recess RC is formed in the ILD18and the helmet19. In some embodiments, the cross-section shape of the recess RC is T-shaped or the like.

Referring toFIG. 4AandFIG. 4B, in some embodiments, a protection layer23is then formed on the metal gate electrodes21a. In some embodiments, the protection layer23includes substantially fluorine-free tungsten (FFW) film. The FFW film may be formed by atomic layer deposition (ALD) or CVD using one or more non-fluorine based W precursors such as, but not limited to, tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), or a combination thereof. In some embodiments, the protection layer23is merely formed on the metal gate electrodes21ato cover the top surfaces of the metal gate electrodes21a, but the disclosure is not limited thereto. In some other embodiments, the protection layer23may cover the metal gate electrodes21aand may further extend to cover the top surfaces of the gate dielectric layers20aand contact with the spacer15a. The sidewalls of the protection layer23may be aligned with the sidewalls of the metal gate electrodes21aor the sidewalls of the gate dielectric layer20a, and the disclosure is not limited thereto.

Referring toFIG. 1AandFIG. 4A, in some embodiments, the metal gate electrodes21a, the gate dielectric layer20a, the interfacial layer14and the protection layer23form the gate line (or referred to as metal gate line) G. The gate lines G are extending along the second direction D2, and arranged along the first direction D1, across the fins11and the hybrid fins13. It is noted that, for the sake of brevity, merely metal gate electrodes21aare shown to represent the gate line G inFIG. 1A.

Referring toFIG. 1C,FIG. 6AandFIG. 6B, a cutting process is performed to cut off or disconnect one or more of the gate lines G. The cutting process may be performed by removing a portion the gate line G, so as to form at least one trench T1in the dielectric layer18and in the gate line G. In some embodiments, the cutting process includes photolithography and etching processes. An example of the cutting process is described as below.

Referring toFIG. 1B,FIG. 5AandFIG. 5B, in some embodiments, a patterned mask layer24with one or more openings OP1is formed over the substrate10. The patterned mask layer24may be a single-layer structure or a multi-layer structure. In some embodiments, the patterned mask layer includes patterned photoresist, and may be formed by a photolithography process. For example, a photoresist layer is formed over the substrate10, and then exposure and development process are performed on the photoresist layer. However, the disclosure is not limited thereto. In some embodiments in which the patterned mask layer24is a multi-layer structure, the forming method thereof will be described as below with reference toFIGS. 17A to 17D.

Referring toFIG. 17A, in some embodiments, the patterned mask layer24is formed from a tri-layer structure including a bottom layer24a, a middle layer24band an upper layer24c. The bottom layer24amay be a bottom anti-reflective coating (BARC) layer. In some embodiments, the middle layer24bis a hard mask layer such as a silicon containing hard-mask layer, or the like. In some embodiments, the middle layer24bmay be formed of or include an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The upper layer24cmay be formed of a photosensitive material, such as a photoresist, which may comprise organic materials. The middle layer24bmay have a high etching selectivity relative to the upper layer24cand the bottom layer24a. The various layers of the bottom layer24ato upper layer24cmay be blanket deposited sequentially using, for example, spin-on coating processes. Other suitable deposition process may be used, such as CVD, ALD, PVD, or the like. Although a tri-layer structure is discussed, the disclosure is not limited thereto.

In some embodiments, the bottom layer24ais formed on the gate lines G, the spacers15a, the CESLs17a, and the helmet19. In other words, the bottom layer24afills into the recesses RC, and the top surface of the bottom layer24amay be located at a higher level than the top surface of the helmet19. The top surfaces of the protection layer23, the spacers15, the CESLs17, and the helmets19, portions of sidewalls of the spacers15, the ILD18and the helmets19are covered and in physical contact with the bottom layer24. The middle layer24band the upper layer24care sequentially formed on the bottom layer24a.

In some embodiments, the upper layer24cis patterned to have an opening OP (or referred to as opening pattern) therein. The location of the opening OP is corresponding to the subsequently formed opening OP1of the patterned mask layer24(FIG. 5A). The opening OP exposes a portion of the top surface of the middle layer24b. The patterning method may be photolithography including exposure and development processes.

Referring toFIG. 17AandFIG. 17B, the opening pattern OP of the upper layer116is sequentially transferred to the middle layer24band exposes the top surface of the bottom layer24a, through etching the middle layer24bwith the upper layer24cas an etching mask. In some embodiments, during the etching process of the middle layer24b, the upper layer24cmay be partially or completely consumed.

Referring toFIG. 17BandFIG. 17C, in some embodiments, a layer24dis then formed on the middle layer24band the bottom layer24aby spin coating, CVD, ALD or other suitable processes. In some embodiments, the layer24cis an oxide layer such as a Low-Temperature (LT) oxide layer, which is deposited at a low temperature, for example, lower than about 100° C., or ranging from 50° C. to 200° C.

Referring toFIG. 17CtoFIG. 17D, an etching process such as an anisotropic process is performed on the layer24d, such that the horizontal portions of the layer24don the top surfaces of the middle layer24band the bottom layer24aare removed. As a result, a layer24d′ is formed on the bottom layer24aand on sidewalls of the middle layer24b. In other words, the layer24d′ is formed along the sidewalls of the opening OP. In some embodiments, the layer24d′ is formed to keep and maintain the profile of the opening pattern OP, and serve as a hard mask in the subsequently etching processes.

Referring toFIG. 17DandFIG. 17E, the bottom layer24ais patterned by an etching process with the layer24d′ and the middle layer24bas an etching mask, in some embodiments, a portion of the bottom layer24aon the helmet19and in the recess RC are removed, so as to form the patterned mask layer24having openings OP1. In some embodiments, the patterned mask layer24includes the bottom layer24a, the middle layer24band the layer24d′. The bottom layer24ais located on and in contact with the gate lines G, the spacers15a, the CESLs17a, the dielectric layer18, and the helmets19. The middle layer24bis located on the bottom layer24a, the layer24d′ is located on the bottom layer24aand on sidewalls of the middle layer24b. In some embodiments, the sidewalls of the bottom layer24aand the sidewalls of the layer24d′ are exposed in the opening OP1, and may be aligned with each other, but the disclosure is not limited thereto.

In the embodiments described above, the layer24dis formed before the opening pattern OP is transferred to the bottom layer24a, but the disclosure is not limited thereto. In some other embodiments, the layer24dmay be formed after the opening pattern OP is transferred to the bottom layer24a, and the layer24d′ may be formed on sidewalls of the bottom layer24aand on sidewalls of the middle layer24b(not shown). The structure and the forming method of the patterned mask layer24described above are merely for illustration, and the disclosure is not limited thereto. Further, for the sake of brevity, the structure of the patterned mask layer24are not specifically shown inFIG. 5AtoFIG. 6B.

Referring back toFIG. 1B, in some embodiments, the patterned mask layer24includes the plurality of openings OP1formed over the hybrid fins13. In some embodiments, the width W3of the opening OP1along the second direction D2is larger than the width W2of the hybrid fin13, but the disclosure is not limited thereto. The openings OP1are extending along the first direction D1, and across one or more gate lines G. In some embodiments, the openings OP1are staggered, and partially overlapped with each other in the second direction D2, but the disclosure is not limited thereto. In some embodiments, each opening OP1may run across two gate lines G. For example, the patterned mask layer24includes openings OP1a, OP1band OP1c, the gate lines G includes gate lines Ga, Gb, Gc and Gd. The opening OP1arun across the gate lines Ga and Gb. The opening OP1brun across the gate lines Gb and Gc. The opening OP1crun across the gate lines Gc and Gd. However, the disclosure is not limited thereto. In some embodiments, each opening OP1may run across one or more than two gate lines G, the gate line G may be exposed by one or more than two openings OP1, some of the gate lines G may be not exposed by the opening OP1, depending on the product design.

Referring toFIG. 1B,FIG. 5AandFIG. 5B, the opening OP1of the patterned mask layer24is in spatial communication with the recess RC. In some embodiments in which the opening OP1run across two gate lines G, the opening OP1has a length L1larger than the space (or referred to as distance) L2between the two helmets19on outer sides of the two gate lines G (such as Ga and Gb). In other words, the opening OP1exposes portions of the protection layer23of the two gate lines G (such as Ga and Gb), portions of top surfaces of the helmets19on outer sides of the exposed two gate lines G (such as Ga and Gb), the top surface of the helmet19between (that is, on inner sides of) the exposed two gate lines G (such as Ga and Gb), the CESLs17aand the spacers15aaside the exposed two gate lines G.

Referring toFIG. 1C,FIG. 6AandFIG. 6B, portions of the gate lines G exposed by the openings OP1are removed to cut off the gate lines G. Specifically, portions of the protection layer23, portions of the metal gate electrodes21a, portions of the gate dielectric layers20a, and portions of the interfacial layer14are removed, and portions of the hybrid fins13are exposed. In some embodiments, the gate lines G are cut by one or more etching processes with the patterned mask layer24, the helmet19, the CESL17a, and the spacer15aas the etching mask. In some embodiments, the etching process includes dry etching, wet etching, or combinations thereof. In some embodiment, the cutting process may further include performing an over etch process, and portions of the hybrid fins13may be removed, so as to ensure (the gate dielectric layer20aof) the exposed gate lines G is completely removed. Upon the over etch process, shown as the dotted line inFIG. 6A, the trench T1may further extend into the hybrid fin13, and has a bottom surface lower than the topmost surface of the hybrid fin13, that is, the hybrid fin13may be recessed. Referring toFIG. 5BandFIG. 6B, the gate dielectric layer20aon the exposed hybrid fin13is completely removed, so as to avoid current leakage. In some embodiment, after the cutting process is performed, a portion of the top surface of the gate dielectric layer20ais substantially level with the top surface of the hybrid fin13.

In other words, trenches T1are formed in the dielectric layer18and in the gate lines G. In some embodiments, the trenches T1may also be referred to as recesses. Referring toFIG. 6A, the trenches T1are underlying portions of the recesses RC and are in spatial communication with the corresponding recesses RC. In other words, portions of the recess RC are deepened. In some embodiments, the opposite sidewalls of the trench T1in the first direction D1exposes a portion of the spacer15a, the opposite sidewalls of the trench T1in the second direction D2exposes a portion of the metal gate electrode21aand a portion of the protection layer23, and the bottom of the trench T1exposes a portion of the hybrid fin13and a portion of the gate dielectric layer20a(FIG. 6B). In some embodiments, the bottom of the trench T1further exposes a portion of the metal gate electrode21a(shown as the dotted line inFIG. 6B).

Referring toFIG. 1CandFIG. 6A, in some embodiments, the cross section shape of the trench T1along line I-I′ may be square, rectangle, or the like. The width Wt of the trench T1along the first direction D1substantially equal to the width of the gate line G along the first direction D1. Referring toFIG. 1CandFIG. 6B, in some embodiments, the cross-section shape of the trench T1along line III-III′ may be trapezoid, square, rectangle, or the like. The sidewalls of the trench T1may be substantially straight or inclined. The aspect ratio (H4/W3′) of the trench T1ranges from 0.125 to 3.75, for example. The width W3′ of the trench T1may range from 8 nm to 40 nm, for example. The height H4of the trench T1is less than the height H3of the gate line G on the isolation structure12. The height H4may be less than 30 nm, and may range from 5 nm to 25 nm, or 5 nm to 30 nm, for example. In some embodiments, the sum of the height H2′ of the hybrid fin13and the height H4of the trench T1equal to the height H3of the gate line G. The height H2′ of the hybrid fin13may be equal to or slightly less than the height H2of the hybrid fin13.

As shown inFIG. 1CandFIG. 6B, the gate line G is cut off by the trenches T1and the hybrid fins13underlying thereof. In the embodiments of the disclosure, since hybrid fins13are formed, the amount and the height of the gate line G need to be removed to cut the gate line G is significantly reduced, and may be adjusted by adjusting the height H2of the hybrid fin13. As such, the gate line G is easier to be etched and cut off. In some embodiments, the width W3′ (i.e. bottom width) of the trench T1is larger than the width W2(i.e. top width) of the hybrid fin13, but the disclosure is not limited thereto. The width W3′ of the trench T1may be equal to or less than the width W2of the hybrid fin13, as long as the gate line G is cut off.

In some embodiment, some of the gate lines G may be cut into two sections disconnect to each other by one trench T1therein, such as the outer two gate lines Ga and Gd inFIG. 1C. Specifically, the gate lines Ga and Gd are cut into two groups of gate lines (or referred to as gate line sections) G1and G2disconnect to each other by the trench T1aand T1d, respectively. Some of the gate lines G may be cut into three sections disconnect to each other by two trenches T1therein, such as the middle two gate lines Gb and Gc shown inFIG. 1CandFIG. 6B. Specifically, the gate lines Gb and Gc are cut into three groups of gate lines (or referred to as gate line sections) G1, G2, and G3by two trenches T1band two trenches T1c, respectively. In the gate line Gb or Gc, gate line G3is located between the two trenches T1bor T1c, and gate lines G1and G2are located at outer sides of the two trenches T1bor T1cin the second direction D2. It is understood that, the cutting mode herein is merely for illustration, and the disclosure is not limited thereto. The cutting mode of the gate lines G may be adjusted according to the requirement of the product design.

Referring toFIG. 1D,FIG. 7AandFIG. 7B, the patterned mask layer24is removed by an ashing process, an etching process or combinations thereof, for example. Thereafter, a patterned mask layer25having one or more openings OP2is formed over the substrate10. In some embodiments, the material, the structure and the forming method of the patterned mask layer25may be the same as or different from those of the patterned mask layer24. In some embodiments, the patterned mask layer25is a patterned photoresist formed by photolithograph including exposure and development processes. In some embodiments, the patterned mask layer25is also a multi-layer structure including a bottom layer, a middle layer, and a low temperature oxide layer. The multi-layer structure of the patterned mask layer25and forming method thereof are similar to those of the patterned mask layer24with reference toFIG. 17AtoFIG. 17E, which are not described here again.

In some embodiments, the openings OP2of the patterned mask layer25are formed over the gate lines G, extending along the same direction D2as the gate lines G, at least exposing portions of the gate lines G. In some embodiments, the opening OP2exposes a portion of one gate line G (such as Gb or Gc) across one or more fins11. In some embodiments, the opening OP2exposes the gate line G3between the two trenches T1(T1bor T1c) and between two hybrid fins13. In some embodiments, since the helmet19is formed on the dielectric layer18, the width W5of the opening OP2may be formed larger than the width of the gate line G along the first direction D1, and may larger than the space (or referred to as distance) W4(FIG. 7B) between the helmet19or the dielectric layer18on opposite sides of the gate line G. In some embodiments, portions of the helmet19, dielectric layer18, the spacer15aand the CESLs17aon opposite sides of the exposed gate line G3are also exposed by the opening OP2.

Referring toFIG. 1DandFIG. 7B, in some embodiments, in the second direction D2, the length L5of the opening OP2may be greater than the length L3of the gate line G3, and less than the distance L4between the gate lines G1and G2. In accordance with some embodiments, the length L3of the gate line G3may be referred to as the distance L3between two adjacent hybrid fins13. The length L5of the opening OP2may be greater than the distance L3between two adjacent hybrid fins13, and less than the distance L4between the two sidewalls (or end walls) OS of the gate lines G1and G2(FIG. 7B). In some embodiments, the opening OP2is partially overlapped with and in spatial communication with the trench T1(such as T1bor T1c), and portions of the hybrid fins13under the trenches T1(such as T1bor T1c) may also be exposed by the opening OP2. The sidewalls OS of the gate lines G1and G2are covered by the patterned mask layer25. However, the disclosure is not limited thereto. In some other embodiments, the length L5of the opening OP2may be equal to the distance L4between the gate lines G1and G2on outer sides of the two trenches T1(such as T1bor T1c). The opening OP2may be overlap with and in spatial communication with the trenches T1, and may further exposes the sidewalls OS of the gate lines G1and G2on outer sides of the two trenches T1(such as T1bor T1c). In some embodiments, the sidewalls of the opening OP2may be aligned with the sidewalls (or referred to as the end walls) OS of the gate lines G1and G2(not shown).

Referring toFIGS. 1D, 7A and 7BtoFIGS. 1E, 8A and 8B, a cutting process (or referred to as removal process) by removing the gate lines G3exposed by the openings OP2is performed to form trenches T2in gate lines G (such as Gb and Gc). That is, portions of the gate lines G between the hybrid fins13under the trenches T1(such as T1band T1c) are removed. In some embodiments, the cutting process may include one or more etching process, such as dry etching process. In some embodiments, the trenches T2includes trench T2band T2cformed in gate lines Gb and Gc, respectively. The trench T2bis located between and in spatial communication with the two trenches T1bon ends thereof. The trench T2cis located between and in spatial communication with the two trenches T1con ends thereof. The trenches T2are extending along the second direction D2. The gate line G is cut off by the trenches T1and the hybrid fins13underlying the trenches T1and/or the trenches T2. For example, the gate line Ga is cut off by the trench T1aand the hybrid fins13underlying the trench T a. The gate line Gd is cut off by the trench T1dand the hybrid fins13underlying the trench T1d. The gate line Gb is cut off by the trenches T1b, the trench T2band the hybrid fins13underlying the trench T1b. The gate line Gc is cut off by the trenches T1c, the trench T2cand the hybrid fins13underlying the trench T1c. As a result, two groups of gate lines G1and G2are remained, and are disconnect to each other.

Referring toFIG. 1E,FIG. 8AandFIG. 8B, after the gate lines G are partially removed, portions of top surfaces and sidewalls of the two hybrid fins13underlying the two trenches T1facing each other, a portion of the top surface of the isolation structure12, and parts of the upper portions11aof the fins11(shown as the dotted line inFIG. 8B) protruding on the isolation structure12are exposed by the trenches T2. Thereafter, the upper portions11aof the fins11exposed by the trenches T2, and the lower portions11bof the fins11covered by the isolation structure12underlying the exposed upper portions11aare further removed, and a trench T3underlying the trench T2is formed in the fin11and in the isolation structure12. In some embodiments, the trench T3is further deepened by removing a portion of the substrate10. That is to say, the trench T3is formed in the fin11, the isolation structure12and in the substrate10. In some embodiments, the fin11and the substrate10are removed by one or more etching process, such as anisotropic etching process, isotropic etching process, or combinations thereof. The etching process may be, dry etching, wet etching or combinations thereof.

Referring toFIG. 8AandFIG. 8B, in some embodiments, the cross-section shape of the trench T3may be bowling shaped, vase shaped, or the like. In some embodiments, the depth H5(from the top surface of the fin11to the bottom of the trench T3) of the trench T3is larger than the height H1(FIG. 2B) of the fin11. In some embodiments, the depth H5of the trench T3is larger than 150 nm, for example. In some embodiments, the depth H5of the trench T3ranges from 90 nm to 250 nm, for example. Referring toFIG. 8A, in some embodiments, along the first direction D1, the trench T3has a non-uniform width from top to bottom. For example, the width of the trench T3may be decreased then increased and then decreased gradually from top to bottom. In some embodiments, the width of the trench T3may be decreased gradually from the top surface of the fin11to the level of the depth of the strained layer16, such that strained layers16on sides of the trench T3would not be damaged upon the formation of the trench T3. The largest width of the trench T3may be under the bottom of the strained layer16, and may be in the fin11, at the interface between the fin11and the substrate10, or in the substrate10. The structure feature (such as shape, height, width) of the trench T3described above is merely for illustration, and the disclosure is not limited thereto.

Referring toFIG. 1E, in some embodiments, the trench T3is configured to cut or disconnect the fins11and therefore to fully isolate the devices at opposite sides of the trench T3in the first direction D1. In some embodiments, the fin11is cut into two groups of fins11aand11b.

Referring toFIG. 1F,FIG. 10AandFIG. 10B, an insulating structure28ais then formed in the trenches T1, T2and T3. The insulating structure28amay be formed by the following processes. Referring toFIG. 9AandFIG. 9B, in some embodiments, an insulating layer28is formed over the gate lines G and the helmet19, and filled in the trenches T1, T2and T3, and the recesses RC. The insulating layer28may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the insulating layer28, the material of the hybrid fin13and the material of the isolation structure12may be the same as or different from each other. In some embodiments, the insulating layer28includes silicon nitride, silicon oxide, silicon oxynitride or a suitable insulating material, and the forming method thereof includes performing a suitable deposition process such as CVD, HDP-CVD, FCVD, or the like.

Referring toFIGS. 9A and 9BtoFIGS. 10A and 10B, a removal process is performed to remove the insulating layer28out of the trenches T1, T2, T3, such that the insulating structure28ais formed. Specifically, the insulating layer28located over the gate lines G, that is, located over the helmet19and in the recess RC is removed. In some embodiments, the removal process includes an etching process, such as an etching back process. In some embodiments, the helmet19, the spacers15a, the CESLs17aand the protection layer23of the gate line G serve as etching stop layer during the removal process. In some embodiments, after the removal process is performed, the top surface of the insulating structure28is substantially coplanar with the top surface of the protection layer23of the gate line G.

Referring toFIG. 1F,FIGS. 10A and 10B, the insulating structure28aand the hybrid fin13underlying thereof are configured to electrically separate gate line G into two groups of gate lines G1and G2, and electrically separate fins11into two groups of fins11aand11b. In some embodiments, the insulating structure28aincludes a plurality of first portions P1and a plurality of second portions P2. In some embodiments, the first portion P1may also be referred to as a cutting metal gate (CMG) layer, and the second portion P2may also be referred to as a “cut poly on OD edge” (CPODE) layer. The first portions P1is the portion of the insulating structure28ain the trenches T1. The first portion P1is located on the hybrid fins13, and surrounded by the spacer15aand the gate lines G or/and the second portion P2. Some of the first portions P1are in contact with the second portion P2, and some of the first portions P1are not in contact with the second portion P2. For example, in the gate line Ga or Gd, the first portion P1of the insulating structure28ais located on the hybrid fin13, between and in contact with the spacers15aalong the first direction D1, between and in contact with the gate lines G1and G2along the second direction D2. In the gate line Gb or Gc, the first portion P1is located on the hybrid fin13, between and in contact with the spacers15aalong the first direction D1, between and in contact with the gate line G1or G2and the second portion P2along the second direction D2.

As shown inFIG. 1F,FIG. 10AandFIG. 10B, in some embodiments, the bottom surface of the first portion P1may be in contact with the hybrid fin13, and may further be in contact with the gate dielectric layer20aand metal gate electrode21a(shown as the dotted line inFIG. 10B) of the gate line G. In some embodiments, the bottom surface of the first portion P1is in contact with the hybrid fin13, and is substantially coplanar with or lower than (see the dotted line inFIG. 10A) the bottom surface of the gate line G on the hybrid fin13(or the topmost surface of the hybrid fin13), but the disclosure is not limited thereto. In some embodiments, a portion of the sidewall of the first portion may be in contact with the hybrid fin13(shown as the dotted line inFIG. 10A). The top surface of the first portion P1is substantially coplanar with the top surface of the protection layer23of the gate line G. In some embodiments, the first portion P1and the hybrid fin13underlying thereof are configured to electrically separate gate line G into two groups of gate lines G1and G2along the second direction D2. Take the gate line Ga or Gd for example, the first portion P1cut and electrically separate the gate line Ga (or Gd) into two groups of gate lines G1and G2. The two groups of gate lines G1and G2of the gate line G are located at opposite sides of the first portion P1along the second direction D2, and are electrically and physically isolated from each other by the first portion P1of the isolation structure28atherebetween. In some embodiments, one gate line G (such as gate lines Ga and Gd) is corresponding to one first portion P1, but the disclosure is not limited thereto. One gate line G (such as gate lines Gb and Gc) may be correspond to two or more first portions P1according to the product design.

In some embodiments, the second portion P2is extending along the second direction D2, and located between two first portions P1and between two hybrid fins13underlying the two first portions P1. The second portion P2is in contact with the first portions P1. Further, in the second direction D2, the sidewalls (or referred to as end walls) of the second portion P2are in contact with the sidewalls (or referred to as end walls) of the hybrid fins13. In some embodiments, the top surface of the second portion P2is substantially coplanar with the top surface of the first portion P1and the top surface of the protection layer23of the gate line G (such as the gate line Gb and Gc). In the embodiments of the disclosure, the second portion P2and the first portion P1are formed simultaneously. As such, no interface is formed between the second portion P2and the first portion P1.

The second portion P2is across the fin11, cutting the fin11into two groups of fins11aand11bat two opposite sides of the second portion P2along the first direction D1, and therefore to fully isolate the gate lines G and devices at opposite sides of the second portions P2on the fins11aand11b. That is, the two groups of the fins11aand11bare physically and electrically separated from each other by the second portion P2of the insulating structure28atherebetween. As a result, the gate lines G (such as the gate line sections G1of the gate lines Gc and Gd) on the fins11aand the gate lines G (such as the gate line sections G2of the gate lines Ga and Gb) on the fins11bare electrically isolated from each other by the second portions P2of the insulating structure28a.

In some embodiments, the second portion P2includes a body portion BP in the trench T2and an extending portion EP in the trench T3. The body portion BP is located on and in contact with the isolation structure12and the extending portion EP, as shown inFIGS. 10A and 10B. In the first direction D1, the body portion BP is located between and in contact with the spacers15a(FIG. 10A). In the second direction D2, the body portion BP is located between the first portions P1and the hybrid fins13underlying the first portions P1(FIG. 10B).

The extending portion EP extends into the fins11aand11b, the isolation structure12and the substrate11. The extending portion EP is located between the fins11aand11b, and surrounded by the fins11aand11b, the isolation structure12, and the substrate11.

As shown inFIGS. 1F and 10B, in some embodiments, the first portions P1of the insulating structure28and the hybrid fins13underlying thereof cut and (electrically and physically) separate the gate lines G into two groups of gate lines G1and G2along the second direction D2. The second portions P2of the insulating structure28cut and (electrically and physically) separate the fin11into two groups of fins11aand11balong the first direction D1. As a result, two regions R1and R2isolated from each other are defined upon the formation of the insulating structure28a. Gate lines G1across fins11aare provided in the region R1. Gate lines G2across fins11bare provided in the second region R2. The gate lines G1and other devices in the region R1and the gate lines G2and other devices in the region R2are isolated and electrically separated from each other by the insulating structure28a. It is noted that, the configuration of the insulating structure28ashown inFIG. 1Fis merely for illustration, and the disclosure is not limited thereto.

Referring toFIG. 11AandFIG. 11B, a helmet material layer30is formed over the helmet19, the gate lines G and the insulating structure28a. The helmet material layer30may include a material the same as or different from that of the helmet19, and different from the material of the insulating structure28a. The helmet material layer30includes dielectric material, such as nitride (e.g. silicon nitride), oxide (e.g. silicon oxide), silicon oxycarbide, or combinations thereof. In some embodiments, the helmet dielectric material layer may include high-K dielectric material or low-K dielectric material. The high-K material includes metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, combinations thereof, or a suitable material. The forming method of the helmet material layer30may include a suitable deposition process such as CVD HDP-CVD, FCVD, or the like, or combinations thereof.

Referring toFIGS. 11A and 11BtoFIGS. 12A and 12B, a planarization process such as CMP, is performed to remove the helmet material layer30and the helmet19over the dielectric layer18, so as to form a helmet30a. In some embodiments, the top surface of the helmet30ais substantially coplanar with the top surface of the dielectric layer18.

The helmet30ais disposed on and in physical contact with top surfaces of the gate lines G and insulating structure28a, and between the dielectric layer18, extending along the second direction D2. In other words, the gate lines G and the insulating structure28are protected by the helmet30a. In some embodiments, the cross-section shape of the helmet30ais T-shaped, but the disclosure is not limited thereto. In some embodiments, the helmet30aincludes a lower portion LP and an upper portion UP on the lower portion LP. As shown inFIG. 12AandFIG. 12B, the lower portion LP is located on the insulating structure28aand the gate line G, and between the spacers15a. The sidewalls of the lower portion LP are in contact with the spacers15a. The upper portion UP is located on the lower portion LP, the spacers15aand the CESLs17a. The bottom surface of the upper portion UP is in physical contact with the top surfaces of the spacers15aand the CESLs17a. The sidewalls of the upper portion UP are in contact with the dielectric layer18.

Still referring toFIG. 1FandFIGS. 12A and 12B, a FinFET device50is thus completed. In some embodiments, the FinFET device50includes a plurality of fins11aand11b, hybrid fins13, a plurality of gate lines G1and G2, and the insulating structure28a. The fins11aand11bare disposed on the substrate10. The isolation structure12is disposed on the substrate10and covers or surrounds lower portions of the fins11aand11b. The insulating structure28aand the hybrid fin13underlying thereof define two regions R1and R2of the FinFET device50. In other words, devices in the region R1and devices in the region R2are isolated from each other by the insulating structure28atherebetween. The insulating structure28ais located between and in physical contact with the gate lines G1and G2, and the fins11aand11b. The gate lines G1and the fins11aare located in the region R1, the gate line G2and the fins11bare located in the region R2. The gate lines G1are across the fins11ain the region R1. The gate lines G2are across the fins111bin the region R2.

In some embodiments, the FinFET device50further includes strained layers16in the fins11aand11band aside the gate lines G1and G2, the gate lines G1and G2includes the interfacial layer14, the gate dielectric layer20a, the metal gate electrode21a, and the protection layer23. Spacers15aare disposed on sidewalls of the gate lines G1and G2. Dielectric layer18is disposed over the substrate10and aside the gate lines G1and G2. CESLs17aare disposed between the dielectric layer18and the spacers15aand between the dielectric layer18and the substrate10. Helmets30aare disposed on the gate lines G1and G2and the insulating structure28aand on the spacers15aand the CESLs17a.

In some embodiments, subsequent processes may be performed on the FinFET device50. For example, a first contact hole (or referred to as a first contact trench) may be formed through the dielectric layer18and the CESL17to expose the strained layer16, and a first connector may be formed in the first contact hole to electrically connect to the strained layer16. A second contact hole (or referred to as a second contact trench) may be formed through the helmet30aon the gate line G1or G2. The second contact hole may further penetrate through the protection layer23on the metal gate electrode21a. Thereafter, a second connector is formed in the second contact hole to electrically connect to the metal gate electrode21aof the gate line G1or G2. In some embodiments, the protection layer23serves as an etching stop layer during forming the second contact hole, and may provide the function of reducing resistance of the metal gate electrode21a.

In the foregoing embodiments, one fin11is disposed between two adjacent hybrid fins13, and the resulting insulating structure28has one extension part EP (FIG. 10B), but the disclosure is not limited thereto. Referring toFIG. 16, In some other embodiments in which two fins11are disposed between two adjacent hybrid fins13, a FinFET device50′ may be formed with the insulating structure28has two extending part EP.

In the first embodiment of the disclosure, the trenches T1for forming the CMG and the trenches T2and T3for forming the CPODE are formed sequentially. Two patterning processes using two patterned mask layer are performed sequentially to form the trench T1and the trenches T2and T3, so as to cut the gate lines and fins, but the disclosure is not limited thereto. In some other embodiments, the trenches T1, T2and T3may be formed simultaneously in one patterning process using one patterned mask layer.

FIG. 13AandFIG. 13Billustrate top views of the configuration of a patterned mask layer for forming the trenches T1, T2, T3according to a second embodiments of the disclosure. It is noted that, for the sake of brevity, two hybrid fins and one fin are shown inFIGS. 13A and 13B.FIGS. 14A and 14BtoFIGS. 15A and 15Billustrate the cutting process of gate lines and fins according to the second embodiments of the disclosure. The processes of the second embodiment are similar to those of the first embodiment, except that the trenches T1, T2, T3are together formed in one patterning process using one patterned mask layer. The difference of the second embodiment from the first embodiment is described in detail as below, and the similar processes of the second embodiment as the first embodiment are not repeated again here.

Referring toFIGS. 4A and 4BandFIGS. 14A and 14B, after the gate lines G are formed, a patterned mask layer124is formed on the gate lines G and the helmet19. The materials and forming method of the patterned mask layer124may be the same as or different from those of the patterned mask layer24or25in the first embodiment, and are not descried again. The patterned mask layer124has an opening OP12, exposing portions of the gate lines G and portions of the helmets19, spacers15aand CESLs17aon sides of the portions of the gate lines G.

Referring toFIG. 13A, in some embodiments, the top view of the opening OP12is “” shaped, I-shaped, inverted H-shaped, horizontal H-shaped, horizontal h-shaped, Z-shaped or the like. The opening OP12includes first portions OP10and a second portion OP20in spatial communication with each other. In some embodiments, the positions of the first portion OP10and the second portion OP20are substantially the same as the openings OP1and the opening OP2described inFIGS. 5 and 6of the first embodiment. The profile of the opening OP12is substantially the same as the combination of the opening OP1(FIG. 1B) and the opening OP2(FIG. 1D) in the first embodiment.

In some embodiments, the first portion OP10is extending along the first direction D1, across two gate lines G, exposing portions of the two gate lines G on the hybrid fins13, and portions of the helmet19. The second portion OP20is extending along the second direction D2, across one or more fins11, exposing a portion of the gate line G. In some embodiments, the second portion OP20is between the two first portions OP10on ends thereof. In some embodiments, the two first portions OP10are staggered, and partially overlapped with each other in the second direction. For example, one of the first portions OP10is across the gate lines Ga and Gb, and another one of the first portions OP10is across the gate lines Gb and Gc, while the second portion OP20is over the gate line Gb, and between the two first portions OP10.

Referring toFIG. 14A, in some embodiments, the first portions OP10exposes portions of two gate lines G, portions of top surfaces of the helmets19on outer sides of the exposed two gate lines Ga and Gb, the top surface of the helmet19between (that is, on inner sides of) the exposed two gate lines Ga and Gb, the CESLs17aand the spacers15aaside the exposed two gate lines G. The second portion OP20exposes a portion of the gate line G between two hybrid fins13and portions of the top surfaces of the helmets19, the spacers15aand the CESLs17aon sides of the exposed gate lines Gb.

As shown inFIG. 13A, in some embodiments, the shapes of the first portions OP10and second portions OP20of the opening OP12may be regular strip shaped, the turning point TP between the first portion OP10and the second portion OP20may be about a right angle. However, the disclosure is not limited thereto. As shown inFIG. 13B, in the embodiments of the disclosure, since helmets19are formed on the dielectric layer18and may also serve as the etching mask in the subsequent process, the opening OP12′ of the patterned mask layer124may have an irregular “” shaped or irregular I-shaped top view. Specifically, compared to the opening OP12shown inFIG. 13A, the opening OP12′ may be expanded to have a larger size than the opening OP12. The shape of the second portion OP20′ of the opening OP12′ may be butterfly-like shaped or bow-knot shaped. The turning point TP′ between the first portion OP10′ and the second portion OP20′ may include an obtuse angle.

Referring toFIG. 15AandFIG. 15B, a removal process is performed to remove the gate lines G and the underlying fin11and a portion of the substrate10underlying the fin11exposed by the opening OP12, so as to form the trenches T1, T2and T3. The resulting structure is substantially the same as the structure shown inFIG. 8AandFIG. 8B. The removal process includes one or more etching processes with the patterned mask layer124and the helmet19as an etching mask. In some embodiments, the removal process is similar to the removal processes described inFIG. 6A/6B andFIG. 8A/8B, the difference lies in that the removal processes illustrated inFIG. 6A/6B andFIG. 8A/8B of the first embodiment are performed simultaneously in the second embodiment. Thereafter, the patterned mask layer124is stripped, and processes fromFIGS. 9A and 9BtoFIGS. 12A and 12Bare performed. The insulating structure is formed in the trenches, and a protection layer is formed on the insulating structure. Other processes and resulting FinFET device of the second embodiment are substantially the same as or different from those of the first embodiment, and are not described again.

In the embodiments of the disclosure, cutting processes of the gate lines and fins, that is, the forming of the trenches for CMG and CPODE are performed just (immediately) after the metal gate etching back process, and the insulating structure is filled in the trenches simultaneously after the trenches are formed. As such, the process is simplified and cost is reduced. On the other hand, with the forming of the hybrid fins, gate high loss for cutting metal gate electrode is reduced, and high etching bombardment during the formation of the trenches for CMG is reduced. On the other embodiments of the disclosure, the trenches for CMG and CPODE are formed by one patterning/cutting process using one patterned mask layer, the process is further simplified and the cost is further reduced.

In accordance with some embodiments of the disclosure, a method of forming a FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.

In accordance with alternative embodiments of the disclosure, a method of forming a FinFET device includes the following steps. A substrate having a plurality of fins is provided. The fins are extending along a first direction. An isolation structure is on the substrate, surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A dielectric layer is formed on the substrate and a helmet is formed on the dielectric layer. A plurality of gate lines are formed across the fins and the hybrid fin. The gate lines are extending along a second direction, and the dielectric layer is aside the gate lines. A first cutting process is performed by removing a first portion of at least one of the gate lines to form a first trench in the at least one of the gate lines. The first trench exposes a portion of the hybrid fin. A second cutting process is performed. The second cutting process comprises performing the following processes. A second portion of one of the gate lines is removed to form a second trench in the dielectric layer. The second trench is extending along the second direction and exposing a portion of the fins. The portion of the fins exposed by the second trench and a portion of the substrate under the portion of the fins are removed, so as to form a third trench under the second trench. An insulating structure is formed in the first, second, and third trenches. A protection layer is formed on the insulating structure and on the gate lines.

In accordance with some embodiments of the disclosure, a FinFET device includes a substrate, a plurality of first fins, a plurality of second fins, an isolation structure, a hybrid fin, a plurality of first gate lines, a plurality of second gate lines, and an insulating structure. The first fins and the second fins are on the substrate. The isolation structure surrounds lower portions of the first fins and the second fins. The hybrid fin is on the isolation structure, and aside the first fins and the second fins. The first gate lines are across the first fins. The second gate lines are across the second fins. The insulating structure is on the hybrid fin, located between and separating the first gate lines and the second gate lines, and between the first fins and the second fins. A first part of the insulating structure on the hybrid fin and a second part of the insulating structure on the isolation structure have no interface therebetween.