Optical amplifying apparatus

The present invention provides an optical amplifying apparatus having: a CPU 11 for processing various signals; a plurality of circuits 17, 18 for controlling respective devices 4, 9 required for optical amplification; a first storing unit 14 for storing a program supplied from a user a gate array 12 for storing various parameters for controlling the devices 4, 9, the gate array being updated based on the program which is stored in the first storing unit 14 and sent via the CPU 11; a latch unit 13, provided between the gate array 12 and the circuits 17, 18, for interrupting a signal path from the gate array 12 to the circuits 17, 18 after receiving a starting signal of an update from the CPU 11 until the update being finished and for controlling the circuits 17, 18 based on the parameters stored in the gate array 12 before the signal path is interrupted; and a second storing unit 16 for, at least during the update, storing the various parameters which are stored in the gate array 12 before the update.

FIELD OF THE INVENTION

The present invention relates to an optical amplifying apparatus and, more particularly, to an optical amplifying apparatus having a controller using an FPGA (FIELD PROGRAMMABLE GATE ARRAY).

RELATED ART

The WDM (Wavelength Division Multiplexing) system is a system in which plural optical signals of different wavelengths are multiplexed into one optical transmission path. This WDM system adopts a configuration using an optical amplifying apparatus which is provided in an optical transmission path to control power of an optical signal and output the optical signal to the optical transmission path such as a single mode optical fiber (SMF) or a dispersion-shifted optical fiber (DSF).

The optical amplifying apparatus includes an EDF (Erbium Doped Fiber) connected to some midpoint of an optical transmission path, a pumping LD (Laser Diode) for optically pumping the EDF, two PDs (Photo Diodes) for monitoring light input to or output from the EDF and a controller for controlling a driving current of the pumping LD based on outputs from the two PDs.

FIG. 6is a circuit diagram illustrating an example of the controller of the optical amplifying apparatus. The controller100includes an LD circuit111for controlling a driving current of the pumping LD, a heater circuit112for controlling the temperature of an EDF heater, a PD circuit113receiving detected signals of the PDs, a configuration ROM (Read Only Memory)103holding programs input from a user interface102via a CPU101, an FPGA104for controlling the LD circuit111, the heater circuit112and the like, an AD converter/DA converter105for performing DA conversion on a signal from the FPGA104to output the signal to the LD circuit111, the heater circuit112and the like and performing AD conversion on signals from the PD circuit113and the like to output the signals to the FPGA104, and other circuits.

In such a controller, the CPU101and FPGA104, which are firmware, can be updated or improved in function/performance by rewriting their programs.

In updating of the FPGA104, the configuration ROM103receives data of a program and the like from the user interface102and stores the data therein. Then, in response to an update request from the CPU101, the FPGA104has the program rewritten with use of the data stored in the configuration ROM103. This program rewriting takes about one second, for example. When the program is rewritten, various parameters in the FPGA104are reset. That is, the various parameters are also updated via the CPU101.

FPGA program writing using a configuration element is disclosed, for example, in the following non-patent document 1.

While the FPGA104is being updated, the FPGA104can not perform various controls of LD driving current and temperature via the LD circuit111and the heater circuit112.

Meanwhile, the following patent document 1 discloses use of two programmable controllers for machine control, of which one controls the machine performance and the other is in the backup mode, and when the one programmable controller is in trouble, the other takes over the control of the machine performance.

Here, with reference to the configuration disclosed in the patent document 1, two FPGAs may be used in the controller of the optical amplifying apparatus, and when one of the FPGAs is being program-updated, the other is used to perform various operations including monitoring of photo diodes, LD driving current control and temperature control.NON-patent document 1: Cyclone Device Handbook, Volume 1, p. 13-9, Altera Corporation, August 2005Patent document 1: Japanese Patent Laid-open Publication No. 6(1994)-51802

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In the configuration illustrated inFIG. 6, if the FPGA104is updated during operation of the optical amplifying apparatus, the FPGA104is prevented from performing various operations, which may causes such a problem that control of an optical signal propagating in the optical amplifying apparatus is interrupted, resulting in communication failure. In addition, as various parameters in the FPGA104are erased they are required to be rewritten after updating, which takes a lot of time and effort.

On the other hand, if two FPGAs are used in the optical amplifying apparatus as disclosed in the patent document1, control of the optical amplifying apparatus is not interrupted. However, this configuration needs to be large-sized and expensive.

The present invention has an object to provide an optical amplifying apparatus which allows simultaneous performance of optical amplification control and FPGA updating without any additional FPGA.

Means for Solving the Problems

In order to solve the above-mentioned problems, a first aspect of the present invention is an optical amplifying apparatus comprising: a CPU for processing various signals; a plurality of circuits for controlling respective devices required for optical amplification; a first storing unit for storing a program supplied from a user; a gate array for storing various parameters for controlling the devices, the gate array being updated based on the program which is stored in the first storing unit and sent via the CPU; a latch unit, provided between the gate array and the circuits, for interrupting a signal path from the gate array to the circuits after receiving a starting signal of an update from the CPU until the update being finished and for controlling the circuits based on the parameters stored in the gate array before the signal path is interrupted; and a second storing unit for, at least during the update, storing the various parameters which are stored in the gate array before the update.

A second aspect of the present invention is an optical amplifying apparatus of the first aspect, in which the devices comprise at least an optically pumping laser diode and the circuits comprise a laser diode circuit for setting a driving current of the laser diode.

A third aspect of the present invention is an optical amplifying apparatus of the second aspect, in which the latch unit is configured to obtain an average value of the driving current of the laser diode which is calculated out by measuring the driving current of the laser diode a predetermined number of times successively before the update is started and to drive the laser diode with the average value during the update.

A fourth aspect of the present invention is an optical amplifying apparatus of the third aspect, in which, after a dither signal output from the gate array is turned off, the gate array measures the driving current the predetermined number of times successively to calculate out the average value.

A fifth aspect of the present invention is an optical amplifying apparatus of any one of the first to fourth aspects, in which the devices comprise a monitoring element for monitoring an optical signal propagating in an optical fiber, and a detected signal from the monitoring element is sent to the CPU via an analog/digital converter.

Effects of the Invention

According to the present invention, when a gate array as firmware is updated, device control to be performed by the gate array is performed instead by a latch unit and various parameters stored in the gate array are temporarily stored in another storing unit for backup. This configuration allows normal control of optical amplification even while the single gate array is being updated and easy reproduction of the various parameters that are deleted from the gate array during the updating.

DESCRIPTION OF REFERENCE NUMERALS

BEST MODE FOR CARRYING OUT THE INVENTION

With reference to the drawings, an embodiment of the present invention will be described in detail below.

FIG. 1is a view illustrating a configuration of an optical amplifying apparatus according to the embodiment of the present invention.

The optical amplifying apparatus according to the embodiment of the present invention includes: as illustrated inFIG. 1, an optical amplifier3including an erbium-doped optical fiber (EDF)1connected to an optical transmission path and a first optical coupler2connected to the EDF1; a pumping laser diode (LD)4emitting optically pumping energy to the EDF1via the first optical coupler2; a first photo diode (PD)6receiving via a second optical coupler5an optical signal which is to be input to the EDF1and performing photo-electric conversion on the optical signal; a second photo diode (PD)8receiving via a third optical coupler7an optical signal outputted from the optical amplifier3and performing photo-electric conversion on the optical signal; a heater9controlling the temperature of the EDF1; and a controller10receiving electric signals from the first photo diode6and the second photo diode8and controlling based on these electric signals a driving current of the pumping LD4and the temperature of the heater9.

The controller10has:, as illustrated inFIG. 2, a CPU11for performing processing such as inputting and outputting of data between devices and controlling of the operation of each device; an FPGA12for rewritably storing a program for controlling the pumping LD4and the heater9and the like and storing various types of data and various parameters; a latch IC13for selectively outputting, based on an instruction from the CPU11, a control signal, which is output from the FPGA12in a predetermined operation mode, as it is or an ACC (Auto Current Control) mode control signal based on preset data; a flash ROM14for storing programs and data; a user interface15for externally acting to store programs in the flash ROM14via the CPU11; a SRAM (Static Random Access Memory)16for temporarily storing data of various parameters, which is stored in the FPGA12, by processing of the CPU11; an LD circuit17for setting the driving current of the pumping LD4; a heater circuit18for setting a heating temperature of the heater; a PD circuit19for receiving signals outputted from the PDs6and8; a DA converter20for converting a digital signal output from the latch IC13to an analog signal to output the signal to the LD circuit17and the heater circuit18; an AD converter21for converting an analog signal output from the PD circuit19to a digital signal to output the signal to the FPGA12and CPU11; an output interface22relaying display signals output from the latch IC13; and the like.

The FPGA12includes, as illustrated inFIG. 3, a shared memory12a, an AGC calculation block12band a selector12c.

The shared memory12ais configured to store various parameters and data including a parameter to be output to the LD circuit17for making a driving current and a dither signal pass to the pumping LD4, a parameter to be output to the heater circuit18for controlling the temperature of the heater9, a parameter to be output to the output interface22for external display, signals for selecting the control mode between the ACC mode and the AGC (Auto Gain Control) mode, control target values and detected values of the PDs6and8received from the PD circuit19via the AD converter21and also to output a signal for setting a control mode in response to a signal from the CPU11and ACC and AGC target values.

Besides, the AGC calculation block12bis configured to calculate parameters for AGC so as to control optical amplification in the AGC mode based on a control signal from the CPU11until program data is sent from the user interface15to the flash ROM14. For example, the AGC calculation block12bcalculates various parameters including a driving current of the pumping LD4based on the detected values of the PDs6and8received from the PD circuit19via the AD converter21in such a manner as to attain a gain target value of input/output power with an optical signal, then, outputs the calculated AGC parameters to the shared memory12aand sends AGC target values obtained based on the calculation result to the selector12c.

The selector12cis configured to selectively output ACC target values or AGC target values to the latch IC13based on a control mode setting signal from the shared memory12a. Here, the ACC target values include a parameter for controlling a driving current, dither signal and the like to keep optical power output from the pumping laser diode4constant.

Next description is made about updating of an FPGA12program in the above-mentioned controller10of the optical amplifying apparatus.

First, the controller10operates in the AGC mode in accordance with a pre-update program. That is, in the FPGA12illustrated inFIG. 3, the shared memory12asends the selector12ca signal for setting the AGC mode as control mode, and AGC target values sent from the shared memory12aare selected to control the LD circuit17, the heater circuit18and the like via the latch IC13in such a manner as to obtain a predetermined gain in the AGC mode.

The AGC target values are calculated out by the AGC calculation block12bbased on detected values of the first PD6and the second PD8received from the AD converter21and the various parameters so as to have a target value of gain. The thus-obtained target values of the parameters are output from the selector12cto the latch IC13. In this case, upon receiving the target values from the FPGA12, the latch IC13then outputs the target values as they are to the output interface22or outputs to the LD circuit17and the heater circuit18via the DA converter20.

Upon receiving the target values, the LD circuit17outputs a driving current and a dither signal to the pumping LD4while the heater circuit18outputs a control signal to control the temperature of the heater9. Besides, the output interface22outputs a signal for controlling a display unit.

During such AGC mode operation, when an updated program is output from the user interface15to the controller10, the CPU11in the controller10stores the program output from the user interface15in the flash ROM14and controls the FPGA12in accordance with the flowchart shown inFIG. 4.

InFIG. 4, first it is determined in the AGC mode control by the FPGA12whether the pumping LD4is controlled by a dither signal or not (S1inFIG. 4). When control by a dither signal is performed, amplitude and a frequency of the dither signal are set to “0” (S2inFIG. 4).

Then, a target value of the driving current of the pumping LD4calculated by the AGC calculation block12bis read by the shared memory12arepeatedly, for example,512times, and the target values obtained by repeated calculation are used to obtain an average value thereof. This average value is then set as a target value of the driving current of the pumping LD4in the ACC mode operation (S3inFIG. 4). Here, when the shared memory12ais used to read the target value of the driving current continuously plural times, the dither signal is set to be invalid and therefore, the calculated target value hardly varies depending on measurement timing.

Further, the various parameters for AGC calculated and stored in the shared memory12aand all other parameters are stored in the SRAM16for backup by the CPU11(S4inFIG. 4).

This is followed by the CPU11sending a mode switching signal to the FPGA12and thereby, the control mode output from the shared memory12ato the selector12cis switched from the AGC mode to the ACC mode, and target values of the ACC mode including an average target value of the driving current of the pumping LD4obtained while disabling the dither signal are sent to the selector12c(S5inFIG. 4). Then, the selector12coutputs the ACC target signals to the LD circuit17and the like via the latch IC13and has the ACC target signals and their parameters stored in the latch IC13.

Then, the CPU11confirms that the control mode of the shared memory12aof the FPGA12becomes the ACC mode (S6inFIG. 4).

Later, the CPU11sends a control signal to the latch IC13and blocks control signals and data from the FPGA12to the latch IC13. On the other hand, the ACC mode control signals and parameters stored in the latch IC13are continuously sent via the DA converter20to the LD circuit17, the heater circuit18and the like, and control signals are also sent to the output interface22(S7inFIG. 4).

After the ACC mode control held by the latch IC13is started, the CPU11erases the program and data in the FPGA12and writes in the FPGA12program data stored in the flash ROM14to update the FPGA program. Then, various parameters and other data saved in the SRAM are written again in the shared memory12aof the FPGA12(S8inFIG. 4). At this time, a parameter regarding the dither signal is also read from the SRAM16and written again in the shared memory12athereby to enable control by way of dither signals again.

Then, as the latch IC13controls the pumping LD4, the heater9and the like, control to the optical amplifying apparatus is kept on during program updating of the FPGA12. Further, as detected values of the photo diodes6and8are also input to the CPU11via the PD circuit19and the AD converter21, for example, such processing may be possible that the CPU11stops optical amplification when a detected signal of the first PD connected to the input side of the EDF1is zero.

After the FPGA12updating is finished and restarted, the CPU11checks to see if the FPGA12operates normally (S9inFIG. 4)

As AGC mode control becomes possible in this state, the CPU11controls the FPGA12to change the control mode set at the selector12cby the shared memory12afrom the ACC mode to the AGC mode and to calculate various parameters for AGC mode by way of the AGC calculation block12bto make the selector12aoutput an AGC signal and AGC target values to the latch IC13.

Then, block state from the FPGA12to the latch IC13is released by the CPU11while the AGC mode control signal and target values controlled by the FPGA12are made to pass through the latch IC13to be output to the DA converter20and the output interface22(S10inFIG. 4).

Thus, the pumping LD4and the heater9are controlled by the various parameters of the AGC mode.

Here, the operation of the optical amplifier was checked in the three phases of while the FPGA program was being updated following the above-described flow and before and after the program was updated. This check result reveals that optical input and output of the EDF1were not changed nor interrupted which the FPGA program was updated and the optical amplification was continuously controlled.

Meanwhile, comparison was made between the case where the driving current target value of the pumping LD4was averaged before the program of the FPGA12was updated and the case where the driving current target value was not averaged, which is shown inFIGS. 5(a) and5(b).

FIG. 5(a) is a graph of the case where the driving current target value of the pumping LD4was not averaged, showing fluctuation of an optical output from the EDF1between the time when the pumping LD4was controlled by the latch IC13and the time when the pumping LD4was controlled by the FPGA12.

On the other hand,FIG. 5(b) is a graph of the case where the driving current target value of the pumping LD4was averaged, showing no fluctuation of an optical output from the EDF1occurring between the time when the pumping LD4was controlled by the latch IC13and the time when the pumping LD4was controlled by the FPGA12.

These results show that when the driving current of the pumping LD4is controlled by the latch IC13in the ACC mode, it is necessary to first obtain an average value of the driving current of the pumping LD4controlled by the FPGA12in the AGC mode while no dither signal is disabled, and then, to use this average value as a driving current value in the ACC mode, thereby assuring stable optical amplification even during program updating of the FPGA12.