Systems and methods for adaptive threshold pattern detection

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. In one case, a data processing system is disclosed that includes: a pattern detector circuit operable to generate a pattern value based upon a comparison of a defined pattern to a first portion of a received input; and a comparator circuit operable to compare the pattern value to an adapted threshold, and to selectively assert a pattern found signal based at least in part on the comparison of the pattern value and the adapted threshold, where the adapted threshold is adjusted based at least in part on a noise component of a second portion of the received input.

FIELD OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

BACKGROUND OF THE INVENTION

Various circuits have been developed that provide for identifying synchronization marks within a data stream. As an example, a synchronization mark is identified based upon a threshold comparison. Such a threshold comparison approach depends highly upon determining an appropriate threshold for comparison. Where the selected threshold is too high, sync marks will be missed. Alternatively, where the selected threshold is too low, sync marks may be incorrectly identified. Either case is problematic for proper data processing.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for sync mark identification.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

Various embodiments of the present invention provide data processing systems that include: a pattern detector circuit, and a comparator circuit. The pattern detector circuit is operable to generate a pattern value based upon a comparison of a defined pattern to a first portion of a received input. The comparator circuit is operable to compare the pattern value to an adapted threshold, and to selectively assert a pattern found signal based at least in part on the comparison of the pattern value and the adapted threshold. The adapted threshold is adjusted based at least in part on a noise component of a second portion of the received input.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

Various embodiments of the present invention provide for pattern detection using an adaptive threshold. In some cases, the adaptive threshold varies as a function of the signal to noise ratio in a stream of input data containing the pattern to be detected. As an example, in one particular embodiment of the present invention, a series of data samples are received that include a pattern to be detected. During a training period, a default threshold is calculated. This may be done, for example, by averaging the best match level of the series of data samples with the second best match level. The best match and the second best match correspond to matches to the pattern in the received series of data samples. In addition, an average energy resulting from other than a periodic pattern (e.g., a preamble patter preceding a sync mark pattern) is repeatedly calculated during the test period to yield an average non-periodic energy. This average non-periodic energy is subtracted from the default threshold to yield a offset value. Then, during normal operation, the best match of the series of data samples to the sync mark pattern is identified and the corresponding value calculated. In addition, the energy resulting from other than the periodic pattern is calculated to yield an instant non-periodic energy. This instant non-periodic energy is added to the offset value to yield an adapted threshold. The value of the best match of the sync mark pattern is compared with the adapted threshold. Where the value is less than the adapted threshold, a sync mark is identified as found. Otherwise, a sync mark is not found. As the non-periodic energy corresponds to the signal to noise ratio in the received series of data samples, the adaptive threshold varies as a function of the instant signal to noise ratio in the received series of digital samples.

Turning toFIG. 1, a storage medium1is shown with two exemplary tracks20,22indicated as dashed lines. The tracks are segregated by servo data written within wedges19,18. These wedges include servo data10that are used for control and synchronization of a read/write head assembly over a desired location on storage medium1. In particular, the servo data generally includes a preamble pattern11followed by a servo address mark12(SAM). Servo address mark12is followed by a Gray code13, and Gray code13is followed by burst information14. It should be noted that while two tracks and two wedges are shown, hundreds of each would typically be included on a given storage medium. Further, it should be noted that a servo data set may have two or more fields of burst information. Yet further, it should be noted that different information may be included in the servo fields such as, for example, repeatable run-out information that may appear after burst information14.

Between the servo data bit patterns10aand10b, a user data region16is provided. User data region16may include one or more sets of data that are stored to storage medium1. The data sets may include user synchronization information some of which may be used as a mark to establish a point of reference from which processing of the data within user data region16may begin processing.

In operation, storage medium1is rotated in relation to a sensor that senses information from the storage medium. In a read operation, the sensor would sense servo data from wedge19(i.e., during a servo data period) followed by user data from a user data region between wedge19and wedge18(i.e., during a user data period) and then servo data from wedge18. In a write operation, the sensor would sense servo data from wedge19then write data to the user data region between wedge19and wedge18. Then, the sensor would be switched to sense a remaining portion of the user data region followed by the servo data from wedge18. Once the user data region is reached, a user sync mark50is detected and used as a reference point from which data processing is performed. User sync mark50is preceded by a user preamble51.

As used herein, the phrase “sync mark” is used in its broadest sense to mean any pattern that may be used to establish a point of reference. Thus, for example, a sync mark may be user sync mark50as is known in the art, or one or more portions of servo data bit patterns10. Based upon the disclosure provided herein, one of ordinary skill in the art may recognize other sync marks that could be used in relation to different embodiments of the present invention.

Various embodiments of the present invention provide data processing systems that include: a pattern detector circuit, and a comparator circuit. The pattern detector circuit is operable to generate a pattern value based upon a comparison of a defined pattern to a first portion of a received input. The comparator circuit is operable to compare the pattern value to an adapted threshold, and to selectively assert a pattern found signal based at least in part on the comparison of the pattern value and the adapted threshold. The adapted threshold is adjusted based at least in part on a noise component of a second portion of the received input. In some cases, the systems are implemented as part of an integrated circuit.

In various embodiments of the present invention, the first portion of the received input is exclusive of the second portion of the received input. In one or more instances of the aforementioned embodiments, the first portion of the received input includes a sync mark, and the second portion of the received input includes a periodic pattern. The periodic pattern may be for example, a 2T preamble pattern. In some instances of the aforementioned embodiments, the data processing system is implemented as part of a storage device, and the received input is derived from a storage medium included in the storage device. In other instances of the aforementioned embodiments, the data processing system is implemented as part of a communication device, and the received input is derived from a transfer medium.

In one or more instances of the aforementioned embodiments, the data processing system further includes a threshold adaptation circuit operable to adjust the adapted threshold based at least in part on the second portion of the received input. In some cases, the threshold adaptation circuit is operable to calculate a noise component of the second portion of the received input, and to add the noise component to an offset value to yield the adapted threshold. In various cases, the threshold adaptation circuit includes a noise calculation circuit operable to calculate a noise component of the second portion of the received input, and a summation circuit operable to add the noise component to an offset value to yield the adapted threshold. In one particular case, the threshold adaptation circuit further includes: a pattern matching circuit operable to compare a defined periodic pattern with the second portion of the received input to yield a first best match value and a second best match value; an averaging circuit operable to average the first best match value and the second best match value to yield an interim value, to calculate a first running average of multiple interim values generated from multiple instances of the second portion of the received input, and to provide the first running average as a trained output; a noise averaging circuit operable to calculate a second running average of the noise components generated from multiple instances of the second portion of the received input, and to provide the second running average as an average noise component; and a summation circuit operable to subtract the average noise component from the trained output to yield the offset value. In various cases, the noise calculation circuit includes: a finite impulse response filter operable to filter the second portion of the received input to yield a filtered output; and a sum of squares circuit operable to sum the squares of elements of the filtered output to yield the noise component.

Other embodiments of the present invention provide methods for detecting a data pattern. The methods include: receiving an input data set; comparing the input data set with a defined pattern to yield a pattern value using a pattern comparison circuit; comparing the pattern value to an adapted threshold; and selectively asserting a pattern found signal based at least in part on the comparison of the pattern value and the adapted threshold. The adapted threshold is adjusted based at least in part on a noise component of a second portion of the received input. In some instances of the aforementioned embodiments, the methods further include: calculating a noise component of the second portion of the received input; and adding the noise component and an offset value to yield the adapted threshold. In some cases, the methods further include: comparing a defined periodic pattern with the second portion of the received input to yield a first best match value and a second best match value; averaging the first best match value and the second best match value to yield an interim value; calculating a first running average of multiple interim values generated from multiple instances of the second portion of the received input where the first running average is provided as a trained output; calculating a second running average of the noise components generated from multiple instances of the second portion of the received input, where the second running average is provided as an average noise component; and subtracting the average noise component from the trained output to yield the offset value. In one or more instances of the aforementioned embodiments, calculating a noise component includes: applying an finite impulse response filtering to the second portion of the received input to yield a filtered output; and summing the squares of elements of the filtered output to yield the noise component.

Turning toFIG. 2a, an adaptive threshold sync mark detector circuit200is shown in accordance with one or more embodiments of the present invention. Adaptive threshold sync mark detector circuit200includes an equalizer circuit213that receives a data input210and provides an equalized output215. In some embodiments, equalizer circuit213is a digital finite impulse response filter as are known in the art. Data input210may be a series of digital samples. The digital samples may represent, for example, data stored on a storage medium or data received via a wireless communication medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of data input210.

Equalizer output215is provided to a sync pattern match calculation circuit289a. Sync pattern match calculation circuit289acompares equalizer output215with different successive combinations of the periodic pattern275aand subsequent portions of a sync mark pattern274a. Sync mark pattern274ais received from a sync pattern273a. Sync pattern273amay be hardwired or user programmable depending upon the particular implementation. Preamble pattern275ais received from a preamble pattern274athat may be hardwired or user programmable. In some embodiments of the present invention, preamble pattern274ais a defined four bit pattern (‘1100’ or ‘0011’) referred to as a 2T pattern as it repeats every two periods (i.e., T). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other periodic patterns that may be used in relation to different embodiments of the present invention. In some embodiments of the present invention, the preamble is twenty bits long. This may be, for example, created as five repetitions of a four bit 2T pattern (i.e., ‘00110011001100110011’).

FIG. 2bgraphically shows comparisons yielding the various outputs of a sync pattern match calculation circuit289athat were described above. In particular, a time line296shows N-bit preamble pattern275repeated a number of times (i.e., elements281a,281b,281c,281d,281e) and a number of different N-bit portions (i.e., elements282,283,284,285,286) of sync mark pattern276lined up in time as they would be expected to be received as part of an incoming data stream. As shown, sync match output231corresponds to a comparison (e.g., a Euclidean difference) between equalizer output215and the five consecutive N-bit portions282,283,284,285,286of sync mark pattern276. Sync plus N match output232corresponds to a comparison (e.g., a Euclidean difference) between equalizer output215and one N-bit portion of the preamble281eappended with the four least recent N-bit portions282,283,284,285of sync mark pattern276. Sync plus 2N match output233corresponds to a comparison (e.g., a Euclidean difference) between equalizer output215and two N-bit portions of the preamble281d,281eappended with the three least recent N-bit portions282,283,284of sync mark pattern276. Sync plus 3N match output234corresponds to a comparison (e.g., a Euclidean difference) between equalizer output215and three N-bit portions of the preamble281c,281d,281eappended with the two least recent N-bit portions282,283of sync mark pattern276. Sync plus 4N match output235corresponds to a comparison (e.g., a Euclidean difference) between equalizer output215and four N-bit portions of the preamble281b,281c,281d,281eappended with the least recent N-bit portion282of sync mark pattern276.

Each of sync match231a, sync plus N match232a, sync plus 2N match233a, sync plus 3N match234a, sync plus 4N match235aare provided to a top two match identification circuit241that selects a best match245and a second best match246to be provided to an averaging circuit250. Best match245is selected by top two match identification circuit241to be the value of the one of sync match231a, sync plus N match232a, sync plus 2N match233a, sync plus 3N match234a, sync plus 4N match235athat exhibits the lowest value. Second best match246is selected by top two match identification circuit241to be the value of the one of sync match231a, sync plus N match232a, sync plus 2N match233a, sync plus 3N match234a, sync plus 4N match235athat exhibits the second lowest value. Averaging circuit250averages the current best match245with the current second best match246to yield an interim average value, and maintains a running average of the interim average values over a number of instances of periodic patterns. The resulting running average is provided as a trained threshold252.

In addition, non-periodic energy associated with the periodic pattern (i.e., noise) is calculated. This is done by filtering equalized output215over the period corresponding to the periodic pattern using a filter circuit224. Filter circuit224may be, for example, a finite impulse response filter that operates based on taps223provided from a filter taps register222. Taps223may be programmable or fixed depending upon the particular implementation. In one particular embodiment where the periodic pattern is a 2T pattern, five taps (i.e., 1, 0, 0, 0, −1) are uses as taps223. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other filters that may be used to generate a value corresponding to the non-periodic energy or noise in the periodic pattern.

Filter circuit224provides a filtered output225to a sum of squares calculation circuit287that sums the squares of all the values of filtered output225within a window of time surrounding the periodic pattern to yield an instant non-periodic energy292representing the noise energy for the currently processing periodic pattern. Of note, this noise energy corresponds to the signal to noise ratio of the periodic pattern (i.e., the signal to noise ratio decreases when the noise energy increases, and increases when the noise energy decreases).

Instant non-periodic energy292is provided to an averaging circuit293that maintains a running average of the instant non-periodic energy292values over the same number of instances of periodic patterns used to yield trained threshold252. The resulting running average is provided as an average non-periodic energy201. Average non-periodic energy201is provided to a summation circuit255where it is subtracted from trained threshold252to yield an offset value257. Offset value257is updated over a training period, and at the end of the training period is stored to an offset buffer circuit260as indicated by a training hold input263. Offset value257is provided as offset value262from offset buffer circuit260. Training hold input263is de-asserted during the training period when periodic patterns are repeatedly processed. In some embodiments of the present invention, offset value262is generated based upon processing a thousand or more instances of the periodic pattern. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of numbers of instances of the periodic pattern that may be processed to yield offset value262.

The training process (i.e., repeatedly processing periodic data) may be performed under different conditions to yield different values of offset value262corresponding to the different conditions. For example, where the sync mark data is being derived from a storage medium, different values for offset value262may be used for different zones on the storage medium. The particular value of offset value may then be selected depending upon the condition during standard processing.

During standard processing (i.e., non-training mode), equalizer output215is processed by a sync pattern match calculation circuit284b. Sync pattern match calculation circuit284bis identical to pattern match calculation circuit284a. In some embodiments of the present invention, pattern match calculation circuit284aand pattern match calculation circuit284aare implemented as the same circuit providing the functionality of pattern match calculation circuit284aduring a training mode and the functionality of pattern match calculation circuit284bduring a standard mode. Sync match231b, sync plus N match232b, sync plus 2N match233b, sync plus 3N match234b, sync plus 4N match235bare provided to a best match identification circuit291that provides the lowest value of sync match231b, sync plus N match232b, sync plus 2N match233b, sync plus 3N match234b, or sync plus 4N match235bas a best sync output295. Best sync output295is provided to a threshold comparator circuit297.

Also during standard processing, instant non-periodic energy292for the periodic pattern in the currently processing equalized output215is provided to a summation circuit203where it is added to offset value262that was generated during the training mode and stored to offset buffer circuit260. The output of summation circuit205is an adaptive threshold value205. Of note, instant non-periodic energy292corresponds to the signal to noise ratio of the currently processing periodic pattern (i.e., the signal to noise ratio decreases when instant non-periodic energy292increases, and increases when instant non-periodic energy292decreases). Adaptive threshold value205is provided to threshold comparator circuit297where it is compared to best sync output295. Where best sync output295is less than adaptive threshold value205, a sync found299is asserted.

Turning toFIG. 3, another adaptive threshold sync mark detector circuit300in accordance with other embodiments of the present invention. Adaptive threshold sync mark detector circuit300includes an equalizer circuit313that receives a data input310and provides an equalized output315. In some embodiments, equalizer circuit313is a digital finite impulse response filter as are known in the art. Data input310may be a series of digital samples. The digital samples may represent, for example, data stored on a storage medium or data received via a wireless communication medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of data input310.

Equalizer output315is provided to a periodic energy calculation circuit320. Periodic energy calculation circuit320may be any circuit known in the art that approximates the energy associated with a periodic signal. As one example, periodic energy calculation circuit320may calculate sine and cosine components of each sample of equalizer output315corresponding to the periodic sample and then perform a sum of squares of the sine and cosine components to yield an interim energy. This interim energy value is then divided by the number of samples to yield a periodic energy336(i.e., signal energy associated with the periodic signal). Periodic energy336is provided to a signal to noise calculation circuit341. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other approaches and circuits that may be used to generate a value corresponding to the periodic energy or signal in the periodic pattern.

In addition, non-periodic energy associated with the periodic pattern (i.e., noise) is calculated. This is done by filtering equalized output315over the period corresponding to the periodic pattern using a filter circuit324. Filter circuit324may be, for example, a finite impulse response filter that operates based on taps323provided from a filter taps register322. Taps323may be programmable or fixed depending upon the particular implementation. In one particular embodiment where the periodic pattern is a 2T pattern, five taps (i.e., 1, 0, 0, 0, −1) are uses as taps323. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other filters that may be used to generate a value corresponding to the non-periodic energy or noise in the periodic pattern.

Filter circuit324provides a filtered output325to a sum of squares calculation circuit387that sums the squares of all the values of filtered output325within a window of time surrounding the periodic pattern to yield a non-periodic energy output389representing the noise energy for the currently processing periodic pattern. Of note, this noise energy corresponds to the signal to noise ratio of the periodic pattern (i.e., the signal to noise ratio decreases when the noise energy increases, and increases when the noise energy decreases). Non-periodic energy389is also provided to signal to noise ratio calculation circuit341. Signal to noise ratio calculation circuit341calculates a signal to noise ratio352of the currently processing periodic pattern. In one particular embodiment, the calculated signal to noise ratio352is calculated in accordance with the following equation:

Signal to noise ratio352is provided to a summation circuit362where it is added to a predefined offset value programmed or hardwired as offset value360. Offset value360may be determined at the factory upon manufacture, or may be developed during a training mode of operation, and is selected such that when it is added to signal to noise ratio352it will provide a desired adaptive threshold value305. Offset value360may be multiple values that are selected between based upon a particular operation. For example, where the sync mark data is being derived from a storage medium, different values for offset value360may be used for different zones on the storage medium. Adaptive threshold value305is provided to threshold comparator circuit397.

In parallel, equalizer output315is processed by a sync pattern match calculation circuit384. Sync pattern match calculation circuit384compares equalizer output315with different successive combinations of the periodic pattern and subsequent portions of a sync mark pattern374. Sync mark pattern374is received from a sync pattern373. Sync pattern373may be hardwired or user programmable depending upon the particular implementation.FIG. 2cgraphically shows comparisons yielding the various outputs of a sync pattern match calculation circuit384that were described above. The results of the comparison process (i.e., sync match331, sync plus N match332, sync plus 2N match333, sync plus 3N match334, sync plus 4N match335) are provided to a best match identification circuit391that provides the lowest value of sync match331, sync plus N match332, sync plus 2N match333, sync plus 3N match334, or sync plus 4N match335as a best sync output395. Best sync output395is provided to a threshold comparator circuit397where it is compared to adaptive threshold value305. Where best sync output395is less than adaptive threshold value305, a sync found399is asserted.

Turning toFIG. 4, a data processing circuit400including an adaptive threshold sync mark detection circuit is shown in accordance with some embodiments of the present invention. Data processing circuit400includes an analog front end circuit410that receives an analog input408. Analog front end circuit410processes analog input408and provides a processed analog signal412to an analog to digital converter circuit415. Analog front end circuit410may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit410. In some cases, analog input408is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog input408is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources from which analog input408may be derived.

Analog to digital converter circuit415converts processed analog signal412into a corresponding series of digital samples417. Analog to digital converter circuit415may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples417are provided to an equalizer circuit420. Equalizer circuit420applies an equalization algorithm to digital samples417to yield an equalized output422. In some embodiments of the present invention, equalizer circuit420is a digital finite impulse response filter circuit as are known in the art.

Equalized output422is provided to a data detector circuit425, a sample buffer circuit475, and an adaptive threshold sync mark detection circuit490. Adaptive threshold sync mark detection circuit490may be implemented similar to that set forth above in relation toFIG. 2a-2c, or that set forth above in relation toFIG. 3. Adaptive threshold sync mark detection circuit490applies the aforementioned adaptive sync mark detection algorithm to identify a possible sync marks. The identified sync mark is used to generate a framing signal493that is used to indicate a location of the beginning of a user data set within equalized output422.

Sample buffer circuit475stores equalized output422as buffered data477for use in subsequent iterations through data detector circuit425. Data detector circuit425may be any data detector circuit known in the art that is capable of producing a detected output427. As some examples, data detector circuit425may be, but is not limited to, a Viterbi algorithm detector circuit or a maximum a posteriori detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. Detected output425may include both hard decisions and soft decisions. The terms “hard decisions” and “soft decisions” are used in their broadest sense. In particular, “hard decisions” are outputs indicating an expected original input value (e.g., a binary ‘1’ or ‘0’, or a non-binary digital value), and the “soft decisions” indicate a likelihood that corresponding hard decisions are correct. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of hard decisions and soft decisions that may be used in relation to different embodiments of the present invention.

Detected output427is provided to a central queue memory circuit460that operates to buffer data passed between data detector circuit425and data decoder circuit450. In some cases, central queue memory circuit460includes interleaving (i.e., data shuffling) and de-interleaving (i.e., data un-shuffling) circuitry known in the art. When data decoder circuit450is available, data decoder circuit450accesses detected output427from central queue memory circuit460as a decoder input456. Data decoder circuit450applies a data decoding algorithm to decoder input456in an attempt to recover originally written data. The result of the data decoding algorithm is provided as a decoded output452. Similar to detected output427, decoded output452may include both hard decisions and soft decisions. For example, data decoder circuit450may be any data decoder circuit known in the art that is capable of applying a decoding algorithm to a received input. Data decoder circuit450may be, but is not limited to, a low density parity check (LDPC) decoder circuit or a Reed Solomon decoder circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoder circuits that may be used in relation to different embodiments of the present invention. Where the original data is recovered (i.e., the data decoding algorithm converges) or a timeout condition occurs, decoded output452is stored to a memory included in a hard decision output circuit480. In turn, hard decision output circuit480provides the converged decoded output452as a data output484to a recipient (not shown). The recipient may be, for example, an interface circuit operable to receive processed data sets. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of recipients that may be used in relation to different embodiments of the present invention. Where the original data is not recovered (i.e., the data decoding algorithm failed to converge) prior to a timeout condition, decoded output452indicates that the data is unusable as is more specifically discussed below, and data output484is similarly identified as unusable.

Data decoder circuit453additionally provides a framing signal selection signal453to sync mark detection and framing circuit490that causes sync mark detection and framing circuit490to provide a next best framing signal493. Equalized output422is then re-processed using the new framing signal493indicating a different starting location of user data in equalized output422. In some embodiments of the present invention, framing signal selection signal453is asserted to cause another framing signal to be provided under particular conditions. Such conditions may include, for example, a failure of data decoder circuit450to converge after a defined number of global iterations, and/or where a number of unsatisfied checks exceed a defined level after a defined number of global iterations have occurred in relation to the currently processing data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of conditions upon which a next best framing signal is selected to restart the processing.

One or more iterations through the combination of data detector circuit425and data decoder circuit450may be made in an effort to converge on the originally written data set. As mentioned above, processing through both the data detector circuit and the data decoder circuit is referred to as a “global iteration”. For the first global iteration, data detector circuit425applies the data detection algorithm to equalized output422without guidance from a decoded output. For subsequent global iterations, data detector circuit425applies the data detection algorithm to buffered data477as guided by decoded output452. To facilitate this guidance, decoded output452is stored to central queue memory circuit460as a decoder output454, and is provided from central queue memory circuit460as a detector input429when equalized output422is being re-processed through data detector circuit425.

During each global iteration it is possible for data decoder circuit450to make one or more local iterations including application of the data decoding algorithm to decoder input456. For the first local iteration, data decoder circuit450applies the data decoder algorithm without guidance from decoded output452. For subsequent local iterations, data decoder circuit450applies the data decoding algorithm to decoder input456as guided by a previous decoded output452. The number of local iterations allowed may be, for example, ten. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of different numbers of local iterations that may be allowed in accordance with different embodiments of the present invention. Where the number of local iterations through data decoder circuit450exceeds that allowed, but it is determined that at least one additional global iteration during standard processing of the data set is allowed, decoded output452is provided back to central queue memory circuit460as decoded output454. Decoded output454is maintained in central queue memory circuit460until data detector circuit425becomes available to perform additional processing.

In contrast, where the number of local iterations through data decoder circuit450exceeds that allowed and it is determined that the allowable number of global iterations has been surpassed for the data set and/or a timeout or memory usage calls for termination of processing of the particular data set, standard processing of the data set concludes and an error is indicated. In some cases, retry processing or some offline processing may be applied to recover the otherwise unconverged data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of non-standard processing techniques that may be applied to recover the otherwise unrecoverable data set.

Turning to Fig. a flow diagram500show a method in accordance with one or more embodiments of the present invention for adaptive threshold sync mark detection. Following flow diagram500, an analog input is received (block505). The analog input may be derived from, for example, a storage medium or a data transmission channel. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog input. The analog input is converted to a series of digital samples (block510). This conversion may be done using an analog to digital converter circuit or system as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital values representing the received analog signal may be used. The resulting digital samples are equalized to yield an equalized output (block515). In some embodiments of the present invention, the equalization is done using a digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention.

It is determined whether a training period is underway (block520). A training period may be selected for example, at the start of operation, at manufacture, and/or at a time when the device does not appear to be functioning properly. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of instances when a training period may be selected. During the training period, several hundred or thousands of instances of a periodic pattern may be processed to yield a default offset value. While not shown in detail inFIG. 5, the training process (i.e., repeatedly processing periodic data) may be performed under different conditions to yield different values of the default offset value corresponding to the different conditions. For example, where the sync mark data is being derived from a storage medium, different values for the default offset value may be used for different zones on the storage medium. The particular value of offset value may then be selected depending upon the condition during standard processing.

Where a training period is underway (block520), matched filtering is applied to samples of the equalized output within a window during which the periodic pattern is expected to yield a first best match to the known periodic pattern and a second best match to the known periodic pattern (block525). The value of the first best match is averaged with the value of the second best match to yield an averaged match (block530), and a running average of the averaged match with instances of the averaged match generated for previous instances of the periodic pattern is performed to yield a Multi-instance average (block535). The multi-instance average is stored as a trained threshold (block540).

In parallel, samples of the equalized output corresponding to a window during which the periodic pattern is expected is filtered to yield a non-periodic energy (block545). A sum of the squares of the values of non-periodic energy corresponding to the respective samples of the equalized output is calculated, and an average of the respective sums of squares is calculated to yield an average trained non-periodic energy across a number of instances of the periodic pattern (block550). The average trained non-periodic energy value is then subtracted from the trained threshold to yield a threshold offset (block555). As previously mentioned, the threshold offset is calculated by averaging a number of instances of the averaged match and the sums of squares generated by processing multiple instances of the periodic data.

Where, on the other hand, a standard operation is ongoing (i.e., a training period is not selected) (block520), samples of the equalized output corresponding to a window during which the periodic pattern is expected is filtered to yield a non-periodic energy (block560), and a sum of the squares of the values of non-periodic energy corresponding to the respective samples of the equalized output is calculated to yield an instant non-periodic energy (i.e., noise included with the currently processing periodic pattern) (block565). This instant non-periodic energy is added to the threshold offset from block555to yield an adaptive threshold value (block570).

In parallel, a known sync mark pattern is compared to a series of samples from the equalized output to yield a sync match value (block575). The sync match value is compared with the adaptive threshold value (block580). It is then determined whether the sync match value is less than the adaptive threshold value (block585). Where the sync match value is less than the adaptive threshold value (block585), a sync found is asserted (block590).

Turning toFIG. 6, a communication system600including a receiver620with an adaptive threshold sync mark detector circuit is shown in accordance with different embodiments of the present invention. Communication system600includes a transmitter610that is operable to transmit encoded information via a transfer medium630as is known in the art. The encoded data is received from transfer medium630by receiver620. The adaptive threshold sync mark detector circuit included in receiver620may be similar to that discussed above in relation toFIGS. 2a-2c, and/orFIG. 3, and/or may operate in accordance with the method discussed above in relation toFIG. 5. In some cases, the adaptive threshold sync mark detector circuit is incorporated in a data processing circuit that itself is included in receiver620. In such cases, the data processing circuit may be similar to that discussed above in relation toFIG. 4.

In operation, a series of data samples are derived by receiver620from information received via transfer medium630. During a training period, a default threshold is calculated. This may be done, for example, by averaging the best match level of the series of data samples with the second best match level. In addition, an average energy resulting from other than a periodic pattern (e.g., a preamble patter preceding a sync mark pattern) is repeatedly calculated during the test period to yield an average non-periodic energy. This average non-periodic energy is subtracted from the default threshold to yield a offset value. Then, during normal operation, the best match of the series of data samples to the sync mark pattern is identified and the corresponding value calculated. In addition, the energy resulting from other than the periodic pattern is calculated to yield an instant non-periodic energy. This instant non-periodic energy is added to the offset value to yield an adapted threshold. The value of the best match of the sync mark pattern is compared with the adapted threshold. Where the value is less than the adapted threshold, a sync mark is identified as found. Otherwise, a sync mark is not found.

Turning toFIG. 7, a storage system700including a read channel circuit710with an adaptive threshold sync mark detector circuit is shown in accordance with various embodiments of the present invention. Storage system700may be, for example, a hard disk drive. Storage system700also includes a preamplifier770, an interface controller720, a hard disk controller766, a motor controller768, a spindle motor772, a disk platter778, and a read/write head776. Interface controller720controls addressing and timing of data to/from disk platter778. The data on disk platter778consists of groups of magnetic signals that may be detected by read/write head assembly776when the assembly is properly positioned over disk platter778. In one embodiment, disk platter778includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly776is accurately positioned by motor controller768over a desired data track on disk platter778. Motor controller768both positions read/write head assembly776in relation to disk platter778and drives spindle motor772by moving read/write head assembly to the proper data track on disk platter778under the direction of hard disk controller766. Spindle motor772spins disk platter778at a determined spin rate (RPMs). Once read/write head assembly778is positioned adjacent the proper data track, magnetic signals representing data on disk platter778are sensed by read/write head assembly776as disk platter778is rotated by spindle motor772. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter778. This minute analog signal is transferred from read/write head assembly776to read channel module764via preamplifier770. Preamplifier770is operable to amplify the minute analog signals accessed from disk platter778. In turn, read channel circuit710decodes and digitizes the received analog signal to recreate the information originally written to disk platter778. This data is provided as read data703to a receiving circuit. As part of decoding the received information, read channel circuit710performs a sync mark detection process. Such a sync mark detection process may be performed using the adaptive threshold sync mark detector circuit. The adaptive threshold sync mark detector circuit may be similar to that discussed above in relation toFIGS. 2a-2c, and/orFIG. 3, and/or may operate in accordance with the method discussed above in relation toFIG. 5. In some cases, the adaptive threshold sync mark detector circuit is incorporated in a data processing circuit that itself is included in read channel710. In such cases, the data processing circuit may be similar to that discussed above in relation toFIG. 4.

In operation, a series of data samples are derived by read channel710from information received from disk platter778. During a training period, a default threshold is calculated. This may be done, for example, by averaging the best match level of the series of data samples with the second best match level. In addition, an average energy resulting from other than a periodic pattern (e.g., a preamble patter preceding a sync mark pattern) is repeatedly calculated during the test period to yield an average non-periodic energy. This average non-periodic energy is subtracted from the default threshold to yield a offset value. Then, during normal operation, the best match of the series of data samples to the sync mark pattern is identified and the corresponding value calculated. In addition, the energy resulting from other than the periodic pattern is calculated to yield an instant non-periodic energy. This instant non-periodic energy is added to the offset value to yield an adapted threshold. The value of the best match of the sync mark pattern is compared with the adapted threshold. Where the value is less than the adapted threshold, a sync mark is identified as found. Otherwise, a sync mark is not found.

It should be noted that storage system700may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system700, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

A data decoder circuit used in relation to read channel circuit710may be, but is not limited to, a low density parity check (LDPC) decoder circuit as are known in the art. Such low density parity check technology is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as DRAM, NAND flash, NOR flash, other non-volatile memories and solid state drives.

In addition, it should be noted that storage system700may be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter778. This solid state memory may be used in parallel to disk platter778to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit710. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered by disk platted778. In such a case, the solid state memory may be disposed between interface controller720and read channel circuit710where it operates as a pass through to disk platter778when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter778and a solid state memory.