Termination region of a semiconductor device

In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.

TECHNICAL FIELD

This description relates to termination regions of a semiconductor device.

BACKGROUND

Implementations of trench-gate type devices (e.g., planar-gate metal-oxide-semiconductor field effect transistor (MOSFET) transistors, vertical gate MOSFET transistors, insulated-gate bipolar transistors (IGBTs), rectifiers, and synchronous rectifiers) can include an array of trenches (e.g., parallel trenches) formed in the top surface of the semiconductor die, with each trench filled with a dielectric, a shield electrode and/or a gate electrode, depending upon the type of power device. The trenches can define a corresponding array of mesas (or mesa regions), where each mesa being disposed between adjacent trenches. Depending upon the device implemented on the die, various electrodes and/or doped regions are disposed at the top of the mesa. One or more of the mesas and adjacent trenches can implement a small instance of the device, and the small instances can be coupled together in parallel to provide the whole power semiconductor device. The device can have an ON state where a desired current flows through the device, an OFF state where current flow is substantially blocked in the device, and a breakdown state where an undesired current flows due to an excess off-state voltage being applied between the current conducting electrodes of the device. The voltage at which breakdown is initiated is called the breakdown voltage. Each mesa and adjacent trenches are configured to provide a desired set of ON-state characteristics and breakdown voltage. The configuration of the mesa and trenches can result in a variety of trade-offs between achieving desirable ON-state characteristics, relatively high breakdown voltage, and desirable switching characteristics.

A power semiconductor die can have an active area where the array of mesas and trenches that implement the device are located, a field termination area around the active area, and an inactive area where interconnects and channel stops may be provided. The field termination area can be used to minimize the electric fields around the active area, and may not be configured to conduct current. The breakdown voltage of the device can be determined by the breakdown processes associated with the active area. However, various breakdown processes in the field termination area and inactive area at significantly lower voltages can occur in an undesirable fashion. These breakdown processes may be referred to as passive breakdown processes or as parasitic breakdown processes.

Known field termination areas that have higher breakdown voltages than the active area have been configured, however such known configurations often compromise total die area, processing costs, performance characteristics, and/or so forth. Thus, a need exists for systems, methods, and apparatus to address the shortfalls of present technology and to provide other new and innovative features.

SUMMARY

In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region. The apparatus can include a dielectric lining a bottom portion of the trench where the dielectric has a first portion disposed in the termination region of the semiconductor region and a second portion disposed in the active region of the semiconductor region. The first portion of the dielectric disposed in the termination region can have a vertical thickness greater than a vertical thickness of the second portion of the dielectric disposed in the active region.

DETAILED DESCRIPTION

FIG. 1Ais a diagram that illustrates a side cross-sectional view of an active region102and a termination region104associated with a portion of a semiconductor device100.FIG. 1Bis a top view of the semiconductor device100cut along line B1 shown inFIG. 1A. The side cross-sectional view of the portion of the semiconductor device100is cut along line B2 of the top view of the semiconductor device100shown inFIG. 1B.

As shown inFIG. 1A, a trench110A included in the semiconductor device100has a portion113in the termination region104and has a portion111in the active region102. A dielectric112(e.g., an oxide) is disposed in the trench110A. Also, a shield electrode120(e.g., a shield polysilicon electrode) and a gate electrode130(e.g., a gate polysilicon electrode) insulated from the shield electrode120by an inter-electrode dielectric (IED)140are disposed in the trench110A. A perimeter trench190is also included in the semiconductor device100. At least a portion of the dielectric112and at least a portion of the shield electrode120are also disposed in the perimeter trench190. The dielectric112can be the combination of more than one dielectric that can be formed using one or more dielectric formation processes (e.g., deposition processes, growth processes).

As shown inFIG. 1A, the trench110A has a length aligned along a longitudinal axis A1 (also can be referred to as a horizontal direction). The shield electrode120, the inter-electrode dielectric140, and the gate electrode130are vertically stacked within the trench110A along a vertical axis A2 (also can be referred to as a vertical direction), which is substantially orthogonal to the longitudinal axis A1. In this implementation, the perimeter trench190is aligned along a longitudinal axis A3 (shown inFIG. 1B) so that the longitudinal axis A3 is substantially orthogonal to the longitudinal axis A1 and the vertical axis A2.

The trench110A is aligned parallel to additional trenches including, for example, trench110B shown inFIG. 1B. A mesa region160is disposed between the trench110A and the trench110B. In other words, the mesa region160is defined, at least in part by, a sidewall of the trench110A and a sidewall of the trench110B.

Although not shown inFIG. 1, the active region of the semiconductor device100can include, or can define, one or more vertical metal-oxide-semiconductor field effect transistor (MOSFET) devices. The vertical MOSFET device(s) can be activated via, for example, the gate electrode130. Many of the elements of the semiconductor device100are formed within an epitaxial layer108, which can be formed within or on a substrate107(e.g., an n-type substrate, a p-type substrate). As shown inFIG. 1A, the semiconductor device100has a drain contact106(e.g., a back-side drain contact).

In some implementations, the elements within the termination region104, and specifically, within a portion150of the termination region104associated with, for example, the trench110A can be configured to avoid undesirable events such as voltage breakdown at the edges of, for example, the active region102of the semiconductor device100. Also, the termination region104can be configured so that the dimensions of the semiconductor device100can be optimized to achieve desirable performance characteristics of the semiconductor device100such as a relatively low on-resistance, a relatively high off-resistance, a breakdown voltage or reverse blocking voltage, a desirable electric field profile, faster switching speeds, and/or so forth. Specifically, the termination region104can have features that are configured so that other dimensions of the semiconductor device100in the active region102can be configured for desirable performance characteristics. For example, the termination region104can be configured so that trench depths, pitches between trenches, doping levels, and/or so forth within the active region102can be optimized for processing efficiency, low cost, relatively small die area, and/or so forth.

As a specific example, when a potential (e.g., a potential of around zero volts) on a gate electrode is defined so that a semiconductor device is in an off-state, a substantial current can flow during a breakdown condition where a drain potential is high relative to a source potential. In the breakdown condition, relatively high electric fields can develop in a mesa region between trenches, and this high electric field can generate avalanche carriers (both holes and electrons) at a breakdown voltage. The breakdown voltage of the mesa region may be increased in a desirable fashion by configuring the elements of termination region such that the thickness of a dielectric within an active region of a trench can be decreased, a width of the mesa region can be decreased, a doping concentration in the drift region can be configured to cause the drift region to be normally depleted of electrons to support a charge-balanced condition, and/or so forth. In some implementations, the elements of the termination region can be configured so that the electric field during off-state conditions can be uniformly distributed along a centerline of the mesa region (e.g., a square-shaped or rectangular-shaped electric field profile) in a desirable fashion, thereby reducing a peak electric field (and thereby increasing the voltage at which avalanche carriers can be generated).

While many of the implementations described herein are with respect to a MOSFET device, the implementations described herein can also be applied to other device types, such as IGBT devices, rectifiers, and particularly in devices in which the above-described charge-balanced conditions exist. Additionally, in this description, the various implementations of are described, for purposes of illustration, as implementing n-type channel devices. However, in other implementations, the devices illustrated may be implemented a p-type channel devices (e.g., by using opposite conductivity types and/or biasing potentials).

FIG. 2is a cross-sectional diagram that illustrates a MOSFET device200, according to an implementation. The MOSFET device200includes MOSFET device MOS1 and a MOSFET device MOS2. Because the MOSFET devices MOS1, MOS2 have similar features, the MOSFET devices MOS1, MOS2 will generally be discussed in terms of a single MOSFET device MOS2 (that is mirrored in the other MOSFET device MOS1 and/or mirrored within the MOSFET device MOS2). The MOSFET device200can be, for example, relatively high voltage devices (e.g., greater than 30V, 60V devices, 100V devices, 300V devices).

As shown inFIG. 2the MOSFET device200is formed within an epitaxial layer236(e.g., N-type). Source regions233(e.g., N+ source regions) are disposed above body regions234(e.g., P-type) which is formed in the epitaxial layer236. The epitaxial layer can be formed on, or in a substrate (e.g., a N+ substrate) (not shown). Trench205extends through body region234and terminates in a drift region237within the epitaxial layer236(also can be referred to as an epitaxial region). Trench205includes a dielectric210(which can include one or more dielectric layers such as a gate dielectric218) disposed within the trench205. A gate electrode220and a shield electrode221are disposed within the trench205. The MOSFET devices200can be configured to operate by applying a voltage (e.g., a gate voltage) to the gate electrode220of the MOSFET device200which can turn the MOSFET device2000N by forming channels adjacent to the gate oxides218so that current may flow between the source regions233and a drain contact (not shown).

In accordance with the termination implementations described herein, the performance characteristics and dimensions of the MOSFET device200can be improved. For example, an ON-resistance of the MOSFET device200can be improved by approximately 50% (or more) and a pitch PH (and mesa region250width) between the MOSFET device MOS1 and the MOSFET device MOS2 can be decreased by approximately 20% (or more) with no decrease (or substantially no decrease) in breakdown voltage (while the MOSFET device200is OFF) and an increase in Qg-totalincrease of approximately 10% (or less). The increase in the ON-resistance of the MOSFET device200can be compensated for through an increase (e.g., a 30% increase) in dopant concentration within the epitaxial layer236—which is enabled by the termination implementations described herein. In addition, trench mask critical dimensions (CDs) (e.g., distances, sizes) can be decreased by approximately 10% or more, the shield electrode221widths can be decreased by more than 10%, contact252widths can be decreased by more than 50%, and/or so forth.

FIGS. 3A through 3Iare diagrams that illustrate configurations of a termination region according to some implementations.FIG. 3Ais a diagram that illustrates a plan view (or top view along the horizontal plane) of at least a portion of a semiconductor device300including an active region302and a termination region304.FIGS. 3B through 3Iare side cross-sectional views along different cuts (e.g., cuts F1 through F8) within the plan viewFIG. 3A. To simplify the plan view shown inFIG. 3Asome of the elements illustrated in the side cross-sectional views ofFIGS. 3B through 3Iare not shown. The side cross-sectional views along the different cuts included inFIGS. 3B through 3Iare not necessarily drawn to the same scale (e.g., numbers of trenches, etc.) as the plan view shown inFIG. 3A.

As shown inFIG. 3A, a plurality of trenches310, including for example trenches310A through310J, are aligned along a longitudinal axis D1 within the semiconductor device300. The plurality of trenches310can be referred to as parallel trenches. At least some portions of the plurality of trenches310can be included in the active region302and at least some portions of the plurality of trenches310can be included in the termination region302. For example, a portion of trench310B is included in the active region302and a portion of the trench310B is included in the termination region304. As shown inFIG. 3A, trench310G is entirely disposed within the termination region304.

In this implementation, the trench310D is entirely disposed within the termination region304and is the outermost trench from the plurality of trenches310. Accordingly, the trench310D can be referred to as an end trench. Trenches from the plurality of trenches310in the semiconductor device300that are lateral to (or interior to) the end trench310D can be referred to as interior trenches317(or as non-end trenches).

As shown inFIG. 3A, the active region302is defined by an area of the semiconductor device300that corresponds with at least one of a source contact region336(e.g., a source contact region336) or a shield dielectric edge region334. The source contact region336defines an area within the semiconductor device300where source contacts (such as source contact357shown inFIG. 3I) are formed. The source contact region336can also correspond with, for example, a source conductor region (e.g., a source metal region). The source contacts can be contacted with source implants (such as source implant363E within a mesa region360E between trenches310E and310F shown inFIG. 3I) of one or more active devices. A source formation region356inFIG. 3A(which can be referred to as a source exclusion edge) defines an area within which mesa regions between the plurality of trenches310are doped as doped source regions of active devices.

The shield dielectric edge region334shown inFIG. 3Acorresponds with (e.g., approximately corresponds with), for example, an edge341of the inter-electrode dielectric340shown inFIG. 3B(which is a side cross-sectional view cut along line F1). In some implementations, at least a portion of the inter-electrode dielectric340can include a gate dielectric such as gate dielectric portion342shown inFIG. 3B.

As shown inFIG. 3A, the termination region304includes areas of the semiconductor device300outside of (e.g., excluded by) the active region302. Accordingly, the termination region304, similar to the active region302, is defined by at least one of the source contact region336or the shield dielectric edge region334.

As shown inFIG. 3A, a transverse trench380A is aligned along a longitudinal axis D2 that is orthogonal to (e.g., substantially orthogonal to) the longitudinal axis D1. In other words, the transverse trench380A intersects in an orthogonal direction, the plurality of trenches310. Accordingly, the transverse trench380A can be considered to be in fluid communication with, for example, trench310A. In some implementations, the transverse trench380A may intersect only a portion of the plurality of trenches310. In some implementations, the transverse trench380A can be referred to as an end of trench trench (EOTT) or as a perpendicular trench because the transverse trench380A is perpendicularly oriented with respect to the parallel trenches (i.e., the plurality of trenches310). In some implementations, the directions along the longitudinal axis D2 can be referred to as a lateral direction. For example, trench310A can be referred to as being lateral to trench310G.

In this implementation, the transverse trench380A is disposed entirely within the termination region304. Although not shown inFIG. 3A, in some implementations, the transverse trench380A can have a least a portion disposed within the active region302.

In this implementation, portions of the plurality of trenches310(that are interior trenches317and) disposed to the left of the transverse trench380A can be referred to as trench extension portions314. Portions of the plurality of trenches310(that are interior trenches317and) disposed to the right of the transverse trench380A and extend into (or toward) the active region302can be referred to as main trench portions312. For example, trench310A includes a trench extension portion314A on the left side of the transverse trench380A (toward the perimeter and in a distal direction away the active region302) and the trench310A includes a main trench portion312A on the right side of the transverse trench380A (away from the perimeter and in a proximal direction toward the active region302). In this implementation, at least a portion of the main trench portion312A is included in (e.g., disposed within) the termination region304, and a portion of the main trench portion312A is included in (e.g., disposed within) the active region302. In some implementations, the transverse trench380A can be considered to be included in the trench extension portion314A. In this implementation, the trench extension portions314can define at least a portion of a mesa (when viewed in a side cross-sectional view).

Although only one transverse trench is included in the semiconductor device300, in some implementations, more than one transverse trench similar to transverse trench380A can be included in the semiconductor device300. For example, an additional transverse trench aligned parallel to the transverse trench380A can be disposed within the trench extension portion314A.

FIG. 3Bis a diagram that illustrates a side cross-sectional view of the semiconductor device300cut along line F1. The cut line F1 is approximately along a centerline of the trench310A so that the side cross-sectional view of the semiconductor device300is along a plane that approximately intersects a center of the trench310A. A portion of the transverse trench380A, which intersects the trench310A, is shown inFIG. 3B. A side cross-sectional view of the transverse trench380A cut along line F2, which is within the mesa region360A between the trench310A and the trench310B, is shown inFIG. 3C. As shown inFIG. 3C, a well region362A is formed (e.g., formed in a self-aligned fashion) in an area of the epitaxial layer308that is not blocked by the surface gate electrode322and the surface shield electrode332. The features shown inFIG. 3Bare disposed in an epitaxial layer308of the semiconductor device300. Other portions of the substrate, drain contact, and/or so forth are not shownFIGS. 3A through 3I. Many of the views associated with other figures are disposed in an epitaxial layer and similarly do not show the substrate, drain contact, and so forth.

As shown inFIG. 3B, the trench310A includes a dielectric370A disposed therein. Specifically, a portion of the dielectric370A is coupled to (e.g., lines, is disposed on) a sidewall and a portion of the dielectric370A is coupled to a bottom surface of the trench310A within the main trench portion312A of the trench310A. In this cross-sectional view the portion of the dielectric370A coupled to the bottom surface of the trench310A is shown, and the portion of the dielectric370A coupled to the sidewall of the trench310A is not shown. In some implementations, the portion of the dielectric370A shown inFIG. 3Balong the bottom surface of the main trench portion312A of the trench310A can be referred to as a bottom dielectric. In some implementations, the dielectric370A can be coupled to, or can include, a field dielectric374(which can be referred to as a field dielectric portion).

As shown inFIG. 3B, a gate electrode320A and a portion331A of a shield electrode330A are disposed in a portion of the main trench portion312A that is included in the active region302of the semiconductor device300. The gate electrode320A and the shield electrode330A are separated by at least a portion of the inter-electrode dielectric340. The portion of the main trench portion312A included in the termination region304has a portion333A of the shield electrode330A disposed therein and insulated from the epitaxial layer308by the dielectric370A. In some implementations, the portion333A of the shield electrode330A can be referred to as a termination region portion of the shield electrode, and the portion331A of the shield electrode330A can be referred to as an active region portion of the shield electrode.

In this implementation, a surface shield electrode332is coupled to the shield electrode330A, and a surface gate electrode322is coupled to the gate electrode320A. The surface electrode332is insulated from the surface gate electrode322by at least a portion of the inter-electrode dielectric340. A gate runner conductor352is coupled to the surface gate electrode322using a via351. Similarly, a source runner conductor354(which is also coupled to a source) is coupled to the surface shield electrode332using a via353through an opening in the surface gate electrode322.

As shown inFIG. 3A, an edge of the surface shield electrode332is disposed between the perimeter trenches390A,390B and an edge of the surface gate electrode322. The surface gate electrode322has at least a portion disposed between at least a portion of the gate runner conductor352and the surface electrode332. The surface gate electrode322also has at least a portion disposed between at least a portion of the source runner conductor354and the surface electrode332. As shown inFIG. 3B, the surface electrode332and surface gate electrode322are disposed between at least a portion of a field dielectric374and an interlayer dielectric (ILD)392.

Although not shown inFIGS. 3A through 3I, semiconductor device300can exclude the surface shield electrode332and/or the surface gate electrode322. In other words, the semiconductor device300(or a portion thereof) can be configured without the surface electrode332and/or the surface gate electrode322. More details related to such implementations are described below.

As shown inFIG. 3B, a portion372A of the dielectric370A (also referred to as an extension portion of the dielectric or as an extension dielectric) is included in the trench extension portion314A. The portion372A of the dielectric370A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the trench extension portion314A of the trench310A to at least a top of the trench310A. The top of the trench310A (which includes the trench portion314A and the main trench portion312A) is aligned along a plane D4, which is aligned along a top surface of a semiconductor region of the semiconductor device300. In some implementations, the semiconductor region of the semiconductor device300can correspond approximately with a top surface of the epitaxial layer308. In some implementations, the dielectric370A can include one or more dielectric layers and/or one or more dielectric types formed using one or more different formation processes.

As shown inFIG. 3B, a portion371A of the dielectric370A is included in the transverse trench380A. The portion371A of the dielectric370A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the transverse trench380A to at least a top of the transverse trench380A. The top of the transverse trench380A is aligned along the plane D4. The transverse trench380A (and such similar transverse trenches in other implementations) can help to eliminate relatively high electric fields along the corner (bottom, left inFIG. 3B) of the shield electrode330A.

The thickness of the dielectric370A included in the trench310A varies along the longitudinal axis D1 of the trench310A. The portion372A of the dielectric370A included in the trench extension portion314A has at least a thickness E1 in the trench extension portion314A (also can be referred to as a height because it is aligned along the vertical axis D3) that is greater than a thickness E2 of a portion of the dielectric370A included in the main portion312A (both in a termination region portion and in an active region portion) of the trench310A. The thickness of the portion372A of the dielectric370A extends up to a bottom surface of a surface shield electrode332beyond the thickness E1. The thickness E1 corresponds approximately with a depth (along the vertical direction D3) of the trench extension portion314A.

Also, the portion371A of the dielectric370A included in the transverse trench380A has at least a thickness E4 (also can be referred to as a height) that is greater than the thickness E2 of a portion of the dielectric370A included in the main portion312A of the trench310A and/or the thickness E1 of the portion372A of the dielectric370A included in the trench extension portion314A. The thickness of the portion371A of the dielectric370A shown inFIG. 3Bextends up to a bottom surface of a surface shield electrode332beyond the thickness E4. The thickness E4 corresponds approximately with a depth (along the vertical direction D3) of the transverse trench380A. The depth (or height) of the transverse trench380A is also illustrated within the mesa region360A shown inFIG. 3C. Accordingly, a depth of the trench310A varies along the longitudinal axis D1 from depth E3 to depth E1 through depth E4 of the transverse trench380A.

Referring back toFIG. 3B, in this implementation, the trench extension portion314A includes the portion372A of the dielectric370A and excludes a shield dielectric. Similarly, in this implementation, the transverse trench380A includes the portion371A of the dielectric370A and excludes the shield dielectric330A. Although not shown, in some implementations, a trench extension portion such as the trench extension portion314A can include a portion of a shield dielectric (e.g., a portion of a shield dielectric, a recessed shield dielectric). Similarly, although not shown, in some implementations, a transverse trench such as the transverse trench380A can include a portion of a shield dielectric (e.g., a portion of a shield dielectric, a recessed shield dielectric).

Although not shown inFIG. 3B, in some implementations, the thickness E2 of the portion of the dielectric370A in the main portion312A of the trench310A can vary along the longitudinal axis D1. For example, a thickness of a portion of the dielectric370A included in the termination region304of the main trench portion312A can be greater than a thickness of a portion of the dielectric370A included in the active region302of the main trench portion312A, or vice versa. As shown inFIG. 3B, an equal potential ring or channel stopper395can be included in the semiconductor device300.

In this implementation, the transverse trench380A has a depth (which corresponds with E4) that is the same as, or approximately equal to, a depth (which corresponds with E3) of the main trench portion312A and is greater than a depth (which corresponds with E1) of the trench extension portion314A. Although not shown inFIGS. 3A through 3I, in some implementations, the transverse trench380A can have a depth that is greater than a depth of the main trench portion312A. Although not shown inFIGS. 3A through 3I, in some implementations, the transverse trench380A can have a depth that is less than a depth of the main trench portion312A and/or is less than a depth of the trench extension portion314A. In some implementations, a depth (which corresponds with E3) of the main trench portion312A can be the same as a depth (which corresponds with E1) of the trench extension portion314A.

As shown inFIG. 3B, a length E16 of the trench extension portion314A of the trench310A is longer than a length E17 of a portion of the main trench portion312A of the trench310A included in the termination region304(up to the edge341of the gate dielectric portion342of the IED340). Although not shown, in some implementations, the length E16 trench of extension portion314A of the trench310A can be equal to or shorter than the length E17 of the portion of the main trench portion312A of the trench310A included in the termination region304.

The trench extension314A (and trench extensions shown in other implementations) can eliminate a high electric field near the end of the trench310A, thus increasing stability, reliability, and breakdown voltage of the semiconductor device300(and associated termination region304). The trench extension314A can also mitigate high lateral electric fields toward the end of the trench310A (along direction D1 toward the left) and along the surface of the mesa360A (shown inFIG. 3C) adjacent trench310A. By maintaining breakdown in the active region302, the on-resistance of the active region302can be minimized. The breakdown voltage, reliability during testing (e.g., unclamped inductive switching (UIS)), device performance, and/or so forth of the semiconductor device300can be maintained in the active region302using the trench extension314A.

The thickness E2 of the portion372A of the dielectric370A included in the trench extension portion314A is configured to have termination region advantages such as those described above. Specifically, an undesirable electric field or breakdown across the dielectric370A included in the main trench portion312A can be prevented or substantially prevented inclusion of the transverse trench380A and/or the trench extension portion314A within the semiconductor device300. In other words, an undesirable electric field at the end of a trench (i.e., the main trench portion312A without the transverse trench380A and/or the trench extension portion314A) or breakdown across a dielectric at the end of the trench could occur without features such as the transverse trench380A and/or the trench extension portion314A. The advantages described above can be applied to other transverse trenches described herein.

Referring back toFIG. 3A, perimeter trenches390A,390B are disposed around a perimeter of the plurality of trenches310. As shown inFIG. 3B, the perimeter trenches390A,390B have a depth E5 that is approximately equal to a depth (e.g., distance E4) of the transverse trench380A and a depth (e.g., distance E3) of the main trench portion312A. The depth E5 of the perimeter trenches390A,390B is greater than a depth (e.g., distance E1) of the trench extension portion314A. In some implementations, the depth of one or more of the perimeter trenches390A,390B can be less than or greater than the depth of the transverse trench380A and/or the depth of the main trench portion312A. In some implementations, the depth of one or more of the perimeter trenches390A,390B can be less than or equal to the depth of the trench extension portion314A. In some implementations, the width of one or more of the perimeter trenches390A,390B can be approximately the same as or different than (e.g., narrower than, wider than) the width of the main trench portions312of the plurality of trenches310. This description of the perimeter trenches above related to dimensions, electrodes, and/or numbers applies to all of the implementations described herein.

In this implementation, each of the perimeter trenches390A,390B includes at least a portion of a shield electrode. For example, the perimeter trench390A includes a shield electrode335(or shield electrode portion). In some implementations, one or more of the perimeter trenches390A,390B can include a recessed electrode, or may not include a shield electrode (e.g., may exclude a shield electrode and can be substantially filled with a dielectric). In some implementations, the semiconductor device300can include more or less perimeter trenches than shown inFIGS. 3A through 3I.

Referring back toFIG. 3A, the trench extension portions314have widths that are less (e.g., narrower) than widths of the main trench portions312. The widths of the trenches described herein can be measured across a cross-section of the trenches while being referenced along a horizontal plane through the trenches. In some implementations, the widths can be referred to as cross-sectional widths. As a specific example, the trench extension portion314A of the trench310A has a width E10 that is less than a width E11 of the main trench portion312A of the trench310A. This difference in width is also shown in, for example, trench310E in the various views. Specifically, trench310E shown inFIG. 3G(which is cut along line F6 through the trench extension portions314orthogonal to the plurality of trenches310) has a width E8 that is smaller than a width E9 of the trench310E shown inFIG. 3I(which is cut along line F8 through the main trench portions312orthogonal to the plurality of trenches310). Although not shown inFIG. 3A, one or more of the trench extension portions314can have widths that equal to or are greater than the widths of one or more of the main trench portions312.

Because the trench extension portions314are narrower than the main trench portions312, the dielectric370A, when formed (using one or more processes) in both the trench extension portions314and in the main trench portions312during semiconductor processing, can entirely fill (from a bottom of the trench to a top of the trench in a centerline of the trench) the trench extension portions314without entirely filling the main trench portions312. Accordingly, the shield electrode330A can be formed in the main trench portion312A while not being formed in the trench extension portion314A. Also, an advantage of the configuration shown inFIGS. 3A through 3Iwith the relatively narrow trench extension portions314, the parallel trenches310can be etched using a single semiconductor process rather than etched using multiple semiconductor processes (to form the trench extension portions314separate from the main trench portions312). More details related to the semiconductor processing are described below.

Although not shown inFIGS. 3A through 3I, the transverse trench380A can be excluded from the semiconductor device300. In such implementations, the narrowing trench widths of the plurality of trenches310with trench extension portions314can still be included in the semiconductor device300. In such implementations, the transverse trench380A would be excluded from the side cross-sectional views shown inFIGS. 3C and 3D. Accordingly, the mesa region360A would be continuous along the top surface of the epitaxial layer308between the perimeter trench390A and the well region362within the active region302.

FIG. 3Dis a side cross-sectional view of a mesa region360G adjacent to trench310G cut along line F3. In this implementation, the mesa region360G is entirely disposed within the termination region304. As shown inFIG. 3D, the source runner conductor354is not contacted with (e.g., is insulated from, is not electrically coupled to) the surface shield electrode332.

FIG. 3Eis a side cross-sectional view of the trench310G, which is cut along line F4 shown inFIG. 3A. In this implementation, the trench310G is entirely disposed within the termination region304. Trench310G, and other trenches entirely disposed within the termination region304, can be referred to as termination trenches318. The dimension of the trench310G is similar to the dimensions of (e.g., dimensions that are directly lateral to) the trench310A shown inFIG. 3B. In some implementations, the dimensions of the trench310G (which includes extension dielectric372G) can be different than corresponding portions of the trench310A shown inFIG. 3B. For example, the trench310G can have a constant depth, which can be the same as or different than (e.g., deeper than, shallower than) the depth E1 of the trench extension portion314A (shown inFIG. 3B) or the same as or different than (e.g., deeper than, shallower than) the depth E3 of the main trench portion312A.

As shown inFIG. 3E, the source runner conductor354is not contacted with (e.g., is insulated from, is not electrically coupled to) the surface shield electrode332or the shield electrode330G. In some implementations, the shield electrode330G disposed within the trench310G can be electrically floating. In some implementations, the shield electrode330G disposed within the trench310G can be electrically coupled to a source potential. Accordingly, the shield electrode330G can be tied to the same source potential as the shield electrode330A shown inFIG. 3B. In some implementations, the shield electrode330G disposed within the trench310G can be recessed.

FIG. 3Fis a side cross-sectional view of the end trench310D, which is cut along line F5 shown inFIG. 3A. The end trench310D has a dielectric370D disposed therein (e.g., and filling the end trench310D). Although not shown, in some implementations, at least a portion of the end trench310D can include a shield electrode. The end trench310D can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench310A.

As shown inFIG. 3A, the transverse trench380A terminates at the end trench310D. In some implementations, the transverse trench380A can terminate at a trench other than the end trench310D such as one of the interior trenches317from the plurality of trenches310.

Referring back toFIG. 3F, the end trench310D has a depth E12 less than a depth E5 of the perimeter trenches390A,390B. In some implementations, the end trench310D can have a depth E12 equal to, or greater than a depth of one or more of the perimeter trenches390A,390B. In this implementation, the depth E12 of the end trench310D is approximately equal to a depth (e.g., distance E1) of the trench extension portion314A (shown inFIG. 3B). In some implementations, the end trench310D can have a depth E12 that is less than or greater than a depth (e.g., distance E1) of the trench extension portion314A (shown inFIG. 3B). In some implementations, the end trench310D can have a depth that varies, similar to the variation in depth of trench310A.

InFIG. 3F, a bottom surface of the transverse trench380A extends from (or protrudes from) a bottom surface of the end trench310D. In other words, the end trench310D has a recess that corresponds with the transverse trench380A because the depth E12 of the end trench310D is shallower than the depth E4 of the transverse trench380A.

Although not shown, in some implementations, multiple trenches (e.g., multiple end trenches) similar to end trench310D, which are filled with (e.g., substantially filled with, from a bottom of the end trench310D to a top of the end trench310D along the centerline E25 of the end trench310D) a dielectric can be included in the semiconductor device300. An example of such an implementation is described in connection withFIGS. 4A through 4E. Although not shown, in some implementations, a trench that varies with width and has a portion that includes a shield dielectric, such as trench310C can be an end trench. In such implementations, the end trench310D can be omitted.

As mentioned above,FIG. 3Gis cut along line F6 (shown inFIG. 3A) through the trench extension portions314orthogonal to the plurality of trenches310. As shown inFIG. 3Gthe end trench310D has a width E13 that is approximately equal to the width E8 of the trench extension portion of trench310E. In some implementations, the end trench310D can have a width that is greater than, or less than, the width E8 of the trench extension portion of trench310E.

A pitch E14 between the end trench310D and trench310C (which are adjacent trenches) is less than a pitch E15 between trench310E and trench310F (which are adjacent trenches). In some implementations, the pitch E14 between the end trench310D and trench310C can be the same as, or greater than, the pitch E15 between trench310E and trench310F.

FIG. 3His a side cross-sectional view of the transverse trench380A, which is cut along line F7 shown inFIG. 3A. The line F7 is approximately along a centerline of the transverse trench380A. The transverse trench380A is filled with (e.g., substantially filled with) a dielectric385A. Although not shown, in some implementations, at least a portion of the transverse trench380A can include a shield electrode. In this implementation, the transverse trench380A has a constant depth E4. In some implementations, the transverse trench380A can have a depth that varies along the longitudinal axis D2.

FIG. 3Iis a side cross-sectional view of the main trench portions312of the plurality of trenches310cut along line F8 shown inFIG. 3A. A portion of the cross-sectional view of the plurality of trenches310is included in the termination region304and a portion of the cross-sectional view of the plurality of trenches310is included in the active region302.

Because the width of the end trench310D is substantially constant along the longitudinal axis D1 in this implementation, the width E13 of the end trench310D (shown inFIG. 3I) is the same along cut line F8 as along cut line F6 (shown inFIG. 3G). In contrast, the width of at least some of the trenches such as, for example, trench310C and trench310E varies along the longitudinal axis D1. Specifically, the width E9 of the trench310E (shown inFIG. 3I) is greater than the width E8 of the trench310E (shown inFIG. 3G). Even though the width of the trench310C varies, the pitch E14 between the end trench310D and the trench310C is substantially constant.

As shown inFIG. 3I, the trenches from the plurality of trenches310that include source implants therebetween can be referred to as active device trenches319. As shown inFIG. 3I, the leftmost active device trench310H includes a gate electrode with a width that is smaller than a gate electrode included in the remaining active device trenches319. In some implementations, the trench310H can be referred to as a partially active gate trench because a source implant is in contact with only one side of the trench310H.

As noted above, the trenches (such as some of the trenches that are shown inFIG. 3I) that are entirely disposed within the termination region304can be referred to as termination trenches318. Trench310I is a termination trench that includes a shield electrode.

As shown inFIG. 3I, at least a portion of the termination trenches from the plurality of trenches310include a shield electrode. In some implementations, at least a portion of the termination trenches318can have a shield electrode that extends above a top portion of the trench. For example, trench310J includes shield electrode330J (or shield electrode portion) that extends to a distance above a top portion of the trench310J aligned within the plane D4. In some implementations, the shield electrode330J can extend to a depth that is the same as or different than (e.g., deeper than, shallower than) the depth E12 of, for example, the end trench310D.

In some implementations, the termination trenches318(or portions thereof) that include a shield electrode can be referred to as shielded termination trenches. In some implementations, one or more of the shield electrodes included in one or more of the termination trenches318can be electrically floating (e.g., may not be coupled to a potential source) or can be coupled to a gate (e.g., a gate potential).

The directions D1, D2, and D3, and plane D4 are used throughout the various views below for simplicity. Also, for simplicity, not all elements are labeled in each of the figures or views.

FIGS. 4A through 4Dare diagrams that illustrate variations on at least some of the features of on the semiconductor device300shown inFIGS. 3A through 3I. Accordingly, the reference numerals and features included inFIGS. 3A through 3Iare generally maintained and some features are not described again in connection withFIGS. 4A through 4D. Additional end trenches (trenches310X,310Y,310Z) similar to the end trench310D are included in the semiconductor device300and are shown inFIGS. 4A through 4D. End trenches310X,310Y,310Z, to further shield trench310C from drain potential and reduce capacitance between surface shield electrode332and a drain (e.g., a back-side drain, the epitaxial layer308). Specifically, each of the end trenches313can have a structure and dimensions similar to the end trench310D (which is a side cross-sectional view cut along line H5) shown inFIG. 4B.

As shown inFIG. 4A, the transverse trench380A intersects all of the end trenches313, and terminates within the outermost end trench310Z. In some implementations, the transverse trench380A can intersect less than all of the end trenches313. In some implementations, the transverse trench380A can terminate within one of the end trenches313disposed between two other end trenches313. In some implementations, the transverse trench380A can terminate within the innermost end trench310D.

FIG. 4Cis a diagram that illustrates the end trenches313cut along line H6. As shown inFIG. 4C, each of the end trenches313has the same depth shown as E12. Also each of the end trenches313has an equal cross-sectional width of E13. In some implementations, one or more of the end trenches313can have a different depth (e.g., a deeper depth, a shallower depth) and/or a different width (e.g., a greater width, and narrower width) than one or more of the other end trenches313. Also, as shown inFIG. 4C, the end trenches313are each separated by the same pitch E14, which is less than the pitch E15 (of the remainder of the plurality of trenches310or the interior trenches317). In some implementations, the pitch between the end trenches can be greater than that shown inFIG. 4C(e.g., equal to or greater than the pitch E15), or less than that shown inFIG. 4C.

FIG. 4Dis a side cross-sectional view of the main trench portions312of the plurality of trenches310cut along line H8 shown inFIG. 4A. A portion of the cross-sectional view of the plurality of trenches310is included in the termination region304and a portion of the cross-sectional view of the plurality of trenches310is included in the active region302.

Because the width of the end trenches313(i.e., end trenches310X,310Y,310Z,310D) is substantially constant along the longitudinal axis D1 in this implementation, the widths of the end trenches313is the same along cut line H8 as along cut line H6 (shown inFIG. 4C).

In some implementations, one or more of the end trenches313can include at least a portion of a shield electrode (e.g., a floating shield electrode). For example, end trench310X can include at least a portion of a shield electrode coupled to, for example, the surface shield electrode332.

FIGS. 5A through 5Iare diagrams that illustrate configurations of another termination region according to some implementations.FIG. 5Ais a diagram that illustrates a plan view (or top view along a horizontal plane) of at least a portion of a semiconductor device500including an active region502and a termination region504.FIGS. 5B through 5Iare side cross-sectional views along different cuts (e.g., cuts G1 through G8) within the plan viewFIG. 5A. To simplify the plan view shown inFIG. 5Asome of the elements illustrated in the side cross-sectional views ofFIGS. 5B through 5Iare not shown. The side cross-sectional views along the different cuts included inFIGS. 5B through 5Iare not necessarily drawn to the same scale (e.g., number of trenches, etc.) as the plan view shown inFIG. 5A.

As shown inFIG. 5A, a plurality of trenches510(or parallel trenches), including for example trenches510A through510J, are aligned along a longitudinal axis D1 within the semiconductor device500. At least some portions of the plurality of trenches510can be included in the active region502and at least some portions of the plurality of trenches510can be included in the termination region504.

In this implementation, the trench510D is entirely disposed within the termination region504and is the outermost trench from the plurality of trenches510. Accordingly, the trench510D can be referred to as an end trench. Trenches from the plurality of trenches510in the semiconductor device500that are lateral to (or interior to) the end trench510D can be referred to as interior trenches517.

As shown inFIG. 5A, the active region502is defined by an area of the semiconductor device500that corresponds with at least one of a source contact region536(e.g., a source contact region536) or a shield dielectric edge region534. The source contact region536defines an area within the semiconductor device500where source contacts (such as source contact557shown inFIG. 5I) are formed. The source contact region536can also correspond with, for example, a source conductor region (e.g., a source metal region). The source contacts can be contacted with source implants (such as source implant563E within a mesa region560E between trenches510E and510F shown inFIG. 5I) of one or more active devices. A source formation region556(which can be referred to as a source exclusion edge) defines an area within which mesa regions between the plurality of trenches510are doped as doped source regions of active devices.

The shield dielectric edge region534shown inFIG. 5Acorresponds with (e.g., approximately corresponds with), for example, an edge541of the inter-electrode dielectric540shown inFIG. 5B(which is a side cross-sectional view cut along line G1). In some implementations, at least a portion of the inter-electrode dielectric540can include a gate dielectric such as gate dielectric portion542shown inFIG. 5B.

As shown inFIG. 5A, the termination region504includes areas of the semiconductor device500outside of (e.g., excluded by) the active region502. Accordingly, the termination region504, similar to the active region502, is defined by at least one of the source contact region536or the shield dielectric edge region534.

Although not shown inFIG. 5A, one or more transverse trenches, similar to transverse trench380A shown inFIGS. 3A through 3I, can be included in the semiconductor device500. In such implementations, the transverse trench(es) can intersect in an orthogonal direction, the plurality of trenches510and can be disposed within the termination region504. In such implementations, the transverse trench would be included in the side cross-sectional views shown in, for example,FIGS. 5C and 5D.

In this implementation, portions of the plurality of trenches510that are interior trenches517and disposed to the left of line G9 can be referred to as trench extension portions514. Portions of the plurality of trenches510that are interior trenches517and that are disposed to the right of line and extend into (or toward) the active region502can be referred to as main trench portions512. For example, trench510A includes a trench extension portion514A on the left side of line G9 (toward the perimeter and in a distal direction away from the active region502) and the trench510A includes a main trench portion512A on the right side of line G9 (away from the perimeter and in a proximal direction toward the active region502). In this implementation, at least a portion of the main trench portion512A is included in (e.g., disposed within) the termination region504, and a portion of the main trench portion512A is included in (e.g., disposed within) the active region502. In this implementation, the trench extension portions514can define recesses (when viewed in a side cross-sectional view).

FIG. 5Bis a diagram that illustrates a side cross-sectional view of the semiconductor device500cut along line G1. The cut line G1 is approximately along a centerline of the trench510A so that the side cross-sectional view of the semiconductor device500is along a plane that approximately intersects a center of the trench510A. A side cross-sectional view of the mesa region560A between the trench510A and the trench510B, is shown inFIG. 5C. As shown inFIG. 5C, a well region562A is formed in an area of the epitaxial layer508that is blocked by the surface gate electrode522and the surface shield electrode532. The features shown inFIG. 5Bare disposed in an epitaxial layer508of the semiconductor device500.

As shown inFIG. 5B, the trench510A includes a dielectric570A disposed therein. Specifically, a portion of the dielectric570A is coupled to (e.g., lines, is disposed on) a sidewall and a portion of the dielectric570A is coupled to a bottom surface of the trench510A within the main trench portion512A of the trench510A. In this cross-sectional view the portion of the dielectric570A coupled to the bottom surface of the trench510A is shown, and the portion of the dielectric570A coupled to the sidewall of the trench510A is not shown. In some implementations, the portion of the dielectric570A shown inFIG. 5Balong the bottom surface of the main trench portion512A of the trench510A can be referred to as a bottom dielectric. In some implementations, the dielectric570A can be coupled to, or can include, a field dielectric574(which can be referred to as a field dielectric portion).

As shown inFIG. 5B, a gate electrode520A and a portion531A of a shield electrode530A are disposed in a portion of the main trench portion512A that is included in the active region502of the semiconductor device500. The gate electrode520A and the shield electrode530A are separated by at least a portion of the inter-electrode dielectric540. The portion of the main trench portion512A included in the termination region504has a portion533A of the shield electrode530A disposed therein and insulated from the epitaxial layer508by the dielectric570A. In some implementations, the portion533A of the shield electrode530A can be referred to as a termination region portion of the shield electrode, and the portion531A of the shield electrode530A can be referred to as an active region portion of the shield electrode.

In this implementation, a surface shield electrode532is coupled to the shield electrode530A, and a surface gate electrode522is coupled to the gate electrode520A. The surface electrode532is insulated from the surface gate electrode522by at least a portion of the inter-electrode dielectric540. A gate runner conductor552is coupled to the surface gate electrode522using a via551. Similarly, a source runner conductor554(which is also coupled to a source) is coupled to the surface shield electrode532using a via553through an opening in the surface gate electrode522.

Although not shown inFIGS. 5A through 5I, semiconductor device500can exclude the surface shield electrode532and/or the surface gate electrode522. In other words, the semiconductor device500(or a portion thereof) can be configured without the surface electrode532and/or the surface gate electrode522. More details related to such implementations are described below.

As shown inFIG. 5B, a portion572A of the dielectric570A (also referred to as an extension portion of the dielectric or as an extension dielectric) is included in the trench extension portion514A. The portion572A of the dielectric570A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the trench extension portion514A of the trench510A to at least a top of the trench510A. The top of the trench510A (which includes the trench portion514A and the main trench portion512A) is aligned along a plane D4, which is aligned along a top surface of a semiconductor region of the semiconductor device500. In some implementations, the dielectric570A can include one or more dielectric layers and/or one or more dielectric types formed using one or more different formation processes.

The thickness of the dielectric570A included in the trench510A varies along the longitudinal axis D1 of the trench510A. The portion572A of the dielectric570A included in the trench extension portion514A has at least a thickness I1 in the trench extension portion514A (also can be referred to as a height because it is aligned along the vertical axis D3) that is greater than a thickness I2 of a portion of the dielectric570A included in the main portion512A (both in a termination region portion and in an active region portion) of the trench510A. The thickness of the portion572A of the dielectric570A extends up to a bottom surface of a surface shield electrode532beyond the thickness I1. The thickness I1 corresponds approximately with a depth (along the vertical direction D3) of the trench extension portion514A. The thickness of the portion572A can help to eliminate relatively high lateral and/or vertical electric fields at the end (toward the left end) of the trench510A.

Referring back toFIG. 5B, in this implementation, the trench extension portion514A includes the portion572A of the dielectric570A and excludes a shield electrode. Although not shown, in some implementations, a trench extension portion such as the trench extension portion514A can include a portion of a shield electrode (e.g., a portion of a shield electrode, a recessed shield electrode).

Although not shown inFIG. 5B, in some implementations, the thickness I2 of the portion of the dielectric570A in the main portion512A of the trench510A can vary along the longitudinal axis D1. For example, a thickness of a portion of the dielectric570A included in the termination region504of the main trench portion512A can be greater than a thickness of a portion of the dielectric570A included in the active region502of the main trench portion512A, or vice versa.

If including a transverse trench, the transverse trench can have a depth that is the same as, or different than (e.g., greater than, less than) a depth (which corresponds with I3) of the main trench portion512A and/or a depth (which corresponds with I1) of the trench extension portion514A. In some implementations, a depth (which corresponds with I3) of the main trench portion512A can be the same as a depth (which corresponds with I1) of the trench extension portion514A.

As shown inFIG. 5B, a length I16 of the trench extension portion514A of the trench510A is longer than a length I17 of a portion of the main trench portion512A of the trench510A included in the termination region504. Although not shown, the length of I16 of trench extension portion514A of the trench510A can be equal to or shorter than the length I17 of the portion of the main trench portion512A of the trench510A included in the termination region504. As shown inFIG. 5B, the main trench portion512A can include a portion575A of the dielectric570A that is in contact with the portion572A of the dielectric570A and has a thickness I7. The thickness I7 can be approximately equal to or different than (e.g., greater than, less than) the thickness I2.

The thickness I2 of the portion572A of the dielectric570A included in the trench extension portion514A is configured to have termination region advantages such as those described above. Specifically, an undesirable electric field or breakdown across the dielectric570A included in the main trench portion512A can be prevented or substantially prevented inclusion of the trench extension portion514A (and/or a transverse trench (not shown)) within the semiconductor device500.

Referring back toFIG. 5A, perimeter trenches590A,590B are disposed around a perimeter of the plurality of trenches510. As shown inFIG. 5B, the perimeter trenches590A,590B have a depth I5 that is approximately equal to a depth (e.g., distance I3) of the main trench portion512A. The depth I5 of the perimeter trenches590A,590B is less than a depth (e.g., distance I1) of the trench extension portion514A. In some implementations, the depth of one or more of the perimeter trenches590A,590B can be less than or greater than the depth of the main trench portion512A. In some implementations, the width of one or more of the perimeter trenches590A,590B can be approximately the same as or different than (e.g., narrower than, wider than) the width of the main trench portions512and/or the extension portions514of the plurality of trenches510.

Referring back toFIG. 5A, the trench extension portions514have widths that are the same as the widths of the main trench portions512. As a specific example, the trench extension portion514A of the trench510A has a width I10 that is equal to (approximately equal to) a width I11 of the main trench portion512A of the trench510A. This equivalence in width is also shown in, for example, trench510E in the various views. Specifically, trench510E shown inFIG. 5G(which is cut along line G6 through the trench extension portions514orthogonal to the plurality of trenches510) has a width I8 that is equal to (or approximately equal to) a width I9 of the trench510E shown inFIG. 5I(which is cut along line G8 through the main trench portions512orthogonal to the plurality of trenches510). Although not shown inFIG. 5A, one or more of the trench extension portions514can have widths that are less than or greater than the widths of one or more of the main trench portions512.

Even though the trench extension portions514have a same width as the main trench portions512, the dielectric570A, when formed (using one or more processes) in both the trench extension portions514and in the main trench portions512during semiconductor processing, can entirely fill the trench extension portions514without entirely filling the main trench portions512. Accordingly, the shield electrode530A can be formed in the main trench portions512A while not being formed in the trench extension portions514A.

FIG. 5Dis a side cross-sectional view of a mesa region560G adjacent to trench510G cut along line G3. In this implementation, the mesa region560G is entirely disposed within the termination region504. As shown inFIG. 5D, the source runner conductor554is not contacted with (e.g., is insulated from, is not electrically coupled to) the surface shield electrode532.

FIG. 5Eis a side cross-sectional view of the trench510G, which is cut along line G4 shown inFIG. 5A. In this implementation, the trench510G is entirely disposed within the termination region504. Trench510G, and other trenches entirely disposed within the termination region504, can be referred to as termination trenches518(which can be a subset of the interior trenches517). The dimension of the trench510G is similar to the dimensions of (e.g., dimensions that are directly lateral to) the trench510A shown inFIG. 5B. In some implementations, the dimensions of the trench510G can be different than corresponding portions of the trench510A shown inFIG. 5B. For example, the trench510G can have a constant depth, which can be the same as or different than (e.g., deeper than, shallower than) the depth I1 of the trench extension portion514A (shown inFIG. 5B) or the same as or different than (e.g., deeper than, shallower than) the depth I3 of the main trench portion512A.

As shown inFIG. 5E, the source runner conductor554is not contacted with (e.g., is insulated from, is not electrically coupled to) the surface shield electrode532or the shield electrode530C. In some implementations, the shield electrode530C disposed within the trench510G can be electrically floating. In some implementations, the shield electrode530C disposed within the trench510G can be electrically coupled to a source potential. Accordingly, the shield electrode530C can be tied to the same source potential as the shield electrode530A shown inFIG. 5B.

FIG. 5Fis a side cross-sectional view of the end trench510D, which is cut along line G5 shown inFIG. 5A. The end trench510D is filled with (e.g., substantially filled with, from a bottom of the end trench510D to a top of the end trench510D along the centerline of the end trench510D) a dielectric570D. Although not shown, in some implementations, at least a portion of the end trench510D can include a shield electrode. The end trench510D can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench510A.

Referring back toFIG. 5F, the end trench510D has a depth I12 greater than a depth I5 of the perimeter trenches590A,590B. In some implementations, the end trench510D can have a depth I12 equal to, or less than a depth of one or more of the perimeter trenches590A,590B. In this implementation, the depth I12 of the end trench510D is approximately equal to a depth (e.g., distance I1) of the trench extension portion514A (shown inFIG. 5B). In some implementations, the end trench510D can have a depth I12 that is less than or greater than a depth (e.g., distance I1) of the trench extension portion514A (shown inFIG. 5B). In some implementations, the end trench510D can have a depth that varies, similar to the variation in depth of trench510A.

Although not shown, in some implementations, multiple trenches similar to end trench510D, which are filled with (e.g., substantially filled with) a dielectric can be included in the semiconductor device500. Such dielectric filled trenches can be referred to as end trenches. Although not shown, in some implementations, a trench that varies with width and has a portion that includes a shield dielectric, such as trench510C can be an end trench. In such implementations, the end trench510D can be omitted.

As mentioned above,FIG. 5Gis cut along line G6 (shown inFIG. 5A) through the trench extension portions514orthogonal to the plurality of trenches510. As shown inFIG. 5Gthe end trench510D has a width I13 that is approximately equal to the width I8 of the trench extension portion of trench510E. In some implementations, the end trench510D can have a width that is greater than, or less than, the width I8 of the trench extension portion of trench510E. In this implementation, the width I13 is approximately equal to each of the widths of the perimeter trenches590A,590B.

A pitch I14 between the end trench510D and trench510C (which are adjacent trenches) is approximately the same as a pitch I15 between trench510E and trench510F (which are adjacent trenches). In some implementations, the pitch I14 between the end trench510D and trench510C can be the less than, or greater than, the pitch I15 between trench510E and trench510F.

FIG. 5His a side cross-sectional view of the main trench portions512of the plurality of trenches510cut along line G7 shown inFIG. 5Awithin the termination region504. In this side cross-sectional view, each of the main trench portions512includes a shield electrode coupled to the surface shield electrode532except for the end trench510D.

FIG. 5Iis a side cross-sectional view of the main trench portions512of the plurality of trenches510cut along line G8 shown inFIG. 5Athrough the termination region504and into the active region502. A portion of the cross-sectional view of the plurality of trenches510is included in the termination region504and a portion of the cross-sectional view of the plurality of trenches510is included in the active region502.

Because the width of the end trench510D is substantially constant along the longitudinal axis D1, in this implementation, the width I13 of the end trench510D (shown inFIG. 5I) is the same along cut line G8 as along cut line G6 (shown inFIG. 5G). Similarly, the width of at least some of the trenches such as, for example, trench510C and trench510E is constant (substantially constant) along the longitudinal axis D1. Specifically, the width I9 of the trench510E (shown inFIG. 5I) is equal to the width I8 of the trench510E (shown inFIG. 5G).

As shown inFIG. 5I, the trenches from the plurality of trenches510that include source implants therebetween can be referred to as active device trenches519. Because the general structure of the active device trenches519, the partially active gate trench, the termination trenches518, the source implants, and so forth are similar to those shown inFIG. 3I, these features will not be described again here in connection withFIG. 5Iexcept as otherwise noted. Although not shown inFIG. 5I, the end trench510D can include at least a portion of a shield electrode (e.g., a recessed shield electrode, a shield electrode with a thick bottom oxide disposed below, an electrically floating shield electrode, a shield electrode coupled to a source potential (e.g., via the surface shield electrode532) or a gate potential (e.g., via the surface gate electrode522)).

As shown inFIG. 5I, at least a portion of the termination trenches518from the plurality of trenches510include a shield electrode. In some implementations, at least a portion of the termination trenches518can have a shield electrode that extends above a top portion of the trench. For example, trench510J includes shield electrode530J (or shield electrode portion) that extends to a distance above a top portion of the trench510J aligned within the plane D4. In some implementations, the shield electrode530J can extend to a depth that is the same as or different than (e.g., deeper than, shallower than) the depth E12 of, for example, the end trench510D.

In some implementations, the termination trenches518(or portions thereof) that include a shield electrode can be referred to as shielded termination trenches. In some implementations, one or more of the shield electrodes included in one or more of the termination trenches518can be electrically floating (e.g., may not be coupled to a potential source) or can be coupled to a gate (e.g., a gate potential).

FIGS. 6A through 6Gare diagrams that illustrate variations on at least some of the features of on the semiconductor device500shown inFIGS. 5A through 5I. Accordingly, the reference numerals and features included inFIGS. 5A through 5Iare generally maintained. InFIGS. 5A through 5I, the trench extension portions514are filled with the dielectric material, however,FIGS. 6A through 6Gillustrate variations where the trench extension portions514include a shield electrode material.

FIG. 6Bis a diagram that illustrates a side cross-sectional view of the semiconductor device500cut along line G1. The cut line G1 is approximately along a centerline of the trench510A so that the side cross-sectional view of the semiconductor device500is along a plane that approximately intersects a center of the trench510A. As shown inFIG. 6B, the shield electrode530A is disposed within (in a contiguous fashion) the trench extension portion514A as well as the main trench portion512A of the trench510A.

As shown inFIG. 6B, the thickness of the dielectric570A along the longitudinal axis D1 varies within the trench510A. Specifically, a thickness I6 of the portion572A of the dielectric570A is greater than the thickness I2 of the dielectric570A. however, the thickness I6 of the portion572A of the dielectric570A is less than the depth I1 of the trench extension portion514A. In some implementations, the thickness I6 of the portion572A of the dielectric570A can be approximately equal to the thickness I2. In some implementations, the thickness I6 can be approximately equal to a thickness I18 of the dielectric570A along a vertical sidewall515A of the trench510A at an end of the trench510A within the termination region504. In some implementations, the thickness I6 can be less than, or greater than the thickness I18 of the dielectric570A along the vertical sidewall515A of the trench510A.

In this implementation, a top surface573A of the dielectric570A along the bottom surface of the trench510A (at an interface between the dielectric570A and a bottom surface of the shield electrode530A) is substantially aligned along the longitudinal direction D1 and is constant or flat. In some implementations, the top surface573A of the dielectric570A can vary along the longitudinal direction D1. For example, if the thickness I6 of the portion572A of the dielectric570A is thinner than that shown inFIG. 6B, the top surface573A can have an inflection between the main trench portion512A and the trench extension portion514A.FIG. 6Cillustrates the trench510G with approximately the same shield electrode530G dimensions in the trench extension portion514G (a profile of the trench extension portion is illustrated with a dashed line) as the dimensions of the shield electrode530A in the trench extension portion514A of the trench510A (shown inFIG. 6B).

FIG. 6Dis a side cross-sectional view of the end trench510D, which is cut along line G5 shown inFIG. 6A. Rather than being filled entirely with a dielectric material as shown inFIG. 5F, the end trench510D, in this implementation, includes a shield electrode530D disposed within at least a portion of the dielectric570D. In this implementation, the depth I12 of the end trench510D is approximately equal to a depth (e.g., distance I1) of the trench extension portion514A (shown inFIG. 5B). In some implementations, the end trench510D can have a depth I12 that is less than or greater than a depth (e.g., distance I1) of the trench extension portion514A (shown inFIG. 5B). In some implementations, the end trench510D can have a depth that varies, similar to the variation in depth of trench510A.

FIG. 6Eis cut along line G6 (shown inFIG. 6A) through the trench extension portions514orthogonal to the plurality of trenches510. As shown inFIG. 6Eall of the trench extension portions514include shield electrodes. Also, the end trench510D has a width I13 that is approximately equal to, for example, the width I8 of the trench extension portion of trench510E. In some implementations, the end trench510D can have a width that is greater than, or less than, the width I8 of the trench extension portion of trench510E. In this implementation, the width I13 is approximately equal to each of the widths of the perimeter trenches590A,590B.

A pitch I14 between the end trench510D and trench510C (which are adjacent trenches) is approximately the same as a pitch I15 between trench510E and trench510F (which are adjacent trenches). In some implementations, the pitch I14 between the end trench510D and trench510C can be the less than, or greater than, the pitch I15 between trench510E and trench510F.

FIG. 6Fis a side cross-sectional view of the main trench portions512of the plurality of trenches510cut along line G7 shown inFIG. 6Awithin the termination region504. In this side cross-sectional view, each of the main trench portions512, including the end trench510D, includes a shield electrode coupled to the surface shield electrode532. In some implementations, the shield electrode530D included in the end trench510D can be electrically floating.

FIG. 6Gis a side cross-sectional view of the main trench portions512of the plurality of trenches510cut along line G8 shown inFIG. 6Athrough the termination region504and into the active region502. A portion of the cross-sectional view of the plurality of trenches510is included in the termination region504and a portion of the cross-sectional view of the plurality of trenches510is included in the active region502.

Because the width of the end trench510D is substantially constant along the longitudinal axis D1, in this implementation, the width I13 of the end trench510D (shown inFIG. 6G) is the same along cut line G8, as along cut line G7 (shown inFIG. 6F) and as along cut line G6 (shown inFIG. 6E).

In contrast, the width of at least some of the trenches such as, for example, trench510C and trench510E is different along the longitudinal axis D1. For example, the width I9 of the trench510E (shown inFIG. 6Gand inFIG. 6F) is less than the width I8 of the trench510E (shown inFIG. 6E).

As shown inFIG. 6G, the trenches from the plurality of trenches510that include source implants therebetween can be referred to as active device trenches519. Because the general structure of the active device trenches519, the partially active gate trench, the termination trenches518, the source implants, and so forth are similar to those shown inFIG. 3I, these features will not be described again here in connection withFIG. 6Gexcept as otherwise noted. Although not shown inFIG. 6G, the end trench510D can include a variety of a shield electrodes (e.g., a recessed shield electrode, an electrically floating shield electrode, a shield electrode with a thick bottom oxide disposed below, a shield electrode coupled to a source potential (e.g., via the surface shield electrode532) or a gate potential (e.g., via the surface gate electrode522)).

FIGS. 7A through 7Jare diagrams that illustrate variations on at least some of the features of the semiconductor device300shown inFIGS. 3A through 3I. Accordingly, the reference numerals and features included inFIGS. 3A through 3Iare generally maintained and some features are not described again in connection withFIGS. 7A through 7J. InFIGS. 3A through 3Ithe transverse trench380A bisects the plurality of trenches310(or parallel trenches), however, inFIGS. 7A through 7J, a transverse trench383A is disposed at an end of the plurality of trenches310(or parallel trenches). Accordingly, each of the plurality of trenches310is not bisected into trench extension portions and main trench portions as discussed in connection withFIGS. 3A through 3I. Specifically, the transverse trench383A as shown inFIG. 7Ais aligned parallel to the perimeter trenches390A,390B (along longitudinal axis D2), but is disposed between the perimeter trenches390A,390B and the ends of the plurality of trenches310, which are orthogonally aligned to the transverse trench383A. The side cross-sectional views along the different cuts included inFIGS. 7B through 7Jare not necessarily drawn to the same scale (e.g., numbers of trenches, etc.) as the plan view shown inFIG. 7A.

In this implementation, the trench310D is entirely disposed within the termination region304and is the outermost trench from the plurality of trenches310. Accordingly, the trench310D can be referred to as an end trench. Trenches from the plurality of trenches310in the semiconductor device300that are lateral to (or interior to) the end trench310D can be referred to as interior trenches317.

As shown inFIG. 7A, the transverse trench383A is aligned along a longitudinal axis D2 that is orthogonal to (e.g., substantially orthogonal to) the longitudinal axis D1. As noted above, the transverse trench383A is aligned parallel to the perimeter trenches390A,390B, but is disposed between the perimeter trenches390A,390B and the ends of the plurality of trenches310, which are orthogonally aligned to the transverse trench383A. The transverse trench383A can be considered to be in fluid communication with, for example, trench310A. In some implementations, the transverse trench383A may intersect only a portion (e.g., less than all) of the plurality of trenches310. In some implementations, the transverse trench383A can be referred to as an end of trench trench (EOTT) or as a perpendicular trench because the transverse trench383A is perpendicularly oriented with respect to the parallel trenches (i.e., the plurality of trenches310). In this implementation, the transverse trench383A is disposed entirely within the termination region304.

Although only one transverse trench is included in the semiconductor device300, in some implementations, more than one transverse trench similar to transverse trench383A can be included in the semiconductor device300. For example, an additional transverse trench aligned parallel to the transverse trench383A and intersecting the plurality of trenches310(similar to the implementations described in connection withFIGS. 3A through 3I) can be included.

FIG. 7Bis a diagram that illustrates a side cross-sectional view of the semiconductor device300cut along line F1. The cut line F1 is approximately along a centerline of the trench310A so that the side cross-sectional view of the semiconductor device300is along a plane that approximately intersects a center of the trench310A. A portion of the transverse trench383A, which intersects the trench310A, is shown inFIG. 7B. A side cross-sectional view of the transverse trench383A cut along line F2, which is within the mesa region360A between the trench310A and the trench310B, is shown inFIG. 7C.

As shown inFIG. 7B, the trench310A includes a dielectric370A disposed therein. Specifically, a portion of the dielectric370A is coupled to (e.g., lines, is disposed on) a sidewall and a portion of the dielectric370A is coupled to a bottom surface of the trench310A within the main trench portion312A of the trench310A. In this cross-sectional view the portion of the dielectric370A coupled to the bottom surface of the trench310A is shown, and the portion of the dielectric370A coupled to the sidewall of the trench310A is not shown.

As shown inFIG. 7B, a portion372A of the dielectric370A is included in the trench310A and a portion371A of the dielectric370A is included in the transverse trench383A. The portion372A of the dielectric370A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the trench310A to at least a top of the trench310A. Similarly, the portion371A of the dielectric370A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the trench310A to at least a top of the transverse trench383A. The top of the trench310A (which includes the trench portion314A and the main trench portion312A) is aligned along a plane D4, which is aligned along a top surface of a semiconductor region of the semiconductor device300. In some implementations, the dielectric370A can include one or more dielectric layers and/or one or more dielectric types formed using one or more different formation processes. For example, the portion372A included in the trench310A can be a first dielectric in contact (e.g., can abut) the portion371A can be a second dielectric included in the transverse trench383A. In some implementations, the portion371A and the portion372A can be formed using the same dielectric formation process.

A thickness E1 of the dielectric370A included in the trench310A is constant (e.g., substantially constant) along the longitudinal axis D1 of the trench310A. The portions371A and372A of the dielectric370A have at least a combined thickness E1 that is greater than a thickness E2 of a portion of the dielectric370A along the bottom of the trench310A. In some implementations the portion372A of the dielectric can have a thickness approximately equal to the thickness E2, and/or the portion371A of the dielectric can have a thickness less than the thickness E2. In some implementations the portion372A of the dielectric can have a thickness approximately different than (e.g., greater than, less than) the thickness E2, and/or the portion371A of the dielectric can have a thickness equal to or greater than the thickness E2.

Also, the portion371A of the dielectric370A included in the transverse trench383A has at least a thickness E4 (also can be referred to as a height) that is greater than the thickness E2 of a portion of the dielectric370A included in the main portion312A of the trench310A and/or the thickness E1 of the portion372A of the dielectric370A included in the trench extension portion314A. The thickness of the portion371A of the dielectric370A shown inFIG. 7Bextends up to a bottom surface of a surface shield electrode332beyond the thickness E4. The thickness E4 corresponds approximately with a depth (along the vertical direction D3) of the transverse trench383A. The depth (or height) of the transverse trench383A is also illustrated within the mesa region360A shown inFIG. 7C.

Although not shown, in some implementations, a transverse trench such as the transverse trench383A can include a portion of a shield electrode (e.g., a portion of the shield electrode330A, a recessed shield electrode).

Although not shown inFIG. 7B, in some implementations, the thickness E2 of the portion of the dielectric370A in the main portion312A of the trench310A can vary along the longitudinal axis D1. For example, a thickness of a portion of the dielectric370A included in the termination region304of the main trench portion312A can be greater than a thickness of a portion of the dielectric370A included in the active region302of the main trench portion312A, or vice versa.

In some implementations, the profile of the trench310A shown inFIG. 3Bcan be included with the transverse trench383A shown inFIG. 7B(with or without transverse trench380A). Such an implementation without transverse trench380A is shown inFIG. 7J.

In this implementation, the transverse trench383A has a depth (which corresponds with E4) that is the same as, or approximately equal to, a depth (which corresponds with E3) of the trench portion310A. Although not shown inFIGS. 7A through 7J, in some implementations, the transverse trench383A can have a depth that is greater than a depth of the trench310A. Although not shown inFIGS. 7A through 7J, in some implementations, the transverse trench383A can have a depth that is less than a depth of the trench310A.

Referring back toFIG. 7A, perimeter trenches390A,390B are disposed around a perimeter of the plurality of trenches310. As shown inFIG. 7B, the perimeter trenches390A,390B have a depth E5 that is approximately equal to a depth (e.g., distance E4) of the transverse trench383A and a depth (e.g., distance E3) of the trench310A. In some implementations, the depth of one or more of the perimeter trenches390A,390B can be less than or greater than the depth of the transverse trench383A and/or the depth of the trench310A.

FIG. 7Dis a side cross-sectional view of a mesa region360G adjacent to trench310G cut along line F3. In this implementation, the mesa region360G is entirely disposed within the termination region304. As shown inFIG. 7D, the source runner conductor354is not contacted with (e.g., is insulated from, is not electrically coupled to) the surface shield electrode332.

FIG. 7Eis a side cross-sectional view of the trench310G, which is cut along line F4 shown inFIG. 7A. In this implementation, the trench310G is entirely disposed within the termination region304. Trench310G, and other trenches entirely disposed within the termination region304, can be referred to as termination trenches318. The dimension of the trench310G is similar to the dimensions of (e.g., dimensions that are directly lateral to) the trench310A shown inFIG. 7B. In some implementations, the dimensions of the trench310G can be different than corresponding portions of the trench310A shown inFIG. 7B.

As shown inFIG. 7E, the source runner conductor354is not contacted with (e.g., is insulated from, is not electrically coupled to) the surface shield electrode332or the shield electrode330G. In some implementations, the shield electrode330G disposed within the trench310G can be electrically floating. In some implementations, the shield electrode330G disposed within the trench310G can be electrically coupled to a source potential. Accordingly, the shield electrode330G can be tied to the same source potential as the shield electrode330A shown inFIG. 7B. In some implementations, the shield electrode330G disposed within the trench310G can be recessed.

FIG. 7Fis a side cross-sectional view of the end trench310D, which is cut along line F5 shown inFIG. 7A. The end trench310D is filled with a dielectric370D. Although not shown, in some implementations, at least a portion of the end trench310D can include a shield electrode. The end trench310D can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench310A.

As shown inFIG. 7A, the transverse trench383A terminates at the end trench310D. In some implementations, the transverse trench383A can terminate at a trench other than the end trench310D such as one of the interior trenches317from the plurality of trenches310.

Referring back toFIG. 7F, the end trench310D has a depth E12 less than a depth E5 of the perimeter trenches390A,390B and the transverse trench E4. In some implementations, the end trench310D can have a depth E12 equal to, or greater than a depth of one or more of the perimeter trenches390A,390B and/or the transverse trench E4.

As mentioned above,FIG. 7Gis cut along line F6 (shown inFIG. 7A) orthogonal to the plurality of trenches310through an area entirely within the termination region304. As shown inFIG. 7G, each interior trenches317(excluding the end trench310D) from the plurality of trenches310includes a shield electrode. This is contrasted with the trench extension portions314A shown inFIG. 3G. Accordingly, the end trench310D has a width E13 that is less than the width E8 of a portion of the trench310E within the termination region304.

In some implementations, the end trench310D can have a width that is greater than, or equal to, the width E8 of the trench310E. Also, in some implementations, the end trench310D can have a depth that is greater than, or equal to, a depth of one or more of the perimeter trenches380A,390A and/or the interior trenches317from the plurality of trenches310.

A pitch E14 between the end trench310D and trench310C (which are adjacent trenches) is less than a pitch E15 between trench310E and trench310F (which are adjacent trenches). In some implementations, the pitch E14 between the end trench310D and trench310C can be the same as, or greater than, the pitch E15 between trench310E and trench310F.

FIG. 7His a side cross-sectional view of the transverse trench383A, which is cut along line F7 shown inFIG. 7A. The line F7 is approximately along a centerline of the transverse trench383A. The transverse trench383A is filled with a dielectric385A. Although not shown, in some implementations, at least a portion of the transverse trench383A can include a shield electrode. In this implementation, the transverse trench383A has a constant depth E4. In some implementations, the transverse trench383A can have a depth that varies along the longitudinal axis D2.

FIG. 7Iis a side cross-sectional view of the main trench portions312of the plurality of trenches310cut along line F8 shown inFIG. 7A. A portion of the cross-sectional view of the plurality of trenches310is included in the termination region304and a portion of the cross-sectional view of the plurality of trenches310is included in the active region302.

Because the width of the end trench310D is substantially constant along the longitudinal axis D1 in this implementation, the width E13 of the end trench310D (shown inFIG. 7I) is the same along cut line F8 as along cut line F6 (shown inFIG. 7G). Similarly, the width of at least some of the trenches such as, for example, trench310C and trench310E is substantially constant along the longitudinal axis D1. This is contrasted with the plurality of trenches310shown inFIG. 3A, which vary along the longitudinal axis. Specifically, the width E9 of the trench310E (shown inFIG. 7I) is approximately equal to the width E8 of the trench310E (shown inFIG. 7G).

In some implementations, the end trench310D can have a width that is greater than, or equal to, the width E9 of the trench310E. Also, in some implementations, the end trench310D can have a depth that is greater than, or equal to, a depth of one or more of the perimeter trenches380A,390A and/or the interior trenches317(e.g., active trenches) from the plurality of trenches310.

FIG. 8is a diagram that illustrates a semiconductor device800, according to an implementation. In this implementation, many of the features included in this implementation are similar to those described above. Accordingly, the reference numerals used in conjunction with same or similar features are used to describe this implementation.

As shown inFIG. 8, the semiconductor device800can optionally include a transverse trench380A (illustrated by a dashed line) that intersects the parallel trenches310(e.g., ends of the parallel trenches). Also, as shown inFIG. 8, the semiconductor device800includes several sets of end trenches870,880, and890. Each of the sets of end trenches870,880, and890has a semicircular shape and includes several concentric end trenches. For example, the set of end trenches870has an end trench870A that is coupled at a first end aligned with (or coupled to) one of the plurality of trenches310via the transverse trench380A, and has a second end aligned with (or coupled to) another of the plurality of trenches310via the transverse trench380A.

Although not shown inFIG. 8, one or more of the end trenches from the sets of end trenches870,880, and/or890can have a trench width that is different than (e.g., wider than, narrower than) a width of one or more of the plurality of trenches310. For example, and trench870A can have a trench width that is less than a trench width of one of the plurality of trenches310corresponding with the trench870A.

In some implementations, a transverse trench can be excluded from the semiconductor device800. In some implementations, multiple transverse trenches similar to transverse trench380A can be included in the semiconductor device800and intersecting one or more of the plurality of trenches310and/or one or more of the sets of end trenches870,880, and/or890.

Although illustrated as having a semicircular shape, in some implementations, one or more of the sets of end trenches870,880, and/or890, can define a different pattern or a different shape. For example, although not shown, a set of end trenches can define a set of rectangular shaped end trenches that can be concentric. In some implementations, the spacing (or mesa width) between each trench from a set of end trenches can be approximately equal or can vary (e.g., can increase in width from the innermost end trench to the outermost end trench, can decrease in width from the innermost end trench to the outermost end trench).

FIGS. 9A through 9Nare diagrams that illustrate configurations of a termination region according to some implementations.FIG. 9Ais a diagram that illustrates a plan view (or top view along the horizontal plane) of at least a portion of a semiconductor device900including an active region902and a termination region904.FIGS. 9B through 9Nare side cross-sectional views along different cuts (e.g., cuts Q1 through Q10) within the plan viewFIG. 9A. To simplify the plan view shown inFIG. 9Asome of the elements illustrated in the side cross-sectional views ofFIGS. 9B through 9Nare not shown. The side cross-sectional views along the different cuts included inFIGS. 9B through 9Nare not necessarily drawn to the same scale (e.g., numbers of trenches, etc.) as the plan view shown inFIG. 9A. Variations of the semiconductor device900, which can be combined in any combination, are illustrated in at leastFIGS. 10A through 13L(and are numbered with the same or similar reference numerals).

As shown inFIG. 9A, a plurality of trenches910, including for example trenches910A through910J, are aligned along a longitudinal axis D1 within the semiconductor device900. At least some portions of the plurality of trenches910can be included in the active region902and at least some portions of the plurality of trenches910can be included in the termination region904. For example, a portion of trench910B is included in the active region902and a portion of the trench910B is included in the termination region904. As shown inFIG. 9A, trench910G is entirely disposed within the termination region904.

In this implementation, the trench910C and910D (which can be referred to as end trenches913) are entirely disposed within the termination region904and are the outermost trenches from the plurality of trenches910. Accordingly, the trenches910C and910D can be referred to as end trenches. Trenches from the plurality of trenches910in the semiconductor device900that are lateral to (or interior to) the end trenches910C and910D can be referred to as interior trenches917.

As shown inFIG. 9A, a source contact region936defines an area within the semiconductor device900where source contacts (not shown) (such as source contact957shown inFIG. 9K) are formed. The source contact region936can also correspond with, for example, a source conductor region (e.g., a source metal region). The source contacts can be contacted with source implants (such as source implant963E within a mesa region960E between trenches910E and910F shown inFIG. 9K) of one or more active devices. A source formation region956(which can be referred to as a source exclusion edge) defines an area within which mesa regions between the plurality of trenches910are doped as doped source regions of active devices.

A shield dielectric edge region934shown inFIG. 9Acorresponds with (e.g., approximately corresponds with), for example, an edge941of the inter-electrode dielectric940shown inFIG. 9B(which is a side cross-sectional view cut along line Q1). In some implementations, at least a portion of the inter-electrode dielectric940can include a gate dielectric such as gate dielectric portion942shown inFIG. 9B.

In this implementation, the active region902is defined by an area of the semiconductor device900that corresponds with a shield dielectric edge region934. The termination region904includes areas of the semiconductor device900outside of (e.g., excluded by) the active region902. Accordingly, the termination region904, similar to the active region902, is defined by the shield dielectric edge region934. The shield dielectric edge region934corresponds approximately with a mask area for a shield electrode, a gate electrode, and an inter-electrode dielectric active area recess. Shield electrodes, in this implementation, are recessed below gate electrodes. For example, as shown inFIG. 9B, at least a portion of a shield electrode930A is recessed below and insulated from a gate electrode920A by the inter-electrode dielectric940in trench910A.

In this implementation, portions of the plurality of trenches910(that are interior trenches917and) starting at line916(along longitudinal axis916) in the plurality of trenches910can be referred to as trench extension portions914. Portions of the plurality of trenches910(that are interior trenches917and) disposed to the right of line916and extend into (or toward) the active region902can be referred to as main trench portions912. The line916can indicate a point at which a change in depth (e.g., a recess) of one or more of the plurality of trenches910starts.

For example, trench910A includes a trench extension portion914A on the left side of line916(toward the perimeter and in a distal direction away from the active region902) and the trench910A includes a main trench portion912A on the right side of line916(away from the perimeter and in a proximal direction toward the active region902). In this implementation, at least a portion of the main trench portion912A is included in (e.g., disposed within) the termination region904, and a portion of the main trench portion912A is included in (e.g., disposed within) the active region902.

FIG. 9Bis a diagram that illustrates a side cross-sectional view of the semiconductor device900cut along line Q1. The cut line Q1 is approximately along a centerline of the trench910A so that the side cross-sectional view of the semiconductor device900is along a plane that approximately intersects a center of the trench910A. The features shown inFIG. 9Bare disposed in an epitaxial layer908of the semiconductor device900. Other portions of the substrate, drain contact, and/or so forth are not shownFIGS. 9A through 9N. Many of the views associated with other figures are disposed in an epitaxial layer and similarly do not show the substrate, drain contact, and so forth.

As shown inFIG. 9B, the trench910A includes a dielectric970A disposed therein. Specifically, a portion of the dielectric970A is coupled to (e.g., lines, is disposed on) a sidewall and a portion of the dielectric970A is coupled to a bottom surface of the trench910A within the main trench portion912A of the trench910A. In this cross-sectional view the portion of the dielectric970A coupled to the bottom surface of the trench910A is shown, and the portion of the dielectric970A coupled to the sidewall of the trench910A is not shown. In some implementations, the portion of the dielectric970A shown inFIG. 9Balong the bottom surface of the main trench portion912A of the trench910A can be referred to as a bottom dielectric. In some implementations, the dielectric970A can be coupled to, or can include, a field dielectric974(which can be referred to as a field dielectric portion).

As shown inFIG. 9B, a gate electrode920A and a portion931A of a shield electrode930A are disposed in a portion of the main trench portion912A that is included in the active region902of the semiconductor device900. The gate electrode920A and the shield electrode930A are separated by (e.g., insulated by) at least a portion of the inter-electrode dielectric940. The portion of the main trench portion912A included in the termination region904has a portion933A of the shield electrode930A disposed therein and insulated from the epitaxial layer908by the dielectric970A. In some implementations, the portion933A of the shield electrode930A can be referred to as a termination region portion of the shield electrode, and the portion931A of the shield electrode930A can be referred to as an active region portion of the shield electrode. As shown inFIG. 9B, the portion933A of the shield electrode930A extends up to and contacts a bottom surface of an interlayer dielectric (ILD)992(which could include another dielectric such as field dielectric974(and/or a gate oxide)) along a thickness R28. The portion933A of the shield electrode930A has a vertical height (or top surface) within the trench910A higher than a top surface of the portion931A of the shield electrode930A, which is recessed within the trench910A. The portion933A of the shield electrode930A also has a thickness (e.g., vertical thickness) within the trench910A greater than a thickness of the portion931A of the shield electrode930A. The portion933A extends vertically along a profile (e.g., a sidewall profile) (not shown) of the trench extension portion914A. The portion933A of the shield electrode930A has a portion is disposed between an edge of the gate electrode920A (and the edge941of the inter-electrode dielectric940and/or the gate dielectric portion942) and the transverse trench983A.

In this implementation, a surface shield electrode and a surface gate electrode are excluded from the semiconductor device900. This is contrasted with the semiconductor device300shown inFIGS. 3A through 3Iwhich includes a surface shield electrode and a surface gate electrode. As shown inFIG. 9A, a gate runner conductor952is coupled directly to the gate electrodes included in at least some of the plurality of trenches910through vias951. For example, gate electrodes in multiple (e.g., more than three) adjacent trenches from the plurality of trenches910are coupled to the gate runner through vias951. Specifically, each of gate electrodes of the plurality of trenches910that includes an active device is coupled to the gate runner conductor952through vias951. Similar to the gate runner conductor952, a source runner conductor954(which is similar to portion933A) is brought up to at least a surface of the epitaxial layer (aligned with plane D4) in the active region902and (which is configured to be coupled to a source potential) is coupled to each source within the plurality of trenches910using one or more vias (not shown).

As shown inFIG. 9A, a doping region938is an area within which a well implant (e.g., a p-type well implant, an n-type well implant) is performed. In this implementation, the doping region938is associated a p-well dopant region (e.g., well dopant region962A shown inFIG. 9C). In this implementation, because a surface shield electrode and a surface gate electrode are excluded from the semiconductor device900the well implant can be performed over a larger area of the semiconductor device900. For example, the area within which a well implant can be performed within the semiconductor device300was limited by a surface area of the surface shield electrode332and/or a surface area of the surface gate electrode322, which block implantation to form the well implant. As a specific example, inFIGS. 3B and 3C, areas of the epitaxial layer308(such as the mesa region360A) under the gate runner conductor352and/or the source runner conductor354could not be implanted with a well implant because the surface shield electrode332and the surface gate electrode322are disposed below the gate runner conductor352and below the source runner conductor354.

In contrast, because the semiconductor device900does not include a surface shield electrode or a surface gate electrode, implantation to form a well implant is not blocked. Accordingly, a well implant can be performed over virtually the entire surface area of the semiconductor device900.

As shown inFIG. 9C, a well dopant region962A extends below the source runner954and below the gate runner conductor952. Although not shown, in some implementations, the well dopant region962A can extend below under only the source runner954or only below the gate runner conductor952(if in a different location). Although not shown, the well dopant region962A can be extended toward the perimeter (e.g., in a distal direction away from the active region920).

An area where the well dopant region962A can be optionally expanded is illustrated with line961. In other words, in some implementations, the well dopant region962A can be expanded up to (e.g., can extend to, can be disposed up to and abut or contact) one or more of the perimeter trenches990A,990B. In such embodiments, the expansion of the well dopant region962A along line961can be implemented in conjunction with the addition of, for example, a transverse trench such as transverse trench383A shown inFIG. 3Aor transverse trench983A shown inFIG. 10Aas a few examples. The transverse trench can be a transverse trench that has an edge substantially aligned with, for example, an edge (e.g., a terminating edge) of the shield electrode930A that is disposed within the trench910A.

In some implementations, the well dopant region can be expanded beyond (e.g., can extend beyond, can be disposed beyond) one or more of the perimeter trenches990A,990B. The line961is illustrated in additional figures associated withFIGS. 9A through 9N. By doping, for example, the entire surface of the semiconductor device900, a doping mask associated with, for example, doping region938can be obviated.

In this implementation, for desirable charge balancing, a length R18 (which can be referred to as a lateral balance length) is equal to or greater than depth R3 (shown inFIG. 9B). The length R18 extends from an end of the main trench portion912A (starting at line916shown inFIG. 9B) to an edge964A of the well dopant region962A (shown inFIG. 9C). In some implementations, length R18 can be less than or equal to length R17, or greater than length R17. When edge964A of the well dopant region962A is spaced laterally (such that R18 is approximately greater than R3, for example) the breakdown can be maintained in the active region902rather than occurring in the termination region904. The breakdown voltage, reliability during testing (e.g., unclamped inductive switching (UIS)), device performance, and/or so forth of the semiconductor device900can be maintained in the active region902when the depletion edge laterally from the edge964A of the well dopant region962A is greater than the vertical depletion associated with distance R3. By doing so, the electric field in the vertical direction can be greater than the electric field in the lateral direction.

Referring back toFIG. 9B, a portion972A of the dielectric970A (also referred to as an extension portion of the dielectric or as an extension dielectric) is included in the trench extension portion914A. The portion972A of the dielectric970A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the trench extension portion914A of the trench910A to at least a top of the trench910A. The top of the trench910A (which includes the trench portion914A and the main trench portion912A) is aligned along a plane D4, which is aligned along a top surface of a semiconductor region of the semiconductor device900. In some implementations, the semiconductor region of the semiconductor device900can correspond approximately with a top surface of the epitaxial layer908. In some implementations, the dielectric970A can include one or more dielectric layers and/or one or more dielectric types formed using one or more different formation processes.

As shown inFIG. 9B, a portion971A of the dielectric970A is included in at an end of the main trench portion912A. The portion971A of the dielectric970A is aligned along (e.g., extends in) a vertical direction D3 from a bottom of the transverse main trench portion912A to at least a top of the main trench portion912A. The top of the main trench portion912A is aligned along the plane D4.

The thickness of the dielectric970A included in the trench910A varies along the longitudinal axis D1 of the trench910A. The portion972A of the dielectric970A included in the trench extension portion914A has at least a thickness R1 in the trench extension portion914A (also can be referred to as a height because it is aligned along the vertical axis D3) that is greater than a thickness R2 of a portion of the dielectric970A included in the main portion912A (both in a termination region portion and in an active region portion) of the trench910A. The thickness of the portion972A of the dielectric970A extends up to the bottom surface of the inter-layer dielectric (IED)992beyond the thickness R1. The thickness R1 corresponds approximately with a depth (along the vertical direction D3) of the trench extension portion914A.

Also, the portion971A of the dielectric970A included in the main trench portion912A has at least a thickness R3 (also can be referred to as a height) that is greater than the thickness R2 of a portion of the dielectric970A included in the main portion912A of the trench910A and is less than the thickness R1 of the portion972A of the dielectric970A included in the trench extension portion914A. The thickness of the portion971A of the dielectric970A shown inFIG. 9Bextends up to a bottom surface of the inter-layer dielectric992beyond the thickness R3. The thickness R3 corresponds approximately with a depth (along the vertical direction D3) of the main trench portion912A. Accordingly, a depth of the trench910A varies along the longitudinal axis D1 from depth R3 to depth R1.

Referring back toFIG. 9B, in this implementation, the trench extension portion914A includes the portion972A of the dielectric970A and excludes a shield electrode. Although not shown, in some implementations, a trench extension portion such as the trench extension portion914A can include a portion of a shield electrode (e.g., a portion of a shield electrode, a recessed shield electrode).

Although not shown inFIG. 9B, in some implementations, the thickness R2 of the portion of the dielectric970A in the main portion912A of the trench910A can vary along the longitudinal axis D1. For example, a thickness of a portion of the dielectric970A included in the termination region904of the main trench portion912A can be greater than a thickness of a portion of the dielectric970A included in the active region902of the main trench portion912A, or vice versa.

As shown inFIG. 9B, a length R16 of the trench extension portion914A of the trench910A is longer than a length R17 of a portion of the main trench portion912A of the trench910A included in the termination region904(up to the edge941of the gate dielectric portion942of the IED940). Although not shown, the length R16 of trench extension portion914A of the trench910A can be equal to or shorter than the length R17 of the portion of the main trench portion912A of the trench910A included in the termination region904.

The thickness R2 of the portion972A of the dielectric970A included in the trench extension portion914A is configured to have termination region advantages such as those described above. Specifically, an undesirable electric field or breakdown across the dielectric970A included in the main trench portion912A can be prevented or substantially prevented inclusion of the trench extension portion914A within the semiconductor device900. In other words, an undesirable electric field at the end of a trench (i.e., the main trench portion912A without the trench extension portion914A) or breakdown across a dielectric at the end of the trench could occur without features such as the trench extension portion914A.

Referring back toFIG. 9A, perimeter trenches990A,990B are disposed around a perimeter of the plurality of trenches910. As shown inFIG. 9B, the perimeter trenches990A,990B have a depth R5 that is approximately equal to a depth (e.g., distance R3) of the main trench portion912A. The depth R5 of the perimeter trenches990A,990B is less than a depth (e.g., distance R1) of the trench extension portion914A. In some implementations, the depth of one or more of the perimeter trenches990A,990B can be less than or greater than the depth of the main trench portion912A. In some implementations, the depth of one or more of the perimeter trenches990A,990B can be greater than or equal to the depth of the trench extension portion914A. In some implementations, the width of one or more of the perimeter trenches990A,990B can be approximately the same as or different than (e.g., narrower than, wider than) the width of the main trench portions912of the plurality of trenches910.

In this implementation, each of the perimeter trenches990A,990B includes at least a portion of a shield electrode. For example, the perimeter trench990A includes a shield electrode935(or shield electrode portion). In some implementations, one or more of the perimeter trenches990A,990B can include a recessed electrode, or may not include a shield electrode (e.g., may exclude a shield electrode and can be substantially filled with a dielectric). In some implementations, the semiconductor device900can include more or less perimeter trenches than shown inFIGS. 9A through 9N.

As shown inFIG. 9A, a portion of the gate electrode920A is recessed below the ILD992. The recessing of the gate electrode920A defines an edge979(shown inFIG. 9B) that corresponds with a mask layer999shown inFIG. 9A. The recessing can be performed for a self-aligned dimple contact (using contact951) active area of the gate electrode920A. For an aligned contact a relatively shallow recess can be formed across the gate electrode920A. An example of such an embodiment is shown inFIG. 10E. A portion of the gate electrode920A in electrical contact with the gate runner conductor952through the via951is not recessed. More details related to recessing of a gate electrode are discussed below in connection with, for example,FIG. 10B.

Referring back toFIG. 9A, the trench extension portions914have widths that are approximately equal to widths of the main trench portions912. The widths of the trenches described herein can be measured across a cross-section of the trenches while being referenced along a horizontal plane through the trenches. In some implementations, the widths can be referred to as cross-sectional widths. As a specific example, the trench extension portion914A of the trench910A has a width R10 that is approximately equal to a width R11 of the main trench portion912A of the trench910A. This consistency in width is also shown in, for example, trench910E in the various views. Specifically, trench910E shown inFIG. 9H(which is cut along line Q7 through the trench extension portions914orthogonal to the plurality of trenches910) has a width R8 that is approximately equal to, for example, the width R8 of the trench910E shown inFIG. 9I(which is cut along line Q8 through the main trench portions912orthogonal to the plurality of trenches910). Although not shown inFIG. 9A, one or more of the trench extension portions914can have widths that are less than or are greater than the widths of one or more of the main trench portions912.

Although not shown, one or more transverse trenches can be included in the semiconductor device900and can be aligned along a longitudinal axis D2 that is orthogonal to (e.g., substantially orthogonal to) the longitudinal axis D1. The transverse trench(es) can be similar to the transverse trenches (e.g., transverse trench380A, transverse trench383A) described above.

FIG. 9Dis a side cross-sectional view of a mesa region960G adjacent to trench910G cut along line Q3. In this implementation, the mesa region960G is entirely disposed within the termination region904. As shown inFIG. 9D, well dopant region962G is included in the mesa region960G. As mentioned above, an area where the well dopant region962G could be expanded is illustrated with line961.

FIG. 9Eis a side cross-sectional view of the trench910G, which is cut along line Q4 shown inFIG. 9A. In this implementation, the trench910G is entirely disposed within the termination region904. Trench910G, and other trenches entirely disposed within the termination region904, can be referred to as termination trenches918. The dimension of the trench910G (which includes extension dielectric972G) is similar to the dimensions of (e.g., dimensions that are directly lateral to) the trench910A shown inFIG. 9B. In some implementations, the dimensions of the trench910G can be different than corresponding portions of the trench910A shown inFIG. 9B. For example, the trench910G can have a constant depth, which can be the same as or different than (e.g., deeper than, shallower than) the depth R1 of the trench extension portion914A (shown inFIG. 9B) or the same as or different than (e.g., deeper than, shallower than) the depth R3 of the main trench portion912A.

In some implementations, the shield electrode930G disposed within the trench910G can be electrically floating. In some implementations, the shield electrode930G disposed within the trench910G can be electrically coupled to a source potential. Accordingly, the shield electrode930G can be tied to the same source potential as the shield electrode930A shown inFIG. 9B. In some implementations, the shield electrode930G disposed within the trench910G can be recessed. As mentioned above, an area where the well dopant region962G could be expanded is illustrated with line961.

FIG. 9Fis a side cross-sectional view of a mesa region960C adjacent to the end trench910D, which is cut along line Q5 shown inFIG. 9A. In this implementation, the mesa region960C is disposed outside of the doping region938. Accordingly, a well dopant region is excluded from the mesa region960C. As mentioned above, an area where a well dopant region can be included in one or more portions of a cross-sectional area is illustrated with line961.

FIG. 9Gis a side cross-sectional view of the end trench910D, which is cut along line Q6 shown inFIG. 9A. The end trench910D is filled with a dielectric970D. Although not shown, in some implementations, at least a portion of the end trench910D can include a shield electrode. The end trench910D can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench910A.

The end trench910D has a depth R12 greater than a depth R5 of the perimeter trenches990A,990B. In some implementations, the end trench910D can have a depth E12 equal to, or less than a depth of one or more of the perimeter trenches990A,990B. In this implementation, the depth R12 of the end trench910D is approximately equal to a depth (e.g., distance R1) of the trench extension portion914A (shown inFIG. 9B). In some implementations, the end trench910D can have a depth R12 that is less than or greater than a depth (e.g., distance R1) of the trench extension portion914A (shown inFIG. 9B). In some implementations, the end trench910D can have a depth that varies, similar to the variation in depth of trench910A.

Although not shown, in some implementations, multiple trenches similar to end trench910D, which are filled with a dielectric can be included in the semiconductor device900. An example of such an implementation is described in connection withFIGS. 4A through 4Eabove. Although not shown, in some implementations, a trench that varies with width and has a portion that includes a shield electrode, such as trench910C can be an end trench. In such implementations, the end trench910D can be omitted.

As mentioned above,FIG. 9His cut along line Q7 (shown inFIG. 9A) through the trench extension portions914orthogonal to the plurality of trenches910. In this implementation, the widths of the plurality of trenches910in the trench extension portions are the same as the widths of the plurality of trenches910in the main trench portions. Also, each of widths of the plurality of trenches910is the same across the plurality of trenches910within the trench extension portions. For example, as shown inFIG. 9Hthe end trench910D has a width R13 that is approximately equal to the width R8 of the trench extension portion of trench910E. In some implementations, the end trench910D can have a width that is greater than, or less than, the width R8 of the trench extension portion of trench910E.

A pitch R14 between the end trench910D and end trench910C (which are adjacent trenches) is approximately equal to a pitch R15 between trench910E and trench910F (which are adjacent trenches). In some implementations, the pitch R14 between the end trench910D and end trench910C can be the less than, or greater than, the pitch R15 between trench910E and trench910F.

FIG. 9Iis a side cross-sectional view cut along line Q8 (shown inFIG. 9A) through the main trench portions912orthogonal to the plurality of trenches910. In this implementation, the gate runner conductor952is disposed above the plurality of trenches910, and the line Q8 intersects along a relatively shallow portion of the interior trenches917from the plurality of trenches910. Both end trench910D and910C (i.e., end trenches913) include a dielectric without a shield electrode, while the remainder of the plurality of trenches910along this cutline Q9 (which includes the interior trenches917) each include a shield electrode. Also, the depth R12 of end trenches910D,910C is greater than a depth of the remainder of the trenches (e.g., non-end trenches, interior trenches917), which include shield electrodes.

As mentioned above, in this implementation, the widths of the plurality of trenches910in the trench extension portions are the same as the widths of the plurality of trenches910in the main trench portions. Also, each of the widths of the plurality of trenches910is the same across the plurality of trenches910within the main trench portions. For example, as shown inFIG. 9Ithe end trench910D in the main trench portion has a width R13 that is approximately equal to the width R8 of the main trench portion of trench910E. In some implementations, the end trench910D can have a width in the main trench portion that is greater than, or less than, the width R8 of the main trench portion of trench910E.

FIG. 9Jis a side cross-sectional view cut along line Q9 (shown inFIG. 9A) through the main trench portions912orthogonal to the plurality of trenches910between the gate runner conductor952and the source runner conductor954. Different types of interior trenches917from the plurality of trenches910are included in this view. The end trenches913include a dielectric without a shield electrode, while the remainder of the plurality of trenches910along this cutline Q9 each include at least a shield electrode. Specifically, both trench910G and910K, which can be referred to as transition region trenches915(which are included in the interior trenches917), include a shield electrode that is grounded and each does not include a gate electrode. The remaining trenches (excluding the end trenches913and the transition region trenches915) each includes a gate electrode as well as a shield electrode.

In some implementations, the end trenches913can include less than two trenches or more than two trenches, and the transition region trenches915can include less than two trenches or more than two trenches. For example, in some implementations, the transition region trenches915can be excluded or converted to an active trench. In such implementations, the end trench910C can be in contact with an active trench. Such an implementation is illustrated in, for example,FIG. 9E(and are described in connection with additional variations to semiconductor device900below).

As shown inFIG. 9E, the end trench910C is in contact with or overlaps in parallel with the active trench910G. In other words, a profile of the end trench910C (shown with a dashed line) intersects (e.g., overlaps, contacts) a profile of the active trench910G (shown with a dashed line). Accordingly, the active trench910G is self-aligned to the end trench910C. Similar structures are described and shown in other variations, however, the trench profiles are not shown in all of the figures. InFIG. 9E, a surface shield conductor and a surface gate conductor are excluded.

In some implementations, the shield electrodes included in the transition region trenches915can be electrically floating. Trenches910C,910D,910G, and910K, which are trenches entirely disposed (along the longitudinal axis D1 within the termination region904, can be referred to as termination trenches918.

In this implementation, the mesa region960G (and the well dopant region962G) can be a grounded or electrically floating mesa region. In some implementations, the mesa region960G (and the well dopant region962G) can be coupled to a source potential. In such implementations, a source contact such as source contact957can be coupled to the mesa region960G. In some implementations, a mesa region between one or more end trenches such as the end trenches913and/or a mesa region between transition region trenches such as the transition region trenches915can be electrically floating or grounded. In some implementations, the mesa region between the one or more transition region trenches can be coupled to a source potential. Also, in some implementations, a mesa region disposed between the transition region trenches915and the end trenches913can be electrically floating.

FIG. 9Kis a side cross-sectional view of the main trench portions912of the plurality of trenches910cut along line Q10 shown inFIG. 9Athrough the termination region904and into the active region902. A portion of the cross-sectional view of the plurality of trenches910is included in the termination region904and a portion of the cross-sectional view of the plurality of trenches910is included in the active region902.

Because the width of the end trench910D is substantially constant along the longitudinal axis D1, in this implementation, the width R13 of the end trench910D (shown inFIG. 9K) is the same along cut line Q10 as along, for example, cut line Q7 (shown inFIG. 9H). Similarly, the width of at least some of the trenches such as, for example, trench910C and trench910E is constant (substantially constant) along the longitudinal axis D1.

As shown inFIG. 9K, the trenches from the plurality of trenches910that include source implants therebetween can be referred to as active device trenches919. Because the general structure of the active device trenches919, the partially active gate trench, the termination trenches918, the source implants, and so forth are similar to those shown inFIG. 3I, these features will not be described again here in connection withFIG. 9Kexcept as otherwise noted. Although not shown inFIG. 9K, the end trenches910D and/or910C can include at least a portion of a shield electrode (e.g., a recessed shield electrode, a shield electrode with a thick bottom oxide disposed below, an electrically floating shield electrode, a shield electrode coupled to a source potential (e.g., via the source conductor runner954) or a gate potential (e.g., via the gate conductor runner952)).

FIG. 9Lis a variation ofFIG. 9B. As shown inFIG. 9B, length R17 extends between an edge (not labeled) of the dielectric970A and edge941such that portion971A (shown inFIG. 9B) is excluded. In some implementations, portion971A can be included. As shown inFIG. 9L, the semiconductor device900includes a dielectric portion974A (which can also be referred to as protrusion dielectric and is illustrated inFIG. 9Lwith a dashed line) that is recessed (similar to or the same as the dielectric disposed above the recessed portion936G of the shield electrode930G shown inFIG. 12H). Accordingly, a portion of the shield electrode930A is recessed below the dielectric portion974A. The dielectric portion974A intersects (e.g., is in contact with, overlaps), or is a part of, the portion972A of the dielectric970A included in the trench extension portion914A (or intersects a profile (which is not shown with a dashed line in this figure) of the trench extension portion914A). The depth of the recess of the shield electrode930A below dielectric portion974A is approximately at a same depth as a bottom surface of the inter-electrode dielectric940. As shown inFIG. 9B, the shield electrode930G (from the left to right) is recessed (e.g., first recess) below dielectric portion974A, is not recessed (e.g., protrudes vertically, extends up to a top of the trench910A) between an edge943of the dielectric portion974A and the edge941of the inter-electrode dielectric940, and then is also recessed (e.g., second recess) below inter-electrode dielectric940.FIG. 9Mis a diagram that illustrates trench910G including dielectric974G (which can be referred to as a protrusion dielectric), which corresponds with dielectric974A shown inFIG. 9L. Many of the other features of the semiconductor device900, such as the edge964A of the well dopant region962A shown inFIG. 9C, can be integrated with the features shown inFIGS. 9L and 9M.

The dielectric974A (and similar protrusion dielectrics shown in other implementations) can eliminate a high electric field near the end of the trench910A, thus increasing stability, reliability, and breakdown voltage of the semiconductor device900(and associated termination region904). The dielectric974A can also mitigate high lateral electric fields toward the end of the trench910A (along direction D1 toward the left and near the portion972A of the dielectric970A) that could be due to relatively light surface doping concentrations near the end of the trench910A.

FIGS. 10A through 10Oare diagrams that illustrate variations on at least some of the features of the semiconductor device900shown inFIGS. 9A through 9N. Accordingly, the reference numerals and features included inFIGS. 9A through 9Nare generally maintained and some features are not described again in connection withFIGS. 10A through 10O.

InFIGS. 10A through 10O, a perimeter trench910L similar to the end trench910C is disposed within the semiconductor device900. The perimeter trench910L includes a portion aligned along the longitudinal axis D1 that is included within the plurality of trenches910. The perimeter trench910L is different from the perimeter trenches990A,990B because the perimeter trench910L is filled with the dielectric (and excludes a shield electrode) while the perimeter trenches990A,990B each include a shield electrode.

Also, as shown inFIGS. 10A through 10O, the end trench910C is coupled to a transverse trench983A. In some implementations, the end trench910C and the transverse trench983A can collectively be referred to as a perimeter trench that has a transverse portion. In some implementations, the end trench910C, the transverse trench983A, and/or the perimeter trench910L can be produced using the same etching process, or multiple separate etching processes.

The transverse trench983A is similar to the transverse trench383A shown and described in connection withFIGS. 7A through 7J. Because the transverse trench983A is disposed at the ends of the plurality of trenches910(or parallel trenches). Accordingly, each of the plurality of trenches910is not bisected into trench extension portions and main trench portions as discussed in connection withFIGS. 9A through 9N. Specifically, the transverse trench983A as shown inFIG. 9Ais aligned parallel to the perimeter trenches990A,990B,910L (along the longitudinal axis D2), but is disposed between the termination trench990A,990B,910L and the ends of the plurality of trenches910, which are orthogonally aligned to the transverse trench983A. The side cross-sectional views along the different cuts included inFIGS. 10B through 10Oare not necessarily drawn to the same scale (e.g., numbers of trenches, etc.) as the plan view shown inFIG. 10A.

FIG. 10Bis a diagram that illustrates a side cross-sectional view of the semiconductor device900cut along line Q1. The cut line Q1 is approximately along a centerline of the trench910A so that the side cross-sectional view of the semiconductor device900is along a plane that approximately intersects a center of the trench910A. As shown inFIG. 10B, the trench910A includes a dielectric970A disposed therein. Specifically, a portion of the dielectric970A is coupled to (e.g., lines, is disposed on) a sidewall and a portion of the dielectric970A is coupled to a bottom surface of the trench910A within the main trench portion912A of the trench910A.

As shown inFIG. 10B, a gate electrode920A and a portion931A of a shield electrode930A are disposed in the trench910A that is included in the active region902of the semiconductor device900. The gate electrode920A and the shield electrode930A are separated by (e.g., insulated by) at least a portion of the inter-electrode dielectric940. A portion933A of the shield electrode930A is also disposed in the trench910A and insulated from the epitaxial layer908by the dielectric970A. In some implementations, the portion933A of the shield electrode930A can be referred to as a termination region portion of the shield electrode, and the portion931A of the shield electrode930A can be referred to as an active region portion of the shield electrode.

A dielectric portion976A is disposed within the transverse trench983A. The dielectric portion976A of the transverse trench983A is coupled to the dielectric970A included in the trench910A. The dielectric portion976A and the dielectric970A can be formed using one or more different dielectric formation processes (e.g., a thermal dielectric formation process, a deposition process). Accordingly, the dielectric portion976A and the dielectric970A can be different dielectrics.

The perimeter trench910L and the transverse trench983A have a depth R1 that is greater than a thickness R2 of a portion of the dielectric970A included in the trench910A. The perimeter trenches990A,990B have a depth R5 that is approximately equal to a depth R3 of the trench910A. The depth R5 of the perimeter trenches990A,990B is less than the depth R1 of the perimeter trench910L and the transverse trench983A. In some implementations, the depth of one or more of the perimeter trenches990A,990B can be less than or greater than the depth of the transverse trench983A and/or the depth of the perimeter trench910L. In some implementations, the depth of one or more of the perimeter trenches990A,990B can be greater than or equal to the depth of the trench910A. Although not shown, in some implementations, the transverse trench983A can have a depth that is approximately equal to the depth R3 of the trench910A.

In some implementations, the width of one or more of the perimeter trenches990A,990B can be approximately the same as or different than (e.g., narrower than, wider than) the width of the plurality of trenches910, the width of the transverse trench983A, and/or the width of the perimeter trench910L. In some implementations, the perimeter trench910L can have a width R19 greater than a width R20 of the perimeter trench990A. Similarly, in some implementations, the transverse trench983A can have a width R21 greater than the width R20 of the perimeter trench990A. Although the cross-sectional dimensions of the transverse trench983A and the cross-sectional dimensions of the perimeter trench910L are approximately the same, in some implementations, the cross-sectional dimensions can be different.

In this implementation, the portion933A of the shield electrode930A is in contact with a dielectric portion976A disposed within the transverse trench983A. Also, the portion933A of the shield electrode930A is insulated from the interlayer dielectric992by a dielectric portion977A. The dielectric portion977A is disposed below the gate runner conductor952, and has a thickness that is less than a thickness of the field dielectric974. In some implementations, the gate electrode920A can be referred to as having a first portion that is recessed relative to a bottom surface of the ILD992below the field dielectric974compared with a second portion that is recessed to a lesser degree (or not recess at all) relative to the bottom surface of the ILD992and disposed below the dielectric portion977A. In other words, the gate electrode920A can include a first recessed portion (which can be disposed below the dielectric portion977A and below the gate runner conductor952) and a second recessed portion (which can have at least a portion disposed below the field dielectric974and below the source runner conductor954).

In some implementations, the dielectric portion977A can be a portion of the field dielectric974. In some implementations, the dielectric portion977A can be disposed around (e.g., can define a perimeter around) the via951. In some implementations, the dielectric portion977A can be in contact with or can be disposed on the gate dielectric portion942.

In this implementation, the transverse trench983A can be used for self-aligned etching of one or more of the plurality of trenches910. Specifically, a first mask used to form the transverse trench983A can overlap with a second mask used to form the plurality of trenches910. Accordingly, misalignment of the first mask and the second mask may not be problematic because of the overlap, which will result in the transverse trench983A still intersecting with one or more of the plurality of trenches910(or the ends thereof). An illustration of the overlap (from a masking perspective) is shown inFIG. 10L. As shown inFIG. 10L, ends929of the plurality of trenches910intersect with the transverse trench983A.

Referring back toFIG. 10B, in this implementation, the perimeter trench910L and the transverse trench983A each exclude a shield dielectric. Although not shown, in some implementations, at least a portion of the perimeter trench910L and/or at least a portion of the transverse trench983A can include a portion of a shield electrode (e.g., electrically floating shield electrode, a recessed shield electrode).

FIG. 10Cis a side cross-sectional view of the mesa region960A cut along line Q2. In this cross-sectional view, the well dopant region962A extends below the source runner conductor954and below the gate runner conductor952. In this implementation, the well dopant region962A contacts the dielectric portion976A included in the transverse trench983A. In accordance with prior examples, an area where the well dopant region962A could be expanded is illustrated with line961.

As mentioned above, an area where the well dopant region962A could be expanded is illustrated with line961. In other words, in some implementations, the well dopant region962A can be expanded up to (e.g., can extend to, can be disposed up to and abut or contact) one or more of the perimeter trenches990A,990B. In some implementations, the well dopant region can be expanded beyond (e.g., can extend beyond, can be disposed beyond) one or more of the perimeter trenches990A,990B. The line961is illustrated in additional figures associated withFIGS. 10A through 10K.

In some implementations, the well dopant region962A can be truncated to (e.g., can extend to, can be disposed up to and abut or contact) end between the left edge of gate electrode920A and left edge of shield electrode933A.

Similar structures and features are illustrated in the cross-sectional view of the mesa region960G cut along line Q3 as illustrated inFIG. 10G. InFIG. 10G, the mesa region960G is entirely disposed within the termination region904. Accordingly, the source runner conductor954has a substantially flat bottom surface that can be insulated from (e.g., does not contact) the mesa region960G. In some implementations, the source runner conductor954can be configured to come in contact with at least a portion of the mesa region960G using, for example, one or more vias.

FIG. 10Dis a side cross-sectional view of a variation of the trench910A of the semiconductor device900cut along line Q1. In this implementation, the shield electrode930A is in contact with the dielectric portion976A included in the transverse trench983A. The shield electrode930A, however, has a constant thickness R22 along the longitudinal axis D1 of the trench910A. In this implementation, the termination region904is approximately aligned along a side wall of the transverse trench983A. Also, the shield electrode930A is disposed entirely within the active region902, rather than having a first portion disposed in the termination region904and a second portion disposed in the active region902. Also, the gate dielectric portion942of the IED940is in contact with the dielectric portion976A included in the transverse trench983A. In such implementations, the gate dielectric portion942of the IED can be referred to as, and can function as, a protrusion dielectric (similar to, for example, protrusion dielectric974A shown inFIG. 9L).

FIGS. 10E and 10Fillustrates side cross-sectional views that are variations of the trench structure of trench910A illustrated inFIG. 10A. As shown inFIG. 10E, gate electrode920A is recessed to a lesser extent than the gate electrode920A shown inFIG. 10F. Accordingly, the field dielectric974disposed between the gate electrode920A and the interlayer dielectric992is thinner inFIG. 10Ethan inFIG. 10F.

WithinFIG. 10E, a first portion of the field dielectric974within the active region902has a thickness that is less than a thickness of a second portion of the field dielectric974included in the termination region904. Also as shown inFIG. 10E, the field dielectric974has a relatively constant thickness along a top surface of the gate electrode920A.

WithinFIG. 10F, a first portion of the field dielectric974within the active region902has a thickness that approximately the same as a thickness of a second portion of the field dielectric974included in the termination region904. InFIG. 10F, the field dielectric974has a third portion disposed above the portion933A of the shield dielectric930A (and below the ILD992) that has a thickness is less than the thickness of the first portion of the field dielectric974and/or the first portion of the field dielectric974. Also as shown inFIG. 10E, the field dielectric974has a relatively constant thickness along a top surface of the gate electrode920A. The features illustrated inFIGS. 10B, 10D, 10E, and 10F, can be combined in any combination except for mutually exclusive combinations.

FIG. 10His a side cross-sectional view of the trench910G, which is cut along line Q4 shown inFIG. 10A. In this implementation, the trench910G is entirely disposed within the termination region904. As shown inFIG. 10H, the shield electrode930G has a thickness that extends from the dielectric970G along a bottom of the trench910G to the field oxide974. In some implementations, the field oxide974can be aligned along plane D4. In some implementations, the shield electrode930G disposed within the trench910G can be recessed.

FIG. 10Iis a side cross-sectional view of a mesa region960G adjacent to the end trench910C, which is cut along line Q5 shown inFIG. 10A. In this implementation, the mesa region960G is disposed outside of the doping region938. Accordingly, a well dopant region is excluded from the mesa region960G.

FIG. 10Jis a side cross-sectional view of the end trench910C, which is cut along line Q6 shown inFIG. 10A. The end trench910C has a dielectric970C disposed therein. Although not shown, in some implementations, at least a portion of the end trench910C can include a shield electrode. The end trench910C can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench910A.

FIG. 10Kis a side cross-sectional view of the transverse trench983A, which is cut along line Q7 (along longitudinal axis D2) shown inFIG. 10A. The transverse trench983A has a dielectric973A disposed therein (e.g., from a bottom of the transverse trench983A to a top of the transverse trench983A). Although not shown, in some implementations, at least a portion of the transverse trench983A can include a shield electrode. The transverse trench983A can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench910A.

FIG. 10Mis a variation ofFIG. 10H. As shown inFIG. 10M, the semiconductor device900includes a dielectric portion974G that is recessed (similar to or the same as the dielectric disposed above the shield electrode930G shown inFIG. 9M). Accordingly, a portion of the shield electrode930G is recessed below the dielectric portion974G (e.g., protrusion dielectric) and the dielectric portion974G is coupled to the dielectric portion976A included in the transverse trench983A. Yet another variation of the semiconductor device900, which includes a dielectric portion974A (that corresponds with dielectric portion974G shown inFIG. 10M), is shown inFIG. 10O.FIG. 10Ois a variation ofFIG. 10B, and portion933A of the shield electrode930A is excluded.

FIG. 10Nillustrates another variation on the semiconductor device900. As shown inFIG. 10N, an edge964G of the well dopant region962A is separated from the transverse trench983A (e.g., a sidewall of the transverse trench983A) by a gap (e.g., a semiconductor region) having a length R24. The length R24 can be less than or equal to length R25 (shown inFIG. 10M or 10O), or greater than length R25. The length R24 can be less than or equal to length R29 (shown inFIG. 10Efrom the transverse trench983A to an edge of the gate electrode920A, or greater than length R29. The length R29 is also shown in other figures such asFIG. 10F. In this implementation, for desirable charge balancing, a length R24 (which can be referred to as a lateral balance length) is equal to or greater than depth R3 (shown inFIGS. 10B, 10D, 10E, 10F, &10O).

The general features of cross-sections along lines Q8 through Q10 in this implementation associated withFIG. 10Aare similar to the features along cut lines Q8 through Q10 illustrated inFIGS. 9I through 9K and 9N. Accordingly, cross-sectional diagrams along lines Q8 through Q10 are not shown in connection withFIG. 10A.

FIGS. 11A through 11Eare diagrams that illustrate variations on at least some of the features of the semiconductor device900shown inFIGS. 9A through 9NandFIGS. 10A through 10O. Accordingly, the reference numerals and features included inFIGS. 9A through 9NandFIGS. 10A through 10Oare generally maintained and some features are not described again in connection withFIGS. 11A through 11E. Specifically,FIGS. 11B through 11Eillustrate variations along cut lines Q8 through Q10, respectively.

As shown inFIG. 11A, the perimeter trench910L includes a portion aligned along the longitudinal axis D1 that is included within the plurality of trenches910. The perimeter trench910L is different from the perimeter trenches990A,990B because the perimeter trench910L is filled with the dielectric (and excludes a shield electrode) while the perimeter trenches990A,990B each include a shield electrode.

Also, as shown inFIGS. 11A through 11M, the end trench910C is coupled to a transverse trench983A. In some implementations, the end trench910C and the transverse trench983A can collectively be referred to as a perimeter trench that has a transverse portion.

In this implementation, at least a portion of the end trench910C is coupled to (e.g., overlaps with) trench910G, which is the outermost of the interior trenches917. The end trench910C and the trench910G are coupled along the longitudinal axis D1. Accordingly, a mesa region between end trench910C and trench910G is excluded from the semiconductor device900. In other words, end trench910C and trench910G are combined to form a single trench structure.

FIG. 11Bis a side cross-sectional view cut along line Q8 (shown inFIG. 11A) through the main trench portions912orthogonal to the plurality of trenches910. In this implementation, the gate runner conductor952is disposed above the plurality of trenches910, and the line Q8 intersects along a relatively shallow portion of the interior trenches917from the plurality of trenches910. Both end trench910L and910C (i.e., end trenches913) include a dielectric without a shield electrode, while the remainder of the plurality of trenches910(which includes the interior trenches917) along this cutline Q8 each include a shield electrode. Also, the depth R12 of end trenches910L,910C is greater than a depth of the remainder of the trenches (e.g., non-end trenches, interior trenches917), which include shield electrodes.

As shown inFIG. 11B, the end trench910C is coupled to the trench910G. In other words, a profile of the end trench910C intersects with or overlaps a profile of the active trench910G. The trench910G has a depth R23 that is shallower than the depth R12 of the end trench910C. Also, the trench910G includes a shield electrode (along the cross-sectional centerline of the trench910G) while the end trench910C does not include a shield electrode (e.g., excludes a shield electrode, includes a dielectric along the cross-sectional centerline of the trench910C). In some implementations, the end trench910C can include a shield electrode (e.g., a recessed electrode, electrically floating shield electrode, etc.). In some implementations, the trench910G can be filled with a dielectric (along the cross-sectional centerline of the trench910G) such that the shield electrode is excluded from at least this cross-sectional view of the trench910G.

The single trench structure defined by end trench910C and trench910G can have two recesses or trench bottoms (or dimples) where the depth of one of the trenches from the single trench structure is greater than a depth of the other trench (or adjacent or coupled trench) from the single trench structure. In the implementation shown inFIG. 11Bthe depth of trench910C is greater than trenches910G &910K. Although not shown, in some implementations, the depth of trench910G can be greater than trench910C, the depth of trench910G can be great than trench910K, or the depth of trench910G can be great than both trenches910K &910C. Because the two trench structures overlap, the combined trenches (e.g., trench910G and end trench910C) can define a point911(or apex). The overlapping of trenches such as trenches910G and910C can be included in any of the embodiments described herein such as those associated withFIGS. 3A through 7J, 9A through 10O, and/or12A through17J.

As shown inFIG. 11B, the mesa regions between the interior trenches917include well dopant regions. In this implementation, the mesa region960G (and the well dopant region962G) can be a grounded or electrically floating mesa region. In some implementations, the mesa region960G (and the well dopant region962G) can be coupled to a source potential. In some implementations, a mesa region between one or more end trenches such as the end trenches913and/or a mesa region between transition region trenches such as the transition region trenches915can be electrically floating or grounded. In some implementations, the mesa region between the one or more end trenches and/or the mesa region between transition region trenches can be coupled to a source potential. Also, in some implementations, a mesa region disposed between the transition region trenches915and the end trenches913can be electrically floating or grounded. In some implementations, the mesa region disposed between the transition region trenches915and the end trenches913can be coupled to a source potential.

In this implementation, the width of each of the end trenches913is greater than the width of the interior trenches917. For example, as shown inFIG. 11Bthe end trench910L in the main trench portion has a width R26 that is greater than the width R8 of the main trench portion of trench910E. Also, as shown inFIG. 11B, a width R27 of the combination of the end trench910C and the trench910G is greater than the width R26 of the end trench910L. Although not shown, in some implementations, the end trench910C and/or the trench910G can have a width that is defined so that the width R27 of the combination of the end trench910C and the trench910G is equal to or less than the width R26 of the end trench910L. In other implementations the width of trench910G can be greater than or less than trench910K.

FIG. 11Cis a side cross-sectional view cut along line Q9 (shown inFIG. 11A) through the main trench portions912orthogonal to the plurality of trenches910between the gate runner conductor952and the source runner conductor954. Different types of interior trenches917from the plurality of trenches910are included in this view. The end trenches913include a dielectric without a shield electrode, while the remainder of the plurality of trenches910along this cutline Q9 each include at least a shield electrode. Specifically, both trench910G and910K, which can be referred to as transition region trenches915(which are included in the interior trenches917), include a shield electrode that is grounded and each does not include a gate electrode. The remaining trenches (excluding the end trenches913and the transition region trenches915) each includes a gate electrode as well as a shield electrode. Because many of the features described above with respect to cut line Q9 apply in this implementation, they will not be described again here.

FIG. 11Dis a side cross-sectional view of the main trench portions912of the plurality of trenches910cut along line Q10 shown inFIG. 11Athrough the termination region904and into the active region902. A portion of the cross-sectional view of the plurality of trenches910is included in the termination region904and a portion of the cross-sectional view of the plurality of trenches910is included in the active region902. Because many of the features described above with respect to cut line Q10 apply in this implementation, they will not be described again here.

FIG. 11Eis a side cross-sectional view of a variation ofFIG. 11Dthat includes a recessed shield electrode in trench910G. Such recessed shield electrodes can be included in one or more of the trenches (e.g., trench910G,910K,910I, and/or so forth illustrated in, for example,FIGS. 11B through 11D). Although not shown inFIG. 11E, in some implementations, one or more of trench910G and910K can be active trenches (which include a gate electrode and a shield electrode).

FIGS. 12A through 12Lare diagrams that illustrate variations on at least some of the features of the semiconductor device900described above. Accordingly, the reference numerals and features described above in connection with semiconductor device900are generally maintained and some features are not described again in connection withFIGS. 12A through 12L. The perimeter trench910L (shown inFIGS. 10A through 11E), although excluded in the implementations shown inFIGS. 12A through 12L, can be optionally included.

As shown inFIGS. 12A through 12L, the end trench910C is coupled to the transverse trench983A. In some implementations, the end trench910C and the transverse trench983A can collectively be referred to as a perimeter trench that has a transverse portion. In some implementations, the end trench910C and/or the transverse trench983A can be produced using the same etching process, or multiple separate etching processes.

FIG. 12Bis a diagram that illustrates a side cross-sectional view of the semiconductor device900cut along line Q1. The trench910A includes the dielectric970A disposed therein. As shown inFIG. 12B, the gate electrode920A and the shield electrode930A are disposed in the trench910A, and are separated by (e.g., insulated by) at least a portion of the inter-electrode dielectric940. In this implementation, a shield electrode989A is disposed within the transverse trench983A. InFIG. 12B, the shield electrode930A has approximately a constant thickness. In some implementations, the shield electrode930A can have a thickness that varies along longitudinal axis D1.

The dielectric portion976A disposed within the transverse trench983A has a bottom thickness R31 that is approximately equal to the thickness R2 of the dielectric970A included in the trench910A. The thickness R31 is measured along a centerline of the transverse trench983A and is measured between a bottom surface of the shield electrode989A disposed within the transverse trench983A and a bottom surface of the transverse trench983A. In some implementations, the thickness R31 can be different than (e.g., greater than, less than) the thickness R2.

The dielectric portion976A of the transverse trench983A is coupled to the dielectric970A included in the trench910A. The dielectric portion976A and the dielectric970A can be formed using one or more different dielectric formation processes (e.g., a thermal dielectric formation process, a deposition process). Accordingly, the dielectric portion976A and the dielectric970A can be different dielectrics.

FIG. 12Cis a side cross-sectional view of the mesa region960A cut along line Q2. In this cross-sectional view, the well dopant region962A extends below the source runner954and below the gate runner conductor952. In this implementation, the well dopant region962A contacts the dielectric portion976A included in the transverse trench983A. In some implementations, the edge964A of the well dopant region962A is separated (by a gap (e.g., a semiconductor region)) from the transverse trench983A similar to that shown in, for example,FIG. 10N. In this implementation, for desirable charge balancing, the separation (which can be referred to as a lateral balance length) is equal to or greater than depth R3 (shown inFIGS. 12B, 12D, 12E, &12G).

Similar structures and features are illustrated in the cross-sectional view of the mesa region960G cut along line Q3 as illustrated inFIG. 12F. InFIG. 12F, the mesa region960G is entirely disposed within the termination region904. In some implementations, the edge964G of the well dopant region962G is separated (by a gap (e.g., a semiconductor region)) from the transverse trench983A similar to that shown in, for example,FIG. 10N.

FIG. 12Dis a side cross-sectional view of a variation of the trench910A of the semiconductor device900cut along line Q1. In this implementation, the shield electrode930A and the gate electrode920A have a configuration similar to that shown inFIG. 10B. In addition to the features described in connection withFIG. 10B, this cross-sectional view illustrates that the gate electrode920A can optionally have a constant thickness without a recessed portion. The portion933A of the shield electrode930A has a vertical height (or top surface) within the trench910A higher than a top surface of the portion931A of the shield electrode930A, which is recessed within the trench910A. The portion933A of the shield electrode930A also has a thickness (e.g., vertical thickness) within the trench910A greater than a thickness of the portion931A of the shield electrode930A. The portion933A extends vertically along a profile (e.g., a sidewall profile) of the transverse trench983A (illustrated with a dashed line). The portion933A of the shield electrode930A has a portion is disposed between an edge of the gate electrode920A (and the gate dielectric portion942) and the transverse trench983A.

FIG. 12Eis a side cross-sectional view of another variation of the trench910A of the semiconductor device900cut along line Q1. In this implementation, the shield electrode930A and the gate electrode920A have a configuration similar to that shown inFIG. 12B. In addition to the features described in connection with, for example,FIG. 10BandFIG. 12B, this cross-sectional view illustrates that the shield electrode989A can optionally be a recessed shield electrode (or a non-recessed electrode (not shown)). As shown inFIG. 12E, the gate electrode920A has an edge that intersects (e.g., contacts, overlaps) the transverse trench983A. Also, the shield electrode930A has an edge that intersects (e.g., contacts, overlaps) the transverse trench983A. The edge of the gate electrode920A is aligned vertically with the edge of the shield electrode930A, and the edge of the gate electrode920A and the edge of the shield electrode930A are aligned vertically with a sidewall (e.g., a sidewall profile shown with a dashed line) of the transverse trench983A.

FIG. 12Gis a side cross-sectional view of another variation of trench910G of the semiconductor device900cut along line Q4. In this implementation, the shield electrode930A has a configuration similar to that shown inFIG. 10H. In addition to the features described in connection with, for example,FIG. 10H, this cross-sectional view illustrates that the shield electrode989A can optionally be a recessed shield electrode (or a non-recessed electrode (not shown)).

FIG. 12His a side cross-sectional view of another variation of trench910G of the semiconductor device900cut along line Q4. In this implementation, the shield electrode930G has a recessed portion936G and a non-recessed portion937G. the recessed portion936G of the shield electrode930G has a thickness R33 that is less than a thickness R34 of the non-recessed portion937G of the shield electrode930G. As shown inFIG. 12H, the field dielectric974as a portion with a thickness above (e.g., between the recessed portion936G and the ILD992) the recessed portion936G of the shield electrode930G that is greater than a thickness of the field dielectric974above the non-recessed portion937G of the shield electrode930G (e.g., between the non-recessed portion937G and the ILD992).

Shown inFIG. 12H, a top surface of the recessed portion936G can be aligned (e.g., horizontally aligned) approximately with a top surface of the shield electrode989A (which is illustrated by a dashed line). However, a bottom surface of the shield electrode989A can be deeper than a bottom surface of the portion936G of the shield electrode930G. In some implementations, the bottom surface of the shield electrode989A can be approximately the same as, or less than, the bottom surface of the portion936G of the shield electrode930G. In some implementations, the top surface of the recessed portion936G may not be aligned with the top surface of the shield electrode989A. In some implementations, the shield electrode989A can optionally be a non-recessed electrode (not shown).

In some implementations, a length R35 of the recessed portion936G of the shield electrode930G (below and corresponding with dielectric portion974G, which can be referred to as a protrusion dielectric) can be disposed within the termination region904. In this implementation, the length R35 of the recessed portion936G of the shield electrode930G has at least a first portion that is disposed below (e.g., vertically disposed below) the gate runner conductor952and a second portion that is disposed below (e.g., is vertically disposed below) the source runner conductor954. In some implementation, the length R35 of the recessed portion936G of the shield electrode930G has at least a first portion that is disposed below (e.g., vertically disposed below) the gate runner conductor952and does not have a second portion that is disposed below (e.g., is vertically disposed below) the source runner conductor954. In some implementations, the recessed portion936G can terminate below the gate runner conductor952. In some implementations, the length R35 of the recessed portion936G of the shield electrode930G can extend into the active region902. Accordingly, in some implementations, at least a portion of the recessed portion936G of the shield electrode930G can be disposed within the termination region904, and a portion of the recessed portion936G of the shield electrode930G can be disposed within the active region902. In some implementations, the shield electrode930G can be recessed along a relatively large portion of (or nearly an entirety of) the trench910G as shown inFIG. 12L.

FIG. 12Iis a side cross-sectional view of the end trench910C, which is cut along line Q6 shown inFIG. 12A. The end trench910C has a shield electrode930C and dielectric970C disposed therein. The end trench910C can have a length (along the longitudinal direction D1) that is approximately the same as a length of, for example, the trench910C. In this implementation, the dielectric910C has a thickness R37 along an end surface (e.g., a vertical end surface) of the trench970C that is approximately equal to the thickness R31 along the bottom surface of the trench. In some implementations, the thickness R37 and the thickness R31 can be approximately the same as the thickness R2 shown in, for example,FIG. 12B. In some implementations, the thickness R37 and/or the thickness R31 can be different than (e.g., greater than, less than) the thickness R2 shown in, for example,FIG. 12B.

Although not shown inFIG. 12I, in some implementations, the shield electrode930C (or a portion thereof) can be recessed within the trench910C. In such implementations, the thickness of the shield electrode930C can be less than that shown inFIG. 12I. In some implementations, the shield electrode930C can be electrically floating, or can be coupled to a source potential via the source runner conductor954. Because the features (and options) of the transverse trench983A, are nearly identical to those of the end trench910C, a cross-sectional view of the transverse trench983A cut along line Q7 is not shown.

FIG. 12Jis a side cross-sectional view cut along line Q9 (shown inFIG. 12A) orthogonal to the plurality of trenches910between the gate runner conductor952and the source runner conductor954. Different types of interior trenches917from the plurality of trenches910are included in this view. The end trench910C include a shield electrode930C (along a vertical centerline), and the remainder of the plurality of trenches910along this cutline Q9 each include at least a shield electrode.

FIG. 12Kis a diagram that illustrates a variation of the portion of the semiconductor device900shown inFIG. 12E. As shown inFIG. 12K, the semiconductor device900includes a dielectric portion974A (similar to the portions (e.g., protrusion dielectrics) described in connection with, for example,FIGS. 9 and 10). The dielectric portion974A is coupled to the dielectric portion976A included in the transverse trench983A. In some implementations, the

FIG. 10Nillustrates another variation on the semiconductor device900. As shown inFIG. 10N, an edge964G of the well dopant region962A is separated from the transverse trench983A (e.g., a sidewall of the transverse trench983A) by a gap having a length R24. The length R24 can be less than or equal to length R25 (shown inFIG. 10M or 10O), or greater than length R25. The length R24 can be less than or equal to length R29 (shown inFIG. 10Efrom the transverse trench983A to an edge of the gate electrode920A, or greater than length R29. The length R29 is also shown in other figures such asFIG. 10F.

FIGS. 13A through 13Lare diagrams that illustrate variations on at least some of the features of the semiconductor device900shown inFIGS. 9A through 9N. Accordingly, the reference numerals and features included inFIGS. 9A through 9Nare generally maintained and some features are not described again in connection withFIGS. 13A through 13L.

As shown inFIGS. 13A through 13L, capacitance reduction trenches998(which include capacitance reduction trenches998A through998E) are disposed below the gate runner conductor952. Also as shown in at leastFIG. 13A, surface gate contacts953are disposed between the capacitance reduction trenches998and the gate runner conductor952. In this implementation, a surface gate electrode922is included in the semiconductor device900. A well implant (which is defined by the doping region938A) is at least partially blocked by the surface gate electrode992. In some implementations, at least a portion of the surface electrode922can be recessed low a mesa region. In other implementations the oxide filled trenches are disposed under surface gate poly in the device gate pad (not shown).

FIG. 13Bis a diagram that illustrates a side cross-sectional view of the semiconductor device900cut along line Q1. As shown inFIG. 13B, the capacitance reduction trenches998each have a depth that is approximately equal to the depth R1 of the perimeter trench910L and/or the transverse trench983A. Each of the capacitance reduction trenches998also has a width that is approximately equal to the width R19 of the perimeter trench910L (and the transverse trench983A). In some implementations, one or more of the capacitance reduction trenches998can be formed using the same process that is used to form the perimeter trench910L and/or the transverse trench983A.

In some implementations, one or more of the capacitance reduction trenches998can have a depth and/or a width different than the perimeter trench910L and/or the transverse trench983A. For example, one or more of the capacitance reduction trenches998can have a depth and or a width similar to the perimeter trenches990A and/or990B. In some embodiments, one or more of the capacitance reduction trenches998can include a shield electrode (not shown).

An example of one or more of the capacitance reduction trenches998shown inFIG. 13Bincluding shield electrodes997are shown inFIG. 13K. In some implementations, less than all of the capacitance reduction trenches998can include a shield electrode997. In this implementation, the shield electrodes997are recessed within the capacitance reduction trenches998. In some implementations, the shield electrodes997may not be recessed within the capacitance reduction trenches998. One or more shield electrodes997can be included in one or more of the capacitance reduction trenches998shown in, for example,FIGS. 13C, 13D, 13E, and/or13F, A cross-sectional view of the shield electrode997along capacitance reduction trench998E (cut Q6) is shown inFIG. 13L.

Referring back toFIG. 13B, a surface gate electrode922is disposed between the inter-electrode dielectric992and the capacitance reduction trenches998. At least a portion of the epitaxial layer908is insulated from the surface gate electrode922by the field dielectric974. At least a portion of the field dielectric974is disposed between the surface gate electrode922and one or more of the capacitance reduction trenches998.

Because the capacitance reduction trenches998are disposed between the gate runner conductor953and a drain (not shown), the capacitance reduction trenches998can reduce a gate to drain capacitance. In some implementations, one or more capacitance reduction trenches similar to the capacitance reduction trenches998can be formed below, for example, a gate pad (not shown).

FIG. 13Cis a side cross-sectional view of the mesa region960A cut along line Q2. In this cross-sectional view, the well dopant region962A extends below the source runner conductor954. In this implementation, the well dopant region962A contacts the dielectric portion976A included in the transverse trench983A. In accordance with prior examples, an area where the well dopant region962A could be expanded is illustrated with line961.

As shown inFIG. 13C, well dopant region962A is separated from, for example, the transverse trench983A by at least a portion of the epitaxial layer908. In some implementations, a distance between the well dopant region962A and the transverse trench983A can be less than shown inFIG. 13C, or greater than shown inFIG. 13C.

Similar structures and features (as included inFIG. 13C) are illustrated in the cross-sectional view of the mesa region960G cut along line Q3 (shown inFIG. 13D). InFIG. 13D, the mesa region960G is entirely disposed within the termination region904.

FIG. 13Eis a side cross-sectional view of the trench910G, which is cut along line Q4 shown inFIG. 13A. In this implementation, the trench910G is entirely disposed within the termination region904. As shown inFIG. 13E, the shield electrode930G has a thickness that extends from the dielectric970G along a bottom of the trench910G to the field oxide974. In some implementations, the field oxide974can be aligned along plane D4. In some implementations, the shield electrode930G disposed within the trench910G can be recessed.

FIG. 13Fis a side cross-sectional view cut along line Q5 shown inFIG. 13A. At least a portion of this cross-sectional view intersects the capacitance reduction trenches, the perimeter trench910L, and the transverse trench983A. Also, at least a portion of this cross-sectional view is a long trench910C, which is a dielectric filled trench.

FIG. 13His a side cross-sectional view cut along line Q6 shown inFIG. 13A. This cross-sectional view is aligned along capacitance reduction trench998E. As shown inFIG. 13G, the capacitance reduction trench998E has an end959that extends in a horizontal direction up to or nearly to an edge958of the gate runner conductor952(which is vertically above the end959). Accordingly, the end959of the capacitance reduction trench998E can be disposed below (e.g., vertically below) at least a portion of the gate runner conductor952. In some embodiments, the end959of the capacitance reduction trench998E can extend beyond the edge958of the gate runner conductor952such that the end959of the capacitance reduction trench998E is not vertically disposed below an area of the gate runner conductor952when view from above. Similarly, the end959of the capacitance reduction trench998E can be disposed below, or can extend beyond an area defined by surface gate electrode922when viewed from above.

FIG. 13His a side cross-sectional view cut along line Q7 shown inFIG. 13A. This cross-sectional view is intersects perimeter trench910L and is aligned along transverse trench983A. As shown inFIG. 13H, both the perimeter trench910L and the transverse trench983A are disposed below the surface gate electrode922.

FIG. 13Iis a side cross-sectional view cut along line Q8 (shown inFIG. 13A) orthogonal to the plurality of trenches910. In this implementation, the mesa regions between the interior trenches do not include a well dopant. In this implementation, the surface gate electrode922is disposed above the plurality of trenches910, and the line Q8 intersects along a relatively shallow portion of the interior trenches917from the plurality of trenches910. Both end trench910L and910C (i.e., end trenches913) include a dielectric without a shield electrode, while the remainder of the plurality of trenches910(which includes the interior trenches917) along this cutline Q8 each include a shield electrode. Also, the depth R12 of end trenches910L,910C is greater than a depth of the remainder of the trenches (e.g., non-end trenches, interior trenches917), which include shield electrodes.

FIG. 13Jis a side cross-sectional view of the plurality of trenches910cut along line Q9 shown inFIG. 13Athrough the termination region904and into the active region902. A portion of the cross-sectional view of the plurality of trenches910is included in the termination region904and a portion of the cross-sectional view of the plurality of trenches910is included in the active region902. Because many of the features described above with respect to cut line Q9 apply in this implementation, many elements will not be described again here.

As shown inFIG. 13J, the well dopant region962G is contacted to the source runner conductor954using a source contact957G. Accordingly, the outermost trench (closest to the perimeter trenches990A,990B) from the interior trenches917is in contact with well dopant region962G, which is contacted to the source runner conductor954through the source contact957G. In this implementation, the outermost trench from the interior trenches917is trench910G, which is coupled to end trench910C. In some embodiments, the outermost trench from the interior trenches917(which can be adjacent to a well dopant region that is electrically coupled to a source) can be a standalone trench that is not coupled to an end trench.

FIGS. 14A through 14Kare side cross-sectional diagrams that illustrate a method for making one or more features of a semiconductor device1400. The semiconductor device1400can be similar to the semiconductor devices described above. In some implementations, the method illustrated byFIGS. 14A through 14Kcan be referred to as a single hard mask process because a hard mask is used to form at least a portion of a trench in a termination region. The trenches illustrated in the side cross-sectional diagrams can be aligned along a longitudinal axis (e.g., longitudinal axis D1) and can be included in a set of parallel trenches (e.g., the plurality of trenches310shown inFIG. 3A).

As shown inFIG. 14A, a first mask1403is formed on an epitaxial layer1408of a semiconductor substrate (not shown). The epitaxial layer1408can be formed within or on top of the semiconductor substrate. Also, as shown inFIG. 14A, a second mask1404is formed over at least a portion of the first mask1403. In some embodiments, the first mask1403can be a hard mask (e.g., an oxide-based mask) (rather than a polymeric or other organic material that can be a soft mask).FIG. 14Aillustrates a portion1411of a trench1410(shown inFIG. 14B) formed in the epitaxial layer1408using an etching process. In some embodiments, the portion1411of the trench1410can be associated with a transverse trench (e.g., transverse trench380A shown inFIG. 3A, transverse trench383A shown inFIG. 7A), a perimeter trench (e.g., perimeter trench390A shown inFIG. 3A, perimeter trench910L shown inFIG. 9A), a trench extension portion (e.g., trench extension portion314A shown inFIG. 3A), and/or so forth.

After the portion1411of the trench1410has been formed, the second mask1404is removed, leaving the first mask1403. After the second mask1404is removed to expose region1407(shown inFIG. 14A), etching of the portion1411and the exposed region1407is commenced to form the trench1410shown inFIG. 14B. As shown inFIG. 14B, the trench1410has a first portion1414that has a depth M1 that is deeper than a depth M2 of a second portion1412. In some embodiments, the first portion1414can correspond with a trench extension portion (e.g., trench extension portion314A shown inFIG. 3A) and the second portion1412can correspond with a main trench portion (e.g., main trench portion312A shown inFIG. 3A). In this implementation, etching after the second mask1404is removed results in a portion1402of the first mask1403being decoupled from the epitaxial layer1408and being removed.

In some embodiments, the first portion1414, when viewed from above or in a vertical cross-section, can have a width that is narrower than a width of the second portion1410, when viewed from above or in a vertical cross-section. In some embodiments, the first portion1414, when viewed from above, can have a width that is approximately equal to, or greater than, a width of the second portion1410, when viewed from above. In some implementations, the trench1410can be formed so that the depth M1 of the first portion1414is shallower than, or equal to, the depth M2 of the second portion1412.

Although not shown, in some implementations, the processing steps described herein can be modified such that a transverse trench can be formed within and in a perpendicular direction to at least a portion of the trench1410. In some implementations, the transverse trench can be formed using the same process used to form the portion1414of the trench1410.

FIG. 14Cillustrates formation of a dielectric1471within the trench1410. As shown inFIG. 14C, the first mask1403is removed before the dielectric1471is formed within the trench1410. In some embodiments, the dielectric1471can be formed using one or more different dielectric formation processes. For example, a first portion of the dielectric1471, which can be an oxide, can be formed using a thermal growth process, and a second portion of the dielectric1471can be formed using a deposition process (e.g., a sub-atmospheric chemical vapor deposition (SACVD) process).

In this embodiment, because the first portion1414is narrower than the second portion1412, the dielectric1471can fill the first portion1414of the trench1410while lining a sidewall and a bottom surface of the second portion1412of the trench1410. In other words, the dielectric1471can entirely fill the first portion1414without entirely filling the second portion1412. In some implementations, the first portion1414can have a width (when viewed from above or in a vertical cross-section) defined so that the dielectric1471lines the first portion1414of the trench1410without filling the first portion1414of the trench1410.

As shown inFIG. 14C, an edge1472of the dielectric1471is offset (e.g., laterally offset) from an edge1413of the first portion1414of the trench1410. In some embodiments, the offset can be a distance M1 that is equal to (e.g., approximately equal to) a thickness M2 of a portion of the dielectric1471included in the second portion1412of the trench1410.

FIG. 14Dillustrates formation of a shield electrode1430in the trench1410. In some embodiments, the shield electrode1430can be formed on (e.g., disposed on) the dielectric1471in the trench1410using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process). In some embodiments, if the dielectric1471lines the first portion1414of the trench1410rather than filling the first portion1414of the trench1410, the shield electrode1430can also be formed in the first portion1414of the trench1410.

After the shield electrode1430has been formed within the trench1410, a portion of the shield electrode1430can be removed as shown inFIG. 14E. Specifically, a chemical mechanical polish (CMP) process can be applied to the shield electrode1430to remove a portion of the shield electrode1430. After the CMP process has been performed, a portion of the shield electrode1430can be etched to recess the shield electrode1430within the trench1410. As shown inFIG. 14E, a top surface1431of the shield electrode1430is below a top surface1474of the dielectric1471. Although not shown, in some implementations a surface shield electrode can also be formed.

As shown inFIG. 14F, the shield electrode1430is further recessed within the trench1410. The shield electrode1430can be recessed using, for example, an etch process. The shield electrode1430can be recessed to have a profile similar to that shown in, for example,FIG. 9BorFIG. 10B. In some implementations, the shield electrode1430can be recessed to have a profile similar to that shown inFIG. 10Bor the profile shown inFIG. 12H.

A dielectric1476is formed as shown inFIG. 14Gafter a profile of the shield electrode1430has been formed. The dielectric1476is formed at least on a portion of the dielectric1471. In some embodiments, the dielectric1476can be used to form an inter-electrode dielectric1440shown inFIG. 14H. In some embodiments, the dielectric1476can be formed using a deposition process (e.g., an SACVD process), a thermal formation process, and/or so forth. In some embodiments, the dielectric1476can include a borosilicate glass (BSG). In some implementations, one or more of the dielectric1471and the dielectric1476can define a field dielectric (e.g., field dielectric374shown inFIG. 3B). Although not shown, a gate dielectric can also be formed after the inter-electrode dielectric1440has been formed.

As shown inFIG. 14H, the inter-electrode dielectric1440can be defined and recessed using any combination of a CMP process or an etch process. As shown inFIG. 14H, the inter-electrode dielectric1440is recessed within the second portion1412of the trench1410.

After a profile of the inter-electrode dielectric1440has been formed as shown inFIG. 14H, a gate electrode1420can be formed as shown inFIG. 14I. In some embodiments, the gate electrode1420can be formed on (e.g., disposed on) the inter-electrode dielectric1440in the trench1410using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process).

The gate electrode1420is recessed to form the gate electrode1420profile shown inFIG. 14J. In this implementation, a surface gate electrode1422and a channel stopper1494are formed. In some implementations, the processing associated with the gate electrode1420, the inter-electrode dielectric1440, and/or the shield electrode1430can be modified to define a different set of profiles (e.g., the profiles shown inFIG. 12B).

As shown inFIG. 14K, an interlayer dielectric1492is formed. In some embodiments, the interlayer dielectric1492can be, for example, a borophosphosilicate glass (BPSG) layer. A gate runner conductor1452and a source runner conductor1454are shown inFIG. 14K. Vias to the gate runner conductor1452and the source runner conductor1454can be formed.

FIGS. 15A through 15Oare side cross-sectional diagrams that illustrate another method for making one or more features of a semiconductor device1500. The semiconductor device1500can be similar to the semiconductor devices described above. In some implementation, the method illustrated byFIGS. 15A through 15Ocan be referred to as double trench termination process because a first trench is formed, and a second trench that is self-aligned with the first trench is later form. The trenches illustrated in the side cross-sectional diagrams can be aligned along a longitudinal axis (e.g., longitudinal axis D1) and can be included in a set of parallel trenches (e.g., the plurality of trenches310shown inFIG. 3A).

As shown inFIG. 15A, a mask1503is formed on an epitaxial layer1508of a semiconductor substrate (not shown). The epitaxial layer1508can be formed within or on top of the semiconductor substrate. In some embodiments, the mask1503can be a hard mask.FIG. 15Aillustrates termination trenches1511(which includes trenches1511A through1511C) formed in the epitaxial layer1508using an etching process through the mask1503. In some embodiments, one or more of the termination trenches1511can be a transverse trench (e.g., transverse trench380A shown inFIG. 3A, transverse trench383A shown inFIG. 7A), a perimeter trench (e.g., perimeter trench390A shown inFIG. 3A, perimeter trench910L shown inFIG. 9A), a trench extension portion (e.g., trench extension portion314A shown inFIG. 3A), and/or so forth.

In this implementation, the termination trenches1511include three separate termination trenches. In some implementations, less than three termination trenches (e.g., a single termination trench, a pair of termination trenches) or a series of termination trenches (such as those shown inFIG. 13) can be formed. In some embodiments, the termination trench1511C can be referred to as a transverse trench.

After the termination trenches1511have been formed, the mask1503is removed, and a dielectric1579is formed within the termination trenches1511and on a surface1507of the epitaxial layer1508as shown inFIG. 15B. In this implementation, portions1578(including portions1578A through1578D) of the dielectric1579are formed within the termination trenches1511and a portion1577of the dielectric1579is formed on the surface1507of the epitaxial layer1508. In some implementations, the portions1578of the dielectric1579can be referred to as dielectric portions.

In some embodiments, the dielectric1579can be formed using one or more different dielectric formation processes. For example, a first portion of the dielectric1571, which can be an oxide, can be formed using a thermal growth process, and a second portion of the dielectric1571can be formed using a deposition process (e.g., a sub-atmospheric chemical vapor deposition (SACVD) process), or vice versa. In some implementations, the dielectric1579can include a borosilicate glass (BSG).

After the termination trenches1511have been filled with the dielectric portions1578of the dielectric1579, the portion1577of the dielectric1579disposed on the surface1507(e.g., a top surface) of the epitaxial layer1508, which is aligned along plane D4, is removed. Dielectric portions1578disposed within the termination trenches1511and substantially aligned along plane D4 remain within the termination trenches1511and top surfaces of the dielectric portions1578are exposed. For example, one of the dielectric portion1578A disposed within the termination trench1511A can have a top surface that is exposed when the portion1577is removed. In some implementations, portion1577can be removed using any combination of a wet etch, a dry etch, and/or a CMP process.

As shown inFIG. 15C, a mask1504(and portions thereof) is formed on at least a portion of a surface of the epitaxial layer1508. Shown inFIG. 15C, the mask1504has at least a portion disposed over the exposed top surfaces of the dielectric portions1578. Openings1509in the mask1504are formed (e.g., defined) so that perimeter trenches1590can be etched into the epitaxial layer1508. Also, a region1506of the epitaxial layer1508is exposed so that etching of trench1510(or a main portion1512of the trench1510) can be formed (e.g., etched).

As shown inFIG. 15D, perimeter trenches1590and the trench1510are formed in the epitaxial layer1508using the mask1504. In some embodiments, the trench1510can be referred to as an active trench, or can have a least a portion that is disposed within an active area of the semiconductor device1500. As shown inFIG. 15D, one or more of the perimeter trenches1590have a depth N1 that is approximately equal to a depth N2 of the trench1510.

In this embodiment, the etching of the trench1510is performed so that the trench1510can abut and be self-aligned with the termination trench1511C. As shown inFIG. 15Dan edge1501of the mask1504is offset from an edge1518of dielectric portion1578C disposed in termination trench1511C so that over etching can guarantee that the trench1510abuts the termination trench1511C even with some misalignment. In other words, less than all of a top surface of the dielectric portion1578C disposed in the termination trench1511C may be covered by the mask1504so that a portion of the top surface of the dielectric portion1578C is exposed to etching. In some embodiments, the portion of the top surface of the dielectric1578C that is exposed to etching can be aligned along (or contiguous with) the edge1518to be contacted with the trench1510.

Although not shown, in some implementations, the processing steps described herein can be modified such that a transverse trench can be etched within and in a perpendicular direction to at least a portion of the trench1510. In some implementations, the transverse trench can be formed using the same process used to form the termination trenches1511.

The mask1504(shown inFIG. 15D) is removed, as shown inFIG. 15E, using any combination of a wet etch, a dry etch, and/or a CMP process. After the mask1504has been removed, a dielectric1571is formed within the trench1510, over the termination trenches1511, and within the perimeter trenches1590. In some embodiments, the dielectric1571can be formed using one or more different dielectric formation processes. For example, a first portion of the dielectric1571, which can be an oxide, can be formed using a thermal growth process, and a second portion of the dielectric1571can be formed using a deposition process (e.g., a sub-atmospheric chemical vapor deposition (SACVD) process).

As shown inFIG. 15F, a thickness of a portion of the dielectric1571disposed along a bottom surface of one or more of the perimeter trenches1590can be the same as, or approximately the same as, a thickness of a portion of the dielectric1571disposed along a bottom surface of the trench1510.

After the formation of the dielectric1571, a combined width N3 of dielectric portion1578C included in termination trench1511C and width of a portion of the dielectric1571can be greater than that shown inFIG. 15Fand can be greater than a width of the dielectric portion1578C alone.

FIG. 15Gillustrates formation of a shield electrode1530in the trench1510. In some embodiments, the shield electrode1530can be formed on (e.g., disposed on) the dielectric1571in the trench1510and in the perimeter trenches1590using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process). In some embodiments, if one or more of the termination trenches1511are not entirely filled with the dielectric portions1578, at least a portion of the shield electrode1530can be included in one or more of the termination trenches1511.

After the shield electrode1530has been formed within the trench1510and in the perimeter trenches1590, one or more portions of the shield electrode1530can be removed as shown inFIG. 15H(to reduce a thickness of the shield electrode1530). Specifically, a chemical mechanical polish (CMP) process can be applied to the shield electrode1530to remove portions of the shield electrode1530. After the CMP process has been performed, portions of the shield electrode1530can be etched to recess the shield electrode1530within the trench1510. Although not shown, in some implementations, at least a portion of a surface shield electrode can also be formed.

As shown inFIG. 15I, the shield electrode1530is further recessed within the trench1510. In some implementations, the shield electrode1530within the perimeter trenches1590can also be further recessed. The shield electrode1530can be recessed using, for example, an etch process. The shield electrode1530can be recessed to have a profile similar to that shown in, for example,FIG. 9BorFIG. 10B. In some implementations, the shield electrode1530can be recessed to have a profile similar to that shown in, for example,FIG. 10O,FIG. 9L,FIG. 9Mand/orFIG. 12H.

A dielectric1576is formed as shown inFIG. 15Jafter a profile of the shield electrode1530has been formed. The dielectric1576is formed at least on a portion of the dielectric1571. In some embodiments, the dielectric1576can be used to form an inter-electrode dielectric1540shown inFIG. 15K. In some embodiments, the dielectric1576can be formed using a deposition process (e.g., an SACVD process), a thermal formation process, and/or so forth. In some embodiments, the dielectric1576can include a borosilicate glass (BSG). In some implementations, one or more of the dielectric1571and the dielectric1576can define a field dielectric (e.g., field dielectric374shown inFIG. 3B). Although not shown, a gate dielectric can also be formed after the inter-electrode dielectric1540has been formed.

As shown inFIG. 15K, the inter-electrode dielectric1540can be defined and recessed using any combination of a CMP process or an etch process. As shown inFIG. 15K, the inter-electrode dielectric1540is recessed within the second portion1512of the trench1510.

After a profile of the inter-electrode dielectric1540has been formed as shown inFIG. 15K, a gate electrode1520can be formed as shown inFIG. 15L. In some embodiments, the gate electrode1520can be formed on (e.g., disposed on) the inter-electrode dielectric1540in the trench1510using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process).

The gate electrode1520is recessed to form the gate electrode1520profile shown inFIG. 15M. In this implementation, a surface gate electrode1522and a channel stopper1594are formed. In some implementations, the processing associated with the gate electrode1520, the inter-electrode dielectric1540, and/or the shield electrode1530can be modified to define a different set of profiles (e.g., the profiles shown inFIG. 12B,FIG. 10O,FIG. 10F,FIG. 10E).

As shown inFIG. 15N, an interlayer dielectric1592is formed. In some embodiments, the interlayer dielectric1592can be, for example, a borophosphosilicate glass (BPSG) layer. A gate runner conductor1552and a source runner conductor1554are shown inFIG. 15N. Vias to the gate runner conductor1552and the source runner conductor1554can also be formed.

FIG. 15Oillustrates a variation of the semiconductor device1500that can be produced using the process illustrated inFIGS. 15A through 15N. In this variation, a single termination trench1511D (which can function as a transverse trench) is formed within the epitaxial layer1508. Also, as shown inFIG. 15O, a surface shield electrode1532is formed within the semiconductor device1500.

FIGS. 16A through 16Fare side cross-sectional diagrams that illustrate a variation of a method for making one or more features of the semiconductor device1500. Accordingly, the reference numerals and features included inFIGS. 15A through 15Oare generally maintained and some features are not described again in connection withFIGS. 16A through 16F. In this implementation, the process for producing the variation uses the same processing steps up throughFIG. 15J. Accordingly,FIG. 16Ain this implementation corresponds withFIG. 15J. The process variation described in connection withFIGS. 16A through 16Fcan correspond with at least some of the features for a semiconductor device that excludes a surface shield electrode and/or a surface gate electrode such as that shown in, for example,FIGS. 9B and 10B.

As shown inFIG. 16B, at least a portion of the dielectric1571and at least a portion of the dielectric1576are removed. The portion of the dielectric1571and portion of the dielectric1576are removed until a surface of the semiconductor device1500is substantially planar and within the plane D4 of the epitaxial layer1508. In some implementations, the semiconductor device1500can be referred to as being planarized.

As shown inFIG. 16B, several of the elements that were previously covered by, for example, the dielectric1571can be exposed. For example, dielectric included in the perimeter trenches1590can be exposed, one or more of the dielectric portions1578can have top surfaces that are exposed, shield electrodes disposed within the perimeter trenches1590can be exposed, a top surface of the shield electrode1530can be exposed, and/or so forth.

As shown inFIG. 16C, an inter-electrode dielectric1540is defined from the dielectric1576. The inter-electrode dielectric1540can have a profile that is defined using any combination of a CMP process or an etch process. As shown inFIG. 16C, the inter-electrode dielectric1540is recessed within the second portion1512of the trench1510.

After a profile of the inter-electrode dielectric1540has been formed as shown inFIG. 16C, a gate dielectric1575can be formed and a gate electrode1520can be formed on the gate dielectric1575as shown inFIG. 16D. In some embodiments, the gate electrode1520can be formed on (e.g., disposed on) the inter-electrode dielectric1540in the trench1510and on the gate dielectric1575using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process).

The gate electrode1520is recessed using one or more masking and/or recessing steps (e.g., etching steps) to form a profile of the gate electrode1520shown inFIG. 16E. As shown inFIG. 16E, the gate electrode1520has two different recessed portions—a recessed portion1523and a recessed portion1522. Accordingly, the recessed portion1523of the gate electrode1520has a thickness that is less than the recessed portion1522of the gate electrode1520. The profile can be similar to the profile of the gate electrode shown in, for example,FIGS. 10E and 10F. In some implementations, the gate electrode1520can be modified with a different profile such as that shown inFIG. 12B,FIG. 10B, and/orFIG. 10D. In some implementations, the gate electrode1520can be recessed so that the gate electrode1520has a substantially constant thickness across longitudinal length.

As shown inFIG. 16F, an interlayer dielectric1592is formed. In some embodiments, the interlayer dielectric1592can be, for example, a borophosphosilicate glass (BPSG) layer. A gate runner conductor1552and a source runner conductor1554are also formed and shown inFIG. 16F. A via1551to the gate runner conductor1552and a via (not shown) the source runner conductor1554can also be formed.

FIGS. 17A through 17Lare side cross-sectional diagrams that illustrate yet another method for making one or more features of a semiconductor device1700. The semiconductor device1700can be similar to the semiconductor devices described above. In some implementation, the method illustrated byFIGS. 17A through 17Lcan be referred to as “later dielectric fill” process because a dielectric associated with a termination region of a trench is formed after a shield electrode has been formed within the trench. The trenches illustrated in the side cross-sectional diagrams can be aligned along a longitudinal axis (e.g., longitudinal axis D1) and can be included in a set of parallel trenches (e.g., the plurality of trenches310shown inFIG. 3A).

As shown inFIG. 17A, a mask1703is formed on an epitaxial layer1708of a semiconductor substrate (not shown). The epitaxial layer1708can be formed within, or on top of, the semiconductor substrate. In some embodiments, the mask1703can be a hard mask. Openings1709in the mask1703are formed (e.g., defined) so that perimeter trenches1790can be etched into the epitaxial layer1708. Also, a region1706of the epitaxial layer1708is exposed so that etching of trench1710(or a main portion1712of the trench1710) can be formed (e.g., etched).

As shown inFIG. 17B, perimeter trenches1790and the trench1710are formed in the epitaxial layer1708using the mask1703. In some embodiments, the trench1710can be referred to as an active trench, or can have a least a portion that is disposed within an active area of the semiconductor device1700. As shown inFIG. 17B, one or more of the perimeter trenches1790have a depth O1 that is approximately equal to a depth O2 of the trench1710.

The mask1703(shown inFIG. 17B) is removed using any combination of a wet etch, a dry etch, and/or a CMP process. After the mask1703has been removed, a dielectric1771is formed within the trench1710, and within the perimeter trenches1790as shown inFIG. 17C. In some embodiments, the dielectric1771can be formed using one or more different dielectric formation processes. For example, a first portion of the dielectric1771, which can be an oxide, can be formed using a thermal growth process, and a second portion of the dielectric1771can be formed using a deposition process (e.g., a sub-atmospheric chemical vapor deposition (SACVD) process).

As shown inFIG. 17C, a thickness of a portion of the dielectric1771disposed along a bottom surface of one or more of the perimeter trenches1790can be the same as, or approximately the same as, a thickness of a portion of the dielectric1771disposed along a bottom surface of the trench1710. Although not shown, in some implementations, the processing steps described herein can be modified such that a transverse trench can be formed within and in a perpendicular direction to at least a portion of the trench1710.

FIG. 17Dillustrates formation of a shield electrode1730in the trench1710. In some embodiments, the shield electrode1730can be formed on (e.g., disposed on) the dielectric1771in the trench1710and in the perimeter trenches1790using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process).

After the shield electrode1730has been formed within the trench1710and in the perimeter trenches1790, one or more portions of the shield electrode1730can be removed as shown inFIG. 17E(to reduce a thickness of the shield electrode1730). Specifically, a chemical mechanical polish (CMP) process can be applied to the shield electrode1730to remove portions of the shield electrode1730. After the CMP process has been performed, portions of the shield electrode1730can be etched to recess the shield electrode1730within the trench1710. Although not shown, in some implementations, at least a portion of a surface shield electrode can also be formed.

As shown inFIG. 17F, the shield electrode1730is further recessed within the trench1710. In some implementations, the shield electrode1730within the perimeter trenches1790can also be further recessed. The shield electrode1730can be recessed using, for example, an etch process. The shield electrode1730can be recessed to have a profile similar to that shown in, for example,FIG. 9BorFIG. 10B. In some implementations, the shield electrode1730can be recessed to have a profile similar to that shown inFIG. 10Bor the profile shown inFIG. 12H.

As shown inFIG. 17G, a portion of the shield electrode1730is removed from a portion1714of the trench1710. Accordingly, an end1731(e.g., an end wall, and an surface) of the shield electrode1730is exposed, and a cavity1734is defined. The cavity1734is defined by at least a portion of the end1731, and a surface of the dielectric1771along one or more sidewalls and bottom surface of the trench1710.

In some embodiments, the portion1714of the trench1710can correspond with a trench extension portion of the trench1710. In some implementations, the portion1712of the trench1710can have a cross-sectional width that is different than a cross-sectional width of the portion1714of the trench1710. Accordingly, when the trench1710is formed, the portion1714of the trench1710can have a different depth than the portion1712of the trench1710.

Although not shown inFIG. 17G, in some embodiments, a transverse trench (e.g., transverse trench380A shown inFIG. 3A) can be formed. In some implementations, the transverse trench can be formed adjacent to the end1731of the shield electrode1730. Accordingly, the transverse trench can be aligned along a vertical axis that is lateral to and parallel to a surface of the end1731.

A dielectric1776is formed as shown inFIG. 17Hafter the cavity1734has been formed via etching of the shield electrode1730has been formed. The dielectric1776is formed at least on a portion of the dielectric1771. In some embodiments, the dielectric1776can be used to form an inter-electrode dielectric1740shown inFIG. 17I. In some embodiments, the dielectric1776can be formed using a deposition process (e.g., an SACVD process), a thermal formation process, and/or so forth. In some embodiments, the dielectric1776can include a borosilicate glass (BSG). In some implementations, one or more of the dielectric1771and the dielectric1776can define a field dielectric (e.g., field dielectric374shown inFIG. 3B). Although not shown, a gate dielectric can also be formed after the inter-electrode dielectric1740has been formed.

As shown inFIG. 17H, the inter-electrode dielectric1740can be defined and recessed using any combination of a CMP process or an etch process. As shown inFIG. 17H, the inter-electrode dielectric1740is recessed within the second portion1712of the trench1710.

After a profile of the inter-electrode dielectric1740has been formed as shown inFIG. 17I, a gate electrode1720can be formed as shown inFIG. 17J. In some embodiments, the gate electrode1720can be formed on (e.g., disposed on) the inter-electrode dielectric1740in the trench1710using a deposition process (e.g., a polysilicon deposition process, an in-situ doped (ISD) amorphous polysilicon deposition process).

The gate electrode1720is recessed to form the gate electrode1720profile shown inFIG. 17K. In this implementation, a surface gate electrode1722and a channel stopper1794are formed. In some implementations, the processing associated with the gate electrode1720, the inter-electrode dielectric1740, and/or the shield electrode1730can be modified to define a different set of profiles (e.g., the profiles shown inFIG. 12B).

As shown inFIG. 17L, an interlayer dielectric1792is formed. In some embodiments, the interlayer dielectric1792can be, for example, a borophosphosilicate glass (BPSG) layer. A gate runner conductor1752and a source runner conductor1754are shown inFIG. 17L. Vias to the gate runner conductor1752and the source runner conductor1754can also be formed.

In another general aspect, an apparatus can include, a semiconductor region, and a first trench defined within the semiconductor region. The first trench can have a depth aligned along a first vertical axis and can have a length aligned along a first longitudinal axis orthogonal to the first vertical axis. The apparatus can include a first dielectric disposed in the first trench, and a second trench defined within the semiconductor region. The second trench can have a depth aligned along a second vertical axis and can have a length aligned along a second longitudinal axis orthogonal to the second vertical axis and orthogonal to the first longitudinal axis. The depth of the second trench can be shallower than the depth of the first trench, and the second trench intersecting can be coupled to the first trench. In some implementations, a second dielectric can be disposed in the second trench, and the second dielectric can have a portion along a bottom surface of the second trench with a thickness along the second vertical axis less than a thickness along the first vertical axis of a portion of the first dielectric along a bottom surface of the first trench.

In some implementations, the first trench is associated with a termination region and the second trench is associated with an active region. The apparatus can include a shield electrode disposed in the second trench, and a gate electrode disposed in the second trench above the shield electrode. In some implementations, the first dielectric has a U-shaped cross-sectional profile, and the second dielectric has a U-shaped cross-sectional profile.

The apparatus can include a first shield electrode disposed in the first trench, and a second shield electrode disposed in the second trench. The first shield electrode can be insulated from the second trench by the first dielectric. In some implementations, the second trench terminates at the first trench such that the first trench is contiguous with the second trench. The apparatus can include a third trench can have at least a portion aligned parallel to a portion of the first trench, the third trench can be isolated from the first trench by a mesa region.

The apparatus can include a first shield electrode disposed in the first trench, and a second shield electrode disposed in the second trench. The first shield electrode can have a bottom surface at a vertical depth deeper than a vertical depth of a bottom surface of the second shield electrode disposed in the second trench.

In some implementations, the first dielectric has a U-shaped cross-sectional profile. The apparatus can include a first shield electrode disposed within the first dielectric in the first trench, and a second shield electrode disposed in the second trench. That apparatus can include a gate electrode disposed in the second trench above the second shield electrode. The gate electrode can have a top surface aligned along a plane. The second shield electrode can have a portion intersecting the plane and disposed between the gate electrode and a sidewall of the first dielectric.

The apparatus can include a first shield electrode disposed in the first trench, and a second shield electrode disposed in the second trench. The first shield electrode can have a recessed top surface at substantially an equal vertical depth of a top surface of the second shield electrode disposed in the second trench.

The apparatus can include a shield electrode disposed in the second trench. The shield electrode can have a first portion along a first portion of the second longitudinal axis with a vertical height different than a vertical height of a second portion of the shield electrode along a second portion of the second longitudinal axis. The apparatus can include a shield electrode disposed in the second trench. The shield electrode can have a recessed portion along a first portion of the second longitudinal axis and can have a non-recessed portion along a second portion of the second longitudinal axis.

In yet another general aspect, an apparatus can include a semiconductor region having a top surface aligned along a first plane and a trench defined within the semiconductor region. The trench can have a depth aligned along a second plane in a vertical direction orthogonal to the first plane and can have a length aligned along a longitudinal axis orthogonal to the second plane. The trench can have a main portion and can have an extension portion and the extension portion can have a bottom surface at a depth different than a depth of a bottom surface of the main portion of the trench. The apparatus can include a shield dielectric disposed in the main portion and aligned along the second plane, and a main dielectric disposed in the main portion of the trench and disposed between the shield dielectric and the bottom surface of the main portion of the trench. The apparatus can include an extension dielectric in contact with the main dielectric and disposed in the extension portion of the trench. The extension dielectric can have a vertical thickness intersecting the second plane and extending between at least the first plane and the bottom surface of the extension portion.

In some implementations, the extension portion of the trench excludes an electrode. In some implementations, the trench is a first trench, and the longitudinal axis is a first longitudinal axis. The apparatus can include a second trench intersecting along a second longitudinal axis orthogonal to the first longitudinal axis and intersecting a junction of the extension portion of the trench and the main portion of the trench.

In some implementations, the extension portion of the trench has a length along the longitudinal axis that is greater than a width of a gate runner can have at least a portion disposed above the extension portion of the trench. In some implementations, the trench is a first trench, and the apparatus can include a plurality of dielectric filled trenches aligned parallel to the first trench. At least one dielectric filled trench from the plurality of dielectric filled trenches can be filled with a dielectric along a length greater than a length of the extension portion along the longitudinal axis.

In some implementations, the depth of the trench extension portion is shallower than a depth of the main portion of the trench. In some implementations, the depth of the trench extension portion is deeper than a depth of the main portion of the trench. In some implementations, the main portion of the trench has a width along the first plane that is different than a width of the extension portion of the trench along the first plane

In some implementations, the main portion of the trench has a width along the first plane that is equal to a width of the extension portion of the trench along the first plane. In some implementations, the main portion of the trench has a width along the first plane that is greater than a width of the extension portion of the trench along the first plane, and the depth of the trench extension portion is shallower than a depth of the main portion of the trench. In some implementations, the main portion of the trench has a width along the first plane that is equal to a width of the extension portion of the trench along the first plane, and the depth of the trench extension portion is deeper than a depth of the main portion of the trench.

It will also be understood that when a layer is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. It will also be understood that when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Portions of methods also may be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Galium Arsenide (GaAs), Silicon Carbide (SiC), and/or so forth.