Enhanced power savings for memory arrays

A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.

BACKGROUND

The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for enhanced power savings in memory arrays.

Static random access memory (SRAM) is a type of volatile digital memory that retains data written to it so long as power is applied to the SRAM. One type of SRAM commonly used in high performance computational circuits is referred to as a “domino” SRAM.

As will be appreciated by those skilled in the art, in prior art domino SRAM designs, the cells are arranged into groups of cells, typically on the order of eight to sixteen cells per group. Each cell in a group is connected to a local bit line pair and the local bit line pair for each group of cells is coupled to a global bit line pair. Rather than use a sense amplifier to detect a differential voltage when reading a cell, in a ripple domino read SRAM scheme the local bit lines are discharged by the cell in a read operation. When a discharge is detected, a state of the cell may then be determined.

SUMMARY

In one illustrative embodiment, a memory array is provided. In the illustrative embodiment, the memory array comprises a plurality of global bit lines, where each bit line is coupled to a plurality of memory cells. In the illustrative embodiment, the memory array comprises a plurality of precharge logic, where each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. In the illustrative embodiment, the memory array comprises identification logic coupled to the plurality precharge logic. In the illustrative embodiment, the identification logic provides a precharge enable signal that enables a subset of the plurality of precharge logic to precharge its associated subset of global bit lines to a voltage level of a voltage source. In the illustrative embodiment, the identification logic sends the precharge enable signal to the subset of precharge logic of the plurality of precharge logic on each clock cycle, thereby reducing the power consumption of the memory array.

In another illustrative embodiment, an integrated chip is provided that comprises a memory array. In the illustrative embodiment, the memory array comprises a plurality of global bit lines, where each bit line is coupled to a plurality of memory cells. In the illustrative embodiment, the memory array comprises a plurality of precharge logic, where each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. In the illustrative embodiment, the memory array comprises identification logic coupled to the plurality of precharge logic. In the illustrative embodiment, the identification logic provides a precharge enable signal that enables a subset of the plurality of precharge logic to precharge its associated subset of global bit lines to a voltage level of a voltage source. In the illustrative embodiment, the identification logic sends the precharge enable signal to the subset of precharge logic of the plurality of precharge logic on each clock cycle, thereby reducing the power consumption of the memory array.

In yet another illustrative embodiment, a data processing system is provided that comprises a processor and a memory coupled to the processor. The memory comprises a memory array and the memory array comprises a plurality of global bit lines, where each bit line is coupled to a plurality of memory cells. In the illustrative embodiment, the memory array comprises a plurality of precharge logic, where each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. In the illustrative embodiment, the memory array comprises identification logic coupled to the plurality of precharge logic. In the illustrative embodiment, the identification logic provides a precharge enable signal that enables a subset of the plurality of precharge logic to precharge its associated subset of global bit lines to a voltage level of a voltage source. In the illustrative embodiment, the identification logic only sends the precharge enable signal to the subset precharge logic of the plurality of precharge logic on each clock cycle, thereby reducing the power consumption of the memory array.

DETAILED DESCRIPTION

The illustrative embodiments provide a circuit arrangement for reducing power consumption in an array system of SRAM cells that addresses shortcomings of prior art array systems of SRAM cells and SRAM devices, thereby enhancing power savings in memory arrays.

FIG. 1is provided as one example of a data processing environment in which a cache memory array may be utilized, i.e. in a cache of a processor.FIG. 1is only offered as an example data processing environment in which the aspects of the illustrative embodiments may be implemented and is not intended to state or imply any limitation with regard to the types of, or configurations of, data processing environments in which the illustrative embodiments may be used. To the contrary, any environment in which a cache memory array may be utilized is intended to be within the spirit and scope of the present invention.

FIG. 1is an exemplary block diagram of processor100in accordance with an illustrative embodiment. Processor100includes controller102, which controls the flow of instructions and data into and out of processor100. Controller102sends control signals to instruction unit104, which includes L1 cache106. Instruction unit104issues instructions to execution unit108, which also includes L1 cache110. Execution unit108executes the instructions and holds or forwards any resulting data results to, for example, L2 cache112or controller102. In turn, execution unit108retrieves data from L2 cache112as appropriate. Instruction unit104also retrieves instructions from L2 cache112when necessary. Controller102sends control signals to control storage or retrieval of data from L2 cache112. Processor100may contain additional components not shown, and is merely provided as a basic representation of a processor and does not limit the scope of the present invention. Although,FIG. 1depicts only level 1 (L1) cache and Level 2 (L2) cache, the illustrative embodiments are not limited to only these levels of memory hierarchy. That is, the illustrative embodiments may be applied to any level of memory hierarchy without departing from the spirit and scope of the invention.

Moreover, the data processing system100may take the form of any of a number of different data processing systems including client computing devices, server computing devices, a tablet computer, laptop computer, telephone or other communication device, a personal digital assistant (PDA), or the like. In some illustrative examples, data processing system100may be a portable computing device which is configured with flash memory to provide non-volatile memory for storing operating system files and/or user-generated data, for example. Essentially, data processing system100may be any known or later developed data processing system without architectural limitation.

FIG. 2depicts an example of a conventional 6 transistor (6T) memory cell in accordance with an illustrative embodiment. Memory cell200forms the basis for most static random-access memories (SRAM) in complementary metal oxide semiconductor (CMOS) technology. Memory cell200uses six transistors201-206to store and access one bit. Transistors201-204in the center form two cross-coupled inverters, which is illustrated in the more simplified memory cell210comprising inverters211and212. Due to the feedback structure created by inverters211and212, a low input value on inverter211will generate a high value on inverter212, which amplifies (and stores) the low value on inverter212. Similarly, a high input value on inverter211will generate a low input value on inverter212, which feeds back the low input value onto inverter211. Therefore, inverters211and212will store their current logical value, whatever value that is.

Lines217and218between inverters211and212are coupled to separate bit-lines219and220via two n-channel pass-transistors215and216. The gates of transistors215and216are driven by word line221. In a memory array, word line221is used to address and enable all bits of one memory word. As long as word line221is kept low, memory cell210is decoupled from bit-lines219and220. Inverters211and212keep feeding themselves and memory cell210stores its current value.

When word line221is high, both transistors215and216are conducting and connect the inputs and outputs of inverters211and212to bit-lines219and220. That is, inverters211and212drive the current data value stored inside the memory cell210onto bit-line219and the inverted data value onto inverted bit-line220. To write new data into memory cell210, word line221is activated and, depending on the current value stored inside memory cell210, there might be a short-circuit condition and the value inside memory cell210is literally overwritten. This only works because transistors202-203are very weak. That is, transistors202-203are considered weak because when new data is to be written to transistors201-204, the current state of transistors201-204may be easily overridden with the new state.

The majority of the power dissipated in cache memory arrays comes from the pre-charging and discharging of bit-lines during a read access. The bit-lines, such as bit-lines219and220inFIG. 2, span the entire height of the cache memory array and tend to be highly capacitive and thus introduce stability issues into each memory cell.

FIG. 3illustrates a high-level example of a typical cache memory array comprising multiple memory cells in accordance with an illustrative embodiment. Memory array300comprises memory cells302arranged as an array having rows304and columns306. Memory cells302in a particular row304are connected to one another by word lines308. Word lines308of each row304are also connected to word line drivers310which receive output312from address decoder314that identifies which row304is to be output and cache memory array300outputs the corresponding data entry through data outputs316. Word line driver310may provide a single word line, such as word line221ofFIG. 2. Memory cells302in a particular column306are connected to one another by a pair of local bit lines318which are driven to complimentary during write executions and are traditionally precharged to the voltage supply. Bit lines318may be true and compliment bit lines, such as true bit line219and compliment bit line220ofFIG. 2. In the ripple domino read scheme ofFIG. 3, a read operation starts with address decoder314receiving an address associated with a read/write access from external logic322. Address decoder314decodes the address and signals the particular one of word line drivers310associated with the decoded address using output312. The particular one of word line drivers310then fires due to the signal from address decoder314and word line308rises such that the data in the associated row304of memory cells302is output. Memory cells302pull down one of their associated local bit lines318. Each local bit line318is coupled to a local evaluation circuit320which acts as an amplifier for the read signal. Therefore the local evaluation circuit320comprises amplifier structure to pull down a global bit line gbl′ which is a high capacity node due to the long wiring length and the device capacitance of the local evaluation circuit pull-down devices. The value of the data read from each memory cell302of the associated row304is then latched by output latch324before being output through data outputs316.

FIG. 4depicts a ripple domino read scheme of an SRAM cell, such as memory cell210ofFIG. 2or one of memory cells302ofFIG. 3, in accordance with an illustrative embodiment. In memory array400, during a read of memory cell402, read word line404is high, which drives the gate of transistor406to pass the value from memory cell402onto bl′ local bit line408, such as bl′ local bit line219ofFIG. 2. Evaluation circuit410, which is coupled to bl′ local bit line408, acts as an amplifier for the read signal of bl′ local bit line408. That is, the elements in evaluation circuit410represent only those elements required for a domino read operation and not for other operations such as precharging. Thus, one of ordinary skill in the art will recognize that evaluation circuit410may comprise many other elements and does not disclose elements that are not the focus of the present invention.

Evaluation circuit410comprises P-Channel Field Effect Transistors (P-FETs)412and414and N-Channel Field Effect Transistor (N-FET)416. P-FET transistor412includes a gate terminal (G1), a source terminal (S1), and a drain terminal (D1). P-FET transistor414includes a gate terminal (G2), a source terminal (S2), and a drain terminal (D2). N-FET transistor416includes a gate terminal (G3), a source terminal (S3), and a drain terminal (D3). Gate terminal G1is electrically coupled to bl′ local bit line408. Source terminal S1is electrically coupled to voltage source (Vdd)418. Drain terminal D1is electrically coupled to source terminal S2. Gate terminal G2is electrically coupled to a read enable (rdt) signal424. Drain terminal D2is electrically coupled to gate terminal G3, drain terminal D3is electrically coupled to ground420, and source terminal S3is electrically coupled to global bit line (gbl′)422.

Thus, in evaluation circuit410, upon a read of memory cell402by word line404going high, if the value stored by memory cell402is a 0, then the gate of transistor412will be high and voltage from Vdd418will not pass to transistor414, and, conversely, if the value stored by memory cell402is a 1, then the gate of transistor412will be low and voltage from Vdd418will pass to transistor416. Further, if the rdt signal424is active, then the gate of transistor414will be high and voltage from Vdd418, if present based on the state of transistor412, will not pass to transistor416, and, conversely, if the rdt signal424is not active, then the gate of transistor414will be low and voltage from Vdd418, if present based on the state of transistor412, will pass to transistor416. If the value received from transistor414is a 1, then the gate of transistor416will be high, which will cause a discharge to ground420and a 0 will be passed onto gbl′422. Conversely, if the value received from transistor414is a 0, then the gate of transistor416will be low, which will cause a 1 to be passed onto gbl′422. Global bit line (gbl′)422, which is a high capacity node due to the long wiring length and the device capacitance of the local evaluation circuit pull-down devices, is the biggest contributor for active and passive power consumption in ripple domino SRAM arrays.

If transistor416outputs a 1 onto gbl′422, inverter426will invert the HIGH signal to a LOW signal, which is recognized by any logic downstream as being a ‘0’ from memory cell402. Conversely, if transistor416outputs a 1 onto gbl′422, inverter426will invert the LOW signal to a HIGH signal, which is recognized by any logic downstream as being a ‘0’ from memory cell402.

Memory cell402is just one example of a memory cell in a plurality of memory cells that may be coupled to local bitline408. Memory cells, such as memory cell402, coupled to word line404are read out all at the same time in spite of the fact that only the information of one memory cell is needed at output428. In a cache that uses a number N global bit lines gbl′, N:1-way multiplexer430chooses which global bit line gbl′ to read based on control signal432.

For each global bit lines in the cache, each global bit line is charged every cycle to the level of voltage from Vdd418. For example, after a read of memory cell402, global bit line restore and latch device434precharges gbl′422. Global bit line restore and latch device434comprises pull-up-PFET436and latch438. P-FET transistor436includes a gate terminal (G4), a source terminal (S4), and a drain terminal (D4). In order to precharge gbl′422, global bit line restore signal440which is electrically coupled to gate terminal G4activates, based on local clock (lclk) signal444from array local clock buffer442, which is inverted through inverter446, so that voltage from Vdd418coupled to source terminal S4will pass to gbl′422which is electrically coupled to drain terminal D4. Once gbl′422is precharged, latch438latches the signal so that global bit line restore signal440may be deactivated. Thus, as is illustrated the precharging of all global bit lines at each cycle and the leakage of transistor416when gbl′422is precharged are the main contributor to power consumption in the cache.

In order to address the precharging of all global bit lines at each cycle, the illustrative embodiments provide logic that reduces power consumption in a memory array system of memory cells.FIG. 5depicts a ripple domino read scheme of an SRAM cell, such as memory cell210ofFIG. 2or one of memory cells302ofFIG. 3, with additional logic for reducing power consumption normally consumed by precharging of all global bit lines at each cycle in accordance with an illustrative embodiment.

With reference toFIG. 5, memory array500includes, in addition to the elements particular to the illustrative embodiments, elements that are similar to elements depicted in memory array400ofFIG. 4. Thus, elements inFIG. 5that are not specifically described as operating differently from elements inFIG. 4are intended to operate in a similar manner as their corresponding elements inFIG. 4. For example, memory array500comprises memory cell502, evaluation circuit510, N:1-way multiplexer530, and global bit line restore and latch device534, as well as elements504-508,512-524,528,532,536,538,542, and544, each of which operate in a similar manner to that described with the corresponding elements inFIG. 4.

However, in order to reduce power consumption normally consumed by precharging of all global bit lines at each cycle, only a subset of global bit line restore and latch devices534, which may also be referred to as precharge logic, activated by the prediction logic546, precharges a subset of global bit lines gbl′522. Similar to memory cell402ofFIG. 4, memory cell502is just one example of a memory cell in a plurality of memory cells that may be coupled to bl′ local bitline508. Further, a plurality of evaluation circuits510may be coupled to global bit line gbl′522. Memory cells, such as memory cell502, coupled to word line504are read out all at the same time in spite of the fact that only the information of one memory cell is needed at output528. In a cache that uses a number N global bit lines gbl′, N:1-way multiplexer530chooses which global bit line gbl′ to read based on control signal532.

In order to only precharge a respective subset of global bit lines gbl′522that are predicted, memory array500may, for example, comprise identification logic such as prediction logic546, which provides early enable signal(s)548to master-slave latch set550and552. In this exemplary embodiment, prediction logic546is logic that looks for repeating patterns of predictable short loops, which are expected to be seen in the highest power benchmarks, in executed program code. In highest power benchmarks, prediction logic546may predict branches in short loops and which global bit lines should be selected later on. Again, memory array500only illustrates one memory cell associated with one global bit line. However, as is shown inFIG. 3, there are many global bit lines in a memory array. As one of ordinary skill in the art will recognize there may be many different ways to identify which global bit line to precharge from the plurality of global bit lines. That is, for example, rather than using prediction logic546to provide early enable signal(s)548to master-slave latch set550and552, memory array500may have identification logic that evaluates a highest read address bit or the like.

That is, prediction logic546predicts which gbl′ will be selected and sends an active “1” early enable signal548to the latches, such as master-slave latch set550and552, and sends an inactive “0” to all of the other latches. In case there is a miss and the prediction logic does not know which global bit line will be selected, prediction logic546sends an active “1” early enable signal548to all latches. While there may be no power savings on a miss, for all other operations, beneficial power savings is provided by not precharging global bit lines that are not predicted.

Thus, if activated by prediction logic546, master latch550provides precharge enable signal L1554as an input to NAND gate556, which replaces inverter446ofFIG. 4. Master latch550provides a scanable boundary in front of memory array500in order to observe prediction logic546during chip testing. That is, in the configuration shown inFIG. 4, local clock (lclk) signal444from array local clock buffer442is the global bit line restore signal440. In memory array500, precharge enable signal L1554is one input to NAND gate556and local clock (lclk) signal544from array local clock buffer542is the other input. Only when precharge enable signal L1554and local clock (lclk) signal544are active will NAND gate556output an active global bit line restore signal540. Thus, master latch550provides a precharge suppression for memory array500.

Further, if activated by prediction logic546, slave latch552provides precharge enable signal L2558as an input to NOR gate560, which replaces inverter426ofFIG. 4. Slave latch552provides storage of the predicted value constant thought the time where the access to memory array500is evaluated. In memory array500, precharge enable signal L2558is one input to NOR gate560and global bit line522is the other input. When either or both of precharge enable signal L2558and global bit line522are active, NOR gate560will output a 0 to N: 1-way multiplexer530. However, if both precharge enable signal L2558and global bit line522are low active, then NOR gate560will output a 1 to N: 1-way multiplexer530. Thus, slave latch552and NOR gate560provide a force structure for N:1-way multiplexer530. That is, N:1 multiplexer530, which is implemented in dynamic logic, requires that the dynamic multiplex input structure return to “0” after each read so that the global bit line gbl′ 522 may be precharged. Therefore, NOR gate560forces the input to N:1 multiplexer530to “0” when either or both of precharge enable signal L2558and global bit line522are active. As one of ordinary skill in the art will realize, there are many different ways to output the signal from NOR gate560to downstream logic coupled to memory array500. That is, instead of using N:1-way multiplexer530as an output device, memory array500could, for example, use any type of output device such as coupling the output of NOR gate560directly to output528, coupling the output of NOR gate560to other static logic, or the like.

Thus, the additional logic provided inFIG. 5provides a significant benefit over the state of the art implementation. Since only the selected global bit line gbl′ is pulled up to supply voltage, power consumption is reduced by not precharging the remaining global bit lines in the memory array.

FIG. 6shows a block diagram of an exemplary design flow600used, for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow600includes processes and mechanisms for processing design structures to generate logically or otherwise functionally equivalent representations of the embodiments of the invention shown inFIGS. 1-5. The design structures processed and/or generated by design flow600may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems.

FIG. 6illustrates multiple such design structures including an input design structure620that is preferably processed by a design process610. Design structure620may be a logical simulation design structure generated and processed by design process610to produce a logically equivalent functional representation of a hardware device. Design structure620may also or alternatively comprise data and/or program instructions that when processed by design process610, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure620may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission or storage medium, design structure620may be accessed and processed by one or more hardware and/or software modules within design process610to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 1-5. As such, design structure620may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process610may include hardware and software modules for processing a variety of input data structure types including netlist680. Such data structure types may reside, for example, within library elements630and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications640, characterization data650, verification data660, design rules670, and test data files685which may include input test patterns, output test results, and other testing information. Design process610may further include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

Design process610employs and incorporates well-known logic and physical design tools such as HDL compilers and simulation model build tools to process design structure620together with some or all of the depicted supporting data structures to generate a second design structure690. Similar to design structure620, design structure690preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown inFIGS. 1-5. In one embodiment, design structure690may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown inFIGS. 1-5.

Design structure690may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure690may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data processed by semiconductor manufacturing tools to fabricate embodiments of the invention as shown inFIGS. 1-5. Design structure690may then proceed to a stage695where, for example, design structure690proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

Again, the design structures processed and/or generated by design flow600may be encoded on machine-readable (i.e., computer readable) transmission or storage media. Therefore, as will be appreciated by one skilled in the art, the present invention may be embodied as a system, method, or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in any one or more computer readable medium(s) having computer usable program code embodied thereon.