Peak detecting cascode for breakdown protection

Peak detecting cascode for breakdown protection. In some embodiments, a power amplifier can include an amplifying transistor configured to amplify a radio-frequency (RF) signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The power amplifier can further include a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit can be configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

BACKGROUND

Field

The present disclosure relates to radio-frequency (RF) amplifiers.

Description of the Related Art

In many radio-frequency (RF) applications, amplifiers are utilized to amplify RF signals. For example, an RF signal to be transmitted can be amplified by a power amplifier (PA). In another example, an RF signal received through an antenna can be amplified by a low-noise amplifier (LNA).

SUMMARY

According to some implementations, the present disclosure relates to a power amplifier (PA) that includes an amplifying transistor configured to amplify a radio-frequency (RF) signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The PA further includes a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit is configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

In some embodiments, the amplifying transistor can be part of a cascode amplifier circuit. The amplifying transistor can be a cascode gain stage transistor. The cascode gain stage transistor can be a bipolar-junction transistor (BJT) having a base, an emitter, and a collector, such that the base is associated with the bias node and the collector is associated with the output node.

In some embodiments, the bias circuit can include an emitter follower having an emitter coupled to the base of the cascode gain stage transistor, a collector coupled to a DC voltage source, and a base coupled to a reference voltage source.

In some embodiments, the bias adjustment circuit can include a detection circuit that couples the collector of the cascode gain stage transistor and the base of the emitter follower. The detection circuit can be configured to be conducting when the potential difference is greater than the threshold value and non-conducting when the potential difference is less than or equal to the threshold value.

In some embodiments, the detection circuit can include one or more diodes arranged in series, with the number of diodes being selected based at least in part on the threshold value and turn-on characteristic of each diode. In some embodiments, the one or more diodes can include a plurality of substantially same diodes. In some embodiments, the one or more diodes can be selected to yield a potential difference threshold between the collector and base of the cascode gain stage transistor having an amount represented by Vdiode(Ndiodes+2 Vbe), with Vdiodebeing a turn-on voltage of each diode, Ndiodesbeing the number of diodes, and 2 Vbe being the potential difference between the emitter of the emitter follower and the base of the cascode gain stage transistor.

In some embodiments, the bias adjustment circuit can further include a capacitance Cpk that couples the base of the emitter follower to ground. The capacitance Cpk can be configured to allow charge to be accumulated from the detection circuit when the detection circuit is conducting, to thereby adjust the voltage at the base of the emitter follower.

In some embodiments, the bias adjustment circuit can be configured to increase the bias voltage in response to the potential difference between the collector and the base exceeding the threshold value to thereby reduce the potential difference to a value less than the threshold value. The threshold value can be at or close to a breakdown voltage between the collector and the base of the BJT, such that the reduction of the potential difference prevents or reduces the likelihood of breakdown of the BJT. The bias adjustment circuit can be further configured to restore the bias voltage to a normal operating value when the potential difference between the collector and the base is less than or equal to the threshold value.

In some embodiments, the cascode amplifier circuit can further include a common emitter gain stage transistor having a base configured to receive the RF signal and a collector coupled to the emitter of the cascode gain stage transistor. The common emitter gain stage transistor can be configured to have a significant range of operating voltage to allow the bias voltage of the cascode gain stage transistor to be adjusted in a relatively large range to prevent or reduce the likelihood of breakdown of the cascode gain stage transistor. The relatively large range of the bias voltage available for the cascode gain stage transistor can allow the cascode gain stage transistor to be operated in a normal condition with nominal voltage peaks that are near a device breakdown voltage.

In some embodiments, the bias adjustment circuit can be a passive circuit having little or no impact on performance of the BJT when the bias voltage is at the normal operating value.

In some teachings, the present disclosure relates to a method for operating a power amplifier (PA). The method includes providing a radio-frequency (RF) signal to an amplifying transistor having a bias node and an output node. The method further includes supplying a bias voltage to the bias node to yield an amplified signal at the output node. The method further includes detecting a condition where a potential difference between the output node and the bias node exceeds a threshold value. The method further includes adjusting the bias voltage in response to the detection of the condition.

In accordance with a number of implementations, the present disclosure relates to a semiconductor die that includes a semiconductor substrate and a power amplifier (PA) implemented on the semiconductor substrate. The PA includes an amplifying transistor configured to amplify a radio-frequency (RF) signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The PA further includes a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit is configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

In some embodiments, the PA can be a gallium arsenide (GaAs) device or a silicon germanium (SiGe) device.

In a number of implementations, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of components, and a power amplifier (PA) implemented on a die that is mounted on the packaging substrate. The PA includes an amplifying transistor configured to amplify an RF signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The PA further includes a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit is configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

In some teachings, the present disclosure relates to a wireless device that includes a transceiver configured to generate a radio-frequency (RF) signal, and an RF module in communication with the transceiver. The RF module includes a power amplifier (PA) having an amplifying transistor configured to amplify the RF signal. The PA further includes a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The PA further includes a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit is configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value. The wireless device further includes an antenna in communication with the RF module. The antenna is configured to facilitate transmission of the amplified RF signal.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Radio-frequency (RF) amplifiers such as power amplifiers (PAs) operating at conditions such as higher DC supply voltage and extreme load voltage standing wave ratio (VSWR) can be subject to voltage breakdown and reduced device reliability. Safeguards to protect against such voltage breakdown are required or desired to avoid device damage under such extreme conditions. However, such safeguards often require added design margins that result in degraded nominal operating conditions.

FIG. 1depicts an RF amplifier100configured to receive an input RF signal (RF_IN) and generate an amplified RF signal (RF_OUT). Such an amplification can be performed by an amplifier circuit102which is typically biased by a bias circuit (not shown inFIG. 1). Described herein are examples of a bias adjustment circuit104that can be configured to provide, for example, protection against voltage breakdown of one or more devices associated with the amplifier circuit102. In various examples, the amplifier circuit102is described as having a cascode amplifier topology which can provide a number of desirable features in RF applications. However, it will be understood that one or more features of the present disclosure can also be implemented in other amplifier topologies.

FIG. 2depicts an example of a cascode amplifier circuit102having a first transistor Q1configured to operate as a common emitter device, and a second transistor Q2configured to operate as a common base device. More particularly, an input RF signal (RF_IN) is shown to be provided to a base of Q1, and Q1is shown to output an amplified signal through its collector. The emitter of Q1is shown to be coupled to ground. The amplified signal from the collector of Q1is shown to be provided to the emitter of Q2for further amplification, and such further amplified signal is shown to be output as RF_OUT through the collector of Q2. Although not shown inFIG. 2, the base of Q2is typically AC coupled to ground.

Each base of Q1and Q2is typically coupled to a bias circuit to provide a base bias voltage for the device (Q1or Q2) at the base. Examples of such bias circuits are described herein in greater detail.

In the example ofFIG. 2, each of Q1and Q2is an NPN device. In an example context where much of the gain of the cascode amplifier circuit102occurs in Q2,FIG. 3depicts various voltage levels associated with operation of Q1and Q2. The base of Q1is typically provided with a relatively low voltage Vbb1. A higher base voltage Vbb2is typically provided for the base of Q2, and the collector of Q2has a voltage level higher than Vbb2. To accommodate the foregoing cascode configuration, there is typically a relatively large overhead in voltage associated with Q2.

As described herein, operating conditions such as higher DC supply voltage and extreme load voltage standing wave ratio (VSWR) can result in a voltage breakdown of, for example, Q2. InFIG. 3, the operating voltage level of Vcc2is depicted as being lower than a breakdown voltage (Vbreakdown2) associated with Q2. Such a breakdown voltage can be relative to, for example, the base voltage Vbb2of Q2. Although not shown inFIG. 3, such a breakdown voltage can also be relative to the emitter voltage level of Q2. Examples of breakdowns associated with Q2are described herein in reference toFIGS. 5 and 6.

Under the foregoing example operating condition of higher DC supply voltage and high VSWR, the collector voltage of Q2can rise above the breakdown voltage threshold (Vbreakdown2) relative to the base voltage Vbb2. InFIG. 3, such a rise of the collector voltage from the normal operating level Vcc2to the elevated level Vcc2′ is depicted by an arrow106. Since the potential difference between Vcc2′ and Vbb2is greater than the threshold potential difference of Vbreakdown2−Vbb2, breakdown can occur between the collector and the base of Q2. In some embodiments, Vbb2can be roughly 2×Vbb1, Vcc2can be roughly 10×Vbb1, and Vcc2′ can be roughly 3×Vcc2. One or more features of the present disclosure can also be implemented in other voltage-level configurations.

FIG. 4shows an example of a conventional power amplifier (PA)110having the cascode amplifier circuit102ofFIG. 2supported by a bias circuit112and a supply circuit128. Such a conventional PA can be subjected to the breakdown described above in reference toFIG. 3, andFIGS. 5 and 6show additional examples of such a breakdown.

In the example ofFIG. 4, an input RF signal (RF_IN) is shown to be provided to the base of Q1(at node120) through, for example, a DC-block capacitance C1. Q2is shown to be coupled to Q1as described herein so as to yield an amplified RF signal as an output (RF_OUT) of the cascode amplifier circuit102at the collector of Q2(at node130).

In the example ofFIG. 4, the supply circuit128is shown to include an inductance L that can couple a supply voltage Vcc node to the collector node130of Q2. The inductance L can be configured to provide, for example, RF choke functionality.

In the example ofFIG. 4, the bias circuit112is shown to provide a bias signal to each of the base nodes (120,126) corresponding to Q1and Q2. For example, the base node120of Q1can be coupled to a source node (e.g., a battery node Vbatt) through an emitter follower Q3and a base resistance R2. The output of the emitter follower Q3can be regulated by a reference voltage at the base (node116) of Q3, and such a reference voltage can be obtained from a current source114configured to obtain a reference current (Ibias) sourced from Vbatt. The reference voltage at the base node116can be obtained from Ibias forward-biasing diodes D1and D2, resulting in a reference voltage which tracks process and temperature of the Q1and Q3devices. Resistance Rck can act as a choke resistor to substantially isolate any RF signal from corrupting the Ibias reference current.

FIG. 4further shows that a resistive shunt path (with a resistance R1) to ground can also be provided at the emitter node118of Q3. R1can provide a shunt path for quiescent biasing of Q3to properly set a low bias impedance presented to Q1through R2. The value of R2can be configured to control gain linearity of the cascode amplifier.

As further shown inFIG. 4, the base node126of Q2is shown to be coupled to ground through a capacitance Ccsd. The base node126of Q2can also be coupled to a source node (e.g., a battery node Vbatt) through an emitter follower Q4and a base resistance Rfilt. The output of the emitter follower Q4can be regulated by a reference voltage at the base (node124) of Q4, and such a reference voltage can be obtained from a current source122configured to obtain a reference current (Ibias) sourced from Vbatt.

In the example ofFIG. 4, the reference voltage at the base node124can be obtained from Ibias forward-biasing diodes D3-D5plus Ratk, resulting in a reference voltage which tracks process and temperature of the Q2and Q4devices and providing sufficient collector-emitter voltage for Q2. Rck can act as a choke resistor to substantially isolate any RF signal from corrupting the Ibias reference current.

FIGS. 5 and 6show examples of breakdowns that can occur for the example PA ofFIG. 4, when the voltage level at the collector node130of Q2rises above a threshold level as described in reference toFIG. 3.

It is noted that a bipolar device such as the bipolar junction transistor (BJT) Q2typically demonstrates two dominant breakdown modes. The first example breakdown mode typically involves a collector-emitter breakdown, with the base open. Such a breakdown can occur when a collector-emitter potential difference VCEboexceeds a threshold which results in carrier injection at the base. A high base impedance prevents the elimination of the extra base charge, thereby forcing the carriers to flow into the base-emitter. Current gain of the device generates increased collector current driving into avalanche breakdown, and mechanical and/or thermal failure of the device can occur.

The second example breakdown mode typically involves a collector-base breakdown, with the emitter open. Such a breakdown can occur when a collector-base potential difference VCBeoexceeds a threshold value. When the base is presented with a low impedance path to ground, the foregoing collector-emitter breakdown involving VCEbocan be avoided by leaking the base charge out of the device. Such a leakage can result in further increase in collector voltage, which in turn results in the collector-base breakdown condition VCBeobeing reached. Accordingly, a reverse-breakdown can occur for the collector-base junction diode. It is noted that VCBeois often about 1.5 to 2 times that of VCEbo.

FIG. 5shows a breakdown configuration140involving the foregoing first breakdown mode in the context of the example PA110ofFIG. 4. In the first breakdown mode involving VCEbo, the high base impedance can prevent or reduce the removal of the extra base charge, thereby forcing the carriers to flow into the base-emitter. However, even in such a condition, the cascode device (e.g., Q2) typically will not demonstrate failure at VCEbobecause the total emitter current is limited. Accordingly, current flow into the base as a result of VCEboor VCBeocan lead to charging of the capacitance Ccsd and raising the base bias voltage. Thus, the increased base and emitter voltages can work to divide the high voltage stress across the two devices Q1, Q2, and lead to a breakdown of either or both devices when the collector voltage (of Q2) reaches, for example, roughly twice the value of VCBeo. Accordingly, in the example ofFIG. 5, the breakdown of Q2is depicted as including a current flow142between the collector node130and the base node126.

FIG. 6shows a breakdown configuration150involving the foregoing second breakdown mode in the context of the example PA110ofFIG. 4. In the second breakdown mode involving VCBbo, presence of a relatively low impedance shunt path from the base to ground can result in the collector-base breakdown instead of the collector-emitter breakdown. Device failure in such a breakdown can occur when the current flowing through the reverse collector-to-base base breakdown and into the shunt path to ground is sufficient to cause mechanical and/or thermal damages. Accordingly, in the example ofFIG. 6, the breakdown of Q2is depicted as including a current flow152between the collector node130to the base node126, with the current flow being facilitated by a shunt path shown to include a resistance Rsh and a diode Dsh.

FIG. 7shows that in some embodiments, a bias adjustment circuit104can be implemented between the collector of Q2and the bias circuit associated with Q2. As described herein, such a bias adjustment circuit can be configured to inhibit or reduce the likelihood of breakdowns involving the base of Q2. For the purpose of description, the cascode amplifier circuit102can be similar to the example described in reference toFIG. 2.

FIG. 8depicts various voltage levels associated with operation of Q1and Q2. Normal operating levels of Vbb1and Vbb2can be similar to the example described herein in reference toFIGS. 2 and 3. Similarly, the operating voltage level of Vcc2is typically lower than a breakdown voltage (Vbreakdown2) associated with Q2. As also described herein, conditions such as higher DC supply voltage and high VSWR can lead to the collector voltage of Q2rising above the breakdown voltage threshold (Vbreakdown2) relative to the base voltage Vbb2. InFIG. 8, such an elevated level of collector voltage is indicated as Vcc2′. Since the potential difference between Vcc2′ and Vbb2is greater than the threshold potential difference ΔV of Vbreakdown2−Vbb2, breakdown can occur between the collector and the base of Q2.

In some embodiments, the bias adjustment circuit104ofFIG. 7can be configured such that when the base voltage is maintained at Vbb2under normal operating condition, and adjusted (e.g., raised as indicated by an arrow162) to Vbb2′ when the collector voltage exceeds the breakdown voltage threshold (Vbreakdown2). InFIG. 8, such collector voltage Vcc2′ and raised Vbb2′ are shown to yield a potential difference ΔV'. In some embodiments, the potential difference ΔV′ can be less than the potential difference ΔV between the breakdown voltage threshold (Vbreakdown2) and the un-raised base voltage Vbb2. Since the potential difference ΔV' is less than the breakdown threshold potential difference of ΔV, breakdown between the collector and the base can be prevented.

FIG. 7further shows that the bias adjustment circuit104can include a detection circuit160that couples the collector of Q2with the bias circuit. In some embodiments, the bias adjustment circuit104can also include, and/or work in conjunction with, at least some portion of the bias circuit to facilitate the foregoing adjustment of the base voltage (e.g., Vbb2to Vbb2′ as shown inFIG. 8). In some embodiments, such a bias adjustment circuit can be configured to have little or no impact on performance of the PA circuit102under normal operating conditions.

FIG. 9shows an example of the bias adjustment circuit104ofFIGS. 1 and 7, implemented in the context of the example PA110ofFIG. 4. InFIG. 9, a PA100is shown to include a PA circuit102and a supply circuit128that can be similar to the example ofFIG. 4. A bias circuit generally indicated as112can be similar to the example ofFIG. 4, but with an addition of a capacitance Cpk that couples the base node124of Q4to ground. Examples of how Cpk, as well as other element(s) of the bias circuit112can be configured to operate as part of and/or in conjunction with the bias adjustment circuit104are described herein in greater detail.

FIG. 9shows that in some embodiments, the detection circuit160described in reference toFIG. 7can include N diode(s) arranged in series between the collector node130of the cascode transistor Q2and the base node124of Q4. The quantity N can be a positive integer, and such a number can depend on, for example, turn-on voltage characteristics. For example, 12 diodes with each being a 1.2V diode can yield a detection circuit having a threshold voltage difference of 12×1.2V=14.4V between the collector node130(of Q2) and the base node124(of Q4). For the cascode transistor Q2, such 12 diodes providing the coupling between Q4and Q2can yield a threshold value of approximately 17V (e.g., 1.2V×(12 diodes)+2 Vbe) between its collector node130and its base node126. Such an approximate value of 17V can result when the diode voltage Vd and Vbe are very similar, such that 1.2V× (12 diodes)+2 Vbe can be expressed as being approximately equal to (1.2)(12)V+2(1.2)≈17V.

In some embodiments, the capacitance Cpk can be configured to allow build-up of charge when the chain of N diodes become conductive, to thereby increase the voltage at the base of Q4. Accordingly, the current passed through Q4also increases, thereby increasing the voltage Vbb2at the base node126of Q2.

In some embodiments, the capacitance Cpk and the resistance Ratk can be configured to work in conjunction to, for example, set the video bandwidth of the peak detector function. In some embodiments, the resistance Rfilt and the cascode base bypass capacitance Ccsd can be configured to, for example, define the dominant pole of the feedback loop for stable loop operation.

As described herein, the detection circuit160ofFIGS. 7 and 9can be implemented as an RF peak detector that allows modification of a bias point of a cascode gain stage during an extreme operating condition. A PA (e.g., 100 inFIGS. 7 and 9) having such a peak detector can be configured to utilize a fixed bias cascode to maximize RF swing on the cascode gain stage (Q2) and minimize overhead of the common emitter gain stage (Q1).

For example, it is noted that there is a significant range of operating voltage available in the common emitter gain stage (Q1) before it is subjected to a breakdown condition. Such a range of Q1can allow the bias point of the cascode gain stage (Q2) to be adjusted as described herein to prevent breakdown of Q2. Accordingly, nominal operation of Q2can be configured so that nominal voltage peaks are near device breakdown. If some of such voltage peaks exceeds the threshold set by the RF peak detector, the bias point of Q2can be adjusted as described herein.

In various examples described herein, the cascode amplifiers are described in the context of BJTs. However, it will be understood that one or more features of the present disclosure can be implemented in cascode amplifiers that include other types of transistors, such as field-effect transistors (FETs).

It will also be understood that while various examples are described in the context of NPN devices which results in corresponding voltage levels, one or more features of the present disclosure can also be implemented in PNP devices, or in applications where voltage levels may be different than in NPN devices.

FIG. 10depicts a semiconductor die200that can include a bias adjustment circuit104having one or more features as described herein. The semiconductor die200can include a substrate202. In some embodiments, a power amplifier (PA) circuit102(e.g., SiGe or GaAs devices) can also be implemented on the substrate202. A plurality of connection pads204can also be formed on the substrate202to provide, for example, power and signals for the PA circuit102.

In some implementations, one or more features described herein can be included in a module.FIG. 11depicts an example module300having a packaging substrate302that is configured to receive a plurality of components. In some embodiments, such components can include a die200having one or more features as described herein. For example, the die200can include a PA circuit102and a bias adjustment circuit104. A plurality of connection pads304can facilitate electrical connections such as wirebonds308to connection pads310on the substrate302to facilitate passing of various power and signals to and from the die200.

In some embodiments, other components can be mounted on or formed on the packaging substrate302. For example, one or more surface mount devices (SMDs) (314) and one or more matching networks (312) can be implemented. In some embodiments, the packaging substrate302can include a laminate substrate.

In some embodiments, the module300can also include one or more packaging structures to, for example, provide protection and facilitate easier handling of the module300. Such a packaging structure can include an overmold formed over the packaging substrate302and dimensioned to substantially encapsulate the various circuits and components thereon.

It will be understood that although the module300is described in the context of wirebond-based electrical connections, one or more features of the present disclosure can also be implemented in other packaging configurations, including flip-chip configurations.

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc.

FIG. 12schematically depicts an example wireless device400having one or more advantageous features described herein. One or more PAs102as described herein can utilize one or more bias adjustment circuits104as described herein. In embodiments where the PAs102and their bias adjustment circuit(s)104are packaged into a module, such a module can be represented by a dashed box300. In some embodiments, the module300can include at least some of input and output matching circuits.

The PAs102can receive their respective RF signals from a transceiver410that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver410is shown to interact with a baseband sub-system408that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver410. The transceiver410is also shown to be connected to a power management component406that is configured to manage power for the operation of the wireless device400. Such power management can also control operations of the baseband sub-system408and the module300.

The baseband sub-system408is shown to be connected to a user interface402to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system408can also be connected to a memory404that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example wireless device400, outputs of the PAs102are shown to be matched and routed to an antenna416via their respective duplexers412a-412dand a band-selection switch414. The band-selection switch414can be configured to allow selection of, for example, an operating band or an operating mode. In some embodiments, each duplexer412can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,416). InFIG. 12, received signals are shown to be routed to “Rx” paths that can include, for example, a low-noise amplifier (LNA).