Low-power clock gating circuit

Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 2006-122514, filed Dec. 5, 2006, and No. 2007-54320, filed Jun. 4, 2007, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a clock gating circuit capable of blocking a clock supplied in an active mode when a device in a targeted logic circuit does not operate and retaining data without leakage current in a sleep mode, by using a Multi-Threshold CMOS (MTCMOS) technique.

The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2006-S-006-01, Components/Module technology for Ubiquitous Terminals] in Korea.

2. Discussion of Related Art

FIG. 1illustrates a conventional clock gating circuit using a single threshold voltage and including an AND gate150. A gated clock GCLK is transferred to a flip-flop200. When an enable signal EN is high, an input clock CP passes through the AND gate150and the gated clock GCLK is transferred to the flip-flop200. When the enable signal EN is low, the gated clock GCLK becomes low irrespective of the input clock CP and the clock is not supplied to the flip-flop200. Thus, the clock gating circuit has such a simple structure. However, the gated clock GCLK from the clock gating circuit ofFIG. 1may include glitch or spike.

FIG. 2illustrates a clock gating circuit160comprising a latch circuit located at an input of the AND gate150to solve the problem associated with the clock gating circuit ofFIG. 1, in which a conventional single threshold voltage is used. Here, when a 130 nm transistor operating at 1.2V is used, the single threshold voltage is about 0.34V. The configuration and operation of the conventional clock gating circuit ofFIG. 2will now be described. The clock gating circuit160using a single threshold voltage includes a transmission gate100that is controlled by a clock signal CP and an inverted clock signal CPb and receives an enable signal EN from a targeted logic gate170, a feedback transmission gate140connected via a second inverter130for inverting an output signal of a first inverter110, and an AND gate150for receiving the enable signal from the third inverter120via the first inverter110and the clock CP and outputting the gated clock GCLK.

The clock signal CP is generated by a clock signal generating circuit (not shown), and the inverted clock signal CPb is an inverted version of the clock signal CP.

Each of the transmission gate100, the inverters110,120and130, the feedback transmission gate140, and the AND gate150consists of a PMOS transistor and an NMOS transistor each having a single threshold voltage, i.e., an intermediate threshold voltage (normal Vt), as shown inFIGS. 3aand3b.

Operation of the clock gating circuit ofFIG. 2will now be described.

When the clock signal CP is high and the inverted clock signal CPb is low, the transmission gate100is turned on and the feedback transmission gate140is turned off.

In this case, when the enable signal EN is high, the output signal passing through the first inverter110and the third inverter120becomes high and is input to the AND gate150. The clock signal CP at a high level is also input to the AND gate150. Accordingly, the gated clock GCLK becomes high to turn the targeted logic circuit170on.

On the other hand, when the enable signal EN is low, the output signal passing through the first inverter110and the third inverter120becomes low and is input to the AND gate150. The clock signal CP at a high level is also input to the AND gate150. Accordingly, the gated clock GCLK becomes low to turn the targeted logic circuit170off and block the clock.

When the clock signal CP is low and the inverted clock signal CPb is high, the transmission gate100is turned off and the feedback transmission gate140is turned on. Accordingly, the clock gating circuit enters a standby state and retains a previous data state in the feedback circuit.

Although a conventional clock gating circuit comprising a single threshold voltage can block the clock when a specific targeted circuit is not active, it is difficult to implement a high-performance and low-power circuit due to leakage current in a scaled-down device.

SUMMARY OF THE INVENTION

The present invention relates to a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The present invention is directed to a low-power clock gating circuit comprising a latch circuit and an AND gate circuit configured by the MTCMOS technique, in which power consumption caused by leakage current is reduced in a sleep mode, and supply of a clock to a targeted logic circuit is prevented in an active mode.

As described above, a conventional clock gating circuit using single threshold voltage devices cannot both block a clock and reduce power consumption caused by leakage current. To solve this problem, the present invention provides a low-power clock gating circuit including a latch circuit and an AND gate using an MTCMOS technique. The present invention is directed to a clock gating circuit which retains data without leakage current in a sleep mode, reduces power consumption caused by leakage current, and prevents a clock from being supplied to an unused targeted logic circuit in an active mode for reduction of power consumption in the targeted logic circuit.

One aspect of the present invention provides a clock gating circuit including a first inverter, a second inverter, an AND gate, a power terminal, a data terminal, a clock terminal, a sleep control terminal, and an output terminal, the clock gating circuit comprising: PMOS transistors electrically connected between the power terminal and the first inverter, between the power terminal and the second inverter, and between the power terminal and the AND gate and controlled by a sleep control signal applied via the sleep control terminal, each PMOS transistor having a high threshold voltage; and NMOS transistors electrically connected between a ground and the first inverter, between the ground and the second inverter, and between the ground and the AND gate and controlled by the sleep control signal, each NMOS transistor having a high threshold voltage.

Preferably, the sleep control signal comprises a sleep signal and an inverted sleep signal.

Each of the first inverter and the second inverter comprises a PMOS transistor having a low threshold voltage and an NMOS transistor having a low threshold voltage.

The AND gate comprises a PMOS transistor having a low threshold voltage and an NMOS transistor having a low threshold voltage.

The clock gating circuit further comprises a transfer gate connected between the data terminal and the first signal inverting circuit for transferring the data signal input via the data terminal to the first signal inverting circuit under control of a clock signal.

The clock gating circuit further comprises a feedback transfer gate for inverting an output signal of the first signal inverting circuit and transferring the inverted signal back to the first signal inverting circuit under control of the clock signal.

Another aspect of the present invention provides a clock gating circuit comprising: a first signal inverting circuit for inverting a data signal through a first inverter and outputting an inverted signal under control of a sleep control signal; a second signal inverting circuit for inverting the output signal of the first signal inverting circuit through a second inverter and outputting an inverted signal under control of the sleep control signal; and an AND gate circuit for receiving the output signal of the second signal inverting circuit and a clock signal and outputting a gated signal under control of the sleep control signal.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention, however, may be changed into several other forms, and the scope of the present invention should not be construed to be limited to the following embodiments. The embodiments of the present invention are intended to more entirely explain the present invention to those skilled in the art.

In general, transistors include transistors having a low threshold voltage and transistors having a high threshold voltage. 130 nm transistors operating at 1.2V have a low threshold voltage of about 0.24V and a high threshold voltage of about 0.44V. In the description below, a signal inverting circuit may be simply referred to as an inverting circuit.

FIG. 4illustrates a clock gating circuit using an MTCMOS technique according to the present invention,FIG. 5aillustrates a transmission gate circuit comprising low threshold voltage devices according to the present invention,FIG. 5billustrates a transmission gate circuit comprising high threshold voltage devices according to the present invention, andFIGS. 6ato6cillustrate individual circuits in an MTCMOS clock gating circuit shown inFIG. 4.

Referring toFIG. 4, the MTCMOS clock gating circuit450comprises a first signal inverting circuit400including: a first inverter402for inverting and outputting an enable signal EN under control of a sleep signal SP and an inverted sleep signal SPb; a transmission gate410for transferring an output signal of the first signal inverting circuit400under control of a clock signal CP, the transmission gate410having an equivalent circuit as shown inFIG. 5a; a second inverter422for outputting an enable signal from the transmission gate410under control of a sleep control signal SLP; an AND gate444for receiving an output signal of the second inverter422; and a feedback circuit430including a feedback transmission gate434for feeding back an output signal of the second inverter422to retain data in a sleep mode, the feedback transmission gate434having an equivalent circuit as shown inFIG. 5b.

The first signal inverting circuit400includes: the first inverter402for receiving and inverting the enable signal EN; a first PMOS transistor G1having a source connected to a power terminal, a gate for receiving the sleep signal SP, and a drain connected to the first inverter402; and a first NMOS transistor G2having a drain connected to the first inverter402, a gate for receiving an inverted sleep signal SPb, and a source connected to a ground.

Here, the first inverter402consists of a PMOS transistor and an NMOS transistor each having a low threshold voltage, which allows the enable signal to be transferred along the shortest path.

The first signal inverting circuit400is represented by an equivalent circuit as shown inFIG. 6a.

Referring toFIG. 6a, the first PMOS transistor G1and the first NMOS transistor G2have high threshold voltages, and the first inverter402consists of the PMOS transistor and the NMOS transistor each having a low threshold voltage.

The transmission gate410transfers the enable signal from the first signal inverting circuit400to the second signal inverting circuit420under control of the clock signal CP and the inverted clock signal CPb. The transmission gate410consists of a PMOS transistor and an NMOS transistor each having a low threshold voltage.

The second signal inverting circuit420is represented by an equivalent circuit as shown inFIG. 6b.

Referring toFIG. 6b, the second signal inverting circuit420includes: the second inverter422for receiving and outputting the output signal of the transmission gate410under control of the sleep signal SP and the inverted sleep signal SPb; a second PMOS transistor G3having a source connected to the power terminal, a gate for receiving the sleep signal SP, and a drain connected to the second inverter422; and a second NMOS transistor G4having a drain connected to the second inverter422, a gate for receiving the inverted sleep signal SPb, and a source connected to a ground.

The second signal inverting circuit420has the equivalent circuit as shown inFIG. 6bwhen the NMOS transistor G6inFIG. 4is included. The second PMOS transistor G3and the second NMOS transistor G4have high threshold voltages, and the second inverter422consists of a PMOS transistor and an NMOS transistor each having a low threshold voltage.

The feedback circuit430enables data to be retained when the MTCMOS latch circuit is in a sleep mode. The feedback circuit430consists of a PMOS transistor and an NMOS transistor having a high threshold voltage and small leakage current.

The feedback circuit430includes: a third inverter432for inverting and outputting an output signal of the second signal inverting circuit420; a third PMOS transistor G5having a source for receiving the output signal of the second signal inverting circuit420and a gate for receiving an output signal of the third inverter432; a third NMOS transistor G6having a drain connected to the second inverter422of the second signal inverting circuit420, a gate for receiving an output signal of the third inverter432, and a source connected to the ground; and a feedback transmission gate434for receiving the output signal of the third inverter432and transferring the same to the second signal inverting circuit420under control of the clock signal CP and the inverted clock signal CPb.

Each of the third inverter432and the feedback transmission gate434consists of a PMOS transistor and an NMOS transistor each having a high threshold voltage.

The AND gate circuit440has an equivalent circuit as shown inFIG. 6c. The AND gate circuit440includes the AND gate444for receiving the output signal of the second inverter422and the clock signal CP and outputting a gated signal GCLK to a targeted logic circuit460under control of the sleep signal SP and the inverted sleep signal SPb.

Referring toFIG. 6c, the sleep signal SP and the inverted sleep signal SPb are received at a PMOS transistor and an NMOS transistor each having a high threshold voltage, and the AND gate444consists of PMOS transistors and NMOS transistors each having a low threshold voltage.

Operation of the MTCMOS clock gating circuit450having the above-described configuration will now be described.

The MTCMOS clock gating circuit operates in an active mode when the sleep signal SP is low and the inverted sleep signal SPb is high and in a sleep mode when the sleep signal SP is high and the inverted sleep signal SPb is low.

First, operation of the MTCMOS clock gating circuit in an active mode will be described.

When the sleep signal SP is low, the first, second and fourth PMOS transistors G1, G3and G7and the first, second and fourth NMOS transistors G2, G4and G8each having a high threshold voltage are all turned on, and the inverted sleep signal SPb becomes high.

In this state, when the clock signal CP is high, the inverted clock signal CPb becomes low, such that the transmission gate410is turned on and the feedback transmission gate434is turned off.

Accordingly, the enable signal EN is output via the first signal inverting circuit400, the transmission gate410, the second signal inverting circuit420, and the AND gate circuit440.

When the sleep signal SP is low, the clock signal CP is low, and the inverted clock signal CPb is high, the transmission gate410is turned off and the feedback transmission gate434is turned on, such that a previous enable signal EN is output.

Thus, in the active mode, the MTCMOS clock gating circuit continues to output the enable signal EN as the clock signal CP is high/low.

When the clock signal CP is high and, at this time, the enable signal EN from the targeted logic circuit460is high, the gated signal GCLK from the AND gate circuit440becomes high and this high clock is transferred to the targeted logic circuit. However, when the clock signal CP is high and, at this time, the enable signal EN from the targeted logic circuit460is low, the gated signal GCLK from the AND gate circuit440becomes low and this low clock is transferred to the targeted logic circuit, thereby preventing the clock from being transferred to a undesired device.

When the clock signal CP is low, the MTCMOS clock gating circuit retains a previous signal in the feedback circuit430irrespective of the enable signal EN from the targeted logic circuit460, and remains in a standby state.

Thus, in the active mode, the MTCMOS clock gating circuit transfers a signal at a high speed because all of the first inverter402of the first signal inverting circuit400, the transmission gate410, the second inverter422of the second signal inverting circuit420, and the AND gate444of the AND gate circuit440consist of a PMOS transistor and an NMOS transistor each having a low threshold voltage.

Next, operation of the MTCMOS clock gating circuit in the sleep mode will be described.

When the sleep signal SP is high, the MTCMOS clock gating circuit operates in the sleep mode.

If the sleep signal SP is high, i.e., when the sleep signal SP is high and the inverted sleep signal SPb is low, the first, second and fourth PMOS transistors G1, G3and G7and the first, second and fourth NMOS transistors G2, G4and G8each having a high threshold voltage are turned off. Accordingly, the enable signal EN is retained in the feedback circuit430.

That is, if the output of the second inverter422is low, a high signal is applied to the gate of the third NMOS transistor G6via the third inverter432to turn the third NMOS transistor G6on, and also applied to the gate of the third PMOS transistor G5to turn the third PMOS transistor G5off.

In this case, when the clock signal CP is low, the feedback transmission gate434is turned on, a high signal is applied to the second inverter422, which outputs a low signal. In this case, the output of the second inverter422remains low because it is connected to the ground via the NMOS transistor in the second inverter422and the third NMOS transistor G6, as shown inFIG. 6b.

If the output of the second inverter422is high, a low signal is applied to the gate of the third NMOS transistor G6via the third inverter432to turn the third NMOS transistor G6off, such that the second inverter422does not operate. The low signal is also applied to the gate of the PMOS transistor G5via the second inverter432to turn the PMOS transistor G5on, and the output of the second inverter422remains high as the source and the drain of the third PMOS transistor G5are high.

Thus, because the feedback circuit430is intended to retain data, it consists of a PMOS transistor and an NMOS transistor having a high threshold voltage and accordingly small leakage current. This allows the feedback circuit430to be designed with a minimum size.

According to the present invention, the clock gating circuit using the MTCMOS technique can minimize power consumption caused by leakage current in nano-level devices and contribute to high-speed operation of logic circuits by using low threshold voltage devices. Furthermore, the clock gating circuit prevents the clock from being supplied to an unused device in response to a state signal, thereby reducing power consumption in the targeted logic circuit. The clock gating circuit using the MTCMOS technique according to the present invention may be widely utilized for a bus interface of a slave device in a system having a pipeline bus structure, and may also be applied to mobile devices for considerable reduction of power consumption.