Magnetic memory device having shared source line and bit line

A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the technical field of semiconductor memory, in particular to a magnetoresistive random access memory (MRAM) with a shared source line (SL) and a shared bit line (BL).

2. Description of the Prior Art

As known in the art, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is a non-volatile memory that has come under much scrutiny recently in the industry, which has several advantages over the conventional magnetoresistive random access memory. For example, these advantages include higher endurance, lower-power consumption, and faster operating speed.

In a magneto-tunnel junction (MTJ) including two ferromagnetic layers having a thin insulating layer therebetween, the tunnel resistance varies depending on the relative directions of magnetization of the two ferromagnetic layers. A magnetoresistive random access memory may be a semiconductor device where magnetic elements (MTJ elements) having MTJs utilizing a tunnel magneto resistance (TMR) effect are arranged in a matrix form as a memory cell.

In conventional designs, the source lines (SL) of the MTJ bit cell arrays are arranged to be parallel to the bit line (BL). However, in conventional designs there is no direct and parallel overlap between the source line and bit line due to via and metal spacing rules. Therefore, the minimum bit cell size of conventional designs cannot be reduced or minimized as a result of metal and via spacing rules.

Because the memory includes hundreds of thousands of cells, even small area savings in each cell can result in major advantages in density of the memory. Accordingly, it is highly desirable to provide apparatus and a method of improving the density of MRAM cells in a memory array by reducing the area of individual MRAM cells.

SUMMARY OF THE INVENTION

The present invention provides an improved magnetic memory device having a shared source line (SL) and a shared bit line (BL), which can solve the shortcomings of the prior art.

One aspect of the invention provides a memory device including a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction, wherein the main source line is electrically connected to the source doped region via the source line extension; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region.

According to some embodiments, the data storage element comprises a magnetic tunneling junction (MTJ) element.

According to some embodiments, the MTJ element comprises a bottom electrode.

According to some embodiments, the memory device further includes a landing pad disposed directly under the MTJ element.

According to some embodiments, the memory device further includes a drain contact electrically connecting the landing pad to the drain doped region.

According to some embodiments, the bottom electrode is electrically connected to the landing pad.

According to some embodiments, the MTJ element comprises a top electrode.

According to some embodiments, the top electrode is electrically connected to a bit line.

According to some embodiments, the bit line extends along the first direction.

According to some embodiments, the memory device further includes a first dielectric layer disposed on the substrate, wherein the landing pad is disposed in the first dielectric layer and is situated in a first horizontal plane; and a second dielectric layer covering the first dielectric layer and the landing pad, wherein the MTJ element is disposed in the second dielectric layer, and wherein the main source line and the source line extension are situated in a second horizontal plane.

According to some embodiments, the second horizontal plane is lower than the first horizontal plane.

Another aspect of the invention provides a magnetic memory device including a substrate; an active area extending along a first direction on the substrate; an isolation region disposed in the substrate and adjacent to the active area; a plurality of gate lines traversing the active area and the isolation region along a second direction that is not parallel to the first direction, wherein the plurality of gate lines comprises a first gate line, a second gate line, and a third gate line between the first gate line and the second gate line; a first source doped region in the active area and on one side of the first gate line; a first drain doped region in the active area and between the first gate line and the third gate line; a second source doped region in the active area and on one side of the second gate line; a second drain doped region in the active area and between the second gate line and the third gate line; a main source line extending along the first direction overlying the isolation region; a first source line extension and a second source line extension coupled to the main source line and extending along the second direction, wherein the man source line is electrically connected to the first source doped region and the second source doped region via the first source line extension and the second source line extension, respectively; a first magnetic tunneling junction (MTJ) element electrically coupled to the first drain doped region; and a second MTJ element electrically coupled to the second drain doped region.

According to some embodiments, the first MTJ element and the second MTJ element are aligned along the first direction.

According to some embodiments, the first MTJ element and the second MTJ element are not aligned along the first direction.

According to some embodiments, the first MTJ element comprises a first bottom electrode and the second MTJ element comprises a second bottom electrode.

According to some embodiments, the magnetic memory device further includes a first landing pad and a second landing pad disposed directly under first MTJ element and the second MTJ element, respectively.

According to some embodiments, the magnetic memory device further includes a first drain contact electrically connecting the first landing pad to the first drain doped region; and a second drain contact electrically connecting the second landing pad to the second drain doped region.

According to some embodiments, the first bottom electrode is electrically connected to the first landing pad and the second bottom electrode is electrically connected to the second landing pad.

According to some embodiments, the first MTJ element comprises a first top electrode and the second MTJ element comprises a second top electrode.

According to some embodiments, the first top electrode and the second top electrode are electrically connected to a bit line.

According to some embodiments, the bit line extends along the first direction.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer toFIG. 1andFIG. 2, whereinFIG. 1is a schematic diagram of a partial layout of a magnetic memory device1according to an embodiment of the invention, andFIG. 2is a cross-sectional view taken along line I-I′ inFIG. 1. According to an embodiment of the present invention, as shown inFIGS. 1 and 2, the magnetic memory device1includes a substrate10, for example, a P-type silicon substrate, but it is not limited thereto. According to an embodiment of the present invention, a P-well (PW) may be provided in the substrate10, but is not limited thereto. The substrate10has a memory array area MA. In the memory array area MA on the substrate10, memory cells100arranged in an array are provided. On the substrate10, there are a plurality of strip-shaped and mutually parallel active areas101(FIG. 1only shows one active area101). The strip-shaped active areas101are isolated from one another by the strip-shaped shallow trench isolation (STI) region102(FIG. 1only shows one STI region102). According to an embodiment of the present invention, the strip-shaped active area101and the strip-shaped STI area102both extend along a first direction (for example, the reference X-axis direction).

According to an embodiment of the present invention, there are a plurality of gate lines or word lines on the substrate10(only two word lines WL1and WL2are shown inFIG. 1), which traverse the active area101and extend in a second direction (for example, the reference Y-axis direction) that is not parallel to the first direction. For example, the first direction is orthogonal to the second direction. According to an embodiment of the present invention, the word lines WL1and WL2may be polysilicon word lines, but not limited thereto. According to an embodiment of the present invention, the magnetic memory device1further includes a selection transistor200located at a position where the word line WL1crosses the active area101, for example. According to an embodiment of the present invention, the selection transistor200may include a gate a drain doped region D, and a source doped region S. For example, the overlapping portion of the word line WL1and the active area101is the gate G of the selection transistor200.

According to an embodiment of the present invention, the drain doped region D and the source doped region S are formed in the active areas101on two opposite sides of the gate respectively. For example, the drain doped region D and the source doped region S may be N-type doped regions or P-type doped regions. The source doped region S is provided on the first side of the gate line WL1. The drain doped region D is disposed on the second side of the gate line WL1opposite to the first side.

As shown inFIG. 2, dielectric layers310-340are provided on the substrate10, but not limited thereto. For example, the dielectric layer310may be an ultra-low dielectric constant (ultra-low k) material layer. For example, the ultra-low k material layer may be a carbon-containing silicon oxide (SiOC) layer having a dielectric constant ranging from 1 to 2.5, but is not limited thereto. According to an embodiment of the present invention, the dielectric layer310may be composed of a single layer of insulating material or multiple layers of insulating film. The dielectric layer310covers the memory array area MA and the selection transistor200. According to an embodiment of the invention, the dielectric layer320covers the dielectric layer310. For example, the dielectric layer320may include a nitrogen-doped silicon carbide (NDC) layer321, a silicon oxide layer322on the NDC layer321, and an ultra-low k material layer323on the silicon oxide layer322. For example, the silicon oxide layer322may be a TEOS silicon oxide layer. The TEOS silicon oxide layer refers to a silicon oxide layer deposited using tetraethoxysilane (TEOS) as a reactive gas.

According to an embodiment of the present invention, a dielectric layer330and a dielectric layer340may be formed on the dielectric layer320. The dielectric layer330may include, for example, a NDC layer331and an ultra-low k material layer332. The dielectric layer340may include, for example, a NDC layer341and an ultra-low k material layer342.

As shown inFIG. 1andFIG. 2, the magnetic memory device1may further include a landing pad MP1. The landing pad MP1overlaps the drain doped region D of the selection transistor200. In addition, the landing pad MP1may partially overlap the word line WL1. According to an embodiment of the invention, the landing pad MP1is disposed in the dielectric layer310.

According to an embodiment of the present invention, as shown inFIG. 2, the landing pad MP1is located at a first horizontal plane and is electrically connected to the drain doped region D of the selection transistor200. According to an embodiment of the invention, the landing pad MP1is located in a first metal (M1) layer. According to an embodiment of the invention, the first metal layer is a damascene copper layer. The landing pad MP1may be electrically coupled to the drain doped region D of the selection transistor200via a contact plug (drain contact) C1. For example, the contact plug C1may be a tungsten metal plug. According to an embodiment of the present invention, between the landing pad MP1and the contact plug C1, a contact pad CP1may be further provided. The contact pad CP1may be a tungsten metal contact pad, and may be formed in the zeroth metal (M0) layer.

The magnetic memory device1further includes a data storage element, for example, cylindrical memory stack MS1. The cylindrical memory stack MS1may be arranged in an array, and the cylindrical memory stack MS1is aligned with the landing pad MP1. According to an embodiment of the present invention,FIG. 2illustrates the via plug VP1disposed in the silicon oxide layer322and the NDC layer321. According to an embodiment of the present invention,FIG. 2further illustrates a cylindrical memory stack MS1provided in the second dielectric layer320. According to an embodiment of the present invention, the cylindrical memory stack MS1may include a bottom electrode BE1electrically coupled to the landing pad MP1through the via plug VP1, and a top electrode TE1electrically coupled to the bit line BL1in the third dielectric layer330through the via V1.

According to an embodiment of the present invention, as shown inFIG. 2, the via plug VP1is electrically connected to the bottom electrode BE1and the landing pad MP1. According to an embodiment of the present invention, the via plug VP1may be a tungsten via plug, but is not limited thereto. According to an embodiment of the present invention, the bit line BL1and the via V1may be a dual damascene copper metal structure formed in the third dielectric layer330.

As shown inFIG. 2, the cylindrical memory stack MS1may include a magnetic tunnel junction element MTJ1. According to an embodiment of the present invention, a spacer SP1may be provided on the sidewall of the cylindrical memory stack MS1. According to an embodiment of the present invention, for example, the spacer SP1may be a silicon nitride spacer, but is not limited thereto.

According to an embodiment of the present invention, the bottom electrode BE1may include, for example, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), etc. The multi-layer structure of the magnetic tunnel junction element MTJ1is a well-known technique, so its details are omitted. For example, the magnetic tunnel junction element MTJ1may include a fixed layer, a free layer, and a capping layer, but not limited thereto. The fixed layer may be made of antiferromagnetic (AFM) materials, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the direction of the magnetic moment of adjacent layers. The free layer may be composed of a ferromagnetic material, such as iron, cobalt, nickel or alloys thereof such as cobalt-iron-boron (CoFeB), but it is not limited thereto. According to an embodiment of the present invention, for example, the top electrode TE1may include a ruthenium (Ru) metal layer and a tantalum (Ta) metal layer, but is not limited thereto.

FIG. 1illustrates a bit line BL1extending along the reference X axis. According to an embodiment of the present invention, as shown inFIG. 1, the bit line BL1partially overlaps the underlying strip-shaped active area101. According to an embodiment of the present invention, the bit line BL1may be formed in an upper metal interconnection, for example, a second metal (M2) layer or a third metal (M3) layer.

As shown inFIG. 1andFIG. 2, a main source line SLM1extending along the reference X axis direction and a source line extension SLE1extending along the reference Y axis direction are provided on the substrate10. The source line extension SLE1is coupled to the main source line SLM1. The extension direction of the source line extension SLE1is parallel to the word line WL1and orthogonal to the main source line SLM1and the bit line BL1. As shown inFIG. 1, the source line extension SLE1is disposed between the word lines WL1and WL2. As shown inFIG. 2, the illustrated source line extension SLE1is disposed in the first dielectric layer310. The main source line SLM1is electrically connected to the source doped region S via the source line extension SLE1.

According to an embodiment of the present invention, the illustrated main source line SLM1and source line extension SLE1may be located at a second horizontal plane. According to an embodiment of the present invention, for example, the second horizontal plane may be lower than the first horizontal plane. In other words, the source line extension SLE1as illustrated inFIG. 2is lower than the landing pad MP1. According to an embodiment of the present invention, the source line extension SLE1illustrated inFIG. 2may be located in the M0 metal layer. According to an embodiment of the present invention, the M0 metal layer may be a tungsten metal layer.

Please refer toFIG. 3andFIG. 4.FIG. 3is a schematic diagram showing a partial layout of a magnetic memory device1aaccording to another embodiment of the invention.FIG. 4is a cross-sectional view taken along line II-II′ inFIG. 3. According to an embodiment of the present invention, as shown inFIG. 3andFIG. 4, the magnetic memory device1aincludes a substrate10, for example, a P-type silicon substrate, but is not limited thereto. According to an embodiment of the present invention, a P-well (PW) may be provided in the substrate10, but is not limited thereto. The substrate10has a memory array area MA. In the memory array area MA on the substrate10, a plurality of memory cells100a,100barranged in an array are provided. The substrate10comprises a plurality of strip-shaped and mutually parallel active areas101(only one active area101is shown inFIG. 3), which are isolated from one another by STI regions102(only one STI region102is shown inFIG. 3). According to an embodiment of the present invention, the strip-shaped active area101and the strip-shaped STI region102both extend along a first direction (for example, the reference X-axis direction).

According to an embodiment of the present invention, gate lines or word lines are disposed on the substrate10(only three word lines WL1, WL2, WL3are shown inFIG. 3), traversing the active area101and extending along a second direction (for example, the reference Y-axis direction) not parallel to the first direction. For example, the first direction is orthogonal to the second direction. According to an embodiment of the present invention, the word lines WL1, WL2, and WL3may be polysilicon word lines, but not limited thereto. According to an embodiment of the present invention, the magnetic memory device1afurther includes selection transistors200aand200b. For example, the selection transistor200ais located at a position where the word line WL1crosses the active area101, and the selection transistor200bis located at a position where the word line WL3crosses the active area101.

According to an embodiment of the present invention, the selection transistor200amay include a gate G1, a drain doped region D1, and a source doped region S1. For example, the portion where the word line WL1overlaps the active area101is the gate G1of the selection transistor200a. According to an embodiment of the present invention, the selection transistor200bmay include a gate G2, a drain doped region D2, and a source doped region S2. For example, the portion where the word line WL3overlaps the active area101is the gate G2of the selection transistor200b.

According to an embodiment of the present invention, the drain doped region D1and the source doped region S1are formed in the active areas101on two sides of the gate G1. For example, the drain doped region D1and the source doped region S1may be N-type doped regions or P-type doped regions. The source doped region S1is disposed on the first side of the word line WL1. The drain doped region D1is disposed on the second side of the word line WL1opposite to the first side.

According to embodiments of the present invention, the drain doped region D2and the source doped region S2are formed in the active areas101on two sides of the gate G2. For example, the drain doped region D2and the source doped region S2may be N-type doped regions or P-type doped regions. The source doped region S2is disposed on the first side of the word line WL3. The drain doped region D2is disposed on the second side of the word line WL3opposite to the first side.

As shown inFIG. 4, dielectric layers310-340are provided on the substrate10, but not limited thereto. For example, the dielectric layer310may be an ultra-low k material layer. For example, the ultra-low k material layer may be a carbon-containing silicon oxide layer having a dielectric constant ranging from 1 to 2.5, but not limited thereto. According to an embodiment of the present invention, the dielectric layer310may be composed of a single layer of insulating material or multiple layers of insulating film. The dielectric layer310covers the memory array area MA and the selection transistors200aand200b. According to an embodiment of the invention, the dielectric layer320covers the dielectric layer310. For example, the dielectric layer320may include a NDC layer321, a silicon oxide layer322on the NDC layer321, and an ultra-low k material layer323on the silicon oxide layer322. For example, the silicon oxide layer322may be a TEOS silicon oxide layer. The TEOS silicon oxide layer refers to a silicon oxide layer deposited using tetraethoxysilane as a reactive gas.

According to an embodiment of the present invention, a dielectric layer330and a dielectric layer340may be formed on the dielectric layer320. The dielectric layer330may include, for example, a NDC layer331and an ultra-low k material layer332, The dielectric layer340may include, for example, a NDC layer341and an ultra-low k material layer342.

As shown inFIGS. 3 and 4, the magnetic memory device1amay further include landing pads MP1and MP2. The landing pad MP1overlaps the drain doped region D1of the selection transistor200a, and the landing pad MP2overlaps the drain doped region D2of the selection transistor200b. According to the embodiment of the invention, the landing pads MP1and MP2are disposed in the dielectric layer310.

According to an embodiment of the present invention, as shown inFIG. 4, the landing pad MP1is located at a first horizontal plane and is electrically connected to the drain doped region D1of the selection transistor200a, and the landing pad MP2is located at the first horizontal plane and is electrically connected to the drain doped region D2of the selection transistor200b. According to an embodiment of the invention, the landing pads MP1and MP2are located in the M1 metal layer. According to an embodiment of the invention, the M1 metal layer is a damascene copper layer. The landing pads MP1, MP2may be electrically coupled to the drain doped regions D1, D2of the transistors200a,200bvia contact plugs (drain contacts) C1, C2, respectively. For example, the contact plugs C1and C2may be tungsten metal plugs. According to the embodiment of the present invention, a contact pad CP1may be further provided between the landing pad MP1and the contact plug C1, and a contact pad CP2may be further provided between the landing pad MP2and the contact plug C2. The contact pads CP1and CP2may be tungsten metal contact pads, and may be formed in the M0 metal layer.

The magnetic memory device1afurther includes data storage elements, for example, cylindrical memory stacks MS1, MS2. The cylindrical memory stacks MS1, MS2can be arranged in an array. The cylindrical memory stack MS1is aligned with the landing pad MP1. The memory stack MS2is aligned with the landing pad MP2. According to an embodiment of the present invention,FIG. 4illustrates the via plugs VP1and VP2disposed in the silicon oxide layer322and the NDC layer321. According to an embodiment of the present invention,FIG. 2further illustrates cylindrical memory stacks MS1and MS2provided in the second dielectric layer320. According to an embodiment of the present invention, the cylindrical memory stack MS1may include a bottom electrode BE1electrically coupled to the landing pad MP1through the via plug VP1, and a top electrode TE1electrically coupled to the bit line BL1in the third dielectric layer330through the via V1. According to an embodiment of the present invention, the cylindrical memory stack MS2may include a bottom electrode BE2electrically coupled to the landing pad MP2through the via plug VP2, and a top electrode TE2electrically coupled to the bit line BL1in the third dielectric layer330through the via V2.

According to an embodiment of the present invention, as shown inFIG. 4, the via plug VP1is electrically connected to the bottom electrode BE1and the landing pad MP1, and the via plug VP2is electrically connected to the bottom electrode BE2and the landing pad MP2. According to an embodiment of the present invention, the via plug VP2may be a tungsten metal via plug, but is not limited thereto. According to an embodiment of the present invention, the bit line BL1and the vias V1and V2may be composed of a dual damascene copper metal structure formed in the third dielectric layer330.

As shown inFIG. 3, the cylindrical memory stacks MS1, MS2may respectively include a magnetic tunnel junction element MTJ1, MTJ2. The magnetic tunnel junction elements MTJ1and MTJ2are aligned along the first direction. In some embodiments, the magnetic tunnel junction elements MTJ1and MTJ2may not be aligned along the first direction. According to an embodiment of the present invention, a spacer SP1may be provided on the sidewall of the cylindrical memory stack MS1, and a spacer SP2may be provided on the sidewall of the cylindrical memory stack MS2. According to an embodiment of the present invention, for example, the spacers SP1and SP2may be silicon nitride spacers, but not limited thereto.

According to embodiments of the present invention, the bottom electrodes BE1, BE2may include, for example, but not limited to, Ta, Pt, Cu, Au, Al, or the like. The multi-layer structure of the magnetic tunnel junction elements MTJ1and MTJ2is a well-known technique, so the details are omitted. For example, the magnetic tunnel junction element MTJ1may include a fixed layer, a free layer, and a capping layer, but not limited thereto. The fixed layer may be composed of antiferromagnetic materials, such as iron manganese, platinum manganese, iridium manganese, nickel oxide, etc., to fix or limit the direction of the magnetic moment of the adjacent layers. The free layer may be composed of a ferromagnetic material, such as iron, cobalt, nickel or alloys thereof such as cobalt iron boron, but not limited thereto. According to an embodiment of the present invention, for example, the top electrodes TE1and TE2may include a ruthenium metal layer and a tantalum metal layer, but not limited thereto.

FIG. 3illustrates a bit line BL1extending along the reference X axis. According to an embodiment of the present invention, as shown inFIG. 3, the bit line BL1partially overlaps the strip-shaped active area101below. According to an embodiment of the present invention, the bit line BL1may be formed in an upper metal interconnection, for example, the M2 metal layer or the M3 metal layer.

As shown inFIG. 3andFIG. 4, a main source line SLM1extending along the reference X-axis direction directly above the STI region102and source line extensions SLE1, SLE2extending along the reference Y-axis direction are provided on the substrate10. The source line extensions SLE1, SLE2are coupled to the main source line SLM1. The extension directions of the source line extensions SLE1and SLE2are parallel to the word line WL1and orthogonal to the main source line SLM1and the bit line BL1. As shown inFIG. 3, the source line extension SLE1is provided on one side of the word line WL1. As shown inFIG. 4, the illustrated source line extensions SLE1and SLE2are provided in the first dielectric layer310. The main source line SLM1is electrically connected to the source doped regions S1, S2via source line extensions SLE1, SLE2.

According to an embodiment of the present invention, the illustrated main source line SLM1and source line extensions SLE1, SLE2may be located at a second horizontal plane. According to an embodiment of the present invention, for example, the second horizontal plane may be lower than the first horizontal plane. In other words, the source line extensions SLE1, SLE2as illustrated inFIG. 4are lower than the landing pads MP1, MP2. According to an embodiment of the present invention, the source line extensions SLE1and SLE2illustrated inFIG. 4may be located in the M0 metal layer. According to an embodiment of the present invention, the M0 metal layer may be a tungsten metal layer.

Please refer toFIG. 5andFIG. 6.FIG. 5is a schematic diagram of a partial layout of a magnetic memory device1caccording to another embodiment of the present invention, illustrating part of the shared source lines.FIG. 6is a layout diagram showing part of bit lines of the magnetic memory device1cinFIG. 5.

As shown inFIG. 5andFIG. 6, likewise, strip-shaped and mutually parallel active areas101a,101bare provided in the memory array area MA, and are separated from one another by strip-shaped STI regions102. Two adjacent active areas101aare grouped into the first group, and two adjacent active areas101bare grouped into the second group. Therefore, there are multiple groups of active areas in the memory array area MA. According to an embodiment of the present invention, the strip-shaped active areas101a,101band the strip-shaped STI region102both extend along the first direction (for example, the reference X-axis direction).

According to an embodiment of the present invention, the magnetic memory device1cfurther includes multiple gate lines or word lines WL1˜WL7, traversing the active areas101a,101band extending along the second direction (for example, reference Y-axis direction) that is not parallel to the first direction. For example, the first direction is orthogonal to the second direction. According to an embodiment of the present invention, the word lines WL1˜WL7may be polysilicon word lines, but not limited thereto.

At predetermined positions on the active areas101aand101b, a landing pad MP at a first horizontal plane and a data storage element containing a magnetic tunnel junction element MTJ (as described inFIG. 2) are provided and electrically connected to the corresponding drain doped region D of the selection transistor200. Above the active area101aof the first group, the magnetic memory device1cfurther includes a main source line SLM1extending along the reference X-axis direction, and source line extensions SLE1a˜SLE1cextending along the reference Y-axis direction. The source line extensions SLE1a˜SLE1care coupled to the main source line SLM1. The extension directions of the source line extensions SLE1a˜SLE1care parallel to the word line WL1˜WL7and orthogonal to the main source line SLM1. The main source line SLM1is electrically connected to the source doped regions S of the selection transistors200provided on the active area101aof the first group via source line extensions SLE1a˜SLE1c.

Similarly, above the active area101bof the second group, the magnetic memory device1cfurther includes a main source line SLM2extending along the reference X-axis direction, and source line extensions SLE2a˜SLE2cextending along the reference Y-axis direction. The source line extensions SLE2a˜SLE2care coupled to the main source line SLM2. The extension directions of the source line extensions SLE2a˜SLE2care parallel to the word line WL1˜WL7and orthogonal to the main source line SLM2. The main source line SLM2is electrically connected to the source doped regions S of the selection transistors200provided on the active area101bof the second group via source line extensions SLE2a˜SLE2c.

According to an embodiment of the present invention, the illustrated main source lines SLM1, SLM2and source line extensions SLE1a˜SLE1c, SLE2a˜SLE2, may be located at the second horizontal plane. According to an embodiment of the present invention, for example, the second horizontal plane may be lower than the first horizontal plane where the landing pad MP is located. In other words, the illustrated main source lines SLM1, SLM2and source line extensions SLE1a˜SLE1c, SLE2a˜SLE2care lower than the landing pad MP. According to embodiments of the present invention, the illustrated main source lines SLM1, SLM2and source line extensions SLE1a˜SLE1c, SLE2a˜SLE2cmay be located in the M0 metal layer. According to an embodiment of the present invention, the M0 metal layer may be a tungsten metal layer.

As shown inFIG. 6, the bit lines BL1˜BL3of the magnetic memory device1care disposed between different groups of active areas and extend along the first direction, and the bit lines BL1˜BL3partially overlap the underlying strip-shaped active areas101aand101b. For example, the bit line BL2is disposed between the active area101aof the first group and the active area101bof the second group, and the magnetic tunnel junction elements MTJ provided on the active area101aand the active area101bare electrically connected to the bit line BL2. The bit lines BL1˜BL3may be formed in the upper metal interconnection, for example, the M2 metal layer or the M3 metal layer. By using the above-mentioned shared source line and shared bit line configuration, a wider pitch P1between the source line and the landing pad can be released (as shown inFIG. 5), and a wider bit line pitch P2can be released (as shown inFIG. 6).

Please refer toFIG. 7andFIG. 8.FIG. 7is a partial layout diagram of a magnetic memory device1daccording to another embodiment of the present invention, illustrating part of the shared source lines.FIG. 8is a layout diagram showing part of bit lines of the magnetic memory device1dinFIG. 7.

As shown inFIG. 7andFIG. 8, four strip-shaped and mutually parallel active areas101aare exemplified in the memory array area MA, and are separated from each other by the strip-shaped STI region102. In the array area MA, every four adjacent active areas101aare divided into a group. Therefore, there can be multiple groups of active areas in the memory array area MA. According to an embodiment of the present invention, the strip-shaped active area101aand the strip-shaped STI area102both extend along the first direction (for example, the reference X-axis direction).

InFIG. 7, four adjacent active areas101ain the same group share a main source line SLM1extending along the reference X-axis direction. The main source line SLM1is electrically connected the source doped region S of each selection transistor200provided on the active area101aof the group via source line extensions SLE1a˜SLE1cextending along the reference Y-axis direction. InFIG. 8, the magnetic memory device1dincludes bit lines BL1˜BL4extending along the first direction. The bit lines BL1, BL4are disposed between different groups of active areas, and the bit lines BL1, BL4may partially overlap with the strip-shaped active area101a. For example, the bit line BL2is disposed on the active area101a, and the magnetic tunnel junction elements MTJ disposed on the active area101aare all electrically connected to the bit line BL2. The bit lines BL1˜BL4may be formed in the upper metal interconnection, for example, the M2 metal layer or the M3 metal layer.

Please refer toFIG. 9AtoFIG. 9C.FIG. 9Aillustrates the active areas divided in three groups in the memory array area MA.FIG. 9Billustrates the layout of the shared source line with respect to the three groups of active areas inFIG. 9A.FIG. 9Cillustrates the layout of the bit lines with respect to the three groups of active areas inFIG. 9A. InFIG. 9A, the three groups of active areas GP1˜GP3are indicated by dotted lines, and each group includes n active areas101ato101cextending in the first direction (inFIG. 9A, n=6). InFIG. 9B, it is shown that the active areas in the first group GP1share a main source line SLM1extending along the reference X axis direction and a source line extension SLE1extending along the reference Y axis direction. The active areas in the second group GP2shares the main source line SLM2extending along the reference X-axis direction and a source line extension SLE2extending along the reference Y-axis direction. The active areas in the third group GP3share a main source line SLM3extending along the reference X-axis direction and a source line extension SLE3extending along the reference Y-axis direction. InFIG. 9C, a plurality of bit lines BL1to BL19extending along the reference X-axis direction are shown, where BL1, BL7, BL13, and BL19are bit lines shared between different groups.

Please refer toFIG. 10, which is an equivalent circuit diagram of a single transistor single memory cell (1T1M) memory array MA1according to another embodiment of the present invention. As shown inFIG. 10, the memory array MA1includes a plurality of selection transistors200, which are respectively arranged in a plurality of rows R1˜Rn, where n may be an integer ranging between 2˜8, for example, n=6, but is not limited thereto. The selection transistor200and the data storage element including the magnetic tunnel junction element MTJ together constitute a 1T1M configuration.FIG. 10shows at least one group of active areas GP1for illustration purposes. The active areas in the group GP1share a main source line SLM1extending along the reference X axis direction and a source line extension SLE1extending along the reference Y axis direction. The group of active areas GP1is provided with a plurality of bit lines BL1˜BLnextending along the reference X-axis direction, where BL1and BLnare bit lines shared between different groups in the Y-axis direction.

The following illustrates an example of the read and write operation method of the 1T1M memory array MA1ofFIG. 10. Taking the reading of the magnetic tunnel junction element MTJ12inFIG. 10as an example, the reading operation conditions include: biasing the word line WL1to VDDand biasing the bit line BL2to a lower voltage, for example, 50 mV. The main source line SLM1and the source line extension SLE1are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ12inFIG. 10to a parallel state (0 state), the writing operation conditions include: biasing the word line WL1to VDDand biasing the bit line BL2to VCC. The main source line SLM1and the source line extension SLE1are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ12inFIG. 10to the anti-parallel state (1 state), the writing operation conditions include: biasing the word line WL1to VDD, grounding the bit line BL2, and biasing the main source line SLM1and the source line extension SLE1to VCC. The other word lines are grounded. The other bit lines and main source lines are both floating.

Please refer toFIG. 11, which is an equivalent circuit diagram of a dual transistor single memory cell (2T1M) memory array MA2according to another embodiment of the present invention. As shown inFIG. 11, the memory array MA2includes a plurality of selection transistors200aand200b, which are respectively arranged in a plurality of rows R1˜Rn, where n may be an integer ranging between 2˜8, for example, n=6, but is not limited thereto. The two selection transistors200a,200band the data storage element containing the magnetic tunnel junction element MTJ together constitute a 2T1M configuration.FIG. 11shows at least one group of active areas GP1for illustration purposes. The active areas in the group GP1share a main source line SLM1extending along the reference X-axis direction and a source line extension SLE1extending along the reference Y-axis direction. The group of active areas GP1is provided with a plurality of bit lines BL1˜BLnextending along the reference X-axis direction, where BL1and BLnare bit lines shared between different groups in the Y-axis direction.

The following illustrates an example of the read and write operation method of the 2T1M memory array MA2ofFIG. 11. Taking the reading of the magnetic tunnel junction element MTJ12inFIG. 11as an example, the reading operation conditions include: biasing the word line WL1to VDD, and biasing the bit line BL2to a lower voltage, for example, 50 mV. The main source line SLM1and the source line extension SLE1are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ12inFIG. 11to a parallel state (0 state), the writing operation conditions include: biasing the word line WL1to VDD, and biasing the bit line BL2to VCC. The main source line SLM1and the source line extension SLE1are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ12inFIG. 11to the anti-parallel state (1 state), the writing operation conditions include: biasing the word line WL1to VDD, grounding the bit line BL2, and biasing the main source line SLM1and the source line extension SLE1to VCC. The other word lines are grounded. The other bit lines and main source lines are both floating.

Please refer toFIG. 12, which is an equivalent circuit diagram of a triple transistor dual memory cell (3T2M) memory array MA3according to another embodiment of the present invention. As shown inFIG. 12, the memory array MA3includes a plurality of selection transistors200a,200b, and200c, which are respectively arranged in a plurality of rows R1˜Rn, where n may be an integer ranging between 2˜8, for example, n=6, but is not limited to. The three selection transistors200a,200b,200cand the two data storage elements including the magnetic tunnel junction element MTJ together constitute a 3T2M configuration.FIG. 12shows at least one group of active areas GP1for illustration purposes. The active areas in the group GP1share a main source line SLM1extending along the reference X axis direction and a source line extension SLE1extending along the reference Y axis direction. The group of active areas GP1is provided with a plurality of bit lines BL1˜BL2nextending along the reference X-axis direction, where BL1and BL2nare bit lines shared between different groups in the Y-axis direction.

The following illustrates an example of the read and write operation method of the 3T2M memory array MA3ofFIG. 12. Taking the reading of the magnetic tunnel junction element MTJ12inFIG. 12as an example, the reading operation conditions include: biasing the word lines WL1˜WL3to VDDand biasing the bit line BL4to a lower voltage, for example 50 mV. The main source line SLM1and the source line extension SLE1are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ12inFIG. 12to a parallel state (0 state), the writing operation conditions include: biasing the word lines WL1˜WL3to VDD, and biasing the bit line BL4to VCC, grounding the main source line SLM1and the source line extension SLE1. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ12inFIG. 12to an anti-parallel state (1 state), the writing operation conditions include: biasing the word lines WL1˜WL3to VDD, and grounding the bit line BL4, The main source line SLM1and the source line extension SLE1are biased to VCC. The other word lines are grounded. The other bit lines and main source lines are both floating.