System and method for preventing controller induced pulse skipping at low duty cycle operations

A voltage regulator generates a regulated output voltage responsive to an input voltage and drive control signals. An error amplifier generates an error voltage signal responsive to the regulated output voltage and a reference voltage. A PWM modulator generates a PWM control signal responsive to the error voltage signal, a ramp voltage and an inverse of the reference voltage. Control circuitry within the PWM modulator maintains the error voltage signal applied to the PWM modulator at substantially a same DC voltage level over the reference voltage operating range and maintains the error voltage signal above a minimum value of the ramp voltage. Driver circuitry generates the drive control signals responsive to the PWM control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIG. 1illustrates a modulator for producing the PWM signal according to the present disclosure;

FIG. 2illustrates the implementation of a voltage regulator and controller including a variable high pass filter;

FIG. 3illustrates a first embodiment of a manner for compensating for the loop gain of the PWM modulator ofFIG. 1;

FIG. 4illustrates an alternative embodiment for compensating for the loop gain associated with the PWM modulator ofFIG. 1;

FIG. 5illustrates yet a further embodiment of a manner for compensating for the loop gain for use with the PWM modulator ofFIG. 1; and

FIG. 6illustrates an electronic/electric system including electronic/electric circuitry including the switching circuitry ofFIGS. 1-5according to one embodiment.

DETAILED DESCRIPTION

Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of a system and method for preventing controller induced pulse skipping at low duty cycle operations are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments.

Referring now toFIG. 1, there is illustrated a block diagram of a PWM modulator100that limits or eliminates pulse skipping events within a voltage regulator. A first comparator102receives the ramp voltage signal VDOWN—RAMPat its non-inverting input. The VDOWN—RAMPsignal sets the steady state PWM switching frequency. When this down ramp signal crosses below VCOMP, the PWM signal is turned on. The first comparator102additionally receives the error voltage signal VCOMPat its non-inverting input. The output of the comparator102is provided to a pulse generation circuit104that generates an output pulse responsive to the output of the comparator102going to a logical “high” level. The output of the pulse generation circuit104is connected to the S input of the SR latch106.

The error voltage VCOMPis also applied to a first input of a summation circuit108. The other input of the summation circuit108receives a current sensing signal Ki×Iaverage. This current sensing signal comprises the current sense signal from the current sense circuit220(FIG. 2). The current sense signal is subtracted from the error signal VCOMPby the summation circuit108to generate a signal VCOMP1. The new signal VCOMP1is provided to the inverting input of a second comparator110. The non-inverting input of the second comparator110receives a signal VUP—RAMPthat is generated at a node112. The VUP—RAMPsignal begins charging when the PWM signal is turned on. When the VUP—RAMPsignal crosses above the signal VCOMP1, the PWM signal turns off. The VUP—RAMPis the main ramp signal that determines where the control signal COMP operates. Thus, when a 1/VREF multiplier is multiplied by the nominal UP_RAMP slew rate (IUPRAMP—NOM), the RAMP signal for the rest of discussion can be considered to be the VUP—RAMPsince this is what is being multiplied by 1/VREF. The output of the comparator110is provided to the R input of the SR latch106.

The VUP—RAMPsignal generated at node112is generated responsive to a current source114that is sourced into the node112responsive to a current control signal IBALANCE. The current source114is additionally responsive to an output of a multiplier circuit116. The multiplier circuit116combines the IUPRAMP—NOMcontrol signal and the inverse of the reference voltage

1VREF.
The IUPRAMP—NOMcontrol signal sets the nominal voltage slew rate of the VUP—RAMPsignal. To increase the voltage slew rate of the VUP—RAMPsignal, the nominal current IUPRAMP—NOMcontrol signal is multiplied by 1/VREF. This corrects the VUP—RAMPsignal slew rate to hold VCOMPat the same control signal voltage. Each of these signals is applied to the multiplier circuit116and the output of the multiplier circuit is provided as a further control signal to the current source114. The signal

1VREF
is a generated gain signal that is multiplied by the nominal up ramp slew rate (IUPRAMP—NOM). As VREFfalls, the nominal up ramp slew rate will increase to maintain the error voltage COMP signal at the same DC level over the reference voltage operating range. Thus, the error voltage signal will operate sufficiently above the bottom of the modulator RAMP signal even at low duty cycle operation. This enables the regulator to avoid a pulse skipping condition. The circuit limits or prevents erroneous pulse skipping due to noise and other non-idealities. This happens for low-duty cycle operation where noise can push the COMP signal around the bottom of the ramp. Low duty-cycle operations occur where the output voltage provided from an associated voltage regulator operates at a point very near the minimum voltage level of the ramp signal being applied to the PWM modulator100. When the output voltage ripple of the voltage regulator is outside of an acceptable window, pulse skipping problems may occur at the output of the PWM modulator100. The circuit should not prevent a pulse skip during a real situation requiring pulse skipping to maintain voltage regulation. A real pulse skip results in the COMP signal falling below the bottom of the ramp. The variable ramp voltage will maintain the control signal at the same DC level over the reference voltage range. A capacitor118is connected between node112and ground. A switch120is responsive to theQoutput of the SR latch106and connects node112to ground when the switch is closed.

In an alternative embodiment, rather than applying the inverse reference voltage 1/VREFto the multiplier116in all cases, the value of 1/VREFcan only be applied only when the output voltage is below some critical threshold level. Thus, there is a break point for VREFwhere the gain applied to IUPRAMP—NOMwould be 1/VREFwhen the output voltage is below a voltage level N and the gain applied to IUPRAMP—NOMwould be 1 whenever the output voltage is above the voltage level N. The voltage value for N can be selected as appropriate.

The faster ramp slew rate will reduce the overall gain of the modulator100. In order to compensate for the reduced modulator gain, a variable high pass filter is inserted between the error amplifier and the PWM modulator100. This will be more fully discussed herein below. The variable gain high pass filter may comprise a number of different configurations as are more fully illustrated inFIGS. 3,4and5. The gain of the variable gain high pass filter will equal to

1VREF.
The error voltage signal will remain at the same DC voltage level without degrading a dynamic response.

Referring now toFIG. 2, there is illustrated a block diagram of the modulator100described with respect toFIG. 1having the variable gain high pass filter204inserted between the error amplifier214and the modulator100. By inserting the variable gain high pass filter204between the error amplifier214and the modulator100, the gain reduction caused by the faster ramp slew rate within the modulator100is compensated for by the filter204. The error voltage signal will remain at the same DC voltage without degrading the dynamic response of the modulator100.

The input voltage VINis applied at an input voltage node202. A first switching transistor205has its drain/source path connected between node202and node206. A second switching transistor208has its drain/source path connected between node206and ground. The gates of each of switching transistors205and208are connected to receive control signals from a driver circuit210. The driver circuits generate the drive signal QU to transistor205and QL to transistor208responsive to the PWM control signal from a PWM modulator200. Diode emulation is achieved by turning off the lower FET, second switching transistor208, when the load current is detected to be zero.

The regulator further includes an inductor216connected between node206and node218. A current sensor220monitors the current through the inductor216at node218and generates an IDROOPcurrent sense signal to the inverting input of the error amplifier214at node222. A capacitor224is connected between node218and ground. The regulated output voltage VOUTis provided from node218. The output voltage VOUTis monitored at node218through an RC circuit consisting of resistors226,228and capacitor230. Resistor226is connected between node218and node222. In parallel with resistor226is a series connection of resistor228and capacitor230between node222and node218.

The error amplifier214compares the monitored output voltage VOUTwith a reference voltage VREFthat is applied to a non-inverting input of the error amplifier214. A feedback signal is provided between the output of the error amplifier214and its non-inverting input consisting of capacitors232and234and resistor236. Capacitor234is connected between the output of the error amplifier214and the non-inverting input at node222. Connected in parallel with capacitor234are a series connection of capacitor232and resistor236.

The variable gain high pass filter204may be implemented in any number of fashions. Several of these implementations are illustrated with respect toFIGS. 3-5. In the embodiment ofFIG. 3, the variable gain high pass filter204consists of an amplifier304having its non-inverting input connected to receive the error voltage signal (COMP) from the error amplifier214. The inverting input of the amplifier304is connected to node306. A variable feedback resistor308is connected between the output of the amplifier304and the inverting input at node306. The value of the variable resistor is established according to the equation (1/VREF−1)×RHPF2. Connected in series between node306and ground are a resistor310and a capacitor312.

Referring now toFIG. 4, there is illustrated a second embodiment of the variable gain high pass filter implemented within the voltage regulator. In this embodiment, the variable gain high pass filter204includes a summation circuit402having a first input connected to node404and a second input connected to the output of an amplifier406. A capacitor408is connected between node404and ground. A resistor410is connected between node404and node412. Node412is connected to the output of the error amplifier214to receive the error voltage signal. Capacitor414is connected between node412and node416. A resistor418is connected between node416and ground. The input of the amplifier406is connected to node416. The amplifier406receives a control input of

1VREF.
The output of the summation circuit402is connected to the input of the PWM modulator100.

A third embodiment is illustrated with respect toFIG. 5. The implementation ofFIG. 5includes the summation circuit502having its output providing an input to the PWM modulator100. A first input of the summation circuit502is connected to node504. Node504is connected to receive the error voltage signal from the output of the error amplifier214. A capacitor506is connected between node504and node508. A resistor510is connected between node508and ground. The second input of the summation circuit502is connected to the output of an amplifier512. The amplifier512has its input connected to node508and also receives a control signal

1VREF-1
as a control input. The

1VREF-1
signal comprises a gain control signal for the amplifier512.

Using the variable up ramp slew rate within the modulator100and the variable gain high pass filter204, the COMP voltage remains flat over the output voltage range. There is no degradation in transient performance when the variable gain high pass filter204is included. The circuits ofFIGS. 1-5provide a simple way to limit or prevent controller induced pulse skipping during low duty cycle operation. The circuit also provides a way to maintain optimal dynamic performance with variable modulator gain. This improves regulation and stability of a voltage regulator by preventing pulse skipping during low duty cycle operation. The circuit provides a simple way to prevent controller induced skipping at low duty cycle operation. Existing solutions for providing these abilities increase the BOM costs of the voltage regulator by adding components to the board to improve regulation during low duty cycle operation.

Voltage regulators and associated circuitry according to the embodiments of the present disclosure can be embodied as a variety of different types of electronic devices and systems, such as computers, cellular telephone, personal digital assistants, and industrial systems and devices. More specifically, some applications include, but are not limited to, CPU power regulators, chip regulators, point of load power regulators and memory regulators.FIG. 6is a block diagram of an electronic/electric system600including electronic/electric circuitry/devices602including the voltage regulation circuitry604as described with respect toFIGS. 1-5. The electronic/electric circuitry/devices602include circuitry for performing various functions required for the given system, such as executing specific software to perform specific calculations or tasks where the electronic system is a computer system. In addition, the electronic/electric system600may include one or more input devices606, such as a keyboard, mouse or touchpad coupled to the electronic circuitry/device602to allow an operator to interface with the system. Typically, the electronic/electric system600also includes one or more output devices608coupled to the electronic/electric circuitry/device602, such output devices typically including a video display such as a LCD display. One or more data storage devices610are also typically coupled to the electronic/electric circuitry/device602to store data or retrieve data from storage media. Examples of typical storage devices610include magnetic disc drives, tape cassettes, compact discs read only (CD ROMS) and compact discs (CD R/W) memories, and digital video discs (DVDs), flash memory drives, and so on.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this system and method for preventing controller induced pulse skipping at low duty cycle operations provides a system and method for eliminating pulse skipping in a voltage regulator. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.