Electronic device

An electronic device is provided to include a semiconductor memory including a variable resistance element. The variable resistance element may include a variable resistance pattern including a first electrode layer, a variable resistance layer, and a second electrode layer that are sequentially stacked; and a switching assist structure spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and including multilayered conductive structures that are vertically spaced from one another.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent document claims priority and benefits of Korean Patent Application No. 10-2015-0052367, entitled “ELECTRONIC DEVICE” and filed on Apr. 14, 2015, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

Recently, as electronic appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, semiconductor devices capable of storing information in various electronic appliances such as a computer, a portable communication device, and so on have been demanded in the art, and research has been conducted for the semiconductor devices. Such semiconductor devices include semiconductor devices which can store data using a characteristic that they are switched between different resistant states according to an applied voltage or current, for example, an RRAM (resistive random access memory), a PRAM (phase change random access memory), an FRAM (ferroelectric random access memory), an MRAM (magnetic random access memory), an E-fuse, etc.

SUMMARY

The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which operation characteristics are improved by providing two independent but collaborative switching mechanisms in each variable resistance elements.

In one aspect, an electronic device is provided to include a semiconductor memory. The semiconductor memory may include a variable resistance element including the variable resistance pattern including a first electrode layer, a variable resistance layer and a second electrode layer that are sequentially stacked; and a switching assist structure spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and including multilayered conductive structures that are vertically spaced from one another.

In some implementations, one end of the switching assist structure may be electrically coupled to the first electrode layer or the second electrode layer. In some implementations, the multilayered conductive structures of the switching assist structure each may include a single conductive line shape and may be coupled in series between a first node of one end of the switching assist and a second node of the other end thereof. In some implementations, the switching assist structure may have a spiral shape. In some implementations, the switching assist structure may include a plurality of ring-type conductive layers, and a plurality of electrically conductive connectors electrically coupled to the plurality of the ring-type conductive layers. In some implementations, each of the plurality of ring-type conductive layers may include a “C” shape of which a side of one end is spaced to face a side of the other end. In some implementations, the plurality of electrically conductive connectors may couple the plurality of ring-type conductive layers such that directions of current flowing through the plurality of ring-type conductive layers are the same with one another.

In another aspect, an electronic device is provided to include a variable resistance element including a variable resistance pattern including a first electrode layer and a second electrode layer that are separated from each other to receive a first current to flow through, and the variable resistance pattern between the first and second electrode layers to include a storage layer exhibiting a variable magnetization that can be changed by the first current when above a required current value, a reference layer exhibiting a fixed magnetization and spaced from the storage layer, and a tunnel barrier layer between the storage and reference layers, wherein the variable resistance pattern shows different resistance values to the first current based on a direction of the variable magnetization relative to the fixed magnetization; and a switching assist structure, located adjacent to the variable resistance element, structured to receive a second current and to produce a magnetic field at the variable resistance pattern in response to the second current to assist a switching of the variable magnetization of the variable resistance pattern under a switching operation caused by the first current when under the required current value.

In some implementations, the switching assist structure may include a plurality of ring-type conductive layers vertically spaced from one another along a direction from the first electrode layer to the second electrode layer of the variable resistance element; and conductive connectors electrically coupling the conductive layers. In some implementations, the plurality of ring-type conductive layers and the conductive connectors may form a spiral shape. In some implementations, each of the conductive layers may have a discontinuous shape having an opening portion. In some implementations, the plurality of ring-type conductive layers and the conductive connectors may surround the variable resistance pattern. In some implementations, the ring-type conductive layers may have the same inner diameter. In some implementations, the ring-type conductive layers may have different inner diameters from one another. In some implementations, the ring-type conductive layers may have the same thickness. In some implementations, the ring-type conductive layers may have different thicknesses from one another. In some implementations, the ring-type conductive layers may have the same interval. In some implementations, the ring-type conductive layers may have different intervals from one another. In some implementations, the ring-type conductive layers may be formed to have a slope with respect to the direction of the first current passing through the variable resistance pattern. In some implementations, the slope may be in a range of 15° to 75°. In some implementations, the variable resistance layer may include a magnetic tunnel junction in which a tunnel barrier is interposed between two magnetic materials. In some implementations, the electronic device may further comprising a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.

In some implementations, the electronic device may further comprising a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

In some implementations, the electronic device may further comprising a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

In some implementations, the electronic device may further comprising a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

In some implementations, the electronic device may further comprising a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

In another aspect, an electric device is provided to include a variable resistance element including a variable resistance pattern in which a first electrode layer, a storage layer, a tunnel barrier layer, a reference layer and a second electrode layer are sequentially stacked, and a switching assist which includes multilayered conductive structures spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and vertically spaced from one another,

In another aspect, an electronic device is provided to include a plurality of first conductive lines and a plurality of second conductive lines crossing one another; and memory cells coupled to the plurality of first conductive lines and the plurality of second conductive lines to form an memory array, each memory cell including a selection element and a variable resistance element coupled in series and the selection element operable to select a respective memory cell to electrically coupled to respective first and second conductive lines. The variable resistance element within each memory cell may include a variable resistance pattern having a first electrode layer, a storage layer, a tunnel barrier layer, a reference layer and a second electrode layer which are sequentially stacked, wherein the storage layer exhibits a variable magnetization that can be changed by a current flowing through the variable resistance pattern when above a required current value or a magnetic field; and a switching assist structure including conductive structures that surround the variable resistance pattern and are electrically connected to each other to receive a switching assist current to produce a switching assist magnetic field at the storage layer to assist switching of the variable magnetization of the storage layer when under a switching operation caused by the current flowing through the variable resistance pattern when under the required current value, wherein each selection element and each variable resistance element are electrically coupled through the switching assist structure.

In some implementations, the conductive structures may be ring shaped to surround the variable resistance pattern. In some implementations, the switching assist structure may include a portion adjacent to the first electrode layer and coupled to the first electrode layer, and another portion adjacent to the second electrode layer and coupled to the selection element.

According to the embodiments, since the variable resistance element of a semiconductor memory includes a switching assist structure, it is possible to reduce the driving current needed for the variable resistance element to be switched between different resistant states.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below in detail with reference to the accompanying drawings.

As described later, the disclosed technology in this patent document includes an electronic device including a semiconductor memory in which operation characteristics are improved. Here, the semiconductor memory in which operation characteristics are improved may mean that a driving current (or switching current) required for writing and erasing of logic information is reduced. In various examples and implementations of the disclosed technology in this patent document, the electronic device may include the semiconductor memory. The semiconductor memory is available at low-current driving.

One implementation of a semiconductor memory according to various examples and implementations of the disclosed technology in this patent document uses a variable resistance element as a storage element. The variable resistance element is an element that exhibits different resistance states of different resistance values and can be operated to switch between different resistance states in response to a bias provided, for example, a current or voltage. The variable resistance element may include variable resistance materials. The variable resistance materials are used in a resistive memory that storage and erasure of the information is formed by changing of resistance characteristics. The variable resistance materials may include various materials used for RRAM, PRAM, FRAM, MRAM, or STTRAM. For example, the variable resistance materials may include metal oxide insulating materials including ferromagnetic materials, transition metal oxide insulating materials or perovskite-based materials, phase change insulating materials including chalcogenide materials and ferromagnetic insulating materials. Various examples and implementations of the disclosed technology in this patent document are described for a case of using a magnetic tunnel Junction (MTJ) in which a tunnel barrier is interposed between two magnetic materials as the variable resistance element.

According to various examples and implementations of the disclosed technology in this patent document, a semiconductor memory including a magnetic tunnel Junction, for example, STTMRAM (Spin transfer torque magnetic RAM) requires a high driving current (or switching current) to reverse the magnetization direction of magnetic materials. For example, a perpendicular magnetic tunnel junction whose magnetic materials have a perpendicular magnetization requires a higher driving current to reverse the magnetization direction. This is because the perpendicular magnetic tunnel junction uses magnetic materials having a high magnetic anisotropy for the thermal stability of the reduced size. Further, when a magnetic field shift occurs by interference between adjacent magnetic materials, the perpendicular magnetic tunnel junction requires more driving current than the case without the magnetic field shift. Thus, it needs to reduce the driving current required for switching between the different resistance states of the magnetic tunnel junction in order to improve operation characteristics of the semiconductor memory having the magnetic tunnel junction.

In light of the above need for reducing the driving current that flows through the variable resistance element for changing its resistance state, various examples and implementations of the disclosed technology in this patent document include, in a variable resistance element, a switching assist structure spaced from the sidewall of a magnetic tunnel junction to surround a magnetic tunnel junction of the variable resistance element. The switching assist structure is designed as an electromagnetic element to produce a desired switching assist magnetic field under a control of a switching assist current that applies to the switching assist structure to produce a switching assist magnetic field as a composite magnetic field around the magnetic tunnel junction in a direction that would help reverse the magnetization direction of the magnetic tunnel junction that is driven by a low driving current through the junction. In the presence of the switching assist structure as disclosed herein, there are two independent magnetization switching mechanisms that collectively operate to cause the switching of the magnetization direction of the variable resistance element: (1) the current-based switching due to the driving current that is directly applied to the variable resistance element to flow through the magnetic tunnel junction of the variable resistance element, and (2) the switching caused by the presence of external magnetic field effect from the switching assist magnetic field generated at the variable resistance element by the switching assist structure as an electromagnet under the control of the switching assist current that applies to the switching assist structure without flowing through the variable resistance element. Due to the additional switching by the switching assist magnetic field from the switching assist structure by the mechanism (2), the magnitude of the current for switching based on the mechanism (1) is reduced in comparison with the needed switching current that flows through the variable resistance element solely under the mechanism (1) without the switching assistance of the mechanism (2).

Therefore, in the combination of the above two mechanisms, the disclosed technology essentially applies a FIMS (field-induced magnetization switching) method of reversing the magnetization direction in addition to the existing conventional MRAM and a CIMS (current-induced magnetization switching) method of reversing the magnetization direction in STTMRAM to reduce a driving current required to switch the magnetic tunnel junction. Due to the added switching mechanism (2) by the switching assist structure, the reduced driving current flowing through the junction can also advantageously reduce the interference of adjacent variable resistance elements in any array of such elements. Therefore, in addition to the reduced driving current in the junction, the disclosed technology can also prevent or mitigate interference between adjacent magnetic materials and prevent the undesired magnetic field shift.

FIGS. 1 and 2illustrate an exemplary variable resistance element and a switching assist structure of a semiconductor memory in accordance with a first implementation.FIG. 3is an exemplary variable resistance element of the semiconductor memory in accordance with a second implementation. Specifically,FIGS. 1 and 3are perspective views showing both the respective switching assist structures and the variable resistance patterns160andFIG. 2is a perspective view of a switching assist structure ofFIG. 1only without showing the corresponding variable resistance pattern160fromFIG. 1.

Referring toFIGS. 1 and 2according to the first implementation, a variable resistance element100of the semiconductor memory includes a variable resistance pattern160in which a first electrode layer110, a variable resistance layer, and a second electrode layer120are sequentially stacked so that the variable resistance layer is located between the first and second electrode layers110and120. Notably, the variable resistance element100includes a switching assist structure200that is separate from but is adjacent to the variable resistance pattern160to produce a switching assist magnetic field in the variable resistance pattern160that assists with the switching. The switching assist structure200is driven by a switching assist current in order to produce the switching assist magnetic field and the switching assist current is separate from the driving current that directly flows through the variable resistance pattern160via the two electrode layers110and120. The switching assist structure200can be configured to include one or more conductive paths to carry the switching assist current and to produce a desired switching assist magnetic field for switching the magnetization of the variable resistance pattern160. The one or more conductive paths of the switching assist structure200can be implemented in various configurations. As shown by the examples below, the switching assist structure200may include multilayered conductive structures which are spaced from a side wall of the variable resistance pattern160to surround the variable resistance pattern160, and vertically spaced from one another. The examples tend to better suited for generating a switching magnetic field with a large magnetic field component along or against the driving current direction through the variable resistance pattern160and perpendicular to the first and second electrode layers. Therefore, such examples are suitable for switching a variable resistance pattern160having a magnetization of each magnetization layer perpendicular the structure layers. For a variable resistance pattern160having an in-plane magnetization that is substantially parallel to the structure layers, the one or more conductive paths of the switching assist structure200can be configured to produce a switching magnetic field with a large magnetic field component along or parallel to the structure layers.

In some implementations of the variable resistance pattern160, the variable resistance layer may include a storage layer130on the first electrode layer110, a tunnel barrier layer140on the storage layer130, and a reference layer150on the tunnel barrier layer140. The variable resistance layer may include the second electrode layer120on the reference layer150. The storage layer130and the reference layer150may include magnetic materials. The variable resistance pattern160may form a magnetic tunnel junction. In some implementations, the reference layer150may serve as a pinned layer that the magnetization direction is pinned, and the storage layer130may serve as a free layer that the magnetization direction is changed. The storage layer130and the reference layer150may be a single layer or multi-layers including Fe—Pt alloy, Co—Pd alloy, Co—Pt alloy, Fe—Ni—Pt alloy, Co—Fe—Pt alloy, or Co—Ni—Pt alloy. The tunnel barrier layer140through charge (for example, electron) tunneling serves to change the magnetization direction of the free layer. The tunnel barrier layer140may include insulating materials. In some implementations, the tunnel barrier layer140may be a single layer or multi-layers including oxide of MgO, MgON, Al2O3, CaO, SrO, TiO, VO or NbO.

The switching assist structure200serves to reduce a driving current (or switching current) that is directed to flow through the variable resistance pattern160required for switching of the variable resistance pattern160, for example, the magnetic tunnel junction between different resistance states by forming a composite magnetic field. To form the composite magnetic field that the magnetic force is provided in a predetermined direction, the switching assist structure200may have a single conductive line shape which surround the variable resistance pattern160and provide current flowing in one direction, for example, from the reference layer150toward the storage layer130. The switching assist structure200may include one end as a first node230and the other end as a second node240. A switching assist current is supplied to the switching assist structure200via the nodes230and240and the magnitude and the direction of this switching assist current are controlled by achieve a desired operation in connection with a separate driving current directed through the layers130,140and150of the variable resistance pattern160. The multilayered conductive structures which are vertically spaced may couple in series between the first node230and the second node240. The first node230and the second node240may be electrically coupled to the first electrode layer110or the second electrode layer120of the variable resistance pattern160. It will be described later on the electrical coupling between the switching assist structure200and the variable resistance element100(seeFIG. 10).

A switching assist structure200may include a plurality of ring-type conductive layers210vertically spaced from one another and a plurality of electrically conductive connectors or plugs220which electrically couple the plurality of ring-type conductive layers, i.e., electrically connecting the different ring-type conductive layers210to form a contiguous electrical path via the different ring-type conductive layers210. In some implementations, the switching assist structure200including the plurality of ring-type conductive layers210and the plurality of electrical connectors or plugs220may have a spiral shape as illustrated inFIG. 3.

Each of the plurality of ring-type conductive layers210may have a discontinuous shape having an opening portion211. For example, each of the plurality of ring-type conductive layers210may have a “C” shaped cross section. In this case, one side of a ring-type conductive layer201has two separate portions spaced to face to each other. The ring-type conductive layers210and the inter-layer connectors220form a coil structure with multiple coils to collectively generate a desired switching magnetic field along the axial direction of the coil structure. The variable resistance pattern160is enclosed within this coil structure or surrounded by the coils. Different variable resistance patterns160of a memory array have their corresponding coil structures.

The plurality of electrical connectors or plugs220may electrically couple the plurality of ring-type conductive layers210vertically spaced such that the switching assist structure200serves as a single conductive line that a current flows in one direction. Therefore, the plurality of electrical connectors or plugs220may couple the plurality of ring-type conductive layers210such that the current flows in the same direction through the plurality of ring-type conductive layers210. For example, referring toFIG. 2, when a first conductive layer210A to a fifth conductive layer210E are vertically spaced, an electrical connector or plug (for example, a first electrical connector or plug220A) on a Nth conductive layer (for example, a first conductive layer210A couples between the Nth conductive layer) and a N+1th conductive layer (for example, a second conductive layer210B) may couple one end of the Nth conductive layer and the other end of the N+1th conductive layer.

As described above, the variable resistance element100may reduce the driving current required for switching the variable resistance element100by including the switching assist structure200which surrounds the variable resistance pattern160.

Herein after, modified variable resistance elements100in accordance with the first implementation will be described in detail with reference toFIGS. 4 to 9. For clarity, the first implementation will be exemplarily described. However, the modifications to be described later may be applied to a variable resistance element100′ in accordance with a second implementation.

FIGS. 4 to 9are views schematically illustrating modified variable resistance elements of a semiconductor memory in accordance with the first implementation.

A switching assist structure200according to the first implementation surrounds the variable resistance pattern160including both the storage layer130and the reference layer150. As a modification of the first implementation, referring toFIG. 4, a switching assist structure200may surround at least the storage layer130. Referring toFIG. 5, the switching assist structure200may surround at least the reference layer150. Here, the switching assist structure200surrounding the storage layer130may reduce a driving current of the variable resistance element100by easily reversing the magnetization of the storage layer130. The switching assist structure200surrounding the reference layer150may reduce the driving current of the variable resistance element100by suppressing interference, for example, the magnetic field shift due to the magnetic field of the reference layer150.

In the switching assist structure200according to the first implementation, all the plurality of ring-type conductive layers210surrounding the variable resistance pattern160have the same inner diameter. As a modification of the first implementation, referring toFIG. 6, a plurality of ring-type conductive layers210surrounding a variable resistance pattern160may have different diameters from one another. In some implementations, the inner diameter gradually increases from a first electrode layer110to a second electrode layer120direction, or vice versa. In some implementations, the plurality of ring-type conductive layers210surrounding a storage layer130has the same inner diameter (a first inner diameter) and the plurality of ring-type conductive layers201surrounding a reference layer150has the same inner diameter (a second inner diameter), while the first inner diameter is smaller than the second inner diameter, or vice versa. For example, in the switching assist structure200, to reduce a driving current of the variable resistance element100by easily reversing the magnetization of the storage layer130, inner diameters of one or more of the ring-type conductive layers210which surround the storage layer130may be smaller than those of one or more of the ring-type conductive layers which surround the reference layer150.

In the switching assist structure200according to the first implementation, all the plurality of ring-type conductive layer210surrounding the variable resistance pattern160has the same thickness. As a modification of the first implementation, referring toFIG. 7, a plurality of ring-type conductive layers210surrounding a variable resistance pattern160may be different from one another in thicknesses. For example, the thickness gradually increases along a direction from a second electrode layer120to a first electrode layer110, or vice versa. In some implementations, the plurality of ring-type conductive layers210surrounding a storage layer130have the same thickness (a first thickness) and the plurality of ring-type conductive layers210surrounding a reference layer150have the same thickness (a second thickness), while the first thickness is greater than the second thickness, or vice versa. For example, in the switching assist structure200, to reduce a driving current of the variable resistance element100by easily reversing the magnetization of the storage layer130, thicknesses of one or more of the ring-type conductive layers210which surround the storage layer130may be greater than those of one or more of the ring-type conductive layers210which surround the reference layer150.

In the switching assist structure200according to the first implementation, all the plurality of ring-type conductive layers210of surrounding the variable resistance pattern160are arranged at the same interval. As a modification of the first implementation, referring toFIG. 8, a plurality of ring-type conductive layers210surrounding a variable resistance pattern160may be arranged at the different intervals from one another. For example, the interval between two adjacent ring-type conductive layers210varies. For example, the interval between two adjacent ring-type conductive layers210gradually increases in a direction from a first electrode layer110to a second electrode layer120, or vice versa. In some implementations, the plurality of ring-type conductive layers surrounding a storage layer130may have the same space (a first interval) and the plurality of ring-type conductive layer surrounding a reference layer150may have the same space (a second interval), while the first interval is smaller than the second interval, or vice versa. For example, in the switching assist structure200, to reduce a driving current of the variable resistance element100by easily reversing the magnetization of the storage layer130, the interval between the ring-type conductive layers210which surround the storage layer130may be smaller than the interval between the ring-type conductive layers210which surround the reference layer150.

In the switching assist structure200according to the first implementation, the plurality of ring-type conductive layers210which surround the variable resistance pattern160may be arranged to be perpendicular to a direction of current passing through the variable resistance pattern160. As a modification of the first implementation, referring toFIG. 9, a plurality of ring-type conductive layers210which surround a variable resistance pattern160may be arranged to have a slope with respect to a current direction. In some implementations, the slope may be in a range of from 15° to 75° with respect to the current direction. The magnetic force required for reversing the magnetization direction becomes the smallest when the slope is 45° as compared when the switching assist structure200is arranged perpendicular or parallel to the current direction.

As described above, the variable resistance element100including the switching assist structure200according to the first implementation may be variously modified and each of the modified examples may be combined with each other. For example, the plurality of ring-type conductive layers210which are spaced from each other in the switching assist structure200may have different inner diameters and be arranged at different intervals. The driving current of the variable resistive element100may be more effectively reduced through the above described structure.

FIG. 10is an equivalent circuit diagram illustrating a semiconductor memory in accordance with an implementation for supplying both (1) a switching current that directly flows through each variable resistance pattern160of a memory cell of a memory array and (2) a switching assist current that flows through only the switching assist structure200. To simply the illustration,FIG. 10shows only the circuitry part that supplies the switching assist current through each switching assist structure200when a selection element330(e.g., a transistor switch) is controlled to select a particular memory cell.

ReferringFIGS. 1 and 10, the semiconductor memory according to an implementation may have a crosspoint cell array structure. For example, the semiconductor memory may include a plurality of first conductive lines310and a plurality of second conductive lines320that cross each other, and memory cells which are located at the intersections thereof. The memory cell may have a form that the variable resistance element100including the switching assist structure200and a selection element330are coupled in series. Here, the variable resistance element100and the selection element330may be electrically coupled through the switching assist structure200.

The first node230of the switching assist structure200adjacent to the first electrode layer110of the variable resistance pattern160may be electrically coupled to the variable resistance element100or the selection element330. The second node240adjacent to the second electrode layer120of the variable resistance pattern160may be electrically coupled to the selection element330or the variable resistance element100. Here, the coupled relations of the first node230and the second node240may be adjusted according to the stacking structure of the variable resistance pattern160. This is because the current needs to flow in the switching assist structure200from the reference layer150toward the storage layer130in order to reduce a driving current. The direction of the current flowing in the switching assist structure200is a current direction when the greatest driving current is necessary, for example, when the magnetization direction of the variable resistance element is switched from the parallel state (low-resistance state) to the antiparallel state (high-resistance state).

For example, when the variable resistance pattern160includes the first electrode layer110, the storage layer130, the tunnel barrier layer140, the reference layer150and the second electrode layer120that are sequentially stacked, the first node230of the switching assist structure200may be coupled to the first electrode layer110of the variable resistance pattern160, and the second node240of the switching assist structure200may be coupled to the selection element330. When the variable resistance pattern160includes the first electrode layer110, the reference layer150, the tunnel barn er layer140, the storage layer130and the second electrode layer120that are sequentially stacked, the first node230of the switching assist structure200may be coupled to the selection element330, and the second node240of the switching assist structure200may be coupled to the first electrode layer110of the variable resistance pattern160.

The selection element330may include any element that can control the supply of a current or voltage to the variable resistance element100. For example, a diode, metal insulator transition (MIT), and a transistor may be employed as the selection element330. The selection element330may be coupled to the second conductive line320.

As described above, the semiconductor memory may reduce a driving current required for switching the variable resistance element100by including the variable resistance element100including the switching assist structure200. Therefore, the semiconductor memory with improved operation characteristics may be provided.

The semiconductor memory in accordance with the implementation of the present disclosure may be applied to diverse electronic devices or systems.FIGS. 11 to 15show some examples of electronic devices or systems that can implement the semiconductor memory disclosed herein.

Referring toFIG. 11, a microprocessor1000may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor1000may include a memory unit1010, an operation unit1020, a control unit1030, and so on. The microprocessor1000may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit1010is a part which stores data in the microprocessor1000, as a processor register, register or the like. The memory unit1010may include a data register, an address register, a floating point register and so on. Besides, the memory unit1010may include various registers. The memory unit1010may perform the function of temporarily storing data for which operations are to be performed by the operation unit1020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit1010may include one or more of the above-described semiconductor devices in accordance with the implementations. the memory unit1010may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the memory unit1010and the microprocessor1000may have improved reliability.

The operation unit1020may perform four arithmetical operations or logical operations according to results that the control unit1030decodes commands. The operation unit1020may include at least one arithmetic logic unit (ALU) and so on.

The control unit1030may receive signals from the memory unit1010, the operation unit1020and an external device of the microprocessor1000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor1000, and execute processing represented by programs.

The microprocessor1000according to the present implementation may additionally include a cache memory unit1040which can temporarily store data to be inputted from an external device other than the memory unit1010or to be outputted to an external device. In this case, the cache memory unit1040may exchange data with the memory unit1010, the operation unit1020and the control unit1030through a bus interface1050.

FIG. 12is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 12, a processor1100may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor1100may include a core unit1110which serves as the microprocessor, a cache memory unit1120which serves to storing data temporarily, and a bus interface1130for transferring data between internal and external devices. The processor1100may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The core unit1110of the present implementation is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit1111, an operation unit1112and a control unit1113.

The memory unit1111is a part which stores data in the processor1100, as a processor register, a register or the like. The memory unit1111may include a data register, an address register, a floating point register and so on. Besides, the memory unit1111may include various registers. The memory unit1111may perform the function of temporarily storing data for which operations are to be performed by the operation unit1112, result data of performing the operations and addresses where data for performing of the operations are stored. The operation unit1112is a part which performs operations in the processor1100. The operation unit1112may perform four arithmetical operations, logical operations, according to results that the control unit1113decodes commands, or the like. The operation unit1112may include at least one arithmetic logic unit (ALU) and so on. The control unit1113may receive signals from the memory unit1111, the operation unit1112and an external device of the processor1100, perform extraction, decoding of commands, controlling input and output of signals of processor1100, and execute processing represented by programs.

The cache memory unit1120is a part which temporarily stores data to compensate for a difference in data processing speed between the core unit1110operating at a high speed and an external device operating at a low speed. The cache memory unit1120may include a primary storage section1121, a secondary storage section1122and a tertiary storage section1123. In general, the cache memory unit1120includes the primary and secondary storage sections1121and1122, and may include the tertiary storage section1123in the case where high storage capacity is required. As the occasion demands, the cache memory unit1120may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit1120may be changed according to a design. The speeds at which the primary, secondary and tertiary storage sections1121,1122and1123store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections1121,1122and1123are different, the speed of the primary storage section1121may be largest. At least one storage section of the primary storage section1121, the secondary storage section1122and the tertiary storage section1123of the cache memory unit1120may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit1120may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the cache memory unit1120and the processor1100may have improved reliability.

Although it was shown inFIG. 12that all the primary, secondary and tertiary storage sections1121,1122and1123are configured inside the cache memory unit1120, it is to be noted that all the primary, secondary and tertiary storage sections1121,1122and1123of the cache memory unit1120may be configured outside the core unit1110and may compensate for a difference in data processing speed between the core unit1110and the external device. Meanwhile, it is to be noted that the primary storage section1121of the cache memory unit1120may be disposed inside the core unit1110and the secondary storage section1122and the tertiary storage section1123may be configured outside the core unit1110to strengthen the function of compensating for a difference in data processing speed. In another implementation, the primary and secondary storage sections1121,1122may be disposed inside the core units1110and tertiary storage sections1123may be disposed outside core units1110.

The bus interface1130is a part which connects the core unit1110, the cache memory unit1120and external device and allows data to be efficiently transmitted.

The processor1100according to the present implementation may include a plurality of core units1110, and the plurality of core units1110may share the cache memory unit1120. The plurality of core units1110and the cache memory unit1120may be directly connected or be connected through the bus interface1130. The plurality of core units1110may be configured in the same way as the above-described configuration of the core unit1110. In the case where the processor1100includes the plurality of core unit1110, the primary storage section1121of the cache memory unit1120may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the secondary storage section1122and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130. The processing speed of the primary storage section1121may be larger than the processing speeds of the secondary and tertiary storage section1122and1123. In another implementation, the primary storage section1121and the secondary storage section1122may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130.

The processor1100according to the present implementation may further include an embedded memory unit1140which stores data, a communication module unit1150which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit1160which drives an external memory device, and a media processing unit1170which processes the data processed in the processor1100or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor1100may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units1110and the cache memory unit1120and with one another, through the bus interface1130.

The embedded memory unit1140may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), a memory with similar functions.

The memory control unit1160is to administrate and process data transmitted between the processor1100and an external storage device operating according to a different communication standard. The memory control unit1160may include various memory controllers, for example, devices which may control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit1170may process the data processed in the processor1100or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit1170may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 13is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 13, a system1200as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations for data. The system1200may include a processor1210, a main memory device1220, an auxiliary memory device1230, an interface device1240, and so on. The system1200of the present implementation may be various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor1210may decode inputted commands and processes operation, comparison, etc. for the data stored in the system1200, and controls these operations. The processor1210may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device1220is a storage which can temporarily store, call and execute program codes or data from the auxiliary memory device1230when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device1220may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the main memory device1220may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the main memory device1220and the system1200may have improved reliability.

Also, the main memory device1220may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device1220may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device1230is a memory device for storing program codes or data. While the speed of the auxiliary memory device1230is slower than the main memory device1220, the auxiliary memory device1230can store a larger amount of data. The auxiliary memory device1230may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device1230may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the auxiliary memory device1230and the system1200may have improved reliability.

Also, the auxiliary memory device1230may further include a data storage system (see the reference numeral1300ofFIG. 14) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device1230may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral1300ofFIG. 14) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device1240may be to perform exchange of commands and data between the system1200of the present implementation and an external device. The interface device1240may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 14is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 14, a data storage system1300may include a storage device1310which has a nonvolatile characteristic as a component for storing data, a controller1320which controls the storage device1310, an interface1330for connection with an external device, and a temporary storage device1340for storing data temporarily. The data storage system1300may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device1310may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on.

The controller1320may control exchange of data between the storage device1310and the interface1330. To this end, the controller1320may include a processor1321for performing an operation for, processing commands inputted through the interface1330from an outside of the data storage system1300and so on.

The interface1330is to perform exchange of commands and data between the data storage system1300and the external device. In the case where the data storage system1300is a card type, the interface1330may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system1300is a disk type, the interface1330may be compatible with interfaces, such as IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface1330may be compatible with one or more interfaces having a different type from each other.

The temporary storage device1340can store data temporarily for efficiently transferring data between the interface1330and the storage device1310according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device1340for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the temporary storage device1340may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the temporary storage device1340and the data storage system1300may have improved reliability.

FIG. 15is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 15, a memory system1400may include a memory1410which has a nonvolatile characteristic as a component for storing data, a memory controller1420which controls the memory1410, an interface1430for connection with an external device, and so on. The memory system1400may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory1410for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory1410may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the memory1410and the memory system1400may have improved reliability.

Also, the memory1410according to the present implementation may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller1420may control exchange of data between the memory1410and the interface1430. To this end, the memory controller1420may include a processor1421for performing an operation for and processing commands inputted through the interface1430from an outside of the memory system1400.

The interface1430is to perform exchange of commands and data between the memory system1400and the external device. The interface1430may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface1430may be compatible with one or more interfaces having a different type from each other.

The memory system1400according to the present implementation may further include a buffer memory1440for efficiently transferring data between the interface1430and the memory1410according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory1440may include semiconductor memory which includes a variable resistance element. The variable resistance element may include a variable resistance pattern in which a first electrode layer, a variable resistance layer and a second electrode layer are sequentially stacked; and a switching assist structure including multilayered conductive structures which are spaced from a side wall of the variable resistance pattern to surround the variable resistance pattern and are vertically spaced from one another. The switching assist structure may have a single conductive line shape in which the multilayered conductive structures are coupled in series between a first node of one end of the switching assist structure and a second node of the other end thereof. The semiconductor memory may reduce a driving current required for switching the variable resistance element by including the variable resistance element including the switching assist structure. Therefore, the semiconductor memory with improved operation characteristics may be provided. Through this, the buffer memory1440and the memory system1400may have improved reliability.

Moreover, the buffer memory1440according to the present implementation may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory1440may not include the semiconductor devices according to the implementations, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

Features in the above examples of electronic devices or systems inFIGS. 11 to 15based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

Only a few implementations and examples are described. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.