Semiconductor memory apparatus

A semiconductor memory apparatus includes: a line calibration unit configured to selectively output one signal from the group of code signals for calibrating termination resistance values and test mode signals for testing a chip of the semiconductor memory apparatus to a common global line based on the level of a line calibration signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2010-0040547, filed on Apr. 30, 2010, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.

2. Related Art

As semiconductor memory devices become more highly integrated and high-performing, efforts to reduce the chip area are taking place with respect to semiconductor memory device manufacturing processes and circuit arrangement methods (i.e., layout), as well as in the area of circuits.

FIG. 1is a block diagram schematically illustrating a conventional semiconductor memory apparatus.

Referring toFIG. 1, the conventional semiconductor memory apparatus10includes an impedance calibration block (a ZQ calibration block)12. The impedance calibration block12generates first and second code signals (PCODE<0:M-1> and NCODE<0:M-1>, respectively), which vary depending on PVT (process, voltage and temperature) conditions, and calibrates termination resistance values of input/output blocks14by using first code signals and second code signals generated as a result of impedance calibration. Since the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1> have a predetermined number of bits, a plurality of lines are required.

Meanwhile, the semiconductor memory apparatus10has lines for a plurality of test mode signals TM<0:N-1> used for testing a chip, in addition to lines for the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>. Accordingly, the semiconductor memory apparatus10uses numerous global lines, resulting in the problem of increased chip area.

SUMMARY

Accordingly, various exemplary embodiments of the invention described herein may provide a semiconductor memory apparatus with a reduced area.

In one embodiment of the present invention, a semiconductor memory apparatus includes: a line calibration unit configured to selectively output one code signal for calibrating termination resistance values or one test mode signal for testing semiconductor memory chips, to a common global line based on the level of a line calibration signal.

In another embodiment of the present invention, semiconductor memory apparatus includes a common global line control block configured to output one code signal or one test mode signal to a common global line in response to a line calibration signal inputted from outside of the semiconductor memory apparatus, and to control the signal outputted to the common global line to be inputted to a corresponding block in response of the line calibration signal.

DETAILED DESCRIPTION

Exemplary embodiments of a semiconductor memory apparatus according to the present invention are described below in detail with reference to the accompanying drawings.

FIG. 2is a block diagram illustrating a semiconductor memory apparatus according to one embodiment of the present invention.

Referring toFIG. 2, the semiconductor memory apparatus100according to the embodiment includes an impedance calibration block120, input/output blocks140and a common global line control block160.

The impedance calibration block120is configured to generate a plurality of first code signals PCODE<0:M-1> and a plurality of second code signals NCODE<0:M-1> in response to an inputted impedance command (hereinafter, referred to as a ZQC command).

In detail, the impedance calibration block120is configured to generate first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1> at the initial driving time and at predetermined intervals in response to the ZQC command applied from outside of the semiconductor memory apparatus.

The impedance calibration block120is configured to calibrate a resistance value of an output terminal such that data signals may be transmitted to a subsequent chip without impedance mismatching.

The input/output block140is configured to generate the resistance value of the output terminal based on first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1>, which are provided from the impedance calibration block120, such that the data signals may be transmitted to the subsequent chip. Typically, such an input/output block140includes a resistance generation unit (not shown) and an input/output pad (not shown).

The common global line control block160is configured to output one signal among first code signals PCODE<0:M-1>, second code signals NCODE<0:M-1>, and test mode signals TM<0:N-1> in response to a line calibration signal Line_en, which is inputted from outside of the semiconductor memory apparatus100, to a common global line, and to control the outputted signal to be inputted to a corresponding block.

The common global line control block160includes a line calibration unit162, a test mode signal output unit164, and a plurality of pad latch units166.

The line calibration unit162is configured to selectively output one signal among the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>, which are provided from the impedance calibration block120, and the test mode signals TM<0:N-1>, which are provided from test mode lines, to the common global line. In this case, the signals outputted to the common global line are inputted to a corresponding block, that is, the test mode signal output unit164, or the plurality of pad latch units166.

In more detail, when the line calibration signal Line_en is at a first level, the line calibration unit162activates first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1> to be outputted to the common global line.

Meanwhile, when the line calibration signal Line_en is at a second level, the line calibration unit162activates test mode signals TM<0:N-1> to be outputted to the common global line.

Here, the first level represents a low level and the second level represents a high level. However, the first level and the second level are not limited thereto, but may be designed differently. For example, the first level may represent a high level and the second level may represent a low level. The line calibration unit162according to an embodiment is described below in detail with reference toFIG. 3.

The test mode signal output unit164is configured only to output the test mode signals TM<0:N-1>, which are outputted from the line calibration unit162, in response to the line calibration signal Line_en.

In more detail, the test mode signal output unit164is activated only when test mode signals TM<0:N-1> are inputted among the signals outputted from the line calibration unit162(in other words, test mode signals TM<0:N-1>, first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1>). Such a test mode signal output unit164is described below in detail with reference toFIG. 4.

The pad latch units166are configured to output or latch the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>, which are outputted from the line calibration unit162, in response to the line calibration signal Line_en.

Here, when the signals outputted from the line calibration unit162are the test mode signals TM<0:N-1>, the pad latch units166substantially prevent the test mode signals TM<0:N-1> from being inputted, and, at the same time, continuously latch the previously inputted first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1>.

Meanwhile, when the signals outputted from the line calibration unit162are the first code signals PCODE<0:M-1> and/or the second code signals NCODE<0:M-1>, the pad latch units166are enabled to latch first code signals PCODE<0:M-1> and second code is signals NCODE<0:M-1>, which are contemporaneously inputted, and simultaneously output the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1> to the input/output blocks140. This pad latch unit166is described below in detail with reference toFIG. 5.

FIG. 3is a detailed circuit diagram illustrating the line calibration unit in the semiconductor memory apparatus according to one embodiment of the present invention.

Referring toFIG. 3, the line calibration unit162in the semiconductor memory apparatus according to one embodiment includes a first switching section112, which is configured to output the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>, and a second switching section114, which is configured to output the test mode signals TM<0:N-1>.

The first switching section112includes transmission gates M1and M2, and is activated based on the level of the line calibration signal Line_en inputted from outside of the semiconductor memory apparatus100, thereby outputting the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>.

In more detail, when the line calibration signal Line_en is inputted at a first level, the first switching section112is turned on such that the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1> provided from the impedance calibration block120are outputted. Here, the first level preferably represents a low level.

The second switching section114includes transmission gates M3and M4, and is activated based on the level of the line calibration signal Line_en, thereby outputting the test mode signals TM<0:N-1>.

In more detail, when the line calibration signal Line_en is inputted at a second level, the second switching section114is turned on such that the test mode signals TM<0:N-1> are outputted. Here, the second level preferably represents a high level.

FIG. 4is a detailed circuit diagram illustrating the test mode signal output unit in the semiconductor memory apparatus according to one embodiment.

Referring toFIG. 4, the test mode signal output unit164in the semiconductor memory apparatus according to one embodiment is configured to output the test mode signals TM<0:N-1> in response to the line calibration signal Line_en.

To this end, the test mode signal output unit164is configured to receive the line calibration signal Line_en and either the test mode signals TM<0:N-1> or the first code signals PCODE<0:M-1> or the second code signals NCODE<0:M-1>. The test mode signal output unit164includes a NAND gate NAND116configured to output the test mode signals TM<0:N-1> in response to the line calibration signal Line_en.

FIG. 5is a detailed circuit diagram illustrating the pad latch unit in the semiconductor memory apparatus according to one embodiment.

Referring toFIG. 5, the pad latch unit166in the semiconductor memory apparatus according to one embodiment includes a third switching section118and a latch section119.

The third switching section118includes transmission gates M5and M6, and is configured to output the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1> to the input/output block140in response to the level of the line calibration signal Line_en, which is inputted from outside of the semiconductor memory apparatus100.

In more detail, when the line calibration signal Line_en is at the first level, the third switching section118outputs the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>, which are provided from the impedance calibration block120, to the input/output blocks140.

Meanwhile, when the line calibration signal Line_en is at the second level, the third switching section118is deactivated such that the test mode signals TM<0:N-1> are not inputted thereto.

When the third switching section118is deactivated, the latch section119continuously stores the values of previously-inputted first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1>. Then, when the third switching section118is activated, the latch section119latches first code signals PCODE<0:M-1> and second code signals NCODE<0:M-1>, which are contemporaneously inputted, and simultaneously outputs the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1> to the input/output blocks140.

Here, the latch section119includes a third inverter IV3, which is configured to receive the values of the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>, and a fourth inverter IV4connected to the third inverter IV3using a latch structure.

In the conventional art, since 2M first and second code signal lines and N test mode signal lines (in other words, a total of 2M+N global lines) are used, the ability to reduce the area of a semiconductor memory apparatus is limited.

However, the present invention allows for the reduction in the number of global lines by interchangeably using first code signal lines, second code signal lines, and test mode signal lines. Consequently, the area of the semiconductor memory apparatus according to one embodiment may be reduced.

While certain embodiments are described above, those skilled in the art will understand that such embodiments are examples only. Accordingly, the semiconductor memory apparatus described herein should not be limited based on the described embodiments. Rather, the semiconductor memory apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.