Pseudo butted junction structure for back plane connection

Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.

BACKGROUND

The present invention relates generally to semiconductor device fabrication and, more particularly, to back gates for SOI devices, methods of forming back gates, and design structures for integrated circuits including the SOI devices.

Semiconductor devices must constantly offer higher performance in a smaller size to satisfy the demand for increased computing power and functionality from integrated circuits. As feature sizes shrink with advances in technology, the dimensions of the spaces between devices are correspondingly reduced. One of the barriers to further improvements in chip densities encountered with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology is maintaining device isolation with increasing device density. Devices sharing the same bulk semiconductor typically rely on p-n junctions for isolation and, as dimensions shrink, leakage currents and latch-up resulting from unwanted interactions between devices can limit the integration densities achievable.

Devices fabricated using semiconductor-on-insulator (SOI) technologies provide certain performance improvements, such as lower parasitic junction capacitance, increased latchup resistance, and reduced power consumption at equivalent performance, in comparison with comparable devices built directly in a bulk silicon substrate. Generally, an SOI wafer includes a thin SOI layer of semiconductor material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate or a silicon epilayer on a bulk silicon substrate), and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the SOI layer from the bulk substrate. In one manifestation of SOI technology, the transistor is devised such that if the BOX layer is thin enough that the electrical potential of the silicon bulk can conveniently influence the transistor.

Therefore, there is a need for improved device structures that can be fabricated that provide increased integration densities and improved device performance, as well as methods of making these device structures and design structures for an integrated circuit.

BRIEF SUMMARY

In an embodiment, a method is provided for forming a device structure on a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate of a first conductivity type, and buried dielectric layer between the semiconductor layer and the bulk substrate. The method includes forming a first back gate of the first conductivity type in the bulk substrate. The method further includes forming a second back gate of a second conductivity type in the bulk substrate and laterally adjacent to the first back gate so that a portion of the first back gate spatially coincides with a portion of the second back gate to define an overlapping region electrically coupling the second back gate with the bulk substrate.

In another embodiment, a device structure is formed on a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate of a first conductivity type, and buried dielectric layer between the semiconductor layer and the bulk substrate. The device structure includes a first back gate of the first conductivity type and a second back gate of a second conductivity type in the bulk substrate. The first back gate is electrically coupled with the bulk substrate of the first conductivity type, which may be p-type. The second back gate is laterally adjacent to the first back gate. An overlapping region is defined by spatial coincidence of a portion of the first back gate and a portion of the second back gate. The overlapping region is configured to electrically couple the second back gate with the first back gate so that the second back gate is electrically coupled with the bulk substrate.

In another embodiment, a design structure is provided that is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate of a first conductivity type, and buried dielectric layer between the semiconductor layer and the bulk substrate. The design structure further includes a first back gate of the first conductivity type and a second back gate of a second conductivity type in the bulk substrate. The first back gate is electrically coupled with the bulk substrate of the first conductivity type. The second back gate is laterally adjacent to the first back gate. The design structure further includes an overlapping region defined by spatial coincidence of a portion of the first back gate and a portion of the second back gate. The overlapping region is configured to electrically couple the second back gate with the first back gate so that the second back gate is electrically coupled with the bulk substrate. The design structure may comprise a netlist. The design structure may also reside on storage medium as a data format used for the exchange of layout data of integrated circuits. The design structure may reside in a programmable gate array.

DETAILED DESCRIPTION

Embodiments of the present invention generally provide back gates for field effect transistors formed using a semiconductor-on-insulator (SOI) wafer or an extremely thin silicon on insulator (ETSOI) wafer. Oppositely-doped regions defining back gates may share a region of overlapping doping and a damage region may be formed in the overlapping region by, for example, ion implantation to define a leaky junction between the back gates. The leaky junction provides an electrical connection between the substrate and the back gate having opposite conductivity type to the substrate. As a result, the back gate of opposite conductivity type is not electrically floating relative to the substrate and any floating body effect is mitigated or eliminated.

With reference toFIG. 1and in accordance with an embodiment of the invention, an SOI wafer10includes a bulk substrate12, which may be formed of p−silicon, a buried dielectric layer14, and an SOI layer16physically and electrically separated from the substrate12by the buried dielectric layer14. The SOI layer16may be composed of silicon or another semiconductor material recognized as suitable for device fabrication by a person having ordinary skill in the art. In a representative ETSOI construction, the SOI layer16may be crystalline silicon having a representative thickness of 20 nm or less and the buried dielectric layer14may have a representative thickness of 50 nm or less.

With reference toFIG. 2in which like reference numerals refer to like features inFIG. 1and at a subsequent fabrication stage, doped regions22,24containing semiconductor material of a first conductivity type are formed in the substrate12below the buried dielectric layer14. A masking layer18is applied to a top surface17of the SOI layer16and windows or openings20are formed in the masking layer18. The openings20are aligned with the intended locations of the doped regions22,24in the substrate12. Energetic ions, as indicated by the single-headed arrows19, are introduced using ion implantation at a selected kinetic energy and dose. The energetic ions19penetrate through the buried dielectric layer14and the SOI layer16to reach the substrate12. The masking layer18operates as an ion-implantation mask that protects the covered surfaces of the SOI layer16and substrate12from receiving an implanted dose of the ions19. The areas of the openings20define the respective areas of the doped regions22,24in a plane parallel to the top surface17if lateral straggle of ions19is neglected from the area determination.

The first conductivity type of the doped regions22,24is opposite to the conductivity type of the substrate12. In a representative embodiment, the doped regions22,24may be implanted with a species that is an n-type dopant, such as phosphorous (P), arsenic (As), or antimony (Sb). The implant conditions, such as dose and kinetic energy, are selected to provide a projected range and a dopant concentration that defines the doped regions22,24in the substrate12. Representative dopant concentrations for the doped regions22,24may be 1×1018atoms per cm3or higher. Multiple implantations may be used to form the doped regions22,24.

The masking layer18may be formed of a resist layer that is applied to the top surface17and photolithographically patterned in a conventional manner, and for which the thickness is selected to provide the needed stopping of ions19outside of the openings20. The masking layer18may be removed from the top surface17by ashing or solvent stripping and a conventional cleaning process is applied.

With reference toFIG. 3in which like reference numerals refer to like features inFIG. 2and at a subsequent fabrication stage, a doped region30is formed in the substrate12below the buried dielectric layer14laterally adjacent to the doped region22of opposite conductivity type. The doped region30participates in forming an overlapping region32that is shared with the doped region22. The overlapping region32represents a section or portion of the doped region22that spatially coincides with a section or portion of doped region30to share a volume of semiconductor material within the substrate12. The overlapping region32has a conductivity type determined by a net dopant concentration of the dopants of opposite conductivity type in regions22,30. The overlapping region32, which is located between the non-overlapping portions of the doped regions22,30, may form a butted junction between the doped regions22,30if the doping levels are high enough to create a tunnel diode in this regions, typically 1×1019atoms per cm3or higher. The overlapped portions of doped regions22,30represent a minor fraction of the respective total doped volumes of the semiconductor material of substrate12.

A masking layer26is applied to the top surface17of the SOI layer16and a window or opening28containing semiconductor material of a second conductivity type is formed in the masking layer26. The window28is aligned with the intended location of the doped region30in the substrate12. Energetic ions, as indicated by the single-headed arrows27, are introduced using ion implantation at a selected kinetic energy and dose. The energetic ions27penetrate through the buried dielectric layer14and the SOI layer16to reach the substrate12. The masking layer26operates as an ion-implantation mask that protects the covered surfaces of the SOI layer16and substrate12from receiving an implanted dose of the ions27. The area of the opening28defines the area of the doped region30in a plane parallel to the top surface17, if lateral straggle of ions27is neglected, as well as the extent of the overlap with doped region22to produce the overlapping region32containing implanted impurity species of the opposite dopant types.

The conductivity type of the doped region30is opposite to the conductivity type of the doped regions22,24and the same conductivity type as the substrate12. In this representative embodiment, the doped region30may be implanted with a species that is a p-type dopant, such as boron (B), aluminum (Al), gallium (Ga), or indium (In). The implant conditions, dose and kinetic energy, are selected to provide a projected range and a dopant concentration that defines the doped region30and the overlapping region32in the substrate12. Representative dopant concentrations for the doped region30may be 1×1018atoms per cm3or higher.

The masking layer26may be formed of a resist layer that is applied and photolithographically patterned in a conventional manner, and for which the thickness is selected to provide the needed ion stopping outside of the opening28to the top surface17. The masking layer26may be removed from the top surface17by ashing or solvent stripping and a conventional cleaning process is applied.

One or more anneals may be used to electrically activate and diffuse the implanted impurities in the doped regions22,24, doped region30, and the overlapping region32, as well as to repair the primary implantation damage to the crystalline lattice from the implantations.

With reference toFIG. 4in which like reference numerals refer to like features inFIG. 3and at a subsequent fabrication stage, a damage region34is formed in the doped region30and in the overlapping region32. The damage region34may be formed using the same masking layer26previously used to form the doped region30and the overlapping region32. This commonality of the window28in the ion-implantation mask localizes the damage region34in a plane parallel to the top surface17and results in self-alignment of the damage region34with the doped region30and the overlapping region32. The addition of the damage region34to the overlapping region32modifies the structure of the overlapping region32to electrically couple, via an ohmic contact and a leakage current, the doped region22of opposite conductivity type to the bulk substrate12with the doped region30and thereby with the bulk substrate12even if the doping level is not high enough to form a tunnel junction.

The damage region34may contain crystalline defects formed by implanting energetic ions, as indicated diagrammatically by singled-headed arrows29, with selected implant conditions into the substrate12. The area of the opening28defines the area of the damage region34in a plane parallel to the top surface17. The masking layer26may protect the covered surfaces of the SOI layer16and substrate12from receiving an implanted dose of the ions29. In particular, the doped region24and the portion of doped region22that does not contribute to the overlapping region32are masked by the masking layer26against being implanted with the ions29. The crystalline defects introduce midgap energy levels in the bandgap of the semiconductor material forming the bulk substrate12.

In one embodiment, ions29may be generated from silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), carbon (C), an inert gas such as argon (Ar) or xenon (Xe), or some combination thereof. The kinetic energy of the ions29is selected to provide a projected range and a range straggle within the substrate12that confines the damage region34to a band that is contained in depth relative to the top surface17within the shallow and deep boundaries of the regions30,32. The implanted dose of ions29is selected to promote the formation of defects in the damage region34and, as a result, causes crystalline damage in both the overlapping region32and doped region30.

The energetic ions29, as they penetrate into the SOI wafer10, lose energy via scattering events with atoms and electrons in the lattice structure of the constituent semiconductor material. Electronic energy losses dominate at relatively high energies and shallow depths in the SOI layer16, and nuclear energy losses dominate at relatively low energies and near the projected range in the substrate12. Energy lost by the ions29in electronic interactions is subsequently transferred to phonons, which produces heating but little or no permanent crystalline damage to the SOI layer16. Energy lost in nuclear collisions displaces target atoms of the substrate12from their original lattice sites, which damages the lattice structure of the substrate12and causes point defects. The point defects may accumulate in larger aggregates to form dislocations or even voids. For example, a thermal anneal applied to the structure may induce uncombined points defect and inert gas atoms to agglomerate and form voids.

The damage region34contains point defects and inert gas atoms from the stopped ions29and extends horizontally in a plane substantially parallel to the top surface17. The point defects and inert gas atoms from the stopped ions29have similar depth profiles each distributed with a range straggle about a projected range, which is measured as a perpendicular distance of the maximum ion concentration and a maximum point defect peak from the top surface17. Essentially all of the implanted ions29stop within a distance of roughly three times the range straggle from the projected range, which implies that the depth profile for the point defects is spatially similar to the depth profile for the inert gas atoms.

The masking layer26may be removed by ashing or solvent stripping and a conventional cleaning process is applied.

In an alternative embodiment, the doped regions22,24may be formed after formation of the doped region30and damage region34. In another alternative embodiment, the doped regions24may be formed simultaneously with the doped region30by adjusting the ion implantation mask for region30and damage region34may be formed using the same implantation mask as used to form doped region22. In this manner, the overlapping region32still contains the damage region34, but the doped region22has the same conductivity type as the doped region30.

With reference toFIG. 5in which like reference numerals refer to like features inFIG. 4and at a subsequent fabrication stage, field effect transistor (FET) devices35,36,70are formed using the SOI wafer10. Active regions37,38,41of the SOI layer16may be defined by isolation regions39formed using, for example, a shallow trench isolation (STI) process. The STI process may include formation of a patterned hardmask on the SOI layer16and reactive ion etching (RIE) to form trenches by etching through the SOI layer16down to the buried dielectric layer14. The trenches may be filled by deposition of an STI oxide, such as silicon dioxide (SiO2), followed by planarization using a chemical mechanical polishing (CMP) process to form isolation regions39. The hardmask may then be removed from the SOI layer16using a wet or dry etching process.

Dopants may be introduced into active regions37,38,41to provide channel doping for the devices35,36,70. The channels of each individual device may be selectively doped with either an n-type or p-type doping, or left un-doped, depending on the type of device35,36,70. The channel doping process may include forming of a sacrificial oxide layer on the SOI layer16. The sacrificial oxide layer may then be patterned using photolithographic and etching methods so that windows are formed in the sacrificial oxide over the active region37,38to be doped, followed by ion implantation and activation steps. Alternatively, the formation of the sacrificial oxide layer may be omitted, and a patterned resist layer used as an ion-implantation mask. The active regions37,38,41may be composed of n-type semiconductor material formed by implanting a dopant such as P, As, Sb, or other suitable n-type dopant or p-type semiconductor material formed by implanting a dopant such as B, Al, Ga, In, or any other suitable p-type dopant. After ion implantation is complete, the sacrificial oxide layer is removed. Alternatively, if all devices35,36,70are destined to have undoped channels, active region doping may be omitted.

The FET devices35,36may be formed before device70. To that end, gate stacks including a gate insulator layer40, a metal gate layer42, and a polysilicon gate layer44are formed for each of the FET devices35,36. The gate insulator layer40may then be formed by depositing a high-K dielectric material using a thin film deposition process, such as Atomic Layer Deposition (ALD), or Metal-Organic Chemical Vapor Deposition (MOCVD). The metal gate layer42may then be deposited over the gate insulator layer40using a process such as physical vapor deposition, MOCVD or ALD, and may be followed by deposition of the polysilicon gate layer44, which may be deposited through Low Pressure Chemical Vapor Deposition (LPCVD) or sputtering. Photolithography and RIE are used to define the gate stack from the gate insulator layer40, the metal gate layer42, and the polysilicon gate layer44.

Dielectric layers46,48and temporary nitride spacers (not shown) are formed adjacent to the layers40,42,44of the gate stack. Elevated or raised source/drain regions50are formed adjacent on the active regions37,38adjacent to the gate stack of each of the devices35,36. An epitaxial growth process to selectively deposit a semiconductor, such as silicon, silicon germanium (SiGe), silicon carbide (SiC), or mixtures of silicon, carbon and germanium, to form the raised source/drain regions50. The temporary nitride spacers space the respective gate stacks from the raised source/drain regions50. Additional oxide cap and nitride cap layers (not shown) may also be formed on top of the polysilicon gate layer44to prevent deposition of epitaxial silicon on the gate stack when the raised source/drain regions50are formed. A thin oxide layer (not shown) may be formed on the raised source drain regions50.

The raised source/drain regions50for n-channel FET devices35,36may be doped with a dopant such as P, As, Sb, or other suitable n-type dopant, while raised source/drain regions50for p-channel FET devices35,36may be implanted with a dopant such as B, Al, Ga, or any other suitable p-type dopant. The dopants may be introduced by ion implantation using the temporary nitride spacers as a self-aligning mask and separate resist masks during n-type and p-type dopant implantations. The FET devices35,36may be of the same type or of different types.

The temporary nitride spacers are removed by a selective etch, such as a hot phosphoric acid etch, with the dielectric layer48and the thin oxide layer acting as etch stops. Permanent nitride spacers52are formed by depositing a nitride layer on the SOI wafer10, applying a patterned resist layer as an etch mask, followed by etching using RIE, with the thin raised source/drain oxide layers again acting as a vertical etch stop.

Silicide areas45,54may then be formed to provide contacts and lower the sheet resistance of the raised source/drain regions50and the polysilicon gate layer44. The silicide areas45,54may be formed by removing the thin raised source/drain oxide and gate oxide cap, depositing Titanium (Ti), Cobalt, (Co), Nickel (Ni), Tungsten (W), Platinum (Pt), or any other suitable metal for forming a silicide, followed by annealing and etching steps, to form silicide areas45,54on the raised source/drain regions50and polysilicon gate layer44.

Device70is formed using the semiconductor material in active region41of the SOI layer16at a location above the doped region22. The device70may consist of a metal-oxide-semiconductor field effect transistors (MOSFET) having heavily doped source/drain diffusions or regions66,68, a gate dielectric60, and a gate electrode62. Contingent upon the specific device type, source/drain region66may act as a drain and source/drain region68may act as a source, or the converse associations may apply. The gate electrode62is located above a planar channel, which is generally defined in the SOI layer16between the doped semiconductor material of the source/drain regions66,68. The thin gate dielectric layer60electrically insulates the gate electrode62from the channel, which is lightly doped to have a conductivity type opposite to the conductivity type of the semiconductor material contained in the source/drain regions66,68.

Candidate dielectric materials for the gate dielectric layer60include, but are not limited to, silicon oxynitride (SiOxNy), silicon nitride (Si3N4), silicon dioxide (SiO2), a hafnium-based dielectric material like hafnium oxide (HfO2) or hafnium oxynitride (HfSiON), and layered stacks of these and other dielectric materials. The material used to form the gate electrode62may be, for example, polysilicon, a metal like tungsten or a tungsten alloy, or any other suitable conductor. The source/drain regions66,68and their extensions and halos may be formed by diffusion and/or ion implantation of suitable dopant species. The source/drain regions66,68and their extensions and halos may be doped to form either an n-channel MOSFET or a p-channel MOSFET. Sidewall spacers64of a material such as Si3N4are applied to the vertical sidewalls of the gate electrode62by a spacer formation technique familiar to a person having ordinary skill in the art. The elements of the device70are fabricated by conventional processes familiar to a person having ordinary skill in the art of device manufacturing.

In an alternative embodiment, FET device70may have a construction identical to the FET devices35,36.

In operation, doped region22may form an n-type back gate for FET device35, which may lower the conduction band in the channel of device35relative to its Fermi level and thereby decrease the threshold voltage, VT, of device35. Likewise, doped region30may form a p-type back gate for FET device36, raising the conduction band in the channel of device36relative to its Fermi level and thereby increasing the VTof device36. Thus, in embodiments of the invention, the VTof each of the overlying FET devices35,36may be adjusted independently of its channel doping by altering the doping level of its respective back gate. In one embodiment, the FET devices35,36may be of the same type (i.e., source/drain doping) and be characterized by different threshold voltages due to the electrically-coupled doped regions22,30. A back-gate voltage (VBG) applied to the electrically-coupled doped regions22,30can be used to modulate the threshold voltages of both FET devices35,36. The modulation to provide different threshold voltages can be achieved without changing the front gate structures to have different work functions.

For device pairs having oppositely doped regions22,30forming back gates, it may be desirable for the back gates of both devices35,36to be tightly coupled so that they are at the same back-gate voltage. The doped region30, which has the same doping type as the substrate12, is electrically connected to the substrate12. The back-gate potential of the doped region30may therefore be adjusted by controlling the voltage on the substrate12. The overlapping region32in conjunction with the damage region34defines a pseudo butted junction that enables a leakage current, under given back-gate bias, to flow between the doped regions22,30so that the junction therebetween is leaky.

However, a back gate of opposite doping type (e.g., doped region24) from the substrate12may form depletion regions at the boundary between the back gate and the substrate12, preventing free carrier movement across the boundary. As a result, the doped region24is electrically isolated from the VBGapplied to the electrically-coupled doped regions22,30. As a result, the threshold voltage for the FET device70can be independently adjusted by applying a different back-gate voltage (VBG) to the doped region24.

By partially overlapping the back gates defined by doped regions22,30in the overlapping region32and forming the damage region34in the overlapping region32, doped region22may be coupled to the substrate12without formation of contacts below the buried dielectric layer14and extending through the dielectric layer14from above. The defects in the damage region34may reduce the carrier lifetime in the overlapping region32between the doped region22forming the back gate for device35and the doped region30forming the back gate for device36. The resulting increased carrier recombination in the overlapping region32may allow conduction between doped regions22,30by forming a leaky junction. The defects in the damage region34may also increase carrier recombination in doped region30. However, because the doped region30and substrate12have a common conductivity type, the increased recombination rate in doped region30may be inconsequential because region30may be inherently conductive with the substrate12. Doped region22may thus be coupled to substrate12through a conduction path that includes the overlapping region32and doped region30.

Doped region24is not impacted by the overlapping implants or the damage region34. As a result, doped region24may form a non-leaky back gate that is electrically floating and a p-n junction with the bulk substrate12of opposite conductivity type. Therefore, the doped region24may be used for other purposes, such as to form an p-n junction diode, or as a back gate to adjust the threshold voltage, VT, of thick oxide devices by forming a contact (not shown) with doped region24and applying a back gate bias voltage independent of the substrate voltage.

By allowing doped regions22,30of adjacent complementary devices to overlap, and introducing defects in damage region34into the back gate having the same doping type as the substrate12, oppositely doped regions22,30may be selectively conductively coupled to the substrate12by adjusting the back gate ion implantation mask pattern. Doped region22is made non-floating without the need for metalized contacts or interconnects below the buried dielectric layer14. This may allow more flexible device positioning and higher integration densities because devices having alternately doped back gates may no longer require substrate contact structures to prevent floating. Design rules requiring devices having back gates that are alternately doped from the substrate12be aligned in a row so that the back gates can share a single contact may no longer be necessary, allowing complementary devices to be placed randomly as required. This feature may allow devices having high VTto be fabricated directly adjacent to devices having low VTwithout regard to horizontal orientation, giving integrated circuit designers more flexibility than processes requiring like devices to be immediately adjacent to each other in a row. Accordingly, the defects in the damage region34and the presence of the overlapping region32may simplify device fabrication, and may allow more flexible device placement between complementary devices, which may increase integration densities and circuit performance.

Design flow100may vary depending on the type of representation being designed. For example, a design flow100for building an application specific IC (ASIC) may differ from a design flow100for designing a standard component or from a design flow100for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG. 6illustrates multiple such design structures including an input design structure102that is preferably processed by a design process104. Design structure102may be a logical simulation design structure generated and processed by design process104to produce a logically equivalent functional representation of a hardware device. Design structure102may also or alternatively comprise data and/or program instructions that when processed by design process104, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure102may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure102may be accessed and processed by one or more hardware and/or software modules within design process104to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIG. 5. As such, design structure102may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

It will be understood that when an element is described as being “connected” or “coupled” to or with another element, it can be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. In contrast, when an element is described as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. When an element is described as being “indirectly connected” or “indirectly coupled” to another element, there is at least one intervening element present.