Array substrate including non-overlapping line segments and gate lines and manufacturing method therefor, and display device

An array substrate includes gate lines, data lines and an insulating layer. The data lines all extend in a first direction, and the gate lines all extend in a second direction, the first direction intersecting the second direction. A data line includes first line segments and second line segments that all extend in the first direction and are arranged alternately. The second line segments are disposed at a side of the gate lines proximate to the base, and the first line segments are disposed at a side of the gate lines away from the base. There is no overlap among orthographic projections of the first line segments on the base and orthographic projections of the gate lines on the base. The insulating layer includes first vias. In the first direction, any two adjacent first line segments are electrically connected to a second fine segment through at least two first vias.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national phase entry under 35 USC 371 of International Patent Application No. PCT/CN20201097025, filed on Jun. 19, 2020, which claims priority to Chinese Patent Application No. 201910536367.8, filed on Jun. 20, 2019, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method of manufacturing the same, and a display device.

BACKGROUND

As a size and resolution of display panels continue to increase, a length and number of gate lines and data lines in the display panels also increase, resulting in an increased voltage drop (i.e., a voltage difference generated between a signal input terminal of a signal line and a distal end of the signal line opposite to the signal input terminal due to an inherent resistance of the signal line) of the gate lines and data lines.

SUMMARY

In one aspect, an array substrate is provided. The array substrate includes a base, a plurality of gate lines and a plurality of data lines disposed on the base, and an insulating layer disposed between the plurality of first line segments and the plurality of second line segments. The plurality of data lines all extend in a first direction, and the plurality of gate lines all extend in a second direction, the first direction intersecting the second direction. At least one of the plurality of data lines includes a plurality of first line segments and a plurality of second line segments that all extend in the first direction, the plurality of first line segments and the plurality of second line segments being arranged alternately. The plurality of second line segments are disposed at a side of the plurality of gate lines proximate to the base, and the plurality of first line segments are disposed at a side of the plurality of gate lines away from the base. Orthographic projections of the plurality of first line segments on the base are non-overlapping with orthographic projections of the plurality of gate lines on the base. The insulating layer includes a plurality of first vias. In the first direction, any two adjacent first line segments are electrically connected to a second line segment located between the two adjacent first line segments through at least two first vias.

In some embodiments, the base has a plurality of sub-pixel regions. The array substrate further includes a plurality of pixel circuits disposed on the base. Each pixel circuit is disposed in a sub-pixel region, and the pixel circuit is electrically connected to a gate line and a data line. The pixel circuit includes a first switching transistor. A first gate of the first switching transistor and the gate line are disposed in a same layer and made of a same material, and a first source and a first drain of the first switching transistor and the plurality of first line segments are disposed in a same layer and made of a same material.

In some embodiments, in the second direction, a width of the second line segment is greater than a width of the first line segment.

In some embodiments, the first switching transistor is a top-gate thin film transistor. The array substrate further includes a plurality of first metal light-shielding patterns disposed on the base. Each first metal light-shielding pattern is disposed at a side, proximate to the base, of the first switching transistor in a corresponding pixel circuit. An orthographic projection of a first active layer of the first switching transistor in the pixel circuit on the base is located within an orthographic projection of the first metal light-shielding pattern on the base. The plurality of second line segments and the plurality of first metal light-shielding patterns are disposed in a same layer and made of a same material, and the plurality of second line segments are insulated from the plurality of first metal light-shielding patterns.

In some embodiments, the insulating layer further includes a plurality of second vias, and one of the first source and the first drain of the first switching transistor is electrically connected to the first metal light-shielding pattern through at least one second via.

In some examples, in a thickness direction of the base, a thickness of the second line segment is equal to a thickness of the first metal light-shielding pattern.

In some embodiments, the array substrate further includes a plurality of pixel electrodes disposed on the base. Each pixel electrode is disposed in a sub-pixel region. The first source of the first switching transistor is electrically connected to the data line, and the first drain of the first switching transistor is electrically connected to the pixel electrode. The pixel electrode is disposed at a side of the first drain away from the base.

In some embodiments, the array substrate further includes a plurality of light-emitting devices disposed on the base. Each light-emitting device is disposed in a sub-pixel region, and the light-emitting device is connected to a corresponding pixel circuit.

In some embodiments, the pixel circuit further includes a driving transistor, the driving transistor being a top-gate thin film transistor. The array substrate further includes a plurality of second metal light-shielding patterns disposed on the base. Each second metal light-shielding pattern is disposed at a side, proximate to the base, of the driving transistor in a corresponding pixel circuit. An orthographic projection of a second active layer of the driving transistor on the base is located within an orthographic projection of the second metal light-shielding pattern on the base. The plurality of second line segments and the plurality of second metal light-shielding patterns are disposed in a same layer and made of a same material, and the plurality of second line segments are insulated from the plurality of second metal light-shielding patterns.

In some embodiments, the array substrate further includes a plurality of power lines. The plurality of power lines all extend in the first direction, and the pixel circuit is electrically connected to a power line. A power line of the plurality of power lines includes a plurality of third line segments and a plurality of fourth line segments that all extend in the first direction, the plurality of third line segments and the plurality of fourth line segments being arranged alternately. Orthographic projections of the plurality of third line segments on the base are non-overlapping with the orthographic projections of the plurality of gate lines on the base. The plurality of third line segments and the plurality of first line segments are disposed in a same layer and made of a same material, and the plurality of fourth line segments and the plurality of second line segments are disposed in a same layer and made of a same material. The insulating layer further includes the plurality of third vias; and in the first direction, any two adjacent third line segments are electrically connected to a fourth line segment located between the two adjacent third line segments through at least two third vias.

In some embodiments, in the second direction, a width of the fourth line segment is greater than a width of the third line segment.

In some embodiments, the power line is electrically connected to a second source of the driving transistor in the pixel circuit, and a second drain of the driving transistor is electrically connected to an anode of the light-emitting device.

In some embodiments, the insulating layer includes a buffer layer and an interlayer dielectric layer that are stacked on the base.

In another aspect, a display device is provided. The display device includes any one of the array substrates described above.

In yet another aspect, a method of manufacturing an array substrate is provided. The method includes: providing a base; forming a plurality of second line segments on the base, the plurality of second line segments being arranged into a plurality of columns of second line segments in a second direction, and each column of second line segments including a plurality of second line segments extending in a first direction and arranged at intervals, the first direction intersecting the second direction; forming a plurality of gate lines on the base on which the plurality of second line segments have been formed, the plurality of gate lines extending in the second direction; forming an insulating layer on the base on which the plurality of second line segments have been formed, the insulating layer including a plurality of first vias; and forming a plurality of first line segments on the base on which the insulating layer has been formed, orthographic projections of the plurality of first line segments on the base are non-overlapping with orthographic projections of the plurality of gate lines on the base; the plurality of first line segments being arranged into a plurality of columns of first line segments in the second direction, and each column of first line segments including first line segments extending in the first direction and arranged at intervals, and in the first direction, any two adjacent first line segments being electrically connected to a second line segment located between the two adjacent first line segments through at least two first vias; all the first line segments and all the second line segments that are electrically connected in each column constituting a single data line.

In some embodiments, after the plurality of second line segments are formed, the method of manufacturing the array substrate further includes: forming a plurality of pixel circuits on the base on which the plurality of second line segments have been formed, each pixel circuit being located in a sub-pixel region, and the pixel circuit including a first switching transistor. The plurality of gate lines and first gates of the first switching transistors are formed through a single patterning process, and the plurality of first line segments and first sources and first drains of the first switching transistors are formed through a single patterning process.

In some embodiments, the insulating layer includes a buffer layer and an interlayer dielectric layer. Forming the insulating layer, includes: forming a buffer film after the plurality of second line segments are formed and before the plurality of gate lines are formed; forming an interlayer dielectric film after the plurality of gate lines are formed; and patterning the interlayer dielectric film and the buffer film to form the interlayer dielectric layer and the buffer layer that include the plurality of first vias.

In some embodiments, forming the plurality of second line segments, includes: forming the plurality of second line segments and a plurality of first metal light-shielding patterns through a single patterning process, the plurality of second line segments being insulated from the plurality of first metal light-shielding patterns. An orthographic projection of a first active layer of the first switching transistor in the pixel circuit on the base is located within an orthographic projection of a corresponding first metal light-shielding pattern on the base.

In some embodiments, the insulating layer includes the buffer layer and the interlayer dielectric layer. Patterning the interlayer dielectric film and the buffer film to form the interlayer dielectric layer and the buffer layer that include the plurality of first vias, includes: patterning the dielectric film and the buffer film to form the interlayer dielectric layer and the buffer layer that include the plurality of first vias and a plurality of second vias. One of the first source and the first drain of the first switching transistor is electrically connected to the first metal light-shielding pattern through the second via.

DETAILED DESCRIPTION

The expression that C and D are disposed in a same layer and made of a same material means that C and D are located on the same carrying surface, and constitute a layer structure made by forming a film layer for forming specific patterns using the same film formation process, and then patterning the film layer through a patterning process using the same mask. The patterning process may include exposure, development and etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at different heights or have different thicknesses.

In the description of some embodiments, the term “connected” and derivatives thereof may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. However, the term “connected” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

Some embodiments of the present disclosure provide a display device. The display device includes, but is not limited to, a cellphone, a television, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer or a display panel,

FIG.1is a schematic top view of a display panel, in accordance with some embodiments of the present disclosure. As shown inFIG.1, the display panel100has a display area AA and a peripheral area S.

Depending on different designs of the display panel100, a specific position of the peripheral area S may be changed accordingly. For example, the peripheral area S surrounds the display area AA; or, the peripheral area S is located at one or more sides of the display area AA, but does not surround the display area AA.

A plurality of sub-pixels are provided in the display area AA, and each sub-pixel is located in a sub-pixel region P. The plurality of sub-pixels include at least sub-pixels of a first color, sub-pixels of a second color and sub-pixels of a third color. The first color, the second color and the third color are three primary colors (e.g., red, green and blue).

FIG.1illustrates an example in which the plurality of sub-pixels are arranged in an array. As shown inFIG.1, sub-pixels arranged in a line along a horizontal direction X (e.g., a row direction) are referred to as sub-pixels in a same row, and sub-pixels arranged in a line along a vertical direction Y (e.g., a column direction) are referred to as sub-pixels in a same column.

In some examples, the sub-pixels in the same row may be connected to a gate line1, and the sub-pixels in the same column may be connected to a data line2.

The display panel100may be, for example, a liquid crystal display panel or a self-luminous display panel.

In some embodiments, the display panel100is a liquid crystal display panel.

In this case, as shown inFIG.2, the sub-pixel region P is provided therein with a pixel circuit30, a pixel electrode50and a common electrode60. The pixel circuit30includes a first switching transistor.

In some examples, a gate301of the first switching transistor is connected to the gate line1, a source302of the first switching transistor is connected to the data line2, and a drain303of the first switching transistor is connected to the pixel electrode50(as shown inFIG.2).

In some other examples, the gate301of the first switching transistor is connected to the gate line1, the source302of the first switching transistor is connected to the pixel electrode50, and the drain303of the first switching transistor is connected to the data line2.

As shown inFIG.2, the pixel electrode50and the common electrode60are configured to apply an electric field to a liquid crystal molecule layer70in the sub-pixel region P, so that liquid crystal molecules in the liquid crystal molecule layer70rotates under an action of the electric field. It will be noted thatFIG.2only exemplarily illustrates a case where the common electrode60and the pixel electrode50are disposed on two opposite sides of the liquid crystal layer molecule layer70. Of course, the common electrode60and the pixel electrode50may also be disposed at a same side of the liquid crystal molecule layer70.

In some examples, a color filter pattern is further provided in the sub-pixel region P.

It can be understood that a color filter pattern located in the first color sub-pixel is of the first color, a color filter pattern located in the second color sub-pixel is of the second color, and a color filter pattern located in the third color sub-pixel is of the third color.

In some other embodiments, the display panel100is a self-luminous display panel.

In this case, as shown inFIG.3, the sub-pixel region P is provided therein with a pixel circuit30and a light-emitting device40that are located on a base10.

The pixel circuit30includes at least a first switching transistor, a driving transistor, and a capacitor (C for short).

For example, referring toFIG.6, the pixel circuit30may be a pixel circuit of a 2T1C structure. That is, the pixel circuit30includes two thin film transistors (TFTs for short) and one capacitor33. The two TFTs include a switching TFT (e.g., the first switching transistor31inFIG.6) and a driving TFT (e.g., the driving transistor32inFIG.6).

Of course, in addition to the 2T1C structure, the pixel circuit30may also be of other structures, for example, a 3T1C structure (that is, the pixel circuit30includes three TFTs and one capacitor), a 5T1C structure (that is, the pixel circuit30includes five TFTs and one capacitor), or a 7T1C structure (that is, the pixel circuit30includes seven TFTs and one capacitor). That is to say, the pixel circuit30may include at least two TFTs and at least one capacitor. The at least two TFTs include at least one switching TFT and one driving TFT.

As shown inFIG.3, the light-emitting device40includes a cathode45, an anode41, and a light-emitting functional layer located between the cathode45and the anode41.

In an example where the light-emitting device40is an organic light-emitting diode (OLE©), as shown inFIG.3, the light-emitting functional layer includes an organic light-emitting layer43, a hole transport layer42located between the organic light-emitting layer43and the anode41, and an electron transport layer44located between the organic light-emitting layer43and the cathode45.

In some examples, the light-emitting functional layer further includes a hole injection layer disposed between the hole transport layer42and the anode41, and/or an electron injection layer disposed between the electron transport layer44and the cathode45.

It will be noted thatFIG.3only exemplarily shows a schematic structural diagram of the self-luminous display panel, and does not show an electrical connection relationship between the pixel circuit30and the light-emitting device40. The embodiments of the present disclosure do not limit an electrical connection mode of the pixel circuit30and the light-emitting device40, which may be selected according to the structure of the pixel circuit30.

In some embodiments, the light-emitting device40emits white light, and a color filter pattern is further provided in the sub-pixel region P.

A light-emitting type of the light-emitting device40may be a top emission type (that is, light emitted from the light-emitting device40exits from a side of the light-emitting device away from the base10) or a bottom emission type (that is, light emitted from the light-emitting device40passes through the base10and exits).

In some examples, the light-emitting device40is a top emission light-emitting device, and the color filter pattern is located on a side of the light-emitting device40away from the pixel circuit30.

In some other examples, as shown inFIG.3, the light-emitting device40is a bottom emission light-emitting device, and the color filter pattern60is located on a side of the light-emitting device40proximate to the pixel circuit30.

Regardless of the type of the display panel, it always includes an array substrate.

As shown inFIGS.4to7, some embodiments of the present disclosure provide an array substrate200, which includes a base10, and a plurality of gate lines1and a plurality of data lines2disposed on the base10. The plurality of data lines2all extend in a first direction Y, and the plurality of gate lines all extend in a second direction X. The first direction intersects the second direction.

In some examples, as shown inFIG.4, the first direction is perpendicular to the second direction.

As shown inFIGS.4to7, at least one of the plurality of data lines2includes a plurality of first line segments21and a plurality of second line segments22that all extend in the first direction Y. The plurality of first line segments21and the plurality of second line segments22are arranged alternately. For example, each data line2includes a plurality of first line segments21and a plurality of second line segments22that all extend in the first direction Y, and the plurality of first line segments21and the plurality of second line segments22are arranged alternately.

As shown inFIGS.4to7, the plurality of second line segments22in the data line2are disposed at a side of the plurality of gate lines1proximate to the base10, and the plurality of first line segments21in the data line2are disposed at a side of the plurality of gate lines1away from the base10. There is no overlap among orthographic projections of the plurality of first line segments21on the base10and orthographic projections of the plurality of gate lines1on the base10. An orthographic projection of each second line segment22on the base10overlaps with an orthographic projection of a corresponding gate line1on the base10.

As shown inFIGS.5and7, the array substrate200further includes an insulating layer16disposed between the plurality of first line segments21and the plurality of second line segments22. The insulating layer16includes a plurality of first vias81. In the first direction, any two adjacent first line segments21are electrically connected to a second line segment22located between the two first line segments21through at least two first vias81.

For example, as shown inFIGS.4and6, any two adjacent first line segments21are electrically connected to a second line segment22located between the two first line segments21through two first vias81. The two first vias81are located at two opposite sides of a corresponding gate line1in the first direction. An orthogonal projection of one of the first vias81on the base10overlaps with orthographic projections of one of the two first line segments21and the second line segment22on the base10, and an orthogonal projection of another first via81on the base10overlaps with orthographic projections of another first line segment21and the second line segment22on the base10.

In some embodiments, as shown inFIGS.5and7, the insulating layer16includes a buffer layer11and an interlayer dielectric layer15that are stacked on the base10.

The buffer layer11is disposed between the plurality of second line segments22and the plurality of gate lines1, so that the plurality of second line segments22are insulated from the plurality of gate lines1.

The buffer layer11may be of a single-layer or multi-layer structure. For example, the buffer layer11is of a single-layer structure, and a material of the buffer layer11may include, for example, silicon oxide (SiOx) or silicon nitride (SiNx). For another example, the buffer layer11is of a two (or morel-layer structure, and the buffer layer11includes at least one SiOxlayer and at least one SiNxlayer.

The interlayer dielectric layer15is disposed between the plurality of gate lines1and the plurality of first line segments21.

The interlayer dielectric layer15may be of a single-layer or multi-layer structure. For example, the interlayer dielectric layer15is of a single-layer structure, and a material of the interlayer dielectric layer15may include, for example, SiOxor SiNx. For another example, the interlayer dielectric layer15is of a two (or more)-layer structure, and the interlayer dielectric layer15includes at least one SiOxlayer and at least one SiNxlayer.

Referring toFIGS.8and9, in the related art, a plurality of gate lines1intersect with a plurality of first data lines2′, and the first data lines2″ are located at a side of the gate lines1away from the base10. An isolation layer16′ is provided between the gate lines1and the base10, and the isolation layer16′ includes a first interlayer dielectric layer15″ and a first buffer layer11″.

Since the gate line1is very long, especially in a large-size display panel, it may cause a serious voltage drop problem.

Since a magnitude of voltage drop is inversely proportional to a cross-sectional area of a wire (ΔU=L(σ*S), in which ΔU is the voltage drop of the wire, L is a length of the wire, a is a conductivity of a material of the wire, and S is the cross-sectional area of the wire), it can be seen that, in a case where a material with a high conductivity a is used as a material of the gate line, a purpose of reducing the voltage drop may be achieved by increasing the cross-sectional area of the gate line. Based on this, on a premise of not reducing an aperture ratio of the display panel, a thickness of the gate line1in a thickness direction of the base may be increased. In this case, due to a large thickness of the gate line1, there will be a large level difference between portions of the first interlayer dielectric layer15″ that cover the gate lines1and portions of the first interlayer dielectric layer15″ that do not cover the gate lines1. It can be seen that, the greater the thickness of the gate line1, the greater the level difference of the first interlayer dielectric layer15″, The large level difference may cause a thickness of the first interlayer dielectric layer15″ to be non-uniform. As a result, the portions of the first interlayer dielectric layer15″ that cover the gate lines1may be very thin, or some gate lines1may not be covered by the first interlayer dielectric layer15″, thereby reducing a ratio at which the first interlayer dielectric layer15″ covers the gate lines1.

In this case, when the first data lines2′ are formed on the first interlayer dielectric layer15″, due to the large level difference of the first interlayer dielectric layer15″, in one aspect, there is a risk that the first data lines2′ may be disconnected. In another aspect, since the gate lines1and the first data lines2′ are disposed on two opposite sides of the first interlayer dielectric layer15″ and the thickness of the first interlayer dielectric layer15″ is non-uniform, around positions where the gate lines1and the first data lines2′ overlap, metal particles in the gate lines1may easily pass through portions of the first interlayer dielectric layer15″ that are very thin and drift to the first data lines2′ due to electro-static discharge (ESD). Consequently, a problem of data gate short (DGS, i.e., a short circuit between a data line and a gate line) may occur between the first data line2′ and the gate line1.

In addition, due to limitations of process conditions, there are particles in film layer(s) between the gate lines1and the base10. Therefore, a surface of the gate line1away from the base10is uneven, thereby causing the first interlayer dielectric layer15″ to be uneven. Thus, the level difference of the first interlayer dielectric layer15″ and a level difference of the first data line2′ are further increased, and a pass rate of the product is further reduced.

In the array substrate200provided in the embodiments of the present disclosure, the data line2includes the plurality of first line segments21and the plurality of second line segments22in the first direction. The plurality of first line segments21are located at the side of the gate lines1away from the base10, and the plurality of second line segments22are located at the side of the gate lines1proximate to the base10. The insulating layer16includes the plurality of first vias81, so that in the first direction, any two adjacent first line segments21may be electrically connected to the second line segment22located between the two adjacent first line segments21through at least two first vias81, so that the plurality of first line segments21and the plurality of second line segments22that are electrically connected in the first direction may form a single data line2. Since there is no overlap among the orthographic projections of the plurality of first line segments21on the base10and the orthographic projections of the gate lines1on the base10, and any two adjacent first line segments21are connected through the second line segment22located at the side of the gate lines1proximate to the base10(that is, a portion of the data line2that overlaps with the gate line1passes between the gate line1and the base10), the data line2will not cross the gate line1from above. Thus, in the array substrate200provided in the embodiments of the present disclosure, problems such as disconnection of the data line and DGS caused by the large thickness of the gate line1or the particles in the film layers may be effectively avoided, and the pass rate of the product may be effectively improved.

In some embodiments, as shown inFIG.4, the base10has a plurality of sub-pixel regions P, The array substrate200further includes a plurality of pixel circuits30, and each pixel circuit30is disposed in a sub-pixel region P. The pixel circuit30is electrically connected to a gate line1and a data line2.

As shown inFIGS.4and5, the pixel circuit30includes a first switching transistor31. The first switching transistor31includes a first gate311, a first source312, a first drain313, a first active layer314, and a first gate insulating pattern315.

The first gate311of the first switching transistor31and the gate line1connected to the pixel circuit30are disposed in a same layer and made of a same material, and the first source312and the first drain313of the first switching transistor31and the first line segment21are disposed in a same layer and made of a same material. An orthographic projection of the first gate311on the base10is within a range of an orthographic projection of the first active layer314of the first switching transistor31on the base10.

In some examples, as shown inFIG.5, the first switching transistor31is a top-gate thin film transistor. In this case, the first active layer314of the first switching transistor31is located at a side of the first gate311proximate to the base10. The interlayer dielectric layer15is located between a layer where the first source312and the first drain313are located and the first gate311. The first source312and the first drain313are electrically connected to the first active layer314of the first switching transistor31through first connection vias84that penetrate the interlayer dielectric layer15.

In some other examples, the first switching transistor31is a bottom-gate thin film transistor. In this case, the first active layer314of the first switching transistor31is located at a side of the first gate311away from the base10. The interlayer dielectric layer15is located between the layer where the first source312and the first drain313are located and the first active layer314. The first source312and the first drain313are electrically connected to the first active layer314of the first switching transistor31through first connection vias84that penetrate the interlayer dielectric layer15. Herein, the interlayer dielectric layer15may also be referred to as an etching barrier layer.

For example, the material of the first gates311and the gate lines1includes at least one of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W), and other elemental metals. That is, the first gates311and the gate lines1may be made of one of the above elemental metals, or made of an alloy composed of two or more of the above elemental metals.

The material of the first line segments21, and the first sources312and the first drains313of the first switching transistors31may include copper (Cu), aluminum (Al), or other elemental metals.

In some embodiments, as shown inFIG.4, in the second direction X (i.e., the row direction), a width of the second line segment22is greater than a width of the first line segment21. In this way, a pass rate of electrical connection between the first line segment21and the second line segment22may be ensured.

In some embodiments, as shown inFIG.5, the first switching transistor31is a top-gate thin film transistor. The array substrate200further includes a plurality of first metal light-shielding patterns12disposed on the base10. Each first metal light-shielding pattern12is disposed at a side, proximate to the base10, of a first switching transistor31in a corresponding pixel circuit. Since the active layer of the transistor is sensitive to light, and electrical properties of the transistor may easily change when the transistor is exposed to light, it is arranged that the orthographic projection of the first active layer314of the first switching transistor31on the base10is located within an orthographic projection of the first metal light-shielding pattern12on the base10, so that the first metal light-shielding pattern12may block light that travels toward the first active layer314.

The plurality of second line segments22and the plurality of first metal light-shielding patterns12are disposed in a same layer and made of a same material, and the plurality of second line segments22are insulated from the plurality of first metal light-shielding patterns12. In some examples, in a thickness direction of the base10, a thickness of the second line segment22is equal to a thickness of the first metal light-shielding pattern12. In this way, it may be possible to reduce a level difference of the buffer layer11located on a side of the second line segments22and the first metal light-shielding patterns12as much as possible, and thus prevent the pass rate of the display panel from being affected by a large level difference of the buffer layer11.

A material of the second line segments22and the first metal light-shielding patterns12includes Mo, Al, or other metal materials having a light-shielding effect. A material of the first active layer314includes, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AlZnO), zinc oxide (ZnO), or gallium zinc oxide (GZO), or other metal oxides.

Optionally, as shown inFIG.5, the insulating layer16further includes a plurality of second vias82, and one of the first source312and the first drain313of the first switching transistor31is electrically connected to the first metal light-shielding pattern12through at least one second via82.

In some examples, as shown inFIGS.5and10, the first drain313of the first switching transistor31is electrically connected to the first metal light-shielding pattern12through a second via82.

In some other examples, as shown inFIG.11, the first source312of the first switching transistor31is electrically connected to the first metal light-shielding pattern12through a second via82.

The first source312or the first drain313of the first switching transistor31is electrically connected to the first metal light-shielding pattern12, and the first source312and the first drain313are also electrically connected to the first active layer314of the first switching transistor31. In this way, it may be possible to make induced charges at the first metal light-shielding pattern12flow to the first source312and the first drain313, avoiding an influence on the first switching transistor31. In addition, it may be ensured that the first active layer314, the first source312, and the first drain313of the first switching transistor31are at a same potential, thereby improving an electrical stability of the first switching transistor31and improving the electrical properties of the first switching transistor31.

In some embodiments, as shown inFIGS.12and13, the array substrate200further includes a plurality of pixel electrodes50disposed on the base10, and each pixel electrode50is disposed in a sub-pixel region P.

As shown inFIGS.12and13, the first drain313of the first switching transistor31is electrically connected to the pixel electrode50. The pixel electrode50is disposed at a side, away from the base10, of the first drain313of the first switching transistor31.

In some examples, the pixel electrode50may be made of indium tin oxide (ITO).

In some embodiments, as shown inFIGS.12and13, the array substrate200further includes a passivation layer34and an organic insulating layer35that are disposed between the pixel electrodes50and the first drains313of the first switching transistors31. The pixel electrode50may be electrically connected to the first drain313of the first switching transistor31through a third connection via that penetrates the organic insulating layer35and the passivation layer34.

In some examples, a material of the passivation layer34may include an inorganic material, such as silicon nitride; and a material of the organic insulating layer35may include an organic polymer material, such as polymethyl methacrylate (PMMA).

In some embodiments, as shown inFIGS.14and15, the array substrate200further includes a plurality of light-emitting devices40disposed on the base10. Each light-emitting device40is disposed in a sub-pixel region P, and the light-emitting device40is connected to a pixel circuit30located in the sub-pixel region P.

In some embodiments, as shown inFIG.6, the pixel circuit30further includes a driving transistor32, and the driving transistor32is a top-gate thin film transistor.

As shown inFIG.7, the driving transistor32includes a second active layer324, a second gate insulating pattern325and a second gate321that are disposed on a side of the second active layer324away from the base10, and a second source322and a second drain323. The second source322and the second drain323are each in contact with the second active layer324of the driving transistor32through at least one second connection via85in the interlayer dielectric layer15. A material of the second active layer324includes, for example, IGZO, IGO, ITZO, AlZnO, ZnO, GZO, or other metal oxides.

As shown inFIGS.6and7, the array substrate200further includes a plurality of second metal light-shielding patterns13disposed on the base10. Each second metal light-shielding pattern13is disposed at a side, proximate to the base10, of a driving transistor32in a corresponding pixel circuit30. An orthographic projection of a second active layer324of the driving transistor32on the base10is located within an orthographic projection of the second metal light-shielding pattern13on the base10, so that the second metal light-shielding pattern13may block light that travels toward the second active layer324.

The plurality of second line segments22and the plurality of second metal light-shielding patterns13are disposed in a same layer and made of a same material, and the plurality of second line segments22are insulated from the plurality of second metal light-shielding patterns13. The material of the second line segments22and the second metal light-shielding patterns13includes, for example, Mo, Al, or other materials having a light-shielding effect.

It will be noted that in a case where the plurality of second line segments22and the plurality of first metal light-shielding patterns12are arranged in a same layer, the plurality of second metal light-shielding patterns13, the plurality of first metal light-shielding patterns12, and the plurality of second line segments22are arranged in a same layer.

In some embodiments, as shown inFIG.7, the second gates321of the driving transistors32, the first gates311of the first switching transistors31, and the gate lines1are disposed in a same layer and made of a same material. The second sources322and the second drains323of the driving transistors32, the first sources312and the first drains313of the first switching transistors31, and the first line segments21are disposed in a same layer and made of a same material.

In some embodiments, as shown inFIG.7, one of the second source322and the second drain323of the driving transistor32is electrically connected to the second metal light-shielding pattern13located at the side of the driving transistor32proximate to the base10through a fourth via86. In some embodiments, as shown inFIGS.6and7, the display substrate200further includes a plurality of power lines9electrically connected to the plurality of pixel circuits30. The power lines9extend in the first direction Y.

A power line9of the plurality of power lines9includes a plurality of third line segments91and a plurality of fourth line segments92that all extend in the first direction, and the plurality of third line segments91and the plurality of fourth line segments92are arranged alternately. For example, each power line9includes a plurality of third line segments91and a plurality of fourth line segments92that all extend in the first direction, and the plurality of third line segments91and the plurality of fourth line segments92are arranged alternately.

There is no overlap among orthographic projections of the plurality of third line segments91on the base10and the orthographic projections of the plurality of gate lines1on the base10, and an orthographic projection of each fourth line segment92on the base10overlaps with an orthographic projection of a corresponding gate line1on the base10. The plurality of third line segments91and the plurality of first line segments21are disposed in a same layer and made of a same material, and the plurality of fourth line segments92and the second line segments22are disposed in a same layer and made of a same material. The insulating layer16further includes a plurality of third vias83. In the first direction Y, any two adjacent third line segments91are electrically connected to a fourth line segment92located between the two third line segments91through at least two third vias83.

In some examples, the power line9is electrically connected to the second source322of the driving transistor32in the pixel circuit30. In this case, in the pixel circuit30of the 2T1C structure, the second drain323of the driving transistor32is electrically connected to the light-emitting device40.

In some other examples, as shown inFIG.7, the power line9is electrically connected to the second drain323of the driving transistor32in the pixel circuit30. In this case, in the pixel circuit30of the 2T1C structure, the second source322of the driving transistor32is electrically connected to the light-emitting device40.

In some embodiments, in the second direction X, a width of the fourth line segment92is greater than a width of the third line segment91, so as to ensure a pass rate of an electrical connection between the third line segment91and the fourth line segment92. In a case where the second line segments22, the first metal light-shielding patterns12and the second metal light-shielding patterns13are arranged in a same layer, the fourth line segments92, the second line segments22, the second metal light-shielding patterns13, and the first metal light-shielding patterns12are arranged in a same layer.

In some embodiments, as shown inFIG.7, the third line segments91, the first line segments21, the second sources322and the second drains323of the driving transistors32, and the first sources312and the first drains313of the first switching transistors31are arranged in a same layer.

Similar to an arrangement manner of the data line2, in the embodiments of the present disclosure, the power line9is divided into a plurality of third line segments91and a plurality of fourth line segments92in the first direction Y; the plurality of third line segments91are located at the side of the gate lines1away from the base10, and the plurality of fourth line segments92are located at the side of the gate lines1proximate to the base10; and a plurality of third vias83are provided in the insulating layer16, so that in the first direction, any two adjacent third line segments91are electrically connected to a fourth line segment92located between the two adjacent third line segments91through at least two third vias83, so that the plurality of third line segments91and the plurality of fourth line segments92in the first direction are electrically connected to form a single power line9. In this case, even if a level difference of the insulating layer16is large, it may be possible to avoid a non-uniform thickness of the power line9caused by the level difference, and thus ensure a thickness uniformity of the power line9and improve the pass rate of the display panels.

In some embodiments, the power line9is electrically connected to the second source322of the driving transistor32in the pixel circuit30, and the second drain323of the driving transistor32is electrically connected to the anode41of the light-emitting device40.

In some examples, a material of the anode41includes ITO.

In some embodiments, the pixel circuit30further includes at least one second switching transistor, and the second switching transistor is a top-gate thin film transistor. In this case, a third metal light-shielding pattern may further be provided between the second switching transistor and the base10. An orthographic projection of the third metal light-shielding pattern on the base10covers an orthographic projection of an active layer of the second switching transistor on the base10. The third metal light-shielding patterns and the first metal light-shielding patterns12are disposed in a same layer and made of a same material, and the third metal light-shielding patterns are insulated from the first metal light-shielding patterns12.

Some embodiments of the present disclosure further provide a method of manufacturing an array substrate. As shown inFIG.16, the method includes following steps.

In S10, a plurality of second line segments22are formed on a base10.

Referring toFIGS.4to7, the base10is provided, and a plurality of columns of second line segments22are formed on the base10in a second direction X. Each column of second line segments22includes second line segments22extending in a first direction Y and arranged at intervals. The first direction intersects the second direction.

In some examples, the first direction is perpendicular to the second direction.

In some embodiments, after the plurality of second line segments22are formed, a plurality of pixel circuits30are formed on the base10on which the plurality of second line segments22have been formed.

The pixel circuit30includes a first switching transistor31. As for a structure of the first switching transistor31, reference may be made to the description about the structure of the first switching transistor31in the above embodiments, and details will not be repeated here.

In some embodiments, as shown in part a inFIG.17, a plurality of second line segments22and a plurality of first metal light-shielding patterns12are formed on the base10through a single patterning process. The plurality of second line segments22are insulated from the plurality of first metal light-shielding patterns12. An orthographic projection of a first active layer314of the first switching transistor31on the base10is located within an orthographic projection of a corresponding first metal light-shielding pattern12on the base10.

In some examples, the first metal light-shielding pattern12has a same thickness as the second line segment22, so that in the subsequent step, when a buffer film11′ is formed on the first metal light-shielding patterns12and the second line segments22, it may be possible to ensure a uniform thickness of the buffer film11in a thickness direction of the base10.

In some embodiments, the pixel circuit30further includes a driving transistor32. As shown in part a inFIG.17, the plurality of second line segments22, the plurality of first metal light-shielding patterns12, and a plurality of second metal light-shielding patterns13may be formed on the base10through a single patterning process. The plurality of second line segments22are insulated from the plurality of first metal light-shielding patterns12and the plurality of second metal light-shielding patterns13, and the plurality of first metal light-shielding patterns12are also insulated from the plurality of second metal light-shielding patterns13. An orthographic projection of a second active layer324of the driving transistor32on the base10is located within an orthographic projection of a corresponding second metal light-shielding pattern13on the base10.

The first metal light-shielding patterns12, the second line segments22, and the second metal light-shielding patterns13may have the same thickness.

In some examples, a material for the second line segments22includes Mo, Al, or other metal materials having a light-shielding effect. The first metal light-shielding patterns12and the second metal light-shielding patterns13may be made of the same material as the second line segments22.

In S20, a plurality of gate lines1are formed on the base10on which the plurality of second line segments22have been formed, the plurality of gate lines1all extending in the second direction X.

Referring toFIGS.4to7, the plurality of gate lines1arranged in the first direction Y are formed on the base10on which the plurality of second line segments22have been formed, and each gate line1extends in the second direction X.

In some embodiments, the plurality of gate lines1and the first gates311of the first switching transistors31are formed through a single patterning process.

In some other embodiments, the plurality of gate lines1, the first gates311of the first switching transistors31, and second gates321of the driving transistors32are formed through a single patterning process.

A material for the gate lines1may include, for example, at least one of Cu, Al, Mo, Ti, Cr, W, and other elemental metals.

In S30, an insulating layer16is formed on the base10on which the plurality of second line segments22have been formed, the insulating layer including a plurality of first vias81.

Referring toFIGS.5and7, the first vias81are used to electrically connect the second line segments22to first line segments21to be formed subsequently.

As shown in part g inFIG.17, the first vias81expose partial regions of the second line segments22.

In S40, a plurality of first line segments21are formed on the base10on which the insulating layer16has been formed.

As shown inFIGS.4to7, there is no overlap among orthographic projections of the plurality of first line segments21on the base10and orthographic projections of the plurality of gate lines1on the base10. The plurality of first line segments21are arranged into a plurality of columns in the second direction X, and first line segments21in each column extend in the first direction and are arranged at intervals. In the first direction Y, any two adjacent first line segments21are electrically connected to a second line segment22located between the two adjacent first line segments21through at least two first vias81. All the first line segments21and all the second line segments22that are electrically connected in each column constitute a single data line2.

In some embodiments, the plurality of first line segments21and first sources312and first drains313of the first switching transistors31may be formed through a single patterning process.

In some other embodiments, referring to part h inFIG.17, the plurality of first line segments21, the first sources312and the first drains313of the first switching transistors31, and second sources322and second drains323of the driving transistors32may be formed through a single patterning process.

A material of the first line segments21may include, for example, Cu, Al, or other elemental metals.

In some embodiments, the insulating layer16includes a buffer layer11and an interlayer dielectric layer15.

As shown in part binFIG.17, the buffer film11′ is formed on the base10after the plurality of second line segments22are formed and before the plurality of gate lines1are formed. The buffer film11′ may be of a single-layer or multi-layer structure. For example, the buffer film11″ is of a single-layer structure, and a material of the buffer film11′ is SiOxor SiNx. The buffer film11′ may be of a two (or more)-layer structure, and the buffer film11′ is, for example, a composite film layer composed of a SiOxlayer and a Sir % layer.

In some embodiments, the first active layers314of the first switching transistors31are formed on the buffer film11′ through a single patterning process.

In some other embodiments, as shown in part c inFIG.17, the first active layers314of the first switching transistors31and the second active layers324of the driving transistors32are formed on the buffer film11′ through a single patterning process.

The buffer film11′ may prevent harmful impurities and ions in the base10from diffusing into the first active layers314of the first switching transistors31and the second active layers324of the driving transistors32.

A material of the first active layers314of the first switching transistors31includes, for example, IGZO, IGO, ITZO, AlZnO, ZnO, GZO, or other metal oxides.

A material of the second active layers324of the driving transistors32includes, for example, IGZO, IGO, ITZO, AlZnO, ZnO, GZO, or other metal oxides.

In some embodiments, a gate insulating film is formed on the base10on which the first active layers314have been formed, and the gate insulating film is patterned with the first gates311and the gate lines1as a mask, so as to form first gate insulating patterns315of the first switching transistors31and remaining patterns14. An orthographic projection of the remaining pattern14on the base10overlaps with the orthographic projection of the gate line1on the base10.

In some other embodiments, referring to parts d and e inFIG.17, a gate insulating film330is formed on the buffer film11′ on which the first active layers314and the second active layers324have been formed, and the gate insulating film330is patterned with the first gates311, the second gates321and the gate lines1as a mask, so as to form first gate insulating patterns315of the first switching transistors31, second gate insulating patterns325of the driving transistors32, and remaining patterns14. An orthographic projection of the remaining pattern14on the base10overlaps with the orthographic projection of the gate line1on the base10.

Of course, after the gate insulating film330is formed, the gate insulating film330may not be patterned. In this case, the first gate insulating patterns315, the second gate insulating patterns325, and the remaining patterns14are of a one-piece structure.

A material for the gate insulating film330includes, for example, at least one of SiNx, SiOx, aluminum oxide (Al2O3), and aluminum nitride (AlN).

It can be understood that, after the first gates311and the first gate insulating patterns315of the first switching transistors31are formed, a conductorization treatment is performed on portions of the first active layers314of the first switching transistors31that are not covered by the first gates311, so as to increase a conductivity of portions of the first active layers314that are in contact with the first sources312and the first drains313. For example, the conductorization treatment may be performed by bombarding portions of the first active layers314of the first switching transistors31that extend beyond the first gates311with plasma, so as to bombard oxygen ions out and thus conductorize the portions of the first active layers314. A gas forming the plasma includes a protective atmosphere or a reactive atmosphere. Protective gases may include, for example, one or a mixture of nitrogen, argon, helium, or neon. Reactive gases may include, for example, one or a mixture of air, oxygen, hydrogen, ammonia, or carbon dioxide.

Of course, after the second gates321and the second gate insulating patterns325of the driving transistors32are formed, the conductorization treatment is performed on portions of the second active layers324of the driving transistors32that are not covered by the second gates321, so as to increase the conductivity of portions of the second active layers324that are in contact with the second sources322and the second drains323.

When the conductorization treatment is performed on the portions of the first active layers314of the first switching transistors31, the conductive treatment may be performed on the portions of the second active layers324of the driving transistors32that are not covered by the second gates321in the same manner. Referring to part finFIG.17, after the gate lines1are formed, an interlayer dielectric film15″ is formed on the buffer film11′ on which the gate lines1have been formed, and then the interlayer dielectric film15′ and the buffer film11′ are patterned to form, as shown in part g inFIG.17, the interlayer dielectric layer15and the buffer layer11. The first vias81penetrate the interlayer dielectric layer15and the buffer layer11, so that in the first direction, any two adjacent first line segments21are electrically connected to a second line segment22located between the two adjacent first line segments21through at least two first vias81.

In addition, in the process of forming the first vias81, a plurality of first connection vias84penetrating the interlayer dielectric layer15are also formed, so that the first source312and the first drain313may each be in contact with the first active layer314through a first connection via84.

Of course, in the process of forming the first vias81, a plurality of first connection vias84and a plurality of second connection vias85penetrating the interlayer dielectric layer15are further formed. In this way, the first source312and the first drain313may each be in contact with the first active layer314through a first connection via84, and the second source322and the second drain323may each be in contact with the second active layer324through a second connection via85.

In some embodiments, in the process of forming the first vias81, a plurality of second vias82penetrating the buffer layer11and the interlayer dielectric layer15are further formed. One of the first source312and the first drain313of the first switching transistor31is electrically connected to the first metal light-shielding pattern12through a second via82.

In some other embodiments, in the process of forming the first vias81, a plurality of second vias82and a plurality of fourth vias86penetrating the buffer layer11and the interlayer dielectric layer15are further formed. One of the first source312and the first drain313of the first switching transistor31is electrically connected to the first metal light-shielding pattern12through a second via82. One of the second source322and the second drain323of the driving transistor32is electrically connected to the second metal light-shielding pattern13through a fourth via86.

In some embodiments, the method of manufacturing the array substrate further includes forming a plurality of power lines, as shown inFIG.14. Each power line9includes a plurality of third line segments91and a plurality of fourth line segments92that all extend in the first direction, and the plurality of third line segments91and the plurality of fourth line segments92are arranged alternately.

There is no overlap among orthographic projections of the plurality of third line segments91on the base10and the orthographic projections of the plurality of gate lines1on the base10, and an orthographic projection of each fourth line segment92on the base10overlaps with an orthographic projection of a corresponding gate line1on the base10. The plurality of third line segments91and the plurality of first line segments21are formed through a single patterning process, and the plurality of fourth line segments92and the second line segments22are formed through a single patterning process.

The insulating layer16further includes a plurality of third vias83. In the first direction, any two adjacent third line segments91are electrically connected to a fourth line segment92located between the two third line segments91through at least two third vias83.

In some examples, the power line9is electrically connected to the second source322of the driving transistor32in the pixel circuit30.

It will be noted that, with regard to a specific structure of the power line9, reference may be made to the structure of the power line9in the array substrate200described above, and details will not be repeated here.