Driving circuits with power MOS breakdown protection and driving methods thereof

A driving circuit is provided. The driving circuit is capable of driving a load coupled to an output node of the driving circuit. The driving circuit includes an output-stage element, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a first P-type metal-oxide-semiconductor (PMOS) transistor. The output-stage element is coupled between an operation voltage source and the output node. The first NMOS transistor has a gate, a drain coupled to the output node, and a source coupled to a ground. The first PMOS transistor has a gate, a drain coupled to the ground, and a source coupled to the output node. When the first NMOS transistor begins to be turned off, the first PMOS transistor is turned on, and a voltage at the drain of the first NMOS transistor is clamped to be lower than a breakdown trigger voltage of the first NMOS transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a driving circuit, and more particularly to a driving circuit with power metal-oxide-semiconductor (MOS) breakdown protection.

2. Description of the Related Art

FIG. 1shows an H-bridge output stage of a driving circuit. Referring toFIG. 1, the H-bridge output stage is coupled between an operation voltage source VDD and a ground GND and used to drive a load10coupled between output nodes OUT10and OUT11, such as an inductance element. The H-bridge output stage comprises four output-stage elements that are P-type metal-oxide-semiconductor (PMOS) transistors P10and P11and NMOS transistors N10and N11. As known by the one skilled in the art, when the PMOS transistor P10and the NMOS transistor N11are turned on while the PMOS transistor P11and the NMOS transistor N10are turned off, a current path passing through the PMOS transistor P10, the inductance element10, and the NMOS transistor N11is formed to drive the inductance element10. When the PMOS transistor P11and the NMOS transistor N10are turned on while the PMOS transistor P10and the NMOS transistor N11are turned off, a current path passing through the PMOS transistor P11, the inductance element10, and the NMOS transistor N10is formed to drive the inductance element10. In this structure, when a current from the inductance element10flows to one of the output nodes OUT10and OUT11of the H-bridge output stage, the corresponding NMOS transistor may be burned.

For example, when the PMOS transistor P10and the NMOS transistor N11are turned on, the current from the inductance element10flows to the output node OUT11. In this case, the current from the inductance element10may flow to the body of the NMOS transistor N11at the time when the NMOS transistor N11is turned off, which may trigger the parasitical NPN of the NMOS transistor N11to be turned on, resulting in the breakdown of the NMOS transistor N11. After the NMOS transistor N11is broken down, the NMOS transistor N11operates as a voltage source with a holding voltage. When the PMOS transistor P11is turned on and the holding voltage is less than the voltage of the operation voltage source VDD, the NMOS transistor N11is burned, and the H-bridge output stage can not work any more.

Thus, it is desired to provide a drive circuit which provides power NMOS breakdown protection.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a driving circuit is provided. The driving circuit is capable of driving a load coupled to an output node of the driving circuit. The driving circuit comprises an output-stage element, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a first P-type metal-oxide-semiconductor (PMOS) transistor. The output-stage element is coupled between an operation voltage source and the output node. The first NMOS transistor has a gate, a drain coupled to the output node, and a source coupled to a ground. The first PMOS transistor has a gate, a drain coupled to the ground, and a source coupled to the output node.

In an embodiment, when the first NMOS transistor begins to be turned off, the first PMOS transistor is turned on, and a voltage at the drain of the first NMOS transistor is clamped to be lower than a breakdown trigger voltage of the first NMOS transistor.

The first NMOS transistor is controlled according to a first driving signal. The gate of first PMOS transistor receives a control signal. At a first time point, the first driving signal switches from a first high voltage level to a first low voltage level for turning off the first NMOS transistor. Also, at the first time point, the control signal is at a second low voltage level to turn on the first PMOS transistor. During a time period from the first time point to a second time point which is later than the first time point, the control signal changes from the second low voltage level to a second high voltage level gradually. Then, at the second time point, the first PMOS transistor is turned off by the control signal with the second high voltage level.

Another exemplary embodiment of a driving circuit is provided. The driving circuit is capable of driving a load coupled to an output node of the driving circuit. The driving circuit comprises a first output-stage element and a protection circuit coupled between the output node and a ground. The protection circuit provides a current path from the output node to the ground to guide a current from the output node and to clamp a voltage at the output node when the first output-stage element begins to be turned off.

Another exemplary embodiment of a driving method for a driving circuit is provided. The driving circuit comprises a first transistor and a second transistor coupled between an output node of the driving circuit and a ground. The driving method comprises when the first transistor begins to be turned off, turning on the second transistor to provide a current path from the output node to the ground and to clamp a voltage of the first transistor to be lower than a breakdown breakdown trigger voltage of the first transistor.

DETAILED DESCRIPTION OF THE INVENTION

Driving circuits are provided. In an exemplary embodiment shown inFIG. 2, a driving circuit2comprises two output-stage elements20and21, a protection circuit22, and two pre-drivers23and24. The driving circuit2is used to drive a load25(such as an inductance element) which is coupled to an output node OUT20of the driving circuit2. In the embodiment, the output-stage element20is implemented by a P-type metal-oxide-semiconductor (PMOS) transistor P20, while the output-stage element21is implemented by an N-type metal-oxide-semiconductor (NMOS) transistor N20. A source of the PMOS transistor P20is coupled to an operation voltage source VDD, and a drain thereof is coupled to the output node OUT20. A drain of the NMOS transistor N20is coupled to the output node OUT20, and a source thereof is coupled to a ground GND. InFIG. 2, a diode D20coupled in parallel with the PMOS transistor P20represents a parasitic element of the PMOS transistor P20. The pre-drivers23and24are coupled to gates of the PMOS transistor P20and the NMOS transistor N20to control the gate voltages at the PMOS transistor P20and the NMOS transistor N20according to driving signals S20and S21for controlling the states of the PMOS transistor P20and the NMOS transistor N20, respectively.

As shown inFIG. 2, the protection circuit22comprises a PMOS transistor P21. A source of the PMOS transistor P21is coupled to the output node OUT20, a drain thereof is coupled to the ground GND, and a gate thereof receives a control signal S22.

FIG. 3is a timing chart of the driving signals S20and S21, the control signal S22, and a voltage V20generated at the output node OUT20. As described above, the drain of the NMOS transistor N20is coupled to the output node OUT20. Thus, the voltage V20is also referred to as the drain voltage of the NMOS transistor N20.

In the following, the operations of the driving circuit2will be described according toFIGS. 2 and 3. Referring toFIGS. 2 and 3, at a time point T1, the driving signal S21switches from a high voltage level LH30to a low voltage level LL30, and the control signal S22is at a low voltage level LL31to keep the PMOS transistor P21turned-on. Due to the parasitic capacitor between the drain and the gate of the NMOS transistor N20, the voltage, which is generated by the pre-driver24, at the gate of the NMOS transistor N20is not rapidly drawn to a ground level, such that the NMOS transistor N20does not switch to be at a turned-off state rapidly. In other words, at the time point T1, the NMOS transistor N20begins to be turned off, but not fully turned off. During the time period from the time point T1to a time point T2which is later than the time point T1, the control signal S22changes from the low voltage level LL31to a high voltage level LH31gradually. At the time point T2, the PMOS transistor P21is turned off by the control signal S22with the high voltage level LH31. Moreover, at the time point T2, the voltage at the gate of the NMOS transistor N20is drawn to the ground level, and the NMOS transistor N20is fully turned off.

Regarding the driving signal S20, during the time period from the time point T1to the time point T3which is later than the time point T2, the driving signal S20is at the high voltage level LH30, and the pre-driver23generates a voltage at the gate of the PMOS transistor P20to turn off the PMOS transistor P20. At the time point T3, the driving signal S20switches from the high voltage level LH30to the low voltage level LL30, and the voltage which is generated by the pre-driver23at the gate of the PMOS transistor P20is drawn to the ground level, such that the PMOS transistor P20is turned on. According to the operations of the NMOS transistor N20and the PMOS transistor P20, the NMOS transistor N20and the PMOS transistor P20are turned on at different time.

According to the above operation, at the time point T1, the control signal S22is at the low voltage level LL31to keep the PMOS transistor P21turned-on, and the NMOS transistor N20begins to be turned off. When a current flows from the load25to the output node OUT20at the time point T1, the turned-on PMOS transistor P21guides the current to the ground GND. During the time period from the time point T1to the time point T2, since the control signal S22changes from the low voltage level LL31to the high voltage level LH31gradually, the voltage V20is clamped by the control signal S22to be lower than the breakdown trigger voltage of the NMOS transistor N20. In other words, the voltage V20changes gradually with the control signal S22, and the maximum value of the voltage V20is less than the value of the breakdown trigger voltage of the NMOS transistor N20. At the time point T2, the voltage at the gate of the NMOS transistor N20is fully drawn to the ground level. It is well known that the higher the voltage at the gate of the NMOS transistor N20is, the lower the breakdown trigger voltage of the NMOS transistor N20is; on the contrary, the lower the voltage at the gate of the NMOS transistor N20is, the higher the breakdown trigger voltage of the NMOS transistor N20is. Accordingly, at the time T2, the breakdown trigger voltage of the NMOS transistor N20rises greatly due to the low voltage at the gate of the NMOS transistor N20. The voltage V20at the time point T2is still lower than the breakdown trigger voltage of the NMOS transistor N20, which prevents the NMOS transistor N20from being at the breakdown state.

In another embodiment, the output-stage element20is implemented by an NMOS transistor N40, as shown inFIG. 4. In the embodiment, the breakdown characteristics of the NMOS transistor N40are better than the breakdown characteristics of the NMOS transistor N20.

In summary, the above embodiments show a mechanism for protecting the power NMOS transistor from suffering the current from the output node. When turning off the output-stage element21(e.g. the NMOS transistor N20) of the driving circuit2, the proposed mechanism controls the protection circuit22to provide a current path from the output node OUT20to the ground GND to guide the current from the output node OUT20. The current path guiles the current to the ground GND. The current path may be formed by drawing the gate voltage of the PMOS transistor P21of the protection circuit22to a low level. The drain voltage of the NMOS transistor N20is therefore clamped and is ensured to be less than the breakdown trigger voltage level of the NMOS transistor N20even though the breakdown trigger voltage level is relatively low due to the high voltage level at the gate of the NMOS transistor N20. Then, when the output-stage elements21(e.g. the NMOS transistor N20) is fully turned off, the current path provided by the protection circuit22is disabled by, for example, pulling the gate voltage of the PMOS transistor P21to a high level to turn off the PMOS transistor P21. Since the breakdown trigger voltage level of the NMOS transistor N20is relatively high now due to the low voltage level at its gate terminal, the NMOS transistor N20will not easily enter the breakdown state, and thereby the power NMOS transistor of the driving circuit2is protected.