Semiconductor memory device, flag generating circuit, and method of outputting data in a semiconductor device

A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2017-0033768, filed on Mar. 17, 2017, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments may generally relate to a semiconductor device, more particularly to a semiconductor device, a flag generating circuit and a method of outputting data.

2. Related Art

A performance of a semiconductor memory device may be determined by various factors. One of the various factors may be a data-processing speed.

Particularly, a performance of a main memory or a graphic memory is mainly dependent upon the data-processing speed of the semiconductor memory device.

Recently, as mobile devices are being diversified and generalized, it may be required to provide the semiconductor memory device applied to the mobile device with low power consumption and high operational speeds.

Thus, it may be required to rapidly process data using minimal resources in the semiconductor memory device.

SUMMARY

In an embodiment, a semiconductor memory device may be provided. The semiconductor memory device may include a memory circuit. The semiconductor memory device may include a flag-generating circuit. The semiconductor memory device may include an output circuit. The memory circuit may include a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. The memory circuit may be configured to output data in the memory cell coupled to each of the bit lines through a global input and output (input/output) line. The flag-generating circuit may be configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation. The output circuit may be configured to output the data in the memory cell provided through the global input/output line in response to at least one of the duplicate data flag signal and the data bus inversion flag signal.

In an embodiment, a circuit for generating a flag signal may be provided. The circuit may include a preliminary flag-generating circuit. The circuit may include a flag-generating circuit. The preliminary flag-generating circuit may be configured to receive data from a memory cell through bit lines provided through a global input/output line. The preliminary flag-generating circuit may be configured to generate a preliminary flag signal by the bit lines by adding the data from the memory cell based on a duplicate data output enablement signal and a data bus inversion enablement signal. The flag-generating circuit may be driven based on the duplicate data output enablement signal and the data bus inversion enablement signal. The flag-generating circuit may be configured to generate the flag signal for each of the bit lines including at least one of a duplicate data flag signal and a data bus inversion flag signal from the preliminary flag signal for each of the bit lines.

In an embodiment, a method of outputting data in a semiconductor memory device may be provided. The semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. The memory circuit may be configured to output data in the memory cell coupled to each of the bit lines through a global input/output line. A flag signal by the bit lines may be generated based on number of data having a specific logic level among the data in the memory cell by the bit lines provided through the global input/output line. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal. The data in the memory cell provided through the global input/output line may be outputted based on at least one of the duplicate data flag signal and the data bus inversion flag signal.

DETAILED DESCRIPTION

Hereinafter, examples of embodiments will be described below with reference to the accompanying drawings through various examples of the embodiments.

FIG. 1is a block diagram illustrating a semiconductor memory device in accordance with various examples of embodiments.

Referring toFIG. 1, a semiconductor memory device10in an embodiment may include a memory circuit110, a flag-generating circuit120, a mode register130, an output circuit140, and a pad group150.

The memory circuit110may include a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. When an address signal is perhaps provided from a controller, data may be written or read by accessing a desired memory cell among the memory cells by an addressing circuit such as a row decoder or a column decoder.

Global input and output (input/output) lines GIO0˜GIOn may be connected with the bit lines BL<0:m>, respectively. Data in the memory cells connected to the bit lines may be transmitted to the output circuit140through the global input/output lines GIO0-GIOn in response to a read command. The data may be represented by GIO0_BL<0:m>˜GIOn_BL<0:m>.

The flag-generating circuit120may generate a flag signal DBI_BL<0:m> by the bit line in response to the data GIO0_BL<0:m>˜GIOn_BL<0:m>, a data bus inversion (DBI) enablement signal (DBI_EN), and a duplicate data output enablement signal DQO_COPY_EN transmitted through the global input/output lines GIO0˜GIOn. The flag signal DBI_BL<0:m> by the bit line may be outputted through a flag transmission line122.

The flag signal DBI_BL<0:m> from the bit line may include data coding information from the bit line BL<0:m>. The output circuit140may output the data in response to the data GIO0_BL<0:m>˜GIOn_BL<0:m> transmitted through the global input/output lines GIO0˜GIOn and the flag signal DBI_BL<0:m> for each of the bit lines.

In an example of an embodiment, when the DBI enablement signal DBI_EN and the duplicate data output enablement signal DQO_COPY_EN are disabled, the flag-generating circuit120may not be operated regardless of a level of the inputted data GIO0_BL<0:m>˜GIOn_BL<0:m>. That is, the flag-generating circuit120must also be disabled.

In an example of an embodiment, when the DBI enablement signal DBI_EN is enabled and the duplicate data output enablement signal DQO_COPY_EN is disabled, the flag-generating circuit120may generate a DBI flag signal with respect to each of the bit lines BL<0:m> as the flag signal DBI_BL<0:m> from the bit line.

In an example of an embodiment, when the DBI enablement signal DBI_EN is disabled and the duplicate data output enablement signal DQO_COPY_EN is enabled, the flag-generating circuit120may generate the duplicate data flag signal through at least one among the flag signals DBI_BL<0:m> for each of the bit lines, for example, a flag signal DBI_BL0with respect to a zeroth bit line. In this case, the rest of bits of the flag signal DBI_BL<0:m> may be disabled.

In an example of an embodiment, when the DBI enablement signal DBI_EN and the duplicate data output enablement signal DQO_COPY_EN are enabled, the flag-generating circuit120may generate a first flag signal DBI_BL0from the duplicate data flag signal through at least one among the flag signals DBI_BL<0:m> from the bit line, for example, a flag signal DBI_BL0with respect to a zeroth bit line and a second flag signal DBI_BL<1:m> from the DBI flag signal through the rest of bits of the flag signal DBI_BL<0:m> from the bit line.

The output circuit140may output the data in response to the flag signals DBI_BL<0:m> from the bit line and the data GIO0_BL<0:m>˜GIOn<0:m> transmitted through the global input/output lines GIO0˜GIOn.

The pad group150may include a pad group and a pad. The pad group may output the data GIO0_BL<0:m>˜GIOn_BL<0:m> provided from the output circuit140. The pad may output the flag signals DBI_BL<0:m> for each of the bit lines.

Therefore, the DBI flag signal and the duplicate data flag signal may be outputted through the flag signal transmission line122.

A DBI function may invert or not invert the data to increase is number of an outputted bit among a logic low level (0) and a logic high level (1), i.e., number of a reference data bit. For example, when the number of the outputted data in the logic low level is increased, the data may be inverted and outputted under a condition that a bit number of the logic low level are no more than half of the total bits of the data. In contrast, the data may be outputted without inversion under a condition that the bit number of the logic low level is no less than half of the total bits of the data.

The DBI function may function to rapidly transmit the massive amounts of data. The DBI function may be used for rapidly transmitting the data between a central processing unit and a DRAM device in a package-on-package (POP), a multi-chip package (MCP), or various memory interfaces. Particularly, the DBI function may be used, for example, in a mobile memory application such as low power double data rate (LPDDR).

A duplicate data output function may output data and a duplicate data flag in any one of the memory cells coupled to the bit line when the data in the memory cells coupled to the same bit line have a same logic level. Thus, the duplicate data flag signal may represent whether the data of the bit line in the duplicate data output function is a duplicate or not.

FIGS. 2A, 2B, 3A and 3Bare block diagrams illustrating a function for outputting duplicate data in accordance with various examples of embodiments.

FIGS. 2A and 2Bmay illustrate the function for outputting the duplicate data by the four bit lines in the semiconductor memory device.

Referring toFIG. 2A, a cell data DQ<0:7> in a zeroth bit line BL<0> and a second bit line BL<2> may be about 0. A cell data DQ<0:7> in a first bit line BL<1> and a third bit line BL<3> may be about 1. In this case, the duplicate data flag signal may be enabled to have a first logic level.

Referring toFIG. 2B, the cell data DQ<0:7> in the zeroth bit line BL<0> and the third second bit line BL<3> may be about 0 and about 1, respectively. Different cell data DQ2_BL1, DQ3_BL1and DQ1_BL2may be in the first bit line BL<1> and the second bit line BL<2>. In this case, the duplicate data flag signal may be disabled to have a second logic level.

When the duplicated data flag signal is enabled, the semiconductor memory device10may output any cell data, for example, DQ<0> with respect to each of the bit lines and the duplicate data flag as illustrated inFIG. 3A. The semiconductor memory device10may not output the rest of the cell data DQ<1:7>.

A receiver may copy the cell data, for example, DQ<0> with the rest of the cell data DQ<1:7> in response to the duplicate data flag.

FIG. 3Billustrates the function for outputting the duplicate data with respect to the sixteen bit lines.

As illustrated inFIGS. 3A and 3B, when the duplicated data output function operated in DQ<0:7> is applied, a DQ power may be decreased by about ⅛.

Therefore, when the data of the memory cell connected to the same bit line is substantially the same, an electric power for outputting the data may be remarkably reduced by transmitting a bit of the data.

In an example of an embodiment, when the duplicate data flag signal is transmitted to assist the duplicate data output function, a signal line for transmitting the DBI flag signal, i.e., the flag signal transmission line122may be used without an additional signal line.

In an example of an embodiment, when a DBI mode or a duplicate data output mode is not activated (i.e., disablement), the flag signal may not be generated (i.e., disablement). When only the DBI mode is activated, the DBI flag signal by the bit line may be outputted. When only the duplicate data output mode is activated (i.e., enablement), the duplicate data flag signal may be outputted using at least one bit among the flag signals. When the DBI mode and the duplicated data output mode is activated (i.e., enablement), the duplicate data flag signal may be outputted using at least one bit among the flag signal and the DBI flag signal may be outputted using the rest of the bits. The above relations may be represented in a following table.

Duplicate dataDBIoutputenablementenablementsignalsignalFlag-generating circuitDisablementDisablementDisablementEnablementDisablementGenerating the DBI flag signal bythe total bit linesDisablementEnablementgenerating the duplicate dataflag signal through any one bitamong the flag signalsdisabling the rest of the bits ofthe flag signalsEnablementEnablementgenerating the duplicate dataflag signal through any one bitamong the flag signalsgenerating the DBI flag signal bythe partial bit lines through therest of the bits of the flag signals.

FIG. 4is a block diagram illustrating a flag-generating circuit in accordance with an example of an embodiment.

The enablement signal-generating circuit1210may be configured to generate a flag generation-enabling signal DBI_DQO_COPY_EN in response to a DBI-enabling signal BDI_EN and a duplicate data output-enabling signal DQO_COPY_EN provided from the mode register130.

In an example of an embodiment, when at least one of two logic signals are enabled, the enablement signal-generating circuit1210may enable the flag generation-enabling signal DBI_DQO_COPY_EN.

The preliminary flag-generating circuit1220may include preliminary signal-generating circuits1220-0˜1220-m coupled to the bit lines BL<0:m>.

Each of the preliminary signal-generating circuits1220-0˜1220-m may generate a preliminary DBI flag signal DBI_BLx_PRE and a preliminary duplicate data flag signal DQO_COPY_BLx in response to data GIO<0:n>_BL0˜GIO<0:n>_BLm transmitted through the global input/output lines GIO0˜GIOn coupled to the bit lines BL<0:m> and the flag generation-enabling signal DBI_DQO_COPY_EN.

For example, a zeroth preliminary signal-generating circuit1220-0may generate a preliminary DBI flag signal DBI_BL0_PRE and a preliminary duplicate data flag signal DQO_COPY_BL0with respect to a zeroth bit line in response to the data GIO<0:n>_BL0transmitted through the global input/output lines GIO0˜GIOn coupled to the zeroth bit line and the flag generation-enabling signal DBI_DQO_COPY_EN.

The first preliminary signal-generating circuits1220-1may generate a preliminary DBI flag signal DBI_BL1_PRE and a preliminary duplicate data flag signal DQO_COPY_BL1with respect to the first bit line in response to the data GIO<0:n>_BL1transmitted through the global input/output lines GIO0˜GIOn coupled to the first bit line and the flag generation-enabling signal DBI_DQO_COPY_EN.

Similarly, the mth preliminary signal-generating circuits1220-m may generate a preliminary DBI flag signal DBI_BLm_PRE and a preliminary duplicate data flag signal DQO_COPY_BLm with respect to the mth bit line in response to the data GIO<0:n>_BLm transmitted through the global input/output lines GIO0˜GIOn coupled to the mth bit line and the flag generation-enabling signal DBI_DQO_COPY_EN.

In an example of an embodiment, each of the preliminary signal-generating circuits1220-0˜1220-m may generate the preliminary DBI flag signal DBI_BLx_PRE and the preliminary duplicate data flag signal DQO_COPY_BLx among the data GIO<0:n>_BLx, which may be transmitted through the global input/output lines GIO0˜GIOn coupled to the bit line, based on a number of the data having a specific logic level. For example, when the number of the data having the specific logic level is no less than half of total number of the data GIO<0:n>_BLx transmitted through the global input/output lines GIO0˜GIOn coupled to the bit line, the preliminary DBI flag signal DBI_BLx_PRE may be enabled. When the number of the data having the specific logic level is substantially the same as the total number of the data GIO<0:n>_BLx transmitted through the global input/output lines GIO0˜GIOn coupled to the bit line or the number of the data having the specific logic level is zero, the preliminary duplicate data flag signal DQO_COPY_BLx may be enabled. When the enablement condition of the preliminary DBI flag signal DBI_BLx_PRE and the enablement condition of the preliminary duplicate data flag signal DQO_COPY_BLx is satisfied, the preliminary DBI flag signal DBI_BLx_PRE and the preliminary duplicate data flag signal DQO_COPY_BLx may be enabled.

In an example of an embodiment, when the number of the data having a high or low level among the data GIO<0:n> transmitted through the global input/output lines GIO0˜GIOn coupled to the zeroth bit line BL0is no less than [(n+1)/2+1], the preliminary DBI flag signal DBI_BL0_PRE may be enabled to a high level. When the number of the data having a high or low level among the data GIO<0:n> transmitted through the global input/output lines GIO0˜GIOn coupled to the zeroth bit line BL0is (n+1) or zero, the preliminary duplicate data flag signal DQO_COPY_BL0may be enabled to a high level.

FIG. 5is a block diagram illustrating a preliminary signal-generating circuit in accordance with an example of embodiment.

Referring toFIGS. 4 and 5, the preliminary flag-generating circuit1220may generate the preliminary flag signals DBI_BLx_PRE and DQO_COPY_BLx in accordance with the number of the specific logic levels in the data transmitted through the same bit line.

The flag-generating circuit1230, also known herein as a bit line flag-generating circuit, may include a first flag-generating circuit1231and a second flag-generating circuit1233.

The first flag-generating circuit1231may receive at least one of the preliminary DBI flag signal DBI_BLx_PRE, for example, the preliminary DBI flag signal DBI_BL0_PRE with respect to the zeroth bit line and the preliminary duplicate data flag signals DQO_COPY_BL0˜DQO_COPY_BLm outputted from the preliminary signal-generating circuits1220-0˜1220-m. The first flag-generating circuit1231may generate a first flag signal DBI_BL0in response to the duplicate data output-enabling signal DQO_COPY_EN.

In an example of an embodiment, when the duplicate data output function from the (m+1) bit lines are performed, the first flag-generating circuit1231may determine an identity of the data by the bit lines by combinations of the preliminary duplicate data flag signals DQO_COPY_BL0˜DQO_COPY_BLm with respect to the bit lines outputted from the preliminary signal-generating circuits1220-0˜1220-m to output a hit signal HIT (SeeFIG. 7).

The first flag-generating circuit1231may receive the hit signal HIT as a first input signal and at least one of the preliminary DBI flag signals, for example, DBI_BL0_PRE as a second input signal. When the duplicate data output-enabling signal DQO_COPY_EN is enabled, the first flag-generating circuit1231may output the hit signal HIT as the first flag signal DBI_BL0. When the duplicate data output-enabling signal DQO_COPY_EN is disabled, the first flag-generating circuit1231may output the at least one preliminary DBI flag signal DBI_BL0_PRE as the first flag signal DBI_BL0.

The second flag-generating circuit1233may receive the rest of the preliminary DBI flag signals, for example, DBI_BL1_PRE˜DBI_BLm_PRE. The second flag-generating circuit1233may generate m bits of a second flag signal DBI_BL1˜DBI_BLm in response to the DBI-enabling signal DBI_EN.

In an example of an embodiment, the second flag-generating circuit1233may include a plurality of output circuits configured to receive the rest of the preliminary DBI flag signals DBI_BL1_PRE˜DBI_BLm_PRE. When the DBI-enabling signal DBI_EN is enabled, each of the output circuits may output the rest of the preliminary DBI flag signals DBI_BL1_PRE˜DBI_BLm_PRE as the second flag signals DBI_BL1˜DBI_BLm.

Referring toFIGS. 4 and 5, the preliminary flag-generating circuit1220may include a plurality of preliminary signal-generating circuits1220-0˜1220-m. The preliminary signal-generating circuits1220-0˜1220-m may have substantially the same configuration.

For example, a preliminary signal-generating circuit1220-x may include a plurality of first arithmetic circuits210-1˜210-k, a plurality of second arithmetic circuits220-1˜220-l, and a determining circuit230.

Each of the first arithmetic circuits210-1˜210-k may receive a pair of the data GIO<0:n> transmitted through the global input/output lines. Each of the first arithmetic circuits210-1˜210-k may generate output signals S0_x, S1_x, and S2_x based on the number of the input data having the specific logic level in response to the flag generation-enabling signal DBI_DQO_COPY_EN.

For example, a first arithmetic circuit#1210-1may receive zeroth and first data DO and D1among the data GIO<0:n> transmitted through the global input/output lines. The first arithmetic circuit210-1may add the zeroth and first data D0and D1in response to the flag generation-enabling signal DBI_DQO_COPY_EN (i.e., EN). The first arithmetic circuit#1210-1may generate the output signals S0_1, S1_1and S2_1representing added results of 0, 1 and 2, respectively.

FIGS. 6A to 6Care block diagrams illustrating operations of a preliminary flag-generating circuit in accordance with an example of an embodiment.

FIG. 6Ais a table representing the output signals S0_1, S1_1and S2_1in accordance with the input data D0and D1of the first arithmetic circuit210-1.

When the flag generating-enabling signal DBI_DQO_COPY_EN; EN) is disabled, all of the output signals S0_1, S1_1and S2_1may be disabled.

When the flag generating-enabling signal DBI_DQO_COPY_EN; EN) is enabled, levels of the output signals S0_1, S1_1and S2_1may be determined in accordance with added results of the input data D0and D1. For example, when the added result is 0 S0_1may be outputted to a high level. When the added result is 1, S1_1may be outputted to a high level. When the added result is 2, S2_1may be outputted to a high level.

Operations of other first arithmetic circuits210-2˜210-k may be substantially the same as those of the first arithmetic circuit#1210-1.

Thus, the output signals S0_x, S1_x and S2_x of the first arithmetic circuits210-1˜210-k may include the pair of the data GIO<0:n> transmitted through the global input/output lines. As a result, the number of the data having the specific logic level may be recognized from the output signals S0_x, S1_x and S2_x of the first arithmetic circuits210-1˜210-k.

The second arithmetic circuits220-1˜220-l may receive the output signals [S0_(x-1), S1_(x-1) and S2_(x-1)] and [S0_x, S1_x and S2_x] of the pair of the first arithmetic circuits210-(x-1) and210-x. The second arithmetic circuit220-1˜220-l may generate the output signals SO0_x, SO1_x, SO2_x and SO3_x representing added results of 0, 1, 2 and 3, respectively.

FIG. 6Bis a table representing the output signals SO0_1, SO1_1, SO2_1and SO3_1in accordance with the input data (SO_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) of the second arithmetic circuit#1220-1.

When the flag generating-enabling signal DBI_DQO_COPY_EN; EN) is disabled, all of the output signals S0_1, S1_1and S2_1may be disabled.

When an added result of the input data is 0, the output signal S0_1of the first arithmetic circuit#1210-1and the output signal S0_2of the first arithmetic circuit#2210-2may be outputted to a high level. When an added result of the input data is 1, the output signal S1_1of the first arithmetic circuit#1210-1and the output signal S1_2of the first arithmetic circuit#2210-2may be outputted to a high level. When an added result of the input data is 2, the output signal S2_1of the first arithmetic circuit#1210-1and the output signal S2_2of the first arithmetic circuit#2210-2may be outputted to a high level.

The second arithmetic circuit#1220-1may add the input data (S0_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) to generate the output signals SO0_1, SO1_1, SO2_1and SO3_1

For example, when the added result of the input data (S0_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) is 0, the second arithmetic circuit#1220-1may output SO0_1to a logic high level. When the added result of the input data (S0_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) is 1, the second arithmetic circuit#1220-1may output SO1_1to a logic high level. When the added result of the input data (S0_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) is 2, the second arithmetic circuit#1220-1may output SO2_1to a logic high level. When the added result of the input data (S0_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) is 3, the second arithmetic circuit#1220-1may output SO2_1and SO1_1to a logic high level. When the added result of the input data (S0_1, S1_1and S2_1) and (S0_2, S1_2and S2_2) is 4, the second arithmetic circuit#1220-1may output SO3_1to a logic high level.

Operations of other second arithmetic circuits220-2˜220-l may be substantially the same as those of the second arithmetic circuit#1220-1.

Thus, the output signals SO0_x, SO1_x, SO2_x and SO3_x of the second arithmetic circuits220-1˜220-l may include the pair of the data S0_x, S1_x and S2_x outputted from the first arithmetic circuits210-1˜210-k. As a result, the number of the data having the specific logic level may be recognized from the output signals SO0_x, SO1_x, SO2_x and SO3_x of the second arithmetic circuits220-1˜220-l.

In an example of an embodiment, the first arithmetic circuits210-1˜210-k and the second arithmetic circuits220-1˜220-l may include an adding circuit. Alternatively, the first arithmetic circuits210-1˜210-k and the second arithmetic circuits220-1˜220-l may include other circuits.

Referring toFIG. 5, the determining circuit230may receive the output signals of the second arithmetic circuits220-1˜220-l to generate the preliminary flag signals DBI_BLx_PRE and DQO_COPY_BLx.

In an example of an embodiment, when the number of the data having a predetermined logic level is no less than half of the total number of the data, the determining circuit230may enable the preliminary DBI flag signal DBI_BLx_PRE based on logic levels of the output signals from the pair of the second arithmetic circuits220-1˜220-l. When the number of the data having the predetermined logic level is 0 or (n+1), the determining circuit230may enable the preliminary duplicate data flag signal DQO_COPY_BLx.

Referring toFIG. 6C, the output signals SO3_1, SO2_1, SO1_1and SO0_1of the second arithmetic circuit220-1may indicate the disablement state (0000) and the added results of 0(0001), 1(0010), 2(0100), 3(0110) and 4(1000). Similarly, the output signals SO3_2, SO2_2, SO1_2and SO0_1of the second arithmetic circuit220-2may indicate the disablement state (0000) and the added results of 0(0001), 1(0010), 2(0100), 3(0110) and 4(1000).

Therefore, when the number of the data having the predetermined logic level is no less than 5, the determining circuit230may enable the preliminary DBI flag signal DBI_BLx_PRE. When the number of the data having the predetermined logic level is 0 or 8, the determining circuit230may enable the preliminary duplicate data flag signal DQO_COPY_BLx.

FIG. 7is a block diagram illustrating a first flag-generating circuit in accordance with an example of an embodiment.

Referring toFIG. 7, the first flag-generating circuit1231-1may include a combination circuit310and an output circuit320.

The combination circuit310may determine an identity of the data from the bit lines by the combination of the preliminary duplicate data flag signal DQO_COPY_BL0˜DQO_COPY_BLm outputted from the preliminary signal-generating circuits1220-0˜1220-m to generate the hit signal HIT.

In an example of an embodiment, when the preliminary duplicate data flag signals DQO_COPY_BL0˜DQO_COPY_BLm have a high level, the combination circuit310may generate the hit signal HIT to a high level.

The output circuit320may receive at least one of the preliminary DBI flag signals DBI_BL0_PRE and the hit signal HIT outputted from the combination circuit310. The output circuit320may output any one of the two input signals as the first flag signal DBI_BL0in response to the duplicate data output-enabling signal DQO_COPY_EN.

In an example of an embodiment, when the duplicate data output-enabling signal DQO_COPY_EN is enabled, the output circuit320may output the hit signal HIT outputted from the combination circuit310as the first flag signal DBI_BL0. When the duplicate data output-enabling signal DQO_COPY_EN is disabled and the DBI-enabling signal DBI_EN is enabled, the output circuit320may output at least one of the preliminary DBI flag signals DBI_BL0_PRE as the first flag signal DBI_BL0.

In an example of an embodiment, the output circuit320may include a multiplexer circuit. Alternatively, the output circuit320may include other circuits.

FIG. 8is a block diagram illustrating a second flag-generating circuit in accordance with an example of an embodiment.

Referring toFIG. 8, the second flag-generating circuit1233-1may include a plurality of output circuits410-1˜410-m.

Each of the output circuits410-1˜410-m may receive the rest of the preliminary DBI flag signals DBI_BL1_PRE˜DBI_BLm_PRE. Each of the output circuits410-1to410-m may receive a ground voltage VSS. When the DBI-enabling signal DBI_EN is enabled, the output circuits410-1˜410-m may output the input signals as the second flag signals DBI_BL1˜DBI_BLm.

When the DBI-enabling signal DBI_EN is disabled, the second flag signals DBI_BL1˜DBI_BLm may have a ground voltage level so that the second flag signals DBI_BL1˜DBI_BLm may be disabled.

In an example of an embodiment, the output circuits410-1˜410-m may include a multiplexer circuit. Alternatively, the output circuits410-1˜410-m may include other circuits.

FIG. 9is a block diagram illustrating an output circuit and a pad group in accordance with an example of an embodiment.

Referring toFIG. 9, the output circuit140-1may include a plurality of data output circuits1401-0˜1401-n and a flag output circuit1403.

The data output circuits1401-0˜1401-n may receive the data GIO0_BL<0:m>˜GIOn_BL<0:m> transmitted through the global input/output lines GIO0˜GIOn. The data output circuits1401-0˜1401-n may code the data GIO0_BL<0:m>˜GIOn_BL<0:m> in accordance with the flag signals DBI_BL<0:m> for each of the bit lines. The data output circuits1401-0˜1401-n may sequentially output the coded data.

The flag output circuit1403may receive the flag signals DBI_BL<0:m> for each of the bit lines. The flag output circuit1403may sequentially output the received flag signals DBI_BL<0:m>.

The pad groups150-1may include a plurality of data pads DQ<0>˜DQ<n> and a flag pad DBI. The data pads DQ<0>˜DQ<n> may output the data provided from the data output circuits1401-0˜1401-n. The flag pad DBI may output the flag signals DBI_BL<0:m> for each of the bit lines provided from the flag output circuit1403.

The data output circuits1401-0˜1401-n inFIG. 9may have substantially the same configuration.

FIG. 10is a block diagram illustrating a data-outputting circuit in accordance with an example of an embodiment.

Referring toFIG. 10, the data output circuit1401-x may include a coding circuit1411, a multiplexer and pipe (multiplexer/pipe) latch1413, and a driver1415.

The coding circuit1411may code the data GIOx_BL<0:m> transmitted through the global input/output lines GIO0˜GIOn in response to the flag signals DBI_BL<0:m> for each of the bit lines. In an example of an embodiment, when the flag signals DBI_BL<0:m> for each of the bit lines are disabled, the coding circuit1411may output the data GIOx_BL<0:m>. When the flag signals DBI_BL<0:m>for each of the bit lines are the DBI flag signals for each of the bit lines, the coding circuit1411may output the inversed or non-inversed data GIOx_BL<0:m> based on the DBI flag signal for each of the bit lines.

When any one of the flag signals DBI_BL<0:m>, for example, the flag signal DBI_BL0with respect to the zeroth bit line include the duplicate data flag signal, the operation of the coding circuit1411may be determined based on the level of the duplicate data flag signal. For example, when the duplicate data flag signal is enabled, only one of the data output circuits1401-0˜1401-n, for example, only the coding circuit of only the data output circuit1401-0may output the data. In contrast, the rest coding circuit of the rest of the data output circuits1401-1˜1401-n may not output the data.

When the flag signals DBI_BL<0:m> for each of the bit lines include the DBI flag signals for each of the bit lines as well as the duplicate data flag signal, the coding circuit1411may output the inversed or non-inversed data GIOx_BL<0:m> based on the rest of the DBI flag signals DBI<1:m> for each of the bit lines.

The multiplexer/pipe latch1413may sequentially output the data from coding circuit1411.

The driver1415may amplify the data outputted from the multiplexer/pipe latch1413. The driver1415may transmit the amplified data to the pad group150.

FIG. 11is a block diagram illustrating a flag-outputting circuit in accordance with an example of an embodiment.

Referring toFIG. 11, the flag output circuit1403may include a multiplexer/pipe latch1431and a driver1433.

The multiplexer/pipe latch1431may sequentially output the flag signals DBI_BL<0:m>.

The driver1433may amplify the flag signals DBI_BL<0:m> outputted from the multiplexer/pipe latch1431. The driver1433may transmit the amplified data to the pad group150.

FIG. 12is a block diagram illustrating an electronic system in accordance with an example of an embodiment.

Referring toFIG. 12, the electronic system50may include a first device510and a second device520.

The first device510may include a receiver. The second device520may include a transmitter and a semiconductor device such as the semiconductor memory device inFIG. 1.

The flag signals DBI_BL<0:m> for each of the bit lines and the data DQ<0:n> may be transmitted between the first device510and the second device520.

When the flag signals DBI_BL<0:m> for each of the bit lines is include the DBI flag signal for each of the bit lines, the second device520may perform an encoding operation for inverting or non-inverting the data DQ<0:n> in accordance with the flag signals DBI_BL<0:m>. The second device520may transmit the encoded data to the first device510. The first device510may decode the data DQ<0:n> in accordance with the flag signals DBI_BL<0:m> for each of the bit lines.

At least one of the flag signals DBI_BL<0:m> for each of the bit lines may include the duplicate data flag signal. When the duplicate data flag signal is enabled, the second device520may transmit only one data DQ<0> to the first device510. The first device510may copy the received data DQ<0> with the rest of the data DQ<1:n> in accordance with the flag signals DBI_BL<0:m>. When the duplicate data flag signal is disable, the second device520may transmit all of the data DQ<0:n> to the first device510. The first device510may copy or receive the received data DQ<0> with the rest of the data DQ<1:n> in accordance with the flag signals DBI_BL<0:m>.

At least one of the flag signals DBI_BL<0:m> for each of the bit lines may include the duplicate data flag signal and the rest of the flag signals DBI_BL<1:m> may include the DBI flag signals with respect to the rest of the bit lines. The second device520may transmit only one data DQ<0> or all of the data DQ<0:n> to the first device510in accordance with an enablement of the duplicate data flag signal. The second device520may perform an encoding operation for inverting or non-inverting the data DQ<0:n> in accordance with the flag signals DBI_BL<1:m> from the rest of the bit lines. The second device520may transmit the encoded data to the first device510. The first device510may copy the received data DQ<0> with the rest of the data DQ<1:n> or all of the data DQ<0:n> in accordance with the flag signals DBI_BL<0:m>. The first device may decode the data DQ<0:n> in accordance with the flag signals DBI_BL<0:m> for each of the bit lines.

The above embodiments of the present disclosure are illustrative and not limitative. Various alternatives and equivalents are possible. The examples of the embodiments are not limited by the embodiments described herein. Nor is the present disclosure limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.