LIQUID CRYSTAL PHASE SHIFTER AND ANTENNA DEVICE

A liquid crystal phase shifter includes a first transistor, a storage capacitor, a phase steering electrode and a common electrode. A first end of the first transistor is electrically connected to a source line, and a control end of the first transistor is configured to receive a first control signal. A first end of the storage capacitor is electrically connected to a second end of the first transistor, and a second end of the storage capacitor is electrically connected to an auxiliary source line. The phase shifting electrode is electrically connected to the second end of the first transistor. The common electrode and the phase shifting electrode form a liquid crystal capacitor, and the common electrode is configured to receive a ground voltage.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number 112119571, filed May 25, 2023, which is herein incorporated by reference.

BACKGROUND

Field of Invention

The disclosure relates to a liquid crystal phase shifter and antenna device. More particularly, the disclosure relates to liquid crystal phase shifter and antenna device associated with liquid crystal based antenna.

Description of Related Art

Nowadays, antennas can be used in many fields, such as, advanced driver assistance system radars, beyond visual line of sight operations for drones, remote monitoring operations of vital signs, emotion recognition, radio transmission, 5G communication, etc. As the array antennas become widely used, how to improve the accuracy of the antennas and to reduce the cost is an important issue in this field.

SUMMARY

In order to solve the foregoing problems, one aspect of the present disclosure is related to a liquid crystal phase shifter which includes a first transistor, a storage capacitor, a phase shifting electrode and a common electrode. A first end of the storage capacitor is electrically connected to a second end of the first transistor, and a second end of the storage capacitor is electrically connected to an auxiliary source line. The phase shifting electrode is electrically connected to the second end of the first transistor. The common electrode is configured to receive a ground voltage. The common electrode and the phase shifting electrode form a liquid crystal capacitor. The liquid crystal phase shifter is attached to a feeding plate, and the common electrode of the liquid crystal phase shifter and a microstrip feed line of the feeding plate form a microstrip antenna.

Another aspect of the present disclosure is related to a liquid crystal phase shifter which includes a phased array. The phased array includes a plurality of first phase shifting circuits, a first source line, a first auxiliary source line and a common electrode. The first phase shifting circuits are arranged in a plurality of rows of a matrix. The first phase shifting circuits comprise a plurality of first transistors, a plurality of first storage capacitors and a plurality of phase shifting electrodes electrically connected to first ends of the first storage capacitors. The first source line is electrically connected to first ends of the first transistors. Second ends of the first transistors are electrically connected to the first ends of the first storage capacitors, respectively. The first auxiliary source line is electrically connected to second ends of the first storage capacitors. The common electrode and the first phase shifting electrodes form a plurality of first liquid crystal capacitors. The common electrode is configured to receive a ground voltage.

Another aspect of the present disclosure is related to an antenna device which includes a feeding plate and a liquid crystal phase shifter. The feeding plate includes a circuit board, a microstrip feed line and a ground layer. The ground layer and the microstrip feed line are disposed in the opposite surfaces of the circuit board. The liquid crystal phase shifter is attached to the feeding plate. The liquid crystal phase shifter overlaps a portion of the microstrip feed line. The liquid crystal phase shifter includes a first substrate, a phased array formed on the first substrate, a liquid crystal layer, a second substrate and a common electrode formed on the second substrate. The liquid crystal layer is disposed between the phased array and the common electrode. The common electrode is electrically connected to the ground layer. The common electrode of the liquid crystal phase shifter and the microstrip feed line of the feeding plate form a microstrip antenna.

Summary, the present disclosure provides a liquid crystal phase shifter including the common electrode configured to receive the ground voltage, in order to use the common electrode as a ground plane of the microstrip antenna, thereby reducing the cost and increasing the accuracy.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the present disclosure, examples of which are described herein and illustrated in the accompanying drawings. While the disclosure will be described in conjunction with embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. Description of the operation does not intend to limit the operation sequence. Any structures resulting from recombination of elements with equivalent effects are within the scope of the present disclosure. It is noted that, in accordance with the standard practice in the industry, the drawings are only used for understanding and are not drawn to scale. Hence, the drawings are not meant to limit the actual embodiments of the present disclosure. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts for better understanding.

In the description herein and throughout the claims that follow, unless otherwise defined, all terms have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. In the description herein and throughout the claims that follow, the terms “comprise” or “comprising,” “include” or “including,” “have” or “having,” “contain” or “containing” and the like used herein are to be understood to be open-ended, i.e., to mean including but not limited to.

A description is provided with reference toFIG.1A.FIG.1Adepicts a schematic diagram of an antenna device100according to some embodiments of the present disclosure. As shown inFIG.1A, the antenna device100includes a liquid crystal phase shifter110, a feeding plate120, a cover plate130, connection elements132and133and a signal generator140.

In some embodiments, the feeding plate120can be implemented by a circuit printed board. In some embodiments, the feeding plate120includes a microstrip feed line122which can be implemented by printed circuit. In some embodiments, the microstrip feed line122is a conductive material, and the microstrip feed line122is configured to transmit the signal supplied from the signal generator140. In some embodiments, the antenna device100can be considered as a microstrip antenna.

In some embodiments, the signal generator140can be implemented by a monolithic microwave integrated circuit. In some embodiments, the signal generator140is electrically connected to the microstrip feed line122to feed the high frequency signal to the microstrip feed line122, in which the said high frequency signal can be radio frequency signal or microwave signal. In some embodiments, the projection of the microstrip feed line122on a horizontal plane extends from the signal generator140to the liquid crystal phase shifter110.

In some embodiments, the liquid crystal phase shifter110overlaps a partial of the microstrip feed line122. As such, the liquid crystal phase shifter110changes the dielectric constant based on the liquid crystal control techniques, so as to adjust the resonant frequency of the microstrip antenna, thereby steering the field pattern and the beam direction of the high frequency signal. In some embodiments, since the large-area element arrays are low-cost to produce, and the process accuracy thereof is better than the traditional array antennas produced by the printed circuit board fabrication process, the liquid crystal phase shifter110produced by the panel manufacturing process can achieve the higher accuracy and lower cost.

In some embodiments, the cover plate130overlaps a partial feeding line of the microstrip feed line122. In some embodiments, the cover plate130is adjacent to the liquid crystal phase shifter110, and the cover plate130is fixed on the feeding plate120by the connection elements132and133which are conductive materials. In some embodiments, the connection elements132and133are components for through holes soldering or screws. In other embodiments, the connection elements132and133can be implemented by the other conductive components, which are not intended to limit the present disclosure.

A description is provided with reference toFIG.1AandFIG.1B.FIG.1Bdepicts a cross section of the antenna device100along a dash-dot line1-2inFIG.1Aaccording to some embodiments of the present disclosure. As shown inFIG.1B, the antenna device100further includes bonding adhesive BA configured to fix the liquid crystal phase shifter110to the feeding plate120. In some embodiments, the feeding plate120includes a microstrip feed line122, a circuit board124and a ground layer126. In some embodiments, the ground layer126and the microstrip feed line122are formed on the opposite surfaces of the circuit board124, and the projection of the ground layer126of the feeding plate120on a horizontal plane does not overlap the liquid crystal phase shifter110.

In some embodiments, the liquid crystal phase shifter110includes substrates112tand112b, a phased array118, a liquid crystal layer116and a common electrode114. In some embodiments, the phased array118is formed on the substrate112t. In some embodiments, the substrates112tand112bcan be implemented by glass substrates, and the material properties of glass substrates have low loss characteristics. In some embodiments, the liquid crystal layer116is disposed between the phased array118and the common electrode114, and the alignment of the liquid crystal in the liquid crystal layer116depends on the voltages controlled by the phased array118, thereby steering the direction of the beam according to the different dielectric constants of different alignments of liquid crystals.

In some embodiments, the cover plate130includes a circuit board138and a conductive layer136disposed in the circuit board138, and the conductive layer136is adjacent to the common electrode114. In some embodiments, the common electrode114of the liquid crystal phase shifter110is electrically connected to the conductive layer136of the cover plate130through the conductive part134. In some embodiments, the conductive part134is soldering component. In some embodiments, the conductive part134is conductive material. As such, the common electrode114of the liquid crystal phase shifter110is electrically connected through the conductive part134, the conductive layer136of the cover plate130and the connection element132to the ground layer126of the feeding plate120, so that the common electrode114of the liquid crystal phase shifter110is grounded. That is, the common electrode114of the liquid crystal phase shifter110can be maintained at the ground voltage GND (such as, 0 volts) through an electrical path between the conductive part134, the conductive layer136of the cover plate130and the connection element132. In the other embodiments, the common electrode114of the liquid crystal phase shifter110can be grounded and maintained at the ground voltage GND (such as, 0 volts) by the other connection manner; the present disclosure is not limited thereto.

In some embodiments, the common electrode114of the liquid crystal phase shifter110is also used as a ground plane of a microstrip antenna, so that the common electrode114of the liquid crystal phase shifter110and the microstrip feed line122can form the microstrip antenna. As such, functions of the ground plane of the microstrip antenna are integrated with the common electrode114of the liquid crystal phase shifter110, in order to reduce the volume and manufacturing process of the antenna device100.

A description is provided with reference toFIG.1BandFIG.2.FIG.2depicts a schematic diagram of substrates112band112t, a liquid crystal layer116and a feeding plate120according to some embodiments of the present disclosure. To be noted that, the front and back surfaces of the substrate112binFIG.2are reversed for better illustrating the phased array118which is formed on the substrate112b. Specifically, in the liquid crystal phase shifter110, the phased array118formed on the substrate112bfaces to the liquid crystal layer116, and the common electrode114formed on the substrate112tfaces to the liquid crystal layer116.

As shown inFIG.2, the phased array118is formed on the substrate112b, and the phased array118includes phase shifting circuits P11and P12. Each of the phase shifting circuits P11˜P12includes a transistor, a storage capacitor and a phase shifting electrode. The elements and connection relationship thereof in the phase shifting circuit are described in detailed in the following embodiments.

In some embodiments, the common electrode114is formed on the substrate112t. In some embodiments, the common electrode114includes multiple slots210(such as, the rectangular slots), and a projection of a center of each of the slots210on the horizontal plane corresponding to an end of the microstrip feed line122. In some embodiments, length of each edges of the slots210of the common electrode114is proportional to wavelength of the high frequency wave, in order to form a microstrip slot antenna by the common electrode114and the microstrip feed line122.

A description is provided with reference toFIG.3.FIG.3depicts a function block of a liquid crystal phase shifter110according to some embodiments of the present disclosure. As shown inFIG.3, the liquid crystal phase shifter110includes a driving circuit310and a phased array118. The driving circuit310is electrically connected to the phased array118, and the driving circuit310is configured to drive the phased array118. The common electrode114is used as a ground plane of the microstrip antenna by maintaining the common electrode114at the ground voltage GND.

Since the common electrode114is used as a ground plane of the microstrip antenna, the polarity reversal driving which is to avoid deformation inertia of the liquid crystal cannot be performed on the common electrode114of the liquid crystal phase shifter110. In addition, the output of the source driver is mostly in a positive voltage range. As such, the following embodiments are described how to provide the positive half cycle and negative half cycle operations while the common electrode114is grounded.

A description is provided with reference toFIG.4.FIG.4depicts a schematic diagram of a liquid crystal phase shifter110according to some embodiments of the present disclosure. As shown inFIG.4, the liquid crystal phase shifter110includes a driving circuit310, a phased array118, transistors Mg1˜Mgm, transistors Ms1˜Msm and conductive lines Gg and Gs. The driving circuit310includes a timing controller410, a gate driving circuit420and a source driving circuit430. In some embodiments, the gate driving circuit420and the source driving circuit430are controlled by the timing controller410. In some embodiments, the gate driving circuit420can be implemented by the gate driver integrated circuit. In the other embodiments, the gate driving circuit420can be implemented by the gate on array techniques. In some embodiments, the source driving circuit430can be implemented by the source driver integrated circuit.

In some embodiments, the phased array118includes phase shifting circuits P11˜P1m, P21˜P2mto Pn1˜Pnm, gate lines G1˜Gn, source lines Sp1˜Spm and auxiliary source lines Ss1˜Ssm, in which “n” and “m” are integers greater than or equal to 1.

In some embodiments, the phase shifting circuits P11˜Pnm arranged in which rows of the phased array118depends on the gate lines G1˜Gn. For example, the phase shifting circuits P11˜P1marranged in a first row are electrically connected to the gate driving circuit420through the gate line G1. The phase shifting circuits P21˜P2marranged in a second row are electrically connected to the gate driving circuit420through the gate line G2, and so on. The phase shifting circuits Pn1˜Pnm arranged in an n-th row are electrically connected to the gate driving circuit420through the gate line Gn. As such, the gate driving circuit420respectively transmit control signals SC1˜SCn through the gate lines G1˜Gn to the phase shifting circuits P11˜Pnm.

In some embodiments, the phase shifting circuit P11˜Pnm arranged in which columns of the phased array118depends on the source lines Sp1˜Spm. For example, phase shifting circuits P11˜Pn1arranged in a first column are electrically connected to the source driving circuit430through the source line Sp1. The phase shifting circuits P12˜Pn2arranged in a second column are electrically connected to the source driving circuit430through the source line Sp2, and so on. The phase shifting circuits P1m˜Pnm arranged in the m-th column are electrically connected to the source driving circuit430through the source line Spm. As such, the voltages supplied from the source driving circuit430are respectively provide through the source lines Sp1˜Spm to the phase shifting circuits P11˜Pnm.

In some embodiments, first ends of the transistor Mg1˜Mgm is grounded. Second ends of the transistors Mg1˜Mgm are electrically connected to the auxiliary source lines Ss1˜Ssm, respectively. Control ends of the transistors Mg1˜Mgm are electrically connected to the gate driving circuit420through the conductive line Gg, so as receive the control signal SCg supplied from the gate driving circuit420.

In some embodiments, the auxiliary source lines Ss1˜Ssm are electrically connected to the corresponding phase shifting circuits P11˜Pnm. Specifically, the auxiliary source line Ss1is electrically connected to the phase shifting circuits P11˜Pn1. The auxiliary source line Ss2is electrically connected to the phase shifting circuits P12˜Pn2, and so on. The auxiliary source line Ssm is electrically connected to the phase shifting circuits P1m˜Pnm.

In some embodiments, first ends of the transistors Ms1˜Msm are electrically connected to the auxiliary source lines Ss1˜Ssm. Second ends of the transistors Ms1˜Msm are electrically connected to the source driving circuit430. Control ends of the transistors Ms1˜Msm are electrically connected to the gate driving circuit420through the conductive line Gs to receive the control signal SCs supplied from the gate driving circuit420.

A description is provided with reference toFIG.4andFIG.5.FIG.5depicts a schematic diagram of a phase shifter circuit Pij according to some embodiments of the present disclosure. In some embodiments, each of the phase shifting circuits P11˜Pnm inFIG.4can be implemented by the phase shifting circuit Pij in the embodiments ofFIG.5, in which “i” refers to a number in a range of 1˜n, and “j” refers to a number in a range of 1˜m. In some embodiments, the phase shifting circuit Pij refers to a phase shifting circuit in i-th row and j-th column. As shown inFIG.5, the phase shifting circuit Pij is electrically connected to the gate line Gi, the source line Spj and the auxiliary source line Ssj. The auxiliary source line Ssj is electrically connected to the transistors Mgj and Msj, in which “i” and “j” are integers greater than or equal to 1. In some embodiments, each of the aforesaid transistors has a first end, a second end and a control end (gate). If a first end of a transistor is a drain end (/source end), a second end of the transistor is a source end (/drain end). And, each of the aforesaid capacitors has a first end and a second end. If a first end of a capacitor is anode (/cathode), a second end of the capacitor is cathode (/anode).

The phase shifting circuit Pij includes a storage capacitor CS, a phase shifting electrode Ep and a transistor T1. In structure, a first end of the transistor T1is electrically connected to the source line Spj. A control end of the transistor T1is electrically connected to the gate line Gi. The control end of the transistor T1is configured to receive the control signal SCi transmitted by the gate line Gi.

Second ends of the transistor T1is electrically connected to a first end of the storage capacitor CS and the phase shifting electrode Ep. In some embodiments, a node N1is a connection between the second end of the transistor T1, the first end of the storage capacitor CS and the phase shifting electrode Ep. There are liquid crystals LC between the phase shifting electrode Ep and the common electrode Ec to form a liquid crystal capacitor CL, and the common electrode Ec is grounded. In some embodiments, the common electrode Ec corresponds to a portion of the common electrode114in the embodiments ofFIG.1BandFIG.2, and the liquid crystals LC correspond to a portion of the liquid crystal layer116in the embodiments ofFIG.1BandFIG.2.

A first end of the storage capacitor CS is electrically connected to a second end of the transistor T1. A second end of the storage capacitor CS is electrically connected to the auxiliary source line Ssj. The e auxiliary source line Ssj is electrically connected to the transistors Mgj and Msj.

A first end of the transistor Mgj is grounded. A control end of the transistor Mgj is configured to receive a control signal SCg. A second end of the transistor Mgj is electrically connected to the auxiliary source line Ssj. In some embodiments, the control signal SCg inFIG.5corresponds to the control signal SCg inFIG.4.

A first end of the transistor Msj is electrically connected to the auxiliary source line Ssj. A control end of the transistor Msj receives the control signal SCs. A second end of the transistor Msj is electrically connected to the source driving circuit430. In some embodiments, the control signal SCs inFIG.5corresponds to the control signal SCs inFIG.4.

For better understanding, a description is provided with reference toFIG.5andFIG.6andFIGS.7A-7D.FIG.6depicts a timing diagram of signals and voltages at nodes of the phase shifter circuit Pij inFIG.5according to some embodiments of the present disclosure.FIG.7AandFIG.7Bdepict operations of the phase shifter circuit Pij inFIG.5during a setting period and positive voltage period of a positive half cycle Cp1according to some embodiments of the present disclosure.FIG.7CandFIG.7Ddepict operations of the phase shifter circuit Pij inFIG.5during a setting period and a negative voltage period of a negative half cycle Cn1according to some embodiments of the present disclosure.

As shown inFIG.6, a cycle of the control timing of the phase shifting circuit Pij can be divided into two half cycles which are a positive half cycle Cp1and a negative half cycle Cn1. The positive half cycle Cp1includes two periods which are a setting period Psa1and a positive voltage period Ppv1. The negative half cycle Cn1includes two periods which are a setting period Psb1and a negative voltage period Pnv1. In some embodiments, the setting periods Psa1and Psb1can be considered as the data setting periods and/or scan periods. In some embodiments, the positive voltage period Ppv1refers to a period that the voltage at the phase shifting electrode Ep is set at 0 volts or a positive voltage, the negative voltage period Pnv1refers to a period that the voltage at the phase shifting electrode Ep is set at 0 volts or a negative voltage.

In some embodiments, the time length of each of the positive half cycle Cp1and the negative half cycle Cn1of the control timing of the phase shifting circuit Pij is 1 ms, in which the time length of each of the setting period Psa1and the setting period Psb1is 180 μs, and the time length of each of the positive voltage period Ppv1and the negative voltage period Pnv1is 820 μs. In some embodiments, the time length of each of the positive voltage period Ppv1and the negative voltage period Pnv1is longer than the time length of each of the setting periods Psa1and Psb1. In the other embodiments, time lengths of the setting periods Psa1and Psb1, the positive voltage period Ppv1and the negative voltage period Pnv1can be implemented by the appropriate time lengths; it is not intended to limit the present disclosure.

Specifically, the control signal SCg is at a low logic level in the setting period Psa1of the positive half cycle Cp1and the setting period Psb1of the negative half cycle Cn1. The control signal SCg is at a high logic level in the positive voltage period Ppv1of the positive half cycle Cp1and the negative voltage period Pnv1of the negative half cycle Cn1. The control signal SCs is at the high logic level in the setting period Psa1of the positive half cycle Cp1and the setting period Psb1of the negative half cycle Cn1. The control signal SCs is at the low logic level in the positive voltage period Ppv1of the positive half cycle Cp1and the negative voltage period Pnv1of the negative half cycle Cn1. In some embodiments, the control signal SCi can be considered as the scan signal.

In some embodiments, the voltages Vai and Vbi supplied by the source driving circuit430are larger than or equal to 0 volts. In some embodiments, the voltages Vai and Vbi supplied by the source driving circuit430are not less than 0 volts. In some embodiments, the voltages supplied by the source driving circuit430are 0 volts and/or positive voltages. In some embodiments, the voltages supplied by the source driving circuit430are not less than 0 volts. To be noted that, each pulse width (e.g., 15 μs) corresponding to the voltages Vai and Vbi supplied by the source driving circuit430is longer than each pulse width (e.g., 10 μs) of the control signal Sci, and each pulse corresponding to the voltages Vai and Vbi supplied by the source driving circuit430overlaps each pulse of the control signal Sci on the timeline.

As shown inFIG.7A, in the setting period Psa1of the positive half cycle Cp1, the transistor Msj is turned on according to the control signal SCs at a high logic level. On the other hand, the transistor Mgj is turned off according to the control signal SCg at a low logic level. In the setting period Psa1, the reference voltage supplied by the source driving circuit430is transmitted through the transistor Msj and auxiliary source line Ssj to the second end of the storage capacitor CS. During the second end of the storage capacitor CS being set at the reference voltage, the transistor T1is turned on according to the control signal SCi, in order to transmit the voltage Vai supplied by the source driving circuit430through the source line Spj and the transistor T1to the first end of the storage capacitor CS.

In some embodiments, the above said reference voltage can be implemented by 0 volts. In some embodiments, the above said reference voltage can be implemented by a voltage which is less than or equal to the voltage Vai, which is not intended to limit the present disclosure. In other words, when the reference voltage supplied by the source driving circuit430is transmitted to the second end of the storage capacitor CS, a voltage (that is, a voltage at node N1) at the first end of the storage capacitor CS is set at the voltage Vai, and the voltage Vai is greater than or equal to 0 volts.FIG.6illustrates an example that the voltage Vai is greater than 0 volts.

As shown inFIG.7B, in the positive voltage period Ppv1of the positive half cycle Cp1, the transistor Msj is turned off according to the control signal SCs at a low logic level. On the other hands, the transistor Mgj is turned on according to the control signal SCg at the high logic level. In the positive voltage period Ppv1, the transistor Mgj is turned on and the second end of the storage capacitor CS is grounded. At this time, since the transistor T1turns off the path between the first end of the storage capacitor CS and the source line Spj, a voltage (that is, a voltage at node N1) at the first end of the storage capacitor CS is still maintained at the voltage Vai. Therefore, the voltage at the phase shifting electrode Ep is also voltage Vai, so as to control the alignment of the liquid crystals.

As shown inFIG.7C, in the setting period Psb1of the negative half cycle Cn1, the transistor Msj is turned on according to the control signal SCs at the high logic level. On the other hand, the transistor Mgj is turned off according to the control signal SCg at the low logic level. In the setting period Psb1, the voltage Vbi supplied by the source driving circuit430is transmitted through the transistor Msj and the auxiliary source line Ssj to the second end of the storage capacitor CS, and the voltage Vbi is greater than or equal to 0 volts.FIG.6illustrates an example that the voltage Vbi is greater than 0 volts. During the second end of the storage capacitor CS being set at the voltage Vbi, the transistor T1is turned on according to the control signal SCi to transmit the reference voltage (e.g. a reference voltage of 0 volts) supplied by the source driving circuit430through the source line Spj and the transistor T1to a first end of the storage capacitor CS. In other words, when the voltage Vbi supplied by the source driving circuit430is transmitted to the second end of the e storage capacitor CS, a voltage (that is, a voltage at the node N1) at the first end of the storage capacitor CS is set at 0 volts, such that the voltage at the first end of the storage capacitor CS is less than or equal to the voltage at the second end of the storage capacitor CS.

As shown inFIG.7D, in the negative voltage period Pnv1of the negative half cycle Cn1, the transistor Msj is turned off according to the control signal SCs at the low logic level. On the other hand, the transistor Mgj is turned on according to the control signal SCg at the high logic level. In the negative voltage period Pnv1, the transistor Mgj is turned on and the second end of the storage capacitor CS is grounded. Since the transistor T1turns off a path between the first end of the storage capacitor CS and the source line Spj, a voltage variation at the second end of the storage capacitor CS variated from the voltage Vbi to a ground voltage is transferred to the first end of the storage capacitor CS by capacitive coupling effect. At this time, a voltage (that is, the voltage at node N1) at the first end of the storage capacitor CS can be expressed by the voltage Vpi in the following formula.

In the above formula, a capacitance of the storage capacitor CS is expressed by CS, and a capacitance of the liquid crystal capacitor CL is expressed by the CL. As such, in the negative voltage period Pnv1, the voltage at the phase shifting electrode Ep is equal to the voltage Vpi which is less than or equal to 0 volts (the voltage Vpi illustrated in the embodiment ofFIG.6is less than 0 volts), so as to control the alignment of the liquid crystals. As a result, the operation at the negative half cycle can be provided on a basis of the voltages supplied by the source driving circuit430greater than and/or less than 0 volts, in order to avoid the deformation inertia of the liquid crystal.

And then, the nest cycle C2includes a positive half cycle Cp2and a negative half cycle Cn2. The positive half cycle Cp2includes two periods which are a setting period Psa2and a positive voltage period Ppv2. The negative half cycle Cn2includes two periods which are a setting period Psb2and a negative voltage period Pnv2.

In the setting period Psa2of the positive half cycle Cp2, the source driving circuit430transmits the voltage Vai′ through the source line Spi to the node N1, and a voltage at the node N1is set at the voltage Vai′ which remains to the positive voltage period Ppv2of the positive half cycle Cp2. In the setting period Psb2of the negative half cycle Cn2, since the source driving circuit430transmits the reference voltage (e.g. 0 volts) through the source line Spi to the node N1, and the source driving circuit430transmits the voltage Vbi′ through the auxiliary source line Spi to the second end of the storage capacitor CS.

In the negative voltage period Pnv2of the negative half cycle Cn2, the second end of the storage capacitor CS is grounded, and a voltage variation (e.g. (0-Vbi′) volts) at the second end of the storage capacitor CS variated from the voltage Vbi′ to the ground voltage is transferred to the first end of the storage capacitor CS by the capacitive coupling effect. At this time, a voltage (that is, a voltage at the node N1) at the first end of the storage capacitor CS can be expressed by the voltage Vpi′ in the following formula.

As such, in the negative voltage period Pnv2, a voltage at the phase shifting electrode Ep is equal to the voltage Vpi′ which is less than or equal to 0 volts (the voltage Vpi′ illustrated in the embodiment ofFIG.6is less than 0 volts), so as to control the alignment of the liquid crystals. As a result, the operation at the negative half cycle can be provided on a basis of the voltages supplied by the source driving circuit430greater than and/or less than 0 volts, in order to avoid the deformation inertia of the liquid crystal. In other words, the voltages supplied by the source driving circuit430are not less than 0 volts.

The detail operation of the phase shifting circuit Pij in cycle C2is similar to the operation of the phase shifting circuit Pij in cycle C1, and the description is omitted here.

A description is provided with reference toFIG.8.FIG.8depicts a schematic diagram of a phased array118according to some embodiments of the present disclosure. In some embodiments, the phased array118includes phase shifting circuits P11˜P31and P12˜P32which correspond to the phase shifting circuits P11˜Pn2inFIG.4. As shown inFIG.8, the phase shifting circuits P11˜P31are respectively arranged in the first to third rows of the matrix. The phase shifting circuits P11˜P31includes transistors T11˜T31, storage capacitors CS11˜CS31and phase shifting electrodes EP11˜EP31.

Specifically, first ends of the transistors T11˜T31are electrically connected to the source line Sp1. Control ends of the transistors T11˜T31are electrically connected to the gate lines G1˜G3, and the control ends of the transistors T11˜T31receive the control signals SC1˜SC3through the gate lines G1˜G3, respectively. Second ends of the transistors T11˜T31are respectively electrically connected to the first ends of the storage capacitors CS11˜CS31and the phase shifting electrodes Ep11˜Ep31. The phase shifting electrodes Ep11˜Ep13and the common electrodes Ec11˜Ec31form the liquid crystal capacitors CL11˜CL13. In some embodiments, the common electrode Ec11˜Ec31correspond to a portion of the common electrode114inFIGS.1B and2.

Similarity, the phase shifting circuits P12˜P32are respectively arranged in the first to third rows of the matrix. The phase shifting circuits P12˜P32include transistors T12˜T32, storage capacitors CS12˜CS32and phase shifting electrodes EP12˜EP32. Specifically, first ends of the transistors T12˜T32are electrically connected to the source line Sp2. Control ends of the transistors T12˜T32are electrically connected to the gate lines G1˜G3, and the control ends of the transistors T12˜T32receive the control signals SC1˜SC3through the gate lines G1˜G3.

Second ends of the transistors T12˜T32are respectively connected to the first ends of the storage capacitors CS12˜CS32and the phase shifting electrodes Ep12˜Ep32. In some embodiments, the nodes N12˜N32are the connections between the phase shifting electrodes Ep12˜Ep32and the corresponding storage capacitors CS12˜CS32, respectively. The phase shifting electrodes Ep12˜Ep32and the common electrodes Ec12˜Ec32form the liquid crystal capacitors CL12˜CL32. In some embodiments, the common electrodes Ec12˜Ec32respectively correspond to the portions of the common electrode114inFIG.1BandFIG.2. The connection relationship of the elements included in the phase shifting circuits P12˜P32is similar to the connection relationship of the elements included in the phase shifting circuits P11˜P31, and the description is omitted here.

A description is provided with reference toFIG.4,FIG.8andFIG.9.FIG.9depicts a timing diagram of signals and voltages at nodes of phase shifting circuits P11˜P31included in the phased array118inFIG.8according to some embodiments of the present disclosure. As shown inFIG.9, a cycle of a control timing of the phased array118can be divided into two half cycles which are a positive half cycle Cp1and a negative half cycle Cn1. The positive half cycle Cp1includes two periods which are a setting period Psa1and a positive voltage period Ppv1. The negative half cycle Cn1includes two periods which are a setting period Psb1and a negative voltage period Pnv1.

In the setting period Psa1of the positive half cycle Cp1, the transistor T11˜T31are turned on in sequence according to the control signals SC1˜SC3, in order to transmit the voltages Va1˜Va3through the source line Sp1to the first ends of the storage capacitors CS11˜CS31in sequence. At this time, the transistor Mg1is turned off according to the control signal SCg, and the transistor Ms1is turned on according to the control signal SCs, so as to transmit the voltage (e.g. 0 volts) supplied by the source driving circuit430to the second ends of the storage capacitors CS11˜CS31.

In the positive voltage period Ppv1of the positive half cycle Cp1, the transistors T11˜T31are turned off according to the control signals SC1˜SC3. At this time, the transistor Ms1is turned off according to the control signal SCs, and the transistor Mg1is turned on according to the control signal SCg, such that the second ends of the storage capacitors CS11˜CS31are grounded. As such, the phase shifting circuit P11˜P31respectively control the alignment of the liquid crystals according to the voltages Va1˜Va3at the phase shifting electrodes Ep11˜Ep31, in order to control the direction and the wave field of the high frequency signal.

In the setting period Psb1of the negative half cycle Cn1, the transistor T11˜T31are turned on in sequence according to the control signals SC1˜SC3, so as to transmit the reference voltage (e.g. 0 volts) through the source line Sp1to the first ends of the storage capacitor CS11˜CS31in sequence. At this time, the transistor Mg1is turned off according to the control signal SCg, and the transistor Ms1is turned on according to the control signal SCs, in order to transmit the voltages Vb1˜Vb3supplied from the source driving circuit430through the source line Ss1to the second ends of the storage capacitors CS11˜CS31, such that the voltage differences between two ends of each of the storage capacitors CS11˜CS31are set at (0-Vb1) volts, (0-Vb2) volts and (0-Vb3) volts.

In the negative voltage period Pnv1of the negative half cycle Cn1, the transistors T11˜T31are turned off according to the control signals SC1˜SC3. At this time, the transistor Ms1is turned off according to the control signal SCs, and the transistor Mg1is turned on according to the control signal SCg, such that the second ends of the storage capacitors CS11˜CS31are grounded. The voltage variations of the second ends of the storage capacitor CS11˜CS31variated from the voltages Vb1˜Vb3to the ground voltage are (0-Vb1) volts, (0-Vb2) volts and (0-Vb3) volts are transferred to the first ends of the storage capacitor CS11˜CS31. At this time, the voltages Vp1˜Vp3at the first ends of the storage capacitor CS11˜CS31(which correspond to the node N11˜N31) can be expressed by the following formula.

In the above formula, the value of the voltage Vb2(e.g. 0 volts) is for an example, and the voltage Vp2is equal to 0 volts in this case. As such, in the negative voltage period Pnv1, the voltages at the phase shifting electrodes Ep11˜EP31are voltages Vp1˜Vp3which less than or equal to 0 volts, in order to control the alignment of the liquid crystal based on the voltages Vp1˜Vp3, such that operation in the negative half cycle is provided. In some embodiments, the voltages Vb1˜Vb3supplied by the source driving circuit430are in the negative half cycle Cn1are greater than or equal to 0 volts (FIG.9illustrates an example that the voltages Vb1and Vb3is greater than 0 volts and the voltage Vb2is equal to 0 volts), such that the output range of the source driving circuit430does not need to include the negative voltage range.

As such, the voltages at the phase shifting electrode Ep11˜Ep31are set at positive voltages and/or the ground voltage in the positive voltage period Ppv1, and the voltages at the phase shifting electrode Ep11˜Ep31are set at negative voltages and/or the ground voltage in the negative voltage period Pnv1by the capacitive coupling effect, so as to avoid the deformation inertia of the liquid crystal.

In the positive half cycle Cp2of the next cycle, the source driving circuit430sets the voltages Va1′˜Va3′ to the first ends of the storage capacitors CS11˜CS31in sequence, and the first ends of the storage capacitors CS11˜CS31are maintained at the voltages Val′˜Va3′.

In the setting period Psb2of the negative half cycle Cn2, the source driving circuit430set the voltages Vb1′˜ Vb3′ to the second ends of the storage capacitors CS11˜CS31, and the voltage variations at the second ends of the storage capacitors CS11˜CS31are transferred to the first ends of the storage capacitors CS11˜CS31in the negative voltage period Pnv2, such the voltage Vp1′˜ Vp3′ at the first ends of the storage capacitor CS11˜CS31are equal to and/or less than 0 volts (FIG.9illustrates an example that the voltages Vp1′ and Vp3′ are less than 0 volts and the voltage Vp2is equal to 0 volts).

The operations in the setting period Psa2and the positive voltage period Ppv2of the positive half cycle Cp2and the setting period Psb2and the negative voltage period Pnv2of the negative half cycle Cn2are similar to the operations in the setting period Psa2and the positive voltage period Ppv2of the positive half cycle Cp1and the setting period Psb2and the negative voltage period Pnv2of the negative half cycle Cn1, and the description is omitted here. The operations of phase shifting circuits P12˜P32in the second column of the phased array118inFIG.8are similar to the operations of phase shifting circuits P11˜P31in the first column of the phased array118inFIG.8, and the description is omitted here.

A description is provided with reference toFIG.1A-1B,FIG.5andFIG.10.FIG.10depicts a cross section of a portion of the antenna device100inFIG.1Aaccording to some embodiments of the present disclosure. As shown inFIG.10, the transistor T1is formed on the substrate112band faces to the liquid crystal layer116. The common electrode114is formed on the substrate112tand faces to the liquid crystal layer116. There is a liquid crystal layer116between the substrate112band the substrate112t. A first end of the transistor T1is electrically connected to the liquid crystal capacitor CL formed by the phase shifting electrode EP and a portion of the common electrode114.

In some embodiments, the common electrode114is formed on the first surface of the substrate112t, and a first surface of the feeding plate120is attached to a second surface of the substrate112tby the bonding adhesive BA. In some embodiments, the microstrip feed line122is formed on the first surface of the feeding plate120. As such, the microstrip feed line122and the common electrode114form the microstrip antenna.

Summary, the liquid crystal phase shifter110and the feeding plate120of the antenna device100can reduce the cost of the traditional array antennas produced by the printed circuit board fabrication process and to reduce the use of high frequency printed circuit boards. The microstrip antenna is formed by the common electrode114of the liquid crystal phase shifter110and the microstrip feed line122of the feeding plate120, such that the volume and cost of the manufacturing process can be reduced. Furthermore, the circuit structure and the configuration control signals of the antenna device100of the present disclosure can provide the operations in positive half cycle and negative half cycle without changing the output range of the source driving circuit430, in order to avoid the deformation inertia of the liquid crystal.

Although specific embodiments of the disclosure have been disclosed with reference to the above embodiments, these embodiments are not intended to limit the disclosure. Various alterations and modifications may be performed on the disclosure by those of ordinary skills in the art without departing from the principle and spirit of the disclosure. Thus, the protective scope of the disclosure shall be defined by the appended claims.