Method and system for optimizing performance of a PCD while mitigating thermal generation

A temperature of a component within the portable computing device (PCD) may be monitored along with a parameter associated with the temperature. The parameter associated with temperature may be an operating frequency, transmission power, or a data flow rate. It is determined if the temperature has exceeded a threshold value. If the temperature has exceeded the threshold value, then the temperature is compared with a temperature set point and a first error value is then calculated based on the comparison. Next, a first optimum value of the parameter is determined based on the first error value. If the temperature is below or equal to the threshold value, then a present value of the parameter is compared with a desired threshold for the parameter and a second error value is calculated based on the comparison. A second optimum value of the parameter may be determined based on the second error value.

DESCRIPTION OF THE RELATED ART

Portable computing devices (“PCDs”) are becoming necessities for people. And optimal performance is desired for these battery operated devices. To achieve optimal performance, PCDs need to manage their internal temperature constantly. PCDs are battery operated devices and therefore, most PCDs do not have any active cooling devices, like fans. So PCDs use thermal mitigation algorithms. Thermal mitigation algorithms help in cooling a PCD passively when it gets hotter than a prescribed temperature threshold.

The thermal mitigation algorithms rely on embedded, on-die thermal sensors (TSENS) to obtain the instantaneous temperature of the various components (e.g., central processing unit [“CPU”] cores, graphics processing unit [“GPU”] cores, modems, etc.) present within a PCD. When any of the components heats up beyond a prescribed temperature, the thermal algorithms(s) are usually designed to throttle those components to reduce their heat generation.

The thermal mitigation algorithms(s) usually must be capable of adapting the device parameters to the heating characteristics of the device to effectively cool them down. At the same time, throttling the operating frequency of a CPU or GPU of a PCD may negatively impact the overall performance of the device. Similarly, throttling data rate and/or transmit power for modems of a PCD may also negatively impact the performance of the device.

Another problem experienced by PCDs include ones caused by battery current limitations (“CLs”).CLs may occur when a particular component within a PCD draws a lot of current within a short time frame (of the order of microseconds) from the battery resulting in a voltage drop across critical components.

Unfortunately, certain critical components, such as memory, CPU, etc. inside the PCD require a minimum voltage to sustain their operation. When a component suddenly draws more power than it commonly does, the resulting voltage drop may result in a device failure (which may cause data erasures from the memory, device reboot, or in worst case, an overheated or permanently damaged device).

A CL situation may arise when, for instance, a CPU core of a PCD (such as a mobile phone) becomes more active when other cores are actively loaded, or a data call is initiated during a voice call, or the camera flash is activated while playing a game on the device. The CL situation may become worse when the battery charge is already low and/r when the temperature of the PCD rises.

Accordingly, what is needed in the art is a method and system for one or more algorithms that may mitigate thermal issues of a PCD while also minimizing the performance degradation experienced by the components due to throttling.

SUMMARY OF THE DISCLOSURE

A temperature of a component within the portable computing device (PCD) may be monitored along with a parameter associated with the temperature. The parameter associated with temperature may be an operating frequency, transmission power, or a data flow rate. It is determined if the temperature has exceeded a threshold value. If the temperature has exceeded the threshold value, then the temperature is compared with a temperature set point and a first error value is then calculated based on the comparison. Next, a first optimum value of the parameter is determined based on the first error value. If the temperature is below or equal to the threshold value, then a present value of the parameter is compared with a desired threshold for the parameter and a second error value is calculated based on the comparison. A second optimum value of the parameter may be determined based on the second error value.

The component of the PCD may be set to at least one of the first and second optimum values. The component may include at least one of a central processing unit, a core of a central processing unit, a graphical processing unit, a digital signal processor, a modem, and a RF-transceiver. The portable computing device may include at least one of a mobile telephone, a personal digital assistant, a pager, a smartphone, a navigation device, and a hand-held computer with a wireless connection or link.

DETAILED DESCRIPTION

In this description, the terms “communication device,” “wireless device,” “wireless telephone,” “wireless communication device,” and “wireless handset” are used interchangeably. With the advent of third generation (“3G”) and fourth generation (“4G”) wireless technology, greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities.

In this description, the term “portable computing device” (“PCD”) is used to describe any device operating on a limited capacity power supply, such as a battery. Although battery operated PCDs have been in use for decades, technological advances in rechargeable batteries coupled with the advent of third generation (“3G”) wireless technology, have enabled numerous PCDs with multiple capabilities. Therefore, a PCD may be a cellular telephone, a satellite telephone, a pager, a PDA, a smartphone, a navigation device, a smartbook or reader, a media player, a combination of the aforementioned devices, and a laptop computer with a wireless connection, among others.

Referring toFIG. 1, this figure is a functional block diagram of an exemplary, non-limiting aspect of a PCD100in the form of a wireless telephone for implementing methods and systems for optimizing performance of the PCD100and while mitigating thermal generation within the PCD100. As shown, the PCD100includes an on-chip system102that includes a multi-core central processing unit (“CPU”)110and an analog signal processor126that are coupled together. The CPU110may comprise a zeroth core222, a first core224, and an Nth core230as understood by one of ordinary skill in the art. Instead of a CPU110, a digital signal processor (“DSP”) may also be employed as understood by one of ordinary skill in the art.

The CPU110may also be coupled to one or more internal, on-chip thermal sensors157A-B as well as one or more external, off-chip thermal sensors157C-D. The on-chip thermal sensors157A-B may comprise one or more proportional to absolute temperature (“PTAT”) temperature sensors that are based on vertical PNP structure and are usually dedicated to complementary metal oxide semiconductor (“CMOS”) very large-scale integration (“VLSI”) circuits. The off-chip thermal sensors157C-D may comprise one or more thermistors.

The thermal sensors157may produce a voltage drop (and/or a current) that is converted to digital signals with an analog-to-digital converter (“ADC”) (not illustrated). However, other types of thermal sensors157may be employed without departing from the scope of this disclosure.

The PCD100ofFIG. 1may include and/or be coupled to a dual proportional integral derivative (“PID”) loop controller205. The dual PID loop controller205may comprise hardware, software, firmware, or a combination thereof. The dual PID loop controller205may be responsible for monitoring temperature of the PCD100and adjusting one or more parameters based on whether a temperature threshold or limit has been reached/achieved. Such parameters which may be adjusted include, but are not limited to, an operating frequency of a component such as the CPU110, processor126, and/or GPU189; transmission power of the RF transceiver168which may comprise a modem; data rate or flow rates of the processor126; as well as other parameters of the PCD100which may mitigate thermal generation and that may also impact operating performance of the PCD100.

The dual PID loop controller205comprises two controllers (seeFIG. 2A) which calculate separate error values relative to each other. One controller is provided with a temperature input while the other controller is provided with an input of an adjustable parameter. One interesting aspect of the dual PID loop controller205is that each PID controller has output that may control/impact the same adjustable parameter, such as operating frequency.

Further details of the dual PID loop controller205are described below in connection withFIG. 2A. The exemplary embodiment of the dual PID loop controller205ofFIGS. 1 and 2Ashow the dual PID loop controller205for controlling the operating frequency of the CPU110. However, as noted above, the dual PID loop controller205may be coupled and/or logically connected to any component and/or a plurality of components within the PCD100. Further, the dual PID loop controller205may also adjust parameters other than operating frequency of a component, such as, but not limited to, transmission power, data flow rates, etc. as mentioned above.

In a particular aspect, one or more of the method steps for the dual PID loop controller205described herein may be implemented by executable instructions and parameters, stored in the memory112, that may form software embodiments of the dual PID loop controller205. These instructions that form the dual PID loop controller205may be executed by the CPU110, the analog signal processor126, or any other processor. Further, the processors,110,126, the memory112, the instructions stored therein, or a combination thereof may serve as a means for performing one or more of the method steps described herein.

The power manager integrated controller (“PMIC”)107may be responsible for distributing power to the various hardware components present on the chip102. The PMIC is coupled to a power supply180. The power supply180, may comprise a battery and it may be coupled to the on-chip system102. In a particular aspect, the power supply may include a rechargeable direct current (“DC”) battery or a DC power supply that is derived from an alternating current (“AC”) to DC transformer that is connected to an AC power source.

As illustrated inFIG. 1, a display controller128and a touchscreen controller130are coupled to the multi-core processor110. A touchscreen display132external to the on-chip system102is coupled to the display controller128and the touchscreen controller130.

FIG. 1is a schematic diagram illustrating an embodiment of a portable computing device (PCD) that includes a video decoder134. The video decoder134is coupled to the multicore central processing unit (“CPU”)110. A video amplifier136is coupled to the video decoder134and the touchscreen display132. A video port138is coupled to the video amplifier136. As depicted inFIG. 1, a universal serial bus (“USB”) controller140is coupled to the CPU110. Also, a USB port142is coupled to the USB controller140. A memory112and a subscriber identity module (SIM) card146may also be coupled to the CPU110.

Further, as shown inFIG. 1, a digital camera or camera subsystem148may be coupled to the CPU110. In an exemplary aspect, the digital camera/cameral subsystem148is a charge-coupled device (“CCD”) camera or a complementary metal-oxide semiconductor (“CMOS”) camera.

As further illustrated inFIG. 1, a stereo audio CODEC150may be coupled to the analog signal processor126. Moreover, an audio amplifier152may be coupled to the stereo audio CODEC150. In an exemplary aspect, a first stereo speaker154and a second stereo speaker156are coupled to the audio amplifier152.FIG. 1shows that a microphone amplifier158may be also coupled to the stereo audio CODEC150. Additionally, a microphone160may be coupled to the microphone amplifier158.

In a particular aspect, a frequency modulation (“FM”) radio tuner162may be coupled to the stereo audio CODEC150. Also, an FM antenna164is coupled to the FM radio tuner162. Further, stereo headphones166may be coupled to the stereo audio CODEC150.

FIG. 1further indicates that a radio frequency (“RF”) transceiver168may be coupled to the analog signal processor126. An RF switch170may be coupled to the RF transceiver168and an RF antenna172. As shown inFIG. 1, a keypad174may be coupled to the analog signal processor126. Also, a mono headset with a microphone176may be coupled to the analog signal processor126. Further, a vibrator device178may be coupled to the analog signal processor126.

As depicted inFIG. 1, the touchscreen display132, the video port138, the USB port142, the camera148, the first stereo speaker154, the second stereo speaker156, the microphone160, the FM antenna164, the stereo headphones166, the RF switch170, the RF antenna172, the keypad174, the mono headset176, the vibrator178, thermal sensors157B, and the power supply180are external to the on-chip system102.

Referring now toFIG. 2A, is a functional block diagram illustrating details of the dual proportional integral derivative (“PID”) loop controller205for a CPU110of the PCD ofFIG. 1. As noted above, the dual PID loop controller205may be implemented in software, hardware, firmware, or a combination thereof.

The dual PID loop controller205may comprise a temperature threshold block206, a first control loop209, and a second control loop212. The first control loop209may control the adjustable parameter of a device when a first threshold is met, such as the operating frequency for a clock (not illustrated) of the CPU110. Meanwhile, the second control loop212of the dual PID loop controller205may control the adjustable parameter of the device when a second threshold is met.

In the exemplary embodiment illustrated inFIG. 2A, the threshold condition/block206of the dual PID loop controller205is an operating temperature of a CPU110of the PCD100. As noted previously, the dual PID loop controller205may control other devices besides a CPU110. For example, the dual PID loop controller205may control the GPU189, RF transceiver168, and/or analog signal processor126, or any other device of the PCD100.

In the exemplary embodiment ofFIG. 2A, if the temperature of the CPU110is greater than a predetermined threshold, then the “YES” branch of the threshold block206is followed to the first loop209in which the first loop209controls the adjustable parameter, which in this example is an operating frequency of the CPU110.

Meanwhile, if the temperature of the CPU110is less than or equal to the predetermined threshold, then the “NO” branch of the threshold block206is followed to the second loop212in which the second loop212controls the adjustable parameter, which in this example is an operating frequency of the CPU110.

The first loop209of the dual PID loop controller205may comprise a temperature input block157, a desired temperature setpoint/target218, and a first PID controller221A. The temperature input block157may comprise outputs from any one or a plurality of temperature data generated and tracked by the thermal sensors157described above in connection withFIG. 1. The desired temperature setpoint/target218may comprise a desired maximum temperature for the CPU110. This desired temperature setpoint/target218may be a fixed/set value and/or it may be dynamic meaning that it can be adjusted by one or more thermal mitigation algorithms/strategies which may be running concurrently relative to the dual PID loop controller205.

The data from block157and block218and produces a temperature error value (Te1) which is provided as input to a first PID controller221A. The first PID controller221A uses the temperature error value (Te1) to calculate a frequency value by how much the operating frequency of the CPU110should be adjusted to reach the desired temperature setpoint/target218. This frequency value which is the output of the first PID controller221A is fed to an adjust CPU frequency block235where the operating frequency of the CPU110may be adjusted based on this frequency value. Further details of the first PID controller221A will be described below.

Meanwhile, as noted above, if the temperature of the CPU110is less than or equal to the predetermined threshold, then the “NO” branch of the threshold block206is followed to the second loop212in which the second loop212controls the adjustable parameter, which in this example is an operating frequency of the CPU110.

The second loop212may comprise a frequency input block224, a desired max operating frequency227, and a second controller221B. The frequency input block224may comprise outputs from any one or a plurality of a clock frequency sensors or the clock itself (not illustrated) of the CPU110.

As noted above, the second loop212may control another adjustable parameter besides frequency, such as transmission power, data flow rates, etc., which may impact thermal generation of the PCD100. For the exemplary embodiment, the second loop212is designed to manage and control the operating frequency of the CPU110when a predetermined threshold is met.

The desired max operating frequency227of the second loop212may comprise a desired maximum operating frequency for the CPU110. This desired maximum operating frequency227may be a fixed/set value and/or it may be dynamic meaning that it can be adjusted by one or more thermal mitigation algorithms/strategies and/or performance enhancing algorithms, such as a Dynamic Clock Voltage Scaling (“DCVS”) algorithm, which may be running concurrently relative to the dual PID loop controller205.

The data from block224and block227are compared and produce a frequency error value (Fe1) which is provided as input to a second PID controller221B. The second PID controller221B uses the frequency error value (Fe1) to calculate a frequency value by how much the operating frequency of the CPU110should be adjusted to reach the desired maximum operating frequency227. This frequency value which is the output of the second PID controller221B is fed to an adjust CPU frequency block235where the operating frequency of the CPU110may be adjusted based on this frequency value. Further details of the second PID controller221B will be described below.

The two loops209,212forming the dual PID loop controller205work in tandem relative to each other. In the illustrated exemplary embodiment ofFIG. 2A, the first loop209is responsible for maintaining device reliability by throttling the parameters when temperature is greater than desired value in threshold block206. Meanwhile, the second loop212is responsible for maintaining performance by adjusting the same parameters when temperature is less than the desired value in threshold block206. Each loop209,212has its own setpoint218,227and input157,224, but the second loop212is active only when the first loop209is not active, and vice-versa.

Further, each loop209,212has their own independent dynamics. This means that one loop error accumulations will not affect the other. Each PID controller221A,221B operates according to the following equation:

Where q(n) is the output of the output of the PID controller proportional to the adjustment to be made at time n; Kp is a proportional error value constant, Ki is an integral error value constant; Kd is a derivative error value constant; e(n) is the error function defined by the difference between the parameter at time n and the desired setpoint; ts is the sampling duration; and i is the integration variable. The value of the contstants (“Ks”) are determined by experiments and simulations, so that the PID controller output is stable and the setpoint intended is reached as quickly as possible with limited overshoots.

Equation EQ1 may lead to integral windup, which may comprise large overshoot in some instances. This may be avoided using the following velocity PID equation EQ2:
q(n)−q(n−1)  (EQ2)
where:

q(n) is given by EQ1. Upon calculating q(n)−q(n−1) using EQ1, we arrive at EQ3.

FIG. 2Bis a logical flowchart illustrating a method205for optimizing performance of the PCD100and while mitigating thermal generation within the PCD100.FIG. 2Btracks the operations presented inFIG. 2Abut in a more traditional, linear flow chart format.

Block305is the first block of the method205. In block305, the present temperature of a component within the PCD100is detected with a temperature sensor157. As noted above, the dual PID loop controller205may be assigned to a single component, such as a CPU110or GPU189. In other exemplary embodiments, a dual PID loop controller205may manage/control a plurality of components. In the embodiments in which a single component, like a CPU110is being managed by the dual PID loop controller205, the temperature monitored in block305may be the temperature of the single component.

Next, block310, a parameter associated with the temperature, such as frequency, may be monitored for the component of interest such as a CPU110. According to one exemplary embodiment, the parameter may comprise clock frequency. However, as noted above, other adjustable parameters associated with temperature may include transmission power of the RF transceiver168which includes a modem; data rate or flow rates of the processor126; as well as other parameters of the PCD100which may mitigate thermal generation and that may also impact operating performance of the PCD100.

Subsequently, in decision block315, the dual PID loop controller205determines if the temperature of a component or component(s) of interest have exceeded a predetermined threshold value. This predetermined threshold value may be established at manufacture of the component. For example, the threshold temperature value of a CPU110may have magnitude of about 90.0 degrees C. If the inquiry to decision block315is positive, then the “YES” branch is followed to block320. If the inquiry to decision block315is negative, then the “NO” branch is followed to block340.

In block320, the PID controller221A of loop209compares the present measured temperature (sensed in block305) with the temperature setpoint218assigned to the component or components of interest. As noted previously inFIG. 2A, the temperature setpoint218may be a fixed value or it may change depending on one or more thermal mitigation algorithms which may be supported by the PCD100.

Next, in block325, the PID controller221A of loop209inFIG. 2A, may calculate an error value (see Te1ofFIG. 2A) based on the comparison between the temperature setpoint218and the present temperature provided by a sensor157. In block330, the PID controller221A of loop209may then determine an ideal operating frequency for the CPU110(the component of interest) based on the error values and equations EQ1 through EQ3.

Once the ideal operating frequency is calculated in block330, then in block335, the PID controller221A of loop209may set the component of interest, such as the CPU110, to the desired operating frequency which minimizes thermal generation by the component of interest which is the CPU110in this example. The method205then returns.

If the inquiry to decision block315is negative, then the “NO” branch is followed to block340in which the PID controller221B of lower loop212compares the present value of the adjustable parameter224, such as frequency which may be the present clock frequency, with maximum frequency227available for the component or components of interest. As noted above, the maximum frequency227may be set or it may be dynamic (changeable) depending on thermal mitigation algorithms which may be running in parallel with method205.

Next, in block345, the PID controller221B of loop212may calculate error value(s) based on the comparison in block340. Subsequently, the method continues to block335where the second PID controller221B issues commands to the CPU110to adjust its operating frequency to the calculated ideal operating frequency. The method205then returns.

As noted previously, the dual PID loop controller205is not limited to the adjustable parameter of frequency. Other adjustable parameters include, but are not limited to, transmission power of the RF transceiver168which includes a modem; data rate or flow rates of the processor126; as well as other parameters of the PCD100which may mitigate thermal generation and that may also impact operating performance of the PCD100.

Referring now toFIG. 3, this figure is a functional block diagram of a generic dual PID loop controller205′ for any component within the PCD100ofFIG. 1. In this exemplary embodiment, the dual PID loop controller205′ has a first loop209′ and a second loop212′ which are coupled together by a threshold condition206′. In the earlier example, the threshold condition206′ may comprise temperature of a component or a plurality of components301controlled by the dual PID loop controller205′.

Both the first loop209′ and second loop212′ may control as output an adjustable parameter235′, such as, but not limited to, an operating frequency. That adjustable parameter235′ is fed into a single component301or a plurality of components301.

In the exemplary embodiment illustrated inFIG. 3, the first loop209′ of the dual PID loop controller205′ may comprise software, hardware, and/or firmware. Similarly, the second loop212′ of the dual PID loop controller205′ may comprise software, hardware, and/or firmware. Each loop209,212may comprise a different structure which means that one loop may comprise software while the second loop comprises hardware, or vice-versa. In other embodiments, each loop209,212may comprise the same structure, i.e. hardware-hardware, software-software, etc.

For some conditions, hardware embodiments of both loops209,212may be the most practical design. For example, response times usually must be minimal to detect and to respond to electrical current limitations (“CLs”). For these conditions, both loops209,212may comprise hardware. Exemplary hardware includes, but is not limited to, First-In/First-Out (FIFOs) type devices.

Meanwhile, component301may comprise a single component such as a CPU110, a GPU189, an analog signal processor126, a digital signal processor, and other similar/like processing entities as understood by one of ordinary skill in the art. The component301may also comprise a plurality of devices in some exemplary embodiments instead of a device/component.

FIG. 4is a functional block diagram of nested dual PID loop controllers205A,205B,205C that may be present within the PCD ofFIG. 1. This diagram illustrates how multiple dual PID loop controllers205A,205B,205C may be coupled to individual components301A.

For example, a first component301A may be controlled by dual (two) PID loop controllers205A,205B. Similarly, a second component301B may be controlled by dual (two) PID loop controllers205A,205C. Other ways of nesting/grouping dual PID loop controllers205A are possible and are included within the scope of this disclosure.

The dual PID loop controller205may maximize performance and reliability: reliability may be maintained by keeping an operating temperature below a setpoint, while performance may be achieved by allowing for a higher operational value once temperature is maintained below desired value. The dual PID controller205provides a flexible design where the algorithm design may be extended to any component in a PCD100—by just varying the controlled and adjustable parameter, such as frequency.

The dual PID loop controller is adaptable: each of the PID loops209,212may be tuned independently to achieve the level of aggressiveness desired in the control of the component301. Dual PID loop controllers205offer stable operation in most operating conditions. The algorithm of the dual PID loop controllers205may achieve quicker convergence to desired temperatures and operational levels compared to single loop control of the conventional art.

Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may performed before, after, or parallel (substantially simultaneously with) other steps without departing from the scope and spirit of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as “thereafter”, “then”, “next”, etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.

Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.

Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.

In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium.

In the context of this document, a computer-readable medium is an electronic, magnetic, optical, or other physical device or means that may contain or store a computer program and data for use by or in connection with a computer-related system or method. The various logic elements and data stores may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” may include any means that may store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise any optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Disk and disc, as used herein, includes compact disc (“CD”), laser disc, optical disc, digital versatile disc (“DVD”), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.