Semiconductor device and method of manufacturing the same

Provided is a semiconductor device that includes a vertical MOS transistor having a trench structure capable of enhancing a driving performance of the vertical MOS transistor. A thick oxide film is formed next to a gate electrode led out of a trench of the vertical MOS transistor having the trench structure, and is removed to form a stepped portion which has a face lower than a surrounding plane and has slopes as well. This makes it possible to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer, thereby solving a problem of no current flow in a part of a driver element and enhancing the driving performance of the vertical MOS transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a vertical MOS transistor with a trench structure and a method of manufacturing the semiconductor device.

2. Description of the Related Art

In recent years, power supply ICs represented by voltage regulators and voltage detectors tend to be smaller in chip size and larger in output current to keep up with the size reduction and diversification of portable devices to which the power supply ICs are mounted. Since a driver element for driving a current occupies the chip area most within elements constituting a power supply IC, MOS transistors having a trench structure have been employed so far in an attempt to enhance the driving performance of the driver element through reduction in area and increase in the effective channel width.

Up to now, semiconductor devices having a trench structure and methods of manufacturing the semiconductor devices have been introduced in, for example, JP 10-32331 A and JP 2008-34794 A.

A conventional method of manufacturing a vertical MOS transistor having a trench structure is described with reference toFIGS. 4A to 5D.FIGS. 4A to 5Dare schematic sectional views illustrating step by step the flow of the manufacturing method.

First, as illustrated inFIG. 4A, a first conductivity type well diffusion layer22(called a body) is formed on a second conductivity type embedded layer21. A thermally oxidized film23, a deposited oxide film24, and a resist film25are stacked on a surface of the body and are partially etched away.

Next, as illustrated inFIG. 4B, the resist film25is removed and then a hard mask which is a laminate of the patterned thermally oxidized film23and deposited oxide film24is used to form a trench26by etching. Subsequently, as illustrated inFIG. 4C, the thermally oxidized film23and the deposited oxide film24which have been used as the hard mask are removed and then a sacrificial oxide film27is formed by thermal oxidation in order to improve the shape of the trench26.

Thereafter, as illustrated inFIG. 4D, removing the sacrificial oxide film27, a gate insulating film28is formed by thermal oxidation, and a doped polycrystalline silicon film29which contains impurities formed by deposition.

Next, as illustrated inFIG. 5A, a resist film31is used in patterning and a gate electrode30is obtained by over-etching the doped polycrystalline silicon film29.

Thereafter, as illustrated inFIG. 5B, a resist film32is patterned and the exposed surface is doped with second conductivity type impurities in order to form a source region. Subsequently, as illustrated inFIG. 5C, a resist film33is newly patterned and the exposed surface is doped with first conductivity type impurities in order to form a substrate-potential region.

Thereafter, as illustrated inFIG. 5D, a second conductivity type heavily doped source diffusion layer34and a first conductivity type heavily doped substrate-potential diffusion layer35are formed by heat treatment. An interlayer insulating film36is subsequently formed by deposition, and then contact holes37are formed to establish electrical connection to the gate electrode30, the second conductivity type heavily doped source diffusion layer34, and the first conductivity type heavily doped substrate-potential diffusion layer35. Plugs made of tungsten or the like are then embedded to form source substrate-potential wiring39and gate-potential wiring38.

An element structure that has the trench26formed in the first conductivity type well diffusion layer22is thus formed as a vertical MOS transistor having a trench structure which operates in the vertical direction.

However, the conventional semiconductor device manufacturing method described above has a problem in that, when the contact holes are provided in the gate electrode led out of the trench of the vertical MOS transistor having a trench structure, a current does not flow in a part of the element because a heavily doped diffusion layer is not formed in the substrate right under the gate electrode.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above, and an object of the present invention is therefore to provide a method of manufacturing a semiconductor device capable of solving the problem of no current flow in a part of a driver element and enhancing the driving performance of the driver element even more by: forming a thick oxide film next to a gate electrode that is led out of a trench of a vertical MOS transistor having a trench structure; removing the thick oxide film to form a stepped portion which has a face lower than a surrounding plane and has slopes as well; and utilizing the stepped portion to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer.

In order to solve the above-mentioned problem, a semiconductor device and a method of manufacturing the semiconductor device according to the present invention are structured as follows.

(1) There is provided a semiconductor device that includes a vertical MOS transistor including: a semiconductor substrate in which a first conductivity type well diffusion layer is formed in a part of a first conductivity type epitaxial layer having a second conductivity type embedded layer in a first conductivity type semiconductor substrate; a trench structure obtained by embedding a gate electrode in a trench with a gate insulating film interposed between the trench and the gate electrode, the trench being formed to a depth that reaches the second conductivity type embedded layer from a surface of the substrate; a second conductivity type heavily doped source diffusion layer and a first conductivity type substrate-potential diffusion layer which are formed above island-like regions, the island-like regions being other regions of the first conductivity type well diffusion layer than the trench structure; contact holes and wiring provided on an exposed surface portion to lead the gate electrode out of the trench structure via the gate insulating film and to thereby establish electrical connection; and wiring that is in contact in common with the second conductivity type heavily doped source diffusion layer and the first conductivity type substrate-potential diffusion layer which are formed on the island-like regions, to thereby operate with side surfaces of the trench structure as channels, and in the semiconductor device, a second conductivity type heavily doped source diffusion layer is formed right under the gate electrode by forming a thick oxide film next to the gate electrode led out of the trench, then removing the thick oxide film, and thus forming a stepped portion which is lower than a surrounding plane and which has slopes.

(2) There is provided a method of manufacturing the semiconductor device, including forming the thick oxide film which is an embedded oxide film by Shallow Trench Isolation (STI).

(3) There is provided a method of manufacturing the semiconductor device, including forming the second conductivity type heavily doped source diffusion layer that is formed right under the gate electrode by one of spin implantation and step implantation.

(4) In the semiconductor device, the trench structure in the first conductivity type well diffusion layer forms one of a lattice pattern and a stripe pattern.

As described above, according to the present invention, a thick oxide film is formed next to a gate electrode led out of a trench of a vertical MOS transistor having a trench structure, and is removed to form a stepped portion which has a face lower than a surrounding plane and has slopes as well. This makes it possible to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer, thereby solving the problem of no current flow in a part of a driver element and enhancing the driving performance of the driver element. The semiconductor device and the semiconductor device manufacturing method that are provided by the present invention are also capable of eliminating the fear of an increase in gate electrode impedance in AC operation which is caused by a width reduction of a part of the gate electrode when the heavily-doped source diffusion layer is to be formed right under the gate electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention is described below with reference to the drawings.FIGS. 1A to 2Dare schematic sectional views illustrating a flow of a semiconductor device manufacturing method according to the embodiment of the present invention. The schematic sectional views illustrating the flow are sectional views taken along the line B-B′ ofFIG. 3B, which is a plan view of an element obtained by the semiconductor device manufacturing method of the present invention.

FIG. 1Aillustrates a substrate after forming of a hard mask for trench etching has been finished. The substrate includes a first conductivity type semiconductor substrate51which is, for example, a P-type semiconductor substrate doped with boron at an impurity concentration that gives the semiconductor substrate a resistivity of 20 Ωcm to 30 Ωcm. As a second conductivity type embedded layer1, an N-type embedded layer in which impurities such as arsenic, phosphorus, or antimony are diffused at a concentration of, for example, approximately 1×1016atoms/cm3to 1×1018atoms/cm3is selectively formed in the first conductivity type semiconductor substrate51. A first conductivity type epitaxial layer52is also grown on the first conductivity type semiconductor substrate51to a thickness of, for example, several μm to several tens μm. In a region of the substrate where a trench structure is to be formed later, a first conductivity type well diffusion layer2(called a body) is formed by ion implantation of impurities such as boron or boron difluoride at a dose of, for example, 1×1012atoms/cm2to 1×1013atoms/cm2. In the case where the second conductivity type embedded layer1is a P-type embedded layer, for example, the embedded layer is doped with boron or similar impurities to the concentration given above. What conductivity types the semiconductor substrate51, the embedded layer1, and the epitaxial layer52have are irrelevant to the essence of the present invention. The semiconductor substrate51and the epitaxial layer52are omitted fromFIGS. 1B to 2D.

A thick oxide film3, which is one of the characteristics of the present invention, is provided in a part of a surface of the first conductivity type well diffusion layer2in the region where the trench structure is to be formed later. The thick oxide film3is, for example, such an embedded oxide film as the one used in Shallow Trench Isolation (STI) for element isolation which has a thickness of several hundreds nm. In order to form the hard mask for trench etching, a thermally oxidized film4having a thickness of, for example, several tens nm to several hundreds nm and a deposited oxide film5having a thickness of, for example, several hundreds nm to 1 μm are stacked on a surface of the first conductivity type well diffusion layer2, and are selectively removed by etching with a resist film6as a pattern to form openings. The hard mask may have a single-layer structure constituted of a thermally oxidized film or a deposited oxide film if the single-layer structure withstands satisfactorily against the subsequent trench etching. As the hard mask, a resist film or a nitride film can also be used without a problem.

Next, as illustrated inFIG. 1B, the resist film6is removed and a trench7is formed by etching with the use of the hard mask which is a laminate of the patterned thermally oxidized film4and deposited oxide film5. The trench7is preferably deep enough to reach the second conductivity type embedded layer1. The trench7and other trenches7together form a lattice pattern or a stripe pattern in plan view as illustrated inFIGS. 3B and 3C. Accordingly, regions where no trenches are formed are island-like regions in plan view which are isolated like islands, and are surrounded by trenches.

Subsequently, as illustrated inFIG. 1C, the thermally oxidized film4and the deposited oxide film5which have been used as the hard mask are removed, and then a sacrificial oxide film8is formed by thermal oxidation to a thickness of, for example, several nm to several tens nm in order to improve the shape of the trench7. Thereafter, as illustrated inFIG. 1D, the sacrificial oxide film8is removed and the thick oxide film3is simultaneously removed. The region from which the thick oxide film3has been removed, which is one of the characteristics of the present invention, is now a stepped portion which is lower than the surrounding plane and which has slopes. A gate insulating film9, for example, a thermally oxidized film having a thickness of several hundreds Å to several thousands Å is subsequently formed. A doped polycrystalline silicon film10is then formed by deposition to a thickness of, preferably, 100 nm to 500 nm, filling the trench7with the polycrystalline silicon film10. The conductivity type of the doped polycrystalline silicon film10can be the first conductivity type or the second conductivity type.

Next, as illustrated inFIG. 2A, a resist film12is used in patterning and the doped polycrystalline silicon film10is over-etched to obtain a gate electrode11. The patterning in this step is performed in a manner that the gate electrode11does not cover the region from which the thick oxide film3has been removed, which is one of the characteristics of the present invention, and in a manner that an edge of the gate electrode11positions at an edge of the thick oxide film3. The following description is given with reference toFIGS. 3A to 3C, too, which are plan views of elements.FIGS. 3A,3B, and3C each illustrate a vertical MOS transistor having a trench structure which is a basic cell integrated on the order of at least several hundreds to several thousands in a chip.

InFIGS. 3A,3B, and3C, a reference symbol C represents a contact hole for establishing electrical connection to the gate electrode11.FIG. 3Aillustrates a manufacturing method in which a second conductivity type heavily doped source diffusion layer15to be formed later in a manner indicated by a reference symbol D ofFIG. 3Ais formed by patterning the gate electrode11in a manner that makes the gate electrode narrow in a portion A ofFIG. 3A. This method solves the problem of no current flow in a part of the element fairly well, but does not remove the fear of characteristics deterioration in AC operation due to an increase in gate electrode impedance. If the gate electrode11is widened in the portion A in order to lower the impedance, the second conductivity type heavily doped source region15is not formed right under the portion A of the gate electrode11and, consequently, a current does not flow in a part of the element.

In a semiconductor device of the present invention which is illustrated in the plan views ofFIGS. 3B and 3C, on the other hand, the stepped portion which is created by the removal of the thick oxide film3and which has a face lower than the surrounding plane and has slopes as well is formed next to the gate electrode11. This makes it possible to form the second conductivity type heavily doped source diffusion layer15right under the gate electrode11, and solves the problem of no current in a part of the element, thereby enhancing the driving performance of the driver element without the need to reduce the width of a part of the gate electrode11.

Thereafter, as illustrated inFIG. 2B, a resist film13is patterned and the exposed surface is doped with second conductivity type impurities to form a source region. The doping uses ion implantation. As illustrated inFIG. 6, the ion implantation is accomplished through spin implantation or step implantation by slanting the semiconductor substrate with respect to ions being implanted, and ions are thus implanted below the gate electrode11from the stepped portion formed by the removal of the thick oxide film3, which is one of the characteristics of the present invention, and having a face lower than the surrounding plane and having slopes as well.

As illustrated inFIG. 2C, after the resist film13is removed, a resist film14is newly patterned and the exposed surface is doped with first conductivity type impurities to form a substrate-potential region. The doping uses ion implantation. In the ion implantation ofFIGS. 2B and 2C, ions of, for example, arsenic or phosphorus are implanted preferably at a dose of 1×1015atoms/cm2to 1×1016atoms/cm2when the conductivity type of the surface on which the ion implantation is to be performed is the N-type. When the conductivity type of the surface on which the ion implantation is to be performed is the P-type, ions of boron or boron difluoride are implanted preferably at a dose of 1×1015atoms/cm2to 1×1016atoms/cm2.

The doping of the source region and the substrate-potential region with impurities can be performed at the same time and under the same conditions as in the forming of MOS transistors in the same chip that do not have the trench7.

Thereafter, as illustrated inFIG. 2D, heat treatment is performed at 800° C. to 1,000° C. for several hours to form the second conductivity type heavily doped source diffusion layer15right under the gate electrode11. A first conductivity type heavily doped substrate-potential diffusion layer16is also formed in the same manner as the heat treatment described above. An element structure that has the trench7formed in the first conductivity type well diffusion layer2is thus formed as a vertical MOS transistor having a trench structure which operates in the vertical direction.

Subsequently, an interlayer insulating film17having a thickness of, for example, several hundreds nm to 1 μm is laid on top and then contact holes18are formed to establish electrical connection to the gate electrode11, the second conductivity type heavily doped source diffusion layer15, and the first conductivity type heavily doped substrate-potential diffusion layer16. Plugs made of tungsten or the like are then embedded to form source substrate-potential wiring19and gate-potential wiring20.

In the manner described above, a thick oxide film formed next to a gate electrode led out of a trench is removed to form a stepped portion which is a characteristic of the present invention and which has a face lower than the surrounding plane and has slopes as well. The stepped portion makes it possible to form a heavily doped source diffusion layer right under the gate electrode by ion implantation. A semiconductor device and semiconductor device manufacturing method according to the present invention are thus capable of solving the problem of no current in a part of a driver element and enhancing the driving performance of the driver element.