Dynamic alignment by electrical potential and flow control to single-wall carbon nanotube field effect transistors

After forming a plurality of metal anchors arranged in a matrix of rows and columns and a plurality trenches separating adjacent rows of metal anchors on a substrate, a dispersion comprising charged single-wall carbon nanotubes (SWCNTs) having a surface binding group on each end of the charged SWCNTs is directed to flow through the plurality of trenches. During the flow process, one end of each of the charged SWCNTs binds to a corresponding metal anchor through a surface binding group. An electric field is then applied to align the charged SWCNTs parallel to lengthwise directions of the plurality of trenches such that another end of the each of the SWCNTs binds to an adjacent metal anchor through another surface binding group. The aligned charged SWCNTs can be used as conducting channels for field effect transistors (FETs).

BACKGROUND

The present application relates to semiconductor device fabrication, and more particularly, to a method of dynamically aligning single-wall carbon nanotubes for fabricating carbon nanotube field effect transistors.

The use of single-wall carbon nanotubes (SWCNTs) as conducting channels for field effect transistors (FETs) has been extensively studied in recent years. SWCNT FETs offer many advantage over conventional silicon-based FETs since the one-dimensional structure of the SWCNTs allows the SWCNT based FETs to be aggressively scaled without incurring deleterious short-channel effects that hinder modern scaled devices.

In SWCNT FETs, the alignment of SWCNTs is a fundamental requirement to ensure their excellent functions. Individual SWCNTs have been aligned and positioned between a source electrode and a drain electrode using atomic force microscope (AFM). However, this approach is often inefficient and tedious. Therefore, there remains a need to develop an effective method to align and position SWCNTs in a massive scale for device applications.

SUMMARY

The present application provides a method for dynamically aligning single-wall carbon nanotubes (SWCNTs) for fabricating field effect transistors. After forming a plurality of metal anchors arranged in a matrix of rows and columns and a plurality trenches separating adjacent rows of metal anchors on a substrate, a dispersion comprising charged SWCNTs having a surface binding group on each end of the charged SWCNTs is directed to flow through the plurality of trenches. During the flow process, one end of each of the charged SWCNTs binds to a corresponding metal anchor through a surface binding group. An electric field is then applied to align the charged SWCNTs parallel to lengthwise directions of the plurality of trenches such that another end of the each of the SWCNTs binds to an adjacent metal anchor through another surface binding group. The aligned charged SWCNTs can be used as conducting channels for field effect transistors (FETs).

In one aspect of the present application, a method of forming a semiconductor structure is provided. The method of forming a semiconductor structure includes first forming a plurality of metal anchors and a plurality of trenches on a substrate. The plurality of metal anchors are arranged in a matrix of rows and columns such that the metal anchors in each row are arranged in a corresponding trench along a lengthwise direction of the corresponding trench. A dispersion comprising a plurality of charged single-wall carbon nanotubes (SWCNTs) having a surface binding group on each end of the plurality of charged SWCNTs is then directed through the plurality of trenches, during which one end of each of the plurality of charged SWCNTs binds to a corresponding metal anchor. Next, the plurality of charged SWCNTs is subjected to an electric field. The electric field aligns the plurality of charged SWCNTs parallel to lengthwise directions of the plurality of trenches such that another end of each of the plurality of charged SWCNTs binds to a metal anchor adjacent to the corresponding metal anchor.

DETAILED DESCRIPTION

Referring toFIGS. 1A and 1B, there is illustrated an exemplary semiconductor structure in accordance with one embodiment of the present application which includes a plurality of metal anchors16and a plurality of trenches18formed on a substrate.

In one embodiment and as shown inFIG. 1B, the substrate includes a base substrate12and a first insulating layer14formed on the base substrate12. The base substrate12may be composed of any suitable semiconductor material, such as, for example, Si, Ge, SiGe, SiC, SiGeC, and III/V compound semiconductors including InAs, GaAs, and InP. In one embodiment, the base substrate12is comprised of Si. The base substrate12provides mechanical support for the rest of the components in the semiconductor structure. The thickness of the base substrate12can be from 400 μm to 1,000 with a thickness from 50 μm to 900 μm being more typical.

The first insulating layer14may include any electrically insulating material. In one embodiment, the first insulating layer14includes a dielectric oxide such as for example, silicon oxide, hafnium oxide and aluminum oxide.

The metal anchors16can be formed by first depositing a metal layer (not shown) over the first insulating layer14by a conventional deposition technique including, but not limited to, a chemical vapor deposition (CVD), sputtering, and physical vapor deposition (PVD). The metal layer that is formed can have a thickness ranging from 10 nm to 100 nm, although lesser and greater thicknesses can also be employed. The metal layer may include any metal that can guide the alignment of the charged SWCNTs of the present application. Exemplary metals that can be employed as the metal layer include, but are not limited to gold, silver, copper, chromium, aluminum, titanium, tungsten, and platinum.

The metal layer can be subsequently patterned to form the metal anchors16by lithography and etching processes. The lithographic step includes applying a photoresist (not shown) on the metal layer, exposing the photoresist to a desired pattern of radiation, and developing the exposed photoresist utilizing a conventional resist developer. The etching process comprises dry etch and/or wet chemical etch. Suitable dry etching processes that can be used in the present application include reactive ion etch (RIE), ion beam etching, plasma etching or laser ablation. Typically, a RIE process is used. The etching process transfers the pattern from the patterned photoresist to the metal layer utilizing the insulating layer14as an etch stop. After transferring the pattern into the metal layer, the residual photoresist can be removed utilizing a conventional resist stripping process such as, for example, ashing. The metal layer is patterned into a matrix of rows and columns for aligning the charged SWCNTs of the present application. In one embodiment, the metal layer is patterned as dots. Adjacent metal anchors in each row may be separated by a pitch ranging from 50 nm to 200 nm, which corresponds to a length of each of the charged SWCNTs.

A second insulating layer (not shown) is then deposited over the first insulating layer14and the metal anchors16by a conventional deposition process such as, for example, CVD, PVD or spin coating. The material of the second insulating layer can be, for example, a dielectric material or a non-conductive polymer. In some embodiments, the second insulating layer may include a same dielectric material as the first insulating layer14. In other embodiments, the second insulating layer may include a different dielectric material from that used in providing the first insulating layer14. In one embodiment, the second insulating layer is composed of silicon oxide. The thickness of the second insulating layer can be from 5 nm to 10 nm, although lesser and greater thicknesses can be employed. The second insulating layer is then patterned, for example, using conventional lithography and dry etching processes to define a plurality of trenches18in the second insulating layer. The plurality of trenches18separate the adjacent rows of the metal anchors16from each other so that the metal anchors16in each row are confined in a corresponding trench18along a lengthwise direction of the trench18. The trenches18expose metal anchors16for directing the assembly of the SWCNTs. In one embodiment, the trenches18may be formed as parallel strip-shaped trenches. Specifically, the second insulating layer can be patterned by first applying a photoresist (not shown) on the second insulating layer, exposing the photoresist to a pattern of radiation, and then developing the pattern into photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, an etch step is performed to transfer the pattern from the patterned photoresist into the second insulating layer by, for example, RIE using the first insulating layer14as an etch stop. The width of the trenches18is configured such that a dispersion of the charged SWCNTs of the present application can be directed to flow through the trenches18. In one embodiment, the width of the trenches18can be from 5 nm to 20 nm. Remaining portions of the second insulating layer that border the trenches18are herein referred to as guiding structures20.

Referring toFIGS. 2A-2B, a passivation layer22is formed on exposed surfaces of the first insulating layer14and the guiding structures20to prevent the absorption of the charged SWCNTs on theses undesired surfaces. Exemplary passivation agents that can be used in the passivation layer22include, but are not limited to, poly(ethylene glycol) (PEG) and PEG containing surfactants. The passivation layer22can be formed by depositing the passivation agent on the first insulating layer14and the guiding structures20by a coating process, such as, for example, spin coating, spray coating, or screen printing. The passivation layer22that is formed generally has a thickness ranging from 3 nm to 10 nm.

Referring toFIGS. 3A-3B, a dispersion24containing charged SWCNTs26having charged moieties (R1) on sidewalls of the SWCNTs and surface binding groups (R2) at opposite ends of the SWCNTs is directed to flow through the trenches18. The charged moieties can be either positively charged or negatively charged. Exemplary charged moieties (R1) that can be employed to functionalize the pristine SWCNTs include, but are not limited to, proteins, lipids, and DNA molecules. In one embedment, the charged moiety (R1) is a negatively charged poly(T) strand DNA. The surface binding groups (R2) may include any functional group that shows a high affinity to the metal anchors16to promote the self-assembly of the charged SWCNTs26on the metal anchors16. Exemplary surface binding groups (R2) include, but are not limited to, thiol (—SH) and isontrile (—NC).

A specific example of functionalizing a pristine SWCNT to form a negatively charged SWCNT26with thiol groups at opposite ends of the negatively charged SWCNT is shown inFIG. 4. The pristine SWCNT is first carboxylated by an acid treatment using a H2SO4—HNO3solution. The carboxyl-functionalized SWCNT is then reacted with DNA molecules and thiol groups sequentially to covalently link the DNA molecules to sidewalls of the SWCNT and the thiol groups to opposite ends of the SWCNT.

Referring toFIGS. 5A-5B, during the directed flow of the dispersion24, the strong specific binding between the surface binding groups (R2) and the metal anchors16binds one end of the charged SWCNTs26to the metal anchors16on the substrate. The charge on the charged SWCNTs26keeps a sufficient distance between any two charged SWCNTs26in the dispersion24. Thus, each metal anchor16can only connect to a single charged SWCNT26.

Referring toFIGS. 6A-6B, after one end of each of the charged SWCNTs26is attached to a corresponding metal anchor16, an alternating current (AC) electric filed is applied between the base substrate12and the SWCNT dispersion24, which is also grounded. AC electrical field alternatively attracts the charged SWCNTs26toward or repel them away from the base substrate12to facilitate the horizontal alignment of the charged SWCNTs26along lengthwise directions of the trenches18. During this electrical field modulation process, the surface binding group (R2) at another end of each of the charged SWCNTs26binds to another metal anchor16adjacent to the corresponding metal anchor16. In one embodiment and when the charged SWCNTs26are functionalized with a negatively-charged DNA molecule, DNA-functionalized SWCNTs are aligned and connected between two adjacent metal anchors during positive potential interval. After the alignment of the charged SWCNTs26, those charged SWCNTs26that are not bound to the metal anchors16can then be washed off from the substrate. The passivation layer22is then removed by rinsing with a dilute carboxylic acid aqueous solution to re-expose the first insulating layer14and the guiding structures20.

Referring toFIGS. 7A-7B, an interlevel dielectric (ILD) layer28L is formed over the substrate covering the exposed surfaces of the first insulating layer14, the metal anchors16and the charged SWCNTs26to fill the trenches18. The ILD layer28L includes a dielectric material that may be easily planarized. For example, the ILD layer28L can be a doped silicate glass, an undoped silicate glass (silicon oxide), an organosilicate glass (OSG), or a porous dielectric material. The ILD layer28L can be formed by CVD, PVD or spin coating. The thickness of the ILD layer28can be selected so that an entirety of the top surface of the ILD layer28L is formed above top surfaces of the guiding structures20. The ILD layer28L can be subsequently planarized, for example, by CMP and/or a recess etch using the guiding structures20as an etch stop. After the planarization, the ILD layer28L has a topmost surface coplanar with the topmost surfaces of the guiding structures20.

Referring toFIGS. 8A-8B, first openings30are formed through the ILD layer28L to expose metal anchors16and portions of the charged SWCNTs26adjacent to the metal anchors16. The first openings30can be forming by lithography and etching. The lithographic process includes forming a photoresist layer (not shown) on the top surface of the ILD layer28L, exposing the photoresist layer to a desired pattern of radiation and developing the exposed photoresist layer utilizing a conventional resist developer. The etching process includes a dry etch, such as, for example, RIE or a wet chemical etch that selectively removes exposed portions of the ILD layer. After etching, the remaining portions of the photoresist layer can be removed by a conventional resist striping process, such as, for example, ashing. Remaining portions of the ILD layer28L are herein referred to as the ILD layer portion28.

Referring toFIGS. 9A-9B, the metal anchors16and portions of the charged SWCNTs26exposed in the first openings30are removed by, for example, RIE. Remaining portions of the charged SWCNTs26that are covered by the ILD layer portion28are intact.

Referring toFIGS. 10A-10B, the ILD layer portions28are patterned to provide second openings32by standard lithography and etching processes described above with respect to forming the first openings30. The second openings32expose portions of the remaining portions of the charged SWCNTs26. The remaining portions of the charged SWCNTs26are herein referred to as functional SWCNT portions26A. Remaining portions of the ILD layer portions28are herein referred to as patterned ILD layer portions28A.

Referring toFIGS. 11A-11B, first gate structures34are formed in the first openings30and second gate structures36are formed in the second openings32. Because the second gate structures36are formed over the exposed portions of the functional SWCNT portions26A, the second gate structures36serve as functional gate structures. The term “functional gate structure” as used herein denotes a gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields. Each of the first and the second gate structures34,36includes, from bottom to top, a gate dielectric38and a gate electrode40. The first and the second gate structures34,36can be formed by first depositing a conformal gate dielectric layer (not shown) on bottom surfaces and sidewalls of the first gate openings30, bottom surfaces and sidewalls of the second gate openings32, and the top surface of the patterned ILD layer portion28A. The gate dielectric layer can be a high dielectric constant (high-k) material layer having a dielectric constant greater than 8.0. Exemplary high-k materials include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In one embodiment, the gate dielectric layer is composed of hafnium oxide (HfO2). The gate dielectric layer can be formed by a conventional deposition process, including but not limited to, CVD, PVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), ion beam deposition, electron beam deposition, and laser assisted deposition. The gate dielectric layer that is formed may have a thickness ranging from 0.9 nm to 6 nm, with a thickness ranging from 1.0 nm to 3 nm being more typical. The gate dielectric layer may have an effective oxide thickness on the order of or less than 1 nm.

Remaining volumes of the first openings30and the second openings32are then filled with a gate electrode layer (not shown). The gate electrode layer can include any conductive material, such as, for example, polycrystalline silicon, polycrystalline silicon germanium, an elemental metal, (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide) and multilayered combinations thereof. In one embodiment, the gate electrode layer is comprised of polycrystalline silicon.

The gate electrode layer can be formed utilizing a conventional deposition process including, for example, CVD, plasma enhanced chemical vapor deposition (PECVD), evaporation, PVD, sputtering, chemical solution deposition and ALD. When silicon-containing materials are used as the gate electrode layer, the silicon-containing materials can be doped with an appropriate impurity by utilizing either an in-situ doping deposition process or by utilizing deposition, followed by a step such as ion implantation or gas phase doping in which the appropriate impurity is introduced into the silicon-containing material. Portions of the gate electrode layer and the gate dielectric layer that are formed above the top surface of the patterned ILD layer portion28A can be removed, for example, by CMP. The remaining portions of the gate dielectric layer constitute gate dielectric38and the remaining portions of the gate electrode layer constitute gate electrode40.

Referring toFIGS. 12A-12B, a contact-level dielectric layer42is deposited over the patterned ILD layer portions28A, the first gate structures34and the second gate structures36. The contact-level dielectric layer42can include a dielectric material such as undoped silicon oxide, doped silicon oxide, porous or non-porous organosilicate glass, porous or non-porous nitrogen-doped organosilicate glass, or a combination thereof. In some embodiments, the contact-level dielectric layer42may include a same dielectric material as the ILD layer28L. In other embodiments, the contact-level dielectric layer42may include a different dielectric material from that used in providing the ILD layer28L. The contact-level dielectric layer42can be formed by CVD, PVD or spin coating. If the contact-level dielectric layer42is not self-planarizing, the top surface of the contact-level dielectric layer42can be planarized, for example, by CMP.

Various contact structures including gate contact structures44in contact with the first gate structures34and the second gate structures36, and source/drain contact structures46in contact with portions of the functional SWCNT portions26A on opposite sides of each of the second gate structures36are formed. Various contact structures (44,46) can be formed, for example, by forming gate contact openings (not shown) and source/drain contact openings (not shown) through the contact-level dielectric layer42using a combination of lithographic patterning and an anisotropic etch. The gate contact openings expose portions of gate electrode40. The source/drain contact openings expose portions of the functional SWCNT portions26A on opposite sides of each of the second gate structures36. The gate contact openings and the source/drain contact openings are then filled with a conductive material using a conventional deposition process, such as, for example, CVD, PVD, ALD, or plating. Exemplary conductive materials include, but are not limited to, Cu, Al, W, Ti, Ta or their alloys. Excess portions of the conductive material above the contact-level dielectric layer42can be subsequently removed, for example, by a recess etch or CMP.