SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a plurality of first electrode layers stacked; a second electrode layer provided on the first electrode layers; a third electrode layer arranged with the second electrode layers on the first electrode layers; a first insulating layer including a first layer provided between the second electrode layer and the third electrode layer, a second layer provided between the second electrode layer and the first layer, and a third layer provided between the third electrode layer and the first layer; a plurality of semiconductor layers extending through the first electrode layers in a stacked direction thereof, and disposed in an arrayed arrangement; and a charge storage portion positioned between one of the first electrode layers and one of the semiconductor layers.

FIELD

Embodiments are generally related to a semiconductor memory device.

BACKGROUND

A non-volatile semiconductor memory device is under developing, which includes three-dimensionally disposed memory cells. For example, a NAND-type semiconductor memory device comprises a memory cell array that includes a plurality of control electrodes and a semiconductor channel extending through the plurality of electrodes. It may be necessary for such a semiconductor memory device to improve the breakdown voltage between the control electrodes in order to have the memory cells of higher density.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor memory device includes a plurality of first electrode layers stacked; a second electrode layer provided on the first electrode layers; a third electrode layer arranged with the second electrode layers on the first electrode layers; a first insulating layer including a first layer provided between the second electrode layer and the third electrode layer, a second layer provided between the second electrode layer and the first layer, and a third layer provided between the third electrode layer and the first layer; a plurality of semiconductor layers extending through the first electrode layers in a stacked direction thereof, and disposed in an arrayed arrangement; and a charge storage portion positioned between one of the first electrode layers and one of the semiconductor layers.

Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.

FIG. 1is a perspective view showing a semiconductor memory device1according to an embodiment. The semiconductor memory device1is, for example, a NAND-type non-volatile memory device, and includes the three dimensionally disposed memory cells.

As shown inFIG. 1, the semiconductor memory device1includes a conductive layer (hereinafter, a source layer10), a plurality of first electrode layers stacked (hereinafter, word lines20), a second electrode layer (hereinafter, a selection gate30a) and a third electrode layer (hereinafter, a selection gate30b). The selection gates30aand30bare disposed side by side on the word lines20that are stacked on the source layer10.

The source layer10is, for example, a P-type well provided in a silicon substrate (not shown). The source layer10may be a poly-crystalline silicon layer provided via an inter-layer insulating layer (not shown) on a silicon substrate (not shown). The word lines20, the selection gates30aand30bare, for example, metal layers that include tungsten (W).

Each of the word lines20has planar broadening, and stacked on a surface of the source layer10. Hereinafter, the stacked direction of the word lines20is defined as a first direction, for example, referred to as the Z-direction. An insulating layer13is provided between the word lines adjacent to each other in the Z-direction. The insulating layer13is, for example, a silicon oxide layer.

The selection gates30aand30bis, for example, arranged in the X-direction on the word lines20. The selection gates30aand30beach include a plurality of stacked layers disposed on the word lines20as shown in the figure. The insulating layer13is also provided respectively between the uppermost layer20aof the word lines20and the selection gate30a, between the uppermost layer20aand the selection gate30b, and between the stacked layers adjacent to each other in the Z-direction of the selection gate30aand30b. Hereinafter, the stacked layers are referred respectively to as a selection gate30aor30b.

The semiconductor memory device1further includes a first insulating layer (hereinafter, an insulating layer50) and a plurality of semiconductor layers60. The insulating layer50is provided between the selection gates30aand30b, and extends in the Y-direction. The plurality of semiconductor layers60extend in the Z-direction through the word lines20. The plurality of semiconductor layers60are electrically connected at bottom ends thereof to the source layer10.

The plurality of semiconductors60includes, for example, a plurality of first semiconductor layers (hereinafter, semiconductor layers60a) and a plurality of second semiconductor layers (herein after, semiconductor layers60b). The semiconductor layers60aextend respectively in the Z-direction through the selection gates30a. The semiconductor layers60bextend respectively in the Z-direction through the selection gates30b.

Hereinafter, the selection gates30aand30bare described as selection gates30except for the case where it is necessary to distinguish between the selection gates30aand30b. The semiconductor layers60aand60bare also described as semiconductor layers60in the same manner.

The semiconductor memory device1further includes, for example, a plurality of first interconnections (hereinafter, bit lines80) and a second interconnection (hereinafter, source line90) provided above the selection gates30. One of the semiconductor layers60aand one of the semiconductor layers60bare electrically connected to and share one of the bit lines80. The semiconductor layers60each are electrically connected the bit line80through a contact plug83. The source line90is electrically connected to the source layer10through a source contact body70. As shown inFIG. 1, the source contact body70extends in the Y-direction and the Z-direction along each lateral surface of word lines20and selection gates30.

It should be noted inFIG. 1that an insulating layer19provided between the selection gate30and the bit line80(seeFIG. 2A) and an insulating layer21provided between the source contact body70and each of the word lines20and the selection gate30(seeFIG. 3I) are omitted for showing a structure of the semiconductor memory device1.

FIGS. 2A and 2Bare schematic views showing a part of the semiconductor memory device1according to the embodiment.FIG. 2Ais the schematic view showing a part of cross-section taken along the X-Z plane.FIG. 2Bis the schematic view showing a cross-section taken along A-A line shown inFIG. 2A. Hereinafter, the structure of the semiconductor memory device1is precisely described with reference toFIGS. 2A and 2B.

The semiconductor memory device1includes memory holes MH extending in the Z-direction through the word lines20and the selection gate30. The memory holes MH each include a semiconductor layer60, an insulating layer63and a core body67. The insulating layer63is provided between an inner wall of a memory hole MH and the semiconductor layer60, and extends along the semiconductor layer60. The semiconductor layer60is positioned between the insulating layer63and the core body67. The core body67is provided so as to fill the inside of the memory hole MH.

The semiconductor layer60is provided in the memory hole MH extending through the selection gate30. Memory cells MC are provided at portions where the semiconductor layer60extends through the word lines20. The semiconductor layer60acts as a channel of each memory cell MC; and the word lines act as control gates of the memory cells.

The insulating layer63has, for example, an ONO structure, wherein a silicon oxide, a silicon nitride and a silicon oxide are stacked on the inner wall of the memory hole MH. The insulating layer63includes a portion positioned between a word line20and the semiconductor layer60, which acts as a charge storage portion of a memory cell MC.

A selection transistor STD is provided at a portion where the semiconductor layer60extends through the selection gate30. The semiconductor layer60acts as a channel of the selection transistor STD; and the selection gate30acts as a gate electrode of the selection transistor STD. A part of the insulating layer63positioned between the selection gate30and the semiconductor layer60acts as a gate insulating film.

As described above, the semiconductor memory device1comprises a plurality of NAND strings each including a plurality of memory cells MC and a selection transistor STD disposed along a semiconductor layer60. For example, increasing the density of memory cells MC by reducing the distance between the memory holes MH may be advantageous for enlarging the memory capacity of the semiconductor memory device. There may be a case, however, where the current leakage becomes larger due to lowering the breakdown voltage between the selection gates30aand30b, when a space between the selection gates30aand30bbecomes narrow in order to increase the density of memory holes MH.

In the embodiment, the insulating layer50is provided between the selection gates30aand30b. The insulating layer50includes, for example, a first layer51, a second layer53and a third layer55. The second layer53is provided between the selection gate30aand the first layer51. The third layer55is provided between the selection gate30band the first layer51. The first layer51is, for example, a silicon nitride layer. The second layer53and the third layer55are, for example, silicon oxide layers. Alternatively, the second layer53and the third layer55may be oxynitride layers.

The insulating layer50includes, for example, an interface between insulating layers different in the layer quality from each other on the current leakage pathway from the selection gate30ato the selection gate30b. Such an interface traps, for example, the charges moving from the selection gate30ato the selection gate30b, and thus, makes the potential barrier between the insulating layers become higher. Thereby, it is possible to suppress the current leakage flowing between the selection gates30aand30bby improving the breakdown voltage of the insulating layer50.

As shown inFIG. 2A, the semiconductor memory device1includes, for example, the selection gates30aand30bthat are provided on the uppermost layer20aof the word lines20. The semiconductor memory device1further includes a second insulating layer (hereinafter, an insulating layer13a) which is provided between the uppermost layer20aand the selection gate30a, and between the uppermost layer20aand the selection gate30b. The first layer51extends between a plurality of selection gates30aand a plurality of selection gates30b; and the bottom end of the insulating layer51is, for example, in contact with the insulating layer13a. Alternatively, the bottom end of the insulating layer50may be provided so as to divide the insulating layer13a.

FIG. 2Bis the schematic view showing an example of the arrangement of the memory holes MH provided in the semiconductor memory device1. For example, a memory hole MHD may be provided in addition to the memory holes MH extending through the selection gates30so as to divide the insulating layer50along the Y-direction. That is, it is preferable to maintain the periodicity of memory holes MH by providing the memory hole MHD, when reducing the distance between the memory holes MH, and thus, lacking the periodicity thereof at the position where the insulating layer50is provided. Thereby, it is possible, for example, in the step for forming the memory holes MH to improve the uniformity of hole patterns provided in a resist layer using photolithography.

There may be a case, however, where the structural defects are induced by an unexpected shape of the memory hole MHD when the insulating layer50has less resistivity against the etching for forming the memory hole MHD as described later. Thus, in the embodiment, the first layer51is made of material that has high resistivity against the etching for forming the memory holes MH, thereby suppressing the occurrence of structural defects, and improving the manufacturing yield.

Hereinafter, a manufacturing method of the semiconductor memory device is described with reference toFIGS. 3A to 31.FIGS. 3A to 31are schematic views showing a manufacturing process of the semiconductor memory device according to the embodiment.

As shown inFIG. 3A, a stacked body110is formed by alternately stacked insulating layers13and15on the source layer10. The insulating layers13are, for example, silicon oxide layers. The insulating layers15are, for example, silicon nitride layers. The insulating layers13and15are formed, for example, using chemical vapor deposition (CVD).

Then, a groove103is formed, which extends downward from the top surface of the stacked body110. The groove103is formed to divide at least one of the insulating layers15and to expose the insulating layer13aat the bottom thereof (seeFIG. 3B). In this example, the groove103is formed to divide three insulating layers15. The groove103is formed, for example, using reactive ion etching (RIE), and extends in the Y-direction.

FIGS. 3B and 3Care the schematic cross-sectional views showing a divided portion Dp shown inFIG. 3A. As shown inFIG. 3B, the end portions of the insulating layers15exposed in the wall surfaces of the groove103are converted to the first layer53and the second layer55.

For example, the second layer53and the third layer55are formed by thermally oxidizing the insulating layers15exposed in the wall surfaces of the groove103. The second layer53and the third layer55are, for example, silicon oxide layers or silicon oxynitride layers. The second layers53and the third layers55are formed, for example, so as to have a thickness of not less than 3 nanometers (nm) in the X-direction.

As shown inFIG. 3C, the first layer51is formed in the groove103. The first layer51is, for example, a silicon nitride layer. For example, a silicon nitride layer is formed using CVD so as to fill the groove103and cover the top surface of the stacked body. Then, the first layer51is formed by etching back the silicon nitride layer, leaving a portion that fills the groove103.

As shown inFIG. 3D, memory holes MH are formed from the top surface of the stacked body110so as to have a depth capable of reaching the source layer10. The memory holes MH are formed, for example, by selectively removing the insulating layers13and15using anisotropic RIE. The source layer10is exposed at the bottom surfaces of the memory holes MH.

As shown inFIG. 3E, an insulating layer63, a semiconductor layer60and a core body67are formed in each of memory holes MH. The insulating layer63is formed, for example, using CVD so as to have a structure in which a silicon oxide layer, a silicon nitride layer and a silicon oxide layer are stacked in order on the inner wall of the memory hole MH (seeFIG. 4C). The semiconductor layer60is, for example, a poly-crystallized silicon layer formed using CVD, and covers the insulating layer63and the source layer10exposed at the bottom surface of the memory hole MH. The core body67is, for example, a silicon oxide formed using CVD, and is embedded in the memory hole MH.

As shown inFIG. 3F, an insulating layer17is formed to cover the top surface of the stacked body110. The insulating layer17is, for example, a silicon oxide layer formed using CVD. Then, a slit105is formed from the top surface of the insulating layer17so as to have a depth capable of reaching the source10. The slit105is formed, for example, using anisotropic RIE, and extends in the Y-direction and the Z-direction. The slit105divides the stacked body110into a plurality of portions each including the insulating layer50and a plurality of memory holes MH.

As shown inFIG. 3G, the insulating layers15are selectively removed by etching liquid supplied through the slit105. For example, it is possible to selectively remove the insulating layers15by supplying hot phosphoric acid as the etching liquid, when the insulating layers13are silicon oxide layers, and the insulating layers15are silicon nitride layers. During this process, the second layer53and the third layer55has a resistivity against the etching liquid, and protect the first layer51.

As shown inFIG. 3H, word lines20and selection gates30are formed in the spaces15sfrom which the insulating layers15are removed (seeFIG. 3G). The word lines20and the selection gates30include, for example, tungsten layers formed using CVD. The word lines20and the selection gates30may include barrier metal such as titanium nitride (TiN) formed between a tungsten layer and an insulating layer13.

The second layer53and the third layer55each have a thickness not less than 3 nanometers in the X-direction. Thus, the first layer51is provided with a distance of 3 nanometers from each selection gate30.

As shown inFIG. 3I, a source contact body70is formed in the slit105. The source contact body70is, for example, a tungsten layer, and is electrically connected to the source layer. The source contact body70is electrically insulated from the word lines20and the selection gates30by an insulating layer21. The insulating layer21is, for example, a silicon oxide layer formed using CVD.

Then, an insulating layer19is formed to cover the insulating layer17and the source contact body70. Further, the bit lines80and the source line90(seeFIG. 1) are formed on the insulating layer19. The bit lines80are electrically connected to semiconductor layers60through contact plugs83. The source contact body70is electrically connected to the source line90at a portion not shown.

FIGS. 4A to 4Care schematic views showing a part of the semiconductor memory device1according to the embodiment.FIGS. 4A to 4Cis the schematic views showing the partial cross-sectional views taken along A-A line shown inFIG. 2A, and showing an example of forming the memory holes MHD.

The memory holes MHD is formed, for example, at the same time with the memory holes MH at the step showing inFIG. 3D. As shown inFIGS. 4A and 4B, the memory holes MHD is formed, for example, so as to divide the insulating layer50in the Y-direction. Further, as shown inFIG. 4C, a semiconductor layer60c, an insulating layer63and a core body67are also provided in each memory hole MHD. In other words, the semiconductor layer60c(the third semiconductor layer) divides the insulating layer50.

The insulating layer63includes, for example, a first layer71, a second layer73and a third layer75. The first layer71is, for example, a silicon oxide layer, and covers the inner wall of the memory hole MHD. The second layer73is, for example, a silicon nitride layer, and is formed between the first layer71and the third layer75. The third layer75is, for example, a silicon oxide layer, and is formed between the second layer73and the semiconductor layer60c.

FIGS. 5A to 5Care schematic views showing a part of a semiconductor memory device2according to a comparable example.FIG. 5Ais the schematic cross-sectional view showing the part corresponding to the divided portion Dp shown inFIG. 3A.FIGS. 5B and 5Cis the schematic views showing the cross-section taken along the B-B line shown inFIG. 5A.

In the example shown inFIG. 5A, the groove103is filled with an insulating layer23. When the insulating layer23has, for example, inferior resistivity against the RIE used for forming the memory holes MHD comparing with the second layer53and the third layer55, the memory holes MHD cannot keep the prescribed shape, and as shown inFIG. 5C, are formed so as to extend in the Y-direction and the reverse direction thereof (the −Y direction). Such a phenomenon may occur, for example, in the case where a silicon oxide layer formed using CVD is used as the insulating layer23. That is, the insulating layer23has inferior resistivity against the RIE comparing with the second layer53and the third layer55formed by the thermally oxidization and the insulating layer15that is the silicon nitride layer.

There may be a case where the memory holes MHD extended in the Y-direction as shown inFIG. 5Cinduces a structural defect, for example, in the process of forming the semiconductor layer60, the insulating layer63and the core body67(seeFIG. 3E), and serves as a factor that lowers the manufacturing yield.

In contrast, in the embodiment, the silicon nitride layer15is used, for example, as the first insulating layer15shown inFIG. 4A. Thus, it is possible to keep the shape of memory holes MHD as shown inFIG. 4B. That is, the shape change of the memory holes MHD is suppressed by using material that has superior resistivity against the RIE for the first layer51, thereby improving the manufacturing yield.

FIGS. 6A to 6Dis schematic cross-sectional views showing a part of a semiconductor memory device1according to a first variation of the embodiment.FIGS. 6A to 6Dare the schematic views showing the divided portion Dp shown inFIG. 3A.

In the example shown inFIG. 6A, a groove113is formed from the top surface of the stacked body110so as to extend through the insulating layers13,15and13ato reach an insulating layer15a. The insulating layer15ais exposed at the bottom surface of the groove113. Further, a forth layer57is formed by oxidizing the insulating layer15aexposed at the bottom surface of the groove113through the process in which the second layer53and the third layer55are formed by thermally oxidizing the insulating layers15exposed in the wall surface of the groove113. The fourth insulating layer57is, for example, a silicon oxide layer or a silicon oxynitride layer.

As shown inFIG. 6B, the first layer51is formed in the groove113. The first layer51is, for example, a silicon nitride layer.

As shown inFIG. 6C, the insulating layers15are selectively removed. The insulating layer15ais removed, leaving the forth layer57. The fourth layer57protects the first layer51through the etching process of the insulating layers15.

As shown inFIG. 6D, the word lines20and the selection gates30are formed in the spaces15sfrom which the insulating layers are removed. The topmost layer20aof the word lines20is also formed after the removal of the insulating layers15a.

In this example, the insulating layers15are surely separated, which are provided at higher levels than a level of the insulating layer13a, by forming the groove113so as to extend through the insulating layer13a. Thereby, it is possible to improve the electrical isolation between the selection gates30aand30b.

FIGS. 7A to 7Dare schematic views showing a part of a semiconductor memory device1according to a second variation of the embodiment.FIGS. 7A to 7Dare the schematic views showing the cross-section of the divided portion Dp shown inFIG. 3A.

As shown inFIG. 7A, the groove113is formed from the top surface of the stacked body110so as to extend through the insulating layers13,15and13ato reach the insulating layer15a. Further, the second layer53, the third layer55and the fourth layer57are formed by thermally oxidizing the insulating layers15exposed in the wall surface of the groove113and the insulating layer15aexposed at the bottom surface of the groove113.

As shown inFIG. 7B, an insulating layer91is formed to cover the inner surface of the groove113, and further, the first layer51is formed in the groove113. The insulating layer91is, for example, a silicon oxide layer.

As shown inFIG. 7C, the insulating layers15are selectively removed. In this example, the first layer51is surely protected through the etching process of the insulating layers15by providing the insulating layer91.

As shown inFIG. 7D, the word lines20and the selection gates30and40are formed in the spaces15sfrom which the insulating layers15are removed.

In this example, the resistivity of protection layers (the second layer53, the third layer55and the insulating layer91) is improved against the etching through the process in which the insulating layers15are selectively removed. Thereby, the unintended change of the hole shape is suppressed by the first layer51through the step of forming the memory holes MHD.

FIGS. 8A to 8Dare schematic cross-sectional views showing a part of a semiconductor memory device1according to a third variation of the embodiment.FIGS. 8Ato8D are the schematic views showing a cross-section of the divided portion Dp shown inFIG. 3A.

As shown inFIG. 8A, the groove113is formed from the top surface of the stacked body110so as to extend through the insulating layers13,15and13ato reach the insulating layer15a. Further, an insulating layer93is formed to cover the inner surface of the groove113. The insulating layer93is, for example, a silicon oxide layer. Alternatively, the insulating layer93may have, for example, the ONO structure in which a silicon oxide layer, a silicon nitride layer and another silicon oxide layer are stacked in order.

As shown inFIG. 8B, the first layer51is formed in the groove113. Further, the insulating layers15are selectively removed as shown inFIG. 8C. In this example, the first layer51is protected by the insulating layer93through the etching process of the insulating layers15.

As shown inFIG. 8D, the word lines20and selection gates30are formed in the spaces15sfrom which the insulating layers15are removed. In this example, a part of the insulating layer93acts as the second layer between the selection gate30aand the first layer51. Another part of the insulating layer93acts as the third layer between the selection gate30band the first layer51.

That is, the insulating layer93protects the first layer51through the process of the selective removal of the insulating layers15. Thus, the unintended change of the hole shape is suppressed by the first layer51through the process of forming the memory holes MHD.