SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (S/D) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced a fast-paced growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

DETAILED DESCRIPTION

The embodiments of the disclosure describe methods for forming a semiconductor device (or a portion of a nanostructure transistor device) with reduced resistance and improved performance. The nanostructure transistor device (also referred to as a gate-all-around (GAA) transistor device) may include a gate structure wrapping around the perimeter of one or more nanosheets (i.e. channel regions) for improved control of channel current flow. The embodiments are not limited in the context. The semiconductor device may be included in microprocessors, memories, and/or other ICs. Moreover, it is understood that the semiconductor device may be part of an IC that further includes a number of other devices such as resistors, capacitors, inductors, fuses, etc. It is understood that the structures illustrated in the drawings are simplified for a better understanding of the concepts of the disclosure.

FIGS.1through14illustrate schematic cross-sectional views of intermediate steps during a process for forming a semiconductor device, according to some embodiments. For clarity of illustrations, in the drawings are illustrated the orthogonal axes (X, Y and Z) of the Cartesian coordinate system according to which the views are oriented. It should be noted thatFIGS.1-4Aare cross-sectional views of the structure taken at the X-Z plane,FIG.4Bis a cross-sectional view of the structure illustrated inFIG.4Ataken along the line A-A′, andFIGS.4B and5-14are cross-sectional views taken at the Y-Z plane and illustrating the following steps of forming a semiconductor device. AlthoughFIGS.1-14are described as a series of acts, these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In alternative embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

Referring toFIG.1, a stack of first semiconductor layers104(e.g.,104-1,104-2, and104-3) and second semiconductor layers106may be formed on a semiconductor substrate102′. In some embodiments, the semiconductor substrate102′ includes a crystalline silicon substrate or a bulk silicon substrate (e.g., wafer). In some embodiments, the semiconductor substrate102′ is made of a suitable elemental semiconductor (e.g., germanium), a suitable compound semiconductor (e.g., gallium arsenide, silicon carbide, indium arsenide, or indium phosphide), a suitable alloy semiconductor (e.g., silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide), and/or the like. In some embodiments, the semiconductor substrate102′ includes a silicon-on-insulator (SOI) substrate or other suitable substrate. The semiconductor substrate102′ may include various doped regions (not individually shown) doped with p-type or n-type dopants, where the doped regions may be configured for an n-type region, or alternatively, configured for a p-type region.

The first semiconductor layers104and the second semiconductor layers106may be alternately stacked upon one another (e.g., along the Z-direction) to form a stack. In some embodiments, the first semiconductor layers104and the second semiconductor layers106are grown from the semiconductor substrate102′. For example, each of the first semiconductor layers104and the second semiconductor layers106is grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, or any suitable growth process. The first semiconductor layers104may be considered sacrificial layers in the sense that they are removed in the subsequent process (seeFIG.12). The second semiconductor layers106may be semiconductor nanosheets that serve as channel regions in the semiconductor device. The terms “semiconductor nanosheets” and “channel regions/layers” may be used interchangeably herein.

In some embodiments, the bottommost one of the first semiconductor layers (i.e. the bottommost first semiconductor layer104-3) is formed on the semiconductor substrate102′, with the remaining second and first semiconductor layers (106and104) alternately stacked on top. However, either the first semiconductor layer104or the second semiconductor layer106may be the bottommost layer (or the layer most proximate from the semiconductor substrate102′). In some embodiments, the second semiconductor layer106may be the topmost layer (or the layer most distanced from the semiconductor substrate102′) of the stack. It should be noted that the number of the first semiconductor layers104and the number of the second semiconductor layers106illustrated herein are examples and construe no limitation in the disclosure.

The first semiconductor layers104and the second semiconductor layers106may include different materials (or compositions) that provide for different oxidation rates and/or different etch selectivity between the layers. For example, the second semiconductor layers106are formed of the same material as the semiconductor substrate102′, while the first semiconductor layers104may be formed of a different material which is selectively removed with respect to the material of the semiconductor substrate102′ and the second semiconductor layers106. In some embodiments, the first semiconductor layers104may each include silicon germanium (SiGe). In some embodiments, the second semiconductor layers106may each include silicon, where the respective second semiconductor layer106may be undoped or substantially dopant-free. In some embodiments, the second semiconductor layers106are doped with a p-type dopant such as boron, aluminum, indium, and gallium. In some embodiments, the second semiconductor layers106are doped with an n-type dopant such as phosphorus, arsenic, antimony. Either of the first semiconductor layers104and the second semiconductor layers106may include other materials, for example, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, any other suitable material, or combinations thereof.

With continued reference toFIG.1, in the example where the first semiconductor layers104are formed of SiGe, the topmost first semiconductor layer104-1may contain SiGe with a first percentage of Ge, and the bottommost first semiconductor layer104-3may contain SiGe with a second percentage of Ge, where the first percentage is different from the second percentage. In some embodiments, the second percentage is less than the first percentage. The second percentage may range from about 10% to about 30%. The first percentage may range from about 20% to about 50%. The middle first semiconductor layer104-2may contain SiGe with the first percentage of Ge (or other percentage of Ge higher than the second percentage of Ge). The bottommost first semiconductor layer104-3formed of SiGe may have less Ge and more Si. For example, Ge may include about 10% to 30% of the bottommost first semiconductor layer104-3in molar ratio. By configuring the bottommost first semiconductor layer104-3having lower percentage of Ge, a less portion of the bottommost first semiconductor layer104-3will be removed during the subsequently-performed process (seeFIG.7).

Referring toFIG.2and with reference toFIG.1, a portion of the stack of first semiconductor layers104and second semiconductor layers106along with the underlying portion of the semiconductor substrate102′ may be removed to form trenches100T, thereby defining a fin structure100″ between adjacent trenches100T. The fin structure100″ may be formed by patterning the stack of first semiconductor layers104and second semiconductor layers106and the underlying semiconductor substrate102′ by using, e.g., lithography and etching, or other suitable patterning processes. For example, a mask layer (not shown) is formed and patterned on the top of the stack, and the fin structure100″ is formed by etching trenches100T at portions of the stack of first semiconductor layers104and second semiconductor layers106and the underlying semiconductor substrate102′ that are accessibly exposed by the mask layer. After forming the trenches100T, the mask layer may be removed to reveal the topmost second semiconductor layer106. The trenches100T may be parallel strips (when viewed from the top) elongated along the Y-direction and distributed along the X-direction.

Referring toFIG.3and with reference toFIG.2, a plurality of isolation structures302, also referred to as shallow trench isolation (STI) structures, may be formed in lower portions of the trenches100T. For example, the isolation structures302extend at opposing sides of a lower portion of the semiconductor substrate102′. In some embodiments, each of the isolation structures302is disposed between adjacent two of the fin structures100″ and covers a sidewall of a lower portion of the respective fin structure100″. The top surface302tof the respective isolation structure302may be a flat surface, a curved (e.g., convex or concave) surface, or a combination thereof. The isolation structures302may be formed of an insulation material (e.g., an oxide, a Si-based oxide (e.g., SiOC, SiOCN, or the like), a nitride, the like, any other suitable material, or combinations thereof) which may electrically isolate neighboring fin structures100″ from each other. The isolation structures302may be formed by high-density plasma CVD, flow-able CVD, the like, a combination thereof, etc.

Referring toFIGS.4A and4Bwith reference toFIG.3, a dummy gate structure203and a mask layer204overlying the dummy gate structure203may be formed on the fin structures100″. For example, the dummy gate structure203includes a dummy dielectric layer2031formed on the fin structures100″ and a dummy gate layer2032formed on the dummy dielectric layer2031. In some embodiments, the dummy dielectric layer2031covers the top surfaces302tof the isolation regions302and may extend between the dummy gate layer2032and the isolation regions302. The dummy dielectric layer2031may include silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate layer2032may be a conductive or non-conductive material, and may be selected from a group including amorphous silicon, polysilicon, poly-crystalline silicon-germanium, metallic oxides, and metals, and may be formed by using physical vapor deposition (PVD), CVD, sputtering, or other suitable techniques.

The mask layer204formed on the dummy gate layer2032may be a single mask layer or include multiple sublayers formed of different materials including silicon nitride, silicon oxynitride, or the like. In the illustrated embodiment, the mask layer204includes a first mask sublayer2041overlying the dummy gate layer2032and a second mask sublayer2042overlying the first mask sublayer2031. For example, a layer of mask material is initially formed and then patterned using acceptable lithography and etching techniques to form the mask layer204. Next, the pattern of the mask layer204may be transferred to the underlying dummy gate and dielectric materials to form the dummy gate layer2032and the dummy dielectric layer2031, respectively. For example, the dummy gate structure203has a lengthwise direction along the X-direction which is perpendicular to the lengthwise direction (e.g., the Y-direction) of the respective fin structure100″.

Referring toFIG.5and with reference toFIG.4B, a gate spacer layer205′ may be conformally formed on the dummy gate structure203, the mask layer204, and portions of the fin structure100″ exposed by the dummy gate structure203and the mask layer204. In the X-Z cross section (not shown), the gate spacer layer205′ may further extend to cover sidewalls of the respective fin structure100″. The gate spacer layer205′ may be a single layer or may include multiple sublayers formed of different materials including silicon oxide, silicon nitride, silicon oxynitride, or the like. The gate spacer layer205′ may be deposited by thermal oxidation or deposited by CVD, ALD, etc.

Referring toFIG.6and with reference toFIG.5, a portion of the gate spacer layer205′ covering an upper portion of the mask layer204and the top surface of the respective fin structure100″ may be removed to form a gate spacer205. For example, the gate spacer layer205′ is partially removed using an etching process to form the gate spacer205, where the gate spacer205may be disposed on the sidewall of the dummy gate structure203and may extend to partially (or fully) cover the sidewall of the mask layer204. In some embodiments, the top surface and the upper sidewall of the second mask sublayer2042are exposed by the gate spacer205. The gate spacer205may act to self-align subsequently-formed source/drain (S/D) regions, as well as to protect sidewalls of the respective fin structure100″ during subsequent processing.

In some embodiments, a portion of the respective fin structure100″ and a portion of the semiconductor substrate102′ underlying the portion of the respective fin structure100″ are removed to form recesses100R and a respective etched fin structure100′ between two adjacent recesses100R. S/D regions will be subsequently formed in the recesses100R, and the recesses100R may be referred to as S/D recesses. The recesses100R may be formed by etching the gate spacer layer205′, the underlying fin structures100″, and the underlying semiconductor substrate102′ using etching processes, such as anisotropic etching, or the like. A single etching process or multiple etching processes may be employed. In some embodiments, outer sidewalls of the gate spacer205are substantially aligned with sidewalls of the etched fin structure100′. The respective recess100R may further extend into the underlying semiconductor substrate102′ to form a semiconductor substrate102having exposed top surfaces102t, where the top surfaces102tmay be a flat surface, a curved (e.g., concave) surface, or combinations thereof, depending on the etching process.

Referring toFIG.7and with reference toFIG.6, portions of the first semiconductor layers104exposed by the recesses100R may be removed in the lateral direction (e.g., the Y-direction) to form a respective etched fin structure100having etched first semiconductor layers104′. The removal may be performed by, e.g., isotropic etching or the like. For example, the etchant of the selective etching process is chosen so that the portions of the first semiconductor layers104are removed to form lateral recesses (e.g.,104R and104R′), while the second semiconductor layers106remain substantially intact after the etching. The respective etched first semiconductor layer104′ may be laterally recessed from the sidewalls of the underlying (or overlying) second semiconductor layer106. Although sidewalls of the etched first semiconductor layers104′ adjacent to the lateral recesses104R are illustrated as being straight inFIG.7, the sidewalls of the etched first semiconductor layers104′ may be tilted, concave, or convex.

With continued reference toFIG.7, since the bottommost first semiconductor layer104-3may have lower percentage of Ge than the topmost first semiconductor layer104-1as mentioned inFIG.1, the etched portion of the bottommost first semiconductor layer104-3is less than the etched portion of the topmost first semiconductor layer104-1. For example, the lateral recess104R surrounding the topmost first semiconductor layer104-1′ may be wider than the lateral recess104R′ surrounding the bottommost first semiconductor layer104-3′. The bottommost first semiconductor layer104-3′ may have a lateral dimension L3greater than a lateral dimension L1of the topmost first semiconductor layer104-1′. In some embodiments, the middle first semiconductor layer104-2′ may have a lateral dimension L2less than the lateral dimension L3.

Referring toFIG.8and with reference toFIG.7, inner spacers212(e.g.,212-1,212-2, and212-3) may be formed in the lateral recesses104R and104R′. For example, the inner spacers212are formed along the etched ends of each of the etched first semiconductor layers104′ and along respective ends (along the Y-direction) of each of the etched first semiconductor layers104′ and the second semiconductor layers106. The inner spacers212may be formed of silicon nitride, silicon carbon-nitride, silicon-carbon-oxynitride, or any other type of dielectric material, and may be deposited using, e.g., a conformal deposition process and subsequent etching back to remove excess spacer material on the sidewalls of the etched fin structure100and on the exposed surface of the semiconductor substrate102. In some embodiments, the inner spacers212are formed of a material different from the gate spacer205. The gate spacer205may serve as an etch mask when removing the excess spacer material, and thus the outer sidewall of the gate spacer205may be substantially aligned with outer sidewalls of the underlying second semiconductor layers106and outer sidewalls of the inner spacers212.

With continued reference toFIG.8andFIG.7, the inner spacers (e.g.,212-1,212-2, and212-3) may each have sidewalls substantially aligned with one another. Since the bottommost first semiconductor layer104-3′ having the greater lateral dimension L3than the lateral dimensions L1and L2of the overlying first semiconductor layers (104-1′ and104-2), the bottommost inner spacer212-3may have a thickness W3less than a thickness W1of the topmost inner spacer212-1and a thickness W2of the middle inner spacer212-2. For example, the difference between the thickness W1and the thickness W3ranges from about 0.5 nm to about 4.0 nm. In some embodiments, the thickness W1of the topmost inner spacer212-1ranges from about 3 nm to about 14 nm. In some embodiments, the thickness W3of the bottommost inner spacer212-3ranges from about 2 nm to about 10 nm. Other differences and thicknesses are within the contemplated scope of the disclosure. The thicknesses W1and W2may be substantially equal or may be different, depending on the lateral etching process variations.

Referring toFIG.9and with reference toFIG.8, epitaxial structures220may be epitaxially grown in the recesses100R using a process such as CVD, ALD, MBE, or the like. The epitaxial structures220grown on the semiconductor substrate102may have a bottom surface conformally coupled to the exposed top surfaces102tof the semiconductor substrate102. In some embodiments where the semiconductor substrate102has a concave top surface, the bottom surface of the respective epitaxial structure220may be a convex surface corresponding to the exposed top surfaces102t. Although the upper surfaces of the epitaxial structures220are illustrated as planar surfaces in the Y-Z cross section, it should be understood that in the perspective view, the upper surfaces of the epitaxial structures220have facets which expand laterally outward along the Y-direction beyond the sidewalls of the dummy gate structures203. In some embodiments, the epitaxial structures220are coupled to the outer sidewalls of the second semiconductor layers106and the inner spacers212along the Y-direction. Each dummy gate structure203may be disposed between respective neighboring pairs of the epitaxial structures220. The gate spacer205may be used to separate the epitaxial structures220from the dummy gate structure203by a lateral distance so that the epitaxial structures220do not short out with subsequently-formed gate structures.

Each epitaxial structure220may include silicon germanium, indium arsenide, indium gallium arsenide, indium antimonide, germanium arsenide, germanium antimonide, indium aluminum phosphide, indium phosphide, any other suitable material, or combinations thereof. The epitaxial structures220may be doped with a conductive dopant to form S/D regions. For example, the S/D dopant may be formed by in-situ epitaxially growth, ion implantation, solid phase diffusion, a combination thereof, etc., where the ion implantation process or the solid phase diffusion process may be processed after epitaxially growth or after the etching ofFIG.12. It should be noted that S/D region(s) may refer to a source or a drain, individually or collectively dependent upon the context. The terms “epitaxial structures” and “S/D regions” are used interchangeably herein. The structure shown herein may be in the n-type region (e.g., the NMOS region) or the p-type region (e.g., the PMOS region). In some embodiments, the dopant of the epitaxial structures220grown in the n-type region (not individually shown) may be donor-type species, such as phosphorus, arsenic, antimony for silicon-based transistor. In some embodiments, the dopant of the epitaxial structures220grown in the p-type region (not individually shown) may be acceptor-type species, such as boron, aluminum, gallium for silicon-based transistor.

With continued reference toFIG.9, the respective epitaxial structure220may have different doping levels. For example, the respective epitaxial structure220includes a bottom region220boverlying the semiconductor substrate102and laterally adjacent to the raised portion of the semiconductor substrate102. The bottom region220bmay be an undoped region (or substantially dopant-free region). The other region of the respective epitaxial structure220overlying the bottom region220bmay be doped with a higher doping concentration than the bottom region220b. Alternatively, the bottom region220bis omitted. The bottoms region220binFIG.9and the followingFIGS.10-14are illustrated in the dashed lines to indicate they may or may not exist.

Referring toFIG.10and with reference toFIG.9, a first interlayer dielectric (ILD) material layer306′ may be formed over the structure illustrated inFIG.9. The first ILD material layer306′ may be formed of a dielectric material including phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or the like. In some embodiments, an etch stop material layer304′ is disposed between the first ILD material layer306′ and the epitaxial structures220, the mask layer204, and the gate spacer205. The etch stop material layer304′ may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, or the like), and may have a different etch rate than the material of the overlying first ILD material layer306′.

Referring toFIG.11and with reference toFIG.10, one or more removal processes may be performed to form a first ILD layer306, the etch stop layer304lining the first ILD layer306, and a recess306R accessibly revealing the topmost one of the second semiconductor layers106of the respective etched fin structure100. For example, the removal processes includes a planarization process performed on the first ILD material layer306′. The planarization process may include CMP, grinding, etching, combinations thereof, or the like. During the planarization process, the mask layer204may be partially (or fully) removed. In some embodiments, the gate spacer205is also planarized during the planarization process. In some embodiments, one or more etching process may be performed after the planarization to remove the rest portion of the mask layer204(if exist) and the underlying dummy gate structure203so as to form the recess306R. For example, reaction gas(es) may be used to selectively etch the dummy structure203at a faster rate than the first ILD material layer306′, the etch stop material layer304′, or the gate spacer205.

Referring toFIG.12and with reference toFIG.11, the etched first semiconductor layers104′ may be removed by etching (e.g., isotropic etching or the like) to form recesses104S (e.g.,104-1S,104-2S, and104-3S). For example, using etchants which are selective to the materials of the etched first semiconductor layers104′, while the second semiconductor layers106, the first ILD layer306, the etch stop layer304, the gate spacer205, and the inner spacers212remain relatively un-etched as compared to the etched first semiconductor layers104′. During the removal process, the first ILD layer306and the etch stop layer304may protect the epitaxial structures220. In some embodiments, after the removal of the etched first semiconductor layers104′, respective bottom and top surfaces of each second semiconductor layers106and the top surface of the semiconductor substrate102may be exposed by the recesses104S. Since the bottommost first semiconductor layer104-3′ has the greater lateral dimension L3(seeFIG.7), the bottommost recess104-3S formed by removing the bottommost first semiconductor layer104-3′ may have a recess size greater than recess sizes of the overlying recesses104-1S and104-2S which are respectively formed by removing the topmost first semiconductor layers104-1′ and the middle first semiconductor layers104-2′.

Referring toFIG.13and with reference toFIG.12, a gate structure240may be formed around the second semiconductor layers106and fill the recesses306R and104S. The gate structure240may include a plurality of gate sections (e.g.,240T,240-1,240-2, and240-3) abutted to each other along the Z-direction in the X-Z plane. Each of the gate sections may extend not only along a horizontal plane (e.g., the X-Y plane), but also along a vertical direction (e.g., the Z-direction), and thus two adjacent ones of the gate sections may adjoin together to wrap around a corresponding one of the second semiconductor layers106, where the second semiconductor layers106(also referred to as semiconductor nanosheets or channel layers) function as channel regions.

The gate structure240may include a gate dielectric layer (not individually shown), an interfacial layer (not individually shown) formed between each channel layer106and the gate dielectric layer, and a gate metal layer (not individually shown) wrapping around each channel layer106with the gate dielectric layer disposed therebetween. The gate dielectric layer may be one or more high-k dielectric material(s). The gate metal layer may include a stack of multiple metal materials. For example, one or more work function sublayers are interposed between the gate dielectric layer and the gate metal layer, where the work function sublayers may be formed separately for the n-type FET and the p-type FET which may use different metal layers. In some embodiments, excess materials of the gate structure240may be removed by a planarization process, so that the top surface of the topmost gate structure240is substantially leveled (e.g., coplanar) with top surfaces of the first ILD layer306and the etch stop layer304, within process variations.

With continued reference toFIG.13, in the Y-Z cross section, the bottommost gate section240-3is laterally surrounded by the bottommost inner spacer212-3may have a lateral dimension (also referred to as the bottommost gate length) GL3greater than a lateral dimension (also referred to as the topmost gate length) GL1of the topmost gate section240-1laterally surrounded by the topmost inner spacer212-1. For example, a ratio of the lateral dimension GL3to the lateral dimension GL1ranges from about 1.0 to about 2.0. Although other ratios are within the contemplated scope of the disclosure. In some embodiments, the lateral dimension GL3is greater than a lateral dimension GL2of the middle gate section240-2laterally surrounded by the middle inner spacer212-2. The lateral dimensions GL1and GL2may be substantially equal or may be different, depending on the thicknesses of the inner spacers212-1and212-2and the process variations.

Referring toFIG.14and with reference toFIG.13, a second ILD layer307may be formed on the first ILD layer306. The second ILD layer307may be formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, S/D contacts312are formed to extend through the second ILD layer307and the underlying first ILD layer306so as to be electrically coupled to the epitaxial structures220. A gate contact314may be formed to extend through the second ILD layer307so as to be electrically coupled to the topmost gate section240T of the gate structure240. In some embodiments, a planarization process is performed to level the top surfaces of the S/D contacts312and the gate contact314.

In some embodiments, a front-side interconnect structure320including interconnect wirings322formed in an interconnect dielectric layer321may be formed on the second ILD layer307, the S/D contacts312, and the gate contact314. The front-side interconnect structure320may be formed by back end of line (BEOL) processes and may be referred to as a BEOL interconnect structure. The material of the interconnect dielectric layer321may include a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The interconnect wirings322may include conductive pads, conductive lines, and conductive vias interconnecting the layers of conductive lines, and may be formed through any acceptable process, such as a damascene process, a dual damascene process, or the like. For example, the conductive vias may extend through the interconnect dielectric layer321to provide vertical connections between layers of the conductive lines, and the bottommost conductive vias of the interconnect wirings322may be in physical and electrical contact with the S/D contacts312and the gate contact314. The front-side interconnect structure320may be electrically coupled to the epitaxial structures220and the gate structure240through the S/D contacts312and the gate contact314, respectively, to form functional circuits.

With continued reference toFIG.14, a semiconductor device10includes a device layer101formed in/on the semiconductor substrate102and the front-side interconnect structure320formed on the device layer101. The device layer101may include a plurality of active devices (e.g., transistors), and the respective active device may include the epitaxial structure220(e.g., S/D regions), the second semiconductor layers106(e.g., the channel regions/layers), and the gate structures240. The structure illustrated inFIG.14may be in the n-type (e.g., NMOS) region or the p-type (e.g., PMOS) region. Although the device layer101shown herein is described as including nano-FETs, other embodiments may include device layers including different types of transistors, such as planar FETs, FinFETs, thin film transistors, or the like. The semiconductor device10may be a portion of a device wafer having a plurality of die regions. The device wafer may be singulated to separate a die from one another, and then the die may be packaged to form an IC package. The die may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a MEMS controller (e.g., application specific integrated circuit (ASIC)), a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof.

Still referring toFIG.14, the bottommost inner spacer212-3extending along sidewalls of the bottommost gate section240-3may be thinner than the overlying inner spacers212, and the bottommost gate section240-3laterally covered by the bottommost inner spacer212-3may have a gate length longer than the overlying gate sections. It should be appreciated that the thickness of the inner spacer212may affect the dimensions of overlapping and underlapping regions of the channel layer. For example, the overlapping region of the bottommost channel layer160-3is a region directly on the bottommost gate section240-3, and the underlapping region of the bottommost channel layer160-3is a region directly on the bottommost inner spacer212-3. By configuring the thinner bottommost inner spacer212-3, the wider bottommost gate section240-3may be formed, the overlapping region may be increased, and the underlapping region may be decreased, thereby reducing resistance of the bottommost channel layer106-3.

It has been observed that for the semiconductor device having the inner spacers with the same thickness at each level, the bottommost channel region has higher resistance than the topmost channel regions due to the longer gate-to-S/D current path for the bottommost channel region and less junction overlapping by lower doping concentration. For example, the lower section of the S/D region laterally adjacent to the bottommost channel region has a lower doping concentration than the top section of the S/D region laterally adjacent to the topmost channel regions. By configuring the thinner bottommost inner spacer212-3, the gate length may be increased and gate-junction overlapping may be improved. This in turn enhances the performance of the semiconductor device10.

FIGS.15-22illustrate schematic cross-sectional views of intermediate steps during a process for forming a semiconductor device, in accordance with some embodiments. It should be noted thatFIGS.15-18Aare cross-sectional views of the structure taken at the X-Z plane,FIG.18Bis a cross-sectional view of the structure illustrated inFIG.18Ataken along the line A-A′, andFIGS.18B and19-22are cross-sectional views taken at the Y-Z plane and illustrating the following steps of forming a semiconductor device. Unless specified otherwise, like reference numerals in this embodiment represent like components in the embodiment shown inFIGS.1-14formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. In addition, althoughFIGS.15-22are described as a series of acts, these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. Alternatively, some acts that are illustrated and/or described may be omitted in whole or in part.

Referring toFIG.15and with reference toFIG.1, the structure shown inFIG.15is similar to the structure shown inFIG.1, and the difference therebetween includes that the semiconductor substrate202′ includes a doped layer202-1′ and the bottommost first semiconductor layer is substantially that same as the overlying first semiconductor layers104. The material of the semiconductor substrate202′ may be similar to that of the semiconductor substrate102′. In some embodiments, the doped layer202-1′ is an anti-punch through (APT) doped layer. For example, the ion implantation is performed on the semiconductor substrate to form the doped layer202-1′. Other suitable methods may be used to form the doped layer202-1′ in the semiconductor substrate202′. In some embodiments, the ion implantation of dopants (e.g., dopants used for APT implants) includes phosphorus, boron, carbon, arsenic, gallium, antimony, etc. In some embodiments, the doped layer202-1′ in the n-type region (not shown) has dopant species and/or doping concentration different from the doped layer202-1′ in the p-type region (not shown). In some embodiments, the doped layers202-1′ in both of the n-type region and the p-type region (not shown) have the same dopant species and/or doping concentration.

Referring toFIG.16and with reference toFIG.15andFIG.2, a portion of the stack of first semiconductor layers104and second semiconductor layers106along with the underlying portion of the semiconductor substrate202′ may be removed to form the trenches100T, thereby defining the fin structure100″ between adjacent the trenches100T. The removal process may be similar to the process described inFIG.2.

Referring toFIG.17and with reference toFIG.16andFIG.3, the isolation structure302may be formed in lower portions of the trenches100T as described inFIG.3. In some embodiments, during the formation of the isolation structure302, an anneal process may be performed once the insulation material is deposited. The anneal temperature may cause dopants in the doped layer202-1′ diffusion. In some embodiments, the dopants from the doped layer202-1′ are diffused into the bottommost first semiconductor layer104-3during (or after) forming the isolation structure302. In some embodiments where the doped layer202-1′ contains boron atoms, the boron atoms in the doped layer202-1′ diffuse into the bottommost first semiconductor layer104-3to form a diffused region104D in the bottommost first semiconductor layer104-3. In some embodiments, the diffused region104D is disposed at the bottom section of the bottommost first semiconductor layer104-3most proximate from the semiconductor substrate202′, and the top section of the bottommost first semiconductor layer104-3most distal from the semiconductor substrate202′ may remain substantially dopant-free. In some embodiments, the diffused region104D extends from the bottom to the top of the bottommost first semiconductor layer104-3. For example, the diffused region104D occupies the entire bottommost first semiconductor layer104-3. The diffused area in the bottommost first semiconductor layer104-3may vary depending on process variations.

Referring toFIGS.18A-18Band with reference toFIGS.4A-4B, the dummy gate structure203and the mask layer204may be sequentially formed on the fin structures100″. The materials and the forming processes of the dummy gate structure203and the mask layer204are similar to those of the dummy gate structure203and the mask layer204described inFIG.4A-4B.

Referring toFIG.19and with reference toFIG.18BandFIGS.5-7, the gate spacer205may be conformally formed on the dummy gate structure203, the mask layer204, and the top of the fin structure100″. Next, the respective fin structure100″ and the semiconductor substrate102′ may be partially removed to form the recesses100R. After forming the recesses100R, a portion of the doped layer may still remain, and thus the semiconductor substrate202with the recessed doped layer202-1is provided. Next, the first semiconductor layers104exposed by the recesses100R may be removed in the lateral direction (e.g., the Y-direction) to form the respective etched fin structure100having the etched first semiconductor layers104′. The forming processes of the gate spacer205, the recesses100R, and the etched first semiconductor layers104′ may be similar to the processes described inFIGS.5-7.

With a selective etching process, the diffused region104D in the bottommost first semiconductor layer104-3′ may slow down the lateral etching. For example, the bottommost first semiconductor layer104-3′ with the diffused region104D is etched more slowly than the first semiconductor layers without the diffused region (e.g.,104-1′ and104-2′). The difference in dimensions of the lateral recesses104R and104R′ may be results of difference in etch rates. For example, the dimension of the lateral recess104R′ corresponding to the bottommost first semiconductor layer104-3′ is less than that of the lateral recess104R corresponding to the topmost first semiconductor layer104-1′. The smaller dimension of the lateral recess104R′ may result in the larger size of the bottommost first semiconductor layer104-3′ remained. For example, the lateral dimension L3of the bottommost first semiconductor layer104-3′ is greater than the lateral dimension L1of the topmost first semiconductor layer104-1′ and also greater than the lateral dimension L2of the middle first semiconductor layer104-2′. The bottommost first semiconductor layer104-3′ may have a tilted (or curved) sidewall (not illustrated) after the lateral etching, since a region of the bottommost first semiconductor layer104-3′ that is substantially free of dopants may be etched faster than the diffused region104D.

Referring toFIG.20and with reference toFIG.19andFIG.8, the inner spacers212(e.g.,212-1,212-2, and212-3) may be formed in the lateral recesses104R and104R′. The material and the forming process of the inner spacers212may be similar to those of the inner spacers described inFIG.8. The bottommost inner spacer212-3may have the thickness W3less than the thickness W1of the topmost inner spacer212-1and also less than the thickness W2of the middle inner spacer212-2.

Referring toFIG.21and with reference toFIG.20andFIGS.9-12, the epitaxial structures220may be epitaxially grown in the recesses100R. The epitaxial structures220grown on the semiconductor substrate102may be in physical contact with the recessed doped layer202-1. As mentioned inFIG.9, the respective epitaxial structure220may have different doping levels and may include an undoped region at the bottom, where the undoped region is illustrated in the dashed lines to indicate it may or may not exist. Next, the first ILD layer306, the etch stop layer304, and the recess306R accessibly revealing the topmost one of the second semiconductor layers106of the respective etched fin structure100may be formed. The materials and the formation processes may be similar to the materials and the processes described inFIGS.10-11. Next, the etched first semiconductor layers104′ may be removed to form the recesses104S (e.g.,104-1S,104-2S, and104-3S). The process may be similar to the process described inFIG.12.

Referring toFIG.22and with reference toFIG.21andFIGS.13-14, the gate structure240may be formed around the second semiconductor layers106and fill the recesses306R and104S. The material and the forming process of the gate structure240may be similar to those of the gate structure240described inFIG.13. Next, the second ILD layer307, the S/D contacts312extending through the second ILD layer307and the first ILD layer306to be coupled to the epitaxial structures220, and the gate contact314extending through the second ILD layer307to be coupled to the topmost gate section240T of the gate structure240may be formed. The front-side interconnect structure320may then be formed on the second ILD layer307, the S/D contacts312, and the gate contact314. The materials and the forming processes of these features may be similar to those of the corresponding features described inFIG.14.

With continued reference toFIG.22andFIG.14, a semiconductor device20including a device layer201formed in/on the semiconductor substrate202and the front-side interconnect structure320formed on the device layer201is provided. The difference between the semiconductor device20and the semiconductor device10illustrated inFIG.14lies in that the semiconductor substrate202of the semiconductor device20includes the recessed doped layer202-1physically coupled to the bottom surfaces of the S/D regions220, the bottommost inner spacer212-3, and the bottommost gate section240-3. Since the bottommost inner spacer212-3is thinner than the overlying inner spacers212, the bottommost gate section240-3laterally covered by the bottommost inner spacer212-3may have a longer gate length than the overlying gate sections. By performing the annealing to allow the dopants in the doped layer of the semiconductor substrate diffused into the bottommost first semiconductor layer so as to form the diffused region, the lateral recessing of the bottommost first semiconductor layer may be slowed down such that the bottommost inner spacer formed around the bottommost first semiconductor layer may have a smaller thickness as compared to the thickness of the overlying inner spacers. By configuring the thinner bottommost inner spacer212-3, the gate length of the bottommost gate section240-3may be increased and gate-junction overlapping may be improved. This in turn enhances the performance of the semiconductor device20.

FIGS.23-29illustrate schematic cross-sectional views of intermediate steps during a process for forming a semiconductor device, in accordance with some embodiments. It should be noted thatFIGS.23-25Aare cross-sectional views of the structure taken at the X-Z plane,FIG.25Bis a cross-sectional view of the structure illustrated inFIG.25Ataken along the line A-A′, andFIGS.25B and26-29are cross-sectional views taken at the Y-Z plane and illustrating the following steps of forming a semiconductor device. Unless specified otherwise, like reference numerals in this embodiment represent like components in the embodiment shown inFIGS.1-22formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. In addition, althoughFIGS.23-29are described as a series of acts, these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. Alternatively, some acts that are illustrated and/or described may be omitted in whole or in part.

Referring toFIG.23and with reference toFIG.1, the structure shown inFIG.23is similar to the structure shown inFIG.1, except for the bottommost first semiconductor layer104-31. The bottommost first semiconductor layer104-31may include a doped region1041D. For example, the bottommost first semiconductor layer104-31and the overlying first semiconductor layer104may have the same material (or composition), and the ion implantation is performed to form the doped region1041D in the bottommost first semiconductor layer104-31. For example, a bottom section of the bottommost first semiconductor layer104-31is lightly doped to form the doped region1041D, where the doped region1041D is viewed as a lightly doped region. In some embodiments, the bottommost first semiconductor layer104-31is a single layer including the doped region1041D at the bottom. In some embodiments (as shown in the enlarged view), the bottommost first semiconductor layer104-31includes different doping levels. In some embodiments (as shown in the enlarged view), the bottommost first semiconductor layer104-31includes a plurality of sublayers, and the sublayers may include different percentages of Ge (or different materials/compositions) to migrate dopant diffusion into the bottommost second semiconductor layer106, where at least the bottommost one of the sublayers is doped to form the doped region1041D. For example, the bottommost first semiconductor layer104-31includes the dopants in the doped region1041D that enable the etch rate of the bottommost first semiconductor layer to be slowed down. In some embodiments, dopants in the doped region1041D include phosphorus, boron, carbon, arsenic, gallium, antimony, etc.

The first semiconductor layers104overlying the bottommost first semiconductor layer104-31may be undoped or substantially dopant-free. In some embodiments, one or more first semiconductor layers104overlying the bottommost first semiconductor layer104-31may have a different doping concentration or may have different dopants than the bottommost first semiconductor layer104-31. For example, the first semiconductor layers104overlying the bottommost first semiconductor layer104-31include the dopants that enable the etch rate of the overlying first semiconductor layers104to be faster than the bottommost first semiconductor layer104-31.

Referring toFIG.24and with reference toFIG.23andFIGS.2-3orFIGS.16-17, a portion of the stack of first semiconductor layers104and second semiconductor layers106along with the underlying portion of the semiconductor substrate102′ may be removed to form the trenches100T, thereby defining the fin structure100″. The removal process may be similar to the process described inFIG.2. Next, the isolation structure302may be formed in lower portions of the trenches100T as described inFIG.3. In some embodiments, during the formation of the isolation structure302, an anneal process may be performed once the insulation material is deposited. The anneal temperature may cause dopants in the doped region1041D diffusion. By configuring the bottommost second semiconductor layer106having multiple sublayers, the doped region1041D may be confined. In alternative embodiments, the doped region1041D expands during (or after) forming the isolation structure302. For example, the doped region1041D occupies the entire bottommost first semiconductor layer104-31.

Referring toFIGS.25A-25Band with reference toFIGS.4A-4B, the dummy gate structure203and the mask layer204may be sequentially formed on the fin structures100″. The materials and the forming processes of the dummy gate structure203and the mask layer204are similar to those of the dummy gate structure203and the mask layer204described inFIG.4A-4B.

Referring toFIG.26and with reference toFIG.25BandFIGS.5-7, the gate spacer205may be conformally formed on the dummy gate structure203, the mask layer204, and the top of the fin structure100″. Next, the respective fin structure100″ and the semiconductor substrate102′ may be partially removed to form the recesses100R. Next, the first semiconductor layers104exposed by the recesses100R may be removed in the lateral direction (e.g., the Y-direction) to form the respective etched fin structure100having etched first semiconductor layers104′. The forming processes of the gate spacer205, the recesses100R, and the etched first semiconductor layers104′ may be similar to the processes described inFIGS.5-7. After forming the etched first semiconductor layers104′, the doped region1041D may still remain in the bottommost first semiconductor layer104-3′.

With a selective etching process, the doped region1041D in the bottommost first semiconductor layer104-3′ may slow down lateral etching. For example, the bottommost first semiconductor layer104-3′ having the doped region1041D is etched more slowly than the first semiconductor layers without the doped region (e.g.,104-1′ and104-2′). The difference in etch rates may result in the difference in dimensions of the lateral recesses104R and104R′. For example, the dimension of the lateral recess104R′ corresponding to the bottommost first semiconductor layer104-3′ is less than that of the lateral recess104R corresponding to the topmost first semiconductor layer104-1′. The smaller dimension of the lateral recess104R′ may result in the larger size of the bottommost first semiconductor layer104-3′ remained. For example, the lateral dimension L3of the bottommost first semiconductor layer104-3′ is greater than the lateral dimension L1of the topmost first semiconductor layer104-1′ and also greater than the lateral dimension L2of the middle first semiconductor layer104-2′.

Referring toFIG.27and with reference toFIG.26andFIG.8, the inner spacers212(e.g.,212-1,212-2, and212-3) may be formed in the lateral recesses104R and104R′. The material and the forming process of the inner spacers212may be similar to those of the inner spacers described inFIG.8. Since the bottommost first semiconductor layer104-3′ having the lateral dimension L3greater than the lateral dimensions L1and L2of the overlying first semiconductor layers (104-1′ and104-2′), the bottommost inner spacer212-3may have the thickness W3less than the thickness W1of the topmost inner spacer212-1and also less than the thickness W2of the middle inner spacer212-2.

Referring toFIG.28and with reference toFIG.27andFIGS.9-12, the epitaxial structures220may be epitaxially grown in the recesses100R. As mentioned inFIG.9, the respective epitaxial structure220may have different doping levels and may include an undoped region at the bottom, where the undoped regions are illustrated in the dashed lines to indicate they may or may not exist. Next, the first ILD layer306, the etch stop layer304, and the recess306R accessibly revealing the topmost one of the second semiconductor layers106of the respective etched fin structure100may be formed. The materials and the formation processes may be similar to the materials and the processes described inFIGS.10-11. Next, the etched first semiconductor layers104′ may be removed to form the recesses104S (e.g.,104-1S,104-2S, and104-3S). The process may be similar to the process described inFIG.12.

Referring toFIG.29and with reference toFIG.28andFIGS.13-14, the gate structure240may be formed around the second semiconductor layers106and fill the recesses306R and104S. The material and the forming process of the gate structure240may be similar to those of the gate structure240described inFIG.13. Next, the second ILD layer307, the S/D contacts312extending through the second ILD layer307and the first ILD layer306to be coupled to the epitaxial structures220, and the gate contact314extending through the second ILD layer307to be coupled to the topmost gate section240T of the gate structure240may be formed. The front-side interconnect structure320may be formed on the second ILD layer307, the S/D contacts312, and the gate contact314. The materials and the forming process of these features may be similar to those of the corresponding features described inFIG.14.

With continued reference toFIG.29andFIG.14, a semiconductor device30including a device layer301formed in/on the semiconductor substrate102and the front-side interconnect structure320formed on the device layer101is provided. The semiconductor device30is similar to the semiconductor device10illustrated inFIG.14, except for the forming method of the thinner bottommost inner spacer and the longer bottommost gate section. In the illustrated embodiment, by configuring the doped region in the bottommost first semiconductor layer, the lateral recessing of the bottommost first semiconductor layer may be slowed down such that the bottommost inner spacer formed around the bottommost first semiconductor layer may have a smaller thickness as compared to the thickness of the overlying inner spacers. By configuring the thinner bottommost inner spacer212-3, the gate length of the bottommost gate section240-3may be increased and gate-junction overlapping may be improved. This in turn enhances the performance of the semiconductor device30.

FIGS.30-36illustrate schematic cross-sectional views of intermediate steps during a process for forming a semiconductor device, in accordance with some embodiments. It should be noted thatFIGS.30-32Aare cross-sectional views of the structure taken at the X-Z plane,FIG.32Bis a cross-sectional view of the structure illustrated inFIG.32Ataken along the line A-A′, andFIGS.32B and33-36are cross-sectional views taken at the Y-Z plane and illustrating the following steps of forming a semiconductor device. Unless specified otherwise, like reference numerals in this embodiment represent like components in the embodiment shown inFIGS.1-14formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. In addition, althoughFIGS.30-36are described as a series of acts, these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. Alternatively, some acts that are illustrated and/or described may be omitted in whole or in part.

Referring toFIG.30and with reference toFIG.1, the structure shown inFIG.30is similar to the structure shown inFIG.1, except for the bottommost first semiconductor layer104-B. The bottommost first semiconductor layer104-B may have a thickness H3less than a thickness H1of the topmost first semiconductor layer104-1. The thickness H3may be less than a thickness H2of the middle first semiconductor layer104-2, where the thicknesses H1and H2may be substantially equal or may be different. In some embodiments, the bottommost first semiconductor layer104-B is the thinnest layer among the first semiconductor layers104. The thickness of each of the first semiconductor layers104may range from few nanometers to few tens of nanometers. In some embodiments, a difference between the thickness H1of the topmost first semiconductor layer104-1and the thickness H3of the bottommost first semiconductor layer104-B is in a range of about 0.5 nm to about 5.0 nm, although other differences are within the contemplated scope of the disclosure.

Referring toFIG.31and with reference toFIG.30andFIGS.2-3, a portion of the stack of first semiconductor layers104and second semiconductor layers106along with the underlying portion of the semiconductor substrate102′ may be removed to form trenches100T, thereby defining the fin structure100″. The removal process may be similar to the process described inFIG.2. Next, the isolation structure302may be formed in lower portions of the trenches100T as described inFIG.3.

Referring toFIGS.32A-32Band with reference toFIGS.4A-4B, the dummy gate structure203and the mask layer204may be sequentially formed on the fin structures100″. The materials and the forming processes of the dummy gate structure203and the mask layer204are similar to those of the dummy gate structure203and the mask layer204described inFIG.4A-4B.

Referring toFIG.33and with reference toFIG.32BandFIGS.5-7, the gate spacer205may be conformally formed on the dummy gate structure203, the mask layer204, and the top of the fin structure100″. Next, the respective fin structure100″ and the semiconductor substrate102′ may be partially removed to form the recesses100R. Next, the first semiconductor layers104exposed by the recesses100R may be removed in the lateral direction (e.g., the Y-direction) to form the respective etched fin structure100having etched first semiconductor layers104′. The forming processes of the gate spacer205, the recesses100R, and the etched first semiconductor layers104′ may be similar to the processes described inFIGS.5-7. The thinner first semiconductor layer104-B may slow down the lateral etching. For example, the bottommost first semiconductor layer104-B′ having the smallest thickness is etched more slowly than the first semiconductor layers (e.g.,104-1′ and104-2′) having greater thickness. For example, the dimension of the lateral recess104R′ corresponding to the bottommost first semiconductor layer104-B′ is less than that of the lateral recess104R corresponding to the topmost first semiconductor layer104-1′. The lateral dimension L3of the bottommost first semiconductor layer104-B′ may be greater than the lateral dimension L1of the topmost first semiconductor layer104-1′ and also greater than the lateral dimension L2of the middle first semiconductor layer104-2′.

Referring toFIG.34and with reference toFIG.33andFIG.8, the inner spacers212(e.g.,212-1,212-2, and212-3) may be formed in the lateral recesses104R and104R′. The material and the forming process of the inner spacers212may be similar to those of the inner spacers described inFIG.8. Since the bottommost first semiconductor layer104-B′ having the greater lateral dimension L3than the lateral dimensions L1and L2of the overlying first semiconductor layers (104-1′ and104-2′), the bottommost inner spacer212-3may have the thickness W3less than the thickness W1of the topmost inner spacer212-1and also less than the thickness W2of the middle inner spacer212-2.

Referring toFIG.35and with reference toFIG.34andFIGS.9-12, the epitaxial structures220may be epitaxially grown in the recesses100R. As mentioned inFIG.9, the respective epitaxial structure220may have different doping levels and may include an undoped region at the bottom, where the undoped region is illustrated in the dashed lines to indicate it may or may not exist. Next, the first ILD layer306, the etch stop layer304, and the recess306R accessibly revealing the topmost one of the second semiconductor layers106of the respective etched fin structure100may be formed. The materials and the formation processes may be similar to the materials and the processes described inFIGS.10-11. Next, the etched first semiconductor layers104′ may be removed to form the recesses104S (e.g.,104-1S,104-2S, and104-3S). The process may be similar to the process described inFIG.12.

Referring toFIG.36and with reference toFIG.35andFIGS.13-14, the gate structure240may be formed around the second semiconductor layers106and fill the recesses306R and104S. The material and the forming process of the gate structure240may be similar to those of the gate structure240described inFIG.13. The bottommost gate section240-3bmay have a longer lateral dimension and a smaller vertical dimension than the topmost gate section240-1. Next, the second ILD layer307, the S/D contacts312extending through the second ILD layer307and the first ILD layer306to be coupled to the epitaxial structures220, and the gate contact314extending through the second ILD layer307to be coupled to the topmost gate section240T of the gate structure240may be formed. The front-side interconnect structure320may then be formed on the second ILD layer307, the S/D contacts312, and the gate contact314. The materials and the forming processes of these features may be similar to those of the corresponding features described inFIG.14.

With continued reference toFIG.36andFIG.14, a semiconductor device40including a device layer401formed in/on the semiconductor substrate102and the front-side interconnect structure320formed on the device layer401is provided. The semiconductor device40is similar to the semiconductor device10illustrated inFIG.14, except for the size of the bottom gate section and the forming method of the bottommost inner spacer and the bottommost gate section. In the illustrated embodiment, by configuring the thinner bottommost first semiconductor layer, the lateral recessing of the bottommost first semiconductor layer may be slowed down such that the bottommost inner spacer formed around the bottommost first semiconductor layer may have a smaller thickness compared to the thickness of the overlying inner spacers. By configuring the thinner bottommost inner spacer212-3, the gate length of the bottommost gate section240-3may be increased and gate-junction overlapping may be improved. This in turn enhances the performance of the semiconductor device40.

FIGS.37through40illustrate schematic cross-sectional views of variations of a semiconductor device, in accordance with some embodiments. Unless specified otherwise, like reference numerals in this embodiment represent like components in the embodiment shown inFIG.14.

Referring toFIG.37and with reference toFIG.14, the difference between a semiconductor device50shown inFIG.37and the semiconductor device10shown inFIG.14lies in that a device layer501of the semiconductor device50further includes bottom isolation structures250vertically interposed between the semiconductor substrate102and the S/D regions220′ for prevention of leakage. The material of the bottom isolation structures250may include SiN, SiO2, SION, SiCN, SiCON, SiCO, a high-k dielectric (e.g., HfO, AlO, etc.), compounds thereof, composites thereof, and/or combinations thereof. For example, the bottom isolation structures250are formed on the top surfaces102tof the semiconductor substrate102after forming the inner spacers212, and then the epitaxial structures (i.e. the S/D regions)220′ are formed on the bottom isolation structures250.

The bottom isolation structures250may isolate the overlying S/D regions220′ from the underlying semiconductor substrate102. The respective bottom isolation structure250may have a substantially flat top surface250t, and the epitaxial structures220′ formed on the top surfaces250tof the bottom isolation structure250may have a substantially flat bottom surfaces. The respective bottom isolation structure250may partially cover the sidewall of the bottommost inner spacer212-3. For example, the upper portion of the sidewall of the bottommost inner spacer212-3is exposed by the neighboring bottom isolation structures250. Since the bottom isolation structures250exposes at least a portion of the bottommost inner spacer212-3, the removal process of the etched first semiconductor layers104′ as described inFIG.12will not be affected.

With continued reference toFIG.37, lower portions of the bottom isolation structures250may be replaced with undoped epitaxial structures220D (or the epitaxial structures that are substantially dopant-free), in some embodiments. The materials of the bottom isolation structures250and the undoped epitaxial structures220D are different. The undoped epitaxial structures220D may be epitaxially grown on the semiconductor substrate102, and the respective undoped epitaxial structure220D may not extend upward beyond the bottom surface212_3bof the bottommost inner spacer212_3. In some embodiments, the top surface220Dt of the respective undoped epitaxial structure220D is substantially level with the bottom surface212_3bof the bottommost inner spacer212_3as pictured inFIG.37, slightly elevated above the bottom surface212_3b, or slightly below the bottom surface212_3b. The bottom isolation structures250may be formed on the top surfaces220Dt of the undoped epitaxial structures220D and laterally adjoin the bottommost inner spacer212-3.

Referring toFIG.38and with reference toFIG.14, the difference between a semiconductor device60shown inFIG.38and the semiconductor device10shown inFIG.14includes the cross-sectional profiles of the S/D regions620, the bottommost inner spacer212-3T, the bottommost channel layer106-3T, and the middle inner spacer212-2T. In some embodiments, the bottom section of the respective S/D region620laterally protrudes toward the bottommost inner spacer212-3T and the bottommost channel layer106-3T. The sidewalls of the bottommost inner spacer212-3T and the bottommost channel layer106-3T which are coupled to the S/D regions620may be curved/tilted (or concave toward the S/D regions620). In some embodiments, the sidewall of the middle inner spacer212-2T may have a curved lower portion connected to the sidewall of the bottommost channel layer106-3T. The bottommost inner spacer212-3T may have a variable thickness. For example, the minimum thickness W3′ of the bottommost inner spacer212-3T is less than the maximum thickness W2of the middle inner spacer212-2T and also less than the maximum thickness W1of the topmost inner spacer212-1.

In some embodiments, a total lateral dimension TL3of the lateral dimension GL3of the bottommost gate section240-3and two times of the minimum thickness W3′ of the bottommost inner spacer212-3T is less than a total lateral dimension TL2of the lateral dimension GL2of the middle gate section240-2and two times of the maximum thickness W2of the middle inner spacer212-2T. In some embodiments, the total lateral dimension TL3is less than a total lateral dimension TL1of the lateral dimension GL1of the topmost gate section240-1and two times of the maximum thickness W1of the topmost inner spacer212-1. In some embodiments, the difference between the total lateral dimension TL3and the total lateral dimension TL1is less than 0, for example, in a range of about-5.0 nm and about 0 nm.

In some embodiments, before forming the epitaxial structures620, the bottom isolation structures250are formed on the semiconductor substrate102as mentioned inFIG.37. The bottom isolation structures250may be coupled to the curved sidewalls of the bottommost inner spacers212-3T. In some embodiments, the undoped epitaxial structures220D are formed on the semiconductor substrate102-1, and the bottom isolation structures250are formed on the undoped epitaxial structures220D as mentioned inFIG.37. The undoped epitaxial structures220D and the bottom isolation structures250are illustrated in the dashed lines to indicate they may or may not exist.

Referring toFIG.39and with reference toFIG.14, a semiconductor device70is similar to the semiconductor device10shown inFIG.14. For example, the semiconductor device70includes a p-type region (e.g., PMOS)70P and an n-type region (e.g., NMOS)70N. The device layer101P in the p-type region70P may be similar to the device layer101N in the n-type region70N. Dopants in the p-type region70P and dopants in the n-type region70N have different diffusion behavior, bottom leakage, and implantation amount, such that the configurations in the p-type region70P and the n-type region70N may be adjusted due to these factors. For example, the device layer101N includes the bottom isolation structures250interposed between the S/D regions220and the semiconductor substrate102, while the device layer101P is free of the bottom isolation structures250.

In alternative embodiments, the device layer101P includes the bottom isolation structures250interposed between the S/D regions220and the semiconductor substrate102, while the device layer101N is free of the bottom isolation structures250. In alternative embodiments, both of the device layers101P and101N include the bottom isolation structures250interposed between the S/D regions220and the semiconductor substrate102. In other embodiments, both of the device layers101P and101N are free of the bottom isolation structures250. In some embodiments, the lower portions of the bottom isolation structures250are replaced with undoped epitaxial structures220D (or the epitaxial structures that are substantially dopant-free). The bottom isolation structures250and the undoped epitaxial structures220D may be similar to the bottom isolation structures250and the undoped epitaxial structures220D described inFIG.37.

Referring toFIG.40and with reference toFIG.39andFIG.14, a semiconductor device80is similar to the semiconductor device10shown inFIG.14and the semiconductor device70shown inFIG.39. For example, the semiconductor device80includes the p-type region (e.g., PMOS)80P and the n-type region (e.g., NMOS)80N. Dopants in the p-type region70P and in the n-type region70N having different diffusion behavior may require varied requirements of thickness of inner spacers. For example, in the p-type region80, the device layer101P, similar to the device layer101described inFIG.14, may have the bottommost inner spacer212-3thinner than the overlying inner spacers212. The bottommost inner spacer212-3N of the device layer101N′ in the n-type region80N may have a thickness W83different from the thickness W3of the bottommost inner spacer212-3. For example, the thickness W83is greater than the thickness W3. In some embodiments, the thickness W83is substantially equal to the thickness W81of the topmost inner spacer212and the thickness W82of the middle inner spacer212. The lateral dimension of the bottommost gate section240-3N may be substantially equal to that of the overlaying gate sections240. In some embodiments, the lateral dimension of the bottommost gate section240-3N in the n-type region80N is greater than that of the bottommost gate section240-3in the p-type region80P.

In some embodiments, the thickness W2of the middle inner spacer212in the p-type region80P is less than the thickness W82of the middle inner spacer212in the n-type region80N. The thickness W1of the topmost inner spacer212in the p-type region80P may be less than the thickness W81of the topmost inner spacer212in the n-type region80N. In some embodiments, the thickness W83is different from the thickness W82and the thickness W81, and the first difference between the thicknesses W83and the W81in the n-type region80N is different from the second difference between the thicknesses W3and W1in the p-type region80P. For example, the difference between the first difference and the second difference is in a range of about 0.5 nm to about 4.0 nm.

In alternative embodiments, the bottommost inner spacer in the n-type region is thinner than the overlying inner spacers, while the bottommost inner spacer in the p-type region has a thickness substantially equal to the thicknesses of the overlying inner spacers. In alternative embodiments, the bottommost inner spacers in both of the p-type region and the n-type region are respectively thinner than the overlying inner spacers. In some embodiments, the device layer101P/101N′ includes the bottom isolation structures (not shown) interposed between the S/D regions220and the semiconductor substrate102. In some embodiments, the undoped epitaxial structures (not shown) are interposed between the bottom isolation structures and the semiconductor substrate102. In some embodiments, in the p-type region80P (and/or the n-type region80N), the cross-sectional profiles of the S/D regions, the bottommost inner spacer, the bottommost channel layer, and the middle inner spacer may be replaced with the cross-sectional profiles described inFIG.38. In some embodiments, the cross-sectional profiles of these features in the p-type region80P are different from the cross-sectional profiles of these features in the n-type region80N. The cross-sectional profiles may vary depending on process/product requirements.

According to some embodiments, a semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and S/D regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

According to some alternative embodiments, a semiconductor device includes a semiconductor substrate and a device layer disposed on the semiconductor substrate. The device layer includes channel regions vertically stacked upon one another, a gate structure surrounding each of the channel regions, S/D regions disposed on the semiconductor substrate and laterally coupled to the channel regions, and inner spacers laterally separating the S/D regions from the gate structure. The gate structure includes a topmost gate section and a bottommost gate section between the topmost gate section and the semiconductor substrate, and a lateral dimension of the bottommost gate section is greater than that of the topmost gate section.

According to some alternative embodiments, a manufacturing method for a semiconductor device includes forming a fin structure over a semiconductor substrate, where the fin structure includes semiconductor channel layers and semiconductor sacrificial layers alternatively formed on top of one another; laterally recessing the semiconductor sacrificial layers, where after the laterally recessing, a lateral dimension of a bottommost semiconductor sacrificial layer of the semiconductor sacrificial layers is greater than that of a topmost semiconductor sacrificial layer of the semiconductor sacrificial layers; forming inner spacers on sidewalls of the semiconductor sacrificial layers after the laterally recessing, where a bottommost inner spacer of the inner spacers surrounding the bottommost semiconductor sacrificial layer is thinner than a topmost semiconductor inner spacer of the semiconductor sacrificial layers inner spacers surrounding the topmost semiconductor sacrificial layer; forming S/D regions on the semiconductor substrate to be laterally coupled to the inner spacers and the semiconductor channel layers; and replacing the semiconductor sacrificial layers with a gate structure.