Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

FIELD OF THE INVENTION

The present disclosure relates to the field of microelectronics, and more specifically to the design of digital integrated circuits. It more specifically aims at specific arrangements relative to the adjustment of the output impedance of digital ports.

BACKGROUND OF THE INVENTION

Generally, digital components have input and output ports which enable the exchange of signals with neighboring components. As an example, communication between a microprocessor and a random access memory (RAM) may be mentioned.

In the search for high performance, increasing the operating frequency of the processor may be desirable, and thus the frequency of exchanges with neighboring components. At a certain level, the characteristic impedance of the connection between the output of a component and the input of the neighboring component may have an influence on the quality of the transmitted signal. In other words, it may be advantageous for the input or output impedance of an input or output port to be calibrated.

Various specifications exist depending on the technology used, which may set the optimal input or output impedance value, as well as the tolerances. To respect these specifications, it may be desirable to calibrate the output impedance of the concerned output ports, since it may depend on multiple factors. One can, in particular, mention factors associated with the component manufacturing process, or factors capable of varying along with the circuit operation, and in particular, the temperature of use, or the value of the power supply voltage for an autonomous device. Calibration of the output impedance of a digital port has already been provided by selecting an appropriate number of active transistors in a buffer or driver stage between a control terminal of the output signal and the actual output terminal.

SUMMARY OF THE INVENTION

Calibration circuits known to date, ensuring the selective activation of various transistors, may cause parasitic signals on reconfiguration of the buffer stages during a calibration process. It may thus be desirable to allow calibrations at any time of the operating cycle of a circuit while generating the smallest possible amount of disturbance during calibration cycles.

With this in mind, the embodiments thus provide an integrated circuit that includes at least one digital output port that includes at least one stage assembled in parallel. Each buffer stage is connected, on one hand, to a common output signal control terminal and, on the other hand, to the output terminal of this port. Each buffer stage may include at least two subassemblies of at least two MOSFET transistors. That is, each buffer stage may include a first subassembly of at least two transistors called pull-up transistors, having their sources connected to a common high voltage, and having their drains connected to a common node connected to the output terminal. Each buffer stage may also include a second subassembly of at least two transistors called pull-down transistors, having their sources connected to a common low voltage, and having their drains connected to a common node connected to the output terminal of the port.

In other words, the first subassembly may include at least two pull-up transistors and the second subassembly may include at least two pull-down transistors. All the transistors are mounted in parallel between two common nodes. In particular, the drains of the transistors of the first and second subassemblies are connected to the common node connected to the output terminal of the port. The sources of the pull-up transistors are connected to the common high voltage, and the sources of the pull-down transistors are connected to the common low-voltage.

In addition, the transistors are formed in the thin semiconductor layer of an FDSOI-type substrate. This substrate includes a relatively thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. The areas of the thick semiconductor layer facing the transistors are connected to a circuit for adjusting their voltage to vary the threshold voltage of the transistors. In other words, this circuit enables setting, by analog means or circuitry, of the impedance of each of the transistors, by acting on the voltage applied to the back plane or ground plane of the transistor.

Each transistor may be selected via their gate, and the selected transistors are thus mounted in parallel between two common nodes. This approach allows combining a plurality of buffers and a plurality of first and second subassemblies, thus allowing a finer calibration setting.

According to various embodiments the adjustment circuit may be controlled by a comparator stage that includes a voltage divider comprising an external calibration resistor. The adjustment circuit may include a capacitive element having its charge or its discharge controlled by the comparator stage. The adjustment circuit may be controlled by a calibration starting circuit, enabling action of the setting circuit during predetermined periods. Each buffer stage may include a resistive linearization element between the common node to which are connected the sources of the transistors and the output terminal of the output port.

The integrated circuit may also include an activation circuit, capable of selectively connecting the gates of all or part of the transistors of a subassembly to the common output signal control terminal. The integrated circuit may also include a configuration circuit capable of connecting in parallel all or part of the buffer stages.

The present embodiments also provide a method for adjusting the output impedance of a digital output port of an integrated circuit. The port may include one or several buffer stages arranged in parallel, and each connected, on the one hand, to a common terminal for controlling the output signal and, on the other hand, to the output terminal of the port. Each stage may include at least two subassemblies of MOSFET transistors, that is, a subassembly of at least two pull-up transistors having their sources connected to a common high potential, and having their drains connected to a common node connected to the output terminal of the port, and a subassembly of at least two pull-down transistors, having their sources connected to a common low potential, and having their drains connected to a common node, connected to the output terminal.

The transistors may be formed in the thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating said thin and thick semiconductor layers. The voltage of the areas of the thick semiconductor layer may be arranged in front of the transistors and adjusted to set the threshold voltage of each transistor.

According to different alternative executions, all or part of the transistors of each subassembly may be selectively activated by selectively connecting the gate of all or part of the transistors of a subassembly to the common output signal control terminal. All or part of the buffer stages may be selectively connected in parallel.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description will use terms power supply voltage or high voltage, also designated by abbreviations VDD, VDDEor the like, to refer to the same type of high voltage level. Similarly, terms “low-level voltage”, ground, or abbreviations GND, GNDEor the like are equivalent.

As illustrated inFIG. 1, an integrated circuit1includes a plurality of output ports2. Each output port includes several buffer stages3arranged in parallel, and which are all connected to a common terminal4for controlling the output signal. The terminal4is typically connected to a core portion of the integrated circuit. These different stages3are also all connected to output terminal5connecting integrated circuit1to the neighboring components.

In the illustrated embodiment, each output stage3includes a plurality of transistors10,11,12,20,21,22, which enable connection of the output terminal5to the high voltage or to the low voltage, according to output signal4. In practice, the different transistors of a buffer stage have different characteristics enabling coverage of the widest desired impedance range with the appropriate combinations. Thus, as an example, the transistors may have increasing gate widths having their values doubling from one transistor to the other to be able to use a binary selection mode. Of course, other configurations may be envisaged with different distributions of the characteristics of the different transistors.

More specifically, part of these transistors10,11,12, enable connection of the output terminal5to a high voltage, typically, a power supply voltage VDDE. Such pMOS-type transistors have their drains all connected to a common node30, itself connected to the output terminal5via a linearization resistor31.

Other transistors20,21,22may be complementary transistors, that is, nMOS, and have their sources connected to a low potential node GNDE, while their drains are all connected to the common node30, also having the drains of the other pull-up transistors connected thereto.

In the embodiment ofFIG. 1, the output port includes a linearization resistor31, which is used to make the voltage-vs.-current characteristic of the output port more linear. However, in certain configurations, the linearization resistor may be omitted.

The gate of each of these transistors is connected to logic gates enabling to apply the voltage present on control terminal4thereto, according to configuration signals. More specifically, pull-up transistors10,11,12have their gates connected to gates60,61,62having an inverting output and which provide a logic “and” between the signal originating from control terminal4and a configuration signal40,41,42. In other words, when configuration signal40,41,42is at a high level, transistors10,11,12are in the off state, whatever the value of the signal originating from the control terminal4. Thus, transistors10,11,12are deactivated. Conversely, when configuration signal40,41,42is at a low level, transistors10,11,12switch to the on or off state when the signal originating from the control terminal4is respectively in the high or low state.

Complementarily, the nMOS-type pull-down transistors have gates controlled by an inverting “or” gate70,71,72having an input connected to the control terminal4. The other terminal is connected to a configuration signal50,51,52. Similarly, when the configuration signals50,51,52are in a low state, transistors20,21,22are off, whatever the state of the control signal4. However, when the configuration signals50,51,52are at a high level, transistors20,21,22are on or off when the signal from the control terminal4is respectively low or high.

In the illustrated embodiment, the different buffer stages3are identical, and the control signal for activating their different transistors is also identical so that the different stages are electrically connected in parallel. The general output impedance of the output port thus corresponds to the impedance of a stage divided by the number of stages arranged in parallel. According to an appropriate control of the activation of the different transistors of the stages arranged in parallel, it may be possible to modulate the number of stages arranged in parallel, and thus the value of the general output impedance of the port according to the value required by the application.

Transistors10,11,12,20,21,22of the output ports are formed from FDSOI-type substrates. Thus, as illustrated inFIG. 2, the pull-down transistor100is formed in a thin layer101of the FDSOI substrate. The thin semiconductor layer101is supported by an oxide layer102, which separates the thin layer101from a thick layer103. Thus, the transistor100may be totally insulated by the oxide layer102from the rest of the substrate103. In contrast to the transistor100, the thick layer103has, in contact with the oxide layer102, an area forming a ground plane or back plane106, and having a voltage capable of being controlled through an analog doping well107at the level of terminal108. It should be noted that for an nMOS-type transistor, it may thus be preferable to provide a deep insulation well109which is itself set to the high voltage by the terminal110to reverse-bias the PN junction formed with the well107, and thus reduce the chances of the substrate from being at the potential of the terminal108.

For the pull-up transistors150illustrated inFIG. 2, a ground plane area156may also be set to a variable voltage to vary the threshold voltage of the transistor150. For this purpose, an N-doped well107enables setting of the ground plane156to a variable voltage, higher than the ground, via a terminal158. It should be noted that it is desirable that the rest of the substrate120be maintained at the low voltage via the terminal160to reverse-bias the PN junctions between the rest of the substrate and the N well107at the variable voltage.

In such a configuration, the ground plane106of the pull-down transistor may be taken to a potential ranging up to the voltage of the VDD power supply. This configuration, however, enables the application of a reverse voltage, lower than GND for the pull-down transistor100, and higher than VDD for the pull-up transistor150corresponding to a configuration slowing down the transistor performances.

FIG. 3illustrates an alternative configuration where the pull-down transistor200has an N-doped ground plane206, which is placed into contact with the terminal208of the application of the variable potential via a well207, also N-doped. The maintaining of the rest220of the substrate at a potential equal to GND enables reverse-biasing of the PN junction between the rest of the substrate220and the well207.

In such a configuration, for the pull-up transistor250, the area256forming the ground plane may be maintained at a variable potential, adjustable via the terminal258connected by a P-doped well257. To insulate the well257from the rest of the substrate220, a deep well259is formed and is maintained at a relatively high potential to reverse-bias the PN junction existing with the P well257, and the junction existing with the rest of the substrate220.

In such a configuration, the voltage which may be applied to the back plane of the pull-down transistor200may be higher than the like in the example ofFIG. 2, which enables acceleration of the transistor for obtaining better dynamics. The same can be observed for the pull-up transistor250with a ground plane which may be substantially lowered, and in particular, below the zero potential to increase the corresponding effect.

As illustrated inFIG. 1, the terminals enabling setting of the potential of the ground planes of the different pull-up and pull-down transistors are controlled by an adjustment circuit integrated in a circuit for calibrating the impedance of the output port. Similarly, the orders of activation40,41,42,50,51,52of the different transistors are also controlled by this circuit for calibrating the impedance.

An embodiment of such a circuit is described in simplified manner inFIG. 4. Specifically, in the illustrated embodiment, the calibration circuit300includes a first area301corresponding to a replica of the assembly of the pull-up transistors10-12and the linearization resistor31. Thus, the pull-up transistors of circuit301are directly controlled by codes310.

At output302of the linearization resistor, the circuit is connected to an external calibration resistor304which may have a value determined by the specifications of the technology used. For example, for standard LPDDR 2, it may be desirable for the impedance of the output ports to be 34.3Ω±15%. Still, as an example, when the output port includes seven stages in parallel, it may be desirable that each stage have a nominal individual impedance of 240Ω. By modulating the number of stages placed in parallel, it may thus be possible to program the total impedance to 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, 34.3Ω by selecting the adequate number of stages, individually calibrated to 240Ω.

The external calibration resistor304is thus selected with this value so that the output terminal302of the circuit301replicating of the assembly of pull-up transistors to be half the power supply voltage. For this purpose, an controller350scans the different possible combinations of activation codes310of the transistors. The output voltage of the replica circuit301is sampled to be compared by a comparator308to half the high power supply voltage307. The result of the comparison is sent to the controller350to determine the optimal combination of activation codes for obtaining an impedance of the front assembly of pull-up transistors301, which may be as close as possible to the external calibration resistance304.

For the pull-down transistors, the calibration is performed by using two replica circuits, that is, on the one hand, a circuit320replicating the set of pull-up transistors and, on the other hand, a circuit330replicating the set of pull-down transistors.

The transistors of the circuit320replicating the pull-up transistors are controlled by activation codes311equal to codes310determined for the above-mentioned replica circuit301. The same logic is applied to the set of pull-down transistors of the replica circuit330, which are controlled by a set of activation codes321also controlled by the controller350.

Midpoint340of the outputs322,332of the circuits320,330replicating the pull-down and pull-up transistors is measured and compared with half the power supply voltage by comparator358. Comparator358delivers the results359of the comparison to the controller350to have it determine the optimal code for the voltage of midpoint340to be as close as possible to half the power supply voltage.

This phase of digital calibration, by the selective application of a number of pull-up and pull-down transistors, may be completed by an adjustment of the resistance of each of the transistors by action on the potential applied to the ground plane such as discussed above. More specifically, and as illustrated inFIG. 4, the calibration circuit300includes an adjustment stage400, which enables application of an adjustable voltage on the ground plane and the pull-up transistors.

More specifically, and as illustrated inFIG. 4, the adjustment circuit400includes a switch401controlled by the controller350. This switch enables connection of the common terminal408of the different ground planes of the transistors of replica circuit301either to a fixed value405, in particular, during initialization phases, and in particular during the adjustment of the different activation codes40,42,50,52, or to a variable value406determined by the adjustment circuit410, which will be described in further detail below. The adjustable voltage406is determined according to the comparison of the output voltage302of the replication circuit with half the value of the power supply voltage.

The same line of reasoning applies for the circuit330replicating the pull-down transistors with a terminal458common to the different ground planes of these transistors and which is selectively connected by the switch451controlled by the controller350, between a fixed voltage455for initialization phases, and a variable voltage456determined by analog adjustment circuit450. Similarly, the voltage of the junction point340of the circuits320,330replicating the pull-up transistors and the pull-down transistors is measured and compared with half the power supply voltage to enable the adjustment circuit450to accordingly modify the adjustable voltage456.

The circuit460for adjusting the variable voltage applied to the ground planes of the pull-up transistors is illustrated inFIG. 5. Thus, at its input, this circuit receives, on the one hand, a signal501representative of an order for starting a calibration phase and, on the other hand, result502of the comparison of the voltage of the output of the circuit replicating the pull-up transistors with half the power supply voltage. Thus, the signal501for controlling the calibration phases can take a zero value outside of the calibration phases, and a value equal to 1 during the calibration phases.

Similarly, the comparison signal has a value equal to 0 or 1 according to whether the output voltage of the replica stage301is greater or lower than half the power supply voltage. The first stage510of the adjustment circuit400delivers two signals505,506to a second stage520, formed of two multiplexers having a common terminal, and further connected, for one,521, to the high potential and, for the other,522, to the low potential.

The first multiplexer521generates a signal524which controls a transistor535enabling raising of the voltage across buffer capacitance550, itself connected to the different ground planes of the pull-up transistors of replica circuit301via the switch401illustrated inFIG. 4. The second multiplexer522delivers a signal525which controls a charge pump538which, on the contrary, enables decreasing of the voltage across the capacitance550when it is activated.

To return to the first stage, the signal505takes a 1 or 0 value according to whether the voltage to be applied to the ground plane is to be increased or decreased to obtain the optimal output resistance. The second signal506makes the two multiplexers521,522of the second stage520active or blocks them. Thus, when a rising edge is detected on the control signal501of a calibration phase, the state of the comparison signal502is set to be applied to the common terminals of the two multiplexers521,522. The second signal506is then set to 0, which starts the calibration process550either by increasing or decreasing the voltage across the buffer capacitance, which corresponds to the voltage applied to the different ground planes.

When a state switching is observed on the comparison signal502, the targeted impedance has been reached. Accordingly, the control signal506of the multiplexers switches state by switching to a high value, which stops the analog calibration phase.

The following truth table summarizes the different possible configurations.

FIG. 6illustrates a diagram450similar to that ofFIG. 5, adapted to control the adjustable voltage of the ground planes of the pull-down transistors. The difference may essentially lie in the use of a charge pump638to raise the voltage in the capacitance650across which the voltage applied to the ground plane can be found.

FIG. 7illustrates a simplified algorithm of operation of the calibration circuit. Thus, after a phase701of starting the integrated circuit, a first phase of digital calibration of the impedance of the assembly of pull-up transistors702is first carried out by determining the optimal set of configuration codes to activate the transistors to obtain an impedance as close as possible to the desired impedance.

During first phase702, the voltage applied to the ground planes of the pull-up transistors is maintained at an initialization value VBBinit. In the specific embodiment corresponding to the configuration ofFIG. 3, where the ground plane voltage of the pull-up transistors may be adjusted between −VDDE and +VDDE, VBBinit is equal to GNDE. More generally, VBBinit may be selected as the midpoint between the limiting voltages applicable to the ground plane. This enables, after a digital calibration to compensate for the effects on the impedance due to the manufacturing process, as much amplitude in one direction as in the other to compensate for impedance variations due to phenomena such as temperature or the value of the power supply voltage.

At a subsequent step703, the digital calibration of the pull-down transistors is performed as mentioned above by maintaining the ground plane voltage of the pull-down transistors at an initial value, for example, selected as the midpoint of the possible excursion. In the case of the configuration ofFIG. 3, the voltage applicable to the ground planes of the pull-down transistors may vary between GNDE and 2xVDDE, so that the initial value is selected to be VDDE.

It may be chosen to no longer act on the different activation codes of the transistors of each of the stages to limit jitter phenomena which might occur based upon modifications of the activation codes, in particular of large-weight activation codes. The system thus provides a self-calibration of the impedance only by the analog adjustment705of the voltage applied to the ground planes of the pull-up transistors, and then of the pull-down transistors,706. Both calibrations705,706may be performed regularly, with no impact or at least a limited impact on signal transmission, since the impedance characteristics of the concerned stage vary continuously. Thus, the starting of a new calibration phase by analog means or circuitry705,706may be triggered after a settable delay708, and if desirable, a monitoring704of the temperature and/or of the power supply voltage.

Based upon the foregoing, an integrated circuit that includes such a mechanism for adjusting its output impedance may have a better impedance tuning sharpness, since this tuning is performed continuously or no longer discretely. Further, this adjustment may occur more frequently than for a simple digital adjustment, since it generates but little disturbance on signal transmission.

Although a combination of two digital and analog adjustments has been described, the above-described principle may apply to systems where the impedance setting is performed by analog means or circuitry only by adapting the impedance range. Similarly, in certain applications a single pull-up or pull-down transistor per stage may be used, with an accordingly modified impedance excursion.