Low-area, wide range clocking scheme using inductance/capacitance oscillators

An oscillator comprising a first oscillator circuit having a first inductive portion, a plurality of shared switches for selectively connecting a shared oscillator tuning circuit and a second oscillator circuit having a second inductive portion, the plurality of shared switches and the shared oscillator tuning circuit. In some embodiments, when the first oscillator circuit is active, the second oscillator circuit is inactive to allow the sharing of the shared oscillator tuning circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS-CLAIM OF PRIORITY

The present application claims priority to Indian Provisional Application No. 202141038433, filed Aug. 25, 2021, entitled “Low-Area, Wide Range Clocking Scheme using LC Oscillators”, which is herein incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to integrated circuit design and more particularly to designs for oscillators within an integrated circuit.

BACKGROUND

Semiconductor Integrated-Circuits (ICs) are used in most of the electronic equipment being designed today. Many of these ICs have clocks that are an essential component of the design. Examples of circuits in which clocks play a key role include Serializer/Deserializer (SerDes) circuits, central processing units (CPUs), graphics processing units (GPUs), memory devices and generally in communication circuits that transmit or receiving data. Several of these applications require clocks to be generated over a relatively wide frequency range and with relatively low noise. Inductance/Capacitance (LC) oscillators are preferred for generating clocks with low noise, but LC oscillators require a large amount of area.

DETAILED DESCRIPTION

A relatively large area is required for an Inductance/Capacitance (LC) oscillator. This makes it difficult to put as many oscillators on the same integrated circuit (IC) chip as are sometimes required to generate clocks over a wide range of frequencies. Several LC oscillator architectures appropriate for use in IC designs that require a relatively wide operational frequency range and that can be fabricated in a relatively small area on an IC chip are disclosed. In accordance with some embodiments, multiple LC oscillator circuits are fabricated in a small area by fabricating inductors of the different oscillator circuits in a closed area. In addition, elements of the various oscillator circuits are shared. In accordance with some embodiments, only one oscillator circuit is active at a time. Accordingly, the active oscillator circuit can use all of the shared elements without impacting the inactive oscillator circuits with which the elements are shared.

In some embodiments, the area required for the disclosed wide frequency range LC oscillator is essentially the same as the area required for a conventional oscillator having only one oscillator circuit. This is true without regard for the number of oscillator circuits provided within the disclosed wide frequency range LC oscillator. Accordingly, multiple oscillator circuits within the area of a single oscillator provide a desired wide operational frequency range without facing an area penalty. As a result, each oscillator circuit can operate over a smaller range of frequencies. This reduces the power consumption when operating any one of the oscillator circuits, allowing the disclosed wide frequency LC oscillator to operate with a relatively low power requirement.

FIG.1is a simplified schematic diagram of an LC oscillator100. The oscillator has an inductive portion102. The inductive portion102is coupled to a cross-couple circuit104comprising a cross-coupled pair.FIG.2is a simplified schematic of one example of a cross-couple circuit104. The gate202of a first FET204is coupled to the drain206of a second FET208. Similarly, the gate210of the second FET208is coupled to the drain212of the first FET204. The cross-couple circuit104has a negative impedance looking in. Accordingly, when placed in parallel with the inductive portion102of the LC oscillator100, the negative impedance of the cross-couple circuit104is matched to the inductance of the inductive portion102at the highest possible resonant frequency of the LC oscillator100. That is, with no other capacitive impedance placed in parallel with the inductive portion102, the oscillator will oscillate at a resonant frequency of:1/√{square root over (LC)}: where L is the inductance of the inductive portion102; andC is the capacitance of the cross-couple circuit104.

An oscillator bias105is provided to entice the oscillator100to oscillate. It can be seen that by placing an oscillator tuning circuit107in parallel with the inductance L, and selecting the oscillator tuning capacitance, the frequency of the oscillator100can be decreased. For example, in some embodiments, oscillator tuning circuit107comprising a set of capacitance selection circuits, such as digitally switched capacitances (DSCs)106, can be selectively placed in parallel with the inductive portion102and with the cross-couple circuit104. Four such DSCs106a,106b,106c,106dare shown, however, more or less such DSCs106may be present the oscillator100. It should be noted that throughout this document, elements shown in the figures having a reference with a numeric portion followed by an alphabetic portion, such as106a, are essentially identical to other elements having the same numeric portion, but with a different alphabetic portion. For example, the DSC106ais essentially the same as the DSC106b. Furthermore, a group of such identical elements may be referenced by the numeric portion alone. Thus, the group of DSC106a,106b,106c,106dmay be referenced simply as106.

FIG.3is a simplified schematic of one example of a DSC106. A capacitor302and a shared switch304are coupled in parallel within the DSC106. Accordingly, when the shared switch304is closed, the capacitor302is placed in parallel with the inductive portion102. When the shared switch304is open, the capacitor302is disconnected from the inductive portion102, reducing the amount of capacitance that is in parallel with inductive portion102. In some embodiments, a CVC (continuously variable capacitance)108is selectively placed in parallel with the inductive portion102.

FIG.4is a simplified schematic of one example of a CVC108implemented with a varactor402coupled in series with a shared switch404. The varactor402is controlled by a continuously variable control voltage (not shown for the sake of simplicity). Similar to the DSC106, closing the shared switch404places the varactor402in parallel with the inductive portion102. Opening the shared switch404disconnects the varactor402from the inductive portion102.

By altering the reactance (e.g., capacitance) of the oscillator600by adjusting the capacitance of an oscillator tuning circuit107(i.e., adjusting capacitance selection circuits, such as DSC106and CVC108, the frequency of the oscillator can be selectively tuned. It should be understood that other components may also be selectively coupled to inductive portion102to alter the frequency of the oscillator100.

The physical length of the oscillator100(as indicated by the double-headed arrow110) can be measured from the distal most point of oscillator bias105to the proximal most point of the oscillator tuning circuit107. The physical width of the oscillator100can be measured as the distance from one end of the oscillator100along an axis perpendicular to the length to the other end of the oscillator100, as indicated by the double-headed arrow112. In some embodiments, the inductive portion102defines the width. In other embodiments, the edges of the oscillator tuning circuit107define the width of the oscillator100, depending upon which extends further in a direction perpendicular to the length.

In some cases, the frequency range that can be attained with such an LC circuit is limited to a smaller range than is required for a particular IC design. In some such cases, the oscillator is provided that has two oscillator circuits. The first oscillator is designed to oscillate in a relatively lower range and the second oscillator is designed to oscillate in a relatively higher range. Accordingly, the particular oscillator that is capable of operating in the frequency range desired is coupled to a clock output port and the other oscillator is disconnected or may be used as a second clock source.

FIG.5is a simplified illustration of an oscillator500having two oscillator circuits100a,100b, each similar to the oscillator100ofFIG.1. The height of the oscillator500remains approximately the same as the oscillator100. However, the width of the oscillator500is at least twice that of the oscillator100. While this approach accomplishes the goal of extending the range of the oscillator500beyond what is possible with either the first or second oscillator circuit alone, the amount of real estate required is difficult to provide in some designs.

FIG.6is an illustration of an oscillator600having two oscillator circuits (dual oscillator circuit). The first oscillator circuit comprises a first inductive portion602and the second oscillator circuit comprises a second inductive portion604. Each of the inductive portions602,604has a different value of inductance. Thus, each oscillator circuit can be tuned to frequencies that lie within different frequency ranges. In some embodiments, such as the embodiment shown inFIG.6, the inductive portions602,604are interleaved. In addition, the oscillator600has three shared switches606that are shared between a first and second oscillator circuit. In some embodiments, the shared switches606are each single pole, double throw switches in which one throw is open when the other is closed. The shared switches606select which oscillator circuit will be active and which oscillator circuit will be inactive by connecting one of the two inductive portions602,604to a shared oscillator bias608and a shared oscillator tuning circuit107. The first shared switch606aconnects the active inductive portion602to a shared oscillator bias608. The second shared switch606bconnects a proximal end610of the active inductive portion602to a first oscillator port109of the shared oscillator tuning circuit107. The third shared switch606cselects the distal end614,616of the active inductive portion602to be connected to a second oscillator port111of the shared oscillator tuning circuit107. The three shared switches606are switched together to: (1) select one of the two inductive portions602,604as the active inductive portion602, (2) apply an oscillator bias608to the active inductive portion602, (3) place a cross-couple circuit620between the proximal end610and the distal end614of the active inductive portion602, and (4) further place the shared oscillator tuning circuit107in parallel with the cross couple circuit620. Accordingly, when the first oscillator circuit is active, it comprises the shared oscillator bias608, the shared switches606, the inductive portion602, the cross-couple circuit620and the shared oscillator tuning circuit107.

As shown inFIG.6, the first inductive portion602is completely contained within the footprint of the second inductive portion604. Accordingly, a relatively small amount of additional real estate is required to fabricate the dual oscillator circuit600. Furthermore, it will be understood that additional such inductive portions (not shown) could be nested within the footprint of the first inductive portion602. In such case, additional throws would be present in the shared switches606to allow the additional inductive portions to be properly connected to activate those portions when the oscillator is running with those portions providing the desired inductive reactance to affect the frequency of the output of the oscillator600.

FIG.7is an illustration of the oscillator600when the shared switches606change to cause the inductive portion602to become inactive and the inductive portion604to become active. That is, shared switch606achanges to disconnect the oscillator shared bias608from the formerly active inductive portion602and connect the oscillator bias608to the newly active inductive portion604. Similarly, the shared switches606b,606cchange to disconnect the shared cross-couple circuit620and the shared oscillator tuning circuit107from the formerly active inductive portion602and place them in parallel with the newly active inductive portion604. Accordingly, when the second oscillator circuit is active it comprises the shared oscillator bias608, the shared switches606, the inductive portion604, the cross-couple circuit620and the shared oscillator tuning circuit107.

In some embodiments, all of the contacts of the shared switches606may be opened to de-activate both of the inductive portions602,604.

FIG.8is an illustration of an oscillator700having a shared oscillator tuning circuit107and shared oscillator bias608, but with independent cross-couple circuits720,722to be used with each of the oscillator circuit. Accordingly, when the first oscillator circuit is active, it comprises the shared oscillator bias608, the shared switches606, the inductive portion602, a first cross-couple circuit720and the shared oscillator tuning circuit107. When the second oscillator circuit is active it comprises the shared oscillator bias608, the shared switches606, the inductive portion604, the cross-couple circuit620and the shared oscillator tuning circuit107.

FIG.9is an illustration of an oscillator900similar to the oscillator800. However, a separate oscillator tuning circuit901having various DSCs906and CVCs908is provided for each oscillator circuit.

FIG.10is an illustration of an oscillator1000similar to the oscillator900, however, a separate oscillator bias circuit1002,1004is provided for each of the two oscillator circuits.