Host interface controller and control method for storage device

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of China Patent Application No. 201510902677.9, filed on Dec. 9, 2015, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a host interface controller, and in particular relates to a host interface controller that is coupled to a central processing unit and retrieves data from a storage device.

Description of the Related Art

A storage device may be connected to a host via a communication interface. A host interface controller corresponding to the communication interface is required on the host side, which is operated by a central processing unit of the host for data access of the storage device via the communication interface.

A host interface controller with high efficiency is called for.

BRIEF SUMMARY OF THE INVENTION

A host interface controller in accordance with an exemplary embodiment of the disclosure has a control module, a first buffer set, a second buffer set, and a buffer mode setting register. The first buffer set and the second buffer set temporarily store data read from a storage device to respond to read requests from a central processing unit. During a start-up procedure, the buffer mode setting register is switched based on whether a cache memory of the central processing unit has started up or not. When the cache memory has not started up, the first buffer set and the second buffer set operate in a cache memory mode to respond to read requests that the central processing unit repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the central processing unit issues for data of sequential addresses of the storage device.

A control method for a storage device in accordance with an exemplary embodiment of the disclosure comprises the following steps: providing a first buffer set and a second buffer set within a host interface controller between a storage device and a central processing unit to temporarily store data read from the storage device to respond to read requests issued from the central processing unit; when a cache memory of the central processing unit has not started up during a start-up procedure, operating the first buffer set and the second buffer set in a cache memory mode to respond to read requests that the central processing unit repeatedly issues for data of specific addresses of the storage device; and, when the cache memory of the central processing unit has started up during the start-up procedure, operating the first buffer set and the second buffer set in a ping-pong buffer mode to respond to read requests that the central processing unit issues for data of sequential addresses of the storage device.

The disclosure effectively improves the boot up of a computer system.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1depicts a computer system100in accordance with an exemplary embodiment of the disclosure, which includes a central processing unit CPU, a host interface controller102and a storage device104. The central processing unit CPU comprises a cache memory (which is a high-speed buffer)106and is further coupled to a dynamic random access memory (DRAM)108. The storage device104stores read-only memory code ROM_Code. The host interface controller102includes a control module112, a buffer mode setting register110, a first buffer set B1, a second buffer set B2, a first register set R1, a second register set R2, a multiplexer Mux and a comparator Comp.

The first buffer set B1and the second buffer set B2are provided to reduce the system load caused by the host interface controller102that frequently outputs commands for data of the storage device104. In an exemplary embodiment, the communication interface is a serial peripheral interface (SPI), and the corresponding host interface controller102has to output a read command consisting of one byte and a read address consisting of three bytes to read one batch of data from the storage device104. The data length of the batch of data read from the storage device104is controlled by the host interface controller102. Following the read command issued by the host interface controller102to read data from the storage device104, the read address consisting of three bytes only indicates a start address but is silent about the end address. The host interface controller102may decide the end address itself. In this disclosure, because of the first buffer set B1and the second buffer set B2being provided within the host interface controller102, the batch of data read by the host interface controller102from the storage device104may be a large amount of data and is not limited to the data length requested in the read request issued from the central processing unit CPU. Thus, the host interface controller102does not need to frequently output read commands to read the storage device104. A large amount of data of the storage device104is pre-fetched and buffered in the first and the second buffer sets B1and B2by the host interface controller102to respond to the read requests issued from the central processing unit CPU.

Corresponding to the first buffer set B1and the second buffer set B2, the first register set R1, the second register set R2, the multiplexer Mux and the comparator Comp are provided to check whether the data of the storage device104requested by the central processing unit CPU has been pre-fetched and buffered in the first or second buffer set B1or B2.

Note that, during a start-up procedure, the control module112adaptively switches the operation mode of the first and second buffer sets B1and B2depending on what data of the storage device104is requested by the central processing unit CPU. The operation mode of the first and second buffer sets B1and B2is set through the buffer mode setting register110. It is not intended to limit the disclosure to the start-up procedure. Once the storage device104is accessed in several stages with various levels of read address continuity, the operation mode of the first and second buffer sets B1and B2may be adaptively changed in accordance with the techniques of the disclosure.

During a start-up procedure, the central processing unit CPU operates in three stages. In the first stage, the cache memory106and the DRAM108have not started up. The central processing unit CPU frequently repeats reading the read-only memory code ROM_Code of specific addresses. Because the cache memory106has not started up, in response to the read requests from the central processing unit CPU, a conventional host interface controller has to repeatedly output read commands of the same addresses to read the storage device104, which results in low efficiency. In the second stage, the cache memory106has started up and the central processing unit CPU issues mostly read requests of sequential addresses. In the third stage, the DRAM108has also started up, the central processing unit CPU requests to move the read-only memory code ROM_Code to the DRAM108in bulk. Because the central processing unit CPU is outputting read requests of contiguous and non-repeated read addresses in the third stage, the data stored in the cache memory106usually does not hit the read requests from the central processing unit CPU. A conventional host interface controller has to output read commands separately for every read request issued from the central processing unit CPU. For example, a conventional SPI controller has to output one read command consisting of one byte and a read address consisting of three bytes to access the storage device104for every read request. In summary, the read requests usually request data of repeated addresses before the cache memory106starts up. After the cache memory106starts up, the read requests mostly request to read data of sequential addresses.

During the start-up procedure, the buffer mode setting register110is set according to whether the cache memory106of the central processing unit CPU has started up or not. In the first stage which is before the cache memory106starts up, the first and second buffer sets B1and B2operate in a cache memory mode to cope with the repeated read requests that the central processing unit CPU issues to access the same data from the storage device104. In the second and third stages (or just the third stage) which are after the cache memory106starts up, the first and second buffer sets B1and B2operate in a ping-pong buffer mode to cope with the sequential read requests issued from the central processing unit CPU to access data of continuous addresses. In the cache memory mode, the control module112uses the first buffer set B1and the second buffer set B2to cache the data which is read from the storage device104in a data length of several line buffers of the first and second buffer sets B1and B2. Referring toFIG. 1, the first buffer set B1and the second buffer set B2each comprise eight line buffers. As shown, the first buffer set B1includes line buffers Data_DW0 to Data_DW7, the second buffer set B2includes line buffers Data_DW8 to Data_DW15. In this example, the size of each line buffer is four bytes and the size of the first and second buffer sets B1and B2is 64 bytes because the address range to be repeatedly read is about 64 bytes during the first stage of the start-up procedure. The central processing unit CPU outputs read requests each requesting for read data of four bytes, for example, but it is not limited thereto. In the cache memory mode of the exemplary embodiment, the data length requested by each read command that the control module112issues to read the storage device104has not to be limited to four bytes and may be in the size of multiple line buffers of the first and second buffer sets B1and B2. For example, the data length requested by a read command that the control module112issues to read the storage device104may be four bytes, or eight bytes, or 16 bytes. A register (not shown) may be provided within the host interface controller102to set the data length requested by each read command of the host interface controller102. There is no need to frequently output read instructions (including a read command consisting of one byte and a read address consisting of three bytes) to access the storage device104. Instead, multiple line buffers of data may be read from the storage device104at a time. In the ping-pong buffer mode, the control module112alternately uses the first buffer set B1and the second buffer set B2as a pre-fetch buffer set to buffer the sequential data pre-fetched from the storage device104. For example, when one buffer set between the first buffer set B1and the second buffer set B2plays the role of a pre-fetch buffer set, the control module112pre-fetches and buffers sequential data starting from a first address of the storage device104into the pre-fetch buffer set, and accesses the other buffer set and uses the data stored in the other buffer set between the first buffer set and the second buffer set B1and B2to respond to a read request that the central processing unit CPU issues to access data of a second address of the storage device104. It is noted that the data stored in the other buffer set between B1and B2are data previously pre-fetched and buffered by the other buffer set when it played the role of the pre-fetch buffer set previously. In an exemplary embodiment, the rule to select the pre-fetch buffer set comprises: when the sequential read operation going to the first line buffer Data_DW8 of the second buffer set B2, switching to use the first buffer set B1as the pre-fetch buffer set to buffer the data that is pre-fetched from the storage device104from an address sequential to the address of the data buffered in the last line buffer Data_DW15 of the second buffer set B2; and when the sequential read operation going to the first line buffer Data_DW0 of the first buffer set B1, switching to use the second buffer set B2as the pre-fetch buffer set to buffer the data that is pre-fetched from the storage device104from an address sequential to the address of the data buffered in the last line buffer Data_DW7 of the first buffer set B1. A sequential read operation means that the central processing unit CPU is requesting to read an address sequential or continuous to the address requested by a previous read request. In some exemplary embodiments, when operating the buffer sets B1and B2in the ping-pong buffer mode, the data length read from the storage device104every time the control module112issues a read command to access the storage device104is controlled by the control module112itself. For example, when it is required to terminate the pre-fetching operation, the control module112ends pre-fetching and buffering data into the pre-fetch buffer set itself without depending on the any register (but it is not limited thereto).

In this paragraph, the operations of the first register set R1, the second register set R2, the multiplexer Mux and the comparator Comp are discussed. In an exemplary, non-limiting embodiment, the central processing unit CPU outputs each read request (e.g. each C2P request) with a read address C2P_Addr[23:0] of 24 bits to read data of four addresses (e.g. to read four bytes of data). Corresponding to the first buffer set B1, the first register set R1stores address information DW0_Addr[23:6] to DW7_Addr[23:6] (e.g. the high address bits) about the data Data_DW0 to Data_DW7 stored in the first buffer set B1. Corresponding to the second buffer set B2, the second register set R2stores address information DW8_Addr[23:6] to DW15_Addr[23:6] (e.g. the high address bits) about the data Data_DW8 to Data_DW15 stored in the second buffer set B2. The first and second buffer sets B1and B2form a table indexed by the low address bits DW0_Addr[5:2] to DW15_Addr[5:2] of the data Data_DW0 to Data_DW15 stored in the first and second buffer sets B1and B2. Regarding the low address bits C2P_Addr[5:2] requested in the read request issued from the central processing unit CPU as a target index n, the multiplexer Mux outputs reference high address bits DWn_Addr[23:6] selected from the first and second register sets R1and R2. The comparator Comp compares the reference high address bits DWn_Addr[23:6] with the high address bits C2P_Addr[23:6] of the read address. When the reference high address bits DWn_Addr[23:6] match the high address bits C2P_Addr[23:6] of the read address, the comparator Comp outputs ‘H’ to represent that the data requested by the central processing unit CPU has been pre-fetched and buffered in the first or second buffer set B1or B2. When the reference high address bits DWn_Addr[23:6] do not match the high address bits C2P_Addr[23:6] of the read address, the comparator Comp outputs ‘M’ to represent that the data requested by the central processing unit CPU has not been pre-fetched and buffered in the first or second buffer set B1or B2. When the data of the read address requested by the central processing unit CPU has been pre-fetched and buffered in the first or second buffer set B1or B2, the control module112returns the line of data pre-fetched and buffered in the first and second buffer sets B1and B2according to the target index n (i.e. C2P_Addr[5:2]) to respond the central processing unit CPU.

FIG. 2is a flowchart depicting how the first and second buffer sets B1and B2operated in the cache memory mode work when the central processing unit CPU outputs a read request. In step S202, a read address C2P_Addr[23:0] requested by the central processing unit CPU is received. In step S204, the low address bits C2P_Addr[5:2] of the read address C2P_Addr[23:0] are transformed into a target index n to look up the first and second register sets R1and R2to get the reference high address bits DWn_Addr[23:6]. In step S206, it is checked whether the reference high address bits DWn_Addr[23:6] match the high address bits C2P_Addr[23:6]. If not, step S208is performed to cache the data which is read from the storage device104in a data length of several line buffers of the first and second buffer sets B1and B2to update the first and second buffer sets B1and B2and, accordingly, the address information in the first and second register sets R1and R2are updated. In step S210, data Data_DWn is retrieved from the updated first and second buffer sets B1and B2according to the target index n to respond to the read request issued from the central processing unit CPU. Step S210that responds to the central processing unit CPU is not limited to being performed after step S208finishes all the pre-fetching and buffering operations. In another exemplary embodiment, the central processing unit CPU is immediately responded to once the data (i.e. 4 bytes of data) requested by the central processing unit CPU has been read from the storage device104. When it is determined in step S206that the reference high address bits DWn_Addr[23:6] match the high address bits C2P_addr[23:6], it means that the data requested by the central processing unit CPU has already been pre-fetched and buffered into the first or second buffer sets B1or B2. Thus, step S210is performed and step S208is bypassed. In step S210, data Data_DWn is retrieved from the first and second buffer sets B1and B2according to the target index n to respond to the read request issued from the central processing unit CPU.

FIG. 3AandFIG. 3Bshow a flowchart depicting how the first and second buffer sets B1and B2operated in the ping-pong buffer mode work when the central processing unit CPU outputs a read request. In step S302, a read address requested by the central processing unit CPU is received. In step S304, it is determined whether the read address is sequential to a previous read address issued from the central processing unit CPU. If not, step S306is performed to transform the low address bits C2P_Addr[5:2] of the read address into a target index n to look up the first and second register sets R1and R2to get the reference high address bits DWn_Addr[23:6]. In step S308, it is checked whether the reference high address bits DWn_Addr[23:6] match the high address bits C2P_Addr[23:6] of the read address. If not, it means that the data of the read address C2P_Addr[23:0] has not been pre-fetched in the first and second buffer sets B1and B2and step S309is performed, and thereby the pre-fetching and buffering operation to the pre-fetch buffer set, which is one of the first and second buffer sets B1and B2, is stopped. When the first and second buffer sets B1and B2operate in the ping-pong buffer mode and the requested read address is determined not to be sequential to the previous read address in step S304and the reference high address bits DWn_Addr[23:6] are determined to not be matching the high address bits C2P_Addr[23:6] of the read address in step S308, it means that the read request from the central processing unit CPU has probably already jumped to another address sector at which the data has not been pre-fetched or buffered. Thus, it is meaningless to continue pre-fetching and buffering data around the address range of the current pre-fetch buffer set. In the disclosure, the pre-fetching and buffering operation to the pre-fetch buffer set, which is one of the first and second buffer sets B1and B2, is stopped and step S310is performed to read the storage device104for data with sequential addresses starting from the current read address C2P_Addr[23:2] and to update the first and second buffer sets B1and B2from the target index n corresponding to the low address bits C2P_Addr[5:2] of the current read address C2P_Addr[23:2] to the last index of the first and second buffer sets B1and B2(e.g. updating Data_DWn to Data_DW15). The first and second register sets R1and R2are updated with the update of the first and second buffer sets B1and B2. In step S312, the first and second buffer sets B1and B2are read according to the target index n to provide the data Data_DWn to respond to the read request from the central processing unit CPU. Step S312that responds to the central processing unit CPU is not limited to being performed after step S310finishes all the pre-fetching and buffering operations. In another exemplary embodiment, the central processing unit CPU is immediately responded to once the data (i.e. 4 bytes of data) requested by the current read request issued from the central processing unit CPU has been read from the storage device104. When it is determined in step S308that the reference high address bits DWn_Addr[23:6] match the high address bits C2P_addr[23:6] of the read address, it means that the data requested by the central processing unit CPU has already been pre-fetched and buffered in the first or second buffer set B1or B2and the step S312is performed and steps S309and S310are bypassed. In step S312, data Data_DWn is retrieved from the first and second buffer sets B1and B2according to the target index n to respond to the read request issued from the central processing unit CPU. In another case wherein the current read request is not sequential to the previous read request but the reference high address bits DWn_Addr[23:6] match the high address bits C2P_addr[23:6] of the read address, step S309is also performed to and thereby the pre-fetching and buffering operation to the pre-fetch buffer set, which is one of the first and second buffer sets B1and B2, is stopped. After step S309, data is pre-fetched from the storage device104from address C2P_addr[23:2]+1. When it is determined in step S304that the read address is sequential to the previous read address, step S314ofFIG. 3Bis performed to continue reading the first and second buffer sets B1and B2to get data to respond to the central processing unit CPU, to take advantage of a ping-pong buffering technique which continuously pre-fetches and buffers data of sequential addresses from the storage device104into the first and second buffer sets B1and B2. In step S316, it is checked whether the target index n transformed from the read address points to the first line buffer of the first buffer set B1or the first line buffer of the second buffer set B2. When the target index n points to the first line buffer of the first buffer set B1, the pre-fetch buffer set is changed to the second buffer set B2in step S318. When the target index n points to the first line buffer of the second buffer set B2, the pre-fetch buffer set is changed to the first buffer set B1in step S318. After step S318, step S320is performed to pre-fetch data from the storage device104to fill the pre-fetch buffer set. When the target index n points to neither the first line buffer of the first buffer set B1nor the first line buffer of the second buffer set B2, the pre-fetch buffer set is not changed between the first buffer set B1and the second buffer set B2and data is continuously pre-fetched from the storage device104till the current pre-fetch buffer set is full.

FIG. 4is a flowchart depicting how the operation mode of the first and second buffer sets B1and B2is switched during the start-up procedure of the computer system100. During the start-up procedure, the read-only memory code ROM_Code stored in the storage device104is executed to start the BIOS. In step S402, it is checked whether the cache memory106of the central processing unit CPU has started up. When the cache memory106has not started up, step S404is performed to operate the first and second buffer sets B1and B2in a cache memory mode (referring to those described inFIG. 2) to store the frequently and repeatedly required read-only memory code ROM_Code therein to respond to the central processing unit CPU. When the cache memory106has started up, step S406is performed to switch the buffer mode setting register110to operate the first and second buffer sets B1and B2in the ping-pong buffer mode (referring to those described inFIG. 3AandFIG. 3B) to alternately pre-fetch and buffer the read-only memory code ROM_Code of sequential addresses. In this manner, the read requests that the central processing unit CPU issues to copy the large-sized read-only memory code ROM_Code of sequential addresses from the storage device104to the DRAM108are properly responded to through the design of the first and second buffer sets B1and B2.