Memory module and memory system

A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean Patent Application number 10-2007-0056936, filed on Jun. 11, 2007, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety as if set forth in full.

BACKGROUND

1. Technical Field

The embodiments described herein relate to a memory module, and more particularly, to a memory module including a plurality of ranks.

2. Related Art

In general, semiconductor memories are manufactured in the forms of modules. A module is a functional unit having an independent function in a system. A conventional memory module may include one or more ranks according to the structure of a memory system. The rank includes a plurality of semiconductor element packages that are controlled in the same condition by one chip selection signal ‘CS’ or one chip enable signal ‘CE’.

Specifically, each rank having a plurality of semiconductor element packages are mounted to a printed circuit board (PCB), and the PCB is connected to, for example, a panel by a plurality of connection terminals. In a conventional semiconductor memory, the chip selection signal ‘CS’ or the chip enable signal ‘CE’ is used to identify the rank.

However, as the number of ranks mounted to the memory module increases, the number of pins of the memory module for supplying the chip selection signals ‘CS’ or the chip enable signals ‘CE’ required to select the ranks also increases. It is difficult to add pins to each rank since the number of pins provided in the memory module is limited.

SUMMARY

A memory module that allows the selection of a rank without a separate rank selection pin is disclosed herein, as is a memory system that allows the selection of a rank without a separate rank selection pin.

According to one aspect, a memory module includes n ranks (n is an integer number that is equal to or greater than 2) each of which includes a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.

The first pin group can include n pins corresponding to the n ranks. The rank selecting unit can include n multiplexers corresponding to the n ranks. The multiplexer can multiplex the signals of the first pin group by using predetermined register signals for each rank, and output the rank pin signals. The predetermined register signals can be as n register signals, which are MRS or EMRS signals. The multiplexer can output any one of the signals of the first pin group as the rank pin signal in response to one of the n register signals that is activated.

According to another aspect, a memory module includes a plurality of ranks (n is an integer number that is equal to or greater than 2) that each include a first pin group and a second pin group each of which is physically connected to external pins in the same connection method, and a rank selecting unit that is coupled with each of the plurality of ranks, the rank selecting unit configured to multiplex the signals received via the first pin group that, and to output different rank pin signals based on the multiplexed, received signals.

According to still another aspect, a memory system includes a host that provides external pin signals, and a memory module coupled with the host, the memory module comprising a plurality of ranks that each have a first pin group and a second pin group for receiving the external pin signals. In the memory system, each of the ranks includes a rank selecting unit that receives the external pin signals and outputs different rank pin signals to the first pin group.

DETAILED DESCRIPTION

According to the embodiments described herein, it is possible to select ranks without separate chip selection signal pins. That is, a host can provide rank signals for identifying ranks to a memory module during an initializing operation. The rank signals can then be stored in a register in the memory module. In this way, it is possible to selectively control the ranks by intercrossing signals corresponding to the register signals for the ranks. It is also possible to selectively control the operations of the ranks without a separate rank selection pin by using a simple multiplexing method based on register information. In addition, it is possible to provide a system including a host for controlling the memory module.

Such a memory system will be described in detail below.

For example,FIG. 1is a block diagram illustrating an example memory system101configured in accordance with one embodiment. Referring toFIG. 1, the memory system101can include a host100and a memory module200.

The host100can be provided outside the memory module200and can be configured to control the operation of the memory module200. The term “host” is used herein to broadly refer to a controller or the like, which can comprise one or multiple chips or circuits. For instances, in the example, the host100can be a chip set circuit unit that directly communicates with the memory module200.

The host100can be connected to the memory module200and can supply signals for controlling the operation of the memory module200. For example, the host100can be configured to supply commands and address signals to the memory module200. However, in this embodiment, a separate chip selection signal (‘CS’) pin is not provided between the host100and the memory module200.

Next, the structure of the memory module200will be described below. The memory module200can include a plurality of ranks210to240, a first pin group250, and a second pin group260.

Specifically, the memory module200according to this embodiment can include first to fourth ranks210to240, and the ranks210to240can be connected to each other by wiring lines. Each rank210to240can include a plurality of semiconductor device packages (not shown). The ranks210to240can be connected to the host100and can receive signals from the host100.

The chip selection signal (‘CS’) pin for operating the ranks210to240is not provided as in conventional memory modules, but wiring lines for connecting the pins of the ranks210to240are physically intercrossed. That is, when the ranks210to240receive signals from the host100, the same signal is transmitted to different pins of the ranks210to240. In other words, the wiring lines for connecting the pins of the ranks210to240can be physically intercrossed such that the same signal is transmitted to different pins of the ranks210to240, thereby identifying the rank responding to the signal.

In this embodiment, the pin group for identifying the ranks is exemplified as the first pin group250. The number of pins included in the first pin group250can therefore correspond to the number of ranks210to240, that is, the first pin group250can include n (n is an integer number equal to or greater than 2) pins corresponding to n ranks. Therefore, in the example ofFIG. 1, since the number of ranks210to240is four, the number of pins included in the first pin group250is four. In this embodiment, the first pin group250includes command pins and address pins, but the embodiments described herein are not limited thereto. In addition, the second pin group260can include the other command pins and address pins and data pins except for the first pin group250.

In this embodiment, the host100can be configured to supply signal ‘0001’ to the first pin group250. Then, the first rank210receives the signal ‘0001’. However, since the wiring lines are intercrossed, the second rank220receives signal ‘0010’ as to the signal ‘0001’ output from the host100. Similarly, the third rank230receives signal ‘0100’ as to the signal ‘0001’ output from the host100, and the fourth rank240receives signal ‘1000’ as to the signal ‘0001’ output from the host100. Therefore, the host100can identify the ranks210to240on the basis of the signals received by the ranks210to240.

In this way, the memory system101can selectively control the ranks without a separate chip selection signal pin by physically connecting the pins with wiring lines such that the wiring lines are intercrossed. However, since the lengths of the wiring lines for connecting the ranks210to240depend on a connection method of the wiring lines, delay can occur in the signals. That is, line delay due to the connection method illustrated inFIG. 1can cause the asymmetry of signals, which can hinder high-speed operation.

FIG. 2therefore illustrated a memory system201configured in accordance with another embodiment in which the signal line are not intercrossed. In describing system201, a description of the structures also that are the same or similar as those shown inFIG. 1will be omitted, and only the difference between the systems will be described.

Referring toFIG. 2, in the memory system201, the host100and the ranks210to240are connected to each other by wiring lines such that all the pins of the ranks210to240receive the same signals. A rank selecting unit300can then be provided across the ranks210to240of the memory module200.

Specifically, in the memory system201, the host100and the ranks of the memory module200are connected to each other by wiring lines such that the same signal is transmitted to the same pin group250or260, thereby reducing the line delay due to the connection between the host100and the memory module200. Similar to the above-described embodiment, in this embodiment, the memory module200can identify the ranks210to240without a separate chip selection signal (‘CS’) pin. That is, the ranks210to240can receive the same signal from the host100. However, predetermined pins of the ranks210to240, for example, the first pin groups250of the ranks210to240receive the same signal, but the signals are differently matched with each other in order to discriminate the ranks. For this reason, the rank selecting unit300can be provided in each rank210to240of the memory module200.

The rank selecting unit300will be described in detail with reference toFIG. 3.

Referring toFIG. 3, the rank selecting unit300can include four multiplexers310to340. It will be understood that while four multiplexers310to340are provided in this example, the number of multiplexers can correspond to n ranks.

The rank selecting unit300can be configured to output rank pin signals ‘Rpin#’ in response to first to fourth rank register signals ‘R<i:l>’ and first to fourth pin signals ‘pin0’ to ‘pin3’, which are pin signals of the first pin group250.

Specifically, the first to fourth multiplexers310to340provided in the rank selecting unit300can be configured to output any one of the first to fourth pin signals ‘pin0’ to ‘pin3’ responding to the register signals ‘R<i:l>’ as the rank pin signal ‘Rpin#’. Different rank pin signals ‘Rpin#’ can be supplied to the ranks210to240according to whether the rank register signals ‘R<i:l>’ are activated.

The register signals ‘R<i:l>’ can be stored signals as predetermined rank signals. That is, the host (see reference numeral100inFIG. 2) can be configured to provide signals for identifying the ranks210to240to the ranks210to240when the memory module200is initialized. The signals can be stored in a register of the memory module200, which can serve as the register signals ‘R<i:l>’. The register signals ‘R<i:l>’ can be MRS (mode register set) signals or EMRS (extended mode register set) signals, but the embodiments described herein are not limited thereto.

In this way, it is possible to provide the rank pin signal ‘Rpin#’ in response to an activated register signal ‘R<i:l>’ of the received n register signals ‘R<i:l>’. That is, it is possible to provide the rank pin signal ‘Rpin#’ for identifying the ranks by multiplexing the first to fourth pin signals ‘pin0’ to ‘pin3’ in response to the register signals ‘R<i:l>’. Therefore, the host (see reference numeral100inFIG. 2) can identify the ranks210to240on the basis of different rank pin signals ‘Rpin#’ provided to the ranks210to240.

The rank pin signals ‘Rpin#’ of the ranks210to240can be provided to a command and address decoding unit400, and the command and address decoding unit400can be configured to decode the rank pin signals to be suitable for the ranks210to240.

FIG. 4is a detailed circuit diagram illustrating the rank selecting unit300. As described above, the rank selecting unit300can include the first to fourth multiplexers310to340. As further described above, each of the multiplexers310to340can receive four register signals ‘R<i:l>, and outputs one of the first to fourth pin signals ‘pin0’ to ‘pin3’ that corresponds to an activated register signal ‘R<i:l>’ as the rank pin signal ‘Rpin#’.

In this embodiment, as examples of the register signals ‘R<i:l>, the first rank register signal, the second rank register signal, the third rank register signal, and the fourth rank register signal are referred to as ‘Ri’, ‘Rl’, ‘Rk’, and ‘Rj’, respectively.

Referring toFIG. 4, each multiplexer310to340can receive n signals and output one signal. The first multiplexer310can include first to fourth NMOS transistors311to314. Each of the NMOS transistors311to314can include a gate that receives the register signal ‘R<i:l>’, a source that receives any one of the first to fourth pin signals ‘pin0’ to ‘pin3’ from the host (see reference numeral100inFIG. 2), and a drain that outputs the rank pin signal ‘Rpin#’. The drains of the NMOS transistors311to314can be connected to each other. The second to fourth multiplexers320to340can have the same NMOS transistors as described above. However, the register signals ‘R<i:l>’ are received by the NMOS transistors of the multiplexers310to340in different orders.

For example, the NMOS transistors311to314of the first multiplexer310can receive the rank register signals ‘Ri’, ‘Rj’, ‘Rk’, and ‘Rl’, respectively. Meanwhile, the NMOS transistors321to324of the second multiplexer320can receive the rank register signals ‘Rl’, ‘Ri’, ‘Rj’, and ‘Rk’, respectively. The NMOS transistors331to334of the third multiplexer330can receive the rank register signals ‘Rk’, ‘Rl’, ‘Ri’, and ‘Rj’ respectively. The NMOS transistors341to344of the fourth multiplexer340can receive the rank register signal ‘Rj’, ‘Rk’, ‘Rl’, and ‘Ri’, respectively. That is, the multiplexers310to340receive the rank register signals ‘Ri’, ‘Rj’, ‘Rk’, and ‘Rl’ in different orders. The first to fourth multiplexers310to340are provided in each of the ranks210to240.

Next, the operation of the multiplexers310to340will be described below.

In this embodiment, as an example, the second rank register signal ‘Rl’ can be activated to select the second rank220. In this case, the host (see reference numeral100inFIG. 2) provides the first to fourth pin signals ‘pin0’ to ‘pin3’ to the first pin group250. In the memory module200according to this embodiment, the pins of the first pin group250and the second pin group260are physically connected to each other by wiring lines such that the first pin group250and the second pin group260of the ranks210to240receive the same signal from the host (see reference numeral100inFIG. 2). Therefore, the ranks210to240receive the same first to fourth pin signals ‘pin0’ to ‘pin3’.

First, the first to fourth multiplexers310to340respond to an activated second rank register signal ‘Rl’. Therefore, the first multiplexer310outputs the fourth pin signal ‘pin3’ as the fourth rank pin signal ‘Rpin3’, the second multiplexer320outputs the first pin signal ‘pin0’ as the first rank pin signal ‘Rpin3’, the third multiplexer330outputs the second pin signal ‘pin1’ as the second rank pin signal ‘Rpin1’, and the fourth multiplexer330outputs the third pin signal ‘pin2’ as the third rank pin signal ‘Rpin2’. That is, according to the rank selecting unit300of this embodiment, when the host (see reference numeral100inFIG. 2) provides the first to fourth pin signals ‘pin0’ to ‘pin3’, the second rank220can rearrange the signals in the order of the rank pin signals ‘Rpin3’, ‘Rpin0’, ‘Rpin1’, and ‘Rpin2’ and output the rearranged signals. In other words, it is possible to identify the ranks by using new rank pin signals ‘Rpin#’ that are matched with the first to fourth pin signals ‘pin0’ to ‘pin3’ of the first pin group250provided from the host (see reference numeral100inFIG. 2).

FIG. 5is a table illustrating the rank pin signals ‘Rpin#’ shown inFIG. 4. Referring toFIG. 5, the table illustrated the pin signals matched with the ranks when the host (see reference numeral100inFIG. 2) provides the first to fourth pin signals ‘pin0’ to ‘pin3’.

More specifically, in response to an activated host register signal ‘Ri’ provided from the host (see reference numeral100inFIG. 2), the rank selecting unit (see reference numeral300inFIG. 2) can be configured to output the first pin signal ‘pin0’, the second pin signal ‘pin1’, the third pin signal ‘pin2’, and the fourth pin signal ‘pin3’ as the first rank pin signal ‘Rpin0’, the second rank pin signal ‘Rpin1’, the third rank pin signal ‘Rpin2’, and the fourth rank pin signal ‘Rpin3’, respectively, which means that the first rank210is selected.

However, in response to an activated host register signal ‘Rl’ supplied from the host (see reference numeral100inFIG. 2), the rank selecting unit (see reference numeral300inFIG. 2) can be configured to output the first pin signal ‘pin0’, the second pin signal ‘pin1’, the third pin signal ‘pin2’, and the fourth pin signal ‘pin3’ as the third rank pin signal ‘Rpin3’, the first rank pin signal ‘Rpin0’, the second rank pin signal ‘Rpin1’, and the third rank pin signal ‘Rpin2’, respectively, which means that the second rank220is selected.

The third and fourth ranks230and240can be selected in the same method as described above. That is, when the rank selecting unit outputs the first pin signal ‘pin0’ as the third rank pin signal ‘Rpin2’ in response to an activated host register signal ‘Rj’ supplied from the host (see reference numeral100inFIG. 2), the third rank230is selected. However, when the rank selecting unit outputs the first pin signal ‘pin0’ as the second rank pin signal ‘Rpin1’ in response to an activated host register signal ‘Rk’ supplied from the host (see reference numeral100inFIG. 2), the fourth rank240is selected. The other rank pin signals ‘Rpin#’ are output in response to the activated register signals ‘Rj’ and ‘Rk’ in the same manner as described above, and thus a description thereof will be omitted.

As described above, according to this embodiment, it is possible to selectively control the ranks210to240without a separate chip selection signal pin, by simply controlling the register signals ‘R<i:l>’. In addition, the host (see reference numeral100inFIG. 2) and the pin groups of the memory module200can be connected by wiring lines by the same connection structure, which makes it possible to reduce the asymmetry of signals due to a physical connection structure.

FIGS. 6A and 6Bare conceptual diagrams illustrating a memory system having the memory module shown inFIG. 2mounted thereto.

FIG. 6Ashows a series of ranks210to240mounted to a PCB10. That is,FIG. 6Ashows a SIMM (single-in line memory module) in which the memory module200is mounted to one surface of the PCB10.

In contrast,FIG. 6Bis a DIMM (dual-in line memory module) in which a plurality of ranks210to220,230to240are mounted to both surfaces of the PCB10. InFIGS. 6A and 6B, the memory modules200are mounted in different structures, but the memory module200can be mounted in various structures depending on the embodiment.

As described in detail above, it is possible to select the ranks without a separate chip selection signal pin. That is, it is possible to supply signals for selecting the ranks by storing information for identifying ranks in the register when the memory module is initialized and multiplexing the register information. It is possible to selectively control the operations of the ranks without separate pins, by simply multiplexing register information. In addition, it is possible to provide a system including a host for controlling the memory module.

While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the apparatus and methods described herein should not be limited based on the described embodiments. Rather, the apparatus and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.