Memory mapped I/O bus selection

A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally related to I/O bus structures. More particularly, the present invention is related to configuring in real time an ASIC I/O bus structure to communicate with multiple external devices having different bus structures.

2. Background Art

Current ASIC architectures have “hardwired” I/O bus structures. In a multi-I/O bus system, the drawbacks of a hardwired I/O bus structure may include requiring: (1) more ASIC package pins; (2) external glue logic; or (3) an external bus bridge IC.

FIG. 1Ais a diagram illustrating an application-specific integrated circuit (ASIC) having multi-I/O bus structures communicating with two devices having different I/O bus structures.FIG. 1Ashows ASIC102, device104, device106, and device108. ASIC102contains two bus structures, a local bus structure110(e.g., Expansion Bus Interface, or EBI) for communicating with device104and a PCI bus structure112for communicating with devices106and108. Thus, ASIC102contains pins for a local bus110and pins for a PCI bus112.

FIG. 1Bshows additional detail of the ASIC102. As shown inFIG. 1B, the ASIC102includes an internal bus120, a CPU interface126, other internal resources128,130, and two interfaces to external buses, e.g., an EBI bus interface122and a PCI bus interface124, which connect to the EBI bus110and the PCI bus112, respectively.

To support the different interfaces, i.e., EBI bus110and PCI bus112, ASIC102is required to have more pins on the package. The more pins required for the ASIC102, the more costly the ASIC will be to manufacture.

Accordingly, what is needed is a system and method for redefining an ASIC's I/O bus structure in real-time to enable operation in a multi-PO bus system.

BRIEF SUMMARY OF THE INVENTION

The present invention solves the above-mentioned problems by providing a system and method for redefining an ASIC's I/O bus structure in real-time to enable operation in a multi-I/O bus system with a variety of external devices having different I/O bus structures.

In one aspect of the present invention there is provided a system for managing I/O traffic in a multi-bus environment including a circuit (or glue logic) that receives address information from a microprocessor, and an interface to a plurality of buses. The interface has a set of pins the functionality of the pins is defined in real time based on the address information. The functionality can also be dynamically charged in real time based on the address.

In another aspect there is provided a method of managing I/O traffic in a multi-bus environment including receiving an address and an I/O request from a processor, and changing in real time characteristics of pins of an interface to a plurality of buses wherein the characteristics are changed based on the address.

Additional features and advantages oft he invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions (i.e., used for bus addressing, used for other purposes, see generallyFIG. 6) and type of bus structure (e.g., PCI, EBI, etc.). When I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.

The present invention takes advantage of the fact that a processor or CPU will never simultaneously request I/O from more than one bus simultaneously. Furthermore, the address mapping in a typical system is such that the same address is never shared by devices on the different buses. This enables the sharing of resources, particularly ASIC pins, between different buses, provided the pins can be configured appropriately.

Examples of such buses include, e.g., an EBI (Expansion Bus Interface) bus and a PCI bus. The PCI bus is a 32-pin bus that includes 16 data pins. A PCI bus is frequently used to communicate with devices such as Ethernet chips, Gigabit ethernet chips, other CPUs, and various peripheral devices. The pinout of the PCI bus is shown in the table below:

In the EBI bus, 16 pins are dedicated to data, 25 pins to address, and 13 pins to control signals plus additional pins for power and ground. The EBI bus is typically used for accessing memory, such as ROM, RAM and flash memory. It is also sometimes used to access other CPUs. A pinout oft he EBI bus is shown in the table below.

Thus, if an ASIC were to support both interfaces, it would need 54+47=101 pins.

In the present invention, pin arbitration is based strictly on the address. The invention allows the reuse of pins from multiple buses in real time, through use of a memory mapping block. The memory mapping block is essentially a look up table, and is based on the address.

The present invention applies to desk top systems, cable modem systems, cable set top boxes, satellite set top boxes and DSL interfaces. It is particularly advantageous in systems where the cost oft he package is a significant part of the overall cost, and the brute force approach of dedicating separate pins and interfaces for each type of bus is difficult or impractical.

It should be noted that the designer should pay particular attention to load and driving requirements, which are frequently different for different buses. For example, the EBI bus typically has lower driver requirements than the PCI bus. The PCI bus has distance requirements, which the EBI bus does not. However, the designer of the system would know in advance how many devices are expected to be connected on each bus, and can design the system accordingly.

In some instances, an ASIC may only contain one I/O bus structure.FIG. 2is a diagram illustrating an application-specific integrated circuit having a local bus structure in communication with an external device having a PCI bus structure.FIG. 2shows ASIC102in communication with ASIC204. ASIC102, as previously stated, has a local bus PO structure. ASIC204has a PCI bus I/O structure. In order for ASIC202to communicate with ASIC204, glue logic or bus bridge206must be interfaced between the two ASICs202,204. Glue logic or bus bridge206communicates with ASIC202via local bus208. Glue logic or bus bridge206communicates with ASIC204via PCI bus210.

Table 3 below shows an example of a pinout of an ASIC where the PCI bus and the EBI bus share pins.

TABLE 3Example of PCI bus and EBI bus sharing one interfacePIN No.EBI BUSPCI BUS1EBI_DATA0PCI_AD02EBI_DATA1PCI_AD13EBI_DATA2PCI_AD24EBI_DATA3PCI_AD35EBI_DATA4PCI_AD46EBI_DATA5PCI_AD57EBI_DATA6PCI_AD68EBI_DATA7PCI_AD79EBI_DATA8PCI_AD810EBI_DATA9PCI_AD911EBI_DATA10PCI_AD1012EBI_DATA11PCI_AD1113EBI_DATA12PCI_AD1214EBI_DATA13PCI_AD1315EBI_DATA14PCI_AD1416EBI_DATA15PCI_AD1517EBI_ADD0PCI_AD1618EBI_ADD1PCI_AD1719EBI_ADD2PCI_AD1820EBI_ADD3PCI_AD1921EBI_ADD4PCI_AD2022EBI_ADD5PCI_AD2123EBI_ADD6PCI_AD2224EBI_ADD7PCI_AD2325EBI_ADD8PCI_AD2426EBI_ADD9PCI_AD2527EBI_ADD10PCI_AD2628EBI_ADD11PCI_AD2729EBI_ADD12PCI_AD2830EBI_ADD13PCI_AD2931EBI_ADD14PCI_AD3032EBI_ADD15PCI_AD3133EBI_ADD16PCI_CBE034EBI_ADD17PCI_CBE135EBI_ADD18PCI_CBE236EBI_ADD19PCI_CBE337EBI_ADD20PCI_PAR38EBI_ADD21PCI_TRDY39EBI_ADD22PCI_IRDY40EBI_ADD23PCI_DEVSEL41EBI_ADD24PCI_STOP42EBI_ADD2543EBI_RESETPCI_RESET44EBI_CLKPCI_CLK45EBI_WR_N46EBI_RD47EBI_DS48EBI_WE49EBI_TS50EBI_TA51EBI_TAE52EBI_CS53PCI_FRAME54PCI_INT55BUS_REQBUS_REQ56BUS_GRNTBUS_GRNT

In this example the ASIC would need 56 pins to support both interfaces.

FIG. 3is a block diagram illustrating memory map I/O bus selection for enabling an ASIC to communicate with multiple I/O bus structures in real time according to an embodiment of the present invention. As shown inFIG. 3, the present invention eliminates the need for multiple pins representative of different I/O bus structures on a single ASIC chip. The present invention also eliminates the need for glue logic or bus bridges to connect one type of I/O bus structure to another type of I/O bus structure. As shown inFIG. 3, memory mapped bus I/O bus selection302enables ASIC202to communicate via an I/O bus304to device104, and also device ASIC204. Device104includes a local bus208as where ASIC204communicates via a PCI bus210. Memory mapped I/O bus selection302enables ASIC chip202to have a single PO bus structure that communicates via I/O bus304to either device104or ASIC204. Memory mapped I/O bus selection302changes the definition of I/O bus304in real time depending upon which device or ASIC ASIC204is communicating with. For example, if ASIC202is communicating with device104, wherein device104has a local bus, I/O bus304is defined in real time to be a local bus. Alternatively, if ASIC202is communicating with ASIC204, memory-mapped I/O bus selection defines I/O bus304to be a PCI bus in order that ASIC204communicates with ASIC202. Thus, when ASIC202needs to be a PCI bus for comminations with ASIC204, the definition of the bus is changed in real time. This eliminates the need for numerous extra pins on ASIC202. Thus, the present invention enables one set of pins on an ASIC chip to support a plurality of I/O bus structures.

FIG. 4Ais a more detailed block diagram of memory-mapped I/O bus selection302. Memory-mapped I/O bus selection302comprises an address map block402, a state machine block404and a bus arbitration block406. Address map block402is coupled to state machine404and state machine block404is coupled to bus arbitration406.

Address map block402is used to configure an address map into regions and types of bus structures. For example, such bus structures may include, but are not limited to, a PCI bus, an EDI bus, a SCSI bus, a MIPS bus, a 68K-type bus, etc.

State machine block404is used to determine the syntax and protocol for a region and type of bus upon receipt of1/0access by a client. Bus arbitration block406is used to enable a bus artibrateur to grant bus ownership.

FIG. 4Bshows additional detail oft he ASIC202oft he present invention, with the PCI bus and the EPI bus used as examples. As shown inFIG. 4B, the ASIC202includes an internal bus120, which is connected to a CPU interface126and other internal resources128,130. The internal bus120is also connected to the address map block402, the state machine404, and an external bus interface408. The external bus interface408is connected to a bus304, which can be configured (in this example) as either a PCI bus or an EBI bus, depending on the address provided to the ASIC202.

FIG. 5is a flow diagram illustrating a method for redefining an I/0bus structure in real time according to an embodiment of the present invention. The process begins with step502(start), where the process immediately proceeds to step504.

In step504, at initialization, the address map block402is configured to divide the address space into region and types of bus structures. The process then proceeds to step506.

In step506, when an P/O access if requested by a client, the request is mapped into a region and type of bus structure by the address map block402. A client may include a CPU, a DMA controller, etc. The process then proceeds to step508.

In step508, the region and type of bus structure is used by the state machine404to determine the syntax and protocol for the region and type of bus. The state machine404then signals the bus arbitration block406to grant I/0bus ownership when it is available in step510. The process then proceeds to step512.

In step512, once ownership is granted, I/O bus pins of the ASIC are defined and access is granted.

FIG. 6illustrates the memory space allocation of the ASIC202. In the example shown inFIG. 6, the lowest addresses are reserved for the PCI bus, access, the next lowest for the EBI bus, and so forth.

FIG. 7illustrates additional detail of operation of the state machine404. As shown inFIG. 7, normally the state machine404is in an idle state (step702). Upon an external bus request, the state machine404can either return to idle (step702) or continue to process the request (step706). If the request is for an internal bus, the next decision is whether a memory mapped I/O decision is required (step708). If the address maps to the EBI bus, the pins of the ASIC pinout should be configured for the EBI bus (step710). The EBI bus is then accessed (step712). If the request is for the PCI bus, based on the address, the pins of the ASIC202are configured for PCI bus operation (step716). (In this example, only two types of buses are supported, but in actuality, other types of buses may be present). The PCI bus is then accessed (step718). After steps712or718, the state machine returns to idle state.

If in step706, the request is not for an internal bus, the bus is granted (step714). The state machine404then returns to the idle state.