16 bit quadrature direct digital frequency synthesizer using interpolative angle rotation

A direct digital synthesizer employs a trigonometric function generator utilizing decomposition of a larger angle into smaller sub-angles, interpolation of a desired sub-angle between two known angles and calculating the trigonometric function using complex arithmetic. The direct digital synthesizer has a phase accumulator to generate an angular increment signal of the output signal. A trigonometric function generator in communication with the phase accumulator receives the angle signal and from the angle signal creates the trigonometric function signal. An angle decomposing circuit is connected to receive the angle signal to separate the angle signal into sub-angles of the angular increment, a sum of the sub-angles equaling the angular increment. An interpolation circuit receives the smallest of the sub-angles to generate the trigonometric function for the smallest of the sub-angles by interpolating between the trigonometric function of two known angles. The direct digital synthesizer has a first angle trigonometric retaining for retaining the trigonometric functions of the known angles. At least one second angle trigonometric retaining circuit retains the trigonometric functions of for the remaining sub-angles. A complex arithmetic unit combines the interpolated trigonometric function and the second trigonometric function from each of the second angle trigonometric retaining circuits to create the trigonometric function.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to methods and apparatus for direct digital frequency synthesis. More particularly this invention relates to methods and apparatus for direct digital frequency synthesis employing interpolation of trigonometric functions of angles between the trigonometric function of known angles.

2. Description of Related Art

As is described inA Technical Tutorial on Digital Signal Synthesis, Analog Devices, Norwood, Mass., 199, pp. 5-9, and shown inFIG. 1a, a direct digital synthesizer in its simplest form is implemented from a precision reference clock5, an address counter10, a read only memory (ROM)15, and a digital-to-converter20. The digital amplitude information that corresponds to a complete cycle of a sine wave is stored in the ROM15as a table of sine functions with the addresses of the ROM15acting as the angular values of the sine contents of the table. The address counter10steps through and accesses each of the ROM's15memory locations and the contents (the equivalent sine amplitude words) are presented to the digital-to-analog converter20. The digital-to-analog converter20generates an output frequency Fout25that is an analog sine wave in response to the sequence digital input words from the ROM15.

The output frequency Fout25of this direct implementation is dependent on the frequency of the reference clock Fclk5and the number of increments of the angular values of the sine function as stored in the ROM15. While the analog output fidelity, jitter, and AC performance of this simplistic architecture can be quite good, it lacks tuning flexibility. The output frequency Fout25can only be changed by changing the frequency of the reference clock Fclk5or by reprogramming the ROM15. Neither of these options support high-speed output frequency hopping such as used in spread spectrum modulation techniques of wireless radio frequency transmission.

With the introduction of a phase accumulator35as shown inFIG. 1b, this architecture becomes a numerically controlled oscillator, which is the core of a highly flexible direct digital synthesis device. The phase accumulator35is a variable-modulus counter and phase register is implemented in the circuit before ROM15, as a replacement for the address counter10. The input word30provides a phase angle increment indicating the number of reference clock Fclk5pulses needed to construct the output frequency Fout25. The phase accumulator35provides the phase angle37that addresses the ROM15. The ROM15then provides the sine amplitude values45for the phase angles indicated by the phase accumulator35.

Referring now toFIG. 1cto visualize the sine wave oscillation as a vector rotating around a unit circle50. Each designated point on the unit circle50corresponds to the equivalent point on a cycle of a sine waveform. As the vector rotates around the circle50, it is apparent that a corresponding output sine wave is being generated. One revolution of the vector around the unit circle50, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator35is utilized to provide the equivalent of the vector's linear rotation around the unit circle50. The contents of the phase accumulator15correspond to the points on the cycle of the output sine wave. The number of discrete phase points contained in the unit circle50is determined by the resolution of the input control word30, of the phase accumulator35. The output of the phase accumulator35is linear and cannot directly be used to generate a sine wave or any other waveform except a ramp. Therefore, the ROM15acts as a phase-to-amplitude lookup table to convert a truncated version of the phase accumulator's15instantaneous output value into the sine wave amplitude information that is presented to the digital-to-analog converter20.

The phase accumulator35is actually a modulus M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by a digital input word30that is summed with the counter. The input word30forms the phase step size between reference clock updates; it effectively sets how many points to skip around the unit circle. The larger the increment size, the faster the phase accumulator overflows and completes its equivalent of a sine wave cycle. For example, an N=32-bit phase accumulator, an M value of 0000 . . . 0001 (one) would result in the phase accumulator overflowing after 232reference clock cycles (increments). If the M value is changed to 0111 . . . 1111, the phase accumulator will overflow after only 21clock cycles, or two reference clock cycles. This control of the jump size constitutes the frequency tuning resolution of the direct digital synthesizer architecture. The relationship of the phase accumulator35and the input word30form the basic tuning equation for direct digital synthesizer architecture:
FOUT=(M(FCLK))/2N
Where:FOUT=the output frequency of the direct digital synthesizerM=the binary tuning wordFclk=the internal reference clock frequency (system clock)N=The length in bits of the phase accumulator
Changes to the value of M in the direct digital synthesizer architecture result in immediate and phase-continuous changes in the output frequency.

Referring now toFIG. 1dfor a description of a direct digital frequency synthesizer of the prior art. The frequency control word55provides the phase increment to the phase accumulator60to provide the phase modulus of the reference clock Fclk57in the generation of the output frequency. The phase accumulator60is the modulus M counter used to increment the sine/cosine generator65. In the description above the sine-cosine generator65is the ROM15that provides the amplitudes of the sine and/or cosine of the phase angles provided by the phase accumulator65. The output amplitudes of the sine/cosine generator70aand70bare the inputs to the digital-to-analog converters75aand75bwhich creates the quadrature output sine and cosine signals that are the inputs to the low pass filters80aand80b. The low pass filters respectively remove any noise components of the quadrature output sine and cosine signals to form the output signals90aand90b.

As the resolution of the frequency adjustment improves, the frequency control word55becomes has more binary digits. This increases the address space of the sine/cosine generator65as implemented in the ROM15. Thus as the frequency control word increase in size linearly, the size of the ROM15must increase exponentially. To compensate for this, the prior art employs a method to minimize the size of the ROM15by exploiting the symmetrical nature of a sine wave and utilize mapping logic to synthesize a complete sine wave cycle from ¼ cycle of data from the phase accumulator65. The phase-to-amplitude lookup table generates all the necessary data by reading forward then back through the lookup table.

“A 150-Mhz Direct Digital Frequency Synthesizer in 1.25 μM CMOS With −90-Dbc Spurious Performance, Nicholas, et al. IEEE Journal of Solid-State Circuits, December 1991 Volume: 26 Issue: 12, pp. 1959-1969, presents a monolithic CMOS direct digital frequency synthesizer (DDFS), which simultaneously achieves high spectral purity and wide bandwidth. The direct digital frequency synthesizer uses an efficient look-up table method for calculating the sine function and reduces ROM storage requirements by a factor of 128:1.

“A 100-Mhz, 16-B, Direct Digital Frequency Synthesizer with a 100-Dbc Spurious-Free Dynamic Range,” Madisetti, et al., IEEE Journal of Solid-State Circuits, August 1999, Volume: 34 Issue: 8, pp. 1034-1043, describes the architecture and implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm employing a technique similar to coordinate rotational digital computation (CORDIC). The architecture is implemented as a multiplierless, feedforward, and easily pipelineable datapath.

“Low-Power Direct Digital Frequency Synthesis for Wireless Communications,” Bellaouar, et al. IEEE Journal of Solid-State Circuits, March 2000, Volume: 35 Issue: 3, pp. 385-390 discusses a low-power direct digital frequency synthesizer (DDFS) architecture. It uses a smaller lookup table for sine and cosine functions compared to systems of the prior art with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points.

U.S. Pat. No. 5,999,581 (Bellaouar, et al.) describes a direct digital frequency synthesizer for generating a digital sine or cosine function waveform from a received digital input signal. A memory stores digital samples along portions of sine and cosine function waveforms. The memory outputs the digital samples in response to a first portion of the digital input. Control logic is responsive to the digital input and controls the output of the digital samples from the memory to allow digital samples along a complete cycle of the sine or cosine function waveform to be output even though only portions of the sine and cosine function waveforms are stored in the memory. A linear interpolator receives a second portion of the digital input and modifies the digital sample output by the memory to generate intermediate digital samples between the digital samples stored in the memory to improve accuracy.

U.S. Pat. No. 5,986,483 (Yu, et al.) teaches a direct digital frequency synthesizer outputting a sine signal. The direct digital frequency synthesizer includes an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit. The accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M most-significant-bits of the symmetric sample address as the first M most-significant-bits of the sine signal. The fine circuit predicts the last N-M least-significant-bits of the sine signal from the last N-M least-significant-bits of the symmetric sample address according to the first M most-significant-bits of the symmetric sample address of the coarse circuit. Then, the sign circuit outputs a sign bit of the sine signal.

U.S. Pat. No. 5,737,253 (Madisetti, et al.) describes a direct digital frequency synthesizer with a phase accumulator provides a normalized angle θ to a sine/cosine generator that outputs the value of the sine/cosine function at the provided angle. The sine/cosine generator in a preferred embodiment comprises a plurality of multiplierless butterfly and carry-save stages in cascade that perform angle rotations on a phasor on the unit circle whose x and y coordinates correspond to cosine and sine values.

SUMMARY OF THE INVENTION

An object of this invention is to provide a function generator that creates an output signal representing a trigonometric function in response to an input singal representing an angle. The trigonometric function such as a sine or cosine is created employing interpolation of the trigonometric function between two known angles.

Another object of this invention is to provide a function generator that creates an output signal representing a trigonometric function in response to an input signal representing an angle. The trigonometric such as a sine or cosine is created by calculating the trigonometric function employing complex arithmetic to combine the trigonometric function for smaller sub-angles of the angle represented by the input angle.

Further, another object of this invention is to provide a direct digital synthesizer employing a trigonometric function generator utilizing interpolation of a desired angle between two known angles and decomposition of a larger angle into smaller sub-angles and calculating the trigonometric function from the smaller sub-angles using complex arithmetic.

To accomplish at least one of these objects and other objects, a direct digital synthesizer generates at least one output signal, each output signal representing one of a plurality of trigonometric functions in response to an input signal indicating a frequency of the output signal. The direct digital synthesizer has a phase accumulator connected to receive the input signal and a timing signal to generate an angular increment signal of the output signal. The angle signal being incremented by the input signal at each occurrence of the timing signal. The direct digital synthesizer, further, includes a trigonometric function generator in communication with the phase accumulator to receive the angle signal and from the angle signal creates at least one trigonometric function signal. Each trigonometric function signal represents one of the trigonometric functions.

The trigonometric function generator has an angle decomposing circuit connected to receive the angle signal to separate the angle signal into a plurality of decomposition signals representing sub-angles of the angular increment, a sum of the sub-angles equaling the angular increment. An interpolation circuit in communication with the angle decomposing circuit receives one of the decomposition signals representing a smallest of the sub-angles. The interpolation circuit generates the trigonometric function signals representing the plurality of trigonometric functions for the smallest of the sub-angles by interpolating between the trigonometric functions of two known angles.

The interpolation circuit includes a fractional angle calculator. The fractional angle calculator creates a fraction signal representing a fraction of the interval between two known angles where the smallest of the sub-angles of the decomposed angle resides. A difference calculator is connected to receive the trigonometric function signal for the two known angles to create a difference signal representing a difference for each trigonometric function of each of the two known angles. A multiplier circuit receives the difference signal and the fraction signal to create a product signal that is the multiplication of the difference signal and the fraction signal indicating a fractional portion of the trigonometric function of the smallest sub-angle in the interval of the two known angles. A summation circuit receives the trigonometric function signal of the least of the two known angles and the fraction signal to add the trigonometric signal of the least of the two known angles with the fraction signal to create the trigonometric function signal representing the trigonometric function for the smallest sub-angle.

The direct digital synthesizer has a first angle trigonometric retaining circuit in communication with the interpolation circuit and the angle decomposing circuit for retaining the trigonometric functions of the known angles. The first angle trigonometric retaining circuit communicates a first trigonometric function signal representing the trigonometric functions for the two known angles to the interpolation circuit. The angle decomposing circuit provides a first indicating signal selecting the two known angles. The two known angles being an adjacent larger known angle and an adjacent smaller known angle of the smallest sub-angle.

The direct digital frequency synthesizer also has at least one second angle trigonometric retaining circuit. Each of the second angle trigonometric retaining circuits is in communication with the angle decomposing circuit and retains the trigonometric functions of for one of the sub-angles. The second angle retaining circuit communicates a second trigonometric function signal representing the trigonometric functions for the sub-angle upon receipt of a second indicating signal from the angle decomposing circuit denoting the sub-angle.

A complex arithmetic unit combines the first trigonometric function signal and the second trigonometric function signal of each of the second angle trigonometric retaining circuits to create the trigonometric function signals. The complex arithmetic unit has a complex multiplier to multiply the first and second function signals to form said output trigonometric function signal representing the angle indicated by the angle signal from the phase accumulator.

The trigonometric function signal is transferred to a digital-to-analog converter to create the output signals. The output signals are filtered by a low pass filter to remove undesired noise signals from the output signal.

In the preferred embodiment of this invention the trigonometric functions are sine and cosine functions and the output signals represent the sine function and a cosine function of the angle represented by the input signal.

DETAILED DESCRIPTION OF THE INVENTION

The direct digital frequency synthesizer of this invention has a trigonometric function generator that upon receipt of an input signal representing a phase angle provides an output signal representing at least one trigonometric function of the phase angle. The trigonometric function generator decomposes the phase angle into multiple sub-angles. One of the sub-angles indicating the quadrant of the unit circuit50ofFIG. 1c. A second sub-angle is a coarse increment of a quadrant of the unit circuit50and a third sub-angle is a fine increment of the coarse increment. The phase angle is the sum of the sub-angles and a small differential between two of the third fine increments.

The trigonometric function generator determines the trigonometric function of the sub-angle of the coarse increment and then interpolates the trigonometric function between the trigonometric function of each of the two of the fine increments larger and smaller than smallest sub-angle of the decomposed phase angle. The trigonometric function generator then performs a complex arithmetic combination of the trigonometric function of the coarse sub-angle and the interpolated trigonometric function of the smallest sub-angle of the phase angle. The symmetry of the trigonometric functions allow the quadrant indication of the first sub-angle to permit either negation or interchange of dualistic trigonometric function to set the trigonometric functions of the second, third, and fourth quadrants of the unit circle.

Refer toFIG. 2for a more detailed discussion of the decomposition of the phase angle into the sub-angle and the interpolation of the smallest sub-angle. The phase angle θ is essentially divided by π/2 radians (90°) to determine the first sub-angle or the quadrant of the unit circle. The second sub-angle is determined by subtracting the quadrant multiplied by the by π/2 radians (90°) from the phase angle θ. The second sub-angle is then divided by a number of increments into which the first quadrant is divided to determine which increment of the coarse angle contains the second sub-angle. In the preferred embodiment the first quadrant is divided into eight increments therefore the second sub-angle is divided by π/16 (11.25°). The third sub-angle is then determined by subtracting the increment of the coarse sub-angle by the increment size π/16 (11.25°) from the second sub-angle. The coarse sub-angle is divided into a number of increments and the third sub-angle is divided by the number of increments of the coarse sub-angle. The third sub-angle being the sum of multiplication of the size of the increments of the third sub-angle and a small increment differential. In the preferred embodiment the coarse sub-angle is divided into eight increments or π/128 (1.4°). In summary, the decomposition of the phase angle θ is determined by the formula:
θ=α+Φ+φ
where:

α=⁢m⁢⁢π2ϕ=⁢n⁢⁢π16φ=⁢k⁢⁢π128+δm is the quadrant of the angle θ.n is the increment of the coarse sub angle into which the first quadrant is divided.k is the increment of the fine sub-angle into which the coarse sub-angle is divided.δ is the differential remainder between the two fine sub-angles.

As is known, the phase angle θ on the unit as projected to the abscissa and the ordinate respectively provide the sine and cosine functions of the phase angle θ. Further, the trigonometric identities state that the sine and cosine of the sum of two angles can be determined by the complex multiplication of the coordinates of the abscissa and the ordinate of the projection of the two angles from the unit circle. Thus sine and the cosine of the sum of the coarse and fine angle are determined from the complex multiplication shown in the formula:
cos(Φ+φ)+jsin(Φ+φ)=(cos(Φ)+jsin(Φ))*(cos(φ)+jsin(φ))
thus
sin(Φ+φ)=(cos(Φ)*sin(Φ))+(cos(φ)*sin(φ))
cos(Φ+φ)=(cos(Φ)*cos(Φ))−(sin(φ)*sin(φ))

The trigonometric functions (sine and cosine) of the smallest sub-angle φ are determined by interpolation of the trigonometric functions of the fine increment angle larger and the fine increment angle smaller that the smallest sub-angle φ. In “A Digital Signal Processing Approach to Interpolation,” Schafer, et al., Proceedings of the IEEE, June 1973, vol. 61, pp. 692-702, describes use of classical linear and polynomial interpolation techniques for digital signal processing. In the preferred embodiment of this invention the interpolation of the smallest sub-angle φ uses linear interpolation, but it is in keeping with the intent of this invention to also employ polynomial interpolation to determine the trigonometric function of the smallest sub-angle φ. The interpolation of the sine and cosine of the smallest sub-angle φ is determined by the formulas:

Refer now toFIG. 3for an explanation of the preferred embodiment of the trigonometric function generator of this invention. The frequency control word100is applied to the phase accumulator105. The frequency control word100is the digital signal representing the magnitude of the phase angle increment of the digital input word as describes inFIG. 1dand is the integer ratio of a reference clock (not shown) and the desired output frequency. The phase accumulator105has an adder107and a phase register108. The adder107sums the frequency control word100with the current phase magnitude signal109from the phase register108to generate a next phase magnitude. At each cycle of the reference clock the current phase magnitude signal109changes to the next phase magnitude. Since the phase magnitude signal109is in fact an address, which in the classical direct synthesizer of the prior art would be an address of the ROM, the phase magnitude is normalized such that the range of the addresses of the current phase magnitude100is normalized to represent the phases from zero radians (0°) to 2π (360°) radians.

In an implementation of the preferred embodiment, the phase accumulator105is a 32 bit phase accumulator. The 32 bit phase accumulator is used to generate the phase from the input frequency control word100. The 32 bit accumulator allows a frequency tuning resolution of Fclk/232, where Fclk is the reference clock. Equivalently, the output frequency can thus be controlled to a resolution less than 0.001 ppm. The 32 b adder is partitioned into two 16 b carry-select adder sections. Each 16 b adder is designed as a Brent-Kung-structured carry-look-ahead adder, and the 16 b addition is completed in 1.8 nsec in 0.35 μm CMOS technology. The output of the phase accumulator is truncated to 15 b.

The current phase magnitude100as truncated by the phase accumulator105is transferred to the angle decomposition circuit110. The angle decomposition circuit110creates the sub-angles of the phase angle θ, which in the preferred embodiment are represented as described above by the formula:
θ=α+Φ+φ

The phase angle magnitude signal109is a binary number having 2N(N being the number of binary digits of the binary number) possible numbers representing the possible phase angles from zero radians (0°) to 2π (360°) radians. The phase decomposition circuit110is essentially a router that chooses particular signals of the phase angle magnitude109for routing. The quadrant selection (α) is determined by the two most significant bits114of the decomposed phase magnitude signal160. The three next most significant bits112indicate the coarse increments Φ of the phase angle and the following next most significant three bits113indicate the fine increments φkwithin each of the coarse increments Φ. The fractional portion

(δπ/128)
of the smallest sub-angle φ (φk+δ) between the smaller fine increment φkand the next larger fine increment φk+1is determined by the least significant seven bits111of the decomposed phase angle160.

The second three of the lessor significant bits113are the address inputs to the sine/cosine table125containing the sine and cosine values for the fine increments (π/16) between the coarse increments. The sine and cosine values the smaller fine increment φkand the next larger fine increment φk+1are the inputs to the linear cosine interpolator115and the linear sine interpolator120. The least significant seven bits111indicating the fractional portion

(δπ/128)
of the smallest sub-angle φ (φk+δ) between the smaller fine increment φkand the next larger fine increment φk+1is a second input to the linear cosine interpolator115and the linear sine interpolator120.

The structure for the linear cosine interpolator115and the linear sine interpolator120are identical and are explained for the linear cosine interpolator115only. The linear cosine interpolator115has a difference circuit116to find the difference in value the cosine of the smaller fine increment φkand the value cosine of the next larger fine increment φk+1. This difference is an input to the multiplier117and is multiplied by the fractional portion fractional portion

(δπ/128)
as indicated by the least significant seven bits111. This provides the interpolated value of the cosine of the small difference angle δ that is to be added to the value of the cosine of the smaller fine increment φk. The adder118provides the addition function for the addition of the interpolated value δ to the value of the cosine of the smaller fine increment φk.

The structure of the sine linear interpolator120similarly determines the difference between the values of the sine of the smaller fine increment φkand the value cosine of the next larger fine increment φk+1. This difference is then multiplier by the fractional portion portion fractional portion

(δπ/128)
as indicated by the least significant seven bits111to provide the interpolated value of the sine of the small difference angle δ. The small difference angle δ then added to the value of the cosine of the smaller fine increment φkto produce the value of the sine of the smallest sub-angle φ.

The three bits112indicating the coarse sub-angle Φ are the input to the coarse sine/cosine lookup table130. The coarse sine/cosine lookup table130contains the sine and cosine values for each of the coarse increments (π/16) from 0 to π/2 radians (0-90°). The signals121and119representing respectively the sine and cosine values of the interpolated fine angle φ and the signals132and134representing the sine and cosine values of the coarse angle Φ are the inputs to the complex multiplier135. The complex multiplier135provides the combination of the sine and cosine values of the coarse sub-angle Φ and the interpolated fine sub-angle φ to for the signals142and143representing values of the sine and cosine of the sum of the coarse sub-angle Φ and the interpolated fine sub-angle φ, as described above.

The complex multiplier135has the multiplier136that multiplies the signal representing the cosine of the interpolated fine sub-angle φ and the signal representing the cosine of the coarse sub-angle Φ to form the signal representing the direct cosine product. The multiplier138multiples the signal representing the sine of the interpolated fine sub-angle φ and the signal representing the sine of the coarse sub-angle Φ to form the signal representing the direct sine products. The multiplier137multiplies the signal representing the cosine of the interpolated fine sub-angle φ and the signal representing the sine of the coarse sub-angle Φ to form the signal representing the cross product. Similarly, the multiplier139multiplies the signal representing the cosine of the interpolated fine sub-angle φ and the signal representing the cosine of the coarse sub-angle Φ to form the cross product. The adder140adds the signal representing the direct product of the cosine of the interpolated fine sub-angle φ and the signal representing the cosine of the coarse sub-angle Φ and the signal representing the cross product of the multiple the signal representing the cosine of the interpolated fine sub-angle φ and the signal representing the sine of the coarse sub-angle Φ. The adder140forms the signal142representing sine of the sum of the interpolated fine sub-angle φ and the coarse sub-angle Φ. The adder141adds the signal representing the direct product of the sine of the interpolated fine sub-angle φ and the signal representing the sine of the coarse sub-angle Φ and the signal representing the cross product of the multiple the signal representing the sine of the interpolated fine sub-angle φ and the signal representing the cosine of the coarse sub-angle Φ. The adder141forms the signal143representing cosine of the sum of the interpolated fine sub-angle φ and the coarse sub-angle Φ.

The symmetry of the sine function and the cosine function allows the sine and cosines of the sum of the interpolated fine sub-angle φ and the coarse sub-angle Φ to be interchanged or negated by the negation and interchange circuit145. The negation or interchange is dependent upon the trigonometric identities and is addressed according to the quadrant address114of the most significant bits of the decomposed normalized phase angle. The output signals150and155of the negation and interchange circuit145represent respectively the amplitude of the cosine and the sine of the phase angle θ indicated by the phase accumulator105.

The output signals150and155representing respectively the amplitude of the cosine and the sine of the phase angle θ are then the input to the digital-to-analog converters75band75aofFIG. 1d. As described above the digital-to-analog converters75band75achanges the signal representing the amplitude of the cosine and sine of the phase angle θ to a voltage amplitude. The output of the digital-to-analog converters75band75aare the inputs to the low pass filters80band80awhich filter any unwanted noise from the synthesized frequency as described above to create the synthesized quadrature signals90and85.

The fine cosine and sine lookup table125and the coarse cosine and sine lookup table130are, in the preferred embodiment, implemented as memory cells such as static random access memory or read only memory (ROM). Further, it is apparent to one skilled in the art that the circuit functions as shown maybe implemented in digital signal computing processor. The circuit functions as shown would be a program process for generation of the signals representing the amplitudes for the sine and cosine functions of the generated phase angles. The program process would be programming code executable by the computing processor. The program code maybe obtained from media such as storage nodes of the cluster network or the global communication network in communication with the digital signal computing processor, or stored on storage media such a read only memory (ROM), or a magnetic disk.

Refer now toFIG. 4for a discussion of the program process of this invention that would be implemented as program code for a digital signal computing system. The desired output frequency Foutis set (Box200) and upon querying (Box205) if the set output frequency is a new frequency and if it is a new frequency, the phase interval (Δθ) is determined ((Box210) according to the formula:

Δ⁢⁢θ=2⁢⁢π*FCLKFOUT
Where:Δθ is the phase interval for the desired frequency for the given reference clock.FOUT=the output frequency of the direct digital synthesizerFclk=the internal reference clock frequency (system clock)

The value of the phase interval (Δθ) is stored digitally in an accumulator register of the digital signal computing system and the sensitivity of the tuning of the frequency synthesizer is dependent on the number of bits of the accumulator register. The first phase angle (θ) is set (Box215) to the value of the phase interval (Δθ) and is normalized (Box220) such that the address space available for the phase angles (θ) represents all the phase angles given the resolution of the accumulator register.

The phase angle (θ) is decomposed (Box230) into the sub-angles, which in the preferred embodiment are represented as described above by the formula:
θ=α+Φ+φ

The phase angle is represented in the accumulator register as a binary number having 2N(N being the number of binary digits of the binary number) possible numbers representing the possible phase angles from zero radians (0°) to 2π (360°) radians. The quadrant selection (α) is determined by the two most significant bits of the decomposed phase resident in the accumulator register. The three next most significant bits indicate the coarse increments Φ of the phase angle and the following next most significant three bits113indicate the fine increments φkwithin each of the coarse increments Φ. The fractional portion

(δπ/128)
of the smallest sub-angle φ (φk+δ) between the smaller fine increment φkand the next larger fine increment φk+1is determined by the least significant seven bits of the decomposed phase angle (θ).

A table (Box240) of the sine/cosines for the smallest increments φkof the coarse sub-angle Φ is maintained in a memory area of the digital signal processing computing system. The memory area containing the table (Box240) is generally a read only memory of the computing system with the bits of the accumulator register representing the smallest increments φkacting as pointers to the memory. The sine and cosine of the angle increment φksmaller than the smallest sub-angle φ and the sine and cosine of the angle increment φk+1larger than the smallest sub-angle φ are retrieved (Box235) from the table (Box240) of sine/cosines of the smallest increments φk. From the sine and cosine of the angle increment φksmaller than the smallest sub-angle φ and the sine and cosine of the angle increment φk+1larger than the smallest sub-angle φ, the sine and cosine of the smallest sub-angle φ is then interpolated (Box245) as the proportion of the angle increment of the fractional portion

(δπ/128)
of the smallest sub-angle φ (φk+δ). The interpolation (Box245) is accomplished according the formulas:

A table (Box255) of the sine/cosines for the coarse increments Φ is maintained in a memory area of the digital signal processing computing system. The memory area containing the table (Box255) is generally a read only memory of the computing system with the bits of the accumulator register representing the coarse sub-angle Φ acting as pointers to the memory area. The sine and cosine of the coarse increment indicated are retrieved from the table (Box255) of the sine/cosines. The sine and cosine of the sum of the coarse sub-angle Φ and the fine sub-angle φ are then calculated (Box260) using complex multiplication of the sines and cosines of the coarse sub-angle Φ and the fine sub-angle φ. The complex multiplication is as the formula:
cos(Φ+φ)+jsin(Φ+φ)=(cos(Φ)+jsin(Φ))*(cos(φ)+jsin(φ))
thus
sin(Φ+φ)=(cos(Φ)*sin(Φ))+(cos(φ)*sin(φ))
cos(Φ+φ)=(cos(Φ)*cos(Φ))−(sin(φ)*sin(φ))

The sine and cosine of the sums of the coarse sub-angle Φ and the fine sub-angle φ are then negated and/or interchanged (Box265) dependent upon the quadrant of the angle θ as indicated by the sub-angle α. The sine and cosine functions are then converted and output (Box270) as an analog signal. The frequency control word is queried (Box205) to determine if a new frequency is specified. If no new frequency is specified, the phase angle is incremented (Box225) and the next sine and cosine for the phase angle is created as described in (Boxes230through270).

Refer now toFIG. 5for a discussion of the performance of an implementation of the direct digital frequency synthesizer of this invention. This implementation is fabricated in 0.35 μm CMOS and works at the sampling rate of 250 MHz. The output bandwidth of the implementation, which is generally defined as Fclk/3, reaches approximately 83 MHz. The 32 bit frequency control word Fcw gives the frequency tuning resolution of 0.06 Hz at 250 MHz sampling rate. The frequency switching latency is 10 clock cycles due to the pipelined structure. The plot ofFIG. 5illustrates the digital frequency as a fraction of the clock reference frequency versus the spurious-free dynamic range (SFDR). The direct digital frequency synthesizer of this invention provides a digital output spectrum, for the output frequency near 0.1 fclk, where the spurious-free dynamic range is greater than 100 dBc. As can be seen, the spurious-free dynamic range performance for other output frequencies from approaching 0*Fclk to approximately 0.5*Fclk is also greater than 100 dBc. To obtain such performance by using the lookup table, a ROM table of 14 b×214 words is necessary. As is shown above for this invention, the table requires only sixteen words for each trigonometric function (sine or cosine).