Heat isolation and dissipation structures for optical components in photonic integrated circuits (PICs) and an optical transport network using the same

Photonic integrated circuits (PIC) semiconductor chips are provided with thermal isolation and/or heat dissipation structures between integrated optical components in the PIC chip, particularly integrated active optical components. These structures may also serve as a ground path for electrical circuitry on the PIC chip. An important function is the enhanced thermal isolation from, or dissipation of heat from, between adjacent or neighboring optical components in the PIC so that required spacing between adjacent optical components can be made even less than the thickness of the substrate thereby realizing a more compact optical component array on the monolithic PIC chips.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to photonic integrated circuit (PIC) chips and more particularly to thermal isolation and heat dissipation of integrated optical components formed in a PIC chip or in a wafer comprising PIC chip die.

2. Description of the Related Art

In a photonic integrated circuit (PIC), many active and passive optical components are integrated on the same semiconductor substrate. Some active photonic devices or components require large amounts of input power and, as a result, generate a substantial amount of heat in the chip. For example, arrays of laser diodes (LDs), electro-optic modulators and/or semiconductor optical amplifiers (SOAs) on a single PIC chip may require large amounts of drive current and/or bias. If many of these optical components are to coexist monolithically on the same semiconductor support or substrate, it is important to insure that they are sufficiently thermally isolated or that heat generated by them can be efficiently dissipated away from adjoining components and off the PIC chip.

There are a number of methods that can be employed for thermal isolation in photonic devices or components integrated in PIC chips. Components are often separated physically, and the host wafer is often thinned. Typically, the rule of thumb is that, if the separation between optical components in the chip is much less than the thickness of the wafer, then the on-chip integrated optical or photonic components will need to be thermally isolated from one another.

Another method that is employed relates to the use of flip chip techniques for placement of chips onto a heatsink. If the heatsink has a higher thermal conductivity than the semiconductor substrate, the heat sink will serve to thermally isolate optical chip components that are adjacent to each other.

Both of these techniques have some problems. PIC devices are typically made on compound semiconductor wafers, e.g., fabricated on InP wafers, which are much more fragile than silicon wafers. As a result, although thinning a wafer helps with thermal isolation, it also results in increased wafer breakage and lowers chip yields. Flip-chip is often used for small photonic devices. For larger devices, the difference in the thermal expansion coefficient, the solder and the heat sink results in excess stress which, in turn, results in poor reliability. For a large photonic integrated circuit, flip chip is rendered impractical by the size of the optical components and the resultant PIC chip.

For high speed electronic circuits, holes or vias are often used to transfer the ground plane at the bottom of the semiconductor to the top surface. A via is created by etching a hole through the semiconductor and then filling the hole with metal, typically by means of electroplating.

OBJECTS OF THE INVENTION

It is an object of the present invention to overcome the aforementioned problems by providing improvements in optical component thermal isolation and/or heat dissipation.

SUMMARY OF THE INVENTION

According to this invention, a thermal isolation or dissipation structure is employed in PIC geometry comprising openings or vias, such as, for example, or holes or troughs or trenches, in a semiconductor chip or photonic integrated circuit (PIC) to provide a thermal path for on-chip integrated optical components to thermally isolate adjacently spaced optical components or provide a high thermally conductive path from between adjacent optical components. If need be, the formed conductive paths can also serve as an on-chip electrical conduit. Rather than using small vias purely for electrical connection, much larger sized vias are employed so that the thermal volume of the metal is substantial. Thus, the openings or vias may, respectively, extend partially into or through the body of the wafer or chip. The openings may extend into the top or bottom surface and preferably extend through openings into the bottom of the PIC substrate so that when the openings are filled with a thermally conductive material, the material will be in direct thermal contact with an underlying heatsink or other thermal submount for the PIC chip or chips. The heatsinks that may be employed, for example, are AlN, BeO, copper sandwiched BeO or CVD diamond. The important factor is that the coefficient of thermal expansion of the heatsink should substantially match that of the PIC chip. This becomes more critical with the development of a structure providing for thermal isolation and/or thermal dissipation paths built into the PIC chip thereby changing its coefficient of thermal expansion properties.

An important result of the deployment of this invention is that the distance between the large metal plated vias and the optical active integrated components can be made to be less than the substrate thickness thereby realizing a more compact optical component array on a PIC chip than previously thought possible. Thus, the primary path of heat flow would be laterally to the metal vias, rather than vertically through the substrate. Therefore, it is possible to use substrates that have not been thinned and do not have to be made thinner to meet the above mentioned rule of thumb. Neighboring optical components are now thermally isolated because the high thermal conductivity of the metal means that the vias will be maintained at a nearly constant temperature as the on-chip optical components heat up due to an applied bias or current. The metal used for the vias in any of the embodiments set forth in this description may be, for example, gold or aluminum.

The vias forming the structure may be left unfilled, i.e., empty (thermal isolation) as well as being filled with a thermally conductive material, such as a metal (thermal dissipation). Unfilled structures serve a similar purpose to isolate the optical components as in the case of filled vias where the heat is efficiently carried away. In either case of filled or unfilled, the openings or vias comprising the structure, being positioned between adjacent optical components integrated in the PIC chip, greatly reduces any lateral thermal conductivity, so that on-chip optical components will not longer experience thermal association with neighboring or adjacent optical components.

Thus, by laterally separating optical components by very low thermal conductivity material or by high conductivity material, both serve to thermally isolate them from neighboring optical components, provided, however, that in the case of the high conductivity material, the material should be contiguous with a heatsink submount for the PIC chip.

DETAILED DESCRIPTION OF THE INVENTION

Reference is now made toFIG. 1which illustrates one example of a PIC chip10. The example shown inFIG. 1is a transmitter photonic integrated circuit (TxPIC) chip, but it should be understood that in the employment of the thermal isolation/dissipation structure according to this invention, any PIC chip requiring thermal separation of neighboring optical components, whether active or passive types of such optical components, can be employed. While the invention herein may have its best functioning relative to thermal isolation or heat dissipation from between active optical components, i.e., components requiring an applied bias or current or other applied energy in order to perform a photonic function, it should be understood that the utility of this invention also extends to passive optical components, i.e., components that require no applied bias or current or other energy source to perform a photonic function, such as in cases, for example, where the passive optical component optical properties may be affected by changes in temperature, such as changes in refractive index.

TxPIC chip10is shown in more detail in earlier filed U.S. patent applications, Ser. No. 10/267,331, now Pub. No. US2003/0095737A1, published May 23, 2003, and Ser. No. 10/267,346, now Pub. No. US2003/001878A1, published May 1, 2003, both of which applications were filed on Oct. 8, 2002 and are incorporated herein by their reference. PIC chip10is deployed in an optical transmitter (Tx) module such as disclosed in U.S. patent application, Ser. No. 10/267,212, filed Oct. 8, 2002, now Pub. No. US2003/0099018A1, published 29, 2003, which application is incorporated herein by its reference.

Chip10comprises an array of DFB lasers12optically coupled to an array of electro-optic modulators (EOMs)14, which are optically coupled, via waveguides18, to an optical combiner16, shown here as an arrayed waveguide grating (AWG)16. As, an example, TxPIC chip10may have eight signal channels with different channel wavelengths of λ1to λ8forming a first wavelength grid approximating that of a standardized wavelength grid. However, the number of channels may be greater than eight channels, the latter depending upon the ability to spatially integrate an array of semiconductor modulator/laser (SML) sets15on a chip while providing minimal cross-talk levels.

Other types of optical combiners may be utilized instead of an AWG 16 shown in FIG.1. For example, optical combiner16may be a power coupler, a star coupler, a MMI coupler or an Echelle grating. AWG combiner16is an optical combiner of choice because of its capability of providing narrow passbands for the respective channel signals with low insertion loss. AWG combiner16, as known in the art, comprises an input slab or free space region20, a plurality of grating arms22of predetermined increasing length, ΔL, and an output slab or free space region24. The multiplexed channel signal output from slab24is provided to an output waveguide26for exit from chip10, such as optical coupling the multiplexed channel signal output to an optical fiber (not shown).

As explained in the above incorporated applications, chip10may be comprise of Group III-V compound semiconductors, in particular, for example, InGaAsP/InP or AIInGaAs/InP alloys. In these chips, a coupling core waveguide or a continuous core waveguide is formed along each optical path comprising a respective SML set15to a respective input of optical combiner16and then to output waveguide26of chip10. The core waveguide is, for example, InGaAsP or AIInGaAs. As shown in bothFIGS. 1 and 2, between each of the SML sets15is formed a structure30providing thermal isolation or for heat dissipation, or both, between adjacent SML sets15each comprising an optically coupled laser12and modulator14. Structure30is shown for isolating entire components of sets15. However, thermal isolator/dissipater structure30can also be limited to be between any spatially neighboring components, e.g., between adjacent or neighboring DFB lasers12.

As will be seen, structure30may be an opening or via, or may be an opening or via filled with a thermal conductive material, such as a metal. However, the purposes ofFIG. 1, along withFIGS. 2-4, are to illustrate a few examples of the geometry for such thermal isolating and heat dissipating structures. Other examples will be readily come to mind by those familiar with this art upon seeing these exemplary geometries. In this regard, the geometry shown inFIG. 2comprises an opening or via, such as a rectangle30formed between adjacent SML sets15in chip10. As shown inFIG. 3, the geometry need not be continuous between sets15, but rather can be a plurality of spatially separated openings, such as circles32, or squares, triangles, polygons, or other geometrical shapes. As shown inFIG. 4, the geometry can be “wavy” or with uneven edges, e.g., a scrolling kind of geometry shown at34. These openings or vias30,32and34can extend into the chip from the bottom or from the top of chip10. Also, it is within the scope of this invention that combinations of such geometries may be employed between adjacent optical components12or14in chip10.

Reference now is made toFIG. 5which illustrates, in cross-section, chip10through either the region of either DFB lasers12or EOMs14, representing the multiple SML sets15. InFIG. 5, the core waveguide17is illustrated for each SML set15, comprising just one of a plurality of layers formed on an InP substrate38, such as by means of MOCVD or MBE. Adjacent or neighboring SML sets15are thermally isolated from one another by means of an opening40such as a trough or groove. In this manner, the heat generated from a neighboring SML set15or its components cannot directly effect the operation of another adjacent SML set15. InFIG. 5, grooves40can have any desirable geometrical shape such as discussed above in connection with the geometries ofFIGS. 2-4.

Reference is now made toFIG. 6which illustrates, in cross-section, another chip10having a plurality of structures44formed in grooves or openings42formed through the bottom of InP substrate38in combination with openings40. Openings42can have any desirable geometrical shape such as discussed above in connection with the geometries ofFIGS. 2-4. Openings42are then filled with a thermally conductive material, such as gold or aluminum. The bottom surfaces25of the formed thermal dissipaters44are place in thermal contact with a heatsink or other such submount (not shown) such as AlN, BeO, copper sandwiched BeO or CVD diamond. In this manner, the heat generated from SML sets15is thermally conducted through channels44directly to the heatsink rather than laterally to neighboring SML sets15. The use of metal filled structures44in conjunction with heatsink also applies to any of the other embodiments in this disclosure.

Reference is now made toFIG. 7which illustrates another embodiment for thermal isolation or heat dissipation comprising vias48formed through the semiconductor bulk such as by means of selective etching between adjacent SML sets15or their individual optical components12or14. As shown inFIG. 7, a selective etch is performed on one side of chip10forming a set of larger openings48A and, then, formed from the otherside of chip10forming a set of smaller openings48B. Etching is completed when through-vias48are formed. The geometric shape of vias48can have any desirable geometrical shape such as discussed above in connection with the geometries ofFIGS. 2-4. The vias48can then be maintained, as is, to provide for thermal isolation between the SML sets15or, alternatively, filed with a thermally conductive material50, as shown in FIG.7.

It should be noted that an additional advantage of the embodiment ofFIG. 7is that the on-chip, metal-filled vias48provide an electrical conduit for current supply paths between the top and bottom surface of the chip which can facilitate the wire bonding when packaging chip10in a module package. For example, the metal-filed vias can function as electrical ground paths for active components or can function, in part, as microwave shielding for adjacently disposed electro-optic modulators14to reduce RF cross-talk between the modulators.

Reference is now made to the embodiment shown inFIG. 8, which is the same as that shown inFIG. 7except that only the larger portion48A of vias48are filed with a thermally conductive material while the smaller portion48B of vias48are left as open space. Thus, in this embodiment, thermal isolation is provided between neighboring SML sets15is provided by means of openings48B, while accompanying heat dissipation is provided from between SML sets15by means of openings48A filled with thermal conductive material50.