Receiving an I/O signal in multiple voltage domains

Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

BACKGROUND

The present disclosure relates to interfacing an integrated circuit (IC or chip) with an external device, and more specifically, to level shifting an (input/output) I/O data signal to an intermediate voltage domain.

As silicon technology advances, the sustainable voltage for CMOS devices continues to decrease. While decreasing operating voltages reduce power and allow for denser logic, chip to chip communication via I/O circuits may still need to support legacy interface voltages (e.g., 3.3V LVTTL JEDEC Spec JESD8-B). However, 22 nm technology and future technology typically support 1.5V and lower devices.

One solution is to stack output devices which enable lower power chips to communicate using the legacy interface voltages. While stacking two output devices permits chips made in technologies such as 45 or 32 nm that support 1.8V devices to communicate with legacy voltages, this technique does not work for 22 nm and future fabrication techniques.

SUMMARY

One embodiment of the present disclosure is a method that includes receiving a first data signal in a first voltage domain at a input/output (I/O) pad, wherein the I/O pad is electrically connected to a node that is between a p-type transistor and an n-type transistor. The method includes applying a gate signal to both gates of the p-type and n-type transistors and controlling the gate signal such that a voltage of the gate signal follows a voltage of the first data signal unless the voltage of the first data signal exceeds an upper limit voltage and unless the voltage of the first data signal falls below a lower limit voltage, where the upper and lower limit voltages defining an intermediate voltage domain. The method includes outputting a second data signal responsive to receiving the gate signal at a receiver circuit and converting the second data signal outputted from the receiver circuit into a second voltage domain, where the converted data signal carries the same data as the first data signal.

Another embodiment of the present disclosure is an I/O module that includes an n-type transistor and a p-type transistor where a drain of the p-type transistor is coupled to a drain of the n-type transistor. The I/O module also includes an I/O pad electrically coupled to the drains of the p-type and n-type transistors where the I/O pad is configured to receive a first data signal in a first voltage domain. The I/O module also includes a voltage feedback control circuit configured to apply a gate signal to both gates of the p-type and n-type transistors and control the gate signal such that a voltage of the gate signal follows a voltage of the first data signal unless the voltage of the first data signal exceeds an upper limit voltage and unless the voltage of the first data signal falls below a lower limit voltage, where the upper and lower limit voltages defining an intermediate voltage domain. The I/O module also includes a receiver circuit configured to output a second data signal responsive to receiving the gate signal from the voltage feedback circuit and a level shifter configured to covert the second data signal into a second voltage domain, where the converted data signal carries the same data as the first data signal.

Another embodiment of the present disclosure is an integrated circuit that includes core logic and an I/O module communicatively coupled to the core logic. The I/O module includes an n-type transistor and a p-type transistor where a drain of the p-type transistor is coupled to a drain of the n-type transistor. The I/O module also includes an I/O pad electrically coupled to the drains of the p-type and n-type transistors where the I/O pad is configured to receive a first data signal in a first voltage domain. The I/O module includes a voltage feedback control circuit configured to generate a gate signal to control both gates of the p-type and n-type transistors and control the gate signal such that a voltage of the gate signal follows a voltage of the first data signal unless the voltage of the first data signal exceeds an upper limit voltage and unless the voltage of the first data signal falls below a lower limit voltages, where the upper and lower limit voltage defining an intermediate voltage domain. The I/O module also includes a receiver circuit configured to output a second data signal responsive to receiving the gate signal from the voltage feedback circuit and a level shifter configured to covert the second data signal into a second voltage domain, where the converted data signal carries the same data as the first data signal.

DETAILED DESCRIPTION

To support legacy, high-voltage communication techniques, an I/O module may include multiple level shifters that establish a plurality of voltage domains. For example, an IC may include core logic that uses small voltage signals but, in order to communicate with an external device, the IC may need to convert these small voltage signals into larger voltage signals. Stated differently, the IC converts data signals in a core logic voltage domain used by the IC to data signals in an external voltage domain. To do so, the I/O module may use at least three voltage domains—e.g., a low voltage domain, intermediate voltage domain, and a high voltage domain.

In one embodiment, when transmitting data signals received from the IC's core logic to the external device, the I/O module level shifts the data signals from the core logic voltage domain to the low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to the intermediate voltage domain. To generate data signals suitable for the external device, the I/O module level shifts the data signals from the intermediate voltage domain to both the low voltage domain and the high voltage domain. Using the data signals from both of these domains, a driver in the I/O module outputs the data signals in a voltage domain corresponding to the external device (e.g., a legacy, high-voltage domain). In this manner, the I/O module uses three stacked voltage domains in order to convert core logic data signals into data signals suitable for a high-voltage communication technique (e.g., a chip-to-chip communication technique).

FIG. 1is a block diagram of a communication system100, according to one embodiment described herein. As shown, the communication system100includes IC105and external devices135A and135B which may be, for example, separate ICs. IC105includes core logic110, voltage regulator115, and I/O modules120. The core logic110may include logic/circuitry that performs the intended function of the IC. For example, the IC105may be a general purpose processor, and as such, the core logic110may include multiple processing cores or multiple processing pipelines. Alternatively, the IC105may be an ASIC where the core logic110includes the logic for performing the ASIC's intended function. In one example, the core logic110may include all circuitry and logic gates that operate in the same voltage domain (i.e., the core logic voltage domain).

Generally, a voltage domain defines a voltage range between a minimum voltage and a maximum voltage. The data signals in the voltage domain are limited by these minimum and maximum voltages. For example, the data signals may oscillate between these voltages. For the core logic voltage domain, the minimum voltage is referred to herein as VSS and the maximum voltage is referred to as VDD. Examples of voltage ranges of the core logic voltage domain include VSS (system ground) to 1.5V, VSS to 1.2V, and VSS to 0.9V. Of course as fabrication techniques improve, the core logic voltage domain may reduce further to even smaller voltage ranges.

To communicate with the external devices135, the core logic110is coupled to the I/O modules120which permit the core logic110to transmit data to the external devices135and receive data from the external devices135. To convert the data signals of the core logic voltage domain to the voltage domain used by the external devices135(or the communication technique used transfer data between IC105and the external devices135), the I/O modules130include a plurality of level shifters125which convert data signals into three different voltage domains—i.e., a low voltage domain, an intermediate voltage domain, and a high voltage domain. A more detailed explanation of the function and arrangement of the level shifters125is provided later. Nonetheless, using the level shifters125, the I/O modules convert data signals from the core logic voltage domain to a voltage domain used at data ports130which couple to the external devices135. This voltage domain is referred to herein as the external voltage domain and ranges from VSS to VDD_IO. For example, if the 3.3V LVTTL JEDEC Spec JESD8-B is used to establish communication between IC105and the external devices135, then the external voltage domain ranges from VSS (system ground) to 3.3V.

Although two I/O modules120are shown, IC105may include any number of these modules120. The I/O modules120may connect to a wide variety of different external devices135and be configured to convert the data signals from the core logic voltage domain to different external voltage domains. That is, the external voltage domains at the data ports130may have different voltage ranges. Furthermore, multiple I/O modules120may be coupled to the same external device135rather than each I/O module120connecting to a respective device135as shown here.

To generate the three voltage domains used by the I/O modules120, the voltage regulator115outputs two voltages—VPL and VPH—where VPL represents the a low protection voltage and VPH represents a high protection voltage. The voltage regulator115provides VPL and VPH to each of the I/O modules120in the IC105, and more specifically, to the level shifters125within the modules120. In one embodiment, IC105has multiple voltage regulators115that provide VPL and VPH to different groups of I/O modules120—e.g., each voltage regulator115may provide VPL and VPH to six I/O modules120.

Although the communication system100includes I/O modules120and level shifters125on an integrated circuit105, the embodiments herein are not limited to such. That is, using three stacked voltage domains (i.e., the low, intermediate, and high voltage domains) to convert data signals may apply to other systems that do not include integrated circuits.

FIGS. 2A and 2Bare circuit diagrams of an up level shifter, according to one embodiment described herein. For convenience, this disclosure uses specific voltages to refer to the different voltage domains described herein. The minimum and maximum voltages for each of the voltage domains described above are provided in the following table.

In the embodiments that follow, it is assumed that VSS is system ground and is the smallest magnitude voltage. Moreover, the magnitude of VPH is defined as being greater than the magnitude of VPL, while VDD_IO is assumed to be the voltage with the greatest magnitude. In one embodiment, VPL is selected to be one-third of VDD_IO and VPH is selected to be two-thirds of VDD_IO but this is not a requirement. Based on these relationships, Table 1 illustrates that the core logic voltage domain, low voltage domain, intermediate voltage domain, and high voltage domain are different subsets of the external voltage domain—i.e., the first four voltage domain defined voltage ranges that are within the voltage range of the external voltage domain. Furthermore, in this example, the low voltage domain, intermediate voltage domain, and high voltage domain define voltage ranges that do not overlap. In contrast, the core logic voltage domain overlaps with the low voltage domain and may also overlap the intermediate and high voltage domains if, for example, VDD is greater than VPL and VPH.

FIG. 2Aillustrates an up level shifter200A that converts, as shown by table205, data signals from the low voltage domain to the intermediate voltage domain. The level shifter200A includes two input pads that receive complementary signals IN_VPL and INbar_VPL. In the circuit diagrams that follow, the maximum voltage is used to identify the voltage domain that contains the data signal. That is, a signal labeled “_VPL” indicates that the data signals are in the low voltage domain, “_VPH” indicates that the data signals are in the intermediate voltage domain, and “_VDD_IO” indicates that the data signals are in the high voltage domain. As such, because the input signals are labeled IN_VPL, the data signals received at the inputs of inverters INV_L1/L2range between VSS and VPL—i.e., the low voltage domain. The outputs of inverters INV_U1/U2provide two output signal OUT_VPH and OUTbar_VPH which are complementary data signals in the intermediate voltage domain.

To up-shift the received data signals into the intermediate voltage domain, level shifter200A includes two different signal paths. The first signal path (referred to herein as the low-frequency path) includes the transistors TP1, TP2, TN1, and TN2which, with the aid of transistors TP3and TP4, convert the input signals from the low voltage domain to the intermediate voltage domain. In some applications, however, this low-frequency path does not have a response time sufficient for high-speed data signals (e.g., signals greater than 200 MHz). In one embodiment, the low-frequency path generates asymmetric rise and fall times in the data signals. For example, the converted data signal may rise faster than it falls (or vice versa) by several nanoseconds. This asymmetry may mean that low-frequency path is unable to provide output data signals that are accurate copies of the data signals received at the input of inverters INV_L1/L2.

To facilitate high-speed data signals, level shifter200A includes a second signal path (referred to herein as a high-frequency path) that includes the path between the output of the inverter INV_L1(or L2), the capacitor CC1(or CC2), and the input of inverter INV_U1(or U2). If CC1and CC2were omitted, the output of INV_L1passes through TN1and TP1to drive inverter INV_U1while the output of INV_L2passes through TN2and TP2to drive INV_U2. Because the capacitors CC1and CC2are charged to a voltage, when the input signal at IN_VPL is rising, the output of INV_U1rises faster than it would if capacitor CC1was omitted from the level shifter200A. Stated differently, the high-frequency path provides a bypass path for high-frequency signals which uses the capacitors CC1and CC2to avoid the low-frequency path. Moreover, the value of the capacitors CC1and CC2may be selected to select which data signals are low frequency data signals, and thus, are routed through the low-frequency path, and which data signals are high frequency data signals and are routed through the high-frequency path. Moreover, adding the high-frequency paths allow the transistors TP1, TP2, TN1, and TN2to be smaller than they otherwise would if the high-frequency paths were omitted thereby reducing the load and improving switching.

FIG. 2Billustrates an up level shifter200B that converts, as shown by table210, signals from the intermediate voltage domain to the high voltage domain. Structurally, level shifter200B is the same as level shifter200A shown inFIG. 2A. However, the power voltages, gate voltages, and input/output signals for the level shifters200are different. As shown, the input signals IN_VPH and INbar_VPH of level shifter200B are complementary data signals in the intermediate voltage domain and the output signals OUT_VDD_IO and OUTbar_VDD_IO are complementary data signals in the high voltage domain. To perform this conversion, instead of using VPH as the power voltage at the sources of transistors TP3and TP4, VDD_IO is used. Moreover, the gate voltages for transistors TP1, TP2, TN1, and TN2are set at VPH rather than VPL as shown inFIG. 2A. By using these different voltages, the first and second signal paths discussed above convert low-speed or high-speed data signals from the intermediate voltage domain to the high voltage domain.

FIGS. 3A and 3Bare circuit diagrams of a down level shifter, according to one embodiment described herein. Specifically,FIG. 3Aillustrates a down level shifter300A with a circuit arrangement configured to convert input data signals IN_VPH and INbar_VPH in the intermediate voltage domain to data signals OUT_VPL and OUTbar_VPL in the low voltage domain. This conversion is shown graphically in table305. To shift the data signals, level shifter300A includes a low-frequency data path that includes the transistors TP1, TP2, TN3, and TN4. Because this low-frequency path may generate asymmetric rise and fall times when shifting high-speed data signals, the level shifter300A includes respective high-frequency signal paths between the inverters INV_U1/2and inverters INV_L1/2through the capacitors CC1and CC2. As discussed above, adding the high-frequency paths allows the transistors TP1, TP2, TN1, and TN2to be smaller than they otherwise would be in the absence of the high-frequency paths thereby reducing the load and improving switching.

FIG. 3Billustrates a down level shifter300B with the same structure as down level shifter300A but is operated using different power and gate voltages. That is, instead of driving the VSS voltage onto the sources of the transistors TN1and TN2as shown inFIG. 3A, in level shifter300B the VPL voltage is used. Additional, the gates of transistors TP1, TP2, TN3, and TN4are driven to VPH instead of VPL. As such, when receiving data signals IN_VDD_IO and INbar_VDD_IO in the high voltage domain at the input interfaces, the level shifter300B converts these data signals into the intermediate voltage domain as shown by table310. These shifted data signals are then provided as output signals OUT_VPH and OUTbar_VPH.

FIG. 4is a block diagram of a communication system400for level shifting an output signal into different voltage domains, according to one embodiment described herein. As shown, system400includes core logic110and I/O module120which may be located on the same IC or located on different ICs or devices. Generally, the data signals flow from the core logic110, through the I/O module120, and out to an external device. As such, system400illustrates only one-directional traffic flow between the core logic110and the external device.FIG. 5, on the other hand, illustrates how data is transmitted in the reverse direction—i.e., from the external device to the core logic110.

The data signals transmitted from the core logic110to the I/O module120using data out interface401are in the core logic voltage domain405—i.e., the data signals range from VSS to VDD. As such, the input interface of up level shifter (LS)200_1is in the core logic voltage domain405. The up LS200_1then converts the data signals from the core logic domain405to the low voltage domain410. That is, the output of LS200_1is the data signals in the low voltage domain410.

Using up LS200_2, the I/O module120shifts the data signals from the low voltage domain410to the intermediate voltage domain415. These data signals are the split and sent to both up LS200_3and down LS300_1. The up LS200_3shifts the data signals from the intermediate voltage domain415to the high voltage domain420. The down LS300_1, in contrast, shifts the data signals back down to the low voltage domain410. As such, the data signals outputted by down LS300_1are the same, or substantially similar to, the data signals outputted by the up LS200_1. Stated differently, the data signals are shifted by LS200_2from the low voltage domain410to the intermediate voltage domain415and then subsequently shifted back down from the intermediate voltage domain415to the low voltage domain410. Although this may seem unnecessary since the output of LS200_1could be forwarded to the input of driver circuit425thereby omitting the down LS300_1, the advantage of the arrangement shown here is that the down LS300_1mirrors the delay introduced on the signal by the up LS200_3. That is, if the output of LS200_1was directly forwarded to the input of the driver circuit425, because of the delay introduced by LS200_2and200_3, the arriving data signals in the high voltage domain420would not arrive at the circuit425as the corresponding data signals in the low voltage domain410. Moreover, using other delay elements such as inverters to mirror the delay introduced by LS200_2and200_3may be infeasible and take up too much real estate on the IC. However, by first shifting the data signal to the intermediate voltage domain415and then down shifting those signals back into the low voltage domain410, the I/O module120can provide data signals that are substantially aligned, but in different voltage domains, at the inputs of the driver circuit425.

As will be described in more detail below, the driver circuit425uses the data signals received from LS200_3in the high voltage domain420(e.g., VPH to VDD_IO) and the data signals received from LS300_1in the low voltage domain410(e.g., VSS to VPL) to generate data signals in the external voltage domain (e.g., VSS to VDD_IO). As such, in this manner, the same data outputted by the core logic110is forwarded to the external device except that the data signals conveying this data is now in the external voltage domain (e.g., VSS to 3.3V) rather than the core logic voltage domain405(e.g., VSS to 1.2V).

FIG. 5is a block diagram of a communication system500for level shifting a received signal into different voltage domains, according to one embodiment described herein. Unlike inFIG. 4where data flows from the core logic110to the external device, in system500, data flows from the external device to the core logic110. In this case, the I/O module120converts the data signals received from the external device from the external voltage domain to data signals in the core logic voltage domain405. As will be described in more detail later, a voltage feedback control505shifts received data signals from the external voltage domain to the intermediate voltage domain415and transmits these shifted data signals to a Schmitt trigger510. In one embodiment, the values of VPL, VPH, and VDD_IO are selected such that the voltage feedback control505receives the data signals from the external device in the intermediate voltage domain which is the middle portion of the external voltage domain. Stated differently, the voltage range of the intermediate voltage domain (VPL-VPH) is the middle region of the voltage range of the external voltage domain (VSS-VDD_IO). For example, VPL may be one-third the value of VDD_IO while VPH is two-thirds the value of VDD_IO. By receiving in the intermediate voltage domain rather than in the high or low voltage domains, the I/O module120is able to avoid additional complexity needed in order to re-shape signals that become skewed when received in voltage domains that are not centered with the external voltage domain. A more detailed explanation of how the driver circuit425may aid the voltage feedback control505to receive the signals in the intermediate voltage domain415is provided below inFIGS. 6A and 6B.

The voltage feedback control505forwards the data signals to a Schmitt trigger510. In one embodiment, the Schmitt trigger510is used to reduce the noise in the received data signals. Moreover, although the trigger510is shown as operating in the intermediate voltage domain415, in other embodiments it may be advantageous to convert the received data signals into the high or low voltage domains before sending these signals to the Schmitt trigger510. Further still, in one embodiment, the data signals outputted from the voltage feedback control505are shifted into both the high and low voltage domains and are passed through respective Schmitt triggers510in each of these domains. Although a Schmitt trigger510is shown, the present disclosure is not limited to such. For example, the Schmitt trigger may be replaced by a receive buffer that is in the intermediate voltage domain. As such, the output of the voltage feedback control505may be fed into a receiver circuit which may be a Schmitt trigger or a buffer whose output is coupled to LS300_2.

The output of the Schmitt trigger510is provided to the down LS300_2which shifts the data signals from the intermediate voltage domain415to the core logic voltage domain405. The down-shifted data signals are then provided to the core logic110via data interface515. In this manner, data received at the external voltage domain is converted into the intermediate voltage domain415that may be centered in the external voltage domain before being converted to the core logic voltage domain405.

FIGS. 6A and 6Billustrate a circuit diagram of the I/O module120for level shifting I/O signals into different voltage domains, according to one embodiment described herein. More specifically,FIGS. 6A and 6Binclude the circuitry that may be used to perform the transmitting and receiving functions shown inFIGS. 4 and 5. That is, the circuitry in I/O module120is capable of both transmitting data from the core logic to the external device and transmitting data from the external device to the core logic. As such, the same level shifters shown inFIGS. 4 and 5are provided with the same reference numbers here (e.g., level shifters200_1,200_2,200_3,300_1, and300_2).

The I/O module120receives data signals from the core logic on data pad600. The I/O module then uses the two inverters to generate complementary signals that are then provided to level shifter200_1. As discussed inFIG. 4, level shifter200_1shifts the complementary data signals from the core logic voltage domain405into the low voltage domain410. The resulting data signals are received by level shifter200_2which converts the signals into the intermediate voltage domain415. The output of level shifter200_2is coupled to both up level shifter200_3and down level shifter300_1which output data signals in the high voltage domain and low voltage domain, respectively. As discussed inFIG. 4, converting the data signals from the low voltage domain to the intermediate voltage domain only to then reconvert the signals to the low voltage domain may be performed to align or synchronize the data signals in the different voltage domains without having to use other delay elements (e.g., a daisy chain of inverters). However, other types of delay elements (e.g., inverters) may still be used to synchronize the signals if the output of level shifter200_3and level shifter300_1are not sufficiently aligned.

The driver circuit425includes a NAND gate that receives the data signals in the high voltage domain420and a NOR gate that receives the data signals in the low voltage domain410. Moreover, in order to tri-state the circuit425, the I/O module120includes an enable pad605that receives an enable signal from, e.g., the core logic. The I/O module level shifts the received enable signal in the same manner as the data signal. As shown, an up level shifter200_4converts the enable signal to the low voltage domain410, while up level shifter200_5converts the enable signal into the intermediate voltage domain415. To maintain alignment, the down level shifter300_3converts the enable signal back into the low level domain410while the up level shifter200_6converts the enable signal into the high voltage domain420. Using the NAND and NOR logic, the driver circuit425uses the enable signal to drive the data signals onto the output pad615only if the enable signal is high—i.e., the circuit425operates in the driver mode. Because the source of the uppermost transistor in the driver circuit425is coupled to VDD_IO and the source of the lowermost transistor is coupled to VSS, the output data signal is in the external voltage domain (i.e., VSS to VDD_IO). Furthermore, for the data signals, only the normal data signals outputted from level shifters200_3and300_1are provided to the NAND and NOR gates (i.e., the complementary data signals are ignored). In contrast, for the enable signal, the normal enable signal is provided to the NAND gate while the complementary enable signal is provided to the NOR gate.

If the enable signal is low, the circuit425does not drive data signals onto pad615—i.e., the circuit425operates in an idle or receiver mode. Meanwhile, the voltage feedback control505and Schmitt trigger510can receive data signals from the external device on the pad615. When receiving data, the voltage feedback control505provides control signals (i.e., gate signals) that control the middle two transistors in the driver circuit425. Stated differently, the control signals force the gates of the middle two transistors to follow the voltage at the output pad615except when (i) the voltage at the pad615falls below VPL in which case the voltage feedback control505fixes the control signals at VPL (the minimum voltage in the intermediate voltage domain415) and (ii) the voltage at pad615rises above VPH in which case the voltage feedback control505fixes the control signals at VPH (the maximum voltage in the intermediate voltage domain415). In this way, the voltage feedback control505permits the voltage of the control signals to follow the voltage on pad615unless the voltage at pad615goes below VPL or above VPH, in which case the voltage is clipped and held at either VPL or VPH.

Moreover, in this embodiment, the three outputs of the feedback control505(i.e., the two gate control signals and the output to node C which is the input to the Schmitt trigger510) are all the same voltage. That is, the output signals follow the voltage on pad615except when the pad voltage exceeds VPH or falls below VPL in which case the voltage is clipped. In one embodiment, the voltage feedback control505and the Schmitt trigger510function as a receiver that receives the external data in the intermediate voltage domain. As described above, complexity of the driver/receiver circuit425is reduced if the voltage range of the intermediate voltage domain415is centered within the external voltage range relative to receiving in a non-centered voltage range. One embodiment of a voltage feedback control circuit505is provided in U.S. patent application Ser. No. 13/443,209 (Publication No. US 2013/0265085) entitled “IMPLEMENTING VOLTAGE FEEDBACK GATE PROTECTION FOR CMOS OUTPUT DRIVERS” which is herein incorporated by reference in its entirety. The output of the Schmitt trigger510is then converted from the intermediate voltage domain415to the core logic voltage domain405using level shifter300_2. The I/O module120data signals are transmitted to the core logic using the interface610.

FIG. 7is a flowchart700for level shifting an output signal into a different voltage domain, according to one embodiment described herein. At block705, the I/O module receives a data signal from core logic of an IC. As described above, the voltage domain used by the core logic may be different than the voltage domain of a communication technique used by the I/O module to transmit the data signal to a different device. Although in the present disclosure the different device is described as being external to the IC, this is not a requirement. For example, the I/O module may instead serve as an interface between two different sub-systems in the same device which operate using two different voltage domains.

At block710, the I/O module level shifts the data from the core logic voltage domain to the intermediate voltage domain. In one embodiment, the I/O module uses three different voltage domains where the intermediate voltage domain defines a voltage range that is between the respective voltage ranges of the low and high voltage domains. In one example, the voltage ranges of the low, intermediate, and high voltage domains are continuous such that the maximum voltage of the low voltage domain is the minimum voltage of the intermediate voltage domain and the maximum voltage of the intermediate voltage domain is the minimum voltage of the high voltage domain.

At block715, the I/O module level shifts the data from the intermediate domain to the low voltage domain and the high voltage domain. In one embodiment, the output of the level shifter (or shifters) used at block710may be split such that the output is coupled to both an up shifter for converting the data signal to the high voltage domain and a down shifter for converting the data signals to the low voltage domain. As such, the conversion from the intermediate voltage domain to the high voltage domain and the conversion form the intermediate voltage domain to the low voltage domain may be performed in parallel. Moreover, by shifting the data signal from the low to intermediate voltage domains at block710and shifting the data signal from the intermediate voltage domain back down to the low voltage domain, the I/O module may maintain the synchronization or alignment of the data signals such that the two data signals convey the same data even though the data signals are in different voltage domains.

At block720, the I/O module generates output data signals using the data in the low voltage domain and the data signals in the high voltage domain. For example, the I/O module may include a driver circuit that uses the two data signals to generate the output data signal in the voltage domain of the communication technique used to transmit the data signal to the external device.

FIG. 8is a flowchart800for level shifting a received signal into a different voltage domain, according to one embodiment described herein. At block805, the I/O module receives data signals intended for the core logic that are in a first voltage domain that is different from the voltage domain of the core logic. For example, the first voltage domain may be the voltage domain used by the communication technique that transmitted the data signals to the I/O module or the voltage domain of an external device coupled to the I/O module.

At block810, the I/O module converts the received data signals using the voltage feedback control into the intermediate voltage domain. In one embodiment, the voltage range of the intermediate voltage domain is a subset of the voltage range of the first voltage domain. For example, the voltage range of the first voltage domain may be between system ground and 3.3V while the voltage range of the intermediate voltage range is between 1-2V. Further still, the range of the intermediate voltage domain may be centered within the range of the first voltage domain. Using the example above, the voltage range of the intermediate voltage domain may be between approximately 1.1-2.2V. As such, both the first and intermediate voltage domains are centered at the same voltage—i.e., 1.65V. By doing so, the receiver circuit used to detect the signals in the I/O module may have reduced complexity when compared to a receiver circuit that uses a non-centered voltage domain. At block815, the I/O module shifts the data signals from the intermediate voltage domain to the voltage domain of the core logic.