Duty cycle detector and phase difference detector

A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using the first inverters, at least one inverter among the first inverters being enabled during a time interval when a clock has a first value, a second ring oscillator including an odd number of second inverters and suitable for generating a second periodic signal using the second inverters, at least one inverter among the second inverters being enabled during a time interval when the clock has a second value. The duty cycle detector further includes a frequency comparator suitable for comparing a frequency of the first periodic signal with a frequency of the second periodic signal and generating a duty cycle detection signal of the clock.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean Patent Application No. 10-2017-0140210, filed on Oct. 26, 2017, which is incorporated herein by reference in its entirety.

BACKGROUND

Illustrative embodiments of the present disclosure relate to a duty cycle detector for detecting a duty cycle of a clock, and a phase difference detector for detecting a phase difference between clocks.

2. Description of the Related Art

As the data transfer rates of diverse integrated circuits, such as a memory, are increased, using a clock of a high frequency to transfer data between integrated circuits becomes increasingly burdensome. In this respect, multi-phase clocks of lower frequencies than the frequency of the clock used for data transfer between integrated circuits may be used in an integrated circuit chip.

FIG. 1illustrates an example of multi-phase clocks. Referring toFIG. 1, four clocks ICK, QCK, IBCK, and QBCK may have a phase difference of approximately 90 degrees (°). Rising edges of the clock ICK and the clock QCK may have a phase difference of approximately 90°, and rising edges of the clock QCK and the clock IBCK may have a phase difference of approximately 90°. Also, the rising edges of the clock IBCK and the clock QBCK may have a phase difference of approximately 90°. Also, all the four clocks ICK, QCK, IBCK, and QBCK may have a duty cycle ratio of approximately 50%. In short, all the four clocks ICK, QCK, IBCK, and QBCK may have a high pulse width that is substantially the same as a low pulse width.

FIG. 1illustrates an ideal phase difference and an ideal duty cycle ratio of the multi-phase clocks ICK, QCK, IBCK, and QBCK. When the multi-phase clocks ICK, QCK, IBCK, and QBCK are used in an actual integrated circuit, the phase difference among the clocks ICK, QCK, IBCK, and QBCK may not be maintained at approximately 90° and the duty cycle ratio of the clocks ICK, QCK, IBCK, and QBCK may not be maintained at approximately 50% due to various noise in the integrated circuit.

In order to maintain the duty cycle ratio of the clocks ICK, QCK, IBCK, and QBCK at approximately 50% and maintain the phase difference among the clocks ICK, QCK, IBCK, and QBCK at approximately 90°, it is desirable to develop a technology for accurately detecting a duty of a clock and a technology for accurately detecting the phase difference between clocks.

SUMMARY

Embodiments of the present disclosure are directed to a technology for accurately detecting a duty cycle ratio of a clock and a technology for accurately detecting a phase difference between clocks.

In accordance with an embodiment of the present disclosure, a duty cycle detector includes: a first ring oscillator including an odd number of first inverters and suitable for generating a first periodic signal using the first inverters, wherein at least one inverter among the first inverters is enabled during a time interval when a clock has a first value; a second ring oscillator including an odd number of second inverters and suitable for generating a second periodic signal using the second inverters, wherein at least one inverter among the second inverters is enabled during a time interval when the clock has a second value; and a frequency comparator suitable for comparing a frequency of the first periodic signal with a frequency of the second periodic signal and generating a duty cycle detection signal of the clock.

In accordance with another embodiment of the present disclosure, a duty cycle detector includes: a ring oscillator suitable for including an odd number of inverters and suitable for generating a periodic signal using the inverters, wherein at least one inverter among the inverters is enabled during a first time interval when a clock has a first value in a first mode and enabled during a second time interval when the clock has a second value in a second mode; and a frequency comparator suitable for comparing a frequency of the periodic signal generated in the first mode with a frequency of the periodic signal generated in the second mode and generating a duty cycle detection signal of the clock.

In accordance with yet another embodiment of the present disclosure, a phase difference detector includes: a first ring oscillator suitable for including an odd number of first inverters, and suitable for generating a first periodic signal using the first inverters, wherein at least one first inverter among the first inverters is enabled in during a first time interval when a first clock and a second clock have different logic values; a second ring oscillator suitable for including an odd number of second inverters and suitable for generating a second periodic signal using the second inverters, wherein at least one inverter among the second inverters is enabled during a second time interval when the first clock and the second have a common logic value; and a frequency comparator suitable for comparing a frequency of the first periodic signal with a frequency of the second periodic signal and generating a phase difference detection signal indicative of a phase difference between the first clock and the second clock.

In accordance with still another embodiment of the present disclosure, a phase difference detector includes: a ring oscillator suitable for including an odd number of inverters and generating a periodic signal by using the inverters, wherein at least one inverter among the inverters is enabled during a first time interval when a first clock and a second clock have different logic values in a first mode and enabled in a second time interval when the first clock and the second clock have a common logic value in a second mode; and a frequency comparator suitable for comparing a frequency of the periodic signal generated in the first mode with a frequency of the periodic signal generated in the second mode and generating a phase difference detection signal between the first clock and the second clock.

DETAILED DESCRIPTION

FIG. 2is a block diagram illustrating a duty cycle detector200in accordance with an embodiment of the present disclosure. Referring toFIG. 2, the duty cycle detector200may include a first ring oscillator210, a second ring oscillator220, and a frequency comparator230.

The first ring oscillator210may generate a first periodic wave (or a first periodic signal) LCK having a frequency which is in proportion to a low pulse width of a clock ICK, which is equal to a high pulse width of an inverted clock IBCK. The first ring oscillator210may include an odd number 2N−1 of first inverters, for example, three first inverters211_0to211_2(where N is an integer equal to or greater than ‘1’), a first low-pass filter (LPF)212, and a first Schmitt trigger circuit213.

The first inverters211_0to211_2may be coupled in a ring to be used for generation of the first periodic wave LCK. An inverter211_2among the first inverters211_0to211_2may be enabled in a section (that is, a time interval) where the clock ICK has a first value (e.g., a logic low level) and disabled when the clock ICK has a second value (e.g., a logic high level). Equivalently, the inverter211_2may be enabled in a section where the inverted clock IBCK has the second value and disabled when the inverted clock IBCK has the first value. Since the inverter211_2is enabled in the section where the clock ICK is in a logic low level and disabled otherwise, the length (or a duration) of the section (that is, a time interval) where the clock ICK is in a logic low level may affect the frequency of the first periodic wave LCK which is generated by the first ring oscillator210. Herein, althoughFIG. 2shows an example where the inverter211_2among the first inverters211_0to211_2is enabled in the section where the clock ICK is in a logic low level, embodiments of the present disclosure are not limited thereto. In an embodiment, one or more of the other first inverters211_0and211_1may be designed to be enabled in the section where the clock ICK has a logic low level and disabled otherwise.

A first end (e.g., a front end) of the first low-pass filter212may be coupled to an output terminal of the inverter211_2. A node A at a second end (e.g., a rear end) of the first low-pass filter212may have a voltage that is gradually changed due to a filtering operation of the first low-pass filter212. The first low-pass filter212may include a resistor and a capacitor.

The first Schmitt trigger circuit213may be coupled to the node A at the rear end of the first low-pass filter212. The first Schmitt trigger circuit213transitions its output signal into a logic high level when the voltage of the node A is higher than a first given value, which may be equal to a reference value plus an offset value α (i.e., the reference value+the offset value α). The first Schmitt trigger circuit213transitions its output signal into a logic low level when the voltage of the node A is lower than a second given value, which may be equal to the reference value minus the offset value α (i.e., the reference value−the offset value α). In an embodiment, the first and second given values are predetermine values. Herein, the reference value may be a reference value for determining logic levels of signals output from general devices, such as the first inverters211_0to211_2, between a logic high level and a logic low level.

The first low-pass filter212and the first Schmitt trigger circuit213are used to accumulate the influence of the length of a section where the clock ICK is in a logic low level on the frequency of the first periodic wave LCK. In another embodiment, the first low-pass filter212and the first Schmitt trigger circuit213may be omitted from the first ring oscillator210.

The second ring oscillator220may generate a second periodic wave (or a second periodic signal) HCK having a frequency which is in proportion to a high pulse width of the clock ICK. The second ring oscillator220may include an odd number 2N−1 of second inverters, for example, three second inverters221_0to221_2(where N is an integer equal to or greater than ‘1’), a second low-pass filter222, and a second Schmitt trigger circuit223.

The second inverters221_0to221_2may be coupled in a ring to be used for generation of the second periodic wave HCK. An inverter221_2among the second inverters221_0to221_2may be enabled in a section where the clock ICK is in a logic high level and disabled in a section where the clock ICK is in a logic low level. Since the inverter221_2is enabled in the section where the clock ICK is in a logic high level, the length of the section where the clock ICK is in a logic high level may affect the frequency of the second periodic wave HCK which is generated in the second ring oscillator220. Herein, althoughFIG. 2shows an example where the inverter221_2among the second inverters221_0to221_2is enabled in the section where the clock ICK is in a logic high level, embodiments of the present disclosure are not limited thereto. In an embodiment, the other second inverters221_0and221_1may be designed to be enabled in the section where the clock ICK is in a logic high level and disabled otherwise.

A first end (e.g., a front end) of the second low-pass filter222may be coupled to an output terminal of the inverter221_2. A node B at a second end (e.g., a rear end) of the second low-pass filter222may be gradually changed due to a filtering operation of the second low-pass filter222. The second low-pass filter222may include a resistor and a capacitor.

The second Schmitt trigger circuit223may be coupled to the node B at the rear end of the second low-pass filter222. The second Schmitt trigger circuit223transitions its output signal into a logic high level when the voltage at the node B is higher than a first given value, which is equal to a reference value plus an offset value α (i.e., the reference value+the offset value α). The second Schmitt trigger circuit223transitions its output signal into a logic low level when the voltage at the node B is lower than a second given value, which is equal to the reference value minus the offset value α (i.e., the reference value−the offset value α). Herein, the reference value may be a reference value for determining logic levels of signals output from general devices, such as the second inverters221_0to221_2, between a logic high level and a logic low level.

When the first low-pass filter212and the first Schmitt trigger circuit213are omitted from the first ring oscillator210, the second low-pass filter222and the second Schmitt trigger circuit223may be omitted from the second ring oscillator220.

The frequency comparator230may compare the frequency of the first periodic wave LCK generated by the first ring oscillator210with the frequency of the second periodic wave HCK generated by the second ring oscillator220and generate a duty cycle detection signal UP/DN indicating a duty cycle ratio of the clock ICK. When the frequency of the first periodic wave LCK is higher than the frequency of the second periodic wave HCK, that is, when a low pulse width (or an off-time duration) of the clock ICK is longer than a high pulse width (or an on-time duration) of the clock ICK, the frequency comparator230may produce the duty cycle detection signal UP/DN of a first value (e.g., a logic high level). Also, when the frequency of the first periodic wave LCK is lower than the frequency of the second periodic wave HCK, that is, when a high pulse width of the clock ICK is longer than a low pulse width of the clock ICK, the frequency comparator230may produce the duty cycle detection result UP/DN of a second value (e.g., a logic low level).

The frequency comparator230may include a first frequency detector231, a second frequency detector232, and a code comparator233. The first frequency detector231may detect the frequency of the first periodic wave LCK and generate a first frequency code FREQ_0which represents the detected frequency of the first periodic wave LCK. The second frequency detector232may detect the frequency of the second periodic wave HCK and generate a second frequency code FREQ_1which represents the detected frequency of the second periodic wave HCK. In an embodiment, the first frequency code FREQ_0may have a value that is proportional to the detected frequency of the first periodic wave LCK, and the second frequency code FREQ_1may have a value that is proportional to the detected frequency of the second periodic wave HCK. The code comparator233may compare the first frequency code FREQ_0and the second frequency code FREQ_1with each other and generate the duty cycle detection signal UP/DN. In an embodiment, the duty cycle detection signal UP/DN may have a logic high value when the value of the first frequency code FREQ_0is greater than the value of the second frequency code FREQ_1. The duty cycle detection signal UP/DN may be transferred to a duty cycle correction circuit (not shown) of diverse forms and used to correct the duty cycle of the clock ICK.

FIG. 3illustrates an operation of the first ring oscillator210and an operation of the second ring oscillator220shown inFIG. 2, in accordance with an embodiment.

Referring toFIG. 3, the ratio of the high pulse width and the low pulse width of the clock ICK is approximately 6:4.

The inverter211_2among the first inverters211-0to211-2of the first ring oscillator210may be enabled during a section where the clock ICK is in a logic low level, that is, during an off-time duration of the clock ICK, and change the voltage at the node A. Since the inverter211_2of the first ring oscillator210may be disabled during a section where the clock ICK is in a logic high level, that is, during an on-time duration of the clock ICK, the voltage at the node A may not be changed during a section where the clock ICK is in a logic high level.

The inverter221_2among the second inverters221_0to221_2of the second ring oscillator220may be enabled during a section where the clock ICK is in a logic high level, that is, during the on-time duration of the clock ICK, and change the voltage at the node B. Since the inverter221_2of the second ring oscillator220may be disabled during a section where the clock ICK is in a logic low level, that is, during the off-time duration of the clock ICK, the voltage at the node B may not be changed during a section where the clock ICK is in a logic low level.

In other words, the voltage at the node A is changed during the off-time duration of the clock ICK and maintained during the on-time duration of the clock ICK, while the voltage at the node B is changed during the on-time duration of the clock ICK and maintained during the off-time duration of the clock ICK. In the embodiment shown inFIG. 3, the ratio of the on-time duration to the off-time duration of the clock ICK is substantially equal to 6:4. After all, a total time taken for the voltage at the node A to transition from a logic high level into a logic low level and then transition again from the logic low level into the logic high level may be longer than a total time taken for the voltage at the node B to transition from a logic high level into a logic low level and then transition again from the logic low level into the logic high level. In short, a first cycle (or a first period) of the first periodic wave LCK corresponding to the voltage at the node A may be longer than a first cycle of the second periodic wave HCK corresponding to the voltage at the node B. In other words, the frequency of the first periodic wave LCK corresponding to the voltage of the node A may be lower than the frequency of the second periodic wave HCK corresponding to the voltage at the node B.

Referring toFIG. 3, it may be seen that when the high pulse width of the clock ICK is longer than the low pulse width of the clock ICK, the frequency of the first periodic wave LCK is lower than the frequency of the second periodic wave HCK. In another example, when the low pulse width of the clock ICK is longer than the high pulse width of the clock ICK, the frequency of the first periodic wave LCK is higher than the frequency of the second periodic wave HCK.

FIG. 4is a schematic diagram illustrating the inverter (or a first inverter)211_2and the inverter (or a second inverter)221_2shown inFIG. 2.

The first inverter211_2may include first and second PMOS transistors411and412that are serially coupled between a power source voltage terminal (or a power supply voltage) VDD and an output node OUT1of the first inverter211_2, and first and second NMOS transistors413and414that are serially coupled between a ground voltage terminal (or a ground) and the output node OUT1of the first inverter211_2. The clock ICK may be inputted into a gate of the first PMOS transistor411, and the inverted clock IBCK may be inputted into a gate of the second NMOS transistor414. The gates of the second PMOS transistor412and the first NMOS transistor413may be coupled to an input node IN1of the first inverter211_2. When the clock ICK is in a logic low level, the first PMOS transistor411and the second NMOS transistor414are turned on to enable the first inverter211_2and thereby invert a signal at the input node IN1and output the inverted signal at the output node OUT1. When the clock ICK is in a logic high level, the first PMOS transistor411and the second NMOS transistor414are turned off to disable the first inverter211_2.

The second inverter221_2may include third and fourth PMOS transistors421and422that are serially coupled between the power source voltage terminal VDD and an output node OUT2of the second inverter221_2, and third and fourth NMOS transistors423and424that are serially coupled between the ground voltage terminal and the output node OUT2of the second inverter221_2. The inverted clock IBCK may be inputted into a gate of the third PMOS transistor421, and the clock ICK may be inputted into a gate of the fourth NMOS transistor424. The gates of the fourth PMOS transistor422and the third NMOS transistor423may be coupled to an input node IN2of the second inverter221_2. When the clock ICK is in a logic high level, the third PMOS transistor421and the fourth NMOS transistor424are turned on to enable the second inverter221_2and thereby invert a signal at the input node IN2and output the inverted signal at the output node OUT2. When the clock ICK is in a logic low level, the third PMOS transistor421and the fourth NMOS transistor424are turned off to disable the second inverter221_2.

FIG. 5is a block diagram illustrating a duty cycle detector500in accordance with another embodiment of the present disclosure.

Referring toFIG. 5, the duty cycle detector500may include a ring oscillator510and a frequency comparator530.

The ring oscillator510may generate a periodic wave (or a periodic signal) LHCK having a frequency which is in proportion to a low pulse width of the clock ICK, that is, a high pulse width of the inverted clock IBCK in a first mode, and generate a periodic wave LHCK having a frequency which is in proportion to a high pulse width of the clock ICK in a second mode. The ring oscillator510may operate in the substantially same manner as the first ring oscillator210ofFIG. 2in the first mode and operate in the substantially same manner as the second ring oscillator220ofFIG. 2in the second mode.

The ring oscillator510may include an odd number 2N−1 of inverters, for example, three inverters511_0to511_2(where N is an integer equal to or greater than ‘1’), a low-pass filter (LPF)512, a Schmitt trigger circuit513, and a selector514.

The inverters511_0to511_2may be coupled in a form of a ring to be used for generation of the periodic wave LHCK. An inverter511_2among the inverters511_0to511_2may be enabled in a section where an output signal of the selector514is in a logic high level, and disabled in a section where an output signal of the selector514is in a logic low level. The selector514may select and output the inverted clock IBCK when a first mode signal MODE1is enabled, and the selector514may select and output the clock ICK when a second mode signal MODE2is enabled. Therefore, the inverter511_2may be enabled in the section where the clock ICK is in a logic low level in the first mode, and the inverter511_2may be enabled in the section where the clock ICK is in a logic high level in the second mode. Herein, althoughFIG. 5shows an example where the inverter511_2among the inverters511_0to511_2is enabled in response to the output of the selector514, embodiments of the present disclosure are not limited thereto. In an embodiment, the remaining inverters511_0and511_1may be enabled in response to the output of the selector514.

A first end (e.g., a front end) of the low-pass filter512may be coupled to an output terminal of the inverter511_2. A node A at a second end (e.g., a rear end) of the low-pass filter512may have a voltage that is gradually changed due to a filtering operation of the low-pass filter512. The low-pass filter512may include a resistor and a capacitor.

The Schmitt trigger circuit513may be coupled to the node A at the rear end of the low-pass filter512. The Schmitt trigger circuit513transitions its output signal into a logic high level when the voltage at the node A is higher than a first given value, which is equal to a reference value plus an offset value α (i.e., the reference value+the offset value α). The Schmitt trigger circuit513transitions its output signal into a logic low level when the voltage at the node A is lower than a second given value, which is equal to the reference value minus the offset value α (i.e., the reference value−the offset value α). Herein, the reference value may be a reference value for determining logic levels of signals output from general devices, such as the inverters511_0to511_2, between a logic high level and a logic low level.

The low-pass filter512and the Schmitt trigger circuit513are used to accumulate the influence of the output of the selector514on the frequency of the periodic wave LHCK. In another embodiment, the low-pass filter512and the Schmitt trigger circuit513may be omitted from the ring oscillator510.

The frequency comparator530may compare the frequency of the periodic wave LHCK generated in the first mode with the frequency of the periodic wave LHCK generated in the second mode and generate a duty cycle detection signal UP/DN indicating a duty cycle ratio of the clock ICK. When the frequency of the periodic wave LHCK generated in the first mode is higher than the frequency of the periodic wave LHCK generated in the second mode, that is, when a low pulse width of the clock ICK is longer than a high pulse width of the clock ICK, the frequency comparator530may produce the duty cycle detection signal UP/DN of a first value (e.g., a logic high level). Also, when the frequency of the periodic wave LHCK generated in the first mode is lower than the frequency of the periodic wave LHCK generated in the second mode, that is, when a high pulse width of the clock ICK is longer than a low pulse width of the clock ICK, the frequency comparator530may produce the duty cycle detection result UP/DN of a second value (e.g., a logic low level).

The frequency comparator530may include a first frequency detector531, a second frequency detector532, and a code comparator533. The first frequency detector531may detect the frequency of the periodic wave LHCK in the first mode where the first mode signal MODE1is enabled and generate a first frequency code FREQ_0. The second frequency detector532may detect the frequency of the periodic wave LHCK in the second mode where the second mode signal MODE2is enabled and generate a second frequency code FREQ_1. The code comparator533may compare the first frequency code FREQ_0and the second frequency code FREQ_1with each other and generate the duty cycle detection signal UP/DN. The duty cycle detection signal UP/DN may be transferred to a duty cycle correction circuit (not shown) of diverse forms and used to correct the duty cycle of the clock ICK.

FIG. 6illustrates a first clock ICK, a second clock QCK, and signals XOR and XNOR that are respectively obtained by performing an XOR operation and an XNOR operation on the first clock ICK and the second clock QCK.

The first clock ICK and the second clock QCK are clocks having a phase difference of approximately 90° from each other. It may be determined whether the phase difference between the first clock ICK and the second clock QCK is greater than approximately 90° or not by comparing a high pulse width (or an on-time duration) of a signal XOR obtained by performing an XOR operation on the first clock ICK and the second clock QCK with a high pulse width (or an on-time duration) of a signal XNOR obtained by performing an XNOR operation on the first clock ICK and the second clock QCK.

When the phase difference between the first clock ICK and the second clock QCK is substantially smaller than 90°, the high pulse width of the signal XNOR may be longer than the high pulse width of the signal XOR as shown inFIG. 6. Conversely, when the phase difference between the first clock ICK and the second clock QCK is substantially greater than 90°, the high pulse width of the signal XOR may be longer than the high pulse width of the signal XNOR differently fromFIG. 6When this principle is applied to the duty detection circuit200shown inFIG. 2, a phase difference detector for detecting whether the phase difference between the first clock ICK and the second clock QCK is substantially greater than or smaller than 90° may be implemented.

FIG. 7is a block diagram illustrating a phase difference detector700in accordance with an embodiment of the present disclosure. The phase difference detector700may detect whether a phase difference between a first clock ICK and a second clock QCK is substantially greater than or smaller than 90°.

Referring toFIG. 7, the phase difference detector700may include a first ring oscillator710, a second ring oscillator720, and a frequency comparator730.

The first ring oscillator710may generate a first periodic wave (or a first periodic signal) LCK having a frequency which is in proportion to a length of a section where the first clock ICK and the second clock QCK have different values. In an embodiment, the first periodic wave LCK has a frequency that is proportional to an on-time duration of a signal SXOR when the first clock ICK has a different logic value from that of the second clock QCK. The first ring oscillator710may include an odd number 2N−1 of first inverters711_0to711_2(where N is an integer equal to or greater than ‘1’), a first low-pass filter (LPF)712, and a first Schmitt trigger circuit713, and an XOR gate714.

The first inverters711_0to711_2may be coupled in a form of a ring to be used for generation of the first periodic wave LCK. An inverter711_2among the first inverters711_0to711_2may be enabled in a section where the output signal SXOR of the XOR gate714has a first value (e.g., a logic high level). Because the output signal SXOR of the XOR gate714is in a logic high level in a section where the first clock ICK and the second clock QCK are of different levels, the length of the section where the first clock ICK and the second clock QCK are of different levels may affect the frequency of the first periodic wave LCK generated in the first ring oscillator710. Herein, althoughFIG. 7shows an example where the inverter711_2among the first inverters711_0to711_2is enabled in response to the output signal SXOR of the XOR gate714, embodiments of the present disclosure are not limited thereto. In an embodiment, the remaining first inverters711_0and711_1may be enabled in response to the output signal SXOR of the XOR gate714. The inverter711_2may have substantially the same configuration as the first inverter211_2shown inFIG. 4.

A first end (e.g., a front end) of the first low-pass filter712may be coupled to an output terminal of the inverter711_2. A node A at a second end (e.g., the rear end) of the first low-pass filter712may be gradually changed due to a filtering operation of the first low-pass filter712. The first low-pass filter712may include a resistor and a capacitor.

The first Schmitt trigger circuit713may be coupled to the node A at the rear end of the first low-pass filter712. The first Schmitt trigger circuit713transitions its output signal into a logic high level when the voltage at the node A is higher than a first given value, which is equal to a reference value plus an offset value α (i.e., the reference value+the offset value α). The first Schmitt trigger circuit713transitions its output signal into a logic low level when the voltage at the node A is lower than a second given value, which is equal to the reference value minus the offset value α (i.e., the reference value−the offset value α). Herein, the reference value may be a reference value for determining logic levels of signals output from general devices, such as the first inverters711_0to711_2, between a logic high level and a logic low level.

The first low-pass filter712and the first Schmitt trigger circuit713are used to accumulate the influence of the length of a section where the output signal SXOR of the XOR gate714is in a logic high level on the frequency of the first periodic wave LCK. In another embodiment, the first low-pass filter712and the first Schmitt trigger circuit713may be omitted from the first ring oscillator710.

The second ring oscillator720may generate a second periodic wave (or a second periodic signal) HCK having a frequency which is in proportion to a length of the section where the first clock ICK and the second clock QCK are in the same level. In an embodiment, the second periodic wave HCK has a frequency that is proportional to an on-time duration of an output signal SXNOR when the first clock ICK has the same logic value as that of the second clock QCK. The second ring oscillator720may include an odd number 2N−1 of second inverters, for example, three second inverters721_0to721_2(where N is an integer equal to or greater than ‘1’), a second low-pass filter722, and a second Schmitt trigger circuit723, and an XNOR gate724.

The second inverters721_0to721_2may be coupled in a form of a ring to be used for generation of the second periodic wave HCK. An inverter721_2among the second inverters721_0to721_2may be enabled in a section where the output signal SXNOR of the XNOR gate724is in a logic high level. Since the output signal SXNOR of the XNOR gate724is in a logic high level in the section where the first clock ICK and the second clock QCK are in the same level, the length of the section where the first clock ICK and the second clock QCK are in the same level may affect the frequency of the second periodic wave HCK which is generated in the second ring oscillator720. Herein, althoughFIG. 7shows an example where the inverter721_2among the second inverters721_0to721_2is enabled in response to the output signal SXNOR of the XNOR gate724, embodiments of the present disclosure are not limited thereto. In an embodiment, the remaining second inverters721_0and721_1may be enabled in response to the output signal SXNOR of the XNOR gate724. The inverter721_2may have substantially the same configuration as the second inverter221_2shown inFIG. 4.

A first end (e.g., a front end) of the second low-pass filter722may be coupled to an output terminal of the inverter721_2. A node B at a second end (e.g., a rear end) of the second low-pass filter722may be gradually changed due to a filtering operation of the second low-pass filter722. The second low-pass filter722may include a resistor and a capacitor.

The second Schmitt trigger circuit723may be coupled to the node B at the rear end of the second low-pass filter722. The second Schmitt trigger circuit723transitions its output signal into a logic high level when the voltage at the node B is higher than a first given value, which is equal to a reference value plus an offset value α (i.e., the reference value+the offset value α). The second Schmitt trigger circuit723transitions its output signal into a logic low level when the voltage at the node B is lower than a second given value, which is equal to the reference value minus the offset value α (i.e., the reference value−the offset value α). Herein, the reference value may be a reference value for determining logic levels of signals output from general devices, such as the second inverters721_0to721_2, between a logic high level and a logic low level.

When the first low-pass filter712and the first Schmitt trigger circuit713are omitted from the first ring oscillator710, the second low-pass filter722and the second Schmitt trigger circuit723may be omitted from the second ring oscillator720.

The frequency comparator730may compare the frequency of the first periodic wave LCK generated by the first ring oscillator710with the frequency of the second periodic wave HCK generated by the second ring oscillator720and generate a phase difference detection signal UP/DN representing a phase difference between the first clock ICK and the second clock QCK is substantially greater than or smaller than 90°. When the frequency of the first periodic wave LCK is higher than the frequency of the second periodic wave HCK, that is, when a phase difference between the first clock ICK and the second clock QCK is substantially greater than 90°, the frequency comparator730may produce the phase difference detection signal UP/DN of a logic high level. Also, when the frequency of the first periodic wave LCK is lower than the frequency of the second periodic wave HCK, that is, when a phase difference between the first clock ICK and the second clock QCK is substantially smaller than 90°, and the frequency comparator730may produce the phase difference detection signal UP/DN of a logic low level.

The frequency comparator730may include a first frequency detector731, a second frequency detector732, and a code comparator733. The first frequency detector731may detect the frequency of the first periodic wave LCK and generate a first frequency code FREQ_0which represents the detected frequency of the first periodic wave LCK. The second frequency detector732may detect the frequency of the second periodic wave HCK and generate a second frequency code FREQ_1which represents the detected frequency of the second periodic wave HCK. The code comparator733may compare the first frequency code FREQ_0and the second frequency code FREQ_1with each other and generate the phase difference detection signal UP/DN. The phase difference detection signal UP/DN may be transferred to a phase difference correction circuit (not shown) and used to correct the relative phase difference (e.g., a delay value of the second clock QCK with respect to the first clock ICK) of the first clock ICK and the second clock QCK.

FIG. 8is a schematic diagram illustrating a first inverter810and a second inverter820that respectively include a first inverter711_2and a second inverter721_2shown inFIG. 7, in accordance with another embodiment of the present disclosure. Because the first inverter810illustrated inFIG. 8performs the functions of the XOR gate714and the first inverter711_2shown inFIG. 7, the XOR gate714is not separately implemented. Because the second inverter820illustrated inFIG. 8performs the functions of the XNOR gate724and the second inverter721_2shown inFIG. 7, the XNOR gate724is not separately implemented.

Referring toFIG. 8, the first inverter810may include first to third PMOS transistors811and813that are serially coupled between a power source voltage terminal (or a power supply voltage) VDD and an output node OUT1of the first inverter810, and first to third NMOS transistors814to816that are serially coupled between a ground voltage terminal (or a ground) and the output node OUT1of the first inverter810. A first PMOS transistor811may be turned on or off in response to an inverted version QBCK of a second clock QCK. A second PMOS transistor812may be turned on or off in response to the first clock ICK. A third PMOS transistor813may be turned on or off in response to an input signal IN1of the first inverter810. The first NMOS transistor814may be turned on or off in response to an inverted version QBCK of the second clock QCK. The second NMOS transistor815may be turned on or off in response to the first clock ICK. The third NMOS transistor816may be turned on or off in response to the input signal IN1of the first inverter810. For example, when the first clock ICK and the second clock QCK have a logic high level and a logic low level, respectively, the first NMOS transistor814and the second NMOS transistor815may be turned on to enable the pull-down driving of the first inverter810. While the first clock ICK and the second clock QCK have a logic low level and a logic high level, respectively, the first PMOS transistor811and the second PMOS transistor812may be turned on to enable the pull-up driving of the first inverter810. As a result, the first inverter810may be enabled in a section where the first clock ICK and the second clock QCK have different logic levels.

The second inverter820may include fourth to sixth PMOS transistors821and823that are serially coupled between the power source voltage terminal VDD and an output node OUT2of the second inverter820, and fourth to sixth NMOS transistors824to826that are serially coupled between the ground voltage terminal and the output node OUT2of the second inverter820. The fourth PMOS transistor821may be turned on or off in response to the first clock ICK. The fifth PMOS transistor822may be turned on or off in response to the second clock QCK. The sixth PMOS transistor823may be turned on or off in response to an input signal IN2of the second inverter820. The fourth NMOS transistor824may be turned on or off in response to the first clock ICK. The fifth NMOS transistor825may be turned on or off in response to the second clock QCK. The sixth NMOS transistor826may be turned on or off in response to the input signal IN2of the second inverter820. When the first clock ICK and the second clock QCK have the same logic high level of, the fourth NMOS transistor824and the fifth NMOS transistor825may be turned on to enable the pull-down driving of the second inverter820. When the first clock ICK and the second clock QCK have the same logic low level, the fourth PMOS transistor821and the fifth PMOS transistor822may be turned on to enable the pull-up driving of the second inverter820. As a result, the second inverter820may be enabled in a section where the first clock ICK and the second clock QCK have the same logic level.

FIG. 9is a block diagram illustrating a phase difference detector900in accordance with another embodiment of the present disclosure.

Referring toFIG. 9, the phase difference detector900may include a ring oscillator910and a frequency comparator930.

The ring oscillator910may generate a periodic wave (or a periodic signal) LHCK having a frequency which is in proportion to a length of a section where the first clock ICK and the second clock QCK have different logic levels from each other in a first mode, generate a periodic wave LHCK having a frequency which is in proportion to a length of a section where the logic level of the first clock ICK and the logic level of the second clock QCK are the same in a second mode. In other words, the ring oscillator910may operate in the substantially same manner as the first ring oscillator710ofFIG. 7in the first mode and operate in the substantially same manner as the second ring oscillator720ofFIG. 7in the second mode.

The ring oscillator910may include an odd number 2N−1 of inverters, for example, three inverters911_0to911_2(where N is an integer equal to or greater than ‘1’), a low-pass filter912, a Schmitt trigger circuit913, a selector914, an XOR gate915, and an XNOR gate916.

The inverters911_0to911_2may be coupled in a form of a ring to be used for generation of the periodic wave LHCK. An inverter911_2among the inverters911_0to911_2may be enabled in a section where an output signal of the selector914is in a logic high level. The selector914may select and output an output signal SXOR of the XOR gate915into which the first clock ICK and the second clock QCK are inputted when a first mode signal MODE1is enabled, and the selector914may select and output an output signal SXNOR of the XNOR gate916into which the first clock ICK and the second clock QCK are inputted when a second mode signal MODE2is enabled. Therefore, the inverter911_2may be enabled in a section where a logic level of the first clock ICK and a logic level of the second clock QCK are different from each other in the first mode, and the inverter911_2may be enabled in a section where the logic level of the first clock ICK and the logic level of the second clock QCK are the same in the second mode. Herein, althoughFIG. 9shows an example where the inverter911_2among the inverters911_0to911_2is enabled in response to the output signal of the selector914, embodiments of the present disclosure are not limited thereto. In an embodiment, the remaining inverters911_0and911_1may be enabled in response to the output signal of the selector914.

A first end (e.g., a front end of) the low-pass filter912may be coupled to an output terminal of the inverter911_2. A node A at a second end (e.g., a rear end) of the low-pass filter912may be gradually changed due to a filtering operation of the low-pass filter912. The low-pass filter912may include a resistor and a capacitor.

The Schmitt trigger circuit913may be coupled to the node A at the rear end of the low-pass filter912. The Schmitt trigger circuit913transitions its output signal into a logic high level when the voltage at the node A is higher than a first given value, which is equal to a reference value plus α (i.e., the reference value+the offset value α). The Schmitt trigger circuit913transitions its output signal into a logic low level when the voltage at the node A is lower than a second given value, which is equal to the reference value minus the offset value α (the reference value−the offset value α). Herein, the reference value may be a reference value for determining logic levels of signals output from general devices, such as the inverters911_0to911_2, between a logic high level and a logic low level.

The low-pass filter912and the Schmitt trigger circuit913are used to accumulate the influence of the output of the selector914on the frequency of the periodic wave LHCK. The low-pass filter912and the Schmitt trigger circuit913may be omitted from the ring oscillator910.

The frequency comparator930may compare the frequency of the periodic wave LHCK generated in the first mode with the frequency of the periodic wave LHCK generated in the second mode and generate a phase difference detection signal UP/DN representing whether the phase difference between the first clock ICK and the second clock QCK is substantially greater than or smaller than 90°. When the frequency of the periodic wave LHCK generated in the first mode is higher than the frequency of the periodic wave LHCK generated in the second mode, that is, when the phase difference between the first clock ICK and the second clock QCK is substantially greater than 90°, the frequency comparator930may produce the phase difference detection signal UP/DN of a logic high level. Also, when the frequency of the periodic wave LHCK generated in the first mode is lower than the frequency of the periodic wave LHCK generated in the second mode, that is, when the phase difference between the first clock ICK and the second clock QCK is substantially smaller than 90°, the frequency comparator930may produce the phase difference detection signal UP/DN of a logic low level.

The frequency comparator930may include a first frequency detector931, a second frequency detector932, and a code comparator933. The first frequency detector931may detect the frequency of the periodic wave LHCK in the first mode where the first mode signal MODE1is enabled and generate the first frequency code FREQ_0. The second frequency detector932may detect the frequency of the periodic wave LHCK in the second mode where the second mode signal MODE2is enabled and generate the second frequency code FREQ_1. The code comparator933may compare the first frequency code FREQ_0and the second frequency code FREQ_1with each other and generate the phase difference detection signal UP/DN. The phase difference detection signal UP/DN may be transferred to a phase difference correction circuit (not shown) and used to correct the relative phase difference (e.g., a delay value of the second clock QCK with respect to the first clock ICK) of the first clock ICK and the second clock QCK.

According to the embodiments of the present disclosure, it is possible to accurately detect a duty cycle ratio of a clock and accurately detect a phase difference between clocks.