Thin film transistor array panel and manufacturing method thereof

A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel and a manufacturing method thereof.

(b) Description of the Related Art

Liquid crystal displays (LCDs) are one of the most widely used flat panel displays. An LCD includes two panels provided with field-generating electrodes and a liquid crystal (LC) layer interposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer, which determines orientations of LC molecules in the LC layer to adjust polarization of incident light.

Among LCDs including field-generating electrodes on respective panels, a kind of LCDs provides a plurality of pixel electrodes arranged in a matrix at one panel and a common electrode covering an entire surface of the other panel. The image display of the LCD is accomplished by applying individual voltages to the respective pixel electrodes. For the application of the individual voltages, a plurality of three-terminal thin film transistors (TFTs) are connected to the respective pixel electrodes, and a plurality of gate lines transmitting signals for controlling the TFTs and a plurality of data lines transmitting voltages to be applied to the pixel electrodes are provided on the panel.

The panel for an LCD has a layered structure including several conductive layers and several insulating layers. The gate lines, the data lines, and the pixel electrodes are made from different conductive layers (referred to as “gate conductor,” “data conductor,” and “pixel conductor” hereinafter) preferably deposited in sequence and separated by insulating layers. A TFT includes three electrodes: a gate electrode made from the gate conductor and source and drain electrodes made from the data conductor. The source electrode and the drain electrode are connected by a semiconductor usually located thereunder, and the drain electrode is connected to the pixel electrode through a hole in an insulating layer.

In order to increase the aperture ratio, the pixel electrodes overlap adjacent signal lines such as the gate lines and the data lines and the parasitic capacitance between the pixel electrodes and the signal lines can be reduced by interposing a low dielectric organic insulator therebetween. The organic insulator is usually used along an inorganic insulator provided thereunder and the insulators have contact holes for connection between the drain electrodes and the pixel electrodes. The contact holes may have undercuts that the lower inorganic insulator is over-etched to the edges of the lower insulator is disposed under the upper insulator.

In the meantime, storage electrode lines are provided on the TFT array panel for forming storage capacitors along with the pixel electrodes. Although the storage capacitor can be increased by increasing overlapping area of the pixel electrodes and the storage electrode lines, it may decrease the aperture ratio.

SUMMARY OF THE INVENTION

A thin film transistor array panel is provided, which includes: a gate line formed on a substrate; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed at least on the semiconductor layer; a drain electrode formed at least on the semiconductor layer and spaced apart from the data line; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

The second contact hole may have an inclined sidewall to have top edges wider than the bottom edges and the second passivation layer may include organic material.

The drain electrode may include an expansion and a connection connected to the expansion, and the second bottom edge of the second contact hole is disposed opposite the connection.

The thin film transistor array panel may further include a storage electrode line overlapping the drain electrode. The storage electrode line may include an expansion overlapping the expansion of the drain electrode. The storage electrode line extends in a direction crossing the first bottom edge of the second contact hole.

The second contact hole may further have a third bottom edge placed inside the first contact hole. The second and the third bottom edges are located adjacent to each other or opposite each other. The second contact hole may further have a fourth bottom edge placed inside the first contact hole.

The second contact hole may have a rounded or chamfered corner.

The semiconductor layer may have substantially the same planar shape as the data line and the drain electrode except for a portion disposed between the data line and the drain electrode.

The thin film transistor array panel may further include a color filter disposed between the first passivation layer and the second passivation layer.

The color filter may have no portion of the second contact hole.

A thin film transistor array panel is provided, which includes: a gate line formed on a substrate; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed at least on the semiconductor layer; a drain electrode formed at least on the semiconductor layer and spaced apart from the data line; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first sidewall having a first slope and a second sidewall having a second slope slop steeper than the first slope; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

The second passivation layer may include organic material.

The drain electrode may include an expansion and a connection connected to the expansion, and the second sidewall of the second contact hole is disposed opposite the connection.

The first passivation layer may be undercut at the second sidewall of the second contact hole.

A thin film transistor array panel is provided, which includes: a gate line formed on a substrate; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed at least on the semiconductor layer; a drain electrode formed at least on the semiconductor layer and spaced apart from the data line; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first sidewall having a stepped profile and a second sidewall having an undercut; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line, a data line, and a thin film transistor on a substrate; depositing first and second passivation layers in sequence; patterning the second passivation layer using a photo mask having a light transmitting area, a light blocking area, and a slit area disposed partly surrounding the light transmitting area; patterning the first passivation layer; and forming a pixel electrode on the passivation layer.

The slit area may include first and second slits extending parallel to each other and the first slit is longer and closer to the light transmitting area than the second slit.

The thin film transistor may include a gate electrode connected to the gate lines, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode, and the light transmitting area corresponds to a portion of the drain electrode.

The method may further include: forming a storage electrode line on the substrate, the storage electrode line overlapping the drain electrode.

A thin film transistor array panel is provided, which includes: a gate line formed on a substrate; a storage electrode formed on the substrate; a gate insulating layer including a first portion disposed on the gate line and a second portion formed on the storage electrode and having a thickness smaller than the first portion; a semiconductor layer formed on the gate insulating layer; a data line formed at least on the semiconductor layer; a drain electrode formed at least on the semiconductor layer and spaced apart from the data line; first and second passivation layers sequentially formed on the data line and the drain electrode; and a pixel electrode formed on the second passivation layer, connected to the drain electrode, and overlapping the storage electrode.

The drain electrode may overlap the storage electrode and may include an expansion overlapping the storage electrode.

The first and the second passivation layers may have a contact hole exposing the drain electrode and the pixel electrode may be connected to the drain electrode through the contact hole.

The contact hole may have a stepped sidewall.

The drain electrode may overlap the storage electrode and the contact hole may be disposed on the storage electrode.

The drain electrode may have an opening exposing the second portion of the gate insulating layer and the pixel electrode may contact the second portion of the gate insulating layer through the opening.

The first passivation layer may include inorganic insulator and the second passivation layer may include organic insulator.

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line and a storage electrode on a substrate; depositing a gate insulating layer on the gate line and the storage electrode; depositing a semiconductor layer on the gate insulating layer; patterning the semiconductor layer and the gate insulating layer using a photo mask including a alit area such that the gate insulating layer includes a first portion disposed on the gate line and a second portion disposed on the storage electrode and having a thickness smaller than the first portion; depositing first and second passivation layers in sequence; patterning the second and the first passivation layers to form a contact hole exposing at least a portion of the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the contact hole.

The photo mask may further include a light blocking area and a light transmitting area, and the patterning of the semiconductor layer and the gate insulating layer etches out a first portion of the semiconductor layer corresponding to the slit area and a second portion of the semiconductor layer corresponding to the light transmitting area and partly etches out a portion of the gate insulating layer corresponding to the light transmitting area.

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line and a storage electrode on a substrate; forming a gate insulating layer on the gate line and the storage electrode; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode having an opening exposing a portion of the gate insulating layer; depositing first and second passivation layers in sequence; patterning the second and the first passivation layers to form a first contact hole exposing at least the opening of the drain electrode; reducing a thickness of the exposed portion of the gate insulating layer through the opening; and forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the contact hole.

The patterning of the second and the first passivation layers and the reduction of the thickness may use a photo mask including a first slit area. The photo mask may further include a light blocking area, a light transmitting area, and a second slit area giving a light transmittance smaller than the first slit area. The first slit area may correspond to the opening of the drain electrode and the second slit area may correspond to the first contact hole except for the opening.

The method may further include: forming a second contact hole at the first and the second passivation layers and the gate insulating layer exposing a portion of the gate line, wherein the light transmitting area corresponds to the second contact hole.

DETAILED DESCRIPTION OF EMBODIMENTS

In the drawings, the thickness of layers, films and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

Now, TFT array panels and manufacturing methods thereof according to embodiments of the present invention will be described with reference to the accompanying drawings.

Now, TFT array panels and manufacturing methods thereof according to embodiments of the present invention will be described with reference to the accompanying drawings.

A TFT array panel for an LCD will be described in detail with reference toFIGS. 1 and 2.

FIG. 1is an exemplary layout view of a TFT array panel according to an embodiment of the present invention, andFIG. 2is a sectional view of the TFT array panel shown inFIG. 1taken along the lines II–II′.

A plurality of gate lines121and a plurality of storage electrode lines131are formed on an insulating substrate110. The gate lines121and the storage electrode lines131are separated from each other and extend substantially in a transverse direction.

Each gate line121includes a plurality of portions projecting upward and downward to form a plurality of gate electrodes124and an expanded end portion129having a large area for contact with another layer or an external device.

Each storage electrode line131is supplied with a predetermined voltage such as a common voltage and it includes a plurality of expansions137protruding upward and downward.

The gate lines121and the storage electrode lines131may be made of Al containing metal such as Al and Al alloy, Ag containing metal such as Ag and Ag alloy, Cu containing metal such as Cu and Cu alloy, Mo containing metal such as Mo and Mo alloy, Cr, Ti or Ta. The gate lines121and the storage electrode lines131may have a multilayered structure including two films having different physical characteristics. One of the films is preferably made of low resistivity metal including Al containing metal for reducing signal delay or voltage drop in the gate lines121, while the other film is preferably made of material such as Cr, Mo, Mo alloy such as MoW, Ta and Ti, which has good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). Good examples of combination of the lower film material and the upper film material are a lower Cr film and an upper Al (or Al—Nd) film and a lower Al (or Al—Nd) film and an upper Mo film.

The lateral sides of the gate lines121are inclined relative to a surface of the substrate110, and the inclination angle thereof ranges about 30–80 degrees.

A gate insulating layer140preferably made of silicon nitride (SiNx) is formed on the gate lines121.

A plurality of semiconductor stripes151preferably made of hydrogenated amorphous silicon (abbreviated to “a-Si”) are formed on the gate insulating layer140. Each semiconductor stripe151extends substantially in the longitudinal direction and has a plurality of projections154branched out toward the gate electrodes124and a plurality of expansions152disposed on the storage electrode lines131.

A plurality of ohmic contact stripes and islands161and165preferably made of silicide or n+hydrogenated a-Si heavily doped with n type impurity are formed on the semiconductor stripes151. Each ohmic contact stripe161has a plurality of projections163, and the projections163and the ohmic contact islands165are located in pairs on the projections154of the semiconductor stripes151.

The lateral sides of the semiconductor stripes151and the ohmic contacts161and165are inclined relative to a surface of the substrate110, and the inclination angles thereof are preferably in a range of about 30–80 degrees.

A plurality of data lines171and a plurality of drain electrodes175are formed on the ohmic contacts161and165.

The data lines171for transmitting data voltages extend substantially in the longitudinal direction and intersect the gate lines121. Each data line171includes an expansion179having a larger area for contact with another layer or an external device.

A plurality of branches of each data line171, which project toward the drain electrodes175, form a plurality of source electrodes173. Each drain electrode175includes one linear end portion disposed on a gate electrode124and partially enclosed by a source electrode173and the other expanded end portion177having a large area for contact with another layer and overlapping an expansion137of a storage electrode line131. A gate electrode124, a source electrode173, and a drain electrode175along with a projection154of a semiconductor stripe151form a TFT having a channel formed in the projection154disposed between the source electrode173and the drain electrode175.

The data lines171and the drain electrodes175may be made of refractory metal such as Cr, Mo containing metal, Ti or Ta. However, they may also include a low resistivity film and a good contact film. Like the gate lines121, the data lines171and the drain electrodes175have tapered lateral sides relative to the surface of the substrate110, and the inclination angles thereof range about 30–80 degrees.

The ohmic contacts161and165are interposed only between the underlying semiconductor stripes151and the overlying data lines171and the overlying drain electrodes175thereon and reduce the contact resistance therebetween. Although the semiconductor stripes151are narrower than the data lines171at most places, the width of the semiconductor stripes151becomes large near the storage electrode lines131as described above, to smooth the profile of the surface, thereby preventing the disconnection of the data lines171.

Lower and upper passivation layers180pand180qare sequentially formed on the data lines171, the drain electrodes175, and the exposed portions of the semiconductor stripes151. The first passivation layer180pis relatively thin and preferably made of inorganic insulator such as silicon nitride, while the second passivation layer180qis relatively thick and preferably made of organic insulator. The first and the second passivation layers180pand180qhave a plurality of contact holes182and187exposing the end portions179of the data lines171and the expanded end portions177of the drain electrodes175, respectively. Furthermore, the first and the second passivation layers180pand180qand the gate insulating layer140have a plurality of contact holes181exposing the end portions129of the gate lines121. The contact holes181,182and187may have sidewalls making a smooth angle and in particular, the sidewalls of the contact holes187consisting of the second passivation180qmake an angle of about 30–85 degrees with the surface of the substrate110. The contact holes181,182and187have a planar shape of rectangle, but they may have a shape of polygon or circle. Examples of detailed configurations of the contact holes187will be described later.

A plurality of pixel electrodes190and a plurality of contact assistants81and82, which are preferably made of ITO or IZO, are formed on the passivation layer180.

The pixel electrodes190are physically and electrically connected to the drain electrodes175through the contact holes187such that the pixel electrodes190receive the data voltages from the drain electrodes175.

The pixel electrodes190supplied with the data voltages generate electric fields in cooperation with a common electrode (not shown) on another panel (not shown), which reorient liquid crystal molecules in a liquid crystal layer (not shown) disposed therebetween.

A pixel electrode190and a common electrode form a liquid crystal capacitor, which stores applied voltages after turn-off of the TFT. An additional capacitor called a “storage capacitor,” which is connected in parallel to the liquid crystal capacitor, is provided for enhancing the voltage storing capacity. The storage capacitors are implemented by overlapping the pixel electrodes190with the storage electrode lines131. The capacitances of the storage capacitors, i.e., the storage capacitances are increased by providing the expansions137at the storage electrode lines137for increasing overlapping areas and by extending the drain electrodes175to overlap the expansion137for decreasing the distance between the terminals of the storage capacitors. The storage capacitors may also be implemented by overlapping the pixel electrodes190and the gate lines121adjacent thereto (called “previous gate lines”).

The pixel electrodes190overlap the gate lines121and the data lines171to increase aperture ratio.

The contact assistants81/82are connected to the exposed expansions129/179of the gate lines121/ the data lines171through the contact holes181/182. The contact assistants81and82protect the exposed portions129and179and complement the adhesion between the exposed portions129and179and external devices.

The pixel electrodes190may be made of ITO or transparent conductive polymer. For a reflective LCD, the pixel electrodes190are made of opaque reflective metal. In these cases, the contact assistants81and82may be made of material such as ITO or IZO different from the pixel electrodes190.

An LCD according to an embodiment of the present invention include a TFT array panel shown inFIGS. 1 and 2, a common electrode panel (not shown), and a liquid crystal layer (not shown) interposed between the panels. Each panel may have an alignment layer (not shown) coated thereon.

Now, examples of detailed configurations of the contact holes187shown inFIGS. 1 and 2will be described with reference toFIGS. 3A–3C,4A–4C,5A–5C,6A–6C, and7A–7C.

FIGS. 3A,4A,5A,6A and7A are expanded layout views of the contact holes exposing the expansions of the drain electrodes175shown inFIGS. 1 and 2,FIGS. 3B,4B,5B,6B and7B are sectional views of the contact holes shown inFIGS. 3A,4A,5A,6A and7A taken along the lines IIIB–IIIB′, IVB–IVB′, VB–VB′, VIB–VIB′, and VIIB–VIIB′, andFIGS. 3C,4C,5C,6C and7C are sectional views of the contact holes shown inFIGS. 3A,4A,5A,6A and7A taken along the lines IIIC–IIIC′, IVC–IVC′, VC–VC′, VIC–VIC′, and VIIC–VIIC′.

FIGS. 3A–7Cshow a contact hole187disposed on an expanded end portion177of a drain electrode175and an expansion137of a storage electrode line131and covered by a pixel electrode190. The contact hole187has sidewalls consisting of a lower passivation layer180pand an upper passivation layer180qthat is much thicker than the lower passivation layer180p. Portion of the sidewalls formed by the upper passivation layer180qmake a smooth angle of about 30–85 degrees with a surface of a substrate110and thus the contact hole187has three dominant rectangular boundaries, i.e., a lower layer boundary187pformed by a lower passivation layer180p, a bottom boundary187qformed by a bottom surface of an upper passivation layer180q, and a top boundary187rformed by a top surface of the upper passivation layer188q. The lower layer boundary187phas a pair of transverse edges defined by points C and D and having a width Wpt and a pair of longitudinal edges defined by points N and O and having a width Wpl. The bottom boundary187qhas a pair of transverse edges defined by points B and E and having a width Wqt and a pair of longitudinal edges defined by points M and P and having a width Wql. The top boundary187rhas a pair of transverse edges defined by points A and F and a pair of longitudinal edges defined by points L and Q. The distance between lower edges of the bottom and the top boundaries is denoted by Dd, the distance between upper edges of the bottom and the top boundaries is denoted by Du, the distance between left edges of the bottom and the top boundaries is denoted by Dl, and the distance between right edges of the bottom and the top boundaries is denoted by Dr.

Referring toFIGS. 3A–3C, the lower layer boundary187pis disposed entirely within the bottom boundary187q. Therefore, all portions of the top surface of the lower passivation layer180paround the lower layer boundary187pare exposed, and thus a stepped profile is formed at each edge of the contact hole187, which ensures the reliability of the contact between the pixel electrode and the expansion177. Furthermore, the distances between the adjacent edges of the bottom and the top boundaries187qand187rare substantially equal.FIG. 3Bshows the lower and the upper edges of the top boundary187rare disposed outside the expansion177as well as the expansion137. In this case, an area R of the contact hole187, which is disposed outside of the opaque expansions137and177, may yield light leakage since the inclined sidewall varies a cell gap that is defined as a thickness of a liquid crystal layer (not shown) and refracts an incident light. Moreover, the inclined sidewalls obstructs uniform rubbing of an alignment layer (not shown) coated on the pixel electrode190and this may also cause light leakage. The light leakage is more severe at the upper edge of the contact hole187than at the lower edge since another portion176of the drain electrode175, which is connected to the expansion177, also blocks the light leakage. Since the above-described light leakage uniformly distributes over a TFT array panel, it may make no spot. However, the light leakage may increase the luminance of an LCD in a black state and thus it decreases the contrast ratio of the LCD and increases the variation of the contrast ratio between LCD products. Although the light leakage can be blocked by increasing the expansions137and177, the increase of the expansions137and177decreases the aperture ratio and the luminance.

Referring toFIGS. 4A–7C, at least one of the edges of the lower layer boundary187pis disposed outside of the bottom boundary187qto form undercut, while the other edge(s) of the lower layer boundary187pare disposed within the bottom boundary187qto form stepped profiles of the sidewall(s). Hereinafter, the edge(s) forming the undercut is referred to as “reversely-stepped edge(s)” and the edge(s) forming the stepped profiles is referred to as “stepped edge(s).” Although the undercut at the reversely-stepped edge(s) may disconnect the pixel electrode190, the connection between the pixel electrode190and the expansion177is still ensured by the stepped edge(s). Meanwhile, the distance(s) between the edges of the bottom and the top boundaries187qand187rat the reversely-stepped edge(s) is shorter than the distance(s) at between the edges of the bottom and the top boundaries187qand187rthe stepped edge(s) and the slope of the sidewall of the contact hole187at the reversely-stepped edge(s) is steeper than at the stepped edge(s). Accordingly, the width of the contact hole187in direction(s) perpendicular to the reversely-stepped edge(s) is decreased3C and thus it is easy to place the contact hole187within the expansion177.

In detail,FIGS. 4A–4Cshow that the upper edge of the lower layer boundary187pis disposed outside of the bottom boundary187q, while the other edges of the lower layer boundary187pare disposed within the bottom boundary187q. The distance Du between the upper edges of the bottom and the top boundaries187qand187ris shorter than other distances Dd, Dl and Dr such that the longitudinal width of the contact hole187is decreased compared with the contact hole187shown inFIGS. 3A–3Cto reduce the light leakage.

Referring toFIGS. 5A–5C, the upper and the lower edges of the lower layer boundary187pare disposed outside of the bottom boundary187q, while the left and the right edges of the lower layer boundary187pare disposed within the bottom boundary187q. The distances Du and Dd between the upper and the lower edges of the bottom and the top boundaries187qand187rare shorter than the other distances Dl and Dr and the contact hole187can be disposed within the expansion much safely to reduce the light leakage. In this case, the size of the expansion177can be also reduced to increase the aperture ratio. To obtain a safer connection between the pixel electrode190and the expansion177, the longitudinal width Wql of the contact hole187may be increased with or without decreasing the transverse width Wqt.

Referring toFIGS. 6A–6C, the upper and the left edges of the lower layer boundary187pare disposed outside of the bottom boundary187q, while the lower and the right edges of the lower layer boundary187pare disposed within the bottom boundary187q. The distances Du and Dl between the upper and the left edges of the bottom and the top boundaries187qand187rare shorter than the other distances Dd and Dr to decrease the light leakage.

Referring toFIGS. 7A–7C, the left edge of the lower layer boundary187pis disposed within the bottom boundary187q, while the other edges of the lower layer boundary187pare disposed out of the bottom boundary187q. The distances Du, Dd and Dr between the upper and the lower edges of the bottom and the top boundaries187qand187rare shorter than the other distances Dl and the contact hole187can be disposed within the expansion177.

A method of manufacturing the TFT array panel shown inFIGS. 1 and 2according to an embodiment of the present invention will be now described in detail with reference toFIGS. 8–17as well asFIGS. 1 and 2.

FIGS. 8,10,12and14are layout views of the TFT array panel shown inFIGS. 1 and 2in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention, andFIGS. 9,11,13and15are sectional views of the TFT array panel shown inFIGS. 8,10,12, and14taken along the lines IX–IX′, XI–XI′, XIII–XIII′ and XV–XV′, respectively.

Referring toFIGS. 8 and 9, conductive film(s) preferably made of Cr, Mo, Al, Ag, and alloys thereof is sputtered on an insulating substrate110such as transparent glass. The conductive film is patterned by photo-etching with dry etch or wet etch to form a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137. The edge profiles of the gate lines121and the storage electrode lines131are tapered for good attachment of overlying layers.

Referring toFIGS. 10 and 11, after sequential deposition of a gate insulating layer140preferably made of silicon nitride or silicon oxide, an intrinsic a-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality of extrinsic semiconductor stripes164and a plurality of intrinsic semiconductor stripes151including a plurality of projections154on the gate insulating layer140.

Referring toFIGS. 12 and 13, a conductive layer is sputtered and photo-etched to form a plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175. Thereafter, portions of the extrinsic semiconductor stripes164, which are not covered with the data lines171and the drain electrodes175, are removed by etch to complete a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165and to expose portions of the intrinsic semiconductor stripes151.

Referring toFIGS. 14 and 15, a lower passivation layer180ppreferably made of silicon nitride or silicon oxide and an upper passivation layer180qpreferably made of photosensitive organic insulator are deposited and etched along with the gate insulating layer140to form a plurality of contact holes181,182and187exposing the end portions129of the gate lines121, the end portions179of the data lines171, and the expansions of the drain electrodes175.

In detail, a photo mask50having a plurality of light transmitting areas TA, a plurality of slit areas SA, and a plurality of light blocking areas BA is aligned with the substrate110as shown inFIG. 16, which shows a portion of the photo mask50facing the contact hole187. The photo mask50includes a transparent substrate51and a plurality of opaque members53. In the slit areas SA, the opaque members53have width smaller than a predetermined width and the distance between the opaque members53is smaller than a predetermined distance. In other words, slits52between the opaque members53has a width smaller than the predetermined distance and the distance between the slits52is smaller than the predetermined width. The light transmitting areas TA are defined as the areas that have no opaque member53within the predetermined distance, and the light blocking areas BA are defined as the areas occupied by a light blocking member53over a distance larger than the predetermined width.

The upper passivation layer180qis exposed to light through the photo mask50and developed to have a shape shown inFIG. 16, which shows that a portion of the upper passivation layer180qfacing the light transmitting area TA is removed to exposed the lower passivation layer180pand a portion facing the light blocking area BA is remained, while a portion facing the slit area SA have a reduced thickness.

Thereafter, the upper passivation layer180qis cured and the exposed portion of the lower passivation layer180qis removed by dry etch as shown inFIG. 17. The curing causes reflow of the upper passivation layer180qand the etch of the lower passivation layer180pconsumes the upper passivation layer180qsuch that the contact hole187has a rounded and increased sidewalls. The sidewall(s) facing the slit area SA has a relatively slow slope and a large width, while other sidewall(s) have relatively steep slope and small width. In addition, the steep sidewall(s) make an undercut that a portion of the lower passivation layer180punder the upper passivation layer180qis removed. Although the undercut at the steep sidewall(s) may cause the disconnection of an overlying layer, the slow sidewall(s) ensures the connections between the expansion177of the drain electrode175and the overlying layer.

The contact holes187may have various shapes shown inFIGS. 3A–7Cusing various photo masks shown inFIGS. 18–25.

FIG. 18shows a photo mask50having slits52surrounding all edges of the light transmitting area TA for forming the contact hole187shown inFIGS. 3A–3C.

Photo masks50shown inFIGS. 19 and 20, which have slits52surrounding three edges of the light transmitting area TA, can be used for forming the contact hole187shown inFIGS. 4A–4C, and the photo mask50shown inFIG. 20has a long inner slit and a short outer slit may make the upper corners of the contact holes187chamfered or rounded to further decrease the size of the contact hole187.

Photo masks50shown inFIGS. 21–23have slits52surrounding two three edges of the light transmitting area TA. The slits52of the photo masks50shown inFIGS. 21 and 22are disposed opposite each other with respect to the light transmitting area TA, while those shown inFIG. 23surround adjacent two edges of the light transmitting area TA. The long inner slit and the short outer slit shown inFIG. 22make the corners of the contact hole187rounded or chamfered.

Photo masks50shown inFIGS. 24 and 25have slits52surrounding only one edge of the light transmitting area TA and the long inner slit and the short outer slit shown inFIG. 25make the corners of the contact hole187rounded or chamfered.

The other contact holes181and182may also be formed to have stepped profiles by using the slit areas SA.

Finally, as shown inFIGS. 1 and 2, a plurality of pixel electrodes190and a plurality of contact assistants81and82are formed on the upper passivation layer180qby sputtering and photo-etching an ITO or IZO layer.

An LCD according to another embodiment of the present invention will be described in detail with reference toFIGS. 26 and 27.

FIG. 26is a layout view of a TFT array panel for an LCD according to another embodiment of the present invention, andFIG. 27is a sectional view of an LCD including the TFT array panel shown inFIG. 26taken along the line XXVII–XXVII′.

Referring toFIGS. 26 and 27, a TFT array panel according to this embodiment has a layered structure almost the same as those shown inFIGS. 1 and 2. In detail, a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137are formed on a substrate110, and a gate insulating layer140, a plurality of semiconductor stripes151including a plurality of projections154, and a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165are sequentially formed thereon. A plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175including expansions177are formed on the ohmic contacts161and165, and lower and upper passivation layers180pand180qare formed thereon. A plurality of contact holes182and187are provided at the passivation layers180pand180q, and a plurality of pixel electrodes190and a plurality of contact assistants82are formed on the upper passivation layer180q.

Different from the TFT array panel shown inFIGS. 1 and 2, the semiconductor stripes151have almost the same planar shapes as the data lines171and the drain electrodes175as well as the underlying ohmic contacts161and165. However, the projections154of the semiconductor stripes151include some exposed portions, which are not covered with the data lines171and the drain electrodes175, such as portions located between the source electrodes173and the drain electrodes175.

In addition, there is no contact hole exposing the gate lines121and no contact assistants thereon. The gate lines121may be directly connected to a gate driving circuit integrated on the substrate110along with the signal lines121and171and the electrodes124,173and175. However, there may be provided a plurality of contact holes (not shown) at the passivation layers180pand180q, and a plurality of connection members (not shown) may be provided on the upper passivation layer180qfor connection with other elements of the gate driving circuit.

A manufacturing method of the TFT array panel according to an embodiment simultaneously forms the data lines171, the drain electrodes175, the semiconductors151, and the ohmic contacts161and165using one photolithography process.

A photoresist pattern for the photolithography process has position-dependent thickness, and in particular, it has first and second portions with decreased thickness. The first portions are located on wire areas that will be occupied by the data lines171and the drain electrodes175and the second portions are located on channel areas of TFTs.

The position-dependent thickness of the photoresist is obtained by several techniques, for example, by providing translucent areas on the exposure mask300as well as transparent areas and light blocking opaque areas. The translucent areas may have a slit pattern, a lattice pattern, a thin film(s) with intermediate transmittance or intermediate thickness. When using a slit pattern, it is preferable that the width of the slits or the distance between the slits is smaller than the resolution of a light exposer used for the photolithography. Another example is to use reflowable photoresist. In detail, once a photoresist pattern made of a reflowable material is formed by using a normal exposure mask only with transparent areas and opaque areas, it is subject to reflow process to flow onto areas without the photoresist, thereby forming thin portions.

As a result, the manufacturing process is simplified by omitting a photolithography step.

Many of the above-described features of the TFT array panel for an LCD shown inFIGS. 1 and 2may be appropriate to the TFT array panel shown inFIGS. 26 and 27.

An LCD according to another embodiment of the present invention will be described in detail with reference toFIGS. 28 and 29.

FIG. 28is a layout view of a TFT array panel for an LCD according to another embodiment of the present invention, andFIG. 29is a sectional view of an LCD including the TFT array panel shown inFIG. 28taken along the line XXIX–XXIX′.

Referring toFIGS. 28 and 29, a TFT array panel according to this embodiment has a layered structure almost the same as those shown inFIGS. 1 and 2. In detail, a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137are formed on a substrate110, and a gate insulating layer140, a plurality of semiconductor stripes151including a plurality of projections154, and a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165are sequentially formed thereon. A plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175including expansions177are formed on the ohmic contacts161and165, and lower and upper passivation layers180pand180qare formed thereon. A plurality of contact holes182and187are provided at the passivation layers180pand180q, and a plurality of pixel electrodes190and a plurality of contact assistants82are formed on the upper passivation layer180q.

Different from the TFT array panel shown inFIGS. 1 and 2, a plurality of color filters230preferably representing red (R), green (G), and blue (B) colors are formed between the lower passivation layer180pand the upper passivation layer180q. Each of the color filters230are disposed substantially between adjacent two the data lines171and extends in a longitudinal direction. The color filters230are not disposed on a peripheral area that is provided with the expansions179of the data lines171, and the color filters230are not disposed or have openings at the contact holes187. Edges of adjacent color filter stripes R, G and B are spaced apart from each other, but they may overlap each other.

In addition, there is no contact hole exposing the gate lines121and no contact assistants thereon.

Many of the above-described features of the TFT array panel for an LCD shown inFIGS. 1 and 2may be appropriate to the TFT array panel shown inFIGS. 28 and 29.

An LCD according to another embodiment of the present invention will be described in detail with reference toFIGS. 30 and 31.

FIG. 30is a layout view of a TFT array panel for an LCD according to another embodiment of the present invention, andFIG. 31is a sectional view of an LCD including the TFT array panel shown inFIG. 30taken along the line XXXI–XXXI′.

Referring toFIGS. 30 and 31, a TFT array panel according to this embodiment has a layered structure almost the same as those shown inFIGS. 1 and 2. In detail, a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137are formed on a substrate110, and a gate insulating layer140, a plurality of semiconductor stripes151including a plurality of projections154, and a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165are sequentially formed thereon. A plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175including expansions177are formed on the ohmic contacts161and165, and lower and upper passivation layers180pand180qare formed thereon. A plurality of contact holes181p,181q,182p,182q,187pand187qare provided at the passivation layers180pand180qand the gate insulating layer140, and a plurality of pixel electrodes190and a plurality of contact assistants81and82are formed on the upper passivation layer180q.

It is noted that the contact holes at the lower passivation layer180pand the upper passivation layer180qare differently illustrated and indicated by different reference numerals in the figures for showing the stepped profiles of the contact holes.

Different from the TFT array panel shown inFIGS. 1 and 2, portions of the gate insulating layer140disposed between the expansions137of the storage electrode lines131and the expansions177of the drain electrodes175have thickness smaller than other portions of the gate insulating layer140as shown inFIG. 31. Accordingly, the distance between the expansions137and177is decreased such that the storage capacitance therebetween is increased without scarifying the aperture ratio. In addition, the aperture ratio can be increased by further thinning the gate insulating layer140and by decreasing the sizes of the expansions137and177.

Many of the above-described features of the TFT array panel for an LCD shown inFIGS. 1 and 2may be appropriate to the TFT array panel shown inFIGS. 30 and 31.

A method of manufacturing the TFT array panel shown inFIGS. 30 and 31according to an embodiment of the present invention will be now described in detail with reference toFIGS. 32–39as well asFIGS. 30 and 31.

FIGS. 32,34,36and38are layout views of the TFT array panel shown inFIGS. 30 and 31in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention, andFIGS. 33,35,37and39are sectional views of the TFT array panel shown inFIGS. 32,34,36and38taken along the lines XXXIII–XXXIII′, XXXV–XXXV′, XXXVII–XXXVII′, and XXXIX–XXXIX′, respectively.

Referring toFIGS. 32 and 33, conductive film(s) preferably made of Cr, Mo, Al, Ag, and alloys thereof is sputtered on an insulating substrate110such as transparent glass. The conductive film is patterned by photo-etching with dry etch or wet etch to form a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137. The edge profiles of the gate lines121and the storage electrode lines131are tapered for good attachment of overlying layers.

Referring toFIGS. 34 and 35, after sequential deposition of a gate insulating layer140preferably made of silicon nitride or silicon oxide, an intrinsic a-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality of extrinsic semiconductor stripes164and a plurality of intrinsic semiconductor stripes151including a plurality of projections154on the gate insulating layer140.

In detail, the gate insulating layer140, the intrinsic a-Si layer, and the extrinsic a-Si layer are deposited and a photoresist (not shown) is coated on the extrinsic a-Si layer. A photo mask60having a plurality of light transmitting areas TA, a plurality of slit areas SA, and a plurality of light blocking areas BA is aligned with the substrate110as shown inFIG. 35. The photo mask60includes a transparent substrate61and a plurality of opaque members63, and the slit area SA has a plurality of slits62. The light transmitting areas TA face the expansions137of the storage electrode lines131, the light blocking areas BA face the semiconductor stripes151and164, and the slit areas SA face the remaining areas of the TFT array panel. The photoresist is exposed to light thorough the photo mask60and developed to have a position dependent thickness. In particular, portions of the photoresist facing the slit areas SA have a thickness smaller than portions facing the light blocking areas BA. Appropriate etches can make the portions of the gate insulating layer on the expansions137to have a thickness smaller than other portions.

Referring toFIGS. 36 and 37, a conductive layer is sputtered and photo-etched to form a plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175. Thereafter, portions of the extrinsic semiconductor stripes164, which are not covered with the data lines171and the drain electrodes175, are removed by etch to complete a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165and to expose portions of the intrinsic semiconductor stripes151.

Referring toFIGS. 38 and 39, a lower passivation layer180ppreferably made of silicon nitride or silicon oxide and an upper passivation layer180qpreferably made of photosensitive organic insulator are deposited and etched along with the gate insulating layer140to form a plurality of contact holes181p,181q,182p,182q,187pand187qexposing the end portions129of the gate lines121, the end portions179of the data lines171, and the expansions of the drain electrodes175. The stepped profiles of the contact holes can be made by the steps described above with reference toFIGS. 16 and 17.

Finally, as shown inFIGS. 30 and 31, a plurality of pixel electrodes190and a plurality of contact assistants81and82are formed on the upper passivation layer180qby sputtering and photo-etching an ITO or IZO layer.

An LCD according to another embodiment of the present invention will be described in detail with reference toFIGS. 40 and 41.

FIG. 40is a layout view of a TFT array panel for an LCD according to another embodiment of the present invention, andFIG. 41is a sectional view of an LCD including the TFT array panel shown inFIG. 40taken along the line XLI–XLI′.

Referring toFIGS. 40 and 41, a TFT array panel according to this embodiment has a layered structure almost the same as those shown inFIGS. 30 and 31. In detail, a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137are formed on a substrate110, and a gate insulating layer140, a plurality of semiconductor stripes151including a plurality of projections154, and a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165are sequentially formed thereon. A plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175including expansions177are formed on the ohmic contacts161and165, and lower and upper passivation layers180pand180qare formed thereon. A plurality of contact holes181p,181q,182p,182q,187pand187qare provided at the passivation layers180pand180qand the gate insulating layer140, and a plurality of pixel electrodes190and a plurality of contact assistants81and82are formed on the upper passivation layer180q.

Different from the TFT array panel shown inFIGS. 30 and 31, the expansions177of the drain electrodes175have openings178have openings178exposing portions of the gate insulating layer140, and the exposed portions of the gate insulating layer140have thickness smaller than other portions of the gate insulating layer140as shown inFIG. 41. Accordingly, the distance between the expansions137and the pixel electrodes190is decreased such that the storage capacitance therebetween is increased without scarifying the aperture ratio. In addition, the aperture ratio can be increased by further thinning the gate insulating layer140and by decreasing the sizes of the expansions137and177.

Many of the above-described features of the TFT array panel for an LCD shown inFIGS. 1 and 2may be appropriate to the TFT array panel shown inFIGS. 40 and 41.

A method of manufacturing the TFT array panel shown inFIGS. 40 and 41according to an embodiment of the present invention will be now described in detail with reference toFIGS. 42–49as well asFIGS. 40 and 41.

FIGS. 42,44,46and48are layout views of the TFT array panel shown inFIGS. 40 and 41in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention, andFIGS. 43,45,47and49are sectional views of the TFT array panel shown inFIGS. 42,44,46and48taken along the lines XLIII–XLIII′, XLV–XLV′, XLVII–XLVII′, and XLIX–XLIX′, respectively.

Referring toFIGS. 42 and 43, conductive film(s) preferably made of Cr, Mo, Al, Ag, and alloys thereof is sputtered on an insulating substrate110such as transparent glass. The conductive film is patterned by photo-etching with dry etch or wet etch to form a plurality of gate lines121including a plurality of gate electrodes124and a plurality of storage electrode lines131including a plurality of expansions137. The edge profiles of the gate lines121and the storage electrode lines131are tapered for good attachment of overlying layers.

Referring toFIGS. 44 and 45, after sequential deposition of a gate insulating layer140preferably made of silicon nitride or silicon oxide, an intrinsic a-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality of extrinsic semiconductor stripes164and a plurality of intrinsic semiconductor stripes151including a plurality of projections154on the gate insulating layer140.

Referring toFIGS. 46 and 47, a conductive layer is sputtered and photo-etched to form a plurality of data lines171including a plurality of source electrodes173and a plurality of drain electrodes175including expansions177. The expansions177have openings178to expose the gate insulating layer. Thereafter, portions of the extrinsic semiconductor stripes164, which are not covered with the data lines171and the drain electrodes175, are removed by etch to complete a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165and to expose portions of the intrinsic semiconductor stripes151.

Referring toFIGS. 48 and 49, a lower passivation layer180ppreferably made of silicon nitride or silicon oxide and an upper passivation layer180qpreferably made of photosensitive organic insulator are deposited and etched along with the gate insulating layer140to form a plurality of contact holes181p,181q,182p,182q,187pand187qexposing the end portions129of the gate lines121, the end portions179of the data lines171, and the expansions of the drain electrodes175.

In detail, the passivation layers180pand180qare deposited and a photoresist (not shown) is coated on the upper passivation layer180q. A photo mask70having a plurality of light transmitting areas TA, a plurality of first and second slit areas S1and S2, and a plurality of light blocking areas BA is aligned with the substrate110as shown inFIG. 49. The photo mask70includes a transparent substrate71and a plurality of opaque members73, and the first and the second slit areas S1and S2have a plurality of slits72. The first and the second slit areas S1and S2have different slit arrangements to give different light transmittances. For example, the distance between the slits72in the second slit area S2is shorter than that in the first slit area S1, or the slits72in the second slit area S2is wider than those in the first slit area S1such that the second slit areas S2give high light transmittance. The light transmitting areas TA face the contact holes181pand181q, the second slit areas S2face the contact holes187p, and the first slit areas S1surrounds the light transmitting areas and the second slit areas S2, and the light blocking areas BA face the remaining areas of the TFT array panel. The photoresist is exposed to light thorough the photo mask60and developed to have a position-dependent thickness. That is, the portions of the photoresist facing the second slit areas S2, those facing the first slit areas S1, and those facing the light blocking areas BA have increasing thickness. Appropriate etches can make the exposed portions of the gate insulating layer140through the openings178to have a thickness smaller than other portions.

Finally, as shown inFIGS. 40 and 41, a plurality of pixel electrodes190and a plurality of contact assistants81and82are formed on the upper passivation layer180qby sputtering and photo-etching an ITO or IZO layer.

The contact structures shown inFIGS. 30–49can also be applied to the TFT array panels shown inFIGS. 26–29.