Semiconductor device and fabrication method thereof

A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the SOI wafer. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates generally to the field of semiconductor technology. More particularly, the present disclosure relates to a semiconductor memory device and a method for fabricating the same.

2. Description of the Prior Art

Dynamic random access memories (DRAMs), which are employed in devices such as power processors and application specific integrated circuits (ASICs), are known in the art.

A DRAM device typically comprises a trench capacitor, which is a three dimensional device formed by etching a trench into a semiconductor substrate. A capacitor dielectric layer is formed on the inner walls of the trench. The trench is then filled with an electrically conductive material such as heavily-doped polysilicon, which can function as one electrode of the trench capacitor while an N-type doped region surrounding the lower portion of the trench functions as the second electrode thereof. A transistor can be formed above and in electrical communication with the trench capacitor.

However, there is a drawback when the transistor is electrically coupled to the trench capacitor via the doped polysilicon as an embedded contact. The embedded polysilicon contacts increase charge and discharge time of the DRAM capacitors. To meet the retention time requirement, a large capacitor that occupies a large valuable chip area is needed to compensate the increased charge and discharge time caused by the employment of the embedded polysilicon contacts.

SUMMARY OF THE INVENTION

It is one object to provide an improved semiconductor device that is capable of reducing charge and discharge time of the capacitors.

One aspect of the present disclosure provides a semiconductor device including a substrate comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the substrate. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the trench capacitor. The embedded contact comprises a metallic layer wrapped around by a silicide layer. A portion of the silicide layer is interposed between the metallic layer and the inner electrode.

According to some embodiments, the node dielectric layer lines a sidewall of the trench.

According to some embodiments, the trench capacitor comprises a node dielectric layer lining a sidewall of the trench.

According to some embodiments, the inner electrode is surrounded by the node dielectric layer.

According to some embodiments, the inner electrode comprises a doped polysilicon layer and a TiN layer between the node dielectric layer and the doped polysilicon layer.

According to some embodiments, the embedded contact is buried in the silicon device layer and the buried oxide layer.

According to some embodiments, the metallic layer comprises W, Ti, TiN, Ta, TaN, Cu, Au, Ni, or any combinations thereof. According to some embodiments, the silicide layer comprises tungsten silicide, cobalt silicide, nickel silicide, or titanium silicide.

According to some embodiments, the transistor is on or in the silicon device layer.

According to another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A substrate comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer is provided. At least a capacitor is formed within a trench of the substrate. An inner electrode and the node dielectric layer of the capacitor penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is formed on the buried oxide layer. The select transistor comprises a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded-contact is formed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.

According to some embodiments, the node dielectric layer lines a sidewall of the trench.

According to some embodiments, the step of forming a capacitor in a trench of the substrate comprises: forming the inner electrode in the trench and recessing the inner electrode, wherein the inner electrode is surrounded by the node dielectric layer.

According to some embodiments, the inner electrode comprises a doped polysilicon layer and a TiN layer between the node dielectric layer and the doped polysilicon layer.

According to some embodiments, the doped polysilicon layer has a top surface that is approximately coplanar with an upper surface of the doped silicon substrate.

According to some embodiments, the embedded contact is buried in the silicon device layer and the buried oxide layer.

According to some embodiments, the embedded contact comprises a metallic layer wrapped around by a silicide layer. A portion of the silicide layer is interposed between the metallic layer and the inner electrode. According to some embodiments, the metallic layer comprises W, Ti, TiN, Ta, TaN, Cu, Au, Ni, or any combinations thereof. According to some embodiments, the silicide layer comprises tungsten silicide, cobalt silicide, nickel silicide, or titanium silicide.

It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.

The present disclosure pertains to a semiconductor device such as a semiconductor memory device having a capacitor, which is particularly suited for DRAM or embedded DRAM (eDRAM) applications. The semiconductor device includes a substrate comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the substrate. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the trench capacitor. The embedded contact comprises a metallic layer wrapped around by a silicide layer. A portion of the silicide layer is interposed between the metallic layer and the inner electrode.

FIG. 1toFIG. 10are schematic, cross-sectional diagrams showing a method for fabricating a semiconductor device1according to one embodiment of the present disclosure. For the sake simplicity only a germane portion of the semiconductor device is illustrated throughFIG. 1toFIG. 10. It is to be understood that the semiconductor device may comprise a memory array and a peripheral circuit (or a support circuit).

As shown inFIG. 1, a substrate10is provided. According to one embodiment, for example, the substrate10may comprise a silicon-on-insulator (SOI) structure comprising a doped silicon substrate100, a buried oxide layer102, and a silicon device layer104. According to one embodiment, for example, the SOI structure may be a SIMOX wafer or a bonded wafer, which are both commercially available. According to one embodiment, for example, the doped silicon substrate100may be an N-type heavily doped silicon substrate100, and the silicon device layer104may be a P-type silicon layer. According to one embodiment, for example, the silicon device layer104may have a thickness of about 50-500 nm, the buried oxide layer102may have a thickness of about 100-500 nm, and the doped silicon substrate100may be 50-500 micrometers, but not limited thereto.

According to one embodiment, a pad oxide layer106may be deposited on a top surface10aof the substrate10. For example, the pad oxide layer106may be deposited by chemical vapor deposition (CVD) methods known in the art. After depositing the pad oxide layer106, a nitride layer108is deposited on the pad oxide layer106. For example, the nitride layer108may be a silicon nitride layer and may have a thickness of about 100-300 nm. The nitride layer108may be deposited by CVD methods. According to one embodiment, after depositing the nitride layer108, an oxide hard mask110having a thickness of about 0.6-1.0 micrometers is deposited on the nitride layer108.

As shown inFIG. 2, an anisotropic dry etching process such as a reactive ion etching (ME) process may be performed to form a trench120extending through the oxide hard mask110, the nitride layer108, the pad oxide layer106, the silicon device layer104, the buried oxide layer102, and into the doped silicon substrate100. A node dielectric layer122is conformally deposited on the interior surface of the trench120and on the top surface of the oxide hard mask110. The node dielectric layer122may comprise, for example, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, barium strontium oxide, or any combinations thereof. Preferably, the node dielectric layer122may comprise a high-k (i.e., k>4.0) dielectric material, such as HfO2or HfSiOx. The node dielectric layer122may be deposited by any suitable deposition methods such as atomic layer deposition (ALD), CVD or physical vapor deposition (PVD) methods. According to one embodiment, the node dielectric layer122may have a thickness of about 10-100 angstroms, but not limited thereto.

According to one embodiment, after the deposition of the node dielectric layer122, a capacitor electrode layer (inner electrode)124is deposited into the trench120. According to one embodiment, for example, the capacitor electrode layer124may comprise a titanium nitride (TiN) layer124alining the sidewall of the trench120on the node dielectric layer122, and a doped polysilicon (poly-1) layer124bthat completely fills up the remaining space within the trench120. According to one embodiment, the TiN layer124amay reduce the series resistance of the trench capacitor. In some embodiments, the TiN layer124amay be omitted. According to one embodiment, the doped polysilicon layer124bmay be an N-type doped polysilicon.

As shown inFIG. 3, after the deposition of the capacitor electrode layer124, a planarization process may be performed to render the upper surface of the capacitor electrode layer124including the TiN layer124aand the doped polysilicon layer124bwithin the trench120and the upper surface of the node dielectric layer122coplanar with the top surface108aof the nitride layer108. According to one embodiment, for example, the planarization process may be a chemical mechanical polishing (CMP) process that is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface. At this point, the capacitor electrode layer124and the node dielectric layer122outside the trench120are removed. The oxide hard mask110is also removed by CMP process. The nitride layer108may act as a polishing stop layer.

As shown inFIG. 4, an upper portion of the capacitor electrode layer124within the trench120is selectively removed to expose an upper portion of the node capacitor layer122. For example, the top surface of the doped polysilicon layer124bmay be first recessed to a horizontal plane that is somewhere between an upper surface and lower surface of the buried oxide layer102. Subsequently, the exposed TiN layer124athat is not covered by the remaining doped polysilicon layer124bwithin the trench120is selectively removed. The exposed upper portion of the node capacitor layer122is then selectively removed. The selective etching of the doped polysilicon layer124, the TiN layer124a, and the node capacitor layer122is known in the art, and therefore the details of the etchant chemistry is omitted.

After the recess etching of the node capacitor layer122, a thin polysilicon (poly-2) layer is conformally deposited on the nitride layer108and on the interior surface within the trench120. The conformal, thin polysilicon layer (not explicitly shown) covers the top surface108aof the nitride layer108, the sidewalls of the silicon device layer104, the partial sidewalls of the buried oxide layer102, the exposed surface of the TiN layer124a, the exposed surface of the node capacitor layer122, and the top surface of the doped polysilicon layer124b. An anisotropic etching process is then performed to etch the conformal, thin polysilicon layer until the top surface108aof the nitride layer108is revealed, thereby forming a polysilicon spacer130covering sidewalls of the buried oxide layer102. The polysilicon spacer130also covers the node capacitor layer122, the TiN layer124a, and partially covers the doped polysilicon layer124b. According to one embodiment, the polysilicon spacer130may partially cover the sidewalls of the silicon device layer104.

According to another embodiment, the polysilicon spacer130may be formed by the following steps. A sacrificial material, such as photoresist, is deposited to fill the trench120and then O2plasma is used to recess the sacrificial material down to the interface between the silicon device layer104and the buried oxide layer102, or slightly higher. Isotropic poly etch can then be employed to remove the exposed portion of the thin polysilicon (poly-2) layer not covered by the sacrificial material.

As shown inFIG. 5, a self-aligned silicide (salicide) process is performed to transform the exposed sidewall of the silicon device layer104, the polysilicon spacer130, and a portion of the doped polysilicon layer124binto a silicide layer140. According to one embodiment, for example, the silicide layer140may comprise tungsten silicide (WSix), cobalt silicide (CoSix), nickel silicide (NiSix), or titanium silicide (TiSix), but not limited thereto. According to one embodiment, for example, to form the silicide layer140, a thin metal layer (not shown) such as W, Co, Ni, or Ti is deposited on the substrate10. The thin metal layer conformally covers the interior surface of the trench120. The thin metal layer is in direct contact with the exposed sidewall of the silicon device layer104, the polysilicon spacer130, and the doped polysilicon layer124b. Subsequently, an thermal or anneal process such as a rapid thermal annealing (RTA) is performed such that the metal reacts with the exposed sidewall of the silicon device layer104, the polysilicon spacer130, and the doped polysilicon layer124b, thereby forming the silicide layer140. The unreacted metal layer may be removed using methods known in the art. As depicted inFIG. 5, the silicon device layer104is electrically coupled to the doped polysilicon layer124bthrough the silicide layer140.

As shown inFIG. 6, a conductive layer150such as a metal layer is deposited on the substrate10. The remaining space within the trench120is completely filled with the conductive layer150. At this point, the top surface108ais also covered by the conductive layer150. According to one embodiment, for example, the conductive layer (or metallic layer)150may comprise W, Ti, TiN, Ta, TaN, Cu, Au, Ni, or any combinations thereof. According to one embodiment, for example, the silicide layer140comprises WSi, and the conductive layer150comprises W. According to one embodiment, the deposited conductive layer150may be formed by CVD or ALD methods and may have low-resistivity.

As shown inFIG. 7, an etching back process is performed to etch the conductive layer150. After the etching back process is complete, the top surface150aof the remaining conductive layer150is approximately coplanar with the top surface104aof the silicon device layer104. According to one embodiment, the remaining conductive layer150and the silicide layer140together form an embedded contact50within the trench120. According to one embodiment, for example, a gas chemistry of SF6, O2and He may be used to etch the conductive layer150comprising W.

As shown inFIG. 8, after recessing the conductive layer150, the nitride layer108is selectively removed from the top surface of the pad oxide layer106. Subsequently, a patterned hard mask208such as a patterned nitride hard mask is formed on the substrate10. According to one embodiment, for example, the patterned hard mask208is formed by performing a lithographic process and a dry etching process. It is noteworthy that the patterned hard mask208overlaps with the conductive layer150. An etching process such as RIE process is then performed to etch the silicon device layer104, the conductive layer150and the silicide layer140, thereby forming an active area1041and an isolation trench240. The isolation trench240also surrounds the active area1041, which is not shown in the cross section ofFIG. 8.

As shown inFIG. 9, a trench oxide layer242is deposited into the isolation trench240. The trench oxide layer242also covers the patterned hard mask208. According to one embodiment, for example, the trench oxide layer242may comprise silicon oxide, but not limited thereto. The trench oxide layer242may be deposited by using any suitable CVD or ALD methods. After the deposition of the trench oxide layer242, a CM′ process is performed to planarize the trench oxide layer242until the top surface of the patterned hard mask208is revealed. The patterned hard mask208is then selectively removed using methods known in the art, for example, hot phosphoric acid solution.

As shown inFIG. 10, a select transistor300is then formed on the active area1041. According to one embodiment, the select transistor300is in close proximity to the embedded contact50. According to one embodiment, the select transistor300may comprise a source doping region302and a drain doping region303such as N+doping regions in the active area1041. The source doping region302is spaced apart from the drain doping region303. A channel region310may be defined between the source doping region302and the drain doping region303. A gate301is disposed directly above the channel region310. According to one embodiment, a passing gate401may be disposed on the trench oxide layer242. According to one embodiment, a contact etch stop layer (CESL)510may be deposited on the substrate10in a blanket manner.

Structurally speaking, as shown inFIG. 10, the semiconductor device1comprises a capacitor TC that is formed in the substrate10. An inner electrode and a node dielectric layer of the capacitor TC may penetrate through the buried oxide layer102and may extend to a predetermined depth (e.g., several micrometers) into the doped silicon substrate100. The capacitor TC comprises the node dielectric layer122lining the sidewall of the trench120. The node dielectric layer122may extend up to the sidewall of the buried oxide layer102. The upper sidewall of the buried oxide layer102may not be covered by the node dielectric layer122. The capacitor electrode layer (inner electrode)124is surrounded by the node dielectric layer122. The node dielectric layer122electrically isolate the capacitor electrode layer (inner electrode)124from the doped silicon substrate100that acts as the other capacitor electrode or outer electrode of the capacitor TC.

According to one embodiment, the top surface of the doped polysilicon layer124bmay be approximately coplanar with the upper surface of the doped silicon substrate100. According to one embodiment, the TiN layer124amay slightly protrude from the top surface of the doped polysilicon layer124b. The upper end of the node dielectric layer122, the upper end of the TiN layer124a, and the top surface of the doped polysilicon layer124bform a step structure S around the upper portion of the trench120.

On top of the capacitor electrode layer124, the embedded contact50comprising metal and metal silicide such as W and WSixis provided. Through the embedded contact50, the capacitor electrode layer124is electrically coupled to the drain doping region303of the select transistor300. The silicide layer140on the sidewall of the active area1041form low resistance ohmic contact between the drain doping region303and the conductive layer150. The passing gate401may be disposed on the trench oxide layer242. The gate301and the passing gate401may be covered with the CESL510. It is to be understood that the select transistor300may be a planar-type transistor or a fin-type transistor. It is advantageous to use the present disclosure because the embedded metal contact significantly reduce the charge and discharge time of the eDRAM capacitor. On the same retention time standard as the prior art, the size and dimension of the capacitor can be shrunk so as to achieve an eDRAM device with higher density.