Semiconductor storage device and method of manufacturing same

A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of U.S. Provisional Patent Application No. 61/695,778, filed on Aug. 31, 2012, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor storage device and a method of manufacturing the same.

BACKGROUND

Description of the Related Art

Nowadays, electrically rewritable resistance change memories, such as a ReRAM and a PRAM, attract attention as a semiconductor storage device. A memory cell of the resistance change memory is configured to be able to change a resistance value, and data is stored in the resistance change memory by the change of the resistance value. The resistance change memory is provided between a word line and a bit line.

However, sometimes, in a manufacturing process of the above-mentioned ReRAM, a buckling phenomenon occurs in a line-and-space pattern, causing a word line or a bit line to short-circuit.

DETAILED DESCRIPTION

A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The variable resistance layer is provided above the first conductive layer. The electrode layer contacts an upper surface of the variable resistance layer. The first liner layer contacts an upper surface of the electrode layer. The stopper layer contacts an upper surface of the first liner layer. The second conductive layer is provided above the stopper layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature.

Hereinafter, a semiconductor storage device according to the embodiment will be described with reference to the drawings.

First Embodiment

Configuration

A circuit configuration of a semiconductor storage device according to a first embodiment will be described below with reference toFIG. 1. Referring toFIG. 1, the semiconductor storage device of the first embodiment includes a memory cell array10, a word line selector circuit20a, a word line driver circuit20b, a bit line selector circuit30a, and a bit line driver circuit30b.

The memory cell array10includes word lines WL and bit lines BL, which intersect each other, and memory cells MC each disposed in an intersection of the word line WL and the bit line BL. The word lines WL are arrayed in a Y-direction at predetermined intervals, and extend in an X-direction. The bit lines BL are arrayed in the X-direction at predetermined intervals, and extend in the Y-direction. That is, the memory cells MC are arranged in a matrix form on a surface formed in the X-direction and the Y-direction.

The memory cell MC includes a diode DI and a variable resistance element R as illustrated inFIG. 1. An anode of the diode DI is connected to the word line WL, and a cathode is connected to one end of the variable resistance element R. The variable resistance element R is electrically rewritable, and stores data in a nonvolatile manner based on a resistance value. The other end of the variable resistance element R is connected to the bit line BL.

The word line selector circuit20aincludes plural selection transistors Tra as illustrated inFIG. 1. One end of the selection transistor Tra is connected to one end of the word line WL, and the other end of the selection transistor Tra is connected to the word line driver circuit20b. A signal Sa is supplied to a gate of the selection transistor Tra. That is, the word line selector circuit20acontrols the signal Sa, thereby selectively connecting the word line WL to the word line driver circuit20b.

As illustrated inFIG. 1, the word line driver circuit20bapplies a voltage, which is necessary to erase the data from the memory cell MC, write the data in the memory cell MC, and read the data from the memory cell MC, to the word line WL.

As illustrated inFIG. 1, the bit line selector circuit30aincludes plural selection transistors Trb. One end of the selection transistor Trb is connected to one end of the bit line BL, and the other end of the selection transistor Trb is connected to the bit line driver circuit30b. A signal Sb is supplied to the gate of the selection transistor Trb. That is, the bit line selector circuit30acontrols the signal Sb, thereby selectively connecting the bit line BL to the bit line driver circuit30b.

As illustrated inFIG. 1, the bit line driver circuit30bapplies the voltage, which is necessary to erase the data from the memory cell MC, write the data in the memory cell MC, and read the data from the memory cell MC, to the bit line BL. The bit line driver circuit30bexternally outputs the data read from the bit line BL.

Next, a stacked structure of the memory cell array10of the first embodiment will be described below with reference toFIG. 2. Referring toFIG. 2, the memory cell array10is formed above a substrate40. The memory cell array10includes a first conductive layer50, a memory layer60, a second conductive layer70, a memory layer60, and a first conductive layer50from the lower layer toward an upper layer. That is, one second conductive layer70is shared by two memory layers60located above and below the second conductive layer70. The first conductive layer50acts as the word line WL. The memory layer60acts as the memory cell MC. The second conductive layer70acts as the bit line BL.

As illustrated inFIG. 2, the first conductive layers50are formed into a stripe shape extending in the X-direction while arrayed in the Y-direction at predetermined intervals. Desirably the first conductive layer50is made of a material having a heat-resistant property and a low resistance. For example, the first conductive layer50is made of tungsten (W), titanium (Ti), tantalum (Ta), a nitride thereof, or a stacked structure thereof.

As illustrated inFIG. 2, each of the memory layers60is provided between the first conductive layer50and the second conductive layer70, and the memory layers60are arranged in a matrix form in the X-direction and the Y-direction.

As illustrated inFIG. 2, the second conductive layers70are formed into the stripe shape extending in the Y-direction while arrayed in the X-direction at predetermined intervals to come into contact with the upper surfaces of the memory layers60. Desirably the second conductive layer70is made of a material having the heat-resistant property and the low resistance. For example, the second conductive layer70is made of tungsten (W), titanium (Ti), tantalum (Ta), a nitride thereof, or a stacked structure thereof.

Next, the detailed stacked structure of the memory layer60will be described below with reference toFIG. 3.FIG. 3is a sectional view illustrating the memory layer60. Referring toFIG. 3, the memory layer60includes a barrier metal layer61, a diode layer62, a lower electrode layer63, a variable resistance layer64, an upper electrode layer65, a liner layer66, a stopper layer67, and an inter-layer insulator68.

The barrier metal layer61contacts an upper surface of the first conductive layer50. The barrier metal layer61is made of titanium nitride (TiN).

The diode layer62contacts an upper surface of the barrier metal layer61. The diode layer62acts as the diode DI. The diode layer62is made of polysilicon. The diode layer62includes a p-type semiconductor layer62a, an intrinsic semiconductor layer62b, and an n-type semiconductor layer62c. The stacking order of the p-type semiconductor layer62a, the intrinsic semiconductor layer62b, and the n-type semiconductor layer62cis inverted in the upper layer and the lower layer of the second conductive layer70.

The variable resistance layer64contacts an upper surface of the lower electrode layer63. The variable resistance layer64acts as the variable resistance element R. In the variable resistance layer64, the resistance value is changed depending on at least one of an applied voltage, a passed current, and an injected charge. For example, the variable resistance layer64is made of a metal oxide.

The upper electrode layer65contacts an upper surface of the variable resistance layer64. The upper electrode layer65is made of the same material as the lower electrode layer63.

The liner layer66contacts an upper surface of the upper electrode layer65. The liner layer66is configured such that, compared with the stopper layer67, an orientation of a lower layer of the liner layer66has no influence on an orientation of an upper layer of the liner layer66. In other words, the liner layer66is made of a material that has a property for canceling the influence of the orientation of the lower layer of the liner layer66, the property being superior compared with the stopper layer67. For example, the liner layer66is made of amorphous silicon (amorphous-Si), or tungsten silicide (WSi).

The stopper layer67contacts an upper surface of the liner layer66. An etching rate of the stopper layer67by Chemical Mechanical Polishing (CMP) is smaller than an etching rate of the inter-layer insulator68by the CMP. For example, the stopper layer67is made of tungsten (W). Moreover, as mentioned later, the stopper67is formed having a thermal expansion coefficient larger than those of the upper electrode layer65and the liner layer66. Since film formation of the liner layer66is performed under high temperature, an internal stress acts on the liner layer66in a direction of contraction (hereinafter, mentioned as “compressive direction”) at room temperature.

The inter-layer insulator68contacts the first interconnection layer50, a side surface of the memory layer60, and the second conductive layer70. For example, the inter-layer insulator68is made of silicon oxide (SiO2).

Known as a method of manufacturing a memory cell array including a variable resistance element is a method where materials configuring the memory cell array are stacked sequentially on a substrate to form a line-and-space pattern. Each layer of a stacked body formed in the line-and-space shape undergoes film formation under high temperature; also, each layer of the stacked body is configured from a different material, respectively, hence has a different thermal expansion coefficient. Therefore, each layer of the above-described stacked body is acted upon by an internal stress in a direction of contraction or a direction of expansion at room temperature. Below, a state where an internal stress acts in a direction of contraction is called a “tensile” state, and a state where an internal stress acts in a direction of expansion is called a “compressive” state.

Buckling may occur in the stacked body depending on magnitude of internal stress in the above-described stacking body, particularly on magnitude of internal stress in an uppermost layer of the stacked body. That is, when a case where the uppermost layer of the stacked body is in a “compressive” state and other layers are in a “tensile” state at room temperature is supposed, the upper most layer tends to expand relatively at room temperature, whereas the other layers tend to contract relatively. This results in the line-and-space pattern getting twisted. This causes short-circuiting between the stacked bodies configuring the line-and-space pattern, breaks in wiring in the uppermost layer, and so on.

On the other hand, in the case where the uppermost layer of the stacked body is in a “tensile” state at room temperature, the uppermost layer contracts along with contraction of the other layers, hence the above-described buckling does not occur. However, if the thermal expansion coefficient of the uppermost layer becomes too large, there is a risk of breaks in wiring occurring in the uppermost layer formed in lines.

In the present embodiment, the uppermost layer of the above-described stacked body is the stopper layer67. Therefore, in order to prevent buckling of the stacked body, it is only required to configure the stopper layer67to be in a “tensile” state at room temperature. That is, it is only required to make the thermal expansion coefficient of the stopper layer67larger than the thermal expansion coefficient of the upper electrode layer65, and so on. However, if tungsten employed as the stopper67is formed directly on the upper electrode layer65, then effects of orientation of a material configuring the upper electrode layer65, and so on, result in the stopper layer67being in a “compressive” state. Accordingly, in the present embodiment, the liner layer66is formed on the upper electrode65. The liner layer66is configured from a material having a property for canceling an influence of an orientation of the upper electrode65, compared to the stopper layer67. In addition to the stopper layer67is deposited on the liner layer66. This results in orientation of the stopper layer67being adjusted, and moreover the thermal expansion coefficient of the stopper layer67being adjusted.

In addition, studies by the inventors have made clear that the lower a bias value of sputtering during film formation of the liner layer66or stopper layer67, the larger the internal stress in the direction of contraction at room temperature of the liner layer66or the stopper layer67.FIG. 4is a graph illustrating a relationship between internal stress of the stacked body (“Stress” inFIG. 4) and buckling of the stacked body (“Diff. Bow” inFIG. 4), and bias of sputtering.

[Each of Manufacturing Processes]

A method of manufacturing the semiconductor storage device in the first embodiment will be described below with reference toFIGS. 5 to 11. As illustrated inFIG. 5, the first-conductive-layer-forming layer50, the barrier-metal-layer-forming layer61, the diode-layer-forming layer62, the lower-electrode-layer-forming layer63, the variable-resistance-layer-forming layer64, the upper-electrode-layer-forming layer65, the liner-layer-forming layer66, and the stopper-layer-forming layer67are stacked on the substrate40via an insulating layer91.

Specifically, tungsten (W) having a thickness of 50 nm is deposited by a sputtering method to form the first-conductive-layer-forming layer50. The first-conductive-layer-forming layer50may have a stacked structure of tungsten (W) and tungsten nitride (WN). Titanium nitride (TiN) having the thickness of 5 nm is deposited by the sputtering method to form the barrier-metal-layer-forming layer61. Amorphous silicon having the thickness of 85 nm is deposited by an LPCVD method to form the diode-layer-forming layer62. The diode-layer-forming layer62is formed by sequentially stacking a phosphorus-doped p-type semiconductor layer, an intrinsic semiconductor layer in which an impurity is not doped, and a boron-doped n-type semiconductor layer. A natural oxide layer formed on the surface of the diode-layer-forming layer62is removed by a wet treatment. The lower-electrode-layer-forming layer63is formed by depositing titanium nitride (TiN) by the sputtering method. The variable-resistance-layer-forming layer64is formed by the LPCVD method or the sputtering method. The upper-electrode-layer-forming layer65is formed by the sputtering method.

The liner-layer-forming layer66and the stopper-layer-forming layer67are formed by the sputtering method. Now, the orientation of the stopper-layer-forming layer67is adjustable by forming the liner-layer-forming layer66. The orientation of the stopper-layer-forming layer67can be further adjusted by adjusting the bias of sputtering during formation of the liner-layer-forming layer66or the stopper-layer-forming layer67. The bias value of sputtering may be adjusted such that internal stress at room temperature of the stopper-layer-forming layer67acts in the compressive direction. Such a bias value may be appropriately adjusted according to aspect ratio and so on of the stacked body after later-described etching.

As illustrated inFIG. 6, a hard mask92is formed on an upper surface of the stopper-layer-forming layer67. d-TEOS having the thickness of 200 nm is deposited by a CVD method, and patterned by a lithography method, thereby forming the hard mask92. In a memory area AR1where the memory cell array10is formed, the hard masks92are formed into the strip shape extending in the X-direction while arrayed in the Y-direction at predetermined intervals. On the other hand, in a peripheral area AR2located around the memory area AR1, the hard mask92is formed so as to cover the whole of the peripheral area AR2.

As illustrated inFIG. 7, etching is performed to the first-conductive-layer-forming layer50through the hard mask92by an RIE method. Therefore, the first conductive layers50, the barrier-metal-layer-forming layers61, the diode-layer-forming layers62, the lower-electrode-layer-forming layers63, the variable-resistance-layer-forming layers64, the upper-electrode-layer-forming layers65, the liner-layer-forming layers66, and the stopper-layer-forming layers67are formed into the stripe shape extending in the X-direction while arrayed in the Y-direction at predetermined intervals.

As illustrated inFIG. 8, the inter-layer insulator68ais formed so as to cover the hard mask92and the-stopper-layer-forming layers67. Then, the hard mask92and the inter-layer insulator68aare planarized until the upper surface of the stopper-layer-forming layers67are exposed by the CMP.

As illustrated inFIG. 9, the second-conductive-layer-forming layer70, the barrier-metal-layer-forming layer61, the diode-layer-forming layer62, the lower-electrode-layer-forming layer63, the variable-resistance-layer-forming layer64, the upper-electrode-layer-forming layer65, the liner-layer-forming layer66, and the stopper-layer-forming layer67are stacked on the stopper-layer-forming layers67and the inter-layer insulator68aof the uppermost layer. At this point, the diode-layer-forming layer62is formed by sequentially stacking the n-type semiconductor layer, the intrinsic semiconductor layer, and the p-type semiconductor layer.

Note that the stopper-layer-forming layer67of the uppermost layer can also be formed similarly to the stopper-layer-forming layer67of the lowermost layer. In this case, each of the layers can also be formed to be in a more “tensile” state with respect to a lower layer as a layer becomes more upward. Such a method is thought to enable occurrence of buckling of the stacked body to be more reliably reduced.

As illustrated inFIG. 9, a hard mask93is formed on the upper surface of the stopper-layer-forming layer67. d-TEOS having the thickness of 200 nm is deposited by the CVD method, and patterned by the lithography method, thereby forming a hard mask93. In the memory area AR1, the hard masks93are formed into the strip shape extending in the Y-direction while arrayed in the X-direction at predetermined intervals. On the other hand, in the peripheral area AR2, the hard mask93is formed so as to cover the whole of the peripheral area AR2.

As illustrated inFIG. 10, the etching is performed through the hard mask93until the barrier-metal-layer-forming layers61that contact the upper surface of the first conductive layers50are divided. Therefore, the barrier metal layers61, the diode layers62, the lower electrode layers63, the variable resistance layers64, the upper electrode layers65, the liner layers66, and the stopper layers67are formed so as to be arranged in a matrix form in the Y-direction and the X-direction at predetermined intervals in the lower layer of the second conductive layer70. The second conductive layers70are formed into the stripe pattern extending in the Y-direction while arrayed in the X-direction at predetermined intervals. The barrier-metal-layer-forming layers61, the diode-layer-forming layers62, the lower-electrode-layer-forming layers63, the variable-resistance-layer-forming layers64, the upper-electrode-layer-forming layers65, the liner-layer-forming layers66, and the stopper-layer-forming layers67are formed into the stripe pattern extending in the Y-direction while arrayed in the X-direction at predetermined intervals in the upper layer of the second conductive layer70.

As illustrated inFIG. 11, the inter-layer insulator68bis formed so as to cover the hard mask93and the upper surface of the stopper-layer-forming layers67of the uppermost layer. Then, the hard mask93and the inter-layer insulator68bare planarized until the upper surface of the stopper-layer-forming layers67are exposed by the CMP. Then, the same processes inFIGS. 5 to 11are repeatedly performed.

Second Embodiment

Next, a semiconductor storage device according to a second embodiment is described. As illustrated inFIG. 12, the semiconductor storage device according to the second embodiment is formed substantially similarly to the semiconductor storage device according to the first embodiment, but differs in further including a liner layer69between the stopper layer67and the word line WL in a memory cell array10uppermost portion.

When performing etching during formation of the bit lines or word lines in the memory cell array uppermost portion, the uppermost layer of the stacking body becomes the above-described bit lines or word lines. Therefore, configuring the bit lines or word lines in the memory cell array uppermost portion to be in a “tensile” state at room temperature is thought to enable buckling in the memory cell array uppermost portion to be effectively suppressed.

Next, a method of manufacturing the semiconductor storage device according to the second embodiment is described. The method of manufacturing the semiconductor storage device according to the second embodiment is similar to that of the first embodiment to processes illustrated inFIG. 11. As illustrated inFIG. 13, formed on an upper surface of the stacking structure illustrated inFIG. 11are the liner-layer-forming layer69and the first-wiring-layer-forming layer50, and formed on an upper surface of the first-wiring-layer-forming layer50is a hard mask94. The same material can be applied to the liner-layer-forming layer69as to the liner layer66, and the hard mask94can be formed by a similar method to the hard mask92.

The liner-layer-forming layer69and the first-wiring-layer-forming layer50are formed by a sputtering method. Now, the orientation of the first-wiring-layer-forming layer50is adjustable by forming the liner-layer-forming layer69. The orientation of the first-wiring-layer-forming layer50can be further adjusted by adjusting the bias of sputtering during formation of the liner-layer-forming layer69or the first-wiring-layer-forming layer50. The bias value of sputtering may be adjusted such that internal stress at room temperature of the first wiring layer50acts in the compressive direction. Such a bias value may be appropriately adjusted according to aspect ratio and so on of the stacked body after later-described etching.

Next, as illustrated inFIG. 14, etching is performed until the barrier-metal-layer-forming layers61are divided through the hard mask94by an RIE method. As a result, the liner layers69and the first wiring layers50are formed into the stripe shape extending in the X-direction while arrayed in the Y-direction at predetermined intervals. Moreover, the barrier metal layers61, the diode layers62, the lower electrode layers63, the variable resistance layers64, the upper electrode layers65, the liner layers66, and the stopper layers67are formed so as to be arranged in a matrix shape in the Y-direction and the X-direction at predetermined intervals in the lower layer of the first wiring layer50. Then, the inter-layer insulator68bis implanted to form the semiconductor storage device according to the second embodiment.