Timing circuits

A clock circuit is initiated by an external trigger pulse. Timing measurements commence at a first rate, and after a first delay (t.sub.1) which is sufficient to allow an oscillator of the clock circuit to stabilize. After a second delay (t.sub.1) the clock circuit operates at a second rate which is half the first rate. The clock circuit then represents the time from reception of the external trigger pulse. The first and second delays are derived by charging a capacitor at a constant rate and comparing the voltage level developed across it with respective reference voltages (V.sub.1, V.sub.2) in comparators. In general, the second rate may be 1/r+1 times the first rate, where r is the ratio of the first delay to the second delay.

This invention relates to a timing circuit. 
In some timing applications it may be necessary to commence timing 
measurements when an external pulse is received by a clock circuit; 
however, this can prove difficult if the external pulse is used also to 
initiate supply of power to the clock circuit. This may occur, for 
example, in the case of a clock circuit including an oscillator which 
usually requires an initial period of stabilisation before reliable clock 
pulses can be derived. 
It is an object of this invention to provide a timing circuit whereby the 
above-described problem is substantially alleviated. 
Accordingly there is provided a timing circuit comprising a clock circuit 
and a control circuit, the control circuit being arranged to receive an 
external pulse and to generate in response thereto, and after a first 
delay, a first control pulse suitable for causing the clock circuit to 
commence operation at a first rate and being arranged to generate, after a 
further delay, a second control pulse suitable for causing the clock 
circuit to operate at a second rate 1/(r+1) times the first rate, where r 
is the ratio of the first delay to the further delay, whereby after said 
further delay the clock circuit provides a representation of elapsed time 
from occurrence of the external pulse. The ratio r may be in the range 0.1 
to 2.0 and values of 1, 3, 7 and 15 may be especially useful. 
In a preferred embodiment the control circuit comprises a voltage source 
for generating in response to said external pulse a voltage which 
increases linearly with time, and respective comparison means for 
generating said first and second control pulses when the voltage generated 
by the voltage source attains first and second reference levels. 
Conveniently, said voltage source may comprise a constant current source 
arranged to charge a capacitor in response to said external pulse and 
means for amplifying a voltage developed across the capacitor. One input 
of each said comparison means may be connected electrically to said 
voltage source and the other input is connected electrically to a 
respective reference voltage.

FIG. 1a shows a control circuit which can be used in conjunction with a 
clock circuit, shown schematically (by way of example only) in FIG. 1b. 
The clock circuit has an oscillator 10 the output of which is connected to 
a pulse forming circuit 11. As described hereinbefore, the oscillator may 
require a significant time interval after power has been applied to reach 
a stable condition suitable for generating reliable clock pulses. If 
switch S1 in FIG. 1b is closed (and S2 is open) pulses formed at 11 are 
counted directly at 12; however, if switch S2 is closed (and S1 is open) 
the pulses pass first through a divide-by-two circuit 13 thus halving the 
count rate. 
The control circuit of FIG. 1a is arranged to generate control pulses which 
actuate switches S1 and S2 at appropriate times to control the operating 
rate of the clock circuit and, as will be described in greater detail, it 
is possible to derive reliable timing measurements, representing elapsed 
time from occurrence of an external pulse, even though operation of the 
clock circuit itself commences some time later, after a delay sufficient 
to allow the oscillator to stabilise. 
Referring to FIG. 1a an external pulse EXT received by the control circuit 
charges a capacitor 20 connected across a constant current source 21. The 
external pulse is received at a time t.sub.R in FIG. 2. The constant 
current source then charges a second capacitor 22 at a constant rate so 
that the voltage developed across it increases linearly with time. This 
voltage is applied to respective input terminals I.sub.1, I.sub.2 of a 
pair of comparators 23, 24. The other input terminals I.sub.1 ' I.sub.2 ' 
of the comparators are connected to respective reference voltages V.sub.1, 
V.sub.2 with which the amplified voltage is compared. Voltage level 
V.sub.1 is set at a value developed across capacitor 22 after a first 
delay t.sub.1 (i.e. at time t.sub.R +t.sub.1) sufficient to allow the 
oscillator in the clock circuit to stabilised. Comparator 23 then 
generates a control pulse P.sub.1 which is used to close switch S1 and 
open switch S2 in the clock circuit which then operates at the relatively 
fast rate. Voltage level V.sub.2, on the other hand, is set at a value 
developed across capacitor 22 after a further delay t.sub.1 (i.e. at time 
t.sub.R +2t.sub.1) and comparator 24 then generates a second control pulse 
P.sub.2 which opens switch S1 and closes switch S2 in the clock circuit 
which then operates at the slower rate. 
The broken line in FIG. 2 represents the clock count which would have been 
attained if the clock circuit had started operating at time t.sub.R at the 
slow rate. In practice, operation was delayed by a time period t.sub.1 to 
allow the oscillator to stabilise; however, by operating the clock circuit 
at twice the slow rate for a further time period t.sub.1 the count 
deficiency is compensated fully and thereafter the count represents 
accurately the elapsed time from occurrence at time t.sub.R of the 
external pulse in units of time corresponding to a clock operating at the 
relatively slow rate. 
In the above dascribed example the time delays t.sub.1 were of equal 
duration but this need not necessarily be the case. 
In general, if the ratio of the first time delay to the further time delay 
is r the clock circuit would need to operate at a slow rate 1/(r+1) times 
the fast rate, and preferably r may be from 0.1 to 2.0. Values of 1, 3, 7 
and 15 may be especially useful.