Automatic bias adjustment circuit for a successive ranged analog/digital converter

An automatic bias adjustment circuit for a successive ranged analog/digital converter (SRADC) that eliminates the need for manual bias adjustments and calibration inputs. The bias correction circuit comprehends dual flip flops that are triggered by selected comparators of the SRADC n bit parallel analog/digital converter. The flip flop output signals control up/down counters whose output bits drive digital/analog converter. The digital/analog converted signals are introduced back into the SRADC analog chain to zero bias errors in a particular sub-range. A disabling circuit prevents operation of the bias adjustment circuits for the first sub-range.

BACKGROUND OF THE INVENTION 
This invention relates to successive ranged analog/digital converter and in 
particular to circuits for automatically adjusting for bias errors that 
are introduced into the analog chain of such devices by the use of high 
speed amplifiers, hot carrier diode switches and the like. 
In a successively ranged analog/digital converter several bits are 
converted at a time in order to increase the speed over that of a 
successive approximation analog/digital converter which converts one bit 
at a time. In the SRADC type of device analog input signals are processed 
through an analog chain and fed to an n bit parallel analog/digital 
converter. The analog chain is the portion of the SRADC that determines 
the maximum operating speed. In order to reduce the propagation time 
through the analog chain the highest speed amplifiers available are 
utilized and hot carrier diode switches are used for gain switching. Also 
the amplifiers are operated over as low an output voltage swing as is 
feasible. These measures tend to increase bias errors, however. Hot 
carrier diode switches inherently produce bias errors, high speed 
amplifiers do not necessarily have good d.c. characteristics and the ratio 
of output offset to true signal is increased. 
The input to the n bit parallel analog/digital converter goes through its 
range of possible voltage levels in every sub-range as the analog input 
goes through its full dynamic range. Bias errors in the analog chain can 
produce saturation of the analog/digital converter in some sub-ranges for 
a given analog input. This produces discontinuities in the final 
analog/digital converter output. Accordingly, there currently exists the 
need for automatic bias correction circuits that obviate the adverse 
effects of the foregoing enumerated source of bias error. The present 
invention is directed toward satisfying that need. 
SUMMARY OF THE INVENTION 
The device to which the invention applies is a successive ranged 
analog/digital converter (SRADC) in which an analog input is applied to a 
switchable gain amplifier chain (analog) the output of which is supplied 
to an n bit parallel analog/digital converter. The n bit parallel 
analog/digital converter includes a comparator bank whose output taps 
provide logic functions that define the various ranges of the SRADC. The 
circuit of the invention comprises a logic circuit that selects 
appropriate logic functions and applies them to dual flip flop circuits 
which in turn enable and effect counting in up/down counters. The up/down 
counters drive digital/analog converters which provide bias correction of 
bias errors for the particular sub-range the circuit is monitoring. The 
invention also includes disabling means for preventing operation in the 
first sub-range of the SRADC. 
It is a principal object of the invention to provide a new and improved 
bias error correction circuit for use in successive ranged analog/digital 
converters. 
It is another object of the invention to provide means for correcting bias 
errors in a successive ranged analog/digital converter that does not 
require the use of manual bias adjustments. 
It is another object of the invention to provide means for correcting bias 
errors in a successive ranged analog/digital converter that does not 
interrupt normal operation of the system nor require the use of 
calibration inputs. 
These together with other objects, features and advantages of the invention 
will become more readily apparent from the following detailed description 
when taken in conjunction with the illustrative embodiment in the 
accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to the block diagram of FIG. 1 the successive ranged 
analog/digital converter to which the invention applies comprises the 
analog switchable gain amplifier chain 5, n bit parallel analog/digital 
converter 6, n bit shift 7, register 8, prime digital/analog converter 9 
and summing means 11. This device is described in detail in U.S. Pat. No. 
3,956,746 issued May 11, 1976 to Thomas K. Lisle et al entitled 
SUCCESSIVELY RANGED A/D CONVERTER WITH ERROR CORRECTION. The bias 
correction circuitry which comprises the invention is fed from the 
comparator circuit of n bit parallel analog/digital converter 6 and 
supplies its bias correction signals to switchable gain amplifier chain 5 
as hereinafter described. 
Operation of the successive ranged analog/digital converter is as follows: 
The output from n bit parallel analog/digital converter 6 is loaded into 
successively lower order bits of register 8 which addresses the Prime 
digital/analog Converter 9. In a given sub-range the Prime digital/analog 
converter output is subtracted from the analog input by summing means 11 
and amplified by the analog chain of switchable gain amplifier chain 5. 
The gain of this analog chain increases by 2.sup.n for each succeeding 
subrange. The output from the analog chain is analog to digital converted 
to generate the next n bits of the final analog/digital output. 
The n-bit parallel analog/digital converter 6 contains 2.sup.n-1 
comparators. FIG. 2 is a schematic diagram of the comparator network. The 
input signal is applied directly to the non-inverting inputs of every 
comparator 13. The inverting inputs of the comparators are connected to 
taps of a linear voltage divider 14 connected between ground and a voltage 
reference. Thus as the input to the analog/digital converter traverses its 
range from minimun to maximum, the comparator outputs progress from all 
"zero" logic state outputs to all ones in a linear fashion. 
FIG. 3 is a simplified diagram of one possible circuit which mechanizes the 
invention. It comprises OR gate 15, NOR gates 16, 17, flip flop 20, dual 
flip flops 18, 19, up/down counters 21, 22 and digital/analog converters 
23, 34. Operation of the circuit is as follows: At the end of the first 
subrange the function SEVEN+ONE is strobed by clock CK1 into a flip-flop 
20. The output from this flip flop (DIS) will disable the operation of the 
corrective circuitry. That is, during the first subrange, when the most 
significant bits are generated, the corrective circuitry is disabled 
because saturation in this range (7&lt;INPUT&lt;1) means that the analog input 
has exceeded its dynamic range. Clock CK2 strobes the function SIX+TWO (if 
DIS=0) and SIX into dual flip-flop 19. If the strobed function 
SIX+TWO=ENABLE 1 is equal to a logic one then corrective action must occur 
and ENABLE 1 enables up down counter 21 whose output bits drive 
digital/analog converter 23. The direction of the counter (UP or DOWN) is 
determined by SIX at the time of CK2. If SIX is a logic one then the 
counter must count up. The signal CORRECTION 1 out of digital/analog 
converter 23 is applied to the SRADC analog chain at a point where it will 
have the most effect for correcting bias errors in that subrange. The 
action in the next subrange is identical to that in the subrange 
hereinabove described so that this scheme can be extended to any number of 
subranges as is desired. 
While the invention has been discribed in terms of one presently preferred 
embodiment it is understood that the words which have been used are words 
of description rather than words of limitation and that changes within the 
purview of the appended claims may be made without departing from the 
scope and spirit of the invention in its broader aspects.