Image sensor device

An image sensor device includes a substrate having a pixel array region, isolation structures in the substrate separating pixel regions from one another in the pixel array region, a photo-sensing region in each of the pixel regions, and a reflective cavity structure in the substrate within each of the pixel region. The reflective cavity structure continuously extends from a bottom of the isolation structure to a deeper central portion of each of the pixel regions, thereby forming a dish-like profile. The reflective cavity structure has a reflective index smaller than that of the substrate.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of Taiwan patent application No. 104124668, filed on Jul. 30, 2015, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor image sensor device and, more particularly, to a front-side illuminated (FSI) CMOS image sensor (CIS) device having an in-substrate reflective cavity structure and a fabrication method thereof.

2. Description of the Prior Art

Complementary metal oxide semiconductor (CMOS) image sensor has been widely used in, for example, security monitoring, digital cameras, toys, cell phones, video phones and other imaging products. With smart phones and tablet PCs become thinner, lighter, and more complicate, CMOS image sensor needs to continue to reduce the size and improve the resolution.

Generally, a CMOS image sensor comprises a plurality of pixels arranged in a pixel array. Each pixel typically has a photodiode fabricated within a semiconductor substrate. The incident light can be converted to a current signal.

As the size of the CMOS image sensor continues to shrink, the spacing between two adjacent pixels also decreases. The incident light causes increased optical scattering noise between the pixels, leading to reduced quantum efficiency (QE) and photosensitivity. The decreased spacing between two adjacent pixels also results in severe optical crosstalk. The aforesaid optical interference makes the spatial resolution and the overall sensitivity of the image sensor difficult to improve, and will produce color mixing, which causes the image noise.

Therefore, there remains a need in the art for an improved CMOS image sensor structure, which is capable of solving the problem and the drawback of the prior art, in particular, to improve the optical crosstalk between pixels, and improve the quantum efficiency.

SUMMARY OF THE INVENTION

It is therefore one object of the invention to provide an improved front-side illuminated (FSI) CMOS image sensor (CIS) device, which is capable of avoiding optical interference between pixels and enhancing the sensitivity and quantum efficiency of the image sensor device.

According to one embodiment of the invention, an image sensor device includes a substrate having a pixel array region, isolation structures in the substrate separating pixel regions from one another in the pixel array region, a photo-sensing region in each of the pixel regions, and a reflective cavity structure in the substrate within each of the pixel region. The reflective cavity structure continuously extends from a bottom of the isolation structure to a deeper central portion of each of the pixel regions, thereby forming a dish-like profile. The reflective cavity structure has a reflective index smaller than that of the substrate.

According to one embodiment of the invention, an image sensor device includes a substrate having a pixel array region comprising therein a plurality of pixel regions; a reflection layer structure disposed at a predetermined depth in the substrate within each of the pixel regions; a plurality of isolation structures in the substrate separating the pixel regions from one another in the pixel array region; and a photo-sensing region in the substrate within each of the pixel regions. The reflection layer structure has a reflective index smaller than that of the substrate.

DETAILED DESCRIPTION

The present invention pertains to a front-side illuminated (FSI) CMOS image sensor (CIS) device, which is capable of avoiding optical interference between pixels and enhancing the sensitivity and quantum efficiency of the image sensor device.

Please refer toFIG. 1toFIG. 7.FIG. 1toFIG. 7are schematic, cross-sectional diagrams showing a method for fabricating a CMOS image sensor in accordance with one embodiment of the invention. As shown inFIG. 1, first, a substrate100is provided. The substrate100includes a pixel array region102and a peripheral circuit region104. According to the embodiment of the invention, the substrate100may be a silicon substrate with a refractive index (n1) of about 4.5, but not limited thereto.

Subsequently, a patterned hard mask layer120is formed on the substrate100. Using the patterned hard mask layer120as an etching mask, a dry etching process is carried out to etch the substrate100, thereby forming a plurality of trenches110in the substrate100. The patterned hard mask layer120may comprise a single layer or multi-layer structure. For example, the patterned hard mask layer120may comprise a silicon oxide layer122and a silicon nitride layer124, but not limited thereto.

As shown inFIG. 2, a plurality of isolation structures112are formed within the trenches110, respectively, to thereby separate the pixel regions102a, for example, red (R) pixels, green (G) pixels, and blue (B) pixels, from one another. For example, a high-density plasma (HDP) oxide layer may be first deposited on the substrate100. The HDP oxide layer is then subjected to a polishing process using the patterned hard mask layer120as a polishing stop layer, but not limited thereto. According to the embodiment of the invention, after forming the isolation structures112, at least the silicon nitride layer124of the patterned hard mask layer120is removed.

As shown inFIG. 3, a patterned photoresist layer130is formed on the substrate100. The patterned photoresist layer130covers the peripheral circuit region104and reveals the pixel array region102. Subsequently, an ion implantation process140is performed to form a doping region142with a predetermined doping profile in the substrate100within the pixel array region102. The patterned photoresist layer130is then removed.

During the ion implantation process140, the silicon oxide layer122may function as a screen layer that avoids the damage to the surface of the substrate100. The ion implantation process140may be an oxygen ion implantation process and the doping region142may be an oxygen ion doping region, but not limited thereto. In other embodiments, other dopants, for example, nitrogen, may be employed. In other embodiments, two or more than two kinds of dopants may be employed, for example, oxygen and nitrogen.

Since the isolation structures112in the pixel array region102, the oxygen ions are implanted to various depth in the substrate100during the ion implantation process140, to thereby form the aforesaid predetermined doping profile. For example, the doping region142has a shallower doping depth directly under the isolation structures112, and it continuously extends to a deeper region at a middle area of each pixel region102a, thereby forming a disk shaped or bowl shaped doping profile within each pixel region102a. According to the embodiment of the invention, the depth d of the doping region142at a middle area of each pixel region102amay be greater than or equal o 6000 angstroms.

As shown inFIG. 4, after the ion implantation process140, an anneal process, for example, at a high temperature above 850° C., may be performed to densify the HDP oxide layer and make the dopants in the doping region142react with the silicon atoms, thereby transforming the doping region142into a reflective cavity structure144having a thickness t ranging between 20 and 1000 angstroms. Likewise, the reflective cavity structure144continuously extends from a shallower portion directly under the isolation structures112to the deeper portion at the middle region of each pixel region102a, to thereby form a disk shaped or bowl shaped profile. Subsequently, the silicon oxide layer122is removed. According to the embodiment of the invention, the reflective cavity structure144may be indirect contact with the bottom of the isolation structures112, but not limited thereto. In other embodiments, the reflective cavity structure144may not be in direct contact with the bottom of the isolation structures112.

According to the embodiment of the invention, the reflective cavity structure144may be composed of silicon dioxide having a refractive index (n2) of about 1.5. Therefore, the refractive index of the reflective cavity structure144is smaller than that of the surrounding substrate100, and a large difference of the refractive index between the substrate100and the reflective cavity structure144may be present. In other embodiments, the reflective cavity structure144may be composed of other materials, for example, silicon oxynitride, silicon nitride, or the like.

As shown inFIG. 5, gate structures160,260are formed on the substrate100within each pixel region102aand peripheral circuit region104respectively. Subsequently, photo-sensing region150and floating drain region162may be formed in the substrate100on two opposite sides of each gate structure160. Source region262and drain region264may be formed in the substrate100on two opposite sides of each gate structure260. The gate structures160,260may comprise a dielectric layer and a conductive layer. The dielectric layer may comprise silicon oxide and the conductive layer may comprise crystalline silicon, undoped polysilicon, doped polysilicon, amorphous silicon, metal silicide, or any combinations thereof. Spacers such as silicon oxide spacer, silicon nitride space or a combination thereof may be formed on sidewalls of the gate structures160,260.

The photo-sensing region150may be a photodiode comprising a first conductivity type doping region152and a second conductivity type doping region154, wherein the first conductivity type is opposite to the second conductivity type. For example, the substrate100is a P type substrate, the first conductivity type doping region152is an N type doping region, the second conductivity type doping region154is a P type doping region, the floating drain region162, the source region262and the drain region264are N type doping regions, and vice versa. For example, the first conductivity type doping region152may be a lightly doping region, the second conductivity type doping region154, the floating drain region162, the source region262and the drain region264may be heavily doping regions.

According to the embodiment of the invention, a contact etching stop layer (CESL)170may be conformally deposited on the substrate100, but not limited thereto. The contact etching stop layer170may comprise silicon nitride.

As shown inFIG. 6, subsequently, an interconnection structure180comprising, for example, at least one dielectric layer and at least one conductive layer, is formed on the substrate100within the pixel array region102and the peripheral circuit region104. The dielectric layer may comprise silicon dioxide, but not limited thereto. The conductive layer may comprise aluminum or copper, but not limited thereto. According to the embodiment of the invention, the interconnection structure180may comprise dielectric layers181,183,185,187. According to the embodiment of the invention, the interconnection structure180may comprise conductive layers M1, V1, M2, V2, M3. The conductive layers M1, M2, M3may be circuit layers. The conductive layer V1may be a via plug connecting conductive layer M1to conductive layer M2. The conductive layer V2may be a via plug connecting conductive layer M2to conductive layer M3. According to the embodiment of the invention, the conductive layers M1, V1, M2, V2, M3within the pixel array region102may be fabricated directly above the isolation structures112for reducing the light scattering of the incident light.

As shown inFIG. 7, a passivation layer189is formed on the dielectric layer187. Subsequently, a color filter layer190is formed on the passivation layer189. According to the embodiment of the invention, the color filter layer190may cover the pixel array region102and the peripheral circuit region104. The fabrication method for making the color filter layer190is well known in the art and therefore the details will be omitted. Subsequently, a micro lens192is formed on the color filter layer190within the pixel array region102.

Because of the large difference of refractive index between the reflective cavity structure144and the substrate100, total reflection occurs at the interface between reflective cavity structure144and the substrate100when the incident light Lienters the substrate100. The reflected light is accordingly guided back to the photo-sensing region150, thereby increasing the quantum efficiency. In addition, the reflective cavity structure144may be used to isolate noise from other pixels and reduce light interference between pixels, thereby increasing the sensitivity of each pixel.

Please refer toFIG. 8toFIG. 14.FIG. 8toFIG. 14are schematic, cross-sectional diagrams showing a method for fabricating a CMOS image sensor in accordance with another embodiment of the invention, wherein like numeral numbers designate like regions, elements, or layers.

As shown inFIG. 8, likewise, a substrate100is provided. The substrate100includes a pixel array region102and a peripheral circuit region104. According to the embodiment of the invention, the substrate100may be a silicon substrate with a refractive index (n1) of about 4.5, but not limited thereto. Subsequently, a patterned photoresist layer130is formed on the substrate100. The patterned photoresist layer130covers the peripheral circuit region104and only reveals the pixel array region102. Thereafter, an ion implantation process140is performed to form a doping region142with predetermined depth in the substrate100within the pixel array region102. The patterned photoresist layer130is then removed.

According to the embodiment of the invention, the ion implantation process140may be an oxygen ion implantation process and the doping region142may be an oxygen ion doping region, but not limited thereto. In other embodiments, other dopants, for example, nitrogen or the like, may be employed. In other embodiments, two or more than two kinds of dopants may be employed, for example, oxygen and nitrogen.

According to the embodiment of the invention, the doping region142may continuously extend across and cover the entire the pixel array region102. According to the embodiment of the invention, the doping region142may have substantially the same depth d in the substrate100. For example, the depth d of the doping region142may be greater than or equal to 6000 angstroms.

As shown inFIG. 9, after the ion implantation process140, an anneal process, for example, at a high temperature above 850° C., may be performed to make the dopants in the doping region142react with the silicon atoms, thereby transforming the doping region142into a reflective layer structure145having a thickness t ranging between 20 and 1000 angstroms. According to the embodiment of the invention, the reflective layer structure145may be composed of silicon dioxide having a refractive index (n2) of about 1.5. Therefore, the refractive index of the reflective cavity structure145is smaller than that of the surrounding substrate100, and a large difference of the refractive index between the substrate100and the reflective layer structure145may be present. In other embodiments, the reflective layer structure145may be composed of other materials, for example, silicon oxynitride, silicon nitride, or the like.

As shown inFIG. 10, a patterned hard mask layer120is then formed on the substrate100. Subsequently, using the patterned hard mask layer120as an etching hard mask, an etching process is performed to etch the substrate100not covered by the patterned hard mask layer120, thereby forming a plurality of first trenches210in the substrate100within the peripheral circuit region104and forming a plurality of second trenches310in the substrate100within the pixel array region102. According to the embodiment of the invention, the second trenches310have a depth that is deeper than that of the first trenches210, but not limited thereto. In other embodiments, the second trenches310may have the same depth as that of the first trenches210. The patterned hard mask layer120may comprise single layer or multi-layer structure. For example, the patterned hard mask layer120may comprise a silicon oxide layer122and a silicon nitride layer124, but not limited thereto.

The methods for forming trenches in the substrate100having two different trench depths are well known in the art, and the details are therefore omitted. For example, a photoresist pattern (not shown) may be formed to cover the peripheral circuit region104when forming the second trenches310, and then an etching process is performed to etch the substrate100not covered by the photoresist pattern120until the reflective layer structure145is revealed. According to the embodiment of the invention, the reflective layer structure145may act as an etching stop layer.

As shown inFIG. 11, a plurality of isolation structures212,312are formed within the first trenches210,310respectively. The isolation structures312may be contiguous with the underlying reflective layer structure145, thereby separating the pixel regions102a, for example, red (R) pixels, green (G) pixels, and blue (B) pixels, from one another in the pixel array region102. For example, a high-density plasma (HDP) oxide layer may be first deposited on the substrate100. The HDP oxide layer is then subjected to a polishing process using the patterned hard mask layer120as a polishing stop layer, but not limited thereto. According to the embodiment of the invention, after forming the isolation structures212,312, the patterned hard mask layer120may be removed.

As shown inFIG. 12, gate structures160,260are formed on the substrate100within each pixel region102aand peripheral circuit region104respectively. Subsequently, photo-sensing region150and floating drain region162may be formed in the substrate100on two opposite sides of each gate structure160. Source region262and drain region264may be formed in the substrate100on two opposite sides of each gate structure260. The gate structures160,260may comprise a dielectric layer and a conductive layer. The dielectric layer may comprise silicon oxide and the conductive layer may comprise crystalline silicon, undoped polysilicon, doped polysilicon, amorphous silicon, metal silicide, or any combinations thereof. Spacers such as silicon oxide spacer, silicon nitride space or a combination thereof may be formed on sidewalls of the gate structures160,260.

The photo-sensing region150may be a photodiode comprising a first conductivity type doping region152and a second conductivity type doping region154, wherein the first conductivity type is opposite to the second conductivity type. For example, the substrate100is a P type substrate, the first conductivity type doping region152is an N type doping region, the second conductivity type doping region154is a P type doping region, the floating drain region162, the source region262and the drain region264are N type doping regions, and vice versa. For example, the first conductivity type doping region152may be a lightly doping region, the second conductivity type doping region154, the floating drain region162, the source region262and the drain region264may be heavily doping regions.

According to the embodiment of the invention, a contact etching stop layer (CESL)170may be conformally deposited on the substrate100, but not limited thereto. The contact etching stop layer170may comprise silicon nitride.

As shown inFIG. 13, subsequently, an interconnection structure180comprising, for example, at least one dielectric layer and at least one conductive layer, is formed on the substrate100within the pixel array region102and the peripheral circuit region104. The dielectric layer may comprise silicon dioxide, but not limited thereto. The conductive layer may comprise aluminum or copper, but not limited thereto. According to the embodiment of the invention, the interconnection structure180may comprise dielectric layers181,183,185,187. According to the embodiment of the invention, the interconnection structure180may comprise conductive layers M1, V1, M2, V2, M3. The conductive layers M1, M2, M3may be circuit layers. The conductive layer V1may be a via plug connecting conductive layer M1to conductive layer M2. The conductive layer V2may be a via plug connecting conductive layer M2to conductive layer M3. According to the embodiment of the invention, the conductive layers M1, V1, M2, V2, M3within the pixel array region102may be fabricated directly above the isolation structures112for reducing the light scattering of the incident light.

As shown inFIG. 14, a passivation layer189is formed on the dielectric layer187. Subsequently, a color filter layer190is formed on the passivation layer189. According to the embodiment of the invention, the color filter layer190may cover the pixel array region102and the peripheral circuit region104. The fabrication method for making the color filter layer190is well known in the art and therefore the details will be omitted. Subsequently, a micro lens192is formed on the color filter layer190within the pixel array region102.

Because of the large difference of refractive index between the reflective layer structure145and the substrate100and between the isolation structures312and the substrate100, total reflection occurs at the interface between reflective layer structure145and the substrate100and between the isolation structures312and the substrate100when the incident light Lienters the substrate100. The reflected light is accordingly guided back to the photo-sensing region150, thereby increasing the quantum efficiency. In addition, the reflective layer structure145may be used to isolate noise from other pixels and reduce light interference between pixels, thereby increasing the sensitivity of each pixel.