Signal processing system capable of performing voltage and frequency calibration

A signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit. The power management unit provides a first voltage to the digital signal processing circuit. When in a calibration mode the digital control circuit controls the power management unit to set the first voltage at a minimum preset value, controls the digital signal processing circuit to operate under a first calibration target frequency, triggers the digital signal processing circuit to perform a built-in self-test, raises the first voltage when the built-in self-test fails, triggers the digital signal processing circuit to perform the built-in self-test again, and stores the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to a non-volatile memory when the built-in self-test has succeeded.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a signal processing system, and more particularly to a signal processing system capable of performing the voltage and frequency calibration.

2. Description of the Prior Art

Since multimedia applications are widely used in different fields, the requirements for the quality of multimedia applications also become higher. The multimedia applications, such as images and sound effects, often involve a large number of complex and repetitive calculations; therefore, the computing power of a digital signal processor is often required to present images and sounds in real-time.

Generally, the maximum operating frequency that a digital signal processor can achieve is related to the power supply voltage it receives. For example, when the digital signal processor receives a voltage of 1.1V, the highest operating frequency of the digital signal processor may be 200 MHz, but when the digital signal processor receives a voltage of 1.2V, the highest operating frequency of the digital signal processor may be increased to 300 MHz. Therefore, to ensure that the digital signal processor can receive the suitable voltage and operate under the desired operating frequency, the manufacturer of the digital signal processor will store the values of the suitable voltages for different operating frequencies before shipment. Consequently, the user can have the digital signal processor operate in the desired frequencies according to the stored voltage values. However, different digital signal processors may have different characteristics due to the uncontrollable variation caused in the manufacturing processes. Therefore, the corresponding relationship between operating frequencies and voltages for each digital signal processor may be different. Furthermore, power management units used to provide power supply voltages may also have different characteristics, making the testing process even more complicate.

SUMMARY OF THE INVENTION

One embodiment of the present invention discloses a signal processing system. The signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit.

The power management unit is coupled to the digital signal processing circuit and provides a first voltage to the digital signal processing circuit. The digital control circuit is coupled to the digital signal processing circuit and the power management unit. The digital control circuit includes a non-volatile memory.

When in a calibration mode, the digital control circuit controls the power management unit to set the first voltage at a minimum preset value, controls the digital signal processing circuit to operate under a first calibration target frequency, triggers the digital signal processing circuit to perform a built-in self-test, raises the first voltage when the built-in self-test fails, triggers the digital signal processing circuit to perform the built-in self-test again, and stores the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to the non-volatile memory when the built-in self-test has succeeded.

Another embodiment of the present invention discloses a method for operating a signal processing system. The signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit. The digital control circuit includes a non-volatile memory.

The method includes, in a calibration mode, the digital control circuit controlling the power management unit to output a first voltage at a minimum preset value to the digital signal processing circuit, the digital control circuit controlling the digital signal processing circuit to operate under a first calibration target frequency, the digital control circuit triggering the digital signal processing circuit to perform a built-in self-test, the digital control circuit controlling the power management unit to raise the first voltage when the built-in self-test fails, the digital control circuit triggering the digital signal processing circuit to perform the built-in self-test again, and the digital control circuit storing the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to the non-volatile memory when the built-in self-test has succeeded.

DETAILED DESCRIPTION

FIG.1shows a signal processing system100according to one embodiment of the present invention. The signal processing system100includes a digital signal processing circuit110, a power management unit120, and a digital control circuit130.

The power management unit120can be coupled to the digital signal processing circuit110and can provide a first voltage V1to the digital signal processing circuit110as a power supply. In addition, the power management unit120can also be coupled to the digital control circuit130, and can provide a second voltage V2to the digital control circuit130as a power supply.

The digital control circuit130can be coupled to the digital signal processing circuit110and the power management unit120. In some embodiments, the digital control circuit130can control the value of the first voltage V1outputted by the power management unit120. That is, the digital control circuit130can control the value of the voltage received by the digital signal processing circuit110. In addition, the digital control circuit130can be used to control the operating frequency of the digital signal processing circuit110. For example, the digital control circuit130can be coupled to a clock generator112of the digital signal processing circuit110and can control the clock generator112to generate a clock signal having the desired operating frequency. Consequently, the digital signal processor114of the digital signal processing circuit110can perform operations according to the clock signal generated by the clock generator112.

In some embodiments, the digital control circuit130can be used to calibrate the voltage corresponding to the desired operating frequency of the digital signal processing circuit110. The digital control circuit130can include a non-voltage memory132, and can store the operating frequencies and the calibrated voltage values corresponding to the operating frequencies to the non-volatile memory132. Consequently, later in the practical application mode, the value of the voltage corresponding to the target operating frequency can be read from the non-volatile memory132, so the digital signal processing circuit110can function normally under the target frequency. In some embodiments, the non-volatile memory132can be a one-time programmable (OTP) non-volatile memory so the user will not overwrite the recorded voltage values in the non-volatile memory132unintentionally. However, the present invention does not limit the non-volatile memory132to be an OTP memory. In some other embodiments, the non-volatile memory132can be a multiple-time programmable non-volatile memory.

FIG.2shows a flowchart of a method200for operating the signal processing system100in a calibration mode. In the calibration mode, the method200can include steps S210to S290.S210: the digital control circuit130controls the power management unit120to output the first voltage V1having a minimum preset value to the digital signal processing circuit110;S220: the digital control circuit130controls the digital signal processing circuit110to operate under a calibration target frequency;S230: the digital control circuit130triggers the digital signal processing circuit110to perform a built-in self-test;S240: if the built-in self-test fails, go to step S250, otherwise go to step S260;S250: the digital control circuit130controls the power management unit110to raise the first voltage V1, go to step S230;S260: the digital control circuit130stores the calibration target frequency and the value of the first voltage corresponding to the calibration target frequency to the non-volatile memory132;S270: if there's another frequency to be calibrated, go to step S280, else go to step S290;S280: update the calibration target frequency and go to step S210;S290: calibration completes.

In step S210, the digital control circuit130can control the power management unit120to provide the first voltage V1having the minimum preset value, for example, but not limited to 1V. In step S220, the digital control circuit130can control the digital signal processing circuit110to operate under the calibration target frequency F1. Later, in step S230, the digital control circuit130can further trigger the digital signal processing circuit110to perform the built-in self-test (BIST) and determine if the test result has succeeded in step S240.

For example, the digital control circuit130can further include a first control unit134. The first control unit134can be coupled to the digital signal processing circuit110and a power management unit120. The first control unit134can output the voltage control signal SIGCTRLVto the power management unit120to adjust the value of the first voltage V1, and can output the frequency control signal SIGCTRLFto the clock generator112of the digital signal processing circuit110to control the operating frequency of the digital signal processing circuit110. Afterward, the digital control circuit130can determine the result of the BIST and see if the test has passed or failed.

InFIG.1, the digital signal processor114of the digital signal processing circuit110can include an internal dynamic random access memory1141and a built-in self-test unit1142. When the digital signal processor114performs the calculations, the internal dynamic random access memory1141can be used to store the information required during the process of the calculation. The built-in self-test unit1142can be coupled to the internal dynamic random access memory1141. In some embodiments, the digital control circuit130can trigger the built-in self-test unit1142to perform the built-in self-test. In this case, the built-in self-test unit1142can read the data stored in the internal dynamic random access memory1141and transmit the data to the digital control circuit130so that the digital control circuit130can determine if the digital signal processing circuit110has passed or failed the built-in self-test.

Furthermore, inFIG.1, the digital signal processing circuit110can further include a static random access memory116and a built-in self-test unit118. The static random access memory116can be coupled to the digital signal processor114through buses BUS, and can be used to store data of greater sizes that are required for the calculations. The built-in self-test unit118can be coupled to the static random access memory116. In this case, the digital control circuit130can trigger the built-in self-test unit118to perform the built-in self-test. That is, in step S230, the digital control circuit130can trigger the built-in self-test units1142and118to view the data stored in the internal dynamic random access memory1141and the static random access memory116, and determine the test results accordingly.

In step S240, if the result of the built-in self-test of the digital signal processing circuit110turns out to have failed, it may imply that the first voltage V1is not high enough for the digital signal processing circuit110to function normally under the calibration target frequency F1. Therefore, in step S250, the digital control circuit130can control the power management unit120to raise the value of the first voltage V1, and step S230can be performed again to trigger the digital signal processing circuit110and perform the built-in self-test. Consequently, before the digital signal processing circuit110can pass the built-in self-test, the first voltage V1will increase gradually. In some embodiments, the first voltage V1can be added with a fixed value, for example, but not limited to 0.05V, whenever step S250is performed. However, the embodiment is not limited thereto.

When the digital signal processing circuit110passes the built-in self-test, it may imply that the first voltage V1is high enough for the digital signal processing circuit110to function normally under the calibration target frequency F1. In this case, the digital control circuit130can store the calibration target frequency F1and the value of the first voltage V1corresponding to the calibration target frequency F1to the non-volatile memory132.

In step S270, if there is another operating frequency to be calibrated, the calibration target frequency F1can be updated as a next calibration target frequency F2in step S280. Next, step S210can be performed again, and the first voltage V1will be reset to the minimum preset value. Also, the digital control circuit130can control the digital signal processing circuit110to operate under the calibration target frequency F2, and trigger the digital signal processing circuit110to perform the built-in self-test. Afterward, the aforesaid operations can be repeated until the digital signal processing circuit110passes the built-in self-test, and the calibration target frequency F2and the value of the first voltage V1corresponding to the calibration target frequency F2can be stored in the non-volatile memory132.

Consequently, with the method200, the values of the first voltage V1required for different operating frequencies can be calibrated in the calibration mode. The digital control circuit130can control the power management unit120to increase the first voltage V1for seeking the proper voltage value required for the digital signal processing circuit110to operate under the target operating frequency; therefore, the proper voltage value suitable for each of the digital signal processing circuits110in different signal processing systems100can be found even if the digital signal processing circuits110and the power management units120have different characteristics due to the manufacturing process variation. In addition, since the operating frequencies and the values of the first voltage corresponding to the operating frequencies can be stored in the non-volatile memory132, the record can be preserved even after the system power down, so the signal processing system100can access the corresponding voltage values repeatedly.

FIG.3shows a flowchart of a method300for operating the signal processing system100in an application mode. In the application mode, the method300can include steps S310to S330.S310: the digital control circuit130reads a calibrated value of the first voltage V1corresponding to an application target frequency from the non-volatile memory132;S320: the digital control circuit130controls the power management unit120to set the first voltage V1at the calibrated value; andS330: the digital control circuit130controls the digital signal processing circuit110to operate under the application target frequency.

That is, in the application mode, after the user determines the application target frequency of the digital signal processing circuit110, the digital control circuit130can read the calibrated value of the first voltage V1corresponding to the application target frequency from the non-volatile memory132in step S310, and control the power management unit120to output the first voltage V1having the calibrated value. Consequently, the digital signal processing circuit110can be operated under the application target frequency normally in step S33.

InFIG.1, the digital control circuit130can further include a second control unit136. The second control unit136can be coupled to the first control unit134. The second control unit136can receive the system instructions and have the first control unit134be switched between the calibration mode and the application mode. For example, when the second control unit136receives the system instruction INS1, the second control unit136can have the first control unit134enter the calibration mode according to the system instruction INS1and set the calibration target frequency F1. Also, when the second control unit136receives the system instruction INS2, the second control unit136can have the first control unit134enter the application mode according to the system instruction INS2and set the application target frequency.

InFIG.1, the digital control circuit130can include two control units134and136for controlling different circuits. However, in some other embodiments, the digital control circuit130can also use one control unit to perform the required operations according to the system requirement.

In summary, the signal processing systems and the methods for operating the signal processing system provided by the embodiments of the present invention can calibrate the voltage values corresponding to different operating frequencies; therefore, the digital signal processing circuit can receive the proper voltage and operate under the desired frequency normally. In addition, since the signal processing systems can adjust the values of the voltages outputted by the power management units gradually in the calibration mode, the proper voltage value suitable for each of the signal processing systems can be found even if the signal processing systems have different characteristics due to the manufacturing process variation. Consequently, the calibration process can be simplified, and the digital signal processing circuit would be able to operate under the desired frequencies normally, thereby improving the yield rate of the signal processing system.