Method of forming micro pattern of semiconductor device

The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Korean patent application number 10-2007-045999, filed on May 11, 2007, which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a method of forming a micro pattern of a semiconductor device and, more particularly, to a method of forming a micro pattern as it applies to the formation of DRAM bit line contact holes.

As the integration level of semiconductor devices is increased, a minimum line width gradually shrinks. Several process methods are employed in order to implement a desired micro line width due to the higher integration of devices.

However, a micro pattern formed using a spacer is applicable to only a line and space pattern. In particular, the micro pattern can be applied to a case where the patterns of a cell gate region have a very simple pattern, such as NAND flash memory devices, or a 2-dimensional array having an excellent regularity. If a Double Exposure & Etch Technique (DEET) method is used, a bit line contact hole pattern of a DRAM can be formed, but a Critical Dimension (CD) becomes irregular due to overlay problem. Further, since a mask formation process has to be performed twice, the production cost is increased.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to form a micro pattern having a target CD by forming a first auxiliary pattern having a first contact hole, which has the same shape as that of an insulating pattern, at the center of four adjacent insulating patterns, which form a quadrilateral, and is also applicable to a DRAM bit line contact hole formation process.

According to a method of forming a micro pattern of a semiconductor device in accordance with a first embodiment of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.

The etch target layer may have a stack structure of a conductive layer and an insulating layer. The first hard mask layer may have a stack structure of an amorphous carbon layer and a SiON layer. The insulating patterns may be made of oxide.

The first auxiliary pattern may be formed from a carbon layer or a polysilicon layer. The first auxiliary pattern may have an etch selectivity different from that of the insulating patterns. The first auxiliary pattern may be formed to a thickness so that the first auxiliary pattern formed on a sidewall of an end of the insulating pattern touches with the first auxiliary pattern formed on a sidewall of an end of an adjacent insulating pattern. The first auxiliary pattern formed in the peripheral region of the contact hole may have a step with the first auxiliary pattern formed on the insulating patterns. The first auxiliary pattern formed in the peripheral region of the contact hole may be lower in height than the first auxiliary pattern formed on the insulating patterns. A second hard mask layer may be further formed on the first auxiliary pattern so that between-the contact holes are gap filled after the first auxiliary pattern is formed. The second hard mask layer may be made of a conductive material or an insulating material. The second hard mask layer may be made of an Organic Bottom Anti-Reflective Coating (OBARC) material containing silicon (Si), or a Spin on Glass (SOG) material. A bake process may be further performed after a deposition process when the SOG material is used. The second hard mask layer may have an etch selectivity different from that of the first auxiliary pattern. The second hard mask layer may be further removed until a top surface of the first auxiliary pattern is exposed after the second hard mask layer is formed.

The first auxiliary pattern may be etched using an etchback process. At the time of the etch process of the first auxiliary pattern formed on the insulating patterns, a top surface of the first auxiliary pattern formed in the peripheral region of the contact hole may be also partially removed. At the time of the removal process of the insulating patterns, the remaining second hard mask layer may be also removed. The second auxiliary pattern formed in the peripheral region of the contact hole may have a step with the second auxiliary pattern formed in the peripheral region of the insulating patterns. The second auxiliary pattern formed in the peripheral region of the contact hole may be lower in height than the second auxiliary pattern formed in the peripheral region of the insulating patterns.

According to a method of forming a micro pattern of a semiconductor device in accordance with a second embodiment of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second hard mask layer is formed between the first auxiliary patterns. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns and the second hard mask are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.

The etch target layer may have a stack structure of a conductive layer and an insulating layer. The first hard mask layer may have a stack structure of an amorphous carbon layer and a SiON layer. The insulating patterns may be made of oxide.

The e first auxiliary pattern may be formed from a carbon layer or a polysilicon layer. The first auxiliary pattern may have an etch selectivity different from that of the insulating patterns. The first auxiliary pattern may be formed to a thickness so that the first auxiliary pattern formed on a sidewall of an end of the insulating pattern touches with the first auxiliary pattern formed on a sidewall of an end of an adjacent insulating pattern. The first auxiliary pattern formed in the peripheral region of the contact hole may have a step with the first auxiliary pattern formed on the insulating patterns. The first auxiliary pattern formed in the peripheral region of the contact hole may be lower in height than the first auxiliary pattern formed on the insulating patterns.

The second hard mask layer may be made of a conductive material or an insulating material. The second hard mask layer may be made of an OBARC material containing silicon (Si), or a SOG material. A bake process may be further performed after a deposition process when the SOG material is used. The second hard mask layer may have an etch selectivity different from that of the first auxiliary pattern.

The first auxiliary pattern may be etched using an etchback process. At the time of the etch process of the first auxiliary pattern formed on the insulating patterns, a top surface of the first auxiliary pattern formed in the peripheral region of the contact hole may be also partially removed. The second auxiliary pattern formed in the peripheral region of the contact hole may have a step with the second auxiliary pattern formed in the peripheral region of the insulating patterns. The second auxiliary pattern formed in the peripheral region of the contact hole may be lower in height than the second auxiliary pattern formed in the peripheral region of the insulating patterns.

DESCRIPTION OF SPECIFIC EMBODIMENTS

FIGS. 1A to 1Hare plan views illustrating a method of forming a micro pattern of a semiconductor device according to an embodiment of the present invention.FIGS. 2A to 2Hare sectional views of the device taken along line A-A ofFIGS. 1A to 1H.FIGS. 3A to 3Hare sectional views of the device taken along line B-B ofFIGS. 1A to 1H. Process steps only in a cell region are described below for simplicity.

Referring toFIGS. 1A,2A and3A, an etch target layer102, a first hard mask layer104, and an insulating layer106are sequentially formed over a semiconductor substrate100. The etch target layer102may have a stack structure including a conductive layer and an insulating layer in order to form bit line contact holes. The first hard mask layer104may have a stack structure including an amorphous carbon layer104aand a silicon oxynitride (SiON) layer104b. The insulating layer106may be formed from oxide. Oxide is used for the insulating layer106because oxide is transparent, which makes wafer alignment possible in a subsequent photoresist pattern formation process and therefore an additional process for aligning the wafer does not need to be performed.

Photoresist patterns108are formed on the insulating layer106. In the prior art, the photoresist patterns108are formed in a subsequent process so that regions in which bit line contact holes will be formed are opened. In the present invention, however, the photoresist patterns108are formed only in regions in which bit line contact holes will be formed using a subsequent process. Further, each of the photoresist patterns108has a lozenge shape (or diamond shape) unlike the existing quadrilateral shape.

Referring toFIGS. 1B,2B and3B, insulating patterns106aare formed by etching the insulating layer106using the photoresist patterns108as an etch mask. The photoresist patterns108are then removed. Each of the insulating patterns106ahas a lozenge shape, which is the same as that of the photoresist patterns108.

Referring toFIGS. 1C,2C and3C, a first auxiliary pattern110is formed on a top surface of the first hard mask layer104and the insulating patterns106a. The first auxiliary pattern110may be formed from a carbon layer or a polysilicon layer. The reason why the first auxiliary pattern110uses a carbon layer or a polysilicon layer is that these layers have an etch selectivity different from that of the insulating patterns106a. This means the insulating patterns106acan be removed while preventing the first auxiliary pattern110from being damaged in a subsequent etch process. For this reason, the first auxiliary pattern110may be made of a material having an etch selectivity different from that of the insulating patterns106a.

If the first auxiliary pattern110formed on the sidewall of the end of the insulating patterns106ahaving a lozenge shape is formed to a thickness to the extent that it touches with the first auxiliary pattern110formed on the sidewall of the end of an adjacent insulating pattern106a(indicated by “a”), the first auxiliary pattern110having first contact holes112, which have the same shape as that of the insulating patterns106a, is formed at the center of the four adjacent insulating patterns106a, which form a quadrilateral, as shown inFIG. 5C. The first contact holes112are regions in which bit line contact holes are formed in a subsequent process. In the formation process of the first contact holes112, the first auxiliary pattern110formed in the peripheral region of the first contact holes112is lower in height than the first auxiliary pattern110formed on the insulating patterns106aby a step b.

Referring toFIGS. 1D,2D and3D, a second hard mask layer114is formed on the first auxiliary pattern110formed in the peripheral region of the first contact holes112, the first auxiliary pattern110formed on the insulating patterns106a, and the silicon oxynitride (SiON) layer104bso that the first contact holes112is gap filled. The second hard mask layer114may be made of a conductive material or an insulating material, such as Organic Bottom Anti-Reflective Coating (OBARC) containing silicon (Si) or Spin on Glass (SOG) having a good gap-fill characteristic. The SOG material contains impurities and moisture and therefore must go through a bake process after a deposition process in order to remove them. The second hard mask layer114may have an etch selectivity different from that of the first auxiliary pattern110.

The second hard mask layer114is formed so that it can prevent damage to the silicon oxynitride (SiON) layer104bexposed due to the first contact holes112in a subsequent etch process of the first auxiliary pattern110. However, in order to reduce the process steps, the second hard mask layer114may be omitted. In the case where the formation process of the second hard mask layer114is omitted, the silicon oxynitride (SiON) layer104bexposed due to the first contact holes112at the time of the etch process of the first auxiliary pattern110can be partially damaged, but a subsequent process will not be affected. Further, in a subsequent process of removing the insulating patterns106a, the silicon oxynitride (SiON) layer104bmay have an etch selectivity different from that of oxide of the insulating patterns106ain order to prevent the exposed silicon oxynitride (SiON) layer104bfrom being excessively damaged.

Referring toFIGS. 1E,2E and3E, the second hard mask layer114is etched using an etch process until a top surface of the first auxiliary pattern110is exposed. The first auxiliary pattern110is exposed using an etch process until a top surface of the insulating patterns106ais exposed, thus forming a second auxiliary pattern110a. The etch process may be performed using an etchback process. At the time of the formation process of the second auxiliary pattern110a, a top surface of the second auxiliary pattern110aformed in the peripheral region of the first contact holes112is partially removed, so the second auxiliary pattern110ahas a step c with the remaining second hard mask layer114.

Referring toFIGS. 1F,2F and3F, second contact holes116are formed between the second auxiliary patterns110aby removing the insulating patterns106aexposed in the formation process of the second auxiliary pattern110aand the remaining second hard mask layer114. The second contact holes116are regions in which bit line contact holes are formed in a subsequent process. At the time of the removal process of the insulating patterns106athe remaining second hard mask layer114, the insulating patterns106aand the second hard mask layer114have an etch selectivity different from that of the second auxiliary pattern110a, so that the second auxiliary pattern110acan be removed without being damaged.

Referring toFIGS. 1G,2G and3G, a first hard mask pattern104chaving a desired line and space is formed by etching the first hard mask layer104using the second auxiliary pattern110aas an etch mask. The first hard mask layer104may be removed using a dry etch process. The second auxiliary pattern110ais then removed.

Referring toFIGS. 1H,2H and3H, a target pattern102ais formed by etching the etch target layer102using the first hard mask pattern104c, having a desired line and space, as an etch mask. The etch target layer102is made of a material deposited to form bit line contact holes. Thus, the bit line contact holes can be formed by forming the target pattern102ausing an etch process. The first hard mask pattern104cis then removed.

As described above, the first auxiliary pattern having the first contact hole, which has the same shape as that of the insulating pattern, is formed at the center of the four adjacent insulating patterns, which form a quadrilateral. Thus, a micro pattern having a target CD can be formed and the present invention can also be applied to a DRAM bit line contact hole formation process.

Further, a micro pattern with a resolution higher than the resolution of the existing exposure equipment can be formed and applied to a formation process of DRAM bit line contact holes. Accordingly, the resolution limits of the exposure equipment can be overcome.

Moreover, micro patterns can be formed using existing exposure equipment without the need to develop new exposure equipment with increased resolution capability.

In addition, the process steps can be reduced by omitting the formation process of the second hard mask layer.

Incidentally, since the process steps are reduced, the production cost can be reduced.

The present invention is not limited to the disclosed embodiments, but may be implemented in various manners. The embodiments are provided to complete the disclosure of the present invention and to allow those having ordinary skill in the art to understand the scope of the present invention. The present invention is defined by the category of the claims.