Circuit and method for sub-harmonic elimination of a power converter

A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen.

FIELD OF THE INVENTION

The present invention is related generally to a power converter and, more particularly, to a circuit and method for sub-harmonic elimination of a power converter.

BACKGROUND OF THE INVENTION

Taking a typical flyback power converter for example, referring toFIG. 1, a rectifier circuit10is used to rectify an alternating-current (AC) input voltage VAC, a capacitor Cbulk is connected to the output of the rectifier circuit10to stabilize the direct-current (DC) input voltage Vbulk produced by the rectifier circuit10to apply to the primary coil Lp of a transformer12, a controller14provides a control signal GATE to switch a power switch M1connected in series with the primary coil Lp to convert the voltage Vbulk into a DC output voltage Vo, a current sense resistor Rcs is connected in series with the power switch M1to produce a current sense signal Vcs related to the current Ip of the power switch M1, the controller14has a pin COMP receiving a feedback signal derived from the DC output voltage Vo for performing negative feedback control, and the controller14determines the control signal GATE according to the current sense signal Vcs and a preset current limit signal. Recently, for making products more competitive, lowering costs has become one of the requirements for product development, and therefore selection of components is increasingly strict while the capacitor Cbulk is increasingly downsized. However, for systems of a same rating, when having low input voltage, the system using a smaller capacitor Cbulk will have shorter hold up time for the voltage Vbulk, so the voltage Vbulk at the primary side of the transformer12varies significantly, which may cause serious sub-harmonic problem when the system escapes from soft-start or becomes overloaded. Such serious sub-harmonic problem may cause the system, when fully loaded, unable to start-up with a low input voltage or lead to a significant difference between a high input voltage over current protection and a low input voltage over current protection.

FIG. 2illustrates the addressed sub-harmonic problem in the conventional flyback power converter, in which waveform20represents an internal clock CLK of the controller14, waveform22represents a leading-edge blanking signal LEB, waveform24represents the control signal GATE, waveform26represents the current limit signal, and waveform28represents the current sense signal Vcs. The clock CLK serves to determine the cycle of the control signal GATE, the leading-edge blanking signal LEB is used to blank spikes of the current sense signal Vcs when the power switch M1turns on, and the control signal GATE turns to low to turn off the power switch M1once the current sense signal Vcs becomes higher than the current limit signal. Under a low input voltage, the power switch M1has a longer on time, such as from time t1to time t2, to obtain adequate energy, and thus has a shorter off time since the power switch M1has a constant cycle, thereby causing incomplete release of energy. As a result, when the power switch M1turns on again, as shown at time t3, the initial level of the current sense signal Vcs will be higher than the previous one, so the current sense signal Vcs will sooner become higher than the current limit signal, as shown at time t4, and the on time of the power switch M1is shortened accordingly. The acute variation of the on time of the power switch M1may cause serious sub-harmonic problem to the flyback power converter.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a circuit for sub-harmonic elimination of a power converter.

Another objective of the present invention is to provide a method for sub-harmonic elimination of a power converter.

According to the present invention, a circuit for sub-harmonic elimination of a power converter includes a current limit signal controller to generate a switch signal according to the duty ratio of a power switch, and responsive to the switch signal, a selector selecting a final current limit signal from two current limit signals provided by two current limit signal generators, to limit the maximum value of the current of the power switch. When the duty ratio is smaller than a preset threshold value, the selector selects one of the two current limit signals as the final current limit signal, and when the duty ratio is larger than the preset threshold value, the selector selects the other of the two current limit signals as the final current limit signal.

According to the present invention, a method for sub-harmonic elimination of a power converter includes the steps of providing two current limit signals, detecting the duty ratio of the power switch, selecting the first current limit signal as the final current limit signal to limit the maximum value of the current of the power switch when the duty ratio is not larger than a preset threshold value, and selecting the second current limit signal as the final current limit signal when the duty ratio is larger than the preset threshold value.

According to the present invention, a circuit for sub-harmonic elimination of a power converter includes a current limit signal controller to generate a switch signal according to the duty ratio of a power switch, and responsive to the switch signal, a selector selecting one from a plurality of current limit signals provided by a plurality of current limit signal generators as a final current limit signal to limit the maximum value of the current of the power switch. When the duty ratio is smaller than a preset threshold value, the selector selects a first one of the plurality of current limit signals as the final current limit signal, and when the duty ratio is larger than the threshold value, the selector selects one from the others of the plurality of current limit signals in an order as the final current limit signal, and if the others of the plurality of current limit signals are all selected once in the order, selects the first current limit signal again as the final current limit signal.

According to the present invention, a method for sub-harmonic elimination of a power converter includes the steps of providing a plurality of current limit signals, detecting the duty ratio of a power switch, remaining a first one of the plurality of current limit signals as a final current limit signal to limit the maximum value of the current of the power switch when the duty ratio is not larger than a preset threshold value, and when the duty ratio is larger than the preset threshold value, selecting one from the others of the plurality of current limit signals in an order as the final current limit signal, and if the others of the plurality of current limit signals are all selected once in the order, selecting the first current limit signal again as the final current limit signal.

By selecting the final current limit signal according to the duty ratio of the power switch, an appropriate final current limit signal may be selected for the next cycle once the duty ratio becomes excessively large, and thus the duty ratio is prevented from acute variation which otherwise causes sub-harmonic problem.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 3, the same as that ofFIG. 1, a flyback power converter includes the transformer12, the power switch M1connected in series with the primary coil Lp of the transformer12, the current sense resistor Rcs connected in series with the power switch M1to produce the current sense signal Vcs derived from the current Ip of the power switch M1, and the controller14to receive a feedback signal through the pin COMP for negative feedback control and provide the control signal GATE to switch the power switch M1to convert the input DC voltage Vin into the output DC voltage Vo. According to the present invention, however, the controller14includes an oscillator20for providing a clock CLK and a ramp signal Vosc synchronous to the clock CLK, an SR flip-flop22for triggering the control signal GATE responsive to the clock CLK, a comparator24for generating a signal S1to reset the SR flip-flop22according to the current sense signal Vcs and a final current limit signal Vclf, and a sub-harmonic eliminate circuit26for detecting the duty ratio of the control signal GATE and changing the final current limit signal Vclf according to the duty ratio of the control signal GATE. When the duty ratio of the control signal GATE is larger than a preset threshold value, the sub-harmonic eliminate circuit26changes the final current limit signal Vclf to prevent the duty ratio of the control signal GATE from acutely changing at the next cycle, thereby eliminating sub-harmonic which otherwise may happen.

The sub-harmonic eliminate circuit26includes a current limit signal controller28, a selector30and two current limit signal generators32and34to provide a ramp current limit signal Vcl1and a constant value current limit signal Vcl2for the selector30to select therebetween under control of the current limit signal controller28. Using a current limit signal generator to generate a ramp current limit signal is a prior art, for example, see U.S. Pat. No. 6,674,656, so the detailed explanation thereof is eliminated herein. The selector30includes a switch SW1connected between the current limit signal generator32and the output terminal Vclf of the sub-harmonic eliminate circuit26, and a switch SW2connected between the current limit signal generator34and the output terminal Vclf of the sub-harmonic eliminate circuit26. The current limit signal controller28detects the duty ratio of the control signal GATE to generate a switch signal CCL for controlling the switches SW1and SW2, and thereby selecting the ramp current limit signal Vcl1or the constant value current limit signal Vcl2as the final current limit signal Vclf.

FIG. 4is a circuit diagram of an embodiment for the current limit signal controller28, which includes a comparator40for comparing the ramp signal Vosc to a reference voltage Vref to generate a signal DX that has a constant duty ratio, an inverter42for inverting the signal DX to generate a signal DX′, a D-type flip-flop44for generating a signal S2according to the control signal GATE applied to its data input terminal D and the signal DX′ applied to its clock terminal clk, and a D-type flip-flop46for generating the switch signal CCL according to the signal S2applied to its data input terminal D and the control signal GATE applied to its clock terminal clk.

FIG. 5is a waveform diagram of the controller14using the circuit ofFIG. 4as the current limit signal controller28, in which waveform50represents the final current limit signal Vclf. The ramp current limit signal Vcl1is preset as the final current limit signal Vclf under normal operation. Referring toFIGS. 3-5, during a cycle T1, the duty ratio of the control signal GATE is larger than a preset threshold value, so when the signal DX turns to low, the control signal GATE still remains at high, as shown at time t5ofFIG. 5, and thus the D-type flip-flop44will remain the signal S2at high. Then, during the next cycle T2, as shown at time t6ofFIG. 5, since the signal S2is high when the control signal GATE turns to high, the D-type flip-flop46will pull the switch signal CCL to high and thus signal the selector30to select the current limit signal Vcl2as the final current limit signal Vclf, as shown by waveform50, which will prevent the on time of the power switch M1from changing acutely, thereby eliminating sub-harmonic which otherwise may happen. Since the duty ratio of the control signal GATE in the cycle T2is no longer larger than the preset threshold value, when the signal DX turns to low, as shown at time t7, the signal S2will also turn to low, and thus, during the next cycle T3, when the control signal GATE turns to high, as shown at time t8, the switch signal CCL will turn to low and thus signal the selector30to select the current limit signal Vcl1again as the final current limit signal Vclf. On the contrary, during the cycle T2, if the duty ratio of the control signal GATE remains larger than the preset threshold value, the selector30will remain the current limit signal Vcl2as the final current limit signal Vclf. In other embodiments, the current limit signal Vcl1may not be limited to have a ramp waveform, and the current limit signal Vcl2may have another waveform instead of a constant value.

Alternatively, when detecting the duty ratio of the control signal GATE larger than the preset threshold value during the cycle T1, the sub-harmonic eliminate circuit26ofFIG. 3may select the current limit signal Vcl2as the final current limit signal Vclf for the next cycle T2, and afterward, no matter whether the duty ratio of the control signal GATE is larger than the preset threshold value during the next cycle T2, the sub-harmonic eliminate circuit26will select the current limit signal Vcl1again as the final current limit signal Vclf for the next cycle T3.

FIG. 6is a circuit diagram of another embodiment for the sub-harmonic eliminate circuit26ofFIG. 3. In addition to the current limit signal controller28, the selector30and the current limit signal generators32and34similar to those in the circuit ofFIG. 3, there is further a current limit signal generator36for providing a constant value current limit signal Vcl3. Besides the switches SW1and SW2, the selector30further has a switch SW3connected between the current limit signal generator36and the output terminal Vclf of the sub-harmonic eliminate circuit26.FIG. 7is a waveform diagram of the circuit shown inFIG. 6, in which waveform52represents the final current limit signal Vclf. Referring toFIGS. 6 and 7, the current limit signal Vcl1is preset as the final current limit signal Vclf under normal operation, and when the current limit signal controller28detects the duty ratio of the control signal GATE not larger than a preset threshold value, it will remain the final current limit signal Vclf=Vcl1. If the current limit signal controller28detects the duty ratio of the control signal GATE larger than the preset threshold value during the cycle T1, the current limit signal controller28will signal the selector30by the switch signal CCL to select the current limit signal Vcl2as the final current limit signal Vclf for the next cycle T2, as shown by waveform52. Then, no matter whether the control signal GATE is larger than the preset threshold value in the cycle T2, the selector30always selects the current limit signal Vcl3as the final current limit signal Vclf for the next cycle T3. Similarly, no matter whether the control signal GATE is larger than the preset threshold value in the cycle T3, the selector30will select the current limit signal Vcl1again as the final current limit signal Vclf for the next cycle. In other embodiments, the current limit signal Vcl1may not be limited to have a ramp waveform, and the other current limit signals Vcl2and Vcl3may have other waveforms instead of constant values.