Semiconductor manufacturing method and semiconductor device

A semiconductor manufacturing method includes forming a first film on an upper surface of a substrate. The semiconductor manufacturing method includes forming concave portions extending from an upper surface of the first film to below the upper surface of the substrate. The method includes forming a second film from bottom surfaces of the concave portions to a first position in the concave portions between the upper surface of the first film and the upper surface of the substrate. The method includes forming a third film in the concave portions to cover side walls of the concave portions and an upper surface of the second film. The method includes grinding the third film to expose the second film. The method includes removing the second film. The method includes forming a fourth film from the bottom surfaces of the concave portions to at least a lower surface of the third film.

FIELD

The embodiments of the present invention relate to a semiconductor manufacturing method and a semiconductor device.

BACKGROUND

In a manufacturing process of a three-dimensional stack memory, a wafer is damaged by etching during formation of memory holes by etching. To provide a satisfactory crystallinity of silicon pillars formed in the memory holes, a film (hereinafter, also “epitaxial film”) being an underlayer for the silicon pillars is formed by epitaxial growth on the wafer damaged by the etching. Because the epitaxial film has a satisfactory crystallinity, the crystallinity of the silicon pillars formed on the epitaxial film can be improved. After the epitaxial film is formed, a charge accumulation layer is formed on the epitaxial film. A conductive layer is then formed using etching. However, the epitaxial film is conventionally damaged by the etching during formation of the conductive layer. This results in a problem that crystallization of the silicon pillars is inhibited and the property of memory cells is degraded.

DETAILED DESCRIPTION

A semiconductor manufacturing method according to an embodiment includes forming a first film on an upper surface of a substrate. The semiconductor manufacturing method includes forming concave portions extending from an upper surface of the first film to below the upper surface of the substrate. The semiconductor manufacturing method includes forming a second film from bottom surfaces of the concave portions to a first position in the concave portions between the upper surface of the first film and the upper surface of the substrate. The semiconductor manufacturing method includes forming a third film in the concave portions to cover side walls of the concave portions and an upper surface of the second film. The semiconductor manufacturing method includes grinding the third film to expose the second film. The semiconductor manufacturing method includes removing the second film. The semiconductor manufacturing method includes forming a fourth film from the bottom surfaces of the concave portions to at least a lower surface of the third film.

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.

First Embodiment

FIG. 1is a schematic sectional view showing a semiconductor device1according to a first embodiment. The semiconductor device1according to the first embodiment is a mode of a three-dimensional stack memory.

The semiconductor device1includes a semiconductor substrate2(that is, a contact layer) being an example of a substrate, a stack film3being an example of a first film, memory strings4, and epitaxial films5being an example of a fourth film.

The stack film3is placed on an upper surface2aof the semiconductor substrate2. The stack film3includes insulating layers31, that is, insulating films and conductive layers32. The insulating layers31and the conductive layers32are stacked alternately and repeatedly. The insulating layers31are, for example, silicon dioxide films. The conductive layers32can include, for example, a tungsten (W) film, a TIN film for growing tungsten, and an AlO film being a block film. The conductive layers32are, for example, word lines. The conductive layers32can include select gate lines.

The memory strings4have a substantially columnar shape extending in a stacking direction d1of the stack film3, that is, in a vertical direction. The memory strings4are embedded in memory holes40being an example of concave portions, respectively. The memory holes40extend from an upper surface3aof the stack film3to below d11the upper surface2aof the semiconductor substrate2. That is, the memory holes40pass through the stack film3to reach an inner portion of the semiconductor substrate2.

Lower surfaces of the memory strings4are connected to the epitaxial films5, that is, source lines. Upper surfaces of the memory strings4are connected to bit lines (not shown).

The memory strings4each include a charge accumulation layer41being an example of a third film, and a silicon pillar42(that is, polysilicon) being an example of a fifth film.

The charge accumulation layer41has a substantially cylindrical shape extending in the stacking direction d1. The charge accumulation layer41covers all around a side wall, that is, an inner circumferential surface of the corresponding memory hole40. The charge accumulation layer41has an ONO structure in which silicon dioxide films411and a silicon nitride film412are placed alternately in a radial direction d2of the memory hole40. The charge accumulation layer41has an amorphous silicon layer413interposed between the charge accumulation layer41and the corresponding silicon pillar42.

The charge accumulation layers41are placed in the memory holes40, respectively, from the upper surface3aof the stack film3to a first position p1between the upper surface3aof the stack film3and the upper surface2aof the semiconductor substrate2. That is, upper surfaces of the charge accumulation layers41are located at a position as high as the upper surface3aof the stack film3and lower surfaces41aof the charge accumulation layers41are located at the first position p1.

The first position p1is a position corresponding to an insulating layer31A placed in a lowermost layer (that is, a lower end in the stacking direction d1) of the stack film3. That is, the position p1of the lower surfaces41aof the charge accumulation layers41is a position between upper and lower surfaces of the insulating film31A in the lowermost layer. When the position p1of the lower surfaces41aof the charge accumulation layers41is thus aligned with the position of the insulating layer31A in the lowermost layer, the charge accumulation layers41can intersect with all the conductive layers32in the stack film3. In this way, all the conductive layers32can be provided with storage areas, that is, unit cells being intersections with the charge accumulation layers41.

The silicon pillar42has a substantially cylindrical shape extending in the stacking direction d1. The silicon pillar42is located on an inner side of the corresponding charge accumulation layer41in the radial direction d2. An insulting layer421is placed on an inner side of the silicon pillar42in the radial direction d2.

A lower surface42aof the silicon pillar42is in contact with an upper surface5aof the corresponding epitaxial film5. More specifically, the silicon pillar42is placed in the corresponding memory hole40to cover a central portion5a_1of the upper surface5aof the epitaxial film5. The silicon pillars42are obtained by annealing amorphous silicon420(seeFIG. 4B) placed on the epitaxial films5for monocrystallization. Because of the monocrystallization on the epitaxial films5, the crystallinity of the silicon pillars42is influenced by the crystallinity of the epitaxial films5. As described below, the crystallinity of the epitaxial films5in the present embodiment is satisfactory and thus the crystallinity of the silicon pillars42is also satisfactory. Because the crystallinity of the silicon pillars42is satisfactory, the property (that is, data storage performance) of the memory cells is also satisfactory.

The epitaxial films5are placed from bottom surfaces40aof the memory holes40to at least the lower surfaces41aof the charge accumulation layers41, that is, the first position p1, respectively. In the example shown inFIG. 1, the upper surfaces5aof the epitaxial films5reach a second position p2above d12the lower surfaces41aof the charge accumulation layers41via through holes410cformed by processing of bottom portions410bof cover films410described later (seeFIGS. 3A and 3B), respectively. In the example shown inFIG. 1, the second position p2is a position corresponding to the conductive layer32being the lowermost one of the conductive layers32.

More specifically, in the upper surface5aof the corresponding epitaxial film5, the central portion5a_1on the inner side of the corresponding charge accumulation layer41in the radial direction d2is located above d12the lower surface41aof the charge accumulation layer41. A peripheral portion5a_2on an outer side of the central portion5a_1in the radial direction d2in the upper surface5aof the epitaxial film5is in contact with the lower surface41aof the charge accumulation layer41. The central portion5a_1can be placed at a position as high as the lower surface41aof the charge accumulation layer41.

The epitaxial films5are, for example, films of a silicon single crystal, that is, semiconductor films. The epitaxial films5bring the semiconductor substrate2and the memory strings4to conduction. The epitaxial films5can be referred to as “contact layers”. Alternatively, the epitaxial films5can be conductor films.

Because the epitaxial films5are formed by a semiconductor manufacturing method describe later, concave portions due to reactive ion etching are not formed in the epitaxial films5. Because the concave portions are not formed therein, the epitaxial films5are not damaged by the reactive ion etching. The epitaxial films5are not damaged and thus have a satisfactory crystallinity. Because the epitaxial films5have a satisfactory crystallinity, the silicon pillars42on the epitaxial films5also have a satisfactory crystallinity.

Therefore, with the semiconductor device1according to the first embodiment, the crystallinity of the silicon pillars42can be improved and thus the device property, that is, the memory cell property can be improved.

A manufacturing method for manufacturing the semiconductor device1shown inFIG. 1is explained next.

FIG. 2Ais a sectional view showing a semiconductor manufacturing method according to the first embodiment. First, the stack film3is formed by alternately stacking the insulating layers31and silicon nitride films320on the semiconductor substrate2as shown inFIG. 2A. The insulating layers31and the silicon nitride films320can be formed, for example, by a CVD (Chemical Vacuum Deposition) method. After the stack film3is formed, the memory holes40extending through the stack film3are formed from the upper surface3aof the stack film3to below d11the upper surface2aof the semiconductor substrate2as shown inFIG. 2A. The memory holes40can be formed, for example, by reactive ion etching.

FIG. 2Bis a sectional view showing a semiconductor manufacturing method followingFIG. 2A. After the memory holes40are formed, carbon films7being an example of a second film are formed from the bottom surfaces40aof the memory holes40to the upper surface3aof the stack film3, respectively, as shown inFIG. 2B. That is, the carbon films7are embedded in the memory holes40, respectively. The carbon films7are films of amorphous carbon. As described later, the carbon films7are removed from the semiconductor substrate2in the course of the manufacturing process of the semiconductor device1. Accordingly, the carbon films7can be referred to as “sacrifice films”. The carbon films7can be formed to above the upper surface3aof the stack film3.

A heatproof temperature of the carbon films7is higher than a process temperature of the cover films410described later. The heatproof temperature of the carbon films7can be, for example, 550° C. or a higher temperature. The carbon films7can be formed, for example, by the CVD method using rare gas and propylene.

FIG. 2Cis a sectional view showing a semiconductor manufacturing method followingFIG. 2B. After the carbon films7are formed, the carbon films7are ground to the first position p1as shown inFIG. 2C. The carbon films7can be, for example, etched back, that is, ground by etching.

FIG. 3Ais a sectional view showing a semiconductor manufacturing method according to the first embodiment followingFIG. 2C. After the carbon films7are ground, the cover films410being an example of the third film are formed in the memory holes40to cover side walls40bof the memory holes40and upper surfaces7aof the carbon films7, respectively, as shown inFIG. 3A.

The cover films410each correspond to a configuration in which the charge accumulation layer41is closed at an opening on a lower end by a same stack film as the charge accumulation layer41. In other words, the cover films410each have a side portion410athat covers the side wall40bof the corresponding memory hole40, and the bottom portion410bthat covers the upper surface7aof the corresponding carbon film7. The cover films410can be formed, for example, by stacking a silicon dioxide film411, a silicon nitride film412, a silicon dioxide film411, and an amorphous silicon layer413in this order by the CVD method.

The cover films410are formed at a temperature lower than the heatproof temperature of the carbon films7. Due to the higher heatproof temperature of the carbon films7than the process temperature of the cover films410, the carbon films7are not lost by heat during formation of the cover films410. Because the carbon films7being underlayers can withstand the process temperature of the cover films410, the cover films410can be formed in appropriate shape and size on the carbon films7, respectively.

FIG. 3Bis a sectional view showing a semiconductor manufacturing method followingFIG. 3A. After the cover films410are formed, the cover films410are ground to expose the carbon films7in the memory holes40, respectively, as shown inFIG. 3B. That is, the through holes410cpassing through the bottom portions410bof the cover films410are formed at central parts of the bottom portions410b. The grinding of the cover films410forms the charge accumulation layers41. Furthermore, due to exposure of the carbon films7, the carbon films7can be exposed to an atmosphere for ashing to remove the carbon films7. During the grinding of the cover films410, the carbon films7can also be ground to some extent. The cover films410can be ground, for example, by reactive ion etching. The cover films410can be ground by etching using gas including fluorine and oxygen.

FIG. 3Cis a sectional view showing a semiconductor manufacturing method followingFIG. 3B. After the cover films410are ground, the carbon films7are removed as shown inFIG. 3C. The carbon films7can be removed, for example, by ashing. When plasma ashing is performed, oxygen gas having been turned into plasma is supplied to the carbon films7exposed through the cover films410to convert the carbon films7into carbon dioxide and water vapor by a reaction with the oxygen gas. In this way, the carbon films7can be removed.

FIG. 4Ais a sectional view showing a semiconductor manufacturing method according to the first embodiment followingFIG. 3C. After the carbon films7are removed, the epitaxial films5are epitaxially grown from the bottom surfaces40aof the memory holes40to the second position p2above d12the lower surfaces41aof the charge accumulation layers41, respectively, as shown inFIG. 4A.

The epitaxial films5are formed in regions in which the charge accumulation layers41are not formed in the memory holes40having substantially-uniform inner diameters, respectively. Meanwhile, the silicon pillars42are formed on the epitaxial films5on the inner side of the charge accumulation layers41in the memory holes40, respectively. Therefore, the outermost diameter of the epitaxial films5is larger than the outer diameter of the silicon pillars42. If the upper surfaces5aof the epitaxial films5are located below d11the lower surfaces41aof the charge accumulation layers41, lower end portions of the silicon pillars42are formed in voids in which the side walls of the charge accumulation layers41are not provided. In this case, control on the outer diameter of the silicon pillars42at the lower end portions becomes difficult and it is difficult to obtain a stable memory cell property. In contrast thereto, in the present embodiment, because the upper surfaces5aof the epitaxial films5can be located above d12the lower surfaces41aof the charge accumulation layers41, the outer diameter of the silicon pillars42can be appropriately controlled by the inner diameter of the charge accumulation layers41.

FIG. 4Bis a sectional view showing a semiconductor manufacturing method followingFIG. 4A. After the epitaxial films5are formed, amorphous silicon420is formed in the memory holes40to be in contact with the upper surfaces5aof the epitaxial films5as shown inFIG. 4B. The amorphous silicon420can be formed, for example, by the CVD method.

FIG. 4Cis a sectional view showing a semiconductor manufacturing method followingFIG. 4B. After the amorphous silicon420is formed, the amorphous silicon420is monocrystallized to form the silicon pillars42as shown inFIG. 4C. The amorphous silicon420can be monocrystallized, for example, by annealing. After the silicon pillars42are formed, the insulating layers421are embedded in inner portions of the silicon pillars42, respectively.

Furthermore, as shown inFIG. 4C, the silicon nitride films320are replaced with the conductive layers32, respectively. Replacement with the conductive layers32can be achieved, for example, by removing the silicon nitride films320by wet etching using a heated phosphoric acid solution and then forming the conductive layers32by the CVD method in voids formed by the removal of the silicon nitride films320.

If the epitaxial films5are formed before the charge accumulation layers41are formed, the charge accumulation layers41are formed using the epitaxial films5as underlayers. In this case, when the cover films410are ground to form the charge accumulation layers41, the epitaxial films5under the cover films410are also ground. Due to being ground, the epitaxial films5are damaged and the crystallinity is disturbed. The disturbed crystallinity of the epitaxial films5inhibits crystallization of the amorphous silicon420formed on the epitaxial films5. Due to the inhibition of the crystallization of the amorphous silicon420, the crystallinity of the silicon pillars42based on the amorphous silicon420is degraded. Accordingly, the memory cell property is degraded.

In contrast thereto, in the first embodiment, after the charge accumulation layers41are formed using the carbon films7instead of the epitaxial films5as the underlayers, the carbon films7are replaced with the epitaxial films5, respectively. Because the carbon films7are removed, the device property is not affected even when the carbon films7are ground together with the cover films410during formation of the charge accumulation layers41. Furthermore, because the charge accumulation layers41are already formed at the time of formation of the epitaxial films5, the epitaxial films5are not damaged by formation of the charge accumulation layers41and the crystallinity is not disturbed.

Therefore, according to the first embodiment, damages of the epitaxial films5can be avoided. This can improve the crystallinity of the silicon pillars42and can improve the memory cell property.

Second Embodiment

The semiconductor device1having contacts on the epitaxial films5, respectively, is explained next as a second embodiment. In the second embodiment, constituent parts corresponding to those in the first embodiment are denoted by like reference characters and explanations thereof will be omitted.FIG. 5is a schematic sectional view showing the semiconductor device1according to the second embodiment.

As shown inFIG. 5, the semiconductor device1according to the second embodiment includes the semiconductor substrate2, an insulating film300being an example of the first film, spacer films403being an example of the third film, contacts400(that is, wiring parts) being an example of the fifth film, and the epitaxial films5. The semiconductor device1also includes contact holes401being an example of the concave portions.

The insulating film300is placed on the upper surface2aof the semiconductor substrate2. The insulating film300can be, for example, a silicon dioxide film.

The contact holes401extend in a thickness direction d10of the insulating film300, that is, in a vertical direction. Specifically, the contact holes401are located from an upper surface300aof the insulating film300to below d11the upper surface2aof the semiconductor substrate2. That is, the contact holes401pass through the insulating film300to reach an inner portion of the semiconductor substrate2.

The spacer films403are placed in the contact holes401, for example, for the purpose of causing the outer diameter of the contacts400to be smaller than the inner diameter of the contact holes401by a desired size, respectively. The spacer films403can be, for example, an insulating film such as a silicon dioxide film.

The spacer films403have a substantially cylindrical shape extending in the thickness direction d10of the insulating film300.

The spacer films403are placed in the contact holes401from the upper surface300aof the insulating film300to the first position p1between the upper surface300aof the insulating film300and the upper surface2aof the semiconductor substrate2.

The spacer films403are formed in the substantially cylindrical shape to cover all around side walls of the contacts400, respectively.

The contacts40have a substantially columnar shape extending in the thickness direction d10of the insulating film300. The contacts400are embedded in the contact holes401with the spacer films403interposed therebetween, respectively.

Lower surfaces400aof the contacts400are in contact with the upper surfaces5aof the epitaxial films5, respectively. More specifically, the contacts400are placed in the contact holes401to cover the central portions5a_1of the upper surfaces5aof the epitaxial films5, respectively. Upper surfaces of the contacts400are connected to upper lines (not shown).

The contacts400are obtained by annealing the amorphous silicon420(seeFIG. 8B) placed on the epitaxial films5for monocrystallization.

The epitaxial films5are placed from bottom surfaces401aof the contact holes401to at least lower surfaces403aof the spacer films403, that is, to the first position p1. In the example shown inFIG. 5, the upper surfaces5aof the epitaxial films5reach the second position p2above d12the lower surfaces403aof the spacer films403via through holes403dformed by processing of bottom portions403cof the spacer films403described later (seeFIGS. 7A and 7B).

More specifically, the central portions5a_1on an inner side of the spacer films403in the radial direction d2in the upper surfaces5aof the epitaxial films5are placed above d12the lower surfaces403aof the spacer films403. The peripheral portions5a_2in the upper surfaces5aof the epitaxial films5are in contact with the lower surfaces403aof the spacer films403. The central portions5a_1can be placed at a position as high as the lower surfaces403aof the spacer films403.

Similarly to the first embodiment, concave portions due to reactive ion etching are not formed in the epitaxial films5. Because no concave portions are formed, the epitaxial films5are not damaged by the reactive ion etching and have a satisfactory crystallinity. Due to a satisfactory crystallinity of the epitaxial films5, the contacts400on the epitaxial films5also have a satisfactory crystallinity.

Therefore, with the semiconductor device1according to the second embodiment, the crystallinity of the contacts400can be improved and thus the device property can be improved.

A manufacturing method for manufacturing the semiconductor device1shown inFIG. 5is explained next.

FIG. 6Ais a sectional view showing a semiconductor manufacturing method according to the second embodiment. First, the insulating film300is formed on the semiconductor substrate2as shown inFIG. 6A. The insulating film300can be formed, for example, by the CVD method. After the insulating film300is formed, the contact holes401extending through the insulting film300are formed from the upper surface300aof the insulating film300to below d11the upper surface2aof the semiconductor substrate2as shown inFIG. 6A. The contact holes401can be formed, for example, by reactive ion etching.

FIG. 6Bis a sectional view showing a semiconductor manufacturing method followingFIG. 6A. After the contact holes401are formed, the carbon films7are formed from the bottom surfaces401aof the contact holes401to the upper surface300aof the insulating film300, respectively, as shown inFIG. 6B.

FIG. 6Cis a sectional view showing a semiconductor manufacturing method followingFIG. 6B. After the carbon films7are formed, the carbon films7are ground to the first position p1as shown inFIG. 6C.

FIG. 7Ais a sectional view showing a semiconductor manufacturing method according to the second embodiment followingFIG. 6C. After the carbon films7are ground, the spacer films403being an example of the third film are formed in the contact holes401to cover side walls401bof the contact holes401and the upper surfaces7aof the carbon films7, respectively, as shown inFIG. 7A. The spacer films403each have a side portion403bcovering the side wall401bof the corresponding contact hole401and a bottom portion403ccovering the upper surface7aof the corresponding carbon film7. The spacer films403are formed, for example, by the CVD method at a temperature lower than the heatproof temperature of the carbon films7. Due to the higher heatproof temperature of the carbon films7than the process temperature of the spacer films403, the carbon films7are not lost during formation of the spacer films403. Because the carbon films7as the underlayers can withstand the process temperature of the spacer films403, the spacer films403can be formed in appropriate shape and size on the carbon films7, respectively.

FIG. 7Bis a sectional view showing a semiconductor manufacturing method followingFIG. 7A. After the spacer films403are formed, the spacer films403are ground to expose the carbon films7in the corresponding contact holes401, respectively, as shown inFIG. 7B. That is, central parts of the bottom portions403cof the spacer films403are removed. When the spacer films403are ground, the carbon films7can also be ground. The spacer films403can be ground, for example, by reactive ion etching.

FIG. 7Cis a sectional view showing a semiconductor manufacturing method followingFIG. 7B. After the spacer films403are ground, the carbon films7are removed as shown inFIG. 7C. The carbon films7can be removed, for example, by ashing.

FIG. 8Ais a sectional view showing a semiconductor manufacturing method according to the second embodiment followingFIG. 7C. After the carbon films7are removed, the epitaxial films5are epitaxially grown from the bottom surfaces401aof the contact holes401to the second position p2above d12the lower surfaces403aof the spacer films403, respectively, as shown inFIG. 8A.

FIG. 8Bis a sectional view showing a semiconductor manufacturing method followingFIG. 8A. After the epitaxial films5are formed, the amorphous silicon420(the fifth film) is formed in the contact holes401to be in contact with the upper surfaces5aof the epitaxial films5as shown inFIG. 8B. The amorphous silicon420can be formed, for example, by the CVD method.

FIG. 8Cis a sectional view showing a semiconductor manufacturing method followingFIG. 8B. After the amorphous silicon420is formed, the amorphous silicon420is monocrystallized to form the contacts400as shown inFIG. 8C. The amorphous silicon420can be monocrystallized, for example, by annealing.

If the epitaxial films5are formed before the spacer films403are formed, the spacer films403are formed using the epitaxial films5as the underlayers. In this case, at the time of grinding of the spacer films403, the epitaxial films5under the spacer films403are also ground. Due to being ground, the epitaxial films5are damaged and the crystallinity is disturbed. The disturbed crystallinity of the epitaxial films5inhibits crystallization of the amorphous silicon420formed on the epitaxial films5. Due to inhibition of the crystallization of the amorphous silicon420, the crystallinity of the contacts40based on the amorphous silicon420is degraded. Accordingly, the device property is degraded.

In contrast thereto, in the second embodiment, after the spacer films403are formed using the carbon films7instead of the epitaxial films5as the underlayers, the carbon films7are replaced with the epitaxial films5, respectively. Because the carbon films7are removed, the device property is not affected even when the carbon films7are ground together with the spacer films403during grinding of the spacer films403. Furthermore, because the spacer films403are already ground when the epitaxial films5are formed, the epitaxial films5are not damaged by processing of the spacer films403and the crystallinity is not disturbed.

Therefore, also in the second embodiment, damages of the epitaxial films5can be avoided. This can improve the crystallinity of the contacts400and improve the device property.

The conductive layers32described in the first embodiment extend in a word line direction (the direction d2inFIG. 1, for example) to outside a cell region. Ends of the conductive layers32in the extension direction are closer to the cell region as the conductive layers32are located in upper layers. Therefore, in the outside the cell region, the conductive layers32form a stepped shape as a whole. The present embodiment can also be applied to connect the conductive layers32in the stepped shape to upper lines with contacts. In this case, the present embodiment can be applied regarding the conductive layers32as substrates.