ENHANCED EYE-WIDTH MARGIN USING DUTY CYCLE ADJUST

A high-speed data communication interface includes first and second lanes. The first lane includes a first transmitter coupled to send a first data signal to a first receiver via a first channel. The second lane includes a second transmitter coupled to send a second data signal to a second receiver via a second channel. The first channel injects crosstalk into the second channel. The second transmitter sets a duty cycle adjuster input to adjust a duty cycle of the second data signal to reduce the crosstalk.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems and more particularly relates to providing enhanced eye width margins using Duty Cycle Adjust in a high-speed data communication interface.

BACKGROUND

SUMMARY

A high-speed data communication interface may include first and second lanes. The first lane may include a first transmitter coupled to send a first data signal to a first receiver via a first channel. The second lane may include a second transmitter coupled to send a second data signal to a second receiver via a second channel. The first channel may inject crosstalk into the second channel. The second transmitter may set a duty cycle adjuster input to adjust a duty cycle of the second data signal to reduce the crosstalk.

DETAILED DESCRIPTION OF DRAWINGS

FIG.1illustrates a high-speed data communication interface100, such as may be found in information handling system300inFIG.3, as described below. High-speed data communication interface100includes a data transmitting component110, a data receiving component120, and a management engine130. Data transmitting component110(hereinafter “transmitter110”) operates to transmit data via a channel to and the data is received by data receiving component120(hereinafter “receiver120”). The channel may be a single-ended data communication interface, as here illustrated, where the data signals are provided over a single conductor and the data values are provided with reference to a common reference voltage, typically a ground level, or the channel may be a double-ended data communication interface where the data signals are provided as differential signals over a pair of conductors, as needed or desired. High-speed data communication interface100represents a high-speed serializer/deserializer, in that transmitter110receives data and transmits the received data in a serialized fashion, and in that receiver120receives the serialized data from the transmitter and deserializes the data to extract the original data.

Examples of a high-speed data communication interface include a memory interface, such as a Double-Data Rate (DDR) interface, a Small Form Factor Pluggable (SFP+) interface for network communications, a Serial-ATA interface, a DisplayPort interface, a PCIe interface, a proprietary high-speed data communication interface, or the like. A typical high-speed data communication interface will include elements for bi-directional data communications. Thus, in a first case, a channel between a transmitter and a receiver may be utilized for bi-directional data transfers (for example DDR interfaces). Here, the typical transmitter component may include receive components as described herein that are coupled to the channel, and the typical receiver component may include transmit components as described herein that are coupled to the channel. In another case, a separate channel may be utilized for data transmission from the receiver component to the transmitter component (for example PCIe interfaces). A typical information handling system will include multiple high-speed data communication interfaces combined to form a larger group of related high-speed data communication interfaces. Here, a single high-speed data communication interface may be referred to as a lane, and the group of high-speed data communication interfaces may be referred to as a link or a bus. The details of high-speed data communication interfaces are known in the art and will not be further described herein, except as needed to illustrate the current embodiments.

Transmitter110includes a physical layer transmitter112(hereinafter “transmit PHY112”), and a Built-In Self Test (BIST) module. In a normal data transmission operating mode, transmit PHY112receives data, and converts the received data into electrical signals on the channel to receiver120. Transmit PHY112includes a Duty Cycle Adjuster (DCA) input. In some cases, such as in parallel bus type high-speed data communication interfaces, like DDR data communication interfaces, the data conversion may include a bit-by-bit translation of the received data bits into associated signals on the channel. In other cases, such as serial type high-speed data communication interfaces, like PCIe data communication interfaces, the data conversion may include an encoding step, such as an 8-bit/10-bit encoding, to ensure adequate state changes are received in the receiver for clock recovery or the like. The operation of BIST module114will be described further below.

The DCA input to transmit PHY112operates to change the duty cycle of the output signal. For example, a pair of signals on adjacent lanes of a high-speed data communication interface such are illustrated140and142. Here, in a nominal case140, both the victim lane and the aggressor lane are set with nominal DCA settings, that is, with no changes to the duty cycle of the signals on the associated lanes. Here, it can be seen that transitions in the signal value from a logic “0” to a logic “1,” or from a logic “1” to a logic “0,” are aligned in time between the victim lane and the aggressor lane. Also, the time each signal remains in the logic “0” state and the time each signal remains in the logic “1” state are equal (T) and the period of the signal (2T) is provided as:

In a DCA case142, the aggressor lane retains the nominal DCA setting, with no change to the duty cycle of the aggressor lane. Here, the time the aggressor signal remains in the logic “0” state and the time aggressor signal remains in the logic “1” state are equal (T) and the period of the signal (2T) is provided as defined in Equation 1, above. However, the victim lane has a DCA setting that offsets the transitions from the logic “0” to the logic “1,” and from the logic “1” to the logic “0.” In particular, the time the victim signal remains in the logic “0” state is increased (T+) and the time the victim signal remains in the logic “1” state is decreased (T−), while the period (2T) of the signal remains constant, as:

Note that the use of the DCA input to transmit PHY112may operate in an opposite sense as described above, with the time the victim signal remains in the logic “0” state being decreased (T) and the time the victim signal remains in the logic “1” state is increased (T+), as needed or desired.

Receiver120includes a physical layer receiver122(hereinafter “receive PHY122”), an equalization module124, a data sampler/demultiplexor126, and an eye sampler/demultiplexor128. In the normal operating mode, receive PHY122receives the electrical signals from the channel. It will be understood that in a typical high-speed data communication interface, the data stream as provided to transmit PHY112is not simply “read” from an output of receive PHY122. This is because the margins for voltage levels and the time duration of the received signals are so small that the distortion effects from the channel result in a received signal that is typically unrecognizable as data without significant post-processing to recover the data stream. As such, the output from receive PHY122is provided to equalization module124for processing, and the output of equalization module is provided to data sampler/demultiplexor126before the data stream is recovered.

Equalization module124operates to clean up the received signal from receive PHY122by compensating for the distortion effects from the channel. For example, equalization module124may include an automatic gain control (AGC) module, a continuous-time linear equalization (CTLE) module, and decision feedback (DFE) module, or other equalization modules as needed or desired. An AGC module is a feedback amplifier that operates to amplify the received signal from a transmitter to provide a constant level signal to the rest of the elements of the receiver. A CTLE module is a linear fitter that attenuates low-frequency components of the signal received from an AGC module that amplifies components of the signal around the Nyquist frequency of the signal, and fitters off high-frequency components of the signal. A DFE module is a non-linear equalization which relies on decisions about the levels of previous symbols (high/low) in the signal received from the transmitter in order to clean up a current symbol, thereby accounting for distortion in the current symbol that is caused by the previous symbols. The details of channel equalization, and in particular of AGC, CTLE, and DFE equalizations are known in the art and will not be further described herein, except as needed to illustrate the current embodiments. The result of the processing by equalization module124is to present a clean data eye to data sampler/demultiplexor126which extracts the data stream from the data eye for use by other elements of receiver120as needed or desired. The details of data recovery in a receiver of a high-speed data communication interface are known in the art and will not be further described herein, except as needed to illustrate the current embodiments.

Eye sampler/demultiplexor128is similar to data sampler/demultiplexor126, and receives the data eye. Here, the data eye represents a flow of data bits on the channel that can be depicted an instrument trace of multiple data bits from the data stream. As such, data sampler/demultiplexor126is focused upon extracting the individual data bits from the data stream, while eye sampler/demultiplexor128is focused on the issues of the quality of the data eye, and particularly on determining the eye height and eye width of the data eye to ensure that sufficient margins are maintained as a result of the equalization process performed by equalization module124.

In various embodiments, eye sampler/demultiplexor128operates in a training mode to provide feedback as to the sufficiency and consistency of the settings of the various stages of the equalization blocks in maintaining adequate margins in the data eye to improve the ability of data sampler/demultiplexor130to detect the data stream and to reduce the bit error rate of the detection process. In other embodiments, eye sampler/demultiplexor132operates in a run time mode to detect changes in the data eye and to proactively notify of the changes, or to amend the settings of the various stages of equalization blocks to maintain the bit error rate within satisfactory levels.

In a particular embodiment, in the training mode, eye sampler/demultiplexor128coordinates link training with transmitter110. Here, management engine130operates to communicate training results from eye sampler/demultiplexor128to BIST module114to determine when the settings of the various stages of equalization module124have converged on a satisfactory set of values to create the adequate margins in the data eye. Here, during a power-on phase, BIST module114operates to transmit training data via transmit PHY112and eye sampler/demultiplexor128, upon detecting an unsatisfactory data eye, systematically adjusts the settings within equalization module124, until the detected eye exhibits the adequate margin to ensure that the bit error rate remains below a predetermined level. In another embodiment, the training is repeatedly performed. Here, it is understood that the same or similar settings for equalization module124will be expected, and eye sampler/multiplexor132selects as a final set of setting values the setting values that represent a best set of setting values. The best set of setting values can be determined as a most commonly reoccurring value for each setting, as an average of the values over the repeated training runs, as the value for each setting that exhibited the best eye margins, or other methods for analyzing the values of the repeated training runs.

It has been understood by the inventors of the current disclosure that crosstalk between lanes of a high-speed data communication interface can have a significant negative impact on the eye width margins of the data eye at a receiver. In particular, in DDR type memory interfaces, such as a fifth generation (DDR5) interface, the individual lanes are typically tightly routed so as to have all signals arrive at the receiver at the same time. However, such tight routing creates an enhanced environment for crosstalk between the lanes. Crosstalk is traditionally handled by spacing the lanes further apart, but such an approach results in less efficient utilization of PCB real estate, and the consequent increase in the number of PCB layers needed to accommodate DDR channels (e.g. from 8-layer PCBs to 12-layer PCBs).

In a particular embodiment, as illustrated in the DCA case142, the DCA input to transmit PHY112is adjusted to intentionally misalign the signal transition edges of a victim lane that is experiencing poor eye width margins. In this way, the cumulative effect of switching transients from neighboring aggressor lanes on the victim lane are not added in with the switching transients of the victim lane, thereby improving the eye width margin of the victim lane. For example, the JEDEC specification for DDR5 interfaces includes a specified DCA input to a transmit PHY. By utilizing this input in DDR5 interfaces on a victim lane that experiences poor eye width margin, the eye width margin for the victim lane may be significantly improved. In a particular embodiment, the eye width margin of a victim lane can be improved up to 25% over normally aligned signaling.

FIG.2illustrates a method200for providing enhanced eye width margins using DCA in a high-speed data communication interface, starting at block202. Link training is initiated in block204. The details of link training are highly dependent upon the type of high-speed data communication interface that is being trained and known in the art, and will not be further described herein except as may be needed to illustrate the current embodiments. The eye height and eye width margins for each lane in the high-speed data communication interface are determined and the equalization settings are locked in block206. Based upon the eye width margins for each lane, a weakest lane, in terms of eye width, is determined in block208. The DCA settings for the adjacent lanes (the aggressor lanes) to the weakest lane are set to manipulate the aggressor lanes to incrementally adjust their duty cycles in block210.

A decision is made as to whether or not the eye width margin for the victim lane has increased in decision block212. If not, the “NO” branch of decision block212is taken and the DCA settings for the aggressor lanes are incrementally adjusted again in block214. A decision is made as to whether or not the DCA settings for the aggressor lanes are at a maximum value in decision block216. If not, the “NO” branch of decision block216is taken and the method returns to decision block212where the decision is made as to whether or not the modified DCA settings have increased the eye width margin of the victim lane. If the DCA settings for the aggressor lanes are at a maximum value, the “YES” branch of decision block216is taken, the link training is ended in block224, and the method ends in block226.

Returning to decision block212, if the eye width margin for the victim lane has increased, the “YES” branch of the decision block is taken, and a next weakest victim lane is selected in block218. A decision is made as to whether or not the new victim lane has a weaker margin that the adjusted (original) victim lane in decision block220. If so, the “YES” branch of decision block220is taken and the method proceeds to block210, where the DCA settings for the adjacent lanes (the aggressor lanes) to the next weakest lane are set to manipulate the aggressor lanes to incrementally adjust their duty cycles. If the new victim lane does not have a weaker margin that the adjusted (original) victim lane, the “NO” branch of decision block220is taken and the DCA values for all lanes are locked in block222. The link training is ended in block224, and the method ends in block226.

Information handling system300can include devices or modules that embody one or more of the devices or modules described below, and operates to perform one or more of the methods described below. Information handling system300includes a processors302and304, an input/output (I/O) interface310, memories320and325, a graphics interface330, a basic input and output system/universal extensible firmware interface (BIOS/UEFI) module340, a disk controller350, a hard disk drive (HDD)354, an optical disk drive (ODD)356, a disk emulator360connected to an external solid state drive (SSD)362, an I/O bridge370, one or more add-on resources374, a trusted platform module (TPM)376, a network interface380, a management device390, and a power supply395. Processors302and304, I/O interface310, memory320, graphics interface330, BIOS/UEFI module340, disk controller350, HDD354, ODD356, disk emulator360, SSD362, I/O bridge370, add-on resources374, TPM376, and network interface380operate together to provide a host environment of information handling system300that operates to provide the data processing functionality of the information handling system. The host environment operates to execute machine-executable code, including platform BIOS/UEFI code, device firmware, operating system code, applications, programs, and the like, to perform the data processing tasks associated with information handling system300.

In the host environment, processor302is connected to I/O interface310via processor interface306, and processor304is connected to the I/O interface via processor interface308. Memory320is connected to processor302via a memory interface322. Memory325is connected to processor304via a memory interface327. Graphics interface330is connected to I/O interface310via a graphics interface332, and provides a video display output336to a video display334. In a particular embodiment, information handling system300includes separate memories that are dedicated to each of processors302and304via separate memory interfaces. An example of memories320and330include random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/UEFI module340, disk controller350, and I/O bridge370are connected to I/O interface310via an I/O channel312. An example of I/O channel312includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. I/O interface310can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/UEFI module340includes BIOS/UEFI code operable to detect resources within information handling system300, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/UEFI module340includes code that operates to detect resources within information handling system300, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller350includes a disk interface352that connects the disk controller to HDD354, to ODD356, and to disk emulator360. An example of disk interface352includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator360permits SSD364to be connected to information handling system300via an external interface362. An example of external interface362includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive364can be disposed within information handling system300.

I/O bridge370includes a peripheral interface372that connects the I/O bridge to add-on resource374, to TPM376, and to network interface380. Peripheral interface372can be the same type of interface as I/O channel312, or can be a different type of interface. As such, I/O bridge370extends the capacity of I/O channel312when peripheral interface372and the I/O channel are of the same type, and the I/O bridge translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel372when they are of a different type. Add-on resource374can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource374can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system300, a device that is external to the information handling system, or a combination thereof.

Network interface380represents a NIC disposed within information handling system300, on a main circuit board of the information handling system, integrated onto another component such as I/O interface310, in another suitable location, or a combination thereof. Network interface device380includes network channels382and384that provide interfaces to devices that are external to information handling system300. In a particular embodiment, network channels382and384are of a different type than peripheral channel372and network interface380translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels382and384includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels382and384can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

Management device390represents one or more processing devices, such as a dedicated baseboard management controller (BMC) System-on-a-Chip (SoC) device, one or more associated memory devices, one or more network interface devices, a complex programmable logic device (CPLD), and the like, that operate together to provide the management environment for information handling system300. In particular, management device390is connected to various components of the host environment via various internal communication interfaces, such as a Low Pin Count (LPC) interface, an Inter-Integrated-Circuit (I2C) interface, a PCIe interface, or the like, to provide an out-of-band (00B) mechanism to retrieve information related to the operation of the host environment, to provide BIOS/UEFI or system firmware updates, to manage non-processing components of information handling system300, such as system cooling fans and power supplies. Management device390can include a network connection to an external management system, and the management device can communicate with the management system to report status information for information handling system300, to receive BIOS/UEFI or system firmware updates, or to perform other task for managing and controlling the operation of information handling system300. Management device390can operate off of a separate power plane from the components of the host environment so that the management device receives power to manage information handling system300when the information handling system is otherwise shut down. An example of management device390include a commercially available BMC product or other device that operates in accordance with an Intelligent Platform Management Initiative (IPMI) specification, a Web Services Management (WSMan) interface, a Redfish Application Programming Interface (API), another Distributed Management Task Force (DMTF), or other management standard, and can include an Integrated Dell Remote Access Controller (iDRAC), an Embedded Controller (EC), or the like. Management device390may further include associated memory devices, logic devices, security devices, or the like, as needed or desired.