Manufacture method of low temperature poly-silicon array substrate

The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

FIELD OF THE INVENTION

The present invention relates to a display panel technology field, and more particularly to a manufacture method of Low Temperature Poly-silicon array substrate.

BACKGROUND OF THE INVENTION

With the development of display technology, the flat panel device, such as Liquid Crystal Display (LCD) possesses advantages of high image quality, power saving, thin body and wide application scope. Thus, it has been widely applied in various consumer electrical products, such as mobile phone, television, personal digital assistant, digital camera, notebook, laptop, and becomes the major display device.

Most of the liquid crystal displays on the present market are back light type liquid crystal displays, which comprise a liquid crystal display panel and a back light module. The working principle of the liquid crystal display panel is to locate liquid crystal molecules between two parallel glass substrates, and a plurality of vertical and horizontal tiny electrical wires are between the two glass substrates. The light of back light module is reflected to generate images by applying driving voltages to control whether the liquid crystal molecules to be changed directions.

Generally, the liquid crystal display panel comprises a CF (Color Filter) substrate, a TFT (Thin Film Transistor) substrate, LC (Liquid Crystal) sandwiched between the CF substrate and TFT substrate and sealant. The formation process generally comprises: a forepart Array process (thin film, photo, etching and stripping), a middle Cell process (Lamination of the TFT substrate and the CF substrate) and a post module assembly process (Attachment of the driving IC and the printed circuit board). The forepart Array process is mainly to form the TFT substrate for controlling the movement of the liquid crystal molecules; the middle Cell process is mainly to add liquid crystal between the TFT substrate and the CF substrate; the post module assembly process is mainly the driving IC attachment and the integration of the printed circuit board. Thus, the liquid crystal molecules are driven to rotate and display pictures.

Low Temperature Poly Silicon (LTPS) is a kind of liquid crystal display technology which has been widely applied in the small, medium size electronic products. The electron mobility of the traditional amorphous silicon material is about 0.5-1.0 cm2/V·S but the electron mobility of the Low Temperature Poly Silicon can reach up to 30-300 cm2/V·S. Therefore, the Low Temperature Poly Silicon display has many advantages of high resolution, fast response speed and high aperture ratio.

However, on the other hand, the volume of the LTPS semiconductor element is small and the integration is high. The manufacture process of the entire LTPS array substrate is complicated, and the production cost is higher.

In the present manufacture process of the LTPS array substrate, the patterning of the polysilicon (Poly-si), the channel doping of the NMOS (Negative channel Metal Oxide Semiconductor) element and the N type heavy doping of the NMOS element (N+doping) respectively needs a mask, and the specific steps are:

as shown inFIG. 1, coating a photoresist layer200on the polysilicon layer, and after employing a first mask to implement exposure, development to the photoresist layer200, and the remaining photoresist layer200is employed for shielding to etch the polysilicon layer to obtain a first polysilicon section300in the NMOS region and a second polysilicon section400in the PMOS (Positive channel Metal Oxide Semiconductor) region;

as shown inFIG. 2, coating a photoresist layer500on the on the first polysilicon section300and the second polysilicon section400, and after employing a second mask to implement exposure, development to the photoresist layer500, the second polysilicon section400of the PMOS region is shielded with the remaining photoresist layer500, and implementing channel doping to the first polysilicon section300;

as shown inFIG. 3, coating a photoresist layer600on the first polysilicon section300and the second polysilicon section400, and after employing a second mask to implement exposure, development to the photoresist layer600, the second polysilicon section400of the PMOS region and the middle region of the first polysilicon section300of the NMOS region are shielded with the remaining photoresist layer600, and implementing N type heavy doping to two ends of the first polysilicon section300.

The aforesaid manufacture processes require three masks for accomplishment. The process is complicated, and the production cost is high. Therefore, there is a need to provide a manufacture method of a Low Temperature Poly-silicon array substrate to solve the technical issue.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced.

For realizing the aforesaid objectives, the present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:

step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;

step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;

step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;

employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region;

employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer of the first photoresist layer and the second photoresist layer thinner; employing remained thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions.

the method further comprises steps of:

step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively;

employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section;

step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section;

step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer;

step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via;

step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain;

step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;

step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer;

step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via.

In the step 2, the low temperature crystallization process is Excimer Laser Annealing or Metal-Induced Lateral Crystallization.

In the step 2, a specific operation of channel doping is: coating a photoresist layer on the polysilicon layer, and employing a mask to implement exposure, development to the photoresist layer, and after removing the photoresist layer in the NMOS region, implementing P type light doping to the polysilicon layer in the entire NMOS region.

In the step 6, rapid thermal annealing is employed to implement the dehydrogenation and activation treatments to the interlayer insulation layer.

The substrate is a glass substrate; material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the buffer layer, the gate isolation layer, the interlayer insulation layer and the passivation protective layer are Silicon Oxide layers, Silicon Nitride layers or composite layers superimposed with Silicon Oxide layers and Silicon Nitride layers; the flat layer is organic photoresist material.

Material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is metal oxide.

The metal oxide is Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide or Indium Germanium Zinc Oxide.

The ion doped by the N type heavy doping and the N type light doping is phosphorus ion or arsenic ion.

The ion doped by the P type heavy doping and the P type light doping is boron ion or gallium ion.

The present invention further provides a manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:

step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;

step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;

step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;

employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region;

employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer of the first photoresist layer and the second photoresist layer thinner; employing remained thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions;

the method further comprises steps of:

step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively;

employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section;

step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section;

step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer;

step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via;

step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain;

step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;

step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer;

step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via;

wherein in the step 2, the low temperature crystallization process is Excimer Laser Annealing or Metal-Induced Lateral Crystallization;

wherein in the step 2, a specific operation of channel doping is: coating a photoresist layer on the polysilicon layer, and employing a mask to implement exposure, development to the photoresist layer, and after removing the photoresist layer in the NMOS region, implementing P type light doping to the polysilicon layer in the entire NMOS region.

The benefits of the present invention are: the present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

In order to better understand the characteristics and technical aspect of the invention, please refer to the following detailed description of the present invention is concerned with the diagrams, however, provide reference to the accompanying drawings and description only and is not intended to be limiting of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Please refer toFIGS. 4-14, the present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:

step 1, as shown inFIG. 4, providing a substrate10, and defining a NMOS region and a PMOS region on the substrate10, and depositing a first metal layer on the substrate10, and patterning the first metal layer to obtain a first light shielding layer21in the NMOS region and a second light shielding layer22in the PMOS region.

step 2, as shown inFIG. 5, forming a buffer layer30on the first light shielding layer21, the second light shielding layer22and the substrate10, and depositing an amorphous silicon layer on the buffer layer30, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer31, and employing a mask to implement a channel doping to the polysilicon layer31in the NMOS region.

The low temperature crystallization process is Excimer Laser Annealing (ELA) or Metal-Induced Lateral Crystallization (MILC).

Specifically, a specific operation of channel doping is: coating a photoresist layer32on the polysilicon layer31, and employing a mask to implement exposure, development to the photoresist layer32, and after removing the photoresist layer32in the NMOS region, implementing P type light doping to the polysilicon layer31in the entire NMOS region.

step 3, as shown inFIG. 6A, coating a photoresist layer on the polysilicon layer31, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer33in the NMOS region and a second photoresist layer34in the PMOS region are obtained, and the first photoresist layer33comprises a thick layer region331in the middle and thin layer regions332at two sides of the thick layer region331, and a thickness of the second photoresist layer34is uniform, and thicknesses of the thick layer region331of the first photoresist layer33and the second photoresist layer34are equal;

as shown inFIG. 6B, employing the first photoresist layer33and the second photoresist layer34for shielding to etch the polysilicon layer31to respectively obtain a first polysilicon section40in the NMOS region and a second polysilicon section90in the PMOS region;

as shown inFIG. 6C, employing a dry etching apparatus to implement ashing treatment to the first photoresist layer33and the second photoresist layer34to completely remove the thin layer regions332at the two sides on the first photoresist layer33, and meanwhile, to make the thicknesses of the thick layer331of the first photoresist layer33and the second photoresist layer34thinner; employing remained thick layer region331on the first photoresist layer33and the second photoresist layer34to be a mask to implement N type heavy doping to the two sides of the first polysilicon section40to obtain two N type heavy doping regions41.

Specifically, in the step 3, a halftone mask is utilized to realize the pattern process to the polysilicon layer31and the N type heavy doping process of the first polysilicon section40of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced.

step 4, as shown inFIG. 7, depositing a gate isolation layer51on the first polysilicon section40, the second polysilicon section90and the buffer layer30, and depositing a second metal layer on the gate isolation layer51, and patterning the second metal layer to obtain a first gate52and a second gate93correspondingly above the first polysilicon section40and the second polysilicon section90, respectively;

employing the first gate52to be a mask to implement N type light doping to the first polysilicon section40to obtain two N type light doping regions43respectively at inner sides of the two N type heavy doping regions41, and a first channel region42is formed in a region between the two N type heavy doping regions43on the first polysilicon section40.

step 5, as shown inFIG. 8, employing a mask to implement P type heavy doping to two sides of the second polysilicon section90to obtain two P type heavy doping regions91, and a second channel region92is formed in a region between the two P type heavy doping regions91on the second polysilicon section90.

step 6, as shown inFIG. 9, depositing an interlayer insulation layer53on the first gate52, the second gate93and the gate isolation layer51, and patterning the interlayer insulation layer53and the gate isolation layer51to obtain a first via55above the N type heavy doping region41and a second via95above the P type heavy doping region91, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer53.

Specifically, the RTA (Rapid Thermal Annealing) is utilized to implement dehydrogenation and activation treatments to the interlayer insulation layer53.

step 7, as shown inFIG. 10, depositing a third metal layer on the interlayer insulation layer53, and patterning the third metal layer to obtain a first source61, a first drain62, a second source96and a second drain97, and the first source61and the first drain62respectively contact with the N type heavy doping region41through the first via55, and the second source96and the second rain97respectively contact with the P type heavy doping region91through the second via95.

step 8, as shown inFIG. 11, forming a flat layer70on the first source61, the first drain62, the second source96, the second drain97and the interlayer insulation layer53, and patterning the flat layer70to obtain a third via71above the first drain62.

step 9, as shown inFIG. 12, depositing a first transparent conductive oxide layer on the flat layer70, and patterning the first transparent conductive oxide layer to obtain a common electrode80.

step 10, as shown inFIG. 13, depositing a passivation protective layer81on the common electrode80and the flat layer70, and the passivation protective layer81covers the third via71on the flat layer70, and then patterning the passivation protective layer81to obtain a fourth via85at a bottom of the third via71on the passivation protective layer81.

step 11, as shown inFIG. 14, depositing a second transparent conductive oxide layer on the passivation protective layer81, and patterning the second transparent conductive oxide layer to obtain a pixel electrode82, and the pixel electrode82contacts with the first drain62through the fourth via85.

Specifically, the substrate10is a transparent substrate, and preferably is a glass substrate.

Specifically, material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu).

Specifically, the buffer layer30, the gate isolation layer51, the interlayer insulation layer53and the passivation protective layer81can be Silicon Oxide layers, Silicon Nitride layers or composite layers superimposed with Silicon Oxide (SiOx) layers and Silicon Nitride (SiNx) layers.

Specifically, material of the flat layer70is organic photoresist material.

Specifically, material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide, Indium Germanium Zinc Oxide or other proper oxides.

Specifically, the ion doped by the P type heavy doping and the P type light doping is boron ion or gallium ion.

Specifically, the ion doped by the N type heavy doping and the N type light doping is phosphorus ion or arsenic ion.

In conclusion, the present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.