Manufacturing method of package structure

A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.

BACKGROUND

Technical Field

The present disclosure relates to a manufacturing method of package structure.

Description of Related Art

As the technology of semiconductor packaging advances, there have been various types of packages for semiconductor devices developed besides the conventional wire bonding semiconductor packaging technique. For example, one type of semiconductor devices allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate. This semiconductor device may desirably reduce the overall size and improve the electrical functionality thereof.

In order to satisfy the demands of shortening the length of conductive wires, reducing structure thickness, and responding to the trends of high-frequency and miniaturization, a method of processing a chip embedded substrate on a coreless carrier has been developed. However, since the coreless carrier lacks the support of a hard core board, it typically results in an insufficient strength and warpage of the overall structure may easily be caused.

SUMMARY

An aspect of the disclosure is to provide a package structure and a manufacturing method thereof to solve the foregoing problems.

To achieve the foregoing purpose, according to one embodiment of the disclosure, a package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The electrode pads are exposed from the sealant. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The circuit layer is located on the dielectric layer and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

In one or more embodiments of the disclosure, the chip has a chip bottom surface exposed from the sealant.

In one or more embodiments of the disclosure, the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.

In one or more embodiments of the disclosure, the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.

In one or more embodiments of the disclosure, the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.

According to another embodiment of the disclosure, a method of manufacturing package structures includes the following steps: providing a carrier, in which the carrier includes a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers; disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers; bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, in which the chip embedded substrate includes a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant; forming a circuit layer structure on each of the chip embedded substrates, in which the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; forming an insulating protective layer on each of the circuit layer structures, in which the insulating protective layer has a plurality of openings, so as to expose parts of the surface of the circuit layer structure in the openings; removing the supporting layer and the release layers to form two package substrates; and cutting each of the package substrates to obtain a plurality of package structures.

In one or more embodiments of the disclosure, each of the sealant has a sealant bottom surface, and each of the chips has a chip bottom surface. The step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material includes the following steps: grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.

In one or more embodiments of the disclosure, the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.

In one or more embodiments of the disclosure, the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.

In one or more embodiments of the disclosure, the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.

Based on the above, the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping, thereby improving not only the process yield, but also the reliability of the package structure.

DETAILED DESCRIPTION

FIG.1AtoFIG.1Gare cross-sectional views illustrating the steps in a manufacturing method of a package structure18according to one embodiment of the disclosure. As shown inFIG.1A, a carrier10is provided. Carrier10includes a supporting layer100having opposite two surfaces100A and100B, a release layer102disposed on each of the two surfaces100A and100B, and a metal layer104disposed on each of the release layers102. In some embodiments, the material of the supporting layer100may be organic polymer material such as bismaleimide triazine (BT). In some embodiments, supporting layer100may be a copper clad laminate (CCL) (not shown) with a dielectric material (such as prepreg) formed on the opposite two surfaces100A and100B. In some embodiments, the release layer102may be a release film. In other embodiments, a copper foil bonded with a release layer as provided by companies such as Mitsui, Nippon-Denk, Furukawa or Olin can be used to provide the release layer102. In some embodiments, the thickness of the metal layer104is in the range of about 1 μm to 10 μm, and the material of the metal layer104may be copper.

In some embodiments, additional metal layer may exist between each of the opposite two surfaces100A and100B of supporting layer100and each release layer102. The thickness of the additional metal layer may be in the range of about 5 μm to 40 μm, and the material of the additional metal layer may be the same as or different from that of the metal layer104, such as copper.

As shown inFIG.1B, a composite layer of a non-conductor inorganic material and an organic material106is disposed on each of the metal layers104.

For example, the material of the composite layer of the non-conductor inorganic material and the organic material106of this embodiment is a composite material composed of a ceramic material and a polymer material, for example. The ceramic material includes zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material includes epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof. The ceramic material may be ceramic layers or ceramic powders, but the ceramic material of this embodiment is not limited thereto.

In the embodiment of the ceramic powders, the polymer material can be impregnated in the ceramic powders using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material106, so as to manufacture the composite layer of the non-conductor inorganic material and the organic material106composed of a composite material formed of the ceramic powders and the polymer material. In the embodiment that the polymer material is a photosensitive resin composition including such as an epoxy-based resin and an imide-based resin, for example, the composite layer of the non-conductor inorganic material and the organic material106is disposed on the metal layer104by hot pressing or vacuum dipping and then irradiating with ultraviolet light and heating, for example.

In the embodiment of the ceramic layers, the polymer material can be impregnated in the ceramic layers using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material106, so as to manufacture the composite layer of the non-conductor inorganic material and the organic material106composed of a composite material formed of the ceramic layers and the polymer material. However, the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material106of the embodiment is not limited thereto. Other methods capable of forming the composite material from the polymer material and the ceramic material are suitable. In the embodiment of the ceramic layers, more specifically, the composite layer of the non-conductor inorganic material and the organic material106includes a composite composition of an organic matter and an inorganic matter (e.g., a composite composition of the polymer material and the ceramic layers). Based on the adhesion of the organic matter to the inorganic matter, the ceramic layers of the composite layer of the non-conductor inorganic material and the organic material106has a microscopic laminated structure in a sheet-shape, a brick-shape, or a combination thereof arrangement. The arrangement suppresses the conduction of transverse rupture forces, thereby significantly improving its hardness. Therefore, the material is strong and has flexibility, which is able to increase ceramic strength and improve ceramic brittleness, and with excellent toughness at the same time. The composite layer of the non-conductor inorganic material and the organic material106may be an imitation nacreous layer.

In some embodiments, a Young's modulus of the composite layer of the non-conductor inorganic material and the organic material106is between 20 GPa and 100 GPa, for example. Compared with a commonly used dielectric layer (with a Young's modulus not more than 10 GPa) and an encapsulating material (with a Young's modulus not more than 20 GPa), the composite layer of the non-conductor inorganic material and the organic material106of the embodiment has an excellent hardness, such that a structural strength of the package structure can be effectively enhanced.

As shown inFIG.1C, a chip embedded substrate12is bonded on each of the composite layers of the non-conductor inorganic material and the organic material106. The chip embedded substrate12includes a plurality of chips120and a sealant122. The chips120are embedded in the sealant122, and each of the chips120has a plurality of electrode pads120P. The electrode pads120P are exposed from the sealant122.

In some embodiments, an adhesive layer (not shown) may be used to bond the chip embedded substrate12on the composite layer of the non-conductor inorganic material and the organic material106. Specifically, the adhesive layer can be adhered to a substrate bottom surface12S of the chip embedded substrate12first, and then bond the chip embedded substrate12on the composite layer of the non-conductor inorganic material and the organic material106. The adhesive layer can include thermal grease with high heat dissipation or high temperature resistance, but the disclosure is not limited thereto.

As shown inFIG.1DtoFIG.1E, a circuit layer structure14is formed on each of the chip embedded substrates12. The circuit layer structure14includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads120P through the conductive blind holes.

A basic unit of the circuit layer structure14is consisted of at least one dielectric layer and at least one circuit layer. A person having ordinary skill in the art may make proper modification to the number of layers of the dielectric layer and the circuit layer according to actual needs. In this embodiment, the circuit layer structure14will be specify in the case of including two dielectric layers (first dielectric layer108and second dielectric layer208) and two circuit layers (first circuit layer110and second circuit layer210) in the following descriptions.

As shown inFIG.1D, a first dielectric layer108is formed on each of the chip embedded substrates12. The first dielectric layer108has a plurality of first conductive blind holes108H. In some embodiments, the material of the first dielectric layer108may include resin and glass fibers. The resin may be novolak resin, epoxy resin, polyimide resin, or polytetrafluoroethylene. In other embodiments, the material of the first dielectric layer108may include photo-imagable dielectric (PID). In some embodiments, the first dielectric layer108may be formed by lamination. In some embodiments, the first conductive blind holes108H can be formed by performing a laser ablation process to the first dielectric layer108, or using PID as the material of the first dielectric layer108so as to form the first conductive blind holes108H by photolithography process, but not limited thereto.

Please continue to refer toFIG.1D. A first circuit layer110is formed on each of the first dielectric layers108. The first circuit layer110extends into the first conductive blind holes108H, such that the first circuit layer110is electrically connected to the electrode pads120P through the first conductive blind holes108H. In some embodiments, the first circuit layer110may be formed by the following steps: forming a photoresist layer (not shown) such as a dry film on the first dielectric layer108; performing a photolithography process to patterning the photoresist layer, so as to expose parts of the first dielectric layer108; and performing an electroplating process and removing the photoresist layer to form the first circuit layer110. In some embodiment, the material of the first circuit layer110may be copper.

In some embodiment, a seed layer may be formed on the first dielectric layer108before forming the first circuit layer110. The seed layer may have a single layer structure or a multi-layer structure consisted of sub-layers having different materials, such as a metal layer consisted of a titanium layer and a copper layer located on the titanium layer. The method of forming the seed layer may include, but not limited to, physical methods such as titanium and copper sputtering, or chemical methods such as chemical palladium and copper plating, and copper electroplating.

As shown inFIG.1E, a second dielectric layer208is formed on each of the first dielectric layers108and each of the first circuit layers110. The second dielectric layer208has a plurality of second conductive blind holes208H. A second circuit layer210is formed on each of the second dielectric layers208. The second circuit layer210extends into the second conductive blind holes208H, such that the second circuit layer210is electrically connected to the first circuit layer110through second conductive blind holes208H.

Accordingly, the circuit layer structure14is formed on each of the chip embedded substrates12. The circuit layer structure14includes the first dielectric layer108, the first circuit layer110, the second dielectric layer208, and the second circuit layer210. The first dielectric layer108has a plurality of the first conductive blind holes108H, and the first circuit layer110is electrically connected to the electrode pads120P through the first conductive blind holes108H. The second dielectric layer208has a plurality of the second conductive blind holes208H, and the second circuit layer210is electrically connected to the first circuit layer110through the second conductive blind holes208H. That is, the circuit layer structure14includes at least one dielectric layer (first dielectric layer108and second dielectric layer208) and at least one circuit layer (first circuit layer110and second circuit layer210). Each dielectric layer has a plurality of conductive blind holes (first conductive blind holes108H and second conductive blind holes208H). Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer (first circuit layer110) is electrically connected to the electrode pads120P through the conductive blind holes (first conductive blind holes108H).

Details about the forming methods and the materials of the second dielectric layer208, the second circuit layer210, and the second conductive blind holes208H may be similar to those of the first dielectric layer108, the first circuit layer110, and the first conductive blind holes108H mentioned above respectively, and therefor they are not to be repeated here again. Moreover, a seed layer may also be formed on the second dielectric layer208before forming the second circuit layer210as mentioned above, and therefore it is not to be repeated here again.

Reference is made toFIG.1E. An insulating protective layer112is formed on each of the circuit layer structures14. The insulating protective layer112has a plurality of openings1120, so as to expose parts of the surface of the circuit layer structure14in the openings1120. Specifically, as shown inFIG.1E, parts of the surface of the outermost second circuit layer210of the circuit layer structure14are exposed in the openings1120.

In some embodiments, the material of the insulating protective layer112may be solder resist material or resin material such as epoxy resin. In other embodiments, the material of the insulating protective layer112may also be the same as above-mentioned material of the first dielectric layer108or second dielectric layer208. The insulating protective layer112may be formed by laminating, printing, or coating.

As shown onFIG.1F, the supporting layer100and the release layers102are removed to form two package substrates16. Therefore, compared to conventional one-side manufacturing method, which easily causes the warpage because of its structural asymmetry, this embodiment provides the same processes on the opposite two surfaces100A and100B of the supporting layer100respectively at the same time to form up-down symmetrical two package substrates16, so as to prevent the supporting layer100from warping phenomenon, and improve the reliability of the overall package structure.

Lastly, as shown inFIG.1G, each of the package substrates16is cut to obtain a plurality of package structures18. Thus, if each package substrate16can produce N package structures18, the two package substrates16manufactured throughFIG.1AtoFIG.1Fcan produce 2N package structures18, and thereby the process yield can be improved significantly.

Accordingly, the package structure18according to this embodiment is obtained. The package structure18includes the metal layer104, the composite layer of the non-conductor inorganic material and the organic material106, the sealant122, the chip120, the circuit layer structure14, and the insulating protective layer112. The composite layer of the non-conductor inorganic material and the organic material106is disposed on the metal layer104. The sealant122is bonded on the composite layer of the non-conductor inorganic material and the organic material106. The chip120is embedded in the sealant122. The chip120has a plurality of electrode pads120P, and the electrode pads120P are exposed from the sealant122. The circuit layer structure14is formed on the sealant122and the chip120. The circuit layer structure14includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads120P through the conductive blind holes. An insulating protective layer112is formed on the circuit layer structure14. The insulating protective layer112has a plurality of openings1120, so as to expose parts of the surface of the circuit layer structure14in the openings1120.

According to the package structure18and the manufacturing method thereof provided in the disclosure, the package substrate16is formed on the composite layer of the non-conductor inorganic material and the organic material106. That is, the composite layer of the non-conductor inorganic material and the organic material106can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure18and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material106, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure18.

Moreover, since the package structure18has the metal layer104in the bottom, the heat generated by the chip120can be dissipated by the metal layer104to achieve an effect of heat dissipation.

FIG.2AtoFIG.2Bare cross-sectional views illustrating some steps in a manufacturing method of a package structure18A according to another embodiment of the disclosure.FIG.3is a cross-sectional view illustrating the package structure18A obtained by the manufacturing method according toFIG.2AtoFIG.2B. The method of manufacturing package structure18A according to this embodiment is similar to the method of manufacturing the package structure18as mentioned above, and the difference is that in this embodiment, the step of bonding the chip embedded substrate12on each of the composite layers of the non-conductor inorganic material and the organic material106further includes the following sub-step: grinding a sealant bottom surface122S to expose a chip bottom surface120S.

Please refer toFIG.2AandFIG.1Cat the same time. The difference between this embodiment and the step shown inFIG.1Cis that a sealant bottom surface122S is ground to expose a chip bottom surface120S, so as to form a ground chip embedded substrate12A before bonding the chip embedded substrate12on each of the composite layers of the non-conductor inorganic material and the organic material106. In some embodiment, the method of grinding the sealant bottom surface122S may be chemical-mechanical polishing (CMP).

As shown inFIG.2B, the ground chip embedded substrate12A is bonded on each of the composite layers of the non-conductor inorganic material and the organic material106. That is, when the ground chip embedded substrate12A is bonded on the composite layer of the non-conductor inorganic material and the organic material106, the chip bottom surface120S is exposed from the sealant122.

In some embodiments, an adhesive layer (not shown) may be used herein to bond the ground chip embedded substrate12A on each of the composite layers of the non-conductor inorganic material and the organic material106as above-mentioned embodiment, and therefore it is not to be repeated here again.

Then, continue the steps inFIG.1DtoFIG.1G, and the package structure18A as shown inFIG.3is accordingly obtained. In this embodiment, since the chip bottom surface120S is exposed from the sealant122, the heat generated by the chip120can be dissipated by the metal layer104more effectively thereby to further improve the effect of heat dissipation. Moreover, the thickness of the package structure18A is also reduced, which is beneficial to the miniaturization of products.

According to the foregoing recitations of the embodiments of the disclosure, it can be seen that the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure.